[ARM/tegra] add NvRm, ODM services, ODM kit for harmony & whistler

add power rail support to GPIO driver

Change-Id: I45d4c1110a635047d68fb14f3e72a28f99acbe1b

372 files changed, 273453 insertions, 26 deletions

diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index 4e7bab798040..505b4885d5d7 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -57,10 +57,20 @@ config MACH_TEGRA_GENERIC
 
 config TEGRA_NVOS
 	bool "Include Tegra NvOS interfaces"
+	depends on MACH_TEGRA_GENERIC
 	default y
 	help
 	  Adds the Tegra NvOS driver layer and associated user-space
 	  interfaces
+
+config TEGRA_NVRM
+	bool "Include Tegra NvRM interfaces"
+	depends on TEGRA_NVOS
+	default n
+	help
+	  Adds the Tegra NVRM driver layer and associated user-space
+	  interfaces.
+
 config TEGRA_IOVMM_GART
 	bool "Enable I/O virtual memory manager for GART"
 	depends on ARCH_TEGRA_2x_SOC
@@ -81,4 +91,8 @@ config TEGRA_SYSTEM_DMA
 config TEGRA_IOVMM
 	bool
 
+if TEGRA_NVRM
+source "arch/arm/mach-tegra/odm_kit/Kconfig"
+endif
+
 endif
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index 4c327c0f03f1..0bc04b54cfc1 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -22,4 +22,9 @@ ccflags-$(CONFIG_TEGRA_NVOS)		+= -DNV_OAL=0
 ccflags-$(CONFIG_TEGRA_NVOS)		+= -DNV_IS_AVP=0
 ccflags-$(CONFIG_TEGRA_NVOS)		+= -DNV_USE_FUSE_CLOCK_ENABLE=0
 obj-$(CONFIG_TEGRA_NVOS)		+= nvos_user.o
-obj-$(CONFIG_TEGRA_NVOS)		+= nvos/
\ No newline at end of file
+obj-$(CONFIG_TEGRA_NVOS)		+= nvos/
+
+obj-$(CONFIG_TEGRA_NVRM)		+= nvrm/
+obj-$(CONFIG_TEGRA_NVRM)		+= nvodm/
+obj-$(CONFIG_TEGRA_NVRM)		+= odm_kit/
+obj-$(CONFIG_TEGRA_NVRM)		+= nvrm_user.o
diff --git a/arch/arm/mach-tegra/gpio.c b/arch/arm/mach-tegra/gpio.c
index afc926624deb..2f06f5849177 100644
--- a/arch/arm/mach-tegra/gpio.c
+++ b/arch/arm/mach-tegra/gpio.c
@@ -20,6 +20,7 @@
 #include <linux/init.h>
 #include <linux/irq.h>
 #include <linux/interrupt.h>
+#include <linux/delay.h>
 
 #include <linux/io.h>
 #include <linux/gpio.h>
@@ -27,6 +28,11 @@
 #include <mach/iomap.h>
 #include <mach/pinmux.h>
 
+#include <mach/nvrm_linux.h>
+#include "nvcommon.h"
+#include "nvrm_pmu.h"
+#include "nvodm_query_discovery.h"
+
 #define GPIO_BANK(x)		((x) >> 5)
 #define GPIO_PORT(x)		(((x) >> 3) & 0x3)
 #define GPIO_BIT(x)		((x) & 0x7)
@@ -59,6 +65,7 @@
 #define GPIO_INT_LVL_LEVEL_LOW		0x000000
 
 extern int gpio_get_pinmux_group(int gpio_nr);
+int tegra_gpio_io_power_config(int gpio_nr, unsigned int enable);
 
 struct tegra_gpio_bank {
 	int bank;
@@ -99,16 +106,6 @@ static void tegra_gpio_mask_write(u32 reg, int gpio, int value)
 	__raw_writel(val, reg);
 }
 
-void tegra_gpio_enable(int gpio)
-{
-	tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 1);
-}
-
-void tegra_gpio_disable(int gpio)
-{
-	tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 0);
-}
-
 static void tegra_set_gpio_tristate(int gpio_nr, tegra_tristate_t ts)
 {
 	tegra_pingroup_t pg;
@@ -123,29 +120,29 @@ static void tegra_set_gpio_tristate(int gpio_nr, tegra_tristate_t ts)
 	}
 }
 
-static int tegra_gpio_request(struct gpio_chip *chip, unsigned offset)
+void tegra_gpio_enable(int gpio)
 {
-	int port;
-	int pin;
+	WARN_ON(tegra_gpio_io_power_config(gpio, 1) != 0);
+	tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 1);
+	tegra_set_gpio_tristate(gpio, TEGRA_TRI_NORMAL);
+}
 
-	port = GPIO_BANK(offset) * 4 + GPIO_PORT(offset);
-	pin = GPIO_BIT(offset);
+void tegra_gpio_disable(int gpio)
+{
+	tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 0);
+	tegra_set_gpio_tristate(gpio, TEGRA_TRI_TRISTATE);
+	WARN_ON(tegra_gpio_io_power_config(gpio, 0) != 0);
+}
 
-	tegra_gpio_mask_write(GPIO_MSK_CNF(offset), offset, 1);
-	tegra_set_gpio_tristate(offset, TEGRA_TRI_NORMAL);
+static int tegra_gpio_request(struct gpio_chip *chip, unsigned offset)
+{
+	tegra_gpio_enable(offset);
 	return 0;
 }
 
 static void tegra_gpio_free(struct gpio_chip *chip, unsigned offset)
 {
-	int port;
-	int pin;
-
-	port = GPIO_BANK(offset) * 4 + GPIO_PORT(offset);
-	pin = GPIO_BIT(offset);
-
-	tegra_gpio_mask_write(GPIO_MSK_CNF(offset), offset, 0);
-	tegra_set_gpio_tristate(offset, TEGRA_TRI_TRISTATE);
+	tegra_gpio_disable(offset);
 }
 
 static void tegra_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
@@ -385,6 +382,47 @@ static struct irq_chip tegra_gpio_irq_chip = {
  */
 static struct lock_class_key gpio_lock_class;
 
+struct gpio_power_rail_info {
+	NvU64 guid;
+	NvU32 address;
+	NvU32 mv;
+};
+
+static struct gpio_power_rail_info gpio_power_rail_table[] = {
+	[TEGRA_VDDIO_BB]    =  {.guid = NV_VDD_BB_ODM_ID,},
+	[TEGRA_VDDIO_LCD]   =  {.guid = NV_VDD_LCD_ODM_ID,},
+	[TEGRA_VDDIO_VI]    =  {.guid = NV_VDD_VI_ODM_ID,},
+	[TEGRA_VDDIO_UART]  =  {.guid = NV_VDD_UART_ODM_ID,},
+	[TEGRA_VDDIO_DDR]   =  {.guid = NV_VDD_DDR_ODM_ID,},
+	[TEGRA_VDDIO_NAND]  =  {.guid = NV_VDD_NAND_ODM_ID,},
+	[TEGRA_VDDIO_SYS]   =  {.guid = NV_VDD_SYS_ODM_ID,},
+	[TEGRA_VDDIO_AUDIO] =  {.guid = NV_VDD_AUD_ODM_ID,},
+	[TEGRA_VDDIO_SD]    =  {.guid = NV_VDD_SDIO_ODM_ID,},
+};
+
+static void gpio_rail_init(void)
+{
+	unsigned int i;
+
+	if (!s_hRmGlobal)
+		return;
+
+	for (i = 0; i < NV_ARRAY_SIZE(gpio_power_rail_table); i++) {
+		struct gpio_power_rail_info *rail = &gpio_power_rail_table[i];
+		const NvOdmPeripheralConnectivity *conn;
+		NvRmPmuVddRailCapabilities caps;
+
+		conn = NvOdmPeripheralGetGuid(rail->guid);
+		if (!conn || !conn->NumAddress)
+			continue;
+
+		rail->address = conn->AddressList[0].Address;
+
+		NvRmPmuGetCapabilities(NULL, rail->address, &caps);
+		rail->mv = (caps.RmProtected) ? 0 : caps.requestMilliVolts;
+	}
+}
+
 static int __init tegra_gpio_init(void)
 {
 	struct tegra_gpio_bank *bank;
@@ -420,6 +458,7 @@ static int __init tegra_gpio_init(void)
 			spin_lock_init(&bank->lvl_lock[j]);
 	}
 
+	gpio_rail_init();
 	return 0;
 }
 
@@ -472,3 +511,33 @@ static int __init tegra_gpio_debuginit(void)
 }
 late_initcall(tegra_gpio_debuginit);
 #endif
+
+int tegra_gpio_io_power_config(int gpio_nr, unsigned int enable)
+{
+	struct gpio_power_rail_info *rail;
+	tegra_pingroup_t pg;
+	NvU32 settle;
+	int vddio_id;
+
+	pg = gpio_get_pinmux_group(gpio_nr);
+	if (pg < 0)
+		return pg;
+	vddio_id = tegra_pinmux_get_vddio(pg);
+	if(vddio_id < 0)
+		return vddio_id;
+
+	if (unlikely(!s_hRmGlobal))
+		return 0;
+
+	rail = &gpio_power_rail_table[vddio_id];
+	if (!rail->address || !rail->mv)
+		return 0;
+
+	NvRmPmuSetVoltage(s_hRmGlobal, rail->address,
+		(enable) ? rail->mv : ODM_VOLTAGE_OFF, &settle);
+
+	if (settle)
+		udelay(settle);
+
+	return 0;
+}
diff --git a/arch/arm/mach-tegra/include/ap15/arahb_arbc.h b/arch/arm/mach-tegra/include/ap15/arahb_arbc.h
new file mode 100644
index 000000000000..42229b51247b
--- /dev/null
+++ b/arch/arm/mach-tegra/include/ap15/arahb_arbc.h
@@ -0,0 +1,2417 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+//
+// DO NOT EDIT - generated by simspec!
+//
+
+#ifndef ___ARAHB_ARBC_H_INC_
+#define ___ARAHB_ARBC_H_INC_
+
+// Register AHB_ARBITRATION_DISABLE_0  
+#define AHB_ARBITRATION_DISABLE_0                       _MK_ADDR_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_WORD_COUNT                    0x1
+#define AHB_ARBITRATION_DISABLE_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_RESET_MASK                    _MK_MASK_CONST(0x800937f7)
+#define AHB_ARBITRATION_DISABLE_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_READ_MASK                     _MK_MASK_CONST(0x800937f7)
+#define AHB_ARBITRATION_DISABLE_0_WRITE_MASK                    _MK_MASK_CONST(0x800937f7)
+//  1 = disable bus parking.
+#define AHB_ARBITRATION_DISABLE_0_DIS_BUS_PARK_SHIFT                    _MK_SHIFT_CONST(31)
+#define AHB_ARBITRATION_DISABLE_0_DIS_BUS_PARK_FIELD                    (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_DISABLE_0_DIS_BUS_PARK_SHIFT)
+#define AHB_ARBITRATION_DISABLE_0_DIS_BUS_PARK_RANGE                    31:31
+#define AHB_ARBITRATION_DISABLE_0_DIS_BUS_PARK_WOFFSET                  0x0
+#define AHB_ARBITRATION_DISABLE_0_DIS_BUS_PARK_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_DIS_BUS_PARK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_DISABLE_0_DIS_BUS_PARK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_DIS_BUS_PARK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_DIS_BUS_PARK_ENABLE                   _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_DISABLE_0_DIS_BUS_PARK_DISABLE                  _MK_ENUM_CONST(1)
+
+//  1 = disable SDIO2 from arbitration.
+#define AHB_ARBITRATION_DISABLE_0_SDIO2_SHIFT                   _MK_SHIFT_CONST(19)
+#define AHB_ARBITRATION_DISABLE_0_SDIO2_FIELD                   (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_DISABLE_0_SDIO2_SHIFT)
+#define AHB_ARBITRATION_DISABLE_0_SDIO2_RANGE                   19:19
+#define AHB_ARBITRATION_DISABLE_0_SDIO2_WOFFSET                 0x0
+#define AHB_ARBITRATION_DISABLE_0_SDIO2_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_SDIO2_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_DISABLE_0_SDIO2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_SDIO2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_SDIO2_ENABLE                  _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_DISABLE_0_SDIO2_DISABLE                 _MK_ENUM_CONST(1)
+
+//  1 = disable BSEA from arbitration.
+#define AHB_ARBITRATION_DISABLE_0_BSEA_SHIFT                    _MK_SHIFT_CONST(16)
+#define AHB_ARBITRATION_DISABLE_0_BSEA_FIELD                    (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_DISABLE_0_BSEA_SHIFT)
+#define AHB_ARBITRATION_DISABLE_0_BSEA_RANGE                    16:16
+#define AHB_ARBITRATION_DISABLE_0_BSEA_WOFFSET                  0x0
+#define AHB_ARBITRATION_DISABLE_0_BSEA_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_BSEA_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_DISABLE_0_BSEA_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_BSEA_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_BSEA_ENABLE                   _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_DISABLE_0_BSEA_DISABLE                  _MK_ENUM_CONST(1)
+
+//  1 = disable BSEV from arbitration.
+#define AHB_ARBITRATION_DISABLE_0_BSEV_SHIFT                    _MK_SHIFT_CONST(13)
+#define AHB_ARBITRATION_DISABLE_0_BSEV_FIELD                    (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_DISABLE_0_BSEV_SHIFT)
+#define AHB_ARBITRATION_DISABLE_0_BSEV_RANGE                    13:13
+#define AHB_ARBITRATION_DISABLE_0_BSEV_WOFFSET                  0x0
+#define AHB_ARBITRATION_DISABLE_0_BSEV_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_BSEV_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_DISABLE_0_BSEV_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_BSEV_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_BSEV_ENABLE                   _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_DISABLE_0_BSEV_DISABLE                  _MK_ENUM_CONST(1)
+
+//  1 = disable HSMMC1 from arbitration.
+#define AHB_ARBITRATION_DISABLE_0_HSMMC1_SHIFT                  _MK_SHIFT_CONST(12)
+#define AHB_ARBITRATION_DISABLE_0_HSMMC1_FIELD                  (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_DISABLE_0_HSMMC1_SHIFT)
+#define AHB_ARBITRATION_DISABLE_0_HSMMC1_RANGE                  12:12
+#define AHB_ARBITRATION_DISABLE_0_HSMMC1_WOFFSET                        0x0
+#define AHB_ARBITRATION_DISABLE_0_HSMMC1_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_HSMMC1_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_DISABLE_0_HSMMC1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_HSMMC1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_HSMMC1_ENABLE                 _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_DISABLE_0_HSMMC1_DISABLE                        _MK_ENUM_CONST(1)
+
+//  1 = disable NAND from arbitration.
+#define AHB_ARBITRATION_DISABLE_0_NAND_SHIFT                    _MK_SHIFT_CONST(10)
+#define AHB_ARBITRATION_DISABLE_0_NAND_FIELD                    (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_DISABLE_0_NAND_SHIFT)
+#define AHB_ARBITRATION_DISABLE_0_NAND_RANGE                    10:10
+#define AHB_ARBITRATION_DISABLE_0_NAND_WOFFSET                  0x0
+#define AHB_ARBITRATION_DISABLE_0_NAND_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_NAND_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_DISABLE_0_NAND_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_NAND_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_NAND_ENABLE                   _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_DISABLE_0_NAND_DISABLE                  _MK_ENUM_CONST(1)
+
+//  1 = disable SDIO1 from arbitration.
+#define AHB_ARBITRATION_DISABLE_0_SDIO1_SHIFT                   _MK_SHIFT_CONST(9)
+#define AHB_ARBITRATION_DISABLE_0_SDIO1_FIELD                   (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_DISABLE_0_SDIO1_SHIFT)
+#define AHB_ARBITRATION_DISABLE_0_SDIO1_RANGE                   9:9
+#define AHB_ARBITRATION_DISABLE_0_SDIO1_WOFFSET                 0x0
+#define AHB_ARBITRATION_DISABLE_0_SDIO1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_SDIO1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_DISABLE_0_SDIO1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_SDIO1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_SDIO1_ENABLE                  _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_DISABLE_0_SDIO1_DISABLE                 _MK_ENUM_CONST(1)
+
+//  1 = disable XIO from arbitration.
+#define AHB_ARBITRATION_DISABLE_0_XIO_SHIFT                     _MK_SHIFT_CONST(8)
+#define AHB_ARBITRATION_DISABLE_0_XIO_FIELD                     (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_DISABLE_0_XIO_SHIFT)
+#define AHB_ARBITRATION_DISABLE_0_XIO_RANGE                     8:8
+#define AHB_ARBITRATION_DISABLE_0_XIO_WOFFSET                   0x0
+#define AHB_ARBITRATION_DISABLE_0_XIO_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_XIO_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_DISABLE_0_XIO_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_XIO_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_XIO_ENABLE                    _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_DISABLE_0_XIO_DISABLE                   _MK_ENUM_CONST(1)
+
+//  1 = disable APB-DMA from arbitration.
+#define AHB_ARBITRATION_DISABLE_0_APBDMA_SHIFT                  _MK_SHIFT_CONST(7)
+#define AHB_ARBITRATION_DISABLE_0_APBDMA_FIELD                  (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_DISABLE_0_APBDMA_SHIFT)
+#define AHB_ARBITRATION_DISABLE_0_APBDMA_RANGE                  7:7
+#define AHB_ARBITRATION_DISABLE_0_APBDMA_WOFFSET                        0x0
+#define AHB_ARBITRATION_DISABLE_0_APBDMA_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_APBDMA_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_DISABLE_0_APBDMA_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_APBDMA_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_APBDMA_ENABLE                 _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_DISABLE_0_APBDMA_DISABLE                        _MK_ENUM_CONST(1)
+
+//  1 = disable USB from arbitration.
+#define AHB_ARBITRATION_DISABLE_0_USB_SHIFT                     _MK_SHIFT_CONST(6)
+#define AHB_ARBITRATION_DISABLE_0_USB_FIELD                     (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_DISABLE_0_USB_SHIFT)
+#define AHB_ARBITRATION_DISABLE_0_USB_RANGE                     6:6
+#define AHB_ARBITRATION_DISABLE_0_USB_WOFFSET                   0x0
+#define AHB_ARBITRATION_DISABLE_0_USB_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_USB_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_DISABLE_0_USB_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_USB_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_USB_ENABLE                    _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_DISABLE_0_USB_DISABLE                   _MK_ENUM_CONST(1)
+
+//  1 = disable AHB-DMA from arbitration.
+#define AHB_ARBITRATION_DISABLE_0_AHBDMA_SHIFT                  _MK_SHIFT_CONST(5)
+#define AHB_ARBITRATION_DISABLE_0_AHBDMA_FIELD                  (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_DISABLE_0_AHBDMA_SHIFT)
+#define AHB_ARBITRATION_DISABLE_0_AHBDMA_RANGE                  5:5
+#define AHB_ARBITRATION_DISABLE_0_AHBDMA_WOFFSET                        0x0
+#define AHB_ARBITRATION_DISABLE_0_AHBDMA_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_AHBDMA_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_DISABLE_0_AHBDMA_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_AHBDMA_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_AHBDMA_ENABLE                 _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_DISABLE_0_AHBDMA_DISABLE                        _MK_ENUM_CONST(1)
+
+//  1 = disable EIDE from arbitration.
+#define AHB_ARBITRATION_DISABLE_0_EIDE_SHIFT                    _MK_SHIFT_CONST(4)
+#define AHB_ARBITRATION_DISABLE_0_EIDE_FIELD                    (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_DISABLE_0_EIDE_SHIFT)
+#define AHB_ARBITRATION_DISABLE_0_EIDE_RANGE                    4:4
+#define AHB_ARBITRATION_DISABLE_0_EIDE_WOFFSET                  0x0
+#define AHB_ARBITRATION_DISABLE_0_EIDE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_EIDE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_DISABLE_0_EIDE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_EIDE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_EIDE_ENABLE                   _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_DISABLE_0_EIDE_DISABLE                  _MK_ENUM_CONST(1)
+
+//  1 = disable VCP from arbitration.
+#define AHB_ARBITRATION_DISABLE_0_VCP_SHIFT                     _MK_SHIFT_CONST(2)
+#define AHB_ARBITRATION_DISABLE_0_VCP_FIELD                     (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_DISABLE_0_VCP_SHIFT)
+#define AHB_ARBITRATION_DISABLE_0_VCP_RANGE                     2:2
+#define AHB_ARBITRATION_DISABLE_0_VCP_WOFFSET                   0x0
+#define AHB_ARBITRATION_DISABLE_0_VCP_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_VCP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_DISABLE_0_VCP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_VCP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_VCP_ENABLE                    _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_DISABLE_0_VCP_DISABLE                   _MK_ENUM_CONST(1)
+
+//  1 = disable COP from arbitration.
+#define AHB_ARBITRATION_DISABLE_0_COP_SHIFT                     _MK_SHIFT_CONST(1)
+#define AHB_ARBITRATION_DISABLE_0_COP_FIELD                     (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_DISABLE_0_COP_SHIFT)
+#define AHB_ARBITRATION_DISABLE_0_COP_RANGE                     1:1
+#define AHB_ARBITRATION_DISABLE_0_COP_WOFFSET                   0x0
+#define AHB_ARBITRATION_DISABLE_0_COP_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_COP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_DISABLE_0_COP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_COP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_COP_ENABLE                    _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_DISABLE_0_COP_DISABLE                   _MK_ENUM_CONST(1)
+
+//  1 = disable CPU from arbitration.
+#define AHB_ARBITRATION_DISABLE_0_CPU_SHIFT                     _MK_SHIFT_CONST(0)
+#define AHB_ARBITRATION_DISABLE_0_CPU_FIELD                     (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_DISABLE_0_CPU_SHIFT)
+#define AHB_ARBITRATION_DISABLE_0_CPU_RANGE                     0:0
+#define AHB_ARBITRATION_DISABLE_0_CPU_WOFFSET                   0x0
+#define AHB_ARBITRATION_DISABLE_0_CPU_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_CPU_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_DISABLE_0_CPU_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_CPU_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_CPU_ENABLE                    _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_DISABLE_0_CPU_DISABLE                   _MK_ENUM_CONST(1)
+
+
+// Register AHB_ARBITRATION_PRIORITY_CTRL_0  ///////////////////////////////////////////////////////////////////////////////////////////////////////////////
+//
+//  The AHB arbiter implements a 2-level priority scheme.  In the 1st level, arbitration is determined between
+//  the high and low priority group according to the priority weight; the higher the weight, the higher the
+//  winning rate of the high priority group.  In the 2nd level, within each of the high/low priority group, 
+//  arbitration is determined in a round-robin fashion.
+//
+///////////////////////////////////////////////////////////////////////////////////////////////////////////////
+#define AHB_ARBITRATION_PRIORITY_CTRL_0                 _MK_ADDR_CONST(0x4)
+#define AHB_ARBITRATION_PRIORITY_CTRL_0_WORD_COUNT                      0x1
+#define AHB_ARBITRATION_PRIORITY_CTRL_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_PRIORITY_CTRL_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define AHB_ARBITRATION_PRIORITY_CTRL_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_PRIORITY_CTRL_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_PRIORITY_CTRL_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define AHB_ARBITRATION_PRIORITY_CTRL_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// AHB priority weight count. This 3-bit field is  use to control 
+// the amount of attention (weight) giving to the high priority 
+// group before switching to the low priority group.
+#define AHB_ARBITRATION_PRIORITY_CTRL_0_AHB_PRIORITY_WEIGHT_SHIFT                       _MK_SHIFT_CONST(29)
+#define AHB_ARBITRATION_PRIORITY_CTRL_0_AHB_PRIORITY_WEIGHT_FIELD                       (_MK_MASK_CONST(0x7) << AHB_ARBITRATION_PRIORITY_CTRL_0_AHB_PRIORITY_WEIGHT_SHIFT)
+#define AHB_ARBITRATION_PRIORITY_CTRL_0_AHB_PRIORITY_WEIGHT_RANGE                       31:29
+#define AHB_ARBITRATION_PRIORITY_CTRL_0_AHB_PRIORITY_WEIGHT_WOFFSET                     0x0
+#define AHB_ARBITRATION_PRIORITY_CTRL_0_AHB_PRIORITY_WEIGHT_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_PRIORITY_CTRL_0_AHB_PRIORITY_WEIGHT_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
+#define AHB_ARBITRATION_PRIORITY_CTRL_0_AHB_PRIORITY_WEIGHT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_PRIORITY_CTRL_0_AHB_PRIORITY_WEIGHT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+//  0 = low priority
+#define AHB_ARBITRATION_PRIORITY_CTRL_0_AHB_PRIORITY_SELECT_SHIFT                       _MK_SHIFT_CONST(0)
+#define AHB_ARBITRATION_PRIORITY_CTRL_0_AHB_PRIORITY_SELECT_FIELD                       (_MK_MASK_CONST(0x1fffffff) << AHB_ARBITRATION_PRIORITY_CTRL_0_AHB_PRIORITY_SELECT_SHIFT)
+#define AHB_ARBITRATION_PRIORITY_CTRL_0_AHB_PRIORITY_SELECT_RANGE                       28:0
+#define AHB_ARBITRATION_PRIORITY_CTRL_0_AHB_PRIORITY_SELECT_WOFFSET                     0x0
+#define AHB_ARBITRATION_PRIORITY_CTRL_0_AHB_PRIORITY_SELECT_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_PRIORITY_CTRL_0_AHB_PRIORITY_SELECT_DEFAULT_MASK                        _MK_MASK_CONST(0x1fffffff)
+#define AHB_ARBITRATION_PRIORITY_CTRL_0_AHB_PRIORITY_SELECT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_PRIORITY_CTRL_0_AHB_PRIORITY_SELECT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register AHB_ARBITRATION_USR_PROTECT_0  
+#define AHB_ARBITRATION_USR_PROTECT_0                   _MK_ADDR_CONST(0x8)
+#define AHB_ARBITRATION_USR_PROTECT_0_WORD_COUNT                        0x1
+#define AHB_ARBITRATION_USR_PROTECT_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_USR_PROTECT_0_RESET_MASK                        _MK_MASK_CONST(0x1ff)
+#define AHB_ARBITRATION_USR_PROTECT_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_USR_PROTECT_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_USR_PROTECT_0_READ_MASK                         _MK_MASK_CONST(0x1ff)
+#define AHB_ARBITRATION_USR_PROTECT_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+// Abort on USR mode access to Cache memory space
+#define AHB_ARBITRATION_USR_PROTECT_0_CACHE_SHIFT                       _MK_SHIFT_CONST(8)
+#define AHB_ARBITRATION_USR_PROTECT_0_CACHE_FIELD                       (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_USR_PROTECT_0_CACHE_SHIFT)
+#define AHB_ARBITRATION_USR_PROTECT_0_CACHE_RANGE                       8:8
+#define AHB_ARBITRATION_USR_PROTECT_0_CACHE_WOFFSET                     0x0
+#define AHB_ARBITRATION_USR_PROTECT_0_CACHE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_USR_PROTECT_0_CACHE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_USR_PROTECT_0_CACHE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_USR_PROTECT_0_CACHE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_USR_PROTECT_0_CACHE_ABT_DIS                     _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_USR_PROTECT_0_CACHE_ABT_EN                      _MK_ENUM_CONST(1)
+
+// Abort on USR mode access to internal ROM memory  space
+#define AHB_ARBITRATION_USR_PROTECT_0_ROM_SHIFT                 _MK_SHIFT_CONST(7)
+#define AHB_ARBITRATION_USR_PROTECT_0_ROM_FIELD                 (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_USR_PROTECT_0_ROM_SHIFT)
+#define AHB_ARBITRATION_USR_PROTECT_0_ROM_RANGE                 7:7
+#define AHB_ARBITRATION_USR_PROTECT_0_ROM_WOFFSET                       0x0
+#define AHB_ARBITRATION_USR_PROTECT_0_ROM_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_USR_PROTECT_0_ROM_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_USR_PROTECT_0_ROM_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_USR_PROTECT_0_ROM_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_USR_PROTECT_0_ROM_ABT_DIS                       _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_USR_PROTECT_0_ROM_ABT_EN                        _MK_ENUM_CONST(1)
+
+// Abort on USR mode access to APB memory space
+#define AHB_ARBITRATION_USR_PROTECT_0_APB_SHIFT                 _MK_SHIFT_CONST(6)
+#define AHB_ARBITRATION_USR_PROTECT_0_APB_FIELD                 (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_USR_PROTECT_0_APB_SHIFT)
+#define AHB_ARBITRATION_USR_PROTECT_0_APB_RANGE                 6:6
+#define AHB_ARBITRATION_USR_PROTECT_0_APB_WOFFSET                       0x0
+#define AHB_ARBITRATION_USR_PROTECT_0_APB_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_USR_PROTECT_0_APB_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_USR_PROTECT_0_APB_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_USR_PROTECT_0_APB_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_USR_PROTECT_0_APB_ABT_DIS                       _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_USR_PROTECT_0_APB_ABT_EN                        _MK_ENUM_CONST(1)
+
+// Abort on USR mode access to AHB memory space
+#define AHB_ARBITRATION_USR_PROTECT_0_AHB_SHIFT                 _MK_SHIFT_CONST(5)
+#define AHB_ARBITRATION_USR_PROTECT_0_AHB_FIELD                 (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_USR_PROTECT_0_AHB_SHIFT)
+#define AHB_ARBITRATION_USR_PROTECT_0_AHB_RANGE                 5:5
+#define AHB_ARBITRATION_USR_PROTECT_0_AHB_WOFFSET                       0x0
+#define AHB_ARBITRATION_USR_PROTECT_0_AHB_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_USR_PROTECT_0_AHB_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_USR_PROTECT_0_AHB_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_USR_PROTECT_0_AHB_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_USR_PROTECT_0_AHB_ABT_DIS                       _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_USR_PROTECT_0_AHB_ABT_EN                        _MK_ENUM_CONST(1)
+
+// Abort on USR mode access to PPSB memory space
+#define AHB_ARBITRATION_USR_PROTECT_0_PPSB_SHIFT                        _MK_SHIFT_CONST(4)
+#define AHB_ARBITRATION_USR_PROTECT_0_PPSB_FIELD                        (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_USR_PROTECT_0_PPSB_SHIFT)
+#define AHB_ARBITRATION_USR_PROTECT_0_PPSB_RANGE                        4:4
+#define AHB_ARBITRATION_USR_PROTECT_0_PPSB_WOFFSET                      0x0
+#define AHB_ARBITRATION_USR_PROTECT_0_PPSB_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_USR_PROTECT_0_PPSB_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_USR_PROTECT_0_PPSB_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_USR_PROTECT_0_PPSB_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_USR_PROTECT_0_PPSB_ABT_DIS                      _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_USR_PROTECT_0_PPSB_ABT_EN                       _MK_ENUM_CONST(1)
+
+// Abort on USR mode access to iRAMd memory space
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMD_SHIFT                       _MK_SHIFT_CONST(3)
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMD_FIELD                       (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_USR_PROTECT_0_IRAMD_SHIFT)
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMD_RANGE                       3:3
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMD_WOFFSET                     0x0
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMD_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMD_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMD_ABT_DIS                     _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMD_ABT_EN                      _MK_ENUM_CONST(1)
+
+// Abort on USR mode access to iRAMc memory space
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMC_SHIFT                       _MK_SHIFT_CONST(2)
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMC_FIELD                       (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_USR_PROTECT_0_IRAMC_SHIFT)
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMC_RANGE                       2:2
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMC_WOFFSET                     0x0
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMC_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMC_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMC_ABT_DIS                     _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMC_ABT_EN                      _MK_ENUM_CONST(1)
+
+// Abort on USR mode access to iRAMb memory space
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMB_SHIFT                       _MK_SHIFT_CONST(1)
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMB_FIELD                       (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_USR_PROTECT_0_IRAMB_SHIFT)
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMB_RANGE                       1:1
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMB_WOFFSET                     0x0
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMB_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMB_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMB_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMB_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMB_ABT_DIS                     _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMB_ABT_EN                      _MK_ENUM_CONST(1)
+
+// Abort on USR mode access to iRAMa memory space
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMA_SHIFT                       _MK_SHIFT_CONST(0)
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMA_FIELD                       (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_USR_PROTECT_0_IRAMA_SHIFT)
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMA_RANGE                       0:0
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMA_WOFFSET                     0x0
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMA_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMA_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMA_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMA_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMA_ABT_DIS                     _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMA_ABT_EN                      _MK_ENUM_CONST(1)
+
+
+// Register AHB_GIZMO_AHB_MEM_0  
+#define AHB_GIZMO_AHB_MEM_0                     _MK_ADDR_CONST(0xc)
+#define AHB_GIZMO_AHB_MEM_0_WORD_COUNT                  0x1
+#define AHB_GIZMO_AHB_MEM_0_RESET_VAL                   _MK_MASK_CONST(0x200c1)
+#define AHB_GIZMO_AHB_MEM_0_RESET_MASK                  _MK_MASK_CONST(0xff0700c7)
+#define AHB_GIZMO_AHB_MEM_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_MEM_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_MEM_0_READ_MASK                   _MK_MASK_CONST(0xff0700c7)
+#define AHB_GIZMO_AHB_MEM_0_WRITE_MASK                  _MK_MASK_CONST(0xff0700c7)
+// AHB master request negate count. This is an 8-bit counter use to indicate 
+// the minimum number of clk count between requests from  this AHB master.
+#define AHB_GIZMO_AHB_MEM_0_REQ_NEG_CNT_SHIFT                   _MK_SHIFT_CONST(24)
+#define AHB_GIZMO_AHB_MEM_0_REQ_NEG_CNT_FIELD                   (_MK_MASK_CONST(0xff) << AHB_GIZMO_AHB_MEM_0_REQ_NEG_CNT_SHIFT)
+#define AHB_GIZMO_AHB_MEM_0_REQ_NEG_CNT_RANGE                   31:24
+#define AHB_GIZMO_AHB_MEM_0_REQ_NEG_CNT_WOFFSET                 0x0
+#define AHB_GIZMO_AHB_MEM_0_REQ_NEG_CNT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_MEM_0_REQ_NEG_CNT_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define AHB_GIZMO_AHB_MEM_0_REQ_NEG_CNT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_MEM_0_REQ_NEG_CNT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// AHB master gizmo (AHB-DMA) - Start AHB write request immediately 
+// 1 = start the AHB write request immediately as soon as the device 
+// has put one write data in hte AHB gizmos queue. 0 = start the AHB 
+// write request only when all the  write data has transferred from 
+// the device to the AHB gizmos queue.
+#define AHB_GIZMO_AHB_MEM_0_IMMEDIATE_SHIFT                     _MK_SHIFT_CONST(18)
+#define AHB_GIZMO_AHB_MEM_0_IMMEDIATE_FIELD                     (_MK_MASK_CONST(0x1) << AHB_GIZMO_AHB_MEM_0_IMMEDIATE_SHIFT)
+#define AHB_GIZMO_AHB_MEM_0_IMMEDIATE_RANGE                     18:18
+#define AHB_GIZMO_AHB_MEM_0_IMMEDIATE_WOFFSET                   0x0
+#define AHB_GIZMO_AHB_MEM_0_IMMEDIATE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_MEM_0_IMMEDIATE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_AHB_MEM_0_IMMEDIATE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_MEM_0_IMMEDIATE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_MEM_0_IMMEDIATE_DISABLE                   _MK_ENUM_CONST(0)
+#define AHB_GIZMO_AHB_MEM_0_IMMEDIATE_ENABLE                    _MK_ENUM_CONST(1)
+
+// AHB master gizmo (AHB-DMA) - Maximum 
+// allowed AHB burst size. 
+// 00 = single transfer. 
+// 01 = burst-of-4. 
+// 10 = burst-of-8 
+// 11 = burst-of-16.
+#define AHB_GIZMO_AHB_MEM_0_MAX_AHB_BURSTSIZE_SHIFT                     _MK_SHIFT_CONST(16)
+#define AHB_GIZMO_AHB_MEM_0_MAX_AHB_BURSTSIZE_FIELD                     (_MK_MASK_CONST(0x3) << AHB_GIZMO_AHB_MEM_0_MAX_AHB_BURSTSIZE_SHIFT)
+#define AHB_GIZMO_AHB_MEM_0_MAX_AHB_BURSTSIZE_RANGE                     17:16
+#define AHB_GIZMO_AHB_MEM_0_MAX_AHB_BURSTSIZE_WOFFSET                   0x0
+#define AHB_GIZMO_AHB_MEM_0_MAX_AHB_BURSTSIZE_DEFAULT                   _MK_MASK_CONST(0x2)
+#define AHB_GIZMO_AHB_MEM_0_MAX_AHB_BURSTSIZE_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define AHB_GIZMO_AHB_MEM_0_MAX_AHB_BURSTSIZE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_MEM_0_MAX_AHB_BURSTSIZE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_MEM_0_MAX_AHB_BURSTSIZE_DMA_BURST_1WORDS                  _MK_ENUM_CONST(0)
+#define AHB_GIZMO_AHB_MEM_0_MAX_AHB_BURSTSIZE_DMA_BURST_4WORDS                  _MK_ENUM_CONST(1)
+#define AHB_GIZMO_AHB_MEM_0_MAX_AHB_BURSTSIZE_DMA_BURST_8WORDS                  _MK_ENUM_CONST(2)
+#define AHB_GIZMO_AHB_MEM_0_MAX_AHB_BURSTSIZE_DMA_BURST_16WORDS                 _MK_ENUM_CONST(3)
+
+// AHB slave gizmo (memory controller)-Dont split AHB write transaction 1 = dont 
+// split AHB write transaction  ever. 0 (and enable_split=1) = allow AHB write 
+// transaction to be split.
+#define AHB_GIZMO_AHB_MEM_0_DONT_SPLIT_AHB_WR_SHIFT                     _MK_SHIFT_CONST(7)
+#define AHB_GIZMO_AHB_MEM_0_DONT_SPLIT_AHB_WR_FIELD                     (_MK_MASK_CONST(0x1) << AHB_GIZMO_AHB_MEM_0_DONT_SPLIT_AHB_WR_SHIFT)
+#define AHB_GIZMO_AHB_MEM_0_DONT_SPLIT_AHB_WR_RANGE                     7:7
+#define AHB_GIZMO_AHB_MEM_0_DONT_SPLIT_AHB_WR_WOFFSET                   0x0
+#define AHB_GIZMO_AHB_MEM_0_DONT_SPLIT_AHB_WR_DEFAULT                   _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_AHB_MEM_0_DONT_SPLIT_AHB_WR_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_AHB_MEM_0_DONT_SPLIT_AHB_WR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_MEM_0_DONT_SPLIT_AHB_WR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_MEM_0_DONT_SPLIT_AHB_WR_ENABLE                    _MK_ENUM_CONST(0)
+#define AHB_GIZMO_AHB_MEM_0_DONT_SPLIT_AHB_WR_DISABLE                   _MK_ENUM_CONST(1)
+
+// AHB slave gizmo (memory controller ) - Accept AHB write request 
+// always. 1= always accept AHB write request without checking 
+// whether there is room in the queue to store the write data.Bypass 
+// Memory Controller AHB slave gizmo write queue. 0 = accept AHB 
+// write request only when theres  enough room in the queue to store 
+// all the write data. Memory controller AHB  slave gizmos write queue 
+// is used in this case.
+#define AHB_GIZMO_AHB_MEM_0_ACCEPT_AHB_WR_ALWAYS_SHIFT                  _MK_SHIFT_CONST(6)
+#define AHB_GIZMO_AHB_MEM_0_ACCEPT_AHB_WR_ALWAYS_FIELD                  (_MK_MASK_CONST(0x1) << AHB_GIZMO_AHB_MEM_0_ACCEPT_AHB_WR_ALWAYS_SHIFT)
+#define AHB_GIZMO_AHB_MEM_0_ACCEPT_AHB_WR_ALWAYS_RANGE                  6:6
+#define AHB_GIZMO_AHB_MEM_0_ACCEPT_AHB_WR_ALWAYS_WOFFSET                        0x0
+#define AHB_GIZMO_AHB_MEM_0_ACCEPT_AHB_WR_ALWAYS_DEFAULT                        _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_AHB_MEM_0_ACCEPT_AHB_WR_ALWAYS_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_AHB_MEM_0_ACCEPT_AHB_WR_ALWAYS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_MEM_0_ACCEPT_AHB_WR_ALWAYS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_MEM_0_ACCEPT_AHB_WR_ALWAYS_ACCEPT_ON_CHECK                        _MK_ENUM_CONST(0)
+#define AHB_GIZMO_AHB_MEM_0_ACCEPT_AHB_WR_ALWAYS_ACCEPT_ON_NOCHECK                      _MK_ENUM_CONST(1)
+
+// AHB slave gizmo - Enable fast re-arbitration. 1 = allow AHB master re-arbitration as 
+// soon as the device returns one read data into the gizmos queue. 0 = allow AHB master 
+// re-arbitration only when the  device returns all read data into the gizmos queue.
+#define AHB_GIZMO_AHB_MEM_0_ENB_FAST_REARBITRATE_SHIFT                  _MK_SHIFT_CONST(2)
+#define AHB_GIZMO_AHB_MEM_0_ENB_FAST_REARBITRATE_FIELD                  (_MK_MASK_CONST(0x1) << AHB_GIZMO_AHB_MEM_0_ENB_FAST_REARBITRATE_SHIFT)
+#define AHB_GIZMO_AHB_MEM_0_ENB_FAST_REARBITRATE_RANGE                  2:2
+#define AHB_GIZMO_AHB_MEM_0_ENB_FAST_REARBITRATE_WOFFSET                        0x0
+#define AHB_GIZMO_AHB_MEM_0_ENB_FAST_REARBITRATE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_MEM_0_ENB_FAST_REARBITRATE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_AHB_MEM_0_ENB_FAST_REARBITRATE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_MEM_0_ENB_FAST_REARBITRATE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_MEM_0_ENB_FAST_REARBITRATE_DISABLE                        _MK_ENUM_CONST(0)
+#define AHB_GIZMO_AHB_MEM_0_ENB_FAST_REARBITRATE_ENABLE                 _MK_ENUM_CONST(1)
+
+// AHB slave gizmo (memory controller ) - Foce all AHB transaction to single 
+// data request transaction 1 = force to single data transaction always.  
+// 0 = dont force to single data transaction.
+#define AHB_GIZMO_AHB_MEM_0_FORCE_TO_AHB_SINGLE_SHIFT                   _MK_SHIFT_CONST(1)
+#define AHB_GIZMO_AHB_MEM_0_FORCE_TO_AHB_SINGLE_FIELD                   (_MK_MASK_CONST(0x1) << AHB_GIZMO_AHB_MEM_0_FORCE_TO_AHB_SINGLE_SHIFT)
+#define AHB_GIZMO_AHB_MEM_0_FORCE_TO_AHB_SINGLE_RANGE                   1:1
+#define AHB_GIZMO_AHB_MEM_0_FORCE_TO_AHB_SINGLE_WOFFSET                 0x0
+#define AHB_GIZMO_AHB_MEM_0_FORCE_TO_AHB_SINGLE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_MEM_0_FORCE_TO_AHB_SINGLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_AHB_MEM_0_FORCE_TO_AHB_SINGLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_MEM_0_FORCE_TO_AHB_SINGLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_MEM_0_FORCE_TO_AHB_SINGLE_NOT_SINGLE_DATA                 _MK_ENUM_CONST(0)
+#define AHB_GIZMO_AHB_MEM_0_FORCE_TO_AHB_SINGLE_SINGLE_DATA                     _MK_ENUM_CONST(1)
+
+// AHB slave gizmo (memory controller ) - Enable splitting AHB transaction. 
+// 1 = enable 0 = disable.
+#define AHB_GIZMO_AHB_MEM_0_ENABLE_SPLIT_SHIFT                  _MK_SHIFT_CONST(0)
+#define AHB_GIZMO_AHB_MEM_0_ENABLE_SPLIT_FIELD                  (_MK_MASK_CONST(0x1) << AHB_GIZMO_AHB_MEM_0_ENABLE_SPLIT_SHIFT)
+#define AHB_GIZMO_AHB_MEM_0_ENABLE_SPLIT_RANGE                  0:0
+#define AHB_GIZMO_AHB_MEM_0_ENABLE_SPLIT_WOFFSET                        0x0
+#define AHB_GIZMO_AHB_MEM_0_ENABLE_SPLIT_DEFAULT                        _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_AHB_MEM_0_ENABLE_SPLIT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_AHB_MEM_0_ENABLE_SPLIT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_MEM_0_ENABLE_SPLIT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_MEM_0_ENABLE_SPLIT_DISABLE                        _MK_ENUM_CONST(0)
+#define AHB_GIZMO_AHB_MEM_0_ENABLE_SPLIT_ENABLE                 _MK_ENUM_CONST(1)
+
+
+// Register AHB_GIZMO_APB_DMA_0  
+#define AHB_GIZMO_APB_DMA_0                     _MK_ADDR_CONST(0x10)
+#define AHB_GIZMO_APB_DMA_0_WORD_COUNT                  0x1
+#define AHB_GIZMO_APB_DMA_0_RESET_VAL                   _MK_MASK_CONST(0xa0000)
+#define AHB_GIZMO_APB_DMA_0_RESET_MASK                  _MK_MASK_CONST(0xff0f0000)
+#define AHB_GIZMO_APB_DMA_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_APB_DMA_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_APB_DMA_0_READ_MASK                   _MK_MASK_CONST(0xff0f0000)
+#define AHB_GIZMO_APB_DMA_0_WRITE_MASK                  _MK_MASK_CONST(0xff0f0000)
+// AHB master request negate count. This is an 8-bit  counter use to indicate 
+// the minimum number of clk count between requests from  this AHB master.
+#define AHB_GIZMO_APB_DMA_0_REQ_NEG_CNT_SHIFT                   _MK_SHIFT_CONST(24)
+#define AHB_GIZMO_APB_DMA_0_REQ_NEG_CNT_FIELD                   (_MK_MASK_CONST(0xff) << AHB_GIZMO_APB_DMA_0_REQ_NEG_CNT_SHIFT)
+#define AHB_GIZMO_APB_DMA_0_REQ_NEG_CNT_RANGE                   31:24
+#define AHB_GIZMO_APB_DMA_0_REQ_NEG_CNT_WOFFSET                 0x0
+#define AHB_GIZMO_APB_DMA_0_REQ_NEG_CNT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_APB_DMA_0_REQ_NEG_CNT_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define AHB_GIZMO_APB_DMA_0_REQ_NEG_CNT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_APB_DMA_0_REQ_NEG_CNT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// AHB master gizmo - Pack all AHB read data.  1 = wait for all 
+// requested read data to be in the AHB gizmos queue before returning 
+// the data back to the IP. 0 = transfer each read data from the AHB 
+// to the IP  immediately.
+#define AHB_GIZMO_APB_DMA_0_RD_DATA_SHIFT                       _MK_SHIFT_CONST(19)
+#define AHB_GIZMO_APB_DMA_0_RD_DATA_FIELD                       (_MK_MASK_CONST(0x1) << AHB_GIZMO_APB_DMA_0_RD_DATA_SHIFT)
+#define AHB_GIZMO_APB_DMA_0_RD_DATA_RANGE                       19:19
+#define AHB_GIZMO_APB_DMA_0_RD_DATA_WOFFSET                     0x0
+#define AHB_GIZMO_APB_DMA_0_RD_DATA_DEFAULT                     _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_APB_DMA_0_RD_DATA_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_APB_DMA_0_RD_DATA_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_APB_DMA_0_RD_DATA_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_APB_DMA_0_RD_DATA_NO_WAIT                     _MK_ENUM_CONST(0)
+#define AHB_GIZMO_APB_DMA_0_RD_DATA_WAIT                        _MK_ENUM_CONST(1)
+
+// AHB master gizmo (AHB-DMA) - Start AHB write request immediately.  
+// 1 = start the AHB write request immediately as soon as the device has 
+// put one write data in the AHB gizmos queue. 0 = start the AHB write 
+// request only when all the  write data has transferred from the device 
+// to the AHB gizmos queue.
+#define AHB_GIZMO_APB_DMA_0_IMMEDIATE_SHIFT                     _MK_SHIFT_CONST(18)
+#define AHB_GIZMO_APB_DMA_0_IMMEDIATE_FIELD                     (_MK_MASK_CONST(0x1) << AHB_GIZMO_APB_DMA_0_IMMEDIATE_SHIFT)
+#define AHB_GIZMO_APB_DMA_0_IMMEDIATE_RANGE                     18:18
+#define AHB_GIZMO_APB_DMA_0_IMMEDIATE_WOFFSET                   0x0
+#define AHB_GIZMO_APB_DMA_0_IMMEDIATE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_APB_DMA_0_IMMEDIATE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_APB_DMA_0_IMMEDIATE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_APB_DMA_0_IMMEDIATE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_APB_DMA_0_IMMEDIATE_DISABLE                   _MK_ENUM_CONST(0)
+#define AHB_GIZMO_APB_DMA_0_IMMEDIATE_ENABLE                    _MK_ENUM_CONST(1)
+
+// AHB master gizmo - Maximum allowed 
+// AHB burst size.  
+// 00 = single transfer.  
+// 01 = burst-of-4.  
+// 10 = burst-of-8. 
+// 11 = burst-of-16.
+#define AHB_GIZMO_APB_DMA_0_MAX_AHB_BURSTSIZE_SHIFT                     _MK_SHIFT_CONST(16)
+#define AHB_GIZMO_APB_DMA_0_MAX_AHB_BURSTSIZE_FIELD                     (_MK_MASK_CONST(0x3) << AHB_GIZMO_APB_DMA_0_MAX_AHB_BURSTSIZE_SHIFT)
+#define AHB_GIZMO_APB_DMA_0_MAX_AHB_BURSTSIZE_RANGE                     17:16
+#define AHB_GIZMO_APB_DMA_0_MAX_AHB_BURSTSIZE_WOFFSET                   0x0
+#define AHB_GIZMO_APB_DMA_0_MAX_AHB_BURSTSIZE_DEFAULT                   _MK_MASK_CONST(0x2)
+#define AHB_GIZMO_APB_DMA_0_MAX_AHB_BURSTSIZE_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define AHB_GIZMO_APB_DMA_0_MAX_AHB_BURSTSIZE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_APB_DMA_0_MAX_AHB_BURSTSIZE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_APB_DMA_0_MAX_AHB_BURSTSIZE_DMA_BURST_1WORDS                  _MK_ENUM_CONST(0)
+#define AHB_GIZMO_APB_DMA_0_MAX_AHB_BURSTSIZE_DMA_BURST_4WORDS                  _MK_ENUM_CONST(1)
+#define AHB_GIZMO_APB_DMA_0_MAX_AHB_BURSTSIZE_DMA_BURST_8WORDS                  _MK_ENUM_CONST(2)
+#define AHB_GIZMO_APB_DMA_0_MAX_AHB_BURSTSIZE_DMA_BURST_16WORDS                 _MK_ENUM_CONST(3)
+
+
+// Reserved address 20 [0x14] 
+
+// Register AHB_GIZMO_IDE_0  
+#define AHB_GIZMO_IDE_0                 _MK_ADDR_CONST(0x18)
+#define AHB_GIZMO_IDE_0_WORD_COUNT                      0x1
+#define AHB_GIZMO_IDE_0_RESET_VAL                       _MK_MASK_CONST(0x200bf)
+#define AHB_GIZMO_IDE_0_RESET_MASK                      _MK_MASK_CONST(0xff0f00ff)
+#define AHB_GIZMO_IDE_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_IDE_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_IDE_0_READ_MASK                       _MK_MASK_CONST(0xff0f00ff)
+#define AHB_GIZMO_IDE_0_WRITE_MASK                      _MK_MASK_CONST(0xff0f00ff)
+// AHB master request negate count. This is an 8-bit  counter use to indicate the minimum number of clk 
+// count between requests from  this AHB master.
+#define AHB_GIZMO_IDE_0_REQ_NEG_CNT_SHIFT                       _MK_SHIFT_CONST(24)
+#define AHB_GIZMO_IDE_0_REQ_NEG_CNT_FIELD                       (_MK_MASK_CONST(0xff) << AHB_GIZMO_IDE_0_REQ_NEG_CNT_SHIFT)
+#define AHB_GIZMO_IDE_0_REQ_NEG_CNT_RANGE                       31:24
+#define AHB_GIZMO_IDE_0_REQ_NEG_CNT_WOFFSET                     0x0
+#define AHB_GIZMO_IDE_0_REQ_NEG_CNT_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_IDE_0_REQ_NEG_CNT_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define AHB_GIZMO_IDE_0_REQ_NEG_CNT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_IDE_0_REQ_NEG_CNT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// AHB master gizmo - Pack all AHB read data.  1 = wait for all requested read data 
+// to be in the AHB gizmos queue before returning the data back to the IP. 0 = transfer 
+// each read data from the AHB to the IP  immediately.
+#define AHB_GIZMO_IDE_0_RD_DATA_SHIFT                   _MK_SHIFT_CONST(19)
+#define AHB_GIZMO_IDE_0_RD_DATA_FIELD                   (_MK_MASK_CONST(0x1) << AHB_GIZMO_IDE_0_RD_DATA_SHIFT)
+#define AHB_GIZMO_IDE_0_RD_DATA_RANGE                   19:19
+#define AHB_GIZMO_IDE_0_RD_DATA_WOFFSET                 0x0
+#define AHB_GIZMO_IDE_0_RD_DATA_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_IDE_0_RD_DATA_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_IDE_0_RD_DATA_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_IDE_0_RD_DATA_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_IDE_0_RD_DATA_NO_WAIT                 _MK_ENUM_CONST(0)
+#define AHB_GIZMO_IDE_0_RD_DATA_WAIT                    _MK_ENUM_CONST(1)
+
+// AHB master gizmo (AHB-DMA) - Start AHB write request immediately.  1 = start the 
+// AHB write request immediately as soon as the device has put one write data in the 
+// AHB gizmos queue. 0 = start the AHB write request only when all the  write data 
+// has transferred from the device to the AHB gizmos queue.
+#define AHB_GIZMO_IDE_0_IMMEDIATE_SHIFT                 _MK_SHIFT_CONST(18)
+#define AHB_GIZMO_IDE_0_IMMEDIATE_FIELD                 (_MK_MASK_CONST(0x1) << AHB_GIZMO_IDE_0_IMMEDIATE_SHIFT)
+#define AHB_GIZMO_IDE_0_IMMEDIATE_RANGE                 18:18
+#define AHB_GIZMO_IDE_0_IMMEDIATE_WOFFSET                       0x0
+#define AHB_GIZMO_IDE_0_IMMEDIATE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_IDE_0_IMMEDIATE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_IDE_0_IMMEDIATE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_IDE_0_IMMEDIATE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_IDE_0_IMMEDIATE_DISABLE                       _MK_ENUM_CONST(0)
+#define AHB_GIZMO_IDE_0_IMMEDIATE_ENABLE                        _MK_ENUM_CONST(1)
+
+// AHB master gizmo - Maximum 
+// allowed AHB burst size.  
+// 00 = single transfer.  
+// 01 = burst-of-4.  
+// 10 = burst-of-8. 
+// 11 = burst-of-16.
+#define AHB_GIZMO_IDE_0_MAX_AHB_BURSTSIZE_SHIFT                 _MK_SHIFT_CONST(16)
+#define AHB_GIZMO_IDE_0_MAX_AHB_BURSTSIZE_FIELD                 (_MK_MASK_CONST(0x3) << AHB_GIZMO_IDE_0_MAX_AHB_BURSTSIZE_SHIFT)
+#define AHB_GIZMO_IDE_0_MAX_AHB_BURSTSIZE_RANGE                 17:16
+#define AHB_GIZMO_IDE_0_MAX_AHB_BURSTSIZE_WOFFSET                       0x0
+#define AHB_GIZMO_IDE_0_MAX_AHB_BURSTSIZE_DEFAULT                       _MK_MASK_CONST(0x2)
+#define AHB_GIZMO_IDE_0_MAX_AHB_BURSTSIZE_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define AHB_GIZMO_IDE_0_MAX_AHB_BURSTSIZE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_IDE_0_MAX_AHB_BURSTSIZE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_IDE_0_MAX_AHB_BURSTSIZE_DMA_BURST_1WORDS                      _MK_ENUM_CONST(0)
+#define AHB_GIZMO_IDE_0_MAX_AHB_BURSTSIZE_DMA_BURST_4WORDS                      _MK_ENUM_CONST(1)
+#define AHB_GIZMO_IDE_0_MAX_AHB_BURSTSIZE_DMA_BURST_8WORDS                      _MK_ENUM_CONST(2)
+#define AHB_GIZMO_IDE_0_MAX_AHB_BURSTSIZE_DMA_BURST_16WORDS                     _MK_ENUM_CONST(3)
+
+// AHB slave gizmo - Dont split AHB write transaction.  1 = dont split AHB write transaction 
+// ever. 0 (and enable_split=1) = allow AHB write  transaction to be split.
+#define AHB_GIZMO_IDE_0_DONT_SPLIT_AHB_WR_SHIFT                 _MK_SHIFT_CONST(7)
+#define AHB_GIZMO_IDE_0_DONT_SPLIT_AHB_WR_FIELD                 (_MK_MASK_CONST(0x1) << AHB_GIZMO_IDE_0_DONT_SPLIT_AHB_WR_SHIFT)
+#define AHB_GIZMO_IDE_0_DONT_SPLIT_AHB_WR_RANGE                 7:7
+#define AHB_GIZMO_IDE_0_DONT_SPLIT_AHB_WR_WOFFSET                       0x0
+#define AHB_GIZMO_IDE_0_DONT_SPLIT_AHB_WR_DEFAULT                       _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_IDE_0_DONT_SPLIT_AHB_WR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_IDE_0_DONT_SPLIT_AHB_WR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_IDE_0_DONT_SPLIT_AHB_WR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_IDE_0_DONT_SPLIT_AHB_WR_ENABLE                        _MK_ENUM_CONST(0)
+#define AHB_GIZMO_IDE_0_DONT_SPLIT_AHB_WR_DISABLE                       _MK_ENUM_CONST(1)
+
+// AHB slave gizmo - Accept AHB write request always.  1 = always accept 
+// AHB write request without checking whether there is room in the queue 
+// to store the write data. 0 = accept AHB write request only when theres  
+// enough room in the queue to store all the write data.
+#define AHB_GIZMO_IDE_0_ACCEPT_AHB_WR_ALWAYS_SHIFT                      _MK_SHIFT_CONST(6)
+#define AHB_GIZMO_IDE_0_ACCEPT_AHB_WR_ALWAYS_FIELD                      (_MK_MASK_CONST(0x1) << AHB_GIZMO_IDE_0_ACCEPT_AHB_WR_ALWAYS_SHIFT)
+#define AHB_GIZMO_IDE_0_ACCEPT_AHB_WR_ALWAYS_RANGE                      6:6
+#define AHB_GIZMO_IDE_0_ACCEPT_AHB_WR_ALWAYS_WOFFSET                    0x0
+#define AHB_GIZMO_IDE_0_ACCEPT_AHB_WR_ALWAYS_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_IDE_0_ACCEPT_AHB_WR_ALWAYS_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_IDE_0_ACCEPT_AHB_WR_ALWAYS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_IDE_0_ACCEPT_AHB_WR_ALWAYS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_IDE_0_ACCEPT_AHB_WR_ALWAYS_ACCEPT_ON_CHECK                    _MK_ENUM_CONST(0)
+#define AHB_GIZMO_IDE_0_ACCEPT_AHB_WR_ALWAYS_ACCEPT_ON_NOCHECK                  _MK_ENUM_CONST(1)
+
+// AHB slave gizmo  Maximum allowed IP 
+// burst size.  
+// 00 = single transfer.  
+// 01 = burst-of-4.  
+// 10 = burst-of-8.
+// 11 = burst-of-16.
+#define AHB_GIZMO_IDE_0_MAX_IP_BURSTSIZE_SHIFT                  _MK_SHIFT_CONST(4)
+#define AHB_GIZMO_IDE_0_MAX_IP_BURSTSIZE_FIELD                  (_MK_MASK_CONST(0x3) << AHB_GIZMO_IDE_0_MAX_IP_BURSTSIZE_SHIFT)
+#define AHB_GIZMO_IDE_0_MAX_IP_BURSTSIZE_RANGE                  5:4
+#define AHB_GIZMO_IDE_0_MAX_IP_BURSTSIZE_WOFFSET                        0x0
+#define AHB_GIZMO_IDE_0_MAX_IP_BURSTSIZE_DEFAULT                        _MK_MASK_CONST(0x3)
+#define AHB_GIZMO_IDE_0_MAX_IP_BURSTSIZE_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define AHB_GIZMO_IDE_0_MAX_IP_BURSTSIZE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_IDE_0_MAX_IP_BURSTSIZE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_IDE_0_MAX_IP_BURSTSIZE_DMA_BURST_1WORDS                       _MK_ENUM_CONST(0)
+#define AHB_GIZMO_IDE_0_MAX_IP_BURSTSIZE_DMA_BURST_4WORDS                       _MK_ENUM_CONST(1)
+#define AHB_GIZMO_IDE_0_MAX_IP_BURSTSIZE_DMA_BURST_8WORDS                       _MK_ENUM_CONST(2)
+#define AHB_GIZMO_IDE_0_MAX_IP_BURSTSIZE_DMA_BURST_16WORDS                      _MK_ENUM_CONST(3)
+
+// AHB slave gizmo  Start write request to device immediately.  1 = start write request on the device side as soon 
+// as the AHB master puts data into the gizmos queue. 0 = start the device write request only when the  AHB master 
+// has placed all write data into the gizmos queue.
+#define AHB_GIZMO_IDE_0_IP_WR_REQ_IMMEDIATE_SHIFT                       _MK_SHIFT_CONST(3)
+#define AHB_GIZMO_IDE_0_IP_WR_REQ_IMMEDIATE_FIELD                       (_MK_MASK_CONST(0x1) << AHB_GIZMO_IDE_0_IP_WR_REQ_IMMEDIATE_SHIFT)
+#define AHB_GIZMO_IDE_0_IP_WR_REQ_IMMEDIATE_RANGE                       3:3
+#define AHB_GIZMO_IDE_0_IP_WR_REQ_IMMEDIATE_WOFFSET                     0x0
+#define AHB_GIZMO_IDE_0_IP_WR_REQ_IMMEDIATE_DEFAULT                     _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_IDE_0_IP_WR_REQ_IMMEDIATE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_IDE_0_IP_WR_REQ_IMMEDIATE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_IDE_0_IP_WR_REQ_IMMEDIATE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// AHB slave gizmo - Enable fast re-arbitration.  1 = allow AHB master re-arbitration as soon 
+// as the device returns one read data into the gizmos queue.0 = allow AHB master re-arbitration 
+// only when the  device returns all read data into the gizmos queue.
+#define AHB_GIZMO_IDE_0_ENB_FAST_REARBITRATE_SHIFT                      _MK_SHIFT_CONST(2)
+#define AHB_GIZMO_IDE_0_ENB_FAST_REARBITRATE_FIELD                      (_MK_MASK_CONST(0x1) << AHB_GIZMO_IDE_0_ENB_FAST_REARBITRATE_SHIFT)
+#define AHB_GIZMO_IDE_0_ENB_FAST_REARBITRATE_RANGE                      2:2
+#define AHB_GIZMO_IDE_0_ENB_FAST_REARBITRATE_WOFFSET                    0x0
+#define AHB_GIZMO_IDE_0_ENB_FAST_REARBITRATE_DEFAULT                    _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_IDE_0_ENB_FAST_REARBITRATE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_IDE_0_ENB_FAST_REARBITRATE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_IDE_0_ENB_FAST_REARBITRATE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_IDE_0_ENB_FAST_REARBITRATE_DISABLE                    _MK_ENUM_CONST(0)
+#define AHB_GIZMO_IDE_0_ENB_FAST_REARBITRATE_ENABLE                     _MK_ENUM_CONST(1)
+
+// AHB slave gizmo - Force all AHB transaction to single data request transaction.  
+// 1 = force to single data transaction always. 
+// 0 = dont force to single data  transaction.
+#define AHB_GIZMO_IDE_0_FORCE_TO_AHB_SINGLE_SHIFT                       _MK_SHIFT_CONST(1)
+#define AHB_GIZMO_IDE_0_FORCE_TO_AHB_SINGLE_FIELD                       (_MK_MASK_CONST(0x1) << AHB_GIZMO_IDE_0_FORCE_TO_AHB_SINGLE_SHIFT)
+#define AHB_GIZMO_IDE_0_FORCE_TO_AHB_SINGLE_RANGE                       1:1
+#define AHB_GIZMO_IDE_0_FORCE_TO_AHB_SINGLE_WOFFSET                     0x0
+#define AHB_GIZMO_IDE_0_FORCE_TO_AHB_SINGLE_DEFAULT                     _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_IDE_0_FORCE_TO_AHB_SINGLE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_IDE_0_FORCE_TO_AHB_SINGLE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_IDE_0_FORCE_TO_AHB_SINGLE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_IDE_0_FORCE_TO_AHB_SINGLE_NOT_SINGLE_DATA                     _MK_ENUM_CONST(0)
+#define AHB_GIZMO_IDE_0_FORCE_TO_AHB_SINGLE_SINGLE_DATA                 _MK_ENUM_CONST(1)
+
+// AHB slave gizmo - Enable splitting AHB transactions.  1 = enable, 0 = disable.
+#define AHB_GIZMO_IDE_0_ENABLE_SPLIT_SHIFT                      _MK_SHIFT_CONST(0)
+#define AHB_GIZMO_IDE_0_ENABLE_SPLIT_FIELD                      (_MK_MASK_CONST(0x1) << AHB_GIZMO_IDE_0_ENABLE_SPLIT_SHIFT)
+#define AHB_GIZMO_IDE_0_ENABLE_SPLIT_RANGE                      0:0
+#define AHB_GIZMO_IDE_0_ENABLE_SPLIT_WOFFSET                    0x0
+#define AHB_GIZMO_IDE_0_ENABLE_SPLIT_DEFAULT                    _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_IDE_0_ENABLE_SPLIT_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_IDE_0_ENABLE_SPLIT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_IDE_0_ENABLE_SPLIT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_IDE_0_ENABLE_SPLIT_DISABLE                    _MK_ENUM_CONST(0)
+#define AHB_GIZMO_IDE_0_ENABLE_SPLIT_ENABLE                     _MK_ENUM_CONST(1)
+
+
+// Register AHB_GIZMO_USB_0  
+#define AHB_GIZMO_USB_0                 _MK_ADDR_CONST(0x1c)
+#define AHB_GIZMO_USB_0_WORD_COUNT                      0x1
+#define AHB_GIZMO_USB_0_RESET_VAL                       _MK_MASK_CONST(0x20083)
+#define AHB_GIZMO_USB_0_RESET_MASK                      _MK_MASK_CONST(0xff0f00cf)
+#define AHB_GIZMO_USB_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB_0_READ_MASK                       _MK_MASK_CONST(0xff0f00cf)
+#define AHB_GIZMO_USB_0_WRITE_MASK                      _MK_MASK_CONST(0xff0f00cf)
+// AHB master request negate count. This is an 8-bit  counter use to indicate the minimum number of clk count 
+// between requests from  this AHB master.
+#define AHB_GIZMO_USB_0_REQ_NEG_CNT_SHIFT                       _MK_SHIFT_CONST(24)
+#define AHB_GIZMO_USB_0_REQ_NEG_CNT_FIELD                       (_MK_MASK_CONST(0xff) << AHB_GIZMO_USB_0_REQ_NEG_CNT_SHIFT)
+#define AHB_GIZMO_USB_0_REQ_NEG_CNT_RANGE                       31:24
+#define AHB_GIZMO_USB_0_REQ_NEG_CNT_WOFFSET                     0x0
+#define AHB_GIZMO_USB_0_REQ_NEG_CNT_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB_0_REQ_NEG_CNT_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define AHB_GIZMO_USB_0_REQ_NEG_CNT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB_0_REQ_NEG_CNT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// AHB master gizmo - Pack all AHB read data.  1 = wait for all requested read data to be in 
+// the AHB gizmos queue before returning the data back to the IP. 0 = transfer each read data 
+// from the AHB to the IP  immediately.
+#define AHB_GIZMO_USB_0_RD_DATA_SHIFT                   _MK_SHIFT_CONST(19)
+#define AHB_GIZMO_USB_0_RD_DATA_FIELD                   (_MK_MASK_CONST(0x1) << AHB_GIZMO_USB_0_RD_DATA_SHIFT)
+#define AHB_GIZMO_USB_0_RD_DATA_RANGE                   19:19
+#define AHB_GIZMO_USB_0_RD_DATA_WOFFSET                 0x0
+#define AHB_GIZMO_USB_0_RD_DATA_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB_0_RD_DATA_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_USB_0_RD_DATA_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB_0_RD_DATA_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB_0_RD_DATA_NO_WAIT                 _MK_ENUM_CONST(0)
+#define AHB_GIZMO_USB_0_RD_DATA_WAIT                    _MK_ENUM_CONST(1)
+
+// AHB master gizmo (AHB-DMA) - Start AHB write request immediately.  1 = start the AHB 
+// write request immediately as soon as the device has put one write data in the AHB gizmos 
+// queue. 0 = start the AHB write request only when all the  write data has transferred 
+// from the device to the AHB gizmos queue.
+#define AHB_GIZMO_USB_0_IMMEDIATE_SHIFT                 _MK_SHIFT_CONST(18)
+#define AHB_GIZMO_USB_0_IMMEDIATE_FIELD                 (_MK_MASK_CONST(0x1) << AHB_GIZMO_USB_0_IMMEDIATE_SHIFT)
+#define AHB_GIZMO_USB_0_IMMEDIATE_RANGE                 18:18
+#define AHB_GIZMO_USB_0_IMMEDIATE_WOFFSET                       0x0
+#define AHB_GIZMO_USB_0_IMMEDIATE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB_0_IMMEDIATE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_USB_0_IMMEDIATE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB_0_IMMEDIATE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB_0_IMMEDIATE_DISABLE                       _MK_ENUM_CONST(0)
+#define AHB_GIZMO_USB_0_IMMEDIATE_ENABLE                        _MK_ENUM_CONST(1)
+
+// AHB master gizmo - Maximum allowed 
+// AHB burst size.  
+// 00 = single transfer.  
+// 01 = burst-of-4.  
+// 10 = burst-of-8. 
+// 11 = burst-of-16.
+#define AHB_GIZMO_USB_0_MAX_AHB_BURSTSIZE_SHIFT                 _MK_SHIFT_CONST(16)
+#define AHB_GIZMO_USB_0_MAX_AHB_BURSTSIZE_FIELD                 (_MK_MASK_CONST(0x3) << AHB_GIZMO_USB_0_MAX_AHB_BURSTSIZE_SHIFT)
+#define AHB_GIZMO_USB_0_MAX_AHB_BURSTSIZE_RANGE                 17:16
+#define AHB_GIZMO_USB_0_MAX_AHB_BURSTSIZE_WOFFSET                       0x0
+#define AHB_GIZMO_USB_0_MAX_AHB_BURSTSIZE_DEFAULT                       _MK_MASK_CONST(0x2)
+#define AHB_GIZMO_USB_0_MAX_AHB_BURSTSIZE_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define AHB_GIZMO_USB_0_MAX_AHB_BURSTSIZE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB_0_MAX_AHB_BURSTSIZE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB_0_MAX_AHB_BURSTSIZE_DMA_BURST_1WORDS                      _MK_ENUM_CONST(0)
+#define AHB_GIZMO_USB_0_MAX_AHB_BURSTSIZE_DMA_BURST_4WORDS                      _MK_ENUM_CONST(1)
+#define AHB_GIZMO_USB_0_MAX_AHB_BURSTSIZE_DMA_BURST_8WORDS                      _MK_ENUM_CONST(2)
+#define AHB_GIZMO_USB_0_MAX_AHB_BURSTSIZE_DMA_BURST_16WORDS                     _MK_ENUM_CONST(3)
+
+// AHB slave gizmo - Dont split AHB write transaction.  1 = dont split AHB write transaction 
+// ever. 0 (and enable_split=1) = allow AHB write  transaction to be split.
+#define AHB_GIZMO_USB_0_DONT_SPLIT_AHB_WR_SHIFT                 _MK_SHIFT_CONST(7)
+#define AHB_GIZMO_USB_0_DONT_SPLIT_AHB_WR_FIELD                 (_MK_MASK_CONST(0x1) << AHB_GIZMO_USB_0_DONT_SPLIT_AHB_WR_SHIFT)
+#define AHB_GIZMO_USB_0_DONT_SPLIT_AHB_WR_RANGE                 7:7
+#define AHB_GIZMO_USB_0_DONT_SPLIT_AHB_WR_WOFFSET                       0x0
+#define AHB_GIZMO_USB_0_DONT_SPLIT_AHB_WR_DEFAULT                       _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_USB_0_DONT_SPLIT_AHB_WR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_USB_0_DONT_SPLIT_AHB_WR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB_0_DONT_SPLIT_AHB_WR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB_0_DONT_SPLIT_AHB_WR_ENABLE                        _MK_ENUM_CONST(0)
+#define AHB_GIZMO_USB_0_DONT_SPLIT_AHB_WR_DISABLE                       _MK_ENUM_CONST(1)
+
+// AHB slave gizmo - Accept AHB write request always.  1 = always accept 
+// AHB write request without checking whether there is room in the queue 
+// to store the write data. 0 = accept AHB write request only when theres  
+// enough room in the queue to store all the write data.
+#define AHB_GIZMO_USB_0_ACCEPT_AHB_WR_ALWAYS_SHIFT                      _MK_SHIFT_CONST(6)
+#define AHB_GIZMO_USB_0_ACCEPT_AHB_WR_ALWAYS_FIELD                      (_MK_MASK_CONST(0x1) << AHB_GIZMO_USB_0_ACCEPT_AHB_WR_ALWAYS_SHIFT)
+#define AHB_GIZMO_USB_0_ACCEPT_AHB_WR_ALWAYS_RANGE                      6:6
+#define AHB_GIZMO_USB_0_ACCEPT_AHB_WR_ALWAYS_WOFFSET                    0x0
+#define AHB_GIZMO_USB_0_ACCEPT_AHB_WR_ALWAYS_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB_0_ACCEPT_AHB_WR_ALWAYS_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_USB_0_ACCEPT_AHB_WR_ALWAYS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB_0_ACCEPT_AHB_WR_ALWAYS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB_0_ACCEPT_AHB_WR_ALWAYS_ACCEPT_ON_CHECK                    _MK_ENUM_CONST(0)
+#define AHB_GIZMO_USB_0_ACCEPT_AHB_WR_ALWAYS_ACCEPT_ON_NOCHECK                  _MK_ENUM_CONST(1)
+
+// AHB slave gizmo  Start write request to device immediately.  1 = start write request on 
+// the device side as soon as the AHB master puts data into the gizmos queue. 0 = start the 
+// device write request only when the  AHB master has placed all write data into the gizmos 
+// queue.
+#define AHB_GIZMO_USB_0_IP_WR_REQ_IMMEDIATE_SHIFT                       _MK_SHIFT_CONST(3)
+#define AHB_GIZMO_USB_0_IP_WR_REQ_IMMEDIATE_FIELD                       (_MK_MASK_CONST(0x1) << AHB_GIZMO_USB_0_IP_WR_REQ_IMMEDIATE_SHIFT)
+#define AHB_GIZMO_USB_0_IP_WR_REQ_IMMEDIATE_RANGE                       3:3
+#define AHB_GIZMO_USB_0_IP_WR_REQ_IMMEDIATE_WOFFSET                     0x0
+#define AHB_GIZMO_USB_0_IP_WR_REQ_IMMEDIATE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB_0_IP_WR_REQ_IMMEDIATE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_USB_0_IP_WR_REQ_IMMEDIATE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB_0_IP_WR_REQ_IMMEDIATE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB_0_IP_WR_REQ_IMMEDIATE_DISABLE                     _MK_ENUM_CONST(0)
+#define AHB_GIZMO_USB_0_IP_WR_REQ_IMMEDIATE_ENABLE                      _MK_ENUM_CONST(1)
+
+// AHB slave gizmo - Enable fast re-arbitration.  1 = allow AHB master re-arbitration as soon 
+// as the device returns one read data into the gizmos queue. 0 = allow AHB master 
+// re-arbitration only when the  device returns all read data into the gizmos queue.
+#define AHB_GIZMO_USB_0_ENB_FAST_REARBITRATE_SHIFT                      _MK_SHIFT_CONST(2)
+#define AHB_GIZMO_USB_0_ENB_FAST_REARBITRATE_FIELD                      (_MK_MASK_CONST(0x1) << AHB_GIZMO_USB_0_ENB_FAST_REARBITRATE_SHIFT)
+#define AHB_GIZMO_USB_0_ENB_FAST_REARBITRATE_RANGE                      2:2
+#define AHB_GIZMO_USB_0_ENB_FAST_REARBITRATE_WOFFSET                    0x0
+#define AHB_GIZMO_USB_0_ENB_FAST_REARBITRATE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB_0_ENB_FAST_REARBITRATE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_USB_0_ENB_FAST_REARBITRATE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB_0_ENB_FAST_REARBITRATE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB_0_ENB_FAST_REARBITRATE_DISABLE                    _MK_ENUM_CONST(0)
+#define AHB_GIZMO_USB_0_ENB_FAST_REARBITRATE_ENABLE                     _MK_ENUM_CONST(1)
+
+// AHB slave gizmo - Force all AHB transaction to single data request transaction.  
+// 1 = force to single data transaction always. 
+// 0 = dont force to single data transaction.
+#define AHB_GIZMO_USB_0_FORCE_TO_AHB_SINGLE_SHIFT                       _MK_SHIFT_CONST(1)
+#define AHB_GIZMO_USB_0_FORCE_TO_AHB_SINGLE_FIELD                       (_MK_MASK_CONST(0x1) << AHB_GIZMO_USB_0_FORCE_TO_AHB_SINGLE_SHIFT)
+#define AHB_GIZMO_USB_0_FORCE_TO_AHB_SINGLE_RANGE                       1:1
+#define AHB_GIZMO_USB_0_FORCE_TO_AHB_SINGLE_WOFFSET                     0x0
+#define AHB_GIZMO_USB_0_FORCE_TO_AHB_SINGLE_DEFAULT                     _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_USB_0_FORCE_TO_AHB_SINGLE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_USB_0_FORCE_TO_AHB_SINGLE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB_0_FORCE_TO_AHB_SINGLE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB_0_FORCE_TO_AHB_SINGLE_NOT_SINGLE_DATA                     _MK_ENUM_CONST(0)
+#define AHB_GIZMO_USB_0_FORCE_TO_AHB_SINGLE_SINGLE_DATA                 _MK_ENUM_CONST(1)
+
+//AHB slave gizmo - Enable splitting AHB transactions.  1 = enable  0 = disable
+#define AHB_GIZMO_USB_0_ENABLE_SPLIT_SHIFT                      _MK_SHIFT_CONST(0)
+#define AHB_GIZMO_USB_0_ENABLE_SPLIT_FIELD                      (_MK_MASK_CONST(0x1) << AHB_GIZMO_USB_0_ENABLE_SPLIT_SHIFT)
+#define AHB_GIZMO_USB_0_ENABLE_SPLIT_RANGE                      0:0
+#define AHB_GIZMO_USB_0_ENABLE_SPLIT_WOFFSET                    0x0
+#define AHB_GIZMO_USB_0_ENABLE_SPLIT_DEFAULT                    _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_USB_0_ENABLE_SPLIT_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_USB_0_ENABLE_SPLIT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB_0_ENABLE_SPLIT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB_0_ENABLE_SPLIT_DISABLE                    _MK_ENUM_CONST(0)
+#define AHB_GIZMO_USB_0_ENABLE_SPLIT_ENABLE                     _MK_ENUM_CONST(1)
+
+
+// Register AHB_GIZMO_AHB_XBAR_BRIDGE_0  
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0                     _MK_ADDR_CONST(0x20)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_WORD_COUNT                  0x1
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_RESET_VAL                   _MK_MASK_CONST(0x8d)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_RESET_MASK                  _MK_MASK_CONST(0xff)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_READ_MASK                   _MK_MASK_CONST(0xff)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
+// AHB slave gizmo - Dont split AHB write transaction.  1 = dont split AHB write transaction ever. 
+// 0 (and enable_split=1) = allow AHB write  transaction to be split.
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_DONT_SPLIT_AHB_WR_SHIFT                     _MK_SHIFT_CONST(7)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_DONT_SPLIT_AHB_WR_FIELD                     (_MK_MASK_CONST(0x1) << AHB_GIZMO_AHB_XBAR_BRIDGE_0_DONT_SPLIT_AHB_WR_SHIFT)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_DONT_SPLIT_AHB_WR_RANGE                     7:7
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_DONT_SPLIT_AHB_WR_WOFFSET                   0x0
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_DONT_SPLIT_AHB_WR_DEFAULT                   _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_DONT_SPLIT_AHB_WR_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_DONT_SPLIT_AHB_WR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_DONT_SPLIT_AHB_WR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_DONT_SPLIT_AHB_WR_ENABLE                    _MK_ENUM_CONST(0)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_DONT_SPLIT_AHB_WR_DISABLE                   _MK_ENUM_CONST(1)
+
+// AHB slave gizmo - Accept AHB write request always.  1 = always accept AHB write 
+// request without checking whether there is room in the queue to store the write 
+// data. 0 = accept AHB write request only when theres  enough room in the queue 
+// to store all the write data.
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_ACCEPT_AHB_WR_ALWAYS_SHIFT                  _MK_SHIFT_CONST(6)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_ACCEPT_AHB_WR_ALWAYS_FIELD                  (_MK_MASK_CONST(0x1) << AHB_GIZMO_AHB_XBAR_BRIDGE_0_ACCEPT_AHB_WR_ALWAYS_SHIFT)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_ACCEPT_AHB_WR_ALWAYS_RANGE                  6:6
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_ACCEPT_AHB_WR_ALWAYS_WOFFSET                        0x0
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_ACCEPT_AHB_WR_ALWAYS_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_ACCEPT_AHB_WR_ALWAYS_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_ACCEPT_AHB_WR_ALWAYS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_ACCEPT_AHB_WR_ALWAYS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_ACCEPT_AHB_WR_ALWAYS_ACCEPT_ON_CHECK                        _MK_ENUM_CONST(0)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_ACCEPT_AHB_WR_ALWAYS_ACCEPT_ON_NOCHECK                      _MK_ENUM_CONST(1)
+
+// AHB slave gizmo - Maximum allowed IP burst 
+// size.  
+// 00 = single transfer.  
+// 01 = burst-of-4.  
+// 10 = burst-of-8.  
+// 11 = burst-of-16.
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_MAX_IP_BURSTSIZE_SHIFT                      _MK_SHIFT_CONST(4)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_MAX_IP_BURSTSIZE_FIELD                      (_MK_MASK_CONST(0x3) << AHB_GIZMO_AHB_XBAR_BRIDGE_0_MAX_IP_BURSTSIZE_SHIFT)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_MAX_IP_BURSTSIZE_RANGE                      5:4
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_MAX_IP_BURSTSIZE_WOFFSET                    0x0
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_MAX_IP_BURSTSIZE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_MAX_IP_BURSTSIZE_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_MAX_IP_BURSTSIZE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_MAX_IP_BURSTSIZE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_MAX_IP_BURSTSIZE_DMA_BURST_1WORDS                   _MK_ENUM_CONST(0)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_MAX_IP_BURSTSIZE_DMA_BURST_4WORDS                   _MK_ENUM_CONST(1)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_MAX_IP_BURSTSIZE_DMA_BURST_8WORDS                   _MK_ENUM_CONST(2)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_MAX_IP_BURSTSIZE_DMA_BURST_16WORDS                  _MK_ENUM_CONST(3)
+
+// AHB slave gizmo - Start write request to device immediately.  1 = start write request on the 
+// device side as soon as the AHB master puts data into the gizmos queue.  0 = start the device 
+// write request only when the  AHB master has placed all write data into the gizmos queue.
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_IMMEDIATE_SHIFT                     _MK_SHIFT_CONST(3)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_IMMEDIATE_FIELD                     (_MK_MASK_CONST(0x1) << AHB_GIZMO_AHB_XBAR_BRIDGE_0_IMMEDIATE_SHIFT)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_IMMEDIATE_RANGE                     3:3
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_IMMEDIATE_WOFFSET                   0x0
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_IMMEDIATE_DEFAULT                   _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_IMMEDIATE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_IMMEDIATE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_IMMEDIATE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_IMMEDIATE_DISABLE                   _MK_ENUM_CONST(0)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_IMMEDIATE_ENABLE                    _MK_ENUM_CONST(1)
+
+// AHB slave gizmo - Enable fast re-arbitration.  1 = allow AHB master re-arbitration as soon as 
+// the device returns one read data into the gizmos queue.  0 = allow AHB master re-arbitration 
+// only when the  device returns all read data into the gizmos queue.
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_ENB_FAST_REARBITRATE_SHIFT                  _MK_SHIFT_CONST(2)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_ENB_FAST_REARBITRATE_FIELD                  (_MK_MASK_CONST(0x1) << AHB_GIZMO_AHB_XBAR_BRIDGE_0_ENB_FAST_REARBITRATE_SHIFT)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_ENB_FAST_REARBITRATE_RANGE                  2:2
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_ENB_FAST_REARBITRATE_WOFFSET                        0x0
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_ENB_FAST_REARBITRATE_DEFAULT                        _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_ENB_FAST_REARBITRATE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_ENB_FAST_REARBITRATE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_ENB_FAST_REARBITRATE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_ENB_FAST_REARBITRATE_DISABLE                        _MK_ENUM_CONST(0)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_ENB_FAST_REARBITRATE_ENABLE                 _MK_ENUM_CONST(1)
+
+// AHB slave gizmo - Force all AHB transaction to single data request transaction.  
+// 1 = force to single data transaction always.  
+// 0 = dont force to single data  transaction.
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_FORCE_TO_AHB_SINGLE_SHIFT                   _MK_SHIFT_CONST(1)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_FORCE_TO_AHB_SINGLE_FIELD                   (_MK_MASK_CONST(0x1) << AHB_GIZMO_AHB_XBAR_BRIDGE_0_FORCE_TO_AHB_SINGLE_SHIFT)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_FORCE_TO_AHB_SINGLE_RANGE                   1:1
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_FORCE_TO_AHB_SINGLE_WOFFSET                 0x0
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_FORCE_TO_AHB_SINGLE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_FORCE_TO_AHB_SINGLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_FORCE_TO_AHB_SINGLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_FORCE_TO_AHB_SINGLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_FORCE_TO_AHB_SINGLE_NOT_SINGLE_DATA                 _MK_ENUM_CONST(0)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_FORCE_TO_AHB_SINGLE_SINGLE_DATA                     _MK_ENUM_CONST(1)
+
+// AHB slave gizmo - Enable splitting AHB transactions.  1 = enable 0 = disable
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_ENABLE_SPLIT_SHIFT                  _MK_SHIFT_CONST(0)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_ENABLE_SPLIT_FIELD                  (_MK_MASK_CONST(0x1) << AHB_GIZMO_AHB_XBAR_BRIDGE_0_ENABLE_SPLIT_SHIFT)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_ENABLE_SPLIT_RANGE                  0:0
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_ENABLE_SPLIT_WOFFSET                        0x0
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_ENABLE_SPLIT_DEFAULT                        _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_ENABLE_SPLIT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_ENABLE_SPLIT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_ENABLE_SPLIT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_ENABLE_SPLIT_DISABLE                        _MK_ENUM_CONST(0)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_ENABLE_SPLIT_ENABLE                 _MK_ENUM_CONST(1)
+
+
+// Register AHB_GIZMO_CPU_AHB_BRIDGE_0  
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0                      _MK_ADDR_CONST(0x24)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_WORD_COUNT                   0x1
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_RESET_VAL                    _MK_MASK_CONST(0x60000)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_RESET_MASK                   _MK_MASK_CONST(0xf0000)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_READ_MASK                    _MK_MASK_CONST(0xf0000)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_WRITE_MASK                   _MK_MASK_CONST(0xf0000)
+// AHB master gizmo - Pack all AHB read data.  1 = wait for all requested read data to be in the 
+// AHB gizmos queue before returning the data back to the IP.  0 = transfer each read data from 
+// the AHB to the IP  immediately.
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_RD_DATA_SHIFT                        _MK_SHIFT_CONST(19)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_RD_DATA_FIELD                        (_MK_MASK_CONST(0x1) << AHB_GIZMO_CPU_AHB_BRIDGE_0_RD_DATA_SHIFT)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_RD_DATA_RANGE                        19:19
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_RD_DATA_WOFFSET                      0x0
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_RD_DATA_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_RD_DATA_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_RD_DATA_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_RD_DATA_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_RD_DATA_NO_WAIT                      _MK_ENUM_CONST(0)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_RD_DATA_WAIT                 _MK_ENUM_CONST(1)
+
+// AHB master gizmo (AHB-DMA) - Start AHB write request immediately.  1 = start the AHB write 
+// request immediately as soon as the device  has put one write data in the AHB gizmos queue.  
+// 0 = start the AHB write request only when all the  write data has transferred from the 
+// device to the AHB gizmos queue.
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_IMMEDIATE_SHIFT                      _MK_SHIFT_CONST(18)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_IMMEDIATE_FIELD                      (_MK_MASK_CONST(0x1) << AHB_GIZMO_CPU_AHB_BRIDGE_0_IMMEDIATE_SHIFT)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_IMMEDIATE_RANGE                      18:18
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_IMMEDIATE_WOFFSET                    0x0
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_IMMEDIATE_DEFAULT                    _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_IMMEDIATE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_IMMEDIATE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_IMMEDIATE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_IMMEDIATE_DISABLE                    _MK_ENUM_CONST(0)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_IMMEDIATE_ENABLE                     _MK_ENUM_CONST(1)
+
+// AHB master gizmo - Maximum allowed AHB 
+// burst size.  
+// 00 = single transfer.  
+// 01 = burst-of-4.  
+// 10 = burst-of-8.  
+// 11 = burst-of-16.
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_SHIFT                      _MK_SHIFT_CONST(16)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_FIELD                      (_MK_MASK_CONST(0x3) << AHB_GIZMO_CPU_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_SHIFT)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_RANGE                      17:16
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_WOFFSET                    0x0
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_DEFAULT                    _MK_MASK_CONST(0x2)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_DMA_BURST_1WORDS                   _MK_ENUM_CONST(0)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_DMA_BURST_4WORDS                   _MK_ENUM_CONST(1)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_DMA_BURST_8WORDS                   _MK_ENUM_CONST(2)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_DMA_BURST_16WORDS                  _MK_ENUM_CONST(3)
+
+
+// Register AHB_GIZMO_COP_AHB_BRIDGE_0  
+#define AHB_GIZMO_COP_AHB_BRIDGE_0                      _MK_ADDR_CONST(0x28)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_WORD_COUNT                   0x1
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_RESET_VAL                    _MK_MASK_CONST(0x60000)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_RESET_MASK                   _MK_MASK_CONST(0xf0000)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_READ_MASK                    _MK_MASK_CONST(0xf0000)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_WRITE_MASK                   _MK_MASK_CONST(0xf0000)
+// AHB master gizmo - Pack all AHB read data.  1 = wait for all requested read data to be in the 
+// AHB gizmos queue before returning the data back to the IP.  0 = transfer each read data from 
+// the AHB to the IP  immediately.
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_RD_DATA_SHIFT                        _MK_SHIFT_CONST(19)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_RD_DATA_FIELD                        (_MK_MASK_CONST(0x1) << AHB_GIZMO_COP_AHB_BRIDGE_0_RD_DATA_SHIFT)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_RD_DATA_RANGE                        19:19
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_RD_DATA_WOFFSET                      0x0
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_RD_DATA_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_RD_DATA_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_RD_DATA_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_RD_DATA_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_RD_DATA_NO_WAIT                      _MK_ENUM_CONST(0)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_RD_DATA_WAIT                 _MK_ENUM_CONST(1)
+
+// AHB master gizmo (AHB-DMA) - Start AHB write request immediately.  1 = start the AHB write 
+// request immediately as soon as the device  has put one write data in the AHB gizmos queue.  
+// 0 = start the AHB write request only when all the  write data has transferred from the 
+// device to the AHB gizmos queue.
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_IMMEDIATE_SHIFT                      _MK_SHIFT_CONST(18)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_IMMEDIATE_FIELD                      (_MK_MASK_CONST(0x1) << AHB_GIZMO_COP_AHB_BRIDGE_0_IMMEDIATE_SHIFT)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_IMMEDIATE_RANGE                      18:18
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_IMMEDIATE_WOFFSET                    0x0
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_IMMEDIATE_DEFAULT                    _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_IMMEDIATE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_IMMEDIATE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_IMMEDIATE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_IMMEDIATE_DISABLE                    _MK_ENUM_CONST(0)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_IMMEDIATE_ENABLE                     _MK_ENUM_CONST(1)
+
+// AHB master gizmo - Maximum allowed AHB 
+// burst size.  
+// 00 = single transfer.  
+// 01 = burst-of-4.  
+// 10 = burst-of-8.  
+// 11 = burst-of-16.
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_SHIFT                      _MK_SHIFT_CONST(16)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_FIELD                      (_MK_MASK_CONST(0x3) << AHB_GIZMO_COP_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_SHIFT)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_RANGE                      17:16
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_WOFFSET                    0x0
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_DEFAULT                    _MK_MASK_CONST(0x2)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_DMA_BURST_1WORDS                   _MK_ENUM_CONST(0)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_DMA_BURST_4WORDS                   _MK_ENUM_CONST(1)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_DMA_BURST_8WORDS                   _MK_ENUM_CONST(2)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_DMA_BURST_16WORDS                  _MK_ENUM_CONST(3)
+
+
+// Register AHB_GIZMO_XBAR_APB_CTLR_0  
+#define AHB_GIZMO_XBAR_APB_CTLR_0                       _MK_ADDR_CONST(0x2c)
+#define AHB_GIZMO_XBAR_APB_CTLR_0_WORD_COUNT                    0x1
+#define AHB_GIZMO_XBAR_APB_CTLR_0_RESET_VAL                     _MK_MASK_CONST(0x8)
+#define AHB_GIZMO_XBAR_APB_CTLR_0_RESET_MASK                    _MK_MASK_CONST(0x38)
+#define AHB_GIZMO_XBAR_APB_CTLR_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_XBAR_APB_CTLR_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_XBAR_APB_CTLR_0_READ_MASK                     _MK_MASK_CONST(0x38)
+#define AHB_GIZMO_XBAR_APB_CTLR_0_WRITE_MASK                    _MK_MASK_CONST(0x38)
+// AHB slave gizmo - Maximum allowed IP 
+// burst size.  
+// 00 = single transfer.  
+// 01 = burst-of-4.  
+// 10 = burst-of-8.  
+// 11 = burst-of-16.
+#define AHB_GIZMO_XBAR_APB_CTLR_0_MAX_IP_BURSTSIZE_SHIFT                        _MK_SHIFT_CONST(4)
+#define AHB_GIZMO_XBAR_APB_CTLR_0_MAX_IP_BURSTSIZE_FIELD                        (_MK_MASK_CONST(0x3) << AHB_GIZMO_XBAR_APB_CTLR_0_MAX_IP_BURSTSIZE_SHIFT)
+#define AHB_GIZMO_XBAR_APB_CTLR_0_MAX_IP_BURSTSIZE_RANGE                        5:4
+#define AHB_GIZMO_XBAR_APB_CTLR_0_MAX_IP_BURSTSIZE_WOFFSET                      0x0
+#define AHB_GIZMO_XBAR_APB_CTLR_0_MAX_IP_BURSTSIZE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_XBAR_APB_CTLR_0_MAX_IP_BURSTSIZE_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define AHB_GIZMO_XBAR_APB_CTLR_0_MAX_IP_BURSTSIZE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_XBAR_APB_CTLR_0_MAX_IP_BURSTSIZE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_XBAR_APB_CTLR_0_MAX_IP_BURSTSIZE_DMA_BURST_1WORDS                     _MK_ENUM_CONST(0)
+#define AHB_GIZMO_XBAR_APB_CTLR_0_MAX_IP_BURSTSIZE_DMA_BURST_4WORDS                     _MK_ENUM_CONST(1)
+#define AHB_GIZMO_XBAR_APB_CTLR_0_MAX_IP_BURSTSIZE_DMA_BURST_8WORDS                     _MK_ENUM_CONST(2)
+#define AHB_GIZMO_XBAR_APB_CTLR_0_MAX_IP_BURSTSIZE_DMA_BURST_16WORDS                    _MK_ENUM_CONST(3)
+
+// AHB slave gizmo - Start write request to device immediately.  1 = start write request on 
+// the device side as soon as the AHB master puts data into the gizmos queue.  0 = start 
+// the device write request only when the  AHB master has placed all write data into the 
+// gizmos queue.
+#define AHB_GIZMO_XBAR_APB_CTLR_0_IMMEDIATE_SHIFT                       _MK_SHIFT_CONST(3)
+#define AHB_GIZMO_XBAR_APB_CTLR_0_IMMEDIATE_FIELD                       (_MK_MASK_CONST(0x1) << AHB_GIZMO_XBAR_APB_CTLR_0_IMMEDIATE_SHIFT)
+#define AHB_GIZMO_XBAR_APB_CTLR_0_IMMEDIATE_RANGE                       3:3
+#define AHB_GIZMO_XBAR_APB_CTLR_0_IMMEDIATE_WOFFSET                     0x0
+#define AHB_GIZMO_XBAR_APB_CTLR_0_IMMEDIATE_DEFAULT                     _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_XBAR_APB_CTLR_0_IMMEDIATE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_XBAR_APB_CTLR_0_IMMEDIATE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_XBAR_APB_CTLR_0_IMMEDIATE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_XBAR_APB_CTLR_0_IMMEDIATE_DISABLE                     _MK_ENUM_CONST(0)
+#define AHB_GIZMO_XBAR_APB_CTLR_0_IMMEDIATE_ENABLE                      _MK_ENUM_CONST(1)
+
+
+// Reserved address 48 [0x30] 
+
+// Reserved address 52 [0x34] 
+
+// Reserved address 56 [0x38] 
+
+// Register AHB_GIZMO_NAND_0  
+#define AHB_GIZMO_NAND_0                        _MK_ADDR_CONST(0x3c)
+#define AHB_GIZMO_NAND_0_WORD_COUNT                     0x1
+#define AHB_GIZMO_NAND_0_RESET_VAL                      _MK_MASK_CONST(0xa0000)
+#define AHB_GIZMO_NAND_0_RESET_MASK                     _MK_MASK_CONST(0xff0f0000)
+#define AHB_GIZMO_NAND_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_NAND_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_NAND_0_READ_MASK                      _MK_MASK_CONST(0xff0f0000)
+#define AHB_GIZMO_NAND_0_WRITE_MASK                     _MK_MASK_CONST(0xff0f0000)
+// AHB master request negate count. This is an 8-bit  counter use to indicate the minimum number of clk count 
+// between requests from  this AHB master.
+#define AHB_GIZMO_NAND_0_REQ_NEG_CNT_SHIFT                      _MK_SHIFT_CONST(24)
+#define AHB_GIZMO_NAND_0_REQ_NEG_CNT_FIELD                      (_MK_MASK_CONST(0xff) << AHB_GIZMO_NAND_0_REQ_NEG_CNT_SHIFT)
+#define AHB_GIZMO_NAND_0_REQ_NEG_CNT_RANGE                      31:24
+#define AHB_GIZMO_NAND_0_REQ_NEG_CNT_WOFFSET                    0x0
+#define AHB_GIZMO_NAND_0_REQ_NEG_CNT_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_NAND_0_REQ_NEG_CNT_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
+#define AHB_GIZMO_NAND_0_REQ_NEG_CNT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_NAND_0_REQ_NEG_CNT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// AHB master gizmo - Pack all AHB read data.  1 = wait for all requested read data to be 
+// in the AHB gizmos queue before returning the data back to the IP.  0 = transfer each read 
+// data from the AHB to the IP  immediately.
+#define AHB_GIZMO_NAND_0_RD_DATA_SHIFT                  _MK_SHIFT_CONST(19)
+#define AHB_GIZMO_NAND_0_RD_DATA_FIELD                  (_MK_MASK_CONST(0x1) << AHB_GIZMO_NAND_0_RD_DATA_SHIFT)
+#define AHB_GIZMO_NAND_0_RD_DATA_RANGE                  19:19
+#define AHB_GIZMO_NAND_0_RD_DATA_WOFFSET                        0x0
+#define AHB_GIZMO_NAND_0_RD_DATA_DEFAULT                        _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_NAND_0_RD_DATA_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_NAND_0_RD_DATA_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_NAND_0_RD_DATA_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_NAND_0_RD_DATA_NO_WAIT                        _MK_ENUM_CONST(0)
+#define AHB_GIZMO_NAND_0_RD_DATA_WAIT                   _MK_ENUM_CONST(1)
+
+// AHB master gizmo (AHB-DMA) - Start AHB write request immediately.  1 = start the AHB 
+// write request immediately as soon as the device  has put one write data in the AHB 
+// gizmos queue.  0 = start the AHB write request only when all the  write data has 
+// transferred from the device to the AHB gizmos queue.
+#define AHB_GIZMO_NAND_0_IMMEDIATE_SHIFT                        _MK_SHIFT_CONST(18)
+#define AHB_GIZMO_NAND_0_IMMEDIATE_FIELD                        (_MK_MASK_CONST(0x1) << AHB_GIZMO_NAND_0_IMMEDIATE_SHIFT)
+#define AHB_GIZMO_NAND_0_IMMEDIATE_RANGE                        18:18
+#define AHB_GIZMO_NAND_0_IMMEDIATE_WOFFSET                      0x0
+#define AHB_GIZMO_NAND_0_IMMEDIATE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_NAND_0_IMMEDIATE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_NAND_0_IMMEDIATE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_NAND_0_IMMEDIATE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_NAND_0_IMMEDIATE_DISABLE                      _MK_ENUM_CONST(0)
+#define AHB_GIZMO_NAND_0_IMMEDIATE_ENABLE                       _MK_ENUM_CONST(1)
+
+// AHB master gizmo - Maximum allowed 
+// AHB burst size.  
+// 00 = single transfer.  
+// 01 = burst-of-4.  
+// 10 = burst-of-8.  
+// 11 = burst-of-16.
+#define AHB_GIZMO_NAND_0_MAX_AHB_BURSTSIZE_SHIFT                        _MK_SHIFT_CONST(16)
+#define AHB_GIZMO_NAND_0_MAX_AHB_BURSTSIZE_FIELD                        (_MK_MASK_CONST(0x3) << AHB_GIZMO_NAND_0_MAX_AHB_BURSTSIZE_SHIFT)
+#define AHB_GIZMO_NAND_0_MAX_AHB_BURSTSIZE_RANGE                        17:16
+#define AHB_GIZMO_NAND_0_MAX_AHB_BURSTSIZE_WOFFSET                      0x0
+#define AHB_GIZMO_NAND_0_MAX_AHB_BURSTSIZE_DEFAULT                      _MK_MASK_CONST(0x2)
+#define AHB_GIZMO_NAND_0_MAX_AHB_BURSTSIZE_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define AHB_GIZMO_NAND_0_MAX_AHB_BURSTSIZE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_NAND_0_MAX_AHB_BURSTSIZE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_NAND_0_MAX_AHB_BURSTSIZE_DMA_BURST_1WORDS                     _MK_ENUM_CONST(0)
+#define AHB_GIZMO_NAND_0_MAX_AHB_BURSTSIZE_DMA_BURST_4WORDS                     _MK_ENUM_CONST(1)
+#define AHB_GIZMO_NAND_0_MAX_AHB_BURSTSIZE_DMA_BURST_8WORDS                     _MK_ENUM_CONST(2)
+#define AHB_GIZMO_NAND_0_MAX_AHB_BURSTSIZE_DMA_BURST_16WORDS                    _MK_ENUM_CONST(3)
+
+
+// Reserved address 64 [0x40] 
+
+// Register AHB_GIZMO_HSMMC1_0  
+#define AHB_GIZMO_HSMMC1_0                      _MK_ADDR_CONST(0x44)
+#define AHB_GIZMO_HSMMC1_0_WORD_COUNT                   0x1
+#define AHB_GIZMO_HSMMC1_0_RESET_VAL                    _MK_MASK_CONST(0x40000)
+#define AHB_GIZMO_HSMMC1_0_RESET_MASK                   _MK_MASK_CONST(0xff040000)
+#define AHB_GIZMO_HSMMC1_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_HSMMC1_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_HSMMC1_0_READ_MASK                    _MK_MASK_CONST(0xff040000)
+#define AHB_GIZMO_HSMMC1_0_WRITE_MASK                   _MK_MASK_CONST(0xff040000)
+// AHB master request negate count. This is an 8-bit  counter use to indicate the minimum number of clk count 
+// between requests from  this AHB master.
+#define AHB_GIZMO_HSMMC1_0_REQ_NEG_CNT_SHIFT                    _MK_SHIFT_CONST(24)
+#define AHB_GIZMO_HSMMC1_0_REQ_NEG_CNT_FIELD                    (_MK_MASK_CONST(0xff) << AHB_GIZMO_HSMMC1_0_REQ_NEG_CNT_SHIFT)
+#define AHB_GIZMO_HSMMC1_0_REQ_NEG_CNT_RANGE                    31:24
+#define AHB_GIZMO_HSMMC1_0_REQ_NEG_CNT_WOFFSET                  0x0
+#define AHB_GIZMO_HSMMC1_0_REQ_NEG_CNT_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_HSMMC1_0_REQ_NEG_CNT_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
+#define AHB_GIZMO_HSMMC1_0_REQ_NEG_CNT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_HSMMC1_0_REQ_NEG_CNT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// AHB master gizmo (AHB-DMA) - Start AHB write request immediately.  1 = start the AHB 
+// write request immediately as soon as the device  has put one write data in the AHB 
+// gizmos queue.  0 = start the AHB write request only when all the  write data has 
+// transferred from the device to the AHB gizmos queue.
+#define AHB_GIZMO_HSMMC1_0_IMMEDIATE_SHIFT                      _MK_SHIFT_CONST(18)
+#define AHB_GIZMO_HSMMC1_0_IMMEDIATE_FIELD                      (_MK_MASK_CONST(0x1) << AHB_GIZMO_HSMMC1_0_IMMEDIATE_SHIFT)
+#define AHB_GIZMO_HSMMC1_0_IMMEDIATE_RANGE                      18:18
+#define AHB_GIZMO_HSMMC1_0_IMMEDIATE_WOFFSET                    0x0
+#define AHB_GIZMO_HSMMC1_0_IMMEDIATE_DEFAULT                    _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_HSMMC1_0_IMMEDIATE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_HSMMC1_0_IMMEDIATE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_HSMMC1_0_IMMEDIATE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_HSMMC1_0_IMMEDIATE_DISABLE                    _MK_ENUM_CONST(0)
+#define AHB_GIZMO_HSMMC1_0_IMMEDIATE_ENABLE                     _MK_ENUM_CONST(1)
+
+
+// Register AHB_GIZMO_XIO_0  
+#define AHB_GIZMO_XIO_0                 _MK_ADDR_CONST(0x48)
+#define AHB_GIZMO_XIO_0_WORD_COUNT                      0x1
+#define AHB_GIZMO_XIO_0_RESET_VAL                       _MK_MASK_CONST(0x40000)
+#define AHB_GIZMO_XIO_0_RESET_MASK                      _MK_MASK_CONST(0xff0f0000)
+#define AHB_GIZMO_XIO_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_XIO_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_XIO_0_READ_MASK                       _MK_MASK_CONST(0xff0f0000)
+#define AHB_GIZMO_XIO_0_WRITE_MASK                      _MK_MASK_CONST(0xff0f0000)
+// AHB master request negate count. This is an 8-bit  counter use to indicate the minimum number of clk count 
+// between requests from  this AHB master.
+#define AHB_GIZMO_XIO_0_REQ_NEG_CNT_SHIFT                       _MK_SHIFT_CONST(24)
+#define AHB_GIZMO_XIO_0_REQ_NEG_CNT_FIELD                       (_MK_MASK_CONST(0xff) << AHB_GIZMO_XIO_0_REQ_NEG_CNT_SHIFT)
+#define AHB_GIZMO_XIO_0_REQ_NEG_CNT_RANGE                       31:24
+#define AHB_GIZMO_XIO_0_REQ_NEG_CNT_WOFFSET                     0x0
+#define AHB_GIZMO_XIO_0_REQ_NEG_CNT_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_XIO_0_REQ_NEG_CNT_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define AHB_GIZMO_XIO_0_REQ_NEG_CNT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_XIO_0_REQ_NEG_CNT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// AHB master gizmo - Pack all AHB read data.  1 = wait for all requested read data to be 
+// in the AHB gizmos queue before returning the data back to the IP.  0 = transfer each read 
+// data from the AHB to the IP  immediately.
+#define AHB_GIZMO_XIO_0_RD_DATA_SHIFT                   _MK_SHIFT_CONST(19)
+#define AHB_GIZMO_XIO_0_RD_DATA_FIELD                   (_MK_MASK_CONST(0x1) << AHB_GIZMO_XIO_0_RD_DATA_SHIFT)
+#define AHB_GIZMO_XIO_0_RD_DATA_RANGE                   19:19
+#define AHB_GIZMO_XIO_0_RD_DATA_WOFFSET                 0x0
+#define AHB_GIZMO_XIO_0_RD_DATA_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_XIO_0_RD_DATA_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_XIO_0_RD_DATA_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_XIO_0_RD_DATA_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_XIO_0_RD_DATA_NO_WAIT                 _MK_ENUM_CONST(0)
+#define AHB_GIZMO_XIO_0_RD_DATA_WAIT                    _MK_ENUM_CONST(1)
+
+// AHB master gizmo (AHB-DMA) - Start AHB write request immediately.  1 = start the AHB 
+// write request immediately as soon as the device  has put one write data in the AHB 
+// gizmos queue.  0 = start the AHB write request only when all the  write data has 
+// transferred from the device to the AHB gizmos queue.
+#define AHB_GIZMO_XIO_0_IMMEDIATE_SHIFT                 _MK_SHIFT_CONST(18)
+#define AHB_GIZMO_XIO_0_IMMEDIATE_FIELD                 (_MK_MASK_CONST(0x1) << AHB_GIZMO_XIO_0_IMMEDIATE_SHIFT)
+#define AHB_GIZMO_XIO_0_IMMEDIATE_RANGE                 18:18
+#define AHB_GIZMO_XIO_0_IMMEDIATE_WOFFSET                       0x0
+#define AHB_GIZMO_XIO_0_IMMEDIATE_DEFAULT                       _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_XIO_0_IMMEDIATE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_XIO_0_IMMEDIATE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_XIO_0_IMMEDIATE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_XIO_0_IMMEDIATE_DISABLE                       _MK_ENUM_CONST(0)
+#define AHB_GIZMO_XIO_0_IMMEDIATE_ENABLE                        _MK_ENUM_CONST(1)
+
+// AHB master gizmo - Maximum allowed 
+// AHB burst size.  
+// 00 = single transfer.  
+// 01 = burst-of-4.  
+// 10 = burst-of-8.  
+// 11 = burst-of-16.
+#define AHB_GIZMO_XIO_0_MAX_AHB_BURSTSIZE_SHIFT                 _MK_SHIFT_CONST(16)
+#define AHB_GIZMO_XIO_0_MAX_AHB_BURSTSIZE_FIELD                 (_MK_MASK_CONST(0x3) << AHB_GIZMO_XIO_0_MAX_AHB_BURSTSIZE_SHIFT)
+#define AHB_GIZMO_XIO_0_MAX_AHB_BURSTSIZE_RANGE                 17:16
+#define AHB_GIZMO_XIO_0_MAX_AHB_BURSTSIZE_WOFFSET                       0x0
+#define AHB_GIZMO_XIO_0_MAX_AHB_BURSTSIZE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_XIO_0_MAX_AHB_BURSTSIZE_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define AHB_GIZMO_XIO_0_MAX_AHB_BURSTSIZE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_XIO_0_MAX_AHB_BURSTSIZE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_XIO_0_MAX_AHB_BURSTSIZE_DMA_BURST_1WORDS                      _MK_ENUM_CONST(0)
+#define AHB_GIZMO_XIO_0_MAX_AHB_BURSTSIZE_DMA_BURST_4WORDS                      _MK_ENUM_CONST(1)
+#define AHB_GIZMO_XIO_0_MAX_AHB_BURSTSIZE_DMA_BURST_8WORDS                      _MK_ENUM_CONST(2)
+#define AHB_GIZMO_XIO_0_MAX_AHB_BURSTSIZE_DMA_BURST_16WORDS                     _MK_ENUM_CONST(3)
+
+
+// Reserved address 76 [0x4c] 
+
+// Reserved address 80 [0x50] 
+
+// Reserved address 84 [0x54] 
+
+// Reserved address 88 [0x58] 
+
+// Reserved address 92 [0x5c] 
+
+// Register AHB_GIZMO_BSEV_0  
+#define AHB_GIZMO_BSEV_0                        _MK_ADDR_CONST(0x60)
+#define AHB_GIZMO_BSEV_0_WORD_COUNT                     0x1
+#define AHB_GIZMO_BSEV_0_RESET_VAL                      _MK_MASK_CONST(0x20000)
+#define AHB_GIZMO_BSEV_0_RESET_MASK                     _MK_MASK_CONST(0xff0f0000)
+#define AHB_GIZMO_BSEV_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_BSEV_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_BSEV_0_READ_MASK                      _MK_MASK_CONST(0xff0f0000)
+#define AHB_GIZMO_BSEV_0_WRITE_MASK                     _MK_MASK_CONST(0xff0f0000)
+// AHB master request negate count. This is an 8-bit  counter use to indicate the minimum number of clk count 
+// between requests from  this AHB master.
+#define AHB_GIZMO_BSEV_0_REQ_NEG_CNT_SHIFT                      _MK_SHIFT_CONST(24)
+#define AHB_GIZMO_BSEV_0_REQ_NEG_CNT_FIELD                      (_MK_MASK_CONST(0xff) << AHB_GIZMO_BSEV_0_REQ_NEG_CNT_SHIFT)
+#define AHB_GIZMO_BSEV_0_REQ_NEG_CNT_RANGE                      31:24
+#define AHB_GIZMO_BSEV_0_REQ_NEG_CNT_WOFFSET                    0x0
+#define AHB_GIZMO_BSEV_0_REQ_NEG_CNT_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_BSEV_0_REQ_NEG_CNT_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
+#define AHB_GIZMO_BSEV_0_REQ_NEG_CNT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_BSEV_0_REQ_NEG_CNT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// AHB master gizmo - Pack all AHB read data.  1 = wait for all requested read data to be 
+// in the AHB gizmos queue before returning the data back to the IP.  0 = transfer each read 
+// data from the AHB to the IP  immediately.
+#define AHB_GIZMO_BSEV_0_RD_DATA_SHIFT                  _MK_SHIFT_CONST(19)
+#define AHB_GIZMO_BSEV_0_RD_DATA_FIELD                  (_MK_MASK_CONST(0x1) << AHB_GIZMO_BSEV_0_RD_DATA_SHIFT)
+#define AHB_GIZMO_BSEV_0_RD_DATA_RANGE                  19:19
+#define AHB_GIZMO_BSEV_0_RD_DATA_WOFFSET                        0x0
+#define AHB_GIZMO_BSEV_0_RD_DATA_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_BSEV_0_RD_DATA_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_BSEV_0_RD_DATA_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_BSEV_0_RD_DATA_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_BSEV_0_RD_DATA_NO_WAIT                        _MK_ENUM_CONST(0)
+#define AHB_GIZMO_BSEV_0_RD_DATA_WAIT                   _MK_ENUM_CONST(1)
+
+// AHB master gizmo (AHB-DMA) - Start AHB write request immediately.  1 = start the AHB 
+// write request immediately as soon as the device  has put one write data in the AHB 
+// gizmos queue.  0 = start the AHB write request only when all the  write data has 
+// transferred from the device to the AHB gizmos queue. !!THIS SHOULD NEVER BE SET TO 
+// ENABLE!! (BSEV requires this bit to be 0) 
+#define AHB_GIZMO_BSEV_0_IMMEDIATE_SHIFT                        _MK_SHIFT_CONST(18)
+#define AHB_GIZMO_BSEV_0_IMMEDIATE_FIELD                        (_MK_MASK_CONST(0x1) << AHB_GIZMO_BSEV_0_IMMEDIATE_SHIFT)
+#define AHB_GIZMO_BSEV_0_IMMEDIATE_RANGE                        18:18
+#define AHB_GIZMO_BSEV_0_IMMEDIATE_WOFFSET                      0x0
+#define AHB_GIZMO_BSEV_0_IMMEDIATE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_BSEV_0_IMMEDIATE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_BSEV_0_IMMEDIATE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_BSEV_0_IMMEDIATE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_BSEV_0_IMMEDIATE_DISABLE                      _MK_ENUM_CONST(0)
+#define AHB_GIZMO_BSEV_0_IMMEDIATE_ENABLE                       _MK_ENUM_CONST(1)
+
+// AHB master gizmo - Maximum 
+// allowed AHB burst size.  
+// 00 = single transfer.  
+// 01 = burst-of-4.  
+// 10 = burst-of-8.
+// 11 = burst-of-16.
+#define AHB_GIZMO_BSEV_0_MAX_AHB_BURSTSIZE_SHIFT                        _MK_SHIFT_CONST(16)
+#define AHB_GIZMO_BSEV_0_MAX_AHB_BURSTSIZE_FIELD                        (_MK_MASK_CONST(0x3) << AHB_GIZMO_BSEV_0_MAX_AHB_BURSTSIZE_SHIFT)
+#define AHB_GIZMO_BSEV_0_MAX_AHB_BURSTSIZE_RANGE                        17:16
+#define AHB_GIZMO_BSEV_0_MAX_AHB_BURSTSIZE_WOFFSET                      0x0
+#define AHB_GIZMO_BSEV_0_MAX_AHB_BURSTSIZE_DEFAULT                      _MK_MASK_CONST(0x2)
+#define AHB_GIZMO_BSEV_0_MAX_AHB_BURSTSIZE_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define AHB_GIZMO_BSEV_0_MAX_AHB_BURSTSIZE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_BSEV_0_MAX_AHB_BURSTSIZE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_BSEV_0_MAX_AHB_BURSTSIZE_DMA_BURST_1WORDS                     _MK_ENUM_CONST(0)
+#define AHB_GIZMO_BSEV_0_MAX_AHB_BURSTSIZE_DMA_BURST_4WORDS                     _MK_ENUM_CONST(1)
+#define AHB_GIZMO_BSEV_0_MAX_AHB_BURSTSIZE_DMA_BURST_8WORDS                     _MK_ENUM_CONST(2)
+#define AHB_GIZMO_BSEV_0_MAX_AHB_BURSTSIZE_DMA_BURST_16WORDS                    _MK_ENUM_CONST(3)
+
+
+// Reserved address 100 [0x64] 
+
+// Reserved address 104 [0x68] 
+
+// Reserved address 108 [0x6c] 
+
+// Register AHB_GIZMO_BSEA_0  
+#define AHB_GIZMO_BSEA_0                        _MK_ADDR_CONST(0x70)
+#define AHB_GIZMO_BSEA_0_WORD_COUNT                     0x1
+#define AHB_GIZMO_BSEA_0_RESET_VAL                      _MK_MASK_CONST(0x20000)
+#define AHB_GIZMO_BSEA_0_RESET_MASK                     _MK_MASK_CONST(0xff070000)
+#define AHB_GIZMO_BSEA_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_BSEA_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_BSEA_0_READ_MASK                      _MK_MASK_CONST(0xff070000)
+#define AHB_GIZMO_BSEA_0_WRITE_MASK                     _MK_MASK_CONST(0xff070000)
+// AHB master request negate count. This is an 8-bit  counter use to indicate the minimum number of clk count 
+// between requests from  this AHB master.
+#define AHB_GIZMO_BSEA_0_REQ_NEG_CNT_SHIFT                      _MK_SHIFT_CONST(24)
+#define AHB_GIZMO_BSEA_0_REQ_NEG_CNT_FIELD                      (_MK_MASK_CONST(0xff) << AHB_GIZMO_BSEA_0_REQ_NEG_CNT_SHIFT)
+#define AHB_GIZMO_BSEA_0_REQ_NEG_CNT_RANGE                      31:24
+#define AHB_GIZMO_BSEA_0_REQ_NEG_CNT_WOFFSET                    0x0
+#define AHB_GIZMO_BSEA_0_REQ_NEG_CNT_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_BSEA_0_REQ_NEG_CNT_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
+#define AHB_GIZMO_BSEA_0_REQ_NEG_CNT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_BSEA_0_REQ_NEG_CNT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// AHB master gizmo - Start AHB write request immediately.  1 = start the AHB 
+// write request immediately as soon as the device puts data in the AHB gizmos 
+// queue.  0 = start the AHB write request only when all the  write data has 
+// transferred from the device to the AHB gizmos queue.  !!THIS SHOULD NEVER BE 
+// SET TO ENABLE!! (BSEV requires this bit to be 0) 
+#define AHB_GIZMO_BSEA_0_IMMEDIATE_SHIFT                        _MK_SHIFT_CONST(18)
+#define AHB_GIZMO_BSEA_0_IMMEDIATE_FIELD                        (_MK_MASK_CONST(0x1) << AHB_GIZMO_BSEA_0_IMMEDIATE_SHIFT)
+#define AHB_GIZMO_BSEA_0_IMMEDIATE_RANGE                        18:18
+#define AHB_GIZMO_BSEA_0_IMMEDIATE_WOFFSET                      0x0
+#define AHB_GIZMO_BSEA_0_IMMEDIATE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_BSEA_0_IMMEDIATE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_BSEA_0_IMMEDIATE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_BSEA_0_IMMEDIATE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_BSEA_0_IMMEDIATE_DISABLE                      _MK_ENUM_CONST(0)
+#define AHB_GIZMO_BSEA_0_IMMEDIATE_ENABLE                       _MK_ENUM_CONST(1)
+
+// AHB master gizmo - Maximum 
+// allowed AHB burst size.  
+// 00 = single transfer.  
+// 01 = burst-of-4.  
+// 10 = burst-of-8.  
+// 11 = burst-of-16.
+#define AHB_GIZMO_BSEA_0_MAX_AHB_BURSTSIZE_SHIFT                        _MK_SHIFT_CONST(16)
+#define AHB_GIZMO_BSEA_0_MAX_AHB_BURSTSIZE_FIELD                        (_MK_MASK_CONST(0x3) << AHB_GIZMO_BSEA_0_MAX_AHB_BURSTSIZE_SHIFT)
+#define AHB_GIZMO_BSEA_0_MAX_AHB_BURSTSIZE_RANGE                        17:16
+#define AHB_GIZMO_BSEA_0_MAX_AHB_BURSTSIZE_WOFFSET                      0x0
+#define AHB_GIZMO_BSEA_0_MAX_AHB_BURSTSIZE_DEFAULT                      _MK_MASK_CONST(0x2)
+#define AHB_GIZMO_BSEA_0_MAX_AHB_BURSTSIZE_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define AHB_GIZMO_BSEA_0_MAX_AHB_BURSTSIZE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_BSEA_0_MAX_AHB_BURSTSIZE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_BSEA_0_MAX_AHB_BURSTSIZE_DMA_BURST_1WORDS                     _MK_ENUM_CONST(0)
+#define AHB_GIZMO_BSEA_0_MAX_AHB_BURSTSIZE_DMA_BURST_4WORDS                     _MK_ENUM_CONST(1)
+#define AHB_GIZMO_BSEA_0_MAX_AHB_BURSTSIZE_DMA_BURST_8WORDS                     _MK_ENUM_CONST(2)
+#define AHB_GIZMO_BSEA_0_MAX_AHB_BURSTSIZE_DMA_BURST_16WORDS                    _MK_ENUM_CONST(3)
+
+
+// Register AHB_GIZMO_NOR_0  
+#define AHB_GIZMO_NOR_0                 _MK_ADDR_CONST(0x74)
+#define AHB_GIZMO_NOR_0_WORD_COUNT                      0x1
+#define AHB_GIZMO_NOR_0_RESET_VAL                       _MK_MASK_CONST(0x85)
+#define AHB_GIZMO_NOR_0_RESET_MASK                      _MK_MASK_CONST(0xc7)
+#define AHB_GIZMO_NOR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_NOR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_NOR_0_READ_MASK                       _MK_MASK_CONST(0xc7)
+#define AHB_GIZMO_NOR_0_WRITE_MASK                      _MK_MASK_CONST(0xc7)
+// AHB slave gizmo - Dont split AHB write transaction.  1 = dont split AHB 
+// write transaction ever. 0 (and enable_split=1) = allow AHB write  
+// transaction to be split.
+#define AHB_GIZMO_NOR_0_DONT_SPLIT_AHB_WR_SHIFT                 _MK_SHIFT_CONST(7)
+#define AHB_GIZMO_NOR_0_DONT_SPLIT_AHB_WR_FIELD                 (_MK_MASK_CONST(0x1) << AHB_GIZMO_NOR_0_DONT_SPLIT_AHB_WR_SHIFT)
+#define AHB_GIZMO_NOR_0_DONT_SPLIT_AHB_WR_RANGE                 7:7
+#define AHB_GIZMO_NOR_0_DONT_SPLIT_AHB_WR_WOFFSET                       0x0
+#define AHB_GIZMO_NOR_0_DONT_SPLIT_AHB_WR_DEFAULT                       _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_NOR_0_DONT_SPLIT_AHB_WR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_NOR_0_DONT_SPLIT_AHB_WR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_NOR_0_DONT_SPLIT_AHB_WR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_NOR_0_DONT_SPLIT_AHB_WR_ENABLE                        _MK_ENUM_CONST(0)
+#define AHB_GIZMO_NOR_0_DONT_SPLIT_AHB_WR_DISABLE                       _MK_ENUM_CONST(1)
+
+// AHB slave gizmo - Accept AHB write request always.  
+// 1 = always accept AHB write request without checking whether 
+// there is room in the queue to store the write data. 0 = accept 
+// AHB write request only when theres  enough room in the queue 
+// to store all the write data.
+#define AHB_GIZMO_NOR_0_ACCEPT_AHB_WR_ALWAYS_SHIFT                      _MK_SHIFT_CONST(6)
+#define AHB_GIZMO_NOR_0_ACCEPT_AHB_WR_ALWAYS_FIELD                      (_MK_MASK_CONST(0x1) << AHB_GIZMO_NOR_0_ACCEPT_AHB_WR_ALWAYS_SHIFT)
+#define AHB_GIZMO_NOR_0_ACCEPT_AHB_WR_ALWAYS_RANGE                      6:6
+#define AHB_GIZMO_NOR_0_ACCEPT_AHB_WR_ALWAYS_WOFFSET                    0x0
+#define AHB_GIZMO_NOR_0_ACCEPT_AHB_WR_ALWAYS_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_NOR_0_ACCEPT_AHB_WR_ALWAYS_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_NOR_0_ACCEPT_AHB_WR_ALWAYS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_NOR_0_ACCEPT_AHB_WR_ALWAYS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_NOR_0_ACCEPT_AHB_WR_ALWAYS_ACCEPT_ON_CHECK                    _MK_ENUM_CONST(0)
+#define AHB_GIZMO_NOR_0_ACCEPT_AHB_WR_ALWAYS_ACCEPT_ON_NOCHECK                  _MK_ENUM_CONST(1)
+
+// AHB slave gizmo - Enable fast re-arbitration.  1 = allow AHB master 
+// re-arbitration as soon as the device returns one read data into the gizmos 
+// queue.  0 = allow AHB master re-arbitration only when the  device returns all 
+// read data into the gizmos queue.
+#define AHB_GIZMO_NOR_0_ENB_FAST_REARBITRATE_SHIFT                      _MK_SHIFT_CONST(2)
+#define AHB_GIZMO_NOR_0_ENB_FAST_REARBITRATE_FIELD                      (_MK_MASK_CONST(0x1) << AHB_GIZMO_NOR_0_ENB_FAST_REARBITRATE_SHIFT)
+#define AHB_GIZMO_NOR_0_ENB_FAST_REARBITRATE_RANGE                      2:2
+#define AHB_GIZMO_NOR_0_ENB_FAST_REARBITRATE_WOFFSET                    0x0
+#define AHB_GIZMO_NOR_0_ENB_FAST_REARBITRATE_DEFAULT                    _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_NOR_0_ENB_FAST_REARBITRATE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_NOR_0_ENB_FAST_REARBITRATE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_NOR_0_ENB_FAST_REARBITRATE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_NOR_0_ENB_FAST_REARBITRATE_DISABLE                    _MK_ENUM_CONST(0)
+#define AHB_GIZMO_NOR_0_ENB_FAST_REARBITRATE_ENABLE                     _MK_ENUM_CONST(1)
+
+// AHB slave gizmo - Force all AHB transaction to single data request 
+// transaction.  1 = force to single data transaction always.  
+// 0 = dont force to single data  transaction.
+#define AHB_GIZMO_NOR_0_FORCE_TO_AHB_SINGLE_SHIFT                       _MK_SHIFT_CONST(1)
+#define AHB_GIZMO_NOR_0_FORCE_TO_AHB_SINGLE_FIELD                       (_MK_MASK_CONST(0x1) << AHB_GIZMO_NOR_0_FORCE_TO_AHB_SINGLE_SHIFT)
+#define AHB_GIZMO_NOR_0_FORCE_TO_AHB_SINGLE_RANGE                       1:1
+#define AHB_GIZMO_NOR_0_FORCE_TO_AHB_SINGLE_WOFFSET                     0x0
+#define AHB_GIZMO_NOR_0_FORCE_TO_AHB_SINGLE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_NOR_0_FORCE_TO_AHB_SINGLE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_NOR_0_FORCE_TO_AHB_SINGLE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_NOR_0_FORCE_TO_AHB_SINGLE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_NOR_0_FORCE_TO_AHB_SINGLE_NOT_SINGLE_DATA                     _MK_ENUM_CONST(0)
+#define AHB_GIZMO_NOR_0_FORCE_TO_AHB_SINGLE_SINGLE_DATA                 _MK_ENUM_CONST(1)
+
+// AHB slave gizmo - Enable splitting AHB transactions.  1 = enable 0 = disable
+#define AHB_GIZMO_NOR_0_ENABLE_SPLIT_SHIFT                      _MK_SHIFT_CONST(0)
+#define AHB_GIZMO_NOR_0_ENABLE_SPLIT_FIELD                      (_MK_MASK_CONST(0x1) << AHB_GIZMO_NOR_0_ENABLE_SPLIT_SHIFT)
+#define AHB_GIZMO_NOR_0_ENABLE_SPLIT_RANGE                      0:0
+#define AHB_GIZMO_NOR_0_ENABLE_SPLIT_WOFFSET                    0x0
+#define AHB_GIZMO_NOR_0_ENABLE_SPLIT_DEFAULT                    _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_NOR_0_ENABLE_SPLIT_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_NOR_0_ENABLE_SPLIT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_NOR_0_ENABLE_SPLIT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_NOR_0_ENABLE_SPLIT_DISABLE                    _MK_ENUM_CONST(0)
+#define AHB_GIZMO_NOR_0_ENABLE_SPLIT_ENABLE                     _MK_ENUM_CONST(1)
+
+
+// Reserved address 120 [0x78] 
+
+// Reserved address 124 [0x7c] 
+
+// Reserved address 128 [0x80] 
+
+// Reserved address 132 [0x84] 
+
+// Reserved address 136 [0x88] 
+
+// Reserved address 140 [0x8c] 
+
+// Reserved address 144 [0x90] 
+
+// Reserved address 148 [0x94] 
+
+// Reserved address 152 [0x98] 
+
+// Reserved address 156 [0x9c] 
+
+// Reserved address 160 [0xa0] 
+
+// Reserved address 164 [0xa4] 
+
+// Reserved address 168 [0xa8] 
+
+// Reserved address 172 [0xac] 
+
+// Reserved address 176 [0xb0] 
+
+// Reserved address 180 [0xb4] 
+
+// Reserved address 184 [0xb8] 
+
+// Reserved address 188 [0xbc] 
+
+// Reserved address 192 [0xc0] 
+
+// Reserved address 196 [0xc4] 
+
+// Reserved address 200 [0xc8] 
+
+// Reserved address 204 [0xcc] 
+
+// Reserved address 208 [0xd0] 
+
+// Reserved address 212 [0xd4] 
+
+// Reserved address 216 [0xd8] 
+
+// Register AHB_ARBITRATION_XBAR_CTRL_0  
+#define AHB_ARBITRATION_XBAR_CTRL_0                     _MK_ADDR_CONST(0xdc)
+#define AHB_ARBITRATION_XBAR_CTRL_0_WORD_COUNT                  0x1
+#define AHB_ARBITRATION_XBAR_CTRL_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_XBAR_CTRL_0_RESET_MASK                  _MK_MASK_CONST(0x10003)
+#define AHB_ARBITRATION_XBAR_CTRL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_XBAR_CTRL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_XBAR_CTRL_0_READ_MASK                   _MK_MASK_CONST(0x10003)
+#define AHB_ARBITRATION_XBAR_CTRL_0_WRITE_MASK                  _MK_MASK_CONST(0x10003)
+// SW should set this bit when memory has been initialized
+#define AHB_ARBITRATION_XBAR_CTRL_0_MEM_INIT_DONE_SHIFT                 _MK_SHIFT_CONST(16)
+#define AHB_ARBITRATION_XBAR_CTRL_0_MEM_INIT_DONE_FIELD                 (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_XBAR_CTRL_0_MEM_INIT_DONE_SHIFT)
+#define AHB_ARBITRATION_XBAR_CTRL_0_MEM_INIT_DONE_RANGE                 16:16
+#define AHB_ARBITRATION_XBAR_CTRL_0_MEM_INIT_DONE_WOFFSET                       0x0
+#define AHB_ARBITRATION_XBAR_CTRL_0_MEM_INIT_DONE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_XBAR_CTRL_0_MEM_INIT_DONE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_XBAR_CTRL_0_MEM_INIT_DONE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_XBAR_CTRL_0_MEM_INIT_DONE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_XBAR_CTRL_0_MEM_INIT_DONE_NOT_DONE                      _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_XBAR_CTRL_0_MEM_INIT_DONE_DONE                  _MK_ENUM_CONST(1)
+
+// By default CPU accesses to IRAMs will be held if  there are any pending requests from the AHB to the 
+// IRAMs. This is done to  avoid data coherency issues. If SW handles coherency then this can be turned  
+// off to improve performance.SW writes to modify
+#define AHB_ARBITRATION_XBAR_CTRL_0_HOLD_DIS_SHIFT                      _MK_SHIFT_CONST(1)
+#define AHB_ARBITRATION_XBAR_CTRL_0_HOLD_DIS_FIELD                      (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_XBAR_CTRL_0_HOLD_DIS_SHIFT)
+#define AHB_ARBITRATION_XBAR_CTRL_0_HOLD_DIS_RANGE                      1:1
+#define AHB_ARBITRATION_XBAR_CTRL_0_HOLD_DIS_WOFFSET                    0x0
+#define AHB_ARBITRATION_XBAR_CTRL_0_HOLD_DIS_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_XBAR_CTRL_0_HOLD_DIS_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_XBAR_CTRL_0_HOLD_DIS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_XBAR_CTRL_0_HOLD_DIS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_XBAR_CTRL_0_HOLD_DIS_ENABLE                     _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_XBAR_CTRL_0_HOLD_DIS_DISABLE                    _MK_ENUM_CONST(1)
+
+// SW writes to modify
+#define AHB_ARBITRATION_XBAR_CTRL_0_POST_DIS_SHIFT                      _MK_SHIFT_CONST(0)
+#define AHB_ARBITRATION_XBAR_CTRL_0_POST_DIS_FIELD                      (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_XBAR_CTRL_0_POST_DIS_SHIFT)
+#define AHB_ARBITRATION_XBAR_CTRL_0_POST_DIS_RANGE                      0:0
+#define AHB_ARBITRATION_XBAR_CTRL_0_POST_DIS_WOFFSET                    0x0
+#define AHB_ARBITRATION_XBAR_CTRL_0_POST_DIS_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_XBAR_CTRL_0_POST_DIS_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_XBAR_CTRL_0_POST_DIS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_XBAR_CTRL_0_POST_DIS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_XBAR_CTRL_0_POST_DIS_ENABLE                     _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_XBAR_CTRL_0_POST_DIS_DISABLE                    _MK_ENUM_CONST(1)
+
+
+// Reserved address 224 [0xe0] 
+
+// Reserved address 228 [0xe4] 
+
+// Register AHB_AVP_PPCS_RD_COH_STATUS_0  
+#define AHB_AVP_PPCS_RD_COH_STATUS_0                    _MK_ADDR_CONST(0xe8)
+#define AHB_AVP_PPCS_RD_COH_STATUS_0_WORD_COUNT                         0x1
+#define AHB_AVP_PPCS_RD_COH_STATUS_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define AHB_AVP_PPCS_RD_COH_STATUS_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define AHB_AVP_PPCS_RD_COH_STATUS_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define AHB_AVP_PPCS_RD_COH_STATUS_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AHB_AVP_PPCS_RD_COH_STATUS_0_READ_MASK                  _MK_MASK_CONST(0x10001)
+#define AHB_AVP_PPCS_RD_COH_STATUS_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
+#define AHB_AVP_PPCS_RD_COH_STATUS_0_RDS_OUTSTANDING_SHIFT                      _MK_SHIFT_CONST(16)
+#define AHB_AVP_PPCS_RD_COH_STATUS_0_RDS_OUTSTANDING_FIELD                      (_MK_MASK_CONST(0x1) << AHB_AVP_PPCS_RD_COH_STATUS_0_RDS_OUTSTANDING_SHIFT)
+#define AHB_AVP_PPCS_RD_COH_STATUS_0_RDS_OUTSTANDING_RANGE                      16:16
+#define AHB_AVP_PPCS_RD_COH_STATUS_0_RDS_OUTSTANDING_WOFFSET                    0x0
+#define AHB_AVP_PPCS_RD_COH_STATUS_0_RDS_OUTSTANDING_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_AVP_PPCS_RD_COH_STATUS_0_RDS_OUTSTANDING_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define AHB_AVP_PPCS_RD_COH_STATUS_0_RDS_OUTSTANDING_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_AVP_PPCS_RD_COH_STATUS_0_RDS_OUTSTANDING_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define AHB_AVP_PPCS_RD_COH_STATUS_0_WRS_OUTSTANDING_SHIFT                      _MK_SHIFT_CONST(0)
+#define AHB_AVP_PPCS_RD_COH_STATUS_0_WRS_OUTSTANDING_FIELD                      (_MK_MASK_CONST(0x1) << AHB_AVP_PPCS_RD_COH_STATUS_0_WRS_OUTSTANDING_SHIFT)
+#define AHB_AVP_PPCS_RD_COH_STATUS_0_WRS_OUTSTANDING_RANGE                      0:0
+#define AHB_AVP_PPCS_RD_COH_STATUS_0_WRS_OUTSTANDING_WOFFSET                    0x0
+#define AHB_AVP_PPCS_RD_COH_STATUS_0_WRS_OUTSTANDING_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_AVP_PPCS_RD_COH_STATUS_0_WRS_OUTSTANDING_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define AHB_AVP_PPCS_RD_COH_STATUS_0_WRS_OUTSTANDING_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_AVP_PPCS_RD_COH_STATUS_0_WRS_OUTSTANDING_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register AHB_AHB_MEM_PREFETCH_CFG1_0  
+#define AHB_AHB_MEM_PREFETCH_CFG1_0                     _MK_ADDR_CONST(0xec)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_WORD_COUNT                  0x1
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_RESET_VAL                   _MK_MASK_CONST(0x14830800)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+// 1=enable 0=disable
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_ENABLE_SHIFT                        _MK_SHIFT_CONST(31)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_ENABLE_FIELD                        (_MK_MASK_CONST(0x1) << AHB_AHB_MEM_PREFETCH_CFG1_0_ENABLE_SHIFT)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_ENABLE_RANGE                        31:31
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_ENABLE_WOFFSET                      0x0
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// AHBDMA master
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_SHIFT                    _MK_SHIFT_CONST(26)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_FIELD                    (_MK_MASK_CONST(0x1f) << AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_SHIFT)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_RANGE                    30:26
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_WOFFSET                  0x0
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_DEFAULT                  _MK_MASK_CONST(0x5)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_CPU                      _MK_ENUM_CONST(0)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_COP                      _MK_ENUM_CONST(1)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_VCP                      _MK_ENUM_CONST(2)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_UNUSED_03                        _MK_ENUM_CONST(3)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_IDE                      _MK_ENUM_CONST(4)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_AHBDMA                   _MK_ENUM_CONST(5)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_USB                      _MK_ENUM_CONST(6)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_APBDMA                   _MK_ENUM_CONST(7)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_XIO                      _MK_ENUM_CONST(8)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_SDIO1                    _MK_ENUM_CONST(9)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_NAND_FLASH                       _MK_ENUM_CONST(10)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_UNUSED_0B                        _MK_ENUM_CONST(11)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_HSMMC                    _MK_ENUM_CONST(12)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_BSEV                     _MK_ENUM_CONST(13)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_UNUSED_0E                        _MK_ENUM_CONST(14)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_UNUSED_0F                        _MK_ENUM_CONST(15)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_BSEA                     _MK_ENUM_CONST(16)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_UNUSED_11                        _MK_ENUM_CONST(17)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_UNUSED_12                        _MK_ENUM_CONST(18)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_SDIO2                    _MK_ENUM_CONST(19)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_UNUSED_14                        _MK_ENUM_CONST(20)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_UNUSED_15                        _MK_ENUM_CONST(20)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_UNUSED_16                        _MK_ENUM_CONST(22)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_UNUSED_17                        _MK_ENUM_CONST(23)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_UNUSED_18                        _MK_ENUM_CONST(24)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_UNUSED_19                        _MK_ENUM_CONST(25)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_UNUSED_1A                        _MK_ENUM_CONST(26)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_UNUSED_1B                        _MK_ENUM_CONST(27)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_UNUSED_1C                        _MK_ENUM_CONST(28)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_UNUSED_1D                        _MK_ENUM_CONST(29)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_UNUSED_1E                        _MK_ENUM_CONST(30)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_UNUSED_1F                        _MK_ENUM_CONST(31)
+
+// 2^(n+4) byte boundary. any value >16 will use n=16
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_ADDR_BNDRY_SHIFT                    _MK_SHIFT_CONST(21)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_ADDR_BNDRY_FIELD                    (_MK_MASK_CONST(0x1f) << AHB_AHB_MEM_PREFETCH_CFG1_0_ADDR_BNDRY_SHIFT)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_ADDR_BNDRY_RANGE                    25:21
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_ADDR_BNDRY_WOFFSET                  0x0
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_ADDR_BNDRY_DEFAULT                  _MK_MASK_CONST(0x4)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_ADDR_BNDRY_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_ADDR_BNDRY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_ADDR_BNDRY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// 0=0, else 2^(n-1). any value >16 will n=16
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_SPEC_THROTTLE_SHIFT                 _MK_SHIFT_CONST(16)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_SPEC_THROTTLE_FIELD                 (_MK_MASK_CONST(0x1f) << AHB_AHB_MEM_PREFETCH_CFG1_0_SPEC_THROTTLE_SHIFT)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_SPEC_THROTTLE_RANGE                 20:16
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_SPEC_THROTTLE_WOFFSET                       0x0
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_SPEC_THROTTLE_DEFAULT                       _MK_MASK_CONST(0x3)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_SPEC_THROTTLE_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_SPEC_THROTTLE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_SPEC_THROTTLE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// 2048 cycles
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_INACTIVITY_TIMEOUT_SHIFT                    _MK_SHIFT_CONST(0)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_INACTIVITY_TIMEOUT_FIELD                    (_MK_MASK_CONST(0xffff) << AHB_AHB_MEM_PREFETCH_CFG1_0_INACTIVITY_TIMEOUT_SHIFT)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_INACTIVITY_TIMEOUT_RANGE                    15:0
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_INACTIVITY_TIMEOUT_WOFFSET                  0x0
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_INACTIVITY_TIMEOUT_DEFAULT                  _MK_MASK_CONST(0x800)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_INACTIVITY_TIMEOUT_DEFAULT_MASK                     _MK_MASK_CONST(0xffff)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_INACTIVITY_TIMEOUT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_INACTIVITY_TIMEOUT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register AHB_AHB_MEM_PREFETCH_CFG2_0  
+#define AHB_AHB_MEM_PREFETCH_CFG2_0                     _MK_ADDR_CONST(0xf0)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_WORD_COUNT                  0x1
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_RESET_VAL                   _MK_MASK_CONST(0x18830800)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+// 1=enable 0=disable
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_ENABLE_SHIFT                        _MK_SHIFT_CONST(31)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_ENABLE_FIELD                        (_MK_MASK_CONST(0x1) << AHB_AHB_MEM_PREFETCH_CFG2_0_ENABLE_SHIFT)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_ENABLE_RANGE                        31:31
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_ENABLE_WOFFSET                      0x0
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// USB
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_SHIFT                    _MK_SHIFT_CONST(26)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_FIELD                    (_MK_MASK_CONST(0x1f) << AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_SHIFT)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_RANGE                    30:26
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_WOFFSET                  0x0
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_DEFAULT                  _MK_MASK_CONST(0x6)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_CPU                      _MK_ENUM_CONST(0)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_COP                      _MK_ENUM_CONST(1)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_VCP                      _MK_ENUM_CONST(2)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_UNUSED_03                        _MK_ENUM_CONST(3)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_IDE                      _MK_ENUM_CONST(4)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_AHBDMA                   _MK_ENUM_CONST(5)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_USB                      _MK_ENUM_CONST(6)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_APBDMA                   _MK_ENUM_CONST(7)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_XIO                      _MK_ENUM_CONST(8)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_SDIO1                    _MK_ENUM_CONST(9)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_NAND_FLASH                       _MK_ENUM_CONST(10)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_UNUSED_0B                        _MK_ENUM_CONST(11)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_HSMMC                    _MK_ENUM_CONST(12)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_BSEV                     _MK_ENUM_CONST(13)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_UNUSED_0E                        _MK_ENUM_CONST(14)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_UNUSED_0F                        _MK_ENUM_CONST(15)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_BSEA                     _MK_ENUM_CONST(16)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_UNUSED_11                        _MK_ENUM_CONST(17)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_UNUSED_12                        _MK_ENUM_CONST(18)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_SDIO2                    _MK_ENUM_CONST(19)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_UNUSED_14                        _MK_ENUM_CONST(20)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_UNUSED_15                        _MK_ENUM_CONST(20)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_UNUSED_16                        _MK_ENUM_CONST(22)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_UNUSED_17                        _MK_ENUM_CONST(23)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_UNUSED_18                        _MK_ENUM_CONST(24)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_UNUSED_19                        _MK_ENUM_CONST(25)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_UNUSED_1A                        _MK_ENUM_CONST(26)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_UNUSED_1B                        _MK_ENUM_CONST(27)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_UNUSED_1C                        _MK_ENUM_CONST(28)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_UNUSED_1D                        _MK_ENUM_CONST(29)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_UNUSED_1E                        _MK_ENUM_CONST(30)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_UNUSED_1F                        _MK_ENUM_CONST(31)
+
+// 2^(n+4) byte boundary. any value >16 will use n=16
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_ADDR_BNDRY_SHIFT                    _MK_SHIFT_CONST(21)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_ADDR_BNDRY_FIELD                    (_MK_MASK_CONST(0x1f) << AHB_AHB_MEM_PREFETCH_CFG2_0_ADDR_BNDRY_SHIFT)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_ADDR_BNDRY_RANGE                    25:21
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_ADDR_BNDRY_WOFFSET                  0x0
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_ADDR_BNDRY_DEFAULT                  _MK_MASK_CONST(0x4)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_ADDR_BNDRY_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_ADDR_BNDRY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_ADDR_BNDRY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// 0=0, else 2^(n-1). any value >16 will n=16
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_SPEC_THROTTLE_SHIFT                 _MK_SHIFT_CONST(16)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_SPEC_THROTTLE_FIELD                 (_MK_MASK_CONST(0x1f) << AHB_AHB_MEM_PREFETCH_CFG2_0_SPEC_THROTTLE_SHIFT)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_SPEC_THROTTLE_RANGE                 20:16
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_SPEC_THROTTLE_WOFFSET                       0x0
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_SPEC_THROTTLE_DEFAULT                       _MK_MASK_CONST(0x3)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_SPEC_THROTTLE_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_SPEC_THROTTLE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_SPEC_THROTTLE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// 
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_INACTIVITY_TIMEOUT_SHIFT                    _MK_SHIFT_CONST(0)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_INACTIVITY_TIMEOUT_FIELD                    (_MK_MASK_CONST(0xffff) << AHB_AHB_MEM_PREFETCH_CFG2_0_INACTIVITY_TIMEOUT_SHIFT)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_INACTIVITY_TIMEOUT_RANGE                    15:0
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_INACTIVITY_TIMEOUT_WOFFSET                  0x0
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_INACTIVITY_TIMEOUT_DEFAULT                  _MK_MASK_CONST(0x800)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_INACTIVITY_TIMEOUT_DEFAULT_MASK                     _MK_MASK_CONST(0xffff)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_INACTIVITY_TIMEOUT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_INACTIVITY_TIMEOUT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register AHB_AHBSLVMEM_STATUS_0  
+#define AHB_AHBSLVMEM_STATUS_0                  _MK_ADDR_CONST(0xf4)
+#define AHB_AHBSLVMEM_STATUS_0_WORD_COUNT                       0x1
+#define AHB_AHBSLVMEM_STATUS_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define AHB_AHBSLVMEM_STATUS_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define AHB_AHBSLVMEM_STATUS_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define AHB_AHBSLVMEM_STATUS_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define AHB_AHBSLVMEM_STATUS_0_READ_MASK                        _MK_MASK_CONST(0x3)
+#define AHB_AHBSLVMEM_STATUS_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
+#define AHB_AHBSLVMEM_STATUS_0_PPCS_RDS_OUTSTANDING_SHIFT                       _MK_SHIFT_CONST(1)
+#define AHB_AHBSLVMEM_STATUS_0_PPCS_RDS_OUTSTANDING_FIELD                       (_MK_MASK_CONST(0x1) << AHB_AHBSLVMEM_STATUS_0_PPCS_RDS_OUTSTANDING_SHIFT)
+#define AHB_AHBSLVMEM_STATUS_0_PPCS_RDS_OUTSTANDING_RANGE                       1:1
+#define AHB_AHBSLVMEM_STATUS_0_PPCS_RDS_OUTSTANDING_WOFFSET                     0x0
+#define AHB_AHBSLVMEM_STATUS_0_PPCS_RDS_OUTSTANDING_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_AHBSLVMEM_STATUS_0_PPCS_RDS_OUTSTANDING_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define AHB_AHBSLVMEM_STATUS_0_PPCS_RDS_OUTSTANDING_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_AHBSLVMEM_STATUS_0_PPCS_RDS_OUTSTANDING_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define AHB_AHBSLVMEM_STATUS_0_GIZMO_IP_RDQUE_EMPTY_SHIFT                       _MK_SHIFT_CONST(0)
+#define AHB_AHBSLVMEM_STATUS_0_GIZMO_IP_RDQUE_EMPTY_FIELD                       (_MK_MASK_CONST(0x1) << AHB_AHBSLVMEM_STATUS_0_GIZMO_IP_RDQUE_EMPTY_SHIFT)
+#define AHB_AHBSLVMEM_STATUS_0_GIZMO_IP_RDQUE_EMPTY_RANGE                       0:0
+#define AHB_AHBSLVMEM_STATUS_0_GIZMO_IP_RDQUE_EMPTY_WOFFSET                     0x0
+#define AHB_AHBSLVMEM_STATUS_0_GIZMO_IP_RDQUE_EMPTY_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_AHBSLVMEM_STATUS_0_GIZMO_IP_RDQUE_EMPTY_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define AHB_AHBSLVMEM_STATUS_0_GIZMO_IP_RDQUE_EMPTY_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_AHBSLVMEM_STATUS_0_GIZMO_IP_RDQUE_EMPTY_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID_0  
+#define AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID_0                  _MK_ADDR_CONST(0xf8)
+#define AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID_0_WORD_COUNT                       0x1
+#define AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID_0_RESET_MASK                       _MK_MASK_CONST(0x7fffffff)
+#define AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID_0_READ_MASK                        _MK_MASK_CONST(0x7fffffff)
+#define AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID_0_WRITE_MASK                       _MK_MASK_CONST(0x7fffffff)
+// 0 = there is no write data in the write queue from  that AHB master.
+#define AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID_0_AHB_MASTER_ID_SHIFT                      _MK_SHIFT_CONST(0)
+#define AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID_0_AHB_MASTER_ID_FIELD                      (_MK_MASK_CONST(0x7fffffff) << AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID_0_AHB_MASTER_ID_SHIFT)
+#define AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID_0_AHB_MASTER_ID_RANGE                      30:0
+#define AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID_0_AHB_MASTER_ID_WOFFSET                    0x0
+#define AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID_0_AHB_MASTER_ID_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID_0_AHB_MASTER_ID_DEFAULT_MASK                       _MK_MASK_CONST(0x7fffffff)
+#define AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID_0_AHB_MASTER_ID_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID_0_AHB_MASTER_ID_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register AHB_ARBITRATION_CPU_ABORT_INFO_0  
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0                        _MK_ADDR_CONST(0xfc)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_WORD_COUNT                     0x1
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_RESET_MASK                     _MK_MASK_CONST(0xffff)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_READ_MASK                      _MK_MASK_CONST(0xffff)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
+// Abort occurred due to an iRAMa protection  violation
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMA_SHIFT                    _MK_SHIFT_CONST(15)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMA_FIELD                    (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMA_SHIFT)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMA_RANGE                    15:15
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMA_WOFFSET                  0x0
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMA_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMA_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMA_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMA_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMA_ABT_DIS                  _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMA_ABT_EN                   _MK_ENUM_CONST(1)
+
+// Abort occurred due to an iRAMb protection  violation
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMB_SHIFT                    _MK_SHIFT_CONST(14)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMB_FIELD                    (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMB_SHIFT)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMB_RANGE                    14:14
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMB_WOFFSET                  0x0
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMB_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMB_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMB_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMB_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMB_ABT_DIS                  _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMB_ABT_EN                   _MK_ENUM_CONST(1)
+
+// Abort occurred due to an iRAMc protection  violation
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMC_SHIFT                    _MK_SHIFT_CONST(13)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMC_FIELD                    (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMC_SHIFT)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMC_RANGE                    13:13
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMC_WOFFSET                  0x0
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMC_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMC_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMC_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMC_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMC_ABT_DIS                  _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMC_ABT_EN                   _MK_ENUM_CONST(1)
+
+// Abort occurred due to an iRAMd protection  violation
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMD_SHIFT                    _MK_SHIFT_CONST(12)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMD_FIELD                    (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMD_SHIFT)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMD_RANGE                    12:12
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMD_WOFFSET                  0x0
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMD_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMD_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMD_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMD_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMD_ABT_DIS                  _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMD_ABT_EN                   _MK_ENUM_CONST(1)
+
+// Abort occurred due to an access to invalid iRAM  address space
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_INV_IRAM_SHIFT                 _MK_SHIFT_CONST(11)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_INV_IRAM_FIELD                 (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_CPU_ABORT_INFO_0_INV_IRAM_SHIFT)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_INV_IRAM_RANGE                 11:11
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_INV_IRAM_WOFFSET                       0x0
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_INV_IRAM_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_INV_IRAM_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_INV_IRAM_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_INV_IRAM_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_INV_IRAM_ABT_DIS                       _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_INV_IRAM_ABT_EN                        _MK_ENUM_CONST(1)
+
+// Abort occurred due to a PPSB protection violation
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_PPSB_SHIFT                     _MK_SHIFT_CONST(10)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_PPSB_FIELD                     (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_CPU_ABORT_INFO_0_PPSB_SHIFT)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_PPSB_RANGE                     10:10
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_PPSB_WOFFSET                   0x0
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_PPSB_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_PPSB_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_PPSB_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_PPSB_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_PPSB_ABT_DIS                   _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_PPSB_ABT_EN                    _MK_ENUM_CONST(1)
+
+// Abort occurred due to an APB protection violation
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_APB_SHIFT                      _MK_SHIFT_CONST(9)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_APB_FIELD                      (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_CPU_ABORT_INFO_0_APB_SHIFT)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_APB_RANGE                      9:9
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_APB_WOFFSET                    0x0
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_APB_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_APB_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_APB_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_APB_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_APB_ABT_DIS                    _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_APB_ABT_EN                     _MK_ENUM_CONST(1)
+
+// Abort occurred due to an AHB protection violation
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_AHB_SHIFT                      _MK_SHIFT_CONST(8)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_AHB_FIELD                      (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_CPU_ABORT_INFO_0_AHB_SHIFT)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_AHB_RANGE                      8:8
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_AHB_WOFFSET                    0x0
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_AHB_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_AHB_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_AHB_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_AHB_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_AHB_ABT_DIS                    _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_AHB_ABT_EN                     _MK_ENUM_CONST(1)
+
+// Abort occurred due to a Cache protection violation
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_CACHE_SHIFT                    _MK_SHIFT_CONST(7)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_CACHE_FIELD                    (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_CPU_ABORT_INFO_0_CACHE_SHIFT)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_CACHE_RANGE                    7:7
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_CACHE_WOFFSET                  0x0
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_CACHE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_CACHE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_CACHE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_CACHE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_CACHE_ABT_DIS                  _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_CACHE_ABT_EN                   _MK_ENUM_CONST(1)
+
+// TRUE for any protection violation
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_PROTECTION_SHIFT                       _MK_SHIFT_CONST(6)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_PROTECTION_FIELD                       (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_CPU_ABORT_INFO_0_PROTECTION_SHIFT)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_PROTECTION_RANGE                       6:6
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_PROTECTION_WOFFSET                     0x0
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_PROTECTION_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_PROTECTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_PROTECTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_PROTECTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_PROTECTION_ABT_DIS                     _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_PROTECTION_ABT_EN                      _MK_ENUM_CONST(1)
+
+// TRUE for abort caused by Misalignment (i.e. word  access at odd byte address)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_ALIGN_SHIFT                    _MK_SHIFT_CONST(5)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_ALIGN_FIELD                    (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_CPU_ABORT_INFO_0_ALIGN_SHIFT)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_ALIGN_RANGE                    5:5
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_ALIGN_WOFFSET                  0x0
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_ALIGN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_ALIGN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_ALIGN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_ALIGN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_ALIGN_ABT_DIS                  _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_ALIGN_ABT_EN                   _MK_ENUM_CONST(1)
+
+// TRUE for abort caused by Bad Size (i.e. word  access at odd byte address)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_BADSIZE_SHIFT                  _MK_SHIFT_CONST(4)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_BADSIZE_FIELD                  (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_CPU_ABORT_INFO_0_BADSIZE_SHIFT)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_BADSIZE_RANGE                  4:4
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_BADSIZE_WOFFSET                        0x0
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_BADSIZE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_BADSIZE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_BADSIZE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_BADSIZE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_BADSIZE_ABT_DIS                        _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_BADSIZE_ABT_EN                 _MK_ENUM_CONST(1)
+
+// Aborted transaction was a Write
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_WRITE_SHIFT                    _MK_SHIFT_CONST(3)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_WRITE_FIELD                    (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_CPU_ABORT_INFO_0_WRITE_SHIFT)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_WRITE_RANGE                    3:3
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_WRITE_WOFFSET                  0x0
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_WRITE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_WRITE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_WRITE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_WRITE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_WRITE_ABT_DIS                  _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_WRITE_ABT_EN                   _MK_ENUM_CONST(1)
+
+// Aborted transaction was a Data access
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_DATA_SHIFT                     _MK_SHIFT_CONST(2)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_DATA_FIELD                     (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_CPU_ABORT_INFO_0_DATA_SHIFT)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_DATA_RANGE                     2:2
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_DATA_WOFFSET                   0x0
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_DATA_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_DATA_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_DATA_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_DATA_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_DATA_ABT_DIS                   _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_DATA_ABT_EN                    _MK_ENUM_CONST(1)
+
+// Aborted transaction Request Size 00=byte,  01=hword, 10=word
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_SIZE_SHIFT                     _MK_SHIFT_CONST(0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_SIZE_FIELD                     (_MK_MASK_CONST(0x3) << AHB_ARBITRATION_CPU_ABORT_INFO_0_SIZE_SHIFT)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_SIZE_RANGE                     1:0
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_SIZE_WOFFSET                   0x0
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_SIZE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_SIZE_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_SIZE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_SIZE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_SIZE_BYTE_ABT                  _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_SIZE_HWORD_ABT                 _MK_ENUM_CONST(1)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_SIZE_WORD_ABT                  _MK_ENUM_CONST(2)
+
+
+// Register AHB_ARBITRATION_CPU_ABORT_ADDR_0  
+#define AHB_ARBITRATION_CPU_ABORT_ADDR_0                        _MK_ADDR_CONST(0x100)
+#define AHB_ARBITRATION_CPU_ABORT_ADDR_0_WORD_COUNT                     0x1
+#define AHB_ARBITRATION_CPU_ABORT_ADDR_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_ADDR_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
+#define AHB_ARBITRATION_CPU_ABORT_ADDR_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_ADDR_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_ADDR_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define AHB_ARBITRATION_CPU_ABORT_ADDR_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
+// Instruction Address which caused the abort
+#define AHB_ARBITRATION_CPU_ABORT_ADDR_0_ADDR_SHIFT                     _MK_SHIFT_CONST(0)
+#define AHB_ARBITRATION_CPU_ABORT_ADDR_0_ADDR_FIELD                     (_MK_MASK_CONST(0xffffffff) << AHB_ARBITRATION_CPU_ABORT_ADDR_0_ADDR_SHIFT)
+#define AHB_ARBITRATION_CPU_ABORT_ADDR_0_ADDR_RANGE                     31:0
+#define AHB_ARBITRATION_CPU_ABORT_ADDR_0_ADDR_WOFFSET                   0x0
+#define AHB_ARBITRATION_CPU_ABORT_ADDR_0_ADDR_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_ADDR_0_ADDR_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define AHB_ARBITRATION_CPU_ABORT_ADDR_0_ADDR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_ADDR_0_ADDR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register AHB_ARBITRATION_COP_ABORT_INFO_0  
+#define AHB_ARBITRATION_COP_ABORT_INFO_0                        _MK_ADDR_CONST(0x104)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_WORD_COUNT                     0x1
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_RESET_MASK                     _MK_MASK_CONST(0xe7ff)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_READ_MASK                      _MK_MASK_CONST(0xe7ff)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
+// Abort occurred due to an iRAMa protection  violation
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMA_SHIFT                    _MK_SHIFT_CONST(15)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMA_FIELD                    (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMA_SHIFT)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMA_RANGE                    15:15
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMA_WOFFSET                  0x0
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMA_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMA_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMA_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMA_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMA_ABT_DIS                  _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMA_ABT_EN                   _MK_ENUM_CONST(1)
+
+// Abort occurred due to an iRAMb protection  violation
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMB_SHIFT                    _MK_SHIFT_CONST(14)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMB_FIELD                    (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMB_SHIFT)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMB_RANGE                    14:14
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMB_WOFFSET                  0x0
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMB_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMB_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMB_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMB_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMB_ABT_DIS                  _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMB_ABT_EN                   _MK_ENUM_CONST(1)
+
+// Abort occurred due to an iRAMc protection  violation
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMC_SHIFT                    _MK_SHIFT_CONST(13)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMC_FIELD                    (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMC_SHIFT)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMC_RANGE                    13:13
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMC_WOFFSET                  0x0
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMC_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMC_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMC_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMC_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMC_ABT_DIS                  _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMC_ABT_EN                   _MK_ENUM_CONST(1)
+
+// Abort occurred due to a PPSB protection violation
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_PPSB_SHIFT                     _MK_SHIFT_CONST(10)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_PPSB_FIELD                     (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_COP_ABORT_INFO_0_PPSB_SHIFT)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_PPSB_RANGE                     10:10
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_PPSB_WOFFSET                   0x0
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_PPSB_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_PPSB_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_PPSB_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_PPSB_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_PPSB_ABT_DIS                   _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_PPSB_ABT_EN                    _MK_ENUM_CONST(1)
+
+// Abort occurred due to an APB protection violation
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_APB_SHIFT                      _MK_SHIFT_CONST(9)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_APB_FIELD                      (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_COP_ABORT_INFO_0_APB_SHIFT)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_APB_RANGE                      9:9
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_APB_WOFFSET                    0x0
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_APB_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_APB_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_APB_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_APB_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_APB_ABT_DIS                    _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_APB_ABT_EN                     _MK_ENUM_CONST(1)
+
+// Abort occurred due to an AHB protection violation
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_AHB_SHIFT                      _MK_SHIFT_CONST(8)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_AHB_FIELD                      (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_COP_ABORT_INFO_0_AHB_SHIFT)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_AHB_RANGE                      8:8
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_AHB_WOFFSET                    0x0
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_AHB_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_AHB_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_AHB_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_AHB_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_AHB_ABT_DIS                    _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_AHB_ABT_EN                     _MK_ENUM_CONST(1)
+
+// Abort occurred due to a Cache protection violation
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_CACHE_SHIFT                    _MK_SHIFT_CONST(7)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_CACHE_FIELD                    (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_COP_ABORT_INFO_0_CACHE_SHIFT)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_CACHE_RANGE                    7:7
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_CACHE_WOFFSET                  0x0
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_CACHE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_CACHE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_CACHE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_CACHE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_CACHE_ABT_DIS                  _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_CACHE_ABT_EN                   _MK_ENUM_CONST(1)
+
+// TRUE for any protection violation
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_PROTECTION_SHIFT                       _MK_SHIFT_CONST(6)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_PROTECTION_FIELD                       (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_COP_ABORT_INFO_0_PROTECTION_SHIFT)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_PROTECTION_RANGE                       6:6
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_PROTECTION_WOFFSET                     0x0
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_PROTECTION_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_PROTECTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_PROTECTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_PROTECTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_PROTECTION_ABT_DIS                     _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_PROTECTION_ABT_EN                      _MK_ENUM_CONST(1)
+
+// TRUE for abort caused by Misalignment (i.e. word  access at odd byte address)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_ALIGN_SHIFT                    _MK_SHIFT_CONST(5)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_ALIGN_FIELD                    (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_COP_ABORT_INFO_0_ALIGN_SHIFT)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_ALIGN_RANGE                    5:5
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_ALIGN_WOFFSET                  0x0
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_ALIGN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_ALIGN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_ALIGN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_ALIGN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_ALIGN_ABT_DIS                  _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_ALIGN_ABT_EN                   _MK_ENUM_CONST(1)
+
+// TRUE for abort caused by Bad Size (i.e. word  access at odd byte address)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_BADSIZE_SHIFT                  _MK_SHIFT_CONST(4)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_BADSIZE_FIELD                  (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_COP_ABORT_INFO_0_BADSIZE_SHIFT)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_BADSIZE_RANGE                  4:4
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_BADSIZE_WOFFSET                        0x0
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_BADSIZE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_BADSIZE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_BADSIZE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_BADSIZE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_BADSIZE_ABT_DIS                        _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_BADSIZE_ABT_EN                 _MK_ENUM_CONST(1)
+
+// Aborted transaction was a Write
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_WRITE_SHIFT                    _MK_SHIFT_CONST(3)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_WRITE_FIELD                    (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_COP_ABORT_INFO_0_WRITE_SHIFT)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_WRITE_RANGE                    3:3
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_WRITE_WOFFSET                  0x0
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_WRITE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_WRITE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_WRITE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_WRITE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_WRITE_ABT_DIS                  _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_WRITE_ABT_EN                   _MK_ENUM_CONST(1)
+
+// Aborted transaction was a Data access
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_DATA_SHIFT                     _MK_SHIFT_CONST(2)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_DATA_FIELD                     (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_COP_ABORT_INFO_0_DATA_SHIFT)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_DATA_RANGE                     2:2
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_DATA_WOFFSET                   0x0
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_DATA_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_DATA_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_DATA_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_DATA_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_DATA_ABT_DIS                   _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_DATA_ABT_EN                    _MK_ENUM_CONST(1)
+
+// Aborted transaction Request Size 00=byte,  01=hword, 10=word
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_SIZE_SHIFT                     _MK_SHIFT_CONST(0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_SIZE_FIELD                     (_MK_MASK_CONST(0x3) << AHB_ARBITRATION_COP_ABORT_INFO_0_SIZE_SHIFT)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_SIZE_RANGE                     1:0
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_SIZE_WOFFSET                   0x0
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_SIZE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_SIZE_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_SIZE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_SIZE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_SIZE_BYTE_ABT                  _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_SIZE_HWORD_ABT                 _MK_ENUM_CONST(1)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_SIZE_WORD_ABT                  _MK_ENUM_CONST(2)
+
+
+// Register AHB_ARBITRATION_COP_ABORT_ADDR_0  
+#define AHB_ARBITRATION_COP_ABORT_ADDR_0                        _MK_ADDR_CONST(0x108)
+#define AHB_ARBITRATION_COP_ABORT_ADDR_0_WORD_COUNT                     0x1
+#define AHB_ARBITRATION_COP_ABORT_ADDR_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_ADDR_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
+#define AHB_ARBITRATION_COP_ABORT_ADDR_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_ADDR_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_ADDR_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define AHB_ARBITRATION_COP_ABORT_ADDR_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
+// Instruction Address which caused the abort
+#define AHB_ARBITRATION_COP_ABORT_ADDR_0_ADDR_SHIFT                     _MK_SHIFT_CONST(0)
+#define AHB_ARBITRATION_COP_ABORT_ADDR_0_ADDR_FIELD                     (_MK_MASK_CONST(0xffffffff) << AHB_ARBITRATION_COP_ABORT_ADDR_0_ADDR_SHIFT)
+#define AHB_ARBITRATION_COP_ABORT_ADDR_0_ADDR_RANGE                     31:0
+#define AHB_ARBITRATION_COP_ABORT_ADDR_0_ADDR_WOFFSET                   0x0
+#define AHB_ARBITRATION_COP_ABORT_ADDR_0_ADDR_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_ADDR_0_ADDR_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define AHB_ARBITRATION_COP_ABORT_ADDR_0_ADDR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_ADDR_0_ADDR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+//
+// REGISTER LIST
+//
+#define LIST_ARAHB_ARBC_REGS(_op_) \
+_op_(AHB_ARBITRATION_DISABLE_0) \
+_op_(AHB_ARBITRATION_PRIORITY_CTRL_0) \
+_op_(AHB_ARBITRATION_USR_PROTECT_0) \
+_op_(AHB_GIZMO_AHB_MEM_0) \
+_op_(AHB_GIZMO_APB_DMA_0) \
+_op_(AHB_GIZMO_IDE_0) \
+_op_(AHB_GIZMO_USB_0) \
+_op_(AHB_GIZMO_AHB_XBAR_BRIDGE_0) \
+_op_(AHB_GIZMO_CPU_AHB_BRIDGE_0) \
+_op_(AHB_GIZMO_COP_AHB_BRIDGE_0) \
+_op_(AHB_GIZMO_XBAR_APB_CTLR_0) \
+_op_(AHB_GIZMO_NAND_0) \
+_op_(AHB_GIZMO_HSMMC1_0) \
+_op_(AHB_GIZMO_XIO_0) \
+_op_(AHB_GIZMO_BSEV_0) \
+_op_(AHB_GIZMO_BSEA_0) \
+_op_(AHB_GIZMO_NOR_0) \
+_op_(AHB_ARBITRATION_XBAR_CTRL_0) \
+_op_(AHB_AVP_PPCS_RD_COH_STATUS_0) \
+_op_(AHB_AHB_MEM_PREFETCH_CFG1_0) \
+_op_(AHB_AHB_MEM_PREFETCH_CFG2_0) \
+_op_(AHB_AHBSLVMEM_STATUS_0) \
+_op_(AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID_0) \
+_op_(AHB_ARBITRATION_CPU_ABORT_INFO_0) \
+_op_(AHB_ARBITRATION_CPU_ABORT_ADDR_0) \
+_op_(AHB_ARBITRATION_COP_ABORT_INFO_0) \
+_op_(AHB_ARBITRATION_COP_ABORT_ADDR_0)
+
+
+//
+// ADDRESS SPACES
+//
+
+#define BASE_ADDRESS_AHB        0x00000000
+
+//
+// ARAHB_ARBC REGISTER BANKS
+//
+
+#define AHB0_FIRST_REG 0x0000 // AHB_ARBITRATION_DISABLE_0
+#define AHB0_LAST_REG 0x0010 // AHB_GIZMO_APB_DMA_0
+#define AHB1_FIRST_REG 0x0018 // AHB_GIZMO_IDE_0
+#define AHB1_LAST_REG 0x002c // AHB_GIZMO_XBAR_APB_CTLR_0
+#define AHB2_FIRST_REG 0x003c // AHB_GIZMO_NAND_0
+#define AHB2_LAST_REG 0x003c // AHB_GIZMO_NAND_0
+#define AHB3_FIRST_REG 0x0044 // AHB_GIZMO_HSMMC1_0
+#define AHB3_LAST_REG 0x0048 // AHB_GIZMO_XIO_0
+#define AHB4_FIRST_REG 0x0060 // AHB_GIZMO_BSEV_0
+#define AHB4_LAST_REG 0x0060 // AHB_GIZMO_BSEV_0
+#define AHB5_FIRST_REG 0x0070 // AHB_GIZMO_BSEA_0
+#define AHB5_LAST_REG 0x0074 // AHB_GIZMO_NOR_0
+#define AHB6_FIRST_REG 0x00dc // AHB_ARBITRATION_XBAR_CTRL_0
+#define AHB6_LAST_REG 0x00dc // AHB_ARBITRATION_XBAR_CTRL_0
+#define AHB7_FIRST_REG 0x00e8 // AHB_AVP_PPCS_RD_COH_STATUS_0
+#define AHB7_LAST_REG 0x0108 // AHB_ARBITRATION_COP_ABORT_ADDR_0
+
+#ifndef _MK_SHIFT_CONST
+  #define _MK_SHIFT_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_MASK_CONST
+  #define _MK_MASK_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_ENUM_CONST
+  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
+#endif
+#ifndef _MK_ADDR_CONST
+  #define _MK_ADDR_CONST(_constant_) _constant_
+#endif
+
+#endif // ifndef ___ARAHB_ARBC_H_INC_
diff --git a/arch/arm/mach-tegra/include/ap15/arapb_misc.h b/arch/arm/mach-tegra/include/ap15/arapb_misc.h
new file mode 100644
index 000000000000..f108944eb63d
--- /dev/null
+++ b/arch/arm/mach-tegra/include/ap15/arapb_misc.h
@@ -0,0 +1,12572 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+//
+// DO NOT EDIT - generated by simspec!
+//
+
+#ifndef ___ARAPB_MISC_H_INC_
+#define ___ARAPB_MISC_H_INC_
+
+// Reserved address 0 [0x0] 
+
+// Reserved address 4 [0x4] 
+
+// Register APB_MISC_PP_STRAPPING_OPT_A_0  
+#define APB_MISC_PP_STRAPPING_OPT_A_0                   _MK_ADDR_CONST(0x8)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_WORD_COUNT                        0x1
+#define APB_MISC_PP_STRAPPING_OPT_A_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_RESET_MASK                        _MK_MASK_CONST(0x101)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_READ_MASK                         _MK_MASK_CONST(0x1c001f1)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_WRITE_MASK                        _MK_MASK_CONST(0x1c001f1)
+// read at power-on reset time from hsmmc_wp strap pad
+// note that BOOT_SRC is only valid in pre-production mode
+#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SRC_USB_RECOVERY_MODE_SHIFT                  _MK_SHIFT_CONST(24)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SRC_USB_RECOVERY_MODE_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SRC_USB_RECOVERY_MODE_SHIFT)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SRC_USB_RECOVERY_MODE_RANGE                  24:24
+#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SRC_USB_RECOVERY_MODE_WOFFSET                        0x0
+#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SRC_USB_RECOVERY_MODE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SRC_USB_RECOVERY_MODE_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SRC_USB_RECOVERY_MODE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SRC_USB_RECOVERY_MODE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SRC_USB_RECOVERY_MODE_IROM                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SRC_USB_RECOVERY_MODE_NOR                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SRC_USB_RECOVERY_MODE_DISABLE                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SRC_USB_RECOVERY_MODE_ENABLE                 _MK_ENUM_CONST(1)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SRC_USB_RECOVERY_MODE_DISABLED                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SRC_USB_RECOVERY_MODE_ENABLED                        _MK_ENUM_CONST(1)
+
+// read at power-on reset time from {nand_cle,nand_ale} strap pads 00=Serial_JTAG, 01=CPU_only, 10=COP_only, 11=Serial_JTAG(same as 00 case)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_ARM_JTAG_SHIFT                    _MK_SHIFT_CONST(22)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_ARM_JTAG_FIELD                    (_MK_MASK_CONST(0x3) << APB_MISC_PP_STRAPPING_OPT_A_0_ARM_JTAG_SHIFT)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_ARM_JTAG_RANGE                    23:22
+#define APB_MISC_PP_STRAPPING_OPT_A_0_ARM_JTAG_WOFFSET                  0x0
+#define APB_MISC_PP_STRAPPING_OPT_A_0_ARM_JTAG_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_ARM_JTAG_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_ARM_JTAG_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_ARM_JTAG_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_ARM_JTAG_SERIAL                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_ARM_JTAG_CPU                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_ARM_JTAG_COP                      _MK_ENUM_CONST(2)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_ARM_JTAG_SERIAL_ALT                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_STRAPPING_OPT_A_0_MIO_WIDTH_SHIFT                   _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_MIO_WIDTH_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_PP_STRAPPING_OPT_A_0_MIO_WIDTH_SHIFT)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_MIO_WIDTH_RANGE                   8:8
+#define APB_MISC_PP_STRAPPING_OPT_A_0_MIO_WIDTH_WOFFSET                 0x0
+#define APB_MISC_PP_STRAPPING_OPT_A_0_MIO_WIDTH_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_MIO_WIDTH_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_MIO_WIDTH_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_MIO_WIDTH_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_MIO_WIDTH_INIT_ENUM                       IS16BIT
+#define APB_MISC_PP_STRAPPING_OPT_A_0_MIO_WIDTH_IS16BIT                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_MIO_WIDTH_IS32BIT                 _MK_ENUM_CONST(1)
+
+// read at power-on reset time from nand_d[3:0] strap pads
+#define APB_MISC_PP_STRAPPING_OPT_A_0_RAM_CODE_SHIFT                    _MK_SHIFT_CONST(4)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_RAM_CODE_FIELD                    (_MK_MASK_CONST(0xf) << APB_MISC_PP_STRAPPING_OPT_A_0_RAM_CODE_SHIFT)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_RAM_CODE_RANGE                    7:4
+#define APB_MISC_PP_STRAPPING_OPT_A_0_RAM_CODE_WOFFSET                  0x0
+#define APB_MISC_PP_STRAPPING_OPT_A_0_RAM_CODE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_RAM_CODE_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_RAM_CODE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_RAM_CODE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_PP_STRAPPING_OPT_A_0_NOR_WIDTH_SHIFT                   _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_NOR_WIDTH_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_PP_STRAPPING_OPT_A_0_NOR_WIDTH_SHIFT)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_NOR_WIDTH_RANGE                   0:0
+#define APB_MISC_PP_STRAPPING_OPT_A_0_NOR_WIDTH_WOFFSET                 0x0
+#define APB_MISC_PP_STRAPPING_OPT_A_0_NOR_WIDTH_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_NOR_WIDTH_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_NOR_WIDTH_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_NOR_WIDTH_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_NOR_WIDTH_INIT_ENUM                       IS16BIT
+#define APB_MISC_PP_STRAPPING_OPT_A_0_NOR_WIDTH_IS16BIT                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_NOR_WIDTH_IS8BIT                  _MK_ENUM_CONST(1)
+
+
+// Reserved address 12 [0xc] 
+
+// Reserved address 16 [0x10] 
+
+// Register APB_MISC_PP_TRISTATE_REG_A_0  
+#define APB_MISC_PP_TRISTATE_REG_A_0                    _MK_ADDR_CONST(0x14)
+#define APB_MISC_PP_TRISTATE_REG_A_0_WORD_COUNT                         0x1
+#define APB_MISC_PP_TRISTATE_REG_A_0_RESET_VAL                  _MK_MASK_CONST(0x11bffff)
+#define APB_MISC_PP_TRISTATE_REG_A_0_RESET_MASK                         _MK_MASK_CONST(0xfffffff)
+#define APB_MISC_PP_TRISTATE_REG_A_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_READ_MASK                  _MK_MASK_CONST(0xfffffff)
+#define APB_MISC_PP_TRISTATE_REG_A_0_WRITE_MASK                         _MK_MASK_CONST(0xfffffff)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCF_SHIFT                       _MK_SHIFT_CONST(27)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCF_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCF_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCF_RANGE                       27:27
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCF_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCF_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCF_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCF_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCF_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCF_INIT_ENUM                   NORMAL
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCF_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCF_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCE_SHIFT                       _MK_SHIFT_CONST(26)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCE_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCE_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCE_RANGE                       26:26
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCE_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCE_INIT_ENUM                   NORMAL
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCE_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCE_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_RM_SHIFT                 _MK_SHIFT_CONST(25)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_RM_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_RM_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_RM_RANGE                 25:25
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_RM_WOFFSET                       0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_RM_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_RM_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_RM_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_RM_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_RM_INIT_ENUM                     NORMAL
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_RM_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_RM_TRISTATE                      _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PTA_SHIFT                        _MK_SHIFT_CONST(24)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PTA_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_PTA_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PTA_RANGE                        24:24
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PTA_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PTA_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PTA_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PTA_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PTA_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PTA_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PTA_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PTA_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PMC_SHIFT                        _MK_SHIFT_CONST(23)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PMC_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_PMC_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PMC_RANGE                        23:23
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PMC_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PMC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PMC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PMC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PMC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PMC_INIT_ENUM                    NORMAL
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PMC_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PMC_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCA_SHIFT                       _MK_SHIFT_CONST(22)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCA_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCA_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCA_RANGE                       22:22
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCA_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCA_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCA_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCA_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCA_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCA_INIT_ENUM                   NORMAL
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCA_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCA_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCB_SHIFT                       _MK_SHIFT_CONST(21)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCB_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCB_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCB_RANGE                       21:21
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCB_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCB_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCB_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCB_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCB_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCB_INIT_ENUM                   NORMAL
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCB_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCB_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRRX_SHIFT                       _MK_SHIFT_CONST(20)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRRX_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_IRRX_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRRX_RANGE                       20:20
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRRX_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRRX_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRRX_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRRX_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRRX_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRRX_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRRX_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRRX_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRTX_SHIFT                       _MK_SHIFT_CONST(19)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRTX_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_IRTX_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRTX_RANGE                       19:19
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRTX_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRTX_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRTX_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRTX_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRTX_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRTX_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRTX_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRTX_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_I2CP_SHIFT                       _MK_SHIFT_CONST(18)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_I2CP_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_I2CP_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_I2CP_RANGE                       18:18
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_I2CP_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_I2CP_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_I2CP_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_I2CP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_I2CP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_I2CP_INIT_ENUM                   NORMAL
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_I2CP_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_I2CP_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPV_SHIFT                        _MK_SHIFT_CONST(17)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPV_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_GPV_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPV_RANGE                        17:17
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPV_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPV_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPV_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPV_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPV_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPV_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPV_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPV_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPU_SHIFT                        _MK_SHIFT_CONST(16)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPU_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_GPU_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPU_RANGE                        16:16
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPU_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPU_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPU_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPU_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPU_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPU_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPU_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPU_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTE_SHIFT                        _MK_SHIFT_CONST(15)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTE_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_DTE_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTE_RANGE                        15:15
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTE_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTE_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTE_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTE_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTE_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTD_SHIFT                        _MK_SHIFT_CONST(14)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTD_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_DTD_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTD_RANGE                        14:14
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTD_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTD_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTD_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTD_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTD_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTD_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTC_SHIFT                        _MK_SHIFT_CONST(13)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTC_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_DTC_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTC_RANGE                        13:13
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTC_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTC_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTC_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTC_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTC_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTB_SHIFT                        _MK_SHIFT_CONST(12)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTB_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_DTB_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTB_RANGE                        12:12
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTB_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTB_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTB_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTB_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTB_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTB_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTB_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTB_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTA_SHIFT                        _MK_SHIFT_CONST(11)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTA_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_DTA_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTA_RANGE                        11:11
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTA_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTA_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTA_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTA_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTA_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTA_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTA_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTA_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP4_SHIFT                       _MK_SHIFT_CONST(10)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP4_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP4_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP4_RANGE                       10:10
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP4_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP4_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP4_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP4_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP4_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP3_SHIFT                       _MK_SHIFT_CONST(9)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP3_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP3_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP3_RANGE                       9:9
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP3_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP3_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP3_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP3_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP3_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP2_SHIFT                       _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP2_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP2_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP2_RANGE                       8:8
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP2_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP2_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP2_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP2_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP2_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP1_SHIFT                       _MK_SHIFT_CONST(7)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP1_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP1_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP1_RANGE                       7:7
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP1_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP1_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP1_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP1_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP1_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CSUS_SHIFT                       _MK_SHIFT_CONST(6)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CSUS_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_CSUS_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CSUS_RANGE                       6:6
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CSUS_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CSUS_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CSUS_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CSUS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CSUS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CSUS_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CSUS_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CSUS_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV2_SHIFT                      _MK_SHIFT_CONST(5)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV2_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV2_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV2_RANGE                      5:5
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV2_WOFFSET                    0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV2_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV2_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV2_INIT_ENUM                  TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV2_NORMAL                     _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV2_TRISTATE                   _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV1_SHIFT                      _MK_SHIFT_CONST(4)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV1_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV1_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV1_RANGE                      4:4
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV1_WOFFSET                    0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV1_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV1_INIT_ENUM                  TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV1_NORMAL                     _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV1_TRISTATE                   _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATD_SHIFT                        _MK_SHIFT_CONST(3)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATD_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_ATD_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATD_RANGE                        3:3
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATD_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATD_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATD_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATD_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATD_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATD_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATC_SHIFT                        _MK_SHIFT_CONST(2)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATC_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_ATC_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATC_RANGE                        2:2
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATC_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATC_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATC_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATC_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATC_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATB_SHIFT                        _MK_SHIFT_CONST(1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATB_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_ATB_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATB_RANGE                        1:1
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATB_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATB_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATB_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATB_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATB_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATB_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATB_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATB_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATA_SHIFT                        _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATA_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_ATA_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATA_RANGE                        0:0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATA_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATA_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATA_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATA_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATA_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATA_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATA_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATA_TRISTATE                     _MK_ENUM_CONST(1)
+
+
+// Register APB_MISC_PP_TRISTATE_REG_B_0  
+#define APB_MISC_PP_TRISTATE_REG_B_0                    _MK_ADDR_CONST(0x18)
+#define APB_MISC_PP_TRISTATE_REG_B_0_WORD_COUNT                         0x1
+#define APB_MISC_PP_TRISTATE_REG_B_0_RESET_VAL                  _MK_MASK_CONST(0x2ffffff)
+#define APB_MISC_PP_TRISTATE_REG_B_0_RESET_MASK                         _MK_MASK_CONST(0x3effffff)
+#define APB_MISC_PP_TRISTATE_REG_B_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_READ_MASK                  _MK_MASK_CONST(0x3effffff)
+#define APB_MISC_PP_TRISTATE_REG_B_0_WRITE_MASK                         _MK_MASK_CONST(0x3effffff)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_XM2S_SHIFT                       _MK_SHIFT_CONST(29)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_XM2S_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_XM2S_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_XM2S_RANGE                       29:29
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_XM2S_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_XM2S_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_XM2S_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_XM2S_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_XM2S_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_XM2S_INIT_ENUM                   NORMAL
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_XM2S_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_XM2S_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_XM2C_SHIFT                       _MK_SHIFT_CONST(28)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_XM2C_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_XM2C_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_XM2C_RANGE                       28:28
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_XM2C_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_XM2C_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_XM2C_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_XM2C_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_XM2C_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_XM2C_INIT_ENUM                   NORMAL
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_XM2C_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_XM2C_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_XM2A_SHIFT                       _MK_SHIFT_CONST(27)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_XM2A_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_XM2A_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_XM2A_RANGE                       27:27
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_XM2A_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_XM2A_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_XM2A_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_XM2A_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_XM2A_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_XM2A_INIT_ENUM                   NORMAL
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_XM2A_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_XM2A_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_KBCC_SHIFT                       _MK_SHIFT_CONST(26)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_KBCC_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_KBCC_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_KBCC_RANGE                       26:26
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_KBCC_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_KBCC_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_KBCC_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_KBCC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_KBCC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_KBCC_INIT_ENUM                   NORMAL
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_KBCC_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_KBCC_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_ATE_SHIFT                        _MK_SHIFT_CONST(25)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_ATE_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_ATE_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_ATE_RANGE                        25:25
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_ATE_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_ATE_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_ATE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_ATE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_ATE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_ATE_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_ATE_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_ATE_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCB_SHIFT                        _MK_SHIFT_CONST(23)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCB_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_UCB_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCB_RANGE                        23:23
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCB_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCB_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCB_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCB_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCB_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCB_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCB_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCB_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCA_SHIFT                        _MK_SHIFT_CONST(22)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCA_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_UCA_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCA_RANGE                        22:22
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCA_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCA_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCA_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCA_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCA_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCA_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCA_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCA_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAD_SHIFT                        _MK_SHIFT_CONST(21)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAD_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_UAD_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAD_RANGE                        21:21
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAD_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAD_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAD_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAD_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAD_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAD_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAC_SHIFT                        _MK_SHIFT_CONST(20)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAC_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_UAC_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAC_RANGE                        20:20
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAC_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAC_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAC_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAC_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAC_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAB_SHIFT                        _MK_SHIFT_CONST(19)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAB_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_UAB_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAB_RANGE                        19:19
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAB_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAB_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAB_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAB_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAB_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAB_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAB_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAB_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAA_SHIFT                        _MK_SHIFT_CONST(18)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAA_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_UAA_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAA_RANGE                        18:18
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAA_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAA_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAA_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAA_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAA_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAA_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAA_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAA_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIH_SHIFT                       _MK_SHIFT_CONST(17)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIH_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIH_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIH_RANGE                       17:17
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIH_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIH_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIH_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIH_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIH_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIH_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIH_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIH_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIG_SHIFT                       _MK_SHIFT_CONST(16)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIG_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIG_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIG_RANGE                       16:16
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIG_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIG_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIG_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIG_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIG_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIG_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIG_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIG_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIF_SHIFT                       _MK_SHIFT_CONST(15)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIF_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIF_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIF_RANGE                       15:15
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIF_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIF_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIF_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIF_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIF_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIF_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIF_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIF_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIE_SHIFT                       _MK_SHIFT_CONST(14)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIE_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIE_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIE_RANGE                       14:14
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIE_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIE_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIE_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIE_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIE_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPID_SHIFT                       _MK_SHIFT_CONST(13)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPID_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_SPID_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPID_RANGE                       13:13
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPID_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPID_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPID_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPID_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPID_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPID_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPID_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPID_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIC_SHIFT                       _MK_SHIFT_CONST(12)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIC_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIC_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIC_RANGE                       12:12
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIC_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIC_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIC_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIC_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIC_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIC_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIB_SHIFT                       _MK_SHIFT_CONST(11)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIB_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIB_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIB_RANGE                       11:11
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIB_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIB_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIB_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIB_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIB_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIB_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIB_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIB_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIA_SHIFT                       _MK_SHIFT_CONST(10)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIA_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIA_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIA_RANGE                       10:10
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIA_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIA_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIA_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIA_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIA_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIA_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIA_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIA_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDO_SHIFT                       _MK_SHIFT_CONST(9)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDO_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDO_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDO_RANGE                       9:9
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDO_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDO_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDO_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDO_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDO_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDO_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDO_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDO_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDI_SHIFT                       _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDI_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDI_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDI_RANGE                       8:8
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDI_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDI_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDI_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDI_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDI_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDI_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDI_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDI_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXK_SHIFT                       _MK_SHIFT_CONST(7)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXK_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXK_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXK_RANGE                       7:7
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXK_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXK_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXK_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXK_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXK_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXD_SHIFT                       _MK_SHIFT_CONST(6)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXD_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXD_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXD_RANGE                       6:6
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXD_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXD_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXD_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXD_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXD_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXD_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXC_SHIFT                       _MK_SHIFT_CONST(5)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXC_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXC_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXC_RANGE                       5:5
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXC_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXC_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXC_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXC_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXC_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXC_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXB_SHIFT                       _MK_SHIFT_CONST(4)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXB_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXB_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXB_RANGE                       4:4
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXB_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXB_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXB_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXB_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXB_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXB_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXB_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXB_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXA_SHIFT                       _MK_SHIFT_CONST(3)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXA_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXA_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXA_RANGE                       3:3
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXA_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXA_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXA_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXA_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXA_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXA_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXA_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXA_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDD_SHIFT                        _MK_SHIFT_CONST(2)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDD_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_SDD_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDD_RANGE                        2:2
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDD_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDD_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDD_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDD_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDD_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDD_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDC_SHIFT                        _MK_SHIFT_CONST(1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDC_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_SDC_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDC_RANGE                        1:1
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDC_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDC_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDC_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDC_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDC_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDB_SHIFT                        _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDB_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_SDB_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDB_RANGE                        0:0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDB_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDB_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDB_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDB_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDB_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDB_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDB_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDB_TRISTATE                     _MK_ENUM_CONST(1)
+
+
+// Register APB_MISC_PP_TRISTATE_REG_C_0  
+#define APB_MISC_PP_TRISTATE_REG_C_0                    _MK_ADDR_CONST(0x1c)
+#define APB_MISC_PP_TRISTATE_REG_C_0_WORD_COUNT                         0x1
+#define APB_MISC_PP_TRISTATE_REG_C_0_RESET_VAL                  _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_TRISTATE_REG_C_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_TRISTATE_REG_C_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_TRISTATE_REG_C_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LCSN_SHIFT                       _MK_SHIFT_CONST(31)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LCSN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LCSN_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LCSN_RANGE                       31:31
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LCSN_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LCSN_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LCSN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LCSN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LCSN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LCSN_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LCSN_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LCSN_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LDC_SHIFT                        _MK_SHIFT_CONST(30)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LDC_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LDC_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LDC_RANGE                        30:30
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LDC_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LDC_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LDC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LDC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LDC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LDC_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LDC_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LDC_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSCK_SHIFT                       _MK_SHIFT_CONST(29)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSCK_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LSCK_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSCK_RANGE                       29:29
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSCK_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSCK_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSCK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSCK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSCK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSCK_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSCK_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSCK_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC1_SHIFT                       _MK_SHIFT_CONST(28)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC1_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC1_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC1_RANGE                       28:28
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC1_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC1_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC1_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC1_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC1_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC0_SHIFT                       _MK_SHIFT_CONST(27)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC0_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC0_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC0_RANGE                       27:27
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC0_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC0_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC0_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC0_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC0_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVS_SHIFT                        _MK_SHIFT_CONST(26)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVS_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LVS_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVS_RANGE                        26:26
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVS_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVS_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVS_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVS_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVS_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVS_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM1_SHIFT                        _MK_SHIFT_CONST(25)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM1_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LM1_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM1_RANGE                        25:25
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM1_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM1_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM1_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM1_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM1_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM1_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM0_SHIFT                        _MK_SHIFT_CONST(24)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM0_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LM0_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM0_RANGE                        24:24
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM0_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM0_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM0_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM0_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM0_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM0_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_HDINT_SHIFT                      _MK_SHIFT_CONST(23)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_HDINT_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_HDINT_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_HDINT_RANGE                      23:23
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_HDINT_WOFFSET                    0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_HDINT_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_HDINT_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_HDINT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_HDINT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_HDINT_INIT_ENUM                  TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_HDINT_NORMAL                     _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_HDINT_TRISTATE                   _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP1_SHIFT                       _MK_SHIFT_CONST(22)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP1_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP1_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP1_RANGE                       22:22
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP1_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP1_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP1_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP1_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP1_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP0_SHIFT                       _MK_SHIFT_CONST(21)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP0_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP0_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP0_RANGE                       21:21
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP0_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP0_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP0_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP0_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP0_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP2_SHIFT                       _MK_SHIFT_CONST(20)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP2_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP2_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP2_RANGE                       20:20
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP2_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP2_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP2_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP2_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP2_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP1_SHIFT                       _MK_SHIFT_CONST(19)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP1_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP1_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP1_RANGE                       19:19
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP1_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP1_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP1_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP1_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP1_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP0_SHIFT                       _MK_SHIFT_CONST(18)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP0_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP0_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP0_RANGE                       18:18
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP0_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP0_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP0_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP0_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP0_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD17_SHIFT                       _MK_SHIFT_CONST(17)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD17_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LD17_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD17_RANGE                       17:17
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD17_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD17_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD17_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD17_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD17_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD17_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD17_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD17_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD16_SHIFT                       _MK_SHIFT_CONST(16)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD16_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LD16_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD16_RANGE                       16:16
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD16_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD16_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD16_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD16_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD16_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD16_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD16_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD16_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD15_SHIFT                       _MK_SHIFT_CONST(15)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD15_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LD15_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD15_RANGE                       15:15
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD15_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD15_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD15_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD15_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD15_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD15_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD15_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD15_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD14_SHIFT                       _MK_SHIFT_CONST(14)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD14_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LD14_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD14_RANGE                       14:14
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD14_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD14_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD14_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD14_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD14_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD14_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD14_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD14_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD13_SHIFT                       _MK_SHIFT_CONST(13)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD13_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LD13_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD13_RANGE                       13:13
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD13_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD13_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD13_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD13_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD13_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD13_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD13_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD13_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD12_SHIFT                       _MK_SHIFT_CONST(12)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD12_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LD12_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD12_RANGE                       12:12
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD12_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD12_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD12_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD12_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD12_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD12_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD12_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD12_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD11_SHIFT                       _MK_SHIFT_CONST(11)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD11_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LD11_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD11_RANGE                       11:11
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD11_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD11_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD11_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD11_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD11_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD11_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD11_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD11_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD10_SHIFT                       _MK_SHIFT_CONST(10)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD10_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LD10_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD10_RANGE                       10:10
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD10_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD10_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD10_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD10_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD10_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD10_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD10_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD10_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD9_SHIFT                        _MK_SHIFT_CONST(9)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD9_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LD9_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD9_RANGE                        9:9
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD9_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD9_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD9_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD9_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD9_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD9_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD9_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD9_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD8_SHIFT                        _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD8_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LD8_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD8_RANGE                        8:8
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD8_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD8_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD8_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD8_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD8_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD8_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD7_SHIFT                        _MK_SHIFT_CONST(7)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD7_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LD7_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD7_RANGE                        7:7
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD7_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD7_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD7_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD7_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD7_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD7_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD6_SHIFT                        _MK_SHIFT_CONST(6)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD6_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LD6_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD6_RANGE                        6:6
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD6_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD6_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD6_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD6_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD6_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD6_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD5_SHIFT                        _MK_SHIFT_CONST(5)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD5_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LD5_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD5_RANGE                        5:5
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD5_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD5_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD5_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD5_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD5_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD5_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD4_SHIFT                        _MK_SHIFT_CONST(4)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD4_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LD4_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD4_RANGE                        4:4
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD4_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD4_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD4_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD4_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD4_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD4_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD3_SHIFT                        _MK_SHIFT_CONST(3)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD3_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LD3_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD3_RANGE                        3:3
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD3_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD3_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD3_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD3_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD3_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD3_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD2_SHIFT                        _MK_SHIFT_CONST(2)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD2_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LD2_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD2_RANGE                        2:2
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD2_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD2_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD2_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD2_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD2_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD2_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD1_SHIFT                        _MK_SHIFT_CONST(1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD1_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LD1_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD1_RANGE                        1:1
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD1_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD1_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD1_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD1_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD1_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD1_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD0_SHIFT                        _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD0_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LD0_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD0_RANGE                        0:0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD0_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD0_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD0_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD0_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD0_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD0_TRISTATE                     _MK_ENUM_CONST(1)
+
+
+// Register APB_MISC_PP_TRISTATE_REG_D_0  
+#define APB_MISC_PP_TRISTATE_REG_D_0                    _MK_ADDR_CONST(0x20)
+#define APB_MISC_PP_TRISTATE_REG_D_0_WORD_COUNT                         0x1
+#define APB_MISC_PP_TRISTATE_REG_D_0_RESET_VAL                  _MK_MASK_CONST(0x11ff)
+#define APB_MISC_PP_TRISTATE_REG_D_0_RESET_MASK                         _MK_MASK_CONST(0x1dff)
+#define APB_MISC_PP_TRISTATE_REG_D_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_READ_MASK                  _MK_MASK_CONST(0x1dff)
+#define APB_MISC_PP_TRISTATE_REG_D_0_WRITE_MASK                         _MK_MASK_CONST(0x1dff)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_DTF_SHIFT                        _MK_SHIFT_CONST(12)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_DTF_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_D_0_Z_DTF_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_DTF_RANGE                        12:12
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_DTF_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_DTF_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_DTF_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_DTF_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_DTF_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_DTF_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_DTF_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_DTF_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_GPU7_SHIFT                       _MK_SHIFT_CONST(11)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_GPU7_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_D_0_Z_GPU7_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_GPU7_RANGE                       11:11
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_GPU7_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_GPU7_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_GPU7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_GPU7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_GPU7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_GPU7_INIT_ENUM                   NORMAL
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_GPU7_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_GPU7_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_KBCD_SHIFT                       _MK_SHIFT_CONST(10)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_KBCD_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_D_0_Z_KBCD_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_KBCD_RANGE                       10:10
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_KBCD_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_KBCD_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_KBCD_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_KBCD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_KBCD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_KBCD_INIT_ENUM                   NORMAL
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_KBCD_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_KBCD_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPP_SHIFT                        _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPP_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_D_0_Z_LPP_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPP_RANGE                        8:8
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPP_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPP_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPP_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPP_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPP_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPP_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LHS_SHIFT                        _MK_SHIFT_CONST(7)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LHS_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_D_0_Z_LHS_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LHS_RANGE                        7:7
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LHS_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LHS_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LHS_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LHS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LHS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LHS_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LHS_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LHS_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LDI_SHIFT                        _MK_SHIFT_CONST(6)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LDI_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_D_0_Z_LDI_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LDI_RANGE                        6:6
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LDI_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LDI_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LDI_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LDI_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LDI_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LDI_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LDI_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LDI_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW2_SHIFT                       _MK_SHIFT_CONST(5)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW2_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW2_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW2_RANGE                       5:5
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW2_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW2_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW2_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW2_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW2_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW1_SHIFT                       _MK_SHIFT_CONST(4)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW1_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW1_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW1_RANGE                       4:4
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW1_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW1_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW1_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW1_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW1_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW0_SHIFT                       _MK_SHIFT_CONST(3)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW0_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW0_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW0_RANGE                       3:3
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW0_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW0_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW0_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW0_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW0_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDI_SHIFT                       _MK_SHIFT_CONST(2)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDI_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDI_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDI_RANGE                       2:2
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDI_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDI_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDI_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDI_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDI_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDI_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDI_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDI_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDA_SHIFT                       _MK_SHIFT_CONST(1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDA_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDA_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDA_RANGE                       1:1
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDA_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDA_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDA_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDA_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDA_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDA_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDA_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDA_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSPI_SHIFT                       _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSPI_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_D_0_Z_LSPI_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSPI_RANGE                       0:0
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSPI_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSPI_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSPI_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSPI_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSPI_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSPI_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSPI_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSPI_TRISTATE                    _MK_ENUM_CONST(1)
+
+
+// Register APB_MISC_PP_CONFIG_CTL_0  
+#define APB_MISC_PP_CONFIG_CTL_0                        _MK_ADDR_CONST(0x24)
+#define APB_MISC_PP_CONFIG_CTL_0_WORD_COUNT                     0x1
+#define APB_MISC_PP_CONFIG_CTL_0_RESET_VAL                      _MK_MASK_CONST(0x40)
+#define APB_MISC_PP_CONFIG_CTL_0_RESET_MASK                     _MK_MASK_CONST(0xc0)
+#define APB_MISC_PP_CONFIG_CTL_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_CONFIG_CTL_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_CONFIG_CTL_0_READ_MASK                      _MK_MASK_CONST(0xc0)
+#define APB_MISC_PP_CONFIG_CTL_0_WRITE_MASK                     _MK_MASK_CONST(0xc0)
+//  0 = Disable ; 1 = Enable RTCK Daisychaining
+#define APB_MISC_PP_CONFIG_CTL_0_TBE_SHIFT                      _MK_SHIFT_CONST(7)
+#define APB_MISC_PP_CONFIG_CTL_0_TBE_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_PP_CONFIG_CTL_0_TBE_SHIFT)
+#define APB_MISC_PP_CONFIG_CTL_0_TBE_RANGE                      7:7
+#define APB_MISC_PP_CONFIG_CTL_0_TBE_WOFFSET                    0x0
+#define APB_MISC_PP_CONFIG_CTL_0_TBE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_CONFIG_CTL_0_TBE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_CONFIG_CTL_0_TBE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_CONFIG_CTL_0_TBE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_CONFIG_CTL_0_TBE_INIT_ENUM                  DISABLE
+#define APB_MISC_PP_CONFIG_CTL_0_TBE_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_CONFIG_CTL_0_TBE_ENABLE                     _MK_ENUM_CONST(1)
+
+//  0 = Disable Debug ; 1 = Enable JTAG DBGEN
+#define APB_MISC_PP_CONFIG_CTL_0_JTAG_SHIFT                     _MK_SHIFT_CONST(6)
+#define APB_MISC_PP_CONFIG_CTL_0_JTAG_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_PP_CONFIG_CTL_0_JTAG_SHIFT)
+#define APB_MISC_PP_CONFIG_CTL_0_JTAG_RANGE                     6:6
+#define APB_MISC_PP_CONFIG_CTL_0_JTAG_WOFFSET                   0x0
+#define APB_MISC_PP_CONFIG_CTL_0_JTAG_DEFAULT                   _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_CONFIG_CTL_0_JTAG_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_CONFIG_CTL_0_JTAG_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_CONFIG_CTL_0_JTAG_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_CONFIG_CTL_0_JTAG_INIT_ENUM                 ENABLE
+#define APB_MISC_PP_CONFIG_CTL_0_JTAG_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_CONFIG_CTL_0_JTAG_ENABLE                    _MK_ENUM_CONST(1)
+
+
+// Register APB_MISC_PP_MISC_USB_OTG_0  
+#define APB_MISC_PP_MISC_USB_OTG_0                      _MK_ADDR_CONST(0x28)
+#define APB_MISC_PP_MISC_USB_OTG_0_WORD_COUNT                   0x1
+#define APB_MISC_PP_MISC_USB_OTG_0_RESET_VAL                    _MK_MASK_CONST(0x1000)
+#define APB_MISC_PP_MISC_USB_OTG_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_MISC_USB_OTG_0_WRITE_MASK                   _MK_MASK_CONST(0xfc7fff29)
+// Wake on Disconnect Enable (device mode)
+// When enabled (1), USB PHY will wakeup
+// from suspend on a disconnect event.
+// Software should only set this bit when
+// the USB PHY is suspended (bit 2 -
+// SUSPENDED = 1).
+// Also, software should clear it after
+// detecting a wakeup event.
+#define APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_DISCON_EN_SHIFT                      _MK_SHIFT_CONST(31)
+#define APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_DISCON_EN_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_DISCON_EN_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_DISCON_EN_RANGE                      31:31
+#define APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_DISCON_EN_WOFFSET                    0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_DISCON_EN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_DISCON_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_DISCON_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_DISCON_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_DISCON_EN_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_DISCON_EN_ENABLE                     _MK_ENUM_CONST(1)
+
+// Wake on Connect Enable (device mode)
+// When enabled (1), USB PHY will wakeup
+// from suspend on a connect event.
+// Software should only set this bit when
+// the USB PHY is suspended (bit 2 -
+// SUSPENDED = 1).
+// Also, software should clear it after
+// detecting a wakeup event.
+#define APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_CNNT_EN_SHIFT                        _MK_SHIFT_CONST(30)
+#define APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_CNNT_EN_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_CNNT_EN_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_CNNT_EN_RANGE                        30:30
+#define APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_CNNT_EN_WOFFSET                      0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_CNNT_EN_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_CNNT_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_CNNT_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_CNNT_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_CNNT_EN_DISABLE                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_CNNT_EN_ENABLE                       _MK_ENUM_CONST(1)
+
+// Debug bus select for USB 
+// Software should not change this.
+#define APB_MISC_PP_MISC_USB_OTG_0_USB_DEBUG_SEL_SHIFT                  _MK_SHIFT_CONST(26)
+#define APB_MISC_PP_MISC_USB_OTG_0_USB_DEBUG_SEL_FIELD                  (_MK_MASK_CONST(0xf) << APB_MISC_PP_MISC_USB_OTG_0_USB_DEBUG_SEL_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_USB_DEBUG_SEL_RANGE                  29:26
+#define APB_MISC_PP_MISC_USB_OTG_0_USB_DEBUG_SEL_WOFFSET                        0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_USB_DEBUG_SEL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_USB_DEBUG_SEL_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
+#define APB_MISC_PP_MISC_USB_OTG_0_USB_DEBUG_SEL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_USB_DEBUG_SEL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// B_SESS_END status from USB PHY.
+// This field is the same as the field
+// B_SESS_END_STS in register USB_PHY_VBUS_SENSORS.
+#define APB_MISC_PP_MISC_USB_OTG_0_B_SESS_END_STS2_SHIFT                        _MK_SHIFT_CONST(25)
+#define APB_MISC_PP_MISC_USB_OTG_0_B_SESS_END_STS2_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_B_SESS_END_STS2_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_B_SESS_END_STS2_RANGE                        25:25
+#define APB_MISC_PP_MISC_USB_OTG_0_B_SESS_END_STS2_WOFFSET                      0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_B_SESS_END_STS2_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_B_SESS_END_STS2_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_B_SESS_END_STS2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_B_SESS_END_STS2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_B_SESS_END_STS2_UNSET                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_B_SESS_END_STS2_SET                  _MK_ENUM_CONST(1)
+
+// A_VBUS_VLD status from USB PHY.
+// This field is the same as the field
+// A_VBUS_VLD_STS in register USB_PHY_VBUS_SENSORS.
+#define APB_MISC_PP_MISC_USB_OTG_0_A_VBUS_VLD_STS2_SHIFT                        _MK_SHIFT_CONST(24)
+#define APB_MISC_PP_MISC_USB_OTG_0_A_VBUS_VLD_STS2_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_A_VBUS_VLD_STS2_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_A_VBUS_VLD_STS2_RANGE                        24:24
+#define APB_MISC_PP_MISC_USB_OTG_0_A_VBUS_VLD_STS2_WOFFSET                      0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_A_VBUS_VLD_STS2_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_A_VBUS_VLD_STS2_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_A_VBUS_VLD_STS2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_A_VBUS_VLD_STS2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_A_VBUS_VLD_STS2_UNSET                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_A_VBUS_VLD_STS2_SET                  _MK_ENUM_CONST(1)
+
+// A_SESS_VLD status from USB PHY.
+// This field is the same as the field
+// A_SESS_VLD_STS in register USB_PHY_VBUS_SENSORS.
+#define APB_MISC_PP_MISC_USB_OTG_0_A_SESS_VLD_STS2_SHIFT                        _MK_SHIFT_CONST(23)
+#define APB_MISC_PP_MISC_USB_OTG_0_A_SESS_VLD_STS2_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_A_SESS_VLD_STS2_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_A_SESS_VLD_STS2_RANGE                        23:23
+#define APB_MISC_PP_MISC_USB_OTG_0_A_SESS_VLD_STS2_WOFFSET                      0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_A_SESS_VLD_STS2_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_A_SESS_VLD_STS2_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_A_SESS_VLD_STS2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_A_SESS_VLD_STS2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_A_SESS_VLD_STS2_UNSET                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_A_SESS_VLD_STS2_SET                  _MK_ENUM_CONST(1)
+
+// Software_B_SESS_END status.
+// Software should write the appropriate
+// value (1/0) to set/unset the B_SESS_END status.
+// This field is the same as the field
+// B_SESS_END_SW_VALUE in register USB_PHY_VBUS_SENSORS.
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_SHIFT                  _MK_SHIFT_CONST(22)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_RANGE                  22:22
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_WOFFSET                        0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_UNSET                  _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_SET                    _MK_ENUM_CONST(1)
+
+// Enable Software Controlled B_SESS_END.
+// Software sets this bit to drive the
+// value in  SW_B_SESS_END to the USB
+// controller.
+// This field is the same as the field
+// B_SESS_END_SW_EN in register USB_PHY_VBUS_SENSORS.
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_EN_SHIFT                       _MK_SHIFT_CONST(21)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_EN_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_EN_RANGE                       21:21
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_EN_WOFFSET                     0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// Software_A_VBUS_VLD status.
+// Software should write the appropriate
+// value (1/0) to set/unset the A_VBUS_VLD status.
+// This field is the same as the field
+// A_VBUS_VLD_SW_VALUE in register USB_PHY_VBUS_SENSORS.
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_SHIFT                  _MK_SHIFT_CONST(20)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_RANGE                  20:20
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_WOFFSET                        0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_UNSET                  _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_SET                    _MK_ENUM_CONST(1)
+
+// Enable Software Controlled A_VBUS_VLD.
+// Software sets this bit to drive the
+// value in SW_A_VBUS_VLD to the USB
+// controller.
+// This field is the same as the field
+// A_VBUS_VLD_SW_EN in register USB_PHY_VBUS_SENSORS.
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_EN_SHIFT                       _MK_SHIFT_CONST(19)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_EN_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_EN_RANGE                       19:19
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_EN_WOFFSET                     0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// Software_A_SESS_VLD status.
+// Software should write the appropriate
+// value (1/0) to set/unset the A_SESS_VLD status.
+// This field is the same as the field
+// A_SESS_VLD_SW_VALUE in register USB_PHY_VBUS_SENSORS.
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_SHIFT                  _MK_SHIFT_CONST(18)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_RANGE                  18:18
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_WOFFSET                        0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_UNSET                  _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_SET                    _MK_ENUM_CONST(1)
+
+// Enable Software Controlled A_SESS_VLD.
+// Software sets this bit to drive the
+// value in SW_A_SESS_VLD to the USB
+// controller.
+// This field is the same as the field
+// A_SESS_VLD_SW_EN in register USB_PHY_VBUS_SENSORS.
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_EN_SHIFT                       _MK_SHIFT_CONST(17)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_EN_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_EN_RANGE                       17:17
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_EN_WOFFSET                     0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// Suspend Set
+// Software must write a 1 to this bit to put the USB PHY in
+// suspend mode. Software should do this only after making sure that
+// the USB is indeed in suspend mode. Setting this bit will stop the
+// PHY clock. Software should write a 0 to clear it.
+// NOTE: It is required that software generate a positive pulse on this
+// bit to guarantee proper operation.
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSP_SET_SHIFT                       _MK_SHIFT_CONST(16)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSP_SET_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_SUSP_SET_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSP_SET_RANGE                       16:16
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSP_SET_WOFFSET                     0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSP_SET_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSP_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSP_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSP_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSP_SET_UNSET                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSP_SET_SET                 _MK_ENUM_CONST(1)
+
+// VBUS Change Interrupt Enable
+// If set, an interrupt will be generated whenever
+// A_SESS_VLD changes value. Software can read the
+// value of A_SESS_VLD from A_SESS_VLD_STS2 bit.
+// This field is the same as the field
+// A_SESS_VLD_INT_EN in register USB_PHY_VBUS_SENSORS.
+#define APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_INT_EN_SHIFT                        _MK_SHIFT_CONST(15)
+#define APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_INT_EN_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_INT_EN_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_INT_EN_RANGE                        15:15
+#define APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_INT_EN_WOFFSET                      0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_INT_EN_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_INT_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_INT_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_INT_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_INT_EN_DISABLE                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_INT_EN_ENABLE                       _MK_ENUM_CONST(1)
+
+// Software controlled OTG_ID.
+// If SW_OTG_ID_EN = 1, then software needs to monitor
+// actual OTG_ID bit used  as a GPIO and based on the value of OTG_ID,
+// it can set this bit.
+// This field is the same as the field
+// ID_SW_VALUE in register USB_PHY_VBUS_WAKEUP_ID.
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_SHIFT                      _MK_SHIFT_CONST(14)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_RANGE                      14:14
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_WOFFSET                    0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_UNSET                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_SET                        _MK_ENUM_CONST(1)
+
+// Reserved
+#define APB_MISC_PP_MISC_USB_OTG_0_RSVD13_SHIFT                 _MK_SHIFT_CONST(13)
+#define APB_MISC_PP_MISC_USB_OTG_0_RSVD13_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_RSVD13_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_RSVD13_RANGE                 13:13
+#define APB_MISC_PP_MISC_USB_OTG_0_RSVD13_WOFFSET                       0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_RSVD13_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_RSVD13_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_RSVD13_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_RSVD13_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// ID pullup enable.
+// This field controls the internal pull-up to
+// OTG_ID pin. Software should set this to
+// 1 if using internal OTG_ID. If software
+// is using a GPIO for OTG_ID, then it
+// can write this to 0.
+#define APB_MISC_PP_MISC_USB_OTG_0_ID_PU_SHIFT                  _MK_SHIFT_CONST(12)
+#define APB_MISC_PP_MISC_USB_OTG_0_ID_PU_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_ID_PU_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_ID_PU_RANGE                  12:12
+#define APB_MISC_PP_MISC_USB_OTG_0_ID_PU_WOFFSET                        0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_ID_PU_DEFAULT                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_ID_PU_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_ID_PU_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_ID_PU_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_ID_PU_DISABLE                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_ID_PU_ENABLE                 _MK_ENUM_CONST(1)
+
+//Suspend Clear
+// Software must write a 1 to this bit to bring the PHY
+// out of suspend mode. This is used when the software stops the PHY
+// clock during suspend and then wants to initiate a resume. Software
+// should also write 0 to clear it.
+// NOTE: It is required that software generate a  positive pulse on this
+// bit to guarantee proper operation.
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSP_CLR_SHIFT                       _MK_SHIFT_CONST(11)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSP_CLR_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_SUSP_CLR_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSP_CLR_RANGE                       11:11
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSP_CLR_WOFFSET                     0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSP_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSP_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSP_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSP_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSP_CLR_UNSET                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSP_CLR_SET                 _MK_ENUM_CONST(1)
+
+// Wake/resume on VBUS change change detect
+// If enabled, the USB PHY will wake up whenever a
+// change in A_SESS_VLD is detected.
+// This should be set only when USB PHY is already
+// suspended.
+#define APB_MISC_PP_MISC_USB_OTG_0_RSM_VBUS_CHG_SHIFT                   _MK_SHIFT_CONST(10)
+#define APB_MISC_PP_MISC_USB_OTG_0_RSM_VBUS_CHG_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_RSM_VBUS_CHG_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_RSM_VBUS_CHG_RANGE                   10:10
+#define APB_MISC_PP_MISC_USB_OTG_0_RSM_VBUS_CHG_WOFFSET                 0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_RSM_VBUS_CHG_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_RSM_VBUS_CHG_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_RSM_VBUS_CHG_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_RSM_VBUS_CHG_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_RSM_VBUS_CHG_DISABLE                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_RSM_VBUS_CHG_ENABLE                  _MK_ENUM_CONST(1)
+
+// Resume/Clock valid interrupt enable
+// If this bit is enabled, interrupt is generated
+// whenever PHY clock becomes valid.
+#define APB_MISC_PP_MISC_USB_OTG_0_RSM_IE_SHIFT                 _MK_SHIFT_CONST(9)
+#define APB_MISC_PP_MISC_USB_OTG_0_RSM_IE_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_RSM_IE_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_RSM_IE_RANGE                 9:9
+#define APB_MISC_PP_MISC_USB_OTG_0_RSM_IE_WOFFSET                       0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_RSM_IE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_RSM_IE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_RSM_IE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_RSM_IE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_RSM_IE_DISABLE                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_RSM_IE_ENABLE                        _MK_ENUM_CONST(1)
+
+// Wake on resume enable
+// If this bit is enabled, USB PHY will wakeup from
+// suspend whenever resume/reset signaling is
+// detected on USB.
+#define APB_MISC_PP_MISC_USB_OTG_0_WK_RSM_EN_SHIFT                      _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_MISC_USB_OTG_0_WK_RSM_EN_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_WK_RSM_EN_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_WK_RSM_EN_RANGE                      8:8
+#define APB_MISC_PP_MISC_USB_OTG_0_WK_RSM_EN_WOFFSET                    0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_WK_RSM_EN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_WK_RSM_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_WK_RSM_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_WK_RSM_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_WK_RSM_EN_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_WK_RSM_EN_ENABLE                     _MK_ENUM_CONST(1)
+
+// PHY clock valid status
+// This bit is set whenever PHY clock becomes valid.
+// It is cleared whenever PHY clock stops.
+#define APB_MISC_PP_MISC_USB_OTG_0_PCLKVLD_SHIFT                        _MK_SHIFT_CONST(7)
+#define APB_MISC_PP_MISC_USB_OTG_0_PCLKVLD_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_PCLKVLD_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_PCLKVLD_RANGE                        7:7
+#define APB_MISC_PP_MISC_USB_OTG_0_PCLKVLD_WOFFSET                      0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_PCLKVLD_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_PCLKVLD_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_PCLKVLD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_PCLKVLD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_PCLKVLD_UNSET                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_PCLKVLD_SET                  _MK_ENUM_CONST(1)
+
+// VBUS change detect
+// This bit is set whenever a change in A_SESS_VLD
+// is detected.
+// Software can read the status of A_SESS_VLD from 
+// A_SESS_VLD_STS2 bit.
+// This field is the same as the field
+// A_SESS_VLD_CHG_DET in register USB_PHY_VBUS_SENSORS.
+#define APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_DET_SHIFT                   _MK_SHIFT_CONST(6)
+#define APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_DET_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_DET_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_DET_RANGE                   6:6
+#define APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_DET_WOFFSET                 0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_DET_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_DET_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_DET_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_DET_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_DET_UNSET                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_DET_SET                     _MK_ENUM_CONST(1)
+
+// Loopback enable
+// Not for normal software use
+#define APB_MISC_PP_MISC_USB_OTG_0_LPBK_EN_SHIFT                        _MK_SHIFT_CONST(5)
+#define APB_MISC_PP_MISC_USB_OTG_0_LPBK_EN_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_LPBK_EN_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_LPBK_EN_RANGE                        5:5
+#define APB_MISC_PP_MISC_USB_OTG_0_LPBK_EN_WOFFSET                      0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_LPBK_EN_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_LPBK_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_LPBK_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_LPBK_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_LPBK_EN_DISABLE                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_LPBK_EN_ENABLE                       _MK_ENUM_CONST(1)
+
+// Real OTG_ID status from the USB PHY.
+// This field is the same as the field
+// ID_STS in register USB_PHY_VBUS_WAKEUP_ID.
+#define APB_MISC_PP_MISC_USB_OTG_0_OTG_ID_SHIFT                 _MK_SHIFT_CONST(4)
+#define APB_MISC_PP_MISC_USB_OTG_0_OTG_ID_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_OTG_ID_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_OTG_ID_RANGE                 4:4
+#define APB_MISC_PP_MISC_USB_OTG_0_OTG_ID_WOFFSET                       0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_OTG_ID_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_OTG_ID_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_OTG_ID_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_OTG_ID_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_OTG_ID_UNSET                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_OTG_ID_SET                   _MK_ENUM_CONST(1)
+
+// Enable Software Controlled OTG_ID
+// If using a GPIO for OTG_ID signal, then
+// software can set this to 1 and write
+// the value from the GPIO to the
+// SW_OTG_ID bit in this register.
+// This field is the same as the field
+// ID_SW_EN in register USB_PHY_VBUS_WAKEUP_ID.
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_EN_SHIFT                   _MK_SHIFT_CONST(3)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_EN_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_EN_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_EN_RANGE                   3:3
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_EN_WOFFSET                 0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_EN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_EN_DISABLE                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_EN_ENABLE                  _MK_ENUM_CONST(1)
+
+// USB PHY suspend status
+// This bit is set to 1 whenver USB is suspended and the PHY clock isnt  available.
+// NOTE: Software should not access any
+// registers in USB controller when this
+// bit is set.
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSPENDED_SHIFT                      _MK_SHIFT_CONST(2)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSPENDED_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_SUSPENDED_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSPENDED_RANGE                      2:2
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSPENDED_WOFFSET                    0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSPENDED_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSPENDED_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSPENDED_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSPENDED_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSPENDED_UNSET                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSPENDED_SET                        _MK_ENUM_CONST(1)
+
+// Static General purpose input coming from ID pin
+#define APB_MISC_PP_MISC_USB_OTG_0_StaticGpi_SHIFT                      _MK_SHIFT_CONST(1)
+#define APB_MISC_PP_MISC_USB_OTG_0_StaticGpi_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_StaticGpi_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_StaticGpi_RANGE                      1:1
+#define APB_MISC_PP_MISC_USB_OTG_0_StaticGpi_WOFFSET                    0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_StaticGpi_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_StaticGpi_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_StaticGpi_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_StaticGpi_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_StaticGpi_UNSET                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_StaticGpi_SET                        _MK_ENUM_CONST(1)
+
+// Polarity of the suspend signal going to USB PHY
+// Software should not change this.
+#define APB_MISC_PP_MISC_USB_OTG_0_SUS_POL_SHIFT                        _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUS_POL_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_SUS_POL_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUS_POL_RANGE                        0:0
+#define APB_MISC_PP_MISC_USB_OTG_0_SUS_POL_WOFFSET                      0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_SUS_POL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUS_POL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUS_POL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUS_POL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUS_POL_ACTIVE_LOW                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUS_POL_ACTIVE_HIGH                  _MK_ENUM_CONST(1)
+
+
+// Register APB_MISC_PP_XMB_CSR_0  
+#define APB_MISC_PP_XMB_CSR_0                   _MK_ADDR_CONST(0x30)
+#define APB_MISC_PP_XMB_CSR_0_WORD_COUNT                        0x1
+#define APB_MISC_PP_XMB_CSR_0_RESET_VAL                         _MK_MASK_CONST(0x58007410)
+#define APB_MISC_PP_XMB_CSR_0_RESET_MASK                        _MK_MASK_CONST(0xde04ffff)
+#define APB_MISC_PP_XMB_CSR_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_CSR_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_CSR_0_READ_MASK                         _MK_MASK_CONST(0xde04ffff)
+#define APB_MISC_PP_XMB_CSR_0_WRITE_MASK                        _MK_MASK_CONST(0x5004ffff)
+// External ROM Busy indicator.
+#define APB_MISC_PP_XMB_CSR_0_ROM_IORDY_IN_SHIFT                        _MK_SHIFT_CONST(31)
+#define APB_MISC_PP_XMB_CSR_0_ROM_IORDY_IN_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_XMB_CSR_0_ROM_IORDY_IN_SHIFT)
+#define APB_MISC_PP_XMB_CSR_0_ROM_IORDY_IN_RANGE                        31:31
+#define APB_MISC_PP_XMB_CSR_0_ROM_IORDY_IN_WOFFSET                      0x0
+#define APB_MISC_PP_XMB_CSR_0_ROM_IORDY_IN_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_CSR_0_ROM_IORDY_IN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_XMB_CSR_0_ROM_IORDY_IN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_CSR_0_ROM_IORDY_IN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// 0 = Write Protected (def)
+#define APB_MISC_PP_XMB_CSR_0_ROM_WE_SHIFT                      _MK_SHIFT_CONST(30)
+#define APB_MISC_PP_XMB_CSR_0_ROM_WE_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_PP_XMB_CSR_0_ROM_WE_SHIFT)
+#define APB_MISC_PP_XMB_CSR_0_ROM_WE_RANGE                      30:30
+#define APB_MISC_PP_XMB_CSR_0_ROM_WE_WOFFSET                    0x0
+#define APB_MISC_PP_XMB_CSR_0_ROM_WE_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_XMB_CSR_0_ROM_WE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_XMB_CSR_0_ROM_WE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_CSR_0_ROM_WE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// 0 = Strobe edge
+#define APB_MISC_PP_XMB_CSR_0_DQM_MASK_MODE_SHIFT                       _MK_SHIFT_CONST(28)
+#define APB_MISC_PP_XMB_CSR_0_DQM_MASK_MODE_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_XMB_CSR_0_DQM_MASK_MODE_SHIFT)
+#define APB_MISC_PP_XMB_CSR_0_DQM_MASK_MODE_RANGE                       28:28
+#define APB_MISC_PP_XMB_CSR_0_DQM_MASK_MODE_WOFFSET                     0x0
+#define APB_MISC_PP_XMB_CSR_0_DQM_MASK_MODE_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_XMB_CSR_0_DQM_MASK_MODE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_XMB_CSR_0_DQM_MASK_MODE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_CSR_0_DQM_MASK_MODE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// 0 = Buffer not empty 1 = Buffer empty (default) (RO  register)
+#define APB_MISC_PP_XMB_CSR_0_AHB_BUF_MT_SHIFT                  _MK_SHIFT_CONST(27)
+#define APB_MISC_PP_XMB_CSR_0_AHB_BUF_MT_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_PP_XMB_CSR_0_AHB_BUF_MT_SHIFT)
+#define APB_MISC_PP_XMB_CSR_0_AHB_BUF_MT_RANGE                  27:27
+#define APB_MISC_PP_XMB_CSR_0_AHB_BUF_MT_WOFFSET                        0x0
+#define APB_MISC_PP_XMB_CSR_0_AHB_BUF_MT_DEFAULT                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_XMB_CSR_0_AHB_BUF_MT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_XMB_CSR_0_AHB_BUF_MT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_CSR_0_AHB_BUF_MT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// 0 = Buffer Not full (default) 1 = Buffer Full (RO  register)
+#define APB_MISC_PP_XMB_CSR_0_AHB_BUF_FULL_SHIFT                        _MK_SHIFT_CONST(26)
+#define APB_MISC_PP_XMB_CSR_0_AHB_BUF_FULL_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_XMB_CSR_0_AHB_BUF_FULL_SHIFT)
+#define APB_MISC_PP_XMB_CSR_0_AHB_BUF_FULL_RANGE                        26:26
+#define APB_MISC_PP_XMB_CSR_0_AHB_BUF_FULL_WOFFSET                      0x0
+#define APB_MISC_PP_XMB_CSR_0_AHB_BUF_FULL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_CSR_0_AHB_BUF_FULL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_XMB_CSR_0_AHB_BUF_FULL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_CSR_0_AHB_BUF_FULL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// 0 = Buffer empty (default) 1 = Buffer full (RO  register)
+#define APB_MISC_PP_XMB_CSR_0_DC_BUF_FULL_SHIFT                 _MK_SHIFT_CONST(25)
+#define APB_MISC_PP_XMB_CSR_0_DC_BUF_FULL_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_PP_XMB_CSR_0_DC_BUF_FULL_SHIFT)
+#define APB_MISC_PP_XMB_CSR_0_DC_BUF_FULL_RANGE                 25:25
+#define APB_MISC_PP_XMB_CSR_0_DC_BUF_FULL_WOFFSET                       0x0
+#define APB_MISC_PP_XMB_CSR_0_DC_BUF_FULL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_CSR_0_DC_BUF_FULL_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_XMB_CSR_0_DC_BUF_FULL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_CSR_0_DC_BUF_FULL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// 0 = don't mask mio_rdy 1 = mask mio_rdy
+#define APB_MISC_PP_XMB_CSR_0_MASK_MIO_RDY_SHIFT                        _MK_SHIFT_CONST(18)
+#define APB_MISC_PP_XMB_CSR_0_MASK_MIO_RDY_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_XMB_CSR_0_MASK_MIO_RDY_SHIFT)
+#define APB_MISC_PP_XMB_CSR_0_MASK_MIO_RDY_RANGE                        18:18
+#define APB_MISC_PP_XMB_CSR_0_MASK_MIO_RDY_WOFFSET                      0x0
+#define APB_MISC_PP_XMB_CSR_0_MASK_MIO_RDY_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_CSR_0_MASK_MIO_RDY_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_XMB_CSR_0_MASK_MIO_RDY_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_CSR_0_MASK_MIO_RDY_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+//  1XXX = Reserved
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_D_SHIFT                   _MK_SHIFT_CONST(12)
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_D_FIELD                   (_MK_MASK_CONST(0xf) << APB_MISC_PP_XMB_CSR_0_XMB_CSN_D_SHIFT)
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_D_RANGE                   15:12
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_D_WOFFSET                 0x0
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_D_DEFAULT                 _MK_MASK_CONST(0x7)
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_D_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_D_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_D_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_D_ROM0                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_D_ROM1                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_D_XMEM1                   _MK_ENUM_CONST(5)
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_D_MIO0                    _MK_ENUM_CONST(6)
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_D_MIO1                    _MK_ENUM_CONST(7)
+
+//  1XXX = Reserved
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_C_SHIFT                   _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_C_FIELD                   (_MK_MASK_CONST(0xf) << APB_MISC_PP_XMB_CSR_0_XMB_CSN_C_SHIFT)
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_C_RANGE                   11:8
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_C_WOFFSET                 0x0
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_C_DEFAULT                 _MK_MASK_CONST(0x4)
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_C_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_C_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_C_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_C_ROM0                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_C_ROM1                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_C_XMEM0                   _MK_ENUM_CONST(4)
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_C_MIO0                    _MK_ENUM_CONST(6)
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_C_MIO1                    _MK_ENUM_CONST(7)
+
+//  1XXX = Reserved
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_B_SHIFT                   _MK_SHIFT_CONST(4)
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_B_FIELD                   (_MK_MASK_CONST(0xf) << APB_MISC_PP_XMB_CSR_0_XMB_CSN_B_SHIFT)
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_B_RANGE                   7:4
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_B_WOFFSET                 0x0
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_B_DEFAULT                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_B_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_B_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_B_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_B_ROM0                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_B_ROM1                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_B_MIO0                    _MK_ENUM_CONST(6)
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_B_MIO1                    _MK_ENUM_CONST(7)
+
+//  1XXX = Reserved
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_A_SHIFT                   _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_A_FIELD                   (_MK_MASK_CONST(0xf) << APB_MISC_PP_XMB_CSR_0_XMB_CSN_A_SHIFT)
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_A_RANGE                   3:0
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_A_WOFFSET                 0x0
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_A_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_A_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_A_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_A_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_A_ROM0                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_A_ROM1                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_A_MIO0                    _MK_ENUM_CONST(6)
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_A_MIO1                    _MK_ENUM_CONST(7)
+
+
+// Register APB_MISC_PP_XMB_NOR_FLASH_CFG_0  
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0                 _MK_ADDR_CONST(0x34)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_WORD_COUNT                      0x1
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_RESET_VAL                       _MK_MASK_CONST(0x1f1f)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_RESET_MASK                      _MK_MASK_CONST(0xc3ff3f3f)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_READ_MASK                       _MK_MASK_CONST(0xc3ff3f3f)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_WRITE_MASK                      _MK_MASK_CONST(0xc3ff3f3f)
+// writing 1 clears nor_muxerr interrupt
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_NOR_MUXERR_INT_CLR_SHIFT                        _MK_SHIFT_CONST(31)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_NOR_MUXERR_INT_CLR_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_XMB_NOR_FLASH_CFG_0_NOR_MUXERR_INT_CLR_SHIFT)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_NOR_MUXERR_INT_CLR_RANGE                        31:31
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_NOR_MUXERR_INT_CLR_WOFFSET                      0x0
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_NOR_MUXERR_INT_CLR_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_NOR_MUXERR_INT_CLR_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_NOR_MUXERR_INT_CLR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_NOR_MUXERR_INT_CLR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// 0 = mask interrupt 1 = don't mask interrupt
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_NOR_MUXERR_INT_MASK_SHIFT                       _MK_SHIFT_CONST(30)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_NOR_MUXERR_INT_MASK_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_XMB_NOR_FLASH_CFG_0_NOR_MUXERR_INT_MASK_SHIFT)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_NOR_MUXERR_INT_MASK_RANGE                       30:30
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_NOR_MUXERR_INT_MASK_WOFFSET                     0x0
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_NOR_MUXERR_INT_MASK_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_NOR_MUXERR_INT_MASK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_NOR_MUXERR_INT_MASK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_NOR_MUXERR_INT_MASK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// NOR minimum transaction time
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_NOR_MIN_TRANS_TIME_SHIFT                        _MK_SHIFT_CONST(16)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_NOR_MIN_TRANS_TIME_FIELD                        (_MK_MASK_CONST(0x3ff) << APB_MISC_PP_XMB_NOR_FLASH_CFG_0_NOR_MIN_TRANS_TIME_SHIFT)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_NOR_MIN_TRANS_TIME_RANGE                        25:16
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_NOR_MIN_TRANS_TIME_WOFFSET                      0x0
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_NOR_MIN_TRANS_TIME_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_NOR_MIN_TRANS_TIME_DEFAULT_MASK                 _MK_MASK_CONST(0x3ff)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_NOR_MIN_TRANS_TIME_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_NOR_MIN_TRANS_TIME_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// ROM Wait cycles after Write. (in SCLK)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_ROM_WR_DEAD_TIME_SHIFT                  _MK_SHIFT_CONST(12)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_ROM_WR_DEAD_TIME_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_XMB_NOR_FLASH_CFG_0_ROM_WR_DEAD_TIME_SHIFT)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_ROM_WR_DEAD_TIME_RANGE                  13:12
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_ROM_WR_DEAD_TIME_WOFFSET                        0x0
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_ROM_WR_DEAD_TIME_DEFAULT                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_ROM_WR_DEAD_TIME_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_ROM_WR_DEAD_TIME_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_ROM_WR_DEAD_TIME_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// ROM Write time (in number of SCLK cycles)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_ROM_WR_TIME_SHIFT                       _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_ROM_WR_TIME_FIELD                       (_MK_MASK_CONST(0xf) << APB_MISC_PP_XMB_NOR_FLASH_CFG_0_ROM_WR_TIME_SHIFT)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_ROM_WR_TIME_RANGE                       11:8
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_ROM_WR_TIME_WOFFSET                     0x0
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_ROM_WR_TIME_DEFAULT                     _MK_MASK_CONST(0xf)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_ROM_WR_TIME_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_ROM_WR_TIME_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_ROM_WR_TIME_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// ROM Wait cycles after Read (in SCLK)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_ROM_RD_DEAD_TIME_SHIFT                  _MK_SHIFT_CONST(4)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_ROM_RD_DEAD_TIME_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_XMB_NOR_FLASH_CFG_0_ROM_RD_DEAD_TIME_SHIFT)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_ROM_RD_DEAD_TIME_RANGE                  5:4
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_ROM_RD_DEAD_TIME_WOFFSET                        0x0
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_ROM_RD_DEAD_TIME_DEFAULT                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_ROM_RD_DEAD_TIME_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_ROM_RD_DEAD_TIME_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_ROM_RD_DEAD_TIME_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// ROM Read time (in number of SCLK cycles)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_ROM_RD_TIME_SHIFT                       _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_ROM_RD_TIME_FIELD                       (_MK_MASK_CONST(0xf) << APB_MISC_PP_XMB_NOR_FLASH_CFG_0_ROM_RD_TIME_SHIFT)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_ROM_RD_TIME_RANGE                       3:0
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_ROM_RD_TIME_WOFFSET                     0x0
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_ROM_RD_TIME_DEFAULT                     _MK_MASK_CONST(0xf)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_ROM_RD_TIME_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_ROM_RD_TIME_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_ROM_RD_TIME_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Reserved address 56 [0x38] 
+
+// Register APB_MISC_PP_XMB_MIO_CFG_0  
+#define APB_MISC_PP_XMB_MIO_CFG_0                       _MK_ADDR_CONST(0x40)
+#define APB_MISC_PP_XMB_MIO_CFG_0_WORD_COUNT                    0x1
+#define APB_MISC_PP_XMB_MIO_CFG_0_RESET_VAL                     _MK_MASK_CONST(0x1f1f1f1f)
+#define APB_MISC_PP_XMB_MIO_CFG_0_RESET_MASK                    _MK_MASK_CONST(0x7f7f7f7f)
+#define APB_MISC_PP_XMB_MIO_CFG_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_MIO_CFG_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_MIO_CFG_0_READ_MASK                     _MK_MASK_CONST(0x7f7f7f7f)
+#define APB_MISC_PP_XMB_MIO_CFG_0_WRITE_MASK                    _MK_MASK_CONST(0x7f7f7f7f)
+// end of a write access and goes low for the start  of another read or write access.
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_B_WR_DEAD_TIME_SHIFT                      _MK_SHIFT_CONST(28)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_B_WR_DEAD_TIME_FIELD                      (_MK_MASK_CONST(0x7) << APB_MISC_PP_XMB_MIO_CFG_0_MIO_B_WR_DEAD_TIME_SHIFT)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_B_WR_DEAD_TIME_RANGE                      30:28
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_B_WR_DEAD_TIME_WOFFSET                    0x0
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_B_WR_DEAD_TIME_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_B_WR_DEAD_TIME_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_B_WR_DEAD_TIME_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_B_WR_DEAD_TIME_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// signal is set low for MIO1. This period extends  beyond the programmed period as long as MIO_RDY signal remains low. MIO_RDY  is connected to a slave wait pin, both active low. As long as this signal is  low, PP5003 maintains all the MIO signals stable, as it waits for the slave  to complete the access. Request is removed after signal goes high.
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_B_WR_TIME_SHIFT                   _MK_SHIFT_CONST(24)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_B_WR_TIME_FIELD                   (_MK_MASK_CONST(0xf) << APB_MISC_PP_XMB_MIO_CFG_0_MIO_B_WR_TIME_SHIFT)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_B_WR_TIME_RANGE                   27:24
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_B_WR_TIME_WOFFSET                 0x0
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_B_WR_TIME_DEFAULT                 _MK_MASK_CONST(0xf)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_B_WR_TIME_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_B_WR_TIME_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_B_WR_TIME_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// start of the following access for MIO1. (The chip  select goes high at the end of a read access and goes low at the start of a  read or write access.)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_B_RD_DEAD_TIME_SHIFT                      _MK_SHIFT_CONST(20)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_B_RD_DEAD_TIME_FIELD                      (_MK_MASK_CONST(0x7) << APB_MISC_PP_XMB_MIO_CFG_0_MIO_B_RD_DEAD_TIME_SHIFT)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_B_RD_DEAD_TIME_RANGE                      22:20
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_B_RD_DEAD_TIME_WOFFSET                    0x0
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_B_RD_DEAD_TIME_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_B_RD_DEAD_TIME_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_B_RD_DEAD_TIME_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_B_RD_DEAD_TIME_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// signal is set low for MIO1. This period extends  beyond the programmed period as long as MIO_RDY signal remains low. MIO_RDY  is connected to a slave wait pin, both active low. As long as this signal is  low, PP5003 maintains all the MIO signals
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_B_RD_TIME_SHIFT                   _MK_SHIFT_CONST(16)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_B_RD_TIME_FIELD                   (_MK_MASK_CONST(0xf) << APB_MISC_PP_XMB_MIO_CFG_0_MIO_B_RD_TIME_SHIFT)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_B_RD_TIME_RANGE                   19:16
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_B_RD_TIME_WOFFSET                 0x0
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_B_RD_TIME_DEFAULT                 _MK_MASK_CONST(0xf)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_B_RD_TIME_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_B_RD_TIME_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_B_RD_TIME_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// the start of the following access (write or read)  for MIO0 . Chip select goes high at the end of a write access and goes low  for the start of another read or write access.
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_A_WR_DEAD_TIME_SHIFT                      _MK_SHIFT_CONST(12)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_A_WR_DEAD_TIME_FIELD                      (_MK_MASK_CONST(0x7) << APB_MISC_PP_XMB_MIO_CFG_0_MIO_A_WR_DEAD_TIME_SHIFT)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_A_WR_DEAD_TIME_RANGE                      14:12
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_A_WR_DEAD_TIME_WOFFSET                    0x0
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_A_WR_DEAD_TIME_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_A_WR_DEAD_TIME_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_A_WR_DEAD_TIME_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_A_WR_DEAD_TIME_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// during a write access for MIO0. This period  extends as long as the MIO_RDY signal remains low.
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_A_WR_TIME_SHIFT                   _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_A_WR_TIME_FIELD                   (_MK_MASK_CONST(0xf) << APB_MISC_PP_XMB_MIO_CFG_0_MIO_A_WR_TIME_SHIFT)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_A_WR_TIME_RANGE                   11:8
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_A_WR_TIME_WOFFSET                 0x0
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_A_WR_TIME_DEFAULT                 _MK_MASK_CONST(0xf)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_A_WR_TIME_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_A_WR_TIME_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_A_WR_TIME_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// start of the following access for MIO0. (The chip  select goes high at the end of a read access and goes low at the start of a  read or write access.)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_A_RD_DEAD_TIME_SHIFT                      _MK_SHIFT_CONST(4)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_A_RD_DEAD_TIME_FIELD                      (_MK_MASK_CONST(0x7) << APB_MISC_PP_XMB_MIO_CFG_0_MIO_A_RD_DEAD_TIME_SHIFT)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_A_RD_DEAD_TIME_RANGE                      6:4
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_A_RD_DEAD_TIME_WOFFSET                    0x0
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_A_RD_DEAD_TIME_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_A_RD_DEAD_TIME_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_A_RD_DEAD_TIME_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_A_RD_DEAD_TIME_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// MIO RDY Indicator. This signal indicates if the  MIO is ready. This also implies that the MIO is not busy with the present  request. The firmware can poll for this to get device status.
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_A_RD_TIME_SHIFT                   _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_A_RD_TIME_FIELD                   (_MK_MASK_CONST(0xf) << APB_MISC_PP_XMB_MIO_CFG_0_MIO_A_RD_TIME_SHIFT)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_A_RD_TIME_RANGE                   3:0
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_A_RD_TIME_WOFFSET                 0x0
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_A_RD_TIME_DEFAULT                 _MK_MASK_CONST(0xf)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_A_RD_TIME_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_A_RD_TIME_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_A_RD_TIME_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Reserved address 68 [0x44] 
+
+// Register APB_MISC_PP_USB_PHY_VCTL_REG_0  
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0                  _MK_ADDR_CONST(0x60)
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_WORD_COUNT                       0x1
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_RESET_VAL                        _MK_MASK_CONST(0x100020)
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_RESET_MASK                       _MK_MASK_CONST(0x10ff3f)
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_READ_MASK                        _MK_MASK_CONST(0x10ff3f)
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_WRITE_MASK                       _MK_MASK_CONST(0x10003f)
+// Unused
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_CLK12_SEL_SHIFT                  _MK_SHIFT_CONST(20)
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_CLK12_SEL_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VCTL_REG_0_CLK12_SEL_SHIFT)
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_CLK12_SEL_RANGE                  20:20
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_CLK12_SEL_WOFFSET                        0x0
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_CLK12_SEL_DEFAULT                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_CLK12_SEL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_CLK12_SEL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_CLK12_SEL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_CLK12_SEL_MHZ_24                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_CLK12_SEL_MHZ_12                 _MK_ENUM_CONST(1)
+
+// Vendor status from PHY. Read only
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_VSTATUS_SHIFT                    _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_VSTATUS_FIELD                    (_MK_MASK_CONST(0xff) << APB_MISC_PP_USB_PHY_VCTL_REG_0_VSTATUS_SHIFT)
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_VSTATUS_RANGE                    15:8
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_VSTATUS_WOFFSET                  0x0
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_VSTATUS_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_VSTATUS_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_VSTATUS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_VSTATUS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Default: 1
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_VLOAD_SHIFT                      _MK_SHIFT_CONST(5)
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_VLOAD_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VCTL_REG_0_VLOAD_SHIFT)
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_VLOAD_RANGE                      5:5
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_VLOAD_WOFFSET                    0x0
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_VLOAD_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_VLOAD_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_VLOAD_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_VLOAD_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_VLOAD_UNSET                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_VLOAD_SET                        _MK_ENUM_CONST(1)
+
+// Default: 0
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_VCONTROL_SHIFT                   _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_VCONTROL_FIELD                   (_MK_MASK_CONST(0x1f) << APB_MISC_PP_USB_PHY_VCTL_REG_0_VCONTROL_SHIFT)
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_VCONTROL_RANGE                   4:0
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_VCONTROL_WOFFSET                 0x0
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_VCONTROL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_VCONTROL_DEFAULT_MASK                    _MK_MASK_CONST(0x1f)
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_VCONTROL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_VCONTROL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_PP_USB_PHY_PARAM_0  
+#define APB_MISC_PP_USB_PHY_PARAM_0                     _MK_ADDR_CONST(0x64)
+#define APB_MISC_PP_USB_PHY_PARAM_0_WORD_COUNT                  0x1
+#define APB_MISC_PP_USB_PHY_PARAM_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_RESET_MASK                  _MK_MASK_CONST(0x3ff9)
+#define APB_MISC_PP_USB_PHY_PARAM_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_READ_MASK                   _MK_MASK_CONST(0x3ff9)
+#define APB_MISC_PP_USB_PHY_PARAM_0_WRITE_MASK                  _MK_MASK_CONST(0x3ff9)
+// Lower 32-bits select.
+// Not intended for software use.
+#define APB_MISC_PP_USB_PHY_PARAM_0_BUF_LOW32BITS_SEL_SHIFT                     _MK_SHIFT_CONST(13)
+#define APB_MISC_PP_USB_PHY_PARAM_0_BUF_LOW32BITS_SEL_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_PARAM_0_BUF_LOW32BITS_SEL_SHIFT)
+#define APB_MISC_PP_USB_PHY_PARAM_0_BUF_LOW32BITS_SEL_RANGE                     13:13
+#define APB_MISC_PP_USB_PHY_PARAM_0_BUF_LOW32BITS_SEL_WOFFSET                   0x0
+#define APB_MISC_PP_USB_PHY_PARAM_0_BUF_LOW32BITS_SEL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_BUF_LOW32BITS_SEL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_PARAM_0_BUF_LOW32BITS_SEL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_BUF_LOW32BITS_SEL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_BUF_LOW32BITS_SEL_UPPER_BITS                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_BUF_LOW32BITS_SEL_LOWER_BITS                        _MK_ENUM_CONST(1)
+
+// Enable reception of test packets
+// Not intended for software use.
+#define APB_MISC_PP_USB_PHY_PARAM_0_RCV_TEST_PKT_SHIFT                  _MK_SHIFT_CONST(12)
+#define APB_MISC_PP_USB_PHY_PARAM_0_RCV_TEST_PKT_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_PARAM_0_RCV_TEST_PKT_SHIFT)
+#define APB_MISC_PP_USB_PHY_PARAM_0_RCV_TEST_PKT_RANGE                  12:12
+#define APB_MISC_PP_USB_PHY_PARAM_0_RCV_TEST_PKT_WOFFSET                        0x0
+#define APB_MISC_PP_USB_PHY_PARAM_0_RCV_TEST_PKT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_RCV_TEST_PKT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_PARAM_0_RCV_TEST_PKT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_RCV_TEST_PKT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_RCV_TEST_PKT_DISABLE                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_RCV_TEST_PKT_ENABLE                 _MK_ENUM_CONST(1)
+
+// Enable transmission of test packets
+// Not intended for software use.
+#define APB_MISC_PP_USB_PHY_PARAM_0_SEND_TEST_PKT_SHIFT                 _MK_SHIFT_CONST(11)
+#define APB_MISC_PP_USB_PHY_PARAM_0_SEND_TEST_PKT_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_PARAM_0_SEND_TEST_PKT_SHIFT)
+#define APB_MISC_PP_USB_PHY_PARAM_0_SEND_TEST_PKT_RANGE                 11:11
+#define APB_MISC_PP_USB_PHY_PARAM_0_SEND_TEST_PKT_WOFFSET                       0x0
+#define APB_MISC_PP_USB_PHY_PARAM_0_SEND_TEST_PKT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_SEND_TEST_PKT_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_PARAM_0_SEND_TEST_PKT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_SEND_TEST_PKT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_SEND_TEST_PKT_DISABLE                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_SEND_TEST_PKT_ENABLE                        _MK_ENUM_CONST(1)
+
+// Enable TEST_J transmission
+// Not intended for software use.
+#define APB_MISC_PP_USB_PHY_PARAM_0_SEND_TEST_K_SHIFT                   _MK_SHIFT_CONST(10)
+#define APB_MISC_PP_USB_PHY_PARAM_0_SEND_TEST_K_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_PARAM_0_SEND_TEST_K_SHIFT)
+#define APB_MISC_PP_USB_PHY_PARAM_0_SEND_TEST_K_RANGE                   10:10
+#define APB_MISC_PP_USB_PHY_PARAM_0_SEND_TEST_K_WOFFSET                 0x0
+#define APB_MISC_PP_USB_PHY_PARAM_0_SEND_TEST_K_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_SEND_TEST_K_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_PARAM_0_SEND_TEST_K_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_SEND_TEST_K_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_SEND_TEST_K_DISABLE                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_SEND_TEST_K_ENABLE                  _MK_ENUM_CONST(1)
+
+// Enable TEST_K transmission
+// Not intended for software use.
+#define APB_MISC_PP_USB_PHY_PARAM_0_SEND_TEST_J_SHIFT                   _MK_SHIFT_CONST(9)
+#define APB_MISC_PP_USB_PHY_PARAM_0_SEND_TEST_J_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_PARAM_0_SEND_TEST_J_SHIFT)
+#define APB_MISC_PP_USB_PHY_PARAM_0_SEND_TEST_J_RANGE                   9:9
+#define APB_MISC_PP_USB_PHY_PARAM_0_SEND_TEST_J_WOFFSET                 0x0
+#define APB_MISC_PP_USB_PHY_PARAM_0_SEND_TEST_J_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_SEND_TEST_J_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_PARAM_0_SEND_TEST_J_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_SEND_TEST_J_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_SEND_TEST_J_DISABLE                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_SEND_TEST_J_ENABLE                  _MK_ENUM_CONST(1)
+
+// If enabled, send SOF with EOP of J, else
+// send SOF with EOP of K
+// Not intended for software use.
+#define APB_MISC_PP_USB_PHY_PARAM_0_TEST_SOF_J_SHIFT                    _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_USB_PHY_PARAM_0_TEST_SOF_J_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_PARAM_0_TEST_SOF_J_SHIFT)
+#define APB_MISC_PP_USB_PHY_PARAM_0_TEST_SOF_J_RANGE                    8:8
+#define APB_MISC_PP_USB_PHY_PARAM_0_TEST_SOF_J_WOFFSET                  0x0
+#define APB_MISC_PP_USB_PHY_PARAM_0_TEST_SOF_J_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_TEST_SOF_J_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_PARAM_0_TEST_SOF_J_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_TEST_SOF_J_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_TEST_SOF_J_DISABLE                  _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_TEST_SOF_J_ENABLE                   _MK_ENUM_CONST(1)
+
+// Unused
+// Not intended for software use.
+#define APB_MISC_PP_USB_PHY_PARAM_0_UTMI_DEBUG_SEL_SHIFT                        _MK_SHIFT_CONST(7)
+#define APB_MISC_PP_USB_PHY_PARAM_0_UTMI_DEBUG_SEL_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_PARAM_0_UTMI_DEBUG_SEL_SHIFT)
+#define APB_MISC_PP_USB_PHY_PARAM_0_UTMI_DEBUG_SEL_RANGE                        7:7
+#define APB_MISC_PP_USB_PHY_PARAM_0_UTMI_DEBUG_SEL_WOFFSET                      0x0
+#define APB_MISC_PP_USB_PHY_PARAM_0_UTMI_DEBUG_SEL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_UTMI_DEBUG_SEL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_PARAM_0_UTMI_DEBUG_SEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_UTMI_DEBUG_SEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_UTMI_DEBUG_SEL_DISABLE                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_UTMI_DEBUG_SEL_ENABLE                       _MK_ENUM_CONST(1)
+
+// Reserved
+#define APB_MISC_PP_USB_PHY_PARAM_0_RSVD6_SHIFT                 _MK_SHIFT_CONST(6)
+#define APB_MISC_PP_USB_PHY_PARAM_0_RSVD6_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_PARAM_0_RSVD6_SHIFT)
+#define APB_MISC_PP_USB_PHY_PARAM_0_RSVD6_RANGE                 6:6
+#define APB_MISC_PP_USB_PHY_PARAM_0_RSVD6_WOFFSET                       0x0
+#define APB_MISC_PP_USB_PHY_PARAM_0_RSVD6_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_RSVD6_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_PARAM_0_RSVD6_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_RSVD6_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Route USB buffers to AHB interface for debug
+// Not intended for software use.
+#define APB_MISC_PP_USB_PHY_PARAM_0_BUF_AHB_IF_SEL_SHIFT                        _MK_SHIFT_CONST(5)
+#define APB_MISC_PP_USB_PHY_PARAM_0_BUF_AHB_IF_SEL_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_PARAM_0_BUF_AHB_IF_SEL_SHIFT)
+#define APB_MISC_PP_USB_PHY_PARAM_0_BUF_AHB_IF_SEL_RANGE                        5:5
+#define APB_MISC_PP_USB_PHY_PARAM_0_BUF_AHB_IF_SEL_WOFFSET                      0x0
+#define APB_MISC_PP_USB_PHY_PARAM_0_BUF_AHB_IF_SEL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_BUF_AHB_IF_SEL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_PARAM_0_BUF_AHB_IF_SEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_BUF_AHB_IF_SEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_BUF_AHB_IF_SEL_DISABLE                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_BUF_AHB_IF_SEL_ENABLE                       _MK_ENUM_CONST(1)
+
+// Vbus_sense control
+// Controls which VBUS sensor input is driven to the controller.
+// 00: Use VBUS_WAKEUP.
+// 01: Use A_SESS_VLD output from the PHY if the PHY clock is available.
+// Otherwise, use VBUS_WAKEUP.
+// 10: Use A_SESS_VLD output from the PHY
+// 11: Use VBUS_WAKEUP.
+#define APB_MISC_PP_USB_PHY_PARAM_0_VS_CTL_SHIFT                        _MK_SHIFT_CONST(3)
+#define APB_MISC_PP_USB_PHY_PARAM_0_VS_CTL_FIELD                        (_MK_MASK_CONST(0x3) << APB_MISC_PP_USB_PHY_PARAM_0_VS_CTL_SHIFT)
+#define APB_MISC_PP_USB_PHY_PARAM_0_VS_CTL_RANGE                        4:3
+#define APB_MISC_PP_USB_PHY_PARAM_0_VS_CTL_WOFFSET                      0x0
+#define APB_MISC_PP_USB_PHY_PARAM_0_VS_CTL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_VS_CTL_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_USB_PHY_PARAM_0_VS_CTL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_VS_CTL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_VS_CTL_VBUS_WAKEUP                  _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_VS_CTL_A_SESS_VLD_OR_VBUS_WAKEUP                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_USB_PHY_PARAM_0_VS_CTL_A_SESS_VLD                   _MK_ENUM_CONST(2)
+#define APB_MISC_PP_USB_PHY_PARAM_0_VS_CTL_VBUS_WAKEUP_1                        _MK_ENUM_CONST(3)
+
+// FS/LS serial interface enable
+// If enabled, use FS/LS serial interface for USB transfers.
+// This mode does not support HS transfers.
+// If disabled, use UTMI interface for USB transfers.
+// This mode supports all transfer speeds - HS/FS/LS.
+#define APB_MISC_PP_USB_PHY_PARAM_0_FS_LS_SER_MODE_SHIFT                        _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_FS_LS_SER_MODE_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_PARAM_0_FS_LS_SER_MODE_SHIFT)
+#define APB_MISC_PP_USB_PHY_PARAM_0_FS_LS_SER_MODE_RANGE                        0:0
+#define APB_MISC_PP_USB_PHY_PARAM_0_FS_LS_SER_MODE_WOFFSET                      0x0
+#define APB_MISC_PP_USB_PHY_PARAM_0_FS_LS_SER_MODE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_FS_LS_SER_MODE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_PARAM_0_FS_LS_SER_MODE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_FS_LS_SER_MODE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_FS_LS_SER_MODE_DISABLE                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_FS_LS_SER_MODE_ENABLE                       _MK_ENUM_CONST(1)
+
+
+// Register APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0  
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0                   _MK_ADDR_CONST(0x68)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_WORD_COUNT                        0x1
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_RESET_MASK                        _MK_MASK_CONST(0x33f3f)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_READ_MASK                         _MK_MASK_CONST(0x33f3f)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+// RX compare fail. Comparison on RX data failed.
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_RXCMF_SHIFT                       _MK_SHIFT_CONST(17)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_RXCMF_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_RXCMF_SHIFT)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_RXCMF_RANGE                       17:17
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_RXCMF_WOFFSET                     0x0
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_RXCMF_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_RXCMF_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_RXCMF_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_RXCMF_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_RXCMF_UNSET                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_RXCMF_SET                 _MK_ENUM_CONST(1)
+
+// Rx valid/Rx validh fail: Indicates that the  Rxvalid/Rxvalidh werent generated according to protocol
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_RXVHF_SHIFT                       _MK_SHIFT_CONST(16)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_RXVHF_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_RXVHF_SHIFT)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_RXVHF_RANGE                       16:16
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_RXVHF_WOFFSET                     0x0
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_RXVHF_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_RXVHF_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_RXVHF_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_RXVHF_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_RXVHF_UNSET                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_RXVHF_SET                 _MK_ENUM_CONST(1)
+
+// Failed packet no: Points to the failed packet no
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_FAIL_PKT_NO_SHIFT                 _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_FAIL_PKT_NO_FIELD                 (_MK_MASK_CONST(0x3f) << APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_FAIL_PKT_NO_SHIFT)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_FAIL_PKT_NO_RANGE                 13:8
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_FAIL_PKT_NO_WOFFSET                       0x0
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_FAIL_PKT_NO_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_FAIL_PKT_NO_DEFAULT_MASK                  _MK_MASK_CONST(0x3f)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_FAIL_PKT_NO_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_FAIL_PKT_NO_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Failed RX byte index: Points to the Rx byte no. in  the current packet which fails
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_FAIL_RX_BYTE_SHIFT                        _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_FAIL_RX_BYTE_FIELD                        (_MK_MASK_CONST(0x3f) << APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_FAIL_RX_BYTE_SHIFT)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_FAIL_RX_BYTE_RANGE                        5:0
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_FAIL_RX_BYTE_WOFFSET                      0x0
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_FAIL_RX_BYTE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_FAIL_RX_BYTE_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_FAIL_RX_BYTE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_FAIL_RX_BYTE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_PP_USB_PHY_SELF_TEST_0  
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0                 _MK_ADDR_CONST(0x6c)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_WORD_COUNT                      0x1
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_RESET_VAL                       _MK_MASK_CONST(0x10150888)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_RESET_MASK                      _MK_MASK_CONST(0x3f3ffbff)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_READ_MASK                       _MK_MASK_CONST(0x3f3ffbff)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_WRITE_MASK                      _MK_MASK_CONST(0x3f3f7bf3)
+// Default: 0x10
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TEST_PKT_CNT_SHIFT                      _MK_SHIFT_CONST(24)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TEST_PKT_CNT_FIELD                      (_MK_MASK_CONST(0x3f) << APB_MISC_PP_USB_PHY_SELF_TEST_0_TEST_PKT_CNT_SHIFT)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TEST_PKT_CNT_RANGE                      29:24
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TEST_PKT_CNT_WOFFSET                    0x0
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TEST_PKT_CNT_DEFAULT                    _MK_MASK_CONST(0x10)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TEST_PKT_CNT_DEFAULT_MASK                       _MK_MASK_CONST(0x3f)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TEST_PKT_CNT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TEST_PKT_CNT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// default: 0x15
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_IPKT_DLY_SHIFT                  _MK_SHIFT_CONST(16)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_IPKT_DLY_FIELD                  (_MK_MASK_CONST(0x3f) << APB_MISC_PP_USB_PHY_SELF_TEST_0_IPKT_DLY_SHIFT)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_IPKT_DLY_RANGE                  21:16
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_IPKT_DLY_WOFFSET                        0x0
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_IPKT_DLY_DEFAULT                        _MK_MASK_CONST(0x15)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_IPKT_DLY_DEFAULT_MASK                   _MK_MASK_CONST(0x3f)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_IPKT_DLY_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_IPKT_DLY_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Status of Disconnect signal from PHY
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_DISCON_SHIFT                    _MK_SHIFT_CONST(15)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_DISCON_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_SELF_TEST_0_DISCON_SHIFT)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_DISCON_RANGE                    15:15
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_DISCON_WOFFSET                  0x0
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_DISCON_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_DISCON_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_DISCON_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_DISCON_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_DISCON_UNSET                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_DISCON_SET                      _MK_ENUM_CONST(1)
+
+// Default: 0
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_SOF_EN_SHIFT                    _MK_SHIFT_CONST(14)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_SOF_EN_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_SELF_TEST_0_SOF_EN_SHIFT)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_SOF_EN_RANGE                    14:14
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_SOF_EN_WOFFSET                  0x0
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_SOF_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_SOF_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_SOF_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_SOF_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_SOF_EN_DISABLE                  _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_SOF_EN_ENABLE                   _MK_ENUM_CONST(1)
+
+// Default: 0
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_DPPD_SHIFT                      _MK_SHIFT_CONST(13)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_DPPD_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_SELF_TEST_0_DPPD_SHIFT)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_DPPD_RANGE                      13:13
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_DPPD_WOFFSET                    0x0
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_DPPD_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_DPPD_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_DPPD_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_DPPD_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_DPPD_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_DPPD_ENABLE                     _MK_ENUM_CONST(1)
+
+// Default: 0
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_DMPD_SHIFT                      _MK_SHIFT_CONST(12)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_DMPD_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_SELF_TEST_0_DMPD_SHIFT)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_DMPD_RANGE                      12:12
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_DMPD_WOFFSET                    0x0
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_DMPD_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_DMPD_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_DMPD_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_DMPD_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_DMPD_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_DMPD_ENABLE                     _MK_ENUM_CONST(1)
+
+// Unused
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_DB16_8_SHIFT                    _MK_SHIFT_CONST(11)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_DB16_8_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_SELF_TEST_0_DB16_8_SHIFT)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_DB16_8_RANGE                    11:11
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_DB16_8_WOFFSET                  0x0
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_DB16_8_DEFAULT                  _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_DB16_8_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_DB16_8_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_DB16_8_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Operational Mode
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_OPMODE_SHIFT                    _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_OPMODE_FIELD                    (_MK_MASK_CONST(0x3) << APB_MISC_PP_USB_PHY_SELF_TEST_0_OPMODE_SHIFT)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_OPMODE_RANGE                    9:8
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_OPMODE_WOFFSET                  0x0
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_OPMODE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_OPMODE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_OPMODE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_OPMODE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Suspend: Default: 1
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_SUSP_SHIFT                      _MK_SHIFT_CONST(7)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_SUSP_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_SELF_TEST_0_SUSP_SHIFT)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_SUSP_RANGE                      7:7
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_SUSP_WOFFSET                    0x0
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_SUSP_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_SUSP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_SUSP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_SUSP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Term_select
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TERM_SHIFT                      _MK_SHIFT_CONST(6)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TERM_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_SELF_TEST_0_TERM_SHIFT)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TERM_RANGE                      6:6
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TERM_WOFFSET                    0x0
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TERM_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TERM_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TERM_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TERM_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// XCVR_select:
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_XCVR_SHIFT                      _MK_SHIFT_CONST(4)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_XCVR_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_USB_PHY_SELF_TEST_0_XCVR_SHIFT)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_XCVR_RANGE                      5:4
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_XCVR_WOFFSET                    0x0
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_XCVR_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_XCVR_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_XCVR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_XCVR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// When test is started, this status signal starts as  1 and is set to 0 if an error is detected. Can be sampled when TSTEND is  asserted.
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTPS_SHIFT                     _MK_SHIFT_CONST(3)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTPS_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTPS_SHIFT)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTPS_RANGE                     3:3
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTPS_WOFFSET                   0x0
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTPS_DEFAULT                   _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTPS_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTPS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTPS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTPS_UNSET                     _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTPS_SET                       _MK_ENUM_CONST(1)
+
+// Goes to 1 when the test finishes. At that time,  TSTPASS is valid and indicates the tests pass/fail status
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTEND_SHIFT                    _MK_SHIFT_CONST(2)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTEND_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTEND_SHIFT)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTEND_RANGE                    2:2
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTEND_WOFFSET                  0x0
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTEND_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTEND_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTEND_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTEND_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTEND_UNSET                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTEND_SET                      _MK_ENUM_CONST(1)
+
+// Sw writes a 1 to start the test. It writes a 0 to  end the test
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTON_SHIFT                     _MK_SHIFT_CONST(1)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTON_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTON_SHIFT)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTON_RANGE                     1:1
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTON_WOFFSET                   0x0
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTON_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTON_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTON_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTON_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTON_UNSET                     _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTON_SET                       _MK_ENUM_CONST(1)
+
+// Default: 0
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTENB_SHIFT                    _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTENB_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTENB_SHIFT)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTENB_RANGE                    0:0
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTENB_WOFFSET                  0x0
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTENB_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTENB_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTENB_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTENB_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTENB_DISABLE                  _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTENB_ENABLE                   _MK_ENUM_CONST(1)
+
+
+// Register APB_MISC_PP_USB_PHY_VBUS_SENSORS_0  
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0                      _MK_ADDR_CONST(0x70)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_WORD_COUNT                   0x1
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_RESET_MASK                   _MK_MASK_CONST(0x3f3f3f3f)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_READ_MASK                    _MK_MASK_CONST(0x3f3f3f3f)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_WRITE_MASK                   _MK_MASK_CONST(0x39393939)
+// A_VBUS_VLD debounce A/B select.
+// Selects between the two debounce values 
+// UTMIP_BIAS_DEBOUNCE_A or
+// UTMIP_BIAS_DEBOUNCE_B from the register
+// UTMIP_DEBOUNCE_CFG0.
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_DEB_SEL_B_SHIFT                   _MK_SHIFT_CONST(29)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_DEB_SEL_B_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_DEB_SEL_B_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_DEB_SEL_B_RANGE                   29:29
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_DEB_SEL_B_WOFFSET                 0x0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_DEB_SEL_B_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_DEB_SEL_B_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_DEB_SEL_B_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_DEB_SEL_B_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_DEB_SEL_B_SEL_A                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_DEB_SEL_B_SEL_B                   _MK_ENUM_CONST(1)
+
+// A_VBUS_VLD software value.
+// Software should write the appropriate
+// value (1/0) to set/unset the A_VBUS_VLD status.
+// This is only valid when A_VBUS_VLD_SW_EN is set.
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_VALUE_SHIFT                    _MK_SHIFT_CONST(28)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_VALUE_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_VALUE_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_VALUE_RANGE                    28:28
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_VALUE_WOFFSET                  0x0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_VALUE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_VALUE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_VALUE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_VALUE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_VALUE_UNSET                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_VALUE_SET                      _MK_ENUM_CONST(1)
+
+// A_VBUS_VLD software enable.
+// Enable Software Controlled A_VBUS_VLD.
+// Software sets this bit to drive the
+// value in A_VBUS_VLD_SW_VALUE to the USB
+// controller.
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_EN_SHIFT                       _MK_SHIFT_CONST(27)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_EN_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_EN_RANGE                       27:27
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_EN_WOFFSET                     0x0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// A_VBUS_VLD status.
+// This is set to 1 whenever A_VBUS_VLD sensor
+// output is 1.
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_STS_SHIFT                 _MK_SHIFT_CONST(26)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_STS_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_STS_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_STS_RANGE                 26:26
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_STS_WOFFSET                       0x0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_STS_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_STS_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_STS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_STS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_STS_UNSET                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_STS_SET                   _MK_ENUM_CONST(1)
+
+// A_VBUS_VLD change detect.
+// This field is set by hardware whenever a change
+// is detected in the value of A_VBUS_VLD.
+// software writes a 1 to clear it
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_CHG_DET_SHIFT                     _MK_SHIFT_CONST(25)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_CHG_DET_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_CHG_DET_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_CHG_DET_RANGE                     25:25
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_CHG_DET_WOFFSET                   0x0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_CHG_DET_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_CHG_DET_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_CHG_DET_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_CHG_DET_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_CHG_DET_UNSET                     _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_CHG_DET_SET                       _MK_ENUM_CONST(1)
+
+// A_VBUS_VLD interrupt enable.
+// If this field is set to 1, an interrupt is
+// generated whenever A_VBUS_VLD_CHG_DET is set to 1.
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_INT_EN_SHIFT                      _MK_SHIFT_CONST(24)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_INT_EN_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_INT_EN_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_INT_EN_RANGE                      24:24
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_INT_EN_WOFFSET                    0x0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_INT_EN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_INT_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_INT_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_INT_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_INT_EN_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_INT_EN_ENABLE                     _MK_ENUM_CONST(1)
+
+// A_SESS_VLD debounce A/B select.
+// Selects between the two debounce values 
+// UTMIP_BIAS_DEBOUNCE_A or
+// UTMIP_BIAS_DEBOUNCE_B from the register
+// UTMIP_DEBOUNCE_CFG0.
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_DEB_SEL_B_SHIFT                   _MK_SHIFT_CONST(21)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_DEB_SEL_B_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_DEB_SEL_B_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_DEB_SEL_B_RANGE                   21:21
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_DEB_SEL_B_WOFFSET                 0x0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_DEB_SEL_B_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_DEB_SEL_B_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_DEB_SEL_B_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_DEB_SEL_B_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_DEB_SEL_B_SEL_A                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_DEB_SEL_B_SEL_B                   _MK_ENUM_CONST(1)
+
+// A_SESS_VLD software value.
+// Software should write the appropriate
+// value (1/0) to set/unset the A_SESS_VLD status.
+// This is only valid when A_SESS_VLD_SW_EN is set.
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_VALUE_SHIFT                    _MK_SHIFT_CONST(20)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_VALUE_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_VALUE_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_VALUE_RANGE                    20:20
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_VALUE_WOFFSET                  0x0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_VALUE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_VALUE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_VALUE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_VALUE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_VALUE_UNSET                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_VALUE_SET                      _MK_ENUM_CONST(1)
+
+// A_SESS_VLD software enable.
+// Enable Software Controlled A_SESS_VLD.
+// Software sets this bit to drive the
+// value in A_SESS_VLD_SW_VALUE to the USB
+// controller.
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_EN_SHIFT                       _MK_SHIFT_CONST(19)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_EN_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_EN_RANGE                       19:19
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_EN_WOFFSET                     0x0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// A_SESS_VLD status.
+// This is set to 1 whenever A_SESS_VLD sensor
+// output is 1.
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_STS_SHIFT                 _MK_SHIFT_CONST(18)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_STS_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_STS_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_STS_RANGE                 18:18
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_STS_WOFFSET                       0x0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_STS_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_STS_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_STS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_STS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_STS_UNSET                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_STS_SET                   _MK_ENUM_CONST(1)
+
+// A_SESS_VLD change detect.
+// This field is set by hardware whenever a change
+// is detected in the value of A_SESS_VLD.
+// software writes a 1 to clear it
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_CHG_DET_SHIFT                     _MK_SHIFT_CONST(17)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_CHG_DET_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_CHG_DET_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_CHG_DET_RANGE                     17:17
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_CHG_DET_WOFFSET                   0x0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_CHG_DET_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_CHG_DET_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_CHG_DET_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_CHG_DET_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_CHG_DET_UNSET                     _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_CHG_DET_SET                       _MK_ENUM_CONST(1)
+
+// A_SESS_VLD interrupt enable.
+// If this field is set to 1, an interrupt is
+// generated whenever A_SESS_VLD_CHG_DET is set to 1.
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_INT_EN_SHIFT                      _MK_SHIFT_CONST(16)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_INT_EN_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_INT_EN_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_INT_EN_RANGE                      16:16
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_INT_EN_WOFFSET                    0x0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_INT_EN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_INT_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_INT_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_INT_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_INT_EN_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_INT_EN_ENABLE                     _MK_ENUM_CONST(1)
+
+// B_SESS_VLD debounce A/B select.
+// Selects between the two debounce values 
+// UTMIP_BIAS_DEBOUNCE_A or
+// UTMIP_BIAS_DEBOUNCE_B from the register
+// UTMIP_DEBOUNCE_CFG0.
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_DEB_SEL_B_SHIFT                   _MK_SHIFT_CONST(13)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_DEB_SEL_B_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_DEB_SEL_B_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_DEB_SEL_B_RANGE                   13:13
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_DEB_SEL_B_WOFFSET                 0x0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_DEB_SEL_B_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_DEB_SEL_B_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_DEB_SEL_B_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_DEB_SEL_B_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_DEB_SEL_B_SEL_A                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_DEB_SEL_B_SEL_B                   _MK_ENUM_CONST(1)
+
+// B_SESS_VLD software value.
+// Software should write the appropriate
+// value (1/0) to set/unset the B_SESS_VLD status.
+// This is only valid when B_SESS_VLD_SW_EN is set.
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_VALUE_SHIFT                    _MK_SHIFT_CONST(12)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_VALUE_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_VALUE_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_VALUE_RANGE                    12:12
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_VALUE_WOFFSET                  0x0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_VALUE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_VALUE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_VALUE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_VALUE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_VALUE_UNSET                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_VALUE_SET                      _MK_ENUM_CONST(1)
+
+// B_SESS_VLD software enable.
+// Enable Software Controlled B_SESS_VLD.
+// Software sets this bit to drive the
+// value in B_SESS_VLD_SW_VALUE to the USB
+// controller.
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_EN_SHIFT                       _MK_SHIFT_CONST(11)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_EN_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_EN_RANGE                       11:11
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_EN_WOFFSET                     0x0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// B_SESS_VLD status.
+// This is set to 1 whenever B_SESS_VLD sensor
+// output is 1.
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_STS_SHIFT                 _MK_SHIFT_CONST(10)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_STS_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_STS_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_STS_RANGE                 10:10
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_STS_WOFFSET                       0x0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_STS_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_STS_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_STS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_STS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_STS_UNSET                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_STS_SET                   _MK_ENUM_CONST(1)
+
+// B_SESS_VLD change detect.
+// This field is set by hardware whenever a change
+// is detected in the value of B_SESS_VLD.
+// software writes a 1 to clear it
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_CHG_DET_SHIFT                     _MK_SHIFT_CONST(9)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_CHG_DET_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_CHG_DET_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_CHG_DET_RANGE                     9:9
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_CHG_DET_WOFFSET                   0x0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_CHG_DET_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_CHG_DET_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_CHG_DET_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_CHG_DET_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_CHG_DET_UNSET                     _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_CHG_DET_SET                       _MK_ENUM_CONST(1)
+
+// B_SESS_VLD interrupt enable.
+// If this field is set to 1, an interrupt is
+// generated whenever B_SESS_VLD_CHG_DET is set to 1.
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_INT_EN_SHIFT                      _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_INT_EN_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_INT_EN_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_INT_EN_RANGE                      8:8
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_INT_EN_WOFFSET                    0x0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_INT_EN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_INT_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_INT_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_INT_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_INT_EN_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_INT_EN_ENABLE                     _MK_ENUM_CONST(1)
+
+// B_SESS_END debounce A/B select
+// Selects between the two debounce values 
+// UTMIP_BIAS_DEBOUNCE_A or
+// UTMIP_BIAS_DEBOUNCE_B from the register
+// UTMIP_DEBOUNCE_CFG0.
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_DEB_SEL_B_SHIFT                   _MK_SHIFT_CONST(5)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_DEB_SEL_B_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_DEB_SEL_B_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_DEB_SEL_B_RANGE                   5:5
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_DEB_SEL_B_WOFFSET                 0x0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_DEB_SEL_B_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_DEB_SEL_B_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_DEB_SEL_B_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_DEB_SEL_B_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_DEB_SEL_B_SEL_A                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_DEB_SEL_B_SEL_B                   _MK_ENUM_CONST(1)
+
+// B_SESS_END software value
+// Software should write the appropriate
+// value (1/0) to set/unset the B_SESS_END status.
+// This is only valid when B_SESS_END_SW_EN is set.
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_VALUE_SHIFT                    _MK_SHIFT_CONST(4)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_VALUE_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_VALUE_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_VALUE_RANGE                    4:4
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_VALUE_WOFFSET                  0x0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_VALUE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_VALUE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_VALUE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_VALUE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_VALUE_UNSET                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_VALUE_SET                      _MK_ENUM_CONST(1)
+
+// B_SESS_END software enable.
+// Enable Software Controlled B_SESS_END
+// Software sets this bit to drive the
+// value in B_SESS_END_SW_VALUE to the USB
+// controller.
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_EN_SHIFT                       _MK_SHIFT_CONST(3)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_EN_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_EN_RANGE                       3:3
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_EN_WOFFSET                     0x0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// B_SESS_END status.
+// This is set to 1 whenever B_SESS_END sensor
+// output is 1.
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_STS_SHIFT                 _MK_SHIFT_CONST(2)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_STS_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_STS_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_STS_RANGE                 2:2
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_STS_WOFFSET                       0x0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_STS_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_STS_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_STS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_STS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_STS_UNSET                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_STS_SET                   _MK_ENUM_CONST(1)
+
+// B_SESS_END change detect.
+// This field is set by hardware whenever a change
+// is detected in the value of B_SESS_END.
+// software writes a 1 to clear it
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_CHG_DET_SHIFT                     _MK_SHIFT_CONST(1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_CHG_DET_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_CHG_DET_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_CHG_DET_RANGE                     1:1
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_CHG_DET_WOFFSET                   0x0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_CHG_DET_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_CHG_DET_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_CHG_DET_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_CHG_DET_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_CHG_DET_UNSET                     _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_CHG_DET_SET                       _MK_ENUM_CONST(1)
+
+// B_SESS_END interrupt enable
+// If this field is set to 1, an interrupt is
+// generated whenever B_SESS_END_CHG_DET is set to 1.
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_INT_EN_SHIFT                      _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_INT_EN_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_INT_EN_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_INT_EN_RANGE                      0:0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_INT_EN_WOFFSET                    0x0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_INT_EN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_INT_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_INT_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_INT_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_INT_EN_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_INT_EN_ENABLE                     _MK_ENUM_CONST(1)
+
+
+// Register APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0  
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0                    _MK_ADDR_CONST(0x74)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_WORD_COUNT                         0x1
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_RESET_VAL                  _MK_MASK_CONST(0x6000000)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_RESET_MASK                         _MK_MASK_CONST(0x3f3f3f3f)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_READ_MASK                  _MK_MASK_CONST(0x3f3f3f3f)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_WRITE_MASK                         _MK_MASK_CONST(0x3f393939)
+// HS Tx to Tx inter-packet delay counter.
+// Software should not change this.
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_IP_DELAY_TX2TX_HS_SHIFT                    _MK_SHIFT_CONST(24)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_IP_DELAY_TX2TX_HS_FIELD                    (_MK_MASK_CONST(0x3f) << APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_IP_DELAY_TX2TX_HS_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_IP_DELAY_TX2TX_HS_RANGE                    29:24
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_IP_DELAY_TX2TX_HS_WOFFSET                  0x0
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_IP_DELAY_TX2TX_HS_DEFAULT                  _MK_MASK_CONST(0x6)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_IP_DELAY_TX2TX_HS_DEFAULT_MASK                     _MK_MASK_CONST(0x3f)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_IP_DELAY_TX2TX_HS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_IP_DELAY_TX2TX_HS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// VDAT_DET debounce A/B select.
+// Selects between the two debounce values 
+// UTMIP_BIAS_DEBOUNCE_A or
+// UTMIP_BIAS_DEBOUNCE_B from the register
+// UTMIP_DEBOUNCE_CFG0.
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_DEB_SEL_B_SHIFT                   _MK_SHIFT_CONST(21)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_DEB_SEL_B_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_DEB_SEL_B_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_DEB_SEL_B_RANGE                   21:21
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_DEB_SEL_B_WOFFSET                 0x0
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_DEB_SEL_B_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_DEB_SEL_B_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_DEB_SEL_B_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_DEB_SEL_B_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_DEB_SEL_B_SEL_A                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_DEB_SEL_B_SEL_B                   _MK_ENUM_CONST(1)
+
+// VDAT_DET software value.
+// Software should write the appropriate
+// value (1/0) to set/unset the VDAT_DET status.
+// This is only valid when VDAT_DET_SW_EN is set.
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_VALUE_SHIFT                    _MK_SHIFT_CONST(20)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_VALUE_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_VALUE_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_VALUE_RANGE                    20:20
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_VALUE_WOFFSET                  0x0
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_VALUE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_VALUE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_VALUE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_VALUE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_VALUE_UNSET                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_VALUE_SET                      _MK_ENUM_CONST(1)
+
+// VDAT_DET software enable.
+// Enable Software Controlled VDAT_DET.
+// Software sets this bit to drive the
+// value in VDAT_DET_SW_VALUE to the USB
+// controller
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_EN_SHIFT                       _MK_SHIFT_CONST(19)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_EN_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_EN_RANGE                       19:19
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_EN_WOFFSET                     0x0
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// VDAT_DET status.
+// This is set to 1 whenever VDAT_DET sensor
+// output is 1.
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_STS_SHIFT                 _MK_SHIFT_CONST(18)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_STS_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_STS_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_STS_RANGE                 18:18
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_STS_WOFFSET                       0x0
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_STS_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_STS_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_STS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_STS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_STS_UNSET                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_STS_SET                   _MK_ENUM_CONST(1)
+
+// VDAT_DET change detect.
+// This field is set by hardware whenever a change
+// is detected in the value of VDAT_DET.
+// software writes a 1 to clear it
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_CHG_DET_SHIFT                     _MK_SHIFT_CONST(17)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_CHG_DET_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_CHG_DET_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_CHG_DET_RANGE                     17:17
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_CHG_DET_WOFFSET                   0x0
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_CHG_DET_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_CHG_DET_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_CHG_DET_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_CHG_DET_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_CHG_DET_UNSET                     _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_CHG_DET_SET                       _MK_ENUM_CONST(1)
+
+// VDAT_DET interrupt enable.
+// If this field is set to 1, an interrupt is
+// generated whenever VDAT_DET_CHG_DET is set to 1.
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_INT_EN_SHIFT                      _MK_SHIFT_CONST(16)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_INT_EN_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_INT_EN_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_INT_EN_RANGE                      16:16
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_INT_EN_WOFFSET                    0x0
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_INT_EN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_INT_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_INT_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_INT_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_INT_EN_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_INT_EN_ENABLE                     _MK_ENUM_CONST(1)
+
+// VBUS_WAKEUP debounce A/B select.
+// Selects between the two debounce values 
+// UTMIP_BIAS_DEBOUNCE_A or
+// UTMIP_BIAS_DEBOUNCE_B from the register
+// UTMIP_DEBOUNCE_CFG0.
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_DEB_SEL_B_SHIFT                        _MK_SHIFT_CONST(13)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_DEB_SEL_B_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_DEB_SEL_B_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_DEB_SEL_B_RANGE                        13:13
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_DEB_SEL_B_WOFFSET                      0x0
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_DEB_SEL_B_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_DEB_SEL_B_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_DEB_SEL_B_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_DEB_SEL_B_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_DEB_SEL_B_SEL_A                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_DEB_SEL_B_SEL_B                        _MK_ENUM_CONST(1)
+
+// VBUS_WAKEUP software value.
+// Software should write the appropriate
+// value (1/0) to set/unset the VBUS_WAKEUP status.
+// This is only valid when VBUS_WAKEUP_SW_EN is set.
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_VALUE_SHIFT                 _MK_SHIFT_CONST(12)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_VALUE_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_VALUE_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_VALUE_RANGE                 12:12
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_VALUE_WOFFSET                       0x0
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_VALUE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_VALUE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_VALUE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_VALUE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_VALUE_UNSET                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_VALUE_SET                   _MK_ENUM_CONST(1)
+
+// VBUS_WAKEUP software enable.
+// Enable Software Controlled VBUS_WAKEUP.
+// Software sets this bit to drive the
+// value in VBUS_WAKEUP_SW_VALUE to the USB
+// controller.
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_EN_SHIFT                    _MK_SHIFT_CONST(11)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_EN_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_EN_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_EN_RANGE                    11:11
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_EN_WOFFSET                  0x0
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_EN_DISABLE                  _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_EN_ENABLE                   _MK_ENUM_CONST(1)
+
+// VBUS_WAKEUP status.
+// This is set to 1 whenever VBUS_WAKEUP sensor
+// output is 1.
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_STS_SHIFT                      _MK_SHIFT_CONST(10)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_STS_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_STS_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_STS_RANGE                      10:10
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_STS_WOFFSET                    0x0
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_STS_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_STS_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_STS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_STS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_STS_UNSET                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_STS_SET                        _MK_ENUM_CONST(1)
+
+// VBUS_WAKEUP change detect.
+// This field is set by hardware whenever a change
+// is detected in the value of VBUS_WAKEUP.
+// software writes a 1 to clear it
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_CHG_DET_SHIFT                  _MK_SHIFT_CONST(9)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_CHG_DET_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_CHG_DET_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_CHG_DET_RANGE                  9:9
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_CHG_DET_WOFFSET                        0x0
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_CHG_DET_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_CHG_DET_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_CHG_DET_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_CHG_DET_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_CHG_DET_UNSET                  _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_CHG_DET_SET                    _MK_ENUM_CONST(1)
+
+// VBUS_WAKEUP interrupt enable
+// If this field is set to 1, an interrupt is
+// generated whenever VBUS_WAKEUP_CHG_DET is set to 1.
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_INT_EN_SHIFT                   _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_INT_EN_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_INT_EN_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_INT_EN_RANGE                   8:8
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_INT_EN_WOFFSET                 0x0
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_INT_EN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_INT_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_INT_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_INT_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_INT_EN_DISABLE                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_INT_EN_ENABLE                  _MK_ENUM_CONST(1)
+
+// ID debounce A/B select.
+// Selects between the two debounce values 
+// UTMIP_BIAS_DEBOUNCE_A or
+// UTMIP_BIAS_DEBOUNCE_B from the register
+// UTMIP_DEBOUNCE_CFG0.
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_DEB_SEL_B_SHIFT                 _MK_SHIFT_CONST(5)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_DEB_SEL_B_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_DEB_SEL_B_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_DEB_SEL_B_RANGE                 5:5
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_DEB_SEL_B_WOFFSET                       0x0
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_DEB_SEL_B_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_DEB_SEL_B_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_DEB_SEL_B_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_DEB_SEL_B_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_DEB_SEL_B_SEL_A                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_DEB_SEL_B_SEL_B                 _MK_ENUM_CONST(1)
+
+// ID software value.
+// Software should write the appropriate
+// value (1/0) to set/unset the ID status.
+// This is only valid when ID_SW_EN is set.
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_VALUE_SHIFT                  _MK_SHIFT_CONST(4)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_VALUE_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_VALUE_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_VALUE_RANGE                  4:4
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_VALUE_WOFFSET                        0x0
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_VALUE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_VALUE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_VALUE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_VALUE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_VALUE_UNSET                  _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_VALUE_SET                    _MK_ENUM_CONST(1)
+
+// ID software enable.
+// Enable Software Controlled ID.
+// Software sets this bit to drive the
+// value in ID_SW_VALUE to the USB
+// controller
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_EN_SHIFT                     _MK_SHIFT_CONST(3)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_EN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_EN_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_EN_RANGE                     3:3
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_EN_WOFFSET                   0x0
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// ID status.
+// This is set to 1 whenever ID sensor
+// output is 1.
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_STS_SHIFT                       _MK_SHIFT_CONST(2)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_STS_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_STS_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_STS_RANGE                       2:2
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_STS_WOFFSET                     0x0
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_STS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_STS_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_STS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_STS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_STS_UNSET                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_STS_SET                 _MK_ENUM_CONST(1)
+
+// ID change detect.
+// This field is set by hardware whenever a change
+// is detected in the value of ID.
+// software writes a 1 to clear it
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_CHG_DET_SHIFT                   _MK_SHIFT_CONST(1)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_CHG_DET_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_CHG_DET_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_CHG_DET_RANGE                   1:1
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_CHG_DET_WOFFSET                 0x0
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_CHG_DET_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_CHG_DET_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_CHG_DET_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_CHG_DET_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_CHG_DET_UNSET                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_CHG_DET_SET                     _MK_ENUM_CONST(1)
+
+// ID interrupt enable.
+// If this field is set to 1, an interrupt is
+// generated whenever ID_CHG_DET is set to 1.
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_INT_EN_SHIFT                    _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_INT_EN_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_INT_EN_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_INT_EN_RANGE                    0:0
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_INT_EN_WOFFSET                  0x0
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_INT_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_INT_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_INT_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_INT_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_INT_EN_DISABLE                  _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_INT_EN_ENABLE                   _MK_ENUM_CONST(1)
+
+
+// Register APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0  
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0                      _MK_ADDR_CONST(0x78)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_WORD_COUNT                   0x1
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_WRITE_MASK                   _MK_MASK_CONST(0xffffff80)
+// Reserved
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_RSVD31_7_SHIFT                       _MK_SHIFT_CONST(7)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_RSVD31_7_FIELD                       (_MK_MASK_CONST(0x1ffffff) << APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_RSVD31_7_SHIFT)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_RSVD31_7_RANGE                       31:7
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_RSVD31_7_WOFFSET                     0x0
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_RSVD31_7_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_RSVD31_7_DEFAULT_MASK                        _MK_MASK_CONST(0x1ffffff)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_RSVD31_7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_RSVD31_7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_RSVD31_7_UNSET                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_RSVD31_7_SET                 _MK_ENUM_CONST(1)
+
+// Avalid alternate status
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_AVALID_ALT_SHIFT                     _MK_SHIFT_CONST(6)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_AVALID_ALT_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_AVALID_ALT_SHIFT)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_AVALID_ALT_RANGE                     6:6
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_AVALID_ALT_WOFFSET                   0x0
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_AVALID_ALT_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_AVALID_ALT_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_AVALID_ALT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_AVALID_ALT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_AVALID_ALT_UNSET                     _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_AVALID_ALT_SET                       _MK_ENUM_CONST(1)
+
+// Bvalid alternate status
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_BVALID_ALT_SHIFT                     _MK_SHIFT_CONST(5)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_BVALID_ALT_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_BVALID_ALT_SHIFT)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_BVALID_ALT_RANGE                     5:5
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_BVALID_ALT_WOFFSET                   0x0
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_BVALID_ALT_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_BVALID_ALT_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_BVALID_ALT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_BVALID_ALT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_BVALID_ALT_UNSET                     _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_BVALID_ALT_SET                       _MK_ENUM_CONST(1)
+
+// ID alternate status
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_ID_DIG_ALT_SHIFT                     _MK_SHIFT_CONST(4)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_ID_DIG_ALT_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_ID_DIG_ALT_SHIFT)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_ID_DIG_ALT_RANGE                     4:4
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_ID_DIG_ALT_WOFFSET                   0x0
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_ID_DIG_ALT_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_ID_DIG_ALT_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_ID_DIG_ALT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_ID_DIG_ALT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_ID_DIG_ALT_UNSET                     _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_ID_DIG_ALT_SET                       _MK_ENUM_CONST(1)
+
+// Session end alternate status
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_SESS_END_ALT_SHIFT                   _MK_SHIFT_CONST(3)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_SESS_END_ALT_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_SESS_END_ALT_SHIFT)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_SESS_END_ALT_RANGE                   3:3
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_SESS_END_ALT_WOFFSET                 0x0
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_SESS_END_ALT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_SESS_END_ALT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_SESS_END_ALT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_SESS_END_ALT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_SESS_END_ALT_UNSET                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_SESS_END_ALT_SET                     _MK_ENUM_CONST(1)
+
+// Static GPI alternate status
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_STATIC_GPI_ALT_SHIFT                 _MK_SHIFT_CONST(2)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_STATIC_GPI_ALT_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_STATIC_GPI_ALT_SHIFT)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_STATIC_GPI_ALT_RANGE                 2:2
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_STATIC_GPI_ALT_WOFFSET                       0x0
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_STATIC_GPI_ALT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_STATIC_GPI_ALT_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_STATIC_GPI_ALT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_STATIC_GPI_ALT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_STATIC_GPI_ALT_UNSET                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_STATIC_GPI_ALT_SET                   _MK_ENUM_CONST(1)
+
+// VBus valid alternate status
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_VBUS_VALID_ALT_SHIFT                 _MK_SHIFT_CONST(1)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_VBUS_VALID_ALT_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_VBUS_VALID_ALT_SHIFT)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_VBUS_VALID_ALT_RANGE                 1:1
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_VBUS_VALID_ALT_WOFFSET                       0x0
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_VBUS_VALID_ALT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_VBUS_VALID_ALT_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_VBUS_VALID_ALT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_VBUS_VALID_ALT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_VBUS_VALID_ALT_UNSET                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_VBUS_VALID_ALT_SET                   _MK_ENUM_CONST(1)
+
+// Vbus wakeup alternate status
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_VBUS_WAKEUP_ALT_SHIFT                        _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_VBUS_WAKEUP_ALT_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_VBUS_WAKEUP_ALT_SHIFT)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_VBUS_WAKEUP_ALT_RANGE                        0:0
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_VBUS_WAKEUP_ALT_WOFFSET                      0x0
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_VBUS_WAKEUP_ALT_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_VBUS_WAKEUP_ALT_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_VBUS_WAKEUP_ALT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_VBUS_WAKEUP_ALT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_VBUS_WAKEUP_ALT_UNSET                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_VBUS_WAKEUP_ALT_SET                  _MK_ENUM_CONST(1)
+
+
+// Register APB_MISC_PP_MISC_SAVE_THE_DAY_0  
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0                 _MK_ADDR_CONST(0x7c)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_WORD_COUNT                      0x1
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Reserved
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_A_SHIFT                    _MK_SHIFT_CONST(24)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_A_FIELD                    (_MK_MASK_CONST(0xff) << APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_A_SHIFT)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_A_RANGE                    31:24
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_A_WOFFSET                  0x0
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_A_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_A_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_A_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_A_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Reserved
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_B_SHIFT                    _MK_SHIFT_CONST(16)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_B_FIELD                    (_MK_MASK_CONST(0xff) << APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_B_SHIFT)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_B_RANGE                    23:16
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_B_WOFFSET                  0x0
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_B_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_B_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_B_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_B_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Reserved
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_C_SHIFT                    _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_C_FIELD                    (_MK_MASK_CONST(0xff) << APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_C_SHIFT)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_C_RANGE                    15:8
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_C_WOFFSET                  0x0
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_C_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_C_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_C_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_C_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Reserved
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_D_SHIFT                    _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_D_FIELD                    (_MK_MASK_CONST(0xff) << APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_D_SHIFT)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_D_RANGE                    7:0
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_D_WOFFSET                  0x0
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_D_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_D_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_D_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_D_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_PP_PIN_MUX_CTL_A_0  
+#define APB_MISC_PP_PIN_MUX_CTL_A_0                     _MK_ADDR_CONST(0x80)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_WORD_COUNT                  0x1
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RSVD_1_SHIFT                        _MK_SHIFT_CONST(30)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RSVD_1_FIELD                        (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_A_0_RSVD_1_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RSVD_1_RANGE                        31:30
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RSVD_1_WOFFSET                      0x0
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RSVD_1_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RSVD_1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RSVD_1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RSVD_1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCE_SEL_SHIFT                      _MK_SHIFT_CONST(28)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCE_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_A_0_KBCE_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCE_SEL_RANGE                      29:28
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCE_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCE_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCE_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCE_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCE_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCE_SEL_KBC                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCE_SEL_RSVD1                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCE_SEL_SDIO1                      _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCE_SEL_RSVD2                      _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCF_SEL_SHIFT                      _MK_SHIFT_CONST(26)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCF_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_A_0_KBCF_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCF_SEL_RANGE                      27:26
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCF_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCF_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCF_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCF_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCF_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCF_SEL_KBC                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCF_SEL_RSVD1                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCF_SEL_RSVD2                      _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCF_SEL_MIO                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATA_SEL_SHIFT                       _MK_SHIFT_CONST(24)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATA_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_A_0_ATA_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATA_SEL_RANGE                       25:24
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATA_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATA_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATA_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATA_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATA_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATA_SEL_IDE                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATA_SEL_NAND                        _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATA_SEL_RSVD                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATA_SEL_NAND_ALT                    _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATC_SEL_SHIFT                       _MK_SHIFT_CONST(22)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATC_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_A_0_ATC_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATC_SEL_RANGE                       23:22
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATC_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATC_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATC_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATC_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATC_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATC_SEL_IDE                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATC_SEL_NAND                        _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATC_SEL_XIO                 _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATC_SEL_RSVD                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATD_SEL_SHIFT                       _MK_SHIFT_CONST(20)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATD_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_A_0_ATD_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATD_SEL_RANGE                       21:20
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATD_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATD_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATD_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATD_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATD_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATD_SEL_IDE                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATD_SEL_NAND                        _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATD_SEL_NAND_ALT                    _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATD_SEL_HSMMC                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RSVD_2_SHIFT                        _MK_SHIFT_CONST(18)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RSVD_2_FIELD                        (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_A_0_RSVD_2_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RSVD_2_RANGE                        19:18
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RSVD_2_WOFFSET                      0x0
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RSVD_2_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RSVD_2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RSVD_2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RSVD_2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATB_SEL_SHIFT                       _MK_SHIFT_CONST(16)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATB_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_A_0_ATB_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATB_SEL_RANGE                       17:16
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATB_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATB_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATB_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATB_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATB_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATB_SEL_IDE                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATB_SEL_NAND                        _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATB_SEL_NAND_ALT                    _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATB_SEL_HSMMC                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RM_SEL_SHIFT                        _MK_SHIFT_CONST(14)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RM_SEL_FIELD                        (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_A_0_RM_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RM_SEL_RANGE                        15:14
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RM_SEL_WOFFSET                      0x0
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RM_SEL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RM_SEL_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RM_SEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RM_SEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RM_SEL_I2C                  _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RM_SEL_RSVD1                        _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RM_SEL_RSVD2                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RM_SEL_RSVD3                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATE_SEL_SHIFT                       _MK_SHIFT_CONST(12)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATE_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_A_0_ATE_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATE_SEL_RANGE                       13:12
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATE_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATE_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATE_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATE_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATE_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATE_SEL_IDE                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATE_SEL_NAND                        _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATE_SEL_NAND_ALT                    _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATE_SEL_HSMMC                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RSVD_3_SHIFT                        _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RSVD_3_FIELD                        (_MK_MASK_CONST(0xf) << APB_MISC_PP_PIN_MUX_CTL_A_0_RSVD_3_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RSVD_3_RANGE                        11:8
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RSVD_3_WOFFSET                      0x0
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RSVD_3_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RSVD_3_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RSVD_3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RSVD_3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAD_SEL_SHIFT                       _MK_SHIFT_CONST(6)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAD_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_A_0_UAD_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAD_SEL_RANGE                       7:6
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAD_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAD_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAD_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAD_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAD_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAD_SEL_IRDA                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAD_SEL_SPDIF                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAD_SEL_UARTA                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAD_SEL_SFLASH                      _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAC_SEL_SHIFT                       _MK_SHIFT_CONST(4)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAC_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_A_0_UAC_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAC_SEL_RANGE                       5:4
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAC_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAC_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAC_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAC_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAC_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAC_SEL_RSVD1                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAC_SEL_RSVD2                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAC_SEL_RSVD3                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAC_SEL_RSVD4                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAB_SEL_SHIFT                       _MK_SHIFT_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAB_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_A_0_UAB_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAB_SEL_RANGE                       3:2
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAB_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAB_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAB_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAB_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAB_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAB_SEL_SPI2                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAB_SEL_MIPI_HS                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAB_SEL_UARTA                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAB_SEL_UARTB                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAA_SEL_SHIFT                       _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAA_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_A_0_UAA_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAA_SEL_RANGE                       1:0
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAA_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAA_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAA_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAA_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAA_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAA_SEL_SPI3                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAA_SEL_MIPI_HS                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAA_SEL_UARTA                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAA_SEL_UARTA_ALT3                  _MK_ENUM_CONST(3)
+
+
+// Register APB_MISC_PP_PIN_MUX_CTL_B_0  
+#define APB_MISC_PP_PIN_MUX_CTL_B_0                     _MK_ADDR_CONST(0x84)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_WORD_COUNT                  0x1
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_RESET_MASK                  _MK_MASK_CONST(0xfcffffff)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_READ_MASK                   _MK_MASK_CONST(0xfcffffff)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_WRITE_MASK                  _MK_MASK_CONST(0xfcffffff)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTE_SEL_SHIFT                       _MK_SHIFT_CONST(30)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTE_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_B_0_DTE_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTE_SEL_RANGE                       31:30
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTE_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTE_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTE_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTE_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTE_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTE_SEL_RSVD1                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTE_SEL_RSVD2                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTE_SEL_VI                  _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTE_SEL_SPI1                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTD_SEL_SHIFT                       _MK_SHIFT_CONST(28)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTD_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_B_0_DTD_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTD_SEL_RANGE                       29:28
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTD_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTD_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTD_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTD_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTD_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTD_SEL_RSVD1                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTD_SEL_SDIO1                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTD_SEL_VI                  _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTD_SEL_RSVD4                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTC_SEL_SHIFT                       _MK_SHIFT_CONST(26)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTC_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_B_0_DTC_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTC_SEL_RANGE                       27:26
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTC_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTC_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTC_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTC_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTC_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTC_SEL_RSVD1                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTC_SEL_RSVD2                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTC_SEL_VI                  _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTC_SEL_RSVD4                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTB_SEL_SHIFT                       _MK_SHIFT_CONST(22)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTB_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_B_0_DTB_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTB_SEL_RANGE                       23:22
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTB_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTB_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTB_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTB_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTB_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTB_SEL_RSVD1                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTB_SEL_RSVD2                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTB_SEL_VI                  _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTB_SEL_SPI1                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTA_SEL_SHIFT                       _MK_SHIFT_CONST(20)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTA_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_B_0_DTA_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTA_SEL_RANGE                       21:20
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTA_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTA_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTA_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTA_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTA_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTA_SEL_RSVD1                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTA_SEL_SDIO1                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTA_SEL_VI                  _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTA_SEL_RSVD4                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCB_SEL_SHIFT                       _MK_SHIFT_CONST(18)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCB_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_B_0_UCB_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCB_SEL_RANGE                       19:18
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCB_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCB_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCB_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCB_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCB_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCB_SEL_PWM0                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCB_SEL_RSVD2                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCB_SEL_RSVD3                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCB_SEL_UARTC                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCA_SEL_SHIFT                       _MK_SHIFT_CONST(16)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCA_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_B_0_UCA_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCA_SEL_RANGE                       17:16
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCA_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCA_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCA_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCA_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCA_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCA_SEL_UARTC                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCA_SEL_RSVD1                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCA_SEL_RSVD2                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCA_SEL_RSVD3                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXK_SEL_SHIFT                      _MK_SHIFT_CONST(14)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXK_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_B_0_SLXK_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXK_SEL_RANGE                      15:14
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXK_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXK_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXK_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXK_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXK_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXK_SEL_SDIO1                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXK_SEL_SLINK4B                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXK_SEL_SDIO2                      _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXK_SEL_SPI2                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXD_SEL_SHIFT                      _MK_SHIFT_CONST(12)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXD_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_B_0_SLXD_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXD_SEL_RANGE                      13:12
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXD_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXD_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXD_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXD_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXD_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXD_SEL_SDIO1                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXD_SEL_SLINK4B                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXD_SEL_SPDIF                      _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXD_SEL_SPI2                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXC_SEL_SHIFT                      _MK_SHIFT_CONST(10)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXC_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_B_0_SLXC_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXC_SEL_RANGE                      11:10
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXC_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXC_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXC_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXC_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXC_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXC_SEL_SDIO1                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXC_SEL_SLINK4B                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXC_SEL_SPDIF                      _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXC_SEL_SPI2                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXB_SEL_SHIFT                      _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXB_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_B_0_SLXB_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXB_SEL_RANGE                      9:8
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXB_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXB_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXB_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXB_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXB_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXB_SEL_SDIO1                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXB_SEL_SLINK4B                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXB_SEL_SDIO2                      _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXB_SEL_SPI2                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXA_SEL_SHIFT                      _MK_SHIFT_CONST(6)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXA_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_B_0_SLXA_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXA_SEL_RANGE                      7:6
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXA_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXA_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXA_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXA_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXA_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXA_SEL_SDIO1                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXA_SEL_SLINK4B                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXA_SEL_SDIO2                      _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXA_SEL_SPI2                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_HDINT_SEL_SHIFT                     _MK_SHIFT_CONST(4)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_HDINT_SEL_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_B_0_HDINT_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_HDINT_SEL_RANGE                     5:4
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_HDINT_SEL_WOFFSET                   0x0
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_HDINT_SEL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_HDINT_SEL_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_HDINT_SEL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_HDINT_SEL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_HDINT_SEL_RSVD1                     _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_HDINT_SEL_DISPLAYA_HSYNC                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_HDINT_SEL_DISPLAYB_HSYNC                    _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_HDINT_SEL_RSVD2                     _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_RSVD_4_SHIFT                        _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_RSVD_4_FIELD                        (_MK_MASK_CONST(0xf) << APB_MISC_PP_PIN_MUX_CTL_B_0_RSVD_4_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_RSVD_4_RANGE                        3:0
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_RSVD_4_WOFFSET                      0x0
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_RSVD_4_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_RSVD_4_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_RSVD_4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_RSVD_4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_PP_PIN_MUX_CTL_C_0  
+#define APB_MISC_PP_PIN_MUX_CTL_C_0                     _MK_ADDR_CONST(0x88)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_WORD_COUNT                  0x1
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_XM2S_SEL_SHIFT                      _MK_SHIFT_CONST(30)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_XM2S_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_C_0_XM2S_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_XM2S_SEL_RANGE                      31:30
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_XM2S_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_XM2S_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_XM2S_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_XM2S_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_XM2S_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_XM2S_SEL_DRAM                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_XM2S_SEL_RSVD2                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_XM2S_SEL_SPI                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_XM2S_SEL_SPROM                      _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_XM2A_SEL_SHIFT                      _MK_SHIFT_CONST(28)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_XM2A_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_C_0_XM2A_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_XM2A_SEL_RANGE                      29:28
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_XM2A_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_XM2A_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_XM2A_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_XM2A_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_XM2A_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_XM2A_SEL_DRAM                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_XM2A_SEL_SPI3                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_XM2A_SEL_SPI                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_XM2A_SEL_SPROM                      _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP4_SEL_SHIFT                      _MK_SHIFT_CONST(26)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP4_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_C_0_DAP4_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP4_SEL_RANGE                      27:26
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP4_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP4_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP4_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP4_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP4_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP4_SEL_DAP4                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP4_SEL_RSVD2                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP4_SEL_RSVD3                      _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP4_SEL_RSVD4                      _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP3_SEL_SHIFT                      _MK_SHIFT_CONST(24)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP3_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_C_0_DAP3_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP3_SEL_RANGE                      25:24
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP3_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP3_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP3_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP3_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP3_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP3_SEL_DAP3                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP3_SEL_RSVD2                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP3_SEL_RSVD3                      _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP3_SEL_RSVD4                      _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP2_SEL_SHIFT                      _MK_SHIFT_CONST(22)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP2_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_C_0_DAP2_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP2_SEL_RANGE                      23:22
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP2_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP2_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP2_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP2_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP2_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP2_SEL_DAP2                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP2_SEL_TWC                        _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP2_SEL_RSVD3                      _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP2_SEL_RSVD4                      _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP1_SEL_SHIFT                      _MK_SHIFT_CONST(20)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP1_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_C_0_DAP1_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP1_SEL_RANGE                      21:20
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP1_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP1_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP1_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP1_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP1_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP1_SEL_DAP1                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP1_SEL_RSVD2                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP1_SEL_RSVD3                      _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP1_SEL_SDIO1                      _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRRX_SEL_SHIFT                      _MK_SHIFT_CONST(18)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRRX_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_C_0_IRRX_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRRX_SEL_RANGE                      19:18
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRRX_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRRX_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRRX_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRRX_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRRX_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRRX_SEL_UARTA                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRRX_SEL_RSVD2                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRRX_SEL_RSVD3                      _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRRX_SEL_UARTB                      _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRTX_SEL_SHIFT                      _MK_SHIFT_CONST(16)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRTX_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_C_0_IRTX_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRTX_SEL_RANGE                      17:16
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRTX_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRTX_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRTX_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRTX_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRTX_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRTX_SEL_UARTA                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRTX_SEL_RSVD2                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRTX_SEL_RSVD3                      _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRTX_SEL_UARTB                      _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCC_SEL_SHIFT                      _MK_SHIFT_CONST(14)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCC_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_C_0_KBCC_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCC_SEL_RANGE                      15:14
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCC_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCC_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCC_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCC_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCC_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCC_SEL_KBC                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCC_SEL_RSVD2                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCC_SEL_RSVD3                      _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCC_SEL_RSVD4                      _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCB_SEL_SHIFT                      _MK_SHIFT_CONST(12)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCB_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_C_0_KBCB_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCB_SEL_RANGE                      13:12
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCB_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCB_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCB_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCB_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCB_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCB_SEL_KBC                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCB_SEL_RSVD2                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCB_SEL_SDIO1                      _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCB_SEL_MIO                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCA_SEL_SHIFT                      _MK_SHIFT_CONST(10)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCA_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_C_0_KBCA_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCA_SEL_RANGE                      11:10
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCA_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCA_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCA_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCA_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCA_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCA_SEL_KBC                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCA_SEL_RSVD2                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCA_SEL_RSVD3                      _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCA_SEL_RSVD4                      _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_I2CP_SEL_SHIFT                      _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_I2CP_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_C_0_I2CP_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_I2CP_SEL_RANGE                      9:8
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_I2CP_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_I2CP_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_I2CP_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_I2CP_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_I2CP_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_I2CP_SEL_I2C                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_I2CP_SEL_RSVD2                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_I2CP_SEL_RSVD3                      _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_I2CP_SEL_RSVD4                      _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CSUS_SEL_SHIFT                      _MK_SHIFT_CONST(6)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CSUS_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_C_0_CSUS_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CSUS_SEL_RANGE                      7:6
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CSUS_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CSUS_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CSUS_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CSUS_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CSUS_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CSUS_SEL_PLLC_OUT1                  _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CSUS_SEL_PLLP_OUT2                  _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CSUS_SEL_PLLP_OUT3                  _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CSUS_SEL_VI_SENSOR_CLK                      _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV2_SEL_SHIFT                     _MK_SHIFT_CONST(4)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV2_SEL_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV2_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV2_SEL_RANGE                     5:4
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV2_SEL_WOFFSET                   0x0
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV2_SEL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV2_SEL_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV2_SEL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV2_SEL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV2_SEL_OSC                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV2_SEL_AHB_CLK                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV2_SEL_APB_CLK                   _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV2_SEL_PLLP_OUT4                 _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV1_SEL_SHIFT                     _MK_SHIFT_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV1_SEL_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV1_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV1_SEL_RANGE                     3:2
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV1_SEL_WOFFSET                   0x0
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV1_SEL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV1_SEL_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV1_SEL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV1_SEL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV1_SEL_OSC                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV1_SEL_PLLA_OUT                  _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV1_SEL_PLLM_OUT1                 _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV1_SEL_AUDIO_SYNC                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CSYS_SEL_SHIFT                      _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CSYS_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_C_0_CSYS_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CSYS_SEL_RANGE                      1:0
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CSYS_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CSYS_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CSYS_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CSYS_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CSYS_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CSYS_SEL_RSVD1                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CSYS_SEL_RSVD2                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CSYS_SEL_RSVD3                      _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CSYS_SEL_RSVD4                      _MK_ENUM_CONST(3)
+
+
+// Register APB_MISC_PP_PIN_MUX_CTL_D_0  
+#define APB_MISC_PP_PIN_MUX_CTL_D_0                     _MK_ADDR_CONST(0x8c)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_WORD_COUNT                  0x1
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIA_SEL_SHIFT                      _MK_SHIFT_CONST(30)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIA_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_D_0_SPIA_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIA_SEL_RANGE                      31:30
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIA_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIA_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIA_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIA_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIA_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIA_SEL_SPI1                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIA_SEL_SPI2                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIA_SEL_SPI3                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIA_SEL_RSVD                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIB_SEL_SHIFT                      _MK_SHIFT_CONST(28)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIB_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_D_0_SPIB_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIB_SEL_RANGE                      29:28
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIB_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIB_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIB_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIB_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIB_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIB_SEL_SPI1                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIB_SEL_SPI2                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIB_SEL_SPI3                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIB_SEL_RSVD                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIC_SEL_SHIFT                      _MK_SHIFT_CONST(26)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIC_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_D_0_SPIC_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIC_SEL_RANGE                      27:26
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIC_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIC_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIC_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIC_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIC_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIC_SEL_SPI1                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIC_SEL_SPI2                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIC_SEL_SPI3                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIC_SEL_RSVD                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPID_SEL_SHIFT                      _MK_SHIFT_CONST(24)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPID_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_D_0_SPID_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPID_SEL_RANGE                      25:24
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPID_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPID_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPID_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPID_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPID_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPID_SEL_SPI2                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPID_SEL_SPI1                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPID_SEL_SPI2_ALT                   _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPID_SEL_RSVD                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIE_SEL_SHIFT                      _MK_SHIFT_CONST(22)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIE_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_D_0_SPIE_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIE_SEL_RANGE                      23:22
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIE_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIE_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIE_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIE_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIE_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIE_SEL_SPI2                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIE_SEL_SPI1                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIE_SEL_SPI2_ALT                   _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIE_SEL_RSVD                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIF_SEL_SHIFT                      _MK_SHIFT_CONST(20)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIF_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_D_0_SPIF_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIF_SEL_RANGE                      21:20
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIF_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIF_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIF_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIF_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIF_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIF_SEL_SPI3                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIF_SEL_SPI1                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIF_SEL_SPI2                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIF_SEL_RSVD                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIG_SEL_SHIFT                      _MK_SHIFT_CONST(18)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIG_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_D_0_SPIG_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIG_SEL_RANGE                      19:18
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIG_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIG_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIG_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIG_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIG_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIG_SEL_SPI3                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIG_SEL_SPI2                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIG_SEL_SPI2_ALT                   _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIG_SEL_I2C                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIH_SEL_SHIFT                      _MK_SHIFT_CONST(16)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIH_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_D_0_SPIH_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIH_SEL_RANGE                      17:16
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIH_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIH_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIH_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIH_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIH_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIH_SEL_SPI3                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIH_SEL_SPI2                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIH_SEL_SPI2_ALT                   _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIH_SEL_I2C                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDD_SEL_SHIFT                       _MK_SHIFT_CONST(14)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDD_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_D_0_SDD_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDD_SEL_RANGE                       15:14
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDD_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDD_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDD_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDD_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDD_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDD_SEL_UARTA                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDD_SEL_PWM                 _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDD_SEL_SDIO2                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDD_SEL_SPI3                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDC_SEL_SHIFT                       _MK_SHIFT_CONST(12)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDC_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_D_0_SDC_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDC_SEL_RANGE                       13:12
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDC_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDC_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDC_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDC_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDC_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDC_SEL_PWM                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDC_SEL_TWC                 _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDC_SEL_SDIO2                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDC_SEL_SPI3                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDB_SEL_SHIFT                       _MK_SHIFT_CONST(10)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDB_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_D_0_SDB_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDB_SEL_RANGE                       11:10
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDB_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDB_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDB_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDB_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDB_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDB_SEL_SDIO2                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDB_SEL_RSVD                        _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDB_SEL_SDIO2_ALT                   _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDB_SEL_RSVD4                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDI_SEL_SHIFT                      _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDI_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_D_0_SPDI_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDI_SEL_RANGE                      9:8
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDI_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDI_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDI_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDI_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDI_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDI_SEL_SPDIF                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDI_SEL_RSVD                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDI_SEL_I2C                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDI_SEL_SDIO1                      _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDO_SEL_SHIFT                      _MK_SHIFT_CONST(6)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDO_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_D_0_SPDO_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDO_SEL_RANGE                      7:6
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDO_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDO_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDO_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDO_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDO_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDO_SEL_SPDIF                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDO_SEL_RSVD                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDO_SEL_I2C                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDO_SEL_SDIO1                      _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPU_SEL_SHIFT                       _MK_SHIFT_CONST(4)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPU_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_D_0_GPU_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPU_SEL_RANGE                       5:4
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPU_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPU_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPU_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPU_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPU_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPU_SEL_RSVD                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPU_SEL_UARTA                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPU_SEL_RSVD3                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPU_SEL_RSVD4                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPV_SEL_SHIFT                       _MK_SHIFT_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPV_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_D_0_GPV_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPV_SEL_RANGE                       3:2
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPV_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPV_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPV_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPV_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPV_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPV_SEL_GPIO_PORT_V                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPV_SEL_RSVD2                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPV_SEL_RSVD3                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPV_SEL_RSVD4                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_DBG_SEL_SHIFT                       _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_DBG_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_D_0_DBG_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_DBG_SEL_RANGE                       1:0
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_DBG_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_DBG_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_DBG_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_DBG_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_DBG_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_DBG_SEL_JTAG                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_DBG_SEL_RSVD2                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_DBG_SEL_RSVD3                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_DBG_SEL_RSVD4                       _MK_ENUM_CONST(3)
+
+
+// Register APB_MISC_PP_PIN_MUX_CTL_E_0  
+#define APB_MISC_PP_PIN_MUX_CTL_E_0                     _MK_ADDR_CONST(0x90)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_WORD_COUNT                  0x1
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVP0_SEL_SHIFT                      _MK_SHIFT_CONST(30)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVP0_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_E_0_LVP0_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVP0_SEL_RANGE                      31:30
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVP0_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVP0_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVP0_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVP0_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVP0_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVP0_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVP0_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVP0_SEL_I2C2                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVP0_SEL_RSVD                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM1_SEL_SHIFT                       _MK_SHIFT_CONST(28)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM1_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_E_0_LM1_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM1_SEL_RANGE                       29:28
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM1_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM1_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM1_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM1_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM1_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM1_SEL_DISPLAYA                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM1_SEL_DISPLAYB                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM1_SEL_I2C2                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM1_SEL_CRT                 _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM0_SEL_SHIFT                       _MK_SHIFT_CONST(26)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM0_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_E_0_LM0_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM0_SEL_RANGE                       27:26
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM0_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM0_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM0_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM0_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM0_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM0_SEL_DISPLAYA                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM0_SEL_DISPLAYB                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM0_SEL_SPI3                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM0_SEL_RSVD                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVS_SEL_SHIFT                       _MK_SHIFT_CONST(24)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVS_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_E_0_LVS_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVS_SEL_RANGE                       25:24
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVS_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVS_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVS_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVS_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVS_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVS_SEL_DISPLAYA                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVS_SEL_DISPLAYB                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVS_SEL_XIO                 _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVS_SEL_CRT                 _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LHS_SEL_SHIFT                       _MK_SHIFT_CONST(22)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LHS_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_E_0_LHS_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LHS_SEL_RANGE                       23:22
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LHS_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LHS_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LHS_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LHS_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LHS_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LHS_SEL_DISPLAYA                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LHS_SEL_DISPLAYB                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LHS_SEL_XIO                 _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LHS_SEL_CRT                 _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC1_SEL_SHIFT                      _MK_SHIFT_CONST(20)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC1_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_E_0_LSC1_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC1_SEL_RANGE                      21:20
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC1_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC1_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC1_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC1_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC1_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC1_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC1_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC1_SEL_SPI3                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC1_SEL_HDMI                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC0_SEL_SHIFT                      _MK_SHIFT_CONST(18)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC0_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_E_0_LSC0_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC0_SEL_RANGE                      19:18
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC0_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC0_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC0_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC0_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC0_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC0_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC0_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC0_SEL_XIO                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC0_SEL_RSVD                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSCK_SEL_SHIFT                      _MK_SHIFT_CONST(16)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSCK_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_E_0_LSCK_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSCK_SEL_RANGE                      17:16
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSCK_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSCK_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSCK_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSCK_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSCK_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSCK_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSCK_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSCK_SEL_SPI3                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSCK_SEL_HDMI                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LDC_SEL_SHIFT                       _MK_SHIFT_CONST(14)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LDC_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_E_0_LDC_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LDC_SEL_RANGE                       15:14
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LDC_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LDC_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LDC_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LDC_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LDC_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LDC_SEL_DISPLAYA                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LDC_SEL_DISPLAYB                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LDC_SEL_RSVD                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LDC_SEL_RSVD4                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LCSN_SEL_SHIFT                      _MK_SHIFT_CONST(12)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LCSN_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_E_0_LCSN_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LCSN_SEL_RANGE                      13:12
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LCSN_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LCSN_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LCSN_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LCSN_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LCSN_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LCSN_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LCSN_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LCSN_SEL_SPI3                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LCSN_SEL_CRT                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSPI_SEL_SHIFT                      _MK_SHIFT_CONST(10)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSPI_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_E_0_LSPI_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSPI_SEL_RANGE                      11:10
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSPI_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSPI_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSPI_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSPI_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSPI_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSPI_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSPI_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSPI_SEL_XIO                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSPI_SEL_RSVD                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDA_SEL_SHIFT                      _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDA_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_E_0_LSDA_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDA_SEL_RANGE                      9:8
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDA_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDA_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDA_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDA_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDA_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDA_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDA_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDA_SEL_SPI3                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDA_SEL_HDMI                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDI_SEL_SHIFT                      _MK_SHIFT_CONST(6)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDI_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_E_0_LSDI_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDI_SEL_RANGE                      7:6
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDI_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDI_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDI_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDI_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDI_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDI_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDI_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDI_SEL_SPI3                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDI_SEL_RSVD                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW2_SEL_SHIFT                      _MK_SHIFT_CONST(4)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW2_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_E_0_LPW2_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW2_SEL_RANGE                      5:4
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW2_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW2_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW2_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW2_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW2_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW2_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW2_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW2_SEL_SPI3                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW2_SEL_HDMI                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW1_SEL_SHIFT                      _MK_SHIFT_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW1_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_E_0_LPW1_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW1_SEL_RANGE                      3:2
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW1_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW1_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW1_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW1_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW1_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW1_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW1_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW1_SEL_RSVD                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW1_SEL_CRT                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW0_SEL_SHIFT                      _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW0_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_E_0_LPW0_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW0_SEL_RANGE                      1:0
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW0_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW0_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW0_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW0_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW0_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW0_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW0_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW0_SEL_SPI3                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW0_SEL_HDMI                       _MK_ENUM_CONST(3)
+
+
+// Register APB_MISC_PP_PIN_MUX_CTL_F_0  
+#define APB_MISC_PP_PIN_MUX_CTL_F_0                     _MK_ADDR_CONST(0x94)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_WORD_COUNT                  0x1
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD15_SEL_SHIFT                      _MK_SHIFT_CONST(30)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD15_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_F_0_LD15_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD15_SEL_RANGE                      31:30
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD15_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD15_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD15_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD15_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD15_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD15_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD15_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD15_SEL_XIO                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD15_SEL_RSVD                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD14_SEL_SHIFT                      _MK_SHIFT_CONST(28)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD14_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_F_0_LD14_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD14_SEL_RANGE                      29:28
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD14_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD14_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD14_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD14_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD14_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD14_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD14_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD14_SEL_XIO                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD14_SEL_RSVD                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD13_SEL_SHIFT                      _MK_SHIFT_CONST(26)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD13_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_F_0_LD13_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD13_SEL_RANGE                      27:26
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD13_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD13_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD13_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD13_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD13_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD13_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD13_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD13_SEL_XIO                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD13_SEL_RSVD                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD12_SEL_SHIFT                      _MK_SHIFT_CONST(24)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD12_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_F_0_LD12_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD12_SEL_RANGE                      25:24
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD12_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD12_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD12_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD12_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD12_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD12_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD12_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD12_SEL_XIO                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD12_SEL_RSVD                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD11_SEL_SHIFT                      _MK_SHIFT_CONST(22)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD11_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_F_0_LD11_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD11_SEL_RANGE                      23:22
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD11_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD11_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD11_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD11_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD11_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD11_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD11_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD11_SEL_XIO                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD11_SEL_RSVD                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD10_SEL_SHIFT                      _MK_SHIFT_CONST(20)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD10_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_F_0_LD10_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD10_SEL_RANGE                      21:20
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD10_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD10_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD10_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD10_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD10_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD10_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD10_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD10_SEL_XIO                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD10_SEL_RSVD                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD9_SEL_SHIFT                       _MK_SHIFT_CONST(18)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD9_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_F_0_LD9_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD9_SEL_RANGE                       19:18
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD9_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD9_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD9_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD9_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD9_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD9_SEL_DISPLAYA                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD9_SEL_DISPLAYB                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD9_SEL_XIO                 _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD9_SEL_RSVD                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD8_SEL_SHIFT                       _MK_SHIFT_CONST(16)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD8_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_F_0_LD8_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD8_SEL_RANGE                       17:16
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD8_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD8_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD8_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD8_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD8_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD8_SEL_DISPLAYA                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD8_SEL_DISPLAYB                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD8_SEL_XIO                 _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD8_SEL_RSVD                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD7_SEL_SHIFT                       _MK_SHIFT_CONST(14)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD7_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_F_0_LD7_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD7_SEL_RANGE                       15:14
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD7_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD7_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD7_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD7_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD7_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD7_SEL_DISPLAYA                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD7_SEL_DISPLAYB                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD7_SEL_XIO                 _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD7_SEL_RSVD                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD6_SEL_SHIFT                       _MK_SHIFT_CONST(12)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD6_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_F_0_LD6_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD6_SEL_RANGE                       13:12
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD6_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD6_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD6_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD6_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD6_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD6_SEL_DISPLAYA                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD6_SEL_DISPLAYB                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD6_SEL_XIO                 _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD6_SEL_RSVD                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD5_SEL_SHIFT                       _MK_SHIFT_CONST(10)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD5_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_F_0_LD5_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD5_SEL_RANGE                       11:10
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD5_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD5_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD5_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD5_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD5_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD5_SEL_DISPLAYA                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD5_SEL_DISPLAYB                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD5_SEL_XIO                 _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD5_SEL_RSVD                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD4_SEL_SHIFT                       _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD4_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_F_0_LD4_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD4_SEL_RANGE                       9:8
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD4_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD4_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD4_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD4_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD4_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD4_SEL_DISPLAYA                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD4_SEL_DISPLAYB                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD4_SEL_XIO                 _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD4_SEL_RSVD                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD3_SEL_SHIFT                       _MK_SHIFT_CONST(6)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD3_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_F_0_LD3_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD3_SEL_RANGE                       7:6
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD3_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD3_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD3_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD3_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD3_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD3_SEL_DISPLAYA                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD3_SEL_DISPLAYB                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD3_SEL_XIO                 _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD3_SEL_RSVD                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD2_SEL_SHIFT                       _MK_SHIFT_CONST(4)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD2_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_F_0_LD2_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD2_SEL_RANGE                       5:4
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD2_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD2_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD2_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD2_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD2_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD2_SEL_DISPLAYA                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD2_SEL_DISPLAYB                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD2_SEL_XIO                 _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD2_SEL_RSVD                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD1_SEL_SHIFT                       _MK_SHIFT_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD1_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_F_0_LD1_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD1_SEL_RANGE                       3:2
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD1_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD1_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD1_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD1_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD1_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD1_SEL_DISPLAYA                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD1_SEL_DISPLAYB                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD1_SEL_XIO                 _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD1_SEL_RSVD                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD0_SEL_SHIFT                       _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD0_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_F_0_LD0_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD0_SEL_RANGE                       1:0
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD0_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD0_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD0_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD0_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD0_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD0_SEL_DISPLAYA                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD0_SEL_DISPLAYB                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD0_SEL_XIO                 _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD0_SEL_RSVD                        _MK_ENUM_CONST(3)
+
+
+// Register APB_MISC_PP_PIN_MUX_CTL_G_0  
+#define APB_MISC_PP_PIN_MUX_CTL_G_0                     _MK_ADDR_CONST(0x98)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_WORD_COUNT                  0x1
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_RESET_MASK                  _MK_MASK_CONST(0xfcffcfff)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_READ_MASK                   _MK_MASK_CONST(0xfcffcfff)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_WRITE_MASK                  _MK_MASK_CONST(0xfcffcfff)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_DTF_SEL_SHIFT                       _MK_SHIFT_CONST(30)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_DTF_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_G_0_DTF_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_DTF_SEL_RANGE                       31:30
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_DTF_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_DTF_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_DTF_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_DTF_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_DTF_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_DTF_SEL_RSVD1                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_DTF_SEL_RSVD2                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_DTF_SEL_VI                  _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_DTF_SEL_I2C2                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_GPU7_SEL_SHIFT                      _MK_SHIFT_CONST(28)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_GPU7_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_G_0_GPU7_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_GPU7_SEL_RANGE                      29:28
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_GPU7_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_GPU7_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_GPU7_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_GPU7_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_GPU7_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_GPU7_SEL_RTCK                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_GPU7_SEL_RSVD1                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_GPU7_SEL_RSVD2                      _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_GPU7_SEL_RSVD3                      _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_KBCD_SEL_SHIFT                      _MK_SHIFT_CONST(26)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_KBCD_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_G_0_KBCD_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_KBCD_SEL_RANGE                      27:26
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_KBCD_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_KBCD_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_KBCD_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_KBCD_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_KBCD_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_KBCD_SEL_KBC                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_KBCD_SEL_RSVD2                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_KBCD_SEL_SDIO1                      _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_KBCD_SEL_MIO                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_PTA_SEL_SHIFT                       _MK_SHIFT_CONST(22)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_PTA_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_G_0_PTA_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_PTA_SEL_RANGE                       23:22
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_PTA_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_PTA_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_PTA_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_PTA_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_PTA_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_PTA_SEL_I2C2                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_PTA_SEL_HDMI                        _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_PTA_SEL_RSVD1                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_PTA_SEL_RSVD2                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_RSVD_5_SHIFT                        _MK_SHIFT_CONST(20)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_RSVD_5_FIELD                        (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_G_0_RSVD_5_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_RSVD_5_RANGE                        21:20
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_RSVD_5_WOFFSET                      0x0
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_RSVD_5_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_RSVD_5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_RSVD_5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_RSVD_5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_PMC_SEL_SHIFT                       _MK_SHIFT_CONST(18)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_PMC_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_G_0_PMC_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_PMC_SEL_RANGE                       19:18
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_PMC_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_PMC_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_PMC_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_PMC_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_PMC_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_PMC_SEL_PWR_ON                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_PMC_SEL_PWR_INTR                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LDI_SEL_SHIFT                       _MK_SHIFT_CONST(16)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LDI_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_G_0_LDI_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LDI_SEL_RANGE                       17:16
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LDI_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LDI_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LDI_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LDI_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LDI_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LDI_SEL_DISPLAYA                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LDI_SEL_DISPLAYB                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LDI_SEL_SPI1                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LDI_SEL_RSVD                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LPP_SEL_SHIFT                       _MK_SHIFT_CONST(14)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LPP_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_G_0_LPP_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LPP_SEL_RANGE                       15:14
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LPP_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LPP_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LPP_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LPP_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LPP_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LPP_SEL_DISPLAYA                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LPP_SEL_DISPLAYB                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LPP_SEL_SPI1                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LPP_SEL_RSVD                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP0_SEL_SHIFT                      _MK_SHIFT_CONST(10)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP0_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_G_0_LHP0_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP0_SEL_RANGE                      11:10
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP0_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP0_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP0_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP0_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP0_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP0_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP0_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP0_SEL_SPI1                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP0_SEL_I2C2                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LVP1_SEL_SHIFT                      _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LVP1_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_G_0_LVP1_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LVP1_SEL_RANGE                      9:8
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LVP1_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LVP1_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LVP1_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LVP1_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LVP1_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LVP1_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LVP1_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LVP1_SEL_SPI1                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LVP1_SEL_I2C2                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP2_SEL_SHIFT                      _MK_SHIFT_CONST(6)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP2_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_G_0_LHP2_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP2_SEL_RANGE                      7:6
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP2_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP2_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP2_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP2_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP2_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP2_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP2_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP2_SEL_SPI1                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP2_SEL_CRT                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP1_SEL_SHIFT                      _MK_SHIFT_CONST(4)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP1_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_G_0_LHP1_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP1_SEL_RANGE                      5:4
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP1_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP1_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP1_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP1_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP1_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP1_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP1_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP1_SEL_SPI1                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP1_SEL_RSVD                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD17_SEL_SHIFT                      _MK_SHIFT_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD17_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_G_0_LD17_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD17_SEL_RANGE                      3:2
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD17_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD17_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD17_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD17_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD17_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD17_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD17_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD17_SEL_RSVD                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD17_SEL_RSVD_ALT                   _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD16_SEL_SHIFT                      _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD16_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_G_0_LD16_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD16_SEL_RANGE                      1:0
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD16_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD16_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD16_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD16_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD16_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD16_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD16_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD16_SEL_XIO                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD16_SEL_RSVD                       _MK_ENUM_CONST(3)
+
+
+// Register APB_MISC_PP_PIN_MUX_CTL_H_0  
+#define APB_MISC_PP_PIN_MUX_CTL_H_0                     _MK_ADDR_CONST(0x9c)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_WORD_COUNT                  0x1
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_RSVD_6_SHIFT                        _MK_SHIFT_CONST(22)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_RSVD_6_FIELD                        (_MK_MASK_CONST(0x3ff) << APB_MISC_PP_PIN_MUX_CTL_H_0_RSVD_6_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_RSVD_6_RANGE                        31:22
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_RSVD_6_WOFFSET                      0x0
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_RSVD_6_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_RSVD_6_DEFAULT_MASK                 _MK_MASK_CONST(0x3ff)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_RSVD_6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_RSVD_6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4M_SEL_SHIFT                     _MK_SHIFT_CONST(21)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4M_SEL_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4M_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4M_SEL_RANGE                     21:21
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4M_SEL_WOFFSET                   0x0
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4M_SEL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4M_SEL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4M_SEL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4M_SEL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4M_SEL_DAP4_SLAVE                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4M_SEL_DAP4_MASTER                       _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3M_SEL_SHIFT                     _MK_SHIFT_CONST(20)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3M_SEL_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3M_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3M_SEL_RANGE                     20:20
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3M_SEL_WOFFSET                   0x0
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3M_SEL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3M_SEL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3M_SEL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3M_SEL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3M_SEL_DAP3_SLAVE                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3M_SEL_DAP3_MASTER                       _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2M_SEL_SHIFT                     _MK_SHIFT_CONST(19)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2M_SEL_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2M_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2M_SEL_RANGE                     19:19
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2M_SEL_WOFFSET                   0x0
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2M_SEL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2M_SEL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2M_SEL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2M_SEL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2M_SEL_DAP2_SLAVE                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2M_SEL_DAP2_MASTER                       _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1M_SEL_SHIFT                     _MK_SHIFT_CONST(18)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1M_SEL_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1M_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1M_SEL_RANGE                     18:18
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1M_SEL_WOFFSET                   0x0
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1M_SEL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1M_SEL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1M_SEL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1M_SEL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1M_SEL_DAP1_SLAVE                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1M_SEL_DAP1_MASTER                       _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC3_SEL_SHIFT                      _MK_SHIFT_CONST(16)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC3_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_H_0_DAC3_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC3_SEL_RANGE                      17:16
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC3_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC3_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC3_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC3_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC3_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC3_SEL_DAP1                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC3_SEL_DAP2                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC3_SEL_DAP3                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC3_SEL_DAP4                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC2_SEL_SHIFT                      _MK_SHIFT_CONST(14)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC2_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_H_0_DAC2_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC2_SEL_RANGE                      15:14
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC2_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC2_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC2_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC2_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC2_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC2_SEL_DAP1                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC2_SEL_DAP2                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC2_SEL_DAP3                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC2_SEL_DAP4                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC1_SEL_SHIFT                      _MK_SHIFT_CONST(12)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC1_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_H_0_DAC1_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC1_SEL_RANGE                      13:12
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC1_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC1_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC1_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC1_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC1_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC1_SEL_DAP1                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC1_SEL_DAP2                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC1_SEL_DAP3                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC1_SEL_DAP4                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4_CNTRL_MUX_SELECT_SHIFT                 _MK_SHIFT_CONST(9)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4_CNTRL_MUX_SELECT_FIELD                 (_MK_MASK_CONST(0x7) << APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4_CNTRL_MUX_SELECT_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4_CNTRL_MUX_SELECT_RANGE                 11:9
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4_CNTRL_MUX_SELECT_WOFFSET                       0x0
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4_CNTRL_MUX_SELECT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4_CNTRL_MUX_SELECT_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4_CNTRL_MUX_SELECT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4_CNTRL_MUX_SELECT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4_CNTRL_MUX_SELECT_DAC1                  _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4_CNTRL_MUX_SELECT_DAC2                  _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4_CNTRL_MUX_SELECT_DAC3                  _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4_CNTRL_MUX_SELECT_RSVD                  _MK_ENUM_CONST(3)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4_CNTRL_MUX_SELECT_DAP1                  _MK_ENUM_CONST(4)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4_CNTRL_MUX_SELECT_DAP2                  _MK_ENUM_CONST(5)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4_CNTRL_MUX_SELECT_DAP3                  _MK_ENUM_CONST(6)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4_CNTRL_MUX_SELECT_RSVD2                 _MK_ENUM_CONST(7)
+
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3_CNTRL_MUX_SELECT_SHIFT                 _MK_SHIFT_CONST(6)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3_CNTRL_MUX_SELECT_FIELD                 (_MK_MASK_CONST(0x7) << APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3_CNTRL_MUX_SELECT_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3_CNTRL_MUX_SELECT_RANGE                 8:6
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3_CNTRL_MUX_SELECT_WOFFSET                       0x0
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3_CNTRL_MUX_SELECT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3_CNTRL_MUX_SELECT_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3_CNTRL_MUX_SELECT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3_CNTRL_MUX_SELECT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3_CNTRL_MUX_SELECT_DAC1                  _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3_CNTRL_MUX_SELECT_DAC2                  _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3_CNTRL_MUX_SELECT_DAC3                  _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3_CNTRL_MUX_SELECT_RSVD1                 _MK_ENUM_CONST(3)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3_CNTRL_MUX_SELECT_DAP1                  _MK_ENUM_CONST(4)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3_CNTRL_MUX_SELECT_DAP2                  _MK_ENUM_CONST(5)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3_CNTRL_MUX_SELECT_RSVD2                 _MK_ENUM_CONST(6)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3_CNTRL_MUX_SELECT_DAP4                  _MK_ENUM_CONST(7)
+
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2_CNTRL_MUX_SELECT_SHIFT                 _MK_SHIFT_CONST(3)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2_CNTRL_MUX_SELECT_FIELD                 (_MK_MASK_CONST(0x7) << APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2_CNTRL_MUX_SELECT_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2_CNTRL_MUX_SELECT_RANGE                 5:3
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2_CNTRL_MUX_SELECT_WOFFSET                       0x0
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2_CNTRL_MUX_SELECT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2_CNTRL_MUX_SELECT_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2_CNTRL_MUX_SELECT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2_CNTRL_MUX_SELECT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2_CNTRL_MUX_SELECT_DAC1                  _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2_CNTRL_MUX_SELECT_DAC2                  _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2_CNTRL_MUX_SELECT_DAC3                  _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2_CNTRL_MUX_SELECT_RSVD1                 _MK_ENUM_CONST(3)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2_CNTRL_MUX_SELECT_DAP1                  _MK_ENUM_CONST(4)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2_CNTRL_MUX_SELECT_RSVD2                 _MK_ENUM_CONST(5)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2_CNTRL_MUX_SELECT_DAP3                  _MK_ENUM_CONST(6)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2_CNTRL_MUX_SELECT_DAP4                  _MK_ENUM_CONST(7)
+
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1_CNTRL_MUX_SELECT_SHIFT                 _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1_CNTRL_MUX_SELECT_FIELD                 (_MK_MASK_CONST(0x7) << APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1_CNTRL_MUX_SELECT_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1_CNTRL_MUX_SELECT_RANGE                 2:0
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1_CNTRL_MUX_SELECT_WOFFSET                       0x0
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1_CNTRL_MUX_SELECT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1_CNTRL_MUX_SELECT_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1_CNTRL_MUX_SELECT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1_CNTRL_MUX_SELECT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1_CNTRL_MUX_SELECT_DAC1                  _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1_CNTRL_MUX_SELECT_DAC2                  _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1_CNTRL_MUX_SELECT_DAC3                  _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1_CNTRL_MUX_SELECT_RSVD1                 _MK_ENUM_CONST(3)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1_CNTRL_MUX_SELECT_RSVD2                 _MK_ENUM_CONST(4)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1_CNTRL_MUX_SELECT_DAP2                  _MK_ENUM_CONST(5)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1_CNTRL_MUX_SELECT_DAP3                  _MK_ENUM_CONST(6)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1_CNTRL_MUX_SELECT_DAP4                  _MK_ENUM_CONST(7)
+
+
+// Register APB_MISC_PP_PULLUPDOWN_REG_A_0  
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0                  _MK_ADDR_CONST(0xa0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_WORD_COUNT                       0x1
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_RESET_VAL                        _MK_MASK_CONST(0x215556aa)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_GPV_PU_PD_SHIFT                  _MK_SHIFT_CONST(30)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_GPV_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_A_0_GPV_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_GPV_PU_PD_RANGE                  31:30
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_GPV_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_GPV_PU_PD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_GPV_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_GPV_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_GPV_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_GPV_PU_PD_INIT_ENUM                      NORMAL
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_GPV_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_GPV_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_GPV_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_GPV_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTF_PU_PD_SHIFT                  _MK_SHIFT_CONST(28)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTF_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_A_0_DTF_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTF_PU_PD_RANGE                  29:28
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTF_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTF_PU_PD_DEFAULT                        _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTF_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTF_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTF_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTF_PU_PD_INIT_ENUM                      PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTF_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTF_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTF_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTF_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTE_PU_PD_SHIFT                  _MK_SHIFT_CONST(26)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTE_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_A_0_DTE_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTE_PU_PD_RANGE                  27:26
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTE_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTE_PU_PD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTE_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTE_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTE_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTE_PU_PD_INIT_ENUM                      NORMAL
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTE_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTE_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTE_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTE_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTD_PU_PD_SHIFT                  _MK_SHIFT_CONST(24)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTD_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_A_0_DTD_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTD_PU_PD_RANGE                  25:24
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTD_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTD_PU_PD_DEFAULT                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTD_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTD_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTD_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTD_PU_PD_INIT_ENUM                      PULL_DOWN
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTD_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTD_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTD_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTD_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTC_PU_PD_SHIFT                  _MK_SHIFT_CONST(22)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTC_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_A_0_DTC_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTC_PU_PD_RANGE                  23:22
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTC_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTC_PU_PD_DEFAULT                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTC_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTC_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTC_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTC_PU_PD_INIT_ENUM                      PULL_DOWN
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTC_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTC_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTC_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTC_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTB_PU_PD_SHIFT                  _MK_SHIFT_CONST(20)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTB_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_A_0_DTB_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTB_PU_PD_RANGE                  21:20
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTB_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTB_PU_PD_DEFAULT                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTB_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTB_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTB_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTB_PU_PD_INIT_ENUM                      PULL_DOWN
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTB_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTB_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTB_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTB_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTA_PU_PD_SHIFT                  _MK_SHIFT_CONST(18)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTA_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_A_0_DTA_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTA_PU_PD_RANGE                  19:18
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTA_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTA_PU_PD_DEFAULT                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTA_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTA_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTA_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTA_PU_PD_INIT_ENUM                      PULL_DOWN
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTA_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTA_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTA_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTA_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP4_PU_PD_SHIFT                 _MK_SHIFT_CONST(16)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP4_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP4_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP4_PU_PD_RANGE                 17:16
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP4_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP4_PU_PD_DEFAULT                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP4_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP4_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP4_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP4_PU_PD_INIT_ENUM                     PULL_DOWN
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP4_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP4_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP4_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP4_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP3_PU_PD_SHIFT                 _MK_SHIFT_CONST(14)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP3_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP3_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP3_PU_PD_RANGE                 15:14
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP3_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP3_PU_PD_DEFAULT                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP3_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP3_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP3_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP3_PU_PD_INIT_ENUM                     PULL_DOWN
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP3_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP3_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP3_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP3_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP2_PU_PD_SHIFT                 _MK_SHIFT_CONST(12)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP2_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP2_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP2_PU_PD_RANGE                 13:12
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP2_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP2_PU_PD_DEFAULT                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP2_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP2_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP2_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP2_PU_PD_INIT_ENUM                     PULL_DOWN
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP2_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP2_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP2_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP2_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP1_PU_PD_SHIFT                 _MK_SHIFT_CONST(10)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP1_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP1_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP1_PU_PD_RANGE                 11:10
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP1_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP1_PU_PD_DEFAULT                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP1_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP1_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP1_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP1_PU_PD_INIT_ENUM                     PULL_DOWN
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP1_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP1_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP1_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP1_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATE_PU_PD_SHIFT                  _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATE_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_A_0_ATE_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATE_PU_PD_RANGE                  9:8
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATE_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATE_PU_PD_DEFAULT                        _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATE_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATE_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATE_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATE_PU_PD_INIT_ENUM                      PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATE_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATE_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATE_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATE_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATD_PU_PD_SHIFT                  _MK_SHIFT_CONST(6)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATD_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_A_0_ATD_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATD_PU_PD_RANGE                  7:6
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATD_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATD_PU_PD_DEFAULT                        _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATD_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATD_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATD_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATD_PU_PD_INIT_ENUM                      PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATD_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATD_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATD_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATD_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATC_PU_PD_SHIFT                  _MK_SHIFT_CONST(4)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATC_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_A_0_ATC_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATC_PU_PD_RANGE                  5:4
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATC_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATC_PU_PD_DEFAULT                        _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATC_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATC_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATC_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATC_PU_PD_INIT_ENUM                      PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATC_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATC_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATC_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATC_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATB_PU_PD_SHIFT                  _MK_SHIFT_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATB_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_A_0_ATB_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATB_PU_PD_RANGE                  3:2
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATB_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATB_PU_PD_DEFAULT                        _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATB_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATB_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATB_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATB_PU_PD_INIT_ENUM                      PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATB_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATB_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATB_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATB_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATA_PU_PD_SHIFT                  _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATA_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_A_0_ATA_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATA_PU_PD_RANGE                  1:0
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATA_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATA_PU_PD_DEFAULT                        _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATA_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATA_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATA_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATA_PU_PD_INIT_ENUM                      PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATA_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATA_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATA_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATA_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+
+// Register APB_MISC_PP_PULLUPDOWN_REG_B_0  
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0                  _MK_ADDR_CONST(0xa4)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_WORD_COUNT                       0x1
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_RESET_VAL                        _MK_MASK_CONST(0x6a8aaaaa)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXK_PU_PD_SHIFT                 _MK_SHIFT_CONST(30)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXK_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXK_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXK_PU_PD_RANGE                 31:30
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXK_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXK_PU_PD_DEFAULT                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXK_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXK_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXK_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXK_PU_PD_INIT_ENUM                     PULL_DOWN
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXK_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXK_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXK_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXK_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXD_PU_PD_SHIFT                 _MK_SHIFT_CONST(28)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXD_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXD_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXD_PU_PD_RANGE                 29:28
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXD_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXD_PU_PD_DEFAULT                       _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXD_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXD_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXD_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXD_PU_PD_INIT_ENUM                     PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXD_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXD_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXD_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXD_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXC_PU_PD_SHIFT                 _MK_SHIFT_CONST(26)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXC_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXC_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXC_PU_PD_RANGE                 27:26
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXC_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXC_PU_PD_DEFAULT                       _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXC_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXC_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXC_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXC_PU_PD_INIT_ENUM                     PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXC_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXC_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXC_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXC_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXB_PU_PD_SHIFT                 _MK_SHIFT_CONST(24)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXB_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXB_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXB_PU_PD_RANGE                 25:24
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXB_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXB_PU_PD_DEFAULT                       _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXB_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXB_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXB_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXB_PU_PD_INIT_ENUM                     PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXB_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXB_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXB_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXB_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXA_PU_PD_SHIFT                 _MK_SHIFT_CONST(22)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXA_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXA_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXA_PU_PD_RANGE                 23:22
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXA_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXA_PU_PD_DEFAULT                       _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXA_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXA_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXA_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXA_PU_PD_INIT_ENUM                     PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXA_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXA_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXA_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXA_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU_PU_PD_SHIFT                  _MK_SHIFT_CONST(20)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU_PU_PD_RANGE                  21:20
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU_PU_PD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU_PU_PD_INIT_ENUM                      NORMAL
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDO_PU_PD_SHIFT                 _MK_SHIFT_CONST(18)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDO_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDO_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDO_PU_PD_RANGE                 19:18
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDO_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDO_PU_PD_DEFAULT                       _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDO_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDO_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDO_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDO_PU_PD_INIT_ENUM                     PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDO_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDO_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDO_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDO_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDI_PU_PD_SHIFT                 _MK_SHIFT_CONST(16)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDI_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDI_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDI_PU_PD_RANGE                 17:16
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDI_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDI_PU_PD_DEFAULT                       _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDI_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDI_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDI_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDI_PU_PD_INIT_ENUM                     PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDI_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDI_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDI_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDI_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCD_PU_PD_SHIFT                 _MK_SHIFT_CONST(14)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCD_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCD_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCD_PU_PD_RANGE                 15:14
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCD_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCD_PU_PD_DEFAULT                       _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCD_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCD_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCD_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCD_PU_PD_INIT_ENUM                     PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCD_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCD_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCD_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCD_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCC_PU_PD_SHIFT                 _MK_SHIFT_CONST(12)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCC_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCC_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCC_PU_PD_RANGE                 13:12
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCC_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCC_PU_PD_DEFAULT                       _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCC_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCC_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCC_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCC_PU_PD_INIT_ENUM                     PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCC_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCC_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCC_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCC_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCB_PU_PD_SHIFT                 _MK_SHIFT_CONST(10)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCB_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCB_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCB_PU_PD_RANGE                 11:10
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCB_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCB_PU_PD_DEFAULT                       _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCB_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCB_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCB_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCB_PU_PD_INIT_ENUM                     PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCB_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCB_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCB_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCB_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCA_PU_PD_SHIFT                 _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCA_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCA_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCA_PU_PD_RANGE                 9:8
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCA_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCA_PU_PD_DEFAULT                       _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCA_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCA_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCA_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCA_PU_PD_INIT_ENUM                     PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCA_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCA_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCA_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCA_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU7_PU_PD_SHIFT                 _MK_SHIFT_CONST(6)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU7_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU7_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU7_PU_PD_RANGE                 7:6
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU7_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU7_PU_PD_DEFAULT                       _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU7_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU7_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU7_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU7_PU_PD_INIT_ENUM                     PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU7_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU7_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU7_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU7_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_PTA_PU_PD_SHIFT                  _MK_SHIFT_CONST(4)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_PTA_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_B_0_PTA_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_PTA_PU_PD_RANGE                  5:4
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_PTA_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_PTA_PU_PD_DEFAULT                        _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_PTA_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_PTA_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_PTA_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_PTA_PU_PD_INIT_ENUM                      PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_PTA_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_PTA_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_PTA_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_PTA_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_I2CP_PU_PD_SHIFT                 _MK_SHIFT_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_I2CP_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_B_0_I2CP_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_I2CP_PU_PD_RANGE                 3:2
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_I2CP_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_I2CP_PU_PD_DEFAULT                       _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_I2CP_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_I2CP_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_I2CP_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_I2CP_PU_PD_INIT_ENUM                     PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_I2CP_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_I2CP_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_I2CP_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_I2CP_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_RM_PU_PD_SHIFT                   _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_RM_PU_PD_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_B_0_RM_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_RM_PU_PD_RANGE                   1:0
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_RM_PU_PD_WOFFSET                 0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_RM_PU_PD_DEFAULT                 _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_RM_PU_PD_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_RM_PU_PD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_RM_PU_PD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_RM_PU_PD_INIT_ENUM                       PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_RM_PU_PD_NORMAL                  _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_RM_PU_PD_PULL_DOWN                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_RM_PU_PD_PULL_UP                 _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_RM_PU_PD_RSVD                    _MK_ENUM_CONST(3)
+
+
+// Register APB_MISC_PP_PULLUPDOWN_REG_C_0  
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0                  _MK_ADDR_CONST(0xa8)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_WORD_COUNT                       0x1
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_RESET_VAL                        _MK_MASK_CONST(0xaa6655)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2S_PU_PD_SHIFT                 _MK_SHIFT_CONST(30)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2S_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2S_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2S_PU_PD_RANGE                 31:30
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2S_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2S_PU_PD_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2S_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2S_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2S_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2S_PU_PD_INIT_ENUM                     NORMAL
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2S_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2S_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2S_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2S_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2D_PU_PD_SHIFT                 _MK_SHIFT_CONST(28)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2D_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2D_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2D_PU_PD_RANGE                 29:28
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2D_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2D_PU_PD_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2D_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2D_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2D_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2D_PU_PD_INIT_ENUM                     NORMAL
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2D_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2D_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2D_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2D_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2C_PU_PD_SHIFT                 _MK_SHIFT_CONST(26)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2C_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2C_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2C_PU_PD_RANGE                 27:26
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2C_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2C_PU_PD_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2C_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2C_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2C_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2C_PU_PD_INIT_ENUM                     NORMAL
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2C_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2C_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2C_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2C_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2A_PU_PD_SHIFT                 _MK_SHIFT_CONST(24)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2A_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2A_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2A_PU_PD_RANGE                 25:24
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2A_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2A_PU_PD_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2A_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2A_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2A_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2A_PU_PD_INIT_ENUM                     NORMAL
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2A_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2A_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2A_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2A_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRRX_PU_PD_SHIFT                 _MK_SHIFT_CONST(22)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRRX_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_C_0_IRRX_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRRX_PU_PD_RANGE                 23:22
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRRX_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRRX_PU_PD_DEFAULT                       _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRRX_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRRX_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRRX_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRRX_PU_PD_INIT_ENUM                     PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRRX_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRRX_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRRX_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRRX_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRTX_PU_PD_SHIFT                 _MK_SHIFT_CONST(20)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRTX_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_C_0_IRTX_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRTX_PU_PD_RANGE                 21:20
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRTX_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRTX_PU_PD_DEFAULT                       _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRTX_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRTX_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRTX_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRTX_PU_PD_INIT_ENUM                     PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRTX_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRTX_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRTX_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRTX_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIH_PU_PD_SHIFT                 _MK_SHIFT_CONST(18)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIH_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIH_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIH_PU_PD_RANGE                 19:18
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIH_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIH_PU_PD_DEFAULT                       _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIH_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIH_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIH_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIH_PU_PD_INIT_ENUM                     PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIH_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIH_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIH_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIH_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIG_PU_PD_SHIFT                 _MK_SHIFT_CONST(16)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIG_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIG_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIG_PU_PD_RANGE                 17:16
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIG_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIG_PU_PD_DEFAULT                       _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIG_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIG_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIG_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIG_PU_PD_INIT_ENUM                     PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIG_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIG_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIG_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIG_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIF_PU_PD_SHIFT                 _MK_SHIFT_CONST(14)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIF_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIF_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIF_PU_PD_RANGE                 15:14
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIF_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIF_PU_PD_DEFAULT                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIF_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIF_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIF_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIF_PU_PD_INIT_ENUM                     PULL_DOWN
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIF_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIF_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIF_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIF_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIE_PU_PD_SHIFT                 _MK_SHIFT_CONST(12)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIE_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIE_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIE_PU_PD_RANGE                 13:12
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIE_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIE_PU_PD_DEFAULT                       _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIE_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIE_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIE_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIE_PU_PD_INIT_ENUM                     PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIE_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIE_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIE_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIE_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPID_PU_PD_SHIFT                 _MK_SHIFT_CONST(10)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPID_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_C_0_SPID_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPID_PU_PD_RANGE                 11:10
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPID_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPID_PU_PD_DEFAULT                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPID_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPID_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPID_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPID_PU_PD_INIT_ENUM                     PULL_DOWN
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPID_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPID_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPID_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPID_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIC_PU_PD_SHIFT                 _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIC_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIC_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIC_PU_PD_RANGE                 9:8
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIC_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIC_PU_PD_DEFAULT                       _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIC_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIC_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIC_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIC_PU_PD_INIT_ENUM                     PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIC_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIC_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIC_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIC_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIB_PU_PD_SHIFT                 _MK_SHIFT_CONST(6)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIB_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIB_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIB_PU_PD_RANGE                 7:6
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIB_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIB_PU_PD_DEFAULT                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIB_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIB_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIB_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIB_PU_PD_INIT_ENUM                     PULL_DOWN
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIB_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIB_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIB_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIB_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIA_PU_PD_SHIFT                 _MK_SHIFT_CONST(4)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIA_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIA_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIA_PU_PD_RANGE                 5:4
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIA_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIA_PU_PD_DEFAULT                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIA_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIA_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIA_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIA_PU_PD_INIT_ENUM                     PULL_DOWN
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIA_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIA_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIA_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIA_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV2_PU_PD_SHIFT                        _MK_SHIFT_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV2_PU_PD_FIELD                        (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV2_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV2_PU_PD_RANGE                        3:2
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV2_PU_PD_WOFFSET                      0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV2_PU_PD_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV2_PU_PD_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV2_PU_PD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV2_PU_PD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV2_PU_PD_INIT_ENUM                    PULL_DOWN
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV2_PU_PD_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV2_PU_PD_PULL_DOWN                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV2_PU_PD_PULL_UP                      _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV2_PU_PD_RSVD                 _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV1_PU_PD_SHIFT                        _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV1_PU_PD_FIELD                        (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV1_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV1_PU_PD_RANGE                        1:0
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV1_PU_PD_WOFFSET                      0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV1_PU_PD_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV1_PU_PD_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV1_PU_PD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV1_PU_PD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV1_PU_PD_INIT_ENUM                    PULL_DOWN
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV1_PU_PD_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV1_PU_PD_PULL_DOWN                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV1_PU_PD_PULL_UP                      _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV1_PU_PD_RSVD                 _MK_ENUM_CONST(3)
+
+
+// Register APB_MISC_PP_PULLUPDOWN_REG_D_0  
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0                  _MK_ADDR_CONST(0xac)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_WORD_COUNT                       0x1
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_RESET_VAL                        _MK_MASK_CONST(0xa8a55a8a)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDD_PU_PD_SHIFT                  _MK_SHIFT_CONST(30)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDD_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_D_0_SDD_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDD_PU_PD_RANGE                  31:30
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDD_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDD_PU_PD_DEFAULT                        _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDD_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDD_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDD_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDD_PU_PD_INIT_ENUM                      PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDD_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDD_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDD_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDD_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDC_PU_PD_SHIFT                  _MK_SHIFT_CONST(28)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDC_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_D_0_SDC_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDC_PU_PD_RANGE                  29:28
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDC_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDC_PU_PD_DEFAULT                        _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDC_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDC_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDC_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDC_PU_PD_INIT_ENUM                      PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDC_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDC_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDC_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDC_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDB_PU_PD_SHIFT                  _MK_SHIFT_CONST(26)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDB_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_D_0_SDB_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDB_PU_PD_RANGE                  27:26
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDB_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDB_PU_PD_DEFAULT                        _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDB_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDB_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDB_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDB_PU_PD_INIT_ENUM                      PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDB_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDB_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDB_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDB_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+// LC_P? for : lcd_pclk, lcd_de, lcd_hsycn, lcd_vsync, lcd_m0, lcd_m1, lcd_vp0, hdmi_int
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_CSUS_PU_PD_SHIFT                 _MK_SHIFT_CONST(24)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_CSUS_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_D_0_CSUS_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_CSUS_PU_PD_RANGE                 25:24
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_CSUS_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_CSUS_PU_PD_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_CSUS_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_CSUS_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_CSUS_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_CSUS_PU_PD_INIT_ENUM                     NORMAL
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_CSUS_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_CSUS_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_CSUS_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_CSUS_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+// LS_P? for : lcd_sdin, lcd_sdout, lcd_wr_, lcd_cs0, lcd_dc0, lcd_sck, lcd_pwr0, lcd_pwr1, lcd_pwr2
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LC_PU_PD_SHIFT                   _MK_SHIFT_CONST(22)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LC_PU_PD_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_D_0_LC_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LC_PU_PD_RANGE                   23:22
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LC_PU_PD_WOFFSET                 0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LC_PU_PD_DEFAULT                 _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LC_PU_PD_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LC_PU_PD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LC_PU_PD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LC_PU_PD_INIT_ENUM                       PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LC_PU_PD_NORMAL                  _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LC_PU_PD_PULL_DOWN                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LC_PU_PD_PULL_UP                 _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LC_PU_PD_RSVD                    _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LS_PU_PD_SHIFT                   _MK_SHIFT_CONST(20)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LS_PU_PD_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_D_0_LS_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LS_PU_PD_RANGE                   21:20
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LS_PU_PD_WOFFSET                 0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LS_PU_PD_DEFAULT                 _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LS_PU_PD_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LS_PU_PD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LS_PU_PD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LS_PU_PD_INIT_ENUM                       PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LS_PU_PD_NORMAL                  _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LS_PU_PD_PULL_DOWN                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LS_PU_PD_PULL_UP                 _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LS_PU_PD_RSVD                    _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD23_22_PU_PD_SHIFT                      _MK_SHIFT_CONST(18)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD23_22_PU_PD_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_D_0_LD23_22_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD23_22_PU_PD_RANGE                      19:18
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD23_22_PU_PD_WOFFSET                    0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD23_22_PU_PD_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD23_22_PU_PD_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD23_22_PU_PD_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD23_22_PU_PD_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD23_22_PU_PD_INIT_ENUM                  PULL_DOWN
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD23_22_PU_PD_NORMAL                     _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD23_22_PU_PD_PULL_DOWN                  _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD23_22_PU_PD_PULL_UP                    _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD23_22_PU_PD_RSVD                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD21_20_PU_PD_SHIFT                      _MK_SHIFT_CONST(16)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD21_20_PU_PD_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_D_0_LD21_20_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD21_20_PU_PD_RANGE                      17:16
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD21_20_PU_PD_WOFFSET                    0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD21_20_PU_PD_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD21_20_PU_PD_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD21_20_PU_PD_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD21_20_PU_PD_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD21_20_PU_PD_INIT_ENUM                  PULL_DOWN
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD21_20_PU_PD_NORMAL                     _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD21_20_PU_PD_PULL_DOWN                  _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD21_20_PU_PD_PULL_UP                    _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD21_20_PU_PD_RSVD                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD19_18_PU_PD_SHIFT                      _MK_SHIFT_CONST(14)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD19_18_PU_PD_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_D_0_LD19_18_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD19_18_PU_PD_RANGE                      15:14
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD19_18_PU_PD_WOFFSET                    0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD19_18_PU_PD_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD19_18_PU_PD_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD19_18_PU_PD_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD19_18_PU_PD_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD19_18_PU_PD_INIT_ENUM                  PULL_DOWN
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD19_18_PU_PD_NORMAL                     _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD19_18_PU_PD_PULL_DOWN                  _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD19_18_PU_PD_PULL_UP                    _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD19_18_PU_PD_RSVD                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD17_0_PU_PD_SHIFT                       _MK_SHIFT_CONST(12)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD17_0_PU_PD_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_D_0_LD17_0_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD17_0_PU_PD_RANGE                       13:12
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD17_0_PU_PD_WOFFSET                     0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD17_0_PU_PD_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD17_0_PU_PD_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD17_0_PU_PD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD17_0_PU_PD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD17_0_PU_PD_INIT_ENUM                   PULL_DOWN
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD17_0_PU_PD_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD17_0_PU_PD_PULL_DOWN                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD17_0_PU_PD_PULL_UP                     _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD17_0_PU_PD_RSVD                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCB_PU_PD_SHIFT                  _MK_SHIFT_CONST(10)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCB_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_D_0_UCB_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCB_PU_PD_RANGE                  11:10
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCB_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCB_PU_PD_DEFAULT                        _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCB_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCB_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCB_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCB_PU_PD_INIT_ENUM                      PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCB_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCB_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCB_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCB_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCA_PU_PD_SHIFT                  _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCA_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_D_0_UCA_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCA_PU_PD_RANGE                  9:8
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCA_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCA_PU_PD_DEFAULT                        _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCA_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCA_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCA_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCA_PU_PD_INIT_ENUM                      PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCA_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCA_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCA_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCA_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAD_PU_PD_SHIFT                  _MK_SHIFT_CONST(6)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAD_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_D_0_UAD_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAD_PU_PD_RANGE                  7:6
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAD_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAD_PU_PD_DEFAULT                        _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAD_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAD_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAD_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAD_PU_PD_INIT_ENUM                      PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAD_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAD_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAD_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAD_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAC_PU_PD_SHIFT                  _MK_SHIFT_CONST(4)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAC_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_D_0_UAC_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAC_PU_PD_RANGE                  5:4
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAC_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAC_PU_PD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAC_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAC_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAC_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAC_PU_PD_INIT_ENUM                      NORMAL
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAC_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAC_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAC_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAC_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAB_PU_PD_SHIFT                  _MK_SHIFT_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAB_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_D_0_UAB_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAB_PU_PD_RANGE                  3:2
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAB_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAB_PU_PD_DEFAULT                        _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAB_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAB_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAB_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAB_PU_PD_INIT_ENUM                      PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAB_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAB_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAB_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAB_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAA_PU_PD_SHIFT                  _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAA_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_D_0_UAA_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAA_PU_PD_RANGE                  1:0
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAA_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAA_PU_PD_DEFAULT                        _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAA_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAA_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAA_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAA_PU_PD_INIT_ENUM                      PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAA_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAA_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAA_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAA_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+
+// Register APB_MISC_PP_PULLUPDOWN_REG_E_0  
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0                  _MK_ADDR_CONST(0xb0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_WORD_COUNT                       0x1
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_RESET_VAL                        _MK_MASK_CONST(0xa)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_RSVD_7_SHIFT                     _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_RSVD_7_FIELD                     (_MK_MASK_CONST(0xffffff) << APB_MISC_PP_PULLUPDOWN_REG_E_0_RSVD_7_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_RSVD_7_RANGE                     31:8
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_RSVD_7_WOFFSET                   0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_RSVD_7_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_RSVD_7_DEFAULT_MASK                      _MK_MASK_CONST(0xffffff)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_RSVD_7_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_RSVD_7_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCB_PU_PD_SHIFT                 _MK_SHIFT_CONST(6)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCB_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCB_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCB_PU_PD_RANGE                 7:6
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCB_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCB_PU_PD_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCB_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCB_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCB_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCB_PU_PD_INIT_ENUM                     NORMAL
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCB_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCB_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCB_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCB_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCA_PU_PD_SHIFT                 _MK_SHIFT_CONST(4)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCA_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCA_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCA_PU_PD_RANGE                 5:4
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCA_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCA_PU_PD_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCA_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCA_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCA_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCA_PU_PD_INIT_ENUM                     NORMAL
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCA_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCA_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCA_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCA_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCE_PU_PD_SHIFT                 _MK_SHIFT_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCE_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCE_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCE_PU_PD_RANGE                 3:2
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCE_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCE_PU_PD_DEFAULT                       _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCE_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCE_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCE_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCE_PU_PD_INIT_ENUM                     PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCE_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCE_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCE_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCE_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCF_PU_PD_SHIFT                 _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCF_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCF_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCF_PU_PD_RANGE                 1:0
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCF_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCF_PU_PD_DEFAULT                       _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCF_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCF_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCF_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCF_PU_PD_INIT_ENUM                     PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCF_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCF_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCF_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCF_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+
+// Register APB_MISC_ASYNC_COREPWRCONFIG_0  
+#define APB_MISC_ASYNC_COREPWRCONFIG_0                  _MK_ADDR_CONST(0x400)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_WORD_COUNT                       0x1
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_RESET_MASK                       _MK_MASK_CONST(0x7)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_READ_MASK                        _MK_MASK_CONST(0x7)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_WRITE_MASK                       _MK_MASK_CONST(0x7)
+// Power is on in TDA/TDB partitions
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_TD_COREPWR_EN_SHIFT                      _MK_SHIFT_CONST(0)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_TD_COREPWR_EN_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_COREPWRCONFIG_0_TD_COREPWR_EN_SHIFT)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_TD_COREPWR_EN_RANGE                      0:0
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_TD_COREPWR_EN_WOFFSET                    0x0
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_TD_COREPWR_EN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_TD_COREPWR_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_TD_COREPWR_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_TD_COREPWR_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_TD_COREPWR_EN_INIT_ENUM                  DISABLE
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_TD_COREPWR_EN_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_TD_COREPWR_EN_ENABLE                     _MK_ENUM_CONST(1)
+
+// Power is on in VE/MPE partitions
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_VE_COREPWR_EN_SHIFT                      _MK_SHIFT_CONST(1)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_VE_COREPWR_EN_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_COREPWRCONFIG_0_VE_COREPWR_EN_SHIFT)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_VE_COREPWR_EN_RANGE                      1:1
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_VE_COREPWR_EN_WOFFSET                    0x0
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_VE_COREPWR_EN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_VE_COREPWR_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_VE_COREPWR_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_VE_COREPWR_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_VE_COREPWR_EN_INIT_ENUM                  DISABLE
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_VE_COREPWR_EN_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_VE_COREPWR_EN_ENABLE                     _MK_ENUM_CONST(1)
+
+// Power is on in CPU partition
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_CPU_COREPWR_EN_SHIFT                     _MK_SHIFT_CONST(2)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_CPU_COREPWR_EN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_COREPWRCONFIG_0_CPU_COREPWR_EN_SHIFT)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_CPU_COREPWR_EN_RANGE                     2:2
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_CPU_COREPWR_EN_WOFFSET                   0x0
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_CPU_COREPWR_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_CPU_COREPWR_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_CPU_COREPWR_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_CPU_COREPWR_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_CPU_COREPWR_EN_INIT_ENUM                 DISABLE
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_CPU_COREPWR_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_CPU_COREPWR_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+
+// Reserved address 1028 [0x404] 
+
+// Register APB_MISC_ASYNC_DLYCTRL_0  
+#define APB_MISC_ASYNC_DLYCTRL_0                        _MK_ADDR_CONST(0x408)
+#define APB_MISC_ASYNC_DLYCTRL_0_WORD_COUNT                     0x1
+#define APB_MISC_ASYNC_DLYCTRL_0_RESET_VAL                      _MK_MASK_CONST(0x8)
+#define APB_MISC_ASYNC_DLYCTRL_0_RESET_MASK                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_ASYNC_DLYCTRL_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_DLYCTRL_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_DLYCTRL_0_READ_MASK                      _MK_MASK_CONST(0x1f)
+#define APB_MISC_ASYNC_DLYCTRL_0_WRITE_MASK                     _MK_MASK_CONST(0x1f)
+// Delay on RDY output.  
+#define APB_MISC_ASYNC_DLYCTRL_0_RDY_DLY_SHIFT                  _MK_SHIFT_CONST(0)
+#define APB_MISC_ASYNC_DLYCTRL_0_RDY_DLY_FIELD                  (_MK_MASK_CONST(0x1f) << APB_MISC_ASYNC_DLYCTRL_0_RDY_DLY_SHIFT)
+#define APB_MISC_ASYNC_DLYCTRL_0_RDY_DLY_RANGE                  4:0
+#define APB_MISC_ASYNC_DLYCTRL_0_RDY_DLY_WOFFSET                        0x0
+#define APB_MISC_ASYNC_DLYCTRL_0_RDY_DLY_DEFAULT                        _MK_MASK_CONST(0x8)
+#define APB_MISC_ASYNC_DLYCTRL_0_RDY_DLY_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define APB_MISC_ASYNC_DLYCTRL_0_RDY_DLY_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_DLYCTRL_0_RDY_DLY_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_ASYNC_CLKMNTREN_0  
+#define APB_MISC_ASYNC_CLKMNTREN_0                      _MK_ADDR_CONST(0x40c)
+#define APB_MISC_ASYNC_CLKMNTREN_0_WORD_COUNT                   0x1
+#define APB_MISC_ASYNC_CLKMNTREN_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_CLKMNTREN_0_RESET_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_CLKMNTREN_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_CLKMNTREN_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_CLKMNTREN_0_READ_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_CLKMNTREN_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
+// clock monitor enable
+#define APB_MISC_ASYNC_CLKMNTREN_0_CLK_MONITOR_EN_SHIFT                 _MK_SHIFT_CONST(0)
+#define APB_MISC_ASYNC_CLKMNTREN_0_CLK_MONITOR_EN_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_CLKMNTREN_0_CLK_MONITOR_EN_SHIFT)
+#define APB_MISC_ASYNC_CLKMNTREN_0_CLK_MONITOR_EN_RANGE                 0:0
+#define APB_MISC_ASYNC_CLKMNTREN_0_CLK_MONITOR_EN_WOFFSET                       0x0
+#define APB_MISC_ASYNC_CLKMNTREN_0_CLK_MONITOR_EN_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_CLKMNTREN_0_CLK_MONITOR_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_CLKMNTREN_0_CLK_MONITOR_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_CLKMNTREN_0_CLK_MONITOR_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_CLKMNTREN_0_CLK_MONITOR_EN_DISABLE                       _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_CLKMNTREN_0_CLK_MONITOR_EN_ENABLE                        _MK_ENUM_CONST(1)
+
+
+// Register APB_MISC_ASYNC_EMCPADEN_0  
+#define APB_MISC_ASYNC_EMCPADEN_0                       _MK_ADDR_CONST(0x410)
+#define APB_MISC_ASYNC_EMCPADEN_0_WORD_COUNT                    0x1
+#define APB_MISC_ASYNC_EMCPADEN_0_RESET_VAL                     _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_EMCPADEN_0_RESET_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_EMCPADEN_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_EMCPADEN_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_EMCPADEN_0_READ_MASK                     _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_EMCPADEN_0_WRITE_MASK                    _MK_MASK_CONST(0x3)
+// outputs enable for EMC pads
+#define APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_OUTPUT_EN_SHIFT                       _MK_SHIFT_CONST(0)
+#define APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_OUTPUT_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_OUTPUT_EN_SHIFT)
+#define APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_OUTPUT_EN_RANGE                       0:0
+#define APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_OUTPUT_EN_WOFFSET                     0x0
+#define APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_OUTPUT_EN_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_OUTPUT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_OUTPUT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_OUTPUT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_OUTPUT_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_OUTPUT_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// inputs enable for EMC pads
+#define APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_INPUT_EN_SHIFT                        _MK_SHIFT_CONST(1)
+#define APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_INPUT_EN_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_INPUT_EN_SHIFT)
+#define APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_INPUT_EN_RANGE                        1:1
+#define APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_INPUT_EN_WOFFSET                      0x0
+#define APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_INPUT_EN_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_INPUT_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_INPUT_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_INPUT_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_INPUT_EN_DISABLE                      _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_INPUT_EN_ENABLE                       _MK_ENUM_CONST(1)
+
+
+// Register APB_MISC_ASYNC_EMCPADCTRL_0  
+#define APB_MISC_ASYNC_EMCPADCTRL_0                     _MK_ADDR_CONST(0x414)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_WORD_COUNT                  0x1
+#define APB_MISC_ASYNC_EMCPADCTRL_0_RESET_VAL                   _MK_MASK_CONST(0xff0f1)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_RESET_MASK                  _MK_MASK_CONST(0x1ff3f3)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_READ_MASK                   _MK_MASK_CONST(0x1ff3f3)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_WRITE_MASK                  _MK_MASK_CONST(0x1ff3f3)
+// EMC 3.3V mode enable
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM_33V_EN_SHIFT                    _MK_SHIFT_CONST(0)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM_33V_EN_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_EMCPADCTRL_0_MEM_33V_EN_SHIFT)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM_33V_EN_RANGE                    0:0
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM_33V_EN_WOFFSET                  0x0
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM_33V_EN_DEFAULT                  _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM_33V_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM_33V_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM_33V_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM_33V_EN_DISABLE                  _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM_33V_EN_ENABLE                   _MK_ENUM_CONST(1)
+
+// EMC vref enable
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM_VREF_EN_SHIFT                   _MK_SHIFT_CONST(1)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM_VREF_EN_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_EMCPADCTRL_0_MEM_VREF_EN_SHIFT)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM_VREF_EN_RANGE                   1:1
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM_VREF_EN_WOFFSET                 0x0
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM_VREF_EN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM_VREF_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM_VREF_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM_VREF_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM_VREF_EN_DISABLE                 _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM_VREF_EN_ENABLE                  _MK_ENUM_CONST(1)
+
+// EMC data pins high speed mode enable
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_DAT_HSM_EN_SHIFT                       _MK_SHIFT_CONST(4)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_DAT_HSM_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_DAT_HSM_EN_SHIFT)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_DAT_HSM_EN_RANGE                       4:4
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_DAT_HSM_EN_WOFFSET                     0x0
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_DAT_HSM_EN_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_DAT_HSM_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_DAT_HSM_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_DAT_HSM_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_DAT_HSM_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_DAT_HSM_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// EMC data pins high speed mode enable
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_DAT_HSM_EN_SHIFT                       _MK_SHIFT_CONST(5)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_DAT_HSM_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_DAT_HSM_EN_SHIFT)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_DAT_HSM_EN_RANGE                       5:5
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_DAT_HSM_EN_WOFFSET                     0x0
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_DAT_HSM_EN_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_DAT_HSM_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_DAT_HSM_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_DAT_HSM_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_DAT_HSM_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_DAT_HSM_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// EMC control pins high speed mode enable
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_CTRL_HSM_EN_SHIFT                      _MK_SHIFT_CONST(6)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_CTRL_HSM_EN_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_CTRL_HSM_EN_SHIFT)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_CTRL_HSM_EN_RANGE                      6:6
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_CTRL_HSM_EN_WOFFSET                    0x0
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_CTRL_HSM_EN_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_CTRL_HSM_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_CTRL_HSM_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_CTRL_HSM_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_CTRL_HSM_EN_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_CTRL_HSM_EN_ENABLE                     _MK_ENUM_CONST(1)
+
+// EMC control pins high speed mode enable
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_CTRL_HSM_EN_SHIFT                      _MK_SHIFT_CONST(7)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_CTRL_HSM_EN_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_CTRL_HSM_EN_SHIFT)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_CTRL_HSM_EN_RANGE                      7:7
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_CTRL_HSM_EN_WOFFSET                    0x0
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_CTRL_HSM_EN_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_CTRL_HSM_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_CTRL_HSM_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_CTRL_HSM_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_CTRL_HSM_EN_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_CTRL_HSM_EN_ENABLE                     _MK_ENUM_CONST(1)
+
+// EMC data pins schmidt enable
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_DAT_SCHMT_EN_SHIFT                     _MK_SHIFT_CONST(8)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_DAT_SCHMT_EN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_DAT_SCHMT_EN_SHIFT)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_DAT_SCHMT_EN_RANGE                     8:8
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_DAT_SCHMT_EN_WOFFSET                   0x0
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_DAT_SCHMT_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_DAT_SCHMT_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_DAT_SCHMT_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_DAT_SCHMT_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_DAT_SCHMT_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_DAT_SCHMT_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// EMC data pins schmidt enable
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_DAT_SCHMT_EN_SHIFT                     _MK_SHIFT_CONST(9)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_DAT_SCHMT_EN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_DAT_SCHMT_EN_SHIFT)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_DAT_SCHMT_EN_RANGE                     9:9
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_DAT_SCHMT_EN_WOFFSET                   0x0
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_DAT_SCHMT_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_DAT_SCHMT_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_DAT_SCHMT_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_DAT_SCHMT_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_DAT_SCHMT_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_DAT_SCHMT_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// EMC data pins low power mode select
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_DAT_LPMD_SHIFT                 _MK_SHIFT_CONST(12)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_DAT_LPMD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_DAT_LPMD_SHIFT)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_DAT_LPMD_RANGE                 13:12
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_DAT_LPMD_WOFFSET                       0x0
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_DAT_LPMD_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_DAT_LPMD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_DAT_LPMD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_DAT_LPMD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// EMC data pins low power mode select
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_DAT_LPMD_SHIFT                 _MK_SHIFT_CONST(14)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_DAT_LPMD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_DAT_LPMD_SHIFT)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_DAT_LPMD_RANGE                 15:14
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_DAT_LPMD_WOFFSET                       0x0
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_DAT_LPMD_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_DAT_LPMD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_DAT_LPMD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_DAT_LPMD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// EMC control pins low power mode select
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_CTRL_LPMD_SHIFT                        _MK_SHIFT_CONST(16)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_CTRL_LPMD_FIELD                        (_MK_MASK_CONST(0x3) << APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_CTRL_LPMD_SHIFT)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_CTRL_LPMD_RANGE                        17:16
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_CTRL_LPMD_WOFFSET                      0x0
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_CTRL_LPMD_DEFAULT                      _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_CTRL_LPMD_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_CTRL_LPMD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_CTRL_LPMD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// EMC control pins low power mode select
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_CTRL_LPMD_SHIFT                        _MK_SHIFT_CONST(18)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_CTRL_LPMD_FIELD                        (_MK_MASK_CONST(0x3) << APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_CTRL_LPMD_SHIFT)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_CTRL_LPMD_RANGE                        19:18
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_CTRL_LPMD_WOFFSET                      0x0
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_CTRL_LPMD_DEFAULT                      _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_CTRL_LPMD_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_CTRL_LPMD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_CTRL_LPMD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// EMC pull-down enable
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM_PULLD_SHIFT                     _MK_SHIFT_CONST(20)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM_PULLD_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_EMCPADCTRL_0_MEM_PULLD_SHIFT)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM_PULLD_RANGE                     20:20
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM_PULLD_WOFFSET                   0x0
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM_PULLD_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM_PULLD_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM_PULLD_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM_PULLD_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM_PULLD_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM_PULLD_ENABLE                    _MK_ENUM_CONST(1)
+
+
+// Register APB_MISC_ASYNC_MEMPADCAL1_0  
+#define APB_MISC_ASYNC_MEMPADCAL1_0                     _MK_ADDR_CONST(0x418)
+#define APB_MISC_ASYNC_MEMPADCAL1_0_WORD_COUNT                  0x1
+#define APB_MISC_ASYNC_MEMPADCAL1_0_RESET_VAL                   _MK_MASK_CONST(0x7f7f)
+#define APB_MISC_ASYNC_MEMPADCAL1_0_RESET_MASK                  _MK_MASK_CONST(0x7f7f)
+#define APB_MISC_ASYNC_MEMPADCAL1_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_MEMPADCAL1_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_MEMPADCAL1_0_READ_MASK                   _MK_MASK_CONST(0x7f7f)
+#define APB_MISC_ASYNC_MEMPADCAL1_0_WRITE_MASK                  _MK_MASK_CONST(0x7f7f)
+#define APB_MISC_ASYNC_MEMPADCAL1_0_MEM_CAL_DRVDN_SHIFT                 _MK_SHIFT_CONST(0)
+#define APB_MISC_ASYNC_MEMPADCAL1_0_MEM_CAL_DRVDN_FIELD                 (_MK_MASK_CONST(0x1f) << APB_MISC_ASYNC_MEMPADCAL1_0_MEM_CAL_DRVDN_SHIFT)
+#define APB_MISC_ASYNC_MEMPADCAL1_0_MEM_CAL_DRVDN_RANGE                 4:0
+#define APB_MISC_ASYNC_MEMPADCAL1_0_MEM_CAL_DRVDN_WOFFSET                       0x0
+#define APB_MISC_ASYNC_MEMPADCAL1_0_MEM_CAL_DRVDN_DEFAULT                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_ASYNC_MEMPADCAL1_0_MEM_CAL_DRVDN_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define APB_MISC_ASYNC_MEMPADCAL1_0_MEM_CAL_DRVDN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_MEMPADCAL1_0_MEM_CAL_DRVDN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_ASYNC_MEMPADCAL1_0_MEM_CAL_DRVDN_SLWR_SHIFT                    _MK_SHIFT_CONST(5)
+#define APB_MISC_ASYNC_MEMPADCAL1_0_MEM_CAL_DRVDN_SLWR_FIELD                    (_MK_MASK_CONST(0x3) << APB_MISC_ASYNC_MEMPADCAL1_0_MEM_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_ASYNC_MEMPADCAL1_0_MEM_CAL_DRVDN_SLWR_RANGE                    6:5
+#define APB_MISC_ASYNC_MEMPADCAL1_0_MEM_CAL_DRVDN_SLWR_WOFFSET                  0x0
+#define APB_MISC_ASYNC_MEMPADCAL1_0_MEM_CAL_DRVDN_SLWR_DEFAULT                  _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_MEMPADCAL1_0_MEM_CAL_DRVDN_SLWR_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_MEMPADCAL1_0_MEM_CAL_DRVDN_SLWR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_MEMPADCAL1_0_MEM_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_ASYNC_MEMPADCAL1_0_MEM_CAL_DRVUP_SHIFT                 _MK_SHIFT_CONST(8)
+#define APB_MISC_ASYNC_MEMPADCAL1_0_MEM_CAL_DRVUP_FIELD                 (_MK_MASK_CONST(0x1f) << APB_MISC_ASYNC_MEMPADCAL1_0_MEM_CAL_DRVUP_SHIFT)
+#define APB_MISC_ASYNC_MEMPADCAL1_0_MEM_CAL_DRVUP_RANGE                 12:8
+#define APB_MISC_ASYNC_MEMPADCAL1_0_MEM_CAL_DRVUP_WOFFSET                       0x0
+#define APB_MISC_ASYNC_MEMPADCAL1_0_MEM_CAL_DRVUP_DEFAULT                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_ASYNC_MEMPADCAL1_0_MEM_CAL_DRVUP_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define APB_MISC_ASYNC_MEMPADCAL1_0_MEM_CAL_DRVUP_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_MEMPADCAL1_0_MEM_CAL_DRVUP_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_ASYNC_MEMPADCAL1_0_MEM_CAL_DRVUP_SLWF_SHIFT                    _MK_SHIFT_CONST(13)
+#define APB_MISC_ASYNC_MEMPADCAL1_0_MEM_CAL_DRVUP_SLWF_FIELD                    (_MK_MASK_CONST(0x3) << APB_MISC_ASYNC_MEMPADCAL1_0_MEM_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_ASYNC_MEMPADCAL1_0_MEM_CAL_DRVUP_SLWF_RANGE                    14:13
+#define APB_MISC_ASYNC_MEMPADCAL1_0_MEM_CAL_DRVUP_SLWF_WOFFSET                  0x0
+#define APB_MISC_ASYNC_MEMPADCAL1_0_MEM_CAL_DRVUP_SLWF_DEFAULT                  _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_MEMPADCAL1_0_MEM_CAL_DRVUP_SLWF_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_MEMPADCAL1_0_MEM_CAL_DRVUP_SLWF_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_MEMPADCAL1_0_MEM_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_ASYNC_LCDPADCTRL_0  
+#define APB_MISC_ASYNC_LCDPADCTRL_0                     _MK_ADDR_CONST(0x41c)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_WORD_COUNT                  0x1
+#define APB_MISC_ASYNC_LCDPADCTRL_0_RESET_VAL                   _MK_MASK_CONST(0xff0f1)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_RESET_MASK                  _MK_MASK_CONST(0xff5f1)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_READ_MASK                   _MK_MASK_CONST(0xff5f1)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_WRITE_MASK                  _MK_MASK_CONST(0xff5f1)
+// LCD 3.3V mode enable
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD_33V_EN_SHIFT                    _MK_SHIFT_CONST(0)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD_33V_EN_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_LCDPADCTRL_0_LCD_33V_EN_SHIFT)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD_33V_EN_RANGE                    0:0
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD_33V_EN_WOFFSET                  0x0
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD_33V_EN_DEFAULT                  _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD_33V_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD_33V_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD_33V_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD_33V_EN_DISABLE                  _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD_33V_EN_ENABLE                   _MK_ENUM_CONST(1)
+
+// LCD data pins high speed mode enable
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD0_DAT_HSM_EN_SHIFT                       _MK_SHIFT_CONST(4)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD0_DAT_HSM_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_LCDPADCTRL_0_LCD0_DAT_HSM_EN_SHIFT)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD0_DAT_HSM_EN_RANGE                       4:4
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD0_DAT_HSM_EN_WOFFSET                     0x0
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD0_DAT_HSM_EN_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD0_DAT_HSM_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD0_DAT_HSM_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD0_DAT_HSM_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD0_DAT_HSM_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD0_DAT_HSM_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// LCD data pins high speed mode enable
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD1_DAT_HSM_EN_SHIFT                       _MK_SHIFT_CONST(5)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD1_DAT_HSM_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_LCDPADCTRL_0_LCD1_DAT_HSM_EN_SHIFT)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD1_DAT_HSM_EN_RANGE                       5:5
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD1_DAT_HSM_EN_WOFFSET                     0x0
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD1_DAT_HSM_EN_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD1_DAT_HSM_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD1_DAT_HSM_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD1_DAT_HSM_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD1_DAT_HSM_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD1_DAT_HSM_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// LCD control pins high speed mode enable
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD0_CTRL_HSM_EN_SHIFT                      _MK_SHIFT_CONST(6)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD0_CTRL_HSM_EN_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_LCDPADCTRL_0_LCD0_CTRL_HSM_EN_SHIFT)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD0_CTRL_HSM_EN_RANGE                      6:6
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD0_CTRL_HSM_EN_WOFFSET                    0x0
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD0_CTRL_HSM_EN_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD0_CTRL_HSM_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD0_CTRL_HSM_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD0_CTRL_HSM_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD0_CTRL_HSM_EN_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD0_CTRL_HSM_EN_ENABLE                     _MK_ENUM_CONST(1)
+
+// LCD control pins high speed mode enable
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD1_CTRL_HSM_EN_SHIFT                      _MK_SHIFT_CONST(7)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD1_CTRL_HSM_EN_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_LCDPADCTRL_0_LCD1_CTRL_HSM_EN_SHIFT)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD1_CTRL_HSM_EN_RANGE                      7:7
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD1_CTRL_HSM_EN_WOFFSET                    0x0
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD1_CTRL_HSM_EN_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD1_CTRL_HSM_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD1_CTRL_HSM_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD1_CTRL_HSM_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD1_CTRL_HSM_EN_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD1_CTRL_HSM_EN_ENABLE                     _MK_ENUM_CONST(1)
+
+// LCD data pins schmidt enable
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD_DAT_SCHMT_EN_SHIFT                      _MK_SHIFT_CONST(8)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD_DAT_SCHMT_EN_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_LCDPADCTRL_0_LCD_DAT_SCHMT_EN_SHIFT)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD_DAT_SCHMT_EN_RANGE                      8:8
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD_DAT_SCHMT_EN_WOFFSET                    0x0
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD_DAT_SCHMT_EN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD_DAT_SCHMT_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD_DAT_SCHMT_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD_DAT_SCHMT_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD_DAT_SCHMT_EN_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD_DAT_SCHMT_EN_ENABLE                     _MK_ENUM_CONST(1)
+
+// LCD control pins schmidt enable
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD_CTRL_SCHMT_EN_SHIFT                     _MK_SHIFT_CONST(10)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD_CTRL_SCHMT_EN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_LCDPADCTRL_0_LCD_CTRL_SCHMT_EN_SHIFT)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD_CTRL_SCHMT_EN_RANGE                     10:10
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD_CTRL_SCHMT_EN_WOFFSET                   0x0
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD_CTRL_SCHMT_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD_CTRL_SCHMT_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD_CTRL_SCHMT_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD_CTRL_SCHMT_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD_CTRL_SCHMT_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD_CTRL_SCHMT_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// LCD data pins low power mode select
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD0_DAT_LPMD_SHIFT                 _MK_SHIFT_CONST(12)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD0_DAT_LPMD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_ASYNC_LCDPADCTRL_0_LCD0_DAT_LPMD_SHIFT)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD0_DAT_LPMD_RANGE                 13:12
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD0_DAT_LPMD_WOFFSET                       0x0
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD0_DAT_LPMD_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD0_DAT_LPMD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD0_DAT_LPMD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD0_DAT_LPMD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// LCD data pins low power mode select
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD1_DAT_LPMD_SHIFT                 _MK_SHIFT_CONST(14)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD1_DAT_LPMD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_ASYNC_LCDPADCTRL_0_LCD1_DAT_LPMD_SHIFT)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD1_DAT_LPMD_RANGE                 15:14
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD1_DAT_LPMD_WOFFSET                       0x0
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD1_DAT_LPMD_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD1_DAT_LPMD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD1_DAT_LPMD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD1_DAT_LPMD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// LCD control pins low power mode select
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD0_CTRL_LPMD_SHIFT                        _MK_SHIFT_CONST(16)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD0_CTRL_LPMD_FIELD                        (_MK_MASK_CONST(0x3) << APB_MISC_ASYNC_LCDPADCTRL_0_LCD0_CTRL_LPMD_SHIFT)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD0_CTRL_LPMD_RANGE                        17:16
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD0_CTRL_LPMD_WOFFSET                      0x0
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD0_CTRL_LPMD_DEFAULT                      _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD0_CTRL_LPMD_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD0_CTRL_LPMD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD0_CTRL_LPMD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// LCD control pins low power mode select
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD1_CTRL_LPMD_SHIFT                        _MK_SHIFT_CONST(18)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD1_CTRL_LPMD_FIELD                        (_MK_MASK_CONST(0x3) << APB_MISC_ASYNC_LCDPADCTRL_0_LCD1_CTRL_LPMD_SHIFT)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD1_CTRL_LPMD_RANGE                        19:18
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD1_CTRL_LPMD_WOFFSET                      0x0
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD1_CTRL_LPMD_DEFAULT                      _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD1_CTRL_LPMD_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD1_CTRL_LPMD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD1_CTRL_LPMD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_ASYNC_LCDPADCAL1_0  
+#define APB_MISC_ASYNC_LCDPADCAL1_0                     _MK_ADDR_CONST(0x420)
+#define APB_MISC_ASYNC_LCDPADCAL1_0_WORD_COUNT                  0x1
+#define APB_MISC_ASYNC_LCDPADCAL1_0_RESET_VAL                   _MK_MASK_CONST(0x7f7f)
+#define APB_MISC_ASYNC_LCDPADCAL1_0_RESET_MASK                  _MK_MASK_CONST(0x7f7f)
+#define APB_MISC_ASYNC_LCDPADCAL1_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_LCDPADCAL1_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_LCDPADCAL1_0_READ_MASK                   _MK_MASK_CONST(0x7f7f)
+#define APB_MISC_ASYNC_LCDPADCAL1_0_WRITE_MASK                  _MK_MASK_CONST(0x7f7f)
+#define APB_MISC_ASYNC_LCDPADCAL1_0_LCD_CAL_DRVDN_SHIFT                 _MK_SHIFT_CONST(0)
+#define APB_MISC_ASYNC_LCDPADCAL1_0_LCD_CAL_DRVDN_FIELD                 (_MK_MASK_CONST(0x1f) << APB_MISC_ASYNC_LCDPADCAL1_0_LCD_CAL_DRVDN_SHIFT)
+#define APB_MISC_ASYNC_LCDPADCAL1_0_LCD_CAL_DRVDN_RANGE                 4:0
+#define APB_MISC_ASYNC_LCDPADCAL1_0_LCD_CAL_DRVDN_WOFFSET                       0x0
+#define APB_MISC_ASYNC_LCDPADCAL1_0_LCD_CAL_DRVDN_DEFAULT                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_ASYNC_LCDPADCAL1_0_LCD_CAL_DRVDN_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define APB_MISC_ASYNC_LCDPADCAL1_0_LCD_CAL_DRVDN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_LCDPADCAL1_0_LCD_CAL_DRVDN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_ASYNC_LCDPADCAL1_0_LCD_CAL_DRVDN_SLWR_SHIFT                    _MK_SHIFT_CONST(5)
+#define APB_MISC_ASYNC_LCDPADCAL1_0_LCD_CAL_DRVDN_SLWR_FIELD                    (_MK_MASK_CONST(0x3) << APB_MISC_ASYNC_LCDPADCAL1_0_LCD_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_ASYNC_LCDPADCAL1_0_LCD_CAL_DRVDN_SLWR_RANGE                    6:5
+#define APB_MISC_ASYNC_LCDPADCAL1_0_LCD_CAL_DRVDN_SLWR_WOFFSET                  0x0
+#define APB_MISC_ASYNC_LCDPADCAL1_0_LCD_CAL_DRVDN_SLWR_DEFAULT                  _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_LCDPADCAL1_0_LCD_CAL_DRVDN_SLWR_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_LCDPADCAL1_0_LCD_CAL_DRVDN_SLWR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_LCDPADCAL1_0_LCD_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_ASYNC_LCDPADCAL1_0_LCD_CAL_DRVUP_SHIFT                 _MK_SHIFT_CONST(8)
+#define APB_MISC_ASYNC_LCDPADCAL1_0_LCD_CAL_DRVUP_FIELD                 (_MK_MASK_CONST(0x1f) << APB_MISC_ASYNC_LCDPADCAL1_0_LCD_CAL_DRVUP_SHIFT)
+#define APB_MISC_ASYNC_LCDPADCAL1_0_LCD_CAL_DRVUP_RANGE                 12:8
+#define APB_MISC_ASYNC_LCDPADCAL1_0_LCD_CAL_DRVUP_WOFFSET                       0x0
+#define APB_MISC_ASYNC_LCDPADCAL1_0_LCD_CAL_DRVUP_DEFAULT                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_ASYNC_LCDPADCAL1_0_LCD_CAL_DRVUP_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define APB_MISC_ASYNC_LCDPADCAL1_0_LCD_CAL_DRVUP_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_LCDPADCAL1_0_LCD_CAL_DRVUP_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_ASYNC_LCDPADCAL1_0_LCD_CAL_DRVUP_SLWF_SHIFT                    _MK_SHIFT_CONST(13)
+#define APB_MISC_ASYNC_LCDPADCAL1_0_LCD_CAL_DRVUP_SLWF_FIELD                    (_MK_MASK_CONST(0x3) << APB_MISC_ASYNC_LCDPADCAL1_0_LCD_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_ASYNC_LCDPADCAL1_0_LCD_CAL_DRVUP_SLWF_RANGE                    14:13
+#define APB_MISC_ASYNC_LCDPADCAL1_0_LCD_CAL_DRVUP_SLWF_WOFFSET                  0x0
+#define APB_MISC_ASYNC_LCDPADCAL1_0_LCD_CAL_DRVUP_SLWF_DEFAULT                  _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_LCDPADCAL1_0_LCD_CAL_DRVUP_SLWF_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_LCDPADCAL1_0_LCD_CAL_DRVUP_SLWF_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_LCDPADCAL1_0_LCD_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_ASYNC_VIPADCTRL_0  
+#define APB_MISC_ASYNC_VIPADCTRL_0                      _MK_ADDR_CONST(0x424)
+#define APB_MISC_ASYNC_VIPADCTRL_0_WORD_COUNT                   0x1
+#define APB_MISC_ASYNC_VIPADCTRL_0_RESET_VAL                    _MK_MASK_CONST(0x33051)
+#define APB_MISC_ASYNC_VIPADCTRL_0_RESET_MASK                   _MK_MASK_CONST(0x33551)
+#define APB_MISC_ASYNC_VIPADCTRL_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_VIPADCTRL_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_VIPADCTRL_0_READ_MASK                    _MK_MASK_CONST(0x33551)
+#define APB_MISC_ASYNC_VIPADCTRL_0_WRITE_MASK                   _MK_MASK_CONST(0x33551)
+// VI 3.3V mode enable
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_33V_EN_SHIFT                      _MK_SHIFT_CONST(0)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_33V_EN_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_VIPADCTRL_0_VI_33V_EN_SHIFT)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_33V_EN_RANGE                      0:0
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_33V_EN_WOFFSET                    0x0
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_33V_EN_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_33V_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_33V_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_33V_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_33V_EN_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_33V_EN_ENABLE                     _MK_ENUM_CONST(1)
+
+// VI data pins high speed mode enable
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_DAT_HSM_EN_SHIFT                  _MK_SHIFT_CONST(4)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_DAT_HSM_EN_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_VIPADCTRL_0_VI_DAT_HSM_EN_SHIFT)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_DAT_HSM_EN_RANGE                  4:4
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_DAT_HSM_EN_WOFFSET                        0x0
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_DAT_HSM_EN_DEFAULT                        _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_DAT_HSM_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_DAT_HSM_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_DAT_HSM_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_DAT_HSM_EN_DISABLE                        _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_DAT_HSM_EN_ENABLE                 _MK_ENUM_CONST(1)
+
+// VI control pins high speed mode enable
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_CTRL_HSM_EN_SHIFT                 _MK_SHIFT_CONST(6)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_CTRL_HSM_EN_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_VIPADCTRL_0_VI_CTRL_HSM_EN_SHIFT)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_CTRL_HSM_EN_RANGE                 6:6
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_CTRL_HSM_EN_WOFFSET                       0x0
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_CTRL_HSM_EN_DEFAULT                       _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_CTRL_HSM_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_CTRL_HSM_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_CTRL_HSM_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_CTRL_HSM_EN_DISABLE                       _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_CTRL_HSM_EN_ENABLE                        _MK_ENUM_CONST(1)
+
+// VI data pins schmidt enable
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_DAT_SCHMT_EN_SHIFT                        _MK_SHIFT_CONST(8)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_DAT_SCHMT_EN_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_VIPADCTRL_0_VI_DAT_SCHMT_EN_SHIFT)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_DAT_SCHMT_EN_RANGE                        8:8
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_DAT_SCHMT_EN_WOFFSET                      0x0
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_DAT_SCHMT_EN_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_DAT_SCHMT_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_DAT_SCHMT_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_DAT_SCHMT_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_DAT_SCHMT_EN_DISABLE                      _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_DAT_SCHMT_EN_ENABLE                       _MK_ENUM_CONST(1)
+
+// VI control pins schmidt enable
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_CTRL_SCHMT_EN_SHIFT                       _MK_SHIFT_CONST(10)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_CTRL_SCHMT_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_VIPADCTRL_0_VI_CTRL_SCHMT_EN_SHIFT)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_CTRL_SCHMT_EN_RANGE                       10:10
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_CTRL_SCHMT_EN_WOFFSET                     0x0
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_CTRL_SCHMT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_CTRL_SCHMT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_CTRL_SCHMT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_CTRL_SCHMT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_CTRL_SCHMT_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_CTRL_SCHMT_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// VI data pins low power mode select
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_DAT_LPMD_SHIFT                    _MK_SHIFT_CONST(12)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_DAT_LPMD_FIELD                    (_MK_MASK_CONST(0x3) << APB_MISC_ASYNC_VIPADCTRL_0_VI_DAT_LPMD_SHIFT)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_DAT_LPMD_RANGE                    13:12
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_DAT_LPMD_WOFFSET                  0x0
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_DAT_LPMD_DEFAULT                  _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_DAT_LPMD_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_DAT_LPMD_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_DAT_LPMD_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// VI control pins low power mode select
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_CTRL_LPMD_SHIFT                   _MK_SHIFT_CONST(16)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_CTRL_LPMD_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_ASYNC_VIPADCTRL_0_VI_CTRL_LPMD_SHIFT)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_CTRL_LPMD_RANGE                   17:16
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_CTRL_LPMD_WOFFSET                 0x0
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_CTRL_LPMD_DEFAULT                 _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_CTRL_LPMD_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_CTRL_LPMD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_CTRL_LPMD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_ASYNC_VIPADCAL1_0  
+#define APB_MISC_ASYNC_VIPADCAL1_0                      _MK_ADDR_CONST(0x428)
+#define APB_MISC_ASYNC_VIPADCAL1_0_WORD_COUNT                   0x1
+#define APB_MISC_ASYNC_VIPADCAL1_0_RESET_VAL                    _MK_MASK_CONST(0x7f7f)
+#define APB_MISC_ASYNC_VIPADCAL1_0_RESET_MASK                   _MK_MASK_CONST(0x7f7f)
+#define APB_MISC_ASYNC_VIPADCAL1_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_VIPADCAL1_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_VIPADCAL1_0_READ_MASK                    _MK_MASK_CONST(0x7f7f)
+#define APB_MISC_ASYNC_VIPADCAL1_0_WRITE_MASK                   _MK_MASK_CONST(0x7f7f)
+#define APB_MISC_ASYNC_VIPADCAL1_0_VI_CAL_DRVDN_SHIFT                   _MK_SHIFT_CONST(0)
+#define APB_MISC_ASYNC_VIPADCAL1_0_VI_CAL_DRVDN_FIELD                   (_MK_MASK_CONST(0x1f) << APB_MISC_ASYNC_VIPADCAL1_0_VI_CAL_DRVDN_SHIFT)
+#define APB_MISC_ASYNC_VIPADCAL1_0_VI_CAL_DRVDN_RANGE                   4:0
+#define APB_MISC_ASYNC_VIPADCAL1_0_VI_CAL_DRVDN_WOFFSET                 0x0
+#define APB_MISC_ASYNC_VIPADCAL1_0_VI_CAL_DRVDN_DEFAULT                 _MK_MASK_CONST(0x1f)
+#define APB_MISC_ASYNC_VIPADCAL1_0_VI_CAL_DRVDN_DEFAULT_MASK                    _MK_MASK_CONST(0x1f)
+#define APB_MISC_ASYNC_VIPADCAL1_0_VI_CAL_DRVDN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_VIPADCAL1_0_VI_CAL_DRVDN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define APB_MISC_ASYNC_VIPADCAL1_0_VI_CAL_DRVDN_SLWR_SHIFT                      _MK_SHIFT_CONST(5)
+#define APB_MISC_ASYNC_VIPADCAL1_0_VI_CAL_DRVDN_SLWR_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_ASYNC_VIPADCAL1_0_VI_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_ASYNC_VIPADCAL1_0_VI_CAL_DRVDN_SLWR_RANGE                      6:5
+#define APB_MISC_ASYNC_VIPADCAL1_0_VI_CAL_DRVDN_SLWR_WOFFSET                    0x0
+#define APB_MISC_ASYNC_VIPADCAL1_0_VI_CAL_DRVDN_SLWR_DEFAULT                    _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_VIPADCAL1_0_VI_CAL_DRVDN_SLWR_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_VIPADCAL1_0_VI_CAL_DRVDN_SLWR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_VIPADCAL1_0_VI_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_ASYNC_VIPADCAL1_0_VI_CAL_DRVUP_SHIFT                   _MK_SHIFT_CONST(8)
+#define APB_MISC_ASYNC_VIPADCAL1_0_VI_CAL_DRVUP_FIELD                   (_MK_MASK_CONST(0x1f) << APB_MISC_ASYNC_VIPADCAL1_0_VI_CAL_DRVUP_SHIFT)
+#define APB_MISC_ASYNC_VIPADCAL1_0_VI_CAL_DRVUP_RANGE                   12:8
+#define APB_MISC_ASYNC_VIPADCAL1_0_VI_CAL_DRVUP_WOFFSET                 0x0
+#define APB_MISC_ASYNC_VIPADCAL1_0_VI_CAL_DRVUP_DEFAULT                 _MK_MASK_CONST(0x1f)
+#define APB_MISC_ASYNC_VIPADCAL1_0_VI_CAL_DRVUP_DEFAULT_MASK                    _MK_MASK_CONST(0x1f)
+#define APB_MISC_ASYNC_VIPADCAL1_0_VI_CAL_DRVUP_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_VIPADCAL1_0_VI_CAL_DRVUP_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define APB_MISC_ASYNC_VIPADCAL1_0_VI_CAL_DRVUP_SLWF_SHIFT                      _MK_SHIFT_CONST(13)
+#define APB_MISC_ASYNC_VIPADCAL1_0_VI_CAL_DRVUP_SLWF_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_ASYNC_VIPADCAL1_0_VI_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_ASYNC_VIPADCAL1_0_VI_CAL_DRVUP_SLWF_RANGE                      14:13
+#define APB_MISC_ASYNC_VIPADCAL1_0_VI_CAL_DRVUP_SLWF_WOFFSET                    0x0
+#define APB_MISC_ASYNC_VIPADCAL1_0_VI_CAL_DRVUP_SLWF_DEFAULT                    _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_VIPADCAL1_0_VI_CAL_DRVUP_SLWF_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_VIPADCAL1_0_VI_CAL_DRVUP_SLWF_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_VIPADCAL1_0_VI_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_ASYNC_VCLKCTRL_0  
+#define APB_MISC_ASYNC_VCLKCTRL_0                       _MK_ADDR_CONST(0x42c)
+#define APB_MISC_ASYNC_VCLKCTRL_0_WORD_COUNT                    0x1
+#define APB_MISC_ASYNC_VCLKCTRL_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_VCLKCTRL_0_RESET_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_VCLKCTRL_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_VCLKCTRL_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_VCLKCTRL_0_READ_MASK                     _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_VCLKCTRL_0_WRITE_MASK                    _MK_MASK_CONST(0x3)
+// VCLK input enable
+#define APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_IE_SHIFT                     _MK_SHIFT_CONST(0)
+#define APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_IE_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_IE_SHIFT)
+#define APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_IE_RANGE                     0:0
+#define APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_IE_WOFFSET                   0x0
+#define APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_IE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_IE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_IE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_IE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_IE_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_IE_ENABLE                    _MK_ENUM_CONST(1)
+
+// VCLK invert enable
+#define APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_INVERSION_SHIFT                      _MK_SHIFT_CONST(1)
+#define APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_INVERSION_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_INVERSION_SHIFT)
+#define APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_INVERSION_RANGE                      1:1
+#define APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_INVERSION_WOFFSET                    0x0
+#define APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_INVERSION_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_INVERSION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_INVERSION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_INVERSION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_INVERSION_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_INVERSION_ENABLE                     _MK_ENUM_CONST(1)
+
+
+// Reserved address 1072 [0x430] 
+
+// Reserved address 1076 [0x434] 
+
+// Register APB_MISC_ASYNC_TVDACVHSYNCCTRL_0  
+#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0                        _MK_ADDR_CONST(0x438)
+#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_WORD_COUNT                     0x1
+#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_RESET_MASK                     _MK_MASK_CONST(0xf)
+#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_READ_MASK                      _MK_MASK_CONST(0xf)
+#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_WRITE_MASK                     _MK_MASK_CONST(0xf)
+#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_TVDAC_HSYNCDLY_SHIFT                   _MK_SHIFT_CONST(0)
+#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_TVDAC_HSYNCDLY_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_TVDAC_HSYNCDLY_SHIFT)
+#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_TVDAC_HSYNCDLY_RANGE                   1:0
+#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_TVDAC_HSYNCDLY_WOFFSET                 0x0
+#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_TVDAC_HSYNCDLY_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_TVDAC_HSYNCDLY_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_TVDAC_HSYNCDLY_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_TVDAC_HSYNCDLY_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_TVDAC_VSYNCDLY_SHIFT                   _MK_SHIFT_CONST(2)
+#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_TVDAC_VSYNCDLY_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_TVDAC_VSYNCDLY_SHIFT)
+#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_TVDAC_VSYNCDLY_RANGE                   3:2
+#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_TVDAC_VSYNCDLY_WOFFSET                 0x0
+#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_TVDAC_VSYNCDLY_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_TVDAC_VSYNCDLY_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_TVDAC_VSYNCDLY_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_TVDAC_VSYNCDLY_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_ASYNC_TVDACCNTL_0  
+#define APB_MISC_ASYNC_TVDACCNTL_0                      _MK_ADDR_CONST(0x43c)
+#define APB_MISC_ASYNC_TVDACCNTL_0_WORD_COUNT                   0x1
+#define APB_MISC_ASYNC_TVDACCNTL_0_RESET_VAL                    _MK_MASK_CONST(0x83b)
+#define APB_MISC_ASYNC_TVDACCNTL_0_RESET_MASK                   _MK_MASK_CONST(0x1effffff)
+#define APB_MISC_ASYNC_TVDACCNTL_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_READ_MASK                    _MK_MASK_CONST(0x1effffff)
+#define APB_MISC_ASYNC_TVDACCNTL_0_WRITE_MASK                   _MK_MASK_CONST(0x1effffff)
+// Power down everything including the band-gap
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_IDDQ_SHIFT                       _MK_SHIFT_CONST(0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_IDDQ_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_TVDACCNTL_0_DAC_IDDQ_SHIFT)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_IDDQ_RANGE                       0:0
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_IDDQ_WOFFSET                     0x0
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_IDDQ_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_IDDQ_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_IDDQ_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_IDDQ_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_IDDQ_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_IDDQ_ENABLE                      _MK_ENUM_CONST(1)
+
+// Power down everything except the band-gap
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_POWERDOWN_SHIFT                  _MK_SHIFT_CONST(1)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_POWERDOWN_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_TVDACCNTL_0_DAC_POWERDOWN_SHIFT)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_POWERDOWN_RANGE                  1:1
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_POWERDOWN_WOFFSET                        0x0
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_POWERDOWN_DEFAULT                        _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_POWERDOWN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_POWERDOWN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_POWERDOWN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_POWERDOWN_DISABLE                        _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_POWERDOWN_ENABLE                 _MK_ENUM_CONST(1)
+
+// Power down everything including the band-gap
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_DETECT_EN_SHIFT                  _MK_SHIFT_CONST(2)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_DETECT_EN_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_TVDACCNTL_0_DAC_DETECT_EN_SHIFT)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_DETECT_EN_RANGE                  2:2
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_DETECT_EN_WOFFSET                        0x0
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_DETECT_EN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_DETECT_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_DETECT_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_DETECT_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_DETECT_EN_DISABLE                        _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_DETECT_EN_ENABLE                 _MK_ENUM_CONST(1)
+
+// Low power (sleep) mode. SHut down OUTR output
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPR_SHIFT                     _MK_SHIFT_CONST(3)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPR_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPR_SHIFT)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPR_RANGE                     3:3
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPR_WOFFSET                   0x0
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPR_DEFAULT                   _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPR_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPR_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPR_ENABLE                    _MK_ENUM_CONST(1)
+
+// Low power (sleep) mode. SHut down OUTG output
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPG_SHIFT                     _MK_SHIFT_CONST(4)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPG_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPG_SHIFT)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPG_RANGE                     4:4
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPG_WOFFSET                   0x0
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPG_DEFAULT                   _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPG_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPG_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPG_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPG_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPG_ENABLE                    _MK_ENUM_CONST(1)
+
+// Low power (sleep) mode. SHut down OUTB output
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPB_SHIFT                     _MK_SHIFT_CONST(5)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPB_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPB_SHIFT)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPB_RANGE                     5:5
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPB_WOFFSET                   0x0
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPB_DEFAULT                   _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPB_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPB_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPB_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPB_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPB_ENABLE                    _MK_ENUM_CONST(1)
+
+// Adjust threshold voltage of comparator inside DAC
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMP_TH_SHIFT                    _MK_SHIFT_CONST(6)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMP_TH_FIELD                    (_MK_MASK_CONST(0x3) << APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMP_TH_SHIFT)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMP_TH_RANGE                    7:6
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMP_TH_WOFFSET                  0x0
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMP_TH_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMP_TH_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMP_TH_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMP_TH_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Turn bandgap averaging on/off
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_AVG_ON_SHIFT                        _MK_SHIFT_CONST(8)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_AVG_ON_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_AVG_ON_SHIFT)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_AVG_ON_RANGE                        8:8
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_AVG_ON_WOFFSET                      0x0
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_AVG_ON_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_AVG_ON_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_AVG_ON_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_AVG_ON_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_AVG_ON_DISABLE                      _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_AVG_ON_ENABLE                       _MK_ENUM_CONST(1)
+
+// To adjust temp coeff
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_CURVE_SHIFT                 _MK_SHIFT_CONST(9)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_CURVE_FIELD                 (_MK_MASK_CONST(0x7) << APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_CURVE_SHIFT)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_CURVE_RANGE                 11:9
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_CURVE_WOFFSET                       0x0
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_CURVE_DEFAULT                       _MK_MASK_CONST(0x4)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_CURVE_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_CURVE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_CURVE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Control bits for bandgap
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_CNTL_SHIFT                  _MK_SHIFT_CONST(12)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_CNTL_FIELD                  (_MK_MASK_CONST(0xf) << APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_CNTL_SHIFT)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_CNTL_RANGE                  15:12
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_CNTL_WOFFSET                        0x0
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_CNTL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_CNTL_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_CNTL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_CNTL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// For debugging. Selects internal analog output to be sent out of VREF pin
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_ATEST_SHIFT                      _MK_SHIFT_CONST(16)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_ATEST_FIELD                      (_MK_MASK_CONST(0x7) << APB_MISC_ASYNC_TVDACCNTL_0_DAC_ATEST_SHIFT)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_ATEST_RANGE                      18:16
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_ATEST_WOFFSET                    0x0
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_ATEST_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_ATEST_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_ATEST_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_ATEST_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Reserved for additional control
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_CNTL_SHIFT                       _MK_SHIFT_CONST(19)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_CNTL_FIELD                       (_MK_MASK_CONST(0x1f) << APB_MISC_ASYNC_TVDACCNTL_0_DAC_CNTL_SHIFT)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_CNTL_RANGE                       23:19
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_CNTL_WOFFSET                     0x0
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_CNTL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_CNTL_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_CNTL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_CNTL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Enable COMPOUTR output
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPR_EN_SHIFT                   _MK_SHIFT_CONST(25)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPR_EN_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPR_EN_SHIFT)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPR_EN_RANGE                   25:25
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPR_EN_WOFFSET                 0x0
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPR_EN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPR_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPR_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPR_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPR_EN_DISABLE                 _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPR_EN_ENABLE                  _MK_ENUM_CONST(1)
+
+// Enable COMPOUTG output
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPG_EN_SHIFT                   _MK_SHIFT_CONST(26)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPG_EN_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPG_EN_SHIFT)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPG_EN_RANGE                   26:26
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPG_EN_WOFFSET                 0x0
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPG_EN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPG_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPG_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPG_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPG_EN_DISABLE                 _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPG_EN_ENABLE                  _MK_ENUM_CONST(1)
+
+// Enable COMPOUTB output
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPB_EN_SHIFT                   _MK_SHIFT_CONST(27)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPB_EN_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPB_EN_SHIFT)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPB_EN_RANGE                   27:27
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPB_EN_WOFFSET                 0x0
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPB_EN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPB_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPB_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPB_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPB_EN_DISABLE                 _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPB_EN_ENABLE                  _MK_ENUM_CONST(1)
+
+// Indicate load status
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_PLUG_OK_SHIFT                    _MK_SHIFT_CONST(28)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_PLUG_OK_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_TVDACCNTL_0_DAC_PLUG_OK_SHIFT)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_PLUG_OK_RANGE                    28:28
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_PLUG_OK_WOFFSET                  0x0
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_PLUG_OK_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_PLUG_OK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_PLUG_OK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_PLUG_OK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_PLUG_OK_UNLOADED                 _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_PLUG_OK_LOADED                   _MK_ENUM_CONST(1)
+
+
+// Register APB_MISC_ASYNC_TVDACSTATUS_0  
+#define APB_MISC_ASYNC_TVDACSTATUS_0                    _MK_ADDR_CONST(0x440)
+#define APB_MISC_ASYNC_TVDACSTATUS_0_WORD_COUNT                         0x1
+#define APB_MISC_ASYNC_TVDACSTATUS_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACSTATUS_0_RESET_MASK                         _MK_MASK_CONST(0x7)
+#define APB_MISC_ASYNC_TVDACSTATUS_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACSTATUS_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACSTATUS_0_READ_MASK                  _MK_MASK_CONST(0x7)
+#define APB_MISC_ASYNC_TVDACSTATUS_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
+// Channel R comparator output for auto-detect
+// 0 = COMPINR > threshold
+// 1 = COMPINR < threshold, or when POWERDOWN==1
+// comparison threshold = 0.325V
+#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTR_SHIFT                 _MK_SHIFT_CONST(0)
+#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTR_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTR_SHIFT)
+#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTR_RANGE                 0:0
+#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTR_WOFFSET                       0x0
+#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTR_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Channel G comparator output for auto-detect
+// 0 = COMPING > threshold
+// 1 = COMPING < threshold, or when POWERDOWN==1
+// comparison threshold = 0.325V
+#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTG_SHIFT                 _MK_SHIFT_CONST(1)
+#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTG_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTG_SHIFT)
+#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTG_RANGE                 1:1
+#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTG_WOFFSET                       0x0
+#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTG_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTG_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTG_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTG_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Channel B comparator output for auto-detect
+// 0 = COMPINB > threshold
+// 1 = COMPINB < threshold, or when POWERDOWN==1
+// comparison threshold = 0.325V
+#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTB_SHIFT                 _MK_SHIFT_CONST(2)
+#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTB_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTB_SHIFT)
+#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTB_RANGE                 2:2
+#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTB_WOFFSET                       0x0
+#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTB_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTB_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTB_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTB_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_ASYNC_TVDACDINCONFIG_0  
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0                 _MK_ADDR_CONST(0x444)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_WORD_COUNT                      0x1
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_RESET_VAL                       _MK_MASK_CONST(0x2)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_RESET_MASK                      _MK_MASK_CONST(0xffffd37)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_READ_MASK                       _MK_MASK_CONST(0xffffd37)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_WRITE_MASK                      _MK_MASK_CONST(0xffffd37)
+// Data Input FIFO threshold
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_FIFO_TH_SHIFT                       _MK_SHIFT_CONST(0)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_FIFO_TH_FIELD                       (_MK_MASK_CONST(0x7) << APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_FIFO_TH_SHIFT)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_FIFO_TH_RANGE                       2:0
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_FIFO_TH_WOFFSET                     0x0
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_FIFO_TH_DEFAULT                     _MK_MASK_CONST(0x2)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_FIFO_TH_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_FIFO_TH_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_FIFO_TH_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// INPUT source for TVDAC
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_SOURCE_SHIFT                        _MK_SHIFT_CONST(4)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_SOURCE_FIELD                        (_MK_MASK_CONST(0x3) << APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_SOURCE_SHIFT)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_SOURCE_RANGE                        5:4
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_SOURCE_WOFFSET                      0x0
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_SOURCE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_SOURCE_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_SOURCE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_SOURCE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_SOURCE_TVDAC_OFF                    _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_SOURCE_TVO                  _MK_ENUM_CONST(1)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_SOURCE_DISPLAY                      _MK_ENUM_CONST(2)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_SOURCE_DISPLAYB                     _MK_ENUM_CONST(3)
+
+// Override DAC DIN inputs
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_DIN_ORIDE_EN_SHIFT                  _MK_SHIFT_CONST(8)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_DIN_ORIDE_EN_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_DIN_ORIDE_EN_SHIFT)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_DIN_ORIDE_EN_RANGE                  8:8
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_DIN_ORIDE_EN_WOFFSET                        0x0
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_DIN_ORIDE_EN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_DIN_ORIDE_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_DIN_ORIDE_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_DIN_ORIDE_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_DIN_ORIDE_EN_DISABLE                        _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_DIN_ORIDE_EN_ENABLE                 _MK_ENUM_CONST(1)
+
+// DIN override
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_DIN_ORIDE_SHIFT                     _MK_SHIFT_CONST(10)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_DIN_ORIDE_FIELD                     (_MK_MASK_CONST(0x3ff) << APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_DIN_ORIDE_SHIFT)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_DIN_ORIDE_RANGE                     19:10
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_DIN_ORIDE_WOFFSET                   0x0
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_DIN_ORIDE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_DIN_ORIDE_DEFAULT_MASK                      _MK_MASK_CONST(0x3ff)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_DIN_ORIDE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_DIN_ORIDE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// AMPIN
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_AMPIN_SHIFT                 _MK_SHIFT_CONST(20)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_AMPIN_FIELD                 (_MK_MASK_CONST(0xff) << APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_AMPIN_SHIFT)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_AMPIN_RANGE                 27:20
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_AMPIN_WOFFSET                       0x0
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_AMPIN_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_AMPIN_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_AMPIN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_AMPIN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_ASYNC_INT_STATUS_0  // Interrupt Status
+//  This reflects status of all pending
+//  interrupts which is valid as long as
+//  the interrupt is not cleared even if the
+//  interrupt is masked. A pending interrupt
+//  can be cleared by writing a '1' to this
+//  the corresponding interrupt status bit
+//  in this register.
+//        0       rt  HGP0_INT_STATUS          // HGP0 Interrupt Status
+//                                             //  (this is cleared on write)
+//                                             //   0= interrupt not pending
+//                                             //   1= interrupt pending
+//        1       rt  HGP1_INT_STATUS          // HGP1 Interrupt Status
+//                                             //  (this is cleared on write)
+//                                             //   0= interrupt not pending
+//                                            //   1= interrupt pending
+//      2       rt  HGP2_INT_STATUS          // HGP2 Interrupt Status
+//                                          //  (this is cleared on write)
+//                                           //   0= interrupt not pending
+//                                           //   1= interrupt pending
+//      4       rt  HGP4_INT_STATUS          // HGP4 Interrupt Status
+//                                           //  (this is cleared on write)
+//                                           //   0= interrupt not pending
+//                                           //   1= interrupt pending
+//      5       rt  HGP5_INT_STATUS          // HGP5 Interrupt Status
+//                                           //  (this is cleared on write)
+//                                           //   0= interrupt not pending
+//                                           //   1= interrupt pending
+//      6       rt  HGP6_INT_STATUS          // HGP6 Interrupt Status
+//                                           //  (this is cleared on write)
+//                                           //   0= interrupt not pending
+//                                           //   1= interrupt pending
+#define APB_MISC_ASYNC_INT_STATUS_0                     _MK_ADDR_CONST(0x448)
+#define APB_MISC_ASYNC_INT_STATUS_0_WORD_COUNT                  0x1
+#define APB_MISC_ASYNC_INT_STATUS_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_STATUS_0_RESET_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_STATUS_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_STATUS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_STATUS_0_READ_MASK                   _MK_MASK_CONST(0x1f80)
+#define APB_MISC_ASYNC_INT_STATUS_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+// HGP7 Interrupt Status
+//  (this is cleared on write)
+//   0= interrupt not pending
+//   1= interrupt pending
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP7_INT_STATUS_SHIFT                       _MK_SHIFT_CONST(7)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP7_INT_STATUS_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_STATUS_0_HGP7_INT_STATUS_SHIFT)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP7_INT_STATUS_RANGE                       7:7
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP7_INT_STATUS_WOFFSET                     0x0
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP7_INT_STATUS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP7_INT_STATUS_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP7_INT_STATUS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP7_INT_STATUS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// HGP8 Interrupt Status
+//  (this is cleared on write)
+//   0= interrupt not pending
+//   1= interrupt pending
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP8_INT_STATUS_SHIFT                       _MK_SHIFT_CONST(8)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP8_INT_STATUS_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_STATUS_0_HGP8_INT_STATUS_SHIFT)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP8_INT_STATUS_RANGE                       8:8
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP8_INT_STATUS_WOFFSET                     0x0
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP8_INT_STATUS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP8_INT_STATUS_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP8_INT_STATUS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP8_INT_STATUS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// HGP9 Interrupt Status
+//  (this is cleared on write)
+//   0= interrupt not pending
+//   1= interrupt pending
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP9_INT_STATUS_SHIFT                       _MK_SHIFT_CONST(9)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP9_INT_STATUS_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_STATUS_0_HGP9_INT_STATUS_SHIFT)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP9_INT_STATUS_RANGE                       9:9
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP9_INT_STATUS_WOFFSET                     0x0
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP9_INT_STATUS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP9_INT_STATUS_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP9_INT_STATUS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP9_INT_STATUS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// HGP10 Interrupt Status
+//  (this is cleared on write)
+//   0= interrupt not pending
+//   1= interrupt pending
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP10_INT_STATUS_SHIFT                      _MK_SHIFT_CONST(10)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP10_INT_STATUS_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_STATUS_0_HGP10_INT_STATUS_SHIFT)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP10_INT_STATUS_RANGE                      10:10
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP10_INT_STATUS_WOFFSET                    0x0
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP10_INT_STATUS_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP10_INT_STATUS_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP10_INT_STATUS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP10_INT_STATUS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// HGP11 Interrupt Status
+//  (this is cleared on write)
+//   0= interrupt not pending
+//   1= interrupt pending
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP11_INT_STATUS_SHIFT                      _MK_SHIFT_CONST(11)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP11_INT_STATUS_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_STATUS_0_HGP11_INT_STATUS_SHIFT)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP11_INT_STATUS_RANGE                      11:11
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP11_INT_STATUS_WOFFSET                    0x0
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP11_INT_STATUS_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP11_INT_STATUS_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP11_INT_STATUS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP11_INT_STATUS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// HGP12 Interrupt Status
+//  (this is cleared on write)
+//   0= interrupt not pending
+//   1= interrupt pending
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP12_INT_STATUS_SHIFT                      _MK_SHIFT_CONST(12)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP12_INT_STATUS_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_STATUS_0_HGP12_INT_STATUS_SHIFT)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP12_INT_STATUS_RANGE                      12:12
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP12_INT_STATUS_WOFFSET                    0x0
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP12_INT_STATUS_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP12_INT_STATUS_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP12_INT_STATUS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP12_INT_STATUS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_ASYNC_INT_MASK_0  // Interrupt Mask
+// Setting bits in this register masked the
+//  corresponding interrupt but does not
+//  clear a pending interrupt and does not
+//  prevent a pending interrupt to be generated.
+//  Masking an interrupt also does not clear
+//  a pending interrupt status and does not
+//  a pending interrupt status to be generated.
+//      0       rw  HGP0_INT_MASK  i=0x0     // HGP0 Interrupt Mask
+//          enum ( MASKED, NOTMASKED )       //   0= interrupt masked
+//                                           //   1= interrupt not masked
+//      1       rw  HGP1_INT_MASK  i=0x0     // HGP1 Interrupt Mask
+//          enum ( MASKED, NOTMASKED )       //   0= interrupt masked
+//                                           //   1= interrupt not masked
+//      2       rw  HGP2_INT_MASK  i=0x0     // HGP2 Interrupt Mask
+//          enum ( MASKED, NOTMASKED )       //   0= interrupt masked
+//                                           //   1= interrupt not masked
+//      4       rw  HGP4_INT_MASK  i=0x0     // HGP4 Interrupt Mask
+//          enum ( MASKED, NOTMASKED )       //   0= interrupt masked
+//                                           //   1= interrupt not masked
+//      5       rw  HGP5_INT_MASK  i=0x0     // HGP5 Interrupt Mask
+//          enum ( MASKED, NOTMASKED )       //   0= interrupt masked
+//                                           //   1= interrupt not masked
+//      6       rw  HGP6_INT_MASK  i=0x0     // HGP6 Interrupt Mask
+//          enum ( MASKED, NOTMASKED )       //   0= interrupt masked
+//                                           //   1= interrupt not masked
+#define APB_MISC_ASYNC_INT_MASK_0                       _MK_ADDR_CONST(0x44c)
+#define APB_MISC_ASYNC_INT_MASK_0_WORD_COUNT                    0x1
+#define APB_MISC_ASYNC_INT_MASK_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_MASK_0_RESET_MASK                    _MK_MASK_CONST(0x1f80)
+#define APB_MISC_ASYNC_INT_MASK_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_MASK_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_MASK_0_READ_MASK                     _MK_MASK_CONST(0x1f80)
+#define APB_MISC_ASYNC_INT_MASK_0_WRITE_MASK                    _MK_MASK_CONST(0x1f80)
+// HGP7 Interrupt Mask   0= interrupt masked
+//   1= interrupt not masked
+#define APB_MISC_ASYNC_INT_MASK_0_HGP7_INT_MASK_SHIFT                   _MK_SHIFT_CONST(7)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP7_INT_MASK_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_MASK_0_HGP7_INT_MASK_SHIFT)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP7_INT_MASK_RANGE                   7:7
+#define APB_MISC_ASYNC_INT_MASK_0_HGP7_INT_MASK_WOFFSET                 0x0
+#define APB_MISC_ASYNC_INT_MASK_0_HGP7_INT_MASK_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP7_INT_MASK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP7_INT_MASK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP7_INT_MASK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP7_INT_MASK_MASKED                  _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP7_INT_MASK_NOTMASKED                       _MK_ENUM_CONST(1)
+
+// HGP8 Interrupt Mask   0= interrupt masked
+//   1= interrupt not masked
+#define APB_MISC_ASYNC_INT_MASK_0_HGP8_INT_MASK_SHIFT                   _MK_SHIFT_CONST(8)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP8_INT_MASK_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_MASK_0_HGP8_INT_MASK_SHIFT)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP8_INT_MASK_RANGE                   8:8
+#define APB_MISC_ASYNC_INT_MASK_0_HGP8_INT_MASK_WOFFSET                 0x0
+#define APB_MISC_ASYNC_INT_MASK_0_HGP8_INT_MASK_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP8_INT_MASK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP8_INT_MASK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP8_INT_MASK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP8_INT_MASK_MASKED                  _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP8_INT_MASK_NOTMASKED                       _MK_ENUM_CONST(1)
+
+// HGP9 Interrupt Mask   0= interrupt masked
+//   1= interrupt not masked
+#define APB_MISC_ASYNC_INT_MASK_0_HGP9_INT_MASK_SHIFT                   _MK_SHIFT_CONST(9)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP9_INT_MASK_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_MASK_0_HGP9_INT_MASK_SHIFT)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP9_INT_MASK_RANGE                   9:9
+#define APB_MISC_ASYNC_INT_MASK_0_HGP9_INT_MASK_WOFFSET                 0x0
+#define APB_MISC_ASYNC_INT_MASK_0_HGP9_INT_MASK_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP9_INT_MASK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP9_INT_MASK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP9_INT_MASK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP9_INT_MASK_MASKED                  _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP9_INT_MASK_NOTMASKED                       _MK_ENUM_CONST(1)
+
+// HGP10 Interrupt Mask   0= interrupt masked
+//   1= interrupt not masked
+#define APB_MISC_ASYNC_INT_MASK_0_HGP10_INT_MASK_SHIFT                  _MK_SHIFT_CONST(10)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP10_INT_MASK_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_MASK_0_HGP10_INT_MASK_SHIFT)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP10_INT_MASK_RANGE                  10:10
+#define APB_MISC_ASYNC_INT_MASK_0_HGP10_INT_MASK_WOFFSET                        0x0
+#define APB_MISC_ASYNC_INT_MASK_0_HGP10_INT_MASK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP10_INT_MASK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP10_INT_MASK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP10_INT_MASK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP10_INT_MASK_MASKED                 _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP10_INT_MASK_NOTMASKED                      _MK_ENUM_CONST(1)
+
+// HGP11 Interrupt Mask   0= interrupt masked
+//   1= interrupt not masked
+#define APB_MISC_ASYNC_INT_MASK_0_HGP11_INT_MASK_SHIFT                  _MK_SHIFT_CONST(11)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP11_INT_MASK_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_MASK_0_HGP11_INT_MASK_SHIFT)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP11_INT_MASK_RANGE                  11:11
+#define APB_MISC_ASYNC_INT_MASK_0_HGP11_INT_MASK_WOFFSET                        0x0
+#define APB_MISC_ASYNC_INT_MASK_0_HGP11_INT_MASK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP11_INT_MASK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP11_INT_MASK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP11_INT_MASK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP11_INT_MASK_MASKED                 _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP11_INT_MASK_NOTMASKED                      _MK_ENUM_CONST(1)
+
+// HGP12 Interrupt Mask   0= interrupt masked
+//   1= interrupt not masked
+#define APB_MISC_ASYNC_INT_MASK_0_HGP12_INT_MASK_SHIFT                  _MK_SHIFT_CONST(12)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP12_INT_MASK_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_MASK_0_HGP12_INT_MASK_SHIFT)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP12_INT_MASK_RANGE                  12:12
+#define APB_MISC_ASYNC_INT_MASK_0_HGP12_INT_MASK_WOFFSET                        0x0
+#define APB_MISC_ASYNC_INT_MASK_0_HGP12_INT_MASK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP12_INT_MASK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP12_INT_MASK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP12_INT_MASK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP12_INT_MASK_MASKED                 _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP12_INT_MASK_NOTMASKED                      _MK_ENUM_CONST(1)
+
+
+// Register APB_MISC_ASYNC_INT_POLARITY_0  // Interrupt Polarity
+//  These bits specify whether a pending interrupt 
+//  is generated on falling edge or on rising edge 
+//  of the corresponding input signal/event.
+//        0       rw  HGP0_INT_POLARITY  i=0x0  // HGP0 Interrupt Polarity
+//      enum ( LOW, HIGH )                    //   0= falling edge interrupt
+//                                            //   1= rising edge interrupt
+//      1       rw  HGP1_INT_POLARITY  i=0x0  // HGP1 Interrupt Polarity
+//      enum ( LOW, HIGH )                    //   0= falling edge interrupt
+//                                            //   1= rising edge interrupt
+//      2       rw  HGP2_INT_POLARITY  i=0x0  // HGP2 Interrupt Polarity
+//      enum ( LOW, HIGH )                    //   0= falling edge interrupt
+//                                            //   1= rising edge interrupt
+//      4       rw  HGP4_INT_POLARITY  i=0x0  // HGP4 Interrupt Polarity
+//      enum ( LOW, HIGH )                    //   0= falling edge interrupt
+//                                            //   1= rising edge interrupt
+//      5       rw  HGP5_INT_POLARITY  i=0x0  // HGP5 Interrupt Polarity
+//      enum ( LOW, HIGH )                    //   0= falling edge interrupt
+//                                            //   1= rising edge interrupt
+//      6       rw  HGP6_INT_POLARITY  i=0x0  // HGP6 Interrupt Polarity
+//      enum ( LOW, HIGH )                    //   0= falling edge interrupt
+//                                            //   1= rising edge interrupt
+#define APB_MISC_ASYNC_INT_POLARITY_0                   _MK_ADDR_CONST(0x450)
+#define APB_MISC_ASYNC_INT_POLARITY_0_WORD_COUNT                        0x1
+#define APB_MISC_ASYNC_INT_POLARITY_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_RESET_MASK                        _MK_MASK_CONST(0x1f80)
+#define APB_MISC_ASYNC_INT_POLARITY_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_READ_MASK                         _MK_MASK_CONST(0x1f80)
+#define APB_MISC_ASYNC_INT_POLARITY_0_WRITE_MASK                        _MK_MASK_CONST(0x1f80)
+// HGP7 Interrupt Polarity   0= falling edge interrupt
+//   1= rising edge interrupt
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP7_INT_POLARITY_SHIFT                   _MK_SHIFT_CONST(7)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP7_INT_POLARITY_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_POLARITY_0_HGP7_INT_POLARITY_SHIFT)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP7_INT_POLARITY_RANGE                   7:7
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP7_INT_POLARITY_WOFFSET                 0x0
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP7_INT_POLARITY_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP7_INT_POLARITY_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP7_INT_POLARITY_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP7_INT_POLARITY_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP7_INT_POLARITY_LOW                     _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP7_INT_POLARITY_HIGH                    _MK_ENUM_CONST(1)
+
+// HGP8 Interrupt Polarity   0= falling edge interrupt
+//   1= rising edge interrupt
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP8_INT_POLARITY_SHIFT                   _MK_SHIFT_CONST(8)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP8_INT_POLARITY_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_POLARITY_0_HGP8_INT_POLARITY_SHIFT)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP8_INT_POLARITY_RANGE                   8:8
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP8_INT_POLARITY_WOFFSET                 0x0
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP8_INT_POLARITY_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP8_INT_POLARITY_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP8_INT_POLARITY_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP8_INT_POLARITY_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP8_INT_POLARITY_LOW                     _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP8_INT_POLARITY_HIGH                    _MK_ENUM_CONST(1)
+
+// HGP9 Interrupt Polarity   0= falling edge interrupt
+//   1= rising edge interrupt
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP9_INT_POLARITY_SHIFT                   _MK_SHIFT_CONST(9)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP9_INT_POLARITY_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_POLARITY_0_HGP9_INT_POLARITY_SHIFT)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP9_INT_POLARITY_RANGE                   9:9
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP9_INT_POLARITY_WOFFSET                 0x0
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP9_INT_POLARITY_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP9_INT_POLARITY_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP9_INT_POLARITY_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP9_INT_POLARITY_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP9_INT_POLARITY_LOW                     _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP9_INT_POLARITY_HIGH                    _MK_ENUM_CONST(1)
+
+// HGP10 Interrupt Polarity   0= falling edge interrupt
+//   1= rising edge interrupt
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP10_INT_POLARITY_SHIFT                  _MK_SHIFT_CONST(10)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP10_INT_POLARITY_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_POLARITY_0_HGP10_INT_POLARITY_SHIFT)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP10_INT_POLARITY_RANGE                  10:10
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP10_INT_POLARITY_WOFFSET                        0x0
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP10_INT_POLARITY_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP10_INT_POLARITY_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP10_INT_POLARITY_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP10_INT_POLARITY_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP10_INT_POLARITY_LOW                    _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP10_INT_POLARITY_HIGH                   _MK_ENUM_CONST(1)
+
+// HGP11 Interrupt Polarity   0= falling edge interrupt
+//   1= rising edge interrupt
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP11_INT_POLARITY_SHIFT                  _MK_SHIFT_CONST(11)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP11_INT_POLARITY_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_POLARITY_0_HGP11_INT_POLARITY_SHIFT)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP11_INT_POLARITY_RANGE                  11:11
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP11_INT_POLARITY_WOFFSET                        0x0
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP11_INT_POLARITY_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP11_INT_POLARITY_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP11_INT_POLARITY_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP11_INT_POLARITY_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP11_INT_POLARITY_LOW                    _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP11_INT_POLARITY_HIGH                   _MK_ENUM_CONST(1)
+
+// HGP12 Interrupt Polarity   0= falling edge interrupt
+//   1= rising edge interrupt
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP12_INT_POLARITY_SHIFT                  _MK_SHIFT_CONST(12)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP12_INT_POLARITY_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_POLARITY_0_HGP12_INT_POLARITY_SHIFT)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP12_INT_POLARITY_RANGE                  12:12
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP12_INT_POLARITY_WOFFSET                        0x0
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP12_INT_POLARITY_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP12_INT_POLARITY_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP12_INT_POLARITY_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP12_INT_POLARITY_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP12_INT_POLARITY_LOW                    _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP12_INT_POLARITY_HIGH                   _MK_ENUM_CONST(1)
+
+
+// Register APB_MISC_ASYNC_INT_TYPE_SELECT_0  // Interrupt Type
+//  These bits specify whether an interrupt 
+//  is generated on an edge of a level type.
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0                        _MK_ADDR_CONST(0x454)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_WORD_COUNT                     0x1
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_RESET_MASK                     _MK_MASK_CONST(0x1f80)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_READ_MASK                      _MK_MASK_CONST(0x1f80)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_WRITE_MASK                     _MK_MASK_CONST(0x1f80)
+// HGP7 Interrupt Type   0= Edge type
+//   1= Level type
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP7_INT_TYPE_SHIFT                    _MK_SHIFT_CONST(7)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP7_INT_TYPE_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP7_INT_TYPE_SHIFT)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP7_INT_TYPE_RANGE                    7:7
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP7_INT_TYPE_WOFFSET                  0x0
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP7_INT_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP7_INT_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP7_INT_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP7_INT_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP7_INT_TYPE_EDGE                     _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP7_INT_TYPE_LEVEL                    _MK_ENUM_CONST(1)
+
+// HGP8 Interrupt Polarity   0= Edge type
+//   1= Level type
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP8_INT_TYPE_SHIFT                    _MK_SHIFT_CONST(8)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP8_INT_TYPE_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP8_INT_TYPE_SHIFT)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP8_INT_TYPE_RANGE                    8:8
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP8_INT_TYPE_WOFFSET                  0x0
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP8_INT_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP8_INT_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP8_INT_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP8_INT_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP8_INT_TYPE_EDGE                     _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP8_INT_TYPE_LEVEL                    _MK_ENUM_CONST(1)
+
+// HGP9 Interrupt Polarity   0= Edge type
+//   1= Level type
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP9_INT_TYPE_SHIFT                    _MK_SHIFT_CONST(9)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP9_INT_TYPE_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP9_INT_TYPE_SHIFT)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP9_INT_TYPE_RANGE                    9:9
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP9_INT_TYPE_WOFFSET                  0x0
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP9_INT_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP9_INT_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP9_INT_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP9_INT_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP9_INT_TYPE_EDGE                     _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP9_INT_TYPE_LEVEL                    _MK_ENUM_CONST(1)
+
+// HGP10 Interrupt Polarity   0= Edge type
+//   1= Level type
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP10_INT_TYPE_SHIFT                   _MK_SHIFT_CONST(10)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP10_INT_TYPE_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP10_INT_TYPE_SHIFT)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP10_INT_TYPE_RANGE                   10:10
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP10_INT_TYPE_WOFFSET                 0x0
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP10_INT_TYPE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP10_INT_TYPE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP10_INT_TYPE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP10_INT_TYPE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP10_INT_TYPE_EDGE                    _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP10_INT_TYPE_LEVEL                   _MK_ENUM_CONST(1)
+
+// HGP11 Interrupt Polarity   0= Edge type
+//   1= Level type
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP11_INT_TYPE_SHIFT                   _MK_SHIFT_CONST(11)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP11_INT_TYPE_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP11_INT_TYPE_SHIFT)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP11_INT_TYPE_RANGE                   11:11
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP11_INT_TYPE_WOFFSET                 0x0
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP11_INT_TYPE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP11_INT_TYPE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP11_INT_TYPE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP11_INT_TYPE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP11_INT_TYPE_EDGE                    _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP11_INT_TYPE_LEVEL                   _MK_ENUM_CONST(1)
+
+// HGP12 Interrupt Polarity   0= Edge type
+//   1= Level type
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP12_INT_TYPE_SHIFT                   _MK_SHIFT_CONST(12)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP12_INT_TYPE_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP12_INT_TYPE_SHIFT)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP12_INT_TYPE_RANGE                   12:12
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP12_INT_TYPE_WOFFSET                 0x0
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP12_INT_TYPE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP12_INT_TYPE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP12_INT_TYPE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP12_INT_TYPE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP12_INT_TYPE_EDGE                    _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP12_INT_TYPE_LEVEL                   _MK_ENUM_CONST(1)
+
+
+// Register APB_MISC_GP_MODEREG_0  
+#define APB_MISC_GP_MODEREG_0                   _MK_ADDR_CONST(0x800)
+#define APB_MISC_GP_MODEREG_0_WORD_COUNT                        0x1
+#define APB_MISC_GP_MODEREG_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_MODEREG_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_MODEREG_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_MODEREG_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_MODEREG_0_READ_MASK                         _MK_MASK_CONST(0x301)
+#define APB_MISC_GP_MODEREG_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+// Standby pad input 1 = STANDBYN is    asserted (low  voltage),                   0 = STANDBYN is desasserted (high voltage)
+#define APB_MISC_GP_MODEREG_0_STANDBY_IE_SHIFT                  _MK_SHIFT_CONST(0)
+#define APB_MISC_GP_MODEREG_0_STANDBY_IE_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_GP_MODEREG_0_STANDBY_IE_SHIFT)
+#define APB_MISC_GP_MODEREG_0_STANDBY_IE_RANGE                  0:0
+#define APB_MISC_GP_MODEREG_0_STANDBY_IE_WOFFSET                        0x0
+#define APB_MISC_GP_MODEREG_0_STANDBY_IE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_MODEREG_0_STANDBY_IE_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_MODEREG_0_STANDBY_IE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_MODEREG_0_STANDBY_IE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_MODEREG_0_STANDBY_IE_DEASSERTED                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_MODEREG_0_STANDBY_IE_ASSERTED                       _MK_ENUM_CONST(1)
+
+// LP-DDR Strap option bit 0.
+#define APB_MISC_GP_MODEREG_0_LPDDR_STRAP0_SHIFT                        _MK_SHIFT_CONST(8)
+#define APB_MISC_GP_MODEREG_0_LPDDR_STRAP0_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_MODEREG_0_LPDDR_STRAP0_SHIFT)
+#define APB_MISC_GP_MODEREG_0_LPDDR_STRAP0_RANGE                        8:8
+#define APB_MISC_GP_MODEREG_0_LPDDR_STRAP0_WOFFSET                      0x0
+#define APB_MISC_GP_MODEREG_0_LPDDR_STRAP0_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_MODEREG_0_LPDDR_STRAP0_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_MODEREG_0_LPDDR_STRAP0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_MODEREG_0_LPDDR_STRAP0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// LP-DDR Strap option bit 1.
+#define APB_MISC_GP_MODEREG_0_LPDDR_STRAP1_SHIFT                        _MK_SHIFT_CONST(9)
+#define APB_MISC_GP_MODEREG_0_LPDDR_STRAP1_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_MODEREG_0_LPDDR_STRAP1_SHIFT)
+#define APB_MISC_GP_MODEREG_0_LPDDR_STRAP1_RANGE                        9:9
+#define APB_MISC_GP_MODEREG_0_LPDDR_STRAP1_WOFFSET                      0x0
+#define APB_MISC_GP_MODEREG_0_LPDDR_STRAP1_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_MODEREG_0_LPDDR_STRAP1_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_MODEREG_0_LPDDR_STRAP1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_MODEREG_0_LPDDR_STRAP1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_HIDREV_0  
+#define APB_MISC_GP_HIDREV_0                    _MK_ADDR_CONST(0x804)
+#define APB_MISC_GP_HIDREV_0_WORD_COUNT                         0x1
+#define APB_MISC_GP_HIDREV_0_RESET_VAL                  _MK_MASK_CONST(0x21517)
+#define APB_MISC_GP_HIDREV_0_RESET_MASK                         _MK_MASK_CONST(0xfffff)
+#define APB_MISC_GP_HIDREV_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_HIDREV_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_HIDREV_0_READ_MASK                  _MK_MASK_CONST(0xfffff)
+#define APB_MISC_GP_HIDREV_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
+// Chip ID family register. There maybe a new HIDFAM code
+// added for MG20 products, this is still being descided.
+#define APB_MISC_GP_HIDREV_0_HIDFAM_SHIFT                       _MK_SHIFT_CONST(0)
+#define APB_MISC_GP_HIDREV_0_HIDFAM_FIELD                       (_MK_MASK_CONST(0xf) << APB_MISC_GP_HIDREV_0_HIDFAM_SHIFT)
+#define APB_MISC_GP_HIDREV_0_HIDFAM_RANGE                       3:0
+#define APB_MISC_GP_HIDREV_0_HIDFAM_WOFFSET                     0x0
+#define APB_MISC_GP_HIDREV_0_HIDFAM_DEFAULT                     _MK_MASK_CONST(0x7)
+#define APB_MISC_GP_HIDREV_0_HIDFAM_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define APB_MISC_GP_HIDREV_0_HIDFAM_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_HIDREV_0_HIDFAM_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_HIDREV_0_HIDFAM_GPU                 _MK_ENUM_CONST(0)
+#define APB_MISC_GP_HIDREV_0_HIDFAM_HANDHELD                    _MK_ENUM_CONST(1)
+#define APB_MISC_GP_HIDREV_0_HIDFAM_BR_CHIPS                    _MK_ENUM_CONST(2)
+#define APB_MISC_GP_HIDREV_0_HIDFAM_CRUSH                       _MK_ENUM_CONST(3)
+#define APB_MISC_GP_HIDREV_0_HIDFAM_MCP                 _MK_ENUM_CONST(4)
+#define APB_MISC_GP_HIDREV_0_HIDFAM_CK                  _MK_ENUM_CONST(5)
+#define APB_MISC_GP_HIDREV_0_HIDFAM_VAIO                        _MK_ENUM_CONST(6)
+#define APB_MISC_GP_HIDREV_0_HIDFAM_HANDHELD_SOC                        _MK_ENUM_CONST(7)
+
+// Chip ID major revision (0: Emulation, 1-15: Silicon)
+#define APB_MISC_GP_HIDREV_0_MAJORREV_SHIFT                     _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_HIDREV_0_MAJORREV_FIELD                     (_MK_MASK_CONST(0xf) << APB_MISC_GP_HIDREV_0_MAJORREV_SHIFT)
+#define APB_MISC_GP_HIDREV_0_MAJORREV_RANGE                     7:4
+#define APB_MISC_GP_HIDREV_0_MAJORREV_WOFFSET                   0x0
+#define APB_MISC_GP_HIDREV_0_MAJORREV_DEFAULT                   _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_HIDREV_0_MAJORREV_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define APB_MISC_GP_HIDREV_0_MAJORREV_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_HIDREV_0_MAJORREV_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_HIDREV_0_MAJORREV_EMULATION                 _MK_ENUM_CONST(0)
+#define APB_MISC_GP_HIDREV_0_MAJORREV_A01                       _MK_ENUM_CONST(1)
+
+// Chip ID
+#define APB_MISC_GP_HIDREV_0_CHIPID_SHIFT                       _MK_SHIFT_CONST(8)
+#define APB_MISC_GP_HIDREV_0_CHIPID_FIELD                       (_MK_MASK_CONST(0xff) << APB_MISC_GP_HIDREV_0_CHIPID_SHIFT)
+#define APB_MISC_GP_HIDREV_0_CHIPID_RANGE                       15:8
+#define APB_MISC_GP_HIDREV_0_CHIPID_WOFFSET                     0x0
+#define APB_MISC_GP_HIDREV_0_CHIPID_DEFAULT                     _MK_MASK_CONST(0x15)
+#define APB_MISC_GP_HIDREV_0_CHIPID_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define APB_MISC_GP_HIDREV_0_CHIPID_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_HIDREV_0_CHIPID_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Chip ID minor revision (IF MAJORREV==0(Emulation) THEN  0: QT, 1:E388 FPGA)
+#define APB_MISC_GP_HIDREV_0_MINORREV_SHIFT                     _MK_SHIFT_CONST(16)
+#define APB_MISC_GP_HIDREV_0_MINORREV_FIELD                     (_MK_MASK_CONST(0xf) << APB_MISC_GP_HIDREV_0_MINORREV_SHIFT)
+#define APB_MISC_GP_HIDREV_0_MINORREV_RANGE                     19:16
+#define APB_MISC_GP_HIDREV_0_MINORREV_WOFFSET                   0x0
+#define APB_MISC_GP_HIDREV_0_MINORREV_DEFAULT                   _MK_MASK_CONST(0x2)
+#define APB_MISC_GP_HIDREV_0_MINORREV_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define APB_MISC_GP_HIDREV_0_MINORREV_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_HIDREV_0_MINORREV_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Reserved address 2056 [0x808] 
+
+// Reserved address 2060 [0x80c] 
+
+// Register APB_MISC_GP_ASDBGREG_0  
+#define APB_MISC_GP_ASDBGREG_0                  _MK_ADDR_CONST(0x810)
+#define APB_MISC_GP_ASDBGREG_0_WORD_COUNT                       0x1
+#define APB_MISC_GP_ASDBGREG_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_RESET_MASK                       _MK_MASK_CONST(0x3ff0ffdf)
+#define APB_MISC_GP_ASDBGREG_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_READ_MASK                        _MK_MASK_CONST(0x3ff0ffdf)
+#define APB_MISC_GP_ASDBGREG_0_WRITE_MASK                       _MK_MASK_CONST(0x3ff0ffdf)
+// Enables iddq (WARNING: Will functionally kill chip)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_IDDQ_EN_SHIFT                    _MK_SHIFT_CONST(0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_IDDQ_EN_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG_0_CFG2TMC_IDDQ_EN_SHIFT)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_IDDQ_EN_RANGE                    0:0
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_IDDQ_EN_WOFFSET                  0x0
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_IDDQ_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_IDDQ_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_IDDQ_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_IDDQ_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_IDDQ_EN_DISABLE                  _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_IDDQ_EN_ENABLE                   _MK_ENUM_CONST(1)
+
+// Enables pullup
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLUP_EN_SHIFT                  _MK_SHIFT_CONST(1)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLUP_EN_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLUP_EN_SHIFT)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLUP_EN_RANGE                  1:1
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLUP_EN_WOFFSET                        0x0
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLUP_EN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLUP_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLUP_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLUP_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLUP_EN_DISABLE                        _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLUP_EN_ENABLE                 _MK_ENUM_CONST(1)
+
+// Enables pulldown
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLDOWN_EN_SHIFT                        _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLDOWN_EN_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLDOWN_EN_SHIFT)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLDOWN_EN_RANGE                        2:2
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLDOWN_EN_WOFFSET                      0x0
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLDOWN_EN_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLDOWN_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLDOWN_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLDOWN_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLDOWN_EN_DISABLE                      _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLDOWN_EN_ENABLE                       _MK_ENUM_CONST(1)
+
+// Enables debug mode
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_DEBUG_ENABLE_SHIFT                       _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_DEBUG_ENABLE_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG_0_CFG2TMC_DEBUG_ENABLE_SHIFT)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_DEBUG_ENABLE_RANGE                       3:3
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_DEBUG_ENABLE_WOFFSET                     0x0
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_DEBUG_ENABLE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_DEBUG_ENABLE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_DEBUG_ENABLE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_DEBUG_ENABLE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_DEBUG_ENABLE_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_DEBUG_ENABLE_ENABLE                      _MK_ENUM_CONST(1)
+
+// Enables performance monitor mode
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PM_ENABLE_SHIFT                  _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PM_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG_0_CFG2TMC_PM_ENABLE_SHIFT)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PM_ENABLE_RANGE                  4:4
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PM_ENABLE_WOFFSET                        0x0
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PM_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PM_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PM_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PM_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PM_ENABLE_DISABLE                        _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PM_ENABLE_ENABLE                 _MK_ENUM_CONST(1)
+
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_CLKBYP_FUNC_SHIFT                        _MK_SHIFT_CONST(6)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_CLKBYP_FUNC_FIELD                        (_MK_MASK_CONST(0x3) << APB_MISC_GP_ASDBGREG_0_CFG2TMC_CLKBYP_FUNC_SHIFT)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_CLKBYP_FUNC_RANGE                        7:6
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_CLKBYP_FUNC_WOFFSET                      0x0
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_CLKBYP_FUNC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_CLKBYP_FUNC_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_CLKBYP_FUNC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_CLKBYP_FUNC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_CLKBYP_FUNC_DISABLE                      _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_CLKBYP_FUNC_ENABLE                       _MK_ENUM_CONST(1)
+
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T1CLK_SHIFT                        _MK_SHIFT_CONST(8)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T1CLK_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T1CLK_SHIFT)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T1CLK_RANGE                        8:8
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T1CLK_WOFFSET                      0x0
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T1CLK_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T1CLK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T1CLK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T1CLK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T1CLK_DISABLE                      _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T1CLK_ENABLE                       _MK_ENUM_CONST(1)
+
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T2CLK_SHIFT                        _MK_SHIFT_CONST(9)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T2CLK_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T2CLK_SHIFT)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T2CLK_RANGE                        9:9
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T2CLK_WOFFSET                      0x0
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T2CLK_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T2CLK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T2CLK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T2CLK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T2CLK_DISABLE                      _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T2CLK_ENABLE                       _MK_ENUM_CONST(1)
+
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T3CLK_SHIFT                        _MK_SHIFT_CONST(10)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T3CLK_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T3CLK_SHIFT)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T3CLK_RANGE                        10:10
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T3CLK_WOFFSET                      0x0
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T3CLK_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T3CLK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T3CLK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T3CLK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T3CLK_DISABLE                      _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T3CLK_ENABLE                       _MK_ENUM_CONST(1)
+
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T4CLK_SHIFT                        _MK_SHIFT_CONST(11)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T4CLK_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T4CLK_SHIFT)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T4CLK_RANGE                        11:11
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T4CLK_WOFFSET                      0x0
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T4CLK_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T4CLK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T4CLK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T4CLK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T4CLK_DISABLE                      _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T4CLK_ENABLE                       _MK_ENUM_CONST(1)
+
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T5CLK_SHIFT                        _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T5CLK_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T5CLK_SHIFT)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T5CLK_RANGE                        12:12
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T5CLK_WOFFSET                      0x0
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T5CLK_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T5CLK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T5CLK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T5CLK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T5CLK_DISABLE                      _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T5CLK_ENABLE                       _MK_ENUM_CONST(1)
+
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T6CLK_SHIFT                        _MK_SHIFT_CONST(13)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T6CLK_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T6CLK_SHIFT)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T6CLK_RANGE                        13:13
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T6CLK_WOFFSET                      0x0
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T6CLK_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T6CLK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T6CLK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T6CLK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T6CLK_DISABLE                      _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T6CLK_ENABLE                       _MK_ENUM_CONST(1)
+
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T7CLK_SHIFT                        _MK_SHIFT_CONST(14)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T7CLK_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T7CLK_SHIFT)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T7CLK_RANGE                        14:14
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T7CLK_WOFFSET                      0x0
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T7CLK_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T7CLK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T7CLK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T7CLK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T7CLK_DISABLE                      _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T7CLK_ENABLE                       _MK_ENUM_CONST(1)
+
+//  Obsolete previously used with host_pad_macros (jmoskal)
+//16      rw  CFG2TMC_SW_BP_WRNCLK      i=0x0
+//    enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_CLK_DIV_SHIFT                      _MK_SHIFT_CONST(15)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_CLK_DIV_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_CLK_DIV_SHIFT)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_CLK_DIV_RANGE                      15:15
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_CLK_DIV_WOFFSET                    0x0
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_CLK_DIV_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_CLK_DIV_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_CLK_DIV_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_CLK_DIV_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_CLK_DIV_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_CLK_DIV_ENABLE                     _MK_ENUM_CONST(1)
+
+// control timing characteristics for the compiled rams
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_EMAA_SHIFT                   _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_EMAA_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_EMAA_SHIFT)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_EMAA_RANGE                   21:20
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_EMAA_WOFFSET                 0x0
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_EMAA_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_EMAA_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_EMAA_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_EMAA_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_EMAA_DISABLE                 _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_EMAA_ENABLE                  _MK_ENUM_CONST(1)
+
+// control write timing characteristics for the compiled RAMDP
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_DP_SHIFT                        _MK_SHIFT_CONST(22)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_DP_FIELD                        (_MK_MASK_CONST(0x3) << APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_DP_SHIFT)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_DP_RANGE                        23:22
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_DP_WOFFSET                      0x0
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_DP_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_DP_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_DP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_DP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// control write timing characteristics for the compiled RAMPDP
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_PDP_SHIFT                       _MK_SHIFT_CONST(24)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_PDP_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_PDP_SHIFT)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_PDP_RANGE                       25:24
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_PDP_WOFFSET                     0x0
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_PDP_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_PDP_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_PDP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_PDP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// control write timing characteristics for the compiled RAMREG
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_REG_SHIFT                       _MK_SHIFT_CONST(26)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_REG_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_REG_SHIFT)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_REG_RANGE                       27:26
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_REG_WOFFSET                     0x0
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_REG_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_REG_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_REG_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_REG_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// control write timing characteristics for the compiled RAMSP
+// ECO 385781, add reset to RAM_SVOP_SP
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_SP_SHIFT                        _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_SP_FIELD                        (_MK_MASK_CONST(0x3) << APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_SP_SHIFT)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_SP_RANGE                        29:28
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_SP_WOFFSET                      0x0
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_SP_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_SP_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_SP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_SP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_RESERVEREG_0  
+#define APB_MISC_GP_RESERVEREG_0                        _MK_ADDR_CONST(0x814)
+#define APB_MISC_GP_RESERVEREG_0_WORD_COUNT                     0x1
+#define APB_MISC_GP_RESERVEREG_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_RESERVEREG_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_GP_RESERVEREG_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_RESERVEREG_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_RESERVEREG_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_GP_RESERVEREG_0_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE0_SHIFT                     _MK_SHIFT_CONST(0)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE0_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_RESERVEREG_0_ECO_RESERVE0_SHIFT)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE0_RANGE                     0:0
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE0_WOFFSET                   0x0
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE0_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE0_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE1_SHIFT                     _MK_SHIFT_CONST(1)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE1_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_RESERVEREG_0_ECO_RESERVE1_SHIFT)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE1_RANGE                     1:1
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE1_WOFFSET                   0x0
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE1_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE1_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE2_SHIFT                     _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE2_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_RESERVEREG_0_ECO_RESERVE2_SHIFT)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE2_RANGE                     2:2
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE2_WOFFSET                   0x0
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE2_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE2_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE3_SHIFT                     _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE3_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_RESERVEREG_0_ECO_RESERVE3_SHIFT)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE3_RANGE                     3:3
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE3_WOFFSET                   0x0
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE3_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE3_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE3_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE3_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE4_SHIFT                     _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE4_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_RESERVEREG_0_ECO_RESERVE4_SHIFT)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE4_RANGE                     4:4
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE4_WOFFSET                   0x0
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE4_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE4_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE4_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE4_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE5_SHIFT                     _MK_SHIFT_CONST(5)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE5_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_RESERVEREG_0_ECO_RESERVE5_SHIFT)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE5_RANGE                     5:5
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE5_WOFFSET                   0x0
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE5_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE5_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE5_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE5_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE6_SHIFT                     _MK_SHIFT_CONST(6)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE6_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_RESERVEREG_0_ECO_RESERVE6_SHIFT)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE6_RANGE                     6:6
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE6_WOFFSET                   0x0
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE6_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE6_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE6_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE6_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE7_SHIFT                     _MK_SHIFT_CONST(7)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE7_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_RESERVEREG_0_ECO_RESERVE7_SHIFT)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE7_RANGE                     7:7
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE7_WOFFSET                   0x0
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE7_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE7_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE7_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE7_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE_B1_SHIFT                   _MK_SHIFT_CONST(8)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE_B1_FIELD                   (_MK_MASK_CONST(0xff) << APB_MISC_GP_RESERVEREG_0_ECO_RESERVE_B1_SHIFT)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE_B1_RANGE                   15:8
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE_B1_WOFFSET                 0x0
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE_B1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE_B1_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE_B1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE_B1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE_B2_SHIFT                   _MK_SHIFT_CONST(16)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE_B2_FIELD                   (_MK_MASK_CONST(0xff) << APB_MISC_GP_RESERVEREG_0_ECO_RESERVE_B2_SHIFT)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE_B2_RANGE                   23:16
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE_B2_WOFFSET                 0x0
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE_B2_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE_B2_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE_B2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE_B2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE_B3_SHIFT                   _MK_SHIFT_CONST(24)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE_B3_FIELD                   (_MK_MASK_CONST(0xff) << APB_MISC_GP_RESERVEREG_0_ECO_RESERVE_B3_SHIFT)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE_B3_RANGE                   31:24
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE_B3_WOFFSET                 0x0
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE_B3_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE_B3_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE_B3_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE_B3_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_OBSCTRL_0  
+#define APB_MISC_GP_OBSCTRL_0                   _MK_ADDR_CONST(0x818)
+#define APB_MISC_GP_OBSCTRL_0_WORD_COUNT                        0x1
+#define APB_MISC_GP_OBSCTRL_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OBSCTRL_0_RESET_MASK                        _MK_MASK_CONST(0x80ffffff)
+#define APB_MISC_GP_OBSCTRL_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OBSCTRL_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OBSCTRL_0_READ_MASK                         _MK_MASK_CONST(0x80ffffff)
+#define APB_MISC_GP_OBSCTRL_0_WRITE_MASK                        _MK_MASK_CONST(0x80ffffff)
+// Module-level mux select for determining which debug signals to send out
+#define APB_MISC_GP_OBSCTRL_0_OBS_SIG_SEL_SHIFT                 _MK_SHIFT_CONST(0)
+#define APB_MISC_GP_OBSCTRL_0_OBS_SIG_SEL_FIELD                 (_MK_MASK_CONST(0xffff) << APB_MISC_GP_OBSCTRL_0_OBS_SIG_SEL_SHIFT)
+#define APB_MISC_GP_OBSCTRL_0_OBS_SIG_SEL_RANGE                 15:0
+#define APB_MISC_GP_OBSCTRL_0_OBS_SIG_SEL_WOFFSET                       0x0
+#define APB_MISC_GP_OBSCTRL_0_OBS_SIG_SEL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OBSCTRL_0_OBS_SIG_SEL_DEFAULT_MASK                  _MK_MASK_CONST(0xffff)
+#define APB_MISC_GP_OBSCTRL_0_OBS_SIG_SEL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OBSCTRL_0_OBS_SIG_SEL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Observation module select
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_SHIFT                 _MK_SHIFT_CONST(16)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_FIELD                 (_MK_MASK_CONST(0xf) << APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_SHIFT)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_RANGE                 19:16
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_WOFFSET                       0x0
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Observation partition select
+#define APB_MISC_GP_OBSCTRL_0_OBS_PART_SEL_SHIFT                        _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_OBSCTRL_0_OBS_PART_SEL_FIELD                        (_MK_MASK_CONST(0xf) << APB_MISC_GP_OBSCTRL_0_OBS_PART_SEL_SHIFT)
+#define APB_MISC_GP_OBSCTRL_0_OBS_PART_SEL_RANGE                        23:20
+#define APB_MISC_GP_OBSCTRL_0_OBS_PART_SEL_WOFFSET                      0x0
+#define APB_MISC_GP_OBSCTRL_0_OBS_PART_SEL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OBSCTRL_0_OBS_PART_SEL_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define APB_MISC_GP_OBSCTRL_0_OBS_PART_SEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OBSCTRL_0_OBS_PART_SEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OBSCTRL_0_OBS_PART_SEL_AO                   _MK_ENUM_CONST(0)
+#define APB_MISC_GP_OBSCTRL_0_OBS_PART_SEL_CPU                  _MK_ENUM_CONST(1)
+#define APB_MISC_GP_OBSCTRL_0_OBS_PART_SEL_DIS                  _MK_ENUM_CONST(2)
+#define APB_MISC_GP_OBSCTRL_0_OBS_PART_SEL_GR                   _MK_ENUM_CONST(3)
+#define APB_MISC_GP_OBSCTRL_0_OBS_PART_SEL_MPE                  _MK_ENUM_CONST(4)
+#define APB_MISC_GP_OBSCTRL_0_OBS_PART_SEL_TDA                  _MK_ENUM_CONST(5)
+#define APB_MISC_GP_OBSCTRL_0_OBS_PART_SEL_TDB                  _MK_ENUM_CONST(6)
+#define APB_MISC_GP_OBSCTRL_0_OBS_PART_SEL_VDE                  _MK_ENUM_CONST(7)
+#define APB_MISC_GP_OBSCTRL_0_OBS_PART_SEL_VE                   _MK_ENUM_CONST(8)
+
+// Observation bus enable
+#define APB_MISC_GP_OBSCTRL_0_OBS_EN_SHIFT                      _MK_SHIFT_CONST(31)
+#define APB_MISC_GP_OBSCTRL_0_OBS_EN_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_OBSCTRL_0_OBS_EN_SHIFT)
+#define APB_MISC_GP_OBSCTRL_0_OBS_EN_RANGE                      31:31
+#define APB_MISC_GP_OBSCTRL_0_OBS_EN_WOFFSET                    0x0
+#define APB_MISC_GP_OBSCTRL_0_OBS_EN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OBSCTRL_0_OBS_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_OBSCTRL_0_OBS_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OBSCTRL_0_OBS_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OBSCTRL_0_OBS_EN_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_GP_OBSCTRL_0_OBS_EN_ENABLE                     _MK_ENUM_CONST(1)
+
+
+// Register APB_MISC_GP_OBSDATA_0  
+#define APB_MISC_GP_OBSDATA_0                   _MK_ADDR_CONST(0x81c)
+#define APB_MISC_GP_OBSDATA_0_WORD_COUNT                        0x1
+#define APB_MISC_GP_OBSDATA_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OBSDATA_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OBSDATA_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OBSDATA_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OBSDATA_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_GP_OBSDATA_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+// Observation port data.  This should be the same data that is going out on the observation bus.
+#define APB_MISC_GP_OBSDATA_0_OBS_DATA_SHIFT                    _MK_SHIFT_CONST(0)
+#define APB_MISC_GP_OBSDATA_0_OBS_DATA_FIELD                    (_MK_MASK_CONST(0xffffffff) << APB_MISC_GP_OBSDATA_0_OBS_DATA_SHIFT)
+#define APB_MISC_GP_OBSDATA_0_OBS_DATA_RANGE                    31:0
+#define APB_MISC_GP_OBSDATA_0_OBS_DATA_WOFFSET                  0x0
+#define APB_MISC_GP_OBSDATA_0_OBS_DATA_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OBSDATA_0_OBS_DATA_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OBSDATA_0_OBS_DATA_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OBSDATA_0_OBS_DATA_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_EFUSEREQ_0  
+#define APB_MISC_GP_EFUSEREQ_0                  _MK_ADDR_CONST(0x820)
+#define APB_MISC_GP_EFUSEREQ_0_WORD_COUNT                       0x1
+#define APB_MISC_GP_EFUSEREQ_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EFUSEREQ_0_RESET_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_EFUSEREQ_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EFUSEREQ_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EFUSEREQ_0_READ_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_EFUSEREQ_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_EFUSEREQ_0_EF_RESERVED0_SHIFT                       _MK_SHIFT_CONST(0)
+#define APB_MISC_GP_EFUSEREQ_0_EF_RESERVED0_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_EFUSEREQ_0_EF_RESERVED0_SHIFT)
+#define APB_MISC_GP_EFUSEREQ_0_EF_RESERVED0_RANGE                       0:0
+#define APB_MISC_GP_EFUSEREQ_0_EF_RESERVED0_WOFFSET                     0x0
+#define APB_MISC_GP_EFUSEREQ_0_EF_RESERVED0_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EFUSEREQ_0_EF_RESERVED0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_EFUSEREQ_0_EF_RESERVED0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EFUSEREQ_0_EF_RESERVED0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_EFUSEOFF_0  
+#define APB_MISC_GP_EFUSEOFF_0                  _MK_ADDR_CONST(0x824)
+#define APB_MISC_GP_EFUSEOFF_0_WORD_COUNT                       0x1
+#define APB_MISC_GP_EFUSEOFF_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EFUSEOFF_0_RESET_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_EFUSEOFF_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EFUSEOFF_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EFUSEOFF_0_READ_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_EFUSEOFF_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_EFUSEOFF_0_EF_RESERVED1_SHIFT                       _MK_SHIFT_CONST(0)
+#define APB_MISC_GP_EFUSEOFF_0_EF_RESERVED1_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_EFUSEOFF_0_EF_RESERVED1_SHIFT)
+#define APB_MISC_GP_EFUSEOFF_0_EF_RESERVED1_RANGE                       0:0
+#define APB_MISC_GP_EFUSEOFF_0_EF_RESERVED1_WOFFSET                     0x0
+#define APB_MISC_GP_EFUSEOFF_0_EF_RESERVED1_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EFUSEOFF_0_EF_RESERVED1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_EFUSEOFF_0_EF_RESERVED1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EFUSEOFF_0_EF_RESERVED1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_EFUSEWRDAT_0  
+#define APB_MISC_GP_EFUSEWRDAT_0                        _MK_ADDR_CONST(0x828)
+#define APB_MISC_GP_EFUSEWRDAT_0_WORD_COUNT                     0x1
+#define APB_MISC_GP_EFUSEWRDAT_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EFUSEWRDAT_0_RESET_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_EFUSEWRDAT_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EFUSEWRDAT_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EFUSEWRDAT_0_READ_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_EFUSEWRDAT_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_EFUSEWRDAT_0_EF_RESERVED2_SHIFT                     _MK_SHIFT_CONST(0)
+#define APB_MISC_GP_EFUSEWRDAT_0_EF_RESERVED2_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_EFUSEWRDAT_0_EF_RESERVED2_SHIFT)
+#define APB_MISC_GP_EFUSEWRDAT_0_EF_RESERVED2_RANGE                     0:0
+#define APB_MISC_GP_EFUSEWRDAT_0_EF_RESERVED2_WOFFSET                   0x0
+#define APB_MISC_GP_EFUSEWRDAT_0_EF_RESERVED2_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EFUSEWRDAT_0_EF_RESERVED2_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_EFUSEWRDAT_0_EF_RESERVED2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EFUSEWRDAT_0_EF_RESERVED2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_EFUSERDDAT_0  
+#define APB_MISC_GP_EFUSERDDAT_0                        _MK_ADDR_CONST(0x82c)
+#define APB_MISC_GP_EFUSERDDAT_0_WORD_COUNT                     0x1
+#define APB_MISC_GP_EFUSERDDAT_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EFUSERDDAT_0_RESET_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_EFUSERDDAT_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EFUSERDDAT_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EFUSERDDAT_0_READ_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_EFUSERDDAT_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_EFUSERDDAT_0_EF_RESERVED3_SHIFT                     _MK_SHIFT_CONST(0)
+#define APB_MISC_GP_EFUSERDDAT_0_EF_RESERVED3_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_EFUSERDDAT_0_EF_RESERVED3_SHIFT)
+#define APB_MISC_GP_EFUSERDDAT_0_EF_RESERVED3_RANGE                     0:0
+#define APB_MISC_GP_EFUSERDDAT_0_EF_RESERVED3_WOFFSET                   0x0
+#define APB_MISC_GP_EFUSERDDAT_0_EF_RESERVED3_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EFUSERDDAT_0_EF_RESERVED3_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_EFUSERDDAT_0_EF_RESERVED3_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EFUSERDDAT_0_EF_RESERVED3_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_EFUSEVAL1_0  
+#define APB_MISC_GP_EFUSEVAL1_0                 _MK_ADDR_CONST(0x830)
+#define APB_MISC_GP_EFUSEVAL1_0_WORD_COUNT                      0x1
+#define APB_MISC_GP_EFUSEVAL1_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EFUSEVAL1_0_RESET_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_EFUSEVAL1_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EFUSEVAL1_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EFUSEVAL1_0_READ_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_EFUSEVAL1_0_WRITE_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_EFUSEVAL1_0_EF_RESERVED4_SHIFT                      _MK_SHIFT_CONST(0)
+#define APB_MISC_GP_EFUSEVAL1_0_EF_RESERVED4_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_EFUSEVAL1_0_EF_RESERVED4_SHIFT)
+#define APB_MISC_GP_EFUSEVAL1_0_EF_RESERVED4_RANGE                      0:0
+#define APB_MISC_GP_EFUSEVAL1_0_EF_RESERVED4_WOFFSET                    0x0
+#define APB_MISC_GP_EFUSEVAL1_0_EF_RESERVED4_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EFUSEVAL1_0_EF_RESERVED4_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_EFUSEVAL1_0_EF_RESERVED4_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EFUSEVAL1_0_EF_RESERVED4_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_EFUSEVAL2_0  
+#define APB_MISC_GP_EFUSEVAL2_0                 _MK_ADDR_CONST(0x834)
+#define APB_MISC_GP_EFUSEVAL2_0_WORD_COUNT                      0x1
+#define APB_MISC_GP_EFUSEVAL2_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EFUSEVAL2_0_RESET_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_EFUSEVAL2_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EFUSEVAL2_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EFUSEVAL2_0_READ_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_EFUSEVAL2_0_WRITE_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_EFUSEVAL2_0_EF_RESERVED5_SHIFT                      _MK_SHIFT_CONST(0)
+#define APB_MISC_GP_EFUSEVAL2_0_EF_RESERVED5_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_EFUSEVAL2_0_EF_RESERVED5_SHIFT)
+#define APB_MISC_GP_EFUSEVAL2_0_EF_RESERVED5_RANGE                      0:0
+#define APB_MISC_GP_EFUSEVAL2_0_EF_RESERVED5_WOFFSET                    0x0
+#define APB_MISC_GP_EFUSEVAL2_0_EF_RESERVED5_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EFUSEVAL2_0_EF_RESERVED5_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_EFUSEVAL2_0_EF_RESERVED5_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EFUSEVAL2_0_EF_RESERVED5_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_EFUSEBYPASSID_0  
+#define APB_MISC_GP_EFUSEBYPASSID_0                     _MK_ADDR_CONST(0x838)
+#define APB_MISC_GP_EFUSEBYPASSID_0_WORD_COUNT                  0x1
+#define APB_MISC_GP_EFUSEBYPASSID_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EFUSEBYPASSID_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_EFUSEBYPASSID_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EFUSEBYPASSID_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EFUSEBYPASSID_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_EFUSEBYPASSID_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_EFUSEBYPASSID_0_EF_RESERVED6_SHIFT                  _MK_SHIFT_CONST(0)
+#define APB_MISC_GP_EFUSEBYPASSID_0_EF_RESERVED6_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_GP_EFUSEBYPASSID_0_EF_RESERVED6_SHIFT)
+#define APB_MISC_GP_EFUSEBYPASSID_0_EF_RESERVED6_RANGE                  0:0
+#define APB_MISC_GP_EFUSEBYPASSID_0_EF_RESERVED6_WOFFSET                        0x0
+#define APB_MISC_GP_EFUSEBYPASSID_0_EF_RESERVED6_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EFUSEBYPASSID_0_EF_RESERVED6_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_EFUSEBYPASSID_0_EF_RESERVED6_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EFUSEBYPASSID_0_EF_RESERVED6_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_BRDCLK_TRIM_0  
+#define APB_MISC_GP_BRDCLK_TRIM_0                       _MK_ADDR_CONST(0x83c)
+#define APB_MISC_GP_BRDCLK_TRIM_0_WORD_COUNT                    0x1
+#define APB_MISC_GP_BRDCLK_TRIM_0_RESET_VAL                     _MK_MASK_CONST(0x4)
+#define APB_MISC_GP_BRDCLK_TRIM_0_RESET_MASK                    _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_BRDCLK_TRIM_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_BRDCLK_TRIM_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_BRDCLK_TRIM_0_READ_MASK                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_BRDCLK_TRIM_0_WRITE_MASK                    _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_BRDCLK_TRIM_0_BRDCLKTRIM_SHIFT                      _MK_SHIFT_CONST(0)
+#define APB_MISC_GP_BRDCLK_TRIM_0_BRDCLKTRIM_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_BRDCLK_TRIM_0_BRDCLKTRIM_SHIFT)
+#define APB_MISC_GP_BRDCLK_TRIM_0_BRDCLKTRIM_RANGE                      4:0
+#define APB_MISC_GP_BRDCLK_TRIM_0_BRDCLKTRIM_WOFFSET                    0x0
+#define APB_MISC_GP_BRDCLK_TRIM_0_BRDCLKTRIM_DEFAULT                    _MK_MASK_CONST(0x4)
+#define APB_MISC_GP_BRDCLK_TRIM_0_BRDCLKTRIM_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_BRDCLK_TRIM_0_BRDCLKTRIM_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_BRDCLK_TRIM_0_BRDCLKTRIM_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Reserved address 2112 [0x840] 
+
+// Reserved address 2116 [0x844] 
+
+// Reserved address 2120 [0x848] 
+
+// Reserved address 2124 [0x84c] 
+
+// Reserved address 2128 [0x850] 
+
+// Reserved address 2132 [0x854] 
+
+// Register APB_MISC_GP_ASDBGREG2_0  
+#define APB_MISC_GP_ASDBGREG2_0                 _MK_ADDR_CONST(0x858)
+#define APB_MISC_GP_ASDBGREG2_0_WORD_COUNT                      0x1
+#define APB_MISC_GP_ASDBGREG2_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_RESET_MASK                      _MK_MASK_CONST(0x7ff80)
+#define APB_MISC_GP_ASDBGREG2_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_READ_MASK                       _MK_MASK_CONST(0x7ff80)
+#define APB_MISC_GP_ASDBGREG2_0_WRITE_MASK                      _MK_MASK_CONST(0x7ff80)
+//Enable bypass of functional clock with test clock 8
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T8CLK_SHIFT                       _MK_SHIFT_CONST(7)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T8CLK_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T8CLK_SHIFT)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T8CLK_RANGE                       7:7
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T8CLK_WOFFSET                     0x0
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T8CLK_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T8CLK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T8CLK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T8CLK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T8CLK_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T8CLK_ENABLE                      _MK_ENUM_CONST(1)
+
+//Enable bypass of functional clock with test clock 9
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T9CLK_SHIFT                       _MK_SHIFT_CONST(8)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T9CLK_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T9CLK_SHIFT)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T9CLK_RANGE                       8:8
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T9CLK_WOFFSET                     0x0
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T9CLK_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T9CLK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T9CLK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T9CLK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T9CLK_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T9CLK_ENABLE                      _MK_ENUM_CONST(1)
+
+//Enable bypass of functional clock with test clock 10
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T10CLK_SHIFT                      _MK_SHIFT_CONST(9)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T10CLK_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T10CLK_SHIFT)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T10CLK_RANGE                      9:9
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T10CLK_WOFFSET                    0x0
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T10CLK_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T10CLK_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T10CLK_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T10CLK_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T10CLK_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T10CLK_ENABLE                     _MK_ENUM_CONST(1)
+
+//Enable bypass of functional clock with test clock 11
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T11CLK_SHIFT                      _MK_SHIFT_CONST(10)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T11CLK_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T11CLK_SHIFT)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T11CLK_RANGE                      10:10
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T11CLK_WOFFSET                    0x0
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T11CLK_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T11CLK_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T11CLK_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T11CLK_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T11CLK_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T11CLK_ENABLE                     _MK_ENUM_CONST(1)
+
+//Enable bypass of functional clock with test clock 12
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T12CLK_SHIFT                      _MK_SHIFT_CONST(11)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T12CLK_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T12CLK_SHIFT)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T12CLK_RANGE                      11:11
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T12CLK_WOFFSET                    0x0
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T12CLK_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T12CLK_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T12CLK_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T12CLK_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T12CLK_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T12CLK_ENABLE                     _MK_ENUM_CONST(1)
+
+//Enable bypass of functional clock with test clock 13
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T13CLK_SHIFT                      _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T13CLK_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T13CLK_SHIFT)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T13CLK_RANGE                      12:12
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T13CLK_WOFFSET                    0x0
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T13CLK_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T13CLK_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T13CLK_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T13CLK_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T13CLK_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T13CLK_ENABLE                     _MK_ENUM_CONST(1)
+
+//Enable bypass of functional clock with test clock 14
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T14CLK_SHIFT                      _MK_SHIFT_CONST(13)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T14CLK_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T14CLK_SHIFT)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T14CLK_RANGE                      13:13
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T14CLK_WOFFSET                    0x0
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T14CLK_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T14CLK_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T14CLK_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T14CLK_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T14CLK_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T14CLK_ENABLE                     _MK_ENUM_CONST(1)
+
+//Enable bypass of functional clock with test clock 15
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T15CLK_SHIFT                      _MK_SHIFT_CONST(14)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T15CLK_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T15CLK_SHIFT)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T15CLK_RANGE                      14:14
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T15CLK_WOFFSET                    0x0
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T15CLK_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T15CLK_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T15CLK_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T15CLK_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T15CLK_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T15CLK_ENABLE                     _MK_ENUM_CONST(1)
+
+//Enable bypass of functional clock with test clock 16
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T16CLK_SHIFT                      _MK_SHIFT_CONST(15)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T16CLK_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T16CLK_SHIFT)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T16CLK_RANGE                      15:15
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T16CLK_WOFFSET                    0x0
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T16CLK_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T16CLK_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T16CLK_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T16CLK_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T16CLK_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T16CLK_ENABLE                     _MK_ENUM_CONST(1)
+
+//Enable bypass of functional clock with test clock 17
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T17CLK_SHIFT                      _MK_SHIFT_CONST(16)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T17CLK_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T17CLK_SHIFT)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T17CLK_RANGE                      16:16
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T17CLK_WOFFSET                    0x0
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T17CLK_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T17CLK_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T17CLK_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T17CLK_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T17CLK_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T17CLK_ENABLE                     _MK_ENUM_CONST(1)
+
+//Enable bypass of functional clock with test clock 18
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T18CLK_SHIFT                      _MK_SHIFT_CONST(17)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T18CLK_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T18CLK_SHIFT)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T18CLK_RANGE                      17:17
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T18CLK_WOFFSET                    0x0
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T18CLK_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T18CLK_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T18CLK_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T18CLK_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T18CLK_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T18CLK_ENABLE                     _MK_ENUM_CONST(1)
+
+//Enable bypass of sync Already in NV_car
+//  18       rw  CFG2TMC_OSCFI_BYPASS     i=0x0  //Enable bypass of oscfi
+//            enum ( DISABLE, ENABLE )
+//  19       rw  CFG2TMC_OSCFI_EN         i=0x0  //Enable oscfi refclk
+//      enum ( DISABLE, ENABLE )
+//      enum ( DISABLE, ENABLE )
+//  25:21   rw  CFG2TMC_OSCFI_D           i=0x0  //
+//  31:26   rw  CFG2TMC_OSCFI_S           i=0x0  //
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_SYNC_SHIFT                        _MK_SHIFT_CONST(18)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_SYNC_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_SYNC_SHIFT)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_SYNC_RANGE                        18:18
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_SYNC_WOFFSET                      0x0
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_SYNC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_SYNC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_SYNC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_SYNC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_SYNC_DISABLE                      _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_SYNC_ENABLE                       _MK_ENUM_CONST(1)
+
+
+// Register APB_MISC_GP_EMU_REVID_0  
+#define APB_MISC_GP_EMU_REVID_0                 _MK_ADDR_CONST(0x860)
+#define APB_MISC_GP_EMU_REVID_0_WORD_COUNT                      0x1
+#define APB_MISC_GP_EMU_REVID_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EMU_REVID_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_GP_EMU_REVID_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EMU_REVID_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EMU_REVID_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_GP_EMU_REVID_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
+// USED by emulators to indicate netlist #, 0 for silicon.
+#define APB_MISC_GP_EMU_REVID_0_NETLIST_SHIFT                   _MK_SHIFT_CONST(0)
+#define APB_MISC_GP_EMU_REVID_0_NETLIST_FIELD                   (_MK_MASK_CONST(0xffff) << APB_MISC_GP_EMU_REVID_0_NETLIST_SHIFT)
+#define APB_MISC_GP_EMU_REVID_0_NETLIST_RANGE                   15:0
+#define APB_MISC_GP_EMU_REVID_0_NETLIST_WOFFSET                 0x0
+#define APB_MISC_GP_EMU_REVID_0_NETLIST_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EMU_REVID_0_NETLIST_DEFAULT_MASK                    _MK_MASK_CONST(0xffff)
+#define APB_MISC_GP_EMU_REVID_0_NETLIST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EMU_REVID_0_NETLIST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EMU_REVID_0_NETLIST_INIT_ENUM                       NV_EMUL_NETLIST
+
+// USED by emulators to indicate patch #, 0 for silicon.
+#define APB_MISC_GP_EMU_REVID_0_PATCH_SHIFT                     _MK_SHIFT_CONST(16)
+#define APB_MISC_GP_EMU_REVID_0_PATCH_FIELD                     (_MK_MASK_CONST(0xffff) << APB_MISC_GP_EMU_REVID_0_PATCH_SHIFT)
+#define APB_MISC_GP_EMU_REVID_0_PATCH_RANGE                     31:16
+#define APB_MISC_GP_EMU_REVID_0_PATCH_WOFFSET                   0x0
+#define APB_MISC_GP_EMU_REVID_0_PATCH_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EMU_REVID_0_PATCH_DEFAULT_MASK                      _MK_MASK_CONST(0xffff)
+#define APB_MISC_GP_EMU_REVID_0_PATCH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EMU_REVID_0_PATCH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EMU_REVID_0_PATCH_INIT_ENUM                 NV_EMUL_PATCH
+
+
+// Register APB_MISC_GP_TRANSACTOR_SCRATCH_0  
+#define APB_MISC_GP_TRANSACTOR_SCRATCH_0                        _MK_ADDR_CONST(0x864)
+#define APB_MISC_GP_TRANSACTOR_SCRATCH_0_WORD_COUNT                     0x1
+#define APB_MISC_GP_TRANSACTOR_SCRATCH_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_TRANSACTOR_SCRATCH_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_GP_TRANSACTOR_SCRATCH_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_TRANSACTOR_SCRATCH_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_TRANSACTOR_SCRATCH_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_GP_TRANSACTOR_SCRATCH_0_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
+// used for emulation to determine test results.
+#define APB_MISC_GP_TRANSACTOR_SCRATCH_0_TRANSACTOR_SCRATCH_SHIFT                       _MK_SHIFT_CONST(0)
+#define APB_MISC_GP_TRANSACTOR_SCRATCH_0_TRANSACTOR_SCRATCH_FIELD                       (_MK_MASK_CONST(0xffffffff) << APB_MISC_GP_TRANSACTOR_SCRATCH_0_TRANSACTOR_SCRATCH_SHIFT)
+#define APB_MISC_GP_TRANSACTOR_SCRATCH_0_TRANSACTOR_SCRATCH_RANGE                       31:0
+#define APB_MISC_GP_TRANSACTOR_SCRATCH_0_TRANSACTOR_SCRATCH_WOFFSET                     0x0
+#define APB_MISC_GP_TRANSACTOR_SCRATCH_0_TRANSACTOR_SCRATCH_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_TRANSACTOR_SCRATCH_0_TRANSACTOR_SCRATCH_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_GP_TRANSACTOR_SCRATCH_0_TRANSACTOR_SCRATCH_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_TRANSACTOR_SCRATCH_0_TRANSACTOR_SCRATCH_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_AOCFG1PADCTRL_0  //        0       rw  CFG2TMC_AOCFG1_PULLD_EN i=0x0   // AOCFG1 pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_AOCFG1_PULLU_EN i=0x0   // AOCFG1 pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_AOCFG1PADCTRL_0                     _MK_ADDR_CONST(0x868)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_WORD_COUNT                  0x1
+#define APB_MISC_GP_AOCFG1PADCTRL_0_RESET_VAL                   _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_RESET_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_READ_MASK                   _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_WRITE_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+// AOCFG1 data pins high speed mode enable
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_HSM_EN_SHIFT                 _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_HSM_EN_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_HSM_EN_SHIFT)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_HSM_EN_RANGE                 2:2
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_HSM_EN_WOFFSET                       0x0
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_HSM_EN_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_HSM_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_HSM_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_HSM_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_HSM_EN_DISABLE                       _MK_ENUM_CONST(0)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_HSM_EN_ENABLE                        _MK_ENUM_CONST(1)
+
+// AOCFG1 data pins schmidt enable
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_SCHMT_EN_SHIFT                       _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_SCHMT_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_SCHMT_EN_RANGE                       3:3
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_SCHMT_EN_WOFFSET                     0x0
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_SCHMT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_SCHMT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_SCHMT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_SCHMT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_SCHMT_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_SCHMT_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// AOCFG1 data pins low power mode select
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_LPMD_SHIFT                   _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_LPMD_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_LPMD_SHIFT)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_LPMD_RANGE                   5:4
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_LPMD_WOFFSET                 0x0
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_LPMD_DEFAULT                 _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_LPMD_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_LPMD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_LPMD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVDN_SHIFT                      _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVDN_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVDN_RANGE                      16:12
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVDN_WOFFSET                    0x0
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVDN_DEFAULT                    _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVDN_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVDN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVDN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVUP_SHIFT                      _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVUP_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVUP_RANGE                      24:20
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVUP_WOFFSET                    0x0
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVUP_DEFAULT                    _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVUP_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVUP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVUP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVDN_SLWR_SHIFT                 _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVDN_SLWR_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVDN_SLWR_RANGE                 29:28
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVDN_SLWR_WOFFSET                       0x0
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVDN_SLWR_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVDN_SLWR_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVDN_SLWR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVUP_SLWF_SHIFT                 _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVUP_SLWF_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVUP_SLWF_RANGE                 31:30
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVUP_SLWF_WOFFSET                       0x0
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVUP_SLWF_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVUP_SLWF_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVUP_SLWF_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_AOCFG2PADCTRL_0  //        0       rw  CFG2TMC_AOCFG2_PULLD_EN i=0x0   // AOCFG2 pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_AOCFG2_PULLU_EN i=0x0   // AOCFG2 pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_AOCFG2PADCTRL_0                     _MK_ADDR_CONST(0x86c)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_WORD_COUNT                  0x1
+#define APB_MISC_GP_AOCFG2PADCTRL_0_RESET_VAL                   _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_RESET_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_READ_MASK                   _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_WRITE_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+// AOCFG2 data pins high speed mode enable
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_HSM_EN_SHIFT                 _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_HSM_EN_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_HSM_EN_SHIFT)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_HSM_EN_RANGE                 2:2
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_HSM_EN_WOFFSET                       0x0
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_HSM_EN_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_HSM_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_HSM_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_HSM_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_HSM_EN_DISABLE                       _MK_ENUM_CONST(0)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_HSM_EN_ENABLE                        _MK_ENUM_CONST(1)
+
+// AOCFG2 data pins schmidt enable
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_SCHMT_EN_SHIFT                       _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_SCHMT_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_SCHMT_EN_RANGE                       3:3
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_SCHMT_EN_WOFFSET                     0x0
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_SCHMT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_SCHMT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_SCHMT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_SCHMT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_SCHMT_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_SCHMT_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// AOCFG2 data pins low power mode select
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_LPMD_SHIFT                   _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_LPMD_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_LPMD_SHIFT)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_LPMD_RANGE                   5:4
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_LPMD_WOFFSET                 0x0
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_LPMD_DEFAULT                 _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_LPMD_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_LPMD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_LPMD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVDN_SHIFT                      _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVDN_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVDN_RANGE                      16:12
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVDN_WOFFSET                    0x0
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVDN_DEFAULT                    _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVDN_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVDN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVDN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVUP_SHIFT                      _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVUP_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVUP_RANGE                      24:20
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVUP_WOFFSET                    0x0
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVUP_DEFAULT                    _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVUP_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVUP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVUP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVDN_SLWR_SHIFT                 _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVDN_SLWR_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVDN_SLWR_RANGE                 29:28
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVDN_SLWR_WOFFSET                       0x0
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVDN_SLWR_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVDN_SLWR_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVDN_SLWR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVUP_SLWF_SHIFT                 _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVUP_SLWF_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVUP_SLWF_RANGE                 31:30
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVUP_SLWF_WOFFSET                       0x0
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVUP_SLWF_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVUP_SLWF_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVUP_SLWF_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_ATCFG1PADCTRL_0  //        0       rw  CFG2TMC_ATCFG1_PULLD_EN   i=0x0   // ATCFG1 pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_ATCFG1_PULLU_EN   i=0x0   // ATCFG1 pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_ATCFG1PADCTRL_0                     _MK_ADDR_CONST(0x870)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_WORD_COUNT                  0x1
+#define APB_MISC_GP_ATCFG1PADCTRL_0_RESET_VAL                   _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_RESET_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_READ_MASK                   _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_WRITE_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+// ATCFG1 data pins high speed mode enable
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_HSM_EN_SHIFT                 _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_HSM_EN_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_HSM_EN_SHIFT)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_HSM_EN_RANGE                 2:2
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_HSM_EN_WOFFSET                       0x0
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_HSM_EN_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_HSM_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_HSM_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_HSM_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_HSM_EN_DISABLE                       _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_HSM_EN_ENABLE                        _MK_ENUM_CONST(1)
+
+// ATCFG1 data pins schmidt enable
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_SCHMT_EN_SHIFT                       _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_SCHMT_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_SCHMT_EN_RANGE                       3:3
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_SCHMT_EN_WOFFSET                     0x0
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_SCHMT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_SCHMT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_SCHMT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_SCHMT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_SCHMT_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_SCHMT_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// ATCFG1 data pins low power mode select
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_LPMD_SHIFT                   _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_LPMD_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_LPMD_SHIFT)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_LPMD_RANGE                   5:4
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_LPMD_WOFFSET                 0x0
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_LPMD_DEFAULT                 _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_LPMD_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_LPMD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_LPMD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVDN_SHIFT                      _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVDN_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVDN_RANGE                      16:12
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVDN_WOFFSET                    0x0
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVDN_DEFAULT                    _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVDN_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVDN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVDN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVUP_SHIFT                      _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVUP_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVUP_RANGE                      24:20
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVUP_WOFFSET                    0x0
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVUP_DEFAULT                    _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVUP_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVUP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVUP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVDN_SLWR_SHIFT                 _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVDN_SLWR_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVDN_SLWR_RANGE                 29:28
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVDN_SLWR_WOFFSET                       0x0
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVDN_SLWR_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVDN_SLWR_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVDN_SLWR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVUP_SLWF_SHIFT                 _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVUP_SLWF_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVUP_SLWF_RANGE                 31:30
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVUP_SLWF_WOFFSET                       0x0
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVUP_SLWF_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVUP_SLWF_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVUP_SLWF_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_ATCFG2PADCTRL_0  //        0       rw  CFG2TMC_ATCFG2_PULLD_EN   i=0x0   // ATCFG2 pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_ATCFG2_PULLU_EN   i=0x0   // ATCFG2 pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_ATCFG2PADCTRL_0                     _MK_ADDR_CONST(0x874)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_WORD_COUNT                  0x1
+#define APB_MISC_GP_ATCFG2PADCTRL_0_RESET_VAL                   _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_RESET_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_READ_MASK                   _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_WRITE_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+// ATCFG2 data pins high speed mode enable
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_HSM_EN_SHIFT                 _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_HSM_EN_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_HSM_EN_SHIFT)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_HSM_EN_RANGE                 2:2
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_HSM_EN_WOFFSET                       0x0
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_HSM_EN_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_HSM_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_HSM_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_HSM_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_HSM_EN_DISABLE                       _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_HSM_EN_ENABLE                        _MK_ENUM_CONST(1)
+
+// ATCFG2 data pins schmidt enable
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_SCHMT_EN_SHIFT                       _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_SCHMT_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_SCHMT_EN_RANGE                       3:3
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_SCHMT_EN_WOFFSET                     0x0
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_SCHMT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_SCHMT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_SCHMT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_SCHMT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_SCHMT_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_SCHMT_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// ATCFG2 data pins low power mode select
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_LPMD_SHIFT                   _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_LPMD_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_LPMD_SHIFT)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_LPMD_RANGE                   5:4
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_LPMD_WOFFSET                 0x0
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_LPMD_DEFAULT                 _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_LPMD_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_LPMD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_LPMD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVDN_SHIFT                      _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVDN_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVDN_RANGE                      16:12
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVDN_WOFFSET                    0x0
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVDN_DEFAULT                    _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVDN_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVDN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVDN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVUP_SHIFT                      _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVUP_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVUP_RANGE                      24:20
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVUP_WOFFSET                    0x0
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVUP_DEFAULT                    _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVUP_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVUP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVUP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVDN_SLWR_SHIFT                 _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVDN_SLWR_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVDN_SLWR_RANGE                 29:28
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVDN_SLWR_WOFFSET                       0x0
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVDN_SLWR_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVDN_SLWR_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVDN_SLWR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVUP_SLWF_SHIFT                 _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVUP_SLWF_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVUP_SLWF_RANGE                 31:30
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVUP_SLWF_WOFFSET                       0x0
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVUP_SLWF_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVUP_SLWF_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVUP_SLWF_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_CDEV1CFGPADCTRL_0  //        0       rw  CFG2TMC_CDEV1CFG_PULLD_EN   i=0x0   // CDEV1CFG pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_CDEV1CFG_PULLU_EN   i=0x0   // CDEV1CFG pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0                   _MK_ADDR_CONST(0x878)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_WORD_COUNT                        0x1
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_RESET_VAL                         _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_RESET_MASK                        _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_READ_MASK                         _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_WRITE_MASK                        _MK_MASK_CONST(0xf1f1f03c)
+// CDEV1CFG data pins high speed mode enable
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_HSM_EN_SHIFT                     _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_HSM_EN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_HSM_EN_SHIFT)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_HSM_EN_RANGE                     2:2
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_HSM_EN_WOFFSET                   0x0
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_HSM_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_HSM_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_HSM_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_HSM_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_HSM_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_HSM_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// CDEV1CFG data pins schmidt enable
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_SCHMT_EN_SHIFT                   _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_SCHMT_EN_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_SCHMT_EN_RANGE                   3:3
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_SCHMT_EN_WOFFSET                 0x0
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_SCHMT_EN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_SCHMT_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_SCHMT_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_SCHMT_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_SCHMT_EN_DISABLE                 _MK_ENUM_CONST(0)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_SCHMT_EN_ENABLE                  _MK_ENUM_CONST(1)
+
+// CDEV1CFG data pins low power mode select
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_LPMD_SHIFT                       _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_LPMD_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_LPMD_SHIFT)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_LPMD_RANGE                       5:4
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_LPMD_WOFFSET                     0x0
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_LPMD_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_LPMD_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_LPMD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_LPMD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVDN_SHIFT                  _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVDN_FIELD                  (_MK_MASK_CONST(0x1f) << APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVDN_RANGE                  16:12
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVDN_WOFFSET                        0x0
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVDN_DEFAULT                        _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVDN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVDN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVDN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVUP_SHIFT                  _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVUP_FIELD                  (_MK_MASK_CONST(0x1f) << APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVUP_RANGE                  24:20
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVUP_WOFFSET                        0x0
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVUP_DEFAULT                        _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVUP_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVUP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVUP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVDN_SLWR_SHIFT                     _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVDN_SLWR_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVDN_SLWR_RANGE                     29:28
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVDN_SLWR_WOFFSET                   0x0
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVDN_SLWR_DEFAULT                   _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVDN_SLWR_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVDN_SLWR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVUP_SLWF_SHIFT                     _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVUP_SLWF_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVUP_SLWF_RANGE                     31:30
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVUP_SLWF_WOFFSET                   0x0
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVUP_SLWF_DEFAULT                   _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVUP_SLWF_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVUP_SLWF_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_CDEV2CFGPADCTRL_0  //        0       rw  CFG2TMC_CDEV2CFG_PULLD_EN   i=0x0   // CDEV2CFG pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_CDEV2CFG_PULLU_EN   i=0x0   // CDEV2CFG pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0                   _MK_ADDR_CONST(0x87c)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_WORD_COUNT                        0x1
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_RESET_VAL                         _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_RESET_MASK                        _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_READ_MASK                         _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_WRITE_MASK                        _MK_MASK_CONST(0xf1f1f03c)
+// CDEV2CFG data pins high speed mode enable
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_HSM_EN_SHIFT                     _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_HSM_EN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_HSM_EN_SHIFT)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_HSM_EN_RANGE                     2:2
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_HSM_EN_WOFFSET                   0x0
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_HSM_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_HSM_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_HSM_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_HSM_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_HSM_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_HSM_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// CDEV2CFG data pins schmidt enable
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_SCHMT_EN_SHIFT                   _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_SCHMT_EN_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_SCHMT_EN_RANGE                   3:3
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_SCHMT_EN_WOFFSET                 0x0
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_SCHMT_EN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_SCHMT_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_SCHMT_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_SCHMT_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_SCHMT_EN_DISABLE                 _MK_ENUM_CONST(0)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_SCHMT_EN_ENABLE                  _MK_ENUM_CONST(1)
+
+// CDEV2CFG data pins low power mode select
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_LPMD_SHIFT                       _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_LPMD_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_LPMD_SHIFT)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_LPMD_RANGE                       5:4
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_LPMD_WOFFSET                     0x0
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_LPMD_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_LPMD_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_LPMD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_LPMD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVDN_SHIFT                  _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVDN_FIELD                  (_MK_MASK_CONST(0x1f) << APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVDN_RANGE                  16:12
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVDN_WOFFSET                        0x0
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVDN_DEFAULT                        _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVDN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVDN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVDN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVUP_SHIFT                  _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVUP_FIELD                  (_MK_MASK_CONST(0x1f) << APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVUP_RANGE                  24:20
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVUP_WOFFSET                        0x0
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVUP_DEFAULT                        _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVUP_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVUP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVUP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVDN_SLWR_SHIFT                     _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVDN_SLWR_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVDN_SLWR_RANGE                     29:28
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVDN_SLWR_WOFFSET                   0x0
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVDN_SLWR_DEFAULT                   _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVDN_SLWR_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVDN_SLWR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVUP_SLWF_SHIFT                     _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVUP_SLWF_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVUP_SLWF_RANGE                     31:30
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVUP_SLWF_WOFFSET                   0x0
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVUP_SLWF_DEFAULT                   _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVUP_SLWF_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVUP_SLWF_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_CSUSCFGPADCTRL_0  //        0       rw  CFG2TMC_CSUSCFG_PULLD_EN   i=0x0   // CSUSCFG pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_CSUSCFG_PULLU_EN   i=0x0   // CSUSCFG pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_CSUSCFGPADCTRL_0                    _MK_ADDR_CONST(0x880)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_WORD_COUNT                         0x1
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_RESET_VAL                  _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_RESET_MASK                         _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_READ_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_WRITE_MASK                         _MK_MASK_CONST(0xf1f1f03c)
+// CSUSCFG data pins high speed mode enable
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_HSM_EN_SHIFT                       _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_HSM_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_HSM_EN_SHIFT)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_HSM_EN_RANGE                       2:2
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_HSM_EN_WOFFSET                     0x0
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_HSM_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_HSM_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_HSM_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_HSM_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_HSM_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_HSM_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// CSUSCFG data pins schmidt enable
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_SCHMT_EN_SHIFT                     _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_SCHMT_EN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_SCHMT_EN_RANGE                     3:3
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_SCHMT_EN_WOFFSET                   0x0
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_SCHMT_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_SCHMT_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_SCHMT_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_SCHMT_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_SCHMT_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_SCHMT_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// CSUSCFG data pins low power mode select
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_LPMD_SHIFT                 _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_LPMD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_LPMD_SHIFT)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_LPMD_RANGE                 5:4
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_LPMD_WOFFSET                       0x0
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_LPMD_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_LPMD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_LPMD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_LPMD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVDN_SHIFT                    _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVDN_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVDN_RANGE                    16:12
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVDN_WOFFSET                  0x0
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVDN_DEFAULT                  _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVDN_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVDN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVDN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVUP_SHIFT                    _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVUP_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVUP_RANGE                    24:20
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVUP_WOFFSET                  0x0
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVUP_DEFAULT                  _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVUP_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVUP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVUP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVDN_SLWR_SHIFT                       _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVDN_SLWR_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVDN_SLWR_RANGE                       29:28
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVDN_SLWR_WOFFSET                     0x0
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVDN_SLWR_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVDN_SLWR_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVDN_SLWR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVUP_SLWF_SHIFT                       _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVUP_SLWF_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVUP_SLWF_RANGE                       31:30
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVUP_SLWF_WOFFSET                     0x0
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVUP_SLWF_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVUP_SLWF_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVUP_SLWF_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_DAP1CFGPADCTRL_0  //        0       rw  CFG2TMC_DAP1CFG_PULLD_EN   i=0x0   // DAP1CFG pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_DAP1CFG_PULLU_EN   i=0x0   // DAP1CFG pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_DAP1CFGPADCTRL_0                    _MK_ADDR_CONST(0x884)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_WORD_COUNT                         0x1
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_RESET_VAL                  _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_RESET_MASK                         _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_READ_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_WRITE_MASK                         _MK_MASK_CONST(0xf1f1f03c)
+// DAP1CFG data pins high speed mode enable
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_HSM_EN_SHIFT                       _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_HSM_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_HSM_EN_SHIFT)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_HSM_EN_RANGE                       2:2
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_HSM_EN_WOFFSET                     0x0
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_HSM_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_HSM_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_HSM_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_HSM_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_HSM_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_HSM_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// DAP1CFG data pins schmidt enable
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_SCHMT_EN_SHIFT                     _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_SCHMT_EN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_SCHMT_EN_RANGE                     3:3
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_SCHMT_EN_WOFFSET                   0x0
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_SCHMT_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_SCHMT_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_SCHMT_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_SCHMT_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_SCHMT_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_SCHMT_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// DAP1CFG data pins low power mode select
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_LPMD_SHIFT                 _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_LPMD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_LPMD_SHIFT)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_LPMD_RANGE                 5:4
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_LPMD_WOFFSET                       0x0
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_LPMD_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_LPMD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_LPMD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_LPMD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVDN_SHIFT                    _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVDN_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVDN_RANGE                    16:12
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVDN_WOFFSET                  0x0
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVDN_DEFAULT                  _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVDN_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVDN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVDN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVUP_SHIFT                    _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVUP_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVUP_RANGE                    24:20
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVUP_WOFFSET                  0x0
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVUP_DEFAULT                  _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVUP_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVUP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVUP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVDN_SLWR_SHIFT                       _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVDN_SLWR_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVDN_SLWR_RANGE                       29:28
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVDN_SLWR_WOFFSET                     0x0
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVDN_SLWR_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVDN_SLWR_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVDN_SLWR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVUP_SLWF_SHIFT                       _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVUP_SLWF_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVUP_SLWF_RANGE                       31:30
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVUP_SLWF_WOFFSET                     0x0
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVUP_SLWF_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVUP_SLWF_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVUP_SLWF_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_DAP2CFGPADCTRL_0  //        0       rw  CFG2TMC_DAP2CFG_PULLD_EN   i=0x0   // DAP2CFG pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_DAP2CFG_PULLU_EN   i=0x0   // DAP2CFG pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_DAP2CFGPADCTRL_0                    _MK_ADDR_CONST(0x888)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_WORD_COUNT                         0x1
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_RESET_VAL                  _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_RESET_MASK                         _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_READ_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_WRITE_MASK                         _MK_MASK_CONST(0xf1f1f03c)
+// DAP2CFG data pins high speed mode enable
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_HSM_EN_SHIFT                       _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_HSM_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_HSM_EN_SHIFT)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_HSM_EN_RANGE                       2:2
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_HSM_EN_WOFFSET                     0x0
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_HSM_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_HSM_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_HSM_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_HSM_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_HSM_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_HSM_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// DAP2CFG data pins schmidt enable
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_SCHMT_EN_SHIFT                     _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_SCHMT_EN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_SCHMT_EN_RANGE                     3:3
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_SCHMT_EN_WOFFSET                   0x0
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_SCHMT_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_SCHMT_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_SCHMT_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_SCHMT_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_SCHMT_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_SCHMT_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// DAP2CFG data pins low power mode select
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_LPMD_SHIFT                 _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_LPMD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_LPMD_SHIFT)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_LPMD_RANGE                 5:4
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_LPMD_WOFFSET                       0x0
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_LPMD_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_LPMD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_LPMD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_LPMD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVDN_SHIFT                    _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVDN_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVDN_RANGE                    16:12
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVDN_WOFFSET                  0x0
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVDN_DEFAULT                  _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVDN_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVDN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVDN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVUP_SHIFT                    _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVUP_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVUP_RANGE                    24:20
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVUP_WOFFSET                  0x0
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVUP_DEFAULT                  _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVUP_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVUP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVUP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVDN_SLWR_SHIFT                       _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVDN_SLWR_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVDN_SLWR_RANGE                       29:28
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVDN_SLWR_WOFFSET                     0x0
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVDN_SLWR_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVDN_SLWR_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVDN_SLWR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVUP_SLWF_SHIFT                       _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVUP_SLWF_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVUP_SLWF_RANGE                       31:30
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVUP_SLWF_WOFFSET                     0x0
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVUP_SLWF_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVUP_SLWF_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVUP_SLWF_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_DAP3CFGPADCTRL_0  //        0       rw  CFG2TMC_DAP3CFG_PULLD_EN   i=0x0   // DAP3CFG pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_DAP3CFG_PULLU_EN   i=0x0   // DAP3CFG pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_DAP3CFGPADCTRL_0                    _MK_ADDR_CONST(0x88c)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_WORD_COUNT                         0x1
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_RESET_VAL                  _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_RESET_MASK                         _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_READ_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_WRITE_MASK                         _MK_MASK_CONST(0xf1f1f03c)
+// DAP3CFG data pins high speed mode enable
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_HSM_EN_SHIFT                       _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_HSM_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_HSM_EN_SHIFT)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_HSM_EN_RANGE                       2:2
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_HSM_EN_WOFFSET                     0x0
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_HSM_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_HSM_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_HSM_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_HSM_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_HSM_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_HSM_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// DAP3CFG data pins schmidt enable
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_SCHMT_EN_SHIFT                     _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_SCHMT_EN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_SCHMT_EN_RANGE                     3:3
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_SCHMT_EN_WOFFSET                   0x0
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_SCHMT_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_SCHMT_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_SCHMT_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_SCHMT_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_SCHMT_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_SCHMT_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// DAP3CFG data pins low power mode select
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_LPMD_SHIFT                 _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_LPMD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_LPMD_SHIFT)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_LPMD_RANGE                 5:4
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_LPMD_WOFFSET                       0x0
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_LPMD_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_LPMD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_LPMD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_LPMD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVDN_SHIFT                    _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVDN_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVDN_RANGE                    16:12
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVDN_WOFFSET                  0x0
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVDN_DEFAULT                  _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVDN_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVDN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVDN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVUP_SHIFT                    _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVUP_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVUP_RANGE                    24:20
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVUP_WOFFSET                  0x0
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVUP_DEFAULT                  _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVUP_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVUP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVUP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVDN_SLWR_SHIFT                       _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVDN_SLWR_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVDN_SLWR_RANGE                       29:28
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVDN_SLWR_WOFFSET                     0x0
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVDN_SLWR_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVDN_SLWR_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVDN_SLWR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVUP_SLWF_SHIFT                       _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVUP_SLWF_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVUP_SLWF_RANGE                       31:30
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVUP_SLWF_WOFFSET                     0x0
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVUP_SLWF_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVUP_SLWF_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVUP_SLWF_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_DAP4CFGPADCTRL_0  //        0       rw  CFG2TMC_DAP4CFG_PULLD_EN   i=0x0   // DAP4CFG pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_DAP4CFG_PULLU_EN   i=0x0   // DAP4CFG pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_DAP4CFGPADCTRL_0                    _MK_ADDR_CONST(0x890)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_WORD_COUNT                         0x1
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_RESET_VAL                  _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_RESET_MASK                         _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_READ_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_WRITE_MASK                         _MK_MASK_CONST(0xf1f1f03c)
+// DAP4CFG data pins high speed mode enable
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_HSM_EN_SHIFT                       _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_HSM_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_HSM_EN_SHIFT)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_HSM_EN_RANGE                       2:2
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_HSM_EN_WOFFSET                     0x0
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_HSM_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_HSM_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_HSM_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_HSM_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_HSM_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_HSM_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// DAP4CFG data pins schmidt enable
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_SCHMT_EN_SHIFT                     _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_SCHMT_EN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_SCHMT_EN_RANGE                     3:3
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_SCHMT_EN_WOFFSET                   0x0
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_SCHMT_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_SCHMT_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_SCHMT_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_SCHMT_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_SCHMT_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_SCHMT_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// DAP4CFG data pins low power mode select
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_LPMD_SHIFT                 _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_LPMD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_LPMD_SHIFT)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_LPMD_RANGE                 5:4
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_LPMD_WOFFSET                       0x0
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_LPMD_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_LPMD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_LPMD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_LPMD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVDN_SHIFT                    _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVDN_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVDN_RANGE                    16:12
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVDN_WOFFSET                  0x0
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVDN_DEFAULT                  _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVDN_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVDN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVDN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVUP_SHIFT                    _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVUP_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVUP_RANGE                    24:20
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVUP_WOFFSET                  0x0
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVUP_DEFAULT                  _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVUP_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVUP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVUP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVDN_SLWR_SHIFT                       _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVDN_SLWR_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVDN_SLWR_RANGE                       29:28
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVDN_SLWR_WOFFSET                     0x0
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVDN_SLWR_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVDN_SLWR_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVDN_SLWR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVUP_SLWF_SHIFT                       _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVUP_SLWF_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVUP_SLWF_RANGE                       31:30
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVUP_SLWF_WOFFSET                     0x0
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVUP_SLWF_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVUP_SLWF_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVUP_SLWF_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_DBGCFGPADCTRL_0  //        0       rw  CFG2TMC_DBGCFG_PULLD_EN   i=0x0   // DBGCFG pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_DBGCFG_PULLU_EN   i=0x0   // DBGCFG pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_DBGCFGPADCTRL_0                     _MK_ADDR_CONST(0x894)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_WORD_COUNT                  0x1
+#define APB_MISC_GP_DBGCFGPADCTRL_0_RESET_VAL                   _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_RESET_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_READ_MASK                   _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_WRITE_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+// DBGCFG data pins high speed mode enable
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_HSM_EN_SHIFT                 _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_HSM_EN_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_HSM_EN_SHIFT)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_HSM_EN_RANGE                 2:2
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_HSM_EN_WOFFSET                       0x0
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_HSM_EN_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_HSM_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_HSM_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_HSM_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_HSM_EN_DISABLE                       _MK_ENUM_CONST(0)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_HSM_EN_ENABLE                        _MK_ENUM_CONST(1)
+
+// DBGCFG data pins schmidt enable
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_SCHMT_EN_SHIFT                       _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_SCHMT_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_SCHMT_EN_RANGE                       3:3
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_SCHMT_EN_WOFFSET                     0x0
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_SCHMT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_SCHMT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_SCHMT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_SCHMT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_SCHMT_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_SCHMT_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// DBGCFG data pins low power mode select
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_LPMD_SHIFT                   _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_LPMD_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_LPMD_SHIFT)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_LPMD_RANGE                   5:4
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_LPMD_WOFFSET                 0x0
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_LPMD_DEFAULT                 _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_LPMD_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_LPMD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_LPMD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVDN_SHIFT                      _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVDN_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVDN_RANGE                      16:12
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVDN_WOFFSET                    0x0
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVDN_DEFAULT                    _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVDN_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVDN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVDN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVUP_SHIFT                      _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVUP_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVUP_RANGE                      24:20
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVUP_WOFFSET                    0x0
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVUP_DEFAULT                    _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVUP_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVUP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVUP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVDN_SLWR_SHIFT                 _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVDN_SLWR_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVDN_SLWR_RANGE                 29:28
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVDN_SLWR_WOFFSET                       0x0
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVDN_SLWR_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVDN_SLWR_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVDN_SLWR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVUP_SLWF_SHIFT                 _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVUP_SLWF_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVUP_SLWF_RANGE                 31:30
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVUP_SLWF_WOFFSET                       0x0
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVUP_SLWF_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVUP_SLWF_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVUP_SLWF_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_LCDCFG1PADCTRL_0  //        0       rw  CFG2TMC_LCDCFG1_PULLD_EN   i=0x0   // LCDCFG1 pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_LCDCFG1_PULLU_EN   i=0x0   // LCDCFG1 pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_LCDCFG1PADCTRL_0                    _MK_ADDR_CONST(0x898)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_WORD_COUNT                         0x1
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_RESET_VAL                  _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_RESET_MASK                         _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_READ_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_WRITE_MASK                         _MK_MASK_CONST(0xf1f1f03c)
+// LCDCFG1 data pins high speed mode enable
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_HSM_EN_SHIFT                       _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_HSM_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_HSM_EN_SHIFT)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_HSM_EN_RANGE                       2:2
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_HSM_EN_WOFFSET                     0x0
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_HSM_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_HSM_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_HSM_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_HSM_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_HSM_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_HSM_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// LCDCFG1 data pins schmidt enable
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_SCHMT_EN_SHIFT                     _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_SCHMT_EN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_SCHMT_EN_RANGE                     3:3
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_SCHMT_EN_WOFFSET                   0x0
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_SCHMT_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_SCHMT_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_SCHMT_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_SCHMT_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_SCHMT_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_SCHMT_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// LCDCFG1 data pins low power mode select
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_LPMD_SHIFT                 _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_LPMD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_LPMD_SHIFT)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_LPMD_RANGE                 5:4
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_LPMD_WOFFSET                       0x0
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_LPMD_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_LPMD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_LPMD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_LPMD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVDN_SHIFT                    _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVDN_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVDN_RANGE                    16:12
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVDN_WOFFSET                  0x0
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVDN_DEFAULT                  _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVDN_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVDN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVDN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVUP_SHIFT                    _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVUP_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVUP_RANGE                    24:20
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVUP_WOFFSET                  0x0
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVUP_DEFAULT                  _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVUP_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVUP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVUP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVDN_SLWR_SHIFT                       _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVDN_SLWR_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVDN_SLWR_RANGE                       29:28
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVDN_SLWR_WOFFSET                     0x0
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVDN_SLWR_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVDN_SLWR_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVDN_SLWR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVUP_SLWF_SHIFT                       _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVUP_SLWF_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVUP_SLWF_RANGE                       31:30
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVUP_SLWF_WOFFSET                     0x0
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVUP_SLWF_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVUP_SLWF_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVUP_SLWF_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_LCDCFG2PADCTRL_0  //        0       rw  CFG2TMC_LCDCFG2_PULLD_EN   i=0x0   // LCDCFG2 pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_LCDCFG2_PULLU_EN   i=0x0   // LCDCFG2 pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_LCDCFG2PADCTRL_0                    _MK_ADDR_CONST(0x89c)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_WORD_COUNT                         0x1
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_RESET_VAL                  _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_RESET_MASK                         _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_READ_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_WRITE_MASK                         _MK_MASK_CONST(0xf1f1f03c)
+// LCDCFG2 data pins high speed mode enable
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_HSM_EN_SHIFT                       _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_HSM_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_HSM_EN_SHIFT)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_HSM_EN_RANGE                       2:2
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_HSM_EN_WOFFSET                     0x0
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_HSM_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_HSM_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_HSM_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_HSM_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_HSM_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_HSM_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// LCDCFG2 data pins schmidt enable
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_SCHMT_EN_SHIFT                     _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_SCHMT_EN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_SCHMT_EN_RANGE                     3:3
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_SCHMT_EN_WOFFSET                   0x0
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_SCHMT_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_SCHMT_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_SCHMT_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_SCHMT_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_SCHMT_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_SCHMT_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// LCDCFG2 data pins low power mode select
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_LPMD_SHIFT                 _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_LPMD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_LPMD_SHIFT)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_LPMD_RANGE                 5:4
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_LPMD_WOFFSET                       0x0
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_LPMD_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_LPMD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_LPMD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_LPMD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVDN_SHIFT                    _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVDN_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVDN_RANGE                    16:12
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVDN_WOFFSET                  0x0
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVDN_DEFAULT                  _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVDN_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVDN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVDN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVUP_SHIFT                    _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVUP_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVUP_RANGE                    24:20
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVUP_WOFFSET                  0x0
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVUP_DEFAULT                  _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVUP_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVUP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVUP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVDN_SLWR_SHIFT                       _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVDN_SLWR_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVDN_SLWR_RANGE                       29:28
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVDN_SLWR_WOFFSET                     0x0
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVDN_SLWR_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVDN_SLWR_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVDN_SLWR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVUP_SLWF_SHIFT                       _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVUP_SLWF_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVUP_SLWF_RANGE                       31:30
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVUP_SLWF_WOFFSET                     0x0
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVUP_SLWF_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVUP_SLWF_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVUP_SLWF_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_SDIO2CFGPADCTRL_0  //        0       rw  CFG2TMC_SDIO2CFG_PULLD_EN   i=0x0   // SDIO2CFG pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_SDIO2CFG_PULLU_EN   i=0x0   // SDIO2CFG pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0                   _MK_ADDR_CONST(0x8a0)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_WORD_COUNT                        0x1
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_RESET_VAL                         _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_RESET_MASK                        _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_READ_MASK                         _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_WRITE_MASK                        _MK_MASK_CONST(0xf1f1f03c)
+// SDIO2CFG data pins high speed mode enable
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_HSM_EN_SHIFT                     _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_HSM_EN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_HSM_EN_SHIFT)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_HSM_EN_RANGE                     2:2
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_HSM_EN_WOFFSET                   0x0
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_HSM_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_HSM_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_HSM_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_HSM_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_HSM_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_HSM_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// SDIO2CFG data pins schmidt enable
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_SCHMT_EN_SHIFT                   _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_SCHMT_EN_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_SCHMT_EN_RANGE                   3:3
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_SCHMT_EN_WOFFSET                 0x0
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_SCHMT_EN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_SCHMT_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_SCHMT_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_SCHMT_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_SCHMT_EN_DISABLE                 _MK_ENUM_CONST(0)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_SCHMT_EN_ENABLE                  _MK_ENUM_CONST(1)
+
+// SDIO2CFG data pins low power mode select
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_LPMD_SHIFT                       _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_LPMD_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_LPMD_SHIFT)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_LPMD_RANGE                       5:4
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_LPMD_WOFFSET                     0x0
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_LPMD_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_LPMD_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_LPMD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_LPMD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVDN_SHIFT                  _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVDN_FIELD                  (_MK_MASK_CONST(0x1f) << APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVDN_RANGE                  16:12
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVDN_WOFFSET                        0x0
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVDN_DEFAULT                        _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVDN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVDN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVDN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVUP_SHIFT                  _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVUP_FIELD                  (_MK_MASK_CONST(0x1f) << APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVUP_RANGE                  24:20
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVUP_WOFFSET                        0x0
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVUP_DEFAULT                        _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVUP_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVUP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVUP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVDN_SLWR_SHIFT                     _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVDN_SLWR_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVDN_SLWR_RANGE                     29:28
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVDN_SLWR_WOFFSET                   0x0
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVDN_SLWR_DEFAULT                   _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVDN_SLWR_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVDN_SLWR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVUP_SLWF_SHIFT                     _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVUP_SLWF_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVUP_SLWF_RANGE                     31:30
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVUP_SLWF_WOFFSET                   0x0
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVUP_SLWF_DEFAULT                   _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVUP_SLWF_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVUP_SLWF_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_SDIO3CFGPADCTRL_0  //        0       rw  CFG2TMC_SDIO3CFG_PULLD_EN   i=0x0   // SDIO3CFG pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_SDIO3CFG_PULLU_EN   i=0x0   // SDIO3CFG pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0                   _MK_ADDR_CONST(0x8a4)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_WORD_COUNT                        0x1
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_RESET_VAL                         _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_RESET_MASK                        _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_READ_MASK                         _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_WRITE_MASK                        _MK_MASK_CONST(0xf1f1f03c)
+// SDIO3CFG data pins high speed mode enable
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_HSM_EN_SHIFT                     _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_HSM_EN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_HSM_EN_SHIFT)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_HSM_EN_RANGE                     2:2
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_HSM_EN_WOFFSET                   0x0
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_HSM_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_HSM_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_HSM_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_HSM_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_HSM_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_HSM_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// SDIO3CFG data pins schmidt enable
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_SCHMT_EN_SHIFT                   _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_SCHMT_EN_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_SCHMT_EN_RANGE                   3:3
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_SCHMT_EN_WOFFSET                 0x0
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_SCHMT_EN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_SCHMT_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_SCHMT_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_SCHMT_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_SCHMT_EN_DISABLE                 _MK_ENUM_CONST(0)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_SCHMT_EN_ENABLE                  _MK_ENUM_CONST(1)
+
+// SDIO3CFG data pins low power mode select
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_LPMD_SHIFT                       _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_LPMD_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_LPMD_SHIFT)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_LPMD_RANGE                       5:4
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_LPMD_WOFFSET                     0x0
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_LPMD_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_LPMD_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_LPMD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_LPMD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVDN_SHIFT                  _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVDN_FIELD                  (_MK_MASK_CONST(0x1f) << APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVDN_RANGE                  16:12
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVDN_WOFFSET                        0x0
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVDN_DEFAULT                        _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVDN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVDN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVDN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVUP_SHIFT                  _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVUP_FIELD                  (_MK_MASK_CONST(0x1f) << APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVUP_RANGE                  24:20
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVUP_WOFFSET                        0x0
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVUP_DEFAULT                        _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVUP_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVUP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVUP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVDN_SLWR_SHIFT                     _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVDN_SLWR_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVDN_SLWR_RANGE                     29:28
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVDN_SLWR_WOFFSET                   0x0
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVDN_SLWR_DEFAULT                   _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVDN_SLWR_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVDN_SLWR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVUP_SLWF_SHIFT                     _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVUP_SLWF_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVUP_SLWF_RANGE                     31:30
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVUP_SLWF_WOFFSET                   0x0
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVUP_SLWF_DEFAULT                   _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVUP_SLWF_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVUP_SLWF_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_SPICFGPADCTRL_0  //        0       rw  CFG2TMC_SPICFG_PULLD_EN   i=0x0   // SPICFG pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_SPICFG_PULLU_EN   i=0x0   // SPICFG pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_SPICFGPADCTRL_0                     _MK_ADDR_CONST(0x8a8)
+#define APB_MISC_GP_SPICFGPADCTRL_0_WORD_COUNT                  0x1
+#define APB_MISC_GP_SPICFGPADCTRL_0_RESET_VAL                   _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_SPICFGPADCTRL_0_RESET_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_SPICFGPADCTRL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SPICFGPADCTRL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SPICFGPADCTRL_0_READ_MASK                   _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_SPICFGPADCTRL_0_WRITE_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+// SPICFG data pins high speed mode enable
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_HSM_EN_SHIFT                 _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_HSM_EN_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_HSM_EN_SHIFT)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_HSM_EN_RANGE                 2:2
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_HSM_EN_WOFFSET                       0x0
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_HSM_EN_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_HSM_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_HSM_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_HSM_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_HSM_EN_DISABLE                       _MK_ENUM_CONST(0)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_HSM_EN_ENABLE                        _MK_ENUM_CONST(1)
+
+// SPICFG data pins schmidt enable
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_SCHMT_EN_SHIFT                       _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_SCHMT_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_SCHMT_EN_RANGE                       3:3
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_SCHMT_EN_WOFFSET                     0x0
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_SCHMT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_SCHMT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_SCHMT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_SCHMT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_SCHMT_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_SCHMT_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// SPICFG data pins low power mode select
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_LPMD_SHIFT                   _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_LPMD_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_LPMD_SHIFT)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_LPMD_RANGE                   5:4
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_LPMD_WOFFSET                 0x0
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_LPMD_DEFAULT                 _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_LPMD_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_LPMD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_LPMD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVDN_SHIFT                      _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVDN_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVDN_RANGE                      16:12
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVDN_WOFFSET                    0x0
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVDN_DEFAULT                    _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVDN_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVDN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVDN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVUP_SHIFT                      _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVUP_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVUP_RANGE                      24:20
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVUP_WOFFSET                    0x0
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVUP_DEFAULT                    _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVUP_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVUP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVUP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVDN_SLWR_SHIFT                 _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVDN_SLWR_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVDN_SLWR_RANGE                 29:28
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVDN_SLWR_WOFFSET                       0x0
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVDN_SLWR_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVDN_SLWR_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVDN_SLWR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVUP_SLWF_SHIFT                 _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVUP_SLWF_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVUP_SLWF_RANGE                 31:30
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVUP_SLWF_WOFFSET                       0x0
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVUP_SLWF_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVUP_SLWF_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVUP_SLWF_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_UAACFGPADCTRL_0  //        0       rw  CFG2TMC_UAACFG_PULLD_EN   i=0x0   // UAACFG pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_UAACFG_PULLU_EN   i=0x0   // UAACFG pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_UAACFGPADCTRL_0                     _MK_ADDR_CONST(0x8ac)
+#define APB_MISC_GP_UAACFGPADCTRL_0_WORD_COUNT                  0x1
+#define APB_MISC_GP_UAACFGPADCTRL_0_RESET_VAL                   _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_UAACFGPADCTRL_0_RESET_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_UAACFGPADCTRL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UAACFGPADCTRL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UAACFGPADCTRL_0_READ_MASK                   _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_UAACFGPADCTRL_0_WRITE_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+// UAACFG data pins high speed mode enable
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_HSM_EN_SHIFT                 _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_HSM_EN_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_HSM_EN_SHIFT)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_HSM_EN_RANGE                 2:2
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_HSM_EN_WOFFSET                       0x0
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_HSM_EN_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_HSM_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_HSM_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_HSM_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_HSM_EN_DISABLE                       _MK_ENUM_CONST(0)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_HSM_EN_ENABLE                        _MK_ENUM_CONST(1)
+
+// UAACFG data pins schmidt enable
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_SCHMT_EN_SHIFT                       _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_SCHMT_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_SCHMT_EN_RANGE                       3:3
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_SCHMT_EN_WOFFSET                     0x0
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_SCHMT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_SCHMT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_SCHMT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_SCHMT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_SCHMT_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_SCHMT_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// UAACFG data pins low power mode select
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_LPMD_SHIFT                   _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_LPMD_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_LPMD_SHIFT)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_LPMD_RANGE                   5:4
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_LPMD_WOFFSET                 0x0
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_LPMD_DEFAULT                 _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_LPMD_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_LPMD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_LPMD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVDN_SHIFT                      _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVDN_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVDN_RANGE                      16:12
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVDN_WOFFSET                    0x0
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVDN_DEFAULT                    _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVDN_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVDN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVDN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVUP_SHIFT                      _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVUP_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVUP_RANGE                      24:20
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVUP_WOFFSET                    0x0
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVUP_DEFAULT                    _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVUP_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVUP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVUP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVDN_SLWR_SHIFT                 _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVDN_SLWR_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVDN_SLWR_RANGE                 29:28
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVDN_SLWR_WOFFSET                       0x0
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVDN_SLWR_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVDN_SLWR_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVDN_SLWR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVUP_SLWF_SHIFT                 _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVUP_SLWF_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVUP_SLWF_RANGE                 31:30
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVUP_SLWF_WOFFSET                       0x0
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVUP_SLWF_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVUP_SLWF_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVUP_SLWF_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_UABCFGPADCTRL_0  //        0       rw  CFG2TMC_UABCFG_PULLD_EN   i=0x0   // UABCFG pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_UABCFG_PULLU_EN   i=0x0   // UABCFG pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_UABCFGPADCTRL_0                     _MK_ADDR_CONST(0x8b0)
+#define APB_MISC_GP_UABCFGPADCTRL_0_WORD_COUNT                  0x1
+#define APB_MISC_GP_UABCFGPADCTRL_0_RESET_VAL                   _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_UABCFGPADCTRL_0_RESET_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_UABCFGPADCTRL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UABCFGPADCTRL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UABCFGPADCTRL_0_READ_MASK                   _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_UABCFGPADCTRL_0_WRITE_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+// UABCFG data pins high speed mode enable
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_HSM_EN_SHIFT                 _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_HSM_EN_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_HSM_EN_SHIFT)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_HSM_EN_RANGE                 2:2
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_HSM_EN_WOFFSET                       0x0
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_HSM_EN_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_HSM_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_HSM_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_HSM_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_HSM_EN_DISABLE                       _MK_ENUM_CONST(0)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_HSM_EN_ENABLE                        _MK_ENUM_CONST(1)
+
+// UABCFG data pins schmidt enable
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_SCHMT_EN_SHIFT                       _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_SCHMT_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_SCHMT_EN_RANGE                       3:3
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_SCHMT_EN_WOFFSET                     0x0
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_SCHMT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_SCHMT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_SCHMT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_SCHMT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_SCHMT_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_SCHMT_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// UABCFG data pins low power mode select
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_LPMD_SHIFT                   _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_LPMD_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_LPMD_SHIFT)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_LPMD_RANGE                   5:4
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_LPMD_WOFFSET                 0x0
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_LPMD_DEFAULT                 _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_LPMD_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_LPMD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_LPMD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVDN_SHIFT                      _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVDN_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVDN_RANGE                      16:12
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVDN_WOFFSET                    0x0
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVDN_DEFAULT                    _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVDN_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVDN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVDN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVUP_SHIFT                      _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVUP_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVUP_RANGE                      24:20
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVUP_WOFFSET                    0x0
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVUP_DEFAULT                    _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVUP_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVUP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVUP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVDN_SLWR_SHIFT                 _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVDN_SLWR_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVDN_SLWR_RANGE                 29:28
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVDN_SLWR_WOFFSET                       0x0
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVDN_SLWR_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVDN_SLWR_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVDN_SLWR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVUP_SLWF_SHIFT                 _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVUP_SLWF_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVUP_SLWF_RANGE                 31:30
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVUP_SLWF_WOFFSET                       0x0
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVUP_SLWF_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVUP_SLWF_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVUP_SLWF_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_UART2CFGPADCTRL_0  //        0       rw  CFG2TMC_UART2CFG_PULLD_EN   i=0x0   // UART2CFG pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_UART2CFG_PULLU_EN   i=0x0   // UART2CFG pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_UART2CFGPADCTRL_0                   _MK_ADDR_CONST(0x8b4)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_WORD_COUNT                        0x1
+#define APB_MISC_GP_UART2CFGPADCTRL_0_RESET_VAL                         _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_RESET_MASK                        _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_READ_MASK                         _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_WRITE_MASK                        _MK_MASK_CONST(0xf1f1f03c)
+// UART2CFG data pins high speed mode enable
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_HSM_EN_SHIFT                     _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_HSM_EN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_HSM_EN_SHIFT)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_HSM_EN_RANGE                     2:2
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_HSM_EN_WOFFSET                   0x0
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_HSM_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_HSM_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_HSM_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_HSM_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_HSM_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_HSM_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// UART2CFG data pins schmidt enable
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_SCHMT_EN_SHIFT                   _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_SCHMT_EN_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_SCHMT_EN_RANGE                   3:3
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_SCHMT_EN_WOFFSET                 0x0
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_SCHMT_EN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_SCHMT_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_SCHMT_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_SCHMT_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_SCHMT_EN_DISABLE                 _MK_ENUM_CONST(0)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_SCHMT_EN_ENABLE                  _MK_ENUM_CONST(1)
+
+// UART2CFG data pins low power mode select
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_LPMD_SHIFT                       _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_LPMD_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_LPMD_SHIFT)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_LPMD_RANGE                       5:4
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_LPMD_WOFFSET                     0x0
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_LPMD_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_LPMD_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_LPMD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_LPMD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVDN_SHIFT                  _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVDN_FIELD                  (_MK_MASK_CONST(0x1f) << APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVDN_RANGE                  16:12
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVDN_WOFFSET                        0x0
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVDN_DEFAULT                        _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVDN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVDN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVDN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVUP_SHIFT                  _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVUP_FIELD                  (_MK_MASK_CONST(0x1f) << APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVUP_RANGE                  24:20
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVUP_WOFFSET                        0x0
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVUP_DEFAULT                        _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVUP_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVUP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVUP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVDN_SLWR_SHIFT                     _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVDN_SLWR_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVDN_SLWR_RANGE                     29:28
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVDN_SLWR_WOFFSET                   0x0
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVDN_SLWR_DEFAULT                   _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVDN_SLWR_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVDN_SLWR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVUP_SLWF_SHIFT                     _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVUP_SLWF_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVUP_SLWF_RANGE                     31:30
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVUP_SLWF_WOFFSET                   0x0
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVUP_SLWF_DEFAULT                   _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVUP_SLWF_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVUP_SLWF_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_UART3CFGPADCTRL_0  //        0       rw  CFG2TMC_UART3CFG_PULLD_EN   i=0x0   // UART3CFG pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_UART3CFG_PULLU_EN   i=0x0   // UART3CFG pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_UART3CFGPADCTRL_0                   _MK_ADDR_CONST(0x8b8)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_WORD_COUNT                        0x1
+#define APB_MISC_GP_UART3CFGPADCTRL_0_RESET_VAL                         _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_RESET_MASK                        _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_READ_MASK                         _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_WRITE_MASK                        _MK_MASK_CONST(0xf1f1f03c)
+// UART3CFG data pins high speed mode enable
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_HSM_EN_SHIFT                     _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_HSM_EN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_HSM_EN_SHIFT)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_HSM_EN_RANGE                     2:2
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_HSM_EN_WOFFSET                   0x0
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_HSM_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_HSM_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_HSM_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_HSM_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_HSM_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_HSM_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// UART3CFG data pins schmidt enable
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_SCHMT_EN_SHIFT                   _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_SCHMT_EN_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_SCHMT_EN_RANGE                   3:3
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_SCHMT_EN_WOFFSET                 0x0
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_SCHMT_EN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_SCHMT_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_SCHMT_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_SCHMT_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_SCHMT_EN_DISABLE                 _MK_ENUM_CONST(0)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_SCHMT_EN_ENABLE                  _MK_ENUM_CONST(1)
+
+// UART3CFG data pins low power mode select
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_LPMD_SHIFT                       _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_LPMD_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_LPMD_SHIFT)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_LPMD_RANGE                       5:4
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_LPMD_WOFFSET                     0x0
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_LPMD_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_LPMD_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_LPMD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_LPMD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVDN_SHIFT                  _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVDN_FIELD                  (_MK_MASK_CONST(0x1f) << APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVDN_RANGE                  16:12
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVDN_WOFFSET                        0x0
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVDN_DEFAULT                        _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVDN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVDN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVDN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVUP_SHIFT                  _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVUP_FIELD                  (_MK_MASK_CONST(0x1f) << APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVUP_RANGE                  24:20
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVUP_WOFFSET                        0x0
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVUP_DEFAULT                        _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVUP_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVUP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVUP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVDN_SLWR_SHIFT                     _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVDN_SLWR_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVDN_SLWR_RANGE                     29:28
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVDN_SLWR_WOFFSET                   0x0
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVDN_SLWR_DEFAULT                   _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVDN_SLWR_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVDN_SLWR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVUP_SLWF_SHIFT                     _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVUP_SLWF_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVUP_SLWF_RANGE                     31:30
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVUP_SLWF_WOFFSET                   0x0
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVUP_SLWF_DEFAULT                   _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVUP_SLWF_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVUP_SLWF_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_VICFG1PADCTRL_0  //        0       rw  CFG2TMC_VICFG1_PULLD_EN   i=0x0   // VICFG1 pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_VICFG1_PULLU_EN   i=0x0   // VICFG1 pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_VICFG1PADCTRL_0                     _MK_ADDR_CONST(0x8bc)
+#define APB_MISC_GP_VICFG1PADCTRL_0_WORD_COUNT                  0x1
+#define APB_MISC_GP_VICFG1PADCTRL_0_RESET_VAL                   _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_VICFG1PADCTRL_0_RESET_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_VICFG1PADCTRL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG1PADCTRL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG1PADCTRL_0_READ_MASK                   _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_VICFG1PADCTRL_0_WRITE_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+// VICFG1 data pins high speed mode enable
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_HSM_EN_SHIFT                 _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_HSM_EN_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_HSM_EN_SHIFT)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_HSM_EN_RANGE                 2:2
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_HSM_EN_WOFFSET                       0x0
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_HSM_EN_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_HSM_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_HSM_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_HSM_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_HSM_EN_DISABLE                       _MK_ENUM_CONST(0)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_HSM_EN_ENABLE                        _MK_ENUM_CONST(1)
+
+// VICFG1 data pins schmidt enable
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_SCHMT_EN_SHIFT                       _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_SCHMT_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_SCHMT_EN_RANGE                       3:3
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_SCHMT_EN_WOFFSET                     0x0
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_SCHMT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_SCHMT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_SCHMT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_SCHMT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_SCHMT_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_SCHMT_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// VICFG1 data pins low power mode select
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_LPMD_SHIFT                   _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_LPMD_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_LPMD_SHIFT)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_LPMD_RANGE                   5:4
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_LPMD_WOFFSET                 0x0
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_LPMD_DEFAULT                 _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_LPMD_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_LPMD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_LPMD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVDN_SHIFT                      _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVDN_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVDN_RANGE                      16:12
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVDN_WOFFSET                    0x0
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVDN_DEFAULT                    _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVDN_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVDN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVDN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVUP_SHIFT                      _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVUP_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVUP_RANGE                      24:20
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVUP_WOFFSET                    0x0
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVUP_DEFAULT                    _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVUP_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVUP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVUP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVDN_SLWR_SHIFT                 _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVDN_SLWR_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVDN_SLWR_RANGE                 29:28
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVDN_SLWR_WOFFSET                       0x0
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVDN_SLWR_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVDN_SLWR_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVDN_SLWR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVUP_SLWF_SHIFT                 _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVUP_SLWF_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVUP_SLWF_RANGE                 31:30
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVUP_SLWF_WOFFSET                       0x0
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVUP_SLWF_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVUP_SLWF_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVUP_SLWF_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_VICFG2PADCTRL_0  //        0       rw  CFG2TMC_VICFG2_PULLD_EN   i=0x0   // VICFG2 pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_VICFG2_PULLU_EN   i=0x0   // VICFG2 pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_VICFG2PADCTRL_0                     _MK_ADDR_CONST(0x8c0)
+#define APB_MISC_GP_VICFG2PADCTRL_0_WORD_COUNT                  0x1
+#define APB_MISC_GP_VICFG2PADCTRL_0_RESET_VAL                   _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_VICFG2PADCTRL_0_RESET_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_VICFG2PADCTRL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG2PADCTRL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG2PADCTRL_0_READ_MASK                   _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_VICFG2PADCTRL_0_WRITE_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+// VICFG2 data pins high speed mode enable
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_HSM_EN_SHIFT                 _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_HSM_EN_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_HSM_EN_SHIFT)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_HSM_EN_RANGE                 2:2
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_HSM_EN_WOFFSET                       0x0
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_HSM_EN_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_HSM_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_HSM_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_HSM_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_HSM_EN_DISABLE                       _MK_ENUM_CONST(0)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_HSM_EN_ENABLE                        _MK_ENUM_CONST(1)
+
+// VICFG2 data pins schmidt enable
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_SCHMT_EN_SHIFT                       _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_SCHMT_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_SCHMT_EN_RANGE                       3:3
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_SCHMT_EN_WOFFSET                     0x0
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_SCHMT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_SCHMT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_SCHMT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_SCHMT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_SCHMT_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_SCHMT_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// VICFG2 data pins low power mode select
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_LPMD_SHIFT                   _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_LPMD_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_LPMD_SHIFT)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_LPMD_RANGE                   5:4
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_LPMD_WOFFSET                 0x0
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_LPMD_DEFAULT                 _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_LPMD_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_LPMD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_LPMD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVDN_SHIFT                      _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVDN_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVDN_RANGE                      16:12
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVDN_WOFFSET                    0x0
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVDN_DEFAULT                    _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVDN_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVDN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVDN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVUP_SHIFT                      _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVUP_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVUP_RANGE                      24:20
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVUP_WOFFSET                    0x0
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVUP_DEFAULT                    _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVUP_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVUP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVUP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVDN_SLWR_SHIFT                 _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVDN_SLWR_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVDN_SLWR_RANGE                 29:28
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVDN_SLWR_WOFFSET                       0x0
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVDN_SLWR_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVDN_SLWR_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVDN_SLWR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVUP_SLWF_SHIFT                 _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVUP_SLWF_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVUP_SLWF_RANGE                 31:30
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVUP_SLWF_WOFFSET                       0x0
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVUP_SLWF_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVUP_SLWF_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVUP_SLWF_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_XM2CFGAPADCTRL_0  //        0       rw  CFG2TMC_XM2CFGA_PULLD_EN   i=0x0 // XM2CFGA pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_XM2CFGA_PULLU_EN i=0x0   // XM2CFGA pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_XM2CFGAPADCTRL_0                    _MK_ADDR_CONST(0x8c4)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_WORD_COUNT                         0x1
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_RESET_VAL                  _MK_MASK_CONST(0xf1f1f030)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_RESET_MASK                         _MK_MASK_CONST(0xf1f1f074)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_READ_MASK                  _MK_MASK_CONST(0xf1f1f074)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_WRITE_MASK                         _MK_MASK_CONST(0xf1f1f074)
+// XM2CFGA data pins high speed mode enable        3       rw  CFG2TMC_XM2CFGA_SCHMT_EN i=0x0   // XM2CFGA data pins schmidt enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_HSM_EN_SHIFT                       _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_HSM_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_HSM_EN_SHIFT)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_HSM_EN_RANGE                       2:2
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_HSM_EN_WOFFSET                     0x0
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_HSM_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_HSM_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_HSM_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_HSM_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_HSM_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_HSM_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// XM2CFGA data pins low power mode select
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_LPMD_SHIFT                 _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_LPMD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_LPMD_SHIFT)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_LPMD_RANGE                 5:4
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_LPMD_WOFFSET                       0x0
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_LPMD_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_LPMD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_LPMD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_LPMD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// XM2CFGA data pins vref enable
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_VREF_EN_SHIFT                      _MK_SHIFT_CONST(6)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_VREF_EN_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_VREF_EN_SHIFT)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_VREF_EN_RANGE                      6:6
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_VREF_EN_WOFFSET                    0x0
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_VREF_EN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_VREF_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_VREF_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_VREF_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_VREF_EN_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_VREF_EN_ENABLE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVDN_SHIFT                    _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVDN_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVDN_RANGE                    16:12
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVDN_WOFFSET                  0x0
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVDN_DEFAULT                  _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVDN_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVDN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVDN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVUP_SHIFT                    _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVUP_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVUP_RANGE                    24:20
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVUP_WOFFSET                  0x0
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVUP_DEFAULT                  _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVUP_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVUP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVUP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVDN_SLWR_SHIFT                       _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVDN_SLWR_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVDN_SLWR_RANGE                       29:28
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVDN_SLWR_WOFFSET                     0x0
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVDN_SLWR_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVDN_SLWR_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVDN_SLWR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVUP_SLWF_SHIFT                       _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVUP_SLWF_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVUP_SLWF_RANGE                       31:30
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVUP_SLWF_WOFFSET                     0x0
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVUP_SLWF_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVUP_SLWF_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVUP_SLWF_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_XM2CFGCPADCTRL_0  //        0       rw  CFG2TMC_XM2CFGC_PULLD_EN   i=0x0   // XM2CFGC pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_XM2CFGC_PULLU_EN   i=0x0   // XM2CFGC pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_XM2CFGCPADCTRL_0                    _MK_ADDR_CONST(0x8c8)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_WORD_COUNT                         0x1
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_RESET_VAL                  _MK_MASK_CONST(0xf1f1f030)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_RESET_MASK                         _MK_MASK_CONST(0xf1f1f07c)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_READ_MASK                  _MK_MASK_CONST(0xf1f1f07c)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_WRITE_MASK                         _MK_MASK_CONST(0xf1f1f07c)
+// XM2CFGC data pins high speed mode enable
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_HSM_EN_SHIFT                       _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_HSM_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_HSM_EN_SHIFT)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_HSM_EN_RANGE                       2:2
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_HSM_EN_WOFFSET                     0x0
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_HSM_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_HSM_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_HSM_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_HSM_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_HSM_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_HSM_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// XM2CFGC data pins schmidt enable
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_SCHMT_EN_SHIFT                     _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_SCHMT_EN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_SCHMT_EN_RANGE                     3:3
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_SCHMT_EN_WOFFSET                   0x0
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_SCHMT_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_SCHMT_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_SCHMT_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_SCHMT_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_SCHMT_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_SCHMT_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// XM2CFGC data pins low power mode select
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_LPMD_SHIFT                 _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_LPMD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_LPMD_SHIFT)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_LPMD_RANGE                 5:4
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_LPMD_WOFFSET                       0x0
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_LPMD_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_LPMD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_LPMD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_LPMD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// XM2CFGC data pins vref enable
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_VREF_EN_SHIFT                      _MK_SHIFT_CONST(6)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_VREF_EN_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_VREF_EN_SHIFT)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_VREF_EN_RANGE                      6:6
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_VREF_EN_WOFFSET                    0x0
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_VREF_EN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_VREF_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_VREF_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_VREF_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_VREF_EN_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_VREF_EN_ENABLE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_SHIFT                    _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_RANGE                    16:12
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_WOFFSET                  0x0
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_DEFAULT                  _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_SHIFT                    _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_RANGE                    24:20
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_WOFFSET                  0x0
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_DEFAULT                  _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_SLWR_SHIFT                       _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_SLWR_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_SLWR_RANGE                       29:28
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_SLWR_WOFFSET                     0x0
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_SLWR_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_SLWR_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_SLWR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_SLWF_SHIFT                       _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_SLWF_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_SLWF_RANGE                       31:30
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_SLWF_WOFFSET                     0x0
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_SLWF_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_SLWF_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_SLWF_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_XM2CFGDPADCTRL_0  //        0       rw  CFG2TMC_XM2CFGD_PULLD_EN   i=0x0   // XM2CFGD pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_XM2CFGD_PULLU_EN   i=0x0   // XM2CFGD pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_XM2CFGDPADCTRL_0                    _MK_ADDR_CONST(0x8cc)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_WORD_COUNT                         0x1
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_RESET_VAL                  _MK_MASK_CONST(0xf1f1f030)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_RESET_MASK                         _MK_MASK_CONST(0xf1f1f07c)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_READ_MASK                  _MK_MASK_CONST(0xf1f1f07c)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_WRITE_MASK                         _MK_MASK_CONST(0xf1f1f07c)
+// XM2CFGD data pins high speed mode enable
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_HSM_EN_SHIFT                       _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_HSM_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_HSM_EN_SHIFT)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_HSM_EN_RANGE                       2:2
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_HSM_EN_WOFFSET                     0x0
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_HSM_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_HSM_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_HSM_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_HSM_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_HSM_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_HSM_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// XM2CFGD data pins schmidt enable
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_SCHMT_EN_SHIFT                     _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_SCHMT_EN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_SCHMT_EN_RANGE                     3:3
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_SCHMT_EN_WOFFSET                   0x0
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_SCHMT_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_SCHMT_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_SCHMT_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_SCHMT_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_SCHMT_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_SCHMT_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// XM2CFGD data pins low power mode select
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_LPMD_SHIFT                 _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_LPMD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_LPMD_SHIFT)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_LPMD_RANGE                 5:4
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_LPMD_WOFFSET                       0x0
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_LPMD_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_LPMD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_LPMD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_LPMD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// XM2CFGD data pins vref enable
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_VREF_EN_SHIFT                      _MK_SHIFT_CONST(6)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_VREF_EN_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_VREF_EN_SHIFT)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_VREF_EN_RANGE                      6:6
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_VREF_EN_WOFFSET                    0x0
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_VREF_EN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_VREF_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_VREF_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_VREF_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_VREF_EN_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_VREF_EN_ENABLE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_SHIFT                    _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_RANGE                    16:12
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_WOFFSET                  0x0
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_DEFAULT                  _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_SHIFT                    _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_RANGE                    24:20
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_WOFFSET                  0x0
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_DEFAULT                  _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_SLWR_SHIFT                       _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_SLWR_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_SLWR_RANGE                       29:28
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_SLWR_WOFFSET                     0x0
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_SLWR_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_SLWR_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_SLWR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_SLWF_SHIFT                       _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_SLWF_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_SLWF_RANGE                       31:30
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_SLWF_WOFFSET                     0x0
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_SLWF_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_SLWF_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_SLWF_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_XM2CLKCFGPADCTRL_0  //        0       rw  CFG2TMC_XM2CLKCFG_PULLD_EN   i=0x0   // XM2CLKCFG pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_XM2CLKCFG_PULLU_EN   i=0x0   // XM2CLKCFG pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0                  _MK_ADDR_CONST(0x8d0)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_WORD_COUNT                       0x1
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_RESET_VAL                        _MK_MASK_CONST(0xf1f1f030)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_RESET_MASK                       _MK_MASK_CONST(0xf1f1f07c)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_READ_MASK                        _MK_MASK_CONST(0xf1f1f07c)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_WRITE_MASK                       _MK_MASK_CONST(0xf1f1f07c)
+// XM2CLKCFG data pins high speed mode enable
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_HSM_EN_SHIFT                   _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_HSM_EN_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_HSM_EN_SHIFT)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_HSM_EN_RANGE                   2:2
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_HSM_EN_WOFFSET                 0x0
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_HSM_EN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_HSM_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_HSM_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_HSM_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_HSM_EN_DISABLE                 _MK_ENUM_CONST(0)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_HSM_EN_ENABLE                  _MK_ENUM_CONST(1)
+
+// XM2CLKCFG data pins schmidt enable
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_SCHMT_EN_SHIFT                 _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_SCHMT_EN_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_SCHMT_EN_RANGE                 3:3
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_SCHMT_EN_WOFFSET                       0x0
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_SCHMT_EN_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_SCHMT_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_SCHMT_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_SCHMT_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_SCHMT_EN_DISABLE                       _MK_ENUM_CONST(0)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_SCHMT_EN_ENABLE                        _MK_ENUM_CONST(1)
+
+// XM2CLKCFG data pins low power mode select
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_LPMD_SHIFT                     _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_LPMD_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_LPMD_SHIFT)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_LPMD_RANGE                     5:4
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_LPMD_WOFFSET                   0x0
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_LPMD_DEFAULT                   _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_LPMD_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_LPMD_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_LPMD_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// XM2CLKCFG data pins vref enable
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_VREF_EN_SHIFT                  _MK_SHIFT_CONST(6)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_VREF_EN_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_VREF_EN_SHIFT)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_VREF_EN_RANGE                  6:6
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_VREF_EN_WOFFSET                        0x0
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_VREF_EN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_VREF_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_VREF_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_VREF_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_VREF_EN_DISABLE                        _MK_ENUM_CONST(0)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_VREF_EN_ENABLE                 _MK_ENUM_CONST(1)
+
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVDN_SHIFT                        _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVDN_FIELD                        (_MK_MASK_CONST(0x1f) << APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVDN_RANGE                        16:12
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVDN_WOFFSET                      0x0
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVDN_DEFAULT                      _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVDN_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVDN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVDN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVUP_SHIFT                        _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVUP_FIELD                        (_MK_MASK_CONST(0x1f) << APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVUP_RANGE                        24:20
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVUP_WOFFSET                      0x0
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVUP_DEFAULT                      _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVUP_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVUP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVUP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVDN_SLWR_SHIFT                   _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVDN_SLWR_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVDN_SLWR_RANGE                   29:28
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVDN_SLWR_WOFFSET                 0x0
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVDN_SLWR_DEFAULT                 _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVDN_SLWR_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVDN_SLWR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVUP_SLWF_SHIFT                   _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVUP_SLWF_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVUP_SLWF_RANGE                   31:30
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVUP_SLWF_WOFFSET                 0x0
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVUP_SLWF_DEFAULT                 _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVUP_SLWF_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVUP_SLWF_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_MEMCOMPPADCTRL_0  //        0       rw  CFG2TMC_MEM_COMP_EN_COMP    i=0x0   // compensation enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_MEMCOMPPADCTRL_0                    _MK_ADDR_CONST(0x8d4)
+#define APB_MISC_GP_MEMCOMPPADCTRL_0_WORD_COUNT                         0x1
+#define APB_MISC_GP_MEMCOMPPADCTRL_0_RESET_VAL                  _MK_MASK_CONST(0x1f1f000)
+#define APB_MISC_GP_MEMCOMPPADCTRL_0_RESET_MASK                         _MK_MASK_CONST(0x1f1f004)
+#define APB_MISC_GP_MEMCOMPPADCTRL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_MEMCOMPPADCTRL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_MEMCOMPPADCTRL_0_READ_MASK                  _MK_MASK_CONST(0x1f1f004)
+#define APB_MISC_GP_MEMCOMPPADCTRL_0_WRITE_MASK                         _MK_MASK_CONST(0x1f1f004)
+// high speed mode enable
+#define APB_MISC_GP_MEMCOMPPADCTRL_0_MEM_E_HSM_SHIFT                    _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_MEMCOMPPADCTRL_0_MEM_E_HSM_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_GP_MEMCOMPPADCTRL_0_MEM_E_HSM_SHIFT)
+#define APB_MISC_GP_MEMCOMPPADCTRL_0_MEM_E_HSM_RANGE                    2:2
+#define APB_MISC_GP_MEMCOMPPADCTRL_0_MEM_E_HSM_WOFFSET                  0x0
+#define APB_MISC_GP_MEMCOMPPADCTRL_0_MEM_E_HSM_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_MEMCOMPPADCTRL_0_MEM_E_HSM_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_MEMCOMPPADCTRL_0_MEM_E_HSM_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_MEMCOMPPADCTRL_0_MEM_E_HSM_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_MEMCOMPPADCTRL_0_MEM_E_HSM_DISABLE                  _MK_ENUM_CONST(0)
+#define APB_MISC_GP_MEMCOMPPADCTRL_0_MEM_E_HSM_ENABLE                   _MK_ENUM_CONST(1)
+
+#define APB_MISC_GP_MEMCOMPPADCTRL_0_MEM2COMPPAD_DRVDN_SHIFT                    _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_MEMCOMPPADCTRL_0_MEM2COMPPAD_DRVDN_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_MEMCOMPPADCTRL_0_MEM2COMPPAD_DRVDN_SHIFT)
+#define APB_MISC_GP_MEMCOMPPADCTRL_0_MEM2COMPPAD_DRVDN_RANGE                    16:12
+#define APB_MISC_GP_MEMCOMPPADCTRL_0_MEM2COMPPAD_DRVDN_WOFFSET                  0x0
+#define APB_MISC_GP_MEMCOMPPADCTRL_0_MEM2COMPPAD_DRVDN_DEFAULT                  _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_MEMCOMPPADCTRL_0_MEM2COMPPAD_DRVDN_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_MEMCOMPPADCTRL_0_MEM2COMPPAD_DRVDN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_MEMCOMPPADCTRL_0_MEM2COMPPAD_DRVDN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_MEMCOMPPADCTRL_0_MEM2COMPPAD_DRVUP_SHIFT                    _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_MEMCOMPPADCTRL_0_MEM2COMPPAD_DRVUP_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_MEMCOMPPADCTRL_0_MEM2COMPPAD_DRVUP_SHIFT)
+#define APB_MISC_GP_MEMCOMPPADCTRL_0_MEM2COMPPAD_DRVUP_RANGE                    24:20
+#define APB_MISC_GP_MEMCOMPPADCTRL_0_MEM2COMPPAD_DRVUP_WOFFSET                  0x0
+#define APB_MISC_GP_MEMCOMPPADCTRL_0_MEM2COMPPAD_DRVUP_DEFAULT                  _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_MEMCOMPPADCTRL_0_MEM2COMPPAD_DRVUP_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_MEMCOMPPADCTRL_0_MEM2COMPPAD_DRVUP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_MEMCOMPPADCTRL_0_MEM2COMPPAD_DRVUP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_PADCTL_DFT_0  
+#define APB_MISC_GP_PADCTL_DFT_0                        _MK_ADDR_CONST(0x8d8)
+#define APB_MISC_GP_PADCTL_DFT_0_WORD_COUNT                     0x1
+#define APB_MISC_GP_PADCTL_DFT_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_PADCTL_DFT_0_RESET_MASK                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_PADCTL_DFT_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_PADCTL_DFT_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_PADCTL_DFT_0_READ_MASK                      _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_PADCTL_DFT_0_WRITE_MASK                     _MK_MASK_CONST(0x3)
+// Enable pin-shorting for tester mode pin-shorting
+#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_EN_SHIFT                      _MK_SHIFT_CONST(0)
+#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_EN_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_PADCTL_DFT_0_PINSHORT_EN_SHIFT)
+#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_EN_RANGE                      0:0
+#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_EN_WOFFSET                    0x0
+#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_EN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_EN_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_EN_ENABLE                     _MK_ENUM_CONST(1)
+
+// Select which pins are used for test-mode observe
+#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_SEL_SHIFT                     _MK_SHIFT_CONST(1)
+#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_SEL_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_PADCTL_DFT_0_PINSHORT_SEL_SHIFT)
+#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_SEL_RANGE                     1:1
+#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_SEL_WOFFSET                   0x0
+#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_SEL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_SEL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_SEL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_SEL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_UTMIP_PLL_CFG0_0  // USB_PHY PLL Configuration Register 0
+//
+// The data sampling frequency relies on a 960MHz clock, so the goal of the PLL is to have:
+// In_Frequency*(PLL_VCOMULTBY2+1)*(PLL_NDIV/PLL_MDIV) = 960MHz
+//
+// With a 12MHz input from PLL_U, the default setting of 
+// PLL_VCOMULTBY2=1, PLL_NDIV=40 and PLL_MDIV=1 results in a correct output.
+#define APB_MISC_UTMIP_PLL_CFG0_0                       _MK_ADDR_CONST(0xa00)
+#define APB_MISC_UTMIP_PLL_CFG0_0_WORD_COUNT                    0x1
+#define APB_MISC_UTMIP_PLL_CFG0_0_RESET_VAL                     _MK_MASK_CONST(0x280180)
+#define APB_MISC_UTMIP_PLL_CFG0_0_RESET_MASK                    _MK_MASK_CONST(0x7fffffff)
+#define APB_MISC_UTMIP_PLL_CFG0_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG0_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG0_0_READ_MASK                     _MK_MASK_CONST(0x7fffffff)
+#define APB_MISC_UTMIP_PLL_CFG0_0_WRITE_MASK                    _MK_MASK_CONST(0x7fffffff)
+// LOCK_ENABLE input of USB_PHY PLL.
+// Normally only used during test. See cell specification.
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKENABLE_SHIFT                    _MK_SHIFT_CONST(0)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKENABLE_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKENABLE_SHIFT)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKENABLE_RANGE                    0:0
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKENABLE_WOFFSET                  0x0
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKENABLE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKENABLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKENABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKENABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// LOCKSEL[5:0] input of USB_PHY PLL.
+// Used in test modes only. See cell specification.
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKSEL_SHIFT                       _MK_SHIFT_CONST(1)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKSEL_FIELD                       (_MK_MASK_CONST(0x3f) << APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKSEL_SHIFT)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKSEL_RANGE                       6:1
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKSEL_WOFFSET                     0x0
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKSEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKSEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3f)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKSEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKSEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// VCOMULTBY2 control of the UTMIP PHY PLL.
+// Recommended setting is on. Additional divide by 2 on the 
+// VCO feedback. Which is setting the bit to 1. See cell spec.
+//
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_VCOMULTBY2_SHIFT                    _MK_SHIFT_CONST(7)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_VCOMULTBY2_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_VCOMULTBY2_SHIFT)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_VCOMULTBY2_RANGE                    7:7
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_VCOMULTBY2_WOFFSET                  0x0
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_VCOMULTBY2_DEFAULT                  _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_VCOMULTBY2_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_VCOMULTBY2_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_VCOMULTBY2_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// MDIV[7:0] input of the USB_PHY PLL. This is the predivide on the PLL. 
+// 0x0 is not allowed. See cell specification.
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_MDIV_SHIFT                  _MK_SHIFT_CONST(8)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_MDIV_FIELD                  (_MK_MASK_CONST(0xff) << APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_MDIV_SHIFT)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_MDIV_RANGE                  15:8
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_MDIV_WOFFSET                        0x0
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_MDIV_DEFAULT                        _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_MDIV_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_MDIV_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_MDIV_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// NDIV[7:0] input of USB_PHY PLL. 
+// This is the feedback divider on the VCO feedback. 
+// 0x0 is not allowed. See cell specification.
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_NDIV_SHIFT                  _MK_SHIFT_CONST(16)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_NDIV_FIELD                  (_MK_MASK_CONST(0xff) << APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_NDIV_SHIFT)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_NDIV_RANGE                  23:16
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_NDIV_WOFFSET                        0x0
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_NDIV_DEFAULT                        _MK_MASK_CONST(0x28)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_NDIV_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_NDIV_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_NDIV_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// PDIV[2:0] input of the USB_PHY PLL.
+// Reserved. Keep at 0x0. Currently there is no post divider on this PLL. 
+// See cell specification.
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIV_SHIFT                  _MK_SHIFT_CONST(24)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIV_FIELD                  (_MK_MASK_CONST(0x7) << APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIV_SHIFT)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIV_RANGE                  26:24
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIV_WOFFSET                        0x0
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIV_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIV_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIV_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIV_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// PDIVRST of the UTMIP PHY PLL.
+// Reserved. Keep at 0x0. Currently there is no post divider on this PLL. 
+// See cell specification.
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIVRST_SHIFT                       _MK_SHIFT_CONST(27)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIVRST_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIVRST_SHIFT)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIVRST_RANGE                       27:27
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIVRST_WOFFSET                     0x0
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIVRST_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIVRST_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIVRST_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIVRST_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Selects which of the eight 60MHz clock phases to produce at the output 
+// of the USB PHY PLL. This is for a test mode. See cell specification.
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_SELECT_SHIFT                        _MK_SHIFT_CONST(28)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_SELECT_FIELD                        (_MK_MASK_CONST(0x7) << APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_SELECT_SHIFT)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_SELECT_RANGE                        30:28
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_SELECT_WOFFSET                      0x0
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_SELECT_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_SELECT_DEFAULT_MASK                 _MK_MASK_CONST(0x7)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_SELECT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_SELECT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_UTMIP_PLL_CFG1_0  // UTMIP PLL and PLLU configuration register 1
+#define APB_MISC_UTMIP_PLL_CFG1_0                       _MK_ADDR_CONST(0xa04)
+#define APB_MISC_UTMIP_PLL_CFG1_0_WORD_COUNT                    0x1
+#define APB_MISC_UTMIP_PLL_CFG1_0_RESET_VAL                     _MK_MASK_CONST(0x182000c0)
+#define APB_MISC_UTMIP_PLL_CFG1_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_UTMIP_PLL_CFG1_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG1_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG1_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_UTMIP_PLL_CFG1_0_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
+// Determines the time to wait until the output of USB_PHY PLL is considered stable. 
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_XTAL_FREQ_COUNT_SHIFT                   _MK_SHIFT_CONST(0)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_XTAL_FREQ_COUNT_FIELD                   (_MK_MASK_CONST(0xfff) << APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_XTAL_FREQ_COUNT_SHIFT)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_XTAL_FREQ_COUNT_RANGE                   11:0
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_XTAL_FREQ_COUNT_WOFFSET                 0x0
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_XTAL_FREQ_COUNT_DEFAULT                 _MK_MASK_CONST(0xc0)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_XTAL_FREQ_COUNT_DEFAULT_MASK                    _MK_MASK_CONST(0xfff)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_XTAL_FREQ_COUNT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_XTAL_FREQ_COUNT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Force USB_PHY PLL pll_active input off. (Overrides FORCE_PLL_ACTIVE_POWERUP.)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERDOWN_SHIFT                        _MK_SHIFT_CONST(12)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERDOWN_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERDOWN_SHIFT)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERDOWN_RANGE                        12:12
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERDOWN_WOFFSET                      0x0
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERDOWN_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERDOWN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERDOWN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERDOWN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Force USB_PHY PLL pll_active input on. 
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERUP_SHIFT                  _MK_SHIFT_CONST(13)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERUP_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERUP_SHIFT)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERUP_RANGE                  13:13
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERUP_WOFFSET                        0x0
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERUP_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERUP_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERUP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERUP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Force USB_PHY PLL pll_enable input off. (Overrides FORCE_PLL_ENABLE_POWERUP.)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERDOWN_SHIFT                        _MK_SHIFT_CONST(14)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERDOWN_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERDOWN_SHIFT)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERDOWN_RANGE                        14:14
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERDOWN_WOFFSET                      0x0
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERDOWN_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERDOWN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERDOWN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERDOWN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Force USB_PHY PLL pll_enable input on. 
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERUP_SHIFT                  _MK_SHIFT_CONST(15)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERUP_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERUP_SHIFT)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERUP_RANGE                  15:15
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERUP_WOFFSET                        0x0
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERUP_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERUP_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERUP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERUP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Force PLL_U into power down. (Overrides FORCE_PLLU_POWERUP.)  
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERDOWN_SHIFT                      _MK_SHIFT_CONST(16)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERDOWN_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERDOWN_SHIFT)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERDOWN_RANGE                      16:16
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERDOWN_WOFFSET                    0x0
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERDOWN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERDOWN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERDOWN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERDOWN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Force PLL_U into power up.
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERUP_SHIFT                        _MK_SHIFT_CONST(17)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERUP_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERUP_SHIFT)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERUP_RANGE                        17:17
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERUP_WOFFSET                      0x0
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERUP_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERUP_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERUP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERUP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// SETUP[8:0] input of USB_PHY PLL.
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_PLL_SETUP_SHIFT                 _MK_SHIFT_CONST(18)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_PLL_SETUP_FIELD                 (_MK_MASK_CONST(0x1ff) << APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_PLL_SETUP_SHIFT)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_PLL_SETUP_RANGE                 26:18
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_PLL_SETUP_WOFFSET                       0x0
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_PLL_SETUP_DEFAULT                       _MK_MASK_CONST(0x8)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_PLL_SETUP_DEFAULT_MASK                  _MK_MASK_CONST(0x1ff)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_PLL_SETUP_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_PLL_SETUP_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Controls the wait time to enable PLL_U when coming out of suspend or reset.
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT                     _MK_SHIFT_CONST(27)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_PLLU_ENABLE_DLY_COUNT_FIELD                     (_MK_MASK_CONST(0x1f) << APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_PLLU_ENABLE_DLY_COUNT_RANGE                     31:27
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_PLLU_ENABLE_DLY_COUNT_WOFFSET                   0x0
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_PLLU_ENABLE_DLY_COUNT_DEFAULT                   _MK_MASK_CONST(0x3)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_PLLU_ENABLE_DLY_COUNT_DEFAULT_MASK                      _MK_MASK_CONST(0x1f)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_PLLU_ENABLE_DLY_COUNT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_PLLU_ENABLE_DLY_COUNT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_UTMIP_XCVR_CFG0_0  // UTMIP transceiver cell configuration register 0
+#define APB_MISC_UTMIP_XCVR_CFG0_0                      _MK_ADDR_CONST(0xa08)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_WORD_COUNT                   0x1
+#define APB_MISC_UTMIP_XCVR_CFG0_0_RESET_VAL                    _MK_MASK_CONST(0x2500)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_RESET_MASK                   _MK_MASK_CONST(0xfffff)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_READ_MASK                    _MK_MASK_CONST(0xfffff)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_WRITE_MASK                   _MK_MASK_CONST(0xfffff)
+// SETUP[3:0] input of XCVR cell. HS driver output control.
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_SETUP_SHIFT                       _MK_SHIFT_CONST(0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_SETUP_FIELD                       (_MK_MASK_CONST(0xf) << APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_SETUP_SHIFT)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_SETUP_RANGE                       3:0
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_SETUP_WOFFSET                     0x0
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_SETUP_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_SETUP_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_SETUP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_SETUP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// HS slew rate control.
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSSLEW_SHIFT                      _MK_SHIFT_CONST(4)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSSLEW_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSSLEW_SHIFT)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSSLEW_RANGE                      5:4
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSSLEW_WOFFSET                    0x0
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSSLEW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSSLEW_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSSLEW_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSSLEW_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// FS slew rate control.
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_FSSLEW_SHIFT                      _MK_SHIFT_CONST(6)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_FSSLEW_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_FSSLEW_SHIFT)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_FSSLEW_RANGE                      7:6
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_FSSLEW_WOFFSET                    0x0
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_FSSLEW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_FSSLEW_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_FSSLEW_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_FSSLEW_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// LS rising slew rate control.
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSRSLEW_SHIFT                     _MK_SHIFT_CONST(8)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSRSLEW_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSRSLEW_SHIFT)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSRSLEW_RANGE                     9:8
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSRSLEW_WOFFSET                   0x0
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSRSLEW_DEFAULT                   _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSRSLEW_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSRSLEW_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSRSLEW_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// LS falling slew rate control.
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSFSLEW_SHIFT                     _MK_SHIFT_CONST(10)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSFSLEW_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSFSLEW_SHIFT)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSFSLEW_RANGE                     11:10
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSFSLEW_WOFFSET                   0x0
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSFSLEW_DEFAULT                   _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSFSLEW_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSFSLEW_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSFSLEW_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Internal loopback inside XCVR cell. Used for IOBIST.
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSLOOPBACK_SHIFT                  _MK_SHIFT_CONST(12)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSLOOPBACK_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSLOOPBACK_SHIFT)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSLOOPBACK_RANGE                  12:12
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSLOOPBACK_WOFFSET                        0x0
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSLOOPBACK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSLOOPBACK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSLOOPBACK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSLOOPBACK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Enable HS termination.
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_TERMEN_SHIFT                      _MK_SHIFT_CONST(13)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_TERMEN_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_TERMEN_SHIFT)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_TERMEN_RANGE                      13:13
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_TERMEN_WOFFSET                    0x0
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_TERMEN_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_TERMEN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_TERMEN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_TERMEN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Force PD input into power down. (Overrides FORCE_PD_POWERUP.)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERDOWN_SHIFT                       _MK_SHIFT_CONST(14)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERDOWN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERDOWN_SHIFT)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERDOWN_RANGE                       14:14
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERDOWN_WOFFSET                     0x0
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERDOWN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERDOWN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERDOWN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERDOWN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Force PD input into power up. 
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERUP_SHIFT                 _MK_SHIFT_CONST(15)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERUP_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERUP_SHIFT)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERUP_RANGE                 15:15
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERUP_WOFFSET                       0x0
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERUP_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERUP_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERUP_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERUP_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Force PD2 input into power down. (Overrides FORCE_PD2_POWERUP.)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERDOWN_SHIFT                      _MK_SHIFT_CONST(16)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERDOWN_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERDOWN_SHIFT)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERDOWN_RANGE                      16:16
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERDOWN_WOFFSET                    0x0
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERDOWN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERDOWN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERDOWN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERDOWN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Force PD2 input into power up.
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERUP_SHIFT                        _MK_SHIFT_CONST(17)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERUP_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERUP_SHIFT)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERUP_RANGE                        17:17
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERUP_WOFFSET                      0x0
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERUP_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERUP_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERUP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERUP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Force PDZI input into power down. (Overrides FORCE_PDZI_POWERUP.)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERDOWN_SHIFT                     _MK_SHIFT_CONST(18)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERDOWN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERDOWN_SHIFT)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERDOWN_RANGE                     18:18
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERDOWN_WOFFSET                   0x0
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERDOWN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERDOWN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERDOWN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERDOWN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Force PDZI input into power up.
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERUP_SHIFT                       _MK_SHIFT_CONST(19)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERUP_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERUP_SHIFT)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERUP_RANGE                       19:19
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERUP_WOFFSET                     0x0
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERUP_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERUP_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERUP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERUP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_UTMIP_BIAS_CFG0_0  // UTMIP Bias cell configuration register 0
+#define APB_MISC_UTMIP_BIAS_CFG0_0                      _MK_ADDR_CONST(0xa0c)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_WORD_COUNT                   0x1
+#define APB_MISC_UTMIP_BIAS_CFG0_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_RESET_MASK                   _MK_MASK_CONST(0xffffff)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_READ_MASK                    _MK_MASK_CONST(0xffffff)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_WRITE_MASK                   _MK_MASK_CONST(0xffffff)
+// HS squelch detector level.
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSSQUELCH_LEVEL_SHIFT                  _MK_SHIFT_CONST(0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSSQUELCH_LEVEL_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSSQUELCH_LEVEL_SHIFT)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSSQUELCH_LEVEL_RANGE                  1:0
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSSQUELCH_LEVEL_WOFFSET                        0x0
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSSQUELCH_LEVEL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSSQUELCH_LEVEL_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSSQUELCH_LEVEL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSSQUELCH_LEVEL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// HS disconnect detector level.
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSDISCON_LEVEL_SHIFT                   _MK_SHIFT_CONST(2)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSDISCON_LEVEL_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSDISCON_LEVEL_SHIFT)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSDISCON_LEVEL_RANGE                   3:2
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSDISCON_LEVEL_WOFFSET                 0x0
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSDISCON_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSDISCON_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSDISCON_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSDISCON_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// HS chirp detector level.
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSCHIRP_LEVEL_SHIFT                    _MK_SHIFT_CONST(4)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSCHIRP_LEVEL_FIELD                    (_MK_MASK_CONST(0x3) << APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSCHIRP_LEVEL_SHIFT)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSCHIRP_LEVEL_RANGE                    5:4
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSCHIRP_LEVEL_WOFFSET                  0x0
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSCHIRP_LEVEL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSCHIRP_LEVEL_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSCHIRP_LEVEL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSCHIRP_LEVEL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// SessionEnd detector level.
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_SESS_LEVEL_LEVEL_SHIFT                 _MK_SHIFT_CONST(6)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_SESS_LEVEL_LEVEL_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_SESS_LEVEL_LEVEL_SHIFT)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_SESS_LEVEL_LEVEL_RANGE                 7:6
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_SESS_LEVEL_LEVEL_WOFFSET                       0x0
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_SESS_LEVEL_LEVEL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_SESS_LEVEL_LEVEL_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_SESS_LEVEL_LEVEL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_SESS_LEVEL_LEVEL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Vbus detector level.
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_VBUS_LEVEL_LEVEL_SHIFT                 _MK_SHIFT_CONST(8)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_VBUS_LEVEL_LEVEL_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_VBUS_LEVEL_LEVEL_SHIFT)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_VBUS_LEVEL_LEVEL_RANGE                 9:8
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_VBUS_LEVEL_LEVEL_WOFFSET                       0x0
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_VBUS_LEVEL_LEVEL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_VBUS_LEVEL_LEVEL_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_VBUS_LEVEL_LEVEL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_VBUS_LEVEL_LEVEL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Power down bias circuit.
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_BIASPD_SHIFT                   _MK_SHIFT_CONST(10)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_BIASPD_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_BIASPD_SHIFT)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_BIASPD_RANGE                   10:10
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_BIASPD_WOFFSET                 0x0
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_BIASPD_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_BIASPD_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_BIASPD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_BIASPD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Power down OTG circuit.
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_OTGPD_SHIFT                    _MK_SHIFT_CONST(11)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_OTGPD_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_OTGPD_SHIFT)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_OTGPD_RANGE                    11:11
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_OTGPD_WOFFSET                  0x0
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_OTGPD_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_OTGPD_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_OTGPD_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_OTGPD_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Active 1.5K pullup control offset.
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_PULLUP_OFFSET_SHIFT                     _MK_SHIFT_CONST(12)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_PULLUP_OFFSET_FIELD                     (_MK_MASK_CONST(0x7) << APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_PULLUP_OFFSET_SHIFT)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_PULLUP_OFFSET_RANGE                     14:12
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_PULLUP_OFFSET_WOFFSET                   0x0
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_PULLUP_OFFSET_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_PULLUP_OFFSET_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_PULLUP_OFFSET_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_PULLUP_OFFSET_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Active termination control offset.
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_TERM_OFFSET_SHIFT                       _MK_SHIFT_CONST(15)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_TERM_OFFSET_FIELD                       (_MK_MASK_CONST(0x7) << APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_TERM_OFFSET_SHIFT)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_TERM_OFFSET_RANGE                       17:15
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_TERM_OFFSET_WOFFSET                     0x0
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_TERM_OFFSET_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_TERM_OFFSET_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_TERM_OFFSET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_TERM_OFFSET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// 0: StaticGpi = IdDig. 1: StaticGpi = GPI_VAL.
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_GPI_SEL_SHIFT                  _MK_SHIFT_CONST(18)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_GPI_SEL_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_GPI_SEL_SHIFT)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_GPI_SEL_RANGE                  18:18
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_GPI_SEL_WOFFSET                        0x0
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_GPI_SEL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_GPI_SEL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_GPI_SEL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_GPI_SEL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// See GPI_SEL.
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_GPI_VAL_SHIFT                  _MK_SHIFT_CONST(19)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_GPI_VAL_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_GPI_VAL_SHIFT)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_GPI_VAL_RANGE                  19:19
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_GPI_VAL_WOFFSET                        0x0
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_GPI_VAL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_GPI_VAL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_GPI_VAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_GPI_VAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// 0: IdDig = IdDig. 1: IdDig = IDDIG_VAL.
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_SEL_SHIFT                        _MK_SHIFT_CONST(20)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_SEL_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_SEL_SHIFT)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_SEL_RANGE                        20:20
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_SEL_WOFFSET                      0x0
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_SEL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_SEL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_SEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_SEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// See IDDIG_SEL.
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_VAL_SHIFT                        _MK_SHIFT_CONST(21)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_VAL_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_VAL_SHIFT)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_VAL_RANGE                        21:21
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_VAL_WOFFSET                      0x0
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_VAL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_VAL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_VAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_VAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// 0: IDPD = ~IdPullup. 1: IDPD = IDPD_VAL.
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_SEL_SHIFT                 _MK_SHIFT_CONST(22)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_SEL_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_SEL_SHIFT)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_SEL_RANGE                 22:22
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_SEL_WOFFSET                       0x0
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_SEL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_SEL_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_SEL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_SEL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// See IDPD_SEL.
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_VAL_SHIFT                 _MK_SHIFT_CONST(23)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_VAL_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_VAL_SHIFT)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_VAL_RANGE                 23:23
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_VAL_WOFFSET                       0x0
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_VAL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_VAL_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_VAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_VAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_UTMIP_HSRX_CFG0_0  // UTMIP High speed receive config 0 
+#define APB_MISC_UTMIP_HSRX_CFG0_0                      _MK_ADDR_CONST(0xa10)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_WORD_COUNT                   0x1
+#define APB_MISC_UTMIP_HSRX_CFG0_0_RESET_VAL                    _MK_MASK_CONST(0x91653400)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
+// Require 4 sync pattern transitions (01) instead of 3
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_USE4SYNC_TRAN_SHIFT                    _MK_SHIFT_CONST(0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_USE4SYNC_TRAN_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_USE4SYNC_TRAN_SHIFT)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_USE4SYNC_TRAN_RANGE                    0:0
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_USE4SYNC_TRAN_WOFFSET                  0x0
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_USE4SYNC_TRAN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_USE4SYNC_TRAN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_USE4SYNC_TRAN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_USE4SYNC_TRAN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Sync pattern detection needs 3 consecutive samples instead of 4
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_THREE_SYNCBITS_SHIFT                   _MK_SHIFT_CONST(1)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_THREE_SYNCBITS_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_THREE_SYNCBITS_SHIFT)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_THREE_SYNCBITS_RANGE                   1:1
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_THREE_SYNCBITS_WOFFSET                 0x0
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_THREE_SYNCBITS_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_THREE_SYNCBITS_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_THREE_SYNCBITS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_THREE_SYNCBITS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Based on incoming edges and current sampling position, adjust phase
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PHASE_ADJUST_SHIFT                     _MK_SHIFT_CONST(2)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PHASE_ADJUST_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PHASE_ADJUST_SHIFT)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PHASE_ADJUST_RANGE                     3:2
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PHASE_ADJUST_WOFFSET                   0x0
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PHASE_ADJUST_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PHASE_ADJUST_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PHASE_ADJUST_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PHASE_ADJUST_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Retime the path. 
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_INERTIA_SHIFT                   _MK_SHIFT_CONST(4)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_INERTIA_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_INERTIA_SHIFT)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_INERTIA_RANGE                   5:4
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_INERTIA_WOFFSET                 0x0
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_INERTIA_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_INERTIA_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_INERTIA_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_INERTIA_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Pass through the feedback, do not block it.
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PASS_FEEDBACK_SHIFT                    _MK_SHIFT_CONST(6)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PASS_FEEDBACK_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PASS_FEEDBACK_SHIFT)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PASS_FEEDBACK_RANGE                    6:6
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PASS_FEEDBACK_WOFFSET                  0x0
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PASS_FEEDBACK_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PASS_FEEDBACK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PASS_FEEDBACK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PASS_FEEDBACK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// When in Chirp Mode, allow chirp rx data through
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PASS_CHIRP_SHIFT                       _MK_SHIFT_CONST(7)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PASS_CHIRP_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PASS_CHIRP_SHIFT)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PASS_CHIRP_RANGE                       7:7
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PASS_CHIRP_WOFFSET                     0x0
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PASS_CHIRP_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PASS_CHIRP_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PASS_CHIRP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PASS_CHIRP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Do not declare underrun errors
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_UNDERRUN_DISABLE_SHIFT                 _MK_SHIFT_CONST(8)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_UNDERRUN_DISABLE_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_UNDERRUN_DISABLE_SHIFT)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_UNDERRUN_DISABLE_RANGE                 8:8
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_UNDERRUN_DISABLE_WOFFSET                       0x0
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_UNDERRUN_DISABLE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_UNDERRUN_DISABLE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_UNDERRUN_DISABLE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_UNDERRUN_DISABLE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Do not declare overrun errors until overflow of FIFO
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_OVERRUN_DISABLE_SHIFT                  _MK_SHIFT_CONST(9)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_OVERRUN_DISABLE_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_OVERRUN_DISABLE_SHIFT)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_OVERRUN_DISABLE_RANGE                  9:9
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_OVERRUN_DISABLE_WOFFSET                        0x0
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_OVERRUN_DISABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_OVERRUN_DISABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_OVERRUN_DISABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_OVERRUN_DISABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Depth of elastic input store
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_LIMIT_SHIFT                    _MK_SHIFT_CONST(10)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_LIMIT_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_LIMIT_SHIFT)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_LIMIT_RANGE                    14:10
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_LIMIT_WOFFSET                  0x0
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_LIMIT_DEFAULT                  _MK_MASK_CONST(0xd)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_LIMIT_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_LIMIT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_LIMIT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Number of cycles of idle to declare IDLE. 
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_IDLE_WAIT_SHIFT                        _MK_SHIFT_CONST(15)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_IDLE_WAIT_FIELD                        (_MK_MASK_CONST(0x1f) << APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_IDLE_WAIT_SHIFT)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_IDLE_WAIT_RANGE                        19:15
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_IDLE_WAIT_WOFFSET                      0x0
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_IDLE_WAIT_DEFAULT                      _MK_MASK_CONST(0xa)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_IDLE_WAIT_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_IDLE_WAIT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_IDLE_WAIT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Do not strip incoming data
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_NO_STRIPPING_SHIFT                     _MK_SHIFT_CONST(20)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_NO_STRIPPING_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_NO_STRIPPING_SHIFT)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_NO_STRIPPING_RANGE                     20:20
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_NO_STRIPPING_WOFFSET                   0x0
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_NO_STRIPPING_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_NO_STRIPPING_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_NO_STRIPPING_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_NO_STRIPPING_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Limit the delay of the squelch at EOP time
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_SQUELCH_EOP_DLY_SHIFT                  _MK_SHIFT_CONST(21)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_SQUELCH_EOP_DLY_FIELD                  (_MK_MASK_CONST(0x7) << APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_SQUELCH_EOP_DLY_SHIFT)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_SQUELCH_EOP_DLY_RANGE                  23:21
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_SQUELCH_EOP_DLY_WOFFSET                        0x0
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_SQUELCH_EOP_DLY_DEFAULT                        _MK_MASK_CONST(0x3)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_SQUELCH_EOP_DLY_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_SQUELCH_EOP_DLY_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_SQUELCH_EOP_DLY_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// The number of (edges-1) needed to move the sampling point
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_UPDN_DIV_SHIFT                  _MK_SHIFT_CONST(24)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_UPDN_DIV_FIELD                  (_MK_MASK_CONST(0xf) << APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_UPDN_DIV_SHIFT)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_UPDN_DIV_RANGE                  27:24
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_UPDN_DIV_WOFFSET                        0x0
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_UPDN_DIV_DEFAULT                        _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_UPDN_DIV_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_UPDN_DIV_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_UPDN_DIV_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Realign the inertia counters on a new packet
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_REALIGN_ON_NEW_PKT_SHIFT                       _MK_SHIFT_CONST(28)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_REALIGN_ON_NEW_PKT_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_REALIGN_ON_NEW_PKT_SHIFT)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_REALIGN_ON_NEW_PKT_RANGE                       28:28
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_REALIGN_ON_NEW_PKT_WOFFSET                     0x0
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_REALIGN_ON_NEW_PKT_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_REALIGN_ON_NEW_PKT_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_REALIGN_ON_NEW_PKT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_REALIGN_ON_NEW_PKT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Allow consecutive ups and downs on the bits, debug only, set to 0.
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ALLOW_CONSEC_UPDN_SHIFT                        _MK_SHIFT_CONST(29)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ALLOW_CONSEC_UPDN_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ALLOW_CONSEC_UPDN_SHIFT)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ALLOW_CONSEC_UPDN_RANGE                        29:29
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ALLOW_CONSEC_UPDN_WOFFSET                      0x0
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ALLOW_CONSEC_UPDN_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ALLOW_CONSEC_UPDN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ALLOW_CONSEC_UPDN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ALLOW_CONSEC_UPDN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Keep the stay alive pattern on active
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_KEEP_PATT_ON_ACTIVE_SHIFT                      _MK_SHIFT_CONST(30)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_KEEP_PATT_ON_ACTIVE_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_KEEP_PATT_ON_ACTIVE_SHIFT)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_KEEP_PATT_ON_ACTIVE_RANGE                      31:30
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_KEEP_PATT_ON_ACTIVE_WOFFSET                    0x0
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_KEEP_PATT_ON_ACTIVE_DEFAULT                    _MK_MASK_CONST(0x2)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_KEEP_PATT_ON_ACTIVE_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_KEEP_PATT_ON_ACTIVE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_KEEP_PATT_ON_ACTIVE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_UTMIP_HSRX_CFG1_0  // UTMIP High speed receive config 1
+#define APB_MISC_UTMIP_HSRX_CFG1_0                      _MK_ADDR_CONST(0xa14)
+#define APB_MISC_UTMIP_HSRX_CFG1_0_WORD_COUNT                   0x1
+#define APB_MISC_UTMIP_HSRX_CFG1_0_RESET_VAL                    _MK_MASK_CONST(0x13)
+#define APB_MISC_UTMIP_HSRX_CFG1_0_RESET_MASK                   _MK_MASK_CONST(0x3f)
+#define APB_MISC_UTMIP_HSRX_CFG1_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG1_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG1_0_READ_MASK                    _MK_MASK_CONST(0x3f)
+#define APB_MISC_UTMIP_HSRX_CFG1_0_WRITE_MASK                   _MK_MASK_CONST(0x3f)
+// Allow Keep Alive packets 
+#define APB_MISC_UTMIP_HSRX_CFG1_0_UTMIP_HS_ALLOW_KEEP_ALIVE_SHIFT                      _MK_SHIFT_CONST(0)
+#define APB_MISC_UTMIP_HSRX_CFG1_0_UTMIP_HS_ALLOW_KEEP_ALIVE_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_HSRX_CFG1_0_UTMIP_HS_ALLOW_KEEP_ALIVE_SHIFT)
+#define APB_MISC_UTMIP_HSRX_CFG1_0_UTMIP_HS_ALLOW_KEEP_ALIVE_RANGE                      0:0
+#define APB_MISC_UTMIP_HSRX_CFG1_0_UTMIP_HS_ALLOW_KEEP_ALIVE_WOFFSET                    0x0
+#define APB_MISC_UTMIP_HSRX_CFG1_0_UTMIP_HS_ALLOW_KEEP_ALIVE_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_HSRX_CFG1_0_UTMIP_HS_ALLOW_KEEP_ALIVE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_HSRX_CFG1_0_UTMIP_HS_ALLOW_KEEP_ALIVE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG1_0_UTMIP_HS_ALLOW_KEEP_ALIVE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// How long to wait before start of sync launches RxActive
+#define APB_MISC_UTMIP_HSRX_CFG1_0_UTMIP_HS_SYNC_START_DLY_SHIFT                        _MK_SHIFT_CONST(1)
+#define APB_MISC_UTMIP_HSRX_CFG1_0_UTMIP_HS_SYNC_START_DLY_FIELD                        (_MK_MASK_CONST(0x1f) << APB_MISC_UTMIP_HSRX_CFG1_0_UTMIP_HS_SYNC_START_DLY_SHIFT)
+#define APB_MISC_UTMIP_HSRX_CFG1_0_UTMIP_HS_SYNC_START_DLY_RANGE                        5:1
+#define APB_MISC_UTMIP_HSRX_CFG1_0_UTMIP_HS_SYNC_START_DLY_WOFFSET                      0x0
+#define APB_MISC_UTMIP_HSRX_CFG1_0_UTMIP_HS_SYNC_START_DLY_DEFAULT                      _MK_MASK_CONST(0x9)
+#define APB_MISC_UTMIP_HSRX_CFG1_0_UTMIP_HS_SYNC_START_DLY_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define APB_MISC_UTMIP_HSRX_CFG1_0_UTMIP_HS_SYNC_START_DLY_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG1_0_UTMIP_HS_SYNC_START_DLY_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_UTMIP_FSLSRX_CFG0_0  // UTMIP full and Low speed receive config 0
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0                    _MK_ADDR_CONST(0xa18)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_WORD_COUNT                         0x1
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_RESET_VAL                  _MK_MASK_CONST(0xfd548429)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+// Give up on packet if a long sequence of J 
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_LIMIT_SHIFT                  _MK_SHIFT_CONST(0)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_LIMIT_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_LIMIT_SHIFT)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_LIMIT_RANGE                  0:0
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_LIMIT_WOFFSET                        0x0
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_LIMIT_DEFAULT                        _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_LIMIT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_LIMIT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_LIMIT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// 20 bits of idle should end the packet if FsLsIdleCountLimitCfg=1.
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_MAX_SHIFT                    _MK_SHIFT_CONST(1)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_MAX_FIELD                    (_MK_MASK_CONST(0x3f) << APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_MAX_SHIFT)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_MAX_RANGE                    6:1
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_MAX_WOFFSET                  0x0
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_MAX_DEFAULT                  _MK_MASK_CONST(0x14)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_MAX_DEFAULT_MASK                     _MK_MASK_CONST(0x3f)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_MAX_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_MAX_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Enable the reset of the state machine on extended SE0
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_LIMIT_SHIFT                   _MK_SHIFT_CONST(7)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_LIMIT_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_LIMIT_SHIFT)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_LIMIT_RANGE                   7:7
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_LIMIT_WOFFSET                 0x0
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_LIMIT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_LIMIT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_LIMIT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_LIMIT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// 4 bits of of SEO should exceed the time limit
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_MAX_SHIFT                     _MK_SHIFT_CONST(8)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_MAX_FIELD                     (_MK_MASK_CONST(0x3f) << APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_MAX_SHIFT)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_MAX_RANGE                     13:8
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_MAX_WOFFSET                   0x0
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_MAX_DEFAULT                   _MK_MASK_CONST(0x4)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_MAX_DEFAULT_MASK                      _MK_MASK_CONST(0x3f)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_MAX_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_MAX_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Require a full sync pattern to declare the data received
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_ACTIVE_ON_FULL_SYNC_SHIFT                       _MK_SHIFT_CONST(14)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_ACTIVE_ON_FULL_SYNC_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_ACTIVE_ON_FULL_SYNC_SHIFT)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_ACTIVE_ON_FULL_SYNC_RANGE                       14:14
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_ACTIVE_ON_FULL_SYNC_WOFFSET                     0x0
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_ACTIVE_ON_FULL_SYNC_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_ACTIVE_ON_FULL_SYNC_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_ACTIVE_ON_FULL_SYNC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_ACTIVE_ON_FULL_SYNC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Limit the number of bit times a K can last
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_LIMIT_SHIFT                      _MK_SHIFT_CONST(15)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_LIMIT_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_LIMIT_SHIFT)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_LIMIT_RANGE                      15:15
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_LIMIT_WOFFSET                    0x0
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_LIMIT_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_LIMIT_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_LIMIT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_LIMIT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Number of K bits in question
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_MAX_SHIFT                        _MK_SHIFT_CONST(16)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_MAX_FIELD                        (_MK_MASK_CONST(0x3f) << APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_MAX_SHIFT)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_MAX_RANGE                        21:16
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_MAX_WOFFSET                      0x0
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_MAX_DEFAULT                      _MK_MASK_CONST(0x14)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_MAX_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_MAX_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_MAX_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Only look for transitioning out of EOP
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_EOP_ENDS_AT_SE0_SHIFT                   _MK_SHIFT_CONST(22)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_EOP_ENDS_AT_SE0_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_EOP_ENDS_AT_SE0_SHIFT)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_EOP_ENDS_AT_SE0_RANGE                   22:22
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_EOP_ENDS_AT_SE0_WOFFSET                 0x0
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_EOP_ENDS_AT_SE0_DEFAULT                 _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_EOP_ENDS_AT_SE0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_EOP_ENDS_AT_SE0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_EOP_ENDS_AT_SE0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Do not allow >= dribble bits 
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_LWR_DRIBBLE_SIZE_SHIFT                  _MK_SHIFT_CONST(23)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_LWR_DRIBBLE_SIZE_FIELD                  (_MK_MASK_CONST(0x7) << APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_LWR_DRIBBLE_SIZE_SHIFT)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_LWR_DRIBBLE_SIZE_RANGE                  25:23
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_LWR_DRIBBLE_SIZE_WOFFSET                        0x0
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_LWR_DRIBBLE_SIZE_DEFAULT                        _MK_MASK_CONST(0x2)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_LWR_DRIBBLE_SIZE_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_LWR_DRIBBLE_SIZE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_LWR_DRIBBLE_SIZE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Do not allow <= dribble bits
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_UPR_DRIBBLE_SIZE_SHIFT                  _MK_SHIFT_CONST(26)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_UPR_DRIBBLE_SIZE_FIELD                  (_MK_MASK_CONST(0x7) << APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_UPR_DRIBBLE_SIZE_SHIFT)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_UPR_DRIBBLE_SIZE_RANGE                  28:26
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_UPR_DRIBBLE_SIZE_WOFFSET                        0x0
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_UPR_DRIBBLE_SIZE_DEFAULT                        _MK_MASK_CONST(0x7)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_UPR_DRIBBLE_SIZE_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_UPR_DRIBBLE_SIZE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_UPR_DRIBBLE_SIZE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SERIAL_SE0_RCV_SHIFT                    _MK_SHIFT_CONST(29)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SERIAL_SE0_RCV_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SERIAL_SE0_RCV_SHIFT)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SERIAL_SE0_RCV_RANGE                    29:29
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SERIAL_SE0_RCV_WOFFSET                  0x0
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SERIAL_SE0_RCV_DEFAULT                  _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SERIAL_SE0_RCV_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SERIAL_SE0_RCV_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SERIAL_SE0_RCV_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Filter SE1
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_FILTER_SHIFT                        _MK_SHIFT_CONST(30)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_FILTER_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_FILTER_SHIFT)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_FILTER_RANGE                        30:30
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_FILTER_WOFFSET                      0x0
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_FILTER_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_FILTER_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_FILTER_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_FILTER_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// One SE1, don't allow dribble
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_DRIBBLE_FILTER_SHIFT                        _MK_SHIFT_CONST(31)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_DRIBBLE_FILTER_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_DRIBBLE_FILTER_SHIFT)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_DRIBBLE_FILTER_RANGE                        31:31
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_DRIBBLE_FILTER_WOFFSET                      0x0
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_DRIBBLE_FILTER_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_DRIBBLE_FILTER_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_DRIBBLE_FILTER_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_DRIBBLE_FILTER_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_UTMIP_FSLSRX_CFG1_0  // UTMIP full and Low speed receive config 1
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0                    _MK_ADDR_CONST(0xa1c)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_WORD_COUNT                         0x1
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_RESET_VAL                  _MK_MASK_CONST(0x2267400)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_RESET_MASK                         _MK_MASK_CONST(0x7ffffff)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_READ_MASK                  _MK_MASK_CONST(0x7ffffff)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_WRITE_MASK                         _MK_MASK_CONST(0x7ffffff)
+// Whether full speed EOP  is determined within 3(0) or 4(1) 60MHz cycles
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_EOP_LENGTH_SHIFT                  _MK_SHIFT_CONST(0)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_EOP_LENGTH_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_EOP_LENGTH_SHIFT)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_EOP_LENGTH_RANGE                  0:0
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_EOP_LENGTH_WOFFSET                        0x0
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_EOP_LENGTH_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_EOP_LENGTH_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_EOP_LENGTH_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_EOP_LENGTH_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Whether full speed uses debouncing
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_DEBOUNCE_SHIFT                    _MK_SHIFT_CONST(1)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_DEBOUNCE_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_DEBOUNCE_SHIFT)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_DEBOUNCE_RANGE                    1:1
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_DEBOUNCE_WOFFSET                  0x0
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_DEBOUNCE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_DEBOUNCE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_DEBOUNCE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_DEBOUNCE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Only look for a KK pattern, instead of KJKK
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_WEAK_SYNC_SHIFT                   _MK_SHIFT_CONST(2)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_WEAK_SYNC_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_WEAK_SYNC_SHIFT)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_WEAK_SYNC_RANGE                   2:2
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_WEAK_SYNC_WOFFSET                 0x0
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_WEAK_SYNC_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_WEAK_SYNC_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_WEAK_SYNC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_WEAK_SYNC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Allow for large dribble in full speed mode
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_LENIENT_DRIBBLE_SHIFT                     _MK_SHIFT_CONST(3)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_LENIENT_DRIBBLE_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_LENIENT_DRIBBLE_SHIFT)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_LENIENT_DRIBBLE_RANGE                     3:3
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_LENIENT_DRIBBLE_WOFFSET                   0x0
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_LENIENT_DRIBBLE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_LENIENT_DRIBBLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_LENIENT_DRIBBLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_LENIENT_DRIBBLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Allow for large dribble in low  speed mode
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_LENIENT_DRIBBLE_SHIFT                     _MK_SHIFT_CONST(4)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_LENIENT_DRIBBLE_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_LENIENT_DRIBBLE_SHIFT)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_LENIENT_DRIBBLE_RANGE                     4:4
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_LENIENT_DRIBBLE_WOFFSET                   0x0
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_LENIENT_DRIBBLE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_LENIENT_DRIBBLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_LENIENT_DRIBBLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_LENIENT_DRIBBLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Only for this number of 60MHz of SEO and Idle to end packet
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_SE0_COUNT_SHIFT                   _MK_SHIFT_CONST(5)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_SE0_COUNT_FIELD                   (_MK_MASK_CONST(0x3f) << APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_SE0_COUNT_SHIFT)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_SE0_COUNT_RANGE                   10:5
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_SE0_COUNT_WOFFSET                 0x0
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_SE0_COUNT_DEFAULT                 _MK_MASK_CONST(0x20)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_SE0_COUNT_DEFAULT_MASK                    _MK_MASK_CONST(0x3f)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_SE0_COUNT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_SE0_COUNT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Number of SEO clock cycles to block bit extraction
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EOP_START_COUNT_SHIFT                     _MK_SHIFT_CONST(11)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EOP_START_COUNT_FIELD                     (_MK_MASK_CONST(0x3f) << APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EOP_START_COUNT_SHIFT)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EOP_START_COUNT_RANGE                     16:11
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EOP_START_COUNT_WOFFSET                   0x0
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EOP_START_COUNT_DEFAULT                   _MK_MASK_CONST(0xe)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EOP_START_COUNT_DEFAULT_MASK                      _MK_MASK_CONST(0x3f)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EOP_START_COUNT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EOP_START_COUNT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Phase count on which LS bits are extracted
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EXTRACTION_COUNT_SHIFT                    _MK_SHIFT_CONST(17)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EXTRACTION_COUNT_FIELD                    (_MK_MASK_CONST(0x3f) << APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EXTRACTION_COUNT_SHIFT)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EXTRACTION_COUNT_RANGE                    22:17
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EXTRACTION_COUNT_WOFFSET                  0x0
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EXTRACTION_COUNT_DEFAULT                  _MK_MASK_CONST(0x13)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EXTRACTION_COUNT_DEFAULT_MASK                     _MK_MASK_CONST(0x3f)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EXTRACTION_COUNT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EXTRACTION_COUNT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Number of clock cycle of LS stable
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_BOUNCE_LENGTH_SHIFT                       _MK_SHIFT_CONST(23)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_BOUNCE_LENGTH_FIELD                       (_MK_MASK_CONST(0x7) << APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_BOUNCE_LENGTH_SHIFT)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_BOUNCE_LENGTH_RANGE                       25:23
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_BOUNCE_LENGTH_WOFFSET                     0x0
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_BOUNCE_LENGTH_DEFAULT                     _MK_MASK_CONST(0x4)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_BOUNCE_LENGTH_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_BOUNCE_LENGTH_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_BOUNCE_LENGTH_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Assumes line state filtering table is inclusive, not exclusive
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_EARLY_LINE_STATE_FILTER_SHIFT                        _MK_SHIFT_CONST(26)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_EARLY_LINE_STATE_FILTER_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_EARLY_LINE_STATE_FILTER_SHIFT)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_EARLY_LINE_STATE_FILTER_RANGE                        26:26
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_EARLY_LINE_STATE_FILTER_WOFFSET                      0x0
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_EARLY_LINE_STATE_FILTER_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_EARLY_LINE_STATE_FILTER_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_EARLY_LINE_STATE_FILTER_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_EARLY_LINE_STATE_FILTER_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_UTMIP_TX_CFG0_0  // UTMIP transmit config signals 
+#define APB_MISC_UTMIP_TX_CFG0_0                        _MK_ADDR_CONST(0xa20)
+#define APB_MISC_UTMIP_TX_CFG0_0_WORD_COUNT                     0x1
+#define APB_MISC_UTMIP_TX_CFG0_0_RESET_VAL                      _MK_MASK_CONST(0x10200)
+#define APB_MISC_UTMIP_TX_CFG0_0_RESET_MASK                     _MK_MASK_CONST(0xfffff)
+#define APB_MISC_UTMIP_TX_CFG0_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_READ_MASK                      _MK_MASK_CONST(0xfffff)
+#define APB_MISC_UTMIP_TX_CFG0_0_WRITE_MASK                     _MK_MASK_CONST(0xfffff)
+// Do not sent SYNC or EOP
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_SYNC_NO_EOP_SHIFT                     _MK_SHIFT_CONST(0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_SYNC_NO_EOP_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_SYNC_NO_EOP_SHIFT)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_SYNC_NO_EOP_RANGE                     0:0
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_SYNC_NO_EOP_WOFFSET                   0x0
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_SYNC_NO_EOP_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_SYNC_NO_EOP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_SYNC_NO_EOP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_SYNC_NO_EOP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// No encoding, static programming
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_ENCODING_SHIFT                        _MK_SHIFT_CONST(1)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_ENCODING_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_ENCODING_SHIFT)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_ENCODING_RANGE                        1:1
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_ENCODING_WOFFSET                      0x0
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_ENCODING_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_ENCODING_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_ENCODING_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_ENCODING_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// No bit stuffing, static programming
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_STUFFING_SHIFT                        _MK_SHIFT_CONST(2)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_STUFFING_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_STUFFING_SHIFT)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_STUFFING_RANGE                        2:2
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_STUFFING_WOFFSET                      0x0
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_STUFFING_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_STUFFING_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_STUFFING_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_STUFFING_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Sof when OpMode 2 -- not likely, for Chirp
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_ENCODE_SHIFT                   _MK_SHIFT_CONST(3)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_ENCODE_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_ENCODE_SHIFT)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_ENCODE_RANGE                   3:3
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_ENCODE_WOFFSET                 0x0
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_ENCODE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_ENCODE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_ENCODE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_ENCODE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Sof when OpMode 3 -- perhaps, when sending controller made packets
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_STUFF_SHIFT                    _MK_SHIFT_CONST(4)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_STUFF_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_STUFF_SHIFT)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_STUFF_RANGE                    4:4
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_STUFF_WOFFSET                  0x0
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_STUFF_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_STUFF_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_STUFF_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_STUFF_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// SIE, not macrocell, detects LineState change to resume
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SIE_RESUME_ON_LINESTATE_SHIFT                    _MK_SHIFT_CONST(5)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SIE_RESUME_ON_LINESTATE_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SIE_RESUME_ON_LINESTATE_SHIFT)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SIE_RESUME_ON_LINESTATE_RANGE                    5:5
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SIE_RESUME_ON_LINESTATE_WOFFSET                  0x0
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SIE_RESUME_ON_LINESTATE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SIE_RESUME_ON_LINESTATE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SIE_RESUME_ON_LINESTATE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SIE_RESUME_ON_LINESTATE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// output enable turns on  1 cycle before
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_PREAMBLE_OUTPUT_ENABLE_SHIFT                  _MK_SHIFT_CONST(6)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_PREAMBLE_OUTPUT_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_PREAMBLE_OUTPUT_ENABLE_SHIFT)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_PREAMBLE_OUTPUT_ENABLE_RANGE                  6:6
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_PREAMBLE_OUTPUT_ENABLE_WOFFSET                        0x0
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_PREAMBLE_OUTPUT_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_PREAMBLE_OUTPUT_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_PREAMBLE_OUTPUT_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_PREAMBLE_OUTPUT_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// output enable turns off 1 cycle after
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_POSTAMBLE_OUTPUT_ENABLE_SHIFT                 _MK_SHIFT_CONST(7)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_POSTAMBLE_OUTPUT_ENABLE_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_POSTAMBLE_OUTPUT_ENABLE_SHIFT)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_POSTAMBLE_OUTPUT_ENABLE_RANGE                 7:7
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_POSTAMBLE_OUTPUT_ENABLE_WOFFSET                       0x0
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_POSTAMBLE_OUTPUT_ENABLE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_POSTAMBLE_OUTPUT_ENABLE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_POSTAMBLE_OUTPUT_ENABLE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_POSTAMBLE_OUTPUT_ENABLE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Disable high speed disconnect
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_DISABLE_SHIFT                  _MK_SHIFT_CONST(8)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_DISABLE_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_DISABLE_SHIFT)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_DISABLE_RANGE                  8:8
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_DISABLE_WOFFSET                        0x0
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_DISABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_DISABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_DISABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_DISABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Only check during EOP
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_EOP_ONLY_SHIFT                 _MK_SHIFT_CONST(9)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_EOP_ONLY_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_EOP_ONLY_SHIFT)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_EOP_ONLY_RANGE                 9:9
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_EOP_ONLY_WOFFSET                       0x0
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_EOP_ONLY_DEFAULT                       _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_EOP_ONLY_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_EOP_ONLY_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_EOP_ONLY_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_TX_IPG_DLY_SHIFT                      _MK_SHIFT_CONST(10)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_TX_IPG_DLY_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_TX_IPG_DLY_SHIFT)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_TX_IPG_DLY_RANGE                      14:10
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_TX_IPG_DLY_WOFFSET                    0x0
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_TX_IPG_DLY_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_TX_IPG_DLY_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_TX_IPG_DLY_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_TX_IPG_DLY_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_READY_WAIT_FOR_VALID_SHIFT                    _MK_SHIFT_CONST(15)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_READY_WAIT_FOR_VALID_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_READY_WAIT_FOR_VALID_SHIFT)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_READY_WAIT_FOR_VALID_RANGE                    15:15
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_READY_WAIT_FOR_VALID_WOFFSET                  0x0
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_READY_WAIT_FOR_VALID_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_READY_WAIT_FOR_VALID_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_READY_WAIT_FOR_VALID_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_READY_WAIT_FOR_VALID_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Allow SOP to be source of transmit error stuffing
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FSLS_ALLOW_SOP_TX_STUFF_ERR_SHIFT                        _MK_SHIFT_CONST(16)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FSLS_ALLOW_SOP_TX_STUFF_ERR_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FSLS_ALLOW_SOP_TX_STUFF_ERR_SHIFT)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FSLS_ALLOW_SOP_TX_STUFF_ERR_RANGE                        16:16
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FSLS_ALLOW_SOP_TX_STUFF_ERR_WOFFSET                      0x0
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FSLS_ALLOW_SOP_TX_STUFF_ERR_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FSLS_ALLOW_SOP_TX_STUFF_ERR_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FSLS_ALLOW_SOP_TX_STUFF_ERR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FSLS_ALLOW_SOP_TX_STUFF_ERR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// output enable turns on  1/2 cycle before
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_OUTPUT_ENABLE_SHIFT                  _MK_SHIFT_CONST(17)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_OUTPUT_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_OUTPUT_ENABLE_SHIFT)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_OUTPUT_ENABLE_RANGE                  17:17
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_OUTPUT_ENABLE_WOFFSET                        0x0
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_OUTPUT_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_OUTPUT_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_OUTPUT_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_OUTPUT_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// output enable turns off 1/2 cycle after 
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_POSTAMBLE_OUTPUT_ENABLE_SHIFT                 _MK_SHIFT_CONST(18)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_POSTAMBLE_OUTPUT_ENABLE_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_POSTAMBLE_OUTPUT_ENABLE_SHIFT)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_POSTAMBLE_OUTPUT_ENABLE_RANGE                 18:18
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_POSTAMBLE_OUTPUT_ENABLE_WOFFSET                       0x0
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_POSTAMBLE_OUTPUT_ENABLE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_POSTAMBLE_OUTPUT_ENABLE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_POSTAMBLE_OUTPUT_ENABLE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_POSTAMBLE_OUTPUT_ENABLE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// output enable sends an initial J before sync pattern
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_J_SHIFT                      _MK_SHIFT_CONST(19)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_J_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_J_SHIFT)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_J_RANGE                      19:19
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_J_WOFFSET                    0x0
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_J_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_J_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_J_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_J_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_UTMIP_MISC_CFG0_0  // UTMIP miscellaneous configurations
+#define APB_MISC_UTMIP_MISC_CFG0_0                      _MK_ADDR_CONST(0xa24)
+#define APB_MISC_UTMIP_MISC_CFG0_0_WORD_COUNT                   0x1
+#define APB_MISC_UTMIP_MISC_CFG0_0_RESET_VAL                    _MK_MASK_CONST(0x3e00078)
+#define APB_MISC_UTMIP_MISC_CFG0_0_RESET_MASK                   _MK_MASK_CONST(0x7fffffff)
+#define APB_MISC_UTMIP_MISC_CFG0_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_READ_MASK                    _MK_MASK_CONST(0x7fffffff)
+#define APB_MISC_UTMIP_MISC_CFG0_0_WRITE_MASK                   _MK_MASK_CONST(0x7fffffff)
+// Use combinational terminations or synced through CLKXTAL
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_COMB_TERMS_SHIFT                       _MK_SHIFT_CONST(0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_COMB_TERMS_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_COMB_TERMS_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_COMB_TERMS_RANGE                       0:0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_COMB_TERMS_WOFFSET                     0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_COMB_TERMS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_COMB_TERMS_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_COMB_TERMS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_COMB_TERMS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Use free running terminations at all time
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_ALWAYS_FREE_RUNNING_TERMS_SHIFT                        _MK_SHIFT_CONST(1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_ALWAYS_FREE_RUNNING_TERMS_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_ALWAYS_FREE_RUNNING_TERMS_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_ALWAYS_FREE_RUNNING_TERMS_RANGE                        1:1
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_ALWAYS_FREE_RUNNING_TERMS_WOFFSET                      0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_ALWAYS_FREE_RUNNING_TERMS_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_ALWAYS_FREE_RUNNING_TERMS_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_ALWAYS_FREE_RUNNING_TERMS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_ALWAYS_FREE_RUNNING_TERMS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Ignore free running terminations, even when no clock
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_NEVER_FREE_RUNNING_TERMS_SHIFT                 _MK_SHIFT_CONST(2)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_NEVER_FREE_RUNNING_TERMS_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_NEVER_FREE_RUNNING_TERMS_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_NEVER_FREE_RUNNING_TERMS_RANGE                 2:2
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_NEVER_FREE_RUNNING_TERMS_WOFFSET                       0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_NEVER_FREE_RUNNING_TERMS_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_NEVER_FREE_RUNNING_TERMS_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_NEVER_FREE_RUNNING_TERMS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_NEVER_FREE_RUNNING_TERMS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Don't use free running terminations during suspend.
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_NO_FREE_ON_SUSPEND_SHIFT                       _MK_SHIFT_CONST(3)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_NO_FREE_ON_SUSPEND_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_NO_FREE_ON_SUSPEND_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_NO_FREE_ON_SUSPEND_RANGE                       3:3
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_NO_FREE_ON_SUSPEND_WOFFSET                     0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_NO_FREE_ON_SUSPEND_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_NO_FREE_ON_SUSPEND_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_NO_FREE_ON_SUSPEND_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_NO_FREE_ON_SUSPEND_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Determines if all signal need to be stable to not change a config.
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_STABLE_ALL_SHIFT                       _MK_SHIFT_CONST(4)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_STABLE_ALL_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_STABLE_ALL_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_STABLE_ALL_RANGE                       4:4
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_STABLE_ALL_WOFFSET                     0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_STABLE_ALL_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_STABLE_ALL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_STABLE_ALL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_STABLE_ALL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Number of cycles of crystal clock of signal not changing to consider stable.
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_STABLE_COUNT_SHIFT                     _MK_SHIFT_CONST(5)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_STABLE_COUNT_FIELD                     (_MK_MASK_CONST(0x7) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_STABLE_COUNT_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_STABLE_COUNT_RANGE                     7:5
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_STABLE_COUNT_WOFFSET                   0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_STABLE_COUNT_DEFAULT                   _MK_MASK_CONST(0x3)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_STABLE_COUNT_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_STABLE_COUNT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_STABLE_COUNT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Force DM pulldown active.
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DM_SHIFT                  _MK_SHIFT_CONST(8)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DM_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DM_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DM_RANGE                  8:8
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DM_WOFFSET                        0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DM_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DM_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Force DP pulldown active.
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DP_SHIFT                  _MK_SHIFT_CONST(9)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DP_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DP_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DP_RANGE                  9:9
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DP_WOFFSET                        0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DP_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DP_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Force DM pullup active.      
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DM_SHIFT                  _MK_SHIFT_CONST(10)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DM_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DM_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DM_RANGE                  10:10
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DM_WOFFSET                        0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DM_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DM_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Force DP pullup active.
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DP_SHIFT                  _MK_SHIFT_CONST(11)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DP_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DP_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DP_RANGE                  11:11
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DP_WOFFSET                        0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DP_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DP_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Force DM pulldown inactive. (Overrides FORCE_PULLDN_DM.)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DM_SHIFT                        _MK_SHIFT_CONST(12)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DM_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DM_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DM_RANGE                        12:12
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DM_WOFFSET                      0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DM_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DM_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DM_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DM_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Force DP pulldown inactive. (Overrides FORCE_PULLDN_DP.)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DP_SHIFT                        _MK_SHIFT_CONST(13)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DP_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DP_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DP_RANGE                        13:13
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DP_WOFFSET                      0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DP_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DP_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Force DM pullup inactive. (Overrides FORCE_PULLUP_DM.)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DM_SHIFT                        _MK_SHIFT_CONST(14)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DM_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DM_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DM_RANGE                        14:14
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DM_WOFFSET                      0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DM_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DM_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DM_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DM_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Force DP pullup inactive. (Overrides FORCE_PULLUP_DP.)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DP_SHIFT                        _MK_SHIFT_CONST(15)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DP_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DP_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DP_RANGE                        15:15
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DP_WOFFSET                      0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DP_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DP_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Force HS termination active.
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_TERM_SHIFT                    _MK_SHIFT_CONST(16)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_TERM_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_TERM_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_TERM_RANGE                    16:16
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_TERM_WOFFSET                  0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_TERM_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_TERM_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_TERM_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_TERM_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Force HS termination inactive.
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_HS_TERM_SHIFT                  _MK_SHIFT_CONST(17)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_HS_TERM_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_HS_TERM_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_HS_TERM_RANGE                  17:17
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_HS_TERM_WOFFSET                        0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_HS_TERM_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_HS_TERM_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_HS_TERM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_HS_TERM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Force HS clock always on.
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_CLOCK_ON_SHIFT                        _MK_SHIFT_CONST(18)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_CLOCK_ON_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_CLOCK_ON_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_CLOCK_ON_RANGE                        18:18
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_CLOCK_ON_WOFFSET                      0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_CLOCK_ON_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_CLOCK_ON_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_CLOCK_ON_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_CLOCK_ON_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Force error insertion into RX path. (Used for IOBIST.)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_INJECT_ERROR_TYPE_SHIFT                        _MK_SHIFT_CONST(19)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_INJECT_ERROR_TYPE_FIELD                        (_MK_MASK_CONST(0x3) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_INJECT_ERROR_TYPE_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_INJECT_ERROR_TYPE_RANGE                        20:19
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_INJECT_ERROR_TYPE_WOFFSET                      0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_INJECT_ERROR_TYPE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_INJECT_ERROR_TYPE_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_INJECT_ERROR_TYPE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_INJECT_ERROR_TYPE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_INJECT_ERROR_TYPE_DISABLE                      _MK_ENUM_CONST(0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_INJECT_ERROR_TYPE_BIT_ERR                      _MK_ENUM_CONST(1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_INJECT_ERROR_TYPE_RX_ERR                       _MK_ENUM_CONST(2)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_INJECT_ERROR_TYPE_BIT_RX_ERR                   _MK_ENUM_CONST(3)
+
+// Don't block changes for 4ms when going from LS to FS (should not happen)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_LS_TO_FS_SKIP_4MS_SHIFT                        _MK_SHIFT_CONST(21)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_LS_TO_FS_SKIP_4MS_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_LS_TO_FS_SKIP_4MS_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_LS_TO_FS_SKIP_4MS_RANGE                        21:21
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_LS_TO_FS_SKIP_4MS_WOFFSET                      0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_LS_TO_FS_SKIP_4MS_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_LS_TO_FS_SKIP_4MS_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_LS_TO_FS_SKIP_4MS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_LS_TO_FS_SKIP_4MS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Suspend exit requires edge or simply a value...
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_SUSPEND_EXIT_ON_EDGE_SHIFT                     _MK_SHIFT_CONST(22)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_SUSPEND_EXIT_ON_EDGE_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_SUSPEND_EXIT_ON_EDGE_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_SUSPEND_EXIT_ON_EDGE_RANGE                     22:22
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_SUSPEND_EXIT_ON_EDGE_WOFFSET                   0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_SUSPEND_EXIT_ON_EDGE_DEFAULT                   _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_SUSPEND_EXIT_ON_EDGE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_SUSPEND_EXIT_ON_EDGE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_SUSPEND_EXIT_ON_EDGE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_FS_DISABLE_ON_DEV_CHIRP_SHIFT                    _MK_SHIFT_CONST(23)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_FS_DISABLE_ON_DEV_CHIRP_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_FS_DISABLE_ON_DEV_CHIRP_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_FS_DISABLE_ON_DEV_CHIRP_RANGE                    23:23
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_FS_DISABLE_ON_DEV_CHIRP_WOFFSET                  0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_FS_DISABLE_ON_DEV_CHIRP_DEFAULT                  _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_FS_DISABLE_ON_DEV_CHIRP_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_FS_DISABLE_ON_DEV_CHIRP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_FS_DISABLE_ON_DEV_CHIRP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_ALLOW_LS_ON_SOFT_DISCON_SHIFT                  _MK_SHIFT_CONST(24)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_ALLOW_LS_ON_SOFT_DISCON_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_ALLOW_LS_ON_SOFT_DISCON_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_ALLOW_LS_ON_SOFT_DISCON_RANGE                  24:24
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_ALLOW_LS_ON_SOFT_DISCON_WOFFSET                        0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_ALLOW_LS_ON_SOFT_DISCON_DEFAULT                        _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_ALLOW_LS_ON_SOFT_DISCON_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_ALLOW_LS_ON_SOFT_DISCON_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_ALLOW_LS_ON_SOFT_DISCON_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_KEEP_XCVR_PD_ON_SOFT_DISCON_SHIFT                      _MK_SHIFT_CONST(25)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_KEEP_XCVR_PD_ON_SOFT_DISCON_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_KEEP_XCVR_PD_ON_SOFT_DISCON_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_KEEP_XCVR_PD_ON_SOFT_DISCON_RANGE                      25:25
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_KEEP_XCVR_PD_ON_SOFT_DISCON_WOFFSET                    0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_KEEP_XCVR_PD_ON_SOFT_DISCON_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_KEEP_XCVR_PD_ON_SOFT_DISCON_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_KEEP_XCVR_PD_ON_SOFT_DISCON_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_KEEP_XCVR_PD_ON_SOFT_DISCON_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Use DP/DM as obs bus
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_SHIFT                     _MK_SHIFT_CONST(26)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_RANGE                     26:26
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_WOFFSET                   0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Select DP/DM obs signals
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_SEL_SHIFT                 _MK_SHIFT_CONST(27)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_SEL_FIELD                 (_MK_MASK_CONST(0xf) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_SEL_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_SEL_RANGE                 30:27
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_SEL_WOFFSET                       0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_SEL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_SEL_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_SEL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_SEL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_UTMIP_MISC_CFG1_0  // UTMIP miscellaneous configurations
+#define APB_MISC_UTMIP_MISC_CFG1_0                      _MK_ADDR_CONST(0xa28)
+#define APB_MISC_UTMIP_MISC_CFG1_0_WORD_COUNT                   0x1
+#define APB_MISC_UTMIP_MISC_CFG1_0_RESET_VAL                    _MK_MASK_CONST(0x198024)
+#define APB_MISC_UTMIP_MISC_CFG1_0_RESET_MASK                   _MK_MASK_CONST(0x3fffffff)
+#define APB_MISC_UTMIP_MISC_CFG1_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_READ_MASK                    _MK_MASK_CONST(0x3fffffff)
+#define APB_MISC_UTMIP_MISC_CFG1_0_WRITE_MASK                   _MK_MASK_CONST(0x3fffffff)
+// Bit 0: 0: 0xa5 -> treat as KeepAlive 
+//        1: treat as regular packet 
+// Bit 1: 0: Turn on FS EOP detection
+//        1: Turn off FS EOP detection
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_XCVRSEL3_SHIFT                 _MK_SHIFT_CONST(0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_XCVRSEL3_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_XCVRSEL3_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_XCVRSEL3_RANGE                 1:0
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_XCVRSEL3_WOFFSET                       0x0
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_XCVRSEL3_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_XCVRSEL3_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_XCVRSEL3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_XCVRSEL3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_SUSPEND_TERMSEL_SHIFT                  _MK_SHIFT_CONST(2)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_SUSPEND_TERMSEL_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_SUSPEND_TERMSEL_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_SUSPEND_TERMSEL_RANGE                  2:2
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_SUSPEND_TERMSEL_WOFFSET                        0x0
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_SUSPEND_TERMSEL_DEFAULT                        _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_SUSPEND_TERMSEL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_SUSPEND_TERMSEL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_SUSPEND_TERMSEL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FLIP_FSLS_POLARITY_SHIFT                       _MK_SHIFT_CONST(3)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FLIP_FSLS_POLARITY_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FLIP_FSLS_POLARITY_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FLIP_FSLS_POLARITY_RANGE                       3:3
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FLIP_FSLS_POLARITY_WOFFSET                     0x0
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FLIP_FSLS_POLARITY_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FLIP_FSLS_POLARITY_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FLIP_FSLS_POLARITY_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FLIP_FSLS_POLARITY_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_EN_SHIFT                  _MK_SHIFT_CONST(4)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_EN_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_EN_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_EN_RANGE                  4:4
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_EN_WOFFSET                        0x0
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_EN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_CLR_SHIFT                 _MK_SHIFT_CONST(5)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_CLR_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_CLR_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_CLR_RANGE                 5:5
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_CLR_WOFFSET                       0x0
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_CLR_DEFAULT                       _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_CLR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_CLR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_CLR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// WRONG! This should be 1ms -> 0x50
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PLLU_STABLE_COUNT_SHIFT                        _MK_SHIFT_CONST(6)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PLLU_STABLE_COUNT_FIELD                        (_MK_MASK_CONST(0xfff) << APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PLLU_STABLE_COUNT_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PLLU_STABLE_COUNT_RANGE                        17:6
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PLLU_STABLE_COUNT_WOFFSET                      0x0
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PLLU_STABLE_COUNT_DEFAULT                      _MK_MASK_CONST(0x600)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PLLU_STABLE_COUNT_DEFAULT_MASK                 _MK_MASK_CONST(0xfff)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PLLU_STABLE_COUNT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PLLU_STABLE_COUNT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// 5 us / (1/19.2MHz) = 96 / 16 = 6
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT                     _MK_SHIFT_CONST(18)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PLL_ACTIVE_DLY_COUNT_FIELD                     (_MK_MASK_CONST(0x1f) << APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PLL_ACTIVE_DLY_COUNT_RANGE                     22:18
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PLL_ACTIVE_DLY_COUNT_WOFFSET                   0x0
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PLL_ACTIVE_DLY_COUNT_DEFAULT                   _MK_MASK_CONST(0x6)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PLL_ACTIVE_DLY_COUNT_DEFAULT_MASK                      _MK_MASK_CONST(0x1f)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PLL_ACTIVE_DLY_COUNT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PLL_ACTIVE_DLY_COUNT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FORCE_IOBIST_CLK_ON_SHIFT                      _MK_SHIFT_CONST(23)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FORCE_IOBIST_CLK_ON_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FORCE_IOBIST_CLK_ON_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FORCE_IOBIST_CLK_ON_RANGE                      23:23
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FORCE_IOBIST_CLK_ON_WOFFSET                    0x0
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FORCE_IOBIST_CLK_ON_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FORCE_IOBIST_CLK_ON_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FORCE_IOBIST_CLK_ON_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FORCE_IOBIST_CLK_ON_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FSLS_TDM_SHIFT                 _MK_SHIFT_CONST(24)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FSLS_TDM_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FSLS_TDM_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FSLS_TDM_RANGE                 24:24
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FSLS_TDM_WOFFSET                       0x0
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FSLS_TDM_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FSLS_TDM_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FSLS_TDM_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FSLS_TDM_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_OBS_SEL_SHIFT                  _MK_SHIFT_CONST(25)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_OBS_SEL_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_OBS_SEL_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_OBS_SEL_RANGE                  26:25
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_OBS_SEL_WOFFSET                        0x0
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_OBS_SEL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_OBS_SEL_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_OBS_SEL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_OBS_SEL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// 0: Use FS filtering on line state when XcvrSel=3
+// 1: Use LS filtering on line state when XcvrSel=3
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_XCVRSEL3_SHIFT                       _MK_SHIFT_CONST(27)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_XCVRSEL3_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_XCVRSEL3_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_XCVRSEL3_RANGE                       27:27
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_XCVRSEL3_WOFFSET                     0x0
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_XCVRSEL3_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_XCVRSEL3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_XCVRSEL3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_XCVRSEL3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Use neg edge sync for linestate
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_NEG_SHIFT                    _MK_SHIFT_CONST(28)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_NEG_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_NEG_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_NEG_RANGE                    28:28
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_NEG_WOFFSET                  0x0
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_NEG_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_NEG_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_NEG_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_NEG_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Bypass LineState reclocking logic
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_BYPASS_SHIFT                 _MK_SHIFT_CONST(29)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_BYPASS_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_BYPASS_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_BYPASS_RANGE                 29:29
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_BYPASS_WOFFSET                       0x0
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_BYPASS_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_BYPASS_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_BYPASS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_BYPASS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_UTMIP_DEBOUNCE_CFG0_0  // UTMIP Avalid and Bvalid debounce
+#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0                  _MK_ADDR_CONST(0xa2c)
+#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_WORD_COUNT                       0x1
+#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_RESET_VAL                        _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+// simulation value -- Used for interrupts
+#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_A_SHIFT                      _MK_SHIFT_CONST(0)
+#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_A_FIELD                      (_MK_MASK_CONST(0xffff) << APB_MISC_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_A_SHIFT)
+#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_A_RANGE                      15:0
+#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_A_WOFFSET                    0x0
+#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_A_DEFAULT                    _MK_MASK_CONST(0xffff)
+#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_A_DEFAULT_MASK                       _MK_MASK_CONST(0xffff)
+#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_A_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_A_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// simulation value -- Used for interrupts
+#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_B_SHIFT                      _MK_SHIFT_CONST(16)
+#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_B_FIELD                      (_MK_MASK_CONST(0xffff) << APB_MISC_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_B_SHIFT)
+#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_B_RANGE                      31:16
+#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_B_WOFFSET                    0x0
+#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_B_DEFAULT                    _MK_MASK_CONST(0xffff)
+#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_B_DEFAULT_MASK                       _MK_MASK_CONST(0xffff)
+#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_B_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_B_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_UTMIP_BAT_CHRG_CFG0_0  // UTMIP battery charger configuration
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0                  _MK_ADDR_CONST(0xa30)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_WORD_COUNT                       0x1
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_RESET_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_READ_MASK                        _MK_MASK_CONST(0x1f)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_WRITE_MASK                       _MK_MASK_CONST(0x1f)
+// Power down charger circuit
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_PD_CHRG_SHIFT                      _MK_SHIFT_CONST(0)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_PD_CHRG_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_PD_CHRG_SHIFT)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_PD_CHRG_RANGE                      0:0
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_PD_CHRG_WOFFSET                    0x0
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_PD_CHRG_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_PD_CHRG_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_PD_CHRG_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_PD_CHRG_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SINK_EN_SHIFT                   _MK_SHIFT_CONST(1)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SINK_EN_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SINK_EN_SHIFT)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SINK_EN_RANGE                   1:1
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SINK_EN_WOFFSET                 0x0
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SINK_EN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SINK_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SINK_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SINK_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SINK_EN_SHIFT                   _MK_SHIFT_CONST(2)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SINK_EN_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SINK_EN_SHIFT)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SINK_EN_RANGE                   2:2
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SINK_EN_WOFFSET                 0x0
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SINK_EN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SINK_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SINK_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SINK_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SRC_EN_SHIFT                    _MK_SHIFT_CONST(3)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SRC_EN_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SRC_EN_SHIFT)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SRC_EN_RANGE                    3:3
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SRC_EN_WOFFSET                  0x0
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SRC_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SRC_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SRC_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SRC_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SRC_EN_SHIFT                    _MK_SHIFT_CONST(4)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SRC_EN_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SRC_EN_SHIFT)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SRC_EN_RANGE                    4:4
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SRC_EN_WOFFSET                  0x0
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SRC_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SRC_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SRC_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SRC_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_UTMIP_SPARE_CFG0_0  // Utmip spare configuration bits 
+#define APB_MISC_UTMIP_SPARE_CFG0_0                     _MK_ADDR_CONST(0xa34)
+#define APB_MISC_UTMIP_SPARE_CFG0_0_WORD_COUNT                  0x1
+#define APB_MISC_UTMIP_SPARE_CFG0_0_RESET_VAL                   _MK_MASK_CONST(0xffff0000)
+#define APB_MISC_UTMIP_SPARE_CFG0_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_UTMIP_SPARE_CFG0_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_SPARE_CFG0_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_SPARE_CFG0_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_UTMIP_SPARE_CFG0_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+// Spare register bits
+// 0: HS_RX_IPG_ERROR_ENABLE
+// 1: HS_RX_FLUSH_ALAP. Flush as late as possible
+// 2: HS_RX_LATE_SQUELCH. Delay Squelch by 1 CLK480 cycle.
+// 31 to 3: Reserved
+#define APB_MISC_UTMIP_SPARE_CFG0_0_UTMIP_SPARE_SHIFT                   _MK_SHIFT_CONST(0)
+#define APB_MISC_UTMIP_SPARE_CFG0_0_UTMIP_SPARE_FIELD                   (_MK_MASK_CONST(0xffffffff) << APB_MISC_UTMIP_SPARE_CFG0_0_UTMIP_SPARE_SHIFT)
+#define APB_MISC_UTMIP_SPARE_CFG0_0_UTMIP_SPARE_RANGE                   31:0
+#define APB_MISC_UTMIP_SPARE_CFG0_0_UTMIP_SPARE_WOFFSET                 0x0
+#define APB_MISC_UTMIP_SPARE_CFG0_0_UTMIP_SPARE_DEFAULT                 _MK_MASK_CONST(0xffff0000)
+#define APB_MISC_UTMIP_SPARE_CFG0_0_UTMIP_SPARE_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_UTMIP_SPARE_CFG0_0_UTMIP_SPARE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_SPARE_CFG0_0_UTMIP_SPARE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_SPARE_CFG0_0_UTMIP_SPARE_INIT_ENUM                       -65536
+
+
+//
+// REGISTER LIST
+//
+#define LIST_ARAPB_MISC_REGS(_op_) \
+_op_(APB_MISC_PP_STRAPPING_OPT_A_0) \
+_op_(APB_MISC_PP_TRISTATE_REG_A_0) \
+_op_(APB_MISC_PP_TRISTATE_REG_B_0) \
+_op_(APB_MISC_PP_TRISTATE_REG_C_0) \
+_op_(APB_MISC_PP_TRISTATE_REG_D_0) \
+_op_(APB_MISC_PP_CONFIG_CTL_0) \
+_op_(APB_MISC_PP_MISC_USB_OTG_0) \
+_op_(APB_MISC_PP_XMB_CSR_0) \
+_op_(APB_MISC_PP_XMB_NOR_FLASH_CFG_0) \
+_op_(APB_MISC_PP_XMB_MIO_CFG_0) \
+_op_(APB_MISC_PP_USB_PHY_VCTL_REG_0) \
+_op_(APB_MISC_PP_USB_PHY_PARAM_0) \
+_op_(APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0) \
+_op_(APB_MISC_PP_USB_PHY_SELF_TEST_0) \
+_op_(APB_MISC_PP_USB_PHY_VBUS_SENSORS_0) \
+_op_(APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0) \
+_op_(APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0) \
+_op_(APB_MISC_PP_MISC_SAVE_THE_DAY_0) \
+_op_(APB_MISC_PP_PIN_MUX_CTL_A_0) \
+_op_(APB_MISC_PP_PIN_MUX_CTL_B_0) \
+_op_(APB_MISC_PP_PIN_MUX_CTL_C_0) \
+_op_(APB_MISC_PP_PIN_MUX_CTL_D_0) \
+_op_(APB_MISC_PP_PIN_MUX_CTL_E_0) \
+_op_(APB_MISC_PP_PIN_MUX_CTL_F_0) \
+_op_(APB_MISC_PP_PIN_MUX_CTL_G_0) \
+_op_(APB_MISC_PP_PIN_MUX_CTL_H_0) \
+_op_(APB_MISC_PP_PULLUPDOWN_REG_A_0) \
+_op_(APB_MISC_PP_PULLUPDOWN_REG_B_0) \
+_op_(APB_MISC_PP_PULLUPDOWN_REG_C_0) \
+_op_(APB_MISC_PP_PULLUPDOWN_REG_D_0) \
+_op_(APB_MISC_PP_PULLUPDOWN_REG_E_0) \
+_op_(APB_MISC_ASYNC_COREPWRCONFIG_0) \
+_op_(APB_MISC_ASYNC_DLYCTRL_0) \
+_op_(APB_MISC_ASYNC_CLKMNTREN_0) \
+_op_(APB_MISC_ASYNC_EMCPADEN_0) \
+_op_(APB_MISC_ASYNC_EMCPADCTRL_0) \
+_op_(APB_MISC_ASYNC_MEMPADCAL1_0) \
+_op_(APB_MISC_ASYNC_LCDPADCTRL_0) \
+_op_(APB_MISC_ASYNC_LCDPADCAL1_0) \
+_op_(APB_MISC_ASYNC_VIPADCTRL_0) \
+_op_(APB_MISC_ASYNC_VIPADCAL1_0) \
+_op_(APB_MISC_ASYNC_VCLKCTRL_0) \
+_op_(APB_MISC_ASYNC_TVDACVHSYNCCTRL_0) \
+_op_(APB_MISC_ASYNC_TVDACCNTL_0) \
+_op_(APB_MISC_ASYNC_TVDACSTATUS_0) \
+_op_(APB_MISC_ASYNC_TVDACDINCONFIG_0) \
+_op_(APB_MISC_ASYNC_INT_STATUS_0) \
+_op_(APB_MISC_ASYNC_INT_MASK_0) \
+_op_(APB_MISC_ASYNC_INT_POLARITY_0) \
+_op_(APB_MISC_ASYNC_INT_TYPE_SELECT_0) \
+_op_(APB_MISC_GP_MODEREG_0) \
+_op_(APB_MISC_GP_HIDREV_0) \
+_op_(APB_MISC_GP_ASDBGREG_0) \
+_op_(APB_MISC_GP_RESERVEREG_0) \
+_op_(APB_MISC_GP_OBSCTRL_0) \
+_op_(APB_MISC_GP_OBSDATA_0) \
+_op_(APB_MISC_GP_EFUSEREQ_0) \
+_op_(APB_MISC_GP_EFUSEOFF_0) \
+_op_(APB_MISC_GP_EFUSEWRDAT_0) \
+_op_(APB_MISC_GP_EFUSERDDAT_0) \
+_op_(APB_MISC_GP_EFUSEVAL1_0) \
+_op_(APB_MISC_GP_EFUSEVAL2_0) \
+_op_(APB_MISC_GP_EFUSEBYPASSID_0) \
+_op_(APB_MISC_GP_BRDCLK_TRIM_0) \
+_op_(APB_MISC_GP_ASDBGREG2_0) \
+_op_(APB_MISC_GP_EMU_REVID_0) \
+_op_(APB_MISC_GP_TRANSACTOR_SCRATCH_0) \
+_op_(APB_MISC_GP_AOCFG1PADCTRL_0) \
+_op_(APB_MISC_GP_AOCFG2PADCTRL_0) \
+_op_(APB_MISC_GP_ATCFG1PADCTRL_0) \
+_op_(APB_MISC_GP_ATCFG2PADCTRL_0) \
+_op_(APB_MISC_GP_CDEV1CFGPADCTRL_0) \
+_op_(APB_MISC_GP_CDEV2CFGPADCTRL_0) \
+_op_(APB_MISC_GP_CSUSCFGPADCTRL_0) \
+_op_(APB_MISC_GP_DAP1CFGPADCTRL_0) \
+_op_(APB_MISC_GP_DAP2CFGPADCTRL_0) \
+_op_(APB_MISC_GP_DAP3CFGPADCTRL_0) \
+_op_(APB_MISC_GP_DAP4CFGPADCTRL_0) \
+_op_(APB_MISC_GP_DBGCFGPADCTRL_0) \
+_op_(APB_MISC_GP_LCDCFG1PADCTRL_0) \
+_op_(APB_MISC_GP_LCDCFG2PADCTRL_0) \
+_op_(APB_MISC_GP_SDIO2CFGPADCTRL_0) \
+_op_(APB_MISC_GP_SDIO3CFGPADCTRL_0) \
+_op_(APB_MISC_GP_SPICFGPADCTRL_0) \
+_op_(APB_MISC_GP_UAACFGPADCTRL_0) \
+_op_(APB_MISC_GP_UABCFGPADCTRL_0) \
+_op_(APB_MISC_GP_UART2CFGPADCTRL_0) \
+_op_(APB_MISC_GP_UART3CFGPADCTRL_0) \
+_op_(APB_MISC_GP_VICFG1PADCTRL_0) \
+_op_(APB_MISC_GP_VICFG2PADCTRL_0) \
+_op_(APB_MISC_GP_XM2CFGAPADCTRL_0) \
+_op_(APB_MISC_GP_XM2CFGCPADCTRL_0) \
+_op_(APB_MISC_GP_XM2CFGDPADCTRL_0) \
+_op_(APB_MISC_GP_XM2CLKCFGPADCTRL_0) \
+_op_(APB_MISC_GP_MEMCOMPPADCTRL_0) \
+_op_(APB_MISC_GP_PADCTL_DFT_0) \
+_op_(APB_MISC_UTMIP_PLL_CFG0_0) \
+_op_(APB_MISC_UTMIP_PLL_CFG1_0) \
+_op_(APB_MISC_UTMIP_XCVR_CFG0_0) \
+_op_(APB_MISC_UTMIP_BIAS_CFG0_0) \
+_op_(APB_MISC_UTMIP_HSRX_CFG0_0) \
+_op_(APB_MISC_UTMIP_HSRX_CFG1_0) \
+_op_(APB_MISC_UTMIP_FSLSRX_CFG0_0) \
+_op_(APB_MISC_UTMIP_FSLSRX_CFG1_0) \
+_op_(APB_MISC_UTMIP_TX_CFG0_0) \
+_op_(APB_MISC_UTMIP_MISC_CFG0_0) \
+_op_(APB_MISC_UTMIP_MISC_CFG1_0) \
+_op_(APB_MISC_UTMIP_DEBOUNCE_CFG0_0) \
+_op_(APB_MISC_UTMIP_BAT_CHRG_CFG0_0) \
+_op_(APB_MISC_UTMIP_SPARE_CFG0_0)
+
+
+//
+// ADDRESS SPACES
+//
+
+#define BASE_ADDRESS_APB_MISC   0x00000000
+#define BASE_ADDRESS_APB_MISC_PP        0x00000000
+#define BASE_ADDRESS_APB_MISC_ASYNC     0x00000400
+#define BASE_ADDRESS_APB_MISC_GP        0x00000800
+#define BASE_ADDRESS_APB_MISC_UTMIP     0x00000a00
+
+//
+// ARAPB_MISC REGISTER BANKS
+//
+
+#define APB_MISC_PP0_FIRST_REG 0x0008 // APB_MISC_PP_STRAPPING_OPT_A_0
+#define APB_MISC_PP0_LAST_REG 0x0008 // APB_MISC_PP_STRAPPING_OPT_A_0
+#define APB_MISC_PP1_FIRST_REG 0x0014 // APB_MISC_PP_TRISTATE_REG_A_0
+#define APB_MISC_PP1_LAST_REG 0x0028 // APB_MISC_PP_MISC_USB_OTG_0
+#define APB_MISC_PP2_FIRST_REG 0x0030 // APB_MISC_PP_XMB_CSR_0
+#define APB_MISC_PP2_LAST_REG 0x0034 // APB_MISC_PP_XMB_NOR_FLASH_CFG_0
+#define APB_MISC_PP3_FIRST_REG 0x0040 // APB_MISC_PP_XMB_MIO_CFG_0
+#define APB_MISC_PP3_LAST_REG 0x0040 // APB_MISC_PP_XMB_MIO_CFG_0
+#define APB_MISC_PP4_FIRST_REG 0x0060 // APB_MISC_PP_USB_PHY_VCTL_REG_0
+#define APB_MISC_PP4_LAST_REG 0x00b0 // APB_MISC_PP_PULLUPDOWN_REG_E_0
+#define APB_MISC_ASYNC0_FIRST_REG 0x0400 // APB_MISC_ASYNC_COREPWRCONFIG_0
+#define APB_MISC_ASYNC0_LAST_REG 0x0400 // APB_MISC_ASYNC_COREPWRCONFIG_0
+#define APB_MISC_ASYNC1_FIRST_REG 0x0408 // APB_MISC_ASYNC_DLYCTRL_0
+#define APB_MISC_ASYNC1_LAST_REG 0x042c // APB_MISC_ASYNC_VCLKCTRL_0
+#define APB_MISC_ASYNC2_FIRST_REG 0x0438 // APB_MISC_ASYNC_TVDACVHSYNCCTRL_0
+#define APB_MISC_ASYNC2_LAST_REG 0x0454 // APB_MISC_ASYNC_INT_TYPE_SELECT_0
+#define APB_MISC_GP0_FIRST_REG 0x0800 // APB_MISC_GP_MODEREG_0
+#define APB_MISC_GP0_LAST_REG 0x0804 // APB_MISC_GP_HIDREV_0
+#define APB_MISC_GP1_FIRST_REG 0x0810 // APB_MISC_GP_ASDBGREG_0
+#define APB_MISC_GP1_LAST_REG 0x083c // APB_MISC_GP_BRDCLK_TRIM_0
+#define APB_MISC_GP2_FIRST_REG 0x0858 // APB_MISC_GP_ASDBGREG2_0
+#define APB_MISC_GP2_LAST_REG 0x0858 // APB_MISC_GP_ASDBGREG2_0
+#define APB_MISC_GP3_FIRST_REG 0x0860 // APB_MISC_GP_EMU_REVID_0
+#define APB_MISC_GP3_LAST_REG 0x08d8 // APB_MISC_GP_PADCTL_DFT_0
+#define APB_MISC_UTMIP0_FIRST_REG 0x0a00 // APB_MISC_UTMIP_PLL_CFG0_0
+#define APB_MISC_UTMIP0_LAST_REG 0x0a34 // APB_MISC_UTMIP_SPARE_CFG0_0
+
+#ifndef _MK_SHIFT_CONST
+  #define _MK_SHIFT_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_MASK_CONST
+  #define _MK_MASK_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_ENUM_CONST
+  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
+#endif
+#ifndef _MK_ADDR_CONST
+  #define _MK_ADDR_CONST(_constant_) _constant_
+#endif
+
+#endif // ifndef ___ARAPB_MISC_H_INC_
diff --git a/arch/arm/mach-tegra/include/ap15/arapbdma.h b/arch/arm/mach-tegra/include/ap15/arapbdma.h
new file mode 100644
index 000000000000..860ca6da52aa
--- /dev/null
+++ b/arch/arm/mach-tegra/include/ap15/arapbdma.h
@@ -0,0 +1,2466 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+//
+// DO NOT EDIT - generated by simspec!
+//
+
+#ifndef ___ARAPBDMA_H_INC_
+#define ___ARAPBDMA_H_INC_
+
+// Register APBDMA_COMMAND_0  
+#define APBDMA_COMMAND_0                        _MK_ADDR_CONST(0x0)
+#define APBDMA_COMMAND_0_WORD_COUNT                     0x1
+#define APBDMA_COMMAND_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define APBDMA_COMMAND_0_RESET_MASK                     _MK_MASK_CONST(0x80000000)
+#define APBDMA_COMMAND_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define APBDMA_COMMAND_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_COMMAND_0_READ_MASK                      _MK_MASK_CONST(0x80000000)
+#define APBDMA_COMMAND_0_WRITE_MASK                     _MK_MASK_CONST(0x80000000)
+// Enables Global APB-DMA  
+#define APBDMA_COMMAND_0_GEN_SHIFT                      _MK_SHIFT_CONST(31)
+#define APBDMA_COMMAND_0_GEN_FIELD                      (_MK_MASK_CONST(0x1) << APBDMA_COMMAND_0_GEN_SHIFT)
+#define APBDMA_COMMAND_0_GEN_RANGE                      31:31
+#define APBDMA_COMMAND_0_GEN_WOFFSET                    0x0
+#define APBDMA_COMMAND_0_GEN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_COMMAND_0_GEN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMA_COMMAND_0_GEN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_COMMAND_0_GEN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMA_COMMAND_0_GEN_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDMA_COMMAND_0_GEN_ENABLE                     _MK_ENUM_CONST(1)
+
+
+// Register APBDMA_STATUS_0  
+#define APBDMA_STATUS_0                 _MK_ADDR_CONST(0x4)
+#define APBDMA_STATUS_0_WORD_COUNT                      0x1
+#define APBDMA_STATUS_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define APBDMA_STATUS_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define APBDMA_STATUS_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
+// DMA channel15  status 
+#define APBDMA_STATUS_0_BSY_15_SHIFT                    _MK_SHIFT_CONST(31)
+#define APBDMA_STATUS_0_BSY_15_FIELD                    (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_BSY_15_SHIFT)
+#define APBDMA_STATUS_0_BSY_15_RANGE                    31:31
+#define APBDMA_STATUS_0_BSY_15_WOFFSET                  0x0
+#define APBDMA_STATUS_0_BSY_15_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_15_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_BSY_15_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_15_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_15_NOT_BUSY                 _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_BSY_15_BUSY                     _MK_ENUM_CONST(1)
+
+// DMA channel14  status
+#define APBDMA_STATUS_0_BSY_14_SHIFT                    _MK_SHIFT_CONST(30)
+#define APBDMA_STATUS_0_BSY_14_FIELD                    (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_BSY_14_SHIFT)
+#define APBDMA_STATUS_0_BSY_14_RANGE                    30:30
+#define APBDMA_STATUS_0_BSY_14_WOFFSET                  0x0
+#define APBDMA_STATUS_0_BSY_14_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_14_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_BSY_14_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_14_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_14_NOT_BUSY                 _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_BSY_14_BUSY                     _MK_ENUM_CONST(1)
+
+// DMA channel13  status 
+#define APBDMA_STATUS_0_BSY_13_SHIFT                    _MK_SHIFT_CONST(29)
+#define APBDMA_STATUS_0_BSY_13_FIELD                    (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_BSY_13_SHIFT)
+#define APBDMA_STATUS_0_BSY_13_RANGE                    29:29
+#define APBDMA_STATUS_0_BSY_13_WOFFSET                  0x0
+#define APBDMA_STATUS_0_BSY_13_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_13_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_BSY_13_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_13_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_13_NOT_BUSY                 _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_BSY_13_BUSY                     _MK_ENUM_CONST(1)
+
+// DMA channel12  status 
+#define APBDMA_STATUS_0_BSY_12_SHIFT                    _MK_SHIFT_CONST(28)
+#define APBDMA_STATUS_0_BSY_12_FIELD                    (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_BSY_12_SHIFT)
+#define APBDMA_STATUS_0_BSY_12_RANGE                    28:28
+#define APBDMA_STATUS_0_BSY_12_WOFFSET                  0x0
+#define APBDMA_STATUS_0_BSY_12_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_12_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_BSY_12_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_12_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_12_NOT_BUSY                 _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_BSY_12_BUSY                     _MK_ENUM_CONST(1)
+
+// DMA channel11  status 
+#define APBDMA_STATUS_0_BSY_11_SHIFT                    _MK_SHIFT_CONST(27)
+#define APBDMA_STATUS_0_BSY_11_FIELD                    (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_BSY_11_SHIFT)
+#define APBDMA_STATUS_0_BSY_11_RANGE                    27:27
+#define APBDMA_STATUS_0_BSY_11_WOFFSET                  0x0
+#define APBDMA_STATUS_0_BSY_11_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_11_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_BSY_11_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_11_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_11_NOT_BUSY                 _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_BSY_11_BUSY                     _MK_ENUM_CONST(1)
+
+// DMA channel10  status
+#define APBDMA_STATUS_0_BSY_10_SHIFT                    _MK_SHIFT_CONST(26)
+#define APBDMA_STATUS_0_BSY_10_FIELD                    (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_BSY_10_SHIFT)
+#define APBDMA_STATUS_0_BSY_10_RANGE                    26:26
+#define APBDMA_STATUS_0_BSY_10_WOFFSET                  0x0
+#define APBDMA_STATUS_0_BSY_10_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_10_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_BSY_10_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_10_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_10_NOT_BUSY                 _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_BSY_10_BUSY                     _MK_ENUM_CONST(1)
+
+// DMA channel9  status 
+#define APBDMA_STATUS_0_BSY_9_SHIFT                     _MK_SHIFT_CONST(25)
+#define APBDMA_STATUS_0_BSY_9_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_BSY_9_SHIFT)
+#define APBDMA_STATUS_0_BSY_9_RANGE                     25:25
+#define APBDMA_STATUS_0_BSY_9_WOFFSET                   0x0
+#define APBDMA_STATUS_0_BSY_9_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_9_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_BSY_9_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_9_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_9_NOT_BUSY                  _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_BSY_9_BUSY                      _MK_ENUM_CONST(1)
+
+// DMA channel8  status 
+#define APBDMA_STATUS_0_BSY_8_SHIFT                     _MK_SHIFT_CONST(24)
+#define APBDMA_STATUS_0_BSY_8_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_BSY_8_SHIFT)
+#define APBDMA_STATUS_0_BSY_8_RANGE                     24:24
+#define APBDMA_STATUS_0_BSY_8_WOFFSET                   0x0
+#define APBDMA_STATUS_0_BSY_8_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_8_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_BSY_8_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_8_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_8_NOT_BUSY                  _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_BSY_8_BUSY                      _MK_ENUM_CONST(1)
+
+// DMA channel7  status 
+#define APBDMA_STATUS_0_BSY_7_SHIFT                     _MK_SHIFT_CONST(23)
+#define APBDMA_STATUS_0_BSY_7_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_BSY_7_SHIFT)
+#define APBDMA_STATUS_0_BSY_7_RANGE                     23:23
+#define APBDMA_STATUS_0_BSY_7_WOFFSET                   0x0
+#define APBDMA_STATUS_0_BSY_7_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_7_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_BSY_7_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_7_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_7_NOT_BUSY                  _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_BSY_7_BUSY                      _MK_ENUM_CONST(1)
+
+// DMA channel6  status 
+#define APBDMA_STATUS_0_BSY_6_SHIFT                     _MK_SHIFT_CONST(22)
+#define APBDMA_STATUS_0_BSY_6_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_BSY_6_SHIFT)
+#define APBDMA_STATUS_0_BSY_6_RANGE                     22:22
+#define APBDMA_STATUS_0_BSY_6_WOFFSET                   0x0
+#define APBDMA_STATUS_0_BSY_6_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_6_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_BSY_6_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_6_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_6_NOT_BUSY                  _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_BSY_6_BUSY                      _MK_ENUM_CONST(1)
+
+// DMA channel5  status 
+#define APBDMA_STATUS_0_BSY_5_SHIFT                     _MK_SHIFT_CONST(21)
+#define APBDMA_STATUS_0_BSY_5_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_BSY_5_SHIFT)
+#define APBDMA_STATUS_0_BSY_5_RANGE                     21:21
+#define APBDMA_STATUS_0_BSY_5_WOFFSET                   0x0
+#define APBDMA_STATUS_0_BSY_5_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_5_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_BSY_5_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_5_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_5_NOT_BUSY                  _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_BSY_5_BUSY                      _MK_ENUM_CONST(1)
+
+// DMA channel4  status 
+#define APBDMA_STATUS_0_BSY_4_SHIFT                     _MK_SHIFT_CONST(20)
+#define APBDMA_STATUS_0_BSY_4_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_BSY_4_SHIFT)
+#define APBDMA_STATUS_0_BSY_4_RANGE                     20:20
+#define APBDMA_STATUS_0_BSY_4_WOFFSET                   0x0
+#define APBDMA_STATUS_0_BSY_4_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_4_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_BSY_4_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_4_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_4_NOT_BUSY                  _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_BSY_4_BUSY                      _MK_ENUM_CONST(1)
+
+// DMA channel3  status 
+#define APBDMA_STATUS_0_BSY_3_SHIFT                     _MK_SHIFT_CONST(19)
+#define APBDMA_STATUS_0_BSY_3_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_BSY_3_SHIFT)
+#define APBDMA_STATUS_0_BSY_3_RANGE                     19:19
+#define APBDMA_STATUS_0_BSY_3_WOFFSET                   0x0
+#define APBDMA_STATUS_0_BSY_3_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_3_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_BSY_3_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_3_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_3_NOT_BUSY                  _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_BSY_3_BUSY                      _MK_ENUM_CONST(1)
+
+// DMA channel2  status 
+#define APBDMA_STATUS_0_BSY_2_SHIFT                     _MK_SHIFT_CONST(18)
+#define APBDMA_STATUS_0_BSY_2_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_BSY_2_SHIFT)
+#define APBDMA_STATUS_0_BSY_2_RANGE                     18:18
+#define APBDMA_STATUS_0_BSY_2_WOFFSET                   0x0
+#define APBDMA_STATUS_0_BSY_2_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_2_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_BSY_2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_2_NOT_BUSY                  _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_BSY_2_BUSY                      _MK_ENUM_CONST(1)
+
+// DMA channel1  status 
+#define APBDMA_STATUS_0_BSY_1_SHIFT                     _MK_SHIFT_CONST(17)
+#define APBDMA_STATUS_0_BSY_1_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_BSY_1_SHIFT)
+#define APBDMA_STATUS_0_BSY_1_RANGE                     17:17
+#define APBDMA_STATUS_0_BSY_1_WOFFSET                   0x0
+#define APBDMA_STATUS_0_BSY_1_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_1_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_BSY_1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_1_NOT_BUSY                  _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_BSY_1_BUSY                      _MK_ENUM_CONST(1)
+
+// DMA channel0  status 
+#define APBDMA_STATUS_0_BSY_0_SHIFT                     _MK_SHIFT_CONST(16)
+#define APBDMA_STATUS_0_BSY_0_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_BSY_0_SHIFT)
+#define APBDMA_STATUS_0_BSY_0_RANGE                     16:16
+#define APBDMA_STATUS_0_BSY_0_WOFFSET                   0x0
+#define APBDMA_STATUS_0_BSY_0_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_0_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_BSY_0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_0_NOT_BUSY                  _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_BSY_0_BUSY                      _MK_ENUM_CONST(1)
+
+// DMA channel15 Interrupt Status
+#define APBDMA_STATUS_0_ISE_EOC_15_SHIFT                        _MK_SHIFT_CONST(15)
+#define APBDMA_STATUS_0_ISE_EOC_15_FIELD                        (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_ISE_EOC_15_SHIFT)
+#define APBDMA_STATUS_0_ISE_EOC_15_RANGE                        15:15
+#define APBDMA_STATUS_0_ISE_EOC_15_WOFFSET                      0x0
+#define APBDMA_STATUS_0_ISE_EOC_15_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_15_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_ISE_EOC_15_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_15_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_15_NOT_ACTIVE                   _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_ISE_EOC_15_ACTIVE                       _MK_ENUM_CONST(1)
+
+// DMA channel14 Interrupt Status 
+#define APBDMA_STATUS_0_ISE_EOC_14_SHIFT                        _MK_SHIFT_CONST(14)
+#define APBDMA_STATUS_0_ISE_EOC_14_FIELD                        (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_ISE_EOC_14_SHIFT)
+#define APBDMA_STATUS_0_ISE_EOC_14_RANGE                        14:14
+#define APBDMA_STATUS_0_ISE_EOC_14_WOFFSET                      0x0
+#define APBDMA_STATUS_0_ISE_EOC_14_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_14_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_ISE_EOC_14_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_14_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_14_NOT_ACTIVE                   _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_ISE_EOC_14_ACTIVE                       _MK_ENUM_CONST(1)
+
+// DMA channel13 Interrupt Status 
+#define APBDMA_STATUS_0_ISE_EOC_13_SHIFT                        _MK_SHIFT_CONST(13)
+#define APBDMA_STATUS_0_ISE_EOC_13_FIELD                        (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_ISE_EOC_13_SHIFT)
+#define APBDMA_STATUS_0_ISE_EOC_13_RANGE                        13:13
+#define APBDMA_STATUS_0_ISE_EOC_13_WOFFSET                      0x0
+#define APBDMA_STATUS_0_ISE_EOC_13_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_13_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_ISE_EOC_13_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_13_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_13_NOT_ACTIVE                   _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_ISE_EOC_13_ACTIVE                       _MK_ENUM_CONST(1)
+
+// DMA channel12 Interrupt Status 
+#define APBDMA_STATUS_0_ISE_EOC_12_SHIFT                        _MK_SHIFT_CONST(12)
+#define APBDMA_STATUS_0_ISE_EOC_12_FIELD                        (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_ISE_EOC_12_SHIFT)
+#define APBDMA_STATUS_0_ISE_EOC_12_RANGE                        12:12
+#define APBDMA_STATUS_0_ISE_EOC_12_WOFFSET                      0x0
+#define APBDMA_STATUS_0_ISE_EOC_12_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_12_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_ISE_EOC_12_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_12_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_12_NOT_ACTIVE                   _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_ISE_EOC_12_ACTIVE                       _MK_ENUM_CONST(1)
+
+// DMA channel11 Interrupt Status 
+#define APBDMA_STATUS_0_ISE_EOC_11_SHIFT                        _MK_SHIFT_CONST(11)
+#define APBDMA_STATUS_0_ISE_EOC_11_FIELD                        (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_ISE_EOC_11_SHIFT)
+#define APBDMA_STATUS_0_ISE_EOC_11_RANGE                        11:11
+#define APBDMA_STATUS_0_ISE_EOC_11_WOFFSET                      0x0
+#define APBDMA_STATUS_0_ISE_EOC_11_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_11_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_ISE_EOC_11_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_11_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_11_NOT_ACTIVE                   _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_ISE_EOC_11_ACTIVE                       _MK_ENUM_CONST(1)
+
+// DMA channel10 Interrupt Status
+#define APBDMA_STATUS_0_ISE_EOC_10_SHIFT                        _MK_SHIFT_CONST(10)
+#define APBDMA_STATUS_0_ISE_EOC_10_FIELD                        (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_ISE_EOC_10_SHIFT)
+#define APBDMA_STATUS_0_ISE_EOC_10_RANGE                        10:10
+#define APBDMA_STATUS_0_ISE_EOC_10_WOFFSET                      0x0
+#define APBDMA_STATUS_0_ISE_EOC_10_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_10_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_ISE_EOC_10_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_10_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_10_NOT_ACTIVE                   _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_ISE_EOC_10_ACTIVE                       _MK_ENUM_CONST(1)
+
+// DMA channel9  Interrupt Status 
+#define APBDMA_STATUS_0_ISE_EOC_9_SHIFT                 _MK_SHIFT_CONST(9)
+#define APBDMA_STATUS_0_ISE_EOC_9_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_ISE_EOC_9_SHIFT)
+#define APBDMA_STATUS_0_ISE_EOC_9_RANGE                 9:9
+#define APBDMA_STATUS_0_ISE_EOC_9_WOFFSET                       0x0
+#define APBDMA_STATUS_0_ISE_EOC_9_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_9_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_ISE_EOC_9_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_9_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_9_NOT_ACTIVE                    _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_ISE_EOC_9_ACTIVE                        _MK_ENUM_CONST(1)
+
+// DMA channel8  Interrupt Status 
+#define APBDMA_STATUS_0_ISE_EOC_8_SHIFT                 _MK_SHIFT_CONST(8)
+#define APBDMA_STATUS_0_ISE_EOC_8_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_ISE_EOC_8_SHIFT)
+#define APBDMA_STATUS_0_ISE_EOC_8_RANGE                 8:8
+#define APBDMA_STATUS_0_ISE_EOC_8_WOFFSET                       0x0
+#define APBDMA_STATUS_0_ISE_EOC_8_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_8_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_ISE_EOC_8_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_8_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_8_NOT_ACTIVE                    _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_ISE_EOC_8_ACTIVE                        _MK_ENUM_CONST(1)
+
+// DMA channel7  Interrupt Status 
+#define APBDMA_STATUS_0_ISE_EOC_7_SHIFT                 _MK_SHIFT_CONST(7)
+#define APBDMA_STATUS_0_ISE_EOC_7_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_ISE_EOC_7_SHIFT)
+#define APBDMA_STATUS_0_ISE_EOC_7_RANGE                 7:7
+#define APBDMA_STATUS_0_ISE_EOC_7_WOFFSET                       0x0
+#define APBDMA_STATUS_0_ISE_EOC_7_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_7_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_ISE_EOC_7_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_7_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_7_NOT_ACTIVE                    _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_ISE_EOC_7_ACTIVE                        _MK_ENUM_CONST(1)
+
+// DMA channel6  Interrupt Status 
+#define APBDMA_STATUS_0_ISE_EOC_6_SHIFT                 _MK_SHIFT_CONST(6)
+#define APBDMA_STATUS_0_ISE_EOC_6_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_ISE_EOC_6_SHIFT)
+#define APBDMA_STATUS_0_ISE_EOC_6_RANGE                 6:6
+#define APBDMA_STATUS_0_ISE_EOC_6_WOFFSET                       0x0
+#define APBDMA_STATUS_0_ISE_EOC_6_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_6_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_ISE_EOC_6_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_6_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_6_NOT_ACTIVE                    _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_ISE_EOC_6_ACTIVE                        _MK_ENUM_CONST(1)
+
+// DMA channel5  Interrupt Status 
+#define APBDMA_STATUS_0_ISE_EOC_5_SHIFT                 _MK_SHIFT_CONST(5)
+#define APBDMA_STATUS_0_ISE_EOC_5_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_ISE_EOC_5_SHIFT)
+#define APBDMA_STATUS_0_ISE_EOC_5_RANGE                 5:5
+#define APBDMA_STATUS_0_ISE_EOC_5_WOFFSET                       0x0
+#define APBDMA_STATUS_0_ISE_EOC_5_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_5_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_ISE_EOC_5_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_5_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_5_NOT_ACTIVE                    _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_ISE_EOC_5_ACTIVE                        _MK_ENUM_CONST(1)
+
+// DMA channel4  Interrupt Status 
+#define APBDMA_STATUS_0_ISE_EOC_4_SHIFT                 _MK_SHIFT_CONST(4)
+#define APBDMA_STATUS_0_ISE_EOC_4_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_ISE_EOC_4_SHIFT)
+#define APBDMA_STATUS_0_ISE_EOC_4_RANGE                 4:4
+#define APBDMA_STATUS_0_ISE_EOC_4_WOFFSET                       0x0
+#define APBDMA_STATUS_0_ISE_EOC_4_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_4_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_ISE_EOC_4_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_4_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_4_NOT_ACTIVE                    _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_ISE_EOC_4_ACTIVE                        _MK_ENUM_CONST(1)
+
+// DMA channel3  Interrupt Status 
+#define APBDMA_STATUS_0_ISE_EOC_3_SHIFT                 _MK_SHIFT_CONST(3)
+#define APBDMA_STATUS_0_ISE_EOC_3_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_ISE_EOC_3_SHIFT)
+#define APBDMA_STATUS_0_ISE_EOC_3_RANGE                 3:3
+#define APBDMA_STATUS_0_ISE_EOC_3_WOFFSET                       0x0
+#define APBDMA_STATUS_0_ISE_EOC_3_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_3_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_ISE_EOC_3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_3_NOT_ACTIVE                    _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_ISE_EOC_3_ACTIVE                        _MK_ENUM_CONST(1)
+
+// DMA channel2  Interrupt Status 
+#define APBDMA_STATUS_0_ISE_EOC_2_SHIFT                 _MK_SHIFT_CONST(2)
+#define APBDMA_STATUS_0_ISE_EOC_2_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_ISE_EOC_2_SHIFT)
+#define APBDMA_STATUS_0_ISE_EOC_2_RANGE                 2:2
+#define APBDMA_STATUS_0_ISE_EOC_2_WOFFSET                       0x0
+#define APBDMA_STATUS_0_ISE_EOC_2_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_2_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_ISE_EOC_2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_2_NOT_ACTIVE                    _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_ISE_EOC_2_ACTIVE                        _MK_ENUM_CONST(1)
+
+// DMA channel1  Interrupt Status 
+#define APBDMA_STATUS_0_ISE_EOC_1_SHIFT                 _MK_SHIFT_CONST(1)
+#define APBDMA_STATUS_0_ISE_EOC_1_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_ISE_EOC_1_SHIFT)
+#define APBDMA_STATUS_0_ISE_EOC_1_RANGE                 1:1
+#define APBDMA_STATUS_0_ISE_EOC_1_WOFFSET                       0x0
+#define APBDMA_STATUS_0_ISE_EOC_1_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_1_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_ISE_EOC_1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_1_NOT_ACTIVE                    _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_ISE_EOC_1_ACTIVE                        _MK_ENUM_CONST(1)
+
+// DMA channel0  Interrupt Status 
+#define APBDMA_STATUS_0_ISE_EOC_0_SHIFT                 _MK_SHIFT_CONST(0)
+#define APBDMA_STATUS_0_ISE_EOC_0_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_ISE_EOC_0_SHIFT)
+#define APBDMA_STATUS_0_ISE_EOC_0_RANGE                 0:0
+#define APBDMA_STATUS_0_ISE_EOC_0_WOFFSET                       0x0
+#define APBDMA_STATUS_0_ISE_EOC_0_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_0_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_ISE_EOC_0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_0_NOT_ACTIVE                    _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_ISE_EOC_0_ACTIVE                        _MK_ENUM_CONST(1)
+
+
+// Register APBDMA_REQUESTORS_TX_0  
+#define APBDMA_REQUESTORS_TX_0                  _MK_ADDR_CONST(0x8)
+#define APBDMA_REQUESTORS_TX_0_WORD_COUNT                       0x1
+#define APBDMA_REQUESTORS_TX_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_RESET_MASK                       _MK_MASK_CONST(0x3ffff)
+#define APBDMA_REQUESTORS_TX_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_READ_MASK                        _MK_MASK_CONST(0x3ffff)
+#define APBDMA_REQUESTORS_TX_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
+// SLINK 2B-3
+#define APBDMA_REQUESTORS_TX_0_SL2B3_SHIFT                      _MK_SHIFT_CONST(17)
+#define APBDMA_REQUESTORS_TX_0_SL2B3_FIELD                      (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_TX_0_SL2B3_SHIFT)
+#define APBDMA_REQUESTORS_TX_0_SL2B3_RANGE                      17:17
+#define APBDMA_REQUESTORS_TX_0_SL2B3_WOFFSET                    0x0
+#define APBDMA_REQUESTORS_TX_0_SL2B3_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_SL2B3_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_TX_0_SL2B3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_SL2B3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_SL2B3_NOT_ACTIVE                 _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_TX_0_SL2B3_ACTIVE                     _MK_ENUM_CONST(1)
+
+// SLINK 2B-2
+#define APBDMA_REQUESTORS_TX_0_SL2B2_SHIFT                      _MK_SHIFT_CONST(16)
+#define APBDMA_REQUESTORS_TX_0_SL2B2_FIELD                      (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_TX_0_SL2B2_SHIFT)
+#define APBDMA_REQUESTORS_TX_0_SL2B2_RANGE                      16:16
+#define APBDMA_REQUESTORS_TX_0_SL2B2_WOFFSET                    0x0
+#define APBDMA_REQUESTORS_TX_0_SL2B2_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_SL2B2_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_TX_0_SL2B2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_SL2B2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_SL2B2_NOT_ACTIVE                 _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_TX_0_SL2B2_ACTIVE                     _MK_ENUM_CONST(1)
+
+// SLINK 2B-1
+#define APBDMA_REQUESTORS_TX_0_SL2B1_SHIFT                      _MK_SHIFT_CONST(15)
+#define APBDMA_REQUESTORS_TX_0_SL2B1_FIELD                      (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_TX_0_SL2B1_SHIFT)
+#define APBDMA_REQUESTORS_TX_0_SL2B1_RANGE                      15:15
+#define APBDMA_REQUESTORS_TX_0_SL2B1_WOFFSET                    0x0
+#define APBDMA_REQUESTORS_TX_0_SL2B1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_SL2B1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_TX_0_SL2B1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_SL2B1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_SL2B1_NOT_ACTIVE                 _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_TX_0_SL2B1_ACTIVE                     _MK_ENUM_CONST(1)
+
+// SLINK 4B
+#define APBDMA_REQUESTORS_TX_0_SL4B_SHIFT                       _MK_SHIFT_CONST(14)
+#define APBDMA_REQUESTORS_TX_0_SL4B_FIELD                       (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_TX_0_SL4B_SHIFT)
+#define APBDMA_REQUESTORS_TX_0_SL4B_RANGE                       14:14
+#define APBDMA_REQUESTORS_TX_0_SL4B_WOFFSET                     0x0
+#define APBDMA_REQUESTORS_TX_0_SL4B_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_SL4B_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_TX_0_SL4B_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_SL4B_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_SL4B_NOT_ACTIVE                  _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_TX_0_SL4B_ACTIVE                      _MK_ENUM_CONST(1)
+
+// ACModem
+#define APBDMA_REQUESTORS_TX_0_ACModem_SHIFT                    _MK_SHIFT_CONST(13)
+#define APBDMA_REQUESTORS_TX_0_ACModem_FIELD                    (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_TX_0_ACModem_SHIFT)
+#define APBDMA_REQUESTORS_TX_0_ACModem_RANGE                    13:13
+#define APBDMA_REQUESTORS_TX_0_ACModem_WOFFSET                  0x0
+#define APBDMA_REQUESTORS_TX_0_ACModem_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_ACModem_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_TX_0_ACModem_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_ACModem_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_ACModem_NOT_ACTIVE                       _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_TX_0_ACModem_ACTIVE                   _MK_ENUM_CONST(1)
+
+// AC97
+#define APBDMA_REQUESTORS_TX_0_AC97_SHIFT                       _MK_SHIFT_CONST(12)
+#define APBDMA_REQUESTORS_TX_0_AC97_FIELD                       (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_TX_0_AC97_SHIFT)
+#define APBDMA_REQUESTORS_TX_0_AC97_RANGE                       12:12
+#define APBDMA_REQUESTORS_TX_0_AC97_WOFFSET                     0x0
+#define APBDMA_REQUESTORS_TX_0_AC97_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_AC97_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_TX_0_AC97_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_AC97_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_AC97_NOT_ACTIVE                  _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_TX_0_AC97_ACTIVE                      _MK_ENUM_CONST(1)
+
+// SPI Controller
+#define APBDMA_REQUESTORS_TX_0_SPI_SHIFT                        _MK_SHIFT_CONST(11)
+#define APBDMA_REQUESTORS_TX_0_SPI_FIELD                        (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_TX_0_SPI_SHIFT)
+#define APBDMA_REQUESTORS_TX_0_SPI_RANGE                        11:11
+#define APBDMA_REQUESTORS_TX_0_SPI_WOFFSET                      0x0
+#define APBDMA_REQUESTORS_TX_0_SPI_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_SPI_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_TX_0_SPI_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_SPI_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_SPI_NOT_ACTIVE                   _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_TX_0_SPI_ACTIVE                       _MK_ENUM_CONST(1)
+
+// UART C
+#define APBDMA_REQUESTORS_TX_0_UART_C_SHIFT                     _MK_SHIFT_CONST(10)
+#define APBDMA_REQUESTORS_TX_0_UART_C_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_TX_0_UART_C_SHIFT)
+#define APBDMA_REQUESTORS_TX_0_UART_C_RANGE                     10:10
+#define APBDMA_REQUESTORS_TX_0_UART_C_WOFFSET                   0x0
+#define APBDMA_REQUESTORS_TX_0_UART_C_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_UART_C_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_TX_0_UART_C_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_UART_C_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_UART_C_NOT_ACTIVE                        _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_TX_0_UART_C_ACTIVE                    _MK_ENUM_CONST(1)
+
+// UART B (VFIR)
+#define APBDMA_REQUESTORS_TX_0_UART_B_SHIFT                     _MK_SHIFT_CONST(9)
+#define APBDMA_REQUESTORS_TX_0_UART_B_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_TX_0_UART_B_SHIFT)
+#define APBDMA_REQUESTORS_TX_0_UART_B_RANGE                     9:9
+#define APBDMA_REQUESTORS_TX_0_UART_B_WOFFSET                   0x0
+#define APBDMA_REQUESTORS_TX_0_UART_B_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_UART_B_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_TX_0_UART_B_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_UART_B_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_UART_B_NOT_ACTIVE                        _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_TX_0_UART_B_ACTIVE                    _MK_ENUM_CONST(1)
+
+// UART A
+#define APBDMA_REQUESTORS_TX_0_UART_A_SHIFT                     _MK_SHIFT_CONST(8)
+#define APBDMA_REQUESTORS_TX_0_UART_A_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_TX_0_UART_A_SHIFT)
+#define APBDMA_REQUESTORS_TX_0_UART_A_RANGE                     8:8
+#define APBDMA_REQUESTORS_TX_0_UART_A_WOFFSET                   0x0
+#define APBDMA_REQUESTORS_TX_0_UART_A_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_UART_A_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_TX_0_UART_A_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_UART_A_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_UART_A_NOT_ACTIVE                        _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_TX_0_UART_A_ACTIVE                    _MK_ENUM_CONST(1)
+
+// I2S2 Tx Output FIFO1 (Play) (Peripheral initiated DMA request) 1 = Activate DMA transfer 0 = NOP
+#define APBDMA_REQUESTORS_TX_0_I2S2_1_SHIFT                     _MK_SHIFT_CONST(7)
+#define APBDMA_REQUESTORS_TX_0_I2S2_1_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_TX_0_I2S2_1_SHIFT)
+#define APBDMA_REQUESTORS_TX_0_I2S2_1_RANGE                     7:7
+#define APBDMA_REQUESTORS_TX_0_I2S2_1_WOFFSET                   0x0
+#define APBDMA_REQUESTORS_TX_0_I2S2_1_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_I2S2_1_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_TX_0_I2S2_1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_I2S2_1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_I2S2_1_NOT_ACTIVE                        _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_TX_0_I2S2_1_ACTIVE                    _MK_ENUM_CONST(1)
+
+// I2S2 Tx Output FIFO2 (Play) (Peripheral initiated DMA request) 1 = Activate DMA transfer 0 = NOP
+#define APBDMA_REQUESTORS_TX_0_I2S2_2_SHIFT                     _MK_SHIFT_CONST(6)
+#define APBDMA_REQUESTORS_TX_0_I2S2_2_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_TX_0_I2S2_2_SHIFT)
+#define APBDMA_REQUESTORS_TX_0_I2S2_2_RANGE                     6:6
+#define APBDMA_REQUESTORS_TX_0_I2S2_2_WOFFSET                   0x0
+#define APBDMA_REQUESTORS_TX_0_I2S2_2_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_I2S2_2_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_TX_0_I2S2_2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_I2S2_2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_I2S2_2_NOT_ACTIVE                        _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_TX_0_I2S2_2_ACTIVE                    _MK_ENUM_CONST(1)
+
+// MIPI Rx Input FIFO.
+#define APBDMA_REQUESTORS_TX_0_MIPI_SHIFT                       _MK_SHIFT_CONST(5)
+#define APBDMA_REQUESTORS_TX_0_MIPI_FIELD                       (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_TX_0_MIPI_SHIFT)
+#define APBDMA_REQUESTORS_TX_0_MIPI_RANGE                       5:5
+#define APBDMA_REQUESTORS_TX_0_MIPI_WOFFSET                     0x0
+#define APBDMA_REQUESTORS_TX_0_MIPI_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_MIPI_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_TX_0_MIPI_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_MIPI_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// EBU USR Output (Peripheral initiated DMA request) 1 = Activate DMA transfer 0 = NOP
+#define APBDMA_REQUESTORS_TX_0_UI_I_SHIFT                       _MK_SHIFT_CONST(4)
+#define APBDMA_REQUESTORS_TX_0_UI_I_FIELD                       (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_TX_0_UI_I_SHIFT)
+#define APBDMA_REQUESTORS_TX_0_UI_I_RANGE                       4:4
+#define APBDMA_REQUESTORS_TX_0_UI_I_WOFFSET                     0x0
+#define APBDMA_REQUESTORS_TX_0_UI_I_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_UI_I_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_TX_0_UI_I_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_UI_I_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_UI_I_NOT_ACTIVE                  _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_TX_0_UI_I_ACTIVE                      _MK_ENUM_CONST(1)
+
+// SPDIF Output FIFO (Rx) (Peripheral initiated DMA request) 1 = Activate DMA transfer 0 = NOP
+#define APBDMA_REQUESTORS_TX_0_SPD_I_SHIFT                      _MK_SHIFT_CONST(3)
+#define APBDMA_REQUESTORS_TX_0_SPD_I_FIELD                      (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_TX_0_SPD_I_SHIFT)
+#define APBDMA_REQUESTORS_TX_0_SPD_I_RANGE                      3:3
+#define APBDMA_REQUESTORS_TX_0_SPD_I_WOFFSET                    0x0
+#define APBDMA_REQUESTORS_TX_0_SPD_I_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_SPD_I_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_TX_0_SPD_I_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_SPD_I_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_SPD_I_NOT_ACTIVE                 _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_TX_0_SPD_I_ACTIVE                     _MK_ENUM_CONST(1)
+
+// I2S Tx Output FIFO1 (Record) (Peripheral initiated DMA request) 1 = Activate DMA transfer0 = NOP
+#define APBDMA_REQUESTORS_TX_0_I2S_1_SHIFT                      _MK_SHIFT_CONST(2)
+#define APBDMA_REQUESTORS_TX_0_I2S_1_FIELD                      (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_TX_0_I2S_1_SHIFT)
+#define APBDMA_REQUESTORS_TX_0_I2S_1_RANGE                      2:2
+#define APBDMA_REQUESTORS_TX_0_I2S_1_WOFFSET                    0x0
+#define APBDMA_REQUESTORS_TX_0_I2S_1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_I2S_1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_TX_0_I2S_1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_I2S_1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_I2S_1_NOT_ACTIVE                 _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_TX_0_I2S_1_ACTIVE                     _MK_ENUM_CONST(1)
+
+// I2S Tx Output FIFO2 (Play) (Peripheral initiated DMA request) 1 = Activate DMA transfer0 = NOP
+#define APBDMA_REQUESTORS_TX_0_I2S_2_SHIFT                      _MK_SHIFT_CONST(1)
+#define APBDMA_REQUESTORS_TX_0_I2S_2_FIELD                      (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_TX_0_I2S_2_SHIFT)
+#define APBDMA_REQUESTORS_TX_0_I2S_2_RANGE                      1:1
+#define APBDMA_REQUESTORS_TX_0_I2S_2_WOFFSET                    0x0
+#define APBDMA_REQUESTORS_TX_0_I2S_2_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_I2S_2_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_TX_0_I2S_2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_I2S_2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_I2S_2_NOT_ACTIVE                 _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_TX_0_I2S_2_ACTIVE                     _MK_ENUM_CONST(1)
+
+// Enables counter request.
+#define APBDMA_REQUESTORS_TX_0_CNTR_REQ_SHIFT                   _MK_SHIFT_CONST(0)
+#define APBDMA_REQUESTORS_TX_0_CNTR_REQ_FIELD                   (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_TX_0_CNTR_REQ_SHIFT)
+#define APBDMA_REQUESTORS_TX_0_CNTR_REQ_RANGE                   0:0
+#define APBDMA_REQUESTORS_TX_0_CNTR_REQ_WOFFSET                 0x0
+#define APBDMA_REQUESTORS_TX_0_CNTR_REQ_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_CNTR_REQ_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_TX_0_CNTR_REQ_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_CNTR_REQ_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_CNTR_REQ_NOT_ACTIVE                      _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_TX_0_CNTR_REQ_ACTIVE                  _MK_ENUM_CONST(1)
+
+
+// Register APBDMA_REQUESTORS_RX_0  
+#define APBDMA_REQUESTORS_RX_0                  _MK_ADDR_CONST(0xc)
+#define APBDMA_REQUESTORS_RX_0_WORD_COUNT                       0x1
+#define APBDMA_REQUESTORS_RX_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_RESET_MASK                       _MK_MASK_CONST(0x3ffff)
+#define APBDMA_REQUESTORS_RX_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_READ_MASK                        _MK_MASK_CONST(0x3ffff)
+#define APBDMA_REQUESTORS_RX_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
+// SLINK 2B-3
+#define APBDMA_REQUESTORS_RX_0_SL2B3_SHIFT                      _MK_SHIFT_CONST(17)
+#define APBDMA_REQUESTORS_RX_0_SL2B3_FIELD                      (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_RX_0_SL2B3_SHIFT)
+#define APBDMA_REQUESTORS_RX_0_SL2B3_RANGE                      17:17
+#define APBDMA_REQUESTORS_RX_0_SL2B3_WOFFSET                    0x0
+#define APBDMA_REQUESTORS_RX_0_SL2B3_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_SL2B3_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_RX_0_SL2B3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_SL2B3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_SL2B3_NOT_ACTIVE                 _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_RX_0_SL2B3_ACTIVE                     _MK_ENUM_CONST(1)
+
+// SLINK 2B-2
+#define APBDMA_REQUESTORS_RX_0_SL2B2_SHIFT                      _MK_SHIFT_CONST(16)
+#define APBDMA_REQUESTORS_RX_0_SL2B2_FIELD                      (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_RX_0_SL2B2_SHIFT)
+#define APBDMA_REQUESTORS_RX_0_SL2B2_RANGE                      16:16
+#define APBDMA_REQUESTORS_RX_0_SL2B2_WOFFSET                    0x0
+#define APBDMA_REQUESTORS_RX_0_SL2B2_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_SL2B2_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_RX_0_SL2B2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_SL2B2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_SL2B2_NOT_ACTIVE                 _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_RX_0_SL2B2_ACTIVE                     _MK_ENUM_CONST(1)
+
+// SLINK 2B-1
+#define APBDMA_REQUESTORS_RX_0_SL2B1_SHIFT                      _MK_SHIFT_CONST(15)
+#define APBDMA_REQUESTORS_RX_0_SL2B1_FIELD                      (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_RX_0_SL2B1_SHIFT)
+#define APBDMA_REQUESTORS_RX_0_SL2B1_RANGE                      15:15
+#define APBDMA_REQUESTORS_RX_0_SL2B1_WOFFSET                    0x0
+#define APBDMA_REQUESTORS_RX_0_SL2B1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_SL2B1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_RX_0_SL2B1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_SL2B1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_SL2B1_NOT_ACTIVE                 _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_RX_0_SL2B1_ACTIVE                     _MK_ENUM_CONST(1)
+
+// SLINK 4B
+#define APBDMA_REQUESTORS_RX_0_SL4B_SHIFT                       _MK_SHIFT_CONST(14)
+#define APBDMA_REQUESTORS_RX_0_SL4B_FIELD                       (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_RX_0_SL4B_SHIFT)
+#define APBDMA_REQUESTORS_RX_0_SL4B_RANGE                       14:14
+#define APBDMA_REQUESTORS_RX_0_SL4B_WOFFSET                     0x0
+#define APBDMA_REQUESTORS_RX_0_SL4B_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_SL4B_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_RX_0_SL4B_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_SL4B_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_SL4B_NOT_ACTIVE                  _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_RX_0_SL4B_ACTIVE                      _MK_ENUM_CONST(1)
+
+// ACModem
+#define APBDMA_REQUESTORS_RX_0_ACModem_SHIFT                    _MK_SHIFT_CONST(13)
+#define APBDMA_REQUESTORS_RX_0_ACModem_FIELD                    (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_RX_0_ACModem_SHIFT)
+#define APBDMA_REQUESTORS_RX_0_ACModem_RANGE                    13:13
+#define APBDMA_REQUESTORS_RX_0_ACModem_WOFFSET                  0x0
+#define APBDMA_REQUESTORS_RX_0_ACModem_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_ACModem_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_RX_0_ACModem_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_ACModem_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_ACModem_NOT_ACTIVE                       _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_RX_0_ACModem_ACTIVE                   _MK_ENUM_CONST(1)
+
+// AC97
+#define APBDMA_REQUESTORS_RX_0_AC97_SHIFT                       _MK_SHIFT_CONST(12)
+#define APBDMA_REQUESTORS_RX_0_AC97_FIELD                       (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_RX_0_AC97_SHIFT)
+#define APBDMA_REQUESTORS_RX_0_AC97_RANGE                       12:12
+#define APBDMA_REQUESTORS_RX_0_AC97_WOFFSET                     0x0
+#define APBDMA_REQUESTORS_RX_0_AC97_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_AC97_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_RX_0_AC97_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_AC97_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_AC97_NOT_ACTIVE                  _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_RX_0_AC97_ACTIVE                      _MK_ENUM_CONST(1)
+
+// SPI Controller
+#define APBDMA_REQUESTORS_RX_0_SPI_SHIFT                        _MK_SHIFT_CONST(11)
+#define APBDMA_REQUESTORS_RX_0_SPI_FIELD                        (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_RX_0_SPI_SHIFT)
+#define APBDMA_REQUESTORS_RX_0_SPI_RANGE                        11:11
+#define APBDMA_REQUESTORS_RX_0_SPI_WOFFSET                      0x0
+#define APBDMA_REQUESTORS_RX_0_SPI_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_SPI_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_RX_0_SPI_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_SPI_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_SPI_NOT_ACTIVE                   _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_RX_0_SPI_ACTIVE                       _MK_ENUM_CONST(1)
+
+// UART C
+#define APBDMA_REQUESTORS_RX_0_UART_C_SHIFT                     _MK_SHIFT_CONST(10)
+#define APBDMA_REQUESTORS_RX_0_UART_C_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_RX_0_UART_C_SHIFT)
+#define APBDMA_REQUESTORS_RX_0_UART_C_RANGE                     10:10
+#define APBDMA_REQUESTORS_RX_0_UART_C_WOFFSET                   0x0
+#define APBDMA_REQUESTORS_RX_0_UART_C_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_UART_C_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_RX_0_UART_C_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_UART_C_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_UART_C_NOT_ACTIVE                        _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_RX_0_UART_C_ACTIVE                    _MK_ENUM_CONST(1)
+
+// UART B (VFIR)
+#define APBDMA_REQUESTORS_RX_0_UART_B_SHIFT                     _MK_SHIFT_CONST(9)
+#define APBDMA_REQUESTORS_RX_0_UART_B_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_RX_0_UART_B_SHIFT)
+#define APBDMA_REQUESTORS_RX_0_UART_B_RANGE                     9:9
+#define APBDMA_REQUESTORS_RX_0_UART_B_WOFFSET                   0x0
+#define APBDMA_REQUESTORS_RX_0_UART_B_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_UART_B_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_RX_0_UART_B_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_UART_B_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_UART_B_NOT_ACTIVE                        _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_RX_0_UART_B_ACTIVE                    _MK_ENUM_CONST(1)
+
+// UART A
+#define APBDMA_REQUESTORS_RX_0_UART_A_SHIFT                     _MK_SHIFT_CONST(8)
+#define APBDMA_REQUESTORS_RX_0_UART_A_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_RX_0_UART_A_SHIFT)
+#define APBDMA_REQUESTORS_RX_0_UART_A_RANGE                     8:8
+#define APBDMA_REQUESTORS_RX_0_UART_A_WOFFSET                   0x0
+#define APBDMA_REQUESTORS_RX_0_UART_A_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_UART_A_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_RX_0_UART_A_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_UART_A_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_UART_A_NOT_ACTIVE                        _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_RX_0_UART_A_ACTIVE                    _MK_ENUM_CONST(1)
+
+// I2S2 Rx Input FIFO2 (Peripheral initiated DMA request) 1 = Activate DMA transfer 0 = NOP
+#define APBDMA_REQUESTORS_RX_0_I2S2_2_SHIFT                     _MK_SHIFT_CONST(7)
+#define APBDMA_REQUESTORS_RX_0_I2S2_2_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_RX_0_I2S2_2_SHIFT)
+#define APBDMA_REQUESTORS_RX_0_I2S2_2_RANGE                     7:7
+#define APBDMA_REQUESTORS_RX_0_I2S2_2_WOFFSET                   0x0
+#define APBDMA_REQUESTORS_RX_0_I2S2_2_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_I2S2_2_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_RX_0_I2S2_2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_I2S2_2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_I2S2_2_NOT_ACTIVE                        _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_RX_0_I2S2_2_ACTIVE                    _MK_ENUM_CONST(1)
+
+// I2S2 Rx Input FIFO1 (Peripheral initiated DMA request) 1 = Activate DMA transfer 0 = NOP
+#define APBDMA_REQUESTORS_RX_0_I2S2_1_SHIFT                     _MK_SHIFT_CONST(6)
+#define APBDMA_REQUESTORS_RX_0_I2S2_1_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_RX_0_I2S2_1_SHIFT)
+#define APBDMA_REQUESTORS_RX_0_I2S2_1_RANGE                     6:6
+#define APBDMA_REQUESTORS_RX_0_I2S2_1_WOFFSET                   0x0
+#define APBDMA_REQUESTORS_RX_0_I2S2_1_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_I2S2_1_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_RX_0_I2S2_1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_I2S2_1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_I2S2_1_NOT_ACTIVE                        _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_RX_0_I2S2_1_ACTIVE                    _MK_ENUM_CONST(1)
+
+// MIPI Rx Input FIFO.
+#define APBDMA_REQUESTORS_RX_0_MIPI_SHIFT                       _MK_SHIFT_CONST(5)
+#define APBDMA_REQUESTORS_RX_0_MIPI_FIELD                       (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_RX_0_MIPI_SHIFT)
+#define APBDMA_REQUESTORS_RX_0_MIPI_RANGE                       5:5
+#define APBDMA_REQUESTORS_RX_0_MIPI_WOFFSET                     0x0
+#define APBDMA_REQUESTORS_RX_0_MIPI_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_MIPI_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_RX_0_MIPI_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_MIPI_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// EBU+SPDIF USR Input (Peripheral initiated DMA request) 1 = Activate DMA transfer 0 = NOP
+#define APBDMA_REQUESTORS_RX_0_UI_I_SHIFT                       _MK_SHIFT_CONST(4)
+#define APBDMA_REQUESTORS_RX_0_UI_I_FIELD                       (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_RX_0_UI_I_SHIFT)
+#define APBDMA_REQUESTORS_RX_0_UI_I_RANGE                       4:4
+#define APBDMA_REQUESTORS_RX_0_UI_I_WOFFSET                     0x0
+#define APBDMA_REQUESTORS_RX_0_UI_I_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_UI_I_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_RX_0_UI_I_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_UI_I_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_UI_I_NOT_ACTIVE                  _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_RX_0_UI_I_ACTIVE                      _MK_ENUM_CONST(1)
+
+// SPDIF Input FIFO (Rx) (Peripheral initiated DMA request) 1 = Activate DMA transfer 0 = NOP
+#define APBDMA_REQUESTORS_RX_0_SPD_I_SHIFT                      _MK_SHIFT_CONST(3)
+#define APBDMA_REQUESTORS_RX_0_SPD_I_FIELD                      (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_RX_0_SPD_I_SHIFT)
+#define APBDMA_REQUESTORS_RX_0_SPD_I_RANGE                      3:3
+#define APBDMA_REQUESTORS_RX_0_SPD_I_WOFFSET                    0x0
+#define APBDMA_REQUESTORS_RX_0_SPD_I_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_SPD_I_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_RX_0_SPD_I_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_SPD_I_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_SPD_I_NOT_ACTIVE                 _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_RX_0_SPD_I_ACTIVE                     _MK_ENUM_CONST(1)
+
+//  I2S Rx Input FIFO2 (Peripheral initiated DMA request) 1 = Activate DMA transfer0 = NOP
+#define APBDMA_REQUESTORS_RX_0_I2S_2_SHIFT                      _MK_SHIFT_CONST(2)
+#define APBDMA_REQUESTORS_RX_0_I2S_2_FIELD                      (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_RX_0_I2S_2_SHIFT)
+#define APBDMA_REQUESTORS_RX_0_I2S_2_RANGE                      2:2
+#define APBDMA_REQUESTORS_RX_0_I2S_2_WOFFSET                    0x0
+#define APBDMA_REQUESTORS_RX_0_I2S_2_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_I2S_2_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_RX_0_I2S_2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_I2S_2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_I2S_2_NOT_ACTIVE                 _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_RX_0_I2S_2_ACTIVE                     _MK_ENUM_CONST(1)
+
+//  I2S Rx Input FIFO1 (Peripheral initiated DMA request) 1 = Activate DMA transfer0 = NOP
+#define APBDMA_REQUESTORS_RX_0_I2S_1_SHIFT                      _MK_SHIFT_CONST(1)
+#define APBDMA_REQUESTORS_RX_0_I2S_1_FIELD                      (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_RX_0_I2S_1_SHIFT)
+#define APBDMA_REQUESTORS_RX_0_I2S_1_RANGE                      1:1
+#define APBDMA_REQUESTORS_RX_0_I2S_1_WOFFSET                    0x0
+#define APBDMA_REQUESTORS_RX_0_I2S_1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_I2S_1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_RX_0_I2S_1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_I2S_1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_I2S_1_NOT_ACTIVE                 _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_RX_0_I2S_1_ACTIVE                     _MK_ENUM_CONST(1)
+
+//  indicates Enabled counter request or not 
+#define APBDMA_REQUESTORS_RX_0_CNTR_REQ_SHIFT                   _MK_SHIFT_CONST(0)
+#define APBDMA_REQUESTORS_RX_0_CNTR_REQ_FIELD                   (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_RX_0_CNTR_REQ_SHIFT)
+#define APBDMA_REQUESTORS_RX_0_CNTR_REQ_RANGE                   0:0
+#define APBDMA_REQUESTORS_RX_0_CNTR_REQ_WOFFSET                 0x0
+#define APBDMA_REQUESTORS_RX_0_CNTR_REQ_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_CNTR_REQ_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_RX_0_CNTR_REQ_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_CNTR_REQ_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_CNTR_REQ_NOT_ACTIVE                      _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_RX_0_CNTR_REQ_ACTIVE                  _MK_ENUM_CONST(1)
+
+
+// Register APBDMA_CNTRL_REG_0  
+#define APBDMA_CNTRL_REG_0                      _MK_ADDR_CONST(0x10)
+#define APBDMA_CNTRL_REG_0_WORD_COUNT                   0x1
+#define APBDMA_CNTRL_REG_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define APBDMA_CNTRL_REG_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
+#define APBDMA_CNTRL_REG_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
+// Enable the channel15 count
+#define APBDMA_CNTRL_REG_0_CH15_CNT_EN_SHIFT                    _MK_SHIFT_CONST(31)
+#define APBDMA_CNTRL_REG_0_CH15_CNT_EN_FIELD                    (_MK_MASK_CONST(0x1) << APBDMA_CNTRL_REG_0_CH15_CNT_EN_SHIFT)
+#define APBDMA_CNTRL_REG_0_CH15_CNT_EN_RANGE                    31:31
+#define APBDMA_CNTRL_REG_0_CH15_CNT_EN_WOFFSET                  0x0
+#define APBDMA_CNTRL_REG_0_CH15_CNT_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH15_CNT_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMA_CNTRL_REG_0_CH15_CNT_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH15_CNT_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH15_CNT_EN_DISABLE                  _MK_ENUM_CONST(0)
+#define APBDMA_CNTRL_REG_0_CH15_CNT_EN_ENABLE                   _MK_ENUM_CONST(1)
+
+// Enable the channel14 count
+#define APBDMA_CNTRL_REG_0_CH14_CNT_EN_SHIFT                    _MK_SHIFT_CONST(30)
+#define APBDMA_CNTRL_REG_0_CH14_CNT_EN_FIELD                    (_MK_MASK_CONST(0x1) << APBDMA_CNTRL_REG_0_CH14_CNT_EN_SHIFT)
+#define APBDMA_CNTRL_REG_0_CH14_CNT_EN_RANGE                    30:30
+#define APBDMA_CNTRL_REG_0_CH14_CNT_EN_WOFFSET                  0x0
+#define APBDMA_CNTRL_REG_0_CH14_CNT_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH14_CNT_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMA_CNTRL_REG_0_CH14_CNT_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH14_CNT_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH14_CNT_EN_DISABLE                  _MK_ENUM_CONST(0)
+#define APBDMA_CNTRL_REG_0_CH14_CNT_EN_ENABLE                   _MK_ENUM_CONST(1)
+
+// Enable the channel13 count
+#define APBDMA_CNTRL_REG_0_CH13_CNT_EN_SHIFT                    _MK_SHIFT_CONST(29)
+#define APBDMA_CNTRL_REG_0_CH13_CNT_EN_FIELD                    (_MK_MASK_CONST(0x1) << APBDMA_CNTRL_REG_0_CH13_CNT_EN_SHIFT)
+#define APBDMA_CNTRL_REG_0_CH13_CNT_EN_RANGE                    29:29
+#define APBDMA_CNTRL_REG_0_CH13_CNT_EN_WOFFSET                  0x0
+#define APBDMA_CNTRL_REG_0_CH13_CNT_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH13_CNT_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMA_CNTRL_REG_0_CH13_CNT_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH13_CNT_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH13_CNT_EN_DISABLE                  _MK_ENUM_CONST(0)
+#define APBDMA_CNTRL_REG_0_CH13_CNT_EN_ENABLE                   _MK_ENUM_CONST(1)
+
+// Enable the channel12 count
+#define APBDMA_CNTRL_REG_0_CH12_CNT_EN_SHIFT                    _MK_SHIFT_CONST(28)
+#define APBDMA_CNTRL_REG_0_CH12_CNT_EN_FIELD                    (_MK_MASK_CONST(0x1) << APBDMA_CNTRL_REG_0_CH12_CNT_EN_SHIFT)
+#define APBDMA_CNTRL_REG_0_CH12_CNT_EN_RANGE                    28:28
+#define APBDMA_CNTRL_REG_0_CH12_CNT_EN_WOFFSET                  0x0
+#define APBDMA_CNTRL_REG_0_CH12_CNT_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH12_CNT_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMA_CNTRL_REG_0_CH12_CNT_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH12_CNT_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH12_CNT_EN_DISABLE                  _MK_ENUM_CONST(0)
+#define APBDMA_CNTRL_REG_0_CH12_CNT_EN_ENABLE                   _MK_ENUM_CONST(1)
+
+// Enable the channel11 count
+#define APBDMA_CNTRL_REG_0_CH11_CNT_EN_SHIFT                    _MK_SHIFT_CONST(27)
+#define APBDMA_CNTRL_REG_0_CH11_CNT_EN_FIELD                    (_MK_MASK_CONST(0x1) << APBDMA_CNTRL_REG_0_CH11_CNT_EN_SHIFT)
+#define APBDMA_CNTRL_REG_0_CH11_CNT_EN_RANGE                    27:27
+#define APBDMA_CNTRL_REG_0_CH11_CNT_EN_WOFFSET                  0x0
+#define APBDMA_CNTRL_REG_0_CH11_CNT_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH11_CNT_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMA_CNTRL_REG_0_CH11_CNT_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH11_CNT_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH11_CNT_EN_DISABLE                  _MK_ENUM_CONST(0)
+#define APBDMA_CNTRL_REG_0_CH11_CNT_EN_ENABLE                   _MK_ENUM_CONST(1)
+
+// Enable the channel10 count
+#define APBDMA_CNTRL_REG_0_CH10_CNT_EN_SHIFT                    _MK_SHIFT_CONST(26)
+#define APBDMA_CNTRL_REG_0_CH10_CNT_EN_FIELD                    (_MK_MASK_CONST(0x1) << APBDMA_CNTRL_REG_0_CH10_CNT_EN_SHIFT)
+#define APBDMA_CNTRL_REG_0_CH10_CNT_EN_RANGE                    26:26
+#define APBDMA_CNTRL_REG_0_CH10_CNT_EN_WOFFSET                  0x0
+#define APBDMA_CNTRL_REG_0_CH10_CNT_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH10_CNT_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMA_CNTRL_REG_0_CH10_CNT_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH10_CNT_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH10_CNT_EN_DISABLE                  _MK_ENUM_CONST(0)
+#define APBDMA_CNTRL_REG_0_CH10_CNT_EN_ENABLE                   _MK_ENUM_CONST(1)
+
+// Enable the channel9 count
+#define APBDMA_CNTRL_REG_0_CH9_CNT_EN_SHIFT                     _MK_SHIFT_CONST(25)
+#define APBDMA_CNTRL_REG_0_CH9_CNT_EN_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_CNTRL_REG_0_CH9_CNT_EN_SHIFT)
+#define APBDMA_CNTRL_REG_0_CH9_CNT_EN_RANGE                     25:25
+#define APBDMA_CNTRL_REG_0_CH9_CNT_EN_WOFFSET                   0x0
+#define APBDMA_CNTRL_REG_0_CH9_CNT_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH9_CNT_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_CNTRL_REG_0_CH9_CNT_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH9_CNT_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH9_CNT_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMA_CNTRL_REG_0_CH9_CNT_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// Enable the channel8 count
+#define APBDMA_CNTRL_REG_0_CH8_CNT_EN_SHIFT                     _MK_SHIFT_CONST(24)
+#define APBDMA_CNTRL_REG_0_CH8_CNT_EN_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_CNTRL_REG_0_CH8_CNT_EN_SHIFT)
+#define APBDMA_CNTRL_REG_0_CH8_CNT_EN_RANGE                     24:24
+#define APBDMA_CNTRL_REG_0_CH8_CNT_EN_WOFFSET                   0x0
+#define APBDMA_CNTRL_REG_0_CH8_CNT_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH8_CNT_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_CNTRL_REG_0_CH8_CNT_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH8_CNT_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH8_CNT_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMA_CNTRL_REG_0_CH8_CNT_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// Enable the channel7 count
+#define APBDMA_CNTRL_REG_0_CH7_CNT_EN_SHIFT                     _MK_SHIFT_CONST(23)
+#define APBDMA_CNTRL_REG_0_CH7_CNT_EN_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_CNTRL_REG_0_CH7_CNT_EN_SHIFT)
+#define APBDMA_CNTRL_REG_0_CH7_CNT_EN_RANGE                     23:23
+#define APBDMA_CNTRL_REG_0_CH7_CNT_EN_WOFFSET                   0x0
+#define APBDMA_CNTRL_REG_0_CH7_CNT_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH7_CNT_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_CNTRL_REG_0_CH7_CNT_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH7_CNT_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH7_CNT_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMA_CNTRL_REG_0_CH7_CNT_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// Enable the channel6 count
+#define APBDMA_CNTRL_REG_0_CH6_CNT_EN_SHIFT                     _MK_SHIFT_CONST(22)
+#define APBDMA_CNTRL_REG_0_CH6_CNT_EN_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_CNTRL_REG_0_CH6_CNT_EN_SHIFT)
+#define APBDMA_CNTRL_REG_0_CH6_CNT_EN_RANGE                     22:22
+#define APBDMA_CNTRL_REG_0_CH6_CNT_EN_WOFFSET                   0x0
+#define APBDMA_CNTRL_REG_0_CH6_CNT_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH6_CNT_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_CNTRL_REG_0_CH6_CNT_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH6_CNT_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH6_CNT_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMA_CNTRL_REG_0_CH6_CNT_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// Enable the channel5 count
+#define APBDMA_CNTRL_REG_0_CH5_CNT_EN_SHIFT                     _MK_SHIFT_CONST(21)
+#define APBDMA_CNTRL_REG_0_CH5_CNT_EN_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_CNTRL_REG_0_CH5_CNT_EN_SHIFT)
+#define APBDMA_CNTRL_REG_0_CH5_CNT_EN_RANGE                     21:21
+#define APBDMA_CNTRL_REG_0_CH5_CNT_EN_WOFFSET                   0x0
+#define APBDMA_CNTRL_REG_0_CH5_CNT_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH5_CNT_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_CNTRL_REG_0_CH5_CNT_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH5_CNT_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH5_CNT_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMA_CNTRL_REG_0_CH5_CNT_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// Enable the channel4 count
+#define APBDMA_CNTRL_REG_0_CH4_CNT_EN_SHIFT                     _MK_SHIFT_CONST(20)
+#define APBDMA_CNTRL_REG_0_CH4_CNT_EN_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_CNTRL_REG_0_CH4_CNT_EN_SHIFT)
+#define APBDMA_CNTRL_REG_0_CH4_CNT_EN_RANGE                     20:20
+#define APBDMA_CNTRL_REG_0_CH4_CNT_EN_WOFFSET                   0x0
+#define APBDMA_CNTRL_REG_0_CH4_CNT_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH4_CNT_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_CNTRL_REG_0_CH4_CNT_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH4_CNT_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH4_CNT_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMA_CNTRL_REG_0_CH4_CNT_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// Enable the channel3 count
+#define APBDMA_CNTRL_REG_0_CH3_CNT_EN_SHIFT                     _MK_SHIFT_CONST(19)
+#define APBDMA_CNTRL_REG_0_CH3_CNT_EN_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_CNTRL_REG_0_CH3_CNT_EN_SHIFT)
+#define APBDMA_CNTRL_REG_0_CH3_CNT_EN_RANGE                     19:19
+#define APBDMA_CNTRL_REG_0_CH3_CNT_EN_WOFFSET                   0x0
+#define APBDMA_CNTRL_REG_0_CH3_CNT_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH3_CNT_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_CNTRL_REG_0_CH3_CNT_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH3_CNT_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH3_CNT_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMA_CNTRL_REG_0_CH3_CNT_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// Enable the channel2 count
+#define APBDMA_CNTRL_REG_0_CH2_CNT_EN_SHIFT                     _MK_SHIFT_CONST(18)
+#define APBDMA_CNTRL_REG_0_CH2_CNT_EN_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_CNTRL_REG_0_CH2_CNT_EN_SHIFT)
+#define APBDMA_CNTRL_REG_0_CH2_CNT_EN_RANGE                     18:18
+#define APBDMA_CNTRL_REG_0_CH2_CNT_EN_WOFFSET                   0x0
+#define APBDMA_CNTRL_REG_0_CH2_CNT_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH2_CNT_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_CNTRL_REG_0_CH2_CNT_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH2_CNT_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH2_CNT_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMA_CNTRL_REG_0_CH2_CNT_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// Enable the channel1 count
+#define APBDMA_CNTRL_REG_0_CH1_CNT_EN_SHIFT                     _MK_SHIFT_CONST(17)
+#define APBDMA_CNTRL_REG_0_CH1_CNT_EN_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_CNTRL_REG_0_CH1_CNT_EN_SHIFT)
+#define APBDMA_CNTRL_REG_0_CH1_CNT_EN_RANGE                     17:17
+#define APBDMA_CNTRL_REG_0_CH1_CNT_EN_WOFFSET                   0x0
+#define APBDMA_CNTRL_REG_0_CH1_CNT_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH1_CNT_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_CNTRL_REG_0_CH1_CNT_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH1_CNT_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH1_CNT_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMA_CNTRL_REG_0_CH1_CNT_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// Enable the channel0 count
+#define APBDMA_CNTRL_REG_0_CH0_CNT_EN_SHIFT                     _MK_SHIFT_CONST(16)
+#define APBDMA_CNTRL_REG_0_CH0_CNT_EN_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_CNTRL_REG_0_CH0_CNT_EN_SHIFT)
+#define APBDMA_CNTRL_REG_0_CH0_CNT_EN_RANGE                     16:16
+#define APBDMA_CNTRL_REG_0_CH0_CNT_EN_WOFFSET                   0x0
+#define APBDMA_CNTRL_REG_0_CH0_CNT_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH0_CNT_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_CNTRL_REG_0_CH0_CNT_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH0_CNT_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH0_CNT_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMA_CNTRL_REG_0_CH0_CNT_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// DMA COUNT Value.
+#define APBDMA_CNTRL_REG_0_COUNT_VALUE_SHIFT                    _MK_SHIFT_CONST(0)
+#define APBDMA_CNTRL_REG_0_COUNT_VALUE_FIELD                    (_MK_MASK_CONST(0xffff) << APBDMA_CNTRL_REG_0_COUNT_VALUE_SHIFT)
+#define APBDMA_CNTRL_REG_0_COUNT_VALUE_RANGE                    15:0
+#define APBDMA_CNTRL_REG_0_COUNT_VALUE_WOFFSET                  0x0
+#define APBDMA_CNTRL_REG_0_COUNT_VALUE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_COUNT_VALUE_DEFAULT_MASK                     _MK_MASK_CONST(0xffff)
+#define APBDMA_CNTRL_REG_0_COUNT_VALUE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_COUNT_VALUE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register APBDMA_IRQ_STA_CPU_0  
+#define APBDMA_IRQ_STA_CPU_0                    _MK_ADDR_CONST(0x14)
+#define APBDMA_IRQ_STA_CPU_0_WORD_COUNT                         0x1
+#define APBDMA_IRQ_STA_CPU_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_RESET_MASK                         _MK_MASK_CONST(0xffff)
+#define APBDMA_IRQ_STA_CPU_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_READ_MASK                  _MK_MASK_CONST(0xffff)
+#define APBDMA_IRQ_STA_CPU_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
+// Gathers all the after-masking CPU directed IRQ status bits from channel15 
+#define APBDMA_IRQ_STA_CPU_0_CH15_SHIFT                 _MK_SHIFT_CONST(15)
+#define APBDMA_IRQ_STA_CPU_0_CH15_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_CPU_0_CH15_SHIFT)
+#define APBDMA_IRQ_STA_CPU_0_CH15_RANGE                 15:15
+#define APBDMA_IRQ_STA_CPU_0_CH15_WOFFSET                       0x0
+#define APBDMA_IRQ_STA_CPU_0_CH15_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH15_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_CPU_0_CH15_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH15_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH15_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_CPU_0_CH15_ENABLE                        _MK_ENUM_CONST(1)
+
+// Gathers all the after-masking CPU directed IRQ status bits from channel14 
+#define APBDMA_IRQ_STA_CPU_0_CH14_SHIFT                 _MK_SHIFT_CONST(14)
+#define APBDMA_IRQ_STA_CPU_0_CH14_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_CPU_0_CH14_SHIFT)
+#define APBDMA_IRQ_STA_CPU_0_CH14_RANGE                 14:14
+#define APBDMA_IRQ_STA_CPU_0_CH14_WOFFSET                       0x0
+#define APBDMA_IRQ_STA_CPU_0_CH14_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH14_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_CPU_0_CH14_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH14_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH14_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_CPU_0_CH14_ENABLE                        _MK_ENUM_CONST(1)
+
+// Gathers all the after-masking CPU directed IRQ status bits from channel13 
+#define APBDMA_IRQ_STA_CPU_0_CH13_SHIFT                 _MK_SHIFT_CONST(13)
+#define APBDMA_IRQ_STA_CPU_0_CH13_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_CPU_0_CH13_SHIFT)
+#define APBDMA_IRQ_STA_CPU_0_CH13_RANGE                 13:13
+#define APBDMA_IRQ_STA_CPU_0_CH13_WOFFSET                       0x0
+#define APBDMA_IRQ_STA_CPU_0_CH13_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH13_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_CPU_0_CH13_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH13_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH13_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_CPU_0_CH13_ENABLE                        _MK_ENUM_CONST(1)
+
+// Gathers all the after-masking CPU directed IRQ status bits from channel12 
+#define APBDMA_IRQ_STA_CPU_0_CH12_SHIFT                 _MK_SHIFT_CONST(12)
+#define APBDMA_IRQ_STA_CPU_0_CH12_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_CPU_0_CH12_SHIFT)
+#define APBDMA_IRQ_STA_CPU_0_CH12_RANGE                 12:12
+#define APBDMA_IRQ_STA_CPU_0_CH12_WOFFSET                       0x0
+#define APBDMA_IRQ_STA_CPU_0_CH12_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH12_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_CPU_0_CH12_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH12_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH12_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_CPU_0_CH12_ENABLE                        _MK_ENUM_CONST(1)
+
+// Gathers all the after-masking CPU directed IRQ status bits from channel11 
+#define APBDMA_IRQ_STA_CPU_0_CH11_SHIFT                 _MK_SHIFT_CONST(11)
+#define APBDMA_IRQ_STA_CPU_0_CH11_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_CPU_0_CH11_SHIFT)
+#define APBDMA_IRQ_STA_CPU_0_CH11_RANGE                 11:11
+#define APBDMA_IRQ_STA_CPU_0_CH11_WOFFSET                       0x0
+#define APBDMA_IRQ_STA_CPU_0_CH11_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH11_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_CPU_0_CH11_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH11_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH11_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_CPU_0_CH11_ENABLE                        _MK_ENUM_CONST(1)
+
+// Gathers all the after-masking CPU directed IRQ status bits from channel10 
+#define APBDMA_IRQ_STA_CPU_0_CH10_SHIFT                 _MK_SHIFT_CONST(10)
+#define APBDMA_IRQ_STA_CPU_0_CH10_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_CPU_0_CH10_SHIFT)
+#define APBDMA_IRQ_STA_CPU_0_CH10_RANGE                 10:10
+#define APBDMA_IRQ_STA_CPU_0_CH10_WOFFSET                       0x0
+#define APBDMA_IRQ_STA_CPU_0_CH10_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH10_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_CPU_0_CH10_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH10_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH10_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_CPU_0_CH10_ENABLE                        _MK_ENUM_CONST(1)
+
+// Gathers all the after-masking CPU directed IRQ status bits from channel9 
+#define APBDMA_IRQ_STA_CPU_0_CH9_SHIFT                  _MK_SHIFT_CONST(9)
+#define APBDMA_IRQ_STA_CPU_0_CH9_FIELD                  (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_CPU_0_CH9_SHIFT)
+#define APBDMA_IRQ_STA_CPU_0_CH9_RANGE                  9:9
+#define APBDMA_IRQ_STA_CPU_0_CH9_WOFFSET                        0x0
+#define APBDMA_IRQ_STA_CPU_0_CH9_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH9_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_CPU_0_CH9_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH9_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH9_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_CPU_0_CH9_ENABLE                 _MK_ENUM_CONST(1)
+
+// Gathers all the after-masking CPU directed IRQ status bits from channel8 
+#define APBDMA_IRQ_STA_CPU_0_CH8_SHIFT                  _MK_SHIFT_CONST(8)
+#define APBDMA_IRQ_STA_CPU_0_CH8_FIELD                  (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_CPU_0_CH8_SHIFT)
+#define APBDMA_IRQ_STA_CPU_0_CH8_RANGE                  8:8
+#define APBDMA_IRQ_STA_CPU_0_CH8_WOFFSET                        0x0
+#define APBDMA_IRQ_STA_CPU_0_CH8_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH8_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_CPU_0_CH8_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH8_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH8_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_CPU_0_CH8_ENABLE                 _MK_ENUM_CONST(1)
+
+// Gathers all the after-masking CPU directed IRQ status bits from channel7 
+#define APBDMA_IRQ_STA_CPU_0_CH7_SHIFT                  _MK_SHIFT_CONST(7)
+#define APBDMA_IRQ_STA_CPU_0_CH7_FIELD                  (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_CPU_0_CH7_SHIFT)
+#define APBDMA_IRQ_STA_CPU_0_CH7_RANGE                  7:7
+#define APBDMA_IRQ_STA_CPU_0_CH7_WOFFSET                        0x0
+#define APBDMA_IRQ_STA_CPU_0_CH7_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH7_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_CPU_0_CH7_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH7_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH7_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_CPU_0_CH7_ENABLE                 _MK_ENUM_CONST(1)
+
+// Gathers all the after-masking CPU directed IRQ status bits from channel6 
+#define APBDMA_IRQ_STA_CPU_0_CH6_SHIFT                  _MK_SHIFT_CONST(6)
+#define APBDMA_IRQ_STA_CPU_0_CH6_FIELD                  (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_CPU_0_CH6_SHIFT)
+#define APBDMA_IRQ_STA_CPU_0_CH6_RANGE                  6:6
+#define APBDMA_IRQ_STA_CPU_0_CH6_WOFFSET                        0x0
+#define APBDMA_IRQ_STA_CPU_0_CH6_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH6_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_CPU_0_CH6_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH6_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH6_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_CPU_0_CH6_ENABLE                 _MK_ENUM_CONST(1)
+
+// Gathers all the after-masking CPU directed IRQ status bits from channel5 
+#define APBDMA_IRQ_STA_CPU_0_CH5_SHIFT                  _MK_SHIFT_CONST(5)
+#define APBDMA_IRQ_STA_CPU_0_CH5_FIELD                  (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_CPU_0_CH5_SHIFT)
+#define APBDMA_IRQ_STA_CPU_0_CH5_RANGE                  5:5
+#define APBDMA_IRQ_STA_CPU_0_CH5_WOFFSET                        0x0
+#define APBDMA_IRQ_STA_CPU_0_CH5_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH5_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_CPU_0_CH5_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH5_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH5_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_CPU_0_CH5_ENABLE                 _MK_ENUM_CONST(1)
+
+// Gathers all the after-masking CPU directed IRQ status bits from channel4 
+#define APBDMA_IRQ_STA_CPU_0_CH4_SHIFT                  _MK_SHIFT_CONST(4)
+#define APBDMA_IRQ_STA_CPU_0_CH4_FIELD                  (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_CPU_0_CH4_SHIFT)
+#define APBDMA_IRQ_STA_CPU_0_CH4_RANGE                  4:4
+#define APBDMA_IRQ_STA_CPU_0_CH4_WOFFSET                        0x0
+#define APBDMA_IRQ_STA_CPU_0_CH4_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH4_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_CPU_0_CH4_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH4_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH4_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_CPU_0_CH4_ENABLE                 _MK_ENUM_CONST(1)
+
+// Gathers all the after-masking CPU directed IRQ status bits from channel3 
+#define APBDMA_IRQ_STA_CPU_0_CH3_SHIFT                  _MK_SHIFT_CONST(3)
+#define APBDMA_IRQ_STA_CPU_0_CH3_FIELD                  (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_CPU_0_CH3_SHIFT)
+#define APBDMA_IRQ_STA_CPU_0_CH3_RANGE                  3:3
+#define APBDMA_IRQ_STA_CPU_0_CH3_WOFFSET                        0x0
+#define APBDMA_IRQ_STA_CPU_0_CH3_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH3_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_CPU_0_CH3_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH3_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH3_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_CPU_0_CH3_ENABLE                 _MK_ENUM_CONST(1)
+
+// Gathers all the after-masking CPU directed IRQ status bits from channel2 
+#define APBDMA_IRQ_STA_CPU_0_CH2_SHIFT                  _MK_SHIFT_CONST(2)
+#define APBDMA_IRQ_STA_CPU_0_CH2_FIELD                  (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_CPU_0_CH2_SHIFT)
+#define APBDMA_IRQ_STA_CPU_0_CH2_RANGE                  2:2
+#define APBDMA_IRQ_STA_CPU_0_CH2_WOFFSET                        0x0
+#define APBDMA_IRQ_STA_CPU_0_CH2_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH2_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_CPU_0_CH2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH2_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_CPU_0_CH2_ENABLE                 _MK_ENUM_CONST(1)
+
+// Gathers all the after-masking CPU directed IRQ status bits from channel1 
+#define APBDMA_IRQ_STA_CPU_0_CH1_SHIFT                  _MK_SHIFT_CONST(1)
+#define APBDMA_IRQ_STA_CPU_0_CH1_FIELD                  (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_CPU_0_CH1_SHIFT)
+#define APBDMA_IRQ_STA_CPU_0_CH1_RANGE                  1:1
+#define APBDMA_IRQ_STA_CPU_0_CH1_WOFFSET                        0x0
+#define APBDMA_IRQ_STA_CPU_0_CH1_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH1_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_CPU_0_CH1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH1_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_CPU_0_CH1_ENABLE                 _MK_ENUM_CONST(1)
+
+// Gathers all the after-masking CPU directed IRQ status bits from channel0 
+#define APBDMA_IRQ_STA_CPU_0_CH0_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDMA_IRQ_STA_CPU_0_CH0_FIELD                  (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_CPU_0_CH0_SHIFT)
+#define APBDMA_IRQ_STA_CPU_0_CH0_RANGE                  0:0
+#define APBDMA_IRQ_STA_CPU_0_CH0_WOFFSET                        0x0
+#define APBDMA_IRQ_STA_CPU_0_CH0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH0_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_CPU_0_CH0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH0_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_CPU_0_CH0_ENABLE                 _MK_ENUM_CONST(1)
+
+
+// Register APBDMA_IRQ_STA_COP_0  
+#define APBDMA_IRQ_STA_COP_0                    _MK_ADDR_CONST(0x18)
+#define APBDMA_IRQ_STA_COP_0_WORD_COUNT                         0x1
+#define APBDMA_IRQ_STA_COP_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_RESET_MASK                         _MK_MASK_CONST(0xffff)
+#define APBDMA_IRQ_STA_COP_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_READ_MASK                  _MK_MASK_CONST(0xffff)
+#define APBDMA_IRQ_STA_COP_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
+// Gathers all the after-masking COP directed IRQ status bits from channel15 
+#define APBDMA_IRQ_STA_COP_0_CH15_SHIFT                 _MK_SHIFT_CONST(15)
+#define APBDMA_IRQ_STA_COP_0_CH15_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_COP_0_CH15_SHIFT)
+#define APBDMA_IRQ_STA_COP_0_CH15_RANGE                 15:15
+#define APBDMA_IRQ_STA_COP_0_CH15_WOFFSET                       0x0
+#define APBDMA_IRQ_STA_COP_0_CH15_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH15_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_COP_0_CH15_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH15_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH15_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_COP_0_CH15_ENABLE                        _MK_ENUM_CONST(1)
+
+// Gathers all the after-masking COP directed IRQ status bits from channel14 
+#define APBDMA_IRQ_STA_COP_0_CH14_SHIFT                 _MK_SHIFT_CONST(14)
+#define APBDMA_IRQ_STA_COP_0_CH14_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_COP_0_CH14_SHIFT)
+#define APBDMA_IRQ_STA_COP_0_CH14_RANGE                 14:14
+#define APBDMA_IRQ_STA_COP_0_CH14_WOFFSET                       0x0
+#define APBDMA_IRQ_STA_COP_0_CH14_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH14_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_COP_0_CH14_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH14_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH14_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_COP_0_CH14_ENABLE                        _MK_ENUM_CONST(1)
+
+// Gathers all the after-masking COP directed IRQ status bits from channel13 
+#define APBDMA_IRQ_STA_COP_0_CH13_SHIFT                 _MK_SHIFT_CONST(13)
+#define APBDMA_IRQ_STA_COP_0_CH13_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_COP_0_CH13_SHIFT)
+#define APBDMA_IRQ_STA_COP_0_CH13_RANGE                 13:13
+#define APBDMA_IRQ_STA_COP_0_CH13_WOFFSET                       0x0
+#define APBDMA_IRQ_STA_COP_0_CH13_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH13_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_COP_0_CH13_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH13_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH13_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_COP_0_CH13_ENABLE                        _MK_ENUM_CONST(1)
+
+// Gathers all the after-masking COP directed IRQ status bits from channel12 
+#define APBDMA_IRQ_STA_COP_0_CH12_SHIFT                 _MK_SHIFT_CONST(12)
+#define APBDMA_IRQ_STA_COP_0_CH12_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_COP_0_CH12_SHIFT)
+#define APBDMA_IRQ_STA_COP_0_CH12_RANGE                 12:12
+#define APBDMA_IRQ_STA_COP_0_CH12_WOFFSET                       0x0
+#define APBDMA_IRQ_STA_COP_0_CH12_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH12_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_COP_0_CH12_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH12_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH12_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_COP_0_CH12_ENABLE                        _MK_ENUM_CONST(1)
+
+// Gathers all the after-masking COP directed IRQ status bits from channel11 
+#define APBDMA_IRQ_STA_COP_0_CH11_SHIFT                 _MK_SHIFT_CONST(11)
+#define APBDMA_IRQ_STA_COP_0_CH11_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_COP_0_CH11_SHIFT)
+#define APBDMA_IRQ_STA_COP_0_CH11_RANGE                 11:11
+#define APBDMA_IRQ_STA_COP_0_CH11_WOFFSET                       0x0
+#define APBDMA_IRQ_STA_COP_0_CH11_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH11_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_COP_0_CH11_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH11_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH11_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_COP_0_CH11_ENABLE                        _MK_ENUM_CONST(1)
+
+// Gathers all the after-masking COP directed IRQ status bits from channel10 
+#define APBDMA_IRQ_STA_COP_0_CH10_SHIFT                 _MK_SHIFT_CONST(10)
+#define APBDMA_IRQ_STA_COP_0_CH10_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_COP_0_CH10_SHIFT)
+#define APBDMA_IRQ_STA_COP_0_CH10_RANGE                 10:10
+#define APBDMA_IRQ_STA_COP_0_CH10_WOFFSET                       0x0
+#define APBDMA_IRQ_STA_COP_0_CH10_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH10_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_COP_0_CH10_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH10_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH10_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_COP_0_CH10_ENABLE                        _MK_ENUM_CONST(1)
+
+// Gathers all the after-masking COP directed IRQ status bits from channel9 
+#define APBDMA_IRQ_STA_COP_0_CH9_SHIFT                  _MK_SHIFT_CONST(9)
+#define APBDMA_IRQ_STA_COP_0_CH9_FIELD                  (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_COP_0_CH9_SHIFT)
+#define APBDMA_IRQ_STA_COP_0_CH9_RANGE                  9:9
+#define APBDMA_IRQ_STA_COP_0_CH9_WOFFSET                        0x0
+#define APBDMA_IRQ_STA_COP_0_CH9_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH9_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_COP_0_CH9_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH9_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH9_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_COP_0_CH9_ENABLE                 _MK_ENUM_CONST(1)
+
+// Gathers all the after-masking COP directed IRQ status bits from channel8 
+#define APBDMA_IRQ_STA_COP_0_CH8_SHIFT                  _MK_SHIFT_CONST(8)
+#define APBDMA_IRQ_STA_COP_0_CH8_FIELD                  (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_COP_0_CH8_SHIFT)
+#define APBDMA_IRQ_STA_COP_0_CH8_RANGE                  8:8
+#define APBDMA_IRQ_STA_COP_0_CH8_WOFFSET                        0x0
+#define APBDMA_IRQ_STA_COP_0_CH8_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH8_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_COP_0_CH8_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH8_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH8_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_COP_0_CH8_ENABLE                 _MK_ENUM_CONST(1)
+
+// Gathers all the after-masking COP directed IRQ status bits from channel7 
+#define APBDMA_IRQ_STA_COP_0_CH7_SHIFT                  _MK_SHIFT_CONST(7)
+#define APBDMA_IRQ_STA_COP_0_CH7_FIELD                  (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_COP_0_CH7_SHIFT)
+#define APBDMA_IRQ_STA_COP_0_CH7_RANGE                  7:7
+#define APBDMA_IRQ_STA_COP_0_CH7_WOFFSET                        0x0
+#define APBDMA_IRQ_STA_COP_0_CH7_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH7_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_COP_0_CH7_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH7_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH7_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_COP_0_CH7_ENABLE                 _MK_ENUM_CONST(1)
+
+// Gathers all the after-masking COP directed IRQ status bits from channel6 
+#define APBDMA_IRQ_STA_COP_0_CH6_SHIFT                  _MK_SHIFT_CONST(6)
+#define APBDMA_IRQ_STA_COP_0_CH6_FIELD                  (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_COP_0_CH6_SHIFT)
+#define APBDMA_IRQ_STA_COP_0_CH6_RANGE                  6:6
+#define APBDMA_IRQ_STA_COP_0_CH6_WOFFSET                        0x0
+#define APBDMA_IRQ_STA_COP_0_CH6_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH6_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_COP_0_CH6_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH6_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH6_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_COP_0_CH6_ENABLE                 _MK_ENUM_CONST(1)
+
+// Gathers all the after-masking COP directed IRQ status bits from channel5 
+#define APBDMA_IRQ_STA_COP_0_CH5_SHIFT                  _MK_SHIFT_CONST(5)
+#define APBDMA_IRQ_STA_COP_0_CH5_FIELD                  (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_COP_0_CH5_SHIFT)
+#define APBDMA_IRQ_STA_COP_0_CH5_RANGE                  5:5
+#define APBDMA_IRQ_STA_COP_0_CH5_WOFFSET                        0x0
+#define APBDMA_IRQ_STA_COP_0_CH5_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH5_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_COP_0_CH5_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH5_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH5_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_COP_0_CH5_ENABLE                 _MK_ENUM_CONST(1)
+
+// Gathers all the after-masking COP directed IRQ status bits from channel4 
+#define APBDMA_IRQ_STA_COP_0_CH4_SHIFT                  _MK_SHIFT_CONST(4)
+#define APBDMA_IRQ_STA_COP_0_CH4_FIELD                  (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_COP_0_CH4_SHIFT)
+#define APBDMA_IRQ_STA_COP_0_CH4_RANGE                  4:4
+#define APBDMA_IRQ_STA_COP_0_CH4_WOFFSET                        0x0
+#define APBDMA_IRQ_STA_COP_0_CH4_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH4_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_COP_0_CH4_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH4_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH4_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_COP_0_CH4_ENABLE                 _MK_ENUM_CONST(1)
+
+// Gathers all the after-masking COP directed IRQ status bits from channel3 
+#define APBDMA_IRQ_STA_COP_0_CH3_SHIFT                  _MK_SHIFT_CONST(3)
+#define APBDMA_IRQ_STA_COP_0_CH3_FIELD                  (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_COP_0_CH3_SHIFT)
+#define APBDMA_IRQ_STA_COP_0_CH3_RANGE                  3:3
+#define APBDMA_IRQ_STA_COP_0_CH3_WOFFSET                        0x0
+#define APBDMA_IRQ_STA_COP_0_CH3_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH3_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_COP_0_CH3_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH3_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH3_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_COP_0_CH3_ENABLE                 _MK_ENUM_CONST(1)
+
+// Gathers all the after-masking COP directed IRQ status bits from channel2 
+#define APBDMA_IRQ_STA_COP_0_CH2_SHIFT                  _MK_SHIFT_CONST(2)
+#define APBDMA_IRQ_STA_COP_0_CH2_FIELD                  (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_COP_0_CH2_SHIFT)
+#define APBDMA_IRQ_STA_COP_0_CH2_RANGE                  2:2
+#define APBDMA_IRQ_STA_COP_0_CH2_WOFFSET                        0x0
+#define APBDMA_IRQ_STA_COP_0_CH2_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH2_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_COP_0_CH2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH2_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_COP_0_CH2_ENABLE                 _MK_ENUM_CONST(1)
+
+// Gathers all the after-masking COP directed IRQ status bits from channel1 
+#define APBDMA_IRQ_STA_COP_0_CH1_SHIFT                  _MK_SHIFT_CONST(1)
+#define APBDMA_IRQ_STA_COP_0_CH1_FIELD                  (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_COP_0_CH1_SHIFT)
+#define APBDMA_IRQ_STA_COP_0_CH1_RANGE                  1:1
+#define APBDMA_IRQ_STA_COP_0_CH1_WOFFSET                        0x0
+#define APBDMA_IRQ_STA_COP_0_CH1_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH1_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_COP_0_CH1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH1_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_COP_0_CH1_ENABLE                 _MK_ENUM_CONST(1)
+
+// Gathers all the after-masking COP directed IRQ status bits from channel0 
+#define APBDMA_IRQ_STA_COP_0_CH0_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDMA_IRQ_STA_COP_0_CH0_FIELD                  (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_COP_0_CH0_SHIFT)
+#define APBDMA_IRQ_STA_COP_0_CH0_RANGE                  0:0
+#define APBDMA_IRQ_STA_COP_0_CH0_WOFFSET                        0x0
+#define APBDMA_IRQ_STA_COP_0_CH0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH0_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_COP_0_CH0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH0_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_COP_0_CH0_ENABLE                 _MK_ENUM_CONST(1)
+
+
+// Register APBDMA_IRQ_MASK_0  
+#define APBDMA_IRQ_MASK_0                       _MK_ADDR_CONST(0x1c)
+#define APBDMA_IRQ_MASK_0_WORD_COUNT                    0x1
+#define APBDMA_IRQ_MASK_0_RESET_VAL                     _MK_MASK_CONST(0xffff)
+#define APBDMA_IRQ_MASK_0_RESET_MASK                    _MK_MASK_CONST(0xffff)
+#define APBDMA_IRQ_MASK_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_READ_MASK                     _MK_MASK_CONST(0xffff)
+#define APBDMA_IRQ_MASK_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+// Each bit allows the associated channel15 IRQ to propagate when '1' 
+#define APBDMA_IRQ_MASK_0_CH15_SHIFT                    _MK_SHIFT_CONST(15)
+#define APBDMA_IRQ_MASK_0_CH15_FIELD                    (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_0_CH15_SHIFT)
+#define APBDMA_IRQ_MASK_0_CH15_RANGE                    15:15
+#define APBDMA_IRQ_MASK_0_CH15_WOFFSET                  0x0
+#define APBDMA_IRQ_MASK_0_CH15_DEFAULT                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH15_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH15_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH15_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH15_DISABLE                  _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_0_CH15_ENABLE                   _MK_ENUM_CONST(1)
+
+// Each bit allows the associated channel14 IRQ to propagate when '1' 
+#define APBDMA_IRQ_MASK_0_CH14_SHIFT                    _MK_SHIFT_CONST(14)
+#define APBDMA_IRQ_MASK_0_CH14_FIELD                    (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_0_CH14_SHIFT)
+#define APBDMA_IRQ_MASK_0_CH14_RANGE                    14:14
+#define APBDMA_IRQ_MASK_0_CH14_WOFFSET                  0x0
+#define APBDMA_IRQ_MASK_0_CH14_DEFAULT                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH14_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH14_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH14_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH14_DISABLE                  _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_0_CH14_ENABLE                   _MK_ENUM_CONST(1)
+
+// Each bit allows the associated channel13 IRQ to propagate when '1' 
+#define APBDMA_IRQ_MASK_0_CH13_SHIFT                    _MK_SHIFT_CONST(13)
+#define APBDMA_IRQ_MASK_0_CH13_FIELD                    (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_0_CH13_SHIFT)
+#define APBDMA_IRQ_MASK_0_CH13_RANGE                    13:13
+#define APBDMA_IRQ_MASK_0_CH13_WOFFSET                  0x0
+#define APBDMA_IRQ_MASK_0_CH13_DEFAULT                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH13_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH13_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH13_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH13_DISABLE                  _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_0_CH13_ENABLE                   _MK_ENUM_CONST(1)
+
+// Each bit allows the associated channel12 IRQ to propagate when '1' 
+#define APBDMA_IRQ_MASK_0_CH12_SHIFT                    _MK_SHIFT_CONST(12)
+#define APBDMA_IRQ_MASK_0_CH12_FIELD                    (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_0_CH12_SHIFT)
+#define APBDMA_IRQ_MASK_0_CH12_RANGE                    12:12
+#define APBDMA_IRQ_MASK_0_CH12_WOFFSET                  0x0
+#define APBDMA_IRQ_MASK_0_CH12_DEFAULT                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH12_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH12_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH12_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH12_DISABLE                  _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_0_CH12_ENABLE                   _MK_ENUM_CONST(1)
+
+// Each bit allows the associated channel11 IRQ to propagate when '1' 
+#define APBDMA_IRQ_MASK_0_CH11_SHIFT                    _MK_SHIFT_CONST(11)
+#define APBDMA_IRQ_MASK_0_CH11_FIELD                    (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_0_CH11_SHIFT)
+#define APBDMA_IRQ_MASK_0_CH11_RANGE                    11:11
+#define APBDMA_IRQ_MASK_0_CH11_WOFFSET                  0x0
+#define APBDMA_IRQ_MASK_0_CH11_DEFAULT                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH11_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH11_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH11_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH11_DISABLE                  _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_0_CH11_ENABLE                   _MK_ENUM_CONST(1)
+
+// Each bit allows the associated channel10 IRQ to propagate when '1' 
+#define APBDMA_IRQ_MASK_0_CH10_SHIFT                    _MK_SHIFT_CONST(10)
+#define APBDMA_IRQ_MASK_0_CH10_FIELD                    (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_0_CH10_SHIFT)
+#define APBDMA_IRQ_MASK_0_CH10_RANGE                    10:10
+#define APBDMA_IRQ_MASK_0_CH10_WOFFSET                  0x0
+#define APBDMA_IRQ_MASK_0_CH10_DEFAULT                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH10_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH10_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH10_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH10_DISABLE                  _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_0_CH10_ENABLE                   _MK_ENUM_CONST(1)
+
+// Each bit allows the associated channel9 IRQ to propagate when '1' 
+#define APBDMA_IRQ_MASK_0_CH9_SHIFT                     _MK_SHIFT_CONST(9)
+#define APBDMA_IRQ_MASK_0_CH9_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_0_CH9_SHIFT)
+#define APBDMA_IRQ_MASK_0_CH9_RANGE                     9:9
+#define APBDMA_IRQ_MASK_0_CH9_WOFFSET                   0x0
+#define APBDMA_IRQ_MASK_0_CH9_DEFAULT                   _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH9_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH9_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH9_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH9_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_0_CH9_ENABLE                    _MK_ENUM_CONST(1)
+
+// Each bit allows the associated channel8 IRQ to propagate when '1' 
+#define APBDMA_IRQ_MASK_0_CH8_SHIFT                     _MK_SHIFT_CONST(8)
+#define APBDMA_IRQ_MASK_0_CH8_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_0_CH8_SHIFT)
+#define APBDMA_IRQ_MASK_0_CH8_RANGE                     8:8
+#define APBDMA_IRQ_MASK_0_CH8_WOFFSET                   0x0
+#define APBDMA_IRQ_MASK_0_CH8_DEFAULT                   _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH8_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH8_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH8_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH8_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_0_CH8_ENABLE                    _MK_ENUM_CONST(1)
+
+// Each bit allows the associated channel7 IRQ to propagate when '1' 
+#define APBDMA_IRQ_MASK_0_CH7_SHIFT                     _MK_SHIFT_CONST(7)
+#define APBDMA_IRQ_MASK_0_CH7_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_0_CH7_SHIFT)
+#define APBDMA_IRQ_MASK_0_CH7_RANGE                     7:7
+#define APBDMA_IRQ_MASK_0_CH7_WOFFSET                   0x0
+#define APBDMA_IRQ_MASK_0_CH7_DEFAULT                   _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH7_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH7_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH7_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH7_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_0_CH7_ENABLE                    _MK_ENUM_CONST(1)
+
+// Each bit allows the associated channel6 IRQ to propagate when '1' 
+#define APBDMA_IRQ_MASK_0_CH6_SHIFT                     _MK_SHIFT_CONST(6)
+#define APBDMA_IRQ_MASK_0_CH6_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_0_CH6_SHIFT)
+#define APBDMA_IRQ_MASK_0_CH6_RANGE                     6:6
+#define APBDMA_IRQ_MASK_0_CH6_WOFFSET                   0x0
+#define APBDMA_IRQ_MASK_0_CH6_DEFAULT                   _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH6_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH6_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH6_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH6_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_0_CH6_ENABLE                    _MK_ENUM_CONST(1)
+
+// Each bit allows the associated channel5 IRQ to propagate when '1' 
+#define APBDMA_IRQ_MASK_0_CH5_SHIFT                     _MK_SHIFT_CONST(5)
+#define APBDMA_IRQ_MASK_0_CH5_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_0_CH5_SHIFT)
+#define APBDMA_IRQ_MASK_0_CH5_RANGE                     5:5
+#define APBDMA_IRQ_MASK_0_CH5_WOFFSET                   0x0
+#define APBDMA_IRQ_MASK_0_CH5_DEFAULT                   _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH5_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH5_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH5_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH5_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_0_CH5_ENABLE                    _MK_ENUM_CONST(1)
+
+// Each bit allows the associated channel4 IRQ to propagate when '1' 
+#define APBDMA_IRQ_MASK_0_CH4_SHIFT                     _MK_SHIFT_CONST(4)
+#define APBDMA_IRQ_MASK_0_CH4_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_0_CH4_SHIFT)
+#define APBDMA_IRQ_MASK_0_CH4_RANGE                     4:4
+#define APBDMA_IRQ_MASK_0_CH4_WOFFSET                   0x0
+#define APBDMA_IRQ_MASK_0_CH4_DEFAULT                   _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH4_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH4_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH4_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH4_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_0_CH4_ENABLE                    _MK_ENUM_CONST(1)
+
+// Each bit allows the associated channel3 IRQ to propagate when '1' 
+#define APBDMA_IRQ_MASK_0_CH3_SHIFT                     _MK_SHIFT_CONST(3)
+#define APBDMA_IRQ_MASK_0_CH3_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_0_CH3_SHIFT)
+#define APBDMA_IRQ_MASK_0_CH3_RANGE                     3:3
+#define APBDMA_IRQ_MASK_0_CH3_WOFFSET                   0x0
+#define APBDMA_IRQ_MASK_0_CH3_DEFAULT                   _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH3_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH3_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH3_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH3_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_0_CH3_ENABLE                    _MK_ENUM_CONST(1)
+
+// Each bit allows the associated channel2 IRQ to propagate when '1' 
+#define APBDMA_IRQ_MASK_0_CH2_SHIFT                     _MK_SHIFT_CONST(2)
+#define APBDMA_IRQ_MASK_0_CH2_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_0_CH2_SHIFT)
+#define APBDMA_IRQ_MASK_0_CH2_RANGE                     2:2
+#define APBDMA_IRQ_MASK_0_CH2_WOFFSET                   0x0
+#define APBDMA_IRQ_MASK_0_CH2_DEFAULT                   _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH2_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH2_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_0_CH2_ENABLE                    _MK_ENUM_CONST(1)
+
+// Each bit allows the associated channel1 IRQ to propagate when '1' 
+#define APBDMA_IRQ_MASK_0_CH1_SHIFT                     _MK_SHIFT_CONST(1)
+#define APBDMA_IRQ_MASK_0_CH1_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_0_CH1_SHIFT)
+#define APBDMA_IRQ_MASK_0_CH1_RANGE                     1:1
+#define APBDMA_IRQ_MASK_0_CH1_WOFFSET                   0x0
+#define APBDMA_IRQ_MASK_0_CH1_DEFAULT                   _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH1_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH1_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_0_CH1_ENABLE                    _MK_ENUM_CONST(1)
+
+// Each bit allows the associated channel0 IRQ to propagate when '1' 
+#define APBDMA_IRQ_MASK_0_CH0_SHIFT                     _MK_SHIFT_CONST(0)
+#define APBDMA_IRQ_MASK_0_CH0_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_0_CH0_SHIFT)
+#define APBDMA_IRQ_MASK_0_CH0_RANGE                     0:0
+#define APBDMA_IRQ_MASK_0_CH0_WOFFSET                   0x0
+#define APBDMA_IRQ_MASK_0_CH0_DEFAULT                   _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH0_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH0_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_0_CH0_ENABLE                    _MK_ENUM_CONST(1)
+
+
+// Register APBDMA_IRQ_MASK_SET_0  
+#define APBDMA_IRQ_MASK_SET_0                   _MK_ADDR_CONST(0x20)
+#define APBDMA_IRQ_MASK_SET_0_WORD_COUNT                        0x1
+#define APBDMA_IRQ_MASK_SET_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_RESET_MASK                        _MK_MASK_CONST(0xffff)
+#define APBDMA_IRQ_MASK_SET_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_READ_MASK                         _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_WRITE_MASK                        _MK_MASK_CONST(0xffff)
+// Sets the Mask Register
+#define APBDMA_IRQ_MASK_SET_0_CH15_SHIFT                        _MK_SHIFT_CONST(15)
+#define APBDMA_IRQ_MASK_SET_0_CH15_FIELD                        (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_SET_0_CH15_SHIFT)
+#define APBDMA_IRQ_MASK_SET_0_CH15_RANGE                        15:15
+#define APBDMA_IRQ_MASK_SET_0_CH15_WOFFSET                      0x0
+#define APBDMA_IRQ_MASK_SET_0_CH15_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH15_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_SET_0_CH15_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH15_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH15_DISABLE                      _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_SET_0_CH15_ENABLE                       _MK_ENUM_CONST(1)
+
+// Sets the Mask Register
+#define APBDMA_IRQ_MASK_SET_0_CH14_SHIFT                        _MK_SHIFT_CONST(14)
+#define APBDMA_IRQ_MASK_SET_0_CH14_FIELD                        (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_SET_0_CH14_SHIFT)
+#define APBDMA_IRQ_MASK_SET_0_CH14_RANGE                        14:14
+#define APBDMA_IRQ_MASK_SET_0_CH14_WOFFSET                      0x0
+#define APBDMA_IRQ_MASK_SET_0_CH14_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH14_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_SET_0_CH14_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH14_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH14_DISABLE                      _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_SET_0_CH14_ENABLE                       _MK_ENUM_CONST(1)
+
+// Sets the Mask Register
+#define APBDMA_IRQ_MASK_SET_0_CH13_SHIFT                        _MK_SHIFT_CONST(13)
+#define APBDMA_IRQ_MASK_SET_0_CH13_FIELD                        (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_SET_0_CH13_SHIFT)
+#define APBDMA_IRQ_MASK_SET_0_CH13_RANGE                        13:13
+#define APBDMA_IRQ_MASK_SET_0_CH13_WOFFSET                      0x0
+#define APBDMA_IRQ_MASK_SET_0_CH13_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH13_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_SET_0_CH13_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH13_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH13_DISABLE                      _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_SET_0_CH13_ENABLE                       _MK_ENUM_CONST(1)
+
+// Sets the Mask Register
+#define APBDMA_IRQ_MASK_SET_0_CH12_SHIFT                        _MK_SHIFT_CONST(12)
+#define APBDMA_IRQ_MASK_SET_0_CH12_FIELD                        (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_SET_0_CH12_SHIFT)
+#define APBDMA_IRQ_MASK_SET_0_CH12_RANGE                        12:12
+#define APBDMA_IRQ_MASK_SET_0_CH12_WOFFSET                      0x0
+#define APBDMA_IRQ_MASK_SET_0_CH12_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH12_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_SET_0_CH12_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH12_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH12_DISABLE                      _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_SET_0_CH12_ENABLE                       _MK_ENUM_CONST(1)
+
+// Sets the Mask Register
+#define APBDMA_IRQ_MASK_SET_0_CH11_SHIFT                        _MK_SHIFT_CONST(11)
+#define APBDMA_IRQ_MASK_SET_0_CH11_FIELD                        (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_SET_0_CH11_SHIFT)
+#define APBDMA_IRQ_MASK_SET_0_CH11_RANGE                        11:11
+#define APBDMA_IRQ_MASK_SET_0_CH11_WOFFSET                      0x0
+#define APBDMA_IRQ_MASK_SET_0_CH11_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH11_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_SET_0_CH11_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH11_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH11_DISABLE                      _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_SET_0_CH11_ENABLE                       _MK_ENUM_CONST(1)
+
+// Sets the Mask Register
+#define APBDMA_IRQ_MASK_SET_0_CH10_SHIFT                        _MK_SHIFT_CONST(10)
+#define APBDMA_IRQ_MASK_SET_0_CH10_FIELD                        (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_SET_0_CH10_SHIFT)
+#define APBDMA_IRQ_MASK_SET_0_CH10_RANGE                        10:10
+#define APBDMA_IRQ_MASK_SET_0_CH10_WOFFSET                      0x0
+#define APBDMA_IRQ_MASK_SET_0_CH10_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH10_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_SET_0_CH10_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH10_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH10_DISABLE                      _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_SET_0_CH10_ENABLE                       _MK_ENUM_CONST(1)
+
+// Sets the Mask Register
+#define APBDMA_IRQ_MASK_SET_0_CH9_SHIFT                 _MK_SHIFT_CONST(9)
+#define APBDMA_IRQ_MASK_SET_0_CH9_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_SET_0_CH9_SHIFT)
+#define APBDMA_IRQ_MASK_SET_0_CH9_RANGE                 9:9
+#define APBDMA_IRQ_MASK_SET_0_CH9_WOFFSET                       0x0
+#define APBDMA_IRQ_MASK_SET_0_CH9_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH9_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_SET_0_CH9_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH9_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH9_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_SET_0_CH9_ENABLE                        _MK_ENUM_CONST(1)
+
+// Sets the Mask Register
+#define APBDMA_IRQ_MASK_SET_0_CH8_SHIFT                 _MK_SHIFT_CONST(8)
+#define APBDMA_IRQ_MASK_SET_0_CH8_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_SET_0_CH8_SHIFT)
+#define APBDMA_IRQ_MASK_SET_0_CH8_RANGE                 8:8
+#define APBDMA_IRQ_MASK_SET_0_CH8_WOFFSET                       0x0
+#define APBDMA_IRQ_MASK_SET_0_CH8_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH8_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_SET_0_CH8_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH8_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH8_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_SET_0_CH8_ENABLE                        _MK_ENUM_CONST(1)
+
+// Sets the Mask Register
+#define APBDMA_IRQ_MASK_SET_0_CH7_SHIFT                 _MK_SHIFT_CONST(7)
+#define APBDMA_IRQ_MASK_SET_0_CH7_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_SET_0_CH7_SHIFT)
+#define APBDMA_IRQ_MASK_SET_0_CH7_RANGE                 7:7
+#define APBDMA_IRQ_MASK_SET_0_CH7_WOFFSET                       0x0
+#define APBDMA_IRQ_MASK_SET_0_CH7_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH7_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_SET_0_CH7_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH7_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH7_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_SET_0_CH7_ENABLE                        _MK_ENUM_CONST(1)
+
+// Sets the Mask Register
+#define APBDMA_IRQ_MASK_SET_0_CH6_SHIFT                 _MK_SHIFT_CONST(6)
+#define APBDMA_IRQ_MASK_SET_0_CH6_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_SET_0_CH6_SHIFT)
+#define APBDMA_IRQ_MASK_SET_0_CH6_RANGE                 6:6
+#define APBDMA_IRQ_MASK_SET_0_CH6_WOFFSET                       0x0
+#define APBDMA_IRQ_MASK_SET_0_CH6_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH6_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_SET_0_CH6_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH6_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH6_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_SET_0_CH6_ENABLE                        _MK_ENUM_CONST(1)
+
+// Sets the Mask Register
+#define APBDMA_IRQ_MASK_SET_0_CH5_SHIFT                 _MK_SHIFT_CONST(5)
+#define APBDMA_IRQ_MASK_SET_0_CH5_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_SET_0_CH5_SHIFT)
+#define APBDMA_IRQ_MASK_SET_0_CH5_RANGE                 5:5
+#define APBDMA_IRQ_MASK_SET_0_CH5_WOFFSET                       0x0
+#define APBDMA_IRQ_MASK_SET_0_CH5_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH5_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_SET_0_CH5_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH5_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH5_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_SET_0_CH5_ENABLE                        _MK_ENUM_CONST(1)
+
+// Sets the Mask Register
+#define APBDMA_IRQ_MASK_SET_0_CH4_SHIFT                 _MK_SHIFT_CONST(4)
+#define APBDMA_IRQ_MASK_SET_0_CH4_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_SET_0_CH4_SHIFT)
+#define APBDMA_IRQ_MASK_SET_0_CH4_RANGE                 4:4
+#define APBDMA_IRQ_MASK_SET_0_CH4_WOFFSET                       0x0
+#define APBDMA_IRQ_MASK_SET_0_CH4_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH4_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_SET_0_CH4_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH4_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH4_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_SET_0_CH4_ENABLE                        _MK_ENUM_CONST(1)
+
+// Sets the Mask Register
+#define APBDMA_IRQ_MASK_SET_0_CH3_SHIFT                 _MK_SHIFT_CONST(3)
+#define APBDMA_IRQ_MASK_SET_0_CH3_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_SET_0_CH3_SHIFT)
+#define APBDMA_IRQ_MASK_SET_0_CH3_RANGE                 3:3
+#define APBDMA_IRQ_MASK_SET_0_CH3_WOFFSET                       0x0
+#define APBDMA_IRQ_MASK_SET_0_CH3_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH3_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_SET_0_CH3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH3_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_SET_0_CH3_ENABLE                        _MK_ENUM_CONST(1)
+
+// Sets the Mask Register
+#define APBDMA_IRQ_MASK_SET_0_CH2_SHIFT                 _MK_SHIFT_CONST(2)
+#define APBDMA_IRQ_MASK_SET_0_CH2_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_SET_0_CH2_SHIFT)
+#define APBDMA_IRQ_MASK_SET_0_CH2_RANGE                 2:2
+#define APBDMA_IRQ_MASK_SET_0_CH2_WOFFSET                       0x0
+#define APBDMA_IRQ_MASK_SET_0_CH2_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH2_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_SET_0_CH2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH2_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_SET_0_CH2_ENABLE                        _MK_ENUM_CONST(1)
+
+// Sets the Mask Register
+#define APBDMA_IRQ_MASK_SET_0_CH1_SHIFT                 _MK_SHIFT_CONST(1)
+#define APBDMA_IRQ_MASK_SET_0_CH1_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_SET_0_CH1_SHIFT)
+#define APBDMA_IRQ_MASK_SET_0_CH1_RANGE                 1:1
+#define APBDMA_IRQ_MASK_SET_0_CH1_WOFFSET                       0x0
+#define APBDMA_IRQ_MASK_SET_0_CH1_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH1_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_SET_0_CH1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH1_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_SET_0_CH1_ENABLE                        _MK_ENUM_CONST(1)
+
+// Sets the Mask Register
+#define APBDMA_IRQ_MASK_SET_0_CH0_SHIFT                 _MK_SHIFT_CONST(0)
+#define APBDMA_IRQ_MASK_SET_0_CH0_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_SET_0_CH0_SHIFT)
+#define APBDMA_IRQ_MASK_SET_0_CH0_RANGE                 0:0
+#define APBDMA_IRQ_MASK_SET_0_CH0_WOFFSET                       0x0
+#define APBDMA_IRQ_MASK_SET_0_CH0_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH0_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_SET_0_CH0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH0_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_SET_0_CH0_ENABLE                        _MK_ENUM_CONST(1)
+
+
+// Register APBDMA_IRQ_MASK_CLR_0  
+#define APBDMA_IRQ_MASK_CLR_0                   _MK_ADDR_CONST(0x24)
+#define APBDMA_IRQ_MASK_CLR_0_WORD_COUNT                        0x1
+#define APBDMA_IRQ_MASK_CLR_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_RESET_MASK                        _MK_MASK_CONST(0xffff)
+#define APBDMA_IRQ_MASK_CLR_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_READ_MASK                         _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_WRITE_MASK                        _MK_MASK_CONST(0xffff)
+// Clears the Mask Register
+#define APBDMA_IRQ_MASK_CLR_0_CH15_SHIFT                        _MK_SHIFT_CONST(15)
+#define APBDMA_IRQ_MASK_CLR_0_CH15_FIELD                        (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_CLR_0_CH15_SHIFT)
+#define APBDMA_IRQ_MASK_CLR_0_CH15_RANGE                        15:15
+#define APBDMA_IRQ_MASK_CLR_0_CH15_WOFFSET                      0x0
+#define APBDMA_IRQ_MASK_CLR_0_CH15_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH15_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_CLR_0_CH15_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH15_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH15_DISABLE                      _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_CLR_0_CH15_ENABLE                       _MK_ENUM_CONST(1)
+
+// Clears the Mask Register
+#define APBDMA_IRQ_MASK_CLR_0_CH14_SHIFT                        _MK_SHIFT_CONST(14)
+#define APBDMA_IRQ_MASK_CLR_0_CH14_FIELD                        (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_CLR_0_CH14_SHIFT)
+#define APBDMA_IRQ_MASK_CLR_0_CH14_RANGE                        14:14
+#define APBDMA_IRQ_MASK_CLR_0_CH14_WOFFSET                      0x0
+#define APBDMA_IRQ_MASK_CLR_0_CH14_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH14_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_CLR_0_CH14_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH14_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH14_DISABLE                      _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_CLR_0_CH14_ENABLE                       _MK_ENUM_CONST(1)
+
+// Clears the Mask Register
+#define APBDMA_IRQ_MASK_CLR_0_CH13_SHIFT                        _MK_SHIFT_CONST(13)
+#define APBDMA_IRQ_MASK_CLR_0_CH13_FIELD                        (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_CLR_0_CH13_SHIFT)
+#define APBDMA_IRQ_MASK_CLR_0_CH13_RANGE                        13:13
+#define APBDMA_IRQ_MASK_CLR_0_CH13_WOFFSET                      0x0
+#define APBDMA_IRQ_MASK_CLR_0_CH13_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH13_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_CLR_0_CH13_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH13_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH13_DISABLE                      _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_CLR_0_CH13_ENABLE                       _MK_ENUM_CONST(1)
+
+// Clears the Mask Register
+#define APBDMA_IRQ_MASK_CLR_0_CH12_SHIFT                        _MK_SHIFT_CONST(12)
+#define APBDMA_IRQ_MASK_CLR_0_CH12_FIELD                        (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_CLR_0_CH12_SHIFT)
+#define APBDMA_IRQ_MASK_CLR_0_CH12_RANGE                        12:12
+#define APBDMA_IRQ_MASK_CLR_0_CH12_WOFFSET                      0x0
+#define APBDMA_IRQ_MASK_CLR_0_CH12_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH12_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_CLR_0_CH12_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH12_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH12_DISABLE                      _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_CLR_0_CH12_ENABLE                       _MK_ENUM_CONST(1)
+
+// Clears the Mask Register
+#define APBDMA_IRQ_MASK_CLR_0_CH11_SHIFT                        _MK_SHIFT_CONST(11)
+#define APBDMA_IRQ_MASK_CLR_0_CH11_FIELD                        (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_CLR_0_CH11_SHIFT)
+#define APBDMA_IRQ_MASK_CLR_0_CH11_RANGE                        11:11
+#define APBDMA_IRQ_MASK_CLR_0_CH11_WOFFSET                      0x0
+#define APBDMA_IRQ_MASK_CLR_0_CH11_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH11_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_CLR_0_CH11_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH11_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH11_DISABLE                      _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_CLR_0_CH11_ENABLE                       _MK_ENUM_CONST(1)
+
+// Clears the Mask Register
+#define APBDMA_IRQ_MASK_CLR_0_CH10_SHIFT                        _MK_SHIFT_CONST(10)
+#define APBDMA_IRQ_MASK_CLR_0_CH10_FIELD                        (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_CLR_0_CH10_SHIFT)
+#define APBDMA_IRQ_MASK_CLR_0_CH10_RANGE                        10:10
+#define APBDMA_IRQ_MASK_CLR_0_CH10_WOFFSET                      0x0
+#define APBDMA_IRQ_MASK_CLR_0_CH10_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH10_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_CLR_0_CH10_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH10_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH10_DISABLE                      _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_CLR_0_CH10_ENABLE                       _MK_ENUM_CONST(1)
+
+// Clears the Mask Register
+#define APBDMA_IRQ_MASK_CLR_0_CH9_SHIFT                 _MK_SHIFT_CONST(9)
+#define APBDMA_IRQ_MASK_CLR_0_CH9_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_CLR_0_CH9_SHIFT)
+#define APBDMA_IRQ_MASK_CLR_0_CH9_RANGE                 9:9
+#define APBDMA_IRQ_MASK_CLR_0_CH9_WOFFSET                       0x0
+#define APBDMA_IRQ_MASK_CLR_0_CH9_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH9_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_CLR_0_CH9_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH9_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH9_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_CLR_0_CH9_ENABLE                        _MK_ENUM_CONST(1)
+
+// Clears the Mask Register
+#define APBDMA_IRQ_MASK_CLR_0_CH8_SHIFT                 _MK_SHIFT_CONST(8)
+#define APBDMA_IRQ_MASK_CLR_0_CH8_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_CLR_0_CH8_SHIFT)
+#define APBDMA_IRQ_MASK_CLR_0_CH8_RANGE                 8:8
+#define APBDMA_IRQ_MASK_CLR_0_CH8_WOFFSET                       0x0
+#define APBDMA_IRQ_MASK_CLR_0_CH8_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH8_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_CLR_0_CH8_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH8_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH8_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_CLR_0_CH8_ENABLE                        _MK_ENUM_CONST(1)
+
+// Clears the Mask Register
+#define APBDMA_IRQ_MASK_CLR_0_CH7_SHIFT                 _MK_SHIFT_CONST(7)
+#define APBDMA_IRQ_MASK_CLR_0_CH7_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_CLR_0_CH7_SHIFT)
+#define APBDMA_IRQ_MASK_CLR_0_CH7_RANGE                 7:7
+#define APBDMA_IRQ_MASK_CLR_0_CH7_WOFFSET                       0x0
+#define APBDMA_IRQ_MASK_CLR_0_CH7_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH7_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_CLR_0_CH7_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH7_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH7_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_CLR_0_CH7_ENABLE                        _MK_ENUM_CONST(1)
+
+// Clears the Mask Register
+#define APBDMA_IRQ_MASK_CLR_0_CH6_SHIFT                 _MK_SHIFT_CONST(6)
+#define APBDMA_IRQ_MASK_CLR_0_CH6_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_CLR_0_CH6_SHIFT)
+#define APBDMA_IRQ_MASK_CLR_0_CH6_RANGE                 6:6
+#define APBDMA_IRQ_MASK_CLR_0_CH6_WOFFSET                       0x0
+#define APBDMA_IRQ_MASK_CLR_0_CH6_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH6_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_CLR_0_CH6_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH6_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH6_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_CLR_0_CH6_ENABLE                        _MK_ENUM_CONST(1)
+
+// Clears the Mask Register
+#define APBDMA_IRQ_MASK_CLR_0_CH5_SHIFT                 _MK_SHIFT_CONST(5)
+#define APBDMA_IRQ_MASK_CLR_0_CH5_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_CLR_0_CH5_SHIFT)
+#define APBDMA_IRQ_MASK_CLR_0_CH5_RANGE                 5:5
+#define APBDMA_IRQ_MASK_CLR_0_CH5_WOFFSET                       0x0
+#define APBDMA_IRQ_MASK_CLR_0_CH5_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH5_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_CLR_0_CH5_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH5_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH5_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_CLR_0_CH5_ENABLE                        _MK_ENUM_CONST(1)
+
+// Clears the Mask Register
+#define APBDMA_IRQ_MASK_CLR_0_CH4_SHIFT                 _MK_SHIFT_CONST(4)
+#define APBDMA_IRQ_MASK_CLR_0_CH4_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_CLR_0_CH4_SHIFT)
+#define APBDMA_IRQ_MASK_CLR_0_CH4_RANGE                 4:4
+#define APBDMA_IRQ_MASK_CLR_0_CH4_WOFFSET                       0x0
+#define APBDMA_IRQ_MASK_CLR_0_CH4_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH4_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_CLR_0_CH4_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH4_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH4_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_CLR_0_CH4_ENABLE                        _MK_ENUM_CONST(1)
+
+// Clears the Mask Register
+#define APBDMA_IRQ_MASK_CLR_0_CH3_SHIFT                 _MK_SHIFT_CONST(3)
+#define APBDMA_IRQ_MASK_CLR_0_CH3_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_CLR_0_CH3_SHIFT)
+#define APBDMA_IRQ_MASK_CLR_0_CH3_RANGE                 3:3
+#define APBDMA_IRQ_MASK_CLR_0_CH3_WOFFSET                       0x0
+#define APBDMA_IRQ_MASK_CLR_0_CH3_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH3_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_CLR_0_CH3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH3_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_CLR_0_CH3_ENABLE                        _MK_ENUM_CONST(1)
+
+// Clears the Mask Register
+#define APBDMA_IRQ_MASK_CLR_0_CH2_SHIFT                 _MK_SHIFT_CONST(2)
+#define APBDMA_IRQ_MASK_CLR_0_CH2_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_CLR_0_CH2_SHIFT)
+#define APBDMA_IRQ_MASK_CLR_0_CH2_RANGE                 2:2
+#define APBDMA_IRQ_MASK_CLR_0_CH2_WOFFSET                       0x0
+#define APBDMA_IRQ_MASK_CLR_0_CH2_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH2_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_CLR_0_CH2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH2_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_CLR_0_CH2_ENABLE                        _MK_ENUM_CONST(1)
+
+// Clears the Mask Register
+#define APBDMA_IRQ_MASK_CLR_0_CH1_SHIFT                 _MK_SHIFT_CONST(1)
+#define APBDMA_IRQ_MASK_CLR_0_CH1_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_CLR_0_CH1_SHIFT)
+#define APBDMA_IRQ_MASK_CLR_0_CH1_RANGE                 1:1
+#define APBDMA_IRQ_MASK_CLR_0_CH1_WOFFSET                       0x0
+#define APBDMA_IRQ_MASK_CLR_0_CH1_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH1_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_CLR_0_CH1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH1_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_CLR_0_CH1_ENABLE                        _MK_ENUM_CONST(1)
+
+// Clears the Mask Register
+#define APBDMA_IRQ_MASK_CLR_0_CH0_SHIFT                 _MK_SHIFT_CONST(0)
+#define APBDMA_IRQ_MASK_CLR_0_CH0_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_CLR_0_CH0_SHIFT)
+#define APBDMA_IRQ_MASK_CLR_0_CH0_RANGE                 0:0
+#define APBDMA_IRQ_MASK_CLR_0_CH0_WOFFSET                       0x0
+#define APBDMA_IRQ_MASK_CLR_0_CH0_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH0_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_CLR_0_CH0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH0_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_CLR_0_CH0_ENABLE                        _MK_ENUM_CONST(1)
+
+
+// Register APBDMA_TRIG_REG_0  
+#define APBDMA_TRIG_REG_0                       _MK_ADDR_CONST(0x28)
+#define APBDMA_TRIG_REG_0_WORD_COUNT                    0x1
+#define APBDMA_TRIG_REG_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_RESET_MASK                    _MK_MASK_CONST(0x1fffffe)
+#define APBDMA_TRIG_REG_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_READ_MASK                     _MK_MASK_CONST(0x1fffffe)
+#define APBDMA_TRIG_REG_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+// EOC-15 Initiated DMA Request after transfer completion 
+#define APBDMA_TRIG_REG_0_APB_15_SHIFT                  _MK_SHIFT_CONST(24)
+#define APBDMA_TRIG_REG_0_APB_15_FIELD                  (_MK_MASK_CONST(0x1) << APBDMA_TRIG_REG_0_APB_15_SHIFT)
+#define APBDMA_TRIG_REG_0_APB_15_RANGE                  24:24
+#define APBDMA_TRIG_REG_0_APB_15_WOFFSET                        0x0
+#define APBDMA_TRIG_REG_0_APB_15_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_15_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMA_TRIG_REG_0_APB_15_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_15_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_15_NOT_ACTIVE                     _MK_ENUM_CONST(0)
+#define APBDMA_TRIG_REG_0_APB_15_ACTIVE                 _MK_ENUM_CONST(1)
+
+// EOC-14 Initiated DMA Request after transfer completion
+#define APBDMA_TRIG_REG_0_APB_14_SHIFT                  _MK_SHIFT_CONST(23)
+#define APBDMA_TRIG_REG_0_APB_14_FIELD                  (_MK_MASK_CONST(0x1) << APBDMA_TRIG_REG_0_APB_14_SHIFT)
+#define APBDMA_TRIG_REG_0_APB_14_RANGE                  23:23
+#define APBDMA_TRIG_REG_0_APB_14_WOFFSET                        0x0
+#define APBDMA_TRIG_REG_0_APB_14_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_14_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMA_TRIG_REG_0_APB_14_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_14_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_14_NOT_ACTIVE                     _MK_ENUM_CONST(0)
+#define APBDMA_TRIG_REG_0_APB_14_ACTIVE                 _MK_ENUM_CONST(1)
+
+// EOC-13 Initiated DMA Request after transfer completion
+#define APBDMA_TRIG_REG_0_APB_13_SHIFT                  _MK_SHIFT_CONST(22)
+#define APBDMA_TRIG_REG_0_APB_13_FIELD                  (_MK_MASK_CONST(0x1) << APBDMA_TRIG_REG_0_APB_13_SHIFT)
+#define APBDMA_TRIG_REG_0_APB_13_RANGE                  22:22
+#define APBDMA_TRIG_REG_0_APB_13_WOFFSET                        0x0
+#define APBDMA_TRIG_REG_0_APB_13_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_13_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMA_TRIG_REG_0_APB_13_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_13_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_13_NOT_ACTIVE                     _MK_ENUM_CONST(0)
+#define APBDMA_TRIG_REG_0_APB_13_ACTIVE                 _MK_ENUM_CONST(1)
+
+// EOC-12 Initiated DMA Request after transfer completion
+#define APBDMA_TRIG_REG_0_APB_12_SHIFT                  _MK_SHIFT_CONST(21)
+#define APBDMA_TRIG_REG_0_APB_12_FIELD                  (_MK_MASK_CONST(0x1) << APBDMA_TRIG_REG_0_APB_12_SHIFT)
+#define APBDMA_TRIG_REG_0_APB_12_RANGE                  21:21
+#define APBDMA_TRIG_REG_0_APB_12_WOFFSET                        0x0
+#define APBDMA_TRIG_REG_0_APB_12_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_12_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMA_TRIG_REG_0_APB_12_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_12_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_12_NOT_ACTIVE                     _MK_ENUM_CONST(0)
+#define APBDMA_TRIG_REG_0_APB_12_ACTIVE                 _MK_ENUM_CONST(1)
+
+// EOC-11 Initiated DMA Request after transfer completion
+#define APBDMA_TRIG_REG_0_APB_11_SHIFT                  _MK_SHIFT_CONST(20)
+#define APBDMA_TRIG_REG_0_APB_11_FIELD                  (_MK_MASK_CONST(0x1) << APBDMA_TRIG_REG_0_APB_11_SHIFT)
+#define APBDMA_TRIG_REG_0_APB_11_RANGE                  20:20
+#define APBDMA_TRIG_REG_0_APB_11_WOFFSET                        0x0
+#define APBDMA_TRIG_REG_0_APB_11_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_11_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMA_TRIG_REG_0_APB_11_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_11_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_11_NOT_ACTIVE                     _MK_ENUM_CONST(0)
+#define APBDMA_TRIG_REG_0_APB_11_ACTIVE                 _MK_ENUM_CONST(1)
+
+// EOC-10 Initiated DMA Request after transfer completion
+#define APBDMA_TRIG_REG_0_APB_10_SHIFT                  _MK_SHIFT_CONST(19)
+#define APBDMA_TRIG_REG_0_APB_10_FIELD                  (_MK_MASK_CONST(0x1) << APBDMA_TRIG_REG_0_APB_10_SHIFT)
+#define APBDMA_TRIG_REG_0_APB_10_RANGE                  19:19
+#define APBDMA_TRIG_REG_0_APB_10_WOFFSET                        0x0
+#define APBDMA_TRIG_REG_0_APB_10_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_10_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMA_TRIG_REG_0_APB_10_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_10_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_10_NOT_ACTIVE                     _MK_ENUM_CONST(0)
+#define APBDMA_TRIG_REG_0_APB_10_ACTIVE                 _MK_ENUM_CONST(1)
+
+// EOC-9 Initiated DMA Request after transfer completion
+#define APBDMA_TRIG_REG_0_APB_9_SHIFT                   _MK_SHIFT_CONST(18)
+#define APBDMA_TRIG_REG_0_APB_9_FIELD                   (_MK_MASK_CONST(0x1) << APBDMA_TRIG_REG_0_APB_9_SHIFT)
+#define APBDMA_TRIG_REG_0_APB_9_RANGE                   18:18
+#define APBDMA_TRIG_REG_0_APB_9_WOFFSET                 0x0
+#define APBDMA_TRIG_REG_0_APB_9_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_9_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMA_TRIG_REG_0_APB_9_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_9_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_9_NOT_ACTIVE                      _MK_ENUM_CONST(0)
+#define APBDMA_TRIG_REG_0_APB_9_ACTIVE                  _MK_ENUM_CONST(1)
+
+// EOC-8 Initiated DMA Request after transfer completion
+#define APBDMA_TRIG_REG_0_APB_8_SHIFT                   _MK_SHIFT_CONST(17)
+#define APBDMA_TRIG_REG_0_APB_8_FIELD                   (_MK_MASK_CONST(0x1) << APBDMA_TRIG_REG_0_APB_8_SHIFT)
+#define APBDMA_TRIG_REG_0_APB_8_RANGE                   17:17
+#define APBDMA_TRIG_REG_0_APB_8_WOFFSET                 0x0
+#define APBDMA_TRIG_REG_0_APB_8_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_8_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMA_TRIG_REG_0_APB_8_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_8_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_8_NOT_ACTIVE                      _MK_ENUM_CONST(0)
+#define APBDMA_TRIG_REG_0_APB_8_ACTIVE                  _MK_ENUM_CONST(1)
+
+// EOC-7 Initiated DMA Request after transfer completion
+#define APBDMA_TRIG_REG_0_APB_7_SHIFT                   _MK_SHIFT_CONST(16)
+#define APBDMA_TRIG_REG_0_APB_7_FIELD                   (_MK_MASK_CONST(0x1) << APBDMA_TRIG_REG_0_APB_7_SHIFT)
+#define APBDMA_TRIG_REG_0_APB_7_RANGE                   16:16
+#define APBDMA_TRIG_REG_0_APB_7_WOFFSET                 0x0
+#define APBDMA_TRIG_REG_0_APB_7_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_7_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMA_TRIG_REG_0_APB_7_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_7_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_7_NOT_ACTIVE                      _MK_ENUM_CONST(0)
+#define APBDMA_TRIG_REG_0_APB_7_ACTIVE                  _MK_ENUM_CONST(1)
+
+// EOC-6 Initiated DMA Request after transfer completion
+#define APBDMA_TRIG_REG_0_APB_6_SHIFT                   _MK_SHIFT_CONST(15)
+#define APBDMA_TRIG_REG_0_APB_6_FIELD                   (_MK_MASK_CONST(0x1) << APBDMA_TRIG_REG_0_APB_6_SHIFT)
+#define APBDMA_TRIG_REG_0_APB_6_RANGE                   15:15
+#define APBDMA_TRIG_REG_0_APB_6_WOFFSET                 0x0
+#define APBDMA_TRIG_REG_0_APB_6_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_6_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMA_TRIG_REG_0_APB_6_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_6_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_6_NOT_ACTIVE                      _MK_ENUM_CONST(0)
+#define APBDMA_TRIG_REG_0_APB_6_ACTIVE                  _MK_ENUM_CONST(1)
+
+// EOC-5 Initiated DMA Request after transfer completion
+#define APBDMA_TRIG_REG_0_APB_5_SHIFT                   _MK_SHIFT_CONST(14)
+#define APBDMA_TRIG_REG_0_APB_5_FIELD                   (_MK_MASK_CONST(0x1) << APBDMA_TRIG_REG_0_APB_5_SHIFT)
+#define APBDMA_TRIG_REG_0_APB_5_RANGE                   14:14
+#define APBDMA_TRIG_REG_0_APB_5_WOFFSET                 0x0
+#define APBDMA_TRIG_REG_0_APB_5_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_5_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMA_TRIG_REG_0_APB_5_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_5_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_5_NOT_ACTIVE                      _MK_ENUM_CONST(0)
+#define APBDMA_TRIG_REG_0_APB_5_ACTIVE                  _MK_ENUM_CONST(1)
+
+// EOC-4 Initiated DMA Request after transfer completion
+#define APBDMA_TRIG_REG_0_APB_4_SHIFT                   _MK_SHIFT_CONST(13)
+#define APBDMA_TRIG_REG_0_APB_4_FIELD                   (_MK_MASK_CONST(0x1) << APBDMA_TRIG_REG_0_APB_4_SHIFT)
+#define APBDMA_TRIG_REG_0_APB_4_RANGE                   13:13
+#define APBDMA_TRIG_REG_0_APB_4_WOFFSET                 0x0
+#define APBDMA_TRIG_REG_0_APB_4_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_4_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMA_TRIG_REG_0_APB_4_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_4_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_4_NOT_ACTIVE                      _MK_ENUM_CONST(0)
+#define APBDMA_TRIG_REG_0_APB_4_ACTIVE                  _MK_ENUM_CONST(1)
+
+// EOC-3 Initiated DMA Request after transfer completion
+#define APBDMA_TRIG_REG_0_APB_3_SHIFT                   _MK_SHIFT_CONST(12)
+#define APBDMA_TRIG_REG_0_APB_3_FIELD                   (_MK_MASK_CONST(0x1) << APBDMA_TRIG_REG_0_APB_3_SHIFT)
+#define APBDMA_TRIG_REG_0_APB_3_RANGE                   12:12
+#define APBDMA_TRIG_REG_0_APB_3_WOFFSET                 0x0
+#define APBDMA_TRIG_REG_0_APB_3_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_3_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMA_TRIG_REG_0_APB_3_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_3_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_3_NOT_ACTIVE                      _MK_ENUM_CONST(0)
+#define APBDMA_TRIG_REG_0_APB_3_ACTIVE                  _MK_ENUM_CONST(1)
+
+// EOC-2 Initiated DMA Request after transfer completion
+#define APBDMA_TRIG_REG_0_APB_2_SHIFT                   _MK_SHIFT_CONST(11)
+#define APBDMA_TRIG_REG_0_APB_2_FIELD                   (_MK_MASK_CONST(0x1) << APBDMA_TRIG_REG_0_APB_2_SHIFT)
+#define APBDMA_TRIG_REG_0_APB_2_RANGE                   11:11
+#define APBDMA_TRIG_REG_0_APB_2_WOFFSET                 0x0
+#define APBDMA_TRIG_REG_0_APB_2_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_2_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMA_TRIG_REG_0_APB_2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_2_NOT_ACTIVE                      _MK_ENUM_CONST(0)
+#define APBDMA_TRIG_REG_0_APB_2_ACTIVE                  _MK_ENUM_CONST(1)
+
+// EOC-1 Initiated DMA Request after transfer completion
+#define APBDMA_TRIG_REG_0_APB_1_SHIFT                   _MK_SHIFT_CONST(10)
+#define APBDMA_TRIG_REG_0_APB_1_FIELD                   (_MK_MASK_CONST(0x1) << APBDMA_TRIG_REG_0_APB_1_SHIFT)
+#define APBDMA_TRIG_REG_0_APB_1_RANGE                   10:10
+#define APBDMA_TRIG_REG_0_APB_1_WOFFSET                 0x0
+#define APBDMA_TRIG_REG_0_APB_1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMA_TRIG_REG_0_APB_1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_1_NOT_ACTIVE                      _MK_ENUM_CONST(0)
+#define APBDMA_TRIG_REG_0_APB_1_ACTIVE                  _MK_ENUM_CONST(1)
+
+// EOC-0 Initiated DMA Request after transfer completion
+#define APBDMA_TRIG_REG_0_APB_0_SHIFT                   _MK_SHIFT_CONST(9)
+#define APBDMA_TRIG_REG_0_APB_0_FIELD                   (_MK_MASK_CONST(0x1) << APBDMA_TRIG_REG_0_APB_0_SHIFT)
+#define APBDMA_TRIG_REG_0_APB_0_RANGE                   9:9
+#define APBDMA_TRIG_REG_0_APB_0_WOFFSET                 0x0
+#define APBDMA_TRIG_REG_0_APB_0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMA_TRIG_REG_0_APB_0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_0_NOT_ACTIVE                      _MK_ENUM_CONST(0)
+#define APBDMA_TRIG_REG_0_APB_0_ACTIVE                  _MK_ENUM_CONST(1)
+
+// Trigger select from Timer (Hardware initiated DMA request) 
+#define APBDMA_TRIG_REG_0_TMR2_SHIFT                    _MK_SHIFT_CONST(8)
+#define APBDMA_TRIG_REG_0_TMR2_FIELD                    (_MK_MASK_CONST(0x1) << APBDMA_TRIG_REG_0_TMR2_SHIFT)
+#define APBDMA_TRIG_REG_0_TMR2_RANGE                    8:8
+#define APBDMA_TRIG_REG_0_TMR2_WOFFSET                  0x0
+#define APBDMA_TRIG_REG_0_TMR2_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_TMR2_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMA_TRIG_REG_0_TMR2_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_TMR2_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_TMR2_NOT_ACTIVE                       _MK_ENUM_CONST(0)
+#define APBDMA_TRIG_REG_0_TMR2_ACTIVE                   _MK_ENUM_CONST(1)
+
+// Trigger select from Timer (Hardware initiated DMA request) 
+#define APBDMA_TRIG_REG_0_TMR1_SHIFT                    _MK_SHIFT_CONST(7)
+#define APBDMA_TRIG_REG_0_TMR1_FIELD                    (_MK_MASK_CONST(0x1) << APBDMA_TRIG_REG_0_TMR1_SHIFT)
+#define APBDMA_TRIG_REG_0_TMR1_RANGE                    7:7
+#define APBDMA_TRIG_REG_0_TMR1_WOFFSET                  0x0
+#define APBDMA_TRIG_REG_0_TMR1_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_TMR1_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMA_TRIG_REG_0_TMR1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_TMR1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_TMR1_NOT_ACTIVE                       _MK_ENUM_CONST(0)
+#define APBDMA_TRIG_REG_0_TMR1_ACTIVE                   _MK_ENUM_CONST(1)
+
+// XRQ.B (GPIOB) (Hardware initiated DMA request) 
+#define APBDMA_TRIG_REG_0_XRQ_B_SHIFT                   _MK_SHIFT_CONST(6)
+#define APBDMA_TRIG_REG_0_XRQ_B_FIELD                   (_MK_MASK_CONST(0x1) << APBDMA_TRIG_REG_0_XRQ_B_SHIFT)
+#define APBDMA_TRIG_REG_0_XRQ_B_RANGE                   6:6
+#define APBDMA_TRIG_REG_0_XRQ_B_WOFFSET                 0x0
+#define APBDMA_TRIG_REG_0_XRQ_B_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_XRQ_B_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMA_TRIG_REG_0_XRQ_B_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_XRQ_B_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_XRQ_B_NOT_ACTIVE                      _MK_ENUM_CONST(0)
+#define APBDMA_TRIG_REG_0_XRQ_B_ACTIVE                  _MK_ENUM_CONST(1)
+
+// XRQ.A (GPIOA) (Hardware initiated DMA request) 
+#define APBDMA_TRIG_REG_0_XRQ_A_SHIFT                   _MK_SHIFT_CONST(5)
+#define APBDMA_TRIG_REG_0_XRQ_A_FIELD                   (_MK_MASK_CONST(0x1) << APBDMA_TRIG_REG_0_XRQ_A_SHIFT)
+#define APBDMA_TRIG_REG_0_XRQ_A_RANGE                   5:5
+#define APBDMA_TRIG_REG_0_XRQ_A_WOFFSET                 0x0
+#define APBDMA_TRIG_REG_0_XRQ_A_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_XRQ_A_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMA_TRIG_REG_0_XRQ_A_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_XRQ_A_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_XRQ_A_NOT_ACTIVE                      _MK_ENUM_CONST(0)
+#define APBDMA_TRIG_REG_0_XRQ_A_ACTIVE                  _MK_ENUM_CONST(1)
+
+// Semaphore requests SW initiated DMA request
+#define APBDMA_TRIG_REG_0_SMP_27_SHIFT                  _MK_SHIFT_CONST(4)
+#define APBDMA_TRIG_REG_0_SMP_27_FIELD                  (_MK_MASK_CONST(0x1) << APBDMA_TRIG_REG_0_SMP_27_SHIFT)
+#define APBDMA_TRIG_REG_0_SMP_27_RANGE                  4:4
+#define APBDMA_TRIG_REG_0_SMP_27_WOFFSET                        0x0
+#define APBDMA_TRIG_REG_0_SMP_27_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_SMP_27_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMA_TRIG_REG_0_SMP_27_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_SMP_27_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_SMP_27_NOT_ACTIVE                     _MK_ENUM_CONST(0)
+#define APBDMA_TRIG_REG_0_SMP_27_ACTIVE                 _MK_ENUM_CONST(1)
+
+// Semaphore requests SW initiated DMA request 
+#define APBDMA_TRIG_REG_0_SMP_26_SHIFT                  _MK_SHIFT_CONST(3)
+#define APBDMA_TRIG_REG_0_SMP_26_FIELD                  (_MK_MASK_CONST(0x1) << APBDMA_TRIG_REG_0_SMP_26_SHIFT)
+#define APBDMA_TRIG_REG_0_SMP_26_RANGE                  3:3
+#define APBDMA_TRIG_REG_0_SMP_26_WOFFSET                        0x0
+#define APBDMA_TRIG_REG_0_SMP_26_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_SMP_26_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMA_TRIG_REG_0_SMP_26_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_SMP_26_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_SMP_26_NOT_ACTIVE                     _MK_ENUM_CONST(0)
+#define APBDMA_TRIG_REG_0_SMP_26_ACTIVE                 _MK_ENUM_CONST(1)
+
+// Semaphore requests SW initiated DMA request 
+#define APBDMA_TRIG_REG_0_SMP_25_SHIFT                  _MK_SHIFT_CONST(2)
+#define APBDMA_TRIG_REG_0_SMP_25_FIELD                  (_MK_MASK_CONST(0x1) << APBDMA_TRIG_REG_0_SMP_25_SHIFT)
+#define APBDMA_TRIG_REG_0_SMP_25_RANGE                  2:2
+#define APBDMA_TRIG_REG_0_SMP_25_WOFFSET                        0x0
+#define APBDMA_TRIG_REG_0_SMP_25_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_SMP_25_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMA_TRIG_REG_0_SMP_25_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_SMP_25_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_SMP_25_NOT_ACTIVE                     _MK_ENUM_CONST(0)
+#define APBDMA_TRIG_REG_0_SMP_25_ACTIVE                 _MK_ENUM_CONST(1)
+
+// Semaphore requests SW initiated DMA request 
+#define APBDMA_TRIG_REG_0_SMP_24_SHIFT                  _MK_SHIFT_CONST(1)
+#define APBDMA_TRIG_REG_0_SMP_24_FIELD                  (_MK_MASK_CONST(0x1) << APBDMA_TRIG_REG_0_SMP_24_SHIFT)
+#define APBDMA_TRIG_REG_0_SMP_24_RANGE                  1:1
+#define APBDMA_TRIG_REG_0_SMP_24_WOFFSET                        0x0
+#define APBDMA_TRIG_REG_0_SMP_24_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_SMP_24_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMA_TRIG_REG_0_SMP_24_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_SMP_24_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_SMP_24_NOT_ACTIVE                     _MK_ENUM_CONST(0)
+#define APBDMA_TRIG_REG_0_SMP_24_ACTIVE                 _MK_ENUM_CONST(1)
+
+
+//
+// REGISTER LIST
+//
+#define LIST_ARAPBDMA_REGS(_op_) \
+_op_(APBDMA_COMMAND_0) \
+_op_(APBDMA_STATUS_0) \
+_op_(APBDMA_REQUESTORS_TX_0) \
+_op_(APBDMA_REQUESTORS_RX_0) \
+_op_(APBDMA_CNTRL_REG_0) \
+_op_(APBDMA_IRQ_STA_CPU_0) \
+_op_(APBDMA_IRQ_STA_COP_0) \
+_op_(APBDMA_IRQ_MASK_0) \
+_op_(APBDMA_IRQ_MASK_SET_0) \
+_op_(APBDMA_IRQ_MASK_CLR_0) \
+_op_(APBDMA_TRIG_REG_0)
+
+
+//
+// ADDRESS SPACES
+//
+
+#define BASE_ADDRESS_APBDMA     0x00000000
+
+//
+// ARAPBDMA REGISTER BANKS
+//
+
+#define APBDMA0_FIRST_REG 0x0000 // APBDMA_COMMAND_0
+#define APBDMA0_LAST_REG 0x0028 // APBDMA_TRIG_REG_0
+
+#ifndef _MK_SHIFT_CONST
+  #define _MK_SHIFT_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_MASK_CONST
+  #define _MK_MASK_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_ENUM_CONST
+  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
+#endif
+#ifndef _MK_ADDR_CONST
+  #define _MK_ADDR_CONST(_constant_) _constant_
+#endif
+
+#endif // ifndef ___ARAPBDMA_H_INC_
diff --git a/arch/arm/mach-tegra/include/ap15/arapbdmachan.h b/arch/arm/mach-tegra/include/ap15/arapbdmachan.h
new file mode 100644
index 000000000000..b745faae4fa3
--- /dev/null
+++ b/arch/arm/mach-tegra/include/ap15/arapbdmachan.h
@@ -0,0 +1,6991 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+//
+// DO NOT EDIT - generated by simspec!
+//
+
+#ifndef ___ARAPBDMACHAN_H_INC_
+#define ___ARAPBDMACHAN_H_INC_
+
+// Register APBDMACHAN_CHANNEL_0_CSR_0  
+#define APBDMACHAN_CHANNEL_0_CSR_0                      _MK_ADDR_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_WORD_COUNT                   0x1
+#define APBDMACHAN_CHANNEL_0_CSR_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_RESET_MASK                   _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_0_CSR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_READ_MASK                    _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_0_CSR_0_WRITE_MASK                   _MK_MASK_CONST(0xfffffffc)
+// Enables DMA channel transfer 
+#define APBDMACHAN_CHANNEL_0_CSR_0_ENB_SHIFT                    _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_0_CSR_0_ENB_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_0_CSR_0_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_0_CSR_0_ENB_RANGE                    31:31
+#define APBDMACHAN_CHANNEL_0_CSR_0_ENB_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_0_CSR_0_ENB_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_ENB_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_0_CSR_0_ENB_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_ENB_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_ENB_DISABLE                  _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_ENB_ENABLE                   _MK_ENUM_CONST(1)
+
+// Interrupts when DMA Block Transfer Completes 
+#define APBDMACHAN_CHANNEL_0_CSR_0_IE_EOC_SHIFT                 _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_0_CSR_0_IE_EOC_FIELD                 (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_0_CSR_0_IE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_0_CSR_0_IE_EOC_RANGE                 30:30
+#define APBDMACHAN_CHANNEL_0_CSR_0_IE_EOC_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_0_CSR_0_IE_EOC_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_IE_EOC_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_0_CSR_0_IE_EOC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_IE_EOC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_IE_EOC_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_IE_EOC_ENABLE                        _MK_ENUM_CONST(1)
+
+// Holds this Processor until DMA Block Transfer Completes 
+#define APBDMACHAN_CHANNEL_0_CSR_0_HOLD_SHIFT                   _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_0_CSR_0_HOLD_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_0_CSR_0_HOLD_SHIFT)
+#define APBDMACHAN_CHANNEL_0_CSR_0_HOLD_RANGE                   29:29
+#define APBDMACHAN_CHANNEL_0_CSR_0_HOLD_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_0_CSR_0_HOLD_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_HOLD_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_0_CSR_0_HOLD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_HOLD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_HOLD_DISABLE                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_HOLD_ENABLE                  _MK_ENUM_CONST(1)
+
+//DMA Transfer Direction 1 = AHB read to APB write 0 = APB read to AHB write
+#define APBDMACHAN_CHANNEL_0_CSR_0_DIR_SHIFT                    _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_0_CSR_0_DIR_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_0_CSR_0_DIR_SHIFT)
+#define APBDMACHAN_CHANNEL_0_CSR_0_DIR_RANGE                    28:28
+#define APBDMACHAN_CHANNEL_0_CSR_0_DIR_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_0_CSR_0_DIR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_DIR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_0_CSR_0_DIR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_DIR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_DIR_AHB_WRITE                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_DIR_AHB_READ                 _MK_ENUM_CONST(1)
+
+// Run Once or Run Multiple Mode (Allow Retriggering of this Channel) 1 = Run for One Block Transfer 0 = Run for Multiple Block Transfer
+#define APBDMACHAN_CHANNEL_0_CSR_0_ONCE_SHIFT                   _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_0_CSR_0_ONCE_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_0_CSR_0_ONCE_SHIFT)
+#define APBDMACHAN_CHANNEL_0_CSR_0_ONCE_RANGE                   27:27
+#define APBDMACHAN_CHANNEL_0_CSR_0_ONCE_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_0_CSR_0_ONCE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_ONCE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_0_CSR_0_ONCE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_ONCE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_ONCE_MULTIPLE_BLOCK                  _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_ONCE_SINGLE_BLOCK                    _MK_ENUM_CONST(1)
+
+// Enable on Non-Zero Value
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_SHIFT                       _MK_SHIFT_CONST(22)
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_FIELD                       (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_RANGE                       26:22
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_NA1                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_SMP24                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_SMP25                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_SMP26                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_SMP27                       _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_XRQ_A                       _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_XRQ_B                       _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_TMR1                        _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_TMR2                        _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_APB_0                       _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_APB_1                       _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_APB_2                       _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_APB_3                       _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_APB_4                       _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_APB_5                       _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_APB_6                       _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_APB_7                       _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_APB_8                       _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_APB_9                       _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_APB_10                      _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_APB_11                      _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_APB_12                      _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_APB_13                      _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_APB_14                      _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_APB_15                      _MK_ENUM_CONST(24)
+
+// Flow Control Enable (Synchronize Burst Transfers) 1 = Link to DRQ source 0 = Independent of DRQ request
+#define APBDMACHAN_CHANNEL_0_CSR_0_FLOW_SHIFT                   _MK_SHIFT_CONST(21)
+#define APBDMACHAN_CHANNEL_0_CSR_0_FLOW_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_0_CSR_0_FLOW_SHIFT)
+#define APBDMACHAN_CHANNEL_0_CSR_0_FLOW_RANGE                   21:21
+#define APBDMACHAN_CHANNEL_0_CSR_0_FLOW_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_0_CSR_0_FLOW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_FLOW_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_0_CSR_0_FLOW_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_FLOW_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_FLOW_DISABLE                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_FLOW_ENABLE                  _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_SHIFT                        _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_FIELD                        (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_RANGE                        20:16
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_CNTR_REQ                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_I2S_2                        _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_I2S_1                        _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_SPD_I                        _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_UI_I                 _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_MIPI                 _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_I2S2_2                       _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_I2S2_1                       _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_UART_A                       _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_UART_B                       _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_UART_C                       _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_SPI                  _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_AC97                 _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_ACModem                      _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_SL4B                 _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_SL2B1                        _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_SL2B2                        _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_SL2B3                        _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_NA18                 _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_NA19                 _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_NA20                 _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_NA21                 _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_NA22                 _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_NA23                 _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_NA24                 _MK_ENUM_CONST(24)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_NA25                 _MK_ENUM_CONST(25)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_NA26                 _MK_ENUM_CONST(26)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_NA27                 _MK_ENUM_CONST(27)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_NA28                 _MK_ENUM_CONST(28)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_NA29                 _MK_ENUM_CONST(29)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_NA30                 _MK_ENUM_CONST(30)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_NA31                 _MK_ENUM_CONST(31)
+
+// Number of 32bit word cycles
+#define APBDMACHAN_CHANNEL_0_CSR_0_WCOUNT_SHIFT                 _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_0_CSR_0_WCOUNT_FIELD                 (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_0_CSR_0_WCOUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_0_CSR_0_WCOUNT_RANGE                 15:2
+#define APBDMACHAN_CHANNEL_0_CSR_0_WCOUNT_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_0_CSR_0_WCOUNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_WCOUNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_0_CSR_0_WCOUNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_WCOUNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_0_STA_0  
+#define APBDMACHAN_CHANNEL_0_STA_0                      _MK_ADDR_CONST(0x4)
+#define APBDMACHAN_CHANNEL_0_STA_0_WORD_COUNT                   0x1
+#define APBDMACHAN_CHANNEL_0_STA_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_STA_0_RESET_MASK                   _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_0_STA_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_STA_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_STA_0_READ_MASK                    _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_0_STA_0_WRITE_MASK                   _MK_MASK_CONST(0x40000000)
+// indicates whether DMA Channel Status active or not
+#define APBDMACHAN_CHANNEL_0_STA_0_BSY_SHIFT                    _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_0_STA_0_BSY_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_0_STA_0_BSY_SHIFT)
+#define APBDMACHAN_CHANNEL_0_STA_0_BSY_RANGE                    31:31
+#define APBDMACHAN_CHANNEL_0_STA_0_BSY_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_0_STA_0_BSY_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_STA_0_BSY_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_0_STA_0_BSY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_STA_0_BSY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_STA_0_BSY_WAIT                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_0_STA_0_BSY_ACTIVE                   _MK_ENUM_CONST(1)
+
+//  Write '1' to clear the flag                                    
+#define APBDMACHAN_CHANNEL_0_STA_0_ISE_EOC_SHIFT                        _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_0_STA_0_ISE_EOC_FIELD                        (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_0_STA_0_ISE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_0_STA_0_ISE_EOC_RANGE                        30:30
+#define APBDMACHAN_CHANNEL_0_STA_0_ISE_EOC_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_0_STA_0_ISE_EOC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_STA_0_ISE_EOC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_0_STA_0_ISE_EOC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_STA_0_ISE_EOC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_STA_0_ISE_EOC_NO_INTR                      _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_0_STA_0_ISE_EOC_INTR                 _MK_ENUM_CONST(1)
+
+// Holding Status of Processor
+#define APBDMACHAN_CHANNEL_0_STA_0_HALT_SHIFT                   _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_0_STA_0_HALT_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_0_STA_0_HALT_SHIFT)
+#define APBDMACHAN_CHANNEL_0_STA_0_HALT_RANGE                   29:29
+#define APBDMACHAN_CHANNEL_0_STA_0_HALT_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_0_STA_0_HALT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_STA_0_HALT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_0_STA_0_HALT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_STA_0_HALT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_STA_0_HALT_NO_HALT                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_0_STA_0_HALT_HALT                    _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_0_STA_0_PING_PONG_STA_SHIFT                  _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_0_STA_0_PING_PONG_STA_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_0_STA_0_PING_PONG_STA_SHIFT)
+#define APBDMACHAN_CHANNEL_0_STA_0_PING_PONG_STA_RANGE                  28:28
+#define APBDMACHAN_CHANNEL_0_STA_0_PING_PONG_STA_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_0_STA_0_PING_PONG_STA_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_STA_0_PING_PONG_STA_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_0_STA_0_PING_PONG_STA_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_STA_0_PING_PONG_STA_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_STA_0_PING_PONG_STA_PING_INTR_STA                  _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_0_STA_0_PING_PONG_STA_PONG_INTR_STA                  _MK_ENUM_CONST(1)
+
+// Current 32bit word cycles Flags set /cleared by HW
+#define APBDMACHAN_CHANNEL_0_STA_0_COUNT_SHIFT                  _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_0_STA_0_COUNT_FIELD                  (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_0_STA_0_COUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_0_STA_0_COUNT_RANGE                  15:2
+#define APBDMACHAN_CHANNEL_0_STA_0_COUNT_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_0_STA_0_COUNT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_STA_0_COUNT_DEFAULT_MASK                   _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_0_STA_0_COUNT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_STA_0_COUNT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Reserved address 8 [0x8] 
+
+// Reserved address 12 [0xc] 
+
+// Register APBDMACHAN_CHANNEL_0_AHB_PTR_0  
+#define APBDMACHAN_CHANNEL_0_AHB_PTR_0                  _MK_ADDR_CONST(0x10)
+#define APBDMACHAN_CHANNEL_0_AHB_PTR_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_0_AHB_PTR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_AHB_PTR_0_RESET_MASK                       _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_0_AHB_PTR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_AHB_PTR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_AHB_PTR_0_READ_MASK                        _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_0_AHB_PTR_0_WRITE_MASK                       _MK_MASK_CONST(0xfffffffc)
+// APB-DMA Starting Address for AHB Bus: SW writes to  modify
+#define APBDMACHAN_CHANNEL_0_AHB_PTR_0_AHB_BASE_SHIFT                   _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_0_AHB_PTR_0_AHB_BASE_FIELD                   (_MK_MASK_CONST(0x3fffffff) << APBDMACHAN_CHANNEL_0_AHB_PTR_0_AHB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_0_AHB_PTR_0_AHB_BASE_RANGE                   31:2
+#define APBDMACHAN_CHANNEL_0_AHB_PTR_0_AHB_BASE_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_0_AHB_PTR_0_AHB_BASE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_AHB_PTR_0_AHB_BASE_DEFAULT_MASK                    _MK_MASK_CONST(0x3fffffff)
+#define APBDMACHAN_CHANNEL_0_AHB_PTR_0_AHB_BASE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_AHB_PTR_0_AHB_BASE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_0_AHB_SEQ_0  
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0                  _MK_ADDR_CONST(0x14)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_RESET_VAL                        _MK_MASK_CONST(0x22000000)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_RESET_MASK                       _MK_MASK_CONST(0xff0f0000)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_READ_MASK                        _MK_MASK_CONST(0xff0f0000)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_WRITE_MASK                       _MK_MASK_CONST(0xff0f0000)
+// 0 = send interrupt to COP
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_INTR_ENB_SHIFT                   _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_INTR_ENB_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_0_AHB_SEQ_0_INTR_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_INTR_ENB_RANGE                   31:31
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_INTR_ENB_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_INTR_ENB_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_INTR_ENB_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_INTR_ENB_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_INTR_ENB_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_INTR_ENB_CPU                     _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_INTR_ENB_COP                     _MK_ENUM_CONST(0)
+
+// AHB Bus Width 0 = 8 bit Bus (RSVD) 1 = 16 bit Bus (RSVD) 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD)4 = 128 bit Bus (RSVD)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT                      _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_BUS_WIDTH_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_BUS_WIDTH_RANGE                      30:28
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_BUS_WIDTH_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT                    _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_8                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_16                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_32                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_64                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_128                      _MK_ENUM_CONST(4)
+
+// when enabled the data going  to AHB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }.
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT                      _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_DATA_SWAP_FIELD                      (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_DATA_SWAP_RANGE                      27:27
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_DATA_SWAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_DATA_SWAP_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_DATA_SWAP_ENABLE                     _MK_ENUM_CONST(1)
+
+// AHB Burst Size DMA Burst Length (encoded) 4 = 1 Word (1x32bits) 5 = 4 Words (4x32bits)else = 8 Words (8x32bits) default
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_BURST_SHIFT                  _MK_SHIFT_CONST(24)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_BURST_FIELD                  (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_BURST_SHIFT)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_BURST_RANGE                  26:24
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_BURST_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_BURST_DEFAULT                        _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_BURST_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_BURST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_BURST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_BURST_DMA_BURST_1WORDS                       _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_BURST_DMA_BURST_4WORDS                       _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_BURST_DMA_BURST_8WORDS                       _MK_ENUM_CONST(6)
+
+// 2X Double Buffering Mode (For Run-Multiple Mode with No Wrap Operations) 1 = Reload Base Address for 2X blocks (reload every other time) 0 = Reload Base Address for 1X blocks  (def) (reload each time)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_DBL_BUF_SHIFT                    _MK_SHIFT_CONST(19)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_DBL_BUF_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_0_AHB_SEQ_0_DBL_BUF_SHIFT)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_DBL_BUF_RANGE                    19:19
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_DBL_BUF_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_DBL_BUF_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_DBL_BUF_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_DBL_BUF_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_DBL_BUF_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_DBL_BUF_RELOAD_FOR_1X_BLOCKS                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_DBL_BUF_RELOAD_FOR_2X_BLOCKS                     _MK_ENUM_CONST(1)
+
+// AHB Address Wrap: AHB Address wrap-around window 0=No Wrap (default) 5=Wrap on 512 word window 1=Wrap on 32 word window 6=Wrap on 1024 word window 2=Wrap on 64 word window 7=Wrap on 2048 word window 3=Wrap on 128 word window 4=Wrap on 256 word window
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_WRAP_SHIFT                       _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_WRAP_FIELD                       (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_0_AHB_SEQ_0_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_WRAP_RANGE                       18:16
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_WRAP_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_WRAP_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_WRAP_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_WRAP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_WRAP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_WRAP_NO_WRAP                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_WRAP_WRAP_0N_32WORDS                     _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_WRAP_WRAP_ON_64WORDS                     _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_WRAP_WRAP_ON_128WORDS                    _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_WRAP_WRAP_ON_256WORDS                    _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_WRAP_WRAP_ON_512WORDS                    _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_WRAP_WRAP_ON_1024WORDS                   _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_WRAP_WRAP_ON_2048WORDS                   _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_0_APB_PTR_0  
+#define APBDMACHAN_CHANNEL_0_APB_PTR_0                  _MK_ADDR_CONST(0x18)
+#define APBDMACHAN_CHANNEL_0_APB_PTR_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_0_APB_PTR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_APB_PTR_0_RESET_MASK                       _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_0_APB_PTR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_APB_PTR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_APB_PTR_0_READ_MASK                        _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_0_APB_PTR_0_WRITE_MASK                       _MK_MASK_CONST(0xfffc)
+// APB-DMA Starting address for APB Bus:APB Base address:Upper 16 bits are fixed at 0x7000:XXXX
+#define APBDMACHAN_CHANNEL_0_APB_PTR_0_APB_BASE_SHIFT                   _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_0_APB_PTR_0_APB_BASE_FIELD                   (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_0_APB_PTR_0_APB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_0_APB_PTR_0_APB_BASE_RANGE                   15:2
+#define APBDMACHAN_CHANNEL_0_APB_PTR_0_APB_BASE_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_0_APB_PTR_0_APB_BASE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_APB_PTR_0_APB_BASE_DEFAULT_MASK                    _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_0_APB_PTR_0_APB_BASE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_APB_PTR_0_APB_BASE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_0_APB_SEQ_0  
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0                  _MK_ADDR_CONST(0x1c)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_RESET_VAL                        _MK_MASK_CONST(0x20010000)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_RESET_MASK                       _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_READ_MASK                        _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_WRITE_MASK                       _MK_MASK_CONST(0x78070000)
+// 0 = 8 bit Bus 1 = 16 bit Bus 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD) 4 = 128 bit BUS (RSVD)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_BUS_WIDTH_SHIFT                      _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_BUS_WIDTH_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_BUS_WIDTH_RANGE                      30:28
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_BUS_WIDTH_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT                    _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_8                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_16                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_32                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_64                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_128                      _MK_ENUM_CONST(4)
+
+//When enabled the data going  to APB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }.
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_DATA_SWAP_SHIFT                      _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_DATA_SWAP_FIELD                      (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_DATA_SWAP_RANGE                      27:27
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_DATA_SWAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_DATA_SWAP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_DATA_SWAP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_DATA_SWAP_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_DATA_SWAP_ENABLE                     _MK_ENUM_CONST(1)
+
+//APB Address Wrap-around Window 0 = No Wrap 1 = Wrap on 1 Word Window (def) 2 = Wrap on 2 Word Window 3 = Wrap on 4 Word Window 4 = Wrap on 8 Word Window 5 = Wrap on 16 Word Window 6 = Wrap on 32 Word Window 7 = Wrap on 64 Word Window (rsvd)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_ADDR_WRAP_SHIFT                      _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_ADDR_WRAP_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_ADDR_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_ADDR_WRAP_RANGE                      18:16
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_ADDR_WRAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_ADDR_WRAP_NO_WRAP                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_ADDR_WRAP_WRAP_0N_1WORDS                     _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_2WORDS                     _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_4WORDS                     _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_8WORDS                     _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_16WORDS                    _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_32WORDS                    _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_64WORDS                    _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_1_CSR_0  
+#define APBDMACHAN_CHANNEL_1_CSR_0                      _MK_ADDR_CONST(0x20)
+#define APBDMACHAN_CHANNEL_1_CSR_0_WORD_COUNT                   0x1
+#define APBDMACHAN_CHANNEL_1_CSR_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_RESET_MASK                   _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_1_CSR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_READ_MASK                    _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_1_CSR_0_WRITE_MASK                   _MK_MASK_CONST(0xfffffffc)
+// Enables DMA channel transfer 
+#define APBDMACHAN_CHANNEL_1_CSR_0_ENB_SHIFT                    _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_1_CSR_0_ENB_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_1_CSR_0_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_1_CSR_0_ENB_RANGE                    31:31
+#define APBDMACHAN_CHANNEL_1_CSR_0_ENB_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_1_CSR_0_ENB_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_ENB_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_1_CSR_0_ENB_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_ENB_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_ENB_DISABLE                  _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_ENB_ENABLE                   _MK_ENUM_CONST(1)
+
+// Interrupts when DMA Block Transfer Completes 
+#define APBDMACHAN_CHANNEL_1_CSR_0_IE_EOC_SHIFT                 _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_1_CSR_0_IE_EOC_FIELD                 (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_1_CSR_0_IE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_1_CSR_0_IE_EOC_RANGE                 30:30
+#define APBDMACHAN_CHANNEL_1_CSR_0_IE_EOC_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_1_CSR_0_IE_EOC_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_IE_EOC_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_1_CSR_0_IE_EOC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_IE_EOC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_IE_EOC_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_IE_EOC_ENABLE                        _MK_ENUM_CONST(1)
+
+// Holds this Processor until DMA Block Transfer Completes
+#define APBDMACHAN_CHANNEL_1_CSR_0_HOLD_SHIFT                   _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_1_CSR_0_HOLD_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_1_CSR_0_HOLD_SHIFT)
+#define APBDMACHAN_CHANNEL_1_CSR_0_HOLD_RANGE                   29:29
+#define APBDMACHAN_CHANNEL_1_CSR_0_HOLD_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_1_CSR_0_HOLD_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_HOLD_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_1_CSR_0_HOLD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_HOLD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_HOLD_DISABLE                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_HOLD_ENABLE                  _MK_ENUM_CONST(1)
+
+// DMA Transfer Direction 1 = AHB read to APB write 0 = APB read to AHB write
+#define APBDMACHAN_CHANNEL_1_CSR_0_DIR_SHIFT                    _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_1_CSR_0_DIR_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_1_CSR_0_DIR_SHIFT)
+#define APBDMACHAN_CHANNEL_1_CSR_0_DIR_RANGE                    28:28
+#define APBDMACHAN_CHANNEL_1_CSR_0_DIR_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_1_CSR_0_DIR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_DIR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_1_CSR_0_DIR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_DIR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_DIR_AHB_WRITE                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_DIR_AHB_READ                 _MK_ENUM_CONST(1)
+
+// Run Once or Run Multiple Mode (Allow Retriggering of this Channel) 1 = Run for One Block Transfer 0 = Run for Multiple Block Transfer
+#define APBDMACHAN_CHANNEL_1_CSR_0_ONCE_SHIFT                   _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_1_CSR_0_ONCE_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_1_CSR_0_ONCE_SHIFT)
+#define APBDMACHAN_CHANNEL_1_CSR_0_ONCE_RANGE                   27:27
+#define APBDMACHAN_CHANNEL_1_CSR_0_ONCE_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_1_CSR_0_ONCE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_ONCE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_1_CSR_0_ONCE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_ONCE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_ONCE_MULTIPLE_BLOCK                  _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_ONCE_SINGLE_BLOCK                    _MK_ENUM_CONST(1)
+
+// Enable on Non-Zero Value
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_SHIFT                       _MK_SHIFT_CONST(22)
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_FIELD                       (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_RANGE                       26:22
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_NA1                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_SMP24                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_SMP25                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_SMP26                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_SMP27                       _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_XRQ_A                       _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_XRQ_B                       _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_TMR1                        _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_TMR2                        _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_APB_0                       _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_APB_1                       _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_APB_2                       _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_APB_3                       _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_APB_4                       _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_APB_5                       _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_APB_6                       _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_APB_7                       _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_APB_8                       _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_APB_9                       _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_APB_10                      _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_APB_11                      _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_APB_12                      _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_APB_13                      _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_APB_14                      _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_APB_15                      _MK_ENUM_CONST(24)
+
+// Flow Control Enable (Synchronize Burst Transfers) 1 = Link to DRQ source 0 = Independent of DRQ request
+#define APBDMACHAN_CHANNEL_1_CSR_0_FLOW_SHIFT                   _MK_SHIFT_CONST(21)
+#define APBDMACHAN_CHANNEL_1_CSR_0_FLOW_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_1_CSR_0_FLOW_SHIFT)
+#define APBDMACHAN_CHANNEL_1_CSR_0_FLOW_RANGE                   21:21
+#define APBDMACHAN_CHANNEL_1_CSR_0_FLOW_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_1_CSR_0_FLOW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_FLOW_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_1_CSR_0_FLOW_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_FLOW_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_FLOW_DISABLE                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_FLOW_ENABLE                  _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_SHIFT                        _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_FIELD                        (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_RANGE                        20:16
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_CNTR_REQ                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_I2S_2                        _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_I2S_1                        _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_SPD_I                        _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_UI_I                 _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_MIPI                 _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_I2S2_2                       _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_I2S2_1                       _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_UART_A                       _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_UART_B                       _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_UART_C                       _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_SPI                  _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_AC97                 _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_ACModem                      _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_SL4B                 _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_SL2B1                        _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_SL2B2                        _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_SL2B3                        _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_NA18                 _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_NA19                 _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_NA20                 _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_NA21                 _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_NA22                 _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_NA23                 _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_NA24                 _MK_ENUM_CONST(24)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_NA25                 _MK_ENUM_CONST(25)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_NA26                 _MK_ENUM_CONST(26)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_NA27                 _MK_ENUM_CONST(27)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_NA28                 _MK_ENUM_CONST(28)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_NA29                 _MK_ENUM_CONST(29)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_NA30                 _MK_ENUM_CONST(30)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_NA31                 _MK_ENUM_CONST(31)
+
+// Number of 32bit word cycles
+#define APBDMACHAN_CHANNEL_1_CSR_0_WCOUNT_SHIFT                 _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_1_CSR_0_WCOUNT_FIELD                 (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_1_CSR_0_WCOUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_1_CSR_0_WCOUNT_RANGE                 15:2
+#define APBDMACHAN_CHANNEL_1_CSR_0_WCOUNT_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_1_CSR_0_WCOUNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_WCOUNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_1_CSR_0_WCOUNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_WCOUNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_1_STA_0  
+#define APBDMACHAN_CHANNEL_1_STA_0                      _MK_ADDR_CONST(0x24)
+#define APBDMACHAN_CHANNEL_1_STA_0_WORD_COUNT                   0x1
+#define APBDMACHAN_CHANNEL_1_STA_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_STA_0_RESET_MASK                   _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_1_STA_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_STA_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_STA_0_READ_MASK                    _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_1_STA_0_WRITE_MASK                   _MK_MASK_CONST(0x40000000)
+// indicates whether DMA Channel Status active or not
+#define APBDMACHAN_CHANNEL_1_STA_0_BSY_SHIFT                    _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_1_STA_0_BSY_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_1_STA_0_BSY_SHIFT)
+#define APBDMACHAN_CHANNEL_1_STA_0_BSY_RANGE                    31:31
+#define APBDMACHAN_CHANNEL_1_STA_0_BSY_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_1_STA_0_BSY_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_STA_0_BSY_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_1_STA_0_BSY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_STA_0_BSY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_STA_0_BSY_WAIT                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_1_STA_0_BSY_ACTIVE                   _MK_ENUM_CONST(1)
+
+//  Write '1' to clear the flag
+#define APBDMACHAN_CHANNEL_1_STA_0_ISE_EOC_SHIFT                        _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_1_STA_0_ISE_EOC_FIELD                        (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_1_STA_0_ISE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_1_STA_0_ISE_EOC_RANGE                        30:30
+#define APBDMACHAN_CHANNEL_1_STA_0_ISE_EOC_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_1_STA_0_ISE_EOC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_STA_0_ISE_EOC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_1_STA_0_ISE_EOC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_STA_0_ISE_EOC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_STA_0_ISE_EOC_NO_INTR                      _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_1_STA_0_ISE_EOC_INTR                 _MK_ENUM_CONST(1)
+
+// Holding Status of Processor
+#define APBDMACHAN_CHANNEL_1_STA_0_HALT_SHIFT                   _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_1_STA_0_HALT_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_1_STA_0_HALT_SHIFT)
+#define APBDMACHAN_CHANNEL_1_STA_0_HALT_RANGE                   29:29
+#define APBDMACHAN_CHANNEL_1_STA_0_HALT_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_1_STA_0_HALT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_STA_0_HALT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_1_STA_0_HALT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_STA_0_HALT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_STA_0_HALT_NO_HALT                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_1_STA_0_HALT_HALT                    _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_1_STA_0_PING_PONG_STA_SHIFT                  _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_1_STA_0_PING_PONG_STA_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_1_STA_0_PING_PONG_STA_SHIFT)
+#define APBDMACHAN_CHANNEL_1_STA_0_PING_PONG_STA_RANGE                  28:28
+#define APBDMACHAN_CHANNEL_1_STA_0_PING_PONG_STA_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_1_STA_0_PING_PONG_STA_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_STA_0_PING_PONG_STA_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_1_STA_0_PING_PONG_STA_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_STA_0_PING_PONG_STA_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_STA_0_PING_PONG_STA_PING_INTR_STA                  _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_1_STA_0_PING_PONG_STA_PONG_INTR_STA                  _MK_ENUM_CONST(1)
+
+// Current 32bit word cycles Flags set /cleared by HW
+#define APBDMACHAN_CHANNEL_1_STA_0_COUNT_SHIFT                  _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_1_STA_0_COUNT_FIELD                  (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_1_STA_0_COUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_1_STA_0_COUNT_RANGE                  15:2
+#define APBDMACHAN_CHANNEL_1_STA_0_COUNT_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_1_STA_0_COUNT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_STA_0_COUNT_DEFAULT_MASK                   _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_1_STA_0_COUNT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_STA_0_COUNT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Reserved address 40 [0x28] 
+
+// Reserved address 44 [0x2c] 
+
+// Register APBDMACHAN_CHANNEL_1_AHB_PTR_0  
+#define APBDMACHAN_CHANNEL_1_AHB_PTR_0                  _MK_ADDR_CONST(0x30)
+#define APBDMACHAN_CHANNEL_1_AHB_PTR_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_1_AHB_PTR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_AHB_PTR_0_RESET_MASK                       _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_1_AHB_PTR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_AHB_PTR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_AHB_PTR_0_READ_MASK                        _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_1_AHB_PTR_0_WRITE_MASK                       _MK_MASK_CONST(0xfffffffc)
+// APB-DMA Starting Address for AHB Bus: SW writes to  modify
+#define APBDMACHAN_CHANNEL_1_AHB_PTR_0_AHB_BASE_SHIFT                   _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_1_AHB_PTR_0_AHB_BASE_FIELD                   (_MK_MASK_CONST(0x3fffffff) << APBDMACHAN_CHANNEL_1_AHB_PTR_0_AHB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_1_AHB_PTR_0_AHB_BASE_RANGE                   31:2
+#define APBDMACHAN_CHANNEL_1_AHB_PTR_0_AHB_BASE_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_1_AHB_PTR_0_AHB_BASE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_AHB_PTR_0_AHB_BASE_DEFAULT_MASK                    _MK_MASK_CONST(0x3fffffff)
+#define APBDMACHAN_CHANNEL_1_AHB_PTR_0_AHB_BASE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_AHB_PTR_0_AHB_BASE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_1_AHB_SEQ_0  
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0                  _MK_ADDR_CONST(0x34)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_RESET_VAL                        _MK_MASK_CONST(0x22000000)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_RESET_MASK                       _MK_MASK_CONST(0xff0f0000)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_READ_MASK                        _MK_MASK_CONST(0xff0f0000)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_WRITE_MASK                       _MK_MASK_CONST(0xff0f0000)
+// 0 = send interrupt to COP
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_INTR_ENB_SHIFT                   _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_INTR_ENB_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_1_AHB_SEQ_0_INTR_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_INTR_ENB_RANGE                   31:31
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_INTR_ENB_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_INTR_ENB_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_INTR_ENB_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_INTR_ENB_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_INTR_ENB_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_INTR_ENB_CPU                     _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_INTR_ENB_COP                     _MK_ENUM_CONST(0)
+
+// AHB Bus Width 0 = 8 bit Bus (RSVD) 1 = 16 bit Bus (RSVD) 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD)4 = 128 bit Bus (RSVD)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT                      _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_BUS_WIDTH_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_BUS_WIDTH_RANGE                      30:28
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_BUS_WIDTH_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT                    _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_8                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_16                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_32                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_64                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_128                      _MK_ENUM_CONST(4)
+
+//when enabled the data going  to AHB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT                      _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_DATA_SWAP_FIELD                      (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_DATA_SWAP_RANGE                      27:27
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_DATA_SWAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_DATA_SWAP_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_DATA_SWAP_ENABLE                     _MK_ENUM_CONST(1)
+
+// AHB Burst Size DMA Burst Length (encoded) 4 = 1 Word (1x32bits) 5 = 4 Words (4x32bits)else = 8 Words (8x32bits) default
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_BURST_SHIFT                  _MK_SHIFT_CONST(24)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_BURST_FIELD                  (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_BURST_SHIFT)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_BURST_RANGE                  26:24
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_BURST_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_BURST_DEFAULT                        _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_BURST_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_BURST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_BURST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_BURST_DMA_BURST_1WORDS                       _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_BURST_DMA_BURST_4WORDS                       _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_BURST_DMA_BURST_8WORDS                       _MK_ENUM_CONST(6)
+
+// 2X Double Buffering Mode (For Run-Multiple Mode with No Wrap Operations) 1 = Reload Base Address for 2X blocks (reload every other time) 0 = Reload Base Address for 1X blocks  (def) (reload each time)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_DBL_BUF_SHIFT                    _MK_SHIFT_CONST(19)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_DBL_BUF_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_1_AHB_SEQ_0_DBL_BUF_SHIFT)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_DBL_BUF_RANGE                    19:19
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_DBL_BUF_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_DBL_BUF_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_DBL_BUF_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_DBL_BUF_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_DBL_BUF_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_DBL_BUF_RELOAD_FOR_1X_BLOCKS                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_DBL_BUF_RELOAD_FOR_2X_BLOCKS                     _MK_ENUM_CONST(1)
+
+// AHB Address Wrap: AHB Address wrap-around window 0=No Wrap (default) 5=Wrap on 512 word window 1=Wrap on 32 word window 6=Wrap on 1024 word window 2=Wrap on 64 word window 7=Wrap on 2048 word window 3=Wrap on 128 word window 4=Wrap on 256 word window
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_WRAP_SHIFT                       _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_WRAP_FIELD                       (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_1_AHB_SEQ_0_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_WRAP_RANGE                       18:16
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_WRAP_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_WRAP_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_WRAP_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_WRAP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_WRAP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_WRAP_NO_WRAP                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_WRAP_WRAP_0N_32WORDS                     _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_WRAP_WRAP_ON_64WORDS                     _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_WRAP_WRAP_ON_128WORDS                    _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_WRAP_WRAP_ON_256WORDS                    _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_WRAP_WRAP_ON_512WORDS                    _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_WRAP_WRAP_ON_1024WORDS                   _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_WRAP_WRAP_ON_2048WORDS                   _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_1_APB_PTR_0  
+#define APBDMACHAN_CHANNEL_1_APB_PTR_0                  _MK_ADDR_CONST(0x38)
+#define APBDMACHAN_CHANNEL_1_APB_PTR_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_1_APB_PTR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_APB_PTR_0_RESET_MASK                       _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_1_APB_PTR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_APB_PTR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_APB_PTR_0_READ_MASK                        _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_1_APB_PTR_0_WRITE_MASK                       _MK_MASK_CONST(0xfffc)
+// APB-DMA Starting address for APB Bus: APB Base address: Upper 16 bits are fixed at 0x7000:XXXX
+#define APBDMACHAN_CHANNEL_1_APB_PTR_0_APB_BASE_SHIFT                   _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_1_APB_PTR_0_APB_BASE_FIELD                   (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_1_APB_PTR_0_APB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_1_APB_PTR_0_APB_BASE_RANGE                   15:2
+#define APBDMACHAN_CHANNEL_1_APB_PTR_0_APB_BASE_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_1_APB_PTR_0_APB_BASE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_APB_PTR_0_APB_BASE_DEFAULT_MASK                    _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_1_APB_PTR_0_APB_BASE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_APB_PTR_0_APB_BASE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_1_APB_SEQ_0  
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0                  _MK_ADDR_CONST(0x3c)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_RESET_VAL                        _MK_MASK_CONST(0x20010000)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_RESET_MASK                       _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_READ_MASK                        _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_WRITE_MASK                       _MK_MASK_CONST(0x78070000)
+// 0 = 8 bit Bus 1 = 16 bit Bus 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD) 4 = 128 bit BUS (RSVD)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_BUS_WIDTH_SHIFT                      _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_BUS_WIDTH_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_BUS_WIDTH_RANGE                      30:28
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_BUS_WIDTH_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT                    _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_8                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_16                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_32                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_64                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_128                      _MK_ENUM_CONST(4)
+
+//when enabled the data going  to APB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_DATA_SWAP_SHIFT                      _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_DATA_SWAP_FIELD                      (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_DATA_SWAP_RANGE                      27:27
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_DATA_SWAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_DATA_SWAP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_DATA_SWAP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_DATA_SWAP_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_DATA_SWAP_ENABLE                     _MK_ENUM_CONST(1)
+
+//APB Address Wrap-around Window 0 = No Wrap 1 = Wrap on 1 Word Window (def) 2 = Wrap on 2 Word Window 3 = Wrap on 4 Word Window 4 = Wrap on 8 Word Window 5 = Wrap on 16 Word Window 6 = Wrap on 32 Word Window 7 = Wrap on 64 Word Window (rsvd)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_ADDR_WRAP_SHIFT                      _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_ADDR_WRAP_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_ADDR_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_ADDR_WRAP_RANGE                      18:16
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_ADDR_WRAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_ADDR_WRAP_NO_WRAP                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_ADDR_WRAP_WRAP_0N_1WORDS                     _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_2WORDS                     _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_4WORDS                     _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_8WORDS                     _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_16WORDS                    _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_32WORDS                    _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_64WORDS                    _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_2_CSR_0  
+#define APBDMACHAN_CHANNEL_2_CSR_0                      _MK_ADDR_CONST(0x40)
+#define APBDMACHAN_CHANNEL_2_CSR_0_WORD_COUNT                   0x1
+#define APBDMACHAN_CHANNEL_2_CSR_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_RESET_MASK                   _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_2_CSR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_READ_MASK                    _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_2_CSR_0_WRITE_MASK                   _MK_MASK_CONST(0xfffffffc)
+// Enables DMA channel transfer 
+#define APBDMACHAN_CHANNEL_2_CSR_0_ENB_SHIFT                    _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_2_CSR_0_ENB_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_2_CSR_0_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_2_CSR_0_ENB_RANGE                    31:31
+#define APBDMACHAN_CHANNEL_2_CSR_0_ENB_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_2_CSR_0_ENB_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_ENB_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_2_CSR_0_ENB_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_ENB_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_ENB_DISABLE                  _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_ENB_ENABLE                   _MK_ENUM_CONST(1)
+
+// Interrupts when DMA Block Transfer Completes 
+#define APBDMACHAN_CHANNEL_2_CSR_0_IE_EOC_SHIFT                 _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_2_CSR_0_IE_EOC_FIELD                 (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_2_CSR_0_IE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_2_CSR_0_IE_EOC_RANGE                 30:30
+#define APBDMACHAN_CHANNEL_2_CSR_0_IE_EOC_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_2_CSR_0_IE_EOC_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_IE_EOC_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_2_CSR_0_IE_EOC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_IE_EOC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_IE_EOC_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_IE_EOC_ENABLE                        _MK_ENUM_CONST(1)
+
+// Holds this Processor until DMA Block Transfer Completes 
+#define APBDMACHAN_CHANNEL_2_CSR_0_HOLD_SHIFT                   _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_2_CSR_0_HOLD_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_2_CSR_0_HOLD_SHIFT)
+#define APBDMACHAN_CHANNEL_2_CSR_0_HOLD_RANGE                   29:29
+#define APBDMACHAN_CHANNEL_2_CSR_0_HOLD_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_2_CSR_0_HOLD_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_HOLD_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_2_CSR_0_HOLD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_HOLD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_HOLD_DISABLE                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_HOLD_ENABLE                  _MK_ENUM_CONST(1)
+
+// DMA Transfer Direction 1 = AHB read to APB write 0 = APB read to AHB write
+#define APBDMACHAN_CHANNEL_2_CSR_0_DIR_SHIFT                    _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_2_CSR_0_DIR_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_2_CSR_0_DIR_SHIFT)
+#define APBDMACHAN_CHANNEL_2_CSR_0_DIR_RANGE                    28:28
+#define APBDMACHAN_CHANNEL_2_CSR_0_DIR_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_2_CSR_0_DIR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_DIR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_2_CSR_0_DIR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_DIR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_DIR_AHB_WRITE                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_DIR_AHB_READ                 _MK_ENUM_CONST(1)
+
+// Run Once or Run Multiple Mode (Allow Retriggering of this Channel) 1 = Run for One Block Transfer 0 = Run for Multiple Block Transfer
+#define APBDMACHAN_CHANNEL_2_CSR_0_ONCE_SHIFT                   _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_2_CSR_0_ONCE_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_2_CSR_0_ONCE_SHIFT)
+#define APBDMACHAN_CHANNEL_2_CSR_0_ONCE_RANGE                   27:27
+#define APBDMACHAN_CHANNEL_2_CSR_0_ONCE_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_2_CSR_0_ONCE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_ONCE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_2_CSR_0_ONCE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_ONCE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_ONCE_MULTIPLE_BLOCK                  _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_ONCE_SINGLE_BLOCK                    _MK_ENUM_CONST(1)
+
+// Enable on Non-Zero Value
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_SHIFT                       _MK_SHIFT_CONST(22)
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_FIELD                       (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_RANGE                       26:22
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_NA1                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_SMP24                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_SMP25                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_SMP26                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_SMP27                       _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_XRQ_A                       _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_XRQ_B                       _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_TMR1                        _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_TMR2                        _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_APB_0                       _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_APB_1                       _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_APB_2                       _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_APB_3                       _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_APB_4                       _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_APB_5                       _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_APB_6                       _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_APB_7                       _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_APB_8                       _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_APB_9                       _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_APB_10                      _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_APB_11                      _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_APB_12                      _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_APB_13                      _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_APB_14                      _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_APB_15                      _MK_ENUM_CONST(24)
+
+// Flow Control Enable (Synchronize Burst Transfers) 1 = Link to DRQ source 0 = Independent of DRQ request
+#define APBDMACHAN_CHANNEL_2_CSR_0_FLOW_SHIFT                   _MK_SHIFT_CONST(21)
+#define APBDMACHAN_CHANNEL_2_CSR_0_FLOW_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_2_CSR_0_FLOW_SHIFT)
+#define APBDMACHAN_CHANNEL_2_CSR_0_FLOW_RANGE                   21:21
+#define APBDMACHAN_CHANNEL_2_CSR_0_FLOW_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_2_CSR_0_FLOW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_FLOW_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_2_CSR_0_FLOW_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_FLOW_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_FLOW_DISABLE                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_FLOW_ENABLE                  _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_SHIFT                        _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_FIELD                        (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_RANGE                        20:16
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_CNTR_REQ                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_I2S_2                        _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_I2S_1                        _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_SPD_I                        _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_UI_I                 _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_MIPI                 _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_I2S2_2                       _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_I2S2_1                       _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_UART_A                       _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_UART_B                       _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_UART_C                       _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_SPI                  _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_AC97                 _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_ACModem                      _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_SL4B                 _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_SL2B1                        _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_SL2B2                        _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_SL2B3                        _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_NA18                 _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_NA19                 _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_NA20                 _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_NA21                 _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_NA22                 _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_NA23                 _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_NA24                 _MK_ENUM_CONST(24)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_NA25                 _MK_ENUM_CONST(25)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_NA26                 _MK_ENUM_CONST(26)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_NA27                 _MK_ENUM_CONST(27)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_NA28                 _MK_ENUM_CONST(28)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_NA29                 _MK_ENUM_CONST(29)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_NA30                 _MK_ENUM_CONST(30)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_NA31                 _MK_ENUM_CONST(31)
+
+// Number of 32bit word cycles
+#define APBDMACHAN_CHANNEL_2_CSR_0_WCOUNT_SHIFT                 _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_2_CSR_0_WCOUNT_FIELD                 (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_2_CSR_0_WCOUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_2_CSR_0_WCOUNT_RANGE                 15:2
+#define APBDMACHAN_CHANNEL_2_CSR_0_WCOUNT_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_2_CSR_0_WCOUNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_WCOUNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_2_CSR_0_WCOUNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_WCOUNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_2_STA_0  
+#define APBDMACHAN_CHANNEL_2_STA_0                      _MK_ADDR_CONST(0x44)
+#define APBDMACHAN_CHANNEL_2_STA_0_WORD_COUNT                   0x1
+#define APBDMACHAN_CHANNEL_2_STA_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_STA_0_RESET_MASK                   _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_2_STA_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_STA_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_STA_0_READ_MASK                    _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_2_STA_0_WRITE_MASK                   _MK_MASK_CONST(0x40000000)
+// indicates whether DMA Channel Status active or not
+#define APBDMACHAN_CHANNEL_2_STA_0_BSY_SHIFT                    _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_2_STA_0_BSY_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_2_STA_0_BSY_SHIFT)
+#define APBDMACHAN_CHANNEL_2_STA_0_BSY_RANGE                    31:31
+#define APBDMACHAN_CHANNEL_2_STA_0_BSY_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_2_STA_0_BSY_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_STA_0_BSY_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_2_STA_0_BSY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_STA_0_BSY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_STA_0_BSY_WAIT                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_2_STA_0_BSY_ACTIVE                   _MK_ENUM_CONST(1)
+
+//  Write '1' to clear the flag
+#define APBDMACHAN_CHANNEL_2_STA_0_ISE_EOC_SHIFT                        _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_2_STA_0_ISE_EOC_FIELD                        (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_2_STA_0_ISE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_2_STA_0_ISE_EOC_RANGE                        30:30
+#define APBDMACHAN_CHANNEL_2_STA_0_ISE_EOC_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_2_STA_0_ISE_EOC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_STA_0_ISE_EOC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_2_STA_0_ISE_EOC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_STA_0_ISE_EOC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_STA_0_ISE_EOC_NO_INTR                      _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_2_STA_0_ISE_EOC_INTR                 _MK_ENUM_CONST(1)
+
+// Holding Status of Processor 
+#define APBDMACHAN_CHANNEL_2_STA_0_HALT_SHIFT                   _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_2_STA_0_HALT_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_2_STA_0_HALT_SHIFT)
+#define APBDMACHAN_CHANNEL_2_STA_0_HALT_RANGE                   29:29
+#define APBDMACHAN_CHANNEL_2_STA_0_HALT_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_2_STA_0_HALT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_STA_0_HALT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_2_STA_0_HALT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_STA_0_HALT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_STA_0_HALT_NO_HALT                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_2_STA_0_HALT_HALT                    _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_2_STA_0_PING_PONG_STA_SHIFT                  _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_2_STA_0_PING_PONG_STA_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_2_STA_0_PING_PONG_STA_SHIFT)
+#define APBDMACHAN_CHANNEL_2_STA_0_PING_PONG_STA_RANGE                  28:28
+#define APBDMACHAN_CHANNEL_2_STA_0_PING_PONG_STA_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_2_STA_0_PING_PONG_STA_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_STA_0_PING_PONG_STA_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_2_STA_0_PING_PONG_STA_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_STA_0_PING_PONG_STA_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_STA_0_PING_PONG_STA_PING_INTR_STA                  _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_2_STA_0_PING_PONG_STA_PONG_INTR_STA                  _MK_ENUM_CONST(1)
+
+// Current 32bit word cycles Flags set /cleared by HW
+#define APBDMACHAN_CHANNEL_2_STA_0_COUNT_SHIFT                  _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_2_STA_0_COUNT_FIELD                  (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_2_STA_0_COUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_2_STA_0_COUNT_RANGE                  15:2
+#define APBDMACHAN_CHANNEL_2_STA_0_COUNT_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_2_STA_0_COUNT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_STA_0_COUNT_DEFAULT_MASK                   _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_2_STA_0_COUNT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_STA_0_COUNT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Reserved address 72 [0x48] 
+
+// Reserved address 76 [0x4c] 
+
+// Register APBDMACHAN_CHANNEL_2_AHB_PTR_0  
+#define APBDMACHAN_CHANNEL_2_AHB_PTR_0                  _MK_ADDR_CONST(0x50)
+#define APBDMACHAN_CHANNEL_2_AHB_PTR_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_2_AHB_PTR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_AHB_PTR_0_RESET_MASK                       _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_2_AHB_PTR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_AHB_PTR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_AHB_PTR_0_READ_MASK                        _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_2_AHB_PTR_0_WRITE_MASK                       _MK_MASK_CONST(0xfffffffc)
+// APB-DMA Starting Address for AHB Bus: SW writes to  modify
+#define APBDMACHAN_CHANNEL_2_AHB_PTR_0_AHB_BASE_SHIFT                   _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_2_AHB_PTR_0_AHB_BASE_FIELD                   (_MK_MASK_CONST(0x3fffffff) << APBDMACHAN_CHANNEL_2_AHB_PTR_0_AHB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_2_AHB_PTR_0_AHB_BASE_RANGE                   31:2
+#define APBDMACHAN_CHANNEL_2_AHB_PTR_0_AHB_BASE_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_2_AHB_PTR_0_AHB_BASE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_AHB_PTR_0_AHB_BASE_DEFAULT_MASK                    _MK_MASK_CONST(0x3fffffff)
+#define APBDMACHAN_CHANNEL_2_AHB_PTR_0_AHB_BASE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_AHB_PTR_0_AHB_BASE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_2_AHB_SEQ_0  
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0                  _MK_ADDR_CONST(0x54)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_RESET_VAL                        _MK_MASK_CONST(0x22000000)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_RESET_MASK                       _MK_MASK_CONST(0xff0f0000)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_READ_MASK                        _MK_MASK_CONST(0xff0f0000)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_WRITE_MASK                       _MK_MASK_CONST(0xff0f0000)
+// 0 = send interrupt to COP
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_INTR_ENB_SHIFT                   _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_INTR_ENB_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_2_AHB_SEQ_0_INTR_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_INTR_ENB_RANGE                   31:31
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_INTR_ENB_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_INTR_ENB_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_INTR_ENB_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_INTR_ENB_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_INTR_ENB_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_INTR_ENB_CPU                     _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_INTR_ENB_COP                     _MK_ENUM_CONST(0)
+
+// AHB Bus Width 0 = 8 bit Bus (RSVD) 1 = 16 bit Bus (RSVD) 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD)4 = 128 bit Bus (RSVD)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT                      _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_BUS_WIDTH_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_BUS_WIDTH_RANGE                      30:28
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_BUS_WIDTH_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT                    _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_8                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_16                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_32                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_64                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_128                      _MK_ENUM_CONST(4)
+
+// when enabled the data going  to AHB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT                      _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_DATA_SWAP_FIELD                      (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_DATA_SWAP_RANGE                      27:27
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_DATA_SWAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_DATA_SWAP_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_DATA_SWAP_ENABLE                     _MK_ENUM_CONST(1)
+
+// AHB Burst Size DMA Burst Length (encoded) 4 = 1 Word (1x32bits) 5 = 4 Words (4x32bits)else = 8 Words (8x32bits) default
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_BURST_SHIFT                  _MK_SHIFT_CONST(24)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_BURST_FIELD                  (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_BURST_SHIFT)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_BURST_RANGE                  26:24
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_BURST_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_BURST_DEFAULT                        _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_BURST_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_BURST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_BURST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_BURST_DMA_BURST_1WORDS                       _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_BURST_DMA_BURST_4WORDS                       _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_BURST_DMA_BURST_8WORDS                       _MK_ENUM_CONST(6)
+
+// 2X Double Buffering Mode (For Run-Multiple Mode with No Wrap Operations) 1 = Reload Base Address for 2X blocks (reload every other time) 0 = Reload Base Address for 1X blocks  (def) (reload each time)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_DBL_BUF_SHIFT                    _MK_SHIFT_CONST(19)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_DBL_BUF_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_2_AHB_SEQ_0_DBL_BUF_SHIFT)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_DBL_BUF_RANGE                    19:19
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_DBL_BUF_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_DBL_BUF_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_DBL_BUF_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_DBL_BUF_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_DBL_BUF_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_DBL_BUF_RELOAD_FOR_1X_BLOCKS                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_DBL_BUF_RELOAD_FOR_2X_BLOCKS                     _MK_ENUM_CONST(1)
+
+// AHB Address Wrap: AHB Address wrap-around window 0=No Wrap (default) 5=Wrap on 512 word window 1=Wrap on 32 word window 6=Wrap on 1024 word window 2=Wrap on 64 word window 7=Wrap on 2048 word window 3=Wrap on 128 word window 4=Wrap on 256 word window
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_WRAP_SHIFT                       _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_WRAP_FIELD                       (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_2_AHB_SEQ_0_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_WRAP_RANGE                       18:16
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_WRAP_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_WRAP_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_WRAP_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_WRAP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_WRAP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_WRAP_NO_WRAP                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_WRAP_WRAP_0N_32WORDS                     _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_WRAP_WRAP_ON_64WORDS                     _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_WRAP_WRAP_ON_128WORDS                    _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_WRAP_WRAP_ON_256WORDS                    _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_WRAP_WRAP_ON_512WORDS                    _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_WRAP_WRAP_ON_1024WORDS                   _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_WRAP_WRAP_ON_2048WORDS                   _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_2_APB_PTR_0  
+#define APBDMACHAN_CHANNEL_2_APB_PTR_0                  _MK_ADDR_CONST(0x58)
+#define APBDMACHAN_CHANNEL_2_APB_PTR_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_2_APB_PTR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_APB_PTR_0_RESET_MASK                       _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_2_APB_PTR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_APB_PTR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_APB_PTR_0_READ_MASK                        _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_2_APB_PTR_0_WRITE_MASK                       _MK_MASK_CONST(0xfffc)
+// APB-DMA Starting address for APB Bus: APB Base  address: Upper 16 bits are fixed at 0x7000:XXXX
+#define APBDMACHAN_CHANNEL_2_APB_PTR_0_APB_BASE_SHIFT                   _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_2_APB_PTR_0_APB_BASE_FIELD                   (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_2_APB_PTR_0_APB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_2_APB_PTR_0_APB_BASE_RANGE                   15:2
+#define APBDMACHAN_CHANNEL_2_APB_PTR_0_APB_BASE_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_2_APB_PTR_0_APB_BASE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_APB_PTR_0_APB_BASE_DEFAULT_MASK                    _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_2_APB_PTR_0_APB_BASE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_APB_PTR_0_APB_BASE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_2_APB_SEQ_0  
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0                  _MK_ADDR_CONST(0x5c)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_RESET_VAL                        _MK_MASK_CONST(0x20010000)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_RESET_MASK                       _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_READ_MASK                        _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_WRITE_MASK                       _MK_MASK_CONST(0x78070000)
+// 0 = 8 bit Bus 1 = 16 bit Bus 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD) 4 = 128 bit BUS (RSVD)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_BUS_WIDTH_SHIFT                      _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_BUS_WIDTH_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_BUS_WIDTH_RANGE                      30:28
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_BUS_WIDTH_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT                    _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_8                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_16                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_32                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_64                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_128                      _MK_ENUM_CONST(4)
+
+// when enabled the data going  to APB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_DATA_SWAP_SHIFT                      _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_DATA_SWAP_FIELD                      (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_DATA_SWAP_RANGE                      27:27
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_DATA_SWAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_DATA_SWAP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_DATA_SWAP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_DATA_SWAP_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_DATA_SWAP_ENABLE                     _MK_ENUM_CONST(1)
+
+//APB Address Wrap-around Window 0 = No Wrap 1 = Wrap on 1 Word Window (def) 2 = Wrap on 2 Word Window 3 = Wrap on 4 Word Window 4 = Wrap on 8 Word Window 5 = Wrap on 16 Word Window 6 = Wrap on 32 Word Window 7 = Wrap on 64 Word Window (rsvd)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_ADDR_WRAP_SHIFT                      _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_ADDR_WRAP_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_ADDR_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_ADDR_WRAP_RANGE                      18:16
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_ADDR_WRAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_ADDR_WRAP_NO_WRAP                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_ADDR_WRAP_WRAP_0N_1WORDS                     _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_2WORDS                     _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_4WORDS                     _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_8WORDS                     _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_16WORDS                    _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_32WORDS                    _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_64WORDS                    _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_3_CSR_0  
+#define APBDMACHAN_CHANNEL_3_CSR_0                      _MK_ADDR_CONST(0x60)
+#define APBDMACHAN_CHANNEL_3_CSR_0_WORD_COUNT                   0x1
+#define APBDMACHAN_CHANNEL_3_CSR_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_RESET_MASK                   _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_3_CSR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_READ_MASK                    _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_3_CSR_0_WRITE_MASK                   _MK_MASK_CONST(0xfffffffc)
+// Enables DMA channel transfer 
+#define APBDMACHAN_CHANNEL_3_CSR_0_ENB_SHIFT                    _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_3_CSR_0_ENB_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_3_CSR_0_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_3_CSR_0_ENB_RANGE                    31:31
+#define APBDMACHAN_CHANNEL_3_CSR_0_ENB_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_3_CSR_0_ENB_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_ENB_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_3_CSR_0_ENB_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_ENB_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_ENB_DISABLE                  _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_ENB_ENABLE                   _MK_ENUM_CONST(1)
+
+// Interrupts when DMA Block Transfer Completes 
+#define APBDMACHAN_CHANNEL_3_CSR_0_IE_EOC_SHIFT                 _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_3_CSR_0_IE_EOC_FIELD                 (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_3_CSR_0_IE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_3_CSR_0_IE_EOC_RANGE                 30:30
+#define APBDMACHAN_CHANNEL_3_CSR_0_IE_EOC_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_3_CSR_0_IE_EOC_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_IE_EOC_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_3_CSR_0_IE_EOC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_IE_EOC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_IE_EOC_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_IE_EOC_ENABLE                        _MK_ENUM_CONST(1)
+
+// Holds this Processor until DMA Block Transfer Completes 
+#define APBDMACHAN_CHANNEL_3_CSR_0_HOLD_SHIFT                   _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_3_CSR_0_HOLD_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_3_CSR_0_HOLD_SHIFT)
+#define APBDMACHAN_CHANNEL_3_CSR_0_HOLD_RANGE                   29:29
+#define APBDMACHAN_CHANNEL_3_CSR_0_HOLD_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_3_CSR_0_HOLD_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_HOLD_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_3_CSR_0_HOLD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_HOLD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_HOLD_DISABLE                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_HOLD_ENABLE                  _MK_ENUM_CONST(1)
+
+// DMA Transfer Direction 1 = AHB read to APB write 0 = APB read to AHB write
+#define APBDMACHAN_CHANNEL_3_CSR_0_DIR_SHIFT                    _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_3_CSR_0_DIR_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_3_CSR_0_DIR_SHIFT)
+#define APBDMACHAN_CHANNEL_3_CSR_0_DIR_RANGE                    28:28
+#define APBDMACHAN_CHANNEL_3_CSR_0_DIR_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_3_CSR_0_DIR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_DIR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_3_CSR_0_DIR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_DIR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_DIR_AHB_WRITE                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_DIR_AHB_READ                 _MK_ENUM_CONST(1)
+
+// Run Once or Run Multiple Mode (Allow Retriggering of this Channel) 1 = Run for One Block Transfer 0 = Run for Multiple Block Transfer
+#define APBDMACHAN_CHANNEL_3_CSR_0_ONCE_SHIFT                   _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_3_CSR_0_ONCE_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_3_CSR_0_ONCE_SHIFT)
+#define APBDMACHAN_CHANNEL_3_CSR_0_ONCE_RANGE                   27:27
+#define APBDMACHAN_CHANNEL_3_CSR_0_ONCE_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_3_CSR_0_ONCE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_ONCE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_3_CSR_0_ONCE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_ONCE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_ONCE_MULTIPLE_BLOCK                  _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_ONCE_SINGLE_BLOCK                    _MK_ENUM_CONST(1)
+
+// Enable on Non-Zero Value
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_SHIFT                       _MK_SHIFT_CONST(22)
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_FIELD                       (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_RANGE                       26:22
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_NA1                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_SMP24                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_SMP25                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_SMP26                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_SMP27                       _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_XRQ_A                       _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_XRQ_B                       _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_TMR1                        _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_TMR2                        _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_APB_0                       _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_APB_1                       _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_APB_2                       _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_APB_3                       _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_APB_4                       _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_APB_5                       _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_APB_6                       _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_APB_7                       _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_APB_8                       _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_APB_9                       _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_APB_10                      _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_APB_11                      _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_APB_12                      _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_APB_13                      _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_APB_14                      _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_APB_15                      _MK_ENUM_CONST(24)
+
+// Flow Control Enable (Synchronize Burst Transfers) 1 = Link to DRQ source 0 = Independent of DRQ request
+#define APBDMACHAN_CHANNEL_3_CSR_0_FLOW_SHIFT                   _MK_SHIFT_CONST(21)
+#define APBDMACHAN_CHANNEL_3_CSR_0_FLOW_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_3_CSR_0_FLOW_SHIFT)
+#define APBDMACHAN_CHANNEL_3_CSR_0_FLOW_RANGE                   21:21
+#define APBDMACHAN_CHANNEL_3_CSR_0_FLOW_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_3_CSR_0_FLOW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_FLOW_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_3_CSR_0_FLOW_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_FLOW_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_FLOW_DISABLE                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_FLOW_ENABLE                  _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_SHIFT                        _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_FIELD                        (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_RANGE                        20:16
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_CNTR_REQ                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_I2S_2                        _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_I2S_1                        _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_SPD_I                        _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_UI_I                 _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_MIPI                 _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_I2S2_2                       _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_I2S2_1                       _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_UART_A                       _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_UART_B                       _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_UART_C                       _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_SPI                  _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_AC97                 _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_ACModem                      _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_SL4B                 _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_SL2B1                        _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_SL2B2                        _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_SL2B3                        _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_NA18                 _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_NA19                 _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_NA20                 _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_NA21                 _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_NA22                 _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_NA23                 _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_NA24                 _MK_ENUM_CONST(24)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_NA25                 _MK_ENUM_CONST(25)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_NA26                 _MK_ENUM_CONST(26)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_NA27                 _MK_ENUM_CONST(27)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_NA28                 _MK_ENUM_CONST(28)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_NA29                 _MK_ENUM_CONST(29)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_NA30                 _MK_ENUM_CONST(30)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_NA31                 _MK_ENUM_CONST(31)
+
+// Number of 32bit word cycles
+#define APBDMACHAN_CHANNEL_3_CSR_0_WCOUNT_SHIFT                 _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_3_CSR_0_WCOUNT_FIELD                 (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_3_CSR_0_WCOUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_3_CSR_0_WCOUNT_RANGE                 15:2
+#define APBDMACHAN_CHANNEL_3_CSR_0_WCOUNT_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_3_CSR_0_WCOUNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_WCOUNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_3_CSR_0_WCOUNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_WCOUNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_3_STA_0  
+#define APBDMACHAN_CHANNEL_3_STA_0                      _MK_ADDR_CONST(0x64)
+#define APBDMACHAN_CHANNEL_3_STA_0_WORD_COUNT                   0x1
+#define APBDMACHAN_CHANNEL_3_STA_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_STA_0_RESET_MASK                   _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_3_STA_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_STA_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_STA_0_READ_MASK                    _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_3_STA_0_WRITE_MASK                   _MK_MASK_CONST(0x40000000)
+// indicates whether DMA Channel Status active
+#define APBDMACHAN_CHANNEL_3_STA_0_BSY_SHIFT                    _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_3_STA_0_BSY_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_3_STA_0_BSY_SHIFT)
+#define APBDMACHAN_CHANNEL_3_STA_0_BSY_RANGE                    31:31
+#define APBDMACHAN_CHANNEL_3_STA_0_BSY_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_3_STA_0_BSY_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_STA_0_BSY_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_3_STA_0_BSY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_STA_0_BSY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_STA_0_BSY_WAIT                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_3_STA_0_BSY_ACTIVE                   _MK_ENUM_CONST(1)
+
+//  Write '1' to clear the flag
+#define APBDMACHAN_CHANNEL_3_STA_0_ISE_EOC_SHIFT                        _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_3_STA_0_ISE_EOC_FIELD                        (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_3_STA_0_ISE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_3_STA_0_ISE_EOC_RANGE                        30:30
+#define APBDMACHAN_CHANNEL_3_STA_0_ISE_EOC_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_3_STA_0_ISE_EOC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_STA_0_ISE_EOC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_3_STA_0_ISE_EOC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_STA_0_ISE_EOC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_STA_0_ISE_EOC_NO_INTR                      _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_3_STA_0_ISE_EOC_INTR                 _MK_ENUM_CONST(1)
+
+// Holding Status of Processor 
+#define APBDMACHAN_CHANNEL_3_STA_0_HALT_SHIFT                   _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_3_STA_0_HALT_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_3_STA_0_HALT_SHIFT)
+#define APBDMACHAN_CHANNEL_3_STA_0_HALT_RANGE                   29:29
+#define APBDMACHAN_CHANNEL_3_STA_0_HALT_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_3_STA_0_HALT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_STA_0_HALT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_3_STA_0_HALT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_STA_0_HALT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_STA_0_HALT_NO_HALT                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_3_STA_0_HALT_HALT                    _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_3_STA_0_PING_PONG_STA_SHIFT                  _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_3_STA_0_PING_PONG_STA_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_3_STA_0_PING_PONG_STA_SHIFT)
+#define APBDMACHAN_CHANNEL_3_STA_0_PING_PONG_STA_RANGE                  28:28
+#define APBDMACHAN_CHANNEL_3_STA_0_PING_PONG_STA_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_3_STA_0_PING_PONG_STA_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_STA_0_PING_PONG_STA_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_3_STA_0_PING_PONG_STA_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_STA_0_PING_PONG_STA_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_STA_0_PING_PONG_STA_PING_INTR_STA                  _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_3_STA_0_PING_PONG_STA_PONG_INTR_STA                  _MK_ENUM_CONST(1)
+
+// Current 32bit word cycles Flags set /cleared by HW
+#define APBDMACHAN_CHANNEL_3_STA_0_COUNT_SHIFT                  _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_3_STA_0_COUNT_FIELD                  (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_3_STA_0_COUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_3_STA_0_COUNT_RANGE                  15:2
+#define APBDMACHAN_CHANNEL_3_STA_0_COUNT_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_3_STA_0_COUNT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_STA_0_COUNT_DEFAULT_MASK                   _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_3_STA_0_COUNT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_STA_0_COUNT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Reserved address 104 [0x68] 
+
+// Reserved address 108 [0x6c] 
+
+// Register APBDMACHAN_CHANNEL_3_AHB_PTR_0  
+#define APBDMACHAN_CHANNEL_3_AHB_PTR_0                  _MK_ADDR_CONST(0x70)
+#define APBDMACHAN_CHANNEL_3_AHB_PTR_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_3_AHB_PTR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_AHB_PTR_0_RESET_MASK                       _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_3_AHB_PTR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_AHB_PTR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_AHB_PTR_0_READ_MASK                        _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_3_AHB_PTR_0_WRITE_MASK                       _MK_MASK_CONST(0xfffffffc)
+// APB-DMA Starting Address for AHB Bus: SW writes to  modify
+#define APBDMACHAN_CHANNEL_3_AHB_PTR_0_AHB_BASE_SHIFT                   _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_3_AHB_PTR_0_AHB_BASE_FIELD                   (_MK_MASK_CONST(0x3fffffff) << APBDMACHAN_CHANNEL_3_AHB_PTR_0_AHB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_3_AHB_PTR_0_AHB_BASE_RANGE                   31:2
+#define APBDMACHAN_CHANNEL_3_AHB_PTR_0_AHB_BASE_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_3_AHB_PTR_0_AHB_BASE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_AHB_PTR_0_AHB_BASE_DEFAULT_MASK                    _MK_MASK_CONST(0x3fffffff)
+#define APBDMACHAN_CHANNEL_3_AHB_PTR_0_AHB_BASE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_AHB_PTR_0_AHB_BASE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_3_AHB_SEQ_0  
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0                  _MK_ADDR_CONST(0x74)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_RESET_VAL                        _MK_MASK_CONST(0x22000000)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_RESET_MASK                       _MK_MASK_CONST(0xff070000)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_READ_MASK                        _MK_MASK_CONST(0xff070000)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_WRITE_MASK                       _MK_MASK_CONST(0xff070000)
+//  0 = send interrupt to COP                                            
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_INTR_ENB_SHIFT                   _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_INTR_ENB_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_3_AHB_SEQ_0_INTR_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_INTR_ENB_RANGE                   31:31
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_INTR_ENB_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_INTR_ENB_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_INTR_ENB_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_INTR_ENB_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_INTR_ENB_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_INTR_ENB_CPU                     _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_INTR_ENB_COP                     _MK_ENUM_CONST(0)
+
+// AHB Bus Width 0 = 8 bit Bus (RSVD) 1 = 16 bit Bus (RSVD) 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD)4 = 128 bit Bus (RSVD)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT                      _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_BUS_WIDTH_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_BUS_WIDTH_RANGE                      30:28
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_BUS_WIDTH_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT                    _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_8                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_16                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_32                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_64                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_128                      _MK_ENUM_CONST(4)
+
+// When enabled the data going  to AHB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT                      _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_DATA_SWAP_FIELD                      (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_DATA_SWAP_RANGE                      27:27
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_DATA_SWAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_DATA_SWAP_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_DATA_SWAP_ENABLE                     _MK_ENUM_CONST(1)
+
+// AHB Burst Size DMA Burst Length (encoded) 4 = 1 Word (1x32bits) 5 = 4 Words (4x32bits)else = 8 Words (8x32bits) default
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_BURST_SHIFT                  _MK_SHIFT_CONST(24)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_BURST_FIELD                  (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_BURST_SHIFT)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_BURST_RANGE                  26:24
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_BURST_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_BURST_DEFAULT                        _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_BURST_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_BURST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_BURST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_BURST_DMA_BURST_1WORDS                       _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_BURST_DMA_BURST_4WORDS                       _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_BURST_DMA_BURST_8WORDS                       _MK_ENUM_CONST(6)
+
+// AHB Address Wrap: AHB Address wrap-around window 0=No Wrap (default) 5=Wrap on 512 word window 1=Wrap on 32 word window 6=Wrap on 1024 word window 2=Wrap on 64 word window 7=Wrap on 2048 word window 3=Wrap on 128 word window 4=Wrap on 256 word window
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_WRAP_SHIFT                       _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_WRAP_FIELD                       (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_3_AHB_SEQ_0_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_WRAP_RANGE                       18:16
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_WRAP_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_WRAP_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_WRAP_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_WRAP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_WRAP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_WRAP_NO_WRAP                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_WRAP_WRAP_0N_32WORDS                     _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_WRAP_WRAP_ON_64WORDS                     _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_WRAP_WRAP_ON_128WORDS                    _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_WRAP_WRAP_ON_256WORDS                    _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_WRAP_WRAP_ON_512WORDS                    _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_WRAP_WRAP_ON_1024WORDS                   _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_WRAP_WRAP_ON_2048WORDS                   _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_3_APB_PTR_0  
+#define APBDMACHAN_CHANNEL_3_APB_PTR_0                  _MK_ADDR_CONST(0x78)
+#define APBDMACHAN_CHANNEL_3_APB_PTR_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_3_APB_PTR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_APB_PTR_0_RESET_MASK                       _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_3_APB_PTR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_APB_PTR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_APB_PTR_0_READ_MASK                        _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_3_APB_PTR_0_WRITE_MASK                       _MK_MASK_CONST(0xfffc)
+// APB-DMA Starting address for APB Bus: APB Base  address: Upper 16 bits are fixed at 0x7000:XXXX
+#define APBDMACHAN_CHANNEL_3_APB_PTR_0_APB_BASE_SHIFT                   _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_3_APB_PTR_0_APB_BASE_FIELD                   (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_3_APB_PTR_0_APB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_3_APB_PTR_0_APB_BASE_RANGE                   15:2
+#define APBDMACHAN_CHANNEL_3_APB_PTR_0_APB_BASE_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_3_APB_PTR_0_APB_BASE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_APB_PTR_0_APB_BASE_DEFAULT_MASK                    _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_3_APB_PTR_0_APB_BASE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_APB_PTR_0_APB_BASE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_3_APB_SEQ_0  
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0                  _MK_ADDR_CONST(0x7c)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_RESET_VAL                        _MK_MASK_CONST(0x20010000)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_RESET_MASK                       _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_READ_MASK                        _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_WRITE_MASK                       _MK_MASK_CONST(0x78070000)
+// 0 = 8 bit Bus 1 = 16 bit Bus 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD) 4 = 128 bit BUS (RSVD)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_BUS_WIDTH_SHIFT                      _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_BUS_WIDTH_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_BUS_WIDTH_RANGE                      30:28
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_BUS_WIDTH_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT                    _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_8                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_16                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_32                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_64                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_128                      _MK_ENUM_CONST(4)
+
+// when enabled the data going  to APB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_DATA_SWAP_SHIFT                      _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_DATA_SWAP_FIELD                      (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_DATA_SWAP_RANGE                      27:27
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_DATA_SWAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_DATA_SWAP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_DATA_SWAP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_DATA_SWAP_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_DATA_SWAP_ENABLE                     _MK_ENUM_CONST(1)
+
+//APB Address Wrap-around Window 0 = No Wrap 1 = Wrap on 1 Word Window (def) 2 = Wrap on 2 Word Window 3 = Wrap on 4 Word Window 4 = Wrap on 8 Word Window 5 = Wrap on 16 Word Window 6 = Wrap on 32 Word Window 7 = Wrap on 64 Word Window (rsvd)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_ADDR_WRAP_SHIFT                      _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_ADDR_WRAP_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_ADDR_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_ADDR_WRAP_RANGE                      18:16
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_ADDR_WRAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_ADDR_WRAP_NO_WRAP                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_ADDR_WRAP_WRAP_0N_1WORDS                     _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_2WORDS                     _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_4WORDS                     _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_8WORDS                     _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_16WORDS                    _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_32WORDS                    _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_64WORDS                    _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_4_CSR_0  
+#define APBDMACHAN_CHANNEL_4_CSR_0                      _MK_ADDR_CONST(0x80)
+#define APBDMACHAN_CHANNEL_4_CSR_0_WORD_COUNT                   0x1
+#define APBDMACHAN_CHANNEL_4_CSR_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_RESET_MASK                   _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_4_CSR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_READ_MASK                    _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_4_CSR_0_WRITE_MASK                   _MK_MASK_CONST(0xfffffffc)
+// Enables DMA channel transfer 
+#define APBDMACHAN_CHANNEL_4_CSR_0_ENB_SHIFT                    _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_4_CSR_0_ENB_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_4_CSR_0_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_4_CSR_0_ENB_RANGE                    31:31
+#define APBDMACHAN_CHANNEL_4_CSR_0_ENB_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_4_CSR_0_ENB_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_ENB_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_4_CSR_0_ENB_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_ENB_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_ENB_DISABLE                  _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_ENB_ENABLE                   _MK_ENUM_CONST(1)
+
+// Interrupts when DMA Block Transfer Completes 
+#define APBDMACHAN_CHANNEL_4_CSR_0_IE_EOC_SHIFT                 _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_4_CSR_0_IE_EOC_FIELD                 (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_4_CSR_0_IE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_4_CSR_0_IE_EOC_RANGE                 30:30
+#define APBDMACHAN_CHANNEL_4_CSR_0_IE_EOC_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_4_CSR_0_IE_EOC_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_IE_EOC_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_4_CSR_0_IE_EOC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_IE_EOC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_IE_EOC_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_IE_EOC_ENABLE                        _MK_ENUM_CONST(1)
+
+// Holds this Processor until DMA Block Transfer Completes 
+#define APBDMACHAN_CHANNEL_4_CSR_0_HOLD_SHIFT                   _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_4_CSR_0_HOLD_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_4_CSR_0_HOLD_SHIFT)
+#define APBDMACHAN_CHANNEL_4_CSR_0_HOLD_RANGE                   29:29
+#define APBDMACHAN_CHANNEL_4_CSR_0_HOLD_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_4_CSR_0_HOLD_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_HOLD_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_4_CSR_0_HOLD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_HOLD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_HOLD_DISABLE                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_HOLD_ENABLE                  _MK_ENUM_CONST(1)
+
+// DMA Transfer Direction 1 = AHB read to APB write 0 = APB read to AHB write
+#define APBDMACHAN_CHANNEL_4_CSR_0_DIR_SHIFT                    _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_4_CSR_0_DIR_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_4_CSR_0_DIR_SHIFT)
+#define APBDMACHAN_CHANNEL_4_CSR_0_DIR_RANGE                    28:28
+#define APBDMACHAN_CHANNEL_4_CSR_0_DIR_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_4_CSR_0_DIR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_DIR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_4_CSR_0_DIR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_DIR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_DIR_AHB_WRITE                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_DIR_AHB_READ                 _MK_ENUM_CONST(1)
+
+// Run Once or Run Multiple Mode (Allow Retriggering of this Channel) 1 = Run for One Block Transfer 0 = Run for Multiple Block Transfer
+#define APBDMACHAN_CHANNEL_4_CSR_0_ONCE_SHIFT                   _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_4_CSR_0_ONCE_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_4_CSR_0_ONCE_SHIFT)
+#define APBDMACHAN_CHANNEL_4_CSR_0_ONCE_RANGE                   27:27
+#define APBDMACHAN_CHANNEL_4_CSR_0_ONCE_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_4_CSR_0_ONCE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_ONCE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_4_CSR_0_ONCE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_ONCE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_ONCE_MULTIPLE_BLOCK                  _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_ONCE_SINGLE_BLOCK                    _MK_ENUM_CONST(1)
+
+// Enable on Non-Zero Value
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_SHIFT                       _MK_SHIFT_CONST(22)
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_FIELD                       (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_RANGE                       26:22
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_NA1                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_SMP24                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_SMP25                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_SMP26                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_SMP27                       _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_XRQ_A                       _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_XRQ_B                       _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_TMR1                        _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_TMR2                        _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_APB_0                       _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_APB_1                       _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_APB_2                       _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_APB_3                       _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_APB_4                       _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_APB_5                       _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_APB_6                       _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_APB_7                       _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_APB_8                       _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_APB_9                       _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_APB_10                      _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_APB_11                      _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_APB_12                      _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_APB_13                      _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_APB_14                      _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_APB_15                      _MK_ENUM_CONST(24)
+
+// Flow Control Enable (Synchronize Burst Transfers) 1 = Link to DRQ source 0 = Independent of DRQ request
+#define APBDMACHAN_CHANNEL_4_CSR_0_FLOW_SHIFT                   _MK_SHIFT_CONST(21)
+#define APBDMACHAN_CHANNEL_4_CSR_0_FLOW_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_4_CSR_0_FLOW_SHIFT)
+#define APBDMACHAN_CHANNEL_4_CSR_0_FLOW_RANGE                   21:21
+#define APBDMACHAN_CHANNEL_4_CSR_0_FLOW_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_4_CSR_0_FLOW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_FLOW_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_4_CSR_0_FLOW_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_FLOW_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_FLOW_DISABLE                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_FLOW_ENABLE                  _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_SHIFT                        _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_FIELD                        (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_RANGE                        20:16
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_CNTR_REQ                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_I2S_2                        _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_I2S_1                        _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_SPD_I                        _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_UI_I                 _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_MIPI                 _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_I2S2_2                       _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_I2S2_1                       _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_UART_A                       _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_UART_B                       _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_UART_C                       _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_SPI                  _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_AC97                 _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_ACModem                      _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_SL4B                 _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_SL2B1                        _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_SL2B2                        _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_SL2B3                        _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_NA18                 _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_NA19                 _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_NA20                 _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_NA21                 _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_NA22                 _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_NA23                 _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_NA24                 _MK_ENUM_CONST(24)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_NA25                 _MK_ENUM_CONST(25)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_NA26                 _MK_ENUM_CONST(26)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_NA27                 _MK_ENUM_CONST(27)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_NA28                 _MK_ENUM_CONST(28)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_NA29                 _MK_ENUM_CONST(29)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_NA30                 _MK_ENUM_CONST(30)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_NA31                 _MK_ENUM_CONST(31)
+
+// Number of 32bit word cycles
+#define APBDMACHAN_CHANNEL_4_CSR_0_WCOUNT_SHIFT                 _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_4_CSR_0_WCOUNT_FIELD                 (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_4_CSR_0_WCOUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_4_CSR_0_WCOUNT_RANGE                 15:2
+#define APBDMACHAN_CHANNEL_4_CSR_0_WCOUNT_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_4_CSR_0_WCOUNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_WCOUNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_4_CSR_0_WCOUNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_WCOUNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_4_STA_0  
+#define APBDMACHAN_CHANNEL_4_STA_0                      _MK_ADDR_CONST(0x84)
+#define APBDMACHAN_CHANNEL_4_STA_0_WORD_COUNT                   0x1
+#define APBDMACHAN_CHANNEL_4_STA_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_STA_0_RESET_MASK                   _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_4_STA_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_STA_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_STA_0_READ_MASK                    _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_4_STA_0_WRITE_MASK                   _MK_MASK_CONST(0x40000000)
+// indicates whether DMA Channel Status active or not
+#define APBDMACHAN_CHANNEL_4_STA_0_BSY_SHIFT                    _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_4_STA_0_BSY_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_4_STA_0_BSY_SHIFT)
+#define APBDMACHAN_CHANNEL_4_STA_0_BSY_RANGE                    31:31
+#define APBDMACHAN_CHANNEL_4_STA_0_BSY_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_4_STA_0_BSY_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_STA_0_BSY_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_4_STA_0_BSY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_STA_0_BSY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_STA_0_BSY_WAIT                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_4_STA_0_BSY_ACTIVE                   _MK_ENUM_CONST(1)
+
+//  Write '1' to clear the flag
+#define APBDMACHAN_CHANNEL_4_STA_0_ISE_EOC_SHIFT                        _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_4_STA_0_ISE_EOC_FIELD                        (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_4_STA_0_ISE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_4_STA_0_ISE_EOC_RANGE                        30:30
+#define APBDMACHAN_CHANNEL_4_STA_0_ISE_EOC_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_4_STA_0_ISE_EOC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_STA_0_ISE_EOC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_4_STA_0_ISE_EOC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_STA_0_ISE_EOC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_STA_0_ISE_EOC_NO_INTR                      _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_4_STA_0_ISE_EOC_INTR                 _MK_ENUM_CONST(1)
+
+// Holding Status of Processor 
+#define APBDMACHAN_CHANNEL_4_STA_0_HALT_SHIFT                   _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_4_STA_0_HALT_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_4_STA_0_HALT_SHIFT)
+#define APBDMACHAN_CHANNEL_4_STA_0_HALT_RANGE                   29:29
+#define APBDMACHAN_CHANNEL_4_STA_0_HALT_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_4_STA_0_HALT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_STA_0_HALT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_4_STA_0_HALT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_STA_0_HALT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_STA_0_HALT_NO_HALT                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_4_STA_0_HALT_HALT                    _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_4_STA_0_PING_PONG_STA_SHIFT                  _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_4_STA_0_PING_PONG_STA_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_4_STA_0_PING_PONG_STA_SHIFT)
+#define APBDMACHAN_CHANNEL_4_STA_0_PING_PONG_STA_RANGE                  28:28
+#define APBDMACHAN_CHANNEL_4_STA_0_PING_PONG_STA_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_4_STA_0_PING_PONG_STA_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_STA_0_PING_PONG_STA_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_4_STA_0_PING_PONG_STA_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_STA_0_PING_PONG_STA_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_STA_0_PING_PONG_STA_PING_INTR_STA                  _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_4_STA_0_PING_PONG_STA_PONG_INTR_STA                  _MK_ENUM_CONST(1)
+
+// Current 32bit word cycles Flags set /cleared by HW
+#define APBDMACHAN_CHANNEL_4_STA_0_COUNT_SHIFT                  _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_4_STA_0_COUNT_FIELD                  (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_4_STA_0_COUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_4_STA_0_COUNT_RANGE                  15:2
+#define APBDMACHAN_CHANNEL_4_STA_0_COUNT_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_4_STA_0_COUNT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_STA_0_COUNT_DEFAULT_MASK                   _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_4_STA_0_COUNT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_STA_0_COUNT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Reserved address 136 [0x88] 
+
+// Reserved address 140 [0x8c] 
+
+// Register APBDMACHAN_CHANNEL_4_AHB_PTR_0  
+#define APBDMACHAN_CHANNEL_4_AHB_PTR_0                  _MK_ADDR_CONST(0x90)
+#define APBDMACHAN_CHANNEL_4_AHB_PTR_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_4_AHB_PTR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_AHB_PTR_0_RESET_MASK                       _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_4_AHB_PTR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_AHB_PTR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_AHB_PTR_0_READ_MASK                        _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_4_AHB_PTR_0_WRITE_MASK                       _MK_MASK_CONST(0xfffffffc)
+// APB-DMA Starting Address for AHB Bus: SW writes to  modify
+#define APBDMACHAN_CHANNEL_4_AHB_PTR_0_AHB_BASE_SHIFT                   _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_4_AHB_PTR_0_AHB_BASE_FIELD                   (_MK_MASK_CONST(0x3fffffff) << APBDMACHAN_CHANNEL_4_AHB_PTR_0_AHB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_4_AHB_PTR_0_AHB_BASE_RANGE                   31:2
+#define APBDMACHAN_CHANNEL_4_AHB_PTR_0_AHB_BASE_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_4_AHB_PTR_0_AHB_BASE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_AHB_PTR_0_AHB_BASE_DEFAULT_MASK                    _MK_MASK_CONST(0x3fffffff)
+#define APBDMACHAN_CHANNEL_4_AHB_PTR_0_AHB_BASE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_AHB_PTR_0_AHB_BASE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_4_AHB_SEQ_0  
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0                  _MK_ADDR_CONST(0x94)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_RESET_VAL                        _MK_MASK_CONST(0x22000000)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_RESET_MASK                       _MK_MASK_CONST(0xff0f0000)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_READ_MASK                        _MK_MASK_CONST(0xff0f0000)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_WRITE_MASK                       _MK_MASK_CONST(0xff0f0000)
+//  0 = send interrupt to COP
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_INTR_ENB_SHIFT                   _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_INTR_ENB_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_4_AHB_SEQ_0_INTR_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_INTR_ENB_RANGE                   31:31
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_INTR_ENB_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_INTR_ENB_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_INTR_ENB_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_INTR_ENB_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_INTR_ENB_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_INTR_ENB_CPU                     _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_INTR_ENB_COP                     _MK_ENUM_CONST(0)
+
+// AHB Bus Width 0 = 8 bit Bus (RSVD) 1 = 16 bit Bus (RSVD) 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD)4 = 128 bit Bus (RSVD)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT                      _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_BUS_WIDTH_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_BUS_WIDTH_RANGE                      30:28
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_BUS_WIDTH_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT                    _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_8                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_16                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_32                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_64                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_128                      _MK_ENUM_CONST(4)
+
+// when enabled the data going  to AHB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT                      _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_DATA_SWAP_FIELD                      (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_DATA_SWAP_RANGE                      27:27
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_DATA_SWAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_DATA_SWAP_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_DATA_SWAP_ENABLE                     _MK_ENUM_CONST(1)
+
+// AHB Burst Size DMA Burst Length (encoded) 4 = 1 Word (1x32bits) 5 = 4 Words (4x32bits)else = 8 Words (8x32bits) default
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_BURST_SHIFT                  _MK_SHIFT_CONST(24)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_BURST_FIELD                  (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_BURST_SHIFT)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_BURST_RANGE                  26:24
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_BURST_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_BURST_DEFAULT                        _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_BURST_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_BURST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_BURST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_BURST_DMA_BURST_1WORDS                       _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_BURST_DMA_BURST_4WORDS                       _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_BURST_DMA_BURST_8WORDS                       _MK_ENUM_CONST(6)
+
+// 2X Double Buffering Mode (For Run-Multiple Mode with No Wrap Operations) 1 = Reload Base Address for 2X blocks (reload every other time) 0 = Reload Base Address for 1X blocks  (def) (reload each time)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_DBL_BUF_SHIFT                    _MK_SHIFT_CONST(19)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_DBL_BUF_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_4_AHB_SEQ_0_DBL_BUF_SHIFT)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_DBL_BUF_RANGE                    19:19
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_DBL_BUF_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_DBL_BUF_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_DBL_BUF_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_DBL_BUF_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_DBL_BUF_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_DBL_BUF_RELOAD_FOR_1X_BLOCKS                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_DBL_BUF_RELOAD_FOR_2X_BLOCKS                     _MK_ENUM_CONST(1)
+
+// AHB Address Wrap: AHB Address wrap-around window 0=No Wrap (default) 5=Wrap on 512 word window 1=Wrap on 32 word window 6=Wrap on 1024 word window 2=Wrap on 64 word window 7=Wrap on 2048 word window 3=Wrap on 128 word window 4=Wrap on 256 word window
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_WRAP_SHIFT                       _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_WRAP_FIELD                       (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_4_AHB_SEQ_0_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_WRAP_RANGE                       18:16
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_WRAP_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_WRAP_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_WRAP_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_WRAP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_WRAP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_WRAP_NO_WRAP                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_WRAP_WRAP_0N_32WORDS                     _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_WRAP_WRAP_ON_64WORDS                     _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_WRAP_WRAP_ON_128WORDS                    _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_WRAP_WRAP_ON_256WORDS                    _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_WRAP_WRAP_ON_512WORDS                    _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_WRAP_WRAP_ON_1024WORDS                   _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_WRAP_WRAP_ON_2048WORDS                   _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_4_APB_PTR_0  
+#define APBDMACHAN_CHANNEL_4_APB_PTR_0                  _MK_ADDR_CONST(0x98)
+#define APBDMACHAN_CHANNEL_4_APB_PTR_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_4_APB_PTR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_APB_PTR_0_RESET_MASK                       _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_4_APB_PTR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_APB_PTR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_APB_PTR_0_READ_MASK                        _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_4_APB_PTR_0_WRITE_MASK                       _MK_MASK_CONST(0xfffc)
+// APB-DMA Starting address for APB Bus: APB Base address:Upper 16 bits are fixed at 0x7000:XXXX
+#define APBDMACHAN_CHANNEL_4_APB_PTR_0_APB_BASE_SHIFT                   _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_4_APB_PTR_0_APB_BASE_FIELD                   (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_4_APB_PTR_0_APB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_4_APB_PTR_0_APB_BASE_RANGE                   15:2
+#define APBDMACHAN_CHANNEL_4_APB_PTR_0_APB_BASE_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_4_APB_PTR_0_APB_BASE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_APB_PTR_0_APB_BASE_DEFAULT_MASK                    _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_4_APB_PTR_0_APB_BASE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_APB_PTR_0_APB_BASE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_4_APB_SEQ_0  
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0                  _MK_ADDR_CONST(0x9c)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_RESET_VAL                        _MK_MASK_CONST(0x20010000)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_RESET_MASK                       _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_READ_MASK                        _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_WRITE_MASK                       _MK_MASK_CONST(0x78070000)
+// 0 = 8 bit Bus 1 = 16 bit Bus 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD) 4 = 128 bit BUS (RSVD)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_BUS_WIDTH_SHIFT                      _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_BUS_WIDTH_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_BUS_WIDTH_RANGE                      30:28
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_BUS_WIDTH_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT                    _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_8                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_16                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_32                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_64                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_128                      _MK_ENUM_CONST(4)
+
+// when enabled the data going  to APB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_DATA_SWAP_SHIFT                      _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_DATA_SWAP_FIELD                      (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_DATA_SWAP_RANGE                      27:27
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_DATA_SWAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_DATA_SWAP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_DATA_SWAP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_DATA_SWAP_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_DATA_SWAP_ENABLE                     _MK_ENUM_CONST(1)
+
+//APB Address Wrap-around Window 0 = No Wrap 1 = Wrap on 1 Word Window (def) 2 = Wrap on 2 Word Window 3 = Wrap on 4 Word Window 4 = Wrap on 8 Word Window 5 = Wrap on 16 Word Window 6 = Wrap on 32 Word Window 7 = Wrap on 64 Word Window (rsvd)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_ADDR_WRAP_SHIFT                      _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_ADDR_WRAP_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_ADDR_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_ADDR_WRAP_RANGE                      18:16
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_ADDR_WRAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_ADDR_WRAP_NO_WRAP                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_ADDR_WRAP_WRAP_0N_1WORDS                     _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_2WORDS                     _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_4WORDS                     _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_8WORDS                     _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_16WORDS                    _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_32WORDS                    _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_64WORDS                    _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_5_CSR_0  
+#define APBDMACHAN_CHANNEL_5_CSR_0                      _MK_ADDR_CONST(0xa0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_WORD_COUNT                   0x1
+#define APBDMACHAN_CHANNEL_5_CSR_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_RESET_MASK                   _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_5_CSR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_READ_MASK                    _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_5_CSR_0_WRITE_MASK                   _MK_MASK_CONST(0xfffffffc)
+// Enables DMA channel transfer
+#define APBDMACHAN_CHANNEL_5_CSR_0_ENB_SHIFT                    _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_5_CSR_0_ENB_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_5_CSR_0_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_5_CSR_0_ENB_RANGE                    31:31
+#define APBDMACHAN_CHANNEL_5_CSR_0_ENB_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_5_CSR_0_ENB_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_ENB_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_5_CSR_0_ENB_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_ENB_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_ENB_DISABLE                  _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_ENB_ENABLE                   _MK_ENUM_CONST(1)
+
+// Interrupts when DMA Block Transfer Completes 
+#define APBDMACHAN_CHANNEL_5_CSR_0_IE_EOC_SHIFT                 _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_5_CSR_0_IE_EOC_FIELD                 (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_5_CSR_0_IE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_5_CSR_0_IE_EOC_RANGE                 30:30
+#define APBDMACHAN_CHANNEL_5_CSR_0_IE_EOC_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_5_CSR_0_IE_EOC_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_IE_EOC_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_5_CSR_0_IE_EOC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_IE_EOC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_IE_EOC_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_IE_EOC_ENABLE                        _MK_ENUM_CONST(1)
+
+// Holds this Processor until DMA Block Transfer Completes 
+#define APBDMACHAN_CHANNEL_5_CSR_0_HOLD_SHIFT                   _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_5_CSR_0_HOLD_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_5_CSR_0_HOLD_SHIFT)
+#define APBDMACHAN_CHANNEL_5_CSR_0_HOLD_RANGE                   29:29
+#define APBDMACHAN_CHANNEL_5_CSR_0_HOLD_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_5_CSR_0_HOLD_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_HOLD_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_5_CSR_0_HOLD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_HOLD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_HOLD_DISABLE                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_HOLD_ENABLE                  _MK_ENUM_CONST(1)
+
+// DMA Transfer Direction 1 = AHB read to APB write 0 = APB read to AHB write
+#define APBDMACHAN_CHANNEL_5_CSR_0_DIR_SHIFT                    _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_5_CSR_0_DIR_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_5_CSR_0_DIR_SHIFT)
+#define APBDMACHAN_CHANNEL_5_CSR_0_DIR_RANGE                    28:28
+#define APBDMACHAN_CHANNEL_5_CSR_0_DIR_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_5_CSR_0_DIR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_DIR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_5_CSR_0_DIR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_DIR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_DIR_AHB_WRITE                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_DIR_AHB_READ                 _MK_ENUM_CONST(1)
+
+// Run Once or Run Multiple Mode (Allow Retriggering of this Channel) 1 = Run for One Block Transfer 0 = Run for Multiple Block Transfer
+#define APBDMACHAN_CHANNEL_5_CSR_0_ONCE_SHIFT                   _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_5_CSR_0_ONCE_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_5_CSR_0_ONCE_SHIFT)
+#define APBDMACHAN_CHANNEL_5_CSR_0_ONCE_RANGE                   27:27
+#define APBDMACHAN_CHANNEL_5_CSR_0_ONCE_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_5_CSR_0_ONCE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_ONCE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_5_CSR_0_ONCE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_ONCE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_ONCE_MULTIPLE_BLOCK                  _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_ONCE_SINGLE_BLOCK                    _MK_ENUM_CONST(1)
+
+// Enable on Non-Zero Value
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_SHIFT                       _MK_SHIFT_CONST(22)
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_FIELD                       (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_RANGE                       26:22
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_NA1                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_SMP24                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_SMP25                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_SMP26                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_SMP27                       _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_XRQ_A                       _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_XRQ_B                       _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_TMR1                        _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_TMR2                        _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_APB_0                       _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_APB_1                       _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_APB_2                       _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_APB_3                       _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_APB_4                       _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_APB_5                       _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_APB_6                       _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_APB_7                       _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_APB_8                       _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_APB_9                       _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_APB_10                      _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_APB_11                      _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_APB_12                      _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_APB_13                      _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_APB_14                      _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_APB_15                      _MK_ENUM_CONST(24)
+
+// Flow Control Enable (Synchronize Burst Transfers) 1 = Link to DRQ source 0 = Independent of DRQ request
+#define APBDMACHAN_CHANNEL_5_CSR_0_FLOW_SHIFT                   _MK_SHIFT_CONST(21)
+#define APBDMACHAN_CHANNEL_5_CSR_0_FLOW_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_5_CSR_0_FLOW_SHIFT)
+#define APBDMACHAN_CHANNEL_5_CSR_0_FLOW_RANGE                   21:21
+#define APBDMACHAN_CHANNEL_5_CSR_0_FLOW_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_5_CSR_0_FLOW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_FLOW_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_5_CSR_0_FLOW_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_FLOW_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_FLOW_DISABLE                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_FLOW_ENABLE                  _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_SHIFT                        _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_FIELD                        (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_RANGE                        20:16
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_CNTR_REQ                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_I2S_2                        _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_I2S_1                        _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_SPD_I                        _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_UI_I                 _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_MIPI                 _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_I2S2_2                       _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_I2S2_1                       _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_UART_A                       _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_UART_B                       _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_UART_C                       _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_SPI                  _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_AC97                 _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_ACModem                      _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_SL4B                 _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_SL2B1                        _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_SL2B2                        _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_SL2B3                        _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_NA18                 _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_NA19                 _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_NA20                 _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_NA21                 _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_NA22                 _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_NA23                 _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_NA24                 _MK_ENUM_CONST(24)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_NA25                 _MK_ENUM_CONST(25)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_NA26                 _MK_ENUM_CONST(26)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_NA27                 _MK_ENUM_CONST(27)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_NA28                 _MK_ENUM_CONST(28)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_NA29                 _MK_ENUM_CONST(29)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_NA30                 _MK_ENUM_CONST(30)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_NA31                 _MK_ENUM_CONST(31)
+
+// Number of 32bit word cycles
+#define APBDMACHAN_CHANNEL_5_CSR_0_WCOUNT_SHIFT                 _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_5_CSR_0_WCOUNT_FIELD                 (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_5_CSR_0_WCOUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_5_CSR_0_WCOUNT_RANGE                 15:2
+#define APBDMACHAN_CHANNEL_5_CSR_0_WCOUNT_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_5_CSR_0_WCOUNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_WCOUNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_5_CSR_0_WCOUNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_WCOUNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_5_STA_0  
+#define APBDMACHAN_CHANNEL_5_STA_0                      _MK_ADDR_CONST(0xa4)
+#define APBDMACHAN_CHANNEL_5_STA_0_WORD_COUNT                   0x1
+#define APBDMACHAN_CHANNEL_5_STA_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_STA_0_RESET_MASK                   _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_5_STA_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_STA_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_STA_0_READ_MASK                    _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_5_STA_0_WRITE_MASK                   _MK_MASK_CONST(0x40000000)
+// indicate whether DMA Channel Status active or not
+#define APBDMACHAN_CHANNEL_5_STA_0_BSY_SHIFT                    _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_5_STA_0_BSY_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_5_STA_0_BSY_SHIFT)
+#define APBDMACHAN_CHANNEL_5_STA_0_BSY_RANGE                    31:31
+#define APBDMACHAN_CHANNEL_5_STA_0_BSY_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_5_STA_0_BSY_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_STA_0_BSY_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_5_STA_0_BSY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_STA_0_BSY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_STA_0_BSY_WAIT                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_5_STA_0_BSY_ACTIVE                   _MK_ENUM_CONST(1)
+
+//  Write '1' to clear the flag
+#define APBDMACHAN_CHANNEL_5_STA_0_ISE_EOC_SHIFT                        _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_5_STA_0_ISE_EOC_FIELD                        (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_5_STA_0_ISE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_5_STA_0_ISE_EOC_RANGE                        30:30
+#define APBDMACHAN_CHANNEL_5_STA_0_ISE_EOC_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_5_STA_0_ISE_EOC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_STA_0_ISE_EOC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_5_STA_0_ISE_EOC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_STA_0_ISE_EOC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_STA_0_ISE_EOC_NO_INTR                      _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_5_STA_0_ISE_EOC_INTR                 _MK_ENUM_CONST(1)
+
+// Holding Status of Processor
+#define APBDMACHAN_CHANNEL_5_STA_0_HALT_SHIFT                   _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_5_STA_0_HALT_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_5_STA_0_HALT_SHIFT)
+#define APBDMACHAN_CHANNEL_5_STA_0_HALT_RANGE                   29:29
+#define APBDMACHAN_CHANNEL_5_STA_0_HALT_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_5_STA_0_HALT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_STA_0_HALT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_5_STA_0_HALT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_STA_0_HALT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_STA_0_HALT_NO_HALT                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_5_STA_0_HALT_HALT                    _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_5_STA_0_PING_PONG_STA_SHIFT                  _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_5_STA_0_PING_PONG_STA_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_5_STA_0_PING_PONG_STA_SHIFT)
+#define APBDMACHAN_CHANNEL_5_STA_0_PING_PONG_STA_RANGE                  28:28
+#define APBDMACHAN_CHANNEL_5_STA_0_PING_PONG_STA_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_5_STA_0_PING_PONG_STA_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_STA_0_PING_PONG_STA_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_5_STA_0_PING_PONG_STA_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_STA_0_PING_PONG_STA_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_STA_0_PING_PONG_STA_PING_INTR_STA                  _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_5_STA_0_PING_PONG_STA_PONG_INTR_STA                  _MK_ENUM_CONST(1)
+
+// Current 32bit word cycles Flags set /cleared by HW
+#define APBDMACHAN_CHANNEL_5_STA_0_COUNT_SHIFT                  _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_5_STA_0_COUNT_FIELD                  (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_5_STA_0_COUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_5_STA_0_COUNT_RANGE                  15:2
+#define APBDMACHAN_CHANNEL_5_STA_0_COUNT_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_5_STA_0_COUNT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_STA_0_COUNT_DEFAULT_MASK                   _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_5_STA_0_COUNT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_STA_0_COUNT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Reserved address 168 [0xa8] 
+
+// Reserved address 172 [0xac] 
+
+// Register APBDMACHAN_CHANNEL_5_AHB_PTR_0  
+#define APBDMACHAN_CHANNEL_5_AHB_PTR_0                  _MK_ADDR_CONST(0xb0)
+#define APBDMACHAN_CHANNEL_5_AHB_PTR_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_5_AHB_PTR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_AHB_PTR_0_RESET_MASK                       _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_5_AHB_PTR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_AHB_PTR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_AHB_PTR_0_READ_MASK                        _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_5_AHB_PTR_0_WRITE_MASK                       _MK_MASK_CONST(0xfffffffc)
+// APB-DMA Starting Address for AHB Bus: SW writes to  modify
+#define APBDMACHAN_CHANNEL_5_AHB_PTR_0_AHB_BASE_SHIFT                   _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_5_AHB_PTR_0_AHB_BASE_FIELD                   (_MK_MASK_CONST(0x3fffffff) << APBDMACHAN_CHANNEL_5_AHB_PTR_0_AHB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_5_AHB_PTR_0_AHB_BASE_RANGE                   31:2
+#define APBDMACHAN_CHANNEL_5_AHB_PTR_0_AHB_BASE_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_5_AHB_PTR_0_AHB_BASE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_AHB_PTR_0_AHB_BASE_DEFAULT_MASK                    _MK_MASK_CONST(0x3fffffff)
+#define APBDMACHAN_CHANNEL_5_AHB_PTR_0_AHB_BASE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_AHB_PTR_0_AHB_BASE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_5_AHB_SEQ_0  
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0                  _MK_ADDR_CONST(0xb4)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_RESET_VAL                        _MK_MASK_CONST(0x22000000)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_RESET_MASK                       _MK_MASK_CONST(0xff0f0000)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_READ_MASK                        _MK_MASK_CONST(0xff0f0000)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_WRITE_MASK                       _MK_MASK_CONST(0xff0f0000)
+//  0 = send interrupt to COP
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_INTR_ENB_SHIFT                   _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_INTR_ENB_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_5_AHB_SEQ_0_INTR_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_INTR_ENB_RANGE                   31:31
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_INTR_ENB_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_INTR_ENB_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_INTR_ENB_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_INTR_ENB_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_INTR_ENB_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_INTR_ENB_CPU                     _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_INTR_ENB_COP                     _MK_ENUM_CONST(0)
+
+// AHB Bus Width 0 = 8 bit Bus (RSVD) 1 = 16 bit Bus (RSVD) 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD)4 = 128 bit Bus (RSVD)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT                      _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_BUS_WIDTH_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_BUS_WIDTH_RANGE                      30:28
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_BUS_WIDTH_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT                    _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_8                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_16                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_32                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_64                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_128                      _MK_ENUM_CONST(4)
+
+// when enabled the data going  to AHB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT                      _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_DATA_SWAP_FIELD                      (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_DATA_SWAP_RANGE                      27:27
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_DATA_SWAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_DATA_SWAP_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_DATA_SWAP_ENABLE                     _MK_ENUM_CONST(1)
+
+// AHB Burst Size DMA Burst Length (encoded) 4 = 1 Word (1x32bits) 5 = 4 Words (4x32bits)else = 8 Words (8x32bits) default
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_BURST_SHIFT                  _MK_SHIFT_CONST(24)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_BURST_FIELD                  (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_BURST_SHIFT)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_BURST_RANGE                  26:24
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_BURST_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_BURST_DEFAULT                        _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_BURST_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_BURST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_BURST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_BURST_DMA_BURST_1WORDS                       _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_BURST_DMA_BURST_4WORDS                       _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_BURST_DMA_BURST_8WORDS                       _MK_ENUM_CONST(6)
+
+// 2X Double Buffering Mode (For Run-Multiple Mode with No Wrap Operations) 1 = Reload Base Address for 2X blocks (reload every other time) 0 = Reload Base Address for 1X blocks  (def) (reload each time)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_DBL_BUF_SHIFT                    _MK_SHIFT_CONST(19)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_DBL_BUF_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_5_AHB_SEQ_0_DBL_BUF_SHIFT)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_DBL_BUF_RANGE                    19:19
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_DBL_BUF_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_DBL_BUF_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_DBL_BUF_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_DBL_BUF_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_DBL_BUF_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_DBL_BUF_RELOAD_FOR_1X_BLOCKS                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_DBL_BUF_RELOAD_FOR_2X_BLOCKS                     _MK_ENUM_CONST(1)
+
+// AHB Address Wrap: AHB Address wrap-around window 0=No Wrap (default) 5=Wrap on 512 word window 1=Wrap on 32 word window 6=Wrap on 1024 word window 2=Wrap on 64 word window 7=Wrap on 2048 word window 3=Wrap on 128 word window 4=Wrap on 256 word window
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_WRAP_SHIFT                       _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_WRAP_FIELD                       (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_5_AHB_SEQ_0_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_WRAP_RANGE                       18:16
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_WRAP_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_WRAP_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_WRAP_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_WRAP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_WRAP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_WRAP_NO_WRAP                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_WRAP_WRAP_0N_32WORDS                     _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_WRAP_WRAP_ON_64WORDS                     _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_WRAP_WRAP_ON_128WORDS                    _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_WRAP_WRAP_ON_256WORDS                    _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_WRAP_WRAP_ON_512WORDS                    _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_WRAP_WRAP_ON_1024WORDS                   _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_WRAP_WRAP_ON_2048WORDS                   _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_5_APB_PTR_0  
+#define APBDMACHAN_CHANNEL_5_APB_PTR_0                  _MK_ADDR_CONST(0xb8)
+#define APBDMACHAN_CHANNEL_5_APB_PTR_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_5_APB_PTR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_APB_PTR_0_RESET_MASK                       _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_5_APB_PTR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_APB_PTR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_APB_PTR_0_READ_MASK                        _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_5_APB_PTR_0_WRITE_MASK                       _MK_MASK_CONST(0xfffc)
+// APB-DMA Starting address for APB Bus: APB Base address:Upper 16 bits are fixed at 0x7000:XXXX
+#define APBDMACHAN_CHANNEL_5_APB_PTR_0_APB_BASE_SHIFT                   _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_5_APB_PTR_0_APB_BASE_FIELD                   (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_5_APB_PTR_0_APB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_5_APB_PTR_0_APB_BASE_RANGE                   15:2
+#define APBDMACHAN_CHANNEL_5_APB_PTR_0_APB_BASE_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_5_APB_PTR_0_APB_BASE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_APB_PTR_0_APB_BASE_DEFAULT_MASK                    _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_5_APB_PTR_0_APB_BASE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_APB_PTR_0_APB_BASE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_5_APB_SEQ_0  
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0                  _MK_ADDR_CONST(0xbc)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_RESET_VAL                        _MK_MASK_CONST(0x20010000)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_RESET_MASK                       _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_READ_MASK                        _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_WRITE_MASK                       _MK_MASK_CONST(0x78070000)
+// 0 = 8 bit Bus 1 = 16 bit Bus 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD) 4 = 128 bit BUS (RSVD)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_BUS_WIDTH_SHIFT                      _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_BUS_WIDTH_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_BUS_WIDTH_RANGE                      30:28
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_BUS_WIDTH_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT                    _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_8                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_16                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_32                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_64                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_128                      _MK_ENUM_CONST(4)
+
+// when enabled the data going  to APB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_DATA_SWAP_SHIFT                      _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_DATA_SWAP_FIELD                      (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_DATA_SWAP_RANGE                      27:27
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_DATA_SWAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_DATA_SWAP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_DATA_SWAP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_DATA_SWAP_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_DATA_SWAP_ENABLE                     _MK_ENUM_CONST(1)
+
+//APB Address Wrap-around Window 0 = No Wrap 1 = Wrap on 1 Word Window (def) 2 = Wrap on 2 Word Window 3 = Wrap on 4 Word Window 4 = Wrap on 8 Word Window 5 = Wrap on 16 Word Window 6 = Wrap on 32 Word Window 7 = Wrap on 64 Word Window (rsvd)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_ADDR_WRAP_SHIFT                      _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_ADDR_WRAP_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_ADDR_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_ADDR_WRAP_RANGE                      18:16
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_ADDR_WRAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_ADDR_WRAP_NO_WRAP                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_ADDR_WRAP_WRAP_0N_1WORDS                     _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_2WORDS                     _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_4WORDS                     _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_8WORDS                     _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_16WORDS                    _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_32WORDS                    _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_64WORDS                    _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_6_CSR_0  
+#define APBDMACHAN_CHANNEL_6_CSR_0                      _MK_ADDR_CONST(0xc0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_WORD_COUNT                   0x1
+#define APBDMACHAN_CHANNEL_6_CSR_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_RESET_MASK                   _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_6_CSR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_READ_MASK                    _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_6_CSR_0_WRITE_MASK                   _MK_MASK_CONST(0xfffffffc)
+// Enables DMA channel transfer 
+#define APBDMACHAN_CHANNEL_6_CSR_0_ENB_SHIFT                    _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_6_CSR_0_ENB_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_6_CSR_0_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_6_CSR_0_ENB_RANGE                    31:31
+#define APBDMACHAN_CHANNEL_6_CSR_0_ENB_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_6_CSR_0_ENB_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_ENB_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_6_CSR_0_ENB_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_ENB_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_ENB_DISABLE                  _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_ENB_ENABLE                   _MK_ENUM_CONST(1)
+
+// Interrupts when DMA Block Transfer Completes 
+#define APBDMACHAN_CHANNEL_6_CSR_0_IE_EOC_SHIFT                 _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_6_CSR_0_IE_EOC_FIELD                 (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_6_CSR_0_IE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_6_CSR_0_IE_EOC_RANGE                 30:30
+#define APBDMACHAN_CHANNEL_6_CSR_0_IE_EOC_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_6_CSR_0_IE_EOC_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_IE_EOC_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_6_CSR_0_IE_EOC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_IE_EOC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_IE_EOC_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_IE_EOC_ENABLE                        _MK_ENUM_CONST(1)
+
+// Holds this Processor until DMA Block Transfer Completes
+#define APBDMACHAN_CHANNEL_6_CSR_0_HOLD_SHIFT                   _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_6_CSR_0_HOLD_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_6_CSR_0_HOLD_SHIFT)
+#define APBDMACHAN_CHANNEL_6_CSR_0_HOLD_RANGE                   29:29
+#define APBDMACHAN_CHANNEL_6_CSR_0_HOLD_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_6_CSR_0_HOLD_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_HOLD_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_6_CSR_0_HOLD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_HOLD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_HOLD_DISABLE                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_HOLD_ENABLE                  _MK_ENUM_CONST(1)
+
+// DMA Transfer Direction 1 = AHB read to APB write 0 = APB read to AHB write
+#define APBDMACHAN_CHANNEL_6_CSR_0_DIR_SHIFT                    _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_6_CSR_0_DIR_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_6_CSR_0_DIR_SHIFT)
+#define APBDMACHAN_CHANNEL_6_CSR_0_DIR_RANGE                    28:28
+#define APBDMACHAN_CHANNEL_6_CSR_0_DIR_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_6_CSR_0_DIR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_DIR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_6_CSR_0_DIR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_DIR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_DIR_AHB_WRITE                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_DIR_AHB_READ                 _MK_ENUM_CONST(1)
+
+// Run Once or Run Multiple Mode (Allow Retriggering of this Channel) 1 = Run for One Block Transfer 0 = Run for Multiple Block Transfer
+#define APBDMACHAN_CHANNEL_6_CSR_0_ONCE_SHIFT                   _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_6_CSR_0_ONCE_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_6_CSR_0_ONCE_SHIFT)
+#define APBDMACHAN_CHANNEL_6_CSR_0_ONCE_RANGE                   27:27
+#define APBDMACHAN_CHANNEL_6_CSR_0_ONCE_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_6_CSR_0_ONCE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_ONCE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_6_CSR_0_ONCE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_ONCE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_ONCE_MULTIPLE_BLOCK                  _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_ONCE_SINGLE_BLOCK                    _MK_ENUM_CONST(1)
+
+// Enable on Non-Zero Value
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_SHIFT                       _MK_SHIFT_CONST(22)
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_FIELD                       (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_RANGE                       26:22
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_NA1                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_SMP24                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_SMP25                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_SMP26                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_SMP27                       _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_XRQ_A                       _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_XRQ_B                       _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_TMR1                        _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_TMR2                        _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_APB_0                       _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_APB_1                       _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_APB_2                       _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_APB_3                       _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_APB_4                       _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_APB_5                       _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_APB_6                       _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_APB_7                       _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_APB_8                       _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_APB_9                       _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_APB_10                      _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_APB_11                      _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_APB_12                      _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_APB_13                      _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_APB_14                      _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_APB_15                      _MK_ENUM_CONST(24)
+
+// Flow Control Enable (Synchronize Burst Transfers) 1 = Link to DRQ source 0 = Independent of DRQ request
+#define APBDMACHAN_CHANNEL_6_CSR_0_FLOW_SHIFT                   _MK_SHIFT_CONST(21)
+#define APBDMACHAN_CHANNEL_6_CSR_0_FLOW_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_6_CSR_0_FLOW_SHIFT)
+#define APBDMACHAN_CHANNEL_6_CSR_0_FLOW_RANGE                   21:21
+#define APBDMACHAN_CHANNEL_6_CSR_0_FLOW_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_6_CSR_0_FLOW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_FLOW_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_6_CSR_0_FLOW_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_FLOW_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_FLOW_DISABLE                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_FLOW_ENABLE                  _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_SHIFT                        _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_FIELD                        (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_RANGE                        20:16
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_CNTR_REQ                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_I2S_2                        _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_I2S_1                        _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_SPD_I                        _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_UI_I                 _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_MIPI                 _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_I2S2_2                       _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_I2S2_1                       _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_UART_A                       _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_UART_B                       _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_UART_C                       _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_SPI                  _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_AC97                 _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_ACModem                      _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_SL4B                 _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_SL2B1                        _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_SL2B2                        _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_SL2B3                        _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_NA18                 _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_NA19                 _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_NA20                 _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_NA21                 _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_NA22                 _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_NA23                 _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_NA24                 _MK_ENUM_CONST(24)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_NA25                 _MK_ENUM_CONST(25)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_NA26                 _MK_ENUM_CONST(26)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_NA27                 _MK_ENUM_CONST(27)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_NA28                 _MK_ENUM_CONST(28)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_NA29                 _MK_ENUM_CONST(29)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_NA30                 _MK_ENUM_CONST(30)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_NA31                 _MK_ENUM_CONST(31)
+
+// Number of 32bit word cycles
+#define APBDMACHAN_CHANNEL_6_CSR_0_WCOUNT_SHIFT                 _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_6_CSR_0_WCOUNT_FIELD                 (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_6_CSR_0_WCOUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_6_CSR_0_WCOUNT_RANGE                 15:2
+#define APBDMACHAN_CHANNEL_6_CSR_0_WCOUNT_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_6_CSR_0_WCOUNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_WCOUNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_6_CSR_0_WCOUNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_WCOUNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_6_STA_0  
+#define APBDMACHAN_CHANNEL_6_STA_0                      _MK_ADDR_CONST(0xc4)
+#define APBDMACHAN_CHANNEL_6_STA_0_WORD_COUNT                   0x1
+#define APBDMACHAN_CHANNEL_6_STA_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_STA_0_RESET_MASK                   _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_6_STA_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_STA_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_STA_0_READ_MASK                    _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_6_STA_0_WRITE_MASK                   _MK_MASK_CONST(0x40000000)
+// indicate whether DMA Channel Status active or not
+#define APBDMACHAN_CHANNEL_6_STA_0_BSY_SHIFT                    _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_6_STA_0_BSY_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_6_STA_0_BSY_SHIFT)
+#define APBDMACHAN_CHANNEL_6_STA_0_BSY_RANGE                    31:31
+#define APBDMACHAN_CHANNEL_6_STA_0_BSY_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_6_STA_0_BSY_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_STA_0_BSY_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_6_STA_0_BSY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_STA_0_BSY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_STA_0_BSY_WAIT                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_6_STA_0_BSY_ACTIVE                   _MK_ENUM_CONST(1)
+
+//  Write '1' to clear the flag
+#define APBDMACHAN_CHANNEL_6_STA_0_ISE_EOC_SHIFT                        _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_6_STA_0_ISE_EOC_FIELD                        (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_6_STA_0_ISE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_6_STA_0_ISE_EOC_RANGE                        30:30
+#define APBDMACHAN_CHANNEL_6_STA_0_ISE_EOC_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_6_STA_0_ISE_EOC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_STA_0_ISE_EOC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_6_STA_0_ISE_EOC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_STA_0_ISE_EOC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_STA_0_ISE_EOC_NO_INTR                      _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_6_STA_0_ISE_EOC_INTR                 _MK_ENUM_CONST(1)
+
+// Holding Status of Processor 
+#define APBDMACHAN_CHANNEL_6_STA_0_HALT_SHIFT                   _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_6_STA_0_HALT_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_6_STA_0_HALT_SHIFT)
+#define APBDMACHAN_CHANNEL_6_STA_0_HALT_RANGE                   29:29
+#define APBDMACHAN_CHANNEL_6_STA_0_HALT_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_6_STA_0_HALT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_STA_0_HALT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_6_STA_0_HALT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_STA_0_HALT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_STA_0_HALT_NO_HALT                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_6_STA_0_HALT_HALT                    _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_6_STA_0_PING_PONG_STA_SHIFT                  _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_6_STA_0_PING_PONG_STA_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_6_STA_0_PING_PONG_STA_SHIFT)
+#define APBDMACHAN_CHANNEL_6_STA_0_PING_PONG_STA_RANGE                  28:28
+#define APBDMACHAN_CHANNEL_6_STA_0_PING_PONG_STA_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_6_STA_0_PING_PONG_STA_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_STA_0_PING_PONG_STA_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_6_STA_0_PING_PONG_STA_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_STA_0_PING_PONG_STA_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_STA_0_PING_PONG_STA_PING_INTR_STA                  _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_6_STA_0_PING_PONG_STA_PONG_INTR_STA                  _MK_ENUM_CONST(1)
+
+// Current 32bit word cycles Flags set /cleared by HW
+#define APBDMACHAN_CHANNEL_6_STA_0_COUNT_SHIFT                  _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_6_STA_0_COUNT_FIELD                  (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_6_STA_0_COUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_6_STA_0_COUNT_RANGE                  15:2
+#define APBDMACHAN_CHANNEL_6_STA_0_COUNT_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_6_STA_0_COUNT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_STA_0_COUNT_DEFAULT_MASK                   _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_6_STA_0_COUNT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_STA_0_COUNT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Reserved address 200 [0xc8] 
+
+// Reserved address 204 [0xcc] 
+
+// Register APBDMACHAN_CHANNEL_6_AHB_PTR_0  
+#define APBDMACHAN_CHANNEL_6_AHB_PTR_0                  _MK_ADDR_CONST(0xd0)
+#define APBDMACHAN_CHANNEL_6_AHB_PTR_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_6_AHB_PTR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_AHB_PTR_0_RESET_MASK                       _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_6_AHB_PTR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_AHB_PTR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_AHB_PTR_0_READ_MASK                        _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_6_AHB_PTR_0_WRITE_MASK                       _MK_MASK_CONST(0xfffffffc)
+// APB-DMA Starting Address for AHB Bus: SW writes to  modify
+#define APBDMACHAN_CHANNEL_6_AHB_PTR_0_AHB_BASE_SHIFT                   _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_6_AHB_PTR_0_AHB_BASE_FIELD                   (_MK_MASK_CONST(0x3fffffff) << APBDMACHAN_CHANNEL_6_AHB_PTR_0_AHB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_6_AHB_PTR_0_AHB_BASE_RANGE                   31:2
+#define APBDMACHAN_CHANNEL_6_AHB_PTR_0_AHB_BASE_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_6_AHB_PTR_0_AHB_BASE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_AHB_PTR_0_AHB_BASE_DEFAULT_MASK                    _MK_MASK_CONST(0x3fffffff)
+#define APBDMACHAN_CHANNEL_6_AHB_PTR_0_AHB_BASE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_AHB_PTR_0_AHB_BASE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_6_AHB_SEQ_0  
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0                  _MK_ADDR_CONST(0xd4)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_RESET_VAL                        _MK_MASK_CONST(0x22000000)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_RESET_MASK                       _MK_MASK_CONST(0xff0f0000)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_READ_MASK                        _MK_MASK_CONST(0xff0f0000)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_WRITE_MASK                       _MK_MASK_CONST(0xff0f0000)
+//  0 = send interrupt to COP
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_INTR_ENB_SHIFT                   _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_INTR_ENB_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_6_AHB_SEQ_0_INTR_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_INTR_ENB_RANGE                   31:31
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_INTR_ENB_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_INTR_ENB_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_INTR_ENB_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_INTR_ENB_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_INTR_ENB_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_INTR_ENB_CPU                     _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_INTR_ENB_COP                     _MK_ENUM_CONST(0)
+
+// AHB Bus Width 0 = 8 bit Bus (RSVD) 1 = 16 bit Bus (RSVD) 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD)4 = 128 bit Bus (RSVD)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT                      _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_BUS_WIDTH_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_BUS_WIDTH_RANGE                      30:28
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_BUS_WIDTH_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT                    _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_8                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_16                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_32                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_64                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_128                      _MK_ENUM_CONST(4)
+
+// when enabled the data going  to AHB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT                      _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_DATA_SWAP_FIELD                      (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_DATA_SWAP_RANGE                      27:27
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_DATA_SWAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_DATA_SWAP_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_DATA_SWAP_ENABLE                     _MK_ENUM_CONST(1)
+
+// AHB Burst Size DMA Burst Length (encoded) 4 = 1 Word (1x32bits) 5 = 4 Words (4x32bits)else = 8 Words (8x32bits) default
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_BURST_SHIFT                  _MK_SHIFT_CONST(24)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_BURST_FIELD                  (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_BURST_SHIFT)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_BURST_RANGE                  26:24
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_BURST_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_BURST_DEFAULT                        _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_BURST_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_BURST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_BURST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_BURST_DMA_BURST_1WORDS                       _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_BURST_DMA_BURST_4WORDS                       _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_BURST_DMA_BURST_8WORDS                       _MK_ENUM_CONST(6)
+
+// 2X Double Buffering Mode (For Run-Multiple Mode with No Wrap Operations) 1 = Reload Base Address for 2X blocks (reload every other time) 0 = Reload Base Address for 1X blocks  (def) (reload each time)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_DBL_BUF_SHIFT                    _MK_SHIFT_CONST(19)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_DBL_BUF_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_6_AHB_SEQ_0_DBL_BUF_SHIFT)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_DBL_BUF_RANGE                    19:19
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_DBL_BUF_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_DBL_BUF_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_DBL_BUF_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_DBL_BUF_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_DBL_BUF_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_DBL_BUF_RELOAD_FOR_1X_BLOCKS                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_DBL_BUF_RELOAD_FOR_2X_BLOCKS                     _MK_ENUM_CONST(1)
+
+// AHB Address Wrap: AHB Address wrap-around window 0=No Wrap (default) 5=Wrap on 512 word window 1=Wrap on 32 word window 6=Wrap on 1024 word window 2=Wrap on 64 word window 7=Wrap on 2048 word window 3=Wrap on 128 word window 4=Wrap on 256 word window
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_WRAP_SHIFT                       _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_WRAP_FIELD                       (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_6_AHB_SEQ_0_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_WRAP_RANGE                       18:16
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_WRAP_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_WRAP_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_WRAP_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_WRAP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_WRAP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_WRAP_NO_WRAP                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_WRAP_WRAP_0N_32WORDS                     _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_WRAP_WRAP_ON_64WORDS                     _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_WRAP_WRAP_ON_128WORDS                    _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_WRAP_WRAP_ON_256WORDS                    _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_WRAP_WRAP_ON_512WORDS                    _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_WRAP_WRAP_ON_1024WORDS                   _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_WRAP_WRAP_ON_2048WORDS                   _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_6_APB_PTR_0  
+#define APBDMACHAN_CHANNEL_6_APB_PTR_0                  _MK_ADDR_CONST(0xd8)
+#define APBDMACHAN_CHANNEL_6_APB_PTR_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_6_APB_PTR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_APB_PTR_0_RESET_MASK                       _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_6_APB_PTR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_APB_PTR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_APB_PTR_0_READ_MASK                        _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_6_APB_PTR_0_WRITE_MASK                       _MK_MASK_CONST(0xfffc)
+// APB-DMA Starting address for APB Bus: APB Base address:Upper 16 bits are fixed at 0x7000:XXXX
+#define APBDMACHAN_CHANNEL_6_APB_PTR_0_APB_BASE_SHIFT                   _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_6_APB_PTR_0_APB_BASE_FIELD                   (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_6_APB_PTR_0_APB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_6_APB_PTR_0_APB_BASE_RANGE                   15:2
+#define APBDMACHAN_CHANNEL_6_APB_PTR_0_APB_BASE_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_6_APB_PTR_0_APB_BASE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_APB_PTR_0_APB_BASE_DEFAULT_MASK                    _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_6_APB_PTR_0_APB_BASE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_APB_PTR_0_APB_BASE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_6_APB_SEQ_0  
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0                  _MK_ADDR_CONST(0xdc)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_RESET_VAL                        _MK_MASK_CONST(0x20010000)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_RESET_MASK                       _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_READ_MASK                        _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_WRITE_MASK                       _MK_MASK_CONST(0x78070000)
+// 0 = 8 bit Bus 1 = 16 bit Bus 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD) 4 = 128 bit BUS (RSVD)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_BUS_WIDTH_SHIFT                      _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_BUS_WIDTH_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_BUS_WIDTH_RANGE                      30:28
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_BUS_WIDTH_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT                    _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_8                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_16                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_32                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_64                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_128                      _MK_ENUM_CONST(4)
+
+// when enabled the data going  to APB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_DATA_SWAP_SHIFT                      _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_DATA_SWAP_FIELD                      (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_DATA_SWAP_RANGE                      27:27
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_DATA_SWAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_DATA_SWAP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_DATA_SWAP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_DATA_SWAP_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_DATA_SWAP_ENABLE                     _MK_ENUM_CONST(1)
+
+//APB Address Wrap-around Window 0 = No Wrap 1 = Wrap on 1 Word Window (def) 2 = Wrap on 2 Word Window 3 = Wrap on 4 Word Window 4 = Wrap on 8 Word Window 5 = Wrap on 16 Word Window 6 = Wrap on 32 Word Window 7 = Wrap on 64 Word Window (rsvd)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_ADDR_WRAP_SHIFT                      _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_ADDR_WRAP_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_ADDR_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_ADDR_WRAP_RANGE                      18:16
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_ADDR_WRAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_ADDR_WRAP_NO_WRAP                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_ADDR_WRAP_WRAP_0N_1WORDS                     _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_2WORDS                     _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_4WORDS                     _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_8WORDS                     _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_16WORDS                    _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_32WORDS                    _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_64WORDS                    _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_7_CSR_0  
+#define APBDMACHAN_CHANNEL_7_CSR_0                      _MK_ADDR_CONST(0xe0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_WORD_COUNT                   0x1
+#define APBDMACHAN_CHANNEL_7_CSR_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_RESET_MASK                   _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_7_CSR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_READ_MASK                    _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_7_CSR_0_WRITE_MASK                   _MK_MASK_CONST(0xfffffffc)
+// Enables DMA channel transfer 
+#define APBDMACHAN_CHANNEL_7_CSR_0_ENB_SHIFT                    _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_7_CSR_0_ENB_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_7_CSR_0_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_7_CSR_0_ENB_RANGE                    31:31
+#define APBDMACHAN_CHANNEL_7_CSR_0_ENB_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_7_CSR_0_ENB_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_ENB_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_7_CSR_0_ENB_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_ENB_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_ENB_DISABLE                  _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_ENB_ENABLE                   _MK_ENUM_CONST(1)
+
+// Interrupts when DMA Block Transfer Completes 
+#define APBDMACHAN_CHANNEL_7_CSR_0_IE_EOC_SHIFT                 _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_7_CSR_0_IE_EOC_FIELD                 (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_7_CSR_0_IE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_7_CSR_0_IE_EOC_RANGE                 30:30
+#define APBDMACHAN_CHANNEL_7_CSR_0_IE_EOC_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_7_CSR_0_IE_EOC_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_IE_EOC_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_7_CSR_0_IE_EOC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_IE_EOC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_IE_EOC_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_IE_EOC_ENABLE                        _MK_ENUM_CONST(1)
+
+// Holds this Processor until DMA Block Transfer Completes
+#define APBDMACHAN_CHANNEL_7_CSR_0_HOLD_SHIFT                   _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_7_CSR_0_HOLD_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_7_CSR_0_HOLD_SHIFT)
+#define APBDMACHAN_CHANNEL_7_CSR_0_HOLD_RANGE                   29:29
+#define APBDMACHAN_CHANNEL_7_CSR_0_HOLD_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_7_CSR_0_HOLD_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_HOLD_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_7_CSR_0_HOLD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_HOLD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_HOLD_DISABLE                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_HOLD_ENABLE                  _MK_ENUM_CONST(1)
+
+// DMA Transfer Direction 1 = AHB read to APB write 0 = APB read to AHB write
+#define APBDMACHAN_CHANNEL_7_CSR_0_DIR_SHIFT                    _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_7_CSR_0_DIR_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_7_CSR_0_DIR_SHIFT)
+#define APBDMACHAN_CHANNEL_7_CSR_0_DIR_RANGE                    28:28
+#define APBDMACHAN_CHANNEL_7_CSR_0_DIR_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_7_CSR_0_DIR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_DIR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_7_CSR_0_DIR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_DIR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_DIR_AHB_WRITE                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_DIR_AHB_READ                 _MK_ENUM_CONST(1)
+
+// Run Once or Run Multiple Mode (Allow Retriggering of this Channel) 1 = Run for One Block Transfer 0 = Run for Multiple Block Transfer
+#define APBDMACHAN_CHANNEL_7_CSR_0_ONCE_SHIFT                   _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_7_CSR_0_ONCE_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_7_CSR_0_ONCE_SHIFT)
+#define APBDMACHAN_CHANNEL_7_CSR_0_ONCE_RANGE                   27:27
+#define APBDMACHAN_CHANNEL_7_CSR_0_ONCE_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_7_CSR_0_ONCE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_ONCE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_7_CSR_0_ONCE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_ONCE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_ONCE_MULTIPLE_BLOCK                  _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_ONCE_SINGLE_BLOCK                    _MK_ENUM_CONST(1)
+
+// Enable on Non-Zero Value
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_SHIFT                       _MK_SHIFT_CONST(22)
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_FIELD                       (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_RANGE                       26:22
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_NA1                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_SMP24                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_SMP25                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_SMP26                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_SMP27                       _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_XRQ_A                       _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_XRQ_B                       _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_TMR1                        _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_TMR2                        _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_APB_0                       _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_APB_1                       _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_APB_2                       _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_APB_3                       _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_APB_4                       _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_APB_5                       _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_APB_6                       _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_APB_7                       _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_APB_8                       _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_APB_9                       _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_APB_10                      _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_APB_11                      _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_APB_12                      _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_APB_13                      _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_APB_14                      _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_APB_15                      _MK_ENUM_CONST(24)
+
+// Flow Control Enable (Synchronize Burst Transfers) 1 = Link to DRQ source 0 = Independent of DRQ request
+#define APBDMACHAN_CHANNEL_7_CSR_0_FLOW_SHIFT                   _MK_SHIFT_CONST(21)
+#define APBDMACHAN_CHANNEL_7_CSR_0_FLOW_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_7_CSR_0_FLOW_SHIFT)
+#define APBDMACHAN_CHANNEL_7_CSR_0_FLOW_RANGE                   21:21
+#define APBDMACHAN_CHANNEL_7_CSR_0_FLOW_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_7_CSR_0_FLOW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_FLOW_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_7_CSR_0_FLOW_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_FLOW_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_FLOW_DISABLE                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_FLOW_ENABLE                  _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_SHIFT                        _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_FIELD                        (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_RANGE                        20:16
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_CNTR_REQ                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_I2S_2                        _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_I2S_1                        _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_SPD_I                        _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_UI_I                 _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_MIPI                 _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_I2S2_2                       _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_I2S2_1                       _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_UART_A                       _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_UART_B                       _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_UART_C                       _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_SPI                  _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_AC97                 _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_ACModem                      _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_SL4B                 _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_SL2B1                        _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_SL2B2                        _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_SL2B3                        _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_NA18                 _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_NA19                 _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_NA20                 _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_NA21                 _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_NA22                 _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_NA23                 _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_NA24                 _MK_ENUM_CONST(24)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_NA25                 _MK_ENUM_CONST(25)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_NA26                 _MK_ENUM_CONST(26)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_NA27                 _MK_ENUM_CONST(27)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_NA28                 _MK_ENUM_CONST(28)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_NA29                 _MK_ENUM_CONST(29)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_NA30                 _MK_ENUM_CONST(30)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_NA31                 _MK_ENUM_CONST(31)
+
+// Number of 32bit word cycles
+#define APBDMACHAN_CHANNEL_7_CSR_0_WCOUNT_SHIFT                 _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_7_CSR_0_WCOUNT_FIELD                 (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_7_CSR_0_WCOUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_7_CSR_0_WCOUNT_RANGE                 15:2
+#define APBDMACHAN_CHANNEL_7_CSR_0_WCOUNT_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_7_CSR_0_WCOUNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_WCOUNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_7_CSR_0_WCOUNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_WCOUNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_7_STA_0  
+#define APBDMACHAN_CHANNEL_7_STA_0                      _MK_ADDR_CONST(0xe4)
+#define APBDMACHAN_CHANNEL_7_STA_0_WORD_COUNT                   0x1
+#define APBDMACHAN_CHANNEL_7_STA_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_STA_0_RESET_MASK                   _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_7_STA_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_STA_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_STA_0_READ_MASK                    _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_7_STA_0_WRITE_MASK                   _MK_MASK_CONST(0x40000000)
+// indicate whether DMA Channel Status Active or not 
+#define APBDMACHAN_CHANNEL_7_STA_0_BSY_SHIFT                    _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_7_STA_0_BSY_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_7_STA_0_BSY_SHIFT)
+#define APBDMACHAN_CHANNEL_7_STA_0_BSY_RANGE                    31:31
+#define APBDMACHAN_CHANNEL_7_STA_0_BSY_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_7_STA_0_BSY_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_STA_0_BSY_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_7_STA_0_BSY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_STA_0_BSY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_STA_0_BSY_WAIT                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_7_STA_0_BSY_ACTIVE                   _MK_ENUM_CONST(1)
+
+//  Write '1' to clear the flag
+#define APBDMACHAN_CHANNEL_7_STA_0_ISE_EOC_SHIFT                        _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_7_STA_0_ISE_EOC_FIELD                        (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_7_STA_0_ISE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_7_STA_0_ISE_EOC_RANGE                        30:30
+#define APBDMACHAN_CHANNEL_7_STA_0_ISE_EOC_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_7_STA_0_ISE_EOC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_STA_0_ISE_EOC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_7_STA_0_ISE_EOC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_STA_0_ISE_EOC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_STA_0_ISE_EOC_NO_INTR                      _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_7_STA_0_ISE_EOC_INTR                 _MK_ENUM_CONST(1)
+
+// Holding Status of Processor 
+#define APBDMACHAN_CHANNEL_7_STA_0_HALT_SHIFT                   _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_7_STA_0_HALT_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_7_STA_0_HALT_SHIFT)
+#define APBDMACHAN_CHANNEL_7_STA_0_HALT_RANGE                   29:29
+#define APBDMACHAN_CHANNEL_7_STA_0_HALT_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_7_STA_0_HALT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_STA_0_HALT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_7_STA_0_HALT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_STA_0_HALT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_STA_0_HALT_NO_HALT                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_7_STA_0_HALT_HALT                    _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_7_STA_0_PING_PONG_STA_SHIFT                  _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_7_STA_0_PING_PONG_STA_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_7_STA_0_PING_PONG_STA_SHIFT)
+#define APBDMACHAN_CHANNEL_7_STA_0_PING_PONG_STA_RANGE                  28:28
+#define APBDMACHAN_CHANNEL_7_STA_0_PING_PONG_STA_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_7_STA_0_PING_PONG_STA_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_STA_0_PING_PONG_STA_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_7_STA_0_PING_PONG_STA_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_STA_0_PING_PONG_STA_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_STA_0_PING_PONG_STA_PING_INTR_STA                  _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_7_STA_0_PING_PONG_STA_PONG_INTR_STA                  _MK_ENUM_CONST(1)
+
+// Current 32bit word cycles Flags set /cleared by HW
+#define APBDMACHAN_CHANNEL_7_STA_0_COUNT_SHIFT                  _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_7_STA_0_COUNT_FIELD                  (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_7_STA_0_COUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_7_STA_0_COUNT_RANGE                  15:2
+#define APBDMACHAN_CHANNEL_7_STA_0_COUNT_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_7_STA_0_COUNT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_STA_0_COUNT_DEFAULT_MASK                   _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_7_STA_0_COUNT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_STA_0_COUNT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Reserved address 232 [0xe8] 
+
+// Reserved address 236 [0xec] 
+
+// Register APBDMACHAN_CHANNEL_7_AHB_PTR_0  
+#define APBDMACHAN_CHANNEL_7_AHB_PTR_0                  _MK_ADDR_CONST(0xf0)
+#define APBDMACHAN_CHANNEL_7_AHB_PTR_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_7_AHB_PTR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_AHB_PTR_0_RESET_MASK                       _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_7_AHB_PTR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_AHB_PTR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_AHB_PTR_0_READ_MASK                        _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_7_AHB_PTR_0_WRITE_MASK                       _MK_MASK_CONST(0xfffffffc)
+// APB-DMA Starting Address for AHB Bus: SW writes to  modify
+#define APBDMACHAN_CHANNEL_7_AHB_PTR_0_AHB_BASE_SHIFT                   _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_7_AHB_PTR_0_AHB_BASE_FIELD                   (_MK_MASK_CONST(0x3fffffff) << APBDMACHAN_CHANNEL_7_AHB_PTR_0_AHB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_7_AHB_PTR_0_AHB_BASE_RANGE                   31:2
+#define APBDMACHAN_CHANNEL_7_AHB_PTR_0_AHB_BASE_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_7_AHB_PTR_0_AHB_BASE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_AHB_PTR_0_AHB_BASE_DEFAULT_MASK                    _MK_MASK_CONST(0x3fffffff)
+#define APBDMACHAN_CHANNEL_7_AHB_PTR_0_AHB_BASE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_AHB_PTR_0_AHB_BASE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_7_AHB_SEQ_0  
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0                  _MK_ADDR_CONST(0xf4)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_RESET_VAL                        _MK_MASK_CONST(0x22000000)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_RESET_MASK                       _MK_MASK_CONST(0xff0f0000)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_READ_MASK                        _MK_MASK_CONST(0xff0f0000)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_WRITE_MASK                       _MK_MASK_CONST(0xff0f0000)
+//  0 = send interrupt to COP
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_INTR_ENB_SHIFT                   _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_INTR_ENB_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_7_AHB_SEQ_0_INTR_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_INTR_ENB_RANGE                   31:31
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_INTR_ENB_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_INTR_ENB_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_INTR_ENB_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_INTR_ENB_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_INTR_ENB_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_INTR_ENB_CPU                     _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_INTR_ENB_COP                     _MK_ENUM_CONST(0)
+
+// AHB Bus Width 0 = 8 bit Bus (RSVD) 1 = 16 bit Bus (RSVD) 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD)4 = 128 bit Bus (RSVD)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT                      _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_BUS_WIDTH_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_BUS_WIDTH_RANGE                      30:28
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_BUS_WIDTH_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT                    _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_8                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_16                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_32                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_64                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_128                      _MK_ENUM_CONST(4)
+
+// when enabled the data going  to AHB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT                      _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_DATA_SWAP_FIELD                      (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_DATA_SWAP_RANGE                      27:27
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_DATA_SWAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_DATA_SWAP_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_DATA_SWAP_ENABLE                     _MK_ENUM_CONST(1)
+
+// AHB Burst Size DMA Burst Length (encoded) 4 = 1 Word (1x32bits) 5 = 4 Words (4x32bits)else = 8 Words (8x32bits) default
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_BURST_SHIFT                  _MK_SHIFT_CONST(24)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_BURST_FIELD                  (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_BURST_SHIFT)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_BURST_RANGE                  26:24
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_BURST_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_BURST_DEFAULT                        _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_BURST_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_BURST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_BURST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_BURST_DMA_BURST_1WORDS                       _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_BURST_DMA_BURST_4WORDS                       _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_BURST_DMA_BURST_8WORDS                       _MK_ENUM_CONST(6)
+
+// 2X Double Buffering Mode (For Run-Multiple Mode with No Wrap Operations) 1 = Reload Base Address for 2X blocks (reload every other time) 0 = Reload Base Address for 1X blocks  (def) (reload each time)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_DBL_BUF_SHIFT                    _MK_SHIFT_CONST(19)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_DBL_BUF_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_7_AHB_SEQ_0_DBL_BUF_SHIFT)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_DBL_BUF_RANGE                    19:19
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_DBL_BUF_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_DBL_BUF_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_DBL_BUF_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_DBL_BUF_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_DBL_BUF_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_DBL_BUF_RELOAD_FOR_1X_BLOCKS                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_DBL_BUF_RELOAD_FOR_2X_BLOCKS                     _MK_ENUM_CONST(1)
+
+// AHB Address Wrap: AHB Address wrap-around window 0=No Wrap (default) 5=Wrap on 512 word window 1=Wrap on 32 word window 6=Wrap on 1024 word window 2=Wrap on 64 word window 7=Wrap on 2048 word window 3=Wrap on 128 word window 4=Wrap on 256 word window
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_WRAP_SHIFT                       _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_WRAP_FIELD                       (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_7_AHB_SEQ_0_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_WRAP_RANGE                       18:16
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_WRAP_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_WRAP_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_WRAP_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_WRAP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_WRAP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_WRAP_NO_WRAP                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_WRAP_WRAP_0N_32WORDS                     _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_WRAP_WRAP_ON_64WORDS                     _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_WRAP_WRAP_ON_128WORDS                    _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_WRAP_WRAP_ON_256WORDS                    _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_WRAP_WRAP_ON_512WORDS                    _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_WRAP_WRAP_ON_1024WORDS                   _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_WRAP_WRAP_ON_2048WORDS                   _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_7_APB_PTR_0  
+#define APBDMACHAN_CHANNEL_7_APB_PTR_0                  _MK_ADDR_CONST(0xf8)
+#define APBDMACHAN_CHANNEL_7_APB_PTR_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_7_APB_PTR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_APB_PTR_0_RESET_MASK                       _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_7_APB_PTR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_APB_PTR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_APB_PTR_0_READ_MASK                        _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_7_APB_PTR_0_WRITE_MASK                       _MK_MASK_CONST(0xfffc)
+// APB-DMA Starting address for APB Bus: APB Base address:Upper 16 bits are fixed at 0x7000:XXXX
+#define APBDMACHAN_CHANNEL_7_APB_PTR_0_APB_BASE_SHIFT                   _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_7_APB_PTR_0_APB_BASE_FIELD                   (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_7_APB_PTR_0_APB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_7_APB_PTR_0_APB_BASE_RANGE                   15:2
+#define APBDMACHAN_CHANNEL_7_APB_PTR_0_APB_BASE_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_7_APB_PTR_0_APB_BASE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_APB_PTR_0_APB_BASE_DEFAULT_MASK                    _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_7_APB_PTR_0_APB_BASE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_APB_PTR_0_APB_BASE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_7_APB_SEQ_0  
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0                  _MK_ADDR_CONST(0xfc)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_RESET_VAL                        _MK_MASK_CONST(0x20010000)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_RESET_MASK                       _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_READ_MASK                        _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_WRITE_MASK                       _MK_MASK_CONST(0x78070000)
+// 0 = 8 bit Bus 1 = 16 bit Bus 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD) 4 = 128 bit BUS (RSVD)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_BUS_WIDTH_SHIFT                      _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_BUS_WIDTH_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_BUS_WIDTH_RANGE                      30:28
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_BUS_WIDTH_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT                    _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_8                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_16                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_32                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_64                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_128                      _MK_ENUM_CONST(4)
+
+// when enabled the data going  to APB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }.
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_DATA_SWAP_SHIFT                      _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_DATA_SWAP_FIELD                      (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_DATA_SWAP_RANGE                      27:27
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_DATA_SWAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_DATA_SWAP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_DATA_SWAP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_DATA_SWAP_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_DATA_SWAP_ENABLE                     _MK_ENUM_CONST(1)
+
+//APB Address Wrap-around Window 0 = No Wrap 1 = Wrap on 1 Word Window (def) 2 = Wrap on 2 Word Window 3 = Wrap on 4 Word Window 4 = Wrap on 8 Word Window 5 = Wrap on 16 Word Window 6 = Wrap on 32 Word Window 7 = Wrap on 64 Word Window (rsvd)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_ADDR_WRAP_SHIFT                      _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_ADDR_WRAP_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_ADDR_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_ADDR_WRAP_RANGE                      18:16
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_ADDR_WRAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_ADDR_WRAP_NO_WRAP                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_ADDR_WRAP_WRAP_0N_1WORDS                     _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_2WORDS                     _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_4WORDS                     _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_8WORDS                     _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_16WORDS                    _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_32WORDS                    _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_64WORDS                    _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_8_CSR_0  
+#define APBDMACHAN_CHANNEL_8_CSR_0                      _MK_ADDR_CONST(0x100)
+#define APBDMACHAN_CHANNEL_8_CSR_0_WORD_COUNT                   0x1
+#define APBDMACHAN_CHANNEL_8_CSR_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_RESET_MASK                   _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_8_CSR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_READ_MASK                    _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_8_CSR_0_WRITE_MASK                   _MK_MASK_CONST(0xfffffffc)
+// Enables DMA channel transfer 
+#define APBDMACHAN_CHANNEL_8_CSR_0_ENB_SHIFT                    _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_8_CSR_0_ENB_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_8_CSR_0_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_8_CSR_0_ENB_RANGE                    31:31
+#define APBDMACHAN_CHANNEL_8_CSR_0_ENB_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_8_CSR_0_ENB_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_ENB_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_8_CSR_0_ENB_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_ENB_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_ENB_DISABLE                  _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_ENB_ENABLE                   _MK_ENUM_CONST(1)
+
+// Interrupts when DMA Block Transfer Completes 
+#define APBDMACHAN_CHANNEL_8_CSR_0_IE_EOC_SHIFT                 _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_8_CSR_0_IE_EOC_FIELD                 (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_8_CSR_0_IE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_8_CSR_0_IE_EOC_RANGE                 30:30
+#define APBDMACHAN_CHANNEL_8_CSR_0_IE_EOC_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_8_CSR_0_IE_EOC_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_IE_EOC_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_8_CSR_0_IE_EOC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_IE_EOC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_IE_EOC_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_IE_EOC_ENABLE                        _MK_ENUM_CONST(1)
+
+// Holds this Processor until DMA Block Transfer Completes
+#define APBDMACHAN_CHANNEL_8_CSR_0_HOLD_SHIFT                   _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_8_CSR_0_HOLD_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_8_CSR_0_HOLD_SHIFT)
+#define APBDMACHAN_CHANNEL_8_CSR_0_HOLD_RANGE                   29:29
+#define APBDMACHAN_CHANNEL_8_CSR_0_HOLD_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_8_CSR_0_HOLD_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_HOLD_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_8_CSR_0_HOLD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_HOLD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_HOLD_DISABLE                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_HOLD_ENABLE                  _MK_ENUM_CONST(1)
+
+// DMA Transfer Direction 1 = AHB read to APB write 0 = APB read to AHB write
+#define APBDMACHAN_CHANNEL_8_CSR_0_DIR_SHIFT                    _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_8_CSR_0_DIR_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_8_CSR_0_DIR_SHIFT)
+#define APBDMACHAN_CHANNEL_8_CSR_0_DIR_RANGE                    28:28
+#define APBDMACHAN_CHANNEL_8_CSR_0_DIR_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_8_CSR_0_DIR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_DIR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_8_CSR_0_DIR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_DIR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_DIR_AHB_WRITE                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_DIR_AHB_READ                 _MK_ENUM_CONST(1)
+
+// Run Once or Run Multiple Mode (Allow Retriggering of this Channel) 1 = Run for One Block Transfer 0 = Run for Multiple Block Transfer
+#define APBDMACHAN_CHANNEL_8_CSR_0_ONCE_SHIFT                   _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_8_CSR_0_ONCE_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_8_CSR_0_ONCE_SHIFT)
+#define APBDMACHAN_CHANNEL_8_CSR_0_ONCE_RANGE                   27:27
+#define APBDMACHAN_CHANNEL_8_CSR_0_ONCE_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_8_CSR_0_ONCE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_ONCE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_8_CSR_0_ONCE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_ONCE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_ONCE_MULTIPLE_BLOCK                  _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_ONCE_SINGLE_BLOCK                    _MK_ENUM_CONST(1)
+
+// Enable on Non-Zero Value
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_SHIFT                       _MK_SHIFT_CONST(22)
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_FIELD                       (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_RANGE                       26:22
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_NA1                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_SMP24                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_SMP25                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_SMP26                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_SMP27                       _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_XRQ_A                       _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_XRQ_B                       _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_TMR1                        _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_TMR2                        _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_APB_0                       _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_APB_1                       _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_APB_2                       _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_APB_3                       _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_APB_4                       _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_APB_5                       _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_APB_6                       _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_APB_7                       _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_APB_8                       _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_APB_9                       _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_APB_10                      _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_APB_11                      _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_APB_12                      _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_APB_13                      _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_APB_14                      _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_APB_15                      _MK_ENUM_CONST(24)
+
+// Flow Control Enable (Synchronize Burst Transfers) 1 = Link to DRQ source 0 = Independent of DRQ request
+#define APBDMACHAN_CHANNEL_8_CSR_0_FLOW_SHIFT                   _MK_SHIFT_CONST(21)
+#define APBDMACHAN_CHANNEL_8_CSR_0_FLOW_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_8_CSR_0_FLOW_SHIFT)
+#define APBDMACHAN_CHANNEL_8_CSR_0_FLOW_RANGE                   21:21
+#define APBDMACHAN_CHANNEL_8_CSR_0_FLOW_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_8_CSR_0_FLOW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_FLOW_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_8_CSR_0_FLOW_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_FLOW_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_FLOW_DISABLE                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_FLOW_ENABLE                  _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_SHIFT                        _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_FIELD                        (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_RANGE                        20:16
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_CNTR_REQ                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_I2S_2                        _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_I2S_1                        _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_SPD_I                        _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_UI_I                 _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_MIPI                 _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_I2S2_2                       _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_I2S2_1                       _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_UART_A                       _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_UART_B                       _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_UART_C                       _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_SPI                  _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_AC97                 _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_ACModem                      _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_SL4B                 _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_SL2B1                        _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_SL2B2                        _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_SL2B3                        _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_NA18                 _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_NA19                 _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_NA20                 _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_NA21                 _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_NA22                 _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_NA23                 _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_NA24                 _MK_ENUM_CONST(24)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_NA25                 _MK_ENUM_CONST(25)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_NA26                 _MK_ENUM_CONST(26)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_NA27                 _MK_ENUM_CONST(27)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_NA28                 _MK_ENUM_CONST(28)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_NA29                 _MK_ENUM_CONST(29)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_NA30                 _MK_ENUM_CONST(30)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_NA31                 _MK_ENUM_CONST(31)
+
+// Number of 32bit word cycles
+#define APBDMACHAN_CHANNEL_8_CSR_0_WCOUNT_SHIFT                 _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_8_CSR_0_WCOUNT_FIELD                 (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_8_CSR_0_WCOUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_8_CSR_0_WCOUNT_RANGE                 15:2
+#define APBDMACHAN_CHANNEL_8_CSR_0_WCOUNT_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_8_CSR_0_WCOUNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_WCOUNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_8_CSR_0_WCOUNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_WCOUNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_8_STA_0  
+#define APBDMACHAN_CHANNEL_8_STA_0                      _MK_ADDR_CONST(0x104)
+#define APBDMACHAN_CHANNEL_8_STA_0_WORD_COUNT                   0x1
+#define APBDMACHAN_CHANNEL_8_STA_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_STA_0_RESET_MASK                   _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_8_STA_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_STA_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_STA_0_READ_MASK                    _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_8_STA_0_WRITE_MASK                   _MK_MASK_CONST(0x40000000)
+// indicate DMA Channel Status activate or not
+#define APBDMACHAN_CHANNEL_8_STA_0_BSY_SHIFT                    _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_8_STA_0_BSY_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_8_STA_0_BSY_SHIFT)
+#define APBDMACHAN_CHANNEL_8_STA_0_BSY_RANGE                    31:31
+#define APBDMACHAN_CHANNEL_8_STA_0_BSY_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_8_STA_0_BSY_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_STA_0_BSY_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_8_STA_0_BSY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_STA_0_BSY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_STA_0_BSY_WAIT                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_8_STA_0_BSY_ACTIVE                   _MK_ENUM_CONST(1)
+
+//  Write '1' to clear the flag
+#define APBDMACHAN_CHANNEL_8_STA_0_ISE_EOC_SHIFT                        _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_8_STA_0_ISE_EOC_FIELD                        (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_8_STA_0_ISE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_8_STA_0_ISE_EOC_RANGE                        30:30
+#define APBDMACHAN_CHANNEL_8_STA_0_ISE_EOC_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_8_STA_0_ISE_EOC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_STA_0_ISE_EOC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_8_STA_0_ISE_EOC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_STA_0_ISE_EOC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_STA_0_ISE_EOC_NO_INTR                      _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_8_STA_0_ISE_EOC_INTR                 _MK_ENUM_CONST(1)
+
+// Holding Status of Processor 
+#define APBDMACHAN_CHANNEL_8_STA_0_HALT_SHIFT                   _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_8_STA_0_HALT_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_8_STA_0_HALT_SHIFT)
+#define APBDMACHAN_CHANNEL_8_STA_0_HALT_RANGE                   29:29
+#define APBDMACHAN_CHANNEL_8_STA_0_HALT_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_8_STA_0_HALT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_STA_0_HALT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_8_STA_0_HALT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_STA_0_HALT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_STA_0_HALT_NO_HALT                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_8_STA_0_HALT_HALT                    _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_8_STA_0_PING_PONG_STA_SHIFT                  _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_8_STA_0_PING_PONG_STA_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_8_STA_0_PING_PONG_STA_SHIFT)
+#define APBDMACHAN_CHANNEL_8_STA_0_PING_PONG_STA_RANGE                  28:28
+#define APBDMACHAN_CHANNEL_8_STA_0_PING_PONG_STA_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_8_STA_0_PING_PONG_STA_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_STA_0_PING_PONG_STA_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_8_STA_0_PING_PONG_STA_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_STA_0_PING_PONG_STA_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_STA_0_PING_PONG_STA_PING_INTR_STA                  _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_8_STA_0_PING_PONG_STA_PONG_INTR_STA                  _MK_ENUM_CONST(1)
+
+// Current 32bit word cycles Flags set /cleared by HW
+#define APBDMACHAN_CHANNEL_8_STA_0_COUNT_SHIFT                  _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_8_STA_0_COUNT_FIELD                  (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_8_STA_0_COUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_8_STA_0_COUNT_RANGE                  15:2
+#define APBDMACHAN_CHANNEL_8_STA_0_COUNT_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_8_STA_0_COUNT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_STA_0_COUNT_DEFAULT_MASK                   _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_8_STA_0_COUNT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_STA_0_COUNT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Reserved address 264 [0x108] 
+
+// Reserved address 268 [0x10c] 
+
+// Register APBDMACHAN_CHANNEL_8_AHB_PTR_0  
+#define APBDMACHAN_CHANNEL_8_AHB_PTR_0                  _MK_ADDR_CONST(0x110)
+#define APBDMACHAN_CHANNEL_8_AHB_PTR_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_8_AHB_PTR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_AHB_PTR_0_RESET_MASK                       _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_8_AHB_PTR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_AHB_PTR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_AHB_PTR_0_READ_MASK                        _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_8_AHB_PTR_0_WRITE_MASK                       _MK_MASK_CONST(0xfffffffc)
+// APB-DMA Starting Address for AHB Bus: SW writes to  modify
+#define APBDMACHAN_CHANNEL_8_AHB_PTR_0_AHB_BASE_SHIFT                   _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_8_AHB_PTR_0_AHB_BASE_FIELD                   (_MK_MASK_CONST(0x3fffffff) << APBDMACHAN_CHANNEL_8_AHB_PTR_0_AHB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_8_AHB_PTR_0_AHB_BASE_RANGE                   31:2
+#define APBDMACHAN_CHANNEL_8_AHB_PTR_0_AHB_BASE_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_8_AHB_PTR_0_AHB_BASE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_AHB_PTR_0_AHB_BASE_DEFAULT_MASK                    _MK_MASK_CONST(0x3fffffff)
+#define APBDMACHAN_CHANNEL_8_AHB_PTR_0_AHB_BASE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_AHB_PTR_0_AHB_BASE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_8_AHB_SEQ_0  
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0                  _MK_ADDR_CONST(0x114)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_RESET_VAL                        _MK_MASK_CONST(0x22000000)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_RESET_MASK                       _MK_MASK_CONST(0xff0f0000)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_READ_MASK                        _MK_MASK_CONST(0xff0f0000)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_WRITE_MASK                       _MK_MASK_CONST(0xff0f0000)
+//  0 = send interrupt to COP
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_INTR_ENB_SHIFT                   _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_INTR_ENB_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_8_AHB_SEQ_0_INTR_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_INTR_ENB_RANGE                   31:31
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_INTR_ENB_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_INTR_ENB_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_INTR_ENB_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_INTR_ENB_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_INTR_ENB_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_INTR_ENB_CPU                     _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_INTR_ENB_COP                     _MK_ENUM_CONST(0)
+
+// AHB Bus Width 0 = 8 bit Bus (RSVD) 1 = 16 bit Bus (RSVD) 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD)4 = 128 bit Bus (RSVD)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT                      _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_BUS_WIDTH_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_BUS_WIDTH_RANGE                      30:28
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_BUS_WIDTH_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT                    _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_8                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_16                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_32                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_64                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_128                      _MK_ENUM_CONST(4)
+
+// When enabled the data going  to AHB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }.
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT                      _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_DATA_SWAP_FIELD                      (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_DATA_SWAP_RANGE                      27:27
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_DATA_SWAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_DATA_SWAP_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_DATA_SWAP_ENABLE                     _MK_ENUM_CONST(1)
+
+// AHB Burst Size DMA Burst Length (encoded) 4 = 1 Word (1x32bits) 5 = 4 Words (4x32bits)else = 8 Words (8x32bits) default
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_BURST_SHIFT                  _MK_SHIFT_CONST(24)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_BURST_FIELD                  (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_BURST_SHIFT)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_BURST_RANGE                  26:24
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_BURST_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_BURST_DEFAULT                        _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_BURST_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_BURST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_BURST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_BURST_DMA_BURST_1WORDS                       _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_BURST_DMA_BURST_4WORDS                       _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_BURST_DMA_BURST_8WORDS                       _MK_ENUM_CONST(6)
+
+// 2X Double Buffering Mode (For Run-Multiple Mode with No Wrap Operations) 1 = Reload Base Address for 2X blocks (reload every other time) 0 = Reload Base Address for 1X blocks  (def) (reload each time)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_DBL_BUF_SHIFT                    _MK_SHIFT_CONST(19)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_DBL_BUF_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_8_AHB_SEQ_0_DBL_BUF_SHIFT)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_DBL_BUF_RANGE                    19:19
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_DBL_BUF_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_DBL_BUF_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_DBL_BUF_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_DBL_BUF_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_DBL_BUF_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_DBL_BUF_RELOAD_FOR_1X_BLOCKS                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_DBL_BUF_RELOAD_FOR_2X_BLOCKS                     _MK_ENUM_CONST(1)
+
+// AHB Address Wrap: AHB Address wrap-around window 0=No Wrap (default) 5=Wrap on 512 word window 1=Wrap on 32 word window 6=Wrap on 1024 word window 2=Wrap on 64 word window 7=Wrap on 2048 word window 3=Wrap on 128 word window 4=Wrap on 256 word window
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_WRAP_SHIFT                       _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_WRAP_FIELD                       (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_8_AHB_SEQ_0_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_WRAP_RANGE                       18:16
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_WRAP_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_WRAP_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_WRAP_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_WRAP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_WRAP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_WRAP_NO_WRAP                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_WRAP_WRAP_0N_32WORDS                     _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_WRAP_WRAP_ON_64WORDS                     _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_WRAP_WRAP_ON_128WORDS                    _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_WRAP_WRAP_ON_256WORDS                    _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_WRAP_WRAP_ON_512WORDS                    _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_WRAP_WRAP_ON_1024WORDS                   _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_WRAP_WRAP_ON_2048WORDS                   _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_8_APB_PTR_0  
+#define APBDMACHAN_CHANNEL_8_APB_PTR_0                  _MK_ADDR_CONST(0x118)
+#define APBDMACHAN_CHANNEL_8_APB_PTR_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_8_APB_PTR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_APB_PTR_0_RESET_MASK                       _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_8_APB_PTR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_APB_PTR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_APB_PTR_0_READ_MASK                        _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_8_APB_PTR_0_WRITE_MASK                       _MK_MASK_CONST(0xfffc)
+// APB-DMA Starting address for APB Bus: APB Base address:Upper 16 bits are fixed at 0x7000:XXXX
+#define APBDMACHAN_CHANNEL_8_APB_PTR_0_APB_BASE_SHIFT                   _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_8_APB_PTR_0_APB_BASE_FIELD                   (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_8_APB_PTR_0_APB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_8_APB_PTR_0_APB_BASE_RANGE                   15:2
+#define APBDMACHAN_CHANNEL_8_APB_PTR_0_APB_BASE_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_8_APB_PTR_0_APB_BASE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_APB_PTR_0_APB_BASE_DEFAULT_MASK                    _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_8_APB_PTR_0_APB_BASE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_APB_PTR_0_APB_BASE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_8_APB_SEQ_0  
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0                  _MK_ADDR_CONST(0x11c)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_RESET_VAL                        _MK_MASK_CONST(0x20010000)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_RESET_MASK                       _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_READ_MASK                        _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_WRITE_MASK                       _MK_MASK_CONST(0x78070000)
+// 0 = 8 bit Bus 1 = 16 bit Bus 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD) 4 = 128 bit BUS (RSVD)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_BUS_WIDTH_SHIFT                      _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_BUS_WIDTH_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_BUS_WIDTH_RANGE                      30:28
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_BUS_WIDTH_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT                    _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_8                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_16                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_32                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_64                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_128                      _MK_ENUM_CONST(4)
+
+// when enabled the data going  to APB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }.
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_DATA_SWAP_SHIFT                      _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_DATA_SWAP_FIELD                      (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_DATA_SWAP_RANGE                      27:27
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_DATA_SWAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_DATA_SWAP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_DATA_SWAP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_DATA_SWAP_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_DATA_SWAP_ENABLE                     _MK_ENUM_CONST(1)
+
+//APB Address Wrap-around Window 0 = No Wrap 1 = Wrap on 1 Word Window (def) 2 = Wrap on 2 Word Window 3 = Wrap on 4 Word Window 4 = Wrap on 8 Word Window 5 = Wrap on 16 Word Window 6 = Wrap on 32 Word Window 7 = Wrap on 64 Word Window (rsvd)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_ADDR_WRAP_SHIFT                      _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_ADDR_WRAP_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_ADDR_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_ADDR_WRAP_RANGE                      18:16
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_ADDR_WRAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_ADDR_WRAP_NO_WRAP                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_ADDR_WRAP_WRAP_0N_1WORDS                     _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_2WORDS                     _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_4WORDS                     _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_8WORDS                     _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_16WORDS                    _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_32WORDS                    _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_64WORDS                    _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_9_CSR_0  
+#define APBDMACHAN_CHANNEL_9_CSR_0                      _MK_ADDR_CONST(0x120)
+#define APBDMACHAN_CHANNEL_9_CSR_0_WORD_COUNT                   0x1
+#define APBDMACHAN_CHANNEL_9_CSR_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_RESET_MASK                   _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_9_CSR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_READ_MASK                    _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_9_CSR_0_WRITE_MASK                   _MK_MASK_CONST(0xfffffffc)
+// Enables DMA channel transfer 
+#define APBDMACHAN_CHANNEL_9_CSR_0_ENB_SHIFT                    _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_9_CSR_0_ENB_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_9_CSR_0_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_9_CSR_0_ENB_RANGE                    31:31
+#define APBDMACHAN_CHANNEL_9_CSR_0_ENB_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_9_CSR_0_ENB_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_ENB_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_9_CSR_0_ENB_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_ENB_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_ENB_DISABLE                  _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_ENB_ENABLE                   _MK_ENUM_CONST(1)
+
+// Interrupts when DMA Block Transfer Completes 
+#define APBDMACHAN_CHANNEL_9_CSR_0_IE_EOC_SHIFT                 _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_9_CSR_0_IE_EOC_FIELD                 (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_9_CSR_0_IE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_9_CSR_0_IE_EOC_RANGE                 30:30
+#define APBDMACHAN_CHANNEL_9_CSR_0_IE_EOC_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_9_CSR_0_IE_EOC_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_IE_EOC_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_9_CSR_0_IE_EOC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_IE_EOC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_IE_EOC_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_IE_EOC_ENABLE                        _MK_ENUM_CONST(1)
+
+// Holds this Processor until DMA Block Transfer Completes 
+#define APBDMACHAN_CHANNEL_9_CSR_0_HOLD_SHIFT                   _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_9_CSR_0_HOLD_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_9_CSR_0_HOLD_SHIFT)
+#define APBDMACHAN_CHANNEL_9_CSR_0_HOLD_RANGE                   29:29
+#define APBDMACHAN_CHANNEL_9_CSR_0_HOLD_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_9_CSR_0_HOLD_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_HOLD_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_9_CSR_0_HOLD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_HOLD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_HOLD_DISABLE                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_HOLD_ENABLE                  _MK_ENUM_CONST(1)
+
+// DMA Transfer Direction 1 = AHB read to APB write 0 = APB read to AHB write
+#define APBDMACHAN_CHANNEL_9_CSR_0_DIR_SHIFT                    _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_9_CSR_0_DIR_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_9_CSR_0_DIR_SHIFT)
+#define APBDMACHAN_CHANNEL_9_CSR_0_DIR_RANGE                    28:28
+#define APBDMACHAN_CHANNEL_9_CSR_0_DIR_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_9_CSR_0_DIR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_DIR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_9_CSR_0_DIR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_DIR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_DIR_AHB_WRITE                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_DIR_AHB_READ                 _MK_ENUM_CONST(1)
+
+// Run Once or Run Multiple Mode (Allow Retriggering of this Channel) 1 = Run for One Block Transfer 0 = Run for Multiple Block Transfer
+#define APBDMACHAN_CHANNEL_9_CSR_0_ONCE_SHIFT                   _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_9_CSR_0_ONCE_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_9_CSR_0_ONCE_SHIFT)
+#define APBDMACHAN_CHANNEL_9_CSR_0_ONCE_RANGE                   27:27
+#define APBDMACHAN_CHANNEL_9_CSR_0_ONCE_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_9_CSR_0_ONCE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_ONCE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_9_CSR_0_ONCE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_ONCE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_ONCE_MULTIPLE_BLOCK                  _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_ONCE_SINGLE_BLOCK                    _MK_ENUM_CONST(1)
+
+// Enable on Non-Zero Value
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_SHIFT                       _MK_SHIFT_CONST(22)
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_FIELD                       (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_RANGE                       26:22
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_NA1                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_SMP24                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_SMP25                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_SMP26                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_SMP27                       _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_XRQ_A                       _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_XRQ_B                       _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_TMR1                        _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_TMR2                        _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_APB_0                       _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_APB_1                       _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_APB_2                       _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_APB_3                       _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_APB_4                       _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_APB_5                       _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_APB_6                       _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_APB_7                       _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_APB_8                       _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_APB_9                       _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_APB_10                      _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_APB_11                      _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_APB_12                      _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_APB_13                      _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_APB_14                      _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_APB_15                      _MK_ENUM_CONST(24)
+
+// Flow Control Enable (Synchronize Burst Transfers) 1 = Link to DRQ source 0 = Independent of DRQ request
+#define APBDMACHAN_CHANNEL_9_CSR_0_FLOW_SHIFT                   _MK_SHIFT_CONST(21)
+#define APBDMACHAN_CHANNEL_9_CSR_0_FLOW_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_9_CSR_0_FLOW_SHIFT)
+#define APBDMACHAN_CHANNEL_9_CSR_0_FLOW_RANGE                   21:21
+#define APBDMACHAN_CHANNEL_9_CSR_0_FLOW_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_9_CSR_0_FLOW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_FLOW_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_9_CSR_0_FLOW_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_FLOW_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_FLOW_DISABLE                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_FLOW_ENABLE                  _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_SHIFT                        _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_FIELD                        (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_RANGE                        20:16
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_CNTR_REQ                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_I2S_2                        _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_I2S_1                        _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_SPD_I                        _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_UI_I                 _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_MIPI                 _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_I2S2_2                       _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_I2S2_1                       _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_UART_A                       _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_UART_B                       _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_UART_C                       _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_SPI                  _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_AC97                 _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_ACModem                      _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_SL4B                 _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_SL2B1                        _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_SL2B2                        _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_SL2B3                        _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_NA18                 _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_NA19                 _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_NA20                 _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_NA21                 _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_NA22                 _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_NA23                 _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_NA24                 _MK_ENUM_CONST(24)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_NA25                 _MK_ENUM_CONST(25)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_NA26                 _MK_ENUM_CONST(26)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_NA27                 _MK_ENUM_CONST(27)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_NA28                 _MK_ENUM_CONST(28)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_NA29                 _MK_ENUM_CONST(29)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_NA30                 _MK_ENUM_CONST(30)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_NA31                 _MK_ENUM_CONST(31)
+
+// Number of 32bit word cycles
+#define APBDMACHAN_CHANNEL_9_CSR_0_WCOUNT_SHIFT                 _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_9_CSR_0_WCOUNT_FIELD                 (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_9_CSR_0_WCOUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_9_CSR_0_WCOUNT_RANGE                 15:2
+#define APBDMACHAN_CHANNEL_9_CSR_0_WCOUNT_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_9_CSR_0_WCOUNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_WCOUNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_9_CSR_0_WCOUNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_WCOUNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_9_STA_0  
+#define APBDMACHAN_CHANNEL_9_STA_0                      _MK_ADDR_CONST(0x124)
+#define APBDMACHAN_CHANNEL_9_STA_0_WORD_COUNT                   0x1
+#define APBDMACHAN_CHANNEL_9_STA_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_STA_0_RESET_MASK                   _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_9_STA_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_STA_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_STA_0_READ_MASK                    _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_9_STA_0_WRITE_MASK                   _MK_MASK_CONST(0x40000000)
+// indicate DMA Channel Status activate or not
+#define APBDMACHAN_CHANNEL_9_STA_0_BSY_SHIFT                    _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_9_STA_0_BSY_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_9_STA_0_BSY_SHIFT)
+#define APBDMACHAN_CHANNEL_9_STA_0_BSY_RANGE                    31:31
+#define APBDMACHAN_CHANNEL_9_STA_0_BSY_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_9_STA_0_BSY_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_STA_0_BSY_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_9_STA_0_BSY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_STA_0_BSY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_STA_0_BSY_WAIT                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_9_STA_0_BSY_ACTIVE                   _MK_ENUM_CONST(1)
+
+//  Write '1' to clear the flag
+#define APBDMACHAN_CHANNEL_9_STA_0_ISE_EOC_SHIFT                        _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_9_STA_0_ISE_EOC_FIELD                        (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_9_STA_0_ISE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_9_STA_0_ISE_EOC_RANGE                        30:30
+#define APBDMACHAN_CHANNEL_9_STA_0_ISE_EOC_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_9_STA_0_ISE_EOC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_STA_0_ISE_EOC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_9_STA_0_ISE_EOC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_STA_0_ISE_EOC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_STA_0_ISE_EOC_NO_INTR                      _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_9_STA_0_ISE_EOC_INTR                 _MK_ENUM_CONST(1)
+
+// Holding Status of Processor 
+#define APBDMACHAN_CHANNEL_9_STA_0_HALT_SHIFT                   _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_9_STA_0_HALT_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_9_STA_0_HALT_SHIFT)
+#define APBDMACHAN_CHANNEL_9_STA_0_HALT_RANGE                   29:29
+#define APBDMACHAN_CHANNEL_9_STA_0_HALT_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_9_STA_0_HALT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_STA_0_HALT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_9_STA_0_HALT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_STA_0_HALT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_STA_0_HALT_NO_HALT                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_9_STA_0_HALT_HALT                    _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_9_STA_0_PING_PONG_STA_SHIFT                  _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_9_STA_0_PING_PONG_STA_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_9_STA_0_PING_PONG_STA_SHIFT)
+#define APBDMACHAN_CHANNEL_9_STA_0_PING_PONG_STA_RANGE                  28:28
+#define APBDMACHAN_CHANNEL_9_STA_0_PING_PONG_STA_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_9_STA_0_PING_PONG_STA_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_STA_0_PING_PONG_STA_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_9_STA_0_PING_PONG_STA_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_STA_0_PING_PONG_STA_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_STA_0_PING_PONG_STA_PING_INTR_STA                  _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_9_STA_0_PING_PONG_STA_PONG_INTR_STA                  _MK_ENUM_CONST(1)
+
+// Current 32bit word cycles Flags set /cleared by HW
+#define APBDMACHAN_CHANNEL_9_STA_0_COUNT_SHIFT                  _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_9_STA_0_COUNT_FIELD                  (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_9_STA_0_COUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_9_STA_0_COUNT_RANGE                  15:2
+#define APBDMACHAN_CHANNEL_9_STA_0_COUNT_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_9_STA_0_COUNT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_STA_0_COUNT_DEFAULT_MASK                   _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_9_STA_0_COUNT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_STA_0_COUNT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Reserved address 296 [0x128] 
+
+// Reserved address 300 [0x12c] 
+
+// Register APBDMACHAN_CHANNEL_9_AHB_PTR_0  
+#define APBDMACHAN_CHANNEL_9_AHB_PTR_0                  _MK_ADDR_CONST(0x130)
+#define APBDMACHAN_CHANNEL_9_AHB_PTR_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_9_AHB_PTR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_AHB_PTR_0_RESET_MASK                       _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_9_AHB_PTR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_AHB_PTR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_AHB_PTR_0_READ_MASK                        _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_9_AHB_PTR_0_WRITE_MASK                       _MK_MASK_CONST(0xfffffffc)
+// APB-DMA Starting Address for AHB Bus: SW writes to  modify
+#define APBDMACHAN_CHANNEL_9_AHB_PTR_0_AHB_BASE_SHIFT                   _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_9_AHB_PTR_0_AHB_BASE_FIELD                   (_MK_MASK_CONST(0x3fffffff) << APBDMACHAN_CHANNEL_9_AHB_PTR_0_AHB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_9_AHB_PTR_0_AHB_BASE_RANGE                   31:2
+#define APBDMACHAN_CHANNEL_9_AHB_PTR_0_AHB_BASE_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_9_AHB_PTR_0_AHB_BASE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_AHB_PTR_0_AHB_BASE_DEFAULT_MASK                    _MK_MASK_CONST(0x3fffffff)
+#define APBDMACHAN_CHANNEL_9_AHB_PTR_0_AHB_BASE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_AHB_PTR_0_AHB_BASE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_9_AHB_SEQ_0  
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0                  _MK_ADDR_CONST(0x134)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_RESET_VAL                        _MK_MASK_CONST(0x22000000)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_RESET_MASK                       _MK_MASK_CONST(0xff0f0000)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_READ_MASK                        _MK_MASK_CONST(0xff0f0000)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_WRITE_MASK                       _MK_MASK_CONST(0xff0f0000)
+//  0 = send interrupt to COP
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_INTR_ENB_SHIFT                   _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_INTR_ENB_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_9_AHB_SEQ_0_INTR_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_INTR_ENB_RANGE                   31:31
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_INTR_ENB_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_INTR_ENB_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_INTR_ENB_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_INTR_ENB_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_INTR_ENB_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_INTR_ENB_CPU                     _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_INTR_ENB_COP                     _MK_ENUM_CONST(0)
+
+// AHB Bus Width 0 = 8 bit Bus (RSVD) 1 = 16 bit Bus (RSVD) 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD)4 = 128 bit Bus (RSVD)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT                      _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_BUS_WIDTH_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_BUS_WIDTH_RANGE                      30:28
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_BUS_WIDTH_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT                    _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_8                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_16                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_32                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_64                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_128                      _MK_ENUM_CONST(4)
+
+//When enabled the data going to AHB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT                      _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_DATA_SWAP_FIELD                      (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_DATA_SWAP_RANGE                      27:27
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_DATA_SWAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_DATA_SWAP_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_DATA_SWAP_ENABLE                     _MK_ENUM_CONST(1)
+
+// AHB Burst Size DMA Burst Length (encoded) 4 = 1 Word (1x32bits) 5 = 4 Words (4x32bits)else = 8 Words (8x32bits) default
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_BURST_SHIFT                  _MK_SHIFT_CONST(24)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_BURST_FIELD                  (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_BURST_SHIFT)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_BURST_RANGE                  26:24
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_BURST_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_BURST_DEFAULT                        _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_BURST_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_BURST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_BURST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_BURST_DMA_BURST_1WORDS                       _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_BURST_DMA_BURST_4WORDS                       _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_BURST_DMA_BURST_8WORDS                       _MK_ENUM_CONST(6)
+
+// 2X Double Buffering Mode (For Run-Multiple Mode with No Wrap Operations) 1 = Reload Base Address for 2X blocks (reload every other time) 0 = Reload Base Address for 1X blocks  (def) (reload each time)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_DBL_BUF_SHIFT                    _MK_SHIFT_CONST(19)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_DBL_BUF_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_9_AHB_SEQ_0_DBL_BUF_SHIFT)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_DBL_BUF_RANGE                    19:19
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_DBL_BUF_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_DBL_BUF_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_DBL_BUF_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_DBL_BUF_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_DBL_BUF_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_DBL_BUF_RELOAD_FOR_1X_BLOCKS                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_DBL_BUF_RELOAD_FOR_2X_BLOCKS                     _MK_ENUM_CONST(1)
+
+// AHB Address Wrap: AHB Address wrap-around window 0=No Wrap (default) 5=Wrap on 512 word window 1=Wrap on 32 word window 6=Wrap on 1024 word window 2=Wrap on 64 word window 7=Wrap on 2048 word window 3=Wrap on 128 word window 4=Wrap on 256 word window
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_WRAP_SHIFT                       _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_WRAP_FIELD                       (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_9_AHB_SEQ_0_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_WRAP_RANGE                       18:16
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_WRAP_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_WRAP_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_WRAP_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_WRAP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_WRAP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_WRAP_NO_WRAP                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_WRAP_WRAP_0N_32WORDS                     _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_WRAP_WRAP_ON_64WORDS                     _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_WRAP_WRAP_ON_128WORDS                    _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_WRAP_WRAP_ON_256WORDS                    _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_WRAP_WRAP_ON_512WORDS                    _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_WRAP_WRAP_ON_1024WORDS                   _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_WRAP_WRAP_ON_2048WORDS                   _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_9_APB_PTR_0  
+#define APBDMACHAN_CHANNEL_9_APB_PTR_0                  _MK_ADDR_CONST(0x138)
+#define APBDMACHAN_CHANNEL_9_APB_PTR_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_9_APB_PTR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_APB_PTR_0_RESET_MASK                       _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_9_APB_PTR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_APB_PTR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_APB_PTR_0_READ_MASK                        _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_9_APB_PTR_0_WRITE_MASK                       _MK_MASK_CONST(0xfffc)
+//APB-DMA Starting address for APB Bus: APB Base address: Upper 16 bits are fixed at 0x7000:XXXX
+#define APBDMACHAN_CHANNEL_9_APB_PTR_0_APB_BASE_SHIFT                   _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_9_APB_PTR_0_APB_BASE_FIELD                   (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_9_APB_PTR_0_APB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_9_APB_PTR_0_APB_BASE_RANGE                   15:2
+#define APBDMACHAN_CHANNEL_9_APB_PTR_0_APB_BASE_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_9_APB_PTR_0_APB_BASE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_APB_PTR_0_APB_BASE_DEFAULT_MASK                    _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_9_APB_PTR_0_APB_BASE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_APB_PTR_0_APB_BASE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_9_APB_SEQ_0  
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0                  _MK_ADDR_CONST(0x13c)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_RESET_VAL                        _MK_MASK_CONST(0x20010000)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_RESET_MASK                       _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_READ_MASK                        _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_WRITE_MASK                       _MK_MASK_CONST(0x78070000)
+// 0 = 8 bit Bus 1 = 16 bit Bus 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD) 4 = 128 bit BUS (RSVD)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_BUS_WIDTH_SHIFT                      _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_BUS_WIDTH_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_BUS_WIDTH_RANGE                      30:28
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_BUS_WIDTH_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT                    _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_8                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_16                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_32                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_64                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_128                      _MK_ENUM_CONST(4)
+
+// When enabled the data going  to APB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_DATA_SWAP_SHIFT                      _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_DATA_SWAP_FIELD                      (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_DATA_SWAP_RANGE                      27:27
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_DATA_SWAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_DATA_SWAP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_DATA_SWAP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_DATA_SWAP_DISBALE                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_DATA_SWAP_ENABLE                     _MK_ENUM_CONST(1)
+
+//APB Address Wrap-around Window 0 = No Wrap 1 = Wrap on 1 Word Window (def) 2 = Wrap on 2 Word Window 3 = Wrap on 4 Word Window 4 = Wrap on 8 Word Window 5 = Wrap on 16 Word Window 6 = Wrap on 32 Word Window 7 = Wrap on 64 Word Window (rsvd)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_ADDR_WRAP_SHIFT                      _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_ADDR_WRAP_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_ADDR_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_ADDR_WRAP_RANGE                      18:16
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_ADDR_WRAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_ADDR_WRAP_NO_WRAP                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_ADDR_WRAP_WRAP_0N_1WORDS                     _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_2WORDS                     _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_4WORDS                     _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_8WORDS                     _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_16WORDS                    _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_32WORDS                    _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_64WORDS                    _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_10_CSR_0  
+#define APBDMACHAN_CHANNEL_10_CSR_0                     _MK_ADDR_CONST(0x140)
+#define APBDMACHAN_CHANNEL_10_CSR_0_WORD_COUNT                  0x1
+#define APBDMACHAN_CHANNEL_10_CSR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_RESET_MASK                  _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_10_CSR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_READ_MASK                   _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_10_CSR_0_WRITE_MASK                  _MK_MASK_CONST(0xfffffffc)
+// Enables DMA channel transfer 
+#define APBDMACHAN_CHANNEL_10_CSR_0_ENB_SHIFT                   _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_10_CSR_0_ENB_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_10_CSR_0_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_10_CSR_0_ENB_RANGE                   31:31
+#define APBDMACHAN_CHANNEL_10_CSR_0_ENB_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_10_CSR_0_ENB_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_ENB_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_10_CSR_0_ENB_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_ENB_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_ENB_DISABLE                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_ENB_ENABLE                  _MK_ENUM_CONST(1)
+
+// Interrupts when DMA Block Transfer Completes
+#define APBDMACHAN_CHANNEL_10_CSR_0_IE_EOC_SHIFT                        _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_10_CSR_0_IE_EOC_FIELD                        (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_10_CSR_0_IE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_10_CSR_0_IE_EOC_RANGE                        30:30
+#define APBDMACHAN_CHANNEL_10_CSR_0_IE_EOC_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_10_CSR_0_IE_EOC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_IE_EOC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_10_CSR_0_IE_EOC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_IE_EOC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_IE_EOC_DISABLE                      _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_IE_EOC_ENABLE                       _MK_ENUM_CONST(1)
+
+// Holds this Processor until DMA Block Transfer Completes
+#define APBDMACHAN_CHANNEL_10_CSR_0_HOLD_SHIFT                  _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_10_CSR_0_HOLD_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_10_CSR_0_HOLD_SHIFT)
+#define APBDMACHAN_CHANNEL_10_CSR_0_HOLD_RANGE                  29:29
+#define APBDMACHAN_CHANNEL_10_CSR_0_HOLD_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_10_CSR_0_HOLD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_HOLD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_10_CSR_0_HOLD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_HOLD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_HOLD_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_HOLD_ENABLE                 _MK_ENUM_CONST(1)
+
+// DMA Transfer Direction 1 = AHB read to APB write 0 = APB read to AHB write
+#define APBDMACHAN_CHANNEL_10_CSR_0_DIR_SHIFT                   _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_10_CSR_0_DIR_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_10_CSR_0_DIR_SHIFT)
+#define APBDMACHAN_CHANNEL_10_CSR_0_DIR_RANGE                   28:28
+#define APBDMACHAN_CHANNEL_10_CSR_0_DIR_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_10_CSR_0_DIR_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_DIR_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_10_CSR_0_DIR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_DIR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_DIR_AHB_WRITE                       _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_DIR_AHB_READ                        _MK_ENUM_CONST(1)
+
+// Run Once or Run Multiple Mode (Allow Retriggering of this Channel) 1 = Run for One Block Transfer 0 = Run for Multiple Block Transfer
+#define APBDMACHAN_CHANNEL_10_CSR_0_ONCE_SHIFT                  _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_10_CSR_0_ONCE_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_10_CSR_0_ONCE_SHIFT)
+#define APBDMACHAN_CHANNEL_10_CSR_0_ONCE_RANGE                  27:27
+#define APBDMACHAN_CHANNEL_10_CSR_0_ONCE_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_10_CSR_0_ONCE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_ONCE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_10_CSR_0_ONCE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_ONCE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_ONCE_MULTIPLE_BLOCK                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_ONCE_SINGLE_BLOCK                   _MK_ENUM_CONST(1)
+
+// Enable on Non-Zero Value
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_SHIFT                      _MK_SHIFT_CONST(22)
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_FIELD                      (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_RANGE                      26:22
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_NA1                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_SMP24                      _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_SMP25                      _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_SMP26                      _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_SMP27                      _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_XRQ_A                      _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_XRQ_B                      _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_TMR1                       _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_TMR2                       _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_APB_0                      _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_APB_1                      _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_APB_2                      _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_APB_3                      _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_APB_4                      _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_APB_5                      _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_APB_6                      _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_APB_7                      _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_APB_8                      _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_APB_9                      _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_APB_10                     _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_APB_11                     _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_APB_12                     _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_APB_13                     _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_APB_14                     _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_APB_15                     _MK_ENUM_CONST(24)
+
+// Flow Control Enable (Synchronize Burst Transfers) 1 = Link to DRQ source 0 = Independent of DRQ request
+#define APBDMACHAN_CHANNEL_10_CSR_0_FLOW_SHIFT                  _MK_SHIFT_CONST(21)
+#define APBDMACHAN_CHANNEL_10_CSR_0_FLOW_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_10_CSR_0_FLOW_SHIFT)
+#define APBDMACHAN_CHANNEL_10_CSR_0_FLOW_RANGE                  21:21
+#define APBDMACHAN_CHANNEL_10_CSR_0_FLOW_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_10_CSR_0_FLOW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_FLOW_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_10_CSR_0_FLOW_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_FLOW_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_FLOW_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_FLOW_ENABLE                 _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_SHIFT                       _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_FIELD                       (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_RANGE                       20:16
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_CNTR_REQ                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_I2S_2                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_I2S_1                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_SPD_I                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_UI_I                        _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_MIPI                        _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_I2S2_2                      _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_I2S2_1                      _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_UART_A                      _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_UART_B                      _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_UART_C                      _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_SPI                 _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_AC97                        _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_ACModem                     _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_SL4B                        _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_SL2B1                       _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_SL2B2                       _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_SL2B3                       _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_NA18                        _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_NA19                        _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_NA20                        _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_NA21                        _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_NA22                        _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_NA23                        _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_NA24                        _MK_ENUM_CONST(24)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_NA25                        _MK_ENUM_CONST(25)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_NA26                        _MK_ENUM_CONST(26)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_NA27                        _MK_ENUM_CONST(27)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_NA28                        _MK_ENUM_CONST(28)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_NA29                        _MK_ENUM_CONST(29)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_NA30                        _MK_ENUM_CONST(30)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_NA31                        _MK_ENUM_CONST(31)
+
+// Number of 32bit word cycles
+#define APBDMACHAN_CHANNEL_10_CSR_0_WCOUNT_SHIFT                        _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_10_CSR_0_WCOUNT_FIELD                        (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_10_CSR_0_WCOUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_10_CSR_0_WCOUNT_RANGE                        15:2
+#define APBDMACHAN_CHANNEL_10_CSR_0_WCOUNT_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_10_CSR_0_WCOUNT_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_WCOUNT_DEFAULT_MASK                 _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_10_CSR_0_WCOUNT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_WCOUNT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_10_STA_0  
+#define APBDMACHAN_CHANNEL_10_STA_0                     _MK_ADDR_CONST(0x144)
+#define APBDMACHAN_CHANNEL_10_STA_0_WORD_COUNT                  0x1
+#define APBDMACHAN_CHANNEL_10_STA_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_STA_0_RESET_MASK                  _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_10_STA_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_STA_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_STA_0_READ_MASK                   _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_10_STA_0_WRITE_MASK                  _MK_MASK_CONST(0x40000000)
+// indicate DMA Channel Status activated or not 
+#define APBDMACHAN_CHANNEL_10_STA_0_BSY_SHIFT                   _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_10_STA_0_BSY_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_10_STA_0_BSY_SHIFT)
+#define APBDMACHAN_CHANNEL_10_STA_0_BSY_RANGE                   31:31
+#define APBDMACHAN_CHANNEL_10_STA_0_BSY_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_10_STA_0_BSY_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_STA_0_BSY_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_10_STA_0_BSY_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_STA_0_BSY_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_STA_0_BSY_WAIT                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_10_STA_0_BSY_ACTIVE                  _MK_ENUM_CONST(1)
+
+// Write '1' to clear the flag
+#define APBDMACHAN_CHANNEL_10_STA_0_ISE_EOC_SHIFT                       _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_10_STA_0_ISE_EOC_FIELD                       (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_10_STA_0_ISE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_10_STA_0_ISE_EOC_RANGE                       30:30
+#define APBDMACHAN_CHANNEL_10_STA_0_ISE_EOC_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_10_STA_0_ISE_EOC_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_STA_0_ISE_EOC_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_10_STA_0_ISE_EOC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_STA_0_ISE_EOC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_STA_0_ISE_EOC_NO_INTR                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_10_STA_0_ISE_EOC_INTR                        _MK_ENUM_CONST(1)
+
+// Holding Status of Processor 
+#define APBDMACHAN_CHANNEL_10_STA_0_HALT_SHIFT                  _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_10_STA_0_HALT_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_10_STA_0_HALT_SHIFT)
+#define APBDMACHAN_CHANNEL_10_STA_0_HALT_RANGE                  29:29
+#define APBDMACHAN_CHANNEL_10_STA_0_HALT_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_10_STA_0_HALT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_STA_0_HALT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_10_STA_0_HALT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_STA_0_HALT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_STA_0_HALT_NO_HALT                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_10_STA_0_HALT_HALT                   _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_10_STA_0_PING_PONG_STA_SHIFT                 _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_10_STA_0_PING_PONG_STA_FIELD                 (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_10_STA_0_PING_PONG_STA_SHIFT)
+#define APBDMACHAN_CHANNEL_10_STA_0_PING_PONG_STA_RANGE                 28:28
+#define APBDMACHAN_CHANNEL_10_STA_0_PING_PONG_STA_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_10_STA_0_PING_PONG_STA_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_STA_0_PING_PONG_STA_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_10_STA_0_PING_PONG_STA_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_STA_0_PING_PONG_STA_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_STA_0_PING_PONG_STA_PING_INTR_STA                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_10_STA_0_PING_PONG_STA_PONG_INTR_STA                 _MK_ENUM_CONST(1)
+
+// Current 32bit word cycles Flags set /cleared by HW
+#define APBDMACHAN_CHANNEL_10_STA_0_COUNT_SHIFT                 _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_10_STA_0_COUNT_FIELD                 (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_10_STA_0_COUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_10_STA_0_COUNT_RANGE                 15:2
+#define APBDMACHAN_CHANNEL_10_STA_0_COUNT_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_10_STA_0_COUNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_STA_0_COUNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_10_STA_0_COUNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_STA_0_COUNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Reserved address 328 [0x148] 
+
+// Reserved address 332 [0x14c] 
+
+// Register APBDMACHAN_CHANNEL_10_AHB_PTR_0  
+#define APBDMACHAN_CHANNEL_10_AHB_PTR_0                 _MK_ADDR_CONST(0x150)
+#define APBDMACHAN_CHANNEL_10_AHB_PTR_0_WORD_COUNT                      0x1
+#define APBDMACHAN_CHANNEL_10_AHB_PTR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_AHB_PTR_0_RESET_MASK                      _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_10_AHB_PTR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_AHB_PTR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_AHB_PTR_0_READ_MASK                       _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_10_AHB_PTR_0_WRITE_MASK                      _MK_MASK_CONST(0xfffffffc)
+// APB-DMA Starting Address for AHB Bus: SW writes to  modify
+#define APBDMACHAN_CHANNEL_10_AHB_PTR_0_AHB_BASE_SHIFT                  _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_10_AHB_PTR_0_AHB_BASE_FIELD                  (_MK_MASK_CONST(0x3fffffff) << APBDMACHAN_CHANNEL_10_AHB_PTR_0_AHB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_10_AHB_PTR_0_AHB_BASE_RANGE                  31:2
+#define APBDMACHAN_CHANNEL_10_AHB_PTR_0_AHB_BASE_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_10_AHB_PTR_0_AHB_BASE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_AHB_PTR_0_AHB_BASE_DEFAULT_MASK                   _MK_MASK_CONST(0x3fffffff)
+#define APBDMACHAN_CHANNEL_10_AHB_PTR_0_AHB_BASE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_AHB_PTR_0_AHB_BASE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_10_AHB_SEQ_0  
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0                 _MK_ADDR_CONST(0x154)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_WORD_COUNT                      0x1
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_RESET_VAL                       _MK_MASK_CONST(0x22000000)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_RESET_MASK                      _MK_MASK_CONST(0xff0f0000)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_READ_MASK                       _MK_MASK_CONST(0xff0f0000)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_WRITE_MASK                      _MK_MASK_CONST(0xff0f0000)
+//  0 = send interrupt to COP
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_INTR_ENB_SHIFT                  _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_INTR_ENB_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_10_AHB_SEQ_0_INTR_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_INTR_ENB_RANGE                  31:31
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_INTR_ENB_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_INTR_ENB_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_INTR_ENB_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_INTR_ENB_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_INTR_ENB_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_INTR_ENB_CPU                    _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_INTR_ENB_COP                    _MK_ENUM_CONST(0)
+
+// AHB Bus Width 0 = 8 bit Bus (RSVD) 1 = 16 bit Bus (RSVD) 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD)4 = 128 bit Bus (RSVD)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT                     _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_BUS_WIDTH_FIELD                     (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_BUS_WIDTH_RANGE                     30:28
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_BUS_WIDTH_WOFFSET                   0x0
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT                   _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_8                       _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_16                      _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_32                      _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_64                      _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_128                     _MK_ENUM_CONST(4)
+
+// when enabled the data going  to AHB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT                     _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_DATA_SWAP_FIELD                     (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_DATA_SWAP_RANGE                     27:27
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_DATA_SWAP_WOFFSET                   0x0
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_DATA_SWAP_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_DATA_SWAP_ENABLE                    _MK_ENUM_CONST(1)
+
+// AHB Burst Size DMA Burst Length (encoded) 4 = 1 Word (1x32bits) 5 = 4 Words (4x32bits)else = 8 Words (8x32bits) default
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_BURST_SHIFT                 _MK_SHIFT_CONST(24)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_BURST_FIELD                 (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_BURST_SHIFT)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_BURST_RANGE                 26:24
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_BURST_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_BURST_DEFAULT                       _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_BURST_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_BURST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_BURST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_BURST_DMA_BURST_1WORDS                      _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_BURST_DMA_BURST_4WORDS                      _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_BURST_DMA_BURST_8WORDS                      _MK_ENUM_CONST(6)
+
+// 2X Double Buffering Mode (For Run-Multiple Mode with No Wrap Operations) 1 = Reload Base Address for 2X blocks (reload every other time) 0 = Reload Base Address for 1X blocks  (def) (reload each time)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_DBL_BUF_SHIFT                   _MK_SHIFT_CONST(19)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_DBL_BUF_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_10_AHB_SEQ_0_DBL_BUF_SHIFT)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_DBL_BUF_RANGE                   19:19
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_DBL_BUF_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_DBL_BUF_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_DBL_BUF_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_DBL_BUF_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_DBL_BUF_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_DBL_BUF_RELOAD_FOR_1X_BLOCKS                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_DBL_BUF_RELOAD_FOR_2X_BLOCKS                    _MK_ENUM_CONST(1)
+
+// AHB Address Wrap: AHB Address wrap-around window 0=No Wrap (default) 5=Wrap on 512 word window 1=Wrap on 32 word window 6=Wrap on 1024 word window 2=Wrap on 64 word window 7=Wrap on 2048 word window 3=Wrap on 128 word window 4=Wrap on 256 word window
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_WRAP_SHIFT                      _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_WRAP_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_10_AHB_SEQ_0_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_WRAP_RANGE                      18:16
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_WRAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_WRAP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_WRAP_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_WRAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_WRAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_WRAP_NO_WRAP                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_WRAP_WRAP_0N_32WORDS                    _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_WRAP_WRAP_ON_64WORDS                    _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_WRAP_WRAP_ON_128WORDS                   _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_WRAP_WRAP_ON_256WORDS                   _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_WRAP_WRAP_ON_512WORDS                   _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_WRAP_WRAP_ON_1024WORDS                  _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_WRAP_WRAP_ON_2048WORDS                  _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_10_APB_PTR_0  
+#define APBDMACHAN_CHANNEL_10_APB_PTR_0                 _MK_ADDR_CONST(0x158)
+#define APBDMACHAN_CHANNEL_10_APB_PTR_0_WORD_COUNT                      0x1
+#define APBDMACHAN_CHANNEL_10_APB_PTR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_APB_PTR_0_RESET_MASK                      _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_10_APB_PTR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_APB_PTR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_APB_PTR_0_READ_MASK                       _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_10_APB_PTR_0_WRITE_MASK                      _MK_MASK_CONST(0xfffc)
+// APB-DMA Starting address for APB Bus: APB Base  address: Upper 16 bits are fixed at 0x7000:XXXX
+#define APBDMACHAN_CHANNEL_10_APB_PTR_0_APB_BASE_SHIFT                  _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_10_APB_PTR_0_APB_BASE_FIELD                  (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_10_APB_PTR_0_APB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_10_APB_PTR_0_APB_BASE_RANGE                  15:2
+#define APBDMACHAN_CHANNEL_10_APB_PTR_0_APB_BASE_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_10_APB_PTR_0_APB_BASE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_APB_PTR_0_APB_BASE_DEFAULT_MASK                   _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_10_APB_PTR_0_APB_BASE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_APB_PTR_0_APB_BASE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_10_APB_SEQ_0  
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0                 _MK_ADDR_CONST(0x15c)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_WORD_COUNT                      0x1
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_RESET_VAL                       _MK_MASK_CONST(0x20010000)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_RESET_MASK                      _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_READ_MASK                       _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_WRITE_MASK                      _MK_MASK_CONST(0x78070000)
+// 0 = 8 bit Bus 1 = 16 bit Bus 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD) 4 = 128 bit BUS (RSVD)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_BUS_WIDTH_SHIFT                     _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_BUS_WIDTH_FIELD                     (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_BUS_WIDTH_RANGE                     30:28
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_BUS_WIDTH_WOFFSET                   0x0
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT                   _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_8                       _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_16                      _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_32                      _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_64                      _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_128                     _MK_ENUM_CONST(4)
+
+// when enabled the data going  to APB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_DATA_SWAP_SHIFT                     _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_DATA_SWAP_FIELD                     (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_DATA_SWAP_RANGE                     27:27
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_DATA_SWAP_WOFFSET                   0x0
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_DATA_SWAP_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_DATA_SWAP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_DATA_SWAP_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_DATA_SWAP_ENABLE                    _MK_ENUM_CONST(1)
+
+//APB Address Wrap-around Window 0 = No Wrap 1 = Wrap on 1 Word Window (def) 2 = Wrap on 2 Word Window 3 = Wrap on 4 Word Window 4 = Wrap on 8 Word Window 5 = Wrap on 16 Word Window 6 = Wrap on 32 Word Window 7 = Wrap on 64 Word Window (rsvd)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_ADDR_WRAP_SHIFT                     _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_ADDR_WRAP_FIELD                     (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_ADDR_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_ADDR_WRAP_RANGE                     18:16
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_ADDR_WRAP_WOFFSET                   0x0
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_ADDR_WRAP_NO_WRAP                   _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_ADDR_WRAP_WRAP_0N_1WORDS                    _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_2WORDS                    _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_4WORDS                    _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_8WORDS                    _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_16WORDS                   _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_32WORDS                   _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_64WORDS                   _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_11_CSR_0  
+#define APBDMACHAN_CHANNEL_11_CSR_0                     _MK_ADDR_CONST(0x160)
+#define APBDMACHAN_CHANNEL_11_CSR_0_WORD_COUNT                  0x1
+#define APBDMACHAN_CHANNEL_11_CSR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_RESET_MASK                  _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_11_CSR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_READ_MASK                   _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_11_CSR_0_WRITE_MASK                  _MK_MASK_CONST(0xfffffffc)
+// Enables DMA channel transfer 
+#define APBDMACHAN_CHANNEL_11_CSR_0_ENB_SHIFT                   _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_11_CSR_0_ENB_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_11_CSR_0_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_11_CSR_0_ENB_RANGE                   31:31
+#define APBDMACHAN_CHANNEL_11_CSR_0_ENB_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_11_CSR_0_ENB_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_ENB_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_11_CSR_0_ENB_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_ENB_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_ENB_DISABLE                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_ENB_ENABLE                  _MK_ENUM_CONST(1)
+
+// Interrupts when DMA Block Transfer Completes
+#define APBDMACHAN_CHANNEL_11_CSR_0_IE_EOC_SHIFT                        _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_11_CSR_0_IE_EOC_FIELD                        (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_11_CSR_0_IE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_11_CSR_0_IE_EOC_RANGE                        30:30
+#define APBDMACHAN_CHANNEL_11_CSR_0_IE_EOC_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_11_CSR_0_IE_EOC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_IE_EOC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_11_CSR_0_IE_EOC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_IE_EOC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_IE_EOC_DISABLE                      _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_IE_EOC_ENABLE                       _MK_ENUM_CONST(1)
+
+// Holds this Processor until DMA Block Transfer Completes
+#define APBDMACHAN_CHANNEL_11_CSR_0_HOLD_SHIFT                  _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_11_CSR_0_HOLD_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_11_CSR_0_HOLD_SHIFT)
+#define APBDMACHAN_CHANNEL_11_CSR_0_HOLD_RANGE                  29:29
+#define APBDMACHAN_CHANNEL_11_CSR_0_HOLD_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_11_CSR_0_HOLD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_HOLD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_11_CSR_0_HOLD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_HOLD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_HOLD_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_HOLD_ENABLE                 _MK_ENUM_CONST(1)
+
+// DMA Transfer Direction 1 = AHB read to APB write 0 = APB read to AHB write
+#define APBDMACHAN_CHANNEL_11_CSR_0_DIR_SHIFT                   _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_11_CSR_0_DIR_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_11_CSR_0_DIR_SHIFT)
+#define APBDMACHAN_CHANNEL_11_CSR_0_DIR_RANGE                   28:28
+#define APBDMACHAN_CHANNEL_11_CSR_0_DIR_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_11_CSR_0_DIR_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_DIR_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_11_CSR_0_DIR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_DIR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_DIR_AHB_WRITE                       _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_DIR_AHB_READ                        _MK_ENUM_CONST(1)
+
+// Run Once or Run Multiple Mode (Allow Retriggering of this Channel) 1 = Run for One Block Transfer 0 = Run for Multiple Block Transfer
+#define APBDMACHAN_CHANNEL_11_CSR_0_ONCE_SHIFT                  _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_11_CSR_0_ONCE_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_11_CSR_0_ONCE_SHIFT)
+#define APBDMACHAN_CHANNEL_11_CSR_0_ONCE_RANGE                  27:27
+#define APBDMACHAN_CHANNEL_11_CSR_0_ONCE_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_11_CSR_0_ONCE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_ONCE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_11_CSR_0_ONCE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_ONCE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_ONCE_MULTIPLE_BLOCK                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_ONCE_SINGLE_BLOCK                   _MK_ENUM_CONST(1)
+
+// Enable on Non-Zero Value
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_SHIFT                      _MK_SHIFT_CONST(22)
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_FIELD                      (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_RANGE                      26:22
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_NA1                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_SMP24                      _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_SMP25                      _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_SMP26                      _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_SMP27                      _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_XRQ_A                      _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_XRQ_B                      _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_TMR1                       _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_TMR2                       _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_APB_0                      _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_APB_1                      _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_APB_2                      _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_APB_3                      _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_APB_4                      _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_APB_5                      _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_APB_6                      _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_APB_7                      _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_APB_8                      _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_APB_9                      _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_APB_10                     _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_APB_11                     _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_APB_12                     _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_APB_13                     _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_APB_14                     _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_APB_15                     _MK_ENUM_CONST(24)
+
+// Flow Control Enable (Synchronize Burst Transfers) 1 = Link to DRQ source 0 = Independent of DRQ request
+#define APBDMACHAN_CHANNEL_11_CSR_0_FLOW_SHIFT                  _MK_SHIFT_CONST(21)
+#define APBDMACHAN_CHANNEL_11_CSR_0_FLOW_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_11_CSR_0_FLOW_SHIFT)
+#define APBDMACHAN_CHANNEL_11_CSR_0_FLOW_RANGE                  21:21
+#define APBDMACHAN_CHANNEL_11_CSR_0_FLOW_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_11_CSR_0_FLOW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_FLOW_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_11_CSR_0_FLOW_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_FLOW_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_FLOW_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_FLOW_ENABLE                 _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_SHIFT                       _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_FIELD                       (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_RANGE                       20:16
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_CNTR_REQ                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_I2S_2                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_I2S_1                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_SPD_I                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_UI_I                        _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_MIPI                        _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_I2S2_2                      _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_I2S2_1                      _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_UART_A                      _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_UART_B                      _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_UART_C                      _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_SPI                 _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_AC97                        _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_ACModem                     _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_SL4B                        _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_SL2B1                       _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_SL2B2                       _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_SL2B3                       _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_NA18                        _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_NA19                        _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_NA20                        _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_NA21                        _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_NA22                        _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_NA23                        _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_NA24                        _MK_ENUM_CONST(24)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_NA25                        _MK_ENUM_CONST(25)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_NA26                        _MK_ENUM_CONST(26)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_NA27                        _MK_ENUM_CONST(27)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_NA28                        _MK_ENUM_CONST(28)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_NA29                        _MK_ENUM_CONST(29)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_NA30                        _MK_ENUM_CONST(30)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_NA31                        _MK_ENUM_CONST(31)
+
+// Number of 32bit word cycles
+#define APBDMACHAN_CHANNEL_11_CSR_0_WCOUNT_SHIFT                        _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_11_CSR_0_WCOUNT_FIELD                        (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_11_CSR_0_WCOUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_11_CSR_0_WCOUNT_RANGE                        15:2
+#define APBDMACHAN_CHANNEL_11_CSR_0_WCOUNT_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_11_CSR_0_WCOUNT_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_WCOUNT_DEFAULT_MASK                 _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_11_CSR_0_WCOUNT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_WCOUNT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_11_STA_0  
+#define APBDMACHAN_CHANNEL_11_STA_0                     _MK_ADDR_CONST(0x164)
+#define APBDMACHAN_CHANNEL_11_STA_0_WORD_COUNT                  0x1
+#define APBDMACHAN_CHANNEL_11_STA_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_STA_0_RESET_MASK                  _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_11_STA_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_STA_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_STA_0_READ_MASK                   _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_11_STA_0_WRITE_MASK                  _MK_MASK_CONST(0x40000000)
+// indicate DMA Channel Status activated or waiting
+#define APBDMACHAN_CHANNEL_11_STA_0_BSY_SHIFT                   _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_11_STA_0_BSY_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_11_STA_0_BSY_SHIFT)
+#define APBDMACHAN_CHANNEL_11_STA_0_BSY_RANGE                   31:31
+#define APBDMACHAN_CHANNEL_11_STA_0_BSY_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_11_STA_0_BSY_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_STA_0_BSY_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_11_STA_0_BSY_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_STA_0_BSY_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_STA_0_BSY_WAIT                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_11_STA_0_BSY_ACTIVE                  _MK_ENUM_CONST(1)
+
+//  Write '1' to clear the flag
+#define APBDMACHAN_CHANNEL_11_STA_0_ISE_EOC_SHIFT                       _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_11_STA_0_ISE_EOC_FIELD                       (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_11_STA_0_ISE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_11_STA_0_ISE_EOC_RANGE                       30:30
+#define APBDMACHAN_CHANNEL_11_STA_0_ISE_EOC_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_11_STA_0_ISE_EOC_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_STA_0_ISE_EOC_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_11_STA_0_ISE_EOC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_STA_0_ISE_EOC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_STA_0_ISE_EOC_NO_INTR                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_11_STA_0_ISE_EOC_INTR                        _MK_ENUM_CONST(1)
+
+// Holding Status of Processor 
+#define APBDMACHAN_CHANNEL_11_STA_0_HALT_SHIFT                  _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_11_STA_0_HALT_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_11_STA_0_HALT_SHIFT)
+#define APBDMACHAN_CHANNEL_11_STA_0_HALT_RANGE                  29:29
+#define APBDMACHAN_CHANNEL_11_STA_0_HALT_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_11_STA_0_HALT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_STA_0_HALT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_11_STA_0_HALT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_STA_0_HALT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_STA_0_HALT_NO_HALT                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_11_STA_0_HALT_HALT                   _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_11_STA_0_PING_PONG_STA_SHIFT                 _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_11_STA_0_PING_PONG_STA_FIELD                 (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_11_STA_0_PING_PONG_STA_SHIFT)
+#define APBDMACHAN_CHANNEL_11_STA_0_PING_PONG_STA_RANGE                 28:28
+#define APBDMACHAN_CHANNEL_11_STA_0_PING_PONG_STA_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_11_STA_0_PING_PONG_STA_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_STA_0_PING_PONG_STA_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_11_STA_0_PING_PONG_STA_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_STA_0_PING_PONG_STA_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_STA_0_PING_PONG_STA_PING_INTR_STA                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_11_STA_0_PING_PONG_STA_PONG_INTR_STA                 _MK_ENUM_CONST(1)
+
+// Current 32bit word cycles Flags set /cleared by HW
+#define APBDMACHAN_CHANNEL_11_STA_0_COUNT_SHIFT                 _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_11_STA_0_COUNT_FIELD                 (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_11_STA_0_COUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_11_STA_0_COUNT_RANGE                 15:2
+#define APBDMACHAN_CHANNEL_11_STA_0_COUNT_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_11_STA_0_COUNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_STA_0_COUNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_11_STA_0_COUNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_STA_0_COUNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Reserved address 360 [0x168] 
+
+// Reserved address 364 [0x16c] 
+
+// Register APBDMACHAN_CHANNEL_11_AHB_PTR_0  
+#define APBDMACHAN_CHANNEL_11_AHB_PTR_0                 _MK_ADDR_CONST(0x170)
+#define APBDMACHAN_CHANNEL_11_AHB_PTR_0_WORD_COUNT                      0x1
+#define APBDMACHAN_CHANNEL_11_AHB_PTR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_AHB_PTR_0_RESET_MASK                      _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_11_AHB_PTR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_AHB_PTR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_AHB_PTR_0_READ_MASK                       _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_11_AHB_PTR_0_WRITE_MASK                      _MK_MASK_CONST(0xfffffffc)
+// APB-DMA Starting Address for AHB Bus: SW writes to  modify
+#define APBDMACHAN_CHANNEL_11_AHB_PTR_0_AHB_BASE_SHIFT                  _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_11_AHB_PTR_0_AHB_BASE_FIELD                  (_MK_MASK_CONST(0x3fffffff) << APBDMACHAN_CHANNEL_11_AHB_PTR_0_AHB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_11_AHB_PTR_0_AHB_BASE_RANGE                  31:2
+#define APBDMACHAN_CHANNEL_11_AHB_PTR_0_AHB_BASE_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_11_AHB_PTR_0_AHB_BASE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_AHB_PTR_0_AHB_BASE_DEFAULT_MASK                   _MK_MASK_CONST(0x3fffffff)
+#define APBDMACHAN_CHANNEL_11_AHB_PTR_0_AHB_BASE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_AHB_PTR_0_AHB_BASE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_11_AHB_SEQ_0  
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0                 _MK_ADDR_CONST(0x174)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_WORD_COUNT                      0x1
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_RESET_VAL                       _MK_MASK_CONST(0x22000000)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_RESET_MASK                      _MK_MASK_CONST(0xff070000)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_READ_MASK                       _MK_MASK_CONST(0xff070000)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_WRITE_MASK                      _MK_MASK_CONST(0xff070000)
+//  0 = send interrupt to COP
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_INTR_ENB_SHIFT                  _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_INTR_ENB_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_11_AHB_SEQ_0_INTR_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_INTR_ENB_RANGE                  31:31
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_INTR_ENB_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_INTR_ENB_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_INTR_ENB_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_INTR_ENB_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_INTR_ENB_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_INTR_ENB_CPU                    _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_INTR_ENB_COP                    _MK_ENUM_CONST(0)
+
+// AHB Bus Width 0 = 8 bit Bus (RSVD) 1 = 16 bit Bus (RSVD) 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD)4 = 128 bit Bus (RSVD)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT                     _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_BUS_WIDTH_FIELD                     (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_BUS_WIDTH_RANGE                     30:28
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_BUS_WIDTH_WOFFSET                   0x0
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT                   _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_8                       _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_16                      _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_32                      _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_64                      _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_128                     _MK_ENUM_CONST(4)
+
+// when enabled the data going  to AHB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT                     _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_DATA_SWAP_FIELD                     (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_DATA_SWAP_RANGE                     27:27
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_DATA_SWAP_WOFFSET                   0x0
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_DATA_SWAP_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_DATA_SWAP_ENABLE                    _MK_ENUM_CONST(1)
+
+// AHB Burst Size DMA Burst Length (encoded) 4 = 1 Word (1x32bits) 5 = 4 Words (4x32bits)else = 8 Words (8x32bits) default
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_BURST_SHIFT                 _MK_SHIFT_CONST(24)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_BURST_FIELD                 (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_BURST_SHIFT)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_BURST_RANGE                 26:24
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_BURST_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_BURST_DEFAULT                       _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_BURST_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_BURST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_BURST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_BURST_DMA_BURST_1WORDS                      _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_BURST_DMA_BURST_4WORDS                      _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_BURST_DMA_BURST_8WORDS                      _MK_ENUM_CONST(6)
+
+// AHB Address Wrap: AHB Address wrap-around window 0=No Wrap (default) 5=Wrap on 512 word window 1=Wrap on 32 word window 6=Wrap on 1024 word window 2=Wrap on 64 word window 7=Wrap on 2048 word window 3=Wrap on 128 word window 4=Wrap on 256 word window
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_WRAP_SHIFT                      _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_WRAP_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_11_AHB_SEQ_0_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_WRAP_RANGE                      18:16
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_WRAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_WRAP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_WRAP_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_WRAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_WRAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_WRAP_NO_WRAP                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_WRAP_WRAP_0N_32WORDS                    _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_WRAP_WRAP_ON_64WORDS                    _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_WRAP_WRAP_ON_128WORDS                   _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_WRAP_WRAP_ON_256WORDS                   _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_WRAP_WRAP_ON_512WORDS                   _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_WRAP_WRAP_ON_1024WORDS                  _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_WRAP_WRAP_ON_2048WORDS                  _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_11_APB_PTR_0  
+#define APBDMACHAN_CHANNEL_11_APB_PTR_0                 _MK_ADDR_CONST(0x178)
+#define APBDMACHAN_CHANNEL_11_APB_PTR_0_WORD_COUNT                      0x1
+#define APBDMACHAN_CHANNEL_11_APB_PTR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_APB_PTR_0_RESET_MASK                      _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_11_APB_PTR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_APB_PTR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_APB_PTR_0_READ_MASK                       _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_11_APB_PTR_0_WRITE_MASK                      _MK_MASK_CONST(0xfffc)
+// APB-DMA Starting address for APB Bus: APB Base  address: Upper 16 bits are fixed at 0x7000:XXXX
+#define APBDMACHAN_CHANNEL_11_APB_PTR_0_APB_BASE_SHIFT                  _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_11_APB_PTR_0_APB_BASE_FIELD                  (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_11_APB_PTR_0_APB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_11_APB_PTR_0_APB_BASE_RANGE                  15:2
+#define APBDMACHAN_CHANNEL_11_APB_PTR_0_APB_BASE_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_11_APB_PTR_0_APB_BASE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_APB_PTR_0_APB_BASE_DEFAULT_MASK                   _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_11_APB_PTR_0_APB_BASE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_APB_PTR_0_APB_BASE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_11_APB_SEQ_0  
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0                 _MK_ADDR_CONST(0x17c)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_WORD_COUNT                      0x1
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_RESET_VAL                       _MK_MASK_CONST(0x20010000)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_RESET_MASK                      _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_READ_MASK                       _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_WRITE_MASK                      _MK_MASK_CONST(0x78070000)
+// 0 = 8 bit Bus 1 = 16 bit Bus 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD) 4 = 128 bit BUS (RSVD)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_BUS_WIDTH_SHIFT                     _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_BUS_WIDTH_FIELD                     (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_BUS_WIDTH_RANGE                     30:28
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_BUS_WIDTH_WOFFSET                   0x0
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT                   _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_8                       _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_16                      _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_32                      _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_64                      _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_128                     _MK_ENUM_CONST(4)
+
+// When enabled the data going  to APB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_DATA_SWAP_SHIFT                     _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_DATA_SWAP_FIELD                     (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_DATA_SWAP_RANGE                     27:27
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_DATA_SWAP_WOFFSET                   0x0
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_DATA_SWAP_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_DATA_SWAP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_DATA_SWAP_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_DATA_SWAP_ENABLE                    _MK_ENUM_CONST(1)
+
+//APB Address Wrap-around Window 0 = No Wrap 1 = Wrap on 1 Word Window (def) 2 = Wrap on 2 Word Window 3 = Wrap on 4 Word Window 4 = Wrap on 8 Word Window 5 = Wrap on 16 Word Window 6 = Wrap on 32 Word Window 7 = Wrap on 64 Word Window (rsvd)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_ADDR_WRAP_SHIFT                     _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_ADDR_WRAP_FIELD                     (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_ADDR_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_ADDR_WRAP_RANGE                     18:16
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_ADDR_WRAP_WOFFSET                   0x0
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_ADDR_WRAP_NO_WRAP                   _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_ADDR_WRAP_WRAP_0N_1WORDS                    _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_2WORDS                    _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_4WORDS                    _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_8WORDS                    _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_16WORDS                   _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_32WORDS                   _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_64WORDS                   _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_12_CSR_0  
+#define APBDMACHAN_CHANNEL_12_CSR_0                     _MK_ADDR_CONST(0x180)
+#define APBDMACHAN_CHANNEL_12_CSR_0_WORD_COUNT                  0x1
+#define APBDMACHAN_CHANNEL_12_CSR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_RESET_MASK                  _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_12_CSR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_READ_MASK                   _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_12_CSR_0_WRITE_MASK                  _MK_MASK_CONST(0xfffffffc)
+// Enables DMA channel transfer 
+#define APBDMACHAN_CHANNEL_12_CSR_0_ENB_SHIFT                   _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_12_CSR_0_ENB_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_12_CSR_0_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_12_CSR_0_ENB_RANGE                   31:31
+#define APBDMACHAN_CHANNEL_12_CSR_0_ENB_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_12_CSR_0_ENB_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_ENB_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_12_CSR_0_ENB_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_ENB_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_ENB_DISABLE                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_ENB_ENABLE                  _MK_ENUM_CONST(1)
+
+// Interrupts when DMA Block Transfer Completes 
+#define APBDMACHAN_CHANNEL_12_CSR_0_IE_EOC_SHIFT                        _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_12_CSR_0_IE_EOC_FIELD                        (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_12_CSR_0_IE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_12_CSR_0_IE_EOC_RANGE                        30:30
+#define APBDMACHAN_CHANNEL_12_CSR_0_IE_EOC_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_12_CSR_0_IE_EOC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_IE_EOC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_12_CSR_0_IE_EOC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_IE_EOC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_IE_EOC_DISABLE                      _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_IE_EOC_ENABLE                       _MK_ENUM_CONST(1)
+
+// Holds this Processor until DMA Block Transfer Completes
+#define APBDMACHAN_CHANNEL_12_CSR_0_HOLD_SHIFT                  _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_12_CSR_0_HOLD_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_12_CSR_0_HOLD_SHIFT)
+#define APBDMACHAN_CHANNEL_12_CSR_0_HOLD_RANGE                  29:29
+#define APBDMACHAN_CHANNEL_12_CSR_0_HOLD_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_12_CSR_0_HOLD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_HOLD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_12_CSR_0_HOLD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_HOLD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_HOLD_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_HOLD_ENABLE                 _MK_ENUM_CONST(1)
+
+// DMA Transfer Direction 1 = AHB read to APB write 0 = APB read to AHB write
+#define APBDMACHAN_CHANNEL_12_CSR_0_DIR_SHIFT                   _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_12_CSR_0_DIR_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_12_CSR_0_DIR_SHIFT)
+#define APBDMACHAN_CHANNEL_12_CSR_0_DIR_RANGE                   28:28
+#define APBDMACHAN_CHANNEL_12_CSR_0_DIR_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_12_CSR_0_DIR_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_DIR_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_12_CSR_0_DIR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_DIR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_DIR_AHB_WRITE                       _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_DIR_AHB_READ                        _MK_ENUM_CONST(1)
+
+// Run Once or Run Multiple Mode (Allow Retriggering of this Channel) 1 = Run for One Block Transfer 0 = Run for Multiple Block Transfer
+#define APBDMACHAN_CHANNEL_12_CSR_0_ONCE_SHIFT                  _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_12_CSR_0_ONCE_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_12_CSR_0_ONCE_SHIFT)
+#define APBDMACHAN_CHANNEL_12_CSR_0_ONCE_RANGE                  27:27
+#define APBDMACHAN_CHANNEL_12_CSR_0_ONCE_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_12_CSR_0_ONCE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_ONCE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_12_CSR_0_ONCE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_ONCE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_ONCE_MULTIPLE_BLOCK                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_ONCE_SINGLE_BLOCK                   _MK_ENUM_CONST(1)
+
+// Enable on Non-Zero Value
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_SHIFT                      _MK_SHIFT_CONST(22)
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_FIELD                      (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_RANGE                      26:22
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_NA1                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_SMP24                      _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_SMP25                      _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_SMP26                      _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_SMP27                      _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_XRQ_A                      _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_XRQ_B                      _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_TMR1                       _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_TMR2                       _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_APB_0                      _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_APB_1                      _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_APB_2                      _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_APB_3                      _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_APB_4                      _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_APB_5                      _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_APB_6                      _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_APB_7                      _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_APB_8                      _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_APB_9                      _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_APB_10                     _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_APB_11                     _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_APB_12                     _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_APB_13                     _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_APB_14                     _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_APB_15                     _MK_ENUM_CONST(24)
+
+// Flow Control Enable (Synchronize Burst Transfers) 1 = Link to DRQ source 0 = Independent of DRQ request
+#define APBDMACHAN_CHANNEL_12_CSR_0_FLOW_SHIFT                  _MK_SHIFT_CONST(21)
+#define APBDMACHAN_CHANNEL_12_CSR_0_FLOW_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_12_CSR_0_FLOW_SHIFT)
+#define APBDMACHAN_CHANNEL_12_CSR_0_FLOW_RANGE                  21:21
+#define APBDMACHAN_CHANNEL_12_CSR_0_FLOW_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_12_CSR_0_FLOW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_FLOW_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_12_CSR_0_FLOW_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_FLOW_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_FLOW_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_FLOW_ENABLE                 _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_SHIFT                       _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_FIELD                       (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_RANGE                       20:16
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_CNTR_REQ                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_I2S_2                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_I2S_1                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_SPD_I                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_UI_I                        _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_MIPI                        _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_I2S2_2                      _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_I2S2_1                      _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_UART_A                      _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_UART_B                      _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_UART_C                      _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_SPI                 _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_AC97                        _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_ACModem                     _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_SL4B                        _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_SL2B1                       _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_SL2B2                       _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_SL2B3                       _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_NA18                        _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_NA19                        _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_NA20                        _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_NA21                        _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_NA22                        _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_NA23                        _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_NA24                        _MK_ENUM_CONST(24)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_NA25                        _MK_ENUM_CONST(25)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_NA26                        _MK_ENUM_CONST(26)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_NA27                        _MK_ENUM_CONST(27)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_NA28                        _MK_ENUM_CONST(28)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_NA29                        _MK_ENUM_CONST(29)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_NA30                        _MK_ENUM_CONST(30)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_NA31                        _MK_ENUM_CONST(31)
+
+// Number of 32bit word cycles
+#define APBDMACHAN_CHANNEL_12_CSR_0_WCOUNT_SHIFT                        _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_12_CSR_0_WCOUNT_FIELD                        (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_12_CSR_0_WCOUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_12_CSR_0_WCOUNT_RANGE                        15:2
+#define APBDMACHAN_CHANNEL_12_CSR_0_WCOUNT_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_12_CSR_0_WCOUNT_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_WCOUNT_DEFAULT_MASK                 _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_12_CSR_0_WCOUNT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_WCOUNT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_12_STA_0  
+#define APBDMACHAN_CHANNEL_12_STA_0                     _MK_ADDR_CONST(0x184)
+#define APBDMACHAN_CHANNEL_12_STA_0_WORD_COUNT                  0x1
+#define APBDMACHAN_CHANNEL_12_STA_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_STA_0_RESET_MASK                  _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_12_STA_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_STA_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_STA_0_READ_MASK                   _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_12_STA_0_WRITE_MASK                  _MK_MASK_CONST(0x40000000)
+// indicate DMA Channel Status activated or not
+#define APBDMACHAN_CHANNEL_12_STA_0_BSY_SHIFT                   _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_12_STA_0_BSY_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_12_STA_0_BSY_SHIFT)
+#define APBDMACHAN_CHANNEL_12_STA_0_BSY_RANGE                   31:31
+#define APBDMACHAN_CHANNEL_12_STA_0_BSY_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_12_STA_0_BSY_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_STA_0_BSY_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_12_STA_0_BSY_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_STA_0_BSY_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_STA_0_BSY_WAIT                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_12_STA_0_BSY_ACTIVE                  _MK_ENUM_CONST(1)
+
+//  Write '1' to clear the flag
+#define APBDMACHAN_CHANNEL_12_STA_0_ISE_EOC_SHIFT                       _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_12_STA_0_ISE_EOC_FIELD                       (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_12_STA_0_ISE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_12_STA_0_ISE_EOC_RANGE                       30:30
+#define APBDMACHAN_CHANNEL_12_STA_0_ISE_EOC_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_12_STA_0_ISE_EOC_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_STA_0_ISE_EOC_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_12_STA_0_ISE_EOC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_STA_0_ISE_EOC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_STA_0_ISE_EOC_NO_INTR                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_12_STA_0_ISE_EOC_INTR                        _MK_ENUM_CONST(1)
+
+// Holding Status of Processor
+#define APBDMACHAN_CHANNEL_12_STA_0_HALT_SHIFT                  _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_12_STA_0_HALT_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_12_STA_0_HALT_SHIFT)
+#define APBDMACHAN_CHANNEL_12_STA_0_HALT_RANGE                  29:29
+#define APBDMACHAN_CHANNEL_12_STA_0_HALT_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_12_STA_0_HALT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_STA_0_HALT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_12_STA_0_HALT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_STA_0_HALT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_STA_0_HALT_NO_HALT                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_12_STA_0_HALT_HALT                   _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_12_STA_0_PING_PONG_STA_SHIFT                 _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_12_STA_0_PING_PONG_STA_FIELD                 (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_12_STA_0_PING_PONG_STA_SHIFT)
+#define APBDMACHAN_CHANNEL_12_STA_0_PING_PONG_STA_RANGE                 28:28
+#define APBDMACHAN_CHANNEL_12_STA_0_PING_PONG_STA_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_12_STA_0_PING_PONG_STA_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_STA_0_PING_PONG_STA_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_12_STA_0_PING_PONG_STA_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_STA_0_PING_PONG_STA_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_STA_0_PING_PONG_STA_PING_INTR_STA                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_12_STA_0_PING_PONG_STA_PONG_INTR_STA                 _MK_ENUM_CONST(1)
+
+// Current 32bit word cycles Flags set /cleared by HW
+#define APBDMACHAN_CHANNEL_12_STA_0_COUNT_SHIFT                 _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_12_STA_0_COUNT_FIELD                 (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_12_STA_0_COUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_12_STA_0_COUNT_RANGE                 15:2
+#define APBDMACHAN_CHANNEL_12_STA_0_COUNT_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_12_STA_0_COUNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_STA_0_COUNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_12_STA_0_COUNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_STA_0_COUNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Reserved address 392 [0x188] 
+
+// Reserved address 396 [0x18c] 
+
+// Register APBDMACHAN_CHANNEL_12_AHB_PTR_0  
+#define APBDMACHAN_CHANNEL_12_AHB_PTR_0                 _MK_ADDR_CONST(0x190)
+#define APBDMACHAN_CHANNEL_12_AHB_PTR_0_WORD_COUNT                      0x1
+#define APBDMACHAN_CHANNEL_12_AHB_PTR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_AHB_PTR_0_RESET_MASK                      _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_12_AHB_PTR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_AHB_PTR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_AHB_PTR_0_READ_MASK                       _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_12_AHB_PTR_0_WRITE_MASK                      _MK_MASK_CONST(0xfffffffc)
+// APB-DMA Starting Address for AHB Bus: SW writes to  modify
+#define APBDMACHAN_CHANNEL_12_AHB_PTR_0_AHB_BASE_SHIFT                  _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_12_AHB_PTR_0_AHB_BASE_FIELD                  (_MK_MASK_CONST(0x3fffffff) << APBDMACHAN_CHANNEL_12_AHB_PTR_0_AHB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_12_AHB_PTR_0_AHB_BASE_RANGE                  31:2
+#define APBDMACHAN_CHANNEL_12_AHB_PTR_0_AHB_BASE_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_12_AHB_PTR_0_AHB_BASE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_AHB_PTR_0_AHB_BASE_DEFAULT_MASK                   _MK_MASK_CONST(0x3fffffff)
+#define APBDMACHAN_CHANNEL_12_AHB_PTR_0_AHB_BASE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_AHB_PTR_0_AHB_BASE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_12_AHB_SEQ_0  
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0                 _MK_ADDR_CONST(0x194)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_WORD_COUNT                      0x1
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_RESET_VAL                       _MK_MASK_CONST(0x22000000)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_RESET_MASK                      _MK_MASK_CONST(0xff0f0000)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_READ_MASK                       _MK_MASK_CONST(0xff0f0000)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_WRITE_MASK                      _MK_MASK_CONST(0xff0f0000)
+//  0 = send interrupt to COP
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_INTR_ENB_SHIFT                  _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_INTR_ENB_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_12_AHB_SEQ_0_INTR_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_INTR_ENB_RANGE                  31:31
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_INTR_ENB_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_INTR_ENB_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_INTR_ENB_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_INTR_ENB_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_INTR_ENB_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_INTR_ENB_CPU                    _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_INTR_ENB_COP                    _MK_ENUM_CONST(0)
+
+// AHB Bus Width 0 = 8 bit Bus (RSVD) 1 = 16 bit Bus (RSVD) 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD)4 = 128 bit Bus (RSVD)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT                     _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_BUS_WIDTH_FIELD                     (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_BUS_WIDTH_RANGE                     30:28
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_BUS_WIDTH_WOFFSET                   0x0
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT                   _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_8                       _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_16                      _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_32                      _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_64                      _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_128                     _MK_ENUM_CONST(4)
+
+// When enabled the data going  to AHB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT                     _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_DATA_SWAP_FIELD                     (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_DATA_SWAP_RANGE                     27:27
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_DATA_SWAP_WOFFSET                   0x0
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_DATA_SWAP_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_DATA_SWAP_ENABLE                    _MK_ENUM_CONST(1)
+
+// AHB Burst Size DMA Burst Length (encoded) 4 = 1 Word (1x32bits) 5 = 4 Words (4x32bits)else = 8 Words (8x32bits) default
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_BURST_SHIFT                 _MK_SHIFT_CONST(24)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_BURST_FIELD                 (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_BURST_SHIFT)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_BURST_RANGE                 26:24
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_BURST_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_BURST_DEFAULT                       _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_BURST_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_BURST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_BURST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_BURST_DMA_BURST_1WORDS                      _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_BURST_DMA_BURST_4WORDS                      _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_BURST_DMA_BURST_8WORDS                      _MK_ENUM_CONST(6)
+
+// 2X Double Buffering Mode (For Run-Multiple Mode with No Wrap Operations) 1 = Reload Base Address for 2X blocks (reload every other time) 0 = Reload Base Address for 1X blocks  (def) (reload each time)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_DBL_BUF_SHIFT                   _MK_SHIFT_CONST(19)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_DBL_BUF_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_12_AHB_SEQ_0_DBL_BUF_SHIFT)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_DBL_BUF_RANGE                   19:19
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_DBL_BUF_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_DBL_BUF_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_DBL_BUF_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_DBL_BUF_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_DBL_BUF_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_DBL_BUF_RELOAD_FOR_1X_BLOCKS                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_DBL_BUF_RELOAD_FOR_2X_BLOCKS                    _MK_ENUM_CONST(1)
+
+// AHB Address Wrap: AHB Address wrap-around window 0=No Wrap (default) 5=Wrap on 512 word window 1=Wrap on 32 word window 6=Wrap on 1024 word window 2=Wrap on 64 word window 7=Wrap on 2048 word window 3=Wrap on 128 word window 4=Wrap on 256 word window
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_WRAP_SHIFT                      _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_WRAP_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_12_AHB_SEQ_0_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_WRAP_RANGE                      18:16
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_WRAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_WRAP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_WRAP_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_WRAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_WRAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_WRAP_NO_WRAP                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_WRAP_WRAP_0N_32WORDS                    _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_WRAP_WRAP_ON_64WORDS                    _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_WRAP_WRAP_ON_128WORDS                   _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_WRAP_WRAP_ON_256WORDS                   _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_WRAP_WRAP_ON_512WORDS                   _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_WRAP_WRAP_ON_1024WORDS                  _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_WRAP_WRAP_ON_2048WORDS                  _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_12_APB_PTR_0  
+#define APBDMACHAN_CHANNEL_12_APB_PTR_0                 _MK_ADDR_CONST(0x198)
+#define APBDMACHAN_CHANNEL_12_APB_PTR_0_WORD_COUNT                      0x1
+#define APBDMACHAN_CHANNEL_12_APB_PTR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_APB_PTR_0_RESET_MASK                      _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_12_APB_PTR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_APB_PTR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_APB_PTR_0_READ_MASK                       _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_12_APB_PTR_0_WRITE_MASK                      _MK_MASK_CONST(0xfffc)
+// APB-DMA Starting address for APB Bus: APB Base address:Upper 16 bits are fixed at 0x7000:XXXX
+#define APBDMACHAN_CHANNEL_12_APB_PTR_0_APB_BASE_SHIFT                  _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_12_APB_PTR_0_APB_BASE_FIELD                  (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_12_APB_PTR_0_APB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_12_APB_PTR_0_APB_BASE_RANGE                  15:2
+#define APBDMACHAN_CHANNEL_12_APB_PTR_0_APB_BASE_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_12_APB_PTR_0_APB_BASE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_APB_PTR_0_APB_BASE_DEFAULT_MASK                   _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_12_APB_PTR_0_APB_BASE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_APB_PTR_0_APB_BASE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_12_APB_SEQ_0  
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0                 _MK_ADDR_CONST(0x19c)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_WORD_COUNT                      0x1
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_RESET_VAL                       _MK_MASK_CONST(0x20010000)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_RESET_MASK                      _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_READ_MASK                       _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_WRITE_MASK                      _MK_MASK_CONST(0x78070000)
+// 0 = 8 bit Bus 1 = 16 bit Bus 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD) 4 = 128 bit BUS (RSVD)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_BUS_WIDTH_SHIFT                     _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_BUS_WIDTH_FIELD                     (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_BUS_WIDTH_RANGE                     30:28
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_BUS_WIDTH_WOFFSET                   0x0
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT                   _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_8                       _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_16                      _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_32                      _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_64                      _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_128                     _MK_ENUM_CONST(4)
+
+// When enabled the data going  to APB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_DATA_SWAP_SHIFT                     _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_DATA_SWAP_FIELD                     (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_DATA_SWAP_RANGE                     27:27
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_DATA_SWAP_WOFFSET                   0x0
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_DATA_SWAP_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_DATA_SWAP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_DATA_SWAP_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_DATA_SWAP_ENABLE                    _MK_ENUM_CONST(1)
+
+//APB Address Wrap-around Window 0 = No Wrap 1 = Wrap on 1 Word Window (def) 2 = Wrap on 2 Word Window 3 = Wrap on 4 Word Window 4 = Wrap on 8 Word Window 5 = Wrap on 16 Word Window 6 = Wrap on 32 Word Window 7 = Wrap on 64 Word Window (rsvd)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_ADDR_WRAP_SHIFT                     _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_ADDR_WRAP_FIELD                     (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_ADDR_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_ADDR_WRAP_RANGE                     18:16
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_ADDR_WRAP_WOFFSET                   0x0
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_ADDR_WRAP_NO_WRAP                   _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_ADDR_WRAP_WRAP_0N_1WORDS                    _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_2WORDS                    _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_4WORDS                    _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_8WORDS                    _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_16WORDS                   _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_32WORDS                   _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_64WORDS                   _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_13_CSR_0  
+#define APBDMACHAN_CHANNEL_13_CSR_0                     _MK_ADDR_CONST(0x1a0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_WORD_COUNT                  0x1
+#define APBDMACHAN_CHANNEL_13_CSR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_RESET_MASK                  _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_13_CSR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_READ_MASK                   _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_13_CSR_0_WRITE_MASK                  _MK_MASK_CONST(0xfffffffc)
+// Enables DMA channel transfer 
+#define APBDMACHAN_CHANNEL_13_CSR_0_ENB_SHIFT                   _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_13_CSR_0_ENB_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_13_CSR_0_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_13_CSR_0_ENB_RANGE                   31:31
+#define APBDMACHAN_CHANNEL_13_CSR_0_ENB_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_13_CSR_0_ENB_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_ENB_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_13_CSR_0_ENB_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_ENB_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_ENB_DISABLE                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_ENB_ENABLE                  _MK_ENUM_CONST(1)
+
+// Interrupts when DMA Block Transfer Completes 
+#define APBDMACHAN_CHANNEL_13_CSR_0_IE_EOC_SHIFT                        _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_13_CSR_0_IE_EOC_FIELD                        (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_13_CSR_0_IE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_13_CSR_0_IE_EOC_RANGE                        30:30
+#define APBDMACHAN_CHANNEL_13_CSR_0_IE_EOC_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_13_CSR_0_IE_EOC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_IE_EOC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_13_CSR_0_IE_EOC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_IE_EOC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_IE_EOC_DISABLE                      _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_IE_EOC_ENABLE                       _MK_ENUM_CONST(1)
+
+// Holds this Processor until DMA Block Transfer Completes 
+#define APBDMACHAN_CHANNEL_13_CSR_0_HOLD_SHIFT                  _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_13_CSR_0_HOLD_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_13_CSR_0_HOLD_SHIFT)
+#define APBDMACHAN_CHANNEL_13_CSR_0_HOLD_RANGE                  29:29
+#define APBDMACHAN_CHANNEL_13_CSR_0_HOLD_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_13_CSR_0_HOLD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_HOLD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_13_CSR_0_HOLD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_HOLD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_HOLD_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_HOLD_ENABLE                 _MK_ENUM_CONST(1)
+
+// DMA Transfer Direction 1 = AHB read to APB write 0 = APB read to AHB write
+#define APBDMACHAN_CHANNEL_13_CSR_0_DIR_SHIFT                   _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_13_CSR_0_DIR_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_13_CSR_0_DIR_SHIFT)
+#define APBDMACHAN_CHANNEL_13_CSR_0_DIR_RANGE                   28:28
+#define APBDMACHAN_CHANNEL_13_CSR_0_DIR_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_13_CSR_0_DIR_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_DIR_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_13_CSR_0_DIR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_DIR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_DIR_AHB_WRITE                       _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_DIR_AHB_READ                        _MK_ENUM_CONST(1)
+
+// Run Once or Run Multiple Mode (Allow Retriggering of this Channel) 1 = Run for One Block Transfer 0 = Run for Multiple Block Transfer
+#define APBDMACHAN_CHANNEL_13_CSR_0_ONCE_SHIFT                  _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_13_CSR_0_ONCE_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_13_CSR_0_ONCE_SHIFT)
+#define APBDMACHAN_CHANNEL_13_CSR_0_ONCE_RANGE                  27:27
+#define APBDMACHAN_CHANNEL_13_CSR_0_ONCE_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_13_CSR_0_ONCE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_ONCE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_13_CSR_0_ONCE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_ONCE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_ONCE_MULTIPLE_BLOCK                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_ONCE_SINGLE_BLOCK                   _MK_ENUM_CONST(1)
+
+// Enable on Non-Zero Value
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_SHIFT                      _MK_SHIFT_CONST(22)
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_FIELD                      (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_RANGE                      26:22
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_NA1                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_SMP24                      _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_SMP25                      _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_SMP26                      _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_SMP27                      _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_XRQ_A                      _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_XRQ_B                      _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_TMR1                       _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_TMR2                       _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_APB_0                      _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_APB_1                      _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_APB_2                      _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_APB_3                      _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_APB_4                      _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_APB_5                      _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_APB_6                      _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_APB_7                      _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_APB_8                      _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_APB_9                      _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_APB_10                     _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_APB_11                     _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_APB_12                     _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_APB_13                     _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_APB_14                     _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_APB_15                     _MK_ENUM_CONST(24)
+
+// Flow Control Enable (Synchronize Burst Transfers) 1 = Link to DRQ source 0 = Independent of DRQ request
+#define APBDMACHAN_CHANNEL_13_CSR_0_FLOW_SHIFT                  _MK_SHIFT_CONST(21)
+#define APBDMACHAN_CHANNEL_13_CSR_0_FLOW_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_13_CSR_0_FLOW_SHIFT)
+#define APBDMACHAN_CHANNEL_13_CSR_0_FLOW_RANGE                  21:21
+#define APBDMACHAN_CHANNEL_13_CSR_0_FLOW_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_13_CSR_0_FLOW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_FLOW_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_13_CSR_0_FLOW_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_FLOW_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_FLOW_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_FLOW_ENABLE                 _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_SHIFT                       _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_FIELD                       (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_RANGE                       20:16
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_CNTR_REQ                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_I2S_2                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_I2S_1                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_SPD_I                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_UI_I                        _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_MIPI                        _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_I2S2_2                      _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_I2S2_1                      _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_UART_A                      _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_UART_B                      _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_UART_C                      _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_SPI                 _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_AC97                        _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_ACModem                     _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_SL4B                        _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_SL2B1                       _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_SL2B2                       _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_SL2B3                       _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_NA18                        _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_NA19                        _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_NA20                        _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_NA21                        _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_NA22                        _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_NA23                        _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_NA24                        _MK_ENUM_CONST(24)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_NA25                        _MK_ENUM_CONST(25)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_NA26                        _MK_ENUM_CONST(26)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_NA27                        _MK_ENUM_CONST(27)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_NA28                        _MK_ENUM_CONST(28)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_NA29                        _MK_ENUM_CONST(29)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_NA30                        _MK_ENUM_CONST(30)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_NA31                        _MK_ENUM_CONST(31)
+
+// Number of 32bit word cycles
+#define APBDMACHAN_CHANNEL_13_CSR_0_WCOUNT_SHIFT                        _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_13_CSR_0_WCOUNT_FIELD                        (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_13_CSR_0_WCOUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_13_CSR_0_WCOUNT_RANGE                        15:2
+#define APBDMACHAN_CHANNEL_13_CSR_0_WCOUNT_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_13_CSR_0_WCOUNT_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_WCOUNT_DEFAULT_MASK                 _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_13_CSR_0_WCOUNT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_WCOUNT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_13_STA_0  
+#define APBDMACHAN_CHANNEL_13_STA_0                     _MK_ADDR_CONST(0x1a4)
+#define APBDMACHAN_CHANNEL_13_STA_0_WORD_COUNT                  0x1
+#define APBDMACHAN_CHANNEL_13_STA_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_STA_0_RESET_MASK                  _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_13_STA_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_STA_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_STA_0_READ_MASK                   _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_13_STA_0_WRITE_MASK                  _MK_MASK_CONST(0x40000000)
+// indicate DMA Channel Status activated or not 
+#define APBDMACHAN_CHANNEL_13_STA_0_BSY_SHIFT                   _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_13_STA_0_BSY_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_13_STA_0_BSY_SHIFT)
+#define APBDMACHAN_CHANNEL_13_STA_0_BSY_RANGE                   31:31
+#define APBDMACHAN_CHANNEL_13_STA_0_BSY_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_13_STA_0_BSY_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_STA_0_BSY_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_13_STA_0_BSY_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_STA_0_BSY_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_STA_0_BSY_WAIT                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_13_STA_0_BSY_ACTIVE                  _MK_ENUM_CONST(1)
+
+//  Write '1' to clear the flag
+#define APBDMACHAN_CHANNEL_13_STA_0_ISE_EOC_SHIFT                       _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_13_STA_0_ISE_EOC_FIELD                       (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_13_STA_0_ISE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_13_STA_0_ISE_EOC_RANGE                       30:30
+#define APBDMACHAN_CHANNEL_13_STA_0_ISE_EOC_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_13_STA_0_ISE_EOC_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_STA_0_ISE_EOC_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_13_STA_0_ISE_EOC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_STA_0_ISE_EOC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_STA_0_ISE_EOC_NO_INTR                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_13_STA_0_ISE_EOC_INTR                        _MK_ENUM_CONST(1)
+
+// Holding Status of Processor
+#define APBDMACHAN_CHANNEL_13_STA_0_HALT_SHIFT                  _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_13_STA_0_HALT_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_13_STA_0_HALT_SHIFT)
+#define APBDMACHAN_CHANNEL_13_STA_0_HALT_RANGE                  29:29
+#define APBDMACHAN_CHANNEL_13_STA_0_HALT_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_13_STA_0_HALT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_STA_0_HALT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_13_STA_0_HALT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_STA_0_HALT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_STA_0_HALT_NO_HALT                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_13_STA_0_HALT_HALT                   _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_13_STA_0_PING_PONG_STA_SHIFT                 _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_13_STA_0_PING_PONG_STA_FIELD                 (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_13_STA_0_PING_PONG_STA_SHIFT)
+#define APBDMACHAN_CHANNEL_13_STA_0_PING_PONG_STA_RANGE                 28:28
+#define APBDMACHAN_CHANNEL_13_STA_0_PING_PONG_STA_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_13_STA_0_PING_PONG_STA_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_STA_0_PING_PONG_STA_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_13_STA_0_PING_PONG_STA_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_STA_0_PING_PONG_STA_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_STA_0_PING_PONG_STA_PING_INTR_STA                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_13_STA_0_PING_PONG_STA_PONG_INTR_STA                 _MK_ENUM_CONST(1)
+
+// Current 32bit word cycles Flags set /cleared by HW
+#define APBDMACHAN_CHANNEL_13_STA_0_COUNT_SHIFT                 _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_13_STA_0_COUNT_FIELD                 (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_13_STA_0_COUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_13_STA_0_COUNT_RANGE                 15:2
+#define APBDMACHAN_CHANNEL_13_STA_0_COUNT_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_13_STA_0_COUNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_STA_0_COUNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_13_STA_0_COUNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_STA_0_COUNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Reserved address 424 [0x1a8] 
+
+// Reserved address 428 [0x1ac] 
+
+// Register APBDMACHAN_CHANNEL_13_AHB_PTR_0  
+#define APBDMACHAN_CHANNEL_13_AHB_PTR_0                 _MK_ADDR_CONST(0x1b0)
+#define APBDMACHAN_CHANNEL_13_AHB_PTR_0_WORD_COUNT                      0x1
+#define APBDMACHAN_CHANNEL_13_AHB_PTR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_AHB_PTR_0_RESET_MASK                      _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_13_AHB_PTR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_AHB_PTR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_AHB_PTR_0_READ_MASK                       _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_13_AHB_PTR_0_WRITE_MASK                      _MK_MASK_CONST(0xfffffffc)
+// APB-DMA Starting Address for AHB Bus: SW writes to  modify
+#define APBDMACHAN_CHANNEL_13_AHB_PTR_0_AHB_BASE_SHIFT                  _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_13_AHB_PTR_0_AHB_BASE_FIELD                  (_MK_MASK_CONST(0x3fffffff) << APBDMACHAN_CHANNEL_13_AHB_PTR_0_AHB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_13_AHB_PTR_0_AHB_BASE_RANGE                  31:2
+#define APBDMACHAN_CHANNEL_13_AHB_PTR_0_AHB_BASE_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_13_AHB_PTR_0_AHB_BASE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_AHB_PTR_0_AHB_BASE_DEFAULT_MASK                   _MK_MASK_CONST(0x3fffffff)
+#define APBDMACHAN_CHANNEL_13_AHB_PTR_0_AHB_BASE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_AHB_PTR_0_AHB_BASE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_13_AHB_SEQ_0  
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0                 _MK_ADDR_CONST(0x1b4)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_WORD_COUNT                      0x1
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_RESET_VAL                       _MK_MASK_CONST(0x22000000)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_RESET_MASK                      _MK_MASK_CONST(0xff0f0000)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_READ_MASK                       _MK_MASK_CONST(0xff0f0000)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_WRITE_MASK                      _MK_MASK_CONST(0xff0f0000)
+//  0 = send interrupt to COP
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_INTR_ENB_SHIFT                  _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_INTR_ENB_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_13_AHB_SEQ_0_INTR_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_INTR_ENB_RANGE                  31:31
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_INTR_ENB_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_INTR_ENB_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_INTR_ENB_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_INTR_ENB_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_INTR_ENB_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_INTR_ENB_CPU                    _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_INTR_ENB_COP                    _MK_ENUM_CONST(0)
+
+// AHB Bus Width 0 = 8 bit Bus (RSVD) 1 = 16 bit Bus (RSVD) 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD)4 = 128 bit Bus (RSVD)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT                     _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_BUS_WIDTH_FIELD                     (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_BUS_WIDTH_RANGE                     30:28
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_BUS_WIDTH_WOFFSET                   0x0
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT                   _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_8                       _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_16                      _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_32                      _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_64                      _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_128                     _MK_ENUM_CONST(4)
+
+// When enabled the data going  to AHB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT                     _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_DATA_SWAP_FIELD                     (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_DATA_SWAP_RANGE                     27:27
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_DATA_SWAP_WOFFSET                   0x0
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_DATA_SWAP_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_DATA_SWAP_ENABLE                    _MK_ENUM_CONST(1)
+
+// AHB Burst Size DMA Burst Length (encoded) 4 = 1 Word (1x32bits) 5 = 4 Words (4x32bits)else = 8 Words (8x32bits) default
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_BURST_SHIFT                 _MK_SHIFT_CONST(24)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_BURST_FIELD                 (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_BURST_SHIFT)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_BURST_RANGE                 26:24
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_BURST_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_BURST_DEFAULT                       _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_BURST_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_BURST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_BURST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_BURST_DMA_BURST_1WORDS                      _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_BURST_DMA_BURST_4WORDS                      _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_BURST_DMA_BURST_8WORDS                      _MK_ENUM_CONST(6)
+
+// 2X Double Buffering Mode (For Run-Multiple Mode with No Wrap Operations) 1 = Reload Base Address for 2X blocks (reload every other time) 0 = Reload Base Address for 1X blocks  (def) (reload each time)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_DBL_BUF_SHIFT                   _MK_SHIFT_CONST(19)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_DBL_BUF_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_13_AHB_SEQ_0_DBL_BUF_SHIFT)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_DBL_BUF_RANGE                   19:19
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_DBL_BUF_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_DBL_BUF_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_DBL_BUF_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_DBL_BUF_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_DBL_BUF_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_DBL_BUF_RELOAD_FOR_1X_BLOCKS                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_DBL_BUF_RELOAD_FOR_2X_BLOCKS                    _MK_ENUM_CONST(1)
+
+// AHB Address Wrap: AHB Address wrap-around window 0=No Wrap (default) 5=Wrap on 512 word window 1=Wrap on 32 word window 6=Wrap on 1024 word window 2=Wrap on 64 word window 7=Wrap on 2048 word window 3=Wrap on 128 word window 4=Wrap on 256 word window
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_WRAP_SHIFT                      _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_WRAP_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_13_AHB_SEQ_0_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_WRAP_RANGE                      18:16
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_WRAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_WRAP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_WRAP_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_WRAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_WRAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_WRAP_NO_WRAP                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_WRAP_WRAP_0N_32WORDS                    _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_WRAP_WRAP_ON_64WORDS                    _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_WRAP_WRAP_ON_128WORDS                   _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_WRAP_WRAP_ON_256WORDS                   _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_WRAP_WRAP_ON_512WORDS                   _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_WRAP_WRAP_ON_1024WORDS                  _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_WRAP_WRAP_ON_2048WORDS                  _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_13_APB_PTR_0  
+#define APBDMACHAN_CHANNEL_13_APB_PTR_0                 _MK_ADDR_CONST(0x1b8)
+#define APBDMACHAN_CHANNEL_13_APB_PTR_0_WORD_COUNT                      0x1
+#define APBDMACHAN_CHANNEL_13_APB_PTR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_APB_PTR_0_RESET_MASK                      _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_13_APB_PTR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_APB_PTR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_APB_PTR_0_READ_MASK                       _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_13_APB_PTR_0_WRITE_MASK                      _MK_MASK_CONST(0xfffc)
+// APB-DMA Starting address for APB Bus: APB Base address:Upper 16 bits are fixed at 0x7000:XXXX
+#define APBDMACHAN_CHANNEL_13_APB_PTR_0_APB_BASE_SHIFT                  _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_13_APB_PTR_0_APB_BASE_FIELD                  (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_13_APB_PTR_0_APB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_13_APB_PTR_0_APB_BASE_RANGE                  15:2
+#define APBDMACHAN_CHANNEL_13_APB_PTR_0_APB_BASE_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_13_APB_PTR_0_APB_BASE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_APB_PTR_0_APB_BASE_DEFAULT_MASK                   _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_13_APB_PTR_0_APB_BASE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_APB_PTR_0_APB_BASE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_13_APB_SEQ_0  
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0                 _MK_ADDR_CONST(0x1bc)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_WORD_COUNT                      0x1
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_RESET_VAL                       _MK_MASK_CONST(0x20010000)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_RESET_MASK                      _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_READ_MASK                       _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_WRITE_MASK                      _MK_MASK_CONST(0x78070000)
+// 0 = 8 bit Bus 1 = 16 bit Bus 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD) 4 = 128 bit BUS (RSVD)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_BUS_WIDTH_SHIFT                     _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_BUS_WIDTH_FIELD                     (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_BUS_WIDTH_RANGE                     30:28
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_BUS_WIDTH_WOFFSET                   0x0
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT                   _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_8                       _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_16                      _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_32                      _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_64                      _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_128                     _MK_ENUM_CONST(4)
+
+// When enabled the data going  to APB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_DATA_SWAP_SHIFT                     _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_DATA_SWAP_FIELD                     (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_DATA_SWAP_RANGE                     27:27
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_DATA_SWAP_WOFFSET                   0x0
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_DATA_SWAP_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_DATA_SWAP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_DATA_SWAP_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_DATA_SWAP_ENABLE                    _MK_ENUM_CONST(1)
+
+//APB Address Wrap-around Window 0 = No Wrap 1 = Wrap on 1 Word Window (def) 2 = Wrap on 2 Word Window 3 = Wrap on 4 Word Window 4 = Wrap on 8 Word Window 5 = Wrap on 16 Word Window 6 = Wrap on 32 Word Window 7 = Wrap on 64 Word Window (rsvd)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_ADDR_WRAP_SHIFT                     _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_ADDR_WRAP_FIELD                     (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_ADDR_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_ADDR_WRAP_RANGE                     18:16
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_ADDR_WRAP_WOFFSET                   0x0
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_ADDR_WRAP_NO_WRAP                   _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_ADDR_WRAP_WRAP_0N_1WORDS                    _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_2WORDS                    _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_4WORDS                    _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_8WORDS                    _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_16WORDS                   _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_32WORDS                   _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_64WORDS                   _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_14_CSR_0  
+#define APBDMACHAN_CHANNEL_14_CSR_0                     _MK_ADDR_CONST(0x1c0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_WORD_COUNT                  0x1
+#define APBDMACHAN_CHANNEL_14_CSR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_RESET_MASK                  _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_14_CSR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_READ_MASK                   _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_14_CSR_0_WRITE_MASK                  _MK_MASK_CONST(0xfffffffc)
+// Enables DMA channel transfer 
+#define APBDMACHAN_CHANNEL_14_CSR_0_ENB_SHIFT                   _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_14_CSR_0_ENB_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_14_CSR_0_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_14_CSR_0_ENB_RANGE                   31:31
+#define APBDMACHAN_CHANNEL_14_CSR_0_ENB_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_14_CSR_0_ENB_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_ENB_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_14_CSR_0_ENB_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_ENB_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_ENB_DISABLE                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_ENB_ENABLE                  _MK_ENUM_CONST(1)
+
+// Interrupts when DMA Block Transfer Completes 
+#define APBDMACHAN_CHANNEL_14_CSR_0_IE_EOC_SHIFT                        _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_14_CSR_0_IE_EOC_FIELD                        (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_14_CSR_0_IE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_14_CSR_0_IE_EOC_RANGE                        30:30
+#define APBDMACHAN_CHANNEL_14_CSR_0_IE_EOC_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_14_CSR_0_IE_EOC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_IE_EOC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_14_CSR_0_IE_EOC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_IE_EOC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_IE_EOC_DISABLE                      _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_IE_EOC_ENABLE                       _MK_ENUM_CONST(1)
+
+// Holds this Processor until DMA Block Transfer Completes 
+#define APBDMACHAN_CHANNEL_14_CSR_0_HOLD_SHIFT                  _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_14_CSR_0_HOLD_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_14_CSR_0_HOLD_SHIFT)
+#define APBDMACHAN_CHANNEL_14_CSR_0_HOLD_RANGE                  29:29
+#define APBDMACHAN_CHANNEL_14_CSR_0_HOLD_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_14_CSR_0_HOLD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_HOLD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_14_CSR_0_HOLD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_HOLD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_HOLD_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_HOLD_ENABLE                 _MK_ENUM_CONST(1)
+
+// DMA Transfer Direction 1 = AHB read to APB write 0 = APB read to AHB write
+#define APBDMACHAN_CHANNEL_14_CSR_0_DIR_SHIFT                   _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_14_CSR_0_DIR_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_14_CSR_0_DIR_SHIFT)
+#define APBDMACHAN_CHANNEL_14_CSR_0_DIR_RANGE                   28:28
+#define APBDMACHAN_CHANNEL_14_CSR_0_DIR_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_14_CSR_0_DIR_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_DIR_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_14_CSR_0_DIR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_DIR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_DIR_AHB_WRITE                       _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_DIR_AHB_READ                        _MK_ENUM_CONST(1)
+
+// Run Once or Run Multiple Mode (Allow Retriggering of this Channel) 1 = Run for One Block Transfer 0 = Run for Multiple Block Transfer
+#define APBDMACHAN_CHANNEL_14_CSR_0_ONCE_SHIFT                  _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_14_CSR_0_ONCE_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_14_CSR_0_ONCE_SHIFT)
+#define APBDMACHAN_CHANNEL_14_CSR_0_ONCE_RANGE                  27:27
+#define APBDMACHAN_CHANNEL_14_CSR_0_ONCE_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_14_CSR_0_ONCE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_ONCE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_14_CSR_0_ONCE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_ONCE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_ONCE_MULTIPLE_BLOCK                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_ONCE_SINGLE_BLOCK                   _MK_ENUM_CONST(1)
+
+// Enable on Non-Zero Value
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_SHIFT                      _MK_SHIFT_CONST(22)
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_FIELD                      (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_RANGE                      26:22
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_NA1                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_SMP24                      _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_SMP25                      _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_SMP26                      _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_SMP27                      _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_XRQ_A                      _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_XRQ_B                      _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_TMR1                       _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_TMR2                       _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_APB_0                      _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_APB_1                      _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_APB_2                      _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_APB_3                      _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_APB_4                      _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_APB_5                      _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_APB_6                      _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_APB_7                      _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_APB_8                      _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_APB_9                      _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_APB_10                     _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_APB_11                     _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_APB_12                     _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_APB_13                     _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_APB_14                     _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_APB_15                     _MK_ENUM_CONST(24)
+
+// Flow Control Enable (Synchronize Burst Transfers) 1 = Link to DRQ source 0 = Independent of DRQ request
+#define APBDMACHAN_CHANNEL_14_CSR_0_FLOW_SHIFT                  _MK_SHIFT_CONST(21)
+#define APBDMACHAN_CHANNEL_14_CSR_0_FLOW_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_14_CSR_0_FLOW_SHIFT)
+#define APBDMACHAN_CHANNEL_14_CSR_0_FLOW_RANGE                  21:21
+#define APBDMACHAN_CHANNEL_14_CSR_0_FLOW_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_14_CSR_0_FLOW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_FLOW_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_14_CSR_0_FLOW_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_FLOW_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_FLOW_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_FLOW_ENABLE                 _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_SHIFT                       _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_FIELD                       (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_RANGE                       20:16
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_CNTR_REQ                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_I2S_2                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_I2S_1                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_SPD_I                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_UI_I                        _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_MIPI                        _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_I2S2_2                      _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_I2S2_1                      _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_UART_A                      _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_UART_B                      _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_UART_C                      _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_SPI                 _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_AC97                        _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_ACModem                     _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_SL4B                        _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_SL2B1                       _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_SL2B2                       _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_SL2B3                       _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_NA18                        _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_NA19                        _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_NA20                        _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_NA21                        _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_NA22                        _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_NA23                        _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_NA24                        _MK_ENUM_CONST(24)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_NA25                        _MK_ENUM_CONST(25)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_NA26                        _MK_ENUM_CONST(26)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_NA27                        _MK_ENUM_CONST(27)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_NA28                        _MK_ENUM_CONST(28)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_NA29                        _MK_ENUM_CONST(29)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_NA30                        _MK_ENUM_CONST(30)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_NA31                        _MK_ENUM_CONST(31)
+
+// Number of 32bit word cycles
+#define APBDMACHAN_CHANNEL_14_CSR_0_WCOUNT_SHIFT                        _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_14_CSR_0_WCOUNT_FIELD                        (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_14_CSR_0_WCOUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_14_CSR_0_WCOUNT_RANGE                        15:2
+#define APBDMACHAN_CHANNEL_14_CSR_0_WCOUNT_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_14_CSR_0_WCOUNT_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_WCOUNT_DEFAULT_MASK                 _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_14_CSR_0_WCOUNT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_WCOUNT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_14_STA_0  
+#define APBDMACHAN_CHANNEL_14_STA_0                     _MK_ADDR_CONST(0x1c4)
+#define APBDMACHAN_CHANNEL_14_STA_0_WORD_COUNT                  0x1
+#define APBDMACHAN_CHANNEL_14_STA_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_STA_0_RESET_MASK                  _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_14_STA_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_STA_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_STA_0_READ_MASK                   _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_14_STA_0_WRITE_MASK                  _MK_MASK_CONST(0x40000000)
+// indicate DMA Channel Status activated or not 
+#define APBDMACHAN_CHANNEL_14_STA_0_BSY_SHIFT                   _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_14_STA_0_BSY_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_14_STA_0_BSY_SHIFT)
+#define APBDMACHAN_CHANNEL_14_STA_0_BSY_RANGE                   31:31
+#define APBDMACHAN_CHANNEL_14_STA_0_BSY_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_14_STA_0_BSY_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_STA_0_BSY_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_14_STA_0_BSY_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_STA_0_BSY_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_STA_0_BSY_WAIT                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_14_STA_0_BSY_ACTIVE                  _MK_ENUM_CONST(1)
+
+//  Write '1' to clear the flag
+#define APBDMACHAN_CHANNEL_14_STA_0_ISE_EOC_SHIFT                       _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_14_STA_0_ISE_EOC_FIELD                       (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_14_STA_0_ISE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_14_STA_0_ISE_EOC_RANGE                       30:30
+#define APBDMACHAN_CHANNEL_14_STA_0_ISE_EOC_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_14_STA_0_ISE_EOC_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_STA_0_ISE_EOC_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_14_STA_0_ISE_EOC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_STA_0_ISE_EOC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_STA_0_ISE_EOC_NO_INTR                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_14_STA_0_ISE_EOC_INTR                        _MK_ENUM_CONST(1)
+
+// Holding Status of Processor 
+#define APBDMACHAN_CHANNEL_14_STA_0_HALT_SHIFT                  _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_14_STA_0_HALT_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_14_STA_0_HALT_SHIFT)
+#define APBDMACHAN_CHANNEL_14_STA_0_HALT_RANGE                  29:29
+#define APBDMACHAN_CHANNEL_14_STA_0_HALT_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_14_STA_0_HALT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_STA_0_HALT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_14_STA_0_HALT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_STA_0_HALT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_STA_0_HALT_NO_HALT                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_14_STA_0_HALT_HALT                   _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_14_STA_0_PING_PONG_STA_SHIFT                 _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_14_STA_0_PING_PONG_STA_FIELD                 (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_14_STA_0_PING_PONG_STA_SHIFT)
+#define APBDMACHAN_CHANNEL_14_STA_0_PING_PONG_STA_RANGE                 28:28
+#define APBDMACHAN_CHANNEL_14_STA_0_PING_PONG_STA_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_14_STA_0_PING_PONG_STA_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_STA_0_PING_PONG_STA_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_14_STA_0_PING_PONG_STA_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_STA_0_PING_PONG_STA_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_STA_0_PING_PONG_STA_PING_INTR_STA                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_14_STA_0_PING_PONG_STA_PONG_INTR_STA                 _MK_ENUM_CONST(1)
+
+// Current 32bit word cycles Flags set /cleared by HW
+#define APBDMACHAN_CHANNEL_14_STA_0_COUNT_SHIFT                 _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_14_STA_0_COUNT_FIELD                 (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_14_STA_0_COUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_14_STA_0_COUNT_RANGE                 15:2
+#define APBDMACHAN_CHANNEL_14_STA_0_COUNT_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_14_STA_0_COUNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_STA_0_COUNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_14_STA_0_COUNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_STA_0_COUNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Reserved address 456 [0x1c8] 
+
+// Reserved address 460 [0x1cc] 
+
+// Register APBDMACHAN_CHANNEL_14_AHB_PTR_0  
+#define APBDMACHAN_CHANNEL_14_AHB_PTR_0                 _MK_ADDR_CONST(0x1d0)
+#define APBDMACHAN_CHANNEL_14_AHB_PTR_0_WORD_COUNT                      0x1
+#define APBDMACHAN_CHANNEL_14_AHB_PTR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_AHB_PTR_0_RESET_MASK                      _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_14_AHB_PTR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_AHB_PTR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_AHB_PTR_0_READ_MASK                       _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_14_AHB_PTR_0_WRITE_MASK                      _MK_MASK_CONST(0xfffffffc)
+// APB-DMA Starting Address for AHB Bus: SW writes to  modify
+#define APBDMACHAN_CHANNEL_14_AHB_PTR_0_AHB_BASE_SHIFT                  _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_14_AHB_PTR_0_AHB_BASE_FIELD                  (_MK_MASK_CONST(0x3fffffff) << APBDMACHAN_CHANNEL_14_AHB_PTR_0_AHB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_14_AHB_PTR_0_AHB_BASE_RANGE                  31:2
+#define APBDMACHAN_CHANNEL_14_AHB_PTR_0_AHB_BASE_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_14_AHB_PTR_0_AHB_BASE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_AHB_PTR_0_AHB_BASE_DEFAULT_MASK                   _MK_MASK_CONST(0x3fffffff)
+#define APBDMACHAN_CHANNEL_14_AHB_PTR_0_AHB_BASE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_AHB_PTR_0_AHB_BASE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_14_AHB_SEQ_0  
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0                 _MK_ADDR_CONST(0x1d4)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_WORD_COUNT                      0x1
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_RESET_VAL                       _MK_MASK_CONST(0x22000000)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_RESET_MASK                      _MK_MASK_CONST(0xff0f0000)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_READ_MASK                       _MK_MASK_CONST(0xff0f0000)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_WRITE_MASK                      _MK_MASK_CONST(0xff0f0000)
+//  0 = send interrupt to COP
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_INTR_ENB_SHIFT                  _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_INTR_ENB_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_14_AHB_SEQ_0_INTR_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_INTR_ENB_RANGE                  31:31
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_INTR_ENB_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_INTR_ENB_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_INTR_ENB_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_INTR_ENB_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_INTR_ENB_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_INTR_ENB_CPU                    _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_INTR_ENB_COP                    _MK_ENUM_CONST(0)
+
+// AHB Bus Width 0 = 8 bit Bus (RSVD) 1 = 16 bit Bus (RSVD) 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD)4 = 128 bit Bus (RSVD)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT                     _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_BUS_WIDTH_FIELD                     (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_BUS_WIDTH_RANGE                     30:28
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_BUS_WIDTH_WOFFSET                   0x0
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT                   _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_8                       _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_16                      _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_32                      _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_64                      _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_128                     _MK_ENUM_CONST(4)
+
+// When enabled the data going  to AHB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT                     _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_DATA_SWAP_FIELD                     (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_DATA_SWAP_RANGE                     27:27
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_DATA_SWAP_WOFFSET                   0x0
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_DATA_SWAP_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_DATA_SWAP_ENABLE                    _MK_ENUM_CONST(1)
+
+// AHB Burst Size DMA Burst Length (encoded) 4 = 1 Word (1x32bits) 5 = 4 Words (4x32bits)else = 8 Words (8x32bits) default
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_BURST_SHIFT                 _MK_SHIFT_CONST(24)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_BURST_FIELD                 (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_BURST_SHIFT)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_BURST_RANGE                 26:24
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_BURST_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_BURST_DEFAULT                       _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_BURST_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_BURST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_BURST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_BURST_DMA_BURST_1WORDS                      _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_BURST_DMA_BURST_4WORDS                      _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_BURST_DMA_BURST_8WORDS                      _MK_ENUM_CONST(6)
+
+// 2X Double Buffering Mode (For Run-Multiple Mode with No Wrap Operations) 1 = Reload Base Address for 2X blocks (reload every other time) 0 = Reload Base Address for 1X blocks  (def) (reload each time)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_DBL_BUF_SHIFT                   _MK_SHIFT_CONST(19)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_DBL_BUF_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_14_AHB_SEQ_0_DBL_BUF_SHIFT)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_DBL_BUF_RANGE                   19:19
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_DBL_BUF_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_DBL_BUF_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_DBL_BUF_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_DBL_BUF_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_DBL_BUF_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_DBL_BUF_RELOAD_FOR_1X_BLOCKS                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_DBL_BUF_RELOAD_FOR_2X_BLOCKS                    _MK_ENUM_CONST(1)
+
+// AHB Address Wrap: AHB Address wrap-around window 0=No Wrap (default) 5=Wrap on 512 word window 1=Wrap on 32 word window 6=Wrap on 1024 word window 2=Wrap on 64 word window 7=Wrap on 2048 word window 3=Wrap on 128 word window 4=Wrap on 256 word window
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_WRAP_SHIFT                      _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_WRAP_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_14_AHB_SEQ_0_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_WRAP_RANGE                      18:16
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_WRAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_WRAP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_WRAP_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_WRAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_WRAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_WRAP_NO_WRAP                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_WRAP_WRAP_0N_32WORDS                    _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_WRAP_WRAP_ON_64WORDS                    _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_WRAP_WRAP_ON_128WORDS                   _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_WRAP_WRAP_ON_256WORDS                   _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_WRAP_WRAP_ON_512WORDS                   _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_WRAP_WRAP_ON_1024WORDS                  _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_WRAP_WRAP_ON_2048WORDS                  _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_14_APB_PTR_0  
+#define APBDMACHAN_CHANNEL_14_APB_PTR_0                 _MK_ADDR_CONST(0x1d8)
+#define APBDMACHAN_CHANNEL_14_APB_PTR_0_WORD_COUNT                      0x1
+#define APBDMACHAN_CHANNEL_14_APB_PTR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_APB_PTR_0_RESET_MASK                      _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_14_APB_PTR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_APB_PTR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_APB_PTR_0_READ_MASK                       _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_14_APB_PTR_0_WRITE_MASK                      _MK_MASK_CONST(0xfffc)
+// APB-DMA Starting address for APB Bus: APB Base address:Upper 16 bits are fixed at 0x7000:XXXX
+#define APBDMACHAN_CHANNEL_14_APB_PTR_0_APB_BASE_SHIFT                  _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_14_APB_PTR_0_APB_BASE_FIELD                  (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_14_APB_PTR_0_APB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_14_APB_PTR_0_APB_BASE_RANGE                  15:2
+#define APBDMACHAN_CHANNEL_14_APB_PTR_0_APB_BASE_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_14_APB_PTR_0_APB_BASE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_APB_PTR_0_APB_BASE_DEFAULT_MASK                   _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_14_APB_PTR_0_APB_BASE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_APB_PTR_0_APB_BASE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_14_APB_SEQ_0  
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0                 _MK_ADDR_CONST(0x1dc)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_WORD_COUNT                      0x1
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_RESET_VAL                       _MK_MASK_CONST(0x20010000)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_RESET_MASK                      _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_READ_MASK                       _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_WRITE_MASK                      _MK_MASK_CONST(0x78070000)
+// 0 = 8 bit Bus 1 = 16 bit Bus 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD) 4 = 128 bit BUS (RSVD)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_BUS_WIDTH_SHIFT                     _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_BUS_WIDTH_FIELD                     (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_BUS_WIDTH_RANGE                     30:28
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_BUS_WIDTH_WOFFSET                   0x0
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT                   _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_8                       _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_16                      _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_32                      _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_64                      _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_128                     _MK_ENUM_CONST(4)
+
+// When enabled the data going  to APB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_DATA_SWAP_SHIFT                     _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_DATA_SWAP_FIELD                     (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_DATA_SWAP_RANGE                     27:27
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_DATA_SWAP_WOFFSET                   0x0
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_DATA_SWAP_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_DATA_SWAP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_DATA_SWAP_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_DATA_SWAP_ENABLE                    _MK_ENUM_CONST(1)
+
+//APB Address Wrap-around Window 0 = No Wrap 1 = Wrap on 1 Word Window (def) 2 = Wrap on 2 Word Window 3 = Wrap on 4 Word Window 4 = Wrap on 8 Word Window 5 = Wrap on 16 Word Window 6 = Wrap on 32 Word Window 7 = Wrap on 64 Word Window (rsvd)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_ADDR_WRAP_SHIFT                     _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_ADDR_WRAP_FIELD                     (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_ADDR_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_ADDR_WRAP_RANGE                     18:16
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_ADDR_WRAP_WOFFSET                   0x0
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_ADDR_WRAP_NO_WRAP                   _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_ADDR_WRAP_WRAP_0N_1WORDS                    _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_2WORDS                    _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_4WORDS                    _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_8WORDS                    _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_16WORDS                   _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_32WORDS                   _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_64WORDS                   _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_15_CSR_0  
+#define APBDMACHAN_CHANNEL_15_CSR_0                     _MK_ADDR_CONST(0x1e0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_WORD_COUNT                  0x1
+#define APBDMACHAN_CHANNEL_15_CSR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_RESET_MASK                  _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_15_CSR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_READ_MASK                   _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_15_CSR_0_WRITE_MASK                  _MK_MASK_CONST(0xfffffffc)
+// Enables DMA channel transfer 
+#define APBDMACHAN_CHANNEL_15_CSR_0_ENB_SHIFT                   _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_15_CSR_0_ENB_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_15_CSR_0_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_15_CSR_0_ENB_RANGE                   31:31
+#define APBDMACHAN_CHANNEL_15_CSR_0_ENB_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_15_CSR_0_ENB_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_ENB_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_15_CSR_0_ENB_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_ENB_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_ENB_DISABLE                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_ENB_ENABLE                  _MK_ENUM_CONST(1)
+
+// Interrupts when DMA Block Transfer Completes 
+#define APBDMACHAN_CHANNEL_15_CSR_0_IE_EOC_SHIFT                        _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_15_CSR_0_IE_EOC_FIELD                        (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_15_CSR_0_IE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_15_CSR_0_IE_EOC_RANGE                        30:30
+#define APBDMACHAN_CHANNEL_15_CSR_0_IE_EOC_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_15_CSR_0_IE_EOC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_IE_EOC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_15_CSR_0_IE_EOC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_IE_EOC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_IE_EOC_DISABLE                      _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_IE_EOC_ENABLE                       _MK_ENUM_CONST(1)
+
+// Holds this Processor until DMA Block Transfer Completes 
+#define APBDMACHAN_CHANNEL_15_CSR_0_HOLD_SHIFT                  _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_15_CSR_0_HOLD_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_15_CSR_0_HOLD_SHIFT)
+#define APBDMACHAN_CHANNEL_15_CSR_0_HOLD_RANGE                  29:29
+#define APBDMACHAN_CHANNEL_15_CSR_0_HOLD_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_15_CSR_0_HOLD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_HOLD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_15_CSR_0_HOLD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_HOLD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_HOLD_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_HOLD_ENABLE                 _MK_ENUM_CONST(1)
+
+// DMA Transfer Direction 1 = AHB read to APB write 0 = APB read to AHB write
+#define APBDMACHAN_CHANNEL_15_CSR_0_DIR_SHIFT                   _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_15_CSR_0_DIR_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_15_CSR_0_DIR_SHIFT)
+#define APBDMACHAN_CHANNEL_15_CSR_0_DIR_RANGE                   28:28
+#define APBDMACHAN_CHANNEL_15_CSR_0_DIR_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_15_CSR_0_DIR_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_DIR_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_15_CSR_0_DIR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_DIR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_DIR_AHB_WRITE                       _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_DIR_AHB_READ                        _MK_ENUM_CONST(1)
+
+// Run Once or Run Multiple Mode (Allow Retriggering of this Channel) 1 = Run for One Block Transfer 0 = Run for Multiple Block Transfer
+#define APBDMACHAN_CHANNEL_15_CSR_0_ONCE_SHIFT                  _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_15_CSR_0_ONCE_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_15_CSR_0_ONCE_SHIFT)
+#define APBDMACHAN_CHANNEL_15_CSR_0_ONCE_RANGE                  27:27
+#define APBDMACHAN_CHANNEL_15_CSR_0_ONCE_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_15_CSR_0_ONCE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_ONCE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_15_CSR_0_ONCE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_ONCE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_ONCE_MULTIPLE_BLOCK                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_ONCE_SINGLE_BLOCK                   _MK_ENUM_CONST(1)
+
+// Enable on Non-Zero Value
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_SHIFT                      _MK_SHIFT_CONST(22)
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_FIELD                      (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_RANGE                      26:22
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_NA1                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_SMP24                      _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_SMP25                      _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_SMP26                      _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_SMP27                      _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_XRQ_A                      _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_XRQ_B                      _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_TMR1                       _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_TMR2                       _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_APB_0                      _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_APB_1                      _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_APB_2                      _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_APB_3                      _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_APB_4                      _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_APB_5                      _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_APB_6                      _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_APB_7                      _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_APB_8                      _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_APB_9                      _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_APB_10                     _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_APB_11                     _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_APB_12                     _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_APB_13                     _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_APB_14                     _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_APB_15                     _MK_ENUM_CONST(24)
+
+// Flow Control Enable (Synchronize Burst Transfers) 1 = Link to DRQ source 0 = Independent of DRQ request
+#define APBDMACHAN_CHANNEL_15_CSR_0_FLOW_SHIFT                  _MK_SHIFT_CONST(21)
+#define APBDMACHAN_CHANNEL_15_CSR_0_FLOW_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_15_CSR_0_FLOW_SHIFT)
+#define APBDMACHAN_CHANNEL_15_CSR_0_FLOW_RANGE                  21:21
+#define APBDMACHAN_CHANNEL_15_CSR_0_FLOW_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_15_CSR_0_FLOW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_FLOW_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_15_CSR_0_FLOW_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_FLOW_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_FLOW_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_FLOW_ENABLE                 _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_SHIFT                       _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_FIELD                       (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_RANGE                       20:16
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_CNTR_REQ                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_I2S_2                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_I2S_1                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_SPD_I                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_UI_I                        _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_MIPI                        _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_I2S2_2                      _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_I2S2_1                      _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_UART_A                      _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_UART_B                      _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_UART_C                      _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_SPI                 _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_AC97                        _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_ACModem                     _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_SL4B                        _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_SL2B1                       _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_SL2B2                       _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_SL2B3                       _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_NA18                        _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_NA19                        _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_NA20                        _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_NA21                        _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_NA22                        _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_NA23                        _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_NA24                        _MK_ENUM_CONST(24)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_NA25                        _MK_ENUM_CONST(25)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_NA26                        _MK_ENUM_CONST(26)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_NA27                        _MK_ENUM_CONST(27)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_NA28                        _MK_ENUM_CONST(28)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_NA29                        _MK_ENUM_CONST(29)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_NA30                        _MK_ENUM_CONST(30)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_NA31                        _MK_ENUM_CONST(31)
+
+// Number of 32bit word cycles
+#define APBDMACHAN_CHANNEL_15_CSR_0_WCOUNT_SHIFT                        _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_15_CSR_0_WCOUNT_FIELD                        (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_15_CSR_0_WCOUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_15_CSR_0_WCOUNT_RANGE                        15:2
+#define APBDMACHAN_CHANNEL_15_CSR_0_WCOUNT_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_15_CSR_0_WCOUNT_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_WCOUNT_DEFAULT_MASK                 _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_15_CSR_0_WCOUNT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_WCOUNT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_15_STA_0  
+#define APBDMACHAN_CHANNEL_15_STA_0                     _MK_ADDR_CONST(0x1e4)
+#define APBDMACHAN_CHANNEL_15_STA_0_WORD_COUNT                  0x1
+#define APBDMACHAN_CHANNEL_15_STA_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_STA_0_RESET_MASK                  _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_15_STA_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_STA_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_STA_0_READ_MASK                   _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_15_STA_0_WRITE_MASK                  _MK_MASK_CONST(0x40000000)
+// indicate DMA Channel Status activated or not 
+#define APBDMACHAN_CHANNEL_15_STA_0_BSY_SHIFT                   _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_15_STA_0_BSY_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_15_STA_0_BSY_SHIFT)
+#define APBDMACHAN_CHANNEL_15_STA_0_BSY_RANGE                   31:31
+#define APBDMACHAN_CHANNEL_15_STA_0_BSY_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_15_STA_0_BSY_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_STA_0_BSY_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_15_STA_0_BSY_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_STA_0_BSY_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_STA_0_BSY_WAIT                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_15_STA_0_BSY_ACTIVE                  _MK_ENUM_CONST(1)
+
+//  Write '1' to clear the flag
+#define APBDMACHAN_CHANNEL_15_STA_0_ISE_EOC_SHIFT                       _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_15_STA_0_ISE_EOC_FIELD                       (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_15_STA_0_ISE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_15_STA_0_ISE_EOC_RANGE                       30:30
+#define APBDMACHAN_CHANNEL_15_STA_0_ISE_EOC_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_15_STA_0_ISE_EOC_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_STA_0_ISE_EOC_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_15_STA_0_ISE_EOC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_STA_0_ISE_EOC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_STA_0_ISE_EOC_NO_INTR                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_15_STA_0_ISE_EOC_INTR                        _MK_ENUM_CONST(1)
+
+// Holding Status of Processor 
+#define APBDMACHAN_CHANNEL_15_STA_0_HALT_SHIFT                  _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_15_STA_0_HALT_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_15_STA_0_HALT_SHIFT)
+#define APBDMACHAN_CHANNEL_15_STA_0_HALT_RANGE                  29:29
+#define APBDMACHAN_CHANNEL_15_STA_0_HALT_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_15_STA_0_HALT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_STA_0_HALT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_15_STA_0_HALT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_STA_0_HALT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_STA_0_HALT_NO_HALT                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_15_STA_0_HALT_HALT                   _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_15_STA_0_PING_PONG_STA_SHIFT                 _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_15_STA_0_PING_PONG_STA_FIELD                 (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_15_STA_0_PING_PONG_STA_SHIFT)
+#define APBDMACHAN_CHANNEL_15_STA_0_PING_PONG_STA_RANGE                 28:28
+#define APBDMACHAN_CHANNEL_15_STA_0_PING_PONG_STA_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_15_STA_0_PING_PONG_STA_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_STA_0_PING_PONG_STA_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_15_STA_0_PING_PONG_STA_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_STA_0_PING_PONG_STA_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_STA_0_PING_PONG_STA_PING_INTR_STA                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_15_STA_0_PING_PONG_STA_PONG_INTR_STA                 _MK_ENUM_CONST(1)
+
+// Current 32bit word cycles Flags set /cleared by HW
+#define APBDMACHAN_CHANNEL_15_STA_0_COUNT_SHIFT                 _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_15_STA_0_COUNT_FIELD                 (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_15_STA_0_COUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_15_STA_0_COUNT_RANGE                 15:2
+#define APBDMACHAN_CHANNEL_15_STA_0_COUNT_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_15_STA_0_COUNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_STA_0_COUNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_15_STA_0_COUNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_STA_0_COUNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Reserved address 488 [0x1e8] 
+
+// Reserved address 492 [0x1ec] 
+
+// Register APBDMACHAN_CHANNEL_15_AHB_PTR_0  
+#define APBDMACHAN_CHANNEL_15_AHB_PTR_0                 _MK_ADDR_CONST(0x1f0)
+#define APBDMACHAN_CHANNEL_15_AHB_PTR_0_WORD_COUNT                      0x1
+#define APBDMACHAN_CHANNEL_15_AHB_PTR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_AHB_PTR_0_RESET_MASK                      _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_15_AHB_PTR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_AHB_PTR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_AHB_PTR_0_READ_MASK                       _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_15_AHB_PTR_0_WRITE_MASK                      _MK_MASK_CONST(0xfffffffc)
+// APB-DMA Starting Address for AHB Bus: SW writes to  modify
+#define APBDMACHAN_CHANNEL_15_AHB_PTR_0_AHB_BASE_SHIFT                  _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_15_AHB_PTR_0_AHB_BASE_FIELD                  (_MK_MASK_CONST(0x3fffffff) << APBDMACHAN_CHANNEL_15_AHB_PTR_0_AHB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_15_AHB_PTR_0_AHB_BASE_RANGE                  31:2
+#define APBDMACHAN_CHANNEL_15_AHB_PTR_0_AHB_BASE_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_15_AHB_PTR_0_AHB_BASE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_AHB_PTR_0_AHB_BASE_DEFAULT_MASK                   _MK_MASK_CONST(0x3fffffff)
+#define APBDMACHAN_CHANNEL_15_AHB_PTR_0_AHB_BASE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_AHB_PTR_0_AHB_BASE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_15_AHB_SEQ_0  
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0                 _MK_ADDR_CONST(0x1f4)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_WORD_COUNT                      0x1
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_RESET_VAL                       _MK_MASK_CONST(0x22000000)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_RESET_MASK                      _MK_MASK_CONST(0xff0f0000)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_READ_MASK                       _MK_MASK_CONST(0xff0f0000)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_WRITE_MASK                      _MK_MASK_CONST(0xff0f0000)
+//  0 = send interrupt to COP
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_INTR_ENB_SHIFT                  _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_INTR_ENB_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_15_AHB_SEQ_0_INTR_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_INTR_ENB_RANGE                  31:31
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_INTR_ENB_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_INTR_ENB_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_INTR_ENB_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_INTR_ENB_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_INTR_ENB_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_INTR_ENB_CPU                    _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_INTR_ENB_COP                    _MK_ENUM_CONST(0)
+
+// AHB Bus Width 0 = 8 bit Bus (RSVD) 1 = 16 bit Bus (RSVD) 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD)4 = 128 bit Bus (RSVD)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT                     _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_BUS_WIDTH_FIELD                     (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_BUS_WIDTH_RANGE                     30:28
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_BUS_WIDTH_WOFFSET                   0x0
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT                   _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_8                       _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_16                      _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_32                      _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_64                      _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_128                     _MK_ENUM_CONST(4)
+
+// When enabled the data going  to AHB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT                     _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_DATA_SWAP_FIELD                     (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_DATA_SWAP_RANGE                     27:27
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_DATA_SWAP_WOFFSET                   0x0
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_DATA_SWAP_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_DATA_SWAP_ENABLE                    _MK_ENUM_CONST(1)
+
+// AHB Burst Size DMA Burst Length (encoded) 4 = 1 Word (1x32bits) 5 = 4 Words (4x32bits)else = 8 Words (8x32bits) default
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_BURST_SHIFT                 _MK_SHIFT_CONST(24)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_BURST_FIELD                 (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_BURST_SHIFT)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_BURST_RANGE                 26:24
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_BURST_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_BURST_DEFAULT                       _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_BURST_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_BURST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_BURST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_BURST_DMA_BURST_1WORDS                      _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_BURST_DMA_BURST_4WORDS                      _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_BURST_DMA_BURST_8WORDS                      _MK_ENUM_CONST(6)
+
+// 2X Double Buffering Mode (For Run-Multiple Mode with No Wrap Operations) 1 = Reload Base Address for 2X blocks (reload every other time) 0 = Reload Base Address for 1X blocks  (def) (reload each time)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_DBL_BUF_SHIFT                   _MK_SHIFT_CONST(19)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_DBL_BUF_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_15_AHB_SEQ_0_DBL_BUF_SHIFT)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_DBL_BUF_RANGE                   19:19
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_DBL_BUF_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_DBL_BUF_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_DBL_BUF_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_DBL_BUF_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_DBL_BUF_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_DBL_BUF_RELOAD_FOR_1X_BLOCKS                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_DBL_BUF_RELOAD_FOR_2X_BLOCKS                    _MK_ENUM_CONST(1)
+
+// AHB Address Wrap: AHB Address wrap-around window 0=No Wrap (default) 5=Wrap on 512 word window 1=Wrap on 32 word window 6=Wrap on 1024 word window 2=Wrap on 64 word window 7=Wrap on 2048 word window 3=Wrap on 128 word window 4=Wrap on 256 word window
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_WRAP_SHIFT                      _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_WRAP_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_15_AHB_SEQ_0_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_WRAP_RANGE                      18:16
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_WRAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_WRAP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_WRAP_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_WRAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_WRAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_WRAP_NO_WRAP                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_WRAP_WRAP_0N_32WORDS                    _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_WRAP_WRAP_ON_64WORDS                    _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_WRAP_WRAP_ON_128WORDS                   _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_WRAP_WRAP_ON_256WORDS                   _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_WRAP_WRAP_ON_512WORDS                   _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_WRAP_WRAP_ON_1024WORDS                  _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_WRAP_WRAP_ON_2048WORDS                  _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_15_APB_PTR_0  
+#define APBDMACHAN_CHANNEL_15_APB_PTR_0                 _MK_ADDR_CONST(0x1f8)
+#define APBDMACHAN_CHANNEL_15_APB_PTR_0_WORD_COUNT                      0x1
+#define APBDMACHAN_CHANNEL_15_APB_PTR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_APB_PTR_0_RESET_MASK                      _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_15_APB_PTR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_APB_PTR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_APB_PTR_0_READ_MASK                       _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_15_APB_PTR_0_WRITE_MASK                      _MK_MASK_CONST(0xfffc)
+// APB-DMA Starting address for APB Bus: APB Base address:Upper 16 bits are fixed at 0x7000:XXXX
+#define APBDMACHAN_CHANNEL_15_APB_PTR_0_APB_BASE_SHIFT                  _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_15_APB_PTR_0_APB_BASE_FIELD                  (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_15_APB_PTR_0_APB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_15_APB_PTR_0_APB_BASE_RANGE                  15:2
+#define APBDMACHAN_CHANNEL_15_APB_PTR_0_APB_BASE_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_15_APB_PTR_0_APB_BASE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_APB_PTR_0_APB_BASE_DEFAULT_MASK                   _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_15_APB_PTR_0_APB_BASE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_APB_PTR_0_APB_BASE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_15_APB_SEQ_0  
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0                 _MK_ADDR_CONST(0x1fc)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_WORD_COUNT                      0x1
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_RESET_VAL                       _MK_MASK_CONST(0x20010000)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_RESET_MASK                      _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_READ_MASK                       _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_WRITE_MASK                      _MK_MASK_CONST(0x78070000)
+// 0 = 8 bit Bus 1 = 16 bit Bus 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD) 4 = 128 bit BUS (RSVD)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_BUS_WIDTH_SHIFT                     _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_BUS_WIDTH_FIELD                     (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_BUS_WIDTH_RANGE                     30:28
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_BUS_WIDTH_WOFFSET                   0x0
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT                   _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_8                       _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_16                      _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_32                      _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_64                      _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_128                     _MK_ENUM_CONST(4)
+
+// When enabled the data going  to APB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }.
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_DATA_SWAP_SHIFT                     _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_DATA_SWAP_FIELD                     (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_DATA_SWAP_RANGE                     27:27
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_DATA_SWAP_WOFFSET                   0x0
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_DATA_SWAP_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_DATA_SWAP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_DATA_SWAP_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_DATA_SWAP_ENABLE                    _MK_ENUM_CONST(1)
+
+//APB Address Wrap-around Window 0 = No Wrap 1 = Wrap on 1 Word Window (def) 2 = Wrap on 2 Word Window 3 = Wrap on 4 Word Window 4 = Wrap on 8 Word Window 5 = Wrap on 16 Word Window 6 = Wrap on 32 Word Window 7 = Wrap on 64 Word Window (rsvd)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_ADDR_WRAP_SHIFT                     _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_ADDR_WRAP_FIELD                     (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_ADDR_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_ADDR_WRAP_RANGE                     18:16
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_ADDR_WRAP_WOFFSET                   0x0
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_ADDR_WRAP_NO_WRAP                   _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_ADDR_WRAP_WRAP_0N_1WORDS                    _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_2WORDS                    _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_4WORDS                    _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_8WORDS                    _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_16WORDS                   _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_32WORDS                   _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_64WORDS                   _MK_ENUM_CONST(7)
+
+
+//
+// REGISTER LIST
+//
+#define LIST_ARAPBDMACHAN_REGS(_op_) \
+_op_(APBDMACHAN_CHANNEL_0_CSR_0) \
+_op_(APBDMACHAN_CHANNEL_0_STA_0) \
+_op_(APBDMACHAN_CHANNEL_0_AHB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_0_AHB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_0_APB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_0_APB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_1_CSR_0) \
+_op_(APBDMACHAN_CHANNEL_1_STA_0) \
+_op_(APBDMACHAN_CHANNEL_1_AHB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_1_AHB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_1_APB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_1_APB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_2_CSR_0) \
+_op_(APBDMACHAN_CHANNEL_2_STA_0) \
+_op_(APBDMACHAN_CHANNEL_2_AHB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_2_AHB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_2_APB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_2_APB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_3_CSR_0) \
+_op_(APBDMACHAN_CHANNEL_3_STA_0) \
+_op_(APBDMACHAN_CHANNEL_3_AHB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_3_AHB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_3_APB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_3_APB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_4_CSR_0) \
+_op_(APBDMACHAN_CHANNEL_4_STA_0) \
+_op_(APBDMACHAN_CHANNEL_4_AHB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_4_AHB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_4_APB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_4_APB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_5_CSR_0) \
+_op_(APBDMACHAN_CHANNEL_5_STA_0) \
+_op_(APBDMACHAN_CHANNEL_5_AHB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_5_AHB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_5_APB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_5_APB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_6_CSR_0) \
+_op_(APBDMACHAN_CHANNEL_6_STA_0) \
+_op_(APBDMACHAN_CHANNEL_6_AHB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_6_AHB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_6_APB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_6_APB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_7_CSR_0) \
+_op_(APBDMACHAN_CHANNEL_7_STA_0) \
+_op_(APBDMACHAN_CHANNEL_7_AHB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_7_AHB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_7_APB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_7_APB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_8_CSR_0) \
+_op_(APBDMACHAN_CHANNEL_8_STA_0) \
+_op_(APBDMACHAN_CHANNEL_8_AHB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_8_AHB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_8_APB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_8_APB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_9_CSR_0) \
+_op_(APBDMACHAN_CHANNEL_9_STA_0) \
+_op_(APBDMACHAN_CHANNEL_9_AHB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_9_AHB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_9_APB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_9_APB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_10_CSR_0) \
+_op_(APBDMACHAN_CHANNEL_10_STA_0) \
+_op_(APBDMACHAN_CHANNEL_10_AHB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_10_AHB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_10_APB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_10_APB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_11_CSR_0) \
+_op_(APBDMACHAN_CHANNEL_11_STA_0) \
+_op_(APBDMACHAN_CHANNEL_11_AHB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_11_AHB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_11_APB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_11_APB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_12_CSR_0) \
+_op_(APBDMACHAN_CHANNEL_12_STA_0) \
+_op_(APBDMACHAN_CHANNEL_12_AHB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_12_AHB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_12_APB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_12_APB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_13_CSR_0) \
+_op_(APBDMACHAN_CHANNEL_13_STA_0) \
+_op_(APBDMACHAN_CHANNEL_13_AHB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_13_AHB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_13_APB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_13_APB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_14_CSR_0) \
+_op_(APBDMACHAN_CHANNEL_14_STA_0) \
+_op_(APBDMACHAN_CHANNEL_14_AHB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_14_AHB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_14_APB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_14_APB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_15_CSR_0) \
+_op_(APBDMACHAN_CHANNEL_15_STA_0) \
+_op_(APBDMACHAN_CHANNEL_15_AHB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_15_AHB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_15_APB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_15_APB_SEQ_0)
+
+
+//
+// ADDRESS SPACES
+//
+
+#define BASE_ADDRESS_APBDMACHAN 0x00000000
+
+//
+// ARAPBDMACHAN REGISTER BANKS
+//
+
+#define APBDMACHAN0_FIRST_REG 0x0000 // APBDMACHAN_CHANNEL_0_CSR_0
+#define APBDMACHAN0_LAST_REG 0x0004 // APBDMACHAN_CHANNEL_0_STA_0
+#define APBDMACHAN1_FIRST_REG 0x0010 // APBDMACHAN_CHANNEL_0_AHB_PTR_0
+#define APBDMACHAN1_LAST_REG 0x0024 // APBDMACHAN_CHANNEL_1_STA_0
+#define APBDMACHAN2_FIRST_REG 0x0030 // APBDMACHAN_CHANNEL_1_AHB_PTR_0
+#define APBDMACHAN2_LAST_REG 0x0044 // APBDMACHAN_CHANNEL_2_STA_0
+#define APBDMACHAN3_FIRST_REG 0x0050 // APBDMACHAN_CHANNEL_2_AHB_PTR_0
+#define APBDMACHAN3_LAST_REG 0x0064 // APBDMACHAN_CHANNEL_3_STA_0
+#define APBDMACHAN4_FIRST_REG 0x0070 // APBDMACHAN_CHANNEL_3_AHB_PTR_0
+#define APBDMACHAN4_LAST_REG 0x0084 // APBDMACHAN_CHANNEL_4_STA_0
+#define APBDMACHAN5_FIRST_REG 0x0090 // APBDMACHAN_CHANNEL_4_AHB_PTR_0
+#define APBDMACHAN5_LAST_REG 0x00a4 // APBDMACHAN_CHANNEL_5_STA_0
+#define APBDMACHAN6_FIRST_REG 0x00b0 // APBDMACHAN_CHANNEL_5_AHB_PTR_0
+#define APBDMACHAN6_LAST_REG 0x00c4 // APBDMACHAN_CHANNEL_6_STA_0
+#define APBDMACHAN7_FIRST_REG 0x00d0 // APBDMACHAN_CHANNEL_6_AHB_PTR_0
+#define APBDMACHAN7_LAST_REG 0x00e4 // APBDMACHAN_CHANNEL_7_STA_0
+#define APBDMACHAN8_FIRST_REG 0x00f0 // APBDMACHAN_CHANNEL_7_AHB_PTR_0
+#define APBDMACHAN8_LAST_REG 0x0104 // APBDMACHAN_CHANNEL_8_STA_0
+#define APBDMACHAN9_FIRST_REG 0x0110 // APBDMACHAN_CHANNEL_8_AHB_PTR_0
+#define APBDMACHAN9_LAST_REG 0x0124 // APBDMACHAN_CHANNEL_9_STA_0
+#define APBDMACHAN10_FIRST_REG 0x0130 // APBDMACHAN_CHANNEL_9_AHB_PTR_0
+#define APBDMACHAN10_LAST_REG 0x0144 // APBDMACHAN_CHANNEL_10_STA_0
+#define APBDMACHAN11_FIRST_REG 0x0150 // APBDMACHAN_CHANNEL_10_AHB_PTR_0
+#define APBDMACHAN11_LAST_REG 0x0164 // APBDMACHAN_CHANNEL_11_STA_0
+#define APBDMACHAN12_FIRST_REG 0x0170 // APBDMACHAN_CHANNEL_11_AHB_PTR_0
+#define APBDMACHAN12_LAST_REG 0x0184 // APBDMACHAN_CHANNEL_12_STA_0
+#define APBDMACHAN13_FIRST_REG 0x0190 // APBDMACHAN_CHANNEL_12_AHB_PTR_0
+#define APBDMACHAN13_LAST_REG 0x01a4 // APBDMACHAN_CHANNEL_13_STA_0
+#define APBDMACHAN14_FIRST_REG 0x01b0 // APBDMACHAN_CHANNEL_13_AHB_PTR_0
+#define APBDMACHAN14_LAST_REG 0x01c4 // APBDMACHAN_CHANNEL_14_STA_0
+#define APBDMACHAN15_FIRST_REG 0x01d0 // APBDMACHAN_CHANNEL_14_AHB_PTR_0
+#define APBDMACHAN15_LAST_REG 0x01e4 // APBDMACHAN_CHANNEL_15_STA_0
+#define APBDMACHAN16_FIRST_REG 0x01f0 // APBDMACHAN_CHANNEL_15_AHB_PTR_0
+#define APBDMACHAN16_LAST_REG 0x01fc // APBDMACHAN_CHANNEL_15_APB_SEQ_0
+
+#ifndef _MK_SHIFT_CONST
+  #define _MK_SHIFT_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_MASK_CONST
+  #define _MK_MASK_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_ENUM_CONST
+  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
+#endif
+#ifndef _MK_ADDR_CONST
+  #define _MK_ADDR_CONST(_constant_) _constant_
+#endif
+
+#endif // ifndef ___ARAPBDMACHAN_H_INC_
diff --git a/arch/arm/mach-tegra/include/ap15/arapbpm.h b/arch/arm/mach-tegra/include/ap15/arapbpm.h
new file mode 100644
index 000000000000..25289c58dfd6
--- /dev/null
+++ b/arch/arm/mach-tegra/include/ap15/arapbpm.h
@@ -0,0 +1,2166 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+//
+// DO NOT EDIT - generated by simspec!
+//
+
+#ifndef ___ARAPBPM_H_INC_
+#define ___ARAPBPM_H_INC_
+
+// Register APBDEV_PMC_CNTRL_0  
+#define APBDEV_PMC_CNTRL_0                      _MK_ADDR_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_WORD_COUNT                   0x1
+#define APBDEV_PMC_CNTRL_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_RESET_MASK                   _MK_MASK_CONST(0x7fff)
+#define APBDEV_PMC_CNTRL_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_READ_MASK                    _MK_MASK_CONST(0x7fff)
+#define APBDEV_PMC_CNTRL_0_WRITE_MASK                   _MK_MASK_CONST(0x7fff)
+// Disable 32KHz clock to KBC 
+#define APBDEV_PMC_CNTRL_0_KBC_CLK_DIS_SHIFT                    _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_CNTRL_0_KBC_CLK_DIS_FIELD                    (_MK_MASK_CONST(0x1) << APBDEV_PMC_CNTRL_0_KBC_CLK_DIS_SHIFT)
+#define APBDEV_PMC_CNTRL_0_KBC_CLK_DIS_RANGE                    0:0
+#define APBDEV_PMC_CNTRL_0_KBC_CLK_DIS_WOFFSET                  0x0
+#define APBDEV_PMC_CNTRL_0_KBC_CLK_DIS_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_KBC_CLK_DIS_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_CNTRL_0_KBC_CLK_DIS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_KBC_CLK_DIS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_KBC_CLK_DIS_DISABLE                  _MK_ENUM_CONST(0)
+#define APBDEV_PMC_CNTRL_0_KBC_CLK_DIS_ENABLE                   _MK_ENUM_CONST(1)
+
+// Disable  32KHz clock to RTC                          
+#define APBDEV_PMC_CNTRL_0_RTC_CLK_DIS_SHIFT                    _MK_SHIFT_CONST(1)
+#define APBDEV_PMC_CNTRL_0_RTC_CLK_DIS_FIELD                    (_MK_MASK_CONST(0x1) << APBDEV_PMC_CNTRL_0_RTC_CLK_DIS_SHIFT)
+#define APBDEV_PMC_CNTRL_0_RTC_CLK_DIS_RANGE                    1:1
+#define APBDEV_PMC_CNTRL_0_RTC_CLK_DIS_WOFFSET                  0x0
+#define APBDEV_PMC_CNTRL_0_RTC_CLK_DIS_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_RTC_CLK_DIS_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_CNTRL_0_RTC_CLK_DIS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_RTC_CLK_DIS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_RTC_CLK_DIS_DISABLE                  _MK_ENUM_CONST(0)
+#define APBDEV_PMC_CNTRL_0_RTC_CLK_DIS_ENABLE                   _MK_ENUM_CONST(1)
+
+// Software reset to RTC
+#define APBDEV_PMC_CNTRL_0_RTC_RST_SHIFT                        _MK_SHIFT_CONST(2)
+#define APBDEV_PMC_CNTRL_0_RTC_RST_FIELD                        (_MK_MASK_CONST(0x1) << APBDEV_PMC_CNTRL_0_RTC_RST_SHIFT)
+#define APBDEV_PMC_CNTRL_0_RTC_RST_RANGE                        2:2
+#define APBDEV_PMC_CNTRL_0_RTC_RST_WOFFSET                      0x0
+#define APBDEV_PMC_CNTRL_0_RTC_RST_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_RTC_RST_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_CNTRL_0_RTC_RST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_RTC_RST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_RTC_RST_DISABLE                      _MK_ENUM_CONST(0)
+#define APBDEV_PMC_CNTRL_0_RTC_RST_ENABLE                       _MK_ENUM_CONST(1)
+
+// Software reset to KBC  
+#define APBDEV_PMC_CNTRL_0_KBC_RST_SHIFT                        _MK_SHIFT_CONST(3)
+#define APBDEV_PMC_CNTRL_0_KBC_RST_FIELD                        (_MK_MASK_CONST(0x1) << APBDEV_PMC_CNTRL_0_KBC_RST_SHIFT)
+#define APBDEV_PMC_CNTRL_0_KBC_RST_RANGE                        3:3
+#define APBDEV_PMC_CNTRL_0_KBC_RST_WOFFSET                      0x0
+#define APBDEV_PMC_CNTRL_0_KBC_RST_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_KBC_RST_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_CNTRL_0_KBC_RST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_KBC_RST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_KBC_RST_DISABLE                      _MK_ENUM_CONST(0)
+#define APBDEV_PMC_CNTRL_0_KBC_RST_ENABLE                       _MK_ENUM_CONST(1)
+
+// Reset to CAR - generates 2 clock cycle  pulse. 
+#define APBDEV_PMC_CNTRL_0_MAIN_RST_SHIFT                       _MK_SHIFT_CONST(4)
+#define APBDEV_PMC_CNTRL_0_MAIN_RST_FIELD                       (_MK_MASK_CONST(0x1) << APBDEV_PMC_CNTRL_0_MAIN_RST_SHIFT)
+#define APBDEV_PMC_CNTRL_0_MAIN_RST_RANGE                       4:4
+#define APBDEV_PMC_CNTRL_0_MAIN_RST_WOFFSET                     0x0
+#define APBDEV_PMC_CNTRL_0_MAIN_RST_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_MAIN_RST_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_CNTRL_0_MAIN_RST_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_MAIN_RST_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_MAIN_RST_DISABLE                     _MK_ENUM_CONST(0)
+#define APBDEV_PMC_CNTRL_0_MAIN_RST_ENABLE                      _MK_ENUM_CONST(1)
+
+// Enables latching wakeup events - stops latching   on transition from 1 to 0(sequence - set to 1,set to 0) 
+#define APBDEV_PMC_CNTRL_0_LATCHWAKE_EN_SHIFT                   _MK_SHIFT_CONST(5)
+#define APBDEV_PMC_CNTRL_0_LATCHWAKE_EN_FIELD                   (_MK_MASK_CONST(0x1) << APBDEV_PMC_CNTRL_0_LATCHWAKE_EN_SHIFT)
+#define APBDEV_PMC_CNTRL_0_LATCHWAKE_EN_RANGE                   5:5
+#define APBDEV_PMC_CNTRL_0_LATCHWAKE_EN_WOFFSET                 0x0
+#define APBDEV_PMC_CNTRL_0_LATCHWAKE_EN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_LATCHWAKE_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_CNTRL_0_LATCHWAKE_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_LATCHWAKE_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_LATCHWAKE_EN_DISABLE                 _MK_ENUM_CONST(0)
+#define APBDEV_PMC_CNTRL_0_LATCHWAKE_EN_ENABLE                  _MK_ENUM_CONST(1)
+
+// Disable  detecting glitch on wakeup event- in default operation glitches are ignored on wakeup lines. if this bit is set to 1, glitch (event shorter than half 32khz clock, will be causing wakeup from lp0
+#define APBDEV_PMC_CNTRL_0_GLITCHDET_DIS_SHIFT                  _MK_SHIFT_CONST(6)
+#define APBDEV_PMC_CNTRL_0_GLITCHDET_DIS_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_PMC_CNTRL_0_GLITCHDET_DIS_SHIFT)
+#define APBDEV_PMC_CNTRL_0_GLITCHDET_DIS_RANGE                  6:6
+#define APBDEV_PMC_CNTRL_0_GLITCHDET_DIS_WOFFSET                        0x0
+#define APBDEV_PMC_CNTRL_0_GLITCHDET_DIS_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_GLITCHDET_DIS_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_CNTRL_0_GLITCHDET_DIS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_GLITCHDET_DIS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_GLITCHDET_DIS_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDEV_PMC_CNTRL_0_GLITCHDET_DIS_ENABLE                 _MK_ENUM_CONST(1)
+
+// Enables blinking counter and blink output -works only if BLINK field in DPD_PADS_ORIDE is set to 1
+#define APBDEV_PMC_CNTRL_0_BLINK_EN_SHIFT                       _MK_SHIFT_CONST(7)
+#define APBDEV_PMC_CNTRL_0_BLINK_EN_FIELD                       (_MK_MASK_CONST(0x1) << APBDEV_PMC_CNTRL_0_BLINK_EN_SHIFT)
+#define APBDEV_PMC_CNTRL_0_BLINK_EN_RANGE                       7:7
+#define APBDEV_PMC_CNTRL_0_BLINK_EN_WOFFSET                     0x0
+#define APBDEV_PMC_CNTRL_0_BLINK_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_BLINK_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_CNTRL_0_BLINK_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_BLINK_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_BLINK_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APBDEV_PMC_CNTRL_0_BLINK_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// Inverts power request polarity
+#define APBDEV_PMC_CNTRL_0_PWRREQ_POLARITY_SHIFT                        _MK_SHIFT_CONST(8)
+#define APBDEV_PMC_CNTRL_0_PWRREQ_POLARITY_FIELD                        (_MK_MASK_CONST(0x1) << APBDEV_PMC_CNTRL_0_PWRREQ_POLARITY_SHIFT)
+#define APBDEV_PMC_CNTRL_0_PWRREQ_POLARITY_RANGE                        8:8
+#define APBDEV_PMC_CNTRL_0_PWRREQ_POLARITY_WOFFSET                      0x0
+#define APBDEV_PMC_CNTRL_0_PWRREQ_POLARITY_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_PWRREQ_POLARITY_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_CNTRL_0_PWRREQ_POLARITY_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_PWRREQ_POLARITY_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_PWRREQ_POLARITY_NORMAL                       _MK_ENUM_CONST(0)
+#define APBDEV_PMC_CNTRL_0_PWRREQ_POLARITY_INVERT                       _MK_ENUM_CONST(1)
+
+// Power request output enable. resets to tristate
+#define APBDEV_PMC_CNTRL_0_PWRREQ_OE_SHIFT                      _MK_SHIFT_CONST(9)
+#define APBDEV_PMC_CNTRL_0_PWRREQ_OE_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_PMC_CNTRL_0_PWRREQ_OE_SHIFT)
+#define APBDEV_PMC_CNTRL_0_PWRREQ_OE_RANGE                      9:9
+#define APBDEV_PMC_CNTRL_0_PWRREQ_OE_WOFFSET                    0x0
+#define APBDEV_PMC_CNTRL_0_PWRREQ_OE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_PWRREQ_OE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_CNTRL_0_PWRREQ_OE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_PWRREQ_OE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_PWRREQ_OE_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_CNTRL_0_PWRREQ_OE_ENABLE                     _MK_ENUM_CONST(1)
+
+// Inverts system clock enable polarity 
+#define APBDEV_PMC_CNTRL_0_SYSCLK_POLARITY_SHIFT                        _MK_SHIFT_CONST(10)
+#define APBDEV_PMC_CNTRL_0_SYSCLK_POLARITY_FIELD                        (_MK_MASK_CONST(0x1) << APBDEV_PMC_CNTRL_0_SYSCLK_POLARITY_SHIFT)
+#define APBDEV_PMC_CNTRL_0_SYSCLK_POLARITY_RANGE                        10:10
+#define APBDEV_PMC_CNTRL_0_SYSCLK_POLARITY_WOFFSET                      0x0
+#define APBDEV_PMC_CNTRL_0_SYSCLK_POLARITY_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_SYSCLK_POLARITY_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_CNTRL_0_SYSCLK_POLARITY_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_SYSCLK_POLARITY_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_SYSCLK_POLARITY_NORMAL                       _MK_ENUM_CONST(0)
+#define APBDEV_PMC_CNTRL_0_SYSCLK_POLARITY_INVERT                       _MK_ENUM_CONST(1)
+
+// Enables output of system enable clock - works only if SYS_CLK field in DPD_PADS_ORIDE is set to 1. resets to tristate
+#define APBDEV_PMC_CNTRL_0_SYSCLK_OE_SHIFT                      _MK_SHIFT_CONST(11)
+#define APBDEV_PMC_CNTRL_0_SYSCLK_OE_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_PMC_CNTRL_0_SYSCLK_OE_SHIFT)
+#define APBDEV_PMC_CNTRL_0_SYSCLK_OE_RANGE                      11:11
+#define APBDEV_PMC_CNTRL_0_SYSCLK_OE_WOFFSET                    0x0
+#define APBDEV_PMC_CNTRL_0_SYSCLK_OE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_SYSCLK_OE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_CNTRL_0_SYSCLK_OE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_SYSCLK_OE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_SYSCLK_OE_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_CNTRL_0_SYSCLK_OE_ENABLE                     _MK_ENUM_CONST(1)
+
+// Disable  power gating - global override, will override function of PWRGATE_TOGGLE register. all partitions will stay enabled. 
+#define APBDEV_PMC_CNTRL_0_PWRGATE_DIS_SHIFT                    _MK_SHIFT_CONST(12)
+#define APBDEV_PMC_CNTRL_0_PWRGATE_DIS_FIELD                    (_MK_MASK_CONST(0x1) << APBDEV_PMC_CNTRL_0_PWRGATE_DIS_SHIFT)
+#define APBDEV_PMC_CNTRL_0_PWRGATE_DIS_RANGE                    12:12
+#define APBDEV_PMC_CNTRL_0_PWRGATE_DIS_WOFFSET                  0x0
+#define APBDEV_PMC_CNTRL_0_PWRGATE_DIS_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_PWRGATE_DIS_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_CNTRL_0_PWRGATE_DIS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_PWRGATE_DIS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_PWRGATE_DIS_DISABLE                  _MK_ENUM_CONST(0)
+#define APBDEV_PMC_CNTRL_0_PWRGATE_DIS_ENABLE                   _MK_ENUM_CONST(1)
+
+// AO intitlized  purely sftw diagnostic and interpretation
+#define APBDEV_PMC_CNTRL_0_AOINIT_SHIFT                 _MK_SHIFT_CONST(13)
+#define APBDEV_PMC_CNTRL_0_AOINIT_FIELD                 (_MK_MASK_CONST(0x1) << APBDEV_PMC_CNTRL_0_AOINIT_SHIFT)
+#define APBDEV_PMC_CNTRL_0_AOINIT_RANGE                 13:13
+#define APBDEV_PMC_CNTRL_0_AOINIT_WOFFSET                       0x0
+#define APBDEV_PMC_CNTRL_0_AOINIT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_AOINIT_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_CNTRL_0_AOINIT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_AOINIT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_AOINIT_NOTDONE                       _MK_ENUM_CONST(0)
+#define APBDEV_PMC_CNTRL_0_AOINIT_DONE                  _MK_ENUM_CONST(1)
+
+// when set causes side effect of entering lp0 after powering down cpu
+#define APBDEV_PMC_CNTRL_0_SIDE_EFFECT_LP0_SHIFT                        _MK_SHIFT_CONST(14)
+#define APBDEV_PMC_CNTRL_0_SIDE_EFFECT_LP0_FIELD                        (_MK_MASK_CONST(0x1) << APBDEV_PMC_CNTRL_0_SIDE_EFFECT_LP0_SHIFT)
+#define APBDEV_PMC_CNTRL_0_SIDE_EFFECT_LP0_RANGE                        14:14
+#define APBDEV_PMC_CNTRL_0_SIDE_EFFECT_LP0_WOFFSET                      0x0
+#define APBDEV_PMC_CNTRL_0_SIDE_EFFECT_LP0_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_SIDE_EFFECT_LP0_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_CNTRL_0_SIDE_EFFECT_LP0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_SIDE_EFFECT_LP0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_SIDE_EFFECT_LP0_DISABLE                      _MK_ENUM_CONST(0)
+#define APBDEV_PMC_CNTRL_0_SIDE_EFFECT_LP0_ENABLE                       _MK_ENUM_CONST(1)
+
+
+// Register APBDEV_PMC_SEC_DISABLE_0  
+#define APBDEV_PMC_SEC_DISABLE_0                        _MK_ADDR_CONST(0x4)
+#define APBDEV_PMC_SEC_DISABLE_0_WORD_COUNT                     0x1
+#define APBDEV_PMC_SEC_DISABLE_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SEC_DISABLE_0_RESET_MASK                     _MK_MASK_CONST(0x3)
+#define APBDEV_PMC_SEC_DISABLE_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SEC_DISABLE_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SEC_DISABLE_0_READ_MASK                      _MK_MASK_CONST(0x3)
+#define APBDEV_PMC_SEC_DISABLE_0_WRITE_MASK                     _MK_MASK_CONST(0x3)
+// disable write to secure registers
+#define APBDEV_PMC_SEC_DISABLE_0_WRITE_SHIFT                    _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SEC_DISABLE_0_WRITE_FIELD                    (_MK_MASK_CONST(0x1) << APBDEV_PMC_SEC_DISABLE_0_WRITE_SHIFT)
+#define APBDEV_PMC_SEC_DISABLE_0_WRITE_RANGE                    0:0
+#define APBDEV_PMC_SEC_DISABLE_0_WRITE_WOFFSET                  0x0
+#define APBDEV_PMC_SEC_DISABLE_0_WRITE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SEC_DISABLE_0_WRITE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_SEC_DISABLE_0_WRITE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SEC_DISABLE_0_WRITE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SEC_DISABLE_0_WRITE_OFF                      _MK_ENUM_CONST(0)
+#define APBDEV_PMC_SEC_DISABLE_0_WRITE_ON                       _MK_ENUM_CONST(1)
+
+// disable read  from  secure registers
+#define APBDEV_PMC_SEC_DISABLE_0_READ_SHIFT                     _MK_SHIFT_CONST(1)
+#define APBDEV_PMC_SEC_DISABLE_0_READ_FIELD                     (_MK_MASK_CONST(0x1) << APBDEV_PMC_SEC_DISABLE_0_READ_SHIFT)
+#define APBDEV_PMC_SEC_DISABLE_0_READ_RANGE                     1:1
+#define APBDEV_PMC_SEC_DISABLE_0_READ_WOFFSET                   0x0
+#define APBDEV_PMC_SEC_DISABLE_0_READ_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SEC_DISABLE_0_READ_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_SEC_DISABLE_0_READ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SEC_DISABLE_0_READ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SEC_DISABLE_0_READ_OFF                       _MK_ENUM_CONST(0)
+#define APBDEV_PMC_SEC_DISABLE_0_READ_ON                        _MK_ENUM_CONST(1)
+
+
+// Register APBDEV_PMC_PMC_SWRST_0  
+#define APBDEV_PMC_PMC_SWRST_0                  _MK_ADDR_CONST(0x8)
+#define APBDEV_PMC_PMC_SWRST_0_WORD_COUNT                       0x1
+#define APBDEV_PMC_PMC_SWRST_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PMC_SWRST_0_RESET_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PMC_SWRST_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PMC_SWRST_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PMC_SWRST_0_READ_MASK                        _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PMC_SWRST_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
+//software reset to pmc only
+#define APBDEV_PMC_PMC_SWRST_0_RST_SHIFT                        _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_PMC_SWRST_0_RST_FIELD                        (_MK_MASK_CONST(0x1) << APBDEV_PMC_PMC_SWRST_0_RST_SHIFT)
+#define APBDEV_PMC_PMC_SWRST_0_RST_RANGE                        0:0
+#define APBDEV_PMC_PMC_SWRST_0_RST_WOFFSET                      0x0
+#define APBDEV_PMC_PMC_SWRST_0_RST_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PMC_SWRST_0_RST_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PMC_SWRST_0_RST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PMC_SWRST_0_RST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PMC_SWRST_0_RST_DISABLE                      _MK_ENUM_CONST(0)
+#define APBDEV_PMC_PMC_SWRST_0_RST_ENABLE                       _MK_ENUM_CONST(1)
+
+
+// Register APBDEV_PMC_WAKE_MASK_0  
+#define APBDEV_PMC_WAKE_MASK_0                  _MK_ADDR_CONST(0xc)
+#define APBDEV_PMC_WAKE_MASK_0_WORD_COUNT                       0x1
+#define APBDEV_PMC_WAKE_MASK_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_MASK_0_RESET_MASK                       _MK_MASK_CONST(0xfffff)
+#define APBDEV_PMC_WAKE_MASK_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_MASK_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_MASK_0_READ_MASK                        _MK_MASK_CONST(0xfffff)
+#define APBDEV_PMC_WAKE_MASK_0_WRITE_MASK                       _MK_MASK_CONST(0xfffff)
+// pin  0-15  wake enable      
+#define APBDEV_PMC_WAKE_MASK_0_EVENT_SHIFT                      _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_WAKE_MASK_0_EVENT_FIELD                      (_MK_MASK_CONST(0xffff) << APBDEV_PMC_WAKE_MASK_0_EVENT_SHIFT)
+#define APBDEV_PMC_WAKE_MASK_0_EVENT_RANGE                      15:0
+#define APBDEV_PMC_WAKE_MASK_0_EVENT_WOFFSET                    0x0
+#define APBDEV_PMC_WAKE_MASK_0_EVENT_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_MASK_0_EVENT_DEFAULT_MASK                       _MK_MASK_CONST(0xffff)
+#define APBDEV_PMC_WAKE_MASK_0_EVENT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_MASK_0_EVENT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_MASK_0_EVENT_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_WAKE_MASK_0_EVENT_ENABLE                     _MK_ENUM_CONST(1)
+
+// RTC  wake enable                
+#define APBDEV_PMC_WAKE_MASK_0_RTC_SHIFT                        _MK_SHIFT_CONST(16)
+#define APBDEV_PMC_WAKE_MASK_0_RTC_FIELD                        (_MK_MASK_CONST(0x1) << APBDEV_PMC_WAKE_MASK_0_RTC_SHIFT)
+#define APBDEV_PMC_WAKE_MASK_0_RTC_RANGE                        16:16
+#define APBDEV_PMC_WAKE_MASK_0_RTC_WOFFSET                      0x0
+#define APBDEV_PMC_WAKE_MASK_0_RTC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_MASK_0_RTC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_WAKE_MASK_0_RTC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_MASK_0_RTC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_MASK_0_RTC_DISABLE                      _MK_ENUM_CONST(0)
+#define APBDEV_PMC_WAKE_MASK_0_RTC_ENABLE                       _MK_ENUM_CONST(1)
+
+// KBC  wake  enable                
+#define APBDEV_PMC_WAKE_MASK_0_KBC_SHIFT                        _MK_SHIFT_CONST(17)
+#define APBDEV_PMC_WAKE_MASK_0_KBC_FIELD                        (_MK_MASK_CONST(0x1) << APBDEV_PMC_WAKE_MASK_0_KBC_SHIFT)
+#define APBDEV_PMC_WAKE_MASK_0_KBC_RANGE                        17:17
+#define APBDEV_PMC_WAKE_MASK_0_KBC_WOFFSET                      0x0
+#define APBDEV_PMC_WAKE_MASK_0_KBC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_MASK_0_KBC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_WAKE_MASK_0_KBC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_MASK_0_KBC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_MASK_0_KBC_DISABLE                      _MK_ENUM_CONST(0)
+#define APBDEV_PMC_WAKE_MASK_0_KBC_ENABLE                       _MK_ENUM_CONST(1)
+
+// PWR_INT wake enable               
+#define APBDEV_PMC_WAKE_MASK_0_PWR_INT_SHIFT                    _MK_SHIFT_CONST(18)
+#define APBDEV_PMC_WAKE_MASK_0_PWR_INT_FIELD                    (_MK_MASK_CONST(0x1) << APBDEV_PMC_WAKE_MASK_0_PWR_INT_SHIFT)
+#define APBDEV_PMC_WAKE_MASK_0_PWR_INT_RANGE                    18:18
+#define APBDEV_PMC_WAKE_MASK_0_PWR_INT_WOFFSET                  0x0
+#define APBDEV_PMC_WAKE_MASK_0_PWR_INT_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_MASK_0_PWR_INT_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_WAKE_MASK_0_PWR_INT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_MASK_0_PWR_INT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_MASK_0_PWR_INT_DISABLE                  _MK_ENUM_CONST(0)
+#define APBDEV_PMC_WAKE_MASK_0_PWR_INT_ENABLE                   _MK_ENUM_CONST(1)
+
+// external reset  wake  enable                
+#define APBDEV_PMC_WAKE_MASK_0_RESET_N_SHIFT                    _MK_SHIFT_CONST(19)
+#define APBDEV_PMC_WAKE_MASK_0_RESET_N_FIELD                    (_MK_MASK_CONST(0x1) << APBDEV_PMC_WAKE_MASK_0_RESET_N_SHIFT)
+#define APBDEV_PMC_WAKE_MASK_0_RESET_N_RANGE                    19:19
+#define APBDEV_PMC_WAKE_MASK_0_RESET_N_WOFFSET                  0x0
+#define APBDEV_PMC_WAKE_MASK_0_RESET_N_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_MASK_0_RESET_N_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_WAKE_MASK_0_RESET_N_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_MASK_0_RESET_N_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_MASK_0_RESET_N_DISABLE                  _MK_ENUM_CONST(0)
+#define APBDEV_PMC_WAKE_MASK_0_RESET_N_ENABLE                   _MK_ENUM_CONST(1)
+
+
+// Register APBDEV_PMC_WAKE_LVL_0  
+#define APBDEV_PMC_WAKE_LVL_0                   _MK_ADDR_CONST(0x10)
+#define APBDEV_PMC_WAKE_LVL_0_WORD_COUNT                        0x1
+#define APBDEV_PMC_WAKE_LVL_0_RESET_VAL                         _MK_MASK_CONST(0x7ffff)
+#define APBDEV_PMC_WAKE_LVL_0_RESET_MASK                        _MK_MASK_CONST(0xfffff)
+#define APBDEV_PMC_WAKE_LVL_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_LVL_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_LVL_0_READ_MASK                         _MK_MASK_CONST(0xfffff)
+#define APBDEV_PMC_WAKE_LVL_0_WRITE_MASK                        _MK_MASK_CONST(0xfffff)
+// pin 0-15 wake  level       
+#define APBDEV_PMC_WAKE_LVL_0_EVENT_SHIFT                       _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_WAKE_LVL_0_EVENT_FIELD                       (_MK_MASK_CONST(0xffff) << APBDEV_PMC_WAKE_LVL_0_EVENT_SHIFT)
+#define APBDEV_PMC_WAKE_LVL_0_EVENT_RANGE                       15:0
+#define APBDEV_PMC_WAKE_LVL_0_EVENT_WOFFSET                     0x0
+#define APBDEV_PMC_WAKE_LVL_0_EVENT_DEFAULT                     _MK_MASK_CONST(0xffff)
+#define APBDEV_PMC_WAKE_LVL_0_EVENT_DEFAULT_MASK                        _MK_MASK_CONST(0xffff)
+#define APBDEV_PMC_WAKE_LVL_0_EVENT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_LVL_0_EVENT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_LVL_0_EVENT_ACTIVE_LOW                  _MK_ENUM_CONST(0)
+#define APBDEV_PMC_WAKE_LVL_0_EVENT_ACTIVE_HIGH                 _MK_ENUM_CONST(1)
+
+// RTC  wake  level               
+#define APBDEV_PMC_WAKE_LVL_0_RTC_SHIFT                 _MK_SHIFT_CONST(16)
+#define APBDEV_PMC_WAKE_LVL_0_RTC_FIELD                 (_MK_MASK_CONST(0x1) << APBDEV_PMC_WAKE_LVL_0_RTC_SHIFT)
+#define APBDEV_PMC_WAKE_LVL_0_RTC_RANGE                 16:16
+#define APBDEV_PMC_WAKE_LVL_0_RTC_WOFFSET                       0x0
+#define APBDEV_PMC_WAKE_LVL_0_RTC_DEFAULT                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_WAKE_LVL_0_RTC_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_WAKE_LVL_0_RTC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_LVL_0_RTC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_LVL_0_RTC_ACTIVE_LOW                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_WAKE_LVL_0_RTC_ACTIVE_HIGH                   _MK_ENUM_CONST(1)
+
+// KBC  wake level                
+#define APBDEV_PMC_WAKE_LVL_0_KBC_SHIFT                 _MK_SHIFT_CONST(17)
+#define APBDEV_PMC_WAKE_LVL_0_KBC_FIELD                 (_MK_MASK_CONST(0x1) << APBDEV_PMC_WAKE_LVL_0_KBC_SHIFT)
+#define APBDEV_PMC_WAKE_LVL_0_KBC_RANGE                 17:17
+#define APBDEV_PMC_WAKE_LVL_0_KBC_WOFFSET                       0x0
+#define APBDEV_PMC_WAKE_LVL_0_KBC_DEFAULT                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_WAKE_LVL_0_KBC_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_WAKE_LVL_0_KBC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_LVL_0_KBC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_LVL_0_KBC_ACTIVE_LOW                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_WAKE_LVL_0_KBC_ACTIVE_HIGH                   _MK_ENUM_CONST(1)
+
+// power interrupt - now pernamently tied to  bit 18            
+#define APBDEV_PMC_WAKE_LVL_0_PWR_INT_SHIFT                     _MK_SHIFT_CONST(18)
+#define APBDEV_PMC_WAKE_LVL_0_PWR_INT_FIELD                     (_MK_MASK_CONST(0x1) << APBDEV_PMC_WAKE_LVL_0_PWR_INT_SHIFT)
+#define APBDEV_PMC_WAKE_LVL_0_PWR_INT_RANGE                     18:18
+#define APBDEV_PMC_WAKE_LVL_0_PWR_INT_WOFFSET                   0x0
+#define APBDEV_PMC_WAKE_LVL_0_PWR_INT_DEFAULT                   _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_WAKE_LVL_0_PWR_INT_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_WAKE_LVL_0_PWR_INT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_LVL_0_PWR_INT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_LVL_0_PWR_INT_ACTIVE_LOW                        _MK_ENUM_CONST(0)
+#define APBDEV_PMC_WAKE_LVL_0_PWR_INT_ACTIVE_HIGH                       _MK_ENUM_CONST(1)
+
+// external reset wake level (low active!)              
+#define APBDEV_PMC_WAKE_LVL_0_RESET_N_SHIFT                     _MK_SHIFT_CONST(19)
+#define APBDEV_PMC_WAKE_LVL_0_RESET_N_FIELD                     (_MK_MASK_CONST(0x1) << APBDEV_PMC_WAKE_LVL_0_RESET_N_SHIFT)
+#define APBDEV_PMC_WAKE_LVL_0_RESET_N_RANGE                     19:19
+#define APBDEV_PMC_WAKE_LVL_0_RESET_N_WOFFSET                   0x0
+#define APBDEV_PMC_WAKE_LVL_0_RESET_N_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_LVL_0_RESET_N_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_WAKE_LVL_0_RESET_N_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_LVL_0_RESET_N_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_LVL_0_RESET_N_ACTIVE_LOW                        _MK_ENUM_CONST(0)
+#define APBDEV_PMC_WAKE_LVL_0_RESET_N_ACTIVE_HIGH                       _MK_ENUM_CONST(1)
+
+
+// Register APBDEV_PMC_WAKE_STATUS_0  
+#define APBDEV_PMC_WAKE_STATUS_0                        _MK_ADDR_CONST(0x14)
+#define APBDEV_PMC_WAKE_STATUS_0_WORD_COUNT                     0x1
+#define APBDEV_PMC_WAKE_STATUS_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_STATUS_0_RESET_MASK                     _MK_MASK_CONST(0xfffff)
+#define APBDEV_PMC_WAKE_STATUS_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_STATUS_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_STATUS_0_READ_MASK                      _MK_MASK_CONST(0xfffff)
+#define APBDEV_PMC_WAKE_STATUS_0_WRITE_MASK                     _MK_MASK_CONST(0xfffff)
+// pin 0-15 wake    
+#define APBDEV_PMC_WAKE_STATUS_0_EVENT_SHIFT                    _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_WAKE_STATUS_0_EVENT_FIELD                    (_MK_MASK_CONST(0xffff) << APBDEV_PMC_WAKE_STATUS_0_EVENT_SHIFT)
+#define APBDEV_PMC_WAKE_STATUS_0_EVENT_RANGE                    15:0
+#define APBDEV_PMC_WAKE_STATUS_0_EVENT_WOFFSET                  0x0
+#define APBDEV_PMC_WAKE_STATUS_0_EVENT_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_STATUS_0_EVENT_DEFAULT_MASK                     _MK_MASK_CONST(0xffff)
+#define APBDEV_PMC_WAKE_STATUS_0_EVENT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_STATUS_0_EVENT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_STATUS_0_EVENT_NOT_SET                  _MK_ENUM_CONST(0)
+#define APBDEV_PMC_WAKE_STATUS_0_EVENT_SET                      _MK_ENUM_CONST(1)
+
+// RTC wake                
+#define APBDEV_PMC_WAKE_STATUS_0_RTC_SHIFT                      _MK_SHIFT_CONST(16)
+#define APBDEV_PMC_WAKE_STATUS_0_RTC_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_PMC_WAKE_STATUS_0_RTC_SHIFT)
+#define APBDEV_PMC_WAKE_STATUS_0_RTC_RANGE                      16:16
+#define APBDEV_PMC_WAKE_STATUS_0_RTC_WOFFSET                    0x0
+#define APBDEV_PMC_WAKE_STATUS_0_RTC_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_STATUS_0_RTC_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_WAKE_STATUS_0_RTC_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_STATUS_0_RTC_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_STATUS_0_RTC_NOT_SET                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_WAKE_STATUS_0_RTC_SET                        _MK_ENUM_CONST(1)
+
+// KBC wake              
+#define APBDEV_PMC_WAKE_STATUS_0_KBC_SHIFT                      _MK_SHIFT_CONST(17)
+#define APBDEV_PMC_WAKE_STATUS_0_KBC_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_PMC_WAKE_STATUS_0_KBC_SHIFT)
+#define APBDEV_PMC_WAKE_STATUS_0_KBC_RANGE                      17:17
+#define APBDEV_PMC_WAKE_STATUS_0_KBC_WOFFSET                    0x0
+#define APBDEV_PMC_WAKE_STATUS_0_KBC_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_STATUS_0_KBC_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_WAKE_STATUS_0_KBC_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_STATUS_0_KBC_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_STATUS_0_KBC_NOT_SET                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_WAKE_STATUS_0_KBC_SET                        _MK_ENUM_CONST(1)
+
+// power interrupt            
+#define APBDEV_PMC_WAKE_STATUS_0_PWR_INT_SHIFT                  _MK_SHIFT_CONST(18)
+#define APBDEV_PMC_WAKE_STATUS_0_PWR_INT_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_PMC_WAKE_STATUS_0_PWR_INT_SHIFT)
+#define APBDEV_PMC_WAKE_STATUS_0_PWR_INT_RANGE                  18:18
+#define APBDEV_PMC_WAKE_STATUS_0_PWR_INT_WOFFSET                        0x0
+#define APBDEV_PMC_WAKE_STATUS_0_PWR_INT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_STATUS_0_PWR_INT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_WAKE_STATUS_0_PWR_INT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_STATUS_0_PWR_INT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_STATUS_0_PWR_INT_NOT_SET                        _MK_ENUM_CONST(0)
+#define APBDEV_PMC_WAKE_STATUS_0_PWR_INT_SET                    _MK_ENUM_CONST(1)
+
+// external reset            
+#define APBDEV_PMC_WAKE_STATUS_0_RESET_N_SHIFT                  _MK_SHIFT_CONST(19)
+#define APBDEV_PMC_WAKE_STATUS_0_RESET_N_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_PMC_WAKE_STATUS_0_RESET_N_SHIFT)
+#define APBDEV_PMC_WAKE_STATUS_0_RESET_N_RANGE                  19:19
+#define APBDEV_PMC_WAKE_STATUS_0_RESET_N_WOFFSET                        0x0
+#define APBDEV_PMC_WAKE_STATUS_0_RESET_N_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_STATUS_0_RESET_N_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_WAKE_STATUS_0_RESET_N_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_STATUS_0_RESET_N_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_STATUS_0_RESET_N_NOT_SET                        _MK_ENUM_CONST(0)
+#define APBDEV_PMC_WAKE_STATUS_0_RESET_N_SET                    _MK_ENUM_CONST(1)
+
+
+// Register APBDEV_PMC_SW_WAKE_STATUS_0  
+#define APBDEV_PMC_SW_WAKE_STATUS_0                     _MK_ADDR_CONST(0x18)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_WORD_COUNT                  0x1
+#define APBDEV_PMC_SW_WAKE_STATUS_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_RESET_MASK                  _MK_MASK_CONST(0xfffff)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_READ_MASK                   _MK_MASK_CONST(0xfffff)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_WRITE_MASK                  _MK_MASK_CONST(0xfffff)
+// pin 0-15 wake    
+#define APBDEV_PMC_SW_WAKE_STATUS_0_EVENT_SHIFT                 _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_EVENT_FIELD                 (_MK_MASK_CONST(0xffff) << APBDEV_PMC_SW_WAKE_STATUS_0_EVENT_SHIFT)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_EVENT_RANGE                 15:0
+#define APBDEV_PMC_SW_WAKE_STATUS_0_EVENT_WOFFSET                       0x0
+#define APBDEV_PMC_SW_WAKE_STATUS_0_EVENT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_EVENT_DEFAULT_MASK                  _MK_MASK_CONST(0xffff)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_EVENT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_EVENT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_EVENT_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_EVENT_ENABLE                        _MK_ENUM_CONST(1)
+
+// RTC wake                
+#define APBDEV_PMC_SW_WAKE_STATUS_0_RTC_SHIFT                   _MK_SHIFT_CONST(16)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_RTC_FIELD                   (_MK_MASK_CONST(0x1) << APBDEV_PMC_SW_WAKE_STATUS_0_RTC_SHIFT)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_RTC_RANGE                   16:16
+#define APBDEV_PMC_SW_WAKE_STATUS_0_RTC_WOFFSET                 0x0
+#define APBDEV_PMC_SW_WAKE_STATUS_0_RTC_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_RTC_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_RTC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_RTC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_RTC_DISABLE                 _MK_ENUM_CONST(0)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_RTC_ENABLE                  _MK_ENUM_CONST(1)
+
+// KBC wake              
+#define APBDEV_PMC_SW_WAKE_STATUS_0_KBC_SHIFT                   _MK_SHIFT_CONST(17)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_KBC_FIELD                   (_MK_MASK_CONST(0x1) << APBDEV_PMC_SW_WAKE_STATUS_0_KBC_SHIFT)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_KBC_RANGE                   17:17
+#define APBDEV_PMC_SW_WAKE_STATUS_0_KBC_WOFFSET                 0x0
+#define APBDEV_PMC_SW_WAKE_STATUS_0_KBC_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_KBC_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_KBC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_KBC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_KBC_DISABLE                 _MK_ENUM_CONST(0)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_KBC_ENABLE                  _MK_ENUM_CONST(1)
+
+// power interrupt            
+#define APBDEV_PMC_SW_WAKE_STATUS_0_PWR_INT_SHIFT                       _MK_SHIFT_CONST(18)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_PWR_INT_FIELD                       (_MK_MASK_CONST(0x1) << APBDEV_PMC_SW_WAKE_STATUS_0_PWR_INT_SHIFT)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_PWR_INT_RANGE                       18:18
+#define APBDEV_PMC_SW_WAKE_STATUS_0_PWR_INT_WOFFSET                     0x0
+#define APBDEV_PMC_SW_WAKE_STATUS_0_PWR_INT_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_PWR_INT_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_PWR_INT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_PWR_INT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_PWR_INT_NOT_SET                     _MK_ENUM_CONST(0)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_PWR_INT_SET                 _MK_ENUM_CONST(1)
+
+// external reset            
+#define APBDEV_PMC_SW_WAKE_STATUS_0_RESET_N_SHIFT                       _MK_SHIFT_CONST(19)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_RESET_N_FIELD                       (_MK_MASK_CONST(0x1) << APBDEV_PMC_SW_WAKE_STATUS_0_RESET_N_SHIFT)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_RESET_N_RANGE                       19:19
+#define APBDEV_PMC_SW_WAKE_STATUS_0_RESET_N_WOFFSET                     0x0
+#define APBDEV_PMC_SW_WAKE_STATUS_0_RESET_N_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_RESET_N_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_RESET_N_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_RESET_N_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_RESET_N_NOT_SET                     _MK_ENUM_CONST(0)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_RESET_N_SET                 _MK_ENUM_CONST(1)
+
+
+// Register APBDEV_PMC_DPD_PADS_ORIDE_0  
+#define APBDEV_PMC_DPD_PADS_ORIDE_0                     _MK_ADDR_CONST(0x1c)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_WORD_COUNT                  0x1
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_RESET_VAL                   _MK_MASK_CONST(0x200000)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_RESET_MASK                  _MK_MASK_CONST(0x3fffff)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_READ_MASK                   _MK_MASK_CONST(0x3fffff)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_WRITE_MASK                  _MK_MASK_CONST(0x3fffff)
+//override dpd idle state with column 0 output
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL0_SHIFT                      _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL0_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL0_SHIFT)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL0_RANGE                      0:0
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL0_WOFFSET                    0x0
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL0_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL0_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL0_ENABLE                     _MK_ENUM_CONST(1)
+
+//override dpd idle state with column 1 output
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL1_SHIFT                      _MK_SHIFT_CONST(1)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL1_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL1_SHIFT)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL1_RANGE                      1:1
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL1_WOFFSET                    0x0
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL1_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL1_ENABLE                     _MK_ENUM_CONST(1)
+
+//override dpd idle state with column 2 output
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL2_SHIFT                      _MK_SHIFT_CONST(2)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL2_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL2_SHIFT)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL2_RANGE                      2:2
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL2_WOFFSET                    0x0
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL2_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL2_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL2_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL2_ENABLE                     _MK_ENUM_CONST(1)
+
+//override dpd idle state with column 3 output
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL3_SHIFT                      _MK_SHIFT_CONST(3)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL3_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL3_SHIFT)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL3_RANGE                      3:3
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL3_WOFFSET                    0x0
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL3_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL3_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL3_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL3_ENABLE                     _MK_ENUM_CONST(1)
+
+//override dpd idle state with column 4 output
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL4_SHIFT                      _MK_SHIFT_CONST(4)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL4_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL4_SHIFT)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL4_RANGE                      4:4
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL4_WOFFSET                    0x0
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL4_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL4_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL4_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL4_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL4_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL4_ENABLE                     _MK_ENUM_CONST(1)
+
+//override dpd idle state with column 5 output
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL5_SHIFT                      _MK_SHIFT_CONST(5)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL5_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL5_SHIFT)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL5_RANGE                      5:5
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL5_WOFFSET                    0x0
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL5_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL5_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL5_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL5_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL5_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL5_ENABLE                     _MK_ENUM_CONST(1)
+
+//override dpd idle state with column 6 output
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL6_SHIFT                      _MK_SHIFT_CONST(6)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL6_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL6_SHIFT)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL6_RANGE                      6:6
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL6_WOFFSET                    0x0
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL6_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL6_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL6_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL6_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL6_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL6_ENABLE                     _MK_ENUM_CONST(1)
+
+//override dpd idle state with column 7 output
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL7_SHIFT                      _MK_SHIFT_CONST(7)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL7_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL7_SHIFT)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL7_RANGE                      7:7
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL7_WOFFSET                    0x0
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL7_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL7_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL7_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL7_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL7_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL7_ENABLE                     _MK_ENUM_CONST(1)
+
+//override dpd idle state with column 8 output
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL8_SHIFT                      _MK_SHIFT_CONST(8)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL8_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL8_SHIFT)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL8_RANGE                      8:8
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL8_WOFFSET                    0x0
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL8_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL8_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL8_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL8_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL8_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL8_ENABLE                     _MK_ENUM_CONST(1)
+
+//override dpd idle state with column 9 output
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL9_SHIFT                      _MK_SHIFT_CONST(9)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL9_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL9_SHIFT)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL9_RANGE                      9:9
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL9_WOFFSET                    0x0
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL9_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL9_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL9_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL9_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL9_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL9_ENABLE                     _MK_ENUM_CONST(1)
+
+//override dpd idle state with column 10 output
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL10_SHIFT                     _MK_SHIFT_CONST(10)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL10_FIELD                     (_MK_MASK_CONST(0x1) << APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL10_SHIFT)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL10_RANGE                     10:10
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL10_WOFFSET                   0x0
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL10_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL10_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL10_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL10_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL10_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL10_ENABLE                    _MK_ENUM_CONST(1)
+
+//override dpd idle state with column 11 output
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL11_SHIFT                     _MK_SHIFT_CONST(11)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL11_FIELD                     (_MK_MASK_CONST(0x1) << APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL11_SHIFT)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL11_RANGE                     11:11
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL11_WOFFSET                   0x0
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL11_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL11_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL11_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL11_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL11_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL11_ENABLE                    _MK_ENUM_CONST(1)
+
+//override dpd idle state with column 12 output
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL12_SHIFT                     _MK_SHIFT_CONST(12)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL12_FIELD                     (_MK_MASK_CONST(0x1) << APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL12_SHIFT)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL12_RANGE                     12:12
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL12_WOFFSET                   0x0
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL12_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL12_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL12_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL12_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL12_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL12_ENABLE                    _MK_ENUM_CONST(1)
+
+//override dpd idle state with row 0  output
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW0_SHIFT                      _MK_SHIFT_CONST(13)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW0_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW0_SHIFT)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW0_RANGE                      13:13
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW0_WOFFSET                    0x0
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW0_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW0_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW0_ENABLE                     _MK_ENUM_CONST(1)
+
+//override dpd idle state with row 1  output
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW1_SHIFT                      _MK_SHIFT_CONST(14)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW1_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW1_SHIFT)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW1_RANGE                      14:14
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW1_WOFFSET                    0x0
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW1_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW1_ENABLE                     _MK_ENUM_CONST(1)
+
+//override dpd idle state with row 2  output
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW2_SHIFT                      _MK_SHIFT_CONST(15)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW2_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW2_SHIFT)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW2_RANGE                      15:15
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW2_WOFFSET                    0x0
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW2_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW2_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW2_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW2_ENABLE                     _MK_ENUM_CONST(1)
+
+//override dpd idle state with row 3  output
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW3_SHIFT                      _MK_SHIFT_CONST(16)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW3_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW3_SHIFT)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW3_RANGE                      16:16
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW3_WOFFSET                    0x0
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW3_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW3_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW3_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW3_ENABLE                     _MK_ENUM_CONST(1)
+
+//override dpd idle state with row 4  output
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW4_SHIFT                      _MK_SHIFT_CONST(17)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW4_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW4_SHIFT)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW4_RANGE                      17:17
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW4_WOFFSET                    0x0
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW4_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW4_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW4_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW4_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW4_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW4_ENABLE                     _MK_ENUM_CONST(1)
+
+//override dpd idle state with row 5  output
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW5_SHIFT                      _MK_SHIFT_CONST(18)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW5_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW5_SHIFT)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW5_RANGE                      18:18
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW5_WOFFSET                    0x0
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW5_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW5_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW5_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW5_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW5_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW5_ENABLE                     _MK_ENUM_CONST(1)
+
+//override dpd idle state with row 6  output
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW6_SHIFT                      _MK_SHIFT_CONST(19)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW6_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW6_SHIFT)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW6_RANGE                      19:19
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW6_WOFFSET                    0x0
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW6_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW6_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW6_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW6_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW6_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW6_ENABLE                     _MK_ENUM_CONST(1)
+
+//override dpd idle state with blink ouptut
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_BLINK_SHIFT                 _MK_SHIFT_CONST(20)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_BLINK_FIELD                 (_MK_MASK_CONST(0x1) << APBDEV_PMC_DPD_PADS_ORIDE_0_BLINK_SHIFT)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_BLINK_RANGE                 20:20
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_BLINK_WOFFSET                       0x0
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_BLINK_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_BLINK_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_BLINK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_BLINK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_BLINK_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_BLINK_ENABLE                        _MK_ENUM_CONST(1)
+
+//override dpd idle state with column with sys_clk_request output
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_SYS_CLK_SHIFT                       _MK_SHIFT_CONST(21)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_SYS_CLK_FIELD                       (_MK_MASK_CONST(0x1) << APBDEV_PMC_DPD_PADS_ORIDE_0_SYS_CLK_SHIFT)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_SYS_CLK_RANGE                       21:21
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_SYS_CLK_WOFFSET                     0x0
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_SYS_CLK_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_SYS_CLK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_SYS_CLK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_SYS_CLK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_SYS_CLK_DISABLE                     _MK_ENUM_CONST(0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_SYS_CLK_ENABLE                      _MK_ENUM_CONST(1)
+
+
+// Register APBDEV_PMC_DPD_SAMPLE_0  
+#define APBDEV_PMC_DPD_SAMPLE_0                 _MK_ADDR_CONST(0x20)
+#define APBDEV_PMC_DPD_SAMPLE_0_WORD_COUNT                      0x1
+#define APBDEV_PMC_DPD_SAMPLE_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_SAMPLE_0_RESET_MASK                      _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_SAMPLE_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_SAMPLE_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_SAMPLE_0_READ_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_SAMPLE_0_WRITE_MASK                      _MK_MASK_CONST(0x1)
+// will set sampling of pads value
+#define APBDEV_PMC_DPD_SAMPLE_0_ON_SHIFT                        _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_DPD_SAMPLE_0_ON_FIELD                        (_MK_MASK_CONST(0x1) << APBDEV_PMC_DPD_SAMPLE_0_ON_SHIFT)
+#define APBDEV_PMC_DPD_SAMPLE_0_ON_RANGE                        0:0
+#define APBDEV_PMC_DPD_SAMPLE_0_ON_WOFFSET                      0x0
+#define APBDEV_PMC_DPD_SAMPLE_0_ON_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_SAMPLE_0_ON_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_SAMPLE_0_ON_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_SAMPLE_0_ON_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_SAMPLE_0_ON_DISABLE                      _MK_ENUM_CONST(0)
+#define APBDEV_PMC_DPD_SAMPLE_0_ON_ENABLE                       _MK_ENUM_CONST(1)
+
+
+// Register APBDEV_PMC_DPD_ENABLE_0  
+#define APBDEV_PMC_DPD_ENABLE_0                 _MK_ADDR_CONST(0x24)
+#define APBDEV_PMC_DPD_ENABLE_0_WORD_COUNT                      0x1
+#define APBDEV_PMC_DPD_ENABLE_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_ENABLE_0_RESET_MASK                      _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_ENABLE_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_ENABLE_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_ENABLE_0_READ_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_ENABLE_0_WRITE_MASK                      _MK_MASK_CONST(0x1)
+// will set sampling of pads value
+#define APBDEV_PMC_DPD_ENABLE_0_ON_SHIFT                        _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_DPD_ENABLE_0_ON_FIELD                        (_MK_MASK_CONST(0x1) << APBDEV_PMC_DPD_ENABLE_0_ON_SHIFT)
+#define APBDEV_PMC_DPD_ENABLE_0_ON_RANGE                        0:0
+#define APBDEV_PMC_DPD_ENABLE_0_ON_WOFFSET                      0x0
+#define APBDEV_PMC_DPD_ENABLE_0_ON_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_ENABLE_0_ON_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_ENABLE_0_ON_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_ENABLE_0_ON_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_ENABLE_0_ON_DISABLE                      _MK_ENUM_CONST(0)
+#define APBDEV_PMC_DPD_ENABLE_0_ON_ENABLE                       _MK_ENUM_CONST(1)
+
+
+// Register APBDEV_PMC_PWRGATE_TIMER_OFF_0  
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0                  _MK_ADDR_CONST(0x28)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_WORD_COUNT                       0x1
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RESET_VAL                        _MK_MASK_CONST(0xeca97531)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+// timer value for rail 0
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL0_SHIFT                      _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL0_FIELD                      (_MK_MASK_CONST(0xf) << APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL0_SHIFT)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL0_RANGE                      3:0
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL0_WOFFSET                    0x0
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL0_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL0_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// timer value for rail 1
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL1_SHIFT                      _MK_SHIFT_CONST(4)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL1_FIELD                      (_MK_MASK_CONST(0xf) << APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL1_SHIFT)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL1_RANGE                      7:4
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL1_WOFFSET                    0x0
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL1_DEFAULT                    _MK_MASK_CONST(0x3)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL1_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// timer value for rail 2
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL2_SHIFT                      _MK_SHIFT_CONST(8)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL2_FIELD                      (_MK_MASK_CONST(0xf) << APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL2_SHIFT)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL2_RANGE                      11:8
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL2_WOFFSET                    0x0
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL2_DEFAULT                    _MK_MASK_CONST(0x5)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL2_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// timer value for rail 3
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL3_SHIFT                      _MK_SHIFT_CONST(12)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL3_FIELD                      (_MK_MASK_CONST(0xf) << APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL3_SHIFT)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL3_RANGE                      15:12
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL3_WOFFSET                    0x0
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL3_DEFAULT                    _MK_MASK_CONST(0x7)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL3_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// timer value for rail 4
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL4_SHIFT                      _MK_SHIFT_CONST(16)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL4_FIELD                      (_MK_MASK_CONST(0xf) << APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL4_SHIFT)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL4_RANGE                      19:16
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL4_WOFFSET                    0x0
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL4_DEFAULT                    _MK_MASK_CONST(0x9)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL4_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL4_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL4_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// timer value for rail 5
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL5_SHIFT                      _MK_SHIFT_CONST(20)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL5_FIELD                      (_MK_MASK_CONST(0xf) << APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL5_SHIFT)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL5_RANGE                      23:20
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL5_WOFFSET                    0x0
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL5_DEFAULT                    _MK_MASK_CONST(0xa)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL5_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL5_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL5_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// timer value for rail 6
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL6_SHIFT                      _MK_SHIFT_CONST(24)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL6_FIELD                      (_MK_MASK_CONST(0xf) << APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL6_SHIFT)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL6_RANGE                      27:24
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL6_WOFFSET                    0x0
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL6_DEFAULT                    _MK_MASK_CONST(0xc)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL6_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL6_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL6_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// timer value for rail 7
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL7_SHIFT                      _MK_SHIFT_CONST(28)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL7_FIELD                      (_MK_MASK_CONST(0xf) << APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL7_SHIFT)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL7_RANGE                      31:28
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL7_WOFFSET                    0x0
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL7_DEFAULT                    _MK_MASK_CONST(0xe)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL7_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL7_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL7_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_PWRGATE_TIMER_ON_0  
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0                   _MK_ADDR_CONST(0x2c)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_WORD_COUNT                        0x1
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RESET_VAL                         _MK_MASK_CONST(0xeca97531)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
+// timer value for rail 0
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL0_SHIFT                       _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL0_FIELD                       (_MK_MASK_CONST(0xf) << APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL0_SHIFT)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL0_RANGE                       3:0
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL0_WOFFSET                     0x0
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL0_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL0_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// timer value for rail 1
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL1_SHIFT                       _MK_SHIFT_CONST(4)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL1_FIELD                       (_MK_MASK_CONST(0xf) << APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL1_SHIFT)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL1_RANGE                       7:4
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL1_WOFFSET                     0x0
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL1_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL1_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// timer value for rail 2
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL2_SHIFT                       _MK_SHIFT_CONST(8)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL2_FIELD                       (_MK_MASK_CONST(0xf) << APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL2_SHIFT)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL2_RANGE                       11:8
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL2_WOFFSET                     0x0
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL2_DEFAULT                     _MK_MASK_CONST(0x5)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL2_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// timer value for rail 3
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL3_SHIFT                       _MK_SHIFT_CONST(12)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL3_FIELD                       (_MK_MASK_CONST(0xf) << APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL3_SHIFT)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL3_RANGE                       15:12
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL3_WOFFSET                     0x0
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL3_DEFAULT                     _MK_MASK_CONST(0x7)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL3_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// timer value for rail 4
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL4_SHIFT                       _MK_SHIFT_CONST(16)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL4_FIELD                       (_MK_MASK_CONST(0xf) << APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL4_SHIFT)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL4_RANGE                       19:16
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL4_WOFFSET                     0x0
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL4_DEFAULT                     _MK_MASK_CONST(0x9)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL4_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// timer value for rail 5
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL5_SHIFT                       _MK_SHIFT_CONST(20)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL5_FIELD                       (_MK_MASK_CONST(0xf) << APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL5_SHIFT)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL5_RANGE                       23:20
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL5_WOFFSET                     0x0
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL5_DEFAULT                     _MK_MASK_CONST(0xa)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL5_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// timer value for rail 6
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL6_SHIFT                       _MK_SHIFT_CONST(24)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL6_FIELD                       (_MK_MASK_CONST(0xf) << APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL6_SHIFT)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL6_RANGE                       27:24
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL6_WOFFSET                     0x0
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL6_DEFAULT                     _MK_MASK_CONST(0xc)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL6_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// timer value for rail 7
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL7_SHIFT                       _MK_SHIFT_CONST(28)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL7_FIELD                       (_MK_MASK_CONST(0xf) << APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL7_SHIFT)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL7_RANGE                       31:28
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL7_WOFFSET                     0x0
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL7_DEFAULT                     _MK_MASK_CONST(0xe)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL7_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_PWRGATE_TOGGLE_0  
+#define APBDEV_PMC_PWRGATE_TOGGLE_0                     _MK_ADDR_CONST(0x30)
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_WORD_COUNT                  0x1
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_RESET_MASK                  _MK_MASK_CONST(0x103)
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_READ_MASK                   _MK_MASK_CONST(0x103)
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_WRITE_MASK                  _MK_MASK_CONST(0x103)
+//id of partition to be toggled 
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_PARTID_SHIFT                        _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_PARTID_FIELD                        (_MK_MASK_CONST(0x3) << APBDEV_PMC_PWRGATE_TOGGLE_0_PARTID_SHIFT)
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_PARTID_RANGE                        1:0
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_PARTID_WOFFSET                      0x0
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_PARTID_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_PARTID_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_PARTID_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_PARTID_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_PARTID_CP                   _MK_ENUM_CONST(0)
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_PARTID_TD                   _MK_ENUM_CONST(1)
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_PARTID_VE                   _MK_ENUM_CONST(2)
+
+//start power down/up
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_START_SHIFT                 _MK_SHIFT_CONST(8)
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_START_FIELD                 (_MK_MASK_CONST(0x1) << APBDEV_PMC_PWRGATE_TOGGLE_0_START_SHIFT)
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_START_RANGE                 8:8
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_START_WOFFSET                       0x0
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_START_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_START_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_START_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_START_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_START_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_START_ENABLE                        _MK_ENUM_CONST(1)
+
+
+// Register APBDEV_PMC_REMOVE_CLAMPING_CMD_0  
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0                        _MK_ADDR_CONST(0x34)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_WORD_COUNT                     0x1
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_RESET_MASK                     _MK_MASK_CONST(0x7)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_READ_MASK                      _MK_MASK_CONST(0x7)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_WRITE_MASK                     _MK_MASK_CONST(0x7)
+//remove clamping to CPU
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_CPU_SHIFT                      _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_CPU_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_PMC_REMOVE_CLAMPING_CMD_0_CPU_SHIFT)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_CPU_RANGE                      0:0
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_CPU_WOFFSET                    0x0
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_CPU_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_CPU_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_CPU_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_CPU_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_CPU_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_CPU_ENABLE                     _MK_ENUM_CONST(1)
+
+//remove clamping to TD
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_TD_SHIFT                       _MK_SHIFT_CONST(1)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_TD_FIELD                       (_MK_MASK_CONST(0x1) << APBDEV_PMC_REMOVE_CLAMPING_CMD_0_TD_SHIFT)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_TD_RANGE                       1:1
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_TD_WOFFSET                     0x0
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_TD_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_TD_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_TD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_TD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_TD_DISABLE                     _MK_ENUM_CONST(0)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_TD_ENABLE                      _MK_ENUM_CONST(1)
+
+//remove clamping to VE
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_VE_SHIFT                       _MK_SHIFT_CONST(2)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_VE_FIELD                       (_MK_MASK_CONST(0x1) << APBDEV_PMC_REMOVE_CLAMPING_CMD_0_VE_SHIFT)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_VE_RANGE                       2:2
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_VE_WOFFSET                     0x0
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_VE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_VE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_VE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_VE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_VE_DISABLE                     _MK_ENUM_CONST(0)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_VE_ENABLE                      _MK_ENUM_CONST(1)
+
+
+// Register APBDEV_PMC_PWRGATE_STATUS_0  
+#define APBDEV_PMC_PWRGATE_STATUS_0                     _MK_ADDR_CONST(0x38)
+#define APBDEV_PMC_PWRGATE_STATUS_0_WORD_COUNT                  0x1
+#define APBDEV_PMC_PWRGATE_STATUS_0_RESET_VAL                   _MK_MASK_CONST(0x7)
+#define APBDEV_PMC_PWRGATE_STATUS_0_RESET_MASK                  _MK_MASK_CONST(0x7)
+#define APBDEV_PMC_PWRGATE_STATUS_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_STATUS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_STATUS_0_READ_MASK                   _MK_MASK_CONST(0x7)
+#define APBDEV_PMC_PWRGATE_STATUS_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+//status of CPU partition
+#define APBDEV_PMC_PWRGATE_STATUS_0_CPU_SHIFT                   _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_PWRGATE_STATUS_0_CPU_FIELD                   (_MK_MASK_CONST(0x1) << APBDEV_PMC_PWRGATE_STATUS_0_CPU_SHIFT)
+#define APBDEV_PMC_PWRGATE_STATUS_0_CPU_RANGE                   0:0
+#define APBDEV_PMC_PWRGATE_STATUS_0_CPU_WOFFSET                 0x0
+#define APBDEV_PMC_PWRGATE_STATUS_0_CPU_DEFAULT                 _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWRGATE_STATUS_0_CPU_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWRGATE_STATUS_0_CPU_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_STATUS_0_CPU_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_STATUS_0_CPU_OFF                     _MK_ENUM_CONST(0)
+#define APBDEV_PMC_PWRGATE_STATUS_0_CPU_ON                      _MK_ENUM_CONST(1)
+
+//status of TD  Partition
+#define APBDEV_PMC_PWRGATE_STATUS_0_TD_SHIFT                    _MK_SHIFT_CONST(1)
+#define APBDEV_PMC_PWRGATE_STATUS_0_TD_FIELD                    (_MK_MASK_CONST(0x1) << APBDEV_PMC_PWRGATE_STATUS_0_TD_SHIFT)
+#define APBDEV_PMC_PWRGATE_STATUS_0_TD_RANGE                    1:1
+#define APBDEV_PMC_PWRGATE_STATUS_0_TD_WOFFSET                  0x0
+#define APBDEV_PMC_PWRGATE_STATUS_0_TD_DEFAULT                  _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWRGATE_STATUS_0_TD_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWRGATE_STATUS_0_TD_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_STATUS_0_TD_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_STATUS_0_TD_OFF                      _MK_ENUM_CONST(0)
+#define APBDEV_PMC_PWRGATE_STATUS_0_TD_ON                       _MK_ENUM_CONST(1)
+
+//status of VE  partition
+#define APBDEV_PMC_PWRGATE_STATUS_0_VE_SHIFT                    _MK_SHIFT_CONST(2)
+#define APBDEV_PMC_PWRGATE_STATUS_0_VE_FIELD                    (_MK_MASK_CONST(0x1) << APBDEV_PMC_PWRGATE_STATUS_0_VE_SHIFT)
+#define APBDEV_PMC_PWRGATE_STATUS_0_VE_RANGE                    2:2
+#define APBDEV_PMC_PWRGATE_STATUS_0_VE_WOFFSET                  0x0
+#define APBDEV_PMC_PWRGATE_STATUS_0_VE_DEFAULT                  _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWRGATE_STATUS_0_VE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWRGATE_STATUS_0_VE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_STATUS_0_VE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_STATUS_0_VE_OFF                      _MK_ENUM_CONST(0)
+#define APBDEV_PMC_PWRGATE_STATUS_0_VE_ON                       _MK_ENUM_CONST(1)
+
+
+// Register APBDEV_PMC_PWRGOOD_TIMER_0  
+#define APBDEV_PMC_PWRGOOD_TIMER_0                      _MK_ADDR_CONST(0x3c)
+#define APBDEV_PMC_PWRGOOD_TIMER_0_WORD_COUNT                   0x1
+#define APBDEV_PMC_PWRGOOD_TIMER_0_RESET_VAL                    _MK_MASK_CONST(0x7f)
+#define APBDEV_PMC_PWRGOOD_TIMER_0_RESET_MASK                   _MK_MASK_CONST(0x7f)
+#define APBDEV_PMC_PWRGOOD_TIMER_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGOOD_TIMER_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGOOD_TIMER_0_READ_MASK                    _MK_MASK_CONST(0x7f)
+#define APBDEV_PMC_PWRGOOD_TIMER_0_WRITE_MASK                   _MK_MASK_CONST(0x7f)
+// timer data
+#define APBDEV_PMC_PWRGOOD_TIMER_0_DATA_SHIFT                   _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_PWRGOOD_TIMER_0_DATA_FIELD                   (_MK_MASK_CONST(0x7f) << APBDEV_PMC_PWRGOOD_TIMER_0_DATA_SHIFT)
+#define APBDEV_PMC_PWRGOOD_TIMER_0_DATA_RANGE                   6:0
+#define APBDEV_PMC_PWRGOOD_TIMER_0_DATA_WOFFSET                 0x0
+#define APBDEV_PMC_PWRGOOD_TIMER_0_DATA_DEFAULT                 _MK_MASK_CONST(0x7f)
+#define APBDEV_PMC_PWRGOOD_TIMER_0_DATA_DEFAULT_MASK                    _MK_MASK_CONST(0x7f)
+#define APBDEV_PMC_PWRGOOD_TIMER_0_DATA_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGOOD_TIMER_0_DATA_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_BLINK_TIMER_0  
+#define APBDEV_PMC_BLINK_TIMER_0                        _MK_ADDR_CONST(0x40)
+#define APBDEV_PMC_BLINK_TIMER_0_WORD_COUNT                     0x1
+#define APBDEV_PMC_BLINK_TIMER_0_RESET_VAL                      _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_BLINK_TIMER_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_BLINK_TIMER_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_BLINK_TIMER_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_BLINK_TIMER_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_BLINK_TIMER_0_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
+// time on 
+#define APBDEV_PMC_BLINK_TIMER_0_DATA_ON_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_BLINK_TIMER_0_DATA_ON_FIELD                  (_MK_MASK_CONST(0x7fff) << APBDEV_PMC_BLINK_TIMER_0_DATA_ON_SHIFT)
+#define APBDEV_PMC_BLINK_TIMER_0_DATA_ON_RANGE                  14:0
+#define APBDEV_PMC_BLINK_TIMER_0_DATA_ON_WOFFSET                        0x0
+#define APBDEV_PMC_BLINK_TIMER_0_DATA_ON_DEFAULT                        _MK_MASK_CONST(0x7fff)
+#define APBDEV_PMC_BLINK_TIMER_0_DATA_ON_DEFAULT_MASK                   _MK_MASK_CONST(0x7fff)
+#define APBDEV_PMC_BLINK_TIMER_0_DATA_ON_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_BLINK_TIMER_0_DATA_ON_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// if 0 32khz clock 
+#define APBDEV_PMC_BLINK_TIMER_0_FORCE_BLINK_SHIFT                      _MK_SHIFT_CONST(15)
+#define APBDEV_PMC_BLINK_TIMER_0_FORCE_BLINK_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_PMC_BLINK_TIMER_0_FORCE_BLINK_SHIFT)
+#define APBDEV_PMC_BLINK_TIMER_0_FORCE_BLINK_RANGE                      15:15
+#define APBDEV_PMC_BLINK_TIMER_0_FORCE_BLINK_WOFFSET                    0x0
+#define APBDEV_PMC_BLINK_TIMER_0_FORCE_BLINK_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_BLINK_TIMER_0_FORCE_BLINK_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_BLINK_TIMER_0_FORCE_BLINK_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_BLINK_TIMER_0_FORCE_BLINK_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// time off         
+#define APBDEV_PMC_BLINK_TIMER_0_DATA_OFF_SHIFT                 _MK_SHIFT_CONST(16)
+#define APBDEV_PMC_BLINK_TIMER_0_DATA_OFF_FIELD                 (_MK_MASK_CONST(0xffff) << APBDEV_PMC_BLINK_TIMER_0_DATA_OFF_SHIFT)
+#define APBDEV_PMC_BLINK_TIMER_0_DATA_OFF_RANGE                 31:16
+#define APBDEV_PMC_BLINK_TIMER_0_DATA_OFF_WOFFSET                       0x0
+#define APBDEV_PMC_BLINK_TIMER_0_DATA_OFF_DEFAULT                       _MK_MASK_CONST(0xffff)
+#define APBDEV_PMC_BLINK_TIMER_0_DATA_OFF_DEFAULT_MASK                  _MK_MASK_CONST(0xffff)
+#define APBDEV_PMC_BLINK_TIMER_0_DATA_OFF_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_BLINK_TIMER_0_DATA_OFF_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_NO_IOPOWER_0  
+#define APBDEV_PMC_NO_IOPOWER_0                 _MK_ADDR_CONST(0x44)
+#define APBDEV_PMC_NO_IOPOWER_0_WORD_COUNT                      0x1
+#define APBDEV_PMC_NO_IOPOWER_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_RESET_MASK                      _MK_MASK_CONST(0x3ff)
+#define APBDEV_PMC_NO_IOPOWER_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_READ_MASK                       _MK_MASK_CONST(0x3ff)
+#define APBDEV_PMC_NO_IOPOWER_0_WRITE_MASK                      _MK_MASK_CONST(0x3ff)
+//rail ao IOs   
+#define APBDEV_PMC_NO_IOPOWER_0_AO_SHIFT                        _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_NO_IOPOWER_0_AO_FIELD                        (_MK_MASK_CONST(0x1) << APBDEV_PMC_NO_IOPOWER_0_AO_SHIFT)
+#define APBDEV_PMC_NO_IOPOWER_0_AO_RANGE                        0:0
+#define APBDEV_PMC_NO_IOPOWER_0_AO_WOFFSET                      0x0
+#define APBDEV_PMC_NO_IOPOWER_0_AO_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_AO_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_NO_IOPOWER_0_AO_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_AO_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_AO_DISABLE                      _MK_ENUM_CONST(0)
+#define APBDEV_PMC_NO_IOPOWER_0_AO_ENABLE                       _MK_ENUM_CONST(1)
+
+//rail at3 IOs 
+#define APBDEV_PMC_NO_IOPOWER_0_AT3_SHIFT                       _MK_SHIFT_CONST(1)
+#define APBDEV_PMC_NO_IOPOWER_0_AT3_FIELD                       (_MK_MASK_CONST(0x1) << APBDEV_PMC_NO_IOPOWER_0_AT3_SHIFT)
+#define APBDEV_PMC_NO_IOPOWER_0_AT3_RANGE                       1:1
+#define APBDEV_PMC_NO_IOPOWER_0_AT3_WOFFSET                     0x0
+#define APBDEV_PMC_NO_IOPOWER_0_AT3_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_AT3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_NO_IOPOWER_0_AT3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_AT3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_AT3_DISABLE                     _MK_ENUM_CONST(0)
+#define APBDEV_PMC_NO_IOPOWER_0_AT3_ENABLE                      _MK_ENUM_CONST(1)
+
+//rail dbg IOs   
+#define APBDEV_PMC_NO_IOPOWER_0_DBG_SHIFT                       _MK_SHIFT_CONST(2)
+#define APBDEV_PMC_NO_IOPOWER_0_DBG_FIELD                       (_MK_MASK_CONST(0x1) << APBDEV_PMC_NO_IOPOWER_0_DBG_SHIFT)
+#define APBDEV_PMC_NO_IOPOWER_0_DBG_RANGE                       2:2
+#define APBDEV_PMC_NO_IOPOWER_0_DBG_WOFFSET                     0x0
+#define APBDEV_PMC_NO_IOPOWER_0_DBG_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_DBG_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_NO_IOPOWER_0_DBG_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_DBG_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_DBG_DISABLE                     _MK_ENUM_CONST(0)
+#define APBDEV_PMC_NO_IOPOWER_0_DBG_ENABLE                      _MK_ENUM_CONST(1)
+
+//rail dlcd IOs   
+#define APBDEV_PMC_NO_IOPOWER_0_DLCD_SHIFT                      _MK_SHIFT_CONST(3)
+#define APBDEV_PMC_NO_IOPOWER_0_DLCD_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_PMC_NO_IOPOWER_0_DLCD_SHIFT)
+#define APBDEV_PMC_NO_IOPOWER_0_DLCD_RANGE                      3:3
+#define APBDEV_PMC_NO_IOPOWER_0_DLCD_WOFFSET                    0x0
+#define APBDEV_PMC_NO_IOPOWER_0_DLCD_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_DLCD_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_NO_IOPOWER_0_DLCD_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_DLCD_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_DLCD_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_NO_IOPOWER_0_DLCD_ENABLE                     _MK_ENUM_CONST(1)
+
+//rail dvi IOs   
+#define APBDEV_PMC_NO_IOPOWER_0_DVI_SHIFT                       _MK_SHIFT_CONST(4)
+#define APBDEV_PMC_NO_IOPOWER_0_DVI_FIELD                       (_MK_MASK_CONST(0x1) << APBDEV_PMC_NO_IOPOWER_0_DVI_SHIFT)
+#define APBDEV_PMC_NO_IOPOWER_0_DVI_RANGE                       4:4
+#define APBDEV_PMC_NO_IOPOWER_0_DVI_WOFFSET                     0x0
+#define APBDEV_PMC_NO_IOPOWER_0_DVI_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_DVI_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_NO_IOPOWER_0_DVI_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_DVI_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_DVI_DISABLE                     _MK_ENUM_CONST(0)
+#define APBDEV_PMC_NO_IOPOWER_0_DVI_ENABLE                      _MK_ENUM_CONST(1)
+
+//rail i2s IOs   
+#define APBDEV_PMC_NO_IOPOWER_0_I2S_SHIFT                       _MK_SHIFT_CONST(5)
+#define APBDEV_PMC_NO_IOPOWER_0_I2S_FIELD                       (_MK_MASK_CONST(0x1) << APBDEV_PMC_NO_IOPOWER_0_I2S_SHIFT)
+#define APBDEV_PMC_NO_IOPOWER_0_I2S_RANGE                       5:5
+#define APBDEV_PMC_NO_IOPOWER_0_I2S_WOFFSET                     0x0
+#define APBDEV_PMC_NO_IOPOWER_0_I2S_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_I2S_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_NO_IOPOWER_0_I2S_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_I2S_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_I2S_DISABLE                     _MK_ENUM_CONST(0)
+#define APBDEV_PMC_NO_IOPOWER_0_I2S_ENABLE                      _MK_ENUM_CONST(1)
+
+//rail lcd IOs   
+#define APBDEV_PMC_NO_IOPOWER_0_LCD_SHIFT                       _MK_SHIFT_CONST(6)
+#define APBDEV_PMC_NO_IOPOWER_0_LCD_FIELD                       (_MK_MASK_CONST(0x1) << APBDEV_PMC_NO_IOPOWER_0_LCD_SHIFT)
+#define APBDEV_PMC_NO_IOPOWER_0_LCD_RANGE                       6:6
+#define APBDEV_PMC_NO_IOPOWER_0_LCD_WOFFSET                     0x0
+#define APBDEV_PMC_NO_IOPOWER_0_LCD_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_LCD_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_NO_IOPOWER_0_LCD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_LCD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_LCD_DISABLE                     _MK_ENUM_CONST(0)
+#define APBDEV_PMC_NO_IOPOWER_0_LCD_ENABLE                      _MK_ENUM_CONST(1)
+
+//rail mem IOs   
+#define APBDEV_PMC_NO_IOPOWER_0_MEM_SHIFT                       _MK_SHIFT_CONST(7)
+#define APBDEV_PMC_NO_IOPOWER_0_MEM_FIELD                       (_MK_MASK_CONST(0x1) << APBDEV_PMC_NO_IOPOWER_0_MEM_SHIFT)
+#define APBDEV_PMC_NO_IOPOWER_0_MEM_RANGE                       7:7
+#define APBDEV_PMC_NO_IOPOWER_0_MEM_WOFFSET                     0x0
+#define APBDEV_PMC_NO_IOPOWER_0_MEM_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_MEM_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_NO_IOPOWER_0_MEM_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_MEM_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_MEM_DISABLE                     _MK_ENUM_CONST(0)
+#define APBDEV_PMC_NO_IOPOWER_0_MEM_ENABLE                      _MK_ENUM_CONST(1)
+
+//rail sd IOs   
+#define APBDEV_PMC_NO_IOPOWER_0_SD_SHIFT                        _MK_SHIFT_CONST(8)
+#define APBDEV_PMC_NO_IOPOWER_0_SD_FIELD                        (_MK_MASK_CONST(0x1) << APBDEV_PMC_NO_IOPOWER_0_SD_SHIFT)
+#define APBDEV_PMC_NO_IOPOWER_0_SD_RANGE                        8:8
+#define APBDEV_PMC_NO_IOPOWER_0_SD_WOFFSET                      0x0
+#define APBDEV_PMC_NO_IOPOWER_0_SD_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_SD_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_NO_IOPOWER_0_SD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_SD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_SD_DISABLE                      _MK_ENUM_CONST(0)
+#define APBDEV_PMC_NO_IOPOWER_0_SD_ENABLE                       _MK_ENUM_CONST(1)
+
+//rail mipi IOs   
+#define APBDEV_PMC_NO_IOPOWER_0_MIPI_SHIFT                      _MK_SHIFT_CONST(9)
+#define APBDEV_PMC_NO_IOPOWER_0_MIPI_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_PMC_NO_IOPOWER_0_MIPI_SHIFT)
+#define APBDEV_PMC_NO_IOPOWER_0_MIPI_RANGE                      9:9
+#define APBDEV_PMC_NO_IOPOWER_0_MIPI_WOFFSET                    0x0
+#define APBDEV_PMC_NO_IOPOWER_0_MIPI_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_MIPI_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_NO_IOPOWER_0_MIPI_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_MIPI_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_MIPI_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_NO_IOPOWER_0_MIPI_ENABLE                     _MK_ENUM_CONST(1)
+
+
+// Register APBDEV_PMC_PWR_DET_0  
+#define APBDEV_PMC_PWR_DET_0                    _MK_ADDR_CONST(0x48)
+#define APBDEV_PMC_PWR_DET_0_WORD_COUNT                         0x1
+#define APBDEV_PMC_PWR_DET_0_RESET_VAL                  _MK_MASK_CONST(0x1ff)
+#define APBDEV_PMC_PWR_DET_0_RESET_MASK                         _MK_MASK_CONST(0x1ff)
+#define APBDEV_PMC_PWR_DET_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_0_READ_MASK                  _MK_MASK_CONST(0x1ff)
+#define APBDEV_PMC_PWR_DET_0_WRITE_MASK                         _MK_MASK_CONST(0x1ff)
+//rail ao IOs   
+#define APBDEV_PMC_PWR_DET_0_AO_SHIFT                   _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_PWR_DET_0_AO_FIELD                   (_MK_MASK_CONST(0x1) << APBDEV_PMC_PWR_DET_0_AO_SHIFT)
+#define APBDEV_PMC_PWR_DET_0_AO_RANGE                   0:0
+#define APBDEV_PMC_PWR_DET_0_AO_WOFFSET                 0x0
+#define APBDEV_PMC_PWR_DET_0_AO_DEFAULT                 _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_0_AO_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_0_AO_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_0_AO_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_0_AO_ENABLE                  _MK_ENUM_CONST(0)
+#define APBDEV_PMC_PWR_DET_0_AO_DISABLE                 _MK_ENUM_CONST(1)
+
+//rail at3 IOs 
+#define APBDEV_PMC_PWR_DET_0_AT3_SHIFT                  _MK_SHIFT_CONST(1)
+#define APBDEV_PMC_PWR_DET_0_AT3_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_PMC_PWR_DET_0_AT3_SHIFT)
+#define APBDEV_PMC_PWR_DET_0_AT3_RANGE                  1:1
+#define APBDEV_PMC_PWR_DET_0_AT3_WOFFSET                        0x0
+#define APBDEV_PMC_PWR_DET_0_AT3_DEFAULT                        _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_0_AT3_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_0_AT3_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_0_AT3_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_0_AT3_ENABLE                 _MK_ENUM_CONST(0)
+#define APBDEV_PMC_PWR_DET_0_AT3_DISABLE                        _MK_ENUM_CONST(1)
+
+//rail dbg IOs   
+#define APBDEV_PMC_PWR_DET_0_DBG_SHIFT                  _MK_SHIFT_CONST(2)
+#define APBDEV_PMC_PWR_DET_0_DBG_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_PMC_PWR_DET_0_DBG_SHIFT)
+#define APBDEV_PMC_PWR_DET_0_DBG_RANGE                  2:2
+#define APBDEV_PMC_PWR_DET_0_DBG_WOFFSET                        0x0
+#define APBDEV_PMC_PWR_DET_0_DBG_DEFAULT                        _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_0_DBG_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_0_DBG_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_0_DBG_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_0_DBG_ENABLE                 _MK_ENUM_CONST(0)
+#define APBDEV_PMC_PWR_DET_0_DBG_DISABLE                        _MK_ENUM_CONST(1)
+
+//rail dlcd IOs   
+#define APBDEV_PMC_PWR_DET_0_DLCD_SHIFT                 _MK_SHIFT_CONST(3)
+#define APBDEV_PMC_PWR_DET_0_DLCD_FIELD                 (_MK_MASK_CONST(0x1) << APBDEV_PMC_PWR_DET_0_DLCD_SHIFT)
+#define APBDEV_PMC_PWR_DET_0_DLCD_RANGE                 3:3
+#define APBDEV_PMC_PWR_DET_0_DLCD_WOFFSET                       0x0
+#define APBDEV_PMC_PWR_DET_0_DLCD_DEFAULT                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_0_DLCD_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_0_DLCD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_0_DLCD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_0_DLCD_ENABLE                        _MK_ENUM_CONST(0)
+#define APBDEV_PMC_PWR_DET_0_DLCD_DISABLE                       _MK_ENUM_CONST(1)
+
+//rail dvi IOs   
+#define APBDEV_PMC_PWR_DET_0_DVI_SHIFT                  _MK_SHIFT_CONST(4)
+#define APBDEV_PMC_PWR_DET_0_DVI_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_PMC_PWR_DET_0_DVI_SHIFT)
+#define APBDEV_PMC_PWR_DET_0_DVI_RANGE                  4:4
+#define APBDEV_PMC_PWR_DET_0_DVI_WOFFSET                        0x0
+#define APBDEV_PMC_PWR_DET_0_DVI_DEFAULT                        _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_0_DVI_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_0_DVI_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_0_DVI_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_0_DVI_ENABLE                 _MK_ENUM_CONST(0)
+#define APBDEV_PMC_PWR_DET_0_DVI_DISABLE                        _MK_ENUM_CONST(1)
+
+//rail i2s IOs   
+#define APBDEV_PMC_PWR_DET_0_I2S_SHIFT                  _MK_SHIFT_CONST(5)
+#define APBDEV_PMC_PWR_DET_0_I2S_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_PMC_PWR_DET_0_I2S_SHIFT)
+#define APBDEV_PMC_PWR_DET_0_I2S_RANGE                  5:5
+#define APBDEV_PMC_PWR_DET_0_I2S_WOFFSET                        0x0
+#define APBDEV_PMC_PWR_DET_0_I2S_DEFAULT                        _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_0_I2S_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_0_I2S_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_0_I2S_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_0_I2S_ENABLE                 _MK_ENUM_CONST(0)
+#define APBDEV_PMC_PWR_DET_0_I2S_DISABLE                        _MK_ENUM_CONST(1)
+
+//rail lcd IOs   
+#define APBDEV_PMC_PWR_DET_0_LCD_SHIFT                  _MK_SHIFT_CONST(6)
+#define APBDEV_PMC_PWR_DET_0_LCD_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_PMC_PWR_DET_0_LCD_SHIFT)
+#define APBDEV_PMC_PWR_DET_0_LCD_RANGE                  6:6
+#define APBDEV_PMC_PWR_DET_0_LCD_WOFFSET                        0x0
+#define APBDEV_PMC_PWR_DET_0_LCD_DEFAULT                        _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_0_LCD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_0_LCD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_0_LCD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_0_LCD_ENABLE                 _MK_ENUM_CONST(0)
+#define APBDEV_PMC_PWR_DET_0_LCD_DISABLE                        _MK_ENUM_CONST(1)
+
+//rail mem IOs   
+#define APBDEV_PMC_PWR_DET_0_MEM_SHIFT                  _MK_SHIFT_CONST(7)
+#define APBDEV_PMC_PWR_DET_0_MEM_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_PMC_PWR_DET_0_MEM_SHIFT)
+#define APBDEV_PMC_PWR_DET_0_MEM_RANGE                  7:7
+#define APBDEV_PMC_PWR_DET_0_MEM_WOFFSET                        0x0
+#define APBDEV_PMC_PWR_DET_0_MEM_DEFAULT                        _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_0_MEM_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_0_MEM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_0_MEM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_0_MEM_ENABLE                 _MK_ENUM_CONST(0)
+#define APBDEV_PMC_PWR_DET_0_MEM_DISABLE                        _MK_ENUM_CONST(1)
+
+//rail sd IOs   
+#define APBDEV_PMC_PWR_DET_0_SD_SHIFT                   _MK_SHIFT_CONST(8)
+#define APBDEV_PMC_PWR_DET_0_SD_FIELD                   (_MK_MASK_CONST(0x1) << APBDEV_PMC_PWR_DET_0_SD_SHIFT)
+#define APBDEV_PMC_PWR_DET_0_SD_RANGE                   8:8
+#define APBDEV_PMC_PWR_DET_0_SD_WOFFSET                 0x0
+#define APBDEV_PMC_PWR_DET_0_SD_DEFAULT                 _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_0_SD_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_0_SD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_0_SD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_0_SD_ENABLE                  _MK_ENUM_CONST(0)
+#define APBDEV_PMC_PWR_DET_0_SD_DISABLE                 _MK_ENUM_CONST(1)
+
+
+// Register APBDEV_PMC_PWR_DET_LATCH_0  
+#define APBDEV_PMC_PWR_DET_LATCH_0                      _MK_ADDR_CONST(0x4c)
+#define APBDEV_PMC_PWR_DET_LATCH_0_WORD_COUNT                   0x1
+#define APBDEV_PMC_PWR_DET_LATCH_0_RESET_VAL                    _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_LATCH_0_RESET_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_LATCH_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_LATCH_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_LATCH_0_READ_MASK                    _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_LATCH_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
+//power detect latch, latches value as long set to 1  
+#define APBDEV_PMC_PWR_DET_LATCH_0_LATCH_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_PWR_DET_LATCH_0_LATCH_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_PMC_PWR_DET_LATCH_0_LATCH_SHIFT)
+#define APBDEV_PMC_PWR_DET_LATCH_0_LATCH_RANGE                  0:0
+#define APBDEV_PMC_PWR_DET_LATCH_0_LATCH_WOFFSET                        0x0
+#define APBDEV_PMC_PWR_DET_LATCH_0_LATCH_DEFAULT                        _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_LATCH_0_LATCH_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_LATCH_0_LATCH_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_LATCH_0_LATCH_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_LATCH_0_LATCH_ENABLE                 _MK_ENUM_CONST(0)
+#define APBDEV_PMC_PWR_DET_LATCH_0_LATCH_DISABLE                        _MK_ENUM_CONST(1)
+
+
+// Register APBDEV_PMC_SCRATCH0_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH0_0                   _MK_ADDR_CONST(0x50)
+#define APBDEV_PMC_SCRATCH0_0_WORD_COUNT                        0x1
+#define APBDEV_PMC_SCRATCH0_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH0_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH0_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH0_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH0_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH0_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
+// General purpose register storage 
+#define APBDEV_PMC_SCRATCH0_0_SCRATCH0_SHIFT                    _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH0_0_SCRATCH0_FIELD                    (_MK_MASK_CONST(0x7fffffff) << APBDEV_PMC_SCRATCH0_0_SCRATCH0_SHIFT)
+#define APBDEV_PMC_SCRATCH0_0_SCRATCH0_RANGE                    30:0
+#define APBDEV_PMC_SCRATCH0_0_SCRATCH0_WOFFSET                  0x0
+#define APBDEV_PMC_SCRATCH0_0_SCRATCH0_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH0_0_SCRATCH0_DEFAULT_MASK                     _MK_MASK_CONST(0x7fffffff)
+#define APBDEV_PMC_SCRATCH0_0_SCRATCH0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH0_0_SCRATCH0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// reset power detect latch to 3.3V
+#define APBDEV_PMC_SCRATCH0_0_RST_PWR_DET_SHIFT                 _MK_SHIFT_CONST(31)
+#define APBDEV_PMC_SCRATCH0_0_RST_PWR_DET_FIELD                 (_MK_MASK_CONST(0x1) << APBDEV_PMC_SCRATCH0_0_RST_PWR_DET_SHIFT)
+#define APBDEV_PMC_SCRATCH0_0_RST_PWR_DET_RANGE                 31:31
+#define APBDEV_PMC_SCRATCH0_0_RST_PWR_DET_WOFFSET                       0x0
+#define APBDEV_PMC_SCRATCH0_0_RST_PWR_DET_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH0_0_RST_PWR_DET_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_SCRATCH0_0_RST_PWR_DET_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH0_0_RST_PWR_DET_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH1_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH1_0                   _MK_ADDR_CONST(0x54)
+#define APBDEV_PMC_SCRATCH1_0_WORD_COUNT                        0x1
+#define APBDEV_PMC_SCRATCH1_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH1_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH1_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH1_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH1_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH1_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH1_0_SCRATCH1_SHIFT                    _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH1_0_SCRATCH1_FIELD                    (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH1_0_SCRATCH1_SHIFT)
+#define APBDEV_PMC_SCRATCH1_0_SCRATCH1_RANGE                    31:0
+#define APBDEV_PMC_SCRATCH1_0_SCRATCH1_WOFFSET                  0x0
+#define APBDEV_PMC_SCRATCH1_0_SCRATCH1_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH1_0_SCRATCH1_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH1_0_SCRATCH1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH1_0_SCRATCH1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH2_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH2_0                   _MK_ADDR_CONST(0x58)
+#define APBDEV_PMC_SCRATCH2_0_WORD_COUNT                        0x1
+#define APBDEV_PMC_SCRATCH2_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH2_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH2_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH2_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH2_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH2_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH2_0_SCRATCH2_SHIFT                    _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH2_0_SCRATCH2_FIELD                    (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH2_0_SCRATCH2_SHIFT)
+#define APBDEV_PMC_SCRATCH2_0_SCRATCH2_RANGE                    31:0
+#define APBDEV_PMC_SCRATCH2_0_SCRATCH2_WOFFSET                  0x0
+#define APBDEV_PMC_SCRATCH2_0_SCRATCH2_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH2_0_SCRATCH2_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH2_0_SCRATCH2_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH2_0_SCRATCH2_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH3_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH3_0                   _MK_ADDR_CONST(0x5c)
+#define APBDEV_PMC_SCRATCH3_0_WORD_COUNT                        0x1
+#define APBDEV_PMC_SCRATCH3_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH3_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH3_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH3_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH3_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH3_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH3_0_SCRATCH3_SHIFT                    _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH3_0_SCRATCH3_FIELD                    (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH3_0_SCRATCH3_SHIFT)
+#define APBDEV_PMC_SCRATCH3_0_SCRATCH3_RANGE                    31:0
+#define APBDEV_PMC_SCRATCH3_0_SCRATCH3_WOFFSET                  0x0
+#define APBDEV_PMC_SCRATCH3_0_SCRATCH3_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH3_0_SCRATCH3_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH3_0_SCRATCH3_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH3_0_SCRATCH3_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH4_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH4_0                   _MK_ADDR_CONST(0x60)
+#define APBDEV_PMC_SCRATCH4_0_WORD_COUNT                        0x1
+#define APBDEV_PMC_SCRATCH4_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH4_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH4_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH4_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH4_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH4_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH4_0_SCRATCH4_SHIFT                    _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH4_0_SCRATCH4_FIELD                    (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH4_0_SCRATCH4_SHIFT)
+#define APBDEV_PMC_SCRATCH4_0_SCRATCH4_RANGE                    31:0
+#define APBDEV_PMC_SCRATCH4_0_SCRATCH4_WOFFSET                  0x0
+#define APBDEV_PMC_SCRATCH4_0_SCRATCH4_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH4_0_SCRATCH4_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH4_0_SCRATCH4_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH4_0_SCRATCH4_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH5_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH5_0                   _MK_ADDR_CONST(0x64)
+#define APBDEV_PMC_SCRATCH5_0_WORD_COUNT                        0x1
+#define APBDEV_PMC_SCRATCH5_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH5_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH5_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH5_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH5_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH5_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH5_0_SCRATCH5_SHIFT                    _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH5_0_SCRATCH5_FIELD                    (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH5_0_SCRATCH5_SHIFT)
+#define APBDEV_PMC_SCRATCH5_0_SCRATCH5_RANGE                    31:0
+#define APBDEV_PMC_SCRATCH5_0_SCRATCH5_WOFFSET                  0x0
+#define APBDEV_PMC_SCRATCH5_0_SCRATCH5_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH5_0_SCRATCH5_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH5_0_SCRATCH5_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH5_0_SCRATCH5_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH6_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH6_0                   _MK_ADDR_CONST(0x68)
+#define APBDEV_PMC_SCRATCH6_0_WORD_COUNT                        0x1
+#define APBDEV_PMC_SCRATCH6_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH6_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH6_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH6_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH6_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH6_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH6_0_SCRATCH6_SHIFT                    _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH6_0_SCRATCH6_FIELD                    (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH6_0_SCRATCH6_SHIFT)
+#define APBDEV_PMC_SCRATCH6_0_SCRATCH6_RANGE                    31:0
+#define APBDEV_PMC_SCRATCH6_0_SCRATCH6_WOFFSET                  0x0
+#define APBDEV_PMC_SCRATCH6_0_SCRATCH6_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH6_0_SCRATCH6_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH6_0_SCRATCH6_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH6_0_SCRATCH6_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH7_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH7_0                   _MK_ADDR_CONST(0x6c)
+#define APBDEV_PMC_SCRATCH7_0_WORD_COUNT                        0x1
+#define APBDEV_PMC_SCRATCH7_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH7_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH7_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH7_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH7_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH7_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH7_0_SCRATCH7_SHIFT                    _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH7_0_SCRATCH7_FIELD                    (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH7_0_SCRATCH7_SHIFT)
+#define APBDEV_PMC_SCRATCH7_0_SCRATCH7_RANGE                    31:0
+#define APBDEV_PMC_SCRATCH7_0_SCRATCH7_WOFFSET                  0x0
+#define APBDEV_PMC_SCRATCH7_0_SCRATCH7_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH7_0_SCRATCH7_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH7_0_SCRATCH7_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH7_0_SCRATCH7_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH8_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH8_0                   _MK_ADDR_CONST(0x70)
+#define APBDEV_PMC_SCRATCH8_0_WORD_COUNT                        0x1
+#define APBDEV_PMC_SCRATCH8_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH8_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH8_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH8_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH8_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH8_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH8_0_SCRATCH8_SHIFT                    _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH8_0_SCRATCH8_FIELD                    (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH8_0_SCRATCH8_SHIFT)
+#define APBDEV_PMC_SCRATCH8_0_SCRATCH8_RANGE                    31:0
+#define APBDEV_PMC_SCRATCH8_0_SCRATCH8_WOFFSET                  0x0
+#define APBDEV_PMC_SCRATCH8_0_SCRATCH8_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH8_0_SCRATCH8_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH8_0_SCRATCH8_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH8_0_SCRATCH8_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH9_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH9_0                   _MK_ADDR_CONST(0x74)
+#define APBDEV_PMC_SCRATCH9_0_WORD_COUNT                        0x1
+#define APBDEV_PMC_SCRATCH9_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH9_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH9_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH9_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH9_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH9_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH9_0_SCRATCH9_SHIFT                    _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH9_0_SCRATCH9_FIELD                    (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH9_0_SCRATCH9_SHIFT)
+#define APBDEV_PMC_SCRATCH9_0_SCRATCH9_RANGE                    31:0
+#define APBDEV_PMC_SCRATCH9_0_SCRATCH9_WOFFSET                  0x0
+#define APBDEV_PMC_SCRATCH9_0_SCRATCH9_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH9_0_SCRATCH9_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH9_0_SCRATCH9_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH9_0_SCRATCH9_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH10_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH10_0                  _MK_ADDR_CONST(0x78)
+#define APBDEV_PMC_SCRATCH10_0_WORD_COUNT                       0x1
+#define APBDEV_PMC_SCRATCH10_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH10_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH10_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH10_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH10_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH10_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH10_0_SCRATCH10_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH10_0_SCRATCH10_FIELD                  (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH10_0_SCRATCH10_SHIFT)
+#define APBDEV_PMC_SCRATCH10_0_SCRATCH10_RANGE                  31:0
+#define APBDEV_PMC_SCRATCH10_0_SCRATCH10_WOFFSET                        0x0
+#define APBDEV_PMC_SCRATCH10_0_SCRATCH10_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH10_0_SCRATCH10_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH10_0_SCRATCH10_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH10_0_SCRATCH10_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH11_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH11_0                  _MK_ADDR_CONST(0x7c)
+#define APBDEV_PMC_SCRATCH11_0_WORD_COUNT                       0x1
+#define APBDEV_PMC_SCRATCH11_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH11_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH11_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH11_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH11_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH11_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH11_0_SCRATCH11_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH11_0_SCRATCH11_FIELD                  (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH11_0_SCRATCH11_SHIFT)
+#define APBDEV_PMC_SCRATCH11_0_SCRATCH11_RANGE                  31:0
+#define APBDEV_PMC_SCRATCH11_0_SCRATCH11_WOFFSET                        0x0
+#define APBDEV_PMC_SCRATCH11_0_SCRATCH11_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH11_0_SCRATCH11_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH11_0_SCRATCH11_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH11_0_SCRATCH11_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH12_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH12_0                  _MK_ADDR_CONST(0x80)
+#define APBDEV_PMC_SCRATCH12_0_WORD_COUNT                       0x1
+#define APBDEV_PMC_SCRATCH12_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH12_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH12_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH12_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH12_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH12_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH12_0_SCRATCH12_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH12_0_SCRATCH12_FIELD                  (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH12_0_SCRATCH12_SHIFT)
+#define APBDEV_PMC_SCRATCH12_0_SCRATCH12_RANGE                  31:0
+#define APBDEV_PMC_SCRATCH12_0_SCRATCH12_WOFFSET                        0x0
+#define APBDEV_PMC_SCRATCH12_0_SCRATCH12_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH12_0_SCRATCH12_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH12_0_SCRATCH12_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH12_0_SCRATCH12_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH13_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH13_0                  _MK_ADDR_CONST(0x84)
+#define APBDEV_PMC_SCRATCH13_0_WORD_COUNT                       0x1
+#define APBDEV_PMC_SCRATCH13_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH13_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH13_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH13_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH13_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH13_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH13_0_SCRATCH13_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH13_0_SCRATCH13_FIELD                  (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH13_0_SCRATCH13_SHIFT)
+#define APBDEV_PMC_SCRATCH13_0_SCRATCH13_RANGE                  31:0
+#define APBDEV_PMC_SCRATCH13_0_SCRATCH13_WOFFSET                        0x0
+#define APBDEV_PMC_SCRATCH13_0_SCRATCH13_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH13_0_SCRATCH13_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH13_0_SCRATCH13_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH13_0_SCRATCH13_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH14_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH14_0                  _MK_ADDR_CONST(0x88)
+#define APBDEV_PMC_SCRATCH14_0_WORD_COUNT                       0x1
+#define APBDEV_PMC_SCRATCH14_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH14_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH14_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH14_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH14_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH14_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH14_0_SCRATCH14_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH14_0_SCRATCH14_FIELD                  (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH14_0_SCRATCH14_SHIFT)
+#define APBDEV_PMC_SCRATCH14_0_SCRATCH14_RANGE                  31:0
+#define APBDEV_PMC_SCRATCH14_0_SCRATCH14_WOFFSET                        0x0
+#define APBDEV_PMC_SCRATCH14_0_SCRATCH14_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH14_0_SCRATCH14_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH14_0_SCRATCH14_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH14_0_SCRATCH14_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH15_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH15_0                  _MK_ADDR_CONST(0x8c)
+#define APBDEV_PMC_SCRATCH15_0_WORD_COUNT                       0x1
+#define APBDEV_PMC_SCRATCH15_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH15_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH15_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH15_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH15_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH15_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH15_0_SCRATCH15_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH15_0_SCRATCH15_FIELD                  (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH15_0_SCRATCH15_SHIFT)
+#define APBDEV_PMC_SCRATCH15_0_SCRATCH15_RANGE                  31:0
+#define APBDEV_PMC_SCRATCH15_0_SCRATCH15_WOFFSET                        0x0
+#define APBDEV_PMC_SCRATCH15_0_SCRATCH15_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH15_0_SCRATCH15_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH15_0_SCRATCH15_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH15_0_SCRATCH15_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH16_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH16_0                  _MK_ADDR_CONST(0x90)
+#define APBDEV_PMC_SCRATCH16_0_WORD_COUNT                       0x1
+#define APBDEV_PMC_SCRATCH16_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH16_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH16_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH16_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH16_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH16_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH16_0_SCRATCH16_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH16_0_SCRATCH16_FIELD                  (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH16_0_SCRATCH16_SHIFT)
+#define APBDEV_PMC_SCRATCH16_0_SCRATCH16_RANGE                  31:0
+#define APBDEV_PMC_SCRATCH16_0_SCRATCH16_WOFFSET                        0x0
+#define APBDEV_PMC_SCRATCH16_0_SCRATCH16_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH16_0_SCRATCH16_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH16_0_SCRATCH16_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH16_0_SCRATCH16_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH17_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH17_0                  _MK_ADDR_CONST(0x94)
+#define APBDEV_PMC_SCRATCH17_0_WORD_COUNT                       0x1
+#define APBDEV_PMC_SCRATCH17_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH17_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH17_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH17_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH17_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH17_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH17_0_SCRATCH17_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH17_0_SCRATCH17_FIELD                  (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH17_0_SCRATCH17_SHIFT)
+#define APBDEV_PMC_SCRATCH17_0_SCRATCH17_RANGE                  31:0
+#define APBDEV_PMC_SCRATCH17_0_SCRATCH17_WOFFSET                        0x0
+#define APBDEV_PMC_SCRATCH17_0_SCRATCH17_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH17_0_SCRATCH17_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH17_0_SCRATCH17_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH17_0_SCRATCH17_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH18_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH18_0                  _MK_ADDR_CONST(0x98)
+#define APBDEV_PMC_SCRATCH18_0_WORD_COUNT                       0x1
+#define APBDEV_PMC_SCRATCH18_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH18_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH18_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH18_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH18_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH18_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH18_0_SCRATCH18_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH18_0_SCRATCH18_FIELD                  (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH18_0_SCRATCH18_SHIFT)
+#define APBDEV_PMC_SCRATCH18_0_SCRATCH18_RANGE                  31:0
+#define APBDEV_PMC_SCRATCH18_0_SCRATCH18_WOFFSET                        0x0
+#define APBDEV_PMC_SCRATCH18_0_SCRATCH18_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH18_0_SCRATCH18_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH18_0_SCRATCH18_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH18_0_SCRATCH18_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH19_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH19_0                  _MK_ADDR_CONST(0x9c)
+#define APBDEV_PMC_SCRATCH19_0_WORD_COUNT                       0x1
+#define APBDEV_PMC_SCRATCH19_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH19_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH19_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH19_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH19_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH19_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH19_0_SCRATCH19_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH19_0_SCRATCH19_FIELD                  (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH19_0_SCRATCH19_SHIFT)
+#define APBDEV_PMC_SCRATCH19_0_SCRATCH19_RANGE                  31:0
+#define APBDEV_PMC_SCRATCH19_0_SCRATCH19_WOFFSET                        0x0
+#define APBDEV_PMC_SCRATCH19_0_SCRATCH19_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH19_0_SCRATCH19_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH19_0_SCRATCH19_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH19_0_SCRATCH19_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH20_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH20_0                  _MK_ADDR_CONST(0xa0)
+#define APBDEV_PMC_SCRATCH20_0_WORD_COUNT                       0x1
+#define APBDEV_PMC_SCRATCH20_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH20_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH20_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH20_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH20_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH20_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH20_0_SCRATCH20_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH20_0_SCRATCH20_FIELD                  (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH20_0_SCRATCH20_SHIFT)
+#define APBDEV_PMC_SCRATCH20_0_SCRATCH20_RANGE                  31:0
+#define APBDEV_PMC_SCRATCH20_0_SCRATCH20_WOFFSET                        0x0
+#define APBDEV_PMC_SCRATCH20_0_SCRATCH20_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH20_0_SCRATCH20_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH20_0_SCRATCH20_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH20_0_SCRATCH20_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH21_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH21_0                  _MK_ADDR_CONST(0xa4)
+#define APBDEV_PMC_SCRATCH21_0_WORD_COUNT                       0x1
+#define APBDEV_PMC_SCRATCH21_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH21_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH21_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH21_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH21_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH21_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH21_0_SCRATCH21_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH21_0_SCRATCH21_FIELD                  (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH21_0_SCRATCH21_SHIFT)
+#define APBDEV_PMC_SCRATCH21_0_SCRATCH21_RANGE                  31:0
+#define APBDEV_PMC_SCRATCH21_0_SCRATCH21_WOFFSET                        0x0
+#define APBDEV_PMC_SCRATCH21_0_SCRATCH21_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH21_0_SCRATCH21_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH21_0_SCRATCH21_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH21_0_SCRATCH21_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH22_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH22_0                  _MK_ADDR_CONST(0xa8)
+#define APBDEV_PMC_SCRATCH22_0_WORD_COUNT                       0x1
+#define APBDEV_PMC_SCRATCH22_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH22_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH22_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH22_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH22_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH22_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH22_0_SCRATCH22_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH22_0_SCRATCH22_FIELD                  (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH22_0_SCRATCH22_SHIFT)
+#define APBDEV_PMC_SCRATCH22_0_SCRATCH22_RANGE                  31:0
+#define APBDEV_PMC_SCRATCH22_0_SCRATCH22_WOFFSET                        0x0
+#define APBDEV_PMC_SCRATCH22_0_SCRATCH22_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH22_0_SCRATCH22_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH22_0_SCRATCH22_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH22_0_SCRATCH22_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH23_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH23_0                  _MK_ADDR_CONST(0xac)
+#define APBDEV_PMC_SCRATCH23_0_WORD_COUNT                       0x1
+#define APBDEV_PMC_SCRATCH23_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH23_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH23_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH23_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH23_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH23_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH23_0_SCRATCH23_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH23_0_SCRATCH23_FIELD                  (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH23_0_SCRATCH23_SHIFT)
+#define APBDEV_PMC_SCRATCH23_0_SCRATCH23_RANGE                  31:0
+#define APBDEV_PMC_SCRATCH23_0_SCRATCH23_WOFFSET                        0x0
+#define APBDEV_PMC_SCRATCH23_0_SCRATCH23_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH23_0_SCRATCH23_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH23_0_SCRATCH23_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH23_0_SCRATCH23_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SECURE_SCRATCH0_0  // Secure scratch register
+#define APBDEV_PMC_SECURE_SCRATCH0_0                    _MK_ADDR_CONST(0xb0)
+#define APBDEV_PMC_SECURE_SCRATCH0_0_WORD_COUNT                         0x1
+#define APBDEV_PMC_SECURE_SCRATCH0_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH0_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH0_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH0_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH0_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SECURE_SCRATCH0_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SECURE_SCRATCH0_0_SECURE_SCRATCH0_SHIFT                      _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SECURE_SCRATCH0_0_SECURE_SCRATCH0_FIELD                      (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SECURE_SCRATCH0_0_SECURE_SCRATCH0_SHIFT)
+#define APBDEV_PMC_SECURE_SCRATCH0_0_SECURE_SCRATCH0_RANGE                      31:0
+#define APBDEV_PMC_SECURE_SCRATCH0_0_SECURE_SCRATCH0_WOFFSET                    0x0
+#define APBDEV_PMC_SECURE_SCRATCH0_0_SECURE_SCRATCH0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH0_0_SECURE_SCRATCH0_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH0_0_SECURE_SCRATCH0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH0_0_SECURE_SCRATCH0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SECURE_SCRATCH1_0  // Secure scratch register
+#define APBDEV_PMC_SECURE_SCRATCH1_0                    _MK_ADDR_CONST(0xb4)
+#define APBDEV_PMC_SECURE_SCRATCH1_0_WORD_COUNT                         0x1
+#define APBDEV_PMC_SECURE_SCRATCH1_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH1_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH1_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SECURE_SCRATCH1_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SECURE_SCRATCH1_0_SECURE_SCRATCH1_SHIFT                      _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SECURE_SCRATCH1_0_SECURE_SCRATCH1_FIELD                      (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SECURE_SCRATCH1_0_SECURE_SCRATCH1_SHIFT)
+#define APBDEV_PMC_SECURE_SCRATCH1_0_SECURE_SCRATCH1_RANGE                      31:0
+#define APBDEV_PMC_SECURE_SCRATCH1_0_SECURE_SCRATCH1_WOFFSET                    0x0
+#define APBDEV_PMC_SECURE_SCRATCH1_0_SECURE_SCRATCH1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH1_0_SECURE_SCRATCH1_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH1_0_SECURE_SCRATCH1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH1_0_SECURE_SCRATCH1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SECURE_SCRATCH2_0  // Secure scratch register
+#define APBDEV_PMC_SECURE_SCRATCH2_0                    _MK_ADDR_CONST(0xb8)
+#define APBDEV_PMC_SECURE_SCRATCH2_0_WORD_COUNT                         0x1
+#define APBDEV_PMC_SECURE_SCRATCH2_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH2_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH2_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH2_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH2_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SECURE_SCRATCH2_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SECURE_SCRATCH2_0_SECURE_SCRATCH2_SHIFT                      _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SECURE_SCRATCH2_0_SECURE_SCRATCH2_FIELD                      (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SECURE_SCRATCH2_0_SECURE_SCRATCH2_SHIFT)
+#define APBDEV_PMC_SECURE_SCRATCH2_0_SECURE_SCRATCH2_RANGE                      31:0
+#define APBDEV_PMC_SECURE_SCRATCH2_0_SECURE_SCRATCH2_WOFFSET                    0x0
+#define APBDEV_PMC_SECURE_SCRATCH2_0_SECURE_SCRATCH2_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH2_0_SECURE_SCRATCH2_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH2_0_SECURE_SCRATCH2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH2_0_SECURE_SCRATCH2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SECURE_SCRATCH3_0  // Secure scratch register
+#define APBDEV_PMC_SECURE_SCRATCH3_0                    _MK_ADDR_CONST(0xbc)
+#define APBDEV_PMC_SECURE_SCRATCH3_0_WORD_COUNT                         0x1
+#define APBDEV_PMC_SECURE_SCRATCH3_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH3_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH3_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH3_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH3_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SECURE_SCRATCH3_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SECURE_SCRATCH3_0_SECURE_SCRATCH3_SHIFT                      _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SECURE_SCRATCH3_0_SECURE_SCRATCH3_FIELD                      (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SECURE_SCRATCH3_0_SECURE_SCRATCH3_SHIFT)
+#define APBDEV_PMC_SECURE_SCRATCH3_0_SECURE_SCRATCH3_RANGE                      31:0
+#define APBDEV_PMC_SECURE_SCRATCH3_0_SECURE_SCRATCH3_WOFFSET                    0x0
+#define APBDEV_PMC_SECURE_SCRATCH3_0_SECURE_SCRATCH3_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH3_0_SECURE_SCRATCH3_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH3_0_SECURE_SCRATCH3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH3_0_SECURE_SCRATCH3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+//
+// REGISTER LIST
+//
+#define LIST_ARAPBPM_REGS(_op_) \
+_op_(APBDEV_PMC_CNTRL_0) \
+_op_(APBDEV_PMC_SEC_DISABLE_0) \
+_op_(APBDEV_PMC_PMC_SWRST_0) \
+_op_(APBDEV_PMC_WAKE_MASK_0) \
+_op_(APBDEV_PMC_WAKE_LVL_0) \
+_op_(APBDEV_PMC_WAKE_STATUS_0) \
+_op_(APBDEV_PMC_SW_WAKE_STATUS_0) \
+_op_(APBDEV_PMC_DPD_PADS_ORIDE_0) \
+_op_(APBDEV_PMC_DPD_SAMPLE_0) \
+_op_(APBDEV_PMC_DPD_ENABLE_0) \
+_op_(APBDEV_PMC_PWRGATE_TIMER_OFF_0) \
+_op_(APBDEV_PMC_PWRGATE_TIMER_ON_0) \
+_op_(APBDEV_PMC_PWRGATE_TOGGLE_0) \
+_op_(APBDEV_PMC_REMOVE_CLAMPING_CMD_0) \
+_op_(APBDEV_PMC_PWRGATE_STATUS_0) \
+_op_(APBDEV_PMC_PWRGOOD_TIMER_0) \
+_op_(APBDEV_PMC_BLINK_TIMER_0) \
+_op_(APBDEV_PMC_NO_IOPOWER_0) \
+_op_(APBDEV_PMC_PWR_DET_0) \
+_op_(APBDEV_PMC_PWR_DET_LATCH_0) \
+_op_(APBDEV_PMC_SCRATCH0_0) \
+_op_(APBDEV_PMC_SCRATCH1_0) \
+_op_(APBDEV_PMC_SCRATCH2_0) \
+_op_(APBDEV_PMC_SCRATCH3_0) \
+_op_(APBDEV_PMC_SCRATCH4_0) \
+_op_(APBDEV_PMC_SCRATCH5_0) \
+_op_(APBDEV_PMC_SCRATCH6_0) \
+_op_(APBDEV_PMC_SCRATCH7_0) \
+_op_(APBDEV_PMC_SCRATCH8_0) \
+_op_(APBDEV_PMC_SCRATCH9_0) \
+_op_(APBDEV_PMC_SCRATCH10_0) \
+_op_(APBDEV_PMC_SCRATCH11_0) \
+_op_(APBDEV_PMC_SCRATCH12_0) \
+_op_(APBDEV_PMC_SCRATCH13_0) \
+_op_(APBDEV_PMC_SCRATCH14_0) \
+_op_(APBDEV_PMC_SCRATCH15_0) \
+_op_(APBDEV_PMC_SCRATCH16_0) \
+_op_(APBDEV_PMC_SCRATCH17_0) \
+_op_(APBDEV_PMC_SCRATCH18_0) \
+_op_(APBDEV_PMC_SCRATCH19_0) \
+_op_(APBDEV_PMC_SCRATCH20_0) \
+_op_(APBDEV_PMC_SCRATCH21_0) \
+_op_(APBDEV_PMC_SCRATCH22_0) \
+_op_(APBDEV_PMC_SCRATCH23_0) \
+_op_(APBDEV_PMC_SECURE_SCRATCH0_0) \
+_op_(APBDEV_PMC_SECURE_SCRATCH1_0) \
+_op_(APBDEV_PMC_SECURE_SCRATCH2_0) \
+_op_(APBDEV_PMC_SECURE_SCRATCH3_0)
+
+
+//
+// ADDRESS SPACES
+//
+
+#define BASE_ADDRESS_APBDEV_PMC 0x00000000
+
+//
+// ARAPBPM REGISTER BANKS
+//
+
+#define APBDEV_PMC0_FIRST_REG 0x0000 // APBDEV_PMC_CNTRL_0
+#define APBDEV_PMC0_LAST_REG 0x00bc // APBDEV_PMC_SECURE_SCRATCH3_0
+
+#ifndef _MK_SHIFT_CONST
+  #define _MK_SHIFT_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_MASK_CONST
+  #define _MK_MASK_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_ENUM_CONST
+  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
+#endif
+#ifndef _MK_ADDR_CONST
+  #define _MK_ADDR_CONST(_constant_) _constant_
+#endif
+
+#endif // ifndef ___ARAPBPM_H_INC_
diff --git a/arch/arm/mach-tegra/include/ap15/ararb_sema.h b/arch/arm/mach-tegra/include/ap15/ararb_sema.h
new file mode 100644
index 000000000000..adc9b4af14b0
--- /dev/null
+++ b/arch/arm/mach-tegra/include/ap15/ararb_sema.h
@@ -0,0 +1,177 @@
+/*
+ * Copyright (c) 2010 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+//
+// DO NOT EDIT - generated by simspec!
+//
+
+#ifndef ___ARARB_SEMA_H_INC_
+#define ___ARARB_SEMA_H_INC_
+// Arbitration semaphores provide a mechanism by which the two processors can arbitrate
+// for the use of various resources. These semaphores provide a hardware locking mechanism,
+// so that when a processor is already using a resource, the second processor is not 
+// granted that resource. There are 32 bits of Arbitration semaphores provided in the system.
+// The hardware does not enforce any resource association to these bits. It is left to the
+// firmware to assign and use these bits.
+// Any processor that needs to access a particular resource will request for the 
+// corresponding bit in the Arbitration semaphores by writing a one to that bit in the 
+// Arbitration Semaphore Request register (SMP_GET register). Firmware will then
+// check the corresponding bit in the Semaphore Granted Status register (SMP_GNT_ST register) 
+// If the requesting processor has been granted the resource, then the status returned will
+// be a one. 
+// Alternately, the processor can configure the interrupt controller to generate an
+// interrupt when the resource becomes available. Refer to the arictlr_arbgnt specfile for details. 
+// When the processor has finished using the resource, it releases the resource by writing a one
+// to the corresponding bit in the Arbitration Semaphore Put Request register 
+// (SMP_PUT register).  Additionally, pending request status is provided through the
+// Arbitration Request Pending Status register (SMP_REQ_ST register).
+// Semaphore Granted Status Register
+
+// Register ARB_SEMA_SMP_GNT_ST_0  
+#define ARB_SEMA_SMP_GNT_ST_0                   _MK_ADDR_CONST(0x0)
+#define ARB_SEMA_SMP_GNT_ST_0_WORD_COUNT                        0x1
+#define ARB_SEMA_SMP_GNT_ST_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define ARB_SEMA_SMP_GNT_ST_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
+#define ARB_SEMA_SMP_GNT_ST_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define ARB_SEMA_SMP_GNT_ST_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define ARB_SEMA_SMP_GNT_ST_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define ARB_SEMA_SMP_GNT_ST_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+// A one in any bit indicates that the processor  reading this register as granted status for that bit. A zero indicates  semaphore not granted.
+#define ARB_SEMA_SMP_GNT_ST_0_ARB_31_ARB_0_SHIFT                        _MK_SHIFT_CONST(0)
+#define ARB_SEMA_SMP_GNT_ST_0_ARB_31_ARB_0_FIELD                        (_MK_MASK_CONST(0xffffffff) << ARB_SEMA_SMP_GNT_ST_0_ARB_31_ARB_0_SHIFT)
+#define ARB_SEMA_SMP_GNT_ST_0_ARB_31_ARB_0_RANGE                        31:0
+#define ARB_SEMA_SMP_GNT_ST_0_ARB_31_ARB_0_WOFFSET                      0x0
+#define ARB_SEMA_SMP_GNT_ST_0_ARB_31_ARB_0_DEFAULT                      _MK_MASK_CONST(0x0)
+#define ARB_SEMA_SMP_GNT_ST_0_ARB_31_ARB_0_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
+#define ARB_SEMA_SMP_GNT_ST_0_ARB_31_ARB_0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define ARB_SEMA_SMP_GNT_ST_0_ARB_31_ARB_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Request Arbitration Semaphore Register
+
+// Register ARB_SEMA_SMP_GET_0  
+#define ARB_SEMA_SMP_GET_0                      _MK_ADDR_CONST(0x4)
+#define ARB_SEMA_SMP_GET_0_WORD_COUNT                   0x1
+#define ARB_SEMA_SMP_GET_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define ARB_SEMA_SMP_GET_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define ARB_SEMA_SMP_GET_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define ARB_SEMA_SMP_GET_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define ARB_SEMA_SMP_GET_0_READ_MASK                    _MK_MASK_CONST(0x0)
+#define ARB_SEMA_SMP_GET_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
+// Writing a one in any bit is a request for that  semaphore bit by the processor performing the register write.
+#define ARB_SEMA_SMP_GET_0_GET_31_GET_0_SHIFT                   _MK_SHIFT_CONST(0)
+#define ARB_SEMA_SMP_GET_0_GET_31_GET_0_FIELD                   (_MK_MASK_CONST(0xffffffff) << ARB_SEMA_SMP_GET_0_GET_31_GET_0_SHIFT)
+#define ARB_SEMA_SMP_GET_0_GET_31_GET_0_RANGE                   31:0
+#define ARB_SEMA_SMP_GET_0_GET_31_GET_0_WOFFSET                 0x0
+#define ARB_SEMA_SMP_GET_0_GET_31_GET_0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define ARB_SEMA_SMP_GET_0_GET_31_GET_0_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
+#define ARB_SEMA_SMP_GET_0_GET_31_GET_0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define ARB_SEMA_SMP_GET_0_GET_31_GET_0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Arbitration Semaphore Put Request Register
+
+// Register ARB_SEMA_SMP_PUT_0  
+#define ARB_SEMA_SMP_PUT_0                      _MK_ADDR_CONST(0x8)
+#define ARB_SEMA_SMP_PUT_0_WORD_COUNT                   0x1
+#define ARB_SEMA_SMP_PUT_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define ARB_SEMA_SMP_PUT_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define ARB_SEMA_SMP_PUT_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define ARB_SEMA_SMP_PUT_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define ARB_SEMA_SMP_PUT_0_READ_MASK                    _MK_MASK_CONST(0x0)
+#define ARB_SEMA_SMP_PUT_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
+// Writing a one in any bit will clear the  corresponding semaphore bit by the processor performing the register write. 
+#define ARB_SEMA_SMP_PUT_0_PUT_31_PUT_0_SHIFT                   _MK_SHIFT_CONST(0)
+#define ARB_SEMA_SMP_PUT_0_PUT_31_PUT_0_FIELD                   (_MK_MASK_CONST(0xffffffff) << ARB_SEMA_SMP_PUT_0_PUT_31_PUT_0_SHIFT)
+#define ARB_SEMA_SMP_PUT_0_PUT_31_PUT_0_RANGE                   31:0
+#define ARB_SEMA_SMP_PUT_0_PUT_31_PUT_0_WOFFSET                 0x0
+#define ARB_SEMA_SMP_PUT_0_PUT_31_PUT_0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define ARB_SEMA_SMP_PUT_0_PUT_31_PUT_0_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
+#define ARB_SEMA_SMP_PUT_0_PUT_31_PUT_0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define ARB_SEMA_SMP_PUT_0_PUT_31_PUT_0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Arbitration Request Pending Status (1=PENDING) Register
+
+// Register ARB_SEMA_SMP_REQ_ST_0  
+#define ARB_SEMA_SMP_REQ_ST_0                   _MK_ADDR_CONST(0xc)
+#define ARB_SEMA_SMP_REQ_ST_0_WORD_COUNT                        0x1
+#define ARB_SEMA_SMP_REQ_ST_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define ARB_SEMA_SMP_REQ_ST_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
+#define ARB_SEMA_SMP_REQ_ST_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define ARB_SEMA_SMP_REQ_ST_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define ARB_SEMA_SMP_REQ_ST_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define ARB_SEMA_SMP_REQ_ST_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+// A one in any bit indicates a request pending status.  The corresponding bits are set when the request for the individual resource  is pending. The read by CPU of this register shows the pending status for CPU  and a read of this register by AVP (COP) shows the pending status for AVP.
+#define ARB_SEMA_SMP_REQ_ST_0_REQ_31_REQ_0_SHIFT                        _MK_SHIFT_CONST(0)
+#define ARB_SEMA_SMP_REQ_ST_0_REQ_31_REQ_0_FIELD                        (_MK_MASK_CONST(0xffffffff) << ARB_SEMA_SMP_REQ_ST_0_REQ_31_REQ_0_SHIFT)
+#define ARB_SEMA_SMP_REQ_ST_0_REQ_31_REQ_0_RANGE                        31:0
+#define ARB_SEMA_SMP_REQ_ST_0_REQ_31_REQ_0_WOFFSET                      0x0
+#define ARB_SEMA_SMP_REQ_ST_0_REQ_31_REQ_0_DEFAULT                      _MK_MASK_CONST(0x0)
+#define ARB_SEMA_SMP_REQ_ST_0_REQ_31_REQ_0_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
+#define ARB_SEMA_SMP_REQ_ST_0_REQ_31_REQ_0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define ARB_SEMA_SMP_REQ_ST_0_REQ_31_REQ_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+//
+// REGISTER LIST
+//
+#define LIST_ARARB_SEMA_REGS(_op_) \
+_op_(ARB_SEMA_SMP_GNT_ST_0) \
+_op_(ARB_SEMA_SMP_GET_0) \
+_op_(ARB_SEMA_SMP_PUT_0) \
+_op_(ARB_SEMA_SMP_REQ_ST_0)
+
+
+//
+// ADDRESS SPACES
+//
+
+#define BASE_ADDRESS_ARB_SEMA   0x00000000
+
+//
+// ARARB_SEMA REGISTER BANKS
+//
+
+#define ARB_SEMA0_FIRST_REG 0x0000 // ARB_SEMA_SMP_GNT_ST_0
+#define ARB_SEMA0_LAST_REG 0x000c // ARB_SEMA_SMP_REQ_ST_0
+
+#ifndef _MK_SHIFT_CONST
+  #define _MK_SHIFT_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_MASK_CONST
+  #define _MK_MASK_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_ENUM_CONST
+  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
+#endif
+#ifndef _MK_ADDR_CONST
+  #define _MK_ADDR_CONST(_constant_) _constant_
+#endif
+
+#endif // ifndef ___ARARB_SEMA_H_INC_
diff --git a/arch/arm/mach-tegra/include/ap15/arclk_rst.h b/arch/arm/mach-tegra/include/ap15/arclk_rst.h
new file mode 100644
index 000000000000..538e8935ba35
--- /dev/null
+++ b/arch/arm/mach-tegra/include/ap15/arclk_rst.h
@@ -0,0 +1,7272 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+//
+// DO NOT EDIT - generated by simspec!
+//
+
+#ifndef ___ARCLK_RST_H_INC_
+#define ___ARCLK_RST_H_INC_
+
+// Register CLK_RST_CONTROLLER_RST_SOURCE_0  
+#define CLK_RST_CONTROLLER_RST_SOURCE_0                 _MK_ADDR_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WORD_COUNT                      0x1
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_RESET_MASK                      _MK_MASK_CONST(0x3f37)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_READ_MASK                       _MK_MASK_CONST(0x3f37)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WRITE_MASK                      _MK_MASK_CONST(0x37)
+// System reset by SW (RO)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_SWR_SYS_RST_STA_SHIFT                   _MK_SHIFT_CONST(13)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_SWR_SYS_RST_STA_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_SOURCE_0_SWR_SYS_RST_STA_SHIFT)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_SWR_SYS_RST_STA_RANGE                   13:13
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_SWR_SYS_RST_STA_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_SWR_SYS_RST_STA_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_SWR_SYS_RST_STA_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_SWR_SYS_RST_STA_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_SWR_SYS_RST_STA_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// System reset by watch dog timer (RO)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SYS_RST_STA_SHIFT                   _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SYS_RST_STA_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SYS_RST_STA_SHIFT)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SYS_RST_STA_RANGE                   12:12
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SYS_RST_STA_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SYS_RST_STA_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SYS_RST_STA_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SYS_RST_STA_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SYS_RST_STA_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// COP reset by SW (RO)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_SWR_COP_RST_STA_SHIFT                   _MK_SHIFT_CONST(11)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_SWR_COP_RST_STA_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_SOURCE_0_SWR_COP_RST_STA_SHIFT)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_SWR_COP_RST_STA_RANGE                   11:11
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_SWR_COP_RST_STA_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_SWR_COP_RST_STA_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_SWR_COP_RST_STA_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_SWR_COP_RST_STA_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_SWR_COP_RST_STA_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// COP reset by watch dog timer (RO)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_COP_RST_STA_SHIFT                   _MK_SHIFT_CONST(10)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_COP_RST_STA_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_COP_RST_STA_SHIFT)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_COP_RST_STA_RANGE                   10:10
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_COP_RST_STA_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_COP_RST_STA_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_COP_RST_STA_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_COP_RST_STA_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_COP_RST_STA_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// CPU reset by SW (RO)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_SWR_CPU_RST_STA_SHIFT                   _MK_SHIFT_CONST(9)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_SWR_CPU_RST_STA_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_SOURCE_0_SWR_CPU_RST_STA_SHIFT)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_SWR_CPU_RST_STA_RANGE                   9:9
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_SWR_CPU_RST_STA_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_SWR_CPU_RST_STA_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_SWR_CPU_RST_STA_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_SWR_CPU_RST_STA_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_SWR_CPU_RST_STA_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// CPU reset by watch dog timer (RO)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_CPU_RST_STA_SHIFT                   _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_CPU_RST_STA_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_CPU_RST_STA_SHIFT)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_CPU_RST_STA_RANGE                   8:8
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_CPU_RST_STA_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_CPU_RST_STA_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_CPU_RST_STA_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_CPU_RST_STA_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_CPU_RST_STA_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Enable Watch Dog Timer (Dead Man Timer)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_EN_SHIFT                    _MK_SHIFT_CONST(5)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_EN_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_EN_SHIFT)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_EN_RANGE                    5:5
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_EN_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_EN_INIT_ENUM                        DISABLE
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_EN_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_EN_ENABLE                   _MK_ENUM_CONST(1)
+
+// Watch Dog Timer Select 
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SEL_SHIFT                   _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SEL_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SEL_SHIFT)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SEL_RANGE                   4:4
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SEL_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SEL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SEL_INIT_ENUM                       TIMER1
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SEL_TIMER1                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SEL_TIMER2                  _MK_ENUM_CONST(1)
+
+// Enable Watch Dog Timer reset for system.
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SYS_RST_EN_SHIFT                    _MK_SHIFT_CONST(2)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SYS_RST_EN_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SYS_RST_EN_SHIFT)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SYS_RST_EN_RANGE                    2:2
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SYS_RST_EN_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SYS_RST_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SYS_RST_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SYS_RST_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SYS_RST_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SYS_RST_EN_INIT_ENUM                        DISABLE
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SYS_RST_EN_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SYS_RST_EN_ENABLE                   _MK_ENUM_CONST(1)
+
+// Enable Watch Dog Timer reset for COP
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_COP_RST_EN_SHIFT                    _MK_SHIFT_CONST(1)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_COP_RST_EN_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_COP_RST_EN_SHIFT)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_COP_RST_EN_RANGE                    1:1
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_COP_RST_EN_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_COP_RST_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_COP_RST_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_COP_RST_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_COP_RST_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_COP_RST_EN_INIT_ENUM                        DISABLE
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_COP_RST_EN_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_COP_RST_EN_ENABLE                   _MK_ENUM_CONST(1)
+
+// Enable Watch Dog Timer reset for CPU
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_CPU_RST_EN_SHIFT                    _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_CPU_RST_EN_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_CPU_RST_EN_SHIFT)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_CPU_RST_EN_RANGE                    0:0
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_CPU_RST_EN_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_CPU_RST_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_CPU_RST_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_CPU_RST_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_CPU_RST_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_CPU_RST_EN_INIT_ENUM                        DISABLE
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_CPU_RST_EN_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_CPU_RST_EN_ENABLE                   _MK_ENUM_CONST(1)
+
+
+// Register CLK_RST_CONTROLLER_RST_DEVICES_L_0  
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0                      _MK_ADDR_CONST(0x4)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_WORD_COUNT                   0x1
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_RESET_VAL                    _MK_MASK_CONST(0x7ffffec9)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
+// Reset COP cache controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CACHE2_RST_SHIFT                 _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CACHE2_RST_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CACHE2_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CACHE2_RST_RANGE                 31:31
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CACHE2_RST_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CACHE2_RST_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CACHE2_RST_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CACHE2_RST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CACHE2_RST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CACHE2_RST_INIT_ENUM                     DISABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CACHE2_RST_DISABLE                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CACHE2_RST_ENABLE                        _MK_ENUM_CONST(1)
+
+// Reset CPU cache controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CACHE1_RST_SHIFT                 _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CACHE1_RST_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CACHE1_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CACHE1_RST_RANGE                 30:30
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CACHE1_RST_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CACHE1_RST_DEFAULT                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CACHE1_RST_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CACHE1_RST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CACHE1_RST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CACHE1_RST_INIT_ENUM                     ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CACHE1_RST_DISABLE                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CACHE1_RST_ENABLE                        _MK_ENUM_CONST(1)
+
+// Reset vector co-processor.
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_VCP_RST_SHIFT                    _MK_SHIFT_CONST(29)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_VCP_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_VCP_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_VCP_RST_RANGE                    29:29
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_VCP_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_VCP_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_VCP_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_VCP_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_VCP_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_VCP_RST_INIT_ENUM                        ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_VCP_RST_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_VCP_RST_ENABLE                   _MK_ENUM_CONST(1)
+
+// Reset HOST1X.
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_HOST1X_RST_SHIFT                 _MK_SHIFT_CONST(28)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_HOST1X_RST_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_HOST1X_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_HOST1X_RST_RANGE                 28:28
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_HOST1X_RST_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_HOST1X_RST_DEFAULT                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_HOST1X_RST_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_HOST1X_RST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_HOST1X_RST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_HOST1X_RST_INIT_ENUM                     ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_HOST1X_RST_DISABLE                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_HOST1X_RST_ENABLE                        _MK_ENUM_CONST(1)
+
+// Reset DISP1 controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_DISP1_RST_SHIFT                  _MK_SHIFT_CONST(27)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_DISP1_RST_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_DISP1_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_DISP1_RST_RANGE                  27:27
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_DISP1_RST_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_DISP1_RST_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_DISP1_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_DISP1_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_DISP1_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_DISP1_RST_INIT_ENUM                      ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_DISP1_RST_DISABLE                        _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_DISP1_RST_ENABLE                 _MK_ENUM_CONST(1)
+
+// Reset DISP2 controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_DISP2_RST_SHIFT                  _MK_SHIFT_CONST(26)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_DISP2_RST_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_DISP2_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_DISP2_RST_RANGE                  26:26
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_DISP2_RST_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_DISP2_RST_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_DISP2_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_DISP2_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_DISP2_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_DISP2_RST_INIT_ENUM                      ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_DISP2_RST_DISABLE                        _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_DISP2_RST_ENABLE                 _MK_ENUM_CONST(1)
+
+// Reset IDE controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_IDE_RST_SHIFT                    _MK_SHIFT_CONST(25)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_IDE_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_IDE_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_IDE_RST_RANGE                    25:25
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_IDE_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_IDE_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_IDE_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_IDE_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_IDE_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_IDE_RST_INIT_ENUM                        ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_IDE_RST_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_IDE_RST_ENABLE                   _MK_ENUM_CONST(1)
+
+// Reset 3D controlelr.
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_3D_RST_SHIFT                     _MK_SHIFT_CONST(24)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_3D_RST_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_3D_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_3D_RST_RANGE                     24:24
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_3D_RST_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_3D_RST_DEFAULT                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_3D_RST_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_3D_RST_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_3D_RST_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_3D_RST_INIT_ENUM                 ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_3D_RST_DISABLE                   _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_3D_RST_ENABLE                    _MK_ENUM_CONST(1)
+
+// Reset ISP controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_ISP_RST_SHIFT                    _MK_SHIFT_CONST(23)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_ISP_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_ISP_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_ISP_RST_RANGE                    23:23
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_ISP_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_ISP_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_ISP_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_ISP_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_ISP_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_ISP_RST_INIT_ENUM                        ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_ISP_RST_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_ISP_RST_ENABLE                   _MK_ENUM_CONST(1)
+
+// Reset USB controller
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_USBD_RST_SHIFT                   _MK_SHIFT_CONST(22)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_USBD_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_USBD_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_USBD_RST_RANGE                   22:22
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_USBD_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_USBD_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_USBD_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_USBD_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_USBD_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_USBD_RST_INIT_ENUM                       ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_USBD_RST_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_USBD_RST_ENABLE                  _MK_ENUM_CONST(1)
+
+// Reset 2D graphics engine controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_2D_RST_SHIFT                     _MK_SHIFT_CONST(21)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_2D_RST_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_2D_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_2D_RST_RANGE                     21:21
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_2D_RST_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_2D_RST_DEFAULT                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_2D_RST_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_2D_RST_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_2D_RST_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_2D_RST_INIT_ENUM                 ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_2D_RST_DISABLE                   _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_2D_RST_ENABLE                    _MK_ENUM_CONST(1)
+
+// Reset VI controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_VI_RST_SHIFT                     _MK_SHIFT_CONST(20)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_VI_RST_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_VI_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_VI_RST_RANGE                     20:20
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_VI_RST_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_VI_RST_DEFAULT                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_VI_RST_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_VI_RST_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_VI_RST_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_VI_RST_INIT_ENUM                 ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_VI_RST_DISABLE                   _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_VI_RST_ENABLE                    _MK_ENUM_CONST(1)
+
+// Reset EPP controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_EPP_RST_SHIFT                    _MK_SHIFT_CONST(19)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_EPP_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_EPP_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_EPP_RST_RANGE                    19:19
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_EPP_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_EPP_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_EPP_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_EPP_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_EPP_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_EPP_RST_INIT_ENUM                        ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_EPP_RST_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_EPP_RST_ENABLE                   _MK_ENUM_CONST(1)
+
+// Reset I2S 2 Controller
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2S2_RST_SHIFT                   _MK_SHIFT_CONST(18)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2S2_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2S2_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2S2_RST_RANGE                   18:18
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2S2_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2S2_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2S2_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2S2_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2S2_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2S2_RST_INIT_ENUM                       ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2S2_RST_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2S2_RST_ENABLE                  _MK_ENUM_CONST(1)
+
+// Reset Pulse Width Modulator
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_PWM_RST_SHIFT                    _MK_SHIFT_CONST(17)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_PWM_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_PWM_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_PWM_RST_RANGE                    17:17
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_PWM_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_PWM_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_PWM_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_PWM_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_PWM_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_PWM_RST_INIT_ENUM                        ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_PWM_RST_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_PWM_RST_ENABLE                   _MK_ENUM_CONST(1)
+
+// Reset Three Wire Controller
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TWC_RST_SHIFT                    _MK_SHIFT_CONST(16)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TWC_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TWC_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TWC_RST_RANGE                    16:16
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TWC_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TWC_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TWC_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TWC_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TWC_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TWC_RST_INIT_ENUM                        ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TWC_RST_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TWC_RST_ENABLE                   _MK_ENUM_CONST(1)
+
+// Reset HSMMC controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_HSMMC_RST_SHIFT                  _MK_SHIFT_CONST(15)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_HSMMC_RST_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_HSMMC_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_HSMMC_RST_RANGE                  15:15
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_HSMMC_RST_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_HSMMC_RST_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_HSMMC_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_HSMMC_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_HSMMC_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_HSMMC_RST_INIT_ENUM                      ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_HSMMC_RST_DISABLE                        _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_HSMMC_RST_ENABLE                 _MK_ENUM_CONST(1)
+
+// Reset SDIO1 controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SDIO1_RST_SHIFT                  _MK_SHIFT_CONST(14)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SDIO1_RST_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SDIO1_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SDIO1_RST_RANGE                  14:14
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SDIO1_RST_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SDIO1_RST_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SDIO1_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SDIO1_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SDIO1_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SDIO1_RST_INIT_ENUM                      ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SDIO1_RST_DISABLE                        _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SDIO1_RST_ENABLE                 _MK_ENUM_CONST(1)
+
+// Reset NAND flash controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_NDFLASH_RST_SHIFT                        _MK_SHIFT_CONST(13)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_NDFLASH_RST_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_NDFLASH_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_NDFLASH_RST_RANGE                        13:13
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_NDFLASH_RST_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_NDFLASH_RST_DEFAULT                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_NDFLASH_RST_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_NDFLASH_RST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_NDFLASH_RST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_NDFLASH_RST_INIT_ENUM                    ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_NDFLASH_RST_DISABLE                      _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_NDFLASH_RST_ENABLE                       _MK_ENUM_CONST(1)
+
+// Reset I2C1 Controller
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2C1_RST_SHIFT                   _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2C1_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2C1_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2C1_RST_RANGE                   12:12
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2C1_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2C1_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2C1_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2C1_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2C1_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2C1_RST_INIT_ENUM                       ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2C1_RST_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2C1_RST_ENABLE                  _MK_ENUM_CONST(1)
+
+// Reset I2S 1 Controller
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2S1_RST_SHIFT                   _MK_SHIFT_CONST(11)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2S1_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2S1_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2S1_RST_RANGE                   11:11
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2S1_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2S1_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2S1_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2S1_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2S1_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2S1_RST_INIT_ENUM                       ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2S1_RST_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2S1_RST_ENABLE                  _MK_ENUM_CONST(1)
+
+// Reset SPDIF Controller
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SPDIF_RST_SHIFT                  _MK_SHIFT_CONST(10)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SPDIF_RST_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SPDIF_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SPDIF_RST_RANGE                  10:10
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SPDIF_RST_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SPDIF_RST_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SPDIF_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SPDIF_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SPDIF_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SPDIF_RST_INIT_ENUM                      ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SPDIF_RST_DISABLE                        _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SPDIF_RST_ENABLE                 _MK_ENUM_CONST(1)
+
+// Reset SDIO2 Controller
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SDIO2_RST_SHIFT                  _MK_SHIFT_CONST(9)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SDIO2_RST_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SDIO2_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SDIO2_RST_RANGE                  9:9
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SDIO2_RST_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SDIO2_RST_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SDIO2_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SDIO2_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SDIO2_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SDIO2_RST_INIT_ENUM                      ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SDIO2_RST_DISABLE                        _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SDIO2_RST_ENABLE                 _MK_ENUM_CONST(1)
+
+// Reset GPIO Controller
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_GPIO_RST_SHIFT                   _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_GPIO_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_GPIO_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_GPIO_RST_RANGE                   8:8
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_GPIO_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_GPIO_RST_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_GPIO_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_GPIO_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_GPIO_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_GPIO_RST_INIT_ENUM                       DISABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_GPIO_RST_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_GPIO_RST_ENABLE                  _MK_ENUM_CONST(1)
+
+// Reset UARTB/VFIR Controller
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_UARTB_RST_SHIFT                  _MK_SHIFT_CONST(7)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_UARTB_RST_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_UARTB_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_UARTB_RST_RANGE                  7:7
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_UARTB_RST_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_UARTB_RST_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_UARTB_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_UARTB_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_UARTB_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_UARTB_RST_INIT_ENUM                      ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_UARTB_RST_DISABLE                        _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_UARTB_RST_ENABLE                 _MK_ENUM_CONST(1)
+
+// Reset UARTA Controller 
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_UARTA_RST_SHIFT                  _MK_SHIFT_CONST(6)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_UARTA_RST_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_UARTA_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_UARTA_RST_RANGE                  6:6
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_UARTA_RST_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_UARTA_RST_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_UARTA_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_UARTA_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_UARTA_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_UARTA_RST_INIT_ENUM                      ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_UARTA_RST_DISABLE                        _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_UARTA_RST_ENABLE                 _MK_ENUM_CONST(1)
+
+// Reset Timer Controller
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TMR_RST_SHIFT                    _MK_SHIFT_CONST(5)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TMR_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TMR_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TMR_RST_RANGE                    5:5
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TMR_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TMR_RST_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TMR_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TMR_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TMR_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TMR_RST_INIT_ENUM                        DISABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TMR_RST_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TMR_RST_ENABLE                   _MK_ENUM_CONST(1)
+
+// Reset RTC Controller
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_RTC_RST_SHIFT                    _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_RTC_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_RTC_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_RTC_RST_RANGE                    4:4
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_RTC_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_RTC_RST_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_RTC_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_RTC_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_RTC_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_RTC_RST_INIT_ENUM                        DISABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_RTC_RST_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_RTC_RST_ENABLE                   _MK_ENUM_CONST(1)
+
+// Reset AC97 Controller
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_AC97_RST_SHIFT                   _MK_SHIFT_CONST(3)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_AC97_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_AC97_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_AC97_RST_RANGE                   3:3
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_AC97_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_AC97_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_AC97_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_AC97_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_AC97_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_AC97_RST_INIT_ENUM                       ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_AC97_RST_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_AC97_RST_ENABLE                  _MK_ENUM_CONST(1)
+
+// Write 1 to pulse System Reset Signal. HW clears  this bit
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TRIG_SYS_RST_SHIFT                       _MK_SHIFT_CONST(2)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TRIG_SYS_RST_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TRIG_SYS_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TRIG_SYS_RST_RANGE                       2:2
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TRIG_SYS_RST_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TRIG_SYS_RST_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TRIG_SYS_RST_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TRIG_SYS_RST_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TRIG_SYS_RST_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TRIG_SYS_RST_INIT_ENUM                   DISABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TRIG_SYS_RST_DISABLE                     _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TRIG_SYS_RST_ENABLE                      _MK_ENUM_CONST(1)
+
+// Write 1 to force COP Reset Signal. SW needs to  clear this bit when done.
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_COP_RST_SHIFT                    _MK_SHIFT_CONST(1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_COP_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_COP_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_COP_RST_RANGE                    1:1
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_COP_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_COP_RST_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_COP_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_COP_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_COP_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_COP_RST_INIT_ENUM                        DISABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_COP_RST_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_COP_RST_ENABLE                   _MK_ENUM_CONST(1)
+
+// Write 1 to force CPU Reset Signal. SW needs to  clear this bit when done.
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CPU_RST_SHIFT                    _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CPU_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CPU_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CPU_RST_RANGE                    0:0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CPU_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CPU_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CPU_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CPU_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CPU_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CPU_RST_INIT_ENUM                        ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CPU_RST_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CPU_RST_ENABLE                   _MK_ENUM_CONST(1)
+
+
+// Register CLK_RST_CONTROLLER_RST_DEVICES_H_0  
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0                      _MK_ADDR_CONST(0x8)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_WORD_COUNT                   0x1
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_RESET_VAL                    _MK_MASK_CONST(0xf3fffb77)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_RESET_MASK                   _MK_MASK_CONST(0xf3fffff7)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_READ_MASK                    _MK_MASK_CONST(0xf3fffff7)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_WRITE_MASK                   _MK_MASK_CONST(0xf3fffff7)
+// Reset BSEV controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_BSEV_RST_SHIFT                   _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_BSEV_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_BSEV_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_BSEV_RST_RANGE                   31:31
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_BSEV_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_BSEV_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_BSEV_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_BSEV_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_BSEV_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_BSEV_RST_INIT_ENUM                       ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_BSEV_RST_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_BSEV_RST_ENABLE                  _MK_ENUM_CONST(1)
+
+// Reset BSEA controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_BSEA_RST_SHIFT                   _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_BSEA_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_BSEA_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_BSEA_RST_RANGE                   30:30
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_BSEA_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_BSEA_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_BSEA_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_BSEA_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_BSEA_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_BSEA_RST_INIT_ENUM                       ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_BSEA_RST_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_BSEA_RST_ENABLE                  _MK_ENUM_CONST(1)
+
+// Reset VDE controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_VDE_RST_SHIFT                    _MK_SHIFT_CONST(29)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_VDE_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_VDE_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_VDE_RST_RANGE                    29:29
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_VDE_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_VDE_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_VDE_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_VDE_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_VDE_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_VDE_RST_INIT_ENUM                        ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_VDE_RST_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_VDE_RST_ENABLE                   _MK_ENUM_CONST(1)
+
+// Reset MPE controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MPE_RST_SHIFT                    _MK_SHIFT_CONST(28)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MPE_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MPE_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MPE_RST_RANGE                    28:28
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MPE_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MPE_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MPE_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MPE_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MPE_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MPE_RST_INIT_ENUM                        ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MPE_RST_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MPE_RST_ENABLE                   _MK_ENUM_CONST(1)
+
+// Reset EMC controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_EMC_RST_SHIFT                    _MK_SHIFT_CONST(25)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_EMC_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_EMC_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_EMC_RST_RANGE                    25:25
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_EMC_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_EMC_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_EMC_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_EMC_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_EMC_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_EMC_RST_INIT_ENUM                        ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_EMC_RST_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_EMC_RST_ENABLE                   _MK_ENUM_CONST(1)
+
+// Reset SPROM Controller
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SPROM_RST_SHIFT                  _MK_SHIFT_CONST(24)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SPROM_RST_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SPROM_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SPROM_RST_RANGE                  24:24
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SPROM_RST_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SPROM_RST_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SPROM_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SPROM_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SPROM_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SPROM_RST_INIT_ENUM                      ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SPROM_RST_DISABLE                        _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SPROM_RST_ENABLE                 _MK_ENUM_CONST(1)
+
+// Reset UART C Controller
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_UARTC_RST_SHIFT                  _MK_SHIFT_CONST(23)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_UARTC_RST_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_UARTC_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_UARTC_RST_RANGE                  23:23
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_UARTC_RST_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_UARTC_RST_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_UARTC_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_UARTC_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_UARTC_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_UARTC_RST_INIT_ENUM                      ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_UARTC_RST_DISABLE                        _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_UARTC_RST_ENABLE                 _MK_ENUM_CONST(1)
+
+// Reset I2C 2 controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_I2C2_RST_SHIFT                   _MK_SHIFT_CONST(22)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_I2C2_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_I2C2_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_I2C2_RST_RANGE                   22:22
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_I2C2_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_I2C2_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_I2C2_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_I2C2_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_I2C2_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_I2C2_RST_INIT_ENUM                       ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_I2C2_RST_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_I2C2_RST_ENABLE                  _MK_ENUM_CONST(1)
+
+// Reset TVDAC controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_TVDAC_RST_SHIFT                  _MK_SHIFT_CONST(21)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_TVDAC_RST_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_TVDAC_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_TVDAC_RST_RANGE                  21:21
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_TVDAC_RST_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_TVDAC_RST_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_TVDAC_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_TVDAC_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_TVDAC_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_TVDAC_RST_INIT_ENUM                      ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_TVDAC_RST_DISABLE                        _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_TVDAC_RST_ENABLE                 _MK_ENUM_CONST(1)
+
+// Reset CSI controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_CSI_RST_SHIFT                    _MK_SHIFT_CONST(20)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_CSI_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_CSI_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_CSI_RST_RANGE                    20:20
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_CSI_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_CSI_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_CSI_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_CSI_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_CSI_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_CSI_RST_INIT_ENUM                        ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_CSI_RST_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_CSI_RST_ENABLE                   _MK_ENUM_CONST(1)
+
+// Reset HDMI
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_HDMI_RST_SHIFT                   _MK_SHIFT_CONST(19)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_HDMI_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_HDMI_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_HDMI_RST_RANGE                   19:19
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_HDMI_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_HDMI_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_HDMI_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_HDMI_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_HDMI_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_HDMI_RST_INIT_ENUM                       ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_HDMI_RST_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_HDMI_RST_ENABLE                  _MK_ENUM_CONST(1)
+
+// Reset MIPI base-band controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MIPI_RST_SHIFT                   _MK_SHIFT_CONST(18)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MIPI_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MIPI_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MIPI_RST_RANGE                   18:18
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MIPI_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MIPI_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MIPI_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MIPI_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MIPI_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MIPI_RST_INIT_ENUM                       ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MIPI_RST_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MIPI_RST_ENABLE                  _MK_ENUM_CONST(1)
+
+// Reset TVO/CVE controller
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_TVO_RST_SHIFT                    _MK_SHIFT_CONST(17)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_TVO_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_TVO_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_TVO_RST_RANGE                    17:17
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_TVO_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_TVO_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_TVO_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_TVO_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_TVO_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_TVO_RST_INIT_ENUM                        ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_TVO_RST_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_TVO_RST_ENABLE                   _MK_ENUM_CONST(1)
+
+// Reset DSI controller
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_DSI_RST_SHIFT                    _MK_SHIFT_CONST(16)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_DSI_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_DSI_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_DSI_RST_RANGE                    16:16
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_DSI_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_DSI_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_DSI_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_DSI_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_DSI_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_DSI_RST_INIT_ENUM                        ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_DSI_RST_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_DSI_RST_ENABLE                   _MK_ENUM_CONST(1)
+
+// Reset DVC-I2C Controller
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_DVC_I2C_RST_SHIFT                        _MK_SHIFT_CONST(15)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_DVC_I2C_RST_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_DVC_I2C_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_DVC_I2C_RST_RANGE                        15:15
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_DVC_I2C_RST_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_DVC_I2C_RST_DEFAULT                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_DVC_I2C_RST_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_DVC_I2C_RST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_DVC_I2C_RST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_DVC_I2C_RST_INIT_ENUM                    ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_DVC_I2C_RST_DISABLE                      _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_DVC_I2C_RST_ENABLE                       _MK_ENUM_CONST(1)
+
+// Reset SBC 3 Controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC3_RST_SHIFT                   _MK_SHIFT_CONST(14)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC3_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC3_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC3_RST_RANGE                   14:14
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC3_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC3_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC3_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC3_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC3_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC3_RST_INIT_ENUM                       ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC3_RST_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC3_RST_ENABLE                  _MK_ENUM_CONST(1)
+
+// Reset XIO controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_XIO_RST_SHIFT                    _MK_SHIFT_CONST(13)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_XIO_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_XIO_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_XIO_RST_RANGE                    13:13
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_XIO_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_XIO_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_XIO_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_XIO_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_XIO_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_XIO_RST_INIT_ENUM                        ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_XIO_RST_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_XIO_RST_ENABLE                   _MK_ENUM_CONST(1)
+
+// Reset SBC 2 Controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC2_RST_SHIFT                   _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC2_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC2_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC2_RST_RANGE                   12:12
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC2_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC2_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC2_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC2_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC2_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC2_RST_INIT_ENUM                       ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC2_RST_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC2_RST_ENABLE                  _MK_ENUM_CONST(1)
+
+// Reset SPI 1 Controller
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SPI1_RST_SHIFT                   _MK_SHIFT_CONST(11)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SPI1_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SPI1_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SPI1_RST_RANGE                   11:11
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SPI1_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SPI1_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SPI1_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SPI1_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SPI1_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SPI1_RST_INIT_ENUM                       ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SPI1_RST_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SPI1_RST_ENABLE                  _MK_ENUM_CONST(1)
+
+// Reset NOR Flash Controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_NOR_RST_SHIFT                    _MK_SHIFT_CONST(10)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_NOR_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_NOR_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_NOR_RST_RANGE                    10:10
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_NOR_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_NOR_RST_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_NOR_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_NOR_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_NOR_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_NOR_RST_INIT_ENUM                        DISABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_NOR_RST_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_NOR_RST_ENABLE                   _MK_ENUM_CONST(1)
+
+// Reset SBC 1 Controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC1_RST_SHIFT                   _MK_SHIFT_CONST(9)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC1_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC1_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC1_RST_RANGE                   9:9
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC1_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC1_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC1_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC1_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC1_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC1_RST_INIT_ENUM                       ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC1_RST_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC1_RST_ENABLE                  _MK_ENUM_CONST(1)
+
+// Reset Serial Link Controller
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SLC1_RST_SHIFT                   _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SLC1_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SLC1_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SLC1_RST_RANGE                   8:8
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SLC1_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SLC1_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SLC1_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SLC1_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SLC1_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SLC1_RST_INIT_ENUM                       ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SLC1_RST_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SLC1_RST_ENABLE                  _MK_ENUM_CONST(1)
+
+// Reset Fuse controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_FUSE_RST_SHIFT                   _MK_SHIFT_CONST(7)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_FUSE_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_FUSE_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_FUSE_RST_RANGE                   7:7
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_FUSE_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_FUSE_RST_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_FUSE_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_FUSE_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_FUSE_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_FUSE_RST_INIT_ENUM                       DISABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_FUSE_RST_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_FUSE_RST_ENABLE                  _MK_ENUM_CONST(1)
+
+// Reset PMC controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_PMC_RST_SHIFT                    _MK_SHIFT_CONST(6)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_PMC_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_PMC_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_PMC_RST_RANGE                    6:6
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_PMC_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_PMC_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_PMC_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_PMC_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_PMC_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_PMC_RST_INIT_ENUM                        ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_PMC_RST_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_PMC_RST_ENABLE                   _MK_ENUM_CONST(1)
+
+// Reset statistic monitor
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_STAT_MON_RST_SHIFT                       _MK_SHIFT_CONST(5)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_STAT_MON_RST_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_STAT_MON_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_STAT_MON_RST_RANGE                       5:5
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_STAT_MON_RST_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_STAT_MON_RST_DEFAULT                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_STAT_MON_RST_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_STAT_MON_RST_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_STAT_MON_RST_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_STAT_MON_RST_INIT_ENUM                   ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_STAT_MON_RST_DISABLE                     _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_STAT_MON_RST_ENABLE                      _MK_ENUM_CONST(1)
+
+// Reset Keyboard controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_KBC_RST_SHIFT                    _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_KBC_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_KBC_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_KBC_RST_RANGE                    4:4
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_KBC_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_KBC_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_KBC_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_KBC_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_KBC_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_KBC_RST_INIT_ENUM                        ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_KBC_RST_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_KBC_RST_ENABLE                   _MK_ENUM_CONST(1)
+
+// Reset APB-DMA.
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_APBDMA_RST_SHIFT                 _MK_SHIFT_CONST(2)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_APBDMA_RST_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_APBDMA_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_APBDMA_RST_RANGE                 2:2
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_APBDMA_RST_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_APBDMA_RST_DEFAULT                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_APBDMA_RST_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_APBDMA_RST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_APBDMA_RST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_APBDMA_RST_INIT_ENUM                     ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_APBDMA_RST_DISABLE                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_APBDMA_RST_ENABLE                        _MK_ENUM_CONST(1)
+
+// Reset AHB-DMA.
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_AHBDMA_RST_SHIFT                 _MK_SHIFT_CONST(1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_AHBDMA_RST_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_AHBDMA_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_AHBDMA_RST_RANGE                 1:1
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_AHBDMA_RST_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_AHBDMA_RST_DEFAULT                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_AHBDMA_RST_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_AHBDMA_RST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_AHBDMA_RST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_AHBDMA_RST_INIT_ENUM                     ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_AHBDMA_RST_DISABLE                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_AHBDMA_RST_ENABLE                        _MK_ENUM_CONST(1)
+
+// Reset MC.
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MEM_RST_SHIFT                    _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MEM_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MEM_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MEM_RST_RANGE                    0:0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MEM_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MEM_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MEM_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MEM_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MEM_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MEM_RST_INIT_ENUM                        ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MEM_RST_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MEM_RST_ENABLE                   _MK_ENUM_CONST(1)
+
+
+// Reserved address 12 [0xc] 
+
+// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0  
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0                      _MK_ADDR_CONST(0x10)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_WORD_COUNT                   0x1
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_RESET_VAL                    _MK_MASK_CONST(0x80000130)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_RESET_MASK                   _MK_MASK_CONST(0xfffffff9)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_READ_MASK                    _MK_MASK_CONST(0xfffffff9)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_WRITE_MASK                   _MK_MASK_CONST(0xfffffff9)
+// Enable clock to COP cache controller.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CACHE2_SHIFT                 _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CACHE2_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CACHE2_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CACHE2_RANGE                 31:31
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CACHE2_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CACHE2_DEFAULT                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CACHE2_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CACHE2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CACHE2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CACHE2_INIT_ENUM                     ENABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CACHE2_DISABLE                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CACHE2_ENABLE                        _MK_ENUM_CONST(1)
+
+// Enable clock to CPU cache controller.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CACHE1_SHIFT                 _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CACHE1_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CACHE1_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CACHE1_RANGE                 30:30
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CACHE1_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CACHE1_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CACHE1_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CACHE1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CACHE1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CACHE1_INIT_ENUM                     DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CACHE1_DISABLE                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CACHE1_ENABLE                        _MK_ENUM_CONST(1)
+
+// Enable clock to vector co-processor.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_VCP_SHIFT                    _MK_SHIFT_CONST(29)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_VCP_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_VCP_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_VCP_RANGE                    29:29
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_VCP_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_VCP_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_VCP_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_VCP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_VCP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_VCP_INIT_ENUM                        DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_VCP_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_VCP_ENABLE                   _MK_ENUM_CONST(1)
+
+// Enable clock to HOST1X.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_HOST1X_SHIFT                 _MK_SHIFT_CONST(28)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_HOST1X_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_HOST1X_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_HOST1X_RANGE                 28:28
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_HOST1X_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_HOST1X_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_HOST1X_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_HOST1X_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_HOST1X_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_HOST1X_INIT_ENUM                     DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_HOST1X_DISABLE                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_HOST1X_ENABLE                        _MK_ENUM_CONST(1)
+
+// Enable clock to DISP1 controller.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_DISP1_SHIFT                  _MK_SHIFT_CONST(27)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_DISP1_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_DISP1_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_DISP1_RANGE                  27:27
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_DISP1_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_DISP1_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_DISP1_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_DISP1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_DISP1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_DISP1_INIT_ENUM                      DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_DISP1_DISABLE                        _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_DISP1_ENABLE                 _MK_ENUM_CONST(1)
+
+// Enable clock to DISP2 controller.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_DISP2_SHIFT                  _MK_SHIFT_CONST(26)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_DISP2_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_DISP2_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_DISP2_RANGE                  26:26
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_DISP2_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_DISP2_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_DISP2_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_DISP2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_DISP2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_DISP2_INIT_ENUM                      DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_DISP2_DISABLE                        _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_DISP2_ENABLE                 _MK_ENUM_CONST(1)
+
+// Enable clock to IDE controller
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_IDE_SHIFT                    _MK_SHIFT_CONST(25)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_IDE_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_IDE_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_IDE_RANGE                    25:25
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_IDE_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_IDE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_IDE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_IDE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_IDE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_IDE_INIT_ENUM                        DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_IDE_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_IDE_ENABLE                   _MK_ENUM_CONST(1)
+
+// Enable clock to 3D controller.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_3D_SHIFT                     _MK_SHIFT_CONST(24)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_3D_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_3D_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_3D_RANGE                     24:24
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_3D_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_3D_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_3D_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_3D_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_3D_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_3D_INIT_ENUM                 DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_3D_DISABLE                   _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_3D_ENABLE                    _MK_ENUM_CONST(1)
+
+// Enable clock to ISP controller.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_ISP_SHIFT                    _MK_SHIFT_CONST(23)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_ISP_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_ISP_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_ISP_RANGE                    23:23
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_ISP_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_ISP_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_ISP_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_ISP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_ISP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_ISP_INIT_ENUM                        DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_ISP_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_ISP_ENABLE                   _MK_ENUM_CONST(1)
+
+// Enable clock to USB controller
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_USBD_SHIFT                   _MK_SHIFT_CONST(22)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_USBD_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_USBD_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_USBD_RANGE                   22:22
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_USBD_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_USBD_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_USBD_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_USBD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_USBD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_USBD_INIT_ENUM                       DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_USBD_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_USBD_ENABLE                  _MK_ENUM_CONST(1)
+
+// Enable clock to 2D graphics engine.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_2D_SHIFT                     _MK_SHIFT_CONST(21)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_2D_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_2D_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_2D_RANGE                     21:21
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_2D_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_2D_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_2D_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_2D_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_2D_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_2D_INIT_ENUM                 DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_2D_DISABLE                   _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_2D_ENABLE                    _MK_ENUM_CONST(1)
+
+// Enable clock to VI controller.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_VI_SHIFT                     _MK_SHIFT_CONST(20)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_VI_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_VI_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_VI_RANGE                     20:20
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_VI_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_VI_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_VI_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_VI_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_VI_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_VI_INIT_ENUM                 DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_VI_DISABLE                   _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_VI_ENABLE                    _MK_ENUM_CONST(1)
+
+// Enable clock to EPP controller.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_EPP_SHIFT                    _MK_SHIFT_CONST(19)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_EPP_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_EPP_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_EPP_RANGE                    19:19
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_EPP_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_EPP_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_EPP_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_EPP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_EPP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_EPP_INIT_ENUM                        DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_EPP_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_EPP_ENABLE                   _MK_ENUM_CONST(1)
+
+// Enable clock to I2S 2 controller
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2S2_SHIFT                   _MK_SHIFT_CONST(18)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2S2_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2S2_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2S2_RANGE                   18:18
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2S2_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2S2_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2S2_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2S2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2S2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2S2_INIT_ENUM                       DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2S2_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2S2_ENABLE                  _MK_ENUM_CONST(1)
+
+// Enable clock to PWM (Pulse Width Modulator)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_PWM_SHIFT                    _MK_SHIFT_CONST(17)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_PWM_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_PWM_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_PWM_RANGE                    17:17
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_PWM_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_PWM_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_PWM_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_PWM_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_PWM_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_PWM_INIT_ENUM                        DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_PWM_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_PWM_ENABLE                   _MK_ENUM_CONST(1)
+
+// Enable clock to 3-Wire Interface Controller
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_TWC_SHIFT                    _MK_SHIFT_CONST(16)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_TWC_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_TWC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_TWC_RANGE                    16:16
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_TWC_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_TWC_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_TWC_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_TWC_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_TWC_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_TWC_INIT_ENUM                        DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_TWC_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_TWC_ENABLE                   _MK_ENUM_CONST(1)
+
+// Enable clock to HSMMC controller.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_HSMMC_SHIFT                  _MK_SHIFT_CONST(15)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_HSMMC_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_HSMMC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_HSMMC_RANGE                  15:15
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_HSMMC_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_HSMMC_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_HSMMC_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_HSMMC_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_HSMMC_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_HSMMC_INIT_ENUM                      DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_HSMMC_DISABLE                        _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_HSMMC_ENABLE                 _MK_ENUM_CONST(1)
+
+// Enable clock to SDIO1 controller.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDIO1_SHIFT                  _MK_SHIFT_CONST(14)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDIO1_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDIO1_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDIO1_RANGE                  14:14
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDIO1_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDIO1_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDIO1_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDIO1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDIO1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDIO1_INIT_ENUM                      DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDIO1_DISABLE                        _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDIO1_ENABLE                 _MK_ENUM_CONST(1)
+
+// Enable clock to NAND flash controller.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_NDFLASH_SHIFT                        _MK_SHIFT_CONST(13)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_NDFLASH_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_NDFLASH_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_NDFLASH_RANGE                        13:13
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_NDFLASH_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_NDFLASH_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_NDFLASH_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_NDFLASH_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_NDFLASH_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_NDFLASH_INIT_ENUM                    DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_NDFLASH_DISABLE                      _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_NDFLASH_ENABLE                       _MK_ENUM_CONST(1)
+
+// Enable clock to I2C1 Controller
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2C1_SHIFT                   _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2C1_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2C1_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2C1_RANGE                   12:12
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2C1_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2C1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2C1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2C1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2C1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2C1_INIT_ENUM                       DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2C1_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2C1_ENABLE                  _MK_ENUM_CONST(1)
+
+// Enable clock to I2S1 Controller
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2S1_SHIFT                   _MK_SHIFT_CONST(11)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2S1_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2S1_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2S1_RANGE                   11:11
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2S1_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2S1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2S1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2S1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2S1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2S1_INIT_ENUM                       DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2S1_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2S1_ENABLE                  _MK_ENUM_CONST(1)
+
+// Enable clock to SPDIF Controller
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SPDIF_SHIFT                  _MK_SHIFT_CONST(10)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SPDIF_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SPDIF_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SPDIF_RANGE                  10:10
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SPDIF_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SPDIF_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SPDIF_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SPDIF_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SPDIF_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SPDIF_INIT_ENUM                      DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SPDIF_DISABLE                        _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SPDIF_ENABLE                 _MK_ENUM_CONST(1)
+
+// Enable clock to SDIO2 controller.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDIO2_SHIFT                  _MK_SHIFT_CONST(9)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDIO2_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDIO2_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDIO2_RANGE                  9:9
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDIO2_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDIO2_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDIO2_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDIO2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDIO2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDIO2_INIT_ENUM                      DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDIO2_DISABLE                        _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDIO2_ENABLE                 _MK_ENUM_CONST(1)
+
+// Enable clock to GPIO Controller
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_GPIO_SHIFT                   _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_GPIO_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_GPIO_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_GPIO_RANGE                   8:8
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_GPIO_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_GPIO_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_GPIO_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_GPIO_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_GPIO_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_GPIO_INIT_ENUM                       ENABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_GPIO_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_GPIO_ENABLE                  _MK_ENUM_CONST(1)
+
+// Enable clock to UARTB/VFIR Controller
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_UARTB_SHIFT                  _MK_SHIFT_CONST(7)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_UARTB_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_UARTB_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_UARTB_RANGE                  7:7
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_UARTB_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_UARTB_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_UARTB_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_UARTB_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_UARTB_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_UARTB_INIT_ENUM                      DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_UARTB_DISABLE                        _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_UARTB_ENABLE                 _MK_ENUM_CONST(1)
+
+// Enable clock to UARTA Controller
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_UARTA_SHIFT                  _MK_SHIFT_CONST(6)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_UARTA_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_UARTA_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_UARTA_RANGE                  6:6
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_UARTA_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_UARTA_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_UARTA_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_UARTA_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_UARTA_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_UARTA_INIT_ENUM                      DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_UARTA_DISABLE                        _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_UARTA_ENABLE                 _MK_ENUM_CONST(1)
+
+// Enable clock to Timer Controller
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_TMR_SHIFT                    _MK_SHIFT_CONST(5)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_TMR_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_TMR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_TMR_RANGE                    5:5
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_TMR_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_TMR_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_TMR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_TMR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_TMR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_TMR_INIT_ENUM                        ENABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_TMR_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_TMR_ENABLE                   _MK_ENUM_CONST(1)
+
+// Enable clock to RTC Controller
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_RTC_SHIFT                    _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_RTC_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_RTC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_RTC_RANGE                    4:4
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_RTC_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_RTC_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_RTC_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_RTC_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_RTC_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_RTC_INIT_ENUM                        ENABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_RTC_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_RTC_ENABLE                   _MK_ENUM_CONST(1)
+
+// Enable clock to AC97 Controller
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_AC97_SHIFT                   _MK_SHIFT_CONST(3)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_AC97_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_AC97_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_AC97_RANGE                   3:3
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_AC97_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_AC97_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_AC97_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_AC97_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_AC97_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_AC97_INIT_ENUM                       DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_AC97_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_AC97_ENABLE                  _MK_ENUM_CONST(1)
+
+// Enable clock to CPU.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CPU_SHIFT                    _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CPU_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CPU_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CPU_RANGE                    0:0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CPU_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CPU_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CPU_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CPU_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CPU_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CPU_INIT_ENUM                        DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CPU_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CPU_ENABLE                   _MK_ENUM_CONST(1)
+
+
+// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0  
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0                      _MK_ADDR_CONST(0x14)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_WORD_COUNT                   0x1
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_RESET_VAL                    _MK_MASK_CONST(0x480)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_RESET_MASK                   _MK_MASK_CONST(0xf3fffff7)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_READ_MASK                    _MK_MASK_CONST(0xf3fffff7)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_WRITE_MASK                   _MK_MASK_CONST(0xf3fffff7)
+// Enable clock to BSEV Controller.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_BSEV_SHIFT                   _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_BSEV_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_BSEV_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_BSEV_RANGE                   31:31
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_BSEV_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_BSEV_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_BSEV_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_BSEV_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_BSEV_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_BSEV_INIT_ENUM                       DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_BSEV_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_BSEV_ENABLE                  _MK_ENUM_CONST(1)
+
+// Enable clock to BSEA Controller
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_BSEA_SHIFT                   _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_BSEA_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_BSEA_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_BSEA_RANGE                   30:30
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_BSEA_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_BSEA_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_BSEA_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_BSEA_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_BSEA_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_BSEA_INIT_ENUM                       DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_BSEA_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_BSEA_ENABLE                  _MK_ENUM_CONST(1)
+
+// Enable clock to VDE Controller
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_VDE_SHIFT                    _MK_SHIFT_CONST(29)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_VDE_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_VDE_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_VDE_RANGE                    29:29
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_VDE_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_VDE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_VDE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_VDE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_VDE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_VDE_INIT_ENUM                        DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_VDE_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_VDE_ENABLE                   _MK_ENUM_CONST(1)
+
+// Enable clock to MPE controller.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MPE_SHIFT                    _MK_SHIFT_CONST(28)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MPE_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MPE_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MPE_RANGE                    28:28
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MPE_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MPE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MPE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MPE_INIT_ENUM                        DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MPE_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MPE_ENABLE                   _MK_ENUM_CONST(1)
+
+// Enable clock to EMC controller.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_EMC_SHIFT                    _MK_SHIFT_CONST(25)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_EMC_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_EMC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_EMC_RANGE                    25:25
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_EMC_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_EMC_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_EMC_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_EMC_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_EMC_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_EMC_INIT_ENUM                        DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_EMC_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_EMC_ENABLE                   _MK_ENUM_CONST(1)
+
+// Enable clock to SPROM Controller
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SPROM_SHIFT                  _MK_SHIFT_CONST(24)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SPROM_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SPROM_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SPROM_RANGE                  24:24
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SPROM_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SPROM_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SPROM_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SPROM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SPROM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SPROM_INIT_ENUM                      DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SPROM_DISABLE                        _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SPROM_ENABLE                 _MK_ENUM_CONST(1)
+
+// Enable clock to UART-C Controller
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_UARTC_SHIFT                  _MK_SHIFT_CONST(23)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_UARTC_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_UARTC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_UARTC_RANGE                  23:23
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_UARTC_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_UARTC_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_UARTC_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_UARTC_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_UARTC_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_UARTC_INIT_ENUM                      DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_UARTC_DISABLE                        _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_UARTC_ENABLE                 _MK_ENUM_CONST(1)
+
+// Enable clock to I2C2 controller.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_I2C2_SHIFT                   _MK_SHIFT_CONST(22)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_I2C2_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_I2C2_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_I2C2_RANGE                   22:22
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_I2C2_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_I2C2_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_I2C2_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_I2C2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_I2C2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_I2C2_INIT_ENUM                       DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_I2C2_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_I2C2_ENABLE                  _MK_ENUM_CONST(1)
+
+// Enable clock to TVDAC controller.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_TVDAC_SHIFT                  _MK_SHIFT_CONST(21)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_TVDAC_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_TVDAC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_TVDAC_RANGE                  21:21
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_TVDAC_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_TVDAC_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_TVDAC_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_TVDAC_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_TVDAC_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_TVDAC_INIT_ENUM                      DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_TVDAC_DISABLE                        _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_TVDAC_ENABLE                 _MK_ENUM_CONST(1)
+
+// Enable clock to CSI controller
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_CSI_SHIFT                    _MK_SHIFT_CONST(20)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_CSI_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_CSI_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_CSI_RANGE                    20:20
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_CSI_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_CSI_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_CSI_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_CSI_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_CSI_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_CSI_INIT_ENUM                        DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_CSI_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_CSI_ENABLE                   _MK_ENUM_CONST(1)
+
+// Enable clock to HDMI
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_HDMI_SHIFT                   _MK_SHIFT_CONST(19)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_HDMI_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_HDMI_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_HDMI_RANGE                   19:19
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_HDMI_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_HDMI_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_HDMI_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_HDMI_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_HDMI_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_HDMI_INIT_ENUM                       DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_HDMI_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_HDMI_ENABLE                  _MK_ENUM_CONST(1)
+
+// Enable clock to MIPI base-band controller
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MIPI_SHIFT                   _MK_SHIFT_CONST(18)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MIPI_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MIPI_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MIPI_RANGE                   18:18
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MIPI_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MIPI_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MIPI_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MIPI_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MIPI_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MIPI_INIT_ENUM                       DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MIPI_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MIPI_ENABLE                  _MK_ENUM_CONST(1)
+
+// Enable clock to TVO/CVE controller
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_TVO_SHIFT                    _MK_SHIFT_CONST(17)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_TVO_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_TVO_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_TVO_RANGE                    17:17
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_TVO_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_TVO_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_TVO_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_TVO_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_TVO_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_TVO_INIT_ENUM                        DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_TVO_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_TVO_ENABLE                   _MK_ENUM_CONST(1)
+
+// Enable clock to DSI controller
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_DSI_SHIFT                    _MK_SHIFT_CONST(16)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_DSI_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_DSI_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_DSI_RANGE                    16:16
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_DSI_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_DSI_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_DSI_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_DSI_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_DSI_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_DSI_INIT_ENUM                        DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_DSI_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_DSI_ENABLE                   _MK_ENUM_CONST(1)
+
+// Enable clock to DVC-I2C Controller
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_DVC_I2C_SHIFT                        _MK_SHIFT_CONST(15)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_DVC_I2C_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_DVC_I2C_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_DVC_I2C_RANGE                        15:15
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_DVC_I2C_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_DVC_I2C_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_DVC_I2C_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_DVC_I2C_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_DVC_I2C_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_DVC_I2C_INIT_ENUM                    DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_DVC_I2C_DISABLE                      _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_DVC_I2C_ENABLE                       _MK_ENUM_CONST(1)
+
+// Enable clock to SBC 3 Controller.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC3_SHIFT                   _MK_SHIFT_CONST(14)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC3_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC3_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC3_RANGE                   14:14
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC3_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC3_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC3_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC3_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC3_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC3_INIT_ENUM                       DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC3_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC3_ENABLE                  _MK_ENUM_CONST(1)
+
+// Enable clock to XIO Controller.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_XIO_SHIFT                    _MK_SHIFT_CONST(13)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_XIO_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_XIO_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_XIO_RANGE                    13:13
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_XIO_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_XIO_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_XIO_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_XIO_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_XIO_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_XIO_INIT_ENUM                        DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_XIO_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_XIO_ENABLE                   _MK_ENUM_CONST(1)
+
+// Enable clock to SBC 2 Controller.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC2_SHIFT                   _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC2_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC2_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC2_RANGE                   12:12
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC2_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC2_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC2_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC2_INIT_ENUM                       DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC2_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC2_ENABLE                  _MK_ENUM_CONST(1)
+
+// Enable clock to SPI 1 Controller
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SPI1_SHIFT                   _MK_SHIFT_CONST(11)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SPI1_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SPI1_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SPI1_RANGE                   11:11
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SPI1_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SPI1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SPI1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SPI1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SPI1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SPI1_INIT_ENUM                       DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SPI1_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SPI1_ENABLE                  _MK_ENUM_CONST(1)
+
+// Enable clock to NOR Flash Controller.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_NOR_SHIFT                    _MK_SHIFT_CONST(10)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_NOR_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_NOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_NOR_RANGE                    10:10
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_NOR_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_NOR_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_NOR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_NOR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_NOR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_NOR_INIT_ENUM                        ENABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_NOR_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_NOR_ENABLE                   _MK_ENUM_CONST(1)
+
+// Enable clock to SBC 1 Controller.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC1_SHIFT                   _MK_SHIFT_CONST(9)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC1_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC1_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC1_RANGE                   9:9
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC1_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC1_INIT_ENUM                       DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC1_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC1_ENABLE                  _MK_ENUM_CONST(1)
+
+// Enable clock to Serial Link Controller
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SLC1_SHIFT                   _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SLC1_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SLC1_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SLC1_RANGE                   8:8
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SLC1_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SLC1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SLC1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SLC1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SLC1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SLC1_INIT_ENUM                       DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SLC1_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SLC1_ENABLE                  _MK_ENUM_CONST(1)
+
+// Enable clock to FUSE controller.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_FUSE_SHIFT                   _MK_SHIFT_CONST(7)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_FUSE_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_FUSE_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_FUSE_RANGE                   7:7
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_FUSE_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_FUSE_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_FUSE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_FUSE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_FUSE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_FUSE_INIT_ENUM                       ENABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_FUSE_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_FUSE_ENABLE                  _MK_ENUM_CONST(1)
+
+// Enable clock to PMC controller.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_PMC_SHIFT                    _MK_SHIFT_CONST(6)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_PMC_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_PMC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_PMC_RANGE                    6:6
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_PMC_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_PMC_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_PMC_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_PMC_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_PMC_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_PMC_INIT_ENUM                        DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_PMC_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_PMC_ENABLE                   _MK_ENUM_CONST(1)
+
+// Enable clock to statistic monitor.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_STAT_MON_SHIFT                       _MK_SHIFT_CONST(5)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_STAT_MON_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_STAT_MON_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_STAT_MON_RANGE                       5:5
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_STAT_MON_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_STAT_MON_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_STAT_MON_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_STAT_MON_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_STAT_MON_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_STAT_MON_INIT_ENUM                   DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_STAT_MON_DISABLE                     _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_STAT_MON_ENABLE                      _MK_ENUM_CONST(1)
+
+// Enable clock to keyboard controller.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_KBC_SHIFT                    _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_KBC_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_KBC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_KBC_RANGE                    4:4
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_KBC_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_KBC_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_KBC_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_KBC_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_KBC_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_KBC_INIT_ENUM                        DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_KBC_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_KBC_ENABLE                   _MK_ENUM_CONST(1)
+
+// Enable clock to APB-DMA.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_APBDMA_SHIFT                 _MK_SHIFT_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_APBDMA_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_APBDMA_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_APBDMA_RANGE                 2:2
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_APBDMA_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_APBDMA_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_APBDMA_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_APBDMA_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_APBDMA_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_APBDMA_INIT_ENUM                     DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_APBDMA_DISABLE                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_APBDMA_ENABLE                        _MK_ENUM_CONST(1)
+
+// Enable clock to AHB-DMA.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_AHBDMA_SHIFT                 _MK_SHIFT_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_AHBDMA_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_AHBDMA_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_AHBDMA_RANGE                 1:1
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_AHBDMA_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_AHBDMA_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_AHBDMA_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_AHBDMA_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_AHBDMA_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_AHBDMA_INIT_ENUM                     DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_AHBDMA_DISABLE                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_AHBDMA_ENABLE                        _MK_ENUM_CONST(1)
+
+// Enable clock to MC/EMC.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MEM_SHIFT                    _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MEM_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MEM_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MEM_RANGE                    0:0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MEM_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MEM_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MEM_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MEM_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MEM_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MEM_INIT_ENUM                        DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MEM_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MEM_ENABLE                   _MK_ENUM_CONST(1)
+
+
+// Reserved address 24 [0x18] 
+
+// Reserved address 28 [0x1c] 
+
+// Register CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0  
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0                  _MK_ADDR_CONST(0x20)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_WORD_COUNT                       0x1
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_RESET_VAL                        _MK_MASK_CONST(0x10000000)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_RESET_MASK                       _MK_MASK_CONST(0xff007777)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_READ_MASK                        _MK_MASK_CONST(0xff007777)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_WRITE_MASK                       _MK_MASK_CONST(0xff007777)
+// 0000=32KHz Clock source; 
+// 0001=IDLE Clock Source;
+// 001X=Run clock source; 
+// 01XX=IRQ Clock Source;
+// 1XXX=FIQ Clock Source
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_STATE_SHIFT                  _MK_SHIFT_CONST(28)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_STATE_FIELD                  (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_STATE_SHIFT)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_STATE_RANGE                  31:28
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_STATE_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_STATE_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_STATE_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_STATE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_STATE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_STATE_STDBY                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_STATE_IDLE                   _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_STATE_RUN                    _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_STATE_IRQ                    _MK_ENUM_CONST(4)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_STATE_FIQ                    _MK_ENUM_CONST(8)
+
+//  0 = NOP ; 1=Burst on COP FIQ
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_COP_AUTO_CWAKEUP_FROM_FIQ_SHIFT                  _MK_SHIFT_CONST(27)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_COP_AUTO_CWAKEUP_FROM_FIQ_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_COP_AUTO_CWAKEUP_FROM_FIQ_SHIFT)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_COP_AUTO_CWAKEUP_FROM_FIQ_RANGE                  27:27
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_COP_AUTO_CWAKEUP_FROM_FIQ_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_COP_AUTO_CWAKEUP_FROM_FIQ_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_COP_AUTO_CWAKEUP_FROM_FIQ_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_COP_AUTO_CWAKEUP_FROM_FIQ_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_COP_AUTO_CWAKEUP_FROM_FIQ_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  0 = NOP ; 1=Burst on CPU FIQ
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_AUTO_CWAKEUP_FROM_FIQ_SHIFT                  _MK_SHIFT_CONST(26)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_AUTO_CWAKEUP_FROM_FIQ_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_AUTO_CWAKEUP_FROM_FIQ_SHIFT)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_AUTO_CWAKEUP_FROM_FIQ_RANGE                  26:26
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_AUTO_CWAKEUP_FROM_FIQ_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_AUTO_CWAKEUP_FROM_FIQ_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_AUTO_CWAKEUP_FROM_FIQ_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_AUTO_CWAKEUP_FROM_FIQ_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_AUTO_CWAKEUP_FROM_FIQ_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  0 = NOP ; 1=Burst on COP IRQ
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_COP_AUTO_CWAKEUP_FROM_IRQ_SHIFT                  _MK_SHIFT_CONST(25)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_COP_AUTO_CWAKEUP_FROM_IRQ_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_COP_AUTO_CWAKEUP_FROM_IRQ_SHIFT)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_COP_AUTO_CWAKEUP_FROM_IRQ_RANGE                  25:25
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_COP_AUTO_CWAKEUP_FROM_IRQ_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_COP_AUTO_CWAKEUP_FROM_IRQ_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_COP_AUTO_CWAKEUP_FROM_IRQ_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_COP_AUTO_CWAKEUP_FROM_IRQ_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_COP_AUTO_CWAKEUP_FROM_IRQ_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  0 = NOP ; 1=Burst on CPU IRQ
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_AUTO_CWAKEUP_FROM_IRQ_SHIFT                  _MK_SHIFT_CONST(24)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_AUTO_CWAKEUP_FROM_IRQ_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_AUTO_CWAKEUP_FROM_IRQ_SHIFT)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_AUTO_CWAKEUP_FROM_IRQ_RANGE                  24:24
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_AUTO_CWAKEUP_FROM_IRQ_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_AUTO_CWAKEUP_FROM_IRQ_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_AUTO_CWAKEUP_FROM_IRQ_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_AUTO_CWAKEUP_FROM_IRQ_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_AUTO_CWAKEUP_FROM_IRQ_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  000 = clk_m,
+//  001 = pllC_out0,
+//  010 = clk_s,
+//  011 = pllM_out0,
+//  100 = pllP_out0,
+//  101 = pllP_out4,
+//  110 = pllP_out3,
+//  111 = clk_d,
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_FIQ_SOURCE_SHIFT                 _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_FIQ_SOURCE_FIELD                 (_MK_MASK_CONST(0x7) << CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_FIQ_SOURCE_SHIFT)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_FIQ_SOURCE_RANGE                 14:12
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_FIQ_SOURCE_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_FIQ_SOURCE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_FIQ_SOURCE_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_FIQ_SOURCE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_FIQ_SOURCE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_FIQ_SOURCE_CLKM                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_FIQ_SOURCE_PLLC_OUT0                     _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_FIQ_SOURCE_CLKS                  _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_FIQ_SOURCE_PLLM_OUT0                     _MK_ENUM_CONST(3)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_FIQ_SOURCE_PLLP_OUT0                     _MK_ENUM_CONST(4)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_FIQ_SOURCE_PLLP_OUT4                     _MK_ENUM_CONST(5)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_FIQ_SOURCE_PLLP_OUT3                     _MK_ENUM_CONST(6)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_FIQ_SOURCE_CLKD                  _MK_ENUM_CONST(7)
+
+//  Same definitions as CWAKEUP_FIQ_SOURCE
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IRQ_SOURCE_SHIFT                 _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IRQ_SOURCE_FIELD                 (_MK_MASK_CONST(0x7) << CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IRQ_SOURCE_SHIFT)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IRQ_SOURCE_RANGE                 10:8
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IRQ_SOURCE_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IRQ_SOURCE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IRQ_SOURCE_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IRQ_SOURCE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IRQ_SOURCE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IRQ_SOURCE_CLKM                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IRQ_SOURCE_PLLC_OUT0                     _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IRQ_SOURCE_CLKS                  _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IRQ_SOURCE_PLLM_OUT0                     _MK_ENUM_CONST(3)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IRQ_SOURCE_PLLP_OUT0                     _MK_ENUM_CONST(4)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IRQ_SOURCE_PLLP_OUT4                     _MK_ENUM_CONST(5)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IRQ_SOURCE_PLLP_OUT3                     _MK_ENUM_CONST(6)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IRQ_SOURCE_CLKD                  _MK_ENUM_CONST(7)
+
+//  Same definitions as CWAKEUP_FIQ_SOURCE
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_RUN_SOURCE_SHIFT                 _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_RUN_SOURCE_FIELD                 (_MK_MASK_CONST(0x7) << CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_RUN_SOURCE_SHIFT)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_RUN_SOURCE_RANGE                 6:4
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_RUN_SOURCE_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_RUN_SOURCE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_RUN_SOURCE_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_RUN_SOURCE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_RUN_SOURCE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_RUN_SOURCE_CLKM                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_RUN_SOURCE_PLLC_OUT0                     _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_RUN_SOURCE_CLKS                  _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_RUN_SOURCE_PLLM_OUT0                     _MK_ENUM_CONST(3)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_RUN_SOURCE_PLLP_OUT0                     _MK_ENUM_CONST(4)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_RUN_SOURCE_PLLP_OUT4                     _MK_ENUM_CONST(5)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_RUN_SOURCE_PLLP_OUT3                     _MK_ENUM_CONST(6)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_RUN_SOURCE_CLKD                  _MK_ENUM_CONST(7)
+
+//  Same definitions as CWAKEUP_FIQ_SOURCE
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IDLE_SOURCE_SHIFT                        _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IDLE_SOURCE_FIELD                        (_MK_MASK_CONST(0x7) << CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IDLE_SOURCE_SHIFT)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IDLE_SOURCE_RANGE                        2:0
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IDLE_SOURCE_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IDLE_SOURCE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IDLE_SOURCE_DEFAULT_MASK                 _MK_MASK_CONST(0x7)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IDLE_SOURCE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IDLE_SOURCE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IDLE_SOURCE_CLKM                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IDLE_SOURCE_PLLC_OUT0                    _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IDLE_SOURCE_CLKS                 _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IDLE_SOURCE_PLLM_OUT0                    _MK_ENUM_CONST(3)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IDLE_SOURCE_PLLP_OUT0                    _MK_ENUM_CONST(4)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IDLE_SOURCE_PLLP_OUT4                    _MK_ENUM_CONST(5)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IDLE_SOURCE_PLLP_OUT3                    _MK_ENUM_CONST(6)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IDLE_SOURCE_CLKD                 _MK_ENUM_CONST(7)
+
+
+// Register CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0  
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0                 _MK_ADDR_CONST(0x24)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_WORD_COUNT                      0x1
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_RESET_MASK                      _MK_MASK_CONST(0x8f00ffff)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_READ_MASK                       _MK_MASK_CONST(0x8f00ffff)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_WRITE_MASK                      _MK_MASK_CONST(0x8f00ffff)
+//  0 = disable divider.
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_ENB_SHIFT                    _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_ENB_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_ENB_SHIFT)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_ENB_RANGE                    31:31
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_ENB_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_ENB_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_ENB_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_ENB_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_ENB_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_ENB_INIT_ENUM                        DISABLE
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_ENB_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_ENB_ENABLE                   _MK_ENUM_CONST(1)
+
+//  0 = enable FIQ, disable FIQ.
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_COP_FIQ_SHIFT                       _MK_SHIFT_CONST(27)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_COP_FIQ_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_COP_FIQ_SHIFT)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_COP_FIQ_RANGE                       27:27
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_COP_FIQ_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_COP_FIQ_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_COP_FIQ_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_COP_FIQ_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_COP_FIQ_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+//  0 = enable FIQ, disable FIQ.
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_CPU_FIQ_SHIFT                       _MK_SHIFT_CONST(26)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_CPU_FIQ_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_CPU_FIQ_SHIFT)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_CPU_FIQ_RANGE                       26:26
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_CPU_FIQ_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_CPU_FIQ_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_CPU_FIQ_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_CPU_FIQ_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_CPU_FIQ_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+//  0 = enable IRQ, disable IRQ.
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_COP_IRQ_SHIFT                       _MK_SHIFT_CONST(25)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_COP_IRQ_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_COP_IRQ_SHIFT)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_COP_IRQ_RANGE                       25:25
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_COP_IRQ_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_COP_IRQ_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_COP_IRQ_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_COP_IRQ_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_COP_IRQ_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+//  0 = enable IRQ, disable IRQ.
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_CPU_IRQ_SHIFT                       _MK_SHIFT_CONST(24)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_CPU_IRQ_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_CPU_IRQ_SHIFT)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_CPU_IRQ_RANGE                       24:24
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_CPU_IRQ_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_CPU_IRQ_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_CPU_IRQ_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_CPU_IRQ_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_CPU_IRQ_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Actual value = n + 1.
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIVIDEND_SHIFT                       _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIVIDEND_FIELD                       (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIVIDEND_SHIFT)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIVIDEND_RANGE                       15:8
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIVIDEND_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIVIDEND_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIVIDEND_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIVIDEND_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIVIDEND_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Actual value = n + 1.
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIVISOR_SHIFT                        _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIVISOR_FIELD                        (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIVISOR_RANGE                        7:0
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIVISOR_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIVISOR_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIVISOR_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIVISOR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIVISOR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0  
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0                  _MK_ADDR_CONST(0x28)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_WORD_COUNT                       0x1
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_RESET_VAL                        _MK_MASK_CONST(0x10000000)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_RESET_MASK                       _MK_MASK_CONST(0xff007777)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_READ_MASK                        _MK_MASK_CONST(0xff007777)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_WRITE_MASK                       _MK_MASK_CONST(0xff007777)
+// 0000=32KHz Clock source; 
+// 0001=IDLE Clock Source;
+// 001X=Run clock source; 
+// 01XX=IRQ Clock Source;
+// 1XXX=FIQ Clock Source
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SYS_STATE_SHIFT                  _MK_SHIFT_CONST(28)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SYS_STATE_FIELD                  (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SYS_STATE_SHIFT)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SYS_STATE_RANGE                  31:28
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SYS_STATE_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SYS_STATE_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SYS_STATE_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SYS_STATE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SYS_STATE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SYS_STATE_STDBY                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SYS_STATE_IDLE                   _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SYS_STATE_RUN                    _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SYS_STATE_IRQ                    _MK_ENUM_CONST(4)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SYS_STATE_FIQ                    _MK_ENUM_CONST(8)
+
+//  0 = NOP ; 1=Burst on COP FIQ
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_COP_AUTO_SWAKEUP_FROM_FIQ_SHIFT                  _MK_SHIFT_CONST(27)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_COP_AUTO_SWAKEUP_FROM_FIQ_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_COP_AUTO_SWAKEUP_FROM_FIQ_SHIFT)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_COP_AUTO_SWAKEUP_FROM_FIQ_RANGE                  27:27
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_COP_AUTO_SWAKEUP_FROM_FIQ_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_COP_AUTO_SWAKEUP_FROM_FIQ_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_COP_AUTO_SWAKEUP_FROM_FIQ_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_COP_AUTO_SWAKEUP_FROM_FIQ_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_COP_AUTO_SWAKEUP_FROM_FIQ_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  0 = NOP ; 1=Burst on CPU FIQ
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_CPU_AUTO_SWAKEUP_FROM_FIQ_SHIFT                  _MK_SHIFT_CONST(26)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_CPU_AUTO_SWAKEUP_FROM_FIQ_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_CPU_AUTO_SWAKEUP_FROM_FIQ_SHIFT)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_CPU_AUTO_SWAKEUP_FROM_FIQ_RANGE                  26:26
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_CPU_AUTO_SWAKEUP_FROM_FIQ_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_CPU_AUTO_SWAKEUP_FROM_FIQ_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_CPU_AUTO_SWAKEUP_FROM_FIQ_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_CPU_AUTO_SWAKEUP_FROM_FIQ_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_CPU_AUTO_SWAKEUP_FROM_FIQ_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  0 = NOP ; 1=Burst on COP IRQ
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_COP_AUTO_SWAKEUP_FROM_IRQ_SHIFT                  _MK_SHIFT_CONST(25)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_COP_AUTO_SWAKEUP_FROM_IRQ_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_COP_AUTO_SWAKEUP_FROM_IRQ_SHIFT)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_COP_AUTO_SWAKEUP_FROM_IRQ_RANGE                  25:25
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_COP_AUTO_SWAKEUP_FROM_IRQ_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_COP_AUTO_SWAKEUP_FROM_IRQ_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_COP_AUTO_SWAKEUP_FROM_IRQ_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_COP_AUTO_SWAKEUP_FROM_IRQ_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_COP_AUTO_SWAKEUP_FROM_IRQ_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  0 = NOP ; 1=Burst on CPU IRQ
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_CPU_AUTO_SWAKEUP_FROM_IRQ_SHIFT                  _MK_SHIFT_CONST(24)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_CPU_AUTO_SWAKEUP_FROM_IRQ_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_CPU_AUTO_SWAKEUP_FROM_IRQ_SHIFT)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_CPU_AUTO_SWAKEUP_FROM_IRQ_RANGE                  24:24
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_CPU_AUTO_SWAKEUP_FROM_IRQ_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_CPU_AUTO_SWAKEUP_FROM_IRQ_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_CPU_AUTO_SWAKEUP_FROM_IRQ_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_CPU_AUTO_SWAKEUP_FROM_IRQ_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_CPU_AUTO_SWAKEUP_FROM_IRQ_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  000 = clk_m,
+//  001 = pllC_out1,
+//  010 = pllP_out4,
+//  011 = pllP_out3,
+//  100 = pllP_out2,
+//  101 = clk_d,
+//  110 = clk_s,
+//  111 = pllM_out1,
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_FIQ_SOURCE_SHIFT                 _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_FIQ_SOURCE_FIELD                 (_MK_MASK_CONST(0x7) << CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_FIQ_SOURCE_SHIFT)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_FIQ_SOURCE_RANGE                 14:12
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_FIQ_SOURCE_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_FIQ_SOURCE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_FIQ_SOURCE_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_FIQ_SOURCE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_FIQ_SOURCE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_FIQ_SOURCE_CLKM                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_FIQ_SOURCE_PLLC_OUT1                     _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_FIQ_SOURCE_PLLP_OUT4                     _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_FIQ_SOURCE_PLLP_OUT3                     _MK_ENUM_CONST(3)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_FIQ_SOURCE_PLLP_OUT2                     _MK_ENUM_CONST(4)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_FIQ_SOURCE_CLKD                  _MK_ENUM_CONST(5)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_FIQ_SOURCE_CLKS                  _MK_ENUM_CONST(6)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_FIQ_SOURCE_PLLM_OUT1                     _MK_ENUM_CONST(7)
+
+//  Same definitions as SWAKEUP_FIQ_SOURCE
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IRQ_SOURCE_SHIFT                 _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IRQ_SOURCE_FIELD                 (_MK_MASK_CONST(0x7) << CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IRQ_SOURCE_SHIFT)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IRQ_SOURCE_RANGE                 10:8
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IRQ_SOURCE_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IRQ_SOURCE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IRQ_SOURCE_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IRQ_SOURCE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IRQ_SOURCE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IRQ_SOURCE_CLKM                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IRQ_SOURCE_PLLC_OUT1                     _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IRQ_SOURCE_PLLP_OUT4                     _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IRQ_SOURCE_PLLP_OUT3                     _MK_ENUM_CONST(3)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IRQ_SOURCE_PLLP_OUT2                     _MK_ENUM_CONST(4)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IRQ_SOURCE_CLKD                  _MK_ENUM_CONST(5)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IRQ_SOURCE_CLKS                  _MK_ENUM_CONST(6)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IRQ_SOURCE_PLLM_OUT1                     _MK_ENUM_CONST(7)
+
+//  Same definitions as SWAKEUP_FIQ_SOURCE
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_RUN_SOURCE_SHIFT                 _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_RUN_SOURCE_FIELD                 (_MK_MASK_CONST(0x7) << CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_RUN_SOURCE_SHIFT)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_RUN_SOURCE_RANGE                 6:4
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_RUN_SOURCE_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_RUN_SOURCE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_RUN_SOURCE_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_RUN_SOURCE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_RUN_SOURCE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_RUN_SOURCE_CLKM                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_RUN_SOURCE_PLLC_OUT1                     _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_RUN_SOURCE_PLLP_OUT4                     _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_RUN_SOURCE_PLLP_OUT3                     _MK_ENUM_CONST(3)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_RUN_SOURCE_PLLP_OUT2                     _MK_ENUM_CONST(4)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_RUN_SOURCE_CLKD                  _MK_ENUM_CONST(5)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_RUN_SOURCE_CLKS                  _MK_ENUM_CONST(6)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_RUN_SOURCE_PLLM_OUT1                     _MK_ENUM_CONST(7)
+
+//  Same definitions as SWAKEUP_FIQ_SOURCE
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IDLE_SOURCE_SHIFT                        _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IDLE_SOURCE_FIELD                        (_MK_MASK_CONST(0x7) << CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IDLE_SOURCE_SHIFT)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IDLE_SOURCE_RANGE                        2:0
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IDLE_SOURCE_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IDLE_SOURCE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IDLE_SOURCE_DEFAULT_MASK                 _MK_MASK_CONST(0x7)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IDLE_SOURCE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IDLE_SOURCE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IDLE_SOURCE_CLKM                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IDLE_SOURCE_PLLC_OUT1                    _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IDLE_SOURCE_PLLP_OUT4                    _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IDLE_SOURCE_PLLP_OUT3                    _MK_ENUM_CONST(3)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IDLE_SOURCE_PLLP_OUT2                    _MK_ENUM_CONST(4)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IDLE_SOURCE_CLKD                 _MK_ENUM_CONST(5)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IDLE_SOURCE_CLKS                 _MK_ENUM_CONST(6)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IDLE_SOURCE_PLLM_OUT1                    _MK_ENUM_CONST(7)
+
+
+// Register CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0  
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0                 _MK_ADDR_CONST(0x2c)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_WORD_COUNT                      0x1
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_RESET_MASK                      _MK_MASK_CONST(0x8f00ffff)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_READ_MASK                       _MK_MASK_CONST(0x8f00ffff)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_WRITE_MASK                      _MK_MASK_CONST(0x8f00ffff)
+//  0 = disable divider.
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_ENB_SHIFT                    _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_ENB_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_ENB_SHIFT)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_ENB_RANGE                    31:31
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_ENB_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_ENB_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_ENB_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_ENB_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_ENB_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_ENB_INIT_ENUM                        DISABLE
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_ENB_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_ENB_ENABLE                   _MK_ENUM_CONST(1)
+
+//  0 = enable FIQ, disable FIQ.
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_COP_FIQ_SHIFT                       _MK_SHIFT_CONST(27)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_COP_FIQ_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_COP_FIQ_SHIFT)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_COP_FIQ_RANGE                       27:27
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_COP_FIQ_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_COP_FIQ_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_COP_FIQ_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_COP_FIQ_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_COP_FIQ_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+//  0 = enable FIQ, disable FIQ.
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_CPU_FIQ_SHIFT                       _MK_SHIFT_CONST(26)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_CPU_FIQ_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_CPU_FIQ_SHIFT)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_CPU_FIQ_RANGE                       26:26
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_CPU_FIQ_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_CPU_FIQ_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_CPU_FIQ_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_CPU_FIQ_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_CPU_FIQ_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+//  0 = enable IRQ, disable IRQ.
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_COP_IRQ_SHIFT                       _MK_SHIFT_CONST(25)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_COP_IRQ_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_COP_IRQ_SHIFT)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_COP_IRQ_RANGE                       25:25
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_COP_IRQ_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_COP_IRQ_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_COP_IRQ_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_COP_IRQ_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_COP_IRQ_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+//  0 = enable IRQ, disable IRQ.
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_CPU_IRQ_SHIFT                       _MK_SHIFT_CONST(24)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_CPU_IRQ_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_CPU_IRQ_SHIFT)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_CPU_IRQ_RANGE                       24:24
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_CPU_IRQ_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_CPU_IRQ_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_CPU_IRQ_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_CPU_IRQ_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_CPU_IRQ_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Actual value = n + 1.
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIVIDEND_SHIFT                       _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIVIDEND_FIELD                       (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIVIDEND_SHIFT)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIVIDEND_RANGE                       15:8
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIVIDEND_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIVIDEND_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIVIDEND_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIVIDEND_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIVIDEND_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Actual value = n + 1.
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIVISOR_SHIFT                        _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIVISOR_FIELD                        (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIVISOR_RANGE                        7:0
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIVISOR_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIVISOR_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIVISOR_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIVISOR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIVISOR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0  
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0                    _MK_ADDR_CONST(0x30)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_WORD_COUNT                         0x1
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_RESET_MASK                         _MK_MASK_CONST(0xf00f00bb)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_READ_MASK                  _MK_MASK_CONST(0xf00f00bb)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_WRITE_MASK                         _MK_MASK_CONST(0xf00f00bb)
+//  0 = Enable AUDIO SYNC CLK
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_SYNC_CLK_DIS_SHIFT                 _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_SYNC_CLK_DIS_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_SYNC_CLK_DIS_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_SYNC_CLK_DIS_RANGE                 31:31
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_SYNC_CLK_DIS_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_SYNC_CLK_DIS_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_SYNC_CLK_DIS_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_SYNC_CLK_DIS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_SYNC_CLK_DIS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// 000 = SPDIFIN recovered bit clock.
+// 001 = I2S1 bit clock.
+// 010 = I2S2 bit clock.
+// 011 = AC97 bit clock.
+// 100 = pllA_out0.
+// 101 = external audio clock (dap_mclk2).
+// 110 = external audio clock (dap_mclk1).
+// 111 = external vimclk (vimclk).
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_SYNC_CLK_RATE_SHIFT                        _MK_SHIFT_CONST(28)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_SYNC_CLK_RATE_FIELD                        (_MK_MASK_CONST(0x7) << CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_SYNC_CLK_RATE_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_SYNC_CLK_RATE_RANGE                        30:28
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_SYNC_CLK_RATE_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_SYNC_CLK_RATE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_SYNC_CLK_RATE_DEFAULT_MASK                 _MK_MASK_CONST(0x7)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_SYNC_CLK_RATE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_SYNC_CLK_RATE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_SYNC_CLK_RATE_SPDIFIN                      _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_SYNC_CLK_RATE_I2S1                 _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_SYNC_CLK_RATE_I2S2                 _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_SYNC_CLK_RATE_AC97                 _MK_ENUM_CONST(3)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_SYNC_CLK_RATE_PLLA_OUT0                    _MK_ENUM_CONST(4)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_SYNC_CLK_RATE_EXT_AUDIO_CLK2                       _MK_ENUM_CONST(5)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_SYNC_CLK_RATE_EXT_AUDIO_CLK1                       _MK_ENUM_CONST(6)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_SYNC_CLK_RATE_EXT_VIMCLK                   _MK_ENUM_CONST(7)
+
+// (n+1)/16 of SCLK.
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_VCLK_RATE_SHIFT                    _MK_SHIFT_CONST(16)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_VCLK_RATE_FIELD                    (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_VCLK_RATE_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_VCLK_RATE_RANGE                    19:16
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_VCLK_RATE_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_VCLK_RATE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_VCLK_RATE_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_VCLK_RATE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_VCLK_RATE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+//  0=enable HCLK, 1=disable HCLK.
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_HCLK_DIS_SHIFT                     _MK_SHIFT_CONST(7)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_HCLK_DIS_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_HCLK_DIS_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_HCLK_DIS_RANGE                     7:7
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_HCLK_DIS_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_HCLK_DIS_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_HCLK_DIS_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_HCLK_DIS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_HCLK_DIS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+//  1/(n+1) of SCLK.
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_AHB_RATE_SHIFT                     _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_AHB_RATE_FIELD                     (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_AHB_RATE_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_AHB_RATE_RANGE                     5:4
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_AHB_RATE_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_AHB_RATE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_AHB_RATE_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_AHB_RATE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_AHB_RATE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+//  0=enable PCLK, 1=disable PCLK.
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_PCLK_DIS_SHIFT                     _MK_SHIFT_CONST(3)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_PCLK_DIS_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_PCLK_DIS_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_PCLK_DIS_RANGE                     3:3
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_PCLK_DIS_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_PCLK_DIS_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_PCLK_DIS_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_PCLK_DIS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_PCLK_DIS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+//  1/(n+1) of HCLK.
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_APB_RATE_SHIFT                     _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_APB_RATE_FIELD                     (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_APB_RATE_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_APB_RATE_RANGE                     1:0
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_APB_RATE_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_APB_RATE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_APB_RATE_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_APB_RATE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_APB_RATE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_PROG_DLY_CLK_0  
+#define CLK_RST_CONTROLLER_PROG_DLY_CLK_0                       _MK_ADDR_CONST(0x34)
+#define CLK_RST_CONTROLLER_PROG_DLY_CLK_0_WORD_COUNT                    0x1
+#define CLK_RST_CONTROLLER_PROG_DLY_CLK_0_RESET_VAL                     _MK_MASK_CONST(0x7700)
+#define CLK_RST_CONTROLLER_PROG_DLY_CLK_0_RESET_MASK                    _MK_MASK_CONST(0xff00)
+#define CLK_RST_CONTROLLER_PROG_DLY_CLK_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PROG_DLY_CLK_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PROG_DLY_CLK_0_READ_MASK                     _MK_MASK_CONST(0xff00)
+#define CLK_RST_CONTROLLER_PROG_DLY_CLK_0_WRITE_MASK                    _MK_MASK_CONST(0xff00)
+// 16 Taps of selectable delay for CLK_M clk doubler
+#define CLK_RST_CONTROLLER_PROG_DLY_CLK_0_CLK_D_DELCLK_SEL_SHIFT                        _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_PROG_DLY_CLK_0_CLK_D_DELCLK_SEL_FIELD                        (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_PROG_DLY_CLK_0_CLK_D_DELCLK_SEL_SHIFT)
+#define CLK_RST_CONTROLLER_PROG_DLY_CLK_0_CLK_D_DELCLK_SEL_RANGE                        15:12
+#define CLK_RST_CONTROLLER_PROG_DLY_CLK_0_CLK_D_DELCLK_SEL_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_PROG_DLY_CLK_0_CLK_D_DELCLK_SEL_DEFAULT                      _MK_MASK_CONST(0x7)
+#define CLK_RST_CONTROLLER_PROG_DLY_CLK_0_CLK_D_DELCLK_SEL_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_PROG_DLY_CLK_0_CLK_D_DELCLK_SEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PROG_DLY_CLK_0_CLK_D_DELCLK_SEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// 16 Taps of selectable delay for SYNC_CLK clk doubler
+#define CLK_RST_CONTROLLER_PROG_DLY_CLK_0_SYNC_CLK_DELCLK_SEL_SHIFT                     _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_PROG_DLY_CLK_0_SYNC_CLK_DELCLK_SEL_FIELD                     (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_PROG_DLY_CLK_0_SYNC_CLK_DELCLK_SEL_SHIFT)
+#define CLK_RST_CONTROLLER_PROG_DLY_CLK_0_SYNC_CLK_DELCLK_SEL_RANGE                     11:8
+#define CLK_RST_CONTROLLER_PROG_DLY_CLK_0_SYNC_CLK_DELCLK_SEL_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_PROG_DLY_CLK_0_SYNC_CLK_DELCLK_SEL_DEFAULT                   _MK_MASK_CONST(0x7)
+#define CLK_RST_CONTROLLER_PROG_DLY_CLK_0_SYNC_CLK_DELCLK_SEL_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_PROG_DLY_CLK_0_SYNC_CLK_DELCLK_SEL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PROG_DLY_CLK_0_SYNC_CLK_DELCLK_SEL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Reserved address 56 [0x38] 
+
+// Reserved address 60 [0x3c] 
+
+// Register CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0  
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0                        _MK_ADDR_CONST(0x40)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_WORD_COUNT                     0x1
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_RESET_MASK                     _MK_MASK_CONST(0xff007777)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_READ_MASK                      _MK_MASK_CONST(0xff007777)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_WRITE_MASK                     _MK_MASK_CONST(0xff007777)
+// 0000=no skip.
+// 0001=skip base on IDLE Clock skip rate;
+// 001X=skip base on Run clock skip rate; 
+// 01XX=skip base on IRQ Clock skip rate;
+// 1XXX=skip base on FIQ Clock skip rate
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_STATE_SHIFT                       _MK_SHIFT_CONST(28)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_STATE_FIELD                       (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_STATE_SHIFT)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_STATE_RANGE                       31:28
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_STATE_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_STATE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_STATE_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_STATE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_STATE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+//  0 = NOP ; 1=Burst on COP FIQ
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_COP_FIQ_SHIFT                    _MK_SHIFT_CONST(27)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_COP_FIQ_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_COP_FIQ_SHIFT)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_COP_FIQ_RANGE                    27:27
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_COP_FIQ_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_COP_FIQ_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_COP_FIQ_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_COP_FIQ_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_COP_FIQ_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+//  0 = NOP ; 1=Burst on CPU FIQ
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_CPU_FIQ_SHIFT                    _MK_SHIFT_CONST(26)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_CPU_FIQ_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_CPU_FIQ_SHIFT)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_CPU_FIQ_RANGE                    26:26
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_CPU_FIQ_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_CPU_FIQ_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_CPU_FIQ_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_CPU_FIQ_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_CPU_FIQ_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+//  0 = NOP ; 1=Burst on COP IRQ
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_COP_IRQ_SHIFT                    _MK_SHIFT_CONST(25)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_COP_IRQ_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_COP_IRQ_SHIFT)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_COP_IRQ_RANGE                    25:25
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_COP_IRQ_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_COP_IRQ_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_COP_IRQ_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_COP_IRQ_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_COP_IRQ_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+//  0 = NOP ; 1=Burst on CPU IRQ
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_CPU_IRQ_SHIFT                    _MK_SHIFT_CONST(24)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_CPU_IRQ_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_CPU_IRQ_SHIFT)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_CPU_IRQ_RANGE                    24:24
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_CPU_IRQ_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_CPU_IRQ_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_CPU_IRQ_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_CPU_IRQ_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_CPU_IRQ_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+//  skip n/16 clock.
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_FIQ_SHIFT                    _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_FIQ_FIELD                    (_MK_MASK_CONST(0x7) << CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_FIQ_SHIFT)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_FIQ_RANGE                    14:12
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_FIQ_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_FIQ_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_FIQ_DEFAULT_MASK                     _MK_MASK_CONST(0x7)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_FIQ_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_FIQ_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+//  Same definitions as COP_CLK_SKIP_RATE_FIQ
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_IRQ_SHIFT                    _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_IRQ_FIELD                    (_MK_MASK_CONST(0x7) << CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_IRQ_SHIFT)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_IRQ_RANGE                    10:8
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_IRQ_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_IRQ_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_IRQ_DEFAULT_MASK                     _MK_MASK_CONST(0x7)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_IRQ_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_IRQ_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+//  Same definitions as COP_CLK_SKIP_RATE_FIQ
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_RUN_SHIFT                    _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_RUN_FIELD                    (_MK_MASK_CONST(0x7) << CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_RUN_SHIFT)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_RUN_RANGE                    6:4
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_RUN_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_RUN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_RUN_DEFAULT_MASK                     _MK_MASK_CONST(0x7)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_RUN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_RUN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+//  Same definitions as COP_CLK_SKIP_RATE_FIQ
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_IDLE_SHIFT                   _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_IDLE_FIELD                   (_MK_MASK_CONST(0x7) << CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_IDLE_SHIFT)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_IDLE_RANGE                   2:0
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_IDLE_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_IDLE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_IDLE_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_IDLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_IDLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_MASK_ARM_0  
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0                       _MK_ADDR_CONST(0x44)
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_WORD_COUNT                    0x1
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_RESET_MASK                    _MK_MASK_CONST(0x80010003)
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_READ_MASK                     _MK_MASK_CONST(0x80010003)
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_WRITE_MASK                    _MK_MASK_CONST(0x10003)
+//  1 = ARM11 AXI pipe is flushed.
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_AXI_FLUSH_DONE_SHIFT                  _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_AXI_FLUSH_DONE_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_MASK_ARM_0_AXI_FLUSH_DONE_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_AXI_FLUSH_DONE_RANGE                  31:31
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_AXI_FLUSH_DONE_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_AXI_FLUSH_DONE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_AXI_FLUSH_DONE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_AXI_FLUSH_DONE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_AXI_FLUSH_DONE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  1 = HW will stop clock to CPU when halt, 0 = no clock stop.
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_CLK_MASK_CPU_HALT_SHIFT                       _MK_SHIFT_CONST(16)
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_CLK_MASK_CPU_HALT_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_MASK_ARM_0_CLK_MASK_CPU_HALT_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_CLK_MASK_CPU_HALT_RANGE                       16:16
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_CLK_MASK_CPU_HALT_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_CLK_MASK_CPU_HALT_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_CLK_MASK_CPU_HALT_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_CLK_MASK_CPU_HALT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_CLK_MASK_CPU_HALT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+//  00 = no clock masking.
+//  01 = u2_nwait_r.
+//  10 = u2_nwait_r.
+//  11 = no clock masking.
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_CLK_MASK_COP_SHIFT                    _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_CLK_MASK_COP_FIELD                    (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_MASK_ARM_0_CLK_MASK_COP_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_CLK_MASK_COP_RANGE                    1:0
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_CLK_MASK_COP_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_CLK_MASK_COP_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_CLK_MASK_COP_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_CLK_MASK_COP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_CLK_MASK_COP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_MISC_CLK_ENB_0  
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0                       _MK_ADDR_CONST(0x48)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_WORD_COUNT                    0x1
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_RESET_VAL                     _MK_MASK_CONST(0x6003f)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_RESET_MASK                    _MK_MASK_CONST(0x1716003f)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_READ_MASK                     _MK_MASK_CONST(0x1716003f)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_WRITE_MASK                    _MK_MASK_CONST(0x1716003f)
+// 1 = VISIBLE, 0 = NOT VISIBLE.
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CFG_ALL_VISIBLE_SHIFT                 _MK_SHIFT_CONST(28)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CFG_ALL_VISIBLE_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CFG_ALL_VISIBLE_SHIFT)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CFG_ALL_VISIBLE_RANGE                 28:28
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CFG_ALL_VISIBLE_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CFG_ALL_VISIBLE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CFG_ALL_VISIBLE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CFG_ALL_VISIBLE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CFG_ALL_VISIBLE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// 1 = Enable clock to DEV1 pad.
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_DEV1_OUT_SHIFT                        _MK_SHIFT_CONST(26)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_DEV1_OUT_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_DEV1_OUT_SHIFT)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_DEV1_OUT_RANGE                        26:26
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_DEV1_OUT_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_DEV1_OUT_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_DEV1_OUT_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_DEV1_OUT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_DEV1_OUT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// 1 = Enable clock to DEV2 pad.
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_DEV2_OUT_SHIFT                        _MK_SHIFT_CONST(25)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_DEV2_OUT_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_DEV2_OUT_SHIFT)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_DEV2_OUT_RANGE                        25:25
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_DEV2_OUT_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_DEV2_OUT_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_DEV2_OUT_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_DEV2_OUT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_DEV2_OUT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// 1 = Enable clock to SUS pad.
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_SUS_OUT_SHIFT                 _MK_SHIFT_CONST(24)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_SUS_OUT_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_SUS_OUT_SHIFT)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_SUS_OUT_RANGE                 24:24
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_SUS_OUT_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_SUS_OUT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_SUS_OUT_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_SUS_OUT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_SUS_OUT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// 1 = wait for EMC to assert EMC clock divider request.
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_WAIT_FOR_EMC_CLKDIV_REQ_SHIFT                 _MK_SHIFT_CONST(20)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_WAIT_FOR_EMC_CLKDIV_REQ_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_MISC_CLK_ENB_0_WAIT_FOR_EMC_CLKDIV_REQ_SHIFT)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_WAIT_FOR_EMC_CLKDIV_REQ_RANGE                 20:20
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_WAIT_FOR_EMC_CLKDIV_REQ_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_WAIT_FOR_EMC_CLKDIV_REQ_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_WAIT_FOR_EMC_CLKDIV_REQ_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_WAIT_FOR_EMC_CLKDIV_REQ_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_WAIT_FOR_EMC_CLKDIV_REQ_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// 1 = Enable CLK_M clk doubler.
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_M_DOUBLER_ENB_SHIFT                       _MK_SHIFT_CONST(18)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_M_DOUBLER_ENB_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_M_DOUBLER_ENB_SHIFT)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_M_DOUBLER_ENB_RANGE                       18:18
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_M_DOUBLER_ENB_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_M_DOUBLER_ENB_DEFAULT                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_M_DOUBLER_ENB_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_M_DOUBLER_ENB_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_M_DOUBLER_ENB_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// 1 = Enable audio sync clk doubler.
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_SYNC_CLK_DOUBLER_ENB_SHIFT                    _MK_SHIFT_CONST(17)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_SYNC_CLK_DOUBLER_ENB_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_MISC_CLK_ENB_0_SYNC_CLK_DOUBLER_ENB_SHIFT)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_SYNC_CLK_DOUBLER_ENB_RANGE                    17:17
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_SYNC_CLK_DOUBLER_ENB_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_SYNC_CLK_DOUBLER_ENB_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_SYNC_CLK_DOUBLER_ENB_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_SYNC_CLK_DOUBLER_ENB_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_SYNC_CLK_DOUBLER_ENB_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// 1 = Enable COP cache ram clk.
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_CRAM2_SHIFT                   _MK_SHIFT_CONST(5)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_CRAM2_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_CRAM2_SHIFT)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_CRAM2_RANGE                   5:5
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_CRAM2_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_CRAM2_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_CRAM2_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_CRAM2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_CRAM2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// 1 = Enable CPU cache ram clk.
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_CRAM1_SHIFT                   _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_CRAM1_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_CRAM1_SHIFT)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_CRAM1_RANGE                   4:4
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_CRAM1_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_CRAM1_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_CRAM1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_CRAM1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_CRAM1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// 1 = Enable IRAMD clk.
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_IRAMD_SHIFT                   _MK_SHIFT_CONST(3)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_IRAMD_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_IRAMD_SHIFT)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_IRAMD_RANGE                   3:3
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_IRAMD_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_IRAMD_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_IRAMD_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_IRAMD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_IRAMD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// 1 = Enable IRAMD clk.
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_IRAMC_SHIFT                   _MK_SHIFT_CONST(2)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_IRAMC_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_IRAMC_SHIFT)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_IRAMC_RANGE                   2:2
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_IRAMC_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_IRAMC_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_IRAMC_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_IRAMC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_IRAMC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// 1 = Enable IRAMD clk.
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_IRAMB_SHIFT                   _MK_SHIFT_CONST(1)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_IRAMB_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_IRAMB_SHIFT)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_IRAMB_RANGE                   1:1
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_IRAMB_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_IRAMB_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_IRAMB_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_IRAMB_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_IRAMB_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// 1 = Enable IRAMD clk.
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_IRAMA_SHIFT                   _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_IRAMA_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_IRAMA_SHIFT)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_IRAMA_RANGE                   0:0
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_IRAMA_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_IRAMA_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_IRAMA_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_IRAMA_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_IRAMA_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Reserved address 76 [0x4c] 
+
+// Register CLK_RST_CONTROLLER_OSC_CTRL_0  
+#define CLK_RST_CONTROLLER_OSC_CTRL_0                   _MK_ADDR_CONST(0x50)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_WORD_COUNT                        0x1
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_RESET_VAL                         _MK_MASK_CONST(0x3f1)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_RESET_MASK                        _MK_MASK_CONST(0xfff1f3f3)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_READ_MASK                         _MK_MASK_CONST(0xfff1f3f3)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_WRITE_MASK                        _MK_MASK_CONST(0xfff1f3f3)
+// 00 = 13MHz, 01 = 19.2MHz, 10 = 12MHz, 11 = 26MHz.
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSC_FREQ_SHIFT                    _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSC_FREQ_FIELD                    (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_OSC_CTRL_0_OSC_FREQ_SHIFT)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSC_FREQ_RANGE                    31:30
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSC_FREQ_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSC_FREQ_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSC_FREQ_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSC_FREQ_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSC_FREQ_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// PLL reference clock divide.  00 = /1, 01 = /2, 10 = /4, 11 = reserve.
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_PLL_REF_DIV_SHIFT                 _MK_SHIFT_CONST(28)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_PLL_REF_DIV_FIELD                 (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_OSC_CTRL_0_PLL_REF_DIV_SHIFT)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_PLL_REF_DIV_RANGE                 29:28
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_PLL_REF_DIV_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_PLL_REF_DIV_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_PLL_REF_DIV_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_PLL_REF_DIV_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_PLL_REF_DIV_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Crystal oscillator spare register control.
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSCFI_SPARE_SHIFT                 _MK_SHIFT_CONST(20)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSCFI_SPARE_FIELD                 (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_OSC_CTRL_0_OSCFI_SPARE_SHIFT)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSCFI_SPARE_RANGE                 27:20
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSCFI_SPARE_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSCFI_SPARE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSCFI_SPARE_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSCFI_SPARE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSCFI_SPARE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Crystal oscillator duty cycle control.
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XODS_SHIFT                        _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XODS_FIELD                        (_MK_MASK_CONST(0x1f) << CLK_RST_CONTROLLER_OSC_CTRL_0_XODS_SHIFT)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XODS_RANGE                        16:12
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XODS_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XODS_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XODS_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XODS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XODS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Crystal oscillator drive strength control.
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOFS_SHIFT                        _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOFS_FIELD                        (_MK_MASK_CONST(0x3f) << CLK_RST_CONTROLLER_OSC_CTRL_0_XOFS_SHIFT)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOFS_RANGE                        9:4
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOFS_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOFS_DEFAULT                      _MK_MASK_CONST(0x3f)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOFS_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOFS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOFS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Crystal oscillator bypass enable (1 = enable bypass).
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOBP_SHIFT                        _MK_SHIFT_CONST(1)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOBP_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_OSC_CTRL_0_XOBP_SHIFT)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOBP_RANGE                        1:1
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOBP_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOBP_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOBP_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOBP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOBP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Crystal oscillator enable (1 = enable).
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOE_SHIFT                 _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOE_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_OSC_CTRL_0_XOE_SHIFT)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOE_RANGE                 0:0
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOE_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOE_DEFAULT                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_PLL_LFSR_0  
+#define CLK_RST_CONTROLLER_PLL_LFSR_0                   _MK_ADDR_CONST(0x54)
+#define CLK_RST_CONTROLLER_PLL_LFSR_0_WORD_COUNT                        0x1
+#define CLK_RST_CONTROLLER_PLL_LFSR_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLL_LFSR_0_RESET_MASK                        _MK_MASK_CONST(0xffff)
+#define CLK_RST_CONTROLLER_PLL_LFSR_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLL_LFSR_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLL_LFSR_0_READ_MASK                         _MK_MASK_CONST(0xffff)
+#define CLK_RST_CONTROLLER_PLL_LFSR_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+// Random number generated from PLL linear feedback shift register.
+#define CLK_RST_CONTROLLER_PLL_LFSR_0_RND_SHIFT                 _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_PLL_LFSR_0_RND_FIELD                 (_MK_MASK_CONST(0xffff) << CLK_RST_CONTROLLER_PLL_LFSR_0_RND_SHIFT)
+#define CLK_RST_CONTROLLER_PLL_LFSR_0_RND_RANGE                 15:0
+#define CLK_RST_CONTROLLER_PLL_LFSR_0_RND_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_PLL_LFSR_0_RND_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLL_LFSR_0_RND_DEFAULT_MASK                  _MK_MASK_CONST(0xffff)
+#define CLK_RST_CONTROLLER_PLL_LFSR_0_RND_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLL_LFSR_0_RND_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_OSC_FREQ_DET_0  
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0                       _MK_ADDR_CONST(0x58)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_WORD_COUNT                    0x1
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_RESET_MASK                    _MK_MASK_CONST(0x8000000f)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_READ_MASK                     _MK_MASK_CONST(0x8000000f)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_WRITE_MASK                    _MK_MASK_CONST(0x8000000f)
+// 0 = default, 1 = enable osc frequency detect. 
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_OSC_FREQ_DET_TRIG_SHIFT                       _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_OSC_FREQ_DET_TRIG_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_OSC_FREQ_DET_0_OSC_FREQ_DET_TRIG_SHIFT)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_OSC_FREQ_DET_TRIG_RANGE                       31:31
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_OSC_FREQ_DET_TRIG_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_OSC_FREQ_DET_TRIG_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_OSC_FREQ_DET_TRIG_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_OSC_FREQ_DET_TRIG_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_OSC_FREQ_DET_TRIG_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_OSC_FREQ_DET_TRIG_INIT_ENUM                   DISABLE
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_OSC_FREQ_DET_TRIG_DISABLE                     _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_OSC_FREQ_DET_TRIG_ENABLE                      _MK_ENUM_CONST(1)
+
+// Indicate the # of 32KHz clock period as window in n+1 scheme.
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_REF_CLK_WIN_CFG_SHIFT                 _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_REF_CLK_WIN_CFG_FIELD                 (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_OSC_FREQ_DET_0_REF_CLK_WIN_CFG_SHIFT)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_REF_CLK_WIN_CFG_RANGE                 3:0
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_REF_CLK_WIN_CFG_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_REF_CLK_WIN_CFG_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_REF_CLK_WIN_CFG_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_REF_CLK_WIN_CFG_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_REF_CLK_WIN_CFG_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0  
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0                        _MK_ADDR_CONST(0x5c)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_WORD_COUNT                     0x1
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_RESET_MASK                     _MK_MASK_CONST(0x8000ffff)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_READ_MASK                      _MK_MASK_CONST(0x8000ffff)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
+// 0 = not busy, 1 = busy.
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_OSC_FREQ_DET_BUSY_SHIFT                        _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_OSC_FREQ_DET_BUSY_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_OSC_FREQ_DET_BUSY_SHIFT)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_OSC_FREQ_DET_BUSY_RANGE                        31:31
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_OSC_FREQ_DET_BUSY_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_OSC_FREQ_DET_BUSY_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_OSC_FREQ_DET_BUSY_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_OSC_FREQ_DET_BUSY_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_OSC_FREQ_DET_BUSY_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// indicate the number of osc count within the 32KHz clock reference window.
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_OSC_FREQ_DET_CNT_SHIFT                 _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_OSC_FREQ_DET_CNT_FIELD                 (_MK_MASK_CONST(0xffff) << CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_OSC_FREQ_DET_CNT_SHIFT)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_OSC_FREQ_DET_CNT_RANGE                 15:0
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_OSC_FREQ_DET_CNT_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_OSC_FREQ_DET_CNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_OSC_FREQ_DET_CNT_DEFAULT_MASK                  _MK_MASK_CONST(0xffff)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_OSC_FREQ_DET_CNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_OSC_FREQ_DET_CNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Reserved address 96 [0x60] 
+
+// Reserved address 100 [0x64] 
+
+// Reserved address 104 [0x68] 
+
+// Reserved address 108 [0x6c] 
+
+// Register CLK_RST_CONTROLLER_BOND_OUT_L_0  
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0                 _MK_ADDR_CONST(0x70)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_WORD_COUNT                      0x1
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_RESET_MASK                      _MK_MASK_CONST(0xfffffff9)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_READ_MASK                       _MK_MASK_CONST(0xfffffff9)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_WRITE_MASK                      _MK_MASK_CONST(0xfffffff9)
+// Bond out COP cache controller.
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_CACHE2_SHIFT                   _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_CACHE2_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_CACHE2_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_CACHE2_RANGE                   31:31
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_CACHE2_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_CACHE2_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_CACHE2_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_CACHE2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_CACHE2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Bond out CPU cache controller.
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_CACHE1_SHIFT                   _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_CACHE1_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_CACHE1_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_CACHE1_RANGE                   30:30
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_CACHE1_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_CACHE1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_CACHE1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_CACHE1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_CACHE1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Bond out vector co-processor.
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_VCP_SHIFT                      _MK_SHIFT_CONST(29)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_VCP_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_VCP_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_VCP_RANGE                      29:29
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_VCP_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_VCP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_VCP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_VCP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_VCP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Bond out HOST1X.
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_HOST1X_SHIFT                   _MK_SHIFT_CONST(28)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_HOST1X_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_HOST1X_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_HOST1X_RANGE                   28:28
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_HOST1X_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_HOST1X_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_HOST1X_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_HOST1X_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_HOST1X_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Bond out DISP1 controller.
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_DISP1_SHIFT                    _MK_SHIFT_CONST(27)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_DISP1_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_DISP1_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_DISP1_RANGE                    27:27
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_DISP1_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_DISP1_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_DISP1_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_DISP1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_DISP1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Bond out DISP2 controller.
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_DISP2_SHIFT                    _MK_SHIFT_CONST(26)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_DISP2_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_DISP2_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_DISP2_RANGE                    26:26
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_DISP2_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_DISP2_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_DISP2_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_DISP2_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_DISP2_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Bond out IDE controller
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_IDE_SHIFT                      _MK_SHIFT_CONST(25)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_IDE_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_IDE_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_IDE_RANGE                      25:25
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_IDE_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_IDE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_IDE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_IDE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_IDE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Bond out 3D controller.
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_3D_SHIFT                       _MK_SHIFT_CONST(24)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_3D_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_3D_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_3D_RANGE                       24:24
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_3D_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_3D_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_3D_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_3D_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_3D_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Bond out ISP controller.
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_ISP_SHIFT                      _MK_SHIFT_CONST(23)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_ISP_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_ISP_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_ISP_RANGE                      23:23
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_ISP_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_ISP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_ISP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_ISP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_ISP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Bond out USB controller
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_USBD_SHIFT                     _MK_SHIFT_CONST(22)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_USBD_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_USBD_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_USBD_RANGE                     22:22
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_USBD_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_USBD_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_USBD_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_USBD_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_USBD_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Bond out 2D graphics engine.
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_2D_SHIFT                       _MK_SHIFT_CONST(21)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_2D_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_2D_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_2D_RANGE                       21:21
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_2D_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_2D_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_2D_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_2D_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_2D_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Bond out VI controller.
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_VI_SHIFT                       _MK_SHIFT_CONST(20)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_VI_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_VI_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_VI_RANGE                       20:20
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_VI_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_VI_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_VI_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_VI_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_VI_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Bond out EPP controller.
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_EPP_SHIFT                      _MK_SHIFT_CONST(19)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_EPP_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_EPP_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_EPP_RANGE                      19:19
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_EPP_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_EPP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_EPP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_EPP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_EPP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Bond out I2S 2 controller
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_I2S2_SHIFT                     _MK_SHIFT_CONST(18)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_I2S2_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_I2S2_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_I2S2_RANGE                     18:18
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_I2S2_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_I2S2_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_I2S2_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_I2S2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_I2S2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Bond out PWM (Pulse Width Modulator)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_PWM_SHIFT                      _MK_SHIFT_CONST(17)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_PWM_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_PWM_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_PWM_RANGE                      17:17
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_PWM_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_PWM_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_PWM_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_PWM_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_PWM_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Bond out 3-Wire Interface Controller
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_TWC_SHIFT                      _MK_SHIFT_CONST(16)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_TWC_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_TWC_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_TWC_RANGE                      16:16
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_TWC_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_TWC_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_TWC_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_TWC_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_TWC_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Bond out HSMMC controller.
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_HSMMC_SHIFT                    _MK_SHIFT_CONST(15)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_HSMMC_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_HSMMC_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_HSMMC_RANGE                    15:15
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_HSMMC_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_HSMMC_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_HSMMC_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_HSMMC_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_HSMMC_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Bond out SDIO1 controller.
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SDIO1_SHIFT                    _MK_SHIFT_CONST(14)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SDIO1_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SDIO1_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SDIO1_RANGE                    14:14
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SDIO1_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SDIO1_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SDIO1_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SDIO1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SDIO1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Bond out NAND flash controller.
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_NDFLASH_SHIFT                  _MK_SHIFT_CONST(13)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_NDFLASH_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_NDFLASH_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_NDFLASH_RANGE                  13:13
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_NDFLASH_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_NDFLASH_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_NDFLASH_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_NDFLASH_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_NDFLASH_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Bond out I2C1 Controller
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_I2C1_SHIFT                     _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_I2C1_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_I2C1_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_I2C1_RANGE                     12:12
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_I2C1_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_I2C1_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_I2C1_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_I2C1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_I2C1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Bond out I2S1 Controller
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_I2S1_SHIFT                     _MK_SHIFT_CONST(11)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_I2S1_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_I2S1_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_I2S1_RANGE                     11:11
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_I2S1_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_I2S1_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_I2S1_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_I2S1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_I2S1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Bond out SPDIF Controller
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SPDIF_SHIFT                    _MK_SHIFT_CONST(10)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SPDIF_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SPDIF_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SPDIF_RANGE                    10:10
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SPDIF_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SPDIF_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SPDIF_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SPDIF_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SPDIF_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Bond out SDIO2 controller.
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SDIO2_SHIFT                    _MK_SHIFT_CONST(9)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SDIO2_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SDIO2_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SDIO2_RANGE                    9:9
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SDIO2_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SDIO2_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SDIO2_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SDIO2_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SDIO2_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Bond out GPIO Controller
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_GPIO_SHIFT                     _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_GPIO_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_GPIO_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_GPIO_RANGE                     8:8
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_GPIO_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_GPIO_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_GPIO_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_GPIO_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_GPIO_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Bond out UARTB/VFIR Controller
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_UARTB_SHIFT                    _MK_SHIFT_CONST(7)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_UARTB_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_UARTB_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_UARTB_RANGE                    7:7
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_UARTB_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_UARTB_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_UARTB_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_UARTB_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_UARTB_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Bond out UARTA Controller
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_UARTA_SHIFT                    _MK_SHIFT_CONST(6)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_UARTA_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_UARTA_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_UARTA_RANGE                    6:6
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_UARTA_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_UARTA_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_UARTA_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_UARTA_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_UARTA_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Bond out Timer Controller
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_TMR_SHIFT                      _MK_SHIFT_CONST(5)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_TMR_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_TMR_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_TMR_RANGE                      5:5
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_TMR_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_TMR_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_TMR_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_TMR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_TMR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Bond out RTC Controller
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_RTC_SHIFT                      _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_RTC_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_RTC_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_RTC_RANGE                      4:4
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_RTC_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_RTC_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_RTC_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_RTC_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_RTC_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Bond out AC97 Controller
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_AC97_SHIFT                     _MK_SHIFT_CONST(3)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_AC97_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_AC97_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_AC97_RANGE                     3:3
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_AC97_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_AC97_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_AC97_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_AC97_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_AC97_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Bond out CPU.
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_CPU_SHIFT                      _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_CPU_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_CPU_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_CPU_RANGE                      0:0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_CPU_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_CPU_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_CPU_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_CPU_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_CPU_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_BOND_OUT_H_0  
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0                 _MK_ADDR_CONST(0x74)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_WORD_COUNT                      0x1
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_RESET_MASK                      _MK_MASK_CONST(0xf3fffff7)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_READ_MASK                       _MK_MASK_CONST(0xf3fffff7)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_WRITE_MASK                      _MK_MASK_CONST(0xf3fffff7)
+// Bond out BSEV Controller.
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_BSEV_SHIFT                     _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_BSEV_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_BSEV_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_BSEV_RANGE                     31:31
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_BSEV_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_BSEV_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_BSEV_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_BSEV_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_BSEV_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Bond out BSEA Controller
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_BSEA_SHIFT                     _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_BSEA_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_BSEA_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_BSEA_RANGE                     30:30
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_BSEA_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_BSEA_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_BSEA_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_BSEA_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_BSEA_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Bond out VDE Controller
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_VDE_SHIFT                      _MK_SHIFT_CONST(29)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_VDE_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_VDE_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_VDE_RANGE                      29:29
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_VDE_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_VDE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_VDE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_VDE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_VDE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Bond out MPE controller.
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_MPE_SHIFT                      _MK_SHIFT_CONST(28)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_MPE_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_MPE_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_MPE_RANGE                      28:28
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_MPE_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_MPE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_MPE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_MPE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_MPE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Bond out EMC controller.
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_EMC_SHIFT                      _MK_SHIFT_CONST(25)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_EMC_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_EMC_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_EMC_RANGE                      25:25
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_EMC_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_EMC_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_EMC_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_EMC_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_EMC_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Bond out SPROM Controller
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SPROM_SHIFT                    _MK_SHIFT_CONST(24)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SPROM_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SPROM_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SPROM_RANGE                    24:24
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SPROM_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SPROM_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SPROM_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SPROM_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SPROM_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Bond out UART-C Controller
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_UARTC_SHIFT                    _MK_SHIFT_CONST(23)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_UARTC_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_UARTC_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_UARTC_RANGE                    23:23
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_UARTC_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_UARTC_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_UARTC_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_UARTC_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_UARTC_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Bond out I2C2 controller.
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_I2C2_SHIFT                     _MK_SHIFT_CONST(22)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_I2C2_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_I2C2_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_I2C2_RANGE                     22:22
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_I2C2_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_I2C2_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_I2C2_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_I2C2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_I2C2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Bond out TVDAC controller.
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_TVDAC_SHIFT                    _MK_SHIFT_CONST(21)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_TVDAC_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_TVDAC_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_TVDAC_RANGE                    21:21
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_TVDAC_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_TVDAC_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_TVDAC_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_TVDAC_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_TVDAC_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Bond out CSI controller
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_CSI_SHIFT                      _MK_SHIFT_CONST(20)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_CSI_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_CSI_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_CSI_RANGE                      20:20
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_CSI_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_CSI_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_CSI_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_CSI_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_CSI_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Bond out HDMI
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_HDMI_SHIFT                     _MK_SHIFT_CONST(19)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_HDMI_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_HDMI_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_HDMI_RANGE                     19:19
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_HDMI_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_HDMI_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_HDMI_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_HDMI_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_HDMI_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Bond out MIPI base-band controller
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_MIPI_SHIFT                     _MK_SHIFT_CONST(18)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_MIPI_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_MIPI_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_MIPI_RANGE                     18:18
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_MIPI_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_MIPI_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_MIPI_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_MIPI_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_MIPI_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Bond out TVO/CVE controller
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_TVO_SHIFT                      _MK_SHIFT_CONST(17)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_TVO_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_TVO_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_TVO_RANGE                      17:17
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_TVO_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_TVO_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_TVO_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_TVO_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_TVO_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Bond out DSI controller
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_DSI_SHIFT                      _MK_SHIFT_CONST(16)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_DSI_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_DSI_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_DSI_RANGE                      16:16
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_DSI_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_DSI_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_DSI_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_DSI_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_DSI_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Bond out DVC-I2C Controller
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_DVC_I2C_SHIFT                  _MK_SHIFT_CONST(15)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_DVC_I2C_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_DVC_I2C_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_DVC_I2C_RANGE                  15:15
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_DVC_I2C_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_DVC_I2C_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_DVC_I2C_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_DVC_I2C_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_DVC_I2C_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Bond out SBC 3 Controller.
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SBC3_SHIFT                     _MK_SHIFT_CONST(14)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SBC3_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SBC3_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SBC3_RANGE                     14:14
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SBC3_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SBC3_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SBC3_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SBC3_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SBC3_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Bond out XIO Controller.
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_XIO_SHIFT                      _MK_SHIFT_CONST(13)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_XIO_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_XIO_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_XIO_RANGE                      13:13
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_XIO_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_XIO_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_XIO_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_XIO_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_XIO_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Bond out SBC 2 Controller.
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SBC2_SHIFT                     _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SBC2_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SBC2_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SBC2_RANGE                     12:12
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SBC2_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SBC2_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SBC2_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SBC2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SBC2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Bond out SPI 1 Controller
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SPI1_SHIFT                     _MK_SHIFT_CONST(11)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SPI1_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SPI1_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SPI1_RANGE                     11:11
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SPI1_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SPI1_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SPI1_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SPI1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SPI1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Bond out NOR Flash Controller.
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_NOR_SHIFT                      _MK_SHIFT_CONST(10)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_NOR_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_NOR_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_NOR_RANGE                      10:10
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_NOR_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_NOR_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_NOR_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_NOR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_NOR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Bond out SBC 1 Controller.
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SBC1_SHIFT                     _MK_SHIFT_CONST(9)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SBC1_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SBC1_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SBC1_RANGE                     9:9
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SBC1_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SBC1_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SBC1_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SBC1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SBC1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Bond out Serial Link Controller
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SLC1_SHIFT                     _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SLC1_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SLC1_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SLC1_RANGE                     8:8
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SLC1_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SLC1_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SLC1_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SLC1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SLC1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Bond out FUSE controller.
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_FUSE_SHIFT                     _MK_SHIFT_CONST(7)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_FUSE_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_FUSE_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_FUSE_RANGE                     7:7
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_FUSE_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_FUSE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_FUSE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_FUSE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_FUSE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Bond out PMC controller.
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_PMC_SHIFT                      _MK_SHIFT_CONST(6)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_PMC_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_PMC_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_PMC_RANGE                      6:6
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_PMC_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_PMC_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_PMC_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_PMC_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_PMC_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Bond out statistic monitor.
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_STAT_MON_SHIFT                 _MK_SHIFT_CONST(5)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_STAT_MON_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_STAT_MON_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_STAT_MON_RANGE                 5:5
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_STAT_MON_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_STAT_MON_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_STAT_MON_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_STAT_MON_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_STAT_MON_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Bond out keyboard controller.
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_KBC_SHIFT                      _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_KBC_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_KBC_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_KBC_RANGE                      4:4
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_KBC_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_KBC_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_KBC_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_KBC_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_KBC_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Bond out APB-DMA.
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_APBDMA_SHIFT                   _MK_SHIFT_CONST(2)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_APBDMA_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_APBDMA_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_APBDMA_RANGE                   2:2
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_APBDMA_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_APBDMA_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_APBDMA_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_APBDMA_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_APBDMA_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Bond out AHB-DMA.
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_AHBDMA_SHIFT                   _MK_SHIFT_CONST(1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_AHBDMA_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_AHBDMA_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_AHBDMA_RANGE                   1:1
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_AHBDMA_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_AHBDMA_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_AHBDMA_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_AHBDMA_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_AHBDMA_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Bond out MC/EMC.
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_MEM_SHIFT                      _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_MEM_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_MEM_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_MEM_RANGE                      0:0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_MEM_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_MEM_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_MEM_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_MEM_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_MEM_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Reserved address 120 [0x78] 
+
+// Reserved address 124 [0x7c] 
+
+// Register CLK_RST_CONTROLLER_PLLC_BASE_0  
+#define CLK_RST_CONTROLLER_PLLC_BASE_0                  _MK_ADDR_CONST(0x80)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_WORD_COUNT                       0x1
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_RESET_VAL                        _MK_MASK_CONST(0x10c)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_RESET_MASK                       _MK_MASK_CONST(0xe873ff1f)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_READ_MASK                        _MK_MASK_CONST(0xe873ff1f)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_WRITE_MASK                       _MK_MASK_CONST(0xe073ff1f)
+//  0 = no bypass, 1 = bypass.
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_BYPASS_SHIFT                        _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_BYPASS_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_BYPASS_SHIFT)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_BYPASS_RANGE                        31:31
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_BYPASS_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_BYPASS_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_BYPASS_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_BYPASS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_BYPASS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_BYPASS_INIT_ENUM                    DISABLE
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_BYPASS_DISABLE                      _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_BYPASS_ENABLE                       _MK_ENUM_CONST(1)
+
+//  0 = disable, 1 = enable.
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_ENABLE_SHIFT                        _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_ENABLE_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_ENABLE_SHIFT)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_ENABLE_RANGE                        30:30
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_ENABLE_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_ENABLE_INIT_ENUM                    DISABLE
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_ENABLE_DISABLE                      _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_ENABLE_ENABLE                       _MK_ENUM_CONST(1)
+
+//  0 = enable reference clk, 1 = disable reference clk.
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_REF_DIS_SHIFT                       _MK_SHIFT_CONST(29)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_REF_DIS_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_REF_DIS_SHIFT)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_REF_DIS_RANGE                       29:29
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_REF_DIS_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_REF_DIS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_REF_DIS_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_REF_DIS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_REF_DIS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_REF_DIS_INIT_ENUM                   REF_ENABLE
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_REF_DIS_REF_ENABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_REF_DIS_REF_DISABLE                 _MK_ENUM_CONST(1)
+
+//  0 = not lock, 1 = lock.
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_LOCK_SHIFT                  _MK_SHIFT_CONST(27)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_LOCK_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_LOCK_SHIFT)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_LOCK_RANGE                  27:27
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_LOCK_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_LOCK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_LOCK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_LOCK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_LOCK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  0 = post divider (2^n).
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVP_SHIFT                  _MK_SHIFT_CONST(20)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVP_FIELD                  (_MK_MASK_CONST(0x7) << CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVP_SHIFT)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVP_RANGE                  22:20
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVP_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVP_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVP_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  PLL feedback divider.
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVN_SHIFT                  _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVN_FIELD                  (_MK_MASK_CONST(0x3ff) << CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVN_SHIFT)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVN_RANGE                  17:8
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVN_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVN_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVN_DEFAULT_MASK                   _MK_MASK_CONST(0x3ff)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  PLL input divider.
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVM_SHIFT                  _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVM_FIELD                  (_MK_MASK_CONST(0x1f) << CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVM_SHIFT)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVM_RANGE                  4:0
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVM_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVM_DEFAULT                        _MK_MASK_CONST(0xc)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVM_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_PLLC_OUT_0  
+#define CLK_RST_CONTROLLER_PLLC_OUT_0                   _MK_ADDR_CONST(0x84)
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_WORD_COUNT                        0x1
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_RESET_VAL                         _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_RESET_MASK                        _MK_MASK_CONST(0xff03)
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_READ_MASK                         _MK_MASK_CONST(0xff03)
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_WRITE_MASK                        _MK_MASK_CONST(0xff03)
+//  PLLC_OUT1 divider from base PLLC (lsb denote 0.5x).
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_RATIO_SHIFT                     _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_RATIO_FIELD                     (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_RATIO_SHIFT)
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_RATIO_RANGE                     15:8
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_RATIO_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_RATIO_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_RATIO_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_RATIO_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_RATIO_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+//  PLLC_OUT1 divider clk enable.  0 = disable, 1 = enable.
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_CLKEN_SHIFT                     _MK_SHIFT_CONST(1)
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_CLKEN_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_CLKEN_SHIFT)
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_CLKEN_RANGE                     1:1
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_CLKEN_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_CLKEN_DEFAULT                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_CLKEN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_CLKEN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_CLKEN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_CLKEN_INIT_ENUM                 ENABLE
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_CLKEN_DISABLE                   _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_CLKEN_ENABLE                    _MK_ENUM_CONST(1)
+
+//  PLLC_OUT1 divider reset.  0 = reset, 1 = not reset.
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_RSTN_SHIFT                      _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_RSTN_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_RSTN_SHIFT)
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_RSTN_RANGE                      0:0
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_RSTN_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_RSTN_DEFAULT                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_RSTN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_RSTN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_RSTN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_RSTN_INIT_ENUM                  RESET_DISABLE
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_RSTN_RESET_ENABLE                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_RSTN_RESET_DISABLE                      _MK_ENUM_CONST(1)
+
+
+// Reserved address 136 [0x88] 
+
+// Register CLK_RST_CONTROLLER_PLLC_MISC_0  
+#define CLK_RST_CONTROLLER_PLLC_MISC_0                  _MK_ADDR_CONST(0x8c)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_WORD_COUNT                       0x1
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_RESET_VAL                        _MK_MASK_CONST(0x100)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_RESET_MASK                       _MK_MASK_CONST(0xc0d7ffff)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_READ_MASK                        _MK_MASK_CONST(0xc0d7ffff)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_WRITE_MASK                       _MK_MASK_CONST(0xc0d7ffff)
+//  1 = invert PLLC_OUT1 clock.
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_OUT1_INV_CLK_SHIFT                  _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_OUT1_INV_CLK_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_OUT1_INV_CLK_SHIFT)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_OUT1_INV_CLK_RANGE                  31:31
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_OUT1_INV_CLK_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_OUT1_INV_CLK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_OUT1_INV_CLK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_OUT1_INV_CLK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_OUT1_INV_CLK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  1 = bypass PLLC_OUT1 divider.
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_OUT1_DIV_BYP_SHIFT                  _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_OUT1_DIV_BYP_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_OUT1_DIV_BYP_SHIFT)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_OUT1_DIV_BYP_RANGE                  30:30
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_OUT1_DIV_BYP_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_OUT1_DIV_BYP_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_OUT1_DIV_BYP_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_OUT1_DIV_BYP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_OUT1_DIV_BYP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  Base PLLC test output select.
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_PTS_SHIFT                   _MK_SHIFT_CONST(22)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_PTS_FIELD                   (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_PTS_SHIFT)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_PTS_RANGE                   23:22
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_PTS_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_PTS_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_PTS_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_PTS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_PTS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+//  Base PLLC DCCON control.
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_DCCON_SHIFT                 _MK_SHIFT_CONST(20)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_DCCON_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_DCCON_SHIFT)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_DCCON_RANGE                 20:20
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_DCCON_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_DCCON_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_DCCON_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_DCCON_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_DCCON_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//  1 = enable, 0 = disable. 
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_LOCK_ENABLE_SHIFT                   _MK_SHIFT_CONST(18)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_LOCK_ENABLE_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_LOCK_ENABLE_SHIFT)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_LOCK_ENABLE_RANGE                   18:18
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_LOCK_ENABLE_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_LOCK_ENABLE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_LOCK_ENABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_LOCK_ENABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_LOCK_ENABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_LOCK_ENABLE_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_LOCK_ENABLE_ENABLE                  _MK_ENUM_CONST(1)
+
+//  lock select.
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_LOCK_SEL_SHIFT                      _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_LOCK_SEL_FIELD                      (_MK_MASK_CONST(0x3f) << CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_LOCK_SEL_SHIFT)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_LOCK_SEL_RANGE                      17:12
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_LOCK_SEL_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_LOCK_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_LOCK_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3f)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_LOCK_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_LOCK_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+//  Base PLLC charge pump setup control.
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_CPCON_SHIFT                 _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_CPCON_FIELD                 (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_CPCON_SHIFT)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_CPCON_RANGE                 11:8
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_CPCON_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_CPCON_DEFAULT                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_CPCON_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_CPCON_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_CPCON_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//  Base PLLC loop filter setup control.
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_LFCON_SHIFT                 _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_LFCON_FIELD                 (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_LFCON_SHIFT)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_LFCON_RANGE                 7:4
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_LFCON_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_LFCON_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_LFCON_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_LFCON_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_LFCON_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//  Base PLLC VCO range setup control.
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_VCOCON_SHIFT                        _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_VCOCON_FIELD                        (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_VCOCON_SHIFT)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_VCOCON_RANGE                        3:0
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_VCOCON_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_VCOCON_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_VCOCON_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_VCOCON_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_VCOCON_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_PLLM_BASE_0  
+#define CLK_RST_CONTROLLER_PLLM_BASE_0                  _MK_ADDR_CONST(0x90)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_WORD_COUNT                       0x1
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_RESET_VAL                        _MK_MASK_CONST(0x10c)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_RESET_MASK                       _MK_MASK_CONST(0xe873ff1f)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_READ_MASK                        _MK_MASK_CONST(0xe873ff1f)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_WRITE_MASK                       _MK_MASK_CONST(0xe073ff1f)
+//  0 = no bypass, 1 = bypass.
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_BYPASS_SHIFT                        _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_BYPASS_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_BYPASS_SHIFT)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_BYPASS_RANGE                        31:31
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_BYPASS_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_BYPASS_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_BYPASS_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_BYPASS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_BYPASS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_BYPASS_INIT_ENUM                    DISABLE
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_BYPASS_DISABLE                      _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_BYPASS_ENABLE                       _MK_ENUM_CONST(1)
+
+//  0 = disable, 1 = enable.
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_ENABLE_SHIFT                        _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_ENABLE_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_ENABLE_SHIFT)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_ENABLE_RANGE                        30:30
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_ENABLE_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_ENABLE_INIT_ENUM                    DISABLE
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_ENABLE_DISABLE                      _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_ENABLE_ENABLE                       _MK_ENUM_CONST(1)
+
+//  0 = enable reference clk, 1 = disable reference clk.
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_REF_DIS_SHIFT                       _MK_SHIFT_CONST(29)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_REF_DIS_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_REF_DIS_SHIFT)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_REF_DIS_RANGE                       29:29
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_REF_DIS_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_REF_DIS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_REF_DIS_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_REF_DIS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_REF_DIS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_REF_DIS_INIT_ENUM                   REF_ENABLE
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_REF_DIS_REF_ENABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_REF_DIS_REF_DISABLE                 _MK_ENUM_CONST(1)
+
+//  0 = not lock, 1 = lock.
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_LOCK_SHIFT                  _MK_SHIFT_CONST(27)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_LOCK_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_LOCK_SHIFT)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_LOCK_RANGE                  27:27
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_LOCK_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_LOCK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_LOCK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_LOCK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_LOCK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  0 = post divider (2^n).
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVP_SHIFT                  _MK_SHIFT_CONST(20)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVP_FIELD                  (_MK_MASK_CONST(0x7) << CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVP_SHIFT)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVP_RANGE                  22:20
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVP_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVP_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVP_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  PLL feedback divider.
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVN_SHIFT                  _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVN_FIELD                  (_MK_MASK_CONST(0x3ff) << CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVN_SHIFT)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVN_RANGE                  17:8
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVN_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVN_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVN_DEFAULT_MASK                   _MK_MASK_CONST(0x3ff)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  PLL input divider.
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVM_SHIFT                  _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVM_FIELD                  (_MK_MASK_CONST(0x1f) << CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVM_SHIFT)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVM_RANGE                  4:0
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVM_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVM_DEFAULT                        _MK_MASK_CONST(0xc)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVM_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_PLLM_OUT_0  
+#define CLK_RST_CONTROLLER_PLLM_OUT_0                   _MK_ADDR_CONST(0x94)
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_WORD_COUNT                        0x1
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_RESET_VAL                         _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_RESET_MASK                        _MK_MASK_CONST(0xff03)
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_READ_MASK                         _MK_MASK_CONST(0xff03)
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_WRITE_MASK                        _MK_MASK_CONST(0xff03)
+//  PLLM_OUT1 divider from base PLLM (lsb denote 0.5x).
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_RATIO_SHIFT                     _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_RATIO_FIELD                     (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_RATIO_SHIFT)
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_RATIO_RANGE                     15:8
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_RATIO_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_RATIO_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_RATIO_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_RATIO_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_RATIO_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+//  PLLM_OUT1 divider clk enable.  0 = disable, 1 = enable.
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_CLKEN_SHIFT                     _MK_SHIFT_CONST(1)
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_CLKEN_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_CLKEN_SHIFT)
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_CLKEN_RANGE                     1:1
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_CLKEN_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_CLKEN_DEFAULT                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_CLKEN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_CLKEN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_CLKEN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_CLKEN_INIT_ENUM                 ENABLE
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_CLKEN_DISABLE                   _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_CLKEN_ENABLE                    _MK_ENUM_CONST(1)
+
+//  PLLM_OUT1 divider reset.  0 = reset, 1 = not reset.
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_RSTN_SHIFT                      _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_RSTN_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_RSTN_SHIFT)
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_RSTN_RANGE                      0:0
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_RSTN_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_RSTN_DEFAULT                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_RSTN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_RSTN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_RSTN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_RSTN_INIT_ENUM                  RESET_DISABLE
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_RSTN_RESET_ENABLE                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_RSTN_RESET_DISABLE                      _MK_ENUM_CONST(1)
+
+
+// Reserved address 152 [0x98] 
+
+// Register CLK_RST_CONTROLLER_PLLM_MISC_0  
+#define CLK_RST_CONTROLLER_PLLM_MISC_0                  _MK_ADDR_CONST(0x9c)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_WORD_COUNT                       0x1
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_RESET_VAL                        _MK_MASK_CONST(0x100)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_RESET_MASK                       _MK_MASK_CONST(0xc0d7ffff)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_READ_MASK                        _MK_MASK_CONST(0xc0d7ffff)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_WRITE_MASK                       _MK_MASK_CONST(0xc0d7ffff)
+//  1 = invert PLLM_OUT1 clock.
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_OUT1_INV_CLK_SHIFT                  _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_OUT1_INV_CLK_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_OUT1_INV_CLK_SHIFT)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_OUT1_INV_CLK_RANGE                  31:31
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_OUT1_INV_CLK_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_OUT1_INV_CLK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_OUT1_INV_CLK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_OUT1_INV_CLK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_OUT1_INV_CLK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  1 = bypass PLLM_OUT1 divider.
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_OUT1_DIV_BYP_SHIFT                  _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_OUT1_DIV_BYP_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_OUT1_DIV_BYP_SHIFT)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_OUT1_DIV_BYP_RANGE                  30:30
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_OUT1_DIV_BYP_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_OUT1_DIV_BYP_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_OUT1_DIV_BYP_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_OUT1_DIV_BYP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_OUT1_DIV_BYP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  Base PLLM test output select.
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_PTS_SHIFT                   _MK_SHIFT_CONST(22)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_PTS_FIELD                   (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_PTS_SHIFT)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_PTS_RANGE                   23:22
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_PTS_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_PTS_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_PTS_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_PTS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_PTS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+//  Base PLLM DCCON control.
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_DCCON_SHIFT                 _MK_SHIFT_CONST(20)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_DCCON_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_DCCON_SHIFT)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_DCCON_RANGE                 20:20
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_DCCON_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_DCCON_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_DCCON_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_DCCON_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_DCCON_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//  1 = enable, 0 = disable. 
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_LOCK_ENABLE_SHIFT                   _MK_SHIFT_CONST(18)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_LOCK_ENABLE_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_LOCK_ENABLE_SHIFT)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_LOCK_ENABLE_RANGE                   18:18
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_LOCK_ENABLE_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_LOCK_ENABLE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_LOCK_ENABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_LOCK_ENABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_LOCK_ENABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_LOCK_ENABLE_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_LOCK_ENABLE_ENABLE                  _MK_ENUM_CONST(1)
+
+//  lock select.
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_LOCK_SEL_SHIFT                      _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_LOCK_SEL_FIELD                      (_MK_MASK_CONST(0x3f) << CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_LOCK_SEL_SHIFT)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_LOCK_SEL_RANGE                      17:12
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_LOCK_SEL_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_LOCK_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_LOCK_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3f)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_LOCK_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_LOCK_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+//  Base PLLM charge pump setup control.
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_CPCON_SHIFT                 _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_CPCON_FIELD                 (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_CPCON_SHIFT)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_CPCON_RANGE                 11:8
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_CPCON_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_CPCON_DEFAULT                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_CPCON_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_CPCON_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_CPCON_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//  Base PLLM loop filter setup control.
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_LFCON_SHIFT                 _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_LFCON_FIELD                 (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_LFCON_SHIFT)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_LFCON_RANGE                 7:4
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_LFCON_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_LFCON_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_LFCON_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_LFCON_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_LFCON_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//  Base PLLM VCO range setup control.
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_VCOCON_SHIFT                        _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_VCOCON_FIELD                        (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_VCOCON_SHIFT)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_VCOCON_RANGE                        3:0
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_VCOCON_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_VCOCON_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_VCOCON_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_VCOCON_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_VCOCON_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_PLLP_BASE_0  
+#define CLK_RST_CONTROLLER_PLLP_BASE_0                  _MK_ADDR_CONST(0xa0)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_WORD_COUNT                       0x1
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_RESET_VAL                        _MK_MASK_CONST(0x10c)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_RESET_MASK                       _MK_MASK_CONST(0xf873ff1f)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_READ_MASK                        _MK_MASK_CONST(0xf873ff1f)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_WRITE_MASK                       _MK_MASK_CONST(0xf073ff1f)
+//  0 = no bypass, 1 = bypass.
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BYPASS_SHIFT                        _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BYPASS_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BYPASS_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BYPASS_RANGE                        31:31
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BYPASS_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BYPASS_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BYPASS_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BYPASS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BYPASS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BYPASS_INIT_ENUM                    DISABLE
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BYPASS_DISABLE                      _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BYPASS_ENABLE                       _MK_ENUM_CONST(1)
+
+//  0 = disable, 1 = enable.
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_ENABLE_SHIFT                        _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_ENABLE_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_ENABLE_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_ENABLE_RANGE                        30:30
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_ENABLE_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_ENABLE_INIT_ENUM                    DISABLE
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_ENABLE_DISABLE                      _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_ENABLE_ENABLE                       _MK_ENUM_CONST(1)
+
+//  0 = enable reference clk, 1 = disable reference clk.
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_REF_DIS_SHIFT                       _MK_SHIFT_CONST(29)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_REF_DIS_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_REF_DIS_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_REF_DIS_RANGE                       29:29
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_REF_DIS_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_REF_DIS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_REF_DIS_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_REF_DIS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_REF_DIS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_REF_DIS_INIT_ENUM                   REF_ENABLE
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_REF_DIS_REF_ENABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_REF_DIS_REF_DISABLE                 _MK_ENUM_CONST(1)
+
+//  0 = disallow base override , 1 = allow base override.
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BASE_OVRRIDE_SHIFT                  _MK_SHIFT_CONST(28)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BASE_OVRRIDE_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BASE_OVRRIDE_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BASE_OVRRIDE_RANGE                  28:28
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BASE_OVRRIDE_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BASE_OVRRIDE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BASE_OVRRIDE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BASE_OVRRIDE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BASE_OVRRIDE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BASE_OVRRIDE_INIT_ENUM                      DISABLE
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BASE_OVRRIDE_DISABLE                        _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BASE_OVRRIDE_ENABLE                 _MK_ENUM_CONST(1)
+
+//  0 = not lock, 1 = lock.
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_LOCK_SHIFT                  _MK_SHIFT_CONST(27)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_LOCK_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_LOCK_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_LOCK_RANGE                  27:27
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_LOCK_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_LOCK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_LOCK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_LOCK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_LOCK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  0 = post divider (2^n).
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVP_SHIFT                  _MK_SHIFT_CONST(20)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVP_FIELD                  (_MK_MASK_CONST(0x7) << CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVP_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVP_RANGE                  22:20
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVP_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVP_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVP_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  PLL feedback divider.
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVN_SHIFT                  _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVN_FIELD                  (_MK_MASK_CONST(0x3ff) << CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVN_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVN_RANGE                  17:8
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVN_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVN_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVN_DEFAULT_MASK                   _MK_MASK_CONST(0x3ff)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  PLL input divider.
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVM_SHIFT                  _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVM_FIELD                  (_MK_MASK_CONST(0x1f) << CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVM_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVM_RANGE                  4:0
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVM_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVM_DEFAULT                        _MK_MASK_CONST(0xc)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVM_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_PLLP_OUTA_0  
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0                  _MK_ADDR_CONST(0xa4)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_WORD_COUNT                       0x1
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_RESET_VAL                        _MK_MASK_CONST(0x30003)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_RESET_MASK                       _MK_MASK_CONST(0xff07ff07)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_READ_MASK                        _MK_MASK_CONST(0xff07ff07)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_WRITE_MASK                       _MK_MASK_CONST(0xff07ff07)
+//  PLLP_OUT2 divider from base PLLP (lsb denote 0.5x).
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_RATIO_SHIFT                    _MK_SHIFT_CONST(24)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_RATIO_FIELD                    (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_RATIO_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_RATIO_RANGE                    31:24
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_RATIO_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_RATIO_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_RATIO_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_RATIO_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_RATIO_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+//  0 = disallow PLLP_OUT2 ratio override, 1 = enable override.
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_OVRRIDE_SHIFT                  _MK_SHIFT_CONST(18)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_OVRRIDE_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_OVRRIDE_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_OVRRIDE_RANGE                  18:18
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_OVRRIDE_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_OVRRIDE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_OVRRIDE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_OVRRIDE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_OVRRIDE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_OVRRIDE_INIT_ENUM                      DISABLE
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_OVRRIDE_DISABLE                        _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_OVRRIDE_ENABLE                 _MK_ENUM_CONST(1)
+
+//  PLLP_OUT2 divider clk enable.  0 = disable, 1 = enable.
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_CLKEN_SHIFT                    _MK_SHIFT_CONST(17)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_CLKEN_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_CLKEN_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_CLKEN_RANGE                    17:17
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_CLKEN_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_CLKEN_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_CLKEN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_CLKEN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_CLKEN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_CLKEN_INIT_ENUM                        ENABLE
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_CLKEN_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_CLKEN_ENABLE                   _MK_ENUM_CONST(1)
+
+//  PLLP_OUT2 divider reset.  0 = reset, 1 = not reset.
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_RSTN_SHIFT                     _MK_SHIFT_CONST(16)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_RSTN_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_RSTN_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_RSTN_RANGE                     16:16
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_RSTN_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_RSTN_DEFAULT                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_RSTN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_RSTN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_RSTN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_RSTN_INIT_ENUM                 RESET_DISABLE
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_RSTN_RESET_ENABLE                      _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_RSTN_RESET_DISABLE                     _MK_ENUM_CONST(1)
+
+//  PLLP_OUT1 divider from base PLLP (lsb denote 0.5x).
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_RATIO_SHIFT                    _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_RATIO_FIELD                    (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_RATIO_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_RATIO_RANGE                    15:8
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_RATIO_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_RATIO_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_RATIO_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_RATIO_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_RATIO_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+//  0 = disallow PLLP_OUT1 ratio override, 1 = enable override.
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_OVRRIDE_SHIFT                  _MK_SHIFT_CONST(2)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_OVRRIDE_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_OVRRIDE_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_OVRRIDE_RANGE                  2:2
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_OVRRIDE_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_OVRRIDE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_OVRRIDE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_OVRRIDE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_OVRRIDE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_OVRRIDE_INIT_ENUM                      DISABLE
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_OVRRIDE_DISABLE                        _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_OVRRIDE_ENABLE                 _MK_ENUM_CONST(1)
+
+//  PLLP_OUT1 divider clk enable.  0 = disable, 1 = enable.
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_CLKEN_SHIFT                    _MK_SHIFT_CONST(1)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_CLKEN_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_CLKEN_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_CLKEN_RANGE                    1:1
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_CLKEN_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_CLKEN_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_CLKEN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_CLKEN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_CLKEN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_CLKEN_INIT_ENUM                        ENABLE
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_CLKEN_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_CLKEN_ENABLE                   _MK_ENUM_CONST(1)
+
+//  PLLP_OUT1 divider reset.  0 = reset, 1 = not reset.
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_RSTN_SHIFT                     _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_RSTN_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_RSTN_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_RSTN_RANGE                     0:0
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_RSTN_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_RSTN_DEFAULT                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_RSTN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_RSTN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_RSTN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_RSTN_INIT_ENUM                 RESET_DISABLE
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_RSTN_RESET_ENABLE                      _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_RSTN_RESET_DISABLE                     _MK_ENUM_CONST(1)
+
+
+// Register CLK_RST_CONTROLLER_PLLP_OUTB_0  
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0                  _MK_ADDR_CONST(0xa8)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_WORD_COUNT                       0x1
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_RESET_VAL                        _MK_MASK_CONST(0x30003)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_RESET_MASK                       _MK_MASK_CONST(0xff07ff07)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_READ_MASK                        _MK_MASK_CONST(0xff07ff07)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_WRITE_MASK                       _MK_MASK_CONST(0xff07ff07)
+//  PLLP_OUT4 divider from base PLLP (lsb denote 0.5x).
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_RATIO_SHIFT                    _MK_SHIFT_CONST(24)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_RATIO_FIELD                    (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_RATIO_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_RATIO_RANGE                    31:24
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_RATIO_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_RATIO_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_RATIO_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_RATIO_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_RATIO_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+//  0 = disallow PLLP_OUT4 ratio override, 1 = enable override.
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_OVRRIDE_SHIFT                  _MK_SHIFT_CONST(18)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_OVRRIDE_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_OVRRIDE_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_OVRRIDE_RANGE                  18:18
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_OVRRIDE_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_OVRRIDE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_OVRRIDE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_OVRRIDE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_OVRRIDE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_OVRRIDE_INIT_ENUM                      DISABLE
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_OVRRIDE_DISABLE                        _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_OVRRIDE_ENABLE                 _MK_ENUM_CONST(1)
+
+//  PLLP_OUT4 divider clk enable.  0 = disable, 1 = enable.
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_CLKEN_SHIFT                    _MK_SHIFT_CONST(17)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_CLKEN_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_CLKEN_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_CLKEN_RANGE                    17:17
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_CLKEN_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_CLKEN_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_CLKEN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_CLKEN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_CLKEN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_CLKEN_INIT_ENUM                        ENABLE
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_CLKEN_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_CLKEN_ENABLE                   _MK_ENUM_CONST(1)
+
+//  PLLP_OUT4 divider reset.  0 = reset, 1 = not reset.
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_RSTN_SHIFT                     _MK_SHIFT_CONST(16)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_RSTN_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_RSTN_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_RSTN_RANGE                     16:16
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_RSTN_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_RSTN_DEFAULT                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_RSTN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_RSTN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_RSTN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_RSTN_INIT_ENUM                 RESET_DISABLE
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_RSTN_RESET_ENABLE                      _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_RSTN_RESET_DISABLE                     _MK_ENUM_CONST(1)
+
+//  PLLP_OUT3 divider from base PLLP (lsb denote 0.5x).
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_RATIO_SHIFT                    _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_RATIO_FIELD                    (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_RATIO_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_RATIO_RANGE                    15:8
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_RATIO_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_RATIO_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_RATIO_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_RATIO_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_RATIO_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+//  0 = disallow PLLP_OUT3 ratio override, 1 = enable override.
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_OVRRIDE_SHIFT                  _MK_SHIFT_CONST(2)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_OVRRIDE_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_OVRRIDE_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_OVRRIDE_RANGE                  2:2
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_OVRRIDE_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_OVRRIDE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_OVRRIDE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_OVRRIDE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_OVRRIDE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_OVRRIDE_INIT_ENUM                      DISABLE
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_OVRRIDE_DISABLE                        _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_OVRRIDE_ENABLE                 _MK_ENUM_CONST(1)
+
+//  PLLP_OUT3 divider clk enable.  0 = disable, 1 = enable.
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_CLKEN_SHIFT                    _MK_SHIFT_CONST(1)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_CLKEN_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_CLKEN_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_CLKEN_RANGE                    1:1
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_CLKEN_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_CLKEN_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_CLKEN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_CLKEN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_CLKEN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_CLKEN_INIT_ENUM                        ENABLE
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_CLKEN_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_CLKEN_ENABLE                   _MK_ENUM_CONST(1)
+
+//  PLLP_OUT3 divider reset.  0 = reset, 1 = not reset.
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_RSTN_SHIFT                     _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_RSTN_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_RSTN_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_RSTN_RANGE                     0:0
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_RSTN_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_RSTN_DEFAULT                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_RSTN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_RSTN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_RSTN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_RSTN_INIT_ENUM                 RESET_DISABLE
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_RSTN_RESET_ENABLE                      _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_RSTN_RESET_DISABLE                     _MK_ENUM_CONST(1)
+
+
+// Register CLK_RST_CONTROLLER_PLLP_MISC_0  
+#define CLK_RST_CONTROLLER_PLLP_MISC_0                  _MK_ADDR_CONST(0xac)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_WORD_COUNT                       0x1
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_RESET_VAL                        _MK_MASK_CONST(0x100)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_RESET_MASK                       _MK_MASK_CONST(0xffd7ffff)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_READ_MASK                        _MK_MASK_CONST(0xffd7ffff)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_WRITE_MASK                       _MK_MASK_CONST(0xffd7ffff)
+//  1 = invert PLLP_OUT4 clock.
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT4_INV_CLK_SHIFT                  _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT4_INV_CLK_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT4_INV_CLK_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT4_INV_CLK_RANGE                  31:31
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT4_INV_CLK_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT4_INV_CLK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT4_INV_CLK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT4_INV_CLK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT4_INV_CLK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  1 = invert PLLP_OUT3 clock.
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT3_INV_CLK_SHIFT                  _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT3_INV_CLK_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT3_INV_CLK_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT3_INV_CLK_RANGE                  30:30
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT3_INV_CLK_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT3_INV_CLK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT3_INV_CLK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT3_INV_CLK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT3_INV_CLK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  1 = invert PLLP_OUT2 clock.
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT2_INV_CLK_SHIFT                  _MK_SHIFT_CONST(29)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT2_INV_CLK_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT2_INV_CLK_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT2_INV_CLK_RANGE                  29:29
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT2_INV_CLK_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT2_INV_CLK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT2_INV_CLK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT2_INV_CLK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT2_INV_CLK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  1 = invert PLLP_OUT1 clock.
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT1_INV_CLK_SHIFT                  _MK_SHIFT_CONST(28)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT1_INV_CLK_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT1_INV_CLK_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT1_INV_CLK_RANGE                  28:28
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT1_INV_CLK_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT1_INV_CLK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT1_INV_CLK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT1_INV_CLK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT1_INV_CLK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  1 = bypass PLLP_OUT4 divider.
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT4_DIV_BYP_SHIFT                  _MK_SHIFT_CONST(27)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT4_DIV_BYP_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT4_DIV_BYP_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT4_DIV_BYP_RANGE                  27:27
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT4_DIV_BYP_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT4_DIV_BYP_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT4_DIV_BYP_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT4_DIV_BYP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT4_DIV_BYP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  1 = bypass PLLP_OUT3 divider.
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT3_DIV_BYP_SHIFT                  _MK_SHIFT_CONST(26)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT3_DIV_BYP_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT3_DIV_BYP_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT3_DIV_BYP_RANGE                  26:26
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT3_DIV_BYP_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT3_DIV_BYP_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT3_DIV_BYP_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT3_DIV_BYP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT3_DIV_BYP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  1 = bypass PLLP_OUT2 divider.
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT2_DIV_BYP_SHIFT                  _MK_SHIFT_CONST(25)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT2_DIV_BYP_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT2_DIV_BYP_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT2_DIV_BYP_RANGE                  25:25
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT2_DIV_BYP_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT2_DIV_BYP_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT2_DIV_BYP_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT2_DIV_BYP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT2_DIV_BYP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  1 = bypass PLLP_OUT1 divider.
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT1_DIV_BYP_SHIFT                  _MK_SHIFT_CONST(24)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT1_DIV_BYP_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT1_DIV_BYP_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT1_DIV_BYP_RANGE                  24:24
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT1_DIV_BYP_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT1_DIV_BYP_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT1_DIV_BYP_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT1_DIV_BYP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT1_DIV_BYP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  Base PLLP test output select.
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_PTS_SHIFT                   _MK_SHIFT_CONST(22)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_PTS_FIELD                   (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_PTS_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_PTS_RANGE                   23:22
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_PTS_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_PTS_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_PTS_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_PTS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_PTS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+//  Base PLLP DCCON control.
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_DCCON_SHIFT                 _MK_SHIFT_CONST(20)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_DCCON_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_DCCON_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_DCCON_RANGE                 20:20
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_DCCON_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_DCCON_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_DCCON_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_DCCON_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_DCCON_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//  1 = enable, 0 = disable. 
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LOCK_ENABLE_SHIFT                   _MK_SHIFT_CONST(18)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LOCK_ENABLE_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LOCK_ENABLE_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LOCK_ENABLE_RANGE                   18:18
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LOCK_ENABLE_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LOCK_ENABLE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LOCK_ENABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LOCK_ENABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LOCK_ENABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LOCK_ENABLE_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LOCK_ENABLE_ENABLE                  _MK_ENUM_CONST(1)
+
+//  lock select.
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LOCK_SEL_SHIFT                      _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LOCK_SEL_FIELD                      (_MK_MASK_CONST(0x3f) << CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LOCK_SEL_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LOCK_SEL_RANGE                      17:12
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LOCK_SEL_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LOCK_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LOCK_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3f)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LOCK_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LOCK_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+//  Base PLLP charge pump setup control.
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_CPCON_SHIFT                 _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_CPCON_FIELD                 (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_CPCON_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_CPCON_RANGE                 11:8
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_CPCON_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_CPCON_DEFAULT                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_CPCON_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_CPCON_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_CPCON_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//  Base PLLP loop filter setup control.
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LFCON_SHIFT                 _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LFCON_FIELD                 (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LFCON_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LFCON_RANGE                 7:4
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LFCON_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LFCON_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LFCON_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LFCON_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LFCON_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//  Base PLLP VCO range setup control.
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_VCOCON_SHIFT                        _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_VCOCON_FIELD                        (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_VCOCON_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_VCOCON_RANGE                        3:0
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_VCOCON_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_VCOCON_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_VCOCON_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_VCOCON_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_VCOCON_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_PLLA_BASE_0  
+#define CLK_RST_CONTROLLER_PLLA_BASE_0                  _MK_ADDR_CONST(0xb0)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_WORD_COUNT                       0x1
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_RESET_VAL                        _MK_MASK_CONST(0x10c)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_RESET_MASK                       _MK_MASK_CONST(0xe873ff1f)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_READ_MASK                        _MK_MASK_CONST(0xe873ff1f)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_WRITE_MASK                       _MK_MASK_CONST(0xe073ff1f)
+//  0 = no bypass, 1 = bypass.
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_BYPASS_SHIFT                        _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_BYPASS_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_BYPASS_SHIFT)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_BYPASS_RANGE                        31:31
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_BYPASS_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_BYPASS_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_BYPASS_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_BYPASS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_BYPASS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_BYPASS_INIT_ENUM                    DISABLE
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_BYPASS_DISABLE                      _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_BYPASS_ENABLE                       _MK_ENUM_CONST(1)
+
+//  0 = disable, 1 = enable.
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_ENABLE_SHIFT                        _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_ENABLE_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_ENABLE_SHIFT)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_ENABLE_RANGE                        30:30
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_ENABLE_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_ENABLE_INIT_ENUM                    DISABLE
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_ENABLE_DISABLE                      _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_ENABLE_ENABLE                       _MK_ENUM_CONST(1)
+
+//  0 = enable reference clk, 1 = disable reference clk.
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_REF_DIS_SHIFT                       _MK_SHIFT_CONST(29)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_REF_DIS_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_REF_DIS_SHIFT)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_REF_DIS_RANGE                       29:29
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_REF_DIS_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_REF_DIS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_REF_DIS_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_REF_DIS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_REF_DIS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_REF_DIS_INIT_ENUM                   REF_ENABLE
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_REF_DIS_REF_ENABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_REF_DIS_REF_DISABLE                 _MK_ENUM_CONST(1)
+
+//  0 = not lock, 1 = lock.
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_LOCK_SHIFT                  _MK_SHIFT_CONST(27)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_LOCK_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_LOCK_SHIFT)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_LOCK_RANGE                  27:27
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_LOCK_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_LOCK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_LOCK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_LOCK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_LOCK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  0 = post divider (2^n).
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVP_SHIFT                  _MK_SHIFT_CONST(20)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVP_FIELD                  (_MK_MASK_CONST(0x7) << CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVP_SHIFT)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVP_RANGE                  22:20
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVP_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVP_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVP_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  PLL feedback divider.
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVN_SHIFT                  _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVN_FIELD                  (_MK_MASK_CONST(0x3ff) << CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVN_SHIFT)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVN_RANGE                  17:8
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVN_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVN_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVN_DEFAULT_MASK                   _MK_MASK_CONST(0x3ff)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  PLL input divider.
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVM_SHIFT                  _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVM_FIELD                  (_MK_MASK_CONST(0x1f) << CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVM_SHIFT)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVM_RANGE                  4:0
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVM_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVM_DEFAULT                        _MK_MASK_CONST(0xc)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVM_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_PLLA_OUT_0  
+#define CLK_RST_CONTROLLER_PLLA_OUT_0                   _MK_ADDR_CONST(0xb4)
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_WORD_COUNT                        0x1
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_RESET_VAL                         _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_RESET_MASK                        _MK_MASK_CONST(0xff03)
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_READ_MASK                         _MK_MASK_CONST(0xff03)
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_WRITE_MASK                        _MK_MASK_CONST(0xff03)
+//  PLLA_OUT0 divider from base PLLA (lsb denote 0.5x).
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RATIO_SHIFT                     _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RATIO_FIELD                     (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RATIO_SHIFT)
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RATIO_RANGE                     15:8
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RATIO_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RATIO_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RATIO_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RATIO_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RATIO_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RATIO_DISABLE                   _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RATIO_ENABLE                    _MK_ENUM_CONST(1)
+
+//  PLLA_OUT0 divider clk enable.  0 = disable, 1 = enable.
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_CLKEN_SHIFT                     _MK_SHIFT_CONST(1)
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_CLKEN_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_CLKEN_SHIFT)
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_CLKEN_RANGE                     1:1
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_CLKEN_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_CLKEN_DEFAULT                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_CLKEN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_CLKEN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_CLKEN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_CLKEN_INIT_ENUM                 ENABLE
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_CLKEN_DISABLE                   _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_CLKEN_ENABLE                    _MK_ENUM_CONST(1)
+
+//  PLLA_OUT0 divider reset.  0 = reset, 1 = not reset.
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RSTN_SHIFT                      _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RSTN_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RSTN_SHIFT)
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RSTN_RANGE                      0:0
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RSTN_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RSTN_DEFAULT                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RSTN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RSTN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RSTN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RSTN_INIT_ENUM                  RESET_DISABLE
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RSTN_RESET_ENABLE                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RSTN_RESET_DISABLE                      _MK_ENUM_CONST(1)
+
+
+// Reserved address 184 [0xb8] 
+
+// Register CLK_RST_CONTROLLER_PLLA_MISC_0  
+#define CLK_RST_CONTROLLER_PLLA_MISC_0                  _MK_ADDR_CONST(0xbc)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_WORD_COUNT                       0x1
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_RESET_VAL                        _MK_MASK_CONST(0x100)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_RESET_MASK                       _MK_MASK_CONST(0xc0d7ffff)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_READ_MASK                        _MK_MASK_CONST(0xc0d7ffff)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_WRITE_MASK                       _MK_MASK_CONST(0xc0d7ffff)
+//  1 = invert PLLA_OUT0 clock.
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_OUT0_INV_CLK_SHIFT                  _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_OUT0_INV_CLK_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_OUT0_INV_CLK_SHIFT)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_OUT0_INV_CLK_RANGE                  31:31
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_OUT0_INV_CLK_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_OUT0_INV_CLK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_OUT0_INV_CLK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_OUT0_INV_CLK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_OUT0_INV_CLK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  1 = bypass PLLA_OUT0 divider.
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_OUT0_DIV_BYP_SHIFT                  _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_OUT0_DIV_BYP_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_OUT0_DIV_BYP_SHIFT)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_OUT0_DIV_BYP_RANGE                  30:30
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_OUT0_DIV_BYP_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_OUT0_DIV_BYP_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_OUT0_DIV_BYP_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_OUT0_DIV_BYP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_OUT0_DIV_BYP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  Base PLLA test output select.
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_PTS_SHIFT                   _MK_SHIFT_CONST(22)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_PTS_FIELD                   (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_PTS_SHIFT)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_PTS_RANGE                   23:22
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_PTS_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_PTS_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_PTS_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_PTS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_PTS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+//  Base PLLA DCCON control.
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_DCCON_SHIFT                 _MK_SHIFT_CONST(20)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_DCCON_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_DCCON_SHIFT)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_DCCON_RANGE                 20:20
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_DCCON_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_DCCON_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_DCCON_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_DCCON_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_DCCON_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//  1 = enable, 0 = disable. 
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_LOCK_ENABLE_SHIFT                   _MK_SHIFT_CONST(18)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_LOCK_ENABLE_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_LOCK_ENABLE_SHIFT)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_LOCK_ENABLE_RANGE                   18:18
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_LOCK_ENABLE_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_LOCK_ENABLE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_LOCK_ENABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_LOCK_ENABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_LOCK_ENABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_LOCK_ENABLE_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_LOCK_ENABLE_ENABLE                  _MK_ENUM_CONST(1)
+
+//  lock select.
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_LOCK_SEL_SHIFT                      _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_LOCK_SEL_FIELD                      (_MK_MASK_CONST(0x3f) << CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_LOCK_SEL_SHIFT)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_LOCK_SEL_RANGE                      17:12
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_LOCK_SEL_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_LOCK_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_LOCK_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3f)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_LOCK_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_LOCK_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+//  Base PLLA charge pump setup control.
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_CPCON_SHIFT                 _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_CPCON_FIELD                 (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_CPCON_SHIFT)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_CPCON_RANGE                 11:8
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_CPCON_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_CPCON_DEFAULT                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_CPCON_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_CPCON_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_CPCON_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//  Base PLLA loop filter setup control.
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_LFCON_SHIFT                 _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_LFCON_FIELD                 (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_LFCON_SHIFT)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_LFCON_RANGE                 7:4
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_LFCON_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_LFCON_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_LFCON_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_LFCON_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_LFCON_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//  Base PLLA VCO range setup control.
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_VCOCON_SHIFT                        _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_VCOCON_FIELD                        (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_VCOCON_SHIFT)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_VCOCON_RANGE                        3:0
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_VCOCON_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_VCOCON_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_VCOCON_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_VCOCON_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_VCOCON_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_PLLU_BASE_0  
+#define CLK_RST_CONTROLLER_PLLU_BASE_0                  _MK_ADDR_CONST(0xc0)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_WORD_COUNT                       0x1
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_RESET_VAL                        _MK_MASK_CONST(0x10c)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_RESET_MASK                       _MK_MASK_CONST(0xe873ff1f)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_READ_MASK                        _MK_MASK_CONST(0xe873ff1f)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_WRITE_MASK                       _MK_MASK_CONST(0xe073ff1f)
+//  0 = no bypass, 1 = bypass.
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_BYPASS_SHIFT                        _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_BYPASS_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_BYPASS_SHIFT)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_BYPASS_RANGE                        31:31
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_BYPASS_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_BYPASS_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_BYPASS_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_BYPASS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_BYPASS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_BYPASS_INIT_ENUM                    DISABLE
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_BYPASS_DISABLE                      _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_BYPASS_ENABLE                       _MK_ENUM_CONST(1)
+
+//  0 = disable, 1 = enable.
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_ENABLE_SHIFT                        _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_ENABLE_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_ENABLE_SHIFT)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_ENABLE_RANGE                        30:30
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_ENABLE_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_ENABLE_INIT_ENUM                    DISABLE
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_ENABLE_DISABLE                      _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_ENABLE_ENABLE                       _MK_ENUM_CONST(1)
+
+//  0 = enable reference clk, 1 = disable reference clk.
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_REF_DIS_SHIFT                       _MK_SHIFT_CONST(29)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_REF_DIS_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_REF_DIS_SHIFT)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_REF_DIS_RANGE                       29:29
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_REF_DIS_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_REF_DIS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_REF_DIS_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_REF_DIS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_REF_DIS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_REF_DIS_INIT_ENUM                   REF_ENABLE
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_REF_DIS_REF_ENABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_REF_DIS_REF_DISABLE                 _MK_ENUM_CONST(1)
+
+//  0 = not lock, 1 = lock.
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_LOCK_SHIFT                  _MK_SHIFT_CONST(27)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_LOCK_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_LOCK_SHIFT)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_LOCK_RANGE                  27:27
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_LOCK_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_LOCK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_LOCK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_LOCK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_LOCK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  0 = post divider (2^n).
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_DIVP_SHIFT                  _MK_SHIFT_CONST(20)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_DIVP_FIELD                  (_MK_MASK_CONST(0x7) << CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_DIVP_SHIFT)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_DIVP_RANGE                  22:20
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_DIVP_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_DIVP_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_DIVP_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_DIVP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_DIVP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  PLL feedback divider.
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_DIVN_SHIFT                  _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_DIVN_FIELD                  (_MK_MASK_CONST(0x3ff) << CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_DIVN_SHIFT)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_DIVN_RANGE                  17:8
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_DIVN_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_DIVN_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_DIVN_DEFAULT_MASK                   _MK_MASK_CONST(0x3ff)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_DIVN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_DIVN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  PLL input divider.
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_DIVM_SHIFT                  _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_DIVM_FIELD                  (_MK_MASK_CONST(0x1f) << CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_DIVM_SHIFT)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_DIVM_RANGE                  4:0
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_DIVM_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_DIVM_DEFAULT                        _MK_MASK_CONST(0xc)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_DIVM_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_DIVM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_DIVM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Reserved address 196 [0xc4] 
+
+// Reserved address 200 [0xc8] 
+
+// Register CLK_RST_CONTROLLER_PLLU_MISC_0  
+#define CLK_RST_CONTROLLER_PLLU_MISC_0                  _MK_ADDR_CONST(0xcc)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_WORD_COUNT                       0x1
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_RESET_VAL                        _MK_MASK_CONST(0x100)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+//  1 = 5-125MHz, 0 = 40-1000MHz.
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_FO_MODE_SHIFT                       _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_FO_MODE_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_FO_MODE_SHIFT)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_FO_MODE_RANGE                       31:31
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_FO_MODE_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_FO_MODE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_FO_MODE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_FO_MODE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_FO_MODE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+//  0 = disable, 1 = normal operation.
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_CLKENABLE_SHIFT                     _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_CLKENABLE_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_CLKENABLE_SHIFT)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_CLKENABLE_RANGE                     30:30
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_CLKENABLE_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_CLKENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_CLKENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_CLKENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_CLKENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+//  Base PLLU test output select.
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_PTS_SHIFT                   _MK_SHIFT_CONST(27)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_PTS_FIELD                   (_MK_MASK_CONST(0x7) << CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_PTS_SHIFT)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_PTS_RANGE                   29:27
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_PTS_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_PTS_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_PTS_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_PTS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_PTS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+//  load pulse position adjust.
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LOADADJ_SHIFT                       _MK_SHIFT_CONST(24)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LOADADJ_FIELD                       (_MK_MASK_CONST(0x7) << CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LOADADJ_SHIFT)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LOADADJ_RANGE                       26:24
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LOADADJ_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LOADADJ_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LOADADJ_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LOADADJ_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LOADADJ_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+//  0 = normal operation, 1 = reset.
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_DIV_RST_SHIFT                       _MK_SHIFT_CONST(23)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_DIV_RST_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_DIV_RST_SHIFT)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_DIV_RST_RANGE                       23:23
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_DIV_RST_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_DIV_RST_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_DIV_RST_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_DIV_RST_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_DIV_RST_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+//  1 = enable, 0 = disable. 
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LOCK_ENABLE_SHIFT                   _MK_SHIFT_CONST(22)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LOCK_ENABLE_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LOCK_ENABLE_SHIFT)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LOCK_ENABLE_RANGE                   22:22
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LOCK_ENABLE_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LOCK_ENABLE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LOCK_ENABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LOCK_ENABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LOCK_ENABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LOCK_ENABLE_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LOCK_ENABLE_ENABLE                  _MK_ENUM_CONST(1)
+
+//  lock select.
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LOCK_SEL_SHIFT                      _MK_SHIFT_CONST(16)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LOCK_SEL_FIELD                      (_MK_MASK_CONST(0x3f) << CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LOCK_SEL_SHIFT)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LOCK_SEL_RANGE                      21:16
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LOCK_SEL_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LOCK_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LOCK_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3f)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LOCK_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LOCK_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+//  Base PLLU DCCON control.
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_DCCON_SHIFT                 _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_DCCON_FIELD                 (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_DCCON_SHIFT)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_DCCON_RANGE                 15:12
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_DCCON_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_DCCON_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_DCCON_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_DCCON_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_DCCON_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//  Base PLLU charge pump setup control.
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_CPCON_SHIFT                 _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_CPCON_FIELD                 (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_CPCON_SHIFT)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_CPCON_RANGE                 11:8
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_CPCON_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_CPCON_DEFAULT                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_CPCON_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_CPCON_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_CPCON_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//  Base PLLU loop filter setup control.
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LFCON_SHIFT                 _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LFCON_FIELD                 (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LFCON_SHIFT)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LFCON_RANGE                 7:4
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LFCON_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LFCON_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LFCON_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LFCON_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LFCON_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//  Base PLLU VCO range setup control.
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_VCOCON_SHIFT                        _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_VCOCON_FIELD                        (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_VCOCON_SHIFT)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_VCOCON_RANGE                        3:0
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_VCOCON_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_VCOCON_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_VCOCON_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_VCOCON_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_VCOCON_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_PLLD_BASE_0  
+#define CLK_RST_CONTROLLER_PLLD_BASE_0                  _MK_ADDR_CONST(0xd0)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_WORD_COUNT                       0x1
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_RESET_VAL                        _MK_MASK_CONST(0x10c)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_RESET_MASK                       _MK_MASK_CONST(0xe873ff1f)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_READ_MASK                        _MK_MASK_CONST(0xe873ff1f)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_WRITE_MASK                       _MK_MASK_CONST(0xe073ff1f)
+//  0 = no bypass, 1 = bypass.
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_BYPASS_SHIFT                        _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_BYPASS_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_BYPASS_SHIFT)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_BYPASS_RANGE                        31:31
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_BYPASS_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_BYPASS_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_BYPASS_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_BYPASS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_BYPASS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_BYPASS_INIT_ENUM                    DISABLE
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_BYPASS_DISABLE                      _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_BYPASS_ENABLE                       _MK_ENUM_CONST(1)
+
+//  0 = disable, 1 = enable.
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_ENABLE_SHIFT                        _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_ENABLE_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_ENABLE_SHIFT)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_ENABLE_RANGE                        30:30
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_ENABLE_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_ENABLE_INIT_ENUM                    DISABLE
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_ENABLE_DISABLE                      _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_ENABLE_ENABLE                       _MK_ENUM_CONST(1)
+
+//  0 = enable reference clk, 1 = disable reference clk.
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_REF_DIS_SHIFT                       _MK_SHIFT_CONST(29)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_REF_DIS_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_REF_DIS_SHIFT)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_REF_DIS_RANGE                       29:29
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_REF_DIS_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_REF_DIS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_REF_DIS_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_REF_DIS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_REF_DIS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_REF_DIS_INIT_ENUM                   REF_ENABLE
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_REF_DIS_REF_ENABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_REF_DIS_REF_DISABLE                 _MK_ENUM_CONST(1)
+
+//  0 = not lock, 1 = lock.
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_LOCK_SHIFT                  _MK_SHIFT_CONST(27)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_LOCK_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_LOCK_SHIFT)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_LOCK_RANGE                  27:27
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_LOCK_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_LOCK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_LOCK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_LOCK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_LOCK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  0 = post divider (2^n).
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVP_SHIFT                  _MK_SHIFT_CONST(20)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVP_FIELD                  (_MK_MASK_CONST(0x7) << CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVP_SHIFT)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVP_RANGE                  22:20
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVP_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVP_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVP_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  PLL feedback divider.
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVN_SHIFT                  _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVN_FIELD                  (_MK_MASK_CONST(0x3ff) << CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVN_SHIFT)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVN_RANGE                  17:8
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVN_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVN_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVN_DEFAULT_MASK                   _MK_MASK_CONST(0x3ff)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  PLL input divider.
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVM_SHIFT                  _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVM_FIELD                  (_MK_MASK_CONST(0x1f) << CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVM_SHIFT)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVM_RANGE                  4:0
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVM_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVM_DEFAULT                        _MK_MASK_CONST(0xc)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVM_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Reserved address 212 [0xd4] 
+
+// Reserved address 216 [0xd8] 
+
+// Register CLK_RST_CONTROLLER_PLLD_MISC_0  
+#define CLK_RST_CONTROLLER_PLLD_MISC_0                  _MK_ADDR_CONST(0xdc)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_WORD_COUNT                       0x1
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_RESET_VAL                        _MK_MASK_CONST(0x100)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+//  1 = 5-125MHz, 0 = 40-1000MHz.
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_FO_MODE_SHIFT                       _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_FO_MODE_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_FO_MODE_SHIFT)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_FO_MODE_RANGE                       31:31
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_FO_MODE_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_FO_MODE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_FO_MODE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_FO_MODE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_FO_MODE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+//  0 = disable, 1 = normal operation.
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_CLKENABLE_SHIFT                     _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_CLKENABLE_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_CLKENABLE_SHIFT)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_CLKENABLE_RANGE                     30:30
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_CLKENABLE_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_CLKENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_CLKENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_CLKENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_CLKENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+//  Base PLLD test output select.
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_PTS_SHIFT                   _MK_SHIFT_CONST(27)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_PTS_FIELD                   (_MK_MASK_CONST(0x7) << CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_PTS_SHIFT)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_PTS_RANGE                   29:27
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_PTS_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_PTS_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_PTS_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_PTS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_PTS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+//  load pulse position adjust.
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOADADJ_SHIFT                       _MK_SHIFT_CONST(24)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOADADJ_FIELD                       (_MK_MASK_CONST(0x7) << CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOADADJ_SHIFT)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOADADJ_RANGE                       26:24
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOADADJ_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOADADJ_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOADADJ_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOADADJ_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOADADJ_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+//  0 = normal operation, 1 = reset.
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_DIV_RST_SHIFT                       _MK_SHIFT_CONST(23)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_DIV_RST_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_DIV_RST_SHIFT)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_DIV_RST_RANGE                       23:23
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_DIV_RST_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_DIV_RST_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_DIV_RST_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_DIV_RST_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_DIV_RST_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+//  1 = enable, 0 = disable. 
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOCK_ENABLE_SHIFT                   _MK_SHIFT_CONST(22)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOCK_ENABLE_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOCK_ENABLE_SHIFT)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOCK_ENABLE_RANGE                   22:22
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOCK_ENABLE_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOCK_ENABLE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOCK_ENABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOCK_ENABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOCK_ENABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOCK_ENABLE_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOCK_ENABLE_ENABLE                  _MK_ENUM_CONST(1)
+
+//  lock select.
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOCK_SEL_SHIFT                      _MK_SHIFT_CONST(16)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOCK_SEL_FIELD                      (_MK_MASK_CONST(0x3f) << CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOCK_SEL_SHIFT)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOCK_SEL_RANGE                      21:16
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOCK_SEL_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOCK_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOCK_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3f)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOCK_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOCK_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+//  Base PLLD DCCON control.
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_DCCON_SHIFT                 _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_DCCON_FIELD                 (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_DCCON_SHIFT)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_DCCON_RANGE                 15:12
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_DCCON_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_DCCON_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_DCCON_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_DCCON_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_DCCON_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//  Base PLLD charge pump setup control.
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_CPCON_SHIFT                 _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_CPCON_FIELD                 (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_CPCON_SHIFT)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_CPCON_RANGE                 11:8
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_CPCON_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_CPCON_DEFAULT                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_CPCON_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_CPCON_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_CPCON_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//  Base PLLD loop filter setup control.
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LFCON_SHIFT                 _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LFCON_FIELD                 (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LFCON_SHIFT)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LFCON_RANGE                 7:4
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LFCON_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LFCON_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LFCON_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LFCON_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LFCON_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//  Base PLLD VCO range setup control.
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_VCOCON_SHIFT                        _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_VCOCON_FIELD                        (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_VCOCON_SHIFT)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_VCOCON_RANGE                        3:0
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_VCOCON_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_VCOCON_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_VCOCON_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_VCOCON_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_VCOCON_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Reserved address 224 [0xe0] 
+
+// Reserved address 228 [0xe4] 
+
+// Reserved address 232 [0xe8] 
+
+// Reserved address 236 [0xec] 
+
+// Register CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0  
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0                 _MK_ADDR_CONST(0xf0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_WORD_COUNT                      0x1
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_TVDAC_CLK_OVR_ON_SHIFT                  _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_TVDAC_CLK_OVR_ON_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_TVDAC_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_TVDAC_CLK_OVR_ON_RANGE                  31:31
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_TVDAC_CLK_OVR_ON_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_TVDAC_CLK_OVR_ON_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_TVDAC_CLK_OVR_ON_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_TVDAC_CLK_OVR_ON_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_TVDAC_CLK_OVR_ON_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_PPCS_CLK_OVR_ON_SHIFT                   _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_PPCS_CLK_OVR_ON_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_PPCS_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_PPCS_CLK_OVR_ON_RANGE                   30:30
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_PPCS_CLK_OVR_ON_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_PPCS_CLK_OVR_ON_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_PPCS_CLK_OVR_ON_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_PPCS_CLK_OVR_ON_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_PPCS_CLK_OVR_ON_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_BSEA_CLK_OVR_ON_SHIFT                   _MK_SHIFT_CONST(29)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_BSEA_CLK_OVR_ON_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_BSEA_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_BSEA_CLK_OVR_ON_RANGE                   29:29
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_BSEA_CLK_OVR_ON_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_BSEA_CLK_OVR_ON_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_BSEA_CLK_OVR_ON_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_BSEA_CLK_OVR_ON_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_BSEA_CLK_OVR_ON_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_BSEV_CLK_OVR_ON_SHIFT                   _MK_SHIFT_CONST(28)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_BSEV_CLK_OVR_ON_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_BSEV_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_BSEV_CLK_OVR_ON_RANGE                   28:28
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_BSEV_CLK_OVR_ON_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_BSEV_CLK_OVR_ON_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_BSEV_CLK_OVR_ON_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_BSEV_CLK_OVR_ON_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_BSEV_CLK_OVR_ON_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_VDE_CLK_OVR_ON_SHIFT                    _MK_SHIFT_CONST(27)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_VDE_CLK_OVR_ON_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_VDE_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_VDE_CLK_OVR_ON_RANGE                    27:27
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_VDE_CLK_OVR_ON_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_VDE_CLK_OVR_ON_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_VDE_CLK_OVR_ON_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_VDE_CLK_OVR_ON_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_VDE_CLK_OVR_ON_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_VPECLK_OVR_ON_SHIFT                        _MK_SHIFT_CONST(26)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_VPECLK_OVR_ON_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_VPECLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_VPECLK_OVR_ON_RANGE                        26:26
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_VPECLK_OVR_ON_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_VPECLK_OVR_ON_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_VPECLK_OVR_ON_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_VPECLK_OVR_ON_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_VPECLK_OVR_ON_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_TEXCLK_OVR_ON_SHIFT                        _MK_SHIFT_CONST(25)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_TEXCLK_OVR_ON_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_TEXCLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_TEXCLK_OVR_ON_RANGE                        25:25
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_TEXCLK_OVR_ON_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_TEXCLK_OVR_ON_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_TEXCLK_OVR_ON_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_TEXCLK_OVR_ON_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_TEXCLK_OVR_ON_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_SETUPCLK_OVR_ON_SHIFT                      _MK_SHIFT_CONST(24)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_SETUPCLK_OVR_ON_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_SETUPCLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_SETUPCLK_OVR_ON_RANGE                      24:24
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_SETUPCLK_OVR_ON_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_SETUPCLK_OVR_ON_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_SETUPCLK_OVR_ON_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_SETUPCLK_OVR_ON_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_SETUPCLK_OVR_ON_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_QRASTCLK_OVR_ON_SHIFT                      _MK_SHIFT_CONST(23)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_QRASTCLK_OVR_ON_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_QRASTCLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_QRASTCLK_OVR_ON_RANGE                      23:23
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_QRASTCLK_OVR_ON_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_QRASTCLK_OVR_ON_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_QRASTCLK_OVR_ON_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_QRASTCLK_OVR_ON_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_QRASTCLK_OVR_ON_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_PSEQCLK_OVR_ON_SHIFT                       _MK_SHIFT_CONST(22)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_PSEQCLK_OVR_ON_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_PSEQCLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_PSEQCLK_OVR_ON_RANGE                       22:22
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_PSEQCLK_OVR_ON_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_PSEQCLK_OVR_ON_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_PSEQCLK_OVR_ON_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_PSEQCLK_OVR_ON_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_PSEQCLK_OVR_ON_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_IDXCLK_OVR_ON_SHIFT                        _MK_SHIFT_CONST(21)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_IDXCLK_OVR_ON_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_IDXCLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_IDXCLK_OVR_ON_RANGE                        21:21
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_IDXCLK_OVR_ON_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_IDXCLK_OVR_ON_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_IDXCLK_OVR_ON_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_IDXCLK_OVR_ON_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_IDXCLK_OVR_ON_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_FDCCLK_OVR_ON_SHIFT                        _MK_SHIFT_CONST(20)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_FDCCLK_OVR_ON_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_FDCCLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_FDCCLK_OVR_ON_RANGE                        20:20
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_FDCCLK_OVR_ON_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_FDCCLK_OVR_ON_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_FDCCLK_OVR_ON_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_FDCCLK_OVR_ON_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_FDCCLK_OVR_ON_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_DWRCLK_OVR_ON_SHIFT                        _MK_SHIFT_CONST(19)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_DWRCLK_OVR_ON_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_DWRCLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_DWRCLK_OVR_ON_RANGE                        19:19
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_DWRCLK_OVR_ON_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_DWRCLK_OVR_ON_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_DWRCLK_OVR_ON_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_DWRCLK_OVR_ON_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_DWRCLK_OVR_ON_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_CLIPCLK_OVR_ON_SHIFT                       _MK_SHIFT_CONST(18)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_CLIPCLK_OVR_ON_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_CLIPCLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_CLIPCLK_OVR_ON_RANGE                       18:18
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_CLIPCLK_OVR_ON_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_CLIPCLK_OVR_ON_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_CLIPCLK_OVR_ON_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_CLIPCLK_OVR_ON_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_CLIPCLK_OVR_ON_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_ATRASTCLK_OVR_ON_SHIFT                     _MK_SHIFT_CONST(17)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_ATRASTCLK_OVR_ON_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_ATRASTCLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_ATRASTCLK_OVR_ON_RANGE                     17:17
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_ATRASTCLK_OVR_ON_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_ATRASTCLK_OVR_ON_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_ATRASTCLK_OVR_ON_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_ATRASTCLK_OVR_ON_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_ATRASTCLK_OVR_ON_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_ALUCLK_OVR_ON_SHIFT                        _MK_SHIFT_CONST(16)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_ALUCLK_OVR_ON_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_ALUCLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_ALUCLK_OVR_ON_RANGE                        16:16
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_ALUCLK_OVR_ON_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_ALUCLK_OVR_ON_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_ALUCLK_OVR_ON_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_ALUCLK_OVR_ON_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_ALUCLK_OVR_ON_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_VI_CLK_OVR_ON_SHIFT                     _MK_SHIFT_CONST(15)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_VI_CLK_OVR_ON_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_VI_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_VI_CLK_OVR_ON_RANGE                     15:15
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_VI_CLK_OVR_ON_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_VI_CLK_OVR_ON_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_VI_CLK_OVR_ON_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_VI_CLK_OVR_ON_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_VI_CLK_OVR_ON_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_MPE_CLK_OVR_ON_SHIFT                    _MK_SHIFT_CONST(14)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_MPE_CLK_OVR_ON_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_MPE_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_MPE_CLK_OVR_ON_RANGE                    14:14
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_MPE_CLK_OVR_ON_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_MPE_CLK_OVR_ON_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_MPE_CLK_OVR_ON_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_MPE_CLK_OVR_ON_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_MPE_CLK_OVR_ON_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_MPCORE_CLK_OVR_ON_SHIFT                 _MK_SHIFT_CONST(13)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_MPCORE_CLK_OVR_ON_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_MPCORE_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_MPCORE_CLK_OVR_ON_RANGE                 13:13
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_MPCORE_CLK_OVR_ON_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_MPCORE_CLK_OVR_ON_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_MPCORE_CLK_OVR_ON_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_MPCORE_CLK_OVR_ON_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_MPCORE_CLK_OVR_ON_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_MC_CLK_OVR_ON_SHIFT                     _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_MC_CLK_OVR_ON_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_MC_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_MC_CLK_OVR_ON_RANGE                     12:12
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_MC_CLK_OVR_ON_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_MC_CLK_OVR_ON_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_MC_CLK_OVR_ON_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_MC_CLK_OVR_ON_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_MC_CLK_OVR_ON_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_KBC_CLK_OVR_ON_SHIFT                    _MK_SHIFT_CONST(11)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_KBC_CLK_OVR_ON_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_KBC_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_KBC_CLK_OVR_ON_RANGE                    11:11
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_KBC_CLK_OVR_ON_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_KBC_CLK_OVR_ON_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_KBC_CLK_OVR_ON_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_KBC_CLK_OVR_ON_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_KBC_CLK_OVR_ON_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_RIF_CLK_OVR_ON_SHIFT                 _MK_SHIFT_CONST(10)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_RIF_CLK_OVR_ON_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_RIF_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_RIF_CLK_OVR_ON_RANGE                 10:10
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_RIF_CLK_OVR_ON_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_RIF_CLK_OVR_ON_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_RIF_CLK_OVR_ON_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_RIF_CLK_OVR_ON_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_RIF_CLK_OVR_ON_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_RDMA_CLK_OVR_ON_SHIFT                        _MK_SHIFT_CONST(9)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_RDMA_CLK_OVR_ON_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_RDMA_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_RDMA_CLK_OVR_ON_RANGE                        9:9
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_RDMA_CLK_OVR_ON_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_RDMA_CLK_OVR_ON_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_RDMA_CLK_OVR_ON_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_RDMA_CLK_OVR_ON_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_RDMA_CLK_OVR_ON_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_INTFC_OVR_ON_SHIFT                   _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_INTFC_OVR_ON_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_INTFC_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_INTFC_OVR_ON_RANGE                   8:8
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_INTFC_OVR_ON_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_INTFC_OVR_ON_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_INTFC_OVR_ON_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_INTFC_OVR_ON_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_INTFC_OVR_ON_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_CLK_OVR_ON_SHIFT                     _MK_SHIFT_CONST(7)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_CLK_OVR_ON_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_CLK_OVR_ON_RANGE                     7:7
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_CLK_OVR_ON_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_CLK_OVR_ON_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_CLK_OVR_ON_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_CLK_OVR_ON_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_CLK_OVR_ON_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_CDMA_CLK_OVR_ON_SHIFT                        _MK_SHIFT_CONST(6)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_CDMA_CLK_OVR_ON_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_CDMA_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_CDMA_CLK_OVR_ON_RANGE                        6:6
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_CDMA_CLK_OVR_ON_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_CDMA_CLK_OVR_ON_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_CDMA_CLK_OVR_ON_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_CDMA_CLK_OVR_ON_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_CDMA_CLK_OVR_ON_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR2D_CLK_OVR_ON_SHIFT                   _MK_SHIFT_CONST(5)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR2D_CLK_OVR_ON_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR2D_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR2D_CLK_OVR_ON_RANGE                   5:5
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR2D_CLK_OVR_ON_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR2D_CLK_OVR_ON_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR2D_CLK_OVR_ON_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR2D_CLK_OVR_ON_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR2D_CLK_OVR_ON_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_EPP_CLK_OVR_ON_SHIFT                    _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_EPP_CLK_OVR_ON_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_EPP_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_EPP_CLK_OVR_ON_RANGE                    4:4
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_EPP_CLK_OVR_ON_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_EPP_CLK_OVR_ON_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_EPP_CLK_OVR_ON_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_EPP_CLK_OVR_ON_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_EPP_CLK_OVR_ON_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_EMC_CLK_OVR_ON_SHIFT                    _MK_SHIFT_CONST(3)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_EMC_CLK_OVR_ON_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_EMC_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_EMC_CLK_OVR_ON_RANGE                    3:3
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_EMC_CLK_OVR_ON_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_EMC_CLK_OVR_ON_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_EMC_CLK_OVR_ON_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_EMC_CLK_OVR_ON_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_EMC_CLK_OVR_ON_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_DCB_CLK_OVR_ON_SHIFT                    _MK_SHIFT_CONST(2)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_DCB_CLK_OVR_ON_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_DCB_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_DCB_CLK_OVR_ON_RANGE                    2:2
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_DCB_CLK_OVR_ON_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_DCB_CLK_OVR_ON_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_DCB_CLK_OVR_ON_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_DCB_CLK_OVR_ON_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_DCB_CLK_OVR_ON_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_DC_CLK_OVR_ON_SHIFT                     _MK_SHIFT_CONST(1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_DC_CLK_OVR_ON_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_DC_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_DC_CLK_OVR_ON_RANGE                     1:1
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_DC_CLK_OVR_ON_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_DC_CLK_OVR_ON_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_DC_CLK_OVR_ON_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_DC_CLK_OVR_ON_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_DC_CLK_OVR_ON_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_CMC_CLK_OVR_ON_SHIFT                    _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_CMC_CLK_OVR_ON_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_CMC_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_CMC_CLK_OVR_ON_RANGE                    0:0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_CMC_CLK_OVR_ON_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_CMC_CLK_OVR_ON_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_CMC_CLK_OVR_ON_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_CMC_CLK_OVR_ON_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_CMC_CLK_OVR_ON_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0  
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0                 _MK_ADDR_CONST(0xf4)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_WORD_COUNT                      0x1
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_RESET_MASK                      _MK_MASK_CONST(0xfe0003ff)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_READ_MASK                       _MK_MASK_CONST(0xfe0003ff)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_WRITE_MASK                      _MK_MASK_CONST(0xfe0003ff)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_TEX_CLK_OVR_ON_SHIFT                 _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_TEX_CLK_OVR_ON_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_TEX_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_TEX_CLK_OVR_ON_RANGE                 31:31
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_TEX_CLK_OVR_ON_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_TEX_CLK_OVR_ON_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_TEX_CLK_OVR_ON_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_TEX_CLK_OVR_ON_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_TEX_CLK_OVR_ON_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_RAST_CLK_OVR_ON_SHIFT                        _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_RAST_CLK_OVR_ON_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_RAST_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_RAST_CLK_OVR_ON_RANGE                        30:30
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_RAST_CLK_OVR_ON_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_RAST_CLK_OVR_ON_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_RAST_CLK_OVR_ON_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_RAST_CLK_OVR_ON_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_RAST_CLK_OVR_ON_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_PIX_XFORM_CLK_OVR_ON_SHIFT                   _MK_SHIFT_CONST(29)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_PIX_XFORM_CLK_OVR_ON_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_PIX_XFORM_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_PIX_XFORM_CLK_OVR_ON_RANGE                   29:29
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_PIX_XFORM_CLK_OVR_ON_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_PIX_XFORM_CLK_OVR_ON_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_PIX_XFORM_CLK_OVR_ON_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_PIX_XFORM_CLK_OVR_ON_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_PIX_XFORM_CLK_OVR_ON_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_GEOM_CLK_OVR_ON_SHIFT                        _MK_SHIFT_CONST(28)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_GEOM_CLK_OVR_ON_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_GEOM_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_GEOM_CLK_OVR_ON_RANGE                        28:28
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_GEOM_CLK_OVR_ON_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_GEOM_CLK_OVR_ON_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_GEOM_CLK_OVR_ON_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_GEOM_CLK_OVR_ON_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_GEOM_CLK_OVR_ON_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_GATH_CLK_OVR_ON_SHIFT                        _MK_SHIFT_CONST(27)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_GATH_CLK_OVR_ON_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_GATH_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_GATH_CLK_OVR_ON_RANGE                        27:27
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_GATH_CLK_OVR_ON_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_GATH_CLK_OVR_ON_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_GATH_CLK_OVR_ON_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_GATH_CLK_OVR_ON_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_GATH_CLK_OVR_ON_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_GEST_CLK_OVR_ON_SHIFT                        _MK_SHIFT_CONST(26)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_GEST_CLK_OVR_ON_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_GEST_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_GEST_CLK_OVR_ON_RANGE                        26:26
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_GEST_CLK_OVR_ON_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_GEST_CLK_OVR_ON_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_GEST_CLK_OVR_ON_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_GEST_CLK_OVR_ON_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_GEST_CLK_OVR_ON_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_BLEND_CLK_OVR_ON_SHIFT                       _MK_SHIFT_CONST(25)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_BLEND_CLK_OVR_ON_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_BLEND_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_BLEND_CLK_OVR_ON_RANGE                       25:25
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_BLEND_CLK_OVR_ON_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_BLEND_CLK_OVR_ON_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_BLEND_CLK_OVR_ON_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_BLEND_CLK_OVR_ON_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_BLEND_CLK_OVR_ON_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MPEC_CLK_OVR_ON_SHIFT                       _MK_SHIFT_CONST(9)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MPEC_CLK_OVR_ON_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MPEC_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MPEC_CLK_OVR_ON_RANGE                       9:9
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MPEC_CLK_OVR_ON_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MPEC_CLK_OVR_ON_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MPEC_CLK_OVR_ON_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MPEC_CLK_OVR_ON_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MPEC_CLK_OVR_ON_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MPEB_CLK_OVR_ON_SHIFT                       _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MPEB_CLK_OVR_ON_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MPEB_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MPEB_CLK_OVR_ON_RANGE                       8:8
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MPEB_CLK_OVR_ON_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MPEB_CLK_OVR_ON_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MPEB_CLK_OVR_ON_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MPEB_CLK_OVR_ON_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MPEB_CLK_OVR_ON_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_REGS_CLK_OVR_ON_SHIFT                       _MK_SHIFT_CONST(7)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_REGS_CLK_OVR_ON_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_REGS_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_REGS_CLK_OVR_ON_RANGE                       7:7
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_REGS_CLK_OVR_ON_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_REGS_CLK_OVR_ON_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_REGS_CLK_OVR_ON_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_REGS_CLK_OVR_ON_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_REGS_CLK_OVR_ON_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MPEA_CLK_OVR_ON_SHIFT                       _MK_SHIFT_CONST(6)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MPEA_CLK_OVR_ON_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MPEA_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MPEA_CLK_OVR_ON_RANGE                       6:6
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MPEA_CLK_OVR_ON_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MPEA_CLK_OVR_ON_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MPEA_CLK_OVR_ON_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MPEA_CLK_OVR_ON_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MPEA_CLK_OVR_ON_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_PMEM_CLK_OVR_ON_SHIFT                       _MK_SHIFT_CONST(5)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_PMEM_CLK_OVR_ON_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_PMEM_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_PMEM_CLK_OVR_ON_RANGE                       5:5
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_PMEM_CLK_OVR_ON_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_PMEM_CLK_OVR_ON_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_PMEM_CLK_OVR_ON_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_PMEM_CLK_OVR_ON_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_PMEM_CLK_OVR_ON_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_IB_CLK_OVR_ON_SHIFT                 _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_IB_CLK_OVR_ON_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_IB_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_IB_CLK_OVR_ON_RANGE                 4:4
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_IB_CLK_OVR_ON_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_IB_CLK_OVR_ON_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_IB_CLK_OVR_ON_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_IB_CLK_OVR_ON_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_IB_CLK_OVR_ON_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MEMRD_CLK_OVR_ON_SHIFT                      _MK_SHIFT_CONST(3)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MEMRD_CLK_OVR_ON_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MEMRD_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MEMRD_CLK_OVR_ON_RANGE                      3:3
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MEMRD_CLK_OVR_ON_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MEMRD_CLK_OVR_ON_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MEMRD_CLK_OVR_ON_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MEMRD_CLK_OVR_ON_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MEMRD_CLK_OVR_ON_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_RC_CLK_OVR_ON_SHIFT                 _MK_SHIFT_CONST(2)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_RC_CLK_OVR_ON_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_RC_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_RC_CLK_OVR_ON_RANGE                 2:2
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_RC_CLK_OVR_ON_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_RC_CLK_OVR_ON_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_RC_CLK_OVR_ON_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_RC_CLK_OVR_ON_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_RC_CLK_OVR_ON_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_CSI_CLK_OVR_ON_SHIFT                    _MK_SHIFT_CONST(1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_CSI_CLK_OVR_ON_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_CSI_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_CSI_CLK_OVR_ON_RANGE                    1:1
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_CSI_CLK_OVR_ON_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_CSI_CLK_OVR_ON_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_CSI_CLK_OVR_ON_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_CSI_CLK_OVR_ON_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_CSI_CLK_OVR_ON_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_RTC_CLK_OVR_ON_SHIFT                    _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_RTC_CLK_OVR_ON_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_RTC_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_RTC_CLK_OVR_ON_RANGE                    0:0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_RTC_CLK_OVR_ON_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_RTC_CLK_OVR_ON_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_RTC_CLK_OVR_ON_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_RTC_CLK_OVR_ON_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_RTC_CLK_OVR_ON_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Reserved address 248 [0xf8] 
+
+// Reserved address 252 [0xfc] 
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0                    _MK_ADDR_CONST(0x100)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_WORD_COUNT                         0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_RESET_VAL                  _MK_MASK_CONST(0x10000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_RESET_MASK                         _MK_MASK_CONST(0xd00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_READ_MASK                  _MK_MASK_CONST(0xd00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_WRITE_MASK                         _MK_MASK_CONST(0xd00000ff)
+//  00 = pllA_out0
+//  01 = audio SYNC_CLK x 2
+//  10 = pllP_out0
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_SRC_SHIFT                 _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_SRC_FIELD                 (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_SRC_RANGE                 31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_SRC_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_SRC_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_SRC_INIT_ENUM                     PLLA_OUT0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_SRC_PLLA_OUT0                     _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_SRC_SYNC_CLK_X2                   _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_SRC_PLLP_OUT0                     _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_SRC_CLK_M                 _MK_ENUM_CONST(3)
+
+// 1 = enable I2S1 master clock, disable I2S1 master clock.
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_MASTER_CLKEN_SHIFT                    _MK_SHIFT_CONST(28)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_MASTER_CLKEN_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_MASTER_CLKEN_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_MASTER_CLKEN_RANGE                    28:28
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_MASTER_CLKEN_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_MASTER_CLKEN_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_MASTER_CLKEN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_MASTER_CLKEN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_MASTER_CLKEN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+//  N  = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_DIVISOR_SHIFT                     _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_DIVISOR_FIELD                     (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_DIVISOR_RANGE                     7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_DIVISOR_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_DIVISOR_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_DIVISOR_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_DIVISOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_DIVISOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0                    _MK_ADDR_CONST(0x104)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_WORD_COUNT                         0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_RESET_VAL                  _MK_MASK_CONST(0x10000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_RESET_MASK                         _MK_MASK_CONST(0xd00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_READ_MASK                  _MK_MASK_CONST(0xd00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_WRITE_MASK                         _MK_MASK_CONST(0xd00000ff)
+//  00 = pllA_out0
+//  01 = audio SYNC_CLK x 2
+//  10 = pllP_out0
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_SRC_SHIFT                 _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_SRC_FIELD                 (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_SRC_RANGE                 31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_SRC_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_SRC_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_SRC_INIT_ENUM                     PLLA_OUT0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_SRC_PLLA_OUT0                     _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_SRC_SYNC_CLK_X2                   _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_SRC_PLLP_OUT0                     _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_SRC_CLK_M                 _MK_ENUM_CONST(3)
+
+// 1 = enable I2S2 master clock, disable I2S2 master clock.
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_MASTER_CLKEN_SHIFT                    _MK_SHIFT_CONST(28)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_MASTER_CLKEN_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_MASTER_CLKEN_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_MASTER_CLKEN_RANGE                    28:28
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_MASTER_CLKEN_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_MASTER_CLKEN_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_MASTER_CLKEN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_MASTER_CLKEN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_MASTER_CLKEN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+//  N  = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_DIVISOR_SHIFT                     _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_DIVISOR_FIELD                     (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_DIVISOR_RANGE                     7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_DIVISOR_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_DIVISOR_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_DIVISOR_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_DIVISOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_DIVISOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0                   _MK_ADDR_CONST(0x108)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0_WORD_COUNT                        0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0_RESET_MASK                        _MK_MASK_CONST(0xc0ffc0ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0_READ_MASK                         _MK_MASK_CONST(0xc0ffc0ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0_WRITE_MASK                        _MK_MASK_CONST(0xc0ffc0ff)
+//  00 = pllA_out0
+//  01 = audio SYNC_CLK x 2
+//  10 = pllP_out0
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0_SPDIFOUT_CLK_SRC_SHIFT                    _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0_SPDIFOUT_CLK_SRC_FIELD                    (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0_SPDIFOUT_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0_SPDIFOUT_CLK_SRC_RANGE                    31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0_SPDIFOUT_CLK_SRC_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0_SPDIFOUT_CLK_SRC_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0_SPDIFOUT_CLK_SRC_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0_SPDIFOUT_CLK_SRC_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0_SPDIFOUT_CLK_SRC_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0_SPDIFOUT_CLK_SRC_INIT_ENUM                        PLLA_OUT0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0_SPDIFOUT_CLK_SRC_PLLA_OUT0                        _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0_SPDIFOUT_CLK_SRC_SYNC_CLK_X2                      _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0_SPDIFOUT_CLK_SRC_PLLP_OUT0                        _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0_SPDIFOUT_CLK_SRC_CLK_M                    _MK_ENUM_CONST(3)
+
+//  N  = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0_SPDIFOUT_CLK_DIVISOR_SHIFT                        _MK_SHIFT_CONST(16)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0_SPDIFOUT_CLK_DIVISOR_FIELD                        (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0_SPDIFOUT_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0_SPDIFOUT_CLK_DIVISOR_RANGE                        23:16
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0_SPDIFOUT_CLK_DIVISOR_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0_SPDIFOUT_CLK_DIVISOR_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0_SPDIFOUT_CLK_DIVISOR_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0_SPDIFOUT_CLK_DIVISOR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0_SPDIFOUT_CLK_DIVISOR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+//  00 = pllP_out0
+//  01 = pllC_out0
+//  10 = pllM_out0
+//  11 = 1'b0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0_SPDIFIN_CLK_SRC_SHIFT                     _MK_SHIFT_CONST(14)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0_SPDIFIN_CLK_SRC_FIELD                     (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0_SPDIFIN_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0_SPDIFIN_CLK_SRC_RANGE                     15:14
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0_SPDIFIN_CLK_SRC_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0_SPDIFIN_CLK_SRC_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0_SPDIFIN_CLK_SRC_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0_SPDIFIN_CLK_SRC_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0_SPDIFIN_CLK_SRC_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0_SPDIFIN_CLK_SRC_INIT_ENUM                 PLLP_OUT0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0_SPDIFIN_CLK_SRC_PLLP_OUT0                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0_SPDIFIN_CLK_SRC_PLLC_OUT0                 _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0_SPDIFIN_CLK_SRC_PLLM_OUT0                 _MK_ENUM_CONST(2)
+
+//  N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0_SPDIFIN_CLK_DIVISOR_SHIFT                 _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0_SPDIFIN_CLK_DIVISOR_FIELD                 (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0_SPDIFIN_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0_SPDIFIN_CLK_DIVISOR_RANGE                 7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0_SPDIFIN_CLK_DIVISOR_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0_SPDIFIN_CLK_DIVISOR_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0_SPDIFIN_CLK_DIVISOR_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0_SPDIFIN_CLK_DIVISOR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0_SPDIFIN_CLK_DIVISOR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Reserved address 268 [0x10c] 
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0                     _MK_ADDR_CONST(0x110)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_WORD_COUNT                  0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_RESET_MASK                  _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_READ_MASK                   _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_WRITE_MASK                  _MK_MASK_CONST(0xc00000ff)
+//  00 = pllP_out0
+//  01 = pllC_out0
+//  10 = audio SYNC_CLK x 2
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_PWM_CLK_SRC_SHIFT                   _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_PWM_CLK_SRC_FIELD                   (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_PWM_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_PWM_CLK_SRC_RANGE                   31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_PWM_CLK_SRC_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_PWM_CLK_SRC_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_PWM_CLK_SRC_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_PWM_CLK_SRC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_PWM_CLK_SRC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_PWM_CLK_SRC_INIT_ENUM                       PLLP_OUT0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_PWM_CLK_SRC_PLLP_OUT0                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_PWM_CLK_SRC_PLLC_OUT0                       _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_PWM_CLK_SRC_SYNC_CLK_X2                     _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_PWM_CLK_SRC_CLK_M                   _MK_ENUM_CONST(3)
+
+//  N  = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_PWM_CLK_DIVISOR_SHIFT                       _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_PWM_CLK_DIVISOR_FIELD                       (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_PWM_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_PWM_CLK_DIVISOR_RANGE                       7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_PWM_CLK_DIVISOR_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_PWM_CLK_DIVISOR_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_PWM_CLK_DIVISOR_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_PWM_CLK_DIVISOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_PWM_CLK_DIVISOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0                    _MK_ADDR_CONST(0x114)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_WORD_COUNT                         0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_RESET_MASK                         _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_READ_MASK                  _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_WRITE_MASK                         _MK_MASK_CONST(0xc00000ff)
+//  00 = pllP_out0
+//  01 = pllC_out0
+//  10 = pllM_out0
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_SRC_SHIFT                 _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_SRC_FIELD                 (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_SRC_RANGE                 31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_SRC_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_SRC_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_SRC_INIT_ENUM                     PLLP_OUT0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_SRC_PLLP_OUT0                     _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_SRC_PLLC_OUT0                     _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_SRC_PLLM_OUT0                     _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_SRC_CLK_M                 _MK_ENUM_CONST(3)
+
+//  N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_DIVISOR_SHIFT                     _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_DIVISOR_FIELD                     (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_DIVISOR_RANGE                     7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_DIVISOR_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_DIVISOR_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_DIVISOR_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_DIVISOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_DIVISOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0                    _MK_ADDR_CONST(0x118)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0_WORD_COUNT                         0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0_RESET_MASK                         _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0_READ_MASK                  _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0_WRITE_MASK                         _MK_MASK_CONST(0xc00000ff)
+//  00 = pllP_out0
+//  01 = pllC_out0
+//  10 = pllM_out0
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0_SBC2_CLK_SRC_SHIFT                 _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0_SBC2_CLK_SRC_FIELD                 (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0_SBC2_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0_SBC2_CLK_SRC_RANGE                 31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0_SBC2_CLK_SRC_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0_SBC2_CLK_SRC_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0_SBC2_CLK_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0_SBC2_CLK_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0_SBC2_CLK_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0_SBC2_CLK_SRC_INIT_ENUM                     PLLP_OUT0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0_SBC2_CLK_SRC_PLLP_OUT0                     _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0_SBC2_CLK_SRC_PLLC_OUT0                     _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0_SBC2_CLK_SRC_PLLM_OUT0                     _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0_SBC2_CLK_SRC_CLK_M                 _MK_ENUM_CONST(3)
+
+//  N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0_SBC2_CLK_DIVISOR_SHIFT                     _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0_SBC2_CLK_DIVISOR_FIELD                     (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0_SBC2_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0_SBC2_CLK_DIVISOR_RANGE                     7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0_SBC2_CLK_DIVISOR_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0_SBC2_CLK_DIVISOR_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0_SBC2_CLK_DIVISOR_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0_SBC2_CLK_DIVISOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0_SBC2_CLK_DIVISOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0                    _MK_ADDR_CONST(0x11c)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0_WORD_COUNT                         0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0_RESET_MASK                         _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0_READ_MASK                  _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0_WRITE_MASK                         _MK_MASK_CONST(0xc00000ff)
+//  00 = pllP_out0
+//  01 = pllC_out0
+//  10 = pllM_out0
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0_SBC3_CLK_SRC_SHIFT                 _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0_SBC3_CLK_SRC_FIELD                 (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0_SBC3_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0_SBC3_CLK_SRC_RANGE                 31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0_SBC3_CLK_SRC_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0_SBC3_CLK_SRC_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0_SBC3_CLK_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0_SBC3_CLK_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0_SBC3_CLK_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0_SBC3_CLK_SRC_INIT_ENUM                     PLLP_OUT0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0_SBC3_CLK_SRC_PLLP_OUT0                     _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0_SBC3_CLK_SRC_PLLC_OUT0                     _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0_SBC3_CLK_SRC_PLLM_OUT0                     _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0_SBC3_CLK_SRC_CLK_M                 _MK_ENUM_CONST(3)
+
+//  N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0_SBC3_CLK_DIVISOR_SHIFT                     _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0_SBC3_CLK_DIVISOR_FIELD                     (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0_SBC3_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0_SBC3_CLK_DIVISOR_RANGE                     7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0_SBC3_CLK_DIVISOR_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0_SBC3_CLK_DIVISOR_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0_SBC3_CLK_DIVISOR_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0_SBC3_CLK_DIVISOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0_SBC3_CLK_DIVISOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0                     _MK_ADDR_CONST(0x120)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0_WORD_COUNT                  0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0_RESET_MASK                  _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0_READ_MASK                   _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0_WRITE_MASK                  _MK_MASK_CONST(0xc00000ff)
+//  00 = pllP_out0
+//  01 = pllC_out0
+//  10 = pllM_out0
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0_XIO_CLK_SRC_SHIFT                   _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0_XIO_CLK_SRC_FIELD                   (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0_XIO_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0_XIO_CLK_SRC_RANGE                   31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0_XIO_CLK_SRC_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0_XIO_CLK_SRC_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0_XIO_CLK_SRC_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0_XIO_CLK_SRC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0_XIO_CLK_SRC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0_XIO_CLK_SRC_INIT_ENUM                       PLLP_OUT0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0_XIO_CLK_SRC_PLLP_OUT0                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0_XIO_CLK_SRC_PLLC_OUT0                       _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0_XIO_CLK_SRC_PLLM_OUT0                       _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0_XIO_CLK_SRC_CLK_M                   _MK_ENUM_CONST(3)
+
+//  N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0_XIO_CLK_DIVISOR_SHIFT                       _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0_XIO_CLK_DIVISOR_FIELD                       (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0_XIO_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0_XIO_CLK_DIVISOR_RANGE                       7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0_XIO_CLK_DIVISOR_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0_XIO_CLK_DIVISOR_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0_XIO_CLK_DIVISOR_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0_XIO_CLK_DIVISOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0_XIO_CLK_DIVISOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0                    _MK_ADDR_CONST(0x124)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_WORD_COUNT                         0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_RESET_MASK                         _MK_MASK_CONST(0xc000ffff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_READ_MASK                  _MK_MASK_CONST(0xc000ffff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_WRITE_MASK                         _MK_MASK_CONST(0xc000ffff)
+//  00 = pllP_out0
+//  01 = pllC_out0
+//  10 = pllM_out0
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_SRC_SHIFT                 _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_SRC_FIELD                 (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_SRC_RANGE                 31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_SRC_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_SRC_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_SRC_INIT_ENUM                     PLLP_OUT0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_SRC_PLLP_OUT0                     _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_SRC_PLLC_OUT0                     _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_SRC_PLLM_OUT0                     _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_SRC_CLK_M                 _MK_ENUM_CONST(3)
+
+//  N = Divide by (n+1) (lsb denote 1.0x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_DIVISOR_SHIFT                     _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_DIVISOR_FIELD                     (_MK_MASK_CONST(0xffff) << CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_DIVISOR_RANGE                     15:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_DIVISOR_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_DIVISOR_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_DIVISOR_DEFAULT_MASK                      _MK_MASK_CONST(0xffff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_DIVISOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_DIVISOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0                 _MK_ADDR_CONST(0x128)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_WORD_COUNT                      0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_RESET_MASK                      _MK_MASK_CONST(0xc000ffff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_READ_MASK                       _MK_MASK_CONST(0xc000ffff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_WRITE_MASK                      _MK_MASK_CONST(0xc000ffff)
+//  00 = pllP_out0
+//  01 = pllC_out0
+//  10 = pllM_out0
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_DVC_I2C_CLK_SRC_SHIFT                   _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_DVC_I2C_CLK_SRC_FIELD                   (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_DVC_I2C_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_DVC_I2C_CLK_SRC_RANGE                   31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_DVC_I2C_CLK_SRC_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_DVC_I2C_CLK_SRC_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_DVC_I2C_CLK_SRC_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_DVC_I2C_CLK_SRC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_DVC_I2C_CLK_SRC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_DVC_I2C_CLK_SRC_INIT_ENUM                       PLLP_OUT0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_DVC_I2C_CLK_SRC_PLLP_OUT0                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_DVC_I2C_CLK_SRC_PLLC_OUT0                       _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_DVC_I2C_CLK_SRC_PLLM_OUT0                       _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_DVC_I2C_CLK_SRC_CLK_M                   _MK_ENUM_CONST(3)
+
+//  N = Divide by (n+1) (lsb denote 1.0x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_DVC_I2C_CLK_DIVISOR_SHIFT                       _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_DVC_I2C_CLK_DIVISOR_FIELD                       (_MK_MASK_CONST(0xffff) << CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_DVC_I2C_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_DVC_I2C_CLK_DIVISOR_RANGE                       15:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_DVC_I2C_CLK_DIVISOR_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_DVC_I2C_CLK_DIVISOR_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_DVC_I2C_CLK_DIVISOR_DEFAULT_MASK                        _MK_MASK_CONST(0xffff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_DVC_I2C_CLK_DIVISOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_DVC_I2C_CLK_DIVISOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0                     _MK_ADDR_CONST(0x12c)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0_WORD_COUNT                  0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0_RESET_MASK                  _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0_READ_MASK                   _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0_WRITE_MASK                  _MK_MASK_CONST(0xc00000ff)
+//  00 = pllP_out0
+//  01 = pllC_out0
+//  10 = pllM_out0
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0_TWC_CLK_SRC_SHIFT                   _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0_TWC_CLK_SRC_FIELD                   (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0_TWC_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0_TWC_CLK_SRC_RANGE                   31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0_TWC_CLK_SRC_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0_TWC_CLK_SRC_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0_TWC_CLK_SRC_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0_TWC_CLK_SRC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0_TWC_CLK_SRC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0_TWC_CLK_SRC_INIT_ENUM                       PLLP_OUT0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0_TWC_CLK_SRC_PLLP_OUT0                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0_TWC_CLK_SRC_PLLC_OUT0                       _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0_TWC_CLK_SRC_PLLM_OUT0                       _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0_TWC_CLK_SRC_CLK_M                   _MK_ENUM_CONST(3)
+
+//  N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0_TWC_CLK_DIVISOR_SHIFT                       _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0_TWC_CLK_DIVISOR_FIELD                       (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0_TWC_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0_TWC_CLK_DIVISOR_RANGE                       7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0_TWC_CLK_DIVISOR_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0_TWC_CLK_DIVISOR_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0_TWC_CLK_DIVISOR_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0_TWC_CLK_DIVISOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0_TWC_CLK_DIVISOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_SLC1_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SLC1_0                    _MK_ADDR_CONST(0x130)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SLC1_0_WORD_COUNT                         0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SLC1_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SLC1_0_RESET_MASK                         _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SLC1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SLC1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SLC1_0_READ_MASK                  _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SLC1_0_WRITE_MASK                         _MK_MASK_CONST(0xc00000ff)
+//  00 = pllP_out0
+//  01 = pllC_out0
+//  10 = pllM_out0
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SLC1_0_SLC1_CLK_SRC_SHIFT                 _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SLC1_0_SLC1_CLK_SRC_FIELD                 (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_SLC1_0_SLC1_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SLC1_0_SLC1_CLK_SRC_RANGE                 31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SLC1_0_SLC1_CLK_SRC_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SLC1_0_SLC1_CLK_SRC_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SLC1_0_SLC1_CLK_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SLC1_0_SLC1_CLK_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SLC1_0_SLC1_CLK_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SLC1_0_SLC1_CLK_SRC_INIT_ENUM                     PLLP_OUT0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SLC1_0_SLC1_CLK_SRC_PLLP_OUT0                     _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SLC1_0_SLC1_CLK_SRC_PLLC_OUT0                     _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SLC1_0_SLC1_CLK_SRC_PLLM_OUT0                     _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SLC1_0_SLC1_CLK_SRC_CLK_M                 _MK_ENUM_CONST(3)
+
+//  N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SLC1_0_SLC1_CLK_DIVISOR_SHIFT                     _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SLC1_0_SLC1_CLK_DIVISOR_FIELD                     (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_SLC1_0_SLC1_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SLC1_0_SLC1_CLK_DIVISOR_RANGE                     7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SLC1_0_SLC1_CLK_DIVISOR_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SLC1_0_SLC1_CLK_DIVISOR_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SLC1_0_SLC1_CLK_DIVISOR_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SLC1_0_SLC1_CLK_DIVISOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SLC1_0_SLC1_CLK_DIVISOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0                    _MK_ADDR_CONST(0x134)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0_WORD_COUNT                         0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0_RESET_MASK                         _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0_READ_MASK                  _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0_WRITE_MASK                         _MK_MASK_CONST(0xc00000ff)
+//  00 = pllP_out0
+//  01 = pllC_out0
+//  10 = pllM_out0
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0_SBC1_CLK_SRC_SHIFT                 _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0_SBC1_CLK_SRC_FIELD                 (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0_SBC1_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0_SBC1_CLK_SRC_RANGE                 31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0_SBC1_CLK_SRC_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0_SBC1_CLK_SRC_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0_SBC1_CLK_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0_SBC1_CLK_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0_SBC1_CLK_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0_SBC1_CLK_SRC_INIT_ENUM                     PLLP_OUT0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0_SBC1_CLK_SRC_PLLP_OUT0                     _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0_SBC1_CLK_SRC_PLLC_OUT0                     _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0_SBC1_CLK_SRC_PLLM_OUT0                     _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0_SBC1_CLK_SRC_CLK_M                 _MK_ENUM_CONST(3)
+
+//  N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0_SBC1_CLK_DIVISOR_SHIFT                     _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0_SBC1_CLK_DIVISOR_FIELD                     (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0_SBC1_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0_SBC1_CLK_DIVISOR_RANGE                     7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0_SBC1_CLK_DIVISOR_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0_SBC1_CLK_DIVISOR_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0_SBC1_CLK_DIVISOR_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0_SBC1_CLK_DIVISOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0_SBC1_CLK_DIVISOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_DISP1_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP1_0                   _MK_ADDR_CONST(0x138)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP1_0_WORD_COUNT                        0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP1_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP1_0_RESET_MASK                        _MK_MASK_CONST(0xc0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP1_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP1_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP1_0_READ_MASK                         _MK_MASK_CONST(0xc0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP1_0_WRITE_MASK                        _MK_MASK_CONST(0xc0000000)
+//  00 = pllP_out0
+//  01 = pllD_out0
+//  10 = pllC_out0
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP1_0_DISP1_CLK_SRC_SHIFT                       _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP1_0_DISP1_CLK_SRC_FIELD                       (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_DISP1_0_DISP1_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP1_0_DISP1_CLK_SRC_RANGE                       31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP1_0_DISP1_CLK_SRC_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP1_0_DISP1_CLK_SRC_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP1_0_DISP1_CLK_SRC_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP1_0_DISP1_CLK_SRC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP1_0_DISP1_CLK_SRC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP1_0_DISP1_CLK_SRC_INIT_ENUM                   PLLP_OUT0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP1_0_DISP1_CLK_SRC_PLLP_OUT0                   _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP1_0_DISP1_CLK_SRC_PLLD_OUT0                   _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP1_0_DISP1_CLK_SRC_PLLC_OUT0                   _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP1_0_DISP1_CLK_SRC_CLK_M                       _MK_ENUM_CONST(3)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_DISP2_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP2_0                   _MK_ADDR_CONST(0x13c)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP2_0_WORD_COUNT                        0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP2_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP2_0_RESET_MASK                        _MK_MASK_CONST(0xc0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP2_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP2_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP2_0_READ_MASK                         _MK_MASK_CONST(0xc0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP2_0_WRITE_MASK                        _MK_MASK_CONST(0xc0000000)
+//  00 = pllP_out0
+//  01 = pllD_out0
+//  10 = pllC_out0
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP2_0_DISP2_CLK_SRC_SHIFT                       _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP2_0_DISP2_CLK_SRC_FIELD                       (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_DISP2_0_DISP2_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP2_0_DISP2_CLK_SRC_RANGE                       31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP2_0_DISP2_CLK_SRC_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP2_0_DISP2_CLK_SRC_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP2_0_DISP2_CLK_SRC_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP2_0_DISP2_CLK_SRC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP2_0_DISP2_CLK_SRC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP2_0_DISP2_CLK_SRC_INIT_ENUM                   PLLP_OUT0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP2_0_DISP2_CLK_SRC_PLLP_OUT0                   _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP2_0_DISP2_CLK_SRC_PLLD_OUT0                   _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP2_0_DISP2_CLK_SRC_PLLC_OUT0                   _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP2_0_DISP2_CLK_SRC_CLK_M                       _MK_ENUM_CONST(3)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0                     _MK_ADDR_CONST(0x140)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_WORD_COUNT                  0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_RESET_MASK                  _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_READ_MASK                   _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_WRITE_MASK                  _MK_MASK_CONST(0xc00000ff)
+//  00 = pllP_out0
+//  01 = pllD_out0
+//  10 = pllC_out0
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_CVE_CLK_SRC_SHIFT                   _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_CVE_CLK_SRC_FIELD                   (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_CVE_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_CVE_CLK_SRC_RANGE                   31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_CVE_CLK_SRC_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_CVE_CLK_SRC_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_CVE_CLK_SRC_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_CVE_CLK_SRC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_CVE_CLK_SRC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_CVE_CLK_SRC_INIT_ENUM                       PLLP_OUT0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_CVE_CLK_SRC_PLLP_OUT0                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_CVE_CLK_SRC_PLLD_OUT0                       _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_CVE_CLK_SRC_PLLC_OUT0                       _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_CVE_CLK_SRC_CLK_M                   _MK_ENUM_CONST(3)
+
+//  N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_CVE_CLK_DIVISOR_SHIFT                       _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_CVE_CLK_DIVISOR_FIELD                       (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_CVE_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_CVE_CLK_DIVISOR_RANGE                       7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_CVE_CLK_DIVISOR_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_CVE_CLK_DIVISOR_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_CVE_CLK_DIVISOR_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_CVE_CLK_DIVISOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_CVE_CLK_DIVISOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0                     _MK_ADDR_CONST(0x144)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0_WORD_COUNT                  0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0_RESET_MASK                  _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0_READ_MASK                   _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0_WRITE_MASK                  _MK_MASK_CONST(0xc00000ff)
+//  00 = pllP_out0
+//  01 = pllC_out0
+//  10 = pllM_out0
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0_IDE_CLK_SRC_SHIFT                   _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0_IDE_CLK_SRC_FIELD                   (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0_IDE_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0_IDE_CLK_SRC_RANGE                   31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0_IDE_CLK_SRC_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0_IDE_CLK_SRC_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0_IDE_CLK_SRC_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0_IDE_CLK_SRC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0_IDE_CLK_SRC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0_IDE_CLK_SRC_INIT_ENUM                       PLLP_OUT0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0_IDE_CLK_SRC_PLLP_OUT0                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0_IDE_CLK_SRC_PLLC_OUT0                       _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0_IDE_CLK_SRC_PLLM_OUT0                       _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0_IDE_CLK_SRC_CLK_M                   _MK_ENUM_CONST(3)
+
+//  N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0_IDE_CLK_DIVISOR_SHIFT                       _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0_IDE_CLK_DIVISOR_FIELD                       (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0_IDE_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0_IDE_CLK_DIVISOR_RANGE                       7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0_IDE_CLK_DIVISOR_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0_IDE_CLK_DIVISOR_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0_IDE_CLK_DIVISOR_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0_IDE_CLK_DIVISOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0_IDE_CLK_DIVISOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_VI_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0                      _MK_ADDR_CONST(0x148)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_WORD_COUNT                   0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_RESET_MASK                   _MK_MASK_CONST(0xc30000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_READ_MASK                    _MK_MASK_CONST(0xc30000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_WRITE_MASK                   _MK_MASK_CONST(0xc30000ff)
+//  00 = pllM_out0
+//  01 = pllC_out0
+//  10 = pllP_out0
+//  11 = pllA_out0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SRC_SHIFT                     _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SRC_FIELD                     (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SRC_RANGE                     31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SRC_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SRC_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SRC_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SRC_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SRC_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SRC_INIT_ENUM                 PLLM_OUT0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SRC_PLLM_OUT0                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SRC_PLLC_OUT0                 _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SRC_PLLP_OUT0                 _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SRC_PLLA_OUT0                 _MK_ENUM_CONST(3)
+
+// 0 = pd2vi_clk, 1 = vi_sensor_clk.
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_PD2VI_CLK_SEL_SHIFT                  _MK_SHIFT_CONST(25)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_PD2VI_CLK_SEL_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_PD2VI_CLK_SEL_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_PD2VI_CLK_SEL_RANGE                  25:25
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_PD2VI_CLK_SEL_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_PD2VI_CLK_SEL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_PD2VI_CLK_SEL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_PD2VI_CLK_SEL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_PD2VI_CLK_SEL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// 0 = select internal clock, 1 = select external clock (pd2vi_clk).
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SEL_SHIFT                     _MK_SHIFT_CONST(24)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SEL_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SEL_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SEL_RANGE                     24:24
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SEL_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SEL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SEL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SEL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SEL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SEL_INIT_ENUM                 INTERNAL
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SEL_INTERNAL                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SEL_EXTERNAL                  _MK_ENUM_CONST(1)
+
+//  N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_DIVISOR_SHIFT                 _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_DIVISOR_FIELD                 (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_DIVISOR_RANGE                 7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_DIVISOR_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_DIVISOR_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_DIVISOR_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_DIVISOR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_DIVISOR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_MEM_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MEM_0                     _MK_ADDR_CONST(0x14c)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MEM_0_WORD_COUNT                  0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MEM_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MEM_0_RESET_MASK                  _MK_MASK_CONST(0x700000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MEM_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MEM_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MEM_0_READ_MASK                   _MK_MASK_CONST(0x700000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MEM_0_WRITE_MASK                  _MK_MASK_CONST(0x700000ff)
+// 000 = clk_m
+// 001 = pllC_out0
+// 010 = clk_s
+// 011 = pllM_out0
+// 100 = pllP_out0
+// 101 = pllP_out4
+// 110 = pllP_out3
+// 111 = clk_d
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MEM_0_MEM_CLK_SRC_SHIFT                   _MK_SHIFT_CONST(28)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MEM_0_MEM_CLK_SRC_FIELD                   (_MK_MASK_CONST(0x7) << CLK_RST_CONTROLLER_CLK_SOURCE_MEM_0_MEM_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MEM_0_MEM_CLK_SRC_RANGE                   30:28
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MEM_0_MEM_CLK_SRC_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MEM_0_MEM_CLK_SRC_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MEM_0_MEM_CLK_SRC_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MEM_0_MEM_CLK_SRC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MEM_0_MEM_CLK_SRC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MEM_0_MEM_CLK_SRC_INIT_ENUM                       CLK_M
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MEM_0_MEM_CLK_SRC_CLK_M                   _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MEM_0_MEM_CLK_SRC_PLLC_OUT0                       _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MEM_0_MEM_CLK_SRC_CLK_S                   _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MEM_0_MEM_CLK_SRC_PLLM_OUT0                       _MK_ENUM_CONST(3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MEM_0_MEM_CLK_SRC_PLLP_OUT0                       _MK_ENUM_CONST(4)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MEM_0_MEM_CLK_SRC_PLLP_OUT4                       _MK_ENUM_CONST(5)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MEM_0_MEM_CLK_SRC_PLLP_OUT3                       _MK_ENUM_CONST(6)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MEM_0_MEM_CLK_SRC_CLK_D                   _MK_ENUM_CONST(7)
+
+//  N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MEM_0_MEM_CLK_DIVISOR_SHIFT                       _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MEM_0_MEM_CLK_DIVISOR_FIELD                       (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_MEM_0_MEM_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MEM_0_MEM_CLK_DIVISOR_RANGE                       7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MEM_0_MEM_CLK_DIVISOR_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MEM_0_MEM_CLK_DIVISOR_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MEM_0_MEM_CLK_DIVISOR_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MEM_0_MEM_CLK_DIVISOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MEM_0_MEM_CLK_DIVISOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_SDIO1_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDIO1_0                   _MK_ADDR_CONST(0x150)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDIO1_0_WORD_COUNT                        0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDIO1_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDIO1_0_RESET_MASK                        _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDIO1_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDIO1_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDIO1_0_READ_MASK                         _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDIO1_0_WRITE_MASK                        _MK_MASK_CONST(0xc00000ff)
+//  00 = pllP_out0
+//  01 = pllC_out0
+//  10 = pllM_out0
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDIO1_0_SDIO1_CLK_SRC_SHIFT                       _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDIO1_0_SDIO1_CLK_SRC_FIELD                       (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_SDIO1_0_SDIO1_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDIO1_0_SDIO1_CLK_SRC_RANGE                       31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDIO1_0_SDIO1_CLK_SRC_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDIO1_0_SDIO1_CLK_SRC_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDIO1_0_SDIO1_CLK_SRC_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDIO1_0_SDIO1_CLK_SRC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDIO1_0_SDIO1_CLK_SRC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDIO1_0_SDIO1_CLK_SRC_INIT_ENUM                   PLLP_OUT0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDIO1_0_SDIO1_CLK_SRC_PLLP_OUT0                   _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDIO1_0_SDIO1_CLK_SRC_PLLC_OUT0                   _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDIO1_0_SDIO1_CLK_SRC_PLLM_OUT0                   _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDIO1_0_SDIO1_CLK_SRC_CLK_M                       _MK_ENUM_CONST(3)
+
+//  N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDIO1_0_SDIO1_CLK_DIVISOR_SHIFT                   _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDIO1_0_SDIO1_CLK_DIVISOR_FIELD                   (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_SDIO1_0_SDIO1_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDIO1_0_SDIO1_CLK_DIVISOR_RANGE                   7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDIO1_0_SDIO1_CLK_DIVISOR_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDIO1_0_SDIO1_CLK_DIVISOR_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDIO1_0_SDIO1_CLK_DIVISOR_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDIO1_0_SDIO1_CLK_DIVISOR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDIO1_0_SDIO1_CLK_DIVISOR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_SDIO2_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDIO2_0                   _MK_ADDR_CONST(0x154)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDIO2_0_WORD_COUNT                        0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDIO2_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDIO2_0_RESET_MASK                        _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDIO2_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDIO2_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDIO2_0_READ_MASK                         _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDIO2_0_WRITE_MASK                        _MK_MASK_CONST(0xc00000ff)
+//  00 = pllP_out0
+//  01 = pllC_out0
+//  10 = pllM_out0
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDIO2_0_SDIO2_CLK_SRC_SHIFT                       _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDIO2_0_SDIO2_CLK_SRC_FIELD                       (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_SDIO2_0_SDIO2_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDIO2_0_SDIO2_CLK_SRC_RANGE                       31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDIO2_0_SDIO2_CLK_SRC_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDIO2_0_SDIO2_CLK_SRC_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDIO2_0_SDIO2_CLK_SRC_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDIO2_0_SDIO2_CLK_SRC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDIO2_0_SDIO2_CLK_SRC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDIO2_0_SDIO2_CLK_SRC_INIT_ENUM                   PLLP_OUT0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDIO2_0_SDIO2_CLK_SRC_PLLP_OUT0                   _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDIO2_0_SDIO2_CLK_SRC_PLLC_OUT0                   _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDIO2_0_SDIO2_CLK_SRC_PLLM_OUT0                   _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDIO2_0_SDIO2_CLK_SRC_CLK_M                       _MK_ENUM_CONST(3)
+
+//  N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDIO2_0_SDIO2_CLK_DIVISOR_SHIFT                   _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDIO2_0_SDIO2_CLK_DIVISOR_FIELD                   (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_SDIO2_0_SDIO2_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDIO2_0_SDIO2_CLK_DIVISOR_RANGE                   7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDIO2_0_SDIO2_CLK_DIVISOR_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDIO2_0_SDIO2_CLK_DIVISOR_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDIO2_0_SDIO2_CLK_DIVISOR_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDIO2_0_SDIO2_CLK_DIVISOR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDIO2_0_SDIO2_CLK_DIVISOR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0                     _MK_ADDR_CONST(0x158)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_WORD_COUNT                  0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_RESET_MASK                  _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_READ_MASK                   _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_WRITE_MASK                  _MK_MASK_CONST(0xc00000ff)
+//  00 = pllM_out0
+//  01 = pllC_out0
+//  10 = pllP_out0
+//  11 = pllA_out0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_G3D_CLK_SRC_SHIFT                   _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_G3D_CLK_SRC_FIELD                   (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_G3D_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_G3D_CLK_SRC_RANGE                   31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_G3D_CLK_SRC_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_G3D_CLK_SRC_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_G3D_CLK_SRC_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_G3D_CLK_SRC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_G3D_CLK_SRC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_G3D_CLK_SRC_INIT_ENUM                       PLLM_OUT0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_G3D_CLK_SRC_PLLM_OUT0                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_G3D_CLK_SRC_PLLC_OUT0                       _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_G3D_CLK_SRC_PLLP_OUT0                       _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_G3D_CLK_SRC_PLLA_OUT0                       _MK_ENUM_CONST(3)
+
+//  N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_G3D_CLK_DIVISOR_SHIFT                       _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_G3D_CLK_DIVISOR_FIELD                       (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_G3D_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_G3D_CLK_DIVISOR_RANGE                       7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_G3D_CLK_DIVISOR_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_G3D_CLK_DIVISOR_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_G3D_CLK_DIVISOR_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_G3D_CLK_DIVISOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_G3D_CLK_DIVISOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0                     _MK_ADDR_CONST(0x15c)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_WORD_COUNT                  0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_RESET_MASK                  _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_READ_MASK                   _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_WRITE_MASK                  _MK_MASK_CONST(0xc00000ff)
+//  00 = pllM_out0
+//  01 = pllC_out0
+//  10 = pllP_out0
+//  11 = pllA_out0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_G2D_CLK_SRC_SHIFT                   _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_G2D_CLK_SRC_FIELD                   (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_G2D_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_G2D_CLK_SRC_RANGE                   31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_G2D_CLK_SRC_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_G2D_CLK_SRC_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_G2D_CLK_SRC_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_G2D_CLK_SRC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_G2D_CLK_SRC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_G2D_CLK_SRC_INIT_ENUM                       PLLM_OUT0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_G2D_CLK_SRC_PLLM_OUT0                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_G2D_CLK_SRC_PLLC_OUT0                       _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_G2D_CLK_SRC_PLLP_OUT0                       _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_G2D_CLK_SRC_PLLA_OUT0                       _MK_ENUM_CONST(3)
+
+//  N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_G2D_CLK_DIVISOR_SHIFT                       _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_G2D_CLK_DIVISOR_FIELD                       (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_G2D_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_G2D_CLK_DIVISOR_RANGE                       7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_G2D_CLK_DIVISOR_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_G2D_CLK_DIVISOR_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_G2D_CLK_DIVISOR_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_G2D_CLK_DIVISOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_G2D_CLK_DIVISOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0                 _MK_ADDR_CONST(0x160)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_WORD_COUNT                      0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_RESET_MASK                      _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_READ_MASK                       _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_WRITE_MASK                      _MK_MASK_CONST(0xc00000ff)
+// 00 = pllP_out0
+// 01 = pllC_out0
+// 10 = pllM_out0
+// 11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_NDFLASH_CLK_SRC_SHIFT                   _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_NDFLASH_CLK_SRC_FIELD                   (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_NDFLASH_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_NDFLASH_CLK_SRC_RANGE                   31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_NDFLASH_CLK_SRC_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_NDFLASH_CLK_SRC_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_NDFLASH_CLK_SRC_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_NDFLASH_CLK_SRC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_NDFLASH_CLK_SRC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_NDFLASH_CLK_SRC_INIT_ENUM                       PLLP_OUT0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_NDFLASH_CLK_SRC_PLLP_OUT0                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_NDFLASH_CLK_SRC_PLLC_OUT0                       _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_NDFLASH_CLK_SRC_PLLM_OUT0                       _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_NDFLASH_CLK_SRC_CLK_M                   _MK_ENUM_CONST(3)
+
+// N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_NDFLASH_CLK_DIVISOR_SHIFT                       _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_NDFLASH_CLK_DIVISOR_FIELD                       (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_NDFLASH_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_NDFLASH_CLK_DIVISOR_RANGE                       7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_NDFLASH_CLK_DIVISOR_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_NDFLASH_CLK_DIVISOR_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_NDFLASH_CLK_DIVISOR_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_NDFLASH_CLK_DIVISOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_NDFLASH_CLK_DIVISOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_HSMMC_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HSMMC_0                   _MK_ADDR_CONST(0x164)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HSMMC_0_WORD_COUNT                        0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HSMMC_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HSMMC_0_RESET_MASK                        _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HSMMC_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HSMMC_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HSMMC_0_READ_MASK                         _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HSMMC_0_WRITE_MASK                        _MK_MASK_CONST(0xc00000ff)
+// 00 = pllP_out0
+// 01 = pllC_out0
+// 10 = pllM_out0
+// 11 = CLK_M
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HSMMC_0_HSMMC_CLK_SRC_SHIFT                       _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HSMMC_0_HSMMC_CLK_SRC_FIELD                       (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_HSMMC_0_HSMMC_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HSMMC_0_HSMMC_CLK_SRC_RANGE                       31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HSMMC_0_HSMMC_CLK_SRC_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HSMMC_0_HSMMC_CLK_SRC_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HSMMC_0_HSMMC_CLK_SRC_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HSMMC_0_HSMMC_CLK_SRC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HSMMC_0_HSMMC_CLK_SRC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HSMMC_0_HSMMC_CLK_SRC_INIT_ENUM                   PLLP_OUT0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HSMMC_0_HSMMC_CLK_SRC_PLLP_OUT0                   _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HSMMC_0_HSMMC_CLK_SRC_PLLC_OUT0                   _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HSMMC_0_HSMMC_CLK_SRC_PLLM_OUT0                   _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HSMMC_0_HSMMC_CLK_SRC_CLK_M                       _MK_ENUM_CONST(3)
+
+// N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HSMMC_0_HSMMC_CLK_DIVISOR_SHIFT                   _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HSMMC_0_HSMMC_CLK_DIVISOR_FIELD                   (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_HSMMC_0_HSMMC_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HSMMC_0_HSMMC_CLK_DIVISOR_RANGE                   7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HSMMC_0_HSMMC_CLK_DIVISOR_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HSMMC_0_HSMMC_CLK_DIVISOR_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HSMMC_0_HSMMC_CLK_DIVISOR_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HSMMC_0_HSMMC_CLK_DIVISOR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HSMMC_0_HSMMC_CLK_DIVISOR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0                    _MK_ADDR_CONST(0x168)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_WORD_COUNT                         0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_RESET_MASK                         _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_READ_MASK                  _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_WRITE_MASK                         _MK_MASK_CONST(0xc00000ff)
+// 00 = pllP_out0
+// 01 = pllC_out0
+// 10 = pllM_out0
+// 11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_VFIR_CLK_SRC_SHIFT                 _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_VFIR_CLK_SRC_FIELD                 (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_VFIR_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_VFIR_CLK_SRC_RANGE                 31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_VFIR_CLK_SRC_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_VFIR_CLK_SRC_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_VFIR_CLK_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_VFIR_CLK_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_VFIR_CLK_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_VFIR_CLK_SRC_INIT_ENUM                     PLLP_OUT0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_VFIR_CLK_SRC_PLLP_OUT0                     _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_VFIR_CLK_SRC_PLLC_OUT0                     _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_VFIR_CLK_SRC_PLLM_OUT0                     _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_VFIR_CLK_SRC_CLK_M                 _MK_ENUM_CONST(3)
+
+// N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_VFIR_CLK_DIVISOR_SHIFT                     _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_VFIR_CLK_DIVISOR_FIELD                     (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_VFIR_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_VFIR_CLK_DIVISOR_RANGE                     7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_VFIR_CLK_DIVISOR_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_VFIR_CLK_DIVISOR_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_VFIR_CLK_DIVISOR_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_VFIR_CLK_DIVISOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_VFIR_CLK_DIVISOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0                     _MK_ADDR_CONST(0x16c)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0_WORD_COUNT                  0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0_RESET_MASK                  _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0_READ_MASK                   _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0_WRITE_MASK                  _MK_MASK_CONST(0xc00000ff)
+//  00 = pllM_out0
+//  01 = pllC_out0
+//  10 = pllP_out0
+//  11 = pllA_out0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0_EPP_CLK_SRC_SHIFT                   _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0_EPP_CLK_SRC_FIELD                   (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0_EPP_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0_EPP_CLK_SRC_RANGE                   31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0_EPP_CLK_SRC_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0_EPP_CLK_SRC_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0_EPP_CLK_SRC_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0_EPP_CLK_SRC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0_EPP_CLK_SRC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0_EPP_CLK_SRC_INIT_ENUM                       PLLM_OUT0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0_EPP_CLK_SRC_PLLM_OUT0                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0_EPP_CLK_SRC_PLLC_OUT0                       _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0_EPP_CLK_SRC_PLLP_OUT0                       _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0_EPP_CLK_SRC_PLLA_OUT0                       _MK_ENUM_CONST(3)
+
+//  N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0_EPP_CLK_DIVISOR_SHIFT                       _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0_EPP_CLK_DIVISOR_FIELD                       (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0_EPP_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0_EPP_CLK_DIVISOR_RANGE                       7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0_EPP_CLK_DIVISOR_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0_EPP_CLK_DIVISOR_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0_EPP_CLK_DIVISOR_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0_EPP_CLK_DIVISOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0_EPP_CLK_DIVISOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0                     _MK_ADDR_CONST(0x170)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0_WORD_COUNT                  0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0_RESET_MASK                  _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0_READ_MASK                   _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0_WRITE_MASK                  _MK_MASK_CONST(0xc00000ff)
+//  00 = pllM_out0
+//  01 = pllC_out0
+//  10 = pllP_out0
+//  11 = pllA_out0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0_MPE_CLK_SRC_SHIFT                   _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0_MPE_CLK_SRC_FIELD                   (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0_MPE_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0_MPE_CLK_SRC_RANGE                   31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0_MPE_CLK_SRC_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0_MPE_CLK_SRC_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0_MPE_CLK_SRC_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0_MPE_CLK_SRC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0_MPE_CLK_SRC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0_MPE_CLK_SRC_INIT_ENUM                       PLLM_out0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0_MPE_CLK_SRC_PLLM_OUT0                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0_MPE_CLK_SRC_PLLC_OUT0                       _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0_MPE_CLK_SRC_PLLP_OUT0                       _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0_MPE_CLK_SRC_PLLA_OUT0                       _MK_ENUM_CONST(3)
+
+//  N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0_MPE_CLK_DIVISOR_SHIFT                       _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0_MPE_CLK_DIVISOR_FIELD                       (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0_MPE_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0_MPE_CLK_DIVISOR_RANGE                       7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0_MPE_CLK_DIVISOR_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0_MPE_CLK_DIVISOR_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0_MPE_CLK_DIVISOR_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0_MPE_CLK_DIVISOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0_MPE_CLK_DIVISOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0                    _MK_ADDR_CONST(0x174)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0_WORD_COUNT                         0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0_RESET_MASK                         _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0_READ_MASK                  _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0_WRITE_MASK                         _MK_MASK_CONST(0xc00000ff)
+//  00 = pllP_out0
+//  01 = pllC_out0
+//  10 = pllM_out0
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0_MIPI_CLK_SRC_SHIFT                 _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0_MIPI_CLK_SRC_FIELD                 (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0_MIPI_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0_MIPI_CLK_SRC_RANGE                 31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0_MIPI_CLK_SRC_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0_MIPI_CLK_SRC_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0_MIPI_CLK_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0_MIPI_CLK_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0_MIPI_CLK_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0_MIPI_CLK_SRC_INIT_ENUM                     PLLP_OUT0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0_MIPI_CLK_SRC_PLLP_OUT0                     _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0_MIPI_CLK_SRC_PLLC_OUT0                     _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0_MIPI_CLK_SRC_PLLM_OUT0                     _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0_MIPI_CLK_SRC_CLK_M                 _MK_ENUM_CONST(3)
+
+//  N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0_MIPI_CLK_DIVISOR_SHIFT                     _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0_MIPI_CLK_DIVISOR_FIELD                     (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0_MIPI_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0_MIPI_CLK_DIVISOR_RANGE                     7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0_MIPI_CLK_DIVISOR_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0_MIPI_CLK_DIVISOR_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0_MIPI_CLK_DIVISOR_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0_MIPI_CLK_DIVISOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0_MIPI_CLK_DIVISOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0                   _MK_ADDR_CONST(0x178)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_WORD_COUNT                        0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_RESET_MASK                        _MK_MASK_CONST(0xc0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_READ_MASK                         _MK_MASK_CONST(0xc0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_WRITE_MASK                        _MK_MASK_CONST(0xc0000000)
+//  00 = pllP_out0
+//  01 = pllC_out0
+//  10 = pllM_out0
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_SRC_SHIFT                       _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_SRC_FIELD                       (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_SRC_RANGE                       31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_SRC_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_SRC_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_SRC_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_SRC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_SRC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_SRC_INIT_ENUM                   PLLP_OUT0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_SRC_PLLP_OUT0                   _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_SRC_PLLC_OUT0                   _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_SRC_PLLM_OUT0                   _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_SRC_CLK_M                       _MK_ENUM_CONST(3)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0                   _MK_ADDR_CONST(0x17c)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_WORD_COUNT                        0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_RESET_MASK                        _MK_MASK_CONST(0xc0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_READ_MASK                         _MK_MASK_CONST(0xc0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_WRITE_MASK                        _MK_MASK_CONST(0xc0000000)
+//  00 = pllP_out0
+//  01 = pllC_out0
+//  10 = pllM_out0
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_CLK_SRC_SHIFT                       _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_CLK_SRC_FIELD                       (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_CLK_SRC_RANGE                       31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_CLK_SRC_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_CLK_SRC_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_CLK_SRC_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_CLK_SRC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_CLK_SRC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_CLK_SRC_INIT_ENUM                   PLLP_OUT0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_CLK_SRC_PLLP_OUT0                   _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_CLK_SRC_PLLC_OUT0                   _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_CLK_SRC_PLLM_OUT0                   _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_CLK_SRC_CLK_M                       _MK_ENUM_CONST(3)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0                  _MK_ADDR_CONST(0x180)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_WORD_COUNT                       0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_RESET_MASK                       _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_READ_MASK                        _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_WRITE_MASK                       _MK_MASK_CONST(0xc00000ff)
+//  00 = pllM_out0
+//  01 = pllC_out0
+//  10 = pllP_out0
+//  11 = pllA_out0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_SRC_SHIFT                     _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_SRC_FIELD                     (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_SRC_RANGE                     31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_SRC_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_SRC_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_SRC_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_SRC_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_SRC_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_SRC_INIT_ENUM                 PLLM_OUT0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_SRC_PLLM_OUT0                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_SRC_PLLC_OUT0                 _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_SRC_PLLP_OUT0                 _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_SRC_PLLA_OUT0                 _MK_ENUM_CONST(3)
+
+//  N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_DIVISOR_SHIFT                 _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_DIVISOR_FIELD                 (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_DIVISOR_RANGE                 7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_DIVISOR_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_DIVISOR_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_DIVISOR_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_DIVISOR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_DIVISOR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Reserved address 388 [0x184] 
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0                     _MK_ADDR_CONST(0x188)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_WORD_COUNT                  0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_RESET_MASK                  _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_READ_MASK                   _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_WRITE_MASK                  _MK_MASK_CONST(0xc00000ff)
+//  00 = pllP_out0
+//  01 = pllD_out0
+//  10 = pllC_out0
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_TVO_CLK_SRC_SHIFT                   _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_TVO_CLK_SRC_FIELD                   (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_TVO_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_TVO_CLK_SRC_RANGE                   31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_TVO_CLK_SRC_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_TVO_CLK_SRC_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_TVO_CLK_SRC_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_TVO_CLK_SRC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_TVO_CLK_SRC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_TVO_CLK_SRC_INIT_ENUM                       PLLP_OUT0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_TVO_CLK_SRC_PLLP_OUT0                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_TVO_CLK_SRC_PLLD_OUT0                       _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_TVO_CLK_SRC_PLLC_OUT0                       _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_TVO_CLK_SRC_CLK_M                   _MK_ENUM_CONST(3)
+
+//  N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_TVO_CLK_DIVISOR_SHIFT                       _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_TVO_CLK_DIVISOR_FIELD                       (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_TVO_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_TVO_CLK_DIVISOR_RANGE                       7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_TVO_CLK_DIVISOR_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_TVO_CLK_DIVISOR_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_TVO_CLK_DIVISOR_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_TVO_CLK_DIVISOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_TVO_CLK_DIVISOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0                    _MK_ADDR_CONST(0x18c)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0_WORD_COUNT                         0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0_RESET_MASK                         _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0_READ_MASK                  _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0_WRITE_MASK                         _MK_MASK_CONST(0xc00000ff)
+//  00 = pllP_out0
+//  01 = pllD_out0
+//  10 = pllC_out0
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0_HDMI_CLK_SRC_SHIFT                 _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0_HDMI_CLK_SRC_FIELD                 (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0_HDMI_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0_HDMI_CLK_SRC_RANGE                 31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0_HDMI_CLK_SRC_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0_HDMI_CLK_SRC_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0_HDMI_CLK_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0_HDMI_CLK_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0_HDMI_CLK_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0_HDMI_CLK_SRC_INIT_ENUM                     PLLP_OUT0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0_HDMI_CLK_SRC_PLLP_OUT0                     _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0_HDMI_CLK_SRC_PLLD_OUT0                     _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0_HDMI_CLK_SRC_PLLC_OUT0                     _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0_HDMI_CLK_SRC_CLK_M                 _MK_ENUM_CONST(3)
+
+//  N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0_HDMI_CLK_DIVISOR_SHIFT                     _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0_HDMI_CLK_DIVISOR_FIELD                     (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0_HDMI_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0_HDMI_CLK_DIVISOR_RANGE                     7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0_HDMI_CLK_DIVISOR_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0_HDMI_CLK_DIVISOR_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0_HDMI_CLK_DIVISOR_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0_HDMI_CLK_DIVISOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0_HDMI_CLK_DIVISOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Reserved address 400 [0x190] 
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0                   _MK_ADDR_CONST(0x194)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_WORD_COUNT                        0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_RESET_MASK                        _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_READ_MASK                         _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_WRITE_MASK                        _MK_MASK_CONST(0xc00000ff)
+//  00 = pllP_out0
+//  01 = pllD_out0
+//  10 = pllC_out0
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_TVDAC_CLK_SRC_SHIFT                       _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_TVDAC_CLK_SRC_FIELD                       (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_TVDAC_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_TVDAC_CLK_SRC_RANGE                       31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_TVDAC_CLK_SRC_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_TVDAC_CLK_SRC_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_TVDAC_CLK_SRC_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_TVDAC_CLK_SRC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_TVDAC_CLK_SRC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_TVDAC_CLK_SRC_INIT_ENUM                   pllP_out0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_TVDAC_CLK_SRC_PLLP_OUT0                   _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_TVDAC_CLK_SRC_PLLD_OUT0                   _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_TVDAC_CLK_SRC_PLLC_OUT0                   _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_TVDAC_CLK_SRC_CLK_M                       _MK_ENUM_CONST(3)
+
+//  N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_TVDAC_CLK_DIVISOR_SHIFT                   _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_TVDAC_CLK_DIVISOR_FIELD                   (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_TVDAC_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_TVDAC_CLK_DIVISOR_RANGE                   7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_TVDAC_CLK_DIVISOR_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_TVDAC_CLK_DIVISOR_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_TVDAC_CLK_DIVISOR_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_TVDAC_CLK_DIVISOR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_TVDAC_CLK_DIVISOR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0                    _MK_ADDR_CONST(0x198)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_WORD_COUNT                         0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_RESET_MASK                         _MK_MASK_CONST(0xc000ffff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_READ_MASK                  _MK_MASK_CONST(0xc000ffff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_WRITE_MASK                         _MK_MASK_CONST(0xc000ffff)
+//  00 = pllP_out0
+//  01 = pllC_out0
+//  10 = pllM_out0
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_SRC_SHIFT                 _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_SRC_FIELD                 (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_SRC_RANGE                 31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_SRC_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_SRC_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_SRC_INIT_ENUM                     PLLP_OUT0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_SRC_PLLP_OUT0                     _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_SRC_PLLC_OUT0                     _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_SRC_PLLM_OUT0                     _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_SRC_CLK_M                 _MK_ENUM_CONST(3)
+
+//  N = Divide by (n+1) (lsb denote 1.0x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_DIVISOR_SHIFT                     _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_DIVISOR_FIELD                     (_MK_MASK_CONST(0xffff) << CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_DIVISOR_RANGE                     15:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_DIVISOR_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_DIVISOR_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_DIVISOR_DEFAULT_MASK                      _MK_MASK_CONST(0xffff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_DIVISOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_DIVISOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0                     _MK_ADDR_CONST(0x19c)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_WORD_COUNT                  0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_RESET_MASK                  _MK_MASK_CONST(0xc30000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_READ_MASK                   _MK_MASK_CONST(0xc30000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_WRITE_MASK                  _MK_MASK_CONST(0xc30000ff)
+//  00 = pllM_out0
+//  01 = pllC_out0
+//  10 = pllP_out0
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_SRC_SHIFT                        _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_SRC_FIELD                        (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_SRC_RANGE                        31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_SRC_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_SRC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_SRC_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_SRC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_SRC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_SRC_INIT_ENUM                    PLLM_OUT0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_SRC_PLLM_OUT0                    _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_SRC_PLLC_OUT0                    _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_SRC_PLLP_OUT0                    _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_SRC_CLK_M                        _MK_ENUM_CONST(3)
+
+//  1 = enable EMC 2X clock.
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_ENB_SHIFT                        _MK_SHIFT_CONST(25)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_ENB_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_ENB_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_ENB_RANGE                        25:25
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_ENB_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_ENB_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_ENB_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_ENB_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_ENB_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_ENB_INIT_ENUM                    DISABLE
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_ENB_DISABLE                      _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_ENB_ENABLE                       _MK_ENUM_CONST(1)
+
+//  1 = enable EMC 1X clock.
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_1X_CLK_ENB_SHIFT                        _MK_SHIFT_CONST(24)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_1X_CLK_ENB_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_1X_CLK_ENB_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_1X_CLK_ENB_RANGE                        24:24
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_1X_CLK_ENB_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_1X_CLK_ENB_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_1X_CLK_ENB_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_1X_CLK_ENB_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_1X_CLK_ENB_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_1X_CLK_ENB_INIT_ENUM                    DISABLE
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_1X_CLK_ENB_DISABLE                      _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_1X_CLK_ENB_ENABLE                       _MK_ENUM_CONST(1)
+
+//  N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_DIVISOR_SHIFT                    _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_DIVISOR_FIELD                    (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_DIVISOR_RANGE                    7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_DIVISOR_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_DIVISOR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_DIVISOR_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_DIVISOR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_DIVISOR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0                   _MK_ADDR_CONST(0x1a0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_WORD_COUNT                        0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_RESET_MASK                        _MK_MASK_CONST(0xc0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_READ_MASK                         _MK_MASK_CONST(0xc0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_WRITE_MASK                        _MK_MASK_CONST(0xc0000000)
+//  00 = pllP_out0
+//  01 = pllC_out0
+//  10 = pllM_out0
+//  11 = CLK_M
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_SRC_SHIFT                       _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_SRC_FIELD                       (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_SRC_RANGE                       31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_SRC_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_SRC_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_SRC_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_SRC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_SRC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_SRC_INIT_ENUM                   PLLP_OUT0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_SRC_PLLP_OUT0                   _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_SRC_PLLC_OUT0                   _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_SRC_PLLM_OUT0                   _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_SRC_CLK_M                       _MK_ENUM_CONST(3)
+
+
+// Reserved address 420 [0x1a4] 
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0                       _MK_ADDR_CONST(0x1a8)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_WORD_COUNT                    0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_RESET_MASK                    _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_READ_MASK                     _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_WRITE_MASK                    _MK_MASK_CONST(0xc00000ff)
+//  00 = pllM_out0
+//  01 = pllC_out0
+//  10 = pllP_out0
+//  11 = pllA_out0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_VI_SENSOR_CLK_SRC_SHIFT                       _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_VI_SENSOR_CLK_SRC_FIELD                       (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_VI_SENSOR_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_VI_SENSOR_CLK_SRC_RANGE                       31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_VI_SENSOR_CLK_SRC_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_VI_SENSOR_CLK_SRC_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_VI_SENSOR_CLK_SRC_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_VI_SENSOR_CLK_SRC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_VI_SENSOR_CLK_SRC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_VI_SENSOR_CLK_SRC_INIT_ENUM                   PLLM_OUT0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_VI_SENSOR_CLK_SRC_PLLM_OUT0                   _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_VI_SENSOR_CLK_SRC_PLLC_OUT0                   _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_VI_SENSOR_CLK_SRC_PLLP_OUT0                   _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_VI_SENSOR_CLK_SRC_PLLA_OUT0                   _MK_ENUM_CONST(3)
+
+//  N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_VI_SENSOR_CLK_DIVISOR_SHIFT                   _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_VI_SENSOR_CLK_DIVISOR_FIELD                   (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_VI_SENSOR_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_VI_SENSOR_CLK_DIVISOR_RANGE                   7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_VI_SENSOR_CLK_DIVISOR_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_VI_SENSOR_CLK_DIVISOR_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_VI_SENSOR_CLK_DIVISOR_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_VI_SENSOR_CLK_DIVISOR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_VI_SENSOR_CLK_DIVISOR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_MPE_AUDIO_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_AUDIO_0                       _MK_ADDR_CONST(0x1ac)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_AUDIO_0_WORD_COUNT                    0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_AUDIO_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_AUDIO_0_RESET_MASK                    _MK_MASK_CONST(0x70000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_AUDIO_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_AUDIO_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_AUDIO_0_READ_MASK                     _MK_MASK_CONST(0x70000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_AUDIO_0_WRITE_MASK                    _MK_MASK_CONST(0x70000000)
+// 000 = SPDIFIN recovered bit clock.
+// 001 = I2S1 bit clock.
+// 010 = I2S2 bit clock.
+// 011 = AC97 bit clock.
+// 100 = pllA_out0.
+// 101 = external audio clock in (dap_mclk2).
+// 110 = external audio clock in (dap_mclk1).
+// 111 = external vimclk (vimclk).
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_AUDIO_0_MPE_AUDIO_CLK_SRC_SHIFT                       _MK_SHIFT_CONST(28)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_AUDIO_0_MPE_AUDIO_CLK_SRC_FIELD                       (_MK_MASK_CONST(0x7) << CLK_RST_CONTROLLER_CLK_SOURCE_MPE_AUDIO_0_MPE_AUDIO_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_AUDIO_0_MPE_AUDIO_CLK_SRC_RANGE                       30:28
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_AUDIO_0_MPE_AUDIO_CLK_SRC_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_AUDIO_0_MPE_AUDIO_CLK_SRC_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_AUDIO_0_MPE_AUDIO_CLK_SRC_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_AUDIO_0_MPE_AUDIO_CLK_SRC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_AUDIO_0_MPE_AUDIO_CLK_SRC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_AUDIO_0_MPE_AUDIO_CLK_SRC_INIT_ENUM                   SPDIFIN
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_AUDIO_0_MPE_AUDIO_CLK_SRC_SPDIFIN                     _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_AUDIO_0_MPE_AUDIO_CLK_SRC_I2S1                        _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_AUDIO_0_MPE_AUDIO_CLK_SRC_I2S2                        _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_AUDIO_0_MPE_AUDIO_CLK_SRC_AC97                        _MK_ENUM_CONST(3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_AUDIO_0_MPE_AUDIO_CLK_SRC_PLLA_OUT0                   _MK_ENUM_CONST(4)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_AUDIO_0_MPE_AUDIO_CLK_SRC_EXT_AUDIO_CLK2                      _MK_ENUM_CONST(5)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_AUDIO_0_MPE_AUDIO_CLK_SRC_EXT_AUDIO_CLK1                      _MK_ENUM_CONST(6)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_AUDIO_0_MPE_AUDIO_CLK_SRC_EXT_VIMCLK                  _MK_ENUM_CONST(7)
+
+
+//
+// REGISTER LIST
+//
+#define LIST_ARCLK_RST_REGS(_op_) \
+_op_(CLK_RST_CONTROLLER_RST_SOURCE_0) \
+_op_(CLK_RST_CONTROLLER_RST_DEVICES_L_0) \
+_op_(CLK_RST_CONTROLLER_RST_DEVICES_H_0) \
+_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0) \
+_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0) \
+_op_(CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0) \
+_op_(CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0) \
+_op_(CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0) \
+_op_(CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0) \
+_op_(CLK_RST_CONTROLLER_PROG_DLY_CLK_0) \
+_op_(CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0) \
+_op_(CLK_RST_CONTROLLER_CLK_MASK_ARM_0) \
+_op_(CLK_RST_CONTROLLER_MISC_CLK_ENB_0) \
+_op_(CLK_RST_CONTROLLER_OSC_CTRL_0) \
+_op_(CLK_RST_CONTROLLER_PLL_LFSR_0) \
+_op_(CLK_RST_CONTROLLER_OSC_FREQ_DET_0) \
+_op_(CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0) \
+_op_(CLK_RST_CONTROLLER_BOND_OUT_L_0) \
+_op_(CLK_RST_CONTROLLER_BOND_OUT_H_0) \
+_op_(CLK_RST_CONTROLLER_PLLC_BASE_0) \
+_op_(CLK_RST_CONTROLLER_PLLC_OUT_0) \
+_op_(CLK_RST_CONTROLLER_PLLC_MISC_0) \
+_op_(CLK_RST_CONTROLLER_PLLM_BASE_0) \
+_op_(CLK_RST_CONTROLLER_PLLM_OUT_0) \
+_op_(CLK_RST_CONTROLLER_PLLM_MISC_0) \
+_op_(CLK_RST_CONTROLLER_PLLP_BASE_0) \
+_op_(CLK_RST_CONTROLLER_PLLP_OUTA_0) \
+_op_(CLK_RST_CONTROLLER_PLLP_OUTB_0) \
+_op_(CLK_RST_CONTROLLER_PLLP_MISC_0) \
+_op_(CLK_RST_CONTROLLER_PLLA_BASE_0) \
+_op_(CLK_RST_CONTROLLER_PLLA_OUT_0) \
+_op_(CLK_RST_CONTROLLER_PLLA_MISC_0) \
+_op_(CLK_RST_CONTROLLER_PLLU_BASE_0) \
+_op_(CLK_RST_CONTROLLER_PLLU_MISC_0) \
+_op_(CLK_RST_CONTROLLER_PLLD_BASE_0) \
+_op_(CLK_RST_CONTROLLER_PLLD_MISC_0) \
+_op_(CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0) \
+_op_(CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_SLC1_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_DISP1_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_DISP2_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_VI_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_MEM_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_SDIO1_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_SDIO2_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_HSMMC_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_MPE_AUDIO_0)
+
+
+//
+// ADDRESS SPACES
+//
+
+#define BASE_ADDRESS_CLK_RST_CONTROLLER 0x00000000
+
+//
+// ARCLK_RST REGISTER BANKS
+//
+
+#define CLK_RST_CONTROLLER0_FIRST_REG 0x0000 // CLK_RST_CONTROLLER_RST_SOURCE_0
+#define CLK_RST_CONTROLLER0_LAST_REG 0x0008 // CLK_RST_CONTROLLER_RST_DEVICES_H_0
+#define CLK_RST_CONTROLLER1_FIRST_REG 0x0010 // CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0
+#define CLK_RST_CONTROLLER1_LAST_REG 0x0014 // CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0
+#define CLK_RST_CONTROLLER2_FIRST_REG 0x0020 // CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0
+#define CLK_RST_CONTROLLER2_LAST_REG 0x0034 // CLK_RST_CONTROLLER_PROG_DLY_CLK_0
+#define CLK_RST_CONTROLLER3_FIRST_REG 0x0040 // CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0
+#define CLK_RST_CONTROLLER3_LAST_REG 0x0048 // CLK_RST_CONTROLLER_MISC_CLK_ENB_0
+#define CLK_RST_CONTROLLER4_FIRST_REG 0x0050 // CLK_RST_CONTROLLER_OSC_CTRL_0
+#define CLK_RST_CONTROLLER4_LAST_REG 0x005c // CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0
+#define CLK_RST_CONTROLLER5_FIRST_REG 0x0070 // CLK_RST_CONTROLLER_BOND_OUT_L_0
+#define CLK_RST_CONTROLLER5_LAST_REG 0x0074 // CLK_RST_CONTROLLER_BOND_OUT_H_0
+#define CLK_RST_CONTROLLER6_FIRST_REG 0x0080 // CLK_RST_CONTROLLER_PLLC_BASE_0
+#define CLK_RST_CONTROLLER6_LAST_REG 0x0084 // CLK_RST_CONTROLLER_PLLC_OUT_0
+#define CLK_RST_CONTROLLER7_FIRST_REG 0x008c // CLK_RST_CONTROLLER_PLLC_MISC_0
+#define CLK_RST_CONTROLLER7_LAST_REG 0x0094 // CLK_RST_CONTROLLER_PLLM_OUT_0
+#define CLK_RST_CONTROLLER8_FIRST_REG 0x009c // CLK_RST_CONTROLLER_PLLM_MISC_0
+#define CLK_RST_CONTROLLER8_LAST_REG 0x00b4 // CLK_RST_CONTROLLER_PLLA_OUT_0
+#define CLK_RST_CONTROLLER9_FIRST_REG 0x00bc // CLK_RST_CONTROLLER_PLLA_MISC_0
+#define CLK_RST_CONTROLLER9_LAST_REG 0x00c0 // CLK_RST_CONTROLLER_PLLU_BASE_0
+#define CLK_RST_CONTROLLER10_FIRST_REG 0x00cc // CLK_RST_CONTROLLER_PLLU_MISC_0
+#define CLK_RST_CONTROLLER10_LAST_REG 0x00d0 // CLK_RST_CONTROLLER_PLLD_BASE_0
+#define CLK_RST_CONTROLLER11_FIRST_REG 0x00dc // CLK_RST_CONTROLLER_PLLD_MISC_0
+#define CLK_RST_CONTROLLER11_LAST_REG 0x00dc // CLK_RST_CONTROLLER_PLLD_MISC_0
+#define CLK_RST_CONTROLLER12_FIRST_REG 0x00f0 // CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0
+#define CLK_RST_CONTROLLER12_LAST_REG 0x00f4 // CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0
+#define CLK_RST_CONTROLLER13_FIRST_REG 0x0100 // CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0
+#define CLK_RST_CONTROLLER13_LAST_REG 0x0108 // CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0
+#define CLK_RST_CONTROLLER14_FIRST_REG 0x0110 // CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0
+#define CLK_RST_CONTROLLER14_LAST_REG 0x0180 // CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0
+#define CLK_RST_CONTROLLER15_FIRST_REG 0x0188 // CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0
+#define CLK_RST_CONTROLLER15_LAST_REG 0x018c // CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0
+#define CLK_RST_CONTROLLER16_FIRST_REG 0x0194 // CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0
+#define CLK_RST_CONTROLLER16_LAST_REG 0x01a0 // CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0
+#define CLK_RST_CONTROLLER17_FIRST_REG 0x01a8 // CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0
+#define CLK_RST_CONTROLLER17_LAST_REG 0x01ac // CLK_RST_CONTROLLER_CLK_SOURCE_MPE_AUDIO_0
+
+#ifndef _MK_SHIFT_CONST
+  #define _MK_SHIFT_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_MASK_CONST
+  #define _MK_MASK_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_ENUM_CONST
+  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
+#endif
+#ifndef _MK_ADDR_CONST
+  #define _MK_ADDR_CONST(_constant_) _constant_
+#endif
+
+#endif // ifndef ___ARCLK_RST_H_INC_
diff --git a/arch/arm/mach-tegra/include/ap15/aremc.h b/arch/arm/mach-tegra/include/ap15/aremc.h
new file mode 100644
index 000000000000..ba241d0e1a47
--- /dev/null
+++ b/arch/arm/mach-tegra/include/ap15/aremc.h
@@ -0,0 +1,4381 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+//
+// DO NOT EDIT - generated by simspec!
+//
+
+#ifndef ___AREMC_H_INC_
+#define ___AREMC_H_INC_
+#define EMC_FBIO_DATA_MAX       31
+#define EMC_FBIO_DATA_WIDTH     32
+#define EMC_FBIO_DOE_MAX        3
+#define EMC_FBIO_DOE_WIDTH      4
+
+// Register EMC_INTSTATUS_0  
+#define EMC_INTSTATUS_0                 _MK_ADDR_CONST(0x0)
+#define EMC_INTSTATUS_0_WORD_COUNT                      0x1
+#define EMC_INTSTATUS_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define EMC_INTSTATUS_0_RESET_MASK                      _MK_MASK_CONST(0x4)
+#define EMC_INTSTATUS_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EMC_INTSTATUS_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_INTSTATUS_0_READ_MASK                       _MK_MASK_CONST(0x4)
+#define EMC_INTSTATUS_0_WRITE_MASK                      _MK_MASK_CONST(0x4)
+// NOR/MIO mux request timeout
+#define EMC_INTSTATUS_0_NOR_TIMEOUT_INT_SHIFT                   _MK_SHIFT_CONST(2)
+#define EMC_INTSTATUS_0_NOR_TIMEOUT_INT_FIELD                   (_MK_MASK_CONST(0x1) << EMC_INTSTATUS_0_NOR_TIMEOUT_INT_SHIFT)
+#define EMC_INTSTATUS_0_NOR_TIMEOUT_INT_RANGE                   2:2
+#define EMC_INTSTATUS_0_NOR_TIMEOUT_INT_WOFFSET                 0x0
+#define EMC_INTSTATUS_0_NOR_TIMEOUT_INT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_INTSTATUS_0_NOR_TIMEOUT_INT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define EMC_INTSTATUS_0_NOR_TIMEOUT_INT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_INTSTATUS_0_NOR_TIMEOUT_INT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define EMC_INTSTATUS_0_NOR_TIMEOUT_INT_INIT_ENUM                       CLEAR
+#define EMC_INTSTATUS_0_NOR_TIMEOUT_INT_CLEAR                   _MK_ENUM_CONST(0)
+#define EMC_INTSTATUS_0_NOR_TIMEOUT_INT_SET                     _MK_ENUM_CONST(1)
+
+
+// Register EMC_INTMASK_0  
+#define EMC_INTMASK_0                   _MK_ADDR_CONST(0x4)
+#define EMC_INTMASK_0_WORD_COUNT                        0x1
+#define EMC_INTMASK_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define EMC_INTMASK_0_RESET_MASK                        _MK_MASK_CONST(0x4)
+#define EMC_INTMASK_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define EMC_INTMASK_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_INTMASK_0_READ_MASK                         _MK_MASK_CONST(0x4)
+#define EMC_INTMASK_0_WRITE_MASK                        _MK_MASK_CONST(0x4)
+// NOR/MIO mux request timeout
+#define EMC_INTMASK_0_NOR_TIMEOUT_INTMASK_SHIFT                 _MK_SHIFT_CONST(2)
+#define EMC_INTMASK_0_NOR_TIMEOUT_INTMASK_FIELD                 (_MK_MASK_CONST(0x1) << EMC_INTMASK_0_NOR_TIMEOUT_INTMASK_SHIFT)
+#define EMC_INTMASK_0_NOR_TIMEOUT_INTMASK_RANGE                 2:2
+#define EMC_INTMASK_0_NOR_TIMEOUT_INTMASK_WOFFSET                       0x0
+#define EMC_INTMASK_0_NOR_TIMEOUT_INTMASK_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_INTMASK_0_NOR_TIMEOUT_INTMASK_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define EMC_INTMASK_0_NOR_TIMEOUT_INTMASK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_INTMASK_0_NOR_TIMEOUT_INTMASK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_INTMASK_0_NOR_TIMEOUT_INTMASK_INIT_ENUM                     MASKED
+#define EMC_INTMASK_0_NOR_TIMEOUT_INTMASK_MASKED                        _MK_ENUM_CONST(0)
+#define EMC_INTMASK_0_NOR_TIMEOUT_INTMASK_UNMASKED                      _MK_ENUM_CONST(1)
+
+
+// Register EMC_DBG_0  // Debug Register
+#define EMC_DBG_0                       _MK_ADDR_CONST(0x8)
+#define EMC_DBG_0_WORD_COUNT                    0x1
+#define EMC_DBG_0_RESET_VAL                     _MK_MASK_CONST(0x1000400)
+#define EMC_DBG_0_RESET_MASK                    _MK_MASK_CONST(0x1000637)
+#define EMC_DBG_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define EMC_DBG_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_DBG_0_READ_MASK                     _MK_MASK_CONST(0x1000637)
+#define EMC_DBG_0_WRITE_MASK                    _MK_MASK_CONST(0x1000637)
+#define EMC_DBG_0_READ_MUX_SHIFT                        _MK_SHIFT_CONST(0)
+#define EMC_DBG_0_READ_MUX_FIELD                        (_MK_MASK_CONST(0x1) << EMC_DBG_0_READ_MUX_SHIFT)
+#define EMC_DBG_0_READ_MUX_RANGE                        0:0
+#define EMC_DBG_0_READ_MUX_WOFFSET                      0x0
+#define EMC_DBG_0_READ_MUX_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_DBG_0_READ_MUX_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define EMC_DBG_0_READ_MUX_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_DBG_0_READ_MUX_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_DBG_0_READ_MUX_INIT_ENUM                    ACTIVE
+#define EMC_DBG_0_READ_MUX_ACTIVE                       _MK_ENUM_CONST(0)
+#define EMC_DBG_0_READ_MUX_ASSEMBLY                     _MK_ENUM_CONST(1)
+
+#define EMC_DBG_0_WRITE_MUX_SHIFT                       _MK_SHIFT_CONST(1)
+#define EMC_DBG_0_WRITE_MUX_FIELD                       (_MK_MASK_CONST(0x1) << EMC_DBG_0_WRITE_MUX_SHIFT)
+#define EMC_DBG_0_WRITE_MUX_RANGE                       1:1
+#define EMC_DBG_0_WRITE_MUX_WOFFSET                     0x0
+#define EMC_DBG_0_WRITE_MUX_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_DBG_0_WRITE_MUX_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define EMC_DBG_0_WRITE_MUX_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_DBG_0_WRITE_MUX_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EMC_DBG_0_WRITE_MUX_INIT_ENUM                   ASSEMBLY
+#define EMC_DBG_0_WRITE_MUX_ASSEMBLY                    _MK_ENUM_CONST(0)
+#define EMC_DBG_0_WRITE_MUX_ACTIVE                      _MK_ENUM_CONST(1)
+
+#define EMC_DBG_0_FORCE_UPDATE_SHIFT                    _MK_SHIFT_CONST(2)
+#define EMC_DBG_0_FORCE_UPDATE_FIELD                    (_MK_MASK_CONST(0x1) << EMC_DBG_0_FORCE_UPDATE_SHIFT)
+#define EMC_DBG_0_FORCE_UPDATE_RANGE                    2:2
+#define EMC_DBG_0_FORCE_UPDATE_WOFFSET                  0x0
+#define EMC_DBG_0_FORCE_UPDATE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_DBG_0_FORCE_UPDATE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define EMC_DBG_0_FORCE_UPDATE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_DBG_0_FORCE_UPDATE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_DBG_0_FORCE_UPDATE_INIT_ENUM                        DISABLED
+#define EMC_DBG_0_FORCE_UPDATE_DISABLED                 _MK_ENUM_CONST(0)
+#define EMC_DBG_0_FORCE_UPDATE_ENABLED                  _MK_ENUM_CONST(1)
+
+#define EMC_DBG_0_MRS_WAIT_SHIFT                        _MK_SHIFT_CONST(4)
+#define EMC_DBG_0_MRS_WAIT_FIELD                        (_MK_MASK_CONST(0x1) << EMC_DBG_0_MRS_WAIT_SHIFT)
+#define EMC_DBG_0_MRS_WAIT_RANGE                        4:4
+#define EMC_DBG_0_MRS_WAIT_WOFFSET                      0x0
+#define EMC_DBG_0_MRS_WAIT_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_DBG_0_MRS_WAIT_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define EMC_DBG_0_MRS_WAIT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_DBG_0_MRS_WAIT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_DBG_0_MRS_WAIT_INIT_ENUM                    MRS_2
+#define EMC_DBG_0_MRS_WAIT_MRS_2                        _MK_ENUM_CONST(0)
+#define EMC_DBG_0_MRS_WAIT_MRS_256                      _MK_ENUM_CONST(1)
+
+#define EMC_DBG_0_PERIODIC_QRST_SHIFT                   _MK_SHIFT_CONST(5)
+#define EMC_DBG_0_PERIODIC_QRST_FIELD                   (_MK_MASK_CONST(0x1) << EMC_DBG_0_PERIODIC_QRST_SHIFT)
+#define EMC_DBG_0_PERIODIC_QRST_RANGE                   5:5
+#define EMC_DBG_0_PERIODIC_QRST_WOFFSET                 0x0
+#define EMC_DBG_0_PERIODIC_QRST_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_DBG_0_PERIODIC_QRST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define EMC_DBG_0_PERIODIC_QRST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_DBG_0_PERIODIC_QRST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define EMC_DBG_0_PERIODIC_QRST_INIT_ENUM                       DISABLED
+#define EMC_DBG_0_PERIODIC_QRST_DISABLED                        _MK_ENUM_CONST(0)
+#define EMC_DBG_0_PERIODIC_QRST_ENABLED                 _MK_ENUM_CONST(1)
+
+#define EMC_DBG_0_READ_DQM_CTRL_SHIFT                   _MK_SHIFT_CONST(9)
+#define EMC_DBG_0_READ_DQM_CTRL_FIELD                   (_MK_MASK_CONST(0x1) << EMC_DBG_0_READ_DQM_CTRL_SHIFT)
+#define EMC_DBG_0_READ_DQM_CTRL_RANGE                   9:9
+#define EMC_DBG_0_READ_DQM_CTRL_WOFFSET                 0x0
+#define EMC_DBG_0_READ_DQM_CTRL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_DBG_0_READ_DQM_CTRL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define EMC_DBG_0_READ_DQM_CTRL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_DBG_0_READ_DQM_CTRL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define EMC_DBG_0_READ_DQM_CTRL_INIT_ENUM                       MANAGED
+#define EMC_DBG_0_READ_DQM_CTRL_MANAGED                 _MK_ENUM_CONST(0)
+#define EMC_DBG_0_READ_DQM_CTRL_ALWAYS_ON                       _MK_ENUM_CONST(1)
+
+#define EMC_DBG_0_AP_REQ_BUSY_CTRL_SHIFT                        _MK_SHIFT_CONST(10)
+#define EMC_DBG_0_AP_REQ_BUSY_CTRL_FIELD                        (_MK_MASK_CONST(0x1) << EMC_DBG_0_AP_REQ_BUSY_CTRL_SHIFT)
+#define EMC_DBG_0_AP_REQ_BUSY_CTRL_RANGE                        10:10
+#define EMC_DBG_0_AP_REQ_BUSY_CTRL_WOFFSET                      0x0
+#define EMC_DBG_0_AP_REQ_BUSY_CTRL_DEFAULT                      _MK_MASK_CONST(0x1)
+#define EMC_DBG_0_AP_REQ_BUSY_CTRL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define EMC_DBG_0_AP_REQ_BUSY_CTRL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_DBG_0_AP_REQ_BUSY_CTRL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_DBG_0_AP_REQ_BUSY_CTRL_INIT_ENUM                    ENABLED
+#define EMC_DBG_0_AP_REQ_BUSY_CTRL_DISABLED                     _MK_ENUM_CONST(0)
+#define EMC_DBG_0_AP_REQ_BUSY_CTRL_ENABLED                      _MK_ENUM_CONST(1)
+
+#define EMC_DBG_0_CFG_PRIORITY_SHIFT                    _MK_SHIFT_CONST(24)
+#define EMC_DBG_0_CFG_PRIORITY_FIELD                    (_MK_MASK_CONST(0x1) << EMC_DBG_0_CFG_PRIORITY_SHIFT)
+#define EMC_DBG_0_CFG_PRIORITY_RANGE                    24:24
+#define EMC_DBG_0_CFG_PRIORITY_WOFFSET                  0x0
+#define EMC_DBG_0_CFG_PRIORITY_DEFAULT                  _MK_MASK_CONST(0x1)
+#define EMC_DBG_0_CFG_PRIORITY_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define EMC_DBG_0_CFG_PRIORITY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_DBG_0_CFG_PRIORITY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_DBG_0_CFG_PRIORITY_INIT_ENUM                        ENABLED
+#define EMC_DBG_0_CFG_PRIORITY_DISABLED                 _MK_ENUM_CONST(0)
+#define EMC_DBG_0_CFG_PRIORITY_ENABLED                  _MK_ENUM_CONST(1)
+
+
+// Register EMC_CFG_0  // Configuration Register
+#define EMC_CFG_0                       _MK_ADDR_CONST(0xc)
+#define EMC_CFG_0_WORD_COUNT                    0x1
+#define EMC_CFG_0_RESET_VAL                     _MK_MASK_CONST(0x300ff00)
+#define EMC_CFG_0_RESET_MASK                    _MK_MASK_CONST(0xa301ff01)
+#define EMC_CFG_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define EMC_CFG_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_CFG_0_READ_MASK                     _MK_MASK_CONST(0xa301ff01)
+#define EMC_CFG_0_WRITE_MASK                    _MK_MASK_CONST(0xa301ff01)
+#define EMC_CFG_0_PRE_IDLE_EN_SHIFT                     _MK_SHIFT_CONST(0)
+#define EMC_CFG_0_PRE_IDLE_EN_FIELD                     (_MK_MASK_CONST(0x1) << EMC_CFG_0_PRE_IDLE_EN_SHIFT)
+#define EMC_CFG_0_PRE_IDLE_EN_RANGE                     0:0
+#define EMC_CFG_0_PRE_IDLE_EN_WOFFSET                   0x0
+#define EMC_CFG_0_PRE_IDLE_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_CFG_0_PRE_IDLE_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define EMC_CFG_0_PRE_IDLE_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_CFG_0_PRE_IDLE_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_CFG_0_PRE_IDLE_EN_INIT_ENUM                 DISABLED
+#define EMC_CFG_0_PRE_IDLE_EN_DISABLED                  _MK_ENUM_CONST(0)
+#define EMC_CFG_0_PRE_IDLE_EN_ENABLED                   _MK_ENUM_CONST(1)
+
+#define EMC_CFG_0_PRE_IDLE_CYCLES_SHIFT                 _MK_SHIFT_CONST(8)
+#define EMC_CFG_0_PRE_IDLE_CYCLES_FIELD                 (_MK_MASK_CONST(0xff) << EMC_CFG_0_PRE_IDLE_CYCLES_SHIFT)
+#define EMC_CFG_0_PRE_IDLE_CYCLES_RANGE                 15:8
+#define EMC_CFG_0_PRE_IDLE_CYCLES_WOFFSET                       0x0
+#define EMC_CFG_0_PRE_IDLE_CYCLES_DEFAULT                       _MK_MASK_CONST(0xff)
+#define EMC_CFG_0_PRE_IDLE_CYCLES_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define EMC_CFG_0_PRE_IDLE_CYCLES_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_CFG_0_PRE_IDLE_CYCLES_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define EMC_CFG_0_CLEAR_AP_PREV_SPREQ_SHIFT                     _MK_SHIFT_CONST(16)
+#define EMC_CFG_0_CLEAR_AP_PREV_SPREQ_FIELD                     (_MK_MASK_CONST(0x1) << EMC_CFG_0_CLEAR_AP_PREV_SPREQ_SHIFT)
+#define EMC_CFG_0_CLEAR_AP_PREV_SPREQ_RANGE                     16:16
+#define EMC_CFG_0_CLEAR_AP_PREV_SPREQ_WOFFSET                   0x0
+#define EMC_CFG_0_CLEAR_AP_PREV_SPREQ_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_CFG_0_CLEAR_AP_PREV_SPREQ_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define EMC_CFG_0_CLEAR_AP_PREV_SPREQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_CFG_0_CLEAR_AP_PREV_SPREQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_CFG_0_CLEAR_AP_PREV_SPREQ_INIT_ENUM                 DISABLED
+#define EMC_CFG_0_CLEAR_AP_PREV_SPREQ_DISABLED                  _MK_ENUM_CONST(0)
+#define EMC_CFG_0_CLEAR_AP_PREV_SPREQ_ENABLED                   _MK_ENUM_CONST(1)
+
+#define EMC_CFG_0_AUTO_PRE_RD_SHIFT                     _MK_SHIFT_CONST(24)
+#define EMC_CFG_0_AUTO_PRE_RD_FIELD                     (_MK_MASK_CONST(0x1) << EMC_CFG_0_AUTO_PRE_RD_SHIFT)
+#define EMC_CFG_0_AUTO_PRE_RD_RANGE                     24:24
+#define EMC_CFG_0_AUTO_PRE_RD_WOFFSET                   0x0
+#define EMC_CFG_0_AUTO_PRE_RD_DEFAULT                   _MK_MASK_CONST(0x1)
+#define EMC_CFG_0_AUTO_PRE_RD_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define EMC_CFG_0_AUTO_PRE_RD_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_CFG_0_AUTO_PRE_RD_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_CFG_0_AUTO_PRE_RD_INIT_ENUM                 ENABLED
+#define EMC_CFG_0_AUTO_PRE_RD_DISABLED                  _MK_ENUM_CONST(0)
+#define EMC_CFG_0_AUTO_PRE_RD_ENABLED                   _MK_ENUM_CONST(1)
+
+#define EMC_CFG_0_AUTO_PRE_WR_SHIFT                     _MK_SHIFT_CONST(25)
+#define EMC_CFG_0_AUTO_PRE_WR_FIELD                     (_MK_MASK_CONST(0x1) << EMC_CFG_0_AUTO_PRE_WR_SHIFT)
+#define EMC_CFG_0_AUTO_PRE_WR_RANGE                     25:25
+#define EMC_CFG_0_AUTO_PRE_WR_WOFFSET                   0x0
+#define EMC_CFG_0_AUTO_PRE_WR_DEFAULT                   _MK_MASK_CONST(0x1)
+#define EMC_CFG_0_AUTO_PRE_WR_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define EMC_CFG_0_AUTO_PRE_WR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_CFG_0_AUTO_PRE_WR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_CFG_0_AUTO_PRE_WR_INIT_ENUM                 ENABLED
+#define EMC_CFG_0_AUTO_PRE_WR_DISABLED                  _MK_ENUM_CONST(0)
+#define EMC_CFG_0_AUTO_PRE_WR_ENABLED                   _MK_ENUM_CONST(1)
+
+#define EMC_CFG_0_DRAM_ACPD_SHIFT                       _MK_SHIFT_CONST(29)
+#define EMC_CFG_0_DRAM_ACPD_FIELD                       (_MK_MASK_CONST(0x1) << EMC_CFG_0_DRAM_ACPD_SHIFT)
+#define EMC_CFG_0_DRAM_ACPD_RANGE                       29:29
+#define EMC_CFG_0_DRAM_ACPD_WOFFSET                     0x0
+#define EMC_CFG_0_DRAM_ACPD_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_CFG_0_DRAM_ACPD_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define EMC_CFG_0_DRAM_ACPD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_CFG_0_DRAM_ACPD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EMC_CFG_0_DRAM_ACPD_INIT_ENUM                   NO_POWERDOWN
+#define EMC_CFG_0_DRAM_ACPD_NO_POWERDOWN                        _MK_ENUM_CONST(0)
+#define EMC_CFG_0_DRAM_ACPD_ACTIVE_POWERDOWN                    _MK_ENUM_CONST(1)
+
+#define EMC_CFG_0_DRAM_CLKSTOP_SHIFT                    _MK_SHIFT_CONST(31)
+#define EMC_CFG_0_DRAM_CLKSTOP_FIELD                    (_MK_MASK_CONST(0x1) << EMC_CFG_0_DRAM_CLKSTOP_SHIFT)
+#define EMC_CFG_0_DRAM_CLKSTOP_RANGE                    31:31
+#define EMC_CFG_0_DRAM_CLKSTOP_WOFFSET                  0x0
+#define EMC_CFG_0_DRAM_CLKSTOP_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_CFG_0_DRAM_CLKSTOP_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define EMC_CFG_0_DRAM_CLKSTOP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_CFG_0_DRAM_CLKSTOP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_CFG_0_DRAM_CLKSTOP_INIT_ENUM                        DISABLED
+#define EMC_CFG_0_DRAM_CLKSTOP_DISABLED                 _MK_ENUM_CONST(0)
+#define EMC_CFG_0_DRAM_CLKSTOP_ENABLED                  _MK_ENUM_CONST(1)
+
+
+// Register EMC_ADR_CFG_0  
+#define EMC_ADR_CFG_0                   _MK_ADDR_CONST(0x10)
+#define EMC_ADR_CFG_0_WORD_COUNT                        0x1
+#define EMC_ADR_CFG_0_RESET_VAL                         _MK_MASK_CONST(0x40202)
+#define EMC_ADR_CFG_0_RESET_MASK                        _MK_MASK_CONST(0x3070307)
+#define EMC_ADR_CFG_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define EMC_ADR_CFG_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_ADR_CFG_0_READ_MASK                         _MK_MASK_CONST(0x3070307)
+#define EMC_ADR_CFG_0_WRITE_MASK                        _MK_MASK_CONST(0x3070307)
+#define EMC_ADR_CFG_0_EMEM_COLWIDTH_SHIFT                       _MK_SHIFT_CONST(0)
+#define EMC_ADR_CFG_0_EMEM_COLWIDTH_FIELD                       (_MK_MASK_CONST(0x7) << EMC_ADR_CFG_0_EMEM_COLWIDTH_SHIFT)
+#define EMC_ADR_CFG_0_EMEM_COLWIDTH_RANGE                       2:0
+#define EMC_ADR_CFG_0_EMEM_COLWIDTH_WOFFSET                     0x0
+#define EMC_ADR_CFG_0_EMEM_COLWIDTH_DEFAULT                     _MK_MASK_CONST(0x2)
+#define EMC_ADR_CFG_0_EMEM_COLWIDTH_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
+#define EMC_ADR_CFG_0_EMEM_COLWIDTH_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_ADR_CFG_0_EMEM_COLWIDTH_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EMC_ADR_CFG_0_EMEM_COLWIDTH_INIT_ENUM                   W9
+#define EMC_ADR_CFG_0_EMEM_COLWIDTH_W7                  _MK_ENUM_CONST(0)
+#define EMC_ADR_CFG_0_EMEM_COLWIDTH_W8                  _MK_ENUM_CONST(1)
+#define EMC_ADR_CFG_0_EMEM_COLWIDTH_W9                  _MK_ENUM_CONST(2)
+#define EMC_ADR_CFG_0_EMEM_COLWIDTH_W10                 _MK_ENUM_CONST(3)
+#define EMC_ADR_CFG_0_EMEM_COLWIDTH_W11                 _MK_ENUM_CONST(4)
+
+#define EMC_ADR_CFG_0_EMEM_BANKWIDTH_SHIFT                      _MK_SHIFT_CONST(8)
+#define EMC_ADR_CFG_0_EMEM_BANKWIDTH_FIELD                      (_MK_MASK_CONST(0x3) << EMC_ADR_CFG_0_EMEM_BANKWIDTH_SHIFT)
+#define EMC_ADR_CFG_0_EMEM_BANKWIDTH_RANGE                      9:8
+#define EMC_ADR_CFG_0_EMEM_BANKWIDTH_WOFFSET                    0x0
+#define EMC_ADR_CFG_0_EMEM_BANKWIDTH_DEFAULT                    _MK_MASK_CONST(0x2)
+#define EMC_ADR_CFG_0_EMEM_BANKWIDTH_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define EMC_ADR_CFG_0_EMEM_BANKWIDTH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_ADR_CFG_0_EMEM_BANKWIDTH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_ADR_CFG_0_EMEM_BANKWIDTH_INIT_ENUM                  W2
+#define EMC_ADR_CFG_0_EMEM_BANKWIDTH_W1                 _MK_ENUM_CONST(1)
+#define EMC_ADR_CFG_0_EMEM_BANKWIDTH_W2                 _MK_ENUM_CONST(2)
+#define EMC_ADR_CFG_0_EMEM_BANKWIDTH_W3                 _MK_ENUM_CONST(3)
+
+#define EMC_ADR_CFG_0_EMEM_DEVSIZE_SHIFT                        _MK_SHIFT_CONST(16)
+#define EMC_ADR_CFG_0_EMEM_DEVSIZE_FIELD                        (_MK_MASK_CONST(0x7) << EMC_ADR_CFG_0_EMEM_DEVSIZE_SHIFT)
+#define EMC_ADR_CFG_0_EMEM_DEVSIZE_RANGE                        18:16
+#define EMC_ADR_CFG_0_EMEM_DEVSIZE_WOFFSET                      0x0
+#define EMC_ADR_CFG_0_EMEM_DEVSIZE_DEFAULT                      _MK_MASK_CONST(0x4)
+#define EMC_ADR_CFG_0_EMEM_DEVSIZE_DEFAULT_MASK                 _MK_MASK_CONST(0x7)
+#define EMC_ADR_CFG_0_EMEM_DEVSIZE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_ADR_CFG_0_EMEM_DEVSIZE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_ADR_CFG_0_EMEM_DEVSIZE_INIT_ENUM                    D64MB
+#define EMC_ADR_CFG_0_EMEM_DEVSIZE_D4MB                 _MK_ENUM_CONST(0)
+#define EMC_ADR_CFG_0_EMEM_DEVSIZE_D8MB                 _MK_ENUM_CONST(1)
+#define EMC_ADR_CFG_0_EMEM_DEVSIZE_D16MB                        _MK_ENUM_CONST(2)
+#define EMC_ADR_CFG_0_EMEM_DEVSIZE_D32MB                        _MK_ENUM_CONST(3)
+#define EMC_ADR_CFG_0_EMEM_DEVSIZE_D64MB                        _MK_ENUM_CONST(4)
+#define EMC_ADR_CFG_0_EMEM_DEVSIZE_D128MB                       _MK_ENUM_CONST(5)
+#define EMC_ADR_CFG_0_EMEM_DEVSIZE_D256MB                       _MK_ENUM_CONST(6)
+#define EMC_ADR_CFG_0_EMEM_DEVSIZE_D512MB                       _MK_ENUM_CONST(7)
+
+#define EMC_ADR_CFG_0_EMEM_NUMDEV_SHIFT                 _MK_SHIFT_CONST(24)
+#define EMC_ADR_CFG_0_EMEM_NUMDEV_FIELD                 (_MK_MASK_CONST(0x3) << EMC_ADR_CFG_0_EMEM_NUMDEV_SHIFT)
+#define EMC_ADR_CFG_0_EMEM_NUMDEV_RANGE                 25:24
+#define EMC_ADR_CFG_0_EMEM_NUMDEV_WOFFSET                       0x0
+#define EMC_ADR_CFG_0_EMEM_NUMDEV_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_ADR_CFG_0_EMEM_NUMDEV_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define EMC_ADR_CFG_0_EMEM_NUMDEV_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_ADR_CFG_0_EMEM_NUMDEV_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_ADR_CFG_0_EMEM_NUMDEV_INIT_ENUM                     N1
+#define EMC_ADR_CFG_0_EMEM_NUMDEV_N1                    _MK_ENUM_CONST(0)
+#define EMC_ADR_CFG_0_EMEM_NUMDEV_N2                    _MK_ENUM_CONST(1)
+
+
+// Register EMC_REFCTRL_0  // Refresh Control Register
+#define EMC_REFCTRL_0                   _MK_ADDR_CONST(0x14)
+#define EMC_REFCTRL_0_WORD_COUNT                        0x1
+#define EMC_REFCTRL_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define EMC_REFCTRL_0_RESET_MASK                        _MK_MASK_CONST(0x80000000)
+#define EMC_REFCTRL_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define EMC_REFCTRL_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_REFCTRL_0_READ_MASK                         _MK_MASK_CONST(0x80000000)
+#define EMC_REFCTRL_0_WRITE_MASK                        _MK_MASK_CONST(0x80000000)
+#define EMC_REFCTRL_0_REF_VALID_SHIFT                   _MK_SHIFT_CONST(31)
+#define EMC_REFCTRL_0_REF_VALID_FIELD                   (_MK_MASK_CONST(0x1) << EMC_REFCTRL_0_REF_VALID_SHIFT)
+#define EMC_REFCTRL_0_REF_VALID_RANGE                   31:31
+#define EMC_REFCTRL_0_REF_VALID_WOFFSET                 0x0
+#define EMC_REFCTRL_0_REF_VALID_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_REFCTRL_0_REF_VALID_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define EMC_REFCTRL_0_REF_VALID_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_REFCTRL_0_REF_VALID_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define EMC_REFCTRL_0_REF_VALID_INIT_ENUM                       DISABLED
+#define EMC_REFCTRL_0_REF_VALID_DISABLED                        _MK_ENUM_CONST(0)
+#define EMC_REFCTRL_0_REF_VALID_ENABLED                 _MK_ENUM_CONST(1)
+
+
+// Register EMC_PIN_0  // Controls state of selected DRAM pins
+#define EMC_PIN_0                       _MK_ADDR_CONST(0x18)
+#define EMC_PIN_0_WORD_COUNT                    0x1
+#define EMC_PIN_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define EMC_PIN_0_RESET_MASK                    _MK_MASK_CONST(0x11)
+#define EMC_PIN_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define EMC_PIN_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_PIN_0_READ_MASK                     _MK_MASK_CONST(0x11)
+#define EMC_PIN_0_WRITE_MASK                    _MK_MASK_CONST(0x11)
+#define EMC_PIN_0_PIN_CKE_SHIFT                 _MK_SHIFT_CONST(0)
+#define EMC_PIN_0_PIN_CKE_FIELD                 (_MK_MASK_CONST(0x1) << EMC_PIN_0_PIN_CKE_SHIFT)
+#define EMC_PIN_0_PIN_CKE_RANGE                 0:0
+#define EMC_PIN_0_PIN_CKE_WOFFSET                       0x0
+#define EMC_PIN_0_PIN_CKE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_PIN_0_PIN_CKE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define EMC_PIN_0_PIN_CKE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_PIN_0_PIN_CKE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_PIN_0_PIN_CKE_INIT_ENUM                     POWERDOWN
+#define EMC_PIN_0_PIN_CKE_POWERDOWN                     _MK_ENUM_CONST(0)
+#define EMC_PIN_0_PIN_CKE_NORMAL                        _MK_ENUM_CONST(1)
+
+#define EMC_PIN_0_PIN_DQM_SHIFT                 _MK_SHIFT_CONST(4)
+#define EMC_PIN_0_PIN_DQM_FIELD                 (_MK_MASK_CONST(0x1) << EMC_PIN_0_PIN_DQM_SHIFT)
+#define EMC_PIN_0_PIN_DQM_RANGE                 4:4
+#define EMC_PIN_0_PIN_DQM_WOFFSET                       0x0
+#define EMC_PIN_0_PIN_DQM_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_PIN_0_PIN_DQM_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define EMC_PIN_0_PIN_DQM_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_PIN_0_PIN_DQM_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_PIN_0_PIN_DQM_INIT_ENUM                     NORMAL
+#define EMC_PIN_0_PIN_DQM_NORMAL                        _MK_ENUM_CONST(0)
+#define EMC_PIN_0_PIN_DQM_INACTIVE                      _MK_ENUM_CONST(1)
+
+
+// Register EMC_TIMING_CONTROL_0  
+#define EMC_TIMING_CONTROL_0                    _MK_ADDR_CONST(0x1c)
+#define EMC_TIMING_CONTROL_0_WORD_COUNT                         0x1
+#define EMC_TIMING_CONTROL_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define EMC_TIMING_CONTROL_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_TIMING_CONTROL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define EMC_TIMING_CONTROL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_TIMING_CONTROL_0_READ_MASK                  _MK_MASK_CONST(0x1)
+#define EMC_TIMING_CONTROL_0_WRITE_MASK                         _MK_MASK_CONST(0x1)
+#define EMC_TIMING_CONTROL_0_TIMING_UPDATE_SHIFT                        _MK_SHIFT_CONST(0)
+#define EMC_TIMING_CONTROL_0_TIMING_UPDATE_FIELD                        (_MK_MASK_CONST(0x1) << EMC_TIMING_CONTROL_0_TIMING_UPDATE_SHIFT)
+#define EMC_TIMING_CONTROL_0_TIMING_UPDATE_RANGE                        0:0
+#define EMC_TIMING_CONTROL_0_TIMING_UPDATE_WOFFSET                      0x0
+#define EMC_TIMING_CONTROL_0_TIMING_UPDATE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_TIMING_CONTROL_0_TIMING_UPDATE_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define EMC_TIMING_CONTROL_0_TIMING_UPDATE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_TIMING_CONTROL_0_TIMING_UPDATE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register EMC_TIMING0_0  // Timing Control Register 0
+#define EMC_TIMING0_0                   _MK_ADDR_CONST(0x20)
+#define EMC_TIMING0_0_WORD_COUNT                        0x1
+#define EMC_TIMING0_0_RESET_VAL                         _MK_MASK_CONST(0x3f3f3f3f)
+#define EMC_TIMING0_0_RESET_MASK                        _MK_MASK_CONST(0x3f3f3f3f)
+#define EMC_TIMING0_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define EMC_TIMING0_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_TIMING0_0_READ_MASK                         _MK_MASK_CONST(0x3f3f3f3f)
+#define EMC_TIMING0_0_WRITE_MASK                        _MK_MASK_CONST(0x3f3f3f3f)
+#define EMC_TIMING0_0_RC_SHIFT                  _MK_SHIFT_CONST(0)
+#define EMC_TIMING0_0_RC_FIELD                  (_MK_MASK_CONST(0x3f) << EMC_TIMING0_0_RC_SHIFT)
+#define EMC_TIMING0_0_RC_RANGE                  5:0
+#define EMC_TIMING0_0_RC_WOFFSET                        0x0
+#define EMC_TIMING0_0_RC_DEFAULT                        _MK_MASK_CONST(0x3f)
+#define EMC_TIMING0_0_RC_DEFAULT_MASK                   _MK_MASK_CONST(0x3f)
+#define EMC_TIMING0_0_RC_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_TIMING0_0_RC_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define EMC_TIMING0_0_RFC_SHIFT                 _MK_SHIFT_CONST(8)
+#define EMC_TIMING0_0_RFC_FIELD                 (_MK_MASK_CONST(0x3f) << EMC_TIMING0_0_RFC_SHIFT)
+#define EMC_TIMING0_0_RFC_RANGE                 13:8
+#define EMC_TIMING0_0_RFC_WOFFSET                       0x0
+#define EMC_TIMING0_0_RFC_DEFAULT                       _MK_MASK_CONST(0x3f)
+#define EMC_TIMING0_0_RFC_DEFAULT_MASK                  _MK_MASK_CONST(0x3f)
+#define EMC_TIMING0_0_RFC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_TIMING0_0_RFC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define EMC_TIMING0_0_RAS_SHIFT                 _MK_SHIFT_CONST(16)
+#define EMC_TIMING0_0_RAS_FIELD                 (_MK_MASK_CONST(0x3f) << EMC_TIMING0_0_RAS_SHIFT)
+#define EMC_TIMING0_0_RAS_RANGE                 21:16
+#define EMC_TIMING0_0_RAS_WOFFSET                       0x0
+#define EMC_TIMING0_0_RAS_DEFAULT                       _MK_MASK_CONST(0x3f)
+#define EMC_TIMING0_0_RAS_DEFAULT_MASK                  _MK_MASK_CONST(0x3f)
+#define EMC_TIMING0_0_RAS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_TIMING0_0_RAS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define EMC_TIMING0_0_RP_SHIFT                  _MK_SHIFT_CONST(24)
+#define EMC_TIMING0_0_RP_FIELD                  (_MK_MASK_CONST(0x3f) << EMC_TIMING0_0_RP_SHIFT)
+#define EMC_TIMING0_0_RP_RANGE                  29:24
+#define EMC_TIMING0_0_RP_WOFFSET                        0x0
+#define EMC_TIMING0_0_RP_DEFAULT                        _MK_MASK_CONST(0x3f)
+#define EMC_TIMING0_0_RP_DEFAULT_MASK                   _MK_MASK_CONST(0x3f)
+#define EMC_TIMING0_0_RP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_TIMING0_0_RP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register EMC_TIMING1_0  // Timing Control Register 1
+#define EMC_TIMING1_0                   _MK_ADDR_CONST(0x24)
+#define EMC_TIMING1_0_WORD_COUNT                        0x1
+#define EMC_TIMING1_0_RESET_VAL                         _MK_MASK_CONST(0x1f1f1f1f)
+#define EMC_TIMING1_0_RESET_MASK                        _MK_MASK_CONST(0x1f1f1f1f)
+#define EMC_TIMING1_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define EMC_TIMING1_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_TIMING1_0_READ_MASK                         _MK_MASK_CONST(0x1f1f1f1f)
+#define EMC_TIMING1_0_WRITE_MASK                        _MK_MASK_CONST(0x1f1f1f1f)
+#define EMC_TIMING1_0_R2W_SHIFT                 _MK_SHIFT_CONST(0)
+#define EMC_TIMING1_0_R2W_FIELD                 (_MK_MASK_CONST(0x1f) << EMC_TIMING1_0_R2W_SHIFT)
+#define EMC_TIMING1_0_R2W_RANGE                 4:0
+#define EMC_TIMING1_0_R2W_WOFFSET                       0x0
+#define EMC_TIMING1_0_R2W_DEFAULT                       _MK_MASK_CONST(0x1f)
+#define EMC_TIMING1_0_R2W_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define EMC_TIMING1_0_R2W_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_TIMING1_0_R2W_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define EMC_TIMING1_0_W2R_SHIFT                 _MK_SHIFT_CONST(8)
+#define EMC_TIMING1_0_W2R_FIELD                 (_MK_MASK_CONST(0x1f) << EMC_TIMING1_0_W2R_SHIFT)
+#define EMC_TIMING1_0_W2R_RANGE                 12:8
+#define EMC_TIMING1_0_W2R_WOFFSET                       0x0
+#define EMC_TIMING1_0_W2R_DEFAULT                       _MK_MASK_CONST(0x1f)
+#define EMC_TIMING1_0_W2R_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define EMC_TIMING1_0_W2R_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_TIMING1_0_W2R_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define EMC_TIMING1_0_R2P_SHIFT                 _MK_SHIFT_CONST(16)
+#define EMC_TIMING1_0_R2P_FIELD                 (_MK_MASK_CONST(0x1f) << EMC_TIMING1_0_R2P_SHIFT)
+#define EMC_TIMING1_0_R2P_RANGE                 20:16
+#define EMC_TIMING1_0_R2P_WOFFSET                       0x0
+#define EMC_TIMING1_0_R2P_DEFAULT                       _MK_MASK_CONST(0x1f)
+#define EMC_TIMING1_0_R2P_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define EMC_TIMING1_0_R2P_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_TIMING1_0_R2P_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define EMC_TIMING1_0_W2P_SHIFT                 _MK_SHIFT_CONST(24)
+#define EMC_TIMING1_0_W2P_FIELD                 (_MK_MASK_CONST(0x1f) << EMC_TIMING1_0_W2P_SHIFT)
+#define EMC_TIMING1_0_W2P_RANGE                 28:24
+#define EMC_TIMING1_0_W2P_WOFFSET                       0x0
+#define EMC_TIMING1_0_W2P_DEFAULT                       _MK_MASK_CONST(0x1f)
+#define EMC_TIMING1_0_W2P_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define EMC_TIMING1_0_W2P_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_TIMING1_0_W2P_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EMC_TIMING2_0  // Timing Control Register 2
+#define EMC_TIMING2_0                   _MK_ADDR_CONST(0x28)
+#define EMC_TIMING2_0_WORD_COUNT                        0x1
+#define EMC_TIMING2_0_RESET_VAL                         _MK_MASK_CONST(0x1f1f1f)
+#define EMC_TIMING2_0_RESET_MASK                        _MK_MASK_CONST(0xfff1f1f)
+#define EMC_TIMING2_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define EMC_TIMING2_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_TIMING2_0_READ_MASK                         _MK_MASK_CONST(0xfff1f1f)
+#define EMC_TIMING2_0_WRITE_MASK                        _MK_MASK_CONST(0xfff1f1f)
+#define EMC_TIMING2_0_RD_RCD_SHIFT                      _MK_SHIFT_CONST(0)
+#define EMC_TIMING2_0_RD_RCD_FIELD                      (_MK_MASK_CONST(0x1f) << EMC_TIMING2_0_RD_RCD_SHIFT)
+#define EMC_TIMING2_0_RD_RCD_RANGE                      4:0
+#define EMC_TIMING2_0_RD_RCD_WOFFSET                    0x0
+#define EMC_TIMING2_0_RD_RCD_DEFAULT                    _MK_MASK_CONST(0x1f)
+#define EMC_TIMING2_0_RD_RCD_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define EMC_TIMING2_0_RD_RCD_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_TIMING2_0_RD_RCD_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define EMC_TIMING2_0_WR_RCD_SHIFT                      _MK_SHIFT_CONST(8)
+#define EMC_TIMING2_0_WR_RCD_FIELD                      (_MK_MASK_CONST(0x1f) << EMC_TIMING2_0_WR_RCD_SHIFT)
+#define EMC_TIMING2_0_WR_RCD_RANGE                      12:8
+#define EMC_TIMING2_0_WR_RCD_WOFFSET                    0x0
+#define EMC_TIMING2_0_WR_RCD_DEFAULT                    _MK_MASK_CONST(0x1f)
+#define EMC_TIMING2_0_WR_RCD_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define EMC_TIMING2_0_WR_RCD_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_TIMING2_0_WR_RCD_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define EMC_TIMING2_0_RRD_SHIFT                 _MK_SHIFT_CONST(16)
+#define EMC_TIMING2_0_RRD_FIELD                 (_MK_MASK_CONST(0xf) << EMC_TIMING2_0_RRD_SHIFT)
+#define EMC_TIMING2_0_RRD_RANGE                 19:16
+#define EMC_TIMING2_0_RRD_WOFFSET                       0x0
+#define EMC_TIMING2_0_RRD_DEFAULT                       _MK_MASK_CONST(0xf)
+#define EMC_TIMING2_0_RRD_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define EMC_TIMING2_0_RRD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_TIMING2_0_RRD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define EMC_TIMING2_0_REXT_SHIFT                        _MK_SHIFT_CONST(20)
+#define EMC_TIMING2_0_REXT_FIELD                        (_MK_MASK_CONST(0xf) << EMC_TIMING2_0_REXT_SHIFT)
+#define EMC_TIMING2_0_REXT_RANGE                        23:20
+#define EMC_TIMING2_0_REXT_WOFFSET                      0x0
+#define EMC_TIMING2_0_REXT_DEFAULT                      _MK_MASK_CONST(0x1)
+#define EMC_TIMING2_0_REXT_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define EMC_TIMING2_0_REXT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_TIMING2_0_REXT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define EMC_TIMING2_0_WDV_SHIFT                 _MK_SHIFT_CONST(24)
+#define EMC_TIMING2_0_WDV_FIELD                 (_MK_MASK_CONST(0xf) << EMC_TIMING2_0_WDV_SHIFT)
+#define EMC_TIMING2_0_WDV_RANGE                 27:24
+#define EMC_TIMING2_0_WDV_WOFFSET                       0x0
+#define EMC_TIMING2_0_WDV_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_TIMING2_0_WDV_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define EMC_TIMING2_0_WDV_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_TIMING2_0_WDV_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EMC_TIMING3_0  // Timing Control Register 3
+#define EMC_TIMING3_0                   _MK_ADDR_CONST(0x2c)
+#define EMC_TIMING3_0_WORD_COUNT                        0x1
+#define EMC_TIMING3_0_RESET_VAL                         _MK_MASK_CONST(0x87102)
+#define EMC_TIMING3_0_RESET_MASK                        _MK_MASK_CONST(0x1fff0f)
+#define EMC_TIMING3_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define EMC_TIMING3_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_TIMING3_0_READ_MASK                         _MK_MASK_CONST(0x1fff0f)
+#define EMC_TIMING3_0_WRITE_MASK                        _MK_MASK_CONST(0x1fff0f)
+#define EMC_TIMING3_0_QUSE_SHIFT                        _MK_SHIFT_CONST(0)
+#define EMC_TIMING3_0_QUSE_FIELD                        (_MK_MASK_CONST(0xf) << EMC_TIMING3_0_QUSE_SHIFT)
+#define EMC_TIMING3_0_QUSE_RANGE                        3:0
+#define EMC_TIMING3_0_QUSE_WOFFSET                      0x0
+#define EMC_TIMING3_0_QUSE_DEFAULT                      _MK_MASK_CONST(0x2)
+#define EMC_TIMING3_0_QUSE_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define EMC_TIMING3_0_QUSE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_TIMING3_0_QUSE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define EMC_TIMING3_0_QRST_SHIFT                        _MK_SHIFT_CONST(8)
+#define EMC_TIMING3_0_QRST_FIELD                        (_MK_MASK_CONST(0xf) << EMC_TIMING3_0_QRST_SHIFT)
+#define EMC_TIMING3_0_QRST_RANGE                        11:8
+#define EMC_TIMING3_0_QRST_WOFFSET                      0x0
+#define EMC_TIMING3_0_QRST_DEFAULT                      _MK_MASK_CONST(0x1)
+#define EMC_TIMING3_0_QRST_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define EMC_TIMING3_0_QRST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_TIMING3_0_QRST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define EMC_TIMING3_0_QSAFE_SHIFT                       _MK_SHIFT_CONST(12)
+#define EMC_TIMING3_0_QSAFE_FIELD                       (_MK_MASK_CONST(0xf) << EMC_TIMING3_0_QSAFE_SHIFT)
+#define EMC_TIMING3_0_QSAFE_RANGE                       15:12
+#define EMC_TIMING3_0_QSAFE_WOFFSET                     0x0
+#define EMC_TIMING3_0_QSAFE_DEFAULT                     _MK_MASK_CONST(0x7)
+#define EMC_TIMING3_0_QSAFE_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define EMC_TIMING3_0_QSAFE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_TIMING3_0_QSAFE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define EMC_TIMING3_0_RDV_SHIFT                 _MK_SHIFT_CONST(16)
+#define EMC_TIMING3_0_RDV_FIELD                 (_MK_MASK_CONST(0x1f) << EMC_TIMING3_0_RDV_SHIFT)
+#define EMC_TIMING3_0_RDV_RANGE                 20:16
+#define EMC_TIMING3_0_RDV_WOFFSET                       0x0
+#define EMC_TIMING3_0_RDV_DEFAULT                       _MK_MASK_CONST(0x8)
+#define EMC_TIMING3_0_RDV_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define EMC_TIMING3_0_RDV_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_TIMING3_0_RDV_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_TIMING3_0_RDV_MAX                   _MK_ENUM_CONST(11)
+
+
+// Register EMC_TIMING4_0  // Timing Control Register 4
+#define EMC_TIMING4_0                   _MK_ADDR_CONST(0x30)
+#define EMC_TIMING4_0_WORD_COUNT                        0x1
+#define EMC_TIMING4_0_RESET_VAL                         _MK_MASK_CONST(0x1f)
+#define EMC_TIMING4_0_RESET_MASK                        _MK_MASK_CONST(0x7001f)
+#define EMC_TIMING4_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define EMC_TIMING4_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_TIMING4_0_READ_MASK                         _MK_MASK_CONST(0x7ffff)
+#define EMC_TIMING4_0_WRITE_MASK                        _MK_MASK_CONST(0x7ffff)
+#define EMC_TIMING4_0_REFRESH_LO_SHIFT                  _MK_SHIFT_CONST(0)
+#define EMC_TIMING4_0_REFRESH_LO_FIELD                  (_MK_MASK_CONST(0x1f) << EMC_TIMING4_0_REFRESH_LO_SHIFT)
+#define EMC_TIMING4_0_REFRESH_LO_RANGE                  4:0
+#define EMC_TIMING4_0_REFRESH_LO_WOFFSET                        0x0
+#define EMC_TIMING4_0_REFRESH_LO_DEFAULT                        _MK_MASK_CONST(0x1f)
+#define EMC_TIMING4_0_REFRESH_LO_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define EMC_TIMING4_0_REFRESH_LO_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_TIMING4_0_REFRESH_LO_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_TIMING4_0_REFRESH_LO_INIT_ENUM                      MAX
+#define EMC_TIMING4_0_REFRESH_LO_MAX                    _MK_ENUM_CONST(31)
+
+#define EMC_TIMING4_0_REFRESH_SHIFT                     _MK_SHIFT_CONST(5)
+#define EMC_TIMING4_0_REFRESH_FIELD                     (_MK_MASK_CONST(0x7ff) << EMC_TIMING4_0_REFRESH_SHIFT)
+#define EMC_TIMING4_0_REFRESH_RANGE                     15:5
+#define EMC_TIMING4_0_REFRESH_WOFFSET                   0x0
+#define EMC_TIMING4_0_REFRESH_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_TIMING4_0_REFRESH_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_TIMING4_0_REFRESH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_TIMING4_0_REFRESH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define EMC_TIMING4_0_BURST_REFRESH_NUM_SHIFT                   _MK_SHIFT_CONST(16)
+#define EMC_TIMING4_0_BURST_REFRESH_NUM_FIELD                   (_MK_MASK_CONST(0x7) << EMC_TIMING4_0_BURST_REFRESH_NUM_SHIFT)
+#define EMC_TIMING4_0_BURST_REFRESH_NUM_RANGE                   18:16
+#define EMC_TIMING4_0_BURST_REFRESH_NUM_WOFFSET                 0x0
+#define EMC_TIMING4_0_BURST_REFRESH_NUM_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_TIMING4_0_BURST_REFRESH_NUM_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
+#define EMC_TIMING4_0_BURST_REFRESH_NUM_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_TIMING4_0_BURST_REFRESH_NUM_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define EMC_TIMING4_0_BURST_REFRESH_NUM_INIT_ENUM                       BR1
+#define EMC_TIMING4_0_BURST_REFRESH_NUM_BR1                     _MK_ENUM_CONST(0)
+#define EMC_TIMING4_0_BURST_REFRESH_NUM_BR2                     _MK_ENUM_CONST(1)
+#define EMC_TIMING4_0_BURST_REFRESH_NUM_BR3                     _MK_ENUM_CONST(2)
+#define EMC_TIMING4_0_BURST_REFRESH_NUM_BR4                     _MK_ENUM_CONST(3)
+#define EMC_TIMING4_0_BURST_REFRESH_NUM_BR5                     _MK_ENUM_CONST(4)
+#define EMC_TIMING4_0_BURST_REFRESH_NUM_BR6                     _MK_ENUM_CONST(5)
+#define EMC_TIMING4_0_BURST_REFRESH_NUM_BR7                     _MK_ENUM_CONST(6)
+#define EMC_TIMING4_0_BURST_REFRESH_NUM_BR8                     _MK_ENUM_CONST(7)
+
+
+// Register EMC_TIMING5_0  // Timing Control Register 5
+#define EMC_TIMING5_0                   _MK_ADDR_CONST(0x34)
+#define EMC_TIMING5_0_WORD_COUNT                        0x1
+#define EMC_TIMING5_0_RESET_VAL                         _MK_MASK_CONST(0x1ffffff)
+#define EMC_TIMING5_0_RESET_MASK                        _MK_MASK_CONST(0x1ffffff)
+#define EMC_TIMING5_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define EMC_TIMING5_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_TIMING5_0_READ_MASK                         _MK_MASK_CONST(0x1ffffff)
+#define EMC_TIMING5_0_WRITE_MASK                        _MK_MASK_CONST(0x1ffffff)
+#define EMC_TIMING5_0_PDEX2WR_SHIFT                     _MK_SHIFT_CONST(0)
+#define EMC_TIMING5_0_PDEX2WR_FIELD                     (_MK_MASK_CONST(0xf) << EMC_TIMING5_0_PDEX2WR_SHIFT)
+#define EMC_TIMING5_0_PDEX2WR_RANGE                     3:0
+#define EMC_TIMING5_0_PDEX2WR_WOFFSET                   0x0
+#define EMC_TIMING5_0_PDEX2WR_DEFAULT                   _MK_MASK_CONST(0xf)
+#define EMC_TIMING5_0_PDEX2WR_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define EMC_TIMING5_0_PDEX2WR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_TIMING5_0_PDEX2WR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define EMC_TIMING5_0_PDEX2RD_SHIFT                     _MK_SHIFT_CONST(4)
+#define EMC_TIMING5_0_PDEX2RD_FIELD                     (_MK_MASK_CONST(0xf) << EMC_TIMING5_0_PDEX2RD_SHIFT)
+#define EMC_TIMING5_0_PDEX2RD_RANGE                     7:4
+#define EMC_TIMING5_0_PDEX2RD_WOFFSET                   0x0
+#define EMC_TIMING5_0_PDEX2RD_DEFAULT                   _MK_MASK_CONST(0xf)
+#define EMC_TIMING5_0_PDEX2RD_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define EMC_TIMING5_0_PDEX2RD_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_TIMING5_0_PDEX2RD_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define EMC_TIMING5_0_PCHG2PDEN_SHIFT                   _MK_SHIFT_CONST(8)
+#define EMC_TIMING5_0_PCHG2PDEN_FIELD                   (_MK_MASK_CONST(0xf) << EMC_TIMING5_0_PCHG2PDEN_SHIFT)
+#define EMC_TIMING5_0_PCHG2PDEN_RANGE                   11:8
+#define EMC_TIMING5_0_PCHG2PDEN_WOFFSET                 0x0
+#define EMC_TIMING5_0_PCHG2PDEN_DEFAULT                 _MK_MASK_CONST(0xf)
+#define EMC_TIMING5_0_PCHG2PDEN_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define EMC_TIMING5_0_PCHG2PDEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_TIMING5_0_PCHG2PDEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define EMC_TIMING5_0_RW2PDEN_SHIFT                     _MK_SHIFT_CONST(12)
+#define EMC_TIMING5_0_RW2PDEN_FIELD                     (_MK_MASK_CONST(0xf) << EMC_TIMING5_0_RW2PDEN_SHIFT)
+#define EMC_TIMING5_0_RW2PDEN_RANGE                     15:12
+#define EMC_TIMING5_0_RW2PDEN_WOFFSET                   0x0
+#define EMC_TIMING5_0_RW2PDEN_DEFAULT                   _MK_MASK_CONST(0xf)
+#define EMC_TIMING5_0_RW2PDEN_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define EMC_TIMING5_0_RW2PDEN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_TIMING5_0_RW2PDEN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define EMC_TIMING5_0_ACT2PDEN_SHIFT                    _MK_SHIFT_CONST(16)
+#define EMC_TIMING5_0_ACT2PDEN_FIELD                    (_MK_MASK_CONST(0xf) << EMC_TIMING5_0_ACT2PDEN_SHIFT)
+#define EMC_TIMING5_0_ACT2PDEN_RANGE                    19:16
+#define EMC_TIMING5_0_ACT2PDEN_WOFFSET                  0x0
+#define EMC_TIMING5_0_ACT2PDEN_DEFAULT                  _MK_MASK_CONST(0xf)
+#define EMC_TIMING5_0_ACT2PDEN_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
+#define EMC_TIMING5_0_ACT2PDEN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_TIMING5_0_ACT2PDEN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define EMC_TIMING5_0_AR2PDEN_SHIFT                     _MK_SHIFT_CONST(20)
+#define EMC_TIMING5_0_AR2PDEN_FIELD                     (_MK_MASK_CONST(0x1f) << EMC_TIMING5_0_AR2PDEN_SHIFT)
+#define EMC_TIMING5_0_AR2PDEN_RANGE                     24:20
+#define EMC_TIMING5_0_AR2PDEN_WOFFSET                   0x0
+#define EMC_TIMING5_0_AR2PDEN_DEFAULT                   _MK_MASK_CONST(0x1f)
+#define EMC_TIMING5_0_AR2PDEN_DEFAULT_MASK                      _MK_MASK_CONST(0x1f)
+#define EMC_TIMING5_0_AR2PDEN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_TIMING5_0_AR2PDEN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EMC_MRS_0  // MRS value
+#define EMC_MRS_0                       _MK_ADDR_CONST(0x38)
+#define EMC_MRS_0_WORD_COUNT                    0x1
+#define EMC_MRS_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define EMC_MRS_0_RESET_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_MRS_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define EMC_MRS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_MRS_0_READ_MASK                     _MK_MASK_CONST(0x303fff)
+#define EMC_MRS_0_WRITE_MASK                    _MK_MASK_CONST(0x303fff)
+#define EMC_MRS_0_MRS_ADR_SHIFT                 _MK_SHIFT_CONST(0)
+#define EMC_MRS_0_MRS_ADR_FIELD                 (_MK_MASK_CONST(0x3fff) << EMC_MRS_0_MRS_ADR_SHIFT)
+#define EMC_MRS_0_MRS_ADR_RANGE                 13:0
+#define EMC_MRS_0_MRS_ADR_WOFFSET                       0x0
+#define EMC_MRS_0_MRS_ADR_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_MRS_0_MRS_ADR_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_MRS_0_MRS_ADR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_MRS_0_MRS_ADR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define EMC_MRS_0_MRS_BA_SHIFT                  _MK_SHIFT_CONST(20)
+#define EMC_MRS_0_MRS_BA_FIELD                  (_MK_MASK_CONST(0x3) << EMC_MRS_0_MRS_BA_SHIFT)
+#define EMC_MRS_0_MRS_BA_RANGE                  21:20
+#define EMC_MRS_0_MRS_BA_WOFFSET                        0x0
+#define EMC_MRS_0_MRS_BA_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_MRS_0_MRS_BA_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_MRS_0_MRS_BA_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_MRS_0_MRS_BA_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register EMC_EMRS_0  // EMRS value
+#define EMC_EMRS_0                      _MK_ADDR_CONST(0x3c)
+#define EMC_EMRS_0_WORD_COUNT                   0x1
+#define EMC_EMRS_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define EMC_EMRS_0_RESET_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_EMRS_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define EMC_EMRS_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_EMRS_0_READ_MASK                    _MK_MASK_CONST(0x303fff)
+#define EMC_EMRS_0_WRITE_MASK                   _MK_MASK_CONST(0x303fff)
+#define EMC_EMRS_0_EMRS_ADR_SHIFT                       _MK_SHIFT_CONST(0)
+#define EMC_EMRS_0_EMRS_ADR_FIELD                       (_MK_MASK_CONST(0x3fff) << EMC_EMRS_0_EMRS_ADR_SHIFT)
+#define EMC_EMRS_0_EMRS_ADR_RANGE                       13:0
+#define EMC_EMRS_0_EMRS_ADR_WOFFSET                     0x0
+#define EMC_EMRS_0_EMRS_ADR_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_EMRS_0_EMRS_ADR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_EMRS_0_EMRS_ADR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_EMRS_0_EMRS_ADR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define EMC_EMRS_0_EMRS_BA_SHIFT                        _MK_SHIFT_CONST(20)
+#define EMC_EMRS_0_EMRS_BA_FIELD                        (_MK_MASK_CONST(0x3) << EMC_EMRS_0_EMRS_BA_SHIFT)
+#define EMC_EMRS_0_EMRS_BA_RANGE                        21:20
+#define EMC_EMRS_0_EMRS_BA_WOFFSET                      0x0
+#define EMC_EMRS_0_EMRS_BA_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_EMRS_0_EMRS_BA_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define EMC_EMRS_0_EMRS_BA_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_EMRS_0_EMRS_BA_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register EMC_REF_0  // Refresh command register
+#define EMC_REF_0                       _MK_ADDR_CONST(0x40)
+#define EMC_REF_0_WORD_COUNT                    0x1
+#define EMC_REF_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define EMC_REF_0_RESET_MASK                    _MK_MASK_CONST(0xff01)
+#define EMC_REF_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define EMC_REF_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_REF_0_READ_MASK                     _MK_MASK_CONST(0xff01)
+#define EMC_REF_0_WRITE_MASK                    _MK_MASK_CONST(0xff01)
+#define EMC_REF_0_REF_CMD_SHIFT                 _MK_SHIFT_CONST(0)
+#define EMC_REF_0_REF_CMD_FIELD                 (_MK_MASK_CONST(0x1) << EMC_REF_0_REF_CMD_SHIFT)
+#define EMC_REF_0_REF_CMD_RANGE                 0:0
+#define EMC_REF_0_REF_CMD_WOFFSET                       0x0
+#define EMC_REF_0_REF_CMD_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_REF_0_REF_CMD_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define EMC_REF_0_REF_CMD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_REF_0_REF_CMD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define EMC_REF_0_REF_NUM_SHIFT                 _MK_SHIFT_CONST(8)
+#define EMC_REF_0_REF_NUM_FIELD                 (_MK_MASK_CONST(0xff) << EMC_REF_0_REF_NUM_SHIFT)
+#define EMC_REF_0_REF_NUM_RANGE                 15:8
+#define EMC_REF_0_REF_NUM_WOFFSET                       0x0
+#define EMC_REF_0_REF_NUM_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_REF_0_REF_NUM_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define EMC_REF_0_REF_NUM_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_REF_0_REF_NUM_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EMC_PRE_0  // Precharge command register
+#define EMC_PRE_0                       _MK_ADDR_CONST(0x44)
+#define EMC_PRE_0_WORD_COUNT                    0x1
+#define EMC_PRE_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define EMC_PRE_0_RESET_MASK                    _MK_MASK_CONST(0x1)
+#define EMC_PRE_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define EMC_PRE_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_PRE_0_READ_MASK                     _MK_MASK_CONST(0x1)
+#define EMC_PRE_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
+#define EMC_PRE_0_PRE_CMD_SHIFT                 _MK_SHIFT_CONST(0)
+#define EMC_PRE_0_PRE_CMD_FIELD                 (_MK_MASK_CONST(0x1) << EMC_PRE_0_PRE_CMD_SHIFT)
+#define EMC_PRE_0_PRE_CMD_RANGE                 0:0
+#define EMC_PRE_0_PRE_CMD_WOFFSET                       0x0
+#define EMC_PRE_0_PRE_CMD_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_PRE_0_PRE_CMD_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define EMC_PRE_0_PRE_CMD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_PRE_0_PRE_CMD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EMC_NOP_0  // NOP command register
+#define EMC_NOP_0                       _MK_ADDR_CONST(0x48)
+#define EMC_NOP_0_WORD_COUNT                    0x1
+#define EMC_NOP_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define EMC_NOP_0_RESET_MASK                    _MK_MASK_CONST(0x1)
+#define EMC_NOP_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define EMC_NOP_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_NOP_0_READ_MASK                     _MK_MASK_CONST(0x1)
+#define EMC_NOP_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
+#define EMC_NOP_0_NOP_CMD_SHIFT                 _MK_SHIFT_CONST(0)
+#define EMC_NOP_0_NOP_CMD_FIELD                 (_MK_MASK_CONST(0x1) << EMC_NOP_0_NOP_CMD_SHIFT)
+#define EMC_NOP_0_NOP_CMD_RANGE                 0:0
+#define EMC_NOP_0_NOP_CMD_WOFFSET                       0x0
+#define EMC_NOP_0_NOP_CMD_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_NOP_0_NOP_CMD_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define EMC_NOP_0_NOP_CMD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_NOP_0_NOP_CMD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EMC_SELF_REF_0  // SELF REFRESH command register
+#define EMC_SELF_REF_0                  _MK_ADDR_CONST(0x4c)
+#define EMC_SELF_REF_0_WORD_COUNT                       0x1
+#define EMC_SELF_REF_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define EMC_SELF_REF_0_RESET_MASK                       _MK_MASK_CONST(0x1)
+#define EMC_SELF_REF_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define EMC_SELF_REF_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_SELF_REF_0_READ_MASK                        _MK_MASK_CONST(0x1)
+#define EMC_SELF_REF_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
+#define EMC_SELF_REF_0_SELF_REF_CMD_SHIFT                       _MK_SHIFT_CONST(0)
+#define EMC_SELF_REF_0_SELF_REF_CMD_FIELD                       (_MK_MASK_CONST(0x1) << EMC_SELF_REF_0_SELF_REF_CMD_SHIFT)
+#define EMC_SELF_REF_0_SELF_REF_CMD_RANGE                       0:0
+#define EMC_SELF_REF_0_SELF_REF_CMD_WOFFSET                     0x0
+#define EMC_SELF_REF_0_SELF_REF_CMD_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_SELF_REF_0_SELF_REF_CMD_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define EMC_SELF_REF_0_SELF_REF_CMD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_SELF_REF_0_SELF_REF_CMD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EMC_SELF_REF_0_SELF_REF_CMD_INIT_ENUM                   DISABLED
+#define EMC_SELF_REF_0_SELF_REF_CMD_DISABLED                    _MK_ENUM_CONST(0)
+#define EMC_SELF_REF_0_SELF_REF_CMD_ENABLED                     _MK_ENUM_CONST(1)
+
+
+// Register EMC_DPD_0  // Deep Power Down command register
+#define EMC_DPD_0                       _MK_ADDR_CONST(0x50)
+#define EMC_DPD_0_WORD_COUNT                    0x1
+#define EMC_DPD_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define EMC_DPD_0_RESET_MASK                    _MK_MASK_CONST(0x1)
+#define EMC_DPD_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define EMC_DPD_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_DPD_0_READ_MASK                     _MK_MASK_CONST(0x1)
+#define EMC_DPD_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
+#define EMC_DPD_0_DPD_CMD_SHIFT                 _MK_SHIFT_CONST(0)
+#define EMC_DPD_0_DPD_CMD_FIELD                 (_MK_MASK_CONST(0x1) << EMC_DPD_0_DPD_CMD_SHIFT)
+#define EMC_DPD_0_DPD_CMD_RANGE                 0:0
+#define EMC_DPD_0_DPD_CMD_WOFFSET                       0x0
+#define EMC_DPD_0_DPD_CMD_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_DPD_0_DPD_CMD_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define EMC_DPD_0_DPD_CMD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_DPD_0_DPD_CMD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_DPD_0_DPD_CMD_INIT_ENUM                     DISABLED
+#define EMC_DPD_0_DPD_CMD_DISABLED                      _MK_ENUM_CONST(0)
+#define EMC_DPD_0_DPD_CMD_ENABLED                       _MK_ENUM_CONST(1)
+
+
+// Register EMC_CMDQ_0  // Command Queue Depth register
+#define EMC_CMDQ_0                      _MK_ADDR_CONST(0x54)
+#define EMC_CMDQ_0_WORD_COUNT                   0x1
+#define EMC_CMDQ_0_RESET_VAL                    _MK_MASK_CONST(0x1304)
+#define EMC_CMDQ_0_RESET_MASK                   _MK_MASK_CONST(0x770f)
+#define EMC_CMDQ_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define EMC_CMDQ_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_CMDQ_0_READ_MASK                    _MK_MASK_CONST(0x770f)
+#define EMC_CMDQ_0_WRITE_MASK                   _MK_MASK_CONST(0x770f)
+#define EMC_CMDQ_0_RW_DEPTH_SHIFT                       _MK_SHIFT_CONST(0)
+#define EMC_CMDQ_0_RW_DEPTH_FIELD                       (_MK_MASK_CONST(0xf) << EMC_CMDQ_0_RW_DEPTH_SHIFT)
+#define EMC_CMDQ_0_RW_DEPTH_RANGE                       3:0
+#define EMC_CMDQ_0_RW_DEPTH_WOFFSET                     0x0
+#define EMC_CMDQ_0_RW_DEPTH_DEFAULT                     _MK_MASK_CONST(0x4)
+#define EMC_CMDQ_0_RW_DEPTH_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define EMC_CMDQ_0_RW_DEPTH_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_CMDQ_0_RW_DEPTH_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define EMC_CMDQ_0_ACT_DEPTH_SHIFT                      _MK_SHIFT_CONST(8)
+#define EMC_CMDQ_0_ACT_DEPTH_FIELD                      (_MK_MASK_CONST(0x7) << EMC_CMDQ_0_ACT_DEPTH_SHIFT)
+#define EMC_CMDQ_0_ACT_DEPTH_RANGE                      10:8
+#define EMC_CMDQ_0_ACT_DEPTH_WOFFSET                    0x0
+#define EMC_CMDQ_0_ACT_DEPTH_DEFAULT                    _MK_MASK_CONST(0x3)
+#define EMC_CMDQ_0_ACT_DEPTH_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define EMC_CMDQ_0_ACT_DEPTH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_CMDQ_0_ACT_DEPTH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define EMC_CMDQ_0_PRE_DEPTH_SHIFT                      _MK_SHIFT_CONST(12)
+#define EMC_CMDQ_0_PRE_DEPTH_FIELD                      (_MK_MASK_CONST(0x7) << EMC_CMDQ_0_PRE_DEPTH_SHIFT)
+#define EMC_CMDQ_0_PRE_DEPTH_RANGE                      14:12
+#define EMC_CMDQ_0_PRE_DEPTH_WOFFSET                    0x0
+#define EMC_CMDQ_0_PRE_DEPTH_DEFAULT                    _MK_MASK_CONST(0x1)
+#define EMC_CMDQ_0_PRE_DEPTH_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define EMC_CMDQ_0_PRE_DEPTH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_CMDQ_0_PRE_DEPTH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register EMC_FBIO_CFG1_0  // FBIO configuration register
+#define EMC_FBIO_CFG1_0                 _MK_ADDR_CONST(0x58)
+#define EMC_FBIO_CFG1_0_WORD_COUNT                      0x1
+#define EMC_FBIO_CFG1_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define EMC_FBIO_CFG1_0_RESET_MASK                      _MK_MASK_CONST(0x10000)
+#define EMC_FBIO_CFG1_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EMC_FBIO_CFG1_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_FBIO_CFG1_0_READ_MASK                       _MK_MASK_CONST(0x10000)
+#define EMC_FBIO_CFG1_0_WRITE_MASK                      _MK_MASK_CONST(0x10000)
+#define EMC_FBIO_CFG1_0_CFG_DEN_EARLY_SHIFT                     _MK_SHIFT_CONST(16)
+#define EMC_FBIO_CFG1_0_CFG_DEN_EARLY_FIELD                     (_MK_MASK_CONST(0x1) << EMC_FBIO_CFG1_0_CFG_DEN_EARLY_SHIFT)
+#define EMC_FBIO_CFG1_0_CFG_DEN_EARLY_RANGE                     16:16
+#define EMC_FBIO_CFG1_0_CFG_DEN_EARLY_WOFFSET                   0x0
+#define EMC_FBIO_CFG1_0_CFG_DEN_EARLY_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_FBIO_CFG1_0_CFG_DEN_EARLY_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define EMC_FBIO_CFG1_0_CFG_DEN_EARLY_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_FBIO_CFG1_0_CFG_DEN_EARLY_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_FBIO_CFG1_0_CFG_DEN_EARLY_INIT_ENUM                 DISABLE
+#define EMC_FBIO_CFG1_0_CFG_DEN_EARLY_DISABLE                   _MK_ENUM_CONST(0)
+#define EMC_FBIO_CFG1_0_CFG_DEN_EARLY_ENABLE                    _MK_ENUM_CONST(1)
+
+
+// Register EMC_FBIO_DQSIB_DLY_0  // FBIO configuration register
+#define EMC_FBIO_DQSIB_DLY_0                    _MK_ADDR_CONST(0x5c)
+#define EMC_FBIO_DQSIB_DLY_0_WORD_COUNT                         0x1
+#define EMC_FBIO_DQSIB_DLY_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define EMC_FBIO_DQSIB_DLY_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_FBIO_DQSIB_DLY_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define EMC_FBIO_DQSIB_DLY_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_FBIO_DQSIB_DLY_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EMC_FBIO_DQSIB_DLY_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_0_SHIFT                 _MK_SHIFT_CONST(0)
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_0_FIELD                 (_MK_MASK_CONST(0xff) << EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_0_SHIFT)
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_0_RANGE                 7:0
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_0_WOFFSET                       0x0
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_0_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_0_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_0_MAX                   _MK_ENUM_CONST(47)
+
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_1_SHIFT                 _MK_SHIFT_CONST(8)
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_1_FIELD                 (_MK_MASK_CONST(0xff) << EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_1_SHIFT)
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_1_RANGE                 15:8
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_1_WOFFSET                       0x0
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_1_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_1_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_1_MAX                   _MK_ENUM_CONST(47)
+
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_2_SHIFT                 _MK_SHIFT_CONST(16)
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_2_FIELD                 (_MK_MASK_CONST(0xff) << EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_2_SHIFT)
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_2_RANGE                 23:16
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_2_WOFFSET                       0x0
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_2_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_2_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_2_MAX                   _MK_ENUM_CONST(47)
+
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_3_SHIFT                 _MK_SHIFT_CONST(24)
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_3_FIELD                 (_MK_MASK_CONST(0xff) << EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_3_SHIFT)
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_3_RANGE                 31:24
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_3_WOFFSET                       0x0
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_3_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_3_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_3_MAX                   _MK_ENUM_CONST(47)
+
+
+// Register EMC_FBIO_SPARE_0  // FBIO spare register
+#define EMC_FBIO_SPARE_0                        _MK_ADDR_CONST(0x60)
+#define EMC_FBIO_SPARE_0_WORD_COUNT                     0x1
+#define EMC_FBIO_SPARE_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define EMC_FBIO_SPARE_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
+#define EMC_FBIO_SPARE_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define EMC_FBIO_SPARE_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_FBIO_SPARE_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EMC_FBIO_SPARE_0_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
+#define EMC_FBIO_SPARE_0_CFG_FBIO_SPARE_SHIFT                   _MK_SHIFT_CONST(0)
+#define EMC_FBIO_SPARE_0_CFG_FBIO_SPARE_FIELD                   (_MK_MASK_CONST(0xffffffff) << EMC_FBIO_SPARE_0_CFG_FBIO_SPARE_SHIFT)
+#define EMC_FBIO_SPARE_0_CFG_FBIO_SPARE_RANGE                   31:0
+#define EMC_FBIO_SPARE_0_CFG_FBIO_SPARE_WOFFSET                 0x0
+#define EMC_FBIO_SPARE_0_CFG_FBIO_SPARE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_FBIO_SPARE_0_CFG_FBIO_SPARE_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
+#define EMC_FBIO_SPARE_0_CFG_FBIO_SPARE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_FBIO_SPARE_0_CFG_FBIO_SPARE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register EMC_FBIO_CFG5_0  // FBIO configuration Register 
+#define EMC_FBIO_CFG5_0                 _MK_ADDR_CONST(0x64)
+#define EMC_FBIO_CFG5_0_WORD_COUNT                      0x1
+#define EMC_FBIO_CFG5_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define EMC_FBIO_CFG5_0_RESET_MASK                      _MK_MASK_CONST(0x11)
+#define EMC_FBIO_CFG5_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EMC_FBIO_CFG5_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_FBIO_CFG5_0_READ_MASK                       _MK_MASK_CONST(0x11)
+#define EMC_FBIO_CFG5_0_WRITE_MASK                      _MK_MASK_CONST(0x11)
+#define EMC_FBIO_CFG5_0_DRAM_TYPE_SHIFT                 _MK_SHIFT_CONST(0)
+#define EMC_FBIO_CFG5_0_DRAM_TYPE_FIELD                 (_MK_MASK_CONST(0x1) << EMC_FBIO_CFG5_0_DRAM_TYPE_SHIFT)
+#define EMC_FBIO_CFG5_0_DRAM_TYPE_RANGE                 0:0
+#define EMC_FBIO_CFG5_0_DRAM_TYPE_WOFFSET                       0x0
+#define EMC_FBIO_CFG5_0_DRAM_TYPE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_FBIO_CFG5_0_DRAM_TYPE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define EMC_FBIO_CFG5_0_DRAM_TYPE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_FBIO_CFG5_0_DRAM_TYPE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_FBIO_CFG5_0_DRAM_TYPE_INIT_ENUM                     SDR
+#define EMC_FBIO_CFG5_0_DRAM_TYPE_SDR                   _MK_ENUM_CONST(0)
+#define EMC_FBIO_CFG5_0_DRAM_TYPE_DDR1                  _MK_ENUM_CONST(1)
+
+#define EMC_FBIO_CFG5_0_DRAM_WIDTH_SHIFT                        _MK_SHIFT_CONST(4)
+#define EMC_FBIO_CFG5_0_DRAM_WIDTH_FIELD                        (_MK_MASK_CONST(0x1) << EMC_FBIO_CFG5_0_DRAM_WIDTH_SHIFT)
+#define EMC_FBIO_CFG5_0_DRAM_WIDTH_RANGE                        4:4
+#define EMC_FBIO_CFG5_0_DRAM_WIDTH_WOFFSET                      0x0
+#define EMC_FBIO_CFG5_0_DRAM_WIDTH_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_FBIO_CFG5_0_DRAM_WIDTH_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define EMC_FBIO_CFG5_0_DRAM_WIDTH_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_FBIO_CFG5_0_DRAM_WIDTH_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_FBIO_CFG5_0_DRAM_WIDTH_INIT_ENUM                    X32
+#define EMC_FBIO_CFG5_0_DRAM_WIDTH_X32                  _MK_ENUM_CONST(0)
+#define EMC_FBIO_CFG5_0_DRAM_WIDTH_X16                  _MK_ENUM_CONST(1)
+
+
+// Register EMC_FBIO_WRPTR_EQ_2_0  // FBIO wrptr register
+#define EMC_FBIO_WRPTR_EQ_2_0                   _MK_ADDR_CONST(0x68)
+#define EMC_FBIO_WRPTR_EQ_2_0_WORD_COUNT                        0x1
+#define EMC_FBIO_WRPTR_EQ_2_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define EMC_FBIO_WRPTR_EQ_2_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_FBIO_WRPTR_EQ_2_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define EMC_FBIO_WRPTR_EQ_2_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_FBIO_WRPTR_EQ_2_0_READ_MASK                         _MK_MASK_CONST(0xf)
+#define EMC_FBIO_WRPTR_EQ_2_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_FBIO_WRPTR_EQ_2_0_FB_WRPTR_EQ_2_SHIFT                       _MK_SHIFT_CONST(0)
+#define EMC_FBIO_WRPTR_EQ_2_0_FB_WRPTR_EQ_2_FIELD                       (_MK_MASK_CONST(0xf) << EMC_FBIO_WRPTR_EQ_2_0_FB_WRPTR_EQ_2_SHIFT)
+#define EMC_FBIO_WRPTR_EQ_2_0_FB_WRPTR_EQ_2_RANGE                       3:0
+#define EMC_FBIO_WRPTR_EQ_2_0_FB_WRPTR_EQ_2_WOFFSET                     0x0
+#define EMC_FBIO_WRPTR_EQ_2_0_FB_WRPTR_EQ_2_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_FBIO_WRPTR_EQ_2_0_FB_WRPTR_EQ_2_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_FBIO_WRPTR_EQ_2_0_FB_WRPTR_EQ_2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_FBIO_WRPTR_EQ_2_0_FB_WRPTR_EQ_2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register EMC_FBIO_QUSE_DLY_0  // QUSE delay register   
+#define EMC_FBIO_QUSE_DLY_0                     _MK_ADDR_CONST(0x6c)
+#define EMC_FBIO_QUSE_DLY_0_WORD_COUNT                  0x1
+#define EMC_FBIO_QUSE_DLY_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define EMC_FBIO_QUSE_DLY_0_RESET_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_FBIO_QUSE_DLY_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define EMC_FBIO_QUSE_DLY_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EMC_FBIO_QUSE_DLY_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define EMC_FBIO_QUSE_DLY_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_0_SHIFT                   _MK_SHIFT_CONST(0)
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_0_FIELD                   (_MK_MASK_CONST(0xff) << EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_0_SHIFT)
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_0_RANGE                   7:0
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_0_WOFFSET                 0x0
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_0_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_0_MAX                     _MK_ENUM_CONST(47)
+
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_1_SHIFT                   _MK_SHIFT_CONST(8)
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_1_FIELD                   (_MK_MASK_CONST(0xff) << EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_1_SHIFT)
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_1_RANGE                   15:8
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_1_WOFFSET                 0x0
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_1_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_1_MAX                     _MK_ENUM_CONST(47)
+
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_2_SHIFT                   _MK_SHIFT_CONST(16)
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_2_FIELD                   (_MK_MASK_CONST(0xff) << EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_2_SHIFT)
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_2_RANGE                   23:16
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_2_WOFFSET                 0x0
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_2_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_2_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_2_MAX                     _MK_ENUM_CONST(47)
+
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_3_SHIFT                   _MK_SHIFT_CONST(24)
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_3_FIELD                   (_MK_MASK_CONST(0xff) << EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_3_SHIFT)
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_3_RANGE                   31:24
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_3_WOFFSET                 0x0
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_3_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_3_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_3_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_3_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_3_MAX                     _MK_ENUM_CONST(47)
+
+
+// Register EMC_FBIO_CFG6_0  // FBIO configuration register   
+#define EMC_FBIO_CFG6_0                 _MK_ADDR_CONST(0x70)
+#define EMC_FBIO_CFG6_0_WORD_COUNT                      0x1
+#define EMC_FBIO_CFG6_0_RESET_VAL                       _MK_MASK_CONST(0x2)
+#define EMC_FBIO_CFG6_0_RESET_MASK                      _MK_MASK_CONST(0x7)
+#define EMC_FBIO_CFG6_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EMC_FBIO_CFG6_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_FBIO_CFG6_0_READ_MASK                       _MK_MASK_CONST(0x7)
+#define EMC_FBIO_CFG6_0_WRITE_MASK                      _MK_MASK_CONST(0x7)
+#define EMC_FBIO_CFG6_0_CFG_QUSE_LATE_SHIFT                     _MK_SHIFT_CONST(0)
+#define EMC_FBIO_CFG6_0_CFG_QUSE_LATE_FIELD                     (_MK_MASK_CONST(0x7) << EMC_FBIO_CFG6_0_CFG_QUSE_LATE_SHIFT)
+#define EMC_FBIO_CFG6_0_CFG_QUSE_LATE_RANGE                     2:0
+#define EMC_FBIO_CFG6_0_CFG_QUSE_LATE_WOFFSET                   0x0
+#define EMC_FBIO_CFG6_0_CFG_QUSE_LATE_DEFAULT                   _MK_MASK_CONST(0x2)
+#define EMC_FBIO_CFG6_0_CFG_QUSE_LATE_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define EMC_FBIO_CFG6_0_CFG_QUSE_LATE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_FBIO_CFG6_0_CFG_QUSE_LATE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EMC_BUSARB_0  // Bus Arbitration Timeout register
+#define EMC_BUSARB_0                    _MK_ADDR_CONST(0x74)
+#define EMC_BUSARB_0_WORD_COUNT                         0x1
+#define EMC_BUSARB_0_RESET_VAL                  _MK_MASK_CONST(0x13ff02f)
+#define EMC_BUSARB_0_RESET_MASK                         _MK_MASK_CONST(0x1ffff3ff)
+#define EMC_BUSARB_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define EMC_BUSARB_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_BUSARB_0_READ_MASK                  _MK_MASK_CONST(0x1ffff3ff)
+#define EMC_BUSARB_0_WRITE_MASK                         _MK_MASK_CONST(0x1ffff3ff)
+#define EMC_BUSARB_0_EMC_MIN_TRANS_TIME_SHIFT                   _MK_SHIFT_CONST(0)
+#define EMC_BUSARB_0_EMC_MIN_TRANS_TIME_FIELD                   (_MK_MASK_CONST(0x3ff) << EMC_BUSARB_0_EMC_MIN_TRANS_TIME_SHIFT)
+#define EMC_BUSARB_0_EMC_MIN_TRANS_TIME_RANGE                   9:0
+#define EMC_BUSARB_0_EMC_MIN_TRANS_TIME_WOFFSET                 0x0
+#define EMC_BUSARB_0_EMC_MIN_TRANS_TIME_DEFAULT                 _MK_MASK_CONST(0x2f)
+#define EMC_BUSARB_0_EMC_MIN_TRANS_TIME_DEFAULT_MASK                    _MK_MASK_CONST(0x3ff)
+#define EMC_BUSARB_0_EMC_MIN_TRANS_TIME_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_BUSARB_0_EMC_MIN_TRANS_TIME_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define EMC_BUSARB_0_NOR_MAX_TRANS_TIME_SHIFT                   _MK_SHIFT_CONST(12)
+#define EMC_BUSARB_0_NOR_MAX_TRANS_TIME_FIELD                   (_MK_MASK_CONST(0xfff) << EMC_BUSARB_0_NOR_MAX_TRANS_TIME_SHIFT)
+#define EMC_BUSARB_0_NOR_MAX_TRANS_TIME_RANGE                   23:12
+#define EMC_BUSARB_0_NOR_MAX_TRANS_TIME_WOFFSET                 0x0
+#define EMC_BUSARB_0_NOR_MAX_TRANS_TIME_DEFAULT                 _MK_MASK_CONST(0x3ff)
+#define EMC_BUSARB_0_NOR_MAX_TRANS_TIME_DEFAULT_MASK                    _MK_MASK_CONST(0xfff)
+#define EMC_BUSARB_0_NOR_MAX_TRANS_TIME_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_BUSARB_0_NOR_MAX_TRANS_TIME_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define EMC_BUSARB_0_BUS_TURNAROUND_SHIFT                       _MK_SHIFT_CONST(24)
+#define EMC_BUSARB_0_BUS_TURNAROUND_FIELD                       (_MK_MASK_CONST(0x1f) << EMC_BUSARB_0_BUS_TURNAROUND_SHIFT)
+#define EMC_BUSARB_0_BUS_TURNAROUND_RANGE                       28:24
+#define EMC_BUSARB_0_BUS_TURNAROUND_WOFFSET                     0x0
+#define EMC_BUSARB_0_BUS_TURNAROUND_DEFAULT                     _MK_MASK_CONST(0x1)
+#define EMC_BUSARB_0_BUS_TURNAROUND_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define EMC_BUSARB_0_BUS_TURNAROUND_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_BUSARB_0_BUS_TURNAROUND_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register EMC_DYN_DQS_0  
+#define EMC_DYN_DQS_0                   _MK_ADDR_CONST(0x78)
+#define EMC_DYN_DQS_0_WORD_COUNT                        0x1
+#define EMC_DYN_DQS_0_RESET_VAL                         _MK_MASK_CONST(0x8000010)
+#define EMC_DYN_DQS_0_RESET_MASK                        _MK_MASK_CONST(0x9f07ff1f)
+#define EMC_DYN_DQS_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define EMC_DYN_DQS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_DYN_DQS_0_READ_MASK                         _MK_MASK_CONST(0x9f07ff1f)
+#define EMC_DYN_DQS_0_WRITE_MASK                        _MK_MASK_CONST(0x9f07ff1f)
+#define EMC_DYN_DQS_0_DYN_DQS_MULT_SHIFT                        _MK_SHIFT_CONST(0)
+#define EMC_DYN_DQS_0_DYN_DQS_MULT_FIELD                        (_MK_MASK_CONST(0x1f) << EMC_DYN_DQS_0_DYN_DQS_MULT_SHIFT)
+#define EMC_DYN_DQS_0_DYN_DQS_MULT_RANGE                        4:0
+#define EMC_DYN_DQS_0_DYN_DQS_MULT_WOFFSET                      0x0
+#define EMC_DYN_DQS_0_DYN_DQS_MULT_DEFAULT                      _MK_MASK_CONST(0x10)
+#define EMC_DYN_DQS_0_DYN_DQS_MULT_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define EMC_DYN_DQS_0_DYN_DQS_MULT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_DYN_DQS_0_DYN_DQS_MULT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define EMC_DYN_DQS_0_DYN_DQS_OFFS_SHIFT                        _MK_SHIFT_CONST(8)
+#define EMC_DYN_DQS_0_DYN_DQS_OFFS_FIELD                        (_MK_MASK_CONST(0x7ff) << EMC_DYN_DQS_0_DYN_DQS_OFFS_SHIFT)
+#define EMC_DYN_DQS_0_DYN_DQS_OFFS_RANGE                        18:8
+#define EMC_DYN_DQS_0_DYN_DQS_OFFS_WOFFSET                      0x0
+#define EMC_DYN_DQS_0_DYN_DQS_OFFS_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_DYN_DQS_0_DYN_DQS_OFFS_DEFAULT_MASK                 _MK_MASK_CONST(0x7ff)
+#define EMC_DYN_DQS_0_DYN_DQS_OFFS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_DYN_DQS_0_DYN_DQS_OFFS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define EMC_DYN_DQS_0_DYN_DQS_MAX_VAL_SHIFT                     _MK_SHIFT_CONST(24)
+#define EMC_DYN_DQS_0_DYN_DQS_MAX_VAL_FIELD                     (_MK_MASK_CONST(0xf) << EMC_DYN_DQS_0_DYN_DQS_MAX_VAL_SHIFT)
+#define EMC_DYN_DQS_0_DYN_DQS_MAX_VAL_RANGE                     27:24
+#define EMC_DYN_DQS_0_DYN_DQS_MAX_VAL_WOFFSET                   0x0
+#define EMC_DYN_DQS_0_DYN_DQS_MAX_VAL_DEFAULT                   _MK_MASK_CONST(0x8)
+#define EMC_DYN_DQS_0_DYN_DQS_MAX_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define EMC_DYN_DQS_0_DYN_DQS_MAX_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_DYN_DQS_0_DYN_DQS_MAX_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define EMC_DYN_DQS_0_DYN_DQS_FREEZE_SHIFT                      _MK_SHIFT_CONST(28)
+#define EMC_DYN_DQS_0_DYN_DQS_FREEZE_FIELD                      (_MK_MASK_CONST(0x1) << EMC_DYN_DQS_0_DYN_DQS_FREEZE_SHIFT)
+#define EMC_DYN_DQS_0_DYN_DQS_FREEZE_RANGE                      28:28
+#define EMC_DYN_DQS_0_DYN_DQS_FREEZE_WOFFSET                    0x0
+#define EMC_DYN_DQS_0_DYN_DQS_FREEZE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_DYN_DQS_0_DYN_DQS_FREEZE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define EMC_DYN_DQS_0_DYN_DQS_FREEZE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_DYN_DQS_0_DYN_DQS_FREEZE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define EMC_DYN_DQS_0_DYN_DQS_ENABLE_SHIFT                      _MK_SHIFT_CONST(31)
+#define EMC_DYN_DQS_0_DYN_DQS_ENABLE_FIELD                      (_MK_MASK_CONST(0x1) << EMC_DYN_DQS_0_DYN_DQS_ENABLE_SHIFT)
+#define EMC_DYN_DQS_0_DYN_DQS_ENABLE_RANGE                      31:31
+#define EMC_DYN_DQS_0_DYN_DQS_ENABLE_WOFFSET                    0x0
+#define EMC_DYN_DQS_0_DYN_DQS_ENABLE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_DYN_DQS_0_DYN_DQS_ENABLE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define EMC_DYN_DQS_0_DYN_DQS_ENABLE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_DYN_DQS_0_DYN_DQS_ENABLE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_DYN_DQS_0_DYN_DQS_ENABLE_INIT_ENUM                  DISABLED
+#define EMC_DYN_DQS_0_DYN_DQS_ENABLE_DISABLED                   _MK_ENUM_CONST(0)
+#define EMC_DYN_DQS_0_DYN_DQS_ENABLE_ENABLED                    _MK_ENUM_CONST(1)
+
+
+// Register EMC_DYN_QUSE_0  
+#define EMC_DYN_QUSE_0                  _MK_ADDR_CONST(0x7c)
+#define EMC_DYN_QUSE_0_WORD_COUNT                       0x1
+#define EMC_DYN_QUSE_0_RESET_VAL                        _MK_MASK_CONST(0x9000008)
+#define EMC_DYN_QUSE_0_RESET_MASK                       _MK_MASK_CONST(0x9f07ff1f)
+#define EMC_DYN_QUSE_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define EMC_DYN_QUSE_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_DYN_QUSE_0_READ_MASK                        _MK_MASK_CONST(0x9f07ff1f)
+#define EMC_DYN_QUSE_0_WRITE_MASK                       _MK_MASK_CONST(0x9f07ff1f)
+#define EMC_DYN_QUSE_0_DYN_QUSE_MULT_SHIFT                      _MK_SHIFT_CONST(0)
+#define EMC_DYN_QUSE_0_DYN_QUSE_MULT_FIELD                      (_MK_MASK_CONST(0x1f) << EMC_DYN_QUSE_0_DYN_QUSE_MULT_SHIFT)
+#define EMC_DYN_QUSE_0_DYN_QUSE_MULT_RANGE                      4:0
+#define EMC_DYN_QUSE_0_DYN_QUSE_MULT_WOFFSET                    0x0
+#define EMC_DYN_QUSE_0_DYN_QUSE_MULT_DEFAULT                    _MK_MASK_CONST(0x8)
+#define EMC_DYN_QUSE_0_DYN_QUSE_MULT_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define EMC_DYN_QUSE_0_DYN_QUSE_MULT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_DYN_QUSE_0_DYN_QUSE_MULT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define EMC_DYN_QUSE_0_DYN_QUSE_OFFS_SHIFT                      _MK_SHIFT_CONST(8)
+#define EMC_DYN_QUSE_0_DYN_QUSE_OFFS_FIELD                      (_MK_MASK_CONST(0x7ff) << EMC_DYN_QUSE_0_DYN_QUSE_OFFS_SHIFT)
+#define EMC_DYN_QUSE_0_DYN_QUSE_OFFS_RANGE                      18:8
+#define EMC_DYN_QUSE_0_DYN_QUSE_OFFS_WOFFSET                    0x0
+#define EMC_DYN_QUSE_0_DYN_QUSE_OFFS_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_DYN_QUSE_0_DYN_QUSE_OFFS_DEFAULT_MASK                       _MK_MASK_CONST(0x7ff)
+#define EMC_DYN_QUSE_0_DYN_QUSE_OFFS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_DYN_QUSE_0_DYN_QUSE_OFFS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define EMC_DYN_QUSE_0_DYN_QUSE_MAX_VAL_SHIFT                   _MK_SHIFT_CONST(24)
+#define EMC_DYN_QUSE_0_DYN_QUSE_MAX_VAL_FIELD                   (_MK_MASK_CONST(0xf) << EMC_DYN_QUSE_0_DYN_QUSE_MAX_VAL_SHIFT)
+#define EMC_DYN_QUSE_0_DYN_QUSE_MAX_VAL_RANGE                   27:24
+#define EMC_DYN_QUSE_0_DYN_QUSE_MAX_VAL_WOFFSET                 0x0
+#define EMC_DYN_QUSE_0_DYN_QUSE_MAX_VAL_DEFAULT                 _MK_MASK_CONST(0x9)
+#define EMC_DYN_QUSE_0_DYN_QUSE_MAX_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define EMC_DYN_QUSE_0_DYN_QUSE_MAX_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_DYN_QUSE_0_DYN_QUSE_MAX_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define EMC_DYN_QUSE_0_DYN_QUSE_FREEZE_SHIFT                    _MK_SHIFT_CONST(28)
+#define EMC_DYN_QUSE_0_DYN_QUSE_FREEZE_FIELD                    (_MK_MASK_CONST(0x1) << EMC_DYN_QUSE_0_DYN_QUSE_FREEZE_SHIFT)
+#define EMC_DYN_QUSE_0_DYN_QUSE_FREEZE_RANGE                    28:28
+#define EMC_DYN_QUSE_0_DYN_QUSE_FREEZE_WOFFSET                  0x0
+#define EMC_DYN_QUSE_0_DYN_QUSE_FREEZE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_DYN_QUSE_0_DYN_QUSE_FREEZE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define EMC_DYN_QUSE_0_DYN_QUSE_FREEZE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_DYN_QUSE_0_DYN_QUSE_FREEZE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define EMC_DYN_QUSE_0_DYN_QUSE_ENABLE_SHIFT                    _MK_SHIFT_CONST(31)
+#define EMC_DYN_QUSE_0_DYN_QUSE_ENABLE_FIELD                    (_MK_MASK_CONST(0x1) << EMC_DYN_QUSE_0_DYN_QUSE_ENABLE_SHIFT)
+#define EMC_DYN_QUSE_0_DYN_QUSE_ENABLE_RANGE                    31:31
+#define EMC_DYN_QUSE_0_DYN_QUSE_ENABLE_WOFFSET                  0x0
+#define EMC_DYN_QUSE_0_DYN_QUSE_ENABLE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_DYN_QUSE_0_DYN_QUSE_ENABLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define EMC_DYN_QUSE_0_DYN_QUSE_ENABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_DYN_QUSE_0_DYN_QUSE_ENABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_DYN_QUSE_0_DYN_QUSE_ENABLE_INIT_ENUM                        DISABLED
+#define EMC_DYN_QUSE_0_DYN_QUSE_ENABLE_DISABLED                 _MK_ENUM_CONST(0)
+#define EMC_DYN_QUSE_0_DYN_QUSE_ENABLE_ENABLED                  _MK_ENUM_CONST(1)
+
+
+// Register EMC_DQS_TRIMMER_RD0_0  
+#define EMC_DQS_TRIMMER_RD0_0                   _MK_ADDR_CONST(0x80)
+#define EMC_DQS_TRIMMER_RD0_0_WORD_COUNT                        0x1
+#define EMC_DQS_TRIMMER_RD0_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD0_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD0_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD0_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD0_0_READ_MASK                         _MK_MASK_CONST(0xe000ffff)
+#define EMC_DQS_TRIMMER_RD0_0_WRITE_MASK                        _MK_MASK_CONST(0xe0000000)
+#define EMC_DQS_TRIMMER_RD0_0_DQS_NEXT_TRIM_VAL_BYTE_0_SHIFT                    _MK_SHIFT_CONST(0)
+#define EMC_DQS_TRIMMER_RD0_0_DQS_NEXT_TRIM_VAL_BYTE_0_FIELD                    (_MK_MASK_CONST(0xff) << EMC_DQS_TRIMMER_RD0_0_DQS_NEXT_TRIM_VAL_BYTE_0_SHIFT)
+#define EMC_DQS_TRIMMER_RD0_0_DQS_NEXT_TRIM_VAL_BYTE_0_RANGE                    7:0
+#define EMC_DQS_TRIMMER_RD0_0_DQS_NEXT_TRIM_VAL_BYTE_0_WOFFSET                  0x0
+#define EMC_DQS_TRIMMER_RD0_0_DQS_NEXT_TRIM_VAL_BYTE_0_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD0_0_DQS_NEXT_TRIM_VAL_BYTE_0_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD0_0_DQS_NEXT_TRIM_VAL_BYTE_0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD0_0_DQS_NEXT_TRIM_VAL_BYTE_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define EMC_DQS_TRIMMER_RD0_0_DQS_CURRENT_TRIM_VAL_BYTE_0_SHIFT                 _MK_SHIFT_CONST(8)
+#define EMC_DQS_TRIMMER_RD0_0_DQS_CURRENT_TRIM_VAL_BYTE_0_FIELD                 (_MK_MASK_CONST(0xff) << EMC_DQS_TRIMMER_RD0_0_DQS_CURRENT_TRIM_VAL_BYTE_0_SHIFT)
+#define EMC_DQS_TRIMMER_RD0_0_DQS_CURRENT_TRIM_VAL_BYTE_0_RANGE                 15:8
+#define EMC_DQS_TRIMMER_RD0_0_DQS_CURRENT_TRIM_VAL_BYTE_0_WOFFSET                       0x0
+#define EMC_DQS_TRIMMER_RD0_0_DQS_CURRENT_TRIM_VAL_BYTE_0_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD0_0_DQS_CURRENT_TRIM_VAL_BYTE_0_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD0_0_DQS_CURRENT_TRIM_VAL_BYTE_0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD0_0_DQS_CURRENT_TRIM_VAL_BYTE_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define EMC_DQS_TRIMMER_RD0_0_DQS_NEXT_NEQ_CURRENT_BYTE_0_SHIFT                 _MK_SHIFT_CONST(29)
+#define EMC_DQS_TRIMMER_RD0_0_DQS_NEXT_NEQ_CURRENT_BYTE_0_FIELD                 (_MK_MASK_CONST(0x1) << EMC_DQS_TRIMMER_RD0_0_DQS_NEXT_NEQ_CURRENT_BYTE_0_SHIFT)
+#define EMC_DQS_TRIMMER_RD0_0_DQS_NEXT_NEQ_CURRENT_BYTE_0_RANGE                 29:29
+#define EMC_DQS_TRIMMER_RD0_0_DQS_NEXT_NEQ_CURRENT_BYTE_0_WOFFSET                       0x0
+#define EMC_DQS_TRIMMER_RD0_0_DQS_NEXT_NEQ_CURRENT_BYTE_0_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD0_0_DQS_NEXT_NEQ_CURRENT_BYTE_0_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD0_0_DQS_NEXT_NEQ_CURRENT_BYTE_0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD0_0_DQS_NEXT_NEQ_CURRENT_BYTE_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define EMC_DQS_TRIMMER_RD0_0_DQS_NEXT_EQ_CURRENT_BYTE_0_SHIFT                  _MK_SHIFT_CONST(30)
+#define EMC_DQS_TRIMMER_RD0_0_DQS_NEXT_EQ_CURRENT_BYTE_0_FIELD                  (_MK_MASK_CONST(0x1) << EMC_DQS_TRIMMER_RD0_0_DQS_NEXT_EQ_CURRENT_BYTE_0_SHIFT)
+#define EMC_DQS_TRIMMER_RD0_0_DQS_NEXT_EQ_CURRENT_BYTE_0_RANGE                  30:30
+#define EMC_DQS_TRIMMER_RD0_0_DQS_NEXT_EQ_CURRENT_BYTE_0_WOFFSET                        0x0
+#define EMC_DQS_TRIMMER_RD0_0_DQS_NEXT_EQ_CURRENT_BYTE_0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD0_0_DQS_NEXT_EQ_CURRENT_BYTE_0_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD0_0_DQS_NEXT_EQ_CURRENT_BYTE_0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD0_0_DQS_NEXT_EQ_CURRENT_BYTE_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define EMC_DQS_TRIMMER_RD0_0_DQS_NEW_CURRENT_VAL_BYTE_0_SHIFT                  _MK_SHIFT_CONST(31)
+#define EMC_DQS_TRIMMER_RD0_0_DQS_NEW_CURRENT_VAL_BYTE_0_FIELD                  (_MK_MASK_CONST(0x1) << EMC_DQS_TRIMMER_RD0_0_DQS_NEW_CURRENT_VAL_BYTE_0_SHIFT)
+#define EMC_DQS_TRIMMER_RD0_0_DQS_NEW_CURRENT_VAL_BYTE_0_RANGE                  31:31
+#define EMC_DQS_TRIMMER_RD0_0_DQS_NEW_CURRENT_VAL_BYTE_0_WOFFSET                        0x0
+#define EMC_DQS_TRIMMER_RD0_0_DQS_NEW_CURRENT_VAL_BYTE_0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD0_0_DQS_NEW_CURRENT_VAL_BYTE_0_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD0_0_DQS_NEW_CURRENT_VAL_BYTE_0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD0_0_DQS_NEW_CURRENT_VAL_BYTE_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register EMC_DQS_TRIMMER_RD1_0  
+#define EMC_DQS_TRIMMER_RD1_0                   _MK_ADDR_CONST(0x84)
+#define EMC_DQS_TRIMMER_RD1_0_WORD_COUNT                        0x1
+#define EMC_DQS_TRIMMER_RD1_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD1_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD1_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD1_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD1_0_READ_MASK                         _MK_MASK_CONST(0xe000ffff)
+#define EMC_DQS_TRIMMER_RD1_0_WRITE_MASK                        _MK_MASK_CONST(0xe0000000)
+#define EMC_DQS_TRIMMER_RD1_0_DQS_NEXT_TRIM_VAL_BYTE_1_SHIFT                    _MK_SHIFT_CONST(0)
+#define EMC_DQS_TRIMMER_RD1_0_DQS_NEXT_TRIM_VAL_BYTE_1_FIELD                    (_MK_MASK_CONST(0xff) << EMC_DQS_TRIMMER_RD1_0_DQS_NEXT_TRIM_VAL_BYTE_1_SHIFT)
+#define EMC_DQS_TRIMMER_RD1_0_DQS_NEXT_TRIM_VAL_BYTE_1_RANGE                    7:0
+#define EMC_DQS_TRIMMER_RD1_0_DQS_NEXT_TRIM_VAL_BYTE_1_WOFFSET                  0x0
+#define EMC_DQS_TRIMMER_RD1_0_DQS_NEXT_TRIM_VAL_BYTE_1_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD1_0_DQS_NEXT_TRIM_VAL_BYTE_1_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD1_0_DQS_NEXT_TRIM_VAL_BYTE_1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD1_0_DQS_NEXT_TRIM_VAL_BYTE_1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define EMC_DQS_TRIMMER_RD1_0_DQS_CURRENT_TRIM_VAL_BYTE_1_SHIFT                 _MK_SHIFT_CONST(8)
+#define EMC_DQS_TRIMMER_RD1_0_DQS_CURRENT_TRIM_VAL_BYTE_1_FIELD                 (_MK_MASK_CONST(0xff) << EMC_DQS_TRIMMER_RD1_0_DQS_CURRENT_TRIM_VAL_BYTE_1_SHIFT)
+#define EMC_DQS_TRIMMER_RD1_0_DQS_CURRENT_TRIM_VAL_BYTE_1_RANGE                 15:8
+#define EMC_DQS_TRIMMER_RD1_0_DQS_CURRENT_TRIM_VAL_BYTE_1_WOFFSET                       0x0
+#define EMC_DQS_TRIMMER_RD1_0_DQS_CURRENT_TRIM_VAL_BYTE_1_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD1_0_DQS_CURRENT_TRIM_VAL_BYTE_1_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD1_0_DQS_CURRENT_TRIM_VAL_BYTE_1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD1_0_DQS_CURRENT_TRIM_VAL_BYTE_1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define EMC_DQS_TRIMMER_RD1_0_DQS_NEXT_NEQ_CURRENT_BYTE_1_SHIFT                 _MK_SHIFT_CONST(29)
+#define EMC_DQS_TRIMMER_RD1_0_DQS_NEXT_NEQ_CURRENT_BYTE_1_FIELD                 (_MK_MASK_CONST(0x1) << EMC_DQS_TRIMMER_RD1_0_DQS_NEXT_NEQ_CURRENT_BYTE_1_SHIFT)
+#define EMC_DQS_TRIMMER_RD1_0_DQS_NEXT_NEQ_CURRENT_BYTE_1_RANGE                 29:29
+#define EMC_DQS_TRIMMER_RD1_0_DQS_NEXT_NEQ_CURRENT_BYTE_1_WOFFSET                       0x0
+#define EMC_DQS_TRIMMER_RD1_0_DQS_NEXT_NEQ_CURRENT_BYTE_1_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD1_0_DQS_NEXT_NEQ_CURRENT_BYTE_1_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD1_0_DQS_NEXT_NEQ_CURRENT_BYTE_1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD1_0_DQS_NEXT_NEQ_CURRENT_BYTE_1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define EMC_DQS_TRIMMER_RD1_0_DQS_NEXT_EQ_CURRENT_BYTE_1_SHIFT                  _MK_SHIFT_CONST(30)
+#define EMC_DQS_TRIMMER_RD1_0_DQS_NEXT_EQ_CURRENT_BYTE_1_FIELD                  (_MK_MASK_CONST(0x1) << EMC_DQS_TRIMMER_RD1_0_DQS_NEXT_EQ_CURRENT_BYTE_1_SHIFT)
+#define EMC_DQS_TRIMMER_RD1_0_DQS_NEXT_EQ_CURRENT_BYTE_1_RANGE                  30:30
+#define EMC_DQS_TRIMMER_RD1_0_DQS_NEXT_EQ_CURRENT_BYTE_1_WOFFSET                        0x0
+#define EMC_DQS_TRIMMER_RD1_0_DQS_NEXT_EQ_CURRENT_BYTE_1_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD1_0_DQS_NEXT_EQ_CURRENT_BYTE_1_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD1_0_DQS_NEXT_EQ_CURRENT_BYTE_1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD1_0_DQS_NEXT_EQ_CURRENT_BYTE_1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define EMC_DQS_TRIMMER_RD1_0_DQS_NEW_CURRENT_VAL_BYTE_1_SHIFT                  _MK_SHIFT_CONST(31)
+#define EMC_DQS_TRIMMER_RD1_0_DQS_NEW_CURRENT_VAL_BYTE_1_FIELD                  (_MK_MASK_CONST(0x1) << EMC_DQS_TRIMMER_RD1_0_DQS_NEW_CURRENT_VAL_BYTE_1_SHIFT)
+#define EMC_DQS_TRIMMER_RD1_0_DQS_NEW_CURRENT_VAL_BYTE_1_RANGE                  31:31
+#define EMC_DQS_TRIMMER_RD1_0_DQS_NEW_CURRENT_VAL_BYTE_1_WOFFSET                        0x0
+#define EMC_DQS_TRIMMER_RD1_0_DQS_NEW_CURRENT_VAL_BYTE_1_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD1_0_DQS_NEW_CURRENT_VAL_BYTE_1_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD1_0_DQS_NEW_CURRENT_VAL_BYTE_1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD1_0_DQS_NEW_CURRENT_VAL_BYTE_1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register EMC_DQS_TRIMMER_RD2_0  
+#define EMC_DQS_TRIMMER_RD2_0                   _MK_ADDR_CONST(0x88)
+#define EMC_DQS_TRIMMER_RD2_0_WORD_COUNT                        0x1
+#define EMC_DQS_TRIMMER_RD2_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD2_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD2_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD2_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD2_0_READ_MASK                         _MK_MASK_CONST(0xe000ffff)
+#define EMC_DQS_TRIMMER_RD2_0_WRITE_MASK                        _MK_MASK_CONST(0xe0000000)
+#define EMC_DQS_TRIMMER_RD2_0_DQS_NEXT_TRIM_VAL_BYTE_2_SHIFT                    _MK_SHIFT_CONST(0)
+#define EMC_DQS_TRIMMER_RD2_0_DQS_NEXT_TRIM_VAL_BYTE_2_FIELD                    (_MK_MASK_CONST(0xff) << EMC_DQS_TRIMMER_RD2_0_DQS_NEXT_TRIM_VAL_BYTE_2_SHIFT)
+#define EMC_DQS_TRIMMER_RD2_0_DQS_NEXT_TRIM_VAL_BYTE_2_RANGE                    7:0
+#define EMC_DQS_TRIMMER_RD2_0_DQS_NEXT_TRIM_VAL_BYTE_2_WOFFSET                  0x0
+#define EMC_DQS_TRIMMER_RD2_0_DQS_NEXT_TRIM_VAL_BYTE_2_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD2_0_DQS_NEXT_TRIM_VAL_BYTE_2_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD2_0_DQS_NEXT_TRIM_VAL_BYTE_2_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD2_0_DQS_NEXT_TRIM_VAL_BYTE_2_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define EMC_DQS_TRIMMER_RD2_0_DQS_CURRENT_TRIM_VAL_BYTE_2_SHIFT                 _MK_SHIFT_CONST(8)
+#define EMC_DQS_TRIMMER_RD2_0_DQS_CURRENT_TRIM_VAL_BYTE_2_FIELD                 (_MK_MASK_CONST(0xff) << EMC_DQS_TRIMMER_RD2_0_DQS_CURRENT_TRIM_VAL_BYTE_2_SHIFT)
+#define EMC_DQS_TRIMMER_RD2_0_DQS_CURRENT_TRIM_VAL_BYTE_2_RANGE                 15:8
+#define EMC_DQS_TRIMMER_RD2_0_DQS_CURRENT_TRIM_VAL_BYTE_2_WOFFSET                       0x0
+#define EMC_DQS_TRIMMER_RD2_0_DQS_CURRENT_TRIM_VAL_BYTE_2_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD2_0_DQS_CURRENT_TRIM_VAL_BYTE_2_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD2_0_DQS_CURRENT_TRIM_VAL_BYTE_2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD2_0_DQS_CURRENT_TRIM_VAL_BYTE_2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define EMC_DQS_TRIMMER_RD2_0_DQS_NEXT_NEQ_CURRENT_BYTE_2_SHIFT                 _MK_SHIFT_CONST(29)
+#define EMC_DQS_TRIMMER_RD2_0_DQS_NEXT_NEQ_CURRENT_BYTE_2_FIELD                 (_MK_MASK_CONST(0x1) << EMC_DQS_TRIMMER_RD2_0_DQS_NEXT_NEQ_CURRENT_BYTE_2_SHIFT)
+#define EMC_DQS_TRIMMER_RD2_0_DQS_NEXT_NEQ_CURRENT_BYTE_2_RANGE                 29:29
+#define EMC_DQS_TRIMMER_RD2_0_DQS_NEXT_NEQ_CURRENT_BYTE_2_WOFFSET                       0x0
+#define EMC_DQS_TRIMMER_RD2_0_DQS_NEXT_NEQ_CURRENT_BYTE_2_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD2_0_DQS_NEXT_NEQ_CURRENT_BYTE_2_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD2_0_DQS_NEXT_NEQ_CURRENT_BYTE_2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD2_0_DQS_NEXT_NEQ_CURRENT_BYTE_2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define EMC_DQS_TRIMMER_RD2_0_DQS_NEXT_EQ_CURRENT_BYTE_2_SHIFT                  _MK_SHIFT_CONST(30)
+#define EMC_DQS_TRIMMER_RD2_0_DQS_NEXT_EQ_CURRENT_BYTE_2_FIELD                  (_MK_MASK_CONST(0x1) << EMC_DQS_TRIMMER_RD2_0_DQS_NEXT_EQ_CURRENT_BYTE_2_SHIFT)
+#define EMC_DQS_TRIMMER_RD2_0_DQS_NEXT_EQ_CURRENT_BYTE_2_RANGE                  30:30
+#define EMC_DQS_TRIMMER_RD2_0_DQS_NEXT_EQ_CURRENT_BYTE_2_WOFFSET                        0x0
+#define EMC_DQS_TRIMMER_RD2_0_DQS_NEXT_EQ_CURRENT_BYTE_2_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD2_0_DQS_NEXT_EQ_CURRENT_BYTE_2_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD2_0_DQS_NEXT_EQ_CURRENT_BYTE_2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD2_0_DQS_NEXT_EQ_CURRENT_BYTE_2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define EMC_DQS_TRIMMER_RD2_0_DQS_NEW_CURRENT_VAL_BYTE_2_SHIFT                  _MK_SHIFT_CONST(31)
+#define EMC_DQS_TRIMMER_RD2_0_DQS_NEW_CURRENT_VAL_BYTE_2_FIELD                  (_MK_MASK_CONST(0x1) << EMC_DQS_TRIMMER_RD2_0_DQS_NEW_CURRENT_VAL_BYTE_2_SHIFT)
+#define EMC_DQS_TRIMMER_RD2_0_DQS_NEW_CURRENT_VAL_BYTE_2_RANGE                  31:31
+#define EMC_DQS_TRIMMER_RD2_0_DQS_NEW_CURRENT_VAL_BYTE_2_WOFFSET                        0x0
+#define EMC_DQS_TRIMMER_RD2_0_DQS_NEW_CURRENT_VAL_BYTE_2_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD2_0_DQS_NEW_CURRENT_VAL_BYTE_2_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD2_0_DQS_NEW_CURRENT_VAL_BYTE_2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD2_0_DQS_NEW_CURRENT_VAL_BYTE_2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register EMC_DQS_TRIMMER_RD3_0  
+#define EMC_DQS_TRIMMER_RD3_0                   _MK_ADDR_CONST(0x8c)
+#define EMC_DQS_TRIMMER_RD3_0_WORD_COUNT                        0x1
+#define EMC_DQS_TRIMMER_RD3_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD3_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD3_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD3_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD3_0_READ_MASK                         _MK_MASK_CONST(0xe000ffff)
+#define EMC_DQS_TRIMMER_RD3_0_WRITE_MASK                        _MK_MASK_CONST(0xe0000000)
+#define EMC_DQS_TRIMMER_RD3_0_DQS_NEXT_TRIM_VAL_BYTE_3_SHIFT                    _MK_SHIFT_CONST(0)
+#define EMC_DQS_TRIMMER_RD3_0_DQS_NEXT_TRIM_VAL_BYTE_3_FIELD                    (_MK_MASK_CONST(0xff) << EMC_DQS_TRIMMER_RD3_0_DQS_NEXT_TRIM_VAL_BYTE_3_SHIFT)
+#define EMC_DQS_TRIMMER_RD3_0_DQS_NEXT_TRIM_VAL_BYTE_3_RANGE                    7:0
+#define EMC_DQS_TRIMMER_RD3_0_DQS_NEXT_TRIM_VAL_BYTE_3_WOFFSET                  0x0
+#define EMC_DQS_TRIMMER_RD3_0_DQS_NEXT_TRIM_VAL_BYTE_3_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD3_0_DQS_NEXT_TRIM_VAL_BYTE_3_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD3_0_DQS_NEXT_TRIM_VAL_BYTE_3_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD3_0_DQS_NEXT_TRIM_VAL_BYTE_3_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define EMC_DQS_TRIMMER_RD3_0_DQS_CURRENT_TRIM_VAL_BYTE_3_SHIFT                 _MK_SHIFT_CONST(8)
+#define EMC_DQS_TRIMMER_RD3_0_DQS_CURRENT_TRIM_VAL_BYTE_3_FIELD                 (_MK_MASK_CONST(0xff) << EMC_DQS_TRIMMER_RD3_0_DQS_CURRENT_TRIM_VAL_BYTE_3_SHIFT)
+#define EMC_DQS_TRIMMER_RD3_0_DQS_CURRENT_TRIM_VAL_BYTE_3_RANGE                 15:8
+#define EMC_DQS_TRIMMER_RD3_0_DQS_CURRENT_TRIM_VAL_BYTE_3_WOFFSET                       0x0
+#define EMC_DQS_TRIMMER_RD3_0_DQS_CURRENT_TRIM_VAL_BYTE_3_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD3_0_DQS_CURRENT_TRIM_VAL_BYTE_3_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD3_0_DQS_CURRENT_TRIM_VAL_BYTE_3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD3_0_DQS_CURRENT_TRIM_VAL_BYTE_3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define EMC_DQS_TRIMMER_RD3_0_DQS_NEXT_NEQ_CURRENT_BYTE_3_SHIFT                 _MK_SHIFT_CONST(29)
+#define EMC_DQS_TRIMMER_RD3_0_DQS_NEXT_NEQ_CURRENT_BYTE_3_FIELD                 (_MK_MASK_CONST(0x1) << EMC_DQS_TRIMMER_RD3_0_DQS_NEXT_NEQ_CURRENT_BYTE_3_SHIFT)
+#define EMC_DQS_TRIMMER_RD3_0_DQS_NEXT_NEQ_CURRENT_BYTE_3_RANGE                 29:29
+#define EMC_DQS_TRIMMER_RD3_0_DQS_NEXT_NEQ_CURRENT_BYTE_3_WOFFSET                       0x0
+#define EMC_DQS_TRIMMER_RD3_0_DQS_NEXT_NEQ_CURRENT_BYTE_3_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD3_0_DQS_NEXT_NEQ_CURRENT_BYTE_3_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD3_0_DQS_NEXT_NEQ_CURRENT_BYTE_3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD3_0_DQS_NEXT_NEQ_CURRENT_BYTE_3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define EMC_DQS_TRIMMER_RD3_0_DQS_NEXT_EQ_CURRENT_BYTE_3_SHIFT                  _MK_SHIFT_CONST(30)
+#define EMC_DQS_TRIMMER_RD3_0_DQS_NEXT_EQ_CURRENT_BYTE_3_FIELD                  (_MK_MASK_CONST(0x1) << EMC_DQS_TRIMMER_RD3_0_DQS_NEXT_EQ_CURRENT_BYTE_3_SHIFT)
+#define EMC_DQS_TRIMMER_RD3_0_DQS_NEXT_EQ_CURRENT_BYTE_3_RANGE                  30:30
+#define EMC_DQS_TRIMMER_RD3_0_DQS_NEXT_EQ_CURRENT_BYTE_3_WOFFSET                        0x0
+#define EMC_DQS_TRIMMER_RD3_0_DQS_NEXT_EQ_CURRENT_BYTE_3_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD3_0_DQS_NEXT_EQ_CURRENT_BYTE_3_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD3_0_DQS_NEXT_EQ_CURRENT_BYTE_3_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD3_0_DQS_NEXT_EQ_CURRENT_BYTE_3_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define EMC_DQS_TRIMMER_RD3_0_DQS_NEW_CURRENT_VAL_BYTE_3_SHIFT                  _MK_SHIFT_CONST(31)
+#define EMC_DQS_TRIMMER_RD3_0_DQS_NEW_CURRENT_VAL_BYTE_3_FIELD                  (_MK_MASK_CONST(0x1) << EMC_DQS_TRIMMER_RD3_0_DQS_NEW_CURRENT_VAL_BYTE_3_SHIFT)
+#define EMC_DQS_TRIMMER_RD3_0_DQS_NEW_CURRENT_VAL_BYTE_3_RANGE                  31:31
+#define EMC_DQS_TRIMMER_RD3_0_DQS_NEW_CURRENT_VAL_BYTE_3_WOFFSET                        0x0
+#define EMC_DQS_TRIMMER_RD3_0_DQS_NEW_CURRENT_VAL_BYTE_3_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD3_0_DQS_NEW_CURRENT_VAL_BYTE_3_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD3_0_DQS_NEW_CURRENT_VAL_BYTE_3_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD3_0_DQS_NEW_CURRENT_VAL_BYTE_3_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register EMC_QUSE_TRIMMER_RD0_0  
+#define EMC_QUSE_TRIMMER_RD0_0                  _MK_ADDR_CONST(0x90)
+#define EMC_QUSE_TRIMMER_RD0_0_WORD_COUNT                       0x1
+#define EMC_QUSE_TRIMMER_RD0_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD0_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD0_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD0_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD0_0_READ_MASK                        _MK_MASK_CONST(0xe000ffff)
+#define EMC_QUSE_TRIMMER_RD0_0_WRITE_MASK                       _MK_MASK_CONST(0xe0000000)
+#define EMC_QUSE_TRIMMER_RD0_0_QUSE_NEXT_TRIM_VAL_BYTE_0_SHIFT                  _MK_SHIFT_CONST(0)
+#define EMC_QUSE_TRIMMER_RD0_0_QUSE_NEXT_TRIM_VAL_BYTE_0_FIELD                  (_MK_MASK_CONST(0xff) << EMC_QUSE_TRIMMER_RD0_0_QUSE_NEXT_TRIM_VAL_BYTE_0_SHIFT)
+#define EMC_QUSE_TRIMMER_RD0_0_QUSE_NEXT_TRIM_VAL_BYTE_0_RANGE                  7:0
+#define EMC_QUSE_TRIMMER_RD0_0_QUSE_NEXT_TRIM_VAL_BYTE_0_WOFFSET                        0x0
+#define EMC_QUSE_TRIMMER_RD0_0_QUSE_NEXT_TRIM_VAL_BYTE_0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD0_0_QUSE_NEXT_TRIM_VAL_BYTE_0_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD0_0_QUSE_NEXT_TRIM_VAL_BYTE_0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD0_0_QUSE_NEXT_TRIM_VAL_BYTE_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define EMC_QUSE_TRIMMER_RD0_0_QUSE_CURRENT_TRIM_VAL_BYTE_0_SHIFT                       _MK_SHIFT_CONST(8)
+#define EMC_QUSE_TRIMMER_RD0_0_QUSE_CURRENT_TRIM_VAL_BYTE_0_FIELD                       (_MK_MASK_CONST(0xff) << EMC_QUSE_TRIMMER_RD0_0_QUSE_CURRENT_TRIM_VAL_BYTE_0_SHIFT)
+#define EMC_QUSE_TRIMMER_RD0_0_QUSE_CURRENT_TRIM_VAL_BYTE_0_RANGE                       15:8
+#define EMC_QUSE_TRIMMER_RD0_0_QUSE_CURRENT_TRIM_VAL_BYTE_0_WOFFSET                     0x0
+#define EMC_QUSE_TRIMMER_RD0_0_QUSE_CURRENT_TRIM_VAL_BYTE_0_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD0_0_QUSE_CURRENT_TRIM_VAL_BYTE_0_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD0_0_QUSE_CURRENT_TRIM_VAL_BYTE_0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD0_0_QUSE_CURRENT_TRIM_VAL_BYTE_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define EMC_QUSE_TRIMMER_RD0_0_QUSE_NEXT_NEQ_CURRENT_BYTE_0_SHIFT                       _MK_SHIFT_CONST(29)
+#define EMC_QUSE_TRIMMER_RD0_0_QUSE_NEXT_NEQ_CURRENT_BYTE_0_FIELD                       (_MK_MASK_CONST(0x1) << EMC_QUSE_TRIMMER_RD0_0_QUSE_NEXT_NEQ_CURRENT_BYTE_0_SHIFT)
+#define EMC_QUSE_TRIMMER_RD0_0_QUSE_NEXT_NEQ_CURRENT_BYTE_0_RANGE                       29:29
+#define EMC_QUSE_TRIMMER_RD0_0_QUSE_NEXT_NEQ_CURRENT_BYTE_0_WOFFSET                     0x0
+#define EMC_QUSE_TRIMMER_RD0_0_QUSE_NEXT_NEQ_CURRENT_BYTE_0_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD0_0_QUSE_NEXT_NEQ_CURRENT_BYTE_0_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD0_0_QUSE_NEXT_NEQ_CURRENT_BYTE_0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD0_0_QUSE_NEXT_NEQ_CURRENT_BYTE_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define EMC_QUSE_TRIMMER_RD0_0_QUSE_NEXT_EQ_CURRENT_BYTE_0_SHIFT                        _MK_SHIFT_CONST(30)
+#define EMC_QUSE_TRIMMER_RD0_0_QUSE_NEXT_EQ_CURRENT_BYTE_0_FIELD                        (_MK_MASK_CONST(0x1) << EMC_QUSE_TRIMMER_RD0_0_QUSE_NEXT_EQ_CURRENT_BYTE_0_SHIFT)
+#define EMC_QUSE_TRIMMER_RD0_0_QUSE_NEXT_EQ_CURRENT_BYTE_0_RANGE                        30:30
+#define EMC_QUSE_TRIMMER_RD0_0_QUSE_NEXT_EQ_CURRENT_BYTE_0_WOFFSET                      0x0
+#define EMC_QUSE_TRIMMER_RD0_0_QUSE_NEXT_EQ_CURRENT_BYTE_0_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD0_0_QUSE_NEXT_EQ_CURRENT_BYTE_0_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD0_0_QUSE_NEXT_EQ_CURRENT_BYTE_0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD0_0_QUSE_NEXT_EQ_CURRENT_BYTE_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define EMC_QUSE_TRIMMER_RD0_0_QUSE_NEW_CURRENT_VAL_BYTE_0_SHIFT                        _MK_SHIFT_CONST(31)
+#define EMC_QUSE_TRIMMER_RD0_0_QUSE_NEW_CURRENT_VAL_BYTE_0_FIELD                        (_MK_MASK_CONST(0x1) << EMC_QUSE_TRIMMER_RD0_0_QUSE_NEW_CURRENT_VAL_BYTE_0_SHIFT)
+#define EMC_QUSE_TRIMMER_RD0_0_QUSE_NEW_CURRENT_VAL_BYTE_0_RANGE                        31:31
+#define EMC_QUSE_TRIMMER_RD0_0_QUSE_NEW_CURRENT_VAL_BYTE_0_WOFFSET                      0x0
+#define EMC_QUSE_TRIMMER_RD0_0_QUSE_NEW_CURRENT_VAL_BYTE_0_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD0_0_QUSE_NEW_CURRENT_VAL_BYTE_0_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD0_0_QUSE_NEW_CURRENT_VAL_BYTE_0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD0_0_QUSE_NEW_CURRENT_VAL_BYTE_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register EMC_QUSE_TRIMMER_RD1_0  
+#define EMC_QUSE_TRIMMER_RD1_0                  _MK_ADDR_CONST(0x94)
+#define EMC_QUSE_TRIMMER_RD1_0_WORD_COUNT                       0x1
+#define EMC_QUSE_TRIMMER_RD1_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD1_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD1_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD1_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD1_0_READ_MASK                        _MK_MASK_CONST(0xe000ffff)
+#define EMC_QUSE_TRIMMER_RD1_0_WRITE_MASK                       _MK_MASK_CONST(0xe0000000)
+#define EMC_QUSE_TRIMMER_RD1_0_QUSE_NEXT_TRIM_VAL_BYTE_1_SHIFT                  _MK_SHIFT_CONST(0)
+#define EMC_QUSE_TRIMMER_RD1_0_QUSE_NEXT_TRIM_VAL_BYTE_1_FIELD                  (_MK_MASK_CONST(0xff) << EMC_QUSE_TRIMMER_RD1_0_QUSE_NEXT_TRIM_VAL_BYTE_1_SHIFT)
+#define EMC_QUSE_TRIMMER_RD1_0_QUSE_NEXT_TRIM_VAL_BYTE_1_RANGE                  7:0
+#define EMC_QUSE_TRIMMER_RD1_0_QUSE_NEXT_TRIM_VAL_BYTE_1_WOFFSET                        0x0
+#define EMC_QUSE_TRIMMER_RD1_0_QUSE_NEXT_TRIM_VAL_BYTE_1_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD1_0_QUSE_NEXT_TRIM_VAL_BYTE_1_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD1_0_QUSE_NEXT_TRIM_VAL_BYTE_1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD1_0_QUSE_NEXT_TRIM_VAL_BYTE_1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define EMC_QUSE_TRIMMER_RD1_0_QUSE_CURRENT_TRIM_VAL_BYTE_1_SHIFT                       _MK_SHIFT_CONST(8)
+#define EMC_QUSE_TRIMMER_RD1_0_QUSE_CURRENT_TRIM_VAL_BYTE_1_FIELD                       (_MK_MASK_CONST(0xff) << EMC_QUSE_TRIMMER_RD1_0_QUSE_CURRENT_TRIM_VAL_BYTE_1_SHIFT)
+#define EMC_QUSE_TRIMMER_RD1_0_QUSE_CURRENT_TRIM_VAL_BYTE_1_RANGE                       15:8
+#define EMC_QUSE_TRIMMER_RD1_0_QUSE_CURRENT_TRIM_VAL_BYTE_1_WOFFSET                     0x0
+#define EMC_QUSE_TRIMMER_RD1_0_QUSE_CURRENT_TRIM_VAL_BYTE_1_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD1_0_QUSE_CURRENT_TRIM_VAL_BYTE_1_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD1_0_QUSE_CURRENT_TRIM_VAL_BYTE_1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD1_0_QUSE_CURRENT_TRIM_VAL_BYTE_1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define EMC_QUSE_TRIMMER_RD1_0_QUSE_NEXT_NEQ_CURRENT_BYTE_1_SHIFT                       _MK_SHIFT_CONST(29)
+#define EMC_QUSE_TRIMMER_RD1_0_QUSE_NEXT_NEQ_CURRENT_BYTE_1_FIELD                       (_MK_MASK_CONST(0x1) << EMC_QUSE_TRIMMER_RD1_0_QUSE_NEXT_NEQ_CURRENT_BYTE_1_SHIFT)
+#define EMC_QUSE_TRIMMER_RD1_0_QUSE_NEXT_NEQ_CURRENT_BYTE_1_RANGE                       29:29
+#define EMC_QUSE_TRIMMER_RD1_0_QUSE_NEXT_NEQ_CURRENT_BYTE_1_WOFFSET                     0x0
+#define EMC_QUSE_TRIMMER_RD1_0_QUSE_NEXT_NEQ_CURRENT_BYTE_1_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD1_0_QUSE_NEXT_NEQ_CURRENT_BYTE_1_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD1_0_QUSE_NEXT_NEQ_CURRENT_BYTE_1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD1_0_QUSE_NEXT_NEQ_CURRENT_BYTE_1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define EMC_QUSE_TRIMMER_RD1_0_QUSE_NEXT_EQ_CURRENT_BYTE_1_SHIFT                        _MK_SHIFT_CONST(30)
+#define EMC_QUSE_TRIMMER_RD1_0_QUSE_NEXT_EQ_CURRENT_BYTE_1_FIELD                        (_MK_MASK_CONST(0x1) << EMC_QUSE_TRIMMER_RD1_0_QUSE_NEXT_EQ_CURRENT_BYTE_1_SHIFT)
+#define EMC_QUSE_TRIMMER_RD1_0_QUSE_NEXT_EQ_CURRENT_BYTE_1_RANGE                        30:30
+#define EMC_QUSE_TRIMMER_RD1_0_QUSE_NEXT_EQ_CURRENT_BYTE_1_WOFFSET                      0x0
+#define EMC_QUSE_TRIMMER_RD1_0_QUSE_NEXT_EQ_CURRENT_BYTE_1_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD1_0_QUSE_NEXT_EQ_CURRENT_BYTE_1_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD1_0_QUSE_NEXT_EQ_CURRENT_BYTE_1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD1_0_QUSE_NEXT_EQ_CURRENT_BYTE_1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define EMC_QUSE_TRIMMER_RD1_0_QUSE_NEW_CURRENT_VAL_BYTE_1_SHIFT                        _MK_SHIFT_CONST(31)
+#define EMC_QUSE_TRIMMER_RD1_0_QUSE_NEW_CURRENT_VAL_BYTE_1_FIELD                        (_MK_MASK_CONST(0x1) << EMC_QUSE_TRIMMER_RD1_0_QUSE_NEW_CURRENT_VAL_BYTE_1_SHIFT)
+#define EMC_QUSE_TRIMMER_RD1_0_QUSE_NEW_CURRENT_VAL_BYTE_1_RANGE                        31:31
+#define EMC_QUSE_TRIMMER_RD1_0_QUSE_NEW_CURRENT_VAL_BYTE_1_WOFFSET                      0x0
+#define EMC_QUSE_TRIMMER_RD1_0_QUSE_NEW_CURRENT_VAL_BYTE_1_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD1_0_QUSE_NEW_CURRENT_VAL_BYTE_1_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD1_0_QUSE_NEW_CURRENT_VAL_BYTE_1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD1_0_QUSE_NEW_CURRENT_VAL_BYTE_1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register EMC_QUSE_TRIMMER_RD2_0  
+#define EMC_QUSE_TRIMMER_RD2_0                  _MK_ADDR_CONST(0x98)
+#define EMC_QUSE_TRIMMER_RD2_0_WORD_COUNT                       0x1
+#define EMC_QUSE_TRIMMER_RD2_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD2_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD2_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD2_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD2_0_READ_MASK                        _MK_MASK_CONST(0xe000ffff)
+#define EMC_QUSE_TRIMMER_RD2_0_WRITE_MASK                       _MK_MASK_CONST(0xe0000000)
+#define EMC_QUSE_TRIMMER_RD2_0_QUSE_NEXT_TRIM_VAL_BYTE_2_SHIFT                  _MK_SHIFT_CONST(0)
+#define EMC_QUSE_TRIMMER_RD2_0_QUSE_NEXT_TRIM_VAL_BYTE_2_FIELD                  (_MK_MASK_CONST(0xff) << EMC_QUSE_TRIMMER_RD2_0_QUSE_NEXT_TRIM_VAL_BYTE_2_SHIFT)
+#define EMC_QUSE_TRIMMER_RD2_0_QUSE_NEXT_TRIM_VAL_BYTE_2_RANGE                  7:0
+#define EMC_QUSE_TRIMMER_RD2_0_QUSE_NEXT_TRIM_VAL_BYTE_2_WOFFSET                        0x0
+#define EMC_QUSE_TRIMMER_RD2_0_QUSE_NEXT_TRIM_VAL_BYTE_2_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD2_0_QUSE_NEXT_TRIM_VAL_BYTE_2_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD2_0_QUSE_NEXT_TRIM_VAL_BYTE_2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD2_0_QUSE_NEXT_TRIM_VAL_BYTE_2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define EMC_QUSE_TRIMMER_RD2_0_QUSE_CURRENT_TRIM_VAL_BYTE_2_SHIFT                       _MK_SHIFT_CONST(8)
+#define EMC_QUSE_TRIMMER_RD2_0_QUSE_CURRENT_TRIM_VAL_BYTE_2_FIELD                       (_MK_MASK_CONST(0xff) << EMC_QUSE_TRIMMER_RD2_0_QUSE_CURRENT_TRIM_VAL_BYTE_2_SHIFT)
+#define EMC_QUSE_TRIMMER_RD2_0_QUSE_CURRENT_TRIM_VAL_BYTE_2_RANGE                       15:8
+#define EMC_QUSE_TRIMMER_RD2_0_QUSE_CURRENT_TRIM_VAL_BYTE_2_WOFFSET                     0x0
+#define EMC_QUSE_TRIMMER_RD2_0_QUSE_CURRENT_TRIM_VAL_BYTE_2_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD2_0_QUSE_CURRENT_TRIM_VAL_BYTE_2_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD2_0_QUSE_CURRENT_TRIM_VAL_BYTE_2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD2_0_QUSE_CURRENT_TRIM_VAL_BYTE_2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define EMC_QUSE_TRIMMER_RD2_0_QUSE_NEXT_NEQ_CURRENT_BYTE_2_SHIFT                       _MK_SHIFT_CONST(29)
+#define EMC_QUSE_TRIMMER_RD2_0_QUSE_NEXT_NEQ_CURRENT_BYTE_2_FIELD                       (_MK_MASK_CONST(0x1) << EMC_QUSE_TRIMMER_RD2_0_QUSE_NEXT_NEQ_CURRENT_BYTE_2_SHIFT)
+#define EMC_QUSE_TRIMMER_RD2_0_QUSE_NEXT_NEQ_CURRENT_BYTE_2_RANGE                       29:29
+#define EMC_QUSE_TRIMMER_RD2_0_QUSE_NEXT_NEQ_CURRENT_BYTE_2_WOFFSET                     0x0
+#define EMC_QUSE_TRIMMER_RD2_0_QUSE_NEXT_NEQ_CURRENT_BYTE_2_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD2_0_QUSE_NEXT_NEQ_CURRENT_BYTE_2_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD2_0_QUSE_NEXT_NEQ_CURRENT_BYTE_2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD2_0_QUSE_NEXT_NEQ_CURRENT_BYTE_2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define EMC_QUSE_TRIMMER_RD2_0_QUSE_NEXT_EQ_CURRENT_BYTE_2_SHIFT                        _MK_SHIFT_CONST(30)
+#define EMC_QUSE_TRIMMER_RD2_0_QUSE_NEXT_EQ_CURRENT_BYTE_2_FIELD                        (_MK_MASK_CONST(0x1) << EMC_QUSE_TRIMMER_RD2_0_QUSE_NEXT_EQ_CURRENT_BYTE_2_SHIFT)
+#define EMC_QUSE_TRIMMER_RD2_0_QUSE_NEXT_EQ_CURRENT_BYTE_2_RANGE                        30:30
+#define EMC_QUSE_TRIMMER_RD2_0_QUSE_NEXT_EQ_CURRENT_BYTE_2_WOFFSET                      0x0
+#define EMC_QUSE_TRIMMER_RD2_0_QUSE_NEXT_EQ_CURRENT_BYTE_2_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD2_0_QUSE_NEXT_EQ_CURRENT_BYTE_2_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD2_0_QUSE_NEXT_EQ_CURRENT_BYTE_2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD2_0_QUSE_NEXT_EQ_CURRENT_BYTE_2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define EMC_QUSE_TRIMMER_RD2_0_QUSE_NEW_CURRENT_VAL_BYTE_2_SHIFT                        _MK_SHIFT_CONST(31)
+#define EMC_QUSE_TRIMMER_RD2_0_QUSE_NEW_CURRENT_VAL_BYTE_2_FIELD                        (_MK_MASK_CONST(0x1) << EMC_QUSE_TRIMMER_RD2_0_QUSE_NEW_CURRENT_VAL_BYTE_2_SHIFT)
+#define EMC_QUSE_TRIMMER_RD2_0_QUSE_NEW_CURRENT_VAL_BYTE_2_RANGE                        31:31
+#define EMC_QUSE_TRIMMER_RD2_0_QUSE_NEW_CURRENT_VAL_BYTE_2_WOFFSET                      0x0
+#define EMC_QUSE_TRIMMER_RD2_0_QUSE_NEW_CURRENT_VAL_BYTE_2_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD2_0_QUSE_NEW_CURRENT_VAL_BYTE_2_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD2_0_QUSE_NEW_CURRENT_VAL_BYTE_2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD2_0_QUSE_NEW_CURRENT_VAL_BYTE_2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register EMC_QUSE_TRIMMER_RD3_0  
+#define EMC_QUSE_TRIMMER_RD3_0                  _MK_ADDR_CONST(0x9c)
+#define EMC_QUSE_TRIMMER_RD3_0_WORD_COUNT                       0x1
+#define EMC_QUSE_TRIMMER_RD3_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD3_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD3_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD3_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD3_0_READ_MASK                        _MK_MASK_CONST(0xe000ffff)
+#define EMC_QUSE_TRIMMER_RD3_0_WRITE_MASK                       _MK_MASK_CONST(0xe0000000)
+#define EMC_QUSE_TRIMMER_RD3_0_QUSE_NEXT_TRIM_VAL_BYTE_3_SHIFT                  _MK_SHIFT_CONST(0)
+#define EMC_QUSE_TRIMMER_RD3_0_QUSE_NEXT_TRIM_VAL_BYTE_3_FIELD                  (_MK_MASK_CONST(0xff) << EMC_QUSE_TRIMMER_RD3_0_QUSE_NEXT_TRIM_VAL_BYTE_3_SHIFT)
+#define EMC_QUSE_TRIMMER_RD3_0_QUSE_NEXT_TRIM_VAL_BYTE_3_RANGE                  7:0
+#define EMC_QUSE_TRIMMER_RD3_0_QUSE_NEXT_TRIM_VAL_BYTE_3_WOFFSET                        0x0
+#define EMC_QUSE_TRIMMER_RD3_0_QUSE_NEXT_TRIM_VAL_BYTE_3_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD3_0_QUSE_NEXT_TRIM_VAL_BYTE_3_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD3_0_QUSE_NEXT_TRIM_VAL_BYTE_3_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD3_0_QUSE_NEXT_TRIM_VAL_BYTE_3_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define EMC_QUSE_TRIMMER_RD3_0_QUSE_CURRENT_TRIM_VAL_BYTE_3_SHIFT                       _MK_SHIFT_CONST(8)
+#define EMC_QUSE_TRIMMER_RD3_0_QUSE_CURRENT_TRIM_VAL_BYTE_3_FIELD                       (_MK_MASK_CONST(0xff) << EMC_QUSE_TRIMMER_RD3_0_QUSE_CURRENT_TRIM_VAL_BYTE_3_SHIFT)
+#define EMC_QUSE_TRIMMER_RD3_0_QUSE_CURRENT_TRIM_VAL_BYTE_3_RANGE                       15:8
+#define EMC_QUSE_TRIMMER_RD3_0_QUSE_CURRENT_TRIM_VAL_BYTE_3_WOFFSET                     0x0
+#define EMC_QUSE_TRIMMER_RD3_0_QUSE_CURRENT_TRIM_VAL_BYTE_3_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD3_0_QUSE_CURRENT_TRIM_VAL_BYTE_3_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD3_0_QUSE_CURRENT_TRIM_VAL_BYTE_3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD3_0_QUSE_CURRENT_TRIM_VAL_BYTE_3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define EMC_QUSE_TRIMMER_RD3_0_QUSE_NEXT_NEQ_CURRENT_BYTE_3_SHIFT                       _MK_SHIFT_CONST(29)
+#define EMC_QUSE_TRIMMER_RD3_0_QUSE_NEXT_NEQ_CURRENT_BYTE_3_FIELD                       (_MK_MASK_CONST(0x1) << EMC_QUSE_TRIMMER_RD3_0_QUSE_NEXT_NEQ_CURRENT_BYTE_3_SHIFT)
+#define EMC_QUSE_TRIMMER_RD3_0_QUSE_NEXT_NEQ_CURRENT_BYTE_3_RANGE                       29:29
+#define EMC_QUSE_TRIMMER_RD3_0_QUSE_NEXT_NEQ_CURRENT_BYTE_3_WOFFSET                     0x0
+#define EMC_QUSE_TRIMMER_RD3_0_QUSE_NEXT_NEQ_CURRENT_BYTE_3_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD3_0_QUSE_NEXT_NEQ_CURRENT_BYTE_3_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD3_0_QUSE_NEXT_NEQ_CURRENT_BYTE_3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD3_0_QUSE_NEXT_NEQ_CURRENT_BYTE_3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define EMC_QUSE_TRIMMER_RD3_0_QUSE_NEXT_EQ_CURRENT_BYTE_3_SHIFT                        _MK_SHIFT_CONST(30)
+#define EMC_QUSE_TRIMMER_RD3_0_QUSE_NEXT_EQ_CURRENT_BYTE_3_FIELD                        (_MK_MASK_CONST(0x1) << EMC_QUSE_TRIMMER_RD3_0_QUSE_NEXT_EQ_CURRENT_BYTE_3_SHIFT)
+#define EMC_QUSE_TRIMMER_RD3_0_QUSE_NEXT_EQ_CURRENT_BYTE_3_RANGE                        30:30
+#define EMC_QUSE_TRIMMER_RD3_0_QUSE_NEXT_EQ_CURRENT_BYTE_3_WOFFSET                      0x0
+#define EMC_QUSE_TRIMMER_RD3_0_QUSE_NEXT_EQ_CURRENT_BYTE_3_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD3_0_QUSE_NEXT_EQ_CURRENT_BYTE_3_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD3_0_QUSE_NEXT_EQ_CURRENT_BYTE_3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD3_0_QUSE_NEXT_EQ_CURRENT_BYTE_3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define EMC_QUSE_TRIMMER_RD3_0_QUSE_NEW_CURRENT_VAL_BYTE_3_SHIFT                        _MK_SHIFT_CONST(31)
+#define EMC_QUSE_TRIMMER_RD3_0_QUSE_NEW_CURRENT_VAL_BYTE_3_FIELD                        (_MK_MASK_CONST(0x1) << EMC_QUSE_TRIMMER_RD3_0_QUSE_NEW_CURRENT_VAL_BYTE_3_SHIFT)
+#define EMC_QUSE_TRIMMER_RD3_0_QUSE_NEW_CURRENT_VAL_BYTE_3_RANGE                        31:31
+#define EMC_QUSE_TRIMMER_RD3_0_QUSE_NEW_CURRENT_VAL_BYTE_3_WOFFSET                      0x0
+#define EMC_QUSE_TRIMMER_RD3_0_QUSE_NEW_CURRENT_VAL_BYTE_3_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD3_0_QUSE_NEW_CURRENT_VAL_BYTE_3_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD3_0_QUSE_NEW_CURRENT_VAL_BYTE_3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD3_0_QUSE_NEW_CURRENT_VAL_BYTE_3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register EMC_CLKEN_OVERRIDE_0  
+#define EMC_CLKEN_OVERRIDE_0                    _MK_ADDR_CONST(0xa0)
+#define EMC_CLKEN_OVERRIDE_0_WORD_COUNT                         0x1
+#define EMC_CLKEN_OVERRIDE_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define EMC_CLKEN_OVERRIDE_0_RESET_MASK                         _MK_MASK_CONST(0x3f)
+#define EMC_CLKEN_OVERRIDE_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define EMC_CLKEN_OVERRIDE_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_CLKEN_OVERRIDE_0_READ_MASK                  _MK_MASK_CONST(0x3f)
+#define EMC_CLKEN_OVERRIDE_0_WRITE_MASK                         _MK_MASK_CONST(0x3f)
+#define EMC_CLKEN_OVERRIDE_0_ARB_CLKEN_OVR_SHIFT                        _MK_SHIFT_CONST(0)
+#define EMC_CLKEN_OVERRIDE_0_ARB_CLKEN_OVR_FIELD                        (_MK_MASK_CONST(0x1) << EMC_CLKEN_OVERRIDE_0_ARB_CLKEN_OVR_SHIFT)
+#define EMC_CLKEN_OVERRIDE_0_ARB_CLKEN_OVR_RANGE                        0:0
+#define EMC_CLKEN_OVERRIDE_0_ARB_CLKEN_OVR_WOFFSET                      0x0
+#define EMC_CLKEN_OVERRIDE_0_ARB_CLKEN_OVR_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_CLKEN_OVERRIDE_0_ARB_CLKEN_OVR_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define EMC_CLKEN_OVERRIDE_0_ARB_CLKEN_OVR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_CLKEN_OVERRIDE_0_ARB_CLKEN_OVR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_CLKEN_OVERRIDE_0_ARB_CLKEN_OVR_INIT_ENUM                    CLK_GATED
+#define EMC_CLKEN_OVERRIDE_0_ARB_CLKEN_OVR_CLK_GATED                    _MK_ENUM_CONST(0)
+#define EMC_CLKEN_OVERRIDE_0_ARB_CLKEN_OVR_CLK_ALWAYS_ON                        _MK_ENUM_CONST(1)
+#define EMC_CLKEN_OVERRIDE_0_ARB_CLKEN_OVR_DISABLE                      _MK_ENUM_CONST(0)
+#define EMC_CLKEN_OVERRIDE_0_ARB_CLKEN_OVR_ENABLE                       _MK_ENUM_CONST(1)
+#define EMC_CLKEN_OVERRIDE_0_ARB_CLKEN_OVR_DISABLED                     _MK_ENUM_CONST(0)
+#define EMC_CLKEN_OVERRIDE_0_ARB_CLKEN_OVR_ENABLED                      _MK_ENUM_CONST(1)
+
+#define EMC_CLKEN_OVERRIDE_0_CMDQ_CLKEN_OVR_SHIFT                       _MK_SHIFT_CONST(1)
+#define EMC_CLKEN_OVERRIDE_0_CMDQ_CLKEN_OVR_FIELD                       (_MK_MASK_CONST(0x1) << EMC_CLKEN_OVERRIDE_0_CMDQ_CLKEN_OVR_SHIFT)
+#define EMC_CLKEN_OVERRIDE_0_CMDQ_CLKEN_OVR_RANGE                       1:1
+#define EMC_CLKEN_OVERRIDE_0_CMDQ_CLKEN_OVR_WOFFSET                     0x0
+#define EMC_CLKEN_OVERRIDE_0_CMDQ_CLKEN_OVR_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_CLKEN_OVERRIDE_0_CMDQ_CLKEN_OVR_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define EMC_CLKEN_OVERRIDE_0_CMDQ_CLKEN_OVR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_CLKEN_OVERRIDE_0_CMDQ_CLKEN_OVR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EMC_CLKEN_OVERRIDE_0_CMDQ_CLKEN_OVR_INIT_ENUM                   CLK_GATED
+#define EMC_CLKEN_OVERRIDE_0_CMDQ_CLKEN_OVR_CLK_GATED                   _MK_ENUM_CONST(0)
+#define EMC_CLKEN_OVERRIDE_0_CMDQ_CLKEN_OVR_CLK_ALWAYS_ON                       _MK_ENUM_CONST(1)
+#define EMC_CLKEN_OVERRIDE_0_CMDQ_CLKEN_OVR_DISABLE                     _MK_ENUM_CONST(0)
+#define EMC_CLKEN_OVERRIDE_0_CMDQ_CLKEN_OVR_ENABLE                      _MK_ENUM_CONST(1)
+#define EMC_CLKEN_OVERRIDE_0_CMDQ_CLKEN_OVR_DISABLED                    _MK_ENUM_CONST(0)
+#define EMC_CLKEN_OVERRIDE_0_CMDQ_CLKEN_OVR_ENABLED                     _MK_ENUM_CONST(1)
+
+#define EMC_CLKEN_OVERRIDE_0_DRAMC_CLKEN_OVR_SHIFT                      _MK_SHIFT_CONST(2)
+#define EMC_CLKEN_OVERRIDE_0_DRAMC_CLKEN_OVR_FIELD                      (_MK_MASK_CONST(0x1) << EMC_CLKEN_OVERRIDE_0_DRAMC_CLKEN_OVR_SHIFT)
+#define EMC_CLKEN_OVERRIDE_0_DRAMC_CLKEN_OVR_RANGE                      2:2
+#define EMC_CLKEN_OVERRIDE_0_DRAMC_CLKEN_OVR_WOFFSET                    0x0
+#define EMC_CLKEN_OVERRIDE_0_DRAMC_CLKEN_OVR_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_CLKEN_OVERRIDE_0_DRAMC_CLKEN_OVR_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define EMC_CLKEN_OVERRIDE_0_DRAMC_CLKEN_OVR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_CLKEN_OVERRIDE_0_DRAMC_CLKEN_OVR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_CLKEN_OVERRIDE_0_DRAMC_CLKEN_OVR_INIT_ENUM                  CLK_GATED
+#define EMC_CLKEN_OVERRIDE_0_DRAMC_CLKEN_OVR_CLK_GATED                  _MK_ENUM_CONST(0)
+#define EMC_CLKEN_OVERRIDE_0_DRAMC_CLKEN_OVR_CLK_ALWAYS_ON                      _MK_ENUM_CONST(1)
+#define EMC_CLKEN_OVERRIDE_0_DRAMC_CLKEN_OVR_DISABLE                    _MK_ENUM_CONST(0)
+#define EMC_CLKEN_OVERRIDE_0_DRAMC_CLKEN_OVR_ENABLE                     _MK_ENUM_CONST(1)
+#define EMC_CLKEN_OVERRIDE_0_DRAMC_CLKEN_OVR_DISABLED                   _MK_ENUM_CONST(0)
+#define EMC_CLKEN_OVERRIDE_0_DRAMC_CLKEN_OVR_ENABLED                    _MK_ENUM_CONST(1)
+
+#define EMC_CLKEN_OVERRIDE_0_RR_CLKEN_OVR_SHIFT                 _MK_SHIFT_CONST(3)
+#define EMC_CLKEN_OVERRIDE_0_RR_CLKEN_OVR_FIELD                 (_MK_MASK_CONST(0x1) << EMC_CLKEN_OVERRIDE_0_RR_CLKEN_OVR_SHIFT)
+#define EMC_CLKEN_OVERRIDE_0_RR_CLKEN_OVR_RANGE                 3:3
+#define EMC_CLKEN_OVERRIDE_0_RR_CLKEN_OVR_WOFFSET                       0x0
+#define EMC_CLKEN_OVERRIDE_0_RR_CLKEN_OVR_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_CLKEN_OVERRIDE_0_RR_CLKEN_OVR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define EMC_CLKEN_OVERRIDE_0_RR_CLKEN_OVR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_CLKEN_OVERRIDE_0_RR_CLKEN_OVR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_CLKEN_OVERRIDE_0_RR_CLKEN_OVR_INIT_ENUM                     CLK_GATED
+#define EMC_CLKEN_OVERRIDE_0_RR_CLKEN_OVR_CLK_GATED                     _MK_ENUM_CONST(0)
+#define EMC_CLKEN_OVERRIDE_0_RR_CLKEN_OVR_CLK_ALWAYS_ON                 _MK_ENUM_CONST(1)
+#define EMC_CLKEN_OVERRIDE_0_RR_CLKEN_OVR_DISABLE                       _MK_ENUM_CONST(0)
+#define EMC_CLKEN_OVERRIDE_0_RR_CLKEN_OVR_ENABLE                        _MK_ENUM_CONST(1)
+#define EMC_CLKEN_OVERRIDE_0_RR_CLKEN_OVR_DISABLED                      _MK_ENUM_CONST(0)
+#define EMC_CLKEN_OVERRIDE_0_RR_CLKEN_OVR_ENABLED                       _MK_ENUM_CONST(1)
+
+#define EMC_CLKEN_OVERRIDE_0_LL_CLKEN_OVR_SHIFT                 _MK_SHIFT_CONST(4)
+#define EMC_CLKEN_OVERRIDE_0_LL_CLKEN_OVR_FIELD                 (_MK_MASK_CONST(0x1) << EMC_CLKEN_OVERRIDE_0_LL_CLKEN_OVR_SHIFT)
+#define EMC_CLKEN_OVERRIDE_0_LL_CLKEN_OVR_RANGE                 4:4
+#define EMC_CLKEN_OVERRIDE_0_LL_CLKEN_OVR_WOFFSET                       0x0
+#define EMC_CLKEN_OVERRIDE_0_LL_CLKEN_OVR_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_CLKEN_OVERRIDE_0_LL_CLKEN_OVR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define EMC_CLKEN_OVERRIDE_0_LL_CLKEN_OVR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_CLKEN_OVERRIDE_0_LL_CLKEN_OVR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_CLKEN_OVERRIDE_0_LL_CLKEN_OVR_INIT_ENUM                     CLK_GATED
+#define EMC_CLKEN_OVERRIDE_0_LL_CLKEN_OVR_CLK_GATED                     _MK_ENUM_CONST(0)
+#define EMC_CLKEN_OVERRIDE_0_LL_CLKEN_OVR_CLK_ALWAYS_ON                 _MK_ENUM_CONST(1)
+#define EMC_CLKEN_OVERRIDE_0_LL_CLKEN_OVR_DISABLE                       _MK_ENUM_CONST(0)
+#define EMC_CLKEN_OVERRIDE_0_LL_CLKEN_OVR_ENABLE                        _MK_ENUM_CONST(1)
+#define EMC_CLKEN_OVERRIDE_0_LL_CLKEN_OVR_DISABLED                      _MK_ENUM_CONST(0)
+#define EMC_CLKEN_OVERRIDE_0_LL_CLKEN_OVR_ENABLED                       _MK_ENUM_CONST(1)
+
+#define EMC_CLKEN_OVERRIDE_0_STATS_CLKEN_OVR_SHIFT                      _MK_SHIFT_CONST(5)
+#define EMC_CLKEN_OVERRIDE_0_STATS_CLKEN_OVR_FIELD                      (_MK_MASK_CONST(0x1) << EMC_CLKEN_OVERRIDE_0_STATS_CLKEN_OVR_SHIFT)
+#define EMC_CLKEN_OVERRIDE_0_STATS_CLKEN_OVR_RANGE                      5:5
+#define EMC_CLKEN_OVERRIDE_0_STATS_CLKEN_OVR_WOFFSET                    0x0
+#define EMC_CLKEN_OVERRIDE_0_STATS_CLKEN_OVR_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_CLKEN_OVERRIDE_0_STATS_CLKEN_OVR_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define EMC_CLKEN_OVERRIDE_0_STATS_CLKEN_OVR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_CLKEN_OVERRIDE_0_STATS_CLKEN_OVR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_CLKEN_OVERRIDE_0_STATS_CLKEN_OVR_INIT_ENUM                  CLK_GATED
+#define EMC_CLKEN_OVERRIDE_0_STATS_CLKEN_OVR_CLK_GATED                  _MK_ENUM_CONST(0)
+#define EMC_CLKEN_OVERRIDE_0_STATS_CLKEN_OVR_CLK_ALWAYS_ON                      _MK_ENUM_CONST(1)
+#define EMC_CLKEN_OVERRIDE_0_STATS_CLKEN_OVR_DISABLE                    _MK_ENUM_CONST(0)
+#define EMC_CLKEN_OVERRIDE_0_STATS_CLKEN_OVR_ENABLE                     _MK_ENUM_CONST(1)
+#define EMC_CLKEN_OVERRIDE_0_STATS_CLKEN_OVR_DISABLED                   _MK_ENUM_CONST(0)
+#define EMC_CLKEN_OVERRIDE_0_STATS_CLKEN_OVR_ENABLED                    _MK_ENUM_CONST(1)
+
+#define NV_MC_EMEM_DFIFO_DEPTH  3
+#define NV_MC_IMEM_DFIFO_DEPTH  5
+#define NV_MC_EMEM_APFIFO_DEPTH 4
+#define NV_MC_ARB_EMEM_REGLEVEL 3
+#define NV_MC_EMEM_REQ_ID_WIDEREQ       9
+#define NV_MC_EMEM_RDI_ID_WIDERDI       9
+#define NV_MC_EMEM_REQ_ID_ILLEGALACC    8
+#define NV_MC_EMEM_RDI_ID_ILLEGALACC    8
+#define NV_MC_EMEM_REQ_ID_LLRAWDECR     7
+#define NV_MC_EMEM_RDI_ID_LLRAWDECR     7
+#define NV_MC_EMEM_REQ_ID_APCIGNORE     6
+#define NV_MC_EMEM_RDI_ID_APCIGNORE     6
+
+// Packet MC2EMC
+#define MC2EMC_SIZE 190
+
+#define MC2EMC_WDO_SHIFT                        _MK_SHIFT_CONST(0)
+#define MC2EMC_WDO_FIELD                        (_MK_MASK_CONST(0xffffffff) << MC2EMC_WDO_SHIFT)
+#define MC2EMC_WDO_RANGE                        _MK_SHIFT_CONST(127):_MK_SHIFT_CONST(0)
+#define MC2EMC_WDO_ROW                  0
+
+#define MC2EMC_WDO_0_SHIFT                      _MK_SHIFT_CONST(0)
+#define MC2EMC_WDO_0_FIELD                      (_MK_MASK_CONST(0xffffffff) << MC2EMC_WDO_0_SHIFT)
+#define MC2EMC_WDO_0_RANGE                      _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define MC2EMC_WDO_0_ROW                        0
+
+#define MC2EMC_WDO_1_SHIFT                      _MK_SHIFT_CONST(32)
+#define MC2EMC_WDO_1_FIELD                      (_MK_MASK_CONST(0xffffffff) << MC2EMC_WDO_1_SHIFT)
+#define MC2EMC_WDO_1_RANGE                      _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(32)
+#define MC2EMC_WDO_1_ROW                        0
+
+#define MC2EMC_WDO_2_SHIFT                      _MK_SHIFT_CONST(64)
+#define MC2EMC_WDO_2_FIELD                      (_MK_MASK_CONST(0xffffffff) << MC2EMC_WDO_2_SHIFT)
+#define MC2EMC_WDO_2_RANGE                      _MK_SHIFT_CONST(95):_MK_SHIFT_CONST(64)
+#define MC2EMC_WDO_2_ROW                        0
+
+#define MC2EMC_WDO_3_SHIFT                      _MK_SHIFT_CONST(96)
+#define MC2EMC_WDO_3_FIELD                      (_MK_MASK_CONST(0xffffffff) << MC2EMC_WDO_3_SHIFT)
+#define MC2EMC_WDO_3_RANGE                      _MK_SHIFT_CONST(127):_MK_SHIFT_CONST(96)
+#define MC2EMC_WDO_3_ROW                        0
+
+#define MC2EMC_BE_SHIFT                 _MK_SHIFT_CONST(128)
+#define MC2EMC_BE_FIELD                 (_MK_MASK_CONST(0xffff) << MC2EMC_BE_SHIFT)
+#define MC2EMC_BE_RANGE                 _MK_SHIFT_CONST(143):_MK_SHIFT_CONST(128)
+#define MC2EMC_BE_ROW                   0
+
+#define MC2EMC_DEV_SHIFT                        _MK_SHIFT_CONST(144)
+#define MC2EMC_DEV_FIELD                        (_MK_MASK_CONST(0x3) << MC2EMC_DEV_SHIFT)
+#define MC2EMC_DEV_RANGE                        _MK_SHIFT_CONST(145):_MK_SHIFT_CONST(144)
+#define MC2EMC_DEV_ROW                  0
+
+#define MC2EMC_BANK_SHIFT                       _MK_SHIFT_CONST(146)
+#define MC2EMC_BANK_FIELD                       (_MK_MASK_CONST(0x3) << MC2EMC_BANK_SHIFT)
+#define MC2EMC_BANK_RANGE                       _MK_SHIFT_CONST(147):_MK_SHIFT_CONST(146)
+#define MC2EMC_BANK_ROW                 0
+
+#define MC2EMC_ROW_SHIFT                        _MK_SHIFT_CONST(148)
+#define MC2EMC_ROW_FIELD                        (_MK_MASK_CONST(0x3fff) << MC2EMC_ROW_SHIFT)
+#define MC2EMC_ROW_RANGE                        _MK_SHIFT_CONST(161):_MK_SHIFT_CONST(148)
+#define MC2EMC_ROW_ROW                  0
+
+#define MC2EMC_COL_SHIFT                        _MK_SHIFT_CONST(162)
+#define MC2EMC_COL_FIELD                        (_MK_MASK_CONST(0x7ff) << MC2EMC_COL_SHIFT)
+#define MC2EMC_COL_RANGE                        _MK_SHIFT_CONST(172):_MK_SHIFT_CONST(162)
+#define MC2EMC_COL_ROW                  0
+
+#define MC2EMC_REQ_ID_SHIFT                     _MK_SHIFT_CONST(173)
+#define MC2EMC_REQ_ID_FIELD                     (_MK_MASK_CONST(0x3ff) << MC2EMC_REQ_ID_SHIFT)
+#define MC2EMC_REQ_ID_RANGE                     _MK_SHIFT_CONST(182):_MK_SHIFT_CONST(173)
+#define MC2EMC_REQ_ID_ROW                       0
+
+#define MC2EMC_AP_SHIFT                 _MK_SHIFT_CONST(183)
+#define MC2EMC_AP_FIELD                 (_MK_MASK_CONST(0x1) << MC2EMC_AP_SHIFT)
+#define MC2EMC_AP_RANGE                 _MK_SHIFT_CONST(183):_MK_SHIFT_CONST(183)
+#define MC2EMC_AP_ROW                   0
+
+#define MC2EMC_WE_SHIFT                 _MK_SHIFT_CONST(184)
+#define MC2EMC_WE_FIELD                 (_MK_MASK_CONST(0x1) << MC2EMC_WE_SHIFT)
+#define MC2EMC_WE_RANGE                 _MK_SHIFT_CONST(184):_MK_SHIFT_CONST(184)
+#define MC2EMC_WE_ROW                   0
+
+#define MC2EMC_TAG_SHIFT                        _MK_SHIFT_CONST(185)
+#define MC2EMC_TAG_FIELD                        (_MK_MASK_CONST(0x1f) << MC2EMC_TAG_SHIFT)
+#define MC2EMC_TAG_RANGE                        _MK_SHIFT_CONST(189):_MK_SHIFT_CONST(185)
+#define MC2EMC_TAG_ROW                  0
+
+
+// Packet MC2EMC_APC
+#define MC2EMC_APC_SIZE 3
+
+#define MC2EMC_APC_CLR_SHIFT                    _MK_SHIFT_CONST(0)
+#define MC2EMC_APC_CLR_FIELD                    (_MK_MASK_CONST(0x1) << MC2EMC_APC_CLR_SHIFT)
+#define MC2EMC_APC_CLR_RANGE                    _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define MC2EMC_APC_CLR_ROW                      0
+
+#define MC2EMC_APC_BANK_SHIFT                   _MK_SHIFT_CONST(1)
+#define MC2EMC_APC_BANK_FIELD                   (_MK_MASK_CONST(0x3) << MC2EMC_APC_BANK_SHIFT)
+#define MC2EMC_APC_BANK_RANGE                   _MK_SHIFT_CONST(2):_MK_SHIFT_CONST(1)
+#define MC2EMC_APC_BANK_ROW                     0
+
+
+// Packet EMC2MC
+#define EMC2MC_SIZE 138
+
+#define EMC2MC_RDI_SHIFT                        _MK_SHIFT_CONST(0)
+#define EMC2MC_RDI_FIELD                        (_MK_MASK_CONST(0xffffffff) << EMC2MC_RDI_SHIFT)
+#define EMC2MC_RDI_RANGE                        _MK_SHIFT_CONST(127):_MK_SHIFT_CONST(0)
+#define EMC2MC_RDI_ROW                  0
+
+#define EMC2MC_RDI_0_SHIFT                      _MK_SHIFT_CONST(0)
+#define EMC2MC_RDI_0_FIELD                      (_MK_MASK_CONST(0xffffffff) << EMC2MC_RDI_0_SHIFT)
+#define EMC2MC_RDI_0_RANGE                      _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define EMC2MC_RDI_0_ROW                        0
+
+#define EMC2MC_RDI_1_SHIFT                      _MK_SHIFT_CONST(32)
+#define EMC2MC_RDI_1_FIELD                      (_MK_MASK_CONST(0xffffffff) << EMC2MC_RDI_1_SHIFT)
+#define EMC2MC_RDI_1_RANGE                      _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(32)
+#define EMC2MC_RDI_1_ROW                        0
+
+#define EMC2MC_RDI_2_SHIFT                      _MK_SHIFT_CONST(64)
+#define EMC2MC_RDI_2_FIELD                      (_MK_MASK_CONST(0xffffffff) << EMC2MC_RDI_2_SHIFT)
+#define EMC2MC_RDI_2_RANGE                      _MK_SHIFT_CONST(95):_MK_SHIFT_CONST(64)
+#define EMC2MC_RDI_2_ROW                        0
+
+#define EMC2MC_RDI_3_SHIFT                      _MK_SHIFT_CONST(96)
+#define EMC2MC_RDI_3_FIELD                      (_MK_MASK_CONST(0xffffffff) << EMC2MC_RDI_3_SHIFT)
+#define EMC2MC_RDI_3_RANGE                      _MK_SHIFT_CONST(127):_MK_SHIFT_CONST(96)
+#define EMC2MC_RDI_3_ROW                        0
+
+#define EMC2MC_RDI_ID_SHIFT                     _MK_SHIFT_CONST(128)
+#define EMC2MC_RDI_ID_FIELD                     (_MK_MASK_CONST(0x3ff) << EMC2MC_RDI_ID_SHIFT)
+#define EMC2MC_RDI_ID_RANGE                     _MK_SHIFT_CONST(137):_MK_SHIFT_CONST(128)
+#define EMC2MC_RDI_ID_ROW                       0
+
+
+// Packet MC2EMC_LL
+#define MC2EMC_LL_SIZE 35
+
+#define MC2EMC_LL_DEV_SHIFT                     _MK_SHIFT_CONST(0)
+#define MC2EMC_LL_DEV_FIELD                     (_MK_MASK_CONST(0x3) << MC2EMC_LL_DEV_SHIFT)
+#define MC2EMC_LL_DEV_RANGE                     _MK_SHIFT_CONST(1):_MK_SHIFT_CONST(0)
+#define MC2EMC_LL_DEV_ROW                       0
+
+#define MC2EMC_LL_BANK_SHIFT                    _MK_SHIFT_CONST(2)
+#define MC2EMC_LL_BANK_FIELD                    (_MK_MASK_CONST(0x3) << MC2EMC_LL_BANK_SHIFT)
+#define MC2EMC_LL_BANK_RANGE                    _MK_SHIFT_CONST(3):_MK_SHIFT_CONST(2)
+#define MC2EMC_LL_BANK_ROW                      0
+
+#define MC2EMC_LL_ROW_SHIFT                     _MK_SHIFT_CONST(4)
+#define MC2EMC_LL_ROW_FIELD                     (_MK_MASK_CONST(0x3fff) << MC2EMC_LL_ROW_SHIFT)
+#define MC2EMC_LL_ROW_RANGE                     _MK_SHIFT_CONST(17):_MK_SHIFT_CONST(4)
+#define MC2EMC_LL_ROW_ROW                       0
+
+#define MC2EMC_LL_COL_SHIFT                     _MK_SHIFT_CONST(18)
+#define MC2EMC_LL_COL_FIELD                     (_MK_MASK_CONST(0x7ff) << MC2EMC_LL_COL_SHIFT)
+#define MC2EMC_LL_COL_RANGE                     _MK_SHIFT_CONST(28):_MK_SHIFT_CONST(18)
+#define MC2EMC_LL_COL_ROW                       0
+
+#define MC2EMC_LL_TAG_SHIFT                     _MK_SHIFT_CONST(29)
+#define MC2EMC_LL_TAG_FIELD                     (_MK_MASK_CONST(0x1f) << MC2EMC_LL_TAG_SHIFT)
+#define MC2EMC_LL_TAG_RANGE                     _MK_SHIFT_CONST(33):_MK_SHIFT_CONST(29)
+#define MC2EMC_LL_TAG_ROW                       0
+
+#define MC2EMC_LL_DOUBLEREQ_SHIFT                       _MK_SHIFT_CONST(34)
+#define MC2EMC_LL_DOUBLEREQ_FIELD                       (_MK_MASK_CONST(0x1) << MC2EMC_LL_DOUBLEREQ_SHIFT)
+#define MC2EMC_LL_DOUBLEREQ_RANGE                       _MK_SHIFT_CONST(34):_MK_SHIFT_CONST(34)
+#define MC2EMC_LL_DOUBLEREQ_ROW                 0
+
+
+// Packet EMC2MC_LL
+#define EMC2MC_LL_SIZE 64
+
+#define EMC2MC_LL_RDI_SHIFT                     _MK_SHIFT_CONST(0)
+#define EMC2MC_LL_RDI_FIELD                     (_MK_MASK_CONST(0xffffffff) << EMC2MC_LL_RDI_SHIFT)
+#define EMC2MC_LL_RDI_RANGE                     _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(0)
+#define EMC2MC_LL_RDI_ROW                       0
+
+
+// Packet MC2EMC_LL_CRITINFO
+#define MC2EMC_LL_CRITINFO_SIZE 11
+
+#define MC2EMC_LL_CRITINFO_HP_SHIFT                     _MK_SHIFT_CONST(0)
+#define MC2EMC_LL_CRITINFO_HP_FIELD                     (_MK_MASK_CONST(0x1f) << MC2EMC_LL_CRITINFO_HP_SHIFT)
+#define MC2EMC_LL_CRITINFO_HP_RANGE                     _MK_SHIFT_CONST(4):_MK_SHIFT_CONST(0)
+#define MC2EMC_LL_CRITINFO_HP_ROW                       0
+
+#define MC2EMC_LL_CRITINFO_TIMEOUT_SHIFT                        _MK_SHIFT_CONST(5)
+#define MC2EMC_LL_CRITINFO_TIMEOUT_FIELD                        (_MK_MASK_CONST(0x3f) << MC2EMC_LL_CRITINFO_TIMEOUT_SHIFT)
+#define MC2EMC_LL_CRITINFO_TIMEOUT_RANGE                        _MK_SHIFT_CONST(10):_MK_SHIFT_CONST(5)
+#define MC2EMC_LL_CRITINFO_TIMEOUT_ROW                  0
+
+
+// Packet MC2EMC_LL_ARBINFO
+#define MC2EMC_LL_ARBINFO_SIZE 2
+
+#define MC2EMC_LL_ARBINFO_BANK_SHIFT                    _MK_SHIFT_CONST(0)
+#define MC2EMC_LL_ARBINFO_BANK_FIELD                    (_MK_MASK_CONST(0x3) << MC2EMC_LL_ARBINFO_BANK_SHIFT)
+#define MC2EMC_LL_ARBINFO_BANK_RANGE                    _MK_SHIFT_CONST(1):_MK_SHIFT_CONST(0)
+#define MC2EMC_LL_ARBINFO_BANK_ROW                      0
+
+
+// Packet CMC2MC_AXI_A
+#define CMC2MC_AXI_A_SIZE 58
+
+#define CMC2MC_AXI_A_AADDR_SHIFT                        _MK_SHIFT_CONST(0)
+#define CMC2MC_AXI_A_AADDR_FIELD                        (_MK_MASK_CONST(0xffffffff) << CMC2MC_AXI_A_AADDR_SHIFT)
+#define CMC2MC_AXI_A_AADDR_RANGE                        _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CMC2MC_AXI_A_AADDR_ROW                  0
+
+#define CMC2MC_AXI_A_AID_SHIFT                  _MK_SHIFT_CONST(32)
+#define CMC2MC_AXI_A_AID_FIELD                  (_MK_MASK_CONST(0xff) << CMC2MC_AXI_A_AID_SHIFT)
+#define CMC2MC_AXI_A_AID_RANGE                  _MK_SHIFT_CONST(39):_MK_SHIFT_CONST(32)
+#define CMC2MC_AXI_A_AID_ROW                    0
+
+#define CMC2MC_AXI_A_ALEN_SHIFT                 _MK_SHIFT_CONST(40)
+#define CMC2MC_AXI_A_ALEN_FIELD                 (_MK_MASK_CONST(0xf) << CMC2MC_AXI_A_ALEN_SHIFT)
+#define CMC2MC_AXI_A_ALEN_RANGE                 _MK_SHIFT_CONST(43):_MK_SHIFT_CONST(40)
+#define CMC2MC_AXI_A_ALEN_ROW                   0
+#define CMC2MC_AXI_A_ALEN_ONEDATA                       _MK_ENUM_CONST(0)
+#define CMC2MC_AXI_A_ALEN_TWODATA                       _MK_ENUM_CONST(1)
+#define CMC2MC_AXI_A_ALEN_THREEDATA                     _MK_ENUM_CONST(2)
+#define CMC2MC_AXI_A_ALEN_FOURDATA                      _MK_ENUM_CONST(3)
+#define CMC2MC_AXI_A_ALEN_FIVEDATA                      _MK_ENUM_CONST(4)
+#define CMC2MC_AXI_A_ALEN_SIXDATA                       _MK_ENUM_CONST(5)
+#define CMC2MC_AXI_A_ALEN_SEVENDATA                     _MK_ENUM_CONST(6)
+#define CMC2MC_AXI_A_ALEN_EIGHTDATA                     _MK_ENUM_CONST(7)
+#define CMC2MC_AXI_A_ALEN_NINEDATA                      _MK_ENUM_CONST(8)
+#define CMC2MC_AXI_A_ALEN_TENDATA                       _MK_ENUM_CONST(9)
+#define CMC2MC_AXI_A_ALEN_ELEVENDATA                    _MK_ENUM_CONST(10)
+#define CMC2MC_AXI_A_ALEN_TWELVEDATA                    _MK_ENUM_CONST(11)
+#define CMC2MC_AXI_A_ALEN_THIRTEENDATA                  _MK_ENUM_CONST(12)
+#define CMC2MC_AXI_A_ALEN_FOURTEENDATA                  _MK_ENUM_CONST(13)
+#define CMC2MC_AXI_A_ALEN_FIFTHTEENDATA                 _MK_ENUM_CONST(14)
+#define CMC2MC_AXI_A_ALEN_SIXTEENDATA                   _MK_ENUM_CONST(15)
+
+#define CMC2MC_AXI_A_ASIZE_SHIFT                        _MK_SHIFT_CONST(44)
+#define CMC2MC_AXI_A_ASIZE_FIELD                        (_MK_MASK_CONST(0x7) << CMC2MC_AXI_A_ASIZE_SHIFT)
+#define CMC2MC_AXI_A_ASIZE_RANGE                        _MK_SHIFT_CONST(46):_MK_SHIFT_CONST(44)
+#define CMC2MC_AXI_A_ASIZE_ROW                  0
+#define CMC2MC_AXI_A_ASIZE_ONEBYTE                      _MK_ENUM_CONST(0)
+#define CMC2MC_AXI_A_ASIZE_TWOBYTES                     _MK_ENUM_CONST(1)
+#define CMC2MC_AXI_A_ASIZE_FOURBYTES                    _MK_ENUM_CONST(2)
+#define CMC2MC_AXI_A_ASIZE_EIGHTBYTES                   _MK_ENUM_CONST(3)
+#define CMC2MC_AXI_A_ASIZE_SIXTEENBYTES                 _MK_ENUM_CONST(4)
+#define CMC2MC_AXI_A_ASIZE_THIRTYTWOBYTES                       _MK_ENUM_CONST(5)
+#define CMC2MC_AXI_A_ASIZE_SIXTYFOURBYTES                       _MK_ENUM_CONST(6)
+#define CMC2MC_AXI_A_ASIZE_ONEHUNDREDTWENTYEIGHTBYTES                   _MK_ENUM_CONST(7)
+
+#define CMC2MC_AXI_A_ABURST_SHIFT                       _MK_SHIFT_CONST(47)
+#define CMC2MC_AXI_A_ABURST_FIELD                       (_MK_MASK_CONST(0x3) << CMC2MC_AXI_A_ABURST_SHIFT)
+#define CMC2MC_AXI_A_ABURST_RANGE                       _MK_SHIFT_CONST(48):_MK_SHIFT_CONST(47)
+#define CMC2MC_AXI_A_ABURST_ROW                 0
+#define CMC2MC_AXI_A_ABURST_FIXED                       _MK_ENUM_CONST(0)
+#define CMC2MC_AXI_A_ABURST_INCR                        _MK_ENUM_CONST(1)
+#define CMC2MC_AXI_A_ABURST_WRAP                        _MK_ENUM_CONST(2)
+#define CMC2MC_AXI_A_ABURST_RSVD                        _MK_ENUM_CONST(3)
+
+#define CMC2MC_AXI_A_ALOCK_SHIFT                        _MK_SHIFT_CONST(49)
+#define CMC2MC_AXI_A_ALOCK_FIELD                        (_MK_MASK_CONST(0x3) << CMC2MC_AXI_A_ALOCK_SHIFT)
+#define CMC2MC_AXI_A_ALOCK_RANGE                        _MK_SHIFT_CONST(50):_MK_SHIFT_CONST(49)
+#define CMC2MC_AXI_A_ALOCK_ROW                  0
+#define CMC2MC_AXI_A_ALOCK_NORMAL                       _MK_ENUM_CONST(0)
+#define CMC2MC_AXI_A_ALOCK_EXCLUSIVE                    _MK_ENUM_CONST(1)
+#define CMC2MC_AXI_A_ALOCK_LOCKED                       _MK_ENUM_CONST(2)
+#define CMC2MC_AXI_A_ALOCK_RSVD                 _MK_ENUM_CONST(3)
+
+#define CMC2MC_AXI_A_ACACHE_SHIFT                       _MK_SHIFT_CONST(51)
+#define CMC2MC_AXI_A_ACACHE_FIELD                       (_MK_MASK_CONST(0xf) << CMC2MC_AXI_A_ACACHE_SHIFT)
+#define CMC2MC_AXI_A_ACACHE_RANGE                       _MK_SHIFT_CONST(54):_MK_SHIFT_CONST(51)
+#define CMC2MC_AXI_A_ACACHE_ROW                 0
+#define CMC2MC_AXI_A_ACACHE_NONCACHEABLE_NONBUFFERABLE                  _MK_ENUM_CONST(0)
+#define CMC2MC_AXI_A_ACACHE_BUFFERABLE                  _MK_ENUM_CONST(1)
+#define CMC2MC_AXI_A_ACACHE_CACHEABLE_DONOTALLOCATE                     _MK_ENUM_CONST(2)
+#define CMC2MC_AXI_A_ACACHE_CACHEABLE_BUFFERABLE_DONOTALLOCATE                  _MK_ENUM_CONST(3)
+#define CMC2MC_AXI_A_ACACHE_CACHEABLEWRITETHROUGH_ALLOCATEONREAD                        _MK_ENUM_CONST(6)
+#define CMC2MC_AXI_A_ACACHE_CACHEABLEWRITEBACK_ALLOCATEONREAD                   _MK_ENUM_CONST(7)
+#define CMC2MC_AXI_A_ACACHE_CACHEABLEWRITETHROUGH_ALLOCATEONWRITE                       _MK_ENUM_CONST(10)
+#define CMC2MC_AXI_A_ACACHE_CACHEABLEWRITEBACK_ALLOCATEONWRITE                  _MK_ENUM_CONST(11)
+#define CMC2MC_AXI_A_ACACHE_CACHEABLEWRITETHROUGH_ALLOCATEONREADWRITE                   _MK_ENUM_CONST(14)
+#define CMC2MC_AXI_A_ACACHE_CACHEABLEWRITEBACK_ALLOCATEONREADWRITE                      _MK_ENUM_CONST(15)
+
+#define CMC2MC_AXI_A_APROT_SHIFT                        _MK_SHIFT_CONST(55)
+#define CMC2MC_AXI_A_APROT_FIELD                        (_MK_MASK_CONST(0x7) << CMC2MC_AXI_A_APROT_SHIFT)
+#define CMC2MC_AXI_A_APROT_RANGE                        _MK_SHIFT_CONST(57):_MK_SHIFT_CONST(55)
+#define CMC2MC_AXI_A_APROT_ROW                  0
+#define CMC2MC_AXI_A_APROT_DATA_SECURE_NORMAL                   _MK_ENUM_CONST(0)
+#define CMC2MC_AXI_A_APROT_DATA_SECURE_PRIVILEGED                       _MK_ENUM_CONST(1)
+#define CMC2MC_AXI_A_APROT_DATA_NONSECURE_NORMAL                        _MK_ENUM_CONST(2)
+#define CMC2MC_AXI_A_APROT_DATA_NONSECURE_PRIVILEGED                    _MK_ENUM_CONST(3)
+#define CMC2MC_AXI_A_APROT_INST_SECURE_NORMAL                   _MK_ENUM_CONST(4)
+#define CMC2MC_AXI_A_APROT_INST_SECURE_PRIVILEGED                       _MK_ENUM_CONST(5)
+#define CMC2MC_AXI_A_APROT_INST_NONSECURE_NORMAL                        _MK_ENUM_CONST(6)
+#define CMC2MC_AXI_A_APROT_INST_NONSECURE_PRIVILEGED                    _MK_ENUM_CONST(7)
+
+
+// Packet CMC2MC_AXI_W
+#define CMC2MC_AXI_W_SIZE 81
+
+#define CMC2MC_AXI_W_WDATA_SHIFT                        _MK_SHIFT_CONST(0)
+#define CMC2MC_AXI_W_WDATA_FIELD                        (_MK_MASK_CONST(0xffffffff) << CMC2MC_AXI_W_WDATA_SHIFT)
+#define CMC2MC_AXI_W_WDATA_RANGE                        _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(0)
+#define CMC2MC_AXI_W_WDATA_ROW                  0
+
+#define CMC2MC_AXI_W_WID_SHIFT                  _MK_SHIFT_CONST(64)
+#define CMC2MC_AXI_W_WID_FIELD                  (_MK_MASK_CONST(0xff) << CMC2MC_AXI_W_WID_SHIFT)
+#define CMC2MC_AXI_W_WID_RANGE                  _MK_SHIFT_CONST(71):_MK_SHIFT_CONST(64)
+#define CMC2MC_AXI_W_WID_ROW                    0
+
+#define CMC2MC_AXI_W_WSTRB_SHIFT                        _MK_SHIFT_CONST(72)
+#define CMC2MC_AXI_W_WSTRB_FIELD                        (_MK_MASK_CONST(0xff) << CMC2MC_AXI_W_WSTRB_SHIFT)
+#define CMC2MC_AXI_W_WSTRB_RANGE                        _MK_SHIFT_CONST(79):_MK_SHIFT_CONST(72)
+#define CMC2MC_AXI_W_WSTRB_ROW                  0
+
+#define CMC2MC_AXI_W_WLAST_SHIFT                        _MK_SHIFT_CONST(80)
+#define CMC2MC_AXI_W_WLAST_FIELD                        (_MK_MASK_CONST(0x1) << CMC2MC_AXI_W_WLAST_SHIFT)
+#define CMC2MC_AXI_W_WLAST_RANGE                        _MK_SHIFT_CONST(80):_MK_SHIFT_CONST(80)
+#define CMC2MC_AXI_W_WLAST_ROW                  0
+#define CMC2MC_AXI_W_WLAST_DISABLED                     _MK_ENUM_CONST(0)
+#define CMC2MC_AXI_W_WLAST_ENABLED                      _MK_ENUM_CONST(1)
+
+
+// Packet CMC2MC_AXI_B
+#define CMC2MC_AXI_B_SIZE 10
+
+#define CMC2MC_AXI_B_BID_SHIFT                  _MK_SHIFT_CONST(0)
+#define CMC2MC_AXI_B_BID_FIELD                  (_MK_MASK_CONST(0xff) << CMC2MC_AXI_B_BID_SHIFT)
+#define CMC2MC_AXI_B_BID_RANGE                  _MK_SHIFT_CONST(7):_MK_SHIFT_CONST(0)
+#define CMC2MC_AXI_B_BID_ROW                    0
+
+#define CMC2MC_AXI_B_BRESP_SHIFT                        _MK_SHIFT_CONST(8)
+#define CMC2MC_AXI_B_BRESP_FIELD                        (_MK_MASK_CONST(0x3) << CMC2MC_AXI_B_BRESP_SHIFT)
+#define CMC2MC_AXI_B_BRESP_RANGE                        _MK_SHIFT_CONST(9):_MK_SHIFT_CONST(8)
+#define CMC2MC_AXI_B_BRESP_ROW                  0
+#define CMC2MC_AXI_B_BRESP_OKAY                 _MK_ENUM_CONST(0)
+#define CMC2MC_AXI_B_BRESP_EXOKAY                       _MK_ENUM_CONST(1)
+#define CMC2MC_AXI_B_BRESP_SLVERR                       _MK_ENUM_CONST(2)
+#define CMC2MC_AXI_B_BRESP_DECERR                       _MK_ENUM_CONST(3)
+
+
+// Packet CMC2MC_AXI_R
+#define CMC2MC_AXI_R_SIZE 75
+
+#define CMC2MC_AXI_R_RDATA_SHIFT                        _MK_SHIFT_CONST(0)
+#define CMC2MC_AXI_R_RDATA_FIELD                        (_MK_MASK_CONST(0xffffffff) << CMC2MC_AXI_R_RDATA_SHIFT)
+#define CMC2MC_AXI_R_RDATA_RANGE                        _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(0)
+#define CMC2MC_AXI_R_RDATA_ROW                  0
+
+#define CMC2MC_AXI_R_RID_SHIFT                  _MK_SHIFT_CONST(64)
+#define CMC2MC_AXI_R_RID_FIELD                  (_MK_MASK_CONST(0xff) << CMC2MC_AXI_R_RID_SHIFT)
+#define CMC2MC_AXI_R_RID_RANGE                  _MK_SHIFT_CONST(71):_MK_SHIFT_CONST(64)
+#define CMC2MC_AXI_R_RID_ROW                    0
+
+#define CMC2MC_AXI_R_RRESP_SHIFT                        _MK_SHIFT_CONST(72)
+#define CMC2MC_AXI_R_RRESP_FIELD                        (_MK_MASK_CONST(0x3) << CMC2MC_AXI_R_RRESP_SHIFT)
+#define CMC2MC_AXI_R_RRESP_RANGE                        _MK_SHIFT_CONST(73):_MK_SHIFT_CONST(72)
+#define CMC2MC_AXI_R_RRESP_ROW                  0
+#define CMC2MC_AXI_R_RRESP_OKAY                 _MK_ENUM_CONST(0)
+#define CMC2MC_AXI_R_RRESP_EXOKAY                       _MK_ENUM_CONST(1)
+#define CMC2MC_AXI_R_RRESP_SLVERR                       _MK_ENUM_CONST(2)
+#define CMC2MC_AXI_R_RRESP_DECERR                       _MK_ENUM_CONST(3)
+
+#define CMC2MC_AXI_R_RLAST_SHIFT                        _MK_SHIFT_CONST(74)
+#define CMC2MC_AXI_R_RLAST_FIELD                        (_MK_MASK_CONST(0x1) << CMC2MC_AXI_R_RLAST_SHIFT)
+#define CMC2MC_AXI_R_RLAST_RANGE                        _MK_SHIFT_CONST(74):_MK_SHIFT_CONST(74)
+#define CMC2MC_AXI_R_RLAST_ROW                  0
+#define CMC2MC_AXI_R_RLAST_DISABLED                     _MK_ENUM_CONST(0)
+#define CMC2MC_AXI_R_RLAST_ENABLED                      _MK_ENUM_CONST(1)
+
+
+// Packet MSELECT2MC_AXI_A
+#define MSELECT2MC_AXI_A_SIZE 58
+
+#define MSELECT2MC_AXI_A_AADDR_SHIFT                    _MK_SHIFT_CONST(0)
+#define MSELECT2MC_AXI_A_AADDR_FIELD                    (_MK_MASK_CONST(0xffffffff) << MSELECT2MC_AXI_A_AADDR_SHIFT)
+#define MSELECT2MC_AXI_A_AADDR_RANGE                    _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define MSELECT2MC_AXI_A_AADDR_ROW                      0
+
+#define MSELECT2MC_AXI_A_AID_SHIFT                      _MK_SHIFT_CONST(32)
+#define MSELECT2MC_AXI_A_AID_FIELD                      (_MK_MASK_CONST(0xff) << MSELECT2MC_AXI_A_AID_SHIFT)
+#define MSELECT2MC_AXI_A_AID_RANGE                      _MK_SHIFT_CONST(39):_MK_SHIFT_CONST(32)
+#define MSELECT2MC_AXI_A_AID_ROW                        0
+
+#define MSELECT2MC_AXI_A_ALEN_SHIFT                     _MK_SHIFT_CONST(40)
+#define MSELECT2MC_AXI_A_ALEN_FIELD                     (_MK_MASK_CONST(0xf) << MSELECT2MC_AXI_A_ALEN_SHIFT)
+#define MSELECT2MC_AXI_A_ALEN_RANGE                     _MK_SHIFT_CONST(43):_MK_SHIFT_CONST(40)
+#define MSELECT2MC_AXI_A_ALEN_ROW                       0
+#define MSELECT2MC_AXI_A_ALEN_ONEDATA                   _MK_ENUM_CONST(0)
+#define MSELECT2MC_AXI_A_ALEN_TWODATA                   _MK_ENUM_CONST(1)
+#define MSELECT2MC_AXI_A_ALEN_THREEDATA                 _MK_ENUM_CONST(2)
+#define MSELECT2MC_AXI_A_ALEN_FOURDATA                  _MK_ENUM_CONST(3)
+#define MSELECT2MC_AXI_A_ALEN_FIVEDATA                  _MK_ENUM_CONST(4)
+#define MSELECT2MC_AXI_A_ALEN_SIXDATA                   _MK_ENUM_CONST(5)
+#define MSELECT2MC_AXI_A_ALEN_SEVENDATA                 _MK_ENUM_CONST(6)
+#define MSELECT2MC_AXI_A_ALEN_EIGHTDATA                 _MK_ENUM_CONST(7)
+#define MSELECT2MC_AXI_A_ALEN_NINEDATA                  _MK_ENUM_CONST(8)
+#define MSELECT2MC_AXI_A_ALEN_TENDATA                   _MK_ENUM_CONST(9)
+#define MSELECT2MC_AXI_A_ALEN_ELEVENDATA                        _MK_ENUM_CONST(10)
+#define MSELECT2MC_AXI_A_ALEN_TWELVEDATA                        _MK_ENUM_CONST(11)
+#define MSELECT2MC_AXI_A_ALEN_THIRTEENDATA                      _MK_ENUM_CONST(12)
+#define MSELECT2MC_AXI_A_ALEN_FOURTEENDATA                      _MK_ENUM_CONST(13)
+#define MSELECT2MC_AXI_A_ALEN_FIFTHTEENDATA                     _MK_ENUM_CONST(14)
+#define MSELECT2MC_AXI_A_ALEN_SIXTEENDATA                       _MK_ENUM_CONST(15)
+
+#define MSELECT2MC_AXI_A_ASIZE_SHIFT                    _MK_SHIFT_CONST(44)
+#define MSELECT2MC_AXI_A_ASIZE_FIELD                    (_MK_MASK_CONST(0x7) << MSELECT2MC_AXI_A_ASIZE_SHIFT)
+#define MSELECT2MC_AXI_A_ASIZE_RANGE                    _MK_SHIFT_CONST(46):_MK_SHIFT_CONST(44)
+#define MSELECT2MC_AXI_A_ASIZE_ROW                      0
+#define MSELECT2MC_AXI_A_ASIZE_ONEBYTE                  _MK_ENUM_CONST(0)
+#define MSELECT2MC_AXI_A_ASIZE_TWOBYTES                 _MK_ENUM_CONST(1)
+#define MSELECT2MC_AXI_A_ASIZE_FOURBYTES                        _MK_ENUM_CONST(2)
+#define MSELECT2MC_AXI_A_ASIZE_EIGHTBYTES                       _MK_ENUM_CONST(3)
+#define MSELECT2MC_AXI_A_ASIZE_SIXTEENBYTES                     _MK_ENUM_CONST(4)
+#define MSELECT2MC_AXI_A_ASIZE_THIRTYTWOBYTES                   _MK_ENUM_CONST(5)
+#define MSELECT2MC_AXI_A_ASIZE_SIXTYFOURBYTES                   _MK_ENUM_CONST(6)
+#define MSELECT2MC_AXI_A_ASIZE_ONEHUNDREDTWENTYEIGHTBYTES                       _MK_ENUM_CONST(7)
+
+#define MSELECT2MC_AXI_A_ABURST_SHIFT                   _MK_SHIFT_CONST(47)
+#define MSELECT2MC_AXI_A_ABURST_FIELD                   (_MK_MASK_CONST(0x3) << MSELECT2MC_AXI_A_ABURST_SHIFT)
+#define MSELECT2MC_AXI_A_ABURST_RANGE                   _MK_SHIFT_CONST(48):_MK_SHIFT_CONST(47)
+#define MSELECT2MC_AXI_A_ABURST_ROW                     0
+#define MSELECT2MC_AXI_A_ABURST_FIXED                   _MK_ENUM_CONST(0)
+#define MSELECT2MC_AXI_A_ABURST_INCR                    _MK_ENUM_CONST(1)
+#define MSELECT2MC_AXI_A_ABURST_WRAP                    _MK_ENUM_CONST(2)
+#define MSELECT2MC_AXI_A_ABURST_RSVD                    _MK_ENUM_CONST(3)
+
+#define MSELECT2MC_AXI_A_ALOCK_SHIFT                    _MK_SHIFT_CONST(49)
+#define MSELECT2MC_AXI_A_ALOCK_FIELD                    (_MK_MASK_CONST(0x3) << MSELECT2MC_AXI_A_ALOCK_SHIFT)
+#define MSELECT2MC_AXI_A_ALOCK_RANGE                    _MK_SHIFT_CONST(50):_MK_SHIFT_CONST(49)
+#define MSELECT2MC_AXI_A_ALOCK_ROW                      0
+#define MSELECT2MC_AXI_A_ALOCK_NORMAL                   _MK_ENUM_CONST(0)
+#define MSELECT2MC_AXI_A_ALOCK_EXCLUSIVE                        _MK_ENUM_CONST(1)
+#define MSELECT2MC_AXI_A_ALOCK_LOCKED                   _MK_ENUM_CONST(2)
+#define MSELECT2MC_AXI_A_ALOCK_RSVD                     _MK_ENUM_CONST(3)
+
+#define MSELECT2MC_AXI_A_ACACHE_SHIFT                   _MK_SHIFT_CONST(51)
+#define MSELECT2MC_AXI_A_ACACHE_FIELD                   (_MK_MASK_CONST(0xf) << MSELECT2MC_AXI_A_ACACHE_SHIFT)
+#define MSELECT2MC_AXI_A_ACACHE_RANGE                   _MK_SHIFT_CONST(54):_MK_SHIFT_CONST(51)
+#define MSELECT2MC_AXI_A_ACACHE_ROW                     0
+#define MSELECT2MC_AXI_A_ACACHE_NONCACHEABLE_NONBUFFERABLE                      _MK_ENUM_CONST(0)
+#define MSELECT2MC_AXI_A_ACACHE_BUFFERABLE                      _MK_ENUM_CONST(1)
+#define MSELECT2MC_AXI_A_ACACHE_CACHEABLE_DONOTALLOCATE                 _MK_ENUM_CONST(2)
+#define MSELECT2MC_AXI_A_ACACHE_CACHEABLE_BUFFERABLE_DONOTALLOCATE                      _MK_ENUM_CONST(3)
+#define MSELECT2MC_AXI_A_ACACHE_CACHEABLEWRITETHROUGH_ALLOCATEONREAD                    _MK_ENUM_CONST(6)
+#define MSELECT2MC_AXI_A_ACACHE_CACHEABLEWRITEBACK_ALLOCATEONREAD                       _MK_ENUM_CONST(7)
+#define MSELECT2MC_AXI_A_ACACHE_CACHEABLEWRITETHROUGH_ALLOCATEONWRITE                   _MK_ENUM_CONST(10)
+#define MSELECT2MC_AXI_A_ACACHE_CACHEABLEWRITEBACK_ALLOCATEONWRITE                      _MK_ENUM_CONST(11)
+#define MSELECT2MC_AXI_A_ACACHE_CACHEABLEWRITETHROUGH_ALLOCATEONREADWRITE                       _MK_ENUM_CONST(14)
+#define MSELECT2MC_AXI_A_ACACHE_CACHEABLEWRITEBACK_ALLOCATEONREADWRITE                  _MK_ENUM_CONST(15)
+
+#define MSELECT2MC_AXI_A_APROT_SHIFT                    _MK_SHIFT_CONST(55)
+#define MSELECT2MC_AXI_A_APROT_FIELD                    (_MK_MASK_CONST(0x7) << MSELECT2MC_AXI_A_APROT_SHIFT)
+#define MSELECT2MC_AXI_A_APROT_RANGE                    _MK_SHIFT_CONST(57):_MK_SHIFT_CONST(55)
+#define MSELECT2MC_AXI_A_APROT_ROW                      0
+#define MSELECT2MC_AXI_A_APROT_DATA_SECURE_NORMAL                       _MK_ENUM_CONST(0)
+#define MSELECT2MC_AXI_A_APROT_DATA_SECURE_PRIVILEGED                   _MK_ENUM_CONST(1)
+#define MSELECT2MC_AXI_A_APROT_DATA_NONSECURE_NORMAL                    _MK_ENUM_CONST(2)
+#define MSELECT2MC_AXI_A_APROT_DATA_NONSECURE_PRIVILEGED                        _MK_ENUM_CONST(3)
+#define MSELECT2MC_AXI_A_APROT_INST_SECURE_NORMAL                       _MK_ENUM_CONST(4)
+#define MSELECT2MC_AXI_A_APROT_INST_SECURE_PRIVILEGED                   _MK_ENUM_CONST(5)
+#define MSELECT2MC_AXI_A_APROT_INST_NONSECURE_NORMAL                    _MK_ENUM_CONST(6)
+#define MSELECT2MC_AXI_A_APROT_INST_NONSECURE_PRIVILEGED                        _MK_ENUM_CONST(7)
+
+
+// Packet MSELECT2MC_AXI_W
+#define MSELECT2MC_AXI_W_SIZE 81
+
+#define MSELECT2MC_AXI_W_WDATA_SHIFT                    _MK_SHIFT_CONST(0)
+#define MSELECT2MC_AXI_W_WDATA_FIELD                    (_MK_MASK_CONST(0xffffffff) << MSELECT2MC_AXI_W_WDATA_SHIFT)
+#define MSELECT2MC_AXI_W_WDATA_RANGE                    _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(0)
+#define MSELECT2MC_AXI_W_WDATA_ROW                      0
+
+#define MSELECT2MC_AXI_W_WID_SHIFT                      _MK_SHIFT_CONST(64)
+#define MSELECT2MC_AXI_W_WID_FIELD                      (_MK_MASK_CONST(0xff) << MSELECT2MC_AXI_W_WID_SHIFT)
+#define MSELECT2MC_AXI_W_WID_RANGE                      _MK_SHIFT_CONST(71):_MK_SHIFT_CONST(64)
+#define MSELECT2MC_AXI_W_WID_ROW                        0
+
+#define MSELECT2MC_AXI_W_WSTRB_SHIFT                    _MK_SHIFT_CONST(72)
+#define MSELECT2MC_AXI_W_WSTRB_FIELD                    (_MK_MASK_CONST(0xff) << MSELECT2MC_AXI_W_WSTRB_SHIFT)
+#define MSELECT2MC_AXI_W_WSTRB_RANGE                    _MK_SHIFT_CONST(79):_MK_SHIFT_CONST(72)
+#define MSELECT2MC_AXI_W_WSTRB_ROW                      0
+
+#define MSELECT2MC_AXI_W_WLAST_SHIFT                    _MK_SHIFT_CONST(80)
+#define MSELECT2MC_AXI_W_WLAST_FIELD                    (_MK_MASK_CONST(0x1) << MSELECT2MC_AXI_W_WLAST_SHIFT)
+#define MSELECT2MC_AXI_W_WLAST_RANGE                    _MK_SHIFT_CONST(80):_MK_SHIFT_CONST(80)
+#define MSELECT2MC_AXI_W_WLAST_ROW                      0
+#define MSELECT2MC_AXI_W_WLAST_DISABLED                 _MK_ENUM_CONST(0)
+#define MSELECT2MC_AXI_W_WLAST_ENABLED                  _MK_ENUM_CONST(1)
+
+
+// Packet MSELECT2MC_AXI_B
+#define MSELECT2MC_AXI_B_SIZE 10
+
+#define MSELECT2MC_AXI_B_BID_SHIFT                      _MK_SHIFT_CONST(0)
+#define MSELECT2MC_AXI_B_BID_FIELD                      (_MK_MASK_CONST(0xff) << MSELECT2MC_AXI_B_BID_SHIFT)
+#define MSELECT2MC_AXI_B_BID_RANGE                      _MK_SHIFT_CONST(7):_MK_SHIFT_CONST(0)
+#define MSELECT2MC_AXI_B_BID_ROW                        0
+
+#define MSELECT2MC_AXI_B_BRESP_SHIFT                    _MK_SHIFT_CONST(8)
+#define MSELECT2MC_AXI_B_BRESP_FIELD                    (_MK_MASK_CONST(0x3) << MSELECT2MC_AXI_B_BRESP_SHIFT)
+#define MSELECT2MC_AXI_B_BRESP_RANGE                    _MK_SHIFT_CONST(9):_MK_SHIFT_CONST(8)
+#define MSELECT2MC_AXI_B_BRESP_ROW                      0
+#define MSELECT2MC_AXI_B_BRESP_OKAY                     _MK_ENUM_CONST(0)
+#define MSELECT2MC_AXI_B_BRESP_EXOKAY                   _MK_ENUM_CONST(1)
+#define MSELECT2MC_AXI_B_BRESP_SLVERR                   _MK_ENUM_CONST(2)
+#define MSELECT2MC_AXI_B_BRESP_DECERR                   _MK_ENUM_CONST(3)
+
+
+// Packet MSELECT2MC_AXI_R
+#define MSELECT2MC_AXI_R_SIZE 75
+
+#define MSELECT2MC_AXI_R_RDATA_SHIFT                    _MK_SHIFT_CONST(0)
+#define MSELECT2MC_AXI_R_RDATA_FIELD                    (_MK_MASK_CONST(0xffffffff) << MSELECT2MC_AXI_R_RDATA_SHIFT)
+#define MSELECT2MC_AXI_R_RDATA_RANGE                    _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(0)
+#define MSELECT2MC_AXI_R_RDATA_ROW                      0
+
+#define MSELECT2MC_AXI_R_RID_SHIFT                      _MK_SHIFT_CONST(64)
+#define MSELECT2MC_AXI_R_RID_FIELD                      (_MK_MASK_CONST(0xff) << MSELECT2MC_AXI_R_RID_SHIFT)
+#define MSELECT2MC_AXI_R_RID_RANGE                      _MK_SHIFT_CONST(71):_MK_SHIFT_CONST(64)
+#define MSELECT2MC_AXI_R_RID_ROW                        0
+
+#define MSELECT2MC_AXI_R_RRESP_SHIFT                    _MK_SHIFT_CONST(72)
+#define MSELECT2MC_AXI_R_RRESP_FIELD                    (_MK_MASK_CONST(0x3) << MSELECT2MC_AXI_R_RRESP_SHIFT)
+#define MSELECT2MC_AXI_R_RRESP_RANGE                    _MK_SHIFT_CONST(73):_MK_SHIFT_CONST(72)
+#define MSELECT2MC_AXI_R_RRESP_ROW                      0
+#define MSELECT2MC_AXI_R_RRESP_OKAY                     _MK_ENUM_CONST(0)
+#define MSELECT2MC_AXI_R_RRESP_EXOKAY                   _MK_ENUM_CONST(1)
+#define MSELECT2MC_AXI_R_RRESP_SLVERR                   _MK_ENUM_CONST(2)
+#define MSELECT2MC_AXI_R_RRESP_DECERR                   _MK_ENUM_CONST(3)
+
+#define MSELECT2MC_AXI_R_RLAST_SHIFT                    _MK_SHIFT_CONST(74)
+#define MSELECT2MC_AXI_R_RLAST_FIELD                    (_MK_MASK_CONST(0x1) << MSELECT2MC_AXI_R_RLAST_SHIFT)
+#define MSELECT2MC_AXI_R_RLAST_RANGE                    _MK_SHIFT_CONST(74):_MK_SHIFT_CONST(74)
+#define MSELECT2MC_AXI_R_RLAST_ROW                      0
+#define MSELECT2MC_AXI_R_RLAST_DISABLED                 _MK_ENUM_CONST(0)
+#define MSELECT2MC_AXI_R_RLAST_ENABLED                  _MK_ENUM_CONST(1)
+
+
+// Packet AXI2MC_AXI_A
+#define AXI2MC_AXI_A_SIZE 58
+
+#define AXI2MC_AXI_A_AADDR_SHIFT                        _MK_SHIFT_CONST(0)
+#define AXI2MC_AXI_A_AADDR_FIELD                        (_MK_MASK_CONST(0xffffffff) << AXI2MC_AXI_A_AADDR_SHIFT)
+#define AXI2MC_AXI_A_AADDR_RANGE                        _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define AXI2MC_AXI_A_AADDR_ROW                  0
+
+#define AXI2MC_AXI_A_AID_SHIFT                  _MK_SHIFT_CONST(32)
+#define AXI2MC_AXI_A_AID_FIELD                  (_MK_MASK_CONST(0xff) << AXI2MC_AXI_A_AID_SHIFT)
+#define AXI2MC_AXI_A_AID_RANGE                  _MK_SHIFT_CONST(39):_MK_SHIFT_CONST(32)
+#define AXI2MC_AXI_A_AID_ROW                    0
+
+#define AXI2MC_AXI_A_ALEN_SHIFT                 _MK_SHIFT_CONST(40)
+#define AXI2MC_AXI_A_ALEN_FIELD                 (_MK_MASK_CONST(0xf) << AXI2MC_AXI_A_ALEN_SHIFT)
+#define AXI2MC_AXI_A_ALEN_RANGE                 _MK_SHIFT_CONST(43):_MK_SHIFT_CONST(40)
+#define AXI2MC_AXI_A_ALEN_ROW                   0
+#define AXI2MC_AXI_A_ALEN_ONEDATA                       _MK_ENUM_CONST(0)
+#define AXI2MC_AXI_A_ALEN_TWODATA                       _MK_ENUM_CONST(1)
+#define AXI2MC_AXI_A_ALEN_THREEDATA                     _MK_ENUM_CONST(2)
+#define AXI2MC_AXI_A_ALEN_FOURDATA                      _MK_ENUM_CONST(3)
+#define AXI2MC_AXI_A_ALEN_FIVEDATA                      _MK_ENUM_CONST(4)
+#define AXI2MC_AXI_A_ALEN_SIXDATA                       _MK_ENUM_CONST(5)
+#define AXI2MC_AXI_A_ALEN_SEVENDATA                     _MK_ENUM_CONST(6)
+#define AXI2MC_AXI_A_ALEN_EIGHTDATA                     _MK_ENUM_CONST(7)
+#define AXI2MC_AXI_A_ALEN_NINEDATA                      _MK_ENUM_CONST(8)
+#define AXI2MC_AXI_A_ALEN_TENDATA                       _MK_ENUM_CONST(9)
+#define AXI2MC_AXI_A_ALEN_ELEVENDATA                    _MK_ENUM_CONST(10)
+#define AXI2MC_AXI_A_ALEN_TWELVEDATA                    _MK_ENUM_CONST(11)
+#define AXI2MC_AXI_A_ALEN_THIRTEENDATA                  _MK_ENUM_CONST(12)
+#define AXI2MC_AXI_A_ALEN_FOURTEENDATA                  _MK_ENUM_CONST(13)
+#define AXI2MC_AXI_A_ALEN_FIFTHTEENDATA                 _MK_ENUM_CONST(14)
+#define AXI2MC_AXI_A_ALEN_SIXTEENDATA                   _MK_ENUM_CONST(15)
+
+#define AXI2MC_AXI_A_ASIZE_SHIFT                        _MK_SHIFT_CONST(44)
+#define AXI2MC_AXI_A_ASIZE_FIELD                        (_MK_MASK_CONST(0x7) << AXI2MC_AXI_A_ASIZE_SHIFT)
+#define AXI2MC_AXI_A_ASIZE_RANGE                        _MK_SHIFT_CONST(46):_MK_SHIFT_CONST(44)
+#define AXI2MC_AXI_A_ASIZE_ROW                  0
+#define AXI2MC_AXI_A_ASIZE_ONEBYTE                      _MK_ENUM_CONST(0)
+#define AXI2MC_AXI_A_ASIZE_TWOBYTES                     _MK_ENUM_CONST(1)
+#define AXI2MC_AXI_A_ASIZE_FOURBYTES                    _MK_ENUM_CONST(2)
+#define AXI2MC_AXI_A_ASIZE_EIGHTBYTES                   _MK_ENUM_CONST(3)
+#define AXI2MC_AXI_A_ASIZE_SIXTEENBYTES                 _MK_ENUM_CONST(4)
+#define AXI2MC_AXI_A_ASIZE_THIRTYTWOBYTES                       _MK_ENUM_CONST(5)
+#define AXI2MC_AXI_A_ASIZE_SIXTYFOURBYTES                       _MK_ENUM_CONST(6)
+#define AXI2MC_AXI_A_ASIZE_ONEHUNDREDTWENTYEIGHTBYTES                   _MK_ENUM_CONST(7)
+
+#define AXI2MC_AXI_A_ABURST_SHIFT                       _MK_SHIFT_CONST(47)
+#define AXI2MC_AXI_A_ABURST_FIELD                       (_MK_MASK_CONST(0x3) << AXI2MC_AXI_A_ABURST_SHIFT)
+#define AXI2MC_AXI_A_ABURST_RANGE                       _MK_SHIFT_CONST(48):_MK_SHIFT_CONST(47)
+#define AXI2MC_AXI_A_ABURST_ROW                 0
+#define AXI2MC_AXI_A_ABURST_FIXED                       _MK_ENUM_CONST(0)
+#define AXI2MC_AXI_A_ABURST_INCR                        _MK_ENUM_CONST(1)
+#define AXI2MC_AXI_A_ABURST_WRAP                        _MK_ENUM_CONST(2)
+#define AXI2MC_AXI_A_ABURST_RSVD                        _MK_ENUM_CONST(3)
+
+#define AXI2MC_AXI_A_ALOCK_SHIFT                        _MK_SHIFT_CONST(49)
+#define AXI2MC_AXI_A_ALOCK_FIELD                        (_MK_MASK_CONST(0x3) << AXI2MC_AXI_A_ALOCK_SHIFT)
+#define AXI2MC_AXI_A_ALOCK_RANGE                        _MK_SHIFT_CONST(50):_MK_SHIFT_CONST(49)
+#define AXI2MC_AXI_A_ALOCK_ROW                  0
+#define AXI2MC_AXI_A_ALOCK_NORMAL                       _MK_ENUM_CONST(0)
+#define AXI2MC_AXI_A_ALOCK_EXCLUSIVE                    _MK_ENUM_CONST(1)
+#define AXI2MC_AXI_A_ALOCK_LOCKED                       _MK_ENUM_CONST(2)
+#define AXI2MC_AXI_A_ALOCK_RSVD                 _MK_ENUM_CONST(3)
+
+#define AXI2MC_AXI_A_ACACHE_SHIFT                       _MK_SHIFT_CONST(51)
+#define AXI2MC_AXI_A_ACACHE_FIELD                       (_MK_MASK_CONST(0xf) << AXI2MC_AXI_A_ACACHE_SHIFT)
+#define AXI2MC_AXI_A_ACACHE_RANGE                       _MK_SHIFT_CONST(54):_MK_SHIFT_CONST(51)
+#define AXI2MC_AXI_A_ACACHE_ROW                 0
+#define AXI2MC_AXI_A_ACACHE_NONCACHEABLE_NONBUFFERABLE                  _MK_ENUM_CONST(0)
+#define AXI2MC_AXI_A_ACACHE_BUFFERABLE                  _MK_ENUM_CONST(1)
+#define AXI2MC_AXI_A_ACACHE_CACHEABLE_DONOTALLOCATE                     _MK_ENUM_CONST(2)
+#define AXI2MC_AXI_A_ACACHE_CACHEABLE_BUFFERABLE_DONOTALLOCATE                  _MK_ENUM_CONST(3)
+#define AXI2MC_AXI_A_ACACHE_CACHEABLEWRITETHROUGH_ALLOCATEONREAD                        _MK_ENUM_CONST(6)
+#define AXI2MC_AXI_A_ACACHE_CACHEABLEWRITEBACK_ALLOCATEONREAD                   _MK_ENUM_CONST(7)
+#define AXI2MC_AXI_A_ACACHE_CACHEABLEWRITETHROUGH_ALLOCATEONWRITE                       _MK_ENUM_CONST(10)
+#define AXI2MC_AXI_A_ACACHE_CACHEABLEWRITEBACK_ALLOCATEONWRITE                  _MK_ENUM_CONST(11)
+#define AXI2MC_AXI_A_ACACHE_CACHEABLEWRITETHROUGH_ALLOCATEONREADWRITE                   _MK_ENUM_CONST(14)
+#define AXI2MC_AXI_A_ACACHE_CACHEABLEWRITEBACK_ALLOCATEONREADWRITE                      _MK_ENUM_CONST(15)
+
+#define AXI2MC_AXI_A_APROT_SHIFT                        _MK_SHIFT_CONST(55)
+#define AXI2MC_AXI_A_APROT_FIELD                        (_MK_MASK_CONST(0x7) << AXI2MC_AXI_A_APROT_SHIFT)
+#define AXI2MC_AXI_A_APROT_RANGE                        _MK_SHIFT_CONST(57):_MK_SHIFT_CONST(55)
+#define AXI2MC_AXI_A_APROT_ROW                  0
+#define AXI2MC_AXI_A_APROT_DATA_SECURE_NORMAL                   _MK_ENUM_CONST(0)
+#define AXI2MC_AXI_A_APROT_DATA_SECURE_PRIVILEGED                       _MK_ENUM_CONST(1)
+#define AXI2MC_AXI_A_APROT_DATA_NONSECURE_NORMAL                        _MK_ENUM_CONST(2)
+#define AXI2MC_AXI_A_APROT_DATA_NONSECURE_PRIVILEGED                    _MK_ENUM_CONST(3)
+#define AXI2MC_AXI_A_APROT_INST_SECURE_NORMAL                   _MK_ENUM_CONST(4)
+#define AXI2MC_AXI_A_APROT_INST_SECURE_PRIVILEGED                       _MK_ENUM_CONST(5)
+#define AXI2MC_AXI_A_APROT_INST_NONSECURE_NORMAL                        _MK_ENUM_CONST(6)
+#define AXI2MC_AXI_A_APROT_INST_NONSECURE_PRIVILEGED                    _MK_ENUM_CONST(7)
+
+
+// Packet AXI2MC_AXI_W
+#define AXI2MC_AXI_W_SIZE 297
+
+#define AXI2MC_AXI_W_WDATA_SHIFT                        _MK_SHIFT_CONST(0)
+#define AXI2MC_AXI_W_WDATA_FIELD                        (_MK_MASK_CONST(0xffffffff) << AXI2MC_AXI_W_WDATA_SHIFT)
+#define AXI2MC_AXI_W_WDATA_RANGE                        _MK_SHIFT_CONST(255):_MK_SHIFT_CONST(0)
+#define AXI2MC_AXI_W_WDATA_ROW                  0
+
+#define AXI2MC_AXI_W_WID_SHIFT                  _MK_SHIFT_CONST(256)
+#define AXI2MC_AXI_W_WID_FIELD                  (_MK_MASK_CONST(0xff) << AXI2MC_AXI_W_WID_SHIFT)
+#define AXI2MC_AXI_W_WID_RANGE                  _MK_SHIFT_CONST(263):_MK_SHIFT_CONST(256)
+#define AXI2MC_AXI_W_WID_ROW                    0
+
+#define AXI2MC_AXI_W_WSTRB_SHIFT                        _MK_SHIFT_CONST(264)
+#define AXI2MC_AXI_W_WSTRB_FIELD                        (_MK_MASK_CONST(0xffffffff) << AXI2MC_AXI_W_WSTRB_SHIFT)
+#define AXI2MC_AXI_W_WSTRB_RANGE                        _MK_SHIFT_CONST(295):_MK_SHIFT_CONST(264)
+#define AXI2MC_AXI_W_WSTRB_ROW                  0
+
+#define AXI2MC_AXI_W_WLAST_SHIFT                        _MK_SHIFT_CONST(296)
+#define AXI2MC_AXI_W_WLAST_FIELD                        (_MK_MASK_CONST(0x1) << AXI2MC_AXI_W_WLAST_SHIFT)
+#define AXI2MC_AXI_W_WLAST_RANGE                        _MK_SHIFT_CONST(296):_MK_SHIFT_CONST(296)
+#define AXI2MC_AXI_W_WLAST_ROW                  0
+#define AXI2MC_AXI_W_WLAST_DISABLED                     _MK_ENUM_CONST(0)
+#define AXI2MC_AXI_W_WLAST_ENABLED                      _MK_ENUM_CONST(1)
+
+
+// Packet AXI2MC_AXI_B
+#define AXI2MC_AXI_B_SIZE 10
+
+#define AXI2MC_AXI_B_BID_SHIFT                  _MK_SHIFT_CONST(0)
+#define AXI2MC_AXI_B_BID_FIELD                  (_MK_MASK_CONST(0xff) << AXI2MC_AXI_B_BID_SHIFT)
+#define AXI2MC_AXI_B_BID_RANGE                  _MK_SHIFT_CONST(7):_MK_SHIFT_CONST(0)
+#define AXI2MC_AXI_B_BID_ROW                    0
+
+#define AXI2MC_AXI_B_BRESP_SHIFT                        _MK_SHIFT_CONST(8)
+#define AXI2MC_AXI_B_BRESP_FIELD                        (_MK_MASK_CONST(0x3) << AXI2MC_AXI_B_BRESP_SHIFT)
+#define AXI2MC_AXI_B_BRESP_RANGE                        _MK_SHIFT_CONST(9):_MK_SHIFT_CONST(8)
+#define AXI2MC_AXI_B_BRESP_ROW                  0
+#define AXI2MC_AXI_B_BRESP_OKAY                 _MK_ENUM_CONST(0)
+#define AXI2MC_AXI_B_BRESP_EXOKAY                       _MK_ENUM_CONST(1)
+#define AXI2MC_AXI_B_BRESP_SLVERR                       _MK_ENUM_CONST(2)
+#define AXI2MC_AXI_B_BRESP_DECERR                       _MK_ENUM_CONST(3)
+
+
+// Packet AXI2MC_AXI_R
+#define AXI2MC_AXI_R_SIZE 267
+
+#define AXI2MC_AXI_R_RDATA_SHIFT                        _MK_SHIFT_CONST(0)
+#define AXI2MC_AXI_R_RDATA_FIELD                        (_MK_MASK_CONST(0xffffffff) << AXI2MC_AXI_R_RDATA_SHIFT)
+#define AXI2MC_AXI_R_RDATA_RANGE                        _MK_SHIFT_CONST(255):_MK_SHIFT_CONST(0)
+#define AXI2MC_AXI_R_RDATA_ROW                  0
+
+#define AXI2MC_AXI_R_RID_SHIFT                  _MK_SHIFT_CONST(256)
+#define AXI2MC_AXI_R_RID_FIELD                  (_MK_MASK_CONST(0xff) << AXI2MC_AXI_R_RID_SHIFT)
+#define AXI2MC_AXI_R_RID_RANGE                  _MK_SHIFT_CONST(263):_MK_SHIFT_CONST(256)
+#define AXI2MC_AXI_R_RID_ROW                    0
+
+#define AXI2MC_AXI_R_RRESP_SHIFT                        _MK_SHIFT_CONST(264)
+#define AXI2MC_AXI_R_RRESP_FIELD                        (_MK_MASK_CONST(0x3) << AXI2MC_AXI_R_RRESP_SHIFT)
+#define AXI2MC_AXI_R_RRESP_RANGE                        _MK_SHIFT_CONST(265):_MK_SHIFT_CONST(264)
+#define AXI2MC_AXI_R_RRESP_ROW                  0
+#define AXI2MC_AXI_R_RRESP_OKAY                 _MK_ENUM_CONST(0)
+#define AXI2MC_AXI_R_RRESP_EXOKAY                       _MK_ENUM_CONST(1)
+#define AXI2MC_AXI_R_RRESP_SLVERR                       _MK_ENUM_CONST(2)
+#define AXI2MC_AXI_R_RRESP_DECERR                       _MK_ENUM_CONST(3)
+
+#define AXI2MC_AXI_R_RLAST_SHIFT                        _MK_SHIFT_CONST(266)
+#define AXI2MC_AXI_R_RLAST_FIELD                        (_MK_MASK_CONST(0x1) << AXI2MC_AXI_R_RLAST_SHIFT)
+#define AXI2MC_AXI_R_RLAST_RANGE                        _MK_SHIFT_CONST(266):_MK_SHIFT_CONST(266)
+#define AXI2MC_AXI_R_RLAST_ROW                  0
+#define AXI2MC_AXI_R_RLAST_DISABLED                     _MK_ENUM_CONST(0)
+#define AXI2MC_AXI_R_RLAST_ENABLED                      _MK_ENUM_CONST(1)
+
+
+// Packet MC_AXI_RWREQ
+#define MC_AXI_RWREQ_SIZE 107
+
+#define MC_AXI_RWREQ_AADDR_SHIFT                        _MK_SHIFT_CONST(0)
+#define MC_AXI_RWREQ_AADDR_FIELD                        (_MK_MASK_CONST(0xffffffff) << MC_AXI_RWREQ_AADDR_SHIFT)
+#define MC_AXI_RWREQ_AADDR_RANGE                        _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define MC_AXI_RWREQ_AADDR_ROW                  0
+
+#define MC_AXI_RWREQ_AID_SHIFT                  _MK_SHIFT_CONST(32)
+#define MC_AXI_RWREQ_AID_FIELD                  (_MK_MASK_CONST(0xff) << MC_AXI_RWREQ_AID_SHIFT)
+#define MC_AXI_RWREQ_AID_RANGE                  _MK_SHIFT_CONST(39):_MK_SHIFT_CONST(32)
+#define MC_AXI_RWREQ_AID_ROW                    0
+
+#define MC_AXI_RWREQ_ALEN_SHIFT                 _MK_SHIFT_CONST(40)
+#define MC_AXI_RWREQ_ALEN_FIELD                 (_MK_MASK_CONST(0xf) << MC_AXI_RWREQ_ALEN_SHIFT)
+#define MC_AXI_RWREQ_ALEN_RANGE                 _MK_SHIFT_CONST(43):_MK_SHIFT_CONST(40)
+#define MC_AXI_RWREQ_ALEN_ROW                   0
+
+#define MC_AXI_RWREQ_ASIZE_SHIFT                        _MK_SHIFT_CONST(44)
+#define MC_AXI_RWREQ_ASIZE_FIELD                        (_MK_MASK_CONST(0x7) << MC_AXI_RWREQ_ASIZE_SHIFT)
+#define MC_AXI_RWREQ_ASIZE_RANGE                        _MK_SHIFT_CONST(46):_MK_SHIFT_CONST(44)
+#define MC_AXI_RWREQ_ASIZE_ROW                  2
+
+#define MC_AXI_RWREQ_ABURST_SHIFT                       _MK_SHIFT_CONST(47)
+#define MC_AXI_RWREQ_ABURST_FIELD                       (_MK_MASK_CONST(0x3) << MC_AXI_RWREQ_ABURST_SHIFT)
+#define MC_AXI_RWREQ_ABURST_RANGE                       _MK_SHIFT_CONST(48):_MK_SHIFT_CONST(47)
+#define MC_AXI_RWREQ_ABURST_ROW                 0
+#define MC_AXI_RWREQ_ABURST_FIXED                       _MK_ENUM_CONST(0)
+#define MC_AXI_RWREQ_ABURST_INCR                        _MK_ENUM_CONST(1)
+#define MC_AXI_RWREQ_ABURST_WRAP                        _MK_ENUM_CONST(2)
+#define MC_AXI_RWREQ_ABURST_RSVD                        _MK_ENUM_CONST(3)
+
+#define MC_AXI_RWREQ_ALOCK_SHIFT                        _MK_SHIFT_CONST(49)
+#define MC_AXI_RWREQ_ALOCK_FIELD                        (_MK_MASK_CONST(0x3) << MC_AXI_RWREQ_ALOCK_SHIFT)
+#define MC_AXI_RWREQ_ALOCK_RANGE                        _MK_SHIFT_CONST(50):_MK_SHIFT_CONST(49)
+#define MC_AXI_RWREQ_ALOCK_ROW                  0
+
+#define MC_AXI_RWREQ_ACACHE_SHIFT                       _MK_SHIFT_CONST(51)
+#define MC_AXI_RWREQ_ACACHE_FIELD                       (_MK_MASK_CONST(0xf) << MC_AXI_RWREQ_ACACHE_SHIFT)
+#define MC_AXI_RWREQ_ACACHE_RANGE                       _MK_SHIFT_CONST(54):_MK_SHIFT_CONST(51)
+#define MC_AXI_RWREQ_ACACHE_ROW                 0
+
+#define MC_AXI_RWREQ_APROT_SHIFT                        _MK_SHIFT_CONST(55)
+#define MC_AXI_RWREQ_APROT_FIELD                        (_MK_MASK_CONST(0x7) << MC_AXI_RWREQ_APROT_SHIFT)
+#define MC_AXI_RWREQ_APROT_RANGE                        _MK_SHIFT_CONST(57):_MK_SHIFT_CONST(55)
+#define MC_AXI_RWREQ_APROT_ROW                  0
+
+#define MC_AXI_RWREQ_ASB_SHIFT                  _MK_SHIFT_CONST(58)
+#define MC_AXI_RWREQ_ASB_FIELD                  (_MK_MASK_CONST(0x3) << MC_AXI_RWREQ_ASB_SHIFT)
+#define MC_AXI_RWREQ_ASB_RANGE                  _MK_SHIFT_CONST(59):_MK_SHIFT_CONST(58)
+#define MC_AXI_RWREQ_ASB_ROW                    0
+
+#define MC_AXI_RWREQ_ARW_SHIFT                  _MK_SHIFT_CONST(60)
+#define MC_AXI_RWREQ_ARW_FIELD                  (_MK_MASK_CONST(0x1) << MC_AXI_RWREQ_ARW_SHIFT)
+#define MC_AXI_RWREQ_ARW_RANGE                  _MK_SHIFT_CONST(60):_MK_SHIFT_CONST(60)
+#define MC_AXI_RWREQ_ARW_ROW                    0
+
+#define MC_AXI_RWREQ_ACT_AADDR_SHIFT                    _MK_SHIFT_CONST(61)
+#define MC_AXI_RWREQ_ACT_AADDR_FIELD                    (_MK_MASK_CONST(0xffffffff) << MC_AXI_RWREQ_ACT_AADDR_SHIFT)
+#define MC_AXI_RWREQ_ACT_AADDR_RANGE                    _MK_SHIFT_CONST(92):_MK_SHIFT_CONST(61)
+#define MC_AXI_RWREQ_ACT_AADDR_ROW                      0
+
+#define MC_AXI_RWREQ_ACT_ALEN_SHIFT                     _MK_SHIFT_CONST(93)
+#define MC_AXI_RWREQ_ACT_ALEN_FIELD                     (_MK_MASK_CONST(0xf) << MC_AXI_RWREQ_ACT_ALEN_SHIFT)
+#define MC_AXI_RWREQ_ACT_ALEN_RANGE                     _MK_SHIFT_CONST(96):_MK_SHIFT_CONST(93)
+#define MC_AXI_RWREQ_ACT_ALEN_ROW                       0
+
+#define MC_AXI_RWREQ_ACT_ASIZE_SHIFT                    _MK_SHIFT_CONST(97)
+#define MC_AXI_RWREQ_ACT_ASIZE_FIELD                    (_MK_MASK_CONST(0x7) << MC_AXI_RWREQ_ACT_ASIZE_SHIFT)
+#define MC_AXI_RWREQ_ACT_ASIZE_RANGE                    _MK_SHIFT_CONST(99):_MK_SHIFT_CONST(97)
+#define MC_AXI_RWREQ_ACT_ASIZE_ROW                      0
+
+#define MC_AXI_RWREQ_DOUBLEREQ_SHIFT                    _MK_SHIFT_CONST(100)
+#define MC_AXI_RWREQ_DOUBLEREQ_FIELD                    (_MK_MASK_CONST(0x1) << MC_AXI_RWREQ_DOUBLEREQ_SHIFT)
+#define MC_AXI_RWREQ_DOUBLEREQ_RANGE                    _MK_SHIFT_CONST(100):_MK_SHIFT_CONST(100)
+#define MC_AXI_RWREQ_DOUBLEREQ_ROW                      0
+
+#define MC_AXI_RWREQ_ILLEGALACC_SHIFT                   _MK_SHIFT_CONST(101)
+#define MC_AXI_RWREQ_ILLEGALACC_FIELD                   (_MK_MASK_CONST(0x1) << MC_AXI_RWREQ_ILLEGALACC_SHIFT)
+#define MC_AXI_RWREQ_ILLEGALACC_RANGE                   _MK_SHIFT_CONST(101):_MK_SHIFT_CONST(101)
+#define MC_AXI_RWREQ_ILLEGALACC_ROW                     0
+
+#define MC_AXI_RWREQ_TAG_SHIFT                  _MK_SHIFT_CONST(102)
+#define MC_AXI_RWREQ_TAG_FIELD                  (_MK_MASK_CONST(0x1f) << MC_AXI_RWREQ_TAG_SHIFT)
+#define MC_AXI_RWREQ_TAG_RANGE                  _MK_SHIFT_CONST(106):_MK_SHIFT_CONST(102)
+#define MC_AXI_RWREQ_TAG_ROW                    0
+
+
+// Packet CSR_C2MC_RESET
+#define CSR_C2MC_RESET_SIZE 1
+
+#define CSR_C2MC_RESET_RSTN_SHIFT                       _MK_SHIFT_CONST(0)
+#define CSR_C2MC_RESET_RSTN_FIELD                       (_MK_MASK_CONST(0x1) << CSR_C2MC_RESET_RSTN_SHIFT)
+#define CSR_C2MC_RESET_RSTN_RANGE                       _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CSR_C2MC_RESET_RSTN_ROW                 0
+
+
+// Packet CSR_C2MC_REQ
+#define CSR_C2MC_REQ_SIZE 32
+
+#define CSR_C2MC_REQ_ADR_SHIFT                  _MK_SHIFT_CONST(0)
+#define CSR_C2MC_REQ_ADR_FIELD                  (_MK_MASK_CONST(0xffffffff) << CSR_C2MC_REQ_ADR_SHIFT)
+#define CSR_C2MC_REQ_ADR_RANGE                  _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CSR_C2MC_REQ_ADR_ROW                    0
+
+
+// Packet CSR_C2MC_BP_REQ
+#define CSR_C2MC_BP_REQ_SIZE 48
+
+#define CSR_C2MC_BP_REQ_BASEADR_SHIFT                   _MK_SHIFT_CONST(0)
+#define CSR_C2MC_BP_REQ_BASEADR_FIELD                   (_MK_MASK_CONST(0xffffffff) << CSR_C2MC_BP_REQ_BASEADR_SHIFT)
+#define CSR_C2MC_BP_REQ_BASEADR_RANGE                   _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CSR_C2MC_BP_REQ_BASEADR_ROW                     0
+
+#define CSR_C2MC_BP_REQ_PITCH_SHIFT                     _MK_SHIFT_CONST(32)
+#define CSR_C2MC_BP_REQ_PITCH_FIELD                     (_MK_MASK_CONST(0xffff) << CSR_C2MC_BP_REQ_PITCH_SHIFT)
+#define CSR_C2MC_BP_REQ_PITCH_RANGE                     _MK_SHIFT_CONST(47):_MK_SHIFT_CONST(32)
+#define CSR_C2MC_BP_REQ_PITCH_ROW                       0
+
+
+// Packet CSR_C2MC_ADRXY
+#define CSR_C2MC_ADRXY_SIZE 30
+
+#define CSR_C2MC_ADRXY_OFFX_SHIFT                       _MK_SHIFT_CONST(0)
+#define CSR_C2MC_ADRXY_OFFX_FIELD                       (_MK_MASK_CONST(0xffff) << CSR_C2MC_ADRXY_OFFX_SHIFT)
+#define CSR_C2MC_ADRXY_OFFX_RANGE                       _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(0)
+#define CSR_C2MC_ADRXY_OFFX_ROW                 0
+
+#define CSR_C2MC_ADRXY_OFFY_SHIFT                       _MK_SHIFT_CONST(16)
+#define CSR_C2MC_ADRXY_OFFY_FIELD                       (_MK_MASK_CONST(0x3fff) << CSR_C2MC_ADRXY_OFFY_SHIFT)
+#define CSR_C2MC_ADRXY_OFFY_RANGE                       _MK_SHIFT_CONST(29):_MK_SHIFT_CONST(16)
+#define CSR_C2MC_ADRXY_OFFY_ROW                 0
+
+
+// Packet CSR_C2MC_TILE
+#define CSR_C2MC_TILE_SIZE 33
+
+#define CSR_C2MC_TILE_LINADR_SHIFT                      _MK_SHIFT_CONST(0)
+#define CSR_C2MC_TILE_LINADR_FIELD                      (_MK_MASK_CONST(0xffffffff) << CSR_C2MC_TILE_LINADR_SHIFT)
+#define CSR_C2MC_TILE_LINADR_RANGE                      _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CSR_C2MC_TILE_LINADR_ROW                        0
+
+#define CSR_C2MC_TILE_TMODE_SHIFT                       _MK_SHIFT_CONST(32)
+#define CSR_C2MC_TILE_TMODE_FIELD                       (_MK_MASK_CONST(0x1) << CSR_C2MC_TILE_TMODE_SHIFT)
+#define CSR_C2MC_TILE_TMODE_RANGE                       _MK_SHIFT_CONST(32):_MK_SHIFT_CONST(32)
+#define CSR_C2MC_TILE_TMODE_ROW                 0
+#define CSR_C2MC_TILE_TMODE_LINEAR                      _MK_ENUM_CONST(0)
+#define CSR_C2MC_TILE_TMODE_TILED                       _MK_ENUM_CONST(1)
+
+
+// Packet CSR_C2MC_RDI
+#define CSR_C2MC_RDI_SIZE 256
+
+#define CSR_C2MC_RDI_RDI_SHIFT                  _MK_SHIFT_CONST(0)
+#define CSR_C2MC_RDI_RDI_FIELD                  (_MK_MASK_CONST(0xffffffff) << CSR_C2MC_RDI_RDI_SHIFT)
+#define CSR_C2MC_RDI_RDI_RANGE                  _MK_SHIFT_CONST(255):_MK_SHIFT_CONST(0)
+#define CSR_C2MC_RDI_RDI_ROW                    0
+
+
+// Packet CSR_C2MC_HP
+#define CSR_C2MC_HP_SIZE 38
+
+// high-priority threshold
+#define CSR_C2MC_HP_HPTH_SHIFT                  _MK_SHIFT_CONST(0)
+#define CSR_C2MC_HP_HPTH_FIELD                  (_MK_MASK_CONST(0xffffffff) << CSR_C2MC_HP_HPTH_SHIFT)
+#define CSR_C2MC_HP_HPTH_RANGE                  _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CSR_C2MC_HP_HPTH_ROW                    0
+
+// high-priority timer
+#define CSR_C2MC_HP_HPTM_SHIFT                  _MK_SHIFT_CONST(32)
+#define CSR_C2MC_HP_HPTM_FIELD                  (_MK_MASK_CONST(0x3f) << CSR_C2MC_HP_HPTM_SHIFT)
+#define CSR_C2MC_HP_HPTM_RANGE                  _MK_SHIFT_CONST(37):_MK_SHIFT_CONST(32)
+#define CSR_C2MC_HP_HPTM_ROW                    0
+
+
+// Packet CSW_C2MC_RESET
+#define CSW_C2MC_RESET_SIZE 1
+
+#define CSW_C2MC_RESET_RSTN_SHIFT                       _MK_SHIFT_CONST(0)
+#define CSW_C2MC_RESET_RSTN_FIELD                       (_MK_MASK_CONST(0x1) << CSW_C2MC_RESET_RSTN_SHIFT)
+#define CSW_C2MC_RESET_RSTN_RANGE                       _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CSW_C2MC_RESET_RSTN_ROW                 0
+
+
+// Packet CSW_C2MC_REQ
+#define CSW_C2MC_REQ_SIZE 321
+
+#define CSW_C2MC_REQ_ADR_SHIFT                  _MK_SHIFT_CONST(0)
+#define CSW_C2MC_REQ_ADR_FIELD                  (_MK_MASK_CONST(0xffffffff) << CSW_C2MC_REQ_ADR_SHIFT)
+#define CSW_C2MC_REQ_ADR_RANGE                  _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CSW_C2MC_REQ_ADR_ROW                    0
+
+#define CSW_C2MC_REQ_BE_SHIFT                   _MK_SHIFT_CONST(32)
+#define CSW_C2MC_REQ_BE_FIELD                   (_MK_MASK_CONST(0xffffffff) << CSW_C2MC_REQ_BE_SHIFT)
+#define CSW_C2MC_REQ_BE_RANGE                   _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(32)
+#define CSW_C2MC_REQ_BE_ROW                     0
+
+#define CSW_C2MC_REQ_WDO_SHIFT                  _MK_SHIFT_CONST(64)
+#define CSW_C2MC_REQ_WDO_FIELD                  (_MK_MASK_CONST(0xffffffff) << CSW_C2MC_REQ_WDO_SHIFT)
+#define CSW_C2MC_REQ_WDO_RANGE                  _MK_SHIFT_CONST(319):_MK_SHIFT_CONST(64)
+#define CSW_C2MC_REQ_WDO_ROW                    0
+
+#define CSW_C2MC_REQ_TAG_SHIFT                  _MK_SHIFT_CONST(320)
+#define CSW_C2MC_REQ_TAG_FIELD                  (_MK_MASK_CONST(0x1) << CSW_C2MC_REQ_TAG_SHIFT)
+#define CSW_C2MC_REQ_TAG_RANGE                  _MK_SHIFT_CONST(320):_MK_SHIFT_CONST(320)
+#define CSW_C2MC_REQ_TAG_ROW                    0
+
+
+// Packet CSW_C2MC_BP_REQ
+#define CSW_C2MC_BP_REQ_SIZE 337
+
+#define CSW_C2MC_BP_REQ_BASEADR_SHIFT                   _MK_SHIFT_CONST(0)
+#define CSW_C2MC_BP_REQ_BASEADR_FIELD                   (_MK_MASK_CONST(0xffffffff) << CSW_C2MC_BP_REQ_BASEADR_SHIFT)
+#define CSW_C2MC_BP_REQ_BASEADR_RANGE                   _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CSW_C2MC_BP_REQ_BASEADR_ROW                     0
+
+#define CSW_C2MC_BP_REQ_PITCH_SHIFT                     _MK_SHIFT_CONST(32)
+#define CSW_C2MC_BP_REQ_PITCH_FIELD                     (_MK_MASK_CONST(0xffff) << CSW_C2MC_BP_REQ_PITCH_SHIFT)
+#define CSW_C2MC_BP_REQ_PITCH_RANGE                     _MK_SHIFT_CONST(47):_MK_SHIFT_CONST(32)
+#define CSW_C2MC_BP_REQ_PITCH_ROW                       0
+
+#define CSW_C2MC_BP_REQ_BE_SHIFT                        _MK_SHIFT_CONST(48)
+#define CSW_C2MC_BP_REQ_BE_FIELD                        (_MK_MASK_CONST(0xffffffff) << CSW_C2MC_BP_REQ_BE_SHIFT)
+#define CSW_C2MC_BP_REQ_BE_RANGE                        _MK_SHIFT_CONST(79):_MK_SHIFT_CONST(48)
+#define CSW_C2MC_BP_REQ_BE_ROW                  0
+
+#define CSW_C2MC_BP_REQ_WDO_SHIFT                       _MK_SHIFT_CONST(80)
+#define CSW_C2MC_BP_REQ_WDO_FIELD                       (_MK_MASK_CONST(0xffffffff) << CSW_C2MC_BP_REQ_WDO_SHIFT)
+#define CSW_C2MC_BP_REQ_WDO_RANGE                       _MK_SHIFT_CONST(335):_MK_SHIFT_CONST(80)
+#define CSW_C2MC_BP_REQ_WDO_ROW                 0
+
+#define CSW_C2MC_BP_REQ_TAG_SHIFT                       _MK_SHIFT_CONST(336)
+#define CSW_C2MC_BP_REQ_TAG_FIELD                       (_MK_MASK_CONST(0x1) << CSW_C2MC_BP_REQ_TAG_SHIFT)
+#define CSW_C2MC_BP_REQ_TAG_RANGE                       _MK_SHIFT_CONST(336):_MK_SHIFT_CONST(336)
+#define CSW_C2MC_BP_REQ_TAG_ROW                 0
+
+
+// Packet CSW_C2MC_ADRXY
+#define CSW_C2MC_ADRXY_SIZE 30
+
+#define CSW_C2MC_ADRXY_OFFX_SHIFT                       _MK_SHIFT_CONST(0)
+#define CSW_C2MC_ADRXY_OFFX_FIELD                       (_MK_MASK_CONST(0xffff) << CSW_C2MC_ADRXY_OFFX_SHIFT)
+#define CSW_C2MC_ADRXY_OFFX_RANGE                       _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(0)
+#define CSW_C2MC_ADRXY_OFFX_ROW                 0
+
+#define CSW_C2MC_ADRXY_OFFY_SHIFT                       _MK_SHIFT_CONST(16)
+#define CSW_C2MC_ADRXY_OFFY_FIELD                       (_MK_MASK_CONST(0x3fff) << CSW_C2MC_ADRXY_OFFY_SHIFT)
+#define CSW_C2MC_ADRXY_OFFY_RANGE                       _MK_SHIFT_CONST(29):_MK_SHIFT_CONST(16)
+#define CSW_C2MC_ADRXY_OFFY_ROW                 0
+
+
+// Packet CSW_C2MC_TILE
+#define CSW_C2MC_TILE_SIZE 33
+
+#define CSW_C2MC_TILE_LINADR_SHIFT                      _MK_SHIFT_CONST(0)
+#define CSW_C2MC_TILE_LINADR_FIELD                      (_MK_MASK_CONST(0xffffffff) << CSW_C2MC_TILE_LINADR_SHIFT)
+#define CSW_C2MC_TILE_LINADR_RANGE                      _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CSW_C2MC_TILE_LINADR_ROW                        0
+
+#define CSW_C2MC_TILE_TMODE_SHIFT                       _MK_SHIFT_CONST(32)
+#define CSW_C2MC_TILE_TMODE_FIELD                       (_MK_MASK_CONST(0x1) << CSW_C2MC_TILE_TMODE_SHIFT)
+#define CSW_C2MC_TILE_TMODE_RANGE                       _MK_SHIFT_CONST(32):_MK_SHIFT_CONST(32)
+#define CSW_C2MC_TILE_TMODE_ROW                 0
+#define CSW_C2MC_TILE_TMODE_LINEAR                      _MK_ENUM_CONST(0)
+#define CSW_C2MC_TILE_TMODE_TILED                       _MK_ENUM_CONST(1)
+
+
+// Packet CSW_C2MC_XDI
+#define CSW_C2MC_XDI_SIZE 1
+
+// fake data
+#define CSW_C2MC_XDI_XDI_SHIFT                  _MK_SHIFT_CONST(0)
+#define CSW_C2MC_XDI_XDI_FIELD                  (_MK_MASK_CONST(0x1) << CSW_C2MC_XDI_XDI_SHIFT)
+#define CSW_C2MC_XDI_XDI_RANGE                  _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CSW_C2MC_XDI_XDI_ROW                    0
+
+
+// Packet CSW_C2MC_HP
+#define CSW_C2MC_HP_SIZE 32
+
+// high-priority threshold
+#define CSW_C2MC_HP_HPTH_SHIFT                  _MK_SHIFT_CONST(0)
+#define CSW_C2MC_HP_HPTH_FIELD                  (_MK_MASK_CONST(0xffffffff) << CSW_C2MC_HP_HPTH_SHIFT)
+#define CSW_C2MC_HP_HPTH_RANGE                  _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CSW_C2MC_HP_HPTH_ROW                    0
+
+
+// Packet CSW_C2MC_WCOAL
+#define CSW_C2MC_WCOAL_SIZE 32
+
+// write-coalescing time-out
+#define CSW_C2MC_WCOAL_WCOALTM_SHIFT                    _MK_SHIFT_CONST(0)
+#define CSW_C2MC_WCOAL_WCOALTM_FIELD                    (_MK_MASK_CONST(0xffffffff) << CSW_C2MC_WCOAL_WCOALTM_SHIFT)
+#define CSW_C2MC_WCOAL_WCOALTM_RANGE                    _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CSW_C2MC_WCOAL_WCOALTM_ROW                      0
+
+
+// Packet CBR_C2MC_RESET
+#define CBR_C2MC_RESET_SIZE 1
+
+#define CBR_C2MC_RESET_RSTN_SHIFT                       _MK_SHIFT_CONST(0)
+#define CBR_C2MC_RESET_RSTN_FIELD                       (_MK_MASK_CONST(0x1) << CBR_C2MC_RESET_RSTN_SHIFT)
+#define CBR_C2MC_RESET_RSTN_RANGE                       _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CBR_C2MC_RESET_RSTN_ROW                 0
+
+
+// Packet CBR_C2MC_REQP
+#define CBR_C2MC_REQP_SIZE 263
+
+#define CBR_C2MC_REQP_ADR_SHIFT                 _MK_SHIFT_CONST(0)
+#define CBR_C2MC_REQP_ADR_FIELD                 (_MK_MASK_CONST(0xffffffff) << CBR_C2MC_REQP_ADR_SHIFT)
+#define CBR_C2MC_REQP_ADR_RANGE                 _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CBR_C2MC_REQP_ADR_ROW                   0
+
+#define CBR_C2MC_REQP_ADRU_SHIFT                        _MK_SHIFT_CONST(32)
+#define CBR_C2MC_REQP_ADRU_FIELD                        (_MK_MASK_CONST(0xffffffff) << CBR_C2MC_REQP_ADRU_SHIFT)
+#define CBR_C2MC_REQP_ADRU_RANGE                        _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(32)
+#define CBR_C2MC_REQP_ADRU_ROW                  0
+
+#define CBR_C2MC_REQP_ADRV_SHIFT                        _MK_SHIFT_CONST(64)
+#define CBR_C2MC_REQP_ADRV_FIELD                        (_MK_MASK_CONST(0xffffffff) << CBR_C2MC_REQP_ADRV_SHIFT)
+#define CBR_C2MC_REQP_ADRV_RANGE                        _MK_SHIFT_CONST(95):_MK_SHIFT_CONST(64)
+#define CBR_C2MC_REQP_ADRV_ROW                  0
+
+#define CBR_C2MC_REQP_LS_SHIFT                  _MK_SHIFT_CONST(96)
+#define CBR_C2MC_REQP_LS_FIELD                  (_MK_MASK_CONST(0xffffffff) << CBR_C2MC_REQP_LS_SHIFT)
+#define CBR_C2MC_REQP_LS_RANGE                  _MK_SHIFT_CONST(127):_MK_SHIFT_CONST(96)
+#define CBR_C2MC_REQP_LS_ROW                    0
+
+#define CBR_C2MC_REQP_LSUV_SHIFT                        _MK_SHIFT_CONST(128)
+#define CBR_C2MC_REQP_LSUV_FIELD                        (_MK_MASK_CONST(0xffffffff) << CBR_C2MC_REQP_LSUV_SHIFT)
+#define CBR_C2MC_REQP_LSUV_RANGE                        _MK_SHIFT_CONST(159):_MK_SHIFT_CONST(128)
+#define CBR_C2MC_REQP_LSUV_ROW                  0
+
+#define CBR_C2MC_REQP_HS_SHIFT                  _MK_SHIFT_CONST(160)
+#define CBR_C2MC_REQP_HS_FIELD                  (_MK_MASK_CONST(0xffffffff) << CBR_C2MC_REQP_HS_SHIFT)
+#define CBR_C2MC_REQP_HS_RANGE                  _MK_SHIFT_CONST(191):_MK_SHIFT_CONST(160)
+#define CBR_C2MC_REQP_HS_ROW                    0
+
+#define CBR_C2MC_REQP_VS_SHIFT                  _MK_SHIFT_CONST(192)
+#define CBR_C2MC_REQP_VS_FIELD                  (_MK_MASK_CONST(0xffffffff) << CBR_C2MC_REQP_VS_SHIFT)
+#define CBR_C2MC_REQP_VS_RANGE                  _MK_SHIFT_CONST(223):_MK_SHIFT_CONST(192)
+#define CBR_C2MC_REQP_VS_ROW                    0
+
+#define CBR_C2MC_REQP_DL_SHIFT                  _MK_SHIFT_CONST(224)
+#define CBR_C2MC_REQP_DL_FIELD                  (_MK_MASK_CONST(0xffffffff) << CBR_C2MC_REQP_DL_SHIFT)
+#define CBR_C2MC_REQP_DL_RANGE                  _MK_SHIFT_CONST(255):_MK_SHIFT_CONST(224)
+#define CBR_C2MC_REQP_DL_ROW                    0
+
+#define CBR_C2MC_REQP_HD_SHIFT                  _MK_SHIFT_CONST(256)
+#define CBR_C2MC_REQP_HD_FIELD                  (_MK_MASK_CONST(0x1) << CBR_C2MC_REQP_HD_SHIFT)
+#define CBR_C2MC_REQP_HD_RANGE                  _MK_SHIFT_CONST(256):_MK_SHIFT_CONST(256)
+#define CBR_C2MC_REQP_HD_ROW                    0
+
+#define CBR_C2MC_REQP_VD_SHIFT                  _MK_SHIFT_CONST(257)
+#define CBR_C2MC_REQP_VD_FIELD                  (_MK_MASK_CONST(0x1) << CBR_C2MC_REQP_VD_SHIFT)
+#define CBR_C2MC_REQP_VD_RANGE                  _MK_SHIFT_CONST(257):_MK_SHIFT_CONST(257)
+#define CBR_C2MC_REQP_VD_ROW                    0
+
+#define CBR_C2MC_REQP_VX2_SHIFT                 _MK_SHIFT_CONST(258)
+#define CBR_C2MC_REQP_VX2_FIELD                 (_MK_MASK_CONST(0x1) << CBR_C2MC_REQP_VX2_SHIFT)
+#define CBR_C2MC_REQP_VX2_RANGE                 _MK_SHIFT_CONST(258):_MK_SHIFT_CONST(258)
+#define CBR_C2MC_REQP_VX2_ROW                   0
+
+#define CBR_C2MC_REQP_LP_SHIFT                  _MK_SHIFT_CONST(259)
+#define CBR_C2MC_REQP_LP_FIELD                  (_MK_MASK_CONST(0x1) << CBR_C2MC_REQP_LP_SHIFT)
+#define CBR_C2MC_REQP_LP_RANGE                  _MK_SHIFT_CONST(259):_MK_SHIFT_CONST(259)
+#define CBR_C2MC_REQP_LP_ROW                    0
+
+#define CBR_C2MC_REQP_YUV_SHIFT                 _MK_SHIFT_CONST(260)
+#define CBR_C2MC_REQP_YUV_FIELD                 (_MK_MASK_CONST(0x7) << CBR_C2MC_REQP_YUV_SHIFT)
+#define CBR_C2MC_REQP_YUV_RANGE                 _MK_SHIFT_CONST(262):_MK_SHIFT_CONST(260)
+#define CBR_C2MC_REQP_YUV_ROW                   0
+
+
+// Packet CBR_C2MC_ADRXY
+#define CBR_C2MC_ADRXY_SIZE 44
+
+#define CBR_C2MC_ADRXY_OFFX_SHIFT                       _MK_SHIFT_CONST(0)
+#define CBR_C2MC_ADRXY_OFFX_FIELD                       (_MK_MASK_CONST(0xffff) << CBR_C2MC_ADRXY_OFFX_SHIFT)
+#define CBR_C2MC_ADRXY_OFFX_RANGE                       _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(0)
+#define CBR_C2MC_ADRXY_OFFX_ROW                 0
+
+#define CBR_C2MC_ADRXY_OFFY_SHIFT                       _MK_SHIFT_CONST(16)
+#define CBR_C2MC_ADRXY_OFFY_FIELD                       (_MK_MASK_CONST(0x3fff) << CBR_C2MC_ADRXY_OFFY_SHIFT)
+#define CBR_C2MC_ADRXY_OFFY_RANGE                       _MK_SHIFT_CONST(29):_MK_SHIFT_CONST(16)
+#define CBR_C2MC_ADRXY_OFFY_ROW                 0
+
+#define CBR_C2MC_ADRXY_OFFYUV_SHIFT                     _MK_SHIFT_CONST(30)
+#define CBR_C2MC_ADRXY_OFFYUV_FIELD                     (_MK_MASK_CONST(0x3fff) << CBR_C2MC_ADRXY_OFFYUV_SHIFT)
+#define CBR_C2MC_ADRXY_OFFYUV_RANGE                     _MK_SHIFT_CONST(43):_MK_SHIFT_CONST(30)
+#define CBR_C2MC_ADRXY_OFFYUV_ROW                       0
+
+
+// Packet CBR_C2MC_TILE
+#define CBR_C2MC_TILE_SIZE 98
+
+#define CBR_C2MC_TILE_LINADR_SHIFT                      _MK_SHIFT_CONST(0)
+#define CBR_C2MC_TILE_LINADR_FIELD                      (_MK_MASK_CONST(0xffffffff) << CBR_C2MC_TILE_LINADR_SHIFT)
+#define CBR_C2MC_TILE_LINADR_RANGE                      _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CBR_C2MC_TILE_LINADR_ROW                        0
+
+#define CBR_C2MC_TILE_LINADRU_SHIFT                     _MK_SHIFT_CONST(32)
+#define CBR_C2MC_TILE_LINADRU_FIELD                     (_MK_MASK_CONST(0xffffffff) << CBR_C2MC_TILE_LINADRU_SHIFT)
+#define CBR_C2MC_TILE_LINADRU_RANGE                     _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(32)
+#define CBR_C2MC_TILE_LINADRU_ROW                       0
+
+#define CBR_C2MC_TILE_LINADRV_SHIFT                     _MK_SHIFT_CONST(64)
+#define CBR_C2MC_TILE_LINADRV_FIELD                     (_MK_MASK_CONST(0xffffffff) << CBR_C2MC_TILE_LINADRV_SHIFT)
+#define CBR_C2MC_TILE_LINADRV_RANGE                     _MK_SHIFT_CONST(95):_MK_SHIFT_CONST(64)
+#define CBR_C2MC_TILE_LINADRV_ROW                       0
+
+#define CBR_C2MC_TILE_TMODE_SHIFT                       _MK_SHIFT_CONST(96)
+#define CBR_C2MC_TILE_TMODE_FIELD                       (_MK_MASK_CONST(0x1) << CBR_C2MC_TILE_TMODE_SHIFT)
+#define CBR_C2MC_TILE_TMODE_RANGE                       _MK_SHIFT_CONST(96):_MK_SHIFT_CONST(96)
+#define CBR_C2MC_TILE_TMODE_ROW                 0
+#define CBR_C2MC_TILE_TMODE_LINEAR                      _MK_ENUM_CONST(0)
+#define CBR_C2MC_TILE_TMODE_TILED                       _MK_ENUM_CONST(1)
+
+#define CBR_C2MC_TILE_TMODEUV_SHIFT                     _MK_SHIFT_CONST(97)
+#define CBR_C2MC_TILE_TMODEUV_FIELD                     (_MK_MASK_CONST(0x1) << CBR_C2MC_TILE_TMODEUV_SHIFT)
+#define CBR_C2MC_TILE_TMODEUV_RANGE                     _MK_SHIFT_CONST(97):_MK_SHIFT_CONST(97)
+#define CBR_C2MC_TILE_TMODEUV_ROW                       0
+#define CBR_C2MC_TILE_TMODEUV_LINEAR                    _MK_ENUM_CONST(0)
+#define CBR_C2MC_TILE_TMODEUV_TILED                     _MK_ENUM_CONST(1)
+
+
+// Packet CBR_C2MC_RDYP
+#define CBR_C2MC_RDYP_SIZE 1
+
+// fake data
+#define CBR_C2MC_RDYP_RDYP_SHIFT                        _MK_SHIFT_CONST(0)
+#define CBR_C2MC_RDYP_RDYP_FIELD                        (_MK_MASK_CONST(0x1) << CBR_C2MC_RDYP_RDYP_SHIFT)
+#define CBR_C2MC_RDYP_RDYP_RANGE                        _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CBR_C2MC_RDYP_RDYP_ROW                  0
+
+
+// Packet CBR_C2MC_OUTSTD
+#define CBR_C2MC_OUTSTD_SIZE 1
+
+#define CBR_C2MC_OUTSTD_OUTSTD_SHIFT                    _MK_SHIFT_CONST(0)
+#define CBR_C2MC_OUTSTD_OUTSTD_FIELD                    (_MK_MASK_CONST(0x1) << CBR_C2MC_OUTSTD_OUTSTD_SHIFT)
+#define CBR_C2MC_OUTSTD_OUTSTD_RANGE                    _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CBR_C2MC_OUTSTD_OUTSTD_ROW                      0
+
+
+// Packet CBR_C2MC_STOP
+#define CBR_C2MC_STOP_SIZE 1
+
+#define CBR_C2MC_STOP_STOP_SHIFT                        _MK_SHIFT_CONST(0)
+#define CBR_C2MC_STOP_STOP_FIELD                        (_MK_MASK_CONST(0x1) << CBR_C2MC_STOP_STOP_SHIFT)
+#define CBR_C2MC_STOP_STOP_RANGE                        _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CBR_C2MC_STOP_STOP_ROW                  0
+
+
+// Packet CBR_C2MC_RDI
+#define CBR_C2MC_RDI_SIZE 262
+
+#define CBR_C2MC_RDI_RDI_SHIFT                  _MK_SHIFT_CONST(0)
+#define CBR_C2MC_RDI_RDI_FIELD                  (_MK_MASK_CONST(0xffffffff) << CBR_C2MC_RDI_RDI_SHIFT)
+#define CBR_C2MC_RDI_RDI_RANGE                  _MK_SHIFT_CONST(255):_MK_SHIFT_CONST(0)
+#define CBR_C2MC_RDI_RDI_ROW                    0
+
+#define CBR_C2MC_RDI_RDILST_SHIFT                       _MK_SHIFT_CONST(256)
+#define CBR_C2MC_RDI_RDILST_FIELD                       (_MK_MASK_CONST(0x1) << CBR_C2MC_RDI_RDILST_SHIFT)
+#define CBR_C2MC_RDI_RDILST_RANGE                       _MK_SHIFT_CONST(256):_MK_SHIFT_CONST(256)
+#define CBR_C2MC_RDI_RDILST_ROW                 0
+
+#define CBR_C2MC_RDI_RDINB_SHIFT                        _MK_SHIFT_CONST(257)
+#define CBR_C2MC_RDI_RDINB_FIELD                        (_MK_MASK_CONST(0x1f) << CBR_C2MC_RDI_RDINB_SHIFT)
+#define CBR_C2MC_RDI_RDINB_RANGE                        _MK_SHIFT_CONST(261):_MK_SHIFT_CONST(257)
+#define CBR_C2MC_RDI_RDINB_ROW                  0
+
+
+// Packet CBR_C2MC_DOREQ
+#define CBR_C2MC_DOREQ_SIZE 64
+
+#define CBR_C2MC_DOREQ_ADR_SHIFT                        _MK_SHIFT_CONST(0)
+#define CBR_C2MC_DOREQ_ADR_FIELD                        (_MK_MASK_CONST(0xffffffff) << CBR_C2MC_DOREQ_ADR_SHIFT)
+#define CBR_C2MC_DOREQ_ADR_RANGE                        _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CBR_C2MC_DOREQ_ADR_ROW                  0
+
+#define CBR_C2MC_DOREQ_LS_SHIFT                 _MK_SHIFT_CONST(32)
+#define CBR_C2MC_DOREQ_LS_FIELD                 (_MK_MASK_CONST(0xffffffff) << CBR_C2MC_DOREQ_LS_SHIFT)
+#define CBR_C2MC_DOREQ_LS_RANGE                 _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(32)
+#define CBR_C2MC_DOREQ_LS_ROW                   0
+
+
+// Packet CBR_C2MC_HP
+#define CBR_C2MC_HP_SIZE 38
+
+// high-priority threshold
+#define CBR_C2MC_HP_HPTH_SHIFT                  _MK_SHIFT_CONST(0)
+#define CBR_C2MC_HP_HPTH_FIELD                  (_MK_MASK_CONST(0xffffffff) << CBR_C2MC_HP_HPTH_SHIFT)
+#define CBR_C2MC_HP_HPTH_RANGE                  _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CBR_C2MC_HP_HPTH_ROW                    0
+
+// high-priority timer
+#define CBR_C2MC_HP_HPTM_SHIFT                  _MK_SHIFT_CONST(32)
+#define CBR_C2MC_HP_HPTM_FIELD                  (_MK_MASK_CONST(0x3f) << CBR_C2MC_HP_HPTM_SHIFT)
+#define CBR_C2MC_HP_HPTM_RANGE                  _MK_SHIFT_CONST(37):_MK_SHIFT_CONST(32)
+#define CBR_C2MC_HP_HPTM_ROW                    0
+
+
+// Packet CBW_C2MC_RESET
+#define CBW_C2MC_RESET_SIZE 1
+
+#define CBW_C2MC_RESET_RSTN_SHIFT                       _MK_SHIFT_CONST(0)
+#define CBW_C2MC_RESET_RSTN_FIELD                       (_MK_MASK_CONST(0x1) << CBW_C2MC_RESET_RSTN_SHIFT)
+#define CBW_C2MC_RESET_RSTN_RANGE                       _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CBW_C2MC_RESET_RSTN_ROW                 0
+
+
+// Packet CBW_C2MC_REQP
+#define CBW_C2MC_REQP_SIZE 134
+
+#define CBW_C2MC_REQP_ADR_SHIFT                 _MK_SHIFT_CONST(0)
+#define CBW_C2MC_REQP_ADR_FIELD                 (_MK_MASK_CONST(0xffffffff) << CBW_C2MC_REQP_ADR_SHIFT)
+#define CBW_C2MC_REQP_ADR_RANGE                 _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CBW_C2MC_REQP_ADR_ROW                   0
+
+#define CBW_C2MC_REQP_LS_SHIFT                  _MK_SHIFT_CONST(32)
+#define CBW_C2MC_REQP_LS_FIELD                  (_MK_MASK_CONST(0xffffffff) << CBW_C2MC_REQP_LS_SHIFT)
+#define CBW_C2MC_REQP_LS_RANGE                  _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(32)
+#define CBW_C2MC_REQP_LS_ROW                    0
+
+#define CBW_C2MC_REQP_HS_SHIFT                  _MK_SHIFT_CONST(64)
+#define CBW_C2MC_REQP_HS_FIELD                  (_MK_MASK_CONST(0xffffffff) << CBW_C2MC_REQP_HS_SHIFT)
+#define CBW_C2MC_REQP_HS_RANGE                  _MK_SHIFT_CONST(95):_MK_SHIFT_CONST(64)
+#define CBW_C2MC_REQP_HS_ROW                    0
+
+#define CBW_C2MC_REQP_VS_SHIFT                  _MK_SHIFT_CONST(96)
+#define CBW_C2MC_REQP_VS_FIELD                  (_MK_MASK_CONST(0xffffffff) << CBW_C2MC_REQP_VS_SHIFT)
+#define CBW_C2MC_REQP_VS_RANGE                  _MK_SHIFT_CONST(127):_MK_SHIFT_CONST(96)
+#define CBW_C2MC_REQP_VS_ROW                    0
+
+#define CBW_C2MC_REQP_HD_SHIFT                  _MK_SHIFT_CONST(128)
+#define CBW_C2MC_REQP_HD_FIELD                  (_MK_MASK_CONST(0x1) << CBW_C2MC_REQP_HD_SHIFT)
+#define CBW_C2MC_REQP_HD_RANGE                  _MK_SHIFT_CONST(128):_MK_SHIFT_CONST(128)
+#define CBW_C2MC_REQP_HD_ROW                    0
+
+#define CBW_C2MC_REQP_VD_SHIFT                  _MK_SHIFT_CONST(129)
+#define CBW_C2MC_REQP_VD_FIELD                  (_MK_MASK_CONST(0x1) << CBW_C2MC_REQP_VD_SHIFT)
+#define CBW_C2MC_REQP_VD_RANGE                  _MK_SHIFT_CONST(129):_MK_SHIFT_CONST(129)
+#define CBW_C2MC_REQP_VD_ROW                    0
+
+#define CBW_C2MC_REQP_BPP_SHIFT                 _MK_SHIFT_CONST(130)
+#define CBW_C2MC_REQP_BPP_FIELD                 (_MK_MASK_CONST(0x3) << CBW_C2MC_REQP_BPP_SHIFT)
+#define CBW_C2MC_REQP_BPP_RANGE                 _MK_SHIFT_CONST(131):_MK_SHIFT_CONST(130)
+#define CBW_C2MC_REQP_BPP_ROW                   0
+
+#define CBW_C2MC_REQP_XY_SHIFT                  _MK_SHIFT_CONST(132)
+#define CBW_C2MC_REQP_XY_FIELD                  (_MK_MASK_CONST(0x1) << CBW_C2MC_REQP_XY_SHIFT)
+#define CBW_C2MC_REQP_XY_RANGE                  _MK_SHIFT_CONST(132):_MK_SHIFT_CONST(132)
+#define CBW_C2MC_REQP_XY_ROW                    0
+
+#define CBW_C2MC_REQP_PK_SHIFT                  _MK_SHIFT_CONST(133)
+#define CBW_C2MC_REQP_PK_FIELD                  (_MK_MASK_CONST(0x1) << CBW_C2MC_REQP_PK_SHIFT)
+#define CBW_C2MC_REQP_PK_RANGE                  _MK_SHIFT_CONST(133):_MK_SHIFT_CONST(133)
+#define CBW_C2MC_REQP_PK_ROW                    0
+
+
+// Packet CBW_C2MC_ADRXY
+#define CBW_C2MC_ADRXY_SIZE 30
+
+#define CBW_C2MC_ADRXY_OFFX_SHIFT                       _MK_SHIFT_CONST(0)
+#define CBW_C2MC_ADRXY_OFFX_FIELD                       (_MK_MASK_CONST(0xffff) << CBW_C2MC_ADRXY_OFFX_SHIFT)
+#define CBW_C2MC_ADRXY_OFFX_RANGE                       _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(0)
+#define CBW_C2MC_ADRXY_OFFX_ROW                 0
+
+#define CBW_C2MC_ADRXY_OFFY_SHIFT                       _MK_SHIFT_CONST(16)
+#define CBW_C2MC_ADRXY_OFFY_FIELD                       (_MK_MASK_CONST(0x3fff) << CBW_C2MC_ADRXY_OFFY_SHIFT)
+#define CBW_C2MC_ADRXY_OFFY_RANGE                       _MK_SHIFT_CONST(29):_MK_SHIFT_CONST(16)
+#define CBW_C2MC_ADRXY_OFFY_ROW                 0
+
+
+// Packet CBW_C2MC_TILE
+#define CBW_C2MC_TILE_SIZE 33
+
+#define CBW_C2MC_TILE_LINADR_SHIFT                      _MK_SHIFT_CONST(0)
+#define CBW_C2MC_TILE_LINADR_FIELD                      (_MK_MASK_CONST(0xffffffff) << CBW_C2MC_TILE_LINADR_SHIFT)
+#define CBW_C2MC_TILE_LINADR_RANGE                      _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CBW_C2MC_TILE_LINADR_ROW                        0
+
+#define CBW_C2MC_TILE_TMODE_SHIFT                       _MK_SHIFT_CONST(32)
+#define CBW_C2MC_TILE_TMODE_FIELD                       (_MK_MASK_CONST(0x1) << CBW_C2MC_TILE_TMODE_SHIFT)
+#define CBW_C2MC_TILE_TMODE_RANGE                       _MK_SHIFT_CONST(32):_MK_SHIFT_CONST(32)
+#define CBW_C2MC_TILE_TMODE_ROW                 0
+#define CBW_C2MC_TILE_TMODE_LINEAR                      _MK_ENUM_CONST(0)
+#define CBW_C2MC_TILE_TMODE_TILED                       _MK_ENUM_CONST(1)
+
+
+// Packet CBW_C2MC_RDYP
+#define CBW_C2MC_RDYP_SIZE 1
+
+// fake data
+#define CBW_C2MC_RDYP_RDYP_SHIFT                        _MK_SHIFT_CONST(0)
+#define CBW_C2MC_RDYP_RDYP_FIELD                        (_MK_MASK_CONST(0x1) << CBW_C2MC_RDYP_RDYP_SHIFT)
+#define CBW_C2MC_RDYP_RDYP_RANGE                        _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CBW_C2MC_RDYP_RDYP_ROW                  0
+
+
+// Packet CBW_C2MC_STOP
+#define CBW_C2MC_STOP_SIZE 1
+
+#define CBW_C2MC_STOP_STOP_SHIFT                        _MK_SHIFT_CONST(0)
+#define CBW_C2MC_STOP_STOP_FIELD                        (_MK_MASK_CONST(0x1) << CBW_C2MC_STOP_STOP_SHIFT)
+#define CBW_C2MC_STOP_STOP_RANGE                        _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CBW_C2MC_STOP_STOP_ROW                  0
+
+
+// Packet CBW_C2MC_XDI
+#define CBW_C2MC_XDI_SIZE 1
+
+// fake data
+#define CBW_C2MC_XDI_XDI_SHIFT                  _MK_SHIFT_CONST(0)
+#define CBW_C2MC_XDI_XDI_FIELD                  (_MK_MASK_CONST(0x1) << CBW_C2MC_XDI_XDI_SHIFT)
+#define CBW_C2MC_XDI_XDI_RANGE                  _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CBW_C2MC_XDI_XDI_ROW                    0
+
+
+// Packet CBW_C2MC_DOREQ
+#define CBW_C2MC_DOREQ_SIZE 321
+
+#define CBW_C2MC_DOREQ_ADR_SHIFT                        _MK_SHIFT_CONST(0)
+#define CBW_C2MC_DOREQ_ADR_FIELD                        (_MK_MASK_CONST(0xffffffff) << CBW_C2MC_DOREQ_ADR_SHIFT)
+#define CBW_C2MC_DOREQ_ADR_RANGE                        _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CBW_C2MC_DOREQ_ADR_ROW                  0
+
+#define CBW_C2MC_DOREQ_BE_SHIFT                 _MK_SHIFT_CONST(32)
+#define CBW_C2MC_DOREQ_BE_FIELD                 (_MK_MASK_CONST(0xffffffff) << CBW_C2MC_DOREQ_BE_SHIFT)
+#define CBW_C2MC_DOREQ_BE_RANGE                 _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(32)
+#define CBW_C2MC_DOREQ_BE_ROW                   0
+
+#define CBW_C2MC_DOREQ_WDO_SHIFT                        _MK_SHIFT_CONST(64)
+#define CBW_C2MC_DOREQ_WDO_FIELD                        (_MK_MASK_CONST(0xffffffff) << CBW_C2MC_DOREQ_WDO_SHIFT)
+#define CBW_C2MC_DOREQ_WDO_RANGE                        _MK_SHIFT_CONST(319):_MK_SHIFT_CONST(64)
+#define CBW_C2MC_DOREQ_WDO_ROW                  0
+
+#define CBW_C2MC_DOREQ_TAG_SHIFT                        _MK_SHIFT_CONST(320)
+#define CBW_C2MC_DOREQ_TAG_FIELD                        (_MK_MASK_CONST(0x1) << CBW_C2MC_DOREQ_TAG_SHIFT)
+#define CBW_C2MC_DOREQ_TAG_RANGE                        _MK_SHIFT_CONST(320):_MK_SHIFT_CONST(320)
+#define CBW_C2MC_DOREQ_TAG_ROW                  0
+
+
+// Packet CBW_C2MC_HP
+#define CBW_C2MC_HP_SIZE 32
+
+// high-priority threshold
+#define CBW_C2MC_HP_HPTH_SHIFT                  _MK_SHIFT_CONST(0)
+#define CBW_C2MC_HP_HPTH_FIELD                  (_MK_MASK_CONST(0xffffffff) << CBW_C2MC_HP_HPTH_SHIFT)
+#define CBW_C2MC_HP_HPTH_RANGE                  _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CBW_C2MC_HP_HPTH_ROW                    0
+
+
+// Packet CBW_C2MC_WCOAL
+#define CBW_C2MC_WCOAL_SIZE 32
+
+// write-coalescing time-out
+#define CBW_C2MC_WCOAL_WCOALTM_SHIFT                    _MK_SHIFT_CONST(0)
+#define CBW_C2MC_WCOAL_WCOALTM_FIELD                    (_MK_MASK_CONST(0xffffffff) << CBW_C2MC_WCOAL_WCOALTM_SHIFT)
+#define CBW_C2MC_WCOAL_WCOALTM_RANGE                    _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CBW_C2MC_WCOAL_WCOALTM_ROW                      0
+
+
+// Packet CCR_C2MC_RESET
+#define CCR_C2MC_RESET_SIZE 1
+
+#define CCR_C2MC_RESET_RSTN_SHIFT                       _MK_SHIFT_CONST(0)
+#define CCR_C2MC_RESET_RSTN_FIELD                       (_MK_MASK_CONST(0x1) << CCR_C2MC_RESET_RSTN_SHIFT)
+#define CCR_C2MC_RESET_RSTN_RANGE                       _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CCR_C2MC_RESET_RSTN_ROW                 0
+
+
+// Packet CCR_C2MC_REQ
+#define CCR_C2MC_REQ_SIZE 101
+
+#define CCR_C2MC_REQ_ADR_SHIFT                  _MK_SHIFT_CONST(0)
+#define CCR_C2MC_REQ_ADR_FIELD                  (_MK_MASK_CONST(0xffffffff) << CCR_C2MC_REQ_ADR_SHIFT)
+#define CCR_C2MC_REQ_ADR_RANGE                  _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CCR_C2MC_REQ_ADR_ROW                    0
+
+#define CCR_C2MC_REQ_LS_SHIFT                   _MK_SHIFT_CONST(32)
+#define CCR_C2MC_REQ_LS_FIELD                   (_MK_MASK_CONST(0xffffffff) << CCR_C2MC_REQ_LS_SHIFT)
+#define CCR_C2MC_REQ_LS_RANGE                   _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(32)
+#define CCR_C2MC_REQ_LS_ROW                     0
+
+// HI is apparently a reserved keyword
+#define CCR_C2MC_REQ_HINC_SHIFT                 _MK_SHIFT_CONST(64)
+#define CCR_C2MC_REQ_HINC_FIELD                 (_MK_MASK_CONST(0xffffffff) << CCR_C2MC_REQ_HINC_SHIFT)
+#define CCR_C2MC_REQ_HINC_RANGE                 _MK_SHIFT_CONST(95):_MK_SHIFT_CONST(64)
+#define CCR_C2MC_REQ_HINC_ROW                   0
+
+#define CCR_C2MC_REQ_ACMD_SHIFT                 _MK_SHIFT_CONST(96)
+#define CCR_C2MC_REQ_ACMD_FIELD                 (_MK_MASK_CONST(0x3) << CCR_C2MC_REQ_ACMD_SHIFT)
+#define CCR_C2MC_REQ_ACMD_RANGE                 _MK_SHIFT_CONST(97):_MK_SHIFT_CONST(96)
+#define CCR_C2MC_REQ_ACMD_ROW                   0
+
+#define CCR_C2MC_REQ_LN_SHIFT                   _MK_SHIFT_CONST(98)
+#define CCR_C2MC_REQ_LN_FIELD                   (_MK_MASK_CONST(0x1) << CCR_C2MC_REQ_LN_SHIFT)
+#define CCR_C2MC_REQ_LN_RANGE                   _MK_SHIFT_CONST(98):_MK_SHIFT_CONST(98)
+#define CCR_C2MC_REQ_LN_ROW                     0
+
+#define CCR_C2MC_REQ_HD_SHIFT                   _MK_SHIFT_CONST(99)
+#define CCR_C2MC_REQ_HD_FIELD                   (_MK_MASK_CONST(0x1) << CCR_C2MC_REQ_HD_SHIFT)
+#define CCR_C2MC_REQ_HD_RANGE                   _MK_SHIFT_CONST(99):_MK_SHIFT_CONST(99)
+#define CCR_C2MC_REQ_HD_ROW                     0
+
+#define CCR_C2MC_REQ_VD_SHIFT                   _MK_SHIFT_CONST(100)
+#define CCR_C2MC_REQ_VD_FIELD                   (_MK_MASK_CONST(0x1) << CCR_C2MC_REQ_VD_SHIFT)
+#define CCR_C2MC_REQ_VD_RANGE                   _MK_SHIFT_CONST(100):_MK_SHIFT_CONST(100)
+#define CCR_C2MC_REQ_VD_ROW                     0
+
+
+// Packet CCR_C2MC_RDI
+#define CCR_C2MC_RDI_SIZE 256
+
+#define CCR_C2MC_RDI_RDI_SHIFT                  _MK_SHIFT_CONST(0)
+#define CCR_C2MC_RDI_RDI_FIELD                  (_MK_MASK_CONST(0xffffffff) << CCR_C2MC_RDI_RDI_SHIFT)
+#define CCR_C2MC_RDI_RDI_RANGE                  _MK_SHIFT_CONST(255):_MK_SHIFT_CONST(0)
+#define CCR_C2MC_RDI_RDI_ROW                    0
+
+
+// Packet CCR_C2MC_HP
+#define CCR_C2MC_HP_SIZE 38
+
+// high-priority threshold
+#define CCR_C2MC_HP_HPTH_SHIFT                  _MK_SHIFT_CONST(0)
+#define CCR_C2MC_HP_HPTH_FIELD                  (_MK_MASK_CONST(0xffffffff) << CCR_C2MC_HP_HPTH_SHIFT)
+#define CCR_C2MC_HP_HPTH_RANGE                  _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CCR_C2MC_HP_HPTH_ROW                    0
+
+// high-priority timer
+#define CCR_C2MC_HP_HPTM_SHIFT                  _MK_SHIFT_CONST(32)
+#define CCR_C2MC_HP_HPTM_FIELD                  (_MK_MASK_CONST(0x3f) << CCR_C2MC_HP_HPTM_SHIFT)
+#define CCR_C2MC_HP_HPTM_RANGE                  _MK_SHIFT_CONST(37):_MK_SHIFT_CONST(32)
+#define CCR_C2MC_HP_HPTM_ROW                    0
+
+
+// Packet CCW_C2MC_RESET
+#define CCW_C2MC_RESET_SIZE 1
+
+#define CCW_C2MC_RESET_RSTN_SHIFT                       _MK_SHIFT_CONST(0)
+#define CCW_C2MC_RESET_RSTN_FIELD                       (_MK_MASK_CONST(0x1) << CCW_C2MC_RESET_RSTN_SHIFT)
+#define CCW_C2MC_RESET_RSTN_RANGE                       _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CCW_C2MC_RESET_RSTN_ROW                 0
+
+
+// Packet CCW_C2MC_REQ
+#define CCW_C2MC_REQ_SIZE 417
+
+#define CCW_C2MC_REQ_ADR_SHIFT                  _MK_SHIFT_CONST(0)
+#define CCW_C2MC_REQ_ADR_FIELD                  (_MK_MASK_CONST(0xffffffff) << CCW_C2MC_REQ_ADR_SHIFT)
+#define CCW_C2MC_REQ_ADR_RANGE                  _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CCW_C2MC_REQ_ADR_ROW                    0
+
+#define CCW_C2MC_REQ_LS_SHIFT                   _MK_SHIFT_CONST(32)
+#define CCW_C2MC_REQ_LS_FIELD                   (_MK_MASK_CONST(0xffffffff) << CCW_C2MC_REQ_LS_SHIFT)
+#define CCW_C2MC_REQ_LS_RANGE                   _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(32)
+#define CCW_C2MC_REQ_LS_ROW                     0
+
+// HI is apparently a reserved keyword
+#define CCW_C2MC_REQ_HINC_SHIFT                 _MK_SHIFT_CONST(64)
+#define CCW_C2MC_REQ_HINC_FIELD                 (_MK_MASK_CONST(0xffffffff) << CCW_C2MC_REQ_HINC_SHIFT)
+#define CCW_C2MC_REQ_HINC_RANGE                 _MK_SHIFT_CONST(95):_MK_SHIFT_CONST(64)
+#define CCW_C2MC_REQ_HINC_ROW                   0
+
+#define CCW_C2MC_REQ_ACMD_SHIFT                 _MK_SHIFT_CONST(96)
+#define CCW_C2MC_REQ_ACMD_FIELD                 (_MK_MASK_CONST(0x3) << CCW_C2MC_REQ_ACMD_SHIFT)
+#define CCW_C2MC_REQ_ACMD_RANGE                 _MK_SHIFT_CONST(97):_MK_SHIFT_CONST(96)
+#define CCW_C2MC_REQ_ACMD_ROW                   0
+
+#define CCW_C2MC_REQ_LN_SHIFT                   _MK_SHIFT_CONST(98)
+#define CCW_C2MC_REQ_LN_FIELD                   (_MK_MASK_CONST(0x1) << CCW_C2MC_REQ_LN_SHIFT)
+#define CCW_C2MC_REQ_LN_RANGE                   _MK_SHIFT_CONST(98):_MK_SHIFT_CONST(98)
+#define CCW_C2MC_REQ_LN_ROW                     0
+
+#define CCW_C2MC_REQ_HD_SHIFT                   _MK_SHIFT_CONST(99)
+#define CCW_C2MC_REQ_HD_FIELD                   (_MK_MASK_CONST(0x1) << CCW_C2MC_REQ_HD_SHIFT)
+#define CCW_C2MC_REQ_HD_RANGE                   _MK_SHIFT_CONST(99):_MK_SHIFT_CONST(99)
+#define CCW_C2MC_REQ_HD_ROW                     0
+
+#define CCW_C2MC_REQ_VD_SHIFT                   _MK_SHIFT_CONST(100)
+#define CCW_C2MC_REQ_VD_FIELD                   (_MK_MASK_CONST(0x1) << CCW_C2MC_REQ_VD_SHIFT)
+#define CCW_C2MC_REQ_VD_RANGE                   _MK_SHIFT_CONST(100):_MK_SHIFT_CONST(100)
+#define CCW_C2MC_REQ_VD_ROW                     0
+
+#define CCW_C2MC_REQ_BPP_SHIFT                  _MK_SHIFT_CONST(101)
+#define CCW_C2MC_REQ_BPP_FIELD                  (_MK_MASK_CONST(0x3) << CCW_C2MC_REQ_BPP_SHIFT)
+#define CCW_C2MC_REQ_BPP_RANGE                  _MK_SHIFT_CONST(102):_MK_SHIFT_CONST(101)
+#define CCW_C2MC_REQ_BPP_ROW                    0
+
+#define CCW_C2MC_REQ_XY_SHIFT                   _MK_SHIFT_CONST(103)
+#define CCW_C2MC_REQ_XY_FIELD                   (_MK_MASK_CONST(0x1) << CCW_C2MC_REQ_XY_SHIFT)
+#define CCW_C2MC_REQ_XY_RANGE                   _MK_SHIFT_CONST(103):_MK_SHIFT_CONST(103)
+#define CCW_C2MC_REQ_XY_ROW                     0
+
+#define CCW_C2MC_REQ_BE_SHIFT                   _MK_SHIFT_CONST(128)
+#define CCW_C2MC_REQ_BE_FIELD                   (_MK_MASK_CONST(0xffffffff) << CCW_C2MC_REQ_BE_SHIFT)
+#define CCW_C2MC_REQ_BE_RANGE                   _MK_SHIFT_CONST(159):_MK_SHIFT_CONST(128)
+#define CCW_C2MC_REQ_BE_ROW                     0
+
+#define CCW_C2MC_REQ_WDO_SHIFT                  _MK_SHIFT_CONST(160)
+#define CCW_C2MC_REQ_WDO_FIELD                  (_MK_MASK_CONST(0xffffffff) << CCW_C2MC_REQ_WDO_SHIFT)
+#define CCW_C2MC_REQ_WDO_RANGE                  _MK_SHIFT_CONST(415):_MK_SHIFT_CONST(160)
+#define CCW_C2MC_REQ_WDO_ROW                    0
+
+#define CCW_C2MC_REQ_TAG_SHIFT                  _MK_SHIFT_CONST(416)
+#define CCW_C2MC_REQ_TAG_FIELD                  (_MK_MASK_CONST(0x1) << CCW_C2MC_REQ_TAG_SHIFT)
+#define CCW_C2MC_REQ_TAG_RANGE                  _MK_SHIFT_CONST(416):_MK_SHIFT_CONST(416)
+#define CCW_C2MC_REQ_TAG_ROW                    0
+
+
+// Packet CCW_C2MC_ADRXY
+#define CCW_C2MC_ADRXY_SIZE 30
+
+#define CCW_C2MC_ADRXY_OFFX_SHIFT                       _MK_SHIFT_CONST(0)
+#define CCW_C2MC_ADRXY_OFFX_FIELD                       (_MK_MASK_CONST(0xffff) << CCW_C2MC_ADRXY_OFFX_SHIFT)
+#define CCW_C2MC_ADRXY_OFFX_RANGE                       _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(0)
+#define CCW_C2MC_ADRXY_OFFX_ROW                 0
+
+#define CCW_C2MC_ADRXY_OFFY_SHIFT                       _MK_SHIFT_CONST(16)
+#define CCW_C2MC_ADRXY_OFFY_FIELD                       (_MK_MASK_CONST(0x3fff) << CCW_C2MC_ADRXY_OFFY_SHIFT)
+#define CCW_C2MC_ADRXY_OFFY_RANGE                       _MK_SHIFT_CONST(29):_MK_SHIFT_CONST(16)
+#define CCW_C2MC_ADRXY_OFFY_ROW                 0
+
+
+// Packet CCW_C2MC_TILE
+#define CCW_C2MC_TILE_SIZE 33
+
+#define CCW_C2MC_TILE_LINADR_SHIFT                      _MK_SHIFT_CONST(0)
+#define CCW_C2MC_TILE_LINADR_FIELD                      (_MK_MASK_CONST(0xffffffff) << CCW_C2MC_TILE_LINADR_SHIFT)
+#define CCW_C2MC_TILE_LINADR_RANGE                      _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CCW_C2MC_TILE_LINADR_ROW                        0
+
+#define CCW_C2MC_TILE_TMODE_SHIFT                       _MK_SHIFT_CONST(32)
+#define CCW_C2MC_TILE_TMODE_FIELD                       (_MK_MASK_CONST(0x1) << CCW_C2MC_TILE_TMODE_SHIFT)
+#define CCW_C2MC_TILE_TMODE_RANGE                       _MK_SHIFT_CONST(32):_MK_SHIFT_CONST(32)
+#define CCW_C2MC_TILE_TMODE_ROW                 0
+#define CCW_C2MC_TILE_TMODE_LINEAR                      _MK_ENUM_CONST(0)
+#define CCW_C2MC_TILE_TMODE_TILED                       _MK_ENUM_CONST(1)
+
+
+// Packet CCW_C2MC_XDI
+#define CCW_C2MC_XDI_SIZE 1
+
+// fake data
+#define CCW_C2MC_XDI_XDI_SHIFT                  _MK_SHIFT_CONST(0)
+#define CCW_C2MC_XDI_XDI_FIELD                  (_MK_MASK_CONST(0x1) << CCW_C2MC_XDI_XDI_SHIFT)
+#define CCW_C2MC_XDI_XDI_RANGE                  _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CCW_C2MC_XDI_XDI_ROW                    0
+
+
+// Packet CCW_C2MC_HP
+#define CCW_C2MC_HP_SIZE 32
+
+// high-priority threshold
+#define CCW_C2MC_HP_HPTH_SHIFT                  _MK_SHIFT_CONST(0)
+#define CCW_C2MC_HP_HPTH_FIELD                  (_MK_MASK_CONST(0xffffffff) << CCW_C2MC_HP_HPTH_SHIFT)
+#define CCW_C2MC_HP_HPTH_RANGE                  _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CCW_C2MC_HP_HPTH_ROW                    0
+
+
+// Packet CCW_C2MC_WCOAL
+#define CCW_C2MC_WCOAL_SIZE 32
+
+// write-coalescing time-out
+#define CCW_C2MC_WCOAL_WCOALTM_SHIFT                    _MK_SHIFT_CONST(0)
+#define CCW_C2MC_WCOAL_WCOALTM_FIELD                    (_MK_MASK_CONST(0xffffffff) << CCW_C2MC_WCOAL_WCOALTM_SHIFT)
+#define CCW_C2MC_WCOAL_WCOALTM_RANGE                    _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CCW_C2MC_WCOAL_WCOALTM_ROW                      0
+
+
+// Packet SC_MCCIF_ASYNC
+#define SC_MCCIF_ASYNC_SIZE 4
+
+#define SC_MCCIF_ASYNC_RDCL_RDFAST_SHIFT                        _MK_SHIFT_CONST(0)
+#define SC_MCCIF_ASYNC_RDCL_RDFAST_FIELD                        (_MK_MASK_CONST(0x1) << SC_MCCIF_ASYNC_RDCL_RDFAST_SHIFT)
+#define SC_MCCIF_ASYNC_RDCL_RDFAST_RANGE                        _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define SC_MCCIF_ASYNC_RDCL_RDFAST_ROW                  0
+
+#define SC_MCCIF_ASYNC_RDMC_RDFAST_SHIFT                        _MK_SHIFT_CONST(1)
+#define SC_MCCIF_ASYNC_RDMC_RDFAST_FIELD                        (_MK_MASK_CONST(0x1) << SC_MCCIF_ASYNC_RDMC_RDFAST_SHIFT)
+#define SC_MCCIF_ASYNC_RDMC_RDFAST_RANGE                        _MK_SHIFT_CONST(1):_MK_SHIFT_CONST(1)
+#define SC_MCCIF_ASYNC_RDMC_RDFAST_ROW                  0
+
+#define SC_MCCIF_ASYNC_WRCL_MCLE2X_SHIFT                        _MK_SHIFT_CONST(2)
+#define SC_MCCIF_ASYNC_WRCL_MCLE2X_FIELD                        (_MK_MASK_CONST(0x1) << SC_MCCIF_ASYNC_WRCL_MCLE2X_SHIFT)
+#define SC_MCCIF_ASYNC_WRCL_MCLE2X_RANGE                        _MK_SHIFT_CONST(2):_MK_SHIFT_CONST(2)
+#define SC_MCCIF_ASYNC_WRCL_MCLE2X_ROW                  0
+
+#define SC_MCCIF_ASYNC_WRMC_CLLE2X_SHIFT                        _MK_SHIFT_CONST(3)
+#define SC_MCCIF_ASYNC_WRMC_CLLE2X_FIELD                        (_MK_MASK_CONST(0x1) << SC_MCCIF_ASYNC_WRMC_CLLE2X_SHIFT)
+#define SC_MCCIF_ASYNC_WRMC_CLLE2X_RANGE                        _MK_SHIFT_CONST(3):_MK_SHIFT_CONST(3)
+#define SC_MCCIF_ASYNC_WRMC_CLLE2X_ROW                  0
+
+
+// Register EMC_LL_ARB_CONFIG_0  // LOW-LATENCY arbiter configuration
+#define EMC_LL_ARB_CONFIG_0                     _MK_ADDR_CONST(0xa4)
+#define EMC_LL_ARB_CONFIG_0_WORD_COUNT                  0x1
+#define EMC_LL_ARB_CONFIG_0_RESET_VAL                   _MK_MASK_CONST(0x2003)
+#define EMC_LL_ARB_CONFIG_0_RESET_MASK                  _MK_MASK_CONST(0x8000f10f)
+#define EMC_LL_ARB_CONFIG_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define EMC_LL_ARB_CONFIG_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EMC_LL_ARB_CONFIG_0_READ_MASK                   _MK_MASK_CONST(0x8000f10f)
+#define EMC_LL_ARB_CONFIG_0_WRITE_MASK                  _MK_MASK_CONST(0x8000f10f)
+#define EMC_LL_ARB_CONFIG_0_DIE_OFF_EXP_SHIFT                   _MK_SHIFT_CONST(0)
+#define EMC_LL_ARB_CONFIG_0_DIE_OFF_EXP_FIELD                   (_MK_MASK_CONST(0xf) << EMC_LL_ARB_CONFIG_0_DIE_OFF_EXP_SHIFT)
+#define EMC_LL_ARB_CONFIG_0_DIE_OFF_EXP_RANGE                   3:0
+#define EMC_LL_ARB_CONFIG_0_DIE_OFF_EXP_WOFFSET                 0x0
+#define EMC_LL_ARB_CONFIG_0_DIE_OFF_EXP_DEFAULT                 _MK_MASK_CONST(0x3)
+#define EMC_LL_ARB_CONFIG_0_DIE_OFF_EXP_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define EMC_LL_ARB_CONFIG_0_DIE_OFF_EXP_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_LL_ARB_CONFIG_0_DIE_OFF_EXP_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define EMC_LL_ARB_CONFIG_0_ALLOW_IDLE_INSERT_SHIFT                     _MK_SHIFT_CONST(8)
+#define EMC_LL_ARB_CONFIG_0_ALLOW_IDLE_INSERT_FIELD                     (_MK_MASK_CONST(0x1) << EMC_LL_ARB_CONFIG_0_ALLOW_IDLE_INSERT_SHIFT)
+#define EMC_LL_ARB_CONFIG_0_ALLOW_IDLE_INSERT_RANGE                     8:8
+#define EMC_LL_ARB_CONFIG_0_ALLOW_IDLE_INSERT_WOFFSET                   0x0
+#define EMC_LL_ARB_CONFIG_0_ALLOW_IDLE_INSERT_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_LL_ARB_CONFIG_0_ALLOW_IDLE_INSERT_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define EMC_LL_ARB_CONFIG_0_ALLOW_IDLE_INSERT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_LL_ARB_CONFIG_0_ALLOW_IDLE_INSERT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_LL_ARB_CONFIG_0_ALLOW_IDLE_INSERT_INIT_ENUM                 DISABLED
+#define EMC_LL_ARB_CONFIG_0_ALLOW_IDLE_INSERT_DISABLED                  _MK_ENUM_CONST(0)
+#define EMC_LL_ARB_CONFIG_0_ALLOW_IDLE_INSERT_ENABLED                   _MK_ENUM_CONST(1)
+
+#define EMC_LL_ARB_CONFIG_0_MAX_LL_GREED_SHIFT                  _MK_SHIFT_CONST(12)
+#define EMC_LL_ARB_CONFIG_0_MAX_LL_GREED_FIELD                  (_MK_MASK_CONST(0xf) << EMC_LL_ARB_CONFIG_0_MAX_LL_GREED_SHIFT)
+#define EMC_LL_ARB_CONFIG_0_MAX_LL_GREED_RANGE                  15:12
+#define EMC_LL_ARB_CONFIG_0_MAX_LL_GREED_WOFFSET                        0x0
+#define EMC_LL_ARB_CONFIG_0_MAX_LL_GREED_DEFAULT                        _MK_MASK_CONST(0x2)
+#define EMC_LL_ARB_CONFIG_0_MAX_LL_GREED_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
+#define EMC_LL_ARB_CONFIG_0_MAX_LL_GREED_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_LL_ARB_CONFIG_0_MAX_LL_GREED_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define EMC_LL_ARB_CONFIG_0_LL_RETRSV_ENABLE_SHIFT                      _MK_SHIFT_CONST(31)
+#define EMC_LL_ARB_CONFIG_0_LL_RETRSV_ENABLE_FIELD                      (_MK_MASK_CONST(0x1) << EMC_LL_ARB_CONFIG_0_LL_RETRSV_ENABLE_SHIFT)
+#define EMC_LL_ARB_CONFIG_0_LL_RETRSV_ENABLE_RANGE                      31:31
+#define EMC_LL_ARB_CONFIG_0_LL_RETRSV_ENABLE_WOFFSET                    0x0
+#define EMC_LL_ARB_CONFIG_0_LL_RETRSV_ENABLE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_LL_ARB_CONFIG_0_LL_RETRSV_ENABLE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define EMC_LL_ARB_CONFIG_0_LL_RETRSV_ENABLE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_LL_ARB_CONFIG_0_LL_RETRSV_ENABLE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_LL_ARB_CONFIG_0_LL_RETRSV_ENABLE_INIT_ENUM                  DISABLED
+#define EMC_LL_ARB_CONFIG_0_LL_RETRSV_ENABLE_DISABLED                   _MK_ENUM_CONST(0)
+#define EMC_LL_ARB_CONFIG_0_LL_RETRSV_ENABLE_ENABLED                    _MK_ENUM_CONST(1)
+
+
+// Register EMC_T_MIN_CRITICAL_HP_0  
+#define EMC_T_MIN_CRITICAL_HP_0                 _MK_ADDR_CONST(0xa8)
+#define EMC_T_MIN_CRITICAL_HP_0_WORD_COUNT                      0x1
+#define EMC_T_MIN_CRITICAL_HP_0_RESET_VAL                       _MK_MASK_CONST(0xa080600)
+#define EMC_T_MIN_CRITICAL_HP_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EMC_T_MIN_CRITICAL_HP_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EMC_T_MIN_CRITICAL_HP_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_T_MIN_CRITICAL_HP_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EMC_T_MIN_CRITICAL_HP_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_0_SHIFT                   _MK_SHIFT_CONST(0)
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_0_FIELD                   (_MK_MASK_CONST(0xff) << EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_0_SHIFT)
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_0_RANGE                   7:0
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_0_WOFFSET                 0x0
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_0_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_1_SHIFT                   _MK_SHIFT_CONST(8)
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_1_FIELD                   (_MK_MASK_CONST(0xff) << EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_1_SHIFT)
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_1_RANGE                   15:8
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_1_WOFFSET                 0x0
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_1_DEFAULT                 _MK_MASK_CONST(0x6)
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_1_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_2_SHIFT                   _MK_SHIFT_CONST(16)
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_2_FIELD                   (_MK_MASK_CONST(0xff) << EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_2_SHIFT)
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_2_RANGE                   23:16
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_2_WOFFSET                 0x0
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_2_DEFAULT                 _MK_MASK_CONST(0x8)
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_2_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_3_SHIFT                   _MK_SHIFT_CONST(24)
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_3_FIELD                   (_MK_MASK_CONST(0xff) << EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_3_SHIFT)
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_3_RANGE                   31:24
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_3_WOFFSET                 0x0
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_3_DEFAULT                 _MK_MASK_CONST(0xa)
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_3_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_3_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_3_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register EMC_T_MIN_CRITICAL_TIMEOUT_0  
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0                    _MK_ADDR_CONST(0xac)
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_WORD_COUNT                         0x1
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_RESET_VAL                  _MK_MASK_CONST(0xa080600)
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_0_SHIFT                 _MK_SHIFT_CONST(0)
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_0_FIELD                 (_MK_MASK_CONST(0xff) << EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_0_SHIFT)
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_0_RANGE                 7:0
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_0_WOFFSET                       0x0
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_0_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_0_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_1_SHIFT                 _MK_SHIFT_CONST(8)
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_1_FIELD                 (_MK_MASK_CONST(0xff) << EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_1_SHIFT)
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_1_RANGE                 15:8
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_1_WOFFSET                       0x0
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_1_DEFAULT                       _MK_MASK_CONST(0x6)
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_1_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_2_SHIFT                 _MK_SHIFT_CONST(16)
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_2_FIELD                 (_MK_MASK_CONST(0xff) << EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_2_SHIFT)
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_2_RANGE                 23:16
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_2_WOFFSET                       0x0
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_2_DEFAULT                       _MK_MASK_CONST(0x8)
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_2_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_3_SHIFT                 _MK_SHIFT_CONST(24)
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_3_FIELD                 (_MK_MASK_CONST(0xff) << EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_3_SHIFT)
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_3_RANGE                 31:24
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_3_WOFFSET                       0x0
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_3_DEFAULT                       _MK_MASK_CONST(0xa)
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_3_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EMC_T_MIN_LOAD_0  
+#define EMC_T_MIN_LOAD_0                        _MK_ADDR_CONST(0xb0)
+#define EMC_T_MIN_LOAD_0_WORD_COUNT                     0x1
+#define EMC_T_MIN_LOAD_0_RESET_VAL                      _MK_MASK_CONST(0x8040200)
+#define EMC_T_MIN_LOAD_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
+#define EMC_T_MIN_LOAD_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define EMC_T_MIN_LOAD_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_T_MIN_LOAD_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EMC_T_MIN_LOAD_0_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_0_SHIFT                     _MK_SHIFT_CONST(0)
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_0_FIELD                     (_MK_MASK_CONST(0xff) << EMC_T_MIN_LOAD_0_T_MIN_LOAD_0_SHIFT)
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_0_RANGE                     7:0
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_0_WOFFSET                   0x0
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_0_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_0_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_1_SHIFT                     _MK_SHIFT_CONST(8)
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_1_FIELD                     (_MK_MASK_CONST(0xff) << EMC_T_MIN_LOAD_0_T_MIN_LOAD_1_SHIFT)
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_1_RANGE                     15:8
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_1_WOFFSET                   0x0
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_1_DEFAULT                   _MK_MASK_CONST(0x2)
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_1_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_2_SHIFT                     _MK_SHIFT_CONST(16)
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_2_FIELD                     (_MK_MASK_CONST(0xff) << EMC_T_MIN_LOAD_0_T_MIN_LOAD_2_SHIFT)
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_2_RANGE                     23:16
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_2_WOFFSET                   0x0
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_2_DEFAULT                   _MK_MASK_CONST(0x4)
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_2_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_3_SHIFT                     _MK_SHIFT_CONST(24)
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_3_FIELD                     (_MK_MASK_CONST(0xff) << EMC_T_MIN_LOAD_0_T_MIN_LOAD_3_SHIFT)
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_3_RANGE                     31:24
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_3_WOFFSET                   0x0
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_3_DEFAULT                   _MK_MASK_CONST(0x8)
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_3_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_3_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_3_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EMC_T_MAX_CRITICAL_HP_0  
+#define EMC_T_MAX_CRITICAL_HP_0                 _MK_ADDR_CONST(0xb4)
+#define EMC_T_MAX_CRITICAL_HP_0_WORD_COUNT                      0x1
+#define EMC_T_MAX_CRITICAL_HP_0_RESET_VAL                       _MK_MASK_CONST(0xb0a0901)
+#define EMC_T_MAX_CRITICAL_HP_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EMC_T_MAX_CRITICAL_HP_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EMC_T_MAX_CRITICAL_HP_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_T_MAX_CRITICAL_HP_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EMC_T_MAX_CRITICAL_HP_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_0_SHIFT                   _MK_SHIFT_CONST(0)
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_0_FIELD                   (_MK_MASK_CONST(0xff) << EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_0_SHIFT)
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_0_RANGE                   7:0
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_0_WOFFSET                 0x0
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_0_DEFAULT                 _MK_MASK_CONST(0x1)
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_0_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_1_SHIFT                   _MK_SHIFT_CONST(8)
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_1_FIELD                   (_MK_MASK_CONST(0xff) << EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_1_SHIFT)
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_1_RANGE                   15:8
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_1_WOFFSET                 0x0
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_1_DEFAULT                 _MK_MASK_CONST(0x9)
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_1_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_2_SHIFT                   _MK_SHIFT_CONST(16)
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_2_FIELD                   (_MK_MASK_CONST(0xff) << EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_2_SHIFT)
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_2_RANGE                   23:16
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_2_WOFFSET                 0x0
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_2_DEFAULT                 _MK_MASK_CONST(0xa)
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_2_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_3_SHIFT                   _MK_SHIFT_CONST(24)
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_3_FIELD                   (_MK_MASK_CONST(0xff) << EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_3_SHIFT)
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_3_RANGE                   31:24
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_3_WOFFSET                 0x0
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_3_DEFAULT                 _MK_MASK_CONST(0xb)
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_3_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_3_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_3_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register EMC_T_MAX_CRITICAL_TIMEOUT_0  
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0                    _MK_ADDR_CONST(0xb8)
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_WORD_COUNT                         0x1
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_RESET_VAL                  _MK_MASK_CONST(0xb0a0901)
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_0_SHIFT                 _MK_SHIFT_CONST(0)
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_0_FIELD                 (_MK_MASK_CONST(0xff) << EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_0_SHIFT)
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_0_RANGE                 7:0
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_0_WOFFSET                       0x0
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_0_DEFAULT                       _MK_MASK_CONST(0x1)
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_0_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_1_SHIFT                 _MK_SHIFT_CONST(8)
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_1_FIELD                 (_MK_MASK_CONST(0xff) << EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_1_SHIFT)
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_1_RANGE                 15:8
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_1_WOFFSET                       0x0
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_1_DEFAULT                       _MK_MASK_CONST(0x9)
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_1_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_2_SHIFT                 _MK_SHIFT_CONST(16)
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_2_FIELD                 (_MK_MASK_CONST(0xff) << EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_2_SHIFT)
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_2_RANGE                 23:16
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_2_WOFFSET                       0x0
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_2_DEFAULT                       _MK_MASK_CONST(0xa)
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_2_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_3_SHIFT                 _MK_SHIFT_CONST(24)
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_3_FIELD                 (_MK_MASK_CONST(0xff) << EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_3_SHIFT)
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_3_RANGE                 31:24
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_3_WOFFSET                       0x0
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_3_DEFAULT                       _MK_MASK_CONST(0xb)
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_3_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EMC_T_MAX_LOAD_0  
+#define EMC_T_MAX_LOAD_0                        _MK_ADDR_CONST(0xbc)
+#define EMC_T_MAX_LOAD_0_WORD_COUNT                     0x1
+#define EMC_T_MAX_LOAD_0_RESET_VAL                      _MK_MASK_CONST(0xf080402)
+#define EMC_T_MAX_LOAD_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
+#define EMC_T_MAX_LOAD_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define EMC_T_MAX_LOAD_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_T_MAX_LOAD_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EMC_T_MAX_LOAD_0_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_0_SHIFT                     _MK_SHIFT_CONST(0)
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_0_FIELD                     (_MK_MASK_CONST(0xff) << EMC_T_MAX_LOAD_0_T_MAX_LOAD_0_SHIFT)
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_0_RANGE                     7:0
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_0_WOFFSET                   0x0
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_0_DEFAULT                   _MK_MASK_CONST(0x2)
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_0_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_1_SHIFT                     _MK_SHIFT_CONST(8)
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_1_FIELD                     (_MK_MASK_CONST(0xff) << EMC_T_MAX_LOAD_0_T_MAX_LOAD_1_SHIFT)
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_1_RANGE                     15:8
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_1_WOFFSET                   0x0
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_1_DEFAULT                   _MK_MASK_CONST(0x4)
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_1_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_2_SHIFT                     _MK_SHIFT_CONST(16)
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_2_FIELD                     (_MK_MASK_CONST(0xff) << EMC_T_MAX_LOAD_0_T_MAX_LOAD_2_SHIFT)
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_2_RANGE                     23:16
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_2_WOFFSET                   0x0
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_2_DEFAULT                   _MK_MASK_CONST(0x8)
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_2_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_3_SHIFT                     _MK_SHIFT_CONST(24)
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_3_FIELD                     (_MK_MASK_CONST(0xff) << EMC_T_MAX_LOAD_0_T_MAX_LOAD_3_SHIFT)
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_3_RANGE                     31:24
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_3_WOFFSET                   0x0
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_3_DEFAULT                   _MK_MASK_CONST(0xf)
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_3_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_3_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_3_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EMC_STAT_CONTROL_0  
+#define EMC_STAT_CONTROL_0                      _MK_ADDR_CONST(0xc0)
+#define EMC_STAT_CONTROL_0_WORD_COUNT                   0x1
+#define EMC_STAT_CONTROL_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_CONTROL_0_RESET_MASK                   _MK_MASK_CONST(0x307)
+#define EMC_STAT_CONTROL_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_CONTROL_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_CONTROL_0_READ_MASK                    _MK_MASK_CONST(0x307)
+#define EMC_STAT_CONTROL_0_WRITE_MASK                   _MK_MASK_CONST(0x307)
+#define EMC_STAT_CONTROL_0_LLMC_GATHER_SHIFT                    _MK_SHIFT_CONST(0)
+#define EMC_STAT_CONTROL_0_LLMC_GATHER_FIELD                    (_MK_MASK_CONST(0x7) << EMC_STAT_CONTROL_0_LLMC_GATHER_SHIFT)
+#define EMC_STAT_CONTROL_0_LLMC_GATHER_RANGE                    2:0
+#define EMC_STAT_CONTROL_0_LLMC_GATHER_WOFFSET                  0x0
+#define EMC_STAT_CONTROL_0_LLMC_GATHER_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_CONTROL_0_LLMC_GATHER_DEFAULT_MASK                     _MK_MASK_CONST(0x7)
+#define EMC_STAT_CONTROL_0_LLMC_GATHER_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_CONTROL_0_LLMC_GATHER_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_CONTROL_0_LLMC_GATHER_INIT_ENUM                        RST
+#define EMC_STAT_CONTROL_0_LLMC_GATHER_RST                      _MK_ENUM_CONST(0)
+#define EMC_STAT_CONTROL_0_LLMC_GATHER_CLEAR                    _MK_ENUM_CONST(1)
+#define EMC_STAT_CONTROL_0_LLMC_GATHER_DISABLE                  _MK_ENUM_CONST(2)
+#define EMC_STAT_CONTROL_0_LLMC_GATHER_ENABLE                   _MK_ENUM_CONST(3)
+#define EMC_STAT_CONTROL_0_LLMC_GATHER_SLAVE_TO_MC                      _MK_ENUM_CONST(4)
+
+#define EMC_STAT_CONTROL_0_PWR_GATHER_SHIFT                     _MK_SHIFT_CONST(8)
+#define EMC_STAT_CONTROL_0_PWR_GATHER_FIELD                     (_MK_MASK_CONST(0x3) << EMC_STAT_CONTROL_0_PWR_GATHER_SHIFT)
+#define EMC_STAT_CONTROL_0_PWR_GATHER_RANGE                     9:8
+#define EMC_STAT_CONTROL_0_PWR_GATHER_WOFFSET                   0x0
+#define EMC_STAT_CONTROL_0_PWR_GATHER_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_STAT_CONTROL_0_PWR_GATHER_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define EMC_STAT_CONTROL_0_PWR_GATHER_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_STAT_CONTROL_0_PWR_GATHER_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_STAT_CONTROL_0_PWR_GATHER_INIT_ENUM                 RST
+#define EMC_STAT_CONTROL_0_PWR_GATHER_RST                       _MK_ENUM_CONST(0)
+#define EMC_STAT_CONTROL_0_PWR_GATHER_CLEAR                     _MK_ENUM_CONST(1)
+#define EMC_STAT_CONTROL_0_PWR_GATHER_DISABLE                   _MK_ENUM_CONST(2)
+#define EMC_STAT_CONTROL_0_PWR_GATHER_ENABLE                    _MK_ENUM_CONST(3)
+
+
+// Register EMC_STAT_STATUS_0  
+#define EMC_STAT_STATUS_0                       _MK_ADDR_CONST(0xc4)
+#define EMC_STAT_STATUS_0_WORD_COUNT                    0x1
+#define EMC_STAT_STATUS_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_STATUS_0_RESET_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_STATUS_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define EMC_STAT_STATUS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_STATUS_0_READ_MASK                     _MK_MASK_CONST(0x101)
+#define EMC_STAT_STATUS_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_STATUS_0_LLMC_LIMIT_SHIFT                      _MK_SHIFT_CONST(0)
+#define EMC_STAT_STATUS_0_LLMC_LIMIT_FIELD                      (_MK_MASK_CONST(0x1) << EMC_STAT_STATUS_0_LLMC_LIMIT_SHIFT)
+#define EMC_STAT_STATUS_0_LLMC_LIMIT_RANGE                      0:0
+#define EMC_STAT_STATUS_0_LLMC_LIMIT_WOFFSET                    0x0
+#define EMC_STAT_STATUS_0_LLMC_LIMIT_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_STATUS_0_LLMC_LIMIT_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_STATUS_0_LLMC_LIMIT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_STAT_STATUS_0_LLMC_LIMIT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define EMC_STAT_STATUS_0_PWR_LIMIT_SHIFT                       _MK_SHIFT_CONST(8)
+#define EMC_STAT_STATUS_0_PWR_LIMIT_FIELD                       (_MK_MASK_CONST(0x1) << EMC_STAT_STATUS_0_PWR_LIMIT_SHIFT)
+#define EMC_STAT_STATUS_0_PWR_LIMIT_RANGE                       8:8
+#define EMC_STAT_STATUS_0_PWR_LIMIT_WOFFSET                     0x0
+#define EMC_STAT_STATUS_0_PWR_LIMIT_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_STATUS_0_PWR_LIMIT_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_STAT_STATUS_0_PWR_LIMIT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_STATUS_0_PWR_LIMIT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register EMC_STAT_LLMC_ADDR_LOW_0  
+#define EMC_STAT_LLMC_ADDR_LOW_0                        _MK_ADDR_CONST(0xc8)
+#define EMC_STAT_LLMC_ADDR_LOW_0_WORD_COUNT                     0x1
+#define EMC_STAT_LLMC_ADDR_LOW_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_ADDR_LOW_0_RESET_MASK                     _MK_MASK_CONST(0x3ffffff0)
+#define EMC_STAT_LLMC_ADDR_LOW_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_ADDR_LOW_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_ADDR_LOW_0_READ_MASK                      _MK_MASK_CONST(0x3ffffff0)
+#define EMC_STAT_LLMC_ADDR_LOW_0_WRITE_MASK                     _MK_MASK_CONST(0x3ffffff0)
+#define EMC_STAT_LLMC_ADDR_LOW_0_LLMC_ADDR_LOW_SHIFT                    _MK_SHIFT_CONST(4)
+#define EMC_STAT_LLMC_ADDR_LOW_0_LLMC_ADDR_LOW_FIELD                    (_MK_MASK_CONST(0x3ffffff) << EMC_STAT_LLMC_ADDR_LOW_0_LLMC_ADDR_LOW_SHIFT)
+#define EMC_STAT_LLMC_ADDR_LOW_0_LLMC_ADDR_LOW_RANGE                    29:4
+#define EMC_STAT_LLMC_ADDR_LOW_0_LLMC_ADDR_LOW_WOFFSET                  0x0
+#define EMC_STAT_LLMC_ADDR_LOW_0_LLMC_ADDR_LOW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_ADDR_LOW_0_LLMC_ADDR_LOW_DEFAULT_MASK                     _MK_MASK_CONST(0x3ffffff)
+#define EMC_STAT_LLMC_ADDR_LOW_0_LLMC_ADDR_LOW_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_ADDR_LOW_0_LLMC_ADDR_LOW_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register EMC_STAT_LLMC_ADDR_HIGH_0  
+#define EMC_STAT_LLMC_ADDR_HIGH_0                       _MK_ADDR_CONST(0xcc)
+#define EMC_STAT_LLMC_ADDR_HIGH_0_WORD_COUNT                    0x1
+#define EMC_STAT_LLMC_ADDR_HIGH_0_RESET_VAL                     _MK_MASK_CONST(0x3ffffff0)
+#define EMC_STAT_LLMC_ADDR_HIGH_0_RESET_MASK                    _MK_MASK_CONST(0x3ffffff0)
+#define EMC_STAT_LLMC_ADDR_HIGH_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_ADDR_HIGH_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_ADDR_HIGH_0_READ_MASK                     _MK_MASK_CONST(0x3ffffff0)
+#define EMC_STAT_LLMC_ADDR_HIGH_0_WRITE_MASK                    _MK_MASK_CONST(0x3ffffff0)
+#define EMC_STAT_LLMC_ADDR_HIGH_0_LLMC_ADDR_HIGH_SHIFT                  _MK_SHIFT_CONST(4)
+#define EMC_STAT_LLMC_ADDR_HIGH_0_LLMC_ADDR_HIGH_FIELD                  (_MK_MASK_CONST(0x3ffffff) << EMC_STAT_LLMC_ADDR_HIGH_0_LLMC_ADDR_HIGH_SHIFT)
+#define EMC_STAT_LLMC_ADDR_HIGH_0_LLMC_ADDR_HIGH_RANGE                  29:4
+#define EMC_STAT_LLMC_ADDR_HIGH_0_LLMC_ADDR_HIGH_WOFFSET                        0x0
+#define EMC_STAT_LLMC_ADDR_HIGH_0_LLMC_ADDR_HIGH_DEFAULT                        _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_LLMC_ADDR_HIGH_0_LLMC_ADDR_HIGH_DEFAULT_MASK                   _MK_MASK_CONST(0x3ffffff)
+#define EMC_STAT_LLMC_ADDR_HIGH_0_LLMC_ADDR_HIGH_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_ADDR_HIGH_0_LLMC_ADDR_HIGH_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_ADDR_HIGH_0_LLMC_ADDR_HIGH_INIT_ENUM                      -1
+
+
+// Register EMC_STAT_LLMC_CLOCK_LIMIT_0  
+#define EMC_STAT_LLMC_CLOCK_LIMIT_0                     _MK_ADDR_CONST(0xd0)
+#define EMC_STAT_LLMC_CLOCK_LIMIT_0_WORD_COUNT                  0x1
+#define EMC_STAT_LLMC_CLOCK_LIMIT_0_RESET_VAL                   _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_LLMC_CLOCK_LIMIT_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_LLMC_CLOCK_LIMIT_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_CLOCK_LIMIT_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_CLOCK_LIMIT_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_LLMC_CLOCK_LIMIT_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_LLMC_CLOCK_LIMIT_0_LLMC_CLOCK_LIMIT_SHIFT                      _MK_SHIFT_CONST(0)
+#define EMC_STAT_LLMC_CLOCK_LIMIT_0_LLMC_CLOCK_LIMIT_FIELD                      (_MK_MASK_CONST(0xffffffff) << EMC_STAT_LLMC_CLOCK_LIMIT_0_LLMC_CLOCK_LIMIT_SHIFT)
+#define EMC_STAT_LLMC_CLOCK_LIMIT_0_LLMC_CLOCK_LIMIT_RANGE                      31:0
+#define EMC_STAT_LLMC_CLOCK_LIMIT_0_LLMC_CLOCK_LIMIT_WOFFSET                    0x0
+#define EMC_STAT_LLMC_CLOCK_LIMIT_0_LLMC_CLOCK_LIMIT_DEFAULT                    _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_LLMC_CLOCK_LIMIT_0_LLMC_CLOCK_LIMIT_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_LLMC_CLOCK_LIMIT_0_LLMC_CLOCK_LIMIT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_CLOCK_LIMIT_0_LLMC_CLOCK_LIMIT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_CLOCK_LIMIT_0_LLMC_CLOCK_LIMIT_INIT_ENUM                  -1
+
+
+// Register EMC_STAT_LLMC_CLOCKS_0  
+#define EMC_STAT_LLMC_CLOCKS_0                  _MK_ADDR_CONST(0xd4)
+#define EMC_STAT_LLMC_CLOCKS_0_WORD_COUNT                       0x1
+#define EMC_STAT_LLMC_CLOCKS_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_CLOCKS_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_CLOCKS_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_CLOCKS_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_CLOCKS_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_LLMC_CLOCKS_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_CLOCKS_0_LLMC_CLOCKS_SHIFT                        _MK_SHIFT_CONST(0)
+#define EMC_STAT_LLMC_CLOCKS_0_LLMC_CLOCKS_FIELD                        (_MK_MASK_CONST(0xffffffff) << EMC_STAT_LLMC_CLOCKS_0_LLMC_CLOCKS_SHIFT)
+#define EMC_STAT_LLMC_CLOCKS_0_LLMC_CLOCKS_RANGE                        31:0
+#define EMC_STAT_LLMC_CLOCKS_0_LLMC_CLOCKS_WOFFSET                      0x0
+#define EMC_STAT_LLMC_CLOCKS_0_LLMC_CLOCKS_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_CLOCKS_0_LLMC_CLOCKS_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_CLOCKS_0_LLMC_CLOCKS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_CLOCKS_0_LLMC_CLOCKS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Packet AREMC_STAT_CONTROL
+#define AREMC_STAT_CONTROL_SIZE 28
+
+#define AREMC_STAT_CONTROL_MODE_SHIFT                   _MK_SHIFT_CONST(0)
+#define AREMC_STAT_CONTROL_MODE_FIELD                   (_MK_MASK_CONST(0x3) << AREMC_STAT_CONTROL_MODE_SHIFT)
+#define AREMC_STAT_CONTROL_MODE_RANGE                   _MK_SHIFT_CONST(1):_MK_SHIFT_CONST(0)
+#define AREMC_STAT_CONTROL_MODE_ROW                     0
+#define AREMC_STAT_CONTROL_MODE_BANDWIDTH                       _MK_ENUM_CONST(0)
+#define AREMC_STAT_CONTROL_MODE_LATENCY_AVG                     _MK_ENUM_CONST(1)
+#define AREMC_STAT_CONTROL_MODE_LATENCY_HISTO                   _MK_ENUM_CONST(2)
+
+#define AREMC_STAT_CONTROL_SKIP_SHIFT                   _MK_SHIFT_CONST(4)
+#define AREMC_STAT_CONTROL_SKIP_FIELD                   (_MK_MASK_CONST(0x7) << AREMC_STAT_CONTROL_SKIP_SHIFT)
+#define AREMC_STAT_CONTROL_SKIP_RANGE                   _MK_SHIFT_CONST(6):_MK_SHIFT_CONST(4)
+#define AREMC_STAT_CONTROL_SKIP_ROW                     0
+
+#define AREMC_STAT_CONTROL_CLIENT_TYPE_SHIFT                    _MK_SHIFT_CONST(8)
+#define AREMC_STAT_CONTROL_CLIENT_TYPE_FIELD                    (_MK_MASK_CONST(0x1) << AREMC_STAT_CONTROL_CLIENT_TYPE_SHIFT)
+#define AREMC_STAT_CONTROL_CLIENT_TYPE_RANGE                    _MK_SHIFT_CONST(8):_MK_SHIFT_CONST(8)
+#define AREMC_STAT_CONTROL_CLIENT_TYPE_ROW                      0
+#define AREMC_STAT_CONTROL_CLIENT_TYPE_CMCR                     _MK_ENUM_CONST(0)
+#define AREMC_STAT_CONTROL_CLIENT_TYPE_MPCORER                  _MK_ENUM_CONST(1)
+
+#define AREMC_STAT_CONTROL_EVENT_SHIFT                  _MK_SHIFT_CONST(16)
+#define AREMC_STAT_CONTROL_EVENT_FIELD                  (_MK_MASK_CONST(0x1) << AREMC_STAT_CONTROL_EVENT_SHIFT)
+#define AREMC_STAT_CONTROL_EVENT_RANGE                  _MK_SHIFT_CONST(16):_MK_SHIFT_CONST(16)
+#define AREMC_STAT_CONTROL_EVENT_ROW                    0
+#define AREMC_STAT_CONTROL_EVENT_QUALIFIED                      _MK_ENUM_CONST(0)
+#define AREMC_STAT_CONTROL_EVENT_RD_WR_CHANGE                   _MK_ENUM_CONST(1)
+
+#define AREMC_STAT_CONTROL_FILTER_CLIENT_SHIFT                  _MK_SHIFT_CONST(26)
+#define AREMC_STAT_CONTROL_FILTER_CLIENT_FIELD                  (_MK_MASK_CONST(0x1) << AREMC_STAT_CONTROL_FILTER_CLIENT_SHIFT)
+#define AREMC_STAT_CONTROL_FILTER_CLIENT_RANGE                  _MK_SHIFT_CONST(26):_MK_SHIFT_CONST(26)
+#define AREMC_STAT_CONTROL_FILTER_CLIENT_ROW                    0
+#define AREMC_STAT_CONTROL_FILTER_CLIENT_DISABLE                        _MK_ENUM_CONST(0)
+#define AREMC_STAT_CONTROL_FILTER_CLIENT_ENABLE                 _MK_ENUM_CONST(1)
+
+#define AREMC_STAT_CONTROL_FILTER_ADDR_SHIFT                    _MK_SHIFT_CONST(27)
+#define AREMC_STAT_CONTROL_FILTER_ADDR_FIELD                    (_MK_MASK_CONST(0x1) << AREMC_STAT_CONTROL_FILTER_ADDR_SHIFT)
+#define AREMC_STAT_CONTROL_FILTER_ADDR_RANGE                    _MK_SHIFT_CONST(27):_MK_SHIFT_CONST(27)
+#define AREMC_STAT_CONTROL_FILTER_ADDR_ROW                      0
+#define AREMC_STAT_CONTROL_FILTER_ADDR_DISABLE                  _MK_ENUM_CONST(0)
+#define AREMC_STAT_CONTROL_FILTER_ADDR_ENABLE                   _MK_ENUM_CONST(1)
+
+
+// Register EMC_STAT_LLMC_CONTROL_0_0  
+#define EMC_STAT_LLMC_CONTROL_0_0                       _MK_ADDR_CONST(0xd8)
+#define EMC_STAT_LLMC_CONTROL_0_0_WORD_COUNT                    0x1
+#define EMC_STAT_LLMC_CONTROL_0_0_RESET_VAL                     _MK_MASK_CONST(0xffff0000)
+#define EMC_STAT_LLMC_CONTROL_0_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_LLMC_CONTROL_0_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_CONTROL_0_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_CONTROL_0_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_LLMC_CONTROL_0_0_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_LLMC_CONTROL_0_0_LLMC_CONTROL_0_SHIFT                  _MK_SHIFT_CONST(0)
+#define EMC_STAT_LLMC_CONTROL_0_0_LLMC_CONTROL_0_FIELD                  (_MK_MASK_CONST(0xffffffff) << EMC_STAT_LLMC_CONTROL_0_0_LLMC_CONTROL_0_SHIFT)
+#define EMC_STAT_LLMC_CONTROL_0_0_LLMC_CONTROL_0_RANGE                  31:0
+#define EMC_STAT_LLMC_CONTROL_0_0_LLMC_CONTROL_0_WOFFSET                        0x0
+#define EMC_STAT_LLMC_CONTROL_0_0_LLMC_CONTROL_0_DEFAULT                        _MK_MASK_CONST(0xffff0000)
+#define EMC_STAT_LLMC_CONTROL_0_0_LLMC_CONTROL_0_DEFAULT_MASK                   _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_LLMC_CONTROL_0_0_LLMC_CONTROL_0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_CONTROL_0_0_LLMC_CONTROL_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_CONTROL_0_0_LLMC_CONTROL_0_INIT_ENUM                      -65536
+
+
+// Reserved address 220 [0xdc] 
+
+// Packet AREMC_STAT_HIST_LIMIT
+#define AREMC_STAT_HIST_LIMIT_SIZE 32
+
+#define AREMC_STAT_HIST_LIMIT_LOW_SHIFT                 _MK_SHIFT_CONST(0)
+#define AREMC_STAT_HIST_LIMIT_LOW_FIELD                 (_MK_MASK_CONST(0xffff) << AREMC_STAT_HIST_LIMIT_LOW_SHIFT)
+#define AREMC_STAT_HIST_LIMIT_LOW_RANGE                 _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(0)
+#define AREMC_STAT_HIST_LIMIT_LOW_ROW                   0
+
+#define AREMC_STAT_HIST_LIMIT_HIGH_SHIFT                        _MK_SHIFT_CONST(16)
+#define AREMC_STAT_HIST_LIMIT_HIGH_FIELD                        (_MK_MASK_CONST(0xffff) << AREMC_STAT_HIST_LIMIT_HIGH_SHIFT)
+#define AREMC_STAT_HIST_LIMIT_HIGH_RANGE                        _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(16)
+#define AREMC_STAT_HIST_LIMIT_HIGH_ROW                  0
+
+
+// Register EMC_STAT_LLMC_HIST_LIMIT_0_0  
+#define EMC_STAT_LLMC_HIST_LIMIT_0_0                    _MK_ADDR_CONST(0xe0)
+#define EMC_STAT_LLMC_HIST_LIMIT_0_0_WORD_COUNT                         0x1
+#define EMC_STAT_LLMC_HIST_LIMIT_0_0_RESET_VAL                  _MK_MASK_CONST(0xffff0000)
+#define EMC_STAT_LLMC_HIST_LIMIT_0_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_LLMC_HIST_LIMIT_0_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_HIST_LIMIT_0_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_HIST_LIMIT_0_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_LLMC_HIST_LIMIT_0_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_LLMC_HIST_LIMIT_0_0_LLMC_HIST_LIMIT_0_SHIFT                    _MK_SHIFT_CONST(0)
+#define EMC_STAT_LLMC_HIST_LIMIT_0_0_LLMC_HIST_LIMIT_0_FIELD                    (_MK_MASK_CONST(0xffffffff) << EMC_STAT_LLMC_HIST_LIMIT_0_0_LLMC_HIST_LIMIT_0_SHIFT)
+#define EMC_STAT_LLMC_HIST_LIMIT_0_0_LLMC_HIST_LIMIT_0_RANGE                    31:0
+#define EMC_STAT_LLMC_HIST_LIMIT_0_0_LLMC_HIST_LIMIT_0_WOFFSET                  0x0
+#define EMC_STAT_LLMC_HIST_LIMIT_0_0_LLMC_HIST_LIMIT_0_DEFAULT                  _MK_MASK_CONST(0xffff0000)
+#define EMC_STAT_LLMC_HIST_LIMIT_0_0_LLMC_HIST_LIMIT_0_DEFAULT_MASK                     _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_LLMC_HIST_LIMIT_0_0_LLMC_HIST_LIMIT_0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_HIST_LIMIT_0_0_LLMC_HIST_LIMIT_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_HIST_LIMIT_0_0_LLMC_HIST_LIMIT_0_INIT_ENUM                        -65536
+
+
+// Reserved address 228 [0xe4] 
+
+// Register EMC_STAT_LLMC_COUNT_0_0  
+#define EMC_STAT_LLMC_COUNT_0_0                 _MK_ADDR_CONST(0xe8)
+#define EMC_STAT_LLMC_COUNT_0_0_WORD_COUNT                      0x1
+#define EMC_STAT_LLMC_COUNT_0_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_COUNT_0_0_RESET_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_COUNT_0_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_COUNT_0_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_COUNT_0_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_LLMC_COUNT_0_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_COUNT_0_0_LLMC_COUNT_0_SHIFT                      _MK_SHIFT_CONST(0)
+#define EMC_STAT_LLMC_COUNT_0_0_LLMC_COUNT_0_FIELD                      (_MK_MASK_CONST(0xffffffff) << EMC_STAT_LLMC_COUNT_0_0_LLMC_COUNT_0_SHIFT)
+#define EMC_STAT_LLMC_COUNT_0_0_LLMC_COUNT_0_RANGE                      31:0
+#define EMC_STAT_LLMC_COUNT_0_0_LLMC_COUNT_0_WOFFSET                    0x0
+#define EMC_STAT_LLMC_COUNT_0_0_LLMC_COUNT_0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_COUNT_0_0_LLMC_COUNT_0_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_COUNT_0_0_LLMC_COUNT_0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_COUNT_0_0_LLMC_COUNT_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Reserved address 236 [0xec] 
+
+// Register EMC_STAT_LLMC_HIST_0_0  
+#define EMC_STAT_LLMC_HIST_0_0                  _MK_ADDR_CONST(0xf0)
+#define EMC_STAT_LLMC_HIST_0_0_WORD_COUNT                       0x1
+#define EMC_STAT_LLMC_HIST_0_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_HIST_0_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_HIST_0_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_HIST_0_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_HIST_0_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_LLMC_HIST_0_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_HIST_0_0_LLMC_HIST_0_SHIFT                        _MK_SHIFT_CONST(0)
+#define EMC_STAT_LLMC_HIST_0_0_LLMC_HIST_0_FIELD                        (_MK_MASK_CONST(0xffffffff) << EMC_STAT_LLMC_HIST_0_0_LLMC_HIST_0_SHIFT)
+#define EMC_STAT_LLMC_HIST_0_0_LLMC_HIST_0_RANGE                        31:0
+#define EMC_STAT_LLMC_HIST_0_0_LLMC_HIST_0_WOFFSET                      0x0
+#define EMC_STAT_LLMC_HIST_0_0_LLMC_HIST_0_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_HIST_0_0_LLMC_HIST_0_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_HIST_0_0_LLMC_HIST_0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_HIST_0_0_LLMC_HIST_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Reserved address 244 [0xf4] 
+
+// Register EMC_STAT_PWR_CLOCK_LIMIT_0  
+#define EMC_STAT_PWR_CLOCK_LIMIT_0                      _MK_ADDR_CONST(0xf8)
+#define EMC_STAT_PWR_CLOCK_LIMIT_0_WORD_COUNT                   0x1
+#define EMC_STAT_PWR_CLOCK_LIMIT_0_RESET_VAL                    _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_PWR_CLOCK_LIMIT_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_PWR_CLOCK_LIMIT_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_PWR_CLOCK_LIMIT_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_PWR_CLOCK_LIMIT_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_PWR_CLOCK_LIMIT_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_PWR_CLOCK_LIMIT_0_PWR_CLOCK_LIMIT_SHIFT                        _MK_SHIFT_CONST(0)
+#define EMC_STAT_PWR_CLOCK_LIMIT_0_PWR_CLOCK_LIMIT_FIELD                        (_MK_MASK_CONST(0xffffffff) << EMC_STAT_PWR_CLOCK_LIMIT_0_PWR_CLOCK_LIMIT_SHIFT)
+#define EMC_STAT_PWR_CLOCK_LIMIT_0_PWR_CLOCK_LIMIT_RANGE                        31:0
+#define EMC_STAT_PWR_CLOCK_LIMIT_0_PWR_CLOCK_LIMIT_WOFFSET                      0x0
+#define EMC_STAT_PWR_CLOCK_LIMIT_0_PWR_CLOCK_LIMIT_DEFAULT                      _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_PWR_CLOCK_LIMIT_0_PWR_CLOCK_LIMIT_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_PWR_CLOCK_LIMIT_0_PWR_CLOCK_LIMIT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_STAT_PWR_CLOCK_LIMIT_0_PWR_CLOCK_LIMIT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_PWR_CLOCK_LIMIT_0_PWR_CLOCK_LIMIT_INIT_ENUM                    -1
+
+
+// Register EMC_STAT_PWR_CLOCKS_0  
+#define EMC_STAT_PWR_CLOCKS_0                   _MK_ADDR_CONST(0xfc)
+#define EMC_STAT_PWR_CLOCKS_0_WORD_COUNT                        0x1
+#define EMC_STAT_PWR_CLOCKS_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define EMC_STAT_PWR_CLOCKS_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_STAT_PWR_CLOCKS_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_PWR_CLOCKS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_STAT_PWR_CLOCKS_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_PWR_CLOCKS_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_STAT_PWR_CLOCKS_0_PWR_CLOCKS_SHIFT                  _MK_SHIFT_CONST(0)
+#define EMC_STAT_PWR_CLOCKS_0_PWR_CLOCKS_FIELD                  (_MK_MASK_CONST(0xffffffff) << EMC_STAT_PWR_CLOCKS_0_PWR_CLOCKS_SHIFT)
+#define EMC_STAT_PWR_CLOCKS_0_PWR_CLOCKS_RANGE                  31:0
+#define EMC_STAT_PWR_CLOCKS_0_PWR_CLOCKS_WOFFSET                        0x0
+#define EMC_STAT_PWR_CLOCKS_0_PWR_CLOCKS_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_STAT_PWR_CLOCKS_0_PWR_CLOCKS_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_STAT_PWR_CLOCKS_0_PWR_CLOCKS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_PWR_CLOCKS_0_PWR_CLOCKS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register EMC_STAT_PWR_COUNT_0  
+#define EMC_STAT_PWR_COUNT_0                    _MK_ADDR_CONST(0x100)
+#define EMC_STAT_PWR_COUNT_0_WORD_COUNT                         0x1
+#define EMC_STAT_PWR_COUNT_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_PWR_COUNT_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_STAT_PWR_COUNT_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_PWR_COUNT_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_PWR_COUNT_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_PWR_COUNT_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_STAT_PWR_COUNT_0_PWR_COUNT_SHIFT                    _MK_SHIFT_CONST(0)
+#define EMC_STAT_PWR_COUNT_0_PWR_COUNT_FIELD                    (_MK_MASK_CONST(0xffffffff) << EMC_STAT_PWR_COUNT_0_PWR_COUNT_SHIFT)
+#define EMC_STAT_PWR_COUNT_0_PWR_COUNT_RANGE                    31:0
+#define EMC_STAT_PWR_COUNT_0_PWR_COUNT_WOFFSET                  0x0
+#define EMC_STAT_PWR_COUNT_0_PWR_COUNT_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_PWR_COUNT_0_PWR_COUNT_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_PWR_COUNT_0_PWR_COUNT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_PWR_COUNT_0_PWR_COUNT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register EMC_AUTO_CAL_CONFIG_0  
+#define EMC_AUTO_CAL_CONFIG_0                   _MK_ADDR_CONST(0x104)
+#define EMC_AUTO_CAL_CONFIG_0_WORD_COUNT                        0x1
+#define EMC_AUTO_CAL_CONFIG_0_RESET_VAL                         _MK_MASK_CONST(0xa60000)
+#define EMC_AUTO_CAL_CONFIG_0_RESET_MASK                        _MK_MASK_CONST(0xc3ff1f1f)
+#define EMC_AUTO_CAL_CONFIG_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_CONFIG_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_CONFIG_0_READ_MASK                         _MK_MASK_CONST(0xc3ff1f1f)
+#define EMC_AUTO_CAL_CONFIG_0_WRITE_MASK                        _MK_MASK_CONST(0x43ff1f1f)
+// 2's complement offset for pull-up value
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_PU_OFFSET_SHIFT                  _MK_SHIFT_CONST(0)
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_PU_OFFSET_FIELD                  (_MK_MASK_CONST(0x1f) << EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_PU_OFFSET_SHIFT)
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_PU_OFFSET_RANGE                  4:0
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_PU_OFFSET_WOFFSET                        0x0
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_PU_OFFSET_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_PU_OFFSET_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_PU_OFFSET_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_PU_OFFSET_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// 2's complement offset for pull-down value
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_PD_OFFSET_SHIFT                  _MK_SHIFT_CONST(8)
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_PD_OFFSET_FIELD                  (_MK_MASK_CONST(0x1f) << EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_PD_OFFSET_SHIFT)
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_PD_OFFSET_RANGE                  12:8
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_PD_OFFSET_WOFFSET                        0x0
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_PD_OFFSET_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_PD_OFFSET_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_PD_OFFSET_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_PD_OFFSET_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Auto Cal calibration step interval (in emc clocks)
+// - the default is set for 1.0us calibration step at 166MHz
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_STEP_SHIFT                       _MK_SHIFT_CONST(16)
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_STEP_FIELD                       (_MK_MASK_CONST(0x3ff) << EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_STEP_SHIFT)
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_STEP_RANGE                       25:16
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_STEP_WOFFSET                     0x0
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_STEP_DEFAULT                     _MK_MASK_CONST(0xa6)
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_STEP_DEFAULT_MASK                        _MK_MASK_CONST(0x3ff)
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_STEP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_STEP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// 0 (normal operation): use AUTO_CAL_PU/PD_OFFSET as an offset 
+//                       to the calibration tate machine setting
+// 1 (override)        : use AUTO_CAL_PU/PD_OFFSET register 
+//                       values directly
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_OVERRIDE_SHIFT                   _MK_SHIFT_CONST(30)
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_OVERRIDE_FIELD                   (_MK_MASK_CONST(0x1) << EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_OVERRIDE_SHIFT)
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_OVERRIDE_RANGE                   30:30
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_OVERRIDE_WOFFSET                 0x0
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_OVERRIDE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_OVERRIDE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_OVERRIDE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_OVERRIDE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Writing a one to this bit starts the calibration state
+// machine.  This bit must be set even if the override is
+// set in order to latch in the override value.
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_START_SHIFT                      _MK_SHIFT_CONST(31)
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_START_FIELD                      (_MK_MASK_CONST(0x1) << EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_START_SHIFT)
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_START_RANGE                      31:31
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_START_WOFFSET                    0x0
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_START_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_START_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_START_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_START_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register EMC_AUTO_CAL_INTERVAL_0  
+#define EMC_AUTO_CAL_INTERVAL_0                 _MK_ADDR_CONST(0x108)
+#define EMC_AUTO_CAL_INTERVAL_0_WORD_COUNT                      0x1
+#define EMC_AUTO_CAL_INTERVAL_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_INTERVAL_0_RESET_MASK                      _MK_MASK_CONST(0xfffffff)
+#define EMC_AUTO_CAL_INTERVAL_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_INTERVAL_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_INTERVAL_0_READ_MASK                       _MK_MASK_CONST(0xfffffff)
+#define EMC_AUTO_CAL_INTERVAL_0_WRITE_MASK                      _MK_MASK_CONST(0xfffffff)
+// 0: do calibration once
+// Otherwise, auto-calibration occurs at intervals equivalent
+// to the programmed number of cycles.
+#define EMC_AUTO_CAL_INTERVAL_0_AUTO_CAL_INTERVAL_SHIFT                 _MK_SHIFT_CONST(0)
+#define EMC_AUTO_CAL_INTERVAL_0_AUTO_CAL_INTERVAL_FIELD                 (_MK_MASK_CONST(0xfffffff) << EMC_AUTO_CAL_INTERVAL_0_AUTO_CAL_INTERVAL_SHIFT)
+#define EMC_AUTO_CAL_INTERVAL_0_AUTO_CAL_INTERVAL_RANGE                 27:0
+#define EMC_AUTO_CAL_INTERVAL_0_AUTO_CAL_INTERVAL_WOFFSET                       0x0
+#define EMC_AUTO_CAL_INTERVAL_0_AUTO_CAL_INTERVAL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_INTERVAL_0_AUTO_CAL_INTERVAL_DEFAULT_MASK                  _MK_MASK_CONST(0xfffffff)
+#define EMC_AUTO_CAL_INTERVAL_0_AUTO_CAL_INTERVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_INTERVAL_0_AUTO_CAL_INTERVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EMC_AUTO_CAL_STATUS_0  
+#define EMC_AUTO_CAL_STATUS_0                   _MK_ADDR_CONST(0x10c)
+#define EMC_AUTO_CAL_STATUS_0_WORD_COUNT                        0x1
+#define EMC_AUTO_CAL_STATUS_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_STATUS_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_STATUS_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_STATUS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_STATUS_0_READ_MASK                         _MK_MASK_CONST(0x9f1f1f1f)
+#define EMC_AUTO_CAL_STATUS_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+// Pullup code generated by auto-calibration
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLUP_SHIFT                     _MK_SHIFT_CONST(0)
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLUP_FIELD                     (_MK_MASK_CONST(0x1f) << EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLUP_SHIFT)
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLUP_RANGE                     4:0
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLUP_WOFFSET                   0x0
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLUP_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLUP_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLUP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLUP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Pulldown code generated by auto-calibration
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLDOWN_SHIFT                   _MK_SHIFT_CONST(8)
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLDOWN_FIELD                   (_MK_MASK_CONST(0x1f) << EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLDOWN_SHIFT)
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLDOWN_RANGE                   12:8
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLDOWN_WOFFSET                 0x0
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLDOWN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLDOWN_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLDOWN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLDOWN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Pullup code sent to pads
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLUP_ADJ_SHIFT                 _MK_SHIFT_CONST(16)
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLUP_ADJ_FIELD                 (_MK_MASK_CONST(0x1f) << EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLUP_ADJ_SHIFT)
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLUP_ADJ_RANGE                 20:16
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLUP_ADJ_WOFFSET                       0x0
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLUP_ADJ_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLUP_ADJ_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLUP_ADJ_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLUP_ADJ_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Pulldown code sent to pads
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLDOWN_ADJ_SHIFT                       _MK_SHIFT_CONST(24)
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLDOWN_ADJ_FIELD                       (_MK_MASK_CONST(0x1f) << EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLDOWN_ADJ_SHIFT)
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLDOWN_ADJ_RANGE                       28:24
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLDOWN_ADJ_WOFFSET                     0x0
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLDOWN_ADJ_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLDOWN_ADJ_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLDOWN_ADJ_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLDOWN_ADJ_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// One when auto calibrate is active
+// - valid only after auto calibrate sequence has 
+// completed (EMC_CAL_ACTIVE == 0)
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_ACTIVE_SHIFT                     _MK_SHIFT_CONST(31)
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_ACTIVE_FIELD                     (_MK_MASK_CONST(0x1) << EMC_AUTO_CAL_STATUS_0_AUTO_CAL_ACTIVE_SHIFT)
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_ACTIVE_RANGE                     31:31
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_ACTIVE_WOFFSET                   0x0
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_ACTIVE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_ACTIVE_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_ACTIVE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_ACTIVE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+//
+// REGISTER LIST
+//
+#define LIST_AREMC_REGS(_op_) \
+_op_(EMC_INTSTATUS_0) \
+_op_(EMC_INTMASK_0) \
+_op_(EMC_DBG_0) \
+_op_(EMC_CFG_0) \
+_op_(EMC_ADR_CFG_0) \
+_op_(EMC_REFCTRL_0) \
+_op_(EMC_PIN_0) \
+_op_(EMC_TIMING_CONTROL_0) \
+_op_(EMC_TIMING0_0) \
+_op_(EMC_TIMING1_0) \
+_op_(EMC_TIMING2_0) \
+_op_(EMC_TIMING3_0) \
+_op_(EMC_TIMING4_0) \
+_op_(EMC_TIMING5_0) \
+_op_(EMC_MRS_0) \
+_op_(EMC_EMRS_0) \
+_op_(EMC_REF_0) \
+_op_(EMC_PRE_0) \
+_op_(EMC_NOP_0) \
+_op_(EMC_SELF_REF_0) \
+_op_(EMC_DPD_0) \
+_op_(EMC_CMDQ_0) \
+_op_(EMC_FBIO_CFG1_0) \
+_op_(EMC_FBIO_DQSIB_DLY_0) \
+_op_(EMC_FBIO_SPARE_0) \
+_op_(EMC_FBIO_CFG5_0) \
+_op_(EMC_FBIO_WRPTR_EQ_2_0) \
+_op_(EMC_FBIO_QUSE_DLY_0) \
+_op_(EMC_FBIO_CFG6_0) \
+_op_(EMC_BUSARB_0) \
+_op_(EMC_DYN_DQS_0) \
+_op_(EMC_DYN_QUSE_0) \
+_op_(EMC_DQS_TRIMMER_RD0_0) \
+_op_(EMC_DQS_TRIMMER_RD1_0) \
+_op_(EMC_DQS_TRIMMER_RD2_0) \
+_op_(EMC_DQS_TRIMMER_RD3_0) \
+_op_(EMC_QUSE_TRIMMER_RD0_0) \
+_op_(EMC_QUSE_TRIMMER_RD1_0) \
+_op_(EMC_QUSE_TRIMMER_RD2_0) \
+_op_(EMC_QUSE_TRIMMER_RD3_0) \
+_op_(EMC_CLKEN_OVERRIDE_0) \
+_op_(EMC_LL_ARB_CONFIG_0) \
+_op_(EMC_T_MIN_CRITICAL_HP_0) \
+_op_(EMC_T_MIN_CRITICAL_TIMEOUT_0) \
+_op_(EMC_T_MIN_LOAD_0) \
+_op_(EMC_T_MAX_CRITICAL_HP_0) \
+_op_(EMC_T_MAX_CRITICAL_TIMEOUT_0) \
+_op_(EMC_T_MAX_LOAD_0) \
+_op_(EMC_STAT_CONTROL_0) \
+_op_(EMC_STAT_STATUS_0) \
+_op_(EMC_STAT_LLMC_ADDR_LOW_0) \
+_op_(EMC_STAT_LLMC_ADDR_HIGH_0) \
+_op_(EMC_STAT_LLMC_CLOCK_LIMIT_0) \
+_op_(EMC_STAT_LLMC_CLOCKS_0) \
+_op_(EMC_STAT_LLMC_CONTROL_0_0) \
+_op_(EMC_STAT_LLMC_HIST_LIMIT_0_0) \
+_op_(EMC_STAT_LLMC_COUNT_0_0) \
+_op_(EMC_STAT_LLMC_HIST_0_0) \
+_op_(EMC_STAT_PWR_CLOCK_LIMIT_0) \
+_op_(EMC_STAT_PWR_CLOCKS_0) \
+_op_(EMC_STAT_PWR_COUNT_0) \
+_op_(EMC_AUTO_CAL_CONFIG_0) \
+_op_(EMC_AUTO_CAL_INTERVAL_0) \
+_op_(EMC_AUTO_CAL_STATUS_0)
+
+
+//
+// ADDRESS SPACES
+//
+
+#define BASE_ADDRESS_EMC        0x00000000
+
+//
+// AREMC REGISTER BANKS
+//
+
+#define EMC0_FIRST_REG 0x0000 // EMC_INTSTATUS_0
+#define EMC0_LAST_REG 0x00d8 // EMC_STAT_LLMC_CONTROL_0_0
+#define EMC1_FIRST_REG 0x00e0 // EMC_STAT_LLMC_HIST_LIMIT_0_0
+#define EMC1_LAST_REG 0x00e0 // EMC_STAT_LLMC_HIST_LIMIT_0_0
+#define EMC2_FIRST_REG 0x00e8 // EMC_STAT_LLMC_COUNT_0_0
+#define EMC2_LAST_REG 0x00e8 // EMC_STAT_LLMC_COUNT_0_0
+#define EMC3_FIRST_REG 0x00f0 // EMC_STAT_LLMC_HIST_0_0
+#define EMC3_LAST_REG 0x00f0 // EMC_STAT_LLMC_HIST_0_0
+#define EMC4_FIRST_REG 0x00f8 // EMC_STAT_PWR_CLOCK_LIMIT_0
+#define EMC4_LAST_REG 0x010c // EMC_AUTO_CAL_STATUS_0
+
+#ifndef _MK_SHIFT_CONST
+  #define _MK_SHIFT_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_MASK_CONST
+  #define _MK_MASK_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_ENUM_CONST
+  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
+#endif
+#ifndef _MK_ADDR_CONST
+  #define _MK_ADDR_CONST(_constant_) _constant_
+#endif
+
+#endif // ifndef ___AREMC_H_INC_
diff --git a/arch/arm/mach-tegra/include/ap15/arfuse.h b/arch/arm/mach-tegra/include/ap15/arfuse.h
new file mode 100644
index 000000000000..67f8e5c142a6
--- /dev/null
+++ b/arch/arm/mach-tegra/include/ap15/arfuse.h
@@ -0,0 +1,3997 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+//
+// DO NOT EDIT - generated by simspec!
+//
+
+#ifndef ___ARFUSE_H_INC_
+#define ___ARFUSE_H_INC_
+
+// Register FUSE_FUSECTRL_0  
+#define FUSE_FUSECTRL_0                 _MK_ADDR_CONST(0x0)
+#define FUSE_FUSECTRL_0_WORD_COUNT                      0x1
+#define FUSE_FUSECTRL_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSECTRL_0_RESET_MASK                      _MK_MASK_CONST(0x3)
+#define FUSE_FUSECTRL_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSECTRL_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define FUSE_FUSECTRL_0_READ_MASK                       _MK_MASK_CONST(0x10f0003)
+#define FUSE_FUSECTRL_0_WRITE_MASK                      _MK_MASK_CONST(0x3)
+#define FUSE_FUSECTRL_0_FUSECTRL_CMD_SHIFT                      _MK_SHIFT_CONST(0)
+#define FUSE_FUSECTRL_0_FUSECTRL_CMD_FIELD                      (_MK_MASK_CONST(0x3) << FUSE_FUSECTRL_0_FUSECTRL_CMD_SHIFT)
+#define FUSE_FUSECTRL_0_FUSECTRL_CMD_RANGE                      1:0
+#define FUSE_FUSECTRL_0_FUSECTRL_CMD_WOFFSET                    0x0
+#define FUSE_FUSECTRL_0_FUSECTRL_CMD_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSECTRL_0_FUSECTRL_CMD_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define FUSE_FUSECTRL_0_FUSECTRL_CMD_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSECTRL_0_FUSECTRL_CMD_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSECTRL_0_FUSECTRL_CMD_INIT_ENUM                  IDLE
+#define FUSE_FUSECTRL_0_FUSECTRL_CMD_IDLE                       _MK_ENUM_CONST(0)
+#define FUSE_FUSECTRL_0_FUSECTRL_CMD_READ                       _MK_ENUM_CONST(1)
+#define FUSE_FUSECTRL_0_FUSECTRL_CMD_WRITE                      _MK_ENUM_CONST(2)
+#define FUSE_FUSECTRL_0_FUSECTRL_CMD_VERIFY                     _MK_ENUM_CONST(3)
+
+#define FUSE_FUSECTRL_0_FUSECTRL_STATE_SHIFT                    _MK_SHIFT_CONST(16)
+#define FUSE_FUSECTRL_0_FUSECTRL_STATE_FIELD                    (_MK_MASK_CONST(0xf) << FUSE_FUSECTRL_0_FUSECTRL_STATE_SHIFT)
+#define FUSE_FUSECTRL_0_FUSECTRL_STATE_RANGE                    19:16
+#define FUSE_FUSECTRL_0_FUSECTRL_STATE_WOFFSET                  0x0
+#define FUSE_FUSECTRL_0_FUSECTRL_STATE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSECTRL_0_FUSECTRL_STATE_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSECTRL_0_FUSECTRL_STATE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSECTRL_0_FUSECTRL_STATE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSECTRL_0_FUSECTRL_VERIFY_SHIFT                   _MK_SHIFT_CONST(24)
+#define FUSE_FUSECTRL_0_FUSECTRL_VERIFY_FIELD                   (_MK_MASK_CONST(0x1) << FUSE_FUSECTRL_0_FUSECTRL_VERIFY_SHIFT)
+#define FUSE_FUSECTRL_0_FUSECTRL_VERIFY_RANGE                   24:24
+#define FUSE_FUSECTRL_0_FUSECTRL_VERIFY_WOFFSET                 0x0
+#define FUSE_FUSECTRL_0_FUSECTRL_VERIFY_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSECTRL_0_FUSECTRL_VERIFY_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSECTRL_0_FUSECTRL_VERIFY_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSECTRL_0_FUSECTRL_VERIFY_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_FUSETIME1_0  
+#define FUSE_FUSETIME1_0                        _MK_ADDR_CONST(0x4)
+#define FUSE_FUSETIME1_0_WORD_COUNT                     0x1
+#define FUSE_FUSETIME1_0_RESET_VAL                      _MK_MASK_CONST(0x11100000)
+#define FUSE_FUSETIME1_0_RESET_MASK                     _MK_MASK_CONST(0xfff00000)
+#define FUSE_FUSETIME1_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define FUSE_FUSETIME1_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSETIME1_0_READ_MASK                      _MK_MASK_CONST(0xfff00000)
+#define FUSE_FUSETIME1_0_WRITE_MASK                     _MK_MASK_CONST(0xfff00000)
+#define FUSE_FUSETIME1_0_FUSETIME1_TSU_FUSEL_SHIFT                      _MK_SHIFT_CONST(20)
+#define FUSE_FUSETIME1_0_FUSETIME1_TSU_FUSEL_FIELD                      (_MK_MASK_CONST(0xf) << FUSE_FUSETIME1_0_FUSETIME1_TSU_FUSEL_SHIFT)
+#define FUSE_FUSETIME1_0_FUSETIME1_TSU_FUSEL_RANGE                      23:20
+#define FUSE_FUSETIME1_0_FUSETIME1_TSU_FUSEL_WOFFSET                    0x0
+#define FUSE_FUSETIME1_0_FUSETIME1_TSU_FUSEL_DEFAULT                    _MK_MASK_CONST(0x1)
+#define FUSE_FUSETIME1_0_FUSETIME1_TSU_FUSEL_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
+#define FUSE_FUSETIME1_0_FUSETIME1_TSU_FUSEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSETIME1_0_FUSETIME1_TSU_FUSEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSETIME1_0_FUSETIME1_TSU_FUSEOUT_SHIFT                    _MK_SHIFT_CONST(24)
+#define FUSE_FUSETIME1_0_FUSETIME1_TSU_FUSEOUT_FIELD                    (_MK_MASK_CONST(0xf) << FUSE_FUSETIME1_0_FUSETIME1_TSU_FUSEOUT_SHIFT)
+#define FUSE_FUSETIME1_0_FUSETIME1_TSU_FUSEOUT_RANGE                    27:24
+#define FUSE_FUSETIME1_0_FUSETIME1_TSU_FUSEOUT_WOFFSET                  0x0
+#define FUSE_FUSETIME1_0_FUSETIME1_TSU_FUSEOUT_DEFAULT                  _MK_MASK_CONST(0x1)
+#define FUSE_FUSETIME1_0_FUSETIME1_TSU_FUSEOUT_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
+#define FUSE_FUSETIME1_0_FUSETIME1_TSU_FUSEOUT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSETIME1_0_FUSETIME1_TSU_FUSEOUT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSETIME1_0_FUSETIME1_THOLD_FUSEL_SHIFT                    _MK_SHIFT_CONST(28)
+#define FUSE_FUSETIME1_0_FUSETIME1_THOLD_FUSEL_FIELD                    (_MK_MASK_CONST(0xf) << FUSE_FUSETIME1_0_FUSETIME1_THOLD_FUSEL_SHIFT)
+#define FUSE_FUSETIME1_0_FUSETIME1_THOLD_FUSEL_RANGE                    31:28
+#define FUSE_FUSETIME1_0_FUSETIME1_THOLD_FUSEL_WOFFSET                  0x0
+#define FUSE_FUSETIME1_0_FUSETIME1_THOLD_FUSEL_DEFAULT                  _MK_MASK_CONST(0x1)
+#define FUSE_FUSETIME1_0_FUSETIME1_THOLD_FUSEL_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
+#define FUSE_FUSETIME1_0_FUSETIME1_THOLD_FUSEL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSETIME1_0_FUSETIME1_THOLD_FUSEL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_FUSETIME2_0  
+#define FUSE_FUSETIME2_0                        _MK_ADDR_CONST(0x8)
+#define FUSE_FUSETIME2_0_WORD_COUNT                     0x1
+#define FUSE_FUSETIME2_0_RESET_VAL                      _MK_MASK_CONST(0x300001a)
+#define FUSE_FUSETIME2_0_RESET_MASK                     _MK_MASK_CONST(0xff0fffff)
+#define FUSE_FUSETIME2_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define FUSE_FUSETIME2_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSETIME2_0_READ_MASK                      _MK_MASK_CONST(0xff0fffff)
+#define FUSE_FUSETIME2_0_WRITE_MASK                     _MK_MASK_CONST(0xff0fffff)
+// Calculation based on 1us program time and 38.4615 ns fuse_clk period.
+// Unfortunately the 1us program time is wrong, the real value is 5us.
+// So the init value is wrong and must be multiplied by 5 to obtain the correct value:
+//    init=0x00000082
+#define FUSE_FUSETIME2_0_FUSETIME2_TPROGRAM_SHIFT                       _MK_SHIFT_CONST(0)
+#define FUSE_FUSETIME2_0_FUSETIME2_TPROGRAM_FIELD                       (_MK_MASK_CONST(0xfffff) << FUSE_FUSETIME2_0_FUSETIME2_TPROGRAM_SHIFT)
+#define FUSE_FUSETIME2_0_FUSETIME2_TPROGRAM_RANGE                       19:0
+#define FUSE_FUSETIME2_0_FUSETIME2_TPROGRAM_WOFFSET                     0x0
+#define FUSE_FUSETIME2_0_FUSETIME2_TPROGRAM_DEFAULT                     _MK_MASK_CONST(0x1a)
+#define FUSE_FUSETIME2_0_FUSETIME2_TPROGRAM_DEFAULT_MASK                        _MK_MASK_CONST(0xfffff)
+#define FUSE_FUSETIME2_0_FUSETIME2_TPROGRAM_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSETIME2_0_FUSETIME2_TPROGRAM_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSETIME2_0_FUSETIME2_TSENSE_SHIFT                 _MK_SHIFT_CONST(24)
+#define FUSE_FUSETIME2_0_FUSETIME2_TSENSE_FIELD                 (_MK_MASK_CONST(0xff) << FUSE_FUSETIME2_0_FUSETIME2_TSENSE_SHIFT)
+#define FUSE_FUSETIME2_0_FUSETIME2_TSENSE_RANGE                 31:24
+#define FUSE_FUSETIME2_0_FUSETIME2_TSENSE_WOFFSET                       0x0
+#define FUSE_FUSETIME2_0_FUSETIME2_TSENSE_DEFAULT                       _MK_MASK_CONST(0x3)
+#define FUSE_FUSETIME2_0_FUSETIME2_TSENSE_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define FUSE_FUSETIME2_0_FUSETIME2_TSENSE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSETIME2_0_FUSETIME2_TSENSE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_FUSEDATA0_0  
+#define FUSE_FUSEDATA0_0                        _MK_ADDR_CONST(0xc)
+#define FUSE_FUSEDATA0_0_WORD_COUNT                     0x1
+#define FUSE_FUSEDATA0_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA0_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA0_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA0_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA0_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA0_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA0_0_FUSEDATA0_SHIFT                        _MK_SHIFT_CONST(0)
+#define FUSE_FUSEDATA0_0_FUSEDATA0_FIELD                        (_MK_MASK_CONST(0xffffffff) << FUSE_FUSEDATA0_0_FUSEDATA0_SHIFT)
+#define FUSE_FUSEDATA0_0_FUSEDATA0_RANGE                        31:0
+#define FUSE_FUSEDATA0_0_FUSEDATA0_WOFFSET                      0x0
+#define FUSE_FUSEDATA0_0_FUSEDATA0_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA0_0_FUSEDATA0_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA0_0_FUSEDATA0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA0_0_FUSEDATA0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA0_0_FUSEDATA_MASTER_ENABLE__PRI_ALIAS_0_SHIFT                      _MK_SHIFT_CONST(0)
+#define FUSE_FUSEDATA0_0_FUSEDATA_MASTER_ENABLE__PRI_ALIAS_0_FIELD                      (_MK_MASK_CONST(0x1) << FUSE_FUSEDATA0_0_FUSEDATA_MASTER_ENABLE__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA0_0_FUSEDATA_MASTER_ENABLE__PRI_ALIAS_0_RANGE                      0:0
+#define FUSE_FUSEDATA0_0_FUSEDATA_MASTER_ENABLE__PRI_ALIAS_0_WOFFSET                    0x0
+#define FUSE_FUSEDATA0_0_FUSEDATA_MASTER_ENABLE__PRI_ALIAS_0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA0_0_FUSEDATA_MASTER_ENABLE__PRI_ALIAS_0_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FUSE_FUSEDATA0_0_FUSEDATA_MASTER_ENABLE__PRI_ALIAS_0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA0_0_FUSEDATA_MASTER_ENABLE__PRI_ALIAS_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA0_0_FUSEDATA_MASTER_DISABLE__PRI_ALIAS_0_SHIFT                     _MK_SHIFT_CONST(1)
+#define FUSE_FUSEDATA0_0_FUSEDATA_MASTER_DISABLE__PRI_ALIAS_0_FIELD                     (_MK_MASK_CONST(0x1) << FUSE_FUSEDATA0_0_FUSEDATA_MASTER_DISABLE__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA0_0_FUSEDATA_MASTER_DISABLE__PRI_ALIAS_0_RANGE                     1:1
+#define FUSE_FUSEDATA0_0_FUSEDATA_MASTER_DISABLE__PRI_ALIAS_0_WOFFSET                   0x0
+#define FUSE_FUSEDATA0_0_FUSEDATA_MASTER_DISABLE__PRI_ALIAS_0_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA0_0_FUSEDATA_MASTER_DISABLE__PRI_ALIAS_0_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FUSE_FUSEDATA0_0_FUSEDATA_MASTER_DISABLE__PRI_ALIAS_0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA0_0_FUSEDATA_MASTER_DISABLE__PRI_ALIAS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA0_0_FUSEDATA_BYPASS__PRI_ALIAS_0_SHIFT                     _MK_SHIFT_CONST(2)
+#define FUSE_FUSEDATA0_0_FUSEDATA_BYPASS__PRI_ALIAS_0_FIELD                     (_MK_MASK_CONST(0x1) << FUSE_FUSEDATA0_0_FUSEDATA_BYPASS__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA0_0_FUSEDATA_BYPASS__PRI_ALIAS_0_RANGE                     2:2
+#define FUSE_FUSEDATA0_0_FUSEDATA_BYPASS__PRI_ALIAS_0_WOFFSET                   0x0
+#define FUSE_FUSEDATA0_0_FUSEDATA_BYPASS__PRI_ALIAS_0_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA0_0_FUSEDATA_BYPASS__PRI_ALIAS_0_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FUSE_FUSEDATA0_0_FUSEDATA_BYPASS__PRI_ALIAS_0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA0_0_FUSEDATA_BYPASS__PRI_ALIAS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA0_0_FUSEDATA_RESERVE_BIT__PRI_ALIAS_0_SHIFT                        _MK_SHIFT_CONST(3)
+#define FUSE_FUSEDATA0_0_FUSEDATA_RESERVE_BIT__PRI_ALIAS_0_FIELD                        (_MK_MASK_CONST(0x1) << FUSE_FUSEDATA0_0_FUSEDATA_RESERVE_BIT__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA0_0_FUSEDATA_RESERVE_BIT__PRI_ALIAS_0_RANGE                        3:3
+#define FUSE_FUSEDATA0_0_FUSEDATA_RESERVE_BIT__PRI_ALIAS_0_WOFFSET                      0x0
+#define FUSE_FUSEDATA0_0_FUSEDATA_RESERVE_BIT__PRI_ALIAS_0_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA0_0_FUSEDATA_RESERVE_BIT__PRI_ALIAS_0_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define FUSE_FUSEDATA0_0_FUSEDATA_RESERVE_BIT__PRI_ALIAS_0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA0_0_FUSEDATA_RESERVE_BIT__PRI_ALIAS_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA0_0_FUSEDATA_PRODUCTION_MODE__PRI_ALIAS_0_SHIFT                    _MK_SHIFT_CONST(4)
+#define FUSE_FUSEDATA0_0_FUSEDATA_PRODUCTION_MODE__PRI_ALIAS_0_FIELD                    (_MK_MASK_CONST(0x1) << FUSE_FUSEDATA0_0_FUSEDATA_PRODUCTION_MODE__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA0_0_FUSEDATA_PRODUCTION_MODE__PRI_ALIAS_0_RANGE                    4:4
+#define FUSE_FUSEDATA0_0_FUSEDATA_PRODUCTION_MODE__PRI_ALIAS_0_WOFFSET                  0x0
+#define FUSE_FUSEDATA0_0_FUSEDATA_PRODUCTION_MODE__PRI_ALIAS_0_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA0_0_FUSEDATA_PRODUCTION_MODE__PRI_ALIAS_0_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FUSE_FUSEDATA0_0_FUSEDATA_PRODUCTION_MODE__PRI_ALIAS_0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA0_0_FUSEDATA_PRODUCTION_MODE__PRI_ALIAS_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA0_0_FUSEDATA_JTAG_SECUREID_VALID__PRI_ALIAS_0_SHIFT                        _MK_SHIFT_CONST(5)
+#define FUSE_FUSEDATA0_0_FUSEDATA_JTAG_SECUREID_VALID__PRI_ALIAS_0_FIELD                        (_MK_MASK_CONST(0x1) << FUSE_FUSEDATA0_0_FUSEDATA_JTAG_SECUREID_VALID__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA0_0_FUSEDATA_JTAG_SECUREID_VALID__PRI_ALIAS_0_RANGE                        5:5
+#define FUSE_FUSEDATA0_0_FUSEDATA_JTAG_SECUREID_VALID__PRI_ALIAS_0_WOFFSET                      0x0
+#define FUSE_FUSEDATA0_0_FUSEDATA_JTAG_SECUREID_VALID__PRI_ALIAS_0_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA0_0_FUSEDATA_JTAG_SECUREID_VALID__PRI_ALIAS_0_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define FUSE_FUSEDATA0_0_FUSEDATA_JTAG_SECUREID_VALID__PRI_ALIAS_0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA0_0_FUSEDATA_JTAG_SECUREID_VALID__PRI_ALIAS_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA0_0_FUSEDATA_SKU_INFO__PRI_ALIAS_0_SHIFT                   _MK_SHIFT_CONST(6)
+#define FUSE_FUSEDATA0_0_FUSEDATA_SKU_INFO__PRI_ALIAS_0_FIELD                   (_MK_MASK_CONST(0xff) << FUSE_FUSEDATA0_0_FUSEDATA_SKU_INFO__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA0_0_FUSEDATA_SKU_INFO__PRI_ALIAS_0_RANGE                   13:6
+#define FUSE_FUSEDATA0_0_FUSEDATA_SKU_INFO__PRI_ALIAS_0_WOFFSET                 0x0
+#define FUSE_FUSEDATA0_0_FUSEDATA_SKU_INFO__PRI_ALIAS_0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA0_0_FUSEDATA_SKU_INFO__PRI_ALIAS_0_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define FUSE_FUSEDATA0_0_FUSEDATA_SKU_INFO__PRI_ALIAS_0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA0_0_FUSEDATA_SKU_INFO__PRI_ALIAS_0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA0_0_FUSEDATA_PROCESS_CALIB__PRI_ALIAS_0_SHIFT                      _MK_SHIFT_CONST(14)
+#define FUSE_FUSEDATA0_0_FUSEDATA_PROCESS_CALIB__PRI_ALIAS_0_FIELD                      (_MK_MASK_CONST(0x3) << FUSE_FUSEDATA0_0_FUSEDATA_PROCESS_CALIB__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA0_0_FUSEDATA_PROCESS_CALIB__PRI_ALIAS_0_RANGE                      15:14
+#define FUSE_FUSEDATA0_0_FUSEDATA_PROCESS_CALIB__PRI_ALIAS_0_WOFFSET                    0x0
+#define FUSE_FUSEDATA0_0_FUSEDATA_PROCESS_CALIB__PRI_ALIAS_0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA0_0_FUSEDATA_PROCESS_CALIB__PRI_ALIAS_0_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define FUSE_FUSEDATA0_0_FUSEDATA_PROCESS_CALIB__PRI_ALIAS_0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA0_0_FUSEDATA_PROCESS_CALIB__PRI_ALIAS_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA0_0_FUSEDATA_IO_CALIB__PRI_ALIAS_0_SHIFT                   _MK_SHIFT_CONST(16)
+#define FUSE_FUSEDATA0_0_FUSEDATA_IO_CALIB__PRI_ALIAS_0_FIELD                   (_MK_MASK_CONST(0x3ff) << FUSE_FUSEDATA0_0_FUSEDATA_IO_CALIB__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA0_0_FUSEDATA_IO_CALIB__PRI_ALIAS_0_RANGE                   25:16
+#define FUSE_FUSEDATA0_0_FUSEDATA_IO_CALIB__PRI_ALIAS_0_WOFFSET                 0x0
+#define FUSE_FUSEDATA0_0_FUSEDATA_IO_CALIB__PRI_ALIAS_0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA0_0_FUSEDATA_IO_CALIB__PRI_ALIAS_0_DEFAULT_MASK                    _MK_MASK_CONST(0x3ff)
+#define FUSE_FUSEDATA0_0_FUSEDATA_IO_CALIB__PRI_ALIAS_0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA0_0_FUSEDATA_IO_CALIB__PRI_ALIAS_0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA0_0_FUSEDATA_DAC_CRT_CALIB__PRI_ALIAS_0_SHIFT                      _MK_SHIFT_CONST(26)
+#define FUSE_FUSEDATA0_0_FUSEDATA_DAC_CRT_CALIB__PRI_ALIAS_0_FIELD                      (_MK_MASK_CONST(0x3f) << FUSE_FUSEDATA0_0_FUSEDATA_DAC_CRT_CALIB__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA0_0_FUSEDATA_DAC_CRT_CALIB__PRI_ALIAS_0_RANGE                      31:26
+#define FUSE_FUSEDATA0_0_FUSEDATA_DAC_CRT_CALIB__PRI_ALIAS_0_WOFFSET                    0x0
+#define FUSE_FUSEDATA0_0_FUSEDATA_DAC_CRT_CALIB__PRI_ALIAS_0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA0_0_FUSEDATA_DAC_CRT_CALIB__PRI_ALIAS_0_DEFAULT_MASK                       _MK_MASK_CONST(0x3f)
+#define FUSE_FUSEDATA0_0_FUSEDATA_DAC_CRT_CALIB__PRI_ALIAS_0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA0_0_FUSEDATA_DAC_CRT_CALIB__PRI_ALIAS_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_FUSEDATA1_0  
+#define FUSE_FUSEDATA1_0                        _MK_ADDR_CONST(0x10)
+#define FUSE_FUSEDATA1_0_WORD_COUNT                     0x1
+#define FUSE_FUSEDATA1_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA1_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA1_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA1_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA1_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA1_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA1_0_FUSEDATA1_SHIFT                        _MK_SHIFT_CONST(0)
+#define FUSE_FUSEDATA1_0_FUSEDATA1_FIELD                        (_MK_MASK_CONST(0xffffffff) << FUSE_FUSEDATA1_0_FUSEDATA1_SHIFT)
+#define FUSE_FUSEDATA1_0_FUSEDATA1_RANGE                        31:0
+#define FUSE_FUSEDATA1_0_FUSEDATA1_WOFFSET                      0x0
+#define FUSE_FUSEDATA1_0_FUSEDATA1_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA1_0_FUSEDATA1_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA1_0_FUSEDATA1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA1_0_FUSEDATA1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA1_0_FUSEDATA_DAC_CRT_CALIB__PRI_ALIAS_1_SHIFT                      _MK_SHIFT_CONST(0)
+#define FUSE_FUSEDATA1_0_FUSEDATA_DAC_CRT_CALIB__PRI_ALIAS_1_FIELD                      (_MK_MASK_CONST(0x3) << FUSE_FUSEDATA1_0_FUSEDATA_DAC_CRT_CALIB__PRI_ALIAS_1_SHIFT)
+#define FUSE_FUSEDATA1_0_FUSEDATA_DAC_CRT_CALIB__PRI_ALIAS_1_RANGE                      1:0
+#define FUSE_FUSEDATA1_0_FUSEDATA_DAC_CRT_CALIB__PRI_ALIAS_1_WOFFSET                    0x0
+#define FUSE_FUSEDATA1_0_FUSEDATA_DAC_CRT_CALIB__PRI_ALIAS_1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA1_0_FUSEDATA_DAC_CRT_CALIB__PRI_ALIAS_1_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define FUSE_FUSEDATA1_0_FUSEDATA_DAC_CRT_CALIB__PRI_ALIAS_1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA1_0_FUSEDATA_DAC_CRT_CALIB__PRI_ALIAS_1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA1_0_FUSEDATA_DAC_HDTV_CALIB__PRI_ALIAS_0_SHIFT                     _MK_SHIFT_CONST(2)
+#define FUSE_FUSEDATA1_0_FUSEDATA_DAC_HDTV_CALIB__PRI_ALIAS_0_FIELD                     (_MK_MASK_CONST(0xff) << FUSE_FUSEDATA1_0_FUSEDATA_DAC_HDTV_CALIB__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA1_0_FUSEDATA_DAC_HDTV_CALIB__PRI_ALIAS_0_RANGE                     9:2
+#define FUSE_FUSEDATA1_0_FUSEDATA_DAC_HDTV_CALIB__PRI_ALIAS_0_WOFFSET                   0x0
+#define FUSE_FUSEDATA1_0_FUSEDATA_DAC_HDTV_CALIB__PRI_ALIAS_0_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA1_0_FUSEDATA_DAC_HDTV_CALIB__PRI_ALIAS_0_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define FUSE_FUSEDATA1_0_FUSEDATA_DAC_HDTV_CALIB__PRI_ALIAS_0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA1_0_FUSEDATA_DAC_HDTV_CALIB__PRI_ALIAS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA1_0_FUSEDATA_DAC_SDTV_CALIB__PRI_ALIAS_0_SHIFT                     _MK_SHIFT_CONST(10)
+#define FUSE_FUSEDATA1_0_FUSEDATA_DAC_SDTV_CALIB__PRI_ALIAS_0_FIELD                     (_MK_MASK_CONST(0xff) << FUSE_FUSEDATA1_0_FUSEDATA_DAC_SDTV_CALIB__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA1_0_FUSEDATA_DAC_SDTV_CALIB__PRI_ALIAS_0_RANGE                     17:10
+#define FUSE_FUSEDATA1_0_FUSEDATA_DAC_SDTV_CALIB__PRI_ALIAS_0_WOFFSET                   0x0
+#define FUSE_FUSEDATA1_0_FUSEDATA_DAC_SDTV_CALIB__PRI_ALIAS_0_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA1_0_FUSEDATA_DAC_SDTV_CALIB__PRI_ALIAS_0_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define FUSE_FUSEDATA1_0_FUSEDATA_DAC_SDTV_CALIB__PRI_ALIAS_0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA1_0_FUSEDATA_DAC_SDTV_CALIB__PRI_ALIAS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA1_0_FUSEDATA_CMC_DATARAM0_0__PRI_ALIAS_0_SHIFT                     _MK_SHIFT_CONST(18)
+#define FUSE_FUSEDATA1_0_FUSEDATA_CMC_DATARAM0_0__PRI_ALIAS_0_FIELD                     (_MK_MASK_CONST(0x7f) << FUSE_FUSEDATA1_0_FUSEDATA_CMC_DATARAM0_0__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA1_0_FUSEDATA_CMC_DATARAM0_0__PRI_ALIAS_0_RANGE                     24:18
+#define FUSE_FUSEDATA1_0_FUSEDATA_CMC_DATARAM0_0__PRI_ALIAS_0_WOFFSET                   0x0
+#define FUSE_FUSEDATA1_0_FUSEDATA_CMC_DATARAM0_0__PRI_ALIAS_0_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA1_0_FUSEDATA_CMC_DATARAM0_0__PRI_ALIAS_0_DEFAULT_MASK                      _MK_MASK_CONST(0x7f)
+#define FUSE_FUSEDATA1_0_FUSEDATA_CMC_DATARAM0_0__PRI_ALIAS_0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA1_0_FUSEDATA_CMC_DATARAM0_0__PRI_ALIAS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA1_0_FUSEDATA_CMC_DATARAM0_1__PRI_ALIAS_0_SHIFT                     _MK_SHIFT_CONST(25)
+#define FUSE_FUSEDATA1_0_FUSEDATA_CMC_DATARAM0_1__PRI_ALIAS_0_FIELD                     (_MK_MASK_CONST(0x7f) << FUSE_FUSEDATA1_0_FUSEDATA_CMC_DATARAM0_1__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA1_0_FUSEDATA_CMC_DATARAM0_1__PRI_ALIAS_0_RANGE                     31:25
+#define FUSE_FUSEDATA1_0_FUSEDATA_CMC_DATARAM0_1__PRI_ALIAS_0_WOFFSET                   0x0
+#define FUSE_FUSEDATA1_0_FUSEDATA_CMC_DATARAM0_1__PRI_ALIAS_0_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA1_0_FUSEDATA_CMC_DATARAM0_1__PRI_ALIAS_0_DEFAULT_MASK                      _MK_MASK_CONST(0x7f)
+#define FUSE_FUSEDATA1_0_FUSEDATA_CMC_DATARAM0_1__PRI_ALIAS_0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA1_0_FUSEDATA_CMC_DATARAM0_1__PRI_ALIAS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_FUSEDATA2_0  
+#define FUSE_FUSEDATA2_0                        _MK_ADDR_CONST(0x14)
+#define FUSE_FUSEDATA2_0_WORD_COUNT                     0x1
+#define FUSE_FUSEDATA2_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA2_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA2_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA2_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA2_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA2_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA2_0_FUSEDATA2_SHIFT                        _MK_SHIFT_CONST(0)
+#define FUSE_FUSEDATA2_0_FUSEDATA2_FIELD                        (_MK_MASK_CONST(0xffffffff) << FUSE_FUSEDATA2_0_FUSEDATA2_SHIFT)
+#define FUSE_FUSEDATA2_0_FUSEDATA2_RANGE                        31:0
+#define FUSE_FUSEDATA2_0_FUSEDATA2_WOFFSET                      0x0
+#define FUSE_FUSEDATA2_0_FUSEDATA2_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA2_0_FUSEDATA2_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA2_0_FUSEDATA2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA2_0_FUSEDATA2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA2_0_FUSEDATA_CMC_DATARAM0_2__PRI_ALIAS_0_SHIFT                     _MK_SHIFT_CONST(0)
+#define FUSE_FUSEDATA2_0_FUSEDATA_CMC_DATARAM0_2__PRI_ALIAS_0_FIELD                     (_MK_MASK_CONST(0x7f) << FUSE_FUSEDATA2_0_FUSEDATA_CMC_DATARAM0_2__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA2_0_FUSEDATA_CMC_DATARAM0_2__PRI_ALIAS_0_RANGE                     6:0
+#define FUSE_FUSEDATA2_0_FUSEDATA_CMC_DATARAM0_2__PRI_ALIAS_0_WOFFSET                   0x0
+#define FUSE_FUSEDATA2_0_FUSEDATA_CMC_DATARAM0_2__PRI_ALIAS_0_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA2_0_FUSEDATA_CMC_DATARAM0_2__PRI_ALIAS_0_DEFAULT_MASK                      _MK_MASK_CONST(0x7f)
+#define FUSE_FUSEDATA2_0_FUSEDATA_CMC_DATARAM0_2__PRI_ALIAS_0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA2_0_FUSEDATA_CMC_DATARAM0_2__PRI_ALIAS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA2_0_FUSEDATA_CMC_DATARAM0_3__PRI_ALIAS_0_SHIFT                     _MK_SHIFT_CONST(7)
+#define FUSE_FUSEDATA2_0_FUSEDATA_CMC_DATARAM0_3__PRI_ALIAS_0_FIELD                     (_MK_MASK_CONST(0x7f) << FUSE_FUSEDATA2_0_FUSEDATA_CMC_DATARAM0_3__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA2_0_FUSEDATA_CMC_DATARAM0_3__PRI_ALIAS_0_RANGE                     13:7
+#define FUSE_FUSEDATA2_0_FUSEDATA_CMC_DATARAM0_3__PRI_ALIAS_0_WOFFSET                   0x0
+#define FUSE_FUSEDATA2_0_FUSEDATA_CMC_DATARAM0_3__PRI_ALIAS_0_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA2_0_FUSEDATA_CMC_DATARAM0_3__PRI_ALIAS_0_DEFAULT_MASK                      _MK_MASK_CONST(0x7f)
+#define FUSE_FUSEDATA2_0_FUSEDATA_CMC_DATARAM0_3__PRI_ALIAS_0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA2_0_FUSEDATA_CMC_DATARAM0_3__PRI_ALIAS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA2_0_FUSEDATA_CMC_DATARAM1_0__PRI_ALIAS_0_SHIFT                     _MK_SHIFT_CONST(14)
+#define FUSE_FUSEDATA2_0_FUSEDATA_CMC_DATARAM1_0__PRI_ALIAS_0_FIELD                     (_MK_MASK_CONST(0x7f) << FUSE_FUSEDATA2_0_FUSEDATA_CMC_DATARAM1_0__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA2_0_FUSEDATA_CMC_DATARAM1_0__PRI_ALIAS_0_RANGE                     20:14
+#define FUSE_FUSEDATA2_0_FUSEDATA_CMC_DATARAM1_0__PRI_ALIAS_0_WOFFSET                   0x0
+#define FUSE_FUSEDATA2_0_FUSEDATA_CMC_DATARAM1_0__PRI_ALIAS_0_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA2_0_FUSEDATA_CMC_DATARAM1_0__PRI_ALIAS_0_DEFAULT_MASK                      _MK_MASK_CONST(0x7f)
+#define FUSE_FUSEDATA2_0_FUSEDATA_CMC_DATARAM1_0__PRI_ALIAS_0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA2_0_FUSEDATA_CMC_DATARAM1_0__PRI_ALIAS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA2_0_FUSEDATA_CMC_DATARAM1_1__PRI_ALIAS_0_SHIFT                     _MK_SHIFT_CONST(21)
+#define FUSE_FUSEDATA2_0_FUSEDATA_CMC_DATARAM1_1__PRI_ALIAS_0_FIELD                     (_MK_MASK_CONST(0x7f) << FUSE_FUSEDATA2_0_FUSEDATA_CMC_DATARAM1_1__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA2_0_FUSEDATA_CMC_DATARAM1_1__PRI_ALIAS_0_RANGE                     27:21
+#define FUSE_FUSEDATA2_0_FUSEDATA_CMC_DATARAM1_1__PRI_ALIAS_0_WOFFSET                   0x0
+#define FUSE_FUSEDATA2_0_FUSEDATA_CMC_DATARAM1_1__PRI_ALIAS_0_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA2_0_FUSEDATA_CMC_DATARAM1_1__PRI_ALIAS_0_DEFAULT_MASK                      _MK_MASK_CONST(0x7f)
+#define FUSE_FUSEDATA2_0_FUSEDATA_CMC_DATARAM1_1__PRI_ALIAS_0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA2_0_FUSEDATA_CMC_DATARAM1_1__PRI_ALIAS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA2_0_FUSEDATA_CMC_DATARAM1_2__PRI_ALIAS_0_SHIFT                     _MK_SHIFT_CONST(28)
+#define FUSE_FUSEDATA2_0_FUSEDATA_CMC_DATARAM1_2__PRI_ALIAS_0_FIELD                     (_MK_MASK_CONST(0xf) << FUSE_FUSEDATA2_0_FUSEDATA_CMC_DATARAM1_2__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA2_0_FUSEDATA_CMC_DATARAM1_2__PRI_ALIAS_0_RANGE                     31:28
+#define FUSE_FUSEDATA2_0_FUSEDATA_CMC_DATARAM1_2__PRI_ALIAS_0_WOFFSET                   0x0
+#define FUSE_FUSEDATA2_0_FUSEDATA_CMC_DATARAM1_2__PRI_ALIAS_0_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA2_0_FUSEDATA_CMC_DATARAM1_2__PRI_ALIAS_0_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define FUSE_FUSEDATA2_0_FUSEDATA_CMC_DATARAM1_2__PRI_ALIAS_0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA2_0_FUSEDATA_CMC_DATARAM1_2__PRI_ALIAS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_FUSEDATA3_0  
+#define FUSE_FUSEDATA3_0                        _MK_ADDR_CONST(0x18)
+#define FUSE_FUSEDATA3_0_WORD_COUNT                     0x1
+#define FUSE_FUSEDATA3_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA3_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA3_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA3_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA3_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA3_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA3_0_FUSEDATA3_SHIFT                        _MK_SHIFT_CONST(0)
+#define FUSE_FUSEDATA3_0_FUSEDATA3_FIELD                        (_MK_MASK_CONST(0xffffffff) << FUSE_FUSEDATA3_0_FUSEDATA3_SHIFT)
+#define FUSE_FUSEDATA3_0_FUSEDATA3_RANGE                        31:0
+#define FUSE_FUSEDATA3_0_FUSEDATA3_WOFFSET                      0x0
+#define FUSE_FUSEDATA3_0_FUSEDATA3_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA3_0_FUSEDATA3_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA3_0_FUSEDATA3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA3_0_FUSEDATA3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA3_0_FUSEDATA_CMC_DATARAM1_2__PRI_ALIAS_1_SHIFT                     _MK_SHIFT_CONST(0)
+#define FUSE_FUSEDATA3_0_FUSEDATA_CMC_DATARAM1_2__PRI_ALIAS_1_FIELD                     (_MK_MASK_CONST(0x7) << FUSE_FUSEDATA3_0_FUSEDATA_CMC_DATARAM1_2__PRI_ALIAS_1_SHIFT)
+#define FUSE_FUSEDATA3_0_FUSEDATA_CMC_DATARAM1_2__PRI_ALIAS_1_RANGE                     2:0
+#define FUSE_FUSEDATA3_0_FUSEDATA_CMC_DATARAM1_2__PRI_ALIAS_1_WOFFSET                   0x0
+#define FUSE_FUSEDATA3_0_FUSEDATA_CMC_DATARAM1_2__PRI_ALIAS_1_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA3_0_FUSEDATA_CMC_DATARAM1_2__PRI_ALIAS_1_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define FUSE_FUSEDATA3_0_FUSEDATA_CMC_DATARAM1_2__PRI_ALIAS_1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA3_0_FUSEDATA_CMC_DATARAM1_2__PRI_ALIAS_1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA3_0_FUSEDATA_CMC_DATARAM1_3__PRI_ALIAS_0_SHIFT                     _MK_SHIFT_CONST(3)
+#define FUSE_FUSEDATA3_0_FUSEDATA_CMC_DATARAM1_3__PRI_ALIAS_0_FIELD                     (_MK_MASK_CONST(0x7f) << FUSE_FUSEDATA3_0_FUSEDATA_CMC_DATARAM1_3__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA3_0_FUSEDATA_CMC_DATARAM1_3__PRI_ALIAS_0_RANGE                     9:3
+#define FUSE_FUSEDATA3_0_FUSEDATA_CMC_DATARAM1_3__PRI_ALIAS_0_WOFFSET                   0x0
+#define FUSE_FUSEDATA3_0_FUSEDATA_CMC_DATARAM1_3__PRI_ALIAS_0_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA3_0_FUSEDATA_CMC_DATARAM1_3__PRI_ALIAS_0_DEFAULT_MASK                      _MK_MASK_CONST(0x7f)
+#define FUSE_FUSEDATA3_0_FUSEDATA_CMC_DATARAM1_3__PRI_ALIAS_0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA3_0_FUSEDATA_CMC_DATARAM1_3__PRI_ALIAS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA3_0_FUSEDATA_FA__PRI_ALIAS_0_SHIFT                 _MK_SHIFT_CONST(10)
+#define FUSE_FUSEDATA3_0_FUSEDATA_FA__PRI_ALIAS_0_FIELD                 (_MK_MASK_CONST(0x1) << FUSE_FUSEDATA3_0_FUSEDATA_FA__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA3_0_FUSEDATA_FA__PRI_ALIAS_0_RANGE                 10:10
+#define FUSE_FUSEDATA3_0_FUSEDATA_FA__PRI_ALIAS_0_WOFFSET                       0x0
+#define FUSE_FUSEDATA3_0_FUSEDATA_FA__PRI_ALIAS_0_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA3_0_FUSEDATA_FA__PRI_ALIAS_0_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_FUSEDATA3_0_FUSEDATA_FA__PRI_ALIAS_0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA3_0_FUSEDATA_FA__PRI_ALIAS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA3_0_FUSEDATA_RESERVED_PRODUCTION__PRI_ALIAS_0_SHIFT                        _MK_SHIFT_CONST(11)
+#define FUSE_FUSEDATA3_0_FUSEDATA_RESERVED_PRODUCTION__PRI_ALIAS_0_FIELD                        (_MK_MASK_CONST(0xf) << FUSE_FUSEDATA3_0_FUSEDATA_RESERVED_PRODUCTION__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA3_0_FUSEDATA_RESERVED_PRODUCTION__PRI_ALIAS_0_RANGE                        14:11
+#define FUSE_FUSEDATA3_0_FUSEDATA_RESERVED_PRODUCTION__PRI_ALIAS_0_WOFFSET                      0x0
+#define FUSE_FUSEDATA3_0_FUSEDATA_RESERVED_PRODUCTION__PRI_ALIAS_0_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA3_0_FUSEDATA_RESERVED_PRODUCTION__PRI_ALIAS_0_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define FUSE_FUSEDATA3_0_FUSEDATA_RESERVED_PRODUCTION__PRI_ALIAS_0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA3_0_FUSEDATA_RESERVED_PRODUCTION__PRI_ALIAS_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA3_0_FUSEDATA_HDMI_LANE0_CALIB__PRI_ALIAS_0_SHIFT                   _MK_SHIFT_CONST(15)
+#define FUSE_FUSEDATA3_0_FUSEDATA_HDMI_LANE0_CALIB__PRI_ALIAS_0_FIELD                   (_MK_MASK_CONST(0x3f) << FUSE_FUSEDATA3_0_FUSEDATA_HDMI_LANE0_CALIB__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA3_0_FUSEDATA_HDMI_LANE0_CALIB__PRI_ALIAS_0_RANGE                   20:15
+#define FUSE_FUSEDATA3_0_FUSEDATA_HDMI_LANE0_CALIB__PRI_ALIAS_0_WOFFSET                 0x0
+#define FUSE_FUSEDATA3_0_FUSEDATA_HDMI_LANE0_CALIB__PRI_ALIAS_0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA3_0_FUSEDATA_HDMI_LANE0_CALIB__PRI_ALIAS_0_DEFAULT_MASK                    _MK_MASK_CONST(0x3f)
+#define FUSE_FUSEDATA3_0_FUSEDATA_HDMI_LANE0_CALIB__PRI_ALIAS_0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA3_0_FUSEDATA_HDMI_LANE0_CALIB__PRI_ALIAS_0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA3_0_FUSEDATA_HDMI_LANE1_CALIB__PRI_ALIAS_0_SHIFT                   _MK_SHIFT_CONST(21)
+#define FUSE_FUSEDATA3_0_FUSEDATA_HDMI_LANE1_CALIB__PRI_ALIAS_0_FIELD                   (_MK_MASK_CONST(0x3f) << FUSE_FUSEDATA3_0_FUSEDATA_HDMI_LANE1_CALIB__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA3_0_FUSEDATA_HDMI_LANE1_CALIB__PRI_ALIAS_0_RANGE                   26:21
+#define FUSE_FUSEDATA3_0_FUSEDATA_HDMI_LANE1_CALIB__PRI_ALIAS_0_WOFFSET                 0x0
+#define FUSE_FUSEDATA3_0_FUSEDATA_HDMI_LANE1_CALIB__PRI_ALIAS_0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA3_0_FUSEDATA_HDMI_LANE1_CALIB__PRI_ALIAS_0_DEFAULT_MASK                    _MK_MASK_CONST(0x3f)
+#define FUSE_FUSEDATA3_0_FUSEDATA_HDMI_LANE1_CALIB__PRI_ALIAS_0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA3_0_FUSEDATA_HDMI_LANE1_CALIB__PRI_ALIAS_0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA3_0_FUSEDATA_HDMI_LANE2_CALIB__PRI_ALIAS_0_SHIFT                   _MK_SHIFT_CONST(27)
+#define FUSE_FUSEDATA3_0_FUSEDATA_HDMI_LANE2_CALIB__PRI_ALIAS_0_FIELD                   (_MK_MASK_CONST(0x1f) << FUSE_FUSEDATA3_0_FUSEDATA_HDMI_LANE2_CALIB__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA3_0_FUSEDATA_HDMI_LANE2_CALIB__PRI_ALIAS_0_RANGE                   31:27
+#define FUSE_FUSEDATA3_0_FUSEDATA_HDMI_LANE2_CALIB__PRI_ALIAS_0_WOFFSET                 0x0
+#define FUSE_FUSEDATA3_0_FUSEDATA_HDMI_LANE2_CALIB__PRI_ALIAS_0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA3_0_FUSEDATA_HDMI_LANE2_CALIB__PRI_ALIAS_0_DEFAULT_MASK                    _MK_MASK_CONST(0x1f)
+#define FUSE_FUSEDATA3_0_FUSEDATA_HDMI_LANE2_CALIB__PRI_ALIAS_0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA3_0_FUSEDATA_HDMI_LANE2_CALIB__PRI_ALIAS_0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_FUSEDATA4_0  
+#define FUSE_FUSEDATA4_0                        _MK_ADDR_CONST(0x1c)
+#define FUSE_FUSEDATA4_0_WORD_COUNT                     0x1
+#define FUSE_FUSEDATA4_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA4_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA4_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA4_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA4_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA4_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA4_0_FUSEDATA4_SHIFT                        _MK_SHIFT_CONST(0)
+#define FUSE_FUSEDATA4_0_FUSEDATA4_FIELD                        (_MK_MASK_CONST(0xffffffff) << FUSE_FUSEDATA4_0_FUSEDATA4_SHIFT)
+#define FUSE_FUSEDATA4_0_FUSEDATA4_RANGE                        31:0
+#define FUSE_FUSEDATA4_0_FUSEDATA4_WOFFSET                      0x0
+#define FUSE_FUSEDATA4_0_FUSEDATA4_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA4_0_FUSEDATA4_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA4_0_FUSEDATA4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA4_0_FUSEDATA4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA4_0_FUSEDATA_HDMI_LANE2_CALIB__PRI_ALIAS_1_SHIFT                   _MK_SHIFT_CONST(0)
+#define FUSE_FUSEDATA4_0_FUSEDATA_HDMI_LANE2_CALIB__PRI_ALIAS_1_FIELD                   (_MK_MASK_CONST(0x1) << FUSE_FUSEDATA4_0_FUSEDATA_HDMI_LANE2_CALIB__PRI_ALIAS_1_SHIFT)
+#define FUSE_FUSEDATA4_0_FUSEDATA_HDMI_LANE2_CALIB__PRI_ALIAS_1_RANGE                   0:0
+#define FUSE_FUSEDATA4_0_FUSEDATA_HDMI_LANE2_CALIB__PRI_ALIAS_1_WOFFSET                 0x0
+#define FUSE_FUSEDATA4_0_FUSEDATA_HDMI_LANE2_CALIB__PRI_ALIAS_1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA4_0_FUSEDATA_HDMI_LANE2_CALIB__PRI_ALIAS_1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FUSE_FUSEDATA4_0_FUSEDATA_HDMI_LANE2_CALIB__PRI_ALIAS_1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA4_0_FUSEDATA_HDMI_LANE2_CALIB__PRI_ALIAS_1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA4_0_FUSEDATA_HDMI_LANE3_CALIB__PRI_ALIAS_0_SHIFT                   _MK_SHIFT_CONST(1)
+#define FUSE_FUSEDATA4_0_FUSEDATA_HDMI_LANE3_CALIB__PRI_ALIAS_0_FIELD                   (_MK_MASK_CONST(0x3f) << FUSE_FUSEDATA4_0_FUSEDATA_HDMI_LANE3_CALIB__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA4_0_FUSEDATA_HDMI_LANE3_CALIB__PRI_ALIAS_0_RANGE                   6:1
+#define FUSE_FUSEDATA4_0_FUSEDATA_HDMI_LANE3_CALIB__PRI_ALIAS_0_WOFFSET                 0x0
+#define FUSE_FUSEDATA4_0_FUSEDATA_HDMI_LANE3_CALIB__PRI_ALIAS_0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA4_0_FUSEDATA_HDMI_LANE3_CALIB__PRI_ALIAS_0_DEFAULT_MASK                    _MK_MASK_CONST(0x3f)
+#define FUSE_FUSEDATA4_0_FUSEDATA_HDMI_LANE3_CALIB__PRI_ALIAS_0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA4_0_FUSEDATA_HDMI_LANE3_CALIB__PRI_ALIAS_0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA4_0_FUSEDATA_SECURITY_MODE__PRI_ALIAS_0_SHIFT                      _MK_SHIFT_CONST(7)
+#define FUSE_FUSEDATA4_0_FUSEDATA_SECURITY_MODE__PRI_ALIAS_0_FIELD                      (_MK_MASK_CONST(0x1) << FUSE_FUSEDATA4_0_FUSEDATA_SECURITY_MODE__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA4_0_FUSEDATA_SECURITY_MODE__PRI_ALIAS_0_RANGE                      7:7
+#define FUSE_FUSEDATA4_0_FUSEDATA_SECURITY_MODE__PRI_ALIAS_0_WOFFSET                    0x0
+#define FUSE_FUSEDATA4_0_FUSEDATA_SECURITY_MODE__PRI_ALIAS_0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA4_0_FUSEDATA_SECURITY_MODE__PRI_ALIAS_0_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FUSE_FUSEDATA4_0_FUSEDATA_SECURITY_MODE__PRI_ALIAS_0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA4_0_FUSEDATA_SECURITY_MODE__PRI_ALIAS_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA4_0_FUSEDATA_PRIVATE_KEY0__PRI_ALIAS_0_SHIFT                       _MK_SHIFT_CONST(8)
+#define FUSE_FUSEDATA4_0_FUSEDATA_PRIVATE_KEY0__PRI_ALIAS_0_FIELD                       (_MK_MASK_CONST(0xffffff) << FUSE_FUSEDATA4_0_FUSEDATA_PRIVATE_KEY0__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA4_0_FUSEDATA_PRIVATE_KEY0__PRI_ALIAS_0_RANGE                       31:8
+#define FUSE_FUSEDATA4_0_FUSEDATA_PRIVATE_KEY0__PRI_ALIAS_0_WOFFSET                     0x0
+#define FUSE_FUSEDATA4_0_FUSEDATA_PRIVATE_KEY0__PRI_ALIAS_0_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA4_0_FUSEDATA_PRIVATE_KEY0__PRI_ALIAS_0_DEFAULT_MASK                        _MK_MASK_CONST(0xffffff)
+#define FUSE_FUSEDATA4_0_FUSEDATA_PRIVATE_KEY0__PRI_ALIAS_0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA4_0_FUSEDATA_PRIVATE_KEY0__PRI_ALIAS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_FUSEDATA5_0  
+#define FUSE_FUSEDATA5_0                        _MK_ADDR_CONST(0x20)
+#define FUSE_FUSEDATA5_0_WORD_COUNT                     0x1
+#define FUSE_FUSEDATA5_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA5_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA5_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA5_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA5_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA5_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA5_0_FUSEDATA5_SHIFT                        _MK_SHIFT_CONST(0)
+#define FUSE_FUSEDATA5_0_FUSEDATA5_FIELD                        (_MK_MASK_CONST(0xffffffff) << FUSE_FUSEDATA5_0_FUSEDATA5_SHIFT)
+#define FUSE_FUSEDATA5_0_FUSEDATA5_RANGE                        31:0
+#define FUSE_FUSEDATA5_0_FUSEDATA5_WOFFSET                      0x0
+#define FUSE_FUSEDATA5_0_FUSEDATA5_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA5_0_FUSEDATA5_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA5_0_FUSEDATA5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA5_0_FUSEDATA5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA5_0_FUSEDATA_PRIVATE_KEY0__PRI_ALIAS_1_SHIFT                       _MK_SHIFT_CONST(0)
+#define FUSE_FUSEDATA5_0_FUSEDATA_PRIVATE_KEY0__PRI_ALIAS_1_FIELD                       (_MK_MASK_CONST(0xff) << FUSE_FUSEDATA5_0_FUSEDATA_PRIVATE_KEY0__PRI_ALIAS_1_SHIFT)
+#define FUSE_FUSEDATA5_0_FUSEDATA_PRIVATE_KEY0__PRI_ALIAS_1_RANGE                       7:0
+#define FUSE_FUSEDATA5_0_FUSEDATA_PRIVATE_KEY0__PRI_ALIAS_1_WOFFSET                     0x0
+#define FUSE_FUSEDATA5_0_FUSEDATA_PRIVATE_KEY0__PRI_ALIAS_1_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA5_0_FUSEDATA_PRIVATE_KEY0__PRI_ALIAS_1_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define FUSE_FUSEDATA5_0_FUSEDATA_PRIVATE_KEY0__PRI_ALIAS_1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA5_0_FUSEDATA_PRIVATE_KEY0__PRI_ALIAS_1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA5_0_FUSEDATA_PRIVATE_KEY1__PRI_ALIAS_0_SHIFT                       _MK_SHIFT_CONST(8)
+#define FUSE_FUSEDATA5_0_FUSEDATA_PRIVATE_KEY1__PRI_ALIAS_0_FIELD                       (_MK_MASK_CONST(0xffffff) << FUSE_FUSEDATA5_0_FUSEDATA_PRIVATE_KEY1__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA5_0_FUSEDATA_PRIVATE_KEY1__PRI_ALIAS_0_RANGE                       31:8
+#define FUSE_FUSEDATA5_0_FUSEDATA_PRIVATE_KEY1__PRI_ALIAS_0_WOFFSET                     0x0
+#define FUSE_FUSEDATA5_0_FUSEDATA_PRIVATE_KEY1__PRI_ALIAS_0_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA5_0_FUSEDATA_PRIVATE_KEY1__PRI_ALIAS_0_DEFAULT_MASK                        _MK_MASK_CONST(0xffffff)
+#define FUSE_FUSEDATA5_0_FUSEDATA_PRIVATE_KEY1__PRI_ALIAS_0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA5_0_FUSEDATA_PRIVATE_KEY1__PRI_ALIAS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_FUSEDATA6_0  
+#define FUSE_FUSEDATA6_0                        _MK_ADDR_CONST(0x24)
+#define FUSE_FUSEDATA6_0_WORD_COUNT                     0x1
+#define FUSE_FUSEDATA6_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA6_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA6_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA6_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA6_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA6_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA6_0_FUSEDATA6_SHIFT                        _MK_SHIFT_CONST(0)
+#define FUSE_FUSEDATA6_0_FUSEDATA6_FIELD                        (_MK_MASK_CONST(0xffffffff) << FUSE_FUSEDATA6_0_FUSEDATA6_SHIFT)
+#define FUSE_FUSEDATA6_0_FUSEDATA6_RANGE                        31:0
+#define FUSE_FUSEDATA6_0_FUSEDATA6_WOFFSET                      0x0
+#define FUSE_FUSEDATA6_0_FUSEDATA6_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA6_0_FUSEDATA6_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA6_0_FUSEDATA6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA6_0_FUSEDATA6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA6_0_FUSEDATA_PRIVATE_KEY1__PRI_ALIAS_1_SHIFT                       _MK_SHIFT_CONST(0)
+#define FUSE_FUSEDATA6_0_FUSEDATA_PRIVATE_KEY1__PRI_ALIAS_1_FIELD                       (_MK_MASK_CONST(0xff) << FUSE_FUSEDATA6_0_FUSEDATA_PRIVATE_KEY1__PRI_ALIAS_1_SHIFT)
+#define FUSE_FUSEDATA6_0_FUSEDATA_PRIVATE_KEY1__PRI_ALIAS_1_RANGE                       7:0
+#define FUSE_FUSEDATA6_0_FUSEDATA_PRIVATE_KEY1__PRI_ALIAS_1_WOFFSET                     0x0
+#define FUSE_FUSEDATA6_0_FUSEDATA_PRIVATE_KEY1__PRI_ALIAS_1_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA6_0_FUSEDATA_PRIVATE_KEY1__PRI_ALIAS_1_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define FUSE_FUSEDATA6_0_FUSEDATA_PRIVATE_KEY1__PRI_ALIAS_1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA6_0_FUSEDATA_PRIVATE_KEY1__PRI_ALIAS_1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA6_0_FUSEDATA_PRIVATE_KEY2__PRI_ALIAS_0_SHIFT                       _MK_SHIFT_CONST(8)
+#define FUSE_FUSEDATA6_0_FUSEDATA_PRIVATE_KEY2__PRI_ALIAS_0_FIELD                       (_MK_MASK_CONST(0xffffff) << FUSE_FUSEDATA6_0_FUSEDATA_PRIVATE_KEY2__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA6_0_FUSEDATA_PRIVATE_KEY2__PRI_ALIAS_0_RANGE                       31:8
+#define FUSE_FUSEDATA6_0_FUSEDATA_PRIVATE_KEY2__PRI_ALIAS_0_WOFFSET                     0x0
+#define FUSE_FUSEDATA6_0_FUSEDATA_PRIVATE_KEY2__PRI_ALIAS_0_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA6_0_FUSEDATA_PRIVATE_KEY2__PRI_ALIAS_0_DEFAULT_MASK                        _MK_MASK_CONST(0xffffff)
+#define FUSE_FUSEDATA6_0_FUSEDATA_PRIVATE_KEY2__PRI_ALIAS_0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA6_0_FUSEDATA_PRIVATE_KEY2__PRI_ALIAS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_FUSEDATA7_0  
+#define FUSE_FUSEDATA7_0                        _MK_ADDR_CONST(0x28)
+#define FUSE_FUSEDATA7_0_WORD_COUNT                     0x1
+#define FUSE_FUSEDATA7_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA7_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA7_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA7_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA7_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA7_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA7_0_FUSEDATA7_SHIFT                        _MK_SHIFT_CONST(0)
+#define FUSE_FUSEDATA7_0_FUSEDATA7_FIELD                        (_MK_MASK_CONST(0xffffffff) << FUSE_FUSEDATA7_0_FUSEDATA7_SHIFT)
+#define FUSE_FUSEDATA7_0_FUSEDATA7_RANGE                        31:0
+#define FUSE_FUSEDATA7_0_FUSEDATA7_WOFFSET                      0x0
+#define FUSE_FUSEDATA7_0_FUSEDATA7_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA7_0_FUSEDATA7_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA7_0_FUSEDATA7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA7_0_FUSEDATA7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA7_0_FUSEDATA_PRIVATE_KEY2__PRI_ALIAS_1_SHIFT                       _MK_SHIFT_CONST(0)
+#define FUSE_FUSEDATA7_0_FUSEDATA_PRIVATE_KEY2__PRI_ALIAS_1_FIELD                       (_MK_MASK_CONST(0xff) << FUSE_FUSEDATA7_0_FUSEDATA_PRIVATE_KEY2__PRI_ALIAS_1_SHIFT)
+#define FUSE_FUSEDATA7_0_FUSEDATA_PRIVATE_KEY2__PRI_ALIAS_1_RANGE                       7:0
+#define FUSE_FUSEDATA7_0_FUSEDATA_PRIVATE_KEY2__PRI_ALIAS_1_WOFFSET                     0x0
+#define FUSE_FUSEDATA7_0_FUSEDATA_PRIVATE_KEY2__PRI_ALIAS_1_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA7_0_FUSEDATA_PRIVATE_KEY2__PRI_ALIAS_1_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define FUSE_FUSEDATA7_0_FUSEDATA_PRIVATE_KEY2__PRI_ALIAS_1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA7_0_FUSEDATA_PRIVATE_KEY2__PRI_ALIAS_1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA7_0_FUSEDATA_PRIVATE_KEY3__PRI_ALIAS_0_SHIFT                       _MK_SHIFT_CONST(8)
+#define FUSE_FUSEDATA7_0_FUSEDATA_PRIVATE_KEY3__PRI_ALIAS_0_FIELD                       (_MK_MASK_CONST(0xffffff) << FUSE_FUSEDATA7_0_FUSEDATA_PRIVATE_KEY3__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA7_0_FUSEDATA_PRIVATE_KEY3__PRI_ALIAS_0_RANGE                       31:8
+#define FUSE_FUSEDATA7_0_FUSEDATA_PRIVATE_KEY3__PRI_ALIAS_0_WOFFSET                     0x0
+#define FUSE_FUSEDATA7_0_FUSEDATA_PRIVATE_KEY3__PRI_ALIAS_0_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA7_0_FUSEDATA_PRIVATE_KEY3__PRI_ALIAS_0_DEFAULT_MASK                        _MK_MASK_CONST(0xffffff)
+#define FUSE_FUSEDATA7_0_FUSEDATA_PRIVATE_KEY3__PRI_ALIAS_0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA7_0_FUSEDATA_PRIVATE_KEY3__PRI_ALIAS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_FUSEDATA8_0  
+#define FUSE_FUSEDATA8_0                        _MK_ADDR_CONST(0x2c)
+#define FUSE_FUSEDATA8_0_WORD_COUNT                     0x1
+#define FUSE_FUSEDATA8_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA8_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA8_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA8_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA8_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA8_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA8_0_FUSEDATA8_SHIFT                        _MK_SHIFT_CONST(0)
+#define FUSE_FUSEDATA8_0_FUSEDATA8_FIELD                        (_MK_MASK_CONST(0xffffffff) << FUSE_FUSEDATA8_0_FUSEDATA8_SHIFT)
+#define FUSE_FUSEDATA8_0_FUSEDATA8_RANGE                        31:0
+#define FUSE_FUSEDATA8_0_FUSEDATA8_WOFFSET                      0x0
+#define FUSE_FUSEDATA8_0_FUSEDATA8_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA8_0_FUSEDATA8_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA8_0_FUSEDATA8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA8_0_FUSEDATA8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA8_0_FUSEDATA_PRIVATE_KEY3__PRI_ALIAS_1_SHIFT                       _MK_SHIFT_CONST(0)
+#define FUSE_FUSEDATA8_0_FUSEDATA_PRIVATE_KEY3__PRI_ALIAS_1_FIELD                       (_MK_MASK_CONST(0xff) << FUSE_FUSEDATA8_0_FUSEDATA_PRIVATE_KEY3__PRI_ALIAS_1_SHIFT)
+#define FUSE_FUSEDATA8_0_FUSEDATA_PRIVATE_KEY3__PRI_ALIAS_1_RANGE                       7:0
+#define FUSE_FUSEDATA8_0_FUSEDATA_PRIVATE_KEY3__PRI_ALIAS_1_WOFFSET                     0x0
+#define FUSE_FUSEDATA8_0_FUSEDATA_PRIVATE_KEY3__PRI_ALIAS_1_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA8_0_FUSEDATA_PRIVATE_KEY3__PRI_ALIAS_1_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define FUSE_FUSEDATA8_0_FUSEDATA_PRIVATE_KEY3__PRI_ALIAS_1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA8_0_FUSEDATA_PRIVATE_KEY3__PRI_ALIAS_1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA8_0_FUSEDATA_PRIVATE_KEY4__PRI_ALIAS_0_SHIFT                       _MK_SHIFT_CONST(8)
+#define FUSE_FUSEDATA8_0_FUSEDATA_PRIVATE_KEY4__PRI_ALIAS_0_FIELD                       (_MK_MASK_CONST(0xffffff) << FUSE_FUSEDATA8_0_FUSEDATA_PRIVATE_KEY4__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA8_0_FUSEDATA_PRIVATE_KEY4__PRI_ALIAS_0_RANGE                       31:8
+#define FUSE_FUSEDATA8_0_FUSEDATA_PRIVATE_KEY4__PRI_ALIAS_0_WOFFSET                     0x0
+#define FUSE_FUSEDATA8_0_FUSEDATA_PRIVATE_KEY4__PRI_ALIAS_0_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA8_0_FUSEDATA_PRIVATE_KEY4__PRI_ALIAS_0_DEFAULT_MASK                        _MK_MASK_CONST(0xffffff)
+#define FUSE_FUSEDATA8_0_FUSEDATA_PRIVATE_KEY4__PRI_ALIAS_0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA8_0_FUSEDATA_PRIVATE_KEY4__PRI_ALIAS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_FUSEDATA9_0  
+#define FUSE_FUSEDATA9_0                        _MK_ADDR_CONST(0x30)
+#define FUSE_FUSEDATA9_0_WORD_COUNT                     0x1
+#define FUSE_FUSEDATA9_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA9_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA9_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA9_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA9_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA9_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA9_0_FUSEDATA9_SHIFT                        _MK_SHIFT_CONST(0)
+#define FUSE_FUSEDATA9_0_FUSEDATA9_FIELD                        (_MK_MASK_CONST(0xffffffff) << FUSE_FUSEDATA9_0_FUSEDATA9_SHIFT)
+#define FUSE_FUSEDATA9_0_FUSEDATA9_RANGE                        31:0
+#define FUSE_FUSEDATA9_0_FUSEDATA9_WOFFSET                      0x0
+#define FUSE_FUSEDATA9_0_FUSEDATA9_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA9_0_FUSEDATA9_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA9_0_FUSEDATA9_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA9_0_FUSEDATA9_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA9_0_FUSEDATA_MASTER_ENABLE__RED_ALIAS_0_SHIFT                      _MK_SHIFT_CONST(24)
+#define FUSE_FUSEDATA9_0_FUSEDATA_MASTER_ENABLE__RED_ALIAS_0_FIELD                      (_MK_MASK_CONST(0x1) << FUSE_FUSEDATA9_0_FUSEDATA_MASTER_ENABLE__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA9_0_FUSEDATA_MASTER_ENABLE__RED_ALIAS_0_RANGE                      24:24
+#define FUSE_FUSEDATA9_0_FUSEDATA_MASTER_ENABLE__RED_ALIAS_0_WOFFSET                    0x0
+#define FUSE_FUSEDATA9_0_FUSEDATA_MASTER_ENABLE__RED_ALIAS_0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA9_0_FUSEDATA_MASTER_ENABLE__RED_ALIAS_0_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FUSE_FUSEDATA9_0_FUSEDATA_MASTER_ENABLE__RED_ALIAS_0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA9_0_FUSEDATA_MASTER_ENABLE__RED_ALIAS_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA9_0_FUSEDATA_MASTER_DISABLE__RED_ALIAS_0_SHIFT                     _MK_SHIFT_CONST(25)
+#define FUSE_FUSEDATA9_0_FUSEDATA_MASTER_DISABLE__RED_ALIAS_0_FIELD                     (_MK_MASK_CONST(0x1) << FUSE_FUSEDATA9_0_FUSEDATA_MASTER_DISABLE__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA9_0_FUSEDATA_MASTER_DISABLE__RED_ALIAS_0_RANGE                     25:25
+#define FUSE_FUSEDATA9_0_FUSEDATA_MASTER_DISABLE__RED_ALIAS_0_WOFFSET                   0x0
+#define FUSE_FUSEDATA9_0_FUSEDATA_MASTER_DISABLE__RED_ALIAS_0_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA9_0_FUSEDATA_MASTER_DISABLE__RED_ALIAS_0_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FUSE_FUSEDATA9_0_FUSEDATA_MASTER_DISABLE__RED_ALIAS_0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA9_0_FUSEDATA_MASTER_DISABLE__RED_ALIAS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA9_0_FUSEDATA_BYPASS__RED_ALIAS_0_SHIFT                     _MK_SHIFT_CONST(26)
+#define FUSE_FUSEDATA9_0_FUSEDATA_BYPASS__RED_ALIAS_0_FIELD                     (_MK_MASK_CONST(0x1) << FUSE_FUSEDATA9_0_FUSEDATA_BYPASS__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA9_0_FUSEDATA_BYPASS__RED_ALIAS_0_RANGE                     26:26
+#define FUSE_FUSEDATA9_0_FUSEDATA_BYPASS__RED_ALIAS_0_WOFFSET                   0x0
+#define FUSE_FUSEDATA9_0_FUSEDATA_BYPASS__RED_ALIAS_0_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA9_0_FUSEDATA_BYPASS__RED_ALIAS_0_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FUSE_FUSEDATA9_0_FUSEDATA_BYPASS__RED_ALIAS_0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA9_0_FUSEDATA_BYPASS__RED_ALIAS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA9_0_FUSEDATA_RESERVE_BIT__RED_ALIAS_0_SHIFT                        _MK_SHIFT_CONST(27)
+#define FUSE_FUSEDATA9_0_FUSEDATA_RESERVE_BIT__RED_ALIAS_0_FIELD                        (_MK_MASK_CONST(0x1) << FUSE_FUSEDATA9_0_FUSEDATA_RESERVE_BIT__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA9_0_FUSEDATA_RESERVE_BIT__RED_ALIAS_0_RANGE                        27:27
+#define FUSE_FUSEDATA9_0_FUSEDATA_RESERVE_BIT__RED_ALIAS_0_WOFFSET                      0x0
+#define FUSE_FUSEDATA9_0_FUSEDATA_RESERVE_BIT__RED_ALIAS_0_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA9_0_FUSEDATA_RESERVE_BIT__RED_ALIAS_0_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define FUSE_FUSEDATA9_0_FUSEDATA_RESERVE_BIT__RED_ALIAS_0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA9_0_FUSEDATA_RESERVE_BIT__RED_ALIAS_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA9_0_FUSEDATA_PRODUCTION_MODE__RED_ALIAS_0_SHIFT                    _MK_SHIFT_CONST(28)
+#define FUSE_FUSEDATA9_0_FUSEDATA_PRODUCTION_MODE__RED_ALIAS_0_FIELD                    (_MK_MASK_CONST(0x1) << FUSE_FUSEDATA9_0_FUSEDATA_PRODUCTION_MODE__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA9_0_FUSEDATA_PRODUCTION_MODE__RED_ALIAS_0_RANGE                    28:28
+#define FUSE_FUSEDATA9_0_FUSEDATA_PRODUCTION_MODE__RED_ALIAS_0_WOFFSET                  0x0
+#define FUSE_FUSEDATA9_0_FUSEDATA_PRODUCTION_MODE__RED_ALIAS_0_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA9_0_FUSEDATA_PRODUCTION_MODE__RED_ALIAS_0_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FUSE_FUSEDATA9_0_FUSEDATA_PRODUCTION_MODE__RED_ALIAS_0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA9_0_FUSEDATA_PRODUCTION_MODE__RED_ALIAS_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA9_0_FUSEDATA_JTAG_SECUREID_VALID__RED_ALIAS_0_SHIFT                        _MK_SHIFT_CONST(29)
+#define FUSE_FUSEDATA9_0_FUSEDATA_JTAG_SECUREID_VALID__RED_ALIAS_0_FIELD                        (_MK_MASK_CONST(0x1) << FUSE_FUSEDATA9_0_FUSEDATA_JTAG_SECUREID_VALID__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA9_0_FUSEDATA_JTAG_SECUREID_VALID__RED_ALIAS_0_RANGE                        29:29
+#define FUSE_FUSEDATA9_0_FUSEDATA_JTAG_SECUREID_VALID__RED_ALIAS_0_WOFFSET                      0x0
+#define FUSE_FUSEDATA9_0_FUSEDATA_JTAG_SECUREID_VALID__RED_ALIAS_0_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA9_0_FUSEDATA_JTAG_SECUREID_VALID__RED_ALIAS_0_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define FUSE_FUSEDATA9_0_FUSEDATA_JTAG_SECUREID_VALID__RED_ALIAS_0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA9_0_FUSEDATA_JTAG_SECUREID_VALID__RED_ALIAS_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA9_0_FUSEDATA_SKU_INFO__RED_ALIAS_0_SHIFT                   _MK_SHIFT_CONST(30)
+#define FUSE_FUSEDATA9_0_FUSEDATA_SKU_INFO__RED_ALIAS_0_FIELD                   (_MK_MASK_CONST(0x3) << FUSE_FUSEDATA9_0_FUSEDATA_SKU_INFO__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA9_0_FUSEDATA_SKU_INFO__RED_ALIAS_0_RANGE                   31:30
+#define FUSE_FUSEDATA9_0_FUSEDATA_SKU_INFO__RED_ALIAS_0_WOFFSET                 0x0
+#define FUSE_FUSEDATA9_0_FUSEDATA_SKU_INFO__RED_ALIAS_0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA9_0_FUSEDATA_SKU_INFO__RED_ALIAS_0_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define FUSE_FUSEDATA9_0_FUSEDATA_SKU_INFO__RED_ALIAS_0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA9_0_FUSEDATA_SKU_INFO__RED_ALIAS_0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA9_0_FUSEDATA_PRIVATE_KEY4__PRI_ALIAS_1_SHIFT                       _MK_SHIFT_CONST(0)
+#define FUSE_FUSEDATA9_0_FUSEDATA_PRIVATE_KEY4__PRI_ALIAS_1_FIELD                       (_MK_MASK_CONST(0xff) << FUSE_FUSEDATA9_0_FUSEDATA_PRIVATE_KEY4__PRI_ALIAS_1_SHIFT)
+#define FUSE_FUSEDATA9_0_FUSEDATA_PRIVATE_KEY4__PRI_ALIAS_1_RANGE                       7:0
+#define FUSE_FUSEDATA9_0_FUSEDATA_PRIVATE_KEY4__PRI_ALIAS_1_WOFFSET                     0x0
+#define FUSE_FUSEDATA9_0_FUSEDATA_PRIVATE_KEY4__PRI_ALIAS_1_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA9_0_FUSEDATA_PRIVATE_KEY4__PRI_ALIAS_1_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define FUSE_FUSEDATA9_0_FUSEDATA_PRIVATE_KEY4__PRI_ALIAS_1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA9_0_FUSEDATA_PRIVATE_KEY4__PRI_ALIAS_1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA9_0_FUSEDATA_ARM_JTAG_DIS__PRI_ALIAS_0_SHIFT                       _MK_SHIFT_CONST(8)
+#define FUSE_FUSEDATA9_0_FUSEDATA_ARM_JTAG_DIS__PRI_ALIAS_0_FIELD                       (_MK_MASK_CONST(0x1) << FUSE_FUSEDATA9_0_FUSEDATA_ARM_JTAG_DIS__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA9_0_FUSEDATA_ARM_JTAG_DIS__PRI_ALIAS_0_RANGE                       8:8
+#define FUSE_FUSEDATA9_0_FUSEDATA_ARM_JTAG_DIS__PRI_ALIAS_0_WOFFSET                     0x0
+#define FUSE_FUSEDATA9_0_FUSEDATA_ARM_JTAG_DIS__PRI_ALIAS_0_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA9_0_FUSEDATA_ARM_JTAG_DIS__PRI_ALIAS_0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FUSE_FUSEDATA9_0_FUSEDATA_ARM_JTAG_DIS__PRI_ALIAS_0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA9_0_FUSEDATA_ARM_JTAG_DIS__PRI_ALIAS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA9_0_FUSEDATA_BOOT_DEVICE_INFO__PRI_ALIAS_0_SHIFT                   _MK_SHIFT_CONST(9)
+#define FUSE_FUSEDATA9_0_FUSEDATA_BOOT_DEVICE_INFO__PRI_ALIAS_0_FIELD                   (_MK_MASK_CONST(0x7f) << FUSE_FUSEDATA9_0_FUSEDATA_BOOT_DEVICE_INFO__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA9_0_FUSEDATA_BOOT_DEVICE_INFO__PRI_ALIAS_0_RANGE                   15:9
+#define FUSE_FUSEDATA9_0_FUSEDATA_BOOT_DEVICE_INFO__PRI_ALIAS_0_WOFFSET                 0x0
+#define FUSE_FUSEDATA9_0_FUSEDATA_BOOT_DEVICE_INFO__PRI_ALIAS_0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA9_0_FUSEDATA_BOOT_DEVICE_INFO__PRI_ALIAS_0_DEFAULT_MASK                    _MK_MASK_CONST(0x7f)
+#define FUSE_FUSEDATA9_0_FUSEDATA_BOOT_DEVICE_INFO__PRI_ALIAS_0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA9_0_FUSEDATA_BOOT_DEVICE_INFO__PRI_ALIAS_0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA9_0_FUSEDATA_RESERVED_SW__PRI_ALIAS_0_SHIFT                        _MK_SHIFT_CONST(16)
+#define FUSE_FUSEDATA9_0_FUSEDATA_RESERVED_SW__PRI_ALIAS_0_FIELD                        (_MK_MASK_CONST(0xff) << FUSE_FUSEDATA9_0_FUSEDATA_RESERVED_SW__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA9_0_FUSEDATA_RESERVED_SW__PRI_ALIAS_0_RANGE                        23:16
+#define FUSE_FUSEDATA9_0_FUSEDATA_RESERVED_SW__PRI_ALIAS_0_WOFFSET                      0x0
+#define FUSE_FUSEDATA9_0_FUSEDATA_RESERVED_SW__PRI_ALIAS_0_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA9_0_FUSEDATA_RESERVED_SW__PRI_ALIAS_0_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
+#define FUSE_FUSEDATA9_0_FUSEDATA_RESERVED_SW__PRI_ALIAS_0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA9_0_FUSEDATA_RESERVED_SW__PRI_ALIAS_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_FUSEDATA10_0  
+#define FUSE_FUSEDATA10_0                       _MK_ADDR_CONST(0x34)
+#define FUSE_FUSEDATA10_0_WORD_COUNT                    0x1
+#define FUSE_FUSEDATA10_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA10_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA10_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA10_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA10_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA10_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA10_0_FUSEDATA10_SHIFT                      _MK_SHIFT_CONST(0)
+#define FUSE_FUSEDATA10_0_FUSEDATA10_FIELD                      (_MK_MASK_CONST(0xffffffff) << FUSE_FUSEDATA10_0_FUSEDATA10_SHIFT)
+#define FUSE_FUSEDATA10_0_FUSEDATA10_RANGE                      31:0
+#define FUSE_FUSEDATA10_0_FUSEDATA10_WOFFSET                    0x0
+#define FUSE_FUSEDATA10_0_FUSEDATA10_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA10_0_FUSEDATA10_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA10_0_FUSEDATA10_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA10_0_FUSEDATA10_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA10_0_FUSEDATA_SKU_INFO__RED_ALIAS_1_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_FUSEDATA10_0_FUSEDATA_SKU_INFO__RED_ALIAS_1_FIELD                  (_MK_MASK_CONST(0x3f) << FUSE_FUSEDATA10_0_FUSEDATA_SKU_INFO__RED_ALIAS_1_SHIFT)
+#define FUSE_FUSEDATA10_0_FUSEDATA_SKU_INFO__RED_ALIAS_1_RANGE                  5:0
+#define FUSE_FUSEDATA10_0_FUSEDATA_SKU_INFO__RED_ALIAS_1_WOFFSET                        0x0
+#define FUSE_FUSEDATA10_0_FUSEDATA_SKU_INFO__RED_ALIAS_1_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA10_0_FUSEDATA_SKU_INFO__RED_ALIAS_1_DEFAULT_MASK                   _MK_MASK_CONST(0x3f)
+#define FUSE_FUSEDATA10_0_FUSEDATA_SKU_INFO__RED_ALIAS_1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA10_0_FUSEDATA_SKU_INFO__RED_ALIAS_1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA10_0_FUSEDATA_PROCESS_CALIB__RED_ALIAS_0_SHIFT                     _MK_SHIFT_CONST(6)
+#define FUSE_FUSEDATA10_0_FUSEDATA_PROCESS_CALIB__RED_ALIAS_0_FIELD                     (_MK_MASK_CONST(0x3) << FUSE_FUSEDATA10_0_FUSEDATA_PROCESS_CALIB__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA10_0_FUSEDATA_PROCESS_CALIB__RED_ALIAS_0_RANGE                     7:6
+#define FUSE_FUSEDATA10_0_FUSEDATA_PROCESS_CALIB__RED_ALIAS_0_WOFFSET                   0x0
+#define FUSE_FUSEDATA10_0_FUSEDATA_PROCESS_CALIB__RED_ALIAS_0_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA10_0_FUSEDATA_PROCESS_CALIB__RED_ALIAS_0_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define FUSE_FUSEDATA10_0_FUSEDATA_PROCESS_CALIB__RED_ALIAS_0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA10_0_FUSEDATA_PROCESS_CALIB__RED_ALIAS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA10_0_FUSEDATA_IO_CALIB__RED_ALIAS_0_SHIFT                  _MK_SHIFT_CONST(8)
+#define FUSE_FUSEDATA10_0_FUSEDATA_IO_CALIB__RED_ALIAS_0_FIELD                  (_MK_MASK_CONST(0x3ff) << FUSE_FUSEDATA10_0_FUSEDATA_IO_CALIB__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA10_0_FUSEDATA_IO_CALIB__RED_ALIAS_0_RANGE                  17:8
+#define FUSE_FUSEDATA10_0_FUSEDATA_IO_CALIB__RED_ALIAS_0_WOFFSET                        0x0
+#define FUSE_FUSEDATA10_0_FUSEDATA_IO_CALIB__RED_ALIAS_0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA10_0_FUSEDATA_IO_CALIB__RED_ALIAS_0_DEFAULT_MASK                   _MK_MASK_CONST(0x3ff)
+#define FUSE_FUSEDATA10_0_FUSEDATA_IO_CALIB__RED_ALIAS_0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA10_0_FUSEDATA_IO_CALIB__RED_ALIAS_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA10_0_FUSEDATA_DAC_CRT_CALIB__RED_ALIAS_0_SHIFT                     _MK_SHIFT_CONST(18)
+#define FUSE_FUSEDATA10_0_FUSEDATA_DAC_CRT_CALIB__RED_ALIAS_0_FIELD                     (_MK_MASK_CONST(0xff) << FUSE_FUSEDATA10_0_FUSEDATA_DAC_CRT_CALIB__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA10_0_FUSEDATA_DAC_CRT_CALIB__RED_ALIAS_0_RANGE                     25:18
+#define FUSE_FUSEDATA10_0_FUSEDATA_DAC_CRT_CALIB__RED_ALIAS_0_WOFFSET                   0x0
+#define FUSE_FUSEDATA10_0_FUSEDATA_DAC_CRT_CALIB__RED_ALIAS_0_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA10_0_FUSEDATA_DAC_CRT_CALIB__RED_ALIAS_0_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define FUSE_FUSEDATA10_0_FUSEDATA_DAC_CRT_CALIB__RED_ALIAS_0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA10_0_FUSEDATA_DAC_CRT_CALIB__RED_ALIAS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA10_0_FUSEDATA_DAC_HDTV_CALIB__RED_ALIAS_0_SHIFT                    _MK_SHIFT_CONST(26)
+#define FUSE_FUSEDATA10_0_FUSEDATA_DAC_HDTV_CALIB__RED_ALIAS_0_FIELD                    (_MK_MASK_CONST(0x3f) << FUSE_FUSEDATA10_0_FUSEDATA_DAC_HDTV_CALIB__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA10_0_FUSEDATA_DAC_HDTV_CALIB__RED_ALIAS_0_RANGE                    31:26
+#define FUSE_FUSEDATA10_0_FUSEDATA_DAC_HDTV_CALIB__RED_ALIAS_0_WOFFSET                  0x0
+#define FUSE_FUSEDATA10_0_FUSEDATA_DAC_HDTV_CALIB__RED_ALIAS_0_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA10_0_FUSEDATA_DAC_HDTV_CALIB__RED_ALIAS_0_DEFAULT_MASK                     _MK_MASK_CONST(0x3f)
+#define FUSE_FUSEDATA10_0_FUSEDATA_DAC_HDTV_CALIB__RED_ALIAS_0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA10_0_FUSEDATA_DAC_HDTV_CALIB__RED_ALIAS_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_FUSEDATA11_0  
+#define FUSE_FUSEDATA11_0                       _MK_ADDR_CONST(0x38)
+#define FUSE_FUSEDATA11_0_WORD_COUNT                    0x1
+#define FUSE_FUSEDATA11_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA11_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA11_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA11_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA11_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA11_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA11_0_FUSEDATA11_SHIFT                      _MK_SHIFT_CONST(0)
+#define FUSE_FUSEDATA11_0_FUSEDATA11_FIELD                      (_MK_MASK_CONST(0xffffffff) << FUSE_FUSEDATA11_0_FUSEDATA11_SHIFT)
+#define FUSE_FUSEDATA11_0_FUSEDATA11_RANGE                      31:0
+#define FUSE_FUSEDATA11_0_FUSEDATA11_WOFFSET                    0x0
+#define FUSE_FUSEDATA11_0_FUSEDATA11_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA11_0_FUSEDATA11_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA11_0_FUSEDATA11_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA11_0_FUSEDATA11_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA11_0_FUSEDATA_DAC_HDTV_CALIB__RED_ALIAS_1_SHIFT                    _MK_SHIFT_CONST(0)
+#define FUSE_FUSEDATA11_0_FUSEDATA_DAC_HDTV_CALIB__RED_ALIAS_1_FIELD                    (_MK_MASK_CONST(0x3) << FUSE_FUSEDATA11_0_FUSEDATA_DAC_HDTV_CALIB__RED_ALIAS_1_SHIFT)
+#define FUSE_FUSEDATA11_0_FUSEDATA_DAC_HDTV_CALIB__RED_ALIAS_1_RANGE                    1:0
+#define FUSE_FUSEDATA11_0_FUSEDATA_DAC_HDTV_CALIB__RED_ALIAS_1_WOFFSET                  0x0
+#define FUSE_FUSEDATA11_0_FUSEDATA_DAC_HDTV_CALIB__RED_ALIAS_1_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA11_0_FUSEDATA_DAC_HDTV_CALIB__RED_ALIAS_1_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define FUSE_FUSEDATA11_0_FUSEDATA_DAC_HDTV_CALIB__RED_ALIAS_1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA11_0_FUSEDATA_DAC_HDTV_CALIB__RED_ALIAS_1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA11_0_FUSEDATA_DAC_SDTV_CALIB__RED_ALIAS_0_SHIFT                    _MK_SHIFT_CONST(2)
+#define FUSE_FUSEDATA11_0_FUSEDATA_DAC_SDTV_CALIB__RED_ALIAS_0_FIELD                    (_MK_MASK_CONST(0xff) << FUSE_FUSEDATA11_0_FUSEDATA_DAC_SDTV_CALIB__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA11_0_FUSEDATA_DAC_SDTV_CALIB__RED_ALIAS_0_RANGE                    9:2
+#define FUSE_FUSEDATA11_0_FUSEDATA_DAC_SDTV_CALIB__RED_ALIAS_0_WOFFSET                  0x0
+#define FUSE_FUSEDATA11_0_FUSEDATA_DAC_SDTV_CALIB__RED_ALIAS_0_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA11_0_FUSEDATA_DAC_SDTV_CALIB__RED_ALIAS_0_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
+#define FUSE_FUSEDATA11_0_FUSEDATA_DAC_SDTV_CALIB__RED_ALIAS_0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA11_0_FUSEDATA_DAC_SDTV_CALIB__RED_ALIAS_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA11_0_FUSEDATA_CMC_DATARAM0_0__RED_ALIAS_0_SHIFT                    _MK_SHIFT_CONST(10)
+#define FUSE_FUSEDATA11_0_FUSEDATA_CMC_DATARAM0_0__RED_ALIAS_0_FIELD                    (_MK_MASK_CONST(0x7f) << FUSE_FUSEDATA11_0_FUSEDATA_CMC_DATARAM0_0__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA11_0_FUSEDATA_CMC_DATARAM0_0__RED_ALIAS_0_RANGE                    16:10
+#define FUSE_FUSEDATA11_0_FUSEDATA_CMC_DATARAM0_0__RED_ALIAS_0_WOFFSET                  0x0
+#define FUSE_FUSEDATA11_0_FUSEDATA_CMC_DATARAM0_0__RED_ALIAS_0_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA11_0_FUSEDATA_CMC_DATARAM0_0__RED_ALIAS_0_DEFAULT_MASK                     _MK_MASK_CONST(0x7f)
+#define FUSE_FUSEDATA11_0_FUSEDATA_CMC_DATARAM0_0__RED_ALIAS_0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA11_0_FUSEDATA_CMC_DATARAM0_0__RED_ALIAS_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA11_0_FUSEDATA_CMC_DATARAM0_1__RED_ALIAS_0_SHIFT                    _MK_SHIFT_CONST(17)
+#define FUSE_FUSEDATA11_0_FUSEDATA_CMC_DATARAM0_1__RED_ALIAS_0_FIELD                    (_MK_MASK_CONST(0x7f) << FUSE_FUSEDATA11_0_FUSEDATA_CMC_DATARAM0_1__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA11_0_FUSEDATA_CMC_DATARAM0_1__RED_ALIAS_0_RANGE                    23:17
+#define FUSE_FUSEDATA11_0_FUSEDATA_CMC_DATARAM0_1__RED_ALIAS_0_WOFFSET                  0x0
+#define FUSE_FUSEDATA11_0_FUSEDATA_CMC_DATARAM0_1__RED_ALIAS_0_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA11_0_FUSEDATA_CMC_DATARAM0_1__RED_ALIAS_0_DEFAULT_MASK                     _MK_MASK_CONST(0x7f)
+#define FUSE_FUSEDATA11_0_FUSEDATA_CMC_DATARAM0_1__RED_ALIAS_0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA11_0_FUSEDATA_CMC_DATARAM0_1__RED_ALIAS_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA11_0_FUSEDATA_CMC_DATARAM0_2__RED_ALIAS_0_SHIFT                    _MK_SHIFT_CONST(24)
+#define FUSE_FUSEDATA11_0_FUSEDATA_CMC_DATARAM0_2__RED_ALIAS_0_FIELD                    (_MK_MASK_CONST(0x7f) << FUSE_FUSEDATA11_0_FUSEDATA_CMC_DATARAM0_2__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA11_0_FUSEDATA_CMC_DATARAM0_2__RED_ALIAS_0_RANGE                    30:24
+#define FUSE_FUSEDATA11_0_FUSEDATA_CMC_DATARAM0_2__RED_ALIAS_0_WOFFSET                  0x0
+#define FUSE_FUSEDATA11_0_FUSEDATA_CMC_DATARAM0_2__RED_ALIAS_0_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA11_0_FUSEDATA_CMC_DATARAM0_2__RED_ALIAS_0_DEFAULT_MASK                     _MK_MASK_CONST(0x7f)
+#define FUSE_FUSEDATA11_0_FUSEDATA_CMC_DATARAM0_2__RED_ALIAS_0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA11_0_FUSEDATA_CMC_DATARAM0_2__RED_ALIAS_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA11_0_FUSEDATA_CMC_DATARAM0_3__RED_ALIAS_0_SHIFT                    _MK_SHIFT_CONST(31)
+#define FUSE_FUSEDATA11_0_FUSEDATA_CMC_DATARAM0_3__RED_ALIAS_0_FIELD                    (_MK_MASK_CONST(0x1) << FUSE_FUSEDATA11_0_FUSEDATA_CMC_DATARAM0_3__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA11_0_FUSEDATA_CMC_DATARAM0_3__RED_ALIAS_0_RANGE                    31:31
+#define FUSE_FUSEDATA11_0_FUSEDATA_CMC_DATARAM0_3__RED_ALIAS_0_WOFFSET                  0x0
+#define FUSE_FUSEDATA11_0_FUSEDATA_CMC_DATARAM0_3__RED_ALIAS_0_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA11_0_FUSEDATA_CMC_DATARAM0_3__RED_ALIAS_0_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FUSE_FUSEDATA11_0_FUSEDATA_CMC_DATARAM0_3__RED_ALIAS_0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA11_0_FUSEDATA_CMC_DATARAM0_3__RED_ALIAS_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_FUSEDATA12_0  
+#define FUSE_FUSEDATA12_0                       _MK_ADDR_CONST(0x3c)
+#define FUSE_FUSEDATA12_0_WORD_COUNT                    0x1
+#define FUSE_FUSEDATA12_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA12_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA12_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA12_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA12_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA12_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA12_0_FUSEDATA12_SHIFT                      _MK_SHIFT_CONST(0)
+#define FUSE_FUSEDATA12_0_FUSEDATA12_FIELD                      (_MK_MASK_CONST(0xffffffff) << FUSE_FUSEDATA12_0_FUSEDATA12_SHIFT)
+#define FUSE_FUSEDATA12_0_FUSEDATA12_RANGE                      31:0
+#define FUSE_FUSEDATA12_0_FUSEDATA12_WOFFSET                    0x0
+#define FUSE_FUSEDATA12_0_FUSEDATA12_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA12_0_FUSEDATA12_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA12_0_FUSEDATA12_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA12_0_FUSEDATA12_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA12_0_FUSEDATA_CMC_DATARAM0_3__RED_ALIAS_1_SHIFT                    _MK_SHIFT_CONST(0)
+#define FUSE_FUSEDATA12_0_FUSEDATA_CMC_DATARAM0_3__RED_ALIAS_1_FIELD                    (_MK_MASK_CONST(0x3f) << FUSE_FUSEDATA12_0_FUSEDATA_CMC_DATARAM0_3__RED_ALIAS_1_SHIFT)
+#define FUSE_FUSEDATA12_0_FUSEDATA_CMC_DATARAM0_3__RED_ALIAS_1_RANGE                    5:0
+#define FUSE_FUSEDATA12_0_FUSEDATA_CMC_DATARAM0_3__RED_ALIAS_1_WOFFSET                  0x0
+#define FUSE_FUSEDATA12_0_FUSEDATA_CMC_DATARAM0_3__RED_ALIAS_1_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA12_0_FUSEDATA_CMC_DATARAM0_3__RED_ALIAS_1_DEFAULT_MASK                     _MK_MASK_CONST(0x3f)
+#define FUSE_FUSEDATA12_0_FUSEDATA_CMC_DATARAM0_3__RED_ALIAS_1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA12_0_FUSEDATA_CMC_DATARAM0_3__RED_ALIAS_1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA12_0_FUSEDATA_CMC_DATARAM1_0__RED_ALIAS_0_SHIFT                    _MK_SHIFT_CONST(6)
+#define FUSE_FUSEDATA12_0_FUSEDATA_CMC_DATARAM1_0__RED_ALIAS_0_FIELD                    (_MK_MASK_CONST(0x7f) << FUSE_FUSEDATA12_0_FUSEDATA_CMC_DATARAM1_0__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA12_0_FUSEDATA_CMC_DATARAM1_0__RED_ALIAS_0_RANGE                    12:6
+#define FUSE_FUSEDATA12_0_FUSEDATA_CMC_DATARAM1_0__RED_ALIAS_0_WOFFSET                  0x0
+#define FUSE_FUSEDATA12_0_FUSEDATA_CMC_DATARAM1_0__RED_ALIAS_0_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA12_0_FUSEDATA_CMC_DATARAM1_0__RED_ALIAS_0_DEFAULT_MASK                     _MK_MASK_CONST(0x7f)
+#define FUSE_FUSEDATA12_0_FUSEDATA_CMC_DATARAM1_0__RED_ALIAS_0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA12_0_FUSEDATA_CMC_DATARAM1_0__RED_ALIAS_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA12_0_FUSEDATA_CMC_DATARAM1_1__RED_ALIAS_0_SHIFT                    _MK_SHIFT_CONST(13)
+#define FUSE_FUSEDATA12_0_FUSEDATA_CMC_DATARAM1_1__RED_ALIAS_0_FIELD                    (_MK_MASK_CONST(0x7f) << FUSE_FUSEDATA12_0_FUSEDATA_CMC_DATARAM1_1__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA12_0_FUSEDATA_CMC_DATARAM1_1__RED_ALIAS_0_RANGE                    19:13
+#define FUSE_FUSEDATA12_0_FUSEDATA_CMC_DATARAM1_1__RED_ALIAS_0_WOFFSET                  0x0
+#define FUSE_FUSEDATA12_0_FUSEDATA_CMC_DATARAM1_1__RED_ALIAS_0_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA12_0_FUSEDATA_CMC_DATARAM1_1__RED_ALIAS_0_DEFAULT_MASK                     _MK_MASK_CONST(0x7f)
+#define FUSE_FUSEDATA12_0_FUSEDATA_CMC_DATARAM1_1__RED_ALIAS_0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA12_0_FUSEDATA_CMC_DATARAM1_1__RED_ALIAS_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA12_0_FUSEDATA_CMC_DATARAM1_2__RED_ALIAS_0_SHIFT                    _MK_SHIFT_CONST(20)
+#define FUSE_FUSEDATA12_0_FUSEDATA_CMC_DATARAM1_2__RED_ALIAS_0_FIELD                    (_MK_MASK_CONST(0x7f) << FUSE_FUSEDATA12_0_FUSEDATA_CMC_DATARAM1_2__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA12_0_FUSEDATA_CMC_DATARAM1_2__RED_ALIAS_0_RANGE                    26:20
+#define FUSE_FUSEDATA12_0_FUSEDATA_CMC_DATARAM1_2__RED_ALIAS_0_WOFFSET                  0x0
+#define FUSE_FUSEDATA12_0_FUSEDATA_CMC_DATARAM1_2__RED_ALIAS_0_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA12_0_FUSEDATA_CMC_DATARAM1_2__RED_ALIAS_0_DEFAULT_MASK                     _MK_MASK_CONST(0x7f)
+#define FUSE_FUSEDATA12_0_FUSEDATA_CMC_DATARAM1_2__RED_ALIAS_0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA12_0_FUSEDATA_CMC_DATARAM1_2__RED_ALIAS_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA12_0_FUSEDATA_CMC_DATARAM1_3__RED_ALIAS_0_SHIFT                    _MK_SHIFT_CONST(27)
+#define FUSE_FUSEDATA12_0_FUSEDATA_CMC_DATARAM1_3__RED_ALIAS_0_FIELD                    (_MK_MASK_CONST(0x1f) << FUSE_FUSEDATA12_0_FUSEDATA_CMC_DATARAM1_3__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA12_0_FUSEDATA_CMC_DATARAM1_3__RED_ALIAS_0_RANGE                    31:27
+#define FUSE_FUSEDATA12_0_FUSEDATA_CMC_DATARAM1_3__RED_ALIAS_0_WOFFSET                  0x0
+#define FUSE_FUSEDATA12_0_FUSEDATA_CMC_DATARAM1_3__RED_ALIAS_0_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA12_0_FUSEDATA_CMC_DATARAM1_3__RED_ALIAS_0_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define FUSE_FUSEDATA12_0_FUSEDATA_CMC_DATARAM1_3__RED_ALIAS_0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA12_0_FUSEDATA_CMC_DATARAM1_3__RED_ALIAS_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_FUSEDATA13_0  
+#define FUSE_FUSEDATA13_0                       _MK_ADDR_CONST(0x40)
+#define FUSE_FUSEDATA13_0_WORD_COUNT                    0x1
+#define FUSE_FUSEDATA13_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA13_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA13_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA13_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA13_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA13_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA13_0_FUSEDATA13_SHIFT                      _MK_SHIFT_CONST(0)
+#define FUSE_FUSEDATA13_0_FUSEDATA13_FIELD                      (_MK_MASK_CONST(0xffffffff) << FUSE_FUSEDATA13_0_FUSEDATA13_SHIFT)
+#define FUSE_FUSEDATA13_0_FUSEDATA13_RANGE                      31:0
+#define FUSE_FUSEDATA13_0_FUSEDATA13_WOFFSET                    0x0
+#define FUSE_FUSEDATA13_0_FUSEDATA13_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA13_0_FUSEDATA13_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA13_0_FUSEDATA13_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA13_0_FUSEDATA13_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA13_0_FUSEDATA_CMC_DATARAM1_3__RED_ALIAS_1_SHIFT                    _MK_SHIFT_CONST(0)
+#define FUSE_FUSEDATA13_0_FUSEDATA_CMC_DATARAM1_3__RED_ALIAS_1_FIELD                    (_MK_MASK_CONST(0x3) << FUSE_FUSEDATA13_0_FUSEDATA_CMC_DATARAM1_3__RED_ALIAS_1_SHIFT)
+#define FUSE_FUSEDATA13_0_FUSEDATA_CMC_DATARAM1_3__RED_ALIAS_1_RANGE                    1:0
+#define FUSE_FUSEDATA13_0_FUSEDATA_CMC_DATARAM1_3__RED_ALIAS_1_WOFFSET                  0x0
+#define FUSE_FUSEDATA13_0_FUSEDATA_CMC_DATARAM1_3__RED_ALIAS_1_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA13_0_FUSEDATA_CMC_DATARAM1_3__RED_ALIAS_1_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define FUSE_FUSEDATA13_0_FUSEDATA_CMC_DATARAM1_3__RED_ALIAS_1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA13_0_FUSEDATA_CMC_DATARAM1_3__RED_ALIAS_1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA13_0_FUSEDATA_FA__RED_ALIAS_0_SHIFT                        _MK_SHIFT_CONST(2)
+#define FUSE_FUSEDATA13_0_FUSEDATA_FA__RED_ALIAS_0_FIELD                        (_MK_MASK_CONST(0x1) << FUSE_FUSEDATA13_0_FUSEDATA_FA__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA13_0_FUSEDATA_FA__RED_ALIAS_0_RANGE                        2:2
+#define FUSE_FUSEDATA13_0_FUSEDATA_FA__RED_ALIAS_0_WOFFSET                      0x0
+#define FUSE_FUSEDATA13_0_FUSEDATA_FA__RED_ALIAS_0_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA13_0_FUSEDATA_FA__RED_ALIAS_0_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define FUSE_FUSEDATA13_0_FUSEDATA_FA__RED_ALIAS_0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA13_0_FUSEDATA_FA__RED_ALIAS_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA13_0_FUSEDATA_RESERVED_PRODUCTION__RED_ALIAS_0_SHIFT                       _MK_SHIFT_CONST(3)
+#define FUSE_FUSEDATA13_0_FUSEDATA_RESERVED_PRODUCTION__RED_ALIAS_0_FIELD                       (_MK_MASK_CONST(0xf) << FUSE_FUSEDATA13_0_FUSEDATA_RESERVED_PRODUCTION__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA13_0_FUSEDATA_RESERVED_PRODUCTION__RED_ALIAS_0_RANGE                       6:3
+#define FUSE_FUSEDATA13_0_FUSEDATA_RESERVED_PRODUCTION__RED_ALIAS_0_WOFFSET                     0x0
+#define FUSE_FUSEDATA13_0_FUSEDATA_RESERVED_PRODUCTION__RED_ALIAS_0_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA13_0_FUSEDATA_RESERVED_PRODUCTION__RED_ALIAS_0_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define FUSE_FUSEDATA13_0_FUSEDATA_RESERVED_PRODUCTION__RED_ALIAS_0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA13_0_FUSEDATA_RESERVED_PRODUCTION__RED_ALIAS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA13_0_FUSEDATA_HDMI_LANE0_CALIB__RED_ALIAS_0_SHIFT                  _MK_SHIFT_CONST(7)
+#define FUSE_FUSEDATA13_0_FUSEDATA_HDMI_LANE0_CALIB__RED_ALIAS_0_FIELD                  (_MK_MASK_CONST(0x3f) << FUSE_FUSEDATA13_0_FUSEDATA_HDMI_LANE0_CALIB__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA13_0_FUSEDATA_HDMI_LANE0_CALIB__RED_ALIAS_0_RANGE                  12:7
+#define FUSE_FUSEDATA13_0_FUSEDATA_HDMI_LANE0_CALIB__RED_ALIAS_0_WOFFSET                        0x0
+#define FUSE_FUSEDATA13_0_FUSEDATA_HDMI_LANE0_CALIB__RED_ALIAS_0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA13_0_FUSEDATA_HDMI_LANE0_CALIB__RED_ALIAS_0_DEFAULT_MASK                   _MK_MASK_CONST(0x3f)
+#define FUSE_FUSEDATA13_0_FUSEDATA_HDMI_LANE0_CALIB__RED_ALIAS_0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA13_0_FUSEDATA_HDMI_LANE0_CALIB__RED_ALIAS_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA13_0_FUSEDATA_HDMI_LANE1_CALIB__RED_ALIAS_0_SHIFT                  _MK_SHIFT_CONST(13)
+#define FUSE_FUSEDATA13_0_FUSEDATA_HDMI_LANE1_CALIB__RED_ALIAS_0_FIELD                  (_MK_MASK_CONST(0x3f) << FUSE_FUSEDATA13_0_FUSEDATA_HDMI_LANE1_CALIB__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA13_0_FUSEDATA_HDMI_LANE1_CALIB__RED_ALIAS_0_RANGE                  18:13
+#define FUSE_FUSEDATA13_0_FUSEDATA_HDMI_LANE1_CALIB__RED_ALIAS_0_WOFFSET                        0x0
+#define FUSE_FUSEDATA13_0_FUSEDATA_HDMI_LANE1_CALIB__RED_ALIAS_0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA13_0_FUSEDATA_HDMI_LANE1_CALIB__RED_ALIAS_0_DEFAULT_MASK                   _MK_MASK_CONST(0x3f)
+#define FUSE_FUSEDATA13_0_FUSEDATA_HDMI_LANE1_CALIB__RED_ALIAS_0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA13_0_FUSEDATA_HDMI_LANE1_CALIB__RED_ALIAS_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA13_0_FUSEDATA_HDMI_LANE2_CALIB__RED_ALIAS_0_SHIFT                  _MK_SHIFT_CONST(19)
+#define FUSE_FUSEDATA13_0_FUSEDATA_HDMI_LANE2_CALIB__RED_ALIAS_0_FIELD                  (_MK_MASK_CONST(0x3f) << FUSE_FUSEDATA13_0_FUSEDATA_HDMI_LANE2_CALIB__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA13_0_FUSEDATA_HDMI_LANE2_CALIB__RED_ALIAS_0_RANGE                  24:19
+#define FUSE_FUSEDATA13_0_FUSEDATA_HDMI_LANE2_CALIB__RED_ALIAS_0_WOFFSET                        0x0
+#define FUSE_FUSEDATA13_0_FUSEDATA_HDMI_LANE2_CALIB__RED_ALIAS_0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA13_0_FUSEDATA_HDMI_LANE2_CALIB__RED_ALIAS_0_DEFAULT_MASK                   _MK_MASK_CONST(0x3f)
+#define FUSE_FUSEDATA13_0_FUSEDATA_HDMI_LANE2_CALIB__RED_ALIAS_0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA13_0_FUSEDATA_HDMI_LANE2_CALIB__RED_ALIAS_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA13_0_FUSEDATA_HDMI_LANE3_CALIB__RED_ALIAS_0_SHIFT                  _MK_SHIFT_CONST(25)
+#define FUSE_FUSEDATA13_0_FUSEDATA_HDMI_LANE3_CALIB__RED_ALIAS_0_FIELD                  (_MK_MASK_CONST(0x3f) << FUSE_FUSEDATA13_0_FUSEDATA_HDMI_LANE3_CALIB__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA13_0_FUSEDATA_HDMI_LANE3_CALIB__RED_ALIAS_0_RANGE                  30:25
+#define FUSE_FUSEDATA13_0_FUSEDATA_HDMI_LANE3_CALIB__RED_ALIAS_0_WOFFSET                        0x0
+#define FUSE_FUSEDATA13_0_FUSEDATA_HDMI_LANE3_CALIB__RED_ALIAS_0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA13_0_FUSEDATA_HDMI_LANE3_CALIB__RED_ALIAS_0_DEFAULT_MASK                   _MK_MASK_CONST(0x3f)
+#define FUSE_FUSEDATA13_0_FUSEDATA_HDMI_LANE3_CALIB__RED_ALIAS_0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA13_0_FUSEDATA_HDMI_LANE3_CALIB__RED_ALIAS_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA13_0_FUSEDATA_SECURITY_MODE__RED_ALIAS_0_SHIFT                     _MK_SHIFT_CONST(31)
+#define FUSE_FUSEDATA13_0_FUSEDATA_SECURITY_MODE__RED_ALIAS_0_FIELD                     (_MK_MASK_CONST(0x1) << FUSE_FUSEDATA13_0_FUSEDATA_SECURITY_MODE__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA13_0_FUSEDATA_SECURITY_MODE__RED_ALIAS_0_RANGE                     31:31
+#define FUSE_FUSEDATA13_0_FUSEDATA_SECURITY_MODE__RED_ALIAS_0_WOFFSET                   0x0
+#define FUSE_FUSEDATA13_0_FUSEDATA_SECURITY_MODE__RED_ALIAS_0_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA13_0_FUSEDATA_SECURITY_MODE__RED_ALIAS_0_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FUSE_FUSEDATA13_0_FUSEDATA_SECURITY_MODE__RED_ALIAS_0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA13_0_FUSEDATA_SECURITY_MODE__RED_ALIAS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_FUSEDATA14_0  
+#define FUSE_FUSEDATA14_0                       _MK_ADDR_CONST(0x44)
+#define FUSE_FUSEDATA14_0_WORD_COUNT                    0x1
+#define FUSE_FUSEDATA14_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA14_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA14_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA14_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA14_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA14_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA14_0_FUSEDATA14_SHIFT                      _MK_SHIFT_CONST(0)
+#define FUSE_FUSEDATA14_0_FUSEDATA14_FIELD                      (_MK_MASK_CONST(0xffffffff) << FUSE_FUSEDATA14_0_FUSEDATA14_SHIFT)
+#define FUSE_FUSEDATA14_0_FUSEDATA14_RANGE                      31:0
+#define FUSE_FUSEDATA14_0_FUSEDATA14_WOFFSET                    0x0
+#define FUSE_FUSEDATA14_0_FUSEDATA14_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA14_0_FUSEDATA14_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA14_0_FUSEDATA14_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA14_0_FUSEDATA14_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA14_0_FUSEDATA_PRIVATE_KEY0__RED_ALIAS_0_SHIFT                      _MK_SHIFT_CONST(0)
+#define FUSE_FUSEDATA14_0_FUSEDATA_PRIVATE_KEY0__RED_ALIAS_0_FIELD                      (_MK_MASK_CONST(0xffffffff) << FUSE_FUSEDATA14_0_FUSEDATA_PRIVATE_KEY0__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA14_0_FUSEDATA_PRIVATE_KEY0__RED_ALIAS_0_RANGE                      31:0
+#define FUSE_FUSEDATA14_0_FUSEDATA_PRIVATE_KEY0__RED_ALIAS_0_WOFFSET                    0x0
+#define FUSE_FUSEDATA14_0_FUSEDATA_PRIVATE_KEY0__RED_ALIAS_0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA14_0_FUSEDATA_PRIVATE_KEY0__RED_ALIAS_0_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA14_0_FUSEDATA_PRIVATE_KEY0__RED_ALIAS_0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA14_0_FUSEDATA_PRIVATE_KEY0__RED_ALIAS_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_FUSEDATA15_0  
+#define FUSE_FUSEDATA15_0                       _MK_ADDR_CONST(0x48)
+#define FUSE_FUSEDATA15_0_WORD_COUNT                    0x1
+#define FUSE_FUSEDATA15_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA15_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA15_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA15_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA15_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA15_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA15_0_FUSEDATA15_SHIFT                      _MK_SHIFT_CONST(0)
+#define FUSE_FUSEDATA15_0_FUSEDATA15_FIELD                      (_MK_MASK_CONST(0xffffffff) << FUSE_FUSEDATA15_0_FUSEDATA15_SHIFT)
+#define FUSE_FUSEDATA15_0_FUSEDATA15_RANGE                      31:0
+#define FUSE_FUSEDATA15_0_FUSEDATA15_WOFFSET                    0x0
+#define FUSE_FUSEDATA15_0_FUSEDATA15_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA15_0_FUSEDATA15_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA15_0_FUSEDATA15_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA15_0_FUSEDATA15_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA15_0_FUSEDATA_PRIVATE_KEY1__RED_ALIAS_0_SHIFT                      _MK_SHIFT_CONST(0)
+#define FUSE_FUSEDATA15_0_FUSEDATA_PRIVATE_KEY1__RED_ALIAS_0_FIELD                      (_MK_MASK_CONST(0xffffffff) << FUSE_FUSEDATA15_0_FUSEDATA_PRIVATE_KEY1__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA15_0_FUSEDATA_PRIVATE_KEY1__RED_ALIAS_0_RANGE                      31:0
+#define FUSE_FUSEDATA15_0_FUSEDATA_PRIVATE_KEY1__RED_ALIAS_0_WOFFSET                    0x0
+#define FUSE_FUSEDATA15_0_FUSEDATA_PRIVATE_KEY1__RED_ALIAS_0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA15_0_FUSEDATA_PRIVATE_KEY1__RED_ALIAS_0_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA15_0_FUSEDATA_PRIVATE_KEY1__RED_ALIAS_0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA15_0_FUSEDATA_PRIVATE_KEY1__RED_ALIAS_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_FUSEDATA16_0  
+#define FUSE_FUSEDATA16_0                       _MK_ADDR_CONST(0x4c)
+#define FUSE_FUSEDATA16_0_WORD_COUNT                    0x1
+#define FUSE_FUSEDATA16_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA16_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA16_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA16_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA16_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA16_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA16_0_FUSEDATA16_SHIFT                      _MK_SHIFT_CONST(0)
+#define FUSE_FUSEDATA16_0_FUSEDATA16_FIELD                      (_MK_MASK_CONST(0xffffffff) << FUSE_FUSEDATA16_0_FUSEDATA16_SHIFT)
+#define FUSE_FUSEDATA16_0_FUSEDATA16_RANGE                      31:0
+#define FUSE_FUSEDATA16_0_FUSEDATA16_WOFFSET                    0x0
+#define FUSE_FUSEDATA16_0_FUSEDATA16_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA16_0_FUSEDATA16_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA16_0_FUSEDATA16_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA16_0_FUSEDATA16_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA16_0_FUSEDATA_PRIVATE_KEY2__RED_ALIAS_0_SHIFT                      _MK_SHIFT_CONST(0)
+#define FUSE_FUSEDATA16_0_FUSEDATA_PRIVATE_KEY2__RED_ALIAS_0_FIELD                      (_MK_MASK_CONST(0xffffffff) << FUSE_FUSEDATA16_0_FUSEDATA_PRIVATE_KEY2__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA16_0_FUSEDATA_PRIVATE_KEY2__RED_ALIAS_0_RANGE                      31:0
+#define FUSE_FUSEDATA16_0_FUSEDATA_PRIVATE_KEY2__RED_ALIAS_0_WOFFSET                    0x0
+#define FUSE_FUSEDATA16_0_FUSEDATA_PRIVATE_KEY2__RED_ALIAS_0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA16_0_FUSEDATA_PRIVATE_KEY2__RED_ALIAS_0_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA16_0_FUSEDATA_PRIVATE_KEY2__RED_ALIAS_0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA16_0_FUSEDATA_PRIVATE_KEY2__RED_ALIAS_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_FUSEDATA17_0  
+#define FUSE_FUSEDATA17_0                       _MK_ADDR_CONST(0x50)
+#define FUSE_FUSEDATA17_0_WORD_COUNT                    0x1
+#define FUSE_FUSEDATA17_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA17_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA17_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA17_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA17_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA17_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA17_0_FUSEDATA17_SHIFT                      _MK_SHIFT_CONST(0)
+#define FUSE_FUSEDATA17_0_FUSEDATA17_FIELD                      (_MK_MASK_CONST(0xffffffff) << FUSE_FUSEDATA17_0_FUSEDATA17_SHIFT)
+#define FUSE_FUSEDATA17_0_FUSEDATA17_RANGE                      31:0
+#define FUSE_FUSEDATA17_0_FUSEDATA17_WOFFSET                    0x0
+#define FUSE_FUSEDATA17_0_FUSEDATA17_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA17_0_FUSEDATA17_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA17_0_FUSEDATA17_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA17_0_FUSEDATA17_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA17_0_FUSEDATA_PRIVATE_KEY3__RED_ALIAS_0_SHIFT                      _MK_SHIFT_CONST(0)
+#define FUSE_FUSEDATA17_0_FUSEDATA_PRIVATE_KEY3__RED_ALIAS_0_FIELD                      (_MK_MASK_CONST(0xffffffff) << FUSE_FUSEDATA17_0_FUSEDATA_PRIVATE_KEY3__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA17_0_FUSEDATA_PRIVATE_KEY3__RED_ALIAS_0_RANGE                      31:0
+#define FUSE_FUSEDATA17_0_FUSEDATA_PRIVATE_KEY3__RED_ALIAS_0_WOFFSET                    0x0
+#define FUSE_FUSEDATA17_0_FUSEDATA_PRIVATE_KEY3__RED_ALIAS_0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA17_0_FUSEDATA_PRIVATE_KEY3__RED_ALIAS_0_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA17_0_FUSEDATA_PRIVATE_KEY3__RED_ALIAS_0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA17_0_FUSEDATA_PRIVATE_KEY3__RED_ALIAS_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_FUSEDATA18_0  
+#define FUSE_FUSEDATA18_0                       _MK_ADDR_CONST(0x54)
+#define FUSE_FUSEDATA18_0_WORD_COUNT                    0x1
+#define FUSE_FUSEDATA18_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA18_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA18_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA18_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA18_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA18_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA18_0_FUSEDATA18_SHIFT                      _MK_SHIFT_CONST(0)
+#define FUSE_FUSEDATA18_0_FUSEDATA18_FIELD                      (_MK_MASK_CONST(0xffffffff) << FUSE_FUSEDATA18_0_FUSEDATA18_SHIFT)
+#define FUSE_FUSEDATA18_0_FUSEDATA18_RANGE                      31:0
+#define FUSE_FUSEDATA18_0_FUSEDATA18_WOFFSET                    0x0
+#define FUSE_FUSEDATA18_0_FUSEDATA18_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA18_0_FUSEDATA18_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA18_0_FUSEDATA18_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA18_0_FUSEDATA18_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA18_0_FUSEDATA_PRIVATE_KEY4__RED_ALIAS_0_SHIFT                      _MK_SHIFT_CONST(0)
+#define FUSE_FUSEDATA18_0_FUSEDATA_PRIVATE_KEY4__RED_ALIAS_0_FIELD                      (_MK_MASK_CONST(0xffffffff) << FUSE_FUSEDATA18_0_FUSEDATA_PRIVATE_KEY4__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA18_0_FUSEDATA_PRIVATE_KEY4__RED_ALIAS_0_RANGE                      31:0
+#define FUSE_FUSEDATA18_0_FUSEDATA_PRIVATE_KEY4__RED_ALIAS_0_WOFFSET                    0x0
+#define FUSE_FUSEDATA18_0_FUSEDATA_PRIVATE_KEY4__RED_ALIAS_0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA18_0_FUSEDATA_PRIVATE_KEY4__RED_ALIAS_0_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA18_0_FUSEDATA_PRIVATE_KEY4__RED_ALIAS_0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA18_0_FUSEDATA_PRIVATE_KEY4__RED_ALIAS_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_FUSEDATA19_0  
+#define FUSE_FUSEDATA19_0                       _MK_ADDR_CONST(0x58)
+#define FUSE_FUSEDATA19_0_WORD_COUNT                    0x1
+#define FUSE_FUSEDATA19_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA19_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA19_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA19_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA19_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA19_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA19_0_FUSEDATA19_SHIFT                      _MK_SHIFT_CONST(0)
+#define FUSE_FUSEDATA19_0_FUSEDATA19_FIELD                      (_MK_MASK_CONST(0xffffffff) << FUSE_FUSEDATA19_0_FUSEDATA19_SHIFT)
+#define FUSE_FUSEDATA19_0_FUSEDATA19_RANGE                      31:0
+#define FUSE_FUSEDATA19_0_FUSEDATA19_WOFFSET                    0x0
+#define FUSE_FUSEDATA19_0_FUSEDATA19_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA19_0_FUSEDATA19_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA19_0_FUSEDATA19_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA19_0_FUSEDATA19_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA19_0_FUSEDATA_ARM_JTAG_DIS__RED_ALIAS_0_SHIFT                      _MK_SHIFT_CONST(0)
+#define FUSE_FUSEDATA19_0_FUSEDATA_ARM_JTAG_DIS__RED_ALIAS_0_FIELD                      (_MK_MASK_CONST(0x1) << FUSE_FUSEDATA19_0_FUSEDATA_ARM_JTAG_DIS__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA19_0_FUSEDATA_ARM_JTAG_DIS__RED_ALIAS_0_RANGE                      0:0
+#define FUSE_FUSEDATA19_0_FUSEDATA_ARM_JTAG_DIS__RED_ALIAS_0_WOFFSET                    0x0
+#define FUSE_FUSEDATA19_0_FUSEDATA_ARM_JTAG_DIS__RED_ALIAS_0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA19_0_FUSEDATA_ARM_JTAG_DIS__RED_ALIAS_0_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FUSE_FUSEDATA19_0_FUSEDATA_ARM_JTAG_DIS__RED_ALIAS_0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA19_0_FUSEDATA_ARM_JTAG_DIS__RED_ALIAS_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA19_0_FUSEDATA_BOOT_DEVICE_INFO__RED_ALIAS_0_SHIFT                  _MK_SHIFT_CONST(1)
+#define FUSE_FUSEDATA19_0_FUSEDATA_BOOT_DEVICE_INFO__RED_ALIAS_0_FIELD                  (_MK_MASK_CONST(0x7f) << FUSE_FUSEDATA19_0_FUSEDATA_BOOT_DEVICE_INFO__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA19_0_FUSEDATA_BOOT_DEVICE_INFO__RED_ALIAS_0_RANGE                  7:1
+#define FUSE_FUSEDATA19_0_FUSEDATA_BOOT_DEVICE_INFO__RED_ALIAS_0_WOFFSET                        0x0
+#define FUSE_FUSEDATA19_0_FUSEDATA_BOOT_DEVICE_INFO__RED_ALIAS_0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA19_0_FUSEDATA_BOOT_DEVICE_INFO__RED_ALIAS_0_DEFAULT_MASK                   _MK_MASK_CONST(0x7f)
+#define FUSE_FUSEDATA19_0_FUSEDATA_BOOT_DEVICE_INFO__RED_ALIAS_0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA19_0_FUSEDATA_BOOT_DEVICE_INFO__RED_ALIAS_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA19_0_FUSEDATA_RESERVED_SW__RED_ALIAS_0_SHIFT                       _MK_SHIFT_CONST(8)
+#define FUSE_FUSEDATA19_0_FUSEDATA_RESERVED_SW__RED_ALIAS_0_FIELD                       (_MK_MASK_CONST(0xff) << FUSE_FUSEDATA19_0_FUSEDATA_RESERVED_SW__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA19_0_FUSEDATA_RESERVED_SW__RED_ALIAS_0_RANGE                       15:8
+#define FUSE_FUSEDATA19_0_FUSEDATA_RESERVED_SW__RED_ALIAS_0_WOFFSET                     0x0
+#define FUSE_FUSEDATA19_0_FUSEDATA_RESERVED_SW__RED_ALIAS_0_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA19_0_FUSEDATA_RESERVED_SW__RED_ALIAS_0_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define FUSE_FUSEDATA19_0_FUSEDATA_RESERVED_SW__RED_ALIAS_0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA19_0_FUSEDATA_RESERVED_SW__RED_ALIAS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA19_0_FUSEDATA_JTAG_SECUREID_0__PRI_ALIAS_0_SHIFT                   _MK_SHIFT_CONST(16)
+#define FUSE_FUSEDATA19_0_FUSEDATA_JTAG_SECUREID_0__PRI_ALIAS_0_FIELD                   (_MK_MASK_CONST(0xffff) << FUSE_FUSEDATA19_0_FUSEDATA_JTAG_SECUREID_0__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA19_0_FUSEDATA_JTAG_SECUREID_0__PRI_ALIAS_0_RANGE                   31:16
+#define FUSE_FUSEDATA19_0_FUSEDATA_JTAG_SECUREID_0__PRI_ALIAS_0_WOFFSET                 0x0
+#define FUSE_FUSEDATA19_0_FUSEDATA_JTAG_SECUREID_0__PRI_ALIAS_0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA19_0_FUSEDATA_JTAG_SECUREID_0__PRI_ALIAS_0_DEFAULT_MASK                    _MK_MASK_CONST(0xffff)
+#define FUSE_FUSEDATA19_0_FUSEDATA_JTAG_SECUREID_0__PRI_ALIAS_0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA19_0_FUSEDATA_JTAG_SECUREID_0__PRI_ALIAS_0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_FUSEDATA20_0  
+#define FUSE_FUSEDATA20_0                       _MK_ADDR_CONST(0x5c)
+#define FUSE_FUSEDATA20_0_WORD_COUNT                    0x1
+#define FUSE_FUSEDATA20_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA20_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA20_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA20_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA20_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA20_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA20_0_FUSEDATA20_SHIFT                      _MK_SHIFT_CONST(0)
+#define FUSE_FUSEDATA20_0_FUSEDATA20_FIELD                      (_MK_MASK_CONST(0xffffffff) << FUSE_FUSEDATA20_0_FUSEDATA20_SHIFT)
+#define FUSE_FUSEDATA20_0_FUSEDATA20_RANGE                      31:0
+#define FUSE_FUSEDATA20_0_FUSEDATA20_WOFFSET                    0x0
+#define FUSE_FUSEDATA20_0_FUSEDATA20_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA20_0_FUSEDATA20_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA20_0_FUSEDATA20_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA20_0_FUSEDATA20_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA20_0_FUSEDATA_JTAG_SECUREID_0__PRI_ALIAS_1_SHIFT                   _MK_SHIFT_CONST(0)
+#define FUSE_FUSEDATA20_0_FUSEDATA_JTAG_SECUREID_0__PRI_ALIAS_1_FIELD                   (_MK_MASK_CONST(0xffff) << FUSE_FUSEDATA20_0_FUSEDATA_JTAG_SECUREID_0__PRI_ALIAS_1_SHIFT)
+#define FUSE_FUSEDATA20_0_FUSEDATA_JTAG_SECUREID_0__PRI_ALIAS_1_RANGE                   15:0
+#define FUSE_FUSEDATA20_0_FUSEDATA_JTAG_SECUREID_0__PRI_ALIAS_1_WOFFSET                 0x0
+#define FUSE_FUSEDATA20_0_FUSEDATA_JTAG_SECUREID_0__PRI_ALIAS_1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA20_0_FUSEDATA_JTAG_SECUREID_0__PRI_ALIAS_1_DEFAULT_MASK                    _MK_MASK_CONST(0xffff)
+#define FUSE_FUSEDATA20_0_FUSEDATA_JTAG_SECUREID_0__PRI_ALIAS_1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA20_0_FUSEDATA_JTAG_SECUREID_0__PRI_ALIAS_1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA20_0_FUSEDATA_JTAG_SECUREID_1__PRI_ALIAS_0_SHIFT                   _MK_SHIFT_CONST(16)
+#define FUSE_FUSEDATA20_0_FUSEDATA_JTAG_SECUREID_1__PRI_ALIAS_0_FIELD                   (_MK_MASK_CONST(0xffff) << FUSE_FUSEDATA20_0_FUSEDATA_JTAG_SECUREID_1__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA20_0_FUSEDATA_JTAG_SECUREID_1__PRI_ALIAS_0_RANGE                   31:16
+#define FUSE_FUSEDATA20_0_FUSEDATA_JTAG_SECUREID_1__PRI_ALIAS_0_WOFFSET                 0x0
+#define FUSE_FUSEDATA20_0_FUSEDATA_JTAG_SECUREID_1__PRI_ALIAS_0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA20_0_FUSEDATA_JTAG_SECUREID_1__PRI_ALIAS_0_DEFAULT_MASK                    _MK_MASK_CONST(0xffff)
+#define FUSE_FUSEDATA20_0_FUSEDATA_JTAG_SECUREID_1__PRI_ALIAS_0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA20_0_FUSEDATA_JTAG_SECUREID_1__PRI_ALIAS_0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_FUSEDATA21_0  
+#define FUSE_FUSEDATA21_0                       _MK_ADDR_CONST(0x60)
+#define FUSE_FUSEDATA21_0_WORD_COUNT                    0x1
+#define FUSE_FUSEDATA21_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA21_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA21_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA21_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA21_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA21_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA21_0_FUSEDATA21_SHIFT                      _MK_SHIFT_CONST(0)
+#define FUSE_FUSEDATA21_0_FUSEDATA21_FIELD                      (_MK_MASK_CONST(0xffffffff) << FUSE_FUSEDATA21_0_FUSEDATA21_SHIFT)
+#define FUSE_FUSEDATA21_0_FUSEDATA21_RANGE                      31:0
+#define FUSE_FUSEDATA21_0_FUSEDATA21_WOFFSET                    0x0
+#define FUSE_FUSEDATA21_0_FUSEDATA21_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA21_0_FUSEDATA21_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA21_0_FUSEDATA21_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA21_0_FUSEDATA21_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA21_0_FUSEDATA_JTAG_SECUREID_1__PRI_ALIAS_1_SHIFT                   _MK_SHIFT_CONST(0)
+#define FUSE_FUSEDATA21_0_FUSEDATA_JTAG_SECUREID_1__PRI_ALIAS_1_FIELD                   (_MK_MASK_CONST(0xffff) << FUSE_FUSEDATA21_0_FUSEDATA_JTAG_SECUREID_1__PRI_ALIAS_1_SHIFT)
+#define FUSE_FUSEDATA21_0_FUSEDATA_JTAG_SECUREID_1__PRI_ALIAS_1_RANGE                   15:0
+#define FUSE_FUSEDATA21_0_FUSEDATA_JTAG_SECUREID_1__PRI_ALIAS_1_WOFFSET                 0x0
+#define FUSE_FUSEDATA21_0_FUSEDATA_JTAG_SECUREID_1__PRI_ALIAS_1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA21_0_FUSEDATA_JTAG_SECUREID_1__PRI_ALIAS_1_DEFAULT_MASK                    _MK_MASK_CONST(0xffff)
+#define FUSE_FUSEDATA21_0_FUSEDATA_JTAG_SECUREID_1__PRI_ALIAS_1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA21_0_FUSEDATA_JTAG_SECUREID_1__PRI_ALIAS_1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_0__PRI_ALIAS_0_SHIFT                       _MK_SHIFT_CONST(16)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_0__PRI_ALIAS_0_FIELD                       (_MK_MASK_CONST(0x1) << FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_0__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_0__PRI_ALIAS_0_RANGE                       16:16
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_0__PRI_ALIAS_0_WOFFSET                     0x0
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_0__PRI_ALIAS_0_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_0__PRI_ALIAS_0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_0__PRI_ALIAS_0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_0__PRI_ALIAS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_1__PRI_ALIAS_0_SHIFT                       _MK_SHIFT_CONST(17)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_1__PRI_ALIAS_0_FIELD                       (_MK_MASK_CONST(0x1) << FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_1__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_1__PRI_ALIAS_0_RANGE                       17:17
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_1__PRI_ALIAS_0_WOFFSET                     0x0
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_1__PRI_ALIAS_0_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_1__PRI_ALIAS_0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_1__PRI_ALIAS_0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_1__PRI_ALIAS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_2__PRI_ALIAS_0_SHIFT                       _MK_SHIFT_CONST(18)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_2__PRI_ALIAS_0_FIELD                       (_MK_MASK_CONST(0x1) << FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_2__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_2__PRI_ALIAS_0_RANGE                       18:18
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_2__PRI_ALIAS_0_WOFFSET                     0x0
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_2__PRI_ALIAS_0_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_2__PRI_ALIAS_0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_2__PRI_ALIAS_0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_2__PRI_ALIAS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_3__PRI_ALIAS_0_SHIFT                       _MK_SHIFT_CONST(19)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_3__PRI_ALIAS_0_FIELD                       (_MK_MASK_CONST(0x1) << FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_3__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_3__PRI_ALIAS_0_RANGE                       19:19
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_3__PRI_ALIAS_0_WOFFSET                     0x0
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_3__PRI_ALIAS_0_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_3__PRI_ALIAS_0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_3__PRI_ALIAS_0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_3__PRI_ALIAS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_4__PRI_ALIAS_0_SHIFT                       _MK_SHIFT_CONST(20)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_4__PRI_ALIAS_0_FIELD                       (_MK_MASK_CONST(0x1) << FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_4__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_4__PRI_ALIAS_0_RANGE                       20:20
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_4__PRI_ALIAS_0_WOFFSET                     0x0
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_4__PRI_ALIAS_0_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_4__PRI_ALIAS_0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_4__PRI_ALIAS_0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_4__PRI_ALIAS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_5__PRI_ALIAS_0_SHIFT                       _MK_SHIFT_CONST(21)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_5__PRI_ALIAS_0_FIELD                       (_MK_MASK_CONST(0x1) << FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_5__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_5__PRI_ALIAS_0_RANGE                       21:21
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_5__PRI_ALIAS_0_WOFFSET                     0x0
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_5__PRI_ALIAS_0_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_5__PRI_ALIAS_0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_5__PRI_ALIAS_0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_5__PRI_ALIAS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_6__PRI_ALIAS_0_SHIFT                       _MK_SHIFT_CONST(22)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_6__PRI_ALIAS_0_FIELD                       (_MK_MASK_CONST(0x1) << FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_6__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_6__PRI_ALIAS_0_RANGE                       22:22
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_6__PRI_ALIAS_0_WOFFSET                     0x0
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_6__PRI_ALIAS_0_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_6__PRI_ALIAS_0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_6__PRI_ALIAS_0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_6__PRI_ALIAS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_7__PRI_ALIAS_0_SHIFT                       _MK_SHIFT_CONST(23)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_7__PRI_ALIAS_0_FIELD                       (_MK_MASK_CONST(0x1) << FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_7__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_7__PRI_ALIAS_0_RANGE                       23:23
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_7__PRI_ALIAS_0_WOFFSET                     0x0
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_7__PRI_ALIAS_0_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_7__PRI_ALIAS_0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_7__PRI_ALIAS_0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_7__PRI_ALIAS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_8__PRI_ALIAS_0_SHIFT                       _MK_SHIFT_CONST(24)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_8__PRI_ALIAS_0_FIELD                       (_MK_MASK_CONST(0x1) << FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_8__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_8__PRI_ALIAS_0_RANGE                       24:24
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_8__PRI_ALIAS_0_WOFFSET                     0x0
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_8__PRI_ALIAS_0_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_8__PRI_ALIAS_0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_8__PRI_ALIAS_0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_8__PRI_ALIAS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_9__PRI_ALIAS_0_SHIFT                       _MK_SHIFT_CONST(25)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_9__PRI_ALIAS_0_FIELD                       (_MK_MASK_CONST(0x1) << FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_9__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_9__PRI_ALIAS_0_RANGE                       25:25
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_9__PRI_ALIAS_0_WOFFSET                     0x0
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_9__PRI_ALIAS_0_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_9__PRI_ALIAS_0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_9__PRI_ALIAS_0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_9__PRI_ALIAS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_10__PRI_ALIAS_0_SHIFT                      _MK_SHIFT_CONST(26)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_10__PRI_ALIAS_0_FIELD                      (_MK_MASK_CONST(0x1) << FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_10__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_10__PRI_ALIAS_0_RANGE                      26:26
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_10__PRI_ALIAS_0_WOFFSET                    0x0
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_10__PRI_ALIAS_0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_10__PRI_ALIAS_0_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_10__PRI_ALIAS_0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_10__PRI_ALIAS_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_11__PRI_ALIAS_0_SHIFT                      _MK_SHIFT_CONST(27)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_11__PRI_ALIAS_0_FIELD                      (_MK_MASK_CONST(0x1) << FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_11__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_11__PRI_ALIAS_0_RANGE                      27:27
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_11__PRI_ALIAS_0_WOFFSET                    0x0
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_11__PRI_ALIAS_0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_11__PRI_ALIAS_0_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_11__PRI_ALIAS_0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_11__PRI_ALIAS_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_12__PRI_ALIAS_0_SHIFT                      _MK_SHIFT_CONST(28)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_12__PRI_ALIAS_0_FIELD                      (_MK_MASK_CONST(0x1) << FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_12__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_12__PRI_ALIAS_0_RANGE                      28:28
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_12__PRI_ALIAS_0_WOFFSET                    0x0
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_12__PRI_ALIAS_0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_12__PRI_ALIAS_0_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_12__PRI_ALIAS_0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_12__PRI_ALIAS_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_13__PRI_ALIAS_0_SHIFT                      _MK_SHIFT_CONST(29)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_13__PRI_ALIAS_0_FIELD                      (_MK_MASK_CONST(0x1) << FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_13__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_13__PRI_ALIAS_0_RANGE                      29:29
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_13__PRI_ALIAS_0_WOFFSET                    0x0
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_13__PRI_ALIAS_0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_13__PRI_ALIAS_0_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_13__PRI_ALIAS_0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_13__PRI_ALIAS_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_14__PRI_ALIAS_0_SHIFT                      _MK_SHIFT_CONST(30)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_14__PRI_ALIAS_0_FIELD                      (_MK_MASK_CONST(0x1) << FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_14__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_14__PRI_ALIAS_0_RANGE                      30:30
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_14__PRI_ALIAS_0_WOFFSET                    0x0
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_14__PRI_ALIAS_0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_14__PRI_ALIAS_0_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_14__PRI_ALIAS_0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_14__PRI_ALIAS_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_15__PRI_ALIAS_0_SHIFT                      _MK_SHIFT_CONST(31)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_15__PRI_ALIAS_0_FIELD                      (_MK_MASK_CONST(0x1) << FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_15__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_15__PRI_ALIAS_0_RANGE                      31:31
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_15__PRI_ALIAS_0_WOFFSET                    0x0
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_15__PRI_ALIAS_0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_15__PRI_ALIAS_0_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_15__PRI_ALIAS_0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_15__PRI_ALIAS_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_FUSEWRDATA0_0  
+#define FUSE_FUSEWRDATA0_0                      _MK_ADDR_CONST(0x64)
+#define FUSE_FUSEWRDATA0_0_WORD_COUNT                   0x1
+#define FUSE_FUSEWRDATA0_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA0_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA0_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA0_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA0_0_READ_MASK                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA0_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA0_SHIFT                    _MK_SHIFT_CONST(0)
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA0_FIELD                    (_MK_MASK_CONST(0xffffffff) << FUSE_FUSEWRDATA0_0_FUSEWRDATA0_SHIFT)
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA0_RANGE                    31:0
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA0_WOFFSET                  0x0
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA0_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA0_DEFAULT_MASK                     _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_MASTER_ENABLE__PRI_ALIAS_0_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_MASTER_ENABLE__PRI_ALIAS_0_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_FUSEWRDATA0_0_FUSEWRDATA_MASTER_ENABLE__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_MASTER_ENABLE__PRI_ALIAS_0_RANGE                  0:0
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_MASTER_ENABLE__PRI_ALIAS_0_WOFFSET                        0x0
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_MASTER_ENABLE__PRI_ALIAS_0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_MASTER_ENABLE__PRI_ALIAS_0_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_MASTER_ENABLE__PRI_ALIAS_0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_MASTER_ENABLE__PRI_ALIAS_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_MASTER_DISABLE__PRI_ALIAS_0_SHIFT                 _MK_SHIFT_CONST(1)
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_MASTER_DISABLE__PRI_ALIAS_0_FIELD                 (_MK_MASK_CONST(0x1) << FUSE_FUSEWRDATA0_0_FUSEWRDATA_MASTER_DISABLE__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_MASTER_DISABLE__PRI_ALIAS_0_RANGE                 1:1
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_MASTER_DISABLE__PRI_ALIAS_0_WOFFSET                       0x0
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_MASTER_DISABLE__PRI_ALIAS_0_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_MASTER_DISABLE__PRI_ALIAS_0_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_MASTER_DISABLE__PRI_ALIAS_0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_MASTER_DISABLE__PRI_ALIAS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_BYPASS__PRI_ALIAS_0_SHIFT                 _MK_SHIFT_CONST(2)
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_BYPASS__PRI_ALIAS_0_FIELD                 (_MK_MASK_CONST(0x1) << FUSE_FUSEWRDATA0_0_FUSEWRDATA_BYPASS__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_BYPASS__PRI_ALIAS_0_RANGE                 2:2
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_BYPASS__PRI_ALIAS_0_WOFFSET                       0x0
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_BYPASS__PRI_ALIAS_0_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_BYPASS__PRI_ALIAS_0_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_BYPASS__PRI_ALIAS_0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_BYPASS__PRI_ALIAS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_RESERVE_BIT__PRI_ALIAS_0_SHIFT                    _MK_SHIFT_CONST(3)
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_RESERVE_BIT__PRI_ALIAS_0_FIELD                    (_MK_MASK_CONST(0x1) << FUSE_FUSEWRDATA0_0_FUSEWRDATA_RESERVE_BIT__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_RESERVE_BIT__PRI_ALIAS_0_RANGE                    3:3
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_RESERVE_BIT__PRI_ALIAS_0_WOFFSET                  0x0
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_RESERVE_BIT__PRI_ALIAS_0_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_RESERVE_BIT__PRI_ALIAS_0_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_RESERVE_BIT__PRI_ALIAS_0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_RESERVE_BIT__PRI_ALIAS_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_PRODUCTION_MODE__PRI_ALIAS_0_SHIFT                        _MK_SHIFT_CONST(4)
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_PRODUCTION_MODE__PRI_ALIAS_0_FIELD                        (_MK_MASK_CONST(0x1) << FUSE_FUSEWRDATA0_0_FUSEWRDATA_PRODUCTION_MODE__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_PRODUCTION_MODE__PRI_ALIAS_0_RANGE                        4:4
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_PRODUCTION_MODE__PRI_ALIAS_0_WOFFSET                      0x0
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_PRODUCTION_MODE__PRI_ALIAS_0_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_PRODUCTION_MODE__PRI_ALIAS_0_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_PRODUCTION_MODE__PRI_ALIAS_0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_PRODUCTION_MODE__PRI_ALIAS_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_JTAG_SECUREID_VALID__PRI_ALIAS_0_SHIFT                    _MK_SHIFT_CONST(5)
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_JTAG_SECUREID_VALID__PRI_ALIAS_0_FIELD                    (_MK_MASK_CONST(0x1) << FUSE_FUSEWRDATA0_0_FUSEWRDATA_JTAG_SECUREID_VALID__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_JTAG_SECUREID_VALID__PRI_ALIAS_0_RANGE                    5:5
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_JTAG_SECUREID_VALID__PRI_ALIAS_0_WOFFSET                  0x0
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_JTAG_SECUREID_VALID__PRI_ALIAS_0_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_JTAG_SECUREID_VALID__PRI_ALIAS_0_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_JTAG_SECUREID_VALID__PRI_ALIAS_0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_JTAG_SECUREID_VALID__PRI_ALIAS_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_SKU_INFO__PRI_ALIAS_0_SHIFT                       _MK_SHIFT_CONST(6)
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_SKU_INFO__PRI_ALIAS_0_FIELD                       (_MK_MASK_CONST(0xff) << FUSE_FUSEWRDATA0_0_FUSEWRDATA_SKU_INFO__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_SKU_INFO__PRI_ALIAS_0_RANGE                       13:6
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_SKU_INFO__PRI_ALIAS_0_WOFFSET                     0x0
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_SKU_INFO__PRI_ALIAS_0_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_SKU_INFO__PRI_ALIAS_0_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_SKU_INFO__PRI_ALIAS_0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_SKU_INFO__PRI_ALIAS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_PROCESS_CALIB__PRI_ALIAS_0_SHIFT                  _MK_SHIFT_CONST(14)
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_PROCESS_CALIB__PRI_ALIAS_0_FIELD                  (_MK_MASK_CONST(0x3) << FUSE_FUSEWRDATA0_0_FUSEWRDATA_PROCESS_CALIB__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_PROCESS_CALIB__PRI_ALIAS_0_RANGE                  15:14
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_PROCESS_CALIB__PRI_ALIAS_0_WOFFSET                        0x0
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_PROCESS_CALIB__PRI_ALIAS_0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_PROCESS_CALIB__PRI_ALIAS_0_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_PROCESS_CALIB__PRI_ALIAS_0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_PROCESS_CALIB__PRI_ALIAS_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_IO_CALIB__PRI_ALIAS_0_SHIFT                       _MK_SHIFT_CONST(16)
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_IO_CALIB__PRI_ALIAS_0_FIELD                       (_MK_MASK_CONST(0x3ff) << FUSE_FUSEWRDATA0_0_FUSEWRDATA_IO_CALIB__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_IO_CALIB__PRI_ALIAS_0_RANGE                       25:16
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_IO_CALIB__PRI_ALIAS_0_WOFFSET                     0x0
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_IO_CALIB__PRI_ALIAS_0_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_IO_CALIB__PRI_ALIAS_0_DEFAULT_MASK                        _MK_MASK_CONST(0x3ff)
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_IO_CALIB__PRI_ALIAS_0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_IO_CALIB__PRI_ALIAS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_DAC_CRT_CALIB__PRI_ALIAS_0_SHIFT                  _MK_SHIFT_CONST(26)
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_DAC_CRT_CALIB__PRI_ALIAS_0_FIELD                  (_MK_MASK_CONST(0x3f) << FUSE_FUSEWRDATA0_0_FUSEWRDATA_DAC_CRT_CALIB__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_DAC_CRT_CALIB__PRI_ALIAS_0_RANGE                  31:26
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_DAC_CRT_CALIB__PRI_ALIAS_0_WOFFSET                        0x0
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_DAC_CRT_CALIB__PRI_ALIAS_0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_DAC_CRT_CALIB__PRI_ALIAS_0_DEFAULT_MASK                   _MK_MASK_CONST(0x3f)
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_DAC_CRT_CALIB__PRI_ALIAS_0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_DAC_CRT_CALIB__PRI_ALIAS_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_FUSEWRDATA1_0  
+#define FUSE_FUSEWRDATA1_0                      _MK_ADDR_CONST(0x68)
+#define FUSE_FUSEWRDATA1_0_WORD_COUNT                   0x1
+#define FUSE_FUSEWRDATA1_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA1_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA1_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA1_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA1_0_READ_MASK                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA1_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA1_0_FUSEWRDATA1_SHIFT                    _MK_SHIFT_CONST(0)
+#define FUSE_FUSEWRDATA1_0_FUSEWRDATA1_FIELD                    (_MK_MASK_CONST(0xffffffff) << FUSE_FUSEWRDATA1_0_FUSEWRDATA1_SHIFT)
+#define FUSE_FUSEWRDATA1_0_FUSEWRDATA1_RANGE                    31:0
+#define FUSE_FUSEWRDATA1_0_FUSEWRDATA1_WOFFSET                  0x0
+#define FUSE_FUSEWRDATA1_0_FUSEWRDATA1_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA1_0_FUSEWRDATA1_DEFAULT_MASK                     _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA1_0_FUSEWRDATA1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA1_0_FUSEWRDATA1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA1_0_FUSEWRDATA_DAC_CRT_CALIB__PRI_ALIAS_1_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_FUSEWRDATA1_0_FUSEWRDATA_DAC_CRT_CALIB__PRI_ALIAS_1_FIELD                  (_MK_MASK_CONST(0x3) << FUSE_FUSEWRDATA1_0_FUSEWRDATA_DAC_CRT_CALIB__PRI_ALIAS_1_SHIFT)
+#define FUSE_FUSEWRDATA1_0_FUSEWRDATA_DAC_CRT_CALIB__PRI_ALIAS_1_RANGE                  1:0
+#define FUSE_FUSEWRDATA1_0_FUSEWRDATA_DAC_CRT_CALIB__PRI_ALIAS_1_WOFFSET                        0x0
+#define FUSE_FUSEWRDATA1_0_FUSEWRDATA_DAC_CRT_CALIB__PRI_ALIAS_1_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA1_0_FUSEWRDATA_DAC_CRT_CALIB__PRI_ALIAS_1_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define FUSE_FUSEWRDATA1_0_FUSEWRDATA_DAC_CRT_CALIB__PRI_ALIAS_1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA1_0_FUSEWRDATA_DAC_CRT_CALIB__PRI_ALIAS_1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA1_0_FUSEWRDATA_DAC_HDTV_CALIB__PRI_ALIAS_0_SHIFT                 _MK_SHIFT_CONST(2)
+#define FUSE_FUSEWRDATA1_0_FUSEWRDATA_DAC_HDTV_CALIB__PRI_ALIAS_0_FIELD                 (_MK_MASK_CONST(0xff) << FUSE_FUSEWRDATA1_0_FUSEWRDATA_DAC_HDTV_CALIB__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA1_0_FUSEWRDATA_DAC_HDTV_CALIB__PRI_ALIAS_0_RANGE                 9:2
+#define FUSE_FUSEWRDATA1_0_FUSEWRDATA_DAC_HDTV_CALIB__PRI_ALIAS_0_WOFFSET                       0x0
+#define FUSE_FUSEWRDATA1_0_FUSEWRDATA_DAC_HDTV_CALIB__PRI_ALIAS_0_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA1_0_FUSEWRDATA_DAC_HDTV_CALIB__PRI_ALIAS_0_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define FUSE_FUSEWRDATA1_0_FUSEWRDATA_DAC_HDTV_CALIB__PRI_ALIAS_0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA1_0_FUSEWRDATA_DAC_HDTV_CALIB__PRI_ALIAS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA1_0_FUSEWRDATA_DAC_SDTV_CALIB__PRI_ALIAS_0_SHIFT                 _MK_SHIFT_CONST(10)
+#define FUSE_FUSEWRDATA1_0_FUSEWRDATA_DAC_SDTV_CALIB__PRI_ALIAS_0_FIELD                 (_MK_MASK_CONST(0xff) << FUSE_FUSEWRDATA1_0_FUSEWRDATA_DAC_SDTV_CALIB__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA1_0_FUSEWRDATA_DAC_SDTV_CALIB__PRI_ALIAS_0_RANGE                 17:10
+#define FUSE_FUSEWRDATA1_0_FUSEWRDATA_DAC_SDTV_CALIB__PRI_ALIAS_0_WOFFSET                       0x0
+#define FUSE_FUSEWRDATA1_0_FUSEWRDATA_DAC_SDTV_CALIB__PRI_ALIAS_0_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA1_0_FUSEWRDATA_DAC_SDTV_CALIB__PRI_ALIAS_0_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define FUSE_FUSEWRDATA1_0_FUSEWRDATA_DAC_SDTV_CALIB__PRI_ALIAS_0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA1_0_FUSEWRDATA_DAC_SDTV_CALIB__PRI_ALIAS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA1_0_FUSEWRDATA_CMC_DATARAM0_0__PRI_ALIAS_0_SHIFT                 _MK_SHIFT_CONST(18)
+#define FUSE_FUSEWRDATA1_0_FUSEWRDATA_CMC_DATARAM0_0__PRI_ALIAS_0_FIELD                 (_MK_MASK_CONST(0x7f) << FUSE_FUSEWRDATA1_0_FUSEWRDATA_CMC_DATARAM0_0__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA1_0_FUSEWRDATA_CMC_DATARAM0_0__PRI_ALIAS_0_RANGE                 24:18
+#define FUSE_FUSEWRDATA1_0_FUSEWRDATA_CMC_DATARAM0_0__PRI_ALIAS_0_WOFFSET                       0x0
+#define FUSE_FUSEWRDATA1_0_FUSEWRDATA_CMC_DATARAM0_0__PRI_ALIAS_0_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA1_0_FUSEWRDATA_CMC_DATARAM0_0__PRI_ALIAS_0_DEFAULT_MASK                  _MK_MASK_CONST(0x7f)
+#define FUSE_FUSEWRDATA1_0_FUSEWRDATA_CMC_DATARAM0_0__PRI_ALIAS_0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA1_0_FUSEWRDATA_CMC_DATARAM0_0__PRI_ALIAS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA1_0_FUSEWRDATA_CMC_DATARAM0_1__PRI_ALIAS_0_SHIFT                 _MK_SHIFT_CONST(25)
+#define FUSE_FUSEWRDATA1_0_FUSEWRDATA_CMC_DATARAM0_1__PRI_ALIAS_0_FIELD                 (_MK_MASK_CONST(0x7f) << FUSE_FUSEWRDATA1_0_FUSEWRDATA_CMC_DATARAM0_1__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA1_0_FUSEWRDATA_CMC_DATARAM0_1__PRI_ALIAS_0_RANGE                 31:25
+#define FUSE_FUSEWRDATA1_0_FUSEWRDATA_CMC_DATARAM0_1__PRI_ALIAS_0_WOFFSET                       0x0
+#define FUSE_FUSEWRDATA1_0_FUSEWRDATA_CMC_DATARAM0_1__PRI_ALIAS_0_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA1_0_FUSEWRDATA_CMC_DATARAM0_1__PRI_ALIAS_0_DEFAULT_MASK                  _MK_MASK_CONST(0x7f)
+#define FUSE_FUSEWRDATA1_0_FUSEWRDATA_CMC_DATARAM0_1__PRI_ALIAS_0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA1_0_FUSEWRDATA_CMC_DATARAM0_1__PRI_ALIAS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_FUSEWRDATA2_0  
+#define FUSE_FUSEWRDATA2_0                      _MK_ADDR_CONST(0x6c)
+#define FUSE_FUSEWRDATA2_0_WORD_COUNT                   0x1
+#define FUSE_FUSEWRDATA2_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA2_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA2_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA2_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA2_0_READ_MASK                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA2_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA2_0_FUSEWRDATA2_SHIFT                    _MK_SHIFT_CONST(0)
+#define FUSE_FUSEWRDATA2_0_FUSEWRDATA2_FIELD                    (_MK_MASK_CONST(0xffffffff) << FUSE_FUSEWRDATA2_0_FUSEWRDATA2_SHIFT)
+#define FUSE_FUSEWRDATA2_0_FUSEWRDATA2_RANGE                    31:0
+#define FUSE_FUSEWRDATA2_0_FUSEWRDATA2_WOFFSET                  0x0
+#define FUSE_FUSEWRDATA2_0_FUSEWRDATA2_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA2_0_FUSEWRDATA2_DEFAULT_MASK                     _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA2_0_FUSEWRDATA2_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA2_0_FUSEWRDATA2_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA2_0_FUSEWRDATA_CMC_DATARAM0_2__PRI_ALIAS_0_SHIFT                 _MK_SHIFT_CONST(0)
+#define FUSE_FUSEWRDATA2_0_FUSEWRDATA_CMC_DATARAM0_2__PRI_ALIAS_0_FIELD                 (_MK_MASK_CONST(0x7f) << FUSE_FUSEWRDATA2_0_FUSEWRDATA_CMC_DATARAM0_2__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA2_0_FUSEWRDATA_CMC_DATARAM0_2__PRI_ALIAS_0_RANGE                 6:0
+#define FUSE_FUSEWRDATA2_0_FUSEWRDATA_CMC_DATARAM0_2__PRI_ALIAS_0_WOFFSET                       0x0
+#define FUSE_FUSEWRDATA2_0_FUSEWRDATA_CMC_DATARAM0_2__PRI_ALIAS_0_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA2_0_FUSEWRDATA_CMC_DATARAM0_2__PRI_ALIAS_0_DEFAULT_MASK                  _MK_MASK_CONST(0x7f)
+#define FUSE_FUSEWRDATA2_0_FUSEWRDATA_CMC_DATARAM0_2__PRI_ALIAS_0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA2_0_FUSEWRDATA_CMC_DATARAM0_2__PRI_ALIAS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA2_0_FUSEWRDATA_CMC_DATARAM0_3__PRI_ALIAS_0_SHIFT                 _MK_SHIFT_CONST(7)
+#define FUSE_FUSEWRDATA2_0_FUSEWRDATA_CMC_DATARAM0_3__PRI_ALIAS_0_FIELD                 (_MK_MASK_CONST(0x7f) << FUSE_FUSEWRDATA2_0_FUSEWRDATA_CMC_DATARAM0_3__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA2_0_FUSEWRDATA_CMC_DATARAM0_3__PRI_ALIAS_0_RANGE                 13:7
+#define FUSE_FUSEWRDATA2_0_FUSEWRDATA_CMC_DATARAM0_3__PRI_ALIAS_0_WOFFSET                       0x0
+#define FUSE_FUSEWRDATA2_0_FUSEWRDATA_CMC_DATARAM0_3__PRI_ALIAS_0_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA2_0_FUSEWRDATA_CMC_DATARAM0_3__PRI_ALIAS_0_DEFAULT_MASK                  _MK_MASK_CONST(0x7f)
+#define FUSE_FUSEWRDATA2_0_FUSEWRDATA_CMC_DATARAM0_3__PRI_ALIAS_0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA2_0_FUSEWRDATA_CMC_DATARAM0_3__PRI_ALIAS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA2_0_FUSEWRDATA_CMC_DATARAM1_0__PRI_ALIAS_0_SHIFT                 _MK_SHIFT_CONST(14)
+#define FUSE_FUSEWRDATA2_0_FUSEWRDATA_CMC_DATARAM1_0__PRI_ALIAS_0_FIELD                 (_MK_MASK_CONST(0x7f) << FUSE_FUSEWRDATA2_0_FUSEWRDATA_CMC_DATARAM1_0__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA2_0_FUSEWRDATA_CMC_DATARAM1_0__PRI_ALIAS_0_RANGE                 20:14
+#define FUSE_FUSEWRDATA2_0_FUSEWRDATA_CMC_DATARAM1_0__PRI_ALIAS_0_WOFFSET                       0x0
+#define FUSE_FUSEWRDATA2_0_FUSEWRDATA_CMC_DATARAM1_0__PRI_ALIAS_0_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA2_0_FUSEWRDATA_CMC_DATARAM1_0__PRI_ALIAS_0_DEFAULT_MASK                  _MK_MASK_CONST(0x7f)
+#define FUSE_FUSEWRDATA2_0_FUSEWRDATA_CMC_DATARAM1_0__PRI_ALIAS_0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA2_0_FUSEWRDATA_CMC_DATARAM1_0__PRI_ALIAS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA2_0_FUSEWRDATA_CMC_DATARAM1_1__PRI_ALIAS_0_SHIFT                 _MK_SHIFT_CONST(21)
+#define FUSE_FUSEWRDATA2_0_FUSEWRDATA_CMC_DATARAM1_1__PRI_ALIAS_0_FIELD                 (_MK_MASK_CONST(0x7f) << FUSE_FUSEWRDATA2_0_FUSEWRDATA_CMC_DATARAM1_1__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA2_0_FUSEWRDATA_CMC_DATARAM1_1__PRI_ALIAS_0_RANGE                 27:21
+#define FUSE_FUSEWRDATA2_0_FUSEWRDATA_CMC_DATARAM1_1__PRI_ALIAS_0_WOFFSET                       0x0
+#define FUSE_FUSEWRDATA2_0_FUSEWRDATA_CMC_DATARAM1_1__PRI_ALIAS_0_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA2_0_FUSEWRDATA_CMC_DATARAM1_1__PRI_ALIAS_0_DEFAULT_MASK                  _MK_MASK_CONST(0x7f)
+#define FUSE_FUSEWRDATA2_0_FUSEWRDATA_CMC_DATARAM1_1__PRI_ALIAS_0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA2_0_FUSEWRDATA_CMC_DATARAM1_1__PRI_ALIAS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA2_0_FUSEWRDATA_CMC_DATARAM1_2__PRI_ALIAS_0_SHIFT                 _MK_SHIFT_CONST(28)
+#define FUSE_FUSEWRDATA2_0_FUSEWRDATA_CMC_DATARAM1_2__PRI_ALIAS_0_FIELD                 (_MK_MASK_CONST(0xf) << FUSE_FUSEWRDATA2_0_FUSEWRDATA_CMC_DATARAM1_2__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA2_0_FUSEWRDATA_CMC_DATARAM1_2__PRI_ALIAS_0_RANGE                 31:28
+#define FUSE_FUSEWRDATA2_0_FUSEWRDATA_CMC_DATARAM1_2__PRI_ALIAS_0_WOFFSET                       0x0
+#define FUSE_FUSEWRDATA2_0_FUSEWRDATA_CMC_DATARAM1_2__PRI_ALIAS_0_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA2_0_FUSEWRDATA_CMC_DATARAM1_2__PRI_ALIAS_0_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define FUSE_FUSEWRDATA2_0_FUSEWRDATA_CMC_DATARAM1_2__PRI_ALIAS_0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA2_0_FUSEWRDATA_CMC_DATARAM1_2__PRI_ALIAS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_FUSEWRDATA3_0  
+#define FUSE_FUSEWRDATA3_0                      _MK_ADDR_CONST(0x70)
+#define FUSE_FUSEWRDATA3_0_WORD_COUNT                   0x1
+#define FUSE_FUSEWRDATA3_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA3_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA3_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA3_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA3_0_READ_MASK                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA3_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA3_SHIFT                    _MK_SHIFT_CONST(0)
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA3_FIELD                    (_MK_MASK_CONST(0xffffffff) << FUSE_FUSEWRDATA3_0_FUSEWRDATA3_SHIFT)
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA3_RANGE                    31:0
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA3_WOFFSET                  0x0
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA3_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA3_DEFAULT_MASK                     _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA3_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA3_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA_CMC_DATARAM1_2__PRI_ALIAS_1_SHIFT                 _MK_SHIFT_CONST(0)
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA_CMC_DATARAM1_2__PRI_ALIAS_1_FIELD                 (_MK_MASK_CONST(0x7) << FUSE_FUSEWRDATA3_0_FUSEWRDATA_CMC_DATARAM1_2__PRI_ALIAS_1_SHIFT)
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA_CMC_DATARAM1_2__PRI_ALIAS_1_RANGE                 2:0
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA_CMC_DATARAM1_2__PRI_ALIAS_1_WOFFSET                       0x0
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA_CMC_DATARAM1_2__PRI_ALIAS_1_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA_CMC_DATARAM1_2__PRI_ALIAS_1_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA_CMC_DATARAM1_2__PRI_ALIAS_1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA_CMC_DATARAM1_2__PRI_ALIAS_1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA_CMC_DATARAM1_3__PRI_ALIAS_0_SHIFT                 _MK_SHIFT_CONST(3)
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA_CMC_DATARAM1_3__PRI_ALIAS_0_FIELD                 (_MK_MASK_CONST(0x7f) << FUSE_FUSEWRDATA3_0_FUSEWRDATA_CMC_DATARAM1_3__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA_CMC_DATARAM1_3__PRI_ALIAS_0_RANGE                 9:3
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA_CMC_DATARAM1_3__PRI_ALIAS_0_WOFFSET                       0x0
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA_CMC_DATARAM1_3__PRI_ALIAS_0_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA_CMC_DATARAM1_3__PRI_ALIAS_0_DEFAULT_MASK                  _MK_MASK_CONST(0x7f)
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA_CMC_DATARAM1_3__PRI_ALIAS_0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA_CMC_DATARAM1_3__PRI_ALIAS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA_FA__PRI_ALIAS_0_SHIFT                     _MK_SHIFT_CONST(10)
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA_FA__PRI_ALIAS_0_FIELD                     (_MK_MASK_CONST(0x1) << FUSE_FUSEWRDATA3_0_FUSEWRDATA_FA__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA_FA__PRI_ALIAS_0_RANGE                     10:10
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA_FA__PRI_ALIAS_0_WOFFSET                   0x0
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA_FA__PRI_ALIAS_0_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA_FA__PRI_ALIAS_0_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA_FA__PRI_ALIAS_0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA_FA__PRI_ALIAS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA_RESERVED_PRODUCTION__PRI_ALIAS_0_SHIFT                    _MK_SHIFT_CONST(11)
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA_RESERVED_PRODUCTION__PRI_ALIAS_0_FIELD                    (_MK_MASK_CONST(0xf) << FUSE_FUSEWRDATA3_0_FUSEWRDATA_RESERVED_PRODUCTION__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA_RESERVED_PRODUCTION__PRI_ALIAS_0_RANGE                    14:11
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA_RESERVED_PRODUCTION__PRI_ALIAS_0_WOFFSET                  0x0
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA_RESERVED_PRODUCTION__PRI_ALIAS_0_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA_RESERVED_PRODUCTION__PRI_ALIAS_0_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA_RESERVED_PRODUCTION__PRI_ALIAS_0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA_RESERVED_PRODUCTION__PRI_ALIAS_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA_HDMI_LANE0_CALIB__PRI_ALIAS_0_SHIFT                       _MK_SHIFT_CONST(15)
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA_HDMI_LANE0_CALIB__PRI_ALIAS_0_FIELD                       (_MK_MASK_CONST(0x3f) << FUSE_FUSEWRDATA3_0_FUSEWRDATA_HDMI_LANE0_CALIB__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA_HDMI_LANE0_CALIB__PRI_ALIAS_0_RANGE                       20:15
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA_HDMI_LANE0_CALIB__PRI_ALIAS_0_WOFFSET                     0x0
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA_HDMI_LANE0_CALIB__PRI_ALIAS_0_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA_HDMI_LANE0_CALIB__PRI_ALIAS_0_DEFAULT_MASK                        _MK_MASK_CONST(0x3f)
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA_HDMI_LANE0_CALIB__PRI_ALIAS_0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA_HDMI_LANE0_CALIB__PRI_ALIAS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA_HDMI_LANE1_CALIB__PRI_ALIAS_0_SHIFT                       _MK_SHIFT_CONST(21)
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA_HDMI_LANE1_CALIB__PRI_ALIAS_0_FIELD                       (_MK_MASK_CONST(0x3f) << FUSE_FUSEWRDATA3_0_FUSEWRDATA_HDMI_LANE1_CALIB__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA_HDMI_LANE1_CALIB__PRI_ALIAS_0_RANGE                       26:21
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA_HDMI_LANE1_CALIB__PRI_ALIAS_0_WOFFSET                     0x0
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA_HDMI_LANE1_CALIB__PRI_ALIAS_0_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA_HDMI_LANE1_CALIB__PRI_ALIAS_0_DEFAULT_MASK                        _MK_MASK_CONST(0x3f)
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA_HDMI_LANE1_CALIB__PRI_ALIAS_0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA_HDMI_LANE1_CALIB__PRI_ALIAS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA_HDMI_LANE2_CALIB__PRI_ALIAS_0_SHIFT                       _MK_SHIFT_CONST(27)
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA_HDMI_LANE2_CALIB__PRI_ALIAS_0_FIELD                       (_MK_MASK_CONST(0x1f) << FUSE_FUSEWRDATA3_0_FUSEWRDATA_HDMI_LANE2_CALIB__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA_HDMI_LANE2_CALIB__PRI_ALIAS_0_RANGE                       31:27
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA_HDMI_LANE2_CALIB__PRI_ALIAS_0_WOFFSET                     0x0
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA_HDMI_LANE2_CALIB__PRI_ALIAS_0_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA_HDMI_LANE2_CALIB__PRI_ALIAS_0_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA_HDMI_LANE2_CALIB__PRI_ALIAS_0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA_HDMI_LANE2_CALIB__PRI_ALIAS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_FUSEWRDATA4_0  
+#define FUSE_FUSEWRDATA4_0                      _MK_ADDR_CONST(0x74)
+#define FUSE_FUSEWRDATA4_0_WORD_COUNT                   0x1
+#define FUSE_FUSEWRDATA4_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA4_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA4_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA4_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA4_0_READ_MASK                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA4_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA4_0_FUSEWRDATA4_SHIFT                    _MK_SHIFT_CONST(0)
+#define FUSE_FUSEWRDATA4_0_FUSEWRDATA4_FIELD                    (_MK_MASK_CONST(0xffffffff) << FUSE_FUSEWRDATA4_0_FUSEWRDATA4_SHIFT)
+#define FUSE_FUSEWRDATA4_0_FUSEWRDATA4_RANGE                    31:0
+#define FUSE_FUSEWRDATA4_0_FUSEWRDATA4_WOFFSET                  0x0
+#define FUSE_FUSEWRDATA4_0_FUSEWRDATA4_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA4_0_FUSEWRDATA4_DEFAULT_MASK                     _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA4_0_FUSEWRDATA4_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA4_0_FUSEWRDATA4_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA4_0_FUSEWRDATA_HDMI_LANE2_CALIB__PRI_ALIAS_1_SHIFT                       _MK_SHIFT_CONST(0)
+#define FUSE_FUSEWRDATA4_0_FUSEWRDATA_HDMI_LANE2_CALIB__PRI_ALIAS_1_FIELD                       (_MK_MASK_CONST(0x1) << FUSE_FUSEWRDATA4_0_FUSEWRDATA_HDMI_LANE2_CALIB__PRI_ALIAS_1_SHIFT)
+#define FUSE_FUSEWRDATA4_0_FUSEWRDATA_HDMI_LANE2_CALIB__PRI_ALIAS_1_RANGE                       0:0
+#define FUSE_FUSEWRDATA4_0_FUSEWRDATA_HDMI_LANE2_CALIB__PRI_ALIAS_1_WOFFSET                     0x0
+#define FUSE_FUSEWRDATA4_0_FUSEWRDATA_HDMI_LANE2_CALIB__PRI_ALIAS_1_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA4_0_FUSEWRDATA_HDMI_LANE2_CALIB__PRI_ALIAS_1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FUSE_FUSEWRDATA4_0_FUSEWRDATA_HDMI_LANE2_CALIB__PRI_ALIAS_1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA4_0_FUSEWRDATA_HDMI_LANE2_CALIB__PRI_ALIAS_1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA4_0_FUSEWRDATA_HDMI_LANE3_CALIB__PRI_ALIAS_0_SHIFT                       _MK_SHIFT_CONST(1)
+#define FUSE_FUSEWRDATA4_0_FUSEWRDATA_HDMI_LANE3_CALIB__PRI_ALIAS_0_FIELD                       (_MK_MASK_CONST(0x3f) << FUSE_FUSEWRDATA4_0_FUSEWRDATA_HDMI_LANE3_CALIB__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA4_0_FUSEWRDATA_HDMI_LANE3_CALIB__PRI_ALIAS_0_RANGE                       6:1
+#define FUSE_FUSEWRDATA4_0_FUSEWRDATA_HDMI_LANE3_CALIB__PRI_ALIAS_0_WOFFSET                     0x0
+#define FUSE_FUSEWRDATA4_0_FUSEWRDATA_HDMI_LANE3_CALIB__PRI_ALIAS_0_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA4_0_FUSEWRDATA_HDMI_LANE3_CALIB__PRI_ALIAS_0_DEFAULT_MASK                        _MK_MASK_CONST(0x3f)
+#define FUSE_FUSEWRDATA4_0_FUSEWRDATA_HDMI_LANE3_CALIB__PRI_ALIAS_0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA4_0_FUSEWRDATA_HDMI_LANE3_CALIB__PRI_ALIAS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA4_0_FUSEWRDATA_SECURITY_MODE__PRI_ALIAS_0_SHIFT                  _MK_SHIFT_CONST(7)
+#define FUSE_FUSEWRDATA4_0_FUSEWRDATA_SECURITY_MODE__PRI_ALIAS_0_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_FUSEWRDATA4_0_FUSEWRDATA_SECURITY_MODE__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA4_0_FUSEWRDATA_SECURITY_MODE__PRI_ALIAS_0_RANGE                  7:7
+#define FUSE_FUSEWRDATA4_0_FUSEWRDATA_SECURITY_MODE__PRI_ALIAS_0_WOFFSET                        0x0
+#define FUSE_FUSEWRDATA4_0_FUSEWRDATA_SECURITY_MODE__PRI_ALIAS_0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA4_0_FUSEWRDATA_SECURITY_MODE__PRI_ALIAS_0_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_FUSEWRDATA4_0_FUSEWRDATA_SECURITY_MODE__PRI_ALIAS_0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA4_0_FUSEWRDATA_SECURITY_MODE__PRI_ALIAS_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA4_0_FUSEWRDATA_PRIVATE_KEY0__PRI_ALIAS_0_SHIFT                   _MK_SHIFT_CONST(8)
+#define FUSE_FUSEWRDATA4_0_FUSEWRDATA_PRIVATE_KEY0__PRI_ALIAS_0_FIELD                   (_MK_MASK_CONST(0xffffff) << FUSE_FUSEWRDATA4_0_FUSEWRDATA_PRIVATE_KEY0__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA4_0_FUSEWRDATA_PRIVATE_KEY0__PRI_ALIAS_0_RANGE                   31:8
+#define FUSE_FUSEWRDATA4_0_FUSEWRDATA_PRIVATE_KEY0__PRI_ALIAS_0_WOFFSET                 0x0
+#define FUSE_FUSEWRDATA4_0_FUSEWRDATA_PRIVATE_KEY0__PRI_ALIAS_0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA4_0_FUSEWRDATA_PRIVATE_KEY0__PRI_ALIAS_0_DEFAULT_MASK                    _MK_MASK_CONST(0xffffff)
+#define FUSE_FUSEWRDATA4_0_FUSEWRDATA_PRIVATE_KEY0__PRI_ALIAS_0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA4_0_FUSEWRDATA_PRIVATE_KEY0__PRI_ALIAS_0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_FUSEWRDATA5_0  
+#define FUSE_FUSEWRDATA5_0                      _MK_ADDR_CONST(0x78)
+#define FUSE_FUSEWRDATA5_0_WORD_COUNT                   0x1
+#define FUSE_FUSEWRDATA5_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA5_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA5_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA5_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA5_0_READ_MASK                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA5_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA5_0_FUSEWRDATA5_SHIFT                    _MK_SHIFT_CONST(0)
+#define FUSE_FUSEWRDATA5_0_FUSEWRDATA5_FIELD                    (_MK_MASK_CONST(0xffffffff) << FUSE_FUSEWRDATA5_0_FUSEWRDATA5_SHIFT)
+#define FUSE_FUSEWRDATA5_0_FUSEWRDATA5_RANGE                    31:0
+#define FUSE_FUSEWRDATA5_0_FUSEWRDATA5_WOFFSET                  0x0
+#define FUSE_FUSEWRDATA5_0_FUSEWRDATA5_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA5_0_FUSEWRDATA5_DEFAULT_MASK                     _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA5_0_FUSEWRDATA5_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA5_0_FUSEWRDATA5_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA5_0_FUSEWRDATA_PRIVATE_KEY0__PRI_ALIAS_1_SHIFT                   _MK_SHIFT_CONST(0)
+#define FUSE_FUSEWRDATA5_0_FUSEWRDATA_PRIVATE_KEY0__PRI_ALIAS_1_FIELD                   (_MK_MASK_CONST(0xff) << FUSE_FUSEWRDATA5_0_FUSEWRDATA_PRIVATE_KEY0__PRI_ALIAS_1_SHIFT)
+#define FUSE_FUSEWRDATA5_0_FUSEWRDATA_PRIVATE_KEY0__PRI_ALIAS_1_RANGE                   7:0
+#define FUSE_FUSEWRDATA5_0_FUSEWRDATA_PRIVATE_KEY0__PRI_ALIAS_1_WOFFSET                 0x0
+#define FUSE_FUSEWRDATA5_0_FUSEWRDATA_PRIVATE_KEY0__PRI_ALIAS_1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA5_0_FUSEWRDATA_PRIVATE_KEY0__PRI_ALIAS_1_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define FUSE_FUSEWRDATA5_0_FUSEWRDATA_PRIVATE_KEY0__PRI_ALIAS_1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA5_0_FUSEWRDATA_PRIVATE_KEY0__PRI_ALIAS_1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA5_0_FUSEWRDATA_PRIVATE_KEY1__PRI_ALIAS_0_SHIFT                   _MK_SHIFT_CONST(8)
+#define FUSE_FUSEWRDATA5_0_FUSEWRDATA_PRIVATE_KEY1__PRI_ALIAS_0_FIELD                   (_MK_MASK_CONST(0xffffff) << FUSE_FUSEWRDATA5_0_FUSEWRDATA_PRIVATE_KEY1__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA5_0_FUSEWRDATA_PRIVATE_KEY1__PRI_ALIAS_0_RANGE                   31:8
+#define FUSE_FUSEWRDATA5_0_FUSEWRDATA_PRIVATE_KEY1__PRI_ALIAS_0_WOFFSET                 0x0
+#define FUSE_FUSEWRDATA5_0_FUSEWRDATA_PRIVATE_KEY1__PRI_ALIAS_0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA5_0_FUSEWRDATA_PRIVATE_KEY1__PRI_ALIAS_0_DEFAULT_MASK                    _MK_MASK_CONST(0xffffff)
+#define FUSE_FUSEWRDATA5_0_FUSEWRDATA_PRIVATE_KEY1__PRI_ALIAS_0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA5_0_FUSEWRDATA_PRIVATE_KEY1__PRI_ALIAS_0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_FUSEWRDATA6_0  
+#define FUSE_FUSEWRDATA6_0                      _MK_ADDR_CONST(0x7c)
+#define FUSE_FUSEWRDATA6_0_WORD_COUNT                   0x1
+#define FUSE_FUSEWRDATA6_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA6_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA6_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA6_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA6_0_READ_MASK                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA6_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA6_0_FUSEWRDATA6_SHIFT                    _MK_SHIFT_CONST(0)
+#define FUSE_FUSEWRDATA6_0_FUSEWRDATA6_FIELD                    (_MK_MASK_CONST(0xffffffff) << FUSE_FUSEWRDATA6_0_FUSEWRDATA6_SHIFT)
+#define FUSE_FUSEWRDATA6_0_FUSEWRDATA6_RANGE                    31:0
+#define FUSE_FUSEWRDATA6_0_FUSEWRDATA6_WOFFSET                  0x0
+#define FUSE_FUSEWRDATA6_0_FUSEWRDATA6_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA6_0_FUSEWRDATA6_DEFAULT_MASK                     _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA6_0_FUSEWRDATA6_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA6_0_FUSEWRDATA6_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA6_0_FUSEWRDATA_PRIVATE_KEY1__PRI_ALIAS_1_SHIFT                   _MK_SHIFT_CONST(0)
+#define FUSE_FUSEWRDATA6_0_FUSEWRDATA_PRIVATE_KEY1__PRI_ALIAS_1_FIELD                   (_MK_MASK_CONST(0xff) << FUSE_FUSEWRDATA6_0_FUSEWRDATA_PRIVATE_KEY1__PRI_ALIAS_1_SHIFT)
+#define FUSE_FUSEWRDATA6_0_FUSEWRDATA_PRIVATE_KEY1__PRI_ALIAS_1_RANGE                   7:0
+#define FUSE_FUSEWRDATA6_0_FUSEWRDATA_PRIVATE_KEY1__PRI_ALIAS_1_WOFFSET                 0x0
+#define FUSE_FUSEWRDATA6_0_FUSEWRDATA_PRIVATE_KEY1__PRI_ALIAS_1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA6_0_FUSEWRDATA_PRIVATE_KEY1__PRI_ALIAS_1_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define FUSE_FUSEWRDATA6_0_FUSEWRDATA_PRIVATE_KEY1__PRI_ALIAS_1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA6_0_FUSEWRDATA_PRIVATE_KEY1__PRI_ALIAS_1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA6_0_FUSEWRDATA_PRIVATE_KEY2__PRI_ALIAS_0_SHIFT                   _MK_SHIFT_CONST(8)
+#define FUSE_FUSEWRDATA6_0_FUSEWRDATA_PRIVATE_KEY2__PRI_ALIAS_0_FIELD                   (_MK_MASK_CONST(0xffffff) << FUSE_FUSEWRDATA6_0_FUSEWRDATA_PRIVATE_KEY2__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA6_0_FUSEWRDATA_PRIVATE_KEY2__PRI_ALIAS_0_RANGE                   31:8
+#define FUSE_FUSEWRDATA6_0_FUSEWRDATA_PRIVATE_KEY2__PRI_ALIAS_0_WOFFSET                 0x0
+#define FUSE_FUSEWRDATA6_0_FUSEWRDATA_PRIVATE_KEY2__PRI_ALIAS_0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA6_0_FUSEWRDATA_PRIVATE_KEY2__PRI_ALIAS_0_DEFAULT_MASK                    _MK_MASK_CONST(0xffffff)
+#define FUSE_FUSEWRDATA6_0_FUSEWRDATA_PRIVATE_KEY2__PRI_ALIAS_0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA6_0_FUSEWRDATA_PRIVATE_KEY2__PRI_ALIAS_0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_FUSEWRDATA7_0  
+#define FUSE_FUSEWRDATA7_0                      _MK_ADDR_CONST(0x80)
+#define FUSE_FUSEWRDATA7_0_WORD_COUNT                   0x1
+#define FUSE_FUSEWRDATA7_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA7_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA7_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA7_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA7_0_READ_MASK                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA7_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA7_0_FUSEWRDATA7_SHIFT                    _MK_SHIFT_CONST(0)
+#define FUSE_FUSEWRDATA7_0_FUSEWRDATA7_FIELD                    (_MK_MASK_CONST(0xffffffff) << FUSE_FUSEWRDATA7_0_FUSEWRDATA7_SHIFT)
+#define FUSE_FUSEWRDATA7_0_FUSEWRDATA7_RANGE                    31:0
+#define FUSE_FUSEWRDATA7_0_FUSEWRDATA7_WOFFSET                  0x0
+#define FUSE_FUSEWRDATA7_0_FUSEWRDATA7_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA7_0_FUSEWRDATA7_DEFAULT_MASK                     _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA7_0_FUSEWRDATA7_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA7_0_FUSEWRDATA7_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA7_0_FUSEWRDATA_PRIVATE_KEY2__PRI_ALIAS_1_SHIFT                   _MK_SHIFT_CONST(0)
+#define FUSE_FUSEWRDATA7_0_FUSEWRDATA_PRIVATE_KEY2__PRI_ALIAS_1_FIELD                   (_MK_MASK_CONST(0xff) << FUSE_FUSEWRDATA7_0_FUSEWRDATA_PRIVATE_KEY2__PRI_ALIAS_1_SHIFT)
+#define FUSE_FUSEWRDATA7_0_FUSEWRDATA_PRIVATE_KEY2__PRI_ALIAS_1_RANGE                   7:0
+#define FUSE_FUSEWRDATA7_0_FUSEWRDATA_PRIVATE_KEY2__PRI_ALIAS_1_WOFFSET                 0x0
+#define FUSE_FUSEWRDATA7_0_FUSEWRDATA_PRIVATE_KEY2__PRI_ALIAS_1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA7_0_FUSEWRDATA_PRIVATE_KEY2__PRI_ALIAS_1_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define FUSE_FUSEWRDATA7_0_FUSEWRDATA_PRIVATE_KEY2__PRI_ALIAS_1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA7_0_FUSEWRDATA_PRIVATE_KEY2__PRI_ALIAS_1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA7_0_FUSEWRDATA_PRIVATE_KEY3__PRI_ALIAS_0_SHIFT                   _MK_SHIFT_CONST(8)
+#define FUSE_FUSEWRDATA7_0_FUSEWRDATA_PRIVATE_KEY3__PRI_ALIAS_0_FIELD                   (_MK_MASK_CONST(0xffffff) << FUSE_FUSEWRDATA7_0_FUSEWRDATA_PRIVATE_KEY3__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA7_0_FUSEWRDATA_PRIVATE_KEY3__PRI_ALIAS_0_RANGE                   31:8
+#define FUSE_FUSEWRDATA7_0_FUSEWRDATA_PRIVATE_KEY3__PRI_ALIAS_0_WOFFSET                 0x0
+#define FUSE_FUSEWRDATA7_0_FUSEWRDATA_PRIVATE_KEY3__PRI_ALIAS_0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA7_0_FUSEWRDATA_PRIVATE_KEY3__PRI_ALIAS_0_DEFAULT_MASK                    _MK_MASK_CONST(0xffffff)
+#define FUSE_FUSEWRDATA7_0_FUSEWRDATA_PRIVATE_KEY3__PRI_ALIAS_0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA7_0_FUSEWRDATA_PRIVATE_KEY3__PRI_ALIAS_0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_FUSEWRDATA8_0  
+#define FUSE_FUSEWRDATA8_0                      _MK_ADDR_CONST(0x84)
+#define FUSE_FUSEWRDATA8_0_WORD_COUNT                   0x1
+#define FUSE_FUSEWRDATA8_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA8_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA8_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA8_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA8_0_READ_MASK                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA8_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA8_0_FUSEWRDATA8_SHIFT                    _MK_SHIFT_CONST(0)
+#define FUSE_FUSEWRDATA8_0_FUSEWRDATA8_FIELD                    (_MK_MASK_CONST(0xffffffff) << FUSE_FUSEWRDATA8_0_FUSEWRDATA8_SHIFT)
+#define FUSE_FUSEWRDATA8_0_FUSEWRDATA8_RANGE                    31:0
+#define FUSE_FUSEWRDATA8_0_FUSEWRDATA8_WOFFSET                  0x0
+#define FUSE_FUSEWRDATA8_0_FUSEWRDATA8_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA8_0_FUSEWRDATA8_DEFAULT_MASK                     _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA8_0_FUSEWRDATA8_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA8_0_FUSEWRDATA8_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA8_0_FUSEWRDATA_PRIVATE_KEY3__PRI_ALIAS_1_SHIFT                   _MK_SHIFT_CONST(0)
+#define FUSE_FUSEWRDATA8_0_FUSEWRDATA_PRIVATE_KEY3__PRI_ALIAS_1_FIELD                   (_MK_MASK_CONST(0xff) << FUSE_FUSEWRDATA8_0_FUSEWRDATA_PRIVATE_KEY3__PRI_ALIAS_1_SHIFT)
+#define FUSE_FUSEWRDATA8_0_FUSEWRDATA_PRIVATE_KEY3__PRI_ALIAS_1_RANGE                   7:0
+#define FUSE_FUSEWRDATA8_0_FUSEWRDATA_PRIVATE_KEY3__PRI_ALIAS_1_WOFFSET                 0x0
+#define FUSE_FUSEWRDATA8_0_FUSEWRDATA_PRIVATE_KEY3__PRI_ALIAS_1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA8_0_FUSEWRDATA_PRIVATE_KEY3__PRI_ALIAS_1_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define FUSE_FUSEWRDATA8_0_FUSEWRDATA_PRIVATE_KEY3__PRI_ALIAS_1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA8_0_FUSEWRDATA_PRIVATE_KEY3__PRI_ALIAS_1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA8_0_FUSEWRDATA_PRIVATE_KEY4__PRI_ALIAS_0_SHIFT                   _MK_SHIFT_CONST(8)
+#define FUSE_FUSEWRDATA8_0_FUSEWRDATA_PRIVATE_KEY4__PRI_ALIAS_0_FIELD                   (_MK_MASK_CONST(0xffffff) << FUSE_FUSEWRDATA8_0_FUSEWRDATA_PRIVATE_KEY4__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA8_0_FUSEWRDATA_PRIVATE_KEY4__PRI_ALIAS_0_RANGE                   31:8
+#define FUSE_FUSEWRDATA8_0_FUSEWRDATA_PRIVATE_KEY4__PRI_ALIAS_0_WOFFSET                 0x0
+#define FUSE_FUSEWRDATA8_0_FUSEWRDATA_PRIVATE_KEY4__PRI_ALIAS_0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA8_0_FUSEWRDATA_PRIVATE_KEY4__PRI_ALIAS_0_DEFAULT_MASK                    _MK_MASK_CONST(0xffffff)
+#define FUSE_FUSEWRDATA8_0_FUSEWRDATA_PRIVATE_KEY4__PRI_ALIAS_0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA8_0_FUSEWRDATA_PRIVATE_KEY4__PRI_ALIAS_0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_FUSEWRDATA9_0  
+#define FUSE_FUSEWRDATA9_0                      _MK_ADDR_CONST(0x88)
+#define FUSE_FUSEWRDATA9_0_WORD_COUNT                   0x1
+#define FUSE_FUSEWRDATA9_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA9_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA9_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA9_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA9_0_READ_MASK                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA9_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA9_SHIFT                    _MK_SHIFT_CONST(0)
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA9_FIELD                    (_MK_MASK_CONST(0xffffffff) << FUSE_FUSEWRDATA9_0_FUSEWRDATA9_SHIFT)
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA9_RANGE                    31:0
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA9_WOFFSET                  0x0
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA9_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA9_DEFAULT_MASK                     _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA9_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA9_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_MASTER_ENABLE__RED_ALIAS_0_SHIFT                  _MK_SHIFT_CONST(24)
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_MASTER_ENABLE__RED_ALIAS_0_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_FUSEWRDATA9_0_FUSEWRDATA_MASTER_ENABLE__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_MASTER_ENABLE__RED_ALIAS_0_RANGE                  24:24
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_MASTER_ENABLE__RED_ALIAS_0_WOFFSET                        0x0
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_MASTER_ENABLE__RED_ALIAS_0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_MASTER_ENABLE__RED_ALIAS_0_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_MASTER_ENABLE__RED_ALIAS_0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_MASTER_ENABLE__RED_ALIAS_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_MASTER_DISABLE__RED_ALIAS_0_SHIFT                 _MK_SHIFT_CONST(25)
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_MASTER_DISABLE__RED_ALIAS_0_FIELD                 (_MK_MASK_CONST(0x1) << FUSE_FUSEWRDATA9_0_FUSEWRDATA_MASTER_DISABLE__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_MASTER_DISABLE__RED_ALIAS_0_RANGE                 25:25
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_MASTER_DISABLE__RED_ALIAS_0_WOFFSET                       0x0
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_MASTER_DISABLE__RED_ALIAS_0_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_MASTER_DISABLE__RED_ALIAS_0_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_MASTER_DISABLE__RED_ALIAS_0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_MASTER_DISABLE__RED_ALIAS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_BYPASS__RED_ALIAS_0_SHIFT                 _MK_SHIFT_CONST(26)
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_BYPASS__RED_ALIAS_0_FIELD                 (_MK_MASK_CONST(0x1) << FUSE_FUSEWRDATA9_0_FUSEWRDATA_BYPASS__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_BYPASS__RED_ALIAS_0_RANGE                 26:26
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_BYPASS__RED_ALIAS_0_WOFFSET                       0x0
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_BYPASS__RED_ALIAS_0_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_BYPASS__RED_ALIAS_0_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_BYPASS__RED_ALIAS_0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_BYPASS__RED_ALIAS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_RESERVE_BIT__RED_ALIAS_0_SHIFT                    _MK_SHIFT_CONST(27)
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_RESERVE_BIT__RED_ALIAS_0_FIELD                    (_MK_MASK_CONST(0x1) << FUSE_FUSEWRDATA9_0_FUSEWRDATA_RESERVE_BIT__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_RESERVE_BIT__RED_ALIAS_0_RANGE                    27:27
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_RESERVE_BIT__RED_ALIAS_0_WOFFSET                  0x0
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_RESERVE_BIT__RED_ALIAS_0_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_RESERVE_BIT__RED_ALIAS_0_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_RESERVE_BIT__RED_ALIAS_0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_RESERVE_BIT__RED_ALIAS_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_PRODUCTION_MODE__RED_ALIAS_0_SHIFT                        _MK_SHIFT_CONST(28)
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_PRODUCTION_MODE__RED_ALIAS_0_FIELD                        (_MK_MASK_CONST(0x1) << FUSE_FUSEWRDATA9_0_FUSEWRDATA_PRODUCTION_MODE__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_PRODUCTION_MODE__RED_ALIAS_0_RANGE                        28:28
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_PRODUCTION_MODE__RED_ALIAS_0_WOFFSET                      0x0
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_PRODUCTION_MODE__RED_ALIAS_0_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_PRODUCTION_MODE__RED_ALIAS_0_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_PRODUCTION_MODE__RED_ALIAS_0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_PRODUCTION_MODE__RED_ALIAS_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_JTAG_SECUREID_VALID__RED_ALIAS_0_SHIFT                    _MK_SHIFT_CONST(29)
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_JTAG_SECUREID_VALID__RED_ALIAS_0_FIELD                    (_MK_MASK_CONST(0x1) << FUSE_FUSEWRDATA9_0_FUSEWRDATA_JTAG_SECUREID_VALID__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_JTAG_SECUREID_VALID__RED_ALIAS_0_RANGE                    29:29
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_JTAG_SECUREID_VALID__RED_ALIAS_0_WOFFSET                  0x0
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_JTAG_SECUREID_VALID__RED_ALIAS_0_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_JTAG_SECUREID_VALID__RED_ALIAS_0_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_JTAG_SECUREID_VALID__RED_ALIAS_0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_JTAG_SECUREID_VALID__RED_ALIAS_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_SKU_INFO__RED_ALIAS_0_SHIFT                       _MK_SHIFT_CONST(30)
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_SKU_INFO__RED_ALIAS_0_FIELD                       (_MK_MASK_CONST(0x3) << FUSE_FUSEWRDATA9_0_FUSEWRDATA_SKU_INFO__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_SKU_INFO__RED_ALIAS_0_RANGE                       31:30
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_SKU_INFO__RED_ALIAS_0_WOFFSET                     0x0
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_SKU_INFO__RED_ALIAS_0_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_SKU_INFO__RED_ALIAS_0_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_SKU_INFO__RED_ALIAS_0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_SKU_INFO__RED_ALIAS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_PRIVATE_KEY4__PRI_ALIAS_1_SHIFT                   _MK_SHIFT_CONST(0)
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_PRIVATE_KEY4__PRI_ALIAS_1_FIELD                   (_MK_MASK_CONST(0xff) << FUSE_FUSEWRDATA9_0_FUSEWRDATA_PRIVATE_KEY4__PRI_ALIAS_1_SHIFT)
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_PRIVATE_KEY4__PRI_ALIAS_1_RANGE                   7:0
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_PRIVATE_KEY4__PRI_ALIAS_1_WOFFSET                 0x0
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_PRIVATE_KEY4__PRI_ALIAS_1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_PRIVATE_KEY4__PRI_ALIAS_1_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_PRIVATE_KEY4__PRI_ALIAS_1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_PRIVATE_KEY4__PRI_ALIAS_1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_ARM_JTAG_DIS__PRI_ALIAS_0_SHIFT                   _MK_SHIFT_CONST(8)
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_ARM_JTAG_DIS__PRI_ALIAS_0_FIELD                   (_MK_MASK_CONST(0x1) << FUSE_FUSEWRDATA9_0_FUSEWRDATA_ARM_JTAG_DIS__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_ARM_JTAG_DIS__PRI_ALIAS_0_RANGE                   8:8
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_ARM_JTAG_DIS__PRI_ALIAS_0_WOFFSET                 0x0
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_ARM_JTAG_DIS__PRI_ALIAS_0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_ARM_JTAG_DIS__PRI_ALIAS_0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_ARM_JTAG_DIS__PRI_ALIAS_0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_ARM_JTAG_DIS__PRI_ALIAS_0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_BOOT_DEVICE_INFO__PRI_ALIAS_0_SHIFT                       _MK_SHIFT_CONST(9)
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_BOOT_DEVICE_INFO__PRI_ALIAS_0_FIELD                       (_MK_MASK_CONST(0x7f) << FUSE_FUSEWRDATA9_0_FUSEWRDATA_BOOT_DEVICE_INFO__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_BOOT_DEVICE_INFO__PRI_ALIAS_0_RANGE                       15:9
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_BOOT_DEVICE_INFO__PRI_ALIAS_0_WOFFSET                     0x0
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_BOOT_DEVICE_INFO__PRI_ALIAS_0_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_BOOT_DEVICE_INFO__PRI_ALIAS_0_DEFAULT_MASK                        _MK_MASK_CONST(0x7f)
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_BOOT_DEVICE_INFO__PRI_ALIAS_0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_BOOT_DEVICE_INFO__PRI_ALIAS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_RESERVED_SW__PRI_ALIAS_0_SHIFT                    _MK_SHIFT_CONST(16)
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_RESERVED_SW__PRI_ALIAS_0_FIELD                    (_MK_MASK_CONST(0xff) << FUSE_FUSEWRDATA9_0_FUSEWRDATA_RESERVED_SW__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_RESERVED_SW__PRI_ALIAS_0_RANGE                    23:16
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_RESERVED_SW__PRI_ALIAS_0_WOFFSET                  0x0
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_RESERVED_SW__PRI_ALIAS_0_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_RESERVED_SW__PRI_ALIAS_0_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_RESERVED_SW__PRI_ALIAS_0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_RESERVED_SW__PRI_ALIAS_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_FUSEWRDATA10_0  
+#define FUSE_FUSEWRDATA10_0                     _MK_ADDR_CONST(0x8c)
+#define FUSE_FUSEWRDATA10_0_WORD_COUNT                  0x1
+#define FUSE_FUSEWRDATA10_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA10_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA10_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA10_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA10_0_READ_MASK                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA10_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA10_0_FUSEWRDATA10_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_FUSEWRDATA10_0_FUSEWRDATA10_FIELD                  (_MK_MASK_CONST(0xffffffff) << FUSE_FUSEWRDATA10_0_FUSEWRDATA10_SHIFT)
+#define FUSE_FUSEWRDATA10_0_FUSEWRDATA10_RANGE                  31:0
+#define FUSE_FUSEWRDATA10_0_FUSEWRDATA10_WOFFSET                        0x0
+#define FUSE_FUSEWRDATA10_0_FUSEWRDATA10_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA10_0_FUSEWRDATA10_DEFAULT_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA10_0_FUSEWRDATA10_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA10_0_FUSEWRDATA10_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA10_0_FUSEWRDATA_SKU_INFO__RED_ALIAS_1_SHIFT                      _MK_SHIFT_CONST(0)
+#define FUSE_FUSEWRDATA10_0_FUSEWRDATA_SKU_INFO__RED_ALIAS_1_FIELD                      (_MK_MASK_CONST(0x3f) << FUSE_FUSEWRDATA10_0_FUSEWRDATA_SKU_INFO__RED_ALIAS_1_SHIFT)
+#define FUSE_FUSEWRDATA10_0_FUSEWRDATA_SKU_INFO__RED_ALIAS_1_RANGE                      5:0
+#define FUSE_FUSEWRDATA10_0_FUSEWRDATA_SKU_INFO__RED_ALIAS_1_WOFFSET                    0x0
+#define FUSE_FUSEWRDATA10_0_FUSEWRDATA_SKU_INFO__RED_ALIAS_1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA10_0_FUSEWRDATA_SKU_INFO__RED_ALIAS_1_DEFAULT_MASK                       _MK_MASK_CONST(0x3f)
+#define FUSE_FUSEWRDATA10_0_FUSEWRDATA_SKU_INFO__RED_ALIAS_1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA10_0_FUSEWRDATA_SKU_INFO__RED_ALIAS_1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA10_0_FUSEWRDATA_PROCESS_CALIB__RED_ALIAS_0_SHIFT                 _MK_SHIFT_CONST(6)
+#define FUSE_FUSEWRDATA10_0_FUSEWRDATA_PROCESS_CALIB__RED_ALIAS_0_FIELD                 (_MK_MASK_CONST(0x3) << FUSE_FUSEWRDATA10_0_FUSEWRDATA_PROCESS_CALIB__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA10_0_FUSEWRDATA_PROCESS_CALIB__RED_ALIAS_0_RANGE                 7:6
+#define FUSE_FUSEWRDATA10_0_FUSEWRDATA_PROCESS_CALIB__RED_ALIAS_0_WOFFSET                       0x0
+#define FUSE_FUSEWRDATA10_0_FUSEWRDATA_PROCESS_CALIB__RED_ALIAS_0_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA10_0_FUSEWRDATA_PROCESS_CALIB__RED_ALIAS_0_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define FUSE_FUSEWRDATA10_0_FUSEWRDATA_PROCESS_CALIB__RED_ALIAS_0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA10_0_FUSEWRDATA_PROCESS_CALIB__RED_ALIAS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA10_0_FUSEWRDATA_IO_CALIB__RED_ALIAS_0_SHIFT                      _MK_SHIFT_CONST(8)
+#define FUSE_FUSEWRDATA10_0_FUSEWRDATA_IO_CALIB__RED_ALIAS_0_FIELD                      (_MK_MASK_CONST(0x3ff) << FUSE_FUSEWRDATA10_0_FUSEWRDATA_IO_CALIB__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA10_0_FUSEWRDATA_IO_CALIB__RED_ALIAS_0_RANGE                      17:8
+#define FUSE_FUSEWRDATA10_0_FUSEWRDATA_IO_CALIB__RED_ALIAS_0_WOFFSET                    0x0
+#define FUSE_FUSEWRDATA10_0_FUSEWRDATA_IO_CALIB__RED_ALIAS_0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA10_0_FUSEWRDATA_IO_CALIB__RED_ALIAS_0_DEFAULT_MASK                       _MK_MASK_CONST(0x3ff)
+#define FUSE_FUSEWRDATA10_0_FUSEWRDATA_IO_CALIB__RED_ALIAS_0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA10_0_FUSEWRDATA_IO_CALIB__RED_ALIAS_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA10_0_FUSEWRDATA_DAC_CRT_CALIB__RED_ALIAS_0_SHIFT                 _MK_SHIFT_CONST(18)
+#define FUSE_FUSEWRDATA10_0_FUSEWRDATA_DAC_CRT_CALIB__RED_ALIAS_0_FIELD                 (_MK_MASK_CONST(0xff) << FUSE_FUSEWRDATA10_0_FUSEWRDATA_DAC_CRT_CALIB__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA10_0_FUSEWRDATA_DAC_CRT_CALIB__RED_ALIAS_0_RANGE                 25:18
+#define FUSE_FUSEWRDATA10_0_FUSEWRDATA_DAC_CRT_CALIB__RED_ALIAS_0_WOFFSET                       0x0
+#define FUSE_FUSEWRDATA10_0_FUSEWRDATA_DAC_CRT_CALIB__RED_ALIAS_0_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA10_0_FUSEWRDATA_DAC_CRT_CALIB__RED_ALIAS_0_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define FUSE_FUSEWRDATA10_0_FUSEWRDATA_DAC_CRT_CALIB__RED_ALIAS_0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA10_0_FUSEWRDATA_DAC_CRT_CALIB__RED_ALIAS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA10_0_FUSEWRDATA_DAC_HDTV_CALIB__RED_ALIAS_0_SHIFT                        _MK_SHIFT_CONST(26)
+#define FUSE_FUSEWRDATA10_0_FUSEWRDATA_DAC_HDTV_CALIB__RED_ALIAS_0_FIELD                        (_MK_MASK_CONST(0x3f) << FUSE_FUSEWRDATA10_0_FUSEWRDATA_DAC_HDTV_CALIB__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA10_0_FUSEWRDATA_DAC_HDTV_CALIB__RED_ALIAS_0_RANGE                        31:26
+#define FUSE_FUSEWRDATA10_0_FUSEWRDATA_DAC_HDTV_CALIB__RED_ALIAS_0_WOFFSET                      0x0
+#define FUSE_FUSEWRDATA10_0_FUSEWRDATA_DAC_HDTV_CALIB__RED_ALIAS_0_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA10_0_FUSEWRDATA_DAC_HDTV_CALIB__RED_ALIAS_0_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
+#define FUSE_FUSEWRDATA10_0_FUSEWRDATA_DAC_HDTV_CALIB__RED_ALIAS_0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA10_0_FUSEWRDATA_DAC_HDTV_CALIB__RED_ALIAS_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_FUSEWRDATA11_0  
+#define FUSE_FUSEWRDATA11_0                     _MK_ADDR_CONST(0x90)
+#define FUSE_FUSEWRDATA11_0_WORD_COUNT                  0x1
+#define FUSE_FUSEWRDATA11_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA11_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA11_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA11_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA11_0_READ_MASK                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA11_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA11_0_FUSEWRDATA11_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_FUSEWRDATA11_0_FUSEWRDATA11_FIELD                  (_MK_MASK_CONST(0xffffffff) << FUSE_FUSEWRDATA11_0_FUSEWRDATA11_SHIFT)
+#define FUSE_FUSEWRDATA11_0_FUSEWRDATA11_RANGE                  31:0
+#define FUSE_FUSEWRDATA11_0_FUSEWRDATA11_WOFFSET                        0x0
+#define FUSE_FUSEWRDATA11_0_FUSEWRDATA11_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA11_0_FUSEWRDATA11_DEFAULT_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA11_0_FUSEWRDATA11_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA11_0_FUSEWRDATA11_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA11_0_FUSEWRDATA_DAC_HDTV_CALIB__RED_ALIAS_1_SHIFT                        _MK_SHIFT_CONST(0)
+#define FUSE_FUSEWRDATA11_0_FUSEWRDATA_DAC_HDTV_CALIB__RED_ALIAS_1_FIELD                        (_MK_MASK_CONST(0x3) << FUSE_FUSEWRDATA11_0_FUSEWRDATA_DAC_HDTV_CALIB__RED_ALIAS_1_SHIFT)
+#define FUSE_FUSEWRDATA11_0_FUSEWRDATA_DAC_HDTV_CALIB__RED_ALIAS_1_RANGE                        1:0
+#define FUSE_FUSEWRDATA11_0_FUSEWRDATA_DAC_HDTV_CALIB__RED_ALIAS_1_WOFFSET                      0x0
+#define FUSE_FUSEWRDATA11_0_FUSEWRDATA_DAC_HDTV_CALIB__RED_ALIAS_1_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA11_0_FUSEWRDATA_DAC_HDTV_CALIB__RED_ALIAS_1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define FUSE_FUSEWRDATA11_0_FUSEWRDATA_DAC_HDTV_CALIB__RED_ALIAS_1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA11_0_FUSEWRDATA_DAC_HDTV_CALIB__RED_ALIAS_1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA11_0_FUSEWRDATA_DAC_SDTV_CALIB__RED_ALIAS_0_SHIFT                        _MK_SHIFT_CONST(2)
+#define FUSE_FUSEWRDATA11_0_FUSEWRDATA_DAC_SDTV_CALIB__RED_ALIAS_0_FIELD                        (_MK_MASK_CONST(0xff) << FUSE_FUSEWRDATA11_0_FUSEWRDATA_DAC_SDTV_CALIB__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA11_0_FUSEWRDATA_DAC_SDTV_CALIB__RED_ALIAS_0_RANGE                        9:2
+#define FUSE_FUSEWRDATA11_0_FUSEWRDATA_DAC_SDTV_CALIB__RED_ALIAS_0_WOFFSET                      0x0
+#define FUSE_FUSEWRDATA11_0_FUSEWRDATA_DAC_SDTV_CALIB__RED_ALIAS_0_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA11_0_FUSEWRDATA_DAC_SDTV_CALIB__RED_ALIAS_0_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
+#define FUSE_FUSEWRDATA11_0_FUSEWRDATA_DAC_SDTV_CALIB__RED_ALIAS_0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA11_0_FUSEWRDATA_DAC_SDTV_CALIB__RED_ALIAS_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA11_0_FUSEWRDATA_CMC_DATARAM0_0__RED_ALIAS_0_SHIFT                        _MK_SHIFT_CONST(10)
+#define FUSE_FUSEWRDATA11_0_FUSEWRDATA_CMC_DATARAM0_0__RED_ALIAS_0_FIELD                        (_MK_MASK_CONST(0x7f) << FUSE_FUSEWRDATA11_0_FUSEWRDATA_CMC_DATARAM0_0__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA11_0_FUSEWRDATA_CMC_DATARAM0_0__RED_ALIAS_0_RANGE                        16:10
+#define FUSE_FUSEWRDATA11_0_FUSEWRDATA_CMC_DATARAM0_0__RED_ALIAS_0_WOFFSET                      0x0
+#define FUSE_FUSEWRDATA11_0_FUSEWRDATA_CMC_DATARAM0_0__RED_ALIAS_0_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA11_0_FUSEWRDATA_CMC_DATARAM0_0__RED_ALIAS_0_DEFAULT_MASK                 _MK_MASK_CONST(0x7f)
+#define FUSE_FUSEWRDATA11_0_FUSEWRDATA_CMC_DATARAM0_0__RED_ALIAS_0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA11_0_FUSEWRDATA_CMC_DATARAM0_0__RED_ALIAS_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA11_0_FUSEWRDATA_CMC_DATARAM0_1__RED_ALIAS_0_SHIFT                        _MK_SHIFT_CONST(17)
+#define FUSE_FUSEWRDATA11_0_FUSEWRDATA_CMC_DATARAM0_1__RED_ALIAS_0_FIELD                        (_MK_MASK_CONST(0x7f) << FUSE_FUSEWRDATA11_0_FUSEWRDATA_CMC_DATARAM0_1__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA11_0_FUSEWRDATA_CMC_DATARAM0_1__RED_ALIAS_0_RANGE                        23:17
+#define FUSE_FUSEWRDATA11_0_FUSEWRDATA_CMC_DATARAM0_1__RED_ALIAS_0_WOFFSET                      0x0
+#define FUSE_FUSEWRDATA11_0_FUSEWRDATA_CMC_DATARAM0_1__RED_ALIAS_0_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA11_0_FUSEWRDATA_CMC_DATARAM0_1__RED_ALIAS_0_DEFAULT_MASK                 _MK_MASK_CONST(0x7f)
+#define FUSE_FUSEWRDATA11_0_FUSEWRDATA_CMC_DATARAM0_1__RED_ALIAS_0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA11_0_FUSEWRDATA_CMC_DATARAM0_1__RED_ALIAS_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA11_0_FUSEWRDATA_CMC_DATARAM0_2__RED_ALIAS_0_SHIFT                        _MK_SHIFT_CONST(24)
+#define FUSE_FUSEWRDATA11_0_FUSEWRDATA_CMC_DATARAM0_2__RED_ALIAS_0_FIELD                        (_MK_MASK_CONST(0x7f) << FUSE_FUSEWRDATA11_0_FUSEWRDATA_CMC_DATARAM0_2__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA11_0_FUSEWRDATA_CMC_DATARAM0_2__RED_ALIAS_0_RANGE                        30:24
+#define FUSE_FUSEWRDATA11_0_FUSEWRDATA_CMC_DATARAM0_2__RED_ALIAS_0_WOFFSET                      0x0
+#define FUSE_FUSEWRDATA11_0_FUSEWRDATA_CMC_DATARAM0_2__RED_ALIAS_0_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA11_0_FUSEWRDATA_CMC_DATARAM0_2__RED_ALIAS_0_DEFAULT_MASK                 _MK_MASK_CONST(0x7f)
+#define FUSE_FUSEWRDATA11_0_FUSEWRDATA_CMC_DATARAM0_2__RED_ALIAS_0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA11_0_FUSEWRDATA_CMC_DATARAM0_2__RED_ALIAS_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA11_0_FUSEWRDATA_CMC_DATARAM0_3__RED_ALIAS_0_SHIFT                        _MK_SHIFT_CONST(31)
+#define FUSE_FUSEWRDATA11_0_FUSEWRDATA_CMC_DATARAM0_3__RED_ALIAS_0_FIELD                        (_MK_MASK_CONST(0x1) << FUSE_FUSEWRDATA11_0_FUSEWRDATA_CMC_DATARAM0_3__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA11_0_FUSEWRDATA_CMC_DATARAM0_3__RED_ALIAS_0_RANGE                        31:31
+#define FUSE_FUSEWRDATA11_0_FUSEWRDATA_CMC_DATARAM0_3__RED_ALIAS_0_WOFFSET                      0x0
+#define FUSE_FUSEWRDATA11_0_FUSEWRDATA_CMC_DATARAM0_3__RED_ALIAS_0_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA11_0_FUSEWRDATA_CMC_DATARAM0_3__RED_ALIAS_0_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define FUSE_FUSEWRDATA11_0_FUSEWRDATA_CMC_DATARAM0_3__RED_ALIAS_0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA11_0_FUSEWRDATA_CMC_DATARAM0_3__RED_ALIAS_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_FUSEWRDATA12_0  
+#define FUSE_FUSEWRDATA12_0                     _MK_ADDR_CONST(0x94)
+#define FUSE_FUSEWRDATA12_0_WORD_COUNT                  0x1
+#define FUSE_FUSEWRDATA12_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA12_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA12_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA12_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA12_0_READ_MASK                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA12_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA12_0_FUSEWRDATA12_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_FUSEWRDATA12_0_FUSEWRDATA12_FIELD                  (_MK_MASK_CONST(0xffffffff) << FUSE_FUSEWRDATA12_0_FUSEWRDATA12_SHIFT)
+#define FUSE_FUSEWRDATA12_0_FUSEWRDATA12_RANGE                  31:0
+#define FUSE_FUSEWRDATA12_0_FUSEWRDATA12_WOFFSET                        0x0
+#define FUSE_FUSEWRDATA12_0_FUSEWRDATA12_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA12_0_FUSEWRDATA12_DEFAULT_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA12_0_FUSEWRDATA12_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA12_0_FUSEWRDATA12_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA12_0_FUSEWRDATA_CMC_DATARAM0_3__RED_ALIAS_1_SHIFT                        _MK_SHIFT_CONST(0)
+#define FUSE_FUSEWRDATA12_0_FUSEWRDATA_CMC_DATARAM0_3__RED_ALIAS_1_FIELD                        (_MK_MASK_CONST(0x3f) << FUSE_FUSEWRDATA12_0_FUSEWRDATA_CMC_DATARAM0_3__RED_ALIAS_1_SHIFT)
+#define FUSE_FUSEWRDATA12_0_FUSEWRDATA_CMC_DATARAM0_3__RED_ALIAS_1_RANGE                        5:0
+#define FUSE_FUSEWRDATA12_0_FUSEWRDATA_CMC_DATARAM0_3__RED_ALIAS_1_WOFFSET                      0x0
+#define FUSE_FUSEWRDATA12_0_FUSEWRDATA_CMC_DATARAM0_3__RED_ALIAS_1_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA12_0_FUSEWRDATA_CMC_DATARAM0_3__RED_ALIAS_1_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
+#define FUSE_FUSEWRDATA12_0_FUSEWRDATA_CMC_DATARAM0_3__RED_ALIAS_1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA12_0_FUSEWRDATA_CMC_DATARAM0_3__RED_ALIAS_1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA12_0_FUSEWRDATA_CMC_DATARAM1_0__RED_ALIAS_0_SHIFT                        _MK_SHIFT_CONST(6)
+#define FUSE_FUSEWRDATA12_0_FUSEWRDATA_CMC_DATARAM1_0__RED_ALIAS_0_FIELD                        (_MK_MASK_CONST(0x7f) << FUSE_FUSEWRDATA12_0_FUSEWRDATA_CMC_DATARAM1_0__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA12_0_FUSEWRDATA_CMC_DATARAM1_0__RED_ALIAS_0_RANGE                        12:6
+#define FUSE_FUSEWRDATA12_0_FUSEWRDATA_CMC_DATARAM1_0__RED_ALIAS_0_WOFFSET                      0x0
+#define FUSE_FUSEWRDATA12_0_FUSEWRDATA_CMC_DATARAM1_0__RED_ALIAS_0_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA12_0_FUSEWRDATA_CMC_DATARAM1_0__RED_ALIAS_0_DEFAULT_MASK                 _MK_MASK_CONST(0x7f)
+#define FUSE_FUSEWRDATA12_0_FUSEWRDATA_CMC_DATARAM1_0__RED_ALIAS_0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA12_0_FUSEWRDATA_CMC_DATARAM1_0__RED_ALIAS_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA12_0_FUSEWRDATA_CMC_DATARAM1_1__RED_ALIAS_0_SHIFT                        _MK_SHIFT_CONST(13)
+#define FUSE_FUSEWRDATA12_0_FUSEWRDATA_CMC_DATARAM1_1__RED_ALIAS_0_FIELD                        (_MK_MASK_CONST(0x7f) << FUSE_FUSEWRDATA12_0_FUSEWRDATA_CMC_DATARAM1_1__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA12_0_FUSEWRDATA_CMC_DATARAM1_1__RED_ALIAS_0_RANGE                        19:13
+#define FUSE_FUSEWRDATA12_0_FUSEWRDATA_CMC_DATARAM1_1__RED_ALIAS_0_WOFFSET                      0x0
+#define FUSE_FUSEWRDATA12_0_FUSEWRDATA_CMC_DATARAM1_1__RED_ALIAS_0_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA12_0_FUSEWRDATA_CMC_DATARAM1_1__RED_ALIAS_0_DEFAULT_MASK                 _MK_MASK_CONST(0x7f)
+#define FUSE_FUSEWRDATA12_0_FUSEWRDATA_CMC_DATARAM1_1__RED_ALIAS_0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA12_0_FUSEWRDATA_CMC_DATARAM1_1__RED_ALIAS_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA12_0_FUSEWRDATA_CMC_DATARAM1_2__RED_ALIAS_0_SHIFT                        _MK_SHIFT_CONST(20)
+#define FUSE_FUSEWRDATA12_0_FUSEWRDATA_CMC_DATARAM1_2__RED_ALIAS_0_FIELD                        (_MK_MASK_CONST(0x7f) << FUSE_FUSEWRDATA12_0_FUSEWRDATA_CMC_DATARAM1_2__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA12_0_FUSEWRDATA_CMC_DATARAM1_2__RED_ALIAS_0_RANGE                        26:20
+#define FUSE_FUSEWRDATA12_0_FUSEWRDATA_CMC_DATARAM1_2__RED_ALIAS_0_WOFFSET                      0x0
+#define FUSE_FUSEWRDATA12_0_FUSEWRDATA_CMC_DATARAM1_2__RED_ALIAS_0_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA12_0_FUSEWRDATA_CMC_DATARAM1_2__RED_ALIAS_0_DEFAULT_MASK                 _MK_MASK_CONST(0x7f)
+#define FUSE_FUSEWRDATA12_0_FUSEWRDATA_CMC_DATARAM1_2__RED_ALIAS_0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA12_0_FUSEWRDATA_CMC_DATARAM1_2__RED_ALIAS_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA12_0_FUSEWRDATA_CMC_DATARAM1_3__RED_ALIAS_0_SHIFT                        _MK_SHIFT_CONST(27)
+#define FUSE_FUSEWRDATA12_0_FUSEWRDATA_CMC_DATARAM1_3__RED_ALIAS_0_FIELD                        (_MK_MASK_CONST(0x1f) << FUSE_FUSEWRDATA12_0_FUSEWRDATA_CMC_DATARAM1_3__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA12_0_FUSEWRDATA_CMC_DATARAM1_3__RED_ALIAS_0_RANGE                        31:27
+#define FUSE_FUSEWRDATA12_0_FUSEWRDATA_CMC_DATARAM1_3__RED_ALIAS_0_WOFFSET                      0x0
+#define FUSE_FUSEWRDATA12_0_FUSEWRDATA_CMC_DATARAM1_3__RED_ALIAS_0_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA12_0_FUSEWRDATA_CMC_DATARAM1_3__RED_ALIAS_0_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define FUSE_FUSEWRDATA12_0_FUSEWRDATA_CMC_DATARAM1_3__RED_ALIAS_0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA12_0_FUSEWRDATA_CMC_DATARAM1_3__RED_ALIAS_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_FUSEWRDATA13_0  
+#define FUSE_FUSEWRDATA13_0                     _MK_ADDR_CONST(0x98)
+#define FUSE_FUSEWRDATA13_0_WORD_COUNT                  0x1
+#define FUSE_FUSEWRDATA13_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA13_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA13_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA13_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA13_0_READ_MASK                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA13_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA13_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA13_FIELD                  (_MK_MASK_CONST(0xffffffff) << FUSE_FUSEWRDATA13_0_FUSEWRDATA13_SHIFT)
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA13_RANGE                  31:0
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA13_WOFFSET                        0x0
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA13_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA13_DEFAULT_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA13_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA13_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_CMC_DATARAM1_3__RED_ALIAS_1_SHIFT                        _MK_SHIFT_CONST(0)
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_CMC_DATARAM1_3__RED_ALIAS_1_FIELD                        (_MK_MASK_CONST(0x3) << FUSE_FUSEWRDATA13_0_FUSEWRDATA_CMC_DATARAM1_3__RED_ALIAS_1_SHIFT)
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_CMC_DATARAM1_3__RED_ALIAS_1_RANGE                        1:0
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_CMC_DATARAM1_3__RED_ALIAS_1_WOFFSET                      0x0
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_CMC_DATARAM1_3__RED_ALIAS_1_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_CMC_DATARAM1_3__RED_ALIAS_1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_CMC_DATARAM1_3__RED_ALIAS_1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_CMC_DATARAM1_3__RED_ALIAS_1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_FA__RED_ALIAS_0_SHIFT                    _MK_SHIFT_CONST(2)
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_FA__RED_ALIAS_0_FIELD                    (_MK_MASK_CONST(0x1) << FUSE_FUSEWRDATA13_0_FUSEWRDATA_FA__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_FA__RED_ALIAS_0_RANGE                    2:2
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_FA__RED_ALIAS_0_WOFFSET                  0x0
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_FA__RED_ALIAS_0_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_FA__RED_ALIAS_0_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_FA__RED_ALIAS_0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_FA__RED_ALIAS_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_RESERVED_PRODUCTION__RED_ALIAS_0_SHIFT                   _MK_SHIFT_CONST(3)
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_RESERVED_PRODUCTION__RED_ALIAS_0_FIELD                   (_MK_MASK_CONST(0xf) << FUSE_FUSEWRDATA13_0_FUSEWRDATA_RESERVED_PRODUCTION__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_RESERVED_PRODUCTION__RED_ALIAS_0_RANGE                   6:3
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_RESERVED_PRODUCTION__RED_ALIAS_0_WOFFSET                 0x0
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_RESERVED_PRODUCTION__RED_ALIAS_0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_RESERVED_PRODUCTION__RED_ALIAS_0_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_RESERVED_PRODUCTION__RED_ALIAS_0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_RESERVED_PRODUCTION__RED_ALIAS_0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_HDMI_LANE0_CALIB__RED_ALIAS_0_SHIFT                      _MK_SHIFT_CONST(7)
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_HDMI_LANE0_CALIB__RED_ALIAS_0_FIELD                      (_MK_MASK_CONST(0x3f) << FUSE_FUSEWRDATA13_0_FUSEWRDATA_HDMI_LANE0_CALIB__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_HDMI_LANE0_CALIB__RED_ALIAS_0_RANGE                      12:7
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_HDMI_LANE0_CALIB__RED_ALIAS_0_WOFFSET                    0x0
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_HDMI_LANE0_CALIB__RED_ALIAS_0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_HDMI_LANE0_CALIB__RED_ALIAS_0_DEFAULT_MASK                       _MK_MASK_CONST(0x3f)
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_HDMI_LANE0_CALIB__RED_ALIAS_0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_HDMI_LANE0_CALIB__RED_ALIAS_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_HDMI_LANE1_CALIB__RED_ALIAS_0_SHIFT                      _MK_SHIFT_CONST(13)
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_HDMI_LANE1_CALIB__RED_ALIAS_0_FIELD                      (_MK_MASK_CONST(0x3f) << FUSE_FUSEWRDATA13_0_FUSEWRDATA_HDMI_LANE1_CALIB__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_HDMI_LANE1_CALIB__RED_ALIAS_0_RANGE                      18:13
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_HDMI_LANE1_CALIB__RED_ALIAS_0_WOFFSET                    0x0
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_HDMI_LANE1_CALIB__RED_ALIAS_0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_HDMI_LANE1_CALIB__RED_ALIAS_0_DEFAULT_MASK                       _MK_MASK_CONST(0x3f)
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_HDMI_LANE1_CALIB__RED_ALIAS_0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_HDMI_LANE1_CALIB__RED_ALIAS_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_HDMI_LANE2_CALIB__RED_ALIAS_0_SHIFT                      _MK_SHIFT_CONST(19)
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_HDMI_LANE2_CALIB__RED_ALIAS_0_FIELD                      (_MK_MASK_CONST(0x3f) << FUSE_FUSEWRDATA13_0_FUSEWRDATA_HDMI_LANE2_CALIB__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_HDMI_LANE2_CALIB__RED_ALIAS_0_RANGE                      24:19
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_HDMI_LANE2_CALIB__RED_ALIAS_0_WOFFSET                    0x0
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_HDMI_LANE2_CALIB__RED_ALIAS_0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_HDMI_LANE2_CALIB__RED_ALIAS_0_DEFAULT_MASK                       _MK_MASK_CONST(0x3f)
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_HDMI_LANE2_CALIB__RED_ALIAS_0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_HDMI_LANE2_CALIB__RED_ALIAS_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_HDMI_LANE3_CALIB__RED_ALIAS_0_SHIFT                      _MK_SHIFT_CONST(25)
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_HDMI_LANE3_CALIB__RED_ALIAS_0_FIELD                      (_MK_MASK_CONST(0x3f) << FUSE_FUSEWRDATA13_0_FUSEWRDATA_HDMI_LANE3_CALIB__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_HDMI_LANE3_CALIB__RED_ALIAS_0_RANGE                      30:25
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_HDMI_LANE3_CALIB__RED_ALIAS_0_WOFFSET                    0x0
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_HDMI_LANE3_CALIB__RED_ALIAS_0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_HDMI_LANE3_CALIB__RED_ALIAS_0_DEFAULT_MASK                       _MK_MASK_CONST(0x3f)
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_HDMI_LANE3_CALIB__RED_ALIAS_0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_HDMI_LANE3_CALIB__RED_ALIAS_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_SECURITY_MODE__RED_ALIAS_0_SHIFT                 _MK_SHIFT_CONST(31)
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_SECURITY_MODE__RED_ALIAS_0_FIELD                 (_MK_MASK_CONST(0x1) << FUSE_FUSEWRDATA13_0_FUSEWRDATA_SECURITY_MODE__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_SECURITY_MODE__RED_ALIAS_0_RANGE                 31:31
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_SECURITY_MODE__RED_ALIAS_0_WOFFSET                       0x0
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_SECURITY_MODE__RED_ALIAS_0_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_SECURITY_MODE__RED_ALIAS_0_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_SECURITY_MODE__RED_ALIAS_0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_SECURITY_MODE__RED_ALIAS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_FUSEWRDATA14_0  
+#define FUSE_FUSEWRDATA14_0                     _MK_ADDR_CONST(0x9c)
+#define FUSE_FUSEWRDATA14_0_WORD_COUNT                  0x1
+#define FUSE_FUSEWRDATA14_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA14_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA14_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA14_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA14_0_READ_MASK                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA14_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA14_0_FUSEWRDATA14_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_FUSEWRDATA14_0_FUSEWRDATA14_FIELD                  (_MK_MASK_CONST(0xffffffff) << FUSE_FUSEWRDATA14_0_FUSEWRDATA14_SHIFT)
+#define FUSE_FUSEWRDATA14_0_FUSEWRDATA14_RANGE                  31:0
+#define FUSE_FUSEWRDATA14_0_FUSEWRDATA14_WOFFSET                        0x0
+#define FUSE_FUSEWRDATA14_0_FUSEWRDATA14_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA14_0_FUSEWRDATA14_DEFAULT_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA14_0_FUSEWRDATA14_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA14_0_FUSEWRDATA14_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA14_0_FUSEWRDATA_PRIVATE_KEY0__RED_ALIAS_0_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_FUSEWRDATA14_0_FUSEWRDATA_PRIVATE_KEY0__RED_ALIAS_0_FIELD                  (_MK_MASK_CONST(0xffffffff) << FUSE_FUSEWRDATA14_0_FUSEWRDATA_PRIVATE_KEY0__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA14_0_FUSEWRDATA_PRIVATE_KEY0__RED_ALIAS_0_RANGE                  31:0
+#define FUSE_FUSEWRDATA14_0_FUSEWRDATA_PRIVATE_KEY0__RED_ALIAS_0_WOFFSET                        0x0
+#define FUSE_FUSEWRDATA14_0_FUSEWRDATA_PRIVATE_KEY0__RED_ALIAS_0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA14_0_FUSEWRDATA_PRIVATE_KEY0__RED_ALIAS_0_DEFAULT_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA14_0_FUSEWRDATA_PRIVATE_KEY0__RED_ALIAS_0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA14_0_FUSEWRDATA_PRIVATE_KEY0__RED_ALIAS_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_FUSEWRDATA15_0  
+#define FUSE_FUSEWRDATA15_0                     _MK_ADDR_CONST(0xa0)
+#define FUSE_FUSEWRDATA15_0_WORD_COUNT                  0x1
+#define FUSE_FUSEWRDATA15_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA15_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA15_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA15_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA15_0_READ_MASK                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA15_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA15_0_FUSEWRDATA15_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_FUSEWRDATA15_0_FUSEWRDATA15_FIELD                  (_MK_MASK_CONST(0xffffffff) << FUSE_FUSEWRDATA15_0_FUSEWRDATA15_SHIFT)
+#define FUSE_FUSEWRDATA15_0_FUSEWRDATA15_RANGE                  31:0
+#define FUSE_FUSEWRDATA15_0_FUSEWRDATA15_WOFFSET                        0x0
+#define FUSE_FUSEWRDATA15_0_FUSEWRDATA15_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA15_0_FUSEWRDATA15_DEFAULT_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA15_0_FUSEWRDATA15_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA15_0_FUSEWRDATA15_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA15_0_FUSEWRDATA_PRIVATE_KEY1__RED_ALIAS_0_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_FUSEWRDATA15_0_FUSEWRDATA_PRIVATE_KEY1__RED_ALIAS_0_FIELD                  (_MK_MASK_CONST(0xffffffff) << FUSE_FUSEWRDATA15_0_FUSEWRDATA_PRIVATE_KEY1__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA15_0_FUSEWRDATA_PRIVATE_KEY1__RED_ALIAS_0_RANGE                  31:0
+#define FUSE_FUSEWRDATA15_0_FUSEWRDATA_PRIVATE_KEY1__RED_ALIAS_0_WOFFSET                        0x0
+#define FUSE_FUSEWRDATA15_0_FUSEWRDATA_PRIVATE_KEY1__RED_ALIAS_0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA15_0_FUSEWRDATA_PRIVATE_KEY1__RED_ALIAS_0_DEFAULT_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA15_0_FUSEWRDATA_PRIVATE_KEY1__RED_ALIAS_0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA15_0_FUSEWRDATA_PRIVATE_KEY1__RED_ALIAS_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_FUSEWRDATA16_0  
+#define FUSE_FUSEWRDATA16_0                     _MK_ADDR_CONST(0xa4)
+#define FUSE_FUSEWRDATA16_0_WORD_COUNT                  0x1
+#define FUSE_FUSEWRDATA16_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA16_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA16_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA16_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA16_0_READ_MASK                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA16_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA16_0_FUSEWRDATA16_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_FUSEWRDATA16_0_FUSEWRDATA16_FIELD                  (_MK_MASK_CONST(0xffffffff) << FUSE_FUSEWRDATA16_0_FUSEWRDATA16_SHIFT)
+#define FUSE_FUSEWRDATA16_0_FUSEWRDATA16_RANGE                  31:0
+#define FUSE_FUSEWRDATA16_0_FUSEWRDATA16_WOFFSET                        0x0
+#define FUSE_FUSEWRDATA16_0_FUSEWRDATA16_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA16_0_FUSEWRDATA16_DEFAULT_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA16_0_FUSEWRDATA16_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA16_0_FUSEWRDATA16_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA16_0_FUSEWRDATA_PRIVATE_KEY2__RED_ALIAS_0_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_FUSEWRDATA16_0_FUSEWRDATA_PRIVATE_KEY2__RED_ALIAS_0_FIELD                  (_MK_MASK_CONST(0xffffffff) << FUSE_FUSEWRDATA16_0_FUSEWRDATA_PRIVATE_KEY2__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA16_0_FUSEWRDATA_PRIVATE_KEY2__RED_ALIAS_0_RANGE                  31:0
+#define FUSE_FUSEWRDATA16_0_FUSEWRDATA_PRIVATE_KEY2__RED_ALIAS_0_WOFFSET                        0x0
+#define FUSE_FUSEWRDATA16_0_FUSEWRDATA_PRIVATE_KEY2__RED_ALIAS_0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA16_0_FUSEWRDATA_PRIVATE_KEY2__RED_ALIAS_0_DEFAULT_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA16_0_FUSEWRDATA_PRIVATE_KEY2__RED_ALIAS_0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA16_0_FUSEWRDATA_PRIVATE_KEY2__RED_ALIAS_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_FUSEWRDATA17_0  
+#define FUSE_FUSEWRDATA17_0                     _MK_ADDR_CONST(0xa8)
+#define FUSE_FUSEWRDATA17_0_WORD_COUNT                  0x1
+#define FUSE_FUSEWRDATA17_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA17_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA17_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA17_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA17_0_READ_MASK                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA17_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA17_0_FUSEWRDATA17_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_FUSEWRDATA17_0_FUSEWRDATA17_FIELD                  (_MK_MASK_CONST(0xffffffff) << FUSE_FUSEWRDATA17_0_FUSEWRDATA17_SHIFT)
+#define FUSE_FUSEWRDATA17_0_FUSEWRDATA17_RANGE                  31:0
+#define FUSE_FUSEWRDATA17_0_FUSEWRDATA17_WOFFSET                        0x0
+#define FUSE_FUSEWRDATA17_0_FUSEWRDATA17_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA17_0_FUSEWRDATA17_DEFAULT_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA17_0_FUSEWRDATA17_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA17_0_FUSEWRDATA17_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA17_0_FUSEWRDATA_PRIVATE_KEY3__RED_ALIAS_0_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_FUSEWRDATA17_0_FUSEWRDATA_PRIVATE_KEY3__RED_ALIAS_0_FIELD                  (_MK_MASK_CONST(0xffffffff) << FUSE_FUSEWRDATA17_0_FUSEWRDATA_PRIVATE_KEY3__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA17_0_FUSEWRDATA_PRIVATE_KEY3__RED_ALIAS_0_RANGE                  31:0
+#define FUSE_FUSEWRDATA17_0_FUSEWRDATA_PRIVATE_KEY3__RED_ALIAS_0_WOFFSET                        0x0
+#define FUSE_FUSEWRDATA17_0_FUSEWRDATA_PRIVATE_KEY3__RED_ALIAS_0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA17_0_FUSEWRDATA_PRIVATE_KEY3__RED_ALIAS_0_DEFAULT_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA17_0_FUSEWRDATA_PRIVATE_KEY3__RED_ALIAS_0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA17_0_FUSEWRDATA_PRIVATE_KEY3__RED_ALIAS_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_FUSEWRDATA18_0  
+#define FUSE_FUSEWRDATA18_0                     _MK_ADDR_CONST(0xac)
+#define FUSE_FUSEWRDATA18_0_WORD_COUNT                  0x1
+#define FUSE_FUSEWRDATA18_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA18_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA18_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA18_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA18_0_READ_MASK                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA18_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA18_0_FUSEWRDATA18_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_FUSEWRDATA18_0_FUSEWRDATA18_FIELD                  (_MK_MASK_CONST(0xffffffff) << FUSE_FUSEWRDATA18_0_FUSEWRDATA18_SHIFT)
+#define FUSE_FUSEWRDATA18_0_FUSEWRDATA18_RANGE                  31:0
+#define FUSE_FUSEWRDATA18_0_FUSEWRDATA18_WOFFSET                        0x0
+#define FUSE_FUSEWRDATA18_0_FUSEWRDATA18_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA18_0_FUSEWRDATA18_DEFAULT_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA18_0_FUSEWRDATA18_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA18_0_FUSEWRDATA18_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA18_0_FUSEWRDATA_PRIVATE_KEY4__RED_ALIAS_0_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_FUSEWRDATA18_0_FUSEWRDATA_PRIVATE_KEY4__RED_ALIAS_0_FIELD                  (_MK_MASK_CONST(0xffffffff) << FUSE_FUSEWRDATA18_0_FUSEWRDATA_PRIVATE_KEY4__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA18_0_FUSEWRDATA_PRIVATE_KEY4__RED_ALIAS_0_RANGE                  31:0
+#define FUSE_FUSEWRDATA18_0_FUSEWRDATA_PRIVATE_KEY4__RED_ALIAS_0_WOFFSET                        0x0
+#define FUSE_FUSEWRDATA18_0_FUSEWRDATA_PRIVATE_KEY4__RED_ALIAS_0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA18_0_FUSEWRDATA_PRIVATE_KEY4__RED_ALIAS_0_DEFAULT_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA18_0_FUSEWRDATA_PRIVATE_KEY4__RED_ALIAS_0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA18_0_FUSEWRDATA_PRIVATE_KEY4__RED_ALIAS_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_FUSEWRDATA19_0  
+#define FUSE_FUSEWRDATA19_0                     _MK_ADDR_CONST(0xb0)
+#define FUSE_FUSEWRDATA19_0_WORD_COUNT                  0x1
+#define FUSE_FUSEWRDATA19_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA19_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA19_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA19_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA19_0_READ_MASK                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA19_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA19_0_FUSEWRDATA19_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_FUSEWRDATA19_0_FUSEWRDATA19_FIELD                  (_MK_MASK_CONST(0xffffffff) << FUSE_FUSEWRDATA19_0_FUSEWRDATA19_SHIFT)
+#define FUSE_FUSEWRDATA19_0_FUSEWRDATA19_RANGE                  31:0
+#define FUSE_FUSEWRDATA19_0_FUSEWRDATA19_WOFFSET                        0x0
+#define FUSE_FUSEWRDATA19_0_FUSEWRDATA19_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA19_0_FUSEWRDATA19_DEFAULT_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA19_0_FUSEWRDATA19_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA19_0_FUSEWRDATA19_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA19_0_FUSEWRDATA_ARM_JTAG_DIS__RED_ALIAS_0_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_FUSEWRDATA19_0_FUSEWRDATA_ARM_JTAG_DIS__RED_ALIAS_0_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_FUSEWRDATA19_0_FUSEWRDATA_ARM_JTAG_DIS__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA19_0_FUSEWRDATA_ARM_JTAG_DIS__RED_ALIAS_0_RANGE                  0:0
+#define FUSE_FUSEWRDATA19_0_FUSEWRDATA_ARM_JTAG_DIS__RED_ALIAS_0_WOFFSET                        0x0
+#define FUSE_FUSEWRDATA19_0_FUSEWRDATA_ARM_JTAG_DIS__RED_ALIAS_0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA19_0_FUSEWRDATA_ARM_JTAG_DIS__RED_ALIAS_0_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_FUSEWRDATA19_0_FUSEWRDATA_ARM_JTAG_DIS__RED_ALIAS_0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA19_0_FUSEWRDATA_ARM_JTAG_DIS__RED_ALIAS_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA19_0_FUSEWRDATA_BOOT_DEVICE_INFO__RED_ALIAS_0_SHIFT                      _MK_SHIFT_CONST(1)
+#define FUSE_FUSEWRDATA19_0_FUSEWRDATA_BOOT_DEVICE_INFO__RED_ALIAS_0_FIELD                      (_MK_MASK_CONST(0x7f) << FUSE_FUSEWRDATA19_0_FUSEWRDATA_BOOT_DEVICE_INFO__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA19_0_FUSEWRDATA_BOOT_DEVICE_INFO__RED_ALIAS_0_RANGE                      7:1
+#define FUSE_FUSEWRDATA19_0_FUSEWRDATA_BOOT_DEVICE_INFO__RED_ALIAS_0_WOFFSET                    0x0
+#define FUSE_FUSEWRDATA19_0_FUSEWRDATA_BOOT_DEVICE_INFO__RED_ALIAS_0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA19_0_FUSEWRDATA_BOOT_DEVICE_INFO__RED_ALIAS_0_DEFAULT_MASK                       _MK_MASK_CONST(0x7f)
+#define FUSE_FUSEWRDATA19_0_FUSEWRDATA_BOOT_DEVICE_INFO__RED_ALIAS_0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA19_0_FUSEWRDATA_BOOT_DEVICE_INFO__RED_ALIAS_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA19_0_FUSEWRDATA_RESERVED_SW__RED_ALIAS_0_SHIFT                   _MK_SHIFT_CONST(8)
+#define FUSE_FUSEWRDATA19_0_FUSEWRDATA_RESERVED_SW__RED_ALIAS_0_FIELD                   (_MK_MASK_CONST(0xff) << FUSE_FUSEWRDATA19_0_FUSEWRDATA_RESERVED_SW__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA19_0_FUSEWRDATA_RESERVED_SW__RED_ALIAS_0_RANGE                   15:8
+#define FUSE_FUSEWRDATA19_0_FUSEWRDATA_RESERVED_SW__RED_ALIAS_0_WOFFSET                 0x0
+#define FUSE_FUSEWRDATA19_0_FUSEWRDATA_RESERVED_SW__RED_ALIAS_0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA19_0_FUSEWRDATA_RESERVED_SW__RED_ALIAS_0_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define FUSE_FUSEWRDATA19_0_FUSEWRDATA_RESERVED_SW__RED_ALIAS_0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA19_0_FUSEWRDATA_RESERVED_SW__RED_ALIAS_0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA19_0_FUSEWRDATA_JTAG_SECUREID_0__PRI_ALIAS_0_SHIFT                       _MK_SHIFT_CONST(16)
+#define FUSE_FUSEWRDATA19_0_FUSEWRDATA_JTAG_SECUREID_0__PRI_ALIAS_0_FIELD                       (_MK_MASK_CONST(0xffff) << FUSE_FUSEWRDATA19_0_FUSEWRDATA_JTAG_SECUREID_0__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA19_0_FUSEWRDATA_JTAG_SECUREID_0__PRI_ALIAS_0_RANGE                       31:16
+#define FUSE_FUSEWRDATA19_0_FUSEWRDATA_JTAG_SECUREID_0__PRI_ALIAS_0_WOFFSET                     0x0
+#define FUSE_FUSEWRDATA19_0_FUSEWRDATA_JTAG_SECUREID_0__PRI_ALIAS_0_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA19_0_FUSEWRDATA_JTAG_SECUREID_0__PRI_ALIAS_0_DEFAULT_MASK                        _MK_MASK_CONST(0xffff)
+#define FUSE_FUSEWRDATA19_0_FUSEWRDATA_JTAG_SECUREID_0__PRI_ALIAS_0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA19_0_FUSEWRDATA_JTAG_SECUREID_0__PRI_ALIAS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_FUSEWRDATA20_0  
+#define FUSE_FUSEWRDATA20_0                     _MK_ADDR_CONST(0xb4)
+#define FUSE_FUSEWRDATA20_0_WORD_COUNT                  0x1
+#define FUSE_FUSEWRDATA20_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA20_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA20_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA20_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA20_0_READ_MASK                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA20_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA20_0_FUSEWRDATA20_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_FUSEWRDATA20_0_FUSEWRDATA20_FIELD                  (_MK_MASK_CONST(0xffffffff) << FUSE_FUSEWRDATA20_0_FUSEWRDATA20_SHIFT)
+#define FUSE_FUSEWRDATA20_0_FUSEWRDATA20_RANGE                  31:0
+#define FUSE_FUSEWRDATA20_0_FUSEWRDATA20_WOFFSET                        0x0
+#define FUSE_FUSEWRDATA20_0_FUSEWRDATA20_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA20_0_FUSEWRDATA20_DEFAULT_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA20_0_FUSEWRDATA20_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA20_0_FUSEWRDATA20_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA20_0_FUSEWRDATA_JTAG_SECUREID_0__PRI_ALIAS_1_SHIFT                       _MK_SHIFT_CONST(0)
+#define FUSE_FUSEWRDATA20_0_FUSEWRDATA_JTAG_SECUREID_0__PRI_ALIAS_1_FIELD                       (_MK_MASK_CONST(0xffff) << FUSE_FUSEWRDATA20_0_FUSEWRDATA_JTAG_SECUREID_0__PRI_ALIAS_1_SHIFT)
+#define FUSE_FUSEWRDATA20_0_FUSEWRDATA_JTAG_SECUREID_0__PRI_ALIAS_1_RANGE                       15:0
+#define FUSE_FUSEWRDATA20_0_FUSEWRDATA_JTAG_SECUREID_0__PRI_ALIAS_1_WOFFSET                     0x0
+#define FUSE_FUSEWRDATA20_0_FUSEWRDATA_JTAG_SECUREID_0__PRI_ALIAS_1_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA20_0_FUSEWRDATA_JTAG_SECUREID_0__PRI_ALIAS_1_DEFAULT_MASK                        _MK_MASK_CONST(0xffff)
+#define FUSE_FUSEWRDATA20_0_FUSEWRDATA_JTAG_SECUREID_0__PRI_ALIAS_1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA20_0_FUSEWRDATA_JTAG_SECUREID_0__PRI_ALIAS_1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA20_0_FUSEWRDATA_JTAG_SECUREID_1__PRI_ALIAS_0_SHIFT                       _MK_SHIFT_CONST(16)
+#define FUSE_FUSEWRDATA20_0_FUSEWRDATA_JTAG_SECUREID_1__PRI_ALIAS_0_FIELD                       (_MK_MASK_CONST(0xffff) << FUSE_FUSEWRDATA20_0_FUSEWRDATA_JTAG_SECUREID_1__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA20_0_FUSEWRDATA_JTAG_SECUREID_1__PRI_ALIAS_0_RANGE                       31:16
+#define FUSE_FUSEWRDATA20_0_FUSEWRDATA_JTAG_SECUREID_1__PRI_ALIAS_0_WOFFSET                     0x0
+#define FUSE_FUSEWRDATA20_0_FUSEWRDATA_JTAG_SECUREID_1__PRI_ALIAS_0_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA20_0_FUSEWRDATA_JTAG_SECUREID_1__PRI_ALIAS_0_DEFAULT_MASK                        _MK_MASK_CONST(0xffff)
+#define FUSE_FUSEWRDATA20_0_FUSEWRDATA_JTAG_SECUREID_1__PRI_ALIAS_0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA20_0_FUSEWRDATA_JTAG_SECUREID_1__PRI_ALIAS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_FUSEWRDATA21_0  
+#define FUSE_FUSEWRDATA21_0                     _MK_ADDR_CONST(0xb8)
+#define FUSE_FUSEWRDATA21_0_WORD_COUNT                  0x1
+#define FUSE_FUSEWRDATA21_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA21_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA21_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA21_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA21_0_READ_MASK                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA21_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA21_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA21_FIELD                  (_MK_MASK_CONST(0xffffffff) << FUSE_FUSEWRDATA21_0_FUSEWRDATA21_SHIFT)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA21_RANGE                  31:0
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA21_WOFFSET                        0x0
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA21_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA21_DEFAULT_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA21_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA21_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_JTAG_SECUREID_1__PRI_ALIAS_1_SHIFT                       _MK_SHIFT_CONST(0)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_JTAG_SECUREID_1__PRI_ALIAS_1_FIELD                       (_MK_MASK_CONST(0xffff) << FUSE_FUSEWRDATA21_0_FUSEWRDATA_JTAG_SECUREID_1__PRI_ALIAS_1_SHIFT)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_JTAG_SECUREID_1__PRI_ALIAS_1_RANGE                       15:0
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_JTAG_SECUREID_1__PRI_ALIAS_1_WOFFSET                     0x0
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_JTAG_SECUREID_1__PRI_ALIAS_1_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_JTAG_SECUREID_1__PRI_ALIAS_1_DEFAULT_MASK                        _MK_MASK_CONST(0xffff)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_JTAG_SECUREID_1__PRI_ALIAS_1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_JTAG_SECUREID_1__PRI_ALIAS_1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_0__PRI_ALIAS_0_SHIFT                   _MK_SHIFT_CONST(16)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_0__PRI_ALIAS_0_FIELD                   (_MK_MASK_CONST(0x1) << FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_0__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_0__PRI_ALIAS_0_RANGE                   16:16
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_0__PRI_ALIAS_0_WOFFSET                 0x0
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_0__PRI_ALIAS_0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_0__PRI_ALIAS_0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_0__PRI_ALIAS_0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_0__PRI_ALIAS_0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_1__PRI_ALIAS_0_SHIFT                   _MK_SHIFT_CONST(17)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_1__PRI_ALIAS_0_FIELD                   (_MK_MASK_CONST(0x1) << FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_1__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_1__PRI_ALIAS_0_RANGE                   17:17
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_1__PRI_ALIAS_0_WOFFSET                 0x0
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_1__PRI_ALIAS_0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_1__PRI_ALIAS_0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_1__PRI_ALIAS_0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_1__PRI_ALIAS_0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_2__PRI_ALIAS_0_SHIFT                   _MK_SHIFT_CONST(18)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_2__PRI_ALIAS_0_FIELD                   (_MK_MASK_CONST(0x1) << FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_2__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_2__PRI_ALIAS_0_RANGE                   18:18
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_2__PRI_ALIAS_0_WOFFSET                 0x0
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_2__PRI_ALIAS_0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_2__PRI_ALIAS_0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_2__PRI_ALIAS_0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_2__PRI_ALIAS_0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_3__PRI_ALIAS_0_SHIFT                   _MK_SHIFT_CONST(19)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_3__PRI_ALIAS_0_FIELD                   (_MK_MASK_CONST(0x1) << FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_3__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_3__PRI_ALIAS_0_RANGE                   19:19
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_3__PRI_ALIAS_0_WOFFSET                 0x0
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_3__PRI_ALIAS_0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_3__PRI_ALIAS_0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_3__PRI_ALIAS_0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_3__PRI_ALIAS_0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_4__PRI_ALIAS_0_SHIFT                   _MK_SHIFT_CONST(20)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_4__PRI_ALIAS_0_FIELD                   (_MK_MASK_CONST(0x1) << FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_4__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_4__PRI_ALIAS_0_RANGE                   20:20
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_4__PRI_ALIAS_0_WOFFSET                 0x0
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_4__PRI_ALIAS_0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_4__PRI_ALIAS_0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_4__PRI_ALIAS_0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_4__PRI_ALIAS_0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_5__PRI_ALIAS_0_SHIFT                   _MK_SHIFT_CONST(21)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_5__PRI_ALIAS_0_FIELD                   (_MK_MASK_CONST(0x1) << FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_5__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_5__PRI_ALIAS_0_RANGE                   21:21
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_5__PRI_ALIAS_0_WOFFSET                 0x0
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_5__PRI_ALIAS_0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_5__PRI_ALIAS_0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_5__PRI_ALIAS_0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_5__PRI_ALIAS_0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_6__PRI_ALIAS_0_SHIFT                   _MK_SHIFT_CONST(22)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_6__PRI_ALIAS_0_FIELD                   (_MK_MASK_CONST(0x1) << FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_6__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_6__PRI_ALIAS_0_RANGE                   22:22
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_6__PRI_ALIAS_0_WOFFSET                 0x0
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_6__PRI_ALIAS_0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_6__PRI_ALIAS_0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_6__PRI_ALIAS_0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_6__PRI_ALIAS_0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_7__PRI_ALIAS_0_SHIFT                   _MK_SHIFT_CONST(23)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_7__PRI_ALIAS_0_FIELD                   (_MK_MASK_CONST(0x1) << FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_7__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_7__PRI_ALIAS_0_RANGE                   23:23
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_7__PRI_ALIAS_0_WOFFSET                 0x0
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_7__PRI_ALIAS_0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_7__PRI_ALIAS_0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_7__PRI_ALIAS_0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_7__PRI_ALIAS_0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_8__PRI_ALIAS_0_SHIFT                   _MK_SHIFT_CONST(24)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_8__PRI_ALIAS_0_FIELD                   (_MK_MASK_CONST(0x1) << FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_8__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_8__PRI_ALIAS_0_RANGE                   24:24
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_8__PRI_ALIAS_0_WOFFSET                 0x0
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_8__PRI_ALIAS_0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_8__PRI_ALIAS_0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_8__PRI_ALIAS_0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_8__PRI_ALIAS_0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_9__PRI_ALIAS_0_SHIFT                   _MK_SHIFT_CONST(25)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_9__PRI_ALIAS_0_FIELD                   (_MK_MASK_CONST(0x1) << FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_9__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_9__PRI_ALIAS_0_RANGE                   25:25
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_9__PRI_ALIAS_0_WOFFSET                 0x0
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_9__PRI_ALIAS_0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_9__PRI_ALIAS_0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_9__PRI_ALIAS_0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_9__PRI_ALIAS_0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_10__PRI_ALIAS_0_SHIFT                  _MK_SHIFT_CONST(26)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_10__PRI_ALIAS_0_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_10__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_10__PRI_ALIAS_0_RANGE                  26:26
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_10__PRI_ALIAS_0_WOFFSET                        0x0
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_10__PRI_ALIAS_0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_10__PRI_ALIAS_0_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_10__PRI_ALIAS_0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_10__PRI_ALIAS_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_11__PRI_ALIAS_0_SHIFT                  _MK_SHIFT_CONST(27)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_11__PRI_ALIAS_0_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_11__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_11__PRI_ALIAS_0_RANGE                  27:27
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_11__PRI_ALIAS_0_WOFFSET                        0x0
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_11__PRI_ALIAS_0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_11__PRI_ALIAS_0_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_11__PRI_ALIAS_0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_11__PRI_ALIAS_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_12__PRI_ALIAS_0_SHIFT                  _MK_SHIFT_CONST(28)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_12__PRI_ALIAS_0_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_12__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_12__PRI_ALIAS_0_RANGE                  28:28
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_12__PRI_ALIAS_0_WOFFSET                        0x0
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_12__PRI_ALIAS_0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_12__PRI_ALIAS_0_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_12__PRI_ALIAS_0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_12__PRI_ALIAS_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_13__PRI_ALIAS_0_SHIFT                  _MK_SHIFT_CONST(29)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_13__PRI_ALIAS_0_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_13__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_13__PRI_ALIAS_0_RANGE                  29:29
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_13__PRI_ALIAS_0_WOFFSET                        0x0
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_13__PRI_ALIAS_0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_13__PRI_ALIAS_0_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_13__PRI_ALIAS_0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_13__PRI_ALIAS_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_14__PRI_ALIAS_0_SHIFT                  _MK_SHIFT_CONST(30)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_14__PRI_ALIAS_0_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_14__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_14__PRI_ALIAS_0_RANGE                  30:30
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_14__PRI_ALIAS_0_WOFFSET                        0x0
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_14__PRI_ALIAS_0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_14__PRI_ALIAS_0_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_14__PRI_ALIAS_0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_14__PRI_ALIAS_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_15__PRI_ALIAS_0_SHIFT                  _MK_SHIFT_CONST(31)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_15__PRI_ALIAS_0_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_15__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_15__PRI_ALIAS_0_RANGE                  31:31
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_15__PRI_ALIAS_0_WOFFSET                        0x0
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_15__PRI_ALIAS_0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_15__PRI_ALIAS_0_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_15__PRI_ALIAS_0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_15__PRI_ALIAS_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Reserved address 188 [0xbc] 
+
+// Reserved address 192 [0xc0] 
+
+// Reserved address 196 [0xc4] 
+
+// Reserved address 200 [0xc8] 
+
+// Reserved address 204 [0xcc] 
+
+// Reserved address 208 [0xd0] 
+
+// Reserved address 212 [0xd4] 
+
+// Reserved address 216 [0xd8] 
+
+// Reserved address 220 [0xdc] 
+
+// Register FUSE_FUSEBYPASS_0  
+#define FUSE_FUSEBYPASS_0                       _MK_ADDR_CONST(0xe0)
+#define FUSE_FUSEBYPASS_0_WORD_COUNT                    0x1
+#define FUSE_FUSEBYPASS_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEBYPASS_0_RESET_MASK                    _MK_MASK_CONST(0x1)
+#define FUSE_FUSEBYPASS_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEBYPASS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEBYPASS_0_READ_MASK                     _MK_MASK_CONST(0x1)
+#define FUSE_FUSEBYPASS_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
+#define FUSE_FUSEBYPASS_0_FUSEBYPASS_VAL_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_FUSEBYPASS_0_FUSEBYPASS_VAL_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_FUSEBYPASS_0_FUSEBYPASS_VAL_SHIFT)
+#define FUSE_FUSEBYPASS_0_FUSEBYPASS_VAL_RANGE                  0:0
+#define FUSE_FUSEBYPASS_0_FUSEBYPASS_VAL_WOFFSET                        0x0
+#define FUSE_FUSEBYPASS_0_FUSEBYPASS_VAL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEBYPASS_0_FUSEBYPASS_VAL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_FUSEBYPASS_0_FUSEBYPASS_VAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEBYPASS_0_FUSEBYPASS_VAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEBYPASS_0_FUSEBYPASS_VAL_INIT_ENUM                      DISABLED
+#define FUSE_FUSEBYPASS_0_FUSEBYPASS_VAL_DISABLED                       _MK_ENUM_CONST(0)
+#define FUSE_FUSEBYPASS_0_FUSEBYPASS_VAL_ENABLED                        _MK_ENUM_CONST(1)
+#define FUSE_FUSEBYPASS_0_FUSEBYPASS_VAL_DISABLE                        _MK_ENUM_CONST(0)
+#define FUSE_FUSEBYPASS_0_FUSEBYPASS_VAL_ENABLE                 _MK_ENUM_CONST(1)
+
+
+// Register FUSE_PRIVATEKEYDISABLE_0  
+#define FUSE_PRIVATEKEYDISABLE_0                        _MK_ADDR_CONST(0xe4)
+#define FUSE_PRIVATEKEYDISABLE_0_WORD_COUNT                     0x1
+#define FUSE_PRIVATEKEYDISABLE_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATEKEYDISABLE_0_RESET_MASK                     _MK_MASK_CONST(0x1)
+#define FUSE_PRIVATEKEYDISABLE_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATEKEYDISABLE_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATEKEYDISABLE_0_READ_MASK                      _MK_MASK_CONST(0x1)
+#define FUSE_PRIVATEKEYDISABLE_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
+#define FUSE_PRIVATEKEYDISABLE_0_PRIVATEKEYDISABLE_VAL_SHIFT                    _MK_SHIFT_CONST(0)
+#define FUSE_PRIVATEKEYDISABLE_0_PRIVATEKEYDISABLE_VAL_FIELD                    (_MK_MASK_CONST(0x1) << FUSE_PRIVATEKEYDISABLE_0_PRIVATEKEYDISABLE_VAL_SHIFT)
+#define FUSE_PRIVATEKEYDISABLE_0_PRIVATEKEYDISABLE_VAL_RANGE                    0:0
+#define FUSE_PRIVATEKEYDISABLE_0_PRIVATEKEYDISABLE_VAL_WOFFSET                  0x0
+#define FUSE_PRIVATEKEYDISABLE_0_PRIVATEKEYDISABLE_VAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATEKEYDISABLE_0_PRIVATEKEYDISABLE_VAL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FUSE_PRIVATEKEYDISABLE_0_PRIVATEKEYDISABLE_VAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATEKEYDISABLE_0_PRIVATEKEYDISABLE_VAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATEKEYDISABLE_0_PRIVATEKEYDISABLE_VAL_INIT_ENUM                        KEY_VISIBLE
+#define FUSE_PRIVATEKEYDISABLE_0_PRIVATEKEYDISABLE_VAL_KEY_VISIBLE                      _MK_ENUM_CONST(0)
+#define FUSE_PRIVATEKEYDISABLE_0_PRIVATEKEYDISABLE_VAL_KEY_INVISIBLE                    _MK_ENUM_CONST(1)
+
+
+// Reserved address 232 [0xe8] 
+
+// Reserved address 236 [0xec] 
+
+// Reserved address 240 [0xf0] 
+
+// Reserved address 244 [0xf4] 
+
+// Reserved address 248 [0xf8] 
+
+// Reserved address 252 [0xfc] 
+
+// Register FUSE_PRODUCTION_MODE_0  
+#define FUSE_PRODUCTION_MODE_0                  _MK_ADDR_CONST(0x100)
+#define FUSE_PRODUCTION_MODE_0_WORD_COUNT                       0x1
+#define FUSE_PRODUCTION_MODE_0_RESET_VAL                        _MK_MASK_CONST(0x1)
+#define FUSE_PRODUCTION_MODE_0_RESET_MASK                       _MK_MASK_CONST(0x1)
+#define FUSE_PRODUCTION_MODE_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_PRODUCTION_MODE_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_PRODUCTION_MODE_0_READ_MASK                        _MK_MASK_CONST(0x1)
+#define FUSE_PRODUCTION_MODE_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
+#define FUSE_PRODUCTION_MODE_0_PRODUCTION_MODE_SHIFT                    _MK_SHIFT_CONST(0)
+#define FUSE_PRODUCTION_MODE_0_PRODUCTION_MODE_FIELD                    (_MK_MASK_CONST(0x1) << FUSE_PRODUCTION_MODE_0_PRODUCTION_MODE_SHIFT)
+#define FUSE_PRODUCTION_MODE_0_PRODUCTION_MODE_RANGE                    0:0
+#define FUSE_PRODUCTION_MODE_0_PRODUCTION_MODE_WOFFSET                  0x0
+#define FUSE_PRODUCTION_MODE_0_PRODUCTION_MODE_DEFAULT                  _MK_MASK_CONST(0x1)
+#define FUSE_PRODUCTION_MODE_0_PRODUCTION_MODE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FUSE_PRODUCTION_MODE_0_PRODUCTION_MODE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_PRODUCTION_MODE_0_PRODUCTION_MODE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_JTAG_SECUREID_VALID_0  
+#define FUSE_JTAG_SECUREID_VALID_0                      _MK_ADDR_CONST(0x104)
+#define FUSE_JTAG_SECUREID_VALID_0_WORD_COUNT                   0x1
+#define FUSE_JTAG_SECUREID_VALID_0_RESET_VAL                    _MK_MASK_CONST(0x1)
+#define FUSE_JTAG_SECUREID_VALID_0_RESET_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_JTAG_SECUREID_VALID_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define FUSE_JTAG_SECUREID_VALID_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define FUSE_JTAG_SECUREID_VALID_0_READ_MASK                    _MK_MASK_CONST(0x1)
+#define FUSE_JTAG_SECUREID_VALID_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
+#define FUSE_JTAG_SECUREID_VALID_0_JTAG_SECUREID_VALID_SHIFT                    _MK_SHIFT_CONST(0)
+#define FUSE_JTAG_SECUREID_VALID_0_JTAG_SECUREID_VALID_FIELD                    (_MK_MASK_CONST(0x1) << FUSE_JTAG_SECUREID_VALID_0_JTAG_SECUREID_VALID_SHIFT)
+#define FUSE_JTAG_SECUREID_VALID_0_JTAG_SECUREID_VALID_RANGE                    0:0
+#define FUSE_JTAG_SECUREID_VALID_0_JTAG_SECUREID_VALID_WOFFSET                  0x0
+#define FUSE_JTAG_SECUREID_VALID_0_JTAG_SECUREID_VALID_DEFAULT                  _MK_MASK_CONST(0x1)
+#define FUSE_JTAG_SECUREID_VALID_0_JTAG_SECUREID_VALID_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FUSE_JTAG_SECUREID_VALID_0_JTAG_SECUREID_VALID_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_JTAG_SECUREID_VALID_0_JTAG_SECUREID_VALID_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_JTAG_SECUREID_0_0  
+#define FUSE_JTAG_SECUREID_0_0                  _MK_ADDR_CONST(0x108)
+#define FUSE_JTAG_SECUREID_0_0_WORD_COUNT                       0x1
+#define FUSE_JTAG_SECUREID_0_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define FUSE_JTAG_SECUREID_0_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
+#define FUSE_JTAG_SECUREID_0_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_JTAG_SECUREID_0_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_JTAG_SECUREID_0_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define FUSE_JTAG_SECUREID_0_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
+#define FUSE_JTAG_SECUREID_0_0_JTAG_SECUREID_0_SHIFT                    _MK_SHIFT_CONST(0)
+#define FUSE_JTAG_SECUREID_0_0_JTAG_SECUREID_0_FIELD                    (_MK_MASK_CONST(0xffffffff) << FUSE_JTAG_SECUREID_0_0_JTAG_SECUREID_0_SHIFT)
+#define FUSE_JTAG_SECUREID_0_0_JTAG_SECUREID_0_RANGE                    31:0
+#define FUSE_JTAG_SECUREID_0_0_JTAG_SECUREID_0_WOFFSET                  0x0
+#define FUSE_JTAG_SECUREID_0_0_JTAG_SECUREID_0_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_JTAG_SECUREID_0_0_JTAG_SECUREID_0_DEFAULT_MASK                     _MK_MASK_CONST(0xffffffff)
+#define FUSE_JTAG_SECUREID_0_0_JTAG_SECUREID_0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_JTAG_SECUREID_0_0_JTAG_SECUREID_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_JTAG_SECUREID_1_0  
+#define FUSE_JTAG_SECUREID_1_0                  _MK_ADDR_CONST(0x10c)
+#define FUSE_JTAG_SECUREID_1_0_WORD_COUNT                       0x1
+#define FUSE_JTAG_SECUREID_1_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define FUSE_JTAG_SECUREID_1_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
+#define FUSE_JTAG_SECUREID_1_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_JTAG_SECUREID_1_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_JTAG_SECUREID_1_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define FUSE_JTAG_SECUREID_1_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
+#define FUSE_JTAG_SECUREID_1_0_JTAG_SECUREID_1_SHIFT                    _MK_SHIFT_CONST(0)
+#define FUSE_JTAG_SECUREID_1_0_JTAG_SECUREID_1_FIELD                    (_MK_MASK_CONST(0xffffffff) << FUSE_JTAG_SECUREID_1_0_JTAG_SECUREID_1_SHIFT)
+#define FUSE_JTAG_SECUREID_1_0_JTAG_SECUREID_1_RANGE                    31:0
+#define FUSE_JTAG_SECUREID_1_0_JTAG_SECUREID_1_WOFFSET                  0x0
+#define FUSE_JTAG_SECUREID_1_0_JTAG_SECUREID_1_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_JTAG_SECUREID_1_0_JTAG_SECUREID_1_DEFAULT_MASK                     _MK_MASK_CONST(0xffffffff)
+#define FUSE_JTAG_SECUREID_1_0_JTAG_SECUREID_1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_JTAG_SECUREID_1_0_JTAG_SECUREID_1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SKU_INFO_0  
+#define FUSE_SKU_INFO_0                 _MK_ADDR_CONST(0x110)
+#define FUSE_SKU_INFO_0_WORD_COUNT                      0x1
+#define FUSE_SKU_INFO_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define FUSE_SKU_INFO_0_RESET_MASK                      _MK_MASK_CONST(0xff)
+#define FUSE_SKU_INFO_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define FUSE_SKU_INFO_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define FUSE_SKU_INFO_0_READ_MASK                       _MK_MASK_CONST(0xff)
+#define FUSE_SKU_INFO_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
+#define FUSE_SKU_INFO_0_SKU_INFO_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_SKU_INFO_0_SKU_INFO_FIELD                  (_MK_MASK_CONST(0xff) << FUSE_SKU_INFO_0_SKU_INFO_SHIFT)
+#define FUSE_SKU_INFO_0_SKU_INFO_RANGE                  7:0
+#define FUSE_SKU_INFO_0_SKU_INFO_WOFFSET                        0x0
+#define FUSE_SKU_INFO_0_SKU_INFO_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_SKU_INFO_0_SKU_INFO_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
+#define FUSE_SKU_INFO_0_SKU_INFO_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_SKU_INFO_0_SKU_INFO_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_PROCESS_CALIB_0  
+#define FUSE_PROCESS_CALIB_0                    _MK_ADDR_CONST(0x114)
+#define FUSE_PROCESS_CALIB_0_WORD_COUNT                         0x1
+#define FUSE_PROCESS_CALIB_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define FUSE_PROCESS_CALIB_0_RESET_MASK                         _MK_MASK_CONST(0x3)
+#define FUSE_PROCESS_CALIB_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define FUSE_PROCESS_CALIB_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define FUSE_PROCESS_CALIB_0_READ_MASK                  _MK_MASK_CONST(0x3)
+#define FUSE_PROCESS_CALIB_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
+#define FUSE_PROCESS_CALIB_0_PROCESS_CALIB_SHIFT                        _MK_SHIFT_CONST(0)
+#define FUSE_PROCESS_CALIB_0_PROCESS_CALIB_FIELD                        (_MK_MASK_CONST(0x3) << FUSE_PROCESS_CALIB_0_PROCESS_CALIB_SHIFT)
+#define FUSE_PROCESS_CALIB_0_PROCESS_CALIB_RANGE                        1:0
+#define FUSE_PROCESS_CALIB_0_PROCESS_CALIB_WOFFSET                      0x0
+#define FUSE_PROCESS_CALIB_0_PROCESS_CALIB_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_PROCESS_CALIB_0_PROCESS_CALIB_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define FUSE_PROCESS_CALIB_0_PROCESS_CALIB_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_PROCESS_CALIB_0_PROCESS_CALIB_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_IO_CALIB_0  
+#define FUSE_IO_CALIB_0                 _MK_ADDR_CONST(0x118)
+#define FUSE_IO_CALIB_0_WORD_COUNT                      0x1
+#define FUSE_IO_CALIB_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define FUSE_IO_CALIB_0_RESET_MASK                      _MK_MASK_CONST(0x3ff)
+#define FUSE_IO_CALIB_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define FUSE_IO_CALIB_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define FUSE_IO_CALIB_0_READ_MASK                       _MK_MASK_CONST(0x3ff)
+#define FUSE_IO_CALIB_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
+#define FUSE_IO_CALIB_0_IO_CALIB_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_IO_CALIB_0_IO_CALIB_FIELD                  (_MK_MASK_CONST(0x3ff) << FUSE_IO_CALIB_0_IO_CALIB_SHIFT)
+#define FUSE_IO_CALIB_0_IO_CALIB_RANGE                  9:0
+#define FUSE_IO_CALIB_0_IO_CALIB_WOFFSET                        0x0
+#define FUSE_IO_CALIB_0_IO_CALIB_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_IO_CALIB_0_IO_CALIB_DEFAULT_MASK                   _MK_MASK_CONST(0x3ff)
+#define FUSE_IO_CALIB_0_IO_CALIB_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_IO_CALIB_0_IO_CALIB_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_DAC_CRT_CALIB_0  
+#define FUSE_DAC_CRT_CALIB_0                    _MK_ADDR_CONST(0x11c)
+#define FUSE_DAC_CRT_CALIB_0_WORD_COUNT                         0x1
+#define FUSE_DAC_CRT_CALIB_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define FUSE_DAC_CRT_CALIB_0_RESET_MASK                         _MK_MASK_CONST(0xff)
+#define FUSE_DAC_CRT_CALIB_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define FUSE_DAC_CRT_CALIB_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define FUSE_DAC_CRT_CALIB_0_READ_MASK                  _MK_MASK_CONST(0xff)
+#define FUSE_DAC_CRT_CALIB_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
+#define FUSE_DAC_CRT_CALIB_0_DAC_CRT_CALIB_SHIFT                        _MK_SHIFT_CONST(0)
+#define FUSE_DAC_CRT_CALIB_0_DAC_CRT_CALIB_FIELD                        (_MK_MASK_CONST(0xff) << FUSE_DAC_CRT_CALIB_0_DAC_CRT_CALIB_SHIFT)
+#define FUSE_DAC_CRT_CALIB_0_DAC_CRT_CALIB_RANGE                        7:0
+#define FUSE_DAC_CRT_CALIB_0_DAC_CRT_CALIB_WOFFSET                      0x0
+#define FUSE_DAC_CRT_CALIB_0_DAC_CRT_CALIB_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_DAC_CRT_CALIB_0_DAC_CRT_CALIB_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
+#define FUSE_DAC_CRT_CALIB_0_DAC_CRT_CALIB_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_DAC_CRT_CALIB_0_DAC_CRT_CALIB_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_DAC_HDTV_CALIB_0  
+#define FUSE_DAC_HDTV_CALIB_0                   _MK_ADDR_CONST(0x120)
+#define FUSE_DAC_HDTV_CALIB_0_WORD_COUNT                        0x1
+#define FUSE_DAC_HDTV_CALIB_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define FUSE_DAC_HDTV_CALIB_0_RESET_MASK                        _MK_MASK_CONST(0xff)
+#define FUSE_DAC_HDTV_CALIB_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define FUSE_DAC_HDTV_CALIB_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define FUSE_DAC_HDTV_CALIB_0_READ_MASK                         _MK_MASK_CONST(0xff)
+#define FUSE_DAC_HDTV_CALIB_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+#define FUSE_DAC_HDTV_CALIB_0_DAC_HDTV_CALIB_SHIFT                      _MK_SHIFT_CONST(0)
+#define FUSE_DAC_HDTV_CALIB_0_DAC_HDTV_CALIB_FIELD                      (_MK_MASK_CONST(0xff) << FUSE_DAC_HDTV_CALIB_0_DAC_HDTV_CALIB_SHIFT)
+#define FUSE_DAC_HDTV_CALIB_0_DAC_HDTV_CALIB_RANGE                      7:0
+#define FUSE_DAC_HDTV_CALIB_0_DAC_HDTV_CALIB_WOFFSET                    0x0
+#define FUSE_DAC_HDTV_CALIB_0_DAC_HDTV_CALIB_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_DAC_HDTV_CALIB_0_DAC_HDTV_CALIB_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
+#define FUSE_DAC_HDTV_CALIB_0_DAC_HDTV_CALIB_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_DAC_HDTV_CALIB_0_DAC_HDTV_CALIB_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_DAC_SDTV_CALIB_0  
+#define FUSE_DAC_SDTV_CALIB_0                   _MK_ADDR_CONST(0x124)
+#define FUSE_DAC_SDTV_CALIB_0_WORD_COUNT                        0x1
+#define FUSE_DAC_SDTV_CALIB_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define FUSE_DAC_SDTV_CALIB_0_RESET_MASK                        _MK_MASK_CONST(0xff)
+#define FUSE_DAC_SDTV_CALIB_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define FUSE_DAC_SDTV_CALIB_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define FUSE_DAC_SDTV_CALIB_0_READ_MASK                         _MK_MASK_CONST(0xff)
+#define FUSE_DAC_SDTV_CALIB_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+#define FUSE_DAC_SDTV_CALIB_0_DAC_SDTV_CALIB_SHIFT                      _MK_SHIFT_CONST(0)
+#define FUSE_DAC_SDTV_CALIB_0_DAC_SDTV_CALIB_FIELD                      (_MK_MASK_CONST(0xff) << FUSE_DAC_SDTV_CALIB_0_DAC_SDTV_CALIB_SHIFT)
+#define FUSE_DAC_SDTV_CALIB_0_DAC_SDTV_CALIB_RANGE                      7:0
+#define FUSE_DAC_SDTV_CALIB_0_DAC_SDTV_CALIB_WOFFSET                    0x0
+#define FUSE_DAC_SDTV_CALIB_0_DAC_SDTV_CALIB_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_DAC_SDTV_CALIB_0_DAC_SDTV_CALIB_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
+#define FUSE_DAC_SDTV_CALIB_0_DAC_SDTV_CALIB_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_DAC_SDTV_CALIB_0_DAC_SDTV_CALIB_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_CMC_DATARAM0_0_0  
+#define FUSE_CMC_DATARAM0_0_0                   _MK_ADDR_CONST(0x128)
+#define FUSE_CMC_DATARAM0_0_0_WORD_COUNT                        0x1
+#define FUSE_CMC_DATARAM0_0_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define FUSE_CMC_DATARAM0_0_0_RESET_MASK                        _MK_MASK_CONST(0x7f)
+#define FUSE_CMC_DATARAM0_0_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define FUSE_CMC_DATARAM0_0_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define FUSE_CMC_DATARAM0_0_0_READ_MASK                         _MK_MASK_CONST(0x7f)
+#define FUSE_CMC_DATARAM0_0_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+#define FUSE_CMC_DATARAM0_0_0_CMC_DATARAM0_0_SHIFT                      _MK_SHIFT_CONST(0)
+#define FUSE_CMC_DATARAM0_0_0_CMC_DATARAM0_0_FIELD                      (_MK_MASK_CONST(0x7f) << FUSE_CMC_DATARAM0_0_0_CMC_DATARAM0_0_SHIFT)
+#define FUSE_CMC_DATARAM0_0_0_CMC_DATARAM0_0_RANGE                      6:0
+#define FUSE_CMC_DATARAM0_0_0_CMC_DATARAM0_0_WOFFSET                    0x0
+#define FUSE_CMC_DATARAM0_0_0_CMC_DATARAM0_0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_CMC_DATARAM0_0_0_CMC_DATARAM0_0_DEFAULT_MASK                       _MK_MASK_CONST(0x7f)
+#define FUSE_CMC_DATARAM0_0_0_CMC_DATARAM0_0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_CMC_DATARAM0_0_0_CMC_DATARAM0_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_CMC_DATARAM0_1_0  
+#define FUSE_CMC_DATARAM0_1_0                   _MK_ADDR_CONST(0x12c)
+#define FUSE_CMC_DATARAM0_1_0_WORD_COUNT                        0x1
+#define FUSE_CMC_DATARAM0_1_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define FUSE_CMC_DATARAM0_1_0_RESET_MASK                        _MK_MASK_CONST(0x7f)
+#define FUSE_CMC_DATARAM0_1_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define FUSE_CMC_DATARAM0_1_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define FUSE_CMC_DATARAM0_1_0_READ_MASK                         _MK_MASK_CONST(0x7f)
+#define FUSE_CMC_DATARAM0_1_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+#define FUSE_CMC_DATARAM0_1_0_CMC_DATARAM0_1_SHIFT                      _MK_SHIFT_CONST(0)
+#define FUSE_CMC_DATARAM0_1_0_CMC_DATARAM0_1_FIELD                      (_MK_MASK_CONST(0x7f) << FUSE_CMC_DATARAM0_1_0_CMC_DATARAM0_1_SHIFT)
+#define FUSE_CMC_DATARAM0_1_0_CMC_DATARAM0_1_RANGE                      6:0
+#define FUSE_CMC_DATARAM0_1_0_CMC_DATARAM0_1_WOFFSET                    0x0
+#define FUSE_CMC_DATARAM0_1_0_CMC_DATARAM0_1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_CMC_DATARAM0_1_0_CMC_DATARAM0_1_DEFAULT_MASK                       _MK_MASK_CONST(0x7f)
+#define FUSE_CMC_DATARAM0_1_0_CMC_DATARAM0_1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_CMC_DATARAM0_1_0_CMC_DATARAM0_1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_CMC_DATARAM0_2_0  
+#define FUSE_CMC_DATARAM0_2_0                   _MK_ADDR_CONST(0x130)
+#define FUSE_CMC_DATARAM0_2_0_WORD_COUNT                        0x1
+#define FUSE_CMC_DATARAM0_2_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define FUSE_CMC_DATARAM0_2_0_RESET_MASK                        _MK_MASK_CONST(0x7f)
+#define FUSE_CMC_DATARAM0_2_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define FUSE_CMC_DATARAM0_2_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define FUSE_CMC_DATARAM0_2_0_READ_MASK                         _MK_MASK_CONST(0x7f)
+#define FUSE_CMC_DATARAM0_2_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+#define FUSE_CMC_DATARAM0_2_0_CMC_DATARAM0_2_SHIFT                      _MK_SHIFT_CONST(0)
+#define FUSE_CMC_DATARAM0_2_0_CMC_DATARAM0_2_FIELD                      (_MK_MASK_CONST(0x7f) << FUSE_CMC_DATARAM0_2_0_CMC_DATARAM0_2_SHIFT)
+#define FUSE_CMC_DATARAM0_2_0_CMC_DATARAM0_2_RANGE                      6:0
+#define FUSE_CMC_DATARAM0_2_0_CMC_DATARAM0_2_WOFFSET                    0x0
+#define FUSE_CMC_DATARAM0_2_0_CMC_DATARAM0_2_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_CMC_DATARAM0_2_0_CMC_DATARAM0_2_DEFAULT_MASK                       _MK_MASK_CONST(0x7f)
+#define FUSE_CMC_DATARAM0_2_0_CMC_DATARAM0_2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_CMC_DATARAM0_2_0_CMC_DATARAM0_2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_CMC_DATARAM0_3_0  
+#define FUSE_CMC_DATARAM0_3_0                   _MK_ADDR_CONST(0x134)
+#define FUSE_CMC_DATARAM0_3_0_WORD_COUNT                        0x1
+#define FUSE_CMC_DATARAM0_3_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define FUSE_CMC_DATARAM0_3_0_RESET_MASK                        _MK_MASK_CONST(0x7f)
+#define FUSE_CMC_DATARAM0_3_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define FUSE_CMC_DATARAM0_3_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define FUSE_CMC_DATARAM0_3_0_READ_MASK                         _MK_MASK_CONST(0x7f)
+#define FUSE_CMC_DATARAM0_3_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+#define FUSE_CMC_DATARAM0_3_0_CMC_DATARAM0_3_SHIFT                      _MK_SHIFT_CONST(0)
+#define FUSE_CMC_DATARAM0_3_0_CMC_DATARAM0_3_FIELD                      (_MK_MASK_CONST(0x7f) << FUSE_CMC_DATARAM0_3_0_CMC_DATARAM0_3_SHIFT)
+#define FUSE_CMC_DATARAM0_3_0_CMC_DATARAM0_3_RANGE                      6:0
+#define FUSE_CMC_DATARAM0_3_0_CMC_DATARAM0_3_WOFFSET                    0x0
+#define FUSE_CMC_DATARAM0_3_0_CMC_DATARAM0_3_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_CMC_DATARAM0_3_0_CMC_DATARAM0_3_DEFAULT_MASK                       _MK_MASK_CONST(0x7f)
+#define FUSE_CMC_DATARAM0_3_0_CMC_DATARAM0_3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_CMC_DATARAM0_3_0_CMC_DATARAM0_3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_CMC_DATARAM1_0_0  
+#define FUSE_CMC_DATARAM1_0_0                   _MK_ADDR_CONST(0x138)
+#define FUSE_CMC_DATARAM1_0_0_WORD_COUNT                        0x1
+#define FUSE_CMC_DATARAM1_0_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define FUSE_CMC_DATARAM1_0_0_RESET_MASK                        _MK_MASK_CONST(0x7f)
+#define FUSE_CMC_DATARAM1_0_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define FUSE_CMC_DATARAM1_0_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define FUSE_CMC_DATARAM1_0_0_READ_MASK                         _MK_MASK_CONST(0x7f)
+#define FUSE_CMC_DATARAM1_0_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+#define FUSE_CMC_DATARAM1_0_0_CMC_DATARAM1_0_SHIFT                      _MK_SHIFT_CONST(0)
+#define FUSE_CMC_DATARAM1_0_0_CMC_DATARAM1_0_FIELD                      (_MK_MASK_CONST(0x7f) << FUSE_CMC_DATARAM1_0_0_CMC_DATARAM1_0_SHIFT)
+#define FUSE_CMC_DATARAM1_0_0_CMC_DATARAM1_0_RANGE                      6:0
+#define FUSE_CMC_DATARAM1_0_0_CMC_DATARAM1_0_WOFFSET                    0x0
+#define FUSE_CMC_DATARAM1_0_0_CMC_DATARAM1_0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_CMC_DATARAM1_0_0_CMC_DATARAM1_0_DEFAULT_MASK                       _MK_MASK_CONST(0x7f)
+#define FUSE_CMC_DATARAM1_0_0_CMC_DATARAM1_0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_CMC_DATARAM1_0_0_CMC_DATARAM1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_CMC_DATARAM1_1_0  
+#define FUSE_CMC_DATARAM1_1_0                   _MK_ADDR_CONST(0x13c)
+#define FUSE_CMC_DATARAM1_1_0_WORD_COUNT                        0x1
+#define FUSE_CMC_DATARAM1_1_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define FUSE_CMC_DATARAM1_1_0_RESET_MASK                        _MK_MASK_CONST(0x7f)
+#define FUSE_CMC_DATARAM1_1_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define FUSE_CMC_DATARAM1_1_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define FUSE_CMC_DATARAM1_1_0_READ_MASK                         _MK_MASK_CONST(0x7f)
+#define FUSE_CMC_DATARAM1_1_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+#define FUSE_CMC_DATARAM1_1_0_CMC_DATARAM1_1_SHIFT                      _MK_SHIFT_CONST(0)
+#define FUSE_CMC_DATARAM1_1_0_CMC_DATARAM1_1_FIELD                      (_MK_MASK_CONST(0x7f) << FUSE_CMC_DATARAM1_1_0_CMC_DATARAM1_1_SHIFT)
+#define FUSE_CMC_DATARAM1_1_0_CMC_DATARAM1_1_RANGE                      6:0
+#define FUSE_CMC_DATARAM1_1_0_CMC_DATARAM1_1_WOFFSET                    0x0
+#define FUSE_CMC_DATARAM1_1_0_CMC_DATARAM1_1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_CMC_DATARAM1_1_0_CMC_DATARAM1_1_DEFAULT_MASK                       _MK_MASK_CONST(0x7f)
+#define FUSE_CMC_DATARAM1_1_0_CMC_DATARAM1_1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_CMC_DATARAM1_1_0_CMC_DATARAM1_1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_CMC_DATARAM1_2_0  
+#define FUSE_CMC_DATARAM1_2_0                   _MK_ADDR_CONST(0x140)
+#define FUSE_CMC_DATARAM1_2_0_WORD_COUNT                        0x1
+#define FUSE_CMC_DATARAM1_2_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define FUSE_CMC_DATARAM1_2_0_RESET_MASK                        _MK_MASK_CONST(0x7f)
+#define FUSE_CMC_DATARAM1_2_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define FUSE_CMC_DATARAM1_2_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define FUSE_CMC_DATARAM1_2_0_READ_MASK                         _MK_MASK_CONST(0x7f)
+#define FUSE_CMC_DATARAM1_2_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+#define FUSE_CMC_DATARAM1_2_0_CMC_DATARAM1_2_SHIFT                      _MK_SHIFT_CONST(0)
+#define FUSE_CMC_DATARAM1_2_0_CMC_DATARAM1_2_FIELD                      (_MK_MASK_CONST(0x7f) << FUSE_CMC_DATARAM1_2_0_CMC_DATARAM1_2_SHIFT)
+#define FUSE_CMC_DATARAM1_2_0_CMC_DATARAM1_2_RANGE                      6:0
+#define FUSE_CMC_DATARAM1_2_0_CMC_DATARAM1_2_WOFFSET                    0x0
+#define FUSE_CMC_DATARAM1_2_0_CMC_DATARAM1_2_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_CMC_DATARAM1_2_0_CMC_DATARAM1_2_DEFAULT_MASK                       _MK_MASK_CONST(0x7f)
+#define FUSE_CMC_DATARAM1_2_0_CMC_DATARAM1_2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_CMC_DATARAM1_2_0_CMC_DATARAM1_2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_CMC_DATARAM1_3_0  
+#define FUSE_CMC_DATARAM1_3_0                   _MK_ADDR_CONST(0x144)
+#define FUSE_CMC_DATARAM1_3_0_WORD_COUNT                        0x1
+#define FUSE_CMC_DATARAM1_3_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define FUSE_CMC_DATARAM1_3_0_RESET_MASK                        _MK_MASK_CONST(0x7f)
+#define FUSE_CMC_DATARAM1_3_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define FUSE_CMC_DATARAM1_3_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define FUSE_CMC_DATARAM1_3_0_READ_MASK                         _MK_MASK_CONST(0x7f)
+#define FUSE_CMC_DATARAM1_3_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+#define FUSE_CMC_DATARAM1_3_0_CMC_DATARAM1_3_SHIFT                      _MK_SHIFT_CONST(0)
+#define FUSE_CMC_DATARAM1_3_0_CMC_DATARAM1_3_FIELD                      (_MK_MASK_CONST(0x7f) << FUSE_CMC_DATARAM1_3_0_CMC_DATARAM1_3_SHIFT)
+#define FUSE_CMC_DATARAM1_3_0_CMC_DATARAM1_3_RANGE                      6:0
+#define FUSE_CMC_DATARAM1_3_0_CMC_DATARAM1_3_WOFFSET                    0x0
+#define FUSE_CMC_DATARAM1_3_0_CMC_DATARAM1_3_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_CMC_DATARAM1_3_0_CMC_DATARAM1_3_DEFAULT_MASK                       _MK_MASK_CONST(0x7f)
+#define FUSE_CMC_DATARAM1_3_0_CMC_DATARAM1_3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_CMC_DATARAM1_3_0_CMC_DATARAM1_3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_FA_0  
+#define FUSE_FA_0                       _MK_ADDR_CONST(0x148)
+#define FUSE_FA_0_WORD_COUNT                    0x1
+#define FUSE_FA_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define FUSE_FA_0_RESET_MASK                    _MK_MASK_CONST(0x1)
+#define FUSE_FA_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define FUSE_FA_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define FUSE_FA_0_READ_MASK                     _MK_MASK_CONST(0x1)
+#define FUSE_FA_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+#define FUSE_FA_0_FA_SHIFT                      _MK_SHIFT_CONST(0)
+#define FUSE_FA_0_FA_FIELD                      (_MK_MASK_CONST(0x1) << FUSE_FA_0_FA_SHIFT)
+#define FUSE_FA_0_FA_RANGE                      0:0
+#define FUSE_FA_0_FA_WOFFSET                    0x0
+#define FUSE_FA_0_FA_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FA_0_FA_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FUSE_FA_0_FA_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FA_0_FA_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_RESERVED_PRODUCTION_0  
+#define FUSE_RESERVED_PRODUCTION_0                      _MK_ADDR_CONST(0x14c)
+#define FUSE_RESERVED_PRODUCTION_0_WORD_COUNT                   0x1
+#define FUSE_RESERVED_PRODUCTION_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_PRODUCTION_0_RESET_MASK                   _MK_MASK_CONST(0xf)
+#define FUSE_RESERVED_PRODUCTION_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_PRODUCTION_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_PRODUCTION_0_READ_MASK                    _MK_MASK_CONST(0xf)
+#define FUSE_RESERVED_PRODUCTION_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_PRODUCTION_0_RESERVED_PRODUCTION_SHIFT                    _MK_SHIFT_CONST(0)
+#define FUSE_RESERVED_PRODUCTION_0_RESERVED_PRODUCTION_FIELD                    (_MK_MASK_CONST(0xf) << FUSE_RESERVED_PRODUCTION_0_RESERVED_PRODUCTION_SHIFT)
+#define FUSE_RESERVED_PRODUCTION_0_RESERVED_PRODUCTION_RANGE                    3:0
+#define FUSE_RESERVED_PRODUCTION_0_RESERVED_PRODUCTION_WOFFSET                  0x0
+#define FUSE_RESERVED_PRODUCTION_0_RESERVED_PRODUCTION_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_PRODUCTION_0_RESERVED_PRODUCTION_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
+#define FUSE_RESERVED_PRODUCTION_0_RESERVED_PRODUCTION_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_PRODUCTION_0_RESERVED_PRODUCTION_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_HDMI_LANE0_CALIB_0  
+#define FUSE_HDMI_LANE0_CALIB_0                 _MK_ADDR_CONST(0x150)
+#define FUSE_HDMI_LANE0_CALIB_0_WORD_COUNT                      0x1
+#define FUSE_HDMI_LANE0_CALIB_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define FUSE_HDMI_LANE0_CALIB_0_RESET_MASK                      _MK_MASK_CONST(0x3f)
+#define FUSE_HDMI_LANE0_CALIB_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define FUSE_HDMI_LANE0_CALIB_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define FUSE_HDMI_LANE0_CALIB_0_READ_MASK                       _MK_MASK_CONST(0x3f)
+#define FUSE_HDMI_LANE0_CALIB_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
+#define FUSE_HDMI_LANE0_CALIB_0_HDMI_LANE0_CALIB_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_HDMI_LANE0_CALIB_0_HDMI_LANE0_CALIB_FIELD                  (_MK_MASK_CONST(0x3f) << FUSE_HDMI_LANE0_CALIB_0_HDMI_LANE0_CALIB_SHIFT)
+#define FUSE_HDMI_LANE0_CALIB_0_HDMI_LANE0_CALIB_RANGE                  5:0
+#define FUSE_HDMI_LANE0_CALIB_0_HDMI_LANE0_CALIB_WOFFSET                        0x0
+#define FUSE_HDMI_LANE0_CALIB_0_HDMI_LANE0_CALIB_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_HDMI_LANE0_CALIB_0_HDMI_LANE0_CALIB_DEFAULT_MASK                   _MK_MASK_CONST(0x3f)
+#define FUSE_HDMI_LANE0_CALIB_0_HDMI_LANE0_CALIB_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_HDMI_LANE0_CALIB_0_HDMI_LANE0_CALIB_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_HDMI_LANE1_CALIB_0  
+#define FUSE_HDMI_LANE1_CALIB_0                 _MK_ADDR_CONST(0x154)
+#define FUSE_HDMI_LANE1_CALIB_0_WORD_COUNT                      0x1
+#define FUSE_HDMI_LANE1_CALIB_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define FUSE_HDMI_LANE1_CALIB_0_RESET_MASK                      _MK_MASK_CONST(0x3f)
+#define FUSE_HDMI_LANE1_CALIB_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define FUSE_HDMI_LANE1_CALIB_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define FUSE_HDMI_LANE1_CALIB_0_READ_MASK                       _MK_MASK_CONST(0x3f)
+#define FUSE_HDMI_LANE1_CALIB_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
+#define FUSE_HDMI_LANE1_CALIB_0_HDMI_LANE1_CALIB_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_HDMI_LANE1_CALIB_0_HDMI_LANE1_CALIB_FIELD                  (_MK_MASK_CONST(0x3f) << FUSE_HDMI_LANE1_CALIB_0_HDMI_LANE1_CALIB_SHIFT)
+#define FUSE_HDMI_LANE1_CALIB_0_HDMI_LANE1_CALIB_RANGE                  5:0
+#define FUSE_HDMI_LANE1_CALIB_0_HDMI_LANE1_CALIB_WOFFSET                        0x0
+#define FUSE_HDMI_LANE1_CALIB_0_HDMI_LANE1_CALIB_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_HDMI_LANE1_CALIB_0_HDMI_LANE1_CALIB_DEFAULT_MASK                   _MK_MASK_CONST(0x3f)
+#define FUSE_HDMI_LANE1_CALIB_0_HDMI_LANE1_CALIB_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_HDMI_LANE1_CALIB_0_HDMI_LANE1_CALIB_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_HDMI_LANE2_CALIB_0  
+#define FUSE_HDMI_LANE2_CALIB_0                 _MK_ADDR_CONST(0x158)
+#define FUSE_HDMI_LANE2_CALIB_0_WORD_COUNT                      0x1
+#define FUSE_HDMI_LANE2_CALIB_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define FUSE_HDMI_LANE2_CALIB_0_RESET_MASK                      _MK_MASK_CONST(0x3f)
+#define FUSE_HDMI_LANE2_CALIB_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define FUSE_HDMI_LANE2_CALIB_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define FUSE_HDMI_LANE2_CALIB_0_READ_MASK                       _MK_MASK_CONST(0x3f)
+#define FUSE_HDMI_LANE2_CALIB_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
+#define FUSE_HDMI_LANE2_CALIB_0_HDMI_LANE2_CALIB_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_HDMI_LANE2_CALIB_0_HDMI_LANE2_CALIB_FIELD                  (_MK_MASK_CONST(0x3f) << FUSE_HDMI_LANE2_CALIB_0_HDMI_LANE2_CALIB_SHIFT)
+#define FUSE_HDMI_LANE2_CALIB_0_HDMI_LANE2_CALIB_RANGE                  5:0
+#define FUSE_HDMI_LANE2_CALIB_0_HDMI_LANE2_CALIB_WOFFSET                        0x0
+#define FUSE_HDMI_LANE2_CALIB_0_HDMI_LANE2_CALIB_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_HDMI_LANE2_CALIB_0_HDMI_LANE2_CALIB_DEFAULT_MASK                   _MK_MASK_CONST(0x3f)
+#define FUSE_HDMI_LANE2_CALIB_0_HDMI_LANE2_CALIB_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_HDMI_LANE2_CALIB_0_HDMI_LANE2_CALIB_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_HDMI_LANE3_CALIB_0  
+#define FUSE_HDMI_LANE3_CALIB_0                 _MK_ADDR_CONST(0x15c)
+#define FUSE_HDMI_LANE3_CALIB_0_WORD_COUNT                      0x1
+#define FUSE_HDMI_LANE3_CALIB_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define FUSE_HDMI_LANE3_CALIB_0_RESET_MASK                      _MK_MASK_CONST(0x3f)
+#define FUSE_HDMI_LANE3_CALIB_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define FUSE_HDMI_LANE3_CALIB_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define FUSE_HDMI_LANE3_CALIB_0_READ_MASK                       _MK_MASK_CONST(0x3f)
+#define FUSE_HDMI_LANE3_CALIB_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
+#define FUSE_HDMI_LANE3_CALIB_0_HDMI_LANE3_CALIB_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_HDMI_LANE3_CALIB_0_HDMI_LANE3_CALIB_FIELD                  (_MK_MASK_CONST(0x3f) << FUSE_HDMI_LANE3_CALIB_0_HDMI_LANE3_CALIB_SHIFT)
+#define FUSE_HDMI_LANE3_CALIB_0_HDMI_LANE3_CALIB_RANGE                  5:0
+#define FUSE_HDMI_LANE3_CALIB_0_HDMI_LANE3_CALIB_WOFFSET                        0x0
+#define FUSE_HDMI_LANE3_CALIB_0_HDMI_LANE3_CALIB_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_HDMI_LANE3_CALIB_0_HDMI_LANE3_CALIB_DEFAULT_MASK                   _MK_MASK_CONST(0x3f)
+#define FUSE_HDMI_LANE3_CALIB_0_HDMI_LANE3_CALIB_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_HDMI_LANE3_CALIB_0_HDMI_LANE3_CALIB_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Reserved address 352 [0x160] 
+
+// Reserved address 356 [0x164] 
+
+// Reserved address 360 [0x168] 
+
+// Reserved address 364 [0x16c] 
+
+// Reserved address 368 [0x170] 
+
+// Reserved address 372 [0x174] 
+
+// Reserved address 376 [0x178] 
+
+// Reserved address 380 [0x17c] 
+
+// Reserved address 384 [0x180] 
+
+// Reserved address 388 [0x184] 
+
+// Reserved address 392 [0x188] 
+
+// Reserved address 396 [0x18c] 
+
+// Reserved address 400 [0x190] 
+
+// Reserved address 404 [0x194] 
+
+// Reserved address 408 [0x198] 
+
+// Reserved address 412 [0x19c] 
+
+// Register FUSE_SECURITY_MODE_0  
+#define FUSE_SECURITY_MODE_0                    _MK_ADDR_CONST(0x1a0)
+#define FUSE_SECURITY_MODE_0_WORD_COUNT                         0x1
+#define FUSE_SECURITY_MODE_0_RESET_VAL                  _MK_MASK_CONST(0x1)
+#define FUSE_SECURITY_MODE_0_RESET_MASK                         _MK_MASK_CONST(0x1)
+#define FUSE_SECURITY_MODE_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define FUSE_SECURITY_MODE_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define FUSE_SECURITY_MODE_0_READ_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_SECURITY_MODE_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
+#define FUSE_SECURITY_MODE_0_SECURITY_MODE_SHIFT                        _MK_SHIFT_CONST(0)
+#define FUSE_SECURITY_MODE_0_SECURITY_MODE_FIELD                        (_MK_MASK_CONST(0x1) << FUSE_SECURITY_MODE_0_SECURITY_MODE_SHIFT)
+#define FUSE_SECURITY_MODE_0_SECURITY_MODE_RANGE                        0:0
+#define FUSE_SECURITY_MODE_0_SECURITY_MODE_WOFFSET                      0x0
+#define FUSE_SECURITY_MODE_0_SECURITY_MODE_DEFAULT                      _MK_MASK_CONST(0x1)
+#define FUSE_SECURITY_MODE_0_SECURITY_MODE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define FUSE_SECURITY_MODE_0_SECURITY_MODE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_SECURITY_MODE_0_SECURITY_MODE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_PRIVATE_KEY0_0  
+#define FUSE_PRIVATE_KEY0_0                     _MK_ADDR_CONST(0x1a4)
+#define FUSE_PRIVATE_KEY0_0_WORD_COUNT                  0x1
+#define FUSE_PRIVATE_KEY0_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY0_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define FUSE_PRIVATE_KEY0_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY0_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY0_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FUSE_PRIVATE_KEY0_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY0_0_PRIVATE_KEY0_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_PRIVATE_KEY0_0_PRIVATE_KEY0_FIELD                  (_MK_MASK_CONST(0xffffffff) << FUSE_PRIVATE_KEY0_0_PRIVATE_KEY0_SHIFT)
+#define FUSE_PRIVATE_KEY0_0_PRIVATE_KEY0_RANGE                  31:0
+#define FUSE_PRIVATE_KEY0_0_PRIVATE_KEY0_WOFFSET                        0x0
+#define FUSE_PRIVATE_KEY0_0_PRIVATE_KEY0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY0_0_PRIVATE_KEY0_DEFAULT_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FUSE_PRIVATE_KEY0_0_PRIVATE_KEY0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY0_0_PRIVATE_KEY0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_PRIVATE_KEY1_0  
+#define FUSE_PRIVATE_KEY1_0                     _MK_ADDR_CONST(0x1a8)
+#define FUSE_PRIVATE_KEY1_0_WORD_COUNT                  0x1
+#define FUSE_PRIVATE_KEY1_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY1_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define FUSE_PRIVATE_KEY1_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY1_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY1_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FUSE_PRIVATE_KEY1_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY1_0_PRIVATE_KEY1_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_PRIVATE_KEY1_0_PRIVATE_KEY1_FIELD                  (_MK_MASK_CONST(0xffffffff) << FUSE_PRIVATE_KEY1_0_PRIVATE_KEY1_SHIFT)
+#define FUSE_PRIVATE_KEY1_0_PRIVATE_KEY1_RANGE                  31:0
+#define FUSE_PRIVATE_KEY1_0_PRIVATE_KEY1_WOFFSET                        0x0
+#define FUSE_PRIVATE_KEY1_0_PRIVATE_KEY1_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY1_0_PRIVATE_KEY1_DEFAULT_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FUSE_PRIVATE_KEY1_0_PRIVATE_KEY1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY1_0_PRIVATE_KEY1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_PRIVATE_KEY2_0  
+#define FUSE_PRIVATE_KEY2_0                     _MK_ADDR_CONST(0x1ac)
+#define FUSE_PRIVATE_KEY2_0_WORD_COUNT                  0x1
+#define FUSE_PRIVATE_KEY2_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY2_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define FUSE_PRIVATE_KEY2_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY2_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY2_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FUSE_PRIVATE_KEY2_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY2_0_PRIVATE_KEY2_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_PRIVATE_KEY2_0_PRIVATE_KEY2_FIELD                  (_MK_MASK_CONST(0xffffffff) << FUSE_PRIVATE_KEY2_0_PRIVATE_KEY2_SHIFT)
+#define FUSE_PRIVATE_KEY2_0_PRIVATE_KEY2_RANGE                  31:0
+#define FUSE_PRIVATE_KEY2_0_PRIVATE_KEY2_WOFFSET                        0x0
+#define FUSE_PRIVATE_KEY2_0_PRIVATE_KEY2_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY2_0_PRIVATE_KEY2_DEFAULT_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FUSE_PRIVATE_KEY2_0_PRIVATE_KEY2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY2_0_PRIVATE_KEY2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_PRIVATE_KEY3_0  
+#define FUSE_PRIVATE_KEY3_0                     _MK_ADDR_CONST(0x1b0)
+#define FUSE_PRIVATE_KEY3_0_WORD_COUNT                  0x1
+#define FUSE_PRIVATE_KEY3_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY3_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define FUSE_PRIVATE_KEY3_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY3_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY3_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FUSE_PRIVATE_KEY3_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY3_0_PRIVATE_KEY3_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_PRIVATE_KEY3_0_PRIVATE_KEY3_FIELD                  (_MK_MASK_CONST(0xffffffff) << FUSE_PRIVATE_KEY3_0_PRIVATE_KEY3_SHIFT)
+#define FUSE_PRIVATE_KEY3_0_PRIVATE_KEY3_RANGE                  31:0
+#define FUSE_PRIVATE_KEY3_0_PRIVATE_KEY3_WOFFSET                        0x0
+#define FUSE_PRIVATE_KEY3_0_PRIVATE_KEY3_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY3_0_PRIVATE_KEY3_DEFAULT_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FUSE_PRIVATE_KEY3_0_PRIVATE_KEY3_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY3_0_PRIVATE_KEY3_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_PRIVATE_KEY4_0  
+#define FUSE_PRIVATE_KEY4_0                     _MK_ADDR_CONST(0x1b4)
+#define FUSE_PRIVATE_KEY4_0_WORD_COUNT                  0x1
+#define FUSE_PRIVATE_KEY4_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY4_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define FUSE_PRIVATE_KEY4_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY4_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY4_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FUSE_PRIVATE_KEY4_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY4_0_PRIVATE_KEY4_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_PRIVATE_KEY4_0_PRIVATE_KEY4_FIELD                  (_MK_MASK_CONST(0xffffffff) << FUSE_PRIVATE_KEY4_0_PRIVATE_KEY4_SHIFT)
+#define FUSE_PRIVATE_KEY4_0_PRIVATE_KEY4_RANGE                  31:0
+#define FUSE_PRIVATE_KEY4_0_PRIVATE_KEY4_WOFFSET                        0x0
+#define FUSE_PRIVATE_KEY4_0_PRIVATE_KEY4_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY4_0_PRIVATE_KEY4_DEFAULT_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FUSE_PRIVATE_KEY4_0_PRIVATE_KEY4_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY4_0_PRIVATE_KEY4_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_ARM_JTAG_DIS_0  
+#define FUSE_ARM_JTAG_DIS_0                     _MK_ADDR_CONST(0x1b8)
+#define FUSE_ARM_JTAG_DIS_0_WORD_COUNT                  0x1
+#define FUSE_ARM_JTAG_DIS_0_RESET_VAL                   _MK_MASK_CONST(0x1)
+#define FUSE_ARM_JTAG_DIS_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_ARM_JTAG_DIS_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_ARM_JTAG_DIS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_ARM_JTAG_DIS_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_ARM_JTAG_DIS_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_ARM_JTAG_DIS_0_ARM_JTAG_DIS_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_ARM_JTAG_DIS_0_ARM_JTAG_DIS_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_ARM_JTAG_DIS_0_ARM_JTAG_DIS_SHIFT)
+#define FUSE_ARM_JTAG_DIS_0_ARM_JTAG_DIS_RANGE                  0:0
+#define FUSE_ARM_JTAG_DIS_0_ARM_JTAG_DIS_WOFFSET                        0x0
+#define FUSE_ARM_JTAG_DIS_0_ARM_JTAG_DIS_DEFAULT                        _MK_MASK_CONST(0x1)
+#define FUSE_ARM_JTAG_DIS_0_ARM_JTAG_DIS_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_ARM_JTAG_DIS_0_ARM_JTAG_DIS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_ARM_JTAG_DIS_0_ARM_JTAG_DIS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_BOOT_DEVICE_INFO_0  
+#define FUSE_BOOT_DEVICE_INFO_0                 _MK_ADDR_CONST(0x1bc)
+#define FUSE_BOOT_DEVICE_INFO_0_WORD_COUNT                      0x1
+#define FUSE_BOOT_DEVICE_INFO_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define FUSE_BOOT_DEVICE_INFO_0_RESET_MASK                      _MK_MASK_CONST(0x7f)
+#define FUSE_BOOT_DEVICE_INFO_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define FUSE_BOOT_DEVICE_INFO_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define FUSE_BOOT_DEVICE_INFO_0_READ_MASK                       _MK_MASK_CONST(0x7f)
+#define FUSE_BOOT_DEVICE_INFO_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
+#define FUSE_BOOT_DEVICE_INFO_0_BOOT_DEVICE_INFO_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_BOOT_DEVICE_INFO_0_BOOT_DEVICE_INFO_FIELD                  (_MK_MASK_CONST(0x7f) << FUSE_BOOT_DEVICE_INFO_0_BOOT_DEVICE_INFO_SHIFT)
+#define FUSE_BOOT_DEVICE_INFO_0_BOOT_DEVICE_INFO_RANGE                  6:0
+#define FUSE_BOOT_DEVICE_INFO_0_BOOT_DEVICE_INFO_WOFFSET                        0x0
+#define FUSE_BOOT_DEVICE_INFO_0_BOOT_DEVICE_INFO_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_BOOT_DEVICE_INFO_0_BOOT_DEVICE_INFO_DEFAULT_MASK                   _MK_MASK_CONST(0x7f)
+#define FUSE_BOOT_DEVICE_INFO_0_BOOT_DEVICE_INFO_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_BOOT_DEVICE_INFO_0_BOOT_DEVICE_INFO_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_RESERVED_SW_0  
+#define FUSE_RESERVED_SW_0                      _MK_ADDR_CONST(0x1c0)
+#define FUSE_RESERVED_SW_0_WORD_COUNT                   0x1
+#define FUSE_RESERVED_SW_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_SW_0_RESET_MASK                   _MK_MASK_CONST(0xff)
+#define FUSE_RESERVED_SW_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_SW_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_SW_0_READ_MASK                    _MK_MASK_CONST(0xff)
+#define FUSE_RESERVED_SW_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_SW_0_RESERVED_SW_SHIFT                    _MK_SHIFT_CONST(0)
+#define FUSE_RESERVED_SW_0_RESERVED_SW_FIELD                    (_MK_MASK_CONST(0xff) << FUSE_RESERVED_SW_0_RESERVED_SW_SHIFT)
+#define FUSE_RESERVED_SW_0_RESERVED_SW_RANGE                    7:0
+#define FUSE_RESERVED_SW_0_RESERVED_SW_WOFFSET                  0x0
+#define FUSE_RESERVED_SW_0_RESERVED_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_SW_0_RESERVED_SW_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
+#define FUSE_RESERVED_SW_0_RESERVED_SW_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_SW_0_RESERVED_SW_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_0_0  
+#define FUSE_SPARE_BIT_0_0                      _MK_ADDR_CONST(0x1c4)
+#define FUSE_SPARE_BIT_0_0_WORD_COUNT                   0x1
+#define FUSE_SPARE_BIT_0_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_0_0_RESET_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_0_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_0_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_0_0_READ_MASK                    _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_0_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_0_0_SPARE_BIT_0_SHIFT                    _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_0_0_SPARE_BIT_0_FIELD                    (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_0_0_SPARE_BIT_0_SHIFT)
+#define FUSE_SPARE_BIT_0_0_SPARE_BIT_0_RANGE                    0:0
+#define FUSE_SPARE_BIT_0_0_SPARE_BIT_0_WOFFSET                  0x0
+#define FUSE_SPARE_BIT_0_0_SPARE_BIT_0_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_0_0_SPARE_BIT_0_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_0_0_SPARE_BIT_0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_0_0_SPARE_BIT_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_1_0  
+#define FUSE_SPARE_BIT_1_0                      _MK_ADDR_CONST(0x1c8)
+#define FUSE_SPARE_BIT_1_0_WORD_COUNT                   0x1
+#define FUSE_SPARE_BIT_1_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_1_0_RESET_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_1_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_1_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_1_0_READ_MASK                    _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_1_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_1_0_SPARE_BIT_1_SHIFT                    _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_1_0_SPARE_BIT_1_FIELD                    (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_1_0_SPARE_BIT_1_SHIFT)
+#define FUSE_SPARE_BIT_1_0_SPARE_BIT_1_RANGE                    0:0
+#define FUSE_SPARE_BIT_1_0_SPARE_BIT_1_WOFFSET                  0x0
+#define FUSE_SPARE_BIT_1_0_SPARE_BIT_1_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_1_0_SPARE_BIT_1_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_1_0_SPARE_BIT_1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_1_0_SPARE_BIT_1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_2_0  
+#define FUSE_SPARE_BIT_2_0                      _MK_ADDR_CONST(0x1cc)
+#define FUSE_SPARE_BIT_2_0_WORD_COUNT                   0x1
+#define FUSE_SPARE_BIT_2_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_2_0_RESET_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_2_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_2_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_2_0_READ_MASK                    _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_2_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_2_0_SPARE_BIT_2_SHIFT                    _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_2_0_SPARE_BIT_2_FIELD                    (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_2_0_SPARE_BIT_2_SHIFT)
+#define FUSE_SPARE_BIT_2_0_SPARE_BIT_2_RANGE                    0:0
+#define FUSE_SPARE_BIT_2_0_SPARE_BIT_2_WOFFSET                  0x0
+#define FUSE_SPARE_BIT_2_0_SPARE_BIT_2_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_2_0_SPARE_BIT_2_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_2_0_SPARE_BIT_2_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_2_0_SPARE_BIT_2_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_3_0  
+#define FUSE_SPARE_BIT_3_0                      _MK_ADDR_CONST(0x1d0)
+#define FUSE_SPARE_BIT_3_0_WORD_COUNT                   0x1
+#define FUSE_SPARE_BIT_3_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_3_0_RESET_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_3_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_3_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_3_0_READ_MASK                    _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_3_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_3_0_SPARE_BIT_3_SHIFT                    _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_3_0_SPARE_BIT_3_FIELD                    (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_3_0_SPARE_BIT_3_SHIFT)
+#define FUSE_SPARE_BIT_3_0_SPARE_BIT_3_RANGE                    0:0
+#define FUSE_SPARE_BIT_3_0_SPARE_BIT_3_WOFFSET                  0x0
+#define FUSE_SPARE_BIT_3_0_SPARE_BIT_3_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_3_0_SPARE_BIT_3_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_3_0_SPARE_BIT_3_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_3_0_SPARE_BIT_3_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_4_0  
+#define FUSE_SPARE_BIT_4_0                      _MK_ADDR_CONST(0x1d4)
+#define FUSE_SPARE_BIT_4_0_WORD_COUNT                   0x1
+#define FUSE_SPARE_BIT_4_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_4_0_RESET_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_4_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_4_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_4_0_READ_MASK                    _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_4_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_4_0_SPARE_BIT_4_SHIFT                    _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_4_0_SPARE_BIT_4_FIELD                    (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_4_0_SPARE_BIT_4_SHIFT)
+#define FUSE_SPARE_BIT_4_0_SPARE_BIT_4_RANGE                    0:0
+#define FUSE_SPARE_BIT_4_0_SPARE_BIT_4_WOFFSET                  0x0
+#define FUSE_SPARE_BIT_4_0_SPARE_BIT_4_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_4_0_SPARE_BIT_4_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_4_0_SPARE_BIT_4_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_4_0_SPARE_BIT_4_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_5_0  
+#define FUSE_SPARE_BIT_5_0                      _MK_ADDR_CONST(0x1d8)
+#define FUSE_SPARE_BIT_5_0_WORD_COUNT                   0x1
+#define FUSE_SPARE_BIT_5_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_5_0_RESET_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_5_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_5_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_5_0_READ_MASK                    _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_5_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_5_0_SPARE_BIT_5_SHIFT                    _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_5_0_SPARE_BIT_5_FIELD                    (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_5_0_SPARE_BIT_5_SHIFT)
+#define FUSE_SPARE_BIT_5_0_SPARE_BIT_5_RANGE                    0:0
+#define FUSE_SPARE_BIT_5_0_SPARE_BIT_5_WOFFSET                  0x0
+#define FUSE_SPARE_BIT_5_0_SPARE_BIT_5_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_5_0_SPARE_BIT_5_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_5_0_SPARE_BIT_5_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_5_0_SPARE_BIT_5_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_6_0  
+#define FUSE_SPARE_BIT_6_0                      _MK_ADDR_CONST(0x1dc)
+#define FUSE_SPARE_BIT_6_0_WORD_COUNT                   0x1
+#define FUSE_SPARE_BIT_6_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_6_0_RESET_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_6_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_6_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_6_0_READ_MASK                    _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_6_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_6_0_SPARE_BIT_6_SHIFT                    _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_6_0_SPARE_BIT_6_FIELD                    (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_6_0_SPARE_BIT_6_SHIFT)
+#define FUSE_SPARE_BIT_6_0_SPARE_BIT_6_RANGE                    0:0
+#define FUSE_SPARE_BIT_6_0_SPARE_BIT_6_WOFFSET                  0x0
+#define FUSE_SPARE_BIT_6_0_SPARE_BIT_6_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_6_0_SPARE_BIT_6_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_6_0_SPARE_BIT_6_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_6_0_SPARE_BIT_6_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_7_0  
+#define FUSE_SPARE_BIT_7_0                      _MK_ADDR_CONST(0x1e0)
+#define FUSE_SPARE_BIT_7_0_WORD_COUNT                   0x1
+#define FUSE_SPARE_BIT_7_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_7_0_RESET_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_7_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_7_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_7_0_READ_MASK                    _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_7_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_7_0_SPARE_BIT_7_SHIFT                    _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_7_0_SPARE_BIT_7_FIELD                    (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_7_0_SPARE_BIT_7_SHIFT)
+#define FUSE_SPARE_BIT_7_0_SPARE_BIT_7_RANGE                    0:0
+#define FUSE_SPARE_BIT_7_0_SPARE_BIT_7_WOFFSET                  0x0
+#define FUSE_SPARE_BIT_7_0_SPARE_BIT_7_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_7_0_SPARE_BIT_7_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_7_0_SPARE_BIT_7_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_7_0_SPARE_BIT_7_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_8_0  
+#define FUSE_SPARE_BIT_8_0                      _MK_ADDR_CONST(0x1e4)
+#define FUSE_SPARE_BIT_8_0_WORD_COUNT                   0x1
+#define FUSE_SPARE_BIT_8_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_8_0_RESET_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_8_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_8_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_8_0_READ_MASK                    _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_8_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_8_0_SPARE_BIT_8_SHIFT                    _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_8_0_SPARE_BIT_8_FIELD                    (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_8_0_SPARE_BIT_8_SHIFT)
+#define FUSE_SPARE_BIT_8_0_SPARE_BIT_8_RANGE                    0:0
+#define FUSE_SPARE_BIT_8_0_SPARE_BIT_8_WOFFSET                  0x0
+#define FUSE_SPARE_BIT_8_0_SPARE_BIT_8_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_8_0_SPARE_BIT_8_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_8_0_SPARE_BIT_8_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_8_0_SPARE_BIT_8_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_9_0  
+#define FUSE_SPARE_BIT_9_0                      _MK_ADDR_CONST(0x1e8)
+#define FUSE_SPARE_BIT_9_0_WORD_COUNT                   0x1
+#define FUSE_SPARE_BIT_9_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_9_0_RESET_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_9_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_9_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_9_0_READ_MASK                    _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_9_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_9_0_SPARE_BIT_9_SHIFT                    _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_9_0_SPARE_BIT_9_FIELD                    (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_9_0_SPARE_BIT_9_SHIFT)
+#define FUSE_SPARE_BIT_9_0_SPARE_BIT_9_RANGE                    0:0
+#define FUSE_SPARE_BIT_9_0_SPARE_BIT_9_WOFFSET                  0x0
+#define FUSE_SPARE_BIT_9_0_SPARE_BIT_9_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_9_0_SPARE_BIT_9_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_9_0_SPARE_BIT_9_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_9_0_SPARE_BIT_9_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_10_0  
+#define FUSE_SPARE_BIT_10_0                     _MK_ADDR_CONST(0x1ec)
+#define FUSE_SPARE_BIT_10_0_WORD_COUNT                  0x1
+#define FUSE_SPARE_BIT_10_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_10_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_10_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_10_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_10_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_10_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_10_0_SPARE_BIT_10_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_10_0_SPARE_BIT_10_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_10_0_SPARE_BIT_10_SHIFT)
+#define FUSE_SPARE_BIT_10_0_SPARE_BIT_10_RANGE                  0:0
+#define FUSE_SPARE_BIT_10_0_SPARE_BIT_10_WOFFSET                        0x0
+#define FUSE_SPARE_BIT_10_0_SPARE_BIT_10_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_10_0_SPARE_BIT_10_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_10_0_SPARE_BIT_10_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_10_0_SPARE_BIT_10_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_11_0  
+#define FUSE_SPARE_BIT_11_0                     _MK_ADDR_CONST(0x1f0)
+#define FUSE_SPARE_BIT_11_0_WORD_COUNT                  0x1
+#define FUSE_SPARE_BIT_11_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_11_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_11_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_11_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_11_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_11_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_11_0_SPARE_BIT_11_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_11_0_SPARE_BIT_11_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_11_0_SPARE_BIT_11_SHIFT)
+#define FUSE_SPARE_BIT_11_0_SPARE_BIT_11_RANGE                  0:0
+#define FUSE_SPARE_BIT_11_0_SPARE_BIT_11_WOFFSET                        0x0
+#define FUSE_SPARE_BIT_11_0_SPARE_BIT_11_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_11_0_SPARE_BIT_11_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_11_0_SPARE_BIT_11_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_11_0_SPARE_BIT_11_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_12_0  
+#define FUSE_SPARE_BIT_12_0                     _MK_ADDR_CONST(0x1f4)
+#define FUSE_SPARE_BIT_12_0_WORD_COUNT                  0x1
+#define FUSE_SPARE_BIT_12_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_12_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_12_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_12_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_12_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_12_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_12_0_SPARE_BIT_12_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_12_0_SPARE_BIT_12_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_12_0_SPARE_BIT_12_SHIFT)
+#define FUSE_SPARE_BIT_12_0_SPARE_BIT_12_RANGE                  0:0
+#define FUSE_SPARE_BIT_12_0_SPARE_BIT_12_WOFFSET                        0x0
+#define FUSE_SPARE_BIT_12_0_SPARE_BIT_12_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_12_0_SPARE_BIT_12_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_12_0_SPARE_BIT_12_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_12_0_SPARE_BIT_12_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_13_0  
+#define FUSE_SPARE_BIT_13_0                     _MK_ADDR_CONST(0x1f8)
+#define FUSE_SPARE_BIT_13_0_WORD_COUNT                  0x1
+#define FUSE_SPARE_BIT_13_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_13_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_13_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_13_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_13_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_13_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_13_0_SPARE_BIT_13_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_13_0_SPARE_BIT_13_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_13_0_SPARE_BIT_13_SHIFT)
+#define FUSE_SPARE_BIT_13_0_SPARE_BIT_13_RANGE                  0:0
+#define FUSE_SPARE_BIT_13_0_SPARE_BIT_13_WOFFSET                        0x0
+#define FUSE_SPARE_BIT_13_0_SPARE_BIT_13_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_13_0_SPARE_BIT_13_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_13_0_SPARE_BIT_13_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_13_0_SPARE_BIT_13_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_14_0  
+#define FUSE_SPARE_BIT_14_0                     _MK_ADDR_CONST(0x1fc)
+#define FUSE_SPARE_BIT_14_0_WORD_COUNT                  0x1
+#define FUSE_SPARE_BIT_14_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_14_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_14_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_14_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_14_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_14_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_14_0_SPARE_BIT_14_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_14_0_SPARE_BIT_14_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_14_0_SPARE_BIT_14_SHIFT)
+#define FUSE_SPARE_BIT_14_0_SPARE_BIT_14_RANGE                  0:0
+#define FUSE_SPARE_BIT_14_0_SPARE_BIT_14_WOFFSET                        0x0
+#define FUSE_SPARE_BIT_14_0_SPARE_BIT_14_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_14_0_SPARE_BIT_14_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_14_0_SPARE_BIT_14_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_14_0_SPARE_BIT_14_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_15_0  
+#define FUSE_SPARE_BIT_15_0                     _MK_ADDR_CONST(0x200)
+#define FUSE_SPARE_BIT_15_0_WORD_COUNT                  0x1
+#define FUSE_SPARE_BIT_15_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_15_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_15_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_15_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_15_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_15_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_15_0_SPARE_BIT_15_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_15_0_SPARE_BIT_15_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_15_0_SPARE_BIT_15_SHIFT)
+#define FUSE_SPARE_BIT_15_0_SPARE_BIT_15_RANGE                  0:0
+#define FUSE_SPARE_BIT_15_0_SPARE_BIT_15_WOFFSET                        0x0
+#define FUSE_SPARE_BIT_15_0_SPARE_BIT_15_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_15_0_SPARE_BIT_15_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_15_0_SPARE_BIT_15_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_15_0_SPARE_BIT_15_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+//
+// REGISTER LIST
+//
+#define LIST_ARFUSE_REGS(_op_) \
+_op_(FUSE_FUSECTRL_0) \
+_op_(FUSE_FUSETIME1_0) \
+_op_(FUSE_FUSETIME2_0) \
+_op_(FUSE_FUSEDATA0_0) \
+_op_(FUSE_FUSEDATA1_0) \
+_op_(FUSE_FUSEDATA2_0) \
+_op_(FUSE_FUSEDATA3_0) \
+_op_(FUSE_FUSEDATA4_0) \
+_op_(FUSE_FUSEDATA5_0) \
+_op_(FUSE_FUSEDATA6_0) \
+_op_(FUSE_FUSEDATA7_0) \
+_op_(FUSE_FUSEDATA8_0) \
+_op_(FUSE_FUSEDATA9_0) \
+_op_(FUSE_FUSEDATA10_0) \
+_op_(FUSE_FUSEDATA11_0) \
+_op_(FUSE_FUSEDATA12_0) \
+_op_(FUSE_FUSEDATA13_0) \
+_op_(FUSE_FUSEDATA14_0) \
+_op_(FUSE_FUSEDATA15_0) \
+_op_(FUSE_FUSEDATA16_0) \
+_op_(FUSE_FUSEDATA17_0) \
+_op_(FUSE_FUSEDATA18_0) \
+_op_(FUSE_FUSEDATA19_0) \
+_op_(FUSE_FUSEDATA20_0) \
+_op_(FUSE_FUSEDATA21_0) \
+_op_(FUSE_FUSEWRDATA0_0) \
+_op_(FUSE_FUSEWRDATA1_0) \
+_op_(FUSE_FUSEWRDATA2_0) \
+_op_(FUSE_FUSEWRDATA3_0) \
+_op_(FUSE_FUSEWRDATA4_0) \
+_op_(FUSE_FUSEWRDATA5_0) \
+_op_(FUSE_FUSEWRDATA6_0) \
+_op_(FUSE_FUSEWRDATA7_0) \
+_op_(FUSE_FUSEWRDATA8_0) \
+_op_(FUSE_FUSEWRDATA9_0) \
+_op_(FUSE_FUSEWRDATA10_0) \
+_op_(FUSE_FUSEWRDATA11_0) \
+_op_(FUSE_FUSEWRDATA12_0) \
+_op_(FUSE_FUSEWRDATA13_0) \
+_op_(FUSE_FUSEWRDATA14_0) \
+_op_(FUSE_FUSEWRDATA15_0) \
+_op_(FUSE_FUSEWRDATA16_0) \
+_op_(FUSE_FUSEWRDATA17_0) \
+_op_(FUSE_FUSEWRDATA18_0) \
+_op_(FUSE_FUSEWRDATA19_0) \
+_op_(FUSE_FUSEWRDATA20_0) \
+_op_(FUSE_FUSEWRDATA21_0) \
+_op_(FUSE_FUSEBYPASS_0) \
+_op_(FUSE_PRIVATEKEYDISABLE_0) \
+_op_(FUSE_PRODUCTION_MODE_0) \
+_op_(FUSE_JTAG_SECUREID_VALID_0) \
+_op_(FUSE_JTAG_SECUREID_0_0) \
+_op_(FUSE_JTAG_SECUREID_1_0) \
+_op_(FUSE_SKU_INFO_0) \
+_op_(FUSE_PROCESS_CALIB_0) \
+_op_(FUSE_IO_CALIB_0) \
+_op_(FUSE_DAC_CRT_CALIB_0) \
+_op_(FUSE_DAC_HDTV_CALIB_0) \
+_op_(FUSE_DAC_SDTV_CALIB_0) \
+_op_(FUSE_CMC_DATARAM0_0_0) \
+_op_(FUSE_CMC_DATARAM0_1_0) \
+_op_(FUSE_CMC_DATARAM0_2_0) \
+_op_(FUSE_CMC_DATARAM0_3_0) \
+_op_(FUSE_CMC_DATARAM1_0_0) \
+_op_(FUSE_CMC_DATARAM1_1_0) \
+_op_(FUSE_CMC_DATARAM1_2_0) \
+_op_(FUSE_CMC_DATARAM1_3_0) \
+_op_(FUSE_FA_0) \
+_op_(FUSE_RESERVED_PRODUCTION_0) \
+_op_(FUSE_HDMI_LANE0_CALIB_0) \
+_op_(FUSE_HDMI_LANE1_CALIB_0) \
+_op_(FUSE_HDMI_LANE2_CALIB_0) \
+_op_(FUSE_HDMI_LANE3_CALIB_0) \
+_op_(FUSE_SECURITY_MODE_0) \
+_op_(FUSE_PRIVATE_KEY0_0) \
+_op_(FUSE_PRIVATE_KEY1_0) \
+_op_(FUSE_PRIVATE_KEY2_0) \
+_op_(FUSE_PRIVATE_KEY3_0) \
+_op_(FUSE_PRIVATE_KEY4_0) \
+_op_(FUSE_ARM_JTAG_DIS_0) \
+_op_(FUSE_BOOT_DEVICE_INFO_0) \
+_op_(FUSE_RESERVED_SW_0) \
+_op_(FUSE_SPARE_BIT_0_0) \
+_op_(FUSE_SPARE_BIT_1_0) \
+_op_(FUSE_SPARE_BIT_2_0) \
+_op_(FUSE_SPARE_BIT_3_0) \
+_op_(FUSE_SPARE_BIT_4_0) \
+_op_(FUSE_SPARE_BIT_5_0) \
+_op_(FUSE_SPARE_BIT_6_0) \
+_op_(FUSE_SPARE_BIT_7_0) \
+_op_(FUSE_SPARE_BIT_8_0) \
+_op_(FUSE_SPARE_BIT_9_0) \
+_op_(FUSE_SPARE_BIT_10_0) \
+_op_(FUSE_SPARE_BIT_11_0) \
+_op_(FUSE_SPARE_BIT_12_0) \
+_op_(FUSE_SPARE_BIT_13_0) \
+_op_(FUSE_SPARE_BIT_14_0) \
+_op_(FUSE_SPARE_BIT_15_0)
+
+
+//
+// ADDRESS SPACES
+//
+
+#define BASE_ADDRESS_FUSE       0x00000000
+
+//
+// ARFUSE REGISTER BANKS
+//
+
+#define FUSE0_FIRST_REG 0x0000 // FUSE_FUSECTRL_0
+#define FUSE0_LAST_REG 0x00b8 // FUSE_FUSEWRDATA21_0
+#define FUSE1_FIRST_REG 0x00e0 // FUSE_FUSEBYPASS_0
+#define FUSE1_LAST_REG 0x00e4 // FUSE_PRIVATEKEYDISABLE_0
+#define FUSE2_FIRST_REG 0x0100 // FUSE_PRODUCTION_MODE_0
+#define FUSE2_LAST_REG 0x015c // FUSE_HDMI_LANE3_CALIB_0
+#define FUSE3_FIRST_REG 0x01a0 // FUSE_SECURITY_MODE_0
+#define FUSE3_LAST_REG 0x0200 // FUSE_SPARE_BIT_15_0
+
+#ifndef _MK_SHIFT_CONST
+  #define _MK_SHIFT_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_MASK_CONST
+  #define _MK_MASK_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_ENUM_CONST
+  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
+#endif
+#ifndef _MK_ADDR_CONST
+  #define _MK_ADDR_CONST(_constant_) _constant_
+#endif
+
+#endif // ifndef ___ARFUSE_H_INC_
diff --git a/arch/arm/mach-tegra/include/ap15/arictlr.h b/arch/arm/mach-tegra/include/ap15/arictlr.h
new file mode 100644
index 000000000000..e7e534faa38d
--- /dev/null
+++ b/arch/arm/mach-tegra/include/ap15/arictlr.h
@@ -0,0 +1,407 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+//
+// DO NOT EDIT - generated by simspec!
+//
+
+#ifndef ___ARICTLR_H_INC_
+#define ___ARICTLR_H_INC_
+
+// Register ICTLR_VIRQ_CPU_0  
+#define ICTLR_VIRQ_CPU_0                        _MK_ADDR_CONST(0x0)
+#define ICTLR_VIRQ_CPU_0_WORD_COUNT                     0x1
+#define ICTLR_VIRQ_CPU_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define ICTLR_VIRQ_CPU_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
+#define ICTLR_VIRQ_CPU_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define ICTLR_VIRQ_CPU_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define ICTLR_VIRQ_CPU_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define ICTLR_VIRQ_CPU_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
+// Flags set by Hardware, cleared by SW
+#define ICTLR_VIRQ_CPU_0_IRQ31_IRQ0_SHIFT                       _MK_SHIFT_CONST(0)
+#define ICTLR_VIRQ_CPU_0_IRQ31_IRQ0_FIELD                       (_MK_MASK_CONST(0xffffffff) << ICTLR_VIRQ_CPU_0_IRQ31_IRQ0_SHIFT)
+#define ICTLR_VIRQ_CPU_0_IRQ31_IRQ0_RANGE                       31:0
+#define ICTLR_VIRQ_CPU_0_IRQ31_IRQ0_WOFFSET                     0x0
+#define ICTLR_VIRQ_CPU_0_IRQ31_IRQ0_DEFAULT                     _MK_MASK_CONST(0x0)
+#define ICTLR_VIRQ_CPU_0_IRQ31_IRQ0_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
+#define ICTLR_VIRQ_CPU_0_IRQ31_IRQ0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define ICTLR_VIRQ_CPU_0_IRQ31_IRQ0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register ICTLR_VIRQ_COP_0  
+#define ICTLR_VIRQ_COP_0                        _MK_ADDR_CONST(0x4)
+#define ICTLR_VIRQ_COP_0_WORD_COUNT                     0x1
+#define ICTLR_VIRQ_COP_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define ICTLR_VIRQ_COP_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
+#define ICTLR_VIRQ_COP_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define ICTLR_VIRQ_COP_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define ICTLR_VIRQ_COP_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define ICTLR_VIRQ_COP_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
+// Flags set by Hardware, cleared by SW
+#define ICTLR_VIRQ_COP_0_IRQ31_IRQ0_SHIFT                       _MK_SHIFT_CONST(0)
+#define ICTLR_VIRQ_COP_0_IRQ31_IRQ0_FIELD                       (_MK_MASK_CONST(0xffffffff) << ICTLR_VIRQ_COP_0_IRQ31_IRQ0_SHIFT)
+#define ICTLR_VIRQ_COP_0_IRQ31_IRQ0_RANGE                       31:0
+#define ICTLR_VIRQ_COP_0_IRQ31_IRQ0_WOFFSET                     0x0
+#define ICTLR_VIRQ_COP_0_IRQ31_IRQ0_DEFAULT                     _MK_MASK_CONST(0x0)
+#define ICTLR_VIRQ_COP_0_IRQ31_IRQ0_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
+#define ICTLR_VIRQ_COP_0_IRQ31_IRQ0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define ICTLR_VIRQ_COP_0_IRQ31_IRQ0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register ICTLR_VFIQ_CPU_0  
+#define ICTLR_VFIQ_CPU_0                        _MK_ADDR_CONST(0x8)
+#define ICTLR_VFIQ_CPU_0_WORD_COUNT                     0x1
+#define ICTLR_VFIQ_CPU_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define ICTLR_VFIQ_CPU_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
+#define ICTLR_VFIQ_CPU_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define ICTLR_VFIQ_CPU_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define ICTLR_VFIQ_CPU_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define ICTLR_VFIQ_CPU_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
+// Flags set by Hardware, cleared by SW
+#define ICTLR_VFIQ_CPU_0_FIQ31_FIQ0_SHIFT                       _MK_SHIFT_CONST(0)
+#define ICTLR_VFIQ_CPU_0_FIQ31_FIQ0_FIELD                       (_MK_MASK_CONST(0xffffffff) << ICTLR_VFIQ_CPU_0_FIQ31_FIQ0_SHIFT)
+#define ICTLR_VFIQ_CPU_0_FIQ31_FIQ0_RANGE                       31:0
+#define ICTLR_VFIQ_CPU_0_FIQ31_FIQ0_WOFFSET                     0x0
+#define ICTLR_VFIQ_CPU_0_FIQ31_FIQ0_DEFAULT                     _MK_MASK_CONST(0x0)
+#define ICTLR_VFIQ_CPU_0_FIQ31_FIQ0_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
+#define ICTLR_VFIQ_CPU_0_FIQ31_FIQ0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define ICTLR_VFIQ_CPU_0_FIQ31_FIQ0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register ICTLR_VFIQ_COP_0  
+#define ICTLR_VFIQ_COP_0                        _MK_ADDR_CONST(0xc)
+#define ICTLR_VFIQ_COP_0_WORD_COUNT                     0x1
+#define ICTLR_VFIQ_COP_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define ICTLR_VFIQ_COP_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
+#define ICTLR_VFIQ_COP_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define ICTLR_VFIQ_COP_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define ICTLR_VFIQ_COP_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define ICTLR_VFIQ_COP_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
+// Flags set by Hardware, cleared by SW
+#define ICTLR_VFIQ_COP_0_FIQ31_FIQ0_SHIFT                       _MK_SHIFT_CONST(0)
+#define ICTLR_VFIQ_COP_0_FIQ31_FIQ0_FIELD                       (_MK_MASK_CONST(0xffffffff) << ICTLR_VFIQ_COP_0_FIQ31_FIQ0_SHIFT)
+#define ICTLR_VFIQ_COP_0_FIQ31_FIQ0_RANGE                       31:0
+#define ICTLR_VFIQ_COP_0_FIQ31_FIQ0_WOFFSET                     0x0
+#define ICTLR_VFIQ_COP_0_FIQ31_FIQ0_DEFAULT                     _MK_MASK_CONST(0x0)
+#define ICTLR_VFIQ_COP_0_FIQ31_FIQ0_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
+#define ICTLR_VFIQ_COP_0_FIQ31_FIQ0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define ICTLR_VFIQ_COP_0_FIQ31_FIQ0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register ICTLR_ISR_0  
+#define ICTLR_ISR_0                     _MK_ADDR_CONST(0x10)
+#define ICTLR_ISR_0_WORD_COUNT                  0x1
+#define ICTLR_ISR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define ICTLR_ISR_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define ICTLR_ISR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define ICTLR_ISR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define ICTLR_ISR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define ICTLR_ISR_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+// Read-only. Set by hardware event, cleared at  source by software.
+#define ICTLR_ISR_0_ISR31_ISR0_SHIFT                    _MK_SHIFT_CONST(0)
+#define ICTLR_ISR_0_ISR31_ISR0_FIELD                    (_MK_MASK_CONST(0xffffffff) << ICTLR_ISR_0_ISR31_ISR0_SHIFT)
+#define ICTLR_ISR_0_ISR31_ISR0_RANGE                    31:0
+#define ICTLR_ISR_0_ISR31_ISR0_WOFFSET                  0x0
+#define ICTLR_ISR_0_ISR31_ISR0_DEFAULT                  _MK_MASK_CONST(0x0)
+#define ICTLR_ISR_0_ISR31_ISR0_DEFAULT_MASK                     _MK_MASK_CONST(0xffffffff)
+#define ICTLR_ISR_0_ISR31_ISR0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define ICTLR_ISR_0_ISR31_ISR0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register ICTLR_FIR_0  
+#define ICTLR_FIR_0                     _MK_ADDR_CONST(0x14)
+#define ICTLR_FIR_0_WORD_COUNT                  0x1
+#define ICTLR_FIR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define ICTLR_FIR_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define ICTLR_FIR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define ICTLR_FIR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define ICTLR_FIR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define ICTLR_FIR_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+// Read only: Set during write to FIR_SET, cleared  during write to FIR_CLR.
+#define ICTLR_FIR_0_FIR31_FIR0_SHIFT                    _MK_SHIFT_CONST(0)
+#define ICTLR_FIR_0_FIR31_FIR0_FIELD                    (_MK_MASK_CONST(0xffffffff) << ICTLR_FIR_0_FIR31_FIR0_SHIFT)
+#define ICTLR_FIR_0_FIR31_FIR0_RANGE                    31:0
+#define ICTLR_FIR_0_FIR31_FIR0_WOFFSET                  0x0
+#define ICTLR_FIR_0_FIR31_FIR0_DEFAULT                  _MK_MASK_CONST(0x0)
+#define ICTLR_FIR_0_FIR31_FIR0_DEFAULT_MASK                     _MK_MASK_CONST(0xffffffff)
+#define ICTLR_FIR_0_FIR31_FIR0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define ICTLR_FIR_0_FIR31_FIR0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register ICTLR_FIR_SET_0  
+#define ICTLR_FIR_SET_0                 _MK_ADDR_CONST(0x18)
+#define ICTLR_FIR_SET_0_WORD_COUNT                      0x1
+#define ICTLR_FIR_SET_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define ICTLR_FIR_SET_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define ICTLR_FIR_SET_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define ICTLR_FIR_SET_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define ICTLR_FIR_SET_0_READ_MASK                       _MK_MASK_CONST(0x0)
+#define ICTLR_FIR_SET_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Set Forced Interrupt Bit. Writing a 1 will set an  interrupt
+#define ICTLR_FIR_SET_0_FIR_SET_SHIFT                   _MK_SHIFT_CONST(0)
+#define ICTLR_FIR_SET_0_FIR_SET_FIELD                   (_MK_MASK_CONST(0xffffffff) << ICTLR_FIR_SET_0_FIR_SET_SHIFT)
+#define ICTLR_FIR_SET_0_FIR_SET_RANGE                   31:0
+#define ICTLR_FIR_SET_0_FIR_SET_WOFFSET                 0x0
+#define ICTLR_FIR_SET_0_FIR_SET_DEFAULT                 _MK_MASK_CONST(0x0)
+#define ICTLR_FIR_SET_0_FIR_SET_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
+#define ICTLR_FIR_SET_0_FIR_SET_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define ICTLR_FIR_SET_0_FIR_SET_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register ICTLR_FIR_CLR_0  
+#define ICTLR_FIR_CLR_0                 _MK_ADDR_CONST(0x1c)
+#define ICTLR_FIR_CLR_0_WORD_COUNT                      0x1
+#define ICTLR_FIR_CLR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define ICTLR_FIR_CLR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define ICTLR_FIR_CLR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define ICTLR_FIR_CLR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define ICTLR_FIR_CLR_0_READ_MASK                       _MK_MASK_CONST(0x0)
+#define ICTLR_FIR_CLR_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Clear Forced Interrupt Bit: Writing a 1 will clear  the forced interrupt
+#define ICTLR_FIR_CLR_0_FIR_CLR_SHIFT                   _MK_SHIFT_CONST(0)
+#define ICTLR_FIR_CLR_0_FIR_CLR_FIELD                   (_MK_MASK_CONST(0xffffffff) << ICTLR_FIR_CLR_0_FIR_CLR_SHIFT)
+#define ICTLR_FIR_CLR_0_FIR_CLR_RANGE                   31:0
+#define ICTLR_FIR_CLR_0_FIR_CLR_WOFFSET                 0x0
+#define ICTLR_FIR_CLR_0_FIR_CLR_DEFAULT                 _MK_MASK_CONST(0x0)
+#define ICTLR_FIR_CLR_0_FIR_CLR_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
+#define ICTLR_FIR_CLR_0_FIR_CLR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define ICTLR_FIR_CLR_0_FIR_CLR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register ICTLR_CPU_IER_0  
+#define ICTLR_CPU_IER_0                 _MK_ADDR_CONST(0x20)
+#define ICTLR_CPU_IER_0_WORD_COUNT                      0x1
+#define ICTLR_CPU_IER_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define ICTLR_CPU_IER_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define ICTLR_CPU_IER_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define ICTLR_CPU_IER_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define ICTLR_CPU_IER_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define ICTLR_CPU_IER_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
+//  Interrupt Enable Status. 0 = Disabled
+#define ICTLR_CPU_IER_0_IER31_IER0_SHIFT                        _MK_SHIFT_CONST(0)
+#define ICTLR_CPU_IER_0_IER31_IER0_FIELD                        (_MK_MASK_CONST(0xffffffff) << ICTLR_CPU_IER_0_IER31_IER0_SHIFT)
+#define ICTLR_CPU_IER_0_IER31_IER0_RANGE                        31:0
+#define ICTLR_CPU_IER_0_IER31_IER0_WOFFSET                      0x0
+#define ICTLR_CPU_IER_0_IER31_IER0_DEFAULT                      _MK_MASK_CONST(0x0)
+#define ICTLR_CPU_IER_0_IER31_IER0_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
+#define ICTLR_CPU_IER_0_IER31_IER0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define ICTLR_CPU_IER_0_IER31_IER0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register ICTLR_CPU_IER_SET_0  
+#define ICTLR_CPU_IER_SET_0                     _MK_ADDR_CONST(0x24)
+#define ICTLR_CPU_IER_SET_0_WORD_COUNT                  0x1
+#define ICTLR_CPU_IER_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define ICTLR_CPU_IER_SET_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define ICTLR_CPU_IER_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define ICTLR_CPU_IER_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define ICTLR_CPU_IER_SET_0_READ_MASK                   _MK_MASK_CONST(0x0)
+#define ICTLR_CPU_IER_SET_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+// Writing a 1 in any bit position will enable the  corresponding Interrupt Source for CPU 
+#define ICTLR_CPU_IER_SET_0_CPU_IER_SET_SHIFT                   _MK_SHIFT_CONST(0)
+#define ICTLR_CPU_IER_SET_0_CPU_IER_SET_FIELD                   (_MK_MASK_CONST(0xffffffff) << ICTLR_CPU_IER_SET_0_CPU_IER_SET_SHIFT)
+#define ICTLR_CPU_IER_SET_0_CPU_IER_SET_RANGE                   31:0
+#define ICTLR_CPU_IER_SET_0_CPU_IER_SET_WOFFSET                 0x0
+#define ICTLR_CPU_IER_SET_0_CPU_IER_SET_DEFAULT                 _MK_MASK_CONST(0x0)
+#define ICTLR_CPU_IER_SET_0_CPU_IER_SET_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
+#define ICTLR_CPU_IER_SET_0_CPU_IER_SET_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define ICTLR_CPU_IER_SET_0_CPU_IER_SET_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register ICTLR_CPU_IER_CLR_0  
+#define ICTLR_CPU_IER_CLR_0                     _MK_ADDR_CONST(0x28)
+#define ICTLR_CPU_IER_CLR_0_WORD_COUNT                  0x1
+#define ICTLR_CPU_IER_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define ICTLR_CPU_IER_CLR_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define ICTLR_CPU_IER_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define ICTLR_CPU_IER_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define ICTLR_CPU_IER_CLR_0_READ_MASK                   _MK_MASK_CONST(0x0)
+#define ICTLR_CPU_IER_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+// Writing a 1 in any bit position will disable the  corresponding Interrupt Source for CPU 
+#define ICTLR_CPU_IER_CLR_0_CPU_IER_CLR_SHIFT                   _MK_SHIFT_CONST(0)
+#define ICTLR_CPU_IER_CLR_0_CPU_IER_CLR_FIELD                   (_MK_MASK_CONST(0xffffffff) << ICTLR_CPU_IER_CLR_0_CPU_IER_CLR_SHIFT)
+#define ICTLR_CPU_IER_CLR_0_CPU_IER_CLR_RANGE                   31:0
+#define ICTLR_CPU_IER_CLR_0_CPU_IER_CLR_WOFFSET                 0x0
+#define ICTLR_CPU_IER_CLR_0_CPU_IER_CLR_DEFAULT                 _MK_MASK_CONST(0x0)
+#define ICTLR_CPU_IER_CLR_0_CPU_IER_CLR_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
+#define ICTLR_CPU_IER_CLR_0_CPU_IER_CLR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define ICTLR_CPU_IER_CLR_0_CPU_IER_CLR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register ICTLR_CPU_IEP_CLASS_0  
+#define ICTLR_CPU_IEP_CLASS_0                   _MK_ADDR_CONST(0x2c)
+#define ICTLR_CPU_IEP_CLASS_0_WORD_COUNT                        0x1
+#define ICTLR_CPU_IEP_CLASS_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define ICTLR_CPU_IEP_CLASS_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
+#define ICTLR_CPU_IEP_CLASS_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define ICTLR_CPU_IEP_CLASS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define ICTLR_CPU_IEP_CLASS_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define ICTLR_CPU_IEP_CLASS_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
+//  Set Priority Interrupt Source For CPU. 1 = FIQ, 0 = IRQ.
+#define ICTLR_CPU_IEP_CLASS_0_CPU_IEP_CLASS_SHIFT                       _MK_SHIFT_CONST(0)
+#define ICTLR_CPU_IEP_CLASS_0_CPU_IEP_CLASS_FIELD                       (_MK_MASK_CONST(0xffffffff) << ICTLR_CPU_IEP_CLASS_0_CPU_IEP_CLASS_SHIFT)
+#define ICTLR_CPU_IEP_CLASS_0_CPU_IEP_CLASS_RANGE                       31:0
+#define ICTLR_CPU_IEP_CLASS_0_CPU_IEP_CLASS_WOFFSET                     0x0
+#define ICTLR_CPU_IEP_CLASS_0_CPU_IEP_CLASS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define ICTLR_CPU_IEP_CLASS_0_CPU_IEP_CLASS_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
+#define ICTLR_CPU_IEP_CLASS_0_CPU_IEP_CLASS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define ICTLR_CPU_IEP_CLASS_0_CPU_IEP_CLASS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register ICTLR_COP_IER_0  
+#define ICTLR_COP_IER_0                 _MK_ADDR_CONST(0x30)
+#define ICTLR_COP_IER_0_WORD_COUNT                      0x1
+#define ICTLR_COP_IER_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define ICTLR_COP_IER_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define ICTLR_COP_IER_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define ICTLR_COP_IER_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define ICTLR_COP_IER_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define ICTLR_COP_IER_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
+//  Interrupt Enable Status. 0 = Disabled.
+#define ICTLR_COP_IER_0_IER31_IER0_SHIFT                        _MK_SHIFT_CONST(0)
+#define ICTLR_COP_IER_0_IER31_IER0_FIELD                        (_MK_MASK_CONST(0xffffffff) << ICTLR_COP_IER_0_IER31_IER0_SHIFT)
+#define ICTLR_COP_IER_0_IER31_IER0_RANGE                        31:0
+#define ICTLR_COP_IER_0_IER31_IER0_WOFFSET                      0x0
+#define ICTLR_COP_IER_0_IER31_IER0_DEFAULT                      _MK_MASK_CONST(0x0)
+#define ICTLR_COP_IER_0_IER31_IER0_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
+#define ICTLR_COP_IER_0_IER31_IER0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define ICTLR_COP_IER_0_IER31_IER0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register ICTLR_COP_IER_SET_0  
+#define ICTLR_COP_IER_SET_0                     _MK_ADDR_CONST(0x34)
+#define ICTLR_COP_IER_SET_0_WORD_COUNT                  0x1
+#define ICTLR_COP_IER_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define ICTLR_COP_IER_SET_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define ICTLR_COP_IER_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define ICTLR_COP_IER_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define ICTLR_COP_IER_SET_0_READ_MASK                   _MK_MASK_CONST(0x0)
+#define ICTLR_COP_IER_SET_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+// Writing a 1 in any bit position will enable the  corresponding Interrupt Source for COP 
+#define ICTLR_COP_IER_SET_0_COP_IER_SET_SHIFT                   _MK_SHIFT_CONST(0)
+#define ICTLR_COP_IER_SET_0_COP_IER_SET_FIELD                   (_MK_MASK_CONST(0xffffffff) << ICTLR_COP_IER_SET_0_COP_IER_SET_SHIFT)
+#define ICTLR_COP_IER_SET_0_COP_IER_SET_RANGE                   31:0
+#define ICTLR_COP_IER_SET_0_COP_IER_SET_WOFFSET                 0x0
+#define ICTLR_COP_IER_SET_0_COP_IER_SET_DEFAULT                 _MK_MASK_CONST(0x0)
+#define ICTLR_COP_IER_SET_0_COP_IER_SET_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
+#define ICTLR_COP_IER_SET_0_COP_IER_SET_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define ICTLR_COP_IER_SET_0_COP_IER_SET_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register ICTLR_COP_IER_CLR_0  
+#define ICTLR_COP_IER_CLR_0                     _MK_ADDR_CONST(0x38)
+#define ICTLR_COP_IER_CLR_0_WORD_COUNT                  0x1
+#define ICTLR_COP_IER_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define ICTLR_COP_IER_CLR_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define ICTLR_COP_IER_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define ICTLR_COP_IER_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define ICTLR_COP_IER_CLR_0_READ_MASK                   _MK_MASK_CONST(0x0)
+#define ICTLR_COP_IER_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+// Writing a 1 in any bit position will disable the  corresponding Interrupt Source for COP
+#define ICTLR_COP_IER_CLR_0_COP_IER_CLR_SHIFT                   _MK_SHIFT_CONST(0)
+#define ICTLR_COP_IER_CLR_0_COP_IER_CLR_FIELD                   (_MK_MASK_CONST(0xffffffff) << ICTLR_COP_IER_CLR_0_COP_IER_CLR_SHIFT)
+#define ICTLR_COP_IER_CLR_0_COP_IER_CLR_RANGE                   31:0
+#define ICTLR_COP_IER_CLR_0_COP_IER_CLR_WOFFSET                 0x0
+#define ICTLR_COP_IER_CLR_0_COP_IER_CLR_DEFAULT                 _MK_MASK_CONST(0x0)
+#define ICTLR_COP_IER_CLR_0_COP_IER_CLR_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
+#define ICTLR_COP_IER_CLR_0_COP_IER_CLR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define ICTLR_COP_IER_CLR_0_COP_IER_CLR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register ICTLR_COP_IEP_CLASS_0  
+#define ICTLR_COP_IEP_CLASS_0                   _MK_ADDR_CONST(0x3c)
+#define ICTLR_COP_IEP_CLASS_0_WORD_COUNT                        0x1
+#define ICTLR_COP_IEP_CLASS_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define ICTLR_COP_IEP_CLASS_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
+#define ICTLR_COP_IEP_CLASS_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define ICTLR_COP_IEP_CLASS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define ICTLR_COP_IEP_CLASS_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define ICTLR_COP_IEP_CLASS_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
+//  Set Priority Interrupt Source For COP. 1 = FIQ, 0 = IRQ.
+#define ICTLR_COP_IEP_CLASS_0_COP_IEP_CLASS_SHIFT                       _MK_SHIFT_CONST(0)
+#define ICTLR_COP_IEP_CLASS_0_COP_IEP_CLASS_FIELD                       (_MK_MASK_CONST(0xffffffff) << ICTLR_COP_IEP_CLASS_0_COP_IEP_CLASS_SHIFT)
+#define ICTLR_COP_IEP_CLASS_0_COP_IEP_CLASS_RANGE                       31:0
+#define ICTLR_COP_IEP_CLASS_0_COP_IEP_CLASS_WOFFSET                     0x0
+#define ICTLR_COP_IEP_CLASS_0_COP_IEP_CLASS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define ICTLR_COP_IEP_CLASS_0_COP_IEP_CLASS_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
+#define ICTLR_COP_IEP_CLASS_0_COP_IEP_CLASS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define ICTLR_COP_IEP_CLASS_0_COP_IEP_CLASS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+//
+// REGISTER LIST
+//
+#define LIST_ARICTLR_REGS(_op_) \
+_op_(ICTLR_VIRQ_CPU_0) \
+_op_(ICTLR_VIRQ_COP_0) \
+_op_(ICTLR_VFIQ_CPU_0) \
+_op_(ICTLR_VFIQ_COP_0) \
+_op_(ICTLR_ISR_0) \
+_op_(ICTLR_FIR_0) \
+_op_(ICTLR_FIR_SET_0) \
+_op_(ICTLR_FIR_CLR_0) \
+_op_(ICTLR_CPU_IER_0) \
+_op_(ICTLR_CPU_IER_SET_0) \
+_op_(ICTLR_CPU_IER_CLR_0) \
+_op_(ICTLR_CPU_IEP_CLASS_0) \
+_op_(ICTLR_COP_IER_0) \
+_op_(ICTLR_COP_IER_SET_0) \
+_op_(ICTLR_COP_IER_CLR_0) \
+_op_(ICTLR_COP_IEP_CLASS_0)
+
+
+//
+// ADDRESS SPACES
+//
+
+#define BASE_ADDRESS_ICTLR      0x00000000
+
+//
+// ARICTLR REGISTER BANKS
+//
+
+#define ICTLR0_FIRST_REG 0x0000 // ICTLR_VIRQ_CPU_0
+#define ICTLR0_LAST_REG 0x003c // ICTLR_COP_IEP_CLASS_0
+
+#ifndef _MK_SHIFT_CONST
+  #define _MK_SHIFT_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_MASK_CONST
+  #define _MK_MASK_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_ENUM_CONST
+  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
+#endif
+#ifndef _MK_ADDR_CONST
+  #define _MK_ADDR_CONST(_constant_) _constant_
+#endif
+
+#endif // ifndef ___ARICTLR_H_INC_
diff --git a/arch/arm/mach-tegra/include/ap15/arictlr_arbgnt.h b/arch/arm/mach-tegra/include/ap15/arictlr_arbgnt.h
new file mode 100644
index 000000000000..2d9790b7cc58
--- /dev/null
+++ b/arch/arm/mach-tegra/include/ap15/arictlr_arbgnt.h
@@ -0,0 +1,183 @@
+/*
+ * Copyright (c) 2010 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+//
+// DO NOT EDIT - generated by simspec!
+//
+
+#ifndef ___ARICTLR_ARBGNT_H_INC_
+#define ___ARICTLR_ARBGNT_H_INC_
+//
+// this spec file is for sw header generation
+//
+// hw should use headers generated from:
+//     arintr_ctlr.spec
+//
+//
+// arb_gnt specific interrupt controller registers
+//
+// Arbitration semaphores provide a mechanism by which the two processors can arbitrate
+// for the use of various resources. These semaphores provide a hardware locking mechanism,
+// so that when a processor is already using a resource, the second processor is not 
+// granted that resource. There are 32 bits of Arbitration semaphores provided in the system.
+// The hardware does not enforce any resource association to these bits. It is left to the
+// firmware to assign and use these bits.
+// The setup/usage of the Arbitration Semaphores is described in the ararb_sema specfile.
+//
+// The Arbitration Semaphores can also generate an interrupt when a hardware resource 
+// becomes available.  The registers in this module configure these interrupts.
+// When a 1 is set in the corresponding bit position of the Arbitration Semaphore Interrupt 
+// Source Register (CPU_enable or COP_enable), an interrupt will be generated when the 
+// processor achieves Grant Status for that resource.
+// The current Grant status can be viewed in the CPU_STATUS or COP_STATUS registers.
+//
+// CPU Arbitration Semaphore Interrupt Status Register
+
+// Register ARBGNT_CPU_STATUS_0  
+#define ARBGNT_CPU_STATUS_0                     _MK_ADDR_CONST(0x0)
+#define ARBGNT_CPU_STATUS_0_WORD_COUNT                  0x1
+#define ARBGNT_CPU_STATUS_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define ARBGNT_CPU_STATUS_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define ARBGNT_CPU_STATUS_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define ARBGNT_CPU_STATUS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define ARBGNT_CPU_STATUS_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define ARBGNT_CPU_STATUS_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+// Each bit is set by hardware when the corresponding  arbitration semaphore ownership is granted to CPU. Interrupt is cleared when  the CPU writes the ARB_SMP.PUT register with the corresponding bit set.
+#define ARBGNT_CPU_STATUS_0_GNT31_GNG0_SHIFT                    _MK_SHIFT_CONST(0)
+#define ARBGNT_CPU_STATUS_0_GNT31_GNG0_FIELD                    (_MK_MASK_CONST(0xffffffff) << ARBGNT_CPU_STATUS_0_GNT31_GNG0_SHIFT)
+#define ARBGNT_CPU_STATUS_0_GNT31_GNG0_RANGE                    31:0
+#define ARBGNT_CPU_STATUS_0_GNT31_GNG0_WOFFSET                  0x0
+#define ARBGNT_CPU_STATUS_0_GNT31_GNG0_DEFAULT                  _MK_MASK_CONST(0x0)
+#define ARBGNT_CPU_STATUS_0_GNT31_GNG0_DEFAULT_MASK                     _MK_MASK_CONST(0xffffffff)
+#define ARBGNT_CPU_STATUS_0_GNT31_GNG0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define ARBGNT_CPU_STATUS_0_GNT31_GNG0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// CPU Arbitration Semaphore Interrupt Enable Register
+
+// Register ARBGNT_CPU_ENABLE_0  
+#define ARBGNT_CPU_ENABLE_0                     _MK_ADDR_CONST(0x4)
+#define ARBGNT_CPU_ENABLE_0_WORD_COUNT                  0x1
+#define ARBGNT_CPU_ENABLE_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define ARBGNT_CPU_ENABLE_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define ARBGNT_CPU_ENABLE_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define ARBGNT_CPU_ENABLE_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define ARBGNT_CPU_ENABLE_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define ARBGNT_CPU_ENABLE_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+// Writing a 1 in any bit position will enable the  corresponding arbitration semaphore interrupt.
+#define ARBGNT_CPU_ENABLE_0_GER31_GER0_SHIFT                    _MK_SHIFT_CONST(0)
+#define ARBGNT_CPU_ENABLE_0_GER31_GER0_FIELD                    (_MK_MASK_CONST(0xffffffff) << ARBGNT_CPU_ENABLE_0_GER31_GER0_SHIFT)
+#define ARBGNT_CPU_ENABLE_0_GER31_GER0_RANGE                    31:0
+#define ARBGNT_CPU_ENABLE_0_GER31_GER0_WOFFSET                  0x0
+#define ARBGNT_CPU_ENABLE_0_GER31_GER0_DEFAULT                  _MK_MASK_CONST(0x0)
+#define ARBGNT_CPU_ENABLE_0_GER31_GER0_DEFAULT_MASK                     _MK_MASK_CONST(0xffffffff)
+#define ARBGNT_CPU_ENABLE_0_GER31_GER0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define ARBGNT_CPU_ENABLE_0_GER31_GER0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// COP Arbitration Semaphore Interrupt Status Register
+
+// Register ARBGNT_COP_STATUS_0  
+#define ARBGNT_COP_STATUS_0                     _MK_ADDR_CONST(0x8)
+#define ARBGNT_COP_STATUS_0_WORD_COUNT                  0x1
+#define ARBGNT_COP_STATUS_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define ARBGNT_COP_STATUS_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define ARBGNT_COP_STATUS_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define ARBGNT_COP_STATUS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define ARBGNT_COP_STATUS_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define ARBGNT_COP_STATUS_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+// Each bit is set by hardware when the corresponding  arbitration semaphore ownership is granted to COP. Interrupt is cleared when  the COP writes the ARB_SMP.PUT register with the corresponding bit set.
+#define ARBGNT_COP_STATUS_0_GNT31_GNG0_SHIFT                    _MK_SHIFT_CONST(0)
+#define ARBGNT_COP_STATUS_0_GNT31_GNG0_FIELD                    (_MK_MASK_CONST(0xffffffff) << ARBGNT_COP_STATUS_0_GNT31_GNG0_SHIFT)
+#define ARBGNT_COP_STATUS_0_GNT31_GNG0_RANGE                    31:0
+#define ARBGNT_COP_STATUS_0_GNT31_GNG0_WOFFSET                  0x0
+#define ARBGNT_COP_STATUS_0_GNT31_GNG0_DEFAULT                  _MK_MASK_CONST(0x0)
+#define ARBGNT_COP_STATUS_0_GNT31_GNG0_DEFAULT_MASK                     _MK_MASK_CONST(0xffffffff)
+#define ARBGNT_COP_STATUS_0_GNT31_GNG0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define ARBGNT_COP_STATUS_0_GNT31_GNG0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// COP Arbitration Semaphore Interrupt Enable Register
+
+// Register ARBGNT_COP_ENABLE_0  
+#define ARBGNT_COP_ENABLE_0                     _MK_ADDR_CONST(0xc)
+#define ARBGNT_COP_ENABLE_0_WORD_COUNT                  0x1
+#define ARBGNT_COP_ENABLE_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define ARBGNT_COP_ENABLE_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define ARBGNT_COP_ENABLE_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define ARBGNT_COP_ENABLE_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define ARBGNT_COP_ENABLE_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define ARBGNT_COP_ENABLE_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+// Writing a 1 in any bit position will enable the  corresponding arbitration semaphore interrupt. 
+#define ARBGNT_COP_ENABLE_0_GER31_GER0_SHIFT                    _MK_SHIFT_CONST(0)
+#define ARBGNT_COP_ENABLE_0_GER31_GER0_FIELD                    (_MK_MASK_CONST(0xffffffff) << ARBGNT_COP_ENABLE_0_GER31_GER0_SHIFT)
+#define ARBGNT_COP_ENABLE_0_GER31_GER0_RANGE                    31:0
+#define ARBGNT_COP_ENABLE_0_GER31_GER0_WOFFSET                  0x0
+#define ARBGNT_COP_ENABLE_0_GER31_GER0_DEFAULT                  _MK_MASK_CONST(0x0)
+#define ARBGNT_COP_ENABLE_0_GER31_GER0_DEFAULT_MASK                     _MK_MASK_CONST(0xffffffff)
+#define ARBGNT_COP_ENABLE_0_GER31_GER0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define ARBGNT_COP_ENABLE_0_GER31_GER0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+//
+// REGISTER LIST
+//
+#define LIST_ARICTLR_ARBGNT_REGS(_op_) \
+_op_(ARBGNT_CPU_STATUS_0) \
+_op_(ARBGNT_CPU_ENABLE_0) \
+_op_(ARBGNT_COP_STATUS_0) \
+_op_(ARBGNT_COP_ENABLE_0)
+
+
+//
+// ADDRESS SPACES
+//
+
+#define BASE_ADDRESS_ARBGNT     0x00000000
+
+//
+// ARICTLR_ARBGNT REGISTER BANKS
+//
+
+#define ARBGNT0_FIRST_REG 0x0000 // ARBGNT_CPU_STATUS_0
+#define ARBGNT0_LAST_REG 0x000c // ARBGNT_COP_ENABLE_0
+
+#ifndef _MK_SHIFT_CONST
+  #define _MK_SHIFT_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_MASK_CONST
+  #define _MK_MASK_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_ENUM_CONST
+  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
+#endif
+#ifndef _MK_ADDR_CONST
+  #define _MK_ADDR_CONST(_constant_) _constant_
+#endif
+
+#endif // ifndef ___ARICTLR_ARBGNT_H_INC_
diff --git a/arch/arm/mach-tegra/include/ap15/armc.h b/arch/arm/mach-tegra/include/ap15/armc.h
new file mode 100644
index 000000000000..f831cef1d6cb
--- /dev/null
+++ b/arch/arm/mach-tegra/include/ap15/armc.h
@@ -0,0 +1,9593 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+//
+// DO NOT EDIT - generated by simspec!
+//
+
+#ifndef ___ARMC_H_INC_
+#define ___ARMC_H_INC_
+
+// Register MC_INTSTATUS_0  
+#define MC_INTSTATUS_0                  _MK_ADDR_CONST(0x0)
+#define MC_INTSTATUS_0_WORD_COUNT                       0x1
+#define MC_INTSTATUS_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define MC_INTSTATUS_0_RESET_MASK                       _MK_MASK_CONST(0xc8)
+#define MC_INTSTATUS_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define MC_INTSTATUS_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_INTSTATUS_0_READ_MASK                        _MK_MASK_CONST(0xc8)
+#define MC_INTSTATUS_0_WRITE_MASK                       _MK_MASK_CONST(0xc8)
+// Address decode error for AXI client.
+#define MC_INTSTATUS_0_DECERR_AXI_INT_SHIFT                     _MK_SHIFT_CONST(3)
+#define MC_INTSTATUS_0_DECERR_AXI_INT_FIELD                     (_MK_MASK_CONST(0x1) << MC_INTSTATUS_0_DECERR_AXI_INT_SHIFT)
+#define MC_INTSTATUS_0_DECERR_AXI_INT_RANGE                     3:3
+#define MC_INTSTATUS_0_DECERR_AXI_INT_WOFFSET                   0x0
+#define MC_INTSTATUS_0_DECERR_AXI_INT_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_INTSTATUS_0_DECERR_AXI_INT_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define MC_INTSTATUS_0_DECERR_AXI_INT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_INTSTATUS_0_DECERR_AXI_INT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_INTSTATUS_0_DECERR_AXI_INT_INIT_ENUM                 CLEAR
+#define MC_INTSTATUS_0_DECERR_AXI_INT_CLEAR                     _MK_ENUM_CONST(0)
+#define MC_INTSTATUS_0_DECERR_AXI_INT_SET                       _MK_ENUM_CONST(1)
+
+// EMEM Address Decode Error for a non AXI client.
+#define MC_INTSTATUS_0_DECERR_EMEM_OTHERS_INT_SHIFT                     _MK_SHIFT_CONST(6)
+#define MC_INTSTATUS_0_DECERR_EMEM_OTHERS_INT_FIELD                     (_MK_MASK_CONST(0x1) << MC_INTSTATUS_0_DECERR_EMEM_OTHERS_INT_SHIFT)
+#define MC_INTSTATUS_0_DECERR_EMEM_OTHERS_INT_RANGE                     6:6
+#define MC_INTSTATUS_0_DECERR_EMEM_OTHERS_INT_WOFFSET                   0x0
+#define MC_INTSTATUS_0_DECERR_EMEM_OTHERS_INT_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_INTSTATUS_0_DECERR_EMEM_OTHERS_INT_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define MC_INTSTATUS_0_DECERR_EMEM_OTHERS_INT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_INTSTATUS_0_DECERR_EMEM_OTHERS_INT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_INTSTATUS_0_DECERR_EMEM_OTHERS_INT_INIT_ENUM                 CLEAR
+#define MC_INTSTATUS_0_DECERR_EMEM_OTHERS_INT_CLEAR                     _MK_ENUM_CONST(0)
+#define MC_INTSTATUS_0_DECERR_EMEM_OTHERS_INT_SET                       _MK_ENUM_CONST(1)
+
+// A GART access was attepted to an invalid page.
+#define MC_INTSTATUS_0_INVALID_GART_PAGE_INT_SHIFT                      _MK_SHIFT_CONST(7)
+#define MC_INTSTATUS_0_INVALID_GART_PAGE_INT_FIELD                      (_MK_MASK_CONST(0x1) << MC_INTSTATUS_0_INVALID_GART_PAGE_INT_SHIFT)
+#define MC_INTSTATUS_0_INVALID_GART_PAGE_INT_RANGE                      7:7
+#define MC_INTSTATUS_0_INVALID_GART_PAGE_INT_WOFFSET                    0x0
+#define MC_INTSTATUS_0_INVALID_GART_PAGE_INT_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_INTSTATUS_0_INVALID_GART_PAGE_INT_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_INTSTATUS_0_INVALID_GART_PAGE_INT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_INTSTATUS_0_INVALID_GART_PAGE_INT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_INTSTATUS_0_INVALID_GART_PAGE_INT_INIT_ENUM                  CLEAR
+#define MC_INTSTATUS_0_INVALID_GART_PAGE_INT_CLEAR                      _MK_ENUM_CONST(0)
+#define MC_INTSTATUS_0_INVALID_GART_PAGE_INT_SET                        _MK_ENUM_CONST(1)
+
+
+// Register MC_INTMASK_0  
+#define MC_INTMASK_0                    _MK_ADDR_CONST(0x4)
+#define MC_INTMASK_0_WORD_COUNT                         0x1
+#define MC_INTMASK_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define MC_INTMASK_0_RESET_MASK                         _MK_MASK_CONST(0xc8)
+#define MC_INTMASK_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define MC_INTMASK_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_INTMASK_0_READ_MASK                  _MK_MASK_CONST(0xc8)
+#define MC_INTMASK_0_WRITE_MASK                         _MK_MASK_CONST(0xc8)
+// Address decode error from an AXI client
+#define MC_INTMASK_0_DECERR_AXI_INTMASK_SHIFT                   _MK_SHIFT_CONST(3)
+#define MC_INTMASK_0_DECERR_AXI_INTMASK_FIELD                   (_MK_MASK_CONST(0x1) << MC_INTMASK_0_DECERR_AXI_INTMASK_SHIFT)
+#define MC_INTMASK_0_DECERR_AXI_INTMASK_RANGE                   3:3
+#define MC_INTMASK_0_DECERR_AXI_INTMASK_WOFFSET                 0x0
+#define MC_INTMASK_0_DECERR_AXI_INTMASK_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_INTMASK_0_DECERR_AXI_INTMASK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define MC_INTMASK_0_DECERR_AXI_INTMASK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_INTMASK_0_DECERR_AXI_INTMASK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_INTMASK_0_DECERR_AXI_INTMASK_INIT_ENUM                       MASKED
+#define MC_INTMASK_0_DECERR_AXI_INTMASK_MASKED                  _MK_ENUM_CONST(0)
+#define MC_INTMASK_0_DECERR_AXI_INTMASK_UNMASKED                        _MK_ENUM_CONST(1)
+
+// EMEM Address Decode Error for a non AXI client.
+#define MC_INTMASK_0_DECERR_EMEM_OTHERS_INTMASK_SHIFT                   _MK_SHIFT_CONST(6)
+#define MC_INTMASK_0_DECERR_EMEM_OTHERS_INTMASK_FIELD                   (_MK_MASK_CONST(0x1) << MC_INTMASK_0_DECERR_EMEM_OTHERS_INTMASK_SHIFT)
+#define MC_INTMASK_0_DECERR_EMEM_OTHERS_INTMASK_RANGE                   6:6
+#define MC_INTMASK_0_DECERR_EMEM_OTHERS_INTMASK_WOFFSET                 0x0
+#define MC_INTMASK_0_DECERR_EMEM_OTHERS_INTMASK_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_INTMASK_0_DECERR_EMEM_OTHERS_INTMASK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define MC_INTMASK_0_DECERR_EMEM_OTHERS_INTMASK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_INTMASK_0_DECERR_EMEM_OTHERS_INTMASK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_INTMASK_0_DECERR_EMEM_OTHERS_INTMASK_INIT_ENUM                       MASKED
+#define MC_INTMASK_0_DECERR_EMEM_OTHERS_INTMASK_MASKED                  _MK_ENUM_CONST(0)
+#define MC_INTMASK_0_DECERR_EMEM_OTHERS_INTMASK_UNMASKED                        _MK_ENUM_CONST(1)
+
+// A GART access was attepted to an invalid page.
+#define MC_INTMASK_0_INVALID_GART_PAGE_INTMASK_SHIFT                    _MK_SHIFT_CONST(7)
+#define MC_INTMASK_0_INVALID_GART_PAGE_INTMASK_FIELD                    (_MK_MASK_CONST(0x1) << MC_INTMASK_0_INVALID_GART_PAGE_INTMASK_SHIFT)
+#define MC_INTMASK_0_INVALID_GART_PAGE_INTMASK_RANGE                    7:7
+#define MC_INTMASK_0_INVALID_GART_PAGE_INTMASK_WOFFSET                  0x0
+#define MC_INTMASK_0_INVALID_GART_PAGE_INTMASK_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_INTMASK_0_INVALID_GART_PAGE_INTMASK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_INTMASK_0_INVALID_GART_PAGE_INTMASK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_INTMASK_0_INVALID_GART_PAGE_INTMASK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_INTMASK_0_INVALID_GART_PAGE_INTMASK_INIT_ENUM                        MASKED
+#define MC_INTMASK_0_INVALID_GART_PAGE_INTMASK_MASKED                   _MK_ENUM_CONST(0)
+#define MC_INTMASK_0_INVALID_GART_PAGE_INTMASK_UNMASKED                 _MK_ENUM_CONST(1)
+
+
+// Reserved address 8 [0x8] 
+
+// Register MC_EMEM_CFG_0  
+#define MC_EMEM_CFG_0                   _MK_ADDR_CONST(0xc)
+#define MC_EMEM_CFG_0_WORD_COUNT                        0x1
+#define MC_EMEM_CFG_0_RESET_VAL                         _MK_MASK_CONST(0x10000)
+#define MC_EMEM_CFG_0_RESET_MASK                        _MK_MASK_CONST(0x3fffff)
+#define MC_EMEM_CFG_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define MC_EMEM_CFG_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_EMEM_CFG_0_READ_MASK                         _MK_MASK_CONST(0x3fffff)
+#define MC_EMEM_CFG_0_WRITE_MASK                        _MK_MASK_CONST(0x3fffff)
+#define MC_EMEM_CFG_0_EMEM_SIZE_KB_SHIFT                        _MK_SHIFT_CONST(0)
+#define MC_EMEM_CFG_0_EMEM_SIZE_KB_FIELD                        (_MK_MASK_CONST(0x3fffff) << MC_EMEM_CFG_0_EMEM_SIZE_KB_SHIFT)
+#define MC_EMEM_CFG_0_EMEM_SIZE_KB_RANGE                        21:0
+#define MC_EMEM_CFG_0_EMEM_SIZE_KB_WOFFSET                      0x0
+#define MC_EMEM_CFG_0_EMEM_SIZE_KB_DEFAULT                      _MK_MASK_CONST(0x10000)
+#define MC_EMEM_CFG_0_EMEM_SIZE_KB_DEFAULT_MASK                 _MK_MASK_CONST(0x3fffff)
+#define MC_EMEM_CFG_0_EMEM_SIZE_KB_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_EMEM_CFG_0_EMEM_SIZE_KB_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register MC_EMEM_ADR_CFG_0  
+#define MC_EMEM_ADR_CFG_0                       _MK_ADDR_CONST(0x10)
+#define MC_EMEM_ADR_CFG_0_WORD_COUNT                    0x1
+#define MC_EMEM_ADR_CFG_0_RESET_VAL                     _MK_MASK_CONST(0x40202)
+#define MC_EMEM_ADR_CFG_0_RESET_MASK                    _MK_MASK_CONST(0x3070307)
+#define MC_EMEM_ADR_CFG_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define MC_EMEM_ADR_CFG_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_EMEM_ADR_CFG_0_READ_MASK                     _MK_MASK_CONST(0x3070307)
+#define MC_EMEM_ADR_CFG_0_WRITE_MASK                    _MK_MASK_CONST(0x3070307)
+#define MC_EMEM_ADR_CFG_0_EMEM_COLWIDTH_SHIFT                   _MK_SHIFT_CONST(0)
+#define MC_EMEM_ADR_CFG_0_EMEM_COLWIDTH_FIELD                   (_MK_MASK_CONST(0x7) << MC_EMEM_ADR_CFG_0_EMEM_COLWIDTH_SHIFT)
+#define MC_EMEM_ADR_CFG_0_EMEM_COLWIDTH_RANGE                   2:0
+#define MC_EMEM_ADR_CFG_0_EMEM_COLWIDTH_WOFFSET                 0x0
+#define MC_EMEM_ADR_CFG_0_EMEM_COLWIDTH_DEFAULT                 _MK_MASK_CONST(0x2)
+#define MC_EMEM_ADR_CFG_0_EMEM_COLWIDTH_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
+#define MC_EMEM_ADR_CFG_0_EMEM_COLWIDTH_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_EMEM_ADR_CFG_0_EMEM_COLWIDTH_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_EMEM_ADR_CFG_0_EMEM_COLWIDTH_INIT_ENUM                       W9
+#define MC_EMEM_ADR_CFG_0_EMEM_COLWIDTH_W7                      _MK_ENUM_CONST(0)
+#define MC_EMEM_ADR_CFG_0_EMEM_COLWIDTH_W8                      _MK_ENUM_CONST(1)
+#define MC_EMEM_ADR_CFG_0_EMEM_COLWIDTH_W9                      _MK_ENUM_CONST(2)
+#define MC_EMEM_ADR_CFG_0_EMEM_COLWIDTH_W10                     _MK_ENUM_CONST(3)
+#define MC_EMEM_ADR_CFG_0_EMEM_COLWIDTH_W11                     _MK_ENUM_CONST(4)
+
+#define MC_EMEM_ADR_CFG_0_EMEM_BANKWIDTH_SHIFT                  _MK_SHIFT_CONST(8)
+#define MC_EMEM_ADR_CFG_0_EMEM_BANKWIDTH_FIELD                  (_MK_MASK_CONST(0x3) << MC_EMEM_ADR_CFG_0_EMEM_BANKWIDTH_SHIFT)
+#define MC_EMEM_ADR_CFG_0_EMEM_BANKWIDTH_RANGE                  9:8
+#define MC_EMEM_ADR_CFG_0_EMEM_BANKWIDTH_WOFFSET                        0x0
+#define MC_EMEM_ADR_CFG_0_EMEM_BANKWIDTH_DEFAULT                        _MK_MASK_CONST(0x2)
+#define MC_EMEM_ADR_CFG_0_EMEM_BANKWIDTH_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define MC_EMEM_ADR_CFG_0_EMEM_BANKWIDTH_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_EMEM_ADR_CFG_0_EMEM_BANKWIDTH_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_EMEM_ADR_CFG_0_EMEM_BANKWIDTH_INIT_ENUM                      W2
+#define MC_EMEM_ADR_CFG_0_EMEM_BANKWIDTH_W1                     _MK_ENUM_CONST(1)
+#define MC_EMEM_ADR_CFG_0_EMEM_BANKWIDTH_W2                     _MK_ENUM_CONST(2)
+#define MC_EMEM_ADR_CFG_0_EMEM_BANKWIDTH_W3                     _MK_ENUM_CONST(3)
+
+#define MC_EMEM_ADR_CFG_0_EMEM_DEVSIZE_SHIFT                    _MK_SHIFT_CONST(16)
+#define MC_EMEM_ADR_CFG_0_EMEM_DEVSIZE_FIELD                    (_MK_MASK_CONST(0x7) << MC_EMEM_ADR_CFG_0_EMEM_DEVSIZE_SHIFT)
+#define MC_EMEM_ADR_CFG_0_EMEM_DEVSIZE_RANGE                    18:16
+#define MC_EMEM_ADR_CFG_0_EMEM_DEVSIZE_WOFFSET                  0x0
+#define MC_EMEM_ADR_CFG_0_EMEM_DEVSIZE_DEFAULT                  _MK_MASK_CONST(0x4)
+#define MC_EMEM_ADR_CFG_0_EMEM_DEVSIZE_DEFAULT_MASK                     _MK_MASK_CONST(0x7)
+#define MC_EMEM_ADR_CFG_0_EMEM_DEVSIZE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_EMEM_ADR_CFG_0_EMEM_DEVSIZE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_EMEM_ADR_CFG_0_EMEM_DEVSIZE_INIT_ENUM                        D64MB
+#define MC_EMEM_ADR_CFG_0_EMEM_DEVSIZE_D4MB                     _MK_ENUM_CONST(0)
+#define MC_EMEM_ADR_CFG_0_EMEM_DEVSIZE_D8MB                     _MK_ENUM_CONST(1)
+#define MC_EMEM_ADR_CFG_0_EMEM_DEVSIZE_D16MB                    _MK_ENUM_CONST(2)
+#define MC_EMEM_ADR_CFG_0_EMEM_DEVSIZE_D32MB                    _MK_ENUM_CONST(3)
+#define MC_EMEM_ADR_CFG_0_EMEM_DEVSIZE_D64MB                    _MK_ENUM_CONST(4)
+#define MC_EMEM_ADR_CFG_0_EMEM_DEVSIZE_D128MB                   _MK_ENUM_CONST(5)
+#define MC_EMEM_ADR_CFG_0_EMEM_DEVSIZE_D256MB                   _MK_ENUM_CONST(6)
+#define MC_EMEM_ADR_CFG_0_EMEM_DEVSIZE_D512MB                   _MK_ENUM_CONST(7)
+
+#define MC_EMEM_ADR_CFG_0_EMEM_NUMDEV_SHIFT                     _MK_SHIFT_CONST(24)
+#define MC_EMEM_ADR_CFG_0_EMEM_NUMDEV_FIELD                     (_MK_MASK_CONST(0x3) << MC_EMEM_ADR_CFG_0_EMEM_NUMDEV_SHIFT)
+#define MC_EMEM_ADR_CFG_0_EMEM_NUMDEV_RANGE                     25:24
+#define MC_EMEM_ADR_CFG_0_EMEM_NUMDEV_WOFFSET                   0x0
+#define MC_EMEM_ADR_CFG_0_EMEM_NUMDEV_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_EMEM_ADR_CFG_0_EMEM_NUMDEV_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define MC_EMEM_ADR_CFG_0_EMEM_NUMDEV_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_EMEM_ADR_CFG_0_EMEM_NUMDEV_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_EMEM_ADR_CFG_0_EMEM_NUMDEV_INIT_ENUM                 N1
+#define MC_EMEM_ADR_CFG_0_EMEM_NUMDEV_N1                        _MK_ENUM_CONST(0)
+#define MC_EMEM_ADR_CFG_0_EMEM_NUMDEV_N2                        _MK_ENUM_CONST(1)
+
+
+// Register MC_EMEM_ARB_CFG0_0  
+#define MC_EMEM_ARB_CFG0_0                      _MK_ADDR_CONST(0x14)
+#define MC_EMEM_ARB_CFG0_0_WORD_COUNT                   0x1
+#define MC_EMEM_ARB_CFG0_0_RESET_VAL                    _MK_MASK_CONST(0x48a1010)
+#define MC_EMEM_ARB_CFG0_0_RESET_MASK                   _MK_MASK_CONST(0x3fffffff)
+#define MC_EMEM_ARB_CFG0_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG0_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG0_0_READ_MASK                    _MK_MASK_CONST(0x3fffffff)
+#define MC_EMEM_ARB_CFG0_0_WRITE_MASK                   _MK_MASK_CONST(0x3fffffff)
+#define MC_EMEM_ARB_CFG0_0_EMEM_RWCNT_TH_SHIFT                  _MK_SHIFT_CONST(0)
+#define MC_EMEM_ARB_CFG0_0_EMEM_RWCNT_TH_FIELD                  (_MK_MASK_CONST(0xff) << MC_EMEM_ARB_CFG0_0_EMEM_RWCNT_TH_SHIFT)
+#define MC_EMEM_ARB_CFG0_0_EMEM_RWCNT_TH_RANGE                  7:0
+#define MC_EMEM_ARB_CFG0_0_EMEM_RWCNT_TH_WOFFSET                        0x0
+#define MC_EMEM_ARB_CFG0_0_EMEM_RWCNT_TH_DEFAULT                        _MK_MASK_CONST(0x10)
+#define MC_EMEM_ARB_CFG0_0_EMEM_RWCNT_TH_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
+#define MC_EMEM_ARB_CFG0_0_EMEM_RWCNT_TH_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG0_0_EMEM_RWCNT_TH_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define MC_EMEM_ARB_CFG0_0_EMEM_WRCNT_TH_SHIFT                  _MK_SHIFT_CONST(8)
+#define MC_EMEM_ARB_CFG0_0_EMEM_WRCNT_TH_FIELD                  (_MK_MASK_CONST(0xff) << MC_EMEM_ARB_CFG0_0_EMEM_WRCNT_TH_SHIFT)
+#define MC_EMEM_ARB_CFG0_0_EMEM_WRCNT_TH_RANGE                  15:8
+#define MC_EMEM_ARB_CFG0_0_EMEM_WRCNT_TH_WOFFSET                        0x0
+#define MC_EMEM_ARB_CFG0_0_EMEM_WRCNT_TH_DEFAULT                        _MK_MASK_CONST(0x10)
+#define MC_EMEM_ARB_CFG0_0_EMEM_WRCNT_TH_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
+#define MC_EMEM_ARB_CFG0_0_EMEM_WRCNT_TH_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG0_0_EMEM_WRCNT_TH_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define MC_EMEM_ARB_CFG0_0_EMEM_BANKCNT_TH_SHIFT                        _MK_SHIFT_CONST(16)
+#define MC_EMEM_ARB_CFG0_0_EMEM_BANKCNT_TH_FIELD                        (_MK_MASK_CONST(0x3f) << MC_EMEM_ARB_CFG0_0_EMEM_BANKCNT_TH_SHIFT)
+#define MC_EMEM_ARB_CFG0_0_EMEM_BANKCNT_TH_RANGE                        21:16
+#define MC_EMEM_ARB_CFG0_0_EMEM_BANKCNT_TH_WOFFSET                      0x0
+#define MC_EMEM_ARB_CFG0_0_EMEM_BANKCNT_TH_DEFAULT                      _MK_MASK_CONST(0xa)
+#define MC_EMEM_ARB_CFG0_0_EMEM_BANKCNT_TH_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
+#define MC_EMEM_ARB_CFG0_0_EMEM_BANKCNT_TH_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG0_0_EMEM_BANKCNT_TH_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define MC_EMEM_ARB_CFG0_0_EMEM_BANKCNT_NSP_TH_SHIFT                    _MK_SHIFT_CONST(22)
+#define MC_EMEM_ARB_CFG0_0_EMEM_BANKCNT_NSP_TH_FIELD                    (_MK_MASK_CONST(0x3f) << MC_EMEM_ARB_CFG0_0_EMEM_BANKCNT_NSP_TH_SHIFT)
+#define MC_EMEM_ARB_CFG0_0_EMEM_BANKCNT_NSP_TH_RANGE                    27:22
+#define MC_EMEM_ARB_CFG0_0_EMEM_BANKCNT_NSP_TH_WOFFSET                  0x0
+#define MC_EMEM_ARB_CFG0_0_EMEM_BANKCNT_NSP_TH_DEFAULT                  _MK_MASK_CONST(0x12)
+#define MC_EMEM_ARB_CFG0_0_EMEM_BANKCNT_NSP_TH_DEFAULT_MASK                     _MK_MASK_CONST(0x3f)
+#define MC_EMEM_ARB_CFG0_0_EMEM_BANKCNT_NSP_TH_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG0_0_EMEM_BANKCNT_NSP_TH_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define MC_EMEM_ARB_CFG0_0_EMEM_CLEAR_SP_ON_AUTOPC_SHIFT                        _MK_SHIFT_CONST(28)
+#define MC_EMEM_ARB_CFG0_0_EMEM_CLEAR_SP_ON_AUTOPC_FIELD                        (_MK_MASK_CONST(0x1) << MC_EMEM_ARB_CFG0_0_EMEM_CLEAR_SP_ON_AUTOPC_SHIFT)
+#define MC_EMEM_ARB_CFG0_0_EMEM_CLEAR_SP_ON_AUTOPC_RANGE                        28:28
+#define MC_EMEM_ARB_CFG0_0_EMEM_CLEAR_SP_ON_AUTOPC_WOFFSET                      0x0
+#define MC_EMEM_ARB_CFG0_0_EMEM_CLEAR_SP_ON_AUTOPC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG0_0_EMEM_CLEAR_SP_ON_AUTOPC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_EMEM_ARB_CFG0_0_EMEM_CLEAR_SP_ON_AUTOPC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG0_0_EMEM_CLEAR_SP_ON_AUTOPC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG0_0_EMEM_CLEAR_SP_ON_AUTOPC_INIT_ENUM                    DISABLE
+#define MC_EMEM_ARB_CFG0_0_EMEM_CLEAR_SP_ON_AUTOPC_DISABLE                      _MK_ENUM_CONST(0)
+#define MC_EMEM_ARB_CFG0_0_EMEM_CLEAR_SP_ON_AUTOPC_ENABLE                       _MK_ENUM_CONST(1)
+#define MC_EMEM_ARB_CFG0_0_EMEM_CLEAR_SP_ON_AUTOPC_DISABLED                     _MK_ENUM_CONST(0)
+#define MC_EMEM_ARB_CFG0_0_EMEM_CLEAR_SP_ON_AUTOPC_ENABLED                      _MK_ENUM_CONST(1)
+
+#define MC_EMEM_ARB_CFG0_0_EMEM_CLEAR_AP_PREV_SPREQ_SHIFT                       _MK_SHIFT_CONST(29)
+#define MC_EMEM_ARB_CFG0_0_EMEM_CLEAR_AP_PREV_SPREQ_FIELD                       (_MK_MASK_CONST(0x1) << MC_EMEM_ARB_CFG0_0_EMEM_CLEAR_AP_PREV_SPREQ_SHIFT)
+#define MC_EMEM_ARB_CFG0_0_EMEM_CLEAR_AP_PREV_SPREQ_RANGE                       29:29
+#define MC_EMEM_ARB_CFG0_0_EMEM_CLEAR_AP_PREV_SPREQ_WOFFSET                     0x0
+#define MC_EMEM_ARB_CFG0_0_EMEM_CLEAR_AP_PREV_SPREQ_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG0_0_EMEM_CLEAR_AP_PREV_SPREQ_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_EMEM_ARB_CFG0_0_EMEM_CLEAR_AP_PREV_SPREQ_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG0_0_EMEM_CLEAR_AP_PREV_SPREQ_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG0_0_EMEM_CLEAR_AP_PREV_SPREQ_INIT_ENUM                   DISABLE
+#define MC_EMEM_ARB_CFG0_0_EMEM_CLEAR_AP_PREV_SPREQ_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_EMEM_ARB_CFG0_0_EMEM_CLEAR_AP_PREV_SPREQ_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_EMEM_ARB_CFG0_0_EMEM_CLEAR_AP_PREV_SPREQ_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_EMEM_ARB_CFG0_0_EMEM_CLEAR_AP_PREV_SPREQ_ENABLED                     _MK_ENUM_CONST(1)
+
+#define NV_MC_ARB_EMEM_SPMSB    5
+
+// Register MC_EMEM_ARB_CFG1_0  
+#define MC_EMEM_ARB_CFG1_0                      _MK_ADDR_CONST(0x18)
+#define MC_EMEM_ARB_CFG1_0_WORD_COUNT                   0x1
+#define MC_EMEM_ARB_CFG1_0_RESET_VAL                    _MK_MASK_CONST(0x10cfff)
+#define MC_EMEM_ARB_CFG1_0_RESET_MASK                   _MK_MASK_CONST(0x3fffff)
+#define MC_EMEM_ARB_CFG1_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG1_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG1_0_READ_MASK                    _MK_MASK_CONST(0x3fffff)
+#define MC_EMEM_ARB_CFG1_0_WRITE_MASK                   _MK_MASK_CONST(0x3fffff)
+#define MC_EMEM_ARB_CFG1_0_EMEM_RCL_MASK_SHIFT                  _MK_SHIFT_CONST(0)
+#define MC_EMEM_ARB_CFG1_0_EMEM_RCL_MASK_FIELD                  (_MK_MASK_CONST(0x3f) << MC_EMEM_ARB_CFG1_0_EMEM_RCL_MASK_SHIFT)
+#define MC_EMEM_ARB_CFG1_0_EMEM_RCL_MASK_RANGE                  5:0
+#define MC_EMEM_ARB_CFG1_0_EMEM_RCL_MASK_WOFFSET                        0x0
+#define MC_EMEM_ARB_CFG1_0_EMEM_RCL_MASK_DEFAULT                        _MK_MASK_CONST(0x3f)
+#define MC_EMEM_ARB_CFG1_0_EMEM_RCL_MASK_DEFAULT_MASK                   _MK_MASK_CONST(0x3f)
+#define MC_EMEM_ARB_CFG1_0_EMEM_RCL_MASK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG1_0_EMEM_RCL_MASK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG1_0_EMEM_RCL_MASK_INIT_ENUM                      ALL
+#define MC_EMEM_ARB_CFG1_0_EMEM_RCL_MASK_NONE                   _MK_ENUM_CONST(0)
+#define MC_EMEM_ARB_CFG1_0_EMEM_RCL_MASK_ALL                    _MK_ENUM_CONST(63)
+
+#define MC_EMEM_ARB_CFG1_0_EMEM_WCL_MASK_SHIFT                  _MK_SHIFT_CONST(6)
+#define MC_EMEM_ARB_CFG1_0_EMEM_WCL_MASK_FIELD                  (_MK_MASK_CONST(0x3f) << MC_EMEM_ARB_CFG1_0_EMEM_WCL_MASK_SHIFT)
+#define MC_EMEM_ARB_CFG1_0_EMEM_WCL_MASK_RANGE                  11:6
+#define MC_EMEM_ARB_CFG1_0_EMEM_WCL_MASK_WOFFSET                        0x0
+#define MC_EMEM_ARB_CFG1_0_EMEM_WCL_MASK_DEFAULT                        _MK_MASK_CONST(0x3f)
+#define MC_EMEM_ARB_CFG1_0_EMEM_WCL_MASK_DEFAULT_MASK                   _MK_MASK_CONST(0x3f)
+#define MC_EMEM_ARB_CFG1_0_EMEM_WCL_MASK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG1_0_EMEM_WCL_MASK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG1_0_EMEM_WCL_MASK_INIT_ENUM                      ALL
+#define MC_EMEM_ARB_CFG1_0_EMEM_WCL_MASK_NONE                   _MK_ENUM_CONST(0)
+#define MC_EMEM_ARB_CFG1_0_EMEM_WCL_MASK_ALL                    _MK_ENUM_CONST(63)
+
+#define MC_EMEM_ARB_CFG1_0_EMEM_NORWSWITCH_BKBLOCK_SHIFT                        _MK_SHIFT_CONST(12)
+#define MC_EMEM_ARB_CFG1_0_EMEM_NORWSWITCH_BKBLOCK_FIELD                        (_MK_MASK_CONST(0x1) << MC_EMEM_ARB_CFG1_0_EMEM_NORWSWITCH_BKBLOCK_SHIFT)
+#define MC_EMEM_ARB_CFG1_0_EMEM_NORWSWITCH_BKBLOCK_RANGE                        12:12
+#define MC_EMEM_ARB_CFG1_0_EMEM_NORWSWITCH_BKBLOCK_WOFFSET                      0x0
+#define MC_EMEM_ARB_CFG1_0_EMEM_NORWSWITCH_BKBLOCK_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG1_0_EMEM_NORWSWITCH_BKBLOCK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_EMEM_ARB_CFG1_0_EMEM_NORWSWITCH_BKBLOCK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG1_0_EMEM_NORWSWITCH_BKBLOCK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG1_0_EMEM_NORWSWITCH_BKBLOCK_INIT_ENUM                    DISABLE
+#define MC_EMEM_ARB_CFG1_0_EMEM_NORWSWITCH_BKBLOCK_DISABLE                      _MK_ENUM_CONST(0)
+#define MC_EMEM_ARB_CFG1_0_EMEM_NORWSWITCH_BKBLOCK_ENABLE                       _MK_ENUM_CONST(1)
+#define MC_EMEM_ARB_CFG1_0_EMEM_NORWSWITCH_BKBLOCK_DISABLED                     _MK_ENUM_CONST(0)
+#define MC_EMEM_ARB_CFG1_0_EMEM_NORWSWITCH_BKBLOCK_ENABLED                      _MK_ENUM_CONST(1)
+
+#define MC_EMEM_ARB_CFG1_0_EMEM_NOWRSWITCH_BKBLOCK_SHIFT                        _MK_SHIFT_CONST(13)
+#define MC_EMEM_ARB_CFG1_0_EMEM_NOWRSWITCH_BKBLOCK_FIELD                        (_MK_MASK_CONST(0x1) << MC_EMEM_ARB_CFG1_0_EMEM_NOWRSWITCH_BKBLOCK_SHIFT)
+#define MC_EMEM_ARB_CFG1_0_EMEM_NOWRSWITCH_BKBLOCK_RANGE                        13:13
+#define MC_EMEM_ARB_CFG1_0_EMEM_NOWRSWITCH_BKBLOCK_WOFFSET                      0x0
+#define MC_EMEM_ARB_CFG1_0_EMEM_NOWRSWITCH_BKBLOCK_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG1_0_EMEM_NOWRSWITCH_BKBLOCK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_EMEM_ARB_CFG1_0_EMEM_NOWRSWITCH_BKBLOCK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG1_0_EMEM_NOWRSWITCH_BKBLOCK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG1_0_EMEM_NOWRSWITCH_BKBLOCK_INIT_ENUM                    DISABLE
+#define MC_EMEM_ARB_CFG1_0_EMEM_NOWRSWITCH_BKBLOCK_DISABLE                      _MK_ENUM_CONST(0)
+#define MC_EMEM_ARB_CFG1_0_EMEM_NOWRSWITCH_BKBLOCK_ENABLE                       _MK_ENUM_CONST(1)
+#define MC_EMEM_ARB_CFG1_0_EMEM_NOWRSWITCH_BKBLOCK_DISABLED                     _MK_ENUM_CONST(0)
+#define MC_EMEM_ARB_CFG1_0_EMEM_NOWRSWITCH_BKBLOCK_ENABLED                      _MK_ENUM_CONST(1)
+
+#define MC_EMEM_ARB_CFG1_0_EMEM_RWSWITCH_RWINEXPIRED_SHIFT                      _MK_SHIFT_CONST(14)
+#define MC_EMEM_ARB_CFG1_0_EMEM_RWSWITCH_RWINEXPIRED_FIELD                      (_MK_MASK_CONST(0x1) << MC_EMEM_ARB_CFG1_0_EMEM_RWSWITCH_RWINEXPIRED_SHIFT)
+#define MC_EMEM_ARB_CFG1_0_EMEM_RWSWITCH_RWINEXPIRED_RANGE                      14:14
+#define MC_EMEM_ARB_CFG1_0_EMEM_RWSWITCH_RWINEXPIRED_WOFFSET                    0x0
+#define MC_EMEM_ARB_CFG1_0_EMEM_RWSWITCH_RWINEXPIRED_DEFAULT                    _MK_MASK_CONST(0x1)
+#define MC_EMEM_ARB_CFG1_0_EMEM_RWSWITCH_RWINEXPIRED_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_EMEM_ARB_CFG1_0_EMEM_RWSWITCH_RWINEXPIRED_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG1_0_EMEM_RWSWITCH_RWINEXPIRED_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG1_0_EMEM_RWSWITCH_RWINEXPIRED_INIT_ENUM                  ENABLE
+#define MC_EMEM_ARB_CFG1_0_EMEM_RWSWITCH_RWINEXPIRED_DISABLE                    _MK_ENUM_CONST(0)
+#define MC_EMEM_ARB_CFG1_0_EMEM_RWSWITCH_RWINEXPIRED_ENABLE                     _MK_ENUM_CONST(1)
+#define MC_EMEM_ARB_CFG1_0_EMEM_RWSWITCH_RWINEXPIRED_DISABLED                   _MK_ENUM_CONST(0)
+#define MC_EMEM_ARB_CFG1_0_EMEM_RWSWITCH_RWINEXPIRED_ENABLED                    _MK_ENUM_CONST(1)
+
+#define MC_EMEM_ARB_CFG1_0_EMEM_WRSWITCH_WWINEXPIRED_SHIFT                      _MK_SHIFT_CONST(15)
+#define MC_EMEM_ARB_CFG1_0_EMEM_WRSWITCH_WWINEXPIRED_FIELD                      (_MK_MASK_CONST(0x1) << MC_EMEM_ARB_CFG1_0_EMEM_WRSWITCH_WWINEXPIRED_SHIFT)
+#define MC_EMEM_ARB_CFG1_0_EMEM_WRSWITCH_WWINEXPIRED_RANGE                      15:15
+#define MC_EMEM_ARB_CFG1_0_EMEM_WRSWITCH_WWINEXPIRED_WOFFSET                    0x0
+#define MC_EMEM_ARB_CFG1_0_EMEM_WRSWITCH_WWINEXPIRED_DEFAULT                    _MK_MASK_CONST(0x1)
+#define MC_EMEM_ARB_CFG1_0_EMEM_WRSWITCH_WWINEXPIRED_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_EMEM_ARB_CFG1_0_EMEM_WRSWITCH_WWINEXPIRED_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG1_0_EMEM_WRSWITCH_WWINEXPIRED_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG1_0_EMEM_WRSWITCH_WWINEXPIRED_INIT_ENUM                  ENABLE
+#define MC_EMEM_ARB_CFG1_0_EMEM_WRSWITCH_WWINEXPIRED_DISABLE                    _MK_ENUM_CONST(0)
+#define MC_EMEM_ARB_CFG1_0_EMEM_WRSWITCH_WWINEXPIRED_ENABLE                     _MK_ENUM_CONST(1)
+#define MC_EMEM_ARB_CFG1_0_EMEM_WRSWITCH_WWINEXPIRED_DISABLED                   _MK_ENUM_CONST(0)
+#define MC_EMEM_ARB_CFG1_0_EMEM_WRSWITCH_WWINEXPIRED_ENABLED                    _MK_ENUM_CONST(1)
+
+#define MC_EMEM_ARB_CFG1_0_EMEM_SP_MAX_GRANT_SHIFT                      _MK_SHIFT_CONST(16)
+#define MC_EMEM_ARB_CFG1_0_EMEM_SP_MAX_GRANT_FIELD                      (_MK_MASK_CONST(0x3f) << MC_EMEM_ARB_CFG1_0_EMEM_SP_MAX_GRANT_SHIFT)
+#define MC_EMEM_ARB_CFG1_0_EMEM_SP_MAX_GRANT_RANGE                      21:16
+#define MC_EMEM_ARB_CFG1_0_EMEM_SP_MAX_GRANT_WOFFSET                    0x0
+#define MC_EMEM_ARB_CFG1_0_EMEM_SP_MAX_GRANT_DEFAULT                    _MK_MASK_CONST(0x10)
+#define MC_EMEM_ARB_CFG1_0_EMEM_SP_MAX_GRANT_DEFAULT_MASK                       _MK_MASK_CONST(0x3f)
+#define MC_EMEM_ARB_CFG1_0_EMEM_SP_MAX_GRANT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG1_0_EMEM_SP_MAX_GRANT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register MC_GART_CONFIG_0  
+#define MC_GART_CONFIG_0                        _MK_ADDR_CONST(0x1c)
+#define MC_GART_CONFIG_0_WORD_COUNT                     0x1
+#define MC_GART_CONFIG_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define MC_GART_CONFIG_0_RESET_MASK                     _MK_MASK_CONST(0x1)
+#define MC_GART_CONFIG_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define MC_GART_CONFIG_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_GART_CONFIG_0_READ_MASK                      _MK_MASK_CONST(0x1)
+#define MC_GART_CONFIG_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
+#define MC_GART_CONFIG_0_GART_ENABLE_SHIFT                      _MK_SHIFT_CONST(0)
+#define MC_GART_CONFIG_0_GART_ENABLE_FIELD                      (_MK_MASK_CONST(0x1) << MC_GART_CONFIG_0_GART_ENABLE_SHIFT)
+#define MC_GART_CONFIG_0_GART_ENABLE_RANGE                      0:0
+#define MC_GART_CONFIG_0_GART_ENABLE_WOFFSET                    0x0
+#define MC_GART_CONFIG_0_GART_ENABLE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_GART_CONFIG_0_GART_ENABLE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_GART_CONFIG_0_GART_ENABLE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_GART_CONFIG_0_GART_ENABLE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_GART_CONFIG_0_GART_ENABLE_INIT_ENUM                  DISABLE
+#define MC_GART_CONFIG_0_GART_ENABLE_DISABLE                    _MK_ENUM_CONST(0)
+#define MC_GART_CONFIG_0_GART_ENABLE_ENABLE                     _MK_ENUM_CONST(1)
+
+
+// Register MC_GART_ENTRY_ADDR_0  
+#define MC_GART_ENTRY_ADDR_0                    _MK_ADDR_CONST(0x20)
+#define MC_GART_ENTRY_ADDR_0_WORD_COUNT                         0x1
+#define MC_GART_ENTRY_ADDR_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define MC_GART_ENTRY_ADDR_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define MC_GART_ENTRY_ADDR_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define MC_GART_ENTRY_ADDR_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_GART_ENTRY_ADDR_0_READ_MASK                  _MK_MASK_CONST(0xfff000)
+#define MC_GART_ENTRY_ADDR_0_WRITE_MASK                         _MK_MASK_CONST(0xfff000)
+#define MC_GART_ENTRY_ADDR_0_GART_ENTRY_ADDR_TABLE_ADDR_SHIFT                   _MK_SHIFT_CONST(12)
+#define MC_GART_ENTRY_ADDR_0_GART_ENTRY_ADDR_TABLE_ADDR_FIELD                   (_MK_MASK_CONST(0xfff) << MC_GART_ENTRY_ADDR_0_GART_ENTRY_ADDR_TABLE_ADDR_SHIFT)
+#define MC_GART_ENTRY_ADDR_0_GART_ENTRY_ADDR_TABLE_ADDR_RANGE                   23:12
+#define MC_GART_ENTRY_ADDR_0_GART_ENTRY_ADDR_TABLE_ADDR_WOFFSET                 0x0
+#define MC_GART_ENTRY_ADDR_0_GART_ENTRY_ADDR_TABLE_ADDR_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_GART_ENTRY_ADDR_0_GART_ENTRY_ADDR_TABLE_ADDR_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_GART_ENTRY_ADDR_0_GART_ENTRY_ADDR_TABLE_ADDR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_GART_ENTRY_ADDR_0_GART_ENTRY_ADDR_TABLE_ADDR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register MC_GART_ENTRY_DATA_0  
+#define MC_GART_ENTRY_DATA_0                    _MK_ADDR_CONST(0x24)
+#define MC_GART_ENTRY_DATA_0_WORD_COUNT                         0x1
+#define MC_GART_ENTRY_DATA_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define MC_GART_ENTRY_DATA_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define MC_GART_ENTRY_DATA_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define MC_GART_ENTRY_DATA_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_GART_ENTRY_DATA_0_READ_MASK                  _MK_MASK_CONST(0xfffff000)
+#define MC_GART_ENTRY_DATA_0_WRITE_MASK                         _MK_MASK_CONST(0xfffff000)
+#define MC_GART_ENTRY_DATA_0_GART_ENTRY_DATA_PHYS_ADDR_VALID_SHIFT                      _MK_SHIFT_CONST(31)
+#define MC_GART_ENTRY_DATA_0_GART_ENTRY_DATA_PHYS_ADDR_VALID_FIELD                      (_MK_MASK_CONST(0x1) << MC_GART_ENTRY_DATA_0_GART_ENTRY_DATA_PHYS_ADDR_VALID_SHIFT)
+#define MC_GART_ENTRY_DATA_0_GART_ENTRY_DATA_PHYS_ADDR_VALID_RANGE                      31:31
+#define MC_GART_ENTRY_DATA_0_GART_ENTRY_DATA_PHYS_ADDR_VALID_WOFFSET                    0x0
+#define MC_GART_ENTRY_DATA_0_GART_ENTRY_DATA_PHYS_ADDR_VALID_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_GART_ENTRY_DATA_0_GART_ENTRY_DATA_PHYS_ADDR_VALID_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_GART_ENTRY_DATA_0_GART_ENTRY_DATA_PHYS_ADDR_VALID_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_GART_ENTRY_DATA_0_GART_ENTRY_DATA_PHYS_ADDR_VALID_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define MC_GART_ENTRY_DATA_0_GART_ENTRY_DATA_PHYS_ADDR_SHIFT                    _MK_SHIFT_CONST(12)
+#define MC_GART_ENTRY_DATA_0_GART_ENTRY_DATA_PHYS_ADDR_FIELD                    (_MK_MASK_CONST(0x7ffff) << MC_GART_ENTRY_DATA_0_GART_ENTRY_DATA_PHYS_ADDR_SHIFT)
+#define MC_GART_ENTRY_DATA_0_GART_ENTRY_DATA_PHYS_ADDR_RANGE                    30:12
+#define MC_GART_ENTRY_DATA_0_GART_ENTRY_DATA_PHYS_ADDR_WOFFSET                  0x0
+#define MC_GART_ENTRY_DATA_0_GART_ENTRY_DATA_PHYS_ADDR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_GART_ENTRY_DATA_0_GART_ENTRY_DATA_PHYS_ADDR_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_GART_ENTRY_DATA_0_GART_ENTRY_DATA_PHYS_ADDR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_GART_ENTRY_DATA_0_GART_ENTRY_DATA_PHYS_ADDR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register MC_GART_ERROR_REQ_0  
+#define MC_GART_ERROR_REQ_0                     _MK_ADDR_CONST(0x28)
+#define MC_GART_ERROR_REQ_0_WORD_COUNT                  0x1
+#define MC_GART_ERROR_REQ_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define MC_GART_ERROR_REQ_0_RESET_MASK                  _MK_MASK_CONST(0x0)
+#define MC_GART_ERROR_REQ_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define MC_GART_ERROR_REQ_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_GART_ERROR_REQ_0_READ_MASK                   _MK_MASK_CONST(0x7f)
+#define MC_GART_ERROR_REQ_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define MC_GART_ERROR_REQ_0_GART_ERROR_DIRECTION_SHIFT                  _MK_SHIFT_CONST(0)
+#define MC_GART_ERROR_REQ_0_GART_ERROR_DIRECTION_FIELD                  (_MK_MASK_CONST(0x1) << MC_GART_ERROR_REQ_0_GART_ERROR_DIRECTION_SHIFT)
+#define MC_GART_ERROR_REQ_0_GART_ERROR_DIRECTION_RANGE                  0:0
+#define MC_GART_ERROR_REQ_0_GART_ERROR_DIRECTION_WOFFSET                        0x0
+#define MC_GART_ERROR_REQ_0_GART_ERROR_DIRECTION_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_GART_ERROR_REQ_0_GART_ERROR_DIRECTION_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_GART_ERROR_REQ_0_GART_ERROR_DIRECTION_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_GART_ERROR_REQ_0_GART_ERROR_DIRECTION_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_GART_ERROR_REQ_0_GART_ERROR_DIRECTION_READ                   _MK_ENUM_CONST(0)
+#define MC_GART_ERROR_REQ_0_GART_ERROR_DIRECTION_WRITE                  _MK_ENUM_CONST(1)
+
+#define MC_GART_ERROR_REQ_0_GART_ERROR_CLIENT_ID_SHIFT                  _MK_SHIFT_CONST(1)
+#define MC_GART_ERROR_REQ_0_GART_ERROR_CLIENT_ID_FIELD                  (_MK_MASK_CONST(0x3f) << MC_GART_ERROR_REQ_0_GART_ERROR_CLIENT_ID_SHIFT)
+#define MC_GART_ERROR_REQ_0_GART_ERROR_CLIENT_ID_RANGE                  6:1
+#define MC_GART_ERROR_REQ_0_GART_ERROR_CLIENT_ID_WOFFSET                        0x0
+#define MC_GART_ERROR_REQ_0_GART_ERROR_CLIENT_ID_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_GART_ERROR_REQ_0_GART_ERROR_CLIENT_ID_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_GART_ERROR_REQ_0_GART_ERROR_CLIENT_ID_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_GART_ERROR_REQ_0_GART_ERROR_CLIENT_ID_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register MC_GART_ERROR_ADDR_0  
+#define MC_GART_ERROR_ADDR_0                    _MK_ADDR_CONST(0x2c)
+#define MC_GART_ERROR_ADDR_0_WORD_COUNT                         0x1
+#define MC_GART_ERROR_ADDR_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define MC_GART_ERROR_ADDR_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define MC_GART_ERROR_ADDR_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define MC_GART_ERROR_ADDR_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_GART_ERROR_ADDR_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define MC_GART_ERROR_ADDR_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
+#define MC_GART_ERROR_ADDR_0_GART_ERROR_ADDRESS_SHIFT                   _MK_SHIFT_CONST(0)
+#define MC_GART_ERROR_ADDR_0_GART_ERROR_ADDRESS_FIELD                   (_MK_MASK_CONST(0xffffffff) << MC_GART_ERROR_ADDR_0_GART_ERROR_ADDRESS_SHIFT)
+#define MC_GART_ERROR_ADDR_0_GART_ERROR_ADDRESS_RANGE                   31:0
+#define MC_GART_ERROR_ADDR_0_GART_ERROR_ADDRESS_WOFFSET                 0x0
+#define MC_GART_ERROR_ADDR_0_GART_ERROR_ADDRESS_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_GART_ERROR_ADDR_0_GART_ERROR_ADDRESS_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_GART_ERROR_ADDR_0_GART_ERROR_ADDRESS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_GART_ERROR_ADDR_0_GART_ERROR_ADDRESS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register MC_PARTITION_CONFLICT_CFG_0  
+#define MC_PARTITION_CONFLICT_CFG_0                     _MK_ADDR_CONST(0x30)
+#define MC_PARTITION_CONFLICT_CFG_0_WORD_COUNT                  0x1
+#define MC_PARTITION_CONFLICT_CFG_0_RESET_VAL                   _MK_MASK_CONST(0x2)
+#define MC_PARTITION_CONFLICT_CFG_0_RESET_MASK                  _MK_MASK_CONST(0x2)
+#define MC_PARTITION_CONFLICT_CFG_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define MC_PARTITION_CONFLICT_CFG_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_PARTITION_CONFLICT_CFG_0_READ_MASK                   _MK_MASK_CONST(0x2)
+#define MC_PARTITION_CONFLICT_CFG_0_WRITE_MASK                  _MK_MASK_CONST(0x2)
+#define MC_PARTITION_CONFLICT_CFG_0_MEM_RDPATHS_SHIFT                   _MK_SHIFT_CONST(1)
+#define MC_PARTITION_CONFLICT_CFG_0_MEM_RDPATHS_FIELD                   (_MK_MASK_CONST(0x1) << MC_PARTITION_CONFLICT_CFG_0_MEM_RDPATHS_SHIFT)
+#define MC_PARTITION_CONFLICT_CFG_0_MEM_RDPATHS_RANGE                   1:1
+#define MC_PARTITION_CONFLICT_CFG_0_MEM_RDPATHS_WOFFSET                 0x0
+#define MC_PARTITION_CONFLICT_CFG_0_MEM_RDPATHS_DEFAULT                 _MK_MASK_CONST(0x1)
+#define MC_PARTITION_CONFLICT_CFG_0_MEM_RDPATHS_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define MC_PARTITION_CONFLICT_CFG_0_MEM_RDPATHS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_PARTITION_CONFLICT_CFG_0_MEM_RDPATHS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_PARTITION_CONFLICT_CFG_0_MEM_RDPATHS_INIT_ENUM                       MULTI
+#define MC_PARTITION_CONFLICT_CFG_0_MEM_RDPATHS_SINGLE                  _MK_ENUM_CONST(0)
+#define MC_PARTITION_CONFLICT_CFG_0_MEM_RDPATHS_MULTI                   _MK_ENUM_CONST(1)
+
+
+// Register MC_TIMEOUT_CTRL_0  
+#define MC_TIMEOUT_CTRL_0                       _MK_ADDR_CONST(0x34)
+#define MC_TIMEOUT_CTRL_0_WORD_COUNT                    0x1
+#define MC_TIMEOUT_CTRL_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_CTRL_0_RESET_MASK                    _MK_MASK_CONST(0x78)
+#define MC_TIMEOUT_CTRL_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_CTRL_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_CTRL_0_READ_MASK                     _MK_MASK_CONST(0x78)
+#define MC_TIMEOUT_CTRL_0_WRITE_MASK                    _MK_MASK_CONST(0x78)
+#define MC_TIMEOUT_CTRL_0_EMEM_TM_SFACTOR_SHIFT                 _MK_SHIFT_CONST(3)
+#define MC_TIMEOUT_CTRL_0_EMEM_TM_SFACTOR_FIELD                 (_MK_MASK_CONST(0x7) << MC_TIMEOUT_CTRL_0_EMEM_TM_SFACTOR_SHIFT)
+#define MC_TIMEOUT_CTRL_0_EMEM_TM_SFACTOR_RANGE                 5:3
+#define MC_TIMEOUT_CTRL_0_EMEM_TM_SFACTOR_WOFFSET                       0x0
+#define MC_TIMEOUT_CTRL_0_EMEM_TM_SFACTOR_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_CTRL_0_EMEM_TM_SFACTOR_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
+#define MC_TIMEOUT_CTRL_0_EMEM_TM_SFACTOR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_CTRL_0_EMEM_TM_SFACTOR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_CTRL_0_TMCREDITS_SHIFT                       _MK_SHIFT_CONST(6)
+#define MC_TIMEOUT_CTRL_0_TMCREDITS_FIELD                       (_MK_MASK_CONST(0x1) << MC_TIMEOUT_CTRL_0_TMCREDITS_SHIFT)
+#define MC_TIMEOUT_CTRL_0_TMCREDITS_RANGE                       6:6
+#define MC_TIMEOUT_CTRL_0_TMCREDITS_WOFFSET                     0x0
+#define MC_TIMEOUT_CTRL_0_TMCREDITS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_CTRL_0_TMCREDITS_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_TIMEOUT_CTRL_0_TMCREDITS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_CTRL_0_TMCREDITS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_CTRL_0_TMCREDITS_INIT_ENUM                   FROM_CIF_FIFO
+#define MC_TIMEOUT_CTRL_0_TMCREDITS_FROM_CIF_FIFO                       _MK_ENUM_CONST(0)
+#define MC_TIMEOUT_CTRL_0_TMCREDITS_ONE                 _MK_ENUM_CONST(1)
+
+
+// Reserved address 56 [0x38] 
+
+// Reserved address 60 [0x3c] 
+
+// Register MC_DECERR_AXI_STATUS_0  
+#define MC_DECERR_AXI_STATUS_0                  _MK_ADDR_CONST(0x40)
+#define MC_DECERR_AXI_STATUS_0_WORD_COUNT                       0x1
+#define MC_DECERR_AXI_STATUS_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define MC_DECERR_AXI_STATUS_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define MC_DECERR_AXI_STATUS_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define MC_DECERR_AXI_STATUS_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_DECERR_AXI_STATUS_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define MC_DECERR_AXI_STATUS_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_RW_SHIFT                      _MK_SHIFT_CONST(0)
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_RW_FIELD                      (_MK_MASK_CONST(0x1) << MC_DECERR_AXI_STATUS_0_DECERR_AXI_RW_SHIFT)
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_RW_RANGE                      0:0
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_RW_WOFFSET                    0x0
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_RW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_RW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_RW_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_RW_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_RW_READ                       _MK_ENUM_CONST(0)
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_RW_WRITE                      _MK_ENUM_CONST(1)
+
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_ID_SHIFT                      _MK_SHIFT_CONST(1)
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_ID_FIELD                      (_MK_MASK_CONST(0xff) << MC_DECERR_AXI_STATUS_0_DECERR_AXI_ID_SHIFT)
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_ID_RANGE                      8:1
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_ID_WOFFSET                    0x0
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_ID_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_ID_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_ID_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_ID_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_LEN_SHIFT                     _MK_SHIFT_CONST(9)
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_LEN_FIELD                     (_MK_MASK_CONST(0xf) << MC_DECERR_AXI_STATUS_0_DECERR_AXI_LEN_SHIFT)
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_LEN_RANGE                     12:9
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_LEN_WOFFSET                   0x0
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_LEN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_LEN_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_LEN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_LEN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_SIZE_SHIFT                    _MK_SHIFT_CONST(13)
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_SIZE_FIELD                    (_MK_MASK_CONST(0x7) << MC_DECERR_AXI_STATUS_0_DECERR_AXI_SIZE_SHIFT)
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_SIZE_RANGE                    15:13
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_SIZE_WOFFSET                  0x0
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_SIZE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_SIZE_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_SIZE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_SIZE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_BURST_SHIFT                   _MK_SHIFT_CONST(16)
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_BURST_FIELD                   (_MK_MASK_CONST(0x3) << MC_DECERR_AXI_STATUS_0_DECERR_AXI_BURST_SHIFT)
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_BURST_RANGE                   17:16
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_BURST_WOFFSET                 0x0
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_BURST_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_BURST_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_BURST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_BURST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_CACHE_SHIFT                   _MK_SHIFT_CONST(18)
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_CACHE_FIELD                   (_MK_MASK_CONST(0xf) << MC_DECERR_AXI_STATUS_0_DECERR_AXI_CACHE_SHIFT)
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_CACHE_RANGE                   21:18
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_CACHE_WOFFSET                 0x0
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_CACHE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_CACHE_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_CACHE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_CACHE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_PROT_SHIFT                    _MK_SHIFT_CONST(22)
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_PROT_FIELD                    (_MK_MASK_CONST(0x7) << MC_DECERR_AXI_STATUS_0_DECERR_AXI_PROT_SHIFT)
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_PROT_RANGE                    24:22
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_PROT_WOFFSET                  0x0
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_PROT_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_PROT_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_PROT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_PROT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_LOCK_SHIFT                    _MK_SHIFT_CONST(25)
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_LOCK_FIELD                    (_MK_MASK_CONST(0x3) << MC_DECERR_AXI_STATUS_0_DECERR_AXI_LOCK_SHIFT)
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_LOCK_RANGE                    26:25
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_LOCK_WOFFSET                  0x0
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_LOCK_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_LOCK_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_LOCK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_LOCK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define MC_DECERR_AXI_STATUS_0_DECERR_SOURCE_SHIFT                      _MK_SHIFT_CONST(27)
+#define MC_DECERR_AXI_STATUS_0_DECERR_SOURCE_FIELD                      (_MK_MASK_CONST(0x1f) << MC_DECERR_AXI_STATUS_0_DECERR_SOURCE_SHIFT)
+#define MC_DECERR_AXI_STATUS_0_DECERR_SOURCE_RANGE                      31:27
+#define MC_DECERR_AXI_STATUS_0_DECERR_SOURCE_WOFFSET                    0x0
+#define MC_DECERR_AXI_STATUS_0_DECERR_SOURCE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_DECERR_AXI_STATUS_0_DECERR_SOURCE_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_DECERR_AXI_STATUS_0_DECERR_SOURCE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_DECERR_AXI_STATUS_0_DECERR_SOURCE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register MC_DECERR_AXI_ADR_0  
+#define MC_DECERR_AXI_ADR_0                     _MK_ADDR_CONST(0x44)
+#define MC_DECERR_AXI_ADR_0_WORD_COUNT                  0x1
+#define MC_DECERR_AXI_ADR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define MC_DECERR_AXI_ADR_0_RESET_MASK                  _MK_MASK_CONST(0x0)
+#define MC_DECERR_AXI_ADR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define MC_DECERR_AXI_ADR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_DECERR_AXI_ADR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define MC_DECERR_AXI_ADR_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define MC_DECERR_AXI_ADR_0_DECERR_AXI_ADR_SHIFT                        _MK_SHIFT_CONST(0)
+#define MC_DECERR_AXI_ADR_0_DECERR_AXI_ADR_FIELD                        (_MK_MASK_CONST(0xffffffff) << MC_DECERR_AXI_ADR_0_DECERR_AXI_ADR_SHIFT)
+#define MC_DECERR_AXI_ADR_0_DECERR_AXI_ADR_RANGE                        31:0
+#define MC_DECERR_AXI_ADR_0_DECERR_AXI_ADR_WOFFSET                      0x0
+#define MC_DECERR_AXI_ADR_0_DECERR_AXI_ADR_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_DECERR_AXI_ADR_0_DECERR_AXI_ADR_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_DECERR_AXI_ADR_0_DECERR_AXI_ADR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_DECERR_AXI_ADR_0_DECERR_AXI_ADR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Reserved address 72 [0x48] 
+
+// Reserved address 76 [0x4c] 
+
+// Register MC_DECERR_EMEM_OTHERS_STATUS_0  
+#define MC_DECERR_EMEM_OTHERS_STATUS_0                  _MK_ADDR_CONST(0x50)
+#define MC_DECERR_EMEM_OTHERS_STATUS_0_WORD_COUNT                       0x1
+#define MC_DECERR_EMEM_OTHERS_STATUS_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define MC_DECERR_EMEM_OTHERS_STATUS_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define MC_DECERR_EMEM_OTHERS_STATUS_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define MC_DECERR_EMEM_OTHERS_STATUS_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_DECERR_EMEM_OTHERS_STATUS_0_READ_MASK                        _MK_MASK_CONST(0x7f)
+#define MC_DECERR_EMEM_OTHERS_STATUS_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
+#define MC_DECERR_EMEM_OTHERS_STATUS_0_DECERR_EMEM_OTHERS_RW_SHIFT                      _MK_SHIFT_CONST(0)
+#define MC_DECERR_EMEM_OTHERS_STATUS_0_DECERR_EMEM_OTHERS_RW_FIELD                      (_MK_MASK_CONST(0x1) << MC_DECERR_EMEM_OTHERS_STATUS_0_DECERR_EMEM_OTHERS_RW_SHIFT)
+#define MC_DECERR_EMEM_OTHERS_STATUS_0_DECERR_EMEM_OTHERS_RW_RANGE                      0:0
+#define MC_DECERR_EMEM_OTHERS_STATUS_0_DECERR_EMEM_OTHERS_RW_WOFFSET                    0x0
+#define MC_DECERR_EMEM_OTHERS_STATUS_0_DECERR_EMEM_OTHERS_RW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_DECERR_EMEM_OTHERS_STATUS_0_DECERR_EMEM_OTHERS_RW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_DECERR_EMEM_OTHERS_STATUS_0_DECERR_EMEM_OTHERS_RW_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_DECERR_EMEM_OTHERS_STATUS_0_DECERR_EMEM_OTHERS_RW_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_DECERR_EMEM_OTHERS_STATUS_0_DECERR_EMEM_OTHERS_RW_READ                       _MK_ENUM_CONST(0)
+#define MC_DECERR_EMEM_OTHERS_STATUS_0_DECERR_EMEM_OTHERS_RW_WRITE                      _MK_ENUM_CONST(1)
+
+#define MC_DECERR_EMEM_OTHERS_STATUS_0_DECERR_EMEM_OTHERS_ID_SHIFT                      _MK_SHIFT_CONST(1)
+#define MC_DECERR_EMEM_OTHERS_STATUS_0_DECERR_EMEM_OTHERS_ID_FIELD                      (_MK_MASK_CONST(0x3f) << MC_DECERR_EMEM_OTHERS_STATUS_0_DECERR_EMEM_OTHERS_ID_SHIFT)
+#define MC_DECERR_EMEM_OTHERS_STATUS_0_DECERR_EMEM_OTHERS_ID_RANGE                      6:1
+#define MC_DECERR_EMEM_OTHERS_STATUS_0_DECERR_EMEM_OTHERS_ID_WOFFSET                    0x0
+#define MC_DECERR_EMEM_OTHERS_STATUS_0_DECERR_EMEM_OTHERS_ID_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_DECERR_EMEM_OTHERS_STATUS_0_DECERR_EMEM_OTHERS_ID_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_DECERR_EMEM_OTHERS_STATUS_0_DECERR_EMEM_OTHERS_ID_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_DECERR_EMEM_OTHERS_STATUS_0_DECERR_EMEM_OTHERS_ID_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register MC_DECERR_EMEM_OTHERS_ADR_0  
+#define MC_DECERR_EMEM_OTHERS_ADR_0                     _MK_ADDR_CONST(0x54)
+#define MC_DECERR_EMEM_OTHERS_ADR_0_WORD_COUNT                  0x1
+#define MC_DECERR_EMEM_OTHERS_ADR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define MC_DECERR_EMEM_OTHERS_ADR_0_RESET_MASK                  _MK_MASK_CONST(0x0)
+#define MC_DECERR_EMEM_OTHERS_ADR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define MC_DECERR_EMEM_OTHERS_ADR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_DECERR_EMEM_OTHERS_ADR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define MC_DECERR_EMEM_OTHERS_ADR_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define MC_DECERR_EMEM_OTHERS_ADR_0_DECERR_EMEM_OTHERS_ADR_SHIFT                        _MK_SHIFT_CONST(0)
+#define MC_DECERR_EMEM_OTHERS_ADR_0_DECERR_EMEM_OTHERS_ADR_FIELD                        (_MK_MASK_CONST(0xffffffff) << MC_DECERR_EMEM_OTHERS_ADR_0_DECERR_EMEM_OTHERS_ADR_SHIFT)
+#define MC_DECERR_EMEM_OTHERS_ADR_0_DECERR_EMEM_OTHERS_ADR_RANGE                        31:0
+#define MC_DECERR_EMEM_OTHERS_ADR_0_DECERR_EMEM_OTHERS_ADR_WOFFSET                      0x0
+#define MC_DECERR_EMEM_OTHERS_ADR_0_DECERR_EMEM_OTHERS_ADR_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_DECERR_EMEM_OTHERS_ADR_0_DECERR_EMEM_OTHERS_ADR_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_DECERR_EMEM_OTHERS_ADR_0_DECERR_EMEM_OTHERS_ADR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_DECERR_EMEM_OTHERS_ADR_0_DECERR_EMEM_OTHERS_ADR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Reserved address 88 [0x58] 
+
+// Reserved address 92 [0x5c] 
+
+// Register MC_CLKEN_OVERRIDE_0  
+#define MC_CLKEN_OVERRIDE_0                     _MK_ADDR_CONST(0x60)
+#define MC_CLKEN_OVERRIDE_0_WORD_COUNT                  0x1
+#define MC_CLKEN_OVERRIDE_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define MC_CLKEN_OVERRIDE_0_RESET_MASK                  _MK_MASK_CONST(0x1d)
+#define MC_CLKEN_OVERRIDE_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define MC_CLKEN_OVERRIDE_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_CLKEN_OVERRIDE_0_READ_MASK                   _MK_MASK_CONST(0x1d)
+#define MC_CLKEN_OVERRIDE_0_WRITE_MASK                  _MK_MASK_CONST(0x1d)
+#define MC_CLKEN_OVERRIDE_0_CIF_CLKEN_OVR_SHIFT                 _MK_SHIFT_CONST(0)
+#define MC_CLKEN_OVERRIDE_0_CIF_CLKEN_OVR_FIELD                 (_MK_MASK_CONST(0x1) << MC_CLKEN_OVERRIDE_0_CIF_CLKEN_OVR_SHIFT)
+#define MC_CLKEN_OVERRIDE_0_CIF_CLKEN_OVR_RANGE                 0:0
+#define MC_CLKEN_OVERRIDE_0_CIF_CLKEN_OVR_WOFFSET                       0x0
+#define MC_CLKEN_OVERRIDE_0_CIF_CLKEN_OVR_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_CLKEN_OVERRIDE_0_CIF_CLKEN_OVR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_CLKEN_OVERRIDE_0_CIF_CLKEN_OVR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_CLKEN_OVERRIDE_0_CIF_CLKEN_OVR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_CLKEN_OVERRIDE_0_CIF_CLKEN_OVR_INIT_ENUM                     CLK_GATED
+#define MC_CLKEN_OVERRIDE_0_CIF_CLKEN_OVR_CLK_GATED                     _MK_ENUM_CONST(0)
+#define MC_CLKEN_OVERRIDE_0_CIF_CLKEN_OVR_CLK_ALWAYS_ON                 _MK_ENUM_CONST(1)
+#define MC_CLKEN_OVERRIDE_0_CIF_CLKEN_OVR_DISABLE                       _MK_ENUM_CONST(0)
+#define MC_CLKEN_OVERRIDE_0_CIF_CLKEN_OVR_ENABLE                        _MK_ENUM_CONST(1)
+#define MC_CLKEN_OVERRIDE_0_CIF_CLKEN_OVR_DISABLED                      _MK_ENUM_CONST(0)
+#define MC_CLKEN_OVERRIDE_0_CIF_CLKEN_OVR_ENABLED                       _MK_ENUM_CONST(1)
+
+#define MC_CLKEN_OVERRIDE_0_ESEQ_CLKEN_OVR_SHIFT                        _MK_SHIFT_CONST(2)
+#define MC_CLKEN_OVERRIDE_0_ESEQ_CLKEN_OVR_FIELD                        (_MK_MASK_CONST(0x1) << MC_CLKEN_OVERRIDE_0_ESEQ_CLKEN_OVR_SHIFT)
+#define MC_CLKEN_OVERRIDE_0_ESEQ_CLKEN_OVR_RANGE                        2:2
+#define MC_CLKEN_OVERRIDE_0_ESEQ_CLKEN_OVR_WOFFSET                      0x0
+#define MC_CLKEN_OVERRIDE_0_ESEQ_CLKEN_OVR_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_CLKEN_OVERRIDE_0_ESEQ_CLKEN_OVR_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_CLKEN_OVERRIDE_0_ESEQ_CLKEN_OVR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_CLKEN_OVERRIDE_0_ESEQ_CLKEN_OVR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_CLKEN_OVERRIDE_0_ESEQ_CLKEN_OVR_INIT_ENUM                    CLK_GATED
+#define MC_CLKEN_OVERRIDE_0_ESEQ_CLKEN_OVR_CLK_GATED                    _MK_ENUM_CONST(0)
+#define MC_CLKEN_OVERRIDE_0_ESEQ_CLKEN_OVR_CLK_ALWAYS_ON                        _MK_ENUM_CONST(1)
+#define MC_CLKEN_OVERRIDE_0_ESEQ_CLKEN_OVR_DISABLE                      _MK_ENUM_CONST(0)
+#define MC_CLKEN_OVERRIDE_0_ESEQ_CLKEN_OVR_ENABLE                       _MK_ENUM_CONST(1)
+#define MC_CLKEN_OVERRIDE_0_ESEQ_CLKEN_OVR_DISABLED                     _MK_ENUM_CONST(0)
+#define MC_CLKEN_OVERRIDE_0_ESEQ_CLKEN_OVR_ENABLED                      _MK_ENUM_CONST(1)
+
+#define MC_CLKEN_OVERRIDE_0_REGS_CLKEN_OVR_SHIFT                        _MK_SHIFT_CONST(3)
+#define MC_CLKEN_OVERRIDE_0_REGS_CLKEN_OVR_FIELD                        (_MK_MASK_CONST(0x1) << MC_CLKEN_OVERRIDE_0_REGS_CLKEN_OVR_SHIFT)
+#define MC_CLKEN_OVERRIDE_0_REGS_CLKEN_OVR_RANGE                        3:3
+#define MC_CLKEN_OVERRIDE_0_REGS_CLKEN_OVR_WOFFSET                      0x0
+#define MC_CLKEN_OVERRIDE_0_REGS_CLKEN_OVR_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_CLKEN_OVERRIDE_0_REGS_CLKEN_OVR_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_CLKEN_OVERRIDE_0_REGS_CLKEN_OVR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_CLKEN_OVERRIDE_0_REGS_CLKEN_OVR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_CLKEN_OVERRIDE_0_REGS_CLKEN_OVR_INIT_ENUM                    CLK_GATED
+#define MC_CLKEN_OVERRIDE_0_REGS_CLKEN_OVR_CLK_GATED                    _MK_ENUM_CONST(0)
+#define MC_CLKEN_OVERRIDE_0_REGS_CLKEN_OVR_CLK_ALWAYS_ON                        _MK_ENUM_CONST(1)
+#define MC_CLKEN_OVERRIDE_0_REGS_CLKEN_OVR_DISABLE                      _MK_ENUM_CONST(0)
+#define MC_CLKEN_OVERRIDE_0_REGS_CLKEN_OVR_ENABLE                       _MK_ENUM_CONST(1)
+#define MC_CLKEN_OVERRIDE_0_REGS_CLKEN_OVR_DISABLED                     _MK_ENUM_CONST(0)
+#define MC_CLKEN_OVERRIDE_0_REGS_CLKEN_OVR_ENABLED                      _MK_ENUM_CONST(1)
+
+#define MC_CLKEN_OVERRIDE_0_GART_CLKEN_OVR_SHIFT                        _MK_SHIFT_CONST(4)
+#define MC_CLKEN_OVERRIDE_0_GART_CLKEN_OVR_FIELD                        (_MK_MASK_CONST(0x1) << MC_CLKEN_OVERRIDE_0_GART_CLKEN_OVR_SHIFT)
+#define MC_CLKEN_OVERRIDE_0_GART_CLKEN_OVR_RANGE                        4:4
+#define MC_CLKEN_OVERRIDE_0_GART_CLKEN_OVR_WOFFSET                      0x0
+#define MC_CLKEN_OVERRIDE_0_GART_CLKEN_OVR_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_CLKEN_OVERRIDE_0_GART_CLKEN_OVR_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_CLKEN_OVERRIDE_0_GART_CLKEN_OVR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_CLKEN_OVERRIDE_0_GART_CLKEN_OVR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_CLKEN_OVERRIDE_0_GART_CLKEN_OVR_INIT_ENUM                    CLK_GATED
+#define MC_CLKEN_OVERRIDE_0_GART_CLKEN_OVR_CLK_GATED                    _MK_ENUM_CONST(0)
+#define MC_CLKEN_OVERRIDE_0_GART_CLKEN_OVR_CLK_ALWAYS_ON                        _MK_ENUM_CONST(1)
+#define MC_CLKEN_OVERRIDE_0_GART_CLKEN_OVR_DISABLE                      _MK_ENUM_CONST(0)
+#define MC_CLKEN_OVERRIDE_0_GART_CLKEN_OVR_ENABLE                       _MK_ENUM_CONST(1)
+#define MC_CLKEN_OVERRIDE_0_GART_CLKEN_OVR_DISABLED                     _MK_ENUM_CONST(0)
+#define MC_CLKEN_OVERRIDE_0_GART_CLKEN_OVR_ENABLED                      _MK_ENUM_CONST(1)
+
+
+// Register MC_STAT_CONTROL_0  
+#define MC_STAT_CONTROL_0                       _MK_ADDR_CONST(0x64)
+#define MC_STAT_CONTROL_0_WORD_COUNT                    0x1
+#define MC_STAT_CONTROL_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define MC_STAT_CONTROL_0_RESET_MASK                    _MK_MASK_CONST(0x300)
+#define MC_STAT_CONTROL_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define MC_STAT_CONTROL_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_STAT_CONTROL_0_READ_MASK                     _MK_MASK_CONST(0x300)
+#define MC_STAT_CONTROL_0_WRITE_MASK                    _MK_MASK_CONST(0x300)
+#define MC_STAT_CONTROL_0_EMC_GATHER_SHIFT                      _MK_SHIFT_CONST(8)
+#define MC_STAT_CONTROL_0_EMC_GATHER_FIELD                      (_MK_MASK_CONST(0x3) << MC_STAT_CONTROL_0_EMC_GATHER_SHIFT)
+#define MC_STAT_CONTROL_0_EMC_GATHER_RANGE                      9:8
+#define MC_STAT_CONTROL_0_EMC_GATHER_WOFFSET                    0x0
+#define MC_STAT_CONTROL_0_EMC_GATHER_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_STAT_CONTROL_0_EMC_GATHER_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define MC_STAT_CONTROL_0_EMC_GATHER_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_STAT_CONTROL_0_EMC_GATHER_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_STAT_CONTROL_0_EMC_GATHER_INIT_ENUM                  RST
+#define MC_STAT_CONTROL_0_EMC_GATHER_RST                        _MK_ENUM_CONST(0)
+#define MC_STAT_CONTROL_0_EMC_GATHER_CLEAR                      _MK_ENUM_CONST(1)
+#define MC_STAT_CONTROL_0_EMC_GATHER_DISABLE                    _MK_ENUM_CONST(2)
+#define MC_STAT_CONTROL_0_EMC_GATHER_ENABLE                     _MK_ENUM_CONST(3)
+
+
+// Register MC_STAT_STATUS_0  
+#define MC_STAT_STATUS_0                        _MK_ADDR_CONST(0x68)
+#define MC_STAT_STATUS_0_WORD_COUNT                     0x1
+#define MC_STAT_STATUS_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define MC_STAT_STATUS_0_RESET_MASK                     _MK_MASK_CONST(0x0)
+#define MC_STAT_STATUS_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define MC_STAT_STATUS_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_STAT_STATUS_0_READ_MASK                      _MK_MASK_CONST(0x100)
+#define MC_STAT_STATUS_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
+#define MC_STAT_STATUS_0_EMC_LIMIT_SHIFT                        _MK_SHIFT_CONST(8)
+#define MC_STAT_STATUS_0_EMC_LIMIT_FIELD                        (_MK_MASK_CONST(0x1) << MC_STAT_STATUS_0_EMC_LIMIT_SHIFT)
+#define MC_STAT_STATUS_0_EMC_LIMIT_RANGE                        8:8
+#define MC_STAT_STATUS_0_EMC_LIMIT_WOFFSET                      0x0
+#define MC_STAT_STATUS_0_EMC_LIMIT_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_STAT_STATUS_0_EMC_LIMIT_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_STAT_STATUS_0_EMC_LIMIT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_STAT_STATUS_0_EMC_LIMIT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register MC_STAT_EMC_ADDR_LOW_0  
+#define MC_STAT_EMC_ADDR_LOW_0                  _MK_ADDR_CONST(0x6c)
+#define MC_STAT_EMC_ADDR_LOW_0_WORD_COUNT                       0x1
+#define MC_STAT_EMC_ADDR_LOW_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_ADDR_LOW_0_RESET_MASK                       _MK_MASK_CONST(0x3ffffff0)
+#define MC_STAT_EMC_ADDR_LOW_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_ADDR_LOW_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_ADDR_LOW_0_READ_MASK                        _MK_MASK_CONST(0x3ffffff0)
+#define MC_STAT_EMC_ADDR_LOW_0_WRITE_MASK                       _MK_MASK_CONST(0x3ffffff0)
+#define MC_STAT_EMC_ADDR_LOW_0_EMC_ADDR_LOW_SHIFT                       _MK_SHIFT_CONST(4)
+#define MC_STAT_EMC_ADDR_LOW_0_EMC_ADDR_LOW_FIELD                       (_MK_MASK_CONST(0x3ffffff) << MC_STAT_EMC_ADDR_LOW_0_EMC_ADDR_LOW_SHIFT)
+#define MC_STAT_EMC_ADDR_LOW_0_EMC_ADDR_LOW_RANGE                       29:4
+#define MC_STAT_EMC_ADDR_LOW_0_EMC_ADDR_LOW_WOFFSET                     0x0
+#define MC_STAT_EMC_ADDR_LOW_0_EMC_ADDR_LOW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_ADDR_LOW_0_EMC_ADDR_LOW_DEFAULT_MASK                        _MK_MASK_CONST(0x3ffffff)
+#define MC_STAT_EMC_ADDR_LOW_0_EMC_ADDR_LOW_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_ADDR_LOW_0_EMC_ADDR_LOW_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register MC_STAT_EMC_ADDR_HIGH_0  
+#define MC_STAT_EMC_ADDR_HIGH_0                 _MK_ADDR_CONST(0x70)
+#define MC_STAT_EMC_ADDR_HIGH_0_WORD_COUNT                      0x1
+#define MC_STAT_EMC_ADDR_HIGH_0_RESET_VAL                       _MK_MASK_CONST(0x3ffffff0)
+#define MC_STAT_EMC_ADDR_HIGH_0_RESET_MASK                      _MK_MASK_CONST(0x3ffffff0)
+#define MC_STAT_EMC_ADDR_HIGH_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_ADDR_HIGH_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_ADDR_HIGH_0_READ_MASK                       _MK_MASK_CONST(0x3ffffff0)
+#define MC_STAT_EMC_ADDR_HIGH_0_WRITE_MASK                      _MK_MASK_CONST(0x3ffffff0)
+#define MC_STAT_EMC_ADDR_HIGH_0_EMC_ADDR_HIGH_SHIFT                     _MK_SHIFT_CONST(4)
+#define MC_STAT_EMC_ADDR_HIGH_0_EMC_ADDR_HIGH_FIELD                     (_MK_MASK_CONST(0x3ffffff) << MC_STAT_EMC_ADDR_HIGH_0_EMC_ADDR_HIGH_SHIFT)
+#define MC_STAT_EMC_ADDR_HIGH_0_EMC_ADDR_HIGH_RANGE                     29:4
+#define MC_STAT_EMC_ADDR_HIGH_0_EMC_ADDR_HIGH_WOFFSET                   0x0
+#define MC_STAT_EMC_ADDR_HIGH_0_EMC_ADDR_HIGH_DEFAULT                   _MK_MASK_CONST(0xffffffff)
+#define MC_STAT_EMC_ADDR_HIGH_0_EMC_ADDR_HIGH_DEFAULT_MASK                      _MK_MASK_CONST(0x3ffffff)
+#define MC_STAT_EMC_ADDR_HIGH_0_EMC_ADDR_HIGH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_ADDR_HIGH_0_EMC_ADDR_HIGH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_ADDR_HIGH_0_EMC_ADDR_HIGH_INIT_ENUM                 -1
+
+
+// Register MC_STAT_EMC_CLOCK_LIMIT_0  
+#define MC_STAT_EMC_CLOCK_LIMIT_0                       _MK_ADDR_CONST(0x74)
+#define MC_STAT_EMC_CLOCK_LIMIT_0_WORD_COUNT                    0x1
+#define MC_STAT_EMC_CLOCK_LIMIT_0_RESET_VAL                     _MK_MASK_CONST(0xffffffff)
+#define MC_STAT_EMC_CLOCK_LIMIT_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
+#define MC_STAT_EMC_CLOCK_LIMIT_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_CLOCK_LIMIT_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_CLOCK_LIMIT_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define MC_STAT_EMC_CLOCK_LIMIT_0_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
+#define MC_STAT_EMC_CLOCK_LIMIT_0_EMC_CLOCK_LIMIT_SHIFT                 _MK_SHIFT_CONST(0)
+#define MC_STAT_EMC_CLOCK_LIMIT_0_EMC_CLOCK_LIMIT_FIELD                 (_MK_MASK_CONST(0xffffffff) << MC_STAT_EMC_CLOCK_LIMIT_0_EMC_CLOCK_LIMIT_SHIFT)
+#define MC_STAT_EMC_CLOCK_LIMIT_0_EMC_CLOCK_LIMIT_RANGE                 31:0
+#define MC_STAT_EMC_CLOCK_LIMIT_0_EMC_CLOCK_LIMIT_WOFFSET                       0x0
+#define MC_STAT_EMC_CLOCK_LIMIT_0_EMC_CLOCK_LIMIT_DEFAULT                       _MK_MASK_CONST(0xffffffff)
+#define MC_STAT_EMC_CLOCK_LIMIT_0_EMC_CLOCK_LIMIT_DEFAULT_MASK                  _MK_MASK_CONST(0xffffffff)
+#define MC_STAT_EMC_CLOCK_LIMIT_0_EMC_CLOCK_LIMIT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_CLOCK_LIMIT_0_EMC_CLOCK_LIMIT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_CLOCK_LIMIT_0_EMC_CLOCK_LIMIT_INIT_ENUM                     -1
+
+
+// Register MC_STAT_EMC_CLOCKS_0  
+#define MC_STAT_EMC_CLOCKS_0                    _MK_ADDR_CONST(0x78)
+#define MC_STAT_EMC_CLOCKS_0_WORD_COUNT                         0x1
+#define MC_STAT_EMC_CLOCKS_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_CLOCKS_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_CLOCKS_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_CLOCKS_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_CLOCKS_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define MC_STAT_EMC_CLOCKS_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_CLOCKS_0_EMC_CLOCKS_SHIFT                   _MK_SHIFT_CONST(0)
+#define MC_STAT_EMC_CLOCKS_0_EMC_CLOCKS_FIELD                   (_MK_MASK_CONST(0xffffffff) << MC_STAT_EMC_CLOCKS_0_EMC_CLOCKS_SHIFT)
+#define MC_STAT_EMC_CLOCKS_0_EMC_CLOCKS_RANGE                   31:0
+#define MC_STAT_EMC_CLOCKS_0_EMC_CLOCKS_WOFFSET                 0x0
+#define MC_STAT_EMC_CLOCKS_0_EMC_CLOCKS_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_CLOCKS_0_EMC_CLOCKS_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_CLOCKS_0_EMC_CLOCKS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_CLOCKS_0_EMC_CLOCKS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Packet ARMC_STAT_CONTROL
+#define ARMC_STAT_CONTROL_SIZE 32
+
+#define ARMC_STAT_CONTROL_MODE_SHIFT                    _MK_SHIFT_CONST(0)
+#define ARMC_STAT_CONTROL_MODE_FIELD                    (_MK_MASK_CONST(0x3) << ARMC_STAT_CONTROL_MODE_SHIFT)
+#define ARMC_STAT_CONTROL_MODE_RANGE                    _MK_SHIFT_CONST(1):_MK_SHIFT_CONST(0)
+#define ARMC_STAT_CONTROL_MODE_ROW                      0
+#define ARMC_STAT_CONTROL_MODE_BANDWIDTH                        _MK_ENUM_CONST(0)
+#define ARMC_STAT_CONTROL_MODE_LATENCY_AVG                      _MK_ENUM_CONST(1)
+#define ARMC_STAT_CONTROL_MODE_LATENCY_HISTO                    _MK_ENUM_CONST(2)
+
+#define ARMC_STAT_CONTROL_SKIP_SHIFT                    _MK_SHIFT_CONST(4)
+#define ARMC_STAT_CONTROL_SKIP_FIELD                    (_MK_MASK_CONST(0x7) << ARMC_STAT_CONTROL_SKIP_SHIFT)
+#define ARMC_STAT_CONTROL_SKIP_RANGE                    _MK_SHIFT_CONST(6):_MK_SHIFT_CONST(4)
+#define ARMC_STAT_CONTROL_SKIP_ROW                      0
+
+#define ARMC_STAT_CONTROL_CLIENT_ID_SHIFT                       _MK_SHIFT_CONST(8)
+#define ARMC_STAT_CONTROL_CLIENT_ID_FIELD                       (_MK_MASK_CONST(0x3f) << ARMC_STAT_CONTROL_CLIENT_ID_SHIFT)
+#define ARMC_STAT_CONTROL_CLIENT_ID_RANGE                       _MK_SHIFT_CONST(13):_MK_SHIFT_CONST(8)
+#define ARMC_STAT_CONTROL_CLIENT_ID_ROW                 0
+
+#define ARMC_STAT_CONTROL_EVENT_SHIFT                   _MK_SHIFT_CONST(16)
+#define ARMC_STAT_CONTROL_EVENT_FIELD                   (_MK_MASK_CONST(0xff) << ARMC_STAT_CONTROL_EVENT_SHIFT)
+#define ARMC_STAT_CONTROL_EVENT_RANGE                   _MK_SHIFT_CONST(23):_MK_SHIFT_CONST(16)
+#define ARMC_STAT_CONTROL_EVENT_ROW                     0
+#define ARMC_STAT_CONTROL_EVENT_QUALIFIED                       _MK_ENUM_CONST(0)
+#define ARMC_STAT_CONTROL_EVENT_ANY_READ                        _MK_ENUM_CONST(1)
+#define ARMC_STAT_CONTROL_EVENT_ANY_WRITE                       _MK_ENUM_CONST(2)
+#define ARMC_STAT_CONTROL_EVENT_RD_WR_CHANGE                    _MK_ENUM_CONST(3)
+#define ARMC_STAT_CONTROL_EVENT_SUCCESSIVE                      _MK_ENUM_CONST(4)
+#define ARMC_STAT_CONTROL_EVENT_ARB_BANK_AA                     _MK_ENUM_CONST(5)
+#define ARMC_STAT_CONTROL_EVENT_ARB_BANK_BB                     _MK_ENUM_CONST(6)
+#define ARMC_STAT_CONTROL_EVENT_PAGE_MISS                       _MK_ENUM_CONST(7)
+#define ARMC_STAT_CONTROL_EVENT_AUTO_PRECHARGE                  _MK_ENUM_CONST(8)
+
+#define ARMC_STAT_CONTROL_PRI_EVENT_SHIFT                       _MK_SHIFT_CONST(24)
+#define ARMC_STAT_CONTROL_PRI_EVENT_FIELD                       (_MK_MASK_CONST(0x3) << ARMC_STAT_CONTROL_PRI_EVENT_SHIFT)
+#define ARMC_STAT_CONTROL_PRI_EVENT_RANGE                       _MK_SHIFT_CONST(25):_MK_SHIFT_CONST(24)
+#define ARMC_STAT_CONTROL_PRI_EVENT_ROW                 0
+#define ARMC_STAT_CONTROL_PRI_EVENT_HP                  _MK_ENUM_CONST(0)
+#define ARMC_STAT_CONTROL_PRI_EVENT_TM                  _MK_ENUM_CONST(1)
+#define ARMC_STAT_CONTROL_PRI_EVENT_BW                  _MK_ENUM_CONST(2)
+
+#define ARMC_STAT_CONTROL_FILTER_CLIENT_SHIFT                   _MK_SHIFT_CONST(26)
+#define ARMC_STAT_CONTROL_FILTER_CLIENT_FIELD                   (_MK_MASK_CONST(0x1) << ARMC_STAT_CONTROL_FILTER_CLIENT_SHIFT)
+#define ARMC_STAT_CONTROL_FILTER_CLIENT_RANGE                   _MK_SHIFT_CONST(26):_MK_SHIFT_CONST(26)
+#define ARMC_STAT_CONTROL_FILTER_CLIENT_ROW                     0
+#define ARMC_STAT_CONTROL_FILTER_CLIENT_DISABLE                 _MK_ENUM_CONST(0)
+#define ARMC_STAT_CONTROL_FILTER_CLIENT_ENABLE                  _MK_ENUM_CONST(1)
+
+#define ARMC_STAT_CONTROL_FILTER_ADDR_SHIFT                     _MK_SHIFT_CONST(27)
+#define ARMC_STAT_CONTROL_FILTER_ADDR_FIELD                     (_MK_MASK_CONST(0x1) << ARMC_STAT_CONTROL_FILTER_ADDR_SHIFT)
+#define ARMC_STAT_CONTROL_FILTER_ADDR_RANGE                     _MK_SHIFT_CONST(27):_MK_SHIFT_CONST(27)
+#define ARMC_STAT_CONTROL_FILTER_ADDR_ROW                       0
+#define ARMC_STAT_CONTROL_FILTER_ADDR_DISABLE                   _MK_ENUM_CONST(0)
+#define ARMC_STAT_CONTROL_FILTER_ADDR_ENABLE                    _MK_ENUM_CONST(1)
+
+#define ARMC_STAT_CONTROL_FILTER_PRI_SHIFT                      _MK_SHIFT_CONST(28)
+#define ARMC_STAT_CONTROL_FILTER_PRI_FIELD                      (_MK_MASK_CONST(0x3) << ARMC_STAT_CONTROL_FILTER_PRI_SHIFT)
+#define ARMC_STAT_CONTROL_FILTER_PRI_RANGE                      _MK_SHIFT_CONST(29):_MK_SHIFT_CONST(28)
+#define ARMC_STAT_CONTROL_FILTER_PRI_ROW                        0
+#define ARMC_STAT_CONTROL_FILTER_PRI_DISABLE                    _MK_ENUM_CONST(0)
+#define ARMC_STAT_CONTROL_FILTER_PRI_NO                 _MK_ENUM_CONST(1)
+#define ARMC_STAT_CONTROL_FILTER_PRI_YES                        _MK_ENUM_CONST(2)
+
+#define ARMC_STAT_CONTROL_FILTER_COALESCED_SHIFT                        _MK_SHIFT_CONST(30)
+#define ARMC_STAT_CONTROL_FILTER_COALESCED_FIELD                        (_MK_MASK_CONST(0x3) << ARMC_STAT_CONTROL_FILTER_COALESCED_SHIFT)
+#define ARMC_STAT_CONTROL_FILTER_COALESCED_RANGE                        _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(30)
+#define ARMC_STAT_CONTROL_FILTER_COALESCED_ROW                  0
+#define ARMC_STAT_CONTROL_FILTER_COALESCED_DISABLE                      _MK_ENUM_CONST(0)
+#define ARMC_STAT_CONTROL_FILTER_COALESCED_NO                   _MK_ENUM_CONST(1)
+#define ARMC_STAT_CONTROL_FILTER_COALESCED_YES                  _MK_ENUM_CONST(2)
+
+
+// Register MC_STAT_EMC_CONTROL_0_0  
+#define MC_STAT_EMC_CONTROL_0_0                 _MK_ADDR_CONST(0x7c)
+#define MC_STAT_EMC_CONTROL_0_0_WORD_COUNT                      0x1
+#define MC_STAT_EMC_CONTROL_0_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_CONTROL_0_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define MC_STAT_EMC_CONTROL_0_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_CONTROL_0_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_CONTROL_0_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define MC_STAT_EMC_CONTROL_0_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+#define MC_STAT_EMC_CONTROL_0_0_EMC_CONTROL_0_SHIFT                     _MK_SHIFT_CONST(0)
+#define MC_STAT_EMC_CONTROL_0_0_EMC_CONTROL_0_FIELD                     (_MK_MASK_CONST(0xffffffff) << MC_STAT_EMC_CONTROL_0_0_EMC_CONTROL_0_SHIFT)
+#define MC_STAT_EMC_CONTROL_0_0_EMC_CONTROL_0_RANGE                     31:0
+#define MC_STAT_EMC_CONTROL_0_0_EMC_CONTROL_0_WOFFSET                   0x0
+#define MC_STAT_EMC_CONTROL_0_0_EMC_CONTROL_0_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_CONTROL_0_0_EMC_CONTROL_0_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define MC_STAT_EMC_CONTROL_0_0_EMC_CONTROL_0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_CONTROL_0_0_EMC_CONTROL_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register MC_STAT_EMC_CONTROL_1_0  
+#define MC_STAT_EMC_CONTROL_1_0                 _MK_ADDR_CONST(0x80)
+#define MC_STAT_EMC_CONTROL_1_0_WORD_COUNT                      0x1
+#define MC_STAT_EMC_CONTROL_1_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_CONTROL_1_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define MC_STAT_EMC_CONTROL_1_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_CONTROL_1_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_CONTROL_1_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define MC_STAT_EMC_CONTROL_1_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+#define MC_STAT_EMC_CONTROL_1_0_EMC_CONTROL_1_SHIFT                     _MK_SHIFT_CONST(0)
+#define MC_STAT_EMC_CONTROL_1_0_EMC_CONTROL_1_FIELD                     (_MK_MASK_CONST(0xffffffff) << MC_STAT_EMC_CONTROL_1_0_EMC_CONTROL_1_SHIFT)
+#define MC_STAT_EMC_CONTROL_1_0_EMC_CONTROL_1_RANGE                     31:0
+#define MC_STAT_EMC_CONTROL_1_0_EMC_CONTROL_1_WOFFSET                   0x0
+#define MC_STAT_EMC_CONTROL_1_0_EMC_CONTROL_1_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_CONTROL_1_0_EMC_CONTROL_1_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define MC_STAT_EMC_CONTROL_1_0_EMC_CONTROL_1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_CONTROL_1_0_EMC_CONTROL_1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Packet ARMC_STAT_HIST_LIMIT
+#define ARMC_STAT_HIST_LIMIT_SIZE 32
+
+#define ARMC_STAT_HIST_LIMIT_LOW_SHIFT                  _MK_SHIFT_CONST(0)
+#define ARMC_STAT_HIST_LIMIT_LOW_FIELD                  (_MK_MASK_CONST(0xffff) << ARMC_STAT_HIST_LIMIT_LOW_SHIFT)
+#define ARMC_STAT_HIST_LIMIT_LOW_RANGE                  _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(0)
+#define ARMC_STAT_HIST_LIMIT_LOW_ROW                    0
+
+#define ARMC_STAT_HIST_LIMIT_HIGH_SHIFT                 _MK_SHIFT_CONST(16)
+#define ARMC_STAT_HIST_LIMIT_HIGH_FIELD                 (_MK_MASK_CONST(0xffff) << ARMC_STAT_HIST_LIMIT_HIGH_SHIFT)
+#define ARMC_STAT_HIST_LIMIT_HIGH_RANGE                 _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(16)
+#define ARMC_STAT_HIST_LIMIT_HIGH_ROW                   0
+
+
+// Register MC_STAT_EMC_HIST_LIMIT_0_0  
+#define MC_STAT_EMC_HIST_LIMIT_0_0                      _MK_ADDR_CONST(0x84)
+#define MC_STAT_EMC_HIST_LIMIT_0_0_WORD_COUNT                   0x1
+#define MC_STAT_EMC_HIST_LIMIT_0_0_RESET_VAL                    _MK_MASK_CONST(0xffff0000)
+#define MC_STAT_EMC_HIST_LIMIT_0_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define MC_STAT_EMC_HIST_LIMIT_0_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_HIST_LIMIT_0_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_HIST_LIMIT_0_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
+#define MC_STAT_EMC_HIST_LIMIT_0_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
+#define MC_STAT_EMC_HIST_LIMIT_0_0_EMC_HIST_LIMIT_0_SHIFT                       _MK_SHIFT_CONST(0)
+#define MC_STAT_EMC_HIST_LIMIT_0_0_EMC_HIST_LIMIT_0_FIELD                       (_MK_MASK_CONST(0xffffffff) << MC_STAT_EMC_HIST_LIMIT_0_0_EMC_HIST_LIMIT_0_SHIFT)
+#define MC_STAT_EMC_HIST_LIMIT_0_0_EMC_HIST_LIMIT_0_RANGE                       31:0
+#define MC_STAT_EMC_HIST_LIMIT_0_0_EMC_HIST_LIMIT_0_WOFFSET                     0x0
+#define MC_STAT_EMC_HIST_LIMIT_0_0_EMC_HIST_LIMIT_0_DEFAULT                     _MK_MASK_CONST(0xffff0000)
+#define MC_STAT_EMC_HIST_LIMIT_0_0_EMC_HIST_LIMIT_0_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
+#define MC_STAT_EMC_HIST_LIMIT_0_0_EMC_HIST_LIMIT_0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_HIST_LIMIT_0_0_EMC_HIST_LIMIT_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_HIST_LIMIT_0_0_EMC_HIST_LIMIT_0_INIT_ENUM                   -65536
+
+
+// Register MC_STAT_EMC_HIST_LIMIT_1_0  
+#define MC_STAT_EMC_HIST_LIMIT_1_0                      _MK_ADDR_CONST(0x88)
+#define MC_STAT_EMC_HIST_LIMIT_1_0_WORD_COUNT                   0x1
+#define MC_STAT_EMC_HIST_LIMIT_1_0_RESET_VAL                    _MK_MASK_CONST(0xffff0000)
+#define MC_STAT_EMC_HIST_LIMIT_1_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define MC_STAT_EMC_HIST_LIMIT_1_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_HIST_LIMIT_1_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_HIST_LIMIT_1_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
+#define MC_STAT_EMC_HIST_LIMIT_1_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
+#define MC_STAT_EMC_HIST_LIMIT_1_0_EMC_HIST_LIMIT_1_SHIFT                       _MK_SHIFT_CONST(0)
+#define MC_STAT_EMC_HIST_LIMIT_1_0_EMC_HIST_LIMIT_1_FIELD                       (_MK_MASK_CONST(0xffffffff) << MC_STAT_EMC_HIST_LIMIT_1_0_EMC_HIST_LIMIT_1_SHIFT)
+#define MC_STAT_EMC_HIST_LIMIT_1_0_EMC_HIST_LIMIT_1_RANGE                       31:0
+#define MC_STAT_EMC_HIST_LIMIT_1_0_EMC_HIST_LIMIT_1_WOFFSET                     0x0
+#define MC_STAT_EMC_HIST_LIMIT_1_0_EMC_HIST_LIMIT_1_DEFAULT                     _MK_MASK_CONST(0xffff0000)
+#define MC_STAT_EMC_HIST_LIMIT_1_0_EMC_HIST_LIMIT_1_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
+#define MC_STAT_EMC_HIST_LIMIT_1_0_EMC_HIST_LIMIT_1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_HIST_LIMIT_1_0_EMC_HIST_LIMIT_1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_HIST_LIMIT_1_0_EMC_HIST_LIMIT_1_INIT_ENUM                   -65536
+
+
+// Register MC_STAT_EMC_COUNT_0_0  
+#define MC_STAT_EMC_COUNT_0_0                   _MK_ADDR_CONST(0x8c)
+#define MC_STAT_EMC_COUNT_0_0_WORD_COUNT                        0x1
+#define MC_STAT_EMC_COUNT_0_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_COUNT_0_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_COUNT_0_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_COUNT_0_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_COUNT_0_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define MC_STAT_EMC_COUNT_0_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_COUNT_0_0_EMC_COUNT_0_SHIFT                 _MK_SHIFT_CONST(0)
+#define MC_STAT_EMC_COUNT_0_0_EMC_COUNT_0_FIELD                 (_MK_MASK_CONST(0xffffffff) << MC_STAT_EMC_COUNT_0_0_EMC_COUNT_0_SHIFT)
+#define MC_STAT_EMC_COUNT_0_0_EMC_COUNT_0_RANGE                 31:0
+#define MC_STAT_EMC_COUNT_0_0_EMC_COUNT_0_WOFFSET                       0x0
+#define MC_STAT_EMC_COUNT_0_0_EMC_COUNT_0_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_COUNT_0_0_EMC_COUNT_0_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_COUNT_0_0_EMC_COUNT_0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_COUNT_0_0_EMC_COUNT_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register MC_STAT_EMC_COUNT_1_0  
+#define MC_STAT_EMC_COUNT_1_0                   _MK_ADDR_CONST(0x90)
+#define MC_STAT_EMC_COUNT_1_0_WORD_COUNT                        0x1
+#define MC_STAT_EMC_COUNT_1_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_COUNT_1_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_COUNT_1_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_COUNT_1_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_COUNT_1_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define MC_STAT_EMC_COUNT_1_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_COUNT_1_0_EMC_COUNT_1_SHIFT                 _MK_SHIFT_CONST(0)
+#define MC_STAT_EMC_COUNT_1_0_EMC_COUNT_1_FIELD                 (_MK_MASK_CONST(0xffffffff) << MC_STAT_EMC_COUNT_1_0_EMC_COUNT_1_SHIFT)
+#define MC_STAT_EMC_COUNT_1_0_EMC_COUNT_1_RANGE                 31:0
+#define MC_STAT_EMC_COUNT_1_0_EMC_COUNT_1_WOFFSET                       0x0
+#define MC_STAT_EMC_COUNT_1_0_EMC_COUNT_1_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_COUNT_1_0_EMC_COUNT_1_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_COUNT_1_0_EMC_COUNT_1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_COUNT_1_0_EMC_COUNT_1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register MC_STAT_EMC_HIST_0_0  
+#define MC_STAT_EMC_HIST_0_0                    _MK_ADDR_CONST(0x94)
+#define MC_STAT_EMC_HIST_0_0_WORD_COUNT                         0x1
+#define MC_STAT_EMC_HIST_0_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_HIST_0_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_HIST_0_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_HIST_0_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_HIST_0_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define MC_STAT_EMC_HIST_0_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_HIST_0_0_EMC_HIST_0_SHIFT                   _MK_SHIFT_CONST(0)
+#define MC_STAT_EMC_HIST_0_0_EMC_HIST_0_FIELD                   (_MK_MASK_CONST(0xffffffff) << MC_STAT_EMC_HIST_0_0_EMC_HIST_0_SHIFT)
+#define MC_STAT_EMC_HIST_0_0_EMC_HIST_0_RANGE                   31:0
+#define MC_STAT_EMC_HIST_0_0_EMC_HIST_0_WOFFSET                 0x0
+#define MC_STAT_EMC_HIST_0_0_EMC_HIST_0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_HIST_0_0_EMC_HIST_0_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_HIST_0_0_EMC_HIST_0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_HIST_0_0_EMC_HIST_0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register MC_STAT_EMC_HIST_1_0  
+#define MC_STAT_EMC_HIST_1_0                    _MK_ADDR_CONST(0x98)
+#define MC_STAT_EMC_HIST_1_0_WORD_COUNT                         0x1
+#define MC_STAT_EMC_HIST_1_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_HIST_1_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_HIST_1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_HIST_1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_HIST_1_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define MC_STAT_EMC_HIST_1_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_HIST_1_0_EMC_HIST_1_SHIFT                   _MK_SHIFT_CONST(0)
+#define MC_STAT_EMC_HIST_1_0_EMC_HIST_1_FIELD                   (_MK_MASK_CONST(0xffffffff) << MC_STAT_EMC_HIST_1_0_EMC_HIST_1_SHIFT)
+#define MC_STAT_EMC_HIST_1_0_EMC_HIST_1_RANGE                   31:0
+#define MC_STAT_EMC_HIST_1_0_EMC_HIST_1_WOFFSET                 0x0
+#define MC_STAT_EMC_HIST_1_0_EMC_HIST_1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_HIST_1_0_EMC_HIST_1_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_HIST_1_0_EMC_HIST_1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_HIST_1_0_EMC_HIST_1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define MC_CLIENT_CTRL_DISABLE  0
+#define MC_CLIENT_CTRL_ENABLE   1
+
+// Register MC_CLIENT_CTRL_0  
+#define MC_CLIENT_CTRL_0                        _MK_ADDR_CONST(0x9c)
+#define MC_CLIENT_CTRL_0_WORD_COUNT                     0x1
+#define MC_CLIENT_CTRL_0_RESET_VAL                      _MK_MASK_CONST(0x7fff)
+#define MC_CLIENT_CTRL_0_RESET_MASK                     _MK_MASK_CONST(0x7fff)
+#define MC_CLIENT_CTRL_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_READ_MASK                      _MK_MASK_CONST(0x7fff)
+#define MC_CLIENT_CTRL_0_WRITE_MASK                     _MK_MASK_CONST(0x7fff)
+#define MC_CLIENT_CTRL_0_CMC_ENABLE_SHIFT                       _MK_SHIFT_CONST(0)
+#define MC_CLIENT_CTRL_0_CMC_ENABLE_FIELD                       (_MK_MASK_CONST(0x1) << MC_CLIENT_CTRL_0_CMC_ENABLE_SHIFT)
+#define MC_CLIENT_CTRL_0_CMC_ENABLE_RANGE                       0:0
+#define MC_CLIENT_CTRL_0_CMC_ENABLE_WOFFSET                     0x0
+#define MC_CLIENT_CTRL_0_CMC_ENABLE_DEFAULT                     _MK_MASK_CONST(0x1)
+#define MC_CLIENT_CTRL_0_CMC_ENABLE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_CLIENT_CTRL_0_CMC_ENABLE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_CMC_ENABLE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_CMC_ENABLE_INIT_ENUM                   ENABLE
+#define MC_CLIENT_CTRL_0_CMC_ENABLE_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_CLIENT_CTRL_0_CMC_ENABLE_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_CLIENT_CTRL_0_CMC_ENABLE_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_CLIENT_CTRL_0_CMC_ENABLE_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_CTRL_0_DC_ENABLE_SHIFT                        _MK_SHIFT_CONST(1)
+#define MC_CLIENT_CTRL_0_DC_ENABLE_FIELD                        (_MK_MASK_CONST(0x1) << MC_CLIENT_CTRL_0_DC_ENABLE_SHIFT)
+#define MC_CLIENT_CTRL_0_DC_ENABLE_RANGE                        1:1
+#define MC_CLIENT_CTRL_0_DC_ENABLE_WOFFSET                      0x0
+#define MC_CLIENT_CTRL_0_DC_ENABLE_DEFAULT                      _MK_MASK_CONST(0x1)
+#define MC_CLIENT_CTRL_0_DC_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_CLIENT_CTRL_0_DC_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_DC_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_DC_ENABLE_INIT_ENUM                    ENABLE
+#define MC_CLIENT_CTRL_0_DC_ENABLE_DISABLE                      _MK_ENUM_CONST(0)
+#define MC_CLIENT_CTRL_0_DC_ENABLE_ENABLE                       _MK_ENUM_CONST(1)
+#define MC_CLIENT_CTRL_0_DC_ENABLE_DISABLED                     _MK_ENUM_CONST(0)
+#define MC_CLIENT_CTRL_0_DC_ENABLE_ENABLED                      _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_CTRL_0_DCB_ENABLE_SHIFT                       _MK_SHIFT_CONST(2)
+#define MC_CLIENT_CTRL_0_DCB_ENABLE_FIELD                       (_MK_MASK_CONST(0x1) << MC_CLIENT_CTRL_0_DCB_ENABLE_SHIFT)
+#define MC_CLIENT_CTRL_0_DCB_ENABLE_RANGE                       2:2
+#define MC_CLIENT_CTRL_0_DCB_ENABLE_WOFFSET                     0x0
+#define MC_CLIENT_CTRL_0_DCB_ENABLE_DEFAULT                     _MK_MASK_CONST(0x1)
+#define MC_CLIENT_CTRL_0_DCB_ENABLE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_CLIENT_CTRL_0_DCB_ENABLE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_DCB_ENABLE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_DCB_ENABLE_INIT_ENUM                   ENABLE
+#define MC_CLIENT_CTRL_0_DCB_ENABLE_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_CLIENT_CTRL_0_DCB_ENABLE_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_CLIENT_CTRL_0_DCB_ENABLE_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_CLIENT_CTRL_0_DCB_ENABLE_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_CTRL_0_EPP_ENABLE_SHIFT                       _MK_SHIFT_CONST(3)
+#define MC_CLIENT_CTRL_0_EPP_ENABLE_FIELD                       (_MK_MASK_CONST(0x1) << MC_CLIENT_CTRL_0_EPP_ENABLE_SHIFT)
+#define MC_CLIENT_CTRL_0_EPP_ENABLE_RANGE                       3:3
+#define MC_CLIENT_CTRL_0_EPP_ENABLE_WOFFSET                     0x0
+#define MC_CLIENT_CTRL_0_EPP_ENABLE_DEFAULT                     _MK_MASK_CONST(0x1)
+#define MC_CLIENT_CTRL_0_EPP_ENABLE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_CLIENT_CTRL_0_EPP_ENABLE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_EPP_ENABLE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_EPP_ENABLE_INIT_ENUM                   ENABLE
+#define MC_CLIENT_CTRL_0_EPP_ENABLE_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_CLIENT_CTRL_0_EPP_ENABLE_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_CLIENT_CTRL_0_EPP_ENABLE_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_CLIENT_CTRL_0_EPP_ENABLE_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_CTRL_0_G2_ENABLE_SHIFT                        _MK_SHIFT_CONST(4)
+#define MC_CLIENT_CTRL_0_G2_ENABLE_FIELD                        (_MK_MASK_CONST(0x1) << MC_CLIENT_CTRL_0_G2_ENABLE_SHIFT)
+#define MC_CLIENT_CTRL_0_G2_ENABLE_RANGE                        4:4
+#define MC_CLIENT_CTRL_0_G2_ENABLE_WOFFSET                      0x0
+#define MC_CLIENT_CTRL_0_G2_ENABLE_DEFAULT                      _MK_MASK_CONST(0x1)
+#define MC_CLIENT_CTRL_0_G2_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_CLIENT_CTRL_0_G2_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_G2_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_G2_ENABLE_INIT_ENUM                    ENABLE
+#define MC_CLIENT_CTRL_0_G2_ENABLE_DISABLE                      _MK_ENUM_CONST(0)
+#define MC_CLIENT_CTRL_0_G2_ENABLE_ENABLE                       _MK_ENUM_CONST(1)
+#define MC_CLIENT_CTRL_0_G2_ENABLE_DISABLED                     _MK_ENUM_CONST(0)
+#define MC_CLIENT_CTRL_0_G2_ENABLE_ENABLED                      _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_CTRL_0_HC_ENABLE_SHIFT                        _MK_SHIFT_CONST(5)
+#define MC_CLIENT_CTRL_0_HC_ENABLE_FIELD                        (_MK_MASK_CONST(0x1) << MC_CLIENT_CTRL_0_HC_ENABLE_SHIFT)
+#define MC_CLIENT_CTRL_0_HC_ENABLE_RANGE                        5:5
+#define MC_CLIENT_CTRL_0_HC_ENABLE_WOFFSET                      0x0
+#define MC_CLIENT_CTRL_0_HC_ENABLE_DEFAULT                      _MK_MASK_CONST(0x1)
+#define MC_CLIENT_CTRL_0_HC_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_CLIENT_CTRL_0_HC_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_HC_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_HC_ENABLE_INIT_ENUM                    ENABLE
+#define MC_CLIENT_CTRL_0_HC_ENABLE_DISABLE                      _MK_ENUM_CONST(0)
+#define MC_CLIENT_CTRL_0_HC_ENABLE_ENABLE                       _MK_ENUM_CONST(1)
+#define MC_CLIENT_CTRL_0_HC_ENABLE_DISABLED                     _MK_ENUM_CONST(0)
+#define MC_CLIENT_CTRL_0_HC_ENABLE_ENABLED                      _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_CTRL_0_ISP_ENABLE_SHIFT                       _MK_SHIFT_CONST(6)
+#define MC_CLIENT_CTRL_0_ISP_ENABLE_FIELD                       (_MK_MASK_CONST(0x1) << MC_CLIENT_CTRL_0_ISP_ENABLE_SHIFT)
+#define MC_CLIENT_CTRL_0_ISP_ENABLE_RANGE                       6:6
+#define MC_CLIENT_CTRL_0_ISP_ENABLE_WOFFSET                     0x0
+#define MC_CLIENT_CTRL_0_ISP_ENABLE_DEFAULT                     _MK_MASK_CONST(0x1)
+#define MC_CLIENT_CTRL_0_ISP_ENABLE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_CLIENT_CTRL_0_ISP_ENABLE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_ISP_ENABLE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_ISP_ENABLE_INIT_ENUM                   ENABLE
+#define MC_CLIENT_CTRL_0_ISP_ENABLE_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_CLIENT_CTRL_0_ISP_ENABLE_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_CLIENT_CTRL_0_ISP_ENABLE_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_CLIENT_CTRL_0_ISP_ENABLE_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_CTRL_0_MPCORE_ENABLE_SHIFT                    _MK_SHIFT_CONST(7)
+#define MC_CLIENT_CTRL_0_MPCORE_ENABLE_FIELD                    (_MK_MASK_CONST(0x1) << MC_CLIENT_CTRL_0_MPCORE_ENABLE_SHIFT)
+#define MC_CLIENT_CTRL_0_MPCORE_ENABLE_RANGE                    7:7
+#define MC_CLIENT_CTRL_0_MPCORE_ENABLE_WOFFSET                  0x0
+#define MC_CLIENT_CTRL_0_MPCORE_ENABLE_DEFAULT                  _MK_MASK_CONST(0x1)
+#define MC_CLIENT_CTRL_0_MPCORE_ENABLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_CLIENT_CTRL_0_MPCORE_ENABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_MPCORE_ENABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_MPCORE_ENABLE_INIT_ENUM                        ENABLE
+#define MC_CLIENT_CTRL_0_MPCORE_ENABLE_DISABLE                  _MK_ENUM_CONST(0)
+#define MC_CLIENT_CTRL_0_MPCORE_ENABLE_ENABLE                   _MK_ENUM_CONST(1)
+#define MC_CLIENT_CTRL_0_MPCORE_ENABLE_DISABLED                 _MK_ENUM_CONST(0)
+#define MC_CLIENT_CTRL_0_MPCORE_ENABLE_ENABLED                  _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_CTRL_0_MPEA_ENABLE_SHIFT                      _MK_SHIFT_CONST(8)
+#define MC_CLIENT_CTRL_0_MPEA_ENABLE_FIELD                      (_MK_MASK_CONST(0x1) << MC_CLIENT_CTRL_0_MPEA_ENABLE_SHIFT)
+#define MC_CLIENT_CTRL_0_MPEA_ENABLE_RANGE                      8:8
+#define MC_CLIENT_CTRL_0_MPEA_ENABLE_WOFFSET                    0x0
+#define MC_CLIENT_CTRL_0_MPEA_ENABLE_DEFAULT                    _MK_MASK_CONST(0x1)
+#define MC_CLIENT_CTRL_0_MPEA_ENABLE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_CLIENT_CTRL_0_MPEA_ENABLE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_MPEA_ENABLE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_MPEA_ENABLE_INIT_ENUM                  ENABLE
+#define MC_CLIENT_CTRL_0_MPEA_ENABLE_DISABLE                    _MK_ENUM_CONST(0)
+#define MC_CLIENT_CTRL_0_MPEA_ENABLE_ENABLE                     _MK_ENUM_CONST(1)
+#define MC_CLIENT_CTRL_0_MPEA_ENABLE_DISABLED                   _MK_ENUM_CONST(0)
+#define MC_CLIENT_CTRL_0_MPEA_ENABLE_ENABLED                    _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_CTRL_0_MPEB_ENABLE_SHIFT                      _MK_SHIFT_CONST(9)
+#define MC_CLIENT_CTRL_0_MPEB_ENABLE_FIELD                      (_MK_MASK_CONST(0x1) << MC_CLIENT_CTRL_0_MPEB_ENABLE_SHIFT)
+#define MC_CLIENT_CTRL_0_MPEB_ENABLE_RANGE                      9:9
+#define MC_CLIENT_CTRL_0_MPEB_ENABLE_WOFFSET                    0x0
+#define MC_CLIENT_CTRL_0_MPEB_ENABLE_DEFAULT                    _MK_MASK_CONST(0x1)
+#define MC_CLIENT_CTRL_0_MPEB_ENABLE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_CLIENT_CTRL_0_MPEB_ENABLE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_MPEB_ENABLE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_MPEB_ENABLE_INIT_ENUM                  ENABLE
+#define MC_CLIENT_CTRL_0_MPEB_ENABLE_DISABLE                    _MK_ENUM_CONST(0)
+#define MC_CLIENT_CTRL_0_MPEB_ENABLE_ENABLE                     _MK_ENUM_CONST(1)
+#define MC_CLIENT_CTRL_0_MPEB_ENABLE_DISABLED                   _MK_ENUM_CONST(0)
+#define MC_CLIENT_CTRL_0_MPEB_ENABLE_ENABLED                    _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_CTRL_0_MPEC_ENABLE_SHIFT                      _MK_SHIFT_CONST(10)
+#define MC_CLIENT_CTRL_0_MPEC_ENABLE_FIELD                      (_MK_MASK_CONST(0x1) << MC_CLIENT_CTRL_0_MPEC_ENABLE_SHIFT)
+#define MC_CLIENT_CTRL_0_MPEC_ENABLE_RANGE                      10:10
+#define MC_CLIENT_CTRL_0_MPEC_ENABLE_WOFFSET                    0x0
+#define MC_CLIENT_CTRL_0_MPEC_ENABLE_DEFAULT                    _MK_MASK_CONST(0x1)
+#define MC_CLIENT_CTRL_0_MPEC_ENABLE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_CLIENT_CTRL_0_MPEC_ENABLE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_MPEC_ENABLE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_MPEC_ENABLE_INIT_ENUM                  ENABLE
+#define MC_CLIENT_CTRL_0_MPEC_ENABLE_DISABLE                    _MK_ENUM_CONST(0)
+#define MC_CLIENT_CTRL_0_MPEC_ENABLE_ENABLE                     _MK_ENUM_CONST(1)
+#define MC_CLIENT_CTRL_0_MPEC_ENABLE_DISABLED                   _MK_ENUM_CONST(0)
+#define MC_CLIENT_CTRL_0_MPEC_ENABLE_ENABLED                    _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_CTRL_0_NV_ENABLE_SHIFT                        _MK_SHIFT_CONST(11)
+#define MC_CLIENT_CTRL_0_NV_ENABLE_FIELD                        (_MK_MASK_CONST(0x1) << MC_CLIENT_CTRL_0_NV_ENABLE_SHIFT)
+#define MC_CLIENT_CTRL_0_NV_ENABLE_RANGE                        11:11
+#define MC_CLIENT_CTRL_0_NV_ENABLE_WOFFSET                      0x0
+#define MC_CLIENT_CTRL_0_NV_ENABLE_DEFAULT                      _MK_MASK_CONST(0x1)
+#define MC_CLIENT_CTRL_0_NV_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_CLIENT_CTRL_0_NV_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_NV_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_NV_ENABLE_INIT_ENUM                    ENABLE
+#define MC_CLIENT_CTRL_0_NV_ENABLE_DISABLE                      _MK_ENUM_CONST(0)
+#define MC_CLIENT_CTRL_0_NV_ENABLE_ENABLE                       _MK_ENUM_CONST(1)
+#define MC_CLIENT_CTRL_0_NV_ENABLE_DISABLED                     _MK_ENUM_CONST(0)
+#define MC_CLIENT_CTRL_0_NV_ENABLE_ENABLED                      _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_CTRL_0_PPCS_ENABLE_SHIFT                      _MK_SHIFT_CONST(12)
+#define MC_CLIENT_CTRL_0_PPCS_ENABLE_FIELD                      (_MK_MASK_CONST(0x1) << MC_CLIENT_CTRL_0_PPCS_ENABLE_SHIFT)
+#define MC_CLIENT_CTRL_0_PPCS_ENABLE_RANGE                      12:12
+#define MC_CLIENT_CTRL_0_PPCS_ENABLE_WOFFSET                    0x0
+#define MC_CLIENT_CTRL_0_PPCS_ENABLE_DEFAULT                    _MK_MASK_CONST(0x1)
+#define MC_CLIENT_CTRL_0_PPCS_ENABLE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_CLIENT_CTRL_0_PPCS_ENABLE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_PPCS_ENABLE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_PPCS_ENABLE_INIT_ENUM                  ENABLE
+#define MC_CLIENT_CTRL_0_PPCS_ENABLE_DISABLE                    _MK_ENUM_CONST(0)
+#define MC_CLIENT_CTRL_0_PPCS_ENABLE_ENABLE                     _MK_ENUM_CONST(1)
+#define MC_CLIENT_CTRL_0_PPCS_ENABLE_DISABLED                   _MK_ENUM_CONST(0)
+#define MC_CLIENT_CTRL_0_PPCS_ENABLE_ENABLED                    _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_CTRL_0_VDE_ENABLE_SHIFT                       _MK_SHIFT_CONST(13)
+#define MC_CLIENT_CTRL_0_VDE_ENABLE_FIELD                       (_MK_MASK_CONST(0x1) << MC_CLIENT_CTRL_0_VDE_ENABLE_SHIFT)
+#define MC_CLIENT_CTRL_0_VDE_ENABLE_RANGE                       13:13
+#define MC_CLIENT_CTRL_0_VDE_ENABLE_WOFFSET                     0x0
+#define MC_CLIENT_CTRL_0_VDE_ENABLE_DEFAULT                     _MK_MASK_CONST(0x1)
+#define MC_CLIENT_CTRL_0_VDE_ENABLE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_CLIENT_CTRL_0_VDE_ENABLE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_VDE_ENABLE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_VDE_ENABLE_INIT_ENUM                   ENABLE
+#define MC_CLIENT_CTRL_0_VDE_ENABLE_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_CLIENT_CTRL_0_VDE_ENABLE_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_CLIENT_CTRL_0_VDE_ENABLE_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_CLIENT_CTRL_0_VDE_ENABLE_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_CTRL_0_VI_ENABLE_SHIFT                        _MK_SHIFT_CONST(14)
+#define MC_CLIENT_CTRL_0_VI_ENABLE_FIELD                        (_MK_MASK_CONST(0x1) << MC_CLIENT_CTRL_0_VI_ENABLE_SHIFT)
+#define MC_CLIENT_CTRL_0_VI_ENABLE_RANGE                        14:14
+#define MC_CLIENT_CTRL_0_VI_ENABLE_WOFFSET                      0x0
+#define MC_CLIENT_CTRL_0_VI_ENABLE_DEFAULT                      _MK_MASK_CONST(0x1)
+#define MC_CLIENT_CTRL_0_VI_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_CLIENT_CTRL_0_VI_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_VI_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_VI_ENABLE_INIT_ENUM                    ENABLE
+#define MC_CLIENT_CTRL_0_VI_ENABLE_DISABLE                      _MK_ENUM_CONST(0)
+#define MC_CLIENT_CTRL_0_VI_ENABLE_ENABLE                       _MK_ENUM_CONST(1)
+#define MC_CLIENT_CTRL_0_VI_ENABLE_DISABLED                     _MK_ENUM_CONST(0)
+#define MC_CLIENT_CTRL_0_VI_ENABLE_ENABLED                      _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_HOTRESETN_DISABLE     1
+#define MC_CLIENT_HOTRESETN_ENABLE      0
+
+// Register MC_CLIENT_HOTRESETN_0  
+#define MC_CLIENT_HOTRESETN_0                   _MK_ADDR_CONST(0xa0)
+#define MC_CLIENT_HOTRESETN_0_WORD_COUNT                        0x1
+#define MC_CLIENT_HOTRESETN_0_RESET_VAL                         _MK_MASK_CONST(0x7fff)
+#define MC_CLIENT_HOTRESETN_0_RESET_MASK                        _MK_MASK_CONST(0x7fff)
+#define MC_CLIENT_HOTRESETN_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_READ_MASK                         _MK_MASK_CONST(0x7fff)
+#define MC_CLIENT_HOTRESETN_0_WRITE_MASK                        _MK_MASK_CONST(0x7fff)
+#define MC_CLIENT_HOTRESETN_0_CMC_HOTRESETN_SHIFT                       _MK_SHIFT_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_CMC_HOTRESETN_FIELD                       (_MK_MASK_CONST(0x1) << MC_CLIENT_HOTRESETN_0_CMC_HOTRESETN_SHIFT)
+#define MC_CLIENT_HOTRESETN_0_CMC_HOTRESETN_RANGE                       0:0
+#define MC_CLIENT_HOTRESETN_0_CMC_HOTRESETN_WOFFSET                     0x0
+#define MC_CLIENT_HOTRESETN_0_CMC_HOTRESETN_DEFAULT                     _MK_MASK_CONST(0x1)
+#define MC_CLIENT_HOTRESETN_0_CMC_HOTRESETN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_CLIENT_HOTRESETN_0_CMC_HOTRESETN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_CMC_HOTRESETN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_CMC_HOTRESETN_INIT_ENUM                   DISABLE
+#define MC_CLIENT_HOTRESETN_0_CMC_HOTRESETN_ENABLE                      _MK_ENUM_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_CMC_HOTRESETN_DISABLE                     _MK_ENUM_CONST(1)
+#define MC_CLIENT_HOTRESETN_0_CMC_HOTRESETN_ENABLED                     _MK_ENUM_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_CMC_HOTRESETN_DISABLED                    _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_HOTRESETN_0_DC_HOTRESETN_SHIFT                        _MK_SHIFT_CONST(1)
+#define MC_CLIENT_HOTRESETN_0_DC_HOTRESETN_FIELD                        (_MK_MASK_CONST(0x1) << MC_CLIENT_HOTRESETN_0_DC_HOTRESETN_SHIFT)
+#define MC_CLIENT_HOTRESETN_0_DC_HOTRESETN_RANGE                        1:1
+#define MC_CLIENT_HOTRESETN_0_DC_HOTRESETN_WOFFSET                      0x0
+#define MC_CLIENT_HOTRESETN_0_DC_HOTRESETN_DEFAULT                      _MK_MASK_CONST(0x1)
+#define MC_CLIENT_HOTRESETN_0_DC_HOTRESETN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_CLIENT_HOTRESETN_0_DC_HOTRESETN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_DC_HOTRESETN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_DC_HOTRESETN_INIT_ENUM                    DISABLE
+#define MC_CLIENT_HOTRESETN_0_DC_HOTRESETN_ENABLE                       _MK_ENUM_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_DC_HOTRESETN_DISABLE                      _MK_ENUM_CONST(1)
+#define MC_CLIENT_HOTRESETN_0_DC_HOTRESETN_ENABLED                      _MK_ENUM_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_DC_HOTRESETN_DISABLED                     _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_HOTRESETN_0_DCB_HOTRESETN_SHIFT                       _MK_SHIFT_CONST(2)
+#define MC_CLIENT_HOTRESETN_0_DCB_HOTRESETN_FIELD                       (_MK_MASK_CONST(0x1) << MC_CLIENT_HOTRESETN_0_DCB_HOTRESETN_SHIFT)
+#define MC_CLIENT_HOTRESETN_0_DCB_HOTRESETN_RANGE                       2:2
+#define MC_CLIENT_HOTRESETN_0_DCB_HOTRESETN_WOFFSET                     0x0
+#define MC_CLIENT_HOTRESETN_0_DCB_HOTRESETN_DEFAULT                     _MK_MASK_CONST(0x1)
+#define MC_CLIENT_HOTRESETN_0_DCB_HOTRESETN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_CLIENT_HOTRESETN_0_DCB_HOTRESETN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_DCB_HOTRESETN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_DCB_HOTRESETN_INIT_ENUM                   DISABLE
+#define MC_CLIENT_HOTRESETN_0_DCB_HOTRESETN_ENABLE                      _MK_ENUM_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_DCB_HOTRESETN_DISABLE                     _MK_ENUM_CONST(1)
+#define MC_CLIENT_HOTRESETN_0_DCB_HOTRESETN_ENABLED                     _MK_ENUM_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_DCB_HOTRESETN_DISABLED                    _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_HOTRESETN_0_EPP_HOTRESETN_SHIFT                       _MK_SHIFT_CONST(3)
+#define MC_CLIENT_HOTRESETN_0_EPP_HOTRESETN_FIELD                       (_MK_MASK_CONST(0x1) << MC_CLIENT_HOTRESETN_0_EPP_HOTRESETN_SHIFT)
+#define MC_CLIENT_HOTRESETN_0_EPP_HOTRESETN_RANGE                       3:3
+#define MC_CLIENT_HOTRESETN_0_EPP_HOTRESETN_WOFFSET                     0x0
+#define MC_CLIENT_HOTRESETN_0_EPP_HOTRESETN_DEFAULT                     _MK_MASK_CONST(0x1)
+#define MC_CLIENT_HOTRESETN_0_EPP_HOTRESETN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_CLIENT_HOTRESETN_0_EPP_HOTRESETN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_EPP_HOTRESETN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_EPP_HOTRESETN_INIT_ENUM                   DISABLE
+#define MC_CLIENT_HOTRESETN_0_EPP_HOTRESETN_ENABLE                      _MK_ENUM_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_EPP_HOTRESETN_DISABLE                     _MK_ENUM_CONST(1)
+#define MC_CLIENT_HOTRESETN_0_EPP_HOTRESETN_ENABLED                     _MK_ENUM_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_EPP_HOTRESETN_DISABLED                    _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_HOTRESETN_0_G2_HOTRESETN_SHIFT                        _MK_SHIFT_CONST(4)
+#define MC_CLIENT_HOTRESETN_0_G2_HOTRESETN_FIELD                        (_MK_MASK_CONST(0x1) << MC_CLIENT_HOTRESETN_0_G2_HOTRESETN_SHIFT)
+#define MC_CLIENT_HOTRESETN_0_G2_HOTRESETN_RANGE                        4:4
+#define MC_CLIENT_HOTRESETN_0_G2_HOTRESETN_WOFFSET                      0x0
+#define MC_CLIENT_HOTRESETN_0_G2_HOTRESETN_DEFAULT                      _MK_MASK_CONST(0x1)
+#define MC_CLIENT_HOTRESETN_0_G2_HOTRESETN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_CLIENT_HOTRESETN_0_G2_HOTRESETN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_G2_HOTRESETN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_G2_HOTRESETN_INIT_ENUM                    DISABLE
+#define MC_CLIENT_HOTRESETN_0_G2_HOTRESETN_ENABLE                       _MK_ENUM_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_G2_HOTRESETN_DISABLE                      _MK_ENUM_CONST(1)
+#define MC_CLIENT_HOTRESETN_0_G2_HOTRESETN_ENABLED                      _MK_ENUM_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_G2_HOTRESETN_DISABLED                     _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_HOTRESETN_0_HC_HOTRESETN_SHIFT                        _MK_SHIFT_CONST(5)
+#define MC_CLIENT_HOTRESETN_0_HC_HOTRESETN_FIELD                        (_MK_MASK_CONST(0x1) << MC_CLIENT_HOTRESETN_0_HC_HOTRESETN_SHIFT)
+#define MC_CLIENT_HOTRESETN_0_HC_HOTRESETN_RANGE                        5:5
+#define MC_CLIENT_HOTRESETN_0_HC_HOTRESETN_WOFFSET                      0x0
+#define MC_CLIENT_HOTRESETN_0_HC_HOTRESETN_DEFAULT                      _MK_MASK_CONST(0x1)
+#define MC_CLIENT_HOTRESETN_0_HC_HOTRESETN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_CLIENT_HOTRESETN_0_HC_HOTRESETN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_HC_HOTRESETN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_HC_HOTRESETN_INIT_ENUM                    DISABLE
+#define MC_CLIENT_HOTRESETN_0_HC_HOTRESETN_ENABLE                       _MK_ENUM_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_HC_HOTRESETN_DISABLE                      _MK_ENUM_CONST(1)
+#define MC_CLIENT_HOTRESETN_0_HC_HOTRESETN_ENABLED                      _MK_ENUM_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_HC_HOTRESETN_DISABLED                     _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_HOTRESETN_0_ISP_HOTRESETN_SHIFT                       _MK_SHIFT_CONST(6)
+#define MC_CLIENT_HOTRESETN_0_ISP_HOTRESETN_FIELD                       (_MK_MASK_CONST(0x1) << MC_CLIENT_HOTRESETN_0_ISP_HOTRESETN_SHIFT)
+#define MC_CLIENT_HOTRESETN_0_ISP_HOTRESETN_RANGE                       6:6
+#define MC_CLIENT_HOTRESETN_0_ISP_HOTRESETN_WOFFSET                     0x0
+#define MC_CLIENT_HOTRESETN_0_ISP_HOTRESETN_DEFAULT                     _MK_MASK_CONST(0x1)
+#define MC_CLIENT_HOTRESETN_0_ISP_HOTRESETN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_CLIENT_HOTRESETN_0_ISP_HOTRESETN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_ISP_HOTRESETN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_ISP_HOTRESETN_INIT_ENUM                   DISABLE
+#define MC_CLIENT_HOTRESETN_0_ISP_HOTRESETN_ENABLE                      _MK_ENUM_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_ISP_HOTRESETN_DISABLE                     _MK_ENUM_CONST(1)
+#define MC_CLIENT_HOTRESETN_0_ISP_HOTRESETN_ENABLED                     _MK_ENUM_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_ISP_HOTRESETN_DISABLED                    _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_HOTRESETN_0_MPCORE_HOTRESETN_SHIFT                    _MK_SHIFT_CONST(7)
+#define MC_CLIENT_HOTRESETN_0_MPCORE_HOTRESETN_FIELD                    (_MK_MASK_CONST(0x1) << MC_CLIENT_HOTRESETN_0_MPCORE_HOTRESETN_SHIFT)
+#define MC_CLIENT_HOTRESETN_0_MPCORE_HOTRESETN_RANGE                    7:7
+#define MC_CLIENT_HOTRESETN_0_MPCORE_HOTRESETN_WOFFSET                  0x0
+#define MC_CLIENT_HOTRESETN_0_MPCORE_HOTRESETN_DEFAULT                  _MK_MASK_CONST(0x1)
+#define MC_CLIENT_HOTRESETN_0_MPCORE_HOTRESETN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_CLIENT_HOTRESETN_0_MPCORE_HOTRESETN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_MPCORE_HOTRESETN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_MPCORE_HOTRESETN_INIT_ENUM                        DISABLE
+#define MC_CLIENT_HOTRESETN_0_MPCORE_HOTRESETN_ENABLE                   _MK_ENUM_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_MPCORE_HOTRESETN_DISABLE                  _MK_ENUM_CONST(1)
+#define MC_CLIENT_HOTRESETN_0_MPCORE_HOTRESETN_ENABLED                  _MK_ENUM_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_MPCORE_HOTRESETN_DISABLED                 _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_HOTRESETN_0_MPEA_HOTRESETN_SHIFT                      _MK_SHIFT_CONST(8)
+#define MC_CLIENT_HOTRESETN_0_MPEA_HOTRESETN_FIELD                      (_MK_MASK_CONST(0x1) << MC_CLIENT_HOTRESETN_0_MPEA_HOTRESETN_SHIFT)
+#define MC_CLIENT_HOTRESETN_0_MPEA_HOTRESETN_RANGE                      8:8
+#define MC_CLIENT_HOTRESETN_0_MPEA_HOTRESETN_WOFFSET                    0x0
+#define MC_CLIENT_HOTRESETN_0_MPEA_HOTRESETN_DEFAULT                    _MK_MASK_CONST(0x1)
+#define MC_CLIENT_HOTRESETN_0_MPEA_HOTRESETN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_CLIENT_HOTRESETN_0_MPEA_HOTRESETN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_MPEA_HOTRESETN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_MPEA_HOTRESETN_INIT_ENUM                  DISABLE
+#define MC_CLIENT_HOTRESETN_0_MPEA_HOTRESETN_ENABLE                     _MK_ENUM_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_MPEA_HOTRESETN_DISABLE                    _MK_ENUM_CONST(1)
+#define MC_CLIENT_HOTRESETN_0_MPEA_HOTRESETN_ENABLED                    _MK_ENUM_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_MPEA_HOTRESETN_DISABLED                   _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_HOTRESETN_0_MPEB_HOTRESETN_SHIFT                      _MK_SHIFT_CONST(9)
+#define MC_CLIENT_HOTRESETN_0_MPEB_HOTRESETN_FIELD                      (_MK_MASK_CONST(0x1) << MC_CLIENT_HOTRESETN_0_MPEB_HOTRESETN_SHIFT)
+#define MC_CLIENT_HOTRESETN_0_MPEB_HOTRESETN_RANGE                      9:9
+#define MC_CLIENT_HOTRESETN_0_MPEB_HOTRESETN_WOFFSET                    0x0
+#define MC_CLIENT_HOTRESETN_0_MPEB_HOTRESETN_DEFAULT                    _MK_MASK_CONST(0x1)
+#define MC_CLIENT_HOTRESETN_0_MPEB_HOTRESETN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_CLIENT_HOTRESETN_0_MPEB_HOTRESETN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_MPEB_HOTRESETN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_MPEB_HOTRESETN_INIT_ENUM                  DISABLE
+#define MC_CLIENT_HOTRESETN_0_MPEB_HOTRESETN_ENABLE                     _MK_ENUM_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_MPEB_HOTRESETN_DISABLE                    _MK_ENUM_CONST(1)
+#define MC_CLIENT_HOTRESETN_0_MPEB_HOTRESETN_ENABLED                    _MK_ENUM_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_MPEB_HOTRESETN_DISABLED                   _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_HOTRESETN_0_MPEC_HOTRESETN_SHIFT                      _MK_SHIFT_CONST(10)
+#define MC_CLIENT_HOTRESETN_0_MPEC_HOTRESETN_FIELD                      (_MK_MASK_CONST(0x1) << MC_CLIENT_HOTRESETN_0_MPEC_HOTRESETN_SHIFT)
+#define MC_CLIENT_HOTRESETN_0_MPEC_HOTRESETN_RANGE                      10:10
+#define MC_CLIENT_HOTRESETN_0_MPEC_HOTRESETN_WOFFSET                    0x0
+#define MC_CLIENT_HOTRESETN_0_MPEC_HOTRESETN_DEFAULT                    _MK_MASK_CONST(0x1)
+#define MC_CLIENT_HOTRESETN_0_MPEC_HOTRESETN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_CLIENT_HOTRESETN_0_MPEC_HOTRESETN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_MPEC_HOTRESETN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_MPEC_HOTRESETN_INIT_ENUM                  DISABLE
+#define MC_CLIENT_HOTRESETN_0_MPEC_HOTRESETN_ENABLE                     _MK_ENUM_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_MPEC_HOTRESETN_DISABLE                    _MK_ENUM_CONST(1)
+#define MC_CLIENT_HOTRESETN_0_MPEC_HOTRESETN_ENABLED                    _MK_ENUM_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_MPEC_HOTRESETN_DISABLED                   _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_HOTRESETN_0_NV_HOTRESETN_SHIFT                        _MK_SHIFT_CONST(11)
+#define MC_CLIENT_HOTRESETN_0_NV_HOTRESETN_FIELD                        (_MK_MASK_CONST(0x1) << MC_CLIENT_HOTRESETN_0_NV_HOTRESETN_SHIFT)
+#define MC_CLIENT_HOTRESETN_0_NV_HOTRESETN_RANGE                        11:11
+#define MC_CLIENT_HOTRESETN_0_NV_HOTRESETN_WOFFSET                      0x0
+#define MC_CLIENT_HOTRESETN_0_NV_HOTRESETN_DEFAULT                      _MK_MASK_CONST(0x1)
+#define MC_CLIENT_HOTRESETN_0_NV_HOTRESETN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_CLIENT_HOTRESETN_0_NV_HOTRESETN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_NV_HOTRESETN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_NV_HOTRESETN_INIT_ENUM                    DISABLE
+#define MC_CLIENT_HOTRESETN_0_NV_HOTRESETN_ENABLE                       _MK_ENUM_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_NV_HOTRESETN_DISABLE                      _MK_ENUM_CONST(1)
+#define MC_CLIENT_HOTRESETN_0_NV_HOTRESETN_ENABLED                      _MK_ENUM_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_NV_HOTRESETN_DISABLED                     _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_HOTRESETN_0_PPCS_HOTRESETN_SHIFT                      _MK_SHIFT_CONST(12)
+#define MC_CLIENT_HOTRESETN_0_PPCS_HOTRESETN_FIELD                      (_MK_MASK_CONST(0x1) << MC_CLIENT_HOTRESETN_0_PPCS_HOTRESETN_SHIFT)
+#define MC_CLIENT_HOTRESETN_0_PPCS_HOTRESETN_RANGE                      12:12
+#define MC_CLIENT_HOTRESETN_0_PPCS_HOTRESETN_WOFFSET                    0x0
+#define MC_CLIENT_HOTRESETN_0_PPCS_HOTRESETN_DEFAULT                    _MK_MASK_CONST(0x1)
+#define MC_CLIENT_HOTRESETN_0_PPCS_HOTRESETN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_CLIENT_HOTRESETN_0_PPCS_HOTRESETN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_PPCS_HOTRESETN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_PPCS_HOTRESETN_INIT_ENUM                  DISABLE
+#define MC_CLIENT_HOTRESETN_0_PPCS_HOTRESETN_ENABLE                     _MK_ENUM_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_PPCS_HOTRESETN_DISABLE                    _MK_ENUM_CONST(1)
+#define MC_CLIENT_HOTRESETN_0_PPCS_HOTRESETN_ENABLED                    _MK_ENUM_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_PPCS_HOTRESETN_DISABLED                   _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_HOTRESETN_0_VDE_HOTRESETN_SHIFT                       _MK_SHIFT_CONST(13)
+#define MC_CLIENT_HOTRESETN_0_VDE_HOTRESETN_FIELD                       (_MK_MASK_CONST(0x1) << MC_CLIENT_HOTRESETN_0_VDE_HOTRESETN_SHIFT)
+#define MC_CLIENT_HOTRESETN_0_VDE_HOTRESETN_RANGE                       13:13
+#define MC_CLIENT_HOTRESETN_0_VDE_HOTRESETN_WOFFSET                     0x0
+#define MC_CLIENT_HOTRESETN_0_VDE_HOTRESETN_DEFAULT                     _MK_MASK_CONST(0x1)
+#define MC_CLIENT_HOTRESETN_0_VDE_HOTRESETN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_CLIENT_HOTRESETN_0_VDE_HOTRESETN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_VDE_HOTRESETN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_VDE_HOTRESETN_INIT_ENUM                   DISABLE
+#define MC_CLIENT_HOTRESETN_0_VDE_HOTRESETN_ENABLE                      _MK_ENUM_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_VDE_HOTRESETN_DISABLE                     _MK_ENUM_CONST(1)
+#define MC_CLIENT_HOTRESETN_0_VDE_HOTRESETN_ENABLED                     _MK_ENUM_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_VDE_HOTRESETN_DISABLED                    _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_HOTRESETN_0_VI_HOTRESETN_SHIFT                        _MK_SHIFT_CONST(14)
+#define MC_CLIENT_HOTRESETN_0_VI_HOTRESETN_FIELD                        (_MK_MASK_CONST(0x1) << MC_CLIENT_HOTRESETN_0_VI_HOTRESETN_SHIFT)
+#define MC_CLIENT_HOTRESETN_0_VI_HOTRESETN_RANGE                        14:14
+#define MC_CLIENT_HOTRESETN_0_VI_HOTRESETN_WOFFSET                      0x0
+#define MC_CLIENT_HOTRESETN_0_VI_HOTRESETN_DEFAULT                      _MK_MASK_CONST(0x1)
+#define MC_CLIENT_HOTRESETN_0_VI_HOTRESETN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_CLIENT_HOTRESETN_0_VI_HOTRESETN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_VI_HOTRESETN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_VI_HOTRESETN_INIT_ENUM                    DISABLE
+#define MC_CLIENT_HOTRESETN_0_VI_HOTRESETN_ENABLE                       _MK_ENUM_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_VI_HOTRESETN_DISABLE                      _MK_ENUM_CONST(1)
+#define MC_CLIENT_HOTRESETN_0_VI_HOTRESETN_ENABLED                      _MK_ENUM_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_VI_HOTRESETN_DISABLED                     _MK_ENUM_CONST(1)
+
+
+// Register MC_CMC_ORRC_0  
+#define MC_CMC_ORRC_0                   _MK_ADDR_CONST(0xa4)
+#define MC_CMC_ORRC_0_WORD_COUNT                        0x1
+#define MC_CMC_ORRC_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define MC_CMC_ORRC_0_RESET_MASK                        _MK_MASK_CONST(0xff)
+#define MC_CMC_ORRC_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define MC_CMC_ORRC_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_CMC_ORRC_0_READ_MASK                         _MK_MASK_CONST(0xff)
+#define MC_CMC_ORRC_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+#define MC_CMC_ORRC_0_CMC_OUTREQCNT_SHIFT                       _MK_SHIFT_CONST(0)
+#define MC_CMC_ORRC_0_CMC_OUTREQCNT_FIELD                       (_MK_MASK_CONST(0xff) << MC_CMC_ORRC_0_CMC_OUTREQCNT_SHIFT)
+#define MC_CMC_ORRC_0_CMC_OUTREQCNT_RANGE                       7:0
+#define MC_CMC_ORRC_0_CMC_OUTREQCNT_WOFFSET                     0x0
+#define MC_CMC_ORRC_0_CMC_OUTREQCNT_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_CMC_ORRC_0_CMC_OUTREQCNT_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define MC_CMC_ORRC_0_CMC_OUTREQCNT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CMC_ORRC_0_CMC_OUTREQCNT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register MC_DC_ORRC_0  
+#define MC_DC_ORRC_0                    _MK_ADDR_CONST(0xa8)
+#define MC_DC_ORRC_0_WORD_COUNT                         0x1
+#define MC_DC_ORRC_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define MC_DC_ORRC_0_RESET_MASK                         _MK_MASK_CONST(0xff)
+#define MC_DC_ORRC_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define MC_DC_ORRC_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_DC_ORRC_0_READ_MASK                  _MK_MASK_CONST(0xff)
+#define MC_DC_ORRC_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
+#define MC_DC_ORRC_0_DC_OUTREQCNT_SHIFT                 _MK_SHIFT_CONST(0)
+#define MC_DC_ORRC_0_DC_OUTREQCNT_FIELD                 (_MK_MASK_CONST(0xff) << MC_DC_ORRC_0_DC_OUTREQCNT_SHIFT)
+#define MC_DC_ORRC_0_DC_OUTREQCNT_RANGE                 7:0
+#define MC_DC_ORRC_0_DC_OUTREQCNT_WOFFSET                       0x0
+#define MC_DC_ORRC_0_DC_OUTREQCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_DC_ORRC_0_DC_OUTREQCNT_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define MC_DC_ORRC_0_DC_OUTREQCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_DC_ORRC_0_DC_OUTREQCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register MC_DCB_ORRC_0  
+#define MC_DCB_ORRC_0                   _MK_ADDR_CONST(0xac)
+#define MC_DCB_ORRC_0_WORD_COUNT                        0x1
+#define MC_DCB_ORRC_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define MC_DCB_ORRC_0_RESET_MASK                        _MK_MASK_CONST(0xff)
+#define MC_DCB_ORRC_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define MC_DCB_ORRC_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_DCB_ORRC_0_READ_MASK                         _MK_MASK_CONST(0xff)
+#define MC_DCB_ORRC_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+#define MC_DCB_ORRC_0_DCB_OUTREQCNT_SHIFT                       _MK_SHIFT_CONST(0)
+#define MC_DCB_ORRC_0_DCB_OUTREQCNT_FIELD                       (_MK_MASK_CONST(0xff) << MC_DCB_ORRC_0_DCB_OUTREQCNT_SHIFT)
+#define MC_DCB_ORRC_0_DCB_OUTREQCNT_RANGE                       7:0
+#define MC_DCB_ORRC_0_DCB_OUTREQCNT_WOFFSET                     0x0
+#define MC_DCB_ORRC_0_DCB_OUTREQCNT_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_DCB_ORRC_0_DCB_OUTREQCNT_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define MC_DCB_ORRC_0_DCB_OUTREQCNT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_DCB_ORRC_0_DCB_OUTREQCNT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register MC_EPP_ORRC_0  
+#define MC_EPP_ORRC_0                   _MK_ADDR_CONST(0xb0)
+#define MC_EPP_ORRC_0_WORD_COUNT                        0x1
+#define MC_EPP_ORRC_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define MC_EPP_ORRC_0_RESET_MASK                        _MK_MASK_CONST(0xff)
+#define MC_EPP_ORRC_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define MC_EPP_ORRC_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_EPP_ORRC_0_READ_MASK                         _MK_MASK_CONST(0xff)
+#define MC_EPP_ORRC_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+#define MC_EPP_ORRC_0_EPP_OUTREQCNT_SHIFT                       _MK_SHIFT_CONST(0)
+#define MC_EPP_ORRC_0_EPP_OUTREQCNT_FIELD                       (_MK_MASK_CONST(0xff) << MC_EPP_ORRC_0_EPP_OUTREQCNT_SHIFT)
+#define MC_EPP_ORRC_0_EPP_OUTREQCNT_RANGE                       7:0
+#define MC_EPP_ORRC_0_EPP_OUTREQCNT_WOFFSET                     0x0
+#define MC_EPP_ORRC_0_EPP_OUTREQCNT_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_EPP_ORRC_0_EPP_OUTREQCNT_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define MC_EPP_ORRC_0_EPP_OUTREQCNT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_EPP_ORRC_0_EPP_OUTREQCNT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register MC_G2_ORRC_0  
+#define MC_G2_ORRC_0                    _MK_ADDR_CONST(0xb4)
+#define MC_G2_ORRC_0_WORD_COUNT                         0x1
+#define MC_G2_ORRC_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define MC_G2_ORRC_0_RESET_MASK                         _MK_MASK_CONST(0xff)
+#define MC_G2_ORRC_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define MC_G2_ORRC_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_G2_ORRC_0_READ_MASK                  _MK_MASK_CONST(0xff)
+#define MC_G2_ORRC_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
+#define MC_G2_ORRC_0_G2_OUTREQCNT_SHIFT                 _MK_SHIFT_CONST(0)
+#define MC_G2_ORRC_0_G2_OUTREQCNT_FIELD                 (_MK_MASK_CONST(0xff) << MC_G2_ORRC_0_G2_OUTREQCNT_SHIFT)
+#define MC_G2_ORRC_0_G2_OUTREQCNT_RANGE                 7:0
+#define MC_G2_ORRC_0_G2_OUTREQCNT_WOFFSET                       0x0
+#define MC_G2_ORRC_0_G2_OUTREQCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_G2_ORRC_0_G2_OUTREQCNT_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define MC_G2_ORRC_0_G2_OUTREQCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_G2_ORRC_0_G2_OUTREQCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register MC_HC_ORRC_0  
+#define MC_HC_ORRC_0                    _MK_ADDR_CONST(0xb8)
+#define MC_HC_ORRC_0_WORD_COUNT                         0x1
+#define MC_HC_ORRC_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define MC_HC_ORRC_0_RESET_MASK                         _MK_MASK_CONST(0xff)
+#define MC_HC_ORRC_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define MC_HC_ORRC_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_HC_ORRC_0_READ_MASK                  _MK_MASK_CONST(0xff)
+#define MC_HC_ORRC_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
+#define MC_HC_ORRC_0_HC_OUTREQCNT_SHIFT                 _MK_SHIFT_CONST(0)
+#define MC_HC_ORRC_0_HC_OUTREQCNT_FIELD                 (_MK_MASK_CONST(0xff) << MC_HC_ORRC_0_HC_OUTREQCNT_SHIFT)
+#define MC_HC_ORRC_0_HC_OUTREQCNT_RANGE                 7:0
+#define MC_HC_ORRC_0_HC_OUTREQCNT_WOFFSET                       0x0
+#define MC_HC_ORRC_0_HC_OUTREQCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_HC_ORRC_0_HC_OUTREQCNT_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define MC_HC_ORRC_0_HC_OUTREQCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_HC_ORRC_0_HC_OUTREQCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register MC_ISP_ORRC_0  
+#define MC_ISP_ORRC_0                   _MK_ADDR_CONST(0xbc)
+#define MC_ISP_ORRC_0_WORD_COUNT                        0x1
+#define MC_ISP_ORRC_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define MC_ISP_ORRC_0_RESET_MASK                        _MK_MASK_CONST(0xff)
+#define MC_ISP_ORRC_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define MC_ISP_ORRC_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_ISP_ORRC_0_READ_MASK                         _MK_MASK_CONST(0xff)
+#define MC_ISP_ORRC_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+#define MC_ISP_ORRC_0_ISP_OUTREQCNT_SHIFT                       _MK_SHIFT_CONST(0)
+#define MC_ISP_ORRC_0_ISP_OUTREQCNT_FIELD                       (_MK_MASK_CONST(0xff) << MC_ISP_ORRC_0_ISP_OUTREQCNT_SHIFT)
+#define MC_ISP_ORRC_0_ISP_OUTREQCNT_RANGE                       7:0
+#define MC_ISP_ORRC_0_ISP_OUTREQCNT_WOFFSET                     0x0
+#define MC_ISP_ORRC_0_ISP_OUTREQCNT_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_ISP_ORRC_0_ISP_OUTREQCNT_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define MC_ISP_ORRC_0_ISP_OUTREQCNT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_ISP_ORRC_0_ISP_OUTREQCNT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register MC_MPCORE_ORRC_0  
+#define MC_MPCORE_ORRC_0                        _MK_ADDR_CONST(0xc0)
+#define MC_MPCORE_ORRC_0_WORD_COUNT                     0x1
+#define MC_MPCORE_ORRC_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define MC_MPCORE_ORRC_0_RESET_MASK                     _MK_MASK_CONST(0xff)
+#define MC_MPCORE_ORRC_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define MC_MPCORE_ORRC_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_MPCORE_ORRC_0_READ_MASK                      _MK_MASK_CONST(0xff)
+#define MC_MPCORE_ORRC_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
+#define MC_MPCORE_ORRC_0_MPCORE_OUTREQCNT_SHIFT                 _MK_SHIFT_CONST(0)
+#define MC_MPCORE_ORRC_0_MPCORE_OUTREQCNT_FIELD                 (_MK_MASK_CONST(0xff) << MC_MPCORE_ORRC_0_MPCORE_OUTREQCNT_SHIFT)
+#define MC_MPCORE_ORRC_0_MPCORE_OUTREQCNT_RANGE                 7:0
+#define MC_MPCORE_ORRC_0_MPCORE_OUTREQCNT_WOFFSET                       0x0
+#define MC_MPCORE_ORRC_0_MPCORE_OUTREQCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_MPCORE_ORRC_0_MPCORE_OUTREQCNT_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define MC_MPCORE_ORRC_0_MPCORE_OUTREQCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_MPCORE_ORRC_0_MPCORE_OUTREQCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register MC_MPEA_ORRC_0  
+#define MC_MPEA_ORRC_0                  _MK_ADDR_CONST(0xc4)
+#define MC_MPEA_ORRC_0_WORD_COUNT                       0x1
+#define MC_MPEA_ORRC_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define MC_MPEA_ORRC_0_RESET_MASK                       _MK_MASK_CONST(0xff)
+#define MC_MPEA_ORRC_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define MC_MPEA_ORRC_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_MPEA_ORRC_0_READ_MASK                        _MK_MASK_CONST(0xff)
+#define MC_MPEA_ORRC_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
+#define MC_MPEA_ORRC_0_MPEA_OUTREQCNT_SHIFT                     _MK_SHIFT_CONST(0)
+#define MC_MPEA_ORRC_0_MPEA_OUTREQCNT_FIELD                     (_MK_MASK_CONST(0xff) << MC_MPEA_ORRC_0_MPEA_OUTREQCNT_SHIFT)
+#define MC_MPEA_ORRC_0_MPEA_OUTREQCNT_RANGE                     7:0
+#define MC_MPEA_ORRC_0_MPEA_OUTREQCNT_WOFFSET                   0x0
+#define MC_MPEA_ORRC_0_MPEA_OUTREQCNT_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_MPEA_ORRC_0_MPEA_OUTREQCNT_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define MC_MPEA_ORRC_0_MPEA_OUTREQCNT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_MPEA_ORRC_0_MPEA_OUTREQCNT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register MC_MPEB_ORRC_0  
+#define MC_MPEB_ORRC_0                  _MK_ADDR_CONST(0xc8)
+#define MC_MPEB_ORRC_0_WORD_COUNT                       0x1
+#define MC_MPEB_ORRC_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define MC_MPEB_ORRC_0_RESET_MASK                       _MK_MASK_CONST(0xff)
+#define MC_MPEB_ORRC_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define MC_MPEB_ORRC_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_MPEB_ORRC_0_READ_MASK                        _MK_MASK_CONST(0xff)
+#define MC_MPEB_ORRC_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
+#define MC_MPEB_ORRC_0_MPEB_OUTREQCNT_SHIFT                     _MK_SHIFT_CONST(0)
+#define MC_MPEB_ORRC_0_MPEB_OUTREQCNT_FIELD                     (_MK_MASK_CONST(0xff) << MC_MPEB_ORRC_0_MPEB_OUTREQCNT_SHIFT)
+#define MC_MPEB_ORRC_0_MPEB_OUTREQCNT_RANGE                     7:0
+#define MC_MPEB_ORRC_0_MPEB_OUTREQCNT_WOFFSET                   0x0
+#define MC_MPEB_ORRC_0_MPEB_OUTREQCNT_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_MPEB_ORRC_0_MPEB_OUTREQCNT_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define MC_MPEB_ORRC_0_MPEB_OUTREQCNT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_MPEB_ORRC_0_MPEB_OUTREQCNT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register MC_MPEC_ORRC_0  
+#define MC_MPEC_ORRC_0                  _MK_ADDR_CONST(0xcc)
+#define MC_MPEC_ORRC_0_WORD_COUNT                       0x1
+#define MC_MPEC_ORRC_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define MC_MPEC_ORRC_0_RESET_MASK                       _MK_MASK_CONST(0xff)
+#define MC_MPEC_ORRC_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define MC_MPEC_ORRC_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_MPEC_ORRC_0_READ_MASK                        _MK_MASK_CONST(0xff)
+#define MC_MPEC_ORRC_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
+#define MC_MPEC_ORRC_0_MPEC_OUTREQCNT_SHIFT                     _MK_SHIFT_CONST(0)
+#define MC_MPEC_ORRC_0_MPEC_OUTREQCNT_FIELD                     (_MK_MASK_CONST(0xff) << MC_MPEC_ORRC_0_MPEC_OUTREQCNT_SHIFT)
+#define MC_MPEC_ORRC_0_MPEC_OUTREQCNT_RANGE                     7:0
+#define MC_MPEC_ORRC_0_MPEC_OUTREQCNT_WOFFSET                   0x0
+#define MC_MPEC_ORRC_0_MPEC_OUTREQCNT_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_MPEC_ORRC_0_MPEC_OUTREQCNT_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define MC_MPEC_ORRC_0_MPEC_OUTREQCNT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_MPEC_ORRC_0_MPEC_OUTREQCNT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register MC_NV_ORRC_0  
+#define MC_NV_ORRC_0                    _MK_ADDR_CONST(0xd0)
+#define MC_NV_ORRC_0_WORD_COUNT                         0x1
+#define MC_NV_ORRC_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define MC_NV_ORRC_0_RESET_MASK                         _MK_MASK_CONST(0xff)
+#define MC_NV_ORRC_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define MC_NV_ORRC_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_NV_ORRC_0_READ_MASK                  _MK_MASK_CONST(0xff)
+#define MC_NV_ORRC_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
+#define MC_NV_ORRC_0_NV_OUTREQCNT_SHIFT                 _MK_SHIFT_CONST(0)
+#define MC_NV_ORRC_0_NV_OUTREQCNT_FIELD                 (_MK_MASK_CONST(0xff) << MC_NV_ORRC_0_NV_OUTREQCNT_SHIFT)
+#define MC_NV_ORRC_0_NV_OUTREQCNT_RANGE                 7:0
+#define MC_NV_ORRC_0_NV_OUTREQCNT_WOFFSET                       0x0
+#define MC_NV_ORRC_0_NV_OUTREQCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_NV_ORRC_0_NV_OUTREQCNT_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define MC_NV_ORRC_0_NV_OUTREQCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_NV_ORRC_0_NV_OUTREQCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register MC_PPCS_ORRC_0  
+#define MC_PPCS_ORRC_0                  _MK_ADDR_CONST(0xd4)
+#define MC_PPCS_ORRC_0_WORD_COUNT                       0x1
+#define MC_PPCS_ORRC_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define MC_PPCS_ORRC_0_RESET_MASK                       _MK_MASK_CONST(0xff)
+#define MC_PPCS_ORRC_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define MC_PPCS_ORRC_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_PPCS_ORRC_0_READ_MASK                        _MK_MASK_CONST(0xff)
+#define MC_PPCS_ORRC_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
+#define MC_PPCS_ORRC_0_PPCS_OUTREQCNT_SHIFT                     _MK_SHIFT_CONST(0)
+#define MC_PPCS_ORRC_0_PPCS_OUTREQCNT_FIELD                     (_MK_MASK_CONST(0xff) << MC_PPCS_ORRC_0_PPCS_OUTREQCNT_SHIFT)
+#define MC_PPCS_ORRC_0_PPCS_OUTREQCNT_RANGE                     7:0
+#define MC_PPCS_ORRC_0_PPCS_OUTREQCNT_WOFFSET                   0x0
+#define MC_PPCS_ORRC_0_PPCS_OUTREQCNT_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_PPCS_ORRC_0_PPCS_OUTREQCNT_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define MC_PPCS_ORRC_0_PPCS_OUTREQCNT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_PPCS_ORRC_0_PPCS_OUTREQCNT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register MC_VDE_ORRC_0  
+#define MC_VDE_ORRC_0                   _MK_ADDR_CONST(0xd8)
+#define MC_VDE_ORRC_0_WORD_COUNT                        0x1
+#define MC_VDE_ORRC_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define MC_VDE_ORRC_0_RESET_MASK                        _MK_MASK_CONST(0xff)
+#define MC_VDE_ORRC_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define MC_VDE_ORRC_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_VDE_ORRC_0_READ_MASK                         _MK_MASK_CONST(0xff)
+#define MC_VDE_ORRC_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+#define MC_VDE_ORRC_0_VDE_OUTREQCNT_SHIFT                       _MK_SHIFT_CONST(0)
+#define MC_VDE_ORRC_0_VDE_OUTREQCNT_FIELD                       (_MK_MASK_CONST(0xff) << MC_VDE_ORRC_0_VDE_OUTREQCNT_SHIFT)
+#define MC_VDE_ORRC_0_VDE_OUTREQCNT_RANGE                       7:0
+#define MC_VDE_ORRC_0_VDE_OUTREQCNT_WOFFSET                     0x0
+#define MC_VDE_ORRC_0_VDE_OUTREQCNT_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_VDE_ORRC_0_VDE_OUTREQCNT_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define MC_VDE_ORRC_0_VDE_OUTREQCNT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_VDE_ORRC_0_VDE_OUTREQCNT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register MC_VI_ORRC_0  
+#define MC_VI_ORRC_0                    _MK_ADDR_CONST(0xdc)
+#define MC_VI_ORRC_0_WORD_COUNT                         0x1
+#define MC_VI_ORRC_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define MC_VI_ORRC_0_RESET_MASK                         _MK_MASK_CONST(0xff)
+#define MC_VI_ORRC_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define MC_VI_ORRC_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_VI_ORRC_0_READ_MASK                  _MK_MASK_CONST(0xff)
+#define MC_VI_ORRC_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
+#define MC_VI_ORRC_0_VI_OUTREQCNT_SHIFT                 _MK_SHIFT_CONST(0)
+#define MC_VI_ORRC_0_VI_OUTREQCNT_FIELD                 (_MK_MASK_CONST(0xff) << MC_VI_ORRC_0_VI_OUTREQCNT_SHIFT)
+#define MC_VI_ORRC_0_VI_OUTREQCNT_RANGE                 7:0
+#define MC_VI_ORRC_0_VI_OUTREQCNT_WOFFSET                       0x0
+#define MC_VI_ORRC_0_VI_OUTREQCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_VI_ORRC_0_VI_OUTREQCNT_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define MC_VI_ORRC_0_VI_OUTREQCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_VI_ORRC_0_VI_OUTREQCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define MC_CLIENT_AP_CTRL_DISABLE       0
+#define MC_CLIENT_AP_CTRL_ENABLE        1
+
+// Register MC_AP_CTRL_0_0  
+#define MC_AP_CTRL_0_0                  _MK_ADDR_CONST(0xe0)
+#define MC_AP_CTRL_0_0_WORD_COUNT                       0x1
+#define MC_AP_CTRL_0_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
+#define MC_AP_CTRL_0_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define MC_AP_CTRL_0_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+#define MC_AP_CTRL_0_0_DISPLAY0A_APVAL_SHIFT                    _MK_SHIFT_CONST(0)
+#define MC_AP_CTRL_0_0_DISPLAY0A_APVAL_FIELD                    (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_DISPLAY0A_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_DISPLAY0A_APVAL_RANGE                    0:0
+#define MC_AP_CTRL_0_0_DISPLAY0A_APVAL_WOFFSET                  0x0
+#define MC_AP_CTRL_0_0_DISPLAY0A_APVAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_DISPLAY0A_APVAL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_DISPLAY0A_APVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_DISPLAY0A_APVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_DISPLAY0A_APVAL_INIT_ENUM                        DISABLE
+#define MC_AP_CTRL_0_0_DISPLAY0A_APVAL_DISABLE                  _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_DISPLAY0A_APVAL_ENABLE                   _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_DISPLAY0A_APVAL_DISABLED                 _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_DISPLAY0A_APVAL_ENABLED                  _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_DISPLAY0AB_APVAL_SHIFT                   _MK_SHIFT_CONST(1)
+#define MC_AP_CTRL_0_0_DISPLAY0AB_APVAL_FIELD                   (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_DISPLAY0AB_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_DISPLAY0AB_APVAL_RANGE                   1:1
+#define MC_AP_CTRL_0_0_DISPLAY0AB_APVAL_WOFFSET                 0x0
+#define MC_AP_CTRL_0_0_DISPLAY0AB_APVAL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_DISPLAY0AB_APVAL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_DISPLAY0AB_APVAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_DISPLAY0AB_APVAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_DISPLAY0AB_APVAL_INIT_ENUM                       DISABLE
+#define MC_AP_CTRL_0_0_DISPLAY0AB_APVAL_DISABLE                 _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_DISPLAY0AB_APVAL_ENABLE                  _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_DISPLAY0AB_APVAL_DISABLED                        _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_DISPLAY0AB_APVAL_ENABLED                 _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_DISPLAY0B_APVAL_SHIFT                    _MK_SHIFT_CONST(2)
+#define MC_AP_CTRL_0_0_DISPLAY0B_APVAL_FIELD                    (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_DISPLAY0B_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_DISPLAY0B_APVAL_RANGE                    2:2
+#define MC_AP_CTRL_0_0_DISPLAY0B_APVAL_WOFFSET                  0x0
+#define MC_AP_CTRL_0_0_DISPLAY0B_APVAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_DISPLAY0B_APVAL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_DISPLAY0B_APVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_DISPLAY0B_APVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_DISPLAY0B_APVAL_INIT_ENUM                        DISABLE
+#define MC_AP_CTRL_0_0_DISPLAY0B_APVAL_DISABLE                  _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_DISPLAY0B_APVAL_ENABLE                   _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_DISPLAY0B_APVAL_DISABLED                 _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_DISPLAY0B_APVAL_ENABLED                  _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_DISPLAY0BB_APVAL_SHIFT                   _MK_SHIFT_CONST(3)
+#define MC_AP_CTRL_0_0_DISPLAY0BB_APVAL_FIELD                   (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_DISPLAY0BB_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_DISPLAY0BB_APVAL_RANGE                   3:3
+#define MC_AP_CTRL_0_0_DISPLAY0BB_APVAL_WOFFSET                 0x0
+#define MC_AP_CTRL_0_0_DISPLAY0BB_APVAL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_DISPLAY0BB_APVAL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_DISPLAY0BB_APVAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_DISPLAY0BB_APVAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_DISPLAY0BB_APVAL_INIT_ENUM                       DISABLE
+#define MC_AP_CTRL_0_0_DISPLAY0BB_APVAL_DISABLE                 _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_DISPLAY0BB_APVAL_ENABLE                  _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_DISPLAY0BB_APVAL_DISABLED                        _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_DISPLAY0BB_APVAL_ENABLED                 _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_DISPLAY0C_APVAL_SHIFT                    _MK_SHIFT_CONST(4)
+#define MC_AP_CTRL_0_0_DISPLAY0C_APVAL_FIELD                    (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_DISPLAY0C_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_DISPLAY0C_APVAL_RANGE                    4:4
+#define MC_AP_CTRL_0_0_DISPLAY0C_APVAL_WOFFSET                  0x0
+#define MC_AP_CTRL_0_0_DISPLAY0C_APVAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_DISPLAY0C_APVAL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_DISPLAY0C_APVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_DISPLAY0C_APVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_DISPLAY0C_APVAL_INIT_ENUM                        DISABLE
+#define MC_AP_CTRL_0_0_DISPLAY0C_APVAL_DISABLE                  _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_DISPLAY0C_APVAL_ENABLE                   _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_DISPLAY0C_APVAL_DISABLED                 _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_DISPLAY0C_APVAL_ENABLED                  _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_DISPLAY0CB_APVAL_SHIFT                   _MK_SHIFT_CONST(5)
+#define MC_AP_CTRL_0_0_DISPLAY0CB_APVAL_FIELD                   (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_DISPLAY0CB_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_DISPLAY0CB_APVAL_RANGE                   5:5
+#define MC_AP_CTRL_0_0_DISPLAY0CB_APVAL_WOFFSET                 0x0
+#define MC_AP_CTRL_0_0_DISPLAY0CB_APVAL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_DISPLAY0CB_APVAL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_DISPLAY0CB_APVAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_DISPLAY0CB_APVAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_DISPLAY0CB_APVAL_INIT_ENUM                       DISABLE
+#define MC_AP_CTRL_0_0_DISPLAY0CB_APVAL_DISABLE                 _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_DISPLAY0CB_APVAL_ENABLE                  _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_DISPLAY0CB_APVAL_DISABLED                        _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_DISPLAY0CB_APVAL_ENABLED                 _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_DISPLAY1B_APVAL_SHIFT                    _MK_SHIFT_CONST(6)
+#define MC_AP_CTRL_0_0_DISPLAY1B_APVAL_FIELD                    (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_DISPLAY1B_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_DISPLAY1B_APVAL_RANGE                    6:6
+#define MC_AP_CTRL_0_0_DISPLAY1B_APVAL_WOFFSET                  0x0
+#define MC_AP_CTRL_0_0_DISPLAY1B_APVAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_DISPLAY1B_APVAL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_DISPLAY1B_APVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_DISPLAY1B_APVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_DISPLAY1B_APVAL_INIT_ENUM                        DISABLE
+#define MC_AP_CTRL_0_0_DISPLAY1B_APVAL_DISABLE                  _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_DISPLAY1B_APVAL_ENABLE                   _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_DISPLAY1B_APVAL_DISABLED                 _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_DISPLAY1B_APVAL_ENABLED                  _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_DISPLAY1BB_APVAL_SHIFT                   _MK_SHIFT_CONST(7)
+#define MC_AP_CTRL_0_0_DISPLAY1BB_APVAL_FIELD                   (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_DISPLAY1BB_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_DISPLAY1BB_APVAL_RANGE                   7:7
+#define MC_AP_CTRL_0_0_DISPLAY1BB_APVAL_WOFFSET                 0x0
+#define MC_AP_CTRL_0_0_DISPLAY1BB_APVAL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_DISPLAY1BB_APVAL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_DISPLAY1BB_APVAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_DISPLAY1BB_APVAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_DISPLAY1BB_APVAL_INIT_ENUM                       DISABLE
+#define MC_AP_CTRL_0_0_DISPLAY1BB_APVAL_DISABLE                 _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_DISPLAY1BB_APVAL_ENABLE                  _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_DISPLAY1BB_APVAL_DISABLED                        _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_DISPLAY1BB_APVAL_ENABLED                 _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_EPPUP_APVAL_SHIFT                        _MK_SHIFT_CONST(8)
+#define MC_AP_CTRL_0_0_EPPUP_APVAL_FIELD                        (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_EPPUP_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_EPPUP_APVAL_RANGE                        8:8
+#define MC_AP_CTRL_0_0_EPPUP_APVAL_WOFFSET                      0x0
+#define MC_AP_CTRL_0_0_EPPUP_APVAL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_EPPUP_APVAL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_EPPUP_APVAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_EPPUP_APVAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_EPPUP_APVAL_INIT_ENUM                    DISABLE
+#define MC_AP_CTRL_0_0_EPPUP_APVAL_DISABLE                      _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_EPPUP_APVAL_ENABLE                       _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_EPPUP_APVAL_DISABLED                     _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_EPPUP_APVAL_ENABLED                      _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_G2PR_APVAL_SHIFT                 _MK_SHIFT_CONST(9)
+#define MC_AP_CTRL_0_0_G2PR_APVAL_FIELD                 (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_G2PR_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_G2PR_APVAL_RANGE                 9:9
+#define MC_AP_CTRL_0_0_G2PR_APVAL_WOFFSET                       0x0
+#define MC_AP_CTRL_0_0_G2PR_APVAL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_G2PR_APVAL_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_G2PR_APVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_G2PR_APVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_G2PR_APVAL_INIT_ENUM                     DISABLE
+#define MC_AP_CTRL_0_0_G2PR_APVAL_DISABLE                       _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_G2PR_APVAL_ENABLE                        _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_G2PR_APVAL_DISABLED                      _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_G2PR_APVAL_ENABLED                       _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_G2SR_APVAL_SHIFT                 _MK_SHIFT_CONST(10)
+#define MC_AP_CTRL_0_0_G2SR_APVAL_FIELD                 (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_G2SR_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_G2SR_APVAL_RANGE                 10:10
+#define MC_AP_CTRL_0_0_G2SR_APVAL_WOFFSET                       0x0
+#define MC_AP_CTRL_0_0_G2SR_APVAL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_G2SR_APVAL_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_G2SR_APVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_G2SR_APVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_G2SR_APVAL_INIT_ENUM                     DISABLE
+#define MC_AP_CTRL_0_0_G2SR_APVAL_DISABLE                       _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_G2SR_APVAL_ENABLE                        _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_G2SR_APVAL_DISABLED                      _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_G2SR_APVAL_ENABLED                       _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_MPEUNIFBR_APVAL_SHIFT                    _MK_SHIFT_CONST(11)
+#define MC_AP_CTRL_0_0_MPEUNIFBR_APVAL_FIELD                    (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_MPEUNIFBR_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_MPEUNIFBR_APVAL_RANGE                    11:11
+#define MC_AP_CTRL_0_0_MPEUNIFBR_APVAL_WOFFSET                  0x0
+#define MC_AP_CTRL_0_0_MPEUNIFBR_APVAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_MPEUNIFBR_APVAL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_MPEUNIFBR_APVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_MPEUNIFBR_APVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_MPEUNIFBR_APVAL_INIT_ENUM                        DISABLE
+#define MC_AP_CTRL_0_0_MPEUNIFBR_APVAL_DISABLE                  _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_MPEUNIFBR_APVAL_ENABLE                   _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_MPEUNIFBR_APVAL_DISABLED                 _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_MPEUNIFBR_APVAL_ENABLED                  _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_VIRUV_APVAL_SHIFT                        _MK_SHIFT_CONST(12)
+#define MC_AP_CTRL_0_0_VIRUV_APVAL_FIELD                        (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_VIRUV_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_VIRUV_APVAL_RANGE                        12:12
+#define MC_AP_CTRL_0_0_VIRUV_APVAL_WOFFSET                      0x0
+#define MC_AP_CTRL_0_0_VIRUV_APVAL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_VIRUV_APVAL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_VIRUV_APVAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_VIRUV_APVAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_VIRUV_APVAL_INIT_ENUM                    DISABLE
+#define MC_AP_CTRL_0_0_VIRUV_APVAL_DISABLE                      _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_VIRUV_APVAL_ENABLE                       _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_VIRUV_APVAL_DISABLED                     _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_VIRUV_APVAL_ENABLED                      _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_CMCR_APVAL_SHIFT                 _MK_SHIFT_CONST(13)
+#define MC_AP_CTRL_0_0_CMCR_APVAL_FIELD                 (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_CMCR_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_CMCR_APVAL_RANGE                 13:13
+#define MC_AP_CTRL_0_0_CMCR_APVAL_WOFFSET                       0x0
+#define MC_AP_CTRL_0_0_CMCR_APVAL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_CMCR_APVAL_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_CMCR_APVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_CMCR_APVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_CMCR_APVAL_INIT_ENUM                     DISABLE
+#define MC_AP_CTRL_0_0_CMCR_APVAL_DISABLE                       _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_CMCR_APVAL_ENABLE                        _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_CMCR_APVAL_DISABLED                      _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_CMCR_APVAL_ENABLED                       _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_DISPLAYHC_APVAL_SHIFT                    _MK_SHIFT_CONST(14)
+#define MC_AP_CTRL_0_0_DISPLAYHC_APVAL_FIELD                    (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_DISPLAYHC_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_DISPLAYHC_APVAL_RANGE                    14:14
+#define MC_AP_CTRL_0_0_DISPLAYHC_APVAL_WOFFSET                  0x0
+#define MC_AP_CTRL_0_0_DISPLAYHC_APVAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_DISPLAYHC_APVAL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_DISPLAYHC_APVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_DISPLAYHC_APVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_DISPLAYHC_APVAL_INIT_ENUM                        DISABLE
+#define MC_AP_CTRL_0_0_DISPLAYHC_APVAL_DISABLE                  _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_DISPLAYHC_APVAL_ENABLE                   _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_DISPLAYHC_APVAL_DISABLED                 _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_DISPLAYHC_APVAL_ENABLED                  _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_DISPLAYHCB_APVAL_SHIFT                   _MK_SHIFT_CONST(15)
+#define MC_AP_CTRL_0_0_DISPLAYHCB_APVAL_FIELD                   (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_DISPLAYHCB_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_DISPLAYHCB_APVAL_RANGE                   15:15
+#define MC_AP_CTRL_0_0_DISPLAYHCB_APVAL_WOFFSET                 0x0
+#define MC_AP_CTRL_0_0_DISPLAYHCB_APVAL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_DISPLAYHCB_APVAL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_DISPLAYHCB_APVAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_DISPLAYHCB_APVAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_DISPLAYHCB_APVAL_INIT_ENUM                       DISABLE
+#define MC_AP_CTRL_0_0_DISPLAYHCB_APVAL_DISABLE                 _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_DISPLAYHCB_APVAL_ENABLE                  _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_DISPLAYHCB_APVAL_DISABLED                        _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_DISPLAYHCB_APVAL_ENABLED                 _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_FDCDRD_APVAL_SHIFT                       _MK_SHIFT_CONST(16)
+#define MC_AP_CTRL_0_0_FDCDRD_APVAL_FIELD                       (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_FDCDRD_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_FDCDRD_APVAL_RANGE                       16:16
+#define MC_AP_CTRL_0_0_FDCDRD_APVAL_WOFFSET                     0x0
+#define MC_AP_CTRL_0_0_FDCDRD_APVAL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_FDCDRD_APVAL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_FDCDRD_APVAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_FDCDRD_APVAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_FDCDRD_APVAL_INIT_ENUM                   DISABLE
+#define MC_AP_CTRL_0_0_FDCDRD_APVAL_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_FDCDRD_APVAL_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_FDCDRD_APVAL_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_FDCDRD_APVAL_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_G2DR_APVAL_SHIFT                 _MK_SHIFT_CONST(17)
+#define MC_AP_CTRL_0_0_G2DR_APVAL_FIELD                 (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_G2DR_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_G2DR_APVAL_RANGE                 17:17
+#define MC_AP_CTRL_0_0_G2DR_APVAL_WOFFSET                       0x0
+#define MC_AP_CTRL_0_0_G2DR_APVAL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_G2DR_APVAL_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_G2DR_APVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_G2DR_APVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_G2DR_APVAL_INIT_ENUM                     DISABLE
+#define MC_AP_CTRL_0_0_G2DR_APVAL_DISABLE                       _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_G2DR_APVAL_ENABLE                        _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_G2DR_APVAL_DISABLED                      _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_G2DR_APVAL_ENABLED                       _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_HOST1XDMAR_APVAL_SHIFT                   _MK_SHIFT_CONST(18)
+#define MC_AP_CTRL_0_0_HOST1XDMAR_APVAL_FIELD                   (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_HOST1XDMAR_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_HOST1XDMAR_APVAL_RANGE                   18:18
+#define MC_AP_CTRL_0_0_HOST1XDMAR_APVAL_WOFFSET                 0x0
+#define MC_AP_CTRL_0_0_HOST1XDMAR_APVAL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_HOST1XDMAR_APVAL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_HOST1XDMAR_APVAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_HOST1XDMAR_APVAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_HOST1XDMAR_APVAL_INIT_ENUM                       DISABLE
+#define MC_AP_CTRL_0_0_HOST1XDMAR_APVAL_DISABLE                 _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_HOST1XDMAR_APVAL_ENABLE                  _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_HOST1XDMAR_APVAL_DISABLED                        _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_HOST1XDMAR_APVAL_ENABLED                 _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_HOST1XR_APVAL_SHIFT                      _MK_SHIFT_CONST(19)
+#define MC_AP_CTRL_0_0_HOST1XR_APVAL_FIELD                      (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_HOST1XR_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_HOST1XR_APVAL_RANGE                      19:19
+#define MC_AP_CTRL_0_0_HOST1XR_APVAL_WOFFSET                    0x0
+#define MC_AP_CTRL_0_0_HOST1XR_APVAL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_HOST1XR_APVAL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_HOST1XR_APVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_HOST1XR_APVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_HOST1XR_APVAL_INIT_ENUM                  DISABLE
+#define MC_AP_CTRL_0_0_HOST1XR_APVAL_DISABLE                    _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_HOST1XR_APVAL_ENABLE                     _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_HOST1XR_APVAL_DISABLED                   _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_HOST1XR_APVAL_ENABLED                    _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_IDXSRD_APVAL_SHIFT                       _MK_SHIFT_CONST(20)
+#define MC_AP_CTRL_0_0_IDXSRD_APVAL_FIELD                       (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_IDXSRD_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_IDXSRD_APVAL_RANGE                       20:20
+#define MC_AP_CTRL_0_0_IDXSRD_APVAL_WOFFSET                     0x0
+#define MC_AP_CTRL_0_0_IDXSRD_APVAL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_IDXSRD_APVAL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_IDXSRD_APVAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_IDXSRD_APVAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_IDXSRD_APVAL_INIT_ENUM                   DISABLE
+#define MC_AP_CTRL_0_0_IDXSRD_APVAL_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_IDXSRD_APVAL_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_IDXSRD_APVAL_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_IDXSRD_APVAL_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_MPCORER_APVAL_SHIFT                      _MK_SHIFT_CONST(21)
+#define MC_AP_CTRL_0_0_MPCORER_APVAL_FIELD                      (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_MPCORER_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_MPCORER_APVAL_RANGE                      21:21
+#define MC_AP_CTRL_0_0_MPCORER_APVAL_WOFFSET                    0x0
+#define MC_AP_CTRL_0_0_MPCORER_APVAL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_MPCORER_APVAL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_MPCORER_APVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_MPCORER_APVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_MPCORER_APVAL_INIT_ENUM                  DISABLE
+#define MC_AP_CTRL_0_0_MPCORER_APVAL_DISABLE                    _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_MPCORER_APVAL_ENABLE                     _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_MPCORER_APVAL_DISABLED                   _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_MPCORER_APVAL_ENABLED                    _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_MPE_IPRED_APVAL_SHIFT                    _MK_SHIFT_CONST(22)
+#define MC_AP_CTRL_0_0_MPE_IPRED_APVAL_FIELD                    (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_MPE_IPRED_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_MPE_IPRED_APVAL_RANGE                    22:22
+#define MC_AP_CTRL_0_0_MPE_IPRED_APVAL_WOFFSET                  0x0
+#define MC_AP_CTRL_0_0_MPE_IPRED_APVAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_MPE_IPRED_APVAL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_MPE_IPRED_APVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_MPE_IPRED_APVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_MPE_IPRED_APVAL_INIT_ENUM                        DISABLE
+#define MC_AP_CTRL_0_0_MPE_IPRED_APVAL_DISABLE                  _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_MPE_IPRED_APVAL_ENABLE                   _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_MPE_IPRED_APVAL_DISABLED                 _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_MPE_IPRED_APVAL_ENABLED                  _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_MPEAMEMRD_APVAL_SHIFT                    _MK_SHIFT_CONST(23)
+#define MC_AP_CTRL_0_0_MPEAMEMRD_APVAL_FIELD                    (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_MPEAMEMRD_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_MPEAMEMRD_APVAL_RANGE                    23:23
+#define MC_AP_CTRL_0_0_MPEAMEMRD_APVAL_WOFFSET                  0x0
+#define MC_AP_CTRL_0_0_MPEAMEMRD_APVAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_MPEAMEMRD_APVAL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_MPEAMEMRD_APVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_MPEAMEMRD_APVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_MPEAMEMRD_APVAL_INIT_ENUM                        DISABLE
+#define MC_AP_CTRL_0_0_MPEAMEMRD_APVAL_DISABLE                  _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_MPEAMEMRD_APVAL_ENABLE                   _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_MPEAMEMRD_APVAL_DISABLED                 _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_MPEAMEMRD_APVAL_ENABLED                  _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_MPECSRD_APVAL_SHIFT                      _MK_SHIFT_CONST(24)
+#define MC_AP_CTRL_0_0_MPECSRD_APVAL_FIELD                      (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_MPECSRD_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_MPECSRD_APVAL_RANGE                      24:24
+#define MC_AP_CTRL_0_0_MPECSRD_APVAL_WOFFSET                    0x0
+#define MC_AP_CTRL_0_0_MPECSRD_APVAL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_MPECSRD_APVAL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_MPECSRD_APVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_MPECSRD_APVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_MPECSRD_APVAL_INIT_ENUM                  DISABLE
+#define MC_AP_CTRL_0_0_MPECSRD_APVAL_DISABLE                    _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_MPECSRD_APVAL_ENABLE                     _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_MPECSRD_APVAL_DISABLED                   _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_MPECSRD_APVAL_ENABLED                    _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_PPCSAHBDMAR_APVAL_SHIFT                  _MK_SHIFT_CONST(25)
+#define MC_AP_CTRL_0_0_PPCSAHBDMAR_APVAL_FIELD                  (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_PPCSAHBDMAR_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_PPCSAHBDMAR_APVAL_RANGE                  25:25
+#define MC_AP_CTRL_0_0_PPCSAHBDMAR_APVAL_WOFFSET                        0x0
+#define MC_AP_CTRL_0_0_PPCSAHBDMAR_APVAL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_PPCSAHBDMAR_APVAL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_PPCSAHBDMAR_APVAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_PPCSAHBDMAR_APVAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_PPCSAHBDMAR_APVAL_INIT_ENUM                      DISABLE
+#define MC_AP_CTRL_0_0_PPCSAHBDMAR_APVAL_DISABLE                        _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_PPCSAHBDMAR_APVAL_ENABLE                 _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_PPCSAHBDMAR_APVAL_DISABLED                       _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_PPCSAHBDMAR_APVAL_ENABLED                        _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_PPCSAHBSLVR_APVAL_SHIFT                  _MK_SHIFT_CONST(26)
+#define MC_AP_CTRL_0_0_PPCSAHBSLVR_APVAL_FIELD                  (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_PPCSAHBSLVR_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_PPCSAHBSLVR_APVAL_RANGE                  26:26
+#define MC_AP_CTRL_0_0_PPCSAHBSLVR_APVAL_WOFFSET                        0x0
+#define MC_AP_CTRL_0_0_PPCSAHBSLVR_APVAL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_PPCSAHBSLVR_APVAL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_PPCSAHBSLVR_APVAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_PPCSAHBSLVR_APVAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_PPCSAHBSLVR_APVAL_INIT_ENUM                      DISABLE
+#define MC_AP_CTRL_0_0_PPCSAHBSLVR_APVAL_DISABLE                        _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_PPCSAHBSLVR_APVAL_ENABLE                 _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_PPCSAHBSLVR_APVAL_DISABLED                       _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_PPCSAHBSLVR_APVAL_ENABLED                        _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_PPCSARM7R_APVAL_SHIFT                    _MK_SHIFT_CONST(27)
+#define MC_AP_CTRL_0_0_PPCSARM7R_APVAL_FIELD                    (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_PPCSARM7R_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_PPCSARM7R_APVAL_RANGE                    27:27
+#define MC_AP_CTRL_0_0_PPCSARM7R_APVAL_WOFFSET                  0x0
+#define MC_AP_CTRL_0_0_PPCSARM7R_APVAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_PPCSARM7R_APVAL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_PPCSARM7R_APVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_PPCSARM7R_APVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_PPCSARM7R_APVAL_INIT_ENUM                        DISABLE
+#define MC_AP_CTRL_0_0_PPCSARM7R_APVAL_DISABLE                  _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_PPCSARM7R_APVAL_ENABLE                   _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_PPCSARM7R_APVAL_DISABLED                 _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_PPCSARM7R_APVAL_ENABLED                  _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_TEXSRD_APVAL_SHIFT                       _MK_SHIFT_CONST(28)
+#define MC_AP_CTRL_0_0_TEXSRD_APVAL_FIELD                       (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_TEXSRD_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_TEXSRD_APVAL_RANGE                       28:28
+#define MC_AP_CTRL_0_0_TEXSRD_APVAL_WOFFSET                     0x0
+#define MC_AP_CTRL_0_0_TEXSRD_APVAL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_TEXSRD_APVAL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_TEXSRD_APVAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_TEXSRD_APVAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_TEXSRD_APVAL_INIT_ENUM                   DISABLE
+#define MC_AP_CTRL_0_0_TEXSRD_APVAL_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_TEXSRD_APVAL_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_TEXSRD_APVAL_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_TEXSRD_APVAL_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_VDEBSEAR_APVAL_SHIFT                     _MK_SHIFT_CONST(29)
+#define MC_AP_CTRL_0_0_VDEBSEAR_APVAL_FIELD                     (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_VDEBSEAR_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_VDEBSEAR_APVAL_RANGE                     29:29
+#define MC_AP_CTRL_0_0_VDEBSEAR_APVAL_WOFFSET                   0x0
+#define MC_AP_CTRL_0_0_VDEBSEAR_APVAL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_VDEBSEAR_APVAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_VDEBSEAR_APVAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_VDEBSEAR_APVAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_VDEBSEAR_APVAL_INIT_ENUM                 DISABLE
+#define MC_AP_CTRL_0_0_VDEBSEAR_APVAL_DISABLE                   _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_VDEBSEAR_APVAL_ENABLE                    _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_VDEBSEAR_APVAL_DISABLED                  _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_VDEBSEAR_APVAL_ENABLED                   _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_VDEBSEVR_APVAL_SHIFT                     _MK_SHIFT_CONST(30)
+#define MC_AP_CTRL_0_0_VDEBSEVR_APVAL_FIELD                     (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_VDEBSEVR_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_VDEBSEVR_APVAL_RANGE                     30:30
+#define MC_AP_CTRL_0_0_VDEBSEVR_APVAL_WOFFSET                   0x0
+#define MC_AP_CTRL_0_0_VDEBSEVR_APVAL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_VDEBSEVR_APVAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_VDEBSEVR_APVAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_VDEBSEVR_APVAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_VDEBSEVR_APVAL_INIT_ENUM                 DISABLE
+#define MC_AP_CTRL_0_0_VDEBSEVR_APVAL_DISABLE                   _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_VDEBSEVR_APVAL_ENABLE                    _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_VDEBSEVR_APVAL_DISABLED                  _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_VDEBSEVR_APVAL_ENABLED                   _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_VDEMBER_APVAL_SHIFT                      _MK_SHIFT_CONST(31)
+#define MC_AP_CTRL_0_0_VDEMBER_APVAL_FIELD                      (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_VDEMBER_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_VDEMBER_APVAL_RANGE                      31:31
+#define MC_AP_CTRL_0_0_VDEMBER_APVAL_WOFFSET                    0x0
+#define MC_AP_CTRL_0_0_VDEMBER_APVAL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_VDEMBER_APVAL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_VDEMBER_APVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_VDEMBER_APVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_VDEMBER_APVAL_INIT_ENUM                  DISABLE
+#define MC_AP_CTRL_0_0_VDEMBER_APVAL_DISABLE                    _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_VDEMBER_APVAL_ENABLE                     _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_VDEMBER_APVAL_DISABLED                   _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_VDEMBER_APVAL_ENABLED                    _MK_ENUM_CONST(1)
+
+
+// Register MC_AP_CTRL_1_0  
+#define MC_AP_CTRL_1_0                  _MK_ADDR_CONST(0xe4)
+#define MC_AP_CTRL_1_0_WORD_COUNT                       0x1
+#define MC_AP_CTRL_1_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_RESET_MASK                       _MK_MASK_CONST(0xffffff)
+#define MC_AP_CTRL_1_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_READ_MASK                        _MK_MASK_CONST(0xffffff)
+#define MC_AP_CTRL_1_0_WRITE_MASK                       _MK_MASK_CONST(0xffffff)
+#define MC_AP_CTRL_1_0_VDEMCER_APVAL_SHIFT                      _MK_SHIFT_CONST(0)
+#define MC_AP_CTRL_1_0_VDEMCER_APVAL_FIELD                      (_MK_MASK_CONST(0x1) << MC_AP_CTRL_1_0_VDEMCER_APVAL_SHIFT)
+#define MC_AP_CTRL_1_0_VDEMCER_APVAL_RANGE                      0:0
+#define MC_AP_CTRL_1_0_VDEMCER_APVAL_WOFFSET                    0x0
+#define MC_AP_CTRL_1_0_VDEMCER_APVAL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_VDEMCER_APVAL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_1_0_VDEMCER_APVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_VDEMCER_APVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_VDEMCER_APVAL_INIT_ENUM                  DISABLE
+#define MC_AP_CTRL_1_0_VDEMCER_APVAL_DISABLE                    _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_VDEMCER_APVAL_ENABLE                     _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_1_0_VDEMCER_APVAL_DISABLED                   _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_VDEMCER_APVAL_ENABLED                    _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_1_0_VDETPER_APVAL_SHIFT                      _MK_SHIFT_CONST(1)
+#define MC_AP_CTRL_1_0_VDETPER_APVAL_FIELD                      (_MK_MASK_CONST(0x1) << MC_AP_CTRL_1_0_VDETPER_APVAL_SHIFT)
+#define MC_AP_CTRL_1_0_VDETPER_APVAL_RANGE                      1:1
+#define MC_AP_CTRL_1_0_VDETPER_APVAL_WOFFSET                    0x0
+#define MC_AP_CTRL_1_0_VDETPER_APVAL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_VDETPER_APVAL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_1_0_VDETPER_APVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_VDETPER_APVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_VDETPER_APVAL_INIT_ENUM                  DISABLE
+#define MC_AP_CTRL_1_0_VDETPER_APVAL_DISABLE                    _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_VDETPER_APVAL_ENABLE                     _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_1_0_VDETPER_APVAL_DISABLED                   _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_VDETPER_APVAL_ENABLED                    _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_1_0_EPPU_APVAL_SHIFT                 _MK_SHIFT_CONST(2)
+#define MC_AP_CTRL_1_0_EPPU_APVAL_FIELD                 (_MK_MASK_CONST(0x1) << MC_AP_CTRL_1_0_EPPU_APVAL_SHIFT)
+#define MC_AP_CTRL_1_0_EPPU_APVAL_RANGE                 2:2
+#define MC_AP_CTRL_1_0_EPPU_APVAL_WOFFSET                       0x0
+#define MC_AP_CTRL_1_0_EPPU_APVAL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_EPPU_APVAL_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_1_0_EPPU_APVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_EPPU_APVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_EPPU_APVAL_INIT_ENUM                     DISABLE
+#define MC_AP_CTRL_1_0_EPPU_APVAL_DISABLE                       _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_EPPU_APVAL_ENABLE                        _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_1_0_EPPU_APVAL_DISABLED                      _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_EPPU_APVAL_ENABLED                       _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_1_0_EPPV_APVAL_SHIFT                 _MK_SHIFT_CONST(3)
+#define MC_AP_CTRL_1_0_EPPV_APVAL_FIELD                 (_MK_MASK_CONST(0x1) << MC_AP_CTRL_1_0_EPPV_APVAL_SHIFT)
+#define MC_AP_CTRL_1_0_EPPV_APVAL_RANGE                 3:3
+#define MC_AP_CTRL_1_0_EPPV_APVAL_WOFFSET                       0x0
+#define MC_AP_CTRL_1_0_EPPV_APVAL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_EPPV_APVAL_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_1_0_EPPV_APVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_EPPV_APVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_EPPV_APVAL_INIT_ENUM                     DISABLE
+#define MC_AP_CTRL_1_0_EPPV_APVAL_DISABLE                       _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_EPPV_APVAL_ENABLE                        _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_1_0_EPPV_APVAL_DISABLED                      _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_EPPV_APVAL_ENABLED                       _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_1_0_EPPY_APVAL_SHIFT                 _MK_SHIFT_CONST(4)
+#define MC_AP_CTRL_1_0_EPPY_APVAL_FIELD                 (_MK_MASK_CONST(0x1) << MC_AP_CTRL_1_0_EPPY_APVAL_SHIFT)
+#define MC_AP_CTRL_1_0_EPPY_APVAL_RANGE                 4:4
+#define MC_AP_CTRL_1_0_EPPY_APVAL_WOFFSET                       0x0
+#define MC_AP_CTRL_1_0_EPPY_APVAL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_EPPY_APVAL_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_1_0_EPPY_APVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_EPPY_APVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_EPPY_APVAL_INIT_ENUM                     DISABLE
+#define MC_AP_CTRL_1_0_EPPY_APVAL_DISABLE                       _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_EPPY_APVAL_ENABLE                        _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_1_0_EPPY_APVAL_DISABLED                      _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_EPPY_APVAL_ENABLED                       _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_1_0_MPEUNIFBW_APVAL_SHIFT                    _MK_SHIFT_CONST(5)
+#define MC_AP_CTRL_1_0_MPEUNIFBW_APVAL_FIELD                    (_MK_MASK_CONST(0x1) << MC_AP_CTRL_1_0_MPEUNIFBW_APVAL_SHIFT)
+#define MC_AP_CTRL_1_0_MPEUNIFBW_APVAL_RANGE                    5:5
+#define MC_AP_CTRL_1_0_MPEUNIFBW_APVAL_WOFFSET                  0x0
+#define MC_AP_CTRL_1_0_MPEUNIFBW_APVAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_MPEUNIFBW_APVAL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_1_0_MPEUNIFBW_APVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_MPEUNIFBW_APVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_MPEUNIFBW_APVAL_INIT_ENUM                        DISABLE
+#define MC_AP_CTRL_1_0_MPEUNIFBW_APVAL_DISABLE                  _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_MPEUNIFBW_APVAL_ENABLE                   _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_1_0_MPEUNIFBW_APVAL_DISABLED                 _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_MPEUNIFBW_APVAL_ENABLED                  _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_1_0_VIWSB_APVAL_SHIFT                        _MK_SHIFT_CONST(6)
+#define MC_AP_CTRL_1_0_VIWSB_APVAL_FIELD                        (_MK_MASK_CONST(0x1) << MC_AP_CTRL_1_0_VIWSB_APVAL_SHIFT)
+#define MC_AP_CTRL_1_0_VIWSB_APVAL_RANGE                        6:6
+#define MC_AP_CTRL_1_0_VIWSB_APVAL_WOFFSET                      0x0
+#define MC_AP_CTRL_1_0_VIWSB_APVAL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_VIWSB_APVAL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_1_0_VIWSB_APVAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_VIWSB_APVAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_VIWSB_APVAL_INIT_ENUM                    DISABLE
+#define MC_AP_CTRL_1_0_VIWSB_APVAL_DISABLE                      _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_VIWSB_APVAL_ENABLE                       _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_1_0_VIWSB_APVAL_DISABLED                     _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_VIWSB_APVAL_ENABLED                      _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_1_0_VIWU_APVAL_SHIFT                 _MK_SHIFT_CONST(7)
+#define MC_AP_CTRL_1_0_VIWU_APVAL_FIELD                 (_MK_MASK_CONST(0x1) << MC_AP_CTRL_1_0_VIWU_APVAL_SHIFT)
+#define MC_AP_CTRL_1_0_VIWU_APVAL_RANGE                 7:7
+#define MC_AP_CTRL_1_0_VIWU_APVAL_WOFFSET                       0x0
+#define MC_AP_CTRL_1_0_VIWU_APVAL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_VIWU_APVAL_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_1_0_VIWU_APVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_VIWU_APVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_VIWU_APVAL_INIT_ENUM                     DISABLE
+#define MC_AP_CTRL_1_0_VIWU_APVAL_DISABLE                       _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_VIWU_APVAL_ENABLE                        _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_1_0_VIWU_APVAL_DISABLED                      _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_VIWU_APVAL_ENABLED                       _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_1_0_VIWV_APVAL_SHIFT                 _MK_SHIFT_CONST(8)
+#define MC_AP_CTRL_1_0_VIWV_APVAL_FIELD                 (_MK_MASK_CONST(0x1) << MC_AP_CTRL_1_0_VIWV_APVAL_SHIFT)
+#define MC_AP_CTRL_1_0_VIWV_APVAL_RANGE                 8:8
+#define MC_AP_CTRL_1_0_VIWV_APVAL_WOFFSET                       0x0
+#define MC_AP_CTRL_1_0_VIWV_APVAL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_VIWV_APVAL_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_1_0_VIWV_APVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_VIWV_APVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_VIWV_APVAL_INIT_ENUM                     DISABLE
+#define MC_AP_CTRL_1_0_VIWV_APVAL_DISABLE                       _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_VIWV_APVAL_ENABLE                        _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_1_0_VIWV_APVAL_DISABLED                      _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_VIWV_APVAL_ENABLED                       _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_1_0_VIWY_APVAL_SHIFT                 _MK_SHIFT_CONST(9)
+#define MC_AP_CTRL_1_0_VIWY_APVAL_FIELD                 (_MK_MASK_CONST(0x1) << MC_AP_CTRL_1_0_VIWY_APVAL_SHIFT)
+#define MC_AP_CTRL_1_0_VIWY_APVAL_RANGE                 9:9
+#define MC_AP_CTRL_1_0_VIWY_APVAL_WOFFSET                       0x0
+#define MC_AP_CTRL_1_0_VIWY_APVAL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_VIWY_APVAL_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_1_0_VIWY_APVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_VIWY_APVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_VIWY_APVAL_INIT_ENUM                     DISABLE
+#define MC_AP_CTRL_1_0_VIWY_APVAL_DISABLE                       _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_VIWY_APVAL_ENABLE                        _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_1_0_VIWY_APVAL_DISABLED                      _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_VIWY_APVAL_ENABLED                       _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_1_0_G2DW_APVAL_SHIFT                 _MK_SHIFT_CONST(10)
+#define MC_AP_CTRL_1_0_G2DW_APVAL_FIELD                 (_MK_MASK_CONST(0x1) << MC_AP_CTRL_1_0_G2DW_APVAL_SHIFT)
+#define MC_AP_CTRL_1_0_G2DW_APVAL_RANGE                 10:10
+#define MC_AP_CTRL_1_0_G2DW_APVAL_WOFFSET                       0x0
+#define MC_AP_CTRL_1_0_G2DW_APVAL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_G2DW_APVAL_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_1_0_G2DW_APVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_G2DW_APVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_G2DW_APVAL_INIT_ENUM                     DISABLE
+#define MC_AP_CTRL_1_0_G2DW_APVAL_DISABLE                       _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_G2DW_APVAL_ENABLE                        _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_1_0_G2DW_APVAL_DISABLED                      _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_G2DW_APVAL_ENABLED                       _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_1_0_CMCW_APVAL_SHIFT                 _MK_SHIFT_CONST(11)
+#define MC_AP_CTRL_1_0_CMCW_APVAL_FIELD                 (_MK_MASK_CONST(0x1) << MC_AP_CTRL_1_0_CMCW_APVAL_SHIFT)
+#define MC_AP_CTRL_1_0_CMCW_APVAL_RANGE                 11:11
+#define MC_AP_CTRL_1_0_CMCW_APVAL_WOFFSET                       0x0
+#define MC_AP_CTRL_1_0_CMCW_APVAL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_CMCW_APVAL_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_1_0_CMCW_APVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_CMCW_APVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_CMCW_APVAL_INIT_ENUM                     DISABLE
+#define MC_AP_CTRL_1_0_CMCW_APVAL_DISABLE                       _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_CMCW_APVAL_ENABLE                        _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_1_0_CMCW_APVAL_DISABLED                      _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_CMCW_APVAL_ENABLED                       _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_1_0_FDCDWR_APVAL_SHIFT                       _MK_SHIFT_CONST(12)
+#define MC_AP_CTRL_1_0_FDCDWR_APVAL_FIELD                       (_MK_MASK_CONST(0x1) << MC_AP_CTRL_1_0_FDCDWR_APVAL_SHIFT)
+#define MC_AP_CTRL_1_0_FDCDWR_APVAL_RANGE                       12:12
+#define MC_AP_CTRL_1_0_FDCDWR_APVAL_WOFFSET                     0x0
+#define MC_AP_CTRL_1_0_FDCDWR_APVAL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_FDCDWR_APVAL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_1_0_FDCDWR_APVAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_FDCDWR_APVAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_FDCDWR_APVAL_INIT_ENUM                   DISABLE
+#define MC_AP_CTRL_1_0_FDCDWR_APVAL_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_FDCDWR_APVAL_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_1_0_FDCDWR_APVAL_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_FDCDWR_APVAL_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_1_0_HOST1XW_APVAL_SHIFT                      _MK_SHIFT_CONST(13)
+#define MC_AP_CTRL_1_0_HOST1XW_APVAL_FIELD                      (_MK_MASK_CONST(0x1) << MC_AP_CTRL_1_0_HOST1XW_APVAL_SHIFT)
+#define MC_AP_CTRL_1_0_HOST1XW_APVAL_RANGE                      13:13
+#define MC_AP_CTRL_1_0_HOST1XW_APVAL_WOFFSET                    0x0
+#define MC_AP_CTRL_1_0_HOST1XW_APVAL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_HOST1XW_APVAL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_1_0_HOST1XW_APVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_HOST1XW_APVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_HOST1XW_APVAL_INIT_ENUM                  DISABLE
+#define MC_AP_CTRL_1_0_HOST1XW_APVAL_DISABLE                    _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_HOST1XW_APVAL_ENABLE                     _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_1_0_HOST1XW_APVAL_DISABLED                   _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_HOST1XW_APVAL_ENABLED                    _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_1_0_ISPW_APVAL_SHIFT                 _MK_SHIFT_CONST(14)
+#define MC_AP_CTRL_1_0_ISPW_APVAL_FIELD                 (_MK_MASK_CONST(0x1) << MC_AP_CTRL_1_0_ISPW_APVAL_SHIFT)
+#define MC_AP_CTRL_1_0_ISPW_APVAL_RANGE                 14:14
+#define MC_AP_CTRL_1_0_ISPW_APVAL_WOFFSET                       0x0
+#define MC_AP_CTRL_1_0_ISPW_APVAL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_ISPW_APVAL_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_1_0_ISPW_APVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_ISPW_APVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_ISPW_APVAL_INIT_ENUM                     DISABLE
+#define MC_AP_CTRL_1_0_ISPW_APVAL_DISABLE                       _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_ISPW_APVAL_ENABLE                        _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_1_0_ISPW_APVAL_DISABLED                      _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_ISPW_APVAL_ENABLED                       _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_1_0_MPCOREW_APVAL_SHIFT                      _MK_SHIFT_CONST(15)
+#define MC_AP_CTRL_1_0_MPCOREW_APVAL_FIELD                      (_MK_MASK_CONST(0x1) << MC_AP_CTRL_1_0_MPCOREW_APVAL_SHIFT)
+#define MC_AP_CTRL_1_0_MPCOREW_APVAL_RANGE                      15:15
+#define MC_AP_CTRL_1_0_MPCOREW_APVAL_WOFFSET                    0x0
+#define MC_AP_CTRL_1_0_MPCOREW_APVAL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_MPCOREW_APVAL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_1_0_MPCOREW_APVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_MPCOREW_APVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_MPCOREW_APVAL_INIT_ENUM                  DISABLE
+#define MC_AP_CTRL_1_0_MPCOREW_APVAL_DISABLE                    _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_MPCOREW_APVAL_ENABLE                     _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_1_0_MPCOREW_APVAL_DISABLED                   _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_MPCOREW_APVAL_ENABLED                    _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_1_0_MPECSWR_APVAL_SHIFT                      _MK_SHIFT_CONST(16)
+#define MC_AP_CTRL_1_0_MPECSWR_APVAL_FIELD                      (_MK_MASK_CONST(0x1) << MC_AP_CTRL_1_0_MPECSWR_APVAL_SHIFT)
+#define MC_AP_CTRL_1_0_MPECSWR_APVAL_RANGE                      16:16
+#define MC_AP_CTRL_1_0_MPECSWR_APVAL_WOFFSET                    0x0
+#define MC_AP_CTRL_1_0_MPECSWR_APVAL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_MPECSWR_APVAL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_1_0_MPECSWR_APVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_MPECSWR_APVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_MPECSWR_APVAL_INIT_ENUM                  DISABLE
+#define MC_AP_CTRL_1_0_MPECSWR_APVAL_DISABLE                    _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_MPECSWR_APVAL_ENABLE                     _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_1_0_MPECSWR_APVAL_DISABLED                   _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_MPECSWR_APVAL_ENABLED                    _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_1_0_PPCSAHBDMAW_APVAL_SHIFT                  _MK_SHIFT_CONST(17)
+#define MC_AP_CTRL_1_0_PPCSAHBDMAW_APVAL_FIELD                  (_MK_MASK_CONST(0x1) << MC_AP_CTRL_1_0_PPCSAHBDMAW_APVAL_SHIFT)
+#define MC_AP_CTRL_1_0_PPCSAHBDMAW_APVAL_RANGE                  17:17
+#define MC_AP_CTRL_1_0_PPCSAHBDMAW_APVAL_WOFFSET                        0x0
+#define MC_AP_CTRL_1_0_PPCSAHBDMAW_APVAL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_PPCSAHBDMAW_APVAL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_1_0_PPCSAHBDMAW_APVAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_PPCSAHBDMAW_APVAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_PPCSAHBDMAW_APVAL_INIT_ENUM                      DISABLE
+#define MC_AP_CTRL_1_0_PPCSAHBDMAW_APVAL_DISABLE                        _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_PPCSAHBDMAW_APVAL_ENABLE                 _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_1_0_PPCSAHBDMAW_APVAL_DISABLED                       _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_PPCSAHBDMAW_APVAL_ENABLED                        _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_1_0_PPCSAHBSLVW_APVAL_SHIFT                  _MK_SHIFT_CONST(18)
+#define MC_AP_CTRL_1_0_PPCSAHBSLVW_APVAL_FIELD                  (_MK_MASK_CONST(0x1) << MC_AP_CTRL_1_0_PPCSAHBSLVW_APVAL_SHIFT)
+#define MC_AP_CTRL_1_0_PPCSAHBSLVW_APVAL_RANGE                  18:18
+#define MC_AP_CTRL_1_0_PPCSAHBSLVW_APVAL_WOFFSET                        0x0
+#define MC_AP_CTRL_1_0_PPCSAHBSLVW_APVAL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_PPCSAHBSLVW_APVAL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_1_0_PPCSAHBSLVW_APVAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_PPCSAHBSLVW_APVAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_PPCSAHBSLVW_APVAL_INIT_ENUM                      DISABLE
+#define MC_AP_CTRL_1_0_PPCSAHBSLVW_APVAL_DISABLE                        _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_PPCSAHBSLVW_APVAL_ENABLE                 _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_1_0_PPCSAHBSLVW_APVAL_DISABLED                       _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_PPCSAHBSLVW_APVAL_ENABLED                        _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_1_0_PPCSARM7W_APVAL_SHIFT                    _MK_SHIFT_CONST(19)
+#define MC_AP_CTRL_1_0_PPCSARM7W_APVAL_FIELD                    (_MK_MASK_CONST(0x1) << MC_AP_CTRL_1_0_PPCSARM7W_APVAL_SHIFT)
+#define MC_AP_CTRL_1_0_PPCSARM7W_APVAL_RANGE                    19:19
+#define MC_AP_CTRL_1_0_PPCSARM7W_APVAL_WOFFSET                  0x0
+#define MC_AP_CTRL_1_0_PPCSARM7W_APVAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_PPCSARM7W_APVAL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_1_0_PPCSARM7W_APVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_PPCSARM7W_APVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_PPCSARM7W_APVAL_INIT_ENUM                        DISABLE
+#define MC_AP_CTRL_1_0_PPCSARM7W_APVAL_DISABLE                  _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_PPCSARM7W_APVAL_ENABLE                   _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_1_0_PPCSARM7W_APVAL_DISABLED                 _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_PPCSARM7W_APVAL_ENABLED                  _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_1_0_VDEBSEAW_APVAL_SHIFT                     _MK_SHIFT_CONST(20)
+#define MC_AP_CTRL_1_0_VDEBSEAW_APVAL_FIELD                     (_MK_MASK_CONST(0x1) << MC_AP_CTRL_1_0_VDEBSEAW_APVAL_SHIFT)
+#define MC_AP_CTRL_1_0_VDEBSEAW_APVAL_RANGE                     20:20
+#define MC_AP_CTRL_1_0_VDEBSEAW_APVAL_WOFFSET                   0x0
+#define MC_AP_CTRL_1_0_VDEBSEAW_APVAL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_VDEBSEAW_APVAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_1_0_VDEBSEAW_APVAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_VDEBSEAW_APVAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_VDEBSEAW_APVAL_INIT_ENUM                 DISABLE
+#define MC_AP_CTRL_1_0_VDEBSEAW_APVAL_DISABLE                   _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_VDEBSEAW_APVAL_ENABLE                    _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_1_0_VDEBSEAW_APVAL_DISABLED                  _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_VDEBSEAW_APVAL_ENABLED                   _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_1_0_VDEBSEVW_APVAL_SHIFT                     _MK_SHIFT_CONST(21)
+#define MC_AP_CTRL_1_0_VDEBSEVW_APVAL_FIELD                     (_MK_MASK_CONST(0x1) << MC_AP_CTRL_1_0_VDEBSEVW_APVAL_SHIFT)
+#define MC_AP_CTRL_1_0_VDEBSEVW_APVAL_RANGE                     21:21
+#define MC_AP_CTRL_1_0_VDEBSEVW_APVAL_WOFFSET                   0x0
+#define MC_AP_CTRL_1_0_VDEBSEVW_APVAL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_VDEBSEVW_APVAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_1_0_VDEBSEVW_APVAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_VDEBSEVW_APVAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_VDEBSEVW_APVAL_INIT_ENUM                 DISABLE
+#define MC_AP_CTRL_1_0_VDEBSEVW_APVAL_DISABLE                   _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_VDEBSEVW_APVAL_ENABLE                    _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_1_0_VDEBSEVW_APVAL_DISABLED                  _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_VDEBSEVW_APVAL_ENABLED                   _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_1_0_VDEMBEW_APVAL_SHIFT                      _MK_SHIFT_CONST(22)
+#define MC_AP_CTRL_1_0_VDEMBEW_APVAL_FIELD                      (_MK_MASK_CONST(0x1) << MC_AP_CTRL_1_0_VDEMBEW_APVAL_SHIFT)
+#define MC_AP_CTRL_1_0_VDEMBEW_APVAL_RANGE                      22:22
+#define MC_AP_CTRL_1_0_VDEMBEW_APVAL_WOFFSET                    0x0
+#define MC_AP_CTRL_1_0_VDEMBEW_APVAL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_VDEMBEW_APVAL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_1_0_VDEMBEW_APVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_VDEMBEW_APVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_VDEMBEW_APVAL_INIT_ENUM                  DISABLE
+#define MC_AP_CTRL_1_0_VDEMBEW_APVAL_DISABLE                    _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_VDEMBEW_APVAL_ENABLE                     _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_1_0_VDEMBEW_APVAL_DISABLED                   _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_VDEMBEW_APVAL_ENABLED                    _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_1_0_VDETPMW_APVAL_SHIFT                      _MK_SHIFT_CONST(23)
+#define MC_AP_CTRL_1_0_VDETPMW_APVAL_FIELD                      (_MK_MASK_CONST(0x1) << MC_AP_CTRL_1_0_VDETPMW_APVAL_SHIFT)
+#define MC_AP_CTRL_1_0_VDETPMW_APVAL_RANGE                      23:23
+#define MC_AP_CTRL_1_0_VDETPMW_APVAL_WOFFSET                    0x0
+#define MC_AP_CTRL_1_0_VDETPMW_APVAL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_VDETPMW_APVAL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_1_0_VDETPMW_APVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_VDETPMW_APVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_VDETPMW_APVAL_INIT_ENUM                  DISABLE
+#define MC_AP_CTRL_1_0_VDETPMW_APVAL_DISABLE                    _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_VDETPMW_APVAL_ENABLE                     _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_1_0_VDETPMW_APVAL_DISABLED                   _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_VDETPMW_APVAL_ENABLED                    _MK_ENUM_CONST(1)
+
+
+// Register MC_FPRI_CTRL_CMC_0  
+#define MC_FPRI_CTRL_CMC_0                      _MK_ADDR_CONST(0xe8)
+#define MC_FPRI_CTRL_CMC_0_WORD_COUNT                   0x1
+#define MC_FPRI_CTRL_CMC_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_CMC_0_RESET_MASK                   _MK_MASK_CONST(0xf)
+#define MC_FPRI_CTRL_CMC_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_CMC_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_CMC_0_READ_MASK                    _MK_MASK_CONST(0xf)
+#define MC_FPRI_CTRL_CMC_0_WRITE_MASK                   _MK_MASK_CONST(0xf)
+#define MC_FPRI_CTRL_CMC_0_CMCR_PRIVAL_SHIFT                    _MK_SHIFT_CONST(0)
+#define MC_FPRI_CTRL_CMC_0_CMCR_PRIVAL_FIELD                    (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_CMC_0_CMCR_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_CMC_0_CMCR_PRIVAL_RANGE                    1:0
+#define MC_FPRI_CTRL_CMC_0_CMCR_PRIVAL_WOFFSET                  0x0
+#define MC_FPRI_CTRL_CMC_0_CMCR_PRIVAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_CMC_0_CMCR_PRIVAL_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_CMC_0_CMCR_PRIVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_CMC_0_CMCR_PRIVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_CMC_0_CMCR_PRIVAL_INIT_ENUM                        LOWEST
+#define MC_FPRI_CTRL_CMC_0_CMCR_PRIVAL_LOWEST                   _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_CMC_0_CMCR_PRIVAL_LOW                      _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_CMC_0_CMCR_PRIVAL_MED                      _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_CMC_0_CMCR_PRIVAL_HIGH                     _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_CMC_0_CMCW_PRIVAL_SHIFT                    _MK_SHIFT_CONST(2)
+#define MC_FPRI_CTRL_CMC_0_CMCW_PRIVAL_FIELD                    (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_CMC_0_CMCW_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_CMC_0_CMCW_PRIVAL_RANGE                    3:2
+#define MC_FPRI_CTRL_CMC_0_CMCW_PRIVAL_WOFFSET                  0x0
+#define MC_FPRI_CTRL_CMC_0_CMCW_PRIVAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_CMC_0_CMCW_PRIVAL_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_CMC_0_CMCW_PRIVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_CMC_0_CMCW_PRIVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_CMC_0_CMCW_PRIVAL_INIT_ENUM                        LOWEST
+#define MC_FPRI_CTRL_CMC_0_CMCW_PRIVAL_LOWEST                   _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_CMC_0_CMCW_PRIVAL_LOW                      _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_CMC_0_CMCW_PRIVAL_MED                      _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_CMC_0_CMCW_PRIVAL_HIGH                     _MK_ENUM_CONST(3)
+
+
+// Register MC_FPRI_CTRL_DC_0  
+#define MC_FPRI_CTRL_DC_0                       _MK_ADDR_CONST(0xec)
+#define MC_FPRI_CTRL_DC_0_WORD_COUNT                    0x1
+#define MC_FPRI_CTRL_DC_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_DC_0_RESET_MASK                    _MK_MASK_CONST(0x3ff)
+#define MC_FPRI_CTRL_DC_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_DC_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_DC_0_READ_MASK                     _MK_MASK_CONST(0x3ff)
+#define MC_FPRI_CTRL_DC_0_WRITE_MASK                    _MK_MASK_CONST(0x3ff)
+#define MC_FPRI_CTRL_DC_0_DISPLAY0A_PRIVAL_SHIFT                        _MK_SHIFT_CONST(0)
+#define MC_FPRI_CTRL_DC_0_DISPLAY0A_PRIVAL_FIELD                        (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_DC_0_DISPLAY0A_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_DC_0_DISPLAY0A_PRIVAL_RANGE                        1:0
+#define MC_FPRI_CTRL_DC_0_DISPLAY0A_PRIVAL_WOFFSET                      0x0
+#define MC_FPRI_CTRL_DC_0_DISPLAY0A_PRIVAL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_DC_0_DISPLAY0A_PRIVAL_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_DC_0_DISPLAY0A_PRIVAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_DC_0_DISPLAY0A_PRIVAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_DC_0_DISPLAY0A_PRIVAL_INIT_ENUM                    LOWEST
+#define MC_FPRI_CTRL_DC_0_DISPLAY0A_PRIVAL_LOWEST                       _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_DC_0_DISPLAY0A_PRIVAL_LOW                  _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_DC_0_DISPLAY0A_PRIVAL_MED                  _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_DC_0_DISPLAY0A_PRIVAL_HIGH                 _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_DC_0_DISPLAY0B_PRIVAL_SHIFT                        _MK_SHIFT_CONST(2)
+#define MC_FPRI_CTRL_DC_0_DISPLAY0B_PRIVAL_FIELD                        (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_DC_0_DISPLAY0B_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_DC_0_DISPLAY0B_PRIVAL_RANGE                        3:2
+#define MC_FPRI_CTRL_DC_0_DISPLAY0B_PRIVAL_WOFFSET                      0x0
+#define MC_FPRI_CTRL_DC_0_DISPLAY0B_PRIVAL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_DC_0_DISPLAY0B_PRIVAL_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_DC_0_DISPLAY0B_PRIVAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_DC_0_DISPLAY0B_PRIVAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_DC_0_DISPLAY0B_PRIVAL_INIT_ENUM                    LOWEST
+#define MC_FPRI_CTRL_DC_0_DISPLAY0B_PRIVAL_LOWEST                       _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_DC_0_DISPLAY0B_PRIVAL_LOW                  _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_DC_0_DISPLAY0B_PRIVAL_MED                  _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_DC_0_DISPLAY0B_PRIVAL_HIGH                 _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_DC_0_DISPLAY0C_PRIVAL_SHIFT                        _MK_SHIFT_CONST(4)
+#define MC_FPRI_CTRL_DC_0_DISPLAY0C_PRIVAL_FIELD                        (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_DC_0_DISPLAY0C_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_DC_0_DISPLAY0C_PRIVAL_RANGE                        5:4
+#define MC_FPRI_CTRL_DC_0_DISPLAY0C_PRIVAL_WOFFSET                      0x0
+#define MC_FPRI_CTRL_DC_0_DISPLAY0C_PRIVAL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_DC_0_DISPLAY0C_PRIVAL_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_DC_0_DISPLAY0C_PRIVAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_DC_0_DISPLAY0C_PRIVAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_DC_0_DISPLAY0C_PRIVAL_INIT_ENUM                    LOWEST
+#define MC_FPRI_CTRL_DC_0_DISPLAY0C_PRIVAL_LOWEST                       _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_DC_0_DISPLAY0C_PRIVAL_LOW                  _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_DC_0_DISPLAY0C_PRIVAL_MED                  _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_DC_0_DISPLAY0C_PRIVAL_HIGH                 _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_DC_0_DISPLAY1B_PRIVAL_SHIFT                        _MK_SHIFT_CONST(6)
+#define MC_FPRI_CTRL_DC_0_DISPLAY1B_PRIVAL_FIELD                        (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_DC_0_DISPLAY1B_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_DC_0_DISPLAY1B_PRIVAL_RANGE                        7:6
+#define MC_FPRI_CTRL_DC_0_DISPLAY1B_PRIVAL_WOFFSET                      0x0
+#define MC_FPRI_CTRL_DC_0_DISPLAY1B_PRIVAL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_DC_0_DISPLAY1B_PRIVAL_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_DC_0_DISPLAY1B_PRIVAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_DC_0_DISPLAY1B_PRIVAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_DC_0_DISPLAY1B_PRIVAL_INIT_ENUM                    LOWEST
+#define MC_FPRI_CTRL_DC_0_DISPLAY1B_PRIVAL_LOWEST                       _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_DC_0_DISPLAY1B_PRIVAL_LOW                  _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_DC_0_DISPLAY1B_PRIVAL_MED                  _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_DC_0_DISPLAY1B_PRIVAL_HIGH                 _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_DC_0_DISPLAYHC_PRIVAL_SHIFT                        _MK_SHIFT_CONST(8)
+#define MC_FPRI_CTRL_DC_0_DISPLAYHC_PRIVAL_FIELD                        (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_DC_0_DISPLAYHC_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_DC_0_DISPLAYHC_PRIVAL_RANGE                        9:8
+#define MC_FPRI_CTRL_DC_0_DISPLAYHC_PRIVAL_WOFFSET                      0x0
+#define MC_FPRI_CTRL_DC_0_DISPLAYHC_PRIVAL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_DC_0_DISPLAYHC_PRIVAL_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_DC_0_DISPLAYHC_PRIVAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_DC_0_DISPLAYHC_PRIVAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_DC_0_DISPLAYHC_PRIVAL_INIT_ENUM                    LOWEST
+#define MC_FPRI_CTRL_DC_0_DISPLAYHC_PRIVAL_LOWEST                       _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_DC_0_DISPLAYHC_PRIVAL_LOW                  _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_DC_0_DISPLAYHC_PRIVAL_MED                  _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_DC_0_DISPLAYHC_PRIVAL_HIGH                 _MK_ENUM_CONST(3)
+
+
+// Register MC_FPRI_CTRL_DCB_0  
+#define MC_FPRI_CTRL_DCB_0                      _MK_ADDR_CONST(0xf0)
+#define MC_FPRI_CTRL_DCB_0_WORD_COUNT                   0x1
+#define MC_FPRI_CTRL_DCB_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_DCB_0_RESET_MASK                   _MK_MASK_CONST(0x3ff)
+#define MC_FPRI_CTRL_DCB_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_DCB_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_DCB_0_READ_MASK                    _MK_MASK_CONST(0x3ff)
+#define MC_FPRI_CTRL_DCB_0_WRITE_MASK                   _MK_MASK_CONST(0x3ff)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0AB_PRIVAL_SHIFT                      _MK_SHIFT_CONST(0)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0AB_PRIVAL_FIELD                      (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_DCB_0_DISPLAY0AB_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0AB_PRIVAL_RANGE                      1:0
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0AB_PRIVAL_WOFFSET                    0x0
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0AB_PRIVAL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0AB_PRIVAL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0AB_PRIVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0AB_PRIVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0AB_PRIVAL_INIT_ENUM                  LOWEST
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0AB_PRIVAL_LOWEST                     _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0AB_PRIVAL_LOW                        _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0AB_PRIVAL_MED                        _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0AB_PRIVAL_HIGH                       _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0BB_PRIVAL_SHIFT                      _MK_SHIFT_CONST(2)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0BB_PRIVAL_FIELD                      (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_DCB_0_DISPLAY0BB_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0BB_PRIVAL_RANGE                      3:2
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0BB_PRIVAL_WOFFSET                    0x0
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0BB_PRIVAL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0BB_PRIVAL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0BB_PRIVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0BB_PRIVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0BB_PRIVAL_INIT_ENUM                  LOWEST
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0BB_PRIVAL_LOWEST                     _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0BB_PRIVAL_LOW                        _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0BB_PRIVAL_MED                        _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0BB_PRIVAL_HIGH                       _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0CB_PRIVAL_SHIFT                      _MK_SHIFT_CONST(4)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0CB_PRIVAL_FIELD                      (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_DCB_0_DISPLAY0CB_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0CB_PRIVAL_RANGE                      5:4
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0CB_PRIVAL_WOFFSET                    0x0
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0CB_PRIVAL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0CB_PRIVAL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0CB_PRIVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0CB_PRIVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0CB_PRIVAL_INIT_ENUM                  LOWEST
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0CB_PRIVAL_LOWEST                     _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0CB_PRIVAL_LOW                        _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0CB_PRIVAL_MED                        _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0CB_PRIVAL_HIGH                       _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_DCB_0_DISPLAY1BB_PRIVAL_SHIFT                      _MK_SHIFT_CONST(6)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY1BB_PRIVAL_FIELD                      (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_DCB_0_DISPLAY1BB_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY1BB_PRIVAL_RANGE                      7:6
+#define MC_FPRI_CTRL_DCB_0_DISPLAY1BB_PRIVAL_WOFFSET                    0x0
+#define MC_FPRI_CTRL_DCB_0_DISPLAY1BB_PRIVAL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY1BB_PRIVAL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY1BB_PRIVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY1BB_PRIVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY1BB_PRIVAL_INIT_ENUM                  LOWEST
+#define MC_FPRI_CTRL_DCB_0_DISPLAY1BB_PRIVAL_LOWEST                     _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY1BB_PRIVAL_LOW                        _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY1BB_PRIVAL_MED                        _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY1BB_PRIVAL_HIGH                       _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_DCB_0_DISPLAYHCB_PRIVAL_SHIFT                      _MK_SHIFT_CONST(8)
+#define MC_FPRI_CTRL_DCB_0_DISPLAYHCB_PRIVAL_FIELD                      (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_DCB_0_DISPLAYHCB_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_DCB_0_DISPLAYHCB_PRIVAL_RANGE                      9:8
+#define MC_FPRI_CTRL_DCB_0_DISPLAYHCB_PRIVAL_WOFFSET                    0x0
+#define MC_FPRI_CTRL_DCB_0_DISPLAYHCB_PRIVAL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_DCB_0_DISPLAYHCB_PRIVAL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_DCB_0_DISPLAYHCB_PRIVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_DCB_0_DISPLAYHCB_PRIVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_DCB_0_DISPLAYHCB_PRIVAL_INIT_ENUM                  LOWEST
+#define MC_FPRI_CTRL_DCB_0_DISPLAYHCB_PRIVAL_LOWEST                     _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_DCB_0_DISPLAYHCB_PRIVAL_LOW                        _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_DCB_0_DISPLAYHCB_PRIVAL_MED                        _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_DCB_0_DISPLAYHCB_PRIVAL_HIGH                       _MK_ENUM_CONST(3)
+
+
+// Register MC_FPRI_CTRL_EPP_0  
+#define MC_FPRI_CTRL_EPP_0                      _MK_ADDR_CONST(0xf4)
+#define MC_FPRI_CTRL_EPP_0_WORD_COUNT                   0x1
+#define MC_FPRI_CTRL_EPP_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_EPP_0_RESET_MASK                   _MK_MASK_CONST(0xff)
+#define MC_FPRI_CTRL_EPP_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_EPP_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_EPP_0_READ_MASK                    _MK_MASK_CONST(0xff)
+#define MC_FPRI_CTRL_EPP_0_WRITE_MASK                   _MK_MASK_CONST(0xff)
+#define MC_FPRI_CTRL_EPP_0_EPPUP_PRIVAL_SHIFT                   _MK_SHIFT_CONST(0)
+#define MC_FPRI_CTRL_EPP_0_EPPUP_PRIVAL_FIELD                   (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_EPP_0_EPPUP_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_EPP_0_EPPUP_PRIVAL_RANGE                   1:0
+#define MC_FPRI_CTRL_EPP_0_EPPUP_PRIVAL_WOFFSET                 0x0
+#define MC_FPRI_CTRL_EPP_0_EPPUP_PRIVAL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_EPP_0_EPPUP_PRIVAL_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_EPP_0_EPPUP_PRIVAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_EPP_0_EPPUP_PRIVAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_EPP_0_EPPUP_PRIVAL_INIT_ENUM                       LOWEST
+#define MC_FPRI_CTRL_EPP_0_EPPUP_PRIVAL_LOWEST                  _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_EPP_0_EPPUP_PRIVAL_LOW                     _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_EPP_0_EPPUP_PRIVAL_MED                     _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_EPP_0_EPPUP_PRIVAL_HIGH                    _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_EPP_0_EPPU_PRIVAL_SHIFT                    _MK_SHIFT_CONST(2)
+#define MC_FPRI_CTRL_EPP_0_EPPU_PRIVAL_FIELD                    (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_EPP_0_EPPU_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_EPP_0_EPPU_PRIVAL_RANGE                    3:2
+#define MC_FPRI_CTRL_EPP_0_EPPU_PRIVAL_WOFFSET                  0x0
+#define MC_FPRI_CTRL_EPP_0_EPPU_PRIVAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_EPP_0_EPPU_PRIVAL_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_EPP_0_EPPU_PRIVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_EPP_0_EPPU_PRIVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_EPP_0_EPPU_PRIVAL_INIT_ENUM                        LOWEST
+#define MC_FPRI_CTRL_EPP_0_EPPU_PRIVAL_LOWEST                   _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_EPP_0_EPPU_PRIVAL_LOW                      _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_EPP_0_EPPU_PRIVAL_MED                      _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_EPP_0_EPPU_PRIVAL_HIGH                     _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_EPP_0_EPPV_PRIVAL_SHIFT                    _MK_SHIFT_CONST(4)
+#define MC_FPRI_CTRL_EPP_0_EPPV_PRIVAL_FIELD                    (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_EPP_0_EPPV_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_EPP_0_EPPV_PRIVAL_RANGE                    5:4
+#define MC_FPRI_CTRL_EPP_0_EPPV_PRIVAL_WOFFSET                  0x0
+#define MC_FPRI_CTRL_EPP_0_EPPV_PRIVAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_EPP_0_EPPV_PRIVAL_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_EPP_0_EPPV_PRIVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_EPP_0_EPPV_PRIVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_EPP_0_EPPV_PRIVAL_INIT_ENUM                        LOWEST
+#define MC_FPRI_CTRL_EPP_0_EPPV_PRIVAL_LOWEST                   _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_EPP_0_EPPV_PRIVAL_LOW                      _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_EPP_0_EPPV_PRIVAL_MED                      _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_EPP_0_EPPV_PRIVAL_HIGH                     _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_EPP_0_EPPY_PRIVAL_SHIFT                    _MK_SHIFT_CONST(6)
+#define MC_FPRI_CTRL_EPP_0_EPPY_PRIVAL_FIELD                    (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_EPP_0_EPPY_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_EPP_0_EPPY_PRIVAL_RANGE                    7:6
+#define MC_FPRI_CTRL_EPP_0_EPPY_PRIVAL_WOFFSET                  0x0
+#define MC_FPRI_CTRL_EPP_0_EPPY_PRIVAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_EPP_0_EPPY_PRIVAL_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_EPP_0_EPPY_PRIVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_EPP_0_EPPY_PRIVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_EPP_0_EPPY_PRIVAL_INIT_ENUM                        LOWEST
+#define MC_FPRI_CTRL_EPP_0_EPPY_PRIVAL_LOWEST                   _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_EPP_0_EPPY_PRIVAL_LOW                      _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_EPP_0_EPPY_PRIVAL_MED                      _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_EPP_0_EPPY_PRIVAL_HIGH                     _MK_ENUM_CONST(3)
+
+
+// Register MC_FPRI_CTRL_G2_0  
+#define MC_FPRI_CTRL_G2_0                       _MK_ADDR_CONST(0xf8)
+#define MC_FPRI_CTRL_G2_0_WORD_COUNT                    0x1
+#define MC_FPRI_CTRL_G2_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_G2_0_RESET_MASK                    _MK_MASK_CONST(0xff)
+#define MC_FPRI_CTRL_G2_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_G2_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_G2_0_READ_MASK                     _MK_MASK_CONST(0xff)
+#define MC_FPRI_CTRL_G2_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
+#define MC_FPRI_CTRL_G2_0_G2PR_PRIVAL_SHIFT                     _MK_SHIFT_CONST(0)
+#define MC_FPRI_CTRL_G2_0_G2PR_PRIVAL_FIELD                     (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_G2_0_G2PR_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_G2_0_G2PR_PRIVAL_RANGE                     1:0
+#define MC_FPRI_CTRL_G2_0_G2PR_PRIVAL_WOFFSET                   0x0
+#define MC_FPRI_CTRL_G2_0_G2PR_PRIVAL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_G2_0_G2PR_PRIVAL_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_G2_0_G2PR_PRIVAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_G2_0_G2PR_PRIVAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_G2_0_G2PR_PRIVAL_INIT_ENUM                 LOWEST
+#define MC_FPRI_CTRL_G2_0_G2PR_PRIVAL_LOWEST                    _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_G2_0_G2PR_PRIVAL_LOW                       _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_G2_0_G2PR_PRIVAL_MED                       _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_G2_0_G2PR_PRIVAL_HIGH                      _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_G2_0_G2SR_PRIVAL_SHIFT                     _MK_SHIFT_CONST(2)
+#define MC_FPRI_CTRL_G2_0_G2SR_PRIVAL_FIELD                     (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_G2_0_G2SR_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_G2_0_G2SR_PRIVAL_RANGE                     3:2
+#define MC_FPRI_CTRL_G2_0_G2SR_PRIVAL_WOFFSET                   0x0
+#define MC_FPRI_CTRL_G2_0_G2SR_PRIVAL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_G2_0_G2SR_PRIVAL_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_G2_0_G2SR_PRIVAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_G2_0_G2SR_PRIVAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_G2_0_G2SR_PRIVAL_INIT_ENUM                 LOWEST
+#define MC_FPRI_CTRL_G2_0_G2SR_PRIVAL_LOWEST                    _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_G2_0_G2SR_PRIVAL_LOW                       _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_G2_0_G2SR_PRIVAL_MED                       _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_G2_0_G2SR_PRIVAL_HIGH                      _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_G2_0_G2DR_PRIVAL_SHIFT                     _MK_SHIFT_CONST(4)
+#define MC_FPRI_CTRL_G2_0_G2DR_PRIVAL_FIELD                     (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_G2_0_G2DR_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_G2_0_G2DR_PRIVAL_RANGE                     5:4
+#define MC_FPRI_CTRL_G2_0_G2DR_PRIVAL_WOFFSET                   0x0
+#define MC_FPRI_CTRL_G2_0_G2DR_PRIVAL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_G2_0_G2DR_PRIVAL_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_G2_0_G2DR_PRIVAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_G2_0_G2DR_PRIVAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_G2_0_G2DR_PRIVAL_INIT_ENUM                 LOWEST
+#define MC_FPRI_CTRL_G2_0_G2DR_PRIVAL_LOWEST                    _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_G2_0_G2DR_PRIVAL_LOW                       _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_G2_0_G2DR_PRIVAL_MED                       _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_G2_0_G2DR_PRIVAL_HIGH                      _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_G2_0_G2DW_PRIVAL_SHIFT                     _MK_SHIFT_CONST(6)
+#define MC_FPRI_CTRL_G2_0_G2DW_PRIVAL_FIELD                     (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_G2_0_G2DW_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_G2_0_G2DW_PRIVAL_RANGE                     7:6
+#define MC_FPRI_CTRL_G2_0_G2DW_PRIVAL_WOFFSET                   0x0
+#define MC_FPRI_CTRL_G2_0_G2DW_PRIVAL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_G2_0_G2DW_PRIVAL_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_G2_0_G2DW_PRIVAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_G2_0_G2DW_PRIVAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_G2_0_G2DW_PRIVAL_INIT_ENUM                 LOWEST
+#define MC_FPRI_CTRL_G2_0_G2DW_PRIVAL_LOWEST                    _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_G2_0_G2DW_PRIVAL_LOW                       _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_G2_0_G2DW_PRIVAL_MED                       _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_G2_0_G2DW_PRIVAL_HIGH                      _MK_ENUM_CONST(3)
+
+
+// Register MC_FPRI_CTRL_HC_0  
+#define MC_FPRI_CTRL_HC_0                       _MK_ADDR_CONST(0xfc)
+#define MC_FPRI_CTRL_HC_0_WORD_COUNT                    0x1
+#define MC_FPRI_CTRL_HC_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_HC_0_RESET_MASK                    _MK_MASK_CONST(0x3f)
+#define MC_FPRI_CTRL_HC_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_HC_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_HC_0_READ_MASK                     _MK_MASK_CONST(0x3f)
+#define MC_FPRI_CTRL_HC_0_WRITE_MASK                    _MK_MASK_CONST(0x3f)
+#define MC_FPRI_CTRL_HC_0_HOST1XDMAR_PRIVAL_SHIFT                       _MK_SHIFT_CONST(0)
+#define MC_FPRI_CTRL_HC_0_HOST1XDMAR_PRIVAL_FIELD                       (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_HC_0_HOST1XDMAR_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_HC_0_HOST1XDMAR_PRIVAL_RANGE                       1:0
+#define MC_FPRI_CTRL_HC_0_HOST1XDMAR_PRIVAL_WOFFSET                     0x0
+#define MC_FPRI_CTRL_HC_0_HOST1XDMAR_PRIVAL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_HC_0_HOST1XDMAR_PRIVAL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_HC_0_HOST1XDMAR_PRIVAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_HC_0_HOST1XDMAR_PRIVAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_HC_0_HOST1XDMAR_PRIVAL_INIT_ENUM                   LOWEST
+#define MC_FPRI_CTRL_HC_0_HOST1XDMAR_PRIVAL_LOWEST                      _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_HC_0_HOST1XDMAR_PRIVAL_LOW                 _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_HC_0_HOST1XDMAR_PRIVAL_MED                 _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_HC_0_HOST1XDMAR_PRIVAL_HIGH                        _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_HC_0_HOST1XR_PRIVAL_SHIFT                  _MK_SHIFT_CONST(2)
+#define MC_FPRI_CTRL_HC_0_HOST1XR_PRIVAL_FIELD                  (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_HC_0_HOST1XR_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_HC_0_HOST1XR_PRIVAL_RANGE                  3:2
+#define MC_FPRI_CTRL_HC_0_HOST1XR_PRIVAL_WOFFSET                        0x0
+#define MC_FPRI_CTRL_HC_0_HOST1XR_PRIVAL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_HC_0_HOST1XR_PRIVAL_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_HC_0_HOST1XR_PRIVAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_HC_0_HOST1XR_PRIVAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_HC_0_HOST1XR_PRIVAL_INIT_ENUM                      LOWEST
+#define MC_FPRI_CTRL_HC_0_HOST1XR_PRIVAL_LOWEST                 _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_HC_0_HOST1XR_PRIVAL_LOW                    _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_HC_0_HOST1XR_PRIVAL_MED                    _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_HC_0_HOST1XR_PRIVAL_HIGH                   _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_HC_0_HOST1XW_PRIVAL_SHIFT                  _MK_SHIFT_CONST(4)
+#define MC_FPRI_CTRL_HC_0_HOST1XW_PRIVAL_FIELD                  (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_HC_0_HOST1XW_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_HC_0_HOST1XW_PRIVAL_RANGE                  5:4
+#define MC_FPRI_CTRL_HC_0_HOST1XW_PRIVAL_WOFFSET                        0x0
+#define MC_FPRI_CTRL_HC_0_HOST1XW_PRIVAL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_HC_0_HOST1XW_PRIVAL_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_HC_0_HOST1XW_PRIVAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_HC_0_HOST1XW_PRIVAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_HC_0_HOST1XW_PRIVAL_INIT_ENUM                      LOWEST
+#define MC_FPRI_CTRL_HC_0_HOST1XW_PRIVAL_LOWEST                 _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_HC_0_HOST1XW_PRIVAL_LOW                    _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_HC_0_HOST1XW_PRIVAL_MED                    _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_HC_0_HOST1XW_PRIVAL_HIGH                   _MK_ENUM_CONST(3)
+
+
+// Register MC_FPRI_CTRL_ISP_0  
+#define MC_FPRI_CTRL_ISP_0                      _MK_ADDR_CONST(0x100)
+#define MC_FPRI_CTRL_ISP_0_WORD_COUNT                   0x1
+#define MC_FPRI_CTRL_ISP_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_ISP_0_RESET_MASK                   _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_ISP_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_ISP_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_ISP_0_READ_MASK                    _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_ISP_0_WRITE_MASK                   _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_ISP_0_ISPW_PRIVAL_SHIFT                    _MK_SHIFT_CONST(0)
+#define MC_FPRI_CTRL_ISP_0_ISPW_PRIVAL_FIELD                    (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_ISP_0_ISPW_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_ISP_0_ISPW_PRIVAL_RANGE                    1:0
+#define MC_FPRI_CTRL_ISP_0_ISPW_PRIVAL_WOFFSET                  0x0
+#define MC_FPRI_CTRL_ISP_0_ISPW_PRIVAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_ISP_0_ISPW_PRIVAL_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_ISP_0_ISPW_PRIVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_ISP_0_ISPW_PRIVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_ISP_0_ISPW_PRIVAL_INIT_ENUM                        LOWEST
+#define MC_FPRI_CTRL_ISP_0_ISPW_PRIVAL_LOWEST                   _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_ISP_0_ISPW_PRIVAL_LOW                      _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_ISP_0_ISPW_PRIVAL_MED                      _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_ISP_0_ISPW_PRIVAL_HIGH                     _MK_ENUM_CONST(3)
+
+
+// Register MC_FPRI_CTRL_MPCORE_0  
+#define MC_FPRI_CTRL_MPCORE_0                   _MK_ADDR_CONST(0x104)
+#define MC_FPRI_CTRL_MPCORE_0_WORD_COUNT                        0x1
+#define MC_FPRI_CTRL_MPCORE_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_MPCORE_0_RESET_MASK                        _MK_MASK_CONST(0xf)
+#define MC_FPRI_CTRL_MPCORE_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_MPCORE_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_MPCORE_0_READ_MASK                         _MK_MASK_CONST(0xf)
+#define MC_FPRI_CTRL_MPCORE_0_WRITE_MASK                        _MK_MASK_CONST(0xf)
+#define MC_FPRI_CTRL_MPCORE_0_MPCORER_PRIVAL_SHIFT                      _MK_SHIFT_CONST(0)
+#define MC_FPRI_CTRL_MPCORE_0_MPCORER_PRIVAL_FIELD                      (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_MPCORE_0_MPCORER_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_MPCORE_0_MPCORER_PRIVAL_RANGE                      1:0
+#define MC_FPRI_CTRL_MPCORE_0_MPCORER_PRIVAL_WOFFSET                    0x0
+#define MC_FPRI_CTRL_MPCORE_0_MPCORER_PRIVAL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_MPCORE_0_MPCORER_PRIVAL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_MPCORE_0_MPCORER_PRIVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_MPCORE_0_MPCORER_PRIVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_MPCORE_0_MPCORER_PRIVAL_INIT_ENUM                  LOWEST
+#define MC_FPRI_CTRL_MPCORE_0_MPCORER_PRIVAL_LOWEST                     _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_MPCORE_0_MPCORER_PRIVAL_LOW                        _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_MPCORE_0_MPCORER_PRIVAL_MED                        _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_MPCORE_0_MPCORER_PRIVAL_HIGH                       _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_MPCORE_0_MPCOREW_PRIVAL_SHIFT                      _MK_SHIFT_CONST(2)
+#define MC_FPRI_CTRL_MPCORE_0_MPCOREW_PRIVAL_FIELD                      (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_MPCORE_0_MPCOREW_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_MPCORE_0_MPCOREW_PRIVAL_RANGE                      3:2
+#define MC_FPRI_CTRL_MPCORE_0_MPCOREW_PRIVAL_WOFFSET                    0x0
+#define MC_FPRI_CTRL_MPCORE_0_MPCOREW_PRIVAL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_MPCORE_0_MPCOREW_PRIVAL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_MPCORE_0_MPCOREW_PRIVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_MPCORE_0_MPCOREW_PRIVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_MPCORE_0_MPCOREW_PRIVAL_INIT_ENUM                  LOWEST
+#define MC_FPRI_CTRL_MPCORE_0_MPCOREW_PRIVAL_LOWEST                     _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_MPCORE_0_MPCOREW_PRIVAL_LOW                        _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_MPCORE_0_MPCOREW_PRIVAL_MED                        _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_MPCORE_0_MPCOREW_PRIVAL_HIGH                       _MK_ENUM_CONST(3)
+
+
+// Register MC_FPRI_CTRL_MPEA_0  
+#define MC_FPRI_CTRL_MPEA_0                     _MK_ADDR_CONST(0x108)
+#define MC_FPRI_CTRL_MPEA_0_WORD_COUNT                  0x1
+#define MC_FPRI_CTRL_MPEA_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_MPEA_0_RESET_MASK                  _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_MPEA_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_MPEA_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_MPEA_0_READ_MASK                   _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_MPEA_0_WRITE_MASK                  _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_MPEA_0_MPEAMEMRD_PRIVAL_SHIFT                      _MK_SHIFT_CONST(0)
+#define MC_FPRI_CTRL_MPEA_0_MPEAMEMRD_PRIVAL_FIELD                      (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_MPEA_0_MPEAMEMRD_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_MPEA_0_MPEAMEMRD_PRIVAL_RANGE                      1:0
+#define MC_FPRI_CTRL_MPEA_0_MPEAMEMRD_PRIVAL_WOFFSET                    0x0
+#define MC_FPRI_CTRL_MPEA_0_MPEAMEMRD_PRIVAL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_MPEA_0_MPEAMEMRD_PRIVAL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_MPEA_0_MPEAMEMRD_PRIVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_MPEA_0_MPEAMEMRD_PRIVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_MPEA_0_MPEAMEMRD_PRIVAL_INIT_ENUM                  LOWEST
+#define MC_FPRI_CTRL_MPEA_0_MPEAMEMRD_PRIVAL_LOWEST                     _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_MPEA_0_MPEAMEMRD_PRIVAL_LOW                        _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_MPEA_0_MPEAMEMRD_PRIVAL_MED                        _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_MPEA_0_MPEAMEMRD_PRIVAL_HIGH                       _MK_ENUM_CONST(3)
+
+
+// Register MC_FPRI_CTRL_MPEB_0  
+#define MC_FPRI_CTRL_MPEB_0                     _MK_ADDR_CONST(0x10c)
+#define MC_FPRI_CTRL_MPEB_0_WORD_COUNT                  0x1
+#define MC_FPRI_CTRL_MPEB_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_MPEB_0_RESET_MASK                  _MK_MASK_CONST(0x3f)
+#define MC_FPRI_CTRL_MPEB_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_MPEB_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_MPEB_0_READ_MASK                   _MK_MASK_CONST(0x3f)
+#define MC_FPRI_CTRL_MPEB_0_WRITE_MASK                  _MK_MASK_CONST(0x3f)
+#define MC_FPRI_CTRL_MPEB_0_MPEUNIFBR_PRIVAL_SHIFT                      _MK_SHIFT_CONST(0)
+#define MC_FPRI_CTRL_MPEB_0_MPEUNIFBR_PRIVAL_FIELD                      (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_MPEB_0_MPEUNIFBR_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_MPEB_0_MPEUNIFBR_PRIVAL_RANGE                      1:0
+#define MC_FPRI_CTRL_MPEB_0_MPEUNIFBR_PRIVAL_WOFFSET                    0x0
+#define MC_FPRI_CTRL_MPEB_0_MPEUNIFBR_PRIVAL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_MPEB_0_MPEUNIFBR_PRIVAL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_MPEB_0_MPEUNIFBR_PRIVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_MPEB_0_MPEUNIFBR_PRIVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_MPEB_0_MPEUNIFBR_PRIVAL_INIT_ENUM                  LOWEST
+#define MC_FPRI_CTRL_MPEB_0_MPEUNIFBR_PRIVAL_LOWEST                     _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_MPEB_0_MPEUNIFBR_PRIVAL_LOW                        _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_MPEB_0_MPEUNIFBR_PRIVAL_MED                        _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_MPEB_0_MPEUNIFBR_PRIVAL_HIGH                       _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_MPEB_0_MPE_IPRED_PRIVAL_SHIFT                      _MK_SHIFT_CONST(2)
+#define MC_FPRI_CTRL_MPEB_0_MPE_IPRED_PRIVAL_FIELD                      (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_MPEB_0_MPE_IPRED_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_MPEB_0_MPE_IPRED_PRIVAL_RANGE                      3:2
+#define MC_FPRI_CTRL_MPEB_0_MPE_IPRED_PRIVAL_WOFFSET                    0x0
+#define MC_FPRI_CTRL_MPEB_0_MPE_IPRED_PRIVAL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_MPEB_0_MPE_IPRED_PRIVAL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_MPEB_0_MPE_IPRED_PRIVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_MPEB_0_MPE_IPRED_PRIVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_MPEB_0_MPE_IPRED_PRIVAL_INIT_ENUM                  LOWEST
+#define MC_FPRI_CTRL_MPEB_0_MPE_IPRED_PRIVAL_LOWEST                     _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_MPEB_0_MPE_IPRED_PRIVAL_LOW                        _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_MPEB_0_MPE_IPRED_PRIVAL_MED                        _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_MPEB_0_MPE_IPRED_PRIVAL_HIGH                       _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_MPEB_0_MPEUNIFBW_PRIVAL_SHIFT                      _MK_SHIFT_CONST(4)
+#define MC_FPRI_CTRL_MPEB_0_MPEUNIFBW_PRIVAL_FIELD                      (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_MPEB_0_MPEUNIFBW_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_MPEB_0_MPEUNIFBW_PRIVAL_RANGE                      5:4
+#define MC_FPRI_CTRL_MPEB_0_MPEUNIFBW_PRIVAL_WOFFSET                    0x0
+#define MC_FPRI_CTRL_MPEB_0_MPEUNIFBW_PRIVAL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_MPEB_0_MPEUNIFBW_PRIVAL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_MPEB_0_MPEUNIFBW_PRIVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_MPEB_0_MPEUNIFBW_PRIVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_MPEB_0_MPEUNIFBW_PRIVAL_INIT_ENUM                  LOWEST
+#define MC_FPRI_CTRL_MPEB_0_MPEUNIFBW_PRIVAL_LOWEST                     _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_MPEB_0_MPEUNIFBW_PRIVAL_LOW                        _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_MPEB_0_MPEUNIFBW_PRIVAL_MED                        _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_MPEB_0_MPEUNIFBW_PRIVAL_HIGH                       _MK_ENUM_CONST(3)
+
+
+// Register MC_FPRI_CTRL_MPEC_0  
+#define MC_FPRI_CTRL_MPEC_0                     _MK_ADDR_CONST(0x110)
+#define MC_FPRI_CTRL_MPEC_0_WORD_COUNT                  0x1
+#define MC_FPRI_CTRL_MPEC_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_MPEC_0_RESET_MASK                  _MK_MASK_CONST(0xf)
+#define MC_FPRI_CTRL_MPEC_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_MPEC_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_MPEC_0_READ_MASK                   _MK_MASK_CONST(0xf)
+#define MC_FPRI_CTRL_MPEC_0_WRITE_MASK                  _MK_MASK_CONST(0xf)
+#define MC_FPRI_CTRL_MPEC_0_MPECSRD_PRIVAL_SHIFT                        _MK_SHIFT_CONST(0)
+#define MC_FPRI_CTRL_MPEC_0_MPECSRD_PRIVAL_FIELD                        (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_MPEC_0_MPECSRD_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_MPEC_0_MPECSRD_PRIVAL_RANGE                        1:0
+#define MC_FPRI_CTRL_MPEC_0_MPECSRD_PRIVAL_WOFFSET                      0x0
+#define MC_FPRI_CTRL_MPEC_0_MPECSRD_PRIVAL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_MPEC_0_MPECSRD_PRIVAL_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_MPEC_0_MPECSRD_PRIVAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_MPEC_0_MPECSRD_PRIVAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_MPEC_0_MPECSRD_PRIVAL_INIT_ENUM                    LOWEST
+#define MC_FPRI_CTRL_MPEC_0_MPECSRD_PRIVAL_LOWEST                       _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_MPEC_0_MPECSRD_PRIVAL_LOW                  _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_MPEC_0_MPECSRD_PRIVAL_MED                  _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_MPEC_0_MPECSRD_PRIVAL_HIGH                 _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_MPEC_0_MPECSWR_PRIVAL_SHIFT                        _MK_SHIFT_CONST(2)
+#define MC_FPRI_CTRL_MPEC_0_MPECSWR_PRIVAL_FIELD                        (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_MPEC_0_MPECSWR_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_MPEC_0_MPECSWR_PRIVAL_RANGE                        3:2
+#define MC_FPRI_CTRL_MPEC_0_MPECSWR_PRIVAL_WOFFSET                      0x0
+#define MC_FPRI_CTRL_MPEC_0_MPECSWR_PRIVAL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_MPEC_0_MPECSWR_PRIVAL_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_MPEC_0_MPECSWR_PRIVAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_MPEC_0_MPECSWR_PRIVAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_MPEC_0_MPECSWR_PRIVAL_INIT_ENUM                    LOWEST
+#define MC_FPRI_CTRL_MPEC_0_MPECSWR_PRIVAL_LOWEST                       _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_MPEC_0_MPECSWR_PRIVAL_LOW                  _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_MPEC_0_MPECSWR_PRIVAL_MED                  _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_MPEC_0_MPECSWR_PRIVAL_HIGH                 _MK_ENUM_CONST(3)
+
+
+// Register MC_FPRI_CTRL_NV_0  
+#define MC_FPRI_CTRL_NV_0                       _MK_ADDR_CONST(0x114)
+#define MC_FPRI_CTRL_NV_0_WORD_COUNT                    0x1
+#define MC_FPRI_CTRL_NV_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_NV_0_RESET_MASK                    _MK_MASK_CONST(0xff)
+#define MC_FPRI_CTRL_NV_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_NV_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_NV_0_READ_MASK                     _MK_MASK_CONST(0xff)
+#define MC_FPRI_CTRL_NV_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
+#define MC_FPRI_CTRL_NV_0_FDCDRD_PRIVAL_SHIFT                   _MK_SHIFT_CONST(0)
+#define MC_FPRI_CTRL_NV_0_FDCDRD_PRIVAL_FIELD                   (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_NV_0_FDCDRD_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_NV_0_FDCDRD_PRIVAL_RANGE                   1:0
+#define MC_FPRI_CTRL_NV_0_FDCDRD_PRIVAL_WOFFSET                 0x0
+#define MC_FPRI_CTRL_NV_0_FDCDRD_PRIVAL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_NV_0_FDCDRD_PRIVAL_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_NV_0_FDCDRD_PRIVAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_NV_0_FDCDRD_PRIVAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_NV_0_FDCDRD_PRIVAL_INIT_ENUM                       LOWEST
+#define MC_FPRI_CTRL_NV_0_FDCDRD_PRIVAL_LOWEST                  _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_NV_0_FDCDRD_PRIVAL_LOW                     _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_NV_0_FDCDRD_PRIVAL_MED                     _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_NV_0_FDCDRD_PRIVAL_HIGH                    _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_NV_0_IDXSRD_PRIVAL_SHIFT                   _MK_SHIFT_CONST(2)
+#define MC_FPRI_CTRL_NV_0_IDXSRD_PRIVAL_FIELD                   (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_NV_0_IDXSRD_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_NV_0_IDXSRD_PRIVAL_RANGE                   3:2
+#define MC_FPRI_CTRL_NV_0_IDXSRD_PRIVAL_WOFFSET                 0x0
+#define MC_FPRI_CTRL_NV_0_IDXSRD_PRIVAL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_NV_0_IDXSRD_PRIVAL_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_NV_0_IDXSRD_PRIVAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_NV_0_IDXSRD_PRIVAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_NV_0_IDXSRD_PRIVAL_INIT_ENUM                       LOWEST
+#define MC_FPRI_CTRL_NV_0_IDXSRD_PRIVAL_LOWEST                  _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_NV_0_IDXSRD_PRIVAL_LOW                     _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_NV_0_IDXSRD_PRIVAL_MED                     _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_NV_0_IDXSRD_PRIVAL_HIGH                    _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_NV_0_TEXSRD_PRIVAL_SHIFT                   _MK_SHIFT_CONST(4)
+#define MC_FPRI_CTRL_NV_0_TEXSRD_PRIVAL_FIELD                   (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_NV_0_TEXSRD_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_NV_0_TEXSRD_PRIVAL_RANGE                   5:4
+#define MC_FPRI_CTRL_NV_0_TEXSRD_PRIVAL_WOFFSET                 0x0
+#define MC_FPRI_CTRL_NV_0_TEXSRD_PRIVAL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_NV_0_TEXSRD_PRIVAL_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_NV_0_TEXSRD_PRIVAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_NV_0_TEXSRD_PRIVAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_NV_0_TEXSRD_PRIVAL_INIT_ENUM                       LOWEST
+#define MC_FPRI_CTRL_NV_0_TEXSRD_PRIVAL_LOWEST                  _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_NV_0_TEXSRD_PRIVAL_LOW                     _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_NV_0_TEXSRD_PRIVAL_MED                     _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_NV_0_TEXSRD_PRIVAL_HIGH                    _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_NV_0_FDCDWR_PRIVAL_SHIFT                   _MK_SHIFT_CONST(6)
+#define MC_FPRI_CTRL_NV_0_FDCDWR_PRIVAL_FIELD                   (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_NV_0_FDCDWR_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_NV_0_FDCDWR_PRIVAL_RANGE                   7:6
+#define MC_FPRI_CTRL_NV_0_FDCDWR_PRIVAL_WOFFSET                 0x0
+#define MC_FPRI_CTRL_NV_0_FDCDWR_PRIVAL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_NV_0_FDCDWR_PRIVAL_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_NV_0_FDCDWR_PRIVAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_NV_0_FDCDWR_PRIVAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_NV_0_FDCDWR_PRIVAL_INIT_ENUM                       LOWEST
+#define MC_FPRI_CTRL_NV_0_FDCDWR_PRIVAL_LOWEST                  _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_NV_0_FDCDWR_PRIVAL_LOW                     _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_NV_0_FDCDWR_PRIVAL_MED                     _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_NV_0_FDCDWR_PRIVAL_HIGH                    _MK_ENUM_CONST(3)
+
+
+// Register MC_FPRI_CTRL_PPCS_0  
+#define MC_FPRI_CTRL_PPCS_0                     _MK_ADDR_CONST(0x118)
+#define MC_FPRI_CTRL_PPCS_0_WORD_COUNT                  0x1
+#define MC_FPRI_CTRL_PPCS_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_PPCS_0_RESET_MASK                  _MK_MASK_CONST(0xfff)
+#define MC_FPRI_CTRL_PPCS_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_PPCS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_PPCS_0_READ_MASK                   _MK_MASK_CONST(0xfff)
+#define MC_FPRI_CTRL_PPCS_0_WRITE_MASK                  _MK_MASK_CONST(0xfff)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBDMAR_PRIVAL_SHIFT                    _MK_SHIFT_CONST(0)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBDMAR_PRIVAL_FIELD                    (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_PPCS_0_PPCSAHBDMAR_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBDMAR_PRIVAL_RANGE                    1:0
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBDMAR_PRIVAL_WOFFSET                  0x0
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBDMAR_PRIVAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBDMAR_PRIVAL_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBDMAR_PRIVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBDMAR_PRIVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBDMAR_PRIVAL_INIT_ENUM                        LOWEST
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBDMAR_PRIVAL_LOWEST                   _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBDMAR_PRIVAL_LOW                      _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBDMAR_PRIVAL_MED                      _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBDMAR_PRIVAL_HIGH                     _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBSLVR_PRIVAL_SHIFT                    _MK_SHIFT_CONST(2)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBSLVR_PRIVAL_FIELD                    (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_PPCS_0_PPCSAHBSLVR_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBSLVR_PRIVAL_RANGE                    3:2
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBSLVR_PRIVAL_WOFFSET                  0x0
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBSLVR_PRIVAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBSLVR_PRIVAL_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBSLVR_PRIVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBSLVR_PRIVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBSLVR_PRIVAL_INIT_ENUM                        LOWEST
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBSLVR_PRIVAL_LOWEST                   _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBSLVR_PRIVAL_LOW                      _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBSLVR_PRIVAL_MED                      _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBSLVR_PRIVAL_HIGH                     _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_PPCS_0_PPCSARM7R_PRIVAL_SHIFT                      _MK_SHIFT_CONST(4)
+#define MC_FPRI_CTRL_PPCS_0_PPCSARM7R_PRIVAL_FIELD                      (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_PPCS_0_PPCSARM7R_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_PPCS_0_PPCSARM7R_PRIVAL_RANGE                      5:4
+#define MC_FPRI_CTRL_PPCS_0_PPCSARM7R_PRIVAL_WOFFSET                    0x0
+#define MC_FPRI_CTRL_PPCS_0_PPCSARM7R_PRIVAL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_PPCS_0_PPCSARM7R_PRIVAL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_PPCS_0_PPCSARM7R_PRIVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_PPCS_0_PPCSARM7R_PRIVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_PPCS_0_PPCSARM7R_PRIVAL_INIT_ENUM                  LOWEST
+#define MC_FPRI_CTRL_PPCS_0_PPCSARM7R_PRIVAL_LOWEST                     _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_PPCS_0_PPCSARM7R_PRIVAL_LOW                        _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_PPCS_0_PPCSARM7R_PRIVAL_MED                        _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_PPCS_0_PPCSARM7R_PRIVAL_HIGH                       _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBDMAW_PRIVAL_SHIFT                    _MK_SHIFT_CONST(6)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBDMAW_PRIVAL_FIELD                    (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_PPCS_0_PPCSAHBDMAW_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBDMAW_PRIVAL_RANGE                    7:6
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBDMAW_PRIVAL_WOFFSET                  0x0
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBDMAW_PRIVAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBDMAW_PRIVAL_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBDMAW_PRIVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBDMAW_PRIVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBDMAW_PRIVAL_INIT_ENUM                        LOWEST
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBDMAW_PRIVAL_LOWEST                   _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBDMAW_PRIVAL_LOW                      _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBDMAW_PRIVAL_MED                      _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBDMAW_PRIVAL_HIGH                     _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBSLVW_PRIVAL_SHIFT                    _MK_SHIFT_CONST(8)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBSLVW_PRIVAL_FIELD                    (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_PPCS_0_PPCSAHBSLVW_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBSLVW_PRIVAL_RANGE                    9:8
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBSLVW_PRIVAL_WOFFSET                  0x0
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBSLVW_PRIVAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBSLVW_PRIVAL_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBSLVW_PRIVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBSLVW_PRIVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBSLVW_PRIVAL_INIT_ENUM                        LOWEST
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBSLVW_PRIVAL_LOWEST                   _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBSLVW_PRIVAL_LOW                      _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBSLVW_PRIVAL_MED                      _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBSLVW_PRIVAL_HIGH                     _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_PPCS_0_PPCSARM7W_PRIVAL_SHIFT                      _MK_SHIFT_CONST(10)
+#define MC_FPRI_CTRL_PPCS_0_PPCSARM7W_PRIVAL_FIELD                      (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_PPCS_0_PPCSARM7W_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_PPCS_0_PPCSARM7W_PRIVAL_RANGE                      11:10
+#define MC_FPRI_CTRL_PPCS_0_PPCSARM7W_PRIVAL_WOFFSET                    0x0
+#define MC_FPRI_CTRL_PPCS_0_PPCSARM7W_PRIVAL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_PPCS_0_PPCSARM7W_PRIVAL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_PPCS_0_PPCSARM7W_PRIVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_PPCS_0_PPCSARM7W_PRIVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_PPCS_0_PPCSARM7W_PRIVAL_INIT_ENUM                  LOWEST
+#define MC_FPRI_CTRL_PPCS_0_PPCSARM7W_PRIVAL_LOWEST                     _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_PPCS_0_PPCSARM7W_PRIVAL_LOW                        _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_PPCS_0_PPCSARM7W_PRIVAL_MED                        _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_PPCS_0_PPCSARM7W_PRIVAL_HIGH                       _MK_ENUM_CONST(3)
+
+
+// Register MC_FPRI_CTRL_VDE_0  
+#define MC_FPRI_CTRL_VDE_0                      _MK_ADDR_CONST(0x11c)
+#define MC_FPRI_CTRL_VDE_0_WORD_COUNT                   0x1
+#define MC_FPRI_CTRL_VDE_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VDE_0_RESET_MASK                   _MK_MASK_CONST(0x3ffff)
+#define MC_FPRI_CTRL_VDE_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VDE_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VDE_0_READ_MASK                    _MK_MASK_CONST(0x3ffff)
+#define MC_FPRI_CTRL_VDE_0_WRITE_MASK                   _MK_MASK_CONST(0x3ffff)
+#define MC_FPRI_CTRL_VDE_0_VDEBSEAR_PRIVAL_SHIFT                        _MK_SHIFT_CONST(0)
+#define MC_FPRI_CTRL_VDE_0_VDEBSEAR_PRIVAL_FIELD                        (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_VDE_0_VDEBSEAR_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_VDE_0_VDEBSEAR_PRIVAL_RANGE                        1:0
+#define MC_FPRI_CTRL_VDE_0_VDEBSEAR_PRIVAL_WOFFSET                      0x0
+#define MC_FPRI_CTRL_VDE_0_VDEBSEAR_PRIVAL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VDE_0_VDEBSEAR_PRIVAL_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_VDE_0_VDEBSEAR_PRIVAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VDE_0_VDEBSEAR_PRIVAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VDE_0_VDEBSEAR_PRIVAL_INIT_ENUM                    LOWEST
+#define MC_FPRI_CTRL_VDE_0_VDEBSEAR_PRIVAL_LOWEST                       _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_VDE_0_VDEBSEAR_PRIVAL_LOW                  _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_VDE_0_VDEBSEAR_PRIVAL_MED                  _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_VDE_0_VDEBSEAR_PRIVAL_HIGH                 _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_VDE_0_VDEBSEVR_PRIVAL_SHIFT                        _MK_SHIFT_CONST(2)
+#define MC_FPRI_CTRL_VDE_0_VDEBSEVR_PRIVAL_FIELD                        (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_VDE_0_VDEBSEVR_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_VDE_0_VDEBSEVR_PRIVAL_RANGE                        3:2
+#define MC_FPRI_CTRL_VDE_0_VDEBSEVR_PRIVAL_WOFFSET                      0x0
+#define MC_FPRI_CTRL_VDE_0_VDEBSEVR_PRIVAL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VDE_0_VDEBSEVR_PRIVAL_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_VDE_0_VDEBSEVR_PRIVAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VDE_0_VDEBSEVR_PRIVAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VDE_0_VDEBSEVR_PRIVAL_INIT_ENUM                    LOWEST
+#define MC_FPRI_CTRL_VDE_0_VDEBSEVR_PRIVAL_LOWEST                       _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_VDE_0_VDEBSEVR_PRIVAL_LOW                  _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_VDE_0_VDEBSEVR_PRIVAL_MED                  _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_VDE_0_VDEBSEVR_PRIVAL_HIGH                 _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_VDE_0_VDEMBER_PRIVAL_SHIFT                 _MK_SHIFT_CONST(4)
+#define MC_FPRI_CTRL_VDE_0_VDEMBER_PRIVAL_FIELD                 (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_VDE_0_VDEMBER_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_VDE_0_VDEMBER_PRIVAL_RANGE                 5:4
+#define MC_FPRI_CTRL_VDE_0_VDEMBER_PRIVAL_WOFFSET                       0x0
+#define MC_FPRI_CTRL_VDE_0_VDEMBER_PRIVAL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VDE_0_VDEMBER_PRIVAL_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_VDE_0_VDEMBER_PRIVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VDE_0_VDEMBER_PRIVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VDE_0_VDEMBER_PRIVAL_INIT_ENUM                     LOWEST
+#define MC_FPRI_CTRL_VDE_0_VDEMBER_PRIVAL_LOWEST                        _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_VDE_0_VDEMBER_PRIVAL_LOW                   _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_VDE_0_VDEMBER_PRIVAL_MED                   _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_VDE_0_VDEMBER_PRIVAL_HIGH                  _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_VDE_0_VDEMCER_PRIVAL_SHIFT                 _MK_SHIFT_CONST(6)
+#define MC_FPRI_CTRL_VDE_0_VDEMCER_PRIVAL_FIELD                 (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_VDE_0_VDEMCER_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_VDE_0_VDEMCER_PRIVAL_RANGE                 7:6
+#define MC_FPRI_CTRL_VDE_0_VDEMCER_PRIVAL_WOFFSET                       0x0
+#define MC_FPRI_CTRL_VDE_0_VDEMCER_PRIVAL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VDE_0_VDEMCER_PRIVAL_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_VDE_0_VDEMCER_PRIVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VDE_0_VDEMCER_PRIVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VDE_0_VDEMCER_PRIVAL_INIT_ENUM                     LOWEST
+#define MC_FPRI_CTRL_VDE_0_VDEMCER_PRIVAL_LOWEST                        _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_VDE_0_VDEMCER_PRIVAL_LOW                   _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_VDE_0_VDEMCER_PRIVAL_MED                   _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_VDE_0_VDEMCER_PRIVAL_HIGH                  _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_VDE_0_VDETPER_PRIVAL_SHIFT                 _MK_SHIFT_CONST(8)
+#define MC_FPRI_CTRL_VDE_0_VDETPER_PRIVAL_FIELD                 (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_VDE_0_VDETPER_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_VDE_0_VDETPER_PRIVAL_RANGE                 9:8
+#define MC_FPRI_CTRL_VDE_0_VDETPER_PRIVAL_WOFFSET                       0x0
+#define MC_FPRI_CTRL_VDE_0_VDETPER_PRIVAL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VDE_0_VDETPER_PRIVAL_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_VDE_0_VDETPER_PRIVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VDE_0_VDETPER_PRIVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VDE_0_VDETPER_PRIVAL_INIT_ENUM                     LOWEST
+#define MC_FPRI_CTRL_VDE_0_VDETPER_PRIVAL_LOWEST                        _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_VDE_0_VDETPER_PRIVAL_LOW                   _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_VDE_0_VDETPER_PRIVAL_MED                   _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_VDE_0_VDETPER_PRIVAL_HIGH                  _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_VDE_0_VDEBSEAW_PRIVAL_SHIFT                        _MK_SHIFT_CONST(10)
+#define MC_FPRI_CTRL_VDE_0_VDEBSEAW_PRIVAL_FIELD                        (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_VDE_0_VDEBSEAW_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_VDE_0_VDEBSEAW_PRIVAL_RANGE                        11:10
+#define MC_FPRI_CTRL_VDE_0_VDEBSEAW_PRIVAL_WOFFSET                      0x0
+#define MC_FPRI_CTRL_VDE_0_VDEBSEAW_PRIVAL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VDE_0_VDEBSEAW_PRIVAL_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_VDE_0_VDEBSEAW_PRIVAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VDE_0_VDEBSEAW_PRIVAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VDE_0_VDEBSEAW_PRIVAL_INIT_ENUM                    LOWEST
+#define MC_FPRI_CTRL_VDE_0_VDEBSEAW_PRIVAL_LOWEST                       _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_VDE_0_VDEBSEAW_PRIVAL_LOW                  _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_VDE_0_VDEBSEAW_PRIVAL_MED                  _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_VDE_0_VDEBSEAW_PRIVAL_HIGH                 _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_VDE_0_VDEBSEVW_PRIVAL_SHIFT                        _MK_SHIFT_CONST(12)
+#define MC_FPRI_CTRL_VDE_0_VDEBSEVW_PRIVAL_FIELD                        (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_VDE_0_VDEBSEVW_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_VDE_0_VDEBSEVW_PRIVAL_RANGE                        13:12
+#define MC_FPRI_CTRL_VDE_0_VDEBSEVW_PRIVAL_WOFFSET                      0x0
+#define MC_FPRI_CTRL_VDE_0_VDEBSEVW_PRIVAL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VDE_0_VDEBSEVW_PRIVAL_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_VDE_0_VDEBSEVW_PRIVAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VDE_0_VDEBSEVW_PRIVAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VDE_0_VDEBSEVW_PRIVAL_INIT_ENUM                    LOWEST
+#define MC_FPRI_CTRL_VDE_0_VDEBSEVW_PRIVAL_LOWEST                       _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_VDE_0_VDEBSEVW_PRIVAL_LOW                  _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_VDE_0_VDEBSEVW_PRIVAL_MED                  _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_VDE_0_VDEBSEVW_PRIVAL_HIGH                 _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_VDE_0_VDEMBEW_PRIVAL_SHIFT                 _MK_SHIFT_CONST(14)
+#define MC_FPRI_CTRL_VDE_0_VDEMBEW_PRIVAL_FIELD                 (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_VDE_0_VDEMBEW_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_VDE_0_VDEMBEW_PRIVAL_RANGE                 15:14
+#define MC_FPRI_CTRL_VDE_0_VDEMBEW_PRIVAL_WOFFSET                       0x0
+#define MC_FPRI_CTRL_VDE_0_VDEMBEW_PRIVAL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VDE_0_VDEMBEW_PRIVAL_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_VDE_0_VDEMBEW_PRIVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VDE_0_VDEMBEW_PRIVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VDE_0_VDEMBEW_PRIVAL_INIT_ENUM                     LOWEST
+#define MC_FPRI_CTRL_VDE_0_VDEMBEW_PRIVAL_LOWEST                        _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_VDE_0_VDEMBEW_PRIVAL_LOW                   _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_VDE_0_VDEMBEW_PRIVAL_MED                   _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_VDE_0_VDEMBEW_PRIVAL_HIGH                  _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_VDE_0_VDETPMW_PRIVAL_SHIFT                 _MK_SHIFT_CONST(16)
+#define MC_FPRI_CTRL_VDE_0_VDETPMW_PRIVAL_FIELD                 (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_VDE_0_VDETPMW_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_VDE_0_VDETPMW_PRIVAL_RANGE                 17:16
+#define MC_FPRI_CTRL_VDE_0_VDETPMW_PRIVAL_WOFFSET                       0x0
+#define MC_FPRI_CTRL_VDE_0_VDETPMW_PRIVAL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VDE_0_VDETPMW_PRIVAL_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_VDE_0_VDETPMW_PRIVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VDE_0_VDETPMW_PRIVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VDE_0_VDETPMW_PRIVAL_INIT_ENUM                     LOWEST
+#define MC_FPRI_CTRL_VDE_0_VDETPMW_PRIVAL_LOWEST                        _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_VDE_0_VDETPMW_PRIVAL_LOW                   _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_VDE_0_VDETPMW_PRIVAL_MED                   _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_VDE_0_VDETPMW_PRIVAL_HIGH                  _MK_ENUM_CONST(3)
+
+
+// Register MC_FPRI_CTRL_VI_0  
+#define MC_FPRI_CTRL_VI_0                       _MK_ADDR_CONST(0x120)
+#define MC_FPRI_CTRL_VI_0_WORD_COUNT                    0x1
+#define MC_FPRI_CTRL_VI_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VI_0_RESET_MASK                    _MK_MASK_CONST(0x3ff)
+#define MC_FPRI_CTRL_VI_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VI_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VI_0_READ_MASK                     _MK_MASK_CONST(0x3ff)
+#define MC_FPRI_CTRL_VI_0_WRITE_MASK                    _MK_MASK_CONST(0x3ff)
+#define MC_FPRI_CTRL_VI_0_VIRUV_PRIVAL_SHIFT                    _MK_SHIFT_CONST(0)
+#define MC_FPRI_CTRL_VI_0_VIRUV_PRIVAL_FIELD                    (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_VI_0_VIRUV_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_VI_0_VIRUV_PRIVAL_RANGE                    1:0
+#define MC_FPRI_CTRL_VI_0_VIRUV_PRIVAL_WOFFSET                  0x0
+#define MC_FPRI_CTRL_VI_0_VIRUV_PRIVAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VI_0_VIRUV_PRIVAL_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_VI_0_VIRUV_PRIVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VI_0_VIRUV_PRIVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VI_0_VIRUV_PRIVAL_INIT_ENUM                        LOWEST
+#define MC_FPRI_CTRL_VI_0_VIRUV_PRIVAL_LOWEST                   _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_VI_0_VIRUV_PRIVAL_LOW                      _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_VI_0_VIRUV_PRIVAL_MED                      _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_VI_0_VIRUV_PRIVAL_HIGH                     _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_VI_0_VIWSB_PRIVAL_SHIFT                    _MK_SHIFT_CONST(2)
+#define MC_FPRI_CTRL_VI_0_VIWSB_PRIVAL_FIELD                    (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_VI_0_VIWSB_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_VI_0_VIWSB_PRIVAL_RANGE                    3:2
+#define MC_FPRI_CTRL_VI_0_VIWSB_PRIVAL_WOFFSET                  0x0
+#define MC_FPRI_CTRL_VI_0_VIWSB_PRIVAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VI_0_VIWSB_PRIVAL_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_VI_0_VIWSB_PRIVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VI_0_VIWSB_PRIVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VI_0_VIWSB_PRIVAL_INIT_ENUM                        LOWEST
+#define MC_FPRI_CTRL_VI_0_VIWSB_PRIVAL_LOWEST                   _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_VI_0_VIWSB_PRIVAL_LOW                      _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_VI_0_VIWSB_PRIVAL_MED                      _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_VI_0_VIWSB_PRIVAL_HIGH                     _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_VI_0_VIWU_PRIVAL_SHIFT                     _MK_SHIFT_CONST(4)
+#define MC_FPRI_CTRL_VI_0_VIWU_PRIVAL_FIELD                     (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_VI_0_VIWU_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_VI_0_VIWU_PRIVAL_RANGE                     5:4
+#define MC_FPRI_CTRL_VI_0_VIWU_PRIVAL_WOFFSET                   0x0
+#define MC_FPRI_CTRL_VI_0_VIWU_PRIVAL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VI_0_VIWU_PRIVAL_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_VI_0_VIWU_PRIVAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VI_0_VIWU_PRIVAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VI_0_VIWU_PRIVAL_INIT_ENUM                 LOWEST
+#define MC_FPRI_CTRL_VI_0_VIWU_PRIVAL_LOWEST                    _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_VI_0_VIWU_PRIVAL_LOW                       _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_VI_0_VIWU_PRIVAL_MED                       _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_VI_0_VIWU_PRIVAL_HIGH                      _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_VI_0_VIWV_PRIVAL_SHIFT                     _MK_SHIFT_CONST(6)
+#define MC_FPRI_CTRL_VI_0_VIWV_PRIVAL_FIELD                     (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_VI_0_VIWV_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_VI_0_VIWV_PRIVAL_RANGE                     7:6
+#define MC_FPRI_CTRL_VI_0_VIWV_PRIVAL_WOFFSET                   0x0
+#define MC_FPRI_CTRL_VI_0_VIWV_PRIVAL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VI_0_VIWV_PRIVAL_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_VI_0_VIWV_PRIVAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VI_0_VIWV_PRIVAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VI_0_VIWV_PRIVAL_INIT_ENUM                 LOWEST
+#define MC_FPRI_CTRL_VI_0_VIWV_PRIVAL_LOWEST                    _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_VI_0_VIWV_PRIVAL_LOW                       _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_VI_0_VIWV_PRIVAL_MED                       _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_VI_0_VIWV_PRIVAL_HIGH                      _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_VI_0_VIWY_PRIVAL_SHIFT                     _MK_SHIFT_CONST(8)
+#define MC_FPRI_CTRL_VI_0_VIWY_PRIVAL_FIELD                     (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_VI_0_VIWY_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_VI_0_VIWY_PRIVAL_RANGE                     9:8
+#define MC_FPRI_CTRL_VI_0_VIWY_PRIVAL_WOFFSET                   0x0
+#define MC_FPRI_CTRL_VI_0_VIWY_PRIVAL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VI_0_VIWY_PRIVAL_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_VI_0_VIWY_PRIVAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VI_0_VIWY_PRIVAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VI_0_VIWY_PRIVAL_INIT_ENUM                 LOWEST
+#define MC_FPRI_CTRL_VI_0_VIWY_PRIVAL_LOWEST                    _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_VI_0_VIWY_PRIVAL_LOW                       _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_VI_0_VIWY_PRIVAL_MED                       _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_VI_0_VIWY_PRIVAL_HIGH                      _MK_ENUM_CONST(3)
+
+
+// Register MC_TIMEOUT_CMC_0  
+#define MC_TIMEOUT_CMC_0                        _MK_ADDR_CONST(0x124)
+#define MC_TIMEOUT_CMC_0_WORD_COUNT                     0x1
+#define MC_TIMEOUT_CMC_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_CMC_0_RESET_MASK                     _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_CMC_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_CMC_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_CMC_0_READ_MASK                      _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_CMC_0_WRITE_MASK                     _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_CMC_0_CMCR_TMVAL_SHIFT                       _MK_SHIFT_CONST(0)
+#define MC_TIMEOUT_CMC_0_CMCR_TMVAL_FIELD                       (_MK_MASK_CONST(0xf) << MC_TIMEOUT_CMC_0_CMCR_TMVAL_SHIFT)
+#define MC_TIMEOUT_CMC_0_CMCR_TMVAL_RANGE                       3:0
+#define MC_TIMEOUT_CMC_0_CMCR_TMVAL_WOFFSET                     0x0
+#define MC_TIMEOUT_CMC_0_CMCR_TMVAL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_CMC_0_CMCR_TMVAL_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_CMC_0_CMCR_TMVAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_CMC_0_CMCR_TMVAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_CMC_0_CMCW_TMVAL_SHIFT                       _MK_SHIFT_CONST(4)
+#define MC_TIMEOUT_CMC_0_CMCW_TMVAL_FIELD                       (_MK_MASK_CONST(0xf) << MC_TIMEOUT_CMC_0_CMCW_TMVAL_SHIFT)
+#define MC_TIMEOUT_CMC_0_CMCW_TMVAL_RANGE                       7:4
+#define MC_TIMEOUT_CMC_0_CMCW_TMVAL_WOFFSET                     0x0
+#define MC_TIMEOUT_CMC_0_CMCW_TMVAL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_CMC_0_CMCW_TMVAL_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_CMC_0_CMCW_TMVAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_CMC_0_CMCW_TMVAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register MC_TIMEOUT_DC_0  
+#define MC_TIMEOUT_DC_0                 _MK_ADDR_CONST(0x128)
+#define MC_TIMEOUT_DC_0_WORD_COUNT                      0x1
+#define MC_TIMEOUT_DC_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_DC_0_RESET_MASK                      _MK_MASK_CONST(0xfffff)
+#define MC_TIMEOUT_DC_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_DC_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_DC_0_READ_MASK                       _MK_MASK_CONST(0xfffff)
+#define MC_TIMEOUT_DC_0_WRITE_MASK                      _MK_MASK_CONST(0xfffff)
+#define MC_TIMEOUT_DC_0_DISPLAY0A_TMVAL_SHIFT                   _MK_SHIFT_CONST(0)
+#define MC_TIMEOUT_DC_0_DISPLAY0A_TMVAL_FIELD                   (_MK_MASK_CONST(0xf) << MC_TIMEOUT_DC_0_DISPLAY0A_TMVAL_SHIFT)
+#define MC_TIMEOUT_DC_0_DISPLAY0A_TMVAL_RANGE                   3:0
+#define MC_TIMEOUT_DC_0_DISPLAY0A_TMVAL_WOFFSET                 0x0
+#define MC_TIMEOUT_DC_0_DISPLAY0A_TMVAL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_DC_0_DISPLAY0A_TMVAL_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_DC_0_DISPLAY0A_TMVAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_DC_0_DISPLAY0A_TMVAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_DC_0_DISPLAY0B_TMVAL_SHIFT                   _MK_SHIFT_CONST(4)
+#define MC_TIMEOUT_DC_0_DISPLAY0B_TMVAL_FIELD                   (_MK_MASK_CONST(0xf) << MC_TIMEOUT_DC_0_DISPLAY0B_TMVAL_SHIFT)
+#define MC_TIMEOUT_DC_0_DISPLAY0B_TMVAL_RANGE                   7:4
+#define MC_TIMEOUT_DC_0_DISPLAY0B_TMVAL_WOFFSET                 0x0
+#define MC_TIMEOUT_DC_0_DISPLAY0B_TMVAL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_DC_0_DISPLAY0B_TMVAL_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_DC_0_DISPLAY0B_TMVAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_DC_0_DISPLAY0B_TMVAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_DC_0_DISPLAY0C_TMVAL_SHIFT                   _MK_SHIFT_CONST(8)
+#define MC_TIMEOUT_DC_0_DISPLAY0C_TMVAL_FIELD                   (_MK_MASK_CONST(0xf) << MC_TIMEOUT_DC_0_DISPLAY0C_TMVAL_SHIFT)
+#define MC_TIMEOUT_DC_0_DISPLAY0C_TMVAL_RANGE                   11:8
+#define MC_TIMEOUT_DC_0_DISPLAY0C_TMVAL_WOFFSET                 0x0
+#define MC_TIMEOUT_DC_0_DISPLAY0C_TMVAL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_DC_0_DISPLAY0C_TMVAL_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_DC_0_DISPLAY0C_TMVAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_DC_0_DISPLAY0C_TMVAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_DC_0_DISPLAY1B_TMVAL_SHIFT                   _MK_SHIFT_CONST(12)
+#define MC_TIMEOUT_DC_0_DISPLAY1B_TMVAL_FIELD                   (_MK_MASK_CONST(0xf) << MC_TIMEOUT_DC_0_DISPLAY1B_TMVAL_SHIFT)
+#define MC_TIMEOUT_DC_0_DISPLAY1B_TMVAL_RANGE                   15:12
+#define MC_TIMEOUT_DC_0_DISPLAY1B_TMVAL_WOFFSET                 0x0
+#define MC_TIMEOUT_DC_0_DISPLAY1B_TMVAL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_DC_0_DISPLAY1B_TMVAL_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_DC_0_DISPLAY1B_TMVAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_DC_0_DISPLAY1B_TMVAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_DC_0_DISPLAYHC_TMVAL_SHIFT                   _MK_SHIFT_CONST(16)
+#define MC_TIMEOUT_DC_0_DISPLAYHC_TMVAL_FIELD                   (_MK_MASK_CONST(0xf) << MC_TIMEOUT_DC_0_DISPLAYHC_TMVAL_SHIFT)
+#define MC_TIMEOUT_DC_0_DISPLAYHC_TMVAL_RANGE                   19:16
+#define MC_TIMEOUT_DC_0_DISPLAYHC_TMVAL_WOFFSET                 0x0
+#define MC_TIMEOUT_DC_0_DISPLAYHC_TMVAL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_DC_0_DISPLAYHC_TMVAL_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_DC_0_DISPLAYHC_TMVAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_DC_0_DISPLAYHC_TMVAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register MC_TIMEOUT_DCB_0  
+#define MC_TIMEOUT_DCB_0                        _MK_ADDR_CONST(0x12c)
+#define MC_TIMEOUT_DCB_0_WORD_COUNT                     0x1
+#define MC_TIMEOUT_DCB_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_DCB_0_RESET_MASK                     _MK_MASK_CONST(0xfffff)
+#define MC_TIMEOUT_DCB_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_DCB_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_DCB_0_READ_MASK                      _MK_MASK_CONST(0xfffff)
+#define MC_TIMEOUT_DCB_0_WRITE_MASK                     _MK_MASK_CONST(0xfffff)
+#define MC_TIMEOUT_DCB_0_DISPLAY0AB_TMVAL_SHIFT                 _MK_SHIFT_CONST(0)
+#define MC_TIMEOUT_DCB_0_DISPLAY0AB_TMVAL_FIELD                 (_MK_MASK_CONST(0xf) << MC_TIMEOUT_DCB_0_DISPLAY0AB_TMVAL_SHIFT)
+#define MC_TIMEOUT_DCB_0_DISPLAY0AB_TMVAL_RANGE                 3:0
+#define MC_TIMEOUT_DCB_0_DISPLAY0AB_TMVAL_WOFFSET                       0x0
+#define MC_TIMEOUT_DCB_0_DISPLAY0AB_TMVAL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_DCB_0_DISPLAY0AB_TMVAL_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_DCB_0_DISPLAY0AB_TMVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_DCB_0_DISPLAY0AB_TMVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_DCB_0_DISPLAY0BB_TMVAL_SHIFT                 _MK_SHIFT_CONST(4)
+#define MC_TIMEOUT_DCB_0_DISPLAY0BB_TMVAL_FIELD                 (_MK_MASK_CONST(0xf) << MC_TIMEOUT_DCB_0_DISPLAY0BB_TMVAL_SHIFT)
+#define MC_TIMEOUT_DCB_0_DISPLAY0BB_TMVAL_RANGE                 7:4
+#define MC_TIMEOUT_DCB_0_DISPLAY0BB_TMVAL_WOFFSET                       0x0
+#define MC_TIMEOUT_DCB_0_DISPLAY0BB_TMVAL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_DCB_0_DISPLAY0BB_TMVAL_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_DCB_0_DISPLAY0BB_TMVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_DCB_0_DISPLAY0BB_TMVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_DCB_0_DISPLAY0CB_TMVAL_SHIFT                 _MK_SHIFT_CONST(8)
+#define MC_TIMEOUT_DCB_0_DISPLAY0CB_TMVAL_FIELD                 (_MK_MASK_CONST(0xf) << MC_TIMEOUT_DCB_0_DISPLAY0CB_TMVAL_SHIFT)
+#define MC_TIMEOUT_DCB_0_DISPLAY0CB_TMVAL_RANGE                 11:8
+#define MC_TIMEOUT_DCB_0_DISPLAY0CB_TMVAL_WOFFSET                       0x0
+#define MC_TIMEOUT_DCB_0_DISPLAY0CB_TMVAL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_DCB_0_DISPLAY0CB_TMVAL_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_DCB_0_DISPLAY0CB_TMVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_DCB_0_DISPLAY0CB_TMVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_DCB_0_DISPLAY1BB_TMVAL_SHIFT                 _MK_SHIFT_CONST(12)
+#define MC_TIMEOUT_DCB_0_DISPLAY1BB_TMVAL_FIELD                 (_MK_MASK_CONST(0xf) << MC_TIMEOUT_DCB_0_DISPLAY1BB_TMVAL_SHIFT)
+#define MC_TIMEOUT_DCB_0_DISPLAY1BB_TMVAL_RANGE                 15:12
+#define MC_TIMEOUT_DCB_0_DISPLAY1BB_TMVAL_WOFFSET                       0x0
+#define MC_TIMEOUT_DCB_0_DISPLAY1BB_TMVAL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_DCB_0_DISPLAY1BB_TMVAL_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_DCB_0_DISPLAY1BB_TMVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_DCB_0_DISPLAY1BB_TMVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_DCB_0_DISPLAYHCB_TMVAL_SHIFT                 _MK_SHIFT_CONST(16)
+#define MC_TIMEOUT_DCB_0_DISPLAYHCB_TMVAL_FIELD                 (_MK_MASK_CONST(0xf) << MC_TIMEOUT_DCB_0_DISPLAYHCB_TMVAL_SHIFT)
+#define MC_TIMEOUT_DCB_0_DISPLAYHCB_TMVAL_RANGE                 19:16
+#define MC_TIMEOUT_DCB_0_DISPLAYHCB_TMVAL_WOFFSET                       0x0
+#define MC_TIMEOUT_DCB_0_DISPLAYHCB_TMVAL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_DCB_0_DISPLAYHCB_TMVAL_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_DCB_0_DISPLAYHCB_TMVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_DCB_0_DISPLAYHCB_TMVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register MC_TIMEOUT_EPP_0  
+#define MC_TIMEOUT_EPP_0                        _MK_ADDR_CONST(0x130)
+#define MC_TIMEOUT_EPP_0_WORD_COUNT                     0x1
+#define MC_TIMEOUT_EPP_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_EPP_0_RESET_MASK                     _MK_MASK_CONST(0xffff)
+#define MC_TIMEOUT_EPP_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_EPP_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_EPP_0_READ_MASK                      _MK_MASK_CONST(0xffff)
+#define MC_TIMEOUT_EPP_0_WRITE_MASK                     _MK_MASK_CONST(0xffff)
+#define MC_TIMEOUT_EPP_0_EPPUP_TMVAL_SHIFT                      _MK_SHIFT_CONST(0)
+#define MC_TIMEOUT_EPP_0_EPPUP_TMVAL_FIELD                      (_MK_MASK_CONST(0xf) << MC_TIMEOUT_EPP_0_EPPUP_TMVAL_SHIFT)
+#define MC_TIMEOUT_EPP_0_EPPUP_TMVAL_RANGE                      3:0
+#define MC_TIMEOUT_EPP_0_EPPUP_TMVAL_WOFFSET                    0x0
+#define MC_TIMEOUT_EPP_0_EPPUP_TMVAL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_EPP_0_EPPUP_TMVAL_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_EPP_0_EPPUP_TMVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_EPP_0_EPPUP_TMVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_EPP_0_EPPU_TMVAL_SHIFT                       _MK_SHIFT_CONST(4)
+#define MC_TIMEOUT_EPP_0_EPPU_TMVAL_FIELD                       (_MK_MASK_CONST(0xf) << MC_TIMEOUT_EPP_0_EPPU_TMVAL_SHIFT)
+#define MC_TIMEOUT_EPP_0_EPPU_TMVAL_RANGE                       7:4
+#define MC_TIMEOUT_EPP_0_EPPU_TMVAL_WOFFSET                     0x0
+#define MC_TIMEOUT_EPP_0_EPPU_TMVAL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_EPP_0_EPPU_TMVAL_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_EPP_0_EPPU_TMVAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_EPP_0_EPPU_TMVAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_EPP_0_EPPV_TMVAL_SHIFT                       _MK_SHIFT_CONST(8)
+#define MC_TIMEOUT_EPP_0_EPPV_TMVAL_FIELD                       (_MK_MASK_CONST(0xf) << MC_TIMEOUT_EPP_0_EPPV_TMVAL_SHIFT)
+#define MC_TIMEOUT_EPP_0_EPPV_TMVAL_RANGE                       11:8
+#define MC_TIMEOUT_EPP_0_EPPV_TMVAL_WOFFSET                     0x0
+#define MC_TIMEOUT_EPP_0_EPPV_TMVAL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_EPP_0_EPPV_TMVAL_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_EPP_0_EPPV_TMVAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_EPP_0_EPPV_TMVAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_EPP_0_EPPY_TMVAL_SHIFT                       _MK_SHIFT_CONST(12)
+#define MC_TIMEOUT_EPP_0_EPPY_TMVAL_FIELD                       (_MK_MASK_CONST(0xf) << MC_TIMEOUT_EPP_0_EPPY_TMVAL_SHIFT)
+#define MC_TIMEOUT_EPP_0_EPPY_TMVAL_RANGE                       15:12
+#define MC_TIMEOUT_EPP_0_EPPY_TMVAL_WOFFSET                     0x0
+#define MC_TIMEOUT_EPP_0_EPPY_TMVAL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_EPP_0_EPPY_TMVAL_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_EPP_0_EPPY_TMVAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_EPP_0_EPPY_TMVAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register MC_TIMEOUT_G2_0  
+#define MC_TIMEOUT_G2_0                 _MK_ADDR_CONST(0x134)
+#define MC_TIMEOUT_G2_0_WORD_COUNT                      0x1
+#define MC_TIMEOUT_G2_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_G2_0_RESET_MASK                      _MK_MASK_CONST(0xffff)
+#define MC_TIMEOUT_G2_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_G2_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_G2_0_READ_MASK                       _MK_MASK_CONST(0xffff)
+#define MC_TIMEOUT_G2_0_WRITE_MASK                      _MK_MASK_CONST(0xffff)
+#define MC_TIMEOUT_G2_0_G2PR_TMVAL_SHIFT                        _MK_SHIFT_CONST(0)
+#define MC_TIMEOUT_G2_0_G2PR_TMVAL_FIELD                        (_MK_MASK_CONST(0xf) << MC_TIMEOUT_G2_0_G2PR_TMVAL_SHIFT)
+#define MC_TIMEOUT_G2_0_G2PR_TMVAL_RANGE                        3:0
+#define MC_TIMEOUT_G2_0_G2PR_TMVAL_WOFFSET                      0x0
+#define MC_TIMEOUT_G2_0_G2PR_TMVAL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_G2_0_G2PR_TMVAL_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_G2_0_G2PR_TMVAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_G2_0_G2PR_TMVAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_G2_0_G2SR_TMVAL_SHIFT                        _MK_SHIFT_CONST(4)
+#define MC_TIMEOUT_G2_0_G2SR_TMVAL_FIELD                        (_MK_MASK_CONST(0xf) << MC_TIMEOUT_G2_0_G2SR_TMVAL_SHIFT)
+#define MC_TIMEOUT_G2_0_G2SR_TMVAL_RANGE                        7:4
+#define MC_TIMEOUT_G2_0_G2SR_TMVAL_WOFFSET                      0x0
+#define MC_TIMEOUT_G2_0_G2SR_TMVAL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_G2_0_G2SR_TMVAL_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_G2_0_G2SR_TMVAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_G2_0_G2SR_TMVAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_G2_0_G2DR_TMVAL_SHIFT                        _MK_SHIFT_CONST(8)
+#define MC_TIMEOUT_G2_0_G2DR_TMVAL_FIELD                        (_MK_MASK_CONST(0xf) << MC_TIMEOUT_G2_0_G2DR_TMVAL_SHIFT)
+#define MC_TIMEOUT_G2_0_G2DR_TMVAL_RANGE                        11:8
+#define MC_TIMEOUT_G2_0_G2DR_TMVAL_WOFFSET                      0x0
+#define MC_TIMEOUT_G2_0_G2DR_TMVAL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_G2_0_G2DR_TMVAL_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_G2_0_G2DR_TMVAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_G2_0_G2DR_TMVAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_G2_0_G2DW_TMVAL_SHIFT                        _MK_SHIFT_CONST(12)
+#define MC_TIMEOUT_G2_0_G2DW_TMVAL_FIELD                        (_MK_MASK_CONST(0xf) << MC_TIMEOUT_G2_0_G2DW_TMVAL_SHIFT)
+#define MC_TIMEOUT_G2_0_G2DW_TMVAL_RANGE                        15:12
+#define MC_TIMEOUT_G2_0_G2DW_TMVAL_WOFFSET                      0x0
+#define MC_TIMEOUT_G2_0_G2DW_TMVAL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_G2_0_G2DW_TMVAL_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_G2_0_G2DW_TMVAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_G2_0_G2DW_TMVAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register MC_TIMEOUT_HC_0  
+#define MC_TIMEOUT_HC_0                 _MK_ADDR_CONST(0x138)
+#define MC_TIMEOUT_HC_0_WORD_COUNT                      0x1
+#define MC_TIMEOUT_HC_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_HC_0_RESET_MASK                      _MK_MASK_CONST(0xfff)
+#define MC_TIMEOUT_HC_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_HC_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_HC_0_READ_MASK                       _MK_MASK_CONST(0xfff)
+#define MC_TIMEOUT_HC_0_WRITE_MASK                      _MK_MASK_CONST(0xfff)
+#define MC_TIMEOUT_HC_0_HOST1XDMAR_TMVAL_SHIFT                  _MK_SHIFT_CONST(0)
+#define MC_TIMEOUT_HC_0_HOST1XDMAR_TMVAL_FIELD                  (_MK_MASK_CONST(0xf) << MC_TIMEOUT_HC_0_HOST1XDMAR_TMVAL_SHIFT)
+#define MC_TIMEOUT_HC_0_HOST1XDMAR_TMVAL_RANGE                  3:0
+#define MC_TIMEOUT_HC_0_HOST1XDMAR_TMVAL_WOFFSET                        0x0
+#define MC_TIMEOUT_HC_0_HOST1XDMAR_TMVAL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_HC_0_HOST1XDMAR_TMVAL_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_HC_0_HOST1XDMAR_TMVAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_HC_0_HOST1XDMAR_TMVAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_HC_0_HOST1XR_TMVAL_SHIFT                     _MK_SHIFT_CONST(4)
+#define MC_TIMEOUT_HC_0_HOST1XR_TMVAL_FIELD                     (_MK_MASK_CONST(0xf) << MC_TIMEOUT_HC_0_HOST1XR_TMVAL_SHIFT)
+#define MC_TIMEOUT_HC_0_HOST1XR_TMVAL_RANGE                     7:4
+#define MC_TIMEOUT_HC_0_HOST1XR_TMVAL_WOFFSET                   0x0
+#define MC_TIMEOUT_HC_0_HOST1XR_TMVAL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_HC_0_HOST1XR_TMVAL_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_HC_0_HOST1XR_TMVAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_HC_0_HOST1XR_TMVAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_HC_0_HOST1XW_TMVAL_SHIFT                     _MK_SHIFT_CONST(8)
+#define MC_TIMEOUT_HC_0_HOST1XW_TMVAL_FIELD                     (_MK_MASK_CONST(0xf) << MC_TIMEOUT_HC_0_HOST1XW_TMVAL_SHIFT)
+#define MC_TIMEOUT_HC_0_HOST1XW_TMVAL_RANGE                     11:8
+#define MC_TIMEOUT_HC_0_HOST1XW_TMVAL_WOFFSET                   0x0
+#define MC_TIMEOUT_HC_0_HOST1XW_TMVAL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_HC_0_HOST1XW_TMVAL_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_HC_0_HOST1XW_TMVAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_HC_0_HOST1XW_TMVAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register MC_TIMEOUT_ISP_0  
+#define MC_TIMEOUT_ISP_0                        _MK_ADDR_CONST(0x13c)
+#define MC_TIMEOUT_ISP_0_WORD_COUNT                     0x1
+#define MC_TIMEOUT_ISP_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_ISP_0_RESET_MASK                     _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_ISP_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_ISP_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_ISP_0_READ_MASK                      _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_ISP_0_WRITE_MASK                     _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_ISP_0_ISPW_TMVAL_SHIFT                       _MK_SHIFT_CONST(0)
+#define MC_TIMEOUT_ISP_0_ISPW_TMVAL_FIELD                       (_MK_MASK_CONST(0xf) << MC_TIMEOUT_ISP_0_ISPW_TMVAL_SHIFT)
+#define MC_TIMEOUT_ISP_0_ISPW_TMVAL_RANGE                       3:0
+#define MC_TIMEOUT_ISP_0_ISPW_TMVAL_WOFFSET                     0x0
+#define MC_TIMEOUT_ISP_0_ISPW_TMVAL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_ISP_0_ISPW_TMVAL_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_ISP_0_ISPW_TMVAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_ISP_0_ISPW_TMVAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register MC_TIMEOUT_MPCORE_0  
+#define MC_TIMEOUT_MPCORE_0                     _MK_ADDR_CONST(0x140)
+#define MC_TIMEOUT_MPCORE_0_WORD_COUNT                  0x1
+#define MC_TIMEOUT_MPCORE_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_MPCORE_0_RESET_MASK                  _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_MPCORE_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_MPCORE_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_MPCORE_0_READ_MASK                   _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_MPCORE_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_MPCORE_0_MPCORER_TMVAL_SHIFT                 _MK_SHIFT_CONST(0)
+#define MC_TIMEOUT_MPCORE_0_MPCORER_TMVAL_FIELD                 (_MK_MASK_CONST(0xf) << MC_TIMEOUT_MPCORE_0_MPCORER_TMVAL_SHIFT)
+#define MC_TIMEOUT_MPCORE_0_MPCORER_TMVAL_RANGE                 3:0
+#define MC_TIMEOUT_MPCORE_0_MPCORER_TMVAL_WOFFSET                       0x0
+#define MC_TIMEOUT_MPCORE_0_MPCORER_TMVAL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_MPCORE_0_MPCORER_TMVAL_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_MPCORE_0_MPCORER_TMVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_MPCORE_0_MPCORER_TMVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_MPCORE_0_MPCOREW_TMVAL_SHIFT                 _MK_SHIFT_CONST(4)
+#define MC_TIMEOUT_MPCORE_0_MPCOREW_TMVAL_FIELD                 (_MK_MASK_CONST(0xf) << MC_TIMEOUT_MPCORE_0_MPCOREW_TMVAL_SHIFT)
+#define MC_TIMEOUT_MPCORE_0_MPCOREW_TMVAL_RANGE                 7:4
+#define MC_TIMEOUT_MPCORE_0_MPCOREW_TMVAL_WOFFSET                       0x0
+#define MC_TIMEOUT_MPCORE_0_MPCOREW_TMVAL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_MPCORE_0_MPCOREW_TMVAL_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_MPCORE_0_MPCOREW_TMVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_MPCORE_0_MPCOREW_TMVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register MC_TIMEOUT_MPEA_0  
+#define MC_TIMEOUT_MPEA_0                       _MK_ADDR_CONST(0x144)
+#define MC_TIMEOUT_MPEA_0_WORD_COUNT                    0x1
+#define MC_TIMEOUT_MPEA_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_MPEA_0_RESET_MASK                    _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_MPEA_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_MPEA_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_MPEA_0_READ_MASK                     _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_MPEA_0_WRITE_MASK                    _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_MPEA_0_MPEAMEMRD_TMVAL_SHIFT                 _MK_SHIFT_CONST(0)
+#define MC_TIMEOUT_MPEA_0_MPEAMEMRD_TMVAL_FIELD                 (_MK_MASK_CONST(0xf) << MC_TIMEOUT_MPEA_0_MPEAMEMRD_TMVAL_SHIFT)
+#define MC_TIMEOUT_MPEA_0_MPEAMEMRD_TMVAL_RANGE                 3:0
+#define MC_TIMEOUT_MPEA_0_MPEAMEMRD_TMVAL_WOFFSET                       0x0
+#define MC_TIMEOUT_MPEA_0_MPEAMEMRD_TMVAL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_MPEA_0_MPEAMEMRD_TMVAL_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_MPEA_0_MPEAMEMRD_TMVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_MPEA_0_MPEAMEMRD_TMVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register MC_TIMEOUT_MPEB_0  
+#define MC_TIMEOUT_MPEB_0                       _MK_ADDR_CONST(0x148)
+#define MC_TIMEOUT_MPEB_0_WORD_COUNT                    0x1
+#define MC_TIMEOUT_MPEB_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_MPEB_0_RESET_MASK                    _MK_MASK_CONST(0xfff)
+#define MC_TIMEOUT_MPEB_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_MPEB_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_MPEB_0_READ_MASK                     _MK_MASK_CONST(0xfff)
+#define MC_TIMEOUT_MPEB_0_WRITE_MASK                    _MK_MASK_CONST(0xfff)
+#define MC_TIMEOUT_MPEB_0_MPEUNIFBR_TMVAL_SHIFT                 _MK_SHIFT_CONST(0)
+#define MC_TIMEOUT_MPEB_0_MPEUNIFBR_TMVAL_FIELD                 (_MK_MASK_CONST(0xf) << MC_TIMEOUT_MPEB_0_MPEUNIFBR_TMVAL_SHIFT)
+#define MC_TIMEOUT_MPEB_0_MPEUNIFBR_TMVAL_RANGE                 3:0
+#define MC_TIMEOUT_MPEB_0_MPEUNIFBR_TMVAL_WOFFSET                       0x0
+#define MC_TIMEOUT_MPEB_0_MPEUNIFBR_TMVAL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_MPEB_0_MPEUNIFBR_TMVAL_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_MPEB_0_MPEUNIFBR_TMVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_MPEB_0_MPEUNIFBR_TMVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_MPEB_0_MPE_IPRED_TMVAL_SHIFT                 _MK_SHIFT_CONST(4)
+#define MC_TIMEOUT_MPEB_0_MPE_IPRED_TMVAL_FIELD                 (_MK_MASK_CONST(0xf) << MC_TIMEOUT_MPEB_0_MPE_IPRED_TMVAL_SHIFT)
+#define MC_TIMEOUT_MPEB_0_MPE_IPRED_TMVAL_RANGE                 7:4
+#define MC_TIMEOUT_MPEB_0_MPE_IPRED_TMVAL_WOFFSET                       0x0
+#define MC_TIMEOUT_MPEB_0_MPE_IPRED_TMVAL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_MPEB_0_MPE_IPRED_TMVAL_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_MPEB_0_MPE_IPRED_TMVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_MPEB_0_MPE_IPRED_TMVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_MPEB_0_MPEUNIFBW_TMVAL_SHIFT                 _MK_SHIFT_CONST(8)
+#define MC_TIMEOUT_MPEB_0_MPEUNIFBW_TMVAL_FIELD                 (_MK_MASK_CONST(0xf) << MC_TIMEOUT_MPEB_0_MPEUNIFBW_TMVAL_SHIFT)
+#define MC_TIMEOUT_MPEB_0_MPEUNIFBW_TMVAL_RANGE                 11:8
+#define MC_TIMEOUT_MPEB_0_MPEUNIFBW_TMVAL_WOFFSET                       0x0
+#define MC_TIMEOUT_MPEB_0_MPEUNIFBW_TMVAL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_MPEB_0_MPEUNIFBW_TMVAL_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_MPEB_0_MPEUNIFBW_TMVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_MPEB_0_MPEUNIFBW_TMVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register MC_TIMEOUT_MPEC_0  
+#define MC_TIMEOUT_MPEC_0                       _MK_ADDR_CONST(0x14c)
+#define MC_TIMEOUT_MPEC_0_WORD_COUNT                    0x1
+#define MC_TIMEOUT_MPEC_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_MPEC_0_RESET_MASK                    _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_MPEC_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_MPEC_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_MPEC_0_READ_MASK                     _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_MPEC_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_MPEC_0_MPECSRD_TMVAL_SHIFT                   _MK_SHIFT_CONST(0)
+#define MC_TIMEOUT_MPEC_0_MPECSRD_TMVAL_FIELD                   (_MK_MASK_CONST(0xf) << MC_TIMEOUT_MPEC_0_MPECSRD_TMVAL_SHIFT)
+#define MC_TIMEOUT_MPEC_0_MPECSRD_TMVAL_RANGE                   3:0
+#define MC_TIMEOUT_MPEC_0_MPECSRD_TMVAL_WOFFSET                 0x0
+#define MC_TIMEOUT_MPEC_0_MPECSRD_TMVAL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_MPEC_0_MPECSRD_TMVAL_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_MPEC_0_MPECSRD_TMVAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_MPEC_0_MPECSRD_TMVAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_MPEC_0_MPECSWR_TMVAL_SHIFT                   _MK_SHIFT_CONST(4)
+#define MC_TIMEOUT_MPEC_0_MPECSWR_TMVAL_FIELD                   (_MK_MASK_CONST(0xf) << MC_TIMEOUT_MPEC_0_MPECSWR_TMVAL_SHIFT)
+#define MC_TIMEOUT_MPEC_0_MPECSWR_TMVAL_RANGE                   7:4
+#define MC_TIMEOUT_MPEC_0_MPECSWR_TMVAL_WOFFSET                 0x0
+#define MC_TIMEOUT_MPEC_0_MPECSWR_TMVAL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_MPEC_0_MPECSWR_TMVAL_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_MPEC_0_MPECSWR_TMVAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_MPEC_0_MPECSWR_TMVAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register MC_TIMEOUT_NV_0  
+#define MC_TIMEOUT_NV_0                 _MK_ADDR_CONST(0x150)
+#define MC_TIMEOUT_NV_0_WORD_COUNT                      0x1
+#define MC_TIMEOUT_NV_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_NV_0_RESET_MASK                      _MK_MASK_CONST(0xffff)
+#define MC_TIMEOUT_NV_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_NV_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_NV_0_READ_MASK                       _MK_MASK_CONST(0xffff)
+#define MC_TIMEOUT_NV_0_WRITE_MASK                      _MK_MASK_CONST(0xffff)
+#define MC_TIMEOUT_NV_0_FDCDRD_TMVAL_SHIFT                      _MK_SHIFT_CONST(0)
+#define MC_TIMEOUT_NV_0_FDCDRD_TMVAL_FIELD                      (_MK_MASK_CONST(0xf) << MC_TIMEOUT_NV_0_FDCDRD_TMVAL_SHIFT)
+#define MC_TIMEOUT_NV_0_FDCDRD_TMVAL_RANGE                      3:0
+#define MC_TIMEOUT_NV_0_FDCDRD_TMVAL_WOFFSET                    0x0
+#define MC_TIMEOUT_NV_0_FDCDRD_TMVAL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_NV_0_FDCDRD_TMVAL_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_NV_0_FDCDRD_TMVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_NV_0_FDCDRD_TMVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_NV_0_IDXSRD_TMVAL_SHIFT                      _MK_SHIFT_CONST(4)
+#define MC_TIMEOUT_NV_0_IDXSRD_TMVAL_FIELD                      (_MK_MASK_CONST(0xf) << MC_TIMEOUT_NV_0_IDXSRD_TMVAL_SHIFT)
+#define MC_TIMEOUT_NV_0_IDXSRD_TMVAL_RANGE                      7:4
+#define MC_TIMEOUT_NV_0_IDXSRD_TMVAL_WOFFSET                    0x0
+#define MC_TIMEOUT_NV_0_IDXSRD_TMVAL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_NV_0_IDXSRD_TMVAL_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_NV_0_IDXSRD_TMVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_NV_0_IDXSRD_TMVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_NV_0_TEXSRD_TMVAL_SHIFT                      _MK_SHIFT_CONST(8)
+#define MC_TIMEOUT_NV_0_TEXSRD_TMVAL_FIELD                      (_MK_MASK_CONST(0xf) << MC_TIMEOUT_NV_0_TEXSRD_TMVAL_SHIFT)
+#define MC_TIMEOUT_NV_0_TEXSRD_TMVAL_RANGE                      11:8
+#define MC_TIMEOUT_NV_0_TEXSRD_TMVAL_WOFFSET                    0x0
+#define MC_TIMEOUT_NV_0_TEXSRD_TMVAL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_NV_0_TEXSRD_TMVAL_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_NV_0_TEXSRD_TMVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_NV_0_TEXSRD_TMVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_NV_0_FDCDWR_TMVAL_SHIFT                      _MK_SHIFT_CONST(12)
+#define MC_TIMEOUT_NV_0_FDCDWR_TMVAL_FIELD                      (_MK_MASK_CONST(0xf) << MC_TIMEOUT_NV_0_FDCDWR_TMVAL_SHIFT)
+#define MC_TIMEOUT_NV_0_FDCDWR_TMVAL_RANGE                      15:12
+#define MC_TIMEOUT_NV_0_FDCDWR_TMVAL_WOFFSET                    0x0
+#define MC_TIMEOUT_NV_0_FDCDWR_TMVAL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_NV_0_FDCDWR_TMVAL_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_NV_0_FDCDWR_TMVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_NV_0_FDCDWR_TMVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register MC_TIMEOUT_PPCS_0  
+#define MC_TIMEOUT_PPCS_0                       _MK_ADDR_CONST(0x154)
+#define MC_TIMEOUT_PPCS_0_WORD_COUNT                    0x1
+#define MC_TIMEOUT_PPCS_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_PPCS_0_RESET_MASK                    _MK_MASK_CONST(0xffffff)
+#define MC_TIMEOUT_PPCS_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_PPCS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_PPCS_0_READ_MASK                     _MK_MASK_CONST(0xffffff)
+#define MC_TIMEOUT_PPCS_0_WRITE_MASK                    _MK_MASK_CONST(0xffffff)
+#define MC_TIMEOUT_PPCS_0_PPCSAHBDMAR_TMVAL_SHIFT                       _MK_SHIFT_CONST(0)
+#define MC_TIMEOUT_PPCS_0_PPCSAHBDMAR_TMVAL_FIELD                       (_MK_MASK_CONST(0xf) << MC_TIMEOUT_PPCS_0_PPCSAHBDMAR_TMVAL_SHIFT)
+#define MC_TIMEOUT_PPCS_0_PPCSAHBDMAR_TMVAL_RANGE                       3:0
+#define MC_TIMEOUT_PPCS_0_PPCSAHBDMAR_TMVAL_WOFFSET                     0x0
+#define MC_TIMEOUT_PPCS_0_PPCSAHBDMAR_TMVAL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_PPCS_0_PPCSAHBDMAR_TMVAL_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_PPCS_0_PPCSAHBDMAR_TMVAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_PPCS_0_PPCSAHBDMAR_TMVAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_PPCS_0_PPCSAHBSLVR_TMVAL_SHIFT                       _MK_SHIFT_CONST(4)
+#define MC_TIMEOUT_PPCS_0_PPCSAHBSLVR_TMVAL_FIELD                       (_MK_MASK_CONST(0xf) << MC_TIMEOUT_PPCS_0_PPCSAHBSLVR_TMVAL_SHIFT)
+#define MC_TIMEOUT_PPCS_0_PPCSAHBSLVR_TMVAL_RANGE                       7:4
+#define MC_TIMEOUT_PPCS_0_PPCSAHBSLVR_TMVAL_WOFFSET                     0x0
+#define MC_TIMEOUT_PPCS_0_PPCSAHBSLVR_TMVAL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_PPCS_0_PPCSAHBSLVR_TMVAL_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_PPCS_0_PPCSAHBSLVR_TMVAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_PPCS_0_PPCSAHBSLVR_TMVAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_PPCS_0_PPCSARM7R_TMVAL_SHIFT                 _MK_SHIFT_CONST(8)
+#define MC_TIMEOUT_PPCS_0_PPCSARM7R_TMVAL_FIELD                 (_MK_MASK_CONST(0xf) << MC_TIMEOUT_PPCS_0_PPCSARM7R_TMVAL_SHIFT)
+#define MC_TIMEOUT_PPCS_0_PPCSARM7R_TMVAL_RANGE                 11:8
+#define MC_TIMEOUT_PPCS_0_PPCSARM7R_TMVAL_WOFFSET                       0x0
+#define MC_TIMEOUT_PPCS_0_PPCSARM7R_TMVAL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_PPCS_0_PPCSARM7R_TMVAL_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_PPCS_0_PPCSARM7R_TMVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_PPCS_0_PPCSARM7R_TMVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_PPCS_0_PPCSAHBDMAW_TMVAL_SHIFT                       _MK_SHIFT_CONST(12)
+#define MC_TIMEOUT_PPCS_0_PPCSAHBDMAW_TMVAL_FIELD                       (_MK_MASK_CONST(0xf) << MC_TIMEOUT_PPCS_0_PPCSAHBDMAW_TMVAL_SHIFT)
+#define MC_TIMEOUT_PPCS_0_PPCSAHBDMAW_TMVAL_RANGE                       15:12
+#define MC_TIMEOUT_PPCS_0_PPCSAHBDMAW_TMVAL_WOFFSET                     0x0
+#define MC_TIMEOUT_PPCS_0_PPCSAHBDMAW_TMVAL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_PPCS_0_PPCSAHBDMAW_TMVAL_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_PPCS_0_PPCSAHBDMAW_TMVAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_PPCS_0_PPCSAHBDMAW_TMVAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_PPCS_0_PPCSAHBSLVW_TMVAL_SHIFT                       _MK_SHIFT_CONST(16)
+#define MC_TIMEOUT_PPCS_0_PPCSAHBSLVW_TMVAL_FIELD                       (_MK_MASK_CONST(0xf) << MC_TIMEOUT_PPCS_0_PPCSAHBSLVW_TMVAL_SHIFT)
+#define MC_TIMEOUT_PPCS_0_PPCSAHBSLVW_TMVAL_RANGE                       19:16
+#define MC_TIMEOUT_PPCS_0_PPCSAHBSLVW_TMVAL_WOFFSET                     0x0
+#define MC_TIMEOUT_PPCS_0_PPCSAHBSLVW_TMVAL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_PPCS_0_PPCSAHBSLVW_TMVAL_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_PPCS_0_PPCSAHBSLVW_TMVAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_PPCS_0_PPCSAHBSLVW_TMVAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_PPCS_0_PPCSARM7W_TMVAL_SHIFT                 _MK_SHIFT_CONST(20)
+#define MC_TIMEOUT_PPCS_0_PPCSARM7W_TMVAL_FIELD                 (_MK_MASK_CONST(0xf) << MC_TIMEOUT_PPCS_0_PPCSARM7W_TMVAL_SHIFT)
+#define MC_TIMEOUT_PPCS_0_PPCSARM7W_TMVAL_RANGE                 23:20
+#define MC_TIMEOUT_PPCS_0_PPCSARM7W_TMVAL_WOFFSET                       0x0
+#define MC_TIMEOUT_PPCS_0_PPCSARM7W_TMVAL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_PPCS_0_PPCSARM7W_TMVAL_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_PPCS_0_PPCSARM7W_TMVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_PPCS_0_PPCSARM7W_TMVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register MC_TIMEOUT_VDE_0  
+#define MC_TIMEOUT_VDE_0                        _MK_ADDR_CONST(0x158)
+#define MC_TIMEOUT_VDE_0_WORD_COUNT                     0x1
+#define MC_TIMEOUT_VDE_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_VDE_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
+#define MC_TIMEOUT_VDE_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_VDE_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_VDE_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define MC_TIMEOUT_VDE_0_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
+#define MC_TIMEOUT_VDE_0_VDEBSEAR_TMVAL_SHIFT                   _MK_SHIFT_CONST(0)
+#define MC_TIMEOUT_VDE_0_VDEBSEAR_TMVAL_FIELD                   (_MK_MASK_CONST(0xf) << MC_TIMEOUT_VDE_0_VDEBSEAR_TMVAL_SHIFT)
+#define MC_TIMEOUT_VDE_0_VDEBSEAR_TMVAL_RANGE                   3:0
+#define MC_TIMEOUT_VDE_0_VDEBSEAR_TMVAL_WOFFSET                 0x0
+#define MC_TIMEOUT_VDE_0_VDEBSEAR_TMVAL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_VDE_0_VDEBSEAR_TMVAL_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_VDE_0_VDEBSEAR_TMVAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_VDE_0_VDEBSEAR_TMVAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_VDE_0_VDEBSEVR_TMVAL_SHIFT                   _MK_SHIFT_CONST(4)
+#define MC_TIMEOUT_VDE_0_VDEBSEVR_TMVAL_FIELD                   (_MK_MASK_CONST(0xf) << MC_TIMEOUT_VDE_0_VDEBSEVR_TMVAL_SHIFT)
+#define MC_TIMEOUT_VDE_0_VDEBSEVR_TMVAL_RANGE                   7:4
+#define MC_TIMEOUT_VDE_0_VDEBSEVR_TMVAL_WOFFSET                 0x0
+#define MC_TIMEOUT_VDE_0_VDEBSEVR_TMVAL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_VDE_0_VDEBSEVR_TMVAL_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_VDE_0_VDEBSEVR_TMVAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_VDE_0_VDEBSEVR_TMVAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_VDE_0_VDEMBER_TMVAL_SHIFT                    _MK_SHIFT_CONST(8)
+#define MC_TIMEOUT_VDE_0_VDEMBER_TMVAL_FIELD                    (_MK_MASK_CONST(0xf) << MC_TIMEOUT_VDE_0_VDEMBER_TMVAL_SHIFT)
+#define MC_TIMEOUT_VDE_0_VDEMBER_TMVAL_RANGE                    11:8
+#define MC_TIMEOUT_VDE_0_VDEMBER_TMVAL_WOFFSET                  0x0
+#define MC_TIMEOUT_VDE_0_VDEMBER_TMVAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_VDE_0_VDEMBER_TMVAL_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_VDE_0_VDEMBER_TMVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_VDE_0_VDEMBER_TMVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_VDE_0_VDEMCER_TMVAL_SHIFT                    _MK_SHIFT_CONST(12)
+#define MC_TIMEOUT_VDE_0_VDEMCER_TMVAL_FIELD                    (_MK_MASK_CONST(0xf) << MC_TIMEOUT_VDE_0_VDEMCER_TMVAL_SHIFT)
+#define MC_TIMEOUT_VDE_0_VDEMCER_TMVAL_RANGE                    15:12
+#define MC_TIMEOUT_VDE_0_VDEMCER_TMVAL_WOFFSET                  0x0
+#define MC_TIMEOUT_VDE_0_VDEMCER_TMVAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_VDE_0_VDEMCER_TMVAL_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_VDE_0_VDEMCER_TMVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_VDE_0_VDEMCER_TMVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_VDE_0_VDETPER_TMVAL_SHIFT                    _MK_SHIFT_CONST(16)
+#define MC_TIMEOUT_VDE_0_VDETPER_TMVAL_FIELD                    (_MK_MASK_CONST(0xf) << MC_TIMEOUT_VDE_0_VDETPER_TMVAL_SHIFT)
+#define MC_TIMEOUT_VDE_0_VDETPER_TMVAL_RANGE                    19:16
+#define MC_TIMEOUT_VDE_0_VDETPER_TMVAL_WOFFSET                  0x0
+#define MC_TIMEOUT_VDE_0_VDETPER_TMVAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_VDE_0_VDETPER_TMVAL_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_VDE_0_VDETPER_TMVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_VDE_0_VDETPER_TMVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_VDE_0_VDEBSEAW_TMVAL_SHIFT                   _MK_SHIFT_CONST(20)
+#define MC_TIMEOUT_VDE_0_VDEBSEAW_TMVAL_FIELD                   (_MK_MASK_CONST(0xf) << MC_TIMEOUT_VDE_0_VDEBSEAW_TMVAL_SHIFT)
+#define MC_TIMEOUT_VDE_0_VDEBSEAW_TMVAL_RANGE                   23:20
+#define MC_TIMEOUT_VDE_0_VDEBSEAW_TMVAL_WOFFSET                 0x0
+#define MC_TIMEOUT_VDE_0_VDEBSEAW_TMVAL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_VDE_0_VDEBSEAW_TMVAL_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_VDE_0_VDEBSEAW_TMVAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_VDE_0_VDEBSEAW_TMVAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_VDE_0_VDEBSEVW_TMVAL_SHIFT                   _MK_SHIFT_CONST(24)
+#define MC_TIMEOUT_VDE_0_VDEBSEVW_TMVAL_FIELD                   (_MK_MASK_CONST(0xf) << MC_TIMEOUT_VDE_0_VDEBSEVW_TMVAL_SHIFT)
+#define MC_TIMEOUT_VDE_0_VDEBSEVW_TMVAL_RANGE                   27:24
+#define MC_TIMEOUT_VDE_0_VDEBSEVW_TMVAL_WOFFSET                 0x0
+#define MC_TIMEOUT_VDE_0_VDEBSEVW_TMVAL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_VDE_0_VDEBSEVW_TMVAL_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_VDE_0_VDEBSEVW_TMVAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_VDE_0_VDEBSEVW_TMVAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_VDE_0_VDEMBEW_TMVAL_SHIFT                    _MK_SHIFT_CONST(28)
+#define MC_TIMEOUT_VDE_0_VDEMBEW_TMVAL_FIELD                    (_MK_MASK_CONST(0xf) << MC_TIMEOUT_VDE_0_VDEMBEW_TMVAL_SHIFT)
+#define MC_TIMEOUT_VDE_0_VDEMBEW_TMVAL_RANGE                    31:28
+#define MC_TIMEOUT_VDE_0_VDEMBEW_TMVAL_WOFFSET                  0x0
+#define MC_TIMEOUT_VDE_0_VDEMBEW_TMVAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_VDE_0_VDEMBEW_TMVAL_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_VDE_0_VDEMBEW_TMVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_VDE_0_VDEMBEW_TMVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register MC_TIMEOUT1_VDE_0  
+#define MC_TIMEOUT1_VDE_0                       _MK_ADDR_CONST(0x15c)
+#define MC_TIMEOUT1_VDE_0_WORD_COUNT                    0x1
+#define MC_TIMEOUT1_VDE_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT1_VDE_0_RESET_MASK                    _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT1_VDE_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT1_VDE_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT1_VDE_0_READ_MASK                     _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT1_VDE_0_WRITE_MASK                    _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT1_VDE_0_VDETPMW_TMVAL_SHIFT                   _MK_SHIFT_CONST(0)
+#define MC_TIMEOUT1_VDE_0_VDETPMW_TMVAL_FIELD                   (_MK_MASK_CONST(0xf) << MC_TIMEOUT1_VDE_0_VDETPMW_TMVAL_SHIFT)
+#define MC_TIMEOUT1_VDE_0_VDETPMW_TMVAL_RANGE                   3:0
+#define MC_TIMEOUT1_VDE_0_VDETPMW_TMVAL_WOFFSET                 0x0
+#define MC_TIMEOUT1_VDE_0_VDETPMW_TMVAL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT1_VDE_0_VDETPMW_TMVAL_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT1_VDE_0_VDETPMW_TMVAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT1_VDE_0_VDETPMW_TMVAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register MC_TIMEOUT_VI_0  
+#define MC_TIMEOUT_VI_0                 _MK_ADDR_CONST(0x160)
+#define MC_TIMEOUT_VI_0_WORD_COUNT                      0x1
+#define MC_TIMEOUT_VI_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_VI_0_RESET_MASK                      _MK_MASK_CONST(0xfffff)
+#define MC_TIMEOUT_VI_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_VI_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_VI_0_READ_MASK                       _MK_MASK_CONST(0xfffff)
+#define MC_TIMEOUT_VI_0_WRITE_MASK                      _MK_MASK_CONST(0xfffff)
+#define MC_TIMEOUT_VI_0_VIRUV_TMVAL_SHIFT                       _MK_SHIFT_CONST(0)
+#define MC_TIMEOUT_VI_0_VIRUV_TMVAL_FIELD                       (_MK_MASK_CONST(0xf) << MC_TIMEOUT_VI_0_VIRUV_TMVAL_SHIFT)
+#define MC_TIMEOUT_VI_0_VIRUV_TMVAL_RANGE                       3:0
+#define MC_TIMEOUT_VI_0_VIRUV_TMVAL_WOFFSET                     0x0
+#define MC_TIMEOUT_VI_0_VIRUV_TMVAL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_VI_0_VIRUV_TMVAL_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_VI_0_VIRUV_TMVAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_VI_0_VIRUV_TMVAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_VI_0_VIWSB_TMVAL_SHIFT                       _MK_SHIFT_CONST(4)
+#define MC_TIMEOUT_VI_0_VIWSB_TMVAL_FIELD                       (_MK_MASK_CONST(0xf) << MC_TIMEOUT_VI_0_VIWSB_TMVAL_SHIFT)
+#define MC_TIMEOUT_VI_0_VIWSB_TMVAL_RANGE                       7:4
+#define MC_TIMEOUT_VI_0_VIWSB_TMVAL_WOFFSET                     0x0
+#define MC_TIMEOUT_VI_0_VIWSB_TMVAL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_VI_0_VIWSB_TMVAL_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_VI_0_VIWSB_TMVAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_VI_0_VIWSB_TMVAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_VI_0_VIWU_TMVAL_SHIFT                        _MK_SHIFT_CONST(8)
+#define MC_TIMEOUT_VI_0_VIWU_TMVAL_FIELD                        (_MK_MASK_CONST(0xf) << MC_TIMEOUT_VI_0_VIWU_TMVAL_SHIFT)
+#define MC_TIMEOUT_VI_0_VIWU_TMVAL_RANGE                        11:8
+#define MC_TIMEOUT_VI_0_VIWU_TMVAL_WOFFSET                      0x0
+#define MC_TIMEOUT_VI_0_VIWU_TMVAL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_VI_0_VIWU_TMVAL_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_VI_0_VIWU_TMVAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_VI_0_VIWU_TMVAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_VI_0_VIWV_TMVAL_SHIFT                        _MK_SHIFT_CONST(12)
+#define MC_TIMEOUT_VI_0_VIWV_TMVAL_FIELD                        (_MK_MASK_CONST(0xf) << MC_TIMEOUT_VI_0_VIWV_TMVAL_SHIFT)
+#define MC_TIMEOUT_VI_0_VIWV_TMVAL_RANGE                        15:12
+#define MC_TIMEOUT_VI_0_VIWV_TMVAL_WOFFSET                      0x0
+#define MC_TIMEOUT_VI_0_VIWV_TMVAL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_VI_0_VIWV_TMVAL_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_VI_0_VIWV_TMVAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_VI_0_VIWV_TMVAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_VI_0_VIWY_TMVAL_SHIFT                        _MK_SHIFT_CONST(16)
+#define MC_TIMEOUT_VI_0_VIWY_TMVAL_FIELD                        (_MK_MASK_CONST(0xf) << MC_TIMEOUT_VI_0_VIWY_TMVAL_SHIFT)
+#define MC_TIMEOUT_VI_0_VIWY_TMVAL_RANGE                        19:16
+#define MC_TIMEOUT_VI_0_VIWY_TMVAL_WOFFSET                      0x0
+#define MC_TIMEOUT_VI_0_VIWY_TMVAL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_VI_0_VIWY_TMVAL_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_VI_0_VIWY_TMVAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_VI_0_VIWY_TMVAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register MC_TIMEOUT_RCOAL_CMC_0  
+#define MC_TIMEOUT_RCOAL_CMC_0                  _MK_ADDR_CONST(0x164)
+#define MC_TIMEOUT_RCOAL_CMC_0_WORD_COUNT                       0x1
+#define MC_TIMEOUT_RCOAL_CMC_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_CMC_0_RESET_MASK                       _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_RCOAL_CMC_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_CMC_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_CMC_0_READ_MASK                        _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_RCOAL_CMC_0_WRITE_MASK                       _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_RCOAL_CMC_0_CMCR_RCOAL_TMVAL_SHIFT                   _MK_SHIFT_CONST(0)
+#define MC_TIMEOUT_RCOAL_CMC_0_CMCR_RCOAL_TMVAL_FIELD                   (_MK_MASK_CONST(0xf) << MC_TIMEOUT_RCOAL_CMC_0_CMCR_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_CMC_0_CMCR_RCOAL_TMVAL_RANGE                   3:0
+#define MC_TIMEOUT_RCOAL_CMC_0_CMCR_RCOAL_TMVAL_WOFFSET                 0x0
+#define MC_TIMEOUT_RCOAL_CMC_0_CMCR_RCOAL_TMVAL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_CMC_0_CMCR_RCOAL_TMVAL_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_RCOAL_CMC_0_CMCR_RCOAL_TMVAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_CMC_0_CMCR_RCOAL_TMVAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register MC_TIMEOUT_RCOAL_DC_0  
+#define MC_TIMEOUT_RCOAL_DC_0                   _MK_ADDR_CONST(0x168)
+#define MC_TIMEOUT_RCOAL_DC_0_WORD_COUNT                        0x1
+#define MC_TIMEOUT_RCOAL_DC_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_DC_0_RESET_MASK                        _MK_MASK_CONST(0xfffff)
+#define MC_TIMEOUT_RCOAL_DC_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_DC_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_DC_0_READ_MASK                         _MK_MASK_CONST(0xfffff)
+#define MC_TIMEOUT_RCOAL_DC_0_WRITE_MASK                        _MK_MASK_CONST(0xfffff)
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY0A_RCOAL_TMVAL_SHIFT                       _MK_SHIFT_CONST(0)
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY0A_RCOAL_TMVAL_FIELD                       (_MK_MASK_CONST(0xf) << MC_TIMEOUT_RCOAL_DC_0_DISPLAY0A_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY0A_RCOAL_TMVAL_RANGE                       3:0
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY0A_RCOAL_TMVAL_WOFFSET                     0x0
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY0A_RCOAL_TMVAL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY0A_RCOAL_TMVAL_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY0A_RCOAL_TMVAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY0A_RCOAL_TMVAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY0B_RCOAL_TMVAL_SHIFT                       _MK_SHIFT_CONST(4)
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY0B_RCOAL_TMVAL_FIELD                       (_MK_MASK_CONST(0xf) << MC_TIMEOUT_RCOAL_DC_0_DISPLAY0B_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY0B_RCOAL_TMVAL_RANGE                       7:4
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY0B_RCOAL_TMVAL_WOFFSET                     0x0
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY0B_RCOAL_TMVAL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY0B_RCOAL_TMVAL_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY0B_RCOAL_TMVAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY0B_RCOAL_TMVAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY0C_RCOAL_TMVAL_SHIFT                       _MK_SHIFT_CONST(8)
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY0C_RCOAL_TMVAL_FIELD                       (_MK_MASK_CONST(0xf) << MC_TIMEOUT_RCOAL_DC_0_DISPLAY0C_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY0C_RCOAL_TMVAL_RANGE                       11:8
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY0C_RCOAL_TMVAL_WOFFSET                     0x0
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY0C_RCOAL_TMVAL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY0C_RCOAL_TMVAL_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY0C_RCOAL_TMVAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY0C_RCOAL_TMVAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY1B_RCOAL_TMVAL_SHIFT                       _MK_SHIFT_CONST(12)
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY1B_RCOAL_TMVAL_FIELD                       (_MK_MASK_CONST(0xf) << MC_TIMEOUT_RCOAL_DC_0_DISPLAY1B_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY1B_RCOAL_TMVAL_RANGE                       15:12
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY1B_RCOAL_TMVAL_WOFFSET                     0x0
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY1B_RCOAL_TMVAL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY1B_RCOAL_TMVAL_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY1B_RCOAL_TMVAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY1B_RCOAL_TMVAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAYHC_RCOAL_TMVAL_SHIFT                       _MK_SHIFT_CONST(16)
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAYHC_RCOAL_TMVAL_FIELD                       (_MK_MASK_CONST(0xf) << MC_TIMEOUT_RCOAL_DC_0_DISPLAYHC_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAYHC_RCOAL_TMVAL_RANGE                       19:16
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAYHC_RCOAL_TMVAL_WOFFSET                     0x0
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAYHC_RCOAL_TMVAL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAYHC_RCOAL_TMVAL_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAYHC_RCOAL_TMVAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAYHC_RCOAL_TMVAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register MC_TIMEOUT_RCOAL_DCB_0  
+#define MC_TIMEOUT_RCOAL_DCB_0                  _MK_ADDR_CONST(0x16c)
+#define MC_TIMEOUT_RCOAL_DCB_0_WORD_COUNT                       0x1
+#define MC_TIMEOUT_RCOAL_DCB_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_DCB_0_RESET_MASK                       _MK_MASK_CONST(0xfffff)
+#define MC_TIMEOUT_RCOAL_DCB_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_DCB_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_DCB_0_READ_MASK                        _MK_MASK_CONST(0xfffff)
+#define MC_TIMEOUT_RCOAL_DCB_0_WRITE_MASK                       _MK_MASK_CONST(0xfffff)
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY0AB_RCOAL_TMVAL_SHIFT                     _MK_SHIFT_CONST(0)
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY0AB_RCOAL_TMVAL_FIELD                     (_MK_MASK_CONST(0xf) << MC_TIMEOUT_RCOAL_DCB_0_DISPLAY0AB_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY0AB_RCOAL_TMVAL_RANGE                     3:0
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY0AB_RCOAL_TMVAL_WOFFSET                   0x0
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY0AB_RCOAL_TMVAL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY0AB_RCOAL_TMVAL_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY0AB_RCOAL_TMVAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY0AB_RCOAL_TMVAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY0BB_RCOAL_TMVAL_SHIFT                     _MK_SHIFT_CONST(4)
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY0BB_RCOAL_TMVAL_FIELD                     (_MK_MASK_CONST(0xf) << MC_TIMEOUT_RCOAL_DCB_0_DISPLAY0BB_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY0BB_RCOAL_TMVAL_RANGE                     7:4
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY0BB_RCOAL_TMVAL_WOFFSET                   0x0
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY0BB_RCOAL_TMVAL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY0BB_RCOAL_TMVAL_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY0BB_RCOAL_TMVAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY0BB_RCOAL_TMVAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY0CB_RCOAL_TMVAL_SHIFT                     _MK_SHIFT_CONST(8)
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY0CB_RCOAL_TMVAL_FIELD                     (_MK_MASK_CONST(0xf) << MC_TIMEOUT_RCOAL_DCB_0_DISPLAY0CB_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY0CB_RCOAL_TMVAL_RANGE                     11:8
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY0CB_RCOAL_TMVAL_WOFFSET                   0x0
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY0CB_RCOAL_TMVAL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY0CB_RCOAL_TMVAL_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY0CB_RCOAL_TMVAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY0CB_RCOAL_TMVAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY1BB_RCOAL_TMVAL_SHIFT                     _MK_SHIFT_CONST(12)
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY1BB_RCOAL_TMVAL_FIELD                     (_MK_MASK_CONST(0xf) << MC_TIMEOUT_RCOAL_DCB_0_DISPLAY1BB_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY1BB_RCOAL_TMVAL_RANGE                     15:12
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY1BB_RCOAL_TMVAL_WOFFSET                   0x0
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY1BB_RCOAL_TMVAL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY1BB_RCOAL_TMVAL_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY1BB_RCOAL_TMVAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY1BB_RCOAL_TMVAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAYHCB_RCOAL_TMVAL_SHIFT                     _MK_SHIFT_CONST(16)
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAYHCB_RCOAL_TMVAL_FIELD                     (_MK_MASK_CONST(0xf) << MC_TIMEOUT_RCOAL_DCB_0_DISPLAYHCB_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAYHCB_RCOAL_TMVAL_RANGE                     19:16
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAYHCB_RCOAL_TMVAL_WOFFSET                   0x0
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAYHCB_RCOAL_TMVAL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAYHCB_RCOAL_TMVAL_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAYHCB_RCOAL_TMVAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAYHCB_RCOAL_TMVAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register MC_TIMEOUT_RCOAL_EPP_0  
+#define MC_TIMEOUT_RCOAL_EPP_0                  _MK_ADDR_CONST(0x170)
+#define MC_TIMEOUT_RCOAL_EPP_0_WORD_COUNT                       0x1
+#define MC_TIMEOUT_RCOAL_EPP_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_EPP_0_RESET_MASK                       _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_RCOAL_EPP_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_EPP_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_EPP_0_READ_MASK                        _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_RCOAL_EPP_0_WRITE_MASK                       _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_RCOAL_EPP_0_EPPUP_RCOAL_TMVAL_SHIFT                  _MK_SHIFT_CONST(0)
+#define MC_TIMEOUT_RCOAL_EPP_0_EPPUP_RCOAL_TMVAL_FIELD                  (_MK_MASK_CONST(0xf) << MC_TIMEOUT_RCOAL_EPP_0_EPPUP_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_EPP_0_EPPUP_RCOAL_TMVAL_RANGE                  3:0
+#define MC_TIMEOUT_RCOAL_EPP_0_EPPUP_RCOAL_TMVAL_WOFFSET                        0x0
+#define MC_TIMEOUT_RCOAL_EPP_0_EPPUP_RCOAL_TMVAL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_EPP_0_EPPUP_RCOAL_TMVAL_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_RCOAL_EPP_0_EPPUP_RCOAL_TMVAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_EPP_0_EPPUP_RCOAL_TMVAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register MC_TIMEOUT_RCOAL_G2_0  
+#define MC_TIMEOUT_RCOAL_G2_0                   _MK_ADDR_CONST(0x174)
+#define MC_TIMEOUT_RCOAL_G2_0_WORD_COUNT                        0x1
+#define MC_TIMEOUT_RCOAL_G2_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_G2_0_RESET_MASK                        _MK_MASK_CONST(0xfff)
+#define MC_TIMEOUT_RCOAL_G2_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_G2_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_G2_0_READ_MASK                         _MK_MASK_CONST(0xfff)
+#define MC_TIMEOUT_RCOAL_G2_0_WRITE_MASK                        _MK_MASK_CONST(0xfff)
+#define MC_TIMEOUT_RCOAL_G2_0_G2PR_RCOAL_TMVAL_SHIFT                    _MK_SHIFT_CONST(0)
+#define MC_TIMEOUT_RCOAL_G2_0_G2PR_RCOAL_TMVAL_FIELD                    (_MK_MASK_CONST(0xf) << MC_TIMEOUT_RCOAL_G2_0_G2PR_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_G2_0_G2PR_RCOAL_TMVAL_RANGE                    3:0
+#define MC_TIMEOUT_RCOAL_G2_0_G2PR_RCOAL_TMVAL_WOFFSET                  0x0
+#define MC_TIMEOUT_RCOAL_G2_0_G2PR_RCOAL_TMVAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_G2_0_G2PR_RCOAL_TMVAL_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_RCOAL_G2_0_G2PR_RCOAL_TMVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_G2_0_G2PR_RCOAL_TMVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_RCOAL_G2_0_G2SR_RCOAL_TMVAL_SHIFT                    _MK_SHIFT_CONST(4)
+#define MC_TIMEOUT_RCOAL_G2_0_G2SR_RCOAL_TMVAL_FIELD                    (_MK_MASK_CONST(0xf) << MC_TIMEOUT_RCOAL_G2_0_G2SR_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_G2_0_G2SR_RCOAL_TMVAL_RANGE                    7:4
+#define MC_TIMEOUT_RCOAL_G2_0_G2SR_RCOAL_TMVAL_WOFFSET                  0x0
+#define MC_TIMEOUT_RCOAL_G2_0_G2SR_RCOAL_TMVAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_G2_0_G2SR_RCOAL_TMVAL_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_RCOAL_G2_0_G2SR_RCOAL_TMVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_G2_0_G2SR_RCOAL_TMVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_RCOAL_G2_0_G2DR_RCOAL_TMVAL_SHIFT                    _MK_SHIFT_CONST(8)
+#define MC_TIMEOUT_RCOAL_G2_0_G2DR_RCOAL_TMVAL_FIELD                    (_MK_MASK_CONST(0xf) << MC_TIMEOUT_RCOAL_G2_0_G2DR_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_G2_0_G2DR_RCOAL_TMVAL_RANGE                    11:8
+#define MC_TIMEOUT_RCOAL_G2_0_G2DR_RCOAL_TMVAL_WOFFSET                  0x0
+#define MC_TIMEOUT_RCOAL_G2_0_G2DR_RCOAL_TMVAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_G2_0_G2DR_RCOAL_TMVAL_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_RCOAL_G2_0_G2DR_RCOAL_TMVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_G2_0_G2DR_RCOAL_TMVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register MC_TIMEOUT_RCOAL_HC_0  
+#define MC_TIMEOUT_RCOAL_HC_0                   _MK_ADDR_CONST(0x178)
+#define MC_TIMEOUT_RCOAL_HC_0_WORD_COUNT                        0x1
+#define MC_TIMEOUT_RCOAL_HC_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_HC_0_RESET_MASK                        _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_RCOAL_HC_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_HC_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_HC_0_READ_MASK                         _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_RCOAL_HC_0_WRITE_MASK                        _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_RCOAL_HC_0_HOST1XDMAR_RCOAL_TMVAL_SHIFT                      _MK_SHIFT_CONST(0)
+#define MC_TIMEOUT_RCOAL_HC_0_HOST1XDMAR_RCOAL_TMVAL_FIELD                      (_MK_MASK_CONST(0xf) << MC_TIMEOUT_RCOAL_HC_0_HOST1XDMAR_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_HC_0_HOST1XDMAR_RCOAL_TMVAL_RANGE                      3:0
+#define MC_TIMEOUT_RCOAL_HC_0_HOST1XDMAR_RCOAL_TMVAL_WOFFSET                    0x0
+#define MC_TIMEOUT_RCOAL_HC_0_HOST1XDMAR_RCOAL_TMVAL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_HC_0_HOST1XDMAR_RCOAL_TMVAL_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_RCOAL_HC_0_HOST1XDMAR_RCOAL_TMVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_HC_0_HOST1XDMAR_RCOAL_TMVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_RCOAL_HC_0_HOST1XR_RCOAL_TMVAL_SHIFT                 _MK_SHIFT_CONST(4)
+#define MC_TIMEOUT_RCOAL_HC_0_HOST1XR_RCOAL_TMVAL_FIELD                 (_MK_MASK_CONST(0xf) << MC_TIMEOUT_RCOAL_HC_0_HOST1XR_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_HC_0_HOST1XR_RCOAL_TMVAL_RANGE                 7:4
+#define MC_TIMEOUT_RCOAL_HC_0_HOST1XR_RCOAL_TMVAL_WOFFSET                       0x0
+#define MC_TIMEOUT_RCOAL_HC_0_HOST1XR_RCOAL_TMVAL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_HC_0_HOST1XR_RCOAL_TMVAL_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_RCOAL_HC_0_HOST1XR_RCOAL_TMVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_HC_0_HOST1XR_RCOAL_TMVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register MC_TIMEOUT_RCOAL_MPCORE_0  
+#define MC_TIMEOUT_RCOAL_MPCORE_0                       _MK_ADDR_CONST(0x17c)
+#define MC_TIMEOUT_RCOAL_MPCORE_0_WORD_COUNT                    0x1
+#define MC_TIMEOUT_RCOAL_MPCORE_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_MPCORE_0_RESET_MASK                    _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_RCOAL_MPCORE_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_MPCORE_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_MPCORE_0_READ_MASK                     _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_RCOAL_MPCORE_0_WRITE_MASK                    _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_RCOAL_MPCORE_0_MPCORER_RCOAL_TMVAL_SHIFT                     _MK_SHIFT_CONST(0)
+#define MC_TIMEOUT_RCOAL_MPCORE_0_MPCORER_RCOAL_TMVAL_FIELD                     (_MK_MASK_CONST(0xf) << MC_TIMEOUT_RCOAL_MPCORE_0_MPCORER_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_MPCORE_0_MPCORER_RCOAL_TMVAL_RANGE                     3:0
+#define MC_TIMEOUT_RCOAL_MPCORE_0_MPCORER_RCOAL_TMVAL_WOFFSET                   0x0
+#define MC_TIMEOUT_RCOAL_MPCORE_0_MPCORER_RCOAL_TMVAL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_MPCORE_0_MPCORER_RCOAL_TMVAL_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_RCOAL_MPCORE_0_MPCORER_RCOAL_TMVAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_MPCORE_0_MPCORER_RCOAL_TMVAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register MC_TIMEOUT_RCOAL_MPEA_0  
+#define MC_TIMEOUT_RCOAL_MPEA_0                 _MK_ADDR_CONST(0x180)
+#define MC_TIMEOUT_RCOAL_MPEA_0_WORD_COUNT                      0x1
+#define MC_TIMEOUT_RCOAL_MPEA_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_MPEA_0_RESET_MASK                      _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_RCOAL_MPEA_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_MPEA_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_MPEA_0_READ_MASK                       _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_RCOAL_MPEA_0_WRITE_MASK                      _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_RCOAL_MPEA_0_MPEAMEMRD_RCOAL_TMVAL_SHIFT                     _MK_SHIFT_CONST(0)
+#define MC_TIMEOUT_RCOAL_MPEA_0_MPEAMEMRD_RCOAL_TMVAL_FIELD                     (_MK_MASK_CONST(0xf) << MC_TIMEOUT_RCOAL_MPEA_0_MPEAMEMRD_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_MPEA_0_MPEAMEMRD_RCOAL_TMVAL_RANGE                     3:0
+#define MC_TIMEOUT_RCOAL_MPEA_0_MPEAMEMRD_RCOAL_TMVAL_WOFFSET                   0x0
+#define MC_TIMEOUT_RCOAL_MPEA_0_MPEAMEMRD_RCOAL_TMVAL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_MPEA_0_MPEAMEMRD_RCOAL_TMVAL_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_RCOAL_MPEA_0_MPEAMEMRD_RCOAL_TMVAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_MPEA_0_MPEAMEMRD_RCOAL_TMVAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register MC_TIMEOUT_RCOAL_MPEB_0  
+#define MC_TIMEOUT_RCOAL_MPEB_0                 _MK_ADDR_CONST(0x184)
+#define MC_TIMEOUT_RCOAL_MPEB_0_WORD_COUNT                      0x1
+#define MC_TIMEOUT_RCOAL_MPEB_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_MPEB_0_RESET_MASK                      _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_RCOAL_MPEB_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_MPEB_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_MPEB_0_READ_MASK                       _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_RCOAL_MPEB_0_WRITE_MASK                      _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_RCOAL_MPEB_0_MPEUNIFBR_RCOAL_TMVAL_SHIFT                     _MK_SHIFT_CONST(0)
+#define MC_TIMEOUT_RCOAL_MPEB_0_MPEUNIFBR_RCOAL_TMVAL_FIELD                     (_MK_MASK_CONST(0xf) << MC_TIMEOUT_RCOAL_MPEB_0_MPEUNIFBR_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_MPEB_0_MPEUNIFBR_RCOAL_TMVAL_RANGE                     3:0
+#define MC_TIMEOUT_RCOAL_MPEB_0_MPEUNIFBR_RCOAL_TMVAL_WOFFSET                   0x0
+#define MC_TIMEOUT_RCOAL_MPEB_0_MPEUNIFBR_RCOAL_TMVAL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_MPEB_0_MPEUNIFBR_RCOAL_TMVAL_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_RCOAL_MPEB_0_MPEUNIFBR_RCOAL_TMVAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_MPEB_0_MPEUNIFBR_RCOAL_TMVAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_RCOAL_MPEB_0_MPE_IPRED_RCOAL_TMVAL_SHIFT                     _MK_SHIFT_CONST(4)
+#define MC_TIMEOUT_RCOAL_MPEB_0_MPE_IPRED_RCOAL_TMVAL_FIELD                     (_MK_MASK_CONST(0xf) << MC_TIMEOUT_RCOAL_MPEB_0_MPE_IPRED_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_MPEB_0_MPE_IPRED_RCOAL_TMVAL_RANGE                     7:4
+#define MC_TIMEOUT_RCOAL_MPEB_0_MPE_IPRED_RCOAL_TMVAL_WOFFSET                   0x0
+#define MC_TIMEOUT_RCOAL_MPEB_0_MPE_IPRED_RCOAL_TMVAL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_MPEB_0_MPE_IPRED_RCOAL_TMVAL_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_RCOAL_MPEB_0_MPE_IPRED_RCOAL_TMVAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_MPEB_0_MPE_IPRED_RCOAL_TMVAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register MC_TIMEOUT_RCOAL_MPEC_0  
+#define MC_TIMEOUT_RCOAL_MPEC_0                 _MK_ADDR_CONST(0x188)
+#define MC_TIMEOUT_RCOAL_MPEC_0_WORD_COUNT                      0x1
+#define MC_TIMEOUT_RCOAL_MPEC_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_MPEC_0_RESET_MASK                      _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_RCOAL_MPEC_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_MPEC_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_MPEC_0_READ_MASK                       _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_RCOAL_MPEC_0_WRITE_MASK                      _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_RCOAL_MPEC_0_MPECSRD_RCOAL_TMVAL_SHIFT                       _MK_SHIFT_CONST(0)
+#define MC_TIMEOUT_RCOAL_MPEC_0_MPECSRD_RCOAL_TMVAL_FIELD                       (_MK_MASK_CONST(0xf) << MC_TIMEOUT_RCOAL_MPEC_0_MPECSRD_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_MPEC_0_MPECSRD_RCOAL_TMVAL_RANGE                       3:0
+#define MC_TIMEOUT_RCOAL_MPEC_0_MPECSRD_RCOAL_TMVAL_WOFFSET                     0x0
+#define MC_TIMEOUT_RCOAL_MPEC_0_MPECSRD_RCOAL_TMVAL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_MPEC_0_MPECSRD_RCOAL_TMVAL_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_RCOAL_MPEC_0_MPECSRD_RCOAL_TMVAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_MPEC_0_MPECSRD_RCOAL_TMVAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register MC_TIMEOUT_RCOAL_NV_0  
+#define MC_TIMEOUT_RCOAL_NV_0                   _MK_ADDR_CONST(0x18c)
+#define MC_TIMEOUT_RCOAL_NV_0_WORD_COUNT                        0x1
+#define MC_TIMEOUT_RCOAL_NV_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_NV_0_RESET_MASK                        _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_RCOAL_NV_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_NV_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_NV_0_READ_MASK                         _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_RCOAL_NV_0_WRITE_MASK                        _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_RCOAL_NV_0_IDXSRD_RCOAL_TMVAL_SHIFT                  _MK_SHIFT_CONST(0)
+#define MC_TIMEOUT_RCOAL_NV_0_IDXSRD_RCOAL_TMVAL_FIELD                  (_MK_MASK_CONST(0xf) << MC_TIMEOUT_RCOAL_NV_0_IDXSRD_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_NV_0_IDXSRD_RCOAL_TMVAL_RANGE                  3:0
+#define MC_TIMEOUT_RCOAL_NV_0_IDXSRD_RCOAL_TMVAL_WOFFSET                        0x0
+#define MC_TIMEOUT_RCOAL_NV_0_IDXSRD_RCOAL_TMVAL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_NV_0_IDXSRD_RCOAL_TMVAL_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_RCOAL_NV_0_IDXSRD_RCOAL_TMVAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_NV_0_IDXSRD_RCOAL_TMVAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_RCOAL_NV_0_TEXSRD_RCOAL_TMVAL_SHIFT                  _MK_SHIFT_CONST(4)
+#define MC_TIMEOUT_RCOAL_NV_0_TEXSRD_RCOAL_TMVAL_FIELD                  (_MK_MASK_CONST(0xf) << MC_TIMEOUT_RCOAL_NV_0_TEXSRD_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_NV_0_TEXSRD_RCOAL_TMVAL_RANGE                  7:4
+#define MC_TIMEOUT_RCOAL_NV_0_TEXSRD_RCOAL_TMVAL_WOFFSET                        0x0
+#define MC_TIMEOUT_RCOAL_NV_0_TEXSRD_RCOAL_TMVAL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_NV_0_TEXSRD_RCOAL_TMVAL_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_RCOAL_NV_0_TEXSRD_RCOAL_TMVAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_NV_0_TEXSRD_RCOAL_TMVAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register MC_TIMEOUT_RCOAL_PPCS_0  
+#define MC_TIMEOUT_RCOAL_PPCS_0                 _MK_ADDR_CONST(0x190)
+#define MC_TIMEOUT_RCOAL_PPCS_0_WORD_COUNT                      0x1
+#define MC_TIMEOUT_RCOAL_PPCS_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_PPCS_0_RESET_MASK                      _MK_MASK_CONST(0xfff)
+#define MC_TIMEOUT_RCOAL_PPCS_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_PPCS_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_PPCS_0_READ_MASK                       _MK_MASK_CONST(0xfff)
+#define MC_TIMEOUT_RCOAL_PPCS_0_WRITE_MASK                      _MK_MASK_CONST(0xfff)
+#define MC_TIMEOUT_RCOAL_PPCS_0_PPCSAHBDMAR_RCOAL_TMVAL_SHIFT                   _MK_SHIFT_CONST(0)
+#define MC_TIMEOUT_RCOAL_PPCS_0_PPCSAHBDMAR_RCOAL_TMVAL_FIELD                   (_MK_MASK_CONST(0xf) << MC_TIMEOUT_RCOAL_PPCS_0_PPCSAHBDMAR_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_PPCS_0_PPCSAHBDMAR_RCOAL_TMVAL_RANGE                   3:0
+#define MC_TIMEOUT_RCOAL_PPCS_0_PPCSAHBDMAR_RCOAL_TMVAL_WOFFSET                 0x0
+#define MC_TIMEOUT_RCOAL_PPCS_0_PPCSAHBDMAR_RCOAL_TMVAL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_PPCS_0_PPCSAHBDMAR_RCOAL_TMVAL_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_RCOAL_PPCS_0_PPCSAHBDMAR_RCOAL_TMVAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_PPCS_0_PPCSAHBDMAR_RCOAL_TMVAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_RCOAL_PPCS_0_PPCSAHBSLVR_RCOAL_TMVAL_SHIFT                   _MK_SHIFT_CONST(4)
+#define MC_TIMEOUT_RCOAL_PPCS_0_PPCSAHBSLVR_RCOAL_TMVAL_FIELD                   (_MK_MASK_CONST(0xf) << MC_TIMEOUT_RCOAL_PPCS_0_PPCSAHBSLVR_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_PPCS_0_PPCSAHBSLVR_RCOAL_TMVAL_RANGE                   7:4
+#define MC_TIMEOUT_RCOAL_PPCS_0_PPCSAHBSLVR_RCOAL_TMVAL_WOFFSET                 0x0
+#define MC_TIMEOUT_RCOAL_PPCS_0_PPCSAHBSLVR_RCOAL_TMVAL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_PPCS_0_PPCSAHBSLVR_RCOAL_TMVAL_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_RCOAL_PPCS_0_PPCSAHBSLVR_RCOAL_TMVAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_PPCS_0_PPCSAHBSLVR_RCOAL_TMVAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_RCOAL_PPCS_0_PPCSARM7R_RCOAL_TMVAL_SHIFT                     _MK_SHIFT_CONST(8)
+#define MC_TIMEOUT_RCOAL_PPCS_0_PPCSARM7R_RCOAL_TMVAL_FIELD                     (_MK_MASK_CONST(0xf) << MC_TIMEOUT_RCOAL_PPCS_0_PPCSARM7R_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_PPCS_0_PPCSARM7R_RCOAL_TMVAL_RANGE                     11:8
+#define MC_TIMEOUT_RCOAL_PPCS_0_PPCSARM7R_RCOAL_TMVAL_WOFFSET                   0x0
+#define MC_TIMEOUT_RCOAL_PPCS_0_PPCSARM7R_RCOAL_TMVAL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_PPCS_0_PPCSARM7R_RCOAL_TMVAL_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_RCOAL_PPCS_0_PPCSARM7R_RCOAL_TMVAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_PPCS_0_PPCSARM7R_RCOAL_TMVAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register MC_TIMEOUT_RCOAL_VDE_0  
+#define MC_TIMEOUT_RCOAL_VDE_0                  _MK_ADDR_CONST(0x194)
+#define MC_TIMEOUT_RCOAL_VDE_0_WORD_COUNT                       0x1
+#define MC_TIMEOUT_RCOAL_VDE_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_VDE_0_RESET_MASK                       _MK_MASK_CONST(0xfffff)
+#define MC_TIMEOUT_RCOAL_VDE_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_VDE_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_VDE_0_READ_MASK                        _MK_MASK_CONST(0xfffff)
+#define MC_TIMEOUT_RCOAL_VDE_0_WRITE_MASK                       _MK_MASK_CONST(0xfffff)
+#define MC_TIMEOUT_RCOAL_VDE_0_VDEBSEAR_RCOAL_TMVAL_SHIFT                       _MK_SHIFT_CONST(0)
+#define MC_TIMEOUT_RCOAL_VDE_0_VDEBSEAR_RCOAL_TMVAL_FIELD                       (_MK_MASK_CONST(0xf) << MC_TIMEOUT_RCOAL_VDE_0_VDEBSEAR_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_VDE_0_VDEBSEAR_RCOAL_TMVAL_RANGE                       3:0
+#define MC_TIMEOUT_RCOAL_VDE_0_VDEBSEAR_RCOAL_TMVAL_WOFFSET                     0x0
+#define MC_TIMEOUT_RCOAL_VDE_0_VDEBSEAR_RCOAL_TMVAL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_VDE_0_VDEBSEAR_RCOAL_TMVAL_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_RCOAL_VDE_0_VDEBSEAR_RCOAL_TMVAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_VDE_0_VDEBSEAR_RCOAL_TMVAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_RCOAL_VDE_0_VDEBSEVR_RCOAL_TMVAL_SHIFT                       _MK_SHIFT_CONST(4)
+#define MC_TIMEOUT_RCOAL_VDE_0_VDEBSEVR_RCOAL_TMVAL_FIELD                       (_MK_MASK_CONST(0xf) << MC_TIMEOUT_RCOAL_VDE_0_VDEBSEVR_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_VDE_0_VDEBSEVR_RCOAL_TMVAL_RANGE                       7:4
+#define MC_TIMEOUT_RCOAL_VDE_0_VDEBSEVR_RCOAL_TMVAL_WOFFSET                     0x0
+#define MC_TIMEOUT_RCOAL_VDE_0_VDEBSEVR_RCOAL_TMVAL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_VDE_0_VDEBSEVR_RCOAL_TMVAL_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_RCOAL_VDE_0_VDEBSEVR_RCOAL_TMVAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_VDE_0_VDEBSEVR_RCOAL_TMVAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_RCOAL_VDE_0_VDEMBER_RCOAL_TMVAL_SHIFT                        _MK_SHIFT_CONST(8)
+#define MC_TIMEOUT_RCOAL_VDE_0_VDEMBER_RCOAL_TMVAL_FIELD                        (_MK_MASK_CONST(0xf) << MC_TIMEOUT_RCOAL_VDE_0_VDEMBER_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_VDE_0_VDEMBER_RCOAL_TMVAL_RANGE                        11:8
+#define MC_TIMEOUT_RCOAL_VDE_0_VDEMBER_RCOAL_TMVAL_WOFFSET                      0x0
+#define MC_TIMEOUT_RCOAL_VDE_0_VDEMBER_RCOAL_TMVAL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_VDE_0_VDEMBER_RCOAL_TMVAL_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_RCOAL_VDE_0_VDEMBER_RCOAL_TMVAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_VDE_0_VDEMBER_RCOAL_TMVAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_RCOAL_VDE_0_VDEMCER_RCOAL_TMVAL_SHIFT                        _MK_SHIFT_CONST(12)
+#define MC_TIMEOUT_RCOAL_VDE_0_VDEMCER_RCOAL_TMVAL_FIELD                        (_MK_MASK_CONST(0xf) << MC_TIMEOUT_RCOAL_VDE_0_VDEMCER_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_VDE_0_VDEMCER_RCOAL_TMVAL_RANGE                        15:12
+#define MC_TIMEOUT_RCOAL_VDE_0_VDEMCER_RCOAL_TMVAL_WOFFSET                      0x0
+#define MC_TIMEOUT_RCOAL_VDE_0_VDEMCER_RCOAL_TMVAL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_VDE_0_VDEMCER_RCOAL_TMVAL_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_RCOAL_VDE_0_VDEMCER_RCOAL_TMVAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_VDE_0_VDEMCER_RCOAL_TMVAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_RCOAL_VDE_0_VDETPER_RCOAL_TMVAL_SHIFT                        _MK_SHIFT_CONST(16)
+#define MC_TIMEOUT_RCOAL_VDE_0_VDETPER_RCOAL_TMVAL_FIELD                        (_MK_MASK_CONST(0xf) << MC_TIMEOUT_RCOAL_VDE_0_VDETPER_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_VDE_0_VDETPER_RCOAL_TMVAL_RANGE                        19:16
+#define MC_TIMEOUT_RCOAL_VDE_0_VDETPER_RCOAL_TMVAL_WOFFSET                      0x0
+#define MC_TIMEOUT_RCOAL_VDE_0_VDETPER_RCOAL_TMVAL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_VDE_0_VDETPER_RCOAL_TMVAL_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_RCOAL_VDE_0_VDETPER_RCOAL_TMVAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_VDE_0_VDETPER_RCOAL_TMVAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register MC_TIMEOUT_RCOAL_VI_0  
+#define MC_TIMEOUT_RCOAL_VI_0                   _MK_ADDR_CONST(0x198)
+#define MC_TIMEOUT_RCOAL_VI_0_WORD_COUNT                        0x1
+#define MC_TIMEOUT_RCOAL_VI_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_VI_0_RESET_MASK                        _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_RCOAL_VI_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_VI_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_VI_0_READ_MASK                         _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_RCOAL_VI_0_WRITE_MASK                        _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_RCOAL_VI_0_VIRUV_RCOAL_TMVAL_SHIFT                   _MK_SHIFT_CONST(0)
+#define MC_TIMEOUT_RCOAL_VI_0_VIRUV_RCOAL_TMVAL_FIELD                   (_MK_MASK_CONST(0xf) << MC_TIMEOUT_RCOAL_VI_0_VIRUV_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_VI_0_VIRUV_RCOAL_TMVAL_RANGE                   3:0
+#define MC_TIMEOUT_RCOAL_VI_0_VIRUV_RCOAL_TMVAL_WOFFSET                 0x0
+#define MC_TIMEOUT_RCOAL_VI_0_VIRUV_RCOAL_TMVAL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_VI_0_VIRUV_RCOAL_TMVAL_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_RCOAL_VI_0_VIRUV_RCOAL_TMVAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_VI_0_VIRUV_RCOAL_TMVAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define MC_CLIENT_BWSHARE_DISABLE       0
+#define MC_CLIENT_BWSHARE_ENABLE        1
+
+// Register MC_BWSHARE_EMEM_CTRL_0_0  
+#define MC_BWSHARE_EMEM_CTRL_0_0                        _MK_ADDR_CONST(0x19c)
+#define MC_BWSHARE_EMEM_CTRL_0_0_WORD_COUNT                     0x1
+#define MC_BWSHARE_EMEM_CTRL_0_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
+#define MC_BWSHARE_EMEM_CTRL_0_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define MC_BWSHARE_EMEM_CTRL_0_0_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0A_BW_EMEM_SHIFT                        _MK_SHIFT_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0A_BW_EMEM_FIELD                        (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0A_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0A_BW_EMEM_RANGE                        0:0
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0A_BW_EMEM_WOFFSET                      0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0A_BW_EMEM_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0A_BW_EMEM_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0A_BW_EMEM_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0A_BW_EMEM_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0A_BW_EMEM_INIT_ENUM                    DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0A_BW_EMEM_DISABLE                      _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0A_BW_EMEM_ENABLE                       _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0A_BW_EMEM_DISABLED                     _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0A_BW_EMEM_ENABLED                      _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0AB_BW_EMEM_SHIFT                       _MK_SHIFT_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0AB_BW_EMEM_FIELD                       (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0AB_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0AB_BW_EMEM_RANGE                       1:1
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0AB_BW_EMEM_WOFFSET                     0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0AB_BW_EMEM_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0AB_BW_EMEM_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0AB_BW_EMEM_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0AB_BW_EMEM_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0AB_BW_EMEM_INIT_ENUM                   DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0AB_BW_EMEM_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0AB_BW_EMEM_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0AB_BW_EMEM_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0AB_BW_EMEM_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0B_BW_EMEM_SHIFT                        _MK_SHIFT_CONST(2)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0B_BW_EMEM_FIELD                        (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0B_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0B_BW_EMEM_RANGE                        2:2
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0B_BW_EMEM_WOFFSET                      0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0B_BW_EMEM_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0B_BW_EMEM_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0B_BW_EMEM_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0B_BW_EMEM_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0B_BW_EMEM_INIT_ENUM                    DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0B_BW_EMEM_DISABLE                      _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0B_BW_EMEM_ENABLE                       _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0B_BW_EMEM_DISABLED                     _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0B_BW_EMEM_ENABLED                      _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0BB_BW_EMEM_SHIFT                       _MK_SHIFT_CONST(3)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0BB_BW_EMEM_FIELD                       (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0BB_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0BB_BW_EMEM_RANGE                       3:3
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0BB_BW_EMEM_WOFFSET                     0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0BB_BW_EMEM_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0BB_BW_EMEM_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0BB_BW_EMEM_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0BB_BW_EMEM_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0BB_BW_EMEM_INIT_ENUM                   DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0BB_BW_EMEM_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0BB_BW_EMEM_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0BB_BW_EMEM_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0BB_BW_EMEM_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0C_BW_EMEM_SHIFT                        _MK_SHIFT_CONST(4)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0C_BW_EMEM_FIELD                        (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0C_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0C_BW_EMEM_RANGE                        4:4
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0C_BW_EMEM_WOFFSET                      0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0C_BW_EMEM_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0C_BW_EMEM_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0C_BW_EMEM_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0C_BW_EMEM_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0C_BW_EMEM_INIT_ENUM                    DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0C_BW_EMEM_DISABLE                      _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0C_BW_EMEM_ENABLE                       _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0C_BW_EMEM_DISABLED                     _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0C_BW_EMEM_ENABLED                      _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0CB_BW_EMEM_SHIFT                       _MK_SHIFT_CONST(5)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0CB_BW_EMEM_FIELD                       (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0CB_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0CB_BW_EMEM_RANGE                       5:5
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0CB_BW_EMEM_WOFFSET                     0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0CB_BW_EMEM_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0CB_BW_EMEM_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0CB_BW_EMEM_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0CB_BW_EMEM_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0CB_BW_EMEM_INIT_ENUM                   DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0CB_BW_EMEM_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0CB_BW_EMEM_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0CB_BW_EMEM_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0CB_BW_EMEM_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY1B_BW_EMEM_SHIFT                        _MK_SHIFT_CONST(6)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY1B_BW_EMEM_FIELD                        (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY1B_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY1B_BW_EMEM_RANGE                        6:6
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY1B_BW_EMEM_WOFFSET                      0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY1B_BW_EMEM_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY1B_BW_EMEM_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY1B_BW_EMEM_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY1B_BW_EMEM_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY1B_BW_EMEM_INIT_ENUM                    DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY1B_BW_EMEM_DISABLE                      _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY1B_BW_EMEM_ENABLE                       _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY1B_BW_EMEM_DISABLED                     _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY1B_BW_EMEM_ENABLED                      _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY1BB_BW_EMEM_SHIFT                       _MK_SHIFT_CONST(7)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY1BB_BW_EMEM_FIELD                       (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY1BB_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY1BB_BW_EMEM_RANGE                       7:7
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY1BB_BW_EMEM_WOFFSET                     0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY1BB_BW_EMEM_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY1BB_BW_EMEM_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY1BB_BW_EMEM_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY1BB_BW_EMEM_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY1BB_BW_EMEM_INIT_ENUM                   DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY1BB_BW_EMEM_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY1BB_BW_EMEM_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY1BB_BW_EMEM_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY1BB_BW_EMEM_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_EPPUP_BW_EMEM_SHIFT                    _MK_SHIFT_CONST(8)
+#define MC_BWSHARE_EMEM_CTRL_0_0_EPPUP_BW_EMEM_FIELD                    (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_EPPUP_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_EPPUP_BW_EMEM_RANGE                    8:8
+#define MC_BWSHARE_EMEM_CTRL_0_0_EPPUP_BW_EMEM_WOFFSET                  0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_EPPUP_BW_EMEM_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_EPPUP_BW_EMEM_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_EPPUP_BW_EMEM_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_EPPUP_BW_EMEM_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_EPPUP_BW_EMEM_INIT_ENUM                        DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_EPPUP_BW_EMEM_DISABLE                  _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_EPPUP_BW_EMEM_ENABLE                   _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_EPPUP_BW_EMEM_DISABLED                 _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_EPPUP_BW_EMEM_ENABLED                  _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2PR_BW_EMEM_SHIFT                     _MK_SHIFT_CONST(9)
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2PR_BW_EMEM_FIELD                     (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_G2PR_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2PR_BW_EMEM_RANGE                     9:9
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2PR_BW_EMEM_WOFFSET                   0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2PR_BW_EMEM_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2PR_BW_EMEM_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2PR_BW_EMEM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2PR_BW_EMEM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2PR_BW_EMEM_INIT_ENUM                 DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2PR_BW_EMEM_DISABLE                   _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2PR_BW_EMEM_ENABLE                    _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2PR_BW_EMEM_DISABLED                  _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2PR_BW_EMEM_ENABLED                   _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2SR_BW_EMEM_SHIFT                     _MK_SHIFT_CONST(10)
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2SR_BW_EMEM_FIELD                     (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_G2SR_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2SR_BW_EMEM_RANGE                     10:10
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2SR_BW_EMEM_WOFFSET                   0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2SR_BW_EMEM_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2SR_BW_EMEM_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2SR_BW_EMEM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2SR_BW_EMEM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2SR_BW_EMEM_INIT_ENUM                 DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2SR_BW_EMEM_DISABLE                   _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2SR_BW_EMEM_ENABLE                    _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2SR_BW_EMEM_DISABLED                  _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2SR_BW_EMEM_ENABLED                   _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPEUNIFBR_BW_EMEM_SHIFT                        _MK_SHIFT_CONST(11)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPEUNIFBR_BW_EMEM_FIELD                        (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_MPEUNIFBR_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPEUNIFBR_BW_EMEM_RANGE                        11:11
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPEUNIFBR_BW_EMEM_WOFFSET                      0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPEUNIFBR_BW_EMEM_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPEUNIFBR_BW_EMEM_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPEUNIFBR_BW_EMEM_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPEUNIFBR_BW_EMEM_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPEUNIFBR_BW_EMEM_INIT_ENUM                    DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPEUNIFBR_BW_EMEM_DISABLE                      _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPEUNIFBR_BW_EMEM_ENABLE                       _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPEUNIFBR_BW_EMEM_DISABLED                     _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPEUNIFBR_BW_EMEM_ENABLED                      _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_VIRUV_BW_EMEM_SHIFT                    _MK_SHIFT_CONST(12)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VIRUV_BW_EMEM_FIELD                    (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_VIRUV_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VIRUV_BW_EMEM_RANGE                    12:12
+#define MC_BWSHARE_EMEM_CTRL_0_0_VIRUV_BW_EMEM_WOFFSET                  0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_VIRUV_BW_EMEM_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VIRUV_BW_EMEM_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VIRUV_BW_EMEM_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VIRUV_BW_EMEM_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VIRUV_BW_EMEM_INIT_ENUM                        DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_VIRUV_BW_EMEM_DISABLE                  _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VIRUV_BW_EMEM_ENABLE                   _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VIRUV_BW_EMEM_DISABLED                 _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VIRUV_BW_EMEM_ENABLED                  _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_CMCR_BW_EMEM_SHIFT                     _MK_SHIFT_CONST(13)
+#define MC_BWSHARE_EMEM_CTRL_0_0_CMCR_BW_EMEM_FIELD                     (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_CMCR_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_CMCR_BW_EMEM_RANGE                     13:13
+#define MC_BWSHARE_EMEM_CTRL_0_0_CMCR_BW_EMEM_WOFFSET                   0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_CMCR_BW_EMEM_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_CMCR_BW_EMEM_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_CMCR_BW_EMEM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_CMCR_BW_EMEM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_CMCR_BW_EMEM_INIT_ENUM                 DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_CMCR_BW_EMEM_DISABLE                   _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_CMCR_BW_EMEM_ENABLE                    _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_CMCR_BW_EMEM_DISABLED                  _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_CMCR_BW_EMEM_ENABLED                   _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAYHC_BW_EMEM_SHIFT                        _MK_SHIFT_CONST(14)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAYHC_BW_EMEM_FIELD                        (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_DISPLAYHC_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAYHC_BW_EMEM_RANGE                        14:14
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAYHC_BW_EMEM_WOFFSET                      0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAYHC_BW_EMEM_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAYHC_BW_EMEM_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAYHC_BW_EMEM_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAYHC_BW_EMEM_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAYHC_BW_EMEM_INIT_ENUM                    DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAYHC_BW_EMEM_DISABLE                      _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAYHC_BW_EMEM_ENABLE                       _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAYHC_BW_EMEM_DISABLED                     _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAYHC_BW_EMEM_ENABLED                      _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAYHCB_BW_EMEM_SHIFT                       _MK_SHIFT_CONST(15)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAYHCB_BW_EMEM_FIELD                       (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_DISPLAYHCB_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAYHCB_BW_EMEM_RANGE                       15:15
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAYHCB_BW_EMEM_WOFFSET                     0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAYHCB_BW_EMEM_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAYHCB_BW_EMEM_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAYHCB_BW_EMEM_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAYHCB_BW_EMEM_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAYHCB_BW_EMEM_INIT_ENUM                   DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAYHCB_BW_EMEM_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAYHCB_BW_EMEM_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAYHCB_BW_EMEM_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAYHCB_BW_EMEM_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_FDCDRD_BW_EMEM_SHIFT                   _MK_SHIFT_CONST(16)
+#define MC_BWSHARE_EMEM_CTRL_0_0_FDCDRD_BW_EMEM_FIELD                   (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_FDCDRD_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_FDCDRD_BW_EMEM_RANGE                   16:16
+#define MC_BWSHARE_EMEM_CTRL_0_0_FDCDRD_BW_EMEM_WOFFSET                 0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_FDCDRD_BW_EMEM_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_FDCDRD_BW_EMEM_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_FDCDRD_BW_EMEM_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_FDCDRD_BW_EMEM_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_FDCDRD_BW_EMEM_INIT_ENUM                       DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_FDCDRD_BW_EMEM_DISABLE                 _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_FDCDRD_BW_EMEM_ENABLE                  _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_FDCDRD_BW_EMEM_DISABLED                        _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_FDCDRD_BW_EMEM_ENABLED                 _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2DR_BW_EMEM_SHIFT                     _MK_SHIFT_CONST(17)
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2DR_BW_EMEM_FIELD                     (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_G2DR_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2DR_BW_EMEM_RANGE                     17:17
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2DR_BW_EMEM_WOFFSET                   0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2DR_BW_EMEM_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2DR_BW_EMEM_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2DR_BW_EMEM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2DR_BW_EMEM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2DR_BW_EMEM_INIT_ENUM                 DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2DR_BW_EMEM_DISABLE                   _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2DR_BW_EMEM_ENABLE                    _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2DR_BW_EMEM_DISABLED                  _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2DR_BW_EMEM_ENABLED                   _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_HOST1XDMAR_BW_EMEM_SHIFT                       _MK_SHIFT_CONST(18)
+#define MC_BWSHARE_EMEM_CTRL_0_0_HOST1XDMAR_BW_EMEM_FIELD                       (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_HOST1XDMAR_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_HOST1XDMAR_BW_EMEM_RANGE                       18:18
+#define MC_BWSHARE_EMEM_CTRL_0_0_HOST1XDMAR_BW_EMEM_WOFFSET                     0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_HOST1XDMAR_BW_EMEM_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_HOST1XDMAR_BW_EMEM_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_HOST1XDMAR_BW_EMEM_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_HOST1XDMAR_BW_EMEM_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_HOST1XDMAR_BW_EMEM_INIT_ENUM                   DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_HOST1XDMAR_BW_EMEM_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_HOST1XDMAR_BW_EMEM_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_HOST1XDMAR_BW_EMEM_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_HOST1XDMAR_BW_EMEM_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_HOST1XR_BW_EMEM_SHIFT                  _MK_SHIFT_CONST(19)
+#define MC_BWSHARE_EMEM_CTRL_0_0_HOST1XR_BW_EMEM_FIELD                  (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_HOST1XR_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_HOST1XR_BW_EMEM_RANGE                  19:19
+#define MC_BWSHARE_EMEM_CTRL_0_0_HOST1XR_BW_EMEM_WOFFSET                        0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_HOST1XR_BW_EMEM_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_HOST1XR_BW_EMEM_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_HOST1XR_BW_EMEM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_HOST1XR_BW_EMEM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_HOST1XR_BW_EMEM_INIT_ENUM                      DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_HOST1XR_BW_EMEM_DISABLE                        _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_HOST1XR_BW_EMEM_ENABLE                 _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_HOST1XR_BW_EMEM_DISABLED                       _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_HOST1XR_BW_EMEM_ENABLED                        _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_IDXSRD_BW_EMEM_SHIFT                   _MK_SHIFT_CONST(20)
+#define MC_BWSHARE_EMEM_CTRL_0_0_IDXSRD_BW_EMEM_FIELD                   (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_IDXSRD_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_IDXSRD_BW_EMEM_RANGE                   20:20
+#define MC_BWSHARE_EMEM_CTRL_0_0_IDXSRD_BW_EMEM_WOFFSET                 0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_IDXSRD_BW_EMEM_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_IDXSRD_BW_EMEM_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_IDXSRD_BW_EMEM_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_IDXSRD_BW_EMEM_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_IDXSRD_BW_EMEM_INIT_ENUM                       DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_IDXSRD_BW_EMEM_DISABLE                 _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_IDXSRD_BW_EMEM_ENABLE                  _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_IDXSRD_BW_EMEM_DISABLED                        _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_IDXSRD_BW_EMEM_ENABLED                 _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPCORER_BW_EMEM_SHIFT                  _MK_SHIFT_CONST(21)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPCORER_BW_EMEM_FIELD                  (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_MPCORER_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPCORER_BW_EMEM_RANGE                  21:21
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPCORER_BW_EMEM_WOFFSET                        0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPCORER_BW_EMEM_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPCORER_BW_EMEM_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPCORER_BW_EMEM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPCORER_BW_EMEM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPCORER_BW_EMEM_INIT_ENUM                      DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPCORER_BW_EMEM_DISABLE                        _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPCORER_BW_EMEM_ENABLE                 _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPCORER_BW_EMEM_DISABLED                       _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPCORER_BW_EMEM_ENABLED                        _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPE_IPRED_BW_EMEM_SHIFT                        _MK_SHIFT_CONST(22)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPE_IPRED_BW_EMEM_FIELD                        (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_MPE_IPRED_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPE_IPRED_BW_EMEM_RANGE                        22:22
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPE_IPRED_BW_EMEM_WOFFSET                      0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPE_IPRED_BW_EMEM_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPE_IPRED_BW_EMEM_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPE_IPRED_BW_EMEM_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPE_IPRED_BW_EMEM_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPE_IPRED_BW_EMEM_INIT_ENUM                    DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPE_IPRED_BW_EMEM_DISABLE                      _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPE_IPRED_BW_EMEM_ENABLE                       _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPE_IPRED_BW_EMEM_DISABLED                     _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPE_IPRED_BW_EMEM_ENABLED                      _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPEAMEMRD_BW_EMEM_SHIFT                        _MK_SHIFT_CONST(23)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPEAMEMRD_BW_EMEM_FIELD                        (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_MPEAMEMRD_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPEAMEMRD_BW_EMEM_RANGE                        23:23
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPEAMEMRD_BW_EMEM_WOFFSET                      0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPEAMEMRD_BW_EMEM_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPEAMEMRD_BW_EMEM_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPEAMEMRD_BW_EMEM_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPEAMEMRD_BW_EMEM_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPEAMEMRD_BW_EMEM_INIT_ENUM                    DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPEAMEMRD_BW_EMEM_DISABLE                      _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPEAMEMRD_BW_EMEM_ENABLE                       _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPEAMEMRD_BW_EMEM_DISABLED                     _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPEAMEMRD_BW_EMEM_ENABLED                      _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPECSRD_BW_EMEM_SHIFT                  _MK_SHIFT_CONST(24)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPECSRD_BW_EMEM_FIELD                  (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_MPECSRD_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPECSRD_BW_EMEM_RANGE                  24:24
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPECSRD_BW_EMEM_WOFFSET                        0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPECSRD_BW_EMEM_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPECSRD_BW_EMEM_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPECSRD_BW_EMEM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPECSRD_BW_EMEM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPECSRD_BW_EMEM_INIT_ENUM                      DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPECSRD_BW_EMEM_DISABLE                        _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPECSRD_BW_EMEM_ENABLE                 _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPECSRD_BW_EMEM_DISABLED                       _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPECSRD_BW_EMEM_ENABLED                        _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSAHBDMAR_BW_EMEM_SHIFT                      _MK_SHIFT_CONST(25)
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSAHBDMAR_BW_EMEM_FIELD                      (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_PPCSAHBDMAR_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSAHBDMAR_BW_EMEM_RANGE                      25:25
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSAHBDMAR_BW_EMEM_WOFFSET                    0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSAHBDMAR_BW_EMEM_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSAHBDMAR_BW_EMEM_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSAHBDMAR_BW_EMEM_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSAHBDMAR_BW_EMEM_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSAHBDMAR_BW_EMEM_INIT_ENUM                  DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSAHBDMAR_BW_EMEM_DISABLE                    _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSAHBDMAR_BW_EMEM_ENABLE                     _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSAHBDMAR_BW_EMEM_DISABLED                   _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSAHBDMAR_BW_EMEM_ENABLED                    _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSAHBSLVR_BW_EMEM_SHIFT                      _MK_SHIFT_CONST(26)
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSAHBSLVR_BW_EMEM_FIELD                      (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_PPCSAHBSLVR_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSAHBSLVR_BW_EMEM_RANGE                      26:26
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSAHBSLVR_BW_EMEM_WOFFSET                    0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSAHBSLVR_BW_EMEM_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSAHBSLVR_BW_EMEM_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSAHBSLVR_BW_EMEM_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSAHBSLVR_BW_EMEM_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSAHBSLVR_BW_EMEM_INIT_ENUM                  DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSAHBSLVR_BW_EMEM_DISABLE                    _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSAHBSLVR_BW_EMEM_ENABLE                     _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSAHBSLVR_BW_EMEM_DISABLED                   _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSAHBSLVR_BW_EMEM_ENABLED                    _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSARM7R_BW_EMEM_SHIFT                        _MK_SHIFT_CONST(27)
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSARM7R_BW_EMEM_FIELD                        (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_PPCSARM7R_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSARM7R_BW_EMEM_RANGE                        27:27
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSARM7R_BW_EMEM_WOFFSET                      0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSARM7R_BW_EMEM_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSARM7R_BW_EMEM_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSARM7R_BW_EMEM_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSARM7R_BW_EMEM_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSARM7R_BW_EMEM_INIT_ENUM                    DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSARM7R_BW_EMEM_DISABLE                      _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSARM7R_BW_EMEM_ENABLE                       _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSARM7R_BW_EMEM_DISABLED                     _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSARM7R_BW_EMEM_ENABLED                      _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_TEXSRD_BW_EMEM_SHIFT                   _MK_SHIFT_CONST(28)
+#define MC_BWSHARE_EMEM_CTRL_0_0_TEXSRD_BW_EMEM_FIELD                   (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_TEXSRD_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_TEXSRD_BW_EMEM_RANGE                   28:28
+#define MC_BWSHARE_EMEM_CTRL_0_0_TEXSRD_BW_EMEM_WOFFSET                 0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_TEXSRD_BW_EMEM_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_TEXSRD_BW_EMEM_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_TEXSRD_BW_EMEM_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_TEXSRD_BW_EMEM_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_TEXSRD_BW_EMEM_INIT_ENUM                       DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_TEXSRD_BW_EMEM_DISABLE                 _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_TEXSRD_BW_EMEM_ENABLE                  _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_TEXSRD_BW_EMEM_DISABLED                        _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_TEXSRD_BW_EMEM_ENABLED                 _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEBSEAR_BW_EMEM_SHIFT                 _MK_SHIFT_CONST(29)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEBSEAR_BW_EMEM_FIELD                 (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_VDEBSEAR_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEBSEAR_BW_EMEM_RANGE                 29:29
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEBSEAR_BW_EMEM_WOFFSET                       0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEBSEAR_BW_EMEM_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEBSEAR_BW_EMEM_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEBSEAR_BW_EMEM_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEBSEAR_BW_EMEM_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEBSEAR_BW_EMEM_INIT_ENUM                     DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEBSEAR_BW_EMEM_DISABLE                       _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEBSEAR_BW_EMEM_ENABLE                        _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEBSEAR_BW_EMEM_DISABLED                      _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEBSEAR_BW_EMEM_ENABLED                       _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEBSEVR_BW_EMEM_SHIFT                 _MK_SHIFT_CONST(30)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEBSEVR_BW_EMEM_FIELD                 (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_VDEBSEVR_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEBSEVR_BW_EMEM_RANGE                 30:30
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEBSEVR_BW_EMEM_WOFFSET                       0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEBSEVR_BW_EMEM_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEBSEVR_BW_EMEM_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEBSEVR_BW_EMEM_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEBSEVR_BW_EMEM_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEBSEVR_BW_EMEM_INIT_ENUM                     DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEBSEVR_BW_EMEM_DISABLE                       _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEBSEVR_BW_EMEM_ENABLE                        _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEBSEVR_BW_EMEM_DISABLED                      _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEBSEVR_BW_EMEM_ENABLED                       _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEMBER_BW_EMEM_SHIFT                  _MK_SHIFT_CONST(31)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEMBER_BW_EMEM_FIELD                  (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_VDEMBER_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEMBER_BW_EMEM_RANGE                  31:31
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEMBER_BW_EMEM_WOFFSET                        0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEMBER_BW_EMEM_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEMBER_BW_EMEM_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEMBER_BW_EMEM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEMBER_BW_EMEM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEMBER_BW_EMEM_INIT_ENUM                      DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEMBER_BW_EMEM_DISABLE                        _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEMBER_BW_EMEM_ENABLE                 _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEMBER_BW_EMEM_DISABLED                       _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEMBER_BW_EMEM_ENABLED                        _MK_ENUM_CONST(1)
+
+
+// Register MC_BWSHARE_EMEM_CTRL_1_0  
+#define MC_BWSHARE_EMEM_CTRL_1_0                        _MK_ADDR_CONST(0x1a0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_WORD_COUNT                     0x1
+#define MC_BWSHARE_EMEM_CTRL_1_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_RESET_MASK                     _MK_MASK_CONST(0xffffff)
+#define MC_BWSHARE_EMEM_CTRL_1_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_READ_MASK                      _MK_MASK_CONST(0xffffff)
+#define MC_BWSHARE_EMEM_CTRL_1_0_WRITE_MASK                     _MK_MASK_CONST(0xffffff)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEMCER_BW_EMEM_SHIFT                  _MK_SHIFT_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEMCER_BW_EMEM_FIELD                  (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_1_0_VDEMCER_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEMCER_BW_EMEM_RANGE                  0:0
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEMCER_BW_EMEM_WOFFSET                        0x0
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEMCER_BW_EMEM_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEMCER_BW_EMEM_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEMCER_BW_EMEM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEMCER_BW_EMEM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEMCER_BW_EMEM_INIT_ENUM                      DISABLE
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEMCER_BW_EMEM_DISABLE                        _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEMCER_BW_EMEM_ENABLE                 _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEMCER_BW_EMEM_DISABLED                       _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEMCER_BW_EMEM_ENABLED                        _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDETPER_BW_EMEM_SHIFT                  _MK_SHIFT_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDETPER_BW_EMEM_FIELD                  (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_1_0_VDETPER_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDETPER_BW_EMEM_RANGE                  1:1
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDETPER_BW_EMEM_WOFFSET                        0x0
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDETPER_BW_EMEM_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDETPER_BW_EMEM_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDETPER_BW_EMEM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDETPER_BW_EMEM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDETPER_BW_EMEM_INIT_ENUM                      DISABLE
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDETPER_BW_EMEM_DISABLE                        _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDETPER_BW_EMEM_ENABLE                 _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDETPER_BW_EMEM_DISABLED                       _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDETPER_BW_EMEM_ENABLED                        _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPU_BW_EMEM_SHIFT                     _MK_SHIFT_CONST(2)
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPU_BW_EMEM_FIELD                     (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_1_0_EPPU_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPU_BW_EMEM_RANGE                     2:2
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPU_BW_EMEM_WOFFSET                   0x0
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPU_BW_EMEM_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPU_BW_EMEM_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPU_BW_EMEM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPU_BW_EMEM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPU_BW_EMEM_INIT_ENUM                 DISABLE
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPU_BW_EMEM_DISABLE                   _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPU_BW_EMEM_ENABLE                    _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPU_BW_EMEM_DISABLED                  _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPU_BW_EMEM_ENABLED                   _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPV_BW_EMEM_SHIFT                     _MK_SHIFT_CONST(3)
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPV_BW_EMEM_FIELD                     (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_1_0_EPPV_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPV_BW_EMEM_RANGE                     3:3
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPV_BW_EMEM_WOFFSET                   0x0
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPV_BW_EMEM_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPV_BW_EMEM_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPV_BW_EMEM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPV_BW_EMEM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPV_BW_EMEM_INIT_ENUM                 DISABLE
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPV_BW_EMEM_DISABLE                   _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPV_BW_EMEM_ENABLE                    _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPV_BW_EMEM_DISABLED                  _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPV_BW_EMEM_ENABLED                   _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPY_BW_EMEM_SHIFT                     _MK_SHIFT_CONST(4)
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPY_BW_EMEM_FIELD                     (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_1_0_EPPY_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPY_BW_EMEM_RANGE                     4:4
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPY_BW_EMEM_WOFFSET                   0x0
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPY_BW_EMEM_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPY_BW_EMEM_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPY_BW_EMEM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPY_BW_EMEM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPY_BW_EMEM_INIT_ENUM                 DISABLE
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPY_BW_EMEM_DISABLE                   _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPY_BW_EMEM_ENABLE                    _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPY_BW_EMEM_DISABLED                  _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPY_BW_EMEM_ENABLED                   _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPEUNIFBW_BW_EMEM_SHIFT                        _MK_SHIFT_CONST(5)
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPEUNIFBW_BW_EMEM_FIELD                        (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_1_0_MPEUNIFBW_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPEUNIFBW_BW_EMEM_RANGE                        5:5
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPEUNIFBW_BW_EMEM_WOFFSET                      0x0
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPEUNIFBW_BW_EMEM_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPEUNIFBW_BW_EMEM_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPEUNIFBW_BW_EMEM_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPEUNIFBW_BW_EMEM_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPEUNIFBW_BW_EMEM_INIT_ENUM                    DISABLE
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPEUNIFBW_BW_EMEM_DISABLE                      _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPEUNIFBW_BW_EMEM_ENABLE                       _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPEUNIFBW_BW_EMEM_DISABLED                     _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPEUNIFBW_BW_EMEM_ENABLED                      _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWSB_BW_EMEM_SHIFT                    _MK_SHIFT_CONST(6)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWSB_BW_EMEM_FIELD                    (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_1_0_VIWSB_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWSB_BW_EMEM_RANGE                    6:6
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWSB_BW_EMEM_WOFFSET                  0x0
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWSB_BW_EMEM_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWSB_BW_EMEM_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWSB_BW_EMEM_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWSB_BW_EMEM_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWSB_BW_EMEM_INIT_ENUM                        DISABLE
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWSB_BW_EMEM_DISABLE                  _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWSB_BW_EMEM_ENABLE                   _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWSB_BW_EMEM_DISABLED                 _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWSB_BW_EMEM_ENABLED                  _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWU_BW_EMEM_SHIFT                     _MK_SHIFT_CONST(7)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWU_BW_EMEM_FIELD                     (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_1_0_VIWU_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWU_BW_EMEM_RANGE                     7:7
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWU_BW_EMEM_WOFFSET                   0x0
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWU_BW_EMEM_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWU_BW_EMEM_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWU_BW_EMEM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWU_BW_EMEM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWU_BW_EMEM_INIT_ENUM                 DISABLE
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWU_BW_EMEM_DISABLE                   _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWU_BW_EMEM_ENABLE                    _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWU_BW_EMEM_DISABLED                  _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWU_BW_EMEM_ENABLED                   _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWV_BW_EMEM_SHIFT                     _MK_SHIFT_CONST(8)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWV_BW_EMEM_FIELD                     (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_1_0_VIWV_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWV_BW_EMEM_RANGE                     8:8
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWV_BW_EMEM_WOFFSET                   0x0
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWV_BW_EMEM_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWV_BW_EMEM_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWV_BW_EMEM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWV_BW_EMEM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWV_BW_EMEM_INIT_ENUM                 DISABLE
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWV_BW_EMEM_DISABLE                   _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWV_BW_EMEM_ENABLE                    _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWV_BW_EMEM_DISABLED                  _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWV_BW_EMEM_ENABLED                   _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWY_BW_EMEM_SHIFT                     _MK_SHIFT_CONST(9)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWY_BW_EMEM_FIELD                     (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_1_0_VIWY_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWY_BW_EMEM_RANGE                     9:9
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWY_BW_EMEM_WOFFSET                   0x0
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWY_BW_EMEM_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWY_BW_EMEM_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWY_BW_EMEM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWY_BW_EMEM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWY_BW_EMEM_INIT_ENUM                 DISABLE
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWY_BW_EMEM_DISABLE                   _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWY_BW_EMEM_ENABLE                    _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWY_BW_EMEM_DISABLED                  _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWY_BW_EMEM_ENABLED                   _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_1_0_G2DW_BW_EMEM_SHIFT                     _MK_SHIFT_CONST(10)
+#define MC_BWSHARE_EMEM_CTRL_1_0_G2DW_BW_EMEM_FIELD                     (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_1_0_G2DW_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_1_0_G2DW_BW_EMEM_RANGE                     10:10
+#define MC_BWSHARE_EMEM_CTRL_1_0_G2DW_BW_EMEM_WOFFSET                   0x0
+#define MC_BWSHARE_EMEM_CTRL_1_0_G2DW_BW_EMEM_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_G2DW_BW_EMEM_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_G2DW_BW_EMEM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_G2DW_BW_EMEM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_G2DW_BW_EMEM_INIT_ENUM                 DISABLE
+#define MC_BWSHARE_EMEM_CTRL_1_0_G2DW_BW_EMEM_DISABLE                   _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_G2DW_BW_EMEM_ENABLE                    _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_G2DW_BW_EMEM_DISABLED                  _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_G2DW_BW_EMEM_ENABLED                   _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_1_0_CMCW_BW_EMEM_SHIFT                     _MK_SHIFT_CONST(11)
+#define MC_BWSHARE_EMEM_CTRL_1_0_CMCW_BW_EMEM_FIELD                     (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_1_0_CMCW_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_1_0_CMCW_BW_EMEM_RANGE                     11:11
+#define MC_BWSHARE_EMEM_CTRL_1_0_CMCW_BW_EMEM_WOFFSET                   0x0
+#define MC_BWSHARE_EMEM_CTRL_1_0_CMCW_BW_EMEM_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_CMCW_BW_EMEM_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_CMCW_BW_EMEM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_CMCW_BW_EMEM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_CMCW_BW_EMEM_INIT_ENUM                 DISABLE
+#define MC_BWSHARE_EMEM_CTRL_1_0_CMCW_BW_EMEM_DISABLE                   _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_CMCW_BW_EMEM_ENABLE                    _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_CMCW_BW_EMEM_DISABLED                  _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_CMCW_BW_EMEM_ENABLED                   _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_1_0_FDCDWR_BW_EMEM_SHIFT                   _MK_SHIFT_CONST(12)
+#define MC_BWSHARE_EMEM_CTRL_1_0_FDCDWR_BW_EMEM_FIELD                   (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_1_0_FDCDWR_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_1_0_FDCDWR_BW_EMEM_RANGE                   12:12
+#define MC_BWSHARE_EMEM_CTRL_1_0_FDCDWR_BW_EMEM_WOFFSET                 0x0
+#define MC_BWSHARE_EMEM_CTRL_1_0_FDCDWR_BW_EMEM_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_FDCDWR_BW_EMEM_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_FDCDWR_BW_EMEM_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_FDCDWR_BW_EMEM_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_FDCDWR_BW_EMEM_INIT_ENUM                       DISABLE
+#define MC_BWSHARE_EMEM_CTRL_1_0_FDCDWR_BW_EMEM_DISABLE                 _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_FDCDWR_BW_EMEM_ENABLE                  _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_FDCDWR_BW_EMEM_DISABLED                        _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_FDCDWR_BW_EMEM_ENABLED                 _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_1_0_HOST1XW_BW_EMEM_SHIFT                  _MK_SHIFT_CONST(13)
+#define MC_BWSHARE_EMEM_CTRL_1_0_HOST1XW_BW_EMEM_FIELD                  (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_1_0_HOST1XW_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_1_0_HOST1XW_BW_EMEM_RANGE                  13:13
+#define MC_BWSHARE_EMEM_CTRL_1_0_HOST1XW_BW_EMEM_WOFFSET                        0x0
+#define MC_BWSHARE_EMEM_CTRL_1_0_HOST1XW_BW_EMEM_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_HOST1XW_BW_EMEM_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_HOST1XW_BW_EMEM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_HOST1XW_BW_EMEM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_HOST1XW_BW_EMEM_INIT_ENUM                      DISABLE
+#define MC_BWSHARE_EMEM_CTRL_1_0_HOST1XW_BW_EMEM_DISABLE                        _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_HOST1XW_BW_EMEM_ENABLE                 _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_HOST1XW_BW_EMEM_DISABLED                       _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_HOST1XW_BW_EMEM_ENABLED                        _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_1_0_ISPW_BW_EMEM_SHIFT                     _MK_SHIFT_CONST(14)
+#define MC_BWSHARE_EMEM_CTRL_1_0_ISPW_BW_EMEM_FIELD                     (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_1_0_ISPW_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_1_0_ISPW_BW_EMEM_RANGE                     14:14
+#define MC_BWSHARE_EMEM_CTRL_1_0_ISPW_BW_EMEM_WOFFSET                   0x0
+#define MC_BWSHARE_EMEM_CTRL_1_0_ISPW_BW_EMEM_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_ISPW_BW_EMEM_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_ISPW_BW_EMEM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_ISPW_BW_EMEM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_ISPW_BW_EMEM_INIT_ENUM                 DISABLE
+#define MC_BWSHARE_EMEM_CTRL_1_0_ISPW_BW_EMEM_DISABLE                   _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_ISPW_BW_EMEM_ENABLE                    _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_ISPW_BW_EMEM_DISABLED                  _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_ISPW_BW_EMEM_ENABLED                   _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPCOREW_BW_EMEM_SHIFT                  _MK_SHIFT_CONST(15)
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPCOREW_BW_EMEM_FIELD                  (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_1_0_MPCOREW_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPCOREW_BW_EMEM_RANGE                  15:15
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPCOREW_BW_EMEM_WOFFSET                        0x0
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPCOREW_BW_EMEM_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPCOREW_BW_EMEM_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPCOREW_BW_EMEM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPCOREW_BW_EMEM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPCOREW_BW_EMEM_INIT_ENUM                      DISABLE
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPCOREW_BW_EMEM_DISABLE                        _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPCOREW_BW_EMEM_ENABLE                 _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPCOREW_BW_EMEM_DISABLED                       _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPCOREW_BW_EMEM_ENABLED                        _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPECSWR_BW_EMEM_SHIFT                  _MK_SHIFT_CONST(16)
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPECSWR_BW_EMEM_FIELD                  (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_1_0_MPECSWR_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPECSWR_BW_EMEM_RANGE                  16:16
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPECSWR_BW_EMEM_WOFFSET                        0x0
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPECSWR_BW_EMEM_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPECSWR_BW_EMEM_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPECSWR_BW_EMEM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPECSWR_BW_EMEM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPECSWR_BW_EMEM_INIT_ENUM                      DISABLE
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPECSWR_BW_EMEM_DISABLE                        _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPECSWR_BW_EMEM_ENABLE                 _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPECSWR_BW_EMEM_DISABLED                       _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPECSWR_BW_EMEM_ENABLED                        _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSAHBDMAW_BW_EMEM_SHIFT                      _MK_SHIFT_CONST(17)
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSAHBDMAW_BW_EMEM_FIELD                      (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_1_0_PPCSAHBDMAW_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSAHBDMAW_BW_EMEM_RANGE                      17:17
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSAHBDMAW_BW_EMEM_WOFFSET                    0x0
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSAHBDMAW_BW_EMEM_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSAHBDMAW_BW_EMEM_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSAHBDMAW_BW_EMEM_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSAHBDMAW_BW_EMEM_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSAHBDMAW_BW_EMEM_INIT_ENUM                  DISABLE
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSAHBDMAW_BW_EMEM_DISABLE                    _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSAHBDMAW_BW_EMEM_ENABLE                     _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSAHBDMAW_BW_EMEM_DISABLED                   _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSAHBDMAW_BW_EMEM_ENABLED                    _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSAHBSLVW_BW_EMEM_SHIFT                      _MK_SHIFT_CONST(18)
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSAHBSLVW_BW_EMEM_FIELD                      (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_1_0_PPCSAHBSLVW_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSAHBSLVW_BW_EMEM_RANGE                      18:18
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSAHBSLVW_BW_EMEM_WOFFSET                    0x0
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSAHBSLVW_BW_EMEM_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSAHBSLVW_BW_EMEM_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSAHBSLVW_BW_EMEM_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSAHBSLVW_BW_EMEM_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSAHBSLVW_BW_EMEM_INIT_ENUM                  DISABLE
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSAHBSLVW_BW_EMEM_DISABLE                    _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSAHBSLVW_BW_EMEM_ENABLE                     _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSAHBSLVW_BW_EMEM_DISABLED                   _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSAHBSLVW_BW_EMEM_ENABLED                    _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSARM7W_BW_EMEM_SHIFT                        _MK_SHIFT_CONST(19)
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSARM7W_BW_EMEM_FIELD                        (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_1_0_PPCSARM7W_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSARM7W_BW_EMEM_RANGE                        19:19
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSARM7W_BW_EMEM_WOFFSET                      0x0
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSARM7W_BW_EMEM_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSARM7W_BW_EMEM_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSARM7W_BW_EMEM_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSARM7W_BW_EMEM_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSARM7W_BW_EMEM_INIT_ENUM                    DISABLE
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSARM7W_BW_EMEM_DISABLE                      _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSARM7W_BW_EMEM_ENABLE                       _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSARM7W_BW_EMEM_DISABLED                     _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSARM7W_BW_EMEM_ENABLED                      _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEBSEAW_BW_EMEM_SHIFT                 _MK_SHIFT_CONST(20)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEBSEAW_BW_EMEM_FIELD                 (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_1_0_VDEBSEAW_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEBSEAW_BW_EMEM_RANGE                 20:20
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEBSEAW_BW_EMEM_WOFFSET                       0x0
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEBSEAW_BW_EMEM_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEBSEAW_BW_EMEM_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEBSEAW_BW_EMEM_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEBSEAW_BW_EMEM_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEBSEAW_BW_EMEM_INIT_ENUM                     DISABLE
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEBSEAW_BW_EMEM_DISABLE                       _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEBSEAW_BW_EMEM_ENABLE                        _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEBSEAW_BW_EMEM_DISABLED                      _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEBSEAW_BW_EMEM_ENABLED                       _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEBSEVW_BW_EMEM_SHIFT                 _MK_SHIFT_CONST(21)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEBSEVW_BW_EMEM_FIELD                 (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_1_0_VDEBSEVW_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEBSEVW_BW_EMEM_RANGE                 21:21
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEBSEVW_BW_EMEM_WOFFSET                       0x0
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEBSEVW_BW_EMEM_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEBSEVW_BW_EMEM_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEBSEVW_BW_EMEM_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEBSEVW_BW_EMEM_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEBSEVW_BW_EMEM_INIT_ENUM                     DISABLE
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEBSEVW_BW_EMEM_DISABLE                       _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEBSEVW_BW_EMEM_ENABLE                        _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEBSEVW_BW_EMEM_DISABLED                      _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEBSEVW_BW_EMEM_ENABLED                       _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEMBEW_BW_EMEM_SHIFT                  _MK_SHIFT_CONST(22)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEMBEW_BW_EMEM_FIELD                  (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_1_0_VDEMBEW_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEMBEW_BW_EMEM_RANGE                  22:22
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEMBEW_BW_EMEM_WOFFSET                        0x0
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEMBEW_BW_EMEM_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEMBEW_BW_EMEM_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEMBEW_BW_EMEM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEMBEW_BW_EMEM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEMBEW_BW_EMEM_INIT_ENUM                      DISABLE
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEMBEW_BW_EMEM_DISABLE                        _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEMBEW_BW_EMEM_ENABLE                 _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEMBEW_BW_EMEM_DISABLED                       _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEMBEW_BW_EMEM_ENABLED                        _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDETPMW_BW_EMEM_SHIFT                  _MK_SHIFT_CONST(23)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDETPMW_BW_EMEM_FIELD                  (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_1_0_VDETPMW_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDETPMW_BW_EMEM_RANGE                  23:23
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDETPMW_BW_EMEM_WOFFSET                        0x0
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDETPMW_BW_EMEM_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDETPMW_BW_EMEM_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDETPMW_BW_EMEM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDETPMW_BW_EMEM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDETPMW_BW_EMEM_INIT_ENUM                      DISABLE
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDETPMW_BW_EMEM_DISABLE                        _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDETPMW_BW_EMEM_ENABLE                 _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDETPMW_BW_EMEM_DISABLED                       _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDETPMW_BW_EMEM_ENABLED                        _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_INCVAL_SIZE  11
+#define MC_BWSHARE_HIGHTH_SIZE  8
+#define MC_BWSHARE_MAXTH_SIZE   8
+#define MC_BWSHARE_ALWAYSINC_DISABLE    0
+#define MC_BWSHARE_ALWAYSINC_ENABLE     1
+#define MC_BWSHARE_TMSFACTORSEL_1       0
+#define MC_BWSHARE_TMSFACTORSEL_2       1
+
+// Register MC_BWSHARE_CMC_0  
+#define MC_BWSHARE_CMC_0                        _MK_ADDR_CONST(0x1a4)
+#define MC_BWSHARE_CMC_0_WORD_COUNT                     0x1
+#define MC_BWSHARE_CMC_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_CMC_0_RESET_MASK                     _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_CMC_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_CMC_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_CMC_0_READ_MASK                      _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_CMC_0_WRITE_MASK                     _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_CMC_0_CMC_BW_INCVAL_SHIFT                    _MK_SHIFT_CONST(0)
+#define MC_BWSHARE_CMC_0_CMC_BW_INCVAL_FIELD                    (_MK_MASK_CONST(0x7ff) << MC_BWSHARE_CMC_0_CMC_BW_INCVAL_SHIFT)
+#define MC_BWSHARE_CMC_0_CMC_BW_INCVAL_RANGE                    10:0
+#define MC_BWSHARE_CMC_0_CMC_BW_INCVAL_WOFFSET                  0x0
+#define MC_BWSHARE_CMC_0_CMC_BW_INCVAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_CMC_0_CMC_BW_INCVAL_DEFAULT_MASK                     _MK_MASK_CONST(0x7ff)
+#define MC_BWSHARE_CMC_0_CMC_BW_INCVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_CMC_0_CMC_BW_INCVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_CMC_0_CMC_BW_HIGHTH_SHIFT                    _MK_SHIFT_CONST(11)
+#define MC_BWSHARE_CMC_0_CMC_BW_HIGHTH_FIELD                    (_MK_MASK_CONST(0xff) << MC_BWSHARE_CMC_0_CMC_BW_HIGHTH_SHIFT)
+#define MC_BWSHARE_CMC_0_CMC_BW_HIGHTH_RANGE                    18:11
+#define MC_BWSHARE_CMC_0_CMC_BW_HIGHTH_WOFFSET                  0x0
+#define MC_BWSHARE_CMC_0_CMC_BW_HIGHTH_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_CMC_0_CMC_BW_HIGHTH_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_CMC_0_CMC_BW_HIGHTH_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_CMC_0_CMC_BW_HIGHTH_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_CMC_0_CMC_BW_MAXTH_SHIFT                     _MK_SHIFT_CONST(19)
+#define MC_BWSHARE_CMC_0_CMC_BW_MAXTH_FIELD                     (_MK_MASK_CONST(0xff) << MC_BWSHARE_CMC_0_CMC_BW_MAXTH_SHIFT)
+#define MC_BWSHARE_CMC_0_CMC_BW_MAXTH_RANGE                     26:19
+#define MC_BWSHARE_CMC_0_CMC_BW_MAXTH_WOFFSET                   0x0
+#define MC_BWSHARE_CMC_0_CMC_BW_MAXTH_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_CMC_0_CMC_BW_MAXTH_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_CMC_0_CMC_BW_MAXTH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_CMC_0_CMC_BW_MAXTH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_CMC_0_CMC_BW_ALWAYSINC_SHIFT                 _MK_SHIFT_CONST(27)
+#define MC_BWSHARE_CMC_0_CMC_BW_ALWAYSINC_FIELD                 (_MK_MASK_CONST(0x1) << MC_BWSHARE_CMC_0_CMC_BW_ALWAYSINC_SHIFT)
+#define MC_BWSHARE_CMC_0_CMC_BW_ALWAYSINC_RANGE                 27:27
+#define MC_BWSHARE_CMC_0_CMC_BW_ALWAYSINC_WOFFSET                       0x0
+#define MC_BWSHARE_CMC_0_CMC_BW_ALWAYSINC_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_CMC_0_CMC_BW_ALWAYSINC_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_CMC_0_CMC_BW_ALWAYSINC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_CMC_0_CMC_BW_ALWAYSINC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_CMC_0_CMC_BW_ALWAYSINC_INIT_ENUM                     DISABLE
+#define MC_BWSHARE_CMC_0_CMC_BW_ALWAYSINC_DISABLE                       _MK_ENUM_CONST(0)
+#define MC_BWSHARE_CMC_0_CMC_BW_ALWAYSINC_ENABLE                        _MK_ENUM_CONST(1)
+#define MC_BWSHARE_CMC_0_CMC_BW_ALWAYSINC_DISABLED                      _MK_ENUM_CONST(0)
+#define MC_BWSHARE_CMC_0_CMC_BW_ALWAYSINC_ENABLED                       _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_CMC_0_CMC_BW_TMSFACTORSEL_SHIFT                      _MK_SHIFT_CONST(28)
+#define MC_BWSHARE_CMC_0_CMC_BW_TMSFACTORSEL_FIELD                      (_MK_MASK_CONST(0x1) << MC_BWSHARE_CMC_0_CMC_BW_TMSFACTORSEL_SHIFT)
+#define MC_BWSHARE_CMC_0_CMC_BW_TMSFACTORSEL_RANGE                      28:28
+#define MC_BWSHARE_CMC_0_CMC_BW_TMSFACTORSEL_WOFFSET                    0x0
+#define MC_BWSHARE_CMC_0_CMC_BW_TMSFACTORSEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_CMC_0_CMC_BW_TMSFACTORSEL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_CMC_0_CMC_BW_TMSFACTORSEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_CMC_0_CMC_BW_TMSFACTORSEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_CMC_0_CMC_BW_TMSFACTORSEL_INIT_ENUM                  TM_SFACTOR1
+#define MC_BWSHARE_CMC_0_CMC_BW_TMSFACTORSEL_TM_SFACTOR1                        _MK_ENUM_CONST(0)
+#define MC_BWSHARE_CMC_0_CMC_BW_TMSFACTORSEL_TM_SFACTOR2                        _MK_ENUM_CONST(1)
+
+
+// Register MC_BWSHARE_DISPLAY_0  
+#define MC_BWSHARE_DISPLAY_0                    _MK_ADDR_CONST(0x1a8)
+#define MC_BWSHARE_DISPLAY_0_WORD_COUNT                         0x1
+#define MC_BWSHARE_DISPLAY_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_DISPLAY_0_RESET_MASK                         _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_DISPLAY_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_DISPLAY_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_DISPLAY_0_READ_MASK                  _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_DISPLAY_0_WRITE_MASK                         _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_DISPLAY_0_DISPLAY_BW_INCVAL_SHIFT                    _MK_SHIFT_CONST(0)
+#define MC_BWSHARE_DISPLAY_0_DISPLAY_BW_INCVAL_FIELD                    (_MK_MASK_CONST(0x7ff) << MC_BWSHARE_DISPLAY_0_DISPLAY_BW_INCVAL_SHIFT)
+#define MC_BWSHARE_DISPLAY_0_DISPLAY_BW_INCVAL_RANGE                    10:0
+#define MC_BWSHARE_DISPLAY_0_DISPLAY_BW_INCVAL_WOFFSET                  0x0
+#define MC_BWSHARE_DISPLAY_0_DISPLAY_BW_INCVAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_DISPLAY_0_DISPLAY_BW_INCVAL_DEFAULT_MASK                     _MK_MASK_CONST(0x7ff)
+#define MC_BWSHARE_DISPLAY_0_DISPLAY_BW_INCVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_DISPLAY_0_DISPLAY_BW_INCVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_DISPLAY_0_DISPLAY_BW_HIGHTH_SHIFT                    _MK_SHIFT_CONST(11)
+#define MC_BWSHARE_DISPLAY_0_DISPLAY_BW_HIGHTH_FIELD                    (_MK_MASK_CONST(0xff) << MC_BWSHARE_DISPLAY_0_DISPLAY_BW_HIGHTH_SHIFT)
+#define MC_BWSHARE_DISPLAY_0_DISPLAY_BW_HIGHTH_RANGE                    18:11
+#define MC_BWSHARE_DISPLAY_0_DISPLAY_BW_HIGHTH_WOFFSET                  0x0
+#define MC_BWSHARE_DISPLAY_0_DISPLAY_BW_HIGHTH_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_DISPLAY_0_DISPLAY_BW_HIGHTH_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_DISPLAY_0_DISPLAY_BW_HIGHTH_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_DISPLAY_0_DISPLAY_BW_HIGHTH_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_DISPLAY_0_DISPLAY_BW_MAXTH_SHIFT                     _MK_SHIFT_CONST(19)
+#define MC_BWSHARE_DISPLAY_0_DISPLAY_BW_MAXTH_FIELD                     (_MK_MASK_CONST(0xff) << MC_BWSHARE_DISPLAY_0_DISPLAY_BW_MAXTH_SHIFT)
+#define MC_BWSHARE_DISPLAY_0_DISPLAY_BW_MAXTH_RANGE                     26:19
+#define MC_BWSHARE_DISPLAY_0_DISPLAY_BW_MAXTH_WOFFSET                   0x0
+#define MC_BWSHARE_DISPLAY_0_DISPLAY_BW_MAXTH_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_DISPLAY_0_DISPLAY_BW_MAXTH_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_DISPLAY_0_DISPLAY_BW_MAXTH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_DISPLAY_0_DISPLAY_BW_MAXTH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_DISPLAY_0_DISPLAY_BW_ALWAYSINC_SHIFT                 _MK_SHIFT_CONST(27)
+#define MC_BWSHARE_DISPLAY_0_DISPLAY_BW_ALWAYSINC_FIELD                 (_MK_MASK_CONST(0x1) << MC_BWSHARE_DISPLAY_0_DISPLAY_BW_ALWAYSINC_SHIFT)
+#define MC_BWSHARE_DISPLAY_0_DISPLAY_BW_ALWAYSINC_RANGE                 27:27
+#define MC_BWSHARE_DISPLAY_0_DISPLAY_BW_ALWAYSINC_WOFFSET                       0x0
+#define MC_BWSHARE_DISPLAY_0_DISPLAY_BW_ALWAYSINC_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_DISPLAY_0_DISPLAY_BW_ALWAYSINC_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_DISPLAY_0_DISPLAY_BW_ALWAYSINC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_DISPLAY_0_DISPLAY_BW_ALWAYSINC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_DISPLAY_0_DISPLAY_BW_ALWAYSINC_INIT_ENUM                     DISABLE
+#define MC_BWSHARE_DISPLAY_0_DISPLAY_BW_ALWAYSINC_DISABLE                       _MK_ENUM_CONST(0)
+#define MC_BWSHARE_DISPLAY_0_DISPLAY_BW_ALWAYSINC_ENABLE                        _MK_ENUM_CONST(1)
+#define MC_BWSHARE_DISPLAY_0_DISPLAY_BW_ALWAYSINC_DISABLED                      _MK_ENUM_CONST(0)
+#define MC_BWSHARE_DISPLAY_0_DISPLAY_BW_ALWAYSINC_ENABLED                       _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_DISPLAY_0_DISPLAY_BW_TMSFACTORSEL_SHIFT                      _MK_SHIFT_CONST(28)
+#define MC_BWSHARE_DISPLAY_0_DISPLAY_BW_TMSFACTORSEL_FIELD                      (_MK_MASK_CONST(0x1) << MC_BWSHARE_DISPLAY_0_DISPLAY_BW_TMSFACTORSEL_SHIFT)
+#define MC_BWSHARE_DISPLAY_0_DISPLAY_BW_TMSFACTORSEL_RANGE                      28:28
+#define MC_BWSHARE_DISPLAY_0_DISPLAY_BW_TMSFACTORSEL_WOFFSET                    0x0
+#define MC_BWSHARE_DISPLAY_0_DISPLAY_BW_TMSFACTORSEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_DISPLAY_0_DISPLAY_BW_TMSFACTORSEL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_DISPLAY_0_DISPLAY_BW_TMSFACTORSEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_DISPLAY_0_DISPLAY_BW_TMSFACTORSEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_DISPLAY_0_DISPLAY_BW_TMSFACTORSEL_INIT_ENUM                  TM_SFACTOR1
+#define MC_BWSHARE_DISPLAY_0_DISPLAY_BW_TMSFACTORSEL_TM_SFACTOR1                        _MK_ENUM_CONST(0)
+#define MC_BWSHARE_DISPLAY_0_DISPLAY_BW_TMSFACTORSEL_TM_SFACTOR2                        _MK_ENUM_CONST(1)
+
+
+// Register MC_BWSHARE_DISPLAYB_0  
+#define MC_BWSHARE_DISPLAYB_0                   _MK_ADDR_CONST(0x1ac)
+#define MC_BWSHARE_DISPLAYB_0_WORD_COUNT                        0x1
+#define MC_BWSHARE_DISPLAYB_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_DISPLAYB_0_RESET_MASK                        _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_DISPLAYB_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_DISPLAYB_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_DISPLAYB_0_READ_MASK                         _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_DISPLAYB_0_WRITE_MASK                        _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_DISPLAYB_0_DISPLAYB_BW_INCVAL_SHIFT                  _MK_SHIFT_CONST(0)
+#define MC_BWSHARE_DISPLAYB_0_DISPLAYB_BW_INCVAL_FIELD                  (_MK_MASK_CONST(0x7ff) << MC_BWSHARE_DISPLAYB_0_DISPLAYB_BW_INCVAL_SHIFT)
+#define MC_BWSHARE_DISPLAYB_0_DISPLAYB_BW_INCVAL_RANGE                  10:0
+#define MC_BWSHARE_DISPLAYB_0_DISPLAYB_BW_INCVAL_WOFFSET                        0x0
+#define MC_BWSHARE_DISPLAYB_0_DISPLAYB_BW_INCVAL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_DISPLAYB_0_DISPLAYB_BW_INCVAL_DEFAULT_MASK                   _MK_MASK_CONST(0x7ff)
+#define MC_BWSHARE_DISPLAYB_0_DISPLAYB_BW_INCVAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_DISPLAYB_0_DISPLAYB_BW_INCVAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_DISPLAYB_0_DISPLAYB_BW_HIGHTH_SHIFT                  _MK_SHIFT_CONST(11)
+#define MC_BWSHARE_DISPLAYB_0_DISPLAYB_BW_HIGHTH_FIELD                  (_MK_MASK_CONST(0xff) << MC_BWSHARE_DISPLAYB_0_DISPLAYB_BW_HIGHTH_SHIFT)
+#define MC_BWSHARE_DISPLAYB_0_DISPLAYB_BW_HIGHTH_RANGE                  18:11
+#define MC_BWSHARE_DISPLAYB_0_DISPLAYB_BW_HIGHTH_WOFFSET                        0x0
+#define MC_BWSHARE_DISPLAYB_0_DISPLAYB_BW_HIGHTH_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_DISPLAYB_0_DISPLAYB_BW_HIGHTH_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_DISPLAYB_0_DISPLAYB_BW_HIGHTH_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_DISPLAYB_0_DISPLAYB_BW_HIGHTH_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_DISPLAYB_0_DISPLAYB_BW_MAXTH_SHIFT                   _MK_SHIFT_CONST(19)
+#define MC_BWSHARE_DISPLAYB_0_DISPLAYB_BW_MAXTH_FIELD                   (_MK_MASK_CONST(0xff) << MC_BWSHARE_DISPLAYB_0_DISPLAYB_BW_MAXTH_SHIFT)
+#define MC_BWSHARE_DISPLAYB_0_DISPLAYB_BW_MAXTH_RANGE                   26:19
+#define MC_BWSHARE_DISPLAYB_0_DISPLAYB_BW_MAXTH_WOFFSET                 0x0
+#define MC_BWSHARE_DISPLAYB_0_DISPLAYB_BW_MAXTH_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_DISPLAYB_0_DISPLAYB_BW_MAXTH_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_DISPLAYB_0_DISPLAYB_BW_MAXTH_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_DISPLAYB_0_DISPLAYB_BW_MAXTH_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_DISPLAYB_0_DISPLAYB_BW_ALWAYSINC_SHIFT                       _MK_SHIFT_CONST(27)
+#define MC_BWSHARE_DISPLAYB_0_DISPLAYB_BW_ALWAYSINC_FIELD                       (_MK_MASK_CONST(0x1) << MC_BWSHARE_DISPLAYB_0_DISPLAYB_BW_ALWAYSINC_SHIFT)
+#define MC_BWSHARE_DISPLAYB_0_DISPLAYB_BW_ALWAYSINC_RANGE                       27:27
+#define MC_BWSHARE_DISPLAYB_0_DISPLAYB_BW_ALWAYSINC_WOFFSET                     0x0
+#define MC_BWSHARE_DISPLAYB_0_DISPLAYB_BW_ALWAYSINC_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_DISPLAYB_0_DISPLAYB_BW_ALWAYSINC_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_DISPLAYB_0_DISPLAYB_BW_ALWAYSINC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_DISPLAYB_0_DISPLAYB_BW_ALWAYSINC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_DISPLAYB_0_DISPLAYB_BW_ALWAYSINC_INIT_ENUM                   DISABLE
+#define MC_BWSHARE_DISPLAYB_0_DISPLAYB_BW_ALWAYSINC_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_BWSHARE_DISPLAYB_0_DISPLAYB_BW_ALWAYSINC_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_BWSHARE_DISPLAYB_0_DISPLAYB_BW_ALWAYSINC_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_BWSHARE_DISPLAYB_0_DISPLAYB_BW_ALWAYSINC_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_DISPLAYB_0_DISPLAYB_BW_TMSFACTORSEL_SHIFT                    _MK_SHIFT_CONST(28)
+#define MC_BWSHARE_DISPLAYB_0_DISPLAYB_BW_TMSFACTORSEL_FIELD                    (_MK_MASK_CONST(0x1) << MC_BWSHARE_DISPLAYB_0_DISPLAYB_BW_TMSFACTORSEL_SHIFT)
+#define MC_BWSHARE_DISPLAYB_0_DISPLAYB_BW_TMSFACTORSEL_RANGE                    28:28
+#define MC_BWSHARE_DISPLAYB_0_DISPLAYB_BW_TMSFACTORSEL_WOFFSET                  0x0
+#define MC_BWSHARE_DISPLAYB_0_DISPLAYB_BW_TMSFACTORSEL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_DISPLAYB_0_DISPLAYB_BW_TMSFACTORSEL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_DISPLAYB_0_DISPLAYB_BW_TMSFACTORSEL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_DISPLAYB_0_DISPLAYB_BW_TMSFACTORSEL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_DISPLAYB_0_DISPLAYB_BW_TMSFACTORSEL_INIT_ENUM                        TM_SFACTOR1
+#define MC_BWSHARE_DISPLAYB_0_DISPLAYB_BW_TMSFACTORSEL_TM_SFACTOR1                      _MK_ENUM_CONST(0)
+#define MC_BWSHARE_DISPLAYB_0_DISPLAYB_BW_TMSFACTORSEL_TM_SFACTOR2                      _MK_ENUM_CONST(1)
+
+
+// Register MC_BWSHARE_EPP_0  
+#define MC_BWSHARE_EPP_0                        _MK_ADDR_CONST(0x1b0)
+#define MC_BWSHARE_EPP_0_WORD_COUNT                     0x1
+#define MC_BWSHARE_EPP_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EPP_0_RESET_MASK                     _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_EPP_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EPP_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EPP_0_READ_MASK                      _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_EPP_0_WRITE_MASK                     _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_EPP_0_EPP_BW_INCVAL_SHIFT                    _MK_SHIFT_CONST(0)
+#define MC_BWSHARE_EPP_0_EPP_BW_INCVAL_FIELD                    (_MK_MASK_CONST(0x7ff) << MC_BWSHARE_EPP_0_EPP_BW_INCVAL_SHIFT)
+#define MC_BWSHARE_EPP_0_EPP_BW_INCVAL_RANGE                    10:0
+#define MC_BWSHARE_EPP_0_EPP_BW_INCVAL_WOFFSET                  0x0
+#define MC_BWSHARE_EPP_0_EPP_BW_INCVAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EPP_0_EPP_BW_INCVAL_DEFAULT_MASK                     _MK_MASK_CONST(0x7ff)
+#define MC_BWSHARE_EPP_0_EPP_BW_INCVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EPP_0_EPP_BW_INCVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_EPP_0_EPP_BW_HIGHTH_SHIFT                    _MK_SHIFT_CONST(11)
+#define MC_BWSHARE_EPP_0_EPP_BW_HIGHTH_FIELD                    (_MK_MASK_CONST(0xff) << MC_BWSHARE_EPP_0_EPP_BW_HIGHTH_SHIFT)
+#define MC_BWSHARE_EPP_0_EPP_BW_HIGHTH_RANGE                    18:11
+#define MC_BWSHARE_EPP_0_EPP_BW_HIGHTH_WOFFSET                  0x0
+#define MC_BWSHARE_EPP_0_EPP_BW_HIGHTH_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EPP_0_EPP_BW_HIGHTH_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_EPP_0_EPP_BW_HIGHTH_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EPP_0_EPP_BW_HIGHTH_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_EPP_0_EPP_BW_MAXTH_SHIFT                     _MK_SHIFT_CONST(19)
+#define MC_BWSHARE_EPP_0_EPP_BW_MAXTH_FIELD                     (_MK_MASK_CONST(0xff) << MC_BWSHARE_EPP_0_EPP_BW_MAXTH_SHIFT)
+#define MC_BWSHARE_EPP_0_EPP_BW_MAXTH_RANGE                     26:19
+#define MC_BWSHARE_EPP_0_EPP_BW_MAXTH_WOFFSET                   0x0
+#define MC_BWSHARE_EPP_0_EPP_BW_MAXTH_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EPP_0_EPP_BW_MAXTH_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_EPP_0_EPP_BW_MAXTH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EPP_0_EPP_BW_MAXTH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_EPP_0_EPP_BW_ALWAYSINC_SHIFT                 _MK_SHIFT_CONST(27)
+#define MC_BWSHARE_EPP_0_EPP_BW_ALWAYSINC_FIELD                 (_MK_MASK_CONST(0x1) << MC_BWSHARE_EPP_0_EPP_BW_ALWAYSINC_SHIFT)
+#define MC_BWSHARE_EPP_0_EPP_BW_ALWAYSINC_RANGE                 27:27
+#define MC_BWSHARE_EPP_0_EPP_BW_ALWAYSINC_WOFFSET                       0x0
+#define MC_BWSHARE_EPP_0_EPP_BW_ALWAYSINC_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EPP_0_EPP_BW_ALWAYSINC_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EPP_0_EPP_BW_ALWAYSINC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EPP_0_EPP_BW_ALWAYSINC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EPP_0_EPP_BW_ALWAYSINC_INIT_ENUM                     DISABLE
+#define MC_BWSHARE_EPP_0_EPP_BW_ALWAYSINC_DISABLE                       _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EPP_0_EPP_BW_ALWAYSINC_ENABLE                        _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EPP_0_EPP_BW_ALWAYSINC_DISABLED                      _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EPP_0_EPP_BW_ALWAYSINC_ENABLED                       _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EPP_0_EPP_BW_TMSFACTORSEL_SHIFT                      _MK_SHIFT_CONST(28)
+#define MC_BWSHARE_EPP_0_EPP_BW_TMSFACTORSEL_FIELD                      (_MK_MASK_CONST(0x1) << MC_BWSHARE_EPP_0_EPP_BW_TMSFACTORSEL_SHIFT)
+#define MC_BWSHARE_EPP_0_EPP_BW_TMSFACTORSEL_RANGE                      28:28
+#define MC_BWSHARE_EPP_0_EPP_BW_TMSFACTORSEL_WOFFSET                    0x0
+#define MC_BWSHARE_EPP_0_EPP_BW_TMSFACTORSEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EPP_0_EPP_BW_TMSFACTORSEL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EPP_0_EPP_BW_TMSFACTORSEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EPP_0_EPP_BW_TMSFACTORSEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EPP_0_EPP_BW_TMSFACTORSEL_INIT_ENUM                  TM_SFACTOR1
+#define MC_BWSHARE_EPP_0_EPP_BW_TMSFACTORSEL_TM_SFACTOR1                        _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EPP_0_EPP_BW_TMSFACTORSEL_TM_SFACTOR2                        _MK_ENUM_CONST(1)
+
+
+// Register MC_BWSHARE_FDC_0  
+#define MC_BWSHARE_FDC_0                        _MK_ADDR_CONST(0x1b4)
+#define MC_BWSHARE_FDC_0_WORD_COUNT                     0x1
+#define MC_BWSHARE_FDC_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_FDC_0_RESET_MASK                     _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_FDC_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_FDC_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_FDC_0_READ_MASK                      _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_FDC_0_WRITE_MASK                     _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_FDC_0_FDC_BW_INCVAL_SHIFT                    _MK_SHIFT_CONST(0)
+#define MC_BWSHARE_FDC_0_FDC_BW_INCVAL_FIELD                    (_MK_MASK_CONST(0x7ff) << MC_BWSHARE_FDC_0_FDC_BW_INCVAL_SHIFT)
+#define MC_BWSHARE_FDC_0_FDC_BW_INCVAL_RANGE                    10:0
+#define MC_BWSHARE_FDC_0_FDC_BW_INCVAL_WOFFSET                  0x0
+#define MC_BWSHARE_FDC_0_FDC_BW_INCVAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_FDC_0_FDC_BW_INCVAL_DEFAULT_MASK                     _MK_MASK_CONST(0x7ff)
+#define MC_BWSHARE_FDC_0_FDC_BW_INCVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_FDC_0_FDC_BW_INCVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_FDC_0_FDC_BW_HIGHTH_SHIFT                    _MK_SHIFT_CONST(11)
+#define MC_BWSHARE_FDC_0_FDC_BW_HIGHTH_FIELD                    (_MK_MASK_CONST(0xff) << MC_BWSHARE_FDC_0_FDC_BW_HIGHTH_SHIFT)
+#define MC_BWSHARE_FDC_0_FDC_BW_HIGHTH_RANGE                    18:11
+#define MC_BWSHARE_FDC_0_FDC_BW_HIGHTH_WOFFSET                  0x0
+#define MC_BWSHARE_FDC_0_FDC_BW_HIGHTH_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_FDC_0_FDC_BW_HIGHTH_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_FDC_0_FDC_BW_HIGHTH_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_FDC_0_FDC_BW_HIGHTH_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_FDC_0_FDC_BW_MAXTH_SHIFT                     _MK_SHIFT_CONST(19)
+#define MC_BWSHARE_FDC_0_FDC_BW_MAXTH_FIELD                     (_MK_MASK_CONST(0xff) << MC_BWSHARE_FDC_0_FDC_BW_MAXTH_SHIFT)
+#define MC_BWSHARE_FDC_0_FDC_BW_MAXTH_RANGE                     26:19
+#define MC_BWSHARE_FDC_0_FDC_BW_MAXTH_WOFFSET                   0x0
+#define MC_BWSHARE_FDC_0_FDC_BW_MAXTH_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_FDC_0_FDC_BW_MAXTH_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_FDC_0_FDC_BW_MAXTH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_FDC_0_FDC_BW_MAXTH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_FDC_0_FDC_BW_ALWAYSINC_SHIFT                 _MK_SHIFT_CONST(27)
+#define MC_BWSHARE_FDC_0_FDC_BW_ALWAYSINC_FIELD                 (_MK_MASK_CONST(0x1) << MC_BWSHARE_FDC_0_FDC_BW_ALWAYSINC_SHIFT)
+#define MC_BWSHARE_FDC_0_FDC_BW_ALWAYSINC_RANGE                 27:27
+#define MC_BWSHARE_FDC_0_FDC_BW_ALWAYSINC_WOFFSET                       0x0
+#define MC_BWSHARE_FDC_0_FDC_BW_ALWAYSINC_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_FDC_0_FDC_BW_ALWAYSINC_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_FDC_0_FDC_BW_ALWAYSINC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_FDC_0_FDC_BW_ALWAYSINC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_FDC_0_FDC_BW_ALWAYSINC_INIT_ENUM                     DISABLE
+#define MC_BWSHARE_FDC_0_FDC_BW_ALWAYSINC_DISABLE                       _MK_ENUM_CONST(0)
+#define MC_BWSHARE_FDC_0_FDC_BW_ALWAYSINC_ENABLE                        _MK_ENUM_CONST(1)
+#define MC_BWSHARE_FDC_0_FDC_BW_ALWAYSINC_DISABLED                      _MK_ENUM_CONST(0)
+#define MC_BWSHARE_FDC_0_FDC_BW_ALWAYSINC_ENABLED                       _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_FDC_0_FDC_BW_TMSFACTORSEL_SHIFT                      _MK_SHIFT_CONST(28)
+#define MC_BWSHARE_FDC_0_FDC_BW_TMSFACTORSEL_FIELD                      (_MK_MASK_CONST(0x1) << MC_BWSHARE_FDC_0_FDC_BW_TMSFACTORSEL_SHIFT)
+#define MC_BWSHARE_FDC_0_FDC_BW_TMSFACTORSEL_RANGE                      28:28
+#define MC_BWSHARE_FDC_0_FDC_BW_TMSFACTORSEL_WOFFSET                    0x0
+#define MC_BWSHARE_FDC_0_FDC_BW_TMSFACTORSEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_FDC_0_FDC_BW_TMSFACTORSEL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_FDC_0_FDC_BW_TMSFACTORSEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_FDC_0_FDC_BW_TMSFACTORSEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_FDC_0_FDC_BW_TMSFACTORSEL_INIT_ENUM                  TM_SFACTOR1
+#define MC_BWSHARE_FDC_0_FDC_BW_TMSFACTORSEL_TM_SFACTOR1                        _MK_ENUM_CONST(0)
+#define MC_BWSHARE_FDC_0_FDC_BW_TMSFACTORSEL_TM_SFACTOR2                        _MK_ENUM_CONST(1)
+
+
+// Register MC_BWSHARE_GR2D_0  
+#define MC_BWSHARE_GR2D_0                       _MK_ADDR_CONST(0x1b8)
+#define MC_BWSHARE_GR2D_0_WORD_COUNT                    0x1
+#define MC_BWSHARE_GR2D_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_GR2D_0_RESET_MASK                    _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_GR2D_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_GR2D_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_GR2D_0_READ_MASK                     _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_GR2D_0_WRITE_MASK                    _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_GR2D_0_GR2D_BW_INCVAL_SHIFT                  _MK_SHIFT_CONST(0)
+#define MC_BWSHARE_GR2D_0_GR2D_BW_INCVAL_FIELD                  (_MK_MASK_CONST(0x7ff) << MC_BWSHARE_GR2D_0_GR2D_BW_INCVAL_SHIFT)
+#define MC_BWSHARE_GR2D_0_GR2D_BW_INCVAL_RANGE                  10:0
+#define MC_BWSHARE_GR2D_0_GR2D_BW_INCVAL_WOFFSET                        0x0
+#define MC_BWSHARE_GR2D_0_GR2D_BW_INCVAL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_GR2D_0_GR2D_BW_INCVAL_DEFAULT_MASK                   _MK_MASK_CONST(0x7ff)
+#define MC_BWSHARE_GR2D_0_GR2D_BW_INCVAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_GR2D_0_GR2D_BW_INCVAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_GR2D_0_GR2D_BW_HIGHTH_SHIFT                  _MK_SHIFT_CONST(11)
+#define MC_BWSHARE_GR2D_0_GR2D_BW_HIGHTH_FIELD                  (_MK_MASK_CONST(0xff) << MC_BWSHARE_GR2D_0_GR2D_BW_HIGHTH_SHIFT)
+#define MC_BWSHARE_GR2D_0_GR2D_BW_HIGHTH_RANGE                  18:11
+#define MC_BWSHARE_GR2D_0_GR2D_BW_HIGHTH_WOFFSET                        0x0
+#define MC_BWSHARE_GR2D_0_GR2D_BW_HIGHTH_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_GR2D_0_GR2D_BW_HIGHTH_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_GR2D_0_GR2D_BW_HIGHTH_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_GR2D_0_GR2D_BW_HIGHTH_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_GR2D_0_GR2D_BW_MAXTH_SHIFT                   _MK_SHIFT_CONST(19)
+#define MC_BWSHARE_GR2D_0_GR2D_BW_MAXTH_FIELD                   (_MK_MASK_CONST(0xff) << MC_BWSHARE_GR2D_0_GR2D_BW_MAXTH_SHIFT)
+#define MC_BWSHARE_GR2D_0_GR2D_BW_MAXTH_RANGE                   26:19
+#define MC_BWSHARE_GR2D_0_GR2D_BW_MAXTH_WOFFSET                 0x0
+#define MC_BWSHARE_GR2D_0_GR2D_BW_MAXTH_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_GR2D_0_GR2D_BW_MAXTH_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_GR2D_0_GR2D_BW_MAXTH_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_GR2D_0_GR2D_BW_MAXTH_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_GR2D_0_GR2D_BW_ALWAYSINC_SHIFT                       _MK_SHIFT_CONST(27)
+#define MC_BWSHARE_GR2D_0_GR2D_BW_ALWAYSINC_FIELD                       (_MK_MASK_CONST(0x1) << MC_BWSHARE_GR2D_0_GR2D_BW_ALWAYSINC_SHIFT)
+#define MC_BWSHARE_GR2D_0_GR2D_BW_ALWAYSINC_RANGE                       27:27
+#define MC_BWSHARE_GR2D_0_GR2D_BW_ALWAYSINC_WOFFSET                     0x0
+#define MC_BWSHARE_GR2D_0_GR2D_BW_ALWAYSINC_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_GR2D_0_GR2D_BW_ALWAYSINC_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_GR2D_0_GR2D_BW_ALWAYSINC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_GR2D_0_GR2D_BW_ALWAYSINC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_GR2D_0_GR2D_BW_ALWAYSINC_INIT_ENUM                   DISABLE
+#define MC_BWSHARE_GR2D_0_GR2D_BW_ALWAYSINC_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_BWSHARE_GR2D_0_GR2D_BW_ALWAYSINC_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_BWSHARE_GR2D_0_GR2D_BW_ALWAYSINC_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_BWSHARE_GR2D_0_GR2D_BW_ALWAYSINC_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_GR2D_0_GR2D_BW_TMSFACTORSEL_SHIFT                    _MK_SHIFT_CONST(28)
+#define MC_BWSHARE_GR2D_0_GR2D_BW_TMSFACTORSEL_FIELD                    (_MK_MASK_CONST(0x1) << MC_BWSHARE_GR2D_0_GR2D_BW_TMSFACTORSEL_SHIFT)
+#define MC_BWSHARE_GR2D_0_GR2D_BW_TMSFACTORSEL_RANGE                    28:28
+#define MC_BWSHARE_GR2D_0_GR2D_BW_TMSFACTORSEL_WOFFSET                  0x0
+#define MC_BWSHARE_GR2D_0_GR2D_BW_TMSFACTORSEL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_GR2D_0_GR2D_BW_TMSFACTORSEL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_GR2D_0_GR2D_BW_TMSFACTORSEL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_GR2D_0_GR2D_BW_TMSFACTORSEL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_GR2D_0_GR2D_BW_TMSFACTORSEL_INIT_ENUM                        TM_SFACTOR1
+#define MC_BWSHARE_GR2D_0_GR2D_BW_TMSFACTORSEL_TM_SFACTOR1                      _MK_ENUM_CONST(0)
+#define MC_BWSHARE_GR2D_0_GR2D_BW_TMSFACTORSEL_TM_SFACTOR2                      _MK_ENUM_CONST(1)
+
+
+// Register MC_BWSHARE_HOST1X_0  
+#define MC_BWSHARE_HOST1X_0                     _MK_ADDR_CONST(0x1bc)
+#define MC_BWSHARE_HOST1X_0_WORD_COUNT                  0x1
+#define MC_BWSHARE_HOST1X_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_HOST1X_0_RESET_MASK                  _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_HOST1X_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_HOST1X_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_HOST1X_0_READ_MASK                   _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_HOST1X_0_WRITE_MASK                  _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_HOST1X_0_HOST1X_BW_INCVAL_SHIFT                      _MK_SHIFT_CONST(0)
+#define MC_BWSHARE_HOST1X_0_HOST1X_BW_INCVAL_FIELD                      (_MK_MASK_CONST(0x7ff) << MC_BWSHARE_HOST1X_0_HOST1X_BW_INCVAL_SHIFT)
+#define MC_BWSHARE_HOST1X_0_HOST1X_BW_INCVAL_RANGE                      10:0
+#define MC_BWSHARE_HOST1X_0_HOST1X_BW_INCVAL_WOFFSET                    0x0
+#define MC_BWSHARE_HOST1X_0_HOST1X_BW_INCVAL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_HOST1X_0_HOST1X_BW_INCVAL_DEFAULT_MASK                       _MK_MASK_CONST(0x7ff)
+#define MC_BWSHARE_HOST1X_0_HOST1X_BW_INCVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_HOST1X_0_HOST1X_BW_INCVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_HOST1X_0_HOST1X_BW_HIGHTH_SHIFT                      _MK_SHIFT_CONST(11)
+#define MC_BWSHARE_HOST1X_0_HOST1X_BW_HIGHTH_FIELD                      (_MK_MASK_CONST(0xff) << MC_BWSHARE_HOST1X_0_HOST1X_BW_HIGHTH_SHIFT)
+#define MC_BWSHARE_HOST1X_0_HOST1X_BW_HIGHTH_RANGE                      18:11
+#define MC_BWSHARE_HOST1X_0_HOST1X_BW_HIGHTH_WOFFSET                    0x0
+#define MC_BWSHARE_HOST1X_0_HOST1X_BW_HIGHTH_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_HOST1X_0_HOST1X_BW_HIGHTH_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_HOST1X_0_HOST1X_BW_HIGHTH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_HOST1X_0_HOST1X_BW_HIGHTH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_HOST1X_0_HOST1X_BW_MAXTH_SHIFT                       _MK_SHIFT_CONST(19)
+#define MC_BWSHARE_HOST1X_0_HOST1X_BW_MAXTH_FIELD                       (_MK_MASK_CONST(0xff) << MC_BWSHARE_HOST1X_0_HOST1X_BW_MAXTH_SHIFT)
+#define MC_BWSHARE_HOST1X_0_HOST1X_BW_MAXTH_RANGE                       26:19
+#define MC_BWSHARE_HOST1X_0_HOST1X_BW_MAXTH_WOFFSET                     0x0
+#define MC_BWSHARE_HOST1X_0_HOST1X_BW_MAXTH_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_HOST1X_0_HOST1X_BW_MAXTH_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_HOST1X_0_HOST1X_BW_MAXTH_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_HOST1X_0_HOST1X_BW_MAXTH_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_HOST1X_0_HOST1X_BW_ALWAYSINC_SHIFT                   _MK_SHIFT_CONST(27)
+#define MC_BWSHARE_HOST1X_0_HOST1X_BW_ALWAYSINC_FIELD                   (_MK_MASK_CONST(0x1) << MC_BWSHARE_HOST1X_0_HOST1X_BW_ALWAYSINC_SHIFT)
+#define MC_BWSHARE_HOST1X_0_HOST1X_BW_ALWAYSINC_RANGE                   27:27
+#define MC_BWSHARE_HOST1X_0_HOST1X_BW_ALWAYSINC_WOFFSET                 0x0
+#define MC_BWSHARE_HOST1X_0_HOST1X_BW_ALWAYSINC_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_HOST1X_0_HOST1X_BW_ALWAYSINC_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_HOST1X_0_HOST1X_BW_ALWAYSINC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_HOST1X_0_HOST1X_BW_ALWAYSINC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_HOST1X_0_HOST1X_BW_ALWAYSINC_INIT_ENUM                       DISABLE
+#define MC_BWSHARE_HOST1X_0_HOST1X_BW_ALWAYSINC_DISABLE                 _MK_ENUM_CONST(0)
+#define MC_BWSHARE_HOST1X_0_HOST1X_BW_ALWAYSINC_ENABLE                  _MK_ENUM_CONST(1)
+#define MC_BWSHARE_HOST1X_0_HOST1X_BW_ALWAYSINC_DISABLED                        _MK_ENUM_CONST(0)
+#define MC_BWSHARE_HOST1X_0_HOST1X_BW_ALWAYSINC_ENABLED                 _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_HOST1X_0_HOST1X_BW_TMSFACTORSEL_SHIFT                        _MK_SHIFT_CONST(28)
+#define MC_BWSHARE_HOST1X_0_HOST1X_BW_TMSFACTORSEL_FIELD                        (_MK_MASK_CONST(0x1) << MC_BWSHARE_HOST1X_0_HOST1X_BW_TMSFACTORSEL_SHIFT)
+#define MC_BWSHARE_HOST1X_0_HOST1X_BW_TMSFACTORSEL_RANGE                        28:28
+#define MC_BWSHARE_HOST1X_0_HOST1X_BW_TMSFACTORSEL_WOFFSET                      0x0
+#define MC_BWSHARE_HOST1X_0_HOST1X_BW_TMSFACTORSEL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_HOST1X_0_HOST1X_BW_TMSFACTORSEL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_HOST1X_0_HOST1X_BW_TMSFACTORSEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_HOST1X_0_HOST1X_BW_TMSFACTORSEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_HOST1X_0_HOST1X_BW_TMSFACTORSEL_INIT_ENUM                    TM_SFACTOR1
+#define MC_BWSHARE_HOST1X_0_HOST1X_BW_TMSFACTORSEL_TM_SFACTOR1                  _MK_ENUM_CONST(0)
+#define MC_BWSHARE_HOST1X_0_HOST1X_BW_TMSFACTORSEL_TM_SFACTOR2                  _MK_ENUM_CONST(1)
+
+
+// Register MC_BWSHARE_IDX_0  
+#define MC_BWSHARE_IDX_0                        _MK_ADDR_CONST(0x1c0)
+#define MC_BWSHARE_IDX_0_WORD_COUNT                     0x1
+#define MC_BWSHARE_IDX_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_IDX_0_RESET_MASK                     _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_IDX_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_IDX_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_IDX_0_READ_MASK                      _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_IDX_0_WRITE_MASK                     _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_IDX_0_IDX_BW_INCVAL_SHIFT                    _MK_SHIFT_CONST(0)
+#define MC_BWSHARE_IDX_0_IDX_BW_INCVAL_FIELD                    (_MK_MASK_CONST(0x7ff) << MC_BWSHARE_IDX_0_IDX_BW_INCVAL_SHIFT)
+#define MC_BWSHARE_IDX_0_IDX_BW_INCVAL_RANGE                    10:0
+#define MC_BWSHARE_IDX_0_IDX_BW_INCVAL_WOFFSET                  0x0
+#define MC_BWSHARE_IDX_0_IDX_BW_INCVAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_IDX_0_IDX_BW_INCVAL_DEFAULT_MASK                     _MK_MASK_CONST(0x7ff)
+#define MC_BWSHARE_IDX_0_IDX_BW_INCVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_IDX_0_IDX_BW_INCVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_IDX_0_IDX_BW_HIGHTH_SHIFT                    _MK_SHIFT_CONST(11)
+#define MC_BWSHARE_IDX_0_IDX_BW_HIGHTH_FIELD                    (_MK_MASK_CONST(0xff) << MC_BWSHARE_IDX_0_IDX_BW_HIGHTH_SHIFT)
+#define MC_BWSHARE_IDX_0_IDX_BW_HIGHTH_RANGE                    18:11
+#define MC_BWSHARE_IDX_0_IDX_BW_HIGHTH_WOFFSET                  0x0
+#define MC_BWSHARE_IDX_0_IDX_BW_HIGHTH_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_IDX_0_IDX_BW_HIGHTH_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_IDX_0_IDX_BW_HIGHTH_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_IDX_0_IDX_BW_HIGHTH_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_IDX_0_IDX_BW_MAXTH_SHIFT                     _MK_SHIFT_CONST(19)
+#define MC_BWSHARE_IDX_0_IDX_BW_MAXTH_FIELD                     (_MK_MASK_CONST(0xff) << MC_BWSHARE_IDX_0_IDX_BW_MAXTH_SHIFT)
+#define MC_BWSHARE_IDX_0_IDX_BW_MAXTH_RANGE                     26:19
+#define MC_BWSHARE_IDX_0_IDX_BW_MAXTH_WOFFSET                   0x0
+#define MC_BWSHARE_IDX_0_IDX_BW_MAXTH_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_IDX_0_IDX_BW_MAXTH_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_IDX_0_IDX_BW_MAXTH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_IDX_0_IDX_BW_MAXTH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_IDX_0_IDX_BW_ALWAYSINC_SHIFT                 _MK_SHIFT_CONST(27)
+#define MC_BWSHARE_IDX_0_IDX_BW_ALWAYSINC_FIELD                 (_MK_MASK_CONST(0x1) << MC_BWSHARE_IDX_0_IDX_BW_ALWAYSINC_SHIFT)
+#define MC_BWSHARE_IDX_0_IDX_BW_ALWAYSINC_RANGE                 27:27
+#define MC_BWSHARE_IDX_0_IDX_BW_ALWAYSINC_WOFFSET                       0x0
+#define MC_BWSHARE_IDX_0_IDX_BW_ALWAYSINC_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_IDX_0_IDX_BW_ALWAYSINC_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_IDX_0_IDX_BW_ALWAYSINC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_IDX_0_IDX_BW_ALWAYSINC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_IDX_0_IDX_BW_ALWAYSINC_INIT_ENUM                     DISABLE
+#define MC_BWSHARE_IDX_0_IDX_BW_ALWAYSINC_DISABLE                       _MK_ENUM_CONST(0)
+#define MC_BWSHARE_IDX_0_IDX_BW_ALWAYSINC_ENABLE                        _MK_ENUM_CONST(1)
+#define MC_BWSHARE_IDX_0_IDX_BW_ALWAYSINC_DISABLED                      _MK_ENUM_CONST(0)
+#define MC_BWSHARE_IDX_0_IDX_BW_ALWAYSINC_ENABLED                       _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_IDX_0_IDX_BW_TMSFACTORSEL_SHIFT                      _MK_SHIFT_CONST(28)
+#define MC_BWSHARE_IDX_0_IDX_BW_TMSFACTORSEL_FIELD                      (_MK_MASK_CONST(0x1) << MC_BWSHARE_IDX_0_IDX_BW_TMSFACTORSEL_SHIFT)
+#define MC_BWSHARE_IDX_0_IDX_BW_TMSFACTORSEL_RANGE                      28:28
+#define MC_BWSHARE_IDX_0_IDX_BW_TMSFACTORSEL_WOFFSET                    0x0
+#define MC_BWSHARE_IDX_0_IDX_BW_TMSFACTORSEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_IDX_0_IDX_BW_TMSFACTORSEL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_IDX_0_IDX_BW_TMSFACTORSEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_IDX_0_IDX_BW_TMSFACTORSEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_IDX_0_IDX_BW_TMSFACTORSEL_INIT_ENUM                  TM_SFACTOR1
+#define MC_BWSHARE_IDX_0_IDX_BW_TMSFACTORSEL_TM_SFACTOR1                        _MK_ENUM_CONST(0)
+#define MC_BWSHARE_IDX_0_IDX_BW_TMSFACTORSEL_TM_SFACTOR2                        _MK_ENUM_CONST(1)
+
+
+// Register MC_BWSHARE_ISP_0  
+#define MC_BWSHARE_ISP_0                        _MK_ADDR_CONST(0x1c4)
+#define MC_BWSHARE_ISP_0_WORD_COUNT                     0x1
+#define MC_BWSHARE_ISP_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_ISP_0_RESET_MASK                     _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_ISP_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_ISP_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_ISP_0_READ_MASK                      _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_ISP_0_WRITE_MASK                     _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_ISP_0_ISP_BW_INCVAL_SHIFT                    _MK_SHIFT_CONST(0)
+#define MC_BWSHARE_ISP_0_ISP_BW_INCVAL_FIELD                    (_MK_MASK_CONST(0x7ff) << MC_BWSHARE_ISP_0_ISP_BW_INCVAL_SHIFT)
+#define MC_BWSHARE_ISP_0_ISP_BW_INCVAL_RANGE                    10:0
+#define MC_BWSHARE_ISP_0_ISP_BW_INCVAL_WOFFSET                  0x0
+#define MC_BWSHARE_ISP_0_ISP_BW_INCVAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_ISP_0_ISP_BW_INCVAL_DEFAULT_MASK                     _MK_MASK_CONST(0x7ff)
+#define MC_BWSHARE_ISP_0_ISP_BW_INCVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_ISP_0_ISP_BW_INCVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_ISP_0_ISP_BW_HIGHTH_SHIFT                    _MK_SHIFT_CONST(11)
+#define MC_BWSHARE_ISP_0_ISP_BW_HIGHTH_FIELD                    (_MK_MASK_CONST(0xff) << MC_BWSHARE_ISP_0_ISP_BW_HIGHTH_SHIFT)
+#define MC_BWSHARE_ISP_0_ISP_BW_HIGHTH_RANGE                    18:11
+#define MC_BWSHARE_ISP_0_ISP_BW_HIGHTH_WOFFSET                  0x0
+#define MC_BWSHARE_ISP_0_ISP_BW_HIGHTH_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_ISP_0_ISP_BW_HIGHTH_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_ISP_0_ISP_BW_HIGHTH_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_ISP_0_ISP_BW_HIGHTH_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_ISP_0_ISP_BW_MAXTH_SHIFT                     _MK_SHIFT_CONST(19)
+#define MC_BWSHARE_ISP_0_ISP_BW_MAXTH_FIELD                     (_MK_MASK_CONST(0xff) << MC_BWSHARE_ISP_0_ISP_BW_MAXTH_SHIFT)
+#define MC_BWSHARE_ISP_0_ISP_BW_MAXTH_RANGE                     26:19
+#define MC_BWSHARE_ISP_0_ISP_BW_MAXTH_WOFFSET                   0x0
+#define MC_BWSHARE_ISP_0_ISP_BW_MAXTH_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_ISP_0_ISP_BW_MAXTH_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_ISP_0_ISP_BW_MAXTH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_ISP_0_ISP_BW_MAXTH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_ISP_0_ISP_BW_ALWAYSINC_SHIFT                 _MK_SHIFT_CONST(27)
+#define MC_BWSHARE_ISP_0_ISP_BW_ALWAYSINC_FIELD                 (_MK_MASK_CONST(0x1) << MC_BWSHARE_ISP_0_ISP_BW_ALWAYSINC_SHIFT)
+#define MC_BWSHARE_ISP_0_ISP_BW_ALWAYSINC_RANGE                 27:27
+#define MC_BWSHARE_ISP_0_ISP_BW_ALWAYSINC_WOFFSET                       0x0
+#define MC_BWSHARE_ISP_0_ISP_BW_ALWAYSINC_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_ISP_0_ISP_BW_ALWAYSINC_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_ISP_0_ISP_BW_ALWAYSINC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_ISP_0_ISP_BW_ALWAYSINC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_ISP_0_ISP_BW_ALWAYSINC_INIT_ENUM                     DISABLE
+#define MC_BWSHARE_ISP_0_ISP_BW_ALWAYSINC_DISABLE                       _MK_ENUM_CONST(0)
+#define MC_BWSHARE_ISP_0_ISP_BW_ALWAYSINC_ENABLE                        _MK_ENUM_CONST(1)
+#define MC_BWSHARE_ISP_0_ISP_BW_ALWAYSINC_DISABLED                      _MK_ENUM_CONST(0)
+#define MC_BWSHARE_ISP_0_ISP_BW_ALWAYSINC_ENABLED                       _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_ISP_0_ISP_BW_TMSFACTORSEL_SHIFT                      _MK_SHIFT_CONST(28)
+#define MC_BWSHARE_ISP_0_ISP_BW_TMSFACTORSEL_FIELD                      (_MK_MASK_CONST(0x1) << MC_BWSHARE_ISP_0_ISP_BW_TMSFACTORSEL_SHIFT)
+#define MC_BWSHARE_ISP_0_ISP_BW_TMSFACTORSEL_RANGE                      28:28
+#define MC_BWSHARE_ISP_0_ISP_BW_TMSFACTORSEL_WOFFSET                    0x0
+#define MC_BWSHARE_ISP_0_ISP_BW_TMSFACTORSEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_ISP_0_ISP_BW_TMSFACTORSEL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_ISP_0_ISP_BW_TMSFACTORSEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_ISP_0_ISP_BW_TMSFACTORSEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_ISP_0_ISP_BW_TMSFACTORSEL_INIT_ENUM                  TM_SFACTOR1
+#define MC_BWSHARE_ISP_0_ISP_BW_TMSFACTORSEL_TM_SFACTOR1                        _MK_ENUM_CONST(0)
+#define MC_BWSHARE_ISP_0_ISP_BW_TMSFACTORSEL_TM_SFACTOR2                        _MK_ENUM_CONST(1)
+
+
+// Register MC_BWSHARE_MPCORE_0  
+#define MC_BWSHARE_MPCORE_0                     _MK_ADDR_CONST(0x1c8)
+#define MC_BWSHARE_MPCORE_0_WORD_COUNT                  0x1
+#define MC_BWSHARE_MPCORE_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPCORE_0_RESET_MASK                  _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_MPCORE_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPCORE_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPCORE_0_READ_MASK                   _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_MPCORE_0_WRITE_MASK                  _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_INCVAL_SHIFT                      _MK_SHIFT_CONST(0)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_INCVAL_FIELD                      (_MK_MASK_CONST(0x7ff) << MC_BWSHARE_MPCORE_0_MPCORE_BW_INCVAL_SHIFT)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_INCVAL_RANGE                      10:0
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_INCVAL_WOFFSET                    0x0
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_INCVAL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_INCVAL_DEFAULT_MASK                       _MK_MASK_CONST(0x7ff)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_INCVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_INCVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_HIGHTH_SHIFT                      _MK_SHIFT_CONST(11)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_HIGHTH_FIELD                      (_MK_MASK_CONST(0xff) << MC_BWSHARE_MPCORE_0_MPCORE_BW_HIGHTH_SHIFT)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_HIGHTH_RANGE                      18:11
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_HIGHTH_WOFFSET                    0x0
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_HIGHTH_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_HIGHTH_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_HIGHTH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_HIGHTH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_MAXTH_SHIFT                       _MK_SHIFT_CONST(19)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_MAXTH_FIELD                       (_MK_MASK_CONST(0xff) << MC_BWSHARE_MPCORE_0_MPCORE_BW_MAXTH_SHIFT)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_MAXTH_RANGE                       26:19
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_MAXTH_WOFFSET                     0x0
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_MAXTH_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_MAXTH_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_MAXTH_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_MAXTH_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_ALWAYSINC_SHIFT                   _MK_SHIFT_CONST(27)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_ALWAYSINC_FIELD                   (_MK_MASK_CONST(0x1) << MC_BWSHARE_MPCORE_0_MPCORE_BW_ALWAYSINC_SHIFT)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_ALWAYSINC_RANGE                   27:27
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_ALWAYSINC_WOFFSET                 0x0
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_ALWAYSINC_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_ALWAYSINC_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_ALWAYSINC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_ALWAYSINC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_ALWAYSINC_INIT_ENUM                       DISABLE
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_ALWAYSINC_DISABLE                 _MK_ENUM_CONST(0)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_ALWAYSINC_ENABLE                  _MK_ENUM_CONST(1)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_ALWAYSINC_DISABLED                        _MK_ENUM_CONST(0)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_ALWAYSINC_ENABLED                 _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_TMSFACTORSEL_SHIFT                        _MK_SHIFT_CONST(28)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_TMSFACTORSEL_FIELD                        (_MK_MASK_CONST(0x1) << MC_BWSHARE_MPCORE_0_MPCORE_BW_TMSFACTORSEL_SHIFT)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_TMSFACTORSEL_RANGE                        28:28
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_TMSFACTORSEL_WOFFSET                      0x0
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_TMSFACTORSEL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_TMSFACTORSEL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_TMSFACTORSEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_TMSFACTORSEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_TMSFACTORSEL_INIT_ENUM                    TM_SFACTOR1
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_TMSFACTORSEL_TM_SFACTOR1                  _MK_ENUM_CONST(0)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_TMSFACTORSEL_TM_SFACTOR2                  _MK_ENUM_CONST(1)
+
+
+// Register MC_BWSHARE_MPEA_0  
+#define MC_BWSHARE_MPEA_0                       _MK_ADDR_CONST(0x1cc)
+#define MC_BWSHARE_MPEA_0_WORD_COUNT                    0x1
+#define MC_BWSHARE_MPEA_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEA_0_RESET_MASK                    _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_MPEA_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEA_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEA_0_READ_MASK                     _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_MPEA_0_WRITE_MASK                    _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_INCVAL_SHIFT                  _MK_SHIFT_CONST(0)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_INCVAL_FIELD                  (_MK_MASK_CONST(0x7ff) << MC_BWSHARE_MPEA_0_MPEA_BW_INCVAL_SHIFT)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_INCVAL_RANGE                  10:0
+#define MC_BWSHARE_MPEA_0_MPEA_BW_INCVAL_WOFFSET                        0x0
+#define MC_BWSHARE_MPEA_0_MPEA_BW_INCVAL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_INCVAL_DEFAULT_MASK                   _MK_MASK_CONST(0x7ff)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_INCVAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_INCVAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_MPEA_0_MPEA_BW_HIGHTH_SHIFT                  _MK_SHIFT_CONST(11)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_HIGHTH_FIELD                  (_MK_MASK_CONST(0xff) << MC_BWSHARE_MPEA_0_MPEA_BW_HIGHTH_SHIFT)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_HIGHTH_RANGE                  18:11
+#define MC_BWSHARE_MPEA_0_MPEA_BW_HIGHTH_WOFFSET                        0x0
+#define MC_BWSHARE_MPEA_0_MPEA_BW_HIGHTH_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_HIGHTH_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_HIGHTH_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_HIGHTH_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_MPEA_0_MPEA_BW_MAXTH_SHIFT                   _MK_SHIFT_CONST(19)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_MAXTH_FIELD                   (_MK_MASK_CONST(0xff) << MC_BWSHARE_MPEA_0_MPEA_BW_MAXTH_SHIFT)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_MAXTH_RANGE                   26:19
+#define MC_BWSHARE_MPEA_0_MPEA_BW_MAXTH_WOFFSET                 0x0
+#define MC_BWSHARE_MPEA_0_MPEA_BW_MAXTH_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_MAXTH_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_MAXTH_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_MAXTH_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_MPEA_0_MPEA_BW_ALWAYSINC_SHIFT                       _MK_SHIFT_CONST(27)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_ALWAYSINC_FIELD                       (_MK_MASK_CONST(0x1) << MC_BWSHARE_MPEA_0_MPEA_BW_ALWAYSINC_SHIFT)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_ALWAYSINC_RANGE                       27:27
+#define MC_BWSHARE_MPEA_0_MPEA_BW_ALWAYSINC_WOFFSET                     0x0
+#define MC_BWSHARE_MPEA_0_MPEA_BW_ALWAYSINC_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_ALWAYSINC_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_ALWAYSINC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_ALWAYSINC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_ALWAYSINC_INIT_ENUM                   DISABLE
+#define MC_BWSHARE_MPEA_0_MPEA_BW_ALWAYSINC_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_ALWAYSINC_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_ALWAYSINC_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_ALWAYSINC_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_MPEA_0_MPEA_BW_TMSFACTORSEL_SHIFT                    _MK_SHIFT_CONST(28)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_TMSFACTORSEL_FIELD                    (_MK_MASK_CONST(0x1) << MC_BWSHARE_MPEA_0_MPEA_BW_TMSFACTORSEL_SHIFT)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_TMSFACTORSEL_RANGE                    28:28
+#define MC_BWSHARE_MPEA_0_MPEA_BW_TMSFACTORSEL_WOFFSET                  0x0
+#define MC_BWSHARE_MPEA_0_MPEA_BW_TMSFACTORSEL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_TMSFACTORSEL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_TMSFACTORSEL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_TMSFACTORSEL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_TMSFACTORSEL_INIT_ENUM                        TM_SFACTOR1
+#define MC_BWSHARE_MPEA_0_MPEA_BW_TMSFACTORSEL_TM_SFACTOR1                      _MK_ENUM_CONST(0)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_TMSFACTORSEL_TM_SFACTOR2                      _MK_ENUM_CONST(1)
+
+
+// Register MC_BWSHARE_MPEB_0  
+#define MC_BWSHARE_MPEB_0                       _MK_ADDR_CONST(0x1d0)
+#define MC_BWSHARE_MPEB_0_WORD_COUNT                    0x1
+#define MC_BWSHARE_MPEB_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEB_0_RESET_MASK                    _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_MPEB_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEB_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEB_0_READ_MASK                     _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_MPEB_0_WRITE_MASK                    _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_INCVAL_SHIFT                  _MK_SHIFT_CONST(0)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_INCVAL_FIELD                  (_MK_MASK_CONST(0x7ff) << MC_BWSHARE_MPEB_0_MPEB_BW_INCVAL_SHIFT)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_INCVAL_RANGE                  10:0
+#define MC_BWSHARE_MPEB_0_MPEB_BW_INCVAL_WOFFSET                        0x0
+#define MC_BWSHARE_MPEB_0_MPEB_BW_INCVAL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_INCVAL_DEFAULT_MASK                   _MK_MASK_CONST(0x7ff)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_INCVAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_INCVAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_MPEB_0_MPEB_BW_HIGHTH_SHIFT                  _MK_SHIFT_CONST(11)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_HIGHTH_FIELD                  (_MK_MASK_CONST(0xff) << MC_BWSHARE_MPEB_0_MPEB_BW_HIGHTH_SHIFT)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_HIGHTH_RANGE                  18:11
+#define MC_BWSHARE_MPEB_0_MPEB_BW_HIGHTH_WOFFSET                        0x0
+#define MC_BWSHARE_MPEB_0_MPEB_BW_HIGHTH_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_HIGHTH_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_HIGHTH_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_HIGHTH_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_MPEB_0_MPEB_BW_MAXTH_SHIFT                   _MK_SHIFT_CONST(19)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_MAXTH_FIELD                   (_MK_MASK_CONST(0xff) << MC_BWSHARE_MPEB_0_MPEB_BW_MAXTH_SHIFT)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_MAXTH_RANGE                   26:19
+#define MC_BWSHARE_MPEB_0_MPEB_BW_MAXTH_WOFFSET                 0x0
+#define MC_BWSHARE_MPEB_0_MPEB_BW_MAXTH_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_MAXTH_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_MAXTH_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_MAXTH_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_MPEB_0_MPEB_BW_ALWAYSINC_SHIFT                       _MK_SHIFT_CONST(27)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_ALWAYSINC_FIELD                       (_MK_MASK_CONST(0x1) << MC_BWSHARE_MPEB_0_MPEB_BW_ALWAYSINC_SHIFT)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_ALWAYSINC_RANGE                       27:27
+#define MC_BWSHARE_MPEB_0_MPEB_BW_ALWAYSINC_WOFFSET                     0x0
+#define MC_BWSHARE_MPEB_0_MPEB_BW_ALWAYSINC_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_ALWAYSINC_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_ALWAYSINC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_ALWAYSINC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_ALWAYSINC_INIT_ENUM                   DISABLE
+#define MC_BWSHARE_MPEB_0_MPEB_BW_ALWAYSINC_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_ALWAYSINC_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_ALWAYSINC_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_ALWAYSINC_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_MPEB_0_MPEB_BW_TMSFACTORSEL_SHIFT                    _MK_SHIFT_CONST(28)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_TMSFACTORSEL_FIELD                    (_MK_MASK_CONST(0x1) << MC_BWSHARE_MPEB_0_MPEB_BW_TMSFACTORSEL_SHIFT)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_TMSFACTORSEL_RANGE                    28:28
+#define MC_BWSHARE_MPEB_0_MPEB_BW_TMSFACTORSEL_WOFFSET                  0x0
+#define MC_BWSHARE_MPEB_0_MPEB_BW_TMSFACTORSEL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_TMSFACTORSEL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_TMSFACTORSEL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_TMSFACTORSEL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_TMSFACTORSEL_INIT_ENUM                        TM_SFACTOR1
+#define MC_BWSHARE_MPEB_0_MPEB_BW_TMSFACTORSEL_TM_SFACTOR1                      _MK_ENUM_CONST(0)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_TMSFACTORSEL_TM_SFACTOR2                      _MK_ENUM_CONST(1)
+
+
+// Register MC_BWSHARE_MPEC_0  
+#define MC_BWSHARE_MPEC_0                       _MK_ADDR_CONST(0x1d4)
+#define MC_BWSHARE_MPEC_0_WORD_COUNT                    0x1
+#define MC_BWSHARE_MPEC_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEC_0_RESET_MASK                    _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_MPEC_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEC_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEC_0_READ_MASK                     _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_MPEC_0_WRITE_MASK                    _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_INCVAL_SHIFT                  _MK_SHIFT_CONST(0)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_INCVAL_FIELD                  (_MK_MASK_CONST(0x7ff) << MC_BWSHARE_MPEC_0_MPEC_BW_INCVAL_SHIFT)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_INCVAL_RANGE                  10:0
+#define MC_BWSHARE_MPEC_0_MPEC_BW_INCVAL_WOFFSET                        0x0
+#define MC_BWSHARE_MPEC_0_MPEC_BW_INCVAL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_INCVAL_DEFAULT_MASK                   _MK_MASK_CONST(0x7ff)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_INCVAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_INCVAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_MPEC_0_MPEC_BW_HIGHTH_SHIFT                  _MK_SHIFT_CONST(11)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_HIGHTH_FIELD                  (_MK_MASK_CONST(0xff) << MC_BWSHARE_MPEC_0_MPEC_BW_HIGHTH_SHIFT)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_HIGHTH_RANGE                  18:11
+#define MC_BWSHARE_MPEC_0_MPEC_BW_HIGHTH_WOFFSET                        0x0
+#define MC_BWSHARE_MPEC_0_MPEC_BW_HIGHTH_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_HIGHTH_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_HIGHTH_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_HIGHTH_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_MPEC_0_MPEC_BW_MAXTH_SHIFT                   _MK_SHIFT_CONST(19)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_MAXTH_FIELD                   (_MK_MASK_CONST(0xff) << MC_BWSHARE_MPEC_0_MPEC_BW_MAXTH_SHIFT)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_MAXTH_RANGE                   26:19
+#define MC_BWSHARE_MPEC_0_MPEC_BW_MAXTH_WOFFSET                 0x0
+#define MC_BWSHARE_MPEC_0_MPEC_BW_MAXTH_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_MAXTH_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_MAXTH_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_MAXTH_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_MPEC_0_MPEC_BW_ALWAYSINC_SHIFT                       _MK_SHIFT_CONST(27)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_ALWAYSINC_FIELD                       (_MK_MASK_CONST(0x1) << MC_BWSHARE_MPEC_0_MPEC_BW_ALWAYSINC_SHIFT)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_ALWAYSINC_RANGE                       27:27
+#define MC_BWSHARE_MPEC_0_MPEC_BW_ALWAYSINC_WOFFSET                     0x0
+#define MC_BWSHARE_MPEC_0_MPEC_BW_ALWAYSINC_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_ALWAYSINC_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_ALWAYSINC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_ALWAYSINC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_ALWAYSINC_INIT_ENUM                   DISABLE
+#define MC_BWSHARE_MPEC_0_MPEC_BW_ALWAYSINC_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_ALWAYSINC_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_ALWAYSINC_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_ALWAYSINC_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_MPEC_0_MPEC_BW_TMSFACTORSEL_SHIFT                    _MK_SHIFT_CONST(28)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_TMSFACTORSEL_FIELD                    (_MK_MASK_CONST(0x1) << MC_BWSHARE_MPEC_0_MPEC_BW_TMSFACTORSEL_SHIFT)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_TMSFACTORSEL_RANGE                    28:28
+#define MC_BWSHARE_MPEC_0_MPEC_BW_TMSFACTORSEL_WOFFSET                  0x0
+#define MC_BWSHARE_MPEC_0_MPEC_BW_TMSFACTORSEL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_TMSFACTORSEL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_TMSFACTORSEL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_TMSFACTORSEL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_TMSFACTORSEL_INIT_ENUM                        TM_SFACTOR1
+#define MC_BWSHARE_MPEC_0_MPEC_BW_TMSFACTORSEL_TM_SFACTOR1                      _MK_ENUM_CONST(0)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_TMSFACTORSEL_TM_SFACTOR2                      _MK_ENUM_CONST(1)
+
+
+// Register MC_BWSHARE_PPCS_0  
+#define MC_BWSHARE_PPCS_0                       _MK_ADDR_CONST(0x1d8)
+#define MC_BWSHARE_PPCS_0_WORD_COUNT                    0x1
+#define MC_BWSHARE_PPCS_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_PPCS_0_RESET_MASK                    _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_PPCS_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_PPCS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_PPCS_0_READ_MASK                     _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_PPCS_0_WRITE_MASK                    _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_INCVAL_SHIFT                  _MK_SHIFT_CONST(0)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_INCVAL_FIELD                  (_MK_MASK_CONST(0x7ff) << MC_BWSHARE_PPCS_0_PPCS_BW_INCVAL_SHIFT)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_INCVAL_RANGE                  10:0
+#define MC_BWSHARE_PPCS_0_PPCS_BW_INCVAL_WOFFSET                        0x0
+#define MC_BWSHARE_PPCS_0_PPCS_BW_INCVAL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_INCVAL_DEFAULT_MASK                   _MK_MASK_CONST(0x7ff)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_INCVAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_INCVAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_PPCS_0_PPCS_BW_HIGHTH_SHIFT                  _MK_SHIFT_CONST(11)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_HIGHTH_FIELD                  (_MK_MASK_CONST(0xff) << MC_BWSHARE_PPCS_0_PPCS_BW_HIGHTH_SHIFT)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_HIGHTH_RANGE                  18:11
+#define MC_BWSHARE_PPCS_0_PPCS_BW_HIGHTH_WOFFSET                        0x0
+#define MC_BWSHARE_PPCS_0_PPCS_BW_HIGHTH_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_HIGHTH_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_HIGHTH_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_HIGHTH_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_PPCS_0_PPCS_BW_MAXTH_SHIFT                   _MK_SHIFT_CONST(19)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_MAXTH_FIELD                   (_MK_MASK_CONST(0xff) << MC_BWSHARE_PPCS_0_PPCS_BW_MAXTH_SHIFT)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_MAXTH_RANGE                   26:19
+#define MC_BWSHARE_PPCS_0_PPCS_BW_MAXTH_WOFFSET                 0x0
+#define MC_BWSHARE_PPCS_0_PPCS_BW_MAXTH_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_MAXTH_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_MAXTH_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_MAXTH_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_PPCS_0_PPCS_BW_ALWAYSINC_SHIFT                       _MK_SHIFT_CONST(27)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_ALWAYSINC_FIELD                       (_MK_MASK_CONST(0x1) << MC_BWSHARE_PPCS_0_PPCS_BW_ALWAYSINC_SHIFT)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_ALWAYSINC_RANGE                       27:27
+#define MC_BWSHARE_PPCS_0_PPCS_BW_ALWAYSINC_WOFFSET                     0x0
+#define MC_BWSHARE_PPCS_0_PPCS_BW_ALWAYSINC_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_ALWAYSINC_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_ALWAYSINC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_ALWAYSINC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_ALWAYSINC_INIT_ENUM                   DISABLE
+#define MC_BWSHARE_PPCS_0_PPCS_BW_ALWAYSINC_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_ALWAYSINC_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_ALWAYSINC_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_ALWAYSINC_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_PPCS_0_PPCS_BW_TMSFACTORSEL_SHIFT                    _MK_SHIFT_CONST(28)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_TMSFACTORSEL_FIELD                    (_MK_MASK_CONST(0x1) << MC_BWSHARE_PPCS_0_PPCS_BW_TMSFACTORSEL_SHIFT)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_TMSFACTORSEL_RANGE                    28:28
+#define MC_BWSHARE_PPCS_0_PPCS_BW_TMSFACTORSEL_WOFFSET                  0x0
+#define MC_BWSHARE_PPCS_0_PPCS_BW_TMSFACTORSEL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_TMSFACTORSEL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_TMSFACTORSEL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_TMSFACTORSEL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_TMSFACTORSEL_INIT_ENUM                        TM_SFACTOR1
+#define MC_BWSHARE_PPCS_0_PPCS_BW_TMSFACTORSEL_TM_SFACTOR1                      _MK_ENUM_CONST(0)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_TMSFACTORSEL_TM_SFACTOR2                      _MK_ENUM_CONST(1)
+
+
+// Register MC_BWSHARE_TEX_0  
+#define MC_BWSHARE_TEX_0                        _MK_ADDR_CONST(0x1dc)
+#define MC_BWSHARE_TEX_0_WORD_COUNT                     0x1
+#define MC_BWSHARE_TEX_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_TEX_0_RESET_MASK                     _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_TEX_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_TEX_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_TEX_0_READ_MASK                      _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_TEX_0_WRITE_MASK                     _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_TEX_0_TEX_BW_INCVAL_SHIFT                    _MK_SHIFT_CONST(0)
+#define MC_BWSHARE_TEX_0_TEX_BW_INCVAL_FIELD                    (_MK_MASK_CONST(0x7ff) << MC_BWSHARE_TEX_0_TEX_BW_INCVAL_SHIFT)
+#define MC_BWSHARE_TEX_0_TEX_BW_INCVAL_RANGE                    10:0
+#define MC_BWSHARE_TEX_0_TEX_BW_INCVAL_WOFFSET                  0x0
+#define MC_BWSHARE_TEX_0_TEX_BW_INCVAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_TEX_0_TEX_BW_INCVAL_DEFAULT_MASK                     _MK_MASK_CONST(0x7ff)
+#define MC_BWSHARE_TEX_0_TEX_BW_INCVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_TEX_0_TEX_BW_INCVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_TEX_0_TEX_BW_HIGHTH_SHIFT                    _MK_SHIFT_CONST(11)
+#define MC_BWSHARE_TEX_0_TEX_BW_HIGHTH_FIELD                    (_MK_MASK_CONST(0xff) << MC_BWSHARE_TEX_0_TEX_BW_HIGHTH_SHIFT)
+#define MC_BWSHARE_TEX_0_TEX_BW_HIGHTH_RANGE                    18:11
+#define MC_BWSHARE_TEX_0_TEX_BW_HIGHTH_WOFFSET                  0x0
+#define MC_BWSHARE_TEX_0_TEX_BW_HIGHTH_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_TEX_0_TEX_BW_HIGHTH_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_TEX_0_TEX_BW_HIGHTH_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_TEX_0_TEX_BW_HIGHTH_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_TEX_0_TEX_BW_MAXTH_SHIFT                     _MK_SHIFT_CONST(19)
+#define MC_BWSHARE_TEX_0_TEX_BW_MAXTH_FIELD                     (_MK_MASK_CONST(0xff) << MC_BWSHARE_TEX_0_TEX_BW_MAXTH_SHIFT)
+#define MC_BWSHARE_TEX_0_TEX_BW_MAXTH_RANGE                     26:19
+#define MC_BWSHARE_TEX_0_TEX_BW_MAXTH_WOFFSET                   0x0
+#define MC_BWSHARE_TEX_0_TEX_BW_MAXTH_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_TEX_0_TEX_BW_MAXTH_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_TEX_0_TEX_BW_MAXTH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_TEX_0_TEX_BW_MAXTH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_TEX_0_TEX_BW_ALWAYSINC_SHIFT                 _MK_SHIFT_CONST(27)
+#define MC_BWSHARE_TEX_0_TEX_BW_ALWAYSINC_FIELD                 (_MK_MASK_CONST(0x1) << MC_BWSHARE_TEX_0_TEX_BW_ALWAYSINC_SHIFT)
+#define MC_BWSHARE_TEX_0_TEX_BW_ALWAYSINC_RANGE                 27:27
+#define MC_BWSHARE_TEX_0_TEX_BW_ALWAYSINC_WOFFSET                       0x0
+#define MC_BWSHARE_TEX_0_TEX_BW_ALWAYSINC_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_TEX_0_TEX_BW_ALWAYSINC_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_TEX_0_TEX_BW_ALWAYSINC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_TEX_0_TEX_BW_ALWAYSINC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_TEX_0_TEX_BW_ALWAYSINC_INIT_ENUM                     DISABLE
+#define MC_BWSHARE_TEX_0_TEX_BW_ALWAYSINC_DISABLE                       _MK_ENUM_CONST(0)
+#define MC_BWSHARE_TEX_0_TEX_BW_ALWAYSINC_ENABLE                        _MK_ENUM_CONST(1)
+#define MC_BWSHARE_TEX_0_TEX_BW_ALWAYSINC_DISABLED                      _MK_ENUM_CONST(0)
+#define MC_BWSHARE_TEX_0_TEX_BW_ALWAYSINC_ENABLED                       _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_TEX_0_TEX_BW_TMSFACTORSEL_SHIFT                      _MK_SHIFT_CONST(28)
+#define MC_BWSHARE_TEX_0_TEX_BW_TMSFACTORSEL_FIELD                      (_MK_MASK_CONST(0x1) << MC_BWSHARE_TEX_0_TEX_BW_TMSFACTORSEL_SHIFT)
+#define MC_BWSHARE_TEX_0_TEX_BW_TMSFACTORSEL_RANGE                      28:28
+#define MC_BWSHARE_TEX_0_TEX_BW_TMSFACTORSEL_WOFFSET                    0x0
+#define MC_BWSHARE_TEX_0_TEX_BW_TMSFACTORSEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_TEX_0_TEX_BW_TMSFACTORSEL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_TEX_0_TEX_BW_TMSFACTORSEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_TEX_0_TEX_BW_TMSFACTORSEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_TEX_0_TEX_BW_TMSFACTORSEL_INIT_ENUM                  TM_SFACTOR1
+#define MC_BWSHARE_TEX_0_TEX_BW_TMSFACTORSEL_TM_SFACTOR1                        _MK_ENUM_CONST(0)
+#define MC_BWSHARE_TEX_0_TEX_BW_TMSFACTORSEL_TM_SFACTOR2                        _MK_ENUM_CONST(1)
+
+
+// Register MC_BWSHARE_VDE_0  
+#define MC_BWSHARE_VDE_0                        _MK_ADDR_CONST(0x1e0)
+#define MC_BWSHARE_VDE_0_WORD_COUNT                     0x1
+#define MC_BWSHARE_VDE_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_VDE_0_RESET_MASK                     _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_VDE_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_VDE_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_VDE_0_READ_MASK                      _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_VDE_0_WRITE_MASK                     _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_VDE_0_VDE_BW_INCVAL_SHIFT                    _MK_SHIFT_CONST(0)
+#define MC_BWSHARE_VDE_0_VDE_BW_INCVAL_FIELD                    (_MK_MASK_CONST(0x7ff) << MC_BWSHARE_VDE_0_VDE_BW_INCVAL_SHIFT)
+#define MC_BWSHARE_VDE_0_VDE_BW_INCVAL_RANGE                    10:0
+#define MC_BWSHARE_VDE_0_VDE_BW_INCVAL_WOFFSET                  0x0
+#define MC_BWSHARE_VDE_0_VDE_BW_INCVAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_VDE_0_VDE_BW_INCVAL_DEFAULT_MASK                     _MK_MASK_CONST(0x7ff)
+#define MC_BWSHARE_VDE_0_VDE_BW_INCVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_VDE_0_VDE_BW_INCVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_VDE_0_VDE_BW_HIGHTH_SHIFT                    _MK_SHIFT_CONST(11)
+#define MC_BWSHARE_VDE_0_VDE_BW_HIGHTH_FIELD                    (_MK_MASK_CONST(0xff) << MC_BWSHARE_VDE_0_VDE_BW_HIGHTH_SHIFT)
+#define MC_BWSHARE_VDE_0_VDE_BW_HIGHTH_RANGE                    18:11
+#define MC_BWSHARE_VDE_0_VDE_BW_HIGHTH_WOFFSET                  0x0
+#define MC_BWSHARE_VDE_0_VDE_BW_HIGHTH_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_VDE_0_VDE_BW_HIGHTH_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_VDE_0_VDE_BW_HIGHTH_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_VDE_0_VDE_BW_HIGHTH_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_VDE_0_VDE_BW_MAXTH_SHIFT                     _MK_SHIFT_CONST(19)
+#define MC_BWSHARE_VDE_0_VDE_BW_MAXTH_FIELD                     (_MK_MASK_CONST(0xff) << MC_BWSHARE_VDE_0_VDE_BW_MAXTH_SHIFT)
+#define MC_BWSHARE_VDE_0_VDE_BW_MAXTH_RANGE                     26:19
+#define MC_BWSHARE_VDE_0_VDE_BW_MAXTH_WOFFSET                   0x0
+#define MC_BWSHARE_VDE_0_VDE_BW_MAXTH_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_VDE_0_VDE_BW_MAXTH_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_VDE_0_VDE_BW_MAXTH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_VDE_0_VDE_BW_MAXTH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_VDE_0_VDE_BW_ALWAYSINC_SHIFT                 _MK_SHIFT_CONST(27)
+#define MC_BWSHARE_VDE_0_VDE_BW_ALWAYSINC_FIELD                 (_MK_MASK_CONST(0x1) << MC_BWSHARE_VDE_0_VDE_BW_ALWAYSINC_SHIFT)
+#define MC_BWSHARE_VDE_0_VDE_BW_ALWAYSINC_RANGE                 27:27
+#define MC_BWSHARE_VDE_0_VDE_BW_ALWAYSINC_WOFFSET                       0x0
+#define MC_BWSHARE_VDE_0_VDE_BW_ALWAYSINC_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_VDE_0_VDE_BW_ALWAYSINC_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_VDE_0_VDE_BW_ALWAYSINC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_VDE_0_VDE_BW_ALWAYSINC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_VDE_0_VDE_BW_ALWAYSINC_INIT_ENUM                     DISABLE
+#define MC_BWSHARE_VDE_0_VDE_BW_ALWAYSINC_DISABLE                       _MK_ENUM_CONST(0)
+#define MC_BWSHARE_VDE_0_VDE_BW_ALWAYSINC_ENABLE                        _MK_ENUM_CONST(1)
+#define MC_BWSHARE_VDE_0_VDE_BW_ALWAYSINC_DISABLED                      _MK_ENUM_CONST(0)
+#define MC_BWSHARE_VDE_0_VDE_BW_ALWAYSINC_ENABLED                       _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_VDE_0_VDE_BW_TMSFACTORSEL_SHIFT                      _MK_SHIFT_CONST(28)
+#define MC_BWSHARE_VDE_0_VDE_BW_TMSFACTORSEL_FIELD                      (_MK_MASK_CONST(0x1) << MC_BWSHARE_VDE_0_VDE_BW_TMSFACTORSEL_SHIFT)
+#define MC_BWSHARE_VDE_0_VDE_BW_TMSFACTORSEL_RANGE                      28:28
+#define MC_BWSHARE_VDE_0_VDE_BW_TMSFACTORSEL_WOFFSET                    0x0
+#define MC_BWSHARE_VDE_0_VDE_BW_TMSFACTORSEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_VDE_0_VDE_BW_TMSFACTORSEL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_VDE_0_VDE_BW_TMSFACTORSEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_VDE_0_VDE_BW_TMSFACTORSEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_VDE_0_VDE_BW_TMSFACTORSEL_INIT_ENUM                  TM_SFACTOR1
+#define MC_BWSHARE_VDE_0_VDE_BW_TMSFACTORSEL_TM_SFACTOR1                        _MK_ENUM_CONST(0)
+#define MC_BWSHARE_VDE_0_VDE_BW_TMSFACTORSEL_TM_SFACTOR2                        _MK_ENUM_CONST(1)
+
+
+// Register MC_BWSHARE_VI_0  
+#define MC_BWSHARE_VI_0                 _MK_ADDR_CONST(0x1e4)
+#define MC_BWSHARE_VI_0_WORD_COUNT                      0x1
+#define MC_BWSHARE_VI_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_VI_0_RESET_MASK                      _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_VI_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_VI_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_VI_0_READ_MASK                       _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_VI_0_WRITE_MASK                      _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_VI_0_VI_BW_INCVAL_SHIFT                      _MK_SHIFT_CONST(0)
+#define MC_BWSHARE_VI_0_VI_BW_INCVAL_FIELD                      (_MK_MASK_CONST(0x7ff) << MC_BWSHARE_VI_0_VI_BW_INCVAL_SHIFT)
+#define MC_BWSHARE_VI_0_VI_BW_INCVAL_RANGE                      10:0
+#define MC_BWSHARE_VI_0_VI_BW_INCVAL_WOFFSET                    0x0
+#define MC_BWSHARE_VI_0_VI_BW_INCVAL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_VI_0_VI_BW_INCVAL_DEFAULT_MASK                       _MK_MASK_CONST(0x7ff)
+#define MC_BWSHARE_VI_0_VI_BW_INCVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_VI_0_VI_BW_INCVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_VI_0_VI_BW_HIGHTH_SHIFT                      _MK_SHIFT_CONST(11)
+#define MC_BWSHARE_VI_0_VI_BW_HIGHTH_FIELD                      (_MK_MASK_CONST(0xff) << MC_BWSHARE_VI_0_VI_BW_HIGHTH_SHIFT)
+#define MC_BWSHARE_VI_0_VI_BW_HIGHTH_RANGE                      18:11
+#define MC_BWSHARE_VI_0_VI_BW_HIGHTH_WOFFSET                    0x0
+#define MC_BWSHARE_VI_0_VI_BW_HIGHTH_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_VI_0_VI_BW_HIGHTH_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_VI_0_VI_BW_HIGHTH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_VI_0_VI_BW_HIGHTH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_VI_0_VI_BW_MAXTH_SHIFT                       _MK_SHIFT_CONST(19)
+#define MC_BWSHARE_VI_0_VI_BW_MAXTH_FIELD                       (_MK_MASK_CONST(0xff) << MC_BWSHARE_VI_0_VI_BW_MAXTH_SHIFT)
+#define MC_BWSHARE_VI_0_VI_BW_MAXTH_RANGE                       26:19
+#define MC_BWSHARE_VI_0_VI_BW_MAXTH_WOFFSET                     0x0
+#define MC_BWSHARE_VI_0_VI_BW_MAXTH_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_VI_0_VI_BW_MAXTH_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_VI_0_VI_BW_MAXTH_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_VI_0_VI_BW_MAXTH_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_VI_0_VI_BW_ALWAYSINC_SHIFT                   _MK_SHIFT_CONST(27)
+#define MC_BWSHARE_VI_0_VI_BW_ALWAYSINC_FIELD                   (_MK_MASK_CONST(0x1) << MC_BWSHARE_VI_0_VI_BW_ALWAYSINC_SHIFT)
+#define MC_BWSHARE_VI_0_VI_BW_ALWAYSINC_RANGE                   27:27
+#define MC_BWSHARE_VI_0_VI_BW_ALWAYSINC_WOFFSET                 0x0
+#define MC_BWSHARE_VI_0_VI_BW_ALWAYSINC_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_VI_0_VI_BW_ALWAYSINC_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_VI_0_VI_BW_ALWAYSINC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_VI_0_VI_BW_ALWAYSINC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_VI_0_VI_BW_ALWAYSINC_INIT_ENUM                       DISABLE
+#define MC_BWSHARE_VI_0_VI_BW_ALWAYSINC_DISABLE                 _MK_ENUM_CONST(0)
+#define MC_BWSHARE_VI_0_VI_BW_ALWAYSINC_ENABLE                  _MK_ENUM_CONST(1)
+#define MC_BWSHARE_VI_0_VI_BW_ALWAYSINC_DISABLED                        _MK_ENUM_CONST(0)
+#define MC_BWSHARE_VI_0_VI_BW_ALWAYSINC_ENABLED                 _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_VI_0_VI_BW_TMSFACTORSEL_SHIFT                        _MK_SHIFT_CONST(28)
+#define MC_BWSHARE_VI_0_VI_BW_TMSFACTORSEL_FIELD                        (_MK_MASK_CONST(0x1) << MC_BWSHARE_VI_0_VI_BW_TMSFACTORSEL_SHIFT)
+#define MC_BWSHARE_VI_0_VI_BW_TMSFACTORSEL_RANGE                        28:28
+#define MC_BWSHARE_VI_0_VI_BW_TMSFACTORSEL_WOFFSET                      0x0
+#define MC_BWSHARE_VI_0_VI_BW_TMSFACTORSEL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_VI_0_VI_BW_TMSFACTORSEL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_VI_0_VI_BW_TMSFACTORSEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_VI_0_VI_BW_TMSFACTORSEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_VI_0_VI_BW_TMSFACTORSEL_INIT_ENUM                    TM_SFACTOR1
+#define MC_BWSHARE_VI_0_VI_BW_TMSFACTORSEL_TM_SFACTOR1                  _MK_ENUM_CONST(0)
+#define MC_BWSHARE_VI_0_VI_BW_TMSFACTORSEL_TM_SFACTOR2                  _MK_ENUM_CONST(1)
+
+
+// Register MC_BWSHARE_TMVAL_0  
+#define MC_BWSHARE_TMVAL_0                      _MK_ADDR_CONST(0x1e8)
+#define MC_BWSHARE_TMVAL_0_WORD_COUNT                   0x1
+#define MC_BWSHARE_TMVAL_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_TMVAL_0_RESET_MASK                   _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_TMVAL_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_TMVAL_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_TMVAL_0_READ_MASK                    _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_TMVAL_0_WRITE_MASK                   _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_TMVAL_0_BW_TM_SFACTOR1_SHIFT                 _MK_SHIFT_CONST(0)
+#define MC_BWSHARE_TMVAL_0_BW_TM_SFACTOR1_FIELD                 (_MK_MASK_CONST(0xf) << MC_BWSHARE_TMVAL_0_BW_TM_SFACTOR1_SHIFT)
+#define MC_BWSHARE_TMVAL_0_BW_TM_SFACTOR1_RANGE                 3:0
+#define MC_BWSHARE_TMVAL_0_BW_TM_SFACTOR1_WOFFSET                       0x0
+#define MC_BWSHARE_TMVAL_0_BW_TM_SFACTOR1_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_TMVAL_0_BW_TM_SFACTOR1_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define MC_BWSHARE_TMVAL_0_BW_TM_SFACTOR1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_TMVAL_0_BW_TM_SFACTOR1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_TMVAL_0_BW_TM_SFACTOR2_SHIFT                 _MK_SHIFT_CONST(4)
+#define MC_BWSHARE_TMVAL_0_BW_TM_SFACTOR2_FIELD                 (_MK_MASK_CONST(0xf) << MC_BWSHARE_TMVAL_0_BW_TM_SFACTOR2_SHIFT)
+#define MC_BWSHARE_TMVAL_0_BW_TM_SFACTOR2_RANGE                 7:4
+#define MC_BWSHARE_TMVAL_0_BW_TM_SFACTOR2_WOFFSET                       0x0
+#define MC_BWSHARE_TMVAL_0_BW_TM_SFACTOR2_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_TMVAL_0_BW_TM_SFACTOR2_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define MC_BWSHARE_TMVAL_0_BW_TM_SFACTOR2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_TMVAL_0_BW_TM_SFACTOR2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register MC_AXI_DECERR_OVR_0  
+#define MC_AXI_DECERR_OVR_0                     _MK_ADDR_CONST(0x1ec)
+#define MC_AXI_DECERR_OVR_0_WORD_COUNT                  0x1
+#define MC_AXI_DECERR_OVR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define MC_AXI_DECERR_OVR_0_RESET_MASK                  _MK_MASK_CONST(0xf)
+#define MC_AXI_DECERR_OVR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define MC_AXI_DECERR_OVR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_AXI_DECERR_OVR_0_READ_MASK                   _MK_MASK_CONST(0xf)
+#define MC_AXI_DECERR_OVR_0_WRITE_MASK                  _MK_MASK_CONST(0xf)
+#define MC_AXI_DECERR_OVR_0_CMCR_DECERR_OVR_SHIFT                       _MK_SHIFT_CONST(0)
+#define MC_AXI_DECERR_OVR_0_CMCR_DECERR_OVR_FIELD                       (_MK_MASK_CONST(0x1) << MC_AXI_DECERR_OVR_0_CMCR_DECERR_OVR_SHIFT)
+#define MC_AXI_DECERR_OVR_0_CMCR_DECERR_OVR_RANGE                       0:0
+#define MC_AXI_DECERR_OVR_0_CMCR_DECERR_OVR_WOFFSET                     0x0
+#define MC_AXI_DECERR_OVR_0_CMCR_DECERR_OVR_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_AXI_DECERR_OVR_0_CMCR_DECERR_OVR_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_AXI_DECERR_OVR_0_CMCR_DECERR_OVR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_AXI_DECERR_OVR_0_CMCR_DECERR_OVR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_AXI_DECERR_OVR_0_CMCR_DECERR_OVR_INIT_ENUM                   DISABLE
+#define MC_AXI_DECERR_OVR_0_CMCR_DECERR_OVR_DECERR_ALLOWED                      _MK_ENUM_CONST(0)
+#define MC_AXI_DECERR_OVR_0_CMCR_DECERR_OVR_ALWAYS_OK                   _MK_ENUM_CONST(1)
+#define MC_AXI_DECERR_OVR_0_CMCR_DECERR_OVR_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_AXI_DECERR_OVR_0_CMCR_DECERR_OVR_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_AXI_DECERR_OVR_0_CMCR_DECERR_OVR_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_AXI_DECERR_OVR_0_CMCR_DECERR_OVR_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_AXI_DECERR_OVR_0_CMCW_DECERR_OVR_SHIFT                       _MK_SHIFT_CONST(1)
+#define MC_AXI_DECERR_OVR_0_CMCW_DECERR_OVR_FIELD                       (_MK_MASK_CONST(0x1) << MC_AXI_DECERR_OVR_0_CMCW_DECERR_OVR_SHIFT)
+#define MC_AXI_DECERR_OVR_0_CMCW_DECERR_OVR_RANGE                       1:1
+#define MC_AXI_DECERR_OVR_0_CMCW_DECERR_OVR_WOFFSET                     0x0
+#define MC_AXI_DECERR_OVR_0_CMCW_DECERR_OVR_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_AXI_DECERR_OVR_0_CMCW_DECERR_OVR_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_AXI_DECERR_OVR_0_CMCW_DECERR_OVR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_AXI_DECERR_OVR_0_CMCW_DECERR_OVR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_AXI_DECERR_OVR_0_CMCW_DECERR_OVR_INIT_ENUM                   DISABLE
+#define MC_AXI_DECERR_OVR_0_CMCW_DECERR_OVR_DECERR_ALLOWED                      _MK_ENUM_CONST(0)
+#define MC_AXI_DECERR_OVR_0_CMCW_DECERR_OVR_ALWAYS_OK                   _MK_ENUM_CONST(1)
+#define MC_AXI_DECERR_OVR_0_CMCW_DECERR_OVR_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_AXI_DECERR_OVR_0_CMCW_DECERR_OVR_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_AXI_DECERR_OVR_0_CMCW_DECERR_OVR_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_AXI_DECERR_OVR_0_CMCW_DECERR_OVR_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_AXI_DECERR_OVR_0_MPCORER_DECERR_OVR_SHIFT                    _MK_SHIFT_CONST(2)
+#define MC_AXI_DECERR_OVR_0_MPCORER_DECERR_OVR_FIELD                    (_MK_MASK_CONST(0x1) << MC_AXI_DECERR_OVR_0_MPCORER_DECERR_OVR_SHIFT)
+#define MC_AXI_DECERR_OVR_0_MPCORER_DECERR_OVR_RANGE                    2:2
+#define MC_AXI_DECERR_OVR_0_MPCORER_DECERR_OVR_WOFFSET                  0x0
+#define MC_AXI_DECERR_OVR_0_MPCORER_DECERR_OVR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_AXI_DECERR_OVR_0_MPCORER_DECERR_OVR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_AXI_DECERR_OVR_0_MPCORER_DECERR_OVR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_AXI_DECERR_OVR_0_MPCORER_DECERR_OVR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_AXI_DECERR_OVR_0_MPCORER_DECERR_OVR_INIT_ENUM                        DISABLE
+#define MC_AXI_DECERR_OVR_0_MPCORER_DECERR_OVR_DECERR_ALLOWED                   _MK_ENUM_CONST(0)
+#define MC_AXI_DECERR_OVR_0_MPCORER_DECERR_OVR_ALWAYS_OK                        _MK_ENUM_CONST(1)
+#define MC_AXI_DECERR_OVR_0_MPCORER_DECERR_OVR_DISABLE                  _MK_ENUM_CONST(0)
+#define MC_AXI_DECERR_OVR_0_MPCORER_DECERR_OVR_ENABLE                   _MK_ENUM_CONST(1)
+#define MC_AXI_DECERR_OVR_0_MPCORER_DECERR_OVR_DISABLED                 _MK_ENUM_CONST(0)
+#define MC_AXI_DECERR_OVR_0_MPCORER_DECERR_OVR_ENABLED                  _MK_ENUM_CONST(1)
+
+#define MC_AXI_DECERR_OVR_0_MPCOREW_DECERR_OVR_SHIFT                    _MK_SHIFT_CONST(3)
+#define MC_AXI_DECERR_OVR_0_MPCOREW_DECERR_OVR_FIELD                    (_MK_MASK_CONST(0x1) << MC_AXI_DECERR_OVR_0_MPCOREW_DECERR_OVR_SHIFT)
+#define MC_AXI_DECERR_OVR_0_MPCOREW_DECERR_OVR_RANGE                    3:3
+#define MC_AXI_DECERR_OVR_0_MPCOREW_DECERR_OVR_WOFFSET                  0x0
+#define MC_AXI_DECERR_OVR_0_MPCOREW_DECERR_OVR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_AXI_DECERR_OVR_0_MPCOREW_DECERR_OVR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_AXI_DECERR_OVR_0_MPCOREW_DECERR_OVR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_AXI_DECERR_OVR_0_MPCOREW_DECERR_OVR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_AXI_DECERR_OVR_0_MPCOREW_DECERR_OVR_INIT_ENUM                        DISABLE
+#define MC_AXI_DECERR_OVR_0_MPCOREW_DECERR_OVR_DECERR_ALLOWED                   _MK_ENUM_CONST(0)
+#define MC_AXI_DECERR_OVR_0_MPCOREW_DECERR_OVR_ALWAYS_OK                        _MK_ENUM_CONST(1)
+#define MC_AXI_DECERR_OVR_0_MPCOREW_DECERR_OVR_DISABLE                  _MK_ENUM_CONST(0)
+#define MC_AXI_DECERR_OVR_0_MPCOREW_DECERR_OVR_ENABLE                   _MK_ENUM_CONST(1)
+#define MC_AXI_DECERR_OVR_0_MPCOREW_DECERR_OVR_DISABLED                 _MK_ENUM_CONST(0)
+#define MC_AXI_DECERR_OVR_0_MPCOREW_DECERR_OVR_ENABLED                  _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_LL_CTRL_DISABLE       0
+#define MC_CLIENT_LL_CTRL_ENABLE        1
+
+// Register MC_LOWLATENCY_CONFIG_0  
+#define MC_LOWLATENCY_CONFIG_0                  _MK_ADDR_CONST(0x1f0)
+#define MC_LOWLATENCY_CONFIG_0_WORD_COUNT                       0x1
+#define MC_LOWLATENCY_CONFIG_0_RESET_VAL                        _MK_MASK_CONST(0x8000000f)
+#define MC_LOWLATENCY_CONFIG_0_RESET_MASK                       _MK_MASK_CONST(0x8000000f)
+#define MC_LOWLATENCY_CONFIG_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_CONFIG_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_CONFIG_0_READ_MASK                        _MK_MASK_CONST(0x8000000f)
+#define MC_LOWLATENCY_CONFIG_0_WRITE_MASK                       _MK_MASK_CONST(0x8000000f)
+#define MC_LOWLATENCY_CONFIG_0_CMCR_LL_CTRL_SHIFT                       _MK_SHIFT_CONST(0)
+#define MC_LOWLATENCY_CONFIG_0_CMCR_LL_CTRL_FIELD                       (_MK_MASK_CONST(0x1) << MC_LOWLATENCY_CONFIG_0_CMCR_LL_CTRL_SHIFT)
+#define MC_LOWLATENCY_CONFIG_0_CMCR_LL_CTRL_RANGE                       0:0
+#define MC_LOWLATENCY_CONFIG_0_CMCR_LL_CTRL_WOFFSET                     0x0
+#define MC_LOWLATENCY_CONFIG_0_CMCR_LL_CTRL_DEFAULT                     _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_CONFIG_0_CMCR_LL_CTRL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_CONFIG_0_CMCR_LL_CTRL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_CONFIG_0_CMCR_LL_CTRL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_CONFIG_0_CMCR_LL_CTRL_INIT_ENUM                   ENABLE
+#define MC_LOWLATENCY_CONFIG_0_CMCR_LL_CTRL_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_CONFIG_0_CMCR_LL_CTRL_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_LOWLATENCY_CONFIG_0_CMCR_LL_CTRL_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_CONFIG_0_CMCR_LL_CTRL_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_LOWLATENCY_CONFIG_0_CMCR_LL_SEND_BOTH_SHIFT                  _MK_SHIFT_CONST(1)
+#define MC_LOWLATENCY_CONFIG_0_CMCR_LL_SEND_BOTH_FIELD                  (_MK_MASK_CONST(0x1) << MC_LOWLATENCY_CONFIG_0_CMCR_LL_SEND_BOTH_SHIFT)
+#define MC_LOWLATENCY_CONFIG_0_CMCR_LL_SEND_BOTH_RANGE                  1:1
+#define MC_LOWLATENCY_CONFIG_0_CMCR_LL_SEND_BOTH_WOFFSET                        0x0
+#define MC_LOWLATENCY_CONFIG_0_CMCR_LL_SEND_BOTH_DEFAULT                        _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_CONFIG_0_CMCR_LL_SEND_BOTH_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_CONFIG_0_CMCR_LL_SEND_BOTH_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_CONFIG_0_CMCR_LL_SEND_BOTH_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_CONFIG_0_CMCR_LL_SEND_BOTH_INIT_ENUM                      ENABLE
+#define MC_LOWLATENCY_CONFIG_0_CMCR_LL_SEND_BOTH_DISABLE                        _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_CONFIG_0_CMCR_LL_SEND_BOTH_ENABLE                 _MK_ENUM_CONST(1)
+#define MC_LOWLATENCY_CONFIG_0_CMCR_LL_SEND_BOTH_DISABLED                       _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_CONFIG_0_CMCR_LL_SEND_BOTH_ENABLED                        _MK_ENUM_CONST(1)
+
+#define MC_LOWLATENCY_CONFIG_0_MPCORER_LL_CTRL_SHIFT                    _MK_SHIFT_CONST(2)
+#define MC_LOWLATENCY_CONFIG_0_MPCORER_LL_CTRL_FIELD                    (_MK_MASK_CONST(0x1) << MC_LOWLATENCY_CONFIG_0_MPCORER_LL_CTRL_SHIFT)
+#define MC_LOWLATENCY_CONFIG_0_MPCORER_LL_CTRL_RANGE                    2:2
+#define MC_LOWLATENCY_CONFIG_0_MPCORER_LL_CTRL_WOFFSET                  0x0
+#define MC_LOWLATENCY_CONFIG_0_MPCORER_LL_CTRL_DEFAULT                  _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_CONFIG_0_MPCORER_LL_CTRL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_CONFIG_0_MPCORER_LL_CTRL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_CONFIG_0_MPCORER_LL_CTRL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_CONFIG_0_MPCORER_LL_CTRL_INIT_ENUM                        ENABLE
+#define MC_LOWLATENCY_CONFIG_0_MPCORER_LL_CTRL_DISABLE                  _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_CONFIG_0_MPCORER_LL_CTRL_ENABLE                   _MK_ENUM_CONST(1)
+#define MC_LOWLATENCY_CONFIG_0_MPCORER_LL_CTRL_DISABLED                 _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_CONFIG_0_MPCORER_LL_CTRL_ENABLED                  _MK_ENUM_CONST(1)
+
+#define MC_LOWLATENCY_CONFIG_0_MPCORER_LL_SEND_BOTH_SHIFT                       _MK_SHIFT_CONST(3)
+#define MC_LOWLATENCY_CONFIG_0_MPCORER_LL_SEND_BOTH_FIELD                       (_MK_MASK_CONST(0x1) << MC_LOWLATENCY_CONFIG_0_MPCORER_LL_SEND_BOTH_SHIFT)
+#define MC_LOWLATENCY_CONFIG_0_MPCORER_LL_SEND_BOTH_RANGE                       3:3
+#define MC_LOWLATENCY_CONFIG_0_MPCORER_LL_SEND_BOTH_WOFFSET                     0x0
+#define MC_LOWLATENCY_CONFIG_0_MPCORER_LL_SEND_BOTH_DEFAULT                     _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_CONFIG_0_MPCORER_LL_SEND_BOTH_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_CONFIG_0_MPCORER_LL_SEND_BOTH_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_CONFIG_0_MPCORER_LL_SEND_BOTH_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_CONFIG_0_MPCORER_LL_SEND_BOTH_INIT_ENUM                   ENABLE
+#define MC_LOWLATENCY_CONFIG_0_MPCORER_LL_SEND_BOTH_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_CONFIG_0_MPCORER_LL_SEND_BOTH_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_LOWLATENCY_CONFIG_0_MPCORER_LL_SEND_BOTH_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_CONFIG_0_MPCORER_LL_SEND_BOTH_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_LOWLATENCY_CONFIG_0_LL_DRAM_INTERLEAVE_SHIFT                 _MK_SHIFT_CONST(31)
+#define MC_LOWLATENCY_CONFIG_0_LL_DRAM_INTERLEAVE_FIELD                 (_MK_MASK_CONST(0x1) << MC_LOWLATENCY_CONFIG_0_LL_DRAM_INTERLEAVE_SHIFT)
+#define MC_LOWLATENCY_CONFIG_0_LL_DRAM_INTERLEAVE_RANGE                 31:31
+#define MC_LOWLATENCY_CONFIG_0_LL_DRAM_INTERLEAVE_WOFFSET                       0x0
+#define MC_LOWLATENCY_CONFIG_0_LL_DRAM_INTERLEAVE_DEFAULT                       _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_CONFIG_0_LL_DRAM_INTERLEAVE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_CONFIG_0_LL_DRAM_INTERLEAVE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_CONFIG_0_LL_DRAM_INTERLEAVE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_CONFIG_0_LL_DRAM_INTERLEAVE_INIT_ENUM                     ENABLE
+#define MC_LOWLATENCY_CONFIG_0_LL_DRAM_INTERLEAVE_DISABLE                       _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_CONFIG_0_LL_DRAM_INTERLEAVE_ENABLE                        _MK_ENUM_CONST(1)
+#define MC_LOWLATENCY_CONFIG_0_LL_DRAM_INTERLEAVE_DISABLED                      _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_CONFIG_0_LL_DRAM_INTERLEAVE_ENABLED                       _MK_ENUM_CONST(1)
+
+
+// Register MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0  
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0                     _MK_ADDR_CONST(0x1f4)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_WORD_COUNT                  0x1
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_RESET_VAL                   _MK_MASK_CONST(0x3fffff)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_RESET_MASK                  _MK_MASK_CONST(0x3fffff)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_READ_MASK                   _MK_MASK_CONST(0x3fffff)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_WRITE_MASK                  _MK_MASK_CONST(0x3fffff)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPU_LL_RAW_PARTICIPATE_SHIFT                       _MK_SHIFT_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPU_LL_RAW_PARTICIPATE_FIELD                       (_MK_MASK_CONST(0x1) << MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPU_LL_RAW_PARTICIPATE_SHIFT)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPU_LL_RAW_PARTICIPATE_RANGE                       0:0
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPU_LL_RAW_PARTICIPATE_WOFFSET                     0x0
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPU_LL_RAW_PARTICIPATE_DEFAULT                     _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPU_LL_RAW_PARTICIPATE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPU_LL_RAW_PARTICIPATE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPU_LL_RAW_PARTICIPATE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPU_LL_RAW_PARTICIPATE_INIT_ENUM                   ENABLE
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPU_LL_RAW_PARTICIPATE_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPU_LL_RAW_PARTICIPATE_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPU_LL_RAW_PARTICIPATE_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPU_LL_RAW_PARTICIPATE_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPV_LL_RAW_PARTICIPATE_SHIFT                       _MK_SHIFT_CONST(1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPV_LL_RAW_PARTICIPATE_FIELD                       (_MK_MASK_CONST(0x1) << MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPV_LL_RAW_PARTICIPATE_SHIFT)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPV_LL_RAW_PARTICIPATE_RANGE                       1:1
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPV_LL_RAW_PARTICIPATE_WOFFSET                     0x0
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPV_LL_RAW_PARTICIPATE_DEFAULT                     _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPV_LL_RAW_PARTICIPATE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPV_LL_RAW_PARTICIPATE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPV_LL_RAW_PARTICIPATE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPV_LL_RAW_PARTICIPATE_INIT_ENUM                   ENABLE
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPV_LL_RAW_PARTICIPATE_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPV_LL_RAW_PARTICIPATE_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPV_LL_RAW_PARTICIPATE_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPV_LL_RAW_PARTICIPATE_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPY_LL_RAW_PARTICIPATE_SHIFT                       _MK_SHIFT_CONST(2)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPY_LL_RAW_PARTICIPATE_FIELD                       (_MK_MASK_CONST(0x1) << MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPY_LL_RAW_PARTICIPATE_SHIFT)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPY_LL_RAW_PARTICIPATE_RANGE                       2:2
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPY_LL_RAW_PARTICIPATE_WOFFSET                     0x0
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPY_LL_RAW_PARTICIPATE_DEFAULT                     _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPY_LL_RAW_PARTICIPATE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPY_LL_RAW_PARTICIPATE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPY_LL_RAW_PARTICIPATE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPY_LL_RAW_PARTICIPATE_INIT_ENUM                   ENABLE
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPY_LL_RAW_PARTICIPATE_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPY_LL_RAW_PARTICIPATE_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPY_LL_RAW_PARTICIPATE_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPY_LL_RAW_PARTICIPATE_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPEUNIFBW_LL_RAW_PARTICIPATE_SHIFT                  _MK_SHIFT_CONST(3)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPEUNIFBW_LL_RAW_PARTICIPATE_FIELD                  (_MK_MASK_CONST(0x1) << MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPEUNIFBW_LL_RAW_PARTICIPATE_SHIFT)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPEUNIFBW_LL_RAW_PARTICIPATE_RANGE                  3:3
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPEUNIFBW_LL_RAW_PARTICIPATE_WOFFSET                        0x0
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPEUNIFBW_LL_RAW_PARTICIPATE_DEFAULT                        _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPEUNIFBW_LL_RAW_PARTICIPATE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPEUNIFBW_LL_RAW_PARTICIPATE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPEUNIFBW_LL_RAW_PARTICIPATE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPEUNIFBW_LL_RAW_PARTICIPATE_INIT_ENUM                      ENABLE
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPEUNIFBW_LL_RAW_PARTICIPATE_DISABLE                        _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPEUNIFBW_LL_RAW_PARTICIPATE_ENABLE                 _MK_ENUM_CONST(1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPEUNIFBW_LL_RAW_PARTICIPATE_DISABLED                       _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPEUNIFBW_LL_RAW_PARTICIPATE_ENABLED                        _MK_ENUM_CONST(1)
+
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWSB_LL_RAW_PARTICIPATE_SHIFT                      _MK_SHIFT_CONST(4)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWSB_LL_RAW_PARTICIPATE_FIELD                      (_MK_MASK_CONST(0x1) << MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWSB_LL_RAW_PARTICIPATE_SHIFT)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWSB_LL_RAW_PARTICIPATE_RANGE                      4:4
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWSB_LL_RAW_PARTICIPATE_WOFFSET                    0x0
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWSB_LL_RAW_PARTICIPATE_DEFAULT                    _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWSB_LL_RAW_PARTICIPATE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWSB_LL_RAW_PARTICIPATE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWSB_LL_RAW_PARTICIPATE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWSB_LL_RAW_PARTICIPATE_INIT_ENUM                  ENABLE
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWSB_LL_RAW_PARTICIPATE_DISABLE                    _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWSB_LL_RAW_PARTICIPATE_ENABLE                     _MK_ENUM_CONST(1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWSB_LL_RAW_PARTICIPATE_DISABLED                   _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWSB_LL_RAW_PARTICIPATE_ENABLED                    _MK_ENUM_CONST(1)
+
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWU_LL_RAW_PARTICIPATE_SHIFT                       _MK_SHIFT_CONST(5)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWU_LL_RAW_PARTICIPATE_FIELD                       (_MK_MASK_CONST(0x1) << MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWU_LL_RAW_PARTICIPATE_SHIFT)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWU_LL_RAW_PARTICIPATE_RANGE                       5:5
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWU_LL_RAW_PARTICIPATE_WOFFSET                     0x0
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWU_LL_RAW_PARTICIPATE_DEFAULT                     _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWU_LL_RAW_PARTICIPATE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWU_LL_RAW_PARTICIPATE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWU_LL_RAW_PARTICIPATE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWU_LL_RAW_PARTICIPATE_INIT_ENUM                   ENABLE
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWU_LL_RAW_PARTICIPATE_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWU_LL_RAW_PARTICIPATE_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWU_LL_RAW_PARTICIPATE_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWU_LL_RAW_PARTICIPATE_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWV_LL_RAW_PARTICIPATE_SHIFT                       _MK_SHIFT_CONST(6)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWV_LL_RAW_PARTICIPATE_FIELD                       (_MK_MASK_CONST(0x1) << MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWV_LL_RAW_PARTICIPATE_SHIFT)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWV_LL_RAW_PARTICIPATE_RANGE                       6:6
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWV_LL_RAW_PARTICIPATE_WOFFSET                     0x0
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWV_LL_RAW_PARTICIPATE_DEFAULT                     _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWV_LL_RAW_PARTICIPATE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWV_LL_RAW_PARTICIPATE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWV_LL_RAW_PARTICIPATE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWV_LL_RAW_PARTICIPATE_INIT_ENUM                   ENABLE
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWV_LL_RAW_PARTICIPATE_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWV_LL_RAW_PARTICIPATE_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWV_LL_RAW_PARTICIPATE_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWV_LL_RAW_PARTICIPATE_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWY_LL_RAW_PARTICIPATE_SHIFT                       _MK_SHIFT_CONST(7)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWY_LL_RAW_PARTICIPATE_FIELD                       (_MK_MASK_CONST(0x1) << MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWY_LL_RAW_PARTICIPATE_SHIFT)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWY_LL_RAW_PARTICIPATE_RANGE                       7:7
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWY_LL_RAW_PARTICIPATE_WOFFSET                     0x0
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWY_LL_RAW_PARTICIPATE_DEFAULT                     _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWY_LL_RAW_PARTICIPATE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWY_LL_RAW_PARTICIPATE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWY_LL_RAW_PARTICIPATE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWY_LL_RAW_PARTICIPATE_INIT_ENUM                   ENABLE
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWY_LL_RAW_PARTICIPATE_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWY_LL_RAW_PARTICIPATE_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWY_LL_RAW_PARTICIPATE_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWY_LL_RAW_PARTICIPATE_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_G2DW_LL_RAW_PARTICIPATE_SHIFT                       _MK_SHIFT_CONST(8)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_G2DW_LL_RAW_PARTICIPATE_FIELD                       (_MK_MASK_CONST(0x1) << MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_G2DW_LL_RAW_PARTICIPATE_SHIFT)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_G2DW_LL_RAW_PARTICIPATE_RANGE                       8:8
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_G2DW_LL_RAW_PARTICIPATE_WOFFSET                     0x0
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_G2DW_LL_RAW_PARTICIPATE_DEFAULT                     _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_G2DW_LL_RAW_PARTICIPATE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_G2DW_LL_RAW_PARTICIPATE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_G2DW_LL_RAW_PARTICIPATE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_G2DW_LL_RAW_PARTICIPATE_INIT_ENUM                   ENABLE
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_G2DW_LL_RAW_PARTICIPATE_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_G2DW_LL_RAW_PARTICIPATE_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_G2DW_LL_RAW_PARTICIPATE_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_G2DW_LL_RAW_PARTICIPATE_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_CMCW_LL_RAW_PARTICIPATE_SHIFT                       _MK_SHIFT_CONST(9)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_CMCW_LL_RAW_PARTICIPATE_FIELD                       (_MK_MASK_CONST(0x1) << MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_CMCW_LL_RAW_PARTICIPATE_SHIFT)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_CMCW_LL_RAW_PARTICIPATE_RANGE                       9:9
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_CMCW_LL_RAW_PARTICIPATE_WOFFSET                     0x0
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_CMCW_LL_RAW_PARTICIPATE_DEFAULT                     _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_CMCW_LL_RAW_PARTICIPATE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_CMCW_LL_RAW_PARTICIPATE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_CMCW_LL_RAW_PARTICIPATE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_CMCW_LL_RAW_PARTICIPATE_INIT_ENUM                   ENABLE
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_CMCW_LL_RAW_PARTICIPATE_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_CMCW_LL_RAW_PARTICIPATE_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_CMCW_LL_RAW_PARTICIPATE_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_CMCW_LL_RAW_PARTICIPATE_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_FDCDWR_LL_RAW_PARTICIPATE_SHIFT                     _MK_SHIFT_CONST(10)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_FDCDWR_LL_RAW_PARTICIPATE_FIELD                     (_MK_MASK_CONST(0x1) << MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_FDCDWR_LL_RAW_PARTICIPATE_SHIFT)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_FDCDWR_LL_RAW_PARTICIPATE_RANGE                     10:10
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_FDCDWR_LL_RAW_PARTICIPATE_WOFFSET                   0x0
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_FDCDWR_LL_RAW_PARTICIPATE_DEFAULT                   _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_FDCDWR_LL_RAW_PARTICIPATE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_FDCDWR_LL_RAW_PARTICIPATE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_FDCDWR_LL_RAW_PARTICIPATE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_FDCDWR_LL_RAW_PARTICIPATE_INIT_ENUM                 ENABLE
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_FDCDWR_LL_RAW_PARTICIPATE_DISABLE                   _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_FDCDWR_LL_RAW_PARTICIPATE_ENABLE                    _MK_ENUM_CONST(1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_FDCDWR_LL_RAW_PARTICIPATE_DISABLED                  _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_FDCDWR_LL_RAW_PARTICIPATE_ENABLED                   _MK_ENUM_CONST(1)
+
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_HOST1XW_LL_RAW_PARTICIPATE_SHIFT                    _MK_SHIFT_CONST(11)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_HOST1XW_LL_RAW_PARTICIPATE_FIELD                    (_MK_MASK_CONST(0x1) << MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_HOST1XW_LL_RAW_PARTICIPATE_SHIFT)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_HOST1XW_LL_RAW_PARTICIPATE_RANGE                    11:11
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_HOST1XW_LL_RAW_PARTICIPATE_WOFFSET                  0x0
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_HOST1XW_LL_RAW_PARTICIPATE_DEFAULT                  _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_HOST1XW_LL_RAW_PARTICIPATE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_HOST1XW_LL_RAW_PARTICIPATE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_HOST1XW_LL_RAW_PARTICIPATE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_HOST1XW_LL_RAW_PARTICIPATE_INIT_ENUM                        ENABLE
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_HOST1XW_LL_RAW_PARTICIPATE_DISABLE                  _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_HOST1XW_LL_RAW_PARTICIPATE_ENABLE                   _MK_ENUM_CONST(1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_HOST1XW_LL_RAW_PARTICIPATE_DISABLED                 _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_HOST1XW_LL_RAW_PARTICIPATE_ENABLED                  _MK_ENUM_CONST(1)
+
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_ISPW_LL_RAW_PARTICIPATE_SHIFT                       _MK_SHIFT_CONST(12)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_ISPW_LL_RAW_PARTICIPATE_FIELD                       (_MK_MASK_CONST(0x1) << MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_ISPW_LL_RAW_PARTICIPATE_SHIFT)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_ISPW_LL_RAW_PARTICIPATE_RANGE                       12:12
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_ISPW_LL_RAW_PARTICIPATE_WOFFSET                     0x0
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_ISPW_LL_RAW_PARTICIPATE_DEFAULT                     _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_ISPW_LL_RAW_PARTICIPATE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_ISPW_LL_RAW_PARTICIPATE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_ISPW_LL_RAW_PARTICIPATE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_ISPW_LL_RAW_PARTICIPATE_INIT_ENUM                   ENABLE
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_ISPW_LL_RAW_PARTICIPATE_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_ISPW_LL_RAW_PARTICIPATE_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_ISPW_LL_RAW_PARTICIPATE_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_ISPW_LL_RAW_PARTICIPATE_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPCOREW_LL_RAW_PARTICIPATE_SHIFT                    _MK_SHIFT_CONST(13)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPCOREW_LL_RAW_PARTICIPATE_FIELD                    (_MK_MASK_CONST(0x1) << MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPCOREW_LL_RAW_PARTICIPATE_SHIFT)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPCOREW_LL_RAW_PARTICIPATE_RANGE                    13:13
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPCOREW_LL_RAW_PARTICIPATE_WOFFSET                  0x0
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPCOREW_LL_RAW_PARTICIPATE_DEFAULT                  _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPCOREW_LL_RAW_PARTICIPATE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPCOREW_LL_RAW_PARTICIPATE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPCOREW_LL_RAW_PARTICIPATE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPCOREW_LL_RAW_PARTICIPATE_INIT_ENUM                        ENABLE
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPCOREW_LL_RAW_PARTICIPATE_DISABLE                  _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPCOREW_LL_RAW_PARTICIPATE_ENABLE                   _MK_ENUM_CONST(1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPCOREW_LL_RAW_PARTICIPATE_DISABLED                 _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPCOREW_LL_RAW_PARTICIPATE_ENABLED                  _MK_ENUM_CONST(1)
+
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPECSWR_LL_RAW_PARTICIPATE_SHIFT                    _MK_SHIFT_CONST(14)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPECSWR_LL_RAW_PARTICIPATE_FIELD                    (_MK_MASK_CONST(0x1) << MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPECSWR_LL_RAW_PARTICIPATE_SHIFT)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPECSWR_LL_RAW_PARTICIPATE_RANGE                    14:14
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPECSWR_LL_RAW_PARTICIPATE_WOFFSET                  0x0
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPECSWR_LL_RAW_PARTICIPATE_DEFAULT                  _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPECSWR_LL_RAW_PARTICIPATE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPECSWR_LL_RAW_PARTICIPATE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPECSWR_LL_RAW_PARTICIPATE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPECSWR_LL_RAW_PARTICIPATE_INIT_ENUM                        ENABLE
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPECSWR_LL_RAW_PARTICIPATE_DISABLE                  _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPECSWR_LL_RAW_PARTICIPATE_ENABLE                   _MK_ENUM_CONST(1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPECSWR_LL_RAW_PARTICIPATE_DISABLED                 _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPECSWR_LL_RAW_PARTICIPATE_ENABLED                  _MK_ENUM_CONST(1)
+
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSAHBDMAW_LL_RAW_PARTICIPATE_SHIFT                        _MK_SHIFT_CONST(15)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSAHBDMAW_LL_RAW_PARTICIPATE_FIELD                        (_MK_MASK_CONST(0x1) << MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSAHBDMAW_LL_RAW_PARTICIPATE_SHIFT)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSAHBDMAW_LL_RAW_PARTICIPATE_RANGE                        15:15
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSAHBDMAW_LL_RAW_PARTICIPATE_WOFFSET                      0x0
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSAHBDMAW_LL_RAW_PARTICIPATE_DEFAULT                      _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSAHBDMAW_LL_RAW_PARTICIPATE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSAHBDMAW_LL_RAW_PARTICIPATE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSAHBDMAW_LL_RAW_PARTICIPATE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSAHBDMAW_LL_RAW_PARTICIPATE_INIT_ENUM                    ENABLE
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSAHBDMAW_LL_RAW_PARTICIPATE_DISABLE                      _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSAHBDMAW_LL_RAW_PARTICIPATE_ENABLE                       _MK_ENUM_CONST(1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSAHBDMAW_LL_RAW_PARTICIPATE_DISABLED                     _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSAHBDMAW_LL_RAW_PARTICIPATE_ENABLED                      _MK_ENUM_CONST(1)
+
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSAHBSLVW_LL_RAW_PARTICIPATE_SHIFT                        _MK_SHIFT_CONST(16)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSAHBSLVW_LL_RAW_PARTICIPATE_FIELD                        (_MK_MASK_CONST(0x1) << MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSAHBSLVW_LL_RAW_PARTICIPATE_SHIFT)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSAHBSLVW_LL_RAW_PARTICIPATE_RANGE                        16:16
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSAHBSLVW_LL_RAW_PARTICIPATE_WOFFSET                      0x0
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSAHBSLVW_LL_RAW_PARTICIPATE_DEFAULT                      _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSAHBSLVW_LL_RAW_PARTICIPATE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSAHBSLVW_LL_RAW_PARTICIPATE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSAHBSLVW_LL_RAW_PARTICIPATE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSAHBSLVW_LL_RAW_PARTICIPATE_INIT_ENUM                    ENABLE
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSAHBSLVW_LL_RAW_PARTICIPATE_DISABLE                      _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSAHBSLVW_LL_RAW_PARTICIPATE_ENABLE                       _MK_ENUM_CONST(1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSAHBSLVW_LL_RAW_PARTICIPATE_DISABLED                     _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSAHBSLVW_LL_RAW_PARTICIPATE_ENABLED                      _MK_ENUM_CONST(1)
+
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSARM7W_LL_RAW_PARTICIPATE_SHIFT                  _MK_SHIFT_CONST(17)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSARM7W_LL_RAW_PARTICIPATE_FIELD                  (_MK_MASK_CONST(0x1) << MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSARM7W_LL_RAW_PARTICIPATE_SHIFT)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSARM7W_LL_RAW_PARTICIPATE_RANGE                  17:17
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSARM7W_LL_RAW_PARTICIPATE_WOFFSET                        0x0
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSARM7W_LL_RAW_PARTICIPATE_DEFAULT                        _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSARM7W_LL_RAW_PARTICIPATE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSARM7W_LL_RAW_PARTICIPATE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSARM7W_LL_RAW_PARTICIPATE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSARM7W_LL_RAW_PARTICIPATE_INIT_ENUM                      ENABLE
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSARM7W_LL_RAW_PARTICIPATE_DISABLE                        _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSARM7W_LL_RAW_PARTICIPATE_ENABLE                 _MK_ENUM_CONST(1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSARM7W_LL_RAW_PARTICIPATE_DISABLED                       _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSARM7W_LL_RAW_PARTICIPATE_ENABLED                        _MK_ENUM_CONST(1)
+
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEBSEAW_LL_RAW_PARTICIPATE_SHIFT                   _MK_SHIFT_CONST(18)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEBSEAW_LL_RAW_PARTICIPATE_FIELD                   (_MK_MASK_CONST(0x1) << MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEBSEAW_LL_RAW_PARTICIPATE_SHIFT)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEBSEAW_LL_RAW_PARTICIPATE_RANGE                   18:18
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEBSEAW_LL_RAW_PARTICIPATE_WOFFSET                 0x0
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEBSEAW_LL_RAW_PARTICIPATE_DEFAULT                 _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEBSEAW_LL_RAW_PARTICIPATE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEBSEAW_LL_RAW_PARTICIPATE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEBSEAW_LL_RAW_PARTICIPATE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEBSEAW_LL_RAW_PARTICIPATE_INIT_ENUM                       ENABLE
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEBSEAW_LL_RAW_PARTICIPATE_DISABLE                 _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEBSEAW_LL_RAW_PARTICIPATE_ENABLE                  _MK_ENUM_CONST(1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEBSEAW_LL_RAW_PARTICIPATE_DISABLED                        _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEBSEAW_LL_RAW_PARTICIPATE_ENABLED                 _MK_ENUM_CONST(1)
+
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEBSEVW_LL_RAW_PARTICIPATE_SHIFT                   _MK_SHIFT_CONST(19)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEBSEVW_LL_RAW_PARTICIPATE_FIELD                   (_MK_MASK_CONST(0x1) << MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEBSEVW_LL_RAW_PARTICIPATE_SHIFT)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEBSEVW_LL_RAW_PARTICIPATE_RANGE                   19:19
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEBSEVW_LL_RAW_PARTICIPATE_WOFFSET                 0x0
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEBSEVW_LL_RAW_PARTICIPATE_DEFAULT                 _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEBSEVW_LL_RAW_PARTICIPATE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEBSEVW_LL_RAW_PARTICIPATE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEBSEVW_LL_RAW_PARTICIPATE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEBSEVW_LL_RAW_PARTICIPATE_INIT_ENUM                       ENABLE
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEBSEVW_LL_RAW_PARTICIPATE_DISABLE                 _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEBSEVW_LL_RAW_PARTICIPATE_ENABLE                  _MK_ENUM_CONST(1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEBSEVW_LL_RAW_PARTICIPATE_DISABLED                        _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEBSEVW_LL_RAW_PARTICIPATE_ENABLED                 _MK_ENUM_CONST(1)
+
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEMBEW_LL_RAW_PARTICIPATE_SHIFT                    _MK_SHIFT_CONST(20)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEMBEW_LL_RAW_PARTICIPATE_FIELD                    (_MK_MASK_CONST(0x1) << MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEMBEW_LL_RAW_PARTICIPATE_SHIFT)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEMBEW_LL_RAW_PARTICIPATE_RANGE                    20:20
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEMBEW_LL_RAW_PARTICIPATE_WOFFSET                  0x0
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEMBEW_LL_RAW_PARTICIPATE_DEFAULT                  _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEMBEW_LL_RAW_PARTICIPATE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEMBEW_LL_RAW_PARTICIPATE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEMBEW_LL_RAW_PARTICIPATE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEMBEW_LL_RAW_PARTICIPATE_INIT_ENUM                        ENABLE
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEMBEW_LL_RAW_PARTICIPATE_DISABLE                  _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEMBEW_LL_RAW_PARTICIPATE_ENABLE                   _MK_ENUM_CONST(1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEMBEW_LL_RAW_PARTICIPATE_DISABLED                 _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEMBEW_LL_RAW_PARTICIPATE_ENABLED                  _MK_ENUM_CONST(1)
+
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDETPMW_LL_RAW_PARTICIPATE_SHIFT                    _MK_SHIFT_CONST(21)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDETPMW_LL_RAW_PARTICIPATE_FIELD                    (_MK_MASK_CONST(0x1) << MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDETPMW_LL_RAW_PARTICIPATE_SHIFT)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDETPMW_LL_RAW_PARTICIPATE_RANGE                    21:21
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDETPMW_LL_RAW_PARTICIPATE_WOFFSET                  0x0
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDETPMW_LL_RAW_PARTICIPATE_DEFAULT                  _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDETPMW_LL_RAW_PARTICIPATE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDETPMW_LL_RAW_PARTICIPATE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDETPMW_LL_RAW_PARTICIPATE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDETPMW_LL_RAW_PARTICIPATE_INIT_ENUM                        ENABLE
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDETPMW_LL_RAW_PARTICIPATE_DISABLE                  _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDETPMW_LL_RAW_PARTICIPATE_ENABLE                   _MK_ENUM_CONST(1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDETPMW_LL_RAW_PARTICIPATE_DISABLED                 _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDETPMW_LL_RAW_PARTICIPATE_ENABLED                  _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_INACTIVE     0
+#define MC_CLIENT_ACTIVITY_MONITOR_ACTIVE       1
+
+// Register MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0  
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0                     _MK_ADDR_CONST(0x1f8)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_WORD_COUNT                  0x1
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0A_EMEM_ACTIVITY_SHIFT                       _MK_SHIFT_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0A_EMEM_ACTIVITY_FIELD                       (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0A_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0A_EMEM_ACTIVITY_RANGE                       0:0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0A_EMEM_ACTIVITY_WOFFSET                     0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0A_EMEM_ACTIVITY_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0A_EMEM_ACTIVITY_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0A_EMEM_ACTIVITY_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0A_EMEM_ACTIVITY_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0A_EMEM_ACTIVITY_INIT_ENUM                   DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0A_EMEM_ACTIVITY_INACTIVE                    _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0A_EMEM_ACTIVITY_ACTIVE                      _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0AB_EMEM_ACTIVITY_SHIFT                      _MK_SHIFT_CONST(1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0AB_EMEM_ACTIVITY_FIELD                      (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0AB_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0AB_EMEM_ACTIVITY_RANGE                      1:1
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0AB_EMEM_ACTIVITY_WOFFSET                    0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0AB_EMEM_ACTIVITY_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0AB_EMEM_ACTIVITY_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0AB_EMEM_ACTIVITY_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0AB_EMEM_ACTIVITY_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0AB_EMEM_ACTIVITY_INIT_ENUM                  DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0AB_EMEM_ACTIVITY_INACTIVE                   _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0AB_EMEM_ACTIVITY_ACTIVE                     _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0B_EMEM_ACTIVITY_SHIFT                       _MK_SHIFT_CONST(2)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0B_EMEM_ACTIVITY_FIELD                       (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0B_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0B_EMEM_ACTIVITY_RANGE                       2:2
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0B_EMEM_ACTIVITY_WOFFSET                     0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0B_EMEM_ACTIVITY_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0B_EMEM_ACTIVITY_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0B_EMEM_ACTIVITY_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0B_EMEM_ACTIVITY_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0B_EMEM_ACTIVITY_INIT_ENUM                   DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0B_EMEM_ACTIVITY_INACTIVE                    _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0B_EMEM_ACTIVITY_ACTIVE                      _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0BB_EMEM_ACTIVITY_SHIFT                      _MK_SHIFT_CONST(3)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0BB_EMEM_ACTIVITY_FIELD                      (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0BB_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0BB_EMEM_ACTIVITY_RANGE                      3:3
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0BB_EMEM_ACTIVITY_WOFFSET                    0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0BB_EMEM_ACTIVITY_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0BB_EMEM_ACTIVITY_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0BB_EMEM_ACTIVITY_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0BB_EMEM_ACTIVITY_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0BB_EMEM_ACTIVITY_INIT_ENUM                  DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0BB_EMEM_ACTIVITY_INACTIVE                   _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0BB_EMEM_ACTIVITY_ACTIVE                     _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0C_EMEM_ACTIVITY_SHIFT                       _MK_SHIFT_CONST(4)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0C_EMEM_ACTIVITY_FIELD                       (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0C_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0C_EMEM_ACTIVITY_RANGE                       4:4
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0C_EMEM_ACTIVITY_WOFFSET                     0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0C_EMEM_ACTIVITY_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0C_EMEM_ACTIVITY_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0C_EMEM_ACTIVITY_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0C_EMEM_ACTIVITY_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0C_EMEM_ACTIVITY_INIT_ENUM                   DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0C_EMEM_ACTIVITY_INACTIVE                    _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0C_EMEM_ACTIVITY_ACTIVE                      _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0CB_EMEM_ACTIVITY_SHIFT                      _MK_SHIFT_CONST(5)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0CB_EMEM_ACTIVITY_FIELD                      (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0CB_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0CB_EMEM_ACTIVITY_RANGE                      5:5
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0CB_EMEM_ACTIVITY_WOFFSET                    0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0CB_EMEM_ACTIVITY_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0CB_EMEM_ACTIVITY_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0CB_EMEM_ACTIVITY_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0CB_EMEM_ACTIVITY_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0CB_EMEM_ACTIVITY_INIT_ENUM                  DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0CB_EMEM_ACTIVITY_INACTIVE                   _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0CB_EMEM_ACTIVITY_ACTIVE                     _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY1B_EMEM_ACTIVITY_SHIFT                       _MK_SHIFT_CONST(6)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY1B_EMEM_ACTIVITY_FIELD                       (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY1B_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY1B_EMEM_ACTIVITY_RANGE                       6:6
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY1B_EMEM_ACTIVITY_WOFFSET                     0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY1B_EMEM_ACTIVITY_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY1B_EMEM_ACTIVITY_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY1B_EMEM_ACTIVITY_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY1B_EMEM_ACTIVITY_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY1B_EMEM_ACTIVITY_INIT_ENUM                   DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY1B_EMEM_ACTIVITY_INACTIVE                    _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY1B_EMEM_ACTIVITY_ACTIVE                      _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY1BB_EMEM_ACTIVITY_SHIFT                      _MK_SHIFT_CONST(7)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY1BB_EMEM_ACTIVITY_FIELD                      (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY1BB_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY1BB_EMEM_ACTIVITY_RANGE                      7:7
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY1BB_EMEM_ACTIVITY_WOFFSET                    0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY1BB_EMEM_ACTIVITY_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY1BB_EMEM_ACTIVITY_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY1BB_EMEM_ACTIVITY_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY1BB_EMEM_ACTIVITY_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY1BB_EMEM_ACTIVITY_INIT_ENUM                  DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY1BB_EMEM_ACTIVITY_INACTIVE                   _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY1BB_EMEM_ACTIVITY_ACTIVE                     _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_EPPUP_EMEM_ACTIVITY_SHIFT                   _MK_SHIFT_CONST(8)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_EPPUP_EMEM_ACTIVITY_FIELD                   (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_EPPUP_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_EPPUP_EMEM_ACTIVITY_RANGE                   8:8
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_EPPUP_EMEM_ACTIVITY_WOFFSET                 0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_EPPUP_EMEM_ACTIVITY_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_EPPUP_EMEM_ACTIVITY_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_EPPUP_EMEM_ACTIVITY_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_EPPUP_EMEM_ACTIVITY_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_EPPUP_EMEM_ACTIVITY_INIT_ENUM                       DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_EPPUP_EMEM_ACTIVITY_INACTIVE                        _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_EPPUP_EMEM_ACTIVITY_ACTIVE                  _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2PR_EMEM_ACTIVITY_SHIFT                    _MK_SHIFT_CONST(9)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2PR_EMEM_ACTIVITY_FIELD                    (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2PR_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2PR_EMEM_ACTIVITY_RANGE                    9:9
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2PR_EMEM_ACTIVITY_WOFFSET                  0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2PR_EMEM_ACTIVITY_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2PR_EMEM_ACTIVITY_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2PR_EMEM_ACTIVITY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2PR_EMEM_ACTIVITY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2PR_EMEM_ACTIVITY_INIT_ENUM                        DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2PR_EMEM_ACTIVITY_INACTIVE                 _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2PR_EMEM_ACTIVITY_ACTIVE                   _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2SR_EMEM_ACTIVITY_SHIFT                    _MK_SHIFT_CONST(10)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2SR_EMEM_ACTIVITY_FIELD                    (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2SR_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2SR_EMEM_ACTIVITY_RANGE                    10:10
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2SR_EMEM_ACTIVITY_WOFFSET                  0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2SR_EMEM_ACTIVITY_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2SR_EMEM_ACTIVITY_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2SR_EMEM_ACTIVITY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2SR_EMEM_ACTIVITY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2SR_EMEM_ACTIVITY_INIT_ENUM                        DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2SR_EMEM_ACTIVITY_INACTIVE                 _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2SR_EMEM_ACTIVITY_ACTIVE                   _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPEUNIFBR_EMEM_ACTIVITY_SHIFT                       _MK_SHIFT_CONST(11)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPEUNIFBR_EMEM_ACTIVITY_FIELD                       (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPEUNIFBR_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPEUNIFBR_EMEM_ACTIVITY_RANGE                       11:11
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPEUNIFBR_EMEM_ACTIVITY_WOFFSET                     0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPEUNIFBR_EMEM_ACTIVITY_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPEUNIFBR_EMEM_ACTIVITY_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPEUNIFBR_EMEM_ACTIVITY_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPEUNIFBR_EMEM_ACTIVITY_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPEUNIFBR_EMEM_ACTIVITY_INIT_ENUM                   DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPEUNIFBR_EMEM_ACTIVITY_INACTIVE                    _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPEUNIFBR_EMEM_ACTIVITY_ACTIVE                      _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VIRUV_EMEM_ACTIVITY_SHIFT                   _MK_SHIFT_CONST(12)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VIRUV_EMEM_ACTIVITY_FIELD                   (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VIRUV_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VIRUV_EMEM_ACTIVITY_RANGE                   12:12
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VIRUV_EMEM_ACTIVITY_WOFFSET                 0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VIRUV_EMEM_ACTIVITY_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VIRUV_EMEM_ACTIVITY_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VIRUV_EMEM_ACTIVITY_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VIRUV_EMEM_ACTIVITY_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VIRUV_EMEM_ACTIVITY_INIT_ENUM                       DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VIRUV_EMEM_ACTIVITY_INACTIVE                        _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VIRUV_EMEM_ACTIVITY_ACTIVE                  _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_CMCR_EMEM_ACTIVITY_SHIFT                    _MK_SHIFT_CONST(13)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_CMCR_EMEM_ACTIVITY_FIELD                    (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_CMCR_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_CMCR_EMEM_ACTIVITY_RANGE                    13:13
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_CMCR_EMEM_ACTIVITY_WOFFSET                  0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_CMCR_EMEM_ACTIVITY_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_CMCR_EMEM_ACTIVITY_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_CMCR_EMEM_ACTIVITY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_CMCR_EMEM_ACTIVITY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_CMCR_EMEM_ACTIVITY_INIT_ENUM                        DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_CMCR_EMEM_ACTIVITY_INACTIVE                 _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_CMCR_EMEM_ACTIVITY_ACTIVE                   _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAYHC_EMEM_ACTIVITY_SHIFT                       _MK_SHIFT_CONST(14)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAYHC_EMEM_ACTIVITY_FIELD                       (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAYHC_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAYHC_EMEM_ACTIVITY_RANGE                       14:14
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAYHC_EMEM_ACTIVITY_WOFFSET                     0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAYHC_EMEM_ACTIVITY_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAYHC_EMEM_ACTIVITY_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAYHC_EMEM_ACTIVITY_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAYHC_EMEM_ACTIVITY_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAYHC_EMEM_ACTIVITY_INIT_ENUM                   DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAYHC_EMEM_ACTIVITY_INACTIVE                    _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAYHC_EMEM_ACTIVITY_ACTIVE                      _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAYHCB_EMEM_ACTIVITY_SHIFT                      _MK_SHIFT_CONST(15)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAYHCB_EMEM_ACTIVITY_FIELD                      (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAYHCB_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAYHCB_EMEM_ACTIVITY_RANGE                      15:15
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAYHCB_EMEM_ACTIVITY_WOFFSET                    0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAYHCB_EMEM_ACTIVITY_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAYHCB_EMEM_ACTIVITY_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAYHCB_EMEM_ACTIVITY_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAYHCB_EMEM_ACTIVITY_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAYHCB_EMEM_ACTIVITY_INIT_ENUM                  DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAYHCB_EMEM_ACTIVITY_INACTIVE                   _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAYHCB_EMEM_ACTIVITY_ACTIVE                     _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_FDCDRD_EMEM_ACTIVITY_SHIFT                  _MK_SHIFT_CONST(16)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_FDCDRD_EMEM_ACTIVITY_FIELD                  (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_FDCDRD_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_FDCDRD_EMEM_ACTIVITY_RANGE                  16:16
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_FDCDRD_EMEM_ACTIVITY_WOFFSET                        0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_FDCDRD_EMEM_ACTIVITY_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_FDCDRD_EMEM_ACTIVITY_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_FDCDRD_EMEM_ACTIVITY_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_FDCDRD_EMEM_ACTIVITY_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_FDCDRD_EMEM_ACTIVITY_INIT_ENUM                      DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_FDCDRD_EMEM_ACTIVITY_INACTIVE                       _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_FDCDRD_EMEM_ACTIVITY_ACTIVE                 _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2DR_EMEM_ACTIVITY_SHIFT                    _MK_SHIFT_CONST(17)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2DR_EMEM_ACTIVITY_FIELD                    (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2DR_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2DR_EMEM_ACTIVITY_RANGE                    17:17
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2DR_EMEM_ACTIVITY_WOFFSET                  0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2DR_EMEM_ACTIVITY_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2DR_EMEM_ACTIVITY_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2DR_EMEM_ACTIVITY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2DR_EMEM_ACTIVITY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2DR_EMEM_ACTIVITY_INIT_ENUM                        DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2DR_EMEM_ACTIVITY_INACTIVE                 _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2DR_EMEM_ACTIVITY_ACTIVE                   _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_HOST1XDMAR_EMEM_ACTIVITY_SHIFT                      _MK_SHIFT_CONST(18)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_HOST1XDMAR_EMEM_ACTIVITY_FIELD                      (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_HOST1XDMAR_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_HOST1XDMAR_EMEM_ACTIVITY_RANGE                      18:18
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_HOST1XDMAR_EMEM_ACTIVITY_WOFFSET                    0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_HOST1XDMAR_EMEM_ACTIVITY_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_HOST1XDMAR_EMEM_ACTIVITY_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_HOST1XDMAR_EMEM_ACTIVITY_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_HOST1XDMAR_EMEM_ACTIVITY_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_HOST1XDMAR_EMEM_ACTIVITY_INIT_ENUM                  DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_HOST1XDMAR_EMEM_ACTIVITY_INACTIVE                   _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_HOST1XDMAR_EMEM_ACTIVITY_ACTIVE                     _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_HOST1XR_EMEM_ACTIVITY_SHIFT                 _MK_SHIFT_CONST(19)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_HOST1XR_EMEM_ACTIVITY_FIELD                 (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_HOST1XR_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_HOST1XR_EMEM_ACTIVITY_RANGE                 19:19
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_HOST1XR_EMEM_ACTIVITY_WOFFSET                       0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_HOST1XR_EMEM_ACTIVITY_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_HOST1XR_EMEM_ACTIVITY_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_HOST1XR_EMEM_ACTIVITY_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_HOST1XR_EMEM_ACTIVITY_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_HOST1XR_EMEM_ACTIVITY_INIT_ENUM                     DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_HOST1XR_EMEM_ACTIVITY_INACTIVE                      _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_HOST1XR_EMEM_ACTIVITY_ACTIVE                        _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_IDXSRD_EMEM_ACTIVITY_SHIFT                  _MK_SHIFT_CONST(20)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_IDXSRD_EMEM_ACTIVITY_FIELD                  (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_IDXSRD_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_IDXSRD_EMEM_ACTIVITY_RANGE                  20:20
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_IDXSRD_EMEM_ACTIVITY_WOFFSET                        0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_IDXSRD_EMEM_ACTIVITY_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_IDXSRD_EMEM_ACTIVITY_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_IDXSRD_EMEM_ACTIVITY_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_IDXSRD_EMEM_ACTIVITY_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_IDXSRD_EMEM_ACTIVITY_INIT_ENUM                      DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_IDXSRD_EMEM_ACTIVITY_INACTIVE                       _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_IDXSRD_EMEM_ACTIVITY_ACTIVE                 _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPCORER_EMEM_ACTIVITY_SHIFT                 _MK_SHIFT_CONST(21)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPCORER_EMEM_ACTIVITY_FIELD                 (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPCORER_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPCORER_EMEM_ACTIVITY_RANGE                 21:21
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPCORER_EMEM_ACTIVITY_WOFFSET                       0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPCORER_EMEM_ACTIVITY_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPCORER_EMEM_ACTIVITY_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPCORER_EMEM_ACTIVITY_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPCORER_EMEM_ACTIVITY_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPCORER_EMEM_ACTIVITY_INIT_ENUM                     DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPCORER_EMEM_ACTIVITY_INACTIVE                      _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPCORER_EMEM_ACTIVITY_ACTIVE                        _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPE_IPRED_EMEM_ACTIVITY_SHIFT                       _MK_SHIFT_CONST(22)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPE_IPRED_EMEM_ACTIVITY_FIELD                       (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPE_IPRED_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPE_IPRED_EMEM_ACTIVITY_RANGE                       22:22
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPE_IPRED_EMEM_ACTIVITY_WOFFSET                     0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPE_IPRED_EMEM_ACTIVITY_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPE_IPRED_EMEM_ACTIVITY_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPE_IPRED_EMEM_ACTIVITY_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPE_IPRED_EMEM_ACTIVITY_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPE_IPRED_EMEM_ACTIVITY_INIT_ENUM                   DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPE_IPRED_EMEM_ACTIVITY_INACTIVE                    _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPE_IPRED_EMEM_ACTIVITY_ACTIVE                      _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPEAMEMRD_EMEM_ACTIVITY_SHIFT                       _MK_SHIFT_CONST(23)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPEAMEMRD_EMEM_ACTIVITY_FIELD                       (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPEAMEMRD_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPEAMEMRD_EMEM_ACTIVITY_RANGE                       23:23
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPEAMEMRD_EMEM_ACTIVITY_WOFFSET                     0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPEAMEMRD_EMEM_ACTIVITY_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPEAMEMRD_EMEM_ACTIVITY_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPEAMEMRD_EMEM_ACTIVITY_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPEAMEMRD_EMEM_ACTIVITY_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPEAMEMRD_EMEM_ACTIVITY_INIT_ENUM                   DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPEAMEMRD_EMEM_ACTIVITY_INACTIVE                    _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPEAMEMRD_EMEM_ACTIVITY_ACTIVE                      _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPECSRD_EMEM_ACTIVITY_SHIFT                 _MK_SHIFT_CONST(24)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPECSRD_EMEM_ACTIVITY_FIELD                 (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPECSRD_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPECSRD_EMEM_ACTIVITY_RANGE                 24:24
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPECSRD_EMEM_ACTIVITY_WOFFSET                       0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPECSRD_EMEM_ACTIVITY_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPECSRD_EMEM_ACTIVITY_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPECSRD_EMEM_ACTIVITY_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPECSRD_EMEM_ACTIVITY_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPECSRD_EMEM_ACTIVITY_INIT_ENUM                     DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPECSRD_EMEM_ACTIVITY_INACTIVE                      _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPECSRD_EMEM_ACTIVITY_ACTIVE                        _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_PPCSAHBDMAR_EMEM_ACTIVITY_SHIFT                     _MK_SHIFT_CONST(25)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_PPCSAHBDMAR_EMEM_ACTIVITY_FIELD                     (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_PPCSAHBDMAR_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_PPCSAHBDMAR_EMEM_ACTIVITY_RANGE                     25:25
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_PPCSAHBDMAR_EMEM_ACTIVITY_WOFFSET                   0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_PPCSAHBDMAR_EMEM_ACTIVITY_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_PPCSAHBDMAR_EMEM_ACTIVITY_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_PPCSAHBDMAR_EMEM_ACTIVITY_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_PPCSAHBDMAR_EMEM_ACTIVITY_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_PPCSAHBDMAR_EMEM_ACTIVITY_INIT_ENUM                 DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_PPCSAHBDMAR_EMEM_ACTIVITY_INACTIVE                  _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_PPCSAHBDMAR_EMEM_ACTIVITY_ACTIVE                    _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_PPCSAHBSLVR_EMEM_ACTIVITY_SHIFT                     _MK_SHIFT_CONST(26)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_PPCSAHBSLVR_EMEM_ACTIVITY_FIELD                     (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_PPCSAHBSLVR_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_PPCSAHBSLVR_EMEM_ACTIVITY_RANGE                     26:26
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_PPCSAHBSLVR_EMEM_ACTIVITY_WOFFSET                   0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_PPCSAHBSLVR_EMEM_ACTIVITY_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_PPCSAHBSLVR_EMEM_ACTIVITY_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_PPCSAHBSLVR_EMEM_ACTIVITY_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_PPCSAHBSLVR_EMEM_ACTIVITY_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_PPCSAHBSLVR_EMEM_ACTIVITY_INIT_ENUM                 DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_PPCSAHBSLVR_EMEM_ACTIVITY_INACTIVE                  _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_PPCSAHBSLVR_EMEM_ACTIVITY_ACTIVE                    _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_PPCSARM7R_EMEM_ACTIVITY_SHIFT                       _MK_SHIFT_CONST(27)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_PPCSARM7R_EMEM_ACTIVITY_FIELD                       (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_PPCSARM7R_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_PPCSARM7R_EMEM_ACTIVITY_RANGE                       27:27
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_PPCSARM7R_EMEM_ACTIVITY_WOFFSET                     0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_PPCSARM7R_EMEM_ACTIVITY_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_PPCSARM7R_EMEM_ACTIVITY_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_PPCSARM7R_EMEM_ACTIVITY_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_PPCSARM7R_EMEM_ACTIVITY_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_PPCSARM7R_EMEM_ACTIVITY_INIT_ENUM                   DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_PPCSARM7R_EMEM_ACTIVITY_INACTIVE                    _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_PPCSARM7R_EMEM_ACTIVITY_ACTIVE                      _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_TEXSRD_EMEM_ACTIVITY_SHIFT                  _MK_SHIFT_CONST(28)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_TEXSRD_EMEM_ACTIVITY_FIELD                  (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_TEXSRD_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_TEXSRD_EMEM_ACTIVITY_RANGE                  28:28
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_TEXSRD_EMEM_ACTIVITY_WOFFSET                        0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_TEXSRD_EMEM_ACTIVITY_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_TEXSRD_EMEM_ACTIVITY_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_TEXSRD_EMEM_ACTIVITY_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_TEXSRD_EMEM_ACTIVITY_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_TEXSRD_EMEM_ACTIVITY_INIT_ENUM                      DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_TEXSRD_EMEM_ACTIVITY_INACTIVE                       _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_TEXSRD_EMEM_ACTIVITY_ACTIVE                 _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEBSEAR_EMEM_ACTIVITY_SHIFT                        _MK_SHIFT_CONST(29)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEBSEAR_EMEM_ACTIVITY_FIELD                        (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEBSEAR_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEBSEAR_EMEM_ACTIVITY_RANGE                        29:29
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEBSEAR_EMEM_ACTIVITY_WOFFSET                      0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEBSEAR_EMEM_ACTIVITY_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEBSEAR_EMEM_ACTIVITY_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEBSEAR_EMEM_ACTIVITY_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEBSEAR_EMEM_ACTIVITY_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEBSEAR_EMEM_ACTIVITY_INIT_ENUM                    DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEBSEAR_EMEM_ACTIVITY_INACTIVE                     _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEBSEAR_EMEM_ACTIVITY_ACTIVE                       _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEBSEVR_EMEM_ACTIVITY_SHIFT                        _MK_SHIFT_CONST(30)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEBSEVR_EMEM_ACTIVITY_FIELD                        (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEBSEVR_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEBSEVR_EMEM_ACTIVITY_RANGE                        30:30
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEBSEVR_EMEM_ACTIVITY_WOFFSET                      0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEBSEVR_EMEM_ACTIVITY_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEBSEVR_EMEM_ACTIVITY_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEBSEVR_EMEM_ACTIVITY_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEBSEVR_EMEM_ACTIVITY_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEBSEVR_EMEM_ACTIVITY_INIT_ENUM                    DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEBSEVR_EMEM_ACTIVITY_INACTIVE                     _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEBSEVR_EMEM_ACTIVITY_ACTIVE                       _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEMBER_EMEM_ACTIVITY_SHIFT                 _MK_SHIFT_CONST(31)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEMBER_EMEM_ACTIVITY_FIELD                 (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEMBER_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEMBER_EMEM_ACTIVITY_RANGE                 31:31
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEMBER_EMEM_ACTIVITY_WOFFSET                       0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEMBER_EMEM_ACTIVITY_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEMBER_EMEM_ACTIVITY_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEMBER_EMEM_ACTIVITY_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEMBER_EMEM_ACTIVITY_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEMBER_EMEM_ACTIVITY_INIT_ENUM                     DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEMBER_EMEM_ACTIVITY_INACTIVE                      _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEMBER_EMEM_ACTIVITY_ACTIVE                        _MK_ENUM_CONST(1)
+
+
+// Register MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0  
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0                     _MK_ADDR_CONST(0x1fc)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_WORD_COUNT                  0x1
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_RESET_MASK                  _MK_MASK_CONST(0xffffff)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_READ_MASK                   _MK_MASK_CONST(0xffffff)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_WRITE_MASK                  _MK_MASK_CONST(0xffffff)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEMCER_EMEM_ACTIVITY_SHIFT                 _MK_SHIFT_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEMCER_EMEM_ACTIVITY_FIELD                 (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEMCER_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEMCER_EMEM_ACTIVITY_RANGE                 0:0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEMCER_EMEM_ACTIVITY_WOFFSET                       0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEMCER_EMEM_ACTIVITY_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEMCER_EMEM_ACTIVITY_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEMCER_EMEM_ACTIVITY_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEMCER_EMEM_ACTIVITY_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEMCER_EMEM_ACTIVITY_INIT_ENUM                     DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEMCER_EMEM_ACTIVITY_INACTIVE                      _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEMCER_EMEM_ACTIVITY_ACTIVE                        _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDETPER_EMEM_ACTIVITY_SHIFT                 _MK_SHIFT_CONST(1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDETPER_EMEM_ACTIVITY_FIELD                 (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDETPER_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDETPER_EMEM_ACTIVITY_RANGE                 1:1
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDETPER_EMEM_ACTIVITY_WOFFSET                       0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDETPER_EMEM_ACTIVITY_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDETPER_EMEM_ACTIVITY_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDETPER_EMEM_ACTIVITY_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDETPER_EMEM_ACTIVITY_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDETPER_EMEM_ACTIVITY_INIT_ENUM                     DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDETPER_EMEM_ACTIVITY_INACTIVE                      _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDETPER_EMEM_ACTIVITY_ACTIVE                        _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPU_EMEM_ACTIVITY_SHIFT                    _MK_SHIFT_CONST(2)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPU_EMEM_ACTIVITY_FIELD                    (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPU_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPU_EMEM_ACTIVITY_RANGE                    2:2
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPU_EMEM_ACTIVITY_WOFFSET                  0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPU_EMEM_ACTIVITY_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPU_EMEM_ACTIVITY_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPU_EMEM_ACTIVITY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPU_EMEM_ACTIVITY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPU_EMEM_ACTIVITY_INIT_ENUM                        DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPU_EMEM_ACTIVITY_INACTIVE                 _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPU_EMEM_ACTIVITY_ACTIVE                   _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPV_EMEM_ACTIVITY_SHIFT                    _MK_SHIFT_CONST(3)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPV_EMEM_ACTIVITY_FIELD                    (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPV_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPV_EMEM_ACTIVITY_RANGE                    3:3
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPV_EMEM_ACTIVITY_WOFFSET                  0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPV_EMEM_ACTIVITY_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPV_EMEM_ACTIVITY_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPV_EMEM_ACTIVITY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPV_EMEM_ACTIVITY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPV_EMEM_ACTIVITY_INIT_ENUM                        DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPV_EMEM_ACTIVITY_INACTIVE                 _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPV_EMEM_ACTIVITY_ACTIVE                   _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPY_EMEM_ACTIVITY_SHIFT                    _MK_SHIFT_CONST(4)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPY_EMEM_ACTIVITY_FIELD                    (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPY_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPY_EMEM_ACTIVITY_RANGE                    4:4
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPY_EMEM_ACTIVITY_WOFFSET                  0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPY_EMEM_ACTIVITY_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPY_EMEM_ACTIVITY_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPY_EMEM_ACTIVITY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPY_EMEM_ACTIVITY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPY_EMEM_ACTIVITY_INIT_ENUM                        DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPY_EMEM_ACTIVITY_INACTIVE                 _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPY_EMEM_ACTIVITY_ACTIVE                   _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPEUNIFBW_EMEM_ACTIVITY_SHIFT                       _MK_SHIFT_CONST(5)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPEUNIFBW_EMEM_ACTIVITY_FIELD                       (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPEUNIFBW_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPEUNIFBW_EMEM_ACTIVITY_RANGE                       5:5
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPEUNIFBW_EMEM_ACTIVITY_WOFFSET                     0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPEUNIFBW_EMEM_ACTIVITY_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPEUNIFBW_EMEM_ACTIVITY_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPEUNIFBW_EMEM_ACTIVITY_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPEUNIFBW_EMEM_ACTIVITY_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPEUNIFBW_EMEM_ACTIVITY_INIT_ENUM                   DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPEUNIFBW_EMEM_ACTIVITY_INACTIVE                    _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPEUNIFBW_EMEM_ACTIVITY_ACTIVE                      _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWSB_EMEM_ACTIVITY_SHIFT                   _MK_SHIFT_CONST(6)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWSB_EMEM_ACTIVITY_FIELD                   (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWSB_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWSB_EMEM_ACTIVITY_RANGE                   6:6
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWSB_EMEM_ACTIVITY_WOFFSET                 0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWSB_EMEM_ACTIVITY_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWSB_EMEM_ACTIVITY_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWSB_EMEM_ACTIVITY_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWSB_EMEM_ACTIVITY_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWSB_EMEM_ACTIVITY_INIT_ENUM                       DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWSB_EMEM_ACTIVITY_INACTIVE                        _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWSB_EMEM_ACTIVITY_ACTIVE                  _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWU_EMEM_ACTIVITY_SHIFT                    _MK_SHIFT_CONST(7)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWU_EMEM_ACTIVITY_FIELD                    (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWU_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWU_EMEM_ACTIVITY_RANGE                    7:7
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWU_EMEM_ACTIVITY_WOFFSET                  0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWU_EMEM_ACTIVITY_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWU_EMEM_ACTIVITY_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWU_EMEM_ACTIVITY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWU_EMEM_ACTIVITY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWU_EMEM_ACTIVITY_INIT_ENUM                        DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWU_EMEM_ACTIVITY_INACTIVE                 _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWU_EMEM_ACTIVITY_ACTIVE                   _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWV_EMEM_ACTIVITY_SHIFT                    _MK_SHIFT_CONST(8)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWV_EMEM_ACTIVITY_FIELD                    (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWV_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWV_EMEM_ACTIVITY_RANGE                    8:8
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWV_EMEM_ACTIVITY_WOFFSET                  0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWV_EMEM_ACTIVITY_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWV_EMEM_ACTIVITY_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWV_EMEM_ACTIVITY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWV_EMEM_ACTIVITY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWV_EMEM_ACTIVITY_INIT_ENUM                        DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWV_EMEM_ACTIVITY_INACTIVE                 _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWV_EMEM_ACTIVITY_ACTIVE                   _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWY_EMEM_ACTIVITY_SHIFT                    _MK_SHIFT_CONST(9)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWY_EMEM_ACTIVITY_FIELD                    (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWY_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWY_EMEM_ACTIVITY_RANGE                    9:9
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWY_EMEM_ACTIVITY_WOFFSET                  0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWY_EMEM_ACTIVITY_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWY_EMEM_ACTIVITY_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWY_EMEM_ACTIVITY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWY_EMEM_ACTIVITY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWY_EMEM_ACTIVITY_INIT_ENUM                        DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWY_EMEM_ACTIVITY_INACTIVE                 _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWY_EMEM_ACTIVITY_ACTIVE                   _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_G2DW_EMEM_ACTIVITY_SHIFT                    _MK_SHIFT_CONST(10)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_G2DW_EMEM_ACTIVITY_FIELD                    (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_G2DW_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_G2DW_EMEM_ACTIVITY_RANGE                    10:10
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_G2DW_EMEM_ACTIVITY_WOFFSET                  0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_G2DW_EMEM_ACTIVITY_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_G2DW_EMEM_ACTIVITY_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_G2DW_EMEM_ACTIVITY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_G2DW_EMEM_ACTIVITY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_G2DW_EMEM_ACTIVITY_INIT_ENUM                        DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_G2DW_EMEM_ACTIVITY_INACTIVE                 _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_G2DW_EMEM_ACTIVITY_ACTIVE                   _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_CMCW_EMEM_ACTIVITY_SHIFT                    _MK_SHIFT_CONST(11)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_CMCW_EMEM_ACTIVITY_FIELD                    (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_CMCW_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_CMCW_EMEM_ACTIVITY_RANGE                    11:11
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_CMCW_EMEM_ACTIVITY_WOFFSET                  0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_CMCW_EMEM_ACTIVITY_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_CMCW_EMEM_ACTIVITY_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_CMCW_EMEM_ACTIVITY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_CMCW_EMEM_ACTIVITY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_CMCW_EMEM_ACTIVITY_INIT_ENUM                        DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_CMCW_EMEM_ACTIVITY_INACTIVE                 _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_CMCW_EMEM_ACTIVITY_ACTIVE                   _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_FDCDWR_EMEM_ACTIVITY_SHIFT                  _MK_SHIFT_CONST(12)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_FDCDWR_EMEM_ACTIVITY_FIELD                  (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_FDCDWR_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_FDCDWR_EMEM_ACTIVITY_RANGE                  12:12
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_FDCDWR_EMEM_ACTIVITY_WOFFSET                        0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_FDCDWR_EMEM_ACTIVITY_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_FDCDWR_EMEM_ACTIVITY_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_FDCDWR_EMEM_ACTIVITY_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_FDCDWR_EMEM_ACTIVITY_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_FDCDWR_EMEM_ACTIVITY_INIT_ENUM                      DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_FDCDWR_EMEM_ACTIVITY_INACTIVE                       _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_FDCDWR_EMEM_ACTIVITY_ACTIVE                 _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_HOST1XW_EMEM_ACTIVITY_SHIFT                 _MK_SHIFT_CONST(13)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_HOST1XW_EMEM_ACTIVITY_FIELD                 (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_HOST1XW_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_HOST1XW_EMEM_ACTIVITY_RANGE                 13:13
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_HOST1XW_EMEM_ACTIVITY_WOFFSET                       0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_HOST1XW_EMEM_ACTIVITY_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_HOST1XW_EMEM_ACTIVITY_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_HOST1XW_EMEM_ACTIVITY_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_HOST1XW_EMEM_ACTIVITY_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_HOST1XW_EMEM_ACTIVITY_INIT_ENUM                     DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_HOST1XW_EMEM_ACTIVITY_INACTIVE                      _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_HOST1XW_EMEM_ACTIVITY_ACTIVE                        _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_ISPW_EMEM_ACTIVITY_SHIFT                    _MK_SHIFT_CONST(14)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_ISPW_EMEM_ACTIVITY_FIELD                    (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_ISPW_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_ISPW_EMEM_ACTIVITY_RANGE                    14:14
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_ISPW_EMEM_ACTIVITY_WOFFSET                  0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_ISPW_EMEM_ACTIVITY_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_ISPW_EMEM_ACTIVITY_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_ISPW_EMEM_ACTIVITY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_ISPW_EMEM_ACTIVITY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_ISPW_EMEM_ACTIVITY_INIT_ENUM                        DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_ISPW_EMEM_ACTIVITY_INACTIVE                 _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_ISPW_EMEM_ACTIVITY_ACTIVE                   _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPCOREW_EMEM_ACTIVITY_SHIFT                 _MK_SHIFT_CONST(15)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPCOREW_EMEM_ACTIVITY_FIELD                 (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPCOREW_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPCOREW_EMEM_ACTIVITY_RANGE                 15:15
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPCOREW_EMEM_ACTIVITY_WOFFSET                       0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPCOREW_EMEM_ACTIVITY_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPCOREW_EMEM_ACTIVITY_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPCOREW_EMEM_ACTIVITY_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPCOREW_EMEM_ACTIVITY_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPCOREW_EMEM_ACTIVITY_INIT_ENUM                     DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPCOREW_EMEM_ACTIVITY_INACTIVE                      _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPCOREW_EMEM_ACTIVITY_ACTIVE                        _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPECSWR_EMEM_ACTIVITY_SHIFT                 _MK_SHIFT_CONST(16)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPECSWR_EMEM_ACTIVITY_FIELD                 (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPECSWR_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPECSWR_EMEM_ACTIVITY_RANGE                 16:16
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPECSWR_EMEM_ACTIVITY_WOFFSET                       0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPECSWR_EMEM_ACTIVITY_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPECSWR_EMEM_ACTIVITY_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPECSWR_EMEM_ACTIVITY_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPECSWR_EMEM_ACTIVITY_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPECSWR_EMEM_ACTIVITY_INIT_ENUM                     DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPECSWR_EMEM_ACTIVITY_INACTIVE                      _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPECSWR_EMEM_ACTIVITY_ACTIVE                        _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_PPCSAHBDMAW_EMEM_ACTIVITY_SHIFT                     _MK_SHIFT_CONST(17)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_PPCSAHBDMAW_EMEM_ACTIVITY_FIELD                     (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_PPCSAHBDMAW_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_PPCSAHBDMAW_EMEM_ACTIVITY_RANGE                     17:17
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_PPCSAHBDMAW_EMEM_ACTIVITY_WOFFSET                   0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_PPCSAHBDMAW_EMEM_ACTIVITY_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_PPCSAHBDMAW_EMEM_ACTIVITY_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_PPCSAHBDMAW_EMEM_ACTIVITY_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_PPCSAHBDMAW_EMEM_ACTIVITY_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_PPCSAHBDMAW_EMEM_ACTIVITY_INIT_ENUM                 DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_PPCSAHBDMAW_EMEM_ACTIVITY_INACTIVE                  _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_PPCSAHBDMAW_EMEM_ACTIVITY_ACTIVE                    _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_PPCSAHBSLVW_EMEM_ACTIVITY_SHIFT                     _MK_SHIFT_CONST(18)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_PPCSAHBSLVW_EMEM_ACTIVITY_FIELD                     (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_PPCSAHBSLVW_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_PPCSAHBSLVW_EMEM_ACTIVITY_RANGE                     18:18
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_PPCSAHBSLVW_EMEM_ACTIVITY_WOFFSET                   0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_PPCSAHBSLVW_EMEM_ACTIVITY_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_PPCSAHBSLVW_EMEM_ACTIVITY_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_PPCSAHBSLVW_EMEM_ACTIVITY_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_PPCSAHBSLVW_EMEM_ACTIVITY_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_PPCSAHBSLVW_EMEM_ACTIVITY_INIT_ENUM                 DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_PPCSAHBSLVW_EMEM_ACTIVITY_INACTIVE                  _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_PPCSAHBSLVW_EMEM_ACTIVITY_ACTIVE                    _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_PPCSARM7W_EMEM_ACTIVITY_SHIFT                       _MK_SHIFT_CONST(19)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_PPCSARM7W_EMEM_ACTIVITY_FIELD                       (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_PPCSARM7W_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_PPCSARM7W_EMEM_ACTIVITY_RANGE                       19:19
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_PPCSARM7W_EMEM_ACTIVITY_WOFFSET                     0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_PPCSARM7W_EMEM_ACTIVITY_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_PPCSARM7W_EMEM_ACTIVITY_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_PPCSARM7W_EMEM_ACTIVITY_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_PPCSARM7W_EMEM_ACTIVITY_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_PPCSARM7W_EMEM_ACTIVITY_INIT_ENUM                   DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_PPCSARM7W_EMEM_ACTIVITY_INACTIVE                    _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_PPCSARM7W_EMEM_ACTIVITY_ACTIVE                      _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEBSEAW_EMEM_ACTIVITY_SHIFT                        _MK_SHIFT_CONST(20)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEBSEAW_EMEM_ACTIVITY_FIELD                        (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEBSEAW_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEBSEAW_EMEM_ACTIVITY_RANGE                        20:20
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEBSEAW_EMEM_ACTIVITY_WOFFSET                      0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEBSEAW_EMEM_ACTIVITY_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEBSEAW_EMEM_ACTIVITY_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEBSEAW_EMEM_ACTIVITY_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEBSEAW_EMEM_ACTIVITY_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEBSEAW_EMEM_ACTIVITY_INIT_ENUM                    DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEBSEAW_EMEM_ACTIVITY_INACTIVE                     _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEBSEAW_EMEM_ACTIVITY_ACTIVE                       _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEBSEVW_EMEM_ACTIVITY_SHIFT                        _MK_SHIFT_CONST(21)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEBSEVW_EMEM_ACTIVITY_FIELD                        (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEBSEVW_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEBSEVW_EMEM_ACTIVITY_RANGE                        21:21
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEBSEVW_EMEM_ACTIVITY_WOFFSET                      0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEBSEVW_EMEM_ACTIVITY_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEBSEVW_EMEM_ACTIVITY_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEBSEVW_EMEM_ACTIVITY_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEBSEVW_EMEM_ACTIVITY_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEBSEVW_EMEM_ACTIVITY_INIT_ENUM                    DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEBSEVW_EMEM_ACTIVITY_INACTIVE                     _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEBSEVW_EMEM_ACTIVITY_ACTIVE                       _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEMBEW_EMEM_ACTIVITY_SHIFT                 _MK_SHIFT_CONST(22)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEMBEW_EMEM_ACTIVITY_FIELD                 (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEMBEW_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEMBEW_EMEM_ACTIVITY_RANGE                 22:22
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEMBEW_EMEM_ACTIVITY_WOFFSET                       0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEMBEW_EMEM_ACTIVITY_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEMBEW_EMEM_ACTIVITY_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEMBEW_EMEM_ACTIVITY_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEMBEW_EMEM_ACTIVITY_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEMBEW_EMEM_ACTIVITY_INIT_ENUM                     DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEMBEW_EMEM_ACTIVITY_INACTIVE                      _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEMBEW_EMEM_ACTIVITY_ACTIVE                        _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDETPMW_EMEM_ACTIVITY_SHIFT                 _MK_SHIFT_CONST(23)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDETPMW_EMEM_ACTIVITY_FIELD                 (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDETPMW_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDETPMW_EMEM_ACTIVITY_RANGE                 23:23
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDETPMW_EMEM_ACTIVITY_WOFFSET                       0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDETPMW_EMEM_ACTIVITY_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDETPMW_EMEM_ACTIVITY_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDETPMW_EMEM_ACTIVITY_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDETPMW_EMEM_ACTIVITY_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDETPMW_EMEM_ACTIVITY_INIT_ENUM                     DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDETPMW_EMEM_ACTIVITY_INACTIVE                      _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDETPMW_EMEM_ACTIVITY_ACTIVE                        _MK_ENUM_CONST(1)
+
+#define NV_MC_EMEM_DFIFO_DEPTH  3
+#define NV_MC_IMEM_DFIFO_DEPTH  5
+#define NV_MC_EMEM_APFIFO_DEPTH 4
+#define NV_MC_ARB_EMEM_REGLEVEL 3
+#define NV_MC_EMEM_REQ_ID_WIDEREQ       9
+#define NV_MC_EMEM_RDI_ID_WIDERDI       9
+#define NV_MC_EMEM_REQ_ID_ILLEGALACC    8
+#define NV_MC_EMEM_RDI_ID_ILLEGALACC    8
+#define NV_MC_EMEM_REQ_ID_LLRAWDECR     7
+#define NV_MC_EMEM_RDI_ID_LLRAWDECR     7
+#define NV_MC_EMEM_REQ_ID_APCIGNORE     6
+#define NV_MC_EMEM_RDI_ID_APCIGNORE     6
+
+// Packet MC2EMC
+#define MC2EMC_SIZE 190
+
+#define MC2EMC_WDO_SHIFT                        _MK_SHIFT_CONST(0)
+#define MC2EMC_WDO_FIELD                        (_MK_MASK_CONST(0xffffffff) << MC2EMC_WDO_SHIFT)
+#define MC2EMC_WDO_RANGE                        _MK_SHIFT_CONST(127):_MK_SHIFT_CONST(0)
+#define MC2EMC_WDO_ROW                  0
+
+#define MC2EMC_WDO_0_SHIFT                      _MK_SHIFT_CONST(0)
+#define MC2EMC_WDO_0_FIELD                      (_MK_MASK_CONST(0xffffffff) << MC2EMC_WDO_0_SHIFT)
+#define MC2EMC_WDO_0_RANGE                      _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define MC2EMC_WDO_0_ROW                        0
+
+#define MC2EMC_WDO_1_SHIFT                      _MK_SHIFT_CONST(32)
+#define MC2EMC_WDO_1_FIELD                      (_MK_MASK_CONST(0xffffffff) << MC2EMC_WDO_1_SHIFT)
+#define MC2EMC_WDO_1_RANGE                      _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(32)
+#define MC2EMC_WDO_1_ROW                        0
+
+#define MC2EMC_WDO_2_SHIFT                      _MK_SHIFT_CONST(64)
+#define MC2EMC_WDO_2_FIELD                      (_MK_MASK_CONST(0xffffffff) << MC2EMC_WDO_2_SHIFT)
+#define MC2EMC_WDO_2_RANGE                      _MK_SHIFT_CONST(95):_MK_SHIFT_CONST(64)
+#define MC2EMC_WDO_2_ROW                        0
+
+#define MC2EMC_WDO_3_SHIFT                      _MK_SHIFT_CONST(96)
+#define MC2EMC_WDO_3_FIELD                      (_MK_MASK_CONST(0xffffffff) << MC2EMC_WDO_3_SHIFT)
+#define MC2EMC_WDO_3_RANGE                      _MK_SHIFT_CONST(127):_MK_SHIFT_CONST(96)
+#define MC2EMC_WDO_3_ROW                        0
+
+#define MC2EMC_BE_SHIFT                 _MK_SHIFT_CONST(128)
+#define MC2EMC_BE_FIELD                 (_MK_MASK_CONST(0xffff) << MC2EMC_BE_SHIFT)
+#define MC2EMC_BE_RANGE                 _MK_SHIFT_CONST(143):_MK_SHIFT_CONST(128)
+#define MC2EMC_BE_ROW                   0
+
+#define MC2EMC_DEV_SHIFT                        _MK_SHIFT_CONST(144)
+#define MC2EMC_DEV_FIELD                        (_MK_MASK_CONST(0x3) << MC2EMC_DEV_SHIFT)
+#define MC2EMC_DEV_RANGE                        _MK_SHIFT_CONST(145):_MK_SHIFT_CONST(144)
+#define MC2EMC_DEV_ROW                  0
+
+#define MC2EMC_BANK_SHIFT                       _MK_SHIFT_CONST(146)
+#define MC2EMC_BANK_FIELD                       (_MK_MASK_CONST(0x3) << MC2EMC_BANK_SHIFT)
+#define MC2EMC_BANK_RANGE                       _MK_SHIFT_CONST(147):_MK_SHIFT_CONST(146)
+#define MC2EMC_BANK_ROW                 0
+
+#define MC2EMC_ROW_SHIFT                        _MK_SHIFT_CONST(148)
+#define MC2EMC_ROW_FIELD                        (_MK_MASK_CONST(0x3fff) << MC2EMC_ROW_SHIFT)
+#define MC2EMC_ROW_RANGE                        _MK_SHIFT_CONST(161):_MK_SHIFT_CONST(148)
+#define MC2EMC_ROW_ROW                  0
+
+#define MC2EMC_COL_SHIFT                        _MK_SHIFT_CONST(162)
+#define MC2EMC_COL_FIELD                        (_MK_MASK_CONST(0x7ff) << MC2EMC_COL_SHIFT)
+#define MC2EMC_COL_RANGE                        _MK_SHIFT_CONST(172):_MK_SHIFT_CONST(162)
+#define MC2EMC_COL_ROW                  0
+
+#define MC2EMC_REQ_ID_SHIFT                     _MK_SHIFT_CONST(173)
+#define MC2EMC_REQ_ID_FIELD                     (_MK_MASK_CONST(0x3ff) << MC2EMC_REQ_ID_SHIFT)
+#define MC2EMC_REQ_ID_RANGE                     _MK_SHIFT_CONST(182):_MK_SHIFT_CONST(173)
+#define MC2EMC_REQ_ID_ROW                       0
+
+#define MC2EMC_AP_SHIFT                 _MK_SHIFT_CONST(183)
+#define MC2EMC_AP_FIELD                 (_MK_MASK_CONST(0x1) << MC2EMC_AP_SHIFT)
+#define MC2EMC_AP_RANGE                 _MK_SHIFT_CONST(183):_MK_SHIFT_CONST(183)
+#define MC2EMC_AP_ROW                   0
+
+#define MC2EMC_WE_SHIFT                 _MK_SHIFT_CONST(184)
+#define MC2EMC_WE_FIELD                 (_MK_MASK_CONST(0x1) << MC2EMC_WE_SHIFT)
+#define MC2EMC_WE_RANGE                 _MK_SHIFT_CONST(184):_MK_SHIFT_CONST(184)
+#define MC2EMC_WE_ROW                   0
+
+#define MC2EMC_TAG_SHIFT                        _MK_SHIFT_CONST(185)
+#define MC2EMC_TAG_FIELD                        (_MK_MASK_CONST(0x1f) << MC2EMC_TAG_SHIFT)
+#define MC2EMC_TAG_RANGE                        _MK_SHIFT_CONST(189):_MK_SHIFT_CONST(185)
+#define MC2EMC_TAG_ROW                  0
+
+
+// Packet MC2EMC_APC
+#define MC2EMC_APC_SIZE 3
+
+#define MC2EMC_APC_CLR_SHIFT                    _MK_SHIFT_CONST(0)
+#define MC2EMC_APC_CLR_FIELD                    (_MK_MASK_CONST(0x1) << MC2EMC_APC_CLR_SHIFT)
+#define MC2EMC_APC_CLR_RANGE                    _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define MC2EMC_APC_CLR_ROW                      0
+
+#define MC2EMC_APC_BANK_SHIFT                   _MK_SHIFT_CONST(1)
+#define MC2EMC_APC_BANK_FIELD                   (_MK_MASK_CONST(0x3) << MC2EMC_APC_BANK_SHIFT)
+#define MC2EMC_APC_BANK_RANGE                   _MK_SHIFT_CONST(2):_MK_SHIFT_CONST(1)
+#define MC2EMC_APC_BANK_ROW                     0
+
+
+// Packet EMC2MC
+#define EMC2MC_SIZE 138
+
+#define EMC2MC_RDI_SHIFT                        _MK_SHIFT_CONST(0)
+#define EMC2MC_RDI_FIELD                        (_MK_MASK_CONST(0xffffffff) << EMC2MC_RDI_SHIFT)
+#define EMC2MC_RDI_RANGE                        _MK_SHIFT_CONST(127):_MK_SHIFT_CONST(0)
+#define EMC2MC_RDI_ROW                  0
+
+#define EMC2MC_RDI_0_SHIFT                      _MK_SHIFT_CONST(0)
+#define EMC2MC_RDI_0_FIELD                      (_MK_MASK_CONST(0xffffffff) << EMC2MC_RDI_0_SHIFT)
+#define EMC2MC_RDI_0_RANGE                      _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define EMC2MC_RDI_0_ROW                        0
+
+#define EMC2MC_RDI_1_SHIFT                      _MK_SHIFT_CONST(32)
+#define EMC2MC_RDI_1_FIELD                      (_MK_MASK_CONST(0xffffffff) << EMC2MC_RDI_1_SHIFT)
+#define EMC2MC_RDI_1_RANGE                      _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(32)
+#define EMC2MC_RDI_1_ROW                        0
+
+#define EMC2MC_RDI_2_SHIFT                      _MK_SHIFT_CONST(64)
+#define EMC2MC_RDI_2_FIELD                      (_MK_MASK_CONST(0xffffffff) << EMC2MC_RDI_2_SHIFT)
+#define EMC2MC_RDI_2_RANGE                      _MK_SHIFT_CONST(95):_MK_SHIFT_CONST(64)
+#define EMC2MC_RDI_2_ROW                        0
+
+#define EMC2MC_RDI_3_SHIFT                      _MK_SHIFT_CONST(96)
+#define EMC2MC_RDI_3_FIELD                      (_MK_MASK_CONST(0xffffffff) << EMC2MC_RDI_3_SHIFT)
+#define EMC2MC_RDI_3_RANGE                      _MK_SHIFT_CONST(127):_MK_SHIFT_CONST(96)
+#define EMC2MC_RDI_3_ROW                        0
+
+#define EMC2MC_RDI_ID_SHIFT                     _MK_SHIFT_CONST(128)
+#define EMC2MC_RDI_ID_FIELD                     (_MK_MASK_CONST(0x3ff) << EMC2MC_RDI_ID_SHIFT)
+#define EMC2MC_RDI_ID_RANGE                     _MK_SHIFT_CONST(137):_MK_SHIFT_CONST(128)
+#define EMC2MC_RDI_ID_ROW                       0
+
+
+// Packet MC2EMC_LL
+#define MC2EMC_LL_SIZE 35
+
+#define MC2EMC_LL_DEV_SHIFT                     _MK_SHIFT_CONST(0)
+#define MC2EMC_LL_DEV_FIELD                     (_MK_MASK_CONST(0x3) << MC2EMC_LL_DEV_SHIFT)
+#define MC2EMC_LL_DEV_RANGE                     _MK_SHIFT_CONST(1):_MK_SHIFT_CONST(0)
+#define MC2EMC_LL_DEV_ROW                       0
+
+#define MC2EMC_LL_BANK_SHIFT                    _MK_SHIFT_CONST(2)
+#define MC2EMC_LL_BANK_FIELD                    (_MK_MASK_CONST(0x3) << MC2EMC_LL_BANK_SHIFT)
+#define MC2EMC_LL_BANK_RANGE                    _MK_SHIFT_CONST(3):_MK_SHIFT_CONST(2)
+#define MC2EMC_LL_BANK_ROW                      0
+
+#define MC2EMC_LL_ROW_SHIFT                     _MK_SHIFT_CONST(4)
+#define MC2EMC_LL_ROW_FIELD                     (_MK_MASK_CONST(0x3fff) << MC2EMC_LL_ROW_SHIFT)
+#define MC2EMC_LL_ROW_RANGE                     _MK_SHIFT_CONST(17):_MK_SHIFT_CONST(4)
+#define MC2EMC_LL_ROW_ROW                       0
+
+#define MC2EMC_LL_COL_SHIFT                     _MK_SHIFT_CONST(18)
+#define MC2EMC_LL_COL_FIELD                     (_MK_MASK_CONST(0x7ff) << MC2EMC_LL_COL_SHIFT)
+#define MC2EMC_LL_COL_RANGE                     _MK_SHIFT_CONST(28):_MK_SHIFT_CONST(18)
+#define MC2EMC_LL_COL_ROW                       0
+
+#define MC2EMC_LL_TAG_SHIFT                     _MK_SHIFT_CONST(29)
+#define MC2EMC_LL_TAG_FIELD                     (_MK_MASK_CONST(0x1f) << MC2EMC_LL_TAG_SHIFT)
+#define MC2EMC_LL_TAG_RANGE                     _MK_SHIFT_CONST(33):_MK_SHIFT_CONST(29)
+#define MC2EMC_LL_TAG_ROW                       0
+
+#define MC2EMC_LL_DOUBLEREQ_SHIFT                       _MK_SHIFT_CONST(34)
+#define MC2EMC_LL_DOUBLEREQ_FIELD                       (_MK_MASK_CONST(0x1) << MC2EMC_LL_DOUBLEREQ_SHIFT)
+#define MC2EMC_LL_DOUBLEREQ_RANGE                       _MK_SHIFT_CONST(34):_MK_SHIFT_CONST(34)
+#define MC2EMC_LL_DOUBLEREQ_ROW                 0
+
+
+// Packet EMC2MC_LL
+#define EMC2MC_LL_SIZE 64
+
+#define EMC2MC_LL_RDI_SHIFT                     _MK_SHIFT_CONST(0)
+#define EMC2MC_LL_RDI_FIELD                     (_MK_MASK_CONST(0xffffffff) << EMC2MC_LL_RDI_SHIFT)
+#define EMC2MC_LL_RDI_RANGE                     _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(0)
+#define EMC2MC_LL_RDI_ROW                       0
+
+
+// Packet MC2EMC_LL_CRITINFO
+#define MC2EMC_LL_CRITINFO_SIZE 11
+
+#define MC2EMC_LL_CRITINFO_HP_SHIFT                     _MK_SHIFT_CONST(0)
+#define MC2EMC_LL_CRITINFO_HP_FIELD                     (_MK_MASK_CONST(0x1f) << MC2EMC_LL_CRITINFO_HP_SHIFT)
+#define MC2EMC_LL_CRITINFO_HP_RANGE                     _MK_SHIFT_CONST(4):_MK_SHIFT_CONST(0)
+#define MC2EMC_LL_CRITINFO_HP_ROW                       0
+
+#define MC2EMC_LL_CRITINFO_TIMEOUT_SHIFT                        _MK_SHIFT_CONST(5)
+#define MC2EMC_LL_CRITINFO_TIMEOUT_FIELD                        (_MK_MASK_CONST(0x3f) << MC2EMC_LL_CRITINFO_TIMEOUT_SHIFT)
+#define MC2EMC_LL_CRITINFO_TIMEOUT_RANGE                        _MK_SHIFT_CONST(10):_MK_SHIFT_CONST(5)
+#define MC2EMC_LL_CRITINFO_TIMEOUT_ROW                  0
+
+
+// Packet MC2EMC_LL_ARBINFO
+#define MC2EMC_LL_ARBINFO_SIZE 2
+
+#define MC2EMC_LL_ARBINFO_BANK_SHIFT                    _MK_SHIFT_CONST(0)
+#define MC2EMC_LL_ARBINFO_BANK_FIELD                    (_MK_MASK_CONST(0x3) << MC2EMC_LL_ARBINFO_BANK_SHIFT)
+#define MC2EMC_LL_ARBINFO_BANK_RANGE                    _MK_SHIFT_CONST(1):_MK_SHIFT_CONST(0)
+#define MC2EMC_LL_ARBINFO_BANK_ROW                      0
+
+
+// Packet CMC2MC_AXI_A
+#define CMC2MC_AXI_A_SIZE 58
+
+#define CMC2MC_AXI_A_AADDR_SHIFT                        _MK_SHIFT_CONST(0)
+#define CMC2MC_AXI_A_AADDR_FIELD                        (_MK_MASK_CONST(0xffffffff) << CMC2MC_AXI_A_AADDR_SHIFT)
+#define CMC2MC_AXI_A_AADDR_RANGE                        _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CMC2MC_AXI_A_AADDR_ROW                  0
+
+#define CMC2MC_AXI_A_AID_SHIFT                  _MK_SHIFT_CONST(32)
+#define CMC2MC_AXI_A_AID_FIELD                  (_MK_MASK_CONST(0xff) << CMC2MC_AXI_A_AID_SHIFT)
+#define CMC2MC_AXI_A_AID_RANGE                  _MK_SHIFT_CONST(39):_MK_SHIFT_CONST(32)
+#define CMC2MC_AXI_A_AID_ROW                    0
+
+#define CMC2MC_AXI_A_ALEN_SHIFT                 _MK_SHIFT_CONST(40)
+#define CMC2MC_AXI_A_ALEN_FIELD                 (_MK_MASK_CONST(0xf) << CMC2MC_AXI_A_ALEN_SHIFT)
+#define CMC2MC_AXI_A_ALEN_RANGE                 _MK_SHIFT_CONST(43):_MK_SHIFT_CONST(40)
+#define CMC2MC_AXI_A_ALEN_ROW                   0
+#define CMC2MC_AXI_A_ALEN_ONEDATA                       _MK_ENUM_CONST(0)
+#define CMC2MC_AXI_A_ALEN_TWODATA                       _MK_ENUM_CONST(1)
+#define CMC2MC_AXI_A_ALEN_THREEDATA                     _MK_ENUM_CONST(2)
+#define CMC2MC_AXI_A_ALEN_FOURDATA                      _MK_ENUM_CONST(3)
+#define CMC2MC_AXI_A_ALEN_FIVEDATA                      _MK_ENUM_CONST(4)
+#define CMC2MC_AXI_A_ALEN_SIXDATA                       _MK_ENUM_CONST(5)
+#define CMC2MC_AXI_A_ALEN_SEVENDATA                     _MK_ENUM_CONST(6)
+#define CMC2MC_AXI_A_ALEN_EIGHTDATA                     _MK_ENUM_CONST(7)
+#define CMC2MC_AXI_A_ALEN_NINEDATA                      _MK_ENUM_CONST(8)
+#define CMC2MC_AXI_A_ALEN_TENDATA                       _MK_ENUM_CONST(9)
+#define CMC2MC_AXI_A_ALEN_ELEVENDATA                    _MK_ENUM_CONST(10)
+#define CMC2MC_AXI_A_ALEN_TWELVEDATA                    _MK_ENUM_CONST(11)
+#define CMC2MC_AXI_A_ALEN_THIRTEENDATA                  _MK_ENUM_CONST(12)
+#define CMC2MC_AXI_A_ALEN_FOURTEENDATA                  _MK_ENUM_CONST(13)
+#define CMC2MC_AXI_A_ALEN_FIFTHTEENDATA                 _MK_ENUM_CONST(14)
+#define CMC2MC_AXI_A_ALEN_SIXTEENDATA                   _MK_ENUM_CONST(15)
+
+#define CMC2MC_AXI_A_ASIZE_SHIFT                        _MK_SHIFT_CONST(44)
+#define CMC2MC_AXI_A_ASIZE_FIELD                        (_MK_MASK_CONST(0x7) << CMC2MC_AXI_A_ASIZE_SHIFT)
+#define CMC2MC_AXI_A_ASIZE_RANGE                        _MK_SHIFT_CONST(46):_MK_SHIFT_CONST(44)
+#define CMC2MC_AXI_A_ASIZE_ROW                  0
+#define CMC2MC_AXI_A_ASIZE_ONEBYTE                      _MK_ENUM_CONST(0)
+#define CMC2MC_AXI_A_ASIZE_TWOBYTES                     _MK_ENUM_CONST(1)
+#define CMC2MC_AXI_A_ASIZE_FOURBYTES                    _MK_ENUM_CONST(2)
+#define CMC2MC_AXI_A_ASIZE_EIGHTBYTES                   _MK_ENUM_CONST(3)
+#define CMC2MC_AXI_A_ASIZE_SIXTEENBYTES                 _MK_ENUM_CONST(4)
+#define CMC2MC_AXI_A_ASIZE_THIRTYTWOBYTES                       _MK_ENUM_CONST(5)
+#define CMC2MC_AXI_A_ASIZE_SIXTYFOURBYTES                       _MK_ENUM_CONST(6)
+#define CMC2MC_AXI_A_ASIZE_ONEHUNDREDTWENTYEIGHTBYTES                   _MK_ENUM_CONST(7)
+
+#define CMC2MC_AXI_A_ABURST_SHIFT                       _MK_SHIFT_CONST(47)
+#define CMC2MC_AXI_A_ABURST_FIELD                       (_MK_MASK_CONST(0x3) << CMC2MC_AXI_A_ABURST_SHIFT)
+#define CMC2MC_AXI_A_ABURST_RANGE                       _MK_SHIFT_CONST(48):_MK_SHIFT_CONST(47)
+#define CMC2MC_AXI_A_ABURST_ROW                 0
+#define CMC2MC_AXI_A_ABURST_FIXED                       _MK_ENUM_CONST(0)
+#define CMC2MC_AXI_A_ABURST_INCR                        _MK_ENUM_CONST(1)
+#define CMC2MC_AXI_A_ABURST_WRAP                        _MK_ENUM_CONST(2)
+#define CMC2MC_AXI_A_ABURST_RSVD                        _MK_ENUM_CONST(3)
+
+#define CMC2MC_AXI_A_ALOCK_SHIFT                        _MK_SHIFT_CONST(49)
+#define CMC2MC_AXI_A_ALOCK_FIELD                        (_MK_MASK_CONST(0x3) << CMC2MC_AXI_A_ALOCK_SHIFT)
+#define CMC2MC_AXI_A_ALOCK_RANGE                        _MK_SHIFT_CONST(50):_MK_SHIFT_CONST(49)
+#define CMC2MC_AXI_A_ALOCK_ROW                  0
+#define CMC2MC_AXI_A_ALOCK_NORMAL                       _MK_ENUM_CONST(0)
+#define CMC2MC_AXI_A_ALOCK_EXCLUSIVE                    _MK_ENUM_CONST(1)
+#define CMC2MC_AXI_A_ALOCK_LOCKED                       _MK_ENUM_CONST(2)
+#define CMC2MC_AXI_A_ALOCK_RSVD                 _MK_ENUM_CONST(3)
+
+#define CMC2MC_AXI_A_ACACHE_SHIFT                       _MK_SHIFT_CONST(51)
+#define CMC2MC_AXI_A_ACACHE_FIELD                       (_MK_MASK_CONST(0xf) << CMC2MC_AXI_A_ACACHE_SHIFT)
+#define CMC2MC_AXI_A_ACACHE_RANGE                       _MK_SHIFT_CONST(54):_MK_SHIFT_CONST(51)
+#define CMC2MC_AXI_A_ACACHE_ROW                 0
+#define CMC2MC_AXI_A_ACACHE_NONCACHEABLE_NONBUFFERABLE                  _MK_ENUM_CONST(0)
+#define CMC2MC_AXI_A_ACACHE_BUFFERABLE                  _MK_ENUM_CONST(1)
+#define CMC2MC_AXI_A_ACACHE_CACHEABLE_DONOTALLOCATE                     _MK_ENUM_CONST(2)
+#define CMC2MC_AXI_A_ACACHE_CACHEABLE_BUFFERABLE_DONOTALLOCATE                  _MK_ENUM_CONST(3)
+#define CMC2MC_AXI_A_ACACHE_CACHEABLEWRITETHROUGH_ALLOCATEONREAD                        _MK_ENUM_CONST(6)
+#define CMC2MC_AXI_A_ACACHE_CACHEABLEWRITEBACK_ALLOCATEONREAD                   _MK_ENUM_CONST(7)
+#define CMC2MC_AXI_A_ACACHE_CACHEABLEWRITETHROUGH_ALLOCATEONWRITE                       _MK_ENUM_CONST(10)
+#define CMC2MC_AXI_A_ACACHE_CACHEABLEWRITEBACK_ALLOCATEONWRITE                  _MK_ENUM_CONST(11)
+#define CMC2MC_AXI_A_ACACHE_CACHEABLEWRITETHROUGH_ALLOCATEONREADWRITE                   _MK_ENUM_CONST(14)
+#define CMC2MC_AXI_A_ACACHE_CACHEABLEWRITEBACK_ALLOCATEONREADWRITE                      _MK_ENUM_CONST(15)
+
+#define CMC2MC_AXI_A_APROT_SHIFT                        _MK_SHIFT_CONST(55)
+#define CMC2MC_AXI_A_APROT_FIELD                        (_MK_MASK_CONST(0x7) << CMC2MC_AXI_A_APROT_SHIFT)
+#define CMC2MC_AXI_A_APROT_RANGE                        _MK_SHIFT_CONST(57):_MK_SHIFT_CONST(55)
+#define CMC2MC_AXI_A_APROT_ROW                  0
+#define CMC2MC_AXI_A_APROT_DATA_SECURE_NORMAL                   _MK_ENUM_CONST(0)
+#define CMC2MC_AXI_A_APROT_DATA_SECURE_PRIVILEGED                       _MK_ENUM_CONST(1)
+#define CMC2MC_AXI_A_APROT_DATA_NONSECURE_NORMAL                        _MK_ENUM_CONST(2)
+#define CMC2MC_AXI_A_APROT_DATA_NONSECURE_PRIVILEGED                    _MK_ENUM_CONST(3)
+#define CMC2MC_AXI_A_APROT_INST_SECURE_NORMAL                   _MK_ENUM_CONST(4)
+#define CMC2MC_AXI_A_APROT_INST_SECURE_PRIVILEGED                       _MK_ENUM_CONST(5)
+#define CMC2MC_AXI_A_APROT_INST_NONSECURE_NORMAL                        _MK_ENUM_CONST(6)
+#define CMC2MC_AXI_A_APROT_INST_NONSECURE_PRIVILEGED                    _MK_ENUM_CONST(7)
+
+
+// Packet CMC2MC_AXI_W
+#define CMC2MC_AXI_W_SIZE 81
+
+#define CMC2MC_AXI_W_WDATA_SHIFT                        _MK_SHIFT_CONST(0)
+#define CMC2MC_AXI_W_WDATA_FIELD                        (_MK_MASK_CONST(0xffffffff) << CMC2MC_AXI_W_WDATA_SHIFT)
+#define CMC2MC_AXI_W_WDATA_RANGE                        _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(0)
+#define CMC2MC_AXI_W_WDATA_ROW                  0
+
+#define CMC2MC_AXI_W_WID_SHIFT                  _MK_SHIFT_CONST(64)
+#define CMC2MC_AXI_W_WID_FIELD                  (_MK_MASK_CONST(0xff) << CMC2MC_AXI_W_WID_SHIFT)
+#define CMC2MC_AXI_W_WID_RANGE                  _MK_SHIFT_CONST(71):_MK_SHIFT_CONST(64)
+#define CMC2MC_AXI_W_WID_ROW                    0
+
+#define CMC2MC_AXI_W_WSTRB_SHIFT                        _MK_SHIFT_CONST(72)
+#define CMC2MC_AXI_W_WSTRB_FIELD                        (_MK_MASK_CONST(0xff) << CMC2MC_AXI_W_WSTRB_SHIFT)
+#define CMC2MC_AXI_W_WSTRB_RANGE                        _MK_SHIFT_CONST(79):_MK_SHIFT_CONST(72)
+#define CMC2MC_AXI_W_WSTRB_ROW                  0
+
+#define CMC2MC_AXI_W_WLAST_SHIFT                        _MK_SHIFT_CONST(80)
+#define CMC2MC_AXI_W_WLAST_FIELD                        (_MK_MASK_CONST(0x1) << CMC2MC_AXI_W_WLAST_SHIFT)
+#define CMC2MC_AXI_W_WLAST_RANGE                        _MK_SHIFT_CONST(80):_MK_SHIFT_CONST(80)
+#define CMC2MC_AXI_W_WLAST_ROW                  0
+#define CMC2MC_AXI_W_WLAST_DISABLED                     _MK_ENUM_CONST(0)
+#define CMC2MC_AXI_W_WLAST_ENABLED                      _MK_ENUM_CONST(1)
+
+
+// Packet CMC2MC_AXI_B
+#define CMC2MC_AXI_B_SIZE 10
+
+#define CMC2MC_AXI_B_BID_SHIFT                  _MK_SHIFT_CONST(0)
+#define CMC2MC_AXI_B_BID_FIELD                  (_MK_MASK_CONST(0xff) << CMC2MC_AXI_B_BID_SHIFT)
+#define CMC2MC_AXI_B_BID_RANGE                  _MK_SHIFT_CONST(7):_MK_SHIFT_CONST(0)
+#define CMC2MC_AXI_B_BID_ROW                    0
+
+#define CMC2MC_AXI_B_BRESP_SHIFT                        _MK_SHIFT_CONST(8)
+#define CMC2MC_AXI_B_BRESP_FIELD                        (_MK_MASK_CONST(0x3) << CMC2MC_AXI_B_BRESP_SHIFT)
+#define CMC2MC_AXI_B_BRESP_RANGE                        _MK_SHIFT_CONST(9):_MK_SHIFT_CONST(8)
+#define CMC2MC_AXI_B_BRESP_ROW                  0
+#define CMC2MC_AXI_B_BRESP_OKAY                 _MK_ENUM_CONST(0)
+#define CMC2MC_AXI_B_BRESP_EXOKAY                       _MK_ENUM_CONST(1)
+#define CMC2MC_AXI_B_BRESP_SLVERR                       _MK_ENUM_CONST(2)
+#define CMC2MC_AXI_B_BRESP_DECERR                       _MK_ENUM_CONST(3)
+
+
+// Packet CMC2MC_AXI_R
+#define CMC2MC_AXI_R_SIZE 75
+
+#define CMC2MC_AXI_R_RDATA_SHIFT                        _MK_SHIFT_CONST(0)
+#define CMC2MC_AXI_R_RDATA_FIELD                        (_MK_MASK_CONST(0xffffffff) << CMC2MC_AXI_R_RDATA_SHIFT)
+#define CMC2MC_AXI_R_RDATA_RANGE                        _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(0)
+#define CMC2MC_AXI_R_RDATA_ROW                  0
+
+#define CMC2MC_AXI_R_RID_SHIFT                  _MK_SHIFT_CONST(64)
+#define CMC2MC_AXI_R_RID_FIELD                  (_MK_MASK_CONST(0xff) << CMC2MC_AXI_R_RID_SHIFT)
+#define CMC2MC_AXI_R_RID_RANGE                  _MK_SHIFT_CONST(71):_MK_SHIFT_CONST(64)
+#define CMC2MC_AXI_R_RID_ROW                    0
+
+#define CMC2MC_AXI_R_RRESP_SHIFT                        _MK_SHIFT_CONST(72)
+#define CMC2MC_AXI_R_RRESP_FIELD                        (_MK_MASK_CONST(0x3) << CMC2MC_AXI_R_RRESP_SHIFT)
+#define CMC2MC_AXI_R_RRESP_RANGE                        _MK_SHIFT_CONST(73):_MK_SHIFT_CONST(72)
+#define CMC2MC_AXI_R_RRESP_ROW                  0
+#define CMC2MC_AXI_R_RRESP_OKAY                 _MK_ENUM_CONST(0)
+#define CMC2MC_AXI_R_RRESP_EXOKAY                       _MK_ENUM_CONST(1)
+#define CMC2MC_AXI_R_RRESP_SLVERR                       _MK_ENUM_CONST(2)
+#define CMC2MC_AXI_R_RRESP_DECERR                       _MK_ENUM_CONST(3)
+
+#define CMC2MC_AXI_R_RLAST_SHIFT                        _MK_SHIFT_CONST(74)
+#define CMC2MC_AXI_R_RLAST_FIELD                        (_MK_MASK_CONST(0x1) << CMC2MC_AXI_R_RLAST_SHIFT)
+#define CMC2MC_AXI_R_RLAST_RANGE                        _MK_SHIFT_CONST(74):_MK_SHIFT_CONST(74)
+#define CMC2MC_AXI_R_RLAST_ROW                  0
+#define CMC2MC_AXI_R_RLAST_DISABLED                     _MK_ENUM_CONST(0)
+#define CMC2MC_AXI_R_RLAST_ENABLED                      _MK_ENUM_CONST(1)
+
+
+// Packet MSELECT2MC_AXI_A
+#define MSELECT2MC_AXI_A_SIZE 58
+
+#define MSELECT2MC_AXI_A_AADDR_SHIFT                    _MK_SHIFT_CONST(0)
+#define MSELECT2MC_AXI_A_AADDR_FIELD                    (_MK_MASK_CONST(0xffffffff) << MSELECT2MC_AXI_A_AADDR_SHIFT)
+#define MSELECT2MC_AXI_A_AADDR_RANGE                    _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define MSELECT2MC_AXI_A_AADDR_ROW                      0
+
+#define MSELECT2MC_AXI_A_AID_SHIFT                      _MK_SHIFT_CONST(32)
+#define MSELECT2MC_AXI_A_AID_FIELD                      (_MK_MASK_CONST(0xff) << MSELECT2MC_AXI_A_AID_SHIFT)
+#define MSELECT2MC_AXI_A_AID_RANGE                      _MK_SHIFT_CONST(39):_MK_SHIFT_CONST(32)
+#define MSELECT2MC_AXI_A_AID_ROW                        0
+
+#define MSELECT2MC_AXI_A_ALEN_SHIFT                     _MK_SHIFT_CONST(40)
+#define MSELECT2MC_AXI_A_ALEN_FIELD                     (_MK_MASK_CONST(0xf) << MSELECT2MC_AXI_A_ALEN_SHIFT)
+#define MSELECT2MC_AXI_A_ALEN_RANGE                     _MK_SHIFT_CONST(43):_MK_SHIFT_CONST(40)
+#define MSELECT2MC_AXI_A_ALEN_ROW                       0
+#define MSELECT2MC_AXI_A_ALEN_ONEDATA                   _MK_ENUM_CONST(0)
+#define MSELECT2MC_AXI_A_ALEN_TWODATA                   _MK_ENUM_CONST(1)
+#define MSELECT2MC_AXI_A_ALEN_THREEDATA                 _MK_ENUM_CONST(2)
+#define MSELECT2MC_AXI_A_ALEN_FOURDATA                  _MK_ENUM_CONST(3)
+#define MSELECT2MC_AXI_A_ALEN_FIVEDATA                  _MK_ENUM_CONST(4)
+#define MSELECT2MC_AXI_A_ALEN_SIXDATA                   _MK_ENUM_CONST(5)
+#define MSELECT2MC_AXI_A_ALEN_SEVENDATA                 _MK_ENUM_CONST(6)
+#define MSELECT2MC_AXI_A_ALEN_EIGHTDATA                 _MK_ENUM_CONST(7)
+#define MSELECT2MC_AXI_A_ALEN_NINEDATA                  _MK_ENUM_CONST(8)
+#define MSELECT2MC_AXI_A_ALEN_TENDATA                   _MK_ENUM_CONST(9)
+#define MSELECT2MC_AXI_A_ALEN_ELEVENDATA                        _MK_ENUM_CONST(10)
+#define MSELECT2MC_AXI_A_ALEN_TWELVEDATA                        _MK_ENUM_CONST(11)
+#define MSELECT2MC_AXI_A_ALEN_THIRTEENDATA                      _MK_ENUM_CONST(12)
+#define MSELECT2MC_AXI_A_ALEN_FOURTEENDATA                      _MK_ENUM_CONST(13)
+#define MSELECT2MC_AXI_A_ALEN_FIFTHTEENDATA                     _MK_ENUM_CONST(14)
+#define MSELECT2MC_AXI_A_ALEN_SIXTEENDATA                       _MK_ENUM_CONST(15)
+
+#define MSELECT2MC_AXI_A_ASIZE_SHIFT                    _MK_SHIFT_CONST(44)
+#define MSELECT2MC_AXI_A_ASIZE_FIELD                    (_MK_MASK_CONST(0x7) << MSELECT2MC_AXI_A_ASIZE_SHIFT)
+#define MSELECT2MC_AXI_A_ASIZE_RANGE                    _MK_SHIFT_CONST(46):_MK_SHIFT_CONST(44)
+#define MSELECT2MC_AXI_A_ASIZE_ROW                      0
+#define MSELECT2MC_AXI_A_ASIZE_ONEBYTE                  _MK_ENUM_CONST(0)
+#define MSELECT2MC_AXI_A_ASIZE_TWOBYTES                 _MK_ENUM_CONST(1)
+#define MSELECT2MC_AXI_A_ASIZE_FOURBYTES                        _MK_ENUM_CONST(2)
+#define MSELECT2MC_AXI_A_ASIZE_EIGHTBYTES                       _MK_ENUM_CONST(3)
+#define MSELECT2MC_AXI_A_ASIZE_SIXTEENBYTES                     _MK_ENUM_CONST(4)
+#define MSELECT2MC_AXI_A_ASIZE_THIRTYTWOBYTES                   _MK_ENUM_CONST(5)
+#define MSELECT2MC_AXI_A_ASIZE_SIXTYFOURBYTES                   _MK_ENUM_CONST(6)
+#define MSELECT2MC_AXI_A_ASIZE_ONEHUNDREDTWENTYEIGHTBYTES                       _MK_ENUM_CONST(7)
+
+#define MSELECT2MC_AXI_A_ABURST_SHIFT                   _MK_SHIFT_CONST(47)
+#define MSELECT2MC_AXI_A_ABURST_FIELD                   (_MK_MASK_CONST(0x3) << MSELECT2MC_AXI_A_ABURST_SHIFT)
+#define MSELECT2MC_AXI_A_ABURST_RANGE                   _MK_SHIFT_CONST(48):_MK_SHIFT_CONST(47)
+#define MSELECT2MC_AXI_A_ABURST_ROW                     0
+#define MSELECT2MC_AXI_A_ABURST_FIXED                   _MK_ENUM_CONST(0)
+#define MSELECT2MC_AXI_A_ABURST_INCR                    _MK_ENUM_CONST(1)
+#define MSELECT2MC_AXI_A_ABURST_WRAP                    _MK_ENUM_CONST(2)
+#define MSELECT2MC_AXI_A_ABURST_RSVD                    _MK_ENUM_CONST(3)
+
+#define MSELECT2MC_AXI_A_ALOCK_SHIFT                    _MK_SHIFT_CONST(49)
+#define MSELECT2MC_AXI_A_ALOCK_FIELD                    (_MK_MASK_CONST(0x3) << MSELECT2MC_AXI_A_ALOCK_SHIFT)
+#define MSELECT2MC_AXI_A_ALOCK_RANGE                    _MK_SHIFT_CONST(50):_MK_SHIFT_CONST(49)
+#define MSELECT2MC_AXI_A_ALOCK_ROW                      0
+#define MSELECT2MC_AXI_A_ALOCK_NORMAL                   _MK_ENUM_CONST(0)
+#define MSELECT2MC_AXI_A_ALOCK_EXCLUSIVE                        _MK_ENUM_CONST(1)
+#define MSELECT2MC_AXI_A_ALOCK_LOCKED                   _MK_ENUM_CONST(2)
+#define MSELECT2MC_AXI_A_ALOCK_RSVD                     _MK_ENUM_CONST(3)
+
+#define MSELECT2MC_AXI_A_ACACHE_SHIFT                   _MK_SHIFT_CONST(51)
+#define MSELECT2MC_AXI_A_ACACHE_FIELD                   (_MK_MASK_CONST(0xf) << MSELECT2MC_AXI_A_ACACHE_SHIFT)
+#define MSELECT2MC_AXI_A_ACACHE_RANGE                   _MK_SHIFT_CONST(54):_MK_SHIFT_CONST(51)
+#define MSELECT2MC_AXI_A_ACACHE_ROW                     0
+#define MSELECT2MC_AXI_A_ACACHE_NONCACHEABLE_NONBUFFERABLE                      _MK_ENUM_CONST(0)
+#define MSELECT2MC_AXI_A_ACACHE_BUFFERABLE                      _MK_ENUM_CONST(1)
+#define MSELECT2MC_AXI_A_ACACHE_CACHEABLE_DONOTALLOCATE                 _MK_ENUM_CONST(2)
+#define MSELECT2MC_AXI_A_ACACHE_CACHEABLE_BUFFERABLE_DONOTALLOCATE                      _MK_ENUM_CONST(3)
+#define MSELECT2MC_AXI_A_ACACHE_CACHEABLEWRITETHROUGH_ALLOCATEONREAD                    _MK_ENUM_CONST(6)
+#define MSELECT2MC_AXI_A_ACACHE_CACHEABLEWRITEBACK_ALLOCATEONREAD                       _MK_ENUM_CONST(7)
+#define MSELECT2MC_AXI_A_ACACHE_CACHEABLEWRITETHROUGH_ALLOCATEONWRITE                   _MK_ENUM_CONST(10)
+#define MSELECT2MC_AXI_A_ACACHE_CACHEABLEWRITEBACK_ALLOCATEONWRITE                      _MK_ENUM_CONST(11)
+#define MSELECT2MC_AXI_A_ACACHE_CACHEABLEWRITETHROUGH_ALLOCATEONREADWRITE                       _MK_ENUM_CONST(14)
+#define MSELECT2MC_AXI_A_ACACHE_CACHEABLEWRITEBACK_ALLOCATEONREADWRITE                  _MK_ENUM_CONST(15)
+
+#define MSELECT2MC_AXI_A_APROT_SHIFT                    _MK_SHIFT_CONST(55)
+#define MSELECT2MC_AXI_A_APROT_FIELD                    (_MK_MASK_CONST(0x7) << MSELECT2MC_AXI_A_APROT_SHIFT)
+#define MSELECT2MC_AXI_A_APROT_RANGE                    _MK_SHIFT_CONST(57):_MK_SHIFT_CONST(55)
+#define MSELECT2MC_AXI_A_APROT_ROW                      0
+#define MSELECT2MC_AXI_A_APROT_DATA_SECURE_NORMAL                       _MK_ENUM_CONST(0)
+#define MSELECT2MC_AXI_A_APROT_DATA_SECURE_PRIVILEGED                   _MK_ENUM_CONST(1)
+#define MSELECT2MC_AXI_A_APROT_DATA_NONSECURE_NORMAL                    _MK_ENUM_CONST(2)
+#define MSELECT2MC_AXI_A_APROT_DATA_NONSECURE_PRIVILEGED                        _MK_ENUM_CONST(3)
+#define MSELECT2MC_AXI_A_APROT_INST_SECURE_NORMAL                       _MK_ENUM_CONST(4)
+#define MSELECT2MC_AXI_A_APROT_INST_SECURE_PRIVILEGED                   _MK_ENUM_CONST(5)
+#define MSELECT2MC_AXI_A_APROT_INST_NONSECURE_NORMAL                    _MK_ENUM_CONST(6)
+#define MSELECT2MC_AXI_A_APROT_INST_NONSECURE_PRIVILEGED                        _MK_ENUM_CONST(7)
+
+
+// Packet MSELECT2MC_AXI_W
+#define MSELECT2MC_AXI_W_SIZE 81
+
+#define MSELECT2MC_AXI_W_WDATA_SHIFT                    _MK_SHIFT_CONST(0)
+#define MSELECT2MC_AXI_W_WDATA_FIELD                    (_MK_MASK_CONST(0xffffffff) << MSELECT2MC_AXI_W_WDATA_SHIFT)
+#define MSELECT2MC_AXI_W_WDATA_RANGE                    _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(0)
+#define MSELECT2MC_AXI_W_WDATA_ROW                      0
+
+#define MSELECT2MC_AXI_W_WID_SHIFT                      _MK_SHIFT_CONST(64)
+#define MSELECT2MC_AXI_W_WID_FIELD                      (_MK_MASK_CONST(0xff) << MSELECT2MC_AXI_W_WID_SHIFT)
+#define MSELECT2MC_AXI_W_WID_RANGE                      _MK_SHIFT_CONST(71):_MK_SHIFT_CONST(64)
+#define MSELECT2MC_AXI_W_WID_ROW                        0
+
+#define MSELECT2MC_AXI_W_WSTRB_SHIFT                    _MK_SHIFT_CONST(72)
+#define MSELECT2MC_AXI_W_WSTRB_FIELD                    (_MK_MASK_CONST(0xff) << MSELECT2MC_AXI_W_WSTRB_SHIFT)
+#define MSELECT2MC_AXI_W_WSTRB_RANGE                    _MK_SHIFT_CONST(79):_MK_SHIFT_CONST(72)
+#define MSELECT2MC_AXI_W_WSTRB_ROW                      0
+
+#define MSELECT2MC_AXI_W_WLAST_SHIFT                    _MK_SHIFT_CONST(80)
+#define MSELECT2MC_AXI_W_WLAST_FIELD                    (_MK_MASK_CONST(0x1) << MSELECT2MC_AXI_W_WLAST_SHIFT)
+#define MSELECT2MC_AXI_W_WLAST_RANGE                    _MK_SHIFT_CONST(80):_MK_SHIFT_CONST(80)
+#define MSELECT2MC_AXI_W_WLAST_ROW                      0
+#define MSELECT2MC_AXI_W_WLAST_DISABLED                 _MK_ENUM_CONST(0)
+#define MSELECT2MC_AXI_W_WLAST_ENABLED                  _MK_ENUM_CONST(1)
+
+
+// Packet MSELECT2MC_AXI_B
+#define MSELECT2MC_AXI_B_SIZE 10
+
+#define MSELECT2MC_AXI_B_BID_SHIFT                      _MK_SHIFT_CONST(0)
+#define MSELECT2MC_AXI_B_BID_FIELD                      (_MK_MASK_CONST(0xff) << MSELECT2MC_AXI_B_BID_SHIFT)
+#define MSELECT2MC_AXI_B_BID_RANGE                      _MK_SHIFT_CONST(7):_MK_SHIFT_CONST(0)
+#define MSELECT2MC_AXI_B_BID_ROW                        0
+
+#define MSELECT2MC_AXI_B_BRESP_SHIFT                    _MK_SHIFT_CONST(8)
+#define MSELECT2MC_AXI_B_BRESP_FIELD                    (_MK_MASK_CONST(0x3) << MSELECT2MC_AXI_B_BRESP_SHIFT)
+#define MSELECT2MC_AXI_B_BRESP_RANGE                    _MK_SHIFT_CONST(9):_MK_SHIFT_CONST(8)
+#define MSELECT2MC_AXI_B_BRESP_ROW                      0
+#define MSELECT2MC_AXI_B_BRESP_OKAY                     _MK_ENUM_CONST(0)
+#define MSELECT2MC_AXI_B_BRESP_EXOKAY                   _MK_ENUM_CONST(1)
+#define MSELECT2MC_AXI_B_BRESP_SLVERR                   _MK_ENUM_CONST(2)
+#define MSELECT2MC_AXI_B_BRESP_DECERR                   _MK_ENUM_CONST(3)
+
+
+// Packet MSELECT2MC_AXI_R
+#define MSELECT2MC_AXI_R_SIZE 75
+
+#define MSELECT2MC_AXI_R_RDATA_SHIFT                    _MK_SHIFT_CONST(0)
+#define MSELECT2MC_AXI_R_RDATA_FIELD                    (_MK_MASK_CONST(0xffffffff) << MSELECT2MC_AXI_R_RDATA_SHIFT)
+#define MSELECT2MC_AXI_R_RDATA_RANGE                    _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(0)
+#define MSELECT2MC_AXI_R_RDATA_ROW                      0
+
+#define MSELECT2MC_AXI_R_RID_SHIFT                      _MK_SHIFT_CONST(64)
+#define MSELECT2MC_AXI_R_RID_FIELD                      (_MK_MASK_CONST(0xff) << MSELECT2MC_AXI_R_RID_SHIFT)
+#define MSELECT2MC_AXI_R_RID_RANGE                      _MK_SHIFT_CONST(71):_MK_SHIFT_CONST(64)
+#define MSELECT2MC_AXI_R_RID_ROW                        0
+
+#define MSELECT2MC_AXI_R_RRESP_SHIFT                    _MK_SHIFT_CONST(72)
+#define MSELECT2MC_AXI_R_RRESP_FIELD                    (_MK_MASK_CONST(0x3) << MSELECT2MC_AXI_R_RRESP_SHIFT)
+#define MSELECT2MC_AXI_R_RRESP_RANGE                    _MK_SHIFT_CONST(73):_MK_SHIFT_CONST(72)
+#define MSELECT2MC_AXI_R_RRESP_ROW                      0
+#define MSELECT2MC_AXI_R_RRESP_OKAY                     _MK_ENUM_CONST(0)
+#define MSELECT2MC_AXI_R_RRESP_EXOKAY                   _MK_ENUM_CONST(1)
+#define MSELECT2MC_AXI_R_RRESP_SLVERR                   _MK_ENUM_CONST(2)
+#define MSELECT2MC_AXI_R_RRESP_DECERR                   _MK_ENUM_CONST(3)
+
+#define MSELECT2MC_AXI_R_RLAST_SHIFT                    _MK_SHIFT_CONST(74)
+#define MSELECT2MC_AXI_R_RLAST_FIELD                    (_MK_MASK_CONST(0x1) << MSELECT2MC_AXI_R_RLAST_SHIFT)
+#define MSELECT2MC_AXI_R_RLAST_RANGE                    _MK_SHIFT_CONST(74):_MK_SHIFT_CONST(74)
+#define MSELECT2MC_AXI_R_RLAST_ROW                      0
+#define MSELECT2MC_AXI_R_RLAST_DISABLED                 _MK_ENUM_CONST(0)
+#define MSELECT2MC_AXI_R_RLAST_ENABLED                  _MK_ENUM_CONST(1)
+
+
+// Packet AXI2MC_AXI_A
+#define AXI2MC_AXI_A_SIZE 58
+
+#define AXI2MC_AXI_A_AADDR_SHIFT                        _MK_SHIFT_CONST(0)
+#define AXI2MC_AXI_A_AADDR_FIELD                        (_MK_MASK_CONST(0xffffffff) << AXI2MC_AXI_A_AADDR_SHIFT)
+#define AXI2MC_AXI_A_AADDR_RANGE                        _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define AXI2MC_AXI_A_AADDR_ROW                  0
+
+#define AXI2MC_AXI_A_AID_SHIFT                  _MK_SHIFT_CONST(32)
+#define AXI2MC_AXI_A_AID_FIELD                  (_MK_MASK_CONST(0xff) << AXI2MC_AXI_A_AID_SHIFT)
+#define AXI2MC_AXI_A_AID_RANGE                  _MK_SHIFT_CONST(39):_MK_SHIFT_CONST(32)
+#define AXI2MC_AXI_A_AID_ROW                    0
+
+#define AXI2MC_AXI_A_ALEN_SHIFT                 _MK_SHIFT_CONST(40)
+#define AXI2MC_AXI_A_ALEN_FIELD                 (_MK_MASK_CONST(0xf) << AXI2MC_AXI_A_ALEN_SHIFT)
+#define AXI2MC_AXI_A_ALEN_RANGE                 _MK_SHIFT_CONST(43):_MK_SHIFT_CONST(40)
+#define AXI2MC_AXI_A_ALEN_ROW                   0
+#define AXI2MC_AXI_A_ALEN_ONEDATA                       _MK_ENUM_CONST(0)
+#define AXI2MC_AXI_A_ALEN_TWODATA                       _MK_ENUM_CONST(1)
+#define AXI2MC_AXI_A_ALEN_THREEDATA                     _MK_ENUM_CONST(2)
+#define AXI2MC_AXI_A_ALEN_FOURDATA                      _MK_ENUM_CONST(3)
+#define AXI2MC_AXI_A_ALEN_FIVEDATA                      _MK_ENUM_CONST(4)
+#define AXI2MC_AXI_A_ALEN_SIXDATA                       _MK_ENUM_CONST(5)
+#define AXI2MC_AXI_A_ALEN_SEVENDATA                     _MK_ENUM_CONST(6)
+#define AXI2MC_AXI_A_ALEN_EIGHTDATA                     _MK_ENUM_CONST(7)
+#define AXI2MC_AXI_A_ALEN_NINEDATA                      _MK_ENUM_CONST(8)
+#define AXI2MC_AXI_A_ALEN_TENDATA                       _MK_ENUM_CONST(9)
+#define AXI2MC_AXI_A_ALEN_ELEVENDATA                    _MK_ENUM_CONST(10)
+#define AXI2MC_AXI_A_ALEN_TWELVEDATA                    _MK_ENUM_CONST(11)
+#define AXI2MC_AXI_A_ALEN_THIRTEENDATA                  _MK_ENUM_CONST(12)
+#define AXI2MC_AXI_A_ALEN_FOURTEENDATA                  _MK_ENUM_CONST(13)
+#define AXI2MC_AXI_A_ALEN_FIFTHTEENDATA                 _MK_ENUM_CONST(14)
+#define AXI2MC_AXI_A_ALEN_SIXTEENDATA                   _MK_ENUM_CONST(15)
+
+#define AXI2MC_AXI_A_ASIZE_SHIFT                        _MK_SHIFT_CONST(44)
+#define AXI2MC_AXI_A_ASIZE_FIELD                        (_MK_MASK_CONST(0x7) << AXI2MC_AXI_A_ASIZE_SHIFT)
+#define AXI2MC_AXI_A_ASIZE_RANGE                        _MK_SHIFT_CONST(46):_MK_SHIFT_CONST(44)
+#define AXI2MC_AXI_A_ASIZE_ROW                  0
+#define AXI2MC_AXI_A_ASIZE_ONEBYTE                      _MK_ENUM_CONST(0)
+#define AXI2MC_AXI_A_ASIZE_TWOBYTES                     _MK_ENUM_CONST(1)
+#define AXI2MC_AXI_A_ASIZE_FOURBYTES                    _MK_ENUM_CONST(2)
+#define AXI2MC_AXI_A_ASIZE_EIGHTBYTES                   _MK_ENUM_CONST(3)
+#define AXI2MC_AXI_A_ASIZE_SIXTEENBYTES                 _MK_ENUM_CONST(4)
+#define AXI2MC_AXI_A_ASIZE_THIRTYTWOBYTES                       _MK_ENUM_CONST(5)
+#define AXI2MC_AXI_A_ASIZE_SIXTYFOURBYTES                       _MK_ENUM_CONST(6)
+#define AXI2MC_AXI_A_ASIZE_ONEHUNDREDTWENTYEIGHTBYTES                   _MK_ENUM_CONST(7)
+
+#define AXI2MC_AXI_A_ABURST_SHIFT                       _MK_SHIFT_CONST(47)
+#define AXI2MC_AXI_A_ABURST_FIELD                       (_MK_MASK_CONST(0x3) << AXI2MC_AXI_A_ABURST_SHIFT)
+#define AXI2MC_AXI_A_ABURST_RANGE                       _MK_SHIFT_CONST(48):_MK_SHIFT_CONST(47)
+#define AXI2MC_AXI_A_ABURST_ROW                 0
+#define AXI2MC_AXI_A_ABURST_FIXED                       _MK_ENUM_CONST(0)
+#define AXI2MC_AXI_A_ABURST_INCR                        _MK_ENUM_CONST(1)
+#define AXI2MC_AXI_A_ABURST_WRAP                        _MK_ENUM_CONST(2)
+#define AXI2MC_AXI_A_ABURST_RSVD                        _MK_ENUM_CONST(3)
+
+#define AXI2MC_AXI_A_ALOCK_SHIFT                        _MK_SHIFT_CONST(49)
+#define AXI2MC_AXI_A_ALOCK_FIELD                        (_MK_MASK_CONST(0x3) << AXI2MC_AXI_A_ALOCK_SHIFT)
+#define AXI2MC_AXI_A_ALOCK_RANGE                        _MK_SHIFT_CONST(50):_MK_SHIFT_CONST(49)
+#define AXI2MC_AXI_A_ALOCK_ROW                  0
+#define AXI2MC_AXI_A_ALOCK_NORMAL                       _MK_ENUM_CONST(0)
+#define AXI2MC_AXI_A_ALOCK_EXCLUSIVE                    _MK_ENUM_CONST(1)
+#define AXI2MC_AXI_A_ALOCK_LOCKED                       _MK_ENUM_CONST(2)
+#define AXI2MC_AXI_A_ALOCK_RSVD                 _MK_ENUM_CONST(3)
+
+#define AXI2MC_AXI_A_ACACHE_SHIFT                       _MK_SHIFT_CONST(51)
+#define AXI2MC_AXI_A_ACACHE_FIELD                       (_MK_MASK_CONST(0xf) << AXI2MC_AXI_A_ACACHE_SHIFT)
+#define AXI2MC_AXI_A_ACACHE_RANGE                       _MK_SHIFT_CONST(54):_MK_SHIFT_CONST(51)
+#define AXI2MC_AXI_A_ACACHE_ROW                 0
+#define AXI2MC_AXI_A_ACACHE_NONCACHEABLE_NONBUFFERABLE                  _MK_ENUM_CONST(0)
+#define AXI2MC_AXI_A_ACACHE_BUFFERABLE                  _MK_ENUM_CONST(1)
+#define AXI2MC_AXI_A_ACACHE_CACHEABLE_DONOTALLOCATE                     _MK_ENUM_CONST(2)
+#define AXI2MC_AXI_A_ACACHE_CACHEABLE_BUFFERABLE_DONOTALLOCATE                  _MK_ENUM_CONST(3)
+#define AXI2MC_AXI_A_ACACHE_CACHEABLEWRITETHROUGH_ALLOCATEONREAD                        _MK_ENUM_CONST(6)
+#define AXI2MC_AXI_A_ACACHE_CACHEABLEWRITEBACK_ALLOCATEONREAD                   _MK_ENUM_CONST(7)
+#define AXI2MC_AXI_A_ACACHE_CACHEABLEWRITETHROUGH_ALLOCATEONWRITE                       _MK_ENUM_CONST(10)
+#define AXI2MC_AXI_A_ACACHE_CACHEABLEWRITEBACK_ALLOCATEONWRITE                  _MK_ENUM_CONST(11)
+#define AXI2MC_AXI_A_ACACHE_CACHEABLEWRITETHROUGH_ALLOCATEONREADWRITE                   _MK_ENUM_CONST(14)
+#define AXI2MC_AXI_A_ACACHE_CACHEABLEWRITEBACK_ALLOCATEONREADWRITE                      _MK_ENUM_CONST(15)
+
+#define AXI2MC_AXI_A_APROT_SHIFT                        _MK_SHIFT_CONST(55)
+#define AXI2MC_AXI_A_APROT_FIELD                        (_MK_MASK_CONST(0x7) << AXI2MC_AXI_A_APROT_SHIFT)
+#define AXI2MC_AXI_A_APROT_RANGE                        _MK_SHIFT_CONST(57):_MK_SHIFT_CONST(55)
+#define AXI2MC_AXI_A_APROT_ROW                  0
+#define AXI2MC_AXI_A_APROT_DATA_SECURE_NORMAL                   _MK_ENUM_CONST(0)
+#define AXI2MC_AXI_A_APROT_DATA_SECURE_PRIVILEGED                       _MK_ENUM_CONST(1)
+#define AXI2MC_AXI_A_APROT_DATA_NONSECURE_NORMAL                        _MK_ENUM_CONST(2)
+#define AXI2MC_AXI_A_APROT_DATA_NONSECURE_PRIVILEGED                    _MK_ENUM_CONST(3)
+#define AXI2MC_AXI_A_APROT_INST_SECURE_NORMAL                   _MK_ENUM_CONST(4)
+#define AXI2MC_AXI_A_APROT_INST_SECURE_PRIVILEGED                       _MK_ENUM_CONST(5)
+#define AXI2MC_AXI_A_APROT_INST_NONSECURE_NORMAL                        _MK_ENUM_CONST(6)
+#define AXI2MC_AXI_A_APROT_INST_NONSECURE_PRIVILEGED                    _MK_ENUM_CONST(7)
+
+
+// Packet AXI2MC_AXI_W
+#define AXI2MC_AXI_W_SIZE 297
+
+#define AXI2MC_AXI_W_WDATA_SHIFT                        _MK_SHIFT_CONST(0)
+#define AXI2MC_AXI_W_WDATA_FIELD                        (_MK_MASK_CONST(0xffffffff) << AXI2MC_AXI_W_WDATA_SHIFT)
+#define AXI2MC_AXI_W_WDATA_RANGE                        _MK_SHIFT_CONST(255):_MK_SHIFT_CONST(0)
+#define AXI2MC_AXI_W_WDATA_ROW                  0
+
+#define AXI2MC_AXI_W_WID_SHIFT                  _MK_SHIFT_CONST(256)
+#define AXI2MC_AXI_W_WID_FIELD                  (_MK_MASK_CONST(0xff) << AXI2MC_AXI_W_WID_SHIFT)
+#define AXI2MC_AXI_W_WID_RANGE                  _MK_SHIFT_CONST(263):_MK_SHIFT_CONST(256)
+#define AXI2MC_AXI_W_WID_ROW                    0
+
+#define AXI2MC_AXI_W_WSTRB_SHIFT                        _MK_SHIFT_CONST(264)
+#define AXI2MC_AXI_W_WSTRB_FIELD                        (_MK_MASK_CONST(0xffffffff) << AXI2MC_AXI_W_WSTRB_SHIFT)
+#define AXI2MC_AXI_W_WSTRB_RANGE                        _MK_SHIFT_CONST(295):_MK_SHIFT_CONST(264)
+#define AXI2MC_AXI_W_WSTRB_ROW                  0
+
+#define AXI2MC_AXI_W_WLAST_SHIFT                        _MK_SHIFT_CONST(296)
+#define AXI2MC_AXI_W_WLAST_FIELD                        (_MK_MASK_CONST(0x1) << AXI2MC_AXI_W_WLAST_SHIFT)
+#define AXI2MC_AXI_W_WLAST_RANGE                        _MK_SHIFT_CONST(296):_MK_SHIFT_CONST(296)
+#define AXI2MC_AXI_W_WLAST_ROW                  0
+#define AXI2MC_AXI_W_WLAST_DISABLED                     _MK_ENUM_CONST(0)
+#define AXI2MC_AXI_W_WLAST_ENABLED                      _MK_ENUM_CONST(1)
+
+
+// Packet AXI2MC_AXI_B
+#define AXI2MC_AXI_B_SIZE 10
+
+#define AXI2MC_AXI_B_BID_SHIFT                  _MK_SHIFT_CONST(0)
+#define AXI2MC_AXI_B_BID_FIELD                  (_MK_MASK_CONST(0xff) << AXI2MC_AXI_B_BID_SHIFT)
+#define AXI2MC_AXI_B_BID_RANGE                  _MK_SHIFT_CONST(7):_MK_SHIFT_CONST(0)
+#define AXI2MC_AXI_B_BID_ROW                    0
+
+#define AXI2MC_AXI_B_BRESP_SHIFT                        _MK_SHIFT_CONST(8)
+#define AXI2MC_AXI_B_BRESP_FIELD                        (_MK_MASK_CONST(0x3) << AXI2MC_AXI_B_BRESP_SHIFT)
+#define AXI2MC_AXI_B_BRESP_RANGE                        _MK_SHIFT_CONST(9):_MK_SHIFT_CONST(8)
+#define AXI2MC_AXI_B_BRESP_ROW                  0
+#define AXI2MC_AXI_B_BRESP_OKAY                 _MK_ENUM_CONST(0)
+#define AXI2MC_AXI_B_BRESP_EXOKAY                       _MK_ENUM_CONST(1)
+#define AXI2MC_AXI_B_BRESP_SLVERR                       _MK_ENUM_CONST(2)
+#define AXI2MC_AXI_B_BRESP_DECERR                       _MK_ENUM_CONST(3)
+
+
+// Packet AXI2MC_AXI_R
+#define AXI2MC_AXI_R_SIZE 267
+
+#define AXI2MC_AXI_R_RDATA_SHIFT                        _MK_SHIFT_CONST(0)
+#define AXI2MC_AXI_R_RDATA_FIELD                        (_MK_MASK_CONST(0xffffffff) << AXI2MC_AXI_R_RDATA_SHIFT)
+#define AXI2MC_AXI_R_RDATA_RANGE                        _MK_SHIFT_CONST(255):_MK_SHIFT_CONST(0)
+#define AXI2MC_AXI_R_RDATA_ROW                  0
+
+#define AXI2MC_AXI_R_RID_SHIFT                  _MK_SHIFT_CONST(256)
+#define AXI2MC_AXI_R_RID_FIELD                  (_MK_MASK_CONST(0xff) << AXI2MC_AXI_R_RID_SHIFT)
+#define AXI2MC_AXI_R_RID_RANGE                  _MK_SHIFT_CONST(263):_MK_SHIFT_CONST(256)
+#define AXI2MC_AXI_R_RID_ROW                    0
+
+#define AXI2MC_AXI_R_RRESP_SHIFT                        _MK_SHIFT_CONST(264)
+#define AXI2MC_AXI_R_RRESP_FIELD                        (_MK_MASK_CONST(0x3) << AXI2MC_AXI_R_RRESP_SHIFT)
+#define AXI2MC_AXI_R_RRESP_RANGE                        _MK_SHIFT_CONST(265):_MK_SHIFT_CONST(264)
+#define AXI2MC_AXI_R_RRESP_ROW                  0
+#define AXI2MC_AXI_R_RRESP_OKAY                 _MK_ENUM_CONST(0)
+#define AXI2MC_AXI_R_RRESP_EXOKAY                       _MK_ENUM_CONST(1)
+#define AXI2MC_AXI_R_RRESP_SLVERR                       _MK_ENUM_CONST(2)
+#define AXI2MC_AXI_R_RRESP_DECERR                       _MK_ENUM_CONST(3)
+
+#define AXI2MC_AXI_R_RLAST_SHIFT                        _MK_SHIFT_CONST(266)
+#define AXI2MC_AXI_R_RLAST_FIELD                        (_MK_MASK_CONST(0x1) << AXI2MC_AXI_R_RLAST_SHIFT)
+#define AXI2MC_AXI_R_RLAST_RANGE                        _MK_SHIFT_CONST(266):_MK_SHIFT_CONST(266)
+#define AXI2MC_AXI_R_RLAST_ROW                  0
+#define AXI2MC_AXI_R_RLAST_DISABLED                     _MK_ENUM_CONST(0)
+#define AXI2MC_AXI_R_RLAST_ENABLED                      _MK_ENUM_CONST(1)
+
+
+// Packet MC_AXI_RWREQ
+#define MC_AXI_RWREQ_SIZE 107
+
+#define MC_AXI_RWREQ_AADDR_SHIFT                        _MK_SHIFT_CONST(0)
+#define MC_AXI_RWREQ_AADDR_FIELD                        (_MK_MASK_CONST(0xffffffff) << MC_AXI_RWREQ_AADDR_SHIFT)
+#define MC_AXI_RWREQ_AADDR_RANGE                        _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define MC_AXI_RWREQ_AADDR_ROW                  0
+
+#define MC_AXI_RWREQ_AID_SHIFT                  _MK_SHIFT_CONST(32)
+#define MC_AXI_RWREQ_AID_FIELD                  (_MK_MASK_CONST(0xff) << MC_AXI_RWREQ_AID_SHIFT)
+#define MC_AXI_RWREQ_AID_RANGE                  _MK_SHIFT_CONST(39):_MK_SHIFT_CONST(32)
+#define MC_AXI_RWREQ_AID_ROW                    0
+
+#define MC_AXI_RWREQ_ALEN_SHIFT                 _MK_SHIFT_CONST(40)
+#define MC_AXI_RWREQ_ALEN_FIELD                 (_MK_MASK_CONST(0xf) << MC_AXI_RWREQ_ALEN_SHIFT)
+#define MC_AXI_RWREQ_ALEN_RANGE                 _MK_SHIFT_CONST(43):_MK_SHIFT_CONST(40)
+#define MC_AXI_RWREQ_ALEN_ROW                   0
+
+#define MC_AXI_RWREQ_ASIZE_SHIFT                        _MK_SHIFT_CONST(44)
+#define MC_AXI_RWREQ_ASIZE_FIELD                        (_MK_MASK_CONST(0x7) << MC_AXI_RWREQ_ASIZE_SHIFT)
+#define MC_AXI_RWREQ_ASIZE_RANGE                        _MK_SHIFT_CONST(46):_MK_SHIFT_CONST(44)
+#define MC_AXI_RWREQ_ASIZE_ROW                  2
+
+#define MC_AXI_RWREQ_ABURST_SHIFT                       _MK_SHIFT_CONST(47)
+#define MC_AXI_RWREQ_ABURST_FIELD                       (_MK_MASK_CONST(0x3) << MC_AXI_RWREQ_ABURST_SHIFT)
+#define MC_AXI_RWREQ_ABURST_RANGE                       _MK_SHIFT_CONST(48):_MK_SHIFT_CONST(47)
+#define MC_AXI_RWREQ_ABURST_ROW                 0
+#define MC_AXI_RWREQ_ABURST_FIXED                       _MK_ENUM_CONST(0)
+#define MC_AXI_RWREQ_ABURST_INCR                        _MK_ENUM_CONST(1)
+#define MC_AXI_RWREQ_ABURST_WRAP                        _MK_ENUM_CONST(2)
+#define MC_AXI_RWREQ_ABURST_RSVD                        _MK_ENUM_CONST(3)
+
+#define MC_AXI_RWREQ_ALOCK_SHIFT                        _MK_SHIFT_CONST(49)
+#define MC_AXI_RWREQ_ALOCK_FIELD                        (_MK_MASK_CONST(0x3) << MC_AXI_RWREQ_ALOCK_SHIFT)
+#define MC_AXI_RWREQ_ALOCK_RANGE                        _MK_SHIFT_CONST(50):_MK_SHIFT_CONST(49)
+#define MC_AXI_RWREQ_ALOCK_ROW                  0
+
+#define MC_AXI_RWREQ_ACACHE_SHIFT                       _MK_SHIFT_CONST(51)
+#define MC_AXI_RWREQ_ACACHE_FIELD                       (_MK_MASK_CONST(0xf) << MC_AXI_RWREQ_ACACHE_SHIFT)
+#define MC_AXI_RWREQ_ACACHE_RANGE                       _MK_SHIFT_CONST(54):_MK_SHIFT_CONST(51)
+#define MC_AXI_RWREQ_ACACHE_ROW                 0
+
+#define MC_AXI_RWREQ_APROT_SHIFT                        _MK_SHIFT_CONST(55)
+#define MC_AXI_RWREQ_APROT_FIELD                        (_MK_MASK_CONST(0x7) << MC_AXI_RWREQ_APROT_SHIFT)
+#define MC_AXI_RWREQ_APROT_RANGE                        _MK_SHIFT_CONST(57):_MK_SHIFT_CONST(55)
+#define MC_AXI_RWREQ_APROT_ROW                  0
+
+#define MC_AXI_RWREQ_ASB_SHIFT                  _MK_SHIFT_CONST(58)
+#define MC_AXI_RWREQ_ASB_FIELD                  (_MK_MASK_CONST(0x3) << MC_AXI_RWREQ_ASB_SHIFT)
+#define MC_AXI_RWREQ_ASB_RANGE                  _MK_SHIFT_CONST(59):_MK_SHIFT_CONST(58)
+#define MC_AXI_RWREQ_ASB_ROW                    0
+
+#define MC_AXI_RWREQ_ARW_SHIFT                  _MK_SHIFT_CONST(60)
+#define MC_AXI_RWREQ_ARW_FIELD                  (_MK_MASK_CONST(0x1) << MC_AXI_RWREQ_ARW_SHIFT)
+#define MC_AXI_RWREQ_ARW_RANGE                  _MK_SHIFT_CONST(60):_MK_SHIFT_CONST(60)
+#define MC_AXI_RWREQ_ARW_ROW                    0
+
+#define MC_AXI_RWREQ_ACT_AADDR_SHIFT                    _MK_SHIFT_CONST(61)
+#define MC_AXI_RWREQ_ACT_AADDR_FIELD                    (_MK_MASK_CONST(0xffffffff) << MC_AXI_RWREQ_ACT_AADDR_SHIFT)
+#define MC_AXI_RWREQ_ACT_AADDR_RANGE                    _MK_SHIFT_CONST(92):_MK_SHIFT_CONST(61)
+#define MC_AXI_RWREQ_ACT_AADDR_ROW                      0
+
+#define MC_AXI_RWREQ_ACT_ALEN_SHIFT                     _MK_SHIFT_CONST(93)
+#define MC_AXI_RWREQ_ACT_ALEN_FIELD                     (_MK_MASK_CONST(0xf) << MC_AXI_RWREQ_ACT_ALEN_SHIFT)
+#define MC_AXI_RWREQ_ACT_ALEN_RANGE                     _MK_SHIFT_CONST(96):_MK_SHIFT_CONST(93)
+#define MC_AXI_RWREQ_ACT_ALEN_ROW                       0
+
+#define MC_AXI_RWREQ_ACT_ASIZE_SHIFT                    _MK_SHIFT_CONST(97)
+#define MC_AXI_RWREQ_ACT_ASIZE_FIELD                    (_MK_MASK_CONST(0x7) << MC_AXI_RWREQ_ACT_ASIZE_SHIFT)
+#define MC_AXI_RWREQ_ACT_ASIZE_RANGE                    _MK_SHIFT_CONST(99):_MK_SHIFT_CONST(97)
+#define MC_AXI_RWREQ_ACT_ASIZE_ROW                      0
+
+#define MC_AXI_RWREQ_DOUBLEREQ_SHIFT                    _MK_SHIFT_CONST(100)
+#define MC_AXI_RWREQ_DOUBLEREQ_FIELD                    (_MK_MASK_CONST(0x1) << MC_AXI_RWREQ_DOUBLEREQ_SHIFT)
+#define MC_AXI_RWREQ_DOUBLEREQ_RANGE                    _MK_SHIFT_CONST(100):_MK_SHIFT_CONST(100)
+#define MC_AXI_RWREQ_DOUBLEREQ_ROW                      0
+
+#define MC_AXI_RWREQ_ILLEGALACC_SHIFT                   _MK_SHIFT_CONST(101)
+#define MC_AXI_RWREQ_ILLEGALACC_FIELD                   (_MK_MASK_CONST(0x1) << MC_AXI_RWREQ_ILLEGALACC_SHIFT)
+#define MC_AXI_RWREQ_ILLEGALACC_RANGE                   _MK_SHIFT_CONST(101):_MK_SHIFT_CONST(101)
+#define MC_AXI_RWREQ_ILLEGALACC_ROW                     0
+
+#define MC_AXI_RWREQ_TAG_SHIFT                  _MK_SHIFT_CONST(102)
+#define MC_AXI_RWREQ_TAG_FIELD                  (_MK_MASK_CONST(0x1f) << MC_AXI_RWREQ_TAG_SHIFT)
+#define MC_AXI_RWREQ_TAG_RANGE                  _MK_SHIFT_CONST(106):_MK_SHIFT_CONST(102)
+#define MC_AXI_RWREQ_TAG_ROW                    0
+
+
+// Packet CSR_C2MC_RESET
+#define CSR_C2MC_RESET_SIZE 1
+
+#define CSR_C2MC_RESET_RSTN_SHIFT                       _MK_SHIFT_CONST(0)
+#define CSR_C2MC_RESET_RSTN_FIELD                       (_MK_MASK_CONST(0x1) << CSR_C2MC_RESET_RSTN_SHIFT)
+#define CSR_C2MC_RESET_RSTN_RANGE                       _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CSR_C2MC_RESET_RSTN_ROW                 0
+
+
+// Packet CSR_C2MC_REQ
+#define CSR_C2MC_REQ_SIZE 32
+
+#define CSR_C2MC_REQ_ADR_SHIFT                  _MK_SHIFT_CONST(0)
+#define CSR_C2MC_REQ_ADR_FIELD                  (_MK_MASK_CONST(0xffffffff) << CSR_C2MC_REQ_ADR_SHIFT)
+#define CSR_C2MC_REQ_ADR_RANGE                  _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CSR_C2MC_REQ_ADR_ROW                    0
+
+
+// Packet CSR_C2MC_BP_REQ
+#define CSR_C2MC_BP_REQ_SIZE 48
+
+#define CSR_C2MC_BP_REQ_BASEADR_SHIFT                   _MK_SHIFT_CONST(0)
+#define CSR_C2MC_BP_REQ_BASEADR_FIELD                   (_MK_MASK_CONST(0xffffffff) << CSR_C2MC_BP_REQ_BASEADR_SHIFT)
+#define CSR_C2MC_BP_REQ_BASEADR_RANGE                   _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CSR_C2MC_BP_REQ_BASEADR_ROW                     0
+
+#define CSR_C2MC_BP_REQ_PITCH_SHIFT                     _MK_SHIFT_CONST(32)
+#define CSR_C2MC_BP_REQ_PITCH_FIELD                     (_MK_MASK_CONST(0xffff) << CSR_C2MC_BP_REQ_PITCH_SHIFT)
+#define CSR_C2MC_BP_REQ_PITCH_RANGE                     _MK_SHIFT_CONST(47):_MK_SHIFT_CONST(32)
+#define CSR_C2MC_BP_REQ_PITCH_ROW                       0
+
+
+// Packet CSR_C2MC_ADRXY
+#define CSR_C2MC_ADRXY_SIZE 30
+
+#define CSR_C2MC_ADRXY_OFFX_SHIFT                       _MK_SHIFT_CONST(0)
+#define CSR_C2MC_ADRXY_OFFX_FIELD                       (_MK_MASK_CONST(0xffff) << CSR_C2MC_ADRXY_OFFX_SHIFT)
+#define CSR_C2MC_ADRXY_OFFX_RANGE                       _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(0)
+#define CSR_C2MC_ADRXY_OFFX_ROW                 0
+
+#define CSR_C2MC_ADRXY_OFFY_SHIFT                       _MK_SHIFT_CONST(16)
+#define CSR_C2MC_ADRXY_OFFY_FIELD                       (_MK_MASK_CONST(0x3fff) << CSR_C2MC_ADRXY_OFFY_SHIFT)
+#define CSR_C2MC_ADRXY_OFFY_RANGE                       _MK_SHIFT_CONST(29):_MK_SHIFT_CONST(16)
+#define CSR_C2MC_ADRXY_OFFY_ROW                 0
+
+
+// Packet CSR_C2MC_TILE
+#define CSR_C2MC_TILE_SIZE 33
+
+#define CSR_C2MC_TILE_LINADR_SHIFT                      _MK_SHIFT_CONST(0)
+#define CSR_C2MC_TILE_LINADR_FIELD                      (_MK_MASK_CONST(0xffffffff) << CSR_C2MC_TILE_LINADR_SHIFT)
+#define CSR_C2MC_TILE_LINADR_RANGE                      _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CSR_C2MC_TILE_LINADR_ROW                        0
+
+#define CSR_C2MC_TILE_TMODE_SHIFT                       _MK_SHIFT_CONST(32)
+#define CSR_C2MC_TILE_TMODE_FIELD                       (_MK_MASK_CONST(0x1) << CSR_C2MC_TILE_TMODE_SHIFT)
+#define CSR_C2MC_TILE_TMODE_RANGE                       _MK_SHIFT_CONST(32):_MK_SHIFT_CONST(32)
+#define CSR_C2MC_TILE_TMODE_ROW                 0
+#define CSR_C2MC_TILE_TMODE_LINEAR                      _MK_ENUM_CONST(0)
+#define CSR_C2MC_TILE_TMODE_TILED                       _MK_ENUM_CONST(1)
+
+
+// Packet CSR_C2MC_RDI
+#define CSR_C2MC_RDI_SIZE 256
+
+#define CSR_C2MC_RDI_RDI_SHIFT                  _MK_SHIFT_CONST(0)
+#define CSR_C2MC_RDI_RDI_FIELD                  (_MK_MASK_CONST(0xffffffff) << CSR_C2MC_RDI_RDI_SHIFT)
+#define CSR_C2MC_RDI_RDI_RANGE                  _MK_SHIFT_CONST(255):_MK_SHIFT_CONST(0)
+#define CSR_C2MC_RDI_RDI_ROW                    0
+
+
+// Packet CSR_C2MC_HP
+#define CSR_C2MC_HP_SIZE 38
+
+// high-priority threshold
+#define CSR_C2MC_HP_HPTH_SHIFT                  _MK_SHIFT_CONST(0)
+#define CSR_C2MC_HP_HPTH_FIELD                  (_MK_MASK_CONST(0xffffffff) << CSR_C2MC_HP_HPTH_SHIFT)
+#define CSR_C2MC_HP_HPTH_RANGE                  _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CSR_C2MC_HP_HPTH_ROW                    0
+
+// high-priority timer
+#define CSR_C2MC_HP_HPTM_SHIFT                  _MK_SHIFT_CONST(32)
+#define CSR_C2MC_HP_HPTM_FIELD                  (_MK_MASK_CONST(0x3f) << CSR_C2MC_HP_HPTM_SHIFT)
+#define CSR_C2MC_HP_HPTM_RANGE                  _MK_SHIFT_CONST(37):_MK_SHIFT_CONST(32)
+#define CSR_C2MC_HP_HPTM_ROW                    0
+
+
+// Packet CSW_C2MC_RESET
+#define CSW_C2MC_RESET_SIZE 1
+
+#define CSW_C2MC_RESET_RSTN_SHIFT                       _MK_SHIFT_CONST(0)
+#define CSW_C2MC_RESET_RSTN_FIELD                       (_MK_MASK_CONST(0x1) << CSW_C2MC_RESET_RSTN_SHIFT)
+#define CSW_C2MC_RESET_RSTN_RANGE                       _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CSW_C2MC_RESET_RSTN_ROW                 0
+
+
+// Packet CSW_C2MC_REQ
+#define CSW_C2MC_REQ_SIZE 321
+
+#define CSW_C2MC_REQ_ADR_SHIFT                  _MK_SHIFT_CONST(0)
+#define CSW_C2MC_REQ_ADR_FIELD                  (_MK_MASK_CONST(0xffffffff) << CSW_C2MC_REQ_ADR_SHIFT)
+#define CSW_C2MC_REQ_ADR_RANGE                  _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CSW_C2MC_REQ_ADR_ROW                    0
+
+#define CSW_C2MC_REQ_BE_SHIFT                   _MK_SHIFT_CONST(32)
+#define CSW_C2MC_REQ_BE_FIELD                   (_MK_MASK_CONST(0xffffffff) << CSW_C2MC_REQ_BE_SHIFT)
+#define CSW_C2MC_REQ_BE_RANGE                   _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(32)
+#define CSW_C2MC_REQ_BE_ROW                     0
+
+#define CSW_C2MC_REQ_WDO_SHIFT                  _MK_SHIFT_CONST(64)
+#define CSW_C2MC_REQ_WDO_FIELD                  (_MK_MASK_CONST(0xffffffff) << CSW_C2MC_REQ_WDO_SHIFT)
+#define CSW_C2MC_REQ_WDO_RANGE                  _MK_SHIFT_CONST(319):_MK_SHIFT_CONST(64)
+#define CSW_C2MC_REQ_WDO_ROW                    0
+
+#define CSW_C2MC_REQ_TAG_SHIFT                  _MK_SHIFT_CONST(320)
+#define CSW_C2MC_REQ_TAG_FIELD                  (_MK_MASK_CONST(0x1) << CSW_C2MC_REQ_TAG_SHIFT)
+#define CSW_C2MC_REQ_TAG_RANGE                  _MK_SHIFT_CONST(320):_MK_SHIFT_CONST(320)
+#define CSW_C2MC_REQ_TAG_ROW                    0
+
+
+// Packet CSW_C2MC_BP_REQ
+#define CSW_C2MC_BP_REQ_SIZE 337
+
+#define CSW_C2MC_BP_REQ_BASEADR_SHIFT                   _MK_SHIFT_CONST(0)
+#define CSW_C2MC_BP_REQ_BASEADR_FIELD                   (_MK_MASK_CONST(0xffffffff) << CSW_C2MC_BP_REQ_BASEADR_SHIFT)
+#define CSW_C2MC_BP_REQ_BASEADR_RANGE                   _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CSW_C2MC_BP_REQ_BASEADR_ROW                     0
+
+#define CSW_C2MC_BP_REQ_PITCH_SHIFT                     _MK_SHIFT_CONST(32)
+#define CSW_C2MC_BP_REQ_PITCH_FIELD                     (_MK_MASK_CONST(0xffff) << CSW_C2MC_BP_REQ_PITCH_SHIFT)
+#define CSW_C2MC_BP_REQ_PITCH_RANGE                     _MK_SHIFT_CONST(47):_MK_SHIFT_CONST(32)
+#define CSW_C2MC_BP_REQ_PITCH_ROW                       0
+
+#define CSW_C2MC_BP_REQ_BE_SHIFT                        _MK_SHIFT_CONST(48)
+#define CSW_C2MC_BP_REQ_BE_FIELD                        (_MK_MASK_CONST(0xffffffff) << CSW_C2MC_BP_REQ_BE_SHIFT)
+#define CSW_C2MC_BP_REQ_BE_RANGE                        _MK_SHIFT_CONST(79):_MK_SHIFT_CONST(48)
+#define CSW_C2MC_BP_REQ_BE_ROW                  0
+
+#define CSW_C2MC_BP_REQ_WDO_SHIFT                       _MK_SHIFT_CONST(80)
+#define CSW_C2MC_BP_REQ_WDO_FIELD                       (_MK_MASK_CONST(0xffffffff) << CSW_C2MC_BP_REQ_WDO_SHIFT)
+#define CSW_C2MC_BP_REQ_WDO_RANGE                       _MK_SHIFT_CONST(335):_MK_SHIFT_CONST(80)
+#define CSW_C2MC_BP_REQ_WDO_ROW                 0
+
+#define CSW_C2MC_BP_REQ_TAG_SHIFT                       _MK_SHIFT_CONST(336)
+#define CSW_C2MC_BP_REQ_TAG_FIELD                       (_MK_MASK_CONST(0x1) << CSW_C2MC_BP_REQ_TAG_SHIFT)
+#define CSW_C2MC_BP_REQ_TAG_RANGE                       _MK_SHIFT_CONST(336):_MK_SHIFT_CONST(336)
+#define CSW_C2MC_BP_REQ_TAG_ROW                 0
+
+
+// Packet CSW_C2MC_ADRXY
+#define CSW_C2MC_ADRXY_SIZE 30
+
+#define CSW_C2MC_ADRXY_OFFX_SHIFT                       _MK_SHIFT_CONST(0)
+#define CSW_C2MC_ADRXY_OFFX_FIELD                       (_MK_MASK_CONST(0xffff) << CSW_C2MC_ADRXY_OFFX_SHIFT)
+#define CSW_C2MC_ADRXY_OFFX_RANGE                       _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(0)
+#define CSW_C2MC_ADRXY_OFFX_ROW                 0
+
+#define CSW_C2MC_ADRXY_OFFY_SHIFT                       _MK_SHIFT_CONST(16)
+#define CSW_C2MC_ADRXY_OFFY_FIELD                       (_MK_MASK_CONST(0x3fff) << CSW_C2MC_ADRXY_OFFY_SHIFT)
+#define CSW_C2MC_ADRXY_OFFY_RANGE                       _MK_SHIFT_CONST(29):_MK_SHIFT_CONST(16)
+#define CSW_C2MC_ADRXY_OFFY_ROW                 0
+
+
+// Packet CSW_C2MC_TILE
+#define CSW_C2MC_TILE_SIZE 33
+
+#define CSW_C2MC_TILE_LINADR_SHIFT                      _MK_SHIFT_CONST(0)
+#define CSW_C2MC_TILE_LINADR_FIELD                      (_MK_MASK_CONST(0xffffffff) << CSW_C2MC_TILE_LINADR_SHIFT)
+#define CSW_C2MC_TILE_LINADR_RANGE                      _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CSW_C2MC_TILE_LINADR_ROW                        0
+
+#define CSW_C2MC_TILE_TMODE_SHIFT                       _MK_SHIFT_CONST(32)
+#define CSW_C2MC_TILE_TMODE_FIELD                       (_MK_MASK_CONST(0x1) << CSW_C2MC_TILE_TMODE_SHIFT)
+#define CSW_C2MC_TILE_TMODE_RANGE                       _MK_SHIFT_CONST(32):_MK_SHIFT_CONST(32)
+#define CSW_C2MC_TILE_TMODE_ROW                 0
+#define CSW_C2MC_TILE_TMODE_LINEAR                      _MK_ENUM_CONST(0)
+#define CSW_C2MC_TILE_TMODE_TILED                       _MK_ENUM_CONST(1)
+
+
+// Packet CSW_C2MC_XDI
+#define CSW_C2MC_XDI_SIZE 1
+
+// fake data
+#define CSW_C2MC_XDI_XDI_SHIFT                  _MK_SHIFT_CONST(0)
+#define CSW_C2MC_XDI_XDI_FIELD                  (_MK_MASK_CONST(0x1) << CSW_C2MC_XDI_XDI_SHIFT)
+#define CSW_C2MC_XDI_XDI_RANGE                  _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CSW_C2MC_XDI_XDI_ROW                    0
+
+
+// Packet CSW_C2MC_HP
+#define CSW_C2MC_HP_SIZE 32
+
+// high-priority threshold
+#define CSW_C2MC_HP_HPTH_SHIFT                  _MK_SHIFT_CONST(0)
+#define CSW_C2MC_HP_HPTH_FIELD                  (_MK_MASK_CONST(0xffffffff) << CSW_C2MC_HP_HPTH_SHIFT)
+#define CSW_C2MC_HP_HPTH_RANGE                  _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CSW_C2MC_HP_HPTH_ROW                    0
+
+
+// Packet CSW_C2MC_WCOAL
+#define CSW_C2MC_WCOAL_SIZE 32
+
+// write-coalescing time-out
+#define CSW_C2MC_WCOAL_WCOALTM_SHIFT                    _MK_SHIFT_CONST(0)
+#define CSW_C2MC_WCOAL_WCOALTM_FIELD                    (_MK_MASK_CONST(0xffffffff) << CSW_C2MC_WCOAL_WCOALTM_SHIFT)
+#define CSW_C2MC_WCOAL_WCOALTM_RANGE                    _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CSW_C2MC_WCOAL_WCOALTM_ROW                      0
+
+
+// Packet CBR_C2MC_RESET
+#define CBR_C2MC_RESET_SIZE 1
+
+#define CBR_C2MC_RESET_RSTN_SHIFT                       _MK_SHIFT_CONST(0)
+#define CBR_C2MC_RESET_RSTN_FIELD                       (_MK_MASK_CONST(0x1) << CBR_C2MC_RESET_RSTN_SHIFT)
+#define CBR_C2MC_RESET_RSTN_RANGE                       _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CBR_C2MC_RESET_RSTN_ROW                 0
+
+
+// Packet CBR_C2MC_REQP
+#define CBR_C2MC_REQP_SIZE 263
+
+#define CBR_C2MC_REQP_ADR_SHIFT                 _MK_SHIFT_CONST(0)
+#define CBR_C2MC_REQP_ADR_FIELD                 (_MK_MASK_CONST(0xffffffff) << CBR_C2MC_REQP_ADR_SHIFT)
+#define CBR_C2MC_REQP_ADR_RANGE                 _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CBR_C2MC_REQP_ADR_ROW                   0
+
+#define CBR_C2MC_REQP_ADRU_SHIFT                        _MK_SHIFT_CONST(32)
+#define CBR_C2MC_REQP_ADRU_FIELD                        (_MK_MASK_CONST(0xffffffff) << CBR_C2MC_REQP_ADRU_SHIFT)
+#define CBR_C2MC_REQP_ADRU_RANGE                        _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(32)
+#define CBR_C2MC_REQP_ADRU_ROW                  0
+
+#define CBR_C2MC_REQP_ADRV_SHIFT                        _MK_SHIFT_CONST(64)
+#define CBR_C2MC_REQP_ADRV_FIELD                        (_MK_MASK_CONST(0xffffffff) << CBR_C2MC_REQP_ADRV_SHIFT)
+#define CBR_C2MC_REQP_ADRV_RANGE                        _MK_SHIFT_CONST(95):_MK_SHIFT_CONST(64)
+#define CBR_C2MC_REQP_ADRV_ROW                  0
+
+#define CBR_C2MC_REQP_LS_SHIFT                  _MK_SHIFT_CONST(96)
+#define CBR_C2MC_REQP_LS_FIELD                  (_MK_MASK_CONST(0xffffffff) << CBR_C2MC_REQP_LS_SHIFT)
+#define CBR_C2MC_REQP_LS_RANGE                  _MK_SHIFT_CONST(127):_MK_SHIFT_CONST(96)
+#define CBR_C2MC_REQP_LS_ROW                    0
+
+#define CBR_C2MC_REQP_LSUV_SHIFT                        _MK_SHIFT_CONST(128)
+#define CBR_C2MC_REQP_LSUV_FIELD                        (_MK_MASK_CONST(0xffffffff) << CBR_C2MC_REQP_LSUV_SHIFT)
+#define CBR_C2MC_REQP_LSUV_RANGE                        _MK_SHIFT_CONST(159):_MK_SHIFT_CONST(128)
+#define CBR_C2MC_REQP_LSUV_ROW                  0
+
+#define CBR_C2MC_REQP_HS_SHIFT                  _MK_SHIFT_CONST(160)
+#define CBR_C2MC_REQP_HS_FIELD                  (_MK_MASK_CONST(0xffffffff) << CBR_C2MC_REQP_HS_SHIFT)
+#define CBR_C2MC_REQP_HS_RANGE                  _MK_SHIFT_CONST(191):_MK_SHIFT_CONST(160)
+#define CBR_C2MC_REQP_HS_ROW                    0
+
+#define CBR_C2MC_REQP_VS_SHIFT                  _MK_SHIFT_CONST(192)
+#define CBR_C2MC_REQP_VS_FIELD                  (_MK_MASK_CONST(0xffffffff) << CBR_C2MC_REQP_VS_SHIFT)
+#define CBR_C2MC_REQP_VS_RANGE                  _MK_SHIFT_CONST(223):_MK_SHIFT_CONST(192)
+#define CBR_C2MC_REQP_VS_ROW                    0
+
+#define CBR_C2MC_REQP_DL_SHIFT                  _MK_SHIFT_CONST(224)
+#define CBR_C2MC_REQP_DL_FIELD                  (_MK_MASK_CONST(0xffffffff) << CBR_C2MC_REQP_DL_SHIFT)
+#define CBR_C2MC_REQP_DL_RANGE                  _MK_SHIFT_CONST(255):_MK_SHIFT_CONST(224)
+#define CBR_C2MC_REQP_DL_ROW                    0
+
+#define CBR_C2MC_REQP_HD_SHIFT                  _MK_SHIFT_CONST(256)
+#define CBR_C2MC_REQP_HD_FIELD                  (_MK_MASK_CONST(0x1) << CBR_C2MC_REQP_HD_SHIFT)
+#define CBR_C2MC_REQP_HD_RANGE                  _MK_SHIFT_CONST(256):_MK_SHIFT_CONST(256)
+#define CBR_C2MC_REQP_HD_ROW                    0
+
+#define CBR_C2MC_REQP_VD_SHIFT                  _MK_SHIFT_CONST(257)
+#define CBR_C2MC_REQP_VD_FIELD                  (_MK_MASK_CONST(0x1) << CBR_C2MC_REQP_VD_SHIFT)
+#define CBR_C2MC_REQP_VD_RANGE                  _MK_SHIFT_CONST(257):_MK_SHIFT_CONST(257)
+#define CBR_C2MC_REQP_VD_ROW                    0
+
+#define CBR_C2MC_REQP_VX2_SHIFT                 _MK_SHIFT_CONST(258)
+#define CBR_C2MC_REQP_VX2_FIELD                 (_MK_MASK_CONST(0x1) << CBR_C2MC_REQP_VX2_SHIFT)
+#define CBR_C2MC_REQP_VX2_RANGE                 _MK_SHIFT_CONST(258):_MK_SHIFT_CONST(258)
+#define CBR_C2MC_REQP_VX2_ROW                   0
+
+#define CBR_C2MC_REQP_LP_SHIFT                  _MK_SHIFT_CONST(259)
+#define CBR_C2MC_REQP_LP_FIELD                  (_MK_MASK_CONST(0x1) << CBR_C2MC_REQP_LP_SHIFT)
+#define CBR_C2MC_REQP_LP_RANGE                  _MK_SHIFT_CONST(259):_MK_SHIFT_CONST(259)
+#define CBR_C2MC_REQP_LP_ROW                    0
+
+#define CBR_C2MC_REQP_YUV_SHIFT                 _MK_SHIFT_CONST(260)
+#define CBR_C2MC_REQP_YUV_FIELD                 (_MK_MASK_CONST(0x7) << CBR_C2MC_REQP_YUV_SHIFT)
+#define CBR_C2MC_REQP_YUV_RANGE                 _MK_SHIFT_CONST(262):_MK_SHIFT_CONST(260)
+#define CBR_C2MC_REQP_YUV_ROW                   0
+
+
+// Packet CBR_C2MC_ADRXY
+#define CBR_C2MC_ADRXY_SIZE 44
+
+#define CBR_C2MC_ADRXY_OFFX_SHIFT                       _MK_SHIFT_CONST(0)
+#define CBR_C2MC_ADRXY_OFFX_FIELD                       (_MK_MASK_CONST(0xffff) << CBR_C2MC_ADRXY_OFFX_SHIFT)
+#define CBR_C2MC_ADRXY_OFFX_RANGE                       _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(0)
+#define CBR_C2MC_ADRXY_OFFX_ROW                 0
+
+#define CBR_C2MC_ADRXY_OFFY_SHIFT                       _MK_SHIFT_CONST(16)
+#define CBR_C2MC_ADRXY_OFFY_FIELD                       (_MK_MASK_CONST(0x3fff) << CBR_C2MC_ADRXY_OFFY_SHIFT)
+#define CBR_C2MC_ADRXY_OFFY_RANGE                       _MK_SHIFT_CONST(29):_MK_SHIFT_CONST(16)
+#define CBR_C2MC_ADRXY_OFFY_ROW                 0
+
+#define CBR_C2MC_ADRXY_OFFYUV_SHIFT                     _MK_SHIFT_CONST(30)
+#define CBR_C2MC_ADRXY_OFFYUV_FIELD                     (_MK_MASK_CONST(0x3fff) << CBR_C2MC_ADRXY_OFFYUV_SHIFT)
+#define CBR_C2MC_ADRXY_OFFYUV_RANGE                     _MK_SHIFT_CONST(43):_MK_SHIFT_CONST(30)
+#define CBR_C2MC_ADRXY_OFFYUV_ROW                       0
+
+
+// Packet CBR_C2MC_TILE
+#define CBR_C2MC_TILE_SIZE 98
+
+#define CBR_C2MC_TILE_LINADR_SHIFT                      _MK_SHIFT_CONST(0)
+#define CBR_C2MC_TILE_LINADR_FIELD                      (_MK_MASK_CONST(0xffffffff) << CBR_C2MC_TILE_LINADR_SHIFT)
+#define CBR_C2MC_TILE_LINADR_RANGE                      _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CBR_C2MC_TILE_LINADR_ROW                        0
+
+#define CBR_C2MC_TILE_LINADRU_SHIFT                     _MK_SHIFT_CONST(32)
+#define CBR_C2MC_TILE_LINADRU_FIELD                     (_MK_MASK_CONST(0xffffffff) << CBR_C2MC_TILE_LINADRU_SHIFT)
+#define CBR_C2MC_TILE_LINADRU_RANGE                     _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(32)
+#define CBR_C2MC_TILE_LINADRU_ROW                       0
+
+#define CBR_C2MC_TILE_LINADRV_SHIFT                     _MK_SHIFT_CONST(64)
+#define CBR_C2MC_TILE_LINADRV_FIELD                     (_MK_MASK_CONST(0xffffffff) << CBR_C2MC_TILE_LINADRV_SHIFT)
+#define CBR_C2MC_TILE_LINADRV_RANGE                     _MK_SHIFT_CONST(95):_MK_SHIFT_CONST(64)
+#define CBR_C2MC_TILE_LINADRV_ROW                       0
+
+#define CBR_C2MC_TILE_TMODE_SHIFT                       _MK_SHIFT_CONST(96)
+#define CBR_C2MC_TILE_TMODE_FIELD                       (_MK_MASK_CONST(0x1) << CBR_C2MC_TILE_TMODE_SHIFT)
+#define CBR_C2MC_TILE_TMODE_RANGE                       _MK_SHIFT_CONST(96):_MK_SHIFT_CONST(96)
+#define CBR_C2MC_TILE_TMODE_ROW                 0
+#define CBR_C2MC_TILE_TMODE_LINEAR                      _MK_ENUM_CONST(0)
+#define CBR_C2MC_TILE_TMODE_TILED                       _MK_ENUM_CONST(1)
+
+#define CBR_C2MC_TILE_TMODEUV_SHIFT                     _MK_SHIFT_CONST(97)
+#define CBR_C2MC_TILE_TMODEUV_FIELD                     (_MK_MASK_CONST(0x1) << CBR_C2MC_TILE_TMODEUV_SHIFT)
+#define CBR_C2MC_TILE_TMODEUV_RANGE                     _MK_SHIFT_CONST(97):_MK_SHIFT_CONST(97)
+#define CBR_C2MC_TILE_TMODEUV_ROW                       0
+#define CBR_C2MC_TILE_TMODEUV_LINEAR                    _MK_ENUM_CONST(0)
+#define CBR_C2MC_TILE_TMODEUV_TILED                     _MK_ENUM_CONST(1)
+
+
+// Packet CBR_C2MC_RDYP
+#define CBR_C2MC_RDYP_SIZE 1
+
+// fake data
+#define CBR_C2MC_RDYP_RDYP_SHIFT                        _MK_SHIFT_CONST(0)
+#define CBR_C2MC_RDYP_RDYP_FIELD                        (_MK_MASK_CONST(0x1) << CBR_C2MC_RDYP_RDYP_SHIFT)
+#define CBR_C2MC_RDYP_RDYP_RANGE                        _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CBR_C2MC_RDYP_RDYP_ROW                  0
+
+
+// Packet CBR_C2MC_OUTSTD
+#define CBR_C2MC_OUTSTD_SIZE 1
+
+#define CBR_C2MC_OUTSTD_OUTSTD_SHIFT                    _MK_SHIFT_CONST(0)
+#define CBR_C2MC_OUTSTD_OUTSTD_FIELD                    (_MK_MASK_CONST(0x1) << CBR_C2MC_OUTSTD_OUTSTD_SHIFT)
+#define CBR_C2MC_OUTSTD_OUTSTD_RANGE                    _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CBR_C2MC_OUTSTD_OUTSTD_ROW                      0
+
+
+// Packet CBR_C2MC_STOP
+#define CBR_C2MC_STOP_SIZE 1
+
+#define CBR_C2MC_STOP_STOP_SHIFT                        _MK_SHIFT_CONST(0)
+#define CBR_C2MC_STOP_STOP_FIELD                        (_MK_MASK_CONST(0x1) << CBR_C2MC_STOP_STOP_SHIFT)
+#define CBR_C2MC_STOP_STOP_RANGE                        _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CBR_C2MC_STOP_STOP_ROW                  0
+
+
+// Packet CBR_C2MC_RDI
+#define CBR_C2MC_RDI_SIZE 262
+
+#define CBR_C2MC_RDI_RDI_SHIFT                  _MK_SHIFT_CONST(0)
+#define CBR_C2MC_RDI_RDI_FIELD                  (_MK_MASK_CONST(0xffffffff) << CBR_C2MC_RDI_RDI_SHIFT)
+#define CBR_C2MC_RDI_RDI_RANGE                  _MK_SHIFT_CONST(255):_MK_SHIFT_CONST(0)
+#define CBR_C2MC_RDI_RDI_ROW                    0
+
+#define CBR_C2MC_RDI_RDILST_SHIFT                       _MK_SHIFT_CONST(256)
+#define CBR_C2MC_RDI_RDILST_FIELD                       (_MK_MASK_CONST(0x1) << CBR_C2MC_RDI_RDILST_SHIFT)
+#define CBR_C2MC_RDI_RDILST_RANGE                       _MK_SHIFT_CONST(256):_MK_SHIFT_CONST(256)
+#define CBR_C2MC_RDI_RDILST_ROW                 0
+
+#define CBR_C2MC_RDI_RDINB_SHIFT                        _MK_SHIFT_CONST(257)
+#define CBR_C2MC_RDI_RDINB_FIELD                        (_MK_MASK_CONST(0x1f) << CBR_C2MC_RDI_RDINB_SHIFT)
+#define CBR_C2MC_RDI_RDINB_RANGE                        _MK_SHIFT_CONST(261):_MK_SHIFT_CONST(257)
+#define CBR_C2MC_RDI_RDINB_ROW                  0
+
+
+// Packet CBR_C2MC_DOREQ
+#define CBR_C2MC_DOREQ_SIZE 64
+
+#define CBR_C2MC_DOREQ_ADR_SHIFT                        _MK_SHIFT_CONST(0)
+#define CBR_C2MC_DOREQ_ADR_FIELD                        (_MK_MASK_CONST(0xffffffff) << CBR_C2MC_DOREQ_ADR_SHIFT)
+#define CBR_C2MC_DOREQ_ADR_RANGE                        _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CBR_C2MC_DOREQ_ADR_ROW                  0
+
+#define CBR_C2MC_DOREQ_LS_SHIFT                 _MK_SHIFT_CONST(32)
+#define CBR_C2MC_DOREQ_LS_FIELD                 (_MK_MASK_CONST(0xffffffff) << CBR_C2MC_DOREQ_LS_SHIFT)
+#define CBR_C2MC_DOREQ_LS_RANGE                 _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(32)
+#define CBR_C2MC_DOREQ_LS_ROW                   0
+
+
+// Packet CBR_C2MC_HP
+#define CBR_C2MC_HP_SIZE 38
+
+// high-priority threshold
+#define CBR_C2MC_HP_HPTH_SHIFT                  _MK_SHIFT_CONST(0)
+#define CBR_C2MC_HP_HPTH_FIELD                  (_MK_MASK_CONST(0xffffffff) << CBR_C2MC_HP_HPTH_SHIFT)
+#define CBR_C2MC_HP_HPTH_RANGE                  _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CBR_C2MC_HP_HPTH_ROW                    0
+
+// high-priority timer
+#define CBR_C2MC_HP_HPTM_SHIFT                  _MK_SHIFT_CONST(32)
+#define CBR_C2MC_HP_HPTM_FIELD                  (_MK_MASK_CONST(0x3f) << CBR_C2MC_HP_HPTM_SHIFT)
+#define CBR_C2MC_HP_HPTM_RANGE                  _MK_SHIFT_CONST(37):_MK_SHIFT_CONST(32)
+#define CBR_C2MC_HP_HPTM_ROW                    0
+
+
+// Packet CBW_C2MC_RESET
+#define CBW_C2MC_RESET_SIZE 1
+
+#define CBW_C2MC_RESET_RSTN_SHIFT                       _MK_SHIFT_CONST(0)
+#define CBW_C2MC_RESET_RSTN_FIELD                       (_MK_MASK_CONST(0x1) << CBW_C2MC_RESET_RSTN_SHIFT)
+#define CBW_C2MC_RESET_RSTN_RANGE                       _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CBW_C2MC_RESET_RSTN_ROW                 0
+
+
+// Packet CBW_C2MC_REQP
+#define CBW_C2MC_REQP_SIZE 134
+
+#define CBW_C2MC_REQP_ADR_SHIFT                 _MK_SHIFT_CONST(0)
+#define CBW_C2MC_REQP_ADR_FIELD                 (_MK_MASK_CONST(0xffffffff) << CBW_C2MC_REQP_ADR_SHIFT)
+#define CBW_C2MC_REQP_ADR_RANGE                 _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CBW_C2MC_REQP_ADR_ROW                   0
+
+#define CBW_C2MC_REQP_LS_SHIFT                  _MK_SHIFT_CONST(32)
+#define CBW_C2MC_REQP_LS_FIELD                  (_MK_MASK_CONST(0xffffffff) << CBW_C2MC_REQP_LS_SHIFT)
+#define CBW_C2MC_REQP_LS_RANGE                  _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(32)
+#define CBW_C2MC_REQP_LS_ROW                    0
+
+#define CBW_C2MC_REQP_HS_SHIFT                  _MK_SHIFT_CONST(64)
+#define CBW_C2MC_REQP_HS_FIELD                  (_MK_MASK_CONST(0xffffffff) << CBW_C2MC_REQP_HS_SHIFT)
+#define CBW_C2MC_REQP_HS_RANGE                  _MK_SHIFT_CONST(95):_MK_SHIFT_CONST(64)
+#define CBW_C2MC_REQP_HS_ROW                    0
+
+#define CBW_C2MC_REQP_VS_SHIFT                  _MK_SHIFT_CONST(96)
+#define CBW_C2MC_REQP_VS_FIELD                  (_MK_MASK_CONST(0xffffffff) << CBW_C2MC_REQP_VS_SHIFT)
+#define CBW_C2MC_REQP_VS_RANGE                  _MK_SHIFT_CONST(127):_MK_SHIFT_CONST(96)
+#define CBW_C2MC_REQP_VS_ROW                    0
+
+#define CBW_C2MC_REQP_HD_SHIFT                  _MK_SHIFT_CONST(128)
+#define CBW_C2MC_REQP_HD_FIELD                  (_MK_MASK_CONST(0x1) << CBW_C2MC_REQP_HD_SHIFT)
+#define CBW_C2MC_REQP_HD_RANGE                  _MK_SHIFT_CONST(128):_MK_SHIFT_CONST(128)
+#define CBW_C2MC_REQP_HD_ROW                    0
+
+#define CBW_C2MC_REQP_VD_SHIFT                  _MK_SHIFT_CONST(129)
+#define CBW_C2MC_REQP_VD_FIELD                  (_MK_MASK_CONST(0x1) << CBW_C2MC_REQP_VD_SHIFT)
+#define CBW_C2MC_REQP_VD_RANGE                  _MK_SHIFT_CONST(129):_MK_SHIFT_CONST(129)
+#define CBW_C2MC_REQP_VD_ROW                    0
+
+#define CBW_C2MC_REQP_BPP_SHIFT                 _MK_SHIFT_CONST(130)
+#define CBW_C2MC_REQP_BPP_FIELD                 (_MK_MASK_CONST(0x3) << CBW_C2MC_REQP_BPP_SHIFT)
+#define CBW_C2MC_REQP_BPP_RANGE                 _MK_SHIFT_CONST(131):_MK_SHIFT_CONST(130)
+#define CBW_C2MC_REQP_BPP_ROW                   0
+
+#define CBW_C2MC_REQP_XY_SHIFT                  _MK_SHIFT_CONST(132)
+#define CBW_C2MC_REQP_XY_FIELD                  (_MK_MASK_CONST(0x1) << CBW_C2MC_REQP_XY_SHIFT)
+#define CBW_C2MC_REQP_XY_RANGE                  _MK_SHIFT_CONST(132):_MK_SHIFT_CONST(132)
+#define CBW_C2MC_REQP_XY_ROW                    0
+
+#define CBW_C2MC_REQP_PK_SHIFT                  _MK_SHIFT_CONST(133)
+#define CBW_C2MC_REQP_PK_FIELD                  (_MK_MASK_CONST(0x1) << CBW_C2MC_REQP_PK_SHIFT)
+#define CBW_C2MC_REQP_PK_RANGE                  _MK_SHIFT_CONST(133):_MK_SHIFT_CONST(133)
+#define CBW_C2MC_REQP_PK_ROW                    0
+
+
+// Packet CBW_C2MC_ADRXY
+#define CBW_C2MC_ADRXY_SIZE 30
+
+#define CBW_C2MC_ADRXY_OFFX_SHIFT                       _MK_SHIFT_CONST(0)
+#define CBW_C2MC_ADRXY_OFFX_FIELD                       (_MK_MASK_CONST(0xffff) << CBW_C2MC_ADRXY_OFFX_SHIFT)
+#define CBW_C2MC_ADRXY_OFFX_RANGE                       _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(0)
+#define CBW_C2MC_ADRXY_OFFX_ROW                 0
+
+#define CBW_C2MC_ADRXY_OFFY_SHIFT                       _MK_SHIFT_CONST(16)
+#define CBW_C2MC_ADRXY_OFFY_FIELD                       (_MK_MASK_CONST(0x3fff) << CBW_C2MC_ADRXY_OFFY_SHIFT)
+#define CBW_C2MC_ADRXY_OFFY_RANGE                       _MK_SHIFT_CONST(29):_MK_SHIFT_CONST(16)
+#define CBW_C2MC_ADRXY_OFFY_ROW                 0
+
+
+// Packet CBW_C2MC_TILE
+#define CBW_C2MC_TILE_SIZE 33
+
+#define CBW_C2MC_TILE_LINADR_SHIFT                      _MK_SHIFT_CONST(0)
+#define CBW_C2MC_TILE_LINADR_FIELD                      (_MK_MASK_CONST(0xffffffff) << CBW_C2MC_TILE_LINADR_SHIFT)
+#define CBW_C2MC_TILE_LINADR_RANGE                      _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CBW_C2MC_TILE_LINADR_ROW                        0
+
+#define CBW_C2MC_TILE_TMODE_SHIFT                       _MK_SHIFT_CONST(32)
+#define CBW_C2MC_TILE_TMODE_FIELD                       (_MK_MASK_CONST(0x1) << CBW_C2MC_TILE_TMODE_SHIFT)
+#define CBW_C2MC_TILE_TMODE_RANGE                       _MK_SHIFT_CONST(32):_MK_SHIFT_CONST(32)
+#define CBW_C2MC_TILE_TMODE_ROW                 0
+#define CBW_C2MC_TILE_TMODE_LINEAR                      _MK_ENUM_CONST(0)
+#define CBW_C2MC_TILE_TMODE_TILED                       _MK_ENUM_CONST(1)
+
+
+// Packet CBW_C2MC_RDYP
+#define CBW_C2MC_RDYP_SIZE 1
+
+// fake data
+#define CBW_C2MC_RDYP_RDYP_SHIFT                        _MK_SHIFT_CONST(0)
+#define CBW_C2MC_RDYP_RDYP_FIELD                        (_MK_MASK_CONST(0x1) << CBW_C2MC_RDYP_RDYP_SHIFT)
+#define CBW_C2MC_RDYP_RDYP_RANGE                        _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CBW_C2MC_RDYP_RDYP_ROW                  0
+
+
+// Packet CBW_C2MC_STOP
+#define CBW_C2MC_STOP_SIZE 1
+
+#define CBW_C2MC_STOP_STOP_SHIFT                        _MK_SHIFT_CONST(0)
+#define CBW_C2MC_STOP_STOP_FIELD                        (_MK_MASK_CONST(0x1) << CBW_C2MC_STOP_STOP_SHIFT)
+#define CBW_C2MC_STOP_STOP_RANGE                        _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CBW_C2MC_STOP_STOP_ROW                  0
+
+
+// Packet CBW_C2MC_XDI
+#define CBW_C2MC_XDI_SIZE 1
+
+// fake data
+#define CBW_C2MC_XDI_XDI_SHIFT                  _MK_SHIFT_CONST(0)
+#define CBW_C2MC_XDI_XDI_FIELD                  (_MK_MASK_CONST(0x1) << CBW_C2MC_XDI_XDI_SHIFT)
+#define CBW_C2MC_XDI_XDI_RANGE                  _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CBW_C2MC_XDI_XDI_ROW                    0
+
+
+// Packet CBW_C2MC_DOREQ
+#define CBW_C2MC_DOREQ_SIZE 321
+
+#define CBW_C2MC_DOREQ_ADR_SHIFT                        _MK_SHIFT_CONST(0)
+#define CBW_C2MC_DOREQ_ADR_FIELD                        (_MK_MASK_CONST(0xffffffff) << CBW_C2MC_DOREQ_ADR_SHIFT)
+#define CBW_C2MC_DOREQ_ADR_RANGE                        _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CBW_C2MC_DOREQ_ADR_ROW                  0
+
+#define CBW_C2MC_DOREQ_BE_SHIFT                 _MK_SHIFT_CONST(32)
+#define CBW_C2MC_DOREQ_BE_FIELD                 (_MK_MASK_CONST(0xffffffff) << CBW_C2MC_DOREQ_BE_SHIFT)
+#define CBW_C2MC_DOREQ_BE_RANGE                 _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(32)
+#define CBW_C2MC_DOREQ_BE_ROW                   0
+
+#define CBW_C2MC_DOREQ_WDO_SHIFT                        _MK_SHIFT_CONST(64)
+#define CBW_C2MC_DOREQ_WDO_FIELD                        (_MK_MASK_CONST(0xffffffff) << CBW_C2MC_DOREQ_WDO_SHIFT)
+#define CBW_C2MC_DOREQ_WDO_RANGE                        _MK_SHIFT_CONST(319):_MK_SHIFT_CONST(64)
+#define CBW_C2MC_DOREQ_WDO_ROW                  0
+
+#define CBW_C2MC_DOREQ_TAG_SHIFT                        _MK_SHIFT_CONST(320)
+#define CBW_C2MC_DOREQ_TAG_FIELD                        (_MK_MASK_CONST(0x1) << CBW_C2MC_DOREQ_TAG_SHIFT)
+#define CBW_C2MC_DOREQ_TAG_RANGE                        _MK_SHIFT_CONST(320):_MK_SHIFT_CONST(320)
+#define CBW_C2MC_DOREQ_TAG_ROW                  0
+
+
+// Packet CBW_C2MC_HP
+#define CBW_C2MC_HP_SIZE 32
+
+// high-priority threshold
+#define CBW_C2MC_HP_HPTH_SHIFT                  _MK_SHIFT_CONST(0)
+#define CBW_C2MC_HP_HPTH_FIELD                  (_MK_MASK_CONST(0xffffffff) << CBW_C2MC_HP_HPTH_SHIFT)
+#define CBW_C2MC_HP_HPTH_RANGE                  _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CBW_C2MC_HP_HPTH_ROW                    0
+
+
+// Packet CBW_C2MC_WCOAL
+#define CBW_C2MC_WCOAL_SIZE 32
+
+// write-coalescing time-out
+#define CBW_C2MC_WCOAL_WCOALTM_SHIFT                    _MK_SHIFT_CONST(0)
+#define CBW_C2MC_WCOAL_WCOALTM_FIELD                    (_MK_MASK_CONST(0xffffffff) << CBW_C2MC_WCOAL_WCOALTM_SHIFT)
+#define CBW_C2MC_WCOAL_WCOALTM_RANGE                    _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CBW_C2MC_WCOAL_WCOALTM_ROW                      0
+
+
+// Packet CCR_C2MC_RESET
+#define CCR_C2MC_RESET_SIZE 1
+
+#define CCR_C2MC_RESET_RSTN_SHIFT                       _MK_SHIFT_CONST(0)
+#define CCR_C2MC_RESET_RSTN_FIELD                       (_MK_MASK_CONST(0x1) << CCR_C2MC_RESET_RSTN_SHIFT)
+#define CCR_C2MC_RESET_RSTN_RANGE                       _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CCR_C2MC_RESET_RSTN_ROW                 0
+
+
+// Packet CCR_C2MC_REQ
+#define CCR_C2MC_REQ_SIZE 101
+
+#define CCR_C2MC_REQ_ADR_SHIFT                  _MK_SHIFT_CONST(0)
+#define CCR_C2MC_REQ_ADR_FIELD                  (_MK_MASK_CONST(0xffffffff) << CCR_C2MC_REQ_ADR_SHIFT)
+#define CCR_C2MC_REQ_ADR_RANGE                  _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CCR_C2MC_REQ_ADR_ROW                    0
+
+#define CCR_C2MC_REQ_LS_SHIFT                   _MK_SHIFT_CONST(32)
+#define CCR_C2MC_REQ_LS_FIELD                   (_MK_MASK_CONST(0xffffffff) << CCR_C2MC_REQ_LS_SHIFT)
+#define CCR_C2MC_REQ_LS_RANGE                   _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(32)
+#define CCR_C2MC_REQ_LS_ROW                     0
+
+// HI is apparently a reserved keyword
+#define CCR_C2MC_REQ_HINC_SHIFT                 _MK_SHIFT_CONST(64)
+#define CCR_C2MC_REQ_HINC_FIELD                 (_MK_MASK_CONST(0xffffffff) << CCR_C2MC_REQ_HINC_SHIFT)
+#define CCR_C2MC_REQ_HINC_RANGE                 _MK_SHIFT_CONST(95):_MK_SHIFT_CONST(64)
+#define CCR_C2MC_REQ_HINC_ROW                   0
+
+#define CCR_C2MC_REQ_ACMD_SHIFT                 _MK_SHIFT_CONST(96)
+#define CCR_C2MC_REQ_ACMD_FIELD                 (_MK_MASK_CONST(0x3) << CCR_C2MC_REQ_ACMD_SHIFT)
+#define CCR_C2MC_REQ_ACMD_RANGE                 _MK_SHIFT_CONST(97):_MK_SHIFT_CONST(96)
+#define CCR_C2MC_REQ_ACMD_ROW                   0
+
+#define CCR_C2MC_REQ_LN_SHIFT                   _MK_SHIFT_CONST(98)
+#define CCR_C2MC_REQ_LN_FIELD                   (_MK_MASK_CONST(0x1) << CCR_C2MC_REQ_LN_SHIFT)
+#define CCR_C2MC_REQ_LN_RANGE                   _MK_SHIFT_CONST(98):_MK_SHIFT_CONST(98)
+#define CCR_C2MC_REQ_LN_ROW                     0
+
+#define CCR_C2MC_REQ_HD_SHIFT                   _MK_SHIFT_CONST(99)
+#define CCR_C2MC_REQ_HD_FIELD                   (_MK_MASK_CONST(0x1) << CCR_C2MC_REQ_HD_SHIFT)
+#define CCR_C2MC_REQ_HD_RANGE                   _MK_SHIFT_CONST(99):_MK_SHIFT_CONST(99)
+#define CCR_C2MC_REQ_HD_ROW                     0
+
+#define CCR_C2MC_REQ_VD_SHIFT                   _MK_SHIFT_CONST(100)
+#define CCR_C2MC_REQ_VD_FIELD                   (_MK_MASK_CONST(0x1) << CCR_C2MC_REQ_VD_SHIFT)
+#define CCR_C2MC_REQ_VD_RANGE                   _MK_SHIFT_CONST(100):_MK_SHIFT_CONST(100)
+#define CCR_C2MC_REQ_VD_ROW                     0
+
+
+// Packet CCR_C2MC_RDI
+#define CCR_C2MC_RDI_SIZE 256
+
+#define CCR_C2MC_RDI_RDI_SHIFT                  _MK_SHIFT_CONST(0)
+#define CCR_C2MC_RDI_RDI_FIELD                  (_MK_MASK_CONST(0xffffffff) << CCR_C2MC_RDI_RDI_SHIFT)
+#define CCR_C2MC_RDI_RDI_RANGE                  _MK_SHIFT_CONST(255):_MK_SHIFT_CONST(0)
+#define CCR_C2MC_RDI_RDI_ROW                    0
+
+
+// Packet CCR_C2MC_HP
+#define CCR_C2MC_HP_SIZE 38
+
+// high-priority threshold
+#define CCR_C2MC_HP_HPTH_SHIFT                  _MK_SHIFT_CONST(0)
+#define CCR_C2MC_HP_HPTH_FIELD                  (_MK_MASK_CONST(0xffffffff) << CCR_C2MC_HP_HPTH_SHIFT)
+#define CCR_C2MC_HP_HPTH_RANGE                  _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CCR_C2MC_HP_HPTH_ROW                    0
+
+// high-priority timer
+#define CCR_C2MC_HP_HPTM_SHIFT                  _MK_SHIFT_CONST(32)
+#define CCR_C2MC_HP_HPTM_FIELD                  (_MK_MASK_CONST(0x3f) << CCR_C2MC_HP_HPTM_SHIFT)
+#define CCR_C2MC_HP_HPTM_RANGE                  _MK_SHIFT_CONST(37):_MK_SHIFT_CONST(32)
+#define CCR_C2MC_HP_HPTM_ROW                    0
+
+
+// Packet CCW_C2MC_RESET
+#define CCW_C2MC_RESET_SIZE 1
+
+#define CCW_C2MC_RESET_RSTN_SHIFT                       _MK_SHIFT_CONST(0)
+#define CCW_C2MC_RESET_RSTN_FIELD                       (_MK_MASK_CONST(0x1) << CCW_C2MC_RESET_RSTN_SHIFT)
+#define CCW_C2MC_RESET_RSTN_RANGE                       _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CCW_C2MC_RESET_RSTN_ROW                 0
+
+
+// Packet CCW_C2MC_REQ
+#define CCW_C2MC_REQ_SIZE 417
+
+#define CCW_C2MC_REQ_ADR_SHIFT                  _MK_SHIFT_CONST(0)
+#define CCW_C2MC_REQ_ADR_FIELD                  (_MK_MASK_CONST(0xffffffff) << CCW_C2MC_REQ_ADR_SHIFT)
+#define CCW_C2MC_REQ_ADR_RANGE                  _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CCW_C2MC_REQ_ADR_ROW                    0
+
+#define CCW_C2MC_REQ_LS_SHIFT                   _MK_SHIFT_CONST(32)
+#define CCW_C2MC_REQ_LS_FIELD                   (_MK_MASK_CONST(0xffffffff) << CCW_C2MC_REQ_LS_SHIFT)
+#define CCW_C2MC_REQ_LS_RANGE                   _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(32)
+#define CCW_C2MC_REQ_LS_ROW                     0
+
+// HI is apparently a reserved keyword
+#define CCW_C2MC_REQ_HINC_SHIFT                 _MK_SHIFT_CONST(64)
+#define CCW_C2MC_REQ_HINC_FIELD                 (_MK_MASK_CONST(0xffffffff) << CCW_C2MC_REQ_HINC_SHIFT)
+#define CCW_C2MC_REQ_HINC_RANGE                 _MK_SHIFT_CONST(95):_MK_SHIFT_CONST(64)
+#define CCW_C2MC_REQ_HINC_ROW                   0
+
+#define CCW_C2MC_REQ_ACMD_SHIFT                 _MK_SHIFT_CONST(96)
+#define CCW_C2MC_REQ_ACMD_FIELD                 (_MK_MASK_CONST(0x3) << CCW_C2MC_REQ_ACMD_SHIFT)
+#define CCW_C2MC_REQ_ACMD_RANGE                 _MK_SHIFT_CONST(97):_MK_SHIFT_CONST(96)
+#define CCW_C2MC_REQ_ACMD_ROW                   0
+
+#define CCW_C2MC_REQ_LN_SHIFT                   _MK_SHIFT_CONST(98)
+#define CCW_C2MC_REQ_LN_FIELD                   (_MK_MASK_CONST(0x1) << CCW_C2MC_REQ_LN_SHIFT)
+#define CCW_C2MC_REQ_LN_RANGE                   _MK_SHIFT_CONST(98):_MK_SHIFT_CONST(98)
+#define CCW_C2MC_REQ_LN_ROW                     0
+
+#define CCW_C2MC_REQ_HD_SHIFT                   _MK_SHIFT_CONST(99)
+#define CCW_C2MC_REQ_HD_FIELD                   (_MK_MASK_CONST(0x1) << CCW_C2MC_REQ_HD_SHIFT)
+#define CCW_C2MC_REQ_HD_RANGE                   _MK_SHIFT_CONST(99):_MK_SHIFT_CONST(99)
+#define CCW_C2MC_REQ_HD_ROW                     0
+
+#define CCW_C2MC_REQ_VD_SHIFT                   _MK_SHIFT_CONST(100)
+#define CCW_C2MC_REQ_VD_FIELD                   (_MK_MASK_CONST(0x1) << CCW_C2MC_REQ_VD_SHIFT)
+#define CCW_C2MC_REQ_VD_RANGE                   _MK_SHIFT_CONST(100):_MK_SHIFT_CONST(100)
+#define CCW_C2MC_REQ_VD_ROW                     0
+
+#define CCW_C2MC_REQ_BPP_SHIFT                  _MK_SHIFT_CONST(101)
+#define CCW_C2MC_REQ_BPP_FIELD                  (_MK_MASK_CONST(0x3) << CCW_C2MC_REQ_BPP_SHIFT)
+#define CCW_C2MC_REQ_BPP_RANGE                  _MK_SHIFT_CONST(102):_MK_SHIFT_CONST(101)
+#define CCW_C2MC_REQ_BPP_ROW                    0
+
+#define CCW_C2MC_REQ_XY_SHIFT                   _MK_SHIFT_CONST(103)
+#define CCW_C2MC_REQ_XY_FIELD                   (_MK_MASK_CONST(0x1) << CCW_C2MC_REQ_XY_SHIFT)
+#define CCW_C2MC_REQ_XY_RANGE                   _MK_SHIFT_CONST(103):_MK_SHIFT_CONST(103)
+#define CCW_C2MC_REQ_XY_ROW                     0
+
+#define CCW_C2MC_REQ_BE_SHIFT                   _MK_SHIFT_CONST(128)
+#define CCW_C2MC_REQ_BE_FIELD                   (_MK_MASK_CONST(0xffffffff) << CCW_C2MC_REQ_BE_SHIFT)
+#define CCW_C2MC_REQ_BE_RANGE                   _MK_SHIFT_CONST(159):_MK_SHIFT_CONST(128)
+#define CCW_C2MC_REQ_BE_ROW                     0
+
+#define CCW_C2MC_REQ_WDO_SHIFT                  _MK_SHIFT_CONST(160)
+#define CCW_C2MC_REQ_WDO_FIELD                  (_MK_MASK_CONST(0xffffffff) << CCW_C2MC_REQ_WDO_SHIFT)
+#define CCW_C2MC_REQ_WDO_RANGE                  _MK_SHIFT_CONST(415):_MK_SHIFT_CONST(160)
+#define CCW_C2MC_REQ_WDO_ROW                    0
+
+#define CCW_C2MC_REQ_TAG_SHIFT                  _MK_SHIFT_CONST(416)
+#define CCW_C2MC_REQ_TAG_FIELD                  (_MK_MASK_CONST(0x1) << CCW_C2MC_REQ_TAG_SHIFT)
+#define CCW_C2MC_REQ_TAG_RANGE                  _MK_SHIFT_CONST(416):_MK_SHIFT_CONST(416)
+#define CCW_C2MC_REQ_TAG_ROW                    0
+
+
+// Packet CCW_C2MC_ADRXY
+#define CCW_C2MC_ADRXY_SIZE 30
+
+#define CCW_C2MC_ADRXY_OFFX_SHIFT                       _MK_SHIFT_CONST(0)
+#define CCW_C2MC_ADRXY_OFFX_FIELD                       (_MK_MASK_CONST(0xffff) << CCW_C2MC_ADRXY_OFFX_SHIFT)
+#define CCW_C2MC_ADRXY_OFFX_RANGE                       _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(0)
+#define CCW_C2MC_ADRXY_OFFX_ROW                 0
+
+#define CCW_C2MC_ADRXY_OFFY_SHIFT                       _MK_SHIFT_CONST(16)
+#define CCW_C2MC_ADRXY_OFFY_FIELD                       (_MK_MASK_CONST(0x3fff) << CCW_C2MC_ADRXY_OFFY_SHIFT)
+#define CCW_C2MC_ADRXY_OFFY_RANGE                       _MK_SHIFT_CONST(29):_MK_SHIFT_CONST(16)
+#define CCW_C2MC_ADRXY_OFFY_ROW                 0
+
+
+// Packet CCW_C2MC_TILE
+#define CCW_C2MC_TILE_SIZE 33
+
+#define CCW_C2MC_TILE_LINADR_SHIFT                      _MK_SHIFT_CONST(0)
+#define CCW_C2MC_TILE_LINADR_FIELD                      (_MK_MASK_CONST(0xffffffff) << CCW_C2MC_TILE_LINADR_SHIFT)
+#define CCW_C2MC_TILE_LINADR_RANGE                      _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CCW_C2MC_TILE_LINADR_ROW                        0
+
+#define CCW_C2MC_TILE_TMODE_SHIFT                       _MK_SHIFT_CONST(32)
+#define CCW_C2MC_TILE_TMODE_FIELD                       (_MK_MASK_CONST(0x1) << CCW_C2MC_TILE_TMODE_SHIFT)
+#define CCW_C2MC_TILE_TMODE_RANGE                       _MK_SHIFT_CONST(32):_MK_SHIFT_CONST(32)
+#define CCW_C2MC_TILE_TMODE_ROW                 0
+#define CCW_C2MC_TILE_TMODE_LINEAR                      _MK_ENUM_CONST(0)
+#define CCW_C2MC_TILE_TMODE_TILED                       _MK_ENUM_CONST(1)
+
+
+// Packet CCW_C2MC_XDI
+#define CCW_C2MC_XDI_SIZE 1
+
+// fake data
+#define CCW_C2MC_XDI_XDI_SHIFT                  _MK_SHIFT_CONST(0)
+#define CCW_C2MC_XDI_XDI_FIELD                  (_MK_MASK_CONST(0x1) << CCW_C2MC_XDI_XDI_SHIFT)
+#define CCW_C2MC_XDI_XDI_RANGE                  _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CCW_C2MC_XDI_XDI_ROW                    0
+
+
+// Packet CCW_C2MC_HP
+#define CCW_C2MC_HP_SIZE 32
+
+// high-priority threshold
+#define CCW_C2MC_HP_HPTH_SHIFT                  _MK_SHIFT_CONST(0)
+#define CCW_C2MC_HP_HPTH_FIELD                  (_MK_MASK_CONST(0xffffffff) << CCW_C2MC_HP_HPTH_SHIFT)
+#define CCW_C2MC_HP_HPTH_RANGE                  _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CCW_C2MC_HP_HPTH_ROW                    0
+
+
+// Packet CCW_C2MC_WCOAL
+#define CCW_C2MC_WCOAL_SIZE 32
+
+// write-coalescing time-out
+#define CCW_C2MC_WCOAL_WCOALTM_SHIFT                    _MK_SHIFT_CONST(0)
+#define CCW_C2MC_WCOAL_WCOALTM_FIELD                    (_MK_MASK_CONST(0xffffffff) << CCW_C2MC_WCOAL_WCOALTM_SHIFT)
+#define CCW_C2MC_WCOAL_WCOALTM_RANGE                    _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CCW_C2MC_WCOAL_WCOALTM_ROW                      0
+
+
+// Packet SC_MCCIF_ASYNC
+#define SC_MCCIF_ASYNC_SIZE 4
+
+#define SC_MCCIF_ASYNC_RDCL_RDFAST_SHIFT                        _MK_SHIFT_CONST(0)
+#define SC_MCCIF_ASYNC_RDCL_RDFAST_FIELD                        (_MK_MASK_CONST(0x1) << SC_MCCIF_ASYNC_RDCL_RDFAST_SHIFT)
+#define SC_MCCIF_ASYNC_RDCL_RDFAST_RANGE                        _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define SC_MCCIF_ASYNC_RDCL_RDFAST_ROW                  0
+
+#define SC_MCCIF_ASYNC_RDMC_RDFAST_SHIFT                        _MK_SHIFT_CONST(1)
+#define SC_MCCIF_ASYNC_RDMC_RDFAST_FIELD                        (_MK_MASK_CONST(0x1) << SC_MCCIF_ASYNC_RDMC_RDFAST_SHIFT)
+#define SC_MCCIF_ASYNC_RDMC_RDFAST_RANGE                        _MK_SHIFT_CONST(1):_MK_SHIFT_CONST(1)
+#define SC_MCCIF_ASYNC_RDMC_RDFAST_ROW                  0
+
+#define SC_MCCIF_ASYNC_WRCL_MCLE2X_SHIFT                        _MK_SHIFT_CONST(2)
+#define SC_MCCIF_ASYNC_WRCL_MCLE2X_FIELD                        (_MK_MASK_CONST(0x1) << SC_MCCIF_ASYNC_WRCL_MCLE2X_SHIFT)
+#define SC_MCCIF_ASYNC_WRCL_MCLE2X_RANGE                        _MK_SHIFT_CONST(2):_MK_SHIFT_CONST(2)
+#define SC_MCCIF_ASYNC_WRCL_MCLE2X_ROW                  0
+
+#define SC_MCCIF_ASYNC_WRMC_CLLE2X_SHIFT                        _MK_SHIFT_CONST(3)
+#define SC_MCCIF_ASYNC_WRMC_CLLE2X_FIELD                        (_MK_MASK_CONST(0x1) << SC_MCCIF_ASYNC_WRMC_CLLE2X_SHIFT)
+#define SC_MCCIF_ASYNC_WRMC_CLLE2X_RANGE                        _MK_SHIFT_CONST(3):_MK_SHIFT_CONST(3)
+#define SC_MCCIF_ASYNC_WRMC_CLLE2X_ROW                  0
+
+
+//
+// REGISTER LIST
+//
+#define LIST_ARMC_REGS(_op_) \
+_op_(MC_INTSTATUS_0) \
+_op_(MC_INTMASK_0) \
+_op_(MC_EMEM_CFG_0) \
+_op_(MC_EMEM_ADR_CFG_0) \
+_op_(MC_EMEM_ARB_CFG0_0) \
+_op_(MC_EMEM_ARB_CFG1_0) \
+_op_(MC_GART_CONFIG_0) \
+_op_(MC_GART_ENTRY_ADDR_0) \
+_op_(MC_GART_ENTRY_DATA_0) \
+_op_(MC_GART_ERROR_REQ_0) \
+_op_(MC_GART_ERROR_ADDR_0) \
+_op_(MC_PARTITION_CONFLICT_CFG_0) \
+_op_(MC_TIMEOUT_CTRL_0) \
+_op_(MC_DECERR_AXI_STATUS_0) \
+_op_(MC_DECERR_AXI_ADR_0) \
+_op_(MC_DECERR_EMEM_OTHERS_STATUS_0) \
+_op_(MC_DECERR_EMEM_OTHERS_ADR_0) \
+_op_(MC_CLKEN_OVERRIDE_0) \
+_op_(MC_STAT_CONTROL_0) \
+_op_(MC_STAT_STATUS_0) \
+_op_(MC_STAT_EMC_ADDR_LOW_0) \
+_op_(MC_STAT_EMC_ADDR_HIGH_0) \
+_op_(MC_STAT_EMC_CLOCK_LIMIT_0) \
+_op_(MC_STAT_EMC_CLOCKS_0) \
+_op_(MC_STAT_EMC_CONTROL_0_0) \
+_op_(MC_STAT_EMC_CONTROL_1_0) \
+_op_(MC_STAT_EMC_HIST_LIMIT_0_0) \
+_op_(MC_STAT_EMC_HIST_LIMIT_1_0) \
+_op_(MC_STAT_EMC_COUNT_0_0) \
+_op_(MC_STAT_EMC_COUNT_1_0) \
+_op_(MC_STAT_EMC_HIST_0_0) \
+_op_(MC_STAT_EMC_HIST_1_0) \
+_op_(MC_CLIENT_CTRL_0) \
+_op_(MC_CLIENT_HOTRESETN_0) \
+_op_(MC_CMC_ORRC_0) \
+_op_(MC_DC_ORRC_0) \
+_op_(MC_DCB_ORRC_0) \
+_op_(MC_EPP_ORRC_0) \
+_op_(MC_G2_ORRC_0) \
+_op_(MC_HC_ORRC_0) \
+_op_(MC_ISP_ORRC_0) \
+_op_(MC_MPCORE_ORRC_0) \
+_op_(MC_MPEA_ORRC_0) \
+_op_(MC_MPEB_ORRC_0) \
+_op_(MC_MPEC_ORRC_0) \
+_op_(MC_NV_ORRC_0) \
+_op_(MC_PPCS_ORRC_0) \
+_op_(MC_VDE_ORRC_0) \
+_op_(MC_VI_ORRC_0) \
+_op_(MC_AP_CTRL_0_0) \
+_op_(MC_AP_CTRL_1_0) \
+_op_(MC_FPRI_CTRL_CMC_0) \
+_op_(MC_FPRI_CTRL_DC_0) \
+_op_(MC_FPRI_CTRL_DCB_0) \
+_op_(MC_FPRI_CTRL_EPP_0) \
+_op_(MC_FPRI_CTRL_G2_0) \
+_op_(MC_FPRI_CTRL_HC_0) \
+_op_(MC_FPRI_CTRL_ISP_0) \
+_op_(MC_FPRI_CTRL_MPCORE_0) \
+_op_(MC_FPRI_CTRL_MPEA_0) \
+_op_(MC_FPRI_CTRL_MPEB_0) \
+_op_(MC_FPRI_CTRL_MPEC_0) \
+_op_(MC_FPRI_CTRL_NV_0) \
+_op_(MC_FPRI_CTRL_PPCS_0) \
+_op_(MC_FPRI_CTRL_VDE_0) \
+_op_(MC_FPRI_CTRL_VI_0) \
+_op_(MC_TIMEOUT_CMC_0) \
+_op_(MC_TIMEOUT_DC_0) \
+_op_(MC_TIMEOUT_DCB_0) \
+_op_(MC_TIMEOUT_EPP_0) \
+_op_(MC_TIMEOUT_G2_0) \
+_op_(MC_TIMEOUT_HC_0) \
+_op_(MC_TIMEOUT_ISP_0) \
+_op_(MC_TIMEOUT_MPCORE_0) \
+_op_(MC_TIMEOUT_MPEA_0) \
+_op_(MC_TIMEOUT_MPEB_0) \
+_op_(MC_TIMEOUT_MPEC_0) \
+_op_(MC_TIMEOUT_NV_0) \
+_op_(MC_TIMEOUT_PPCS_0) \
+_op_(MC_TIMEOUT_VDE_0) \
+_op_(MC_TIMEOUT1_VDE_0) \
+_op_(MC_TIMEOUT_VI_0) \
+_op_(MC_TIMEOUT_RCOAL_CMC_0) \
+_op_(MC_TIMEOUT_RCOAL_DC_0) \
+_op_(MC_TIMEOUT_RCOAL_DCB_0) \
+_op_(MC_TIMEOUT_RCOAL_EPP_0) \
+_op_(MC_TIMEOUT_RCOAL_G2_0) \
+_op_(MC_TIMEOUT_RCOAL_HC_0) \
+_op_(MC_TIMEOUT_RCOAL_MPCORE_0) \
+_op_(MC_TIMEOUT_RCOAL_MPEA_0) \
+_op_(MC_TIMEOUT_RCOAL_MPEB_0) \
+_op_(MC_TIMEOUT_RCOAL_MPEC_0) \
+_op_(MC_TIMEOUT_RCOAL_NV_0) \
+_op_(MC_TIMEOUT_RCOAL_PPCS_0) \
+_op_(MC_TIMEOUT_RCOAL_VDE_0) \
+_op_(MC_TIMEOUT_RCOAL_VI_0) \
+_op_(MC_BWSHARE_EMEM_CTRL_0_0) \
+_op_(MC_BWSHARE_EMEM_CTRL_1_0) \
+_op_(MC_BWSHARE_CMC_0) \
+_op_(MC_BWSHARE_DISPLAY_0) \
+_op_(MC_BWSHARE_DISPLAYB_0) \
+_op_(MC_BWSHARE_EPP_0) \
+_op_(MC_BWSHARE_FDC_0) \
+_op_(MC_BWSHARE_GR2D_0) \
+_op_(MC_BWSHARE_HOST1X_0) \
+_op_(MC_BWSHARE_IDX_0) \
+_op_(MC_BWSHARE_ISP_0) \
+_op_(MC_BWSHARE_MPCORE_0) \
+_op_(MC_BWSHARE_MPEA_0) \
+_op_(MC_BWSHARE_MPEB_0) \
+_op_(MC_BWSHARE_MPEC_0) \
+_op_(MC_BWSHARE_PPCS_0) \
+_op_(MC_BWSHARE_TEX_0) \
+_op_(MC_BWSHARE_VDE_0) \
+_op_(MC_BWSHARE_VI_0) \
+_op_(MC_BWSHARE_TMVAL_0) \
+_op_(MC_AXI_DECERR_OVR_0) \
+_op_(MC_LOWLATENCY_CONFIG_0) \
+_op_(MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0) \
+_op_(MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0) \
+_op_(MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0)
+
+
+//
+// ADDRESS SPACES
+//
+
+#define BASE_ADDRESS_MC 0x00000000
+
+//
+// ARMC REGISTER BANKS
+//
+
+#define MC0_FIRST_REG 0x0000 // MC_INTSTATUS_0
+#define MC0_LAST_REG 0x0004 // MC_INTMASK_0
+#define MC1_FIRST_REG 0x000c // MC_EMEM_CFG_0
+#define MC1_LAST_REG 0x0034 // MC_TIMEOUT_CTRL_0
+#define MC2_FIRST_REG 0x0040 // MC_DECERR_AXI_STATUS_0
+#define MC2_LAST_REG 0x0044 // MC_DECERR_AXI_ADR_0
+#define MC3_FIRST_REG 0x0050 // MC_DECERR_EMEM_OTHERS_STATUS_0
+#define MC3_LAST_REG 0x0054 // MC_DECERR_EMEM_OTHERS_ADR_0
+#define MC4_FIRST_REG 0x0060 // MC_CLKEN_OVERRIDE_0
+#define MC4_LAST_REG 0x01fc // MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0
+
+#ifndef _MK_SHIFT_CONST
+  #define _MK_SHIFT_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_MASK_CONST
+  #define _MK_MASK_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_ENUM_CONST
+  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
+#endif
+#ifndef _MK_ADDR_CONST
+  #define _MK_ADDR_CONST(_constant_) _constant_
+#endif
+
+#endif // ifndef ___ARMC_H_INC_
diff --git a/arch/arm/mach-tegra/include/ap15/arpwfm.h b/arch/arm/mach-tegra/include/ap15/arpwfm.h
new file mode 100644
index 000000000000..2139d4bfa51a
--- /dev/null
+++ b/arch/arm/mach-tegra/include/ap15/arpwfm.h
@@ -0,0 +1,271 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+//
+// DO NOT EDIT - generated by simspec!
+//
+
+#ifndef ___ARPWFM_H_INC_
+#define ___ARPWFM_H_INC_
+
+// Register PWM_CONTROLLER_PWM_CSR_0_0  
+#define PWM_CONTROLLER_PWM_CSR_0_0                      _MK_ADDR_CONST(0x0)
+#define PWM_CONTROLLER_PWM_CSR_0_0_WORD_COUNT                   0x1
+#define PWM_CONTROLLER_PWM_CSR_0_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define PWM_CONTROLLER_PWM_CSR_0_0_RESET_MASK                   _MK_MASK_CONST(0x80ff1fff)
+#define PWM_CONTROLLER_PWM_CSR_0_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define PWM_CONTROLLER_PWM_CSR_0_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define PWM_CONTROLLER_PWM_CSR_0_0_READ_MASK                    _MK_MASK_CONST(0x80ff1fff)
+#define PWM_CONTROLLER_PWM_CSR_0_0_WRITE_MASK                   _MK_MASK_CONST(0x80ff1fff)
+// Enable Pulse width modulator
+#define PWM_CONTROLLER_PWM_CSR_0_0_ENB_SHIFT                    _MK_SHIFT_CONST(31)
+#define PWM_CONTROLLER_PWM_CSR_0_0_ENB_FIELD                    (_MK_MASK_CONST(0x1) << PWM_CONTROLLER_PWM_CSR_0_0_ENB_SHIFT)
+#define PWM_CONTROLLER_PWM_CSR_0_0_ENB_RANGE                    31:31
+#define PWM_CONTROLLER_PWM_CSR_0_0_ENB_WOFFSET                  0x0
+#define PWM_CONTROLLER_PWM_CSR_0_0_ENB_DEFAULT                  _MK_MASK_CONST(0x0)
+#define PWM_CONTROLLER_PWM_CSR_0_0_ENB_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define PWM_CONTROLLER_PWM_CSR_0_0_ENB_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define PWM_CONTROLLER_PWM_CSR_0_0_ENB_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define PWM_CONTROLLER_PWM_CSR_0_0_ENB_DISABLE                  _MK_ENUM_CONST(0)
+#define PWM_CONTROLLER_PWM_CSR_0_0_ENB_ENABLE                   _MK_ENUM_CONST(1)
+
+// pulse width thats needs to be programmed. 
+//0=Always low 1=1/256 Pulse high 2=2/256 Pulse  High .N=N/256 Pulse high
+#define PWM_CONTROLLER_PWM_CSR_0_0_PWM_0_SHIFT                  _MK_SHIFT_CONST(16)
+#define PWM_CONTROLLER_PWM_CSR_0_0_PWM_0_FIELD                  (_MK_MASK_CONST(0xff) << PWM_CONTROLLER_PWM_CSR_0_0_PWM_0_SHIFT)
+#define PWM_CONTROLLER_PWM_CSR_0_0_PWM_0_RANGE                  23:16
+#define PWM_CONTROLLER_PWM_CSR_0_0_PWM_0_WOFFSET                        0x0
+#define PWM_CONTROLLER_PWM_CSR_0_0_PWM_0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define PWM_CONTROLLER_PWM_CSR_0_0_PWM_0_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
+#define PWM_CONTROLLER_PWM_CSR_0_0_PWM_0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define PWM_CONTROLLER_PWM_CSR_0_0_PWM_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Frequency divider that needs to be Programmed. 
+#define PWM_CONTROLLER_PWM_CSR_0_0_PFM_0_SHIFT                  _MK_SHIFT_CONST(0)
+#define PWM_CONTROLLER_PWM_CSR_0_0_PFM_0_FIELD                  (_MK_MASK_CONST(0x1fff) << PWM_CONTROLLER_PWM_CSR_0_0_PFM_0_SHIFT)
+#define PWM_CONTROLLER_PWM_CSR_0_0_PFM_0_RANGE                  12:0
+#define PWM_CONTROLLER_PWM_CSR_0_0_PFM_0_WOFFSET                        0x0
+#define PWM_CONTROLLER_PWM_CSR_0_0_PFM_0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define PWM_CONTROLLER_PWM_CSR_0_0_PFM_0_DEFAULT_MASK                   _MK_MASK_CONST(0x1fff)
+#define PWM_CONTROLLER_PWM_CSR_0_0_PFM_0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define PWM_CONTROLLER_PWM_CSR_0_0_PFM_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Reserved address 4 [0x4] 
+
+// Reserved address 8 [0x8] 
+
+// Reserved address 12 [0xc] 
+
+// Register PWM_CONTROLLER_PWM_CSR_1_0  
+#define PWM_CONTROLLER_PWM_CSR_1_0                      _MK_ADDR_CONST(0x10)
+#define PWM_CONTROLLER_PWM_CSR_1_0_WORD_COUNT                   0x1
+#define PWM_CONTROLLER_PWM_CSR_1_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define PWM_CONTROLLER_PWM_CSR_1_0_RESET_MASK                   _MK_MASK_CONST(0x80ff1fff)
+#define PWM_CONTROLLER_PWM_CSR_1_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define PWM_CONTROLLER_PWM_CSR_1_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define PWM_CONTROLLER_PWM_CSR_1_0_READ_MASK                    _MK_MASK_CONST(0x80ff1fff)
+#define PWM_CONTROLLER_PWM_CSR_1_0_WRITE_MASK                   _MK_MASK_CONST(0x80ff1fff)
+//  Enable pulse width modulator 
+#define PWM_CONTROLLER_PWM_CSR_1_0_ENB_SHIFT                    _MK_SHIFT_CONST(31)
+#define PWM_CONTROLLER_PWM_CSR_1_0_ENB_FIELD                    (_MK_MASK_CONST(0x1) << PWM_CONTROLLER_PWM_CSR_1_0_ENB_SHIFT)
+#define PWM_CONTROLLER_PWM_CSR_1_0_ENB_RANGE                    31:31
+#define PWM_CONTROLLER_PWM_CSR_1_0_ENB_WOFFSET                  0x0
+#define PWM_CONTROLLER_PWM_CSR_1_0_ENB_DEFAULT                  _MK_MASK_CONST(0x0)
+#define PWM_CONTROLLER_PWM_CSR_1_0_ENB_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define PWM_CONTROLLER_PWM_CSR_1_0_ENB_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define PWM_CONTROLLER_PWM_CSR_1_0_ENB_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define PWM_CONTROLLER_PWM_CSR_1_0_ENB_DISABLE                  _MK_ENUM_CONST(0)
+#define PWM_CONTROLLER_PWM_CSR_1_0_ENB_ENABLE                   _MK_ENUM_CONST(1)
+
+// pulse width that needs to be programmed
+// 0=Always low 1=1/256 Pulse high 2=2/256 Pulse  High .N=N/256 Pulse high
+#define PWM_CONTROLLER_PWM_CSR_1_0_PWM_0_SHIFT                  _MK_SHIFT_CONST(16)
+#define PWM_CONTROLLER_PWM_CSR_1_0_PWM_0_FIELD                  (_MK_MASK_CONST(0xff) << PWM_CONTROLLER_PWM_CSR_1_0_PWM_0_SHIFT)
+#define PWM_CONTROLLER_PWM_CSR_1_0_PWM_0_RANGE                  23:16
+#define PWM_CONTROLLER_PWM_CSR_1_0_PWM_0_WOFFSET                        0x0
+#define PWM_CONTROLLER_PWM_CSR_1_0_PWM_0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define PWM_CONTROLLER_PWM_CSR_1_0_PWM_0_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
+#define PWM_CONTROLLER_PWM_CSR_1_0_PWM_0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define PWM_CONTROLLER_PWM_CSR_1_0_PWM_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Frequency divider that needs to be Programmed. 
+#define PWM_CONTROLLER_PWM_CSR_1_0_PFM_1_SHIFT                  _MK_SHIFT_CONST(0)
+#define PWM_CONTROLLER_PWM_CSR_1_0_PFM_1_FIELD                  (_MK_MASK_CONST(0x1fff) << PWM_CONTROLLER_PWM_CSR_1_0_PFM_1_SHIFT)
+#define PWM_CONTROLLER_PWM_CSR_1_0_PFM_1_RANGE                  12:0
+#define PWM_CONTROLLER_PWM_CSR_1_0_PFM_1_WOFFSET                        0x0
+#define PWM_CONTROLLER_PWM_CSR_1_0_PFM_1_DEFAULT                        _MK_MASK_CONST(0x0)
+#define PWM_CONTROLLER_PWM_CSR_1_0_PFM_1_DEFAULT_MASK                   _MK_MASK_CONST(0x1fff)
+#define PWM_CONTROLLER_PWM_CSR_1_0_PFM_1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define PWM_CONTROLLER_PWM_CSR_1_0_PFM_1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Reserved address 20 [0x14] 
+
+// Reserved address 24 [0x18] 
+
+// Reserved address 28 [0x1c] 
+
+// Register PWM_CONTROLLER_PWM_CSR_2_0  
+#define PWM_CONTROLLER_PWM_CSR_2_0                      _MK_ADDR_CONST(0x20)
+#define PWM_CONTROLLER_PWM_CSR_2_0_WORD_COUNT                   0x1
+#define PWM_CONTROLLER_PWM_CSR_2_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define PWM_CONTROLLER_PWM_CSR_2_0_RESET_MASK                   _MK_MASK_CONST(0x80ff1fff)
+#define PWM_CONTROLLER_PWM_CSR_2_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define PWM_CONTROLLER_PWM_CSR_2_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define PWM_CONTROLLER_PWM_CSR_2_0_READ_MASK                    _MK_MASK_CONST(0x80ff1fff)
+#define PWM_CONTROLLER_PWM_CSR_2_0_WRITE_MASK                   _MK_MASK_CONST(0x80ff1fff)
+//  Enable pulse width modulator 
+#define PWM_CONTROLLER_PWM_CSR_2_0_ENB_SHIFT                    _MK_SHIFT_CONST(31)
+#define PWM_CONTROLLER_PWM_CSR_2_0_ENB_FIELD                    (_MK_MASK_CONST(0x1) << PWM_CONTROLLER_PWM_CSR_2_0_ENB_SHIFT)
+#define PWM_CONTROLLER_PWM_CSR_2_0_ENB_RANGE                    31:31
+#define PWM_CONTROLLER_PWM_CSR_2_0_ENB_WOFFSET                  0x0
+#define PWM_CONTROLLER_PWM_CSR_2_0_ENB_DEFAULT                  _MK_MASK_CONST(0x0)
+#define PWM_CONTROLLER_PWM_CSR_2_0_ENB_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define PWM_CONTROLLER_PWM_CSR_2_0_ENB_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define PWM_CONTROLLER_PWM_CSR_2_0_ENB_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define PWM_CONTROLLER_PWM_CSR_2_0_ENB_DISABLE                  _MK_ENUM_CONST(0)
+#define PWM_CONTROLLER_PWM_CSR_2_0_ENB_ENABLE                   _MK_ENUM_CONST(1)
+
+// Pulse Width that needs to be programmed.
+// 0=Always low 1=1/256 Pulse high 2=2/256 Pulse  High .N=N/256 Pulse high
+#define PWM_CONTROLLER_PWM_CSR_2_0_PWM_0_SHIFT                  _MK_SHIFT_CONST(16)
+#define PWM_CONTROLLER_PWM_CSR_2_0_PWM_0_FIELD                  (_MK_MASK_CONST(0xff) << PWM_CONTROLLER_PWM_CSR_2_0_PWM_0_SHIFT)
+#define PWM_CONTROLLER_PWM_CSR_2_0_PWM_0_RANGE                  23:16
+#define PWM_CONTROLLER_PWM_CSR_2_0_PWM_0_WOFFSET                        0x0
+#define PWM_CONTROLLER_PWM_CSR_2_0_PWM_0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define PWM_CONTROLLER_PWM_CSR_2_0_PWM_0_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
+#define PWM_CONTROLLER_PWM_CSR_2_0_PWM_0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define PWM_CONTROLLER_PWM_CSR_2_0_PWM_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Frequency divider that needs to be Programmed. 
+#define PWM_CONTROLLER_PWM_CSR_2_0_PFM_2_SHIFT                  _MK_SHIFT_CONST(0)
+#define PWM_CONTROLLER_PWM_CSR_2_0_PFM_2_FIELD                  (_MK_MASK_CONST(0x1fff) << PWM_CONTROLLER_PWM_CSR_2_0_PFM_2_SHIFT)
+#define PWM_CONTROLLER_PWM_CSR_2_0_PFM_2_RANGE                  12:0
+#define PWM_CONTROLLER_PWM_CSR_2_0_PFM_2_WOFFSET                        0x0
+#define PWM_CONTROLLER_PWM_CSR_2_0_PFM_2_DEFAULT                        _MK_MASK_CONST(0x0)
+#define PWM_CONTROLLER_PWM_CSR_2_0_PFM_2_DEFAULT_MASK                   _MK_MASK_CONST(0x1fff)
+#define PWM_CONTROLLER_PWM_CSR_2_0_PFM_2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define PWM_CONTROLLER_PWM_CSR_2_0_PFM_2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Reserved address 36 [0x24] 
+
+// Reserved address 40 [0x28] 
+
+// Reserved address 44 [0x2c] 
+
+// Register PWM_CONTROLLER_PWM_CSR_3_0  
+#define PWM_CONTROLLER_PWM_CSR_3_0                      _MK_ADDR_CONST(0x30)
+#define PWM_CONTROLLER_PWM_CSR_3_0_WORD_COUNT                   0x1
+#define PWM_CONTROLLER_PWM_CSR_3_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define PWM_CONTROLLER_PWM_CSR_3_0_RESET_MASK                   _MK_MASK_CONST(0x80ff1fff)
+#define PWM_CONTROLLER_PWM_CSR_3_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define PWM_CONTROLLER_PWM_CSR_3_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define PWM_CONTROLLER_PWM_CSR_3_0_READ_MASK                    _MK_MASK_CONST(0x80ff1fff)
+#define PWM_CONTROLLER_PWM_CSR_3_0_WRITE_MASK                   _MK_MASK_CONST(0x80ff1fff)
+//  Enable pulse width modulator 
+#define PWM_CONTROLLER_PWM_CSR_3_0_ENB_SHIFT                    _MK_SHIFT_CONST(31)
+#define PWM_CONTROLLER_PWM_CSR_3_0_ENB_FIELD                    (_MK_MASK_CONST(0x1) << PWM_CONTROLLER_PWM_CSR_3_0_ENB_SHIFT)
+#define PWM_CONTROLLER_PWM_CSR_3_0_ENB_RANGE                    31:31
+#define PWM_CONTROLLER_PWM_CSR_3_0_ENB_WOFFSET                  0x0
+#define PWM_CONTROLLER_PWM_CSR_3_0_ENB_DEFAULT                  _MK_MASK_CONST(0x0)
+#define PWM_CONTROLLER_PWM_CSR_3_0_ENB_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define PWM_CONTROLLER_PWM_CSR_3_0_ENB_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define PWM_CONTROLLER_PWM_CSR_3_0_ENB_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define PWM_CONTROLLER_PWM_CSR_3_0_ENB_DISABLE                  _MK_ENUM_CONST(0)
+#define PWM_CONTROLLER_PWM_CSR_3_0_ENB_ENABLE                   _MK_ENUM_CONST(1)
+
+// pulse width  that needs to be programmed
+// 0=Always low 1=1/256 Pulse high 2=2/256 Pulse  High .N=N/256 Pulse high
+#define PWM_CONTROLLER_PWM_CSR_3_0_PWM_0_SHIFT                  _MK_SHIFT_CONST(16)
+#define PWM_CONTROLLER_PWM_CSR_3_0_PWM_0_FIELD                  (_MK_MASK_CONST(0xff) << PWM_CONTROLLER_PWM_CSR_3_0_PWM_0_SHIFT)
+#define PWM_CONTROLLER_PWM_CSR_3_0_PWM_0_RANGE                  23:16
+#define PWM_CONTROLLER_PWM_CSR_3_0_PWM_0_WOFFSET                        0x0
+#define PWM_CONTROLLER_PWM_CSR_3_0_PWM_0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define PWM_CONTROLLER_PWM_CSR_3_0_PWM_0_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
+#define PWM_CONTROLLER_PWM_CSR_3_0_PWM_0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define PWM_CONTROLLER_PWM_CSR_3_0_PWM_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Frequency divider that needs to be Programmed. 
+#define PWM_CONTROLLER_PWM_CSR_3_0_PFM_3_SHIFT                  _MK_SHIFT_CONST(0)
+#define PWM_CONTROLLER_PWM_CSR_3_0_PFM_3_FIELD                  (_MK_MASK_CONST(0x1fff) << PWM_CONTROLLER_PWM_CSR_3_0_PFM_3_SHIFT)
+#define PWM_CONTROLLER_PWM_CSR_3_0_PFM_3_RANGE                  12:0
+#define PWM_CONTROLLER_PWM_CSR_3_0_PFM_3_WOFFSET                        0x0
+#define PWM_CONTROLLER_PWM_CSR_3_0_PFM_3_DEFAULT                        _MK_MASK_CONST(0x0)
+#define PWM_CONTROLLER_PWM_CSR_3_0_PFM_3_DEFAULT_MASK                   _MK_MASK_CONST(0x1fff)
+#define PWM_CONTROLLER_PWM_CSR_3_0_PFM_3_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define PWM_CONTROLLER_PWM_CSR_3_0_PFM_3_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+//
+// REGISTER LIST
+//
+#define LIST_ARPWFM_REGS(_op_) \
+_op_(PWM_CONTROLLER_PWM_CSR_0_0) \
+_op_(PWM_CONTROLLER_PWM_CSR_1_0) \
+_op_(PWM_CONTROLLER_PWM_CSR_2_0) \
+_op_(PWM_CONTROLLER_PWM_CSR_3_0)
+
+
+//
+// ADDRESS SPACES
+//
+
+#define BASE_ADDRESS_PWM_CONTROLLER     0x00000000
+
+//
+// ARPWFM REGISTER BANKS
+//
+
+#define PWM_CONTROLLER0_FIRST_REG 0x0000 // PWM_CONTROLLER_PWM_CSR_0_0
+#define PWM_CONTROLLER0_LAST_REG 0x0000 // PWM_CONTROLLER_PWM_CSR_0_0
+#define PWM_CONTROLLER1_FIRST_REG 0x0010 // PWM_CONTROLLER_PWM_CSR_1_0
+#define PWM_CONTROLLER1_LAST_REG 0x0010 // PWM_CONTROLLER_PWM_CSR_1_0
+#define PWM_CONTROLLER2_FIRST_REG 0x0020 // PWM_CONTROLLER_PWM_CSR_2_0
+#define PWM_CONTROLLER2_LAST_REG 0x0020 // PWM_CONTROLLER_PWM_CSR_2_0
+#define PWM_CONTROLLER3_FIRST_REG 0x0030 // PWM_CONTROLLER_PWM_CSR_3_0
+#define PWM_CONTROLLER3_LAST_REG 0x0030 // PWM_CONTROLLER_PWM_CSR_3_0
+
+#ifndef _MK_SHIFT_CONST
+  #define _MK_SHIFT_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_MASK_CONST
+  #define _MK_MASK_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_ENUM_CONST
+  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
+#endif
+#ifndef _MK_ADDR_CONST
+  #define _MK_ADDR_CONST(_constant_) _constant_
+#endif
+
+#endif // ifndef ___ARPWFM_H_INC_
diff --git a/arch/arm/mach-tegra/include/ap15/arres_sema.h b/arch/arm/mach-tegra/include/ap15/arres_sema.h
new file mode 100644
index 000000000000..093439d20511
--- /dev/null
+++ b/arch/arm/mach-tegra/include/ap15/arres_sema.h
@@ -0,0 +1,325 @@
+/*
+ * Copyright (c) 2010 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+//
+// DO NOT EDIT - generated by simspec!
+//
+
+#ifndef ___ARRES_SEMA_H_INC_
+#define ___ARRES_SEMA_H_INC_
+// Shared Resource Semaphore Status
+
+// Register RES_SEMA_SHRD_SMP_STA_0  
+#define RES_SEMA_SHRD_SMP_STA_0                 _MK_ADDR_CONST(0x0)
+#define RES_SEMA_SHRD_SMP_STA_0_WORD_COUNT                      0x1
+#define RES_SEMA_SHRD_SMP_STA_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define RES_SEMA_SHRD_SMP_STA_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define RES_SEMA_SHRD_SMP_STA_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define RES_SEMA_SHRD_SMP_STA_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define RES_SEMA_SHRD_SMP_STA_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define RES_SEMA_SHRD_SMP_STA_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
+// SMP.27:SMP.24: Available in APB_DMA.REQUESTORS  register
+#define RES_SEMA_SHRD_SMP_STA_0_SMP_31_SMP_0_SHIFT                      _MK_SHIFT_CONST(0)
+#define RES_SEMA_SHRD_SMP_STA_0_SMP_31_SMP_0_FIELD                      (_MK_MASK_CONST(0xffffffff) << RES_SEMA_SHRD_SMP_STA_0_SMP_31_SMP_0_SHIFT)
+#define RES_SEMA_SHRD_SMP_STA_0_SMP_31_SMP_0_RANGE                      31:0
+#define RES_SEMA_SHRD_SMP_STA_0_SMP_31_SMP_0_WOFFSET                    0x0
+#define RES_SEMA_SHRD_SMP_STA_0_SMP_31_SMP_0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define RES_SEMA_SHRD_SMP_STA_0_SMP_31_SMP_0_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
+#define RES_SEMA_SHRD_SMP_STA_0_SMP_31_SMP_0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define RES_SEMA_SHRD_SMP_STA_0_SMP_31_SMP_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Shared Resource Semaphore Set-bit Request
+
+// Register RES_SEMA_SHRD_SMP_SET_0  
+#define RES_SEMA_SHRD_SMP_SET_0                 _MK_ADDR_CONST(0x4)
+#define RES_SEMA_SHRD_SMP_SET_0_WORD_COUNT                      0x1
+#define RES_SEMA_SHRD_SMP_SET_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define RES_SEMA_SHRD_SMP_SET_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define RES_SEMA_SHRD_SMP_SET_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define RES_SEMA_SHRD_SMP_SET_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define RES_SEMA_SHRD_SMP_SET_0_READ_MASK                       _MK_MASK_CONST(0x0)
+#define RES_SEMA_SHRD_SMP_SET_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Semaphore set register. Writing a one to any bit  will set the corresponding semaphore bit. Shared resource set-bit requests
+#define RES_SEMA_SHRD_SMP_SET_0_SET_31_SET_0_SHIFT                      _MK_SHIFT_CONST(0)
+#define RES_SEMA_SHRD_SMP_SET_0_SET_31_SET_0_FIELD                      (_MK_MASK_CONST(0xffffffff) << RES_SEMA_SHRD_SMP_SET_0_SET_31_SET_0_SHIFT)
+#define RES_SEMA_SHRD_SMP_SET_0_SET_31_SET_0_RANGE                      31:0
+#define RES_SEMA_SHRD_SMP_SET_0_SET_31_SET_0_WOFFSET                    0x0
+#define RES_SEMA_SHRD_SMP_SET_0_SET_31_SET_0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define RES_SEMA_SHRD_SMP_SET_0_SET_31_SET_0_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
+#define RES_SEMA_SHRD_SMP_SET_0_SET_31_SET_0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define RES_SEMA_SHRD_SMP_SET_0_SET_31_SET_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Shared Resource Semaphore Clr-bit Request Register
+
+// Register RES_SEMA_SHRD_SMP_CLR_0  
+#define RES_SEMA_SHRD_SMP_CLR_0                 _MK_ADDR_CONST(0x8)
+#define RES_SEMA_SHRD_SMP_CLR_0_WORD_COUNT                      0x1
+#define RES_SEMA_SHRD_SMP_CLR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define RES_SEMA_SHRD_SMP_CLR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define RES_SEMA_SHRD_SMP_CLR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define RES_SEMA_SHRD_SMP_CLR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define RES_SEMA_SHRD_SMP_CLR_0_READ_MASK                       _MK_MASK_CONST(0x0)
+#define RES_SEMA_SHRD_SMP_CLR_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
+// corresponding semaphore bit
+#define RES_SEMA_SHRD_SMP_CLR_0_CLR_31_CLR_0_SHIFT                      _MK_SHIFT_CONST(0)
+#define RES_SEMA_SHRD_SMP_CLR_0_CLR_31_CLR_0_FIELD                      (_MK_MASK_CONST(0xffffffff) << RES_SEMA_SHRD_SMP_CLR_0_CLR_31_CLR_0_SHIFT)
+#define RES_SEMA_SHRD_SMP_CLR_0_CLR_31_CLR_0_RANGE                      31:0
+#define RES_SEMA_SHRD_SMP_CLR_0_CLR_31_CLR_0_WOFFSET                    0x0
+#define RES_SEMA_SHRD_SMP_CLR_0_CLR_31_CLR_0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define RES_SEMA_SHRD_SMP_CLR_0_CLR_31_CLR_0_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
+#define RES_SEMA_SHRD_SMP_CLR_0_CLR_31_CLR_0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define RES_SEMA_SHRD_SMP_CLR_0_CLR_31_CLR_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Reserved address 12 [0xc] 
+// Shared Resource Inbox (messages from COP to CPU)
+
+// Register RES_SEMA_SHRD_INBOX_0  
+#define RES_SEMA_SHRD_INBOX_0                   _MK_ADDR_CONST(0x10)
+#define RES_SEMA_SHRD_INBOX_0_WORD_COUNT                        0x1
+#define RES_SEMA_SHRD_INBOX_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define RES_SEMA_SHRD_INBOX_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
+#define RES_SEMA_SHRD_INBOX_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define RES_SEMA_SHRD_INBOX_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define RES_SEMA_SHRD_INBOX_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define RES_SEMA_SHRD_INBOX_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+// Interrupt CPU on INBOX Full (TAG=1)
+#define RES_SEMA_SHRD_INBOX_0_IE_IBF_SHIFT                      _MK_SHIFT_CONST(31)
+#define RES_SEMA_SHRD_INBOX_0_IE_IBF_FIELD                      (_MK_MASK_CONST(0x1) << RES_SEMA_SHRD_INBOX_0_IE_IBF_SHIFT)
+#define RES_SEMA_SHRD_INBOX_0_IE_IBF_RANGE                      31:31
+#define RES_SEMA_SHRD_INBOX_0_IE_IBF_WOFFSET                    0x0
+#define RES_SEMA_SHRD_INBOX_0_IE_IBF_DEFAULT                    _MK_MASK_CONST(0x0)
+#define RES_SEMA_SHRD_INBOX_0_IE_IBF_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define RES_SEMA_SHRD_INBOX_0_IE_IBF_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define RES_SEMA_SHRD_INBOX_0_IE_IBF_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define RES_SEMA_SHRD_INBOX_0_IE_IBF_EMPTY                      _MK_ENUM_CONST(0)
+#define RES_SEMA_SHRD_INBOX_0_IE_IBF_FULL                       _MK_ENUM_CONST(1)
+
+// Interrupt COP on INBOX Empty (TAG=0)
+#define RES_SEMA_SHRD_INBOX_0_IE_IBE_SHIFT                      _MK_SHIFT_CONST(30)
+#define RES_SEMA_SHRD_INBOX_0_IE_IBE_FIELD                      (_MK_MASK_CONST(0x1) << RES_SEMA_SHRD_INBOX_0_IE_IBE_SHIFT)
+#define RES_SEMA_SHRD_INBOX_0_IE_IBE_RANGE                      30:30
+#define RES_SEMA_SHRD_INBOX_0_IE_IBE_WOFFSET                    0x0
+#define RES_SEMA_SHRD_INBOX_0_IE_IBE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define RES_SEMA_SHRD_INBOX_0_IE_IBE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define RES_SEMA_SHRD_INBOX_0_IE_IBE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define RES_SEMA_SHRD_INBOX_0_IE_IBE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define RES_SEMA_SHRD_INBOX_0_IE_IBE_EMPTY                      _MK_ENUM_CONST(0)
+#define RES_SEMA_SHRD_INBOX_0_IE_IBE_FULL                       _MK_ENUM_CONST(1)
+
+// Read-only. Set when COP writes this register and  cleared when CPU Reads this register.
+#define RES_SEMA_SHRD_INBOX_0_TAG_SHIFT                 _MK_SHIFT_CONST(29)
+#define RES_SEMA_SHRD_INBOX_0_TAG_FIELD                 (_MK_MASK_CONST(0x1) << RES_SEMA_SHRD_INBOX_0_TAG_SHIFT)
+#define RES_SEMA_SHRD_INBOX_0_TAG_RANGE                 29:29
+#define RES_SEMA_SHRD_INBOX_0_TAG_WOFFSET                       0x0
+#define RES_SEMA_SHRD_INBOX_0_TAG_DEFAULT                       _MK_MASK_CONST(0x0)
+#define RES_SEMA_SHRD_INBOX_0_TAG_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define RES_SEMA_SHRD_INBOX_0_TAG_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define RES_SEMA_SHRD_INBOX_0_TAG_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define RES_SEMA_SHRD_INBOX_0_TAG_INVALID                       _MK_ENUM_CONST(0)
+#define RES_SEMA_SHRD_INBOX_0_TAG_VALID                 _MK_ENUM_CONST(1)
+
+// Reserved = 0
+#define RES_SEMA_SHRD_INBOX_0_N_A1_SHIFT                        _MK_SHIFT_CONST(28)
+#define RES_SEMA_SHRD_INBOX_0_N_A1_FIELD                        (_MK_MASK_CONST(0x1) << RES_SEMA_SHRD_INBOX_0_N_A1_SHIFT)
+#define RES_SEMA_SHRD_INBOX_0_N_A1_RANGE                        28:28
+#define RES_SEMA_SHRD_INBOX_0_N_A1_WOFFSET                      0x0
+#define RES_SEMA_SHRD_INBOX_0_N_A1_DEFAULT                      _MK_MASK_CONST(0x0)
+#define RES_SEMA_SHRD_INBOX_0_N_A1_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define RES_SEMA_SHRD_INBOX_0_N_A1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define RES_SEMA_SHRD_INBOX_0_N_A1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// definition)
+#define RES_SEMA_SHRD_INBOX_0_IN_BOX_STAT_SHIFT                 _MK_SHIFT_CONST(24)
+#define RES_SEMA_SHRD_INBOX_0_IN_BOX_STAT_FIELD                 (_MK_MASK_CONST(0xf) << RES_SEMA_SHRD_INBOX_0_IN_BOX_STAT_SHIFT)
+#define RES_SEMA_SHRD_INBOX_0_IN_BOX_STAT_RANGE                 27:24
+#define RES_SEMA_SHRD_INBOX_0_IN_BOX_STAT_WOFFSET                       0x0
+#define RES_SEMA_SHRD_INBOX_0_IN_BOX_STAT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define RES_SEMA_SHRD_INBOX_0_IN_BOX_STAT_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define RES_SEMA_SHRD_INBOX_0_IN_BOX_STAT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define RES_SEMA_SHRD_INBOX_0_IN_BOX_STAT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// General purpose data bits, suggested usage is for  INBOX command (SW can change definition)
+#define RES_SEMA_SHRD_INBOX_0_IN_BOX_CMD_SHIFT                  _MK_SHIFT_CONST(17)
+#define RES_SEMA_SHRD_INBOX_0_IN_BOX_CMD_FIELD                  (_MK_MASK_CONST(0x7f) << RES_SEMA_SHRD_INBOX_0_IN_BOX_CMD_SHIFT)
+#define RES_SEMA_SHRD_INBOX_0_IN_BOX_CMD_RANGE                  23:17
+#define RES_SEMA_SHRD_INBOX_0_IN_BOX_CMD_WOFFSET                        0x0
+#define RES_SEMA_SHRD_INBOX_0_IN_BOX_CMD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define RES_SEMA_SHRD_INBOX_0_IN_BOX_CMD_DEFAULT_MASK                   _MK_MASK_CONST(0x7f)
+#define RES_SEMA_SHRD_INBOX_0_IN_BOX_CMD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define RES_SEMA_SHRD_INBOX_0_IN_BOX_CMD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// definition)
+#define RES_SEMA_SHRD_INBOX_0_IN_BOX_DATA_SHIFT                 _MK_SHIFT_CONST(0)
+#define RES_SEMA_SHRD_INBOX_0_IN_BOX_DATA_FIELD                 (_MK_MASK_CONST(0x1ffff) << RES_SEMA_SHRD_INBOX_0_IN_BOX_DATA_SHIFT)
+#define RES_SEMA_SHRD_INBOX_0_IN_BOX_DATA_RANGE                 16:0
+#define RES_SEMA_SHRD_INBOX_0_IN_BOX_DATA_WOFFSET                       0x0
+#define RES_SEMA_SHRD_INBOX_0_IN_BOX_DATA_DEFAULT                       _MK_MASK_CONST(0x0)
+#define RES_SEMA_SHRD_INBOX_0_IN_BOX_DATA_DEFAULT_MASK                  _MK_MASK_CONST(0x1ffff)
+#define RES_SEMA_SHRD_INBOX_0_IN_BOX_DATA_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define RES_SEMA_SHRD_INBOX_0_IN_BOX_DATA_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Reserved address 20 [0x14] 
+
+// Reserved address 24 [0x18] 
+
+// Reserved address 28 [0x1c] 
+// Shared Resource Outbox (messages from CPU to COP)
+
+// Register RES_SEMA_SHRD_OUTBOX_0  
+#define RES_SEMA_SHRD_OUTBOX_0                  _MK_ADDR_CONST(0x20)
+#define RES_SEMA_SHRD_OUTBOX_0_WORD_COUNT                       0x1
+#define RES_SEMA_SHRD_OUTBOX_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define RES_SEMA_SHRD_OUTBOX_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
+#define RES_SEMA_SHRD_OUTBOX_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define RES_SEMA_SHRD_OUTBOX_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define RES_SEMA_SHRD_OUTBOX_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define RES_SEMA_SHRD_OUTBOX_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
+// Interrupt COP on OUTBOX Full (TAG=1)
+#define RES_SEMA_SHRD_OUTBOX_0_IE_OBF_SHIFT                     _MK_SHIFT_CONST(31)
+#define RES_SEMA_SHRD_OUTBOX_0_IE_OBF_FIELD                     (_MK_MASK_CONST(0x1) << RES_SEMA_SHRD_OUTBOX_0_IE_OBF_SHIFT)
+#define RES_SEMA_SHRD_OUTBOX_0_IE_OBF_RANGE                     31:31
+#define RES_SEMA_SHRD_OUTBOX_0_IE_OBF_WOFFSET                   0x0
+#define RES_SEMA_SHRD_OUTBOX_0_IE_OBF_DEFAULT                   _MK_MASK_CONST(0x0)
+#define RES_SEMA_SHRD_OUTBOX_0_IE_OBF_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define RES_SEMA_SHRD_OUTBOX_0_IE_OBF_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define RES_SEMA_SHRD_OUTBOX_0_IE_OBF_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define RES_SEMA_SHRD_OUTBOX_0_IE_OBF_EMPTY                     _MK_ENUM_CONST(0)
+#define RES_SEMA_SHRD_OUTBOX_0_IE_OBF_FULL                      _MK_ENUM_CONST(1)
+
+// Interrupt CPU on OUTBOX Empty (TAG=0)
+#define RES_SEMA_SHRD_OUTBOX_0_IE_OBE_SHIFT                     _MK_SHIFT_CONST(30)
+#define RES_SEMA_SHRD_OUTBOX_0_IE_OBE_FIELD                     (_MK_MASK_CONST(0x1) << RES_SEMA_SHRD_OUTBOX_0_IE_OBE_SHIFT)
+#define RES_SEMA_SHRD_OUTBOX_0_IE_OBE_RANGE                     30:30
+#define RES_SEMA_SHRD_OUTBOX_0_IE_OBE_WOFFSET                   0x0
+#define RES_SEMA_SHRD_OUTBOX_0_IE_OBE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define RES_SEMA_SHRD_OUTBOX_0_IE_OBE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define RES_SEMA_SHRD_OUTBOX_0_IE_OBE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define RES_SEMA_SHRD_OUTBOX_0_IE_OBE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define RES_SEMA_SHRD_OUTBOX_0_IE_OBE_EMPTY                     _MK_ENUM_CONST(0)
+#define RES_SEMA_SHRD_OUTBOX_0_IE_OBE_FULL                      _MK_ENUM_CONST(1)
+
+// HW clears this bit when COP Reads the Outbox Register.  Read-only. Set when CPU writes this register and cleared when COP reads this  register.
+#define RES_SEMA_SHRD_OUTBOX_0_TAG_SHIFT                        _MK_SHIFT_CONST(29)
+#define RES_SEMA_SHRD_OUTBOX_0_TAG_FIELD                        (_MK_MASK_CONST(0x1) << RES_SEMA_SHRD_OUTBOX_0_TAG_SHIFT)
+#define RES_SEMA_SHRD_OUTBOX_0_TAG_RANGE                        29:29
+#define RES_SEMA_SHRD_OUTBOX_0_TAG_WOFFSET                      0x0
+#define RES_SEMA_SHRD_OUTBOX_0_TAG_DEFAULT                      _MK_MASK_CONST(0x0)
+#define RES_SEMA_SHRD_OUTBOX_0_TAG_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define RES_SEMA_SHRD_OUTBOX_0_TAG_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define RES_SEMA_SHRD_OUTBOX_0_TAG_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define RES_SEMA_SHRD_OUTBOX_0_TAG_INVALID                      _MK_ENUM_CONST(0)
+#define RES_SEMA_SHRD_OUTBOX_0_TAG_VALID                        _MK_ENUM_CONST(1)
+
+// Reserved = 0
+#define RES_SEMA_SHRD_OUTBOX_0_N_A1_SHIFT                       _MK_SHIFT_CONST(28)
+#define RES_SEMA_SHRD_OUTBOX_0_N_A1_FIELD                       (_MK_MASK_CONST(0x1) << RES_SEMA_SHRD_OUTBOX_0_N_A1_SHIFT)
+#define RES_SEMA_SHRD_OUTBOX_0_N_A1_RANGE                       28:28
+#define RES_SEMA_SHRD_OUTBOX_0_N_A1_WOFFSET                     0x0
+#define RES_SEMA_SHRD_OUTBOX_0_N_A1_DEFAULT                     _MK_MASK_CONST(0x0)
+#define RES_SEMA_SHRD_OUTBOX_0_N_A1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define RES_SEMA_SHRD_OUTBOX_0_N_A1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define RES_SEMA_SHRD_OUTBOX_0_N_A1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// General purpose data bits, suggested usage is for  Out Box OUTBOX status (SW can change definition)
+#define RES_SEMA_SHRD_OUTBOX_0_OUT_BOX_STAT_SHIFT                       _MK_SHIFT_CONST(24)
+#define RES_SEMA_SHRD_OUTBOX_0_OUT_BOX_STAT_FIELD                       (_MK_MASK_CONST(0xf) << RES_SEMA_SHRD_OUTBOX_0_OUT_BOX_STAT_SHIFT)
+#define RES_SEMA_SHRD_OUTBOX_0_OUT_BOX_STAT_RANGE                       27:24
+#define RES_SEMA_SHRD_OUTBOX_0_OUT_BOX_STAT_WOFFSET                     0x0
+#define RES_SEMA_SHRD_OUTBOX_0_OUT_BOX_STAT_DEFAULT                     _MK_MASK_CONST(0x0)
+#define RES_SEMA_SHRD_OUTBOX_0_OUT_BOX_STAT_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define RES_SEMA_SHRD_OUTBOX_0_OUT_BOX_STAT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define RES_SEMA_SHRD_OUTBOX_0_OUT_BOX_STAT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// General purpose data bits, suggested usage is for  Out Box OUTBOX command (SW can change definition)
+#define RES_SEMA_SHRD_OUTBOX_0_OUT_BOX_CMD_SHIFT                        _MK_SHIFT_CONST(17)
+#define RES_SEMA_SHRD_OUTBOX_0_OUT_BOX_CMD_FIELD                        (_MK_MASK_CONST(0x7f) << RES_SEMA_SHRD_OUTBOX_0_OUT_BOX_CMD_SHIFT)
+#define RES_SEMA_SHRD_OUTBOX_0_OUT_BOX_CMD_RANGE                        23:17
+#define RES_SEMA_SHRD_OUTBOX_0_OUT_BOX_CMD_WOFFSET                      0x0
+#define RES_SEMA_SHRD_OUTBOX_0_OUT_BOX_CMD_DEFAULT                      _MK_MASK_CONST(0x0)
+#define RES_SEMA_SHRD_OUTBOX_0_OUT_BOX_CMD_DEFAULT_MASK                 _MK_MASK_CONST(0x7f)
+#define RES_SEMA_SHRD_OUTBOX_0_OUT_BOX_CMD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define RES_SEMA_SHRD_OUTBOX_0_OUT_BOX_CMD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// General purpose Out Box data bits, suggested usage  is for OUTBOX data (SW can change definition)
+#define RES_SEMA_SHRD_OUTBOX_0_OUT_BOX_DATA_SHIFT                       _MK_SHIFT_CONST(0)
+#define RES_SEMA_SHRD_OUTBOX_0_OUT_BOX_DATA_FIELD                       (_MK_MASK_CONST(0x1ffff) << RES_SEMA_SHRD_OUTBOX_0_OUT_BOX_DATA_SHIFT)
+#define RES_SEMA_SHRD_OUTBOX_0_OUT_BOX_DATA_RANGE                       16:0
+#define RES_SEMA_SHRD_OUTBOX_0_OUT_BOX_DATA_WOFFSET                     0x0
+#define RES_SEMA_SHRD_OUTBOX_0_OUT_BOX_DATA_DEFAULT                     _MK_MASK_CONST(0x0)
+#define RES_SEMA_SHRD_OUTBOX_0_OUT_BOX_DATA_DEFAULT_MASK                        _MK_MASK_CONST(0x1ffff)
+#define RES_SEMA_SHRD_OUTBOX_0_OUT_BOX_DATA_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define RES_SEMA_SHRD_OUTBOX_0_OUT_BOX_DATA_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+//
+// REGISTER LIST
+//
+#define LIST_ARRES_SEMA_REGS(_op_) \
+_op_(RES_SEMA_SHRD_SMP_STA_0) \
+_op_(RES_SEMA_SHRD_SMP_SET_0) \
+_op_(RES_SEMA_SHRD_SMP_CLR_0) \
+_op_(RES_SEMA_SHRD_INBOX_0) \
+_op_(RES_SEMA_SHRD_OUTBOX_0)
+
+
+//
+// ADDRESS SPACES
+//
+
+#define BASE_ADDRESS_RES_SEMA   0x00000000
+
+//
+// ARRES_SEMA REGISTER BANKS
+//
+
+#define RES_SEMA0_FIRST_REG 0x0000 // RES_SEMA_SHRD_SMP_STA_0
+#define RES_SEMA0_LAST_REG 0x0008 // RES_SEMA_SHRD_SMP_CLR_0
+#define RES_SEMA1_FIRST_REG 0x0010 // RES_SEMA_SHRD_INBOX_0
+#define RES_SEMA1_LAST_REG 0x0010 // RES_SEMA_SHRD_INBOX_0
+#define RES_SEMA2_FIRST_REG 0x0020 // RES_SEMA_SHRD_OUTBOX_0
+#define RES_SEMA2_LAST_REG 0x0020 // RES_SEMA_SHRD_OUTBOX_0
+
+#ifndef _MK_SHIFT_CONST
+  #define _MK_SHIFT_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_MASK_CONST
+  #define _MK_MASK_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_ENUM_CONST
+  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
+#endif
+#ifndef _MK_ADDR_CONST
+  #define _MK_ADDR_CONST(_constant_) _constant_
+#endif
+
+#endif // ifndef ___ARRES_SEMA_H_INC_
diff --git a/arch/arm/mach-tegra/include/ap15/arslink.h b/arch/arm/mach-tegra/include/ap15/arslink.h
new file mode 100644
index 000000000000..36c5031de57d
--- /dev/null
+++ b/arch/arm/mach-tegra/include/ap15/arslink.h
@@ -0,0 +1,1178 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+//
+// DO NOT EDIT - generated by simspec!
+//
+
+#ifndef ___ARSLINK_H_INC_
+#define ___ARSLINK_H_INC_
+
+// Register SLINK_COMMAND_0  
+#define SLINK_COMMAND_0                 _MK_ADDR_CONST(0x0)
+#define SLINK_COMMAND_0_WORD_COUNT                      0x1
+#define SLINK_COMMAND_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define SLINK_COMMAND_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define SLINK_COMMAND_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// RD/WD access to Data Register would start the next  transfer. (This allows continuous Receive via RD of Buffer and Automated  Transmit per WD of Buffer Register)
+#define SLINK_COMMAND_0_ENB_SHIFT                       _MK_SHIFT_CONST(31)
+#define SLINK_COMMAND_0_ENB_FIELD                       (_MK_MASK_CONST(0x1) << SLINK_COMMAND_0_ENB_SHIFT)
+#define SLINK_COMMAND_0_ENB_RANGE                       31:31
+#define SLINK_COMMAND_0_ENB_WOFFSET                     0x0
+#define SLINK_COMMAND_0_ENB_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_ENB_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define SLINK_COMMAND_0_ENB_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_ENB_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_ENB_DISABLE                     _MK_ENUM_CONST(0)
+#define SLINK_COMMAND_0_ENB_ENABLE                      _MK_ENUM_CONST(1)
+
+// Program 1 after all the other bits in the COMMAND2 and COMMAND are programmed to start the trasnfer
+// HW clears this bit automatically after the trasnfer is done
+// Clearing of the bit by SW will stop the Shifter  and latch the partial data into buffer
+#define SLINK_COMMAND_0_GO_SHIFT                        _MK_SHIFT_CONST(30)
+#define SLINK_COMMAND_0_GO_FIELD                        (_MK_MASK_CONST(0x1) << SLINK_COMMAND_0_GO_SHIFT)
+#define SLINK_COMMAND_0_GO_RANGE                        30:30
+#define SLINK_COMMAND_0_GO_WOFFSET                      0x0
+#define SLINK_COMMAND_0_GO_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_GO_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define SLINK_COMMAND_0_GO_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_GO_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_GO_STOP                 _MK_ENUM_CONST(0)
+#define SLINK_COMMAND_0_GO_GO                   _MK_ENUM_CONST(1)
+
+//  1 = Hold APB Cycle from writing another data into COMMAND register until RDY 0  = NOP. Use of this bit is deprecated.
+#define SLINK_COMMAND_0_WAIT_SHIFT                      _MK_SHIFT_CONST(29)
+#define SLINK_COMMAND_0_WAIT_FIELD                      (_MK_MASK_CONST(0x1) << SLINK_COMMAND_0_WAIT_SHIFT)
+#define SLINK_COMMAND_0_WAIT_RANGE                      29:29
+#define SLINK_COMMAND_0_WAIT_WOFFSET                    0x0
+#define SLINK_COMMAND_0_WAIT_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_WAIT_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define SLINK_COMMAND_0_WAIT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_WAIT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_WAIT_NOP                        _MK_ENUM_CONST(0)
+#define SLINK_COMMAND_0_WAIT_WAIT                       _MK_ENUM_CONST(1)
+
+// 1 = Master Mode (internal Clock) 0 = Slave Mode  (external Clock)
+#define SLINK_COMMAND_0_M_S_SHIFT                       _MK_SHIFT_CONST(28)
+#define SLINK_COMMAND_0_M_S_FIELD                       (_MK_MASK_CONST(0x1) << SLINK_COMMAND_0_M_S_SHIFT)
+#define SLINK_COMMAND_0_M_S_RANGE                       28:28
+#define SLINK_COMMAND_0_M_S_WOFFSET                     0x0
+#define SLINK_COMMAND_0_M_S_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_M_S_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define SLINK_COMMAND_0_M_S_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_M_S_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_M_S_SLAVE                       _MK_ENUM_CONST(0)
+#define SLINK_COMMAND_0_M_S_MASTER                      _MK_ENUM_CONST(1)
+
+// 11 = Pull High 10 = Pull Low 01 = Driven High (o.H) 00 = Driven Low (o.L)  (def)
+#define SLINK_COMMAND_0_ACTIVE_SCLK_SHIFT                       _MK_SHIFT_CONST(26)
+#define SLINK_COMMAND_0_ACTIVE_SCLK_FIELD                       (_MK_MASK_CONST(0x3) << SLINK_COMMAND_0_ACTIVE_SCLK_SHIFT)
+#define SLINK_COMMAND_0_ACTIVE_SCLK_RANGE                       27:26
+#define SLINK_COMMAND_0_ACTIVE_SCLK_WOFFSET                     0x0
+#define SLINK_COMMAND_0_ACTIVE_SCLK_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_ACTIVE_SCLK_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define SLINK_COMMAND_0_ACTIVE_SCLK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_ACTIVE_SCLK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_ACTIVE_SCLK_DRIVE_LOW                   _MK_ENUM_CONST(0)
+#define SLINK_COMMAND_0_ACTIVE_SCLK_DRIVE_HIGH                  _MK_ENUM_CONST(1)
+#define SLINK_COMMAND_0_ACTIVE_SCLK_PULL_LOW                    _MK_ENUM_CONST(2)
+#define SLINK_COMMAND_0_ACTIVE_SCLK_PULL_HIGH                   _MK_ENUM_CONST(3)
+
+// 11 = Pull High 10 = Pull Low 01 = Driven High 00 =  Driven Low (def)
+#define SLINK_COMMAND_0_IDLE_SCLK_SHIFT                 _MK_SHIFT_CONST(24)
+#define SLINK_COMMAND_0_IDLE_SCLK_FIELD                 (_MK_MASK_CONST(0x3) << SLINK_COMMAND_0_IDLE_SCLK_SHIFT)
+#define SLINK_COMMAND_0_IDLE_SCLK_RANGE                 25:24
+#define SLINK_COMMAND_0_IDLE_SCLK_WOFFSET                       0x0
+#define SLINK_COMMAND_0_IDLE_SCLK_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_IDLE_SCLK_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define SLINK_COMMAND_0_IDLE_SCLK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_IDLE_SCLK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_IDLE_SCLK_DRIVE_LOW                     _MK_ENUM_CONST(0)
+#define SLINK_COMMAND_0_IDLE_SCLK_DRIVE_HIGH                    _MK_ENUM_CONST(1)
+#define SLINK_COMMAND_0_IDLE_SCLK_PULL_LOW                      _MK_ENUM_CONST(2)
+#define SLINK_COMMAND_0_IDLE_SCLK_PULL_HIGH                     _MK_ENUM_CONST(3)
+
+// Reserved = 0
+#define SLINK_COMMAND_0_N_A_0_SHIFT                     _MK_SHIFT_CONST(22)
+#define SLINK_COMMAND_0_N_A_0_FIELD                     (_MK_MASK_CONST(0x3) << SLINK_COMMAND_0_N_A_0_SHIFT)
+#define SLINK_COMMAND_0_N_A_0_RANGE                     23:22
+#define SLINK_COMMAND_0_N_A_0_WOFFSET                   0x0
+#define SLINK_COMMAND_0_N_A_0_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_N_A_0_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define SLINK_COMMAND_0_N_A_0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_N_A_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+//  1 = Second Edge 0 =  First Edge (def)
+#define SLINK_COMMAND_0_CK_SDA_SHIFT                    _MK_SHIFT_CONST(21)
+#define SLINK_COMMAND_0_CK_SDA_FIELD                    (_MK_MASK_CONST(0x1) << SLINK_COMMAND_0_CK_SDA_SHIFT)
+#define SLINK_COMMAND_0_CK_SDA_RANGE                    21:21
+#define SLINK_COMMAND_0_CK_SDA_WOFFSET                  0x0
+#define SLINK_COMMAND_0_CK_SDA_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_CK_SDA_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define SLINK_COMMAND_0_CK_SDA_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_CK_SDA_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_CK_SDA_FIRST_CLK_EDGE                   _MK_ENUM_CONST(0)
+#define SLINK_COMMAND_0_CK_SDA_SECOND_CLK_EDGE                  _MK_ENUM_CONST(1)
+
+// Reserved = 0
+#define SLINK_COMMAND_0_N_A_1_SHIFT                     _MK_SHIFT_CONST(20)
+#define SLINK_COMMAND_0_N_A_1_FIELD                     (_MK_MASK_CONST(0x1) << SLINK_COMMAND_0_N_A_1_SHIFT)
+#define SLINK_COMMAND_0_N_A_1_RANGE                     20:20
+#define SLINK_COMMAND_0_N_A_1_WOFFSET                   0x0
+#define SLINK_COMMAND_0_N_A_1_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_N_A_1_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define SLINK_COMMAND_0_N_A_1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_N_A_1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// 11 = Pull High 10 = Pull Low 01 = Driven High (o.H) 00 = Driven  Low (o.L)
+#define SLINK_COMMAND_0_ACTIVE_SDA_SHIFT                        _MK_SHIFT_CONST(18)
+#define SLINK_COMMAND_0_ACTIVE_SDA_FIELD                        (_MK_MASK_CONST(0x3) << SLINK_COMMAND_0_ACTIVE_SDA_SHIFT)
+#define SLINK_COMMAND_0_ACTIVE_SDA_RANGE                        19:18
+#define SLINK_COMMAND_0_ACTIVE_SDA_WOFFSET                      0x0
+#define SLINK_COMMAND_0_ACTIVE_SDA_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_ACTIVE_SDA_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define SLINK_COMMAND_0_ACTIVE_SDA_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_ACTIVE_SDA_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_ACTIVE_SDA_DRIVE_LOW                    _MK_ENUM_CONST(0)
+#define SLINK_COMMAND_0_ACTIVE_SDA_DRIVE_HIGH                   _MK_ENUM_CONST(1)
+#define SLINK_COMMAND_0_ACTIVE_SDA_PULL_LOW                     _MK_ENUM_CONST(2)
+#define SLINK_COMMAND_0_ACTIVE_SDA_PULL_HIGH                    _MK_ENUM_CONST(3)
+
+// 11 = Pull High 10 = Pull Low 01 = Driven High 00  = Driven Low
+#define SLINK_COMMAND_0_IDLE_SDA_SHIFT                  _MK_SHIFT_CONST(16)
+#define SLINK_COMMAND_0_IDLE_SDA_FIELD                  (_MK_MASK_CONST(0x3) << SLINK_COMMAND_0_IDLE_SDA_SHIFT)
+#define SLINK_COMMAND_0_IDLE_SDA_RANGE                  17:16
+#define SLINK_COMMAND_0_IDLE_SDA_WOFFSET                        0x0
+#define SLINK_COMMAND_0_IDLE_SDA_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_IDLE_SDA_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define SLINK_COMMAND_0_IDLE_SDA_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_IDLE_SDA_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_IDLE_SDA_DRIVE_LOW                      _MK_ENUM_CONST(0)
+#define SLINK_COMMAND_0_IDLE_SDA_DRIVE_HIGH                     _MK_ENUM_CONST(1)
+#define SLINK_COMMAND_0_IDLE_SDA_PULL_LOW                       _MK_ENUM_CONST(2)
+#define SLINK_COMMAND_0_IDLE_SDA_PULL_HIGH                      _MK_ENUM_CONST(3)
+
+// Reserved = 0
+#define SLINK_COMMAND_0_N_A_2_SHIFT                     _MK_SHIFT_CONST(14)
+#define SLINK_COMMAND_0_N_A_2_FIELD                     (_MK_MASK_CONST(0x3) << SLINK_COMMAND_0_N_A_2_SHIFT)
+#define SLINK_COMMAND_0_N_A_2_RANGE                     15:14
+#define SLINK_COMMAND_0_N_A_2_WOFFSET                   0x0
+#define SLINK_COMMAND_0_N_A_2_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_N_A_2_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define SLINK_COMMAND_0_N_A_2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_N_A_2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+//  1 = CS active high  0  = CS active low
+#define SLINK_COMMAND_0_CS_POLARITY_SHIFT                       _MK_SHIFT_CONST(13)
+#define SLINK_COMMAND_0_CS_POLARITY_FIELD                       (_MK_MASK_CONST(0x1) << SLINK_COMMAND_0_CS_POLARITY_SHIFT)
+#define SLINK_COMMAND_0_CS_POLARITY_RANGE                       13:13
+#define SLINK_COMMAND_0_CS_POLARITY_WOFFSET                     0x0
+#define SLINK_COMMAND_0_CS_POLARITY_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_CS_POLARITY_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define SLINK_COMMAND_0_CS_POLARITY_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_CS_POLARITY_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_CS_POLARITY_LOW                 _MK_ENUM_CONST(0)
+#define SLINK_COMMAND_0_CS_POLARITY_HIGH                        _MK_ENUM_CONST(1)
+
+//  1 = CS is high  0  = CS is low  
+#define SLINK_COMMAND_0_CS_VALUE_SHIFT                  _MK_SHIFT_CONST(12)
+#define SLINK_COMMAND_0_CS_VALUE_FIELD                  (_MK_MASK_CONST(0x1) << SLINK_COMMAND_0_CS_VALUE_SHIFT)
+#define SLINK_COMMAND_0_CS_VALUE_RANGE                  12:12
+#define SLINK_COMMAND_0_CS_VALUE_WOFFSET                        0x0
+#define SLINK_COMMAND_0_CS_VALUE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_CS_VALUE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define SLINK_COMMAND_0_CS_VALUE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_CS_VALUE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_CS_VALUE_LOW                    _MK_ENUM_CONST(0)
+#define SLINK_COMMAND_0_CS_VALUE_HIGH                   _MK_ENUM_CONST(1)
+
+//  1 = CS controlled by SW   0  = CS controlled by hardware
+#define SLINK_COMMAND_0_CS_SW_SHIFT                     _MK_SHIFT_CONST(11)
+#define SLINK_COMMAND_0_CS_SW_FIELD                     (_MK_MASK_CONST(0x1) << SLINK_COMMAND_0_CS_SW_SHIFT)
+#define SLINK_COMMAND_0_CS_SW_RANGE                     11:11
+#define SLINK_COMMAND_0_CS_SW_WOFFSET                   0x0
+#define SLINK_COMMAND_0_CS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_CS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define SLINK_COMMAND_0_CS_SW_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_CS_SW_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_CS_SW_HARD                      _MK_ENUM_CONST(0)
+#define SLINK_COMMAND_0_CS_SW_SOFT                      _MK_ENUM_CONST(1)
+
+//  1 = both lines transmit/receive   0  = one line transmit and other receive 
+#define SLINK_COMMAND_0_BOTH_EN_SHIFT                   _MK_SHIFT_CONST(10)
+#define SLINK_COMMAND_0_BOTH_EN_FIELD                   (_MK_MASK_CONST(0x1) << SLINK_COMMAND_0_BOTH_EN_SHIFT)
+#define SLINK_COMMAND_0_BOTH_EN_RANGE                   10:10
+#define SLINK_COMMAND_0_BOTH_EN_WOFFSET                 0x0
+#define SLINK_COMMAND_0_BOTH_EN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_BOTH_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define SLINK_COMMAND_0_BOTH_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_BOTH_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_BOTH_EN_DISABLE                 _MK_ENUM_CONST(0)
+#define SLINK_COMMAND_0_BOTH_EN_ENABLE                  _MK_ENUM_CONST(1)
+
+// 31 = Thirty Two words (Max)
+#define SLINK_COMMAND_0_WORD_SIZE_SHIFT                 _MK_SHIFT_CONST(5)
+#define SLINK_COMMAND_0_WORD_SIZE_FIELD                 (_MK_MASK_CONST(0x1f) << SLINK_COMMAND_0_WORD_SIZE_SHIFT)
+#define SLINK_COMMAND_0_WORD_SIZE_RANGE                 9:5
+#define SLINK_COMMAND_0_WORD_SIZE_WOFFSET                       0x0
+#define SLINK_COMMAND_0_WORD_SIZE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_WORD_SIZE_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define SLINK_COMMAND_0_WORD_SIZE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_WORD_SIZE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// 31 = Thirty Two bit Transfers (Max)
+#define SLINK_COMMAND_0_BIT_LENGTH_SHIFT                        _MK_SHIFT_CONST(0)
+#define SLINK_COMMAND_0_BIT_LENGTH_FIELD                        (_MK_MASK_CONST(0x1f) << SLINK_COMMAND_0_BIT_LENGTH_SHIFT)
+#define SLINK_COMMAND_0_BIT_LENGTH_RANGE                        4:0
+#define SLINK_COMMAND_0_BIT_LENGTH_WOFFSET                      0x0
+#define SLINK_COMMAND_0_BIT_LENGTH_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_BIT_LENGTH_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define SLINK_COMMAND_0_BIT_LENGTH_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_BIT_LENGTH_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register SLINK_COMMAND2_0  
+#define SLINK_COMMAND2_0                        _MK_ADDR_CONST(0x4)
+#define SLINK_COMMAND2_0_WORD_COUNT                     0x1
+#define SLINK_COMMAND2_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
+#define SLINK_COMMAND2_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define SLINK_COMMAND2_0_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
+// Receive enable 
+#define SLINK_COMMAND2_0_RXEN_SHIFT                     _MK_SHIFT_CONST(31)
+#define SLINK_COMMAND2_0_RXEN_FIELD                     (_MK_MASK_CONST(0x1) << SLINK_COMMAND2_0_RXEN_SHIFT)
+#define SLINK_COMMAND2_0_RXEN_RANGE                     31:31
+#define SLINK_COMMAND2_0_RXEN_WOFFSET                   0x0
+#define SLINK_COMMAND2_0_RXEN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_RXEN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define SLINK_COMMAND2_0_RXEN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_RXEN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_RXEN_DISABLE                   _MK_ENUM_CONST(0)
+#define SLINK_COMMAND2_0_RXEN_ENABLE                    _MK_ENUM_CONST(1)
+
+// Transmit enable 
+#define SLINK_COMMAND2_0_TXEN_SHIFT                     _MK_SHIFT_CONST(30)
+#define SLINK_COMMAND2_0_TXEN_FIELD                     (_MK_MASK_CONST(0x1) << SLINK_COMMAND2_0_TXEN_SHIFT)
+#define SLINK_COMMAND2_0_TXEN_RANGE                     30:30
+#define SLINK_COMMAND2_0_TXEN_WOFFSET                   0x0
+#define SLINK_COMMAND2_0_TXEN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_TXEN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define SLINK_COMMAND2_0_TXEN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_TXEN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_TXEN_DISABLE                   _MK_ENUM_CONST(0)
+#define SLINK_COMMAND2_0_TXEN_ENABLE                    _MK_ENUM_CONST(1)
+
+//  1 = bi directional mode 0 = Normal mode
+#define SLINK_COMMAND2_0_SPC0_SHIFT                     _MK_SHIFT_CONST(29)
+#define SLINK_COMMAND2_0_SPC0_FIELD                     (_MK_MASK_CONST(0x1) << SLINK_COMMAND2_0_SPC0_SHIFT)
+#define SLINK_COMMAND2_0_SPC0_RANGE                     29:29
+#define SLINK_COMMAND2_0_SPC0_WOFFSET                   0x0
+#define SLINK_COMMAND2_0_SPC0_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_SPC0_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define SLINK_COMMAND2_0_SPC0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_SPC0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_SPC0_NORMAL                    _MK_ENUM_CONST(0)
+#define SLINK_COMMAND2_0_SPC0_BIDIR                     _MK_ENUM_CONST(1)
+
+// number of cycles between two packs in the DMA. Use of this field is deprecated. Use INT_SIZE 8 = number of cycles between 2 packs (Max) 
+#define SLINK_COMMAND2_0_WAIT_PACK_INT_SHIFT                    _MK_SHIFT_CONST(26)
+#define SLINK_COMMAND2_0_WAIT_PACK_INT_FIELD                    (_MK_MASK_CONST(0x7) << SLINK_COMMAND2_0_WAIT_PACK_INT_SHIFT)
+#define SLINK_COMMAND2_0_WAIT_PACK_INT_RANGE                    28:26
+#define SLINK_COMMAND2_0_WAIT_PACK_INT_WOFFSET                  0x0
+#define SLINK_COMMAND2_0_WAIT_PACK_INT_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_WAIT_PACK_INT_DEFAULT_MASK                     _MK_MASK_CONST(0x7)
+#define SLINK_COMMAND2_0_WAIT_PACK_INT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_WAIT_PACK_INT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Reserved = 0
+#define SLINK_COMMAND2_0_N_A_3_SHIFT                    _MK_SHIFT_CONST(24)
+#define SLINK_COMMAND2_0_N_A_3_FIELD                    (_MK_MASK_CONST(0x3) << SLINK_COMMAND2_0_N_A_3_SHIFT)
+#define SLINK_COMMAND2_0_N_A_3_RANGE                    25:24
+#define SLINK_COMMAND2_0_N_A_3_WOFFSET                  0x0
+#define SLINK_COMMAND2_0_N_A_3_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_N_A_3_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define SLINK_COMMAND2_0_N_A_3_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_N_A_3_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Reserved = 0
+#define SLINK_COMMAND2_0_N_A_4_SHIFT                    _MK_SHIFT_CONST(22)
+#define SLINK_COMMAND2_0_N_A_4_FIELD                    (_MK_MASK_CONST(0x3) << SLINK_COMMAND2_0_N_A_4_SHIFT)
+#define SLINK_COMMAND2_0_N_A_4_RANGE                    23:22
+#define SLINK_COMMAND2_0_N_A_4_WOFFSET                  0x0
+#define SLINK_COMMAND2_0_N_A_4_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_N_A_4_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define SLINK_COMMAND2_0_N_A_4_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_N_A_4_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// number of cycles CS should stay inactive between packets 4 = number of cycles in setup for chip select (Max)   
+#define SLINK_COMMAND2_0_SS_SETUP_SHIFT                 _MK_SHIFT_CONST(20)
+#define SLINK_COMMAND2_0_SS_SETUP_FIELD                 (_MK_MASK_CONST(0x3) << SLINK_COMMAND2_0_SS_SETUP_SHIFT)
+#define SLINK_COMMAND2_0_SS_SETUP_RANGE                 21:20
+#define SLINK_COMMAND2_0_SS_SETUP_WOFFSET                       0x0
+#define SLINK_COMMAND2_0_SS_SETUP_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_SS_SETUP_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define SLINK_COMMAND2_0_SS_SETUP_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_SS_SETUP_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// 11 = chip select3 10 = chip select2 01 = chip select1 00 = chip select0(def)
+#define SLINK_COMMAND2_0_SS_EN_SHIFT                    _MK_SHIFT_CONST(18)
+#define SLINK_COMMAND2_0_SS_EN_FIELD                    (_MK_MASK_CONST(0x3) << SLINK_COMMAND2_0_SS_EN_SHIFT)
+#define SLINK_COMMAND2_0_SS_EN_RANGE                    19:18
+#define SLINK_COMMAND2_0_SS_EN_WOFFSET                  0x0
+#define SLINK_COMMAND2_0_SS_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_SS_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define SLINK_COMMAND2_0_SS_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_SS_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_SS_EN_CS0                      _MK_ENUM_CONST(0)
+#define SLINK_COMMAND2_0_SS_EN_CS1                      _MK_ENUM_CONST(1)
+#define SLINK_COMMAND2_0_SS_EN_CS2                      _MK_ENUM_CONST(2)
+#define SLINK_COMMAND2_0_SS_EN_CS3                      _MK_ENUM_CONST(3)
+
+// Reserved = 0
+#define SLINK_COMMAND2_0_N_A_5_SHIFT                    _MK_SHIFT_CONST(13)
+#define SLINK_COMMAND2_0_N_A_5_FIELD                    (_MK_MASK_CONST(0x1f) << SLINK_COMMAND2_0_N_A_5_SHIFT)
+#define SLINK_COMMAND2_0_N_A_5_RANGE                    17:13
+#define SLINK_COMMAND2_0_N_A_5_WOFFSET                  0x0
+#define SLINK_COMMAND2_0_N_A_5_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_N_A_5_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define SLINK_COMMAND2_0_N_A_5_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_N_A_5_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// number of IDLE cycles between two packets
+// 31 = thirty two cycles between 2 packets
+#define SLINK_COMMAND2_0_INT_SIZE_SHIFT                 _MK_SHIFT_CONST(8)
+#define SLINK_COMMAND2_0_INT_SIZE_FIELD                 (_MK_MASK_CONST(0x1f) << SLINK_COMMAND2_0_INT_SIZE_SHIFT)
+#define SLINK_COMMAND2_0_INT_SIZE_RANGE                 12:8
+#define SLINK_COMMAND2_0_INT_SIZE_WOFFSET                       0x0
+#define SLINK_COMMAND2_0_INT_SIZE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_INT_SIZE_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define SLINK_COMMAND2_0_INT_SIZE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_INT_SIZE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//  1 = Enable Modef   0 = Disable Modef (def)
+#define SLINK_COMMAND2_0_MODFEN_SHIFT                   _MK_SHIFT_CONST(7)
+#define SLINK_COMMAND2_0_MODFEN_FIELD                   (_MK_MASK_CONST(0x1) << SLINK_COMMAND2_0_MODFEN_SHIFT)
+#define SLINK_COMMAND2_0_MODFEN_RANGE                   7:7
+#define SLINK_COMMAND2_0_MODFEN_WOFFSET                 0x0
+#define SLINK_COMMAND2_0_MODFEN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_MODFEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define SLINK_COMMAND2_0_MODFEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_MODFEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_MODFEN_DISABLE                 _MK_ENUM_CONST(0)
+#define SLINK_COMMAND2_0_MODFEN_ENABLE                  _MK_ENUM_CONST(1)
+
+// When set to 1 SLINK uses only one data line (mosi/miso) for Tx and Rx depending on Master/Slave mode.
+// This has effect only when SPC0 is set to 1
+// 1 = Enable Output buffer 0 = Disable Output buffer (def)
+#define SLINK_COMMAND2_0_BIDIROE_SHIFT                  _MK_SHIFT_CONST(6)
+#define SLINK_COMMAND2_0_BIDIROE_FIELD                  (_MK_MASK_CONST(0x1) << SLINK_COMMAND2_0_BIDIROE_SHIFT)
+#define SLINK_COMMAND2_0_BIDIROE_RANGE                  6:6
+#define SLINK_COMMAND2_0_BIDIROE_WOFFSET                        0x0
+#define SLINK_COMMAND2_0_BIDIROE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_BIDIROE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define SLINK_COMMAND2_0_BIDIROE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_BIDIROE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_BIDIROE_DISABLE                        _MK_ENUM_CONST(0)
+#define SLINK_COMMAND2_0_BIDIROE_ENABLE                 _MK_ENUM_CONST(1)
+
+// Reserved
+#define SLINK_COMMAND2_0_N_A_6_SHIFT                    _MK_SHIFT_CONST(5)
+#define SLINK_COMMAND2_0_N_A_6_FIELD                    (_MK_MASK_CONST(0x1) << SLINK_COMMAND2_0_N_A_6_SHIFT)
+#define SLINK_COMMAND2_0_N_A_6_RANGE                    5:5
+#define SLINK_COMMAND2_0_N_A_6_WOFFSET                  0x0
+#define SLINK_COMMAND2_0_N_A_6_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_N_A_6_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define SLINK_COMMAND2_0_N_A_6_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_N_A_6_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// 1 = Enable SPIE interrupt 0 = Disable SPIE interrupt
+#define SLINK_COMMAND2_0_SPIE_SHIFT                     _MK_SHIFT_CONST(4)
+#define SLINK_COMMAND2_0_SPIE_FIELD                     (_MK_MASK_CONST(0x1) << SLINK_COMMAND2_0_SPIE_SHIFT)
+#define SLINK_COMMAND2_0_SPIE_RANGE                     4:4
+#define SLINK_COMMAND2_0_SPIE_WOFFSET                   0x0
+#define SLINK_COMMAND2_0_SPIE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_SPIE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define SLINK_COMMAND2_0_SPIE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_SPIE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_SPIE_DISABLE                   _MK_ENUM_CONST(0)
+#define SLINK_COMMAND2_0_SPIE_ENABLE                    _MK_ENUM_CONST(1)
+
+// Reserved
+#define SLINK_COMMAND2_0_N_A_8_SHIFT                    _MK_SHIFT_CONST(3)
+#define SLINK_COMMAND2_0_N_A_8_FIELD                    (_MK_MASK_CONST(0x1) << SLINK_COMMAND2_0_N_A_8_SHIFT)
+#define SLINK_COMMAND2_0_N_A_8_RANGE                    3:3
+#define SLINK_COMMAND2_0_N_A_8_WOFFSET                  0x0
+#define SLINK_COMMAND2_0_N_A_8_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_N_A_8_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define SLINK_COMMAND2_0_N_A_8_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_N_A_8_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Reserved
+#define SLINK_COMMAND2_0_N_A_9_SHIFT                    _MK_SHIFT_CONST(2)
+#define SLINK_COMMAND2_0_N_A_9_FIELD                    (_MK_MASK_CONST(0x1) << SLINK_COMMAND2_0_N_A_9_SHIFT)
+#define SLINK_COMMAND2_0_N_A_9_RANGE                    2:2
+#define SLINK_COMMAND2_0_N_A_9_WOFFSET                  0x0
+#define SLINK_COMMAND2_0_N_A_9_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_N_A_9_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define SLINK_COMMAND2_0_N_A_9_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_N_A_9_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// 1 = Enable 0 = Disable (def)
+#define SLINK_COMMAND2_0_SSOE_SHIFT                     _MK_SHIFT_CONST(1)
+#define SLINK_COMMAND2_0_SSOE_FIELD                     (_MK_MASK_CONST(0x1) << SLINK_COMMAND2_0_SSOE_SHIFT)
+#define SLINK_COMMAND2_0_SSOE_RANGE                     1:1
+#define SLINK_COMMAND2_0_SSOE_WOFFSET                   0x0
+#define SLINK_COMMAND2_0_SSOE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_SSOE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define SLINK_COMMAND2_0_SSOE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_SSOE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_SSOE_DISABLE                   _MK_ENUM_CONST(0)
+#define SLINK_COMMAND2_0_SSOE_ENABLE                    _MK_ENUM_CONST(1)
+
+//  1 = Transmit LSB first 0 = Transmit LSB last
+#define SLINK_COMMAND2_0_LSBFE_SHIFT                    _MK_SHIFT_CONST(0)
+#define SLINK_COMMAND2_0_LSBFE_FIELD                    (_MK_MASK_CONST(0x1) << SLINK_COMMAND2_0_LSBFE_SHIFT)
+#define SLINK_COMMAND2_0_LSBFE_RANGE                    0:0
+#define SLINK_COMMAND2_0_LSBFE_WOFFSET                  0x0
+#define SLINK_COMMAND2_0_LSBFE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_LSBFE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define SLINK_COMMAND2_0_LSBFE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_LSBFE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_LSBFE_LAST                     _MK_ENUM_CONST(0)
+#define SLINK_COMMAND2_0_LSBFE_FIRST                    _MK_ENUM_CONST(1)
+
+
+// Register SLINK_STATUS_0  
+#define SLINK_STATUS_0                  _MK_ADDR_CONST(0x8)
+#define SLINK_STATUS_0_WORD_COUNT                       0x1
+#define SLINK_STATUS_0_RESET_VAL                        _MK_MASK_CONST(0xa00000)
+#define SLINK_STATUS_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
+#define SLINK_STATUS_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define SLINK_STATUS_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+//  1 = Controller is Busy 0 =  Controller is Free
+#define SLINK_STATUS_0_BSY_SHIFT                        _MK_SHIFT_CONST(31)
+#define SLINK_STATUS_0_BSY_FIELD                        (_MK_MASK_CONST(0x1) << SLINK_STATUS_0_BSY_SHIFT)
+#define SLINK_STATUS_0_BSY_RANGE                        31:31
+#define SLINK_STATUS_0_BSY_WOFFSET                      0x0
+#define SLINK_STATUS_0_BSY_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_BSY_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define SLINK_STATUS_0_BSY_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_BSY_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_BSY_IDLE                 _MK_ENUM_CONST(0)
+#define SLINK_STATUS_0_BSY_BUSY                 _MK_ENUM_CONST(1)
+
+// 1= contoller is Ready for transfer 0 = controller is Busy. Write 1 to clear the flag
+#define SLINK_STATUS_0_RDY_SHIFT                        _MK_SHIFT_CONST(30)
+#define SLINK_STATUS_0_RDY_FIELD                        (_MK_MASK_CONST(0x1) << SLINK_STATUS_0_RDY_SHIFT)
+#define SLINK_STATUS_0_RDY_RANGE                        30:30
+#define SLINK_STATUS_0_RDY_WOFFSET                      0x0
+#define SLINK_STATUS_0_RDY_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_RDY_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define SLINK_STATUS_0_RDY_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_RDY_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_RDY_NOT_READY                    _MK_ENUM_CONST(0)
+#define SLINK_STATUS_0_RDY_READY                        _MK_ENUM_CONST(1)
+
+// Will be set to 1 by HW when Errors such as Underflow/overflow occurs.Write 1 to clear the flag
+#define SLINK_STATUS_0_ERR_SHIFT                        _MK_SHIFT_CONST(29)
+#define SLINK_STATUS_0_ERR_FIELD                        (_MK_MASK_CONST(0x1) << SLINK_STATUS_0_ERR_SHIFT)
+#define SLINK_STATUS_0_ERR_RANGE                        29:29
+#define SLINK_STATUS_0_ERR_WOFFSET                      0x0
+#define SLINK_STATUS_0_ERR_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_ERR_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define SLINK_STATUS_0_ERR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_ERR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_ERR_OK                   _MK_ENUM_CONST(0)
+#define SLINK_STATUS_0_ERR_ERROR                        _MK_ENUM_CONST(1)
+
+// SCLK input signal State
+#define SLINK_STATUS_0_SCLK_SHIFT                       _MK_SHIFT_CONST(28)
+#define SLINK_STATUS_0_SCLK_FIELD                       (_MK_MASK_CONST(0x1) << SLINK_STATUS_0_SCLK_SHIFT)
+#define SLINK_STATUS_0_SCLK_RANGE                       28:28
+#define SLINK_STATUS_0_SCLK_WOFFSET                     0x0
+#define SLINK_STATUS_0_SCLK_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_SCLK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define SLINK_STATUS_0_SCLK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_SCLK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_SCLK_LOW                 _MK_ENUM_CONST(0)
+#define SLINK_STATUS_0_SCLK_HIGH                        _MK_ENUM_CONST(1)
+
+// Flush the RX FIFO
+#define SLINK_STATUS_0_RX_FLUSH_SHIFT                   _MK_SHIFT_CONST(27)
+#define SLINK_STATUS_0_RX_FLUSH_FIELD                   (_MK_MASK_CONST(0x1) << SLINK_STATUS_0_RX_FLUSH_SHIFT)
+#define SLINK_STATUS_0_RX_FLUSH_RANGE                   27:27
+#define SLINK_STATUS_0_RX_FLUSH_WOFFSET                 0x0
+#define SLINK_STATUS_0_RX_FLUSH_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_RX_FLUSH_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define SLINK_STATUS_0_RX_FLUSH_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_RX_FLUSH_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_RX_FLUSH_NOP                     _MK_ENUM_CONST(0)
+#define SLINK_STATUS_0_RX_FLUSH_FLUSH                   _MK_ENUM_CONST(1)
+
+// Flush the TX FIFO
+#define SLINK_STATUS_0_TX_FLUSH_SHIFT                   _MK_SHIFT_CONST(26)
+#define SLINK_STATUS_0_TX_FLUSH_FIELD                   (_MK_MASK_CONST(0x1) << SLINK_STATUS_0_TX_FLUSH_SHIFT)
+#define SLINK_STATUS_0_TX_FLUSH_RANGE                   26:26
+#define SLINK_STATUS_0_TX_FLUSH_WOFFSET                 0x0
+#define SLINK_STATUS_0_TX_FLUSH_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_TX_FLUSH_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define SLINK_STATUS_0_TX_FLUSH_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_TX_FLUSH_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_TX_FLUSH_NOP                     _MK_ENUM_CONST(0)
+#define SLINK_STATUS_0_TX_FLUSH_FLUSH                   _MK_ENUM_CONST(1)
+
+// RX FIFO Overflow
+#define SLINK_STATUS_0_RX_OVF_SHIFT                     _MK_SHIFT_CONST(25)
+#define SLINK_STATUS_0_RX_OVF_FIELD                     (_MK_MASK_CONST(0x1) << SLINK_STATUS_0_RX_OVF_SHIFT)
+#define SLINK_STATUS_0_RX_OVF_RANGE                     25:25
+#define SLINK_STATUS_0_RX_OVF_WOFFSET                   0x0
+#define SLINK_STATUS_0_RX_OVF_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_RX_OVF_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define SLINK_STATUS_0_RX_OVF_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_RX_OVF_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_RX_OVF_OK                        _MK_ENUM_CONST(0)
+#define SLINK_STATUS_0_RX_OVF_ERROR                     _MK_ENUM_CONST(1)
+
+// TX FIFO Underflow
+#define SLINK_STATUS_0_TX_UNF_SHIFT                     _MK_SHIFT_CONST(24)
+#define SLINK_STATUS_0_TX_UNF_FIELD                     (_MK_MASK_CONST(0x1) << SLINK_STATUS_0_TX_UNF_SHIFT)
+#define SLINK_STATUS_0_TX_UNF_RANGE                     24:24
+#define SLINK_STATUS_0_TX_UNF_WOFFSET                   0x0
+#define SLINK_STATUS_0_TX_UNF_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_TX_UNF_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define SLINK_STATUS_0_TX_UNF_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_TX_UNF_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_TX_UNF_OK                        _MK_ENUM_CONST(0)
+#define SLINK_STATUS_0_TX_UNF_ERROR                     _MK_ENUM_CONST(1)
+
+// RX FIFO Empty
+#define SLINK_STATUS_0_RX_EMPTY_SHIFT                   _MK_SHIFT_CONST(23)
+#define SLINK_STATUS_0_RX_EMPTY_FIELD                   (_MK_MASK_CONST(0x1) << SLINK_STATUS_0_RX_EMPTY_SHIFT)
+#define SLINK_STATUS_0_RX_EMPTY_RANGE                   23:23
+#define SLINK_STATUS_0_RX_EMPTY_WOFFSET                 0x0
+#define SLINK_STATUS_0_RX_EMPTY_DEFAULT                 _MK_MASK_CONST(0x1)
+#define SLINK_STATUS_0_RX_EMPTY_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define SLINK_STATUS_0_RX_EMPTY_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_RX_EMPTY_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_RX_EMPTY_NOT_EMPTY                       _MK_ENUM_CONST(0)
+#define SLINK_STATUS_0_RX_EMPTY_EMPTY                   _MK_ENUM_CONST(1)
+
+// RX FIFO Full
+#define SLINK_STATUS_0_RX_FULL_SHIFT                    _MK_SHIFT_CONST(22)
+#define SLINK_STATUS_0_RX_FULL_FIELD                    (_MK_MASK_CONST(0x1) << SLINK_STATUS_0_RX_FULL_SHIFT)
+#define SLINK_STATUS_0_RX_FULL_RANGE                    22:22
+#define SLINK_STATUS_0_RX_FULL_WOFFSET                  0x0
+#define SLINK_STATUS_0_RX_FULL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_RX_FULL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define SLINK_STATUS_0_RX_FULL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_RX_FULL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_RX_FULL_NOT_FULL                 _MK_ENUM_CONST(0)
+#define SLINK_STATUS_0_RX_FULL_FULL                     _MK_ENUM_CONST(1)
+
+// TX FIFO Empty
+#define SLINK_STATUS_0_TX_EMPTY_SHIFT                   _MK_SHIFT_CONST(21)
+#define SLINK_STATUS_0_TX_EMPTY_FIELD                   (_MK_MASK_CONST(0x1) << SLINK_STATUS_0_TX_EMPTY_SHIFT)
+#define SLINK_STATUS_0_TX_EMPTY_RANGE                   21:21
+#define SLINK_STATUS_0_TX_EMPTY_WOFFSET                 0x0
+#define SLINK_STATUS_0_TX_EMPTY_DEFAULT                 _MK_MASK_CONST(0x1)
+#define SLINK_STATUS_0_TX_EMPTY_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define SLINK_STATUS_0_TX_EMPTY_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_TX_EMPTY_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_TX_EMPTY_NOT_EMPTY                       _MK_ENUM_CONST(0)
+#define SLINK_STATUS_0_TX_EMPTY_EMPTY                   _MK_ENUM_CONST(1)
+
+// TX FIFO Full
+#define SLINK_STATUS_0_TX_FULL_SHIFT                    _MK_SHIFT_CONST(20)
+#define SLINK_STATUS_0_TX_FULL_FIELD                    (_MK_MASK_CONST(0x1) << SLINK_STATUS_0_TX_FULL_SHIFT)
+#define SLINK_STATUS_0_TX_FULL_RANGE                    20:20
+#define SLINK_STATUS_0_TX_FULL_WOFFSET                  0x0
+#define SLINK_STATUS_0_TX_FULL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_TX_FULL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define SLINK_STATUS_0_TX_FULL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_TX_FULL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_TX_FULL_NOT_FULL                 _MK_ENUM_CONST(0)
+#define SLINK_STATUS_0_TX_FULL_FULL                     _MK_ENUM_CONST(1)
+
+// TX FIFO Overflow
+#define SLINK_STATUS_0_TX_OVF_SHIFT                     _MK_SHIFT_CONST(19)
+#define SLINK_STATUS_0_TX_OVF_FIELD                     (_MK_MASK_CONST(0x1) << SLINK_STATUS_0_TX_OVF_SHIFT)
+#define SLINK_STATUS_0_TX_OVF_RANGE                     19:19
+#define SLINK_STATUS_0_TX_OVF_WOFFSET                   0x0
+#define SLINK_STATUS_0_TX_OVF_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_TX_OVF_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define SLINK_STATUS_0_TX_OVF_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_TX_OVF_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_TX_OVF_OK                        _MK_ENUM_CONST(0)
+#define SLINK_STATUS_0_TX_OVF_ERROR                     _MK_ENUM_CONST(1)
+
+// RX FIFO Underflow
+#define SLINK_STATUS_0_RX_UNF_SHIFT                     _MK_SHIFT_CONST(18)
+#define SLINK_STATUS_0_RX_UNF_FIELD                     (_MK_MASK_CONST(0x1) << SLINK_STATUS_0_RX_UNF_SHIFT)
+#define SLINK_STATUS_0_RX_UNF_RANGE                     18:18
+#define SLINK_STATUS_0_RX_UNF_WOFFSET                   0x0
+#define SLINK_STATUS_0_RX_UNF_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_RX_UNF_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define SLINK_STATUS_0_RX_UNF_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_RX_UNF_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_RX_UNF_OK                        _MK_ENUM_CONST(0)
+#define SLINK_STATUS_0_RX_UNF_ERROR                     _MK_ENUM_CONST(1)
+
+// Reserved
+#define SLINK_STATUS_0_N_A_10_SHIFT                     _MK_SHIFT_CONST(17)
+#define SLINK_STATUS_0_N_A_10_FIELD                     (_MK_MASK_CONST(0x1) << SLINK_STATUS_0_N_A_10_SHIFT)
+#define SLINK_STATUS_0_N_A_10_RANGE                     17:17
+#define SLINK_STATUS_0_N_A_10_WOFFSET                   0x0
+#define SLINK_STATUS_0_N_A_10_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_N_A_10_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define SLINK_STATUS_0_N_A_10_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_N_A_10_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Mode fault
+#define SLINK_STATUS_0_MODF_SHIFT                       _MK_SHIFT_CONST(16)
+#define SLINK_STATUS_0_MODF_FIELD                       (_MK_MASK_CONST(0x1) << SLINK_STATUS_0_MODF_SHIFT)
+#define SLINK_STATUS_0_MODF_RANGE                       16:16
+#define SLINK_STATUS_0_MODF_WOFFSET                     0x0
+#define SLINK_STATUS_0_MODF_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_MODF_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define SLINK_STATUS_0_MODF_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_MODF_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_MODF_OK                  _MK_ENUM_CONST(0)
+#define SLINK_STATUS_0_MODF_ERROR                       _MK_ENUM_CONST(1)
+
+// number of blocks transferred (BLOCK count) during dma
+#define SLINK_STATUS_0_BLK_CNT_SHIFT                    _MK_SHIFT_CONST(0)
+#define SLINK_STATUS_0_BLK_CNT_FIELD                    (_MK_MASK_CONST(0xffff) << SLINK_STATUS_0_BLK_CNT_SHIFT)
+#define SLINK_STATUS_0_BLK_CNT_RANGE                    15:0
+#define SLINK_STATUS_0_BLK_CNT_WOFFSET                  0x0
+#define SLINK_STATUS_0_BLK_CNT_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_BLK_CNT_DEFAULT_MASK                     _MK_MASK_CONST(0xffff)
+#define SLINK_STATUS_0_BLK_CNT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_BLK_CNT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Reserved
+#define SLINK_STATUS_0_N_A_100_SHIFT                    _MK_SHIFT_CONST(10)
+#define SLINK_STATUS_0_N_A_100_FIELD                    (_MK_MASK_CONST(0x3f) << SLINK_STATUS_0_N_A_100_SHIFT)
+#define SLINK_STATUS_0_N_A_100_RANGE                    15:10
+#define SLINK_STATUS_0_N_A_100_WOFFSET                  0x0
+#define SLINK_STATUS_0_N_A_100_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_N_A_100_DEFAULT_MASK                     _MK_MASK_CONST(0x3f)
+#define SLINK_STATUS_0_N_A_100_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_N_A_100_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// In GO mode indicates number of words transferred (word count) 
+#define SLINK_STATUS_0_WORD_SHIFT                       _MK_SHIFT_CONST(5)
+#define SLINK_STATUS_0_WORD_FIELD                       (_MK_MASK_CONST(0x1f) << SLINK_STATUS_0_WORD_SHIFT)
+#define SLINK_STATUS_0_WORD_RANGE                       9:5
+#define SLINK_STATUS_0_WORD_WOFFSET                     0x0
+#define SLINK_STATUS_0_WORD_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_WORD_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define SLINK_STATUS_0_WORD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_WORD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// In Go mode indicates mumber of bits trasnferred (bit count)
+#define SLINK_STATUS_0_COUNT_SHIFT                      _MK_SHIFT_CONST(0)
+#define SLINK_STATUS_0_COUNT_FIELD                      (_MK_MASK_CONST(0x1f) << SLINK_STATUS_0_COUNT_SHIFT)
+#define SLINK_STATUS_0_COUNT_RANGE                      4:0
+#define SLINK_STATUS_0_COUNT_WOFFSET                    0x0
+#define SLINK_STATUS_0_COUNT_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_COUNT_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define SLINK_STATUS_0_COUNT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_COUNT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Reserved address 12 [0xc] 
+
+// Register SLINK_MAS_DATA_0  
+#define SLINK_MAS_DATA_0                        _MK_ADDR_CONST(0x10)
+#define SLINK_MAS_DATA_0_WORD_COUNT                     0x1
+#define SLINK_MAS_DATA_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define SLINK_MAS_DATA_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
+#define SLINK_MAS_DATA_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define SLINK_MAS_DATA_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define SLINK_MAS_DATA_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define SLINK_MAS_DATA_0_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
+// Tx/Rx Shift Pattern
+#define SLINK_MAS_DATA_0_MASTER_BUFFER_SHIFT                    _MK_SHIFT_CONST(0)
+#define SLINK_MAS_DATA_0_MASTER_BUFFER_FIELD                    (_MK_MASK_CONST(0xffffffff) << SLINK_MAS_DATA_0_MASTER_BUFFER_SHIFT)
+#define SLINK_MAS_DATA_0_MASTER_BUFFER_RANGE                    31:0
+#define SLINK_MAS_DATA_0_MASTER_BUFFER_WOFFSET                  0x0
+#define SLINK_MAS_DATA_0_MASTER_BUFFER_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SLINK_MAS_DATA_0_MASTER_BUFFER_DEFAULT_MASK                     _MK_MASK_CONST(0xffffffff)
+#define SLINK_MAS_DATA_0_MASTER_BUFFER_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SLINK_MAS_DATA_0_MASTER_BUFFER_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register SLINK_SLAVE_DATA_0  
+#define SLINK_SLAVE_DATA_0                      _MK_ADDR_CONST(0x14)
+#define SLINK_SLAVE_DATA_0_WORD_COUNT                   0x1
+#define SLINK_SLAVE_DATA_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define SLINK_SLAVE_DATA_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define SLINK_SLAVE_DATA_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define SLINK_SLAVE_DATA_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define SLINK_SLAVE_DATA_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
+#define SLINK_SLAVE_DATA_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
+// Tx/Rx Shift Pattern
+#define SLINK_SLAVE_DATA_0_SLAVE_BUFFER_SHIFT                   _MK_SHIFT_CONST(0)
+#define SLINK_SLAVE_DATA_0_SLAVE_BUFFER_FIELD                   (_MK_MASK_CONST(0xffffffff) << SLINK_SLAVE_DATA_0_SLAVE_BUFFER_SHIFT)
+#define SLINK_SLAVE_DATA_0_SLAVE_BUFFER_RANGE                   31:0
+#define SLINK_SLAVE_DATA_0_SLAVE_BUFFER_WOFFSET                 0x0
+#define SLINK_SLAVE_DATA_0_SLAVE_BUFFER_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SLINK_SLAVE_DATA_0_SLAVE_BUFFER_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
+#define SLINK_SLAVE_DATA_0_SLAVE_BUFFER_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SLINK_SLAVE_DATA_0_SLAVE_BUFFER_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register SLINK_DMA_CTL_0  
+#define SLINK_DMA_CTL_0                 _MK_ADDR_CONST(0x18)
+#define SLINK_DMA_CTL_0_WORD_COUNT                      0x1
+#define SLINK_DMA_CTL_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define SLINK_DMA_CTL_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define SLINK_DMA_CTL_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define SLINK_DMA_CTL_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define SLINK_DMA_CTL_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define SLINK_DMA_CTL_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+//  1 = DMA mode is enabled, 0 = DMA disabled
+#define SLINK_DMA_CTL_0_DMA_EN_SHIFT                    _MK_SHIFT_CONST(31)
+#define SLINK_DMA_CTL_0_DMA_EN_FIELD                    (_MK_MASK_CONST(0x1) << SLINK_DMA_CTL_0_DMA_EN_SHIFT)
+#define SLINK_DMA_CTL_0_DMA_EN_RANGE                    31:31
+#define SLINK_DMA_CTL_0_DMA_EN_WOFFSET                  0x0
+#define SLINK_DMA_CTL_0_DMA_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SLINK_DMA_CTL_0_DMA_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define SLINK_DMA_CTL_0_DMA_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SLINK_DMA_CTL_0_DMA_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define SLINK_DMA_CTL_0_DMA_EN_DISABLE                  _MK_ENUM_CONST(0)
+#define SLINK_DMA_CTL_0_DMA_EN_ENABLE                   _MK_ENUM_CONST(1)
+
+// Reserved
+#define SLINK_DMA_CTL_0_N_A_11_SHIFT                    _MK_SHIFT_CONST(28)
+#define SLINK_DMA_CTL_0_N_A_11_FIELD                    (_MK_MASK_CONST(0x7) << SLINK_DMA_CTL_0_N_A_11_SHIFT)
+#define SLINK_DMA_CTL_0_N_A_11_RANGE                    30:28
+#define SLINK_DMA_CTL_0_N_A_11_WOFFSET                  0x0
+#define SLINK_DMA_CTL_0_N_A_11_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SLINK_DMA_CTL_0_N_A_11_DEFAULT_MASK                     _MK_MASK_CONST(0x7)
+#define SLINK_DMA_CTL_0_N_A_11_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SLINK_DMA_CTL_0_N_A_11_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Interrupt enable on receive completion.
+// 1 = Enable interrupt generation at the end of a receive transfer.
+// 0 = Disable interrupt generation for receive.
+#define SLINK_DMA_CTL_0_IE_RXC_SHIFT                    _MK_SHIFT_CONST(27)
+#define SLINK_DMA_CTL_0_IE_RXC_FIELD                    (_MK_MASK_CONST(0x1) << SLINK_DMA_CTL_0_IE_RXC_SHIFT)
+#define SLINK_DMA_CTL_0_IE_RXC_RANGE                    27:27
+#define SLINK_DMA_CTL_0_IE_RXC_WOFFSET                  0x0
+#define SLINK_DMA_CTL_0_IE_RXC_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SLINK_DMA_CTL_0_IE_RXC_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define SLINK_DMA_CTL_0_IE_RXC_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SLINK_DMA_CTL_0_IE_RXC_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define SLINK_DMA_CTL_0_IE_RXC_DISABLE                  _MK_ENUM_CONST(0)
+#define SLINK_DMA_CTL_0_IE_RXC_ENABLE                   _MK_ENUM_CONST(1)
+
+// Interrupt enable on transmit completion.
+// 1 = Enable interrupt generation at the end of a transmit transfer.
+// 0 = Disable interrupt generation for transmit.
+#define SLINK_DMA_CTL_0_IE_TXC_SHIFT                    _MK_SHIFT_CONST(26)
+#define SLINK_DMA_CTL_0_IE_TXC_FIELD                    (_MK_MASK_CONST(0x1) << SLINK_DMA_CTL_0_IE_TXC_SHIFT)
+#define SLINK_DMA_CTL_0_IE_TXC_RANGE                    26:26
+#define SLINK_DMA_CTL_0_IE_TXC_WOFFSET                  0x0
+#define SLINK_DMA_CTL_0_IE_TXC_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SLINK_DMA_CTL_0_IE_TXC_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define SLINK_DMA_CTL_0_IE_TXC_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SLINK_DMA_CTL_0_IE_TXC_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define SLINK_DMA_CTL_0_IE_TXC_DISABLE                  _MK_ENUM_CONST(0)
+#define SLINK_DMA_CTL_0_IE_TXC_ENABLE                   _MK_ENUM_CONST(1)
+
+// Reserved
+#define SLINK_DMA_CTL_0_N_A_12_SHIFT                    _MK_SHIFT_CONST(23)
+#define SLINK_DMA_CTL_0_N_A_12_FIELD                    (_MK_MASK_CONST(0x7) << SLINK_DMA_CTL_0_N_A_12_SHIFT)
+#define SLINK_DMA_CTL_0_N_A_12_RANGE                    25:23
+#define SLINK_DMA_CTL_0_N_A_12_WOFFSET                  0x0
+#define SLINK_DMA_CTL_0_N_A_12_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SLINK_DMA_CTL_0_N_A_12_DEFAULT_MASK                     _MK_MASK_CONST(0x7)
+#define SLINK_DMA_CTL_0_N_A_12_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SLINK_DMA_CTL_0_N_A_12_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Specifies the packet size during the DMA mode
+//             00      = 4 bits in a pack
+//           01      = 8bits in a pack
+//            10      = 16 in a pack
+//               10      = 32 in a pack
+#define SLINK_DMA_CTL_0_PACK_SIZE_SHIFT                 _MK_SHIFT_CONST(21)
+#define SLINK_DMA_CTL_0_PACK_SIZE_FIELD                 (_MK_MASK_CONST(0x3) << SLINK_DMA_CTL_0_PACK_SIZE_SHIFT)
+#define SLINK_DMA_CTL_0_PACK_SIZE_RANGE                 22:21
+#define SLINK_DMA_CTL_0_PACK_SIZE_WOFFSET                       0x0
+#define SLINK_DMA_CTL_0_PACK_SIZE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SLINK_DMA_CTL_0_PACK_SIZE_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define SLINK_DMA_CTL_0_PACK_SIZE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SLINK_DMA_CTL_0_PACK_SIZE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define SLINK_DMA_CTL_0_PACK_SIZE_PACK4                 _MK_ENUM_CONST(0)
+#define SLINK_DMA_CTL_0_PACK_SIZE_PACK8                 _MK_ENUM_CONST(1)
+#define SLINK_DMA_CTL_0_PACK_SIZE_PACK16                        _MK_ENUM_CONST(2)
+#define SLINK_DMA_CTL_0_PACK_SIZE_PACK32                        _MK_ENUM_CONST(3)
+
+// Packed mode enable bit.
+//  1 = Packed mode is enabled. This is only valid if BIT_LENGTH in SBCX_COMMAND register is set to 3, 7, 15 or 31
+// When enabled, all 32-bits of data in the FIFO contains valid
+// data packets of either 8-bit or 16-bit length.
+// 0 = Packed mode is disabled.
+#define SLINK_DMA_CTL_0_PACKED_SHIFT                    _MK_SHIFT_CONST(20)
+#define SLINK_DMA_CTL_0_PACKED_FIELD                    (_MK_MASK_CONST(0x1) << SLINK_DMA_CTL_0_PACKED_SHIFT)
+#define SLINK_DMA_CTL_0_PACKED_RANGE                    20:20
+#define SLINK_DMA_CTL_0_PACKED_WOFFSET                  0x0
+#define SLINK_DMA_CTL_0_PACKED_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SLINK_DMA_CTL_0_PACKED_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define SLINK_DMA_CTL_0_PACKED_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SLINK_DMA_CTL_0_PACKED_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define SLINK_DMA_CTL_0_PACKED_DISABLE                  _MK_ENUM_CONST(0)
+#define SLINK_DMA_CTL_0_PACKED_ENABLE                   _MK_ENUM_CONST(1)
+
+// Receive FIFO trigger level.
+// 00: 1 word. DMA trigger is asserted whenever there is at least 1 word in the RX FIFO.
+// 01: 4 word. DMA trigger is asserted when there are at least 4 words in the RX FIFO.
+// 10: 8 word. DMA trigger is asserted when there are at least 8 words in the RX FIFO.
+// 11: 16 word. DMA trigger is asserted when there are at least 16 words in the RX FIFO.
+#define SLINK_DMA_CTL_0_RX_TRIG_SHIFT                   _MK_SHIFT_CONST(18)
+#define SLINK_DMA_CTL_0_RX_TRIG_FIELD                   (_MK_MASK_CONST(0x3) << SLINK_DMA_CTL_0_RX_TRIG_SHIFT)
+#define SLINK_DMA_CTL_0_RX_TRIG_RANGE                   19:18
+#define SLINK_DMA_CTL_0_RX_TRIG_WOFFSET                 0x0
+#define SLINK_DMA_CTL_0_RX_TRIG_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SLINK_DMA_CTL_0_RX_TRIG_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define SLINK_DMA_CTL_0_RX_TRIG_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SLINK_DMA_CTL_0_RX_TRIG_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define SLINK_DMA_CTL_0_RX_TRIG_TRIG1                   _MK_ENUM_CONST(0)
+#define SLINK_DMA_CTL_0_RX_TRIG_TRIG4                   _MK_ENUM_CONST(1)
+#define SLINK_DMA_CTL_0_RX_TRIG_TRIG8                   _MK_ENUM_CONST(2)
+#define SLINK_DMA_CTL_0_RX_TRIG_TRIG16                  _MK_ENUM_CONST(3)
+
+// Transmit FIFO trigger level.
+// 00: 1 word. DMA trigger is asserted whenever there is at least 1 word in the TX FIFO.
+// 01: 4 word. DMA trigger is asserted when there are at least 4 words in the TX FIFO.
+// 10: 8 word. DMA trigger is asserted when there are at least 8 words in the TX FIFO.
+// 11: 16 word. DMA trigger is asserted when there are at least 16 words in the TX FIFO.
+#define SLINK_DMA_CTL_0_TX_TRIG_SHIFT                   _MK_SHIFT_CONST(16)
+#define SLINK_DMA_CTL_0_TX_TRIG_FIELD                   (_MK_MASK_CONST(0x3) << SLINK_DMA_CTL_0_TX_TRIG_SHIFT)
+#define SLINK_DMA_CTL_0_TX_TRIG_RANGE                   17:16
+#define SLINK_DMA_CTL_0_TX_TRIG_WOFFSET                 0x0
+#define SLINK_DMA_CTL_0_TX_TRIG_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SLINK_DMA_CTL_0_TX_TRIG_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define SLINK_DMA_CTL_0_TX_TRIG_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SLINK_DMA_CTL_0_TX_TRIG_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define SLINK_DMA_CTL_0_TX_TRIG_TRIG1                   _MK_ENUM_CONST(0)
+#define SLINK_DMA_CTL_0_TX_TRIG_TRIG4                   _MK_ENUM_CONST(1)
+#define SLINK_DMA_CTL_0_TX_TRIG_TRIG8                   _MK_ENUM_CONST(2)
+#define SLINK_DMA_CTL_0_TX_TRIG_TRIG16                  _MK_ENUM_CONST(3)
+
+// N = N+1 packets
+// number of packets should be aligned in the packed mode trasnfers.
+// packed mode     --> Number of packets
+//    3                                        multiple of 8
+//    7                                   multiple of 4
+//    15                          multiple of 2
+//    31                          from 0 to N
+#define SLINK_DMA_CTL_0_DMA_BLOCK_SIZE_SHIFT                    _MK_SHIFT_CONST(0)
+#define SLINK_DMA_CTL_0_DMA_BLOCK_SIZE_FIELD                    (_MK_MASK_CONST(0xffff) << SLINK_DMA_CTL_0_DMA_BLOCK_SIZE_SHIFT)
+#define SLINK_DMA_CTL_0_DMA_BLOCK_SIZE_RANGE                    15:0
+#define SLINK_DMA_CTL_0_DMA_BLOCK_SIZE_WOFFSET                  0x0
+#define SLINK_DMA_CTL_0_DMA_BLOCK_SIZE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SLINK_DMA_CTL_0_DMA_BLOCK_SIZE_DEFAULT_MASK                     _MK_MASK_CONST(0xffff)
+#define SLINK_DMA_CTL_0_DMA_BLOCK_SIZE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SLINK_DMA_CTL_0_DMA_BLOCK_SIZE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Reserved address 28 [0x1c] 
+
+// Reserved address 32 [0x20] 
+
+// Reserved address 36 [0x24] 
+
+// Reserved address 40 [0x28] 
+
+// Reserved address 44 [0x2c] 
+
+// Reserved address 48 [0x30] 
+
+// Reserved address 52 [0x34] 
+
+// Reserved address 56 [0x38] 
+
+// Reserved address 60 [0x3c] 
+
+// Reserved address 64 [0x40] 
+
+// Reserved address 68 [0x44] 
+
+// Reserved address 72 [0x48] 
+
+// Reserved address 76 [0x4c] 
+
+// Reserved address 80 [0x50] 
+
+// Reserved address 84 [0x54] 
+
+// Reserved address 88 [0x58] 
+
+// Reserved address 92 [0x5c] 
+
+// Reserved address 96 [0x60] 
+
+// Reserved address 100 [0x64] 
+
+// Reserved address 104 [0x68] 
+
+// Reserved address 108 [0x6c] 
+
+// Reserved address 112 [0x70] 
+
+// Reserved address 116 [0x74] 
+
+// Reserved address 120 [0x78] 
+
+// Reserved address 124 [0x7c] 
+
+// Reserved address 128 [0x80] 
+
+// Reserved address 132 [0x84] 
+
+// Reserved address 136 [0x88] 
+
+// Reserved address 140 [0x8c] 
+
+// Reserved address 144 [0x90] 
+
+// Reserved address 148 [0x94] 
+
+// Reserved address 152 [0x98] 
+
+// Reserved address 156 [0x9c] 
+
+// Reserved address 160 [0xa0] 
+
+// Reserved address 164 [0xa4] 
+
+// Reserved address 168 [0xa8] 
+
+// Reserved address 172 [0xac] 
+
+// Reserved address 176 [0xb0] 
+
+// Reserved address 180 [0xb4] 
+
+// Reserved address 184 [0xb8] 
+
+// Reserved address 188 [0xbc] 
+
+// Reserved address 192 [0xc0] 
+
+// Reserved address 196 [0xc4] 
+
+// Reserved address 200 [0xc8] 
+
+// Reserved address 204 [0xcc] 
+
+// Reserved address 208 [0xd0] 
+
+// Reserved address 212 [0xd4] 
+
+// Reserved address 216 [0xd8] 
+
+// Reserved address 220 [0xdc] 
+
+// Reserved address 224 [0xe0] 
+
+// Reserved address 228 [0xe4] 
+
+// Reserved address 232 [0xe8] 
+
+// Reserved address 236 [0xec] 
+
+// Reserved address 240 [0xf0] 
+
+// Reserved address 244 [0xf4] 
+
+// Reserved address 248 [0xf8] 
+
+// Reserved address 252 [0xfc] 
+
+// Register SLINK_TX_FIFO_0  
+#define SLINK_TX_FIFO_0                 _MK_ADDR_CONST(0x100)
+#define SLINK_TX_FIFO_0_WORD_COUNT                      0x1
+#define SLINK_TX_FIFO_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define SLINK_TX_FIFO_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define SLINK_TX_FIFO_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define SLINK_TX_FIFO_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define SLINK_TX_FIFO_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define SLINK_TX_FIFO_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Tx/Rx Shift Pattern
+#define SLINK_TX_FIFO_0_TX_FIFO_REGISTER_SHIFT                  _MK_SHIFT_CONST(0)
+#define SLINK_TX_FIFO_0_TX_FIFO_REGISTER_FIELD                  (_MK_MASK_CONST(0xffffffff) << SLINK_TX_FIFO_0_TX_FIFO_REGISTER_SHIFT)
+#define SLINK_TX_FIFO_0_TX_FIFO_REGISTER_RANGE                  31:0
+#define SLINK_TX_FIFO_0_TX_FIFO_REGISTER_WOFFSET                        0x0
+#define SLINK_TX_FIFO_0_TX_FIFO_REGISTER_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SLINK_TX_FIFO_0_TX_FIFO_REGISTER_DEFAULT_MASK                   _MK_MASK_CONST(0xffffffff)
+#define SLINK_TX_FIFO_0_TX_FIFO_REGISTER_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SLINK_TX_FIFO_0_TX_FIFO_REGISTER_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Reserved address 260 [0x104] 
+
+// Reserved address 264 [0x108] 
+
+// Reserved address 268 [0x10c] 
+
+// Reserved address 272 [0x110] 
+
+// Reserved address 276 [0x114] 
+
+// Reserved address 280 [0x118] 
+
+// Reserved address 284 [0x11c] 
+
+// Reserved address 288 [0x120] 
+
+// Reserved address 292 [0x124] 
+
+// Reserved address 296 [0x128] 
+
+// Reserved address 300 [0x12c] 
+
+// Reserved address 304 [0x130] 
+
+// Reserved address 308 [0x134] 
+
+// Reserved address 312 [0x138] 
+
+// Reserved address 316 [0x13c] 
+
+// Reserved address 320 [0x140] 
+
+// Reserved address 324 [0x144] 
+
+// Reserved address 328 [0x148] 
+
+// Reserved address 332 [0x14c] 
+
+// Reserved address 336 [0x150] 
+
+// Reserved address 340 [0x154] 
+
+// Reserved address 344 [0x158] 
+
+// Reserved address 348 [0x15c] 
+
+// Reserved address 352 [0x160] 
+
+// Reserved address 356 [0x164] 
+
+// Reserved address 360 [0x168] 
+
+// Reserved address 364 [0x16c] 
+
+// Reserved address 368 [0x170] 
+
+// Reserved address 372 [0x174] 
+
+// Reserved address 376 [0x178] 
+
+// Reserved address 380 [0x17c] 
+
+// Register SLINK_RX_FIFO_0  
+#define SLINK_RX_FIFO_0                 _MK_ADDR_CONST(0x180)
+#define SLINK_RX_FIFO_0_WORD_COUNT                      0x1
+#define SLINK_RX_FIFO_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define SLINK_RX_FIFO_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define SLINK_RX_FIFO_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define SLINK_RX_FIFO_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define SLINK_RX_FIFO_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define SLINK_RX_FIFO_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Tx/Rx Shift Pattern
+#define SLINK_RX_FIFO_0_RX_FIFO_REGISTER_SHIFT                  _MK_SHIFT_CONST(0)
+#define SLINK_RX_FIFO_0_RX_FIFO_REGISTER_FIELD                  (_MK_MASK_CONST(0xffffffff) << SLINK_RX_FIFO_0_RX_FIFO_REGISTER_SHIFT)
+#define SLINK_RX_FIFO_0_RX_FIFO_REGISTER_RANGE                  31:0
+#define SLINK_RX_FIFO_0_RX_FIFO_REGISTER_WOFFSET                        0x0
+#define SLINK_RX_FIFO_0_RX_FIFO_REGISTER_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SLINK_RX_FIFO_0_RX_FIFO_REGISTER_DEFAULT_MASK                   _MK_MASK_CONST(0xffffffff)
+#define SLINK_RX_FIFO_0_RX_FIFO_REGISTER_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SLINK_RX_FIFO_0_RX_FIFO_REGISTER_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+//
+// REGISTER LIST
+//
+#define LIST_ARSLINK_REGS(_op_) \
+_op_(SLINK_COMMAND_0) \
+_op_(SLINK_COMMAND2_0) \
+_op_(SLINK_STATUS_0) \
+_op_(SLINK_MAS_DATA_0) \
+_op_(SLINK_SLAVE_DATA_0) \
+_op_(SLINK_DMA_CTL_0) \
+_op_(SLINK_TX_FIFO_0) \
+_op_(SLINK_RX_FIFO_0)
+
+
+//
+// ADDRESS SPACES
+//
+
+#define BASE_ADDRESS_SLINK      0x00000000
+
+//
+// ARSLINK REGISTER BANKS
+//
+
+#define SLINK0_FIRST_REG 0x0000 // SLINK_COMMAND_0
+#define SLINK0_LAST_REG 0x0008 // SLINK_STATUS_0
+#define SLINK1_FIRST_REG 0x0010 // SLINK_MAS_DATA_0
+#define SLINK1_LAST_REG 0x0018 // SLINK_DMA_CTL_0
+#define SLINK2_FIRST_REG 0x0100 // SLINK_TX_FIFO_0
+#define SLINK2_LAST_REG 0x0100 // SLINK_TX_FIFO_0
+#define SLINK3_FIRST_REG 0x0180 // SLINK_RX_FIFO_0
+#define SLINK3_LAST_REG 0x0180 // SLINK_RX_FIFO_0
+
+#ifndef _MK_SHIFT_CONST
+  #define _MK_SHIFT_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_MASK_CONST
+  #define _MK_MASK_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_ENUM_CONST
+  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
+#endif
+#ifndef _MK_ADDR_CONST
+  #define _MK_ADDR_CONST(_constant_) _constant_
+#endif
+
+#endif // ifndef ___ARSLINK_H_INC_
diff --git a/arch/arm/mach-tegra/include/ap15/arspi.h b/arch/arm/mach-tegra/include/ap15/arspi.h
new file mode 100644
index 000000000000..45ef3d2699e0
--- /dev/null
+++ b/arch/arm/mach-tegra/include/ap15/arspi.h
@@ -0,0 +1,703 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+//
+// DO NOT EDIT - generated by simspec!
+//
+
+#ifndef ___ARSPI_H_INC_
+#define ___ARSPI_H_INC_
+
+// Register SPI_COMMAND_0  
+#define SPI_COMMAND_0                   _MK_ADDR_CONST(0x0)
+#define SPI_COMMAND_0_WORD_COUNT                        0x1
+#define SPI_COMMAND_0_RESET_VAL                         _MK_MASK_CONST(0x10000420)
+#define SPI_COMMAND_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
+#define SPI_COMMAND_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define SPI_COMMAND_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
+// Reserved = 0
+#define SPI_COMMAND_0_N_A_1_SHIFT                       _MK_SHIFT_CONST(31)
+#define SPI_COMMAND_0_N_A_1_FIELD                       (_MK_MASK_CONST(0x1) << SPI_COMMAND_0_N_A_1_SHIFT)
+#define SPI_COMMAND_0_N_A_1_RANGE                       31:31
+#define SPI_COMMAND_0_N_A_1_WOFFSET                     0x0
+#define SPI_COMMAND_0_N_A_1_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_N_A_1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define SPI_COMMAND_0_N_A_1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_N_A_1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Default: 0 Go Mode enable bit. Software sets this bit to 1 to enable transmit or receive of packets without specifying the no. of packets.  In receive mode, the controller receives one packet whenever software sets this bit.  In transmit mode, controller transmits all data present in the TX FIFO until TX FIFO becomes empty. If packed mode is enabled, then all packets in the last word from the TX FIFO are transmitted before finishing the transfer.  Software must set up all fields in SPI_COMMAND and SPI_DMA_CTL registers before setting this bit to 1.  This bit clears to 0 by the hardware on the completion of the transfer.  
+#define SPI_COMMAND_0_GO_SHIFT                  _MK_SHIFT_CONST(30)
+#define SPI_COMMAND_0_GO_FIELD                  (_MK_MASK_CONST(0x1) << SPI_COMMAND_0_GO_SHIFT)
+#define SPI_COMMAND_0_GO_RANGE                  30:30
+#define SPI_COMMAND_0_GO_WOFFSET                        0x0
+#define SPI_COMMAND_0_GO_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_GO_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define SPI_COMMAND_0_GO_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_GO_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_GO_DISABLE                        _MK_ENUM_CONST(0)
+#define SPI_COMMAND_0_GO_ENABLE                 _MK_ENUM_CONST(1)
+
+// Reserved = 0
+#define SPI_COMMAND_0_N_A_2_SHIFT                       _MK_SHIFT_CONST(29)
+#define SPI_COMMAND_0_N_A_2_FIELD                       (_MK_MASK_CONST(0x1) << SPI_COMMAND_0_N_A_2_SHIFT)
+#define SPI_COMMAND_0_N_A_2_RANGE                       29:29
+#define SPI_COMMAND_0_N_A_2_WOFFSET                     0x0
+#define SPI_COMMAND_0_N_A_2_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_N_A_2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define SPI_COMMAND_0_N_A_2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_N_A_2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Default: 1.  Master/slave mode select. RO 1 = Controller is operating in master mode.  0 = Controller is operating in slave mode. This bit is read-only and fixed to 1. Only master mode is supported in this design.  
+#define SPI_COMMAND_0_M_S_SHIFT                 _MK_SHIFT_CONST(28)
+#define SPI_COMMAND_0_M_S_FIELD                 (_MK_MASK_CONST(0x1) << SPI_COMMAND_0_M_S_SHIFT)
+#define SPI_COMMAND_0_M_S_RANGE                 28:28
+#define SPI_COMMAND_0_M_S_WOFFSET                       0x0
+#define SPI_COMMAND_0_M_S_DEFAULT                       _MK_MASK_CONST(0x1)
+#define SPI_COMMAND_0_M_S_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define SPI_COMMAND_0_M_S_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_M_S_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_M_S_SLAVE                 _MK_ENUM_CONST(0)
+#define SPI_COMMAND_0_M_S_MASTER                        _MK_ENUM_CONST(1)
+
+// Active clock signal format. Controls the output enable of the SCK line when the controller is actively doing data transfers.  00: Drive low.  01: Drive high.  10: Pull low.  11: Pull high.  Default: 00
+#define SPI_COMMAND_0_ACTIVE_SCLK_SHIFT                 _MK_SHIFT_CONST(26)
+#define SPI_COMMAND_0_ACTIVE_SCLK_FIELD                 (_MK_MASK_CONST(0x3) << SPI_COMMAND_0_ACTIVE_SCLK_SHIFT)
+#define SPI_COMMAND_0_ACTIVE_SCLK_RANGE                 27:26
+#define SPI_COMMAND_0_ACTIVE_SCLK_WOFFSET                       0x0
+#define SPI_COMMAND_0_ACTIVE_SCLK_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_ACTIVE_SCLK_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define SPI_COMMAND_0_ACTIVE_SCLK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_ACTIVE_SCLK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_ACTIVE_SCLK_DRIVE_LOW                     _MK_ENUM_CONST(0)
+#define SPI_COMMAND_0_ACTIVE_SCLK_DRIVE_HIGH                    _MK_ENUM_CONST(1)
+#define SPI_COMMAND_0_ACTIVE_SCLK_PULL_LOW                      _MK_ENUM_CONST(2)
+#define SPI_COMMAND_0_ACTIVE_SCLK_PULL_HIGH                     _MK_ENUM_CONST(3)
+
+// Reserved = 0
+#define SPI_COMMAND_0_N_A_3_SHIFT                       _MK_SHIFT_CONST(22)
+#define SPI_COMMAND_0_N_A_3_FIELD                       (_MK_MASK_CONST(0xf) << SPI_COMMAND_0_N_A_3_SHIFT)
+#define SPI_COMMAND_0_N_A_3_RANGE                       25:22
+#define SPI_COMMAND_0_N_A_3_WOFFSET                     0x0
+#define SPI_COMMAND_0_N_A_3_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_N_A_3_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define SPI_COMMAND_0_N_A_3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_N_A_3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Clock phase. Controls how the data is transferred with respect to clock edge.  0 = Data is transferred on first clock edge after CS is driven low.  1 = Data is transferred on second clock edge after CS is driven low.
+#define SPI_COMMAND_0_CK_SDA_SHIFT                      _MK_SHIFT_CONST(21)
+#define SPI_COMMAND_0_CK_SDA_FIELD                      (_MK_MASK_CONST(0x1) << SPI_COMMAND_0_CK_SDA_SHIFT)
+#define SPI_COMMAND_0_CK_SDA_RANGE                      21:21
+#define SPI_COMMAND_0_CK_SDA_WOFFSET                    0x0
+#define SPI_COMMAND_0_CK_SDA_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_CK_SDA_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define SPI_COMMAND_0_CK_SDA_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_CK_SDA_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_CK_SDA_FIRST_CLK_EDGE                     _MK_ENUM_CONST(0)
+#define SPI_COMMAND_0_CK_SDA_SECOND_CLK_EDGE                    _MK_ENUM_CONST(1)
+
+// Reserved = 0
+#define SPI_COMMAND_0_N_A_4_SHIFT                       _MK_SHIFT_CONST(20)
+#define SPI_COMMAND_0_N_A_4_FIELD                       (_MK_MASK_CONST(0x1) << SPI_COMMAND_0_N_A_4_SHIFT)
+#define SPI_COMMAND_0_N_A_4_RANGE                       20:20
+#define SPI_COMMAND_0_N_A_4_WOFFSET                     0x0
+#define SPI_COMMAND_0_N_A_4_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_N_A_4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define SPI_COMMAND_0_N_A_4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_N_A_4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Active Data signal format. Controls the output enable of the SCK line when the controller is actively doing data transfers.  00: Drive low.  01: Drive high.  10: Pull low.  11: Pull high.  Default: 00.
+#define SPI_COMMAND_0_ACTIVE_SDA_SHIFT                  _MK_SHIFT_CONST(18)
+#define SPI_COMMAND_0_ACTIVE_SDA_FIELD                  (_MK_MASK_CONST(0x3) << SPI_COMMAND_0_ACTIVE_SDA_SHIFT)
+#define SPI_COMMAND_0_ACTIVE_SDA_RANGE                  19:18
+#define SPI_COMMAND_0_ACTIVE_SDA_WOFFSET                        0x0
+#define SPI_COMMAND_0_ACTIVE_SDA_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_ACTIVE_SDA_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define SPI_COMMAND_0_ACTIVE_SDA_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_ACTIVE_SDA_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_ACTIVE_SDA_DRIVE_LOW                      _MK_ENUM_CONST(0)
+#define SPI_COMMAND_0_ACTIVE_SDA_DRIVE_HIGH                     _MK_ENUM_CONST(1)
+#define SPI_COMMAND_0_ACTIVE_SDA_PULL_LOW                       _MK_ENUM_CONST(2)
+#define SPI_COMMAND_0_ACTIVE_SDA_PULL_HIGH                      _MK_ENUM_CONST(3)
+
+// Reserved
+#define SPI_COMMAND_0_N_A_5_SHIFT                       _MK_SHIFT_CONST(17)
+#define SPI_COMMAND_0_N_A_5_FIELD                       (_MK_MASK_CONST(0x1) << SPI_COMMAND_0_N_A_5_SHIFT)
+#define SPI_COMMAND_0_N_A_5_RANGE                       17:17
+#define SPI_COMMAND_0_N_A_5_WOFFSET                     0x0
+#define SPI_COMMAND_0_N_A_5_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_N_A_5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define SPI_COMMAND_0_N_A_5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_N_A_5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// CS signal Polarity.  For both SW and HW CS modes, this bit works as the polarity of the CS signal Default:0 
+#define SPI_COMMAND_0_CS_POL_SHIFT                      _MK_SHIFT_CONST(16)
+#define SPI_COMMAND_0_CS_POL_FIELD                      (_MK_MASK_CONST(0x1) << SPI_COMMAND_0_CS_POL_SHIFT)
+#define SPI_COMMAND_0_CS_POL_RANGE                      16:16
+#define SPI_COMMAND_0_CS_POL_WOFFSET                    0x0
+#define SPI_COMMAND_0_CS_POL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_CS_POL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define SPI_COMMAND_0_CS_POL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_CS_POL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_CS_POL_ACTIVE_LOW                 _MK_ENUM_CONST(0)
+#define SPI_COMMAND_0_CS_POL_ACTIVE_HIGH                        _MK_ENUM_CONST(1)
+
+// Transmit enable.  1 = Transmit is enabled. Data is transmitted out from the TX FIFO to SDA output.  0 = Transmit is disabled.  Default: 0 
+#define SPI_COMMAND_0_TXEN_SHIFT                        _MK_SHIFT_CONST(15)
+#define SPI_COMMAND_0_TXEN_FIELD                        (_MK_MASK_CONST(0x1) << SPI_COMMAND_0_TXEN_SHIFT)
+#define SPI_COMMAND_0_TXEN_RANGE                        15:15
+#define SPI_COMMAND_0_TXEN_WOFFSET                      0x0
+#define SPI_COMMAND_0_TXEN_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_TXEN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define SPI_COMMAND_0_TXEN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_TXEN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_TXEN_DISABLE                      _MK_ENUM_CONST(0)
+#define SPI_COMMAND_0_TXEN_ENABLE                       _MK_ENUM_CONST(1)
+
+// Receive enable.  1 = Receive is enabled. Data is received on SDI line and placed in the RX FIFO.  0 = Receive is disabled.  Default: 0 
+#define SPI_COMMAND_0_RXEN_SHIFT                        _MK_SHIFT_CONST(14)
+#define SPI_COMMAND_0_RXEN_FIELD                        (_MK_MASK_CONST(0x1) << SPI_COMMAND_0_RXEN_SHIFT)
+#define SPI_COMMAND_0_RXEN_RANGE                        14:14
+#define SPI_COMMAND_0_RXEN_WOFFSET                      0x0
+#define SPI_COMMAND_0_RXEN_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_RXEN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define SPI_COMMAND_0_RXEN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_RXEN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_RXEN_DISABLE                      _MK_ENUM_CONST(0)
+#define SPI_COMMAND_0_RXEN_ENABLE                       _MK_ENUM_CONST(1)
+
+// CS signal value/polarity.  If CS_SOFT is 1, then the value in CS_VAL is driven out on SPI_CS. If  CS_SOFT is 0, then this bit works as the polarity of the CS signal and is driven to active state during packet transfers and inactive state in between packet transfers. 
+#define SPI_COMMAND_0_CS_VAL_SHIFT                      _MK_SHIFT_CONST(13)
+#define SPI_COMMAND_0_CS_VAL_FIELD                      (_MK_MASK_CONST(0x1) << SPI_COMMAND_0_CS_VAL_SHIFT)
+#define SPI_COMMAND_0_CS_VAL_RANGE                      13:13
+#define SPI_COMMAND_0_CS_VAL_WOFFSET                    0x0
+#define SPI_COMMAND_0_CS_VAL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_CS_VAL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define SPI_COMMAND_0_CS_VAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_CS_VAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_CS_VAL_LOW                        _MK_ENUM_CONST(0)
+#define SPI_COMMAND_0_CS_VAL_HIGH                       _MK_ENUM_CONST(1)
+
+// Software control of SPI_CS signal 1 = SPI_CS is driven with the value in the CS bit.  0 = SPI_CS is driven to active during packet transfers by the hardware.  Default: 0
+#define SPI_COMMAND_0_CS_SOFT_SHIFT                     _MK_SHIFT_CONST(12)
+#define SPI_COMMAND_0_CS_SOFT_FIELD                     (_MK_MASK_CONST(0x1) << SPI_COMMAND_0_CS_SOFT_SHIFT)
+#define SPI_COMMAND_0_CS_SOFT_RANGE                     12:12
+#define SPI_COMMAND_0_CS_SOFT_WOFFSET                   0x0
+#define SPI_COMMAND_0_CS_SOFT_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_CS_SOFT_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define SPI_COMMAND_0_CS_SOFT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_CS_SOFT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_CS_SOFT_HW_CTL                    _MK_ENUM_CONST(0)
+#define SPI_COMMAND_0_CS_SOFT_SW_CTL                    _MK_ENUM_CONST(1)
+
+// Programmable delay between two packets if CS is used in hardware mode (CS_SOFT = 0).  Default: 2.
+#define SPI_COMMAND_0_CS_DELAY_SHIFT                    _MK_SHIFT_CONST(9)
+#define SPI_COMMAND_0_CS_DELAY_FIELD                    (_MK_MASK_CONST(0x7) << SPI_COMMAND_0_CS_DELAY_SHIFT)
+#define SPI_COMMAND_0_CS_DELAY_RANGE                    11:9
+#define SPI_COMMAND_0_CS_DELAY_WOFFSET                  0x0
+#define SPI_COMMAND_0_CS_DELAY_DEFAULT                  _MK_MASK_CONST(0x2)
+#define SPI_COMMAND_0_CS_DELAY_DEFAULT_MASK                     _MK_MASK_CONST(0x7)
+#define SPI_COMMAND_0_CS_DELAY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_CS_DELAY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Enable for Chip select 3: 1 = cs3 is enabled.  0 = cs3 is disabled. (Default)
+#define SPI_COMMAND_0_CS3_EN_SHIFT                      _MK_SHIFT_CONST(8)
+#define SPI_COMMAND_0_CS3_EN_FIELD                      (_MK_MASK_CONST(0x1) << SPI_COMMAND_0_CS3_EN_SHIFT)
+#define SPI_COMMAND_0_CS3_EN_RANGE                      8:8
+#define SPI_COMMAND_0_CS3_EN_WOFFSET                    0x0
+#define SPI_COMMAND_0_CS3_EN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_CS3_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define SPI_COMMAND_0_CS3_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_CS3_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_CS3_EN_DISABLE                    _MK_ENUM_CONST(0)
+#define SPI_COMMAND_0_CS3_EN_ENABLE                     _MK_ENUM_CONST(1)
+
+// Enable for Chip select 2: 1 = cs2 is enabled.  0 = cs2 is disabled. (Default)
+#define SPI_COMMAND_0_CS2_EN_SHIFT                      _MK_SHIFT_CONST(7)
+#define SPI_COMMAND_0_CS2_EN_FIELD                      (_MK_MASK_CONST(0x1) << SPI_COMMAND_0_CS2_EN_SHIFT)
+#define SPI_COMMAND_0_CS2_EN_RANGE                      7:7
+#define SPI_COMMAND_0_CS2_EN_WOFFSET                    0x0
+#define SPI_COMMAND_0_CS2_EN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_CS2_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define SPI_COMMAND_0_CS2_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_CS2_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_CS2_EN_DISABLE                    _MK_ENUM_CONST(0)
+#define SPI_COMMAND_0_CS2_EN_ENABLE                     _MK_ENUM_CONST(1)
+
+// Enable for Chip select 1: 1 = cs1 is enabled.  0 = cs1 is disabled. (Default)
+#define SPI_COMMAND_0_CS1_EN_SHIFT                      _MK_SHIFT_CONST(6)
+#define SPI_COMMAND_0_CS1_EN_FIELD                      (_MK_MASK_CONST(0x1) << SPI_COMMAND_0_CS1_EN_SHIFT)
+#define SPI_COMMAND_0_CS1_EN_RANGE                      6:6
+#define SPI_COMMAND_0_CS1_EN_WOFFSET                    0x0
+#define SPI_COMMAND_0_CS1_EN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_CS1_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define SPI_COMMAND_0_CS1_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_CS1_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_CS1_EN_DISABLE                    _MK_ENUM_CONST(0)
+#define SPI_COMMAND_0_CS1_EN_ENABLE                     _MK_ENUM_CONST(1)
+
+// Enable for Chip select 0: 1 = cs0 is enabled(Default).  0 = cs0 is disabled
+#define SPI_COMMAND_0_CS0_EN_SHIFT                      _MK_SHIFT_CONST(5)
+#define SPI_COMMAND_0_CS0_EN_FIELD                      (_MK_MASK_CONST(0x1) << SPI_COMMAND_0_CS0_EN_SHIFT)
+#define SPI_COMMAND_0_CS0_EN_RANGE                      5:5
+#define SPI_COMMAND_0_CS0_EN_WOFFSET                    0x0
+#define SPI_COMMAND_0_CS0_EN_DEFAULT                    _MK_MASK_CONST(0x1)
+#define SPI_COMMAND_0_CS0_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define SPI_COMMAND_0_CS0_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_CS0_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_CS0_EN_DISABLE                    _MK_ENUM_CONST(0)
+#define SPI_COMMAND_0_CS0_EN_ENABLE                     _MK_ENUM_CONST(1)
+
+// Bit stream length.  0 = Single bit transfer.  1 = 2 bit transfer N = N + 1 bit transfer.  31 = 32 bit transfer (max) Default: 0 
+#define SPI_COMMAND_0_BIT_LENGTH_SHIFT                  _MK_SHIFT_CONST(0)
+#define SPI_COMMAND_0_BIT_LENGTH_FIELD                  (_MK_MASK_CONST(0x1f) << SPI_COMMAND_0_BIT_LENGTH_SHIFT)
+#define SPI_COMMAND_0_BIT_LENGTH_RANGE                  4:0
+#define SPI_COMMAND_0_BIT_LENGTH_WOFFSET                        0x0
+#define SPI_COMMAND_0_BIT_LENGTH_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_BIT_LENGTH_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define SPI_COMMAND_0_BIT_LENGTH_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_BIT_LENGTH_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register SPI_STATUS_0  
+#define SPI_STATUS_0                    _MK_ADDR_CONST(0x4)
+#define SPI_STATUS_0_WORD_COUNT                         0x1
+#define SPI_STATUS_0_RESET_VAL                  _MK_MASK_CONST(0x2800000)
+#define SPI_STATUS_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
+#define SPI_STATUS_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define SPI_STATUS_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define SPI_STATUS_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define SPI_STATUS_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+// Busy bit. Indicates that the controller is currently doing a data transfer.  This bit is set at the start of every transfer and will be cleared at the end of every transfer.  Default: 0 
+#define SPI_STATUS_0_BSY_SHIFT                  _MK_SHIFT_CONST(31)
+#define SPI_STATUS_0_BSY_FIELD                  (_MK_MASK_CONST(0x1) << SPI_STATUS_0_BSY_SHIFT)
+#define SPI_STATUS_0_BSY_RANGE                  31:31
+#define SPI_STATUS_0_BSY_WOFFSET                        0x0
+#define SPI_STATUS_0_BSY_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SPI_STATUS_0_BSY_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define SPI_STATUS_0_BSY_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SPI_STATUS_0_BSY_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define SPI_STATUS_0_BSY_NOT_BUSY                       _MK_ENUM_CONST(0)
+#define SPI_STATUS_0_BSY_BUSY                   _MK_ENUM_CONST(1)
+
+// Ready bit. This bit is set at the end of every transfer and an interrupt is also generated if the corresponding interrupt enable is set. Software writes a 1 to clear it. The interrupt is also cleared when this bit is cleared.  Default: 0 
+#define SPI_STATUS_0_RDY_SHIFT                  _MK_SHIFT_CONST(30)
+#define SPI_STATUS_0_RDY_FIELD                  (_MK_MASK_CONST(0x1) << SPI_STATUS_0_RDY_SHIFT)
+#define SPI_STATUS_0_RDY_RANGE                  30:30
+#define SPI_STATUS_0_RDY_WOFFSET                        0x0
+#define SPI_STATUS_0_RDY_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SPI_STATUS_0_RDY_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define SPI_STATUS_0_RDY_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SPI_STATUS_0_RDY_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define SPI_STATUS_0_RDY_NOT_READY                      _MK_ENUM_CONST(0)
+#define SPI_STATUS_0_RDY_READY                  _MK_ENUM_CONST(1)
+
+// RX FIFO Flush: WO. Software writes 1 to this bit to flush the RX FIFO. This bit will read 1 when the flush operation is in progress and will return to 0 when it is finished.  Default: 0 
+#define SPI_STATUS_0_RXF_FLUSH_SHIFT                    _MK_SHIFT_CONST(29)
+#define SPI_STATUS_0_RXF_FLUSH_FIELD                    (_MK_MASK_CONST(0x1) << SPI_STATUS_0_RXF_FLUSH_SHIFT)
+#define SPI_STATUS_0_RXF_FLUSH_RANGE                    29:29
+#define SPI_STATUS_0_RXF_FLUSH_WOFFSET                  0x0
+#define SPI_STATUS_0_RXF_FLUSH_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SPI_STATUS_0_RXF_FLUSH_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define SPI_STATUS_0_RXF_FLUSH_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SPI_STATUS_0_RXF_FLUSH_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define SPI_STATUS_0_RXF_FLUSH_DISABLE                  _MK_ENUM_CONST(0)
+#define SPI_STATUS_0_RXF_FLUSH_ENABLE                   _MK_ENUM_CONST(1)
+
+// TX FIFO Flush: WO. Software writes 1 to this bit to flush the TX FIFO. This bit will read 1 when the flush operation is in progress and will return to 0 when it is finished.  Default: 0 
+#define SPI_STATUS_0_TXF_FLUSH_SHIFT                    _MK_SHIFT_CONST(28)
+#define SPI_STATUS_0_TXF_FLUSH_FIELD                    (_MK_MASK_CONST(0x1) << SPI_STATUS_0_TXF_FLUSH_SHIFT)
+#define SPI_STATUS_0_TXF_FLUSH_RANGE                    28:28
+#define SPI_STATUS_0_TXF_FLUSH_WOFFSET                  0x0
+#define SPI_STATUS_0_TXF_FLUSH_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SPI_STATUS_0_TXF_FLUSH_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define SPI_STATUS_0_TXF_FLUSH_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SPI_STATUS_0_TXF_FLUSH_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define SPI_STATUS_0_TXF_FLUSH_DISABLE                  _MK_ENUM_CONST(0)
+#define SPI_STATUS_0_TXF_FLUSH_ENABLE                   _MK_ENUM_CONST(1)
+
+// RX FIFO Under run: RO.  This bit is set to 1 whenever software tries to read from an empty RX FIFO. An interrupt is generated if the interrupt enable is set for receive operation (IE.RXC in SPI_DMA_CTL register). Software writes a 1 to clear this bit. Clearing this bit also clears the interrupt.  Default: 0 
+#define SPI_STATUS_0_RXF_UNR_SHIFT                      _MK_SHIFT_CONST(27)
+#define SPI_STATUS_0_RXF_UNR_FIELD                      (_MK_MASK_CONST(0x1) << SPI_STATUS_0_RXF_UNR_SHIFT)
+#define SPI_STATUS_0_RXF_UNR_RANGE                      27:27
+#define SPI_STATUS_0_RXF_UNR_WOFFSET                    0x0
+#define SPI_STATUS_0_RXF_UNR_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SPI_STATUS_0_RXF_UNR_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define SPI_STATUS_0_RXF_UNR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SPI_STATUS_0_RXF_UNR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define SPI_STATUS_0_RXF_UNR_UNSET                      _MK_ENUM_CONST(0)
+#define SPI_STATUS_0_RXF_UNR_SET                        _MK_ENUM_CONST(1)
+
+// TX FIFO Overflow: RO.  This bit is set to 1 whenever software tries to write to a full TX FIFO. An interrupt is generated if the interrupt enable is set for transmit operation (IE.TXC in SPI_DMA_CTL register). Software writes a 1 to clear this bit. Clearing this bit also clears the interrupt.  Default: 0 
+#define SPI_STATUS_0_TXF_OVF_SHIFT                      _MK_SHIFT_CONST(26)
+#define SPI_STATUS_0_TXF_OVF_FIELD                      (_MK_MASK_CONST(0x1) << SPI_STATUS_0_TXF_OVF_SHIFT)
+#define SPI_STATUS_0_TXF_OVF_RANGE                      26:26
+#define SPI_STATUS_0_TXF_OVF_WOFFSET                    0x0
+#define SPI_STATUS_0_TXF_OVF_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SPI_STATUS_0_TXF_OVF_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define SPI_STATUS_0_TXF_OVF_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SPI_STATUS_0_TXF_OVF_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define SPI_STATUS_0_TXF_OVF_UNSET                      _MK_ENUM_CONST(0)
+#define SPI_STATUS_0_TXF_OVF_SET                        _MK_ENUM_CONST(1)
+
+// RX FIFO empty status: RO.  Hardware sets this bit to 1 if RX FIFO is empty. Otherwise, this bit is set to 0.  Default: 1. FIFO is empty at POR.  
+#define SPI_STATUS_0_RXF_EMPTY_SHIFT                    _MK_SHIFT_CONST(25)
+#define SPI_STATUS_0_RXF_EMPTY_FIELD                    (_MK_MASK_CONST(0x1) << SPI_STATUS_0_RXF_EMPTY_SHIFT)
+#define SPI_STATUS_0_RXF_EMPTY_RANGE                    25:25
+#define SPI_STATUS_0_RXF_EMPTY_WOFFSET                  0x0
+#define SPI_STATUS_0_RXF_EMPTY_DEFAULT                  _MK_MASK_CONST(0x1)
+#define SPI_STATUS_0_RXF_EMPTY_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define SPI_STATUS_0_RXF_EMPTY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SPI_STATUS_0_RXF_EMPTY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define SPI_STATUS_0_RXF_EMPTY_NOT_EMPTY                        _MK_ENUM_CONST(0)
+#define SPI_STATUS_0_RXF_EMPTY_EMPTY                    _MK_ENUM_CONST(1)
+
+// RX FIFO full status: RO.  Hardware sets this bit to 1 if RX FIFO is full. Otherwise, this bit is set to 0.  Default: 0. FIFO is empty at POR.  
+#define SPI_STATUS_0_RXF_FULL_SHIFT                     _MK_SHIFT_CONST(24)
+#define SPI_STATUS_0_RXF_FULL_FIELD                     (_MK_MASK_CONST(0x1) << SPI_STATUS_0_RXF_FULL_SHIFT)
+#define SPI_STATUS_0_RXF_FULL_RANGE                     24:24
+#define SPI_STATUS_0_RXF_FULL_WOFFSET                   0x0
+#define SPI_STATUS_0_RXF_FULL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SPI_STATUS_0_RXF_FULL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define SPI_STATUS_0_RXF_FULL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SPI_STATUS_0_RXF_FULL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define SPI_STATUS_0_RXF_FULL_NOT_FULL                  _MK_ENUM_CONST(0)
+#define SPI_STATUS_0_RXF_FULL_FULL                      _MK_ENUM_CONST(1)
+
+// TX FIFO empty status: RO.  Hardware sets this bit to 1 if TX FIFO is empty. Otherwise, this bit is set to 0.  Default: 1. FIFO is empty at POR.  
+#define SPI_STATUS_0_TXF_EMPTY_SHIFT                    _MK_SHIFT_CONST(23)
+#define SPI_STATUS_0_TXF_EMPTY_FIELD                    (_MK_MASK_CONST(0x1) << SPI_STATUS_0_TXF_EMPTY_SHIFT)
+#define SPI_STATUS_0_TXF_EMPTY_RANGE                    23:23
+#define SPI_STATUS_0_TXF_EMPTY_WOFFSET                  0x0
+#define SPI_STATUS_0_TXF_EMPTY_DEFAULT                  _MK_MASK_CONST(0x1)
+#define SPI_STATUS_0_TXF_EMPTY_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define SPI_STATUS_0_TXF_EMPTY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SPI_STATUS_0_TXF_EMPTY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define SPI_STATUS_0_TXF_EMPTY_NOT_EMPTY                        _MK_ENUM_CONST(0)
+#define SPI_STATUS_0_TXF_EMPTY_EMPTY                    _MK_ENUM_CONST(1)
+
+// TX FIFO full status: RO.  Hardware sets this bit to 1 if TX FIFO is full. Otherwise, this bit is set to 0.  Default: 0. FIFO is empty at POR.  
+#define SPI_STATUS_0_TXF_FULL_SHIFT                     _MK_SHIFT_CONST(22)
+#define SPI_STATUS_0_TXF_FULL_FIELD                     (_MK_MASK_CONST(0x1) << SPI_STATUS_0_TXF_FULL_SHIFT)
+#define SPI_STATUS_0_TXF_FULL_RANGE                     22:22
+#define SPI_STATUS_0_TXF_FULL_WOFFSET                   0x0
+#define SPI_STATUS_0_TXF_FULL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SPI_STATUS_0_TXF_FULL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define SPI_STATUS_0_TXF_FULL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SPI_STATUS_0_TXF_FULL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define SPI_STATUS_0_TXF_FULL_NOT_FULL                  _MK_ENUM_CONST(0)
+#define SPI_STATUS_0_TXF_FULL_FULL                      _MK_ENUM_CONST(1)
+
+// Reserved = 0
+#define SPI_STATUS_0_N_A_6_SHIFT                        _MK_SHIFT_CONST(17)
+#define SPI_STATUS_0_N_A_6_FIELD                        (_MK_MASK_CONST(0x1f) << SPI_STATUS_0_N_A_6_SHIFT)
+#define SPI_STATUS_0_N_A_6_RANGE                        21:17
+#define SPI_STATUS_0_N_A_6_WOFFSET                      0x0
+#define SPI_STATUS_0_N_A_6_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SPI_STATUS_0_N_A_6_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define SPI_STATUS_0_N_A_6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SPI_STATUS_0_N_A_6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Selects whether the receive or transmit block count to be read in the field CUR_BLOCK_COUNT.  1: Transmit block count will be read in CUR_BLOCK_COUNT.  0: Receive block count will be read in CUR_BLOCK_COUNT.  Default: 0.  
+#define SPI_STATUS_0_SEL_TX_RX_N_SHIFT                  _MK_SHIFT_CONST(16)
+#define SPI_STATUS_0_SEL_TX_RX_N_FIELD                  (_MK_MASK_CONST(0x1) << SPI_STATUS_0_SEL_TX_RX_N_SHIFT)
+#define SPI_STATUS_0_SEL_TX_RX_N_RANGE                  16:16
+#define SPI_STATUS_0_SEL_TX_RX_N_WOFFSET                        0x0
+#define SPI_STATUS_0_SEL_TX_RX_N_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SPI_STATUS_0_SEL_TX_RX_N_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define SPI_STATUS_0_SEL_TX_RX_N_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SPI_STATUS_0_SEL_TX_RX_N_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define SPI_STATUS_0_SEL_TX_RX_N_SEL_RX_CNT                     _MK_ENUM_CONST(0)
+#define SPI_STATUS_0_SEL_TX_RX_N_SEL_TX_CNT                     _MK_ENUM_CONST(1)
+
+// Selects whether the receive or transmit block count to be read in the field CUR_BLOCK_COUNT.  1: Transmit block count will be read in CUR_BLOCK_COUNT.  0: Receive block count will be read in CUR_BLOCK_COUNT.  Default: 0.  
+#define SPI_STATUS_0_CUR_BLOCK_COUNT_SHIFT                      _MK_SHIFT_CONST(0)
+#define SPI_STATUS_0_CUR_BLOCK_COUNT_FIELD                      (_MK_MASK_CONST(0xffff) << SPI_STATUS_0_CUR_BLOCK_COUNT_SHIFT)
+#define SPI_STATUS_0_CUR_BLOCK_COUNT_RANGE                      15:0
+#define SPI_STATUS_0_CUR_BLOCK_COUNT_WOFFSET                    0x0
+#define SPI_STATUS_0_CUR_BLOCK_COUNT_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SPI_STATUS_0_CUR_BLOCK_COUNT_DEFAULT_MASK                       _MK_MASK_CONST(0xffff)
+#define SPI_STATUS_0_CUR_BLOCK_COUNT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SPI_STATUS_0_CUR_BLOCK_COUNT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register SPI_RX_CMP_0  
+#define SPI_RX_CMP_0                    _MK_ADDR_CONST(0x8)
+#define SPI_RX_CMP_0_WORD_COUNT                         0x1
+#define SPI_RX_CMP_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define SPI_RX_CMP_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
+#define SPI_RX_CMP_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define SPI_RX_CMP_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define SPI_RX_CMP_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define SPI_RX_CMP_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+// Reserved = 0
+#define SPI_RX_CMP_0_N_A_7_SHIFT                        _MK_SHIFT_CONST(17)
+#define SPI_RX_CMP_0_N_A_7_FIELD                        (_MK_MASK_CONST(0x7fff) << SPI_RX_CMP_0_N_A_7_SHIFT)
+#define SPI_RX_CMP_0_N_A_7_RANGE                        31:17
+#define SPI_RX_CMP_0_N_A_7_WOFFSET                      0x0
+#define SPI_RX_CMP_0_N_A_7_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SPI_RX_CMP_0_N_A_7_DEFAULT_MASK                 _MK_MASK_CONST(0x7fff)
+#define SPI_RX_CMP_0_N_A_7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SPI_RX_CMP_0_N_A_7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Enable Receive Compare mode.  1 = Enable receive compare mode. Data received on SDI signal is ignored until a compare match occurs, that is, if the mask on the data input by RXCMP_MASK matches the RXCMP_VAL. This is only valid if the BIT_LENGTH field in SPI_COMMAND register is set to 7 (8-bit packet length).  0 = Disable receive compare mode. All data received on SDI signal is placed in the RX FIFO.  Default: 0 
+#define SPI_RX_CMP_0_RXCMP_EN_SHIFT                     _MK_SHIFT_CONST(16)
+#define SPI_RX_CMP_0_RXCMP_EN_FIELD                     (_MK_MASK_CONST(0x1) << SPI_RX_CMP_0_RXCMP_EN_SHIFT)
+#define SPI_RX_CMP_0_RXCMP_EN_RANGE                     16:16
+#define SPI_RX_CMP_0_RXCMP_EN_WOFFSET                   0x0
+#define SPI_RX_CMP_0_RXCMP_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SPI_RX_CMP_0_RXCMP_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define SPI_RX_CMP_0_RXCMP_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SPI_RX_CMP_0_RXCMP_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define SPI_RX_CMP_0_RXCMP_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define SPI_RX_CMP_0_RXCMP_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// Mask on the receive data.  This mask value is applied to the receive data before comparing it to RXCMP_VAL for a match. A 1 in any bit position in RXCMP_MASK will exclude that bit position in the received data from comparing against corresponding bit position in RXCMP_VAL. Only the bits that have 0 will be compared.  Default: 0 
+#define SPI_RX_CMP_0_RXCMP_MASK_SHIFT                   _MK_SHIFT_CONST(8)
+#define SPI_RX_CMP_0_RXCMP_MASK_FIELD                   (_MK_MASK_CONST(0xff) << SPI_RX_CMP_0_RXCMP_MASK_SHIFT)
+#define SPI_RX_CMP_0_RXCMP_MASK_RANGE                   15:8
+#define SPI_RX_CMP_0_RXCMP_MASK_WOFFSET                 0x0
+#define SPI_RX_CMP_0_RXCMP_MASK_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SPI_RX_CMP_0_RXCMP_MASK_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define SPI_RX_CMP_0_RXCMP_MASK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SPI_RX_CMP_0_RXCMP_MASK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Receive compare value.  This value is compared to the received data after applying the mask in RXCMP_MASK.  Default:0 
+#define SPI_RX_CMP_0_RXCMP_VAL_SHIFT                    _MK_SHIFT_CONST(0)
+#define SPI_RX_CMP_0_RXCMP_VAL_FIELD                    (_MK_MASK_CONST(0xff) << SPI_RX_CMP_0_RXCMP_VAL_SHIFT)
+#define SPI_RX_CMP_0_RXCMP_VAL_RANGE                    7:0
+#define SPI_RX_CMP_0_RXCMP_VAL_WOFFSET                  0x0
+#define SPI_RX_CMP_0_RXCMP_VAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SPI_RX_CMP_0_RXCMP_VAL_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
+#define SPI_RX_CMP_0_RXCMP_VAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SPI_RX_CMP_0_RXCMP_VAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register SPI_DMA_CTL_0  
+#define SPI_DMA_CTL_0                   _MK_ADDR_CONST(0xc)
+#define SPI_DMA_CTL_0_WORD_COUNT                        0x1
+#define SPI_DMA_CTL_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define SPI_DMA_CTL_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
+#define SPI_DMA_CTL_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define SPI_DMA_CTL_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define SPI_DMA_CTL_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define SPI_DMA_CTL_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
+// Enable DMA mode transfer.  Software writes a 1 to this bit to start a transfer in the DMA mode. All fields in the SPI_COMMAND and SPI_DMA_CTL register must be set before writing a 1 to this bit. This bit is cleared by the controller after all packets have been transferred as indicated by the DMA_BLOCK_SIZE field.  Default: 0 
+#define SPI_DMA_CTL_0_DMA_EN_SHIFT                      _MK_SHIFT_CONST(31)
+#define SPI_DMA_CTL_0_DMA_EN_FIELD                      (_MK_MASK_CONST(0x1) << SPI_DMA_CTL_0_DMA_EN_SHIFT)
+#define SPI_DMA_CTL_0_DMA_EN_RANGE                      31:31
+#define SPI_DMA_CTL_0_DMA_EN_WOFFSET                    0x0
+#define SPI_DMA_CTL_0_DMA_EN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SPI_DMA_CTL_0_DMA_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define SPI_DMA_CTL_0_DMA_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SPI_DMA_CTL_0_DMA_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define SPI_DMA_CTL_0_DMA_EN_DISABLE                    _MK_ENUM_CONST(0)
+#define SPI_DMA_CTL_0_DMA_EN_ENABLE                     _MK_ENUM_CONST(1)
+
+// Reserved = 0
+#define SPI_DMA_CTL_0_N_A_8_SHIFT                       _MK_SHIFT_CONST(28)
+#define SPI_DMA_CTL_0_N_A_8_FIELD                       (_MK_MASK_CONST(0x7) << SPI_DMA_CTL_0_N_A_8_SHIFT)
+#define SPI_DMA_CTL_0_N_A_8_RANGE                       30:28
+#define SPI_DMA_CTL_0_N_A_8_WOFFSET                     0x0
+#define SPI_DMA_CTL_0_N_A_8_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SPI_DMA_CTL_0_N_A_8_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
+#define SPI_DMA_CTL_0_N_A_8_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SPI_DMA_CTL_0_N_A_8_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Interrupt enable on receive completion.  1 = Enable interrupt generation at the end of a receive transfer.  0 = Disable interrupt generation for receive.  Default: 0 
+#define SPI_DMA_CTL_0_IE_RXC_SHIFT                      _MK_SHIFT_CONST(27)
+#define SPI_DMA_CTL_0_IE_RXC_FIELD                      (_MK_MASK_CONST(0x1) << SPI_DMA_CTL_0_IE_RXC_SHIFT)
+#define SPI_DMA_CTL_0_IE_RXC_RANGE                      27:27
+#define SPI_DMA_CTL_0_IE_RXC_WOFFSET                    0x0
+#define SPI_DMA_CTL_0_IE_RXC_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SPI_DMA_CTL_0_IE_RXC_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define SPI_DMA_CTL_0_IE_RXC_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SPI_DMA_CTL_0_IE_RXC_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define SPI_DMA_CTL_0_IE_RXC_DISABLE                    _MK_ENUM_CONST(0)
+#define SPI_DMA_CTL_0_IE_RXC_ENABLE                     _MK_ENUM_CONST(1)
+
+// Interrupt enable on transmit completion.  1 = Enable interrupt generation at the end of a transmit transfer.  0 = Disable interrupt generation for transmit.  Default: 0 
+#define SPI_DMA_CTL_0_IE_TXC_SHIFT                      _MK_SHIFT_CONST(26)
+#define SPI_DMA_CTL_0_IE_TXC_FIELD                      (_MK_MASK_CONST(0x1) << SPI_DMA_CTL_0_IE_TXC_SHIFT)
+#define SPI_DMA_CTL_0_IE_TXC_RANGE                      26:26
+#define SPI_DMA_CTL_0_IE_TXC_WOFFSET                    0x0
+#define SPI_DMA_CTL_0_IE_TXC_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SPI_DMA_CTL_0_IE_TXC_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define SPI_DMA_CTL_0_IE_TXC_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SPI_DMA_CTL_0_IE_TXC_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define SPI_DMA_CTL_0_IE_TXC_DISABLE                    _MK_ENUM_CONST(0)
+#define SPI_DMA_CTL_0_IE_TXC_ENABLE                     _MK_ENUM_CONST(1)
+
+// Reserved = 0
+#define SPI_DMA_CTL_0_N_A_9_SHIFT                       _MK_SHIFT_CONST(21)
+#define SPI_DMA_CTL_0_N_A_9_FIELD                       (_MK_MASK_CONST(0x1f) << SPI_DMA_CTL_0_N_A_9_SHIFT)
+#define SPI_DMA_CTL_0_N_A_9_RANGE                       25:21
+#define SPI_DMA_CTL_0_N_A_9_WOFFSET                     0x0
+#define SPI_DMA_CTL_0_N_A_9_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SPI_DMA_CTL_0_N_A_9_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define SPI_DMA_CTL_0_N_A_9_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SPI_DMA_CTL_0_N_A_9_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Packed mode enable bit.  1 = Packed mode is enabled. This is only valid if BIT_LENGTH in SPI_COMMAND register is set to either 7 (8-bit transfer) or 15 (16-bit transfer). When enabled, all 32-bits of data in the FIFO contains valid data packets of either 8-bit or 16-bit length.  0 = Packed mode is disabled.  Default: 0 
+#define SPI_DMA_CTL_0_PACKED_SHIFT                      _MK_SHIFT_CONST(20)
+#define SPI_DMA_CTL_0_PACKED_FIELD                      (_MK_MASK_CONST(0x1) << SPI_DMA_CTL_0_PACKED_SHIFT)
+#define SPI_DMA_CTL_0_PACKED_RANGE                      20:20
+#define SPI_DMA_CTL_0_PACKED_WOFFSET                    0x0
+#define SPI_DMA_CTL_0_PACKED_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SPI_DMA_CTL_0_PACKED_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define SPI_DMA_CTL_0_PACKED_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SPI_DMA_CTL_0_PACKED_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define SPI_DMA_CTL_0_PACKED_DISABLE                    _MK_ENUM_CONST(0)
+#define SPI_DMA_CTL_0_PACKED_ENABLE                     _MK_ENUM_CONST(1)
+
+//  Receive FIFO Trigger level 00: 1 word. DMA trigger is asserted whenever there is space for at least 1 word in the TX FIFO.  01: 4 words. DMA trigger is asserted when there is space for 4 words in the TX FIFO.  10: Reserved.  11: Reserved
+#define SPI_DMA_CTL_0_RX_TRIG_SHIFT                     _MK_SHIFT_CONST(18)
+#define SPI_DMA_CTL_0_RX_TRIG_FIELD                     (_MK_MASK_CONST(0x3) << SPI_DMA_CTL_0_RX_TRIG_SHIFT)
+#define SPI_DMA_CTL_0_RX_TRIG_RANGE                     19:18
+#define SPI_DMA_CTL_0_RX_TRIG_WOFFSET                   0x0
+#define SPI_DMA_CTL_0_RX_TRIG_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SPI_DMA_CTL_0_RX_TRIG_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define SPI_DMA_CTL_0_RX_TRIG_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SPI_DMA_CTL_0_RX_TRIG_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define SPI_DMA_CTL_0_RX_TRIG_TRIG1                     _MK_ENUM_CONST(0)
+#define SPI_DMA_CTL_0_RX_TRIG_TRIG4                     _MK_ENUM_CONST(1)
+
+// Transmit FIFO trigger level.  00: 1 word. DMA trigger is asserted whenever there is space for at least 1 word in the TX FIFO.  01: 4 words. DMA trigger is asserted when there is space for 4 words in the TX FIFO.  10: Reserved.  11: Reserved.  Default: 00 
+#define SPI_DMA_CTL_0_TX_TRIG_SHIFT                     _MK_SHIFT_CONST(16)
+#define SPI_DMA_CTL_0_TX_TRIG_FIELD                     (_MK_MASK_CONST(0x3) << SPI_DMA_CTL_0_TX_TRIG_SHIFT)
+#define SPI_DMA_CTL_0_TX_TRIG_RANGE                     17:16
+#define SPI_DMA_CTL_0_TX_TRIG_WOFFSET                   0x0
+#define SPI_DMA_CTL_0_TX_TRIG_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SPI_DMA_CTL_0_TX_TRIG_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define SPI_DMA_CTL_0_TX_TRIG_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SPI_DMA_CTL_0_TX_TRIG_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define SPI_DMA_CTL_0_TX_TRIG_TRIG1                     _MK_ENUM_CONST(0)
+#define SPI_DMA_CTL_0_TX_TRIG_TRIG4                     _MK_ENUM_CONST(1)
+
+// Size of data block to be transferred using DMA mode.  This field specifies the size of the data block to be transferred through DMA mode.  N: N + 1 Data packets.  Default: 0 
+#define SPI_DMA_CTL_0_DMA_BLOCK_SIZE_SHIFT                      _MK_SHIFT_CONST(0)
+#define SPI_DMA_CTL_0_DMA_BLOCK_SIZE_FIELD                      (_MK_MASK_CONST(0xffff) << SPI_DMA_CTL_0_DMA_BLOCK_SIZE_SHIFT)
+#define SPI_DMA_CTL_0_DMA_BLOCK_SIZE_RANGE                      15:0
+#define SPI_DMA_CTL_0_DMA_BLOCK_SIZE_WOFFSET                    0x0
+#define SPI_DMA_CTL_0_DMA_BLOCK_SIZE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SPI_DMA_CTL_0_DMA_BLOCK_SIZE_DEFAULT_MASK                       _MK_MASK_CONST(0xffff)
+#define SPI_DMA_CTL_0_DMA_BLOCK_SIZE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SPI_DMA_CTL_0_DMA_BLOCK_SIZE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register SPI_TX_FIFO_0  
+#define SPI_TX_FIFO_0                   _MK_ADDR_CONST(0x10)
+#define SPI_TX_FIFO_0_WORD_COUNT                        0x1
+#define SPI_TX_FIFO_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define SPI_TX_FIFO_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
+#define SPI_TX_FIFO_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define SPI_TX_FIFO_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define SPI_TX_FIFO_0_READ_MASK                         _MK_MASK_CONST(0x0)
+#define SPI_TX_FIFO_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
+// TX FIFO
+#define SPI_TX_FIFO_0_SPI_TX_FIFO_SHIFT                 _MK_SHIFT_CONST(0)
+#define SPI_TX_FIFO_0_SPI_TX_FIFO_FIELD                 (_MK_MASK_CONST(0xffffffff) << SPI_TX_FIFO_0_SPI_TX_FIFO_SHIFT)
+#define SPI_TX_FIFO_0_SPI_TX_FIFO_RANGE                 31:0
+#define SPI_TX_FIFO_0_SPI_TX_FIFO_WOFFSET                       0x0
+#define SPI_TX_FIFO_0_SPI_TX_FIFO_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SPI_TX_FIFO_0_SPI_TX_FIFO_DEFAULT_MASK                  _MK_MASK_CONST(0xffffffff)
+#define SPI_TX_FIFO_0_SPI_TX_FIFO_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SPI_TX_FIFO_0_SPI_TX_FIFO_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Reserved address 20 [0x14] 
+
+// Reserved address 24 [0x18] 
+
+// Reserved address 28 [0x1c] 
+
+// Register SPI_RX_FIFO_0  
+#define SPI_RX_FIFO_0                   _MK_ADDR_CONST(0x20)
+#define SPI_RX_FIFO_0_WORD_COUNT                        0x1
+#define SPI_RX_FIFO_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define SPI_RX_FIFO_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
+#define SPI_RX_FIFO_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define SPI_RX_FIFO_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define SPI_RX_FIFO_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define SPI_RX_FIFO_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+// RX FIFO
+#define SPI_RX_FIFO_0_SPI_RX_FIFO_SHIFT                 _MK_SHIFT_CONST(0)
+#define SPI_RX_FIFO_0_SPI_RX_FIFO_FIELD                 (_MK_MASK_CONST(0xffffffff) << SPI_RX_FIFO_0_SPI_RX_FIFO_SHIFT)
+#define SPI_RX_FIFO_0_SPI_RX_FIFO_RANGE                 31:0
+#define SPI_RX_FIFO_0_SPI_RX_FIFO_WOFFSET                       0x0
+#define SPI_RX_FIFO_0_SPI_RX_FIFO_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SPI_RX_FIFO_0_SPI_RX_FIFO_DEFAULT_MASK                  _MK_MASK_CONST(0xffffffff)
+#define SPI_RX_FIFO_0_SPI_RX_FIFO_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SPI_RX_FIFO_0_SPI_RX_FIFO_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+//
+// REGISTER LIST
+//
+#define LIST_ARSPI_REGS(_op_) \
+_op_(SPI_COMMAND_0) \
+_op_(SPI_STATUS_0) \
+_op_(SPI_RX_CMP_0) \
+_op_(SPI_DMA_CTL_0) \
+_op_(SPI_TX_FIFO_0) \
+_op_(SPI_RX_FIFO_0)
+
+
+//
+// ADDRESS SPACES
+//
+
+#define BASE_ADDRESS_SPI        0x00000000
+
+//
+// ARSPI REGISTER BANKS
+//
+
+#define SPI0_FIRST_REG 0x0000 // SPI_COMMAND_0
+#define SPI0_LAST_REG 0x0010 // SPI_TX_FIFO_0
+#define SPI1_FIRST_REG 0x0020 // SPI_RX_FIFO_0
+#define SPI1_LAST_REG 0x0020 // SPI_RX_FIFO_0
+
+#ifndef _MK_SHIFT_CONST
+  #define _MK_SHIFT_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_MASK_CONST
+  #define _MK_MASK_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_ENUM_CONST
+  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
+#endif
+#ifndef _MK_ADDR_CONST
+  #define _MK_ADDR_CONST(_constant_) _constant_
+#endif
+
+#endif // ifndef ___ARSPI_H_INC_
diff --git a/arch/arm/mach-tegra/include/ap15/arstat_mon.h b/arch/arm/mach-tegra/include/ap15/arstat_mon.h
new file mode 100644
index 000000000000..f755e20b2571
--- /dev/null
+++ b/arch/arm/mach-tegra/include/ap15/arstat_mon.h
@@ -0,0 +1,1696 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+//
+// DO NOT EDIT - generated by simspec!
+//
+
+#ifndef ___ARSTAT_MON_H_INC_
+#define ___ARSTAT_MON_H_INC_
+
+// Register STAT_MON_GLB_INT_STATUS_0  
+#define STAT_MON_GLB_INT_STATUS_0                       _MK_ADDR_CONST(0x0)
+#define STAT_MON_GLB_INT_STATUS_0_WORD_COUNT                    0x1
+#define STAT_MON_GLB_INT_STATUS_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define STAT_MON_GLB_INT_STATUS_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
+#define STAT_MON_GLB_INT_STATUS_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define STAT_MON_GLB_INT_STATUS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define STAT_MON_GLB_INT_STATUS_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define STAT_MON_GLB_INT_STATUS_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+// CPU Monitor interrupt status. 1 = interrupt detected
+#define STAT_MON_GLB_INT_STATUS_0_CPU_INT_SHIFT                 _MK_SHIFT_CONST(31)
+#define STAT_MON_GLB_INT_STATUS_0_CPU_INT_FIELD                 (_MK_MASK_CONST(0x1) << STAT_MON_GLB_INT_STATUS_0_CPU_INT_SHIFT)
+#define STAT_MON_GLB_INT_STATUS_0_CPU_INT_RANGE                 31:31
+#define STAT_MON_GLB_INT_STATUS_0_CPU_INT_WOFFSET                       0x0
+#define STAT_MON_GLB_INT_STATUS_0_CPU_INT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define STAT_MON_GLB_INT_STATUS_0_CPU_INT_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define STAT_MON_GLB_INT_STATUS_0_CPU_INT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define STAT_MON_GLB_INT_STATUS_0_CPU_INT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define STAT_MON_GLB_INT_STATUS_0_CPU_INT_NOINT                 _MK_ENUM_CONST(0)    // // 0 = interrupt not detected
+
+#define STAT_MON_GLB_INT_STATUS_0_CPU_INT_INT                   _MK_ENUM_CONST(1)
+
+// COP Monitor interrupt status. 1 = interrupt detected
+#define STAT_MON_GLB_INT_STATUS_0_COP_INT_SHIFT                 _MK_SHIFT_CONST(30)
+#define STAT_MON_GLB_INT_STATUS_0_COP_INT_FIELD                 (_MK_MASK_CONST(0x1) << STAT_MON_GLB_INT_STATUS_0_COP_INT_SHIFT)
+#define STAT_MON_GLB_INT_STATUS_0_COP_INT_RANGE                 30:30
+#define STAT_MON_GLB_INT_STATUS_0_COP_INT_WOFFSET                       0x0
+#define STAT_MON_GLB_INT_STATUS_0_COP_INT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define STAT_MON_GLB_INT_STATUS_0_COP_INT_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define STAT_MON_GLB_INT_STATUS_0_COP_INT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define STAT_MON_GLB_INT_STATUS_0_COP_INT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define STAT_MON_GLB_INT_STATUS_0_COP_INT_NOINT                 _MK_ENUM_CONST(0)    // // 0 = interrupt not detected
+
+#define STAT_MON_GLB_INT_STATUS_0_COP_INT_INT                   _MK_ENUM_CONST(1)
+
+// Rsvd
+#define STAT_MON_GLB_INT_STATUS_0_N_A4_SHIFT                    _MK_SHIFT_CONST(29)
+#define STAT_MON_GLB_INT_STATUS_0_N_A4_FIELD                    (_MK_MASK_CONST(0x1) << STAT_MON_GLB_INT_STATUS_0_N_A4_SHIFT)
+#define STAT_MON_GLB_INT_STATUS_0_N_A4_RANGE                    29:29
+#define STAT_MON_GLB_INT_STATUS_0_N_A4_WOFFSET                  0x0
+#define STAT_MON_GLB_INT_STATUS_0_N_A4_DEFAULT                  _MK_MASK_CONST(0x0)
+#define STAT_MON_GLB_INT_STATUS_0_N_A4_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define STAT_MON_GLB_INT_STATUS_0_N_A4_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define STAT_MON_GLB_INT_STATUS_0_N_A4_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// COP Cache Monitor interrupt status. 1 = interrupt detected
+#define STAT_MON_GLB_INT_STATUS_0_CACHE2_INT_SHIFT                      _MK_SHIFT_CONST(28)
+#define STAT_MON_GLB_INT_STATUS_0_CACHE2_INT_FIELD                      (_MK_MASK_CONST(0x1) << STAT_MON_GLB_INT_STATUS_0_CACHE2_INT_SHIFT)
+#define STAT_MON_GLB_INT_STATUS_0_CACHE2_INT_RANGE                      28:28
+#define STAT_MON_GLB_INT_STATUS_0_CACHE2_INT_WOFFSET                    0x0
+#define STAT_MON_GLB_INT_STATUS_0_CACHE2_INT_DEFAULT                    _MK_MASK_CONST(0x0)
+#define STAT_MON_GLB_INT_STATUS_0_CACHE2_INT_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define STAT_MON_GLB_INT_STATUS_0_CACHE2_INT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define STAT_MON_GLB_INT_STATUS_0_CACHE2_INT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define STAT_MON_GLB_INT_STATUS_0_CACHE2_INT_NOINT                      _MK_ENUM_CONST(0)    // // 0 = interrupt not detected
+
+#define STAT_MON_GLB_INT_STATUS_0_CACHE2_INT_INT                        _MK_ENUM_CONST(1)
+
+// Memory Controller Monitor interrupt status. 1 = interrupt detected
+#define STAT_MON_GLB_INT_STATUS_0_MEM_INT_SHIFT                 _MK_SHIFT_CONST(27)
+#define STAT_MON_GLB_INT_STATUS_0_MEM_INT_FIELD                 (_MK_MASK_CONST(0x1) << STAT_MON_GLB_INT_STATUS_0_MEM_INT_SHIFT)
+#define STAT_MON_GLB_INT_STATUS_0_MEM_INT_RANGE                 27:27
+#define STAT_MON_GLB_INT_STATUS_0_MEM_INT_WOFFSET                       0x0
+#define STAT_MON_GLB_INT_STATUS_0_MEM_INT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define STAT_MON_GLB_INT_STATUS_0_MEM_INT_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define STAT_MON_GLB_INT_STATUS_0_MEM_INT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define STAT_MON_GLB_INT_STATUS_0_MEM_INT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define STAT_MON_GLB_INT_STATUS_0_MEM_INT_NOINT                 _MK_ENUM_CONST(0)    // // 0 = interrupt not detected
+
+#define STAT_MON_GLB_INT_STATUS_0_MEM_INT_INT                   _MK_ENUM_CONST(1)
+
+// Video Pipe Monitor interrupt status. 1 = interrupt detected
+#define STAT_MON_GLB_INT_STATUS_0_VPIPE_INT_SHIFT                       _MK_SHIFT_CONST(26)
+#define STAT_MON_GLB_INT_STATUS_0_VPIPE_INT_FIELD                       (_MK_MASK_CONST(0x1) << STAT_MON_GLB_INT_STATUS_0_VPIPE_INT_SHIFT)
+#define STAT_MON_GLB_INT_STATUS_0_VPIPE_INT_RANGE                       26:26
+#define STAT_MON_GLB_INT_STATUS_0_VPIPE_INT_WOFFSET                     0x0
+#define STAT_MON_GLB_INT_STATUS_0_VPIPE_INT_DEFAULT                     _MK_MASK_CONST(0x0)
+#define STAT_MON_GLB_INT_STATUS_0_VPIPE_INT_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define STAT_MON_GLB_INT_STATUS_0_VPIPE_INT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define STAT_MON_GLB_INT_STATUS_0_VPIPE_INT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define STAT_MON_GLB_INT_STATUS_0_VPIPE_INT_NOINT                       _MK_ENUM_CONST(0)    // // 0 = interrupt not detected
+
+#define STAT_MON_GLB_INT_STATUS_0_VPIPE_INT_INT                 _MK_ENUM_CONST(1)
+
+// AHB Monitor interrupt status. 1 = interrupt detected
+#define STAT_MON_GLB_INT_STATUS_0_AHB_INT_SHIFT                 _MK_SHIFT_CONST(25)
+#define STAT_MON_GLB_INT_STATUS_0_AHB_INT_FIELD                 (_MK_MASK_CONST(0x1) << STAT_MON_GLB_INT_STATUS_0_AHB_INT_SHIFT)
+#define STAT_MON_GLB_INT_STATUS_0_AHB_INT_RANGE                 25:25
+#define STAT_MON_GLB_INT_STATUS_0_AHB_INT_WOFFSET                       0x0
+#define STAT_MON_GLB_INT_STATUS_0_AHB_INT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define STAT_MON_GLB_INT_STATUS_0_AHB_INT_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define STAT_MON_GLB_INT_STATUS_0_AHB_INT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define STAT_MON_GLB_INT_STATUS_0_AHB_INT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define STAT_MON_GLB_INT_STATUS_0_AHB_INT_NOINT                 _MK_ENUM_CONST(0)    // // 0 = interrupt not detected
+
+#define STAT_MON_GLB_INT_STATUS_0_AHB_INT_INT                   _MK_ENUM_CONST(1)
+
+// APB Monitor interrupt status. 1 = interrupt detected
+#define STAT_MON_GLB_INT_STATUS_0_APB_INT_SHIFT                 _MK_SHIFT_CONST(24)
+#define STAT_MON_GLB_INT_STATUS_0_APB_INT_FIELD                 (_MK_MASK_CONST(0x1) << STAT_MON_GLB_INT_STATUS_0_APB_INT_SHIFT)
+#define STAT_MON_GLB_INT_STATUS_0_APB_INT_RANGE                 24:24
+#define STAT_MON_GLB_INT_STATUS_0_APB_INT_WOFFSET                       0x0
+#define STAT_MON_GLB_INT_STATUS_0_APB_INT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define STAT_MON_GLB_INT_STATUS_0_APB_INT_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define STAT_MON_GLB_INT_STATUS_0_APB_INT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define STAT_MON_GLB_INT_STATUS_0_APB_INT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define STAT_MON_GLB_INT_STATUS_0_APB_INT_NOINT                 _MK_ENUM_CONST(0)    // // 0 = interrupt not detected
+
+#define STAT_MON_GLB_INT_STATUS_0_APB_INT_INT                   _MK_ENUM_CONST(1)
+
+// Semaphore Monitor interrupt status. 1 = interrupt detected
+#define STAT_MON_GLB_INT_STATUS_0_SMP_INT_SHIFT                 _MK_SHIFT_CONST(23)
+#define STAT_MON_GLB_INT_STATUS_0_SMP_INT_FIELD                 (_MK_MASK_CONST(0x1) << STAT_MON_GLB_INT_STATUS_0_SMP_INT_SHIFT)
+#define STAT_MON_GLB_INT_STATUS_0_SMP_INT_RANGE                 23:23
+#define STAT_MON_GLB_INT_STATUS_0_SMP_INT_WOFFSET                       0x0
+#define STAT_MON_GLB_INT_STATUS_0_SMP_INT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define STAT_MON_GLB_INT_STATUS_0_SMP_INT_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define STAT_MON_GLB_INT_STATUS_0_SMP_INT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define STAT_MON_GLB_INT_STATUS_0_SMP_INT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define STAT_MON_GLB_INT_STATUS_0_SMP_INT_NOINT                 _MK_ENUM_CONST(0)    // // 0 = interrupt not detected
+
+#define STAT_MON_GLB_INT_STATUS_0_SMP_INT_INT                   _MK_ENUM_CONST(1)
+
+// Rsvd
+#define STAT_MON_GLB_INT_STATUS_0_N_A3_SHIFT                    _MK_SHIFT_CONST(16)
+#define STAT_MON_GLB_INT_STATUS_0_N_A3_FIELD                    (_MK_MASK_CONST(0x7f) << STAT_MON_GLB_INT_STATUS_0_N_A3_SHIFT)
+#define STAT_MON_GLB_INT_STATUS_0_N_A3_RANGE                    22:16
+#define STAT_MON_GLB_INT_STATUS_0_N_A3_WOFFSET                  0x0
+#define STAT_MON_GLB_INT_STATUS_0_N_A3_DEFAULT                  _MK_MASK_CONST(0x0)
+#define STAT_MON_GLB_INT_STATUS_0_N_A3_DEFAULT_MASK                     _MK_MASK_CONST(0x7f)
+#define STAT_MON_GLB_INT_STATUS_0_N_A3_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define STAT_MON_GLB_INT_STATUS_0_N_A3_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// CPU monitor active status.  1 = active
+#define STAT_MON_GLB_INT_STATUS_0_CPU_MON_ACT_SHIFT                     _MK_SHIFT_CONST(15)
+#define STAT_MON_GLB_INT_STATUS_0_CPU_MON_ACT_FIELD                     (_MK_MASK_CONST(0x1) << STAT_MON_GLB_INT_STATUS_0_CPU_MON_ACT_SHIFT)
+#define STAT_MON_GLB_INT_STATUS_0_CPU_MON_ACT_RANGE                     15:15
+#define STAT_MON_GLB_INT_STATUS_0_CPU_MON_ACT_WOFFSET                   0x0
+#define STAT_MON_GLB_INT_STATUS_0_CPU_MON_ACT_DEFAULT                   _MK_MASK_CONST(0x0)
+#define STAT_MON_GLB_INT_STATUS_0_CPU_MON_ACT_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define STAT_MON_GLB_INT_STATUS_0_CPU_MON_ACT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define STAT_MON_GLB_INT_STATUS_0_CPU_MON_ACT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define STAT_MON_GLB_INT_STATUS_0_CPU_MON_ACT_INACTIVE                  _MK_ENUM_CONST(0)    // // 0 = inactive
+
+#define STAT_MON_GLB_INT_STATUS_0_CPU_MON_ACT_ACTIVE                    _MK_ENUM_CONST(1)
+
+// COP monitor active status. 0 = inactive. 1 = active
+#define STAT_MON_GLB_INT_STATUS_0_COP_MON_ACT_SHIFT                     _MK_SHIFT_CONST(14)
+#define STAT_MON_GLB_INT_STATUS_0_COP_MON_ACT_FIELD                     (_MK_MASK_CONST(0x1) << STAT_MON_GLB_INT_STATUS_0_COP_MON_ACT_SHIFT)
+#define STAT_MON_GLB_INT_STATUS_0_COP_MON_ACT_RANGE                     14:14
+#define STAT_MON_GLB_INT_STATUS_0_COP_MON_ACT_WOFFSET                   0x0
+#define STAT_MON_GLB_INT_STATUS_0_COP_MON_ACT_DEFAULT                   _MK_MASK_CONST(0x0)
+#define STAT_MON_GLB_INT_STATUS_0_COP_MON_ACT_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define STAT_MON_GLB_INT_STATUS_0_COP_MON_ACT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define STAT_MON_GLB_INT_STATUS_0_COP_MON_ACT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define STAT_MON_GLB_INT_STATUS_0_COP_MON_ACT_INACTIVE                  _MK_ENUM_CONST(0)    // // 0 = inactive
+
+#define STAT_MON_GLB_INT_STATUS_0_COP_MON_ACT_ACTIVE                    _MK_ENUM_CONST(1)
+
+// Rsvd
+#define STAT_MON_GLB_INT_STATUS_0_N_A2_SHIFT                    _MK_SHIFT_CONST(13)
+#define STAT_MON_GLB_INT_STATUS_0_N_A2_FIELD                    (_MK_MASK_CONST(0x1) << STAT_MON_GLB_INT_STATUS_0_N_A2_SHIFT)
+#define STAT_MON_GLB_INT_STATUS_0_N_A2_RANGE                    13:13
+#define STAT_MON_GLB_INT_STATUS_0_N_A2_WOFFSET                  0x0
+#define STAT_MON_GLB_INT_STATUS_0_N_A2_DEFAULT                  _MK_MASK_CONST(0x0)
+#define STAT_MON_GLB_INT_STATUS_0_N_A2_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define STAT_MON_GLB_INT_STATUS_0_N_A2_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define STAT_MON_GLB_INT_STATUS_0_N_A2_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// COP cache monitor active status. 0 = inactive. 1 = active
+#define STAT_MON_GLB_INT_STATUS_0_CACHE2_MON_ACT_SHIFT                  _MK_SHIFT_CONST(12)
+#define STAT_MON_GLB_INT_STATUS_0_CACHE2_MON_ACT_FIELD                  (_MK_MASK_CONST(0x1) << STAT_MON_GLB_INT_STATUS_0_CACHE2_MON_ACT_SHIFT)
+#define STAT_MON_GLB_INT_STATUS_0_CACHE2_MON_ACT_RANGE                  12:12
+#define STAT_MON_GLB_INT_STATUS_0_CACHE2_MON_ACT_WOFFSET                        0x0
+#define STAT_MON_GLB_INT_STATUS_0_CACHE2_MON_ACT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define STAT_MON_GLB_INT_STATUS_0_CACHE2_MON_ACT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define STAT_MON_GLB_INT_STATUS_0_CACHE2_MON_ACT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define STAT_MON_GLB_INT_STATUS_0_CACHE2_MON_ACT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define STAT_MON_GLB_INT_STATUS_0_CACHE2_MON_ACT_INACTIVE                       _MK_ENUM_CONST(0)    // // 0 = inactive
+
+#define STAT_MON_GLB_INT_STATUS_0_CACHE2_MON_ACT_ACTIVE                 _MK_ENUM_CONST(1)
+
+// Rsvd
+#define STAT_MON_GLB_INT_STATUS_0_N_A1_SHIFT                    _MK_SHIFT_CONST(11)
+#define STAT_MON_GLB_INT_STATUS_0_N_A1_FIELD                    (_MK_MASK_CONST(0x1) << STAT_MON_GLB_INT_STATUS_0_N_A1_SHIFT)
+#define STAT_MON_GLB_INT_STATUS_0_N_A1_RANGE                    11:11
+#define STAT_MON_GLB_INT_STATUS_0_N_A1_WOFFSET                  0x0
+#define STAT_MON_GLB_INT_STATUS_0_N_A1_DEFAULT                  _MK_MASK_CONST(0x0)
+#define STAT_MON_GLB_INT_STATUS_0_N_A1_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define STAT_MON_GLB_INT_STATUS_0_N_A1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define STAT_MON_GLB_INT_STATUS_0_N_A1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// 0 = inactive. 1 = active
+#define STAT_MON_GLB_INT_STATUS_0_VPIPE_MON_ACT_SHIFT                   _MK_SHIFT_CONST(10)
+#define STAT_MON_GLB_INT_STATUS_0_VPIPE_MON_ACT_FIELD                   (_MK_MASK_CONST(0x1) << STAT_MON_GLB_INT_STATUS_0_VPIPE_MON_ACT_SHIFT)
+#define STAT_MON_GLB_INT_STATUS_0_VPIPE_MON_ACT_RANGE                   10:10
+#define STAT_MON_GLB_INT_STATUS_0_VPIPE_MON_ACT_WOFFSET                 0x0
+#define STAT_MON_GLB_INT_STATUS_0_VPIPE_MON_ACT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define STAT_MON_GLB_INT_STATUS_0_VPIPE_MON_ACT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define STAT_MON_GLB_INT_STATUS_0_VPIPE_MON_ACT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define STAT_MON_GLB_INT_STATUS_0_VPIPE_MON_ACT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define STAT_MON_GLB_INT_STATUS_0_VPIPE_MON_ACT_INACTIVE                        _MK_ENUM_CONST(0)    // // 0 = inactive
+
+#define STAT_MON_GLB_INT_STATUS_0_VPIPE_MON_ACT_ACTIVE                  _MK_ENUM_CONST(1)
+
+// 0 = inactive. 1 = active
+#define STAT_MON_GLB_INT_STATUS_0_AHB_MON_ACT_SHIFT                     _MK_SHIFT_CONST(9)
+#define STAT_MON_GLB_INT_STATUS_0_AHB_MON_ACT_FIELD                     (_MK_MASK_CONST(0x1) << STAT_MON_GLB_INT_STATUS_0_AHB_MON_ACT_SHIFT)
+#define STAT_MON_GLB_INT_STATUS_0_AHB_MON_ACT_RANGE                     9:9
+#define STAT_MON_GLB_INT_STATUS_0_AHB_MON_ACT_WOFFSET                   0x0
+#define STAT_MON_GLB_INT_STATUS_0_AHB_MON_ACT_DEFAULT                   _MK_MASK_CONST(0x0)
+#define STAT_MON_GLB_INT_STATUS_0_AHB_MON_ACT_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define STAT_MON_GLB_INT_STATUS_0_AHB_MON_ACT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define STAT_MON_GLB_INT_STATUS_0_AHB_MON_ACT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define STAT_MON_GLB_INT_STATUS_0_AHB_MON_ACT_INACTIVE                  _MK_ENUM_CONST(0)    // // 0 = inactive
+
+#define STAT_MON_GLB_INT_STATUS_0_AHB_MON_ACT_ACTIVE                    _MK_ENUM_CONST(1)
+
+// 0 = inactive. 1 = active
+#define STAT_MON_GLB_INT_STATUS_0_APB_MON_ACT_SHIFT                     _MK_SHIFT_CONST(8)
+#define STAT_MON_GLB_INT_STATUS_0_APB_MON_ACT_FIELD                     (_MK_MASK_CONST(0x1) << STAT_MON_GLB_INT_STATUS_0_APB_MON_ACT_SHIFT)
+#define STAT_MON_GLB_INT_STATUS_0_APB_MON_ACT_RANGE                     8:8
+#define STAT_MON_GLB_INT_STATUS_0_APB_MON_ACT_WOFFSET                   0x0
+#define STAT_MON_GLB_INT_STATUS_0_APB_MON_ACT_DEFAULT                   _MK_MASK_CONST(0x0)
+#define STAT_MON_GLB_INT_STATUS_0_APB_MON_ACT_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define STAT_MON_GLB_INT_STATUS_0_APB_MON_ACT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define STAT_MON_GLB_INT_STATUS_0_APB_MON_ACT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define STAT_MON_GLB_INT_STATUS_0_APB_MON_ACT_INACTIVE                  _MK_ENUM_CONST(0)    // // 0 = inactive
+
+#define STAT_MON_GLB_INT_STATUS_0_APB_MON_ACT_ACTIVE                    _MK_ENUM_CONST(1)
+
+// 0 = inactive. 1 = active
+#define STAT_MON_GLB_INT_STATUS_0_SMP_MON_ACT_SHIFT                     _MK_SHIFT_CONST(7)
+#define STAT_MON_GLB_INT_STATUS_0_SMP_MON_ACT_FIELD                     (_MK_MASK_CONST(0x1) << STAT_MON_GLB_INT_STATUS_0_SMP_MON_ACT_SHIFT)
+#define STAT_MON_GLB_INT_STATUS_0_SMP_MON_ACT_RANGE                     7:7
+#define STAT_MON_GLB_INT_STATUS_0_SMP_MON_ACT_WOFFSET                   0x0
+#define STAT_MON_GLB_INT_STATUS_0_SMP_MON_ACT_DEFAULT                   _MK_MASK_CONST(0x0)
+#define STAT_MON_GLB_INT_STATUS_0_SMP_MON_ACT_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define STAT_MON_GLB_INT_STATUS_0_SMP_MON_ACT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define STAT_MON_GLB_INT_STATUS_0_SMP_MON_ACT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define STAT_MON_GLB_INT_STATUS_0_SMP_MON_ACT_INACTIVE                  _MK_ENUM_CONST(0)    // // 0 = inactive
+
+#define STAT_MON_GLB_INT_STATUS_0_SMP_MON_ACT_ACTIVE                    _MK_ENUM_CONST(1)
+
+// Rsvd
+#define STAT_MON_GLB_INT_STATUS_0_N_A0_SHIFT                    _MK_SHIFT_CONST(0)
+#define STAT_MON_GLB_INT_STATUS_0_N_A0_FIELD                    (_MK_MASK_CONST(0x7f) << STAT_MON_GLB_INT_STATUS_0_N_A0_SHIFT)
+#define STAT_MON_GLB_INT_STATUS_0_N_A0_RANGE                    6:0
+#define STAT_MON_GLB_INT_STATUS_0_N_A0_WOFFSET                  0x0
+#define STAT_MON_GLB_INT_STATUS_0_N_A0_DEFAULT                  _MK_MASK_CONST(0x0)
+#define STAT_MON_GLB_INT_STATUS_0_N_A0_DEFAULT_MASK                     _MK_MASK_CONST(0x7f)
+#define STAT_MON_GLB_INT_STATUS_0_N_A0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define STAT_MON_GLB_INT_STATUS_0_N_A0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Reserved address 4 [0x4] 
+
+// Reserved address 8 [0x8] 
+
+// Reserved address 12 [0xc] 
+
+// Reserved address 16 [0x10] 
+
+// Reserved address 20 [0x14] 
+
+// Reserved address 24 [0x18] 
+
+// Reserved address 28 [0x1c] 
+
+// Reserved address 32 [0x20] 
+
+// Reserved address 36 [0x24] 
+
+// Reserved address 40 [0x28] 
+
+// Reserved address 44 [0x2c] 
+
+// Reserved address 48 [0x30] 
+
+// Reserved address 52 [0x34] 
+
+// Reserved address 56 [0x38] 
+
+// Reserved address 60 [0x3c] 
+
+// Reserved address 64 [0x40] 
+
+// Reserved address 68 [0x44] 
+
+// Reserved address 72 [0x48] 
+
+// Reserved address 76 [0x4c] 
+
+// Reserved address 80 [0x50] 
+
+// Reserved address 84 [0x54] 
+
+// Reserved address 88 [0x58] 
+
+// Reserved address 92 [0x5c] 
+
+// Reserved address 96 [0x60] 
+
+// Reserved address 100 [0x64] 
+
+// Reserved address 104 [0x68] 
+
+// Reserved address 108 [0x6c] 
+
+// Reserved address 112 [0x70] 
+
+// Reserved address 116 [0x74] 
+
+// Reserved address 120 [0x78] 
+
+// Reserved address 124 [0x7c] 
+
+// Reserved address 128 [0x80] 
+
+// Reserved address 132 [0x84] 
+
+// Reserved address 136 [0x88] 
+
+// Reserved address 140 [0x8c] 
+
+// Reserved address 144 [0x90] 
+
+// Reserved address 148 [0x94] 
+
+// Reserved address 152 [0x98] 
+
+// Reserved address 156 [0x9c] 
+
+// Reserved address 160 [0xa0] 
+
+// Reserved address 164 [0xa4] 
+
+// Reserved address 168 [0xa8] 
+
+// Reserved address 172 [0xac] 
+
+// Reserved address 176 [0xb0] 
+
+// Reserved address 180 [0xb4] 
+
+// Reserved address 184 [0xb8] 
+
+// Reserved address 188 [0xbc] 
+
+// Reserved address 192 [0xc0] 
+
+// Reserved address 196 [0xc4] 
+
+// Reserved address 200 [0xc8] 
+
+// Reserved address 204 [0xcc] 
+
+// Reserved address 208 [0xd0] 
+
+// Reserved address 212 [0xd4] 
+
+// Reserved address 216 [0xd8] 
+
+// Reserved address 220 [0xdc] 
+
+// Reserved address 224 [0xe0] 
+
+// Reserved address 228 [0xe4] 
+
+// Reserved address 232 [0xe8] 
+
+// Reserved address 236 [0xec] 
+
+// Reserved address 240 [0xf0] 
+
+// Reserved address 244 [0xf4] 
+
+// Reserved address 248 [0xf8] 
+
+// Reserved address 252 [0xfc] 
+
+// Register STAT_MON_CPU_MON_CTRL_0  
+#define STAT_MON_CPU_MON_CTRL_0                 _MK_ADDR_CONST(0x100)
+#define STAT_MON_CPU_MON_CTRL_0_WORD_COUNT                      0x1
+#define STAT_MON_CPU_MON_CTRL_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define STAT_MON_CPU_MON_CTRL_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define STAT_MON_CPU_MON_CTRL_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define STAT_MON_CPU_MON_CTRL_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define STAT_MON_CPU_MON_CTRL_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define STAT_MON_CPU_MON_CTRL_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Enable Monitor. Set by SW to enable sampling. cpu monitor is enabled.
+// Cleared in one of the following ways,
+// (a) When SW intends to stop the  monitor, it can do so by clearing this field,
+// (b) when the sampling period  expires, or
+// (c) in case of indefinite sampling mode, 
+// the field is cleared  when the statistic counter overflows.
+#define STAT_MON_CPU_MON_CTRL_0_ENB_SHIFT                       _MK_SHIFT_CONST(31)
+#define STAT_MON_CPU_MON_CTRL_0_ENB_FIELD                       (_MK_MASK_CONST(0x1) << STAT_MON_CPU_MON_CTRL_0_ENB_SHIFT)
+#define STAT_MON_CPU_MON_CTRL_0_ENB_RANGE                       31:31
+#define STAT_MON_CPU_MON_CTRL_0_ENB_WOFFSET                     0x0
+#define STAT_MON_CPU_MON_CTRL_0_ENB_DEFAULT                     _MK_MASK_CONST(0x0)
+#define STAT_MON_CPU_MON_CTRL_0_ENB_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define STAT_MON_CPU_MON_CTRL_0_ENB_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define STAT_MON_CPU_MON_CTRL_0_ENB_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define STAT_MON_CPU_MON_CTRL_0_ENB_DISABLE                     _MK_ENUM_CONST(0)    // // cpu monitor is disabled.     
+
+#define STAT_MON_CPU_MON_CTRL_0_ENB_ENABLE                      _MK_ENUM_CONST(1)
+
+// Enable interrupt when sampling period expires. interrupt is enabled.
+#define STAT_MON_CPU_MON_CTRL_0_INT_EN_SHIFT                    _MK_SHIFT_CONST(30)
+#define STAT_MON_CPU_MON_CTRL_0_INT_EN_FIELD                    (_MK_MASK_CONST(0x1) << STAT_MON_CPU_MON_CTRL_0_INT_EN_SHIFT)
+#define STAT_MON_CPU_MON_CTRL_0_INT_EN_RANGE                    30:30
+#define STAT_MON_CPU_MON_CTRL_0_INT_EN_WOFFSET                  0x0
+#define STAT_MON_CPU_MON_CTRL_0_INT_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define STAT_MON_CPU_MON_CTRL_0_INT_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define STAT_MON_CPU_MON_CTRL_0_INT_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define STAT_MON_CPU_MON_CTRL_0_INT_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define STAT_MON_CPU_MON_CTRL_0_INT_EN_DISABLE                  _MK_ENUM_CONST(0)    // // interrupt is disabled.     
+
+#define STAT_MON_CPU_MON_CTRL_0_INT_EN_ENABLE                   _MK_ENUM_CONST(1)
+
+// Assert by HW when sampling period expires when  INT_EN is set. 1 = interrupt detected
+// SW writing a 1 clears this bit. Writing 0 is ignored.
+#define STAT_MON_CPU_MON_CTRL_0_INT_SHIFT                       _MK_SHIFT_CONST(29)
+#define STAT_MON_CPU_MON_CTRL_0_INT_FIELD                       (_MK_MASK_CONST(0x1) << STAT_MON_CPU_MON_CTRL_0_INT_SHIFT)
+#define STAT_MON_CPU_MON_CTRL_0_INT_RANGE                       29:29
+#define STAT_MON_CPU_MON_CTRL_0_INT_WOFFSET                     0x0
+#define STAT_MON_CPU_MON_CTRL_0_INT_DEFAULT                     _MK_MASK_CONST(0x0)
+#define STAT_MON_CPU_MON_CTRL_0_INT_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define STAT_MON_CPU_MON_CTRL_0_INT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define STAT_MON_CPU_MON_CTRL_0_INT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define STAT_MON_CPU_MON_CTRL_0_INT_NOINT                       _MK_ENUM_CONST(0)    // // 0 = interrupt not detected
+
+#define STAT_MON_CPU_MON_CTRL_0_INT_INT                 _MK_ENUM_CONST(1)
+
+// 0 = sample only for the period mentioned in  SAMPLE_PERIOD. sample mode is enabled.
+#define STAT_MON_CPU_MON_CTRL_0_SAMPLE_MODE_SHIFT                       _MK_SHIFT_CONST(28)
+#define STAT_MON_CPU_MON_CTRL_0_SAMPLE_MODE_FIELD                       (_MK_MASK_CONST(0x1) << STAT_MON_CPU_MON_CTRL_0_SAMPLE_MODE_SHIFT)
+#define STAT_MON_CPU_MON_CTRL_0_SAMPLE_MODE_RANGE                       28:28
+#define STAT_MON_CPU_MON_CTRL_0_SAMPLE_MODE_WOFFSET                     0x0
+#define STAT_MON_CPU_MON_CTRL_0_SAMPLE_MODE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define STAT_MON_CPU_MON_CTRL_0_SAMPLE_MODE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define STAT_MON_CPU_MON_CTRL_0_SAMPLE_MODE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define STAT_MON_CPU_MON_CTRL_0_SAMPLE_MODE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define STAT_MON_CPU_MON_CTRL_0_SAMPLE_MODE_DISABLE                     _MK_ENUM_CONST(0)    // // sample mode is disabled.     
+
+#define STAT_MON_CPU_MON_CTRL_0_SAMPLE_MODE_ENABLE                      _MK_ENUM_CONST(1)
+
+// Sampling period in milliseconds (implemented as  n+1 counter).
+// Programming a 0 imply a 1 millisecond sampling period.
+#define STAT_MON_CPU_MON_CTRL_0_SAMPLE_PERIOD_SHIFT                     _MK_SHIFT_CONST(20)
+#define STAT_MON_CPU_MON_CTRL_0_SAMPLE_PERIOD_FIELD                     (_MK_MASK_CONST(0xff) << STAT_MON_CPU_MON_CTRL_0_SAMPLE_PERIOD_SHIFT)
+#define STAT_MON_CPU_MON_CTRL_0_SAMPLE_PERIOD_RANGE                     27:20
+#define STAT_MON_CPU_MON_CTRL_0_SAMPLE_PERIOD_WOFFSET                   0x0
+#define STAT_MON_CPU_MON_CTRL_0_SAMPLE_PERIOD_DEFAULT                   _MK_MASK_CONST(0x0)
+#define STAT_MON_CPU_MON_CTRL_0_SAMPLE_PERIOD_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define STAT_MON_CPU_MON_CTRL_0_SAMPLE_PERIOD_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define STAT_MON_CPU_MON_CTRL_0_SAMPLE_PERIOD_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Reserved
+#define STAT_MON_CPU_MON_CTRL_0_N_A_SHIFT                       _MK_SHIFT_CONST(4)
+#define STAT_MON_CPU_MON_CTRL_0_N_A_FIELD                       (_MK_MASK_CONST(0xffff) << STAT_MON_CPU_MON_CTRL_0_N_A_SHIFT)
+#define STAT_MON_CPU_MON_CTRL_0_N_A_RANGE                       19:4
+#define STAT_MON_CPU_MON_CTRL_0_N_A_WOFFSET                     0x0
+#define STAT_MON_CPU_MON_CTRL_0_N_A_DEFAULT                     _MK_MASK_CONST(0x0)
+#define STAT_MON_CPU_MON_CTRL_0_N_A_DEFAULT_MASK                        _MK_MASK_CONST(0xffff)
+#define STAT_MON_CPU_MON_CTRL_0_N_A_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define STAT_MON_CPU_MON_CTRL_0_N_A_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// 4b0000 = automatically detect CPU idle  condition.
+// Idle is defined as the period when the halt bit to the 
+// processor is asserted in the flow controller.
+#define STAT_MON_CPU_MON_CTRL_0_SAMPLE_COND_SHIFT                       _MK_SHIFT_CONST(0)
+#define STAT_MON_CPU_MON_CTRL_0_SAMPLE_COND_FIELD                       (_MK_MASK_CONST(0xf) << STAT_MON_CPU_MON_CTRL_0_SAMPLE_COND_SHIFT)
+#define STAT_MON_CPU_MON_CTRL_0_SAMPLE_COND_RANGE                       3:0
+#define STAT_MON_CPU_MON_CTRL_0_SAMPLE_COND_WOFFSET                     0x0
+#define STAT_MON_CPU_MON_CTRL_0_SAMPLE_COND_DEFAULT                     _MK_MASK_CONST(0x0)
+#define STAT_MON_CPU_MON_CTRL_0_SAMPLE_COND_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define STAT_MON_CPU_MON_CTRL_0_SAMPLE_COND_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define STAT_MON_CPU_MON_CTRL_0_SAMPLE_COND_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register STAT_MON_CPU_MON_STATUS_0  
+#define STAT_MON_CPU_MON_STATUS_0                       _MK_ADDR_CONST(0x104)
+#define STAT_MON_CPU_MON_STATUS_0_WORD_COUNT                    0x1
+#define STAT_MON_CPU_MON_STATUS_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define STAT_MON_CPU_MON_STATUS_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
+#define STAT_MON_CPU_MON_STATUS_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define STAT_MON_CPU_MON_STATUS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define STAT_MON_CPU_MON_STATUS_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define STAT_MON_CPU_MON_STATUS_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+// Indicates the number of idle cycles.
+// A value of  FFFF:FFFF is an overflow condition.
+// If the counter hits this value, it does  not increment from here.
+// This counter is always reset when the monitor is  enabled the next time.
+#define STAT_MON_CPU_MON_STATUS_0_COUNT_SHIFT                   _MK_SHIFT_CONST(0)
+#define STAT_MON_CPU_MON_STATUS_0_COUNT_FIELD                   (_MK_MASK_CONST(0xffffffff) << STAT_MON_CPU_MON_STATUS_0_COUNT_SHIFT)
+#define STAT_MON_CPU_MON_STATUS_0_COUNT_RANGE                   31:0
+#define STAT_MON_CPU_MON_STATUS_0_COUNT_WOFFSET                 0x0
+#define STAT_MON_CPU_MON_STATUS_0_COUNT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define STAT_MON_CPU_MON_STATUS_0_COUNT_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
+#define STAT_MON_CPU_MON_STATUS_0_COUNT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define STAT_MON_CPU_MON_STATUS_0_COUNT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Reserved address 264 [0x108] 
+
+// Reserved address 268 [0x10c] 
+
+// Reserved address 272 [0x110] 
+
+// Reserved address 276 [0x114] 
+
+// Reserved address 280 [0x118] 
+
+// Reserved address 284 [0x11c] 
+
+// Register STAT_MON_COP_MON_CTRL_0  
+#define STAT_MON_COP_MON_CTRL_0                 _MK_ADDR_CONST(0x120)
+#define STAT_MON_COP_MON_CTRL_0_WORD_COUNT                      0x1
+#define STAT_MON_COP_MON_CTRL_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define STAT_MON_COP_MON_CTRL_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define STAT_MON_COP_MON_CTRL_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define STAT_MON_COP_MON_CTRL_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define STAT_MON_COP_MON_CTRL_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define STAT_MON_COP_MON_CTRL_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Enable Monitor. Set by SW to enable sampling. cop monitor is enabled.
+// Cleared in one of the following ways, 
+// (a) When SW intends to stop the  monitor, it can do so by clearing this field, 
+// (b) when the sampling period  expires, or
+// (c) in case of indefinite sampling mode, the field is cleared
+// when the statistic counter overflows.
+#define STAT_MON_COP_MON_CTRL_0_ENB_SHIFT                       _MK_SHIFT_CONST(31)
+#define STAT_MON_COP_MON_CTRL_0_ENB_FIELD                       (_MK_MASK_CONST(0x1) << STAT_MON_COP_MON_CTRL_0_ENB_SHIFT)
+#define STAT_MON_COP_MON_CTRL_0_ENB_RANGE                       31:31
+#define STAT_MON_COP_MON_CTRL_0_ENB_WOFFSET                     0x0
+#define STAT_MON_COP_MON_CTRL_0_ENB_DEFAULT                     _MK_MASK_CONST(0x0)
+#define STAT_MON_COP_MON_CTRL_0_ENB_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define STAT_MON_COP_MON_CTRL_0_ENB_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define STAT_MON_COP_MON_CTRL_0_ENB_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define STAT_MON_COP_MON_CTRL_0_ENB_DISABLE                     _MK_ENUM_CONST(0)    // // cop monitor is disabled.     
+
+#define STAT_MON_COP_MON_CTRL_0_ENB_ENABLE                      _MK_ENUM_CONST(1)
+
+// Enable interrupt when sampling period expires. interrupt is enabled.
+#define STAT_MON_COP_MON_CTRL_0_INT_EN_SHIFT                    _MK_SHIFT_CONST(30)
+#define STAT_MON_COP_MON_CTRL_0_INT_EN_FIELD                    (_MK_MASK_CONST(0x1) << STAT_MON_COP_MON_CTRL_0_INT_EN_SHIFT)
+#define STAT_MON_COP_MON_CTRL_0_INT_EN_RANGE                    30:30
+#define STAT_MON_COP_MON_CTRL_0_INT_EN_WOFFSET                  0x0
+#define STAT_MON_COP_MON_CTRL_0_INT_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define STAT_MON_COP_MON_CTRL_0_INT_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define STAT_MON_COP_MON_CTRL_0_INT_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define STAT_MON_COP_MON_CTRL_0_INT_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define STAT_MON_COP_MON_CTRL_0_INT_EN_DISABLE                  _MK_ENUM_CONST(0)    // // interrupt is disabled.     
+
+#define STAT_MON_COP_MON_CTRL_0_INT_EN_ENABLE                   _MK_ENUM_CONST(1)
+
+// Assert by HW when sampling period expires when  INT_EN is set. 1 = interrupt detected
+// SW writing a 1 clears this bit. Writing 0 is ignored.
+#define STAT_MON_COP_MON_CTRL_0_INT_SHIFT                       _MK_SHIFT_CONST(29)
+#define STAT_MON_COP_MON_CTRL_0_INT_FIELD                       (_MK_MASK_CONST(0x1) << STAT_MON_COP_MON_CTRL_0_INT_SHIFT)
+#define STAT_MON_COP_MON_CTRL_0_INT_RANGE                       29:29
+#define STAT_MON_COP_MON_CTRL_0_INT_WOFFSET                     0x0
+#define STAT_MON_COP_MON_CTRL_0_INT_DEFAULT                     _MK_MASK_CONST(0x0)
+#define STAT_MON_COP_MON_CTRL_0_INT_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define STAT_MON_COP_MON_CTRL_0_INT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define STAT_MON_COP_MON_CTRL_0_INT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define STAT_MON_COP_MON_CTRL_0_INT_NOINT                       _MK_ENUM_CONST(0)    // // 0 = interrupt not detected
+
+#define STAT_MON_COP_MON_CTRL_0_INT_INT                 _MK_ENUM_CONST(1)
+
+// 0 = sample only for the period mentioned in  SAMPLE_PERIOD. sample mode is enabled.
+#define STAT_MON_COP_MON_CTRL_0_SAMPLE_MODE_SHIFT                       _MK_SHIFT_CONST(28)
+#define STAT_MON_COP_MON_CTRL_0_SAMPLE_MODE_FIELD                       (_MK_MASK_CONST(0x1) << STAT_MON_COP_MON_CTRL_0_SAMPLE_MODE_SHIFT)
+#define STAT_MON_COP_MON_CTRL_0_SAMPLE_MODE_RANGE                       28:28
+#define STAT_MON_COP_MON_CTRL_0_SAMPLE_MODE_WOFFSET                     0x0
+#define STAT_MON_COP_MON_CTRL_0_SAMPLE_MODE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define STAT_MON_COP_MON_CTRL_0_SAMPLE_MODE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define STAT_MON_COP_MON_CTRL_0_SAMPLE_MODE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define STAT_MON_COP_MON_CTRL_0_SAMPLE_MODE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define STAT_MON_COP_MON_CTRL_0_SAMPLE_MODE_DISABLE                     _MK_ENUM_CONST(0)    // // sample mode is disabled.     
+
+#define STAT_MON_COP_MON_CTRL_0_SAMPLE_MODE_ENABLE                      _MK_ENUM_CONST(1)
+
+// Sampling period in milliseconds (implemented as  n+1 counter).
+// Programming a 0 imply a 1 millisecond sampling period.
+#define STAT_MON_COP_MON_CTRL_0_SAMPLE_PERIOD_SHIFT                     _MK_SHIFT_CONST(20)
+#define STAT_MON_COP_MON_CTRL_0_SAMPLE_PERIOD_FIELD                     (_MK_MASK_CONST(0xff) << STAT_MON_COP_MON_CTRL_0_SAMPLE_PERIOD_SHIFT)
+#define STAT_MON_COP_MON_CTRL_0_SAMPLE_PERIOD_RANGE                     27:20
+#define STAT_MON_COP_MON_CTRL_0_SAMPLE_PERIOD_WOFFSET                   0x0
+#define STAT_MON_COP_MON_CTRL_0_SAMPLE_PERIOD_DEFAULT                   _MK_MASK_CONST(0x0)
+#define STAT_MON_COP_MON_CTRL_0_SAMPLE_PERIOD_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define STAT_MON_COP_MON_CTRL_0_SAMPLE_PERIOD_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define STAT_MON_COP_MON_CTRL_0_SAMPLE_PERIOD_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Reserved
+#define STAT_MON_COP_MON_CTRL_0_N_A_SHIFT                       _MK_SHIFT_CONST(4)
+#define STAT_MON_COP_MON_CTRL_0_N_A_FIELD                       (_MK_MASK_CONST(0xffff) << STAT_MON_COP_MON_CTRL_0_N_A_SHIFT)
+#define STAT_MON_COP_MON_CTRL_0_N_A_RANGE                       19:4
+#define STAT_MON_COP_MON_CTRL_0_N_A_WOFFSET                     0x0
+#define STAT_MON_COP_MON_CTRL_0_N_A_DEFAULT                     _MK_MASK_CONST(0x0)
+#define STAT_MON_COP_MON_CTRL_0_N_A_DEFAULT_MASK                        _MK_MASK_CONST(0xffff)
+#define STAT_MON_COP_MON_CTRL_0_N_A_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define STAT_MON_COP_MON_CTRL_0_N_A_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// 4b0000 = automatically detect COP idle  condition.
+// Idle is defined as the period when the halt bit to the 
+// processor is asserted in the flow controller.
+#define STAT_MON_COP_MON_CTRL_0_SAMPLE_COND_SHIFT                       _MK_SHIFT_CONST(0)
+#define STAT_MON_COP_MON_CTRL_0_SAMPLE_COND_FIELD                       (_MK_MASK_CONST(0xf) << STAT_MON_COP_MON_CTRL_0_SAMPLE_COND_SHIFT)
+#define STAT_MON_COP_MON_CTRL_0_SAMPLE_COND_RANGE                       3:0
+#define STAT_MON_COP_MON_CTRL_0_SAMPLE_COND_WOFFSET                     0x0
+#define STAT_MON_COP_MON_CTRL_0_SAMPLE_COND_DEFAULT                     _MK_MASK_CONST(0x0)
+#define STAT_MON_COP_MON_CTRL_0_SAMPLE_COND_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define STAT_MON_COP_MON_CTRL_0_SAMPLE_COND_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define STAT_MON_COP_MON_CTRL_0_SAMPLE_COND_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register STAT_MON_COP_MON_STATUS_0  
+#define STAT_MON_COP_MON_STATUS_0                       _MK_ADDR_CONST(0x124)
+#define STAT_MON_COP_MON_STATUS_0_WORD_COUNT                    0x1
+#define STAT_MON_COP_MON_STATUS_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define STAT_MON_COP_MON_STATUS_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
+#define STAT_MON_COP_MON_STATUS_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define STAT_MON_COP_MON_STATUS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define STAT_MON_COP_MON_STATUS_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define STAT_MON_COP_MON_STATUS_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+// Indicates the number of idle cycles.
+// A value of  FFFF:FFFF is an overflow condition.
+// If the counter hits this value, it does  not increment from here. 
+// This counter is always reset when the monitor is  enabled the next time.
+#define STAT_MON_COP_MON_STATUS_0_COUNT_SHIFT                   _MK_SHIFT_CONST(0)
+#define STAT_MON_COP_MON_STATUS_0_COUNT_FIELD                   (_MK_MASK_CONST(0xffffffff) << STAT_MON_COP_MON_STATUS_0_COUNT_SHIFT)
+#define STAT_MON_COP_MON_STATUS_0_COUNT_RANGE                   31:0
+#define STAT_MON_COP_MON_STATUS_0_COUNT_WOFFSET                 0x0
+#define STAT_MON_COP_MON_STATUS_0_COUNT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define STAT_MON_COP_MON_STATUS_0_COUNT_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
+#define STAT_MON_COP_MON_STATUS_0_COUNT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define STAT_MON_COP_MON_STATUS_0_COUNT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Reserved address 296 [0x128] 
+
+// Reserved address 300 [0x12c] 
+
+// Reserved address 304 [0x130] 
+
+// Reserved address 308 [0x134] 
+
+// Reserved address 312 [0x138] 
+
+// Reserved address 316 [0x13c] 
+
+// Reserved address 320 [0x140] 
+
+// Reserved address 324 [0x144] 
+
+// Reserved address 328 [0x148] 
+
+// Reserved address 332 [0x14c] 
+
+// Reserved address 336 [0x150] 
+
+// Reserved address 340 [0x154] 
+
+// Reserved address 344 [0x158] 
+
+// Reserved address 348 [0x15c] 
+
+// Register STAT_MON_CACHE2_MON_CTRL_0  
+#define STAT_MON_CACHE2_MON_CTRL_0                      _MK_ADDR_CONST(0x160)
+#define STAT_MON_CACHE2_MON_CTRL_0_WORD_COUNT                   0x1
+#define STAT_MON_CACHE2_MON_CTRL_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define STAT_MON_CACHE2_MON_CTRL_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define STAT_MON_CACHE2_MON_CTRL_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define STAT_MON_CACHE2_MON_CTRL_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define STAT_MON_CACHE2_MON_CTRL_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
+#define STAT_MON_CACHE2_MON_CTRL_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
+// Enable Monitor. Set by SW to enable sampling.  cache2 monitor is enabled.
+// Cleared in one of the following ways,
+// (a) When SW intends to stop the  monitor, it can do so by clearing this field, or
+// (b) when the sampling period  expires.
+#define STAT_MON_CACHE2_MON_CTRL_0_ENB_SHIFT                    _MK_SHIFT_CONST(31)
+#define STAT_MON_CACHE2_MON_CTRL_0_ENB_FIELD                    (_MK_MASK_CONST(0x1) << STAT_MON_CACHE2_MON_CTRL_0_ENB_SHIFT)
+#define STAT_MON_CACHE2_MON_CTRL_0_ENB_RANGE                    31:31
+#define STAT_MON_CACHE2_MON_CTRL_0_ENB_WOFFSET                  0x0
+#define STAT_MON_CACHE2_MON_CTRL_0_ENB_DEFAULT                  _MK_MASK_CONST(0x0)
+#define STAT_MON_CACHE2_MON_CTRL_0_ENB_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define STAT_MON_CACHE2_MON_CTRL_0_ENB_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define STAT_MON_CACHE2_MON_CTRL_0_ENB_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define STAT_MON_CACHE2_MON_CTRL_0_ENB_DISABLE                  _MK_ENUM_CONST(0)    // // cache2 monitor is disabled.     
+
+#define STAT_MON_CACHE2_MON_CTRL_0_ENB_ENABLE                   _MK_ENUM_CONST(1)
+
+// Enable interrupt when sampling period expires. interrupt is enabled.
+#define STAT_MON_CACHE2_MON_CTRL_0_INT_EN_SHIFT                 _MK_SHIFT_CONST(30)
+#define STAT_MON_CACHE2_MON_CTRL_0_INT_EN_FIELD                 (_MK_MASK_CONST(0x1) << STAT_MON_CACHE2_MON_CTRL_0_INT_EN_SHIFT)
+#define STAT_MON_CACHE2_MON_CTRL_0_INT_EN_RANGE                 30:30
+#define STAT_MON_CACHE2_MON_CTRL_0_INT_EN_WOFFSET                       0x0
+#define STAT_MON_CACHE2_MON_CTRL_0_INT_EN_DEFAULT                       _MK_MASK_CONST(0x0)
+#define STAT_MON_CACHE2_MON_CTRL_0_INT_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define STAT_MON_CACHE2_MON_CTRL_0_INT_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define STAT_MON_CACHE2_MON_CTRL_0_INT_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define STAT_MON_CACHE2_MON_CTRL_0_INT_EN_DISABLE                       _MK_ENUM_CONST(0)    // // interrupt is disabled.     
+
+#define STAT_MON_CACHE2_MON_CTRL_0_INT_EN_ENABLE                        _MK_ENUM_CONST(1)
+
+// Assert by HW when sampling period expires when  INT_EN is set. 1 = interrupt detected
+// SW writing a 1 clears this bit. Writing 0 is ignored.
+#define STAT_MON_CACHE2_MON_CTRL_0_INT_SHIFT                    _MK_SHIFT_CONST(29)
+#define STAT_MON_CACHE2_MON_CTRL_0_INT_FIELD                    (_MK_MASK_CONST(0x1) << STAT_MON_CACHE2_MON_CTRL_0_INT_SHIFT)
+#define STAT_MON_CACHE2_MON_CTRL_0_INT_RANGE                    29:29
+#define STAT_MON_CACHE2_MON_CTRL_0_INT_WOFFSET                  0x0
+#define STAT_MON_CACHE2_MON_CTRL_0_INT_DEFAULT                  _MK_MASK_CONST(0x0)
+#define STAT_MON_CACHE2_MON_CTRL_0_INT_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define STAT_MON_CACHE2_MON_CTRL_0_INT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define STAT_MON_CACHE2_MON_CTRL_0_INT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define STAT_MON_CACHE2_MON_CTRL_0_INT_NOINT                    _MK_ENUM_CONST(0)    // // 0 = interrupt not detected
+
+#define STAT_MON_CACHE2_MON_CTRL_0_INT_INT                      _MK_ENUM_CONST(1)
+
+// 0 = sample only for the period mentioned in  SAMPLE_PERIOD. sample mode is enabled.
+#define STAT_MON_CACHE2_MON_CTRL_0_SAMPLE_MODE_SHIFT                    _MK_SHIFT_CONST(28)
+#define STAT_MON_CACHE2_MON_CTRL_0_SAMPLE_MODE_FIELD                    (_MK_MASK_CONST(0x1) << STAT_MON_CACHE2_MON_CTRL_0_SAMPLE_MODE_SHIFT)
+#define STAT_MON_CACHE2_MON_CTRL_0_SAMPLE_MODE_RANGE                    28:28
+#define STAT_MON_CACHE2_MON_CTRL_0_SAMPLE_MODE_WOFFSET                  0x0
+#define STAT_MON_CACHE2_MON_CTRL_0_SAMPLE_MODE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define STAT_MON_CACHE2_MON_CTRL_0_SAMPLE_MODE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define STAT_MON_CACHE2_MON_CTRL_0_SAMPLE_MODE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define STAT_MON_CACHE2_MON_CTRL_0_SAMPLE_MODE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define STAT_MON_CACHE2_MON_CTRL_0_SAMPLE_MODE_DISABLE                  _MK_ENUM_CONST(0)    // // sample mode is disabled.     
+
+#define STAT_MON_CACHE2_MON_CTRL_0_SAMPLE_MODE_ENABLE                   _MK_ENUM_CONST(1)
+
+// Sampling period in milliseconds (implemented as  n+1 counter).
+// Programming a 0 imply a 1 millisecond sampling period.
+#define STAT_MON_CACHE2_MON_CTRL_0_SAMPLE_PERIOD_SHIFT                  _MK_SHIFT_CONST(20)
+#define STAT_MON_CACHE2_MON_CTRL_0_SAMPLE_PERIOD_FIELD                  (_MK_MASK_CONST(0xff) << STAT_MON_CACHE2_MON_CTRL_0_SAMPLE_PERIOD_SHIFT)
+#define STAT_MON_CACHE2_MON_CTRL_0_SAMPLE_PERIOD_RANGE                  27:20
+#define STAT_MON_CACHE2_MON_CTRL_0_SAMPLE_PERIOD_WOFFSET                        0x0
+#define STAT_MON_CACHE2_MON_CTRL_0_SAMPLE_PERIOD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define STAT_MON_CACHE2_MON_CTRL_0_SAMPLE_PERIOD_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
+#define STAT_MON_CACHE2_MON_CTRL_0_SAMPLE_PERIOD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define STAT_MON_CACHE2_MON_CTRL_0_SAMPLE_PERIOD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Reserved
+#define STAT_MON_CACHE2_MON_CTRL_0_N_A_SHIFT                    _MK_SHIFT_CONST(4)
+#define STAT_MON_CACHE2_MON_CTRL_0_N_A_FIELD                    (_MK_MASK_CONST(0xffff) << STAT_MON_CACHE2_MON_CTRL_0_N_A_SHIFT)
+#define STAT_MON_CACHE2_MON_CTRL_0_N_A_RANGE                    19:4
+#define STAT_MON_CACHE2_MON_CTRL_0_N_A_WOFFSET                  0x0
+#define STAT_MON_CACHE2_MON_CTRL_0_N_A_DEFAULT                  _MK_MASK_CONST(0x0)
+#define STAT_MON_CACHE2_MON_CTRL_0_N_A_DEFAULT_MASK                     _MK_MASK_CONST(0xffff)
+#define STAT_MON_CACHE2_MON_CTRL_0_N_A_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define STAT_MON_CACHE2_MON_CTRL_0_N_A_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// 4b0010 = calculate hit/miss for cacheable data  only.
+#define STAT_MON_CACHE2_MON_CTRL_0_SAMPLE_COND_SHIFT                    _MK_SHIFT_CONST(0)
+#define STAT_MON_CACHE2_MON_CTRL_0_SAMPLE_COND_FIELD                    (_MK_MASK_CONST(0xf) << STAT_MON_CACHE2_MON_CTRL_0_SAMPLE_COND_SHIFT)
+#define STAT_MON_CACHE2_MON_CTRL_0_SAMPLE_COND_RANGE                    3:0
+#define STAT_MON_CACHE2_MON_CTRL_0_SAMPLE_COND_WOFFSET                  0x0
+#define STAT_MON_CACHE2_MON_CTRL_0_SAMPLE_COND_DEFAULT                  _MK_MASK_CONST(0x0)
+#define STAT_MON_CACHE2_MON_CTRL_0_SAMPLE_COND_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
+#define STAT_MON_CACHE2_MON_CTRL_0_SAMPLE_COND_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define STAT_MON_CACHE2_MON_CTRL_0_SAMPLE_COND_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register STAT_MON_CACHE2_REQ_STATUS_0  
+#define STAT_MON_CACHE2_REQ_STATUS_0                    _MK_ADDR_CONST(0x164)
+#define STAT_MON_CACHE2_REQ_STATUS_0_WORD_COUNT                         0x1
+#define STAT_MON_CACHE2_REQ_STATUS_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define STAT_MON_CACHE2_REQ_STATUS_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
+#define STAT_MON_CACHE2_REQ_STATUS_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define STAT_MON_CACHE2_REQ_STATUS_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define STAT_MON_CACHE2_REQ_STATUS_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define STAT_MON_CACHE2_REQ_STATUS_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
+// Number of cacheable requests from COP during the  sampling period.
+#define STAT_MON_CACHE2_REQ_STATUS_0_COUNT_SHIFT                        _MK_SHIFT_CONST(0)
+#define STAT_MON_CACHE2_REQ_STATUS_0_COUNT_FIELD                        (_MK_MASK_CONST(0xffffffff) << STAT_MON_CACHE2_REQ_STATUS_0_COUNT_SHIFT)
+#define STAT_MON_CACHE2_REQ_STATUS_0_COUNT_RANGE                        31:0
+#define STAT_MON_CACHE2_REQ_STATUS_0_COUNT_WOFFSET                      0x0
+#define STAT_MON_CACHE2_REQ_STATUS_0_COUNT_DEFAULT                      _MK_MASK_CONST(0x0)
+#define STAT_MON_CACHE2_REQ_STATUS_0_COUNT_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
+#define STAT_MON_CACHE2_REQ_STATUS_0_COUNT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define STAT_MON_CACHE2_REQ_STATUS_0_COUNT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register STAT_MON_CACHE2_HIT_STATUS_0  
+#define STAT_MON_CACHE2_HIT_STATUS_0                    _MK_ADDR_CONST(0x168)
+#define STAT_MON_CACHE2_HIT_STATUS_0_WORD_COUNT                         0x1
+#define STAT_MON_CACHE2_HIT_STATUS_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define STAT_MON_CACHE2_HIT_STATUS_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
+#define STAT_MON_CACHE2_HIT_STATUS_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define STAT_MON_CACHE2_HIT_STATUS_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define STAT_MON_CACHE2_HIT_STATUS_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define STAT_MON_CACHE2_HIT_STATUS_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
+// Number of cacheable requests that were hit during  the sampling period.
+#define STAT_MON_CACHE2_HIT_STATUS_0_COUNT_SHIFT                        _MK_SHIFT_CONST(0)
+#define STAT_MON_CACHE2_HIT_STATUS_0_COUNT_FIELD                        (_MK_MASK_CONST(0xffffffff) << STAT_MON_CACHE2_HIT_STATUS_0_COUNT_SHIFT)
+#define STAT_MON_CACHE2_HIT_STATUS_0_COUNT_RANGE                        31:0
+#define STAT_MON_CACHE2_HIT_STATUS_0_COUNT_WOFFSET                      0x0
+#define STAT_MON_CACHE2_HIT_STATUS_0_COUNT_DEFAULT                      _MK_MASK_CONST(0x0)
+#define STAT_MON_CACHE2_HIT_STATUS_0_COUNT_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
+#define STAT_MON_CACHE2_HIT_STATUS_0_COUNT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define STAT_MON_CACHE2_HIT_STATUS_0_COUNT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Reserved address 364 [0x16c] 
+
+// Reserved address 368 [0x170] 
+
+// Reserved address 372 [0x174] 
+
+// Reserved address 376 [0x178] 
+
+// Reserved address 380 [0x17c] 
+
+// Register STAT_MON_AHB_MON_CTRL_0  
+#define STAT_MON_AHB_MON_CTRL_0                 _MK_ADDR_CONST(0x180)
+#define STAT_MON_AHB_MON_CTRL_0_WORD_COUNT                      0x1
+#define STAT_MON_AHB_MON_CTRL_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define STAT_MON_AHB_MON_CTRL_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define STAT_MON_AHB_MON_CTRL_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define STAT_MON_AHB_MON_CTRL_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define STAT_MON_AHB_MON_CTRL_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define STAT_MON_AHB_MON_CTRL_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Enable Monitor. Set by SW to enable sampling.  Cleared when the sampling period expires. AHB monitor is enabled.
+#define STAT_MON_AHB_MON_CTRL_0_ENB_SHIFT                       _MK_SHIFT_CONST(31)
+#define STAT_MON_AHB_MON_CTRL_0_ENB_FIELD                       (_MK_MASK_CONST(0x1) << STAT_MON_AHB_MON_CTRL_0_ENB_SHIFT)
+#define STAT_MON_AHB_MON_CTRL_0_ENB_RANGE                       31:31
+#define STAT_MON_AHB_MON_CTRL_0_ENB_WOFFSET                     0x0
+#define STAT_MON_AHB_MON_CTRL_0_ENB_DEFAULT                     _MK_MASK_CONST(0x0)
+#define STAT_MON_AHB_MON_CTRL_0_ENB_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define STAT_MON_AHB_MON_CTRL_0_ENB_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define STAT_MON_AHB_MON_CTRL_0_ENB_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define STAT_MON_AHB_MON_CTRL_0_ENB_DISABLE                     _MK_ENUM_CONST(0)    // // AHB monitor is disabled.     
+
+#define STAT_MON_AHB_MON_CTRL_0_ENB_ENABLE                      _MK_ENUM_CONST(1)
+
+// Enable interrupt. interrupt is enabled.
+#define STAT_MON_AHB_MON_CTRL_0_INT_EN_SHIFT                    _MK_SHIFT_CONST(30)
+#define STAT_MON_AHB_MON_CTRL_0_INT_EN_FIELD                    (_MK_MASK_CONST(0x1) << STAT_MON_AHB_MON_CTRL_0_INT_EN_SHIFT)
+#define STAT_MON_AHB_MON_CTRL_0_INT_EN_RANGE                    30:30
+#define STAT_MON_AHB_MON_CTRL_0_INT_EN_WOFFSET                  0x0
+#define STAT_MON_AHB_MON_CTRL_0_INT_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define STAT_MON_AHB_MON_CTRL_0_INT_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define STAT_MON_AHB_MON_CTRL_0_INT_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define STAT_MON_AHB_MON_CTRL_0_INT_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define STAT_MON_AHB_MON_CTRL_0_INT_EN_DISABLE                  _MK_ENUM_CONST(0)    // // interrupt is disabled.     
+
+#define STAT_MON_AHB_MON_CTRL_0_INT_EN_ENABLE                   _MK_ENUM_CONST(1)
+
+// Assert by HW when sampling period expires when  INT_EN is set. 1 = interrupt detected
+// SW writing a 1 clears this bit. Writing 0 is ignored.
+#define STAT_MON_AHB_MON_CTRL_0_INT_SHIFT                       _MK_SHIFT_CONST(29)
+#define STAT_MON_AHB_MON_CTRL_0_INT_FIELD                       (_MK_MASK_CONST(0x1) << STAT_MON_AHB_MON_CTRL_0_INT_SHIFT)
+#define STAT_MON_AHB_MON_CTRL_0_INT_RANGE                       29:29
+#define STAT_MON_AHB_MON_CTRL_0_INT_WOFFSET                     0x0
+#define STAT_MON_AHB_MON_CTRL_0_INT_DEFAULT                     _MK_MASK_CONST(0x0)
+#define STAT_MON_AHB_MON_CTRL_0_INT_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define STAT_MON_AHB_MON_CTRL_0_INT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define STAT_MON_AHB_MON_CTRL_0_INT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define STAT_MON_AHB_MON_CTRL_0_INT_NOINT                       _MK_ENUM_CONST(0)    // // 0 = interrupt not detected
+
+#define STAT_MON_AHB_MON_CTRL_0_INT_INT                 _MK_ENUM_CONST(1)
+
+// 0 = sample only for the period mentioned in  SAMPLE_PERIOD. sample mode is enabled.
+#define STAT_MON_AHB_MON_CTRL_0_SAMPLE_MODE_SHIFT                       _MK_SHIFT_CONST(28)
+#define STAT_MON_AHB_MON_CTRL_0_SAMPLE_MODE_FIELD                       (_MK_MASK_CONST(0x1) << STAT_MON_AHB_MON_CTRL_0_SAMPLE_MODE_SHIFT)
+#define STAT_MON_AHB_MON_CTRL_0_SAMPLE_MODE_RANGE                       28:28
+#define STAT_MON_AHB_MON_CTRL_0_SAMPLE_MODE_WOFFSET                     0x0
+#define STAT_MON_AHB_MON_CTRL_0_SAMPLE_MODE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define STAT_MON_AHB_MON_CTRL_0_SAMPLE_MODE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define STAT_MON_AHB_MON_CTRL_0_SAMPLE_MODE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define STAT_MON_AHB_MON_CTRL_0_SAMPLE_MODE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define STAT_MON_AHB_MON_CTRL_0_SAMPLE_MODE_DISABLE                     _MK_ENUM_CONST(0)    // // sample mode is disabled.     
+
+#define STAT_MON_AHB_MON_CTRL_0_SAMPLE_MODE_ENABLE                      _MK_ENUM_CONST(1)
+
+// Sampling period in milliseconds (implemented as  n+1 counter).
+// Programming a 0 imply a 1 millisecond sampling period.
+#define STAT_MON_AHB_MON_CTRL_0_SAMPLE_PERIOD_SHIFT                     _MK_SHIFT_CONST(20)
+#define STAT_MON_AHB_MON_CTRL_0_SAMPLE_PERIOD_FIELD                     (_MK_MASK_CONST(0xff) << STAT_MON_AHB_MON_CTRL_0_SAMPLE_PERIOD_SHIFT)
+#define STAT_MON_AHB_MON_CTRL_0_SAMPLE_PERIOD_RANGE                     27:20
+#define STAT_MON_AHB_MON_CTRL_0_SAMPLE_PERIOD_WOFFSET                   0x0
+#define STAT_MON_AHB_MON_CTRL_0_SAMPLE_PERIOD_DEFAULT                   _MK_MASK_CONST(0x0)
+#define STAT_MON_AHB_MON_CTRL_0_SAMPLE_PERIOD_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define STAT_MON_AHB_MON_CTRL_0_SAMPLE_PERIOD_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define STAT_MON_AHB_MON_CTRL_0_SAMPLE_PERIOD_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Enable periodic mode. periodic mode is enabled.
+#define STAT_MON_AHB_MON_CTRL_0_ENB_PERIODIC_SHIFT                      _MK_SHIFT_CONST(19)
+#define STAT_MON_AHB_MON_CTRL_0_ENB_PERIODIC_FIELD                      (_MK_MASK_CONST(0x1) << STAT_MON_AHB_MON_CTRL_0_ENB_PERIODIC_SHIFT)
+#define STAT_MON_AHB_MON_CTRL_0_ENB_PERIODIC_RANGE                      19:19
+#define STAT_MON_AHB_MON_CTRL_0_ENB_PERIODIC_WOFFSET                    0x0
+#define STAT_MON_AHB_MON_CTRL_0_ENB_PERIODIC_DEFAULT                    _MK_MASK_CONST(0x0)
+#define STAT_MON_AHB_MON_CTRL_0_ENB_PERIODIC_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define STAT_MON_AHB_MON_CTRL_0_ENB_PERIODIC_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define STAT_MON_AHB_MON_CTRL_0_ENB_PERIODIC_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define STAT_MON_AHB_MON_CTRL_0_ENB_PERIODIC_DISABLE                    _MK_ENUM_CONST(0)    // // periodic mode is disabled.     
+
+#define STAT_MON_AHB_MON_CTRL_0_ENB_PERIODIC_ENABLE                     _MK_ENUM_CONST(1)
+
+// 
+#define STAT_MON_AHB_MON_CTRL_0_N_A1_SHIFT                      _MK_SHIFT_CONST(16)
+#define STAT_MON_AHB_MON_CTRL_0_N_A1_FIELD                      (_MK_MASK_CONST(0x7) << STAT_MON_AHB_MON_CTRL_0_N_A1_SHIFT)
+#define STAT_MON_AHB_MON_CTRL_0_N_A1_RANGE                      18:16
+#define STAT_MON_AHB_MON_CTRL_0_N_A1_WOFFSET                    0x0
+#define STAT_MON_AHB_MON_CTRL_0_N_A1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define STAT_MON_AHB_MON_CTRL_0_N_A1_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define STAT_MON_AHB_MON_CTRL_0_N_A1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define STAT_MON_AHB_MON_CTRL_0_N_A1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Interrupt always at end of sample period. interrupt is enabled.
+#define STAT_MON_AHB_MON_CTRL_0_INT_AT_END_SHIFT                        _MK_SHIFT_CONST(15)
+#define STAT_MON_AHB_MON_CTRL_0_INT_AT_END_FIELD                        (_MK_MASK_CONST(0x1) << STAT_MON_AHB_MON_CTRL_0_INT_AT_END_SHIFT)
+#define STAT_MON_AHB_MON_CTRL_0_INT_AT_END_RANGE                        15:15
+#define STAT_MON_AHB_MON_CTRL_0_INT_AT_END_WOFFSET                      0x0
+#define STAT_MON_AHB_MON_CTRL_0_INT_AT_END_DEFAULT                      _MK_MASK_CONST(0x0)
+#define STAT_MON_AHB_MON_CTRL_0_INT_AT_END_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define STAT_MON_AHB_MON_CTRL_0_INT_AT_END_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define STAT_MON_AHB_MON_CTRL_0_INT_AT_END_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define STAT_MON_AHB_MON_CTRL_0_INT_AT_END_DISABLE                      _MK_ENUM_CONST(0)    // // interrupt is disabled.     
+
+#define STAT_MON_AHB_MON_CTRL_0_INT_AT_END_ENABLE                       _MK_ENUM_CONST(1)
+
+// Interrupt only if count is below the lower  watermark at the end of sample period. interrupt is enabled.
+#define STAT_MON_AHB_MON_CTRL_0_INT_IF_BELOW_WMARK_SHIFT                        _MK_SHIFT_CONST(14)
+#define STAT_MON_AHB_MON_CTRL_0_INT_IF_BELOW_WMARK_FIELD                        (_MK_MASK_CONST(0x1) << STAT_MON_AHB_MON_CTRL_0_INT_IF_BELOW_WMARK_SHIFT)
+#define STAT_MON_AHB_MON_CTRL_0_INT_IF_BELOW_WMARK_RANGE                        14:14
+#define STAT_MON_AHB_MON_CTRL_0_INT_IF_BELOW_WMARK_WOFFSET                      0x0
+#define STAT_MON_AHB_MON_CTRL_0_INT_IF_BELOW_WMARK_DEFAULT                      _MK_MASK_CONST(0x0)
+#define STAT_MON_AHB_MON_CTRL_0_INT_IF_BELOW_WMARK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define STAT_MON_AHB_MON_CTRL_0_INT_IF_BELOW_WMARK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define STAT_MON_AHB_MON_CTRL_0_INT_IF_BELOW_WMARK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define STAT_MON_AHB_MON_CTRL_0_INT_IF_BELOW_WMARK_DISABLE                      _MK_ENUM_CONST(0)    // // interrupt is disabled.     
+
+#define STAT_MON_AHB_MON_CTRL_0_INT_IF_BELOW_WMARK_ENABLE                       _MK_ENUM_CONST(1)
+
+// Interrupt only if count is above the upper  watermark at the end of sample period. interrupt is enabled.
+#define STAT_MON_AHB_MON_CTRL_0_INT_IF_ABOVE_WMARK_SHIFT                        _MK_SHIFT_CONST(13)
+#define STAT_MON_AHB_MON_CTRL_0_INT_IF_ABOVE_WMARK_FIELD                        (_MK_MASK_CONST(0x1) << STAT_MON_AHB_MON_CTRL_0_INT_IF_ABOVE_WMARK_SHIFT)
+#define STAT_MON_AHB_MON_CTRL_0_INT_IF_ABOVE_WMARK_RANGE                        13:13
+#define STAT_MON_AHB_MON_CTRL_0_INT_IF_ABOVE_WMARK_WOFFSET                      0x0
+#define STAT_MON_AHB_MON_CTRL_0_INT_IF_ABOVE_WMARK_DEFAULT                      _MK_MASK_CONST(0x0)
+#define STAT_MON_AHB_MON_CTRL_0_INT_IF_ABOVE_WMARK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define STAT_MON_AHB_MON_CTRL_0_INT_IF_ABOVE_WMARK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define STAT_MON_AHB_MON_CTRL_0_INT_IF_ABOVE_WMARK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define STAT_MON_AHB_MON_CTRL_0_INT_IF_ABOVE_WMARK_DISABLE                      _MK_ENUM_CONST(0)    // // interrupt is disabled.     
+
+#define STAT_MON_AHB_MON_CTRL_0_INT_IF_ABOVE_WMARK_ENABLE                       _MK_ENUM_CONST(1)
+
+// Interrupt when count rolls over. interrupt is enabled.
+#define STAT_MON_AHB_MON_CTRL_0_INT_WHEN_CNT_ROVER_SHIFT                        _MK_SHIFT_CONST(12)
+#define STAT_MON_AHB_MON_CTRL_0_INT_WHEN_CNT_ROVER_FIELD                        (_MK_MASK_CONST(0x1) << STAT_MON_AHB_MON_CTRL_0_INT_WHEN_CNT_ROVER_SHIFT)
+#define STAT_MON_AHB_MON_CTRL_0_INT_WHEN_CNT_ROVER_RANGE                        12:12
+#define STAT_MON_AHB_MON_CTRL_0_INT_WHEN_CNT_ROVER_WOFFSET                      0x0
+#define STAT_MON_AHB_MON_CTRL_0_INT_WHEN_CNT_ROVER_DEFAULT                      _MK_MASK_CONST(0x0)
+#define STAT_MON_AHB_MON_CTRL_0_INT_WHEN_CNT_ROVER_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define STAT_MON_AHB_MON_CTRL_0_INT_WHEN_CNT_ROVER_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define STAT_MON_AHB_MON_CTRL_0_INT_WHEN_CNT_ROVER_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define STAT_MON_AHB_MON_CTRL_0_INT_WHEN_CNT_ROVER_DISABLE                      _MK_ENUM_CONST(0)    // // interrupt is disabled.     
+
+#define STAT_MON_AHB_MON_CTRL_0_INT_WHEN_CNT_ROVER_ENABLE                       _MK_ENUM_CONST(1)
+
+// Reserved
+#define STAT_MON_AHB_MON_CTRL_0_N_A0_SHIFT                      _MK_SHIFT_CONST(9)
+#define STAT_MON_AHB_MON_CTRL_0_N_A0_FIELD                      (_MK_MASK_CONST(0x7) << STAT_MON_AHB_MON_CTRL_0_N_A0_SHIFT)
+#define STAT_MON_AHB_MON_CTRL_0_N_A0_RANGE                      11:9
+#define STAT_MON_AHB_MON_CTRL_0_N_A0_WOFFSET                    0x0
+#define STAT_MON_AHB_MON_CTRL_0_N_A0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define STAT_MON_AHB_MON_CTRL_0_N_A0_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define STAT_MON_AHB_MON_CTRL_0_N_A0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define STAT_MON_AHB_MON_CTRL_0_N_A0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Indicate which AHB master to monitor. ALL 1s  means any master.
+#define STAT_MON_AHB_MON_CTRL_0_MST_NUMBER_SHIFT                        _MK_SHIFT_CONST(4)
+#define STAT_MON_AHB_MON_CTRL_0_MST_NUMBER_FIELD                        (_MK_MASK_CONST(0x1f) << STAT_MON_AHB_MON_CTRL_0_MST_NUMBER_SHIFT)
+#define STAT_MON_AHB_MON_CTRL_0_MST_NUMBER_RANGE                        8:4
+#define STAT_MON_AHB_MON_CTRL_0_MST_NUMBER_WOFFSET                      0x0
+#define STAT_MON_AHB_MON_CTRL_0_MST_NUMBER_DEFAULT                      _MK_MASK_CONST(0x0)
+#define STAT_MON_AHB_MON_CTRL_0_MST_NUMBER_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define STAT_MON_AHB_MON_CTRL_0_MST_NUMBER_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define STAT_MON_AHB_MON_CTRL_0_MST_NUMBER_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// 4b0010 = request/grant latency (one master only). 
+#define STAT_MON_AHB_MON_CTRL_0_SAMPLE_COND_SHIFT                       _MK_SHIFT_CONST(0)
+#define STAT_MON_AHB_MON_CTRL_0_SAMPLE_COND_FIELD                       (_MK_MASK_CONST(0xf) << STAT_MON_AHB_MON_CTRL_0_SAMPLE_COND_SHIFT)
+#define STAT_MON_AHB_MON_CTRL_0_SAMPLE_COND_RANGE                       3:0
+#define STAT_MON_AHB_MON_CTRL_0_SAMPLE_COND_WOFFSET                     0x0
+#define STAT_MON_AHB_MON_CTRL_0_SAMPLE_COND_DEFAULT                     _MK_MASK_CONST(0x0)
+#define STAT_MON_AHB_MON_CTRL_0_SAMPLE_COND_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define STAT_MON_AHB_MON_CTRL_0_SAMPLE_COND_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define STAT_MON_AHB_MON_CTRL_0_SAMPLE_COND_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register STAT_MON_AHB_MON_STATUS_0  
+#define STAT_MON_AHB_MON_STATUS_0                       _MK_ADDR_CONST(0x184)
+#define STAT_MON_AHB_MON_STATUS_0_WORD_COUNT                    0x1
+#define STAT_MON_AHB_MON_STATUS_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define STAT_MON_AHB_MON_STATUS_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
+#define STAT_MON_AHB_MON_STATUS_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define STAT_MON_AHB_MON_STATUS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define STAT_MON_AHB_MON_STATUS_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define STAT_MON_AHB_MON_STATUS_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+// Count.
+#define STAT_MON_AHB_MON_STATUS_0_COUNT_SHIFT                   _MK_SHIFT_CONST(0)
+#define STAT_MON_AHB_MON_STATUS_0_COUNT_FIELD                   (_MK_MASK_CONST(0xffffffff) << STAT_MON_AHB_MON_STATUS_0_COUNT_SHIFT)
+#define STAT_MON_AHB_MON_STATUS_0_COUNT_RANGE                   31:0
+#define STAT_MON_AHB_MON_STATUS_0_COUNT_WOFFSET                 0x0
+#define STAT_MON_AHB_MON_STATUS_0_COUNT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define STAT_MON_AHB_MON_STATUS_0_COUNT_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
+#define STAT_MON_AHB_MON_STATUS_0_COUNT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define STAT_MON_AHB_MON_STATUS_0_COUNT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register STAT_MON_AHB_LOWER_WMARK_0  
+#define STAT_MON_AHB_LOWER_WMARK_0                      _MK_ADDR_CONST(0x188)
+#define STAT_MON_AHB_LOWER_WMARK_0_WORD_COUNT                   0x1
+#define STAT_MON_AHB_LOWER_WMARK_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define STAT_MON_AHB_LOWER_WMARK_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define STAT_MON_AHB_LOWER_WMARK_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define STAT_MON_AHB_LOWER_WMARK_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define STAT_MON_AHB_LOWER_WMARK_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
+#define STAT_MON_AHB_LOWER_WMARK_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
+// Lower watermark count value.
+#define STAT_MON_AHB_LOWER_WMARK_0_LOWER_WMARK_CNT_SHIFT                        _MK_SHIFT_CONST(0)
+#define STAT_MON_AHB_LOWER_WMARK_0_LOWER_WMARK_CNT_FIELD                        (_MK_MASK_CONST(0xffffffff) << STAT_MON_AHB_LOWER_WMARK_0_LOWER_WMARK_CNT_SHIFT)
+#define STAT_MON_AHB_LOWER_WMARK_0_LOWER_WMARK_CNT_RANGE                        31:0
+#define STAT_MON_AHB_LOWER_WMARK_0_LOWER_WMARK_CNT_WOFFSET                      0x0
+#define STAT_MON_AHB_LOWER_WMARK_0_LOWER_WMARK_CNT_DEFAULT                      _MK_MASK_CONST(0x0)
+#define STAT_MON_AHB_LOWER_WMARK_0_LOWER_WMARK_CNT_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
+#define STAT_MON_AHB_LOWER_WMARK_0_LOWER_WMARK_CNT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define STAT_MON_AHB_LOWER_WMARK_0_LOWER_WMARK_CNT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register STAT_MON_AHB_UPPER_WMARK_0  
+#define STAT_MON_AHB_UPPER_WMARK_0                      _MK_ADDR_CONST(0x18c)
+#define STAT_MON_AHB_UPPER_WMARK_0_WORD_COUNT                   0x1
+#define STAT_MON_AHB_UPPER_WMARK_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define STAT_MON_AHB_UPPER_WMARK_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define STAT_MON_AHB_UPPER_WMARK_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define STAT_MON_AHB_UPPER_WMARK_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define STAT_MON_AHB_UPPER_WMARK_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
+#define STAT_MON_AHB_UPPER_WMARK_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
+// Upper watermark count value.
+#define STAT_MON_AHB_UPPER_WMARK_0_UPPER_WMARK_CNT_SHIFT                        _MK_SHIFT_CONST(0)
+#define STAT_MON_AHB_UPPER_WMARK_0_UPPER_WMARK_CNT_FIELD                        (_MK_MASK_CONST(0xffffffff) << STAT_MON_AHB_UPPER_WMARK_0_UPPER_WMARK_CNT_SHIFT)
+#define STAT_MON_AHB_UPPER_WMARK_0_UPPER_WMARK_CNT_RANGE                        31:0
+#define STAT_MON_AHB_UPPER_WMARK_0_UPPER_WMARK_CNT_WOFFSET                      0x0
+#define STAT_MON_AHB_UPPER_WMARK_0_UPPER_WMARK_CNT_DEFAULT                      _MK_MASK_CONST(0x0)
+#define STAT_MON_AHB_UPPER_WMARK_0_UPPER_WMARK_CNT_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
+#define STAT_MON_AHB_UPPER_WMARK_0_UPPER_WMARK_CNT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define STAT_MON_AHB_UPPER_WMARK_0_UPPER_WMARK_CNT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Reserved address 400 [0x190] 
+
+// Reserved address 404 [0x194] 
+
+// Reserved address 408 [0x198] 
+
+// Reserved address 412 [0x19c] 
+
+// Register STAT_MON_APB_MON_CTRL_0  
+#define STAT_MON_APB_MON_CTRL_0                 _MK_ADDR_CONST(0x1a0)
+#define STAT_MON_APB_MON_CTRL_0_WORD_COUNT                      0x1
+#define STAT_MON_APB_MON_CTRL_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define STAT_MON_APB_MON_CTRL_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define STAT_MON_APB_MON_CTRL_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define STAT_MON_APB_MON_CTRL_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define STAT_MON_APB_MON_CTRL_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define STAT_MON_APB_MON_CTRL_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Enable Monitor. Set by SW to enable sampling.  Cleared when the sampling period expires. APB monitor is enabled.
+#define STAT_MON_APB_MON_CTRL_0_ENB_SHIFT                       _MK_SHIFT_CONST(31)
+#define STAT_MON_APB_MON_CTRL_0_ENB_FIELD                       (_MK_MASK_CONST(0x1) << STAT_MON_APB_MON_CTRL_0_ENB_SHIFT)
+#define STAT_MON_APB_MON_CTRL_0_ENB_RANGE                       31:31
+#define STAT_MON_APB_MON_CTRL_0_ENB_WOFFSET                     0x0
+#define STAT_MON_APB_MON_CTRL_0_ENB_DEFAULT                     _MK_MASK_CONST(0x0)
+#define STAT_MON_APB_MON_CTRL_0_ENB_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define STAT_MON_APB_MON_CTRL_0_ENB_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define STAT_MON_APB_MON_CTRL_0_ENB_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define STAT_MON_APB_MON_CTRL_0_ENB_DISABLE                     _MK_ENUM_CONST(0)    // // APB monitor is disabled.     
+
+#define STAT_MON_APB_MON_CTRL_0_ENB_ENABLE                      _MK_ENUM_CONST(1)
+
+// Enable interrupt. interrupt is enabled.
+#define STAT_MON_APB_MON_CTRL_0_INT_EN_SHIFT                    _MK_SHIFT_CONST(30)
+#define STAT_MON_APB_MON_CTRL_0_INT_EN_FIELD                    (_MK_MASK_CONST(0x1) << STAT_MON_APB_MON_CTRL_0_INT_EN_SHIFT)
+#define STAT_MON_APB_MON_CTRL_0_INT_EN_RANGE                    30:30
+#define STAT_MON_APB_MON_CTRL_0_INT_EN_WOFFSET                  0x0
+#define STAT_MON_APB_MON_CTRL_0_INT_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define STAT_MON_APB_MON_CTRL_0_INT_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define STAT_MON_APB_MON_CTRL_0_INT_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define STAT_MON_APB_MON_CTRL_0_INT_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define STAT_MON_APB_MON_CTRL_0_INT_EN_DISABLE                  _MK_ENUM_CONST(0)    // // interrupt is disabled.     
+
+#define STAT_MON_APB_MON_CTRL_0_INT_EN_ENABLE                   _MK_ENUM_CONST(1)
+
+// Assert by HW when sampling period expires when  INT_EN is set. 1 = interrupt detected
+// SW writing a 1 clears this bit. Writing 0 is ignored.
+#define STAT_MON_APB_MON_CTRL_0_INT_SHIFT                       _MK_SHIFT_CONST(29)
+#define STAT_MON_APB_MON_CTRL_0_INT_FIELD                       (_MK_MASK_CONST(0x1) << STAT_MON_APB_MON_CTRL_0_INT_SHIFT)
+#define STAT_MON_APB_MON_CTRL_0_INT_RANGE                       29:29
+#define STAT_MON_APB_MON_CTRL_0_INT_WOFFSET                     0x0
+#define STAT_MON_APB_MON_CTRL_0_INT_DEFAULT                     _MK_MASK_CONST(0x0)
+#define STAT_MON_APB_MON_CTRL_0_INT_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define STAT_MON_APB_MON_CTRL_0_INT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define STAT_MON_APB_MON_CTRL_0_INT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define STAT_MON_APB_MON_CTRL_0_INT_NOINT                       _MK_ENUM_CONST(0)    // // 0 = interrupt not detected
+
+#define STAT_MON_APB_MON_CTRL_0_INT_INT                 _MK_ENUM_CONST(1)
+
+// 0 = sample only for the period mentioned in  SAMPLE_PERIOD. sample mode is enabled.
+#define STAT_MON_APB_MON_CTRL_0_SAMPLE_MODE_SHIFT                       _MK_SHIFT_CONST(28)
+#define STAT_MON_APB_MON_CTRL_0_SAMPLE_MODE_FIELD                       (_MK_MASK_CONST(0x1) << STAT_MON_APB_MON_CTRL_0_SAMPLE_MODE_SHIFT)
+#define STAT_MON_APB_MON_CTRL_0_SAMPLE_MODE_RANGE                       28:28
+#define STAT_MON_APB_MON_CTRL_0_SAMPLE_MODE_WOFFSET                     0x0
+#define STAT_MON_APB_MON_CTRL_0_SAMPLE_MODE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define STAT_MON_APB_MON_CTRL_0_SAMPLE_MODE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define STAT_MON_APB_MON_CTRL_0_SAMPLE_MODE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define STAT_MON_APB_MON_CTRL_0_SAMPLE_MODE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define STAT_MON_APB_MON_CTRL_0_SAMPLE_MODE_DISABLE                     _MK_ENUM_CONST(0)    // // sample mode is disabled.     
+
+#define STAT_MON_APB_MON_CTRL_0_SAMPLE_MODE_ENABLE                      _MK_ENUM_CONST(1)
+
+// Sampling period in milliseconds (implemented as  n+1 counter).
+// Programming a 0 imply a 1 millisecond sampling period.
+#define STAT_MON_APB_MON_CTRL_0_SAMPLE_PERIOD_SHIFT                     _MK_SHIFT_CONST(20)
+#define STAT_MON_APB_MON_CTRL_0_SAMPLE_PERIOD_FIELD                     (_MK_MASK_CONST(0xff) << STAT_MON_APB_MON_CTRL_0_SAMPLE_PERIOD_SHIFT)
+#define STAT_MON_APB_MON_CTRL_0_SAMPLE_PERIOD_RANGE                     27:20
+#define STAT_MON_APB_MON_CTRL_0_SAMPLE_PERIOD_WOFFSET                   0x0
+#define STAT_MON_APB_MON_CTRL_0_SAMPLE_PERIOD_DEFAULT                   _MK_MASK_CONST(0x0)
+#define STAT_MON_APB_MON_CTRL_0_SAMPLE_PERIOD_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define STAT_MON_APB_MON_CTRL_0_SAMPLE_PERIOD_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define STAT_MON_APB_MON_CTRL_0_SAMPLE_PERIOD_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Enable periodic mode. periodic mode is enabled.
+#define STAT_MON_APB_MON_CTRL_0_ENB_PERIODIC_SHIFT                      _MK_SHIFT_CONST(19)
+#define STAT_MON_APB_MON_CTRL_0_ENB_PERIODIC_FIELD                      (_MK_MASK_CONST(0x1) << STAT_MON_APB_MON_CTRL_0_ENB_PERIODIC_SHIFT)
+#define STAT_MON_APB_MON_CTRL_0_ENB_PERIODIC_RANGE                      19:19
+#define STAT_MON_APB_MON_CTRL_0_ENB_PERIODIC_WOFFSET                    0x0
+#define STAT_MON_APB_MON_CTRL_0_ENB_PERIODIC_DEFAULT                    _MK_MASK_CONST(0x0)
+#define STAT_MON_APB_MON_CTRL_0_ENB_PERIODIC_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define STAT_MON_APB_MON_CTRL_0_ENB_PERIODIC_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define STAT_MON_APB_MON_CTRL_0_ENB_PERIODIC_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define STAT_MON_APB_MON_CTRL_0_ENB_PERIODIC_DISABLE                    _MK_ENUM_CONST(0)    // // periodic mode is disabled.     
+
+#define STAT_MON_APB_MON_CTRL_0_ENB_PERIODIC_ENABLE                     _MK_ENUM_CONST(1)
+
+// 
+#define STAT_MON_APB_MON_CTRL_0_N_A1_SHIFT                      _MK_SHIFT_CONST(16)
+#define STAT_MON_APB_MON_CTRL_0_N_A1_FIELD                      (_MK_MASK_CONST(0x7) << STAT_MON_APB_MON_CTRL_0_N_A1_SHIFT)
+#define STAT_MON_APB_MON_CTRL_0_N_A1_RANGE                      18:16
+#define STAT_MON_APB_MON_CTRL_0_N_A1_WOFFSET                    0x0
+#define STAT_MON_APB_MON_CTRL_0_N_A1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define STAT_MON_APB_MON_CTRL_0_N_A1_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define STAT_MON_APB_MON_CTRL_0_N_A1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define STAT_MON_APB_MON_CTRL_0_N_A1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Interrupt always at end of sample period. interrupt is enabled.
+#define STAT_MON_APB_MON_CTRL_0_INT_AT_END_SHIFT                        _MK_SHIFT_CONST(15)
+#define STAT_MON_APB_MON_CTRL_0_INT_AT_END_FIELD                        (_MK_MASK_CONST(0x1) << STAT_MON_APB_MON_CTRL_0_INT_AT_END_SHIFT)
+#define STAT_MON_APB_MON_CTRL_0_INT_AT_END_RANGE                        15:15
+#define STAT_MON_APB_MON_CTRL_0_INT_AT_END_WOFFSET                      0x0
+#define STAT_MON_APB_MON_CTRL_0_INT_AT_END_DEFAULT                      _MK_MASK_CONST(0x0)
+#define STAT_MON_APB_MON_CTRL_0_INT_AT_END_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define STAT_MON_APB_MON_CTRL_0_INT_AT_END_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define STAT_MON_APB_MON_CTRL_0_INT_AT_END_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define STAT_MON_APB_MON_CTRL_0_INT_AT_END_DISABLE                      _MK_ENUM_CONST(0)    // // interrupt is disabled.     
+
+#define STAT_MON_APB_MON_CTRL_0_INT_AT_END_ENABLE                       _MK_ENUM_CONST(1)
+
+// Interrupt only if count is below the lower  watermark at the end of sample period. interrupt is enabled.
+#define STAT_MON_APB_MON_CTRL_0_INT_IF_BELOW_WMARK_SHIFT                        _MK_SHIFT_CONST(14)
+#define STAT_MON_APB_MON_CTRL_0_INT_IF_BELOW_WMARK_FIELD                        (_MK_MASK_CONST(0x1) << STAT_MON_APB_MON_CTRL_0_INT_IF_BELOW_WMARK_SHIFT)
+#define STAT_MON_APB_MON_CTRL_0_INT_IF_BELOW_WMARK_RANGE                        14:14
+#define STAT_MON_APB_MON_CTRL_0_INT_IF_BELOW_WMARK_WOFFSET                      0x0
+#define STAT_MON_APB_MON_CTRL_0_INT_IF_BELOW_WMARK_DEFAULT                      _MK_MASK_CONST(0x0)
+#define STAT_MON_APB_MON_CTRL_0_INT_IF_BELOW_WMARK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define STAT_MON_APB_MON_CTRL_0_INT_IF_BELOW_WMARK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define STAT_MON_APB_MON_CTRL_0_INT_IF_BELOW_WMARK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define STAT_MON_APB_MON_CTRL_0_INT_IF_BELOW_WMARK_DISABLE                      _MK_ENUM_CONST(0)    // // interrupt is disabled.     
+
+#define STAT_MON_APB_MON_CTRL_0_INT_IF_BELOW_WMARK_ENABLE                       _MK_ENUM_CONST(1)
+
+// Interrupt only if count is above the upper  watermark at the end of sample period. interrupt is enabled.
+#define STAT_MON_APB_MON_CTRL_0_INT_IF_ABOVE_WMARK_SHIFT                        _MK_SHIFT_CONST(13)
+#define STAT_MON_APB_MON_CTRL_0_INT_IF_ABOVE_WMARK_FIELD                        (_MK_MASK_CONST(0x1) << STAT_MON_APB_MON_CTRL_0_INT_IF_ABOVE_WMARK_SHIFT)
+#define STAT_MON_APB_MON_CTRL_0_INT_IF_ABOVE_WMARK_RANGE                        13:13
+#define STAT_MON_APB_MON_CTRL_0_INT_IF_ABOVE_WMARK_WOFFSET                      0x0
+#define STAT_MON_APB_MON_CTRL_0_INT_IF_ABOVE_WMARK_DEFAULT                      _MK_MASK_CONST(0x0)
+#define STAT_MON_APB_MON_CTRL_0_INT_IF_ABOVE_WMARK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define STAT_MON_APB_MON_CTRL_0_INT_IF_ABOVE_WMARK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define STAT_MON_APB_MON_CTRL_0_INT_IF_ABOVE_WMARK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define STAT_MON_APB_MON_CTRL_0_INT_IF_ABOVE_WMARK_DISABLE                      _MK_ENUM_CONST(0)    // // interrupt is disabled.     
+
+#define STAT_MON_APB_MON_CTRL_0_INT_IF_ABOVE_WMARK_ENABLE                       _MK_ENUM_CONST(1)
+
+// Interrupt when count rolls over. interrupt is enabled.
+#define STAT_MON_APB_MON_CTRL_0_INT_WHEN_CNT_ROVER_SHIFT                        _MK_SHIFT_CONST(12)
+#define STAT_MON_APB_MON_CTRL_0_INT_WHEN_CNT_ROVER_FIELD                        (_MK_MASK_CONST(0x1) << STAT_MON_APB_MON_CTRL_0_INT_WHEN_CNT_ROVER_SHIFT)
+#define STAT_MON_APB_MON_CTRL_0_INT_WHEN_CNT_ROVER_RANGE                        12:12
+#define STAT_MON_APB_MON_CTRL_0_INT_WHEN_CNT_ROVER_WOFFSET                      0x0
+#define STAT_MON_APB_MON_CTRL_0_INT_WHEN_CNT_ROVER_DEFAULT                      _MK_MASK_CONST(0x0)
+#define STAT_MON_APB_MON_CTRL_0_INT_WHEN_CNT_ROVER_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define STAT_MON_APB_MON_CTRL_0_INT_WHEN_CNT_ROVER_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define STAT_MON_APB_MON_CTRL_0_INT_WHEN_CNT_ROVER_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define STAT_MON_APB_MON_CTRL_0_INT_WHEN_CNT_ROVER_DISABLE                      _MK_ENUM_CONST(0)    // // interrupt is disabled.     
+
+#define STAT_MON_APB_MON_CTRL_0_INT_WHEN_CNT_ROVER_ENABLE                       _MK_ENUM_CONST(1)
+
+// Reserved
+#define STAT_MON_APB_MON_CTRL_0_N_A0_SHIFT                      _MK_SHIFT_CONST(9)
+#define STAT_MON_APB_MON_CTRL_0_N_A0_FIELD                      (_MK_MASK_CONST(0x7) << STAT_MON_APB_MON_CTRL_0_N_A0_SHIFT)
+#define STAT_MON_APB_MON_CTRL_0_N_A0_RANGE                      11:9
+#define STAT_MON_APB_MON_CTRL_0_N_A0_WOFFSET                    0x0
+#define STAT_MON_APB_MON_CTRL_0_N_A0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define STAT_MON_APB_MON_CTRL_0_N_A0_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define STAT_MON_APB_MON_CTRL_0_N_A0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define STAT_MON_APB_MON_CTRL_0_N_A0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Indicate which APB slave to monitor. ALL 1s  means any master.
+#define STAT_MON_APB_MON_CTRL_0_SLV_NUMBER_SHIFT                        _MK_SHIFT_CONST(4)
+#define STAT_MON_APB_MON_CTRL_0_SLV_NUMBER_FIELD                        (_MK_MASK_CONST(0x1f) << STAT_MON_APB_MON_CTRL_0_SLV_NUMBER_SHIFT)
+#define STAT_MON_APB_MON_CTRL_0_SLV_NUMBER_RANGE                        8:4
+#define STAT_MON_APB_MON_CTRL_0_SLV_NUMBER_WOFFSET                      0x0
+#define STAT_MON_APB_MON_CTRL_0_SLV_NUMBER_DEFAULT                      _MK_MASK_CONST(0x0)
+#define STAT_MON_APB_MON_CTRL_0_SLV_NUMBER_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define STAT_MON_APB_MON_CTRL_0_SLV_NUMBER_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define STAT_MON_APB_MON_CTRL_0_SLV_NUMBER_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// 4b0001 = active data transfer count (one or any  slaves). 
+#define STAT_MON_APB_MON_CTRL_0_SAMPLE_COND_SHIFT                       _MK_SHIFT_CONST(0)
+#define STAT_MON_APB_MON_CTRL_0_SAMPLE_COND_FIELD                       (_MK_MASK_CONST(0xf) << STAT_MON_APB_MON_CTRL_0_SAMPLE_COND_SHIFT)
+#define STAT_MON_APB_MON_CTRL_0_SAMPLE_COND_RANGE                       3:0
+#define STAT_MON_APB_MON_CTRL_0_SAMPLE_COND_WOFFSET                     0x0
+#define STAT_MON_APB_MON_CTRL_0_SAMPLE_COND_DEFAULT                     _MK_MASK_CONST(0x0)
+#define STAT_MON_APB_MON_CTRL_0_SAMPLE_COND_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define STAT_MON_APB_MON_CTRL_0_SAMPLE_COND_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define STAT_MON_APB_MON_CTRL_0_SAMPLE_COND_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register STAT_MON_APB_MON_STATUS_0  
+#define STAT_MON_APB_MON_STATUS_0                       _MK_ADDR_CONST(0x1a4)
+#define STAT_MON_APB_MON_STATUS_0_WORD_COUNT                    0x1
+#define STAT_MON_APB_MON_STATUS_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define STAT_MON_APB_MON_STATUS_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
+#define STAT_MON_APB_MON_STATUS_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define STAT_MON_APB_MON_STATUS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define STAT_MON_APB_MON_STATUS_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define STAT_MON_APB_MON_STATUS_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+// Count.
+#define STAT_MON_APB_MON_STATUS_0_COUNT_SHIFT                   _MK_SHIFT_CONST(0)
+#define STAT_MON_APB_MON_STATUS_0_COUNT_FIELD                   (_MK_MASK_CONST(0xffffffff) << STAT_MON_APB_MON_STATUS_0_COUNT_SHIFT)
+#define STAT_MON_APB_MON_STATUS_0_COUNT_RANGE                   31:0
+#define STAT_MON_APB_MON_STATUS_0_COUNT_WOFFSET                 0x0
+#define STAT_MON_APB_MON_STATUS_0_COUNT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define STAT_MON_APB_MON_STATUS_0_COUNT_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
+#define STAT_MON_APB_MON_STATUS_0_COUNT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define STAT_MON_APB_MON_STATUS_0_COUNT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register STAT_MON_APB_LOWER_WMARK_0  
+#define STAT_MON_APB_LOWER_WMARK_0                      _MK_ADDR_CONST(0x1a8)
+#define STAT_MON_APB_LOWER_WMARK_0_WORD_COUNT                   0x1
+#define STAT_MON_APB_LOWER_WMARK_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define STAT_MON_APB_LOWER_WMARK_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define STAT_MON_APB_LOWER_WMARK_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define STAT_MON_APB_LOWER_WMARK_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define STAT_MON_APB_LOWER_WMARK_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
+#define STAT_MON_APB_LOWER_WMARK_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
+// Lower watermark count value.
+#define STAT_MON_APB_LOWER_WMARK_0_LOWER_WMARK_CNT_SHIFT                        _MK_SHIFT_CONST(0)
+#define STAT_MON_APB_LOWER_WMARK_0_LOWER_WMARK_CNT_FIELD                        (_MK_MASK_CONST(0xffffffff) << STAT_MON_APB_LOWER_WMARK_0_LOWER_WMARK_CNT_SHIFT)
+#define STAT_MON_APB_LOWER_WMARK_0_LOWER_WMARK_CNT_RANGE                        31:0
+#define STAT_MON_APB_LOWER_WMARK_0_LOWER_WMARK_CNT_WOFFSET                      0x0
+#define STAT_MON_APB_LOWER_WMARK_0_LOWER_WMARK_CNT_DEFAULT                      _MK_MASK_CONST(0x0)
+#define STAT_MON_APB_LOWER_WMARK_0_LOWER_WMARK_CNT_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
+#define STAT_MON_APB_LOWER_WMARK_0_LOWER_WMARK_CNT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define STAT_MON_APB_LOWER_WMARK_0_LOWER_WMARK_CNT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register STAT_MON_APB_UPPER_WMARK_0  
+#define STAT_MON_APB_UPPER_WMARK_0                      _MK_ADDR_CONST(0x1ac)
+#define STAT_MON_APB_UPPER_WMARK_0_WORD_COUNT                   0x1
+#define STAT_MON_APB_UPPER_WMARK_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define STAT_MON_APB_UPPER_WMARK_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define STAT_MON_APB_UPPER_WMARK_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define STAT_MON_APB_UPPER_WMARK_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define STAT_MON_APB_UPPER_WMARK_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
+#define STAT_MON_APB_UPPER_WMARK_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
+// Upper watermark count value.
+#define STAT_MON_APB_UPPER_WMARK_0_UPPER_WMARK_CNT_SHIFT                        _MK_SHIFT_CONST(0)
+#define STAT_MON_APB_UPPER_WMARK_0_UPPER_WMARK_CNT_FIELD                        (_MK_MASK_CONST(0xffffffff) << STAT_MON_APB_UPPER_WMARK_0_UPPER_WMARK_CNT_SHIFT)
+#define STAT_MON_APB_UPPER_WMARK_0_UPPER_WMARK_CNT_RANGE                        31:0
+#define STAT_MON_APB_UPPER_WMARK_0_UPPER_WMARK_CNT_WOFFSET                      0x0
+#define STAT_MON_APB_UPPER_WMARK_0_UPPER_WMARK_CNT_DEFAULT                      _MK_MASK_CONST(0x0)
+#define STAT_MON_APB_UPPER_WMARK_0_UPPER_WMARK_CNT_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
+#define STAT_MON_APB_UPPER_WMARK_0_UPPER_WMARK_CNT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define STAT_MON_APB_UPPER_WMARK_0_UPPER_WMARK_CNT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Reserved address 432 [0x1b0] 
+
+// Reserved address 436 [0x1b4] 
+
+// Reserved address 440 [0x1b8] 
+
+// Reserved address 444 [0x1bc] 
+
+// Register STAT_MON_VPIPE_MON_CTRL_0  
+#define STAT_MON_VPIPE_MON_CTRL_0                       _MK_ADDR_CONST(0x1c0)
+#define STAT_MON_VPIPE_MON_CTRL_0_WORD_COUNT                    0x1
+#define STAT_MON_VPIPE_MON_CTRL_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define STAT_MON_VPIPE_MON_CTRL_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
+#define STAT_MON_VPIPE_MON_CTRL_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define STAT_MON_VPIPE_MON_CTRL_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define STAT_MON_VPIPE_MON_CTRL_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define STAT_MON_VPIPE_MON_CTRL_0_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
+// Enable Monitor. Set by SW to enable sampling.  vpipe monitor is enabled.
+// Cleared in one of the following ways,
+// (a) When SW intends to stop the  monitor, it can do so by clearing this field, or
+// (b) when the sampling period  expires.
+#define STAT_MON_VPIPE_MON_CTRL_0_ENB_SHIFT                     _MK_SHIFT_CONST(31)
+#define STAT_MON_VPIPE_MON_CTRL_0_ENB_FIELD                     (_MK_MASK_CONST(0x1) << STAT_MON_VPIPE_MON_CTRL_0_ENB_SHIFT)
+#define STAT_MON_VPIPE_MON_CTRL_0_ENB_RANGE                     31:31
+#define STAT_MON_VPIPE_MON_CTRL_0_ENB_WOFFSET                   0x0
+#define STAT_MON_VPIPE_MON_CTRL_0_ENB_DEFAULT                   _MK_MASK_CONST(0x0)
+#define STAT_MON_VPIPE_MON_CTRL_0_ENB_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define STAT_MON_VPIPE_MON_CTRL_0_ENB_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define STAT_MON_VPIPE_MON_CTRL_0_ENB_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define STAT_MON_VPIPE_MON_CTRL_0_ENB_DISABLE                   _MK_ENUM_CONST(0)    // // vpipe monitor is disabled.     
+
+#define STAT_MON_VPIPE_MON_CTRL_0_ENB_ENABLE                    _MK_ENUM_CONST(1)
+
+// Enable interrupt when sampling period expires. interrupt is enabled.
+#define STAT_MON_VPIPE_MON_CTRL_0_INT_EN_SHIFT                  _MK_SHIFT_CONST(30)
+#define STAT_MON_VPIPE_MON_CTRL_0_INT_EN_FIELD                  (_MK_MASK_CONST(0x1) << STAT_MON_VPIPE_MON_CTRL_0_INT_EN_SHIFT)
+#define STAT_MON_VPIPE_MON_CTRL_0_INT_EN_RANGE                  30:30
+#define STAT_MON_VPIPE_MON_CTRL_0_INT_EN_WOFFSET                        0x0
+#define STAT_MON_VPIPE_MON_CTRL_0_INT_EN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define STAT_MON_VPIPE_MON_CTRL_0_INT_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define STAT_MON_VPIPE_MON_CTRL_0_INT_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define STAT_MON_VPIPE_MON_CTRL_0_INT_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define STAT_MON_VPIPE_MON_CTRL_0_INT_EN_DISABLE                        _MK_ENUM_CONST(0)    // // interrupt is disabled.     
+
+#define STAT_MON_VPIPE_MON_CTRL_0_INT_EN_ENABLE                 _MK_ENUM_CONST(1)
+
+// Assert by HW when sampling period expires when  INT_EN is set. 1 = interrupt detected
+// SW writing a 1 clears this bit. Writing 0 is ignored.
+#define STAT_MON_VPIPE_MON_CTRL_0_INT_SHIFT                     _MK_SHIFT_CONST(29)
+#define STAT_MON_VPIPE_MON_CTRL_0_INT_FIELD                     (_MK_MASK_CONST(0x1) << STAT_MON_VPIPE_MON_CTRL_0_INT_SHIFT)
+#define STAT_MON_VPIPE_MON_CTRL_0_INT_RANGE                     29:29
+#define STAT_MON_VPIPE_MON_CTRL_0_INT_WOFFSET                   0x0
+#define STAT_MON_VPIPE_MON_CTRL_0_INT_DEFAULT                   _MK_MASK_CONST(0x0)
+#define STAT_MON_VPIPE_MON_CTRL_0_INT_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define STAT_MON_VPIPE_MON_CTRL_0_INT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define STAT_MON_VPIPE_MON_CTRL_0_INT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define STAT_MON_VPIPE_MON_CTRL_0_INT_NOINT                     _MK_ENUM_CONST(0)    // // 0 = interrupt not detected
+
+#define STAT_MON_VPIPE_MON_CTRL_0_INT_INT                       _MK_ENUM_CONST(1)
+
+// 0 = sample only for the period mentioned in  SAMPLE_PERIOD. sample mode is enabled.
+#define STAT_MON_VPIPE_MON_CTRL_0_SAMPLE_MODE_SHIFT                     _MK_SHIFT_CONST(28)
+#define STAT_MON_VPIPE_MON_CTRL_0_SAMPLE_MODE_FIELD                     (_MK_MASK_CONST(0x1) << STAT_MON_VPIPE_MON_CTRL_0_SAMPLE_MODE_SHIFT)
+#define STAT_MON_VPIPE_MON_CTRL_0_SAMPLE_MODE_RANGE                     28:28
+#define STAT_MON_VPIPE_MON_CTRL_0_SAMPLE_MODE_WOFFSET                   0x0
+#define STAT_MON_VPIPE_MON_CTRL_0_SAMPLE_MODE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define STAT_MON_VPIPE_MON_CTRL_0_SAMPLE_MODE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define STAT_MON_VPIPE_MON_CTRL_0_SAMPLE_MODE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define STAT_MON_VPIPE_MON_CTRL_0_SAMPLE_MODE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define STAT_MON_VPIPE_MON_CTRL_0_SAMPLE_MODE_DISABLE                   _MK_ENUM_CONST(0)    // // sample mode is disabled.     
+
+#define STAT_MON_VPIPE_MON_CTRL_0_SAMPLE_MODE_ENABLE                    _MK_ENUM_CONST(1)
+
+// Sampling period in milliseconds (implemented as  n+1 counter).
+// Programming a 0 imply a 1 millisecond sampling period.
+#define STAT_MON_VPIPE_MON_CTRL_0_SAMPLE_PERIOD_SHIFT                   _MK_SHIFT_CONST(20)
+#define STAT_MON_VPIPE_MON_CTRL_0_SAMPLE_PERIOD_FIELD                   (_MK_MASK_CONST(0xff) << STAT_MON_VPIPE_MON_CTRL_0_SAMPLE_PERIOD_SHIFT)
+#define STAT_MON_VPIPE_MON_CTRL_0_SAMPLE_PERIOD_RANGE                   27:20
+#define STAT_MON_VPIPE_MON_CTRL_0_SAMPLE_PERIOD_WOFFSET                 0x0
+#define STAT_MON_VPIPE_MON_CTRL_0_SAMPLE_PERIOD_DEFAULT                 _MK_MASK_CONST(0x0)
+#define STAT_MON_VPIPE_MON_CTRL_0_SAMPLE_PERIOD_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define STAT_MON_VPIPE_MON_CTRL_0_SAMPLE_PERIOD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define STAT_MON_VPIPE_MON_CTRL_0_SAMPLE_PERIOD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Reserved
+#define STAT_MON_VPIPE_MON_CTRL_0_N_A_SHIFT                     _MK_SHIFT_CONST(4)
+#define STAT_MON_VPIPE_MON_CTRL_0_N_A_FIELD                     (_MK_MASK_CONST(0xffff) << STAT_MON_VPIPE_MON_CTRL_0_N_A_SHIFT)
+#define STAT_MON_VPIPE_MON_CTRL_0_N_A_RANGE                     19:4
+#define STAT_MON_VPIPE_MON_CTRL_0_N_A_WOFFSET                   0x0
+#define STAT_MON_VPIPE_MON_CTRL_0_N_A_DEFAULT                   _MK_MASK_CONST(0x0)
+#define STAT_MON_VPIPE_MON_CTRL_0_N_A_DEFAULT_MASK                      _MK_MASK_CONST(0xffff)
+#define STAT_MON_VPIPE_MON_CTRL_0_N_A_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define STAT_MON_VPIPE_MON_CTRL_0_N_A_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// 4b0011 = Monitor total words written during the 
+// sample period (writing to external Memory) on slot 2 + AHB: 32-bit data
+// writes only (not command data).
+#define STAT_MON_VPIPE_MON_CTRL_0_SAMPLE_COND_SHIFT                     _MK_SHIFT_CONST(0)
+#define STAT_MON_VPIPE_MON_CTRL_0_SAMPLE_COND_FIELD                     (_MK_MASK_CONST(0xf) << STAT_MON_VPIPE_MON_CTRL_0_SAMPLE_COND_SHIFT)
+#define STAT_MON_VPIPE_MON_CTRL_0_SAMPLE_COND_RANGE                     3:0
+#define STAT_MON_VPIPE_MON_CTRL_0_SAMPLE_COND_WOFFSET                   0x0
+#define STAT_MON_VPIPE_MON_CTRL_0_SAMPLE_COND_DEFAULT                   _MK_MASK_CONST(0x0)
+#define STAT_MON_VPIPE_MON_CTRL_0_SAMPLE_COND_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define STAT_MON_VPIPE_MON_CTRL_0_SAMPLE_COND_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define STAT_MON_VPIPE_MON_CTRL_0_SAMPLE_COND_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register STAT_MON_VPIPE_MON_STATUS_0  
+#define STAT_MON_VPIPE_MON_STATUS_0                     _MK_ADDR_CONST(0x1c4)
+#define STAT_MON_VPIPE_MON_STATUS_0_WORD_COUNT                  0x1
+#define STAT_MON_VPIPE_MON_STATUS_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define STAT_MON_VPIPE_MON_STATUS_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define STAT_MON_VPIPE_MON_STATUS_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define STAT_MON_VPIPE_MON_STATUS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define STAT_MON_VPIPE_MON_STATUS_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define STAT_MON_VPIPE_MON_STATUS_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+// SAMPLE_COND = 4b0011: number of words written to  external memory in the Sample period.
+#define STAT_MON_VPIPE_MON_STATUS_0_COUNT_SHIFT                 _MK_SHIFT_CONST(0)
+#define STAT_MON_VPIPE_MON_STATUS_0_COUNT_FIELD                 (_MK_MASK_CONST(0xffffffff) << STAT_MON_VPIPE_MON_STATUS_0_COUNT_SHIFT)
+#define STAT_MON_VPIPE_MON_STATUS_0_COUNT_RANGE                 31:0
+#define STAT_MON_VPIPE_MON_STATUS_0_COUNT_WOFFSET                       0x0
+#define STAT_MON_VPIPE_MON_STATUS_0_COUNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define STAT_MON_VPIPE_MON_STATUS_0_COUNT_DEFAULT_MASK                  _MK_MASK_CONST(0xffffffff)
+#define STAT_MON_VPIPE_MON_STATUS_0_COUNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define STAT_MON_VPIPE_MON_STATUS_0_COUNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Reserved address 456 [0x1c8] 
+
+// Reserved address 460 [0x1cc] 
+
+// Reserved address 464 [0x1d0] 
+
+// Reserved address 468 [0x1d4] 
+
+// Reserved address 472 [0x1d8] 
+
+// Reserved address 476 [0x1dc] 
+
+// Register STAT_MON_SMP_MON_CTRL_0  
+#define STAT_MON_SMP_MON_CTRL_0                 _MK_ADDR_CONST(0x1e0)
+#define STAT_MON_SMP_MON_CTRL_0_WORD_COUNT                      0x1
+#define STAT_MON_SMP_MON_CTRL_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define STAT_MON_SMP_MON_CTRL_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define STAT_MON_SMP_MON_CTRL_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define STAT_MON_SMP_MON_CTRL_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define STAT_MON_SMP_MON_CTRL_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define STAT_MON_SMP_MON_CTRL_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Enable Monitor. Set by SW to enable sampling. semaphore monitor is enabled.
+// Cleared in one of the following ways,
+// (a) When SW intends to stop the  monitor, it can do so by clearing this field, or
+// (b) when the sampling period  expires.
+#define STAT_MON_SMP_MON_CTRL_0_ENB_SHIFT                       _MK_SHIFT_CONST(31)
+#define STAT_MON_SMP_MON_CTRL_0_ENB_FIELD                       (_MK_MASK_CONST(0x1) << STAT_MON_SMP_MON_CTRL_0_ENB_SHIFT)
+#define STAT_MON_SMP_MON_CTRL_0_ENB_RANGE                       31:31
+#define STAT_MON_SMP_MON_CTRL_0_ENB_WOFFSET                     0x0
+#define STAT_MON_SMP_MON_CTRL_0_ENB_DEFAULT                     _MK_MASK_CONST(0x0)
+#define STAT_MON_SMP_MON_CTRL_0_ENB_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define STAT_MON_SMP_MON_CTRL_0_ENB_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define STAT_MON_SMP_MON_CTRL_0_ENB_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define STAT_MON_SMP_MON_CTRL_0_ENB_DISABLE                     _MK_ENUM_CONST(0)    // // semaphore monitor is disabled.     
+
+#define STAT_MON_SMP_MON_CTRL_0_ENB_ENABLE                      _MK_ENUM_CONST(1)
+
+// Enable interrupt when sampling period expires. interrupt is enabled.
+#define STAT_MON_SMP_MON_CTRL_0_INT_EN_SHIFT                    _MK_SHIFT_CONST(30)
+#define STAT_MON_SMP_MON_CTRL_0_INT_EN_FIELD                    (_MK_MASK_CONST(0x1) << STAT_MON_SMP_MON_CTRL_0_INT_EN_SHIFT)
+#define STAT_MON_SMP_MON_CTRL_0_INT_EN_RANGE                    30:30
+#define STAT_MON_SMP_MON_CTRL_0_INT_EN_WOFFSET                  0x0
+#define STAT_MON_SMP_MON_CTRL_0_INT_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define STAT_MON_SMP_MON_CTRL_0_INT_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define STAT_MON_SMP_MON_CTRL_0_INT_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define STAT_MON_SMP_MON_CTRL_0_INT_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define STAT_MON_SMP_MON_CTRL_0_INT_EN_DISABLE                  _MK_ENUM_CONST(0)    // // interrupt is disabled.     
+
+#define STAT_MON_SMP_MON_CTRL_0_INT_EN_ENABLE                   _MK_ENUM_CONST(1)
+
+// Assert by HW when sampling period expires when INT_EN  is set. 1 = interrupt detected
+// SW writing a 1 clears this bit. Writing 0 is ignored.
+#define STAT_MON_SMP_MON_CTRL_0_INT_SHIFT                       _MK_SHIFT_CONST(29)
+#define STAT_MON_SMP_MON_CTRL_0_INT_FIELD                       (_MK_MASK_CONST(0x1) << STAT_MON_SMP_MON_CTRL_0_INT_SHIFT)
+#define STAT_MON_SMP_MON_CTRL_0_INT_RANGE                       29:29
+#define STAT_MON_SMP_MON_CTRL_0_INT_WOFFSET                     0x0
+#define STAT_MON_SMP_MON_CTRL_0_INT_DEFAULT                     _MK_MASK_CONST(0x0)
+#define STAT_MON_SMP_MON_CTRL_0_INT_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define STAT_MON_SMP_MON_CTRL_0_INT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define STAT_MON_SMP_MON_CTRL_0_INT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define STAT_MON_SMP_MON_CTRL_0_INT_NOINT                       _MK_ENUM_CONST(0)    // // 0 = interrupt not detected
+
+#define STAT_MON_SMP_MON_CTRL_0_INT_INT                 _MK_ENUM_CONST(1)
+
+// 0 = sample only for the period mentioned in  SAMPLE_PERIOD. sample mode is enabled.
+#define STAT_MON_SMP_MON_CTRL_0_SAMPLE_MODE_SHIFT                       _MK_SHIFT_CONST(28)
+#define STAT_MON_SMP_MON_CTRL_0_SAMPLE_MODE_FIELD                       (_MK_MASK_CONST(0x1) << STAT_MON_SMP_MON_CTRL_0_SAMPLE_MODE_SHIFT)
+#define STAT_MON_SMP_MON_CTRL_0_SAMPLE_MODE_RANGE                       28:28
+#define STAT_MON_SMP_MON_CTRL_0_SAMPLE_MODE_WOFFSET                     0x0
+#define STAT_MON_SMP_MON_CTRL_0_SAMPLE_MODE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define STAT_MON_SMP_MON_CTRL_0_SAMPLE_MODE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define STAT_MON_SMP_MON_CTRL_0_SAMPLE_MODE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define STAT_MON_SMP_MON_CTRL_0_SAMPLE_MODE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define STAT_MON_SMP_MON_CTRL_0_SAMPLE_MODE_DISABLE                     _MK_ENUM_CONST(0)    // // sample mode is disabled.     
+
+#define STAT_MON_SMP_MON_CTRL_0_SAMPLE_MODE_ENABLE                      _MK_ENUM_CONST(1)
+
+// Sampling period in milliseconds (implemented as  n+1 counter).
+// Programming a 0 imply a 1 millisecond sampling period.
+#define STAT_MON_SMP_MON_CTRL_0_SAMPLE_PERIOD_SHIFT                     _MK_SHIFT_CONST(20)
+#define STAT_MON_SMP_MON_CTRL_0_SAMPLE_PERIOD_FIELD                     (_MK_MASK_CONST(0xff) << STAT_MON_SMP_MON_CTRL_0_SAMPLE_PERIOD_SHIFT)
+#define STAT_MON_SMP_MON_CTRL_0_SAMPLE_PERIOD_RANGE                     27:20
+#define STAT_MON_SMP_MON_CTRL_0_SAMPLE_PERIOD_WOFFSET                   0x0
+#define STAT_MON_SMP_MON_CTRL_0_SAMPLE_PERIOD_DEFAULT                   _MK_MASK_CONST(0x0)
+#define STAT_MON_SMP_MON_CTRL_0_SAMPLE_PERIOD_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define STAT_MON_SMP_MON_CTRL_0_SAMPLE_PERIOD_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define STAT_MON_SMP_MON_CTRL_0_SAMPLE_PERIOD_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// 
+#define STAT_MON_SMP_MON_CTRL_0_N_A1_SHIFT                      _MK_SHIFT_CONST(19)
+#define STAT_MON_SMP_MON_CTRL_0_N_A1_FIELD                      (_MK_MASK_CONST(0x1) << STAT_MON_SMP_MON_CTRL_0_N_A1_SHIFT)
+#define STAT_MON_SMP_MON_CTRL_0_N_A1_RANGE                      19:19
+#define STAT_MON_SMP_MON_CTRL_0_N_A1_WOFFSET                    0x0
+#define STAT_MON_SMP_MON_CTRL_0_N_A1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define STAT_MON_SMP_MON_CTRL_0_N_A1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define STAT_MON_SMP_MON_CTRL_0_N_A1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define STAT_MON_SMP_MON_CTRL_0_N_A1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+//  0 = clk count mode (in number of  sclk).  countmode is enabled.
+#define STAT_MON_SMP_MON_CTRL_0_CLK_CNT_MODE_SHIFT                      _MK_SHIFT_CONST(18)
+#define STAT_MON_SMP_MON_CTRL_0_CLK_CNT_MODE_FIELD                      (_MK_MASK_CONST(0x1) << STAT_MON_SMP_MON_CTRL_0_CLK_CNT_MODE_SHIFT)
+#define STAT_MON_SMP_MON_CTRL_0_CLK_CNT_MODE_RANGE                      18:18
+#define STAT_MON_SMP_MON_CTRL_0_CLK_CNT_MODE_WOFFSET                    0x0
+#define STAT_MON_SMP_MON_CTRL_0_CLK_CNT_MODE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define STAT_MON_SMP_MON_CTRL_0_CLK_CNT_MODE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define STAT_MON_SMP_MON_CTRL_0_CLK_CNT_MODE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define STAT_MON_SMP_MON_CTRL_0_CLK_CNT_MODE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define STAT_MON_SMP_MON_CTRL_0_CLK_CNT_MODE_DISABLE                    _MK_ENUM_CONST(0)    // // count mode is disabled.     
+
+#define STAT_MON_SMP_MON_CTRL_0_CLK_CNT_MODE_ENABLE                     _MK_ENUM_CONST(1)
+
+// Reserved
+#define STAT_MON_SMP_MON_CTRL_0_N_A0_SHIFT                      _MK_SHIFT_CONST(9)
+#define STAT_MON_SMP_MON_CTRL_0_N_A0_FIELD                      (_MK_MASK_CONST(0x1ff) << STAT_MON_SMP_MON_CTRL_0_N_A0_SHIFT)
+#define STAT_MON_SMP_MON_CTRL_0_N_A0_RANGE                      17:9
+#define STAT_MON_SMP_MON_CTRL_0_N_A0_WOFFSET                    0x0
+#define STAT_MON_SMP_MON_CTRL_0_N_A0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define STAT_MON_SMP_MON_CTRL_0_N_A0_DEFAULT_MASK                       _MK_MASK_CONST(0x1ff)
+#define STAT_MON_SMP_MON_CTRL_0_N_A0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define STAT_MON_SMP_MON_CTRL_0_N_A0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// 5h1F: start counter when CMP.31 is set.
+#define STAT_MON_SMP_MON_CTRL_0_START_COND_SHIFT                        _MK_SHIFT_CONST(4)
+#define STAT_MON_SMP_MON_CTRL_0_START_COND_FIELD                        (_MK_MASK_CONST(0x1f) << STAT_MON_SMP_MON_CTRL_0_START_COND_SHIFT)
+#define STAT_MON_SMP_MON_CTRL_0_START_COND_RANGE                        8:4
+#define STAT_MON_SMP_MON_CTRL_0_START_COND_WOFFSET                      0x0
+#define STAT_MON_SMP_MON_CTRL_0_START_COND_DEFAULT                      _MK_MASK_CONST(0x0)
+#define STAT_MON_SMP_MON_CTRL_0_START_COND_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define STAT_MON_SMP_MON_CTRL_0_START_COND_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define STAT_MON_SMP_MON_CTRL_0_START_COND_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+//  The sample period expires, whichever happens  first.
+#define STAT_MON_SMP_MON_CTRL_0_STOP_COND_SHIFT                 _MK_SHIFT_CONST(0)
+#define STAT_MON_SMP_MON_CTRL_0_STOP_COND_FIELD                 (_MK_MASK_CONST(0xf) << STAT_MON_SMP_MON_CTRL_0_STOP_COND_SHIFT)
+#define STAT_MON_SMP_MON_CTRL_0_STOP_COND_RANGE                 3:0
+#define STAT_MON_SMP_MON_CTRL_0_STOP_COND_WOFFSET                       0x0
+#define STAT_MON_SMP_MON_CTRL_0_STOP_COND_DEFAULT                       _MK_MASK_CONST(0x0)
+#define STAT_MON_SMP_MON_CTRL_0_STOP_COND_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define STAT_MON_SMP_MON_CTRL_0_STOP_COND_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define STAT_MON_SMP_MON_CTRL_0_STOP_COND_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register STAT_MON_SMP_MON_STATUS_0  
+#define STAT_MON_SMP_MON_STATUS_0                       _MK_ADDR_CONST(0x1e4)
+#define STAT_MON_SMP_MON_STATUS_0_WORD_COUNT                    0x1
+#define STAT_MON_SMP_MON_STATUS_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define STAT_MON_SMP_MON_STATUS_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
+#define STAT_MON_SMP_MON_STATUS_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define STAT_MON_SMP_MON_STATUS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define STAT_MON_SMP_MON_STATUS_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define STAT_MON_SMP_MON_STATUS_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+// count
+#define STAT_MON_SMP_MON_STATUS_0_COUNT_SHIFT                   _MK_SHIFT_CONST(0)
+#define STAT_MON_SMP_MON_STATUS_0_COUNT_FIELD                   (_MK_MASK_CONST(0xffffffff) << STAT_MON_SMP_MON_STATUS_0_COUNT_SHIFT)
+#define STAT_MON_SMP_MON_STATUS_0_COUNT_RANGE                   31:0
+#define STAT_MON_SMP_MON_STATUS_0_COUNT_WOFFSET                 0x0
+#define STAT_MON_SMP_MON_STATUS_0_COUNT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define STAT_MON_SMP_MON_STATUS_0_COUNT_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
+#define STAT_MON_SMP_MON_STATUS_0_COUNT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define STAT_MON_SMP_MON_STATUS_0_COUNT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+//
+// REGISTER LIST
+//
+#define LIST_ARSTAT_MON_REGS(_op_) \
+_op_(STAT_MON_GLB_INT_STATUS_0) \
+_op_(STAT_MON_CPU_MON_CTRL_0) \
+_op_(STAT_MON_CPU_MON_STATUS_0) \
+_op_(STAT_MON_COP_MON_CTRL_0) \
+_op_(STAT_MON_COP_MON_STATUS_0) \
+_op_(STAT_MON_CACHE2_MON_CTRL_0) \
+_op_(STAT_MON_CACHE2_REQ_STATUS_0) \
+_op_(STAT_MON_CACHE2_HIT_STATUS_0) \
+_op_(STAT_MON_AHB_MON_CTRL_0) \
+_op_(STAT_MON_AHB_MON_STATUS_0) \
+_op_(STAT_MON_AHB_LOWER_WMARK_0) \
+_op_(STAT_MON_AHB_UPPER_WMARK_0) \
+_op_(STAT_MON_APB_MON_CTRL_0) \
+_op_(STAT_MON_APB_MON_STATUS_0) \
+_op_(STAT_MON_APB_LOWER_WMARK_0) \
+_op_(STAT_MON_APB_UPPER_WMARK_0) \
+_op_(STAT_MON_VPIPE_MON_CTRL_0) \
+_op_(STAT_MON_VPIPE_MON_STATUS_0) \
+_op_(STAT_MON_SMP_MON_CTRL_0) \
+_op_(STAT_MON_SMP_MON_STATUS_0)
+
+
+//
+// ADDRESS SPACES
+//
+
+#define BASE_ADDRESS_STAT_MON   0x00000000
+
+//
+// ARSTAT_MON REGISTER BANKS
+//
+
+#define STAT_MON0_FIRST_REG 0x0000 // STAT_MON_GLB_INT_STATUS_0
+#define STAT_MON0_LAST_REG 0x0000 // STAT_MON_GLB_INT_STATUS_0
+#define STAT_MON1_FIRST_REG 0x0100 // STAT_MON_CPU_MON_CTRL_0
+#define STAT_MON1_LAST_REG 0x0104 // STAT_MON_CPU_MON_STATUS_0
+#define STAT_MON2_FIRST_REG 0x0120 // STAT_MON_COP_MON_CTRL_0
+#define STAT_MON2_LAST_REG 0x0124 // STAT_MON_COP_MON_STATUS_0
+#define STAT_MON3_FIRST_REG 0x0160 // STAT_MON_CACHE2_MON_CTRL_0
+#define STAT_MON3_LAST_REG 0x0168 // STAT_MON_CACHE2_HIT_STATUS_0
+#define STAT_MON4_FIRST_REG 0x0180 // STAT_MON_AHB_MON_CTRL_0
+#define STAT_MON4_LAST_REG 0x018c // STAT_MON_AHB_UPPER_WMARK_0
+#define STAT_MON5_FIRST_REG 0x01a0 // STAT_MON_APB_MON_CTRL_0
+#define STAT_MON5_LAST_REG 0x01ac // STAT_MON_APB_UPPER_WMARK_0
+#define STAT_MON6_FIRST_REG 0x01c0 // STAT_MON_VPIPE_MON_CTRL_0
+#define STAT_MON6_LAST_REG 0x01c4 // STAT_MON_VPIPE_MON_STATUS_0
+#define STAT_MON7_FIRST_REG 0x01e0 // STAT_MON_SMP_MON_CTRL_0
+#define STAT_MON7_LAST_REG 0x01e4 // STAT_MON_SMP_MON_STATUS_0
+
+#ifndef _MK_SHIFT_CONST
+  #define _MK_SHIFT_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_MASK_CONST
+  #define _MK_MASK_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_ENUM_CONST
+  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
+#endif
+#ifndef _MK_ADDR_CONST
+  #define _MK_ADDR_CONST(_constant_) _constant_
+#endif
+
+#endif // ifndef ___ARSTAT_MON_H_INC_
diff --git a/arch/arm/mach-tegra/include/ap15/artimer.h b/arch/arm/mach-tegra/include/ap15/artimer.h
new file mode 100644
index 000000000000..235d6b512fab
--- /dev/null
+++ b/arch/arm/mach-tegra/include/ap15/artimer.h
@@ -0,0 +1,179 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+//
+// DO NOT EDIT - generated by simspec!
+//
+
+#ifndef ___ARTIMER_H_INC_
+#define ___ARTIMER_H_INC_
+
+// Register TIMER_TMR_PTV_0  
+#define TIMER_TMR_PTV_0                 _MK_ADDR_CONST(0x0)
+#define TIMER_TMR_PTV_0_WORD_COUNT                      0x1
+#define TIMER_TMR_PTV_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define TIMER_TMR_PTV_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define TIMER_TMR_PTV_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define TIMER_TMR_PTV_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define TIMER_TMR_PTV_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define TIMER_TMR_PTV_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Enable Timer 
+#define TIMER_TMR_PTV_0_EN_SHIFT                        _MK_SHIFT_CONST(31)
+#define TIMER_TMR_PTV_0_EN_FIELD                        (_MK_MASK_CONST(0x1) << TIMER_TMR_PTV_0_EN_SHIFT)
+#define TIMER_TMR_PTV_0_EN_RANGE                        31:31
+#define TIMER_TMR_PTV_0_EN_WOFFSET                      0x0
+#define TIMER_TMR_PTV_0_EN_DEFAULT                      _MK_MASK_CONST(0x0)
+#define TIMER_TMR_PTV_0_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define TIMER_TMR_PTV_0_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define TIMER_TMR_PTV_0_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define TIMER_TMR_PTV_0_EN_DISABLE                      _MK_ENUM_CONST(0)
+#define TIMER_TMR_PTV_0_EN_ENABLE                       _MK_ENUM_CONST(1)
+
+// Enable Periodic Interrupt
+#define TIMER_TMR_PTV_0_PER_SHIFT                       _MK_SHIFT_CONST(30)
+#define TIMER_TMR_PTV_0_PER_FIELD                       (_MK_MASK_CONST(0x1) << TIMER_TMR_PTV_0_PER_SHIFT)
+#define TIMER_TMR_PTV_0_PER_RANGE                       30:30
+#define TIMER_TMR_PTV_0_PER_WOFFSET                     0x0
+#define TIMER_TMR_PTV_0_PER_DEFAULT                     _MK_MASK_CONST(0x0)
+#define TIMER_TMR_PTV_0_PER_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define TIMER_TMR_PTV_0_PER_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define TIMER_TMR_PTV_0_PER_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define TIMER_TMR_PTV_0_PER_DISABLE                     _MK_ENUM_CONST(0)
+#define TIMER_TMR_PTV_0_PER_ENABLE                      _MK_ENUM_CONST(1)
+
+// Reserved 
+#define TIMER_TMR_PTV_0_N_A_SHIFT                       _MK_SHIFT_CONST(29)
+#define TIMER_TMR_PTV_0_N_A_FIELD                       (_MK_MASK_CONST(0x1) << TIMER_TMR_PTV_0_N_A_SHIFT)
+#define TIMER_TMR_PTV_0_N_A_RANGE                       29:29
+#define TIMER_TMR_PTV_0_N_A_WOFFSET                     0x0
+#define TIMER_TMR_PTV_0_N_A_DEFAULT                     _MK_MASK_CONST(0x0)
+#define TIMER_TMR_PTV_0_N_A_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define TIMER_TMR_PTV_0_N_A_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define TIMER_TMR_PTV_0_N_A_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Trigger Value: count trigger value (count length).  This
+// is in n+1 scheme.  If you program the value n, the count
+// trigger value will actually be n+1.
+#define TIMER_TMR_PTV_0_TMR_PTV_SHIFT                   _MK_SHIFT_CONST(0)
+#define TIMER_TMR_PTV_0_TMR_PTV_FIELD                   (_MK_MASK_CONST(0x1fffffff) << TIMER_TMR_PTV_0_TMR_PTV_SHIFT)
+#define TIMER_TMR_PTV_0_TMR_PTV_RANGE                   28:0
+#define TIMER_TMR_PTV_0_TMR_PTV_WOFFSET                 0x0
+#define TIMER_TMR_PTV_0_TMR_PTV_DEFAULT                 _MK_MASK_CONST(0x0)
+#define TIMER_TMR_PTV_0_TMR_PTV_DEFAULT_MASK                    _MK_MASK_CONST(0x1fffffff)
+#define TIMER_TMR_PTV_0_TMR_PTV_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define TIMER_TMR_PTV_0_TMR_PTV_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register TIMER_TMR_PCR_0  
+#define TIMER_TMR_PCR_0                 _MK_ADDR_CONST(0x4)
+#define TIMER_TMR_PCR_0_WORD_COUNT                      0x1
+#define TIMER_TMR_PCR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define TIMER_TMR_PCR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define TIMER_TMR_PCR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define TIMER_TMR_PCR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define TIMER_TMR_PCR_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define TIMER_TMR_PCR_0_WRITE_MASK                      _MK_MASK_CONST(0x40000000)
+// Reserved = 0
+#define TIMER_TMR_PCR_0_N_A2_SHIFT                      _MK_SHIFT_CONST(31)
+#define TIMER_TMR_PCR_0_N_A2_FIELD                      (_MK_MASK_CONST(0x1) << TIMER_TMR_PCR_0_N_A2_SHIFT)
+#define TIMER_TMR_PCR_0_N_A2_RANGE                      31:31
+#define TIMER_TMR_PCR_0_N_A2_WOFFSET                    0x0
+#define TIMER_TMR_PCR_0_N_A2_DEFAULT                    _MK_MASK_CONST(0x0)
+#define TIMER_TMR_PCR_0_N_A2_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define TIMER_TMR_PCR_0_N_A2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define TIMER_TMR_PCR_0_N_A2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// 1 = clears the interrupt, 0 = no affect. Wtite-1-to-Clear
+#define TIMER_TMR_PCR_0_INTR_CLR_SHIFT                  _MK_SHIFT_CONST(30)
+#define TIMER_TMR_PCR_0_INTR_CLR_FIELD                  (_MK_MASK_CONST(0x1) << TIMER_TMR_PCR_0_INTR_CLR_SHIFT)
+#define TIMER_TMR_PCR_0_INTR_CLR_RANGE                  30:30
+#define TIMER_TMR_PCR_0_INTR_CLR_WOFFSET                        0x0
+#define TIMER_TMR_PCR_0_INTR_CLR_DEFAULT                        _MK_MASK_CONST(0x0)
+#define TIMER_TMR_PCR_0_INTR_CLR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define TIMER_TMR_PCR_0_INTR_CLR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define TIMER_TMR_PCR_0_INTR_CLR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Reserved = 0 
+#define TIMER_TMR_PCR_0_N_A1_SHIFT                      _MK_SHIFT_CONST(29)
+#define TIMER_TMR_PCR_0_N_A1_FIELD                      (_MK_MASK_CONST(0x1) << TIMER_TMR_PCR_0_N_A1_SHIFT)
+#define TIMER_TMR_PCR_0_N_A1_RANGE                      29:29
+#define TIMER_TMR_PCR_0_N_A1_WOFFSET                    0x0
+#define TIMER_TMR_PCR_0_N_A1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define TIMER_TMR_PCR_0_N_A1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define TIMER_TMR_PCR_0_N_A1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define TIMER_TMR_PCR_0_N_A1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Counter value: decrements from PTV.
+#define TIMER_TMR_PCR_0_TMR_PCV_SHIFT                   _MK_SHIFT_CONST(0)
+#define TIMER_TMR_PCR_0_TMR_PCV_FIELD                   (_MK_MASK_CONST(0x1fffffff) << TIMER_TMR_PCR_0_TMR_PCV_SHIFT)
+#define TIMER_TMR_PCR_0_TMR_PCV_RANGE                   28:0
+#define TIMER_TMR_PCR_0_TMR_PCV_WOFFSET                 0x0
+#define TIMER_TMR_PCR_0_TMR_PCV_DEFAULT                 _MK_MASK_CONST(0x0)
+#define TIMER_TMR_PCR_0_TMR_PCV_DEFAULT_MASK                    _MK_MASK_CONST(0x1fffffff)
+#define TIMER_TMR_PCR_0_TMR_PCV_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define TIMER_TMR_PCR_0_TMR_PCV_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+//
+// REGISTER LIST
+//
+#define LIST_ARTIMER_REGS(_op_) \
+_op_(TIMER_TMR_PTV_0) \
+_op_(TIMER_TMR_PCR_0)
+
+
+//
+// ADDRESS SPACES
+//
+
+#define BASE_ADDRESS_TIMER      0x00000000
+
+//
+// ARTIMER REGISTER BANKS
+//
+
+#define TIMER0_FIRST_REG 0x0000 // TIMER_TMR_PTV_0
+#define TIMER0_LAST_REG 0x0004 // TIMER_TMR_PCR_0
+
+#ifndef _MK_SHIFT_CONST
+  #define _MK_SHIFT_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_MASK_CONST
+  #define _MK_MASK_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_ENUM_CONST
+  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
+#endif
+#ifndef _MK_ADDR_CONST
+  #define _MK_ADDR_CONST(_constant_) _constant_
+#endif
+
+#endif // ifndef ___ARTIMER_H_INC_
diff --git a/arch/arm/mach-tegra/include/ap15/artimerus.h b/arch/arm/mach-tegra/include/ap15/artimerus.h
new file mode 100644
index 000000000000..8cabac1f4349
--- /dev/null
+++ b/arch/arm/mach-tegra/include/ap15/artimerus.h
@@ -0,0 +1,135 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+//
+// DO NOT EDIT - generated by simspec!
+//
+
+#ifndef ___ARTIMERUS_H_INC_
+#define ___ARTIMERUS_H_INC_
+
+// Register TIMERUS_CNTR_1US_0  
+#define TIMERUS_CNTR_1US_0                      _MK_ADDR_CONST(0x0)
+#define TIMERUS_CNTR_1US_0_WORD_COUNT                   0x1
+#define TIMERUS_CNTR_1US_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define TIMERUS_CNTR_1US_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define TIMERUS_CNTR_1US_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define TIMERUS_CNTR_1US_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define TIMERUS_CNTR_1US_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
+#define TIMERUS_CNTR_1US_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
+// Elapsed time in micro-second 
+#define TIMERUS_CNTR_1US_0_HIGH_VALUE_SHIFT                     _MK_SHIFT_CONST(16)
+#define TIMERUS_CNTR_1US_0_HIGH_VALUE_FIELD                     (_MK_MASK_CONST(0xffff) << TIMERUS_CNTR_1US_0_HIGH_VALUE_SHIFT)
+#define TIMERUS_CNTR_1US_0_HIGH_VALUE_RANGE                     31:16
+#define TIMERUS_CNTR_1US_0_HIGH_VALUE_WOFFSET                   0x0
+#define TIMERUS_CNTR_1US_0_HIGH_VALUE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define TIMERUS_CNTR_1US_0_HIGH_VALUE_DEFAULT_MASK                      _MK_MASK_CONST(0xffff)
+#define TIMERUS_CNTR_1US_0_HIGH_VALUE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define TIMERUS_CNTR_1US_0_HIGH_VALUE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define TIMERUS_CNTR_1US_0_HIGH_VALUE_INIT_ENUM                 x
+
+// Elapsed time in micro-second 
+#define TIMERUS_CNTR_1US_0_LOW_VALUE_SHIFT                      _MK_SHIFT_CONST(0)
+#define TIMERUS_CNTR_1US_0_LOW_VALUE_FIELD                      (_MK_MASK_CONST(0xffff) << TIMERUS_CNTR_1US_0_LOW_VALUE_SHIFT)
+#define TIMERUS_CNTR_1US_0_LOW_VALUE_RANGE                      15:0
+#define TIMERUS_CNTR_1US_0_LOW_VALUE_WOFFSET                    0x0
+#define TIMERUS_CNTR_1US_0_LOW_VALUE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define TIMERUS_CNTR_1US_0_LOW_VALUE_DEFAULT_MASK                       _MK_MASK_CONST(0xffff)
+#define TIMERUS_CNTR_1US_0_LOW_VALUE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define TIMERUS_CNTR_1US_0_LOW_VALUE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define TIMERUS_CNTR_1US_0_LOW_VALUE_INIT_ENUM                  x
+
+
+// Register TIMERUS_USEC_CFG_0  
+#define TIMERUS_USEC_CFG_0                      _MK_ADDR_CONST(0x4)
+#define TIMERUS_USEC_CFG_0_WORD_COUNT                   0x1
+#define TIMERUS_USEC_CFG_0_RESET_VAL                    _MK_MASK_CONST(0xc)
+#define TIMERUS_USEC_CFG_0_RESET_MASK                   _MK_MASK_CONST(0xffff)
+#define TIMERUS_USEC_CFG_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define TIMERUS_USEC_CFG_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define TIMERUS_USEC_CFG_0_READ_MASK                    _MK_MASK_CONST(0xffff)
+#define TIMERUS_USEC_CFG_0_WRITE_MASK                   _MK_MASK_CONST(0xffff)
+// usec dividend.
+#define TIMERUS_USEC_CFG_0_USEC_DIVIDEND_SHIFT                  _MK_SHIFT_CONST(8)
+#define TIMERUS_USEC_CFG_0_USEC_DIVIDEND_FIELD                  (_MK_MASK_CONST(0xff) << TIMERUS_USEC_CFG_0_USEC_DIVIDEND_SHIFT)
+#define TIMERUS_USEC_CFG_0_USEC_DIVIDEND_RANGE                  15:8
+#define TIMERUS_USEC_CFG_0_USEC_DIVIDEND_WOFFSET                        0x0
+#define TIMERUS_USEC_CFG_0_USEC_DIVIDEND_DEFAULT                        _MK_MASK_CONST(0x0)
+#define TIMERUS_USEC_CFG_0_USEC_DIVIDEND_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
+#define TIMERUS_USEC_CFG_0_USEC_DIVIDEND_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define TIMERUS_USEC_CFG_0_USEC_DIVIDEND_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// usec divisor.
+#define TIMERUS_USEC_CFG_0_USEC_DIVISOR_SHIFT                   _MK_SHIFT_CONST(0)
+#define TIMERUS_USEC_CFG_0_USEC_DIVISOR_FIELD                   (_MK_MASK_CONST(0xff) << TIMERUS_USEC_CFG_0_USEC_DIVISOR_SHIFT)
+#define TIMERUS_USEC_CFG_0_USEC_DIVISOR_RANGE                   7:0
+#define TIMERUS_USEC_CFG_0_USEC_DIVISOR_WOFFSET                 0x0
+#define TIMERUS_USEC_CFG_0_USEC_DIVISOR_DEFAULT                 _MK_MASK_CONST(0xc)
+#define TIMERUS_USEC_CFG_0_USEC_DIVISOR_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define TIMERUS_USEC_CFG_0_USEC_DIVISOR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define TIMERUS_USEC_CFG_0_USEC_DIVISOR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+//
+// REGISTER LIST
+//
+#define LIST_ARTIMERUS_REGS(_op_) \
+_op_(TIMERUS_CNTR_1US_0) \
+_op_(TIMERUS_USEC_CFG_0)
+
+
+//
+// ADDRESS SPACES
+//
+
+#define BASE_ADDRESS_TIMERUS    0x00000000
+
+//
+// ARTIMERUS REGISTER BANKS
+//
+
+#define TIMERUS0_FIRST_REG 0x0000 // TIMERUS_CNTR_1US_0
+#define TIMERUS0_LAST_REG 0x0004 // TIMERUS_USEC_CFG_0
+
+#ifndef _MK_SHIFT_CONST
+  #define _MK_SHIFT_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_MASK_CONST
+  #define _MK_MASK_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_ENUM_CONST
+  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
+#endif
+#ifndef _MK_ADDR_CONST
+  #define _MK_ADDR_CONST(_constant_) _constant_
+#endif
+
+#endif // ifndef ___ARTIMERUS_H_INC_
diff --git a/arch/arm/mach-tegra/include/ap15/arvde_mon.h b/arch/arm/mach-tegra/include/ap15/arvde_mon.h
new file mode 100644
index 000000000000..0ab6185bee33
--- /dev/null
+++ b/arch/arm/mach-tegra/include/ap15/arvde_mon.h
@@ -0,0 +1,268 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+#ifndef ___ARVDE_MON_H_INC_
+#define ___ARVDE_MON_H_INC_
+//----------------------------------------------------------
+// PPB, IDLE, & debug-observability
+// --------------------------------------------------
+// PPB, IDLE, & debug-observability registers in VDE
+// --------------------------------------------------
+// This IDLE monitor is intended to count the number of cycles where
+// all of the NV_VDE_<submodule>'s are all idle. This information is
+// expected to be used by software to adjust the system clock and video
+// clock to optimal values.
+
+// Register ARVDE_PPB_IDLE_MON_0  
+#define ARVDE_PPB_IDLE_MON_0                    _MK_ADDR_CONST(0x2800)
+#define ARVDE_PPB_IDLE_MON_0_WORD_COUNT                         0x1
+#define ARVDE_PPB_IDLE_MON_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define ARVDE_PPB_IDLE_MON_0_RESET_MASK                         _MK_MASK_CONST(0xbfffffff)
+#define ARVDE_PPB_IDLE_MON_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define ARVDE_PPB_IDLE_MON_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define ARVDE_PPB_IDLE_MON_0_READ_MASK                  _MK_MASK_CONST(0xbfffffff)
+#define ARVDE_PPB_IDLE_MON_0_WRITE_MASK                         _MK_MASK_CONST(0xbfffffff)
+// read=1 means monitoring active. read=0 means monitoring inactive
+// write1 means start monitoring. write0 means stop monitoring.
+// monitor will also become inactive automatically if either
+// 1. sample period ends, or
+// 2. overflow is reached (in either indefinite sampling or sample-period mode).
+#define ARVDE_PPB_IDLE_MON_0_ENB_SHIFT                  _MK_SHIFT_CONST(31)
+#define ARVDE_PPB_IDLE_MON_0_ENB_FIELD                  (_MK_MASK_CONST(0x1) << ARVDE_PPB_IDLE_MON_0_ENB_SHIFT)
+#define ARVDE_PPB_IDLE_MON_0_ENB_RANGE                  31:31
+#define ARVDE_PPB_IDLE_MON_0_ENB_WOFFSET                        0x0
+#define ARVDE_PPB_IDLE_MON_0_ENB_DEFAULT                        _MK_MASK_CONST(0x0)
+#define ARVDE_PPB_IDLE_MON_0_ENB_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define ARVDE_PPB_IDLE_MON_0_ENB_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define ARVDE_PPB_IDLE_MON_0_ENB_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// read=1 means monitoring transitioned to inactive automically
+// because of cause 1 or 2 above.
+// write1 means clear this interrupt bit. write0 is ignored
+#define ARVDE_PPB_IDLE_MON_0_INT_STATUS_SHIFT                   _MK_SHIFT_CONST(29)
+#define ARVDE_PPB_IDLE_MON_0_INT_STATUS_FIELD                   (_MK_MASK_CONST(0x1) << ARVDE_PPB_IDLE_MON_0_INT_STATUS_SHIFT)
+#define ARVDE_PPB_IDLE_MON_0_INT_STATUS_RANGE                   29:29
+#define ARVDE_PPB_IDLE_MON_0_INT_STATUS_WOFFSET                 0x0
+#define ARVDE_PPB_IDLE_MON_0_INT_STATUS_DEFAULT                 _MK_MASK_CONST(0x0)
+#define ARVDE_PPB_IDLE_MON_0_INT_STATUS_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define ARVDE_PPB_IDLE_MON_0_INT_STATUS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define ARVDE_PPB_IDLE_MON_0_INT_STATUS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// 1 means indefinite/continous sampling
+// 0 means use SAMPLE_PERIOD for duration
+#define ARVDE_PPB_IDLE_MON_0_SAMPLE_MODE_SHIFT                  _MK_SHIFT_CONST(28)
+#define ARVDE_PPB_IDLE_MON_0_SAMPLE_MODE_FIELD                  (_MK_MASK_CONST(0x1) << ARVDE_PPB_IDLE_MON_0_SAMPLE_MODE_SHIFT)
+#define ARVDE_PPB_IDLE_MON_0_SAMPLE_MODE_RANGE                  28:28
+#define ARVDE_PPB_IDLE_MON_0_SAMPLE_MODE_WOFFSET                        0x0
+#define ARVDE_PPB_IDLE_MON_0_SAMPLE_MODE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define ARVDE_PPB_IDLE_MON_0_SAMPLE_MODE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define ARVDE_PPB_IDLE_MON_0_SAMPLE_MODE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define ARVDE_PPB_IDLE_MON_0_SAMPLE_MODE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// sample period in clock cycles. implemented as n+1, so that
+// "0" means sample period is 1 clock cycle
+#define ARVDE_PPB_IDLE_MON_0_SAMPLE_PERIOD_SHIFT                        _MK_SHIFT_CONST(3)
+#define ARVDE_PPB_IDLE_MON_0_SAMPLE_PERIOD_FIELD                        (_MK_MASK_CONST(0x1ffffff) << ARVDE_PPB_IDLE_MON_0_SAMPLE_PERIOD_SHIFT)
+#define ARVDE_PPB_IDLE_MON_0_SAMPLE_PERIOD_RANGE                        27:3
+#define ARVDE_PPB_IDLE_MON_0_SAMPLE_PERIOD_WOFFSET                      0x0
+#define ARVDE_PPB_IDLE_MON_0_SAMPLE_PERIOD_DEFAULT                      _MK_MASK_CONST(0x0)
+#define ARVDE_PPB_IDLE_MON_0_SAMPLE_PERIOD_DEFAULT_MASK                 _MK_MASK_CONST(0x1ffffff)
+#define ARVDE_PPB_IDLE_MON_0_SAMPLE_PERIOD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define ARVDE_PPB_IDLE_MON_0_SAMPLE_PERIOD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// power-of-2 encoding for # of required continously active IDLE cycles
+// before counting will start. 0 means don't use thresh, just count directly.
+// 1 means start counting after 1 continuous idle cycle  has  been observed. (if idle active for 10 clocks, count would be 9)
+// 2 means start counting after 2 continuous idle cycles have been observed. (if idle active for 10 clocks, count would be 8)
+// 3 means start counting after 4 continuous idle cycles have been observed. (if idle active for 10 clocks, count would be 6)
+#define ARVDE_PPB_IDLE_MON_0_THRESH_SHIFT                       _MK_SHIFT_CONST(0)
+#define ARVDE_PPB_IDLE_MON_0_THRESH_FIELD                       (_MK_MASK_CONST(0x7) << ARVDE_PPB_IDLE_MON_0_THRESH_SHIFT)
+#define ARVDE_PPB_IDLE_MON_0_THRESH_RANGE                       2:0
+#define ARVDE_PPB_IDLE_MON_0_THRESH_WOFFSET                     0x0
+#define ARVDE_PPB_IDLE_MON_0_THRESH_DEFAULT                     _MK_MASK_CONST(0x0)
+#define ARVDE_PPB_IDLE_MON_0_THRESH_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
+#define ARVDE_PPB_IDLE_MON_0_THRESH_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define ARVDE_PPB_IDLE_MON_0_THRESH_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register ARVDE_PPB_IDLE_STATUS_0  
+#define ARVDE_PPB_IDLE_STATUS_0                 _MK_ADDR_CONST(0x2804)
+#define ARVDE_PPB_IDLE_STATUS_0_WORD_COUNT                      0x1
+#define ARVDE_PPB_IDLE_STATUS_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define ARVDE_PPB_IDLE_STATUS_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define ARVDE_PPB_IDLE_STATUS_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define ARVDE_PPB_IDLE_STATUS_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define ARVDE_PPB_IDLE_STATUS_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define ARVDE_PPB_IDLE_STATUS_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
+// # of cycles of idle observed. value of 0xFFFF.FFFF indicates overflow
+// condition. COUNT will not stay at 0xFFFF.FFFF once overflow has been
+// detected. Value is cleared to 0 whenever VDE_IDLE_MON.ENB field is
+// written to 1 (see above register)
+#define ARVDE_PPB_IDLE_STATUS_0_COUNT_SHIFT                     _MK_SHIFT_CONST(0)
+#define ARVDE_PPB_IDLE_STATUS_0_COUNT_FIELD                     (_MK_MASK_CONST(0xffffffff) << ARVDE_PPB_IDLE_STATUS_0_COUNT_SHIFT)
+#define ARVDE_PPB_IDLE_STATUS_0_COUNT_RANGE                     31:0
+#define ARVDE_PPB_IDLE_STATUS_0_COUNT_WOFFSET                   0x0
+#define ARVDE_PPB_IDLE_STATUS_0_COUNT_DEFAULT                   _MK_MASK_CONST(0x0)
+#define ARVDE_PPB_IDLE_STATUS_0_COUNT_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define ARVDE_PPB_IDLE_STATUS_0_COUNT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define ARVDE_PPB_IDLE_STATUS_0_COUNT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Reserved address 10248 [0x2808] 
+
+// Reserved address 10252 [0x280c] 
+// This submodule IDLE monitor is intended measure the activity/idle status of a single selected VDE_<submodule>. 
+// Software can use these registers to measure the effectiveness of hardware controlled dynamic clock-enable
+// power-gating, or to profile submodule activity during a particular video stream or set of streams.
+
+// Register ARVDE_PPB_IDLE_SUBMOD_MON_0  
+#define ARVDE_PPB_IDLE_SUBMOD_MON_0                     _MK_ADDR_CONST(0x2810)
+#define ARVDE_PPB_IDLE_SUBMOD_MON_0_WORD_COUNT                  0x1
+#define ARVDE_PPB_IDLE_SUBMOD_MON_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define ARVDE_PPB_IDLE_SUBMOD_MON_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define ARVDE_PPB_IDLE_SUBMOD_MON_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define ARVDE_PPB_IDLE_SUBMOD_MON_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define ARVDE_PPB_IDLE_SUBMOD_MON_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define ARVDE_PPB_IDLE_SUBMOD_MON_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+// read=1 means monitoring active. read=0 means monitoring inactive
+// write1 means start monitoring. write0 means stop monitoring.
+// monitor will also become inactive automatically if either
+// 1. sample period ends, or
+// 2. overflow is reached in indefinite sampling mode.
+#define ARVDE_PPB_IDLE_SUBMOD_MON_0_ENB_SHIFT                   _MK_SHIFT_CONST(31)
+#define ARVDE_PPB_IDLE_SUBMOD_MON_0_ENB_FIELD                   (_MK_MASK_CONST(0x1) << ARVDE_PPB_IDLE_SUBMOD_MON_0_ENB_SHIFT)
+#define ARVDE_PPB_IDLE_SUBMOD_MON_0_ENB_RANGE                   31:31
+#define ARVDE_PPB_IDLE_SUBMOD_MON_0_ENB_WOFFSET                 0x0
+#define ARVDE_PPB_IDLE_SUBMOD_MON_0_ENB_DEFAULT                 _MK_MASK_CONST(0x0)
+#define ARVDE_PPB_IDLE_SUBMOD_MON_0_ENB_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define ARVDE_PPB_IDLE_SUBMOD_MON_0_ENB_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define ARVDE_PPB_IDLE_SUBMOD_MON_0_ENB_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// AND'd with INT_STATUS below for passing interrupt signal. 0=mask, 1=enable
+#define ARVDE_PPB_IDLE_SUBMOD_MON_0_INT_ENB_SHIFT                       _MK_SHIFT_CONST(30)
+#define ARVDE_PPB_IDLE_SUBMOD_MON_0_INT_ENB_FIELD                       (_MK_MASK_CONST(0x1) << ARVDE_PPB_IDLE_SUBMOD_MON_0_INT_ENB_SHIFT)
+#define ARVDE_PPB_IDLE_SUBMOD_MON_0_INT_ENB_RANGE                       30:30
+#define ARVDE_PPB_IDLE_SUBMOD_MON_0_INT_ENB_WOFFSET                     0x0
+#define ARVDE_PPB_IDLE_SUBMOD_MON_0_INT_ENB_DEFAULT                     _MK_MASK_CONST(0x0)
+#define ARVDE_PPB_IDLE_SUBMOD_MON_0_INT_ENB_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define ARVDE_PPB_IDLE_SUBMOD_MON_0_INT_ENB_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define ARVDE_PPB_IDLE_SUBMOD_MON_0_INT_ENB_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// read=1 means monitoring transitioned to inactive automically
+// because of one of the two causes above.
+// write1 means clear this interrupt bit. write0 is ignored
+#define ARVDE_PPB_IDLE_SUBMOD_MON_0_INT_STATUS_SHIFT                    _MK_SHIFT_CONST(29)
+#define ARVDE_PPB_IDLE_SUBMOD_MON_0_INT_STATUS_FIELD                    (_MK_MASK_CONST(0x1) << ARVDE_PPB_IDLE_SUBMOD_MON_0_INT_STATUS_SHIFT)
+#define ARVDE_PPB_IDLE_SUBMOD_MON_0_INT_STATUS_RANGE                    29:29
+#define ARVDE_PPB_IDLE_SUBMOD_MON_0_INT_STATUS_WOFFSET                  0x0
+#define ARVDE_PPB_IDLE_SUBMOD_MON_0_INT_STATUS_DEFAULT                  _MK_MASK_CONST(0x0)
+#define ARVDE_PPB_IDLE_SUBMOD_MON_0_INT_STATUS_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define ARVDE_PPB_IDLE_SUBMOD_MON_0_INT_STATUS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define ARVDE_PPB_IDLE_SUBMOD_MON_0_INT_STATUS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// 1 means indefinite/continous sampling
+// 0 means use SAMPLE_PERIOD for duration
+#define ARVDE_PPB_IDLE_SUBMOD_MON_0_SAMPLE_MODE_SHIFT                   _MK_SHIFT_CONST(28)
+#define ARVDE_PPB_IDLE_SUBMOD_MON_0_SAMPLE_MODE_FIELD                   (_MK_MASK_CONST(0x1) << ARVDE_PPB_IDLE_SUBMOD_MON_0_SAMPLE_MODE_SHIFT)
+#define ARVDE_PPB_IDLE_SUBMOD_MON_0_SAMPLE_MODE_RANGE                   28:28
+#define ARVDE_PPB_IDLE_SUBMOD_MON_0_SAMPLE_MODE_WOFFSET                 0x0
+#define ARVDE_PPB_IDLE_SUBMOD_MON_0_SAMPLE_MODE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define ARVDE_PPB_IDLE_SUBMOD_MON_0_SAMPLE_MODE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define ARVDE_PPB_IDLE_SUBMOD_MON_0_SAMPLE_MODE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define ARVDE_PPB_IDLE_SUBMOD_MON_0_SAMPLE_MODE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// sample period in clock cycles. implemented as n+1, so that
+// "0" means sample period is 1 clock cycle
+#define ARVDE_PPB_IDLE_SUBMOD_MON_0_SAMPLE_PERIOD_SHIFT                 _MK_SHIFT_CONST(3)
+#define ARVDE_PPB_IDLE_SUBMOD_MON_0_SAMPLE_PERIOD_FIELD                 (_MK_MASK_CONST(0x1ffffff) << ARVDE_PPB_IDLE_SUBMOD_MON_0_SAMPLE_PERIOD_SHIFT)
+#define ARVDE_PPB_IDLE_SUBMOD_MON_0_SAMPLE_PERIOD_RANGE                 27:3
+#define ARVDE_PPB_IDLE_SUBMOD_MON_0_SAMPLE_PERIOD_WOFFSET                       0x0
+#define ARVDE_PPB_IDLE_SUBMOD_MON_0_SAMPLE_PERIOD_DEFAULT                       _MK_MASK_CONST(0x0)
+#define ARVDE_PPB_IDLE_SUBMOD_MON_0_SAMPLE_PERIOD_DEFAULT_MASK                  _MK_MASK_CONST(0x1ffffff)
+#define ARVDE_PPB_IDLE_SUBMOD_MON_0_SAMPLE_PERIOD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define ARVDE_PPB_IDLE_SUBMOD_MON_0_SAMPLE_PERIOD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// power-of-2 encoding for # of required continously active IDLE cycles
+// before counting will start.
+#define ARVDE_PPB_IDLE_SUBMOD_MON_0_THRESH_SHIFT                        _MK_SHIFT_CONST(0)
+#define ARVDE_PPB_IDLE_SUBMOD_MON_0_THRESH_FIELD                        (_MK_MASK_CONST(0x7) << ARVDE_PPB_IDLE_SUBMOD_MON_0_THRESH_SHIFT)
+#define ARVDE_PPB_IDLE_SUBMOD_MON_0_THRESH_RANGE                        2:0
+#define ARVDE_PPB_IDLE_SUBMOD_MON_0_THRESH_WOFFSET                      0x0
+#define ARVDE_PPB_IDLE_SUBMOD_MON_0_THRESH_DEFAULT                      _MK_MASK_CONST(0x0)
+#define ARVDE_PPB_IDLE_SUBMOD_MON_0_THRESH_DEFAULT_MASK                 _MK_MASK_CONST(0x7)
+#define ARVDE_PPB_IDLE_SUBMOD_MON_0_THRESH_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define ARVDE_PPB_IDLE_SUBMOD_MON_0_THRESH_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register ARVDE_PPB_IDLE_SUBMOD_STATUS_0  
+#define ARVDE_PPB_IDLE_SUBMOD_STATUS_0                  _MK_ADDR_CONST(0x2814)
+#define ARVDE_PPB_IDLE_SUBMOD_STATUS_0_WORD_COUNT                       0x1
+#define ARVDE_PPB_IDLE_SUBMOD_STATUS_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define ARVDE_PPB_IDLE_SUBMOD_STATUS_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
+#define ARVDE_PPB_IDLE_SUBMOD_STATUS_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define ARVDE_PPB_IDLE_SUBMOD_STATUS_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define ARVDE_PPB_IDLE_SUBMOD_STATUS_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define ARVDE_PPB_IDLE_SUBMOD_STATUS_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
+// # of cycles of idle observed. value of 0xFFFF.FFFF indicates overflow
+// condition. COUNT will not stay at 0xFFFF.FFFF once overflow has been
+// detected. Value is cleared to 0 whenever VDE_IDLE_MON.ENB field is
+// written to 1 (see above register)
+#define ARVDE_PPB_IDLE_SUBMOD_STATUS_0_COUNT_SHIFT                      _MK_SHIFT_CONST(0)
+#define ARVDE_PPB_IDLE_SUBMOD_STATUS_0_COUNT_FIELD                      (_MK_MASK_CONST(0xffffffff) << ARVDE_PPB_IDLE_SUBMOD_STATUS_0_COUNT_SHIFT)
+#define ARVDE_PPB_IDLE_SUBMOD_STATUS_0_COUNT_RANGE                      31:0
+#define ARVDE_PPB_IDLE_SUBMOD_STATUS_0_COUNT_WOFFSET                    0x0
+#define ARVDE_PPB_IDLE_SUBMOD_STATUS_0_COUNT_DEFAULT                    _MK_MASK_CONST(0x0)
+#define ARVDE_PPB_IDLE_SUBMOD_STATUS_0_COUNT_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
+#define ARVDE_PPB_IDLE_SUBMOD_STATUS_0_COUNT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define ARVDE_PPB_IDLE_SUBMOD_STATUS_0_COUNT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register ARVDE_PPB_IDLE_SUBMOD_SELECT_0  
+#define ARVDE_PPB_IDLE_SUBMOD_SELECT_0                  _MK_ADDR_CONST(0x2818)
+#define ARVDE_PPB_IDLE_SUBMOD_SELECT_0_WORD_COUNT                       0x1
+#define ARVDE_PPB_IDLE_SUBMOD_SELECT_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define ARVDE_PPB_IDLE_SUBMOD_SELECT_0_RESET_MASK                       _MK_MASK_CONST(0x7)
+#define ARVDE_PPB_IDLE_SUBMOD_SELECT_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define ARVDE_PPB_IDLE_SUBMOD_SELECT_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define ARVDE_PPB_IDLE_SUBMOD_SELECT_0_READ_MASK                        _MK_MASK_CONST(0x7)
+#define ARVDE_PPB_IDLE_SUBMOD_SELECT_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
+// 0=SXE, 1=BSEV, 2=TFE, 3=MBE, 4=MCE, 5=PPE, others=RESERVED
+#define ARVDE_PPB_IDLE_SUBMOD_SELECT_0_MODULE_SHIFT                     _MK_SHIFT_CONST(0)
+#define ARVDE_PPB_IDLE_SUBMOD_SELECT_0_MODULE_FIELD                     (_MK_MASK_CONST(0x7) << ARVDE_PPB_IDLE_SUBMOD_SELECT_0_MODULE_SHIFT)
+#define ARVDE_PPB_IDLE_SUBMOD_SELECT_0_MODULE_RANGE                     2:0
+#define ARVDE_PPB_IDLE_SUBMOD_SELECT_0_MODULE_WOFFSET                   0x0
+#define ARVDE_PPB_IDLE_SUBMOD_SELECT_0_MODULE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define ARVDE_PPB_IDLE_SUBMOD_SELECT_0_MODULE_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define ARVDE_PPB_IDLE_SUBMOD_SELECT_0_MODULE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define ARVDE_PPB_IDLE_SUBMOD_SELECT_0_MODULE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#endif // ifndef ___ARVDE_MON_H_INC_
+
diff --git a/arch/arm/mach-tegra/include/ap15/arvi.h b/arch/arm/mach-tegra/include/ap15/arvi.h
new file mode 100644
index 000000000000..bc9d9244844c
--- /dev/null
+++ b/arch/arm/mach-tegra/include/ap15/arvi.h
@@ -0,0 +1,13401 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+//
+// DO NOT EDIT - generated by simspec!
+//
+
+#ifndef ___ARVI_H_INC_
+#define ___ARVI_H_INC_
+#define NV_VI_OUT_1_INCR_SYNCPT_NB_CONDS        5
+
+// Register VI_OUT_1_INCR_SYNCPT_0  
+#define VI_OUT_1_INCR_SYNCPT_0                  _MK_ADDR_CONST(0x0)
+#define VI_OUT_1_INCR_SYNCPT_0_WORD_COUNT                       0x1
+#define VI_OUT_1_INCR_SYNCPT_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define VI_OUT_1_INCR_SYNCPT_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
+#define VI_OUT_1_INCR_SYNCPT_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define VI_OUT_1_INCR_SYNCPT_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_OUT_1_INCR_SYNCPT_0_READ_MASK                        _MK_MASK_CONST(0xffff)
+#define VI_OUT_1_INCR_SYNCPT_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
+// Condition mapped from raise/wait
+#define VI_OUT_1_INCR_SYNCPT_0_OUT_1_COND_SHIFT                 _MK_SHIFT_CONST(8)
+#define VI_OUT_1_INCR_SYNCPT_0_OUT_1_COND_FIELD                 (_MK_MASK_CONST(0xff) << VI_OUT_1_INCR_SYNCPT_0_OUT_1_COND_SHIFT)
+#define VI_OUT_1_INCR_SYNCPT_0_OUT_1_COND_RANGE                 15:8
+#define VI_OUT_1_INCR_SYNCPT_0_OUT_1_COND_WOFFSET                       0x0
+#define VI_OUT_1_INCR_SYNCPT_0_OUT_1_COND_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_OUT_1_INCR_SYNCPT_0_OUT_1_COND_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define VI_OUT_1_INCR_SYNCPT_0_OUT_1_COND_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_OUT_1_INCR_SYNCPT_0_OUT_1_COND_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_OUT_1_INCR_SYNCPT_0_OUT_1_COND_IMMEDIATE                     _MK_ENUM_CONST(0)
+#define VI_OUT_1_INCR_SYNCPT_0_OUT_1_COND_OP_DONE                       _MK_ENUM_CONST(1)
+#define VI_OUT_1_INCR_SYNCPT_0_OUT_1_COND_RD_DONE                       _MK_ENUM_CONST(2)
+#define VI_OUT_1_INCR_SYNCPT_0_OUT_1_COND_REG_WR_SAFE                   _MK_ENUM_CONST(3)
+#define VI_OUT_1_INCR_SYNCPT_0_OUT_1_COND_START_WRITE                   _MK_ENUM_CONST(4)
+#define VI_OUT_1_INCR_SYNCPT_0_OUT_1_COND_COND_5                        _MK_ENUM_CONST(5)
+#define VI_OUT_1_INCR_SYNCPT_0_OUT_1_COND_COND_6                        _MK_ENUM_CONST(6)
+#define VI_OUT_1_INCR_SYNCPT_0_OUT_1_COND_COND_7                        _MK_ENUM_CONST(7)
+#define VI_OUT_1_INCR_SYNCPT_0_OUT_1_COND_COND_8                        _MK_ENUM_CONST(8)
+#define VI_OUT_1_INCR_SYNCPT_0_OUT_1_COND_COND_9                        _MK_ENUM_CONST(9)
+#define VI_OUT_1_INCR_SYNCPT_0_OUT_1_COND_COND_10                       _MK_ENUM_CONST(10)
+#define VI_OUT_1_INCR_SYNCPT_0_OUT_1_COND_COND_11                       _MK_ENUM_CONST(11)
+#define VI_OUT_1_INCR_SYNCPT_0_OUT_1_COND_COND_12                       _MK_ENUM_CONST(12)
+#define VI_OUT_1_INCR_SYNCPT_0_OUT_1_COND_COND_13                       _MK_ENUM_CONST(13)
+#define VI_OUT_1_INCR_SYNCPT_0_OUT_1_COND_COND_14                       _MK_ENUM_CONST(14)
+#define VI_OUT_1_INCR_SYNCPT_0_OUT_1_COND_COND_15                       _MK_ENUM_CONST(15)
+
+// syncpt index value
+#define VI_OUT_1_INCR_SYNCPT_0_OUT_1_INDX_SHIFT                 _MK_SHIFT_CONST(0)
+#define VI_OUT_1_INCR_SYNCPT_0_OUT_1_INDX_FIELD                 (_MK_MASK_CONST(0xff) << VI_OUT_1_INCR_SYNCPT_0_OUT_1_INDX_SHIFT)
+#define VI_OUT_1_INCR_SYNCPT_0_OUT_1_INDX_RANGE                 7:0
+#define VI_OUT_1_INCR_SYNCPT_0_OUT_1_INDX_WOFFSET                       0x0
+#define VI_OUT_1_INCR_SYNCPT_0_OUT_1_INDX_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_OUT_1_INCR_SYNCPT_0_OUT_1_INDX_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define VI_OUT_1_INCR_SYNCPT_0_OUT_1_INDX_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_OUT_1_INCR_SYNCPT_0_OUT_1_INDX_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register VI_OUT_1_INCR_SYNCPT_CNTRL_0  
+#define VI_OUT_1_INCR_SYNCPT_CNTRL_0                    _MK_ADDR_CONST(0x1)
+#define VI_OUT_1_INCR_SYNCPT_CNTRL_0_WORD_COUNT                         0x1
+#define VI_OUT_1_INCR_SYNCPT_CNTRL_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define VI_OUT_1_INCR_SYNCPT_CNTRL_0_RESET_MASK                         _MK_MASK_CONST(0x101)
+#define VI_OUT_1_INCR_SYNCPT_CNTRL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define VI_OUT_1_INCR_SYNCPT_CNTRL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_OUT_1_INCR_SYNCPT_CNTRL_0_READ_MASK                  _MK_MASK_CONST(0x101)
+#define VI_OUT_1_INCR_SYNCPT_CNTRL_0_WRITE_MASK                         _MK_MASK_CONST(0x101)
+// If NO_STALL is 1, then when fifos are full,
+// INCR_SYNCPT methods will be dropped and the
+// INCR_SYNCPT_ERROR[COND] bit will be set.
+// If NO_STALL is 0, then when fifos are full,
+// the client host interface will be stalled.
+#define VI_OUT_1_INCR_SYNCPT_CNTRL_0_OUT_1_INCR_SYNCPT_NO_STALL_SHIFT                   _MK_SHIFT_CONST(8)
+#define VI_OUT_1_INCR_SYNCPT_CNTRL_0_OUT_1_INCR_SYNCPT_NO_STALL_FIELD                   (_MK_MASK_CONST(0x1) << VI_OUT_1_INCR_SYNCPT_CNTRL_0_OUT_1_INCR_SYNCPT_NO_STALL_SHIFT)
+#define VI_OUT_1_INCR_SYNCPT_CNTRL_0_OUT_1_INCR_SYNCPT_NO_STALL_RANGE                   8:8
+#define VI_OUT_1_INCR_SYNCPT_CNTRL_0_OUT_1_INCR_SYNCPT_NO_STALL_WOFFSET                 0x0
+#define VI_OUT_1_INCR_SYNCPT_CNTRL_0_OUT_1_INCR_SYNCPT_NO_STALL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_OUT_1_INCR_SYNCPT_CNTRL_0_OUT_1_INCR_SYNCPT_NO_STALL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define VI_OUT_1_INCR_SYNCPT_CNTRL_0_OUT_1_INCR_SYNCPT_NO_STALL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_OUT_1_INCR_SYNCPT_CNTRL_0_OUT_1_INCR_SYNCPT_NO_STALL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// If SOFT_RESET is set, then all internal state
+// of the client syncpt block will be reset.
+// To do soft reset, first set SOFT_RESET of
+// all host1x clients affected, then clear all
+// SOFT_RESETs.
+#define VI_OUT_1_INCR_SYNCPT_CNTRL_0_OUT_1_INCR_SYNCPT_SOFT_RESET_SHIFT                 _MK_SHIFT_CONST(0)
+#define VI_OUT_1_INCR_SYNCPT_CNTRL_0_OUT_1_INCR_SYNCPT_SOFT_RESET_FIELD                 (_MK_MASK_CONST(0x1) << VI_OUT_1_INCR_SYNCPT_CNTRL_0_OUT_1_INCR_SYNCPT_SOFT_RESET_SHIFT)
+#define VI_OUT_1_INCR_SYNCPT_CNTRL_0_OUT_1_INCR_SYNCPT_SOFT_RESET_RANGE                 0:0
+#define VI_OUT_1_INCR_SYNCPT_CNTRL_0_OUT_1_INCR_SYNCPT_SOFT_RESET_WOFFSET                       0x0
+#define VI_OUT_1_INCR_SYNCPT_CNTRL_0_OUT_1_INCR_SYNCPT_SOFT_RESET_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_OUT_1_INCR_SYNCPT_CNTRL_0_OUT_1_INCR_SYNCPT_SOFT_RESET_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define VI_OUT_1_INCR_SYNCPT_CNTRL_0_OUT_1_INCR_SYNCPT_SOFT_RESET_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_OUT_1_INCR_SYNCPT_CNTRL_0_OUT_1_INCR_SYNCPT_SOFT_RESET_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register VI_OUT_1_INCR_SYNCPT_ERROR_0  
+#define VI_OUT_1_INCR_SYNCPT_ERROR_0                    _MK_ADDR_CONST(0x2)
+#define VI_OUT_1_INCR_SYNCPT_ERROR_0_WORD_COUNT                         0x1
+#define VI_OUT_1_INCR_SYNCPT_ERROR_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define VI_OUT_1_INCR_SYNCPT_ERROR_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define VI_OUT_1_INCR_SYNCPT_ERROR_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define VI_OUT_1_INCR_SYNCPT_ERROR_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_OUT_1_INCR_SYNCPT_ERROR_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define VI_OUT_1_INCR_SYNCPT_ERROR_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+// COND_STATUS[COND] is set if the fifo for COND overflows.
+// This bit is sticky and will remain set until cleared.
+// Cleared by writing 1.
+#define VI_OUT_1_INCR_SYNCPT_ERROR_0_OUT_1_COND_STATUS_SHIFT                    _MK_SHIFT_CONST(0)
+#define VI_OUT_1_INCR_SYNCPT_ERROR_0_OUT_1_COND_STATUS_FIELD                    (_MK_MASK_CONST(0xffffffff) << VI_OUT_1_INCR_SYNCPT_ERROR_0_OUT_1_COND_STATUS_SHIFT)
+#define VI_OUT_1_INCR_SYNCPT_ERROR_0_OUT_1_COND_STATUS_RANGE                    31:0
+#define VI_OUT_1_INCR_SYNCPT_ERROR_0_OUT_1_COND_STATUS_WOFFSET                  0x0
+#define VI_OUT_1_INCR_SYNCPT_ERROR_0_OUT_1_COND_STATUS_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_OUT_1_INCR_SYNCPT_ERROR_0_OUT_1_COND_STATUS_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_OUT_1_INCR_SYNCPT_ERROR_0_OUT_1_COND_STATUS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_OUT_1_INCR_SYNCPT_ERROR_0_OUT_1_COND_STATUS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Reserved address 3 [0x3] 
+
+// Reserved address 4 [0x4] 
+
+// Reserved address 5 [0x5] 
+
+// Reserved address 6 [0x6] 
+
+// Reserved address 7 [0x7] 
+#define NV_VI_OUT_2_INCR_SYNCPT_NB_CONDS        5
+
+// Register VI_OUT_2_INCR_SYNCPT_0  
+#define VI_OUT_2_INCR_SYNCPT_0                  _MK_ADDR_CONST(0x8)
+#define VI_OUT_2_INCR_SYNCPT_0_WORD_COUNT                       0x1
+#define VI_OUT_2_INCR_SYNCPT_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define VI_OUT_2_INCR_SYNCPT_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
+#define VI_OUT_2_INCR_SYNCPT_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define VI_OUT_2_INCR_SYNCPT_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_OUT_2_INCR_SYNCPT_0_READ_MASK                        _MK_MASK_CONST(0xffff)
+#define VI_OUT_2_INCR_SYNCPT_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
+// Condition mapped from raise/wait
+#define VI_OUT_2_INCR_SYNCPT_0_OUT_2_COND_SHIFT                 _MK_SHIFT_CONST(8)
+#define VI_OUT_2_INCR_SYNCPT_0_OUT_2_COND_FIELD                 (_MK_MASK_CONST(0xff) << VI_OUT_2_INCR_SYNCPT_0_OUT_2_COND_SHIFT)
+#define VI_OUT_2_INCR_SYNCPT_0_OUT_2_COND_RANGE                 15:8
+#define VI_OUT_2_INCR_SYNCPT_0_OUT_2_COND_WOFFSET                       0x0
+#define VI_OUT_2_INCR_SYNCPT_0_OUT_2_COND_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_OUT_2_INCR_SYNCPT_0_OUT_2_COND_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define VI_OUT_2_INCR_SYNCPT_0_OUT_2_COND_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_OUT_2_INCR_SYNCPT_0_OUT_2_COND_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_OUT_2_INCR_SYNCPT_0_OUT_2_COND_IMMEDIATE                     _MK_ENUM_CONST(0)
+#define VI_OUT_2_INCR_SYNCPT_0_OUT_2_COND_OP_DONE                       _MK_ENUM_CONST(1)
+#define VI_OUT_2_INCR_SYNCPT_0_OUT_2_COND_RD_DONE                       _MK_ENUM_CONST(2)
+#define VI_OUT_2_INCR_SYNCPT_0_OUT_2_COND_REG_WR_SAFE                   _MK_ENUM_CONST(3)
+#define VI_OUT_2_INCR_SYNCPT_0_OUT_2_COND_START_WRITE                   _MK_ENUM_CONST(4)
+#define VI_OUT_2_INCR_SYNCPT_0_OUT_2_COND_COND_5                        _MK_ENUM_CONST(5)
+#define VI_OUT_2_INCR_SYNCPT_0_OUT_2_COND_COND_6                        _MK_ENUM_CONST(6)
+#define VI_OUT_2_INCR_SYNCPT_0_OUT_2_COND_COND_7                        _MK_ENUM_CONST(7)
+#define VI_OUT_2_INCR_SYNCPT_0_OUT_2_COND_COND_8                        _MK_ENUM_CONST(8)
+#define VI_OUT_2_INCR_SYNCPT_0_OUT_2_COND_COND_9                        _MK_ENUM_CONST(9)
+#define VI_OUT_2_INCR_SYNCPT_0_OUT_2_COND_COND_10                       _MK_ENUM_CONST(10)
+#define VI_OUT_2_INCR_SYNCPT_0_OUT_2_COND_COND_11                       _MK_ENUM_CONST(11)
+#define VI_OUT_2_INCR_SYNCPT_0_OUT_2_COND_COND_12                       _MK_ENUM_CONST(12)
+#define VI_OUT_2_INCR_SYNCPT_0_OUT_2_COND_COND_13                       _MK_ENUM_CONST(13)
+#define VI_OUT_2_INCR_SYNCPT_0_OUT_2_COND_COND_14                       _MK_ENUM_CONST(14)
+#define VI_OUT_2_INCR_SYNCPT_0_OUT_2_COND_COND_15                       _MK_ENUM_CONST(15)
+
+// syncpt index value
+#define VI_OUT_2_INCR_SYNCPT_0_OUT_2_INDX_SHIFT                 _MK_SHIFT_CONST(0)
+#define VI_OUT_2_INCR_SYNCPT_0_OUT_2_INDX_FIELD                 (_MK_MASK_CONST(0xff) << VI_OUT_2_INCR_SYNCPT_0_OUT_2_INDX_SHIFT)
+#define VI_OUT_2_INCR_SYNCPT_0_OUT_2_INDX_RANGE                 7:0
+#define VI_OUT_2_INCR_SYNCPT_0_OUT_2_INDX_WOFFSET                       0x0
+#define VI_OUT_2_INCR_SYNCPT_0_OUT_2_INDX_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_OUT_2_INCR_SYNCPT_0_OUT_2_INDX_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define VI_OUT_2_INCR_SYNCPT_0_OUT_2_INDX_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_OUT_2_INCR_SYNCPT_0_OUT_2_INDX_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register VI_OUT_2_INCR_SYNCPT_CNTRL_0  
+#define VI_OUT_2_INCR_SYNCPT_CNTRL_0                    _MK_ADDR_CONST(0x9)
+#define VI_OUT_2_INCR_SYNCPT_CNTRL_0_WORD_COUNT                         0x1
+#define VI_OUT_2_INCR_SYNCPT_CNTRL_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define VI_OUT_2_INCR_SYNCPT_CNTRL_0_RESET_MASK                         _MK_MASK_CONST(0x101)
+#define VI_OUT_2_INCR_SYNCPT_CNTRL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define VI_OUT_2_INCR_SYNCPT_CNTRL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_OUT_2_INCR_SYNCPT_CNTRL_0_READ_MASK                  _MK_MASK_CONST(0x101)
+#define VI_OUT_2_INCR_SYNCPT_CNTRL_0_WRITE_MASK                         _MK_MASK_CONST(0x101)
+// If NO_STALL is 1, then when fifos are full,
+// INCR_SYNCPT methods will be dropped and the
+// INCR_SYNCPT_ERROR[COND] bit will be set.
+// If NO_STALL is 0, then when fifos are full,
+// the client host interface will be stalled.
+#define VI_OUT_2_INCR_SYNCPT_CNTRL_0_OUT_2_INCR_SYNCPT_NO_STALL_SHIFT                   _MK_SHIFT_CONST(8)
+#define VI_OUT_2_INCR_SYNCPT_CNTRL_0_OUT_2_INCR_SYNCPT_NO_STALL_FIELD                   (_MK_MASK_CONST(0x1) << VI_OUT_2_INCR_SYNCPT_CNTRL_0_OUT_2_INCR_SYNCPT_NO_STALL_SHIFT)
+#define VI_OUT_2_INCR_SYNCPT_CNTRL_0_OUT_2_INCR_SYNCPT_NO_STALL_RANGE                   8:8
+#define VI_OUT_2_INCR_SYNCPT_CNTRL_0_OUT_2_INCR_SYNCPT_NO_STALL_WOFFSET                 0x0
+#define VI_OUT_2_INCR_SYNCPT_CNTRL_0_OUT_2_INCR_SYNCPT_NO_STALL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_OUT_2_INCR_SYNCPT_CNTRL_0_OUT_2_INCR_SYNCPT_NO_STALL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define VI_OUT_2_INCR_SYNCPT_CNTRL_0_OUT_2_INCR_SYNCPT_NO_STALL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_OUT_2_INCR_SYNCPT_CNTRL_0_OUT_2_INCR_SYNCPT_NO_STALL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// If SOFT_RESET is set, then all internal state
+// of the client syncpt block will be reset.
+// To do soft reset, first set SOFT_RESET of
+// all host1x clients affected, then clear all
+// SOFT_RESETs.
+#define VI_OUT_2_INCR_SYNCPT_CNTRL_0_OUT_2_INCR_SYNCPT_SOFT_RESET_SHIFT                 _MK_SHIFT_CONST(0)
+#define VI_OUT_2_INCR_SYNCPT_CNTRL_0_OUT_2_INCR_SYNCPT_SOFT_RESET_FIELD                 (_MK_MASK_CONST(0x1) << VI_OUT_2_INCR_SYNCPT_CNTRL_0_OUT_2_INCR_SYNCPT_SOFT_RESET_SHIFT)
+#define VI_OUT_2_INCR_SYNCPT_CNTRL_0_OUT_2_INCR_SYNCPT_SOFT_RESET_RANGE                 0:0
+#define VI_OUT_2_INCR_SYNCPT_CNTRL_0_OUT_2_INCR_SYNCPT_SOFT_RESET_WOFFSET                       0x0
+#define VI_OUT_2_INCR_SYNCPT_CNTRL_0_OUT_2_INCR_SYNCPT_SOFT_RESET_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_OUT_2_INCR_SYNCPT_CNTRL_0_OUT_2_INCR_SYNCPT_SOFT_RESET_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define VI_OUT_2_INCR_SYNCPT_CNTRL_0_OUT_2_INCR_SYNCPT_SOFT_RESET_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_OUT_2_INCR_SYNCPT_CNTRL_0_OUT_2_INCR_SYNCPT_SOFT_RESET_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register VI_OUT_2_INCR_SYNCPT_ERROR_0  
+#define VI_OUT_2_INCR_SYNCPT_ERROR_0                    _MK_ADDR_CONST(0xa)
+#define VI_OUT_2_INCR_SYNCPT_ERROR_0_WORD_COUNT                         0x1
+#define VI_OUT_2_INCR_SYNCPT_ERROR_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define VI_OUT_2_INCR_SYNCPT_ERROR_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define VI_OUT_2_INCR_SYNCPT_ERROR_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define VI_OUT_2_INCR_SYNCPT_ERROR_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_OUT_2_INCR_SYNCPT_ERROR_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define VI_OUT_2_INCR_SYNCPT_ERROR_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+// COND_STATUS[COND] is set if the fifo for COND overflows.
+// This bit is sticky and will remain set until cleared.
+// Cleared by writing 1.
+#define VI_OUT_2_INCR_SYNCPT_ERROR_0_OUT_2_COND_STATUS_SHIFT                    _MK_SHIFT_CONST(0)
+#define VI_OUT_2_INCR_SYNCPT_ERROR_0_OUT_2_COND_STATUS_FIELD                    (_MK_MASK_CONST(0xffffffff) << VI_OUT_2_INCR_SYNCPT_ERROR_0_OUT_2_COND_STATUS_SHIFT)
+#define VI_OUT_2_INCR_SYNCPT_ERROR_0_OUT_2_COND_STATUS_RANGE                    31:0
+#define VI_OUT_2_INCR_SYNCPT_ERROR_0_OUT_2_COND_STATUS_WOFFSET                  0x0
+#define VI_OUT_2_INCR_SYNCPT_ERROR_0_OUT_2_COND_STATUS_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_OUT_2_INCR_SYNCPT_ERROR_0_OUT_2_COND_STATUS_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_OUT_2_INCR_SYNCPT_ERROR_0_OUT_2_COND_STATUS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_OUT_2_INCR_SYNCPT_ERROR_0_OUT_2_COND_STATUS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Reserved address 11 [0xb] 
+
+// Reserved address 12 [0xc] 
+
+// Reserved address 13 [0xd] 
+
+// Reserved address 14 [0xe] 
+
+// Reserved address 15 [0xf] 
+#define NV_VI_MISC_INCR_SYNCPT_NB_CONDS 9
+
+// Register VI_MISC_INCR_SYNCPT_0  
+#define VI_MISC_INCR_SYNCPT_0                   _MK_ADDR_CONST(0x10)
+#define VI_MISC_INCR_SYNCPT_0_WORD_COUNT                        0x1
+#define VI_MISC_INCR_SYNCPT_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define VI_MISC_INCR_SYNCPT_0_RESET_MASK                        _MK_MASK_CONST(0xffff)
+#define VI_MISC_INCR_SYNCPT_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define VI_MISC_INCR_SYNCPT_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_MISC_INCR_SYNCPT_0_READ_MASK                         _MK_MASK_CONST(0xffff)
+#define VI_MISC_INCR_SYNCPT_0_WRITE_MASK                        _MK_MASK_CONST(0xffff)
+// Condition mapped from raise/wait
+#define VI_MISC_INCR_SYNCPT_0_MISC_COND_SHIFT                   _MK_SHIFT_CONST(8)
+#define VI_MISC_INCR_SYNCPT_0_MISC_COND_FIELD                   (_MK_MASK_CONST(0xff) << VI_MISC_INCR_SYNCPT_0_MISC_COND_SHIFT)
+#define VI_MISC_INCR_SYNCPT_0_MISC_COND_RANGE                   15:8
+#define VI_MISC_INCR_SYNCPT_0_MISC_COND_WOFFSET                 0x0
+#define VI_MISC_INCR_SYNCPT_0_MISC_COND_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_MISC_INCR_SYNCPT_0_MISC_COND_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define VI_MISC_INCR_SYNCPT_0_MISC_COND_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_MISC_INCR_SYNCPT_0_MISC_COND_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_MISC_INCR_SYNCPT_0_MISC_COND_IMMEDIATE                       _MK_ENUM_CONST(0)
+#define VI_MISC_INCR_SYNCPT_0_MISC_COND_OP_DONE                 _MK_ENUM_CONST(1)
+#define VI_MISC_INCR_SYNCPT_0_MISC_COND_RD_DONE                 _MK_ENUM_CONST(2)
+#define VI_MISC_INCR_SYNCPT_0_MISC_COND_REG_WR_SAFE                     _MK_ENUM_CONST(3)
+#define VI_MISC_INCR_SYNCPT_0_MISC_COND_MISC_VIP_VSYNC                  _MK_ENUM_CONST(4)
+#define VI_MISC_INCR_SYNCPT_0_MISC_COND_MISC_CSI_PPA_FRAME_START                        _MK_ENUM_CONST(5)
+#define VI_MISC_INCR_SYNCPT_0_MISC_COND_MISC_CSI_PPA_FRAME_END                  _MK_ENUM_CONST(6)
+#define VI_MISC_INCR_SYNCPT_0_MISC_COND_MISC_CSI_PPB_FRAME_START                        _MK_ENUM_CONST(7)
+#define VI_MISC_INCR_SYNCPT_0_MISC_COND_MISC_CSI_PPB_FRAME_END                  _MK_ENUM_CONST(8)
+#define VI_MISC_INCR_SYNCPT_0_MISC_COND_COND_9                  _MK_ENUM_CONST(9)
+#define VI_MISC_INCR_SYNCPT_0_MISC_COND_COND_10                 _MK_ENUM_CONST(10)
+#define VI_MISC_INCR_SYNCPT_0_MISC_COND_COND_11                 _MK_ENUM_CONST(11)
+#define VI_MISC_INCR_SYNCPT_0_MISC_COND_COND_12                 _MK_ENUM_CONST(12)
+#define VI_MISC_INCR_SYNCPT_0_MISC_COND_COND_13                 _MK_ENUM_CONST(13)
+#define VI_MISC_INCR_SYNCPT_0_MISC_COND_COND_14                 _MK_ENUM_CONST(14)
+#define VI_MISC_INCR_SYNCPT_0_MISC_COND_COND_15                 _MK_ENUM_CONST(15)
+
+// syncpt index value
+#define VI_MISC_INCR_SYNCPT_0_MISC_INDX_SHIFT                   _MK_SHIFT_CONST(0)
+#define VI_MISC_INCR_SYNCPT_0_MISC_INDX_FIELD                   (_MK_MASK_CONST(0xff) << VI_MISC_INCR_SYNCPT_0_MISC_INDX_SHIFT)
+#define VI_MISC_INCR_SYNCPT_0_MISC_INDX_RANGE                   7:0
+#define VI_MISC_INCR_SYNCPT_0_MISC_INDX_WOFFSET                 0x0
+#define VI_MISC_INCR_SYNCPT_0_MISC_INDX_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_MISC_INCR_SYNCPT_0_MISC_INDX_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define VI_MISC_INCR_SYNCPT_0_MISC_INDX_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_MISC_INCR_SYNCPT_0_MISC_INDX_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register VI_MISC_INCR_SYNCPT_CNTRL_0  
+#define VI_MISC_INCR_SYNCPT_CNTRL_0                     _MK_ADDR_CONST(0x11)
+#define VI_MISC_INCR_SYNCPT_CNTRL_0_WORD_COUNT                  0x1
+#define VI_MISC_INCR_SYNCPT_CNTRL_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define VI_MISC_INCR_SYNCPT_CNTRL_0_RESET_MASK                  _MK_MASK_CONST(0x101)
+#define VI_MISC_INCR_SYNCPT_CNTRL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define VI_MISC_INCR_SYNCPT_CNTRL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_MISC_INCR_SYNCPT_CNTRL_0_READ_MASK                   _MK_MASK_CONST(0x101)
+#define VI_MISC_INCR_SYNCPT_CNTRL_0_WRITE_MASK                  _MK_MASK_CONST(0x101)
+// If NO_STALL is 1, then when fifos are full,
+// INCR_SYNCPT methods will be dropped and the
+// INCR_SYNCPT_ERROR[COND] bit will be set.
+// If NO_STALL is 0, then when fifos are full,
+// the client host interface will be stalled.
+#define VI_MISC_INCR_SYNCPT_CNTRL_0_MISC_INCR_SYNCPT_NO_STALL_SHIFT                     _MK_SHIFT_CONST(8)
+#define VI_MISC_INCR_SYNCPT_CNTRL_0_MISC_INCR_SYNCPT_NO_STALL_FIELD                     (_MK_MASK_CONST(0x1) << VI_MISC_INCR_SYNCPT_CNTRL_0_MISC_INCR_SYNCPT_NO_STALL_SHIFT)
+#define VI_MISC_INCR_SYNCPT_CNTRL_0_MISC_INCR_SYNCPT_NO_STALL_RANGE                     8:8
+#define VI_MISC_INCR_SYNCPT_CNTRL_0_MISC_INCR_SYNCPT_NO_STALL_WOFFSET                   0x0
+#define VI_MISC_INCR_SYNCPT_CNTRL_0_MISC_INCR_SYNCPT_NO_STALL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_MISC_INCR_SYNCPT_CNTRL_0_MISC_INCR_SYNCPT_NO_STALL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define VI_MISC_INCR_SYNCPT_CNTRL_0_MISC_INCR_SYNCPT_NO_STALL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_MISC_INCR_SYNCPT_CNTRL_0_MISC_INCR_SYNCPT_NO_STALL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// If SOFT_RESET is set, then all internal state
+// of the client syncpt block will be reset.
+// To do soft reset, first set SOFT_RESET of
+// all host1x clients affected, then clear all
+// SOFT_RESETs.
+#define VI_MISC_INCR_SYNCPT_CNTRL_0_MISC_INCR_SYNCPT_SOFT_RESET_SHIFT                   _MK_SHIFT_CONST(0)
+#define VI_MISC_INCR_SYNCPT_CNTRL_0_MISC_INCR_SYNCPT_SOFT_RESET_FIELD                   (_MK_MASK_CONST(0x1) << VI_MISC_INCR_SYNCPT_CNTRL_0_MISC_INCR_SYNCPT_SOFT_RESET_SHIFT)
+#define VI_MISC_INCR_SYNCPT_CNTRL_0_MISC_INCR_SYNCPT_SOFT_RESET_RANGE                   0:0
+#define VI_MISC_INCR_SYNCPT_CNTRL_0_MISC_INCR_SYNCPT_SOFT_RESET_WOFFSET                 0x0
+#define VI_MISC_INCR_SYNCPT_CNTRL_0_MISC_INCR_SYNCPT_SOFT_RESET_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_MISC_INCR_SYNCPT_CNTRL_0_MISC_INCR_SYNCPT_SOFT_RESET_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define VI_MISC_INCR_SYNCPT_CNTRL_0_MISC_INCR_SYNCPT_SOFT_RESET_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_MISC_INCR_SYNCPT_CNTRL_0_MISC_INCR_SYNCPT_SOFT_RESET_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register VI_MISC_INCR_SYNCPT_ERROR_0  
+#define VI_MISC_INCR_SYNCPT_ERROR_0                     _MK_ADDR_CONST(0x12)
+#define VI_MISC_INCR_SYNCPT_ERROR_0_WORD_COUNT                  0x1
+#define VI_MISC_INCR_SYNCPT_ERROR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define VI_MISC_INCR_SYNCPT_ERROR_0_RESET_MASK                  _MK_MASK_CONST(0x0)
+#define VI_MISC_INCR_SYNCPT_ERROR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define VI_MISC_INCR_SYNCPT_ERROR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_MISC_INCR_SYNCPT_ERROR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define VI_MISC_INCR_SYNCPT_ERROR_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+// COND_STATUS[COND] is set if the fifo for COND overflows.
+// This bit is sticky and will remain set until cleared.
+// Cleared by writing 1.
+#define VI_MISC_INCR_SYNCPT_ERROR_0_MISC_COND_STATUS_SHIFT                      _MK_SHIFT_CONST(0)
+#define VI_MISC_INCR_SYNCPT_ERROR_0_MISC_COND_STATUS_FIELD                      (_MK_MASK_CONST(0xffffffff) << VI_MISC_INCR_SYNCPT_ERROR_0_MISC_COND_STATUS_SHIFT)
+#define VI_MISC_INCR_SYNCPT_ERROR_0_MISC_COND_STATUS_RANGE                      31:0
+#define VI_MISC_INCR_SYNCPT_ERROR_0_MISC_COND_STATUS_WOFFSET                    0x0
+#define VI_MISC_INCR_SYNCPT_ERROR_0_MISC_COND_STATUS_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_MISC_INCR_SYNCPT_ERROR_0_MISC_COND_STATUS_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_MISC_INCR_SYNCPT_ERROR_0_MISC_COND_STATUS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_MISC_INCR_SYNCPT_ERROR_0_MISC_COND_STATUS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Reserved address 19 [0x13] 
+
+// Reserved address 20 [0x14] 
+
+// Reserved address 21 [0x15] 
+
+// Reserved address 22 [0x16] 
+
+// Reserved address 23 [0x17] 
+
+// Register VI_CONT_SYNCPT_OUT_1_0  
+#define VI_CONT_SYNCPT_OUT_1_0                  _MK_ADDR_CONST(0x18)
+#define VI_CONT_SYNCPT_OUT_1_0_WORD_COUNT                       0x1
+#define VI_CONT_SYNCPT_OUT_1_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_OUT_1_0_RESET_MASK                       _MK_MASK_CONST(0x100)
+#define VI_CONT_SYNCPT_OUT_1_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_OUT_1_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_OUT_1_0_READ_MASK                        _MK_MASK_CONST(0x1ff)
+#define VI_CONT_SYNCPT_OUT_1_0_WRITE_MASK                       _MK_MASK_CONST(0x1ff)
+// return INDX (set HOST_CLRD packet TYPE field to SYNCPT)
+#define VI_CONT_SYNCPT_OUT_1_0_INDX_OUT_1_SHIFT                 _MK_SHIFT_CONST(0)
+#define VI_CONT_SYNCPT_OUT_1_0_INDX_OUT_1_FIELD                 (_MK_MASK_CONST(0xff) << VI_CONT_SYNCPT_OUT_1_0_INDX_OUT_1_SHIFT)
+#define VI_CONT_SYNCPT_OUT_1_0_INDX_OUT_1_RANGE                 7:0
+#define VI_CONT_SYNCPT_OUT_1_0_INDX_OUT_1_WOFFSET                       0x0
+#define VI_CONT_SYNCPT_OUT_1_0_INDX_OUT_1_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_OUT_1_0_INDX_OUT_1_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_OUT_1_0_INDX_OUT_1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_OUT_1_0_INDX_OUT_1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// on host read bus every time OUT_1 condition is true and OUT_1_EN is set
+#define VI_CONT_SYNCPT_OUT_1_0_EN_OUT_1_SHIFT                   _MK_SHIFT_CONST(8)
+#define VI_CONT_SYNCPT_OUT_1_0_EN_OUT_1_FIELD                   (_MK_MASK_CONST(0x1) << VI_CONT_SYNCPT_OUT_1_0_EN_OUT_1_SHIFT)
+#define VI_CONT_SYNCPT_OUT_1_0_EN_OUT_1_RANGE                   8:8
+#define VI_CONT_SYNCPT_OUT_1_0_EN_OUT_1_WOFFSET                 0x0
+#define VI_CONT_SYNCPT_OUT_1_0_EN_OUT_1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_OUT_1_0_EN_OUT_1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define VI_CONT_SYNCPT_OUT_1_0_EN_OUT_1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_OUT_1_0_EN_OUT_1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register VI_CONT_SYNCPT_OUT_2_0  
+#define VI_CONT_SYNCPT_OUT_2_0                  _MK_ADDR_CONST(0x19)
+#define VI_CONT_SYNCPT_OUT_2_0_WORD_COUNT                       0x1
+#define VI_CONT_SYNCPT_OUT_2_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_OUT_2_0_RESET_MASK                       _MK_MASK_CONST(0x100)
+#define VI_CONT_SYNCPT_OUT_2_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_OUT_2_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_OUT_2_0_READ_MASK                        _MK_MASK_CONST(0x1ff)
+#define VI_CONT_SYNCPT_OUT_2_0_WRITE_MASK                       _MK_MASK_CONST(0x1ff)
+// return INDX (set HOST_CLRD packet TYPE field to SYNCPT)
+#define VI_CONT_SYNCPT_OUT_2_0_INDX_OUT_2_SHIFT                 _MK_SHIFT_CONST(0)
+#define VI_CONT_SYNCPT_OUT_2_0_INDX_OUT_2_FIELD                 (_MK_MASK_CONST(0xff) << VI_CONT_SYNCPT_OUT_2_0_INDX_OUT_2_SHIFT)
+#define VI_CONT_SYNCPT_OUT_2_0_INDX_OUT_2_RANGE                 7:0
+#define VI_CONT_SYNCPT_OUT_2_0_INDX_OUT_2_WOFFSET                       0x0
+#define VI_CONT_SYNCPT_OUT_2_0_INDX_OUT_2_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_OUT_2_0_INDX_OUT_2_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_OUT_2_0_INDX_OUT_2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_OUT_2_0_INDX_OUT_2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// on host read bus every time OUT_2 condition is true and OUT_2_EN is set
+#define VI_CONT_SYNCPT_OUT_2_0_EN_OUT_2_SHIFT                   _MK_SHIFT_CONST(8)
+#define VI_CONT_SYNCPT_OUT_2_0_EN_OUT_2_FIELD                   (_MK_MASK_CONST(0x1) << VI_CONT_SYNCPT_OUT_2_0_EN_OUT_2_SHIFT)
+#define VI_CONT_SYNCPT_OUT_2_0_EN_OUT_2_RANGE                   8:8
+#define VI_CONT_SYNCPT_OUT_2_0_EN_OUT_2_WOFFSET                 0x0
+#define VI_CONT_SYNCPT_OUT_2_0_EN_OUT_2_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_OUT_2_0_EN_OUT_2_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define VI_CONT_SYNCPT_OUT_2_0_EN_OUT_2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_OUT_2_0_EN_OUT_2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register VI_CONT_SYNCPT_VIP_VSYNC_0  
+#define VI_CONT_SYNCPT_VIP_VSYNC_0                      _MK_ADDR_CONST(0x1a)
+#define VI_CONT_SYNCPT_VIP_VSYNC_0_WORD_COUNT                   0x1
+#define VI_CONT_SYNCPT_VIP_VSYNC_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_VIP_VSYNC_0_RESET_MASK                   _MK_MASK_CONST(0x100)
+#define VI_CONT_SYNCPT_VIP_VSYNC_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_VIP_VSYNC_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_VIP_VSYNC_0_READ_MASK                    _MK_MASK_CONST(0x1ff)
+#define VI_CONT_SYNCPT_VIP_VSYNC_0_WRITE_MASK                   _MK_MASK_CONST(0x1ff)
+// return INDX (set HOST_CLRD packet TYPE field to SYNCPT)
+#define VI_CONT_SYNCPT_VIP_VSYNC_0_INDX_VIP_VSYNC_SHIFT                 _MK_SHIFT_CONST(0)
+#define VI_CONT_SYNCPT_VIP_VSYNC_0_INDX_VIP_VSYNC_FIELD                 (_MK_MASK_CONST(0xff) << VI_CONT_SYNCPT_VIP_VSYNC_0_INDX_VIP_VSYNC_SHIFT)
+#define VI_CONT_SYNCPT_VIP_VSYNC_0_INDX_VIP_VSYNC_RANGE                 7:0
+#define VI_CONT_SYNCPT_VIP_VSYNC_0_INDX_VIP_VSYNC_WOFFSET                       0x0
+#define VI_CONT_SYNCPT_VIP_VSYNC_0_INDX_VIP_VSYNC_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_VIP_VSYNC_0_INDX_VIP_VSYNC_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_VIP_VSYNC_0_INDX_VIP_VSYNC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_VIP_VSYNC_0_INDX_VIP_VSYNC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// on host read bus every time VSYNC condition is true and EN_VSYNC is set
+#define VI_CONT_SYNCPT_VIP_VSYNC_0_EN_VIP_VSYNC_SHIFT                   _MK_SHIFT_CONST(8)
+#define VI_CONT_SYNCPT_VIP_VSYNC_0_EN_VIP_VSYNC_FIELD                   (_MK_MASK_CONST(0x1) << VI_CONT_SYNCPT_VIP_VSYNC_0_EN_VIP_VSYNC_SHIFT)
+#define VI_CONT_SYNCPT_VIP_VSYNC_0_EN_VIP_VSYNC_RANGE                   8:8
+#define VI_CONT_SYNCPT_VIP_VSYNC_0_EN_VIP_VSYNC_WOFFSET                 0x0
+#define VI_CONT_SYNCPT_VIP_VSYNC_0_EN_VIP_VSYNC_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_VIP_VSYNC_0_EN_VIP_VSYNC_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define VI_CONT_SYNCPT_VIP_VSYNC_0_EN_VIP_VSYNC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_VIP_VSYNC_0_EN_VIP_VSYNC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register VI_CONT_SYNCPT_VI2EPP_0  
+#define VI_CONT_SYNCPT_VI2EPP_0                 _MK_ADDR_CONST(0x1b)
+#define VI_CONT_SYNCPT_VI2EPP_0_WORD_COUNT                      0x1
+#define VI_CONT_SYNCPT_VI2EPP_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_VI2EPP_0_RESET_MASK                      _MK_MASK_CONST(0x100)
+#define VI_CONT_SYNCPT_VI2EPP_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_VI2EPP_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_VI2EPP_0_READ_MASK                       _MK_MASK_CONST(0x1ff)
+#define VI_CONT_SYNCPT_VI2EPP_0_WRITE_MASK                      _MK_MASK_CONST(0x1ff)
+// return INDX (set HOST_CLRD packet TYPE field to SYNCPT)
+#define VI_CONT_SYNCPT_VI2EPP_0_INDX_VI2EPP_SHIFT                       _MK_SHIFT_CONST(0)
+#define VI_CONT_SYNCPT_VI2EPP_0_INDX_VI2EPP_FIELD                       (_MK_MASK_CONST(0xff) << VI_CONT_SYNCPT_VI2EPP_0_INDX_VI2EPP_SHIFT)
+#define VI_CONT_SYNCPT_VI2EPP_0_INDX_VI2EPP_RANGE                       7:0
+#define VI_CONT_SYNCPT_VI2EPP_0_INDX_VI2EPP_WOFFSET                     0x0
+#define VI_CONT_SYNCPT_VI2EPP_0_INDX_VI2EPP_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_VI2EPP_0_INDX_VI2EPP_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_VI2EPP_0_INDX_VI2EPP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_VI2EPP_0_INDX_VI2EPP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// on host read bus every time VI2EPP condition is true and EN_VSYNC is set
+#define VI_CONT_SYNCPT_VI2EPP_0_EN_VI2EPP_SHIFT                 _MK_SHIFT_CONST(8)
+#define VI_CONT_SYNCPT_VI2EPP_0_EN_VI2EPP_FIELD                 (_MK_MASK_CONST(0x1) << VI_CONT_SYNCPT_VI2EPP_0_EN_VI2EPP_SHIFT)
+#define VI_CONT_SYNCPT_VI2EPP_0_EN_VI2EPP_RANGE                 8:8
+#define VI_CONT_SYNCPT_VI2EPP_0_EN_VI2EPP_WOFFSET                       0x0
+#define VI_CONT_SYNCPT_VI2EPP_0_EN_VI2EPP_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_VI2EPP_0_EN_VI2EPP_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define VI_CONT_SYNCPT_VI2EPP_0_EN_VI2EPP_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_VI2EPP_0_EN_VI2EPP_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register VI_CONT_SYNCPT_CSI_PPA_FRAME_START_0  
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_START_0                    _MK_ADDR_CONST(0x1c)
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_START_0_WORD_COUNT                         0x1
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_START_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_START_0_RESET_MASK                         _MK_MASK_CONST(0x100)
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_START_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_START_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_START_0_READ_MASK                  _MK_MASK_CONST(0x1ff)
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_START_0_WRITE_MASK                         _MK_MASK_CONST(0x1ff)
+// return INDX (set HOST_CLRD packet TYPE field to SYNCPT)
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_START_0_INDX_CSI_PPA_FRAME_START_SHIFT                     _MK_SHIFT_CONST(0)
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_START_0_INDX_CSI_PPA_FRAME_START_FIELD                     (_MK_MASK_CONST(0xff) << VI_CONT_SYNCPT_CSI_PPA_FRAME_START_0_INDX_CSI_PPA_FRAME_START_SHIFT)
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_START_0_INDX_CSI_PPA_FRAME_START_RANGE                     7:0
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_START_0_INDX_CSI_PPA_FRAME_START_WOFFSET                   0x0
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_START_0_INDX_CSI_PPA_FRAME_START_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_START_0_INDX_CSI_PPA_FRAME_START_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_START_0_INDX_CSI_PPA_FRAME_START_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_START_0_INDX_CSI_PPA_FRAME_START_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// on host read bus every time CSI_PPA_FRAME_START condition is true and EN_VSYNC is set
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_START_0_EN_CSI_PPA_FRAME_START_SHIFT                       _MK_SHIFT_CONST(8)
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_START_0_EN_CSI_PPA_FRAME_START_FIELD                       (_MK_MASK_CONST(0x1) << VI_CONT_SYNCPT_CSI_PPA_FRAME_START_0_EN_CSI_PPA_FRAME_START_SHIFT)
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_START_0_EN_CSI_PPA_FRAME_START_RANGE                       8:8
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_START_0_EN_CSI_PPA_FRAME_START_WOFFSET                     0x0
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_START_0_EN_CSI_PPA_FRAME_START_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_START_0_EN_CSI_PPA_FRAME_START_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_START_0_EN_CSI_PPA_FRAME_START_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_START_0_EN_CSI_PPA_FRAME_START_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register VI_CONT_SYNCPT_CSI_PPA_FRAME_END_0  
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_END_0                      _MK_ADDR_CONST(0x1d)
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_END_0_WORD_COUNT                   0x1
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_END_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_END_0_RESET_MASK                   _MK_MASK_CONST(0x100)
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_END_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_END_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_END_0_READ_MASK                    _MK_MASK_CONST(0x1ff)
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_END_0_WRITE_MASK                   _MK_MASK_CONST(0x1ff)
+// return INDX (set HOST_CLRD packet TYPE field to SYNCPT)
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_END_0_INDX_CSI_PPA_FRAME_END_SHIFT                 _MK_SHIFT_CONST(0)
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_END_0_INDX_CSI_PPA_FRAME_END_FIELD                 (_MK_MASK_CONST(0xff) << VI_CONT_SYNCPT_CSI_PPA_FRAME_END_0_INDX_CSI_PPA_FRAME_END_SHIFT)
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_END_0_INDX_CSI_PPA_FRAME_END_RANGE                 7:0
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_END_0_INDX_CSI_PPA_FRAME_END_WOFFSET                       0x0
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_END_0_INDX_CSI_PPA_FRAME_END_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_END_0_INDX_CSI_PPA_FRAME_END_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_END_0_INDX_CSI_PPA_FRAME_END_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_END_0_INDX_CSI_PPA_FRAME_END_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// on host read bus every time CSI_PPA_FRAME_END condition is true and EN_VSYNC is set
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_END_0_EN_CSI_PPA_FRAME_END_SHIFT                   _MK_SHIFT_CONST(8)
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_END_0_EN_CSI_PPA_FRAME_END_FIELD                   (_MK_MASK_CONST(0x1) << VI_CONT_SYNCPT_CSI_PPA_FRAME_END_0_EN_CSI_PPA_FRAME_END_SHIFT)
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_END_0_EN_CSI_PPA_FRAME_END_RANGE                   8:8
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_END_0_EN_CSI_PPA_FRAME_END_WOFFSET                 0x0
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_END_0_EN_CSI_PPA_FRAME_END_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_END_0_EN_CSI_PPA_FRAME_END_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_END_0_EN_CSI_PPA_FRAME_END_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_END_0_EN_CSI_PPA_FRAME_END_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register VI_CONT_SYNCPT_CSI_PPB_FRAME_START_0  
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_START_0                    _MK_ADDR_CONST(0x1e)
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_START_0_WORD_COUNT                         0x1
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_START_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_START_0_RESET_MASK                         _MK_MASK_CONST(0x100)
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_START_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_START_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_START_0_READ_MASK                  _MK_MASK_CONST(0x1ff)
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_START_0_WRITE_MASK                         _MK_MASK_CONST(0x1ff)
+// return INDX (set HOST_CLRD packet TYPE field to SYNCPT)
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_START_0_INDX_CSI_PPB_FRAME_START_SHIFT                     _MK_SHIFT_CONST(0)
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_START_0_INDX_CSI_PPB_FRAME_START_FIELD                     (_MK_MASK_CONST(0xff) << VI_CONT_SYNCPT_CSI_PPB_FRAME_START_0_INDX_CSI_PPB_FRAME_START_SHIFT)
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_START_0_INDX_CSI_PPB_FRAME_START_RANGE                     7:0
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_START_0_INDX_CSI_PPB_FRAME_START_WOFFSET                   0x0
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_START_0_INDX_CSI_PPB_FRAME_START_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_START_0_INDX_CSI_PPB_FRAME_START_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_START_0_INDX_CSI_PPB_FRAME_START_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_START_0_INDX_CSI_PPB_FRAME_START_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// on host read bus every time CSI_PPB_FRAME_START condition is true and EN_VSYNC is set
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_START_0_EN_CSI_PPB_FRAME_START_SHIFT                       _MK_SHIFT_CONST(8)
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_START_0_EN_CSI_PPB_FRAME_START_FIELD                       (_MK_MASK_CONST(0x1) << VI_CONT_SYNCPT_CSI_PPB_FRAME_START_0_EN_CSI_PPB_FRAME_START_SHIFT)
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_START_0_EN_CSI_PPB_FRAME_START_RANGE                       8:8
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_START_0_EN_CSI_PPB_FRAME_START_WOFFSET                     0x0
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_START_0_EN_CSI_PPB_FRAME_START_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_START_0_EN_CSI_PPB_FRAME_START_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_START_0_EN_CSI_PPB_FRAME_START_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_START_0_EN_CSI_PPB_FRAME_START_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register VI_CONT_SYNCPT_CSI_PPB_FRAME_END_0  
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_END_0                      _MK_ADDR_CONST(0x1f)
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_END_0_WORD_COUNT                   0x1
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_END_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_END_0_RESET_MASK                   _MK_MASK_CONST(0x100)
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_END_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_END_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_END_0_READ_MASK                    _MK_MASK_CONST(0x1ff)
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_END_0_WRITE_MASK                   _MK_MASK_CONST(0x1ff)
+// return INDX (set HOST_CLRD packet TYPE field to SYNCPT)
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_END_0_INDX_CSI_PPB_FRAME_END_SHIFT                 _MK_SHIFT_CONST(0)
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_END_0_INDX_CSI_PPB_FRAME_END_FIELD                 (_MK_MASK_CONST(0xff) << VI_CONT_SYNCPT_CSI_PPB_FRAME_END_0_INDX_CSI_PPB_FRAME_END_SHIFT)
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_END_0_INDX_CSI_PPB_FRAME_END_RANGE                 7:0
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_END_0_INDX_CSI_PPB_FRAME_END_WOFFSET                       0x0
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_END_0_INDX_CSI_PPB_FRAME_END_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_END_0_INDX_CSI_PPB_FRAME_END_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_END_0_INDX_CSI_PPB_FRAME_END_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_END_0_INDX_CSI_PPB_FRAME_END_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// on host read bus every time CSI_PPB_FRAME_END condition is true and EN_VSYNC is set
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_END_0_EN_CSI_PPB_FRAME_END_SHIFT                   _MK_SHIFT_CONST(8)
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_END_0_EN_CSI_PPB_FRAME_END_FIELD                   (_MK_MASK_CONST(0x1) << VI_CONT_SYNCPT_CSI_PPB_FRAME_END_0_EN_CSI_PPB_FRAME_END_SHIFT)
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_END_0_EN_CSI_PPB_FRAME_END_RANGE                   8:8
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_END_0_EN_CSI_PPB_FRAME_END_WOFFSET                 0x0
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_END_0_EN_CSI_PPB_FRAME_END_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_END_0_EN_CSI_PPB_FRAME_END_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_END_0_EN_CSI_PPB_FRAME_END_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_END_0_EN_CSI_PPB_FRAME_END_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register VI_CTXSW_0  
+#define VI_CTXSW_0                      _MK_ADDR_CONST(0x20)
+#define VI_CTXSW_0_WORD_COUNT                   0x1
+#define VI_CTXSW_0_RESET_VAL                    _MK_MASK_CONST(0xf000f800)
+#define VI_CTXSW_0_RESET_MASK                   _MK_MASK_CONST(0xf3fffbff)
+#define VI_CTXSW_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define VI_CTXSW_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_CTXSW_0_READ_MASK                    _MK_MASK_CONST(0xf3fffbff)
+#define VI_CTXSW_0_WRITE_MASK                   _MK_MASK_CONST(0xfbff)
+// Current working class
+#define VI_CTXSW_0_CURR_CLASS_SHIFT                     _MK_SHIFT_CONST(0)
+#define VI_CTXSW_0_CURR_CLASS_FIELD                     (_MK_MASK_CONST(0x3ff) << VI_CTXSW_0_CURR_CLASS_SHIFT)
+#define VI_CTXSW_0_CURR_CLASS_RANGE                     9:0
+#define VI_CTXSW_0_CURR_CLASS_WOFFSET                   0x0
+#define VI_CTXSW_0_CURR_CLASS_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_CTXSW_0_CURR_CLASS_DEFAULT_MASK                      _MK_MASK_CONST(0x3ff)
+#define VI_CTXSW_0_CURR_CLASS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_CTXSW_0_CURR_CLASS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Automatically acknowledge any incoming context switch requests
+#define VI_CTXSW_0_AUTO_ACK_SHIFT                       _MK_SHIFT_CONST(11)
+#define VI_CTXSW_0_AUTO_ACK_FIELD                       (_MK_MASK_CONST(0x1) << VI_CTXSW_0_AUTO_ACK_SHIFT)
+#define VI_CTXSW_0_AUTO_ACK_RANGE                       11:11
+#define VI_CTXSW_0_AUTO_ACK_WOFFSET                     0x0
+#define VI_CTXSW_0_AUTO_ACK_DEFAULT                     _MK_MASK_CONST(0x1)
+#define VI_CTXSW_0_AUTO_ACK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define VI_CTXSW_0_AUTO_ACK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_CTXSW_0_AUTO_ACK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_CTXSW_0_AUTO_ACK_MANUAL                      _MK_ENUM_CONST(0)
+#define VI_CTXSW_0_AUTO_ACK_AUTOACK                     _MK_ENUM_CONST(1)
+
+// Current working channel, reset to 'invalid'
+#define VI_CTXSW_0_CURR_CHANNEL_SHIFT                   _MK_SHIFT_CONST(12)
+#define VI_CTXSW_0_CURR_CHANNEL_FIELD                   (_MK_MASK_CONST(0xf) << VI_CTXSW_0_CURR_CHANNEL_SHIFT)
+#define VI_CTXSW_0_CURR_CHANNEL_RANGE                   15:12
+#define VI_CTXSW_0_CURR_CHANNEL_WOFFSET                 0x0
+#define VI_CTXSW_0_CURR_CHANNEL_DEFAULT                 _MK_MASK_CONST(0xf)
+#define VI_CTXSW_0_CURR_CHANNEL_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define VI_CTXSW_0_CURR_CHANNEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_CTXSW_0_CURR_CHANNEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Next requested class
+#define VI_CTXSW_0_NEXT_CLASS_SHIFT                     _MK_SHIFT_CONST(16)
+#define VI_CTXSW_0_NEXT_CLASS_FIELD                     (_MK_MASK_CONST(0x3ff) << VI_CTXSW_0_NEXT_CLASS_SHIFT)
+#define VI_CTXSW_0_NEXT_CLASS_RANGE                     25:16
+#define VI_CTXSW_0_NEXT_CLASS_WOFFSET                   0x0
+#define VI_CTXSW_0_NEXT_CLASS_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_CTXSW_0_NEXT_CLASS_DEFAULT_MASK                      _MK_MASK_CONST(0x3ff)
+#define VI_CTXSW_0_NEXT_CLASS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_CTXSW_0_NEXT_CLASS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Next requested channel
+#define VI_CTXSW_0_NEXT_CHANNEL_SHIFT                   _MK_SHIFT_CONST(28)
+#define VI_CTXSW_0_NEXT_CHANNEL_FIELD                   (_MK_MASK_CONST(0xf) << VI_CTXSW_0_NEXT_CHANNEL_SHIFT)
+#define VI_CTXSW_0_NEXT_CHANNEL_RANGE                   31:28
+#define VI_CTXSW_0_NEXT_CHANNEL_WOFFSET                 0x0
+#define VI_CTXSW_0_NEXT_CHANNEL_DEFAULT                 _MK_MASK_CONST(0xf)
+#define VI_CTXSW_0_NEXT_CHANNEL_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define VI_CTXSW_0_NEXT_CHANNEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_CTXSW_0_NEXT_CHANNEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register VI_INTSTATUS_0  
+#define VI_INTSTATUS_0                  _MK_ADDR_CONST(0x21)
+#define VI_INTSTATUS_0_WORD_COUNT                       0x1
+#define VI_INTSTATUS_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define VI_INTSTATUS_0_RESET_MASK                       _MK_MASK_CONST(0x1)
+#define VI_INTSTATUS_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define VI_INTSTATUS_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_INTSTATUS_0_READ_MASK                        _MK_MASK_CONST(0x1)
+#define VI_INTSTATUS_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
+// Context switch interrupt status (clear on write)
+#define VI_INTSTATUS_0_CTXSW_INT_SHIFT                  _MK_SHIFT_CONST(0)
+#define VI_INTSTATUS_0_CTXSW_INT_FIELD                  (_MK_MASK_CONST(0x1) << VI_INTSTATUS_0_CTXSW_INT_SHIFT)
+#define VI_INTSTATUS_0_CTXSW_INT_RANGE                  0:0
+#define VI_INTSTATUS_0_CTXSW_INT_WOFFSET                        0x0
+#define VI_INTSTATUS_0_CTXSW_INT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_INTSTATUS_0_CTXSW_INT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define VI_INTSTATUS_0_CTXSW_INT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_INTSTATUS_0_CTXSW_INT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register VI_VI_INPUT_CONTROL_0  // VI Input Control
+#define VI_VI_INPUT_CONTROL_0                   _MK_ADDR_CONST(0x22)
+#define VI_VI_INPUT_CONTROL_0_WORD_COUNT                        0x1
+#define VI_VI_INPUT_CONTROL_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_RESET_MASK                        _MK_MASK_CONST(0x7f801fff)
+#define VI_VI_INPUT_CONTROL_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_READ_MASK                         _MK_MASK_CONST(0x7f801fff)
+#define VI_VI_INPUT_CONTROL_0_WRITE_MASK                        _MK_MASK_CONST(0x7f801fff)
+// Host Input Enable   0= DISABLED
+//   1= ENABLED
+#define VI_VI_INPUT_CONTROL_0_HOST_INPUT_ENABLE_SHIFT                   _MK_SHIFT_CONST(0)
+#define VI_VI_INPUT_CONTROL_0_HOST_INPUT_ENABLE_FIELD                   (_MK_MASK_CONST(0x1) << VI_VI_INPUT_CONTROL_0_HOST_INPUT_ENABLE_SHIFT)
+#define VI_VI_INPUT_CONTROL_0_HOST_INPUT_ENABLE_RANGE                   0:0
+#define VI_VI_INPUT_CONTROL_0_HOST_INPUT_ENABLE_WOFFSET                 0x0
+#define VI_VI_INPUT_CONTROL_0_HOST_INPUT_ENABLE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_HOST_INPUT_ENABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define VI_VI_INPUT_CONTROL_0_HOST_INPUT_ENABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_HOST_INPUT_ENABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_HOST_INPUT_ENABLE_DISABLED                        _MK_ENUM_CONST(0)
+#define VI_VI_INPUT_CONTROL_0_HOST_INPUT_ENABLE_ENABLED                 _MK_ENUM_CONST(1)
+
+// VIP Input Enable   0= DISABLED
+//   1= ENABLED
+// This bit turn on clocks for VIP input logic. This
+//   bit has to be enabled before CAMERA_CONTROL's
+//   VIP_ENABLE bit for any VIP logic to start!
+#define VI_VI_INPUT_CONTROL_0_VIP_INPUT_ENABLE_SHIFT                    _MK_SHIFT_CONST(1)
+#define VI_VI_INPUT_CONTROL_0_VIP_INPUT_ENABLE_FIELD                    (_MK_MASK_CONST(0x1) << VI_VI_INPUT_CONTROL_0_VIP_INPUT_ENABLE_SHIFT)
+#define VI_VI_INPUT_CONTROL_0_VIP_INPUT_ENABLE_RANGE                    1:1
+#define VI_VI_INPUT_CONTROL_0_VIP_INPUT_ENABLE_WOFFSET                  0x0
+#define VI_VI_INPUT_CONTROL_0_VIP_INPUT_ENABLE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_VIP_INPUT_ENABLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define VI_VI_INPUT_CONTROL_0_VIP_INPUT_ENABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_VIP_INPUT_ENABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_VIP_INPUT_ENABLE_DISABLED                 _MK_ENUM_CONST(0)
+#define VI_VI_INPUT_CONTROL_0_VIP_INPUT_ENABLE_ENABLED                  _MK_ENUM_CONST(1)
+
+// Input port data Format  (effective if input source is VI Port)
+//   0000= YUV422 or ITU-R BT.656
+//   0001= Reserved 1
+//   0010= Bayer Pattern, enables ISP
+//   0011= Reserved 2
+//   0100= Pattern A, written directly to memory
+//   0101= Pattern B, written directly to memory
+//   0110= Pattern C, written directly to memory
+//   0111= Pattern C, do not remove the 0xFF, 0x02
+//   1000= Pattern D, ISDB-T input
+//   1001= YUV420NP, written directly to memory as YUV420P
+//   1010= RGB565, written directly to EPP
+//   1011= RGB888, written directly to EPP
+//   1100= RGB444, written directly to EPP
+//   1101= CSI,    written directly to CSI
+//         For YUV420NP no cropping will be done.
+//         For RGB565,RGB888,RGB444 written to EPP
+//         all cropping will be done in the EPP.
+#define VI_VI_INPUT_CONTROL_0_INPUT_PORT_FORMAT_SHIFT                   _MK_SHIFT_CONST(2)
+#define VI_VI_INPUT_CONTROL_0_INPUT_PORT_FORMAT_FIELD                   (_MK_MASK_CONST(0xf) << VI_VI_INPUT_CONTROL_0_INPUT_PORT_FORMAT_SHIFT)
+#define VI_VI_INPUT_CONTROL_0_INPUT_PORT_FORMAT_RANGE                   5:2
+#define VI_VI_INPUT_CONTROL_0_INPUT_PORT_FORMAT_WOFFSET                 0x0
+#define VI_VI_INPUT_CONTROL_0_INPUT_PORT_FORMAT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_INPUT_PORT_FORMAT_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define VI_VI_INPUT_CONTROL_0_INPUT_PORT_FORMAT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_INPUT_PORT_FORMAT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_INPUT_PORT_FORMAT_YUV422                  _MK_ENUM_CONST(0)
+#define VI_VI_INPUT_CONTROL_0_INPUT_PORT_FORMAT_RESERVED_1                      _MK_ENUM_CONST(1)
+#define VI_VI_INPUT_CONTROL_0_INPUT_PORT_FORMAT_BAYER                   _MK_ENUM_CONST(2)
+#define VI_VI_INPUT_CONTROL_0_INPUT_PORT_FORMAT_RESERVED_2                      _MK_ENUM_CONST(3)
+#define VI_VI_INPUT_CONTROL_0_INPUT_PORT_FORMAT_PATTERN_A                       _MK_ENUM_CONST(4)
+#define VI_VI_INPUT_CONTROL_0_INPUT_PORT_FORMAT_PATTERN_B                       _MK_ENUM_CONST(5)
+#define VI_VI_INPUT_CONTROL_0_INPUT_PORT_FORMAT_PATTERN_C                       _MK_ENUM_CONST(6)
+#define VI_VI_INPUT_CONTROL_0_INPUT_PORT_FORMAT_PATTERN_C_RAW                   _MK_ENUM_CONST(7)
+#define VI_VI_INPUT_CONTROL_0_INPUT_PORT_FORMAT_PATTERN_D                       _MK_ENUM_CONST(8)
+#define VI_VI_INPUT_CONTROL_0_INPUT_PORT_FORMAT_YUV420                  _MK_ENUM_CONST(9)
+#define VI_VI_INPUT_CONTROL_0_INPUT_PORT_FORMAT_RGB565                  _MK_ENUM_CONST(10)
+#define VI_VI_INPUT_CONTROL_0_INPUT_PORT_FORMAT_RGB888                  _MK_ENUM_CONST(11)
+#define VI_VI_INPUT_CONTROL_0_INPUT_PORT_FORMAT_RGB444                  _MK_ENUM_CONST(12)
+#define VI_VI_INPUT_CONTROL_0_INPUT_PORT_FORMAT_CSI                     _MK_ENUM_CONST(13)
+
+// Host data Format  (effective if input source is host)
+//   00= Non-planar YUV422
+//      (only Y-FIFO is used)
+//   01= Planar YUV420
+//      (Y-FIFO, U-FIFO, V-FIFO are used)
+//   10= Bayer 8-bit  - enables ISP
+//   11= Bayer 12-bit - enables ISP
+#define VI_VI_INPUT_CONTROL_0_HOST_FORMAT_SHIFT                 _MK_SHIFT_CONST(6)
+#define VI_VI_INPUT_CONTROL_0_HOST_FORMAT_FIELD                 (_MK_MASK_CONST(0x3) << VI_VI_INPUT_CONTROL_0_HOST_FORMAT_SHIFT)
+#define VI_VI_INPUT_CONTROL_0_HOST_FORMAT_RANGE                 7:6
+#define VI_VI_INPUT_CONTROL_0_HOST_FORMAT_WOFFSET                       0x0
+#define VI_VI_INPUT_CONTROL_0_HOST_FORMAT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_HOST_FORMAT_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define VI_VI_INPUT_CONTROL_0_HOST_FORMAT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_HOST_FORMAT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_HOST_FORMAT_NONPLANAR                     _MK_ENUM_CONST(0)
+#define VI_VI_INPUT_CONTROL_0_HOST_FORMAT_PLANAR                        _MK_ENUM_CONST(1)
+#define VI_VI_INPUT_CONTROL_0_HOST_FORMAT_BAYER8                        _MK_ENUM_CONST(2)
+#define VI_VI_INPUT_CONTROL_0_HOST_FORMAT_BAYER12                       _MK_ENUM_CONST(3)
+
+// YUV Input Format This is applicable when input source is
+// VI Port and format is YUV422/ITU-R BT.656
+// or when input source is host and host
+// format is non-planar YUV422.
+//  8 bits per component
+//   00= UYVY => Y1_V0_Y0_U0 MSB to LSB 32bit mapping
+//   01= VYUY => Y1_U0_Y0_V0
+//   10= YUYV => V0_Y1_U0_Y0
+//   11= YVYU => U0_Y1_V0_Y0
+#define VI_VI_INPUT_CONTROL_0_YUV_INPUT_FORMAT_SHIFT                    _MK_SHIFT_CONST(8)
+#define VI_VI_INPUT_CONTROL_0_YUV_INPUT_FORMAT_FIELD                    (_MK_MASK_CONST(0x3) << VI_VI_INPUT_CONTROL_0_YUV_INPUT_FORMAT_SHIFT)
+#define VI_VI_INPUT_CONTROL_0_YUV_INPUT_FORMAT_RANGE                    9:8
+#define VI_VI_INPUT_CONTROL_0_YUV_INPUT_FORMAT_WOFFSET                  0x0
+#define VI_VI_INPUT_CONTROL_0_YUV_INPUT_FORMAT_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_YUV_INPUT_FORMAT_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define VI_VI_INPUT_CONTROL_0_YUV_INPUT_FORMAT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_YUV_INPUT_FORMAT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_YUV_INPUT_FORMAT_UYVY                     _MK_ENUM_CONST(0)
+#define VI_VI_INPUT_CONTROL_0_YUV_INPUT_FORMAT_VYUY                     _MK_ENUM_CONST(1)
+#define VI_VI_INPUT_CONTROL_0_YUV_INPUT_FORMAT_YUYV                     _MK_ENUM_CONST(2)
+#define VI_VI_INPUT_CONTROL_0_YUV_INPUT_FORMAT_YVYU                     _MK_ENUM_CONST(3)
+
+// Select a data source input to HOST (extension field).  (use when input source is host)
+//  000= Source is selected with HOST_FORMAT field (backward compatible)
+//  001= Bayer 10 bpp: 2 16-bit values packed into 32-bit, LSbit aligned {6'b0, bayer, 6'b0, bayer} (to ISP)
+//  010= Bayer 14 bpp: 2 16-bit values packed into 32-bit, LSbit aligned {2'b0, bayer, 2'b0, bayer} (to ISP)
+//  011= RGB565             (to EPP)
+//  100= MSB Alpha + RGB888 (to EPP)
+//  101= MSB Alpha + BGR888 (to EPP)
+//  110= CSI                (to CSI)
+//  111= reserved
+// 22:13 reserved
+#define VI_VI_INPUT_CONTROL_0_HOST_FORMAT_EXT_SHIFT                     _MK_SHIFT_CONST(10)
+#define VI_VI_INPUT_CONTROL_0_HOST_FORMAT_EXT_FIELD                     (_MK_MASK_CONST(0x7) << VI_VI_INPUT_CONTROL_0_HOST_FORMAT_EXT_SHIFT)
+#define VI_VI_INPUT_CONTROL_0_HOST_FORMAT_EXT_RANGE                     12:10
+#define VI_VI_INPUT_CONTROL_0_HOST_FORMAT_EXT_WOFFSET                   0x0
+#define VI_VI_INPUT_CONTROL_0_HOST_FORMAT_EXT_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_HOST_FORMAT_EXT_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define VI_VI_INPUT_CONTROL_0_HOST_FORMAT_EXT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_HOST_FORMAT_EXT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_HOST_FORMAT_EXT_USE_HOST_FORMAT                   _MK_ENUM_CONST(0)
+#define VI_VI_INPUT_CONTROL_0_HOST_FORMAT_EXT_BAYER10                   _MK_ENUM_CONST(1)
+#define VI_VI_INPUT_CONTROL_0_HOST_FORMAT_EXT_BAYER14                   _MK_ENUM_CONST(2)
+#define VI_VI_INPUT_CONTROL_0_HOST_FORMAT_EXT_RGB565                    _MK_ENUM_CONST(3)
+#define VI_VI_INPUT_CONTROL_0_HOST_FORMAT_EXT_ARGB8888                  _MK_ENUM_CONST(4)
+#define VI_VI_INPUT_CONTROL_0_HOST_FORMAT_EXT_ABGR8888                  _MK_ENUM_CONST(5)
+#define VI_VI_INPUT_CONTROL_0_HOST_FORMAT_EXT_CSI                       _MK_ENUM_CONST(6)
+
+// VHS input signal active edge which is used  as horizontal reference of input data.
+//  VHS input inversion is evaluated first
+//  before determining active edge.
+//   0= Rising edge of VHS is active edge.
+//      For ITU-R BT.656 data, leading edge of
+//      horizontal sync is the active edge.
+//   1= Falling edge of VHS is active edge
+//      For ITU-R BT.656 data, trailing edge
+//      of horizontal sync is the active edge.
+#define VI_VI_INPUT_CONTROL_0_VHS_IN_EDGE_SHIFT                 _MK_SHIFT_CONST(23)
+#define VI_VI_INPUT_CONTROL_0_VHS_IN_EDGE_FIELD                 (_MK_MASK_CONST(0x1) << VI_VI_INPUT_CONTROL_0_VHS_IN_EDGE_SHIFT)
+#define VI_VI_INPUT_CONTROL_0_VHS_IN_EDGE_RANGE                 23:23
+#define VI_VI_INPUT_CONTROL_0_VHS_IN_EDGE_WOFFSET                       0x0
+#define VI_VI_INPUT_CONTROL_0_VHS_IN_EDGE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_VHS_IN_EDGE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define VI_VI_INPUT_CONTROL_0_VHS_IN_EDGE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_VHS_IN_EDGE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_VHS_IN_EDGE_RISING                        _MK_ENUM_CONST(0)
+#define VI_VI_INPUT_CONTROL_0_VHS_IN_EDGE_FALLING                       _MK_ENUM_CONST(1)
+
+// VVS input signal active edge which is used  as vertical reference of input data
+//  VVS input inversion is evaluated first
+//  before determining active edge.
+//   0= Rising edge of VVS is active edge
+//      For ITU-R BT.656 data, leading edge of
+//      vertical sync is the active edge.
+//   1= Falling edge of VVS is active edge
+//      For ITU-R BT.656 data, trailing edge
+//      of vertical sync is the active edge.
+#define VI_VI_INPUT_CONTROL_0_VVS_IN_EDGE_SHIFT                 _MK_SHIFT_CONST(24)
+#define VI_VI_INPUT_CONTROL_0_VVS_IN_EDGE_FIELD                 (_MK_MASK_CONST(0x1) << VI_VI_INPUT_CONTROL_0_VVS_IN_EDGE_SHIFT)
+#define VI_VI_INPUT_CONTROL_0_VVS_IN_EDGE_RANGE                 24:24
+#define VI_VI_INPUT_CONTROL_0_VVS_IN_EDGE_WOFFSET                       0x0
+#define VI_VI_INPUT_CONTROL_0_VVS_IN_EDGE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_VVS_IN_EDGE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define VI_VI_INPUT_CONTROL_0_VVS_IN_EDGE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_VVS_IN_EDGE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_VVS_IN_EDGE_RISING                        _MK_ENUM_CONST(0)
+#define VI_VI_INPUT_CONTROL_0_VVS_IN_EDGE_FALLING                       _MK_ENUM_CONST(1)
+
+// Horizontal and Vertical Sync Format  (effective if VIDEO_SOURCE is VIP)
+//   00= horizontal sync comes from VHS pin
+//       and vertical sync comes from VVS pin
+//       consistent with standard YUV422 data
+//       format.
+//       In this case, VHS_Input_Control and
+//       VVS_Input_Control must be enabled.
+//   01= horizontal and vertical syncs are
+//       decoded from the received video data
+//       bytes as specified in ITU-R BT.656
+//       (CCIR656) standard.
+//   10= horizontal and vertical syncs are
+//       generated internally and they are
+//       output on VHS and VVS pins if VHS and
+//       VVS are in output mode.
+#define VI_VI_INPUT_CONTROL_0_SYNC_FORMAT_SHIFT                 _MK_SHIFT_CONST(25)
+#define VI_VI_INPUT_CONTROL_0_SYNC_FORMAT_FIELD                 (_MK_MASK_CONST(0x3) << VI_VI_INPUT_CONTROL_0_SYNC_FORMAT_SHIFT)
+#define VI_VI_INPUT_CONTROL_0_SYNC_FORMAT_RANGE                 26:25
+#define VI_VI_INPUT_CONTROL_0_SYNC_FORMAT_WOFFSET                       0x0
+#define VI_VI_INPUT_CONTROL_0_SYNC_FORMAT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_SYNC_FORMAT_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define VI_VI_INPUT_CONTROL_0_SYNC_FORMAT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_SYNC_FORMAT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_SYNC_FORMAT_YUV422                        _MK_ENUM_CONST(0)
+#define VI_VI_INPUT_CONTROL_0_SYNC_FORMAT_ITU656                        _MK_ENUM_CONST(1)
+#define VI_VI_INPUT_CONTROL_0_SYNC_FORMAT_INTHVS                        _MK_ENUM_CONST(2)
+
+// Interlaced video Field Detection  (effective if VIDEO_SOURCE is VIP)
+//   0= Disabled (top field only)
+//   1= Enabled
+//      When H/V syncs are decoded per ITU-R
+//      BT.656 standard, odd/even field is
+//      detected from the control bytes.
+//      When H/V syncs come from VHS/VVS pins
+//      (YUV422), odd/even field is detected
+//      from the position of VVS active edge
+//      with respect to VHS active pulse.
+//      This bit should be disabled for non-
+//      interlaced source or when H/V syncs
+//      are generated internally.
+//  If VIDEO_SOURCE is HOST, field information
+//  is always specified by host.
+#define VI_VI_INPUT_CONTROL_0_FIELD_DETECT_SHIFT                        _MK_SHIFT_CONST(27)
+#define VI_VI_INPUT_CONTROL_0_FIELD_DETECT_FIELD                        (_MK_MASK_CONST(0x1) << VI_VI_INPUT_CONTROL_0_FIELD_DETECT_SHIFT)
+#define VI_VI_INPUT_CONTROL_0_FIELD_DETECT_RANGE                        27:27
+#define VI_VI_INPUT_CONTROL_0_FIELD_DETECT_WOFFSET                      0x0
+#define VI_VI_INPUT_CONTROL_0_FIELD_DETECT_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_FIELD_DETECT_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define VI_VI_INPUT_CONTROL_0_FIELD_DETECT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_FIELD_DETECT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_FIELD_DETECT_DISABLED                     _MK_ENUM_CONST(0)
+#define VI_VI_INPUT_CONTROL_0_FIELD_DETECT_ENABLED                      _MK_ENUM_CONST(1)
+
+// Odd/Even Field type  (effective for interlaced video source)
+//   0= Top field is odd field
+//   1= Top field is even field
+#define VI_VI_INPUT_CONTROL_0_FIELD_TYPE_SHIFT                  _MK_SHIFT_CONST(28)
+#define VI_VI_INPUT_CONTROL_0_FIELD_TYPE_FIELD                  (_MK_MASK_CONST(0x1) << VI_VI_INPUT_CONTROL_0_FIELD_TYPE_SHIFT)
+#define VI_VI_INPUT_CONTROL_0_FIELD_TYPE_RANGE                  28:28
+#define VI_VI_INPUT_CONTROL_0_FIELD_TYPE_WOFFSET                        0x0
+#define VI_VI_INPUT_CONTROL_0_FIELD_TYPE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_FIELD_TYPE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define VI_VI_INPUT_CONTROL_0_FIELD_TYPE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_FIELD_TYPE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_FIELD_TYPE_TOPODD                 _MK_ENUM_CONST(0)
+#define VI_VI_INPUT_CONTROL_0_FIELD_TYPE_TOPEVEN                        _MK_ENUM_CONST(1)
+
+// Horizontal Counter   0= Enabled
+//   1= Disabled (reset to 0)
+#define VI_VI_INPUT_CONTROL_0_H_COUNTER_SHIFT                   _MK_SHIFT_CONST(29)
+#define VI_VI_INPUT_CONTROL_0_H_COUNTER_FIELD                   (_MK_MASK_CONST(0x1) << VI_VI_INPUT_CONTROL_0_H_COUNTER_SHIFT)
+#define VI_VI_INPUT_CONTROL_0_H_COUNTER_RANGE                   29:29
+#define VI_VI_INPUT_CONTROL_0_H_COUNTER_WOFFSET                 0x0
+#define VI_VI_INPUT_CONTROL_0_H_COUNTER_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_H_COUNTER_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define VI_VI_INPUT_CONTROL_0_H_COUNTER_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_H_COUNTER_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_H_COUNTER_ENABLED                 _MK_ENUM_CONST(0)
+#define VI_VI_INPUT_CONTROL_0_H_COUNTER_DISABLED                        _MK_ENUM_CONST(1)
+
+// Vertical Counter   0= Enabled
+//   1= Disabled (reset to 0)
+#define VI_VI_INPUT_CONTROL_0_V_COUNTER_SHIFT                   _MK_SHIFT_CONST(30)
+#define VI_VI_INPUT_CONTROL_0_V_COUNTER_FIELD                   (_MK_MASK_CONST(0x1) << VI_VI_INPUT_CONTROL_0_V_COUNTER_SHIFT)
+#define VI_VI_INPUT_CONTROL_0_V_COUNTER_RANGE                   30:30
+#define VI_VI_INPUT_CONTROL_0_V_COUNTER_WOFFSET                 0x0
+#define VI_VI_INPUT_CONTROL_0_V_COUNTER_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_V_COUNTER_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define VI_VI_INPUT_CONTROL_0_V_COUNTER_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_V_COUNTER_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_V_COUNTER_ENABLED                 _MK_ENUM_CONST(0)
+#define VI_VI_INPUT_CONTROL_0_V_COUNTER_DISABLED                        _MK_ENUM_CONST(1)
+
+
+// Register VI_VI_CORE_CONTROL_0  // VI Core Control and Output to EPP/ISP
+#define VI_VI_CORE_CONTROL_0                    _MK_ADDR_CONST(0x23)
+#define VI_VI_CORE_CONTROL_0_WORD_COUNT                         0x1
+#define VI_VI_CORE_CONTROL_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_RESET_MASK                         _MK_MASK_CONST(0x7ff0f7f)
+#define VI_VI_CORE_CONTROL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_READ_MASK                  _MK_MASK_CONST(0x7ef0f7f)
+#define VI_VI_CORE_CONTROL_0_WRITE_MASK                         _MK_MASK_CONST(0x7ff0f7f)
+// Output to ISP  Enable data output to ISP
+//   00= Output to ISP is disabled
+//   01= Parallel Video Input Port data
+//   10= Host I/F data
+//   11= reserved
+#define VI_VI_CORE_CONTROL_0_OUTPUT_TO_ISP_SHIFT                        _MK_SHIFT_CONST(0)
+#define VI_VI_CORE_CONTROL_0_OUTPUT_TO_ISP_FIELD                        (_MK_MASK_CONST(0x3) << VI_VI_CORE_CONTROL_0_OUTPUT_TO_ISP_SHIFT)
+#define VI_VI_CORE_CONTROL_0_OUTPUT_TO_ISP_RANGE                        1:0
+#define VI_VI_CORE_CONTROL_0_OUTPUT_TO_ISP_WOFFSET                      0x0
+#define VI_VI_CORE_CONTROL_0_OUTPUT_TO_ISP_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_OUTPUT_TO_ISP_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define VI_VI_CORE_CONTROL_0_OUTPUT_TO_ISP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_OUTPUT_TO_ISP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_OUTPUT_TO_ISP_DISABLED                     _MK_ENUM_CONST(0)
+#define VI_VI_CORE_CONTROL_0_OUTPUT_TO_ISP_VIP                  _MK_ENUM_CONST(1)
+#define VI_VI_CORE_CONTROL_0_OUTPUT_TO_ISP_HOST                 _MK_ENUM_CONST(2)
+
+// Output to EPP enable  VI can output a YUV pixel stream to
+//  Encoder Pre-Processor (EPP) module
+//   000= Output to EPP is disabled
+//   001= YUV444 stream after down-scaling
+//   010= YUV444 stream before down-scaling
+//        WARNING: FOR YUV444PRE, only the selects
+//        in INPUT_TO_CORE are supported.  Selects from
+//        INPUT_TO_CORE_EXT are not supported since they
+//        are duplicated in the CSI* selections of this field.
+//   011= YUV444 stream from ISP, no LPF or down-scaling
+//   100= RGB565,RGB444,RGB888 from VIP, no LPF or down-scaling
+//   101= RGB565,RGB888 from Host
+//   110= CSI_PPA
+//   111= CSI_PPB
+#define VI_VI_CORE_CONTROL_0_OUTPUT_TO_EPP_SHIFT                        _MK_SHIFT_CONST(2)
+#define VI_VI_CORE_CONTROL_0_OUTPUT_TO_EPP_FIELD                        (_MK_MASK_CONST(0x7) << VI_VI_CORE_CONTROL_0_OUTPUT_TO_EPP_SHIFT)
+#define VI_VI_CORE_CONTROL_0_OUTPUT_TO_EPP_RANGE                        4:2
+#define VI_VI_CORE_CONTROL_0_OUTPUT_TO_EPP_WOFFSET                      0x0
+#define VI_VI_CORE_CONTROL_0_OUTPUT_TO_EPP_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_OUTPUT_TO_EPP_DEFAULT_MASK                 _MK_MASK_CONST(0x7)
+#define VI_VI_CORE_CONTROL_0_OUTPUT_TO_EPP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_OUTPUT_TO_EPP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_OUTPUT_TO_EPP_DISABLED                     _MK_ENUM_CONST(0)
+#define VI_VI_CORE_CONTROL_0_OUTPUT_TO_EPP_YUV444POST                   _MK_ENUM_CONST(1)
+#define VI_VI_CORE_CONTROL_0_OUTPUT_TO_EPP_YUV444PRE                    _MK_ENUM_CONST(2)
+#define VI_VI_CORE_CONTROL_0_OUTPUT_TO_EPP_YUV444ISP                    _MK_ENUM_CONST(3)
+#define VI_VI_CORE_CONTROL_0_OUTPUT_TO_EPP_RGB                  _MK_ENUM_CONST(4)
+#define VI_VI_CORE_CONTROL_0_OUTPUT_TO_EPP_HOST_RGB                     _MK_ENUM_CONST(5)
+#define VI_VI_CORE_CONTROL_0_OUTPUT_TO_EPP_CSI_PPA                      _MK_ENUM_CONST(6)
+#define VI_VI_CORE_CONTROL_0_OUTPUT_TO_EPP_CSI_PPB                      _MK_ENUM_CONST(7)
+
+// Downsample from YUV444 to YUV422   00 = Cosited, take even UV's for each two Y's.
+//   01 = Cosited, take odd UV's for each two Y's. (Not implemented)
+//   10 = Non Cosited, take even U and odd V, use for Bayer passthru
+//   11 = Averaged, average the odd and even UVs. (Not Implemented)
+#define VI_VI_CORE_CONTROL_0_ISP_DOWNSAMPLE_SHIFT                       _MK_SHIFT_CONST(5)
+#define VI_VI_CORE_CONTROL_0_ISP_DOWNSAMPLE_FIELD                       (_MK_MASK_CONST(0x3) << VI_VI_CORE_CONTROL_0_ISP_DOWNSAMPLE_SHIFT)
+#define VI_VI_CORE_CONTROL_0_ISP_DOWNSAMPLE_RANGE                       6:5
+#define VI_VI_CORE_CONTROL_0_ISP_DOWNSAMPLE_WOFFSET                     0x0
+#define VI_VI_CORE_CONTROL_0_ISP_DOWNSAMPLE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_ISP_DOWNSAMPLE_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define VI_VI_CORE_CONTROL_0_ISP_DOWNSAMPLE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_ISP_DOWNSAMPLE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_ISP_DOWNSAMPLE_COSITED_EVEN                        _MK_ENUM_CONST(0)
+#define VI_VI_CORE_CONTROL_0_ISP_DOWNSAMPLE_COSITED_ODD                 _MK_ENUM_CONST(1)
+#define VI_VI_CORE_CONTROL_0_ISP_DOWNSAMPLE_NONCOSITED                  _MK_ENUM_CONST(2)
+#define VI_VI_CORE_CONTROL_0_ISP_DOWNSAMPLE_AVERAGED                    _MK_ENUM_CONST(3)
+
+// Input to VI Core  Select between possible data input sources
+//   00= Parallel Video Input Port data
+//   01= Host I/F data
+//   10= ISP data, from 444 to 422 converter
+//   11= reserved
+#define VI_VI_CORE_CONTROL_0_INPUT_TO_CORE_SHIFT                        _MK_SHIFT_CONST(8)
+#define VI_VI_CORE_CONTROL_0_INPUT_TO_CORE_FIELD                        (_MK_MASK_CONST(0x3) << VI_VI_CORE_CONTROL_0_INPUT_TO_CORE_SHIFT)
+#define VI_VI_CORE_CONTROL_0_INPUT_TO_CORE_RANGE                        9:8
+#define VI_VI_CORE_CONTROL_0_INPUT_TO_CORE_WOFFSET                      0x0
+#define VI_VI_CORE_CONTROL_0_INPUT_TO_CORE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_INPUT_TO_CORE_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define VI_VI_CORE_CONTROL_0_INPUT_TO_CORE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_INPUT_TO_CORE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_INPUT_TO_CORE_VIP                  _MK_ENUM_CONST(0)
+#define VI_VI_CORE_CONTROL_0_INPUT_TO_CORE_HOST                 _MK_ENUM_CONST(1)
+#define VI_VI_CORE_CONTROL_0_INPUT_TO_CORE_ISP                  _MK_ENUM_CONST(2)
+
+// Planar Conversion Module Input select   0= YUV422 after down-scaling, POST core
+//   1= YUV422 before down-scaling, PRE core
+//
+#define VI_VI_CORE_CONTROL_0_PLANAR_CONV_INPUT_SEL_SHIFT                        _MK_SHIFT_CONST(10)
+#define VI_VI_CORE_CONTROL_0_PLANAR_CONV_INPUT_SEL_FIELD                        (_MK_MASK_CONST(0x1) << VI_VI_CORE_CONTROL_0_PLANAR_CONV_INPUT_SEL_SHIFT)
+#define VI_VI_CORE_CONTROL_0_PLANAR_CONV_INPUT_SEL_RANGE                        10:10
+#define VI_VI_CORE_CONTROL_0_PLANAR_CONV_INPUT_SEL_WOFFSET                      0x0
+#define VI_VI_CORE_CONTROL_0_PLANAR_CONV_INPUT_SEL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_PLANAR_CONV_INPUT_SEL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define VI_VI_CORE_CONTROL_0_PLANAR_CONV_INPUT_SEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_PLANAR_CONV_INPUT_SEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_PLANAR_CONV_INPUT_SEL_YUV422POST                   _MK_ENUM_CONST(0)
+#define VI_VI_CORE_CONTROL_0_PLANAR_CONV_INPUT_SEL_YUV422PRE                    _MK_ENUM_CONST(1)
+
+// Color Space Conversion Input select   0= YUV422 after down-scaling, POST core
+//   1= YUV422 before down-scaling, PRE core
+// 15:12 reserved
+#define VI_VI_CORE_CONTROL_0_CSC_INPUT_SEL_SHIFT                        _MK_SHIFT_CONST(11)
+#define VI_VI_CORE_CONTROL_0_CSC_INPUT_SEL_FIELD                        (_MK_MASK_CONST(0x1) << VI_VI_CORE_CONTROL_0_CSC_INPUT_SEL_SHIFT)
+#define VI_VI_CORE_CONTROL_0_CSC_INPUT_SEL_RANGE                        11:11
+#define VI_VI_CORE_CONTROL_0_CSC_INPUT_SEL_WOFFSET                      0x0
+#define VI_VI_CORE_CONTROL_0_CSC_INPUT_SEL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_CSC_INPUT_SEL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define VI_VI_CORE_CONTROL_0_CSC_INPUT_SEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_CSC_INPUT_SEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_CSC_INPUT_SEL_YUV422POST                   _MK_ENUM_CONST(0)
+#define VI_VI_CORE_CONTROL_0_CSC_INPUT_SEL_YUV422PRE                    _MK_ENUM_CONST(1)
+
+// Horizontal Averaging   0= disabled, H_DOWNSCALING can be used
+//      to enable horizontal downscaling
+//   1= enabled, H_DOWNSCALING is ignored
+//      and horizontal downscaling is
+//      controlled by H_AVG_FACTOR
+#define VI_VI_CORE_CONTROL_0_H_AVERAGING_SHIFT                  _MK_SHIFT_CONST(16)
+#define VI_VI_CORE_CONTROL_0_H_AVERAGING_FIELD                  (_MK_MASK_CONST(0x1) << VI_VI_CORE_CONTROL_0_H_AVERAGING_SHIFT)
+#define VI_VI_CORE_CONTROL_0_H_AVERAGING_RANGE                  16:16
+#define VI_VI_CORE_CONTROL_0_H_AVERAGING_WOFFSET                        0x0
+#define VI_VI_CORE_CONTROL_0_H_AVERAGING_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_H_AVERAGING_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define VI_VI_CORE_CONTROL_0_H_AVERAGING_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_H_AVERAGING_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_H_AVERAGING_DISABLED                       _MK_ENUM_CONST(0)
+#define VI_VI_CORE_CONTROL_0_H_AVERAGING_ENABLED                        _MK_ENUM_CONST(1)
+
+// Horizontal Down-scaling  (effective if H_AVERAGING is DISABLED)
+//   0= disabled
+//   1= enabled and controlled by H_DOWN_M
+//      and H_DOWN_N parameters
+#define VI_VI_CORE_CONTROL_0_H_DOWNSCALING_SHIFT                        _MK_SHIFT_CONST(17)
+#define VI_VI_CORE_CONTROL_0_H_DOWNSCALING_FIELD                        (_MK_MASK_CONST(0x1) << VI_VI_CORE_CONTROL_0_H_DOWNSCALING_SHIFT)
+#define VI_VI_CORE_CONTROL_0_H_DOWNSCALING_RANGE                        17:17
+#define VI_VI_CORE_CONTROL_0_H_DOWNSCALING_WOFFSET                      0x0
+#define VI_VI_CORE_CONTROL_0_H_DOWNSCALING_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_H_DOWNSCALING_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define VI_VI_CORE_CONTROL_0_H_DOWNSCALING_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_H_DOWNSCALING_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_H_DOWNSCALING_DISABLED                     _MK_ENUM_CONST(0)
+#define VI_VI_CORE_CONTROL_0_H_DOWNSCALING_ENABLED                      _MK_ENUM_CONST(1)
+
+// Vertical Averaging   0= disabled, V_DOWNSCALING can be used
+//      to enable vertical downscaling
+//   1= enabled, V_DOWNSCALING is ignored
+//      and vertical downscaling is
+//      controlled by V_AVG_FACTOR
+#define VI_VI_CORE_CONTROL_0_V_AVERAGING_SHIFT                  _MK_SHIFT_CONST(18)
+#define VI_VI_CORE_CONTROL_0_V_AVERAGING_FIELD                  (_MK_MASK_CONST(0x1) << VI_VI_CORE_CONTROL_0_V_AVERAGING_SHIFT)
+#define VI_VI_CORE_CONTROL_0_V_AVERAGING_RANGE                  18:18
+#define VI_VI_CORE_CONTROL_0_V_AVERAGING_WOFFSET                        0x0
+#define VI_VI_CORE_CONTROL_0_V_AVERAGING_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_V_AVERAGING_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define VI_VI_CORE_CONTROL_0_V_AVERAGING_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_V_AVERAGING_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_V_AVERAGING_DISABLED                       _MK_ENUM_CONST(0)
+#define VI_VI_CORE_CONTROL_0_V_AVERAGING_ENABLED                        _MK_ENUM_CONST(1)
+
+// Vertical Down-scaling  (effective if V_AVERAGING is DISABLED)
+//   0= disabled
+//   1= enabled and controlled by V_DOWN_M
+//      and V_DOWN_N parameters
+#define VI_VI_CORE_CONTROL_0_V_DOWNSCALING_SHIFT                        _MK_SHIFT_CONST(19)
+#define VI_VI_CORE_CONTROL_0_V_DOWNSCALING_FIELD                        (_MK_MASK_CONST(0x1) << VI_VI_CORE_CONTROL_0_V_DOWNSCALING_SHIFT)
+#define VI_VI_CORE_CONTROL_0_V_DOWNSCALING_RANGE                        19:19
+#define VI_VI_CORE_CONTROL_0_V_DOWNSCALING_WOFFSET                      0x0
+#define VI_VI_CORE_CONTROL_0_V_DOWNSCALING_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_V_DOWNSCALING_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define VI_VI_CORE_CONTROL_0_V_DOWNSCALING_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_V_DOWNSCALING_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_V_DOWNSCALING_DISABLED                     _MK_ENUM_CONST(0)
+#define VI_VI_CORE_CONTROL_0_V_DOWNSCALING_ENABLED                      _MK_ENUM_CONST(1)
+
+// ISP Host data stall capability is enabled by default  Use this bit to disable the host data stall capability
+//   0= disabled - default allows for VI to turn off
+//                 the ISP clock to stall the Host.
+//   1= enabled - to turn off the VI's ability to stall the Host
+//                when data from ISP comes from Host.
+//
+#define VI_VI_CORE_CONTROL_0_ISP_HOST_STALL_OFF_SHIFT                   _MK_SHIFT_CONST(20)
+#define VI_VI_CORE_CONTROL_0_ISP_HOST_STALL_OFF_FIELD                   (_MK_MASK_CONST(0x1) << VI_VI_CORE_CONTROL_0_ISP_HOST_STALL_OFF_SHIFT)
+#define VI_VI_CORE_CONTROL_0_ISP_HOST_STALL_OFF_RANGE                   20:20
+#define VI_VI_CORE_CONTROL_0_ISP_HOST_STALL_OFF_WOFFSET                 0x0
+#define VI_VI_CORE_CONTROL_0_ISP_HOST_STALL_OFF_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_ISP_HOST_STALL_OFF_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define VI_VI_CORE_CONTROL_0_ISP_HOST_STALL_OFF_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_ISP_HOST_STALL_OFF_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_ISP_HOST_STALL_OFF_DISABLED                        _MK_ENUM_CONST(0)
+#define VI_VI_CORE_CONTROL_0_ISP_HOST_STALL_OFF_ENABLED                 _MK_ENUM_CONST(1)
+
+// Select a data source output to ISP (extension field).
+//   000= Source is selected with OUTPUT_TO_ISP field (backward compatible)
+//   001= CSI Pixel Parser A
+//   010= CSI Pixel Parser B
+#define VI_VI_CORE_CONTROL_0_OUTPUT_TO_ISP_EXT_SHIFT                    _MK_SHIFT_CONST(21)
+#define VI_VI_CORE_CONTROL_0_OUTPUT_TO_ISP_EXT_FIELD                    (_MK_MASK_CONST(0x7) << VI_VI_CORE_CONTROL_0_OUTPUT_TO_ISP_EXT_SHIFT)
+#define VI_VI_CORE_CONTROL_0_OUTPUT_TO_ISP_EXT_RANGE                    23:21
+#define VI_VI_CORE_CONTROL_0_OUTPUT_TO_ISP_EXT_WOFFSET                  0x0
+#define VI_VI_CORE_CONTROL_0_OUTPUT_TO_ISP_EXT_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_OUTPUT_TO_ISP_EXT_DEFAULT_MASK                     _MK_MASK_CONST(0x7)
+#define VI_VI_CORE_CONTROL_0_OUTPUT_TO_ISP_EXT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_OUTPUT_TO_ISP_EXT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_OUTPUT_TO_ISP_EXT_USE_OUTPUT_TO_ISP                        _MK_ENUM_CONST(0)
+#define VI_VI_CORE_CONTROL_0_OUTPUT_TO_ISP_EXT_CSI_PPA                  _MK_ENUM_CONST(1)
+#define VI_VI_CORE_CONTROL_0_OUTPUT_TO_ISP_EXT_CSI_PPB                  _MK_ENUM_CONST(2)
+
+// Select a data source input to core (extension field).
+//   000= Source is selected with INPUT_TO_CORE field (backward compatible)
+//   001= CSI_PPA data in YUV444NP format
+//   010= CSI_PPA data in YUV422NP format
+//   011= CSI_PPB data in YUV444NP format
+//   100= CSI_PPB data in YUV422NP format
+#define VI_VI_CORE_CONTROL_0_INPUT_TO_CORE_EXT_SHIFT                    _MK_SHIFT_CONST(24)
+#define VI_VI_CORE_CONTROL_0_INPUT_TO_CORE_EXT_FIELD                    (_MK_MASK_CONST(0x7) << VI_VI_CORE_CONTROL_0_INPUT_TO_CORE_EXT_SHIFT)
+#define VI_VI_CORE_CONTROL_0_INPUT_TO_CORE_EXT_RANGE                    26:24
+#define VI_VI_CORE_CONTROL_0_INPUT_TO_CORE_EXT_WOFFSET                  0x0
+#define VI_VI_CORE_CONTROL_0_INPUT_TO_CORE_EXT_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_INPUT_TO_CORE_EXT_DEFAULT_MASK                     _MK_MASK_CONST(0x7)
+#define VI_VI_CORE_CONTROL_0_INPUT_TO_CORE_EXT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_INPUT_TO_CORE_EXT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_INPUT_TO_CORE_EXT_USE_INPUT_TO_CORE                        _MK_ENUM_CONST(0)
+#define VI_VI_CORE_CONTROL_0_INPUT_TO_CORE_EXT_CSI_PPA_YUV444                   _MK_ENUM_CONST(1)
+#define VI_VI_CORE_CONTROL_0_INPUT_TO_CORE_EXT_CSI_PPA_YUV422                   _MK_ENUM_CONST(2)
+#define VI_VI_CORE_CONTROL_0_INPUT_TO_CORE_EXT_CSI_PPB_YUV444                   _MK_ENUM_CONST(3)
+#define VI_VI_CORE_CONTROL_0_INPUT_TO_CORE_EXT_CSI_PPB_YUV422                   _MK_ENUM_CONST(4)
+
+
+// Register VI_VI_FIRST_OUTPUT_CONTROL_0  // VI Output Control of YUV/RGB and YUV420P
+#define VI_VI_FIRST_OUTPUT_CONTROL_0                    _MK_ADDR_CONST(0x24)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_WORD_COUNT                         0x1
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_RESET_MASK                         _MK_MASK_CONST(0x3f0107)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_READ_MASK                  _MK_MASK_CONST(0x3f0107)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_WRITE_MASK                         _MK_MASK_CONST(0x3f0107)
+// Output data Format  Take from the CSC Unit:
+//   000= 16-bit RGB (B5G6R5)
+//   001= 16-bit RGB (B5G6R5) Dithered
+//        (This is currently NOT implemented)
+//   010= 24-bit RGB (B8G8R8)
+//  Take from the YUV422 Core output path:
+//      (Same thing as using YUV422PRE and YUV_SOURCE==CORE_OUTPUT)
+//   011= YUV422 non-planar (U8Y8V8Y8) after down-scaling, POST
+//  Take from the YUV422 paths: (see YUV_SOURCE field)
+//   100= YUV422 non-planar (U8Y8V8Y8) before down-scaling, PRE
+//   101= YUV422 Planar
+//   110= YUV420 Planar
+//   111= YUV420 Planar with Averaging
+//        (UV is averaged for each line pair)
+// 7:3 reserved
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_OUTPUT_FORMAT_SHIFT                        _MK_SHIFT_CONST(0)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_OUTPUT_FORMAT_FIELD                        (_MK_MASK_CONST(0x7) << VI_VI_FIRST_OUTPUT_CONTROL_0_OUTPUT_FORMAT_SHIFT)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_OUTPUT_FORMAT_RANGE                        2:0
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_OUTPUT_FORMAT_WOFFSET                      0x0
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_OUTPUT_FORMAT_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_OUTPUT_FORMAT_DEFAULT_MASK                 _MK_MASK_CONST(0x7)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_OUTPUT_FORMAT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_OUTPUT_FORMAT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_OUTPUT_FORMAT_RGB16                        _MK_ENUM_CONST(0)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_OUTPUT_FORMAT_RGB16D                       _MK_ENUM_CONST(1)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_OUTPUT_FORMAT_RGB24                        _MK_ENUM_CONST(2)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_OUTPUT_FORMAT_YUV422POST                   _MK_ENUM_CONST(3)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_OUTPUT_FORMAT_YUV422PRE                    _MK_ENUM_CONST(4)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_OUTPUT_FORMAT_YUV422P                      _MK_ENUM_CONST(5)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_OUTPUT_FORMAT_YUV420P                      _MK_ENUM_CONST(6)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_OUTPUT_FORMAT_YUV420PA                     _MK_ENUM_CONST(7)
+
+// For Planar Output Only, enabling this register  duplicates the last pixel of each line when
+//  the output width is set to an odd number of pixels.
+//  Used when JPEGE/MPEGE which requires valid data filled
+//  to the word(16-bit) boundary.
+//  The Buffer Horizontal Size (Line Stride) must be
+//  set to accomodate the extra pixel.
+//  Example: Disabled - y0,y1,y2,y3,y4
+//           Enabled - y0,y1,y2,y3,y4,y4
+// 15:9 reserved
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_LAST_PIXEL_DUPLICATION_SHIFT                       _MK_SHIFT_CONST(8)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_LAST_PIXEL_DUPLICATION_FIELD                       (_MK_MASK_CONST(0x1) << VI_VI_FIRST_OUTPUT_CONTROL_0_LAST_PIXEL_DUPLICATION_SHIFT)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_LAST_PIXEL_DUPLICATION_RANGE                       8:8
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_LAST_PIXEL_DUPLICATION_WOFFSET                     0x0
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_LAST_PIXEL_DUPLICATION_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_LAST_PIXEL_DUPLICATION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_LAST_PIXEL_DUPLICATION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_LAST_PIXEL_DUPLICATION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_LAST_PIXEL_DUPLICATION_DISABLED                    _MK_ENUM_CONST(0)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_LAST_PIXEL_DUPLICATION_ENABLED                     _MK_ENUM_CONST(1)
+
+// Output Byte Swap  (effective if input source is host)
+//   0= disabled
+//   1= enabled
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_OUTPUT_BYTE_SWAP_SHIFT                     _MK_SHIFT_CONST(16)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_OUTPUT_BYTE_SWAP_FIELD                     (_MK_MASK_CONST(0x1) << VI_VI_FIRST_OUTPUT_CONTROL_0_OUTPUT_BYTE_SWAP_SHIFT)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_OUTPUT_BYTE_SWAP_RANGE                     16:16
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_OUTPUT_BYTE_SWAP_WOFFSET                   0x0
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_OUTPUT_BYTE_SWAP_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_OUTPUT_BYTE_SWAP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_OUTPUT_BYTE_SWAP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_OUTPUT_BYTE_SWAP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_OUTPUT_BYTE_SWAP_DISABLED                  _MK_ENUM_CONST(0)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_OUTPUT_BYTE_SWAP_ENABLED                   _MK_ENUM_CONST(1)
+
+// YUV Output Format This is applicable when output format is
+// non-planar YUV422.
+//   00= UYVY => Y1_V0_Y1_U0 MSB to LSB 32bit mapping
+//   01= VYUY => Y1_U0_Y1_V0
+//   10= YUYV => V0_Y1_U0_Y0
+//   11= YVYU => U0_Y1_V0_Y0
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_YUV_OUTPUT_FORMAT_SHIFT                    _MK_SHIFT_CONST(17)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_YUV_OUTPUT_FORMAT_FIELD                    (_MK_MASK_CONST(0x3) << VI_VI_FIRST_OUTPUT_CONTROL_0_YUV_OUTPUT_FORMAT_SHIFT)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_YUV_OUTPUT_FORMAT_RANGE                    18:17
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_YUV_OUTPUT_FORMAT_WOFFSET                  0x0
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_YUV_OUTPUT_FORMAT_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_YUV_OUTPUT_FORMAT_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_YUV_OUTPUT_FORMAT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_YUV_OUTPUT_FORMAT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_YUV_OUTPUT_FORMAT_UYVY                     _MK_ENUM_CONST(0)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_YUV_OUTPUT_FORMAT_VYUY                     _MK_ENUM_CONST(1)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_YUV_OUTPUT_FORMAT_YUYV                     _MK_ENUM_CONST(2)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_YUV_OUTPUT_FORMAT_YVYU                     _MK_ENUM_CONST(3)
+
+//  H-direction in internal memory
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_H_DIRECTION_SHIFT                  _MK_SHIFT_CONST(19)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_H_DIRECTION_FIELD                  (_MK_MASK_CONST(0x1) << VI_VI_FIRST_OUTPUT_CONTROL_0_H_DIRECTION_SHIFT)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_H_DIRECTION_RANGE                  19:19
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_H_DIRECTION_WOFFSET                        0x0
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_H_DIRECTION_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_H_DIRECTION_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_H_DIRECTION_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_H_DIRECTION_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  V-direction in internal memory
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_V_DIRECTION_SHIFT                  _MK_SHIFT_CONST(20)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_V_DIRECTION_FIELD                  (_MK_MASK_CONST(0x1) << VI_VI_FIRST_OUTPUT_CONTROL_0_V_DIRECTION_SHIFT)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_V_DIRECTION_RANGE                  20:20
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_V_DIRECTION_WOFFSET                        0x0
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_V_DIRECTION_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_V_DIRECTION_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_V_DIRECTION_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_V_DIRECTION_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  XY-Swap in internal memory
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_XY_SWAP_SHIFT                      _MK_SHIFT_CONST(21)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_XY_SWAP_FIELD                      (_MK_MASK_CONST(0x1) << VI_VI_FIRST_OUTPUT_CONTROL_0_XY_SWAP_SHIFT)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_XY_SWAP_RANGE                      21:21
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_XY_SWAP_WOFFSET                    0x0
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_XY_SWAP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_XY_SWAP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_XY_SWAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_XY_SWAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register VI_VI_SECOND_OUTPUT_CONTROL_0  // VI Second Output Control of YUV422NP and RGB
+#define VI_VI_SECOND_OUTPUT_CONTROL_0                   _MK_ADDR_CONST(0x25)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_WORD_COUNT                        0x1
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_RESET_MASK                        _MK_MASK_CONST(0x3f000f)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_READ_MASK                         _MK_MASK_CONST(0x3f000f)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_WRITE_MASK                        _MK_MASK_CONST(0x3f000f)
+// Secondary Output to MC  Use case: when VI needs to send decimated preview data
+//  and at the same time send non-decimated data
+//  to the memory for StretchBLT, meanwhile the StretchBLT
+//  is sending EPP stretched data to be encoded.
+//  Only YUV422, RGB888, RGB565 is supported
+//
+//  Take from the CSC Unit
+//  0000= 16-bit RGB (B5G6R5), all RGB data can be pre or
+//        post decimated depending on mux select programming
+//        on the input to the Color Space Converter
+//  0001= 16-bit RGB (B5G6R5) Dithered
+//        (This is currently NOT implemented)
+//  0010= 24-bit RGB (B8G8R8)
+//  Take from the YUV422 Core output path:
+//      (Same thing as using YUV422PRE and YUV_SOURCE==CORE_OUTPUT)
+//  0011= YUV422 stream after down-scaling, POST
+//  Take from the YUV422 paths: (see YUV_SOURCE field)
+//  0100= YUV422 stream before down-scaling, PRE
+//  Take from the WriteBuffer interface logic, which is used for JPEG Stream
+//  0101= JPEG Stream (Pattern A,B,C)
+//  0110= VIP Bayer     direct to memory as a 16-bit value {6'b0, VIP_pad[9:0]}
+//  0111= CSI_PPA Bayer direct to memory as a 16-bit value {6'b0, CSI_SVD[15:6]}
+//  1000= CSI_PPB Bayer direct to memory as a 16-bit value {6'b0, CSI_SVD[15:6]}
+// 15:4 reserved
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_OUTPUT_FORMAT_SHIFT                        _MK_SHIFT_CONST(0)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_OUTPUT_FORMAT_FIELD                        (_MK_MASK_CONST(0xf) << VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_OUTPUT_FORMAT_SHIFT)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_OUTPUT_FORMAT_RANGE                        3:0
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_OUTPUT_FORMAT_WOFFSET                      0x0
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_OUTPUT_FORMAT_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_OUTPUT_FORMAT_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_OUTPUT_FORMAT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_OUTPUT_FORMAT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_OUTPUT_FORMAT_RGB16                        _MK_ENUM_CONST(0)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_OUTPUT_FORMAT_RGB16D                       _MK_ENUM_CONST(1)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_OUTPUT_FORMAT_RGB24                        _MK_ENUM_CONST(2)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_OUTPUT_FORMAT_YUV422POST                   _MK_ENUM_CONST(3)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_OUTPUT_FORMAT_YUV422PRE                    _MK_ENUM_CONST(4)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_OUTPUT_FORMAT_JPEG_STREAM                  _MK_ENUM_CONST(5)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_OUTPUT_FORMAT_VIP_BAYER                    _MK_ENUM_CONST(6)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_OUTPUT_FORMAT_CSI_PPA_BAYER                        _MK_ENUM_CONST(7)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_OUTPUT_FORMAT_CSI_PPB_BAYER                        _MK_ENUM_CONST(8)
+
+// Output Byte Swap  (effective if input source is host)
+//   0= disabled
+//   1= enabled
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_OUTPUT_BYTE_SWAP_SHIFT                     _MK_SHIFT_CONST(16)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_OUTPUT_BYTE_SWAP_FIELD                     (_MK_MASK_CONST(0x1) << VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_OUTPUT_BYTE_SWAP_SHIFT)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_OUTPUT_BYTE_SWAP_RANGE                     16:16
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_OUTPUT_BYTE_SWAP_WOFFSET                   0x0
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_OUTPUT_BYTE_SWAP_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_OUTPUT_BYTE_SWAP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_OUTPUT_BYTE_SWAP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_OUTPUT_BYTE_SWAP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_OUTPUT_BYTE_SWAP_DISABLED                  _MK_ENUM_CONST(0)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_OUTPUT_BYTE_SWAP_ENABLED                   _MK_ENUM_CONST(1)
+
+// YUV Second Output Format This is applicable when output format is
+// non-planar YUV422.
+//   00= UYVY => Y1_V0_Y1_U0 MSB to LSB 32bit mapping
+//   01= VYUY => Y1_U0_Y1_V0
+//   10= YUYV => V0_Y1_U0_Y0
+//   11= YVYU => U0_Y1_V0_Y0
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_YUV_SECOND_OUTPUT_FORMAT_SHIFT                    _MK_SHIFT_CONST(17)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_YUV_SECOND_OUTPUT_FORMAT_FIELD                    (_MK_MASK_CONST(0x3) << VI_VI_SECOND_OUTPUT_CONTROL_0_YUV_SECOND_OUTPUT_FORMAT_SHIFT)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_YUV_SECOND_OUTPUT_FORMAT_RANGE                    18:17
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_YUV_SECOND_OUTPUT_FORMAT_WOFFSET                  0x0
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_YUV_SECOND_OUTPUT_FORMAT_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_YUV_SECOND_OUTPUT_FORMAT_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_YUV_SECOND_OUTPUT_FORMAT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_YUV_SECOND_OUTPUT_FORMAT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_YUV_SECOND_OUTPUT_FORMAT_UYVY                     _MK_ENUM_CONST(0)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_YUV_SECOND_OUTPUT_FORMAT_VYUY                     _MK_ENUM_CONST(1)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_YUV_SECOND_OUTPUT_FORMAT_YUYV                     _MK_ENUM_CONST(2)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_YUV_SECOND_OUTPUT_FORMAT_YVYU                     _MK_ENUM_CONST(3)
+
+//  Second output's H-direction in internal memory
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_H_DIRECTION_SHIFT                  _MK_SHIFT_CONST(19)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_H_DIRECTION_FIELD                  (_MK_MASK_CONST(0x1) << VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_H_DIRECTION_SHIFT)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_H_DIRECTION_RANGE                  19:19
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_H_DIRECTION_WOFFSET                        0x0
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_H_DIRECTION_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_H_DIRECTION_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_H_DIRECTION_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_H_DIRECTION_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  Second output's V-direction in internal memory
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_V_DIRECTION_SHIFT                  _MK_SHIFT_CONST(20)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_V_DIRECTION_FIELD                  (_MK_MASK_CONST(0x1) << VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_V_DIRECTION_SHIFT)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_V_DIRECTION_RANGE                  20:20
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_V_DIRECTION_WOFFSET                        0x0
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_V_DIRECTION_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_V_DIRECTION_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_V_DIRECTION_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_V_DIRECTION_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  Second output's XY-Swap in internal memory
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_XY_SWAP_SHIFT                      _MK_SHIFT_CONST(21)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_XY_SWAP_FIELD                      (_MK_MASK_CONST(0x1) << VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_XY_SWAP_SHIFT)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_XY_SWAP_RANGE                      21:21
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_XY_SWAP_WOFFSET                    0x0
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_XY_SWAP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_XY_SWAP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_XY_SWAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_XY_SWAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register VI_HOST_INPUT_FRAME_SIZE_0  // Host Input Frame Width
+#define VI_HOST_INPUT_FRAME_SIZE_0                      _MK_ADDR_CONST(0x26)
+#define VI_HOST_INPUT_FRAME_SIZE_0_WORD_COUNT                   0x1
+#define VI_HOST_INPUT_FRAME_SIZE_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define VI_HOST_INPUT_FRAME_SIZE_0_RESET_MASK                   _MK_MASK_CONST(0x0)
+#define VI_HOST_INPUT_FRAME_SIZE_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define VI_HOST_INPUT_FRAME_SIZE_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_HOST_INPUT_FRAME_SIZE_0_READ_MASK                    _MK_MASK_CONST(0x1fff1fff)
+#define VI_HOST_INPUT_FRAME_SIZE_0_WRITE_MASK                   _MK_MASK_CONST(0x1fff1fff)
+// Specifies in terms of pixels the width of
+// the input data coming from host.
+#define VI_HOST_INPUT_FRAME_SIZE_0_INPUT_FRAME_WIDTH_SHIFT                      _MK_SHIFT_CONST(0)
+#define VI_HOST_INPUT_FRAME_SIZE_0_INPUT_FRAME_WIDTH_FIELD                      (_MK_MASK_CONST(0x1fff) << VI_HOST_INPUT_FRAME_SIZE_0_INPUT_FRAME_WIDTH_SHIFT)
+#define VI_HOST_INPUT_FRAME_SIZE_0_INPUT_FRAME_WIDTH_RANGE                      12:0
+#define VI_HOST_INPUT_FRAME_SIZE_0_INPUT_FRAME_WIDTH_WOFFSET                    0x0
+#define VI_HOST_INPUT_FRAME_SIZE_0_INPUT_FRAME_WIDTH_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_HOST_INPUT_FRAME_SIZE_0_INPUT_FRAME_WIDTH_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_HOST_INPUT_FRAME_SIZE_0_INPUT_FRAME_WIDTH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_HOST_INPUT_FRAME_SIZE_0_INPUT_FRAME_WIDTH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Host Input Frame Height
+// Specifies in terms of lines the height of
+// the input data coming from host.
+#define VI_HOST_INPUT_FRAME_SIZE_0_INPUT_FRAME_HEIGHT_SHIFT                     _MK_SHIFT_CONST(16)
+#define VI_HOST_INPUT_FRAME_SIZE_0_INPUT_FRAME_HEIGHT_FIELD                     (_MK_MASK_CONST(0x1fff) << VI_HOST_INPUT_FRAME_SIZE_0_INPUT_FRAME_HEIGHT_SHIFT)
+#define VI_HOST_INPUT_FRAME_SIZE_0_INPUT_FRAME_HEIGHT_RANGE                     28:16
+#define VI_HOST_INPUT_FRAME_SIZE_0_INPUT_FRAME_HEIGHT_WOFFSET                   0x0
+#define VI_HOST_INPUT_FRAME_SIZE_0_INPUT_FRAME_HEIGHT_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_HOST_INPUT_FRAME_SIZE_0_INPUT_FRAME_HEIGHT_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_HOST_INPUT_FRAME_SIZE_0_INPUT_FRAME_HEIGHT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_HOST_INPUT_FRAME_SIZE_0_INPUT_FRAME_HEIGHT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register VI_HOST_H_ACTIVE_0  // VI Horizontal Active
+#define VI_HOST_H_ACTIVE_0                      _MK_ADDR_CONST(0x27)
+#define VI_HOST_H_ACTIVE_0_WORD_COUNT                   0x1
+#define VI_HOST_H_ACTIVE_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define VI_HOST_H_ACTIVE_0_RESET_MASK                   _MK_MASK_CONST(0x0)
+#define VI_HOST_H_ACTIVE_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define VI_HOST_H_ACTIVE_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_HOST_H_ACTIVE_0_READ_MASK                    _MK_MASK_CONST(0x1fff1fff)
+#define VI_HOST_H_ACTIVE_0_WRITE_MASK                   _MK_MASK_CONST(0x1fff1fff)
+// Horizontal Active Start (offset to active)
+//  This parameter specifies the number of
+//  pixels to be discarded until the first
+//  active pixel. If programmed to 0, the
+//  first active pixel is the first pixel popped
+//  from the Host YUV FIFO.
+#define VI_HOST_H_ACTIVE_0_HOST_H_ACTIVE_START_SHIFT                    _MK_SHIFT_CONST(0)
+#define VI_HOST_H_ACTIVE_0_HOST_H_ACTIVE_START_FIELD                    (_MK_MASK_CONST(0x1fff) << VI_HOST_H_ACTIVE_0_HOST_H_ACTIVE_START_SHIFT)
+#define VI_HOST_H_ACTIVE_0_HOST_H_ACTIVE_START_RANGE                    12:0
+#define VI_HOST_H_ACTIVE_0_HOST_H_ACTIVE_START_WOFFSET                  0x0
+#define VI_HOST_H_ACTIVE_0_HOST_H_ACTIVE_START_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_HOST_H_ACTIVE_0_HOST_H_ACTIVE_START_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_HOST_H_ACTIVE_0_HOST_H_ACTIVE_START_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_HOST_H_ACTIVE_0_HOST_H_ACTIVE_START_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Horizontal Active Period
+//  This parameter specifies the number of
+//  pixels in the horizontal active area.
+//  H_ACTIVE_START + H_ACTIVE_PERIOD should be
+//  less than 2^NV_VI_H_IN (or 8192) This parameter
+//  should be programmed with an even number
+//  (bit 16 is ignored internally).
+#define VI_HOST_H_ACTIVE_0_HOST_H_ACTIVE_PERIOD_SHIFT                   _MK_SHIFT_CONST(16)
+#define VI_HOST_H_ACTIVE_0_HOST_H_ACTIVE_PERIOD_FIELD                   (_MK_MASK_CONST(0x1fff) << VI_HOST_H_ACTIVE_0_HOST_H_ACTIVE_PERIOD_SHIFT)
+#define VI_HOST_H_ACTIVE_0_HOST_H_ACTIVE_PERIOD_RANGE                   28:16
+#define VI_HOST_H_ACTIVE_0_HOST_H_ACTIVE_PERIOD_WOFFSET                 0x0
+#define VI_HOST_H_ACTIVE_0_HOST_H_ACTIVE_PERIOD_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_HOST_H_ACTIVE_0_HOST_H_ACTIVE_PERIOD_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_HOST_H_ACTIVE_0_HOST_H_ACTIVE_PERIOD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_HOST_H_ACTIVE_0_HOST_H_ACTIVE_PERIOD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register VI_HOST_V_ACTIVE_0  // Vertical Active
+#define VI_HOST_V_ACTIVE_0                      _MK_ADDR_CONST(0x28)
+#define VI_HOST_V_ACTIVE_0_WORD_COUNT                   0x1
+#define VI_HOST_V_ACTIVE_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define VI_HOST_V_ACTIVE_0_RESET_MASK                   _MK_MASK_CONST(0x0)
+#define VI_HOST_V_ACTIVE_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define VI_HOST_V_ACTIVE_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_HOST_V_ACTIVE_0_READ_MASK                    _MK_MASK_CONST(0x1fff1fff)
+#define VI_HOST_V_ACTIVE_0_WRITE_MASK                   _MK_MASK_CONST(0x1fff1fff)
+// Vertical Active Start (offset to active)
+//  This parameter specifies the number of
+//  horizontal sync active edges from vertical
+//  sync active edge to the first vertical
+//  active line. If programmed to 0, the
+//  first active line starts after the first
+//  horizontal sync active edge following
+//  the vertical sync active edge.
+#define VI_HOST_V_ACTIVE_0_HOST_V_ACTIVE_START_SHIFT                    _MK_SHIFT_CONST(0)
+#define VI_HOST_V_ACTIVE_0_HOST_V_ACTIVE_START_FIELD                    (_MK_MASK_CONST(0x1fff) << VI_HOST_V_ACTIVE_0_HOST_V_ACTIVE_START_SHIFT)
+#define VI_HOST_V_ACTIVE_0_HOST_V_ACTIVE_START_RANGE                    12:0
+#define VI_HOST_V_ACTIVE_0_HOST_V_ACTIVE_START_WOFFSET                  0x0
+#define VI_HOST_V_ACTIVE_0_HOST_V_ACTIVE_START_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_HOST_V_ACTIVE_0_HOST_V_ACTIVE_START_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_HOST_V_ACTIVE_0_HOST_V_ACTIVE_START_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_HOST_V_ACTIVE_0_HOST_V_ACTIVE_START_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Vertical Active Period
+//  This parameter specifies the number of
+//  lines in the vertical active area.
+//  V_ACTIVE_START + V_ACTIVE_PERIOD should be
+//  less than 2^NV_VI_V_IN (or 8192).
+#define VI_HOST_V_ACTIVE_0_HOST_V_ACTIVE_PERIOD_SHIFT                   _MK_SHIFT_CONST(16)
+#define VI_HOST_V_ACTIVE_0_HOST_V_ACTIVE_PERIOD_FIELD                   (_MK_MASK_CONST(0x1fff) << VI_HOST_V_ACTIVE_0_HOST_V_ACTIVE_PERIOD_SHIFT)
+#define VI_HOST_V_ACTIVE_0_HOST_V_ACTIVE_PERIOD_RANGE                   28:16
+#define VI_HOST_V_ACTIVE_0_HOST_V_ACTIVE_PERIOD_WOFFSET                 0x0
+#define VI_HOST_V_ACTIVE_0_HOST_V_ACTIVE_PERIOD_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_HOST_V_ACTIVE_0_HOST_V_ACTIVE_PERIOD_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_HOST_V_ACTIVE_0_HOST_V_ACTIVE_PERIOD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_HOST_V_ACTIVE_0_HOST_V_ACTIVE_PERIOD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register VI_VIP_H_ACTIVE_0  // VI Horizontal Active
+#define VI_VIP_H_ACTIVE_0                       _MK_ADDR_CONST(0x29)
+#define VI_VIP_H_ACTIVE_0_WORD_COUNT                    0x1
+#define VI_VIP_H_ACTIVE_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define VI_VIP_H_ACTIVE_0_RESET_MASK                    _MK_MASK_CONST(0x0)
+#define VI_VIP_H_ACTIVE_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define VI_VIP_H_ACTIVE_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_VIP_H_ACTIVE_0_READ_MASK                     _MK_MASK_CONST(0x1fff1fff)
+#define VI_VIP_H_ACTIVE_0_WRITE_MASK                    _MK_MASK_CONST(0x1fff1fff)
+// Horizontal Active Start (offset to active)
+//  This parameter specifies the number of
+//  clock active edges from horizontal
+//  sync active edge to the first horizontal
+//  active pixel. If programmed to 0, the
+//  first active line starts after the first
+//  active clock edge following the horizontal
+//  sync active edge.
+#define VI_VIP_H_ACTIVE_0_VIP_H_ACTIVE_START_SHIFT                      _MK_SHIFT_CONST(0)
+#define VI_VIP_H_ACTIVE_0_VIP_H_ACTIVE_START_FIELD                      (_MK_MASK_CONST(0x1fff) << VI_VIP_H_ACTIVE_0_VIP_H_ACTIVE_START_SHIFT)
+#define VI_VIP_H_ACTIVE_0_VIP_H_ACTIVE_START_RANGE                      12:0
+#define VI_VIP_H_ACTIVE_0_VIP_H_ACTIVE_START_WOFFSET                    0x0
+#define VI_VIP_H_ACTIVE_0_VIP_H_ACTIVE_START_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_VIP_H_ACTIVE_0_VIP_H_ACTIVE_START_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_VIP_H_ACTIVE_0_VIP_H_ACTIVE_START_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_VIP_H_ACTIVE_0_VIP_H_ACTIVE_START_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Horizontal Active Period
+//  This parameter specifies the number of
+//  pixels in the horizontal active area.
+//  Bug #178631
+//  The value is the END of the active region,
+//  so PERIOD-START = active area
+//  This parameter should be programmed
+//  with an even number
+#define VI_VIP_H_ACTIVE_0_VIP_H_ACTIVE_PERIOD_SHIFT                     _MK_SHIFT_CONST(16)
+#define VI_VIP_H_ACTIVE_0_VIP_H_ACTIVE_PERIOD_FIELD                     (_MK_MASK_CONST(0x1fff) << VI_VIP_H_ACTIVE_0_VIP_H_ACTIVE_PERIOD_SHIFT)
+#define VI_VIP_H_ACTIVE_0_VIP_H_ACTIVE_PERIOD_RANGE                     28:16
+#define VI_VIP_H_ACTIVE_0_VIP_H_ACTIVE_PERIOD_WOFFSET                   0x0
+#define VI_VIP_H_ACTIVE_0_VIP_H_ACTIVE_PERIOD_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_VIP_H_ACTIVE_0_VIP_H_ACTIVE_PERIOD_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_VIP_H_ACTIVE_0_VIP_H_ACTIVE_PERIOD_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_VIP_H_ACTIVE_0_VIP_H_ACTIVE_PERIOD_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register VI_VIP_V_ACTIVE_0  // Vertical Active
+#define VI_VIP_V_ACTIVE_0                       _MK_ADDR_CONST(0x2a)
+#define VI_VIP_V_ACTIVE_0_WORD_COUNT                    0x1
+#define VI_VIP_V_ACTIVE_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define VI_VIP_V_ACTIVE_0_RESET_MASK                    _MK_MASK_CONST(0x0)
+#define VI_VIP_V_ACTIVE_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define VI_VIP_V_ACTIVE_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_VIP_V_ACTIVE_0_READ_MASK                     _MK_MASK_CONST(0x1fff1fff)
+#define VI_VIP_V_ACTIVE_0_WRITE_MASK                    _MK_MASK_CONST(0x1fff1fff)
+// Vertical Active Start (offset to active)
+//  This parameter specifies the number of
+//  horizontal sync active edges from vertical
+//  sync active edge to the first vertical
+//  active line. If programmed to 0, the
+//  first active line starts after the first
+//  horizontal sync active edge following
+//  the vertical sync active edge.
+#define VI_VIP_V_ACTIVE_0_VIP_V_ACTIVE_START_SHIFT                      _MK_SHIFT_CONST(0)
+#define VI_VIP_V_ACTIVE_0_VIP_V_ACTIVE_START_FIELD                      (_MK_MASK_CONST(0x1fff) << VI_VIP_V_ACTIVE_0_VIP_V_ACTIVE_START_SHIFT)
+#define VI_VIP_V_ACTIVE_0_VIP_V_ACTIVE_START_RANGE                      12:0
+#define VI_VIP_V_ACTIVE_0_VIP_V_ACTIVE_START_WOFFSET                    0x0
+#define VI_VIP_V_ACTIVE_0_VIP_V_ACTIVE_START_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_VIP_V_ACTIVE_0_VIP_V_ACTIVE_START_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_VIP_V_ACTIVE_0_VIP_V_ACTIVE_START_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_VIP_V_ACTIVE_0_VIP_V_ACTIVE_START_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Vertical Active Period
+//  This parameter specifies the number of
+//  lines in the vertical active area.
+//  Bug #178631
+//  The value is the END of the active region,
+//  so PERIOD-START = active area
+#define VI_VIP_V_ACTIVE_0_VIP_V_ACTIVE_PERIOD_SHIFT                     _MK_SHIFT_CONST(16)
+#define VI_VIP_V_ACTIVE_0_VIP_V_ACTIVE_PERIOD_FIELD                     (_MK_MASK_CONST(0x1fff) << VI_VIP_V_ACTIVE_0_VIP_V_ACTIVE_PERIOD_SHIFT)
+#define VI_VIP_V_ACTIVE_0_VIP_V_ACTIVE_PERIOD_RANGE                     28:16
+#define VI_VIP_V_ACTIVE_0_VIP_V_ACTIVE_PERIOD_WOFFSET                   0x0
+#define VI_VIP_V_ACTIVE_0_VIP_V_ACTIVE_PERIOD_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_VIP_V_ACTIVE_0_VIP_V_ACTIVE_PERIOD_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_VIP_V_ACTIVE_0_VIP_V_ACTIVE_PERIOD_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_VIP_V_ACTIVE_0_VIP_V_ACTIVE_PERIOD_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register VI_VI_PEER_CONTROL_0  // VI Peer to Peer Control
+// For all fields:
+//   00= Disabled
+//   01= First memory
+//   10= Second memory
+//   11= not defined
+#define VI_VI_PEER_CONTROL_0                    _MK_ADDR_CONST(0x2b)
+#define VI_VI_PEER_CONTROL_0_WORD_COUNT                         0x1
+#define VI_VI_PEER_CONTROL_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define VI_VI_PEER_CONTROL_0_RESET_MASK                         _MK_MASK_CONST(0xff)
+#define VI_VI_PEER_CONTROL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define VI_VI_PEER_CONTROL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_VI_PEER_CONTROL_0_READ_MASK                  _MK_MASK_CONST(0xff)
+#define VI_VI_PEER_CONTROL_0_WRITE_MASK                         _MK_MASK_CONST(0xff)
+// VI to Display Control Bus enable  VI will send a valid buffer signal
+//  along with Y,U,V buffer addresses
+//  and Frame Start and Frame End
+#define VI_VI_PEER_CONTROL_0_DISPLAY_CONTROL_SHIFT                      _MK_SHIFT_CONST(0)
+#define VI_VI_PEER_CONTROL_0_DISPLAY_CONTROL_FIELD                      (_MK_MASK_CONST(0x3) << VI_VI_PEER_CONTROL_0_DISPLAY_CONTROL_SHIFT)
+#define VI_VI_PEER_CONTROL_0_DISPLAY_CONTROL_RANGE                      1:0
+#define VI_VI_PEER_CONTROL_0_DISPLAY_CONTROL_WOFFSET                    0x0
+#define VI_VI_PEER_CONTROL_0_DISPLAY_CONTROL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_VI_PEER_CONTROL_0_DISPLAY_CONTROL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define VI_VI_PEER_CONTROL_0_DISPLAY_CONTROL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_VI_PEER_CONTROL_0_DISPLAY_CONTROL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_VI_PEER_CONTROL_0_DISPLAY_CONTROL_DISABLED                   _MK_ENUM_CONST(0)
+#define VI_VI_PEER_CONTROL_0_DISPLAY_CONTROL_FIRST                      _MK_ENUM_CONST(1)
+#define VI_VI_PEER_CONTROL_0_DISPLAY_CONTROL_SECOND                     _MK_ENUM_CONST(2)
+
+// VI to JPEGE & MPEGE Control Bus enable  VI will send a valid buffer signal
+//  along with buffer index
+//  and Frame Start and Frame End
+#define VI_VI_PEER_CONTROL_0_ENCODER_CONTROL_SHIFT                      _MK_SHIFT_CONST(2)
+#define VI_VI_PEER_CONTROL_0_ENCODER_CONTROL_FIELD                      (_MK_MASK_CONST(0x3) << VI_VI_PEER_CONTROL_0_ENCODER_CONTROL_SHIFT)
+#define VI_VI_PEER_CONTROL_0_ENCODER_CONTROL_RANGE                      3:2
+#define VI_VI_PEER_CONTROL_0_ENCODER_CONTROL_WOFFSET                    0x0
+#define VI_VI_PEER_CONTROL_0_ENCODER_CONTROL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_VI_PEER_CONTROL_0_ENCODER_CONTROL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define VI_VI_PEER_CONTROL_0_ENCODER_CONTROL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_VI_PEER_CONTROL_0_ENCODER_CONTROL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_VI_PEER_CONTROL_0_ENCODER_CONTROL_DISABLED                   _MK_ENUM_CONST(0)
+#define VI_VI_PEER_CONTROL_0_ENCODER_CONTROL_FIRST                      _MK_ENUM_CONST(1)
+#define VI_VI_PEER_CONTROL_0_ENCODER_CONTROL_SECOND                     _MK_ENUM_CONST(2)
+
+// VI to StretchBLT Control Bus enable  VI will send a valid buffer signal
+//  along with buffer index
+//  and Frame Start and Frame End
+//  The VI to SB control bus is separate from
+//  the VI to JPEGE/MPEGE bus.  This control
+//  bus is controlled by the "2nd Output to
+//  MC" write client interface.
+#define VI_VI_PEER_CONTROL_0_SB_CONTROL_SHIFT                   _MK_SHIFT_CONST(4)
+#define VI_VI_PEER_CONTROL_0_SB_CONTROL_FIELD                   (_MK_MASK_CONST(0x3) << VI_VI_PEER_CONTROL_0_SB_CONTROL_SHIFT)
+#define VI_VI_PEER_CONTROL_0_SB_CONTROL_RANGE                   5:4
+#define VI_VI_PEER_CONTROL_0_SB_CONTROL_WOFFSET                 0x0
+#define VI_VI_PEER_CONTROL_0_SB_CONTROL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_VI_PEER_CONTROL_0_SB_CONTROL_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define VI_VI_PEER_CONTROL_0_SB_CONTROL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_VI_PEER_CONTROL_0_SB_CONTROL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_VI_PEER_CONTROL_0_SB_CONTROL_DISABLED                        _MK_ENUM_CONST(0)
+#define VI_VI_PEER_CONTROL_0_SB_CONTROL_FIRST                   _MK_ENUM_CONST(1)
+#define VI_VI_PEER_CONTROL_0_SB_CONTROL_SECOND                  _MK_ENUM_CONST(2)
+
+// VI to Display B Control Bus enable  VI will send a valid buffer signal
+//  along with Y,U,V buffer addresses
+//  and Frame Start and Frame End
+#define VI_VI_PEER_CONTROL_0_DISPLAY_B_CONTROL_SHIFT                    _MK_SHIFT_CONST(6)
+#define VI_VI_PEER_CONTROL_0_DISPLAY_B_CONTROL_FIELD                    (_MK_MASK_CONST(0x3) << VI_VI_PEER_CONTROL_0_DISPLAY_B_CONTROL_SHIFT)
+#define VI_VI_PEER_CONTROL_0_DISPLAY_B_CONTROL_RANGE                    7:6
+#define VI_VI_PEER_CONTROL_0_DISPLAY_B_CONTROL_WOFFSET                  0x0
+#define VI_VI_PEER_CONTROL_0_DISPLAY_B_CONTROL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_VI_PEER_CONTROL_0_DISPLAY_B_CONTROL_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define VI_VI_PEER_CONTROL_0_DISPLAY_B_CONTROL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_VI_PEER_CONTROL_0_DISPLAY_B_CONTROL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_VI_PEER_CONTROL_0_DISPLAY_B_CONTROL_DISABLED                 _MK_ENUM_CONST(0)
+#define VI_VI_PEER_CONTROL_0_DISPLAY_B_CONTROL_FIRST                    _MK_ENUM_CONST(1)
+#define VI_VI_PEER_CONTROL_0_DISPLAY_B_CONTROL_SECOND                   _MK_ENUM_CONST(2)
+
+
+// Register VI_VI_DMA_SELECT_0  // Host DMA select
+#define VI_VI_DMA_SELECT_0                      _MK_ADDR_CONST(0x2c)
+#define VI_VI_DMA_SELECT_0_WORD_COUNT                   0x1
+#define VI_VI_DMA_SELECT_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define VI_VI_DMA_SELECT_0_RESET_MASK                   _MK_MASK_CONST(0x3)
+#define VI_VI_DMA_SELECT_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define VI_VI_DMA_SELECT_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_VI_DMA_SELECT_0_READ_MASK                    _MK_MASK_CONST(0x3)
+#define VI_VI_DMA_SELECT_0_WRITE_MASK                   _MK_MASK_CONST(0x3)
+// Host DMA Request enable at end of block  Request to host DMA can be enabled every
+//  time a block of video input data is
+//  written to memory.
+//   00= Disabled
+//   01= Write Buffer DMA for RAW data stream
+//   10= First memory
+//   11= Second memory
+#define VI_VI_DMA_SELECT_0_DMA_REQUEST_SHIFT                    _MK_SHIFT_CONST(0)
+#define VI_VI_DMA_SELECT_0_DMA_REQUEST_FIELD                    (_MK_MASK_CONST(0x3) << VI_VI_DMA_SELECT_0_DMA_REQUEST_SHIFT)
+#define VI_VI_DMA_SELECT_0_DMA_REQUEST_RANGE                    1:0
+#define VI_VI_DMA_SELECT_0_DMA_REQUEST_WOFFSET                  0x0
+#define VI_VI_DMA_SELECT_0_DMA_REQUEST_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_VI_DMA_SELECT_0_DMA_REQUEST_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define VI_VI_DMA_SELECT_0_DMA_REQUEST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_VI_DMA_SELECT_0_DMA_REQUEST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_VI_DMA_SELECT_0_DMA_REQUEST_DISABLED                 _MK_ENUM_CONST(0)
+#define VI_VI_DMA_SELECT_0_DMA_REQUEST_STREAM                   _MK_ENUM_CONST(1)
+#define VI_VI_DMA_SELECT_0_DMA_REQUEST_FIRST                    _MK_ENUM_CONST(2)
+#define VI_VI_DMA_SELECT_0_DMA_REQUEST_SECOND                   _MK_ENUM_CONST(3)
+
+
+// Register VI_HOST_DMA_WRITE_BUFFER_0  // Host DMA Write Buffer Configuration Registers
+#define VI_HOST_DMA_WRITE_BUFFER_0                      _MK_ADDR_CONST(0x2d)
+#define VI_HOST_DMA_WRITE_BUFFER_0_WORD_COUNT                   0x1
+#define VI_HOST_DMA_WRITE_BUFFER_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define VI_HOST_DMA_WRITE_BUFFER_0_RESET_MASK                   _MK_MASK_CONST(0xe000000)
+#define VI_HOST_DMA_WRITE_BUFFER_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define VI_HOST_DMA_WRITE_BUFFER_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_HOST_DMA_WRITE_BUFFER_0_READ_MASK                    _MK_MASK_CONST(0xfffffff)
+#define VI_HOST_DMA_WRITE_BUFFER_0_WRITE_MASK                   _MK_MASK_CONST(0xfffffff)
+// Buffer Size
+#define VI_HOST_DMA_WRITE_BUFFER_0_BUFFER_SIZE_SHIFT                    _MK_SHIFT_CONST(0)
+#define VI_HOST_DMA_WRITE_BUFFER_0_BUFFER_SIZE_FIELD                    (_MK_MASK_CONST(0xffff) << VI_HOST_DMA_WRITE_BUFFER_0_BUFFER_SIZE_SHIFT)
+#define VI_HOST_DMA_WRITE_BUFFER_0_BUFFER_SIZE_RANGE                    15:0
+#define VI_HOST_DMA_WRITE_BUFFER_0_BUFFER_SIZE_WOFFSET                  0x0
+#define VI_HOST_DMA_WRITE_BUFFER_0_BUFFER_SIZE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_HOST_DMA_WRITE_BUFFER_0_BUFFER_SIZE_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_HOST_DMA_WRITE_BUFFER_0_BUFFER_SIZE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_HOST_DMA_WRITE_BUFFER_0_BUFFER_SIZE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Buffer Number
+#define VI_HOST_DMA_WRITE_BUFFER_0_BUFFER_NUMBER_SHIFT                  _MK_SHIFT_CONST(16)
+#define VI_HOST_DMA_WRITE_BUFFER_0_BUFFER_NUMBER_FIELD                  (_MK_MASK_CONST(0x1ff) << VI_HOST_DMA_WRITE_BUFFER_0_BUFFER_NUMBER_SHIFT)
+#define VI_HOST_DMA_WRITE_BUFFER_0_BUFFER_NUMBER_RANGE                  24:16
+#define VI_HOST_DMA_WRITE_BUFFER_0_BUFFER_NUMBER_WOFFSET                        0x0
+#define VI_HOST_DMA_WRITE_BUFFER_0_BUFFER_NUMBER_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_HOST_DMA_WRITE_BUFFER_0_BUFFER_NUMBER_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_HOST_DMA_WRITE_BUFFER_0_BUFFER_NUMBER_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_HOST_DMA_WRITE_BUFFER_0_BUFFER_NUMBER_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// DMA Enable
+#define VI_HOST_DMA_WRITE_BUFFER_0_DMA_ENABLE_SHIFT                     _MK_SHIFT_CONST(25)
+#define VI_HOST_DMA_WRITE_BUFFER_0_DMA_ENABLE_FIELD                     (_MK_MASK_CONST(0x1) << VI_HOST_DMA_WRITE_BUFFER_0_DMA_ENABLE_SHIFT)
+#define VI_HOST_DMA_WRITE_BUFFER_0_DMA_ENABLE_RANGE                     25:25
+#define VI_HOST_DMA_WRITE_BUFFER_0_DMA_ENABLE_WOFFSET                   0x0
+#define VI_HOST_DMA_WRITE_BUFFER_0_DMA_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_HOST_DMA_WRITE_BUFFER_0_DMA_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define VI_HOST_DMA_WRITE_BUFFER_0_DMA_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_HOST_DMA_WRITE_BUFFER_0_DMA_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_HOST_DMA_WRITE_BUFFER_0_DMA_ENABLE_DISABLED                  _MK_ENUM_CONST(0)
+#define VI_HOST_DMA_WRITE_BUFFER_0_DMA_ENABLE_ENABLED                   _MK_ENUM_CONST(1)
+
+// Data source selection 00= VIP     (backward compatible)
+// 01= CSI_PPA
+// 10= CSI_PPB
+#define VI_HOST_DMA_WRITE_BUFFER_0_SOURCE_SEL_SHIFT                     _MK_SHIFT_CONST(26)
+#define VI_HOST_DMA_WRITE_BUFFER_0_SOURCE_SEL_FIELD                     (_MK_MASK_CONST(0x3) << VI_HOST_DMA_WRITE_BUFFER_0_SOURCE_SEL_SHIFT)
+#define VI_HOST_DMA_WRITE_BUFFER_0_SOURCE_SEL_RANGE                     27:26
+#define VI_HOST_DMA_WRITE_BUFFER_0_SOURCE_SEL_WOFFSET                   0x0
+#define VI_HOST_DMA_WRITE_BUFFER_0_SOURCE_SEL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_HOST_DMA_WRITE_BUFFER_0_SOURCE_SEL_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define VI_HOST_DMA_WRITE_BUFFER_0_SOURCE_SEL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_HOST_DMA_WRITE_BUFFER_0_SOURCE_SEL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_HOST_DMA_WRITE_BUFFER_0_SOURCE_SEL_VIP                       _MK_ENUM_CONST(0)
+#define VI_HOST_DMA_WRITE_BUFFER_0_SOURCE_SEL_CSI_PPA                   _MK_ENUM_CONST(1)
+#define VI_HOST_DMA_WRITE_BUFFER_0_SOURCE_SEL_CSI_PPB                   _MK_ENUM_CONST(2)
+
+
+// Register VI_HOST_DMA_BASE_ADDRESS_0  // Host DMA Write Buffer Configuration Registers
+#define VI_HOST_DMA_BASE_ADDRESS_0                      _MK_ADDR_CONST(0x2e)
+#define VI_HOST_DMA_BASE_ADDRESS_0_WORD_COUNT                   0x1
+#define VI_HOST_DMA_BASE_ADDRESS_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define VI_HOST_DMA_BASE_ADDRESS_0_RESET_MASK                   _MK_MASK_CONST(0x0)
+#define VI_HOST_DMA_BASE_ADDRESS_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define VI_HOST_DMA_BASE_ADDRESS_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_HOST_DMA_BASE_ADDRESS_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
+#define VI_HOST_DMA_BASE_ADDRESS_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
+// Base Address
+#define VI_HOST_DMA_BASE_ADDRESS_0_DMA_BASE_ADDR_SHIFT                  _MK_SHIFT_CONST(0)
+#define VI_HOST_DMA_BASE_ADDRESS_0_DMA_BASE_ADDR_FIELD                  (_MK_MASK_CONST(0xffffffff) << VI_HOST_DMA_BASE_ADDRESS_0_DMA_BASE_ADDR_SHIFT)
+#define VI_HOST_DMA_BASE_ADDRESS_0_DMA_BASE_ADDR_RANGE                  31:0
+#define VI_HOST_DMA_BASE_ADDRESS_0_DMA_BASE_ADDR_WOFFSET                        0x0
+#define VI_HOST_DMA_BASE_ADDRESS_0_DMA_BASE_ADDR_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_HOST_DMA_BASE_ADDRESS_0_DMA_BASE_ADDR_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_HOST_DMA_BASE_ADDRESS_0_DMA_BASE_ADDR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_HOST_DMA_BASE_ADDRESS_0_DMA_BASE_ADDR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register VI_HOST_DMA_WRITE_BUFFER_STATUS_0  // Host DMA Write Buffer Status Register
+#define VI_HOST_DMA_WRITE_BUFFER_STATUS_0                       _MK_ADDR_CONST(0x2f)
+#define VI_HOST_DMA_WRITE_BUFFER_STATUS_0_WORD_COUNT                    0x1
+#define VI_HOST_DMA_WRITE_BUFFER_STATUS_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define VI_HOST_DMA_WRITE_BUFFER_STATUS_0_RESET_MASK                    _MK_MASK_CONST(0x0)
+#define VI_HOST_DMA_WRITE_BUFFER_STATUS_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define VI_HOST_DMA_WRITE_BUFFER_STATUS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_HOST_DMA_WRITE_BUFFER_STATUS_0_READ_MASK                     _MK_MASK_CONST(0x7ffffff)
+#define VI_HOST_DMA_WRITE_BUFFER_STATUS_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+// Read Only
+#define VI_HOST_DMA_WRITE_BUFFER_STATUS_0_WB_STATUS_SHIFT                       _MK_SHIFT_CONST(0)
+#define VI_HOST_DMA_WRITE_BUFFER_STATUS_0_WB_STATUS_FIELD                       (_MK_MASK_CONST(0x7ffffff) << VI_HOST_DMA_WRITE_BUFFER_STATUS_0_WB_STATUS_SHIFT)
+#define VI_HOST_DMA_WRITE_BUFFER_STATUS_0_WB_STATUS_RANGE                       26:0
+#define VI_HOST_DMA_WRITE_BUFFER_STATUS_0_WB_STATUS_WOFFSET                     0x0
+#define VI_HOST_DMA_WRITE_BUFFER_STATUS_0_WB_STATUS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_HOST_DMA_WRITE_BUFFER_STATUS_0_WB_STATUS_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_HOST_DMA_WRITE_BUFFER_STATUS_0_WB_STATUS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_HOST_DMA_WRITE_BUFFER_STATUS_0_WB_STATUS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register VI_HOST_DMA_WRITE_PEND_BUFCOUNT_0  // Host DMA Write Buffer Pending Buffer Count
+#define VI_HOST_DMA_WRITE_PEND_BUFCOUNT_0                       _MK_ADDR_CONST(0x30)
+#define VI_HOST_DMA_WRITE_PEND_BUFCOUNT_0_WORD_COUNT                    0x1
+#define VI_HOST_DMA_WRITE_PEND_BUFCOUNT_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define VI_HOST_DMA_WRITE_PEND_BUFCOUNT_0_RESET_MASK                    _MK_MASK_CONST(0x0)
+#define VI_HOST_DMA_WRITE_PEND_BUFCOUNT_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define VI_HOST_DMA_WRITE_PEND_BUFCOUNT_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_HOST_DMA_WRITE_PEND_BUFCOUNT_0_READ_MASK                     _MK_MASK_CONST(0x1ff)
+#define VI_HOST_DMA_WRITE_PEND_BUFCOUNT_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+// Read Only
+#define VI_HOST_DMA_WRITE_PEND_BUFCOUNT_0_PEND_BUFCOUNT_SHIFT                   _MK_SHIFT_CONST(0)
+#define VI_HOST_DMA_WRITE_PEND_BUFCOUNT_0_PEND_BUFCOUNT_FIELD                   (_MK_MASK_CONST(0x1ff) << VI_HOST_DMA_WRITE_PEND_BUFCOUNT_0_PEND_BUFCOUNT_SHIFT)
+#define VI_HOST_DMA_WRITE_PEND_BUFCOUNT_0_PEND_BUFCOUNT_RANGE                   8:0
+#define VI_HOST_DMA_WRITE_PEND_BUFCOUNT_0_PEND_BUFCOUNT_WOFFSET                 0x0
+#define VI_HOST_DMA_WRITE_PEND_BUFCOUNT_0_PEND_BUFCOUNT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_HOST_DMA_WRITE_PEND_BUFCOUNT_0_PEND_BUFCOUNT_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_HOST_DMA_WRITE_PEND_BUFCOUNT_0_PEND_BUFCOUNT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_HOST_DMA_WRITE_PEND_BUFCOUNT_0_PEND_BUFCOUNT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register VI_VB0_START_ADDRESS_FIRST_0  // Video Buffer O Start Address for First Output
+#define VI_VB0_START_ADDRESS_FIRST_0                    _MK_ADDR_CONST(0x31)
+#define VI_VB0_START_ADDRESS_FIRST_0_WORD_COUNT                         0x1
+#define VI_VB0_START_ADDRESS_FIRST_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define VI_VB0_START_ADDRESS_FIRST_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define VI_VB0_START_ADDRESS_FIRST_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define VI_VB0_START_ADDRESS_FIRST_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_VB0_START_ADDRESS_FIRST_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define VI_VB0_START_ADDRESS_FIRST_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+//  This is byte address of video buffer 0 if
+//  output data format is RGB or YUV non-planar.
+//  This is byte address of video buffer 0
+//  Y-plane if output data format is YUV planar.
+#define VI_VB0_START_ADDRESS_FIRST_0_VB0_START_ADDRESS_1_SHIFT                  _MK_SHIFT_CONST(0)
+#define VI_VB0_START_ADDRESS_FIRST_0_VB0_START_ADDRESS_1_FIELD                  (_MK_MASK_CONST(0xffffffff) << VI_VB0_START_ADDRESS_FIRST_0_VB0_START_ADDRESS_1_SHIFT)
+#define VI_VB0_START_ADDRESS_FIRST_0_VB0_START_ADDRESS_1_RANGE                  31:0
+#define VI_VB0_START_ADDRESS_FIRST_0_VB0_START_ADDRESS_1_WOFFSET                        0x0
+#define VI_VB0_START_ADDRESS_FIRST_0_VB0_START_ADDRESS_1_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_VB0_START_ADDRESS_FIRST_0_VB0_START_ADDRESS_1_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_VB0_START_ADDRESS_FIRST_0_VB0_START_ADDRESS_1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_VB0_START_ADDRESS_FIRST_0_VB0_START_ADDRESS_1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register VI_VB0_BASE_ADDRESS_FIRST_0  // Video Buffer O BASE Address for First Output
+#define VI_VB0_BASE_ADDRESS_FIRST_0                     _MK_ADDR_CONST(0x32)
+#define VI_VB0_BASE_ADDRESS_FIRST_0_WORD_COUNT                  0x1
+#define VI_VB0_BASE_ADDRESS_FIRST_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define VI_VB0_BASE_ADDRESS_FIRST_0_RESET_MASK                  _MK_MASK_CONST(0x0)
+#define VI_VB0_BASE_ADDRESS_FIRST_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define VI_VB0_BASE_ADDRESS_FIRST_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_VB0_BASE_ADDRESS_FIRST_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define VI_VB0_BASE_ADDRESS_FIRST_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+//  This is the first byte address of video
+//  buffer 0.
+//  This is byte address of video buffer 0
+//  Y-plane if output data format is planar.
+#define VI_VB0_BASE_ADDRESS_FIRST_0_VB0_BASE_ADDRESS_1_SHIFT                    _MK_SHIFT_CONST(0)
+#define VI_VB0_BASE_ADDRESS_FIRST_0_VB0_BASE_ADDRESS_1_FIELD                    (_MK_MASK_CONST(0xffffffff) << VI_VB0_BASE_ADDRESS_FIRST_0_VB0_BASE_ADDRESS_1_SHIFT)
+#define VI_VB0_BASE_ADDRESS_FIRST_0_VB0_BASE_ADDRESS_1_RANGE                    31:0
+#define VI_VB0_BASE_ADDRESS_FIRST_0_VB0_BASE_ADDRESS_1_WOFFSET                  0x0
+#define VI_VB0_BASE_ADDRESS_FIRST_0_VB0_BASE_ADDRESS_1_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_VB0_BASE_ADDRESS_FIRST_0_VB0_BASE_ADDRESS_1_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_VB0_BASE_ADDRESS_FIRST_0_VB0_BASE_ADDRESS_1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_VB0_BASE_ADDRESS_FIRST_0_VB0_BASE_ADDRESS_1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register VI_VB0_START_ADDRESS_U_0  // Video Buffer O Start Address U (linked to First Output)
+#define VI_VB0_START_ADDRESS_U_0                        _MK_ADDR_CONST(0x33)
+#define VI_VB0_START_ADDRESS_U_0_WORD_COUNT                     0x1
+#define VI_VB0_START_ADDRESS_U_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define VI_VB0_START_ADDRESS_U_0_RESET_MASK                     _MK_MASK_CONST(0x0)
+#define VI_VB0_START_ADDRESS_U_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define VI_VB0_START_ADDRESS_U_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_VB0_START_ADDRESS_U_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define VI_VB0_START_ADDRESS_U_0_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
+//  This is byte address of video buffer 0
+//  U-plane if output data format is YUV planar.
+//  output data format is YUV planar.
+#define VI_VB0_START_ADDRESS_U_0_VB0_START_ADDRESS_U_SHIFT                      _MK_SHIFT_CONST(0)
+#define VI_VB0_START_ADDRESS_U_0_VB0_START_ADDRESS_U_FIELD                      (_MK_MASK_CONST(0xffffffff) << VI_VB0_START_ADDRESS_U_0_VB0_START_ADDRESS_U_SHIFT)
+#define VI_VB0_START_ADDRESS_U_0_VB0_START_ADDRESS_U_RANGE                      31:0
+#define VI_VB0_START_ADDRESS_U_0_VB0_START_ADDRESS_U_WOFFSET                    0x0
+#define VI_VB0_START_ADDRESS_U_0_VB0_START_ADDRESS_U_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_VB0_START_ADDRESS_U_0_VB0_START_ADDRESS_U_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_VB0_START_ADDRESS_U_0_VB0_START_ADDRESS_U_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_VB0_START_ADDRESS_U_0_VB0_START_ADDRESS_U_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register VI_VB0_BASE_ADDRESS_U_0  // Video Buffer O BASE Address U
+//(linked to First Output)
+#define VI_VB0_BASE_ADDRESS_U_0                 _MK_ADDR_CONST(0x34)
+#define VI_VB0_BASE_ADDRESS_U_0_WORD_COUNT                      0x1
+#define VI_VB0_BASE_ADDRESS_U_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define VI_VB0_BASE_ADDRESS_U_0_RESET_MASK                      _MK_MASK_CONST(0x0)
+#define VI_VB0_BASE_ADDRESS_U_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define VI_VB0_BASE_ADDRESS_U_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define VI_VB0_BASE_ADDRESS_U_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define VI_VB0_BASE_ADDRESS_U_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+//  This is the first byte address of video
+//  buffer 0 U-plane if output data format
+//  is planar.
+#define VI_VB0_BASE_ADDRESS_U_0_VB0_BASE_ADDRESS_U_SHIFT                        _MK_SHIFT_CONST(0)
+#define VI_VB0_BASE_ADDRESS_U_0_VB0_BASE_ADDRESS_U_FIELD                        (_MK_MASK_CONST(0xffffffff) << VI_VB0_BASE_ADDRESS_U_0_VB0_BASE_ADDRESS_U_SHIFT)
+#define VI_VB0_BASE_ADDRESS_U_0_VB0_BASE_ADDRESS_U_RANGE                        31:0
+#define VI_VB0_BASE_ADDRESS_U_0_VB0_BASE_ADDRESS_U_WOFFSET                      0x0
+#define VI_VB0_BASE_ADDRESS_U_0_VB0_BASE_ADDRESS_U_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_VB0_BASE_ADDRESS_U_0_VB0_BASE_ADDRESS_U_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_VB0_BASE_ADDRESS_U_0_VB0_BASE_ADDRESS_U_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_VB0_BASE_ADDRESS_U_0_VB0_BASE_ADDRESS_U_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register VI_VB0_START_ADDRESS_V_0  // Video Buffer O Start Address V (linked to First Output)
+#define VI_VB0_START_ADDRESS_V_0                        _MK_ADDR_CONST(0x35)
+#define VI_VB0_START_ADDRESS_V_0_WORD_COUNT                     0x1
+#define VI_VB0_START_ADDRESS_V_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define VI_VB0_START_ADDRESS_V_0_RESET_MASK                     _MK_MASK_CONST(0x0)
+#define VI_VB0_START_ADDRESS_V_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define VI_VB0_START_ADDRESS_V_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_VB0_START_ADDRESS_V_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define VI_VB0_START_ADDRESS_V_0_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
+//  This is byte address of video buffer 0
+//  V-plane if output data format is YUV planar.
+//  output data format is YUV planar.
+#define VI_VB0_START_ADDRESS_V_0_VB0_START_ADDRESS_V_SHIFT                      _MK_SHIFT_CONST(0)
+#define VI_VB0_START_ADDRESS_V_0_VB0_START_ADDRESS_V_FIELD                      (_MK_MASK_CONST(0xffffffff) << VI_VB0_START_ADDRESS_V_0_VB0_START_ADDRESS_V_SHIFT)
+#define VI_VB0_START_ADDRESS_V_0_VB0_START_ADDRESS_V_RANGE                      31:0
+#define VI_VB0_START_ADDRESS_V_0_VB0_START_ADDRESS_V_WOFFSET                    0x0
+#define VI_VB0_START_ADDRESS_V_0_VB0_START_ADDRESS_V_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_VB0_START_ADDRESS_V_0_VB0_START_ADDRESS_V_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_VB0_START_ADDRESS_V_0_VB0_START_ADDRESS_V_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_VB0_START_ADDRESS_V_0_VB0_START_ADDRESS_V_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register VI_VB0_BASE_ADDRESS_V_0  // Video Buffer O BASE Address V
+//(linked to First Output)
+#define VI_VB0_BASE_ADDRESS_V_0                 _MK_ADDR_CONST(0x36)
+#define VI_VB0_BASE_ADDRESS_V_0_WORD_COUNT                      0x1
+#define VI_VB0_BASE_ADDRESS_V_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define VI_VB0_BASE_ADDRESS_V_0_RESET_MASK                      _MK_MASK_CONST(0x0)
+#define VI_VB0_BASE_ADDRESS_V_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define VI_VB0_BASE_ADDRESS_V_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define VI_VB0_BASE_ADDRESS_V_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define VI_VB0_BASE_ADDRESS_V_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+//  This is byte address of video buffer 0
+//  V-plane if output data format is YUV planar.
+//  output data format is YUV planar.
+#define VI_VB0_BASE_ADDRESS_V_0_VB0_BASE_ADDRESS_V_SHIFT                        _MK_SHIFT_CONST(0)
+#define VI_VB0_BASE_ADDRESS_V_0_VB0_BASE_ADDRESS_V_FIELD                        (_MK_MASK_CONST(0xffffffff) << VI_VB0_BASE_ADDRESS_V_0_VB0_BASE_ADDRESS_V_SHIFT)
+#define VI_VB0_BASE_ADDRESS_V_0_VB0_BASE_ADDRESS_V_RANGE                        31:0
+#define VI_VB0_BASE_ADDRESS_V_0_VB0_BASE_ADDRESS_V_WOFFSET                      0x0
+#define VI_VB0_BASE_ADDRESS_V_0_VB0_BASE_ADDRESS_V_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_VB0_BASE_ADDRESS_V_0_VB0_BASE_ADDRESS_V_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_VB0_BASE_ADDRESS_V_0_VB0_BASE_ADDRESS_V_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_VB0_BASE_ADDRESS_V_0_VB0_BASE_ADDRESS_V_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register VI_VB0_SCRATCH_ADDRESS_UV_0  // Video Buffer O Scratch Address UV (linked to First Output)
+#define VI_VB0_SCRATCH_ADDRESS_UV_0                     _MK_ADDR_CONST(0x37)
+#define VI_VB0_SCRATCH_ADDRESS_UV_0_WORD_COUNT                  0x1
+#define VI_VB0_SCRATCH_ADDRESS_UV_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define VI_VB0_SCRATCH_ADDRESS_UV_0_RESET_MASK                  _MK_MASK_CONST(0x0)
+#define VI_VB0_SCRATCH_ADDRESS_UV_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define VI_VB0_SCRATCH_ADDRESS_UV_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_VB0_SCRATCH_ADDRESS_UV_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define VI_VB0_SCRATCH_ADDRESS_UV_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+//  If OUTPUT_FORMAT is YUV420PA, this is used.
+//  This is byte address of video buffer 0
+//  UV intermediate data is saved here during the
+//  YUV422 to YUV420PA conversion.
+//  The size allocated needs to match the
+//  FIRST_FRAME_WIDTH register setting
+#define VI_VB0_SCRATCH_ADDRESS_UV_0_VB0_SCRATCH_ADDRESS_UV_SHIFT                        _MK_SHIFT_CONST(0)
+#define VI_VB0_SCRATCH_ADDRESS_UV_0_VB0_SCRATCH_ADDRESS_UV_FIELD                        (_MK_MASK_CONST(0xffffffff) << VI_VB0_SCRATCH_ADDRESS_UV_0_VB0_SCRATCH_ADDRESS_UV_SHIFT)
+#define VI_VB0_SCRATCH_ADDRESS_UV_0_VB0_SCRATCH_ADDRESS_UV_RANGE                        31:0
+#define VI_VB0_SCRATCH_ADDRESS_UV_0_VB0_SCRATCH_ADDRESS_UV_WOFFSET                      0x0
+#define VI_VB0_SCRATCH_ADDRESS_UV_0_VB0_SCRATCH_ADDRESS_UV_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_VB0_SCRATCH_ADDRESS_UV_0_VB0_SCRATCH_ADDRESS_UV_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_VB0_SCRATCH_ADDRESS_UV_0_VB0_SCRATCH_ADDRESS_UV_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_VB0_SCRATCH_ADDRESS_UV_0_VB0_SCRATCH_ADDRESS_UV_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register VI_FIRST_OUTPUT_FRAME_SIZE_0  // Width and height of first output frame
+// This is the size of the frame being written to memory.
+// Apply decimation or averaging to calculate the output frame
+// size.  Whether or not downscaling is used specify whatever the
+// size of the frame being written to memory.
+#define VI_FIRST_OUTPUT_FRAME_SIZE_0                    _MK_ADDR_CONST(0x38)
+#define VI_FIRST_OUTPUT_FRAME_SIZE_0_WORD_COUNT                         0x1
+#define VI_FIRST_OUTPUT_FRAME_SIZE_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define VI_FIRST_OUTPUT_FRAME_SIZE_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define VI_FIRST_OUTPUT_FRAME_SIZE_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define VI_FIRST_OUTPUT_FRAME_SIZE_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_FIRST_OUTPUT_FRAME_SIZE_0_READ_MASK                  _MK_MASK_CONST(0x1fff1fff)
+#define VI_FIRST_OUTPUT_FRAME_SIZE_0_WRITE_MASK                         _MK_MASK_CONST(0x1fff1fff)
+// frame width in pixel which VI needs to process
+#define VI_FIRST_OUTPUT_FRAME_SIZE_0_FIRST_FRAME_WIDTH_SHIFT                    _MK_SHIFT_CONST(0)
+#define VI_FIRST_OUTPUT_FRAME_SIZE_0_FIRST_FRAME_WIDTH_FIELD                    (_MK_MASK_CONST(0x1fff) << VI_FIRST_OUTPUT_FRAME_SIZE_0_FIRST_FRAME_WIDTH_SHIFT)
+#define VI_FIRST_OUTPUT_FRAME_SIZE_0_FIRST_FRAME_WIDTH_RANGE                    12:0
+#define VI_FIRST_OUTPUT_FRAME_SIZE_0_FIRST_FRAME_WIDTH_WOFFSET                  0x0
+#define VI_FIRST_OUTPUT_FRAME_SIZE_0_FIRST_FRAME_WIDTH_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_FIRST_OUTPUT_FRAME_SIZE_0_FIRST_FRAME_WIDTH_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_FIRST_OUTPUT_FRAME_SIZE_0_FIRST_FRAME_WIDTH_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_FIRST_OUTPUT_FRAME_SIZE_0_FIRST_FRAME_WIDTH_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// frame height in lines which VI needs to process
+#define VI_FIRST_OUTPUT_FRAME_SIZE_0_FIRST_FRAME_HEIGHT_SHIFT                   _MK_SHIFT_CONST(16)
+#define VI_FIRST_OUTPUT_FRAME_SIZE_0_FIRST_FRAME_HEIGHT_FIELD                   (_MK_MASK_CONST(0x1fff) << VI_FIRST_OUTPUT_FRAME_SIZE_0_FIRST_FRAME_HEIGHT_SHIFT)
+#define VI_FIRST_OUTPUT_FRAME_SIZE_0_FIRST_FRAME_HEIGHT_RANGE                   28:16
+#define VI_FIRST_OUTPUT_FRAME_SIZE_0_FIRST_FRAME_HEIGHT_WOFFSET                 0x0
+#define VI_FIRST_OUTPUT_FRAME_SIZE_0_FIRST_FRAME_HEIGHT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_FIRST_OUTPUT_FRAME_SIZE_0_FIRST_FRAME_HEIGHT_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_FIRST_OUTPUT_FRAME_SIZE_0_FIRST_FRAME_HEIGHT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_FIRST_OUTPUT_FRAME_SIZE_0_FIRST_FRAME_HEIGHT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register VI_VB0_COUNT_FIRST_0  // Video Buffer Set 0 Count for First Output
+#define VI_VB0_COUNT_FIRST_0                    _MK_ADDR_CONST(0x39)
+#define VI_VB0_COUNT_FIRST_0_WORD_COUNT                         0x1
+#define VI_VB0_COUNT_FIRST_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define VI_VB0_COUNT_FIRST_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define VI_VB0_COUNT_FIRST_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define VI_VB0_COUNT_FIRST_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_VB0_COUNT_FIRST_0_READ_MASK                  _MK_MASK_CONST(0xff)
+#define VI_VB0_COUNT_FIRST_0_WRITE_MASK                         _MK_MASK_CONST(0xff)
+// Video Buffer Set 0 Count
+//  This specifies the number of buffers in
+//  video buffer set 0.
+#define VI_VB0_COUNT_FIRST_0_VB0_COUNT_1_SHIFT                  _MK_SHIFT_CONST(0)
+#define VI_VB0_COUNT_FIRST_0_VB0_COUNT_1_FIELD                  (_MK_MASK_CONST(0xff) << VI_VB0_COUNT_FIRST_0_VB0_COUNT_1_SHIFT)
+#define VI_VB0_COUNT_FIRST_0_VB0_COUNT_1_RANGE                  7:0
+#define VI_VB0_COUNT_FIRST_0_VB0_COUNT_1_WOFFSET                        0x0
+#define VI_VB0_COUNT_FIRST_0_VB0_COUNT_1_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_VB0_COUNT_FIRST_0_VB0_COUNT_1_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_VB0_COUNT_FIRST_0_VB0_COUNT_1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_VB0_COUNT_FIRST_0_VB0_COUNT_1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register VI_VB0_SIZE_FIRST_0  // Video Buffer Set 0 Size for First Output
+#define VI_VB0_SIZE_FIRST_0                     _MK_ADDR_CONST(0x3a)
+#define VI_VB0_SIZE_FIRST_0_WORD_COUNT                  0x1
+#define VI_VB0_SIZE_FIRST_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define VI_VB0_SIZE_FIRST_0_RESET_MASK                  _MK_MASK_CONST(0x0)
+#define VI_VB0_SIZE_FIRST_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define VI_VB0_SIZE_FIRST_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_VB0_SIZE_FIRST_0_READ_MASK                   _MK_MASK_CONST(0x1fff1fff)
+#define VI_VB0_SIZE_FIRST_0_WRITE_MASK                  _MK_MASK_CONST(0x1fff1fff)
+// Video Buffer Set 0 Horizontal Size
+//  This parameter specifies the line stride
+//  (in pixels) for lines in the video buffer
+//  set 0.
+//  For YUV non-planar format, this parameter
+//  must be programmed as multiple of 2 pixels
+//  (bit 0 is ignored).
+//  For YUV planar format, this parameter
+//  must be programmed as multiple of 8 pixels
+//  (bits 2-0 are ignored) and it specifies the
+//  luma line stride or twice the chroma line
+//  stride.
+//  This value will be divided by 2 for chroma
+//  buffers for YUV422 and YUV420 planar formats
+#define VI_VB0_SIZE_FIRST_0_VB0_H_SIZE_1_SHIFT                  _MK_SHIFT_CONST(0)
+#define VI_VB0_SIZE_FIRST_0_VB0_H_SIZE_1_FIELD                  (_MK_MASK_CONST(0x1fff) << VI_VB0_SIZE_FIRST_0_VB0_H_SIZE_1_SHIFT)
+#define VI_VB0_SIZE_FIRST_0_VB0_H_SIZE_1_RANGE                  12:0
+#define VI_VB0_SIZE_FIRST_0_VB0_H_SIZE_1_WOFFSET                        0x0
+#define VI_VB0_SIZE_FIRST_0_VB0_H_SIZE_1_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_VB0_SIZE_FIRST_0_VB0_H_SIZE_1_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_VB0_SIZE_FIRST_0_VB0_H_SIZE_1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_VB0_SIZE_FIRST_0_VB0_H_SIZE_1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Video Buffer Set 0 Vertical Size
+//  This specifies the number of lines in each
+//  buffer in video buffer set 0.
+//  This value will be divided by 2 for chroma
+//  buffers for YUV420 planar formats
+#define VI_VB0_SIZE_FIRST_0_VB0_V_SIZE_1_SHIFT                  _MK_SHIFT_CONST(16)
+#define VI_VB0_SIZE_FIRST_0_VB0_V_SIZE_1_FIELD                  (_MK_MASK_CONST(0x1fff) << VI_VB0_SIZE_FIRST_0_VB0_V_SIZE_1_SHIFT)
+#define VI_VB0_SIZE_FIRST_0_VB0_V_SIZE_1_RANGE                  28:16
+#define VI_VB0_SIZE_FIRST_0_VB0_V_SIZE_1_WOFFSET                        0x0
+#define VI_VB0_SIZE_FIRST_0_VB0_V_SIZE_1_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_VB0_SIZE_FIRST_0_VB0_V_SIZE_1_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_VB0_SIZE_FIRST_0_VB0_V_SIZE_1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_VB0_SIZE_FIRST_0_VB0_V_SIZE_1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register VI_VB0_BUFFER_STRIDE_FIRST_0  // Video Buffer Set 0 Buffer Stride
+#define VI_VB0_BUFFER_STRIDE_FIRST_0                    _MK_ADDR_CONST(0x3b)
+#define VI_VB0_BUFFER_STRIDE_FIRST_0_WORD_COUNT                         0x1
+#define VI_VB0_BUFFER_STRIDE_FIRST_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define VI_VB0_BUFFER_STRIDE_FIRST_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define VI_VB0_BUFFER_STRIDE_FIRST_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define VI_VB0_BUFFER_STRIDE_FIRST_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_VB0_BUFFER_STRIDE_FIRST_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define VI_VB0_BUFFER_STRIDE_FIRST_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+// Video Buffer Set 0 Luma Buffer Stride
+//  This is luma buffer stride (in bytes)
+#define VI_VB0_BUFFER_STRIDE_FIRST_0_VB0_BUFFER_STRIDE_L_SHIFT                  _MK_SHIFT_CONST(0)
+#define VI_VB0_BUFFER_STRIDE_FIRST_0_VB0_BUFFER_STRIDE_L_FIELD                  (_MK_MASK_CONST(0x3fffffff) << VI_VB0_BUFFER_STRIDE_FIRST_0_VB0_BUFFER_STRIDE_L_SHIFT)
+#define VI_VB0_BUFFER_STRIDE_FIRST_0_VB0_BUFFER_STRIDE_L_RANGE                  29:0
+#define VI_VB0_BUFFER_STRIDE_FIRST_0_VB0_BUFFER_STRIDE_L_WOFFSET                        0x0
+#define VI_VB0_BUFFER_STRIDE_FIRST_0_VB0_BUFFER_STRIDE_L_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_VB0_BUFFER_STRIDE_FIRST_0_VB0_BUFFER_STRIDE_L_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_VB0_BUFFER_STRIDE_FIRST_0_VB0_BUFFER_STRIDE_L_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_VB0_BUFFER_STRIDE_FIRST_0_VB0_BUFFER_STRIDE_L_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Video Buffer Set 0 Chroma Buffer Stride   00= Equal to Luma Buffer Stride
+//   01= Equal to Luma Buffer Stride divided by 2
+//       in this case Luma Buffer Stride should
+//       be multiple of 2 bytes.
+//   10= Equal to Luma Buffer Stride divided by 4
+//       in this case Luma Buffer Stride should
+//       be multiple of 4 bytes.
+//   1x= Reserved
+#define VI_VB0_BUFFER_STRIDE_FIRST_0_VB0_BUFFER_STRIDE_C_SHIFT                  _MK_SHIFT_CONST(30)
+#define VI_VB0_BUFFER_STRIDE_FIRST_0_VB0_BUFFER_STRIDE_C_FIELD                  (_MK_MASK_CONST(0x3) << VI_VB0_BUFFER_STRIDE_FIRST_0_VB0_BUFFER_STRIDE_C_SHIFT)
+#define VI_VB0_BUFFER_STRIDE_FIRST_0_VB0_BUFFER_STRIDE_C_RANGE                  31:30
+#define VI_VB0_BUFFER_STRIDE_FIRST_0_VB0_BUFFER_STRIDE_C_WOFFSET                        0x0
+#define VI_VB0_BUFFER_STRIDE_FIRST_0_VB0_BUFFER_STRIDE_C_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_VB0_BUFFER_STRIDE_FIRST_0_VB0_BUFFER_STRIDE_C_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_VB0_BUFFER_STRIDE_FIRST_0_VB0_BUFFER_STRIDE_C_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_VB0_BUFFER_STRIDE_FIRST_0_VB0_BUFFER_STRIDE_C_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_VB0_BUFFER_STRIDE_FIRST_0_VB0_BUFFER_STRIDE_C_CBS1X                  _MK_ENUM_CONST(0)
+#define VI_VB0_BUFFER_STRIDE_FIRST_0_VB0_BUFFER_STRIDE_C_CBS2X                  _MK_ENUM_CONST(1)
+#define VI_VB0_BUFFER_STRIDE_FIRST_0_VB0_BUFFER_STRIDE_C_CBS4X                  _MK_ENUM_CONST(2)
+
+
+// Register VI_VB0_START_ADDRESS_SECOND_0  // Video Buffer O Start Address for Second Output
+#define VI_VB0_START_ADDRESS_SECOND_0                   _MK_ADDR_CONST(0x3c)
+#define VI_VB0_START_ADDRESS_SECOND_0_WORD_COUNT                        0x1
+#define VI_VB0_START_ADDRESS_SECOND_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define VI_VB0_START_ADDRESS_SECOND_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define VI_VB0_START_ADDRESS_SECOND_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define VI_VB0_START_ADDRESS_SECOND_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_VB0_START_ADDRESS_SECOND_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define VI_VB0_START_ADDRESS_SECOND_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
+//  This is byte address of video buffer 0 if
+//  output data format is RGB or YUV non-planar.
+//  This is byte address of video buffer 0
+//  This output data is read by the SB
+#define VI_VB0_START_ADDRESS_SECOND_0_VB0_START_ADDRESS_2_SHIFT                 _MK_SHIFT_CONST(0)
+#define VI_VB0_START_ADDRESS_SECOND_0_VB0_START_ADDRESS_2_FIELD                 (_MK_MASK_CONST(0xffffffff) << VI_VB0_START_ADDRESS_SECOND_0_VB0_START_ADDRESS_2_SHIFT)
+#define VI_VB0_START_ADDRESS_SECOND_0_VB0_START_ADDRESS_2_RANGE                 31:0
+#define VI_VB0_START_ADDRESS_SECOND_0_VB0_START_ADDRESS_2_WOFFSET                       0x0
+#define VI_VB0_START_ADDRESS_SECOND_0_VB0_START_ADDRESS_2_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_VB0_START_ADDRESS_SECOND_0_VB0_START_ADDRESS_2_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_VB0_START_ADDRESS_SECOND_0_VB0_START_ADDRESS_2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_VB0_START_ADDRESS_SECOND_0_VB0_START_ADDRESS_2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register VI_VB0_BASE_ADDRESS_SECOND_0  // Video Buffer O Base Address for Second Output
+#define VI_VB0_BASE_ADDRESS_SECOND_0                    _MK_ADDR_CONST(0x3d)
+#define VI_VB0_BASE_ADDRESS_SECOND_0_WORD_COUNT                         0x1
+#define VI_VB0_BASE_ADDRESS_SECOND_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define VI_VB0_BASE_ADDRESS_SECOND_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define VI_VB0_BASE_ADDRESS_SECOND_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define VI_VB0_BASE_ADDRESS_SECOND_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_VB0_BASE_ADDRESS_SECOND_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define VI_VB0_BASE_ADDRESS_SECOND_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+//  This is byte address of video buffer 0 if
+//  output data format is RGB or non-planar.
+//  This is the first byte address of video
+//  buffer
+#define VI_VB0_BASE_ADDRESS_SECOND_0_VB0_BASE_ADDRESS_2_SHIFT                   _MK_SHIFT_CONST(0)
+#define VI_VB0_BASE_ADDRESS_SECOND_0_VB0_BASE_ADDRESS_2_FIELD                   (_MK_MASK_CONST(0xffffffff) << VI_VB0_BASE_ADDRESS_SECOND_0_VB0_BASE_ADDRESS_2_SHIFT)
+#define VI_VB0_BASE_ADDRESS_SECOND_0_VB0_BASE_ADDRESS_2_RANGE                   31:0
+#define VI_VB0_BASE_ADDRESS_SECOND_0_VB0_BASE_ADDRESS_2_WOFFSET                 0x0
+#define VI_VB0_BASE_ADDRESS_SECOND_0_VB0_BASE_ADDRESS_2_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_VB0_BASE_ADDRESS_SECOND_0_VB0_BASE_ADDRESS_2_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_VB0_BASE_ADDRESS_SECOND_0_VB0_BASE_ADDRESS_2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_VB0_BASE_ADDRESS_SECOND_0_VB0_BASE_ADDRESS_2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register VI_SECOND_OUTPUT_FRAME_SIZE_0  // width and height of second output frame
+#define VI_SECOND_OUTPUT_FRAME_SIZE_0                   _MK_ADDR_CONST(0x3e)
+#define VI_SECOND_OUTPUT_FRAME_SIZE_0_WORD_COUNT                        0x1
+#define VI_SECOND_OUTPUT_FRAME_SIZE_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define VI_SECOND_OUTPUT_FRAME_SIZE_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define VI_SECOND_OUTPUT_FRAME_SIZE_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define VI_SECOND_OUTPUT_FRAME_SIZE_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_SECOND_OUTPUT_FRAME_SIZE_0_READ_MASK                         _MK_MASK_CONST(0x1fff1fff)
+#define VI_SECOND_OUTPUT_FRAME_SIZE_0_WRITE_MASK                        _MK_MASK_CONST(0x1fff1fff)
+// frame width in pixel which VI needs to process
+#define VI_SECOND_OUTPUT_FRAME_SIZE_0_SECOND_FRAME_WIDTH_SHIFT                  _MK_SHIFT_CONST(0)
+#define VI_SECOND_OUTPUT_FRAME_SIZE_0_SECOND_FRAME_WIDTH_FIELD                  (_MK_MASK_CONST(0x1fff) << VI_SECOND_OUTPUT_FRAME_SIZE_0_SECOND_FRAME_WIDTH_SHIFT)
+#define VI_SECOND_OUTPUT_FRAME_SIZE_0_SECOND_FRAME_WIDTH_RANGE                  12:0
+#define VI_SECOND_OUTPUT_FRAME_SIZE_0_SECOND_FRAME_WIDTH_WOFFSET                        0x0
+#define VI_SECOND_OUTPUT_FRAME_SIZE_0_SECOND_FRAME_WIDTH_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_SECOND_OUTPUT_FRAME_SIZE_0_SECOND_FRAME_WIDTH_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_SECOND_OUTPUT_FRAME_SIZE_0_SECOND_FRAME_WIDTH_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_SECOND_OUTPUT_FRAME_SIZE_0_SECOND_FRAME_WIDTH_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// frame height in lines which VI needs to process
+#define VI_SECOND_OUTPUT_FRAME_SIZE_0_SECOND_FRAME_HEIGHT_SHIFT                 _MK_SHIFT_CONST(16)
+#define VI_SECOND_OUTPUT_FRAME_SIZE_0_SECOND_FRAME_HEIGHT_FIELD                 (_MK_MASK_CONST(0x1fff) << VI_SECOND_OUTPUT_FRAME_SIZE_0_SECOND_FRAME_HEIGHT_SHIFT)
+#define VI_SECOND_OUTPUT_FRAME_SIZE_0_SECOND_FRAME_HEIGHT_RANGE                 28:16
+#define VI_SECOND_OUTPUT_FRAME_SIZE_0_SECOND_FRAME_HEIGHT_WOFFSET                       0x0
+#define VI_SECOND_OUTPUT_FRAME_SIZE_0_SECOND_FRAME_HEIGHT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_SECOND_OUTPUT_FRAME_SIZE_0_SECOND_FRAME_HEIGHT_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_SECOND_OUTPUT_FRAME_SIZE_0_SECOND_FRAME_HEIGHT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_SECOND_OUTPUT_FRAME_SIZE_0_SECOND_FRAME_HEIGHT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register VI_VB0_COUNT_SECOND_0  // Video Buffer Set 0 Count for Second Output
+#define VI_VB0_COUNT_SECOND_0                   _MK_ADDR_CONST(0x3f)
+#define VI_VB0_COUNT_SECOND_0_WORD_COUNT                        0x1
+#define VI_VB0_COUNT_SECOND_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define VI_VB0_COUNT_SECOND_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define VI_VB0_COUNT_SECOND_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define VI_VB0_COUNT_SECOND_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_VB0_COUNT_SECOND_0_READ_MASK                         _MK_MASK_CONST(0xff)
+#define VI_VB0_COUNT_SECOND_0_WRITE_MASK                        _MK_MASK_CONST(0xff)
+//
+//  This specifies the number of buffers in
+//  video buffer set 0.
+#define VI_VB0_COUNT_SECOND_0_VB0_COUNT_2_SHIFT                 _MK_SHIFT_CONST(0)
+#define VI_VB0_COUNT_SECOND_0_VB0_COUNT_2_FIELD                 (_MK_MASK_CONST(0xff) << VI_VB0_COUNT_SECOND_0_VB0_COUNT_2_SHIFT)
+#define VI_VB0_COUNT_SECOND_0_VB0_COUNT_2_RANGE                 7:0
+#define VI_VB0_COUNT_SECOND_0_VB0_COUNT_2_WOFFSET                       0x0
+#define VI_VB0_COUNT_SECOND_0_VB0_COUNT_2_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_VB0_COUNT_SECOND_0_VB0_COUNT_2_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_VB0_COUNT_SECOND_0_VB0_COUNT_2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_VB0_COUNT_SECOND_0_VB0_COUNT_2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register VI_VB0_SIZE_SECOND_0  // Video Buffer Set 0 Size for Second Output
+#define VI_VB0_SIZE_SECOND_0                    _MK_ADDR_CONST(0x40)
+#define VI_VB0_SIZE_SECOND_0_WORD_COUNT                         0x1
+#define VI_VB0_SIZE_SECOND_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define VI_VB0_SIZE_SECOND_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define VI_VB0_SIZE_SECOND_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define VI_VB0_SIZE_SECOND_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_VB0_SIZE_SECOND_0_READ_MASK                  _MK_MASK_CONST(0x1fff1fff)
+#define VI_VB0_SIZE_SECOND_0_WRITE_MASK                         _MK_MASK_CONST(0x1fff1fff)
+// Video Buffer Set 0 Horizontal Size
+//  This parameter specifies the line stride
+//  (in pixels) for lines in the video buffer
+//  set 0.
+//  For YUV non-planar format, this parameter
+//  must be programmed as multiple of 2 pixels
+//  (bit 0 is ignored).
+#define VI_VB0_SIZE_SECOND_0_VB0_H_SIZE_2_SHIFT                 _MK_SHIFT_CONST(0)
+#define VI_VB0_SIZE_SECOND_0_VB0_H_SIZE_2_FIELD                 (_MK_MASK_CONST(0x1fff) << VI_VB0_SIZE_SECOND_0_VB0_H_SIZE_2_SHIFT)
+#define VI_VB0_SIZE_SECOND_0_VB0_H_SIZE_2_RANGE                 12:0
+#define VI_VB0_SIZE_SECOND_0_VB0_H_SIZE_2_WOFFSET                       0x0
+#define VI_VB0_SIZE_SECOND_0_VB0_H_SIZE_2_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_VB0_SIZE_SECOND_0_VB0_H_SIZE_2_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_VB0_SIZE_SECOND_0_VB0_H_SIZE_2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_VB0_SIZE_SECOND_0_VB0_H_SIZE_2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Video Buffer Set 0 Vertical Size
+//  This specifies the number of lines in each
+//  buffer in video buffer set 0.
+#define VI_VB0_SIZE_SECOND_0_VB0_V_SIZE_2_SHIFT                 _MK_SHIFT_CONST(16)
+#define VI_VB0_SIZE_SECOND_0_VB0_V_SIZE_2_FIELD                 (_MK_MASK_CONST(0x1fff) << VI_VB0_SIZE_SECOND_0_VB0_V_SIZE_2_SHIFT)
+#define VI_VB0_SIZE_SECOND_0_VB0_V_SIZE_2_RANGE                 28:16
+#define VI_VB0_SIZE_SECOND_0_VB0_V_SIZE_2_WOFFSET                       0x0
+#define VI_VB0_SIZE_SECOND_0_VB0_V_SIZE_2_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_VB0_SIZE_SECOND_0_VB0_V_SIZE_2_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_VB0_SIZE_SECOND_0_VB0_V_SIZE_2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_VB0_SIZE_SECOND_0_VB0_V_SIZE_2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register VI_VB0_BUFFER_STRIDE_SECOND_0  // Video Buffer Set 0 Buffer Stride for Second Output
+#define VI_VB0_BUFFER_STRIDE_SECOND_0                   _MK_ADDR_CONST(0x41)
+#define VI_VB0_BUFFER_STRIDE_SECOND_0_WORD_COUNT                        0x1
+#define VI_VB0_BUFFER_STRIDE_SECOND_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define VI_VB0_BUFFER_STRIDE_SECOND_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define VI_VB0_BUFFER_STRIDE_SECOND_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define VI_VB0_BUFFER_STRIDE_SECOND_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_VB0_BUFFER_STRIDE_SECOND_0_READ_MASK                         _MK_MASK_CONST(0x3fffffff)
+#define VI_VB0_BUFFER_STRIDE_SECOND_0_WRITE_MASK                        _MK_MASK_CONST(0x3fffffff)
+// Video Buffer Set 0 Luma Buffer Stride
+//  This is luma buffer stride (in bytes)
+#define VI_VB0_BUFFER_STRIDE_SECOND_0_VB0_BUFFER_STRIDE_2_SHIFT                 _MK_SHIFT_CONST(0)
+#define VI_VB0_BUFFER_STRIDE_SECOND_0_VB0_BUFFER_STRIDE_2_FIELD                 (_MK_MASK_CONST(0x3fffffff) << VI_VB0_BUFFER_STRIDE_SECOND_0_VB0_BUFFER_STRIDE_2_SHIFT)
+#define VI_VB0_BUFFER_STRIDE_SECOND_0_VB0_BUFFER_STRIDE_2_RANGE                 29:0
+#define VI_VB0_BUFFER_STRIDE_SECOND_0_VB0_BUFFER_STRIDE_2_WOFFSET                       0x0
+#define VI_VB0_BUFFER_STRIDE_SECOND_0_VB0_BUFFER_STRIDE_2_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_VB0_BUFFER_STRIDE_SECOND_0_VB0_BUFFER_STRIDE_2_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_VB0_BUFFER_STRIDE_SECOND_0_VB0_BUFFER_STRIDE_2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_VB0_BUFFER_STRIDE_SECOND_0_VB0_BUFFER_STRIDE_2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define VI_H_LPF_NO_FILTER      576
+#define VI_H_LPF_ONE_MINUS_HPF_CUBED_C  3518
+#define VI_H_LPF_ONE_MINUS_HPF_CUBED_L  2350
+#define VI_H_LPF_ONE_MINUS_HPF_SQUARED_C        438
+#define VI_H_LPF_ONE_MINUS_HPF_SQUARED_L        294
+#define VI_H_LPF_ONE_MINUS_HPF_SQUARED_PLUS_LPF_C       1463
+#define VI_H_LPF_ONE_MINUS_HPF_SQUARED_PLUS_LPF_L       295
+#define VI_H_LPF_LPF_C  1608
+#define VI_H_LPF_LPF_L  584
+#define VI_H_LPF_LPF_PLUS_LPF_SQUARED_C 1169
+#define VI_H_LPF_LPF_PLUS_LPF_SQUARED_L 1
+#define VI_H_LPF_LPF_SQUARED_C  144
+#define VI_H_LPF_LPF_SQUARED_L  0
+#define VI_H_LPF_LPF_CUBED_C    1176
+#define VI_H_LPF_LPF_CUBED_L    8
+#define VI_H_LPF_LPF_SQUARED_SCALED_C   1944
+#define VI_H_LPF_LPF_SQUARED_SCALED_L   776
+#define VI_H_LPF_LPF_SQUARED_SCALED2_C  2040
+#define VI_H_LPF_LPF_SQUARED_SCALED2_L  872
+
+// Register VI_H_LPF_CONTROL_0  // VI Horizontal Low-Pass Filter (LPF) Control
+#define VI_H_LPF_CONTROL_0                      _MK_ADDR_CONST(0x42)
+#define VI_H_LPF_CONTROL_0_WORD_COUNT                   0x1
+#define VI_H_LPF_CONTROL_0_RESET_VAL                    _MK_MASK_CONST(0x2400240)
+#define VI_H_LPF_CONTROL_0_RESET_MASK                   _MK_MASK_CONST(0x1fff1fff)
+#define VI_H_LPF_CONTROL_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define VI_H_LPF_CONTROL_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_H_LPF_CONTROL_0_READ_MASK                    _MK_MASK_CONST(0x1fff1fff)
+#define VI_H_LPF_CONTROL_0_WRITE_MASK                   _MK_MASK_CONST(0x1fff1fff)
+// Horizontal LPF Luminance filter
+//  This controls low pass filter for Y data.
+#define VI_H_LPF_CONTROL_0_H_LPF_L_SHIFT                        _MK_SHIFT_CONST(0)
+#define VI_H_LPF_CONTROL_0_H_LPF_L_FIELD                        (_MK_MASK_CONST(0x1fff) << VI_H_LPF_CONTROL_0_H_LPF_L_SHIFT)
+#define VI_H_LPF_CONTROL_0_H_LPF_L_RANGE                        12:0
+#define VI_H_LPF_CONTROL_0_H_LPF_L_WOFFSET                      0x0
+#define VI_H_LPF_CONTROL_0_H_LPF_L_DEFAULT                      _MK_MASK_CONST(0x240)
+#define VI_H_LPF_CONTROL_0_H_LPF_L_DEFAULT_MASK                 _MK_MASK_CONST(0x1fff)
+#define VI_H_LPF_CONTROL_0_H_LPF_L_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_H_LPF_CONTROL_0_H_LPF_L_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Horizontal LPF Chrominance filter
+//  This controls low pass filter for U V data.
+#define VI_H_LPF_CONTROL_0_H_LPF_C_SHIFT                        _MK_SHIFT_CONST(16)
+#define VI_H_LPF_CONTROL_0_H_LPF_C_FIELD                        (_MK_MASK_CONST(0x1fff) << VI_H_LPF_CONTROL_0_H_LPF_C_SHIFT)
+#define VI_H_LPF_CONTROL_0_H_LPF_C_RANGE                        28:16
+#define VI_H_LPF_CONTROL_0_H_LPF_C_WOFFSET                      0x0
+#define VI_H_LPF_CONTROL_0_H_LPF_C_DEFAULT                      _MK_MASK_CONST(0x240)
+#define VI_H_LPF_CONTROL_0_H_LPF_C_DEFAULT_MASK                 _MK_MASK_CONST(0x1fff)
+#define VI_H_LPF_CONTROL_0_H_LPF_C_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_H_LPF_CONTROL_0_H_LPF_C_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register VI_H_DOWNSCALE_CONTROL_0  // VI Horizontal Down-scaling Control
+#define VI_H_DOWNSCALE_CONTROL_0                        _MK_ADDR_CONST(0x43)
+#define VI_H_DOWNSCALE_CONTROL_0_WORD_COUNT                     0x1
+#define VI_H_DOWNSCALE_CONTROL_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define VI_H_DOWNSCALE_CONTROL_0_RESET_MASK                     _MK_MASK_CONST(0x1fff000c)
+#define VI_H_DOWNSCALE_CONTROL_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define VI_H_DOWNSCALE_CONTROL_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_H_DOWNSCALE_CONTROL_0_READ_MASK                      _MK_MASK_CONST(0x1fff070f)
+#define VI_H_DOWNSCALE_CONTROL_0_WRITE_MASK                     _MK_MASK_CONST(0x1fff070f)
+// Input Horizontal Size Select  Selects between the VIP and HOST input active
+//  area widths for the denominator in the
+//  downscaling ratio.  Uses VIP_H_ACTIVE_PERIOD or
+//  HOST_H_ACTIVE_PERIOD, which is the width of the
+//  data after cropping.  This is effective only when
+//  H_AVERAGING is DISABLED and H_DOWNSCALING is
+//  ENABLED.
+#define VI_H_DOWNSCALE_CONTROL_0_INPUT_H_SIZE_SEL_SHIFT                 _MK_SHIFT_CONST(0)
+#define VI_H_DOWNSCALE_CONTROL_0_INPUT_H_SIZE_SEL_FIELD                 (_MK_MASK_CONST(0x1) << VI_H_DOWNSCALE_CONTROL_0_INPUT_H_SIZE_SEL_SHIFT)
+#define VI_H_DOWNSCALE_CONTROL_0_INPUT_H_SIZE_SEL_RANGE                 0:0
+#define VI_H_DOWNSCALE_CONTROL_0_INPUT_H_SIZE_SEL_WOFFSET                       0x0
+#define VI_H_DOWNSCALE_CONTROL_0_INPUT_H_SIZE_SEL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_H_DOWNSCALE_CONTROL_0_INPUT_H_SIZE_SEL_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_H_DOWNSCALE_CONTROL_0_INPUT_H_SIZE_SEL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_H_DOWNSCALE_CONTROL_0_INPUT_H_SIZE_SEL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_H_DOWNSCALE_CONTROL_0_INPUT_H_SIZE_SEL_VIP                   _MK_ENUM_CONST(0)
+#define VI_H_DOWNSCALE_CONTROL_0_INPUT_H_SIZE_SEL_HOST                  _MK_ENUM_CONST(1)
+
+// Output Horizontal Size Select  Selects between the first and second memory output
+//  frame widths for the numerator in the downscaling
+//  ratio.  Uses FIRST_FRAME_WIDTH or
+//  SECOND_FRAME_WIDTH.
+//  This is effective
+//  only when H_AVERAGING is DISABLED and
+//  H_DOWNSCALING is ENABLED.
+#define VI_H_DOWNSCALE_CONTROL_0_OUTPUT_H_SIZE_SEL_SHIFT                        _MK_SHIFT_CONST(1)
+#define VI_H_DOWNSCALE_CONTROL_0_OUTPUT_H_SIZE_SEL_FIELD                        (_MK_MASK_CONST(0x1) << VI_H_DOWNSCALE_CONTROL_0_OUTPUT_H_SIZE_SEL_SHIFT)
+#define VI_H_DOWNSCALE_CONTROL_0_OUTPUT_H_SIZE_SEL_RANGE                        1:1
+#define VI_H_DOWNSCALE_CONTROL_0_OUTPUT_H_SIZE_SEL_WOFFSET                      0x0
+#define VI_H_DOWNSCALE_CONTROL_0_OUTPUT_H_SIZE_SEL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_H_DOWNSCALE_CONTROL_0_OUTPUT_H_SIZE_SEL_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_H_DOWNSCALE_CONTROL_0_OUTPUT_H_SIZE_SEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_H_DOWNSCALE_CONTROL_0_OUTPUT_H_SIZE_SEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_H_DOWNSCALE_CONTROL_0_OUTPUT_H_SIZE_SEL_FIRST                        _MK_ENUM_CONST(0)
+#define VI_H_DOWNSCALE_CONTROL_0_OUTPUT_H_SIZE_SEL_SECOND                       _MK_ENUM_CONST(1)
+
+//  Selects input horizontal size into scalers (extension field)
+//  00= Hor. size selected with INPUT_H_SIZE_SEL field (backward compatible)
+//  01= Hor. size of CSI_PPA is provided by CSI_PPA_H_ACTIVE register
+//  10= Hor. size of CSI_PPB is provided by CSI_PPB_H_ACTIVE register
+//  11= Hor. size of ISP     is provided by ISP_H_ACTIVE     register
+// 7:4 reserved
+#define VI_H_DOWNSCALE_CONTROL_0_INPUT_H_SIZE_SEL_EXT_SHIFT                     _MK_SHIFT_CONST(2)
+#define VI_H_DOWNSCALE_CONTROL_0_INPUT_H_SIZE_SEL_EXT_FIELD                     (_MK_MASK_CONST(0x3) << VI_H_DOWNSCALE_CONTROL_0_INPUT_H_SIZE_SEL_EXT_SHIFT)
+#define VI_H_DOWNSCALE_CONTROL_0_INPUT_H_SIZE_SEL_EXT_RANGE                     3:2
+#define VI_H_DOWNSCALE_CONTROL_0_INPUT_H_SIZE_SEL_EXT_WOFFSET                   0x0
+#define VI_H_DOWNSCALE_CONTROL_0_INPUT_H_SIZE_SEL_EXT_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_H_DOWNSCALE_CONTROL_0_INPUT_H_SIZE_SEL_EXT_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define VI_H_DOWNSCALE_CONTROL_0_INPUT_H_SIZE_SEL_EXT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_H_DOWNSCALE_CONTROL_0_INPUT_H_SIZE_SEL_EXT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_H_DOWNSCALE_CONTROL_0_INPUT_H_SIZE_SEL_EXT_USE_INPUT_H_SIZE_SEL                      _MK_ENUM_CONST(0)
+#define VI_H_DOWNSCALE_CONTROL_0_INPUT_H_SIZE_SEL_EXT_CSI_PPA                   _MK_ENUM_CONST(1)
+#define VI_H_DOWNSCALE_CONTROL_0_INPUT_H_SIZE_SEL_EXT_CSI_PPB                   _MK_ENUM_CONST(2)
+#define VI_H_DOWNSCALE_CONTROL_0_INPUT_H_SIZE_SEL_EXT_ISP                       _MK_ENUM_CONST(3)
+
+// Horizontal Averaging Control  This specifies the number of pixels to
+//  average and to decimate horizontally.
+//   000= 2-pixel averaging and 1/2 down-scaling
+//   001= 4-pixel averaging and 1/3 down-scaling
+//   010= 4-pixel averaging and 1/4 down-scaling
+//   011= 8-pixel averaging and 1/7 down-scaling
+//   100= 8-pixel averaging and 1/8 down-scaling
+//   other= reserved
+#define VI_H_DOWNSCALE_CONTROL_0_H_AVG_CONTROL_SHIFT                    _MK_SHIFT_CONST(8)
+#define VI_H_DOWNSCALE_CONTROL_0_H_AVG_CONTROL_FIELD                    (_MK_MASK_CONST(0x7) << VI_H_DOWNSCALE_CONTROL_0_H_AVG_CONTROL_SHIFT)
+#define VI_H_DOWNSCALE_CONTROL_0_H_AVG_CONTROL_RANGE                    10:8
+#define VI_H_DOWNSCALE_CONTROL_0_H_AVG_CONTROL_WOFFSET                  0x0
+#define VI_H_DOWNSCALE_CONTROL_0_H_AVG_CONTROL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_H_DOWNSCALE_CONTROL_0_H_AVG_CONTROL_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_H_DOWNSCALE_CONTROL_0_H_AVG_CONTROL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_H_DOWNSCALE_CONTROL_0_H_AVG_CONTROL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_H_DOWNSCALE_CONTROL_0_H_AVG_CONTROL_A2D2                     _MK_ENUM_CONST(0)
+#define VI_H_DOWNSCALE_CONTROL_0_H_AVG_CONTROL_A4D3                     _MK_ENUM_CONST(1)
+#define VI_H_DOWNSCALE_CONTROL_0_H_AVG_CONTROL_A4D4                     _MK_ENUM_CONST(2)
+#define VI_H_DOWNSCALE_CONTROL_0_H_AVG_CONTROL_A8D7                     _MK_ENUM_CONST(3)
+#define VI_H_DOWNSCALE_CONTROL_0_H_AVG_CONTROL_A8D8                     _MK_ENUM_CONST(4)
+
+// Horizontal Decimation Accumulator Initial Value
+//  The user may initialized the H-Dec accumulator with
+//  a value between 0-(H_ACTIVE_PERIOD) to change the phase
+//  of the decimation pattern.  This will allow the user
+//  to decide which is the first pixel to keep.
+#define VI_H_DOWNSCALE_CONTROL_0_H_DEC_INIT_VAL_SHIFT                   _MK_SHIFT_CONST(16)
+#define VI_H_DOWNSCALE_CONTROL_0_H_DEC_INIT_VAL_FIELD                   (_MK_MASK_CONST(0x1fff) << VI_H_DOWNSCALE_CONTROL_0_H_DEC_INIT_VAL_SHIFT)
+#define VI_H_DOWNSCALE_CONTROL_0_H_DEC_INIT_VAL_RANGE                   28:16
+#define VI_H_DOWNSCALE_CONTROL_0_H_DEC_INIT_VAL_WOFFSET                 0x0
+#define VI_H_DOWNSCALE_CONTROL_0_H_DEC_INIT_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_H_DOWNSCALE_CONTROL_0_H_DEC_INIT_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0x1fff)
+#define VI_H_DOWNSCALE_CONTROL_0_H_DEC_INIT_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_H_DOWNSCALE_CONTROL_0_H_DEC_INIT_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register VI_V_DOWNSCALE_CONTROL_0  // VI Vertical Down-scaling Control
+#define VI_V_DOWNSCALE_CONTROL_0                        _MK_ADDR_CONST(0x44)
+#define VI_V_DOWNSCALE_CONTROL_0_WORD_COUNT                     0x1
+#define VI_V_DOWNSCALE_CONTROL_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define VI_V_DOWNSCALE_CONTROL_0_RESET_MASK                     _MK_MASK_CONST(0x1fff000c)
+#define VI_V_DOWNSCALE_CONTROL_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define VI_V_DOWNSCALE_CONTROL_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_V_DOWNSCALE_CONTROL_0_READ_MASK                      _MK_MASK_CONST(0x1fff370f)
+#define VI_V_DOWNSCALE_CONTROL_0_WRITE_MASK                     _MK_MASK_CONST(0x1fff370f)
+// Input Vertical Size Select  Selects between the VIP and HOST input active
+//  area heights for the denominator in the
+//  downscaling ratio.  Uses VIP_V_ACTIVE_PERIOD or
+//  HOST_V_ACTIVE_PERIOD, which is the height of the
+//  data after cropping.  This is effective only when
+//  V_AVERAGING is DISABLED and V_DOWNSCALING is
+//  ENABLED.
+#define VI_V_DOWNSCALE_CONTROL_0_INPUT_V_SIZE_SEL_SHIFT                 _MK_SHIFT_CONST(0)
+#define VI_V_DOWNSCALE_CONTROL_0_INPUT_V_SIZE_SEL_FIELD                 (_MK_MASK_CONST(0x1) << VI_V_DOWNSCALE_CONTROL_0_INPUT_V_SIZE_SEL_SHIFT)
+#define VI_V_DOWNSCALE_CONTROL_0_INPUT_V_SIZE_SEL_RANGE                 0:0
+#define VI_V_DOWNSCALE_CONTROL_0_INPUT_V_SIZE_SEL_WOFFSET                       0x0
+#define VI_V_DOWNSCALE_CONTROL_0_INPUT_V_SIZE_SEL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_V_DOWNSCALE_CONTROL_0_INPUT_V_SIZE_SEL_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_V_DOWNSCALE_CONTROL_0_INPUT_V_SIZE_SEL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_V_DOWNSCALE_CONTROL_0_INPUT_V_SIZE_SEL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_V_DOWNSCALE_CONTROL_0_INPUT_V_SIZE_SEL_VIP                   _MK_ENUM_CONST(0)
+#define VI_V_DOWNSCALE_CONTROL_0_INPUT_V_SIZE_SEL_HOST                  _MK_ENUM_CONST(1)
+
+// Output Vertical Size Select  Selects between the first and second memory output
+//  frame heights for the numerator in the downscaling
+//  ratio.  Uses FIRST_FRAME_HEIGHT or
+//  SECOND_FRAME_HEIGHT.
+//  This is effective
+//  only when V_AVERAGING is DISABLED and
+//  V_DOWNSCALING is ENABLED.
+#define VI_V_DOWNSCALE_CONTROL_0_OUTPUT_V_SIZE_SEL_SHIFT                        _MK_SHIFT_CONST(1)
+#define VI_V_DOWNSCALE_CONTROL_0_OUTPUT_V_SIZE_SEL_FIELD                        (_MK_MASK_CONST(0x1) << VI_V_DOWNSCALE_CONTROL_0_OUTPUT_V_SIZE_SEL_SHIFT)
+#define VI_V_DOWNSCALE_CONTROL_0_OUTPUT_V_SIZE_SEL_RANGE                        1:1
+#define VI_V_DOWNSCALE_CONTROL_0_OUTPUT_V_SIZE_SEL_WOFFSET                      0x0
+#define VI_V_DOWNSCALE_CONTROL_0_OUTPUT_V_SIZE_SEL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_V_DOWNSCALE_CONTROL_0_OUTPUT_V_SIZE_SEL_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_V_DOWNSCALE_CONTROL_0_OUTPUT_V_SIZE_SEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_V_DOWNSCALE_CONTROL_0_OUTPUT_V_SIZE_SEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_V_DOWNSCALE_CONTROL_0_OUTPUT_V_SIZE_SEL_FIRST                        _MK_ENUM_CONST(0)
+#define VI_V_DOWNSCALE_CONTROL_0_OUTPUT_V_SIZE_SEL_SECOND                       _MK_ENUM_CONST(1)
+
+//  Selects input vertical size into scalers (extension field)
+//  00= Vert. size selected with INPUT_V_SIZE_SEL field (backward compatible)
+//  01= Vert. size of CSI_PPA is provided by CSI_PPA_V_ACTIVE register
+//  10= Vert. size of CSI_PPB is provided by CSI_PPB_V_ACTIVE register
+//  11= Vert. size of ISP     is provided by ISP_V_ACTIVE     register
+// 7:4 reserved
+#define VI_V_DOWNSCALE_CONTROL_0_INPUT_V_SIZE_SEL_EXT_SHIFT                     _MK_SHIFT_CONST(2)
+#define VI_V_DOWNSCALE_CONTROL_0_INPUT_V_SIZE_SEL_EXT_FIELD                     (_MK_MASK_CONST(0x3) << VI_V_DOWNSCALE_CONTROL_0_INPUT_V_SIZE_SEL_EXT_SHIFT)
+#define VI_V_DOWNSCALE_CONTROL_0_INPUT_V_SIZE_SEL_EXT_RANGE                     3:2
+#define VI_V_DOWNSCALE_CONTROL_0_INPUT_V_SIZE_SEL_EXT_WOFFSET                   0x0
+#define VI_V_DOWNSCALE_CONTROL_0_INPUT_V_SIZE_SEL_EXT_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_V_DOWNSCALE_CONTROL_0_INPUT_V_SIZE_SEL_EXT_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define VI_V_DOWNSCALE_CONTROL_0_INPUT_V_SIZE_SEL_EXT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_V_DOWNSCALE_CONTROL_0_INPUT_V_SIZE_SEL_EXT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_V_DOWNSCALE_CONTROL_0_INPUT_V_SIZE_SEL_EXT_USE_INPUT_V_SIZE_SEL                      _MK_ENUM_CONST(0)
+#define VI_V_DOWNSCALE_CONTROL_0_INPUT_V_SIZE_SEL_EXT_CSI_PPA                   _MK_ENUM_CONST(1)
+#define VI_V_DOWNSCALE_CONTROL_0_INPUT_V_SIZE_SEL_EXT_CSI_PPB                   _MK_ENUM_CONST(2)
+#define VI_V_DOWNSCALE_CONTROL_0_INPUT_V_SIZE_SEL_EXT_ISP                       _MK_ENUM_CONST(3)
+
+// Vertical Averaging Control  This specifies the number of lines to
+//  average and to decimate vertically.
+//   000= 2-line averaging and 1/2 down-scaling
+//   001= 4-line averaging and 1/3 down-scaling
+//   010= 4-line averaging and 1/4 down-scaling
+//   011= 8-line averaging and 1/7 down-scaling
+//   100= 8-line averaging and 1/8 down-scaling
+//   other= reserved
+#define VI_V_DOWNSCALE_CONTROL_0_V_AVG_CONTROL_SHIFT                    _MK_SHIFT_CONST(8)
+#define VI_V_DOWNSCALE_CONTROL_0_V_AVG_CONTROL_FIELD                    (_MK_MASK_CONST(0x7) << VI_V_DOWNSCALE_CONTROL_0_V_AVG_CONTROL_SHIFT)
+#define VI_V_DOWNSCALE_CONTROL_0_V_AVG_CONTROL_RANGE                    10:8
+#define VI_V_DOWNSCALE_CONTROL_0_V_AVG_CONTROL_WOFFSET                  0x0
+#define VI_V_DOWNSCALE_CONTROL_0_V_AVG_CONTROL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_V_DOWNSCALE_CONTROL_0_V_AVG_CONTROL_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_V_DOWNSCALE_CONTROL_0_V_AVG_CONTROL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_V_DOWNSCALE_CONTROL_0_V_AVG_CONTROL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_V_DOWNSCALE_CONTROL_0_V_AVG_CONTROL_A2D2                     _MK_ENUM_CONST(0)
+#define VI_V_DOWNSCALE_CONTROL_0_V_AVG_CONTROL_A4D3                     _MK_ENUM_CONST(1)
+#define VI_V_DOWNSCALE_CONTROL_0_V_AVG_CONTROL_A4D4                     _MK_ENUM_CONST(2)
+#define VI_V_DOWNSCALE_CONTROL_0_V_AVG_CONTROL_A8D7                     _MK_ENUM_CONST(3)
+#define VI_V_DOWNSCALE_CONTROL_0_V_AVG_CONTROL_A8D8                     _MK_ENUM_CONST(4)
+
+// Flexible Vertical Scaling   0 = disabled, V_AVG_CONTROL specifies both
+//       vertical averaging and down-scaling
+//       factor.
+//   1 = enabled, fixed 2-line averaging with
+//       vertical downscaling controlled by
+//       V_DOWN_N and V_DOWN_D.
+#define VI_V_DOWNSCALE_CONTROL_0_FLEXIBLE_VSCALE_SHIFT                  _MK_SHIFT_CONST(12)
+#define VI_V_DOWNSCALE_CONTROL_0_FLEXIBLE_VSCALE_FIELD                  (_MK_MASK_CONST(0x1) << VI_V_DOWNSCALE_CONTROL_0_FLEXIBLE_VSCALE_SHIFT)
+#define VI_V_DOWNSCALE_CONTROL_0_FLEXIBLE_VSCALE_RANGE                  12:12
+#define VI_V_DOWNSCALE_CONTROL_0_FLEXIBLE_VSCALE_WOFFSET                        0x0
+#define VI_V_DOWNSCALE_CONTROL_0_FLEXIBLE_VSCALE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_V_DOWNSCALE_CONTROL_0_FLEXIBLE_VSCALE_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_V_DOWNSCALE_CONTROL_0_FLEXIBLE_VSCALE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_V_DOWNSCALE_CONTROL_0_FLEXIBLE_VSCALE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_V_DOWNSCALE_CONTROL_0_FLEXIBLE_VSCALE_DISABLED                       _MK_ENUM_CONST(0)
+#define VI_V_DOWNSCALE_CONTROL_0_FLEXIBLE_VSCALE_ENABLED                        _MK_ENUM_CONST(1)
+
+// Multi-Tap Vertical Averaging Filter   0 = disabled
+//   1 = enabled
+//  This will enable the Multi-Tap filtering
+//  when the Vertical Averaging is enabled.
+//  The filter settings will depend on the
+//  V_AVG_CONTROL value.
+//  000 - 3 Taps (1,2,1)/4
+//  001 - 5 Taps (1,2,2,2,1)/8
+//  010 - 6 Taps (1,1,2,2,1,1)/8
+//  011 - 11 Taps (1,1,1,2,2,2,2,2,1,1,1)/16
+//  100 - 12 Taps (1,1,1,1,2,2,2,2,1,1,1,1)/16
+#define VI_V_DOWNSCALE_CONTROL_0_MULTI_TAP_V_AVG_FILTER_SHIFT                   _MK_SHIFT_CONST(13)
+#define VI_V_DOWNSCALE_CONTROL_0_MULTI_TAP_V_AVG_FILTER_FIELD                   (_MK_MASK_CONST(0x1) << VI_V_DOWNSCALE_CONTROL_0_MULTI_TAP_V_AVG_FILTER_SHIFT)
+#define VI_V_DOWNSCALE_CONTROL_0_MULTI_TAP_V_AVG_FILTER_RANGE                   13:13
+#define VI_V_DOWNSCALE_CONTROL_0_MULTI_TAP_V_AVG_FILTER_WOFFSET                 0x0
+#define VI_V_DOWNSCALE_CONTROL_0_MULTI_TAP_V_AVG_FILTER_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_V_DOWNSCALE_CONTROL_0_MULTI_TAP_V_AVG_FILTER_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_V_DOWNSCALE_CONTROL_0_MULTI_TAP_V_AVG_FILTER_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_V_DOWNSCALE_CONTROL_0_MULTI_TAP_V_AVG_FILTER_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_V_DOWNSCALE_CONTROL_0_MULTI_TAP_V_AVG_FILTER_DISABLED                        _MK_ENUM_CONST(0)
+#define VI_V_DOWNSCALE_CONTROL_0_MULTI_TAP_V_AVG_FILTER_ENABLED                 _MK_ENUM_CONST(1)
+
+// Vertical Decimation Accumulator Initial Value
+//  The user may initialized the V-Dec accumulator with
+//  a value between 0-(V_ACTIVE_PERIOD) to change the phase
+//  of the decimation pattern.  This will allow the user
+//  to decide which is the first line to keep.
+#define VI_V_DOWNSCALE_CONTROL_0_V_DEC_INIT_VAL_SHIFT                   _MK_SHIFT_CONST(16)
+#define VI_V_DOWNSCALE_CONTROL_0_V_DEC_INIT_VAL_FIELD                   (_MK_MASK_CONST(0x1fff) << VI_V_DOWNSCALE_CONTROL_0_V_DEC_INIT_VAL_SHIFT)
+#define VI_V_DOWNSCALE_CONTROL_0_V_DEC_INIT_VAL_RANGE                   28:16
+#define VI_V_DOWNSCALE_CONTROL_0_V_DEC_INIT_VAL_WOFFSET                 0x0
+#define VI_V_DOWNSCALE_CONTROL_0_V_DEC_INIT_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_V_DOWNSCALE_CONTROL_0_V_DEC_INIT_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0x1fff)
+#define VI_V_DOWNSCALE_CONTROL_0_V_DEC_INIT_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_V_DOWNSCALE_CONTROL_0_V_DEC_INIT_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Specifies whether odd/even field affects vertical  decimation.
+//   0 = disabled - odd/even field affects the vertical downscaling
+//   1 = enabled - field is ignored in vertical downscaling
+#define VI_V_DOWNSCALE_CONTROL_0_IGNORE_FIELD_SHIFT                     _MK_SHIFT_CONST(28)
+#define VI_V_DOWNSCALE_CONTROL_0_IGNORE_FIELD_FIELD                     (_MK_MASK_CONST(0x1) << VI_V_DOWNSCALE_CONTROL_0_IGNORE_FIELD_SHIFT)
+#define VI_V_DOWNSCALE_CONTROL_0_IGNORE_FIELD_RANGE                     28:28
+#define VI_V_DOWNSCALE_CONTROL_0_IGNORE_FIELD_WOFFSET                   0x0
+#define VI_V_DOWNSCALE_CONTROL_0_IGNORE_FIELD_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_V_DOWNSCALE_CONTROL_0_IGNORE_FIELD_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_V_DOWNSCALE_CONTROL_0_IGNORE_FIELD_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_V_DOWNSCALE_CONTROL_0_IGNORE_FIELD_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_V_DOWNSCALE_CONTROL_0_IGNORE_FIELD_DISABLED                  _MK_ENUM_CONST(0)
+#define VI_V_DOWNSCALE_CONTROL_0_IGNORE_FIELD_ENABLED                   _MK_ENUM_CONST(1)
+
+
+// Register VI_CSC_Y_0  // CSC Y Offset and Gain
+#define VI_CSC_Y_0                      _MK_ADDR_CONST(0x45)
+#define VI_CSC_Y_0_WORD_COUNT                   0x1
+#define VI_CSC_Y_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define VI_CSC_Y_0_RESET_MASK                   _MK_MASK_CONST(0x0)
+#define VI_CSC_Y_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define VI_CSC_Y_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_CSC_Y_0_READ_MASK                    _MK_MASK_CONST(0x3ff00ff)
+#define VI_CSC_Y_0_WRITE_MASK                   _MK_MASK_CONST(0x3ff00ff)
+// Y Offset in s.7.0 format
+#define VI_CSC_Y_0_YOF_SHIFT                    _MK_SHIFT_CONST(0)
+#define VI_CSC_Y_0_YOF_FIELD                    (_MK_MASK_CONST(0xff) << VI_CSC_Y_0_YOF_SHIFT)
+#define VI_CSC_Y_0_YOF_RANGE                    7:0
+#define VI_CSC_Y_0_YOF_WOFFSET                  0x0
+#define VI_CSC_Y_0_YOF_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_CSC_Y_0_YOF_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_CSC_Y_0_YOF_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_CSC_Y_0_YOF_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Y Gain for R, G, B colors in 2.8 format
+#define VI_CSC_Y_0_KYRGB_SHIFT                  _MK_SHIFT_CONST(16)
+#define VI_CSC_Y_0_KYRGB_FIELD                  (_MK_MASK_CONST(0x3ff) << VI_CSC_Y_0_KYRGB_SHIFT)
+#define VI_CSC_Y_0_KYRGB_RANGE                  25:16
+#define VI_CSC_Y_0_KYRGB_WOFFSET                        0x0
+#define VI_CSC_Y_0_KYRGB_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_CSC_Y_0_KYRGB_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_CSC_Y_0_KYRGB_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_CSC_Y_0_KYRGB_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register VI_CSC_UV_R_0  // CSC U & V coefficent for R
+#define VI_CSC_UV_R_0                   _MK_ADDR_CONST(0x46)
+#define VI_CSC_UV_R_0_WORD_COUNT                        0x1
+#define VI_CSC_UV_R_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define VI_CSC_UV_R_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define VI_CSC_UV_R_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define VI_CSC_UV_R_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_CSC_UV_R_0_READ_MASK                         _MK_MASK_CONST(0x7ff07ff)
+#define VI_CSC_UV_R_0_WRITE_MASK                        _MK_MASK_CONST(0x7ff07ff)
+// U coefficients for R in s.2.8 format
+#define VI_CSC_UV_R_0_KUR_SHIFT                 _MK_SHIFT_CONST(0)
+#define VI_CSC_UV_R_0_KUR_FIELD                 (_MK_MASK_CONST(0x7ff) << VI_CSC_UV_R_0_KUR_SHIFT)
+#define VI_CSC_UV_R_0_KUR_RANGE                 10:0
+#define VI_CSC_UV_R_0_KUR_WOFFSET                       0x0
+#define VI_CSC_UV_R_0_KUR_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_CSC_UV_R_0_KUR_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_CSC_UV_R_0_KUR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_CSC_UV_R_0_KUR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// V coefficients for R in s.2.8 format
+#define VI_CSC_UV_R_0_KVR_SHIFT                 _MK_SHIFT_CONST(16)
+#define VI_CSC_UV_R_0_KVR_FIELD                 (_MK_MASK_CONST(0x7ff) << VI_CSC_UV_R_0_KVR_SHIFT)
+#define VI_CSC_UV_R_0_KVR_RANGE                 26:16
+#define VI_CSC_UV_R_0_KVR_WOFFSET                       0x0
+#define VI_CSC_UV_R_0_KVR_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_CSC_UV_R_0_KVR_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_CSC_UV_R_0_KVR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_CSC_UV_R_0_KVR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register VI_CSC_UV_G_0  // CSC U & V coefficent for G
+#define VI_CSC_UV_G_0                   _MK_ADDR_CONST(0x47)
+#define VI_CSC_UV_G_0_WORD_COUNT                        0x1
+#define VI_CSC_UV_G_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define VI_CSC_UV_G_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define VI_CSC_UV_G_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define VI_CSC_UV_G_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_CSC_UV_G_0_READ_MASK                         _MK_MASK_CONST(0x3ff03ff)
+#define VI_CSC_UV_G_0_WRITE_MASK                        _MK_MASK_CONST(0x3ff03ff)
+// U coefficients for G in s.1.8 format
+#define VI_CSC_UV_G_0_KUG_SHIFT                 _MK_SHIFT_CONST(0)
+#define VI_CSC_UV_G_0_KUG_FIELD                 (_MK_MASK_CONST(0x3ff) << VI_CSC_UV_G_0_KUG_SHIFT)
+#define VI_CSC_UV_G_0_KUG_RANGE                 9:0
+#define VI_CSC_UV_G_0_KUG_WOFFSET                       0x0
+#define VI_CSC_UV_G_0_KUG_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_CSC_UV_G_0_KUG_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_CSC_UV_G_0_KUG_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_CSC_UV_G_0_KUG_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// V coefficients for G in s.1.8 format
+#define VI_CSC_UV_G_0_KVG_SHIFT                 _MK_SHIFT_CONST(16)
+#define VI_CSC_UV_G_0_KVG_FIELD                 (_MK_MASK_CONST(0x3ff) << VI_CSC_UV_G_0_KVG_SHIFT)
+#define VI_CSC_UV_G_0_KVG_RANGE                 25:16
+#define VI_CSC_UV_G_0_KVG_WOFFSET                       0x0
+#define VI_CSC_UV_G_0_KVG_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_CSC_UV_G_0_KVG_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_CSC_UV_G_0_KVG_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_CSC_UV_G_0_KVG_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register VI_CSC_UV_B_0  // CSC U & V coefficent for B
+#define VI_CSC_UV_B_0                   _MK_ADDR_CONST(0x48)
+#define VI_CSC_UV_B_0_WORD_COUNT                        0x1
+#define VI_CSC_UV_B_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define VI_CSC_UV_B_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define VI_CSC_UV_B_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define VI_CSC_UV_B_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_CSC_UV_B_0_READ_MASK                         _MK_MASK_CONST(0x7ff07ff)
+#define VI_CSC_UV_B_0_WRITE_MASK                        _MK_MASK_CONST(0x7ff07ff)
+// U coefficients for B in s.2.8 format
+#define VI_CSC_UV_B_0_KUB_SHIFT                 _MK_SHIFT_CONST(0)
+#define VI_CSC_UV_B_0_KUB_FIELD                 (_MK_MASK_CONST(0x7ff) << VI_CSC_UV_B_0_KUB_SHIFT)
+#define VI_CSC_UV_B_0_KUB_RANGE                 10:0
+#define VI_CSC_UV_B_0_KUB_WOFFSET                       0x0
+#define VI_CSC_UV_B_0_KUB_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_CSC_UV_B_0_KUB_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_CSC_UV_B_0_KUB_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_CSC_UV_B_0_KUB_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// V coefficients for B in s.2.8 format
+#define VI_CSC_UV_B_0_KVB_SHIFT                 _MK_SHIFT_CONST(16)
+#define VI_CSC_UV_B_0_KVB_FIELD                 (_MK_MASK_CONST(0x7ff) << VI_CSC_UV_B_0_KVB_SHIFT)
+#define VI_CSC_UV_B_0_KVB_RANGE                 26:16
+#define VI_CSC_UV_B_0_KVB_WOFFSET                       0x0
+#define VI_CSC_UV_B_0_KVB_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_CSC_UV_B_0_KVB_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_CSC_UV_B_0_KVB_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_CSC_UV_B_0_KVB_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register VI_CSC_ALPHA_0  // RGB Color Space Converter Alpha value
+#define VI_CSC_ALPHA_0                  _MK_ADDR_CONST(0x49)
+#define VI_CSC_ALPHA_0_WORD_COUNT                       0x1
+#define VI_CSC_ALPHA_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define VI_CSC_ALPHA_0_RESET_MASK                       _MK_MASK_CONST(0xff)
+#define VI_CSC_ALPHA_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define VI_CSC_ALPHA_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_CSC_ALPHA_0_READ_MASK                        _MK_MASK_CONST(0xff)
+#define VI_CSC_ALPHA_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
+// When output format to memory is selected
+//  for RGB888, the pixel data is 32-bit aligned
+//  The value programmed here will be appended to the
+//  RGB888 data as the 8 MSBs and can be used as an
+//  alpha value.
+#define VI_CSC_ALPHA_0_RGB888_ALPHA_SHIFT                       _MK_SHIFT_CONST(0)
+#define VI_CSC_ALPHA_0_RGB888_ALPHA_FIELD                       (_MK_MASK_CONST(0xff) << VI_CSC_ALPHA_0_RGB888_ALPHA_SHIFT)
+#define VI_CSC_ALPHA_0_RGB888_ALPHA_RANGE                       7:0
+#define VI_CSC_ALPHA_0_RGB888_ALPHA_WOFFSET                     0x0
+#define VI_CSC_ALPHA_0_RGB888_ALPHA_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_CSC_ALPHA_0_RGB888_ALPHA_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define VI_CSC_ALPHA_0_RGB888_ALPHA_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_CSC_ALPHA_0_RGB888_ALPHA_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register VI_HOST_VSYNC_0  // Valid when INPUT_SOURCE is HOST
+#define VI_HOST_VSYNC_0                 _MK_ADDR_CONST(0x4a)
+#define VI_HOST_VSYNC_0_WORD_COUNT                      0x1
+#define VI_HOST_VSYNC_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define VI_HOST_VSYNC_0_RESET_MASK                      _MK_MASK_CONST(0x0)
+#define VI_HOST_VSYNC_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define VI_HOST_VSYNC_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define VI_HOST_VSYNC_0_READ_MASK                       _MK_MASK_CONST(0x1)
+#define VI_HOST_VSYNC_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
+// This triggers VI's internal VSYNC generation
+// Always write once to this register with '1'
+// before writing the Frame's data to Y_FIFO_DATA
+#define VI_HOST_VSYNC_0_HOST_VSYNC_TRIGGER_SHIFT                        _MK_SHIFT_CONST(0)
+#define VI_HOST_VSYNC_0_HOST_VSYNC_TRIGGER_FIELD                        (_MK_MASK_CONST(0x1) << VI_HOST_VSYNC_0_HOST_VSYNC_TRIGGER_SHIFT)
+#define VI_HOST_VSYNC_0_HOST_VSYNC_TRIGGER_RANGE                        0:0
+#define VI_HOST_VSYNC_0_HOST_VSYNC_TRIGGER_WOFFSET                      0x0
+#define VI_HOST_VSYNC_0_HOST_VSYNC_TRIGGER_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_HOST_VSYNC_0_HOST_VSYNC_TRIGGER_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_HOST_VSYNC_0_HOST_VSYNC_TRIGGER_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_HOST_VSYNC_0_HOST_VSYNC_TRIGGER_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register VI_COMMAND_0  // VI Command
+#define VI_COMMAND_0                    _MK_ADDR_CONST(0x4b)
+#define VI_COMMAND_0_WORD_COUNT                         0x1
+#define VI_COMMAND_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define VI_COMMAND_0_RESET_MASK                         _MK_MASK_CONST(0x1)
+#define VI_COMMAND_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define VI_COMMAND_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_COMMAND_0_READ_MASK                  _MK_MASK_CONST(0x1fff0f01)
+#define VI_COMMAND_0_WRITE_MASK                         _MK_MASK_CONST(0x1fff0f01)
+// Process Odd/Even field  (effective when INPUT_SOURCE is HOST)
+//  Writing to this bit will initialize VI
+//  to receive one field of video.
+//   0= odd field
+//   1= even field
+#define VI_COMMAND_0_PROCESS_FIELD_SHIFT                        _MK_SHIFT_CONST(0)
+#define VI_COMMAND_0_PROCESS_FIELD_FIELD                        (_MK_MASK_CONST(0x1) << VI_COMMAND_0_PROCESS_FIELD_SHIFT)
+#define VI_COMMAND_0_PROCESS_FIELD_RANGE                        0:0
+#define VI_COMMAND_0_PROCESS_FIELD_WOFFSET                      0x0
+#define VI_COMMAND_0_PROCESS_FIELD_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_COMMAND_0_PROCESS_FIELD_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define VI_COMMAND_0_PROCESS_FIELD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_COMMAND_0_PROCESS_FIELD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_COMMAND_0_PROCESS_FIELD_ODD                  _MK_ENUM_CONST(0)
+#define VI_COMMAND_0_PROCESS_FIELD_EVEN                 _MK_ENUM_CONST(1)
+
+// Y-FIFO Threshold
+//  This specifies maximum number of filled
+//  locations in Y-FIFO for the Y-FIFO Threshold
+//  Status bit.
+#define VI_COMMAND_0_Y_FIFO_THRESHOLD_SHIFT                     _MK_SHIFT_CONST(8)
+#define VI_COMMAND_0_Y_FIFO_THRESHOLD_FIELD                     (_MK_MASK_CONST(0xf) << VI_COMMAND_0_Y_FIFO_THRESHOLD_SHIFT)
+#define VI_COMMAND_0_Y_FIFO_THRESHOLD_RANGE                     11:8
+#define VI_COMMAND_0_Y_FIFO_THRESHOLD_WOFFSET                   0x0
+#define VI_COMMAND_0_Y_FIFO_THRESHOLD_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_COMMAND_0_Y_FIFO_THRESHOLD_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_COMMAND_0_Y_FIFO_THRESHOLD_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_COMMAND_0_Y_FIFO_THRESHOLD_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Vertical Counter Threshold
+//  This specifies a threshold which, when
+//  exceeded, would generate the vertical
+//  counter interrupt if the interrupt is
+//  enabled. This is used to detect the case
+//  when the host is sending too many input data
+//  than expected by VI module.
+#define VI_COMMAND_0_V_COUNTER_THRESHOLD_SHIFT                  _MK_SHIFT_CONST(16)
+#define VI_COMMAND_0_V_COUNTER_THRESHOLD_FIELD                  (_MK_MASK_CONST(0x1fff) << VI_COMMAND_0_V_COUNTER_THRESHOLD_SHIFT)
+#define VI_COMMAND_0_V_COUNTER_THRESHOLD_RANGE                  28:16
+#define VI_COMMAND_0_V_COUNTER_THRESHOLD_WOFFSET                        0x0
+#define VI_COMMAND_0_V_COUNTER_THRESHOLD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_COMMAND_0_V_COUNTER_THRESHOLD_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_COMMAND_0_V_COUNTER_THRESHOLD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_COMMAND_0_V_COUNTER_THRESHOLD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register VI_HOST_FIFO_STATUS_0  // Host FIFO status
+#define VI_HOST_FIFO_STATUS_0                   _MK_ADDR_CONST(0x4c)
+#define VI_HOST_FIFO_STATUS_0_WORD_COUNT                        0x1
+#define VI_HOST_FIFO_STATUS_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define VI_HOST_FIFO_STATUS_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define VI_HOST_FIFO_STATUS_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define VI_HOST_FIFO_STATUS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_HOST_FIFO_STATUS_0_READ_MASK                         _MK_MASK_CONST(0x770f)
+#define VI_HOST_FIFO_STATUS_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+// This indicates the number of filled locations
+//  in Y-FIFO. If the returned value is 4'h0, the
+//  fifo is empty and if the returned value is
+//  4'hF then the fifo is full.
+#define VI_HOST_FIFO_STATUS_0_Y_FIFO_STATUS_SHIFT                       _MK_SHIFT_CONST(0)
+#define VI_HOST_FIFO_STATUS_0_Y_FIFO_STATUS_FIELD                       (_MK_MASK_CONST(0xf) << VI_HOST_FIFO_STATUS_0_Y_FIFO_STATUS_SHIFT)
+#define VI_HOST_FIFO_STATUS_0_Y_FIFO_STATUS_RANGE                       3:0
+#define VI_HOST_FIFO_STATUS_0_Y_FIFO_STATUS_WOFFSET                     0x0
+#define VI_HOST_FIFO_STATUS_0_Y_FIFO_STATUS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_HOST_FIFO_STATUS_0_Y_FIFO_STATUS_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_HOST_FIFO_STATUS_0_Y_FIFO_STATUS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_HOST_FIFO_STATUS_0_Y_FIFO_STATUS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// This indicates the number of filled locations
+//  in U-FIFO. If the returned value is 3'h0, the
+//  fifo is empty and if the returned value is
+//  3'h7 then the fifo is full.
+#define VI_HOST_FIFO_STATUS_0_U_FIFO_STATUS_SHIFT                       _MK_SHIFT_CONST(8)
+#define VI_HOST_FIFO_STATUS_0_U_FIFO_STATUS_FIELD                       (_MK_MASK_CONST(0x7) << VI_HOST_FIFO_STATUS_0_U_FIFO_STATUS_SHIFT)
+#define VI_HOST_FIFO_STATUS_0_U_FIFO_STATUS_RANGE                       10:8
+#define VI_HOST_FIFO_STATUS_0_U_FIFO_STATUS_WOFFSET                     0x0
+#define VI_HOST_FIFO_STATUS_0_U_FIFO_STATUS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_HOST_FIFO_STATUS_0_U_FIFO_STATUS_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_HOST_FIFO_STATUS_0_U_FIFO_STATUS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_HOST_FIFO_STATUS_0_U_FIFO_STATUS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// This indicates the number of filled locations
+//  in V-FIFO. If the returned value is 3'h0, the
+//  fifo is empty and if the returned value is
+//  3'h7 then the fifo is full.
+#define VI_HOST_FIFO_STATUS_0_V_FIFO_STATUS_SHIFT                       _MK_SHIFT_CONST(12)
+#define VI_HOST_FIFO_STATUS_0_V_FIFO_STATUS_FIELD                       (_MK_MASK_CONST(0x7) << VI_HOST_FIFO_STATUS_0_V_FIFO_STATUS_SHIFT)
+#define VI_HOST_FIFO_STATUS_0_V_FIFO_STATUS_RANGE                       14:12
+#define VI_HOST_FIFO_STATUS_0_V_FIFO_STATUS_WOFFSET                     0x0
+#define VI_HOST_FIFO_STATUS_0_V_FIFO_STATUS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_HOST_FIFO_STATUS_0_V_FIFO_STATUS_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_HOST_FIFO_STATUS_0_V_FIFO_STATUS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_HOST_FIFO_STATUS_0_V_FIFO_STATUS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register VI_INTERRUPT_MASK_0  // Interrupt Mask
+#define VI_INTERRUPT_MASK_0                     _MK_ADDR_CONST(0x4d)
+#define VI_INTERRUPT_MASK_0_WORD_COUNT                  0x1
+#define VI_INTERRUPT_MASK_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_RESET_MASK                  _MK_MASK_CONST(0x1fefffff)
+#define VI_INTERRUPT_MASK_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_READ_MASK                   _MK_MASK_CONST(0x1fefffff)
+#define VI_INTERRUPT_MASK_0_WRITE_MASK                  _MK_MASK_CONST(0x1fefffff)
+// VD8 pin Interrupt Mask  This bit controls interrupt when VD8
+//  rising/falling edge is detected.
+//   0= Disabled
+//   1= Enabled
+#define VI_INTERRUPT_MASK_0_VD8_INT_MASK_SHIFT                  _MK_SHIFT_CONST(0)
+#define VI_INTERRUPT_MASK_0_VD8_INT_MASK_FIELD                  (_MK_MASK_CONST(0x1) << VI_INTERRUPT_MASK_0_VD8_INT_MASK_SHIFT)
+#define VI_INTERRUPT_MASK_0_VD8_INT_MASK_RANGE                  0:0
+#define VI_INTERRUPT_MASK_0_VD8_INT_MASK_WOFFSET                        0x0
+#define VI_INTERRUPT_MASK_0_VD8_INT_MASK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_VD8_INT_MASK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_MASK_0_VD8_INT_MASK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_VD8_INT_MASK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_VD8_INT_MASK_DISABLED                       _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_MASK_0_VD8_INT_MASK_ENABLED                        _MK_ENUM_CONST(1)
+
+// VD9 pin Interrupt Mask  This bit controls interrupt when VD9
+//  rising/falling edge is detected.
+//   0= Disabled
+//   1= Enabled
+#define VI_INTERRUPT_MASK_0_VD9_INT_MASK_SHIFT                  _MK_SHIFT_CONST(1)
+#define VI_INTERRUPT_MASK_0_VD9_INT_MASK_FIELD                  (_MK_MASK_CONST(0x1) << VI_INTERRUPT_MASK_0_VD9_INT_MASK_SHIFT)
+#define VI_INTERRUPT_MASK_0_VD9_INT_MASK_RANGE                  1:1
+#define VI_INTERRUPT_MASK_0_VD9_INT_MASK_WOFFSET                        0x0
+#define VI_INTERRUPT_MASK_0_VD9_INT_MASK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_VD9_INT_MASK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_MASK_0_VD9_INT_MASK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_VD9_INT_MASK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_VD9_INT_MASK_DISABLED                       _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_MASK_0_VD9_INT_MASK_ENABLED                        _MK_ENUM_CONST(1)
+
+// VD10 pin Interrupt Mask  This bit controls interrupt when VD10
+//  rising/falling edge is detected.
+//   0= Disabled
+//   1= Enabled
+#define VI_INTERRUPT_MASK_0_VD10_INT_MASK_SHIFT                 _MK_SHIFT_CONST(2)
+#define VI_INTERRUPT_MASK_0_VD10_INT_MASK_FIELD                 (_MK_MASK_CONST(0x1) << VI_INTERRUPT_MASK_0_VD10_INT_MASK_SHIFT)
+#define VI_INTERRUPT_MASK_0_VD10_INT_MASK_RANGE                 2:2
+#define VI_INTERRUPT_MASK_0_VD10_INT_MASK_WOFFSET                       0x0
+#define VI_INTERRUPT_MASK_0_VD10_INT_MASK_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_VD10_INT_MASK_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_MASK_0_VD10_INT_MASK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_VD10_INT_MASK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_VD10_INT_MASK_DISABLED                      _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_MASK_0_VD10_INT_MASK_ENABLED                       _MK_ENUM_CONST(1)
+
+// VD11 pin Interrupt Mask  This bit controls interrupt when VD11
+//  rising/falling edge is detected.
+//   0= Disabled
+//   1= Enabled
+#define VI_INTERRUPT_MASK_0_VD11_INT_MASK_SHIFT                 _MK_SHIFT_CONST(3)
+#define VI_INTERRUPT_MASK_0_VD11_INT_MASK_FIELD                 (_MK_MASK_CONST(0x1) << VI_INTERRUPT_MASK_0_VD11_INT_MASK_SHIFT)
+#define VI_INTERRUPT_MASK_0_VD11_INT_MASK_RANGE                 3:3
+#define VI_INTERRUPT_MASK_0_VD11_INT_MASK_WOFFSET                       0x0
+#define VI_INTERRUPT_MASK_0_VD11_INT_MASK_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_VD11_INT_MASK_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_MASK_0_VD11_INT_MASK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_VD11_INT_MASK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_VD11_INT_MASK_DISABLED                      _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_MASK_0_VD11_INT_MASK_ENABLED                       _MK_ENUM_CONST(1)
+
+// VGP4 pin Interrupt Mask  This bit controls interrupt when VGP4
+//  rising/falling edge is detected.
+//   0= Disabled
+//   1= Enabled
+#define VI_INTERRUPT_MASK_0_VGP4_INT_MASK_SHIFT                 _MK_SHIFT_CONST(4)
+#define VI_INTERRUPT_MASK_0_VGP4_INT_MASK_FIELD                 (_MK_MASK_CONST(0x1) << VI_INTERRUPT_MASK_0_VGP4_INT_MASK_SHIFT)
+#define VI_INTERRUPT_MASK_0_VGP4_INT_MASK_RANGE                 4:4
+#define VI_INTERRUPT_MASK_0_VGP4_INT_MASK_WOFFSET                       0x0
+#define VI_INTERRUPT_MASK_0_VGP4_INT_MASK_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_VGP4_INT_MASK_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_MASK_0_VGP4_INT_MASK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_VGP4_INT_MASK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_VGP4_INT_MASK_DISABLED                      _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_MASK_0_VGP4_INT_MASK_ENABLED                       _MK_ENUM_CONST(1)
+
+// VGP5 pin Interrupt Mask  This bit controls interrupt when VGP5
+//  rising/falling edge is detected.
+//   0= Disabled
+//   1= Enabled
+#define VI_INTERRUPT_MASK_0_VGP5_INT_MASK_SHIFT                 _MK_SHIFT_CONST(5)
+#define VI_INTERRUPT_MASK_0_VGP5_INT_MASK_FIELD                 (_MK_MASK_CONST(0x1) << VI_INTERRUPT_MASK_0_VGP5_INT_MASK_SHIFT)
+#define VI_INTERRUPT_MASK_0_VGP5_INT_MASK_RANGE                 5:5
+#define VI_INTERRUPT_MASK_0_VGP5_INT_MASK_WOFFSET                       0x0
+#define VI_INTERRUPT_MASK_0_VGP5_INT_MASK_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_VGP5_INT_MASK_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_MASK_0_VGP5_INT_MASK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_VGP5_INT_MASK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_VGP5_INT_MASK_DISABLED                      _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_MASK_0_VGP5_INT_MASK_ENABLED                       _MK_ENUM_CONST(1)
+
+// VGP6 pin Interrupt Mask  This bit controls interrupt when VGP6
+//  rising/falling edge is detected.
+//   0= Disabled
+//   1= Enabled
+#define VI_INTERRUPT_MASK_0_VGP6_INT_MASK_SHIFT                 _MK_SHIFT_CONST(6)
+#define VI_INTERRUPT_MASK_0_VGP6_INT_MASK_FIELD                 (_MK_MASK_CONST(0x1) << VI_INTERRUPT_MASK_0_VGP6_INT_MASK_SHIFT)
+#define VI_INTERRUPT_MASK_0_VGP6_INT_MASK_RANGE                 6:6
+#define VI_INTERRUPT_MASK_0_VGP6_INT_MASK_WOFFSET                       0x0
+#define VI_INTERRUPT_MASK_0_VGP6_INT_MASK_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_VGP6_INT_MASK_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_MASK_0_VGP6_INT_MASK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_VGP6_INT_MASK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_VGP6_INT_MASK_DISABLED                      _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_MASK_0_VGP6_INT_MASK_ENABLED                       _MK_ENUM_CONST(1)
+
+// VHS pin Interrupt Mask  This bit controls interrupt when VHS
+//  rising/falling edge is detected.
+//   0= Disabled
+//   1= Enabled
+#define VI_INTERRUPT_MASK_0_VHS_INT_MASK_SHIFT                  _MK_SHIFT_CONST(7)
+#define VI_INTERRUPT_MASK_0_VHS_INT_MASK_FIELD                  (_MK_MASK_CONST(0x1) << VI_INTERRUPT_MASK_0_VHS_INT_MASK_SHIFT)
+#define VI_INTERRUPT_MASK_0_VHS_INT_MASK_RANGE                  7:7
+#define VI_INTERRUPT_MASK_0_VHS_INT_MASK_WOFFSET                        0x0
+#define VI_INTERRUPT_MASK_0_VHS_INT_MASK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_VHS_INT_MASK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_MASK_0_VHS_INT_MASK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_VHS_INT_MASK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_VHS_INT_MASK_DISABLED                       _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_MASK_0_VHS_INT_MASK_ENABLED                        _MK_ENUM_CONST(1)
+
+// VVS pin Interrupt Mask  This bit controls interrupt when VVS
+//  rising/falling edge is detected.
+//   0= Disabled
+//   1= Enabled
+#define VI_INTERRUPT_MASK_0_VVS_INT_MASK_SHIFT                  _MK_SHIFT_CONST(8)
+#define VI_INTERRUPT_MASK_0_VVS_INT_MASK_FIELD                  (_MK_MASK_CONST(0x1) << VI_INTERRUPT_MASK_0_VVS_INT_MASK_SHIFT)
+#define VI_INTERRUPT_MASK_0_VVS_INT_MASK_RANGE                  8:8
+#define VI_INTERRUPT_MASK_0_VVS_INT_MASK_WOFFSET                        0x0
+#define VI_INTERRUPT_MASK_0_VVS_INT_MASK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_VVS_INT_MASK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_MASK_0_VVS_INT_MASK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_VVS_INT_MASK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_VVS_INT_MASK_DISABLED                       _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_MASK_0_VVS_INT_MASK_ENABLED                        _MK_ENUM_CONST(1)
+
+// Vertical Counter Interrupt Mask  (effective when VIDEO_SOURCE is HOST)
+//  This bit controls interrupt when the
+//  vertical counter threshold is reached.
+//   0= Disabled
+//   1= Enabled
+#define VI_INTERRUPT_MASK_0_V_COUNTER_INT_MASK_SHIFT                    _MK_SHIFT_CONST(9)
+#define VI_INTERRUPT_MASK_0_V_COUNTER_INT_MASK_FIELD                    (_MK_MASK_CONST(0x1) << VI_INTERRUPT_MASK_0_V_COUNTER_INT_MASK_SHIFT)
+#define VI_INTERRUPT_MASK_0_V_COUNTER_INT_MASK_RANGE                    9:9
+#define VI_INTERRUPT_MASK_0_V_COUNTER_INT_MASK_WOFFSET                  0x0
+#define VI_INTERRUPT_MASK_0_V_COUNTER_INT_MASK_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_V_COUNTER_INT_MASK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_MASK_0_V_COUNTER_INT_MASK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_V_COUNTER_INT_MASK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_V_COUNTER_INT_MASK_DISABLED                 _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_MASK_0_V_COUNTER_INT_MASK_ENABLED                  _MK_ENUM_CONST(1)
+
+// Y-FIFO Threshold Interrupt Mask  This bit controls interrupt when the number
+//  of filled locations in Y-FIFO is equal or
+//  greater than the Y_FIFO_THRESHOLD value.
+//  This bit should be set to 1 only when
+//  INPUT_SOURCE is HOST.
+//   0= Disabled
+//   1= Enabled
+#define VI_INTERRUPT_MASK_0_Y_THRESHOLD_INT_MASK_SHIFT                  _MK_SHIFT_CONST(10)
+#define VI_INTERRUPT_MASK_0_Y_THRESHOLD_INT_MASK_FIELD                  (_MK_MASK_CONST(0x1) << VI_INTERRUPT_MASK_0_Y_THRESHOLD_INT_MASK_SHIFT)
+#define VI_INTERRUPT_MASK_0_Y_THRESHOLD_INT_MASK_RANGE                  10:10
+#define VI_INTERRUPT_MASK_0_Y_THRESHOLD_INT_MASK_WOFFSET                        0x0
+#define VI_INTERRUPT_MASK_0_Y_THRESHOLD_INT_MASK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_Y_THRESHOLD_INT_MASK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_MASK_0_Y_THRESHOLD_INT_MASK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_Y_THRESHOLD_INT_MASK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_Y_THRESHOLD_INT_MASK_DISABLED                       _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_MASK_0_Y_THRESHOLD_INT_MASK_ENABLED                        _MK_ENUM_CONST(1)
+
+// Buffer Done First Output Interrupt Mask  This bit controls interrupt when the
+//  First Output to memory has written
+//  a buffer to memory.
+//   0= Disabled
+//   1= Enabled
+#define VI_INTERRUPT_MASK_0_BUFFER_FIRST_OUTPUT_INT_MASK_SHIFT                  _MK_SHIFT_CONST(11)
+#define VI_INTERRUPT_MASK_0_BUFFER_FIRST_OUTPUT_INT_MASK_FIELD                  (_MK_MASK_CONST(0x1) << VI_INTERRUPT_MASK_0_BUFFER_FIRST_OUTPUT_INT_MASK_SHIFT)
+#define VI_INTERRUPT_MASK_0_BUFFER_FIRST_OUTPUT_INT_MASK_RANGE                  11:11
+#define VI_INTERRUPT_MASK_0_BUFFER_FIRST_OUTPUT_INT_MASK_WOFFSET                        0x0
+#define VI_INTERRUPT_MASK_0_BUFFER_FIRST_OUTPUT_INT_MASK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_BUFFER_FIRST_OUTPUT_INT_MASK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_MASK_0_BUFFER_FIRST_OUTPUT_INT_MASK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_BUFFER_FIRST_OUTPUT_INT_MASK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_BUFFER_FIRST_OUTPUT_INT_MASK_DISABLED                       _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_MASK_0_BUFFER_FIRST_OUTPUT_INT_MASK_ENABLED                        _MK_ENUM_CONST(1)
+
+// Frame Done First Output Interrupt Mask  This bit controls interrupt when the
+//  First Output to memory has written
+//  a frame to memory.
+//   0= Disabled
+//   1= Enabled
+#define VI_INTERRUPT_MASK_0_FRAME_FIRST_OUTPUT_INT_MASK_SHIFT                   _MK_SHIFT_CONST(12)
+#define VI_INTERRUPT_MASK_0_FRAME_FIRST_OUTPUT_INT_MASK_FIELD                   (_MK_MASK_CONST(0x1) << VI_INTERRUPT_MASK_0_FRAME_FIRST_OUTPUT_INT_MASK_SHIFT)
+#define VI_INTERRUPT_MASK_0_FRAME_FIRST_OUTPUT_INT_MASK_RANGE                   12:12
+#define VI_INTERRUPT_MASK_0_FRAME_FIRST_OUTPUT_INT_MASK_WOFFSET                 0x0
+#define VI_INTERRUPT_MASK_0_FRAME_FIRST_OUTPUT_INT_MASK_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_FRAME_FIRST_OUTPUT_INT_MASK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_MASK_0_FRAME_FIRST_OUTPUT_INT_MASK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_FRAME_FIRST_OUTPUT_INT_MASK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_FRAME_FIRST_OUTPUT_INT_MASK_DISABLED                        _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_MASK_0_FRAME_FIRST_OUTPUT_INT_MASK_ENABLED                 _MK_ENUM_CONST(1)
+
+// Buffer Done Second Output Interrupt Mask  This bit controls interrupt when the
+//  Second Output to memory has written
+//  a buffer to memory.
+//   0= Disabled
+//   1= Enabled
+#define VI_INTERRUPT_MASK_0_BUFFER_SECOND_OUTPUT_INT_MASK_SHIFT                 _MK_SHIFT_CONST(13)
+#define VI_INTERRUPT_MASK_0_BUFFER_SECOND_OUTPUT_INT_MASK_FIELD                 (_MK_MASK_CONST(0x1) << VI_INTERRUPT_MASK_0_BUFFER_SECOND_OUTPUT_INT_MASK_SHIFT)
+#define VI_INTERRUPT_MASK_0_BUFFER_SECOND_OUTPUT_INT_MASK_RANGE                 13:13
+#define VI_INTERRUPT_MASK_0_BUFFER_SECOND_OUTPUT_INT_MASK_WOFFSET                       0x0
+#define VI_INTERRUPT_MASK_0_BUFFER_SECOND_OUTPUT_INT_MASK_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_BUFFER_SECOND_OUTPUT_INT_MASK_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_MASK_0_BUFFER_SECOND_OUTPUT_INT_MASK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_BUFFER_SECOND_OUTPUT_INT_MASK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_BUFFER_SECOND_OUTPUT_INT_MASK_DISABLED                      _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_MASK_0_BUFFER_SECOND_OUTPUT_INT_MASK_ENABLED                       _MK_ENUM_CONST(1)
+
+// Buffer Done Second Output Interrupt Mask  This bit controls interrupt when the
+//  Second Output to memory has written
+//  a frame to memory.
+//   0= Disabled
+//   1= Enabled
+#define VI_INTERRUPT_MASK_0_FRAME_SECOND_OUTPUT_INT_MASK_SHIFT                  _MK_SHIFT_CONST(14)
+#define VI_INTERRUPT_MASK_0_FRAME_SECOND_OUTPUT_INT_MASK_FIELD                  (_MK_MASK_CONST(0x1) << VI_INTERRUPT_MASK_0_FRAME_SECOND_OUTPUT_INT_MASK_SHIFT)
+#define VI_INTERRUPT_MASK_0_FRAME_SECOND_OUTPUT_INT_MASK_RANGE                  14:14
+#define VI_INTERRUPT_MASK_0_FRAME_SECOND_OUTPUT_INT_MASK_WOFFSET                        0x0
+#define VI_INTERRUPT_MASK_0_FRAME_SECOND_OUTPUT_INT_MASK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_FRAME_SECOND_OUTPUT_INT_MASK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_MASK_0_FRAME_SECOND_OUTPUT_INT_MASK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_FRAME_SECOND_OUTPUT_INT_MASK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_FRAME_SECOND_OUTPUT_INT_MASK_DISABLED                       _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_MASK_0_FRAME_SECOND_OUTPUT_INT_MASK_ENABLED                        _MK_ENUM_CONST(1)
+
+// VI to EPP Error Interrupt Mask  This bit controls interrupt when the
+//  VI drops data to the EPP because the
+//  EPP is stalling the vi2epp bus and
+//  data is coming from the pins
+//   0= Disabled
+//   1= Enabled
+#define VI_INTERRUPT_MASK_0_EPP_ERROR_INT_MASK_SHIFT                    _MK_SHIFT_CONST(15)
+#define VI_INTERRUPT_MASK_0_EPP_ERROR_INT_MASK_FIELD                    (_MK_MASK_CONST(0x1) << VI_INTERRUPT_MASK_0_EPP_ERROR_INT_MASK_SHIFT)
+#define VI_INTERRUPT_MASK_0_EPP_ERROR_INT_MASK_RANGE                    15:15
+#define VI_INTERRUPT_MASK_0_EPP_ERROR_INT_MASK_WOFFSET                  0x0
+#define VI_INTERRUPT_MASK_0_EPP_ERROR_INT_MASK_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_EPP_ERROR_INT_MASK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_MASK_0_EPP_ERROR_INT_MASK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_EPP_ERROR_INT_MASK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_EPP_ERROR_INT_MASK_DISABLED                 _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_MASK_0_EPP_ERROR_INT_MASK_ENABLED                  _MK_ENUM_CONST(1)
+
+// YUV420PA Error Interrupt Mask  This bit controls interrupt when the
+//  VI does not average data because the
+//  line buffer data is not ready from the
+//  memory controller.  The VI will write
+//  unaveraged data and will write the U,V
+//  data from the even line in such cases.
+//   0= Disabled
+//   1= Enabled
+#define VI_INTERRUPT_MASK_0_YUV420PA_ERROR_INT_MASK_SHIFT                       _MK_SHIFT_CONST(16)
+#define VI_INTERRUPT_MASK_0_YUV420PA_ERROR_INT_MASK_FIELD                       (_MK_MASK_CONST(0x1) << VI_INTERRUPT_MASK_0_YUV420PA_ERROR_INT_MASK_SHIFT)
+#define VI_INTERRUPT_MASK_0_YUV420PA_ERROR_INT_MASK_RANGE                       16:16
+#define VI_INTERRUPT_MASK_0_YUV420PA_ERROR_INT_MASK_WOFFSET                     0x0
+#define VI_INTERRUPT_MASK_0_YUV420PA_ERROR_INT_MASK_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_YUV420PA_ERROR_INT_MASK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_MASK_0_YUV420PA_ERROR_INT_MASK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_YUV420PA_ERROR_INT_MASK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_YUV420PA_ERROR_INT_MASK_DISABLED                    _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_MASK_0_YUV420PA_ERROR_INT_MASK_ENABLED                     _MK_ENUM_CONST(1)
+
+// VI to Peer stall - First Memory Output  This bit controls interrupt when the
+//  VI drops peer bus packet(s) because the
+//  peer is stalling the first output peer
+//  bus and data is coming from the pins
+//   0= Disabled
+//   1= Enabled
+#define VI_INTERRUPT_MASK_0_FIRST_OUTPUT_PEER_STALL_INT_MASK_SHIFT                      _MK_SHIFT_CONST(17)
+#define VI_INTERRUPT_MASK_0_FIRST_OUTPUT_PEER_STALL_INT_MASK_FIELD                      (_MK_MASK_CONST(0x1) << VI_INTERRUPT_MASK_0_FIRST_OUTPUT_PEER_STALL_INT_MASK_SHIFT)
+#define VI_INTERRUPT_MASK_0_FIRST_OUTPUT_PEER_STALL_INT_MASK_RANGE                      17:17
+#define VI_INTERRUPT_MASK_0_FIRST_OUTPUT_PEER_STALL_INT_MASK_WOFFSET                    0x0
+#define VI_INTERRUPT_MASK_0_FIRST_OUTPUT_PEER_STALL_INT_MASK_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_FIRST_OUTPUT_PEER_STALL_INT_MASK_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_MASK_0_FIRST_OUTPUT_PEER_STALL_INT_MASK_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_FIRST_OUTPUT_PEER_STALL_INT_MASK_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_FIRST_OUTPUT_PEER_STALL_INT_MASK_DISABLED                   _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_MASK_0_FIRST_OUTPUT_PEER_STALL_INT_MASK_ENABLED                    _MK_ENUM_CONST(1)
+
+// VI to Peer stall - Second Memory Output  This bit controls interrupt when the
+//  VI drops peer bus packet(s) because the
+//  peer is stalling the second output peer
+//  bus and data is coming from the pins
+//   0= Disabled
+//   1= Enabled
+#define VI_INTERRUPT_MASK_0_SECOND_OUTPUT_PEER_STALL_INT_MASK_SHIFT                     _MK_SHIFT_CONST(18)
+#define VI_INTERRUPT_MASK_0_SECOND_OUTPUT_PEER_STALL_INT_MASK_FIELD                     (_MK_MASK_CONST(0x1) << VI_INTERRUPT_MASK_0_SECOND_OUTPUT_PEER_STALL_INT_MASK_SHIFT)
+#define VI_INTERRUPT_MASK_0_SECOND_OUTPUT_PEER_STALL_INT_MASK_RANGE                     18:18
+#define VI_INTERRUPT_MASK_0_SECOND_OUTPUT_PEER_STALL_INT_MASK_WOFFSET                   0x0
+#define VI_INTERRUPT_MASK_0_SECOND_OUTPUT_PEER_STALL_INT_MASK_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_SECOND_OUTPUT_PEER_STALL_INT_MASK_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_MASK_0_SECOND_OUTPUT_PEER_STALL_INT_MASK_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_SECOND_OUTPUT_PEER_STALL_INT_MASK_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_SECOND_OUTPUT_PEER_STALL_INT_MASK_DISABLED                  _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_MASK_0_SECOND_OUTPUT_PEER_STALL_INT_MASK_ENABLED                   _MK_ENUM_CONST(1)
+
+// Write Buffer DMA to VI Stalls VI and causes an error  This bit controls interrupt when the
+//  VI drops raw 8-bit stream data because
+//  the Write Buffer DMA is stalling.
+//   0= Disabled
+//   1= Enabled
+#define VI_INTERRUPT_MASK_0_DMA_STALL_INT_MASK_SHIFT                    _MK_SHIFT_CONST(19)
+#define VI_INTERRUPT_MASK_0_DMA_STALL_INT_MASK_FIELD                    (_MK_MASK_CONST(0x1) << VI_INTERRUPT_MASK_0_DMA_STALL_INT_MASK_SHIFT)
+#define VI_INTERRUPT_MASK_0_DMA_STALL_INT_MASK_RANGE                    19:19
+#define VI_INTERRUPT_MASK_0_DMA_STALL_INT_MASK_WOFFSET                  0x0
+#define VI_INTERRUPT_MASK_0_DMA_STALL_INT_MASK_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_DMA_STALL_INT_MASK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_MASK_0_DMA_STALL_INT_MASK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_DMA_STALL_INT_MASK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_DMA_STALL_INT_MASK_DISABLED                 _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_MASK_0_DMA_STALL_INT_MASK_ENABLED                  _MK_ENUM_CONST(1)
+
+// Stream 1 raise  This bit controls interrupt when the
+//  the Stream 1 Raise is enabled and
+//  returned
+//   0= Disabled
+//   1= Enabled
+#define VI_INTERRUPT_MASK_0_RAISE_STREAM_1_INT_MASK_SHIFT                       _MK_SHIFT_CONST(21)
+#define VI_INTERRUPT_MASK_0_RAISE_STREAM_1_INT_MASK_FIELD                       (_MK_MASK_CONST(0x1) << VI_INTERRUPT_MASK_0_RAISE_STREAM_1_INT_MASK_SHIFT)
+#define VI_INTERRUPT_MASK_0_RAISE_STREAM_1_INT_MASK_RANGE                       21:21
+#define VI_INTERRUPT_MASK_0_RAISE_STREAM_1_INT_MASK_WOFFSET                     0x0
+#define VI_INTERRUPT_MASK_0_RAISE_STREAM_1_INT_MASK_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_RAISE_STREAM_1_INT_MASK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_MASK_0_RAISE_STREAM_1_INT_MASK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_RAISE_STREAM_1_INT_MASK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_RAISE_STREAM_1_INT_MASK_DISABLED                    _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_MASK_0_RAISE_STREAM_1_INT_MASK_ENABLED                     _MK_ENUM_CONST(1)
+
+// Stream 2 raise  This bit controls interrupt when the
+//  the Stream 2 Raise is enabled and
+//  returned
+//   0= Disabled
+//   1= Enabled
+#define VI_INTERRUPT_MASK_0_RAISE_STREAM_2_INT_MASK_SHIFT                       _MK_SHIFT_CONST(22)
+#define VI_INTERRUPT_MASK_0_RAISE_STREAM_2_INT_MASK_FIELD                       (_MK_MASK_CONST(0x1) << VI_INTERRUPT_MASK_0_RAISE_STREAM_2_INT_MASK_SHIFT)
+#define VI_INTERRUPT_MASK_0_RAISE_STREAM_2_INT_MASK_RANGE                       22:22
+#define VI_INTERRUPT_MASK_0_RAISE_STREAM_2_INT_MASK_WOFFSET                     0x0
+#define VI_INTERRUPT_MASK_0_RAISE_STREAM_2_INT_MASK_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_RAISE_STREAM_2_INT_MASK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_MASK_0_RAISE_STREAM_2_INT_MASK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_RAISE_STREAM_2_INT_MASK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_RAISE_STREAM_2_INT_MASK_DISABLED                    _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_MASK_0_RAISE_STREAM_2_INT_MASK_ENABLED                     _MK_ENUM_CONST(1)
+
+// This bit controls interrupt when the
+//  ISDB-T vi input gets an upstream error.
+//   0= Disabled
+//   1= Enabled
+#define VI_INTERRUPT_MASK_0_TS_UPSTREAM_ERROR_INT_MASK_SHIFT                    _MK_SHIFT_CONST(23)
+#define VI_INTERRUPT_MASK_0_TS_UPSTREAM_ERROR_INT_MASK_FIELD                    (_MK_MASK_CONST(0x1) << VI_INTERRUPT_MASK_0_TS_UPSTREAM_ERROR_INT_MASK_SHIFT)
+#define VI_INTERRUPT_MASK_0_TS_UPSTREAM_ERROR_INT_MASK_RANGE                    23:23
+#define VI_INTERRUPT_MASK_0_TS_UPSTREAM_ERROR_INT_MASK_WOFFSET                  0x0
+#define VI_INTERRUPT_MASK_0_TS_UPSTREAM_ERROR_INT_MASK_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_TS_UPSTREAM_ERROR_INT_MASK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_MASK_0_TS_UPSTREAM_ERROR_INT_MASK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_TS_UPSTREAM_ERROR_INT_MASK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_TS_UPSTREAM_ERROR_INT_MASK_DISABLED                 _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_MASK_0_TS_UPSTREAM_ERROR_INT_MASK_ENABLED                  _MK_ENUM_CONST(1)
+
+// This bit controls interrupt when the
+//  ISDB-T input get an underrun error
+//   0= Disabled
+//   1= Enabled
+#define VI_INTERRUPT_MASK_0_TS_UNDERRUN_ERROR_INT_MASK_SHIFT                    _MK_SHIFT_CONST(24)
+#define VI_INTERRUPT_MASK_0_TS_UNDERRUN_ERROR_INT_MASK_FIELD                    (_MK_MASK_CONST(0x1) << VI_INTERRUPT_MASK_0_TS_UNDERRUN_ERROR_INT_MASK_SHIFT)
+#define VI_INTERRUPT_MASK_0_TS_UNDERRUN_ERROR_INT_MASK_RANGE                    24:24
+#define VI_INTERRUPT_MASK_0_TS_UNDERRUN_ERROR_INT_MASK_WOFFSET                  0x0
+#define VI_INTERRUPT_MASK_0_TS_UNDERRUN_ERROR_INT_MASK_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_TS_UNDERRUN_ERROR_INT_MASK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_MASK_0_TS_UNDERRUN_ERROR_INT_MASK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_TS_UNDERRUN_ERROR_INT_MASK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_TS_UNDERRUN_ERROR_INT_MASK_DISABLED                 _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_MASK_0_TS_UNDERRUN_ERROR_INT_MASK_ENABLED                  _MK_ENUM_CONST(1)
+
+// This bit controls interrupt when the
+//  ISDB-T input get an overrun error
+//   0= Disabled
+//   1= Enabled
+#define VI_INTERRUPT_MASK_0_TS_OVERRUN_ERROR_INT_MASK_SHIFT                     _MK_SHIFT_CONST(25)
+#define VI_INTERRUPT_MASK_0_TS_OVERRUN_ERROR_INT_MASK_FIELD                     (_MK_MASK_CONST(0x1) << VI_INTERRUPT_MASK_0_TS_OVERRUN_ERROR_INT_MASK_SHIFT)
+#define VI_INTERRUPT_MASK_0_TS_OVERRUN_ERROR_INT_MASK_RANGE                     25:25
+#define VI_INTERRUPT_MASK_0_TS_OVERRUN_ERROR_INT_MASK_WOFFSET                   0x0
+#define VI_INTERRUPT_MASK_0_TS_OVERRUN_ERROR_INT_MASK_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_TS_OVERRUN_ERROR_INT_MASK_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_MASK_0_TS_OVERRUN_ERROR_INT_MASK_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_TS_OVERRUN_ERROR_INT_MASK_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_TS_OVERRUN_ERROR_INT_MASK_DISABLED                  _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_MASK_0_TS_OVERRUN_ERROR_INT_MASK_ENABLED                   _MK_ENUM_CONST(1)
+
+// This bit controls interrupt when the
+//  ISDB-T input get a packet which means
+//  FEC+BODY in totalsize but FEC and BODY
+//  do not match FEC_SIZE and BODY_SIZE
+//   0= Disabled
+//   1= Enabled
+#define VI_INTERRUPT_MASK_0_TS_OTHER_PROTOCOL_ERROR_INT_MASK_SHIFT                      _MK_SHIFT_CONST(26)
+#define VI_INTERRUPT_MASK_0_TS_OTHER_PROTOCOL_ERROR_INT_MASK_FIELD                      (_MK_MASK_CONST(0x1) << VI_INTERRUPT_MASK_0_TS_OTHER_PROTOCOL_ERROR_INT_MASK_SHIFT)
+#define VI_INTERRUPT_MASK_0_TS_OTHER_PROTOCOL_ERROR_INT_MASK_RANGE                      26:26
+#define VI_INTERRUPT_MASK_0_TS_OTHER_PROTOCOL_ERROR_INT_MASK_WOFFSET                    0x0
+#define VI_INTERRUPT_MASK_0_TS_OTHER_PROTOCOL_ERROR_INT_MASK_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_TS_OTHER_PROTOCOL_ERROR_INT_MASK_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_MASK_0_TS_OTHER_PROTOCOL_ERROR_INT_MASK_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_TS_OTHER_PROTOCOL_ERROR_INT_MASK_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_TS_OTHER_PROTOCOL_ERROR_INT_MASK_DISABLED                   _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_MASK_0_TS_OTHER_PROTOCOL_ERROR_INT_MASK_ENABLED                    _MK_ENUM_CONST(1)
+
+// This bit controls interrupt when VI drops
+// data to MC.
+#define VI_INTERRUPT_MASK_0_FIRST_OUTPUT_DROP_MC_DATA_INT_MASK_SHIFT                    _MK_SHIFT_CONST(27)
+#define VI_INTERRUPT_MASK_0_FIRST_OUTPUT_DROP_MC_DATA_INT_MASK_FIELD                    (_MK_MASK_CONST(0x1) << VI_INTERRUPT_MASK_0_FIRST_OUTPUT_DROP_MC_DATA_INT_MASK_SHIFT)
+#define VI_INTERRUPT_MASK_0_FIRST_OUTPUT_DROP_MC_DATA_INT_MASK_RANGE                    27:27
+#define VI_INTERRUPT_MASK_0_FIRST_OUTPUT_DROP_MC_DATA_INT_MASK_WOFFSET                  0x0
+#define VI_INTERRUPT_MASK_0_FIRST_OUTPUT_DROP_MC_DATA_INT_MASK_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_FIRST_OUTPUT_DROP_MC_DATA_INT_MASK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_MASK_0_FIRST_OUTPUT_DROP_MC_DATA_INT_MASK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_FIRST_OUTPUT_DROP_MC_DATA_INT_MASK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_FIRST_OUTPUT_DROP_MC_DATA_INT_MASK_DISABLED                 _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_MASK_0_FIRST_OUTPUT_DROP_MC_DATA_INT_MASK_ENABLED                  _MK_ENUM_CONST(1)
+
+// This bit controls interrupt when VI drops
+// data to MC.
+#define VI_INTERRUPT_MASK_0_SECOND_OUTPUT_DROP_MC_DATA_INT_MASK_SHIFT                   _MK_SHIFT_CONST(28)
+#define VI_INTERRUPT_MASK_0_SECOND_OUTPUT_DROP_MC_DATA_INT_MASK_FIELD                   (_MK_MASK_CONST(0x1) << VI_INTERRUPT_MASK_0_SECOND_OUTPUT_DROP_MC_DATA_INT_MASK_SHIFT)
+#define VI_INTERRUPT_MASK_0_SECOND_OUTPUT_DROP_MC_DATA_INT_MASK_RANGE                   28:28
+#define VI_INTERRUPT_MASK_0_SECOND_OUTPUT_DROP_MC_DATA_INT_MASK_WOFFSET                 0x0
+#define VI_INTERRUPT_MASK_0_SECOND_OUTPUT_DROP_MC_DATA_INT_MASK_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_SECOND_OUTPUT_DROP_MC_DATA_INT_MASK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_MASK_0_SECOND_OUTPUT_DROP_MC_DATA_INT_MASK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_SECOND_OUTPUT_DROP_MC_DATA_INT_MASK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_SECOND_OUTPUT_DROP_MC_DATA_INT_MASK_DISABLED                        _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_MASK_0_SECOND_OUTPUT_DROP_MC_DATA_INT_MASK_ENABLED                 _MK_ENUM_CONST(1)
+
+
+// Register VI_INTERRUPT_TYPE_SELECT_0  // Interrupt Type Select
+#define VI_INTERRUPT_TYPE_SELECT_0                      _MK_ADDR_CONST(0x4e)
+#define VI_INTERRUPT_TYPE_SELECT_0_WORD_COUNT                   0x1
+#define VI_INTERRUPT_TYPE_SELECT_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_TYPE_SELECT_0_RESET_MASK                   _MK_MASK_CONST(0x1ff)
+#define VI_INTERRUPT_TYPE_SELECT_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_TYPE_SELECT_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_TYPE_SELECT_0_READ_MASK                    _MK_MASK_CONST(0x1ff)
+#define VI_INTERRUPT_TYPE_SELECT_0_WRITE_MASK                   _MK_MASK_CONST(0x1ff)
+// VD8 pin Interrupt Type  This bit controls interrupt VD8
+//  if edge or level type
+//   0= Edge type
+//   1= Level type
+#define VI_INTERRUPT_TYPE_SELECT_0_VD8_INT_TYPE_SHIFT                   _MK_SHIFT_CONST(0)
+#define VI_INTERRUPT_TYPE_SELECT_0_VD8_INT_TYPE_FIELD                   (_MK_MASK_CONST(0x1) << VI_INTERRUPT_TYPE_SELECT_0_VD8_INT_TYPE_SHIFT)
+#define VI_INTERRUPT_TYPE_SELECT_0_VD8_INT_TYPE_RANGE                   0:0
+#define VI_INTERRUPT_TYPE_SELECT_0_VD8_INT_TYPE_WOFFSET                 0x0
+#define VI_INTERRUPT_TYPE_SELECT_0_VD8_INT_TYPE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_TYPE_SELECT_0_VD8_INT_TYPE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_TYPE_SELECT_0_VD8_INT_TYPE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_TYPE_SELECT_0_VD8_INT_TYPE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_TYPE_SELECT_0_VD8_INT_TYPE_EDGE                    _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_TYPE_SELECT_0_VD8_INT_TYPE_LEVEL                   _MK_ENUM_CONST(1)
+
+// VD9 pin Interrupt Type  This bit controls interrupt VD9
+//   0= Edge type
+//   1= Level type
+#define VI_INTERRUPT_TYPE_SELECT_0_VD9_INT_TYPE_SHIFT                   _MK_SHIFT_CONST(1)
+#define VI_INTERRUPT_TYPE_SELECT_0_VD9_INT_TYPE_FIELD                   (_MK_MASK_CONST(0x1) << VI_INTERRUPT_TYPE_SELECT_0_VD9_INT_TYPE_SHIFT)
+#define VI_INTERRUPT_TYPE_SELECT_0_VD9_INT_TYPE_RANGE                   1:1
+#define VI_INTERRUPT_TYPE_SELECT_0_VD9_INT_TYPE_WOFFSET                 0x0
+#define VI_INTERRUPT_TYPE_SELECT_0_VD9_INT_TYPE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_TYPE_SELECT_0_VD9_INT_TYPE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_TYPE_SELECT_0_VD9_INT_TYPE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_TYPE_SELECT_0_VD9_INT_TYPE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_TYPE_SELECT_0_VD9_INT_TYPE_EDGE                    _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_TYPE_SELECT_0_VD9_INT_TYPE_LEVEL                   _MK_ENUM_CONST(1)
+
+// VD10 pin Interrupt Type  This bit controls interrupt VD10
+//   0= Edge type
+//   1= Level type
+#define VI_INTERRUPT_TYPE_SELECT_0_VD10_INT_TYPE_SHIFT                  _MK_SHIFT_CONST(2)
+#define VI_INTERRUPT_TYPE_SELECT_0_VD10_INT_TYPE_FIELD                  (_MK_MASK_CONST(0x1) << VI_INTERRUPT_TYPE_SELECT_0_VD10_INT_TYPE_SHIFT)
+#define VI_INTERRUPT_TYPE_SELECT_0_VD10_INT_TYPE_RANGE                  2:2
+#define VI_INTERRUPT_TYPE_SELECT_0_VD10_INT_TYPE_WOFFSET                        0x0
+#define VI_INTERRUPT_TYPE_SELECT_0_VD10_INT_TYPE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_TYPE_SELECT_0_VD10_INT_TYPE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_TYPE_SELECT_0_VD10_INT_TYPE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_TYPE_SELECT_0_VD10_INT_TYPE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_TYPE_SELECT_0_VD10_INT_TYPE_EDGE                   _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_TYPE_SELECT_0_VD10_INT_TYPE_LEVEL                  _MK_ENUM_CONST(1)
+
+// VD11 pin Interrupt Type  This bit controls interrupt VD11
+//   0= Edge type
+//   1= Level type
+#define VI_INTERRUPT_TYPE_SELECT_0_VD11_INT_TYPE_SHIFT                  _MK_SHIFT_CONST(3)
+#define VI_INTERRUPT_TYPE_SELECT_0_VD11_INT_TYPE_FIELD                  (_MK_MASK_CONST(0x1) << VI_INTERRUPT_TYPE_SELECT_0_VD11_INT_TYPE_SHIFT)
+#define VI_INTERRUPT_TYPE_SELECT_0_VD11_INT_TYPE_RANGE                  3:3
+#define VI_INTERRUPT_TYPE_SELECT_0_VD11_INT_TYPE_WOFFSET                        0x0
+#define VI_INTERRUPT_TYPE_SELECT_0_VD11_INT_TYPE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_TYPE_SELECT_0_VD11_INT_TYPE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_TYPE_SELECT_0_VD11_INT_TYPE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_TYPE_SELECT_0_VD11_INT_TYPE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_TYPE_SELECT_0_VD11_INT_TYPE_EDGE                   _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_TYPE_SELECT_0_VD11_INT_TYPE_LEVEL                  _MK_ENUM_CONST(1)
+
+// VGP4 pin Interrupt Type  This bit controls interrupt VGP4
+//   0= Edge type
+//   1= Level type
+#define VI_INTERRUPT_TYPE_SELECT_0_VGP4_INT_TYPE_SHIFT                  _MK_SHIFT_CONST(4)
+#define VI_INTERRUPT_TYPE_SELECT_0_VGP4_INT_TYPE_FIELD                  (_MK_MASK_CONST(0x1) << VI_INTERRUPT_TYPE_SELECT_0_VGP4_INT_TYPE_SHIFT)
+#define VI_INTERRUPT_TYPE_SELECT_0_VGP4_INT_TYPE_RANGE                  4:4
+#define VI_INTERRUPT_TYPE_SELECT_0_VGP4_INT_TYPE_WOFFSET                        0x0
+#define VI_INTERRUPT_TYPE_SELECT_0_VGP4_INT_TYPE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_TYPE_SELECT_0_VGP4_INT_TYPE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_TYPE_SELECT_0_VGP4_INT_TYPE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_TYPE_SELECT_0_VGP4_INT_TYPE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_TYPE_SELECT_0_VGP4_INT_TYPE_EDGE                   _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_TYPE_SELECT_0_VGP4_INT_TYPE_LEVEL                  _MK_ENUM_CONST(1)
+
+// VGP5 pin Interrupt Type  This bit controls interrupt VGP5
+//   0= Edge type
+//   1= Level type
+#define VI_INTERRUPT_TYPE_SELECT_0_VGP5_INT_TYPE_SHIFT                  _MK_SHIFT_CONST(5)
+#define VI_INTERRUPT_TYPE_SELECT_0_VGP5_INT_TYPE_FIELD                  (_MK_MASK_CONST(0x1) << VI_INTERRUPT_TYPE_SELECT_0_VGP5_INT_TYPE_SHIFT)
+#define VI_INTERRUPT_TYPE_SELECT_0_VGP5_INT_TYPE_RANGE                  5:5
+#define VI_INTERRUPT_TYPE_SELECT_0_VGP5_INT_TYPE_WOFFSET                        0x0
+#define VI_INTERRUPT_TYPE_SELECT_0_VGP5_INT_TYPE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_TYPE_SELECT_0_VGP5_INT_TYPE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_TYPE_SELECT_0_VGP5_INT_TYPE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_TYPE_SELECT_0_VGP5_INT_TYPE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_TYPE_SELECT_0_VGP5_INT_TYPE_EDGE                   _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_TYPE_SELECT_0_VGP5_INT_TYPE_LEVEL                  _MK_ENUM_CONST(1)
+
+// VGP6 pin Interrupt Type  This bit controls interrupt VGP6
+//   0= Edge type
+//   1= Level type
+#define VI_INTERRUPT_TYPE_SELECT_0_VGP6_INT_TYPE_SHIFT                  _MK_SHIFT_CONST(6)
+#define VI_INTERRUPT_TYPE_SELECT_0_VGP6_INT_TYPE_FIELD                  (_MK_MASK_CONST(0x1) << VI_INTERRUPT_TYPE_SELECT_0_VGP6_INT_TYPE_SHIFT)
+#define VI_INTERRUPT_TYPE_SELECT_0_VGP6_INT_TYPE_RANGE                  6:6
+#define VI_INTERRUPT_TYPE_SELECT_0_VGP6_INT_TYPE_WOFFSET                        0x0
+#define VI_INTERRUPT_TYPE_SELECT_0_VGP6_INT_TYPE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_TYPE_SELECT_0_VGP6_INT_TYPE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_TYPE_SELECT_0_VGP6_INT_TYPE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_TYPE_SELECT_0_VGP6_INT_TYPE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_TYPE_SELECT_0_VGP6_INT_TYPE_EDGE                   _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_TYPE_SELECT_0_VGP6_INT_TYPE_LEVEL                  _MK_ENUM_CONST(1)
+
+// VHS pin Interrupt Type  This bit controls interrupt VHS
+//   0= Edge type
+//   1= Level type
+#define VI_INTERRUPT_TYPE_SELECT_0_VHS_INT_TYPE_SHIFT                   _MK_SHIFT_CONST(7)
+#define VI_INTERRUPT_TYPE_SELECT_0_VHS_INT_TYPE_FIELD                   (_MK_MASK_CONST(0x1) << VI_INTERRUPT_TYPE_SELECT_0_VHS_INT_TYPE_SHIFT)
+#define VI_INTERRUPT_TYPE_SELECT_0_VHS_INT_TYPE_RANGE                   7:7
+#define VI_INTERRUPT_TYPE_SELECT_0_VHS_INT_TYPE_WOFFSET                 0x0
+#define VI_INTERRUPT_TYPE_SELECT_0_VHS_INT_TYPE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_TYPE_SELECT_0_VHS_INT_TYPE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_TYPE_SELECT_0_VHS_INT_TYPE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_TYPE_SELECT_0_VHS_INT_TYPE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_TYPE_SELECT_0_VHS_INT_TYPE_EDGE                    _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_TYPE_SELECT_0_VHS_INT_TYPE_LEVEL                   _MK_ENUM_CONST(1)
+
+// VVS pin Interrupt Type  This bit controls interrupt VVS
+//   0= Edge type
+//   1= Level type
+#define VI_INTERRUPT_TYPE_SELECT_0_VVS_INT_TYPE_SHIFT                   _MK_SHIFT_CONST(8)
+#define VI_INTERRUPT_TYPE_SELECT_0_VVS_INT_TYPE_FIELD                   (_MK_MASK_CONST(0x1) << VI_INTERRUPT_TYPE_SELECT_0_VVS_INT_TYPE_SHIFT)
+#define VI_INTERRUPT_TYPE_SELECT_0_VVS_INT_TYPE_RANGE                   8:8
+#define VI_INTERRUPT_TYPE_SELECT_0_VVS_INT_TYPE_WOFFSET                 0x0
+#define VI_INTERRUPT_TYPE_SELECT_0_VVS_INT_TYPE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_TYPE_SELECT_0_VVS_INT_TYPE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_TYPE_SELECT_0_VVS_INT_TYPE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_TYPE_SELECT_0_VVS_INT_TYPE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_TYPE_SELECT_0_VVS_INT_TYPE_EDGE                    _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_TYPE_SELECT_0_VVS_INT_TYPE_LEVEL                   _MK_ENUM_CONST(1)
+
+
+// Register VI_INTERRUPT_POLARITY_SELECT_0  // Interrupt Polarity Select
+#define VI_INTERRUPT_POLARITY_SELECT_0                  _MK_ADDR_CONST(0x4f)
+#define VI_INTERRUPT_POLARITY_SELECT_0_WORD_COUNT                       0x1
+#define VI_INTERRUPT_POLARITY_SELECT_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_POLARITY_SELECT_0_RESET_MASK                       _MK_MASK_CONST(0x1ff)
+#define VI_INTERRUPT_POLARITY_SELECT_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_POLARITY_SELECT_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_POLARITY_SELECT_0_READ_MASK                        _MK_MASK_CONST(0x1ff)
+#define VI_INTERRUPT_POLARITY_SELECT_0_WRITE_MASK                       _MK_MASK_CONST(0x1ff)
+// VD8 pin Interrupt Type  This bit controls interrupt VD8
+//  if edge or level type
+//   0= falling edge or low level
+//   1= rising edge or high level
+#define VI_INTERRUPT_POLARITY_SELECT_0_VD8_INT_POLARITY_SHIFT                   _MK_SHIFT_CONST(0)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VD8_INT_POLARITY_FIELD                   (_MK_MASK_CONST(0x1) << VI_INTERRUPT_POLARITY_SELECT_0_VD8_INT_POLARITY_SHIFT)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VD8_INT_POLARITY_RANGE                   0:0
+#define VI_INTERRUPT_POLARITY_SELECT_0_VD8_INT_POLARITY_WOFFSET                 0x0
+#define VI_INTERRUPT_POLARITY_SELECT_0_VD8_INT_POLARITY_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VD8_INT_POLARITY_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VD8_INT_POLARITY_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VD8_INT_POLARITY_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VD8_INT_POLARITY_LOW                     _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VD8_INT_POLARITY_HIGH                    _MK_ENUM_CONST(1)
+
+// VD9 pin Interrupt Type  This bit controls interrupt VD9
+//   0= falling edge or low level
+//   1= rising edge or high level
+#define VI_INTERRUPT_POLARITY_SELECT_0_VD9_INT_POLARITY_SHIFT                   _MK_SHIFT_CONST(1)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VD9_INT_POLARITY_FIELD                   (_MK_MASK_CONST(0x1) << VI_INTERRUPT_POLARITY_SELECT_0_VD9_INT_POLARITY_SHIFT)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VD9_INT_POLARITY_RANGE                   1:1
+#define VI_INTERRUPT_POLARITY_SELECT_0_VD9_INT_POLARITY_WOFFSET                 0x0
+#define VI_INTERRUPT_POLARITY_SELECT_0_VD9_INT_POLARITY_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VD9_INT_POLARITY_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VD9_INT_POLARITY_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VD9_INT_POLARITY_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VD9_INT_POLARITY_LOW                     _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VD9_INT_POLARITY_HIGH                    _MK_ENUM_CONST(1)
+
+// VD10 pin Interrupt Type  This bit controls interrupt VD10
+//   0= falling edge or low level
+//   1= rising edge or high level
+#define VI_INTERRUPT_POLARITY_SELECT_0_VD10_INT_POLARITY_SHIFT                  _MK_SHIFT_CONST(2)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VD10_INT_POLARITY_FIELD                  (_MK_MASK_CONST(0x1) << VI_INTERRUPT_POLARITY_SELECT_0_VD10_INT_POLARITY_SHIFT)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VD10_INT_POLARITY_RANGE                  2:2
+#define VI_INTERRUPT_POLARITY_SELECT_0_VD10_INT_POLARITY_WOFFSET                        0x0
+#define VI_INTERRUPT_POLARITY_SELECT_0_VD10_INT_POLARITY_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VD10_INT_POLARITY_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VD10_INT_POLARITY_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VD10_INT_POLARITY_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VD10_INT_POLARITY_LOW                    _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VD10_INT_POLARITY_HIGH                   _MK_ENUM_CONST(1)
+
+// VD11 pin Interrupt Type  This bit controls interrupt VD11
+//   0= falling edge or low level
+//   1= rising edge or high level
+#define VI_INTERRUPT_POLARITY_SELECT_0_VD11_INT_POLARITY_SHIFT                  _MK_SHIFT_CONST(3)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VD11_INT_POLARITY_FIELD                  (_MK_MASK_CONST(0x1) << VI_INTERRUPT_POLARITY_SELECT_0_VD11_INT_POLARITY_SHIFT)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VD11_INT_POLARITY_RANGE                  3:3
+#define VI_INTERRUPT_POLARITY_SELECT_0_VD11_INT_POLARITY_WOFFSET                        0x0
+#define VI_INTERRUPT_POLARITY_SELECT_0_VD11_INT_POLARITY_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VD11_INT_POLARITY_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VD11_INT_POLARITY_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VD11_INT_POLARITY_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VD11_INT_POLARITY_LOW                    _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VD11_INT_POLARITY_HIGH                   _MK_ENUM_CONST(1)
+
+// VGP4 pin Interrupt Type  This bit controls interrupt VGP4
+//   0= falling edge or low level
+//   1= rising edge or high level
+#define VI_INTERRUPT_POLARITY_SELECT_0_VGP4_INT_POLARITY_SHIFT                  _MK_SHIFT_CONST(4)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VGP4_INT_POLARITY_FIELD                  (_MK_MASK_CONST(0x1) << VI_INTERRUPT_POLARITY_SELECT_0_VGP4_INT_POLARITY_SHIFT)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VGP4_INT_POLARITY_RANGE                  4:4
+#define VI_INTERRUPT_POLARITY_SELECT_0_VGP4_INT_POLARITY_WOFFSET                        0x0
+#define VI_INTERRUPT_POLARITY_SELECT_0_VGP4_INT_POLARITY_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VGP4_INT_POLARITY_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VGP4_INT_POLARITY_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VGP4_INT_POLARITY_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VGP4_INT_POLARITY_LOW                    _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VGP4_INT_POLARITY_HIGH                   _MK_ENUM_CONST(1)
+
+// VGP5 pin Interrupt Type  This bit controls interrupt VGP5
+//   0= falling edge or low level
+//   1= rising edge or high level
+#define VI_INTERRUPT_POLARITY_SELECT_0_VGP5_INT_POLARITY_SHIFT                  _MK_SHIFT_CONST(5)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VGP5_INT_POLARITY_FIELD                  (_MK_MASK_CONST(0x1) << VI_INTERRUPT_POLARITY_SELECT_0_VGP5_INT_POLARITY_SHIFT)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VGP5_INT_POLARITY_RANGE                  5:5
+#define VI_INTERRUPT_POLARITY_SELECT_0_VGP5_INT_POLARITY_WOFFSET                        0x0
+#define VI_INTERRUPT_POLARITY_SELECT_0_VGP5_INT_POLARITY_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VGP5_INT_POLARITY_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VGP5_INT_POLARITY_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VGP5_INT_POLARITY_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VGP5_INT_POLARITY_LOW                    _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VGP5_INT_POLARITY_HIGH                   _MK_ENUM_CONST(1)
+
+// VGP6 pin Interrupt Type  This bit controls interrupt VGP6
+//   0= falling edge or low level
+//   1= rising edge or high level
+#define VI_INTERRUPT_POLARITY_SELECT_0_VGP6_INT_POLARITY_SHIFT                  _MK_SHIFT_CONST(6)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VGP6_INT_POLARITY_FIELD                  (_MK_MASK_CONST(0x1) << VI_INTERRUPT_POLARITY_SELECT_0_VGP6_INT_POLARITY_SHIFT)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VGP6_INT_POLARITY_RANGE                  6:6
+#define VI_INTERRUPT_POLARITY_SELECT_0_VGP6_INT_POLARITY_WOFFSET                        0x0
+#define VI_INTERRUPT_POLARITY_SELECT_0_VGP6_INT_POLARITY_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VGP6_INT_POLARITY_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VGP6_INT_POLARITY_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VGP6_INT_POLARITY_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VGP6_INT_POLARITY_LOW                    _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VGP6_INT_POLARITY_HIGH                   _MK_ENUM_CONST(1)
+
+// VHS pin Interrupt Type  This bit controls interrupt VHS
+//   0= falling edge or low level
+//   1= rising edge or high level
+#define VI_INTERRUPT_POLARITY_SELECT_0_VHS_INT_POLARITY_SHIFT                   _MK_SHIFT_CONST(7)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VHS_INT_POLARITY_FIELD                   (_MK_MASK_CONST(0x1) << VI_INTERRUPT_POLARITY_SELECT_0_VHS_INT_POLARITY_SHIFT)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VHS_INT_POLARITY_RANGE                   7:7
+#define VI_INTERRUPT_POLARITY_SELECT_0_VHS_INT_POLARITY_WOFFSET                 0x0
+#define VI_INTERRUPT_POLARITY_SELECT_0_VHS_INT_POLARITY_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VHS_INT_POLARITY_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VHS_INT_POLARITY_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VHS_INT_POLARITY_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VHS_INT_POLARITY_LOW                     _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VHS_INT_POLARITY_HIGH                    _MK_ENUM_CONST(1)
+
+// VVS pin Interrupt Type  This bit controls interrupt VVS
+//   0= falling edge or low level
+//   1= rising edge or high level
+#define VI_INTERRUPT_POLARITY_SELECT_0_VVS_INT_POLARITY_SHIFT                   _MK_SHIFT_CONST(8)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VVS_INT_POLARITY_FIELD                   (_MK_MASK_CONST(0x1) << VI_INTERRUPT_POLARITY_SELECT_0_VVS_INT_POLARITY_SHIFT)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VVS_INT_POLARITY_RANGE                   8:8
+#define VI_INTERRUPT_POLARITY_SELECT_0_VVS_INT_POLARITY_WOFFSET                 0x0
+#define VI_INTERRUPT_POLARITY_SELECT_0_VVS_INT_POLARITY_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VVS_INT_POLARITY_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VVS_INT_POLARITY_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VVS_INT_POLARITY_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VVS_INT_POLARITY_LOW                     _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VVS_INT_POLARITY_HIGH                    _MK_ENUM_CONST(1)
+
+
+// Register VI_INTERRUPT_STATUS_0  // Interrupt Enable
+#define VI_INTERRUPT_STATUS_0                   _MK_ADDR_CONST(0x50)
+#define VI_INTERRUPT_STATUS_0_WORD_COUNT                        0x1
+#define VI_INTERRUPT_STATUS_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_READ_MASK                         _MK_MASK_CONST(0x1fffffff)
+#define VI_INTERRUPT_STATUS_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+// VD8 pin Interrupt Status  This bit controls interrupt when VD8
+//  rising/falling edge is detected.
+//   0= Interrupt not detected
+//   1= Interrupt detected
+#define VI_INTERRUPT_STATUS_0_VD8_INT_STATUS_SHIFT                      _MK_SHIFT_CONST(0)
+#define VI_INTERRUPT_STATUS_0_VD8_INT_STATUS_FIELD                      (_MK_MASK_CONST(0x1) << VI_INTERRUPT_STATUS_0_VD8_INT_STATUS_SHIFT)
+#define VI_INTERRUPT_STATUS_0_VD8_INT_STATUS_RANGE                      0:0
+#define VI_INTERRUPT_STATUS_0_VD8_INT_STATUS_WOFFSET                    0x0
+#define VI_INTERRUPT_STATUS_0_VD8_INT_STATUS_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_VD8_INT_STATUS_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_VD8_INT_STATUS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_VD8_INT_STATUS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_VD8_INT_STATUS_NOINTR                     _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_STATUS_0_VD8_INT_STATUS_INTR                       _MK_ENUM_CONST(1)
+
+// VD9 pin Interrupt Status  This bit controls interrupt when VD9
+//  rising/falling edge is detected.
+//   0= Interrupt not detected
+//   1= Interrupt detected
+#define VI_INTERRUPT_STATUS_0_VD9_INT_STATUS_SHIFT                      _MK_SHIFT_CONST(1)
+#define VI_INTERRUPT_STATUS_0_VD9_INT_STATUS_FIELD                      (_MK_MASK_CONST(0x1) << VI_INTERRUPT_STATUS_0_VD9_INT_STATUS_SHIFT)
+#define VI_INTERRUPT_STATUS_0_VD9_INT_STATUS_RANGE                      1:1
+#define VI_INTERRUPT_STATUS_0_VD9_INT_STATUS_WOFFSET                    0x0
+#define VI_INTERRUPT_STATUS_0_VD9_INT_STATUS_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_VD9_INT_STATUS_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_VD9_INT_STATUS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_VD9_INT_STATUS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_VD9_INT_STATUS_NOINTR                     _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_STATUS_0_VD9_INT_STATUS_INTR                       _MK_ENUM_CONST(1)
+
+// VD10 pin Interrupt Status  This bit controls interrupt when VD10
+//  rising/falling edge is detected.
+//   0= Interrupt not detected
+//   1= Interrupt detected
+#define VI_INTERRUPT_STATUS_0_VD10_INT_STATUS_SHIFT                     _MK_SHIFT_CONST(2)
+#define VI_INTERRUPT_STATUS_0_VD10_INT_STATUS_FIELD                     (_MK_MASK_CONST(0x1) << VI_INTERRUPT_STATUS_0_VD10_INT_STATUS_SHIFT)
+#define VI_INTERRUPT_STATUS_0_VD10_INT_STATUS_RANGE                     2:2
+#define VI_INTERRUPT_STATUS_0_VD10_INT_STATUS_WOFFSET                   0x0
+#define VI_INTERRUPT_STATUS_0_VD10_INT_STATUS_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_VD10_INT_STATUS_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_VD10_INT_STATUS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_VD10_INT_STATUS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_VD10_INT_STATUS_NOINTR                    _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_STATUS_0_VD10_INT_STATUS_INTR                      _MK_ENUM_CONST(1)
+
+// VD11 pin Interrupt Status  This bit controls interrupt when VD11
+//  rising/falling edge is detected.
+//   0= Interrupt not detected
+//   1= Interrupt detected
+#define VI_INTERRUPT_STATUS_0_VD11_INT_STATUS_SHIFT                     _MK_SHIFT_CONST(3)
+#define VI_INTERRUPT_STATUS_0_VD11_INT_STATUS_FIELD                     (_MK_MASK_CONST(0x1) << VI_INTERRUPT_STATUS_0_VD11_INT_STATUS_SHIFT)
+#define VI_INTERRUPT_STATUS_0_VD11_INT_STATUS_RANGE                     3:3
+#define VI_INTERRUPT_STATUS_0_VD11_INT_STATUS_WOFFSET                   0x0
+#define VI_INTERRUPT_STATUS_0_VD11_INT_STATUS_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_VD11_INT_STATUS_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_VD11_INT_STATUS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_VD11_INT_STATUS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_VD11_INT_STATUS_NOINTR                    _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_STATUS_0_VD11_INT_STATUS_INTR                      _MK_ENUM_CONST(1)
+
+// VGP4 pin Interrupt Status  This bit controls interrupt when VGP4
+//  rising/falling edge is detected.
+//   0= Interrupt not detected
+//   1= Interrupt detected
+#define VI_INTERRUPT_STATUS_0_VGP4_INT_STATUS_SHIFT                     _MK_SHIFT_CONST(4)
+#define VI_INTERRUPT_STATUS_0_VGP4_INT_STATUS_FIELD                     (_MK_MASK_CONST(0x1) << VI_INTERRUPT_STATUS_0_VGP4_INT_STATUS_SHIFT)
+#define VI_INTERRUPT_STATUS_0_VGP4_INT_STATUS_RANGE                     4:4
+#define VI_INTERRUPT_STATUS_0_VGP4_INT_STATUS_WOFFSET                   0x0
+#define VI_INTERRUPT_STATUS_0_VGP4_INT_STATUS_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_VGP4_INT_STATUS_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_VGP4_INT_STATUS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_VGP4_INT_STATUS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_VGP4_INT_STATUS_NOINTR                    _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_STATUS_0_VGP4_INT_STATUS_INTR                      _MK_ENUM_CONST(1)
+
+// VGP5 pin Interrupt Status  This bit controls interrupt when VGP5
+//  rising/falling edge is detected.
+//   0= Interrupt not detected
+//   1= Interrupt detected
+#define VI_INTERRUPT_STATUS_0_VGP5_INT_STATUS_SHIFT                     _MK_SHIFT_CONST(5)
+#define VI_INTERRUPT_STATUS_0_VGP5_INT_STATUS_FIELD                     (_MK_MASK_CONST(0x1) << VI_INTERRUPT_STATUS_0_VGP5_INT_STATUS_SHIFT)
+#define VI_INTERRUPT_STATUS_0_VGP5_INT_STATUS_RANGE                     5:5
+#define VI_INTERRUPT_STATUS_0_VGP5_INT_STATUS_WOFFSET                   0x0
+#define VI_INTERRUPT_STATUS_0_VGP5_INT_STATUS_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_VGP5_INT_STATUS_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_VGP5_INT_STATUS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_VGP5_INT_STATUS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_VGP5_INT_STATUS_NOINTR                    _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_STATUS_0_VGP5_INT_STATUS_INTR                      _MK_ENUM_CONST(1)
+
+// VGP6 pin Interrupt Status  This bit controls interrupt when VGP6
+//  rising/falling edge is detected.
+//   0= Interrupt not detected
+//   1= Interrupt detected
+#define VI_INTERRUPT_STATUS_0_VGP6_INT_STATUS_SHIFT                     _MK_SHIFT_CONST(6)
+#define VI_INTERRUPT_STATUS_0_VGP6_INT_STATUS_FIELD                     (_MK_MASK_CONST(0x1) << VI_INTERRUPT_STATUS_0_VGP6_INT_STATUS_SHIFT)
+#define VI_INTERRUPT_STATUS_0_VGP6_INT_STATUS_RANGE                     6:6
+#define VI_INTERRUPT_STATUS_0_VGP6_INT_STATUS_WOFFSET                   0x0
+#define VI_INTERRUPT_STATUS_0_VGP6_INT_STATUS_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_VGP6_INT_STATUS_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_VGP6_INT_STATUS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_VGP6_INT_STATUS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_VGP6_INT_STATUS_NOINTR                    _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_STATUS_0_VGP6_INT_STATUS_INTR                      _MK_ENUM_CONST(1)
+
+// VHS pin Interrupt Status  This bit controls interrupt when VHS
+//  rising/falling edge is detected.
+//   0= Interrupt not detected
+//   1= Interrupt detected
+#define VI_INTERRUPT_STATUS_0_VHS_INT_STATUS_SHIFT                      _MK_SHIFT_CONST(7)
+#define VI_INTERRUPT_STATUS_0_VHS_INT_STATUS_FIELD                      (_MK_MASK_CONST(0x1) << VI_INTERRUPT_STATUS_0_VHS_INT_STATUS_SHIFT)
+#define VI_INTERRUPT_STATUS_0_VHS_INT_STATUS_RANGE                      7:7
+#define VI_INTERRUPT_STATUS_0_VHS_INT_STATUS_WOFFSET                    0x0
+#define VI_INTERRUPT_STATUS_0_VHS_INT_STATUS_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_VHS_INT_STATUS_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_VHS_INT_STATUS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_VHS_INT_STATUS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_VHS_INT_STATUS_NOINTR                     _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_STATUS_0_VHS_INT_STATUS_INTR                       _MK_ENUM_CONST(1)
+
+// VVS pin Interrupt Status  This bit controls interrupt when VVS
+//  rising/falling edge is detected.
+//   0= Interrupt not detected
+//   1= Interrupt detected
+#define VI_INTERRUPT_STATUS_0_VVS_INT_STATUS_SHIFT                      _MK_SHIFT_CONST(8)
+#define VI_INTERRUPT_STATUS_0_VVS_INT_STATUS_FIELD                      (_MK_MASK_CONST(0x1) << VI_INTERRUPT_STATUS_0_VVS_INT_STATUS_SHIFT)
+#define VI_INTERRUPT_STATUS_0_VVS_INT_STATUS_RANGE                      8:8
+#define VI_INTERRUPT_STATUS_0_VVS_INT_STATUS_WOFFSET                    0x0
+#define VI_INTERRUPT_STATUS_0_VVS_INT_STATUS_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_VVS_INT_STATUS_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_VVS_INT_STATUS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_VVS_INT_STATUS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_VVS_INT_STATUS_NOINTR                     _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_STATUS_0_VVS_INT_STATUS_INTR                       _MK_ENUM_CONST(1)
+
+// Vertical Counter Interrupt Status  (effective when VIDEO_SOURCE is HOST)
+//  This bit controls interrupt when the
+//  vertical counter threshold is reached.
+#define VI_INTERRUPT_STATUS_0_V_COUNTER_INT_STATUS_SHIFT                        _MK_SHIFT_CONST(9)
+#define VI_INTERRUPT_STATUS_0_V_COUNTER_INT_STATUS_FIELD                        (_MK_MASK_CONST(0x1) << VI_INTERRUPT_STATUS_0_V_COUNTER_INT_STATUS_SHIFT)
+#define VI_INTERRUPT_STATUS_0_V_COUNTER_INT_STATUS_RANGE                        9:9
+#define VI_INTERRUPT_STATUS_0_V_COUNTER_INT_STATUS_WOFFSET                      0x0
+#define VI_INTERRUPT_STATUS_0_V_COUNTER_INT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_V_COUNTER_INT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_V_COUNTER_INT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_V_COUNTER_INT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_V_COUNTER_INT_STATUS_NOINTR                       _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_STATUS_0_V_COUNTER_INT_STATUS_INTR                 _MK_ENUM_CONST(1)
+
+// Y-FIFO Threshold Interrupt Enable  This bit controls interrupt when the number
+//  of filled locations in Y-FIFO is equal or
+//  greater than the Y_FIFO_THRESHOLD value.
+//   0= Interrupt not detected
+//   1= Interrupt detected
+#define VI_INTERRUPT_STATUS_0_Y_THRESHOLD_INT_STATUS_SHIFT                      _MK_SHIFT_CONST(10)
+#define VI_INTERRUPT_STATUS_0_Y_THRESHOLD_INT_STATUS_FIELD                      (_MK_MASK_CONST(0x1) << VI_INTERRUPT_STATUS_0_Y_THRESHOLD_INT_STATUS_SHIFT)
+#define VI_INTERRUPT_STATUS_0_Y_THRESHOLD_INT_STATUS_RANGE                      10:10
+#define VI_INTERRUPT_STATUS_0_Y_THRESHOLD_INT_STATUS_WOFFSET                    0x0
+#define VI_INTERRUPT_STATUS_0_Y_THRESHOLD_INT_STATUS_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_Y_THRESHOLD_INT_STATUS_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_Y_THRESHOLD_INT_STATUS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_Y_THRESHOLD_INT_STATUS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_Y_THRESHOLD_INT_STATUS_NOINTR                     _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_STATUS_0_Y_THRESHOLD_INT_STATUS_INTR                       _MK_ENUM_CONST(1)
+
+// Buffer Done First Output Interrupt Status  This bit is set when a buffer has been
+//  written to memory by the first output.
+//   0= Interrupt not detected
+//   1= Interrupt detected
+#define VI_INTERRUPT_STATUS_0_BUFFER_FIRST_OUTPUT_INT_STATUS_SHIFT                      _MK_SHIFT_CONST(11)
+#define VI_INTERRUPT_STATUS_0_BUFFER_FIRST_OUTPUT_INT_STATUS_FIELD                      (_MK_MASK_CONST(0x1) << VI_INTERRUPT_STATUS_0_BUFFER_FIRST_OUTPUT_INT_STATUS_SHIFT)
+#define VI_INTERRUPT_STATUS_0_BUFFER_FIRST_OUTPUT_INT_STATUS_RANGE                      11:11
+#define VI_INTERRUPT_STATUS_0_BUFFER_FIRST_OUTPUT_INT_STATUS_WOFFSET                    0x0
+#define VI_INTERRUPT_STATUS_0_BUFFER_FIRST_OUTPUT_INT_STATUS_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_BUFFER_FIRST_OUTPUT_INT_STATUS_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_BUFFER_FIRST_OUTPUT_INT_STATUS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_BUFFER_FIRST_OUTPUT_INT_STATUS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_BUFFER_FIRST_OUTPUT_INT_STATUS_NOINTR                     _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_STATUS_0_BUFFER_FIRST_OUTPUT_INT_STATUS_INTR                       _MK_ENUM_CONST(1)
+
+// Frame Done First Output Interrupt Status  This bit is set when a frame has been
+//  written to memory by the first output.
+//   0= Interrupt not detected
+//   1= Interrupt detected
+#define VI_INTERRUPT_STATUS_0_FRAME_FIRST_OUTPUT_INT_STATUS_SHIFT                       _MK_SHIFT_CONST(12)
+#define VI_INTERRUPT_STATUS_0_FRAME_FIRST_OUTPUT_INT_STATUS_FIELD                       (_MK_MASK_CONST(0x1) << VI_INTERRUPT_STATUS_0_FRAME_FIRST_OUTPUT_INT_STATUS_SHIFT)
+#define VI_INTERRUPT_STATUS_0_FRAME_FIRST_OUTPUT_INT_STATUS_RANGE                       12:12
+#define VI_INTERRUPT_STATUS_0_FRAME_FIRST_OUTPUT_INT_STATUS_WOFFSET                     0x0
+#define VI_INTERRUPT_STATUS_0_FRAME_FIRST_OUTPUT_INT_STATUS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_FRAME_FIRST_OUTPUT_INT_STATUS_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_FRAME_FIRST_OUTPUT_INT_STATUS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_FRAME_FIRST_OUTPUT_INT_STATUS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_FRAME_FIRST_OUTPUT_INT_STATUS_NOINTR                      _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_STATUS_0_FRAME_FIRST_OUTPUT_INT_STATUS_INTR                        _MK_ENUM_CONST(1)
+
+// Buffer Done Second Output Interrupt Status  This bit is set when a buffer has been
+//  written to memory by the second output.
+//   0= Interrupt not detected
+//   1= Interrupt detected
+#define VI_INTERRUPT_STATUS_0_BUFFER_SECOND_OUTPUT_INT_STATUS_SHIFT                     _MK_SHIFT_CONST(13)
+#define VI_INTERRUPT_STATUS_0_BUFFER_SECOND_OUTPUT_INT_STATUS_FIELD                     (_MK_MASK_CONST(0x1) << VI_INTERRUPT_STATUS_0_BUFFER_SECOND_OUTPUT_INT_STATUS_SHIFT)
+#define VI_INTERRUPT_STATUS_0_BUFFER_SECOND_OUTPUT_INT_STATUS_RANGE                     13:13
+#define VI_INTERRUPT_STATUS_0_BUFFER_SECOND_OUTPUT_INT_STATUS_WOFFSET                   0x0
+#define VI_INTERRUPT_STATUS_0_BUFFER_SECOND_OUTPUT_INT_STATUS_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_BUFFER_SECOND_OUTPUT_INT_STATUS_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_BUFFER_SECOND_OUTPUT_INT_STATUS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_BUFFER_SECOND_OUTPUT_INT_STATUS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_BUFFER_SECOND_OUTPUT_INT_STATUS_NOINTR                    _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_STATUS_0_BUFFER_SECOND_OUTPUT_INT_STATUS_INTR                      _MK_ENUM_CONST(1)
+
+// Frame Done Second Output Interrupt Status  This bit is set when a frame has been
+//  written to memory by the second output.
+//   0= Interrupt not detected
+//   1= Interrupt detected
+#define VI_INTERRUPT_STATUS_0_FRAME_SECOND_OUTPUT_INT_STATUS_SHIFT                      _MK_SHIFT_CONST(14)
+#define VI_INTERRUPT_STATUS_0_FRAME_SECOND_OUTPUT_INT_STATUS_FIELD                      (_MK_MASK_CONST(0x1) << VI_INTERRUPT_STATUS_0_FRAME_SECOND_OUTPUT_INT_STATUS_SHIFT)
+#define VI_INTERRUPT_STATUS_0_FRAME_SECOND_OUTPUT_INT_STATUS_RANGE                      14:14
+#define VI_INTERRUPT_STATUS_0_FRAME_SECOND_OUTPUT_INT_STATUS_WOFFSET                    0x0
+#define VI_INTERRUPT_STATUS_0_FRAME_SECOND_OUTPUT_INT_STATUS_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_FRAME_SECOND_OUTPUT_INT_STATUS_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_FRAME_SECOND_OUTPUT_INT_STATUS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_FRAME_SECOND_OUTPUT_INT_STATUS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_FRAME_SECOND_OUTPUT_INT_STATUS_NOINTR                     _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_STATUS_0_FRAME_SECOND_OUTPUT_INT_STATUS_INTR                       _MK_ENUM_CONST(1)
+
+// VI to EPP Error Interrupt Enable  This bit controls interrupt when the
+//  VI drops data to the EPP because the
+//  EPP is stalling the vi2epp bus and
+//  data is coming from the pins
+//   0= Interrupt not detected
+//   1= Interrupt detected
+#define VI_INTERRUPT_STATUS_0_EPP_ERROR_INT_STATUS_SHIFT                        _MK_SHIFT_CONST(15)
+#define VI_INTERRUPT_STATUS_0_EPP_ERROR_INT_STATUS_FIELD                        (_MK_MASK_CONST(0x1) << VI_INTERRUPT_STATUS_0_EPP_ERROR_INT_STATUS_SHIFT)
+#define VI_INTERRUPT_STATUS_0_EPP_ERROR_INT_STATUS_RANGE                        15:15
+#define VI_INTERRUPT_STATUS_0_EPP_ERROR_INT_STATUS_WOFFSET                      0x0
+#define VI_INTERRUPT_STATUS_0_EPP_ERROR_INT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_EPP_ERROR_INT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_EPP_ERROR_INT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_EPP_ERROR_INT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_EPP_ERROR_INT_STATUS_NOINTR                       _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_STATUS_0_EPP_ERROR_INT_STATUS_INTR                 _MK_ENUM_CONST(1)
+
+// YUV420PA Error Interrupt Enable This bit shows the status of if the
+//  VI does not average data because the
+//  line buffer data is not ready from the
+//  memory controller.  The VI will write
+//  unaveraged data and will write the U,V
+//  data from the even line in such cases.
+//   0= Interrupt not detected
+//   1= Interrupt detected
+#define VI_INTERRUPT_STATUS_0_YUV420PA_ERROR_INT_STATUS_SHIFT                   _MK_SHIFT_CONST(16)
+#define VI_INTERRUPT_STATUS_0_YUV420PA_ERROR_INT_STATUS_FIELD                   (_MK_MASK_CONST(0x1) << VI_INTERRUPT_STATUS_0_YUV420PA_ERROR_INT_STATUS_SHIFT)
+#define VI_INTERRUPT_STATUS_0_YUV420PA_ERROR_INT_STATUS_RANGE                   16:16
+#define VI_INTERRUPT_STATUS_0_YUV420PA_ERROR_INT_STATUS_WOFFSET                 0x0
+#define VI_INTERRUPT_STATUS_0_YUV420PA_ERROR_INT_STATUS_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_YUV420PA_ERROR_INT_STATUS_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_YUV420PA_ERROR_INT_STATUS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_YUV420PA_ERROR_INT_STATUS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_YUV420PA_ERROR_INT_STATUS_NOINTR                  _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_STATUS_0_YUV420PA_ERROR_INT_STATUS_INTR                    _MK_ENUM_CONST(1)
+
+// This bit shows the status of if the
+//  VI dropped a buffer packet to the
+//  peer communicating with the first memory
+//  output
+//   0= Interrupt not detected
+//   1= Interrupt detected
+#define VI_INTERRUPT_STATUS_0_FIRST_OUTPUT_PEER_STALL_INT_STATUS_SHIFT                  _MK_SHIFT_CONST(17)
+#define VI_INTERRUPT_STATUS_0_FIRST_OUTPUT_PEER_STALL_INT_STATUS_FIELD                  (_MK_MASK_CONST(0x1) << VI_INTERRUPT_STATUS_0_FIRST_OUTPUT_PEER_STALL_INT_STATUS_SHIFT)
+#define VI_INTERRUPT_STATUS_0_FIRST_OUTPUT_PEER_STALL_INT_STATUS_RANGE                  17:17
+#define VI_INTERRUPT_STATUS_0_FIRST_OUTPUT_PEER_STALL_INT_STATUS_WOFFSET                        0x0
+#define VI_INTERRUPT_STATUS_0_FIRST_OUTPUT_PEER_STALL_INT_STATUS_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_FIRST_OUTPUT_PEER_STALL_INT_STATUS_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_FIRST_OUTPUT_PEER_STALL_INT_STATUS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_FIRST_OUTPUT_PEER_STALL_INT_STATUS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_FIRST_OUTPUT_PEER_STALL_INT_STATUS_NOINTR                 _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_STATUS_0_FIRST_OUTPUT_PEER_STALL_INT_STATUS_INTR                   _MK_ENUM_CONST(1)
+
+// This bit shows the status of if the
+//  VI dropped a buffer packet to the
+//  peer communicating with the second memory
+//  output
+//   0= Interrupt not detected
+//   1= Interrupt detected
+#define VI_INTERRUPT_STATUS_0_SECOND_OUTPUT_PEER_STALL_INT_STATUS_SHIFT                 _MK_SHIFT_CONST(18)
+#define VI_INTERRUPT_STATUS_0_SECOND_OUTPUT_PEER_STALL_INT_STATUS_FIELD                 (_MK_MASK_CONST(0x1) << VI_INTERRUPT_STATUS_0_SECOND_OUTPUT_PEER_STALL_INT_STATUS_SHIFT)
+#define VI_INTERRUPT_STATUS_0_SECOND_OUTPUT_PEER_STALL_INT_STATUS_RANGE                 18:18
+#define VI_INTERRUPT_STATUS_0_SECOND_OUTPUT_PEER_STALL_INT_STATUS_WOFFSET                       0x0
+#define VI_INTERRUPT_STATUS_0_SECOND_OUTPUT_PEER_STALL_INT_STATUS_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_SECOND_OUTPUT_PEER_STALL_INT_STATUS_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_SECOND_OUTPUT_PEER_STALL_INT_STATUS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_SECOND_OUTPUT_PEER_STALL_INT_STATUS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_SECOND_OUTPUT_PEER_STALL_INT_STATUS_NOINTR                        _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_STATUS_0_SECOND_OUTPUT_PEER_STALL_INT_STATUS_INTR                  _MK_ENUM_CONST(1)
+
+// This bit shows the status of the condition when the
+//  VI drops data to the Write Buffer DMA
+//   0= Interrupt not detected
+//   1= Interrupt detected
+#define VI_INTERRUPT_STATUS_0_DMA_STALL_INT_STATUS_SHIFT                        _MK_SHIFT_CONST(19)
+#define VI_INTERRUPT_STATUS_0_DMA_STALL_INT_STATUS_FIELD                        (_MK_MASK_CONST(0x1) << VI_INTERRUPT_STATUS_0_DMA_STALL_INT_STATUS_SHIFT)
+#define VI_INTERRUPT_STATUS_0_DMA_STALL_INT_STATUS_RANGE                        19:19
+#define VI_INTERRUPT_STATUS_0_DMA_STALL_INT_STATUS_WOFFSET                      0x0
+#define VI_INTERRUPT_STATUS_0_DMA_STALL_INT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_DMA_STALL_INT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_DMA_STALL_INT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_DMA_STALL_INT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_DMA_STALL_INT_STATUS_NOINTR                       _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_STATUS_0_DMA_STALL_INT_STATUS_INTR                 _MK_ENUM_CONST(1)
+
+// Top or Bottom Field Status  This bit specifies whether the last received
+//  video data field is top field or bottom
+//  field as defined by FIELD_TYPE bit. This bit
+//  is forced to 0 if FIELD_DETECT is DISABLED
+//  when VIDEO_SOURCE is VIP.
+//  This bit cannot be reset by software by
+//  writing a 1.
+//   0= Bottom field received
+//   1= Top field received
+#define VI_INTERRUPT_STATUS_0_FIELD_STATUS_SHIFT                        _MK_SHIFT_CONST(20)
+#define VI_INTERRUPT_STATUS_0_FIELD_STATUS_FIELD                        (_MK_MASK_CONST(0x1) << VI_INTERRUPT_STATUS_0_FIELD_STATUS_SHIFT)
+#define VI_INTERRUPT_STATUS_0_FIELD_STATUS_RANGE                        20:20
+#define VI_INTERRUPT_STATUS_0_FIELD_STATUS_WOFFSET                      0x0
+#define VI_INTERRUPT_STATUS_0_FIELD_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_FIELD_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_FIELD_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_FIELD_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_FIELD_STATUS_BOTTOM                       _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_STATUS_0_FIELD_STATUS_TOP                  _MK_ENUM_CONST(1)
+
+// This bit shows the status of the condition when the
+//  Raise Stream 1 returns to the Host
+//   0= Interrupt not detected
+//   1= Interrupt detected
+#define VI_INTERRUPT_STATUS_0_RAISE_STREAM_1_INT_STATUS_SHIFT                   _MK_SHIFT_CONST(21)
+#define VI_INTERRUPT_STATUS_0_RAISE_STREAM_1_INT_STATUS_FIELD                   (_MK_MASK_CONST(0x1) << VI_INTERRUPT_STATUS_0_RAISE_STREAM_1_INT_STATUS_SHIFT)
+#define VI_INTERRUPT_STATUS_0_RAISE_STREAM_1_INT_STATUS_RANGE                   21:21
+#define VI_INTERRUPT_STATUS_0_RAISE_STREAM_1_INT_STATUS_WOFFSET                 0x0
+#define VI_INTERRUPT_STATUS_0_RAISE_STREAM_1_INT_STATUS_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_RAISE_STREAM_1_INT_STATUS_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_RAISE_STREAM_1_INT_STATUS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_RAISE_STREAM_1_INT_STATUS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_RAISE_STREAM_1_INT_STATUS_NOINTR                  _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_STATUS_0_RAISE_STREAM_1_INT_STATUS_INTR                    _MK_ENUM_CONST(1)
+
+// This bit shows the status of the condition when the
+//  Raise Stream 2 returns to the Host
+//   0= Interrupt not detected
+//   1= Interrupt detected
+#define VI_INTERRUPT_STATUS_0_RAISE_STREAM_2_INT_STATUS_SHIFT                   _MK_SHIFT_CONST(22)
+#define VI_INTERRUPT_STATUS_0_RAISE_STREAM_2_INT_STATUS_FIELD                   (_MK_MASK_CONST(0x1) << VI_INTERRUPT_STATUS_0_RAISE_STREAM_2_INT_STATUS_SHIFT)
+#define VI_INTERRUPT_STATUS_0_RAISE_STREAM_2_INT_STATUS_RANGE                   22:22
+#define VI_INTERRUPT_STATUS_0_RAISE_STREAM_2_INT_STATUS_WOFFSET                 0x0
+#define VI_INTERRUPT_STATUS_0_RAISE_STREAM_2_INT_STATUS_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_RAISE_STREAM_2_INT_STATUS_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_RAISE_STREAM_2_INT_STATUS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_RAISE_STREAM_2_INT_STATUS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_RAISE_STREAM_2_INT_STATUS_NOINTR                  _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_STATUS_0_RAISE_STREAM_2_INT_STATUS_INTR                    _MK_ENUM_CONST(1)
+
+// This bit shows the status of the condition when the
+//  ISDB-T vi input gets an upstream error (error from the tuner)
+//   0= Interrupt not detected
+//   1= Interrupt detected
+#define VI_INTERRUPT_STATUS_0_TS_UPSTREAM_ERROR_INT_STATUS_SHIFT                        _MK_SHIFT_CONST(23)
+#define VI_INTERRUPT_STATUS_0_TS_UPSTREAM_ERROR_INT_STATUS_FIELD                        (_MK_MASK_CONST(0x1) << VI_INTERRUPT_STATUS_0_TS_UPSTREAM_ERROR_INT_STATUS_SHIFT)
+#define VI_INTERRUPT_STATUS_0_TS_UPSTREAM_ERROR_INT_STATUS_RANGE                        23:23
+#define VI_INTERRUPT_STATUS_0_TS_UPSTREAM_ERROR_INT_STATUS_WOFFSET                      0x0
+#define VI_INTERRUPT_STATUS_0_TS_UPSTREAM_ERROR_INT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_TS_UPSTREAM_ERROR_INT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_TS_UPSTREAM_ERROR_INT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_TS_UPSTREAM_ERROR_INT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_TS_UPSTREAM_ERROR_INT_STATUS_NOINTR                       _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_STATUS_0_TS_UPSTREAM_ERROR_INT_STATUS_INTR                 _MK_ENUM_CONST(1)
+
+// This bit shows the status of the condition when the
+//  ISDB-T input get an underrun error (START condition detected
+//  prior to receiving a full packet)
+//   0= Interrupt not detected
+//   1= Interrupt detected
+#define VI_INTERRUPT_STATUS_0_TS_UNDERRUN_ERROR_INT_STATUS_SHIFT                        _MK_SHIFT_CONST(24)
+#define VI_INTERRUPT_STATUS_0_TS_UNDERRUN_ERROR_INT_STATUS_FIELD                        (_MK_MASK_CONST(0x1) << VI_INTERRUPT_STATUS_0_TS_UNDERRUN_ERROR_INT_STATUS_SHIFT)
+#define VI_INTERRUPT_STATUS_0_TS_UNDERRUN_ERROR_INT_STATUS_RANGE                        24:24
+#define VI_INTERRUPT_STATUS_0_TS_UNDERRUN_ERROR_INT_STATUS_WOFFSET                      0x0
+#define VI_INTERRUPT_STATUS_0_TS_UNDERRUN_ERROR_INT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_TS_UNDERRUN_ERROR_INT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_TS_UNDERRUN_ERROR_INT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_TS_UNDERRUN_ERROR_INT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_TS_UNDERRUN_ERROR_INT_STATUS_NOINTR                       _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_STATUS_0_TS_UNDERRUN_ERROR_INT_STATUS_INTR                 _MK_ENUM_CONST(1)
+
+// This bit shows the status of the condition when the
+//  ISDB-T input get an overrun error (more bytes in packet than specified
+//   0= Interrupt not detected
+//   1= Interrupt detected
+#define VI_INTERRUPT_STATUS_0_TS_OVERRUN_ERROR_INT_STATUS_SHIFT                 _MK_SHIFT_CONST(25)
+#define VI_INTERRUPT_STATUS_0_TS_OVERRUN_ERROR_INT_STATUS_FIELD                 (_MK_MASK_CONST(0x1) << VI_INTERRUPT_STATUS_0_TS_OVERRUN_ERROR_INT_STATUS_SHIFT)
+#define VI_INTERRUPT_STATUS_0_TS_OVERRUN_ERROR_INT_STATUS_RANGE                 25:25
+#define VI_INTERRUPT_STATUS_0_TS_OVERRUN_ERROR_INT_STATUS_WOFFSET                       0x0
+#define VI_INTERRUPT_STATUS_0_TS_OVERRUN_ERROR_INT_STATUS_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_TS_OVERRUN_ERROR_INT_STATUS_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_TS_OVERRUN_ERROR_INT_STATUS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_TS_OVERRUN_ERROR_INT_STATUS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_TS_OVERRUN_ERROR_INT_STATUS_NOINTR                        _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_STATUS_0_TS_OVERRUN_ERROR_INT_STATUS_INTR                  _MK_ENUM_CONST(1)
+
+// This bit shows the status of the condition when the
+//  ISDB-T input an other protocol error (ex:
+//  total packet received is FEC_SIZE+BODY_SIZE but
+//  the individual FEC portion != FEC_SIZE and
+//  the individual BODY portion != BODY_SIZE
+//   0= Interrupt not detected
+//   1= Interrupt detected
+#define VI_INTERRUPT_STATUS_0_TS_OTHER_PROTOCOL_ERROR_INT_STATUS_SHIFT                  _MK_SHIFT_CONST(26)
+#define VI_INTERRUPT_STATUS_0_TS_OTHER_PROTOCOL_ERROR_INT_STATUS_FIELD                  (_MK_MASK_CONST(0x1) << VI_INTERRUPT_STATUS_0_TS_OTHER_PROTOCOL_ERROR_INT_STATUS_SHIFT)
+#define VI_INTERRUPT_STATUS_0_TS_OTHER_PROTOCOL_ERROR_INT_STATUS_RANGE                  26:26
+#define VI_INTERRUPT_STATUS_0_TS_OTHER_PROTOCOL_ERROR_INT_STATUS_WOFFSET                        0x0
+#define VI_INTERRUPT_STATUS_0_TS_OTHER_PROTOCOL_ERROR_INT_STATUS_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_TS_OTHER_PROTOCOL_ERROR_INT_STATUS_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_TS_OTHER_PROTOCOL_ERROR_INT_STATUS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_TS_OTHER_PROTOCOL_ERROR_INT_STATUS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_TS_OTHER_PROTOCOL_ERROR_INT_STATUS_NOINTR                 _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_STATUS_0_TS_OTHER_PROTOCOL_ERROR_INT_STATUS_INTR                   _MK_ENUM_CONST(1)
+
+// If FIRST_OUTPUT is dropping data to MC, INTR
+//   will be set.
+#define VI_INTERRUPT_STATUS_0_FIRST_OUTPUT_DROP_MC_DATA_INT_STATUS_SHIFT                        _MK_SHIFT_CONST(27)
+#define VI_INTERRUPT_STATUS_0_FIRST_OUTPUT_DROP_MC_DATA_INT_STATUS_FIELD                        (_MK_MASK_CONST(0x1) << VI_INTERRUPT_STATUS_0_FIRST_OUTPUT_DROP_MC_DATA_INT_STATUS_SHIFT)
+#define VI_INTERRUPT_STATUS_0_FIRST_OUTPUT_DROP_MC_DATA_INT_STATUS_RANGE                        27:27
+#define VI_INTERRUPT_STATUS_0_FIRST_OUTPUT_DROP_MC_DATA_INT_STATUS_WOFFSET                      0x0
+#define VI_INTERRUPT_STATUS_0_FIRST_OUTPUT_DROP_MC_DATA_INT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_FIRST_OUTPUT_DROP_MC_DATA_INT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_FIRST_OUTPUT_DROP_MC_DATA_INT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_FIRST_OUTPUT_DROP_MC_DATA_INT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_FIRST_OUTPUT_DROP_MC_DATA_INT_STATUS_NOINTR                       _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_STATUS_0_FIRST_OUTPUT_DROP_MC_DATA_INT_STATUS_INTR                 _MK_ENUM_CONST(1)
+
+// If SECOND_OUTPUT is dropping data to MC, INTR
+//   will be set.
+#define VI_INTERRUPT_STATUS_0_SECOND_OUTPUT_DROP_MC_DATA_INT_STATUS_SHIFT                       _MK_SHIFT_CONST(28)
+#define VI_INTERRUPT_STATUS_0_SECOND_OUTPUT_DROP_MC_DATA_INT_STATUS_FIELD                       (_MK_MASK_CONST(0x1) << VI_INTERRUPT_STATUS_0_SECOND_OUTPUT_DROP_MC_DATA_INT_STATUS_SHIFT)
+#define VI_INTERRUPT_STATUS_0_SECOND_OUTPUT_DROP_MC_DATA_INT_STATUS_RANGE                       28:28
+#define VI_INTERRUPT_STATUS_0_SECOND_OUTPUT_DROP_MC_DATA_INT_STATUS_WOFFSET                     0x0
+#define VI_INTERRUPT_STATUS_0_SECOND_OUTPUT_DROP_MC_DATA_INT_STATUS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_SECOND_OUTPUT_DROP_MC_DATA_INT_STATUS_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_SECOND_OUTPUT_DROP_MC_DATA_INT_STATUS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_SECOND_OUTPUT_DROP_MC_DATA_INT_STATUS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_SECOND_OUTPUT_DROP_MC_DATA_INT_STATUS_NOINTR                      _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_STATUS_0_SECOND_OUTPUT_DROP_MC_DATA_INT_STATUS_INTR                        _MK_ENUM_CONST(1)
+
+
+// Register VI_VIP_INPUT_STATUS_0  // Video Input Port status
+#define VI_VIP_INPUT_STATUS_0                   _MK_ADDR_CONST(0x51)
+#define VI_VIP_INPUT_STATUS_0_WORD_COUNT                        0x1
+#define VI_VIP_INPUT_STATUS_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define VI_VIP_INPUT_STATUS_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define VI_VIP_INPUT_STATUS_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define VI_VIP_INPUT_STATUS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_VIP_INPUT_STATUS_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define VI_VIP_INPUT_STATUS_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+// The number of lines received (hsyncs)
+#define VI_VIP_INPUT_STATUS_0_LINE_COUNT_SHIFT                  _MK_SHIFT_CONST(0)
+#define VI_VIP_INPUT_STATUS_0_LINE_COUNT_FIELD                  (_MK_MASK_CONST(0xffff) << VI_VIP_INPUT_STATUS_0_LINE_COUNT_SHIFT)
+#define VI_VIP_INPUT_STATUS_0_LINE_COUNT_RANGE                  15:0
+#define VI_VIP_INPUT_STATUS_0_LINE_COUNT_WOFFSET                        0x0
+#define VI_VIP_INPUT_STATUS_0_LINE_COUNT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_VIP_INPUT_STATUS_0_LINE_COUNT_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_VIP_INPUT_STATUS_0_LINE_COUNT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_VIP_INPUT_STATUS_0_LINE_COUNT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// The number of frames received (vsyncs)
+// Any write to this register, clears.
+#define VI_VIP_INPUT_STATUS_0_FRAME_COUNT_SHIFT                 _MK_SHIFT_CONST(16)
+#define VI_VIP_INPUT_STATUS_0_FRAME_COUNT_FIELD                 (_MK_MASK_CONST(0xffff) << VI_VIP_INPUT_STATUS_0_FRAME_COUNT_SHIFT)
+#define VI_VIP_INPUT_STATUS_0_FRAME_COUNT_RANGE                 31:16
+#define VI_VIP_INPUT_STATUS_0_FRAME_COUNT_WOFFSET                       0x0
+#define VI_VIP_INPUT_STATUS_0_FRAME_COUNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_VIP_INPUT_STATUS_0_FRAME_COUNT_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_VIP_INPUT_STATUS_0_FRAME_COUNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_VIP_INPUT_STATUS_0_FRAME_COUNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register VI_VIDEO_BUFFER_STATUS_0  // Interrupt Enable
+#define VI_VIDEO_BUFFER_STATUS_0                        _MK_ADDR_CONST(0x52)
+#define VI_VIDEO_BUFFER_STATUS_0_WORD_COUNT                     0x1
+#define VI_VIDEO_BUFFER_STATUS_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define VI_VIDEO_BUFFER_STATUS_0_RESET_MASK                     _MK_MASK_CONST(0x0)
+#define VI_VIDEO_BUFFER_STATUS_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define VI_VIDEO_BUFFER_STATUS_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_VIDEO_BUFFER_STATUS_0_READ_MASK                      _MK_MASK_CONST(0xfffff)
+#define VI_VIDEO_BUFFER_STATUS_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
+// Buffer status
+//  This specifies the buffer number of the
+//  the last video data field written to memory
+#define VI_VIDEO_BUFFER_STATUS_0_FIRST_VIDEO_BUFFER_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
+#define VI_VIDEO_BUFFER_STATUS_0_FIRST_VIDEO_BUFFER_STATUS_FIELD                        (_MK_MASK_CONST(0xff) << VI_VIDEO_BUFFER_STATUS_0_FIRST_VIDEO_BUFFER_STATUS_SHIFT)
+#define VI_VIDEO_BUFFER_STATUS_0_FIRST_VIDEO_BUFFER_STATUS_RANGE                        7:0
+#define VI_VIDEO_BUFFER_STATUS_0_FIRST_VIDEO_BUFFER_STATUS_WOFFSET                      0x0
+#define VI_VIDEO_BUFFER_STATUS_0_FIRST_VIDEO_BUFFER_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_VIDEO_BUFFER_STATUS_0_FIRST_VIDEO_BUFFER_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_VIDEO_BUFFER_STATUS_0_FIRST_VIDEO_BUFFER_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_VIDEO_BUFFER_STATUS_0_FIRST_VIDEO_BUFFER_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Buffer status
+//  This specifies the buffer number of the
+//  the last video data field written to memory
+#define VI_VIDEO_BUFFER_STATUS_0_SECOND_VIDEO_BUFFER_STATUS_SHIFT                       _MK_SHIFT_CONST(8)
+#define VI_VIDEO_BUFFER_STATUS_0_SECOND_VIDEO_BUFFER_STATUS_FIELD                       (_MK_MASK_CONST(0xff) << VI_VIDEO_BUFFER_STATUS_0_SECOND_VIDEO_BUFFER_STATUS_SHIFT)
+#define VI_VIDEO_BUFFER_STATUS_0_SECOND_VIDEO_BUFFER_STATUS_RANGE                       15:8
+#define VI_VIDEO_BUFFER_STATUS_0_SECOND_VIDEO_BUFFER_STATUS_WOFFSET                     0x0
+#define VI_VIDEO_BUFFER_STATUS_0_SECOND_VIDEO_BUFFER_STATUS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_VIDEO_BUFFER_STATUS_0_SECOND_VIDEO_BUFFER_STATUS_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_VIDEO_BUFFER_STATUS_0_SECOND_VIDEO_BUFFER_STATUS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_VIDEO_BUFFER_STATUS_0_SECOND_VIDEO_BUFFER_STATUS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Write count of the Raw Stream Write FIFO
+//  This is the fifo used to synchronize the
+//  data coming from pads into the vi clock domain.
+#define VI_VIDEO_BUFFER_STATUS_0_RAW_STREAM_WRITE_COUNT_SHIFT                   _MK_SHIFT_CONST(16)
+#define VI_VIDEO_BUFFER_STATUS_0_RAW_STREAM_WRITE_COUNT_FIELD                   (_MK_MASK_CONST(0xf) << VI_VIDEO_BUFFER_STATUS_0_RAW_STREAM_WRITE_COUNT_SHIFT)
+#define VI_VIDEO_BUFFER_STATUS_0_RAW_STREAM_WRITE_COUNT_RANGE                   19:16
+#define VI_VIDEO_BUFFER_STATUS_0_RAW_STREAM_WRITE_COUNT_WOFFSET                 0x0
+#define VI_VIDEO_BUFFER_STATUS_0_RAW_STREAM_WRITE_COUNT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_VIDEO_BUFFER_STATUS_0_RAW_STREAM_WRITE_COUNT_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_VIDEO_BUFFER_STATUS_0_RAW_STREAM_WRITE_COUNT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_VIDEO_BUFFER_STATUS_0_RAW_STREAM_WRITE_COUNT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register VI_SYNC_OUTPUT_0  // VI H and V sync Output control
+#define VI_SYNC_OUTPUT_0                        _MK_ADDR_CONST(0x53)
+#define VI_SYNC_OUTPUT_0_WORD_COUNT                     0x1
+#define VI_SYNC_OUTPUT_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define VI_SYNC_OUTPUT_0_RESET_MASK                     _MK_MASK_CONST(0x0)
+#define VI_SYNC_OUTPUT_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define VI_SYNC_OUTPUT_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_SYNC_OUTPUT_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define VI_SYNC_OUTPUT_0_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
+// This specifies VHS output pulse width in
+//  term of number of VI clock cycles.
+//  Programmed value is actual value - 1 so
+//  valid value ranges from 1 to 8.
+#define VI_SYNC_OUTPUT_0_VHS_OUTPUT_WIDTH_SHIFT                 _MK_SHIFT_CONST(0)
+#define VI_SYNC_OUTPUT_0_VHS_OUTPUT_WIDTH_FIELD                 (_MK_MASK_CONST(0x7) << VI_SYNC_OUTPUT_0_VHS_OUTPUT_WIDTH_SHIFT)
+#define VI_SYNC_OUTPUT_0_VHS_OUTPUT_WIDTH_RANGE                 2:0
+#define VI_SYNC_OUTPUT_0_VHS_OUTPUT_WIDTH_WOFFSET                       0x0
+#define VI_SYNC_OUTPUT_0_VHS_OUTPUT_WIDTH_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_SYNC_OUTPUT_0_VHS_OUTPUT_WIDTH_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_SYNC_OUTPUT_0_VHS_OUTPUT_WIDTH_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_SYNC_OUTPUT_0_VHS_OUTPUT_WIDTH_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// This specifies VHS output pulse period in
+//  term of number of VI clock cycles.
+//  Programmed value is actual value - 1 so
+//  valid value ranges from 32 to 8192.
+#define VI_SYNC_OUTPUT_0_VHS_OUTPUT_PERIOD_SHIFT                        _MK_SHIFT_CONST(3)
+#define VI_SYNC_OUTPUT_0_VHS_OUTPUT_PERIOD_FIELD                        (_MK_MASK_CONST(0x1fff) << VI_SYNC_OUTPUT_0_VHS_OUTPUT_PERIOD_SHIFT)
+#define VI_SYNC_OUTPUT_0_VHS_OUTPUT_PERIOD_RANGE                        15:3
+#define VI_SYNC_OUTPUT_0_VHS_OUTPUT_PERIOD_WOFFSET                      0x0
+#define VI_SYNC_OUTPUT_0_VHS_OUTPUT_PERIOD_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_SYNC_OUTPUT_0_VHS_OUTPUT_PERIOD_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_SYNC_OUTPUT_0_VHS_OUTPUT_PERIOD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_SYNC_OUTPUT_0_VHS_OUTPUT_PERIOD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// This specifies VVS output pulse width in
+//  term of number of VHS cycles.
+//  Programmed value is actual value - 1 so
+//  valid value ranges from 1 to 8.
+#define VI_SYNC_OUTPUT_0_VVS_OUTPUT_WIDTH_SHIFT                 _MK_SHIFT_CONST(16)
+#define VI_SYNC_OUTPUT_0_VVS_OUTPUT_WIDTH_FIELD                 (_MK_MASK_CONST(0x7) << VI_SYNC_OUTPUT_0_VVS_OUTPUT_WIDTH_SHIFT)
+#define VI_SYNC_OUTPUT_0_VVS_OUTPUT_WIDTH_RANGE                 18:16
+#define VI_SYNC_OUTPUT_0_VVS_OUTPUT_WIDTH_WOFFSET                       0x0
+#define VI_SYNC_OUTPUT_0_VVS_OUTPUT_WIDTH_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_SYNC_OUTPUT_0_VVS_OUTPUT_WIDTH_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_SYNC_OUTPUT_0_VVS_OUTPUT_WIDTH_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_SYNC_OUTPUT_0_VVS_OUTPUT_WIDTH_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// This specifies VVS output pulse period in
+//  term of number of VHS cycles.
+//  Programmed value is actual value - 1 so
+//  valid value ranges from 2 to 4096.
+#define VI_SYNC_OUTPUT_0_VVS_OUTPUT_PERIOD_SHIFT                        _MK_SHIFT_CONST(19)
+#define VI_SYNC_OUTPUT_0_VVS_OUTPUT_PERIOD_FIELD                        (_MK_MASK_CONST(0x1fff) << VI_SYNC_OUTPUT_0_VVS_OUTPUT_PERIOD_SHIFT)
+#define VI_SYNC_OUTPUT_0_VVS_OUTPUT_PERIOD_RANGE                        31:19
+#define VI_SYNC_OUTPUT_0_VVS_OUTPUT_PERIOD_WOFFSET                      0x0
+#define VI_SYNC_OUTPUT_0_VVS_OUTPUT_PERIOD_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_SYNC_OUTPUT_0_VVS_OUTPUT_PERIOD_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_SYNC_OUTPUT_0_VVS_OUTPUT_PERIOD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_SYNC_OUTPUT_0_VVS_OUTPUT_PERIOD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register VI_VVS_OUTPUT_DELAY_0  // VI V sync Output Delay
+#define VI_VVS_OUTPUT_DELAY_0                   _MK_ADDR_CONST(0x54)
+#define VI_VVS_OUTPUT_DELAY_0_WORD_COUNT                        0x1
+#define VI_VVS_OUTPUT_DELAY_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define VI_VVS_OUTPUT_DELAY_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define VI_VVS_OUTPUT_DELAY_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define VI_VVS_OUTPUT_DELAY_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_VVS_OUTPUT_DELAY_0_READ_MASK                         _MK_MASK_CONST(0xf)
+#define VI_VVS_OUTPUT_DELAY_0_WRITE_MASK                        _MK_MASK_CONST(0xf)
+// This specifies the number of VI clock cycles
+//  from leading edge of VHS to leading edge of
+//  VVS.
+//  Programmed value is actual value + 2 so
+//  valid value ranges from -2 to 13.
+#define VI_VVS_OUTPUT_DELAY_0_VVS_OUTPUT_DELAY_SHIFT                    _MK_SHIFT_CONST(0)
+#define VI_VVS_OUTPUT_DELAY_0_VVS_OUTPUT_DELAY_FIELD                    (_MK_MASK_CONST(0xf) << VI_VVS_OUTPUT_DELAY_0_VVS_OUTPUT_DELAY_SHIFT)
+#define VI_VVS_OUTPUT_DELAY_0_VVS_OUTPUT_DELAY_RANGE                    3:0
+#define VI_VVS_OUTPUT_DELAY_0_VVS_OUTPUT_DELAY_WOFFSET                  0x0
+#define VI_VVS_OUTPUT_DELAY_0_VVS_OUTPUT_DELAY_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_VVS_OUTPUT_DELAY_0_VVS_OUTPUT_DELAY_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_VVS_OUTPUT_DELAY_0_VVS_OUTPUT_DELAY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_VVS_OUTPUT_DELAY_0_VVS_OUTPUT_DELAY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register VI_PWM_CONTROL_0  // VI Pulse Width Modulation Control
+#define VI_PWM_CONTROL_0                        _MK_ADDR_CONST(0x55)
+#define VI_PWM_CONTROL_0_WORD_COUNT                     0x1
+#define VI_PWM_CONTROL_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define VI_PWM_CONTROL_0_RESET_MASK                     _MK_MASK_CONST(0xff30ff11)
+#define VI_PWM_CONTROL_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define VI_PWM_CONTROL_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_PWM_CONTROL_0_READ_MASK                      _MK_MASK_CONST(0xff30ff11)
+#define VI_PWM_CONTROL_0_WRITE_MASK                     _MK_MASK_CONST(0xff30ff11)
+// PWM Enable  0= Disabled
+//  1= Enabled
+#define VI_PWM_CONTROL_0_PWM_ENABLE_SHIFT                       _MK_SHIFT_CONST(0)
+#define VI_PWM_CONTROL_0_PWM_ENABLE_FIELD                       (_MK_MASK_CONST(0x1) << VI_PWM_CONTROL_0_PWM_ENABLE_SHIFT)
+#define VI_PWM_CONTROL_0_PWM_ENABLE_RANGE                       0:0
+#define VI_PWM_CONTROL_0_PWM_ENABLE_WOFFSET                     0x0
+#define VI_PWM_CONTROL_0_PWM_ENABLE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_PWM_CONTROL_0_PWM_ENABLE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define VI_PWM_CONTROL_0_PWM_ENABLE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_PWM_CONTROL_0_PWM_ENABLE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_PWM_CONTROL_0_PWM_ENABLE_DISABLED                    _MK_ENUM_CONST(0)
+#define VI_PWM_CONTROL_0_PWM_ENABLE_ENABLED                     _MK_ENUM_CONST(1)
+
+// PWM Direction  0= Incrementing
+//  1= Decrementing
+#define VI_PWM_CONTROL_0_PWM_DIRECTION_SHIFT                    _MK_SHIFT_CONST(4)
+#define VI_PWM_CONTROL_0_PWM_DIRECTION_FIELD                    (_MK_MASK_CONST(0x1) << VI_PWM_CONTROL_0_PWM_DIRECTION_SHIFT)
+#define VI_PWM_CONTROL_0_PWM_DIRECTION_RANGE                    4:4
+#define VI_PWM_CONTROL_0_PWM_DIRECTION_WOFFSET                  0x0
+#define VI_PWM_CONTROL_0_PWM_DIRECTION_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_PWM_CONTROL_0_PWM_DIRECTION_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define VI_PWM_CONTROL_0_PWM_DIRECTION_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_PWM_CONTROL_0_PWM_DIRECTION_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_PWM_CONTROL_0_PWM_DIRECTION_INCR                     _MK_ENUM_CONST(0)
+#define VI_PWM_CONTROL_0_PWM_DIRECTION_DECR                     _MK_ENUM_CONST(1)
+
+// PWM High Pulse (1 to 16)
+#define VI_PWM_CONTROL_0_PWM_HIGH_PULSE_SHIFT                   _MK_SHIFT_CONST(8)
+#define VI_PWM_CONTROL_0_PWM_HIGH_PULSE_FIELD                   (_MK_MASK_CONST(0xf) << VI_PWM_CONTROL_0_PWM_HIGH_PULSE_SHIFT)
+#define VI_PWM_CONTROL_0_PWM_HIGH_PULSE_RANGE                   11:8
+#define VI_PWM_CONTROL_0_PWM_HIGH_PULSE_WOFFSET                 0x0
+#define VI_PWM_CONTROL_0_PWM_HIGH_PULSE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PWM_CONTROL_0_PWM_HIGH_PULSE_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define VI_PWM_CONTROL_0_PWM_HIGH_PULSE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_PWM_CONTROL_0_PWM_HIGH_PULSE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// PWM Low Pulse  (1 to 16)
+// 19:16 reserved
+#define VI_PWM_CONTROL_0_PWM_LOW_PULSE_SHIFT                    _MK_SHIFT_CONST(12)
+#define VI_PWM_CONTROL_0_PWM_LOW_PULSE_FIELD                    (_MK_MASK_CONST(0xf) << VI_PWM_CONTROL_0_PWM_LOW_PULSE_SHIFT)
+#define VI_PWM_CONTROL_0_PWM_LOW_PULSE_RANGE                    15:12
+#define VI_PWM_CONTROL_0_PWM_LOW_PULSE_WOFFSET                  0x0
+#define VI_PWM_CONTROL_0_PWM_LOW_PULSE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_PWM_CONTROL_0_PWM_LOW_PULSE_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
+#define VI_PWM_CONTROL_0_PWM_LOW_PULSE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_PWM_CONTROL_0_PWM_LOW_PULSE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// PWM Mode Continous - after PWM is turned on, continue
+//              through the PWM's 128 cycles
+//              repeatedly until the pwm is turned off.
+// Single - after PWM is turned on, cycle once through
+//          the 128 cycles and stop.
+// Counter - after PWM is turned on, cycle through
+//           the 128 cycles PWM_COUNTER number of
+//           times then stop.
+// 23:22 reserved
+#define VI_PWM_CONTROL_0_PWM_MODE_SHIFT                 _MK_SHIFT_CONST(20)
+#define VI_PWM_CONTROL_0_PWM_MODE_FIELD                 (_MK_MASK_CONST(0x3) << VI_PWM_CONTROL_0_PWM_MODE_SHIFT)
+#define VI_PWM_CONTROL_0_PWM_MODE_RANGE                 21:20
+#define VI_PWM_CONTROL_0_PWM_MODE_WOFFSET                       0x0
+#define VI_PWM_CONTROL_0_PWM_MODE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_PWM_CONTROL_0_PWM_MODE_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define VI_PWM_CONTROL_0_PWM_MODE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PWM_CONTROL_0_PWM_MODE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_PWM_CONTROL_0_PWM_MODE_CONTINUOUS                    _MK_ENUM_CONST(0)
+#define VI_PWM_CONTROL_0_PWM_MODE_SINGLE                        _MK_ENUM_CONST(1)
+#define VI_PWM_CONTROL_0_PWM_MODE_COUNTER                       _MK_ENUM_CONST(2)
+
+// PWM Counter
+//  8-bit value used when PWM_MODE is set to COUNTER
+//  to determine how many times the PWM will cycle
+//  through the 128 cycles
+//  before stopping.
+#define VI_PWM_CONTROL_0_PWM_COUNTER_SHIFT                      _MK_SHIFT_CONST(24)
+#define VI_PWM_CONTROL_0_PWM_COUNTER_FIELD                      (_MK_MASK_CONST(0xff) << VI_PWM_CONTROL_0_PWM_COUNTER_SHIFT)
+#define VI_PWM_CONTROL_0_PWM_COUNTER_RANGE                      31:24
+#define VI_PWM_CONTROL_0_PWM_COUNTER_WOFFSET                    0x0
+#define VI_PWM_CONTROL_0_PWM_COUNTER_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PWM_CONTROL_0_PWM_COUNTER_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
+#define VI_PWM_CONTROL_0_PWM_COUNTER_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PWM_CONTROL_0_PWM_COUNTER_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register VI_PWM_SELECT_PULSE_A_0  // PWM Pulse Select A
+#define VI_PWM_SELECT_PULSE_A_0                 _MK_ADDR_CONST(0x56)
+#define VI_PWM_SELECT_PULSE_A_0_WORD_COUNT                      0x1
+#define VI_PWM_SELECT_PULSE_A_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define VI_PWM_SELECT_PULSE_A_0_RESET_MASK                      _MK_MASK_CONST(0x0)
+#define VI_PWM_SELECT_PULSE_A_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define VI_PWM_SELECT_PULSE_A_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define VI_PWM_SELECT_PULSE_A_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define VI_PWM_SELECT_PULSE_A_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// PWM Select bits 31 to 0
+#define VI_PWM_SELECT_PULSE_A_0_PWM_SELECT_A_SHIFT                      _MK_SHIFT_CONST(0)
+#define VI_PWM_SELECT_PULSE_A_0_PWM_SELECT_A_FIELD                      (_MK_MASK_CONST(0xffffffff) << VI_PWM_SELECT_PULSE_A_0_PWM_SELECT_A_SHIFT)
+#define VI_PWM_SELECT_PULSE_A_0_PWM_SELECT_A_RANGE                      31:0
+#define VI_PWM_SELECT_PULSE_A_0_PWM_SELECT_A_WOFFSET                    0x0
+#define VI_PWM_SELECT_PULSE_A_0_PWM_SELECT_A_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PWM_SELECT_PULSE_A_0_PWM_SELECT_A_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_PWM_SELECT_PULSE_A_0_PWM_SELECT_A_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PWM_SELECT_PULSE_A_0_PWM_SELECT_A_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register VI_PWM_SELECT_PULSE_B_0  // PWM Pulse Select B
+#define VI_PWM_SELECT_PULSE_B_0                 _MK_ADDR_CONST(0x57)
+#define VI_PWM_SELECT_PULSE_B_0_WORD_COUNT                      0x1
+#define VI_PWM_SELECT_PULSE_B_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define VI_PWM_SELECT_PULSE_B_0_RESET_MASK                      _MK_MASK_CONST(0x0)
+#define VI_PWM_SELECT_PULSE_B_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define VI_PWM_SELECT_PULSE_B_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define VI_PWM_SELECT_PULSE_B_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define VI_PWM_SELECT_PULSE_B_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// PWM Select bits 63 to 32
+#define VI_PWM_SELECT_PULSE_B_0_PWM_SELECT_B_SHIFT                      _MK_SHIFT_CONST(0)
+#define VI_PWM_SELECT_PULSE_B_0_PWM_SELECT_B_FIELD                      (_MK_MASK_CONST(0xffffffff) << VI_PWM_SELECT_PULSE_B_0_PWM_SELECT_B_SHIFT)
+#define VI_PWM_SELECT_PULSE_B_0_PWM_SELECT_B_RANGE                      31:0
+#define VI_PWM_SELECT_PULSE_B_0_PWM_SELECT_B_WOFFSET                    0x0
+#define VI_PWM_SELECT_PULSE_B_0_PWM_SELECT_B_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PWM_SELECT_PULSE_B_0_PWM_SELECT_B_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_PWM_SELECT_PULSE_B_0_PWM_SELECT_B_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PWM_SELECT_PULSE_B_0_PWM_SELECT_B_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register VI_PWM_SELECT_PULSE_C_0  // PWM Pulse Select C
+#define VI_PWM_SELECT_PULSE_C_0                 _MK_ADDR_CONST(0x58)
+#define VI_PWM_SELECT_PULSE_C_0_WORD_COUNT                      0x1
+#define VI_PWM_SELECT_PULSE_C_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define VI_PWM_SELECT_PULSE_C_0_RESET_MASK                      _MK_MASK_CONST(0x0)
+#define VI_PWM_SELECT_PULSE_C_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define VI_PWM_SELECT_PULSE_C_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define VI_PWM_SELECT_PULSE_C_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define VI_PWM_SELECT_PULSE_C_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// PWM Select bits 95 to 64
+#define VI_PWM_SELECT_PULSE_C_0_PWM_SELECT_C_SHIFT                      _MK_SHIFT_CONST(0)
+#define VI_PWM_SELECT_PULSE_C_0_PWM_SELECT_C_FIELD                      (_MK_MASK_CONST(0xffffffff) << VI_PWM_SELECT_PULSE_C_0_PWM_SELECT_C_SHIFT)
+#define VI_PWM_SELECT_PULSE_C_0_PWM_SELECT_C_RANGE                      31:0
+#define VI_PWM_SELECT_PULSE_C_0_PWM_SELECT_C_WOFFSET                    0x0
+#define VI_PWM_SELECT_PULSE_C_0_PWM_SELECT_C_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PWM_SELECT_PULSE_C_0_PWM_SELECT_C_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_PWM_SELECT_PULSE_C_0_PWM_SELECT_C_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PWM_SELECT_PULSE_C_0_PWM_SELECT_C_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register VI_PWM_SELECT_PULSE_D_0  // PWM Pulse Select D
+#define VI_PWM_SELECT_PULSE_D_0                 _MK_ADDR_CONST(0x59)
+#define VI_PWM_SELECT_PULSE_D_0_WORD_COUNT                      0x1
+#define VI_PWM_SELECT_PULSE_D_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define VI_PWM_SELECT_PULSE_D_0_RESET_MASK                      _MK_MASK_CONST(0x0)
+#define VI_PWM_SELECT_PULSE_D_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define VI_PWM_SELECT_PULSE_D_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define VI_PWM_SELECT_PULSE_D_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define VI_PWM_SELECT_PULSE_D_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// PWM Select bits 127 to 96
+#define VI_PWM_SELECT_PULSE_D_0_PWM_SELECT_D_SHIFT                      _MK_SHIFT_CONST(0)
+#define VI_PWM_SELECT_PULSE_D_0_PWM_SELECT_D_FIELD                      (_MK_MASK_CONST(0xffffffff) << VI_PWM_SELECT_PULSE_D_0_PWM_SELECT_D_SHIFT)
+#define VI_PWM_SELECT_PULSE_D_0_PWM_SELECT_D_RANGE                      31:0
+#define VI_PWM_SELECT_PULSE_D_0_PWM_SELECT_D_WOFFSET                    0x0
+#define VI_PWM_SELECT_PULSE_D_0_PWM_SELECT_D_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PWM_SELECT_PULSE_D_0_PWM_SELECT_D_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_PWM_SELECT_PULSE_D_0_PWM_SELECT_D_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PWM_SELECT_PULSE_D_0_PWM_SELECT_D_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register VI_VI_DATA_INPUT_CONTROL_0  // VI Input Mask
+#define VI_VI_DATA_INPUT_CONTROL_0                      _MK_ADDR_CONST(0x5a)
+#define VI_VI_DATA_INPUT_CONTROL_0_WORD_COUNT                   0x1
+#define VI_VI_DATA_INPUT_CONTROL_0_RESET_VAL                    _MK_MASK_CONST(0xfff)
+#define VI_VI_DATA_INPUT_CONTROL_0_RESET_MASK                   _MK_MASK_CONST(0xfff)
+#define VI_VI_DATA_INPUT_CONTROL_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define VI_VI_DATA_INPUT_CONTROL_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_VI_DATA_INPUT_CONTROL_0_READ_MASK                    _MK_MASK_CONST(0xfff)
+#define VI_VI_DATA_INPUT_CONTROL_0_WRITE_MASK                   _MK_MASK_CONST(0xfff)
+// Mask the VD[11:0] pin inputs to the VI core and ISP
+// The mask is not applied to the Host GPIO read value
+#define VI_VI_DATA_INPUT_CONTROL_0_VI_DATA_INPUT_MASK_SHIFT                     _MK_SHIFT_CONST(0)
+#define VI_VI_DATA_INPUT_CONTROL_0_VI_DATA_INPUT_MASK_FIELD                     (_MK_MASK_CONST(0xfff) << VI_VI_DATA_INPUT_CONTROL_0_VI_DATA_INPUT_MASK_SHIFT)
+#define VI_VI_DATA_INPUT_CONTROL_0_VI_DATA_INPUT_MASK_RANGE                     11:0
+#define VI_VI_DATA_INPUT_CONTROL_0_VI_DATA_INPUT_MASK_WOFFSET                   0x0
+#define VI_VI_DATA_INPUT_CONTROL_0_VI_DATA_INPUT_MASK_DEFAULT                   _MK_MASK_CONST(0xfff)
+#define VI_VI_DATA_INPUT_CONTROL_0_VI_DATA_INPUT_MASK_DEFAULT_MASK                      _MK_MASK_CONST(0xfff)
+#define VI_VI_DATA_INPUT_CONTROL_0_VI_DATA_INPUT_MASK_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_VI_DATA_INPUT_CONTROL_0_VI_DATA_INPUT_MASK_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register VI_PIN_INPUT_ENABLE_0  // VI pins Input Enable
+#define VI_PIN_INPUT_ENABLE_0                   _MK_ADDR_CONST(0x5b)
+#define VI_PIN_INPUT_ENABLE_0_WORD_COUNT                        0x1
+#define VI_PIN_INPUT_ENABLE_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_RESET_MASK                        _MK_MASK_CONST(0x3fefff)
+#define VI_PIN_INPUT_ENABLE_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_READ_MASK                         _MK_MASK_CONST(0x3fefff)
+#define VI_PIN_INPUT_ENABLE_0_WRITE_MASK                        _MK_MASK_CONST(0x3fefff)
+// VD0 pin Input Enable  This bit controls VD0 pin input.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_INPUT_ENABLE_0_VD0_INPUT_ENABLE_SHIFT                    _MK_SHIFT_CONST(0)
+#define VI_PIN_INPUT_ENABLE_0_VD0_INPUT_ENABLE_FIELD                    (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_ENABLE_0_VD0_INPUT_ENABLE_SHIFT)
+#define VI_PIN_INPUT_ENABLE_0_VD0_INPUT_ENABLE_RANGE                    0:0
+#define VI_PIN_INPUT_ENABLE_0_VD0_INPUT_ENABLE_WOFFSET                  0x0
+#define VI_PIN_INPUT_ENABLE_0_VD0_INPUT_ENABLE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VD0_INPUT_ENABLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define VI_PIN_INPUT_ENABLE_0_VD0_INPUT_ENABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VD0_INPUT_ENABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VD0_INPUT_ENABLE_DISABLED                 _MK_ENUM_CONST(0)
+#define VI_PIN_INPUT_ENABLE_0_VD0_INPUT_ENABLE_ENABLED                  _MK_ENUM_CONST(1)
+
+// VD1 pin Input Enable  This bit controls VD1 pin input.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_INPUT_ENABLE_0_VD1_INPUT_ENABLE_SHIFT                    _MK_SHIFT_CONST(1)
+#define VI_PIN_INPUT_ENABLE_0_VD1_INPUT_ENABLE_FIELD                    (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_ENABLE_0_VD1_INPUT_ENABLE_SHIFT)
+#define VI_PIN_INPUT_ENABLE_0_VD1_INPUT_ENABLE_RANGE                    1:1
+#define VI_PIN_INPUT_ENABLE_0_VD1_INPUT_ENABLE_WOFFSET                  0x0
+#define VI_PIN_INPUT_ENABLE_0_VD1_INPUT_ENABLE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VD1_INPUT_ENABLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define VI_PIN_INPUT_ENABLE_0_VD1_INPUT_ENABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VD1_INPUT_ENABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VD1_INPUT_ENABLE_DISABLED                 _MK_ENUM_CONST(0)
+#define VI_PIN_INPUT_ENABLE_0_VD1_INPUT_ENABLE_ENABLED                  _MK_ENUM_CONST(1)
+
+// VD2 pin Input Enable  This bit controls VD2 pin input.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_INPUT_ENABLE_0_VD2_INPUT_ENABLE_SHIFT                    _MK_SHIFT_CONST(2)
+#define VI_PIN_INPUT_ENABLE_0_VD2_INPUT_ENABLE_FIELD                    (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_ENABLE_0_VD2_INPUT_ENABLE_SHIFT)
+#define VI_PIN_INPUT_ENABLE_0_VD2_INPUT_ENABLE_RANGE                    2:2
+#define VI_PIN_INPUT_ENABLE_0_VD2_INPUT_ENABLE_WOFFSET                  0x0
+#define VI_PIN_INPUT_ENABLE_0_VD2_INPUT_ENABLE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VD2_INPUT_ENABLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define VI_PIN_INPUT_ENABLE_0_VD2_INPUT_ENABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VD2_INPUT_ENABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VD2_INPUT_ENABLE_DISABLED                 _MK_ENUM_CONST(0)
+#define VI_PIN_INPUT_ENABLE_0_VD2_INPUT_ENABLE_ENABLED                  _MK_ENUM_CONST(1)
+
+// VD3 pin Input Enable  This bit controls VD3 pin input.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_INPUT_ENABLE_0_VD3_INPUT_ENABLE_SHIFT                    _MK_SHIFT_CONST(3)
+#define VI_PIN_INPUT_ENABLE_0_VD3_INPUT_ENABLE_FIELD                    (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_ENABLE_0_VD3_INPUT_ENABLE_SHIFT)
+#define VI_PIN_INPUT_ENABLE_0_VD3_INPUT_ENABLE_RANGE                    3:3
+#define VI_PIN_INPUT_ENABLE_0_VD3_INPUT_ENABLE_WOFFSET                  0x0
+#define VI_PIN_INPUT_ENABLE_0_VD3_INPUT_ENABLE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VD3_INPUT_ENABLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define VI_PIN_INPUT_ENABLE_0_VD3_INPUT_ENABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VD3_INPUT_ENABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VD3_INPUT_ENABLE_DISABLED                 _MK_ENUM_CONST(0)
+#define VI_PIN_INPUT_ENABLE_0_VD3_INPUT_ENABLE_ENABLED                  _MK_ENUM_CONST(1)
+
+// VD4 pin Input Enable  This bit controls VD4 pin input.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_INPUT_ENABLE_0_VD4_INPUT_ENABLE_SHIFT                    _MK_SHIFT_CONST(4)
+#define VI_PIN_INPUT_ENABLE_0_VD4_INPUT_ENABLE_FIELD                    (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_ENABLE_0_VD4_INPUT_ENABLE_SHIFT)
+#define VI_PIN_INPUT_ENABLE_0_VD4_INPUT_ENABLE_RANGE                    4:4
+#define VI_PIN_INPUT_ENABLE_0_VD4_INPUT_ENABLE_WOFFSET                  0x0
+#define VI_PIN_INPUT_ENABLE_0_VD4_INPUT_ENABLE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VD4_INPUT_ENABLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define VI_PIN_INPUT_ENABLE_0_VD4_INPUT_ENABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VD4_INPUT_ENABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VD4_INPUT_ENABLE_DISABLED                 _MK_ENUM_CONST(0)
+#define VI_PIN_INPUT_ENABLE_0_VD4_INPUT_ENABLE_ENABLED                  _MK_ENUM_CONST(1)
+
+// VD5 pin Input Enable  This bit controls VD5 pin input.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_INPUT_ENABLE_0_VD5_INPUT_ENABLE_SHIFT                    _MK_SHIFT_CONST(5)
+#define VI_PIN_INPUT_ENABLE_0_VD5_INPUT_ENABLE_FIELD                    (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_ENABLE_0_VD5_INPUT_ENABLE_SHIFT)
+#define VI_PIN_INPUT_ENABLE_0_VD5_INPUT_ENABLE_RANGE                    5:5
+#define VI_PIN_INPUT_ENABLE_0_VD5_INPUT_ENABLE_WOFFSET                  0x0
+#define VI_PIN_INPUT_ENABLE_0_VD5_INPUT_ENABLE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VD5_INPUT_ENABLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define VI_PIN_INPUT_ENABLE_0_VD5_INPUT_ENABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VD5_INPUT_ENABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VD5_INPUT_ENABLE_DISABLED                 _MK_ENUM_CONST(0)
+#define VI_PIN_INPUT_ENABLE_0_VD5_INPUT_ENABLE_ENABLED                  _MK_ENUM_CONST(1)
+
+// VD6 pin Input Enable  This bit controls VD6 pin input.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_INPUT_ENABLE_0_VD6_INPUT_ENABLE_SHIFT                    _MK_SHIFT_CONST(6)
+#define VI_PIN_INPUT_ENABLE_0_VD6_INPUT_ENABLE_FIELD                    (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_ENABLE_0_VD6_INPUT_ENABLE_SHIFT)
+#define VI_PIN_INPUT_ENABLE_0_VD6_INPUT_ENABLE_RANGE                    6:6
+#define VI_PIN_INPUT_ENABLE_0_VD6_INPUT_ENABLE_WOFFSET                  0x0
+#define VI_PIN_INPUT_ENABLE_0_VD6_INPUT_ENABLE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VD6_INPUT_ENABLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define VI_PIN_INPUT_ENABLE_0_VD6_INPUT_ENABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VD6_INPUT_ENABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VD6_INPUT_ENABLE_DISABLED                 _MK_ENUM_CONST(0)
+#define VI_PIN_INPUT_ENABLE_0_VD6_INPUT_ENABLE_ENABLED                  _MK_ENUM_CONST(1)
+
+// VD7 pin Input Enable  This bit controls VD7 pin input.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_INPUT_ENABLE_0_VD7_INPUT_ENABLE_SHIFT                    _MK_SHIFT_CONST(7)
+#define VI_PIN_INPUT_ENABLE_0_VD7_INPUT_ENABLE_FIELD                    (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_ENABLE_0_VD7_INPUT_ENABLE_SHIFT)
+#define VI_PIN_INPUT_ENABLE_0_VD7_INPUT_ENABLE_RANGE                    7:7
+#define VI_PIN_INPUT_ENABLE_0_VD7_INPUT_ENABLE_WOFFSET                  0x0
+#define VI_PIN_INPUT_ENABLE_0_VD7_INPUT_ENABLE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VD7_INPUT_ENABLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define VI_PIN_INPUT_ENABLE_0_VD7_INPUT_ENABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VD7_INPUT_ENABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VD7_INPUT_ENABLE_DISABLED                 _MK_ENUM_CONST(0)
+#define VI_PIN_INPUT_ENABLE_0_VD7_INPUT_ENABLE_ENABLED                  _MK_ENUM_CONST(1)
+
+// VD8 pin Input Enable  This bit controls VD7 pin input.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_INPUT_ENABLE_0_VD8_INPUT_ENABLE_SHIFT                    _MK_SHIFT_CONST(8)
+#define VI_PIN_INPUT_ENABLE_0_VD8_INPUT_ENABLE_FIELD                    (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_ENABLE_0_VD8_INPUT_ENABLE_SHIFT)
+#define VI_PIN_INPUT_ENABLE_0_VD8_INPUT_ENABLE_RANGE                    8:8
+#define VI_PIN_INPUT_ENABLE_0_VD8_INPUT_ENABLE_WOFFSET                  0x0
+#define VI_PIN_INPUT_ENABLE_0_VD8_INPUT_ENABLE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VD8_INPUT_ENABLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define VI_PIN_INPUT_ENABLE_0_VD8_INPUT_ENABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VD8_INPUT_ENABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VD8_INPUT_ENABLE_DISABLED                 _MK_ENUM_CONST(0)
+#define VI_PIN_INPUT_ENABLE_0_VD8_INPUT_ENABLE_ENABLED                  _MK_ENUM_CONST(1)
+
+// VD9 pin Input Enable  This bit controls VD7 pin input.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_INPUT_ENABLE_0_VD9_INPUT_ENABLE_SHIFT                    _MK_SHIFT_CONST(9)
+#define VI_PIN_INPUT_ENABLE_0_VD9_INPUT_ENABLE_FIELD                    (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_ENABLE_0_VD9_INPUT_ENABLE_SHIFT)
+#define VI_PIN_INPUT_ENABLE_0_VD9_INPUT_ENABLE_RANGE                    9:9
+#define VI_PIN_INPUT_ENABLE_0_VD9_INPUT_ENABLE_WOFFSET                  0x0
+#define VI_PIN_INPUT_ENABLE_0_VD9_INPUT_ENABLE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VD9_INPUT_ENABLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define VI_PIN_INPUT_ENABLE_0_VD9_INPUT_ENABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VD9_INPUT_ENABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VD9_INPUT_ENABLE_DISABLED                 _MK_ENUM_CONST(0)
+#define VI_PIN_INPUT_ENABLE_0_VD9_INPUT_ENABLE_ENABLED                  _MK_ENUM_CONST(1)
+
+// VD10 pin Input Enable  This bit controls VD7 pin input.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_INPUT_ENABLE_0_VD10_INPUT_ENABLE_SHIFT                   _MK_SHIFT_CONST(10)
+#define VI_PIN_INPUT_ENABLE_0_VD10_INPUT_ENABLE_FIELD                   (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_ENABLE_0_VD10_INPUT_ENABLE_SHIFT)
+#define VI_PIN_INPUT_ENABLE_0_VD10_INPUT_ENABLE_RANGE                   10:10
+#define VI_PIN_INPUT_ENABLE_0_VD10_INPUT_ENABLE_WOFFSET                 0x0
+#define VI_PIN_INPUT_ENABLE_0_VD10_INPUT_ENABLE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VD10_INPUT_ENABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define VI_PIN_INPUT_ENABLE_0_VD10_INPUT_ENABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VD10_INPUT_ENABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VD10_INPUT_ENABLE_DISABLED                        _MK_ENUM_CONST(0)
+#define VI_PIN_INPUT_ENABLE_0_VD10_INPUT_ENABLE_ENABLED                 _MK_ENUM_CONST(1)
+
+// VD11 pin Input Enable  This bit controls VD7 pin input.
+//   0= Disabled
+//   1= Enabled
+// 12 reserved
+#define VI_PIN_INPUT_ENABLE_0_VD11_INPUT_ENABLE_SHIFT                   _MK_SHIFT_CONST(11)
+#define VI_PIN_INPUT_ENABLE_0_VD11_INPUT_ENABLE_FIELD                   (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_ENABLE_0_VD11_INPUT_ENABLE_SHIFT)
+#define VI_PIN_INPUT_ENABLE_0_VD11_INPUT_ENABLE_RANGE                   11:11
+#define VI_PIN_INPUT_ENABLE_0_VD11_INPUT_ENABLE_WOFFSET                 0x0
+#define VI_PIN_INPUT_ENABLE_0_VD11_INPUT_ENABLE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VD11_INPUT_ENABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define VI_PIN_INPUT_ENABLE_0_VD11_INPUT_ENABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VD11_INPUT_ENABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VD11_INPUT_ENABLE_DISABLED                        _MK_ENUM_CONST(0)
+#define VI_PIN_INPUT_ENABLE_0_VD11_INPUT_ENABLE_ENABLED                 _MK_ENUM_CONST(1)
+
+// VHS pin Input Enable  This bit controls VHS pin input.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_INPUT_ENABLE_0_VHS_INPUT_ENABLE_SHIFT                    _MK_SHIFT_CONST(13)
+#define VI_PIN_INPUT_ENABLE_0_VHS_INPUT_ENABLE_FIELD                    (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_ENABLE_0_VHS_INPUT_ENABLE_SHIFT)
+#define VI_PIN_INPUT_ENABLE_0_VHS_INPUT_ENABLE_RANGE                    13:13
+#define VI_PIN_INPUT_ENABLE_0_VHS_INPUT_ENABLE_WOFFSET                  0x0
+#define VI_PIN_INPUT_ENABLE_0_VHS_INPUT_ENABLE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VHS_INPUT_ENABLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define VI_PIN_INPUT_ENABLE_0_VHS_INPUT_ENABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VHS_INPUT_ENABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VHS_INPUT_ENABLE_DISABLED                 _MK_ENUM_CONST(0)
+#define VI_PIN_INPUT_ENABLE_0_VHS_INPUT_ENABLE_ENABLED                  _MK_ENUM_CONST(1)
+
+// VVS pin Input Enable  This bit controls VVS pin input.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_INPUT_ENABLE_0_VVS_INPUT_ENABLE_SHIFT                    _MK_SHIFT_CONST(14)
+#define VI_PIN_INPUT_ENABLE_0_VVS_INPUT_ENABLE_FIELD                    (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_ENABLE_0_VVS_INPUT_ENABLE_SHIFT)
+#define VI_PIN_INPUT_ENABLE_0_VVS_INPUT_ENABLE_RANGE                    14:14
+#define VI_PIN_INPUT_ENABLE_0_VVS_INPUT_ENABLE_WOFFSET                  0x0
+#define VI_PIN_INPUT_ENABLE_0_VVS_INPUT_ENABLE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VVS_INPUT_ENABLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define VI_PIN_INPUT_ENABLE_0_VVS_INPUT_ENABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VVS_INPUT_ENABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VVS_INPUT_ENABLE_DISABLED                 _MK_ENUM_CONST(0)
+#define VI_PIN_INPUT_ENABLE_0_VVS_INPUT_ENABLE_ENABLED                  _MK_ENUM_CONST(1)
+
+// VGP0 pin Input Enable  This bit controls VGP0 pin input.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_INPUT_ENABLE_0_VGP0_INPUT_ENABLE_SHIFT                   _MK_SHIFT_CONST(15)
+#define VI_PIN_INPUT_ENABLE_0_VGP0_INPUT_ENABLE_FIELD                   (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_ENABLE_0_VGP0_INPUT_ENABLE_SHIFT)
+#define VI_PIN_INPUT_ENABLE_0_VGP0_INPUT_ENABLE_RANGE                   15:15
+#define VI_PIN_INPUT_ENABLE_0_VGP0_INPUT_ENABLE_WOFFSET                 0x0
+#define VI_PIN_INPUT_ENABLE_0_VGP0_INPUT_ENABLE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VGP0_INPUT_ENABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define VI_PIN_INPUT_ENABLE_0_VGP0_INPUT_ENABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VGP0_INPUT_ENABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VGP0_INPUT_ENABLE_DISABLED                        _MK_ENUM_CONST(0)
+#define VI_PIN_INPUT_ENABLE_0_VGP0_INPUT_ENABLE_ENABLED                 _MK_ENUM_CONST(1)
+
+// VGP1 pin Input Enable  This bit controls VGP1 pin input.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_INPUT_ENABLE_0_VGP1_INPUT_ENABLE_SHIFT                   _MK_SHIFT_CONST(16)
+#define VI_PIN_INPUT_ENABLE_0_VGP1_INPUT_ENABLE_FIELD                   (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_ENABLE_0_VGP1_INPUT_ENABLE_SHIFT)
+#define VI_PIN_INPUT_ENABLE_0_VGP1_INPUT_ENABLE_RANGE                   16:16
+#define VI_PIN_INPUT_ENABLE_0_VGP1_INPUT_ENABLE_WOFFSET                 0x0
+#define VI_PIN_INPUT_ENABLE_0_VGP1_INPUT_ENABLE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VGP1_INPUT_ENABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define VI_PIN_INPUT_ENABLE_0_VGP1_INPUT_ENABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VGP1_INPUT_ENABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VGP1_INPUT_ENABLE_DISABLED                        _MK_ENUM_CONST(0)
+#define VI_PIN_INPUT_ENABLE_0_VGP1_INPUT_ENABLE_ENABLED                 _MK_ENUM_CONST(1)
+
+// VGP2 pin Input Enable  This bit controls VGP2 pin input.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_INPUT_ENABLE_0_VGP2_INPUT_ENABLE_SHIFT                   _MK_SHIFT_CONST(17)
+#define VI_PIN_INPUT_ENABLE_0_VGP2_INPUT_ENABLE_FIELD                   (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_ENABLE_0_VGP2_INPUT_ENABLE_SHIFT)
+#define VI_PIN_INPUT_ENABLE_0_VGP2_INPUT_ENABLE_RANGE                   17:17
+#define VI_PIN_INPUT_ENABLE_0_VGP2_INPUT_ENABLE_WOFFSET                 0x0
+#define VI_PIN_INPUT_ENABLE_0_VGP2_INPUT_ENABLE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VGP2_INPUT_ENABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define VI_PIN_INPUT_ENABLE_0_VGP2_INPUT_ENABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VGP2_INPUT_ENABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VGP2_INPUT_ENABLE_DISABLED                        _MK_ENUM_CONST(0)
+#define VI_PIN_INPUT_ENABLE_0_VGP2_INPUT_ENABLE_ENABLED                 _MK_ENUM_CONST(1)
+
+// VGP3 pin Input Enable  This bit controls VGP3 pin input.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_INPUT_ENABLE_0_VGP3_INPUT_ENABLE_SHIFT                   _MK_SHIFT_CONST(18)
+#define VI_PIN_INPUT_ENABLE_0_VGP3_INPUT_ENABLE_FIELD                   (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_ENABLE_0_VGP3_INPUT_ENABLE_SHIFT)
+#define VI_PIN_INPUT_ENABLE_0_VGP3_INPUT_ENABLE_RANGE                   18:18
+#define VI_PIN_INPUT_ENABLE_0_VGP3_INPUT_ENABLE_WOFFSET                 0x0
+#define VI_PIN_INPUT_ENABLE_0_VGP3_INPUT_ENABLE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VGP3_INPUT_ENABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define VI_PIN_INPUT_ENABLE_0_VGP3_INPUT_ENABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VGP3_INPUT_ENABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VGP3_INPUT_ENABLE_DISABLED                        _MK_ENUM_CONST(0)
+#define VI_PIN_INPUT_ENABLE_0_VGP3_INPUT_ENABLE_ENABLED                 _MK_ENUM_CONST(1)
+
+// VGP4 pin Input Enable  This bit controls VGP4 pin input.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_INPUT_ENABLE_0_VGP4_INPUT_ENABLE_SHIFT                   _MK_SHIFT_CONST(19)
+#define VI_PIN_INPUT_ENABLE_0_VGP4_INPUT_ENABLE_FIELD                   (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_ENABLE_0_VGP4_INPUT_ENABLE_SHIFT)
+#define VI_PIN_INPUT_ENABLE_0_VGP4_INPUT_ENABLE_RANGE                   19:19
+#define VI_PIN_INPUT_ENABLE_0_VGP4_INPUT_ENABLE_WOFFSET                 0x0
+#define VI_PIN_INPUT_ENABLE_0_VGP4_INPUT_ENABLE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VGP4_INPUT_ENABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define VI_PIN_INPUT_ENABLE_0_VGP4_INPUT_ENABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VGP4_INPUT_ENABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VGP4_INPUT_ENABLE_DISABLED                        _MK_ENUM_CONST(0)
+#define VI_PIN_INPUT_ENABLE_0_VGP4_INPUT_ENABLE_ENABLED                 _MK_ENUM_CONST(1)
+
+// VGP5 pin Input Enable  This bit controls VGP5 pin input.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_INPUT_ENABLE_0_VGP5_INPUT_ENABLE_SHIFT                   _MK_SHIFT_CONST(20)
+#define VI_PIN_INPUT_ENABLE_0_VGP5_INPUT_ENABLE_FIELD                   (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_ENABLE_0_VGP5_INPUT_ENABLE_SHIFT)
+#define VI_PIN_INPUT_ENABLE_0_VGP5_INPUT_ENABLE_RANGE                   20:20
+#define VI_PIN_INPUT_ENABLE_0_VGP5_INPUT_ENABLE_WOFFSET                 0x0
+#define VI_PIN_INPUT_ENABLE_0_VGP5_INPUT_ENABLE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VGP5_INPUT_ENABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define VI_PIN_INPUT_ENABLE_0_VGP5_INPUT_ENABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VGP5_INPUT_ENABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VGP5_INPUT_ENABLE_DISABLED                        _MK_ENUM_CONST(0)
+#define VI_PIN_INPUT_ENABLE_0_VGP5_INPUT_ENABLE_ENABLED                 _MK_ENUM_CONST(1)
+
+// VGP6 pin Input Enable  This bit controls VGP6 pin input.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_INPUT_ENABLE_0_VGP6_INPUT_ENABLE_SHIFT                   _MK_SHIFT_CONST(21)
+#define VI_PIN_INPUT_ENABLE_0_VGP6_INPUT_ENABLE_FIELD                   (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_ENABLE_0_VGP6_INPUT_ENABLE_SHIFT)
+#define VI_PIN_INPUT_ENABLE_0_VGP6_INPUT_ENABLE_RANGE                   21:21
+#define VI_PIN_INPUT_ENABLE_0_VGP6_INPUT_ENABLE_WOFFSET                 0x0
+#define VI_PIN_INPUT_ENABLE_0_VGP6_INPUT_ENABLE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VGP6_INPUT_ENABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define VI_PIN_INPUT_ENABLE_0_VGP6_INPUT_ENABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VGP6_INPUT_ENABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VGP6_INPUT_ENABLE_DISABLED                        _MK_ENUM_CONST(0)
+#define VI_PIN_INPUT_ENABLE_0_VGP6_INPUT_ENABLE_ENABLED                 _MK_ENUM_CONST(1)
+
+
+// Register VI_PIN_OUTPUT_ENABLE_0  // VI pins Output Enable
+#define VI_PIN_OUTPUT_ENABLE_0                  _MK_ADDR_CONST(0x5c)
+#define VI_PIN_OUTPUT_ENABLE_0_WORD_COUNT                       0x1
+#define VI_PIN_OUTPUT_ENABLE_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_RESET_MASK                       _MK_MASK_CONST(0x3fffff)
+#define VI_PIN_OUTPUT_ENABLE_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_READ_MASK                        _MK_MASK_CONST(0x3fffff)
+#define VI_PIN_OUTPUT_ENABLE_0_WRITE_MASK                       _MK_MASK_CONST(0x3fffff)
+// VD0 pin Output Enable  This bit controls VD0 pin output.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_OUTPUT_ENABLE_0_VD0_OUTPUT_ENABLE_SHIFT                  _MK_SHIFT_CONST(0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD0_OUTPUT_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_ENABLE_0_VD0_OUTPUT_ENABLE_SHIFT)
+#define VI_PIN_OUTPUT_ENABLE_0_VD0_OUTPUT_ENABLE_RANGE                  0:0
+#define VI_PIN_OUTPUT_ENABLE_0_VD0_OUTPUT_ENABLE_WOFFSET                        0x0
+#define VI_PIN_OUTPUT_ENABLE_0_VD0_OUTPUT_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD0_OUTPUT_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_ENABLE_0_VD0_OUTPUT_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD0_OUTPUT_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD0_OUTPUT_ENABLE_DISABLED                       _MK_ENUM_CONST(0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD0_OUTPUT_ENABLE_ENABLED                        _MK_ENUM_CONST(1)
+
+// VD1 pin Output Enable  This bit controls VD1 pin output.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_OUTPUT_ENABLE_0_VD1_OUTPUT_ENABLE_SHIFT                  _MK_SHIFT_CONST(1)
+#define VI_PIN_OUTPUT_ENABLE_0_VD1_OUTPUT_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_ENABLE_0_VD1_OUTPUT_ENABLE_SHIFT)
+#define VI_PIN_OUTPUT_ENABLE_0_VD1_OUTPUT_ENABLE_RANGE                  1:1
+#define VI_PIN_OUTPUT_ENABLE_0_VD1_OUTPUT_ENABLE_WOFFSET                        0x0
+#define VI_PIN_OUTPUT_ENABLE_0_VD1_OUTPUT_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD1_OUTPUT_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_ENABLE_0_VD1_OUTPUT_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD1_OUTPUT_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD1_OUTPUT_ENABLE_DISABLED                       _MK_ENUM_CONST(0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD1_OUTPUT_ENABLE_ENABLED                        _MK_ENUM_CONST(1)
+
+// VD2 pin Output Enable  This bit controls VD2 pin output.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_OUTPUT_ENABLE_0_VD2_OUTPUT_ENABLE_SHIFT                  _MK_SHIFT_CONST(2)
+#define VI_PIN_OUTPUT_ENABLE_0_VD2_OUTPUT_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_ENABLE_0_VD2_OUTPUT_ENABLE_SHIFT)
+#define VI_PIN_OUTPUT_ENABLE_0_VD2_OUTPUT_ENABLE_RANGE                  2:2
+#define VI_PIN_OUTPUT_ENABLE_0_VD2_OUTPUT_ENABLE_WOFFSET                        0x0
+#define VI_PIN_OUTPUT_ENABLE_0_VD2_OUTPUT_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD2_OUTPUT_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_ENABLE_0_VD2_OUTPUT_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD2_OUTPUT_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD2_OUTPUT_ENABLE_DISABLED                       _MK_ENUM_CONST(0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD2_OUTPUT_ENABLE_ENABLED                        _MK_ENUM_CONST(1)
+
+// VD3 pin Output Enable  This bit controls VD3 pin output.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_OUTPUT_ENABLE_0_VD3_OUTPUT_ENABLE_SHIFT                  _MK_SHIFT_CONST(3)
+#define VI_PIN_OUTPUT_ENABLE_0_VD3_OUTPUT_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_ENABLE_0_VD3_OUTPUT_ENABLE_SHIFT)
+#define VI_PIN_OUTPUT_ENABLE_0_VD3_OUTPUT_ENABLE_RANGE                  3:3
+#define VI_PIN_OUTPUT_ENABLE_0_VD3_OUTPUT_ENABLE_WOFFSET                        0x0
+#define VI_PIN_OUTPUT_ENABLE_0_VD3_OUTPUT_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD3_OUTPUT_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_ENABLE_0_VD3_OUTPUT_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD3_OUTPUT_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD3_OUTPUT_ENABLE_DISABLED                       _MK_ENUM_CONST(0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD3_OUTPUT_ENABLE_ENABLED                        _MK_ENUM_CONST(1)
+
+// VD4 pin Output Enable  This bit controls VD4 pin output.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_OUTPUT_ENABLE_0_VD4_OUTPUT_ENABLE_SHIFT                  _MK_SHIFT_CONST(4)
+#define VI_PIN_OUTPUT_ENABLE_0_VD4_OUTPUT_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_ENABLE_0_VD4_OUTPUT_ENABLE_SHIFT)
+#define VI_PIN_OUTPUT_ENABLE_0_VD4_OUTPUT_ENABLE_RANGE                  4:4
+#define VI_PIN_OUTPUT_ENABLE_0_VD4_OUTPUT_ENABLE_WOFFSET                        0x0
+#define VI_PIN_OUTPUT_ENABLE_0_VD4_OUTPUT_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD4_OUTPUT_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_ENABLE_0_VD4_OUTPUT_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD4_OUTPUT_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD4_OUTPUT_ENABLE_DISABLED                       _MK_ENUM_CONST(0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD4_OUTPUT_ENABLE_ENABLED                        _MK_ENUM_CONST(1)
+
+// VD5 pin Output Enable  This bit controls VD5 pin output.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_OUTPUT_ENABLE_0_VD5_OUTPUT_ENABLE_SHIFT                  _MK_SHIFT_CONST(5)
+#define VI_PIN_OUTPUT_ENABLE_0_VD5_OUTPUT_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_ENABLE_0_VD5_OUTPUT_ENABLE_SHIFT)
+#define VI_PIN_OUTPUT_ENABLE_0_VD5_OUTPUT_ENABLE_RANGE                  5:5
+#define VI_PIN_OUTPUT_ENABLE_0_VD5_OUTPUT_ENABLE_WOFFSET                        0x0
+#define VI_PIN_OUTPUT_ENABLE_0_VD5_OUTPUT_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD5_OUTPUT_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_ENABLE_0_VD5_OUTPUT_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD5_OUTPUT_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD5_OUTPUT_ENABLE_DISABLED                       _MK_ENUM_CONST(0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD5_OUTPUT_ENABLE_ENABLED                        _MK_ENUM_CONST(1)
+
+// VD6 pin Output Enable  This bit controls VD6 pin output.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_OUTPUT_ENABLE_0_VD6_OUTPUT_ENABLE_SHIFT                  _MK_SHIFT_CONST(6)
+#define VI_PIN_OUTPUT_ENABLE_0_VD6_OUTPUT_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_ENABLE_0_VD6_OUTPUT_ENABLE_SHIFT)
+#define VI_PIN_OUTPUT_ENABLE_0_VD6_OUTPUT_ENABLE_RANGE                  6:6
+#define VI_PIN_OUTPUT_ENABLE_0_VD6_OUTPUT_ENABLE_WOFFSET                        0x0
+#define VI_PIN_OUTPUT_ENABLE_0_VD6_OUTPUT_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD6_OUTPUT_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_ENABLE_0_VD6_OUTPUT_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD6_OUTPUT_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD6_OUTPUT_ENABLE_DISABLED                       _MK_ENUM_CONST(0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD6_OUTPUT_ENABLE_ENABLED                        _MK_ENUM_CONST(1)
+
+// VD7 pin Output Enable  This bit controls VD7 pin output.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_OUTPUT_ENABLE_0_VD7_OUTPUT_ENABLE_SHIFT                  _MK_SHIFT_CONST(7)
+#define VI_PIN_OUTPUT_ENABLE_0_VD7_OUTPUT_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_ENABLE_0_VD7_OUTPUT_ENABLE_SHIFT)
+#define VI_PIN_OUTPUT_ENABLE_0_VD7_OUTPUT_ENABLE_RANGE                  7:7
+#define VI_PIN_OUTPUT_ENABLE_0_VD7_OUTPUT_ENABLE_WOFFSET                        0x0
+#define VI_PIN_OUTPUT_ENABLE_0_VD7_OUTPUT_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD7_OUTPUT_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_ENABLE_0_VD7_OUTPUT_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD7_OUTPUT_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD7_OUTPUT_ENABLE_DISABLED                       _MK_ENUM_CONST(0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD7_OUTPUT_ENABLE_ENABLED                        _MK_ENUM_CONST(1)
+
+// VD8 pin Output Enable  This bit controls VD7 pin output.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_OUTPUT_ENABLE_0_VD8_OUTPUT_ENABLE_SHIFT                  _MK_SHIFT_CONST(8)
+#define VI_PIN_OUTPUT_ENABLE_0_VD8_OUTPUT_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_ENABLE_0_VD8_OUTPUT_ENABLE_SHIFT)
+#define VI_PIN_OUTPUT_ENABLE_0_VD8_OUTPUT_ENABLE_RANGE                  8:8
+#define VI_PIN_OUTPUT_ENABLE_0_VD8_OUTPUT_ENABLE_WOFFSET                        0x0
+#define VI_PIN_OUTPUT_ENABLE_0_VD8_OUTPUT_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD8_OUTPUT_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_ENABLE_0_VD8_OUTPUT_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD8_OUTPUT_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD8_OUTPUT_ENABLE_DISABLED                       _MK_ENUM_CONST(0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD8_OUTPUT_ENABLE_ENABLED                        _MK_ENUM_CONST(1)
+
+// VD9 pin Output Enable  This bit controls VD7 pin output.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_OUTPUT_ENABLE_0_VD9_OUTPUT_ENABLE_SHIFT                  _MK_SHIFT_CONST(9)
+#define VI_PIN_OUTPUT_ENABLE_0_VD9_OUTPUT_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_ENABLE_0_VD9_OUTPUT_ENABLE_SHIFT)
+#define VI_PIN_OUTPUT_ENABLE_0_VD9_OUTPUT_ENABLE_RANGE                  9:9
+#define VI_PIN_OUTPUT_ENABLE_0_VD9_OUTPUT_ENABLE_WOFFSET                        0x0
+#define VI_PIN_OUTPUT_ENABLE_0_VD9_OUTPUT_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD9_OUTPUT_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_ENABLE_0_VD9_OUTPUT_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD9_OUTPUT_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD9_OUTPUT_ENABLE_DISABLED                       _MK_ENUM_CONST(0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD9_OUTPUT_ENABLE_ENABLED                        _MK_ENUM_CONST(1)
+
+// VD10 pin Output Enable  This bit controls VD7 pin output.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_OUTPUT_ENABLE_0_VD10_OUTPUT_ENABLE_SHIFT                 _MK_SHIFT_CONST(10)
+#define VI_PIN_OUTPUT_ENABLE_0_VD10_OUTPUT_ENABLE_FIELD                 (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_ENABLE_0_VD10_OUTPUT_ENABLE_SHIFT)
+#define VI_PIN_OUTPUT_ENABLE_0_VD10_OUTPUT_ENABLE_RANGE                 10:10
+#define VI_PIN_OUTPUT_ENABLE_0_VD10_OUTPUT_ENABLE_WOFFSET                       0x0
+#define VI_PIN_OUTPUT_ENABLE_0_VD10_OUTPUT_ENABLE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD10_OUTPUT_ENABLE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_ENABLE_0_VD10_OUTPUT_ENABLE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD10_OUTPUT_ENABLE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD10_OUTPUT_ENABLE_DISABLED                      _MK_ENUM_CONST(0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD10_OUTPUT_ENABLE_ENABLED                       _MK_ENUM_CONST(1)
+
+// VD11 pin Output Enable  This bit controls VD7 pin output.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_OUTPUT_ENABLE_0_VD11_OUTPUT_ENABLE_SHIFT                 _MK_SHIFT_CONST(11)
+#define VI_PIN_OUTPUT_ENABLE_0_VD11_OUTPUT_ENABLE_FIELD                 (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_ENABLE_0_VD11_OUTPUT_ENABLE_SHIFT)
+#define VI_PIN_OUTPUT_ENABLE_0_VD11_OUTPUT_ENABLE_RANGE                 11:11
+#define VI_PIN_OUTPUT_ENABLE_0_VD11_OUTPUT_ENABLE_WOFFSET                       0x0
+#define VI_PIN_OUTPUT_ENABLE_0_VD11_OUTPUT_ENABLE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD11_OUTPUT_ENABLE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_ENABLE_0_VD11_OUTPUT_ENABLE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD11_OUTPUT_ENABLE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD11_OUTPUT_ENABLE_DISABLED                      _MK_ENUM_CONST(0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD11_OUTPUT_ENABLE_ENABLED                       _MK_ENUM_CONST(1)
+
+// VSCK pin Output Enable  This bit controls VSCK pin output.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_OUTPUT_ENABLE_0_VSCK_OUTPUT_ENABLE_SHIFT                 _MK_SHIFT_CONST(12)
+#define VI_PIN_OUTPUT_ENABLE_0_VSCK_OUTPUT_ENABLE_FIELD                 (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_ENABLE_0_VSCK_OUTPUT_ENABLE_SHIFT)
+#define VI_PIN_OUTPUT_ENABLE_0_VSCK_OUTPUT_ENABLE_RANGE                 12:12
+#define VI_PIN_OUTPUT_ENABLE_0_VSCK_OUTPUT_ENABLE_WOFFSET                       0x0
+#define VI_PIN_OUTPUT_ENABLE_0_VSCK_OUTPUT_ENABLE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VSCK_OUTPUT_ENABLE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_ENABLE_0_VSCK_OUTPUT_ENABLE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VSCK_OUTPUT_ENABLE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VSCK_OUTPUT_ENABLE_DISABLED                      _MK_ENUM_CONST(0)
+#define VI_PIN_OUTPUT_ENABLE_0_VSCK_OUTPUT_ENABLE_ENABLED                       _MK_ENUM_CONST(1)
+
+// VHS pin Output Enable  This bit controls VHS pin output.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_OUTPUT_ENABLE_0_VHS_OUTPUT_ENABLE_SHIFT                  _MK_SHIFT_CONST(13)
+#define VI_PIN_OUTPUT_ENABLE_0_VHS_OUTPUT_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_ENABLE_0_VHS_OUTPUT_ENABLE_SHIFT)
+#define VI_PIN_OUTPUT_ENABLE_0_VHS_OUTPUT_ENABLE_RANGE                  13:13
+#define VI_PIN_OUTPUT_ENABLE_0_VHS_OUTPUT_ENABLE_WOFFSET                        0x0
+#define VI_PIN_OUTPUT_ENABLE_0_VHS_OUTPUT_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VHS_OUTPUT_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_ENABLE_0_VHS_OUTPUT_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VHS_OUTPUT_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VHS_OUTPUT_ENABLE_DISABLED                       _MK_ENUM_CONST(0)
+#define VI_PIN_OUTPUT_ENABLE_0_VHS_OUTPUT_ENABLE_ENABLED                        _MK_ENUM_CONST(1)
+
+// VVS pin Output Enable  This bit controls VVS pin output.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_OUTPUT_ENABLE_0_VVS_OUTPUT_ENABLE_SHIFT                  _MK_SHIFT_CONST(14)
+#define VI_PIN_OUTPUT_ENABLE_0_VVS_OUTPUT_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_ENABLE_0_VVS_OUTPUT_ENABLE_SHIFT)
+#define VI_PIN_OUTPUT_ENABLE_0_VVS_OUTPUT_ENABLE_RANGE                  14:14
+#define VI_PIN_OUTPUT_ENABLE_0_VVS_OUTPUT_ENABLE_WOFFSET                        0x0
+#define VI_PIN_OUTPUT_ENABLE_0_VVS_OUTPUT_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VVS_OUTPUT_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_ENABLE_0_VVS_OUTPUT_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VVS_OUTPUT_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VVS_OUTPUT_ENABLE_DISABLED                       _MK_ENUM_CONST(0)
+#define VI_PIN_OUTPUT_ENABLE_0_VVS_OUTPUT_ENABLE_ENABLED                        _MK_ENUM_CONST(1)
+
+// VGP0 pin Output Enable  This bit controls VGP0 pin output.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_OUTPUT_ENABLE_0_VGP0_OUTPUT_ENABLE_SHIFT                 _MK_SHIFT_CONST(15)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP0_OUTPUT_ENABLE_FIELD                 (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_ENABLE_0_VGP0_OUTPUT_ENABLE_SHIFT)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP0_OUTPUT_ENABLE_RANGE                 15:15
+#define VI_PIN_OUTPUT_ENABLE_0_VGP0_OUTPUT_ENABLE_WOFFSET                       0x0
+#define VI_PIN_OUTPUT_ENABLE_0_VGP0_OUTPUT_ENABLE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP0_OUTPUT_ENABLE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP0_OUTPUT_ENABLE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP0_OUTPUT_ENABLE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP0_OUTPUT_ENABLE_DISABLED                      _MK_ENUM_CONST(0)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP0_OUTPUT_ENABLE_ENABLED                       _MK_ENUM_CONST(1)
+
+// VGP1 pin Output Enable  This bit controls VGP1 pin output.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_OUTPUT_ENABLE_0_VGP1_OUTPUT_ENABLE_SHIFT                 _MK_SHIFT_CONST(16)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP1_OUTPUT_ENABLE_FIELD                 (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_ENABLE_0_VGP1_OUTPUT_ENABLE_SHIFT)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP1_OUTPUT_ENABLE_RANGE                 16:16
+#define VI_PIN_OUTPUT_ENABLE_0_VGP1_OUTPUT_ENABLE_WOFFSET                       0x0
+#define VI_PIN_OUTPUT_ENABLE_0_VGP1_OUTPUT_ENABLE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP1_OUTPUT_ENABLE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP1_OUTPUT_ENABLE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP1_OUTPUT_ENABLE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP1_OUTPUT_ENABLE_DISABLED                      _MK_ENUM_CONST(0)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP1_OUTPUT_ENABLE_ENABLED                       _MK_ENUM_CONST(1)
+
+// VGP2 pin Output Enable  This bit controls VGP2 pin output.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_OUTPUT_ENABLE_0_VGP2_OUTPUT_ENABLE_SHIFT                 _MK_SHIFT_CONST(17)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP2_OUTPUT_ENABLE_FIELD                 (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_ENABLE_0_VGP2_OUTPUT_ENABLE_SHIFT)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP2_OUTPUT_ENABLE_RANGE                 17:17
+#define VI_PIN_OUTPUT_ENABLE_0_VGP2_OUTPUT_ENABLE_WOFFSET                       0x0
+#define VI_PIN_OUTPUT_ENABLE_0_VGP2_OUTPUT_ENABLE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP2_OUTPUT_ENABLE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP2_OUTPUT_ENABLE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP2_OUTPUT_ENABLE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP2_OUTPUT_ENABLE_DISABLED                      _MK_ENUM_CONST(0)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP2_OUTPUT_ENABLE_ENABLED                       _MK_ENUM_CONST(1)
+
+// VGP3 pin Output Enable  This bit controls VGP3 pin output.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_OUTPUT_ENABLE_0_VGP3_OUTPUT_ENABLE_SHIFT                 _MK_SHIFT_CONST(18)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP3_OUTPUT_ENABLE_FIELD                 (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_ENABLE_0_VGP3_OUTPUT_ENABLE_SHIFT)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP3_OUTPUT_ENABLE_RANGE                 18:18
+#define VI_PIN_OUTPUT_ENABLE_0_VGP3_OUTPUT_ENABLE_WOFFSET                       0x0
+#define VI_PIN_OUTPUT_ENABLE_0_VGP3_OUTPUT_ENABLE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP3_OUTPUT_ENABLE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP3_OUTPUT_ENABLE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP3_OUTPUT_ENABLE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP3_OUTPUT_ENABLE_DISABLED                      _MK_ENUM_CONST(0)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP3_OUTPUT_ENABLE_ENABLED                       _MK_ENUM_CONST(1)
+
+// VGP4 pin Output Enable  This bit controls VGP4 pin output.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_OUTPUT_ENABLE_0_VGP4_OUTPUT_ENABLE_SHIFT                 _MK_SHIFT_CONST(19)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP4_OUTPUT_ENABLE_FIELD                 (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_ENABLE_0_VGP4_OUTPUT_ENABLE_SHIFT)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP4_OUTPUT_ENABLE_RANGE                 19:19
+#define VI_PIN_OUTPUT_ENABLE_0_VGP4_OUTPUT_ENABLE_WOFFSET                       0x0
+#define VI_PIN_OUTPUT_ENABLE_0_VGP4_OUTPUT_ENABLE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP4_OUTPUT_ENABLE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP4_OUTPUT_ENABLE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP4_OUTPUT_ENABLE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP4_OUTPUT_ENABLE_DISABLED                      _MK_ENUM_CONST(0)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP4_OUTPUT_ENABLE_ENABLED                       _MK_ENUM_CONST(1)
+
+// VGP5 pin Output Enable  This bit controls VGP5 pin output.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_OUTPUT_ENABLE_0_VGP5_OUTPUT_ENABLE_SHIFT                 _MK_SHIFT_CONST(20)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP5_OUTPUT_ENABLE_FIELD                 (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_ENABLE_0_VGP5_OUTPUT_ENABLE_SHIFT)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP5_OUTPUT_ENABLE_RANGE                 20:20
+#define VI_PIN_OUTPUT_ENABLE_0_VGP5_OUTPUT_ENABLE_WOFFSET                       0x0
+#define VI_PIN_OUTPUT_ENABLE_0_VGP5_OUTPUT_ENABLE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP5_OUTPUT_ENABLE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP5_OUTPUT_ENABLE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP5_OUTPUT_ENABLE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP5_OUTPUT_ENABLE_DISABLED                      _MK_ENUM_CONST(0)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP5_OUTPUT_ENABLE_ENABLED                       _MK_ENUM_CONST(1)
+
+// VGP6 pin Output Enable  This bit controls VGP6 pin output.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_OUTPUT_ENABLE_0_VGP6_OUTPUT_ENABLE_SHIFT                 _MK_SHIFT_CONST(21)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP6_OUTPUT_ENABLE_FIELD                 (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_ENABLE_0_VGP6_OUTPUT_ENABLE_SHIFT)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP6_OUTPUT_ENABLE_RANGE                 21:21
+#define VI_PIN_OUTPUT_ENABLE_0_VGP6_OUTPUT_ENABLE_WOFFSET                       0x0
+#define VI_PIN_OUTPUT_ENABLE_0_VGP6_OUTPUT_ENABLE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP6_OUTPUT_ENABLE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP6_OUTPUT_ENABLE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP6_OUTPUT_ENABLE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP6_OUTPUT_ENABLE_DISABLED                      _MK_ENUM_CONST(0)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP6_OUTPUT_ENABLE_ENABLED                       _MK_ENUM_CONST(1)
+
+
+// Register VI_PIN_INVERSION_0  // VI pins input/output Inversion
+//    0  reserved
+#define VI_PIN_INVERSION_0                      _MK_ADDR_CONST(0x5d)
+#define VI_PIN_INVERSION_0_WORD_COUNT                   0x1
+#define VI_PIN_INVERSION_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define VI_PIN_INVERSION_0_RESET_MASK                   _MK_MASK_CONST(0x70006)
+#define VI_PIN_INVERSION_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define VI_PIN_INVERSION_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_PIN_INVERSION_0_READ_MASK                    _MK_MASK_CONST(0x70006)
+#define VI_PIN_INVERSION_0_WRITE_MASK                   _MK_MASK_CONST(0x70006)
+// VHS pin Input Inversion   0= VHS input is not inverted
+//      (VHS input is active high)
+//   1= VHS input is inverted
+//      (VHS input is active low)
+#define VI_PIN_INVERSION_0_VHS_IN_INVERSION_SHIFT                       _MK_SHIFT_CONST(1)
+#define VI_PIN_INVERSION_0_VHS_IN_INVERSION_FIELD                       (_MK_MASK_CONST(0x1) << VI_PIN_INVERSION_0_VHS_IN_INVERSION_SHIFT)
+#define VI_PIN_INVERSION_0_VHS_IN_INVERSION_RANGE                       1:1
+#define VI_PIN_INVERSION_0_VHS_IN_INVERSION_WOFFSET                     0x0
+#define VI_PIN_INVERSION_0_VHS_IN_INVERSION_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_PIN_INVERSION_0_VHS_IN_INVERSION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define VI_PIN_INVERSION_0_VHS_IN_INVERSION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_PIN_INVERSION_0_VHS_IN_INVERSION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_PIN_INVERSION_0_VHS_IN_INVERSION_DISABLED                    _MK_ENUM_CONST(0)
+#define VI_PIN_INVERSION_0_VHS_IN_INVERSION_ENABLED                     _MK_ENUM_CONST(1)
+
+// VVS pin Input Inversion   0= VVS input is not inverted
+//      (VVS input is active high)
+//   1= VVS input is inverted
+//      (VVS input is active low)
+#define VI_PIN_INVERSION_0_VVS_IN_INVERSION_SHIFT                       _MK_SHIFT_CONST(2)
+#define VI_PIN_INVERSION_0_VVS_IN_INVERSION_FIELD                       (_MK_MASK_CONST(0x1) << VI_PIN_INVERSION_0_VVS_IN_INVERSION_SHIFT)
+#define VI_PIN_INVERSION_0_VVS_IN_INVERSION_RANGE                       2:2
+#define VI_PIN_INVERSION_0_VVS_IN_INVERSION_WOFFSET                     0x0
+#define VI_PIN_INVERSION_0_VVS_IN_INVERSION_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_PIN_INVERSION_0_VVS_IN_INVERSION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define VI_PIN_INVERSION_0_VVS_IN_INVERSION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_PIN_INVERSION_0_VVS_IN_INVERSION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_PIN_INVERSION_0_VVS_IN_INVERSION_DISABLED                    _MK_ENUM_CONST(0)
+#define VI_PIN_INVERSION_0_VVS_IN_INVERSION_ENABLED                     _MK_ENUM_CONST(1)
+
+// VSCK pin Output Inversion   0= VSCK output is not inverted
+//   1= VSCK output is inverted
+#define VI_PIN_INVERSION_0_VSCK_OUT_INVERSION_SHIFT                     _MK_SHIFT_CONST(16)
+#define VI_PIN_INVERSION_0_VSCK_OUT_INVERSION_FIELD                     (_MK_MASK_CONST(0x1) << VI_PIN_INVERSION_0_VSCK_OUT_INVERSION_SHIFT)
+#define VI_PIN_INVERSION_0_VSCK_OUT_INVERSION_RANGE                     16:16
+#define VI_PIN_INVERSION_0_VSCK_OUT_INVERSION_WOFFSET                   0x0
+#define VI_PIN_INVERSION_0_VSCK_OUT_INVERSION_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_PIN_INVERSION_0_VSCK_OUT_INVERSION_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define VI_PIN_INVERSION_0_VSCK_OUT_INVERSION_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_PIN_INVERSION_0_VSCK_OUT_INVERSION_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_PIN_INVERSION_0_VSCK_OUT_INVERSION_DISABLED                  _MK_ENUM_CONST(0)
+#define VI_PIN_INVERSION_0_VSCK_OUT_INVERSION_ENABLED                   _MK_ENUM_CONST(1)
+
+// VHS pin Output Inversion   0= VHS output is not inverted
+//      (VHS output is active high)
+//   1= VHS output is inverted
+//      (VHS output is active low)
+#define VI_PIN_INVERSION_0_VHS_OUT_INVERSION_SHIFT                      _MK_SHIFT_CONST(17)
+#define VI_PIN_INVERSION_0_VHS_OUT_INVERSION_FIELD                      (_MK_MASK_CONST(0x1) << VI_PIN_INVERSION_0_VHS_OUT_INVERSION_SHIFT)
+#define VI_PIN_INVERSION_0_VHS_OUT_INVERSION_RANGE                      17:17
+#define VI_PIN_INVERSION_0_VHS_OUT_INVERSION_WOFFSET                    0x0
+#define VI_PIN_INVERSION_0_VHS_OUT_INVERSION_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PIN_INVERSION_0_VHS_OUT_INVERSION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define VI_PIN_INVERSION_0_VHS_OUT_INVERSION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PIN_INVERSION_0_VHS_OUT_INVERSION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_PIN_INVERSION_0_VHS_OUT_INVERSION_DISABLED                   _MK_ENUM_CONST(0)
+#define VI_PIN_INVERSION_0_VHS_OUT_INVERSION_ENABLED                    _MK_ENUM_CONST(1)
+
+// VVS pin Output Inversion   0= VVS output is not inverted
+//      (VVS output is active high)
+//   1= VVS output is inverted
+//      (VVS output is active low)
+#define VI_PIN_INVERSION_0_VVS_OUT_INVERSION_SHIFT                      _MK_SHIFT_CONST(18)
+#define VI_PIN_INVERSION_0_VVS_OUT_INVERSION_FIELD                      (_MK_MASK_CONST(0x1) << VI_PIN_INVERSION_0_VVS_OUT_INVERSION_SHIFT)
+#define VI_PIN_INVERSION_0_VVS_OUT_INVERSION_RANGE                      18:18
+#define VI_PIN_INVERSION_0_VVS_OUT_INVERSION_WOFFSET                    0x0
+#define VI_PIN_INVERSION_0_VVS_OUT_INVERSION_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PIN_INVERSION_0_VVS_OUT_INVERSION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define VI_PIN_INVERSION_0_VVS_OUT_INVERSION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PIN_INVERSION_0_VVS_OUT_INVERSION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_PIN_INVERSION_0_VVS_OUT_INVERSION_DISABLED                   _MK_ENUM_CONST(0)
+#define VI_PIN_INVERSION_0_VVS_OUT_INVERSION_ENABLED                    _MK_ENUM_CONST(1)
+
+
+// Register VI_PIN_INPUT_DATA_0  // VI pins Input Data
+#define VI_PIN_INPUT_DATA_0                     _MK_ADDR_CONST(0x5e)
+#define VI_PIN_INPUT_DATA_0_WORD_COUNT                  0x1
+#define VI_PIN_INPUT_DATA_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_RESET_MASK                  _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_READ_MASK                   _MK_MASK_CONST(0x3fffff)
+#define VI_PIN_INPUT_DATA_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+// VD0 pin Input Data
+//  (effective if VD0_INPUT_ENABLE is ENABLED)
+//   0= VD0 input low
+//   1= VD0 input high
+#define VI_PIN_INPUT_DATA_0_VD0_INPUT_DATA_SHIFT                        _MK_SHIFT_CONST(0)
+#define VI_PIN_INPUT_DATA_0_VD0_INPUT_DATA_FIELD                        (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_DATA_0_VD0_INPUT_DATA_SHIFT)
+#define VI_PIN_INPUT_DATA_0_VD0_INPUT_DATA_RANGE                        0:0
+#define VI_PIN_INPUT_DATA_0_VD0_INPUT_DATA_WOFFSET                      0x0
+#define VI_PIN_INPUT_DATA_0_VD0_INPUT_DATA_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VD0_INPUT_DATA_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VD0_INPUT_DATA_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VD0_INPUT_DATA_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// VD1 pin Input Data
+//  (effective if VD1_INPUT_ENABLE is ENABLED)
+//   0= VD1 input low
+//   1= VD1 input high
+#define VI_PIN_INPUT_DATA_0_VD1_INPUT_DATA_SHIFT                        _MK_SHIFT_CONST(1)
+#define VI_PIN_INPUT_DATA_0_VD1_INPUT_DATA_FIELD                        (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_DATA_0_VD1_INPUT_DATA_SHIFT)
+#define VI_PIN_INPUT_DATA_0_VD1_INPUT_DATA_RANGE                        1:1
+#define VI_PIN_INPUT_DATA_0_VD1_INPUT_DATA_WOFFSET                      0x0
+#define VI_PIN_INPUT_DATA_0_VD1_INPUT_DATA_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VD1_INPUT_DATA_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VD1_INPUT_DATA_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VD1_INPUT_DATA_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// VD2 pin Input Data
+//  (effective if VD2_INPUT_ENABLE is ENABLED)
+//   0= VD2 input low
+//   1= VD2 input high
+#define VI_PIN_INPUT_DATA_0_VD2_INPUT_DATA_SHIFT                        _MK_SHIFT_CONST(2)
+#define VI_PIN_INPUT_DATA_0_VD2_INPUT_DATA_FIELD                        (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_DATA_0_VD2_INPUT_DATA_SHIFT)
+#define VI_PIN_INPUT_DATA_0_VD2_INPUT_DATA_RANGE                        2:2
+#define VI_PIN_INPUT_DATA_0_VD2_INPUT_DATA_WOFFSET                      0x0
+#define VI_PIN_INPUT_DATA_0_VD2_INPUT_DATA_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VD2_INPUT_DATA_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VD2_INPUT_DATA_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VD2_INPUT_DATA_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// VD3 pin Input Data
+//  (effective if VD3_INPUT_ENABLE is ENABLED)
+//   0= VD3 input low
+//   1= VD3 input high
+#define VI_PIN_INPUT_DATA_0_VD3_INPUT_DATA_SHIFT                        _MK_SHIFT_CONST(3)
+#define VI_PIN_INPUT_DATA_0_VD3_INPUT_DATA_FIELD                        (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_DATA_0_VD3_INPUT_DATA_SHIFT)
+#define VI_PIN_INPUT_DATA_0_VD3_INPUT_DATA_RANGE                        3:3
+#define VI_PIN_INPUT_DATA_0_VD3_INPUT_DATA_WOFFSET                      0x0
+#define VI_PIN_INPUT_DATA_0_VD3_INPUT_DATA_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VD3_INPUT_DATA_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VD3_INPUT_DATA_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VD3_INPUT_DATA_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// VD4 pin Input Data
+//  (effective if VD4_INPUT_ENABLE is ENABLED)
+//   0= VD4 input low
+//   1= VD4 input high
+#define VI_PIN_INPUT_DATA_0_VD4_INPUT_DATA_SHIFT                        _MK_SHIFT_CONST(4)
+#define VI_PIN_INPUT_DATA_0_VD4_INPUT_DATA_FIELD                        (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_DATA_0_VD4_INPUT_DATA_SHIFT)
+#define VI_PIN_INPUT_DATA_0_VD4_INPUT_DATA_RANGE                        4:4
+#define VI_PIN_INPUT_DATA_0_VD4_INPUT_DATA_WOFFSET                      0x0
+#define VI_PIN_INPUT_DATA_0_VD4_INPUT_DATA_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VD4_INPUT_DATA_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VD4_INPUT_DATA_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VD4_INPUT_DATA_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// VD5 pin Input Data
+//  (effective if VD5_INPUT_ENABLE is ENABLED)
+//   0= VD5 input low
+//   1= VD5 input high
+#define VI_PIN_INPUT_DATA_0_VD5_INPUT_DATA_SHIFT                        _MK_SHIFT_CONST(5)
+#define VI_PIN_INPUT_DATA_0_VD5_INPUT_DATA_FIELD                        (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_DATA_0_VD5_INPUT_DATA_SHIFT)
+#define VI_PIN_INPUT_DATA_0_VD5_INPUT_DATA_RANGE                        5:5
+#define VI_PIN_INPUT_DATA_0_VD5_INPUT_DATA_WOFFSET                      0x0
+#define VI_PIN_INPUT_DATA_0_VD5_INPUT_DATA_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VD5_INPUT_DATA_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VD5_INPUT_DATA_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VD5_INPUT_DATA_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// VD6 pin Input Data
+//  (effective if VD6_INPUT_ENABLE is ENABLED)
+//   0= VD6 input low
+//   1= VD6 input high
+#define VI_PIN_INPUT_DATA_0_VD6_INPUT_DATA_SHIFT                        _MK_SHIFT_CONST(6)
+#define VI_PIN_INPUT_DATA_0_VD6_INPUT_DATA_FIELD                        (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_DATA_0_VD6_INPUT_DATA_SHIFT)
+#define VI_PIN_INPUT_DATA_0_VD6_INPUT_DATA_RANGE                        6:6
+#define VI_PIN_INPUT_DATA_0_VD6_INPUT_DATA_WOFFSET                      0x0
+#define VI_PIN_INPUT_DATA_0_VD6_INPUT_DATA_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VD6_INPUT_DATA_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VD6_INPUT_DATA_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VD6_INPUT_DATA_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// VD7 pin Input Data
+//  (effective if VD7_INPUT_ENABLE is ENABLED)
+//   0= VD7 input low
+//   1= VD7 input high
+#define VI_PIN_INPUT_DATA_0_VD7_INPUT_DATA_SHIFT                        _MK_SHIFT_CONST(7)
+#define VI_PIN_INPUT_DATA_0_VD7_INPUT_DATA_FIELD                        (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_DATA_0_VD7_INPUT_DATA_SHIFT)
+#define VI_PIN_INPUT_DATA_0_VD7_INPUT_DATA_RANGE                        7:7
+#define VI_PIN_INPUT_DATA_0_VD7_INPUT_DATA_WOFFSET                      0x0
+#define VI_PIN_INPUT_DATA_0_VD7_INPUT_DATA_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VD7_INPUT_DATA_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VD7_INPUT_DATA_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VD7_INPUT_DATA_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// VD8 pin Input Data
+//  (effective if VD8_INPUT_ENABLE is ENABLED)
+//   0= VD8 input low
+//   1= VD8 input high
+#define VI_PIN_INPUT_DATA_0_VD8_INPUT_DATA_SHIFT                        _MK_SHIFT_CONST(8)
+#define VI_PIN_INPUT_DATA_0_VD8_INPUT_DATA_FIELD                        (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_DATA_0_VD8_INPUT_DATA_SHIFT)
+#define VI_PIN_INPUT_DATA_0_VD8_INPUT_DATA_RANGE                        8:8
+#define VI_PIN_INPUT_DATA_0_VD8_INPUT_DATA_WOFFSET                      0x0
+#define VI_PIN_INPUT_DATA_0_VD8_INPUT_DATA_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VD8_INPUT_DATA_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VD8_INPUT_DATA_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VD8_INPUT_DATA_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// VD9 pin Input Data
+//  (effective if VD9_INPUT_ENABLE is ENABLED)
+//   0= VD9 input low
+//   1= VD9 input high
+#define VI_PIN_INPUT_DATA_0_VD9_INPUT_DATA_SHIFT                        _MK_SHIFT_CONST(9)
+#define VI_PIN_INPUT_DATA_0_VD9_INPUT_DATA_FIELD                        (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_DATA_0_VD9_INPUT_DATA_SHIFT)
+#define VI_PIN_INPUT_DATA_0_VD9_INPUT_DATA_RANGE                        9:9
+#define VI_PIN_INPUT_DATA_0_VD9_INPUT_DATA_WOFFSET                      0x0
+#define VI_PIN_INPUT_DATA_0_VD9_INPUT_DATA_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VD9_INPUT_DATA_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VD9_INPUT_DATA_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VD9_INPUT_DATA_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// VD10 pin Input Data
+//  (effective if VD10_INPUT_ENABLE is ENABLED)
+//   0= VD10 input low
+//   1= VD10 input high
+#define VI_PIN_INPUT_DATA_0_VD10_INPUT_DATA_SHIFT                       _MK_SHIFT_CONST(10)
+#define VI_PIN_INPUT_DATA_0_VD10_INPUT_DATA_FIELD                       (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_DATA_0_VD10_INPUT_DATA_SHIFT)
+#define VI_PIN_INPUT_DATA_0_VD10_INPUT_DATA_RANGE                       10:10
+#define VI_PIN_INPUT_DATA_0_VD10_INPUT_DATA_WOFFSET                     0x0
+#define VI_PIN_INPUT_DATA_0_VD10_INPUT_DATA_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VD10_INPUT_DATA_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VD10_INPUT_DATA_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VD10_INPUT_DATA_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// VD11 pin Input Data
+//  (effective if VD11_INPUT_ENABLE is ENABLED)
+//   0= VD11 input low
+//   1= VD11 input high
+#define VI_PIN_INPUT_DATA_0_VD11_INPUT_DATA_SHIFT                       _MK_SHIFT_CONST(11)
+#define VI_PIN_INPUT_DATA_0_VD11_INPUT_DATA_FIELD                       (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_DATA_0_VD11_INPUT_DATA_SHIFT)
+#define VI_PIN_INPUT_DATA_0_VD11_INPUT_DATA_RANGE                       11:11
+#define VI_PIN_INPUT_DATA_0_VD11_INPUT_DATA_WOFFSET                     0x0
+#define VI_PIN_INPUT_DATA_0_VD11_INPUT_DATA_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VD11_INPUT_DATA_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VD11_INPUT_DATA_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VD11_INPUT_DATA_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// VSCK pin Input Data
+//  (effective if VSCK_INPUT_ENABLE is ENABLED)
+//   0= VSCK input low
+//   1= VSCK input high
+#define VI_PIN_INPUT_DATA_0_VSCK_INPUT_DATA_SHIFT                       _MK_SHIFT_CONST(12)
+#define VI_PIN_INPUT_DATA_0_VSCK_INPUT_DATA_FIELD                       (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_DATA_0_VSCK_INPUT_DATA_SHIFT)
+#define VI_PIN_INPUT_DATA_0_VSCK_INPUT_DATA_RANGE                       12:12
+#define VI_PIN_INPUT_DATA_0_VSCK_INPUT_DATA_WOFFSET                     0x0
+#define VI_PIN_INPUT_DATA_0_VSCK_INPUT_DATA_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VSCK_INPUT_DATA_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VSCK_INPUT_DATA_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VSCK_INPUT_DATA_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// VHS pin Input Data
+//  (effective if VHS_INPUT_ENABLE is ENABLED)
+//   0= VHS input low
+//   1= VHS input high
+#define VI_PIN_INPUT_DATA_0_VHS_INPUT_DATA_SHIFT                        _MK_SHIFT_CONST(13)
+#define VI_PIN_INPUT_DATA_0_VHS_INPUT_DATA_FIELD                        (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_DATA_0_VHS_INPUT_DATA_SHIFT)
+#define VI_PIN_INPUT_DATA_0_VHS_INPUT_DATA_RANGE                        13:13
+#define VI_PIN_INPUT_DATA_0_VHS_INPUT_DATA_WOFFSET                      0x0
+#define VI_PIN_INPUT_DATA_0_VHS_INPUT_DATA_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VHS_INPUT_DATA_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VHS_INPUT_DATA_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VHS_INPUT_DATA_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// VVS pin Input Data
+//  (effective if VVS_INPUT_ENABLE is ENABLED)
+//   0= VVS input low
+//   1= VVS input high
+#define VI_PIN_INPUT_DATA_0_VVS_INPUT_DATA_SHIFT                        _MK_SHIFT_CONST(14)
+#define VI_PIN_INPUT_DATA_0_VVS_INPUT_DATA_FIELD                        (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_DATA_0_VVS_INPUT_DATA_SHIFT)
+#define VI_PIN_INPUT_DATA_0_VVS_INPUT_DATA_RANGE                        14:14
+#define VI_PIN_INPUT_DATA_0_VVS_INPUT_DATA_WOFFSET                      0x0
+#define VI_PIN_INPUT_DATA_0_VVS_INPUT_DATA_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VVS_INPUT_DATA_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VVS_INPUT_DATA_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VVS_INPUT_DATA_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// VGP0 pin Input Data
+//  (effective if VGP0_INPUT_ENABLE is ENABLED)
+//   0= VGP0 input low
+//   1= VGP0 input high
+#define VI_PIN_INPUT_DATA_0_VGP0_INPUT_DATA_SHIFT                       _MK_SHIFT_CONST(15)
+#define VI_PIN_INPUT_DATA_0_VGP0_INPUT_DATA_FIELD                       (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_DATA_0_VGP0_INPUT_DATA_SHIFT)
+#define VI_PIN_INPUT_DATA_0_VGP0_INPUT_DATA_RANGE                       15:15
+#define VI_PIN_INPUT_DATA_0_VGP0_INPUT_DATA_WOFFSET                     0x0
+#define VI_PIN_INPUT_DATA_0_VGP0_INPUT_DATA_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VGP0_INPUT_DATA_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VGP0_INPUT_DATA_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VGP0_INPUT_DATA_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// VGP1 pin Input Data
+//  (effective if VGP1_INPUT_ENABLE is ENABLED)
+//   0= VGP1 input low
+//   1= VGP1 input high
+#define VI_PIN_INPUT_DATA_0_VGP1_INPUT_DATA_SHIFT                       _MK_SHIFT_CONST(16)
+#define VI_PIN_INPUT_DATA_0_VGP1_INPUT_DATA_FIELD                       (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_DATA_0_VGP1_INPUT_DATA_SHIFT)
+#define VI_PIN_INPUT_DATA_0_VGP1_INPUT_DATA_RANGE                       16:16
+#define VI_PIN_INPUT_DATA_0_VGP1_INPUT_DATA_WOFFSET                     0x0
+#define VI_PIN_INPUT_DATA_0_VGP1_INPUT_DATA_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VGP1_INPUT_DATA_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VGP1_INPUT_DATA_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VGP1_INPUT_DATA_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// VGP2 pin Input Data
+//  (effective if VGP2_INPUT_ENABLE is ENABLED)
+//   0= VGP2 input low
+//   1= VGP2 input high
+#define VI_PIN_INPUT_DATA_0_VGP2_INPUT_DATA_SHIFT                       _MK_SHIFT_CONST(17)
+#define VI_PIN_INPUT_DATA_0_VGP2_INPUT_DATA_FIELD                       (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_DATA_0_VGP2_INPUT_DATA_SHIFT)
+#define VI_PIN_INPUT_DATA_0_VGP2_INPUT_DATA_RANGE                       17:17
+#define VI_PIN_INPUT_DATA_0_VGP2_INPUT_DATA_WOFFSET                     0x0
+#define VI_PIN_INPUT_DATA_0_VGP2_INPUT_DATA_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VGP2_INPUT_DATA_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VGP2_INPUT_DATA_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VGP2_INPUT_DATA_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// VGP3 pin Input Data
+//  (effective if VGP3_INPUT_ENABLE is ENABLED)
+//   0= VGP3 input low
+//   1= VGP3 input high
+#define VI_PIN_INPUT_DATA_0_VGP3_INPUT_DATA_SHIFT                       _MK_SHIFT_CONST(18)
+#define VI_PIN_INPUT_DATA_0_VGP3_INPUT_DATA_FIELD                       (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_DATA_0_VGP3_INPUT_DATA_SHIFT)
+#define VI_PIN_INPUT_DATA_0_VGP3_INPUT_DATA_RANGE                       18:18
+#define VI_PIN_INPUT_DATA_0_VGP3_INPUT_DATA_WOFFSET                     0x0
+#define VI_PIN_INPUT_DATA_0_VGP3_INPUT_DATA_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VGP3_INPUT_DATA_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VGP3_INPUT_DATA_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VGP3_INPUT_DATA_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// VGP4 pin Input Data
+//  (effective if VGP4_INPUT_ENABLE is ENABLED)
+//   0= VGP4 input low
+//   1= VGP4 input high
+#define VI_PIN_INPUT_DATA_0_VGP4_INPUT_DATA_SHIFT                       _MK_SHIFT_CONST(19)
+#define VI_PIN_INPUT_DATA_0_VGP4_INPUT_DATA_FIELD                       (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_DATA_0_VGP4_INPUT_DATA_SHIFT)
+#define VI_PIN_INPUT_DATA_0_VGP4_INPUT_DATA_RANGE                       19:19
+#define VI_PIN_INPUT_DATA_0_VGP4_INPUT_DATA_WOFFSET                     0x0
+#define VI_PIN_INPUT_DATA_0_VGP4_INPUT_DATA_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VGP4_INPUT_DATA_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VGP4_INPUT_DATA_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VGP4_INPUT_DATA_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// VGP5 pin Input Data
+//  (effective if VGP5_INPUT_ENABLE is ENABLED)
+//   0= VGP5 input low
+//   1= VGP5 input high
+#define VI_PIN_INPUT_DATA_0_VGP5_INPUT_DATA_SHIFT                       _MK_SHIFT_CONST(20)
+#define VI_PIN_INPUT_DATA_0_VGP5_INPUT_DATA_FIELD                       (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_DATA_0_VGP5_INPUT_DATA_SHIFT)
+#define VI_PIN_INPUT_DATA_0_VGP5_INPUT_DATA_RANGE                       20:20
+#define VI_PIN_INPUT_DATA_0_VGP5_INPUT_DATA_WOFFSET                     0x0
+#define VI_PIN_INPUT_DATA_0_VGP5_INPUT_DATA_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VGP5_INPUT_DATA_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VGP5_INPUT_DATA_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VGP5_INPUT_DATA_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// VGP6 pin Input Data
+//  (effective if VGP6_INPUT_ENABLE is ENABLED)
+//   0= VGP6 input low
+//   1= VGP6 input high
+#define VI_PIN_INPUT_DATA_0_VGP6_INPUT_DATA_SHIFT                       _MK_SHIFT_CONST(21)
+#define VI_PIN_INPUT_DATA_0_VGP6_INPUT_DATA_FIELD                       (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_DATA_0_VGP6_INPUT_DATA_SHIFT)
+#define VI_PIN_INPUT_DATA_0_VGP6_INPUT_DATA_RANGE                       21:21
+#define VI_PIN_INPUT_DATA_0_VGP6_INPUT_DATA_WOFFSET                     0x0
+#define VI_PIN_INPUT_DATA_0_VGP6_INPUT_DATA_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VGP6_INPUT_DATA_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VGP6_INPUT_DATA_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VGP6_INPUT_DATA_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register VI_PIN_OUTPUT_DATA_0  // VI pins Output Data
+#define VI_PIN_OUTPUT_DATA_0                    _MK_ADDR_CONST(0x5f)
+#define VI_PIN_OUTPUT_DATA_0_WORD_COUNT                         0x1
+#define VI_PIN_OUTPUT_DATA_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_READ_MASK                  _MK_MASK_CONST(0x3fffff)
+#define VI_PIN_OUTPUT_DATA_0_WRITE_MASK                         _MK_MASK_CONST(0x3fffff)
+// VD0 pin Output Data
+//  (effective if VD0_OUTPUT_ENABLE is ENABLED
+//   and VD0_OUTPUT_SELECT is DATA)
+#define VI_PIN_OUTPUT_DATA_0_VD0_OUTPUT_DATA_SHIFT                      _MK_SHIFT_CONST(0)
+#define VI_PIN_OUTPUT_DATA_0_VD0_OUTPUT_DATA_FIELD                      (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_DATA_0_VD0_OUTPUT_DATA_SHIFT)
+#define VI_PIN_OUTPUT_DATA_0_VD0_OUTPUT_DATA_RANGE                      0:0
+#define VI_PIN_OUTPUT_DATA_0_VD0_OUTPUT_DATA_WOFFSET                    0x0
+#define VI_PIN_OUTPUT_DATA_0_VD0_OUTPUT_DATA_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VD0_OUTPUT_DATA_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VD0_OUTPUT_DATA_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VD0_OUTPUT_DATA_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// VD1 pin Output Data
+//  (effective if VD1_OUTPUT_ENABLE is ENABLED
+//   and VD1_OUTPUT_SELECT is DATA)
+#define VI_PIN_OUTPUT_DATA_0_VD1_OUTPUT_DATA_SHIFT                      _MK_SHIFT_CONST(1)
+#define VI_PIN_OUTPUT_DATA_0_VD1_OUTPUT_DATA_FIELD                      (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_DATA_0_VD1_OUTPUT_DATA_SHIFT)
+#define VI_PIN_OUTPUT_DATA_0_VD1_OUTPUT_DATA_RANGE                      1:1
+#define VI_PIN_OUTPUT_DATA_0_VD1_OUTPUT_DATA_WOFFSET                    0x0
+#define VI_PIN_OUTPUT_DATA_0_VD1_OUTPUT_DATA_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VD1_OUTPUT_DATA_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VD1_OUTPUT_DATA_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VD1_OUTPUT_DATA_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// VD2 pin Output Data
+//  (effective if VD2_OUTPUT_ENABLE is ENABLED
+//   and VD2_OUTPUT_SELECT is DATA)
+#define VI_PIN_OUTPUT_DATA_0_VD2_OUTPUT_DATA_SHIFT                      _MK_SHIFT_CONST(2)
+#define VI_PIN_OUTPUT_DATA_0_VD2_OUTPUT_DATA_FIELD                      (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_DATA_0_VD2_OUTPUT_DATA_SHIFT)
+#define VI_PIN_OUTPUT_DATA_0_VD2_OUTPUT_DATA_RANGE                      2:2
+#define VI_PIN_OUTPUT_DATA_0_VD2_OUTPUT_DATA_WOFFSET                    0x0
+#define VI_PIN_OUTPUT_DATA_0_VD2_OUTPUT_DATA_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VD2_OUTPUT_DATA_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VD2_OUTPUT_DATA_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VD2_OUTPUT_DATA_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// VD3 pin Output Data
+//  (effective if VD3_OUTPUT_ENABLE is ENABLED
+//   and VD3_OUTPUT_SELECT is DATA)
+#define VI_PIN_OUTPUT_DATA_0_VD3_OUTPUT_DATA_SHIFT                      _MK_SHIFT_CONST(3)
+#define VI_PIN_OUTPUT_DATA_0_VD3_OUTPUT_DATA_FIELD                      (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_DATA_0_VD3_OUTPUT_DATA_SHIFT)
+#define VI_PIN_OUTPUT_DATA_0_VD3_OUTPUT_DATA_RANGE                      3:3
+#define VI_PIN_OUTPUT_DATA_0_VD3_OUTPUT_DATA_WOFFSET                    0x0
+#define VI_PIN_OUTPUT_DATA_0_VD3_OUTPUT_DATA_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VD3_OUTPUT_DATA_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VD3_OUTPUT_DATA_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VD3_OUTPUT_DATA_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// VD4 pin Output Data
+//  (effective if VD4_OUTPUT_ENABLE is ENABLED
+//   and VD4_OUTPUT_SELECT is DATA)
+#define VI_PIN_OUTPUT_DATA_0_VD4_OUTPUT_DATA_SHIFT                      _MK_SHIFT_CONST(4)
+#define VI_PIN_OUTPUT_DATA_0_VD4_OUTPUT_DATA_FIELD                      (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_DATA_0_VD4_OUTPUT_DATA_SHIFT)
+#define VI_PIN_OUTPUT_DATA_0_VD4_OUTPUT_DATA_RANGE                      4:4
+#define VI_PIN_OUTPUT_DATA_0_VD4_OUTPUT_DATA_WOFFSET                    0x0
+#define VI_PIN_OUTPUT_DATA_0_VD4_OUTPUT_DATA_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VD4_OUTPUT_DATA_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VD4_OUTPUT_DATA_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VD4_OUTPUT_DATA_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// VD5 pin Output Data
+//  (effective if VD5_OUTPUT_ENABLE is ENABLED
+//   and VD5_OUTPUT_SELECT is DATA)
+#define VI_PIN_OUTPUT_DATA_0_VD5_OUTPUT_DATA_SHIFT                      _MK_SHIFT_CONST(5)
+#define VI_PIN_OUTPUT_DATA_0_VD5_OUTPUT_DATA_FIELD                      (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_DATA_0_VD5_OUTPUT_DATA_SHIFT)
+#define VI_PIN_OUTPUT_DATA_0_VD5_OUTPUT_DATA_RANGE                      5:5
+#define VI_PIN_OUTPUT_DATA_0_VD5_OUTPUT_DATA_WOFFSET                    0x0
+#define VI_PIN_OUTPUT_DATA_0_VD5_OUTPUT_DATA_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VD5_OUTPUT_DATA_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VD5_OUTPUT_DATA_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VD5_OUTPUT_DATA_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// VD6 pin Output Data
+//  (effective if VD6_OUTPUT_ENABLE is ENABLED
+//   and VD6_OUTPUT_SELECT is DATA)
+#define VI_PIN_OUTPUT_DATA_0_VD6_OUTPUT_DATA_SHIFT                      _MK_SHIFT_CONST(6)
+#define VI_PIN_OUTPUT_DATA_0_VD6_OUTPUT_DATA_FIELD                      (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_DATA_0_VD6_OUTPUT_DATA_SHIFT)
+#define VI_PIN_OUTPUT_DATA_0_VD6_OUTPUT_DATA_RANGE                      6:6
+#define VI_PIN_OUTPUT_DATA_0_VD6_OUTPUT_DATA_WOFFSET                    0x0
+#define VI_PIN_OUTPUT_DATA_0_VD6_OUTPUT_DATA_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VD6_OUTPUT_DATA_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VD6_OUTPUT_DATA_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VD6_OUTPUT_DATA_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// VD7 pin Output Data
+//  (effective if VD7_OUTPUT_ENABLE is ENABLED
+//   and VD7_OUTPUT_SELECT is DATA)
+#define VI_PIN_OUTPUT_DATA_0_VD7_OUTPUT_DATA_SHIFT                      _MK_SHIFT_CONST(7)
+#define VI_PIN_OUTPUT_DATA_0_VD7_OUTPUT_DATA_FIELD                      (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_DATA_0_VD7_OUTPUT_DATA_SHIFT)
+#define VI_PIN_OUTPUT_DATA_0_VD7_OUTPUT_DATA_RANGE                      7:7
+#define VI_PIN_OUTPUT_DATA_0_VD7_OUTPUT_DATA_WOFFSET                    0x0
+#define VI_PIN_OUTPUT_DATA_0_VD7_OUTPUT_DATA_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VD7_OUTPUT_DATA_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VD7_OUTPUT_DATA_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VD7_OUTPUT_DATA_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// VD8 pin Output Data
+//  (effective if VD8_OUTPUT_ENABLE is ENABLED
+//   and VD8_OUTPUT_SELECT is DATA)
+#define VI_PIN_OUTPUT_DATA_0_VD8_OUTPUT_DATA_SHIFT                      _MK_SHIFT_CONST(8)
+#define VI_PIN_OUTPUT_DATA_0_VD8_OUTPUT_DATA_FIELD                      (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_DATA_0_VD8_OUTPUT_DATA_SHIFT)
+#define VI_PIN_OUTPUT_DATA_0_VD8_OUTPUT_DATA_RANGE                      8:8
+#define VI_PIN_OUTPUT_DATA_0_VD8_OUTPUT_DATA_WOFFSET                    0x0
+#define VI_PIN_OUTPUT_DATA_0_VD8_OUTPUT_DATA_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VD8_OUTPUT_DATA_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VD8_OUTPUT_DATA_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VD8_OUTPUT_DATA_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// VD9 pin Output Data
+//  (effective if VD9_OUTPUT_ENABLE is ENABLED
+//   and VD9_OUTPUT_SELECT is DATA)
+#define VI_PIN_OUTPUT_DATA_0_VD9_OUTPUT_DATA_SHIFT                      _MK_SHIFT_CONST(9)
+#define VI_PIN_OUTPUT_DATA_0_VD9_OUTPUT_DATA_FIELD                      (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_DATA_0_VD9_OUTPUT_DATA_SHIFT)
+#define VI_PIN_OUTPUT_DATA_0_VD9_OUTPUT_DATA_RANGE                      9:9
+#define VI_PIN_OUTPUT_DATA_0_VD9_OUTPUT_DATA_WOFFSET                    0x0
+#define VI_PIN_OUTPUT_DATA_0_VD9_OUTPUT_DATA_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VD9_OUTPUT_DATA_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VD9_OUTPUT_DATA_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VD9_OUTPUT_DATA_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// VD10 pin Output Data
+//  (effective if VD10_OUTPUT_ENABLE is ENABLED
+//   and VD10_OUTPUT_SELECT is DATA)
+#define VI_PIN_OUTPUT_DATA_0_VD10_OUTPUT_DATA_SHIFT                     _MK_SHIFT_CONST(10)
+#define VI_PIN_OUTPUT_DATA_0_VD10_OUTPUT_DATA_FIELD                     (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_DATA_0_VD10_OUTPUT_DATA_SHIFT)
+#define VI_PIN_OUTPUT_DATA_0_VD10_OUTPUT_DATA_RANGE                     10:10
+#define VI_PIN_OUTPUT_DATA_0_VD10_OUTPUT_DATA_WOFFSET                   0x0
+#define VI_PIN_OUTPUT_DATA_0_VD10_OUTPUT_DATA_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VD10_OUTPUT_DATA_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VD10_OUTPUT_DATA_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VD10_OUTPUT_DATA_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// VD11 pin Output Data
+//  (effective if VD11_OUTPUT_ENABLE is ENABLED
+//   and VD11_OUTPUT_SELECT is DATA)
+#define VI_PIN_OUTPUT_DATA_0_VD11_OUTPUT_DATA_SHIFT                     _MK_SHIFT_CONST(11)
+#define VI_PIN_OUTPUT_DATA_0_VD11_OUTPUT_DATA_FIELD                     (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_DATA_0_VD11_OUTPUT_DATA_SHIFT)
+#define VI_PIN_OUTPUT_DATA_0_VD11_OUTPUT_DATA_RANGE                     11:11
+#define VI_PIN_OUTPUT_DATA_0_VD11_OUTPUT_DATA_WOFFSET                   0x0
+#define VI_PIN_OUTPUT_DATA_0_VD11_OUTPUT_DATA_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VD11_OUTPUT_DATA_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VD11_OUTPUT_DATA_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VD11_OUTPUT_DATA_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// VSCK pin Output Data
+//  (effective if VSCK_OUTPUT_ENABLE is ENABLED
+//   and VSCK_OUTPUT_SELECT is DATA)
+#define VI_PIN_OUTPUT_DATA_0_VSCK_OUTPUT_DATA_SHIFT                     _MK_SHIFT_CONST(12)
+#define VI_PIN_OUTPUT_DATA_0_VSCK_OUTPUT_DATA_FIELD                     (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_DATA_0_VSCK_OUTPUT_DATA_SHIFT)
+#define VI_PIN_OUTPUT_DATA_0_VSCK_OUTPUT_DATA_RANGE                     12:12
+#define VI_PIN_OUTPUT_DATA_0_VSCK_OUTPUT_DATA_WOFFSET                   0x0
+#define VI_PIN_OUTPUT_DATA_0_VSCK_OUTPUT_DATA_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VSCK_OUTPUT_DATA_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VSCK_OUTPUT_DATA_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VSCK_OUTPUT_DATA_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// VHS pin Output Data
+//  (effective if VHS_OUTPUT_ENABLE is ENABLED
+//   and VHS_OUTPUT_SELECT is DATA)
+#define VI_PIN_OUTPUT_DATA_0_VHS_OUTPUT_DATA_SHIFT                      _MK_SHIFT_CONST(13)
+#define VI_PIN_OUTPUT_DATA_0_VHS_OUTPUT_DATA_FIELD                      (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_DATA_0_VHS_OUTPUT_DATA_SHIFT)
+#define VI_PIN_OUTPUT_DATA_0_VHS_OUTPUT_DATA_RANGE                      13:13
+#define VI_PIN_OUTPUT_DATA_0_VHS_OUTPUT_DATA_WOFFSET                    0x0
+#define VI_PIN_OUTPUT_DATA_0_VHS_OUTPUT_DATA_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VHS_OUTPUT_DATA_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VHS_OUTPUT_DATA_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VHS_OUTPUT_DATA_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// VVS pin Output Data
+//  (effective if VVS_OUTPUT_ENABLE is ENABLED
+//   and VVS_OUTPUT_SELECT is DATA)
+#define VI_PIN_OUTPUT_DATA_0_VVS_OUTPUT_DATA_SHIFT                      _MK_SHIFT_CONST(14)
+#define VI_PIN_OUTPUT_DATA_0_VVS_OUTPUT_DATA_FIELD                      (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_DATA_0_VVS_OUTPUT_DATA_SHIFT)
+#define VI_PIN_OUTPUT_DATA_0_VVS_OUTPUT_DATA_RANGE                      14:14
+#define VI_PIN_OUTPUT_DATA_0_VVS_OUTPUT_DATA_WOFFSET                    0x0
+#define VI_PIN_OUTPUT_DATA_0_VVS_OUTPUT_DATA_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VVS_OUTPUT_DATA_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VVS_OUTPUT_DATA_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VVS_OUTPUT_DATA_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// VGP0 pin Output Data
+//  (effective if VGP0_OUTPUT_ENABLE is ENABLED
+//   and VGP0_OUTPUT_SELECT is DATA)
+#define VI_PIN_OUTPUT_DATA_0_VGP0_OUTPUT_DATA_SHIFT                     _MK_SHIFT_CONST(15)
+#define VI_PIN_OUTPUT_DATA_0_VGP0_OUTPUT_DATA_FIELD                     (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_DATA_0_VGP0_OUTPUT_DATA_SHIFT)
+#define VI_PIN_OUTPUT_DATA_0_VGP0_OUTPUT_DATA_RANGE                     15:15
+#define VI_PIN_OUTPUT_DATA_0_VGP0_OUTPUT_DATA_WOFFSET                   0x0
+#define VI_PIN_OUTPUT_DATA_0_VGP0_OUTPUT_DATA_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VGP0_OUTPUT_DATA_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VGP0_OUTPUT_DATA_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VGP0_OUTPUT_DATA_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// VGP1 pin Output Data
+//  (effective if VGP1_OUTPUT_ENABLE is ENABLED
+//   and VGP1_OUTPUT_SELECT is DATA)
+#define VI_PIN_OUTPUT_DATA_0_VGP1_OUTPUT_DATA_SHIFT                     _MK_SHIFT_CONST(16)
+#define VI_PIN_OUTPUT_DATA_0_VGP1_OUTPUT_DATA_FIELD                     (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_DATA_0_VGP1_OUTPUT_DATA_SHIFT)
+#define VI_PIN_OUTPUT_DATA_0_VGP1_OUTPUT_DATA_RANGE                     16:16
+#define VI_PIN_OUTPUT_DATA_0_VGP1_OUTPUT_DATA_WOFFSET                   0x0
+#define VI_PIN_OUTPUT_DATA_0_VGP1_OUTPUT_DATA_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VGP1_OUTPUT_DATA_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VGP1_OUTPUT_DATA_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VGP1_OUTPUT_DATA_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// VGP2 pin Output Data
+//  (effective if VGP2_OUTPUT_ENABLE is ENABLED
+//   and VGP2_OUTPUT_SELECT is DATA)
+#define VI_PIN_OUTPUT_DATA_0_VGP2_OUTPUT_DATA_SHIFT                     _MK_SHIFT_CONST(17)
+#define VI_PIN_OUTPUT_DATA_0_VGP2_OUTPUT_DATA_FIELD                     (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_DATA_0_VGP2_OUTPUT_DATA_SHIFT)
+#define VI_PIN_OUTPUT_DATA_0_VGP2_OUTPUT_DATA_RANGE                     17:17
+#define VI_PIN_OUTPUT_DATA_0_VGP2_OUTPUT_DATA_WOFFSET                   0x0
+#define VI_PIN_OUTPUT_DATA_0_VGP2_OUTPUT_DATA_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VGP2_OUTPUT_DATA_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VGP2_OUTPUT_DATA_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VGP2_OUTPUT_DATA_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// VGP3 pin Output Data
+//  (effective if VGP3_OUTPUT_ENABLE is ENABLED
+//   and VGP3_OUTPUT_SELECT is DATA)
+#define VI_PIN_OUTPUT_DATA_0_VGP3_OUTPUT_DATA_SHIFT                     _MK_SHIFT_CONST(18)
+#define VI_PIN_OUTPUT_DATA_0_VGP3_OUTPUT_DATA_FIELD                     (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_DATA_0_VGP3_OUTPUT_DATA_SHIFT)
+#define VI_PIN_OUTPUT_DATA_0_VGP3_OUTPUT_DATA_RANGE                     18:18
+#define VI_PIN_OUTPUT_DATA_0_VGP3_OUTPUT_DATA_WOFFSET                   0x0
+#define VI_PIN_OUTPUT_DATA_0_VGP3_OUTPUT_DATA_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VGP3_OUTPUT_DATA_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VGP3_OUTPUT_DATA_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VGP3_OUTPUT_DATA_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// VGP4 pin Output Data
+//  (effective if VGP4_OUTPUT_ENABLE is ENABLED
+//   and VGP4_OUTPUT_SELECT is DATA)
+#define VI_PIN_OUTPUT_DATA_0_VGP4_OUTPUT_DATA_SHIFT                     _MK_SHIFT_CONST(19)
+#define VI_PIN_OUTPUT_DATA_0_VGP4_OUTPUT_DATA_FIELD                     (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_DATA_0_VGP4_OUTPUT_DATA_SHIFT)
+#define VI_PIN_OUTPUT_DATA_0_VGP4_OUTPUT_DATA_RANGE                     19:19
+#define VI_PIN_OUTPUT_DATA_0_VGP4_OUTPUT_DATA_WOFFSET                   0x0
+#define VI_PIN_OUTPUT_DATA_0_VGP4_OUTPUT_DATA_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VGP4_OUTPUT_DATA_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VGP4_OUTPUT_DATA_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VGP4_OUTPUT_DATA_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// VGP5 pin Output Data
+//  (effective if VGP5_OUTPUT_ENABLE is ENABLED
+//   and VGP5_OUTPUT_SELECT is DATA)
+#define VI_PIN_OUTPUT_DATA_0_VGP5_OUTPUT_DATA_SHIFT                     _MK_SHIFT_CONST(20)
+#define VI_PIN_OUTPUT_DATA_0_VGP5_OUTPUT_DATA_FIELD                     (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_DATA_0_VGP5_OUTPUT_DATA_SHIFT)
+#define VI_PIN_OUTPUT_DATA_0_VGP5_OUTPUT_DATA_RANGE                     20:20
+#define VI_PIN_OUTPUT_DATA_0_VGP5_OUTPUT_DATA_WOFFSET                   0x0
+#define VI_PIN_OUTPUT_DATA_0_VGP5_OUTPUT_DATA_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VGP5_OUTPUT_DATA_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VGP5_OUTPUT_DATA_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VGP5_OUTPUT_DATA_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// VGP6 pin Output Data
+//  (effective if VGP6_OUTPUT_ENABLE is ENABLED
+//   and VGP6_OUTPUT_SELECT is DATA)
+#define VI_PIN_OUTPUT_DATA_0_VGP6_OUTPUT_DATA_SHIFT                     _MK_SHIFT_CONST(21)
+#define VI_PIN_OUTPUT_DATA_0_VGP6_OUTPUT_DATA_FIELD                     (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_DATA_0_VGP6_OUTPUT_DATA_SHIFT)
+#define VI_PIN_OUTPUT_DATA_0_VGP6_OUTPUT_DATA_RANGE                     21:21
+#define VI_PIN_OUTPUT_DATA_0_VGP6_OUTPUT_DATA_WOFFSET                   0x0
+#define VI_PIN_OUTPUT_DATA_0_VGP6_OUTPUT_DATA_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VGP6_OUTPUT_DATA_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VGP6_OUTPUT_DATA_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VGP6_OUTPUT_DATA_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register VI_PIN_OUTPUT_SELECT_0  // VI pins Output Select
+// This is the mux select used at the Pad Macro
+// For VCLK, VHSYNC, VVSYNC
+// Selects between the register programmed GPIO outputs (set to 0)
+// and the internally generated viclk, hsync, vsync (set to 1)
+// For VGP1-VGP2
+// Selects between the I^2C outputs (set to 0)
+// and the VI register programmed GPIO outputs (set to 1)
+// For VD0-VD11
+// Reserved for future use
+// data pins output will be driven by GPIO outputs if enabled
+#define VI_PIN_OUTPUT_SELECT_0                  _MK_ADDR_CONST(0x60)
+#define VI_PIN_OUTPUT_SELECT_0_WORD_COUNT                       0x1
+#define VI_PIN_OUTPUT_SELECT_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_RESET_MASK                       _MK_MASK_CONST(0x3fffff)
+#define VI_PIN_OUTPUT_SELECT_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_READ_MASK                        _MK_MASK_CONST(0x3fffff)
+#define VI_PIN_OUTPUT_SELECT_0_WRITE_MASK                       _MK_MASK_CONST(0x3fffff)
+// Pin Output Select VD0
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd0_SHIFT                      _MK_SHIFT_CONST(0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd0_FIELD                      (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd0_SHIFT)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd0_RANGE                      0:0
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd0_WOFFSET                    0x0
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd0_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Pin Output Select VD1
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd1_SHIFT                      _MK_SHIFT_CONST(1)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd1_FIELD                      (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd1_SHIFT)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd1_RANGE                      1:1
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd1_WOFFSET                    0x0
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Pin Output Select VD2
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd2_SHIFT                      _MK_SHIFT_CONST(2)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd2_FIELD                      (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd2_SHIFT)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd2_RANGE                      2:2
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd2_WOFFSET                    0x0
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd2_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd2_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Pin Output Select VD3
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd3_SHIFT                      _MK_SHIFT_CONST(3)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd3_FIELD                      (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd3_SHIFT)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd3_RANGE                      3:3
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd3_WOFFSET                    0x0
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd3_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd3_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Pin Output Select VD4
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd4_SHIFT                      _MK_SHIFT_CONST(4)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd4_FIELD                      (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd4_SHIFT)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd4_RANGE                      4:4
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd4_WOFFSET                    0x0
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd4_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd4_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd4_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd4_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Pin Output Select VD5
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd5_SHIFT                      _MK_SHIFT_CONST(5)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd5_FIELD                      (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd5_SHIFT)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd5_RANGE                      5:5
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd5_WOFFSET                    0x0
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd5_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd5_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd5_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd5_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Pin Output Select VD6
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd6_SHIFT                      _MK_SHIFT_CONST(6)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd6_FIELD                      (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd6_SHIFT)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd6_RANGE                      6:6
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd6_WOFFSET                    0x0
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd6_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd6_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd6_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd6_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Pin Output Select VD7
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd7_SHIFT                      _MK_SHIFT_CONST(7)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd7_FIELD                      (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd7_SHIFT)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd7_RANGE                      7:7
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd7_WOFFSET                    0x0
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd7_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd7_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd7_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd7_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Pin Output Select VD8
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd8_SHIFT                      _MK_SHIFT_CONST(8)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd8_FIELD                      (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd8_SHIFT)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd8_RANGE                      8:8
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd8_WOFFSET                    0x0
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd8_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd8_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd8_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd8_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Pin Output Select VD9
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd9_SHIFT                      _MK_SHIFT_CONST(9)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd9_FIELD                      (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd9_SHIFT)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd9_RANGE                      9:9
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd9_WOFFSET                    0x0
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd9_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd9_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd9_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd9_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Pin Output Select VD10
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd10_SHIFT                     _MK_SHIFT_CONST(10)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd10_FIELD                     (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd10_SHIFT)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd10_RANGE                     10:10
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd10_WOFFSET                   0x0
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd10_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd10_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd10_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd10_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Pin Output Select VD11
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd11_SHIFT                     _MK_SHIFT_CONST(11)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd11_FIELD                     (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd11_SHIFT)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd11_RANGE                     11:11
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd11_WOFFSET                   0x0
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd11_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd11_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd11_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd11_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Pin Output Select VCLK
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vclk_SHIFT                     _MK_SHIFT_CONST(12)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vclk_FIELD                     (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vclk_SHIFT)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vclk_RANGE                     12:12
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vclk_WOFFSET                   0x0
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vclk_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vclk_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vclk_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vclk_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Pin Output Select VHSYNC
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vhs_SHIFT                      _MK_SHIFT_CONST(13)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vhs_FIELD                      (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vhs_SHIFT)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vhs_RANGE                      13:13
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vhs_WOFFSET                    0x0
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vhs_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vhs_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vhs_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vhs_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Pin Output Select VVSYNC
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vvs_SHIFT                      _MK_SHIFT_CONST(14)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vvs_FIELD                      (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vvs_SHIFT)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vvs_RANGE                      14:14
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vvs_WOFFSET                    0x0
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vvs_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vvs_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vvs_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vvs_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Pin Output Select VGP0
+//  0 = VGP0 output register
+//  1 = refclk
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp0_SHIFT                     _MK_SHIFT_CONST(15)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp0_FIELD                     (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp0_SHIFT)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp0_RANGE                     15:15
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp0_WOFFSET                   0x0
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp0_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp0_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Pin Output Select VGP1
+//  0 = I^2C SCK pin
+//  1 = 1'b0
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp1_SHIFT                     _MK_SHIFT_CONST(16)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp1_FIELD                     (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp1_SHIFT)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp1_RANGE                     16:16
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp1_WOFFSET                   0x0
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp1_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp1_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Pin Output Select VGP2
+//  0 = I^2C SDA pin
+//  1 = 1'b0
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp2_SHIFT                     _MK_SHIFT_CONST(17)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp2_FIELD                     (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp2_SHIFT)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp2_RANGE                     17:17
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp2_WOFFSET                   0x0
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp2_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp2_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Pin Output Select VGP3
+//  0 = VGP3 output register
+//  1 = 1'b0
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp3_SHIFT                     _MK_SHIFT_CONST(18)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp3_FIELD                     (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp3_SHIFT)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp3_RANGE                     18:18
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp3_WOFFSET                   0x0
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp3_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp3_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp3_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp3_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Pin Output Select VGP4
+//  0 = VGP4 output register
+//  1 = 1'b0
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp4_SHIFT                     _MK_SHIFT_CONST(19)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp4_FIELD                     (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp4_SHIFT)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp4_RANGE                     19:19
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp4_WOFFSET                   0x0
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp4_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp4_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp4_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp4_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Pin Output Select VGP5
+//  0 = VGP5 output register
+//  1 = 1'b0
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp5_SHIFT                     _MK_SHIFT_CONST(20)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp5_FIELD                     (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp5_SHIFT)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp5_RANGE                     20:20
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp5_WOFFSET                   0x0
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp5_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp5_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp5_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp5_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Pin Output Select VGP6   0= select VGP6 register data out
+//   1= select PWM out
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp6_SHIFT                     _MK_SHIFT_CONST(21)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp6_FIELD                     (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp6_SHIFT)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp6_RANGE                     21:21
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp6_WOFFSET                   0x0
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp6_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp6_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp6_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp6_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp6_DATA                      _MK_ENUM_CONST(0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp6_PWM                       _MK_ENUM_CONST(1)
+
+
+// Register VI_RAISE_VIP_BUFFER_FIRST_OUTPUT_0  // raise vector at buffer end
+#define VI_RAISE_VIP_BUFFER_FIRST_OUTPUT_0                      _MK_ADDR_CONST(0x61)
+#define VI_RAISE_VIP_BUFFER_FIRST_OUTPUT_0_WORD_COUNT                   0x1
+#define VI_RAISE_VIP_BUFFER_FIRST_OUTPUT_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define VI_RAISE_VIP_BUFFER_FIRST_OUTPUT_0_RESET_MASK                   _MK_MASK_CONST(0x0)
+#define VI_RAISE_VIP_BUFFER_FIRST_OUTPUT_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define VI_RAISE_VIP_BUFFER_FIRST_OUTPUT_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_RAISE_VIP_BUFFER_FIRST_OUTPUT_0_READ_MASK                    _MK_MASK_CONST(0x1f)
+#define VI_RAISE_VIP_BUFFER_FIRST_OUTPUT_0_WRITE_MASK                   _MK_MASK_CONST(0xf001f)
+#define VI_RAISE_VIP_BUFFER_FIRST_OUTPUT_0_RAISE_BUFFER_1_VECTOR_SHIFT                  _MK_SHIFT_CONST(0)
+#define VI_RAISE_VIP_BUFFER_FIRST_OUTPUT_0_RAISE_BUFFER_1_VECTOR_FIELD                  (_MK_MASK_CONST(0x1f) << VI_RAISE_VIP_BUFFER_FIRST_OUTPUT_0_RAISE_BUFFER_1_VECTOR_SHIFT)
+#define VI_RAISE_VIP_BUFFER_FIRST_OUTPUT_0_RAISE_BUFFER_1_VECTOR_RANGE                  4:0
+#define VI_RAISE_VIP_BUFFER_FIRST_OUTPUT_0_RAISE_BUFFER_1_VECTOR_WOFFSET                        0x0
+#define VI_RAISE_VIP_BUFFER_FIRST_OUTPUT_0_RAISE_BUFFER_1_VECTOR_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_RAISE_VIP_BUFFER_FIRST_OUTPUT_0_RAISE_BUFFER_1_VECTOR_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_RAISE_VIP_BUFFER_FIRST_OUTPUT_0_RAISE_BUFFER_1_VECTOR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_RAISE_VIP_BUFFER_FIRST_OUTPUT_0_RAISE_BUFFER_1_VECTOR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define VI_RAISE_VIP_BUFFER_FIRST_OUTPUT_0_RAISE_BUFFER_1_CHANNEL_SHIFT                 _MK_SHIFT_CONST(16)
+#define VI_RAISE_VIP_BUFFER_FIRST_OUTPUT_0_RAISE_BUFFER_1_CHANNEL_FIELD                 (_MK_MASK_CONST(0xf) << VI_RAISE_VIP_BUFFER_FIRST_OUTPUT_0_RAISE_BUFFER_1_CHANNEL_SHIFT)
+#define VI_RAISE_VIP_BUFFER_FIRST_OUTPUT_0_RAISE_BUFFER_1_CHANNEL_RANGE                 19:16
+#define VI_RAISE_VIP_BUFFER_FIRST_OUTPUT_0_RAISE_BUFFER_1_CHANNEL_WOFFSET                       0x0
+#define VI_RAISE_VIP_BUFFER_FIRST_OUTPUT_0_RAISE_BUFFER_1_CHANNEL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_RAISE_VIP_BUFFER_FIRST_OUTPUT_0_RAISE_BUFFER_1_CHANNEL_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_RAISE_VIP_BUFFER_FIRST_OUTPUT_0_RAISE_BUFFER_1_CHANNEL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_RAISE_VIP_BUFFER_FIRST_OUTPUT_0_RAISE_BUFFER_1_CHANNEL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register VI_RAISE_VIP_FRAME_FIRST_OUTPUT_0  // raise vector at frame end
+#define VI_RAISE_VIP_FRAME_FIRST_OUTPUT_0                       _MK_ADDR_CONST(0x62)
+#define VI_RAISE_VIP_FRAME_FIRST_OUTPUT_0_WORD_COUNT                    0x1
+#define VI_RAISE_VIP_FRAME_FIRST_OUTPUT_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define VI_RAISE_VIP_FRAME_FIRST_OUTPUT_0_RESET_MASK                    _MK_MASK_CONST(0x0)
+#define VI_RAISE_VIP_FRAME_FIRST_OUTPUT_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define VI_RAISE_VIP_FRAME_FIRST_OUTPUT_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_RAISE_VIP_FRAME_FIRST_OUTPUT_0_READ_MASK                     _MK_MASK_CONST(0x1f)
+#define VI_RAISE_VIP_FRAME_FIRST_OUTPUT_0_WRITE_MASK                    _MK_MASK_CONST(0xf001f)
+#define VI_RAISE_VIP_FRAME_FIRST_OUTPUT_0_RAISE_FRAME_1_VECTOR_SHIFT                    _MK_SHIFT_CONST(0)
+#define VI_RAISE_VIP_FRAME_FIRST_OUTPUT_0_RAISE_FRAME_1_VECTOR_FIELD                    (_MK_MASK_CONST(0x1f) << VI_RAISE_VIP_FRAME_FIRST_OUTPUT_0_RAISE_FRAME_1_VECTOR_SHIFT)
+#define VI_RAISE_VIP_FRAME_FIRST_OUTPUT_0_RAISE_FRAME_1_VECTOR_RANGE                    4:0
+#define VI_RAISE_VIP_FRAME_FIRST_OUTPUT_0_RAISE_FRAME_1_VECTOR_WOFFSET                  0x0
+#define VI_RAISE_VIP_FRAME_FIRST_OUTPUT_0_RAISE_FRAME_1_VECTOR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_RAISE_VIP_FRAME_FIRST_OUTPUT_0_RAISE_FRAME_1_VECTOR_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_RAISE_VIP_FRAME_FIRST_OUTPUT_0_RAISE_FRAME_1_VECTOR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_RAISE_VIP_FRAME_FIRST_OUTPUT_0_RAISE_FRAME_1_VECTOR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define VI_RAISE_VIP_FRAME_FIRST_OUTPUT_0_RAISE_FRAME_1_CHANNEL_SHIFT                   _MK_SHIFT_CONST(16)
+#define VI_RAISE_VIP_FRAME_FIRST_OUTPUT_0_RAISE_FRAME_1_CHANNEL_FIELD                   (_MK_MASK_CONST(0xf) << VI_RAISE_VIP_FRAME_FIRST_OUTPUT_0_RAISE_FRAME_1_CHANNEL_SHIFT)
+#define VI_RAISE_VIP_FRAME_FIRST_OUTPUT_0_RAISE_FRAME_1_CHANNEL_RANGE                   19:16
+#define VI_RAISE_VIP_FRAME_FIRST_OUTPUT_0_RAISE_FRAME_1_CHANNEL_WOFFSET                 0x0
+#define VI_RAISE_VIP_FRAME_FIRST_OUTPUT_0_RAISE_FRAME_1_CHANNEL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_RAISE_VIP_FRAME_FIRST_OUTPUT_0_RAISE_FRAME_1_CHANNEL_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_RAISE_VIP_FRAME_FIRST_OUTPUT_0_RAISE_FRAME_1_CHANNEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_RAISE_VIP_FRAME_FIRST_OUTPUT_0_RAISE_FRAME_1_CHANNEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register VI_RAISE_VIP_BUFFER_SECOND_OUTPUT_0  // raise vector at buffer end
+#define VI_RAISE_VIP_BUFFER_SECOND_OUTPUT_0                     _MK_ADDR_CONST(0x63)
+#define VI_RAISE_VIP_BUFFER_SECOND_OUTPUT_0_WORD_COUNT                  0x1
+#define VI_RAISE_VIP_BUFFER_SECOND_OUTPUT_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define VI_RAISE_VIP_BUFFER_SECOND_OUTPUT_0_RESET_MASK                  _MK_MASK_CONST(0x0)
+#define VI_RAISE_VIP_BUFFER_SECOND_OUTPUT_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define VI_RAISE_VIP_BUFFER_SECOND_OUTPUT_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_RAISE_VIP_BUFFER_SECOND_OUTPUT_0_READ_MASK                   _MK_MASK_CONST(0x1f)
+#define VI_RAISE_VIP_BUFFER_SECOND_OUTPUT_0_WRITE_MASK                  _MK_MASK_CONST(0xf001f)
+#define VI_RAISE_VIP_BUFFER_SECOND_OUTPUT_0_RAISE_BUFFER_2_VECTOR_SHIFT                 _MK_SHIFT_CONST(0)
+#define VI_RAISE_VIP_BUFFER_SECOND_OUTPUT_0_RAISE_BUFFER_2_VECTOR_FIELD                 (_MK_MASK_CONST(0x1f) << VI_RAISE_VIP_BUFFER_SECOND_OUTPUT_0_RAISE_BUFFER_2_VECTOR_SHIFT)
+#define VI_RAISE_VIP_BUFFER_SECOND_OUTPUT_0_RAISE_BUFFER_2_VECTOR_RANGE                 4:0
+#define VI_RAISE_VIP_BUFFER_SECOND_OUTPUT_0_RAISE_BUFFER_2_VECTOR_WOFFSET                       0x0
+#define VI_RAISE_VIP_BUFFER_SECOND_OUTPUT_0_RAISE_BUFFER_2_VECTOR_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_RAISE_VIP_BUFFER_SECOND_OUTPUT_0_RAISE_BUFFER_2_VECTOR_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_RAISE_VIP_BUFFER_SECOND_OUTPUT_0_RAISE_BUFFER_2_VECTOR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_RAISE_VIP_BUFFER_SECOND_OUTPUT_0_RAISE_BUFFER_2_VECTOR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define VI_RAISE_VIP_BUFFER_SECOND_OUTPUT_0_RAISE_BUFFER_2_CHANNEL_SHIFT                        _MK_SHIFT_CONST(16)
+#define VI_RAISE_VIP_BUFFER_SECOND_OUTPUT_0_RAISE_BUFFER_2_CHANNEL_FIELD                        (_MK_MASK_CONST(0xf) << VI_RAISE_VIP_BUFFER_SECOND_OUTPUT_0_RAISE_BUFFER_2_CHANNEL_SHIFT)
+#define VI_RAISE_VIP_BUFFER_SECOND_OUTPUT_0_RAISE_BUFFER_2_CHANNEL_RANGE                        19:16
+#define VI_RAISE_VIP_BUFFER_SECOND_OUTPUT_0_RAISE_BUFFER_2_CHANNEL_WOFFSET                      0x0
+#define VI_RAISE_VIP_BUFFER_SECOND_OUTPUT_0_RAISE_BUFFER_2_CHANNEL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_RAISE_VIP_BUFFER_SECOND_OUTPUT_0_RAISE_BUFFER_2_CHANNEL_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_RAISE_VIP_BUFFER_SECOND_OUTPUT_0_RAISE_BUFFER_2_CHANNEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_RAISE_VIP_BUFFER_SECOND_OUTPUT_0_RAISE_BUFFER_2_CHANNEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register VI_RAISE_VIP_FRAME_SECOND_OUTPUT_0  // raise vector at frame end
+#define VI_RAISE_VIP_FRAME_SECOND_OUTPUT_0                      _MK_ADDR_CONST(0x64)
+#define VI_RAISE_VIP_FRAME_SECOND_OUTPUT_0_WORD_COUNT                   0x1
+#define VI_RAISE_VIP_FRAME_SECOND_OUTPUT_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define VI_RAISE_VIP_FRAME_SECOND_OUTPUT_0_RESET_MASK                   _MK_MASK_CONST(0x0)
+#define VI_RAISE_VIP_FRAME_SECOND_OUTPUT_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define VI_RAISE_VIP_FRAME_SECOND_OUTPUT_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_RAISE_VIP_FRAME_SECOND_OUTPUT_0_READ_MASK                    _MK_MASK_CONST(0x1f)
+#define VI_RAISE_VIP_FRAME_SECOND_OUTPUT_0_WRITE_MASK                   _MK_MASK_CONST(0xf001f)
+#define VI_RAISE_VIP_FRAME_SECOND_OUTPUT_0_RAISE_FRAME_2_VECTOR_SHIFT                   _MK_SHIFT_CONST(0)
+#define VI_RAISE_VIP_FRAME_SECOND_OUTPUT_0_RAISE_FRAME_2_VECTOR_FIELD                   (_MK_MASK_CONST(0x1f) << VI_RAISE_VIP_FRAME_SECOND_OUTPUT_0_RAISE_FRAME_2_VECTOR_SHIFT)
+#define VI_RAISE_VIP_FRAME_SECOND_OUTPUT_0_RAISE_FRAME_2_VECTOR_RANGE                   4:0
+#define VI_RAISE_VIP_FRAME_SECOND_OUTPUT_0_RAISE_FRAME_2_VECTOR_WOFFSET                 0x0
+#define VI_RAISE_VIP_FRAME_SECOND_OUTPUT_0_RAISE_FRAME_2_VECTOR_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_RAISE_VIP_FRAME_SECOND_OUTPUT_0_RAISE_FRAME_2_VECTOR_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_RAISE_VIP_FRAME_SECOND_OUTPUT_0_RAISE_FRAME_2_VECTOR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_RAISE_VIP_FRAME_SECOND_OUTPUT_0_RAISE_FRAME_2_VECTOR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define VI_RAISE_VIP_FRAME_SECOND_OUTPUT_0_RAISE_FRAME_2_CHANNEL_SHIFT                  _MK_SHIFT_CONST(16)
+#define VI_RAISE_VIP_FRAME_SECOND_OUTPUT_0_RAISE_FRAME_2_CHANNEL_FIELD                  (_MK_MASK_CONST(0xf) << VI_RAISE_VIP_FRAME_SECOND_OUTPUT_0_RAISE_FRAME_2_CHANNEL_SHIFT)
+#define VI_RAISE_VIP_FRAME_SECOND_OUTPUT_0_RAISE_FRAME_2_CHANNEL_RANGE                  19:16
+#define VI_RAISE_VIP_FRAME_SECOND_OUTPUT_0_RAISE_FRAME_2_CHANNEL_WOFFSET                        0x0
+#define VI_RAISE_VIP_FRAME_SECOND_OUTPUT_0_RAISE_FRAME_2_CHANNEL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_RAISE_VIP_FRAME_SECOND_OUTPUT_0_RAISE_FRAME_2_CHANNEL_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_RAISE_VIP_FRAME_SECOND_OUTPUT_0_RAISE_FRAME_2_CHANNEL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_RAISE_VIP_FRAME_SECOND_OUTPUT_0_RAISE_FRAME_2_CHANNEL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register VI_RAISE_HOST_FIRST_OUTPUT_0  // raise vector when from host
+#define VI_RAISE_HOST_FIRST_OUTPUT_0                    _MK_ADDR_CONST(0x65)
+#define VI_RAISE_HOST_FIRST_OUTPUT_0_WORD_COUNT                         0x1
+#define VI_RAISE_HOST_FIRST_OUTPUT_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define VI_RAISE_HOST_FIRST_OUTPUT_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define VI_RAISE_HOST_FIRST_OUTPUT_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define VI_RAISE_HOST_FIRST_OUTPUT_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_RAISE_HOST_FIRST_OUTPUT_0_READ_MASK                  _MK_MASK_CONST(0x1f)
+#define VI_RAISE_HOST_FIRST_OUTPUT_0_WRITE_MASK                         _MK_MASK_CONST(0xf001f)
+#define VI_RAISE_HOST_FIRST_OUTPUT_0_RAISE_HOST_1_VECTOR_SHIFT                  _MK_SHIFT_CONST(0)
+#define VI_RAISE_HOST_FIRST_OUTPUT_0_RAISE_HOST_1_VECTOR_FIELD                  (_MK_MASK_CONST(0x1f) << VI_RAISE_HOST_FIRST_OUTPUT_0_RAISE_HOST_1_VECTOR_SHIFT)
+#define VI_RAISE_HOST_FIRST_OUTPUT_0_RAISE_HOST_1_VECTOR_RANGE                  4:0
+#define VI_RAISE_HOST_FIRST_OUTPUT_0_RAISE_HOST_1_VECTOR_WOFFSET                        0x0
+#define VI_RAISE_HOST_FIRST_OUTPUT_0_RAISE_HOST_1_VECTOR_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_RAISE_HOST_FIRST_OUTPUT_0_RAISE_HOST_1_VECTOR_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_RAISE_HOST_FIRST_OUTPUT_0_RAISE_HOST_1_VECTOR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_RAISE_HOST_FIRST_OUTPUT_0_RAISE_HOST_1_VECTOR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define VI_RAISE_HOST_FIRST_OUTPUT_0_RAISE_HOST_1_CHANNEL_SHIFT                 _MK_SHIFT_CONST(16)
+#define VI_RAISE_HOST_FIRST_OUTPUT_0_RAISE_HOST_1_CHANNEL_FIELD                 (_MK_MASK_CONST(0xf) << VI_RAISE_HOST_FIRST_OUTPUT_0_RAISE_HOST_1_CHANNEL_SHIFT)
+#define VI_RAISE_HOST_FIRST_OUTPUT_0_RAISE_HOST_1_CHANNEL_RANGE                 19:16
+#define VI_RAISE_HOST_FIRST_OUTPUT_0_RAISE_HOST_1_CHANNEL_WOFFSET                       0x0
+#define VI_RAISE_HOST_FIRST_OUTPUT_0_RAISE_HOST_1_CHANNEL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_RAISE_HOST_FIRST_OUTPUT_0_RAISE_HOST_1_CHANNEL_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_RAISE_HOST_FIRST_OUTPUT_0_RAISE_HOST_1_CHANNEL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_RAISE_HOST_FIRST_OUTPUT_0_RAISE_HOST_1_CHANNEL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register VI_RAISE_HOST_SECOND_OUTPUT_0  // raise vector when from host
+#define VI_RAISE_HOST_SECOND_OUTPUT_0                   _MK_ADDR_CONST(0x66)
+#define VI_RAISE_HOST_SECOND_OUTPUT_0_WORD_COUNT                        0x1
+#define VI_RAISE_HOST_SECOND_OUTPUT_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define VI_RAISE_HOST_SECOND_OUTPUT_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define VI_RAISE_HOST_SECOND_OUTPUT_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define VI_RAISE_HOST_SECOND_OUTPUT_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_RAISE_HOST_SECOND_OUTPUT_0_READ_MASK                         _MK_MASK_CONST(0x1f)
+#define VI_RAISE_HOST_SECOND_OUTPUT_0_WRITE_MASK                        _MK_MASK_CONST(0xf001f)
+#define VI_RAISE_HOST_SECOND_OUTPUT_0_RAISE_HOST_2_VECTOR_SHIFT                 _MK_SHIFT_CONST(0)
+#define VI_RAISE_HOST_SECOND_OUTPUT_0_RAISE_HOST_2_VECTOR_FIELD                 (_MK_MASK_CONST(0x1f) << VI_RAISE_HOST_SECOND_OUTPUT_0_RAISE_HOST_2_VECTOR_SHIFT)
+#define VI_RAISE_HOST_SECOND_OUTPUT_0_RAISE_HOST_2_VECTOR_RANGE                 4:0
+#define VI_RAISE_HOST_SECOND_OUTPUT_0_RAISE_HOST_2_VECTOR_WOFFSET                       0x0
+#define VI_RAISE_HOST_SECOND_OUTPUT_0_RAISE_HOST_2_VECTOR_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_RAISE_HOST_SECOND_OUTPUT_0_RAISE_HOST_2_VECTOR_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_RAISE_HOST_SECOND_OUTPUT_0_RAISE_HOST_2_VECTOR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_RAISE_HOST_SECOND_OUTPUT_0_RAISE_HOST_2_VECTOR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define VI_RAISE_HOST_SECOND_OUTPUT_0_RAISE_HOST_2_CHANNEL_SHIFT                        _MK_SHIFT_CONST(16)
+#define VI_RAISE_HOST_SECOND_OUTPUT_0_RAISE_HOST_2_CHANNEL_FIELD                        (_MK_MASK_CONST(0xf) << VI_RAISE_HOST_SECOND_OUTPUT_0_RAISE_HOST_2_CHANNEL_SHIFT)
+#define VI_RAISE_HOST_SECOND_OUTPUT_0_RAISE_HOST_2_CHANNEL_RANGE                        19:16
+#define VI_RAISE_HOST_SECOND_OUTPUT_0_RAISE_HOST_2_CHANNEL_WOFFSET                      0x0
+#define VI_RAISE_HOST_SECOND_OUTPUT_0_RAISE_HOST_2_CHANNEL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_RAISE_HOST_SECOND_OUTPUT_0_RAISE_HOST_2_CHANNEL_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_RAISE_HOST_SECOND_OUTPUT_0_RAISE_HOST_2_CHANNEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_RAISE_HOST_SECOND_OUTPUT_0_RAISE_HOST_2_CHANNEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register VI_RAISE_EPP_0  // raise vector at line end
+#define VI_RAISE_EPP_0                  _MK_ADDR_CONST(0x67)
+#define VI_RAISE_EPP_0_WORD_COUNT                       0x1
+#define VI_RAISE_EPP_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define VI_RAISE_EPP_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define VI_RAISE_EPP_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define VI_RAISE_EPP_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_RAISE_EPP_0_READ_MASK                        _MK_MASK_CONST(0x1f)
+#define VI_RAISE_EPP_0_WRITE_MASK                       _MK_MASK_CONST(0xf001f)
+#define VI_RAISE_EPP_0_RAISE_EPP_VECTOR_SHIFT                   _MK_SHIFT_CONST(0)
+#define VI_RAISE_EPP_0_RAISE_EPP_VECTOR_FIELD                   (_MK_MASK_CONST(0x1f) << VI_RAISE_EPP_0_RAISE_EPP_VECTOR_SHIFT)
+#define VI_RAISE_EPP_0_RAISE_EPP_VECTOR_RANGE                   4:0
+#define VI_RAISE_EPP_0_RAISE_EPP_VECTOR_WOFFSET                 0x0
+#define VI_RAISE_EPP_0_RAISE_EPP_VECTOR_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_RAISE_EPP_0_RAISE_EPP_VECTOR_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_RAISE_EPP_0_RAISE_EPP_VECTOR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_RAISE_EPP_0_RAISE_EPP_VECTOR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define VI_RAISE_EPP_0_RAISE_EPP_CHANNEL_SHIFT                  _MK_SHIFT_CONST(16)
+#define VI_RAISE_EPP_0_RAISE_EPP_CHANNEL_FIELD                  (_MK_MASK_CONST(0xf) << VI_RAISE_EPP_0_RAISE_EPP_CHANNEL_SHIFT)
+#define VI_RAISE_EPP_0_RAISE_EPP_CHANNEL_RANGE                  19:16
+#define VI_RAISE_EPP_0_RAISE_EPP_CHANNEL_WOFFSET                        0x0
+#define VI_RAISE_EPP_0_RAISE_EPP_CHANNEL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_RAISE_EPP_0_RAISE_EPP_CHANNEL_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_RAISE_EPP_0_RAISE_EPP_CHANNEL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_RAISE_EPP_0_RAISE_EPP_CHANNEL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register VI_CAMERA_CONTROL_0  // VI camera control bits
+#define VI_CAMERA_CONTROL_0                     _MK_ADDR_CONST(0x68)
+#define VI_CAMERA_CONTROL_0_WORD_COUNT                  0x1
+#define VI_CAMERA_CONTROL_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define VI_CAMERA_CONTROL_0_RESET_MASK                  _MK_MASK_CONST(0x7)
+#define VI_CAMERA_CONTROL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define VI_CAMERA_CONTROL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_CAMERA_CONTROL_0_READ_MASK                   _MK_MASK_CONST(0x7)
+#define VI_CAMERA_CONTROL_0_WRITE_MASK                  _MK_MASK_CONST(0x6)
+// VI camera input module Enable   0= Ignored - use the STOP_CAPTURE to turn off the capturing
+//   1= Enabled
+// Write a 1'b1 to this register to enable
+// the camera interface to start capturing data.
+#define VI_CAMERA_CONTROL_0_VIP_ENABLE_SHIFT                    _MK_SHIFT_CONST(0)
+#define VI_CAMERA_CONTROL_0_VIP_ENABLE_FIELD                    (_MK_MASK_CONST(0x1) << VI_CAMERA_CONTROL_0_VIP_ENABLE_SHIFT)
+#define VI_CAMERA_CONTROL_0_VIP_ENABLE_RANGE                    0:0
+#define VI_CAMERA_CONTROL_0_VIP_ENABLE_WOFFSET                  0x0
+#define VI_CAMERA_CONTROL_0_VIP_ENABLE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_CAMERA_CONTROL_0_VIP_ENABLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define VI_CAMERA_CONTROL_0_VIP_ENABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_CAMERA_CONTROL_0_VIP_ENABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_CAMERA_CONTROL_0_VIP_ENABLE_DISABLED                 _MK_ENUM_CONST(0)
+#define VI_CAMERA_CONTROL_0_VIP_ENABLE_ENABLED                  _MK_ENUM_CONST(1)
+
+// Test Mode Enable   0= Disabled
+//   1= Enabled
+#define VI_CAMERA_CONTROL_0_TEST_MODE_ENABLE_SHIFT                      _MK_SHIFT_CONST(1)
+#define VI_CAMERA_CONTROL_0_TEST_MODE_ENABLE_FIELD                      (_MK_MASK_CONST(0x1) << VI_CAMERA_CONTROL_0_TEST_MODE_ENABLE_SHIFT)
+#define VI_CAMERA_CONTROL_0_TEST_MODE_ENABLE_RANGE                      1:1
+#define VI_CAMERA_CONTROL_0_TEST_MODE_ENABLE_WOFFSET                    0x0
+#define VI_CAMERA_CONTROL_0_TEST_MODE_ENABLE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_CAMERA_CONTROL_0_TEST_MODE_ENABLE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define VI_CAMERA_CONTROL_0_TEST_MODE_ENABLE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_CAMERA_CONTROL_0_TEST_MODE_ENABLE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_CAMERA_CONTROL_0_TEST_MODE_ENABLE_DISABLED                   _MK_ENUM_CONST(0)
+#define VI_CAMERA_CONTROL_0_TEST_MODE_ENABLE_ENABLED                    _MK_ENUM_CONST(1)
+
+// Disables camera capturing VI_ENABLE after the  next end of frame.
+//   0= Disabled
+//   1= Enabled
+#define VI_CAMERA_CONTROL_0_STOP_CAPTURE_SHIFT                  _MK_SHIFT_CONST(2)
+#define VI_CAMERA_CONTROL_0_STOP_CAPTURE_FIELD                  (_MK_MASK_CONST(0x1) << VI_CAMERA_CONTROL_0_STOP_CAPTURE_SHIFT)
+#define VI_CAMERA_CONTROL_0_STOP_CAPTURE_RANGE                  2:2
+#define VI_CAMERA_CONTROL_0_STOP_CAPTURE_WOFFSET                        0x0
+#define VI_CAMERA_CONTROL_0_STOP_CAPTURE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_CAMERA_CONTROL_0_STOP_CAPTURE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define VI_CAMERA_CONTROL_0_STOP_CAPTURE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_CAMERA_CONTROL_0_STOP_CAPTURE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_CAMERA_CONTROL_0_STOP_CAPTURE_DISABLED                       _MK_ENUM_CONST(0)
+#define VI_CAMERA_CONTROL_0_STOP_CAPTURE_ENABLED                        _MK_ENUM_CONST(1)
+
+
+// Register VI_VI_ENABLE_0  // VI Enables
+#define VI_VI_ENABLE_0                  _MK_ADDR_CONST(0x69)
+#define VI_VI_ENABLE_0_WORD_COUNT                       0x1
+#define VI_VI_ENABLE_0_RESET_VAL                        _MK_MASK_CONST(0x1)
+#define VI_VI_ENABLE_0_RESET_MASK                       _MK_MASK_CONST(0x3)
+#define VI_VI_ENABLE_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define VI_VI_ENABLE_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_VI_ENABLE_0_READ_MASK                        _MK_MASK_CONST(0x3)
+#define VI_VI_ENABLE_0_WRITE_MASK                       _MK_MASK_CONST(0x3)
+// First Output to Memory   0= Enabled
+//   1= Disabled
+#define VI_VI_ENABLE_0_FIRST_OUTPUT_TO_MEMORY_SHIFT                     _MK_SHIFT_CONST(0)
+#define VI_VI_ENABLE_0_FIRST_OUTPUT_TO_MEMORY_FIELD                     (_MK_MASK_CONST(0x1) << VI_VI_ENABLE_0_FIRST_OUTPUT_TO_MEMORY_SHIFT)
+#define VI_VI_ENABLE_0_FIRST_OUTPUT_TO_MEMORY_RANGE                     0:0
+#define VI_VI_ENABLE_0_FIRST_OUTPUT_TO_MEMORY_WOFFSET                   0x0
+#define VI_VI_ENABLE_0_FIRST_OUTPUT_TO_MEMORY_DEFAULT                   _MK_MASK_CONST(0x1)
+#define VI_VI_ENABLE_0_FIRST_OUTPUT_TO_MEMORY_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define VI_VI_ENABLE_0_FIRST_OUTPUT_TO_MEMORY_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_VI_ENABLE_0_FIRST_OUTPUT_TO_MEMORY_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_VI_ENABLE_0_FIRST_OUTPUT_TO_MEMORY_ENABLED                   _MK_ENUM_CONST(0)
+#define VI_VI_ENABLE_0_FIRST_OUTPUT_TO_MEMORY_DISABLED                  _MK_ENUM_CONST(1)
+
+// SW enable flow control for output1
+#define VI_VI_ENABLE_0_SW_FLOW_CONTROL_OUT1_SHIFT                       _MK_SHIFT_CONST(1)
+#define VI_VI_ENABLE_0_SW_FLOW_CONTROL_OUT1_FIELD                       (_MK_MASK_CONST(0x1) << VI_VI_ENABLE_0_SW_FLOW_CONTROL_OUT1_SHIFT)
+#define VI_VI_ENABLE_0_SW_FLOW_CONTROL_OUT1_RANGE                       1:1
+#define VI_VI_ENABLE_0_SW_FLOW_CONTROL_OUT1_WOFFSET                     0x0
+#define VI_VI_ENABLE_0_SW_FLOW_CONTROL_OUT1_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_VI_ENABLE_0_SW_FLOW_CONTROL_OUT1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define VI_VI_ENABLE_0_SW_FLOW_CONTROL_OUT1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_VI_ENABLE_0_SW_FLOW_CONTROL_OUT1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_VI_ENABLE_0_SW_FLOW_CONTROL_OUT1_DISABLE                     _MK_ENUM_CONST(0)
+#define VI_VI_ENABLE_0_SW_FLOW_CONTROL_OUT1_ENABLE                      _MK_ENUM_CONST(1)
+
+
+// Register VI_VI_ENABLE_2_0  // VI Enables second output
+#define VI_VI_ENABLE_2_0                        _MK_ADDR_CONST(0x6a)
+#define VI_VI_ENABLE_2_0_WORD_COUNT                     0x1
+#define VI_VI_ENABLE_2_0_RESET_VAL                      _MK_MASK_CONST(0x1)
+#define VI_VI_ENABLE_2_0_RESET_MASK                     _MK_MASK_CONST(0x3)
+#define VI_VI_ENABLE_2_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define VI_VI_ENABLE_2_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_VI_ENABLE_2_0_READ_MASK                      _MK_MASK_CONST(0x3)
+#define VI_VI_ENABLE_2_0_WRITE_MASK                     _MK_MASK_CONST(0x3)
+// Second Output to Memory   0= Enabled
+//   1= Disabled
+//  Disabling output to memory may be set
+//  if only output to encoder pre-processor
+//  is needed. This will also power-down
+//  all logic which is only used to send
+//  output data to memory.
+//   0= Disabled
+//   1= Enabled
+#define VI_VI_ENABLE_2_0_SECOND_OUTPUT_TO_MEMORY_SHIFT                  _MK_SHIFT_CONST(0)
+#define VI_VI_ENABLE_2_0_SECOND_OUTPUT_TO_MEMORY_FIELD                  (_MK_MASK_CONST(0x1) << VI_VI_ENABLE_2_0_SECOND_OUTPUT_TO_MEMORY_SHIFT)
+#define VI_VI_ENABLE_2_0_SECOND_OUTPUT_TO_MEMORY_RANGE                  0:0
+#define VI_VI_ENABLE_2_0_SECOND_OUTPUT_TO_MEMORY_WOFFSET                        0x0
+#define VI_VI_ENABLE_2_0_SECOND_OUTPUT_TO_MEMORY_DEFAULT                        _MK_MASK_CONST(0x1)
+#define VI_VI_ENABLE_2_0_SECOND_OUTPUT_TO_MEMORY_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define VI_VI_ENABLE_2_0_SECOND_OUTPUT_TO_MEMORY_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_VI_ENABLE_2_0_SECOND_OUTPUT_TO_MEMORY_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_VI_ENABLE_2_0_SECOND_OUTPUT_TO_MEMORY_ENABLED                        _MK_ENUM_CONST(0)
+#define VI_VI_ENABLE_2_0_SECOND_OUTPUT_TO_MEMORY_DISABLED                       _MK_ENUM_CONST(1)
+
+// SW enable flow control for output2
+#define VI_VI_ENABLE_2_0_SW_FLOW_CONTROL_OUT2_SHIFT                     _MK_SHIFT_CONST(1)
+#define VI_VI_ENABLE_2_0_SW_FLOW_CONTROL_OUT2_FIELD                     (_MK_MASK_CONST(0x1) << VI_VI_ENABLE_2_0_SW_FLOW_CONTROL_OUT2_SHIFT)
+#define VI_VI_ENABLE_2_0_SW_FLOW_CONTROL_OUT2_RANGE                     1:1
+#define VI_VI_ENABLE_2_0_SW_FLOW_CONTROL_OUT2_WOFFSET                   0x0
+#define VI_VI_ENABLE_2_0_SW_FLOW_CONTROL_OUT2_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_VI_ENABLE_2_0_SW_FLOW_CONTROL_OUT2_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define VI_VI_ENABLE_2_0_SW_FLOW_CONTROL_OUT2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_VI_ENABLE_2_0_SW_FLOW_CONTROL_OUT2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_VI_ENABLE_2_0_SW_FLOW_CONTROL_OUT2_DISABLE                   _MK_ENUM_CONST(0)
+#define VI_VI_ENABLE_2_0_SW_FLOW_CONTROL_OUT2_ENABLE                    _MK_ENUM_CONST(1)
+
+
+// Register VI_VI_RAISE_0  // VI Enables second output
+#define VI_VI_RAISE_0                   _MK_ADDR_CONST(0x6b)
+#define VI_VI_RAISE_0_WORD_COUNT                        0x1
+#define VI_VI_RAISE_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define VI_VI_RAISE_0_RESET_MASK                        _MK_MASK_CONST(0x1)
+#define VI_VI_RAISE_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define VI_VI_RAISE_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_VI_RAISE_0_READ_MASK                         _MK_MASK_CONST(0x1)
+#define VI_VI_RAISE_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
+// Makes Raises edge triggered not level sensitive  i.e. only return raise at the end of frame, not
+//  in the middle of the v-blank time.
+//   0= Disabled
+//   1= Enabled
+#define VI_VI_RAISE_0_RAISE_ON_EDGE_SHIFT                       _MK_SHIFT_CONST(0)
+#define VI_VI_RAISE_0_RAISE_ON_EDGE_FIELD                       (_MK_MASK_CONST(0x1) << VI_VI_RAISE_0_RAISE_ON_EDGE_SHIFT)
+#define VI_VI_RAISE_0_RAISE_ON_EDGE_RANGE                       0:0
+#define VI_VI_RAISE_0_RAISE_ON_EDGE_WOFFSET                     0x0
+#define VI_VI_RAISE_0_RAISE_ON_EDGE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_VI_RAISE_0_RAISE_ON_EDGE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define VI_VI_RAISE_0_RAISE_ON_EDGE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_VI_RAISE_0_RAISE_ON_EDGE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_VI_RAISE_0_RAISE_ON_EDGE_DISABLED                    _MK_ENUM_CONST(0)
+#define VI_VI_RAISE_0_RAISE_ON_EDGE_ENABLED                     _MK_ENUM_CONST(1)
+
+
+// Register VI_Y_FIFO_WRITE_0  // YUV 4:2:0 Planar Y-FIFO, YUV 4:2:2 non-Planar YUV FIFO
+#define VI_Y_FIFO_WRITE_0                       _MK_ADDR_CONST(0x6c)
+#define VI_Y_FIFO_WRITE_0_WORD_COUNT                    0x1
+#define VI_Y_FIFO_WRITE_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define VI_Y_FIFO_WRITE_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
+#define VI_Y_FIFO_WRITE_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define VI_Y_FIFO_WRITE_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_Y_FIFO_WRITE_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define VI_Y_FIFO_WRITE_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+#define VI_Y_FIFO_WRITE_0_Y_FIFO_DATA_SHIFT                     _MK_SHIFT_CONST(0)
+#define VI_Y_FIFO_WRITE_0_Y_FIFO_DATA_FIELD                     (_MK_MASK_CONST(0xffffffff) << VI_Y_FIFO_WRITE_0_Y_FIFO_DATA_SHIFT)
+#define VI_Y_FIFO_WRITE_0_Y_FIFO_DATA_RANGE                     31:0
+#define VI_Y_FIFO_WRITE_0_Y_FIFO_DATA_WOFFSET                   0x0
+#define VI_Y_FIFO_WRITE_0_Y_FIFO_DATA_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_Y_FIFO_WRITE_0_Y_FIFO_DATA_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define VI_Y_FIFO_WRITE_0_Y_FIFO_DATA_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_Y_FIFO_WRITE_0_Y_FIFO_DATA_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register VI_U_FIFO_WRITE_0  // YUV 4:2:0 Planar U-FIFO
+#define VI_U_FIFO_WRITE_0                       _MK_ADDR_CONST(0x6d)
+#define VI_U_FIFO_WRITE_0_WORD_COUNT                    0x1
+#define VI_U_FIFO_WRITE_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define VI_U_FIFO_WRITE_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
+#define VI_U_FIFO_WRITE_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define VI_U_FIFO_WRITE_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_U_FIFO_WRITE_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define VI_U_FIFO_WRITE_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+#define VI_U_FIFO_WRITE_0_U_FIFO_DATA_SHIFT                     _MK_SHIFT_CONST(0)
+#define VI_U_FIFO_WRITE_0_U_FIFO_DATA_FIELD                     (_MK_MASK_CONST(0xffffffff) << VI_U_FIFO_WRITE_0_U_FIFO_DATA_SHIFT)
+#define VI_U_FIFO_WRITE_0_U_FIFO_DATA_RANGE                     31:0
+#define VI_U_FIFO_WRITE_0_U_FIFO_DATA_WOFFSET                   0x0
+#define VI_U_FIFO_WRITE_0_U_FIFO_DATA_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_U_FIFO_WRITE_0_U_FIFO_DATA_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define VI_U_FIFO_WRITE_0_U_FIFO_DATA_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_U_FIFO_WRITE_0_U_FIFO_DATA_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register VI_V_FIFO_WRITE_0  // YUV 4:2:0 Planar V-FIFO
+#define VI_V_FIFO_WRITE_0                       _MK_ADDR_CONST(0x6e)
+#define VI_V_FIFO_WRITE_0_WORD_COUNT                    0x1
+#define VI_V_FIFO_WRITE_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define VI_V_FIFO_WRITE_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
+#define VI_V_FIFO_WRITE_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define VI_V_FIFO_WRITE_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_V_FIFO_WRITE_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define VI_V_FIFO_WRITE_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+#define VI_V_FIFO_WRITE_0_V_FIFO_DATA_SHIFT                     _MK_SHIFT_CONST(0)
+#define VI_V_FIFO_WRITE_0_V_FIFO_DATA_FIELD                     (_MK_MASK_CONST(0xffffffff) << VI_V_FIFO_WRITE_0_V_FIFO_DATA_SHIFT)
+#define VI_V_FIFO_WRITE_0_V_FIFO_DATA_RANGE                     31:0
+#define VI_V_FIFO_WRITE_0_V_FIFO_DATA_WOFFSET                   0x0
+#define VI_V_FIFO_WRITE_0_V_FIFO_DATA_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_V_FIFO_WRITE_0_V_FIFO_DATA_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define VI_V_FIFO_WRITE_0_V_FIFO_DATA_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_V_FIFO_WRITE_0_V_FIFO_DATA_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register VI_VI_MCCIF_FIFOCTRL_0  
+#define VI_VI_MCCIF_FIFOCTRL_0                  _MK_ADDR_CONST(0x6f)
+#define VI_VI_MCCIF_FIFOCTRL_0_WORD_COUNT                       0x1
+#define VI_VI_MCCIF_FIFOCTRL_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define VI_VI_MCCIF_FIFOCTRL_0_RESET_MASK                       _MK_MASK_CONST(0xf)
+#define VI_VI_MCCIF_FIFOCTRL_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define VI_VI_MCCIF_FIFOCTRL_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_VI_MCCIF_FIFOCTRL_0_READ_MASK                        _MK_MASK_CONST(0xf)
+#define VI_VI_MCCIF_FIFOCTRL_0_WRITE_MASK                       _MK_MASK_CONST(0xf)
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_WRCL_MCLE2X_SHIFT                       _MK_SHIFT_CONST(0)
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_WRCL_MCLE2X_FIELD                       (_MK_MASK_CONST(0x1) << VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_WRCL_MCLE2X_SHIFT)
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_WRCL_MCLE2X_RANGE                       0:0
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_WRCL_MCLE2X_WOFFSET                     0x0
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_WRCL_MCLE2X_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_WRCL_MCLE2X_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_WRCL_MCLE2X_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_WRCL_MCLE2X_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_WRCL_MCLE2X_INIT_ENUM                   DISABLE
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_WRCL_MCLE2X_DISABLE                     _MK_ENUM_CONST(0)
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_WRCL_MCLE2X_ENABLE                      _MK_ENUM_CONST(1)
+
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_RDMC_RDFAST_SHIFT                       _MK_SHIFT_CONST(1)
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_RDMC_RDFAST_FIELD                       (_MK_MASK_CONST(0x1) << VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_RDMC_RDFAST_SHIFT)
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_RDMC_RDFAST_RANGE                       1:1
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_RDMC_RDFAST_WOFFSET                     0x0
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_RDMC_RDFAST_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_RDMC_RDFAST_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_RDMC_RDFAST_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_RDMC_RDFAST_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_RDMC_RDFAST_INIT_ENUM                   DISABLE
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_RDMC_RDFAST_DISABLE                     _MK_ENUM_CONST(0)
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_RDMC_RDFAST_ENABLE                      _MK_ENUM_CONST(1)
+
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_WRMC_CLLE2X_SHIFT                       _MK_SHIFT_CONST(2)
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_WRMC_CLLE2X_FIELD                       (_MK_MASK_CONST(0x1) << VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_WRMC_CLLE2X_SHIFT)
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_WRMC_CLLE2X_RANGE                       2:2
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_WRMC_CLLE2X_WOFFSET                     0x0
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_WRMC_CLLE2X_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_WRMC_CLLE2X_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_WRMC_CLLE2X_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_WRMC_CLLE2X_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_WRMC_CLLE2X_INIT_ENUM                   DISABLE
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_WRMC_CLLE2X_DISABLE                     _MK_ENUM_CONST(0)
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_WRMC_CLLE2X_ENABLE                      _MK_ENUM_CONST(1)
+
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_RDCL_RDFAST_SHIFT                       _MK_SHIFT_CONST(3)
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_RDCL_RDFAST_FIELD                       (_MK_MASK_CONST(0x1) << VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_RDCL_RDFAST_SHIFT)
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_RDCL_RDFAST_RANGE                       3:3
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_RDCL_RDFAST_WOFFSET                     0x0
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_RDCL_RDFAST_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_RDCL_RDFAST_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_RDCL_RDFAST_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_RDCL_RDFAST_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_RDCL_RDFAST_INIT_ENUM                   DISABLE
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_RDCL_RDFAST_DISABLE                     _MK_ENUM_CONST(0)
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_RDCL_RDFAST_ENABLE                      _MK_ENUM_CONST(1)
+
+
+// Register VI_TIMEOUT_WCOAL_VI_0  
+#define VI_TIMEOUT_WCOAL_VI_0                   _MK_ADDR_CONST(0x70)
+#define VI_TIMEOUT_WCOAL_VI_0_WORD_COUNT                        0x1
+#define VI_TIMEOUT_WCOAL_VI_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define VI_TIMEOUT_WCOAL_VI_0_RESET_MASK                        _MK_MASK_CONST(0xffff)
+#define VI_TIMEOUT_WCOAL_VI_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define VI_TIMEOUT_WCOAL_VI_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_TIMEOUT_WCOAL_VI_0_READ_MASK                         _MK_MASK_CONST(0xffff)
+#define VI_TIMEOUT_WCOAL_VI_0_WRITE_MASK                        _MK_MASK_CONST(0xffff)
+#define VI_TIMEOUT_WCOAL_VI_0_VIWSB_WCOAL_TMVAL_SHIFT                   _MK_SHIFT_CONST(0)
+#define VI_TIMEOUT_WCOAL_VI_0_VIWSB_WCOAL_TMVAL_FIELD                   (_MK_MASK_CONST(0xf) << VI_TIMEOUT_WCOAL_VI_0_VIWSB_WCOAL_TMVAL_SHIFT)
+#define VI_TIMEOUT_WCOAL_VI_0_VIWSB_WCOAL_TMVAL_RANGE                   3:0
+#define VI_TIMEOUT_WCOAL_VI_0_VIWSB_WCOAL_TMVAL_WOFFSET                 0x0
+#define VI_TIMEOUT_WCOAL_VI_0_VIWSB_WCOAL_TMVAL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_TIMEOUT_WCOAL_VI_0_VIWSB_WCOAL_TMVAL_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define VI_TIMEOUT_WCOAL_VI_0_VIWSB_WCOAL_TMVAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_TIMEOUT_WCOAL_VI_0_VIWSB_WCOAL_TMVAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define VI_TIMEOUT_WCOAL_VI_0_VIWU_WCOAL_TMVAL_SHIFT                    _MK_SHIFT_CONST(4)
+#define VI_TIMEOUT_WCOAL_VI_0_VIWU_WCOAL_TMVAL_FIELD                    (_MK_MASK_CONST(0xf) << VI_TIMEOUT_WCOAL_VI_0_VIWU_WCOAL_TMVAL_SHIFT)
+#define VI_TIMEOUT_WCOAL_VI_0_VIWU_WCOAL_TMVAL_RANGE                    7:4
+#define VI_TIMEOUT_WCOAL_VI_0_VIWU_WCOAL_TMVAL_WOFFSET                  0x0
+#define VI_TIMEOUT_WCOAL_VI_0_VIWU_WCOAL_TMVAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_TIMEOUT_WCOAL_VI_0_VIWU_WCOAL_TMVAL_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
+#define VI_TIMEOUT_WCOAL_VI_0_VIWU_WCOAL_TMVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_TIMEOUT_WCOAL_VI_0_VIWU_WCOAL_TMVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define VI_TIMEOUT_WCOAL_VI_0_VIWV_WCOAL_TMVAL_SHIFT                    _MK_SHIFT_CONST(8)
+#define VI_TIMEOUT_WCOAL_VI_0_VIWV_WCOAL_TMVAL_FIELD                    (_MK_MASK_CONST(0xf) << VI_TIMEOUT_WCOAL_VI_0_VIWV_WCOAL_TMVAL_SHIFT)
+#define VI_TIMEOUT_WCOAL_VI_0_VIWV_WCOAL_TMVAL_RANGE                    11:8
+#define VI_TIMEOUT_WCOAL_VI_0_VIWV_WCOAL_TMVAL_WOFFSET                  0x0
+#define VI_TIMEOUT_WCOAL_VI_0_VIWV_WCOAL_TMVAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_TIMEOUT_WCOAL_VI_0_VIWV_WCOAL_TMVAL_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
+#define VI_TIMEOUT_WCOAL_VI_0_VIWV_WCOAL_TMVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_TIMEOUT_WCOAL_VI_0_VIWV_WCOAL_TMVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define VI_TIMEOUT_WCOAL_VI_0_VIWY_WCOAL_TMVAL_SHIFT                    _MK_SHIFT_CONST(12)
+#define VI_TIMEOUT_WCOAL_VI_0_VIWY_WCOAL_TMVAL_FIELD                    (_MK_MASK_CONST(0xf) << VI_TIMEOUT_WCOAL_VI_0_VIWY_WCOAL_TMVAL_SHIFT)
+#define VI_TIMEOUT_WCOAL_VI_0_VIWY_WCOAL_TMVAL_RANGE                    15:12
+#define VI_TIMEOUT_WCOAL_VI_0_VIWY_WCOAL_TMVAL_WOFFSET                  0x0
+#define VI_TIMEOUT_WCOAL_VI_0_VIWY_WCOAL_TMVAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_TIMEOUT_WCOAL_VI_0_VIWY_WCOAL_TMVAL_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
+#define VI_TIMEOUT_WCOAL_VI_0_VIWY_WCOAL_TMVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_TIMEOUT_WCOAL_VI_0_VIWY_WCOAL_TMVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register VI_MCCIF_VIRUV_HP_0  
+#define VI_MCCIF_VIRUV_HP_0                     _MK_ADDR_CONST(0x71)
+#define VI_MCCIF_VIRUV_HP_0_WORD_COUNT                  0x1
+#define VI_MCCIF_VIRUV_HP_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define VI_MCCIF_VIRUV_HP_0_RESET_MASK                  _MK_MASK_CONST(0x3f000f)
+#define VI_MCCIF_VIRUV_HP_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define VI_MCCIF_VIRUV_HP_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_MCCIF_VIRUV_HP_0_READ_MASK                   _MK_MASK_CONST(0x3f000f)
+#define VI_MCCIF_VIRUV_HP_0_WRITE_MASK                  _MK_MASK_CONST(0x3f000f)
+#define VI_MCCIF_VIRUV_HP_0_CBR_VIRUV2MC_HPTH_SHIFT                     _MK_SHIFT_CONST(0)
+#define VI_MCCIF_VIRUV_HP_0_CBR_VIRUV2MC_HPTH_FIELD                     (_MK_MASK_CONST(0xf) << VI_MCCIF_VIRUV_HP_0_CBR_VIRUV2MC_HPTH_SHIFT)
+#define VI_MCCIF_VIRUV_HP_0_CBR_VIRUV2MC_HPTH_RANGE                     3:0
+#define VI_MCCIF_VIRUV_HP_0_CBR_VIRUV2MC_HPTH_WOFFSET                   0x0
+#define VI_MCCIF_VIRUV_HP_0_CBR_VIRUV2MC_HPTH_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_MCCIF_VIRUV_HP_0_CBR_VIRUV2MC_HPTH_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define VI_MCCIF_VIRUV_HP_0_CBR_VIRUV2MC_HPTH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_MCCIF_VIRUV_HP_0_CBR_VIRUV2MC_HPTH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define VI_MCCIF_VIRUV_HP_0_CBR_VIRUV2MC_HPTM_SHIFT                     _MK_SHIFT_CONST(16)
+#define VI_MCCIF_VIRUV_HP_0_CBR_VIRUV2MC_HPTM_FIELD                     (_MK_MASK_CONST(0x3f) << VI_MCCIF_VIRUV_HP_0_CBR_VIRUV2MC_HPTM_SHIFT)
+#define VI_MCCIF_VIRUV_HP_0_CBR_VIRUV2MC_HPTM_RANGE                     21:16
+#define VI_MCCIF_VIRUV_HP_0_CBR_VIRUV2MC_HPTM_WOFFSET                   0x0
+#define VI_MCCIF_VIRUV_HP_0_CBR_VIRUV2MC_HPTM_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_MCCIF_VIRUV_HP_0_CBR_VIRUV2MC_HPTM_DEFAULT_MASK                      _MK_MASK_CONST(0x3f)
+#define VI_MCCIF_VIRUV_HP_0_CBR_VIRUV2MC_HPTM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_MCCIF_VIRUV_HP_0_CBR_VIRUV2MC_HPTM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register VI_MCCIF_VIWSB_HP_0  
+#define VI_MCCIF_VIWSB_HP_0                     _MK_ADDR_CONST(0x72)
+#define VI_MCCIF_VIWSB_HP_0_WORD_COUNT                  0x1
+#define VI_MCCIF_VIWSB_HP_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define VI_MCCIF_VIWSB_HP_0_RESET_MASK                  _MK_MASK_CONST(0x7f)
+#define VI_MCCIF_VIWSB_HP_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define VI_MCCIF_VIWSB_HP_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_MCCIF_VIWSB_HP_0_READ_MASK                   _MK_MASK_CONST(0x7f)
+#define VI_MCCIF_VIWSB_HP_0_WRITE_MASK                  _MK_MASK_CONST(0x7f)
+#define VI_MCCIF_VIWSB_HP_0_CBW_VIWSB2MC_HPTH_SHIFT                     _MK_SHIFT_CONST(0)
+#define VI_MCCIF_VIWSB_HP_0_CBW_VIWSB2MC_HPTH_FIELD                     (_MK_MASK_CONST(0x7f) << VI_MCCIF_VIWSB_HP_0_CBW_VIWSB2MC_HPTH_SHIFT)
+#define VI_MCCIF_VIWSB_HP_0_CBW_VIWSB2MC_HPTH_RANGE                     6:0
+#define VI_MCCIF_VIWSB_HP_0_CBW_VIWSB2MC_HPTH_WOFFSET                   0x0
+#define VI_MCCIF_VIWSB_HP_0_CBW_VIWSB2MC_HPTH_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_MCCIF_VIWSB_HP_0_CBW_VIWSB2MC_HPTH_DEFAULT_MASK                      _MK_MASK_CONST(0x7f)
+#define VI_MCCIF_VIWSB_HP_0_CBW_VIWSB2MC_HPTH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_MCCIF_VIWSB_HP_0_CBW_VIWSB2MC_HPTH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register VI_MCCIF_VIWU_HP_0  
+#define VI_MCCIF_VIWU_HP_0                      _MK_ADDR_CONST(0x73)
+#define VI_MCCIF_VIWU_HP_0_WORD_COUNT                   0x1
+#define VI_MCCIF_VIWU_HP_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define VI_MCCIF_VIWU_HP_0_RESET_MASK                   _MK_MASK_CONST(0x7f)
+#define VI_MCCIF_VIWU_HP_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define VI_MCCIF_VIWU_HP_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_MCCIF_VIWU_HP_0_READ_MASK                    _MK_MASK_CONST(0x7f)
+#define VI_MCCIF_VIWU_HP_0_WRITE_MASK                   _MK_MASK_CONST(0x7f)
+#define VI_MCCIF_VIWU_HP_0_CBW_VIWU2MC_HPTH_SHIFT                       _MK_SHIFT_CONST(0)
+#define VI_MCCIF_VIWU_HP_0_CBW_VIWU2MC_HPTH_FIELD                       (_MK_MASK_CONST(0x7f) << VI_MCCIF_VIWU_HP_0_CBW_VIWU2MC_HPTH_SHIFT)
+#define VI_MCCIF_VIWU_HP_0_CBW_VIWU2MC_HPTH_RANGE                       6:0
+#define VI_MCCIF_VIWU_HP_0_CBW_VIWU2MC_HPTH_WOFFSET                     0x0
+#define VI_MCCIF_VIWU_HP_0_CBW_VIWU2MC_HPTH_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_MCCIF_VIWU_HP_0_CBW_VIWU2MC_HPTH_DEFAULT_MASK                        _MK_MASK_CONST(0x7f)
+#define VI_MCCIF_VIWU_HP_0_CBW_VIWU2MC_HPTH_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_MCCIF_VIWU_HP_0_CBW_VIWU2MC_HPTH_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register VI_MCCIF_VIWV_HP_0  
+#define VI_MCCIF_VIWV_HP_0                      _MK_ADDR_CONST(0x74)
+#define VI_MCCIF_VIWV_HP_0_WORD_COUNT                   0x1
+#define VI_MCCIF_VIWV_HP_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define VI_MCCIF_VIWV_HP_0_RESET_MASK                   _MK_MASK_CONST(0x7f)
+#define VI_MCCIF_VIWV_HP_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define VI_MCCIF_VIWV_HP_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_MCCIF_VIWV_HP_0_READ_MASK                    _MK_MASK_CONST(0x7f)
+#define VI_MCCIF_VIWV_HP_0_WRITE_MASK                   _MK_MASK_CONST(0x7f)
+#define VI_MCCIF_VIWV_HP_0_CBW_VIWV2MC_HPTH_SHIFT                       _MK_SHIFT_CONST(0)
+#define VI_MCCIF_VIWV_HP_0_CBW_VIWV2MC_HPTH_FIELD                       (_MK_MASK_CONST(0x7f) << VI_MCCIF_VIWV_HP_0_CBW_VIWV2MC_HPTH_SHIFT)
+#define VI_MCCIF_VIWV_HP_0_CBW_VIWV2MC_HPTH_RANGE                       6:0
+#define VI_MCCIF_VIWV_HP_0_CBW_VIWV2MC_HPTH_WOFFSET                     0x0
+#define VI_MCCIF_VIWV_HP_0_CBW_VIWV2MC_HPTH_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_MCCIF_VIWV_HP_0_CBW_VIWV2MC_HPTH_DEFAULT_MASK                        _MK_MASK_CONST(0x7f)
+#define VI_MCCIF_VIWV_HP_0_CBW_VIWV2MC_HPTH_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_MCCIF_VIWV_HP_0_CBW_VIWV2MC_HPTH_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register VI_MCCIF_VIWY_HP_0  
+#define VI_MCCIF_VIWY_HP_0                      _MK_ADDR_CONST(0x75)
+#define VI_MCCIF_VIWY_HP_0_WORD_COUNT                   0x1
+#define VI_MCCIF_VIWY_HP_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define VI_MCCIF_VIWY_HP_0_RESET_MASK                   _MK_MASK_CONST(0x7f)
+#define VI_MCCIF_VIWY_HP_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define VI_MCCIF_VIWY_HP_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_MCCIF_VIWY_HP_0_READ_MASK                    _MK_MASK_CONST(0x7f)
+#define VI_MCCIF_VIWY_HP_0_WRITE_MASK                   _MK_MASK_CONST(0x7f)
+#define VI_MCCIF_VIWY_HP_0_CBW_VIWY2MC_HPTH_SHIFT                       _MK_SHIFT_CONST(0)
+#define VI_MCCIF_VIWY_HP_0_CBW_VIWY2MC_HPTH_FIELD                       (_MK_MASK_CONST(0x7f) << VI_MCCIF_VIWY_HP_0_CBW_VIWY2MC_HPTH_SHIFT)
+#define VI_MCCIF_VIWY_HP_0_CBW_VIWY2MC_HPTH_RANGE                       6:0
+#define VI_MCCIF_VIWY_HP_0_CBW_VIWY2MC_HPTH_WOFFSET                     0x0
+#define VI_MCCIF_VIWY_HP_0_CBW_VIWY2MC_HPTH_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_MCCIF_VIWY_HP_0_CBW_VIWY2MC_HPTH_DEFAULT_MASK                        _MK_MASK_CONST(0x7f)
+#define VI_MCCIF_VIWY_HP_0_CBW_VIWY2MC_HPTH_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_MCCIF_VIWY_HP_0_CBW_VIWY2MC_HPTH_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register VI_CSI_PPA_RAISE_FRAME_START_0  // CSI Pixel Parser A Raise
+#define VI_CSI_PPA_RAISE_FRAME_START_0                  _MK_ADDR_CONST(0x76)
+#define VI_CSI_PPA_RAISE_FRAME_START_0_WORD_COUNT                       0x1
+#define VI_CSI_PPA_RAISE_FRAME_START_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_RAISE_FRAME_START_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_RAISE_FRAME_START_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_RAISE_FRAME_START_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_RAISE_FRAME_START_0_READ_MASK                        _MK_MASK_CONST(0xfff1f)
+#define VI_CSI_PPA_RAISE_FRAME_START_0_WRITE_MASK                       _MK_MASK_CONST(0xfff1f)
+//   Raise returned by VI when CSI PPA
+//   issues a frame start to consumer.
+#define VI_CSI_PPA_RAISE_FRAME_START_0_CSI_PPA_RAISE_FRAME_START_VECTOR_SHIFT                   _MK_SHIFT_CONST(0)
+#define VI_CSI_PPA_RAISE_FRAME_START_0_CSI_PPA_RAISE_FRAME_START_VECTOR_FIELD                   (_MK_MASK_CONST(0x1f) << VI_CSI_PPA_RAISE_FRAME_START_0_CSI_PPA_RAISE_FRAME_START_VECTOR_SHIFT)
+#define VI_CSI_PPA_RAISE_FRAME_START_0_CSI_PPA_RAISE_FRAME_START_VECTOR_RANGE                   4:0
+#define VI_CSI_PPA_RAISE_FRAME_START_0_CSI_PPA_RAISE_FRAME_START_VECTOR_WOFFSET                 0x0
+#define VI_CSI_PPA_RAISE_FRAME_START_0_CSI_PPA_RAISE_FRAME_START_VECTOR_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_RAISE_FRAME_START_0_CSI_PPA_RAISE_FRAME_START_VECTOR_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_RAISE_FRAME_START_0_CSI_PPA_RAISE_FRAME_START_VECTOR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_RAISE_FRAME_START_0_CSI_PPA_RAISE_FRAME_START_VECTOR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+//   Number of frame start since last raise >= count for raise to be returned
+#define VI_CSI_PPA_RAISE_FRAME_START_0_CSI_PPA_RAISE_FRAME_START_COUNT_SHIFT                    _MK_SHIFT_CONST(8)
+#define VI_CSI_PPA_RAISE_FRAME_START_0_CSI_PPA_RAISE_FRAME_START_COUNT_FIELD                    (_MK_MASK_CONST(0xff) << VI_CSI_PPA_RAISE_FRAME_START_0_CSI_PPA_RAISE_FRAME_START_COUNT_SHIFT)
+#define VI_CSI_PPA_RAISE_FRAME_START_0_CSI_PPA_RAISE_FRAME_START_COUNT_RANGE                    15:8
+#define VI_CSI_PPA_RAISE_FRAME_START_0_CSI_PPA_RAISE_FRAME_START_COUNT_WOFFSET                  0x0
+#define VI_CSI_PPA_RAISE_FRAME_START_0_CSI_PPA_RAISE_FRAME_START_COUNT_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_RAISE_FRAME_START_0_CSI_PPA_RAISE_FRAME_START_COUNT_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_RAISE_FRAME_START_0_CSI_PPA_RAISE_FRAME_START_COUNT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_RAISE_FRAME_START_0_CSI_PPA_RAISE_FRAME_START_COUNT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+//   Raise return channel
+#define VI_CSI_PPA_RAISE_FRAME_START_0_CSI_PPA_RAISE_FRAME_START_CHANNEL_SHIFT                  _MK_SHIFT_CONST(16)
+#define VI_CSI_PPA_RAISE_FRAME_START_0_CSI_PPA_RAISE_FRAME_START_CHANNEL_FIELD                  (_MK_MASK_CONST(0xf) << VI_CSI_PPA_RAISE_FRAME_START_0_CSI_PPA_RAISE_FRAME_START_CHANNEL_SHIFT)
+#define VI_CSI_PPA_RAISE_FRAME_START_0_CSI_PPA_RAISE_FRAME_START_CHANNEL_RANGE                  19:16
+#define VI_CSI_PPA_RAISE_FRAME_START_0_CSI_PPA_RAISE_FRAME_START_CHANNEL_WOFFSET                        0x0
+#define VI_CSI_PPA_RAISE_FRAME_START_0_CSI_PPA_RAISE_FRAME_START_CHANNEL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_RAISE_FRAME_START_0_CSI_PPA_RAISE_FRAME_START_CHANNEL_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_RAISE_FRAME_START_0_CSI_PPA_RAISE_FRAME_START_CHANNEL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_RAISE_FRAME_START_0_CSI_PPA_RAISE_FRAME_START_CHANNEL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register VI_CSI_PPA_RAISE_FRAME_END_0  // CSI Pixel Parser A Raise
+#define VI_CSI_PPA_RAISE_FRAME_END_0                    _MK_ADDR_CONST(0x77)
+#define VI_CSI_PPA_RAISE_FRAME_END_0_WORD_COUNT                         0x1
+#define VI_CSI_PPA_RAISE_FRAME_END_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_RAISE_FRAME_END_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_RAISE_FRAME_END_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_RAISE_FRAME_END_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_RAISE_FRAME_END_0_READ_MASK                  _MK_MASK_CONST(0xfff1f)
+#define VI_CSI_PPA_RAISE_FRAME_END_0_WRITE_MASK                         _MK_MASK_CONST(0xfff1f)
+//   Raise returned by VI when CSI PPA
+//   issues a frame end to consumer.
+#define VI_CSI_PPA_RAISE_FRAME_END_0_CSI_PPA_RAISE_FRAME_END_VECTOR_SHIFT                       _MK_SHIFT_CONST(0)
+#define VI_CSI_PPA_RAISE_FRAME_END_0_CSI_PPA_RAISE_FRAME_END_VECTOR_FIELD                       (_MK_MASK_CONST(0x1f) << VI_CSI_PPA_RAISE_FRAME_END_0_CSI_PPA_RAISE_FRAME_END_VECTOR_SHIFT)
+#define VI_CSI_PPA_RAISE_FRAME_END_0_CSI_PPA_RAISE_FRAME_END_VECTOR_RANGE                       4:0
+#define VI_CSI_PPA_RAISE_FRAME_END_0_CSI_PPA_RAISE_FRAME_END_VECTOR_WOFFSET                     0x0
+#define VI_CSI_PPA_RAISE_FRAME_END_0_CSI_PPA_RAISE_FRAME_END_VECTOR_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_RAISE_FRAME_END_0_CSI_PPA_RAISE_FRAME_END_VECTOR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_RAISE_FRAME_END_0_CSI_PPA_RAISE_FRAME_END_VECTOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_RAISE_FRAME_END_0_CSI_PPA_RAISE_FRAME_END_VECTOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+//   Number of frame end since last raise >= count for raise to be returned
+#define VI_CSI_PPA_RAISE_FRAME_END_0_CSI_PPA_RAISE_FRAME_END_COUNT_SHIFT                        _MK_SHIFT_CONST(8)
+#define VI_CSI_PPA_RAISE_FRAME_END_0_CSI_PPA_RAISE_FRAME_END_COUNT_FIELD                        (_MK_MASK_CONST(0xff) << VI_CSI_PPA_RAISE_FRAME_END_0_CSI_PPA_RAISE_FRAME_END_COUNT_SHIFT)
+#define VI_CSI_PPA_RAISE_FRAME_END_0_CSI_PPA_RAISE_FRAME_END_COUNT_RANGE                        15:8
+#define VI_CSI_PPA_RAISE_FRAME_END_0_CSI_PPA_RAISE_FRAME_END_COUNT_WOFFSET                      0x0
+#define VI_CSI_PPA_RAISE_FRAME_END_0_CSI_PPA_RAISE_FRAME_END_COUNT_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_RAISE_FRAME_END_0_CSI_PPA_RAISE_FRAME_END_COUNT_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_RAISE_FRAME_END_0_CSI_PPA_RAISE_FRAME_END_COUNT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_RAISE_FRAME_END_0_CSI_PPA_RAISE_FRAME_END_COUNT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+//   Raise return channel
+#define VI_CSI_PPA_RAISE_FRAME_END_0_CSI_PPA_RAISE_FRAME_END_CHANNEL_SHIFT                      _MK_SHIFT_CONST(16)
+#define VI_CSI_PPA_RAISE_FRAME_END_0_CSI_PPA_RAISE_FRAME_END_CHANNEL_FIELD                      (_MK_MASK_CONST(0xf) << VI_CSI_PPA_RAISE_FRAME_END_0_CSI_PPA_RAISE_FRAME_END_CHANNEL_SHIFT)
+#define VI_CSI_PPA_RAISE_FRAME_END_0_CSI_PPA_RAISE_FRAME_END_CHANNEL_RANGE                      19:16
+#define VI_CSI_PPA_RAISE_FRAME_END_0_CSI_PPA_RAISE_FRAME_END_CHANNEL_WOFFSET                    0x0
+#define VI_CSI_PPA_RAISE_FRAME_END_0_CSI_PPA_RAISE_FRAME_END_CHANNEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_RAISE_FRAME_END_0_CSI_PPA_RAISE_FRAME_END_CHANNEL_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_RAISE_FRAME_END_0_CSI_PPA_RAISE_FRAME_END_CHANNEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_RAISE_FRAME_END_0_CSI_PPA_RAISE_FRAME_END_CHANNEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register VI_CSI_PPB_RAISE_FRAME_START_0  // CSI Pixel Parser B Raise
+#define VI_CSI_PPB_RAISE_FRAME_START_0                  _MK_ADDR_CONST(0x78)
+#define VI_CSI_PPB_RAISE_FRAME_START_0_WORD_COUNT                       0x1
+#define VI_CSI_PPB_RAISE_FRAME_START_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_RAISE_FRAME_START_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_RAISE_FRAME_START_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_RAISE_FRAME_START_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_RAISE_FRAME_START_0_READ_MASK                        _MK_MASK_CONST(0xfff1f)
+#define VI_CSI_PPB_RAISE_FRAME_START_0_WRITE_MASK                       _MK_MASK_CONST(0xfff1f)
+//   Raise returned by VI when CSI PPB
+//   issues a frame start to consumer.
+#define VI_CSI_PPB_RAISE_FRAME_START_0_CSI_PPB_RAISE_FRAME_START_VECTOR_SHIFT                   _MK_SHIFT_CONST(0)
+#define VI_CSI_PPB_RAISE_FRAME_START_0_CSI_PPB_RAISE_FRAME_START_VECTOR_FIELD                   (_MK_MASK_CONST(0x1f) << VI_CSI_PPB_RAISE_FRAME_START_0_CSI_PPB_RAISE_FRAME_START_VECTOR_SHIFT)
+#define VI_CSI_PPB_RAISE_FRAME_START_0_CSI_PPB_RAISE_FRAME_START_VECTOR_RANGE                   4:0
+#define VI_CSI_PPB_RAISE_FRAME_START_0_CSI_PPB_RAISE_FRAME_START_VECTOR_WOFFSET                 0x0
+#define VI_CSI_PPB_RAISE_FRAME_START_0_CSI_PPB_RAISE_FRAME_START_VECTOR_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_RAISE_FRAME_START_0_CSI_PPB_RAISE_FRAME_START_VECTOR_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_RAISE_FRAME_START_0_CSI_PPB_RAISE_FRAME_START_VECTOR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_RAISE_FRAME_START_0_CSI_PPB_RAISE_FRAME_START_VECTOR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+//   Number of frame start since last raise >= count for raise to be returned
+#define VI_CSI_PPB_RAISE_FRAME_START_0_CSI_PPB_RAISE_FRAME_START_COUNT_SHIFT                    _MK_SHIFT_CONST(8)
+#define VI_CSI_PPB_RAISE_FRAME_START_0_CSI_PPB_RAISE_FRAME_START_COUNT_FIELD                    (_MK_MASK_CONST(0xff) << VI_CSI_PPB_RAISE_FRAME_START_0_CSI_PPB_RAISE_FRAME_START_COUNT_SHIFT)
+#define VI_CSI_PPB_RAISE_FRAME_START_0_CSI_PPB_RAISE_FRAME_START_COUNT_RANGE                    15:8
+#define VI_CSI_PPB_RAISE_FRAME_START_0_CSI_PPB_RAISE_FRAME_START_COUNT_WOFFSET                  0x0
+#define VI_CSI_PPB_RAISE_FRAME_START_0_CSI_PPB_RAISE_FRAME_START_COUNT_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_RAISE_FRAME_START_0_CSI_PPB_RAISE_FRAME_START_COUNT_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_RAISE_FRAME_START_0_CSI_PPB_RAISE_FRAME_START_COUNT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_RAISE_FRAME_START_0_CSI_PPB_RAISE_FRAME_START_COUNT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+//   Raise return channel
+#define VI_CSI_PPB_RAISE_FRAME_START_0_CSI_PPB_RAISE_FRAME_START_CHANNEL_SHIFT                  _MK_SHIFT_CONST(16)
+#define VI_CSI_PPB_RAISE_FRAME_START_0_CSI_PPB_RAISE_FRAME_START_CHANNEL_FIELD                  (_MK_MASK_CONST(0xf) << VI_CSI_PPB_RAISE_FRAME_START_0_CSI_PPB_RAISE_FRAME_START_CHANNEL_SHIFT)
+#define VI_CSI_PPB_RAISE_FRAME_START_0_CSI_PPB_RAISE_FRAME_START_CHANNEL_RANGE                  19:16
+#define VI_CSI_PPB_RAISE_FRAME_START_0_CSI_PPB_RAISE_FRAME_START_CHANNEL_WOFFSET                        0x0
+#define VI_CSI_PPB_RAISE_FRAME_START_0_CSI_PPB_RAISE_FRAME_START_CHANNEL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_RAISE_FRAME_START_0_CSI_PPB_RAISE_FRAME_START_CHANNEL_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_RAISE_FRAME_START_0_CSI_PPB_RAISE_FRAME_START_CHANNEL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_RAISE_FRAME_START_0_CSI_PPB_RAISE_FRAME_START_CHANNEL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register VI_CSI_PPB_RAISE_FRAME_END_0  // CSI Pixel Parser B Raise
+#define VI_CSI_PPB_RAISE_FRAME_END_0                    _MK_ADDR_CONST(0x79)
+#define VI_CSI_PPB_RAISE_FRAME_END_0_WORD_COUNT                         0x1
+#define VI_CSI_PPB_RAISE_FRAME_END_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_RAISE_FRAME_END_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_RAISE_FRAME_END_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_RAISE_FRAME_END_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_RAISE_FRAME_END_0_READ_MASK                  _MK_MASK_CONST(0xfff1f)
+#define VI_CSI_PPB_RAISE_FRAME_END_0_WRITE_MASK                         _MK_MASK_CONST(0xfff1f)
+//   Raise returned by VI when CSI PPB
+//   issues a frame end to consumer.
+#define VI_CSI_PPB_RAISE_FRAME_END_0_CSI_PPB_RAISE_FRAME_END_VECTOR_SHIFT                       _MK_SHIFT_CONST(0)
+#define VI_CSI_PPB_RAISE_FRAME_END_0_CSI_PPB_RAISE_FRAME_END_VECTOR_FIELD                       (_MK_MASK_CONST(0x1f) << VI_CSI_PPB_RAISE_FRAME_END_0_CSI_PPB_RAISE_FRAME_END_VECTOR_SHIFT)
+#define VI_CSI_PPB_RAISE_FRAME_END_0_CSI_PPB_RAISE_FRAME_END_VECTOR_RANGE                       4:0
+#define VI_CSI_PPB_RAISE_FRAME_END_0_CSI_PPB_RAISE_FRAME_END_VECTOR_WOFFSET                     0x0
+#define VI_CSI_PPB_RAISE_FRAME_END_0_CSI_PPB_RAISE_FRAME_END_VECTOR_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_RAISE_FRAME_END_0_CSI_PPB_RAISE_FRAME_END_VECTOR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_RAISE_FRAME_END_0_CSI_PPB_RAISE_FRAME_END_VECTOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_RAISE_FRAME_END_0_CSI_PPB_RAISE_FRAME_END_VECTOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+//   Number of frame end since last raise >= count for raise to be returned
+#define VI_CSI_PPB_RAISE_FRAME_END_0_CSI_PPB_RAISE_FRAME_END_COUNT_SHIFT                        _MK_SHIFT_CONST(8)
+#define VI_CSI_PPB_RAISE_FRAME_END_0_CSI_PPB_RAISE_FRAME_END_COUNT_FIELD                        (_MK_MASK_CONST(0xff) << VI_CSI_PPB_RAISE_FRAME_END_0_CSI_PPB_RAISE_FRAME_END_COUNT_SHIFT)
+#define VI_CSI_PPB_RAISE_FRAME_END_0_CSI_PPB_RAISE_FRAME_END_COUNT_RANGE                        15:8
+#define VI_CSI_PPB_RAISE_FRAME_END_0_CSI_PPB_RAISE_FRAME_END_COUNT_WOFFSET                      0x0
+#define VI_CSI_PPB_RAISE_FRAME_END_0_CSI_PPB_RAISE_FRAME_END_COUNT_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_RAISE_FRAME_END_0_CSI_PPB_RAISE_FRAME_END_COUNT_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_RAISE_FRAME_END_0_CSI_PPB_RAISE_FRAME_END_COUNT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_RAISE_FRAME_END_0_CSI_PPB_RAISE_FRAME_END_COUNT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+//   Raise return channel
+#define VI_CSI_PPB_RAISE_FRAME_END_0_CSI_PPB_RAISE_FRAME_END_CHANNEL_SHIFT                      _MK_SHIFT_CONST(16)
+#define VI_CSI_PPB_RAISE_FRAME_END_0_CSI_PPB_RAISE_FRAME_END_CHANNEL_FIELD                      (_MK_MASK_CONST(0xf) << VI_CSI_PPB_RAISE_FRAME_END_0_CSI_PPB_RAISE_FRAME_END_CHANNEL_SHIFT)
+#define VI_CSI_PPB_RAISE_FRAME_END_0_CSI_PPB_RAISE_FRAME_END_CHANNEL_RANGE                      19:16
+#define VI_CSI_PPB_RAISE_FRAME_END_0_CSI_PPB_RAISE_FRAME_END_CHANNEL_WOFFSET                    0x0
+#define VI_CSI_PPB_RAISE_FRAME_END_0_CSI_PPB_RAISE_FRAME_END_CHANNEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_RAISE_FRAME_END_0_CSI_PPB_RAISE_FRAME_END_CHANNEL_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_RAISE_FRAME_END_0_CSI_PPB_RAISE_FRAME_END_CHANNEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_RAISE_FRAME_END_0_CSI_PPB_RAISE_FRAME_END_CHANNEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register VI_CSI_PPA_H_ACTIVE_0  // VI Horizontal Active
+#define VI_CSI_PPA_H_ACTIVE_0                   _MK_ADDR_CONST(0x7a)
+#define VI_CSI_PPA_H_ACTIVE_0_WORD_COUNT                        0x1
+#define VI_CSI_PPA_H_ACTIVE_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_H_ACTIVE_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_H_ACTIVE_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_H_ACTIVE_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_H_ACTIVE_0_READ_MASK                         _MK_MASK_CONST(0x1fff1fff)
+#define VI_CSI_PPA_H_ACTIVE_0_WRITE_MASK                        _MK_MASK_CONST(0x1fff1fff)
+// Horizontal Active Start (offset to active)
+//  This parameter specifies the number of
+//  clock active edges from horizontal
+//  sync active edge to the first horizontal
+//  active pixel. If programmed to 0, the
+//  first active line starts after the first
+//  active clock edge following the horizontal
+//  sync active edge.
+#define VI_CSI_PPA_H_ACTIVE_0_CSI_PPA_H_ACTIVE_START_SHIFT                      _MK_SHIFT_CONST(0)
+#define VI_CSI_PPA_H_ACTIVE_0_CSI_PPA_H_ACTIVE_START_FIELD                      (_MK_MASK_CONST(0x1fff) << VI_CSI_PPA_H_ACTIVE_0_CSI_PPA_H_ACTIVE_START_SHIFT)
+#define VI_CSI_PPA_H_ACTIVE_0_CSI_PPA_H_ACTIVE_START_RANGE                      12:0
+#define VI_CSI_PPA_H_ACTIVE_0_CSI_PPA_H_ACTIVE_START_WOFFSET                    0x0
+#define VI_CSI_PPA_H_ACTIVE_0_CSI_PPA_H_ACTIVE_START_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_H_ACTIVE_0_CSI_PPA_H_ACTIVE_START_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_H_ACTIVE_0_CSI_PPA_H_ACTIVE_START_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_H_ACTIVE_0_CSI_PPA_H_ACTIVE_START_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Horizontal Active Period
+//  This parameter specifies the number of
+//  pixels in the horizontal active area.
+//  H_ACTIVE_START + H_ACTIVE_PERIOD should be
+//  less than 2^NV_VI_H_IN (or 8192). This parameter
+//  should be programmed with an even number
+//  (bit 16 is ignored internally).
+#define VI_CSI_PPA_H_ACTIVE_0_CSI_PPA_H_ACTIVE_PERIOD_SHIFT                     _MK_SHIFT_CONST(16)
+#define VI_CSI_PPA_H_ACTIVE_0_CSI_PPA_H_ACTIVE_PERIOD_FIELD                     (_MK_MASK_CONST(0x1fff) << VI_CSI_PPA_H_ACTIVE_0_CSI_PPA_H_ACTIVE_PERIOD_SHIFT)
+#define VI_CSI_PPA_H_ACTIVE_0_CSI_PPA_H_ACTIVE_PERIOD_RANGE                     28:16
+#define VI_CSI_PPA_H_ACTIVE_0_CSI_PPA_H_ACTIVE_PERIOD_WOFFSET                   0x0
+#define VI_CSI_PPA_H_ACTIVE_0_CSI_PPA_H_ACTIVE_PERIOD_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_H_ACTIVE_0_CSI_PPA_H_ACTIVE_PERIOD_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_H_ACTIVE_0_CSI_PPA_H_ACTIVE_PERIOD_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_H_ACTIVE_0_CSI_PPA_H_ACTIVE_PERIOD_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register VI_CSI_PPA_V_ACTIVE_0  // Vertical Active
+#define VI_CSI_PPA_V_ACTIVE_0                   _MK_ADDR_CONST(0x7b)
+#define VI_CSI_PPA_V_ACTIVE_0_WORD_COUNT                        0x1
+#define VI_CSI_PPA_V_ACTIVE_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_V_ACTIVE_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_V_ACTIVE_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_V_ACTIVE_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_V_ACTIVE_0_READ_MASK                         _MK_MASK_CONST(0x1fff1fff)
+#define VI_CSI_PPA_V_ACTIVE_0_WRITE_MASK                        _MK_MASK_CONST(0x1fff1fff)
+// Vertical Active Start (offset to active)
+//  This parameter specifies the number of
+//  horizontal sync active edges from vertical
+//  sync active edge to the first vertical
+//  active line. If programmed to 0, the
+//  first active line starts after the first
+//  horizontal sync active edge following
+//  the vertical sync active edge.
+#define VI_CSI_PPA_V_ACTIVE_0_CSI_PPA_V_ACTIVE_START_SHIFT                      _MK_SHIFT_CONST(0)
+#define VI_CSI_PPA_V_ACTIVE_0_CSI_PPA_V_ACTIVE_START_FIELD                      (_MK_MASK_CONST(0x1fff) << VI_CSI_PPA_V_ACTIVE_0_CSI_PPA_V_ACTIVE_START_SHIFT)
+#define VI_CSI_PPA_V_ACTIVE_0_CSI_PPA_V_ACTIVE_START_RANGE                      12:0
+#define VI_CSI_PPA_V_ACTIVE_0_CSI_PPA_V_ACTIVE_START_WOFFSET                    0x0
+#define VI_CSI_PPA_V_ACTIVE_0_CSI_PPA_V_ACTIVE_START_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_V_ACTIVE_0_CSI_PPA_V_ACTIVE_START_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_V_ACTIVE_0_CSI_PPA_V_ACTIVE_START_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_V_ACTIVE_0_CSI_PPA_V_ACTIVE_START_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Vertical Active Period
+//  This parameter specifies the number of
+//  lines in the vertical active area.
+//  V_ACTIVE_START + V_ACTIVE_PERIOD should be
+//  less than 2^NV_VI_V_IN (or 8192).
+#define VI_CSI_PPA_V_ACTIVE_0_CSI_PPA_V_ACTIVE_PERIOD_SHIFT                     _MK_SHIFT_CONST(16)
+#define VI_CSI_PPA_V_ACTIVE_0_CSI_PPA_V_ACTIVE_PERIOD_FIELD                     (_MK_MASK_CONST(0x1fff) << VI_CSI_PPA_V_ACTIVE_0_CSI_PPA_V_ACTIVE_PERIOD_SHIFT)
+#define VI_CSI_PPA_V_ACTIVE_0_CSI_PPA_V_ACTIVE_PERIOD_RANGE                     28:16
+#define VI_CSI_PPA_V_ACTIVE_0_CSI_PPA_V_ACTIVE_PERIOD_WOFFSET                   0x0
+#define VI_CSI_PPA_V_ACTIVE_0_CSI_PPA_V_ACTIVE_PERIOD_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_V_ACTIVE_0_CSI_PPA_V_ACTIVE_PERIOD_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_V_ACTIVE_0_CSI_PPA_V_ACTIVE_PERIOD_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_V_ACTIVE_0_CSI_PPA_V_ACTIVE_PERIOD_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register VI_CSI_PPB_H_ACTIVE_0  // VI Horizontal Active
+#define VI_CSI_PPB_H_ACTIVE_0                   _MK_ADDR_CONST(0x7c)
+#define VI_CSI_PPB_H_ACTIVE_0_WORD_COUNT                        0x1
+#define VI_CSI_PPB_H_ACTIVE_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_H_ACTIVE_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_H_ACTIVE_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_H_ACTIVE_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_H_ACTIVE_0_READ_MASK                         _MK_MASK_CONST(0x1fff1fff)
+#define VI_CSI_PPB_H_ACTIVE_0_WRITE_MASK                        _MK_MASK_CONST(0x1fff1fff)
+// Horizontal Active Start (offset to active)
+//  This parameter specifies the number of
+//  clock active edges from horizontal
+//  sync active edge to the first horizontal
+//  active pixel. If programmed to 0, the
+//  first active line starts after the first
+//  active clock edge following the horizontal
+//  sync active edge.
+#define VI_CSI_PPB_H_ACTIVE_0_CSI_PPB_H_ACTIVE_START_SHIFT                      _MK_SHIFT_CONST(0)
+#define VI_CSI_PPB_H_ACTIVE_0_CSI_PPB_H_ACTIVE_START_FIELD                      (_MK_MASK_CONST(0x1fff) << VI_CSI_PPB_H_ACTIVE_0_CSI_PPB_H_ACTIVE_START_SHIFT)
+#define VI_CSI_PPB_H_ACTIVE_0_CSI_PPB_H_ACTIVE_START_RANGE                      12:0
+#define VI_CSI_PPB_H_ACTIVE_0_CSI_PPB_H_ACTIVE_START_WOFFSET                    0x0
+#define VI_CSI_PPB_H_ACTIVE_0_CSI_PPB_H_ACTIVE_START_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_H_ACTIVE_0_CSI_PPB_H_ACTIVE_START_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_H_ACTIVE_0_CSI_PPB_H_ACTIVE_START_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_H_ACTIVE_0_CSI_PPB_H_ACTIVE_START_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Horizontal Active Period
+//  This parameter specifies the number of
+//  pixels in the horizontal active area.
+//  H_ACTIVE_START + H_ACTIVE_PERIOD should be
+//  less than 2^NV_VI_H_IN (or 8192). This parameter
+//  should be programmed with an even number
+//  (bit 16 is ignored internally).
+#define VI_CSI_PPB_H_ACTIVE_0_CSI_PPB_H_ACTIVE_PERIOD_SHIFT                     _MK_SHIFT_CONST(16)
+#define VI_CSI_PPB_H_ACTIVE_0_CSI_PPB_H_ACTIVE_PERIOD_FIELD                     (_MK_MASK_CONST(0x1fff) << VI_CSI_PPB_H_ACTIVE_0_CSI_PPB_H_ACTIVE_PERIOD_SHIFT)
+#define VI_CSI_PPB_H_ACTIVE_0_CSI_PPB_H_ACTIVE_PERIOD_RANGE                     28:16
+#define VI_CSI_PPB_H_ACTIVE_0_CSI_PPB_H_ACTIVE_PERIOD_WOFFSET                   0x0
+#define VI_CSI_PPB_H_ACTIVE_0_CSI_PPB_H_ACTIVE_PERIOD_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_H_ACTIVE_0_CSI_PPB_H_ACTIVE_PERIOD_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_H_ACTIVE_0_CSI_PPB_H_ACTIVE_PERIOD_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_H_ACTIVE_0_CSI_PPB_H_ACTIVE_PERIOD_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register VI_CSI_PPB_V_ACTIVE_0  // Vertical Active
+#define VI_CSI_PPB_V_ACTIVE_0                   _MK_ADDR_CONST(0x7d)
+#define VI_CSI_PPB_V_ACTIVE_0_WORD_COUNT                        0x1
+#define VI_CSI_PPB_V_ACTIVE_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_V_ACTIVE_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_V_ACTIVE_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_V_ACTIVE_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_V_ACTIVE_0_READ_MASK                         _MK_MASK_CONST(0x1fff1fff)
+#define VI_CSI_PPB_V_ACTIVE_0_WRITE_MASK                        _MK_MASK_CONST(0x1fff1fff)
+// Vertical Active Start (offset to active)
+//  This parameter specifies the number of
+//  horizontal sync active edges from vertical
+//  sync active edge to the first vertical
+//  active line. If programmed to 0, the
+//  first active line starts after the first
+//  horizontal sync active edge following
+//  the vertical sync active edge.
+#define VI_CSI_PPB_V_ACTIVE_0_CSI_PPB_V_ACTIVE_START_SHIFT                      _MK_SHIFT_CONST(0)
+#define VI_CSI_PPB_V_ACTIVE_0_CSI_PPB_V_ACTIVE_START_FIELD                      (_MK_MASK_CONST(0x1fff) << VI_CSI_PPB_V_ACTIVE_0_CSI_PPB_V_ACTIVE_START_SHIFT)
+#define VI_CSI_PPB_V_ACTIVE_0_CSI_PPB_V_ACTIVE_START_RANGE                      12:0
+#define VI_CSI_PPB_V_ACTIVE_0_CSI_PPB_V_ACTIVE_START_WOFFSET                    0x0
+#define VI_CSI_PPB_V_ACTIVE_0_CSI_PPB_V_ACTIVE_START_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_V_ACTIVE_0_CSI_PPB_V_ACTIVE_START_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_V_ACTIVE_0_CSI_PPB_V_ACTIVE_START_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_V_ACTIVE_0_CSI_PPB_V_ACTIVE_START_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Vertical Active Period
+//  This parameter specifies the number of
+//  lines in the vertical active area.
+//  V_ACTIVE_START + V_ACTIVE_PERIOD should be
+//  less than 2^NV_VI_V_IN (or 8192).
+#define VI_CSI_PPB_V_ACTIVE_0_CSI_PPB_V_ACTIVE_PERIOD_SHIFT                     _MK_SHIFT_CONST(16)
+#define VI_CSI_PPB_V_ACTIVE_0_CSI_PPB_V_ACTIVE_PERIOD_FIELD                     (_MK_MASK_CONST(0x1fff) << VI_CSI_PPB_V_ACTIVE_0_CSI_PPB_V_ACTIVE_PERIOD_SHIFT)
+#define VI_CSI_PPB_V_ACTIVE_0_CSI_PPB_V_ACTIVE_PERIOD_RANGE                     28:16
+#define VI_CSI_PPB_V_ACTIVE_0_CSI_PPB_V_ACTIVE_PERIOD_WOFFSET                   0x0
+#define VI_CSI_PPB_V_ACTIVE_0_CSI_PPB_V_ACTIVE_PERIOD_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_V_ACTIVE_0_CSI_PPB_V_ACTIVE_PERIOD_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_V_ACTIVE_0_CSI_PPB_V_ACTIVE_PERIOD_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_V_ACTIVE_0_CSI_PPB_V_ACTIVE_PERIOD_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register VI_ISP_H_ACTIVE_0  // Used when an image comes from ISP
+#define VI_ISP_H_ACTIVE_0                       _MK_ADDR_CONST(0x7e)
+#define VI_ISP_H_ACTIVE_0_WORD_COUNT                    0x1
+#define VI_ISP_H_ACTIVE_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define VI_ISP_H_ACTIVE_0_RESET_MASK                    _MK_MASK_CONST(0x0)
+#define VI_ISP_H_ACTIVE_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define VI_ISP_H_ACTIVE_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_ISP_H_ACTIVE_0_READ_MASK                     _MK_MASK_CONST(0x1fff)
+#define VI_ISP_H_ACTIVE_0_WRITE_MASK                    _MK_MASK_CONST(0x1fff)
+// Horizontal image size in pixels coming out of ISP.
+// Must be an even number (bit 0 is ignored).
+#define VI_ISP_H_ACTIVE_0_ISP_H_ACTIVE_PERIOD_SHIFT                     _MK_SHIFT_CONST(0)
+#define VI_ISP_H_ACTIVE_0_ISP_H_ACTIVE_PERIOD_FIELD                     (_MK_MASK_CONST(0x1fff) << VI_ISP_H_ACTIVE_0_ISP_H_ACTIVE_PERIOD_SHIFT)
+#define VI_ISP_H_ACTIVE_0_ISP_H_ACTIVE_PERIOD_RANGE                     12:0
+#define VI_ISP_H_ACTIVE_0_ISP_H_ACTIVE_PERIOD_WOFFSET                   0x0
+#define VI_ISP_H_ACTIVE_0_ISP_H_ACTIVE_PERIOD_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_ISP_H_ACTIVE_0_ISP_H_ACTIVE_PERIOD_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_ISP_H_ACTIVE_0_ISP_H_ACTIVE_PERIOD_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_ISP_H_ACTIVE_0_ISP_H_ACTIVE_PERIOD_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register VI_ISP_V_ACTIVE_0  // Used when an image comes from ISP
+#define VI_ISP_V_ACTIVE_0                       _MK_ADDR_CONST(0x7f)
+#define VI_ISP_V_ACTIVE_0_WORD_COUNT                    0x1
+#define VI_ISP_V_ACTIVE_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define VI_ISP_V_ACTIVE_0_RESET_MASK                    _MK_MASK_CONST(0x0)
+#define VI_ISP_V_ACTIVE_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define VI_ISP_V_ACTIVE_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_ISP_V_ACTIVE_0_READ_MASK                     _MK_MASK_CONST(0x1fff)
+#define VI_ISP_V_ACTIVE_0_WRITE_MASK                    _MK_MASK_CONST(0x1fff)
+// Vertical image size in lines coming out of ISP.
+// Must be an even number (bit 0 is ignored).
+#define VI_ISP_V_ACTIVE_0_ISP_V_ACTIVE_PERIOD_SHIFT                     _MK_SHIFT_CONST(0)
+#define VI_ISP_V_ACTIVE_0_ISP_V_ACTIVE_PERIOD_FIELD                     (_MK_MASK_CONST(0x1fff) << VI_ISP_V_ACTIVE_0_ISP_V_ACTIVE_PERIOD_SHIFT)
+#define VI_ISP_V_ACTIVE_0_ISP_V_ACTIVE_PERIOD_RANGE                     12:0
+#define VI_ISP_V_ACTIVE_0_ISP_V_ACTIVE_PERIOD_WOFFSET                   0x0
+#define VI_ISP_V_ACTIVE_0_ISP_V_ACTIVE_PERIOD_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_ISP_V_ACTIVE_0_ISP_V_ACTIVE_PERIOD_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_ISP_V_ACTIVE_0_ISP_V_ACTIVE_PERIOD_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_ISP_V_ACTIVE_0_ISP_V_ACTIVE_PERIOD_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register VI_STREAM_1_RESOURCE_DEFINE_0  // defines resources used by stream 1.
+// Field definition is: 0 = resource not used; 1 = resource used.
+#define VI_STREAM_1_RESOURCE_DEFINE_0                   _MK_ADDR_CONST(0x80)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_WORD_COUNT                        0x1
+#define VI_STREAM_1_RESOURCE_DEFINE_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_RESET_MASK                        _MK_MASK_CONST(0xfff)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_READ_MASK                         _MK_MASK_CONST(0xfff)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_WRITE_MASK                        _MK_MASK_CONST(0xfff)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_VIP_INPUT_1_SHIFT                 _MK_SHIFT_CONST(0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_VIP_INPUT_1_FIELD                 (_MK_MASK_CONST(0x1) << VI_STREAM_1_RESOURCE_DEFINE_0_VIP_INPUT_1_SHIFT)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_VIP_INPUT_1_RANGE                 0:0
+#define VI_STREAM_1_RESOURCE_DEFINE_0_VIP_INPUT_1_WOFFSET                       0x0
+#define VI_STREAM_1_RESOURCE_DEFINE_0_VIP_INPUT_1_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_VIP_INPUT_1_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_VIP_INPUT_1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_VIP_INPUT_1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_VIP_INPUT_1_NOT_USED                      _MK_ENUM_CONST(0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_VIP_INPUT_1_USED                  _MK_ENUM_CONST(1)
+
+#define VI_STREAM_1_RESOURCE_DEFINE_0_HOST_INPUT_1_SHIFT                        _MK_SHIFT_CONST(1)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_HOST_INPUT_1_FIELD                        (_MK_MASK_CONST(0x1) << VI_STREAM_1_RESOURCE_DEFINE_0_HOST_INPUT_1_SHIFT)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_HOST_INPUT_1_RANGE                        1:1
+#define VI_STREAM_1_RESOURCE_DEFINE_0_HOST_INPUT_1_WOFFSET                      0x0
+#define VI_STREAM_1_RESOURCE_DEFINE_0_HOST_INPUT_1_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_HOST_INPUT_1_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_HOST_INPUT_1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_HOST_INPUT_1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_HOST_INPUT_1_NOT_USED                     _MK_ENUM_CONST(0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_HOST_INPUT_1_USED                 _MK_ENUM_CONST(1)
+
+#define VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPA_CROPPED_INPUT_1_SHIFT                     _MK_SHIFT_CONST(2)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPA_CROPPED_INPUT_1_FIELD                     (_MK_MASK_CONST(0x1) << VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPA_CROPPED_INPUT_1_SHIFT)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPA_CROPPED_INPUT_1_RANGE                     2:2
+#define VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPA_CROPPED_INPUT_1_WOFFSET                   0x0
+#define VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPA_CROPPED_INPUT_1_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPA_CROPPED_INPUT_1_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPA_CROPPED_INPUT_1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPA_CROPPED_INPUT_1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPA_CROPPED_INPUT_1_NOT_USED                  _MK_ENUM_CONST(0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPA_CROPPED_INPUT_1_USED                      _MK_ENUM_CONST(1)
+
+#define VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPA_UNCROPPED_INPUT_1_SHIFT                   _MK_SHIFT_CONST(3)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPA_UNCROPPED_INPUT_1_FIELD                   (_MK_MASK_CONST(0x1) << VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPA_UNCROPPED_INPUT_1_SHIFT)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPA_UNCROPPED_INPUT_1_RANGE                   3:3
+#define VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPA_UNCROPPED_INPUT_1_WOFFSET                 0x0
+#define VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPA_UNCROPPED_INPUT_1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPA_UNCROPPED_INPUT_1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPA_UNCROPPED_INPUT_1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPA_UNCROPPED_INPUT_1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPA_UNCROPPED_INPUT_1_NOT_USED                        _MK_ENUM_CONST(0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPA_UNCROPPED_INPUT_1_USED                    _MK_ENUM_CONST(1)
+
+#define VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPB_CROPPED_INPUT_1_SHIFT                     _MK_SHIFT_CONST(4)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPB_CROPPED_INPUT_1_FIELD                     (_MK_MASK_CONST(0x1) << VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPB_CROPPED_INPUT_1_SHIFT)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPB_CROPPED_INPUT_1_RANGE                     4:4
+#define VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPB_CROPPED_INPUT_1_WOFFSET                   0x0
+#define VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPB_CROPPED_INPUT_1_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPB_CROPPED_INPUT_1_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPB_CROPPED_INPUT_1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPB_CROPPED_INPUT_1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPB_CROPPED_INPUT_1_NOT_USED                  _MK_ENUM_CONST(0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPB_CROPPED_INPUT_1_USED                      _MK_ENUM_CONST(1)
+
+#define VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPB_UNCROPPED_INPUT_1_SHIFT                   _MK_SHIFT_CONST(5)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPB_UNCROPPED_INPUT_1_FIELD                   (_MK_MASK_CONST(0x1) << VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPB_UNCROPPED_INPUT_1_SHIFT)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPB_UNCROPPED_INPUT_1_RANGE                   5:5
+#define VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPB_UNCROPPED_INPUT_1_WOFFSET                 0x0
+#define VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPB_UNCROPPED_INPUT_1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPB_UNCROPPED_INPUT_1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPB_UNCROPPED_INPUT_1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPB_UNCROPPED_INPUT_1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPB_UNCROPPED_INPUT_1_NOT_USED                        _MK_ENUM_CONST(0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPB_UNCROPPED_INPUT_1_USED                    _MK_ENUM_CONST(1)
+
+#define VI_STREAM_1_RESOURCE_DEFINE_0_ISP_INPUT_1_SHIFT                 _MK_SHIFT_CONST(6)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_ISP_INPUT_1_FIELD                 (_MK_MASK_CONST(0x1) << VI_STREAM_1_RESOURCE_DEFINE_0_ISP_INPUT_1_SHIFT)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_ISP_INPUT_1_RANGE                 6:6
+#define VI_STREAM_1_RESOURCE_DEFINE_0_ISP_INPUT_1_WOFFSET                       0x0
+#define VI_STREAM_1_RESOURCE_DEFINE_0_ISP_INPUT_1_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_ISP_INPUT_1_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_ISP_INPUT_1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_ISP_INPUT_1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_ISP_INPUT_1_NOT_USED                      _MK_ENUM_CONST(0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_ISP_INPUT_1_USED                  _MK_ENUM_CONST(1)
+
+#define VI_STREAM_1_RESOURCE_DEFINE_0_FIRST_OUTPUT_1_SHIFT                      _MK_SHIFT_CONST(7)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_FIRST_OUTPUT_1_FIELD                      (_MK_MASK_CONST(0x1) << VI_STREAM_1_RESOURCE_DEFINE_0_FIRST_OUTPUT_1_SHIFT)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_FIRST_OUTPUT_1_RANGE                      7:7
+#define VI_STREAM_1_RESOURCE_DEFINE_0_FIRST_OUTPUT_1_WOFFSET                    0x0
+#define VI_STREAM_1_RESOURCE_DEFINE_0_FIRST_OUTPUT_1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_FIRST_OUTPUT_1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_FIRST_OUTPUT_1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_FIRST_OUTPUT_1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_FIRST_OUTPUT_1_NOT_USED                   _MK_ENUM_CONST(0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_FIRST_OUTPUT_1_USED                       _MK_ENUM_CONST(1)
+
+#define VI_STREAM_1_RESOURCE_DEFINE_0_SECOND_OUTPUT_1_SHIFT                     _MK_SHIFT_CONST(8)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_SECOND_OUTPUT_1_FIELD                     (_MK_MASK_CONST(0x1) << VI_STREAM_1_RESOURCE_DEFINE_0_SECOND_OUTPUT_1_SHIFT)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_SECOND_OUTPUT_1_RANGE                     8:8
+#define VI_STREAM_1_RESOURCE_DEFINE_0_SECOND_OUTPUT_1_WOFFSET                   0x0
+#define VI_STREAM_1_RESOURCE_DEFINE_0_SECOND_OUTPUT_1_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_SECOND_OUTPUT_1_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_SECOND_OUTPUT_1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_SECOND_OUTPUT_1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_SECOND_OUTPUT_1_NOT_USED                  _MK_ENUM_CONST(0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_SECOND_OUTPUT_1_USED                      _MK_ENUM_CONST(1)
+
+#define VI_STREAM_1_RESOURCE_DEFINE_0_HOST_DMA_VSYNC_OUTPUT_1_SHIFT                     _MK_SHIFT_CONST(9)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_HOST_DMA_VSYNC_OUTPUT_1_FIELD                     (_MK_MASK_CONST(0x1) << VI_STREAM_1_RESOURCE_DEFINE_0_HOST_DMA_VSYNC_OUTPUT_1_SHIFT)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_HOST_DMA_VSYNC_OUTPUT_1_RANGE                     9:9
+#define VI_STREAM_1_RESOURCE_DEFINE_0_HOST_DMA_VSYNC_OUTPUT_1_WOFFSET                   0x0
+#define VI_STREAM_1_RESOURCE_DEFINE_0_HOST_DMA_VSYNC_OUTPUT_1_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_HOST_DMA_VSYNC_OUTPUT_1_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_HOST_DMA_VSYNC_OUTPUT_1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_HOST_DMA_VSYNC_OUTPUT_1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_HOST_DMA_VSYNC_OUTPUT_1_NOT_USED                  _MK_ENUM_CONST(0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_HOST_DMA_VSYNC_OUTPUT_1_USED                      _MK_ENUM_CONST(1)
+
+#define VI_STREAM_1_RESOURCE_DEFINE_0_EPP_OUTPUT_1_SHIFT                        _MK_SHIFT_CONST(10)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_EPP_OUTPUT_1_FIELD                        (_MK_MASK_CONST(0x1) << VI_STREAM_1_RESOURCE_DEFINE_0_EPP_OUTPUT_1_SHIFT)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_EPP_OUTPUT_1_RANGE                        10:10
+#define VI_STREAM_1_RESOURCE_DEFINE_0_EPP_OUTPUT_1_WOFFSET                      0x0
+#define VI_STREAM_1_RESOURCE_DEFINE_0_EPP_OUTPUT_1_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_EPP_OUTPUT_1_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_EPP_OUTPUT_1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_EPP_OUTPUT_1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_EPP_OUTPUT_1_NOT_USED                     _MK_ENUM_CONST(0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_EPP_OUTPUT_1_USED                 _MK_ENUM_CONST(1)
+
+#define VI_STREAM_1_RESOURCE_DEFINE_0_HOST_DMA_BUFFER_OUTPUT_1_SHIFT                    _MK_SHIFT_CONST(11)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_HOST_DMA_BUFFER_OUTPUT_1_FIELD                    (_MK_MASK_CONST(0x1) << VI_STREAM_1_RESOURCE_DEFINE_0_HOST_DMA_BUFFER_OUTPUT_1_SHIFT)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_HOST_DMA_BUFFER_OUTPUT_1_RANGE                    11:11
+#define VI_STREAM_1_RESOURCE_DEFINE_0_HOST_DMA_BUFFER_OUTPUT_1_WOFFSET                  0x0
+#define VI_STREAM_1_RESOURCE_DEFINE_0_HOST_DMA_BUFFER_OUTPUT_1_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_HOST_DMA_BUFFER_OUTPUT_1_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_HOST_DMA_BUFFER_OUTPUT_1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_HOST_DMA_BUFFER_OUTPUT_1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_HOST_DMA_BUFFER_OUTPUT_1_NOT_USED                 _MK_ENUM_CONST(0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_HOST_DMA_BUFFER_OUTPUT_1_USED                     _MK_ENUM_CONST(1)
+
+
+// Register VI_STREAM_2_RESOURCE_DEFINE_0  // defines resources used by stream 2.
+// Field definition is: 0 = resource not used; 1 = resource used.
+#define VI_STREAM_2_RESOURCE_DEFINE_0                   _MK_ADDR_CONST(0x81)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_WORD_COUNT                        0x1
+#define VI_STREAM_2_RESOURCE_DEFINE_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_RESET_MASK                        _MK_MASK_CONST(0xfff)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_READ_MASK                         _MK_MASK_CONST(0xfff)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_WRITE_MASK                        _MK_MASK_CONST(0xfff)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_VIP_INPUT_2_SHIFT                 _MK_SHIFT_CONST(0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_VIP_INPUT_2_FIELD                 (_MK_MASK_CONST(0x1) << VI_STREAM_2_RESOURCE_DEFINE_0_VIP_INPUT_2_SHIFT)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_VIP_INPUT_2_RANGE                 0:0
+#define VI_STREAM_2_RESOURCE_DEFINE_0_VIP_INPUT_2_WOFFSET                       0x0
+#define VI_STREAM_2_RESOURCE_DEFINE_0_VIP_INPUT_2_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_VIP_INPUT_2_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_VIP_INPUT_2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_VIP_INPUT_2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_VIP_INPUT_2_NOT_USED                      _MK_ENUM_CONST(0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_VIP_INPUT_2_USED                  _MK_ENUM_CONST(1)
+
+#define VI_STREAM_2_RESOURCE_DEFINE_0_HOST_INPUT_2_SHIFT                        _MK_SHIFT_CONST(1)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_HOST_INPUT_2_FIELD                        (_MK_MASK_CONST(0x1) << VI_STREAM_2_RESOURCE_DEFINE_0_HOST_INPUT_2_SHIFT)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_HOST_INPUT_2_RANGE                        1:1
+#define VI_STREAM_2_RESOURCE_DEFINE_0_HOST_INPUT_2_WOFFSET                      0x0
+#define VI_STREAM_2_RESOURCE_DEFINE_0_HOST_INPUT_2_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_HOST_INPUT_2_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_HOST_INPUT_2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_HOST_INPUT_2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_HOST_INPUT_2_NOT_USED                     _MK_ENUM_CONST(0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_HOST_INPUT_2_USED                 _MK_ENUM_CONST(1)
+
+#define VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPA_CROPPED_INPUT_2_SHIFT                     _MK_SHIFT_CONST(2)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPA_CROPPED_INPUT_2_FIELD                     (_MK_MASK_CONST(0x1) << VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPA_CROPPED_INPUT_2_SHIFT)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPA_CROPPED_INPUT_2_RANGE                     2:2
+#define VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPA_CROPPED_INPUT_2_WOFFSET                   0x0
+#define VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPA_CROPPED_INPUT_2_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPA_CROPPED_INPUT_2_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPA_CROPPED_INPUT_2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPA_CROPPED_INPUT_2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPA_CROPPED_INPUT_2_NOT_USED                  _MK_ENUM_CONST(0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPA_CROPPED_INPUT_2_USED                      _MK_ENUM_CONST(1)
+
+#define VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPA_UNCROPPED_INPUT_2_SHIFT                   _MK_SHIFT_CONST(3)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPA_UNCROPPED_INPUT_2_FIELD                   (_MK_MASK_CONST(0x1) << VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPA_UNCROPPED_INPUT_2_SHIFT)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPA_UNCROPPED_INPUT_2_RANGE                   3:3
+#define VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPA_UNCROPPED_INPUT_2_WOFFSET                 0x0
+#define VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPA_UNCROPPED_INPUT_2_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPA_UNCROPPED_INPUT_2_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPA_UNCROPPED_INPUT_2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPA_UNCROPPED_INPUT_2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPA_UNCROPPED_INPUT_2_NOT_USED                        _MK_ENUM_CONST(0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPA_UNCROPPED_INPUT_2_USED                    _MK_ENUM_CONST(1)
+
+#define VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPB_CROPPED_INPUT_2_SHIFT                     _MK_SHIFT_CONST(4)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPB_CROPPED_INPUT_2_FIELD                     (_MK_MASK_CONST(0x1) << VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPB_CROPPED_INPUT_2_SHIFT)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPB_CROPPED_INPUT_2_RANGE                     4:4
+#define VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPB_CROPPED_INPUT_2_WOFFSET                   0x0
+#define VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPB_CROPPED_INPUT_2_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPB_CROPPED_INPUT_2_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPB_CROPPED_INPUT_2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPB_CROPPED_INPUT_2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPB_CROPPED_INPUT_2_NOT_USED                  _MK_ENUM_CONST(0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPB_CROPPED_INPUT_2_USED                      _MK_ENUM_CONST(1)
+
+#define VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPB_UNCROPPED_INPUT_2_SHIFT                   _MK_SHIFT_CONST(5)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPB_UNCROPPED_INPUT_2_FIELD                   (_MK_MASK_CONST(0x1) << VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPB_UNCROPPED_INPUT_2_SHIFT)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPB_UNCROPPED_INPUT_2_RANGE                   5:5
+#define VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPB_UNCROPPED_INPUT_2_WOFFSET                 0x0
+#define VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPB_UNCROPPED_INPUT_2_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPB_UNCROPPED_INPUT_2_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPB_UNCROPPED_INPUT_2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPB_UNCROPPED_INPUT_2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPB_UNCROPPED_INPUT_2_NOT_USED                        _MK_ENUM_CONST(0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPB_UNCROPPED_INPUT_2_USED                    _MK_ENUM_CONST(1)
+
+#define VI_STREAM_2_RESOURCE_DEFINE_0_ISP_INPUT_2_SHIFT                 _MK_SHIFT_CONST(6)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_ISP_INPUT_2_FIELD                 (_MK_MASK_CONST(0x1) << VI_STREAM_2_RESOURCE_DEFINE_0_ISP_INPUT_2_SHIFT)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_ISP_INPUT_2_RANGE                 6:6
+#define VI_STREAM_2_RESOURCE_DEFINE_0_ISP_INPUT_2_WOFFSET                       0x0
+#define VI_STREAM_2_RESOURCE_DEFINE_0_ISP_INPUT_2_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_ISP_INPUT_2_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_ISP_INPUT_2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_ISP_INPUT_2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_ISP_INPUT_2_NOT_USED                      _MK_ENUM_CONST(0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_ISP_INPUT_2_USED                  _MK_ENUM_CONST(1)
+
+#define VI_STREAM_2_RESOURCE_DEFINE_0_FIRST_OUTPUT_2_SHIFT                      _MK_SHIFT_CONST(7)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_FIRST_OUTPUT_2_FIELD                      (_MK_MASK_CONST(0x1) << VI_STREAM_2_RESOURCE_DEFINE_0_FIRST_OUTPUT_2_SHIFT)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_FIRST_OUTPUT_2_RANGE                      7:7
+#define VI_STREAM_2_RESOURCE_DEFINE_0_FIRST_OUTPUT_2_WOFFSET                    0x0
+#define VI_STREAM_2_RESOURCE_DEFINE_0_FIRST_OUTPUT_2_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_FIRST_OUTPUT_2_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_FIRST_OUTPUT_2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_FIRST_OUTPUT_2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_FIRST_OUTPUT_2_NOT_USED                   _MK_ENUM_CONST(0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_FIRST_OUTPUT_2_USED                       _MK_ENUM_CONST(1)
+
+#define VI_STREAM_2_RESOURCE_DEFINE_0_SECOND_OUTPUT_2_SHIFT                     _MK_SHIFT_CONST(8)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_SECOND_OUTPUT_2_FIELD                     (_MK_MASK_CONST(0x1) << VI_STREAM_2_RESOURCE_DEFINE_0_SECOND_OUTPUT_2_SHIFT)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_SECOND_OUTPUT_2_RANGE                     8:8
+#define VI_STREAM_2_RESOURCE_DEFINE_0_SECOND_OUTPUT_2_WOFFSET                   0x0
+#define VI_STREAM_2_RESOURCE_DEFINE_0_SECOND_OUTPUT_2_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_SECOND_OUTPUT_2_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_SECOND_OUTPUT_2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_SECOND_OUTPUT_2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_SECOND_OUTPUT_2_NOT_USED                  _MK_ENUM_CONST(0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_SECOND_OUTPUT_2_USED                      _MK_ENUM_CONST(1)
+
+#define VI_STREAM_2_RESOURCE_DEFINE_0_HOST_DMA_VSYNC_OUTPUT_2_SHIFT                     _MK_SHIFT_CONST(9)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_HOST_DMA_VSYNC_OUTPUT_2_FIELD                     (_MK_MASK_CONST(0x1) << VI_STREAM_2_RESOURCE_DEFINE_0_HOST_DMA_VSYNC_OUTPUT_2_SHIFT)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_HOST_DMA_VSYNC_OUTPUT_2_RANGE                     9:9
+#define VI_STREAM_2_RESOURCE_DEFINE_0_HOST_DMA_VSYNC_OUTPUT_2_WOFFSET                   0x0
+#define VI_STREAM_2_RESOURCE_DEFINE_0_HOST_DMA_VSYNC_OUTPUT_2_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_HOST_DMA_VSYNC_OUTPUT_2_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_HOST_DMA_VSYNC_OUTPUT_2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_HOST_DMA_VSYNC_OUTPUT_2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_HOST_DMA_VSYNC_OUTPUT_2_NOT_USED                  _MK_ENUM_CONST(0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_HOST_DMA_VSYNC_OUTPUT_2_USED                      _MK_ENUM_CONST(1)
+
+#define VI_STREAM_2_RESOURCE_DEFINE_0_EPP_OUTPUT_2_SHIFT                        _MK_SHIFT_CONST(10)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_EPP_OUTPUT_2_FIELD                        (_MK_MASK_CONST(0x1) << VI_STREAM_2_RESOURCE_DEFINE_0_EPP_OUTPUT_2_SHIFT)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_EPP_OUTPUT_2_RANGE                        10:10
+#define VI_STREAM_2_RESOURCE_DEFINE_0_EPP_OUTPUT_2_WOFFSET                      0x0
+#define VI_STREAM_2_RESOURCE_DEFINE_0_EPP_OUTPUT_2_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_EPP_OUTPUT_2_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_EPP_OUTPUT_2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_EPP_OUTPUT_2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_EPP_OUTPUT_2_NOT_USED                     _MK_ENUM_CONST(0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_EPP_OUTPUT_2_USED                 _MK_ENUM_CONST(1)
+
+#define VI_STREAM_2_RESOURCE_DEFINE_0_HOST_DMA_BUFFER_OUTPUT_2_SHIFT                    _MK_SHIFT_CONST(11)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_HOST_DMA_BUFFER_OUTPUT_2_FIELD                    (_MK_MASK_CONST(0x1) << VI_STREAM_2_RESOURCE_DEFINE_0_HOST_DMA_BUFFER_OUTPUT_2_SHIFT)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_HOST_DMA_BUFFER_OUTPUT_2_RANGE                    11:11
+#define VI_STREAM_2_RESOURCE_DEFINE_0_HOST_DMA_BUFFER_OUTPUT_2_WOFFSET                  0x0
+#define VI_STREAM_2_RESOURCE_DEFINE_0_HOST_DMA_BUFFER_OUTPUT_2_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_HOST_DMA_BUFFER_OUTPUT_2_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_HOST_DMA_BUFFER_OUTPUT_2_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_HOST_DMA_BUFFER_OUTPUT_2_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_HOST_DMA_BUFFER_OUTPUT_2_NOT_USED                 _MK_ENUM_CONST(0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_HOST_DMA_BUFFER_OUTPUT_2_USED                     _MK_ENUM_CONST(1)
+
+
+// Register VI_RAISE_STREAM_1_DONE_0  // raise vector when all stream 1 resources,
+// as defined by STREAM_1_RESOURCE_DEFINE register,
+// become idle after the start of the following frame.
+#define VI_RAISE_STREAM_1_DONE_0                        _MK_ADDR_CONST(0x82)
+#define VI_RAISE_STREAM_1_DONE_0_WORD_COUNT                     0x1
+#define VI_RAISE_STREAM_1_DONE_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define VI_RAISE_STREAM_1_DONE_0_RESET_MASK                     _MK_MASK_CONST(0x0)
+#define VI_RAISE_STREAM_1_DONE_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define VI_RAISE_STREAM_1_DONE_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_RAISE_STREAM_1_DONE_0_READ_MASK                      _MK_MASK_CONST(0x1f)
+#define VI_RAISE_STREAM_1_DONE_0_WRITE_MASK                     _MK_MASK_CONST(0xf001f)
+#define VI_RAISE_STREAM_1_DONE_0_RAISE_VECTOR_STREAM_1_SHIFT                    _MK_SHIFT_CONST(0)
+#define VI_RAISE_STREAM_1_DONE_0_RAISE_VECTOR_STREAM_1_FIELD                    (_MK_MASK_CONST(0x1f) << VI_RAISE_STREAM_1_DONE_0_RAISE_VECTOR_STREAM_1_SHIFT)
+#define VI_RAISE_STREAM_1_DONE_0_RAISE_VECTOR_STREAM_1_RANGE                    4:0
+#define VI_RAISE_STREAM_1_DONE_0_RAISE_VECTOR_STREAM_1_WOFFSET                  0x0
+#define VI_RAISE_STREAM_1_DONE_0_RAISE_VECTOR_STREAM_1_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_RAISE_STREAM_1_DONE_0_RAISE_VECTOR_STREAM_1_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_RAISE_STREAM_1_DONE_0_RAISE_VECTOR_STREAM_1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_RAISE_STREAM_1_DONE_0_RAISE_VECTOR_STREAM_1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define VI_RAISE_STREAM_1_DONE_0_RAISE_CHANNEL_STREAM_1_SHIFT                   _MK_SHIFT_CONST(16)
+#define VI_RAISE_STREAM_1_DONE_0_RAISE_CHANNEL_STREAM_1_FIELD                   (_MK_MASK_CONST(0xf) << VI_RAISE_STREAM_1_DONE_0_RAISE_CHANNEL_STREAM_1_SHIFT)
+#define VI_RAISE_STREAM_1_DONE_0_RAISE_CHANNEL_STREAM_1_RANGE                   19:16
+#define VI_RAISE_STREAM_1_DONE_0_RAISE_CHANNEL_STREAM_1_WOFFSET                 0x0
+#define VI_RAISE_STREAM_1_DONE_0_RAISE_CHANNEL_STREAM_1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_RAISE_STREAM_1_DONE_0_RAISE_CHANNEL_STREAM_1_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_RAISE_STREAM_1_DONE_0_RAISE_CHANNEL_STREAM_1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_RAISE_STREAM_1_DONE_0_RAISE_CHANNEL_STREAM_1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register VI_RAISE_STREAM_2_DONE_0  // raise vector when all stream 2 resources,
+// as defined by STREAM_2_RESOURCE_DEFINE register,
+// become idle after the start of the following frame
+#define VI_RAISE_STREAM_2_DONE_0                        _MK_ADDR_CONST(0x83)
+#define VI_RAISE_STREAM_2_DONE_0_WORD_COUNT                     0x1
+#define VI_RAISE_STREAM_2_DONE_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define VI_RAISE_STREAM_2_DONE_0_RESET_MASK                     _MK_MASK_CONST(0x0)
+#define VI_RAISE_STREAM_2_DONE_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define VI_RAISE_STREAM_2_DONE_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_RAISE_STREAM_2_DONE_0_READ_MASK                      _MK_MASK_CONST(0x1f)
+#define VI_RAISE_STREAM_2_DONE_0_WRITE_MASK                     _MK_MASK_CONST(0xf001f)
+#define VI_RAISE_STREAM_2_DONE_0_RAISE_VECTOR_STREAM_2_SHIFT                    _MK_SHIFT_CONST(0)
+#define VI_RAISE_STREAM_2_DONE_0_RAISE_VECTOR_STREAM_2_FIELD                    (_MK_MASK_CONST(0x1f) << VI_RAISE_STREAM_2_DONE_0_RAISE_VECTOR_STREAM_2_SHIFT)
+#define VI_RAISE_STREAM_2_DONE_0_RAISE_VECTOR_STREAM_2_RANGE                    4:0
+#define VI_RAISE_STREAM_2_DONE_0_RAISE_VECTOR_STREAM_2_WOFFSET                  0x0
+#define VI_RAISE_STREAM_2_DONE_0_RAISE_VECTOR_STREAM_2_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_RAISE_STREAM_2_DONE_0_RAISE_VECTOR_STREAM_2_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_RAISE_STREAM_2_DONE_0_RAISE_VECTOR_STREAM_2_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_RAISE_STREAM_2_DONE_0_RAISE_VECTOR_STREAM_2_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define VI_RAISE_STREAM_2_DONE_0_RAISE_CHANNEL_STREAM_2_SHIFT                   _MK_SHIFT_CONST(16)
+#define VI_RAISE_STREAM_2_DONE_0_RAISE_CHANNEL_STREAM_2_FIELD                   (_MK_MASK_CONST(0xf) << VI_RAISE_STREAM_2_DONE_0_RAISE_CHANNEL_STREAM_2_SHIFT)
+#define VI_RAISE_STREAM_2_DONE_0_RAISE_CHANNEL_STREAM_2_RANGE                   19:16
+#define VI_RAISE_STREAM_2_DONE_0_RAISE_CHANNEL_STREAM_2_WOFFSET                 0x0
+#define VI_RAISE_STREAM_2_DONE_0_RAISE_CHANNEL_STREAM_2_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_RAISE_STREAM_2_DONE_0_RAISE_CHANNEL_STREAM_2_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_RAISE_STREAM_2_DONE_0_RAISE_CHANNEL_STREAM_2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_RAISE_STREAM_2_DONE_0_RAISE_CHANNEL_STREAM_2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register VI_TS_MODE_0  // ISDB-T mode selection register
+#define VI_TS_MODE_0                    _MK_ADDR_CONST(0x84)
+#define VI_TS_MODE_0_WORD_COUNT                         0x1
+#define VI_TS_MODE_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define VI_TS_MODE_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define VI_TS_MODE_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define VI_TS_MODE_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_TS_MODE_0_READ_MASK                  _MK_MASK_CONST(0x3f)
+#define VI_TS_MODE_0_WRITE_MASK                         _MK_MASK_CONST(0x3f)
+// This field indicates the global enable for ISDB-T protocol handling
+#define VI_TS_MODE_0_ENABLE_SHIFT                       _MK_SHIFT_CONST(0)
+#define VI_TS_MODE_0_ENABLE_FIELD                       (_MK_MASK_CONST(0x1) << VI_TS_MODE_0_ENABLE_SHIFT)
+#define VI_TS_MODE_0_ENABLE_RANGE                       0:0
+#define VI_TS_MODE_0_ENABLE_WOFFSET                     0x0
+#define VI_TS_MODE_0_ENABLE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_TS_MODE_0_ENABLE_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_TS_MODE_0_ENABLE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_TS_MODE_0_ENABLE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_TS_MODE_0_ENABLE_DISABLED                    _MK_ENUM_CONST(0)
+#define VI_TS_MODE_0_ENABLE_ENABLED                     _MK_ENUM_CONST(1)
+
+// This field determines if input data is in serial or parallel format
+#define VI_TS_MODE_0_INPUT_MODE_SHIFT                   _MK_SHIFT_CONST(1)
+#define VI_TS_MODE_0_INPUT_MODE_FIELD                   (_MK_MASK_CONST(0x1) << VI_TS_MODE_0_INPUT_MODE_SHIFT)
+#define VI_TS_MODE_0_INPUT_MODE_RANGE                   1:1
+#define VI_TS_MODE_0_INPUT_MODE_WOFFSET                 0x0
+#define VI_TS_MODE_0_INPUT_MODE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_TS_MODE_0_INPUT_MODE_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_TS_MODE_0_INPUT_MODE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_TS_MODE_0_INPUT_MODE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_TS_MODE_0_INPUT_MODE_PARALLEL                        _MK_ENUM_CONST(0)
+#define VI_TS_MODE_0_INPUT_MODE_SERIAL                  _MK_ENUM_CONST(1)
+
+// This field selected the pin configuration used for VD[1]  NONE:     TS_ERROR is tied to 0
+//            TS_PSYNC is tied to 0
+//  TS_ERROR: TS_ERROR is on VD[1]
+//            TS_PSYNC is tied to 0
+//  TS_PSYNC: TS_ERROR is tied to 0
+//            TS_PSYNC is on VD[1]
+#define VI_TS_MODE_0_PROTOCOL_SELECT_SHIFT                      _MK_SHIFT_CONST(2)
+#define VI_TS_MODE_0_PROTOCOL_SELECT_FIELD                      (_MK_MASK_CONST(0x3) << VI_TS_MODE_0_PROTOCOL_SELECT_SHIFT)
+#define VI_TS_MODE_0_PROTOCOL_SELECT_RANGE                      3:2
+#define VI_TS_MODE_0_PROTOCOL_SELECT_WOFFSET                    0x0
+#define VI_TS_MODE_0_PROTOCOL_SELECT_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_TS_MODE_0_PROTOCOL_SELECT_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_TS_MODE_0_PROTOCOL_SELECT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_TS_MODE_0_PROTOCOL_SELECT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_TS_MODE_0_PROTOCOL_SELECT_NONE                       _MK_ENUM_CONST(0)
+#define VI_TS_MODE_0_PROTOCOL_SELECT_TS_ERROR                   _MK_ENUM_CONST(1)
+#define VI_TS_MODE_0_PROTOCOL_SELECT_TS_PSYNC                   _MK_ENUM_CONST(2)
+#define VI_TS_MODE_0_PROTOCOL_SELECT_RESERVED                   _MK_ENUM_CONST(3)
+
+// This field selects the buffer flow control for the Write DMA RDMA:      The RDMA engine will release the buffers back to the WDMA
+//            as the buffers are consumed
+// NONE:      The VI will automatically release the buffer back to the
+//            WMDA after each buffer ready is generated.
+// CPU:       SW needs to write the TS_CPU_FLOW_CTL register to release
+//            each buffer to the WDMA
+#define VI_TS_MODE_0_FLOW_CONTROL_MODE_SHIFT                    _MK_SHIFT_CONST(4)
+#define VI_TS_MODE_0_FLOW_CONTROL_MODE_FIELD                    (_MK_MASK_CONST(0x3) << VI_TS_MODE_0_FLOW_CONTROL_MODE_SHIFT)
+#define VI_TS_MODE_0_FLOW_CONTROL_MODE_RANGE                    5:4
+#define VI_TS_MODE_0_FLOW_CONTROL_MODE_WOFFSET                  0x0
+#define VI_TS_MODE_0_FLOW_CONTROL_MODE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_TS_MODE_0_FLOW_CONTROL_MODE_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_TS_MODE_0_FLOW_CONTROL_MODE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_TS_MODE_0_FLOW_CONTROL_MODE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_TS_MODE_0_FLOW_CONTROL_MODE_RDMA                     _MK_ENUM_CONST(0)
+#define VI_TS_MODE_0_FLOW_CONTROL_MODE_NONE                     _MK_ENUM_CONST(1)
+#define VI_TS_MODE_0_FLOW_CONTROL_MODE_CPU                      _MK_ENUM_CONST(2)
+#define VI_TS_MODE_0_FLOW_CONTROL_MODE_RESERVED                 _MK_ENUM_CONST(3)
+
+
+// Register VI_TS_CONTROL_0  // ISDB-T mode control register
+#define VI_TS_CONTROL_0                 _MK_ADDR_CONST(0x85)
+#define VI_TS_CONTROL_0_WORD_COUNT                      0x1
+#define VI_TS_CONTROL_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define VI_TS_CONTROL_0_RESET_MASK                      _MK_MASK_CONST(0x0)
+#define VI_TS_CONTROL_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define VI_TS_CONTROL_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define VI_TS_CONTROL_0_READ_MASK                       _MK_MASK_CONST(0x7fff00ff)
+#define VI_TS_CONTROL_0_WRITE_MASK                      _MK_MASK_CONST(0x7fff00ff)
+// This field indicates the polarity of TS_VALID. Only has affect when TS_MODE.ENABLE == ENABLED    LOW indicates that the polarity of TS_VALID is active low.
+//    HIGH indicates that the polarity of TS_VALID is active high.
+#define VI_TS_CONTROL_0_VALID_POLARITY_SHIFT                    _MK_SHIFT_CONST(0)
+#define VI_TS_CONTROL_0_VALID_POLARITY_FIELD                    (_MK_MASK_CONST(0x1) << VI_TS_CONTROL_0_VALID_POLARITY_SHIFT)
+#define VI_TS_CONTROL_0_VALID_POLARITY_RANGE                    0:0
+#define VI_TS_CONTROL_0_VALID_POLARITY_WOFFSET                  0x0
+#define VI_TS_CONTROL_0_VALID_POLARITY_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_TS_CONTROL_0_VALID_POLARITY_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_TS_CONTROL_0_VALID_POLARITY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_TS_CONTROL_0_VALID_POLARITY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_TS_CONTROL_0_VALID_POLARITY_HIGH                     _MK_ENUM_CONST(0)
+#define VI_TS_CONTROL_0_VALID_POLARITY_LOW                      _MK_ENUM_CONST(1)
+
+#define VI_TS_CONTROL_0_PSYNC_POLARITY_SHIFT                    _MK_SHIFT_CONST(1)
+#define VI_TS_CONTROL_0_PSYNC_POLARITY_FIELD                    (_MK_MASK_CONST(0x1) << VI_TS_CONTROL_0_PSYNC_POLARITY_SHIFT)
+#define VI_TS_CONTROL_0_PSYNC_POLARITY_RANGE                    1:1
+#define VI_TS_CONTROL_0_PSYNC_POLARITY_WOFFSET                  0x0
+#define VI_TS_CONTROL_0_PSYNC_POLARITY_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_TS_CONTROL_0_PSYNC_POLARITY_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_TS_CONTROL_0_PSYNC_POLARITY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_TS_CONTROL_0_PSYNC_POLARITY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_TS_CONTROL_0_PSYNC_POLARITY_HIGH                     _MK_ENUM_CONST(0)
+#define VI_TS_CONTROL_0_PSYNC_POLARITY_LOW                      _MK_ENUM_CONST(1)
+
+#define VI_TS_CONTROL_0_ERROR_POLARITY_SHIFT                    _MK_SHIFT_CONST(2)
+#define VI_TS_CONTROL_0_ERROR_POLARITY_FIELD                    (_MK_MASK_CONST(0x1) << VI_TS_CONTROL_0_ERROR_POLARITY_SHIFT)
+#define VI_TS_CONTROL_0_ERROR_POLARITY_RANGE                    2:2
+#define VI_TS_CONTROL_0_ERROR_POLARITY_WOFFSET                  0x0
+#define VI_TS_CONTROL_0_ERROR_POLARITY_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_TS_CONTROL_0_ERROR_POLARITY_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_TS_CONTROL_0_ERROR_POLARITY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_TS_CONTROL_0_ERROR_POLARITY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_TS_CONTROL_0_ERROR_POLARITY_HIGH                     _MK_ENUM_CONST(0)
+#define VI_TS_CONTROL_0_ERROR_POLARITY_LOW                      _MK_ENUM_CONST(1)
+
+#define VI_TS_CONTROL_0_CLK_POLARITY_SHIFT                      _MK_SHIFT_CONST(3)
+#define VI_TS_CONTROL_0_CLK_POLARITY_FIELD                      (_MK_MASK_CONST(0x1) << VI_TS_CONTROL_0_CLK_POLARITY_SHIFT)
+#define VI_TS_CONTROL_0_CLK_POLARITY_RANGE                      3:3
+#define VI_TS_CONTROL_0_CLK_POLARITY_WOFFSET                    0x0
+#define VI_TS_CONTROL_0_CLK_POLARITY_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_TS_CONTROL_0_CLK_POLARITY_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_TS_CONTROL_0_CLK_POLARITY_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_TS_CONTROL_0_CLK_POLARITY_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_TS_CONTROL_0_CLK_POLARITY_HIGH                       _MK_ENUM_CONST(0)
+#define VI_TS_CONTROL_0_CLK_POLARITY_LOW                        _MK_ENUM_CONST(1)
+
+// This field defines how the START of packet condition is determined  PSYNC: PSYNC assertion rising edge
+//  VALID: VALID assertion rising edge
+//  BOTH:  PSYNC && VALID asserted rising edge
+#define VI_TS_CONTROL_0_START_SELECT_SHIFT                      _MK_SHIFT_CONST(4)
+#define VI_TS_CONTROL_0_START_SELECT_FIELD                      (_MK_MASK_CONST(0x3) << VI_TS_CONTROL_0_START_SELECT_SHIFT)
+#define VI_TS_CONTROL_0_START_SELECT_RANGE                      5:4
+#define VI_TS_CONTROL_0_START_SELECT_WOFFSET                    0x0
+#define VI_TS_CONTROL_0_START_SELECT_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_TS_CONTROL_0_START_SELECT_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_TS_CONTROL_0_START_SELECT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_TS_CONTROL_0_START_SELECT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_TS_CONTROL_0_START_SELECT_RESERVED                   _MK_ENUM_CONST(0)
+#define VI_TS_CONTROL_0_START_SELECT_PSYNC                      _MK_ENUM_CONST(1)
+#define VI_TS_CONTROL_0_START_SELECT_VALID                      _MK_ENUM_CONST(2)
+#define VI_TS_CONTROL_0_START_SELECT_BOTH                       _MK_ENUM_CONST(3)
+
+// This field determines if VALID is used during BODY packet capture  IGNORE: the VALID signal is ignored during the capture
+//  GATE: the VALID signal gates the capture of BODY data.
+#define VI_TS_CONTROL_0_BODY_VALID_SELECT_SHIFT                 _MK_SHIFT_CONST(6)
+#define VI_TS_CONTROL_0_BODY_VALID_SELECT_FIELD                 (_MK_MASK_CONST(0x1) << VI_TS_CONTROL_0_BODY_VALID_SELECT_SHIFT)
+#define VI_TS_CONTROL_0_BODY_VALID_SELECT_RANGE                 6:6
+#define VI_TS_CONTROL_0_BODY_VALID_SELECT_WOFFSET                       0x0
+#define VI_TS_CONTROL_0_BODY_VALID_SELECT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_TS_CONTROL_0_BODY_VALID_SELECT_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_TS_CONTROL_0_BODY_VALID_SELECT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_TS_CONTROL_0_BODY_VALID_SELECT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_TS_CONTROL_0_BODY_VALID_SELECT_IGNORE                        _MK_ENUM_CONST(0)
+#define VI_TS_CONTROL_0_BODY_VALID_SELECT_GATE                  _MK_ENUM_CONST(1)
+
+// This field determines is VI should store packets to memory that have been flagged as UPSTREAM_ERROR packets.
+//  DISCARD: Do not store packets in memory
+//  STORE:   Store UPSTREAM_ERROR packets in memory
+#define VI_TS_CONTROL_0_STORE_UPSTREAM_ERROR_PKTS_SHIFT                 _MK_SHIFT_CONST(7)
+#define VI_TS_CONTROL_0_STORE_UPSTREAM_ERROR_PKTS_FIELD                 (_MK_MASK_CONST(0x1) << VI_TS_CONTROL_0_STORE_UPSTREAM_ERROR_PKTS_SHIFT)
+#define VI_TS_CONTROL_0_STORE_UPSTREAM_ERROR_PKTS_RANGE                 7:7
+#define VI_TS_CONTROL_0_STORE_UPSTREAM_ERROR_PKTS_WOFFSET                       0x0
+#define VI_TS_CONTROL_0_STORE_UPSTREAM_ERROR_PKTS_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_TS_CONTROL_0_STORE_UPSTREAM_ERROR_PKTS_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_TS_CONTROL_0_STORE_UPSTREAM_ERROR_PKTS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_TS_CONTROL_0_STORE_UPSTREAM_ERROR_PKTS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_TS_CONTROL_0_STORE_UPSTREAM_ERROR_PKTS_DISCARD                       _MK_ENUM_CONST(0)
+#define VI_TS_CONTROL_0_STORE_UPSTREAM_ERROR_PKTS_STORE                 _MK_ENUM_CONST(1)
+
+// This field stores the number of BODY bytes to capture (including PSYNC)
+#define VI_TS_CONTROL_0_BODY_SIZE_SHIFT                 _MK_SHIFT_CONST(16)
+#define VI_TS_CONTROL_0_BODY_SIZE_FIELD                 (_MK_MASK_CONST(0xff) << VI_TS_CONTROL_0_BODY_SIZE_SHIFT)
+#define VI_TS_CONTROL_0_BODY_SIZE_RANGE                 23:16
+#define VI_TS_CONTROL_0_BODY_SIZE_WOFFSET                       0x0
+#define VI_TS_CONTROL_0_BODY_SIZE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_TS_CONTROL_0_BODY_SIZE_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_TS_CONTROL_0_BODY_SIZE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_TS_CONTROL_0_BODY_SIZE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// This field stores the number of FEC bytes to catpure (after the BODY has been captured)
+#define VI_TS_CONTROL_0_FEC_SIZE_SHIFT                  _MK_SHIFT_CONST(24)
+#define VI_TS_CONTROL_0_FEC_SIZE_FIELD                  (_MK_MASK_CONST(0x7f) << VI_TS_CONTROL_0_FEC_SIZE_SHIFT)
+#define VI_TS_CONTROL_0_FEC_SIZE_RANGE                  30:24
+#define VI_TS_CONTROL_0_FEC_SIZE_WOFFSET                        0x0
+#define VI_TS_CONTROL_0_FEC_SIZE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_TS_CONTROL_0_FEC_SIZE_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_TS_CONTROL_0_FEC_SIZE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_TS_CONTROL_0_FEC_SIZE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register VI_TS_PACKET_COUNT_0  // ISDB-T packet count register
+#define VI_TS_PACKET_COUNT_0                    _MK_ADDR_CONST(0x86)
+#define VI_TS_PACKET_COUNT_0_WORD_COUNT                         0x1
+#define VI_TS_PACKET_COUNT_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define VI_TS_PACKET_COUNT_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define VI_TS_PACKET_COUNT_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define VI_TS_PACKET_COUNT_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_TS_PACKET_COUNT_0_READ_MASK                  _MK_MASK_CONST(0x1ffff)
+#define VI_TS_PACKET_COUNT_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
+// This field holds the current value of the received packet counter.  This counter increments
+// in the presence of a new packet, regardless of whether it is flagged as an error
+// The counter can be cleared by writing this register with 0's and can also
+// be preloaded to any value by writing the preload value to the register.
+#define VI_TS_PACKET_COUNT_0_TS_PACKET_COUNT_VALUE_SHIFT                        _MK_SHIFT_CONST(0)
+#define VI_TS_PACKET_COUNT_0_TS_PACKET_COUNT_VALUE_FIELD                        (_MK_MASK_CONST(0xffff) << VI_TS_PACKET_COUNT_0_TS_PACKET_COUNT_VALUE_SHIFT)
+#define VI_TS_PACKET_COUNT_0_TS_PACKET_COUNT_VALUE_RANGE                        15:0
+#define VI_TS_PACKET_COUNT_0_TS_PACKET_COUNT_VALUE_WOFFSET                      0x0
+#define VI_TS_PACKET_COUNT_0_TS_PACKET_COUNT_VALUE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_TS_PACKET_COUNT_0_TS_PACKET_COUNT_VALUE_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_TS_PACKET_COUNT_0_TS_PACKET_COUNT_VALUE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_TS_PACKET_COUNT_0_TS_PACKET_COUNT_VALUE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// This field is set to OVERFLOW when VALUE passes from 0xFFFF to 0x0000. It stays high until the CPU writes a zero to this bit to reset it.
+#define VI_TS_PACKET_COUNT_0_TS_PACKET_COUNT_VALUE_OVERFLOW_SHIFT                       _MK_SHIFT_CONST(16)
+#define VI_TS_PACKET_COUNT_0_TS_PACKET_COUNT_VALUE_OVERFLOW_FIELD                       (_MK_MASK_CONST(0x1) << VI_TS_PACKET_COUNT_0_TS_PACKET_COUNT_VALUE_OVERFLOW_SHIFT)
+#define VI_TS_PACKET_COUNT_0_TS_PACKET_COUNT_VALUE_OVERFLOW_RANGE                       16:16
+#define VI_TS_PACKET_COUNT_0_TS_PACKET_COUNT_VALUE_OVERFLOW_WOFFSET                     0x0
+#define VI_TS_PACKET_COUNT_0_TS_PACKET_COUNT_VALUE_OVERFLOW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_TS_PACKET_COUNT_0_TS_PACKET_COUNT_VALUE_OVERFLOW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_TS_PACKET_COUNT_0_TS_PACKET_COUNT_VALUE_OVERFLOW_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_TS_PACKET_COUNT_0_TS_PACKET_COUNT_VALUE_OVERFLOW_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_TS_PACKET_COUNT_0_TS_PACKET_COUNT_VALUE_OVERFLOW_NONE                        _MK_ENUM_CONST(0)
+#define VI_TS_PACKET_COUNT_0_TS_PACKET_COUNT_VALUE_OVERFLOW_OVERFLOW                    _MK_ENUM_CONST(1)
+
+
+// Register VI_TS_ERROR_COUNT_0  // ISDB-T error count register
+#define VI_TS_ERROR_COUNT_0                     _MK_ADDR_CONST(0x87)
+#define VI_TS_ERROR_COUNT_0_WORD_COUNT                  0x1
+#define VI_TS_ERROR_COUNT_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define VI_TS_ERROR_COUNT_0_RESET_MASK                  _MK_MASK_CONST(0x0)
+#define VI_TS_ERROR_COUNT_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define VI_TS_ERROR_COUNT_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_TS_ERROR_COUNT_0_READ_MASK                   _MK_MASK_CONST(0x1ffff)
+#define VI_TS_ERROR_COUNT_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+// This field holds the current value of the error packet counter.  This counter increments in the
+// presence of a packet flagged as error (see TS_ERROR)0000 or a detected protocol violation.
+// The counter can be cleared by writing this register with 0's and can also
+// be preloaded to any value by writing the preload value to the register.
+#define VI_TS_ERROR_COUNT_0_TS_ERROR_COUNT_VALUE_SHIFT                  _MK_SHIFT_CONST(0)
+#define VI_TS_ERROR_COUNT_0_TS_ERROR_COUNT_VALUE_FIELD                  (_MK_MASK_CONST(0xffff) << VI_TS_ERROR_COUNT_0_TS_ERROR_COUNT_VALUE_SHIFT)
+#define VI_TS_ERROR_COUNT_0_TS_ERROR_COUNT_VALUE_RANGE                  15:0
+#define VI_TS_ERROR_COUNT_0_TS_ERROR_COUNT_VALUE_WOFFSET                        0x0
+#define VI_TS_ERROR_COUNT_0_TS_ERROR_COUNT_VALUE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_TS_ERROR_COUNT_0_TS_ERROR_COUNT_VALUE_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_TS_ERROR_COUNT_0_TS_ERROR_COUNT_VALUE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_TS_ERROR_COUNT_0_TS_ERROR_COUNT_VALUE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// This field is set to OVEFLOW when VALUE passes from 0xFFFF to 0x0000. It stays high until the CPU writes a zero to this bit to reset it.
+#define VI_TS_ERROR_COUNT_0_TS_ERROR_COUNT_VALUE_OVERFLOW_SHIFT                 _MK_SHIFT_CONST(16)
+#define VI_TS_ERROR_COUNT_0_TS_ERROR_COUNT_VALUE_OVERFLOW_FIELD                 (_MK_MASK_CONST(0x1) << VI_TS_ERROR_COUNT_0_TS_ERROR_COUNT_VALUE_OVERFLOW_SHIFT)
+#define VI_TS_ERROR_COUNT_0_TS_ERROR_COUNT_VALUE_OVERFLOW_RANGE                 16:16
+#define VI_TS_ERROR_COUNT_0_TS_ERROR_COUNT_VALUE_OVERFLOW_WOFFSET                       0x0
+#define VI_TS_ERROR_COUNT_0_TS_ERROR_COUNT_VALUE_OVERFLOW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_TS_ERROR_COUNT_0_TS_ERROR_COUNT_VALUE_OVERFLOW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_TS_ERROR_COUNT_0_TS_ERROR_COUNT_VALUE_OVERFLOW_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_TS_ERROR_COUNT_0_TS_ERROR_COUNT_VALUE_OVERFLOW_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_TS_ERROR_COUNT_0_TS_ERROR_COUNT_VALUE_OVERFLOW_NONE                  _MK_ENUM_CONST(0)
+#define VI_TS_ERROR_COUNT_0_TS_ERROR_COUNT_VALUE_OVERFLOW_OVERFLOW                      _MK_ENUM_CONST(1)
+
+
+// Register VI_TS_CPU_FLOW_CTL_0  // ISDB-T CPU flow control register
+#define VI_TS_CPU_FLOW_CTL_0                    _MK_ADDR_CONST(0x88)
+#define VI_TS_CPU_FLOW_CTL_0_WORD_COUNT                         0x1
+#define VI_TS_CPU_FLOW_CTL_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define VI_TS_CPU_FLOW_CTL_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define VI_TS_CPU_FLOW_CTL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define VI_TS_CPU_FLOW_CTL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_TS_CPU_FLOW_CTL_0_READ_MASK                  _MK_MASK_CONST(0x1)
+#define VI_TS_CPU_FLOW_CTL_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
+// Used only when the FLOW_CONTROL_MODE register is set to CPU
+// SW must write this register to release each buffer back to
+// WDMA.  Failure to write this register when buffers are
+// consumed will result in the WDMA stalling when it consumes all
+// allocated/free buffers.
+#define VI_TS_CPU_FLOW_CTL_0_BUFFER_RELEASE_SHIFT                       _MK_SHIFT_CONST(0)
+#define VI_TS_CPU_FLOW_CTL_0_BUFFER_RELEASE_FIELD                       (_MK_MASK_CONST(0x1) << VI_TS_CPU_FLOW_CTL_0_BUFFER_RELEASE_SHIFT)
+#define VI_TS_CPU_FLOW_CTL_0_BUFFER_RELEASE_RANGE                       0:0
+#define VI_TS_CPU_FLOW_CTL_0_BUFFER_RELEASE_WOFFSET                     0x0
+#define VI_TS_CPU_FLOW_CTL_0_BUFFER_RELEASE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_TS_CPU_FLOW_CTL_0_BUFFER_RELEASE_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_TS_CPU_FLOW_CTL_0_BUFFER_RELEASE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_TS_CPU_FLOW_CTL_0_BUFFER_RELEASE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register VI_VB0_CHROMA_BUFFER_STRIDE_FIRST_0  // Video Buffer Set 0 Chroma Buffer Stride.
+// This feature was introduced in SC17,
+// and represents an alternative value to using
+// VB0_BUFFER_STRIDE_C.
+#define VI_VB0_CHROMA_BUFFER_STRIDE_FIRST_0                     _MK_ADDR_CONST(0x89)
+#define VI_VB0_CHROMA_BUFFER_STRIDE_FIRST_0_WORD_COUNT                  0x1
+#define VI_VB0_CHROMA_BUFFER_STRIDE_FIRST_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define VI_VB0_CHROMA_BUFFER_STRIDE_FIRST_0_RESET_MASK                  _MK_MASK_CONST(0x80000000)
+#define VI_VB0_CHROMA_BUFFER_STRIDE_FIRST_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define VI_VB0_CHROMA_BUFFER_STRIDE_FIRST_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_VB0_CHROMA_BUFFER_STRIDE_FIRST_0_READ_MASK                   _MK_MASK_CONST(0xbfffffff)
+#define VI_VB0_CHROMA_BUFFER_STRIDE_FIRST_0_WRITE_MASK                  _MK_MASK_CONST(0xbfffffff)
+// Chroma buffer stride in bytes
+// 30 reserved
+#define VI_VB0_CHROMA_BUFFER_STRIDE_FIRST_0_VB0_CHROMA_BUFFER_STRIDE_SHIFT                      _MK_SHIFT_CONST(0)
+#define VI_VB0_CHROMA_BUFFER_STRIDE_FIRST_0_VB0_CHROMA_BUFFER_STRIDE_FIELD                      (_MK_MASK_CONST(0x3fffffff) << VI_VB0_CHROMA_BUFFER_STRIDE_FIRST_0_VB0_CHROMA_BUFFER_STRIDE_SHIFT)
+#define VI_VB0_CHROMA_BUFFER_STRIDE_FIRST_0_VB0_CHROMA_BUFFER_STRIDE_RANGE                      29:0
+#define VI_VB0_CHROMA_BUFFER_STRIDE_FIRST_0_VB0_CHROMA_BUFFER_STRIDE_WOFFSET                    0x0
+#define VI_VB0_CHROMA_BUFFER_STRIDE_FIRST_0_VB0_CHROMA_BUFFER_STRIDE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_VB0_CHROMA_BUFFER_STRIDE_FIRST_0_VB0_CHROMA_BUFFER_STRIDE_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_VB0_CHROMA_BUFFER_STRIDE_FIRST_0_VB0_CHROMA_BUFFER_STRIDE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_VB0_CHROMA_BUFFER_STRIDE_FIRST_0_VB0_CHROMA_BUFFER_STRIDE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// select type of Chroma buffer stride: 0 = Use VB0_BUFFER_STRIDE_C, deriving chroma
+// buffer stride from luma buffer stride
+// (default and backward compatible to SC15).
+// 1 = Use VB0_CHROMA_BUFFER_STRIDE.
+#define VI_VB0_CHROMA_BUFFER_STRIDE_FIRST_0_VB0_CHROMA_BUFFER_STRIDE_SELECT_SHIFT                       _MK_SHIFT_CONST(31)
+#define VI_VB0_CHROMA_BUFFER_STRIDE_FIRST_0_VB0_CHROMA_BUFFER_STRIDE_SELECT_FIELD                       (_MK_MASK_CONST(0x1) << VI_VB0_CHROMA_BUFFER_STRIDE_FIRST_0_VB0_CHROMA_BUFFER_STRIDE_SELECT_SHIFT)
+#define VI_VB0_CHROMA_BUFFER_STRIDE_FIRST_0_VB0_CHROMA_BUFFER_STRIDE_SELECT_RANGE                       31:31
+#define VI_VB0_CHROMA_BUFFER_STRIDE_FIRST_0_VB0_CHROMA_BUFFER_STRIDE_SELECT_WOFFSET                     0x0
+#define VI_VB0_CHROMA_BUFFER_STRIDE_FIRST_0_VB0_CHROMA_BUFFER_STRIDE_SELECT_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_VB0_CHROMA_BUFFER_STRIDE_FIRST_0_VB0_CHROMA_BUFFER_STRIDE_SELECT_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define VI_VB0_CHROMA_BUFFER_STRIDE_FIRST_0_VB0_CHROMA_BUFFER_STRIDE_SELECT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_VB0_CHROMA_BUFFER_STRIDE_FIRST_0_VB0_CHROMA_BUFFER_STRIDE_SELECT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_VB0_CHROMA_BUFFER_STRIDE_FIRST_0_VB0_CHROMA_BUFFER_STRIDE_SELECT_RATIO                       _MK_ENUM_CONST(0)
+#define VI_VB0_CHROMA_BUFFER_STRIDE_FIRST_0_VB0_CHROMA_BUFFER_STRIDE_SELECT_VALUE                       _MK_ENUM_CONST(1)
+
+
+// Register VI_VB0_CHROMA_LINE_STRIDE_FIRST_0  // Video Buffer Set 0 chroma line stride for First Output of planar YUV formats
+#define VI_VB0_CHROMA_LINE_STRIDE_FIRST_0                       _MK_ADDR_CONST(0x8a)
+#define VI_VB0_CHROMA_LINE_STRIDE_FIRST_0_WORD_COUNT                    0x1
+#define VI_VB0_CHROMA_LINE_STRIDE_FIRST_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define VI_VB0_CHROMA_LINE_STRIDE_FIRST_0_RESET_MASK                    _MK_MASK_CONST(0x80000000)
+#define VI_VB0_CHROMA_LINE_STRIDE_FIRST_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define VI_VB0_CHROMA_LINE_STRIDE_FIRST_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_VB0_CHROMA_LINE_STRIDE_FIRST_0_READ_MASK                     _MK_MASK_CONST(0x80001fff)
+#define VI_VB0_CHROMA_LINE_STRIDE_FIRST_0_WRITE_MASK                    _MK_MASK_CONST(0x80001fff)
+// Video Buffer Set 0 chroma horizontal size
+//  This parameter specifies the chroma line stride
+//  (in pixels) for lines in the video buffer
+//  set 0.
+//  this parameter
+//  must be programmed as multiple of 4 pixels
+//  (bits 1-0 are ignored).
+#define VI_VB0_CHROMA_LINE_STRIDE_FIRST_0_VB0_CHROMA_H_SIZE_1_SHIFT                     _MK_SHIFT_CONST(0)
+#define VI_VB0_CHROMA_LINE_STRIDE_FIRST_0_VB0_CHROMA_H_SIZE_1_FIELD                     (_MK_MASK_CONST(0x1fff) << VI_VB0_CHROMA_LINE_STRIDE_FIRST_0_VB0_CHROMA_H_SIZE_1_SHIFT)
+#define VI_VB0_CHROMA_LINE_STRIDE_FIRST_0_VB0_CHROMA_H_SIZE_1_RANGE                     12:0
+#define VI_VB0_CHROMA_LINE_STRIDE_FIRST_0_VB0_CHROMA_H_SIZE_1_WOFFSET                   0x0
+#define VI_VB0_CHROMA_LINE_STRIDE_FIRST_0_VB0_CHROMA_H_SIZE_1_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_VB0_CHROMA_LINE_STRIDE_FIRST_0_VB0_CHROMA_H_SIZE_1_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_VB0_CHROMA_LINE_STRIDE_FIRST_0_VB0_CHROMA_H_SIZE_1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_VB0_CHROMA_LINE_STRIDE_FIRST_0_VB0_CHROMA_H_SIZE_1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// select type of Chroma line stride: 0 = Use VB0_H_SIZE_1, deriving chroma line stride from luma line stride (default and backward compatible to SC15).
+// 1 = Use VB0_CHROMA_H_SIZE_1.
+#define VI_VB0_CHROMA_LINE_STRIDE_FIRST_0_VB0_CHROMA_LINE_STRIDE_SELECT_SHIFT                   _MK_SHIFT_CONST(31)
+#define VI_VB0_CHROMA_LINE_STRIDE_FIRST_0_VB0_CHROMA_LINE_STRIDE_SELECT_FIELD                   (_MK_MASK_CONST(0x1) << VI_VB0_CHROMA_LINE_STRIDE_FIRST_0_VB0_CHROMA_LINE_STRIDE_SELECT_SHIFT)
+#define VI_VB0_CHROMA_LINE_STRIDE_FIRST_0_VB0_CHROMA_LINE_STRIDE_SELECT_RANGE                   31:31
+#define VI_VB0_CHROMA_LINE_STRIDE_FIRST_0_VB0_CHROMA_LINE_STRIDE_SELECT_WOFFSET                 0x0
+#define VI_VB0_CHROMA_LINE_STRIDE_FIRST_0_VB0_CHROMA_LINE_STRIDE_SELECT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_VB0_CHROMA_LINE_STRIDE_FIRST_0_VB0_CHROMA_LINE_STRIDE_SELECT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define VI_VB0_CHROMA_LINE_STRIDE_FIRST_0_VB0_CHROMA_LINE_STRIDE_SELECT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_VB0_CHROMA_LINE_STRIDE_FIRST_0_VB0_CHROMA_LINE_STRIDE_SELECT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_VB0_CHROMA_LINE_STRIDE_FIRST_0_VB0_CHROMA_LINE_STRIDE_SELECT_RATIO                   _MK_ENUM_CONST(0)
+#define VI_VB0_CHROMA_LINE_STRIDE_FIRST_0_VB0_CHROMA_LINE_STRIDE_SELECT_VALUE                   _MK_ENUM_CONST(1)
+
+
+// Register VI_EPP_LINES_PER_BUFFER_0  // number of buffers per output frame in EPP
+#define VI_EPP_LINES_PER_BUFFER_0                       _MK_ADDR_CONST(0x8b)
+#define VI_EPP_LINES_PER_BUFFER_0_WORD_COUNT                    0x1
+#define VI_EPP_LINES_PER_BUFFER_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define VI_EPP_LINES_PER_BUFFER_0_RESET_MASK                    _MK_MASK_CONST(0x0)
+#define VI_EPP_LINES_PER_BUFFER_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define VI_EPP_LINES_PER_BUFFER_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_EPP_LINES_PER_BUFFER_0_READ_MASK                     _MK_MASK_CONST(0x1fff)
+#define VI_EPP_LINES_PER_BUFFER_0_WRITE_MASK                    _MK_MASK_CONST(0x1fff)
+// maximum 256 buffers per frame.
+// linesPerBuffer = FLOOR(eppLineCount/eppBufferCount)
+// linesPerBuffer must be > 2
+// eppLineCount must take into account any cropping in EPP.
+#define VI_EPP_LINES_PER_BUFFER_0_LINES_PER_BUFFER_SHIFT                        _MK_SHIFT_CONST(0)
+#define VI_EPP_LINES_PER_BUFFER_0_LINES_PER_BUFFER_FIELD                        (_MK_MASK_CONST(0x1fff) << VI_EPP_LINES_PER_BUFFER_0_LINES_PER_BUFFER_SHIFT)
+#define VI_EPP_LINES_PER_BUFFER_0_LINES_PER_BUFFER_RANGE                        12:0
+#define VI_EPP_LINES_PER_BUFFER_0_LINES_PER_BUFFER_WOFFSET                      0x0
+#define VI_EPP_LINES_PER_BUFFER_0_LINES_PER_BUFFER_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_EPP_LINES_PER_BUFFER_0_LINES_PER_BUFFER_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_EPP_LINES_PER_BUFFER_0_LINES_PER_BUFFER_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_EPP_LINES_PER_BUFFER_0_LINES_PER_BUFFER_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register VI_BUFFER_RELEASE_OUTPUT1_0  // write to this register will decrease
+// BUFFER_COUNTER by 1
+#define VI_BUFFER_RELEASE_OUTPUT1_0                     _MK_ADDR_CONST(0x8c)
+#define VI_BUFFER_RELEASE_OUTPUT1_0_WORD_COUNT                  0x1
+#define VI_BUFFER_RELEASE_OUTPUT1_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define VI_BUFFER_RELEASE_OUTPUT1_0_RESET_MASK                  _MK_MASK_CONST(0x0)
+#define VI_BUFFER_RELEASE_OUTPUT1_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define VI_BUFFER_RELEASE_OUTPUT1_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_BUFFER_RELEASE_OUTPUT1_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define VI_BUFFER_RELEASE_OUTPUT1_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
+#define VI_BUFFER_RELEASE_OUTPUT1_0_BUFFER_RELEASE_OUTPUT1_SHIFT                        _MK_SHIFT_CONST(0)
+#define VI_BUFFER_RELEASE_OUTPUT1_0_BUFFER_RELEASE_OUTPUT1_FIELD                        (_MK_MASK_CONST(0x1) << VI_BUFFER_RELEASE_OUTPUT1_0_BUFFER_RELEASE_OUTPUT1_SHIFT)
+#define VI_BUFFER_RELEASE_OUTPUT1_0_BUFFER_RELEASE_OUTPUT1_RANGE                        0:0
+#define VI_BUFFER_RELEASE_OUTPUT1_0_BUFFER_RELEASE_OUTPUT1_WOFFSET                      0x0
+#define VI_BUFFER_RELEASE_OUTPUT1_0_BUFFER_RELEASE_OUTPUT1_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_BUFFER_RELEASE_OUTPUT1_0_BUFFER_RELEASE_OUTPUT1_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_BUFFER_RELEASE_OUTPUT1_0_BUFFER_RELEASE_OUTPUT1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_BUFFER_RELEASE_OUTPUT1_0_BUFFER_RELEASE_OUTPUT1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register VI_BUFFER_RELEASE_OUTPUT2_0  
+#define VI_BUFFER_RELEASE_OUTPUT2_0                     _MK_ADDR_CONST(0x8d)
+#define VI_BUFFER_RELEASE_OUTPUT2_0_WORD_COUNT                  0x1
+#define VI_BUFFER_RELEASE_OUTPUT2_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define VI_BUFFER_RELEASE_OUTPUT2_0_RESET_MASK                  _MK_MASK_CONST(0x0)
+#define VI_BUFFER_RELEASE_OUTPUT2_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define VI_BUFFER_RELEASE_OUTPUT2_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_BUFFER_RELEASE_OUTPUT2_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define VI_BUFFER_RELEASE_OUTPUT2_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
+#define VI_BUFFER_RELEASE_OUTPUT2_0_BUFFER_RELEASE_OUTPUT2_SHIFT                        _MK_SHIFT_CONST(0)
+#define VI_BUFFER_RELEASE_OUTPUT2_0_BUFFER_RELEASE_OUTPUT2_FIELD                        (_MK_MASK_CONST(0x1) << VI_BUFFER_RELEASE_OUTPUT2_0_BUFFER_RELEASE_OUTPUT2_SHIFT)
+#define VI_BUFFER_RELEASE_OUTPUT2_0_BUFFER_RELEASE_OUTPUT2_RANGE                        0:0
+#define VI_BUFFER_RELEASE_OUTPUT2_0_BUFFER_RELEASE_OUTPUT2_WOFFSET                      0x0
+#define VI_BUFFER_RELEASE_OUTPUT2_0_BUFFER_RELEASE_OUTPUT2_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_BUFFER_RELEASE_OUTPUT2_0_BUFFER_RELEASE_OUTPUT2_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_BUFFER_RELEASE_OUTPUT2_0_BUFFER_RELEASE_OUTPUT2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_BUFFER_RELEASE_OUTPUT2_0_BUFFER_RELEASE_OUTPUT2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register VI_DEBUG_FLOW_CONTROL_COUNTER_OUTPUT1_0  // this is a debug register
+#define VI_DEBUG_FLOW_CONTROL_COUNTER_OUTPUT1_0                 _MK_ADDR_CONST(0x8e)
+#define VI_DEBUG_FLOW_CONTROL_COUNTER_OUTPUT1_0_WORD_COUNT                      0x1
+#define VI_DEBUG_FLOW_CONTROL_COUNTER_OUTPUT1_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define VI_DEBUG_FLOW_CONTROL_COUNTER_OUTPUT1_0_RESET_MASK                      _MK_MASK_CONST(0x0)
+#define VI_DEBUG_FLOW_CONTROL_COUNTER_OUTPUT1_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define VI_DEBUG_FLOW_CONTROL_COUNTER_OUTPUT1_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define VI_DEBUG_FLOW_CONTROL_COUNTER_OUTPUT1_0_READ_MASK                       _MK_MASK_CONST(0xff)
+#define VI_DEBUG_FLOW_CONTROL_COUNTER_OUTPUT1_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
+#define VI_DEBUG_FLOW_CONTROL_COUNTER_OUTPUT1_0_BUFFER_COUNT_OUTPUT1_SHIFT                      _MK_SHIFT_CONST(0)
+#define VI_DEBUG_FLOW_CONTROL_COUNTER_OUTPUT1_0_BUFFER_COUNT_OUTPUT1_FIELD                      (_MK_MASK_CONST(0xff) << VI_DEBUG_FLOW_CONTROL_COUNTER_OUTPUT1_0_BUFFER_COUNT_OUTPUT1_SHIFT)
+#define VI_DEBUG_FLOW_CONTROL_COUNTER_OUTPUT1_0_BUFFER_COUNT_OUTPUT1_RANGE                      7:0
+#define VI_DEBUG_FLOW_CONTROL_COUNTER_OUTPUT1_0_BUFFER_COUNT_OUTPUT1_WOFFSET                    0x0
+#define VI_DEBUG_FLOW_CONTROL_COUNTER_OUTPUT1_0_BUFFER_COUNT_OUTPUT1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_DEBUG_FLOW_CONTROL_COUNTER_OUTPUT1_0_BUFFER_COUNT_OUTPUT1_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_DEBUG_FLOW_CONTROL_COUNTER_OUTPUT1_0_BUFFER_COUNT_OUTPUT1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_DEBUG_FLOW_CONTROL_COUNTER_OUTPUT1_0_BUFFER_COUNT_OUTPUT1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register VI_DEBUG_FLOW_CONTROL_COUNTER_OUTPUT2_0  
+#define VI_DEBUG_FLOW_CONTROL_COUNTER_OUTPUT2_0                 _MK_ADDR_CONST(0x8f)
+#define VI_DEBUG_FLOW_CONTROL_COUNTER_OUTPUT2_0_WORD_COUNT                      0x1
+#define VI_DEBUG_FLOW_CONTROL_COUNTER_OUTPUT2_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define VI_DEBUG_FLOW_CONTROL_COUNTER_OUTPUT2_0_RESET_MASK                      _MK_MASK_CONST(0x0)
+#define VI_DEBUG_FLOW_CONTROL_COUNTER_OUTPUT2_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define VI_DEBUG_FLOW_CONTROL_COUNTER_OUTPUT2_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define VI_DEBUG_FLOW_CONTROL_COUNTER_OUTPUT2_0_READ_MASK                       _MK_MASK_CONST(0xff)
+#define VI_DEBUG_FLOW_CONTROL_COUNTER_OUTPUT2_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
+#define VI_DEBUG_FLOW_CONTROL_COUNTER_OUTPUT2_0_BUFFER_COUNT_OUTPUT2_SHIFT                      _MK_SHIFT_CONST(0)
+#define VI_DEBUG_FLOW_CONTROL_COUNTER_OUTPUT2_0_BUFFER_COUNT_OUTPUT2_FIELD                      (_MK_MASK_CONST(0xff) << VI_DEBUG_FLOW_CONTROL_COUNTER_OUTPUT2_0_BUFFER_COUNT_OUTPUT2_SHIFT)
+#define VI_DEBUG_FLOW_CONTROL_COUNTER_OUTPUT2_0_BUFFER_COUNT_OUTPUT2_RANGE                      7:0
+#define VI_DEBUG_FLOW_CONTROL_COUNTER_OUTPUT2_0_BUFFER_COUNT_OUTPUT2_WOFFSET                    0x0
+#define VI_DEBUG_FLOW_CONTROL_COUNTER_OUTPUT2_0_BUFFER_COUNT_OUTPUT2_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_DEBUG_FLOW_CONTROL_COUNTER_OUTPUT2_0_BUFFER_COUNT_OUTPUT2_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_DEBUG_FLOW_CONTROL_COUNTER_OUTPUT2_0_BUFFER_COUNT_OUTPUT2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_DEBUG_FLOW_CONTROL_COUNTER_OUTPUT2_0_BUFFER_COUNT_OUTPUT2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register VI_TERMINATE_BW_FIRST_0  // write to this register will terminate
+// MC on BW operation in FIRST output.
+#define VI_TERMINATE_BW_FIRST_0                 _MK_ADDR_CONST(0x90)
+#define VI_TERMINATE_BW_FIRST_0_WORD_COUNT                      0x1
+#define VI_TERMINATE_BW_FIRST_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define VI_TERMINATE_BW_FIRST_0_RESET_MASK                      _MK_MASK_CONST(0x0)
+#define VI_TERMINATE_BW_FIRST_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define VI_TERMINATE_BW_FIRST_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define VI_TERMINATE_BW_FIRST_0_READ_MASK                       _MK_MASK_CONST(0x1)
+#define VI_TERMINATE_BW_FIRST_0_WRITE_MASK                      _MK_MASK_CONST(0x1)
+#define VI_TERMINATE_BW_FIRST_0_TERMINATE_FIRST_BW_SHIFT                        _MK_SHIFT_CONST(0)
+#define VI_TERMINATE_BW_FIRST_0_TERMINATE_FIRST_BW_FIELD                        (_MK_MASK_CONST(0x1) << VI_TERMINATE_BW_FIRST_0_TERMINATE_FIRST_BW_SHIFT)
+#define VI_TERMINATE_BW_FIRST_0_TERMINATE_FIRST_BW_RANGE                        0:0
+#define VI_TERMINATE_BW_FIRST_0_TERMINATE_FIRST_BW_WOFFSET                      0x0
+#define VI_TERMINATE_BW_FIRST_0_TERMINATE_FIRST_BW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_TERMINATE_BW_FIRST_0_TERMINATE_FIRST_BW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_TERMINATE_BW_FIRST_0_TERMINATE_FIRST_BW_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_TERMINATE_BW_FIRST_0_TERMINATE_FIRST_BW_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register VI_TERMINATE_BW_SECOND_0  // write to this register will terminate
+// MC on BW operationn in SECOND output.
+#define VI_TERMINATE_BW_SECOND_0                        _MK_ADDR_CONST(0x91)
+#define VI_TERMINATE_BW_SECOND_0_WORD_COUNT                     0x1
+#define VI_TERMINATE_BW_SECOND_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define VI_TERMINATE_BW_SECOND_0_RESET_MASK                     _MK_MASK_CONST(0x0)
+#define VI_TERMINATE_BW_SECOND_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define VI_TERMINATE_BW_SECOND_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_TERMINATE_BW_SECOND_0_READ_MASK                      _MK_MASK_CONST(0x1)
+#define VI_TERMINATE_BW_SECOND_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
+#define VI_TERMINATE_BW_SECOND_0_TERMINATE_SECOND_BW_SHIFT                      _MK_SHIFT_CONST(0)
+#define VI_TERMINATE_BW_SECOND_0_TERMINATE_SECOND_BW_FIELD                      (_MK_MASK_CONST(0x1) << VI_TERMINATE_BW_SECOND_0_TERMINATE_SECOND_BW_SHIFT)
+#define VI_TERMINATE_BW_SECOND_0_TERMINATE_SECOND_BW_RANGE                      0:0
+#define VI_TERMINATE_BW_SECOND_0_TERMINATE_SECOND_BW_WOFFSET                    0x0
+#define VI_TERMINATE_BW_SECOND_0_TERMINATE_SECOND_BW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_TERMINATE_BW_SECOND_0_TERMINATE_SECOND_BW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_TERMINATE_BW_SECOND_0_TERMINATE_SECOND_BW_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_TERMINATE_BW_SECOND_0_TERMINATE_SECOND_BW_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register VI_VB0_FIRST_BUFFER_ADDR_MODE_0  
+#define VI_VB0_FIRST_BUFFER_ADDR_MODE_0                 _MK_ADDR_CONST(0x92)
+#define VI_VB0_FIRST_BUFFER_ADDR_MODE_0_WORD_COUNT                      0x1
+#define VI_VB0_FIRST_BUFFER_ADDR_MODE_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define VI_VB0_FIRST_BUFFER_ADDR_MODE_0_RESET_MASK                      _MK_MASK_CONST(0x101)
+#define VI_VB0_FIRST_BUFFER_ADDR_MODE_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define VI_VB0_FIRST_BUFFER_ADDR_MODE_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define VI_VB0_FIRST_BUFFER_ADDR_MODE_0_READ_MASK                       _MK_MASK_CONST(0x101)
+#define VI_VB0_FIRST_BUFFER_ADDR_MODE_0_WRITE_MASK                      _MK_MASK_CONST(0x101)
+#define VI_VB0_FIRST_BUFFER_ADDR_MODE_0_Y1_TILE_MODE_SHIFT                      _MK_SHIFT_CONST(0)
+#define VI_VB0_FIRST_BUFFER_ADDR_MODE_0_Y1_TILE_MODE_FIELD                      (_MK_MASK_CONST(0x1) << VI_VB0_FIRST_BUFFER_ADDR_MODE_0_Y1_TILE_MODE_SHIFT)
+#define VI_VB0_FIRST_BUFFER_ADDR_MODE_0_Y1_TILE_MODE_RANGE                      0:0
+#define VI_VB0_FIRST_BUFFER_ADDR_MODE_0_Y1_TILE_MODE_WOFFSET                    0x0
+#define VI_VB0_FIRST_BUFFER_ADDR_MODE_0_Y1_TILE_MODE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_VB0_FIRST_BUFFER_ADDR_MODE_0_Y1_TILE_MODE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define VI_VB0_FIRST_BUFFER_ADDR_MODE_0_Y1_TILE_MODE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_VB0_FIRST_BUFFER_ADDR_MODE_0_Y1_TILE_MODE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_VB0_FIRST_BUFFER_ADDR_MODE_0_Y1_TILE_MODE_LINEAR                     _MK_ENUM_CONST(0)
+#define VI_VB0_FIRST_BUFFER_ADDR_MODE_0_Y1_TILE_MODE_TILED                      _MK_ENUM_CONST(1)
+
+#define VI_VB0_FIRST_BUFFER_ADDR_MODE_0_UV1_TILE_MODE_SHIFT                     _MK_SHIFT_CONST(8)
+#define VI_VB0_FIRST_BUFFER_ADDR_MODE_0_UV1_TILE_MODE_FIELD                     (_MK_MASK_CONST(0x1) << VI_VB0_FIRST_BUFFER_ADDR_MODE_0_UV1_TILE_MODE_SHIFT)
+#define VI_VB0_FIRST_BUFFER_ADDR_MODE_0_UV1_TILE_MODE_RANGE                     8:8
+#define VI_VB0_FIRST_BUFFER_ADDR_MODE_0_UV1_TILE_MODE_WOFFSET                   0x0
+#define VI_VB0_FIRST_BUFFER_ADDR_MODE_0_UV1_TILE_MODE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_VB0_FIRST_BUFFER_ADDR_MODE_0_UV1_TILE_MODE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define VI_VB0_FIRST_BUFFER_ADDR_MODE_0_UV1_TILE_MODE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_VB0_FIRST_BUFFER_ADDR_MODE_0_UV1_TILE_MODE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_VB0_FIRST_BUFFER_ADDR_MODE_0_UV1_TILE_MODE_LINEAR                    _MK_ENUM_CONST(0)
+#define VI_VB0_FIRST_BUFFER_ADDR_MODE_0_UV1_TILE_MODE_TILED                     _MK_ENUM_CONST(1)
+
+
+// Register VI_VB0_SECOND_BUFFER_ADDR_MODE_0  
+#define VI_VB0_SECOND_BUFFER_ADDR_MODE_0                        _MK_ADDR_CONST(0x93)
+#define VI_VB0_SECOND_BUFFER_ADDR_MODE_0_WORD_COUNT                     0x1
+#define VI_VB0_SECOND_BUFFER_ADDR_MODE_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define VI_VB0_SECOND_BUFFER_ADDR_MODE_0_RESET_MASK                     _MK_MASK_CONST(0x1)
+#define VI_VB0_SECOND_BUFFER_ADDR_MODE_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define VI_VB0_SECOND_BUFFER_ADDR_MODE_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_VB0_SECOND_BUFFER_ADDR_MODE_0_READ_MASK                      _MK_MASK_CONST(0x1)
+#define VI_VB0_SECOND_BUFFER_ADDR_MODE_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
+#define VI_VB0_SECOND_BUFFER_ADDR_MODE_0_Y2_TILE_MODE_SHIFT                     _MK_SHIFT_CONST(0)
+#define VI_VB0_SECOND_BUFFER_ADDR_MODE_0_Y2_TILE_MODE_FIELD                     (_MK_MASK_CONST(0x1) << VI_VB0_SECOND_BUFFER_ADDR_MODE_0_Y2_TILE_MODE_SHIFT)
+#define VI_VB0_SECOND_BUFFER_ADDR_MODE_0_Y2_TILE_MODE_RANGE                     0:0
+#define VI_VB0_SECOND_BUFFER_ADDR_MODE_0_Y2_TILE_MODE_WOFFSET                   0x0
+#define VI_VB0_SECOND_BUFFER_ADDR_MODE_0_Y2_TILE_MODE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_VB0_SECOND_BUFFER_ADDR_MODE_0_Y2_TILE_MODE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define VI_VB0_SECOND_BUFFER_ADDR_MODE_0_Y2_TILE_MODE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_VB0_SECOND_BUFFER_ADDR_MODE_0_Y2_TILE_MODE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_VB0_SECOND_BUFFER_ADDR_MODE_0_Y2_TILE_MODE_LINEAR                    _MK_ENUM_CONST(0)
+#define VI_VB0_SECOND_BUFFER_ADDR_MODE_0_Y2_TILE_MODE_TILED                     _MK_ENUM_CONST(1)
+
+
+// Register VI_RESERVE_0_0  // reserved register for emergency ...
+// bits[13:0] are reserved for
+// VIP Pattern Gen (Pattern Width)
+#define VI_RESERVE_0_0                  _MK_ADDR_CONST(0x94)
+#define VI_RESERVE_0_0_WORD_COUNT                       0x1
+#define VI_RESERVE_0_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define VI_RESERVE_0_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define VI_RESERVE_0_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define VI_RESERVE_0_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_RESERVE_0_0_READ_MASK                        _MK_MASK_CONST(0xffff)
+#define VI_RESERVE_0_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
+//  Program to *one less* than the desired
+#define VI_RESERVE_0_0_nc_RESERVE_0_0_SHIFT                     _MK_SHIFT_CONST(0)
+#define VI_RESERVE_0_0_nc_RESERVE_0_0_FIELD                     (_MK_MASK_CONST(0xf) << VI_RESERVE_0_0_nc_RESERVE_0_0_SHIFT)
+#define VI_RESERVE_0_0_nc_RESERVE_0_0_RANGE                     3:0
+#define VI_RESERVE_0_0_nc_RESERVE_0_0_WOFFSET                   0x0
+#define VI_RESERVE_0_0_nc_RESERVE_0_0_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_RESERVE_0_0_nc_RESERVE_0_0_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_RESERVE_0_0_nc_RESERVE_0_0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_RESERVE_0_0_nc_RESERVE_0_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+//  pattern width in clocks. (note that
+#define VI_RESERVE_0_0_nc_RESERVE_0_1_SHIFT                     _MK_SHIFT_CONST(4)
+#define VI_RESERVE_0_0_nc_RESERVE_0_1_FIELD                     (_MK_MASK_CONST(0xf) << VI_RESERVE_0_0_nc_RESERVE_0_1_SHIFT)
+#define VI_RESERVE_0_0_nc_RESERVE_0_1_RANGE                     7:4
+#define VI_RESERVE_0_0_nc_RESERVE_0_1_WOFFSET                   0x0
+#define VI_RESERVE_0_0_nc_RESERVE_0_1_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_RESERVE_0_0_nc_RESERVE_0_1_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_RESERVE_0_0_nc_RESERVE_0_1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_RESERVE_0_0_nc_RESERVE_0_1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+//  there are 2 clocker per pixel for YUV422)
+#define VI_RESERVE_0_0_nc_RESERVE_0_2_SHIFT                     _MK_SHIFT_CONST(8)
+#define VI_RESERVE_0_0_nc_RESERVE_0_2_FIELD                     (_MK_MASK_CONST(0xf) << VI_RESERVE_0_0_nc_RESERVE_0_2_SHIFT)
+#define VI_RESERVE_0_0_nc_RESERVE_0_2_RANGE                     11:8
+#define VI_RESERVE_0_0_nc_RESERVE_0_2_WOFFSET                   0x0
+#define VI_RESERVE_0_0_nc_RESERVE_0_2_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_RESERVE_0_0_nc_RESERVE_0_2_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_RESERVE_0_0_nc_RESERVE_0_2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_RESERVE_0_0_nc_RESERVE_0_2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define VI_RESERVE_0_0_nc_RESERVE_0_3_SHIFT                     _MK_SHIFT_CONST(12)
+#define VI_RESERVE_0_0_nc_RESERVE_0_3_FIELD                     (_MK_MASK_CONST(0xf) << VI_RESERVE_0_0_nc_RESERVE_0_3_SHIFT)
+#define VI_RESERVE_0_0_nc_RESERVE_0_3_RANGE                     15:12
+#define VI_RESERVE_0_0_nc_RESERVE_0_3_WOFFSET                   0x0
+#define VI_RESERVE_0_0_nc_RESERVE_0_3_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_RESERVE_0_0_nc_RESERVE_0_3_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_RESERVE_0_0_nc_RESERVE_0_3_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_RESERVE_0_0_nc_RESERVE_0_3_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register VI_RESERVE_1_0  // reserved register for emergency ...
+// bits[13:0] are reserved for
+// VIP Pattern Gen (Pattern Height)
+#define VI_RESERVE_1_0                  _MK_ADDR_CONST(0x95)
+#define VI_RESERVE_1_0_WORD_COUNT                       0x1
+#define VI_RESERVE_1_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define VI_RESERVE_1_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define VI_RESERVE_1_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define VI_RESERVE_1_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_RESERVE_1_0_READ_MASK                        _MK_MASK_CONST(0xffff)
+#define VI_RESERVE_1_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
+//  Program to *one less* than the desired
+#define VI_RESERVE_1_0_nc_RESERVE_1_0_SHIFT                     _MK_SHIFT_CONST(0)
+#define VI_RESERVE_1_0_nc_RESERVE_1_0_FIELD                     (_MK_MASK_CONST(0xf) << VI_RESERVE_1_0_nc_RESERVE_1_0_SHIFT)
+#define VI_RESERVE_1_0_nc_RESERVE_1_0_RANGE                     3:0
+#define VI_RESERVE_1_0_nc_RESERVE_1_0_WOFFSET                   0x0
+#define VI_RESERVE_1_0_nc_RESERVE_1_0_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_RESERVE_1_0_nc_RESERVE_1_0_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_RESERVE_1_0_nc_RESERVE_1_0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_RESERVE_1_0_nc_RESERVE_1_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+//  pattern height in lines
+#define VI_RESERVE_1_0_nc_RESERVE_1_1_SHIFT                     _MK_SHIFT_CONST(4)
+#define VI_RESERVE_1_0_nc_RESERVE_1_1_FIELD                     (_MK_MASK_CONST(0xf) << VI_RESERVE_1_0_nc_RESERVE_1_1_SHIFT)
+#define VI_RESERVE_1_0_nc_RESERVE_1_1_RANGE                     7:4
+#define VI_RESERVE_1_0_nc_RESERVE_1_1_WOFFSET                   0x0
+#define VI_RESERVE_1_0_nc_RESERVE_1_1_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_RESERVE_1_0_nc_RESERVE_1_1_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_RESERVE_1_0_nc_RESERVE_1_1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_RESERVE_1_0_nc_RESERVE_1_1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define VI_RESERVE_1_0_nc_RESERVE_1_2_SHIFT                     _MK_SHIFT_CONST(8)
+#define VI_RESERVE_1_0_nc_RESERVE_1_2_FIELD                     (_MK_MASK_CONST(0xf) << VI_RESERVE_1_0_nc_RESERVE_1_2_SHIFT)
+#define VI_RESERVE_1_0_nc_RESERVE_1_2_RANGE                     11:8
+#define VI_RESERVE_1_0_nc_RESERVE_1_2_WOFFSET                   0x0
+#define VI_RESERVE_1_0_nc_RESERVE_1_2_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_RESERVE_1_0_nc_RESERVE_1_2_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_RESERVE_1_0_nc_RESERVE_1_2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_RESERVE_1_0_nc_RESERVE_1_2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define VI_RESERVE_1_0_nc_RESERVE_1_3_SHIFT                     _MK_SHIFT_CONST(12)
+#define VI_RESERVE_1_0_nc_RESERVE_1_3_FIELD                     (_MK_MASK_CONST(0xf) << VI_RESERVE_1_0_nc_RESERVE_1_3_SHIFT)
+#define VI_RESERVE_1_0_nc_RESERVE_1_3_RANGE                     15:12
+#define VI_RESERVE_1_0_nc_RESERVE_1_3_WOFFSET                   0x0
+#define VI_RESERVE_1_0_nc_RESERVE_1_3_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_RESERVE_1_0_nc_RESERVE_1_3_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_RESERVE_1_0_nc_RESERVE_1_3_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_RESERVE_1_0_nc_RESERVE_1_3_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register VI_RESERVE_2_0  // reserved register for emergency ...
+// bit 0 is reserved for VIP Pattern Gen Enable
+// bit 1 is reserved for VIP Pattern Gen BayerSelect
+#define VI_RESERVE_2_0                  _MK_ADDR_CONST(0x96)
+#define VI_RESERVE_2_0_WORD_COUNT                       0x1
+#define VI_RESERVE_2_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define VI_RESERVE_2_0_RESET_MASK                       _MK_MASK_CONST(0xf)
+#define VI_RESERVE_2_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define VI_RESERVE_2_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_RESERVE_2_0_READ_MASK                        _MK_MASK_CONST(0xffff)
+#define VI_RESERVE_2_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
+// 1 for BAYER pattern and 0 for YUV pattern
+#define VI_RESERVE_2_0_nc_RESERVE_2_0_SHIFT                     _MK_SHIFT_CONST(0)
+#define VI_RESERVE_2_0_nc_RESERVE_2_0_FIELD                     (_MK_MASK_CONST(0xf) << VI_RESERVE_2_0_nc_RESERVE_2_0_SHIFT)
+#define VI_RESERVE_2_0_nc_RESERVE_2_0_RANGE                     3:0
+#define VI_RESERVE_2_0_nc_RESERVE_2_0_WOFFSET                   0x0
+#define VI_RESERVE_2_0_nc_RESERVE_2_0_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_RESERVE_2_0_nc_RESERVE_2_0_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define VI_RESERVE_2_0_nc_RESERVE_2_0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_RESERVE_2_0_nc_RESERVE_2_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define VI_RESERVE_2_0_nc_RESERVE_2_1_SHIFT                     _MK_SHIFT_CONST(4)
+#define VI_RESERVE_2_0_nc_RESERVE_2_1_FIELD                     (_MK_MASK_CONST(0xf) << VI_RESERVE_2_0_nc_RESERVE_2_1_SHIFT)
+#define VI_RESERVE_2_0_nc_RESERVE_2_1_RANGE                     7:4
+#define VI_RESERVE_2_0_nc_RESERVE_2_1_WOFFSET                   0x0
+#define VI_RESERVE_2_0_nc_RESERVE_2_1_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_RESERVE_2_0_nc_RESERVE_2_1_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_RESERVE_2_0_nc_RESERVE_2_1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_RESERVE_2_0_nc_RESERVE_2_1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define VI_RESERVE_2_0_nc_RESERVE_2_2_SHIFT                     _MK_SHIFT_CONST(8)
+#define VI_RESERVE_2_0_nc_RESERVE_2_2_FIELD                     (_MK_MASK_CONST(0xf) << VI_RESERVE_2_0_nc_RESERVE_2_2_SHIFT)
+#define VI_RESERVE_2_0_nc_RESERVE_2_2_RANGE                     11:8
+#define VI_RESERVE_2_0_nc_RESERVE_2_2_WOFFSET                   0x0
+#define VI_RESERVE_2_0_nc_RESERVE_2_2_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_RESERVE_2_0_nc_RESERVE_2_2_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_RESERVE_2_0_nc_RESERVE_2_2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_RESERVE_2_0_nc_RESERVE_2_2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define VI_RESERVE_2_0_nc_RESERVE_2_3_SHIFT                     _MK_SHIFT_CONST(12)
+#define VI_RESERVE_2_0_nc_RESERVE_2_3_FIELD                     (_MK_MASK_CONST(0xf) << VI_RESERVE_2_0_nc_RESERVE_2_3_SHIFT)
+#define VI_RESERVE_2_0_nc_RESERVE_2_3_RANGE                     15:12
+#define VI_RESERVE_2_0_nc_RESERVE_2_3_WOFFSET                   0x0
+#define VI_RESERVE_2_0_nc_RESERVE_2_3_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_RESERVE_2_0_nc_RESERVE_2_3_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_RESERVE_2_0_nc_RESERVE_2_3_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_RESERVE_2_0_nc_RESERVE_2_3_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register VI_RESERVE_3_0  // reserved register for emergency ...
+#define VI_RESERVE_3_0                  _MK_ADDR_CONST(0x97)
+#define VI_RESERVE_3_0_WORD_COUNT                       0x1
+#define VI_RESERVE_3_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define VI_RESERVE_3_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define VI_RESERVE_3_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define VI_RESERVE_3_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_RESERVE_3_0_READ_MASK                        _MK_MASK_CONST(0xffff)
+#define VI_RESERVE_3_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
+#define VI_RESERVE_3_0_nc_RESERVE_3_0_SHIFT                     _MK_SHIFT_CONST(0)
+#define VI_RESERVE_3_0_nc_RESERVE_3_0_FIELD                     (_MK_MASK_CONST(0xf) << VI_RESERVE_3_0_nc_RESERVE_3_0_SHIFT)
+#define VI_RESERVE_3_0_nc_RESERVE_3_0_RANGE                     3:0
+#define VI_RESERVE_3_0_nc_RESERVE_3_0_WOFFSET                   0x0
+#define VI_RESERVE_3_0_nc_RESERVE_3_0_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_RESERVE_3_0_nc_RESERVE_3_0_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_RESERVE_3_0_nc_RESERVE_3_0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_RESERVE_3_0_nc_RESERVE_3_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define VI_RESERVE_3_0_nc_RESERVE_3_1_SHIFT                     _MK_SHIFT_CONST(4)
+#define VI_RESERVE_3_0_nc_RESERVE_3_1_FIELD                     (_MK_MASK_CONST(0xf) << VI_RESERVE_3_0_nc_RESERVE_3_1_SHIFT)
+#define VI_RESERVE_3_0_nc_RESERVE_3_1_RANGE                     7:4
+#define VI_RESERVE_3_0_nc_RESERVE_3_1_WOFFSET                   0x0
+#define VI_RESERVE_3_0_nc_RESERVE_3_1_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_RESERVE_3_0_nc_RESERVE_3_1_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_RESERVE_3_0_nc_RESERVE_3_1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_RESERVE_3_0_nc_RESERVE_3_1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define VI_RESERVE_3_0_nc_RESERVE_3_2_SHIFT                     _MK_SHIFT_CONST(8)
+#define VI_RESERVE_3_0_nc_RESERVE_3_2_FIELD                     (_MK_MASK_CONST(0xf) << VI_RESERVE_3_0_nc_RESERVE_3_2_SHIFT)
+#define VI_RESERVE_3_0_nc_RESERVE_3_2_RANGE                     11:8
+#define VI_RESERVE_3_0_nc_RESERVE_3_2_WOFFSET                   0x0
+#define VI_RESERVE_3_0_nc_RESERVE_3_2_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_RESERVE_3_0_nc_RESERVE_3_2_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_RESERVE_3_0_nc_RESERVE_3_2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_RESERVE_3_0_nc_RESERVE_3_2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define VI_RESERVE_3_0_nc_RESERVE_3_3_SHIFT                     _MK_SHIFT_CONST(12)
+#define VI_RESERVE_3_0_nc_RESERVE_3_3_FIELD                     (_MK_MASK_CONST(0xf) << VI_RESERVE_3_0_nc_RESERVE_3_3_SHIFT)
+#define VI_RESERVE_3_0_nc_RESERVE_3_3_RANGE                     15:12
+#define VI_RESERVE_3_0_nc_RESERVE_3_3_WOFFSET                   0x0
+#define VI_RESERVE_3_0_nc_RESERVE_3_3_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_RESERVE_3_0_nc_RESERVE_3_3_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_RESERVE_3_0_nc_RESERVE_3_3_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_RESERVE_3_0_nc_RESERVE_3_3_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register VI_RESERVE_4_0  // reserved register for emergency ...
+#define VI_RESERVE_4_0                  _MK_ADDR_CONST(0x98)
+#define VI_RESERVE_4_0_WORD_COUNT                       0x1
+#define VI_RESERVE_4_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define VI_RESERVE_4_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define VI_RESERVE_4_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define VI_RESERVE_4_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_RESERVE_4_0_READ_MASK                        _MK_MASK_CONST(0xffff)
+#define VI_RESERVE_4_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
+#define VI_RESERVE_4_0_nc_RESERVE_4_0_SHIFT                     _MK_SHIFT_CONST(0)
+#define VI_RESERVE_4_0_nc_RESERVE_4_0_FIELD                     (_MK_MASK_CONST(0xf) << VI_RESERVE_4_0_nc_RESERVE_4_0_SHIFT)
+#define VI_RESERVE_4_0_nc_RESERVE_4_0_RANGE                     3:0
+#define VI_RESERVE_4_0_nc_RESERVE_4_0_WOFFSET                   0x0
+#define VI_RESERVE_4_0_nc_RESERVE_4_0_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_RESERVE_4_0_nc_RESERVE_4_0_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_RESERVE_4_0_nc_RESERVE_4_0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_RESERVE_4_0_nc_RESERVE_4_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define VI_RESERVE_4_0_nc_RESERVE_4_1_SHIFT                     _MK_SHIFT_CONST(4)
+#define VI_RESERVE_4_0_nc_RESERVE_4_1_FIELD                     (_MK_MASK_CONST(0xf) << VI_RESERVE_4_0_nc_RESERVE_4_1_SHIFT)
+#define VI_RESERVE_4_0_nc_RESERVE_4_1_RANGE                     7:4
+#define VI_RESERVE_4_0_nc_RESERVE_4_1_WOFFSET                   0x0
+#define VI_RESERVE_4_0_nc_RESERVE_4_1_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_RESERVE_4_0_nc_RESERVE_4_1_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_RESERVE_4_0_nc_RESERVE_4_1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_RESERVE_4_0_nc_RESERVE_4_1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define VI_RESERVE_4_0_nc_RESERVE_4_2_SHIFT                     _MK_SHIFT_CONST(8)
+#define VI_RESERVE_4_0_nc_RESERVE_4_2_FIELD                     (_MK_MASK_CONST(0xf) << VI_RESERVE_4_0_nc_RESERVE_4_2_SHIFT)
+#define VI_RESERVE_4_0_nc_RESERVE_4_2_RANGE                     11:8
+#define VI_RESERVE_4_0_nc_RESERVE_4_2_WOFFSET                   0x0
+#define VI_RESERVE_4_0_nc_RESERVE_4_2_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_RESERVE_4_0_nc_RESERVE_4_2_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_RESERVE_4_0_nc_RESERVE_4_2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_RESERVE_4_0_nc_RESERVE_4_2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define VI_RESERVE_4_0_nc_RESERVE_4_3_SHIFT                     _MK_SHIFT_CONST(12)
+#define VI_RESERVE_4_0_nc_RESERVE_4_3_FIELD                     (_MK_MASK_CONST(0xf) << VI_RESERVE_4_0_nc_RESERVE_4_3_SHIFT)
+#define VI_RESERVE_4_0_nc_RESERVE_4_3_RANGE                     15:12
+#define VI_RESERVE_4_0_nc_RESERVE_4_3_WOFFSET                   0x0
+#define VI_RESERVE_4_0_nc_RESERVE_4_3_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_RESERVE_4_0_nc_RESERVE_4_3_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_RESERVE_4_0_nc_RESERVE_4_3_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_RESERVE_4_0_nc_RESERVE_4_3_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register CSI_VI_INPUT_STREAM_CONTROL_0  // VI Input Stream Control
+#define CSI_VI_INPUT_STREAM_CONTROL_0                   _MK_ADDR_CONST(0x200)
+#define CSI_VI_INPUT_STREAM_CONTROL_0_WORD_COUNT                        0x1
+#define CSI_VI_INPUT_STREAM_CONTROL_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define CSI_VI_INPUT_STREAM_CONTROL_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define CSI_VI_INPUT_STREAM_CONTROL_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define CSI_VI_INPUT_STREAM_CONTROL_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_VI_INPUT_STREAM_CONTROL_0_READ_MASK                         _MK_MASK_CONST(0x80)
+#define CSI_VI_INPUT_STREAM_CONTROL_0_WRITE_MASK                        _MK_MASK_CONST(0x80)
+// VIP Start Frame Generation Don't use vi2csi_vip_vsync to generate start frame
+// (SF), or end frame (EF) markers in the pixel parser
+// output stream.
+#define CSI_VI_INPUT_STREAM_CONTROL_0_VIP_SF_GEN_SHIFT                  _MK_SHIFT_CONST(7)
+#define CSI_VI_INPUT_STREAM_CONTROL_0_VIP_SF_GEN_FIELD                  (_MK_MASK_CONST(0x1) << CSI_VI_INPUT_STREAM_CONTROL_0_VIP_SF_GEN_SHIFT)
+#define CSI_VI_INPUT_STREAM_CONTROL_0_VIP_SF_GEN_RANGE                  7:7
+#define CSI_VI_INPUT_STREAM_CONTROL_0_VIP_SF_GEN_WOFFSET                        0x0
+#define CSI_VI_INPUT_STREAM_CONTROL_0_VIP_SF_GEN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_VI_INPUT_STREAM_CONTROL_0_VIP_SF_GEN_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_VI_INPUT_STREAM_CONTROL_0_VIP_SF_GEN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_VI_INPUT_STREAM_CONTROL_0_VIP_SF_GEN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CSI_VI_INPUT_STREAM_CONTROL_0_VIP_SF_GEN_VSYNC_SF                       _MK_ENUM_CONST(0)    // // Pulses on vi2csi_vip_vsync will be used to
+// generate start frame (SF) and end frame (EF) markers
+// in the pixel parser output stream.
+// In AP15, only payload_only mode is supported in
+// the VIP input stream path, and this fields may 
+// always be programmed to VSYNC_SF.
+
+#define CSI_VI_INPUT_STREAM_CONTROL_0_VIP_SF_GEN_NO_VSYNC_SF                    _MK_ENUM_CONST(1)
+
+
+// Reserved address 513 [0x201] 
+
+// Register CSI_HOST_INPUT_STREAM_CONTROL_0  // Host Input Stream Control
+#define CSI_HOST_INPUT_STREAM_CONTROL_0                 _MK_ADDR_CONST(0x202)
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_WORD_COUNT                      0x1
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_RESET_MASK                      _MK_MASK_CONST(0x0)
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_READ_MASK                       _MK_MASK_CONST(0x1fff018f)
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_WRITE_MASK                      _MK_MASK_CONST(0x1fff008f)
+// Host Data Format Data written to Y_FIFO_WRITE port should be in CSI
+// packet format. To indicate end of packet a 1 should
+// be written to HOST_END_OF_PACKET. A 1 should also be
+// written to HOST_END_OF_PACKET before writing the first
+// word of packet data to Y_FIFO_WRITE.
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_HOST_DATA_FORMAT_SHIFT                  _MK_SHIFT_CONST(0)
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_HOST_DATA_FORMAT_FIELD                  (_MK_MASK_CONST(0xf) << CSI_HOST_INPUT_STREAM_CONTROL_0_HOST_DATA_FORMAT_SHIFT)
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_HOST_DATA_FORMAT_RANGE                  3:0
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_HOST_DATA_FORMAT_WOFFSET                        0x0
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_HOST_DATA_FORMAT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_HOST_DATA_FORMAT_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_HOST_DATA_FORMAT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_HOST_DATA_FORMAT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_HOST_DATA_FORMAT_PAYLOAD_ONLY                   _MK_ENUM_CONST(0)    // // Data written to Y_FIFO_WRITE port should be
+// CSI line payload data only (no header, no footer,
+// and  no short packets). A value of 1 should not
+// be written to HOST_END_OF_PACKET (end of packet
+// pulse only gets generated when a 1 is written to
+// this bit). 
+// First line will be indicated when one of the pixel
+// parsers is first enabled with its 
+// CSI_PPA/B_STREAM_SOURCE set to "HOST".
+// The values in the following PIXEL_STREAM_A/B_CONTROL0 
+// fields, for the pixel parser that is receiving host
+// data, will be ignored;
+// CSI_PPA/B_PACKET_HEADER overridden with "NOT_SENT",
+// CSI_PPA/B_DATA_IDENTIFIER overridden with "DISABLED",
+// CSI_PPA/B_WORD_COUNT_SELECT overridden with "REGISTER".
+// CSI_PPA/B_CRC_CHECK overridden with "DISABLE",
+// CSI_PPA/B_VIRTUAL_CHANNEL_ID,
+// CSI_PPA/B_EMBEDDED_DATA_OPTIONS, and
+// CSI_PPA/B_HEADER_EC_ENABLE.
+// CSI_PPA/B_DATA_TYPE should be programmed with the 
+// 6 bit data type that is to be used to interpret the
+// stream. CSI_PPA/B_WORD_COUNT should be programmed with
+// the number of bytes per line.
+
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_HOST_DATA_FORMAT_PACKETS                        _MK_ENUM_CONST(1)
+
+// Host Start Frame Generation Don't use CSI Host Line counter to generate start, or
+// End, of Frame control outputs. This setting should only
+// be used if HOST_DATA_FORMAT is set to PACKETS, and the
+// Host data stream has frame sync packets.
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_HOST_SF_GEN_SHIFT                       _MK_SHIFT_CONST(7)
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_HOST_SF_GEN_FIELD                       (_MK_MASK_CONST(0x1) << CSI_HOST_INPUT_STREAM_CONTROL_0_HOST_SF_GEN_SHIFT)
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_HOST_SF_GEN_RANGE                       7:7
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_HOST_SF_GEN_WOFFSET                     0x0
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_HOST_SF_GEN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_HOST_SF_GEN_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_HOST_SF_GEN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_HOST_SF_GEN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_HOST_SF_GEN_LINE_COUNTER                        _MK_ENUM_CONST(0)    // // CSI Host Line counter will be used to generate Frame
+// start and end control. To signal the start of the first
+// frame the pixel parser will send a SF control, and
+// signal start of frame mark, when it is first enabled
+// with Host as its source. This setting should be used 
+// when HOST_DATA_FORMAT is set to PAYLOAD_ONLY.
+
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_HOST_SF_GEN_SHORT_PACKETS                       _MK_ENUM_CONST(1)
+
+// Writing this bit with a 1 indicates End of Packet,
+// when CSI Host data is being received in Packet Format.
+// In Packet Format vi2csi_host_hsync is not used to 
+// indicate beginning of packet.
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_HOST_END_OF_PACKET_SHIFT                        _MK_SHIFT_CONST(8)
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_HOST_END_OF_PACKET_FIELD                        (_MK_MASK_CONST(0x1) << CSI_HOST_INPUT_STREAM_CONTROL_0_HOST_END_OF_PACKET_SHIFT)
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_HOST_END_OF_PACKET_RANGE                        8:8
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_HOST_END_OF_PACKET_WOFFSET                      0x0
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_HOST_END_OF_PACKET_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_HOST_END_OF_PACKET_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_HOST_END_OF_PACKET_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_HOST_END_OF_PACKET_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Host Frame Height
+// Specifies the height of the host frame when the host
+// is supplying CSI format payload only data to one of 
+// the CSI pixel parsers.
+// Programmed Value = number of lines - 1
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_HOST_FRAME_HEIGHT_SHIFT                 _MK_SHIFT_CONST(16)
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_HOST_FRAME_HEIGHT_FIELD                 (_MK_MASK_CONST(0x1fff) << CSI_HOST_INPUT_STREAM_CONTROL_0_HOST_FRAME_HEIGHT_SHIFT)
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_HOST_FRAME_HEIGHT_RANGE                 28:16
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_HOST_FRAME_HEIGHT_WOFFSET                       0x0
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_HOST_FRAME_HEIGHT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_HOST_FRAME_HEIGHT_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_HOST_FRAME_HEIGHT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_HOST_FRAME_HEIGHT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Reserved address 515 [0x203] 
+
+// Register CSI_INPUT_STREAM_A_CONTROL_0  // CSI Input Stream A Control
+#define CSI_INPUT_STREAM_A_CONTROL_0                    _MK_ADDR_CONST(0x204)
+#define CSI_INPUT_STREAM_A_CONTROL_0_WORD_COUNT                         0x1
+#define CSI_INPUT_STREAM_A_CONTROL_0_RESET_VAL                  _MK_MASK_CONST(0x7f0001)
+#define CSI_INPUT_STREAM_A_CONTROL_0_RESET_MASK                         _MK_MASK_CONST(0xff0013)
+#define CSI_INPUT_STREAM_A_CONTROL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define CSI_INPUT_STREAM_A_CONTROL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CSI_INPUT_STREAM_A_CONTROL_0_READ_MASK                  _MK_MASK_CONST(0xff0013)
+#define CSI_INPUT_STREAM_A_CONTROL_0_WRITE_MASK                         _MK_MASK_CONST(0xff0013)
+// CSI-A Data Lane
+//   0= 1 data lane
+//   1= 2 data lanes
+//   2= 3 data lanes (not supported on SC17 & SC25)
+//   3= 4 data lanes (not supported on SC17 & SC25)
+#define CSI_INPUT_STREAM_A_CONTROL_0_CSI_A_DATA_LANE_SHIFT                      _MK_SHIFT_CONST(0)
+#define CSI_INPUT_STREAM_A_CONTROL_0_CSI_A_DATA_LANE_FIELD                      (_MK_MASK_CONST(0x3) << CSI_INPUT_STREAM_A_CONTROL_0_CSI_A_DATA_LANE_SHIFT)
+#define CSI_INPUT_STREAM_A_CONTROL_0_CSI_A_DATA_LANE_RANGE                      1:0
+#define CSI_INPUT_STREAM_A_CONTROL_0_CSI_A_DATA_LANE_WOFFSET                    0x0
+#define CSI_INPUT_STREAM_A_CONTROL_0_CSI_A_DATA_LANE_DEFAULT                    _MK_MASK_CONST(0x1)
+#define CSI_INPUT_STREAM_A_CONTROL_0_CSI_A_DATA_LANE_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define CSI_INPUT_STREAM_A_CONTROL_0_CSI_A_DATA_LANE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_INPUT_STREAM_A_CONTROL_0_CSI_A_DATA_LANE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Enables skip packet threshold feature. Skip packet feature is enabled.
+#define CSI_INPUT_STREAM_A_CONTROL_0_CSI_A_SKIP_PACKET_THRESHOLD_ENABLE_SHIFT                   _MK_SHIFT_CONST(4)
+#define CSI_INPUT_STREAM_A_CONTROL_0_CSI_A_SKIP_PACKET_THRESHOLD_ENABLE_FIELD                   (_MK_MASK_CONST(0x1) << CSI_INPUT_STREAM_A_CONTROL_0_CSI_A_SKIP_PACKET_THRESHOLD_ENABLE_SHIFT)
+#define CSI_INPUT_STREAM_A_CONTROL_0_CSI_A_SKIP_PACKET_THRESHOLD_ENABLE_RANGE                   4:4
+#define CSI_INPUT_STREAM_A_CONTROL_0_CSI_A_SKIP_PACKET_THRESHOLD_ENABLE_WOFFSET                 0x0
+#define CSI_INPUT_STREAM_A_CONTROL_0_CSI_A_SKIP_PACKET_THRESHOLD_ENABLE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_INPUT_STREAM_A_CONTROL_0_CSI_A_SKIP_PACKET_THRESHOLD_ENABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CSI_INPUT_STREAM_A_CONTROL_0_CSI_A_SKIP_PACKET_THRESHOLD_ENABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_INPUT_STREAM_A_CONTROL_0_CSI_A_SKIP_PACKET_THRESHOLD_ENABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CSI_INPUT_STREAM_A_CONTROL_0_CSI_A_SKIP_PACKET_THRESHOLD_ENABLE_DISABLE                 _MK_ENUM_CONST(0)    // // Skip packet feature is disabled.     
+
+#define CSI_INPUT_STREAM_A_CONTROL_0_CSI_A_SKIP_PACKET_THRESHOLD_ENABLE_ENABLE                  _MK_ENUM_CONST(1)
+
+// CSI-A Skip Packet Threshold
+//  This value is compared against the internal
+//  FIFO that buffer the input streams. A packet
+//  will be skipped (discarded) if the pixel
+//  stream processor is busy (probably due to
+//  padding process of a short line) and the
+//  number of entries in the internal FIFO
+//  exceeds this threshold value. Note that
+//  each entry in the internal FIFO buffer is
+//  four bytes.
+//  To turn off this feature, set the value
+//  to its maximum value (all ones).
+#define CSI_INPUT_STREAM_A_CONTROL_0_CSI_A_SKIP_PACKET_THRESHOLD_SHIFT                  _MK_SHIFT_CONST(16)
+#define CSI_INPUT_STREAM_A_CONTROL_0_CSI_A_SKIP_PACKET_THRESHOLD_FIELD                  (_MK_MASK_CONST(0xff) << CSI_INPUT_STREAM_A_CONTROL_0_CSI_A_SKIP_PACKET_THRESHOLD_SHIFT)
+#define CSI_INPUT_STREAM_A_CONTROL_0_CSI_A_SKIP_PACKET_THRESHOLD_RANGE                  23:16
+#define CSI_INPUT_STREAM_A_CONTROL_0_CSI_A_SKIP_PACKET_THRESHOLD_WOFFSET                        0x0
+#define CSI_INPUT_STREAM_A_CONTROL_0_CSI_A_SKIP_PACKET_THRESHOLD_DEFAULT                        _MK_MASK_CONST(0x7f)
+#define CSI_INPUT_STREAM_A_CONTROL_0_CSI_A_SKIP_PACKET_THRESHOLD_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
+#define CSI_INPUT_STREAM_A_CONTROL_0_CSI_A_SKIP_PACKET_THRESHOLD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_INPUT_STREAM_A_CONTROL_0_CSI_A_SKIP_PACKET_THRESHOLD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Reserved address 517 [0x205] 
+
+// Register CSI_PIXEL_STREAM_A_CONTROL0_0  // CSI Pixel Stream A Control 0
+#define CSI_PIXEL_STREAM_A_CONTROL0_0                   _MK_ADDR_CONST(0x206)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_WORD_COUNT                        0x1
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_RESET_MASK                        _MK_MASK_CONST(0x7)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_READ_MASK                         _MK_MASK_CONST(0x3b3ffff7)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_WRITE_MASK                        _MK_MASK_CONST(0x3b3ffff7)
+// CSI Pixel Parser A Stream Source   Host
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_STREAM_SOURCE_SHIFT                       _MK_SHIFT_CONST(0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_STREAM_SOURCE_FIELD                       (_MK_MASK_CONST(0x7) << CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_STREAM_SOURCE_SHIFT)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_STREAM_SOURCE_RANGE                       2:0
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_STREAM_SOURCE_WOFFSET                     0x0
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_STREAM_SOURCE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_STREAM_SOURCE_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_STREAM_SOURCE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_STREAM_SOURCE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_STREAM_SOURCE_CSI_A                       _MK_ENUM_CONST(0)    // //   CSI Interface A
+
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_STREAM_SOURCE_CSI_B                       _MK_ENUM_CONST(1)    // //   CSI Interface B
+
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_STREAM_SOURCE_VI_PORT                     _MK_ENUM_CONST(6)    // //   VI port
+
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_STREAM_SOURCE_HOST                        _MK_ENUM_CONST(7)
+
+// CSI Pixel Parser A Packet Header processing
+//  This specifies whether packet header is
+//  sent in the beginning of packet or not.      Packet header is sent.
+//      This setting should be used if the
+//      stream source is CSI Interface A or B.
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_PACKET_HEADER_SHIFT                       _MK_SHIFT_CONST(4)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_PACKET_HEADER_FIELD                       (_MK_MASK_CONST(0x1) << CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_PACKET_HEADER_SHIFT)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_PACKET_HEADER_RANGE                       4:4
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_PACKET_HEADER_WOFFSET                     0x0
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_PACKET_HEADER_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_PACKET_HEADER_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_PACKET_HEADER_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_PACKET_HEADER_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_PACKET_HEADER_NOT_SENT                    _MK_ENUM_CONST(0)    // //      Packet header is not sent.
+//      This setting should not be used if the
+//      stream source is CSI Interface A or B.
+//      Unless CSI-A, or CSI-B, is operating in a
+//      stream capture debug mode.
+//      In this case, CSI_PPA_DATA_TYPE specifies
+//      the stream data format and the number
+//      of bytes per line/packet is
+//      specified by CSI_PPA_WORD_COUNT.
+//      This implies that a packet footer
+//      is also not sent.  In this case, no 
+//      packet footer CRC check should be performed.
+
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_PACKET_HEADER_SENT                        _MK_ENUM_CONST(1)
+
+// CSI Pixel Parser A Data Identifier (DI) byte processing
+//  This parameter is effective only if packet
+//  header is sent as part of the stream.      Enabled  - Data Identifier byte in
+//      packet header should be compared against
+//      the CSI_PPA_DATA_TYPE and the
+//      CSI_PPA_VIRTUAL_CHANNEL_ID.
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_IDENTIFIER_SHIFT                     _MK_SHIFT_CONST(5)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_IDENTIFIER_FIELD                     (_MK_MASK_CONST(0x1) << CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_IDENTIFIER_SHIFT)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_IDENTIFIER_RANGE                     5:5
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_IDENTIFIER_WOFFSET                   0x0
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_IDENTIFIER_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_IDENTIFIER_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_IDENTIFIER_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_IDENTIFIER_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_IDENTIFIER_DISABLED                  _MK_ENUM_CONST(0)    // //      Disabled - Data Identifier byte in
+//      packet header should be ignored
+//      (not checked against CSI_PPA_DATA_TYPE
+//      and against CSI_PPA_VIRTUAL_CHANNEL_ID).
+//      In this case, CSI_PPA_DATA_TYPE specifies
+//      the stream data format.
+
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_IDENTIFIER_ENABLED                   _MK_ENUM_CONST(1)
+
+// CSI Pixel Parser A Word Count Select
+//  This parameter is effective only if packet
+//  header is sent as part of the stream.      The number of bytes per line is to be
+//      extracted from Word Count field in the
+//      packet header. Note that if the serial
+//      link is not error free, programming this
+//      bit to HEADER may be dangerous because 
+//      the word count information in the header 
+//      may be corrupted. 
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_WORD_COUNT_SELECT_SHIFT                   _MK_SHIFT_CONST(6)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_WORD_COUNT_SELECT_FIELD                   (_MK_MASK_CONST(0x1) << CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_WORD_COUNT_SELECT_SHIFT)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_WORD_COUNT_SELECT_RANGE                   6:6
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_WORD_COUNT_SELECT_WOFFSET                 0x0
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_WORD_COUNT_SELECT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_WORD_COUNT_SELECT_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_WORD_COUNT_SELECT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_WORD_COUNT_SELECT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_WORD_COUNT_SELECT_REGISTER                        _MK_ENUM_CONST(0)    // //      Word Count in packet header is ignored
+//      and the number of bytes per line/packet
+//      is specified by CSI_PPA_WORD_COUNT. Payload
+//      CRC check will not be valid if the word
+//      count in CSI_PPA_WORD_COUNT is different 
+//      than the count in the packet header.
+//      It is recommended to always program
+//      this bit to REGISTER and always program
+//      CSI_PPA_WORD_COUNT.
+
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_WORD_COUNT_SELECT_HEADER                  _MK_ENUM_CONST(1)
+
+// CSI Pixel Parser A Data CRC Check
+//  This parameter specifies whether the last
+//  2 bytes of packet should be treated as
+//  CRC checksum and used to perform CRC check
+//  on the payload data. Note that in case there
+//  are 2 bytes of data CRC at the end of the
+//  packet, the packet word count does not
+//  include the CRC bytes.      Data CRC Check is enabled.
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_CRC_CHECK_SHIFT                   _MK_SHIFT_CONST(7)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_CRC_CHECK_FIELD                   (_MK_MASK_CONST(0x1) << CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_CRC_CHECK_SHIFT)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_CRC_CHECK_RANGE                   7:7
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_CRC_CHECK_WOFFSET                 0x0
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_CRC_CHECK_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_CRC_CHECK_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_CRC_CHECK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_CRC_CHECK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_CRC_CHECK_DISABLE                 _MK_ENUM_CONST(0)    // //      Data CRC Check is disabled regardless
+//      of whether there are CRC checksum at
+//      the end of the packet.
+
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_CRC_CHECK_ENABLE                  _MK_ENUM_CONST(1)
+
+// CSI Pixel Parser A Data Type  This is CSI compatible data type as defined
+//  in CSI specification. If the source stream
+//  contains packet headers this value can be compared
+//  to the CSI Data Type value in the 6 LSB of the
+//  CSI Data Identifier (DI) byte. If the source stream
+//  doesn't contain packet headers, or CSI_PPA_DATA_IDENTIFIER
+//  is DISABLED, this value will be used to determine how
+//  the stream will be converted to pixels.
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_TYPE_SHIFT                   _MK_SHIFT_CONST(8)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_TYPE_FIELD                   (_MK_MASK_CONST(0x3f) << CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_TYPE_SHIFT)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_TYPE_RANGE                   13:8
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_TYPE_WOFFSET                 0x0
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_TYPE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_TYPE_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_TYPE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_TYPE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_TYPE_YUV420_8                        _MK_ENUM_CONST(24)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_TYPE_YUV420_10                       _MK_ENUM_CONST(25)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_TYPE_LEG_YUV420_8                    _MK_ENUM_CONST(26)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_TYPE_YUV420CSPS_8                    _MK_ENUM_CONST(28)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_TYPE_YUV420CSPS_10                   _MK_ENUM_CONST(29)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_TYPE_YUV422_8                        _MK_ENUM_CONST(30)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_TYPE_YUV422_10                       _MK_ENUM_CONST(31)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_TYPE_RGB444                  _MK_ENUM_CONST(32)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_TYPE_RGB555                  _MK_ENUM_CONST(33)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_TYPE_RGB565                  _MK_ENUM_CONST(34)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_TYPE_RGB666                  _MK_ENUM_CONST(35)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_TYPE_RGB888                  _MK_ENUM_CONST(36)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_TYPE_RAW6                    _MK_ENUM_CONST(40)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_TYPE_RAW7                    _MK_ENUM_CONST(41)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_TYPE_RAW8                    _MK_ENUM_CONST(42)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_TYPE_RAW10                   _MK_ENUM_CONST(43)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_TYPE_RAW12                   _MK_ENUM_CONST(44)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_TYPE_RAW14                   _MK_ENUM_CONST(45)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_TYPE_ARB_DT1                 _MK_ENUM_CONST(48)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_TYPE_ARB_DT2                 _MK_ENUM_CONST(49)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_TYPE_ARB_DT3                 _MK_ENUM_CONST(50)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_TYPE_ARB_DT4                 _MK_ENUM_CONST(51)
+
+// CSI Pixel Parser A Virtual Channel Identifier  
+//  This is CSI compatible virtual channel
+//  identifier as defined in CSI specification.
+//  If the source stream contains packet headers
+//  and CSI_PPA_DATA_IDENTIFIER is ENABLED this
+//  value will be compared to the CSI Virtual
+//  Channel Identifier value in the 2 MSB of the
+//  CSI Data Identifier (DI) byte. This value will
+//  be ignored if the source stream doesn't contain
+//  packet headers, or CSI_PPA_DATA_IDENTIFIER is 
+//  DISABLED, then this value will be ignored.
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_VIRTUAL_CHANNEL_ID_SHIFT                  _MK_SHIFT_CONST(14)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_VIRTUAL_CHANNEL_ID_FIELD                  (_MK_MASK_CONST(0x3) << CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_VIRTUAL_CHANNEL_ID_SHIFT)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_VIRTUAL_CHANNEL_ID_RANGE                  15:14
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_VIRTUAL_CHANNEL_ID_WOFFSET                        0x0
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_VIRTUAL_CHANNEL_ID_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_VIRTUAL_CHANNEL_ID_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_VIRTUAL_CHANNEL_ID_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_VIRTUAL_CHANNEL_ID_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_VIRTUAL_CHANNEL_ID_ONE                    _MK_ENUM_CONST(0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_VIRTUAL_CHANNEL_ID_TWO                    _MK_ENUM_CONST(1)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_VIRTUAL_CHANNEL_ID_THREE                  _MK_ENUM_CONST(2)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_VIRTUAL_CHANNEL_ID_FOUR                   _MK_ENUM_CONST(3)
+
+// CSI Pixel Parser A Output Format Options
+//  This parameter specifies options for output data 
+//  format.       Output for storing RAW data to memory through
+//       ISP. Undefined LS color bits for RGB_666, 
+//       RGB_565, RGB_555, and RGB_444, will be zeroed.
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_OUTPUT_FORMAT_OPTIONS_SHIFT                       _MK_SHIFT_CONST(16)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_OUTPUT_FORMAT_OPTIONS_FIELD                       (_MK_MASK_CONST(0xf) << CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_OUTPUT_FORMAT_OPTIONS_SHIFT)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_OUTPUT_FORMAT_OPTIONS_RANGE                       19:16
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_OUTPUT_FORMAT_OPTIONS_WOFFSET                     0x0
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_OUTPUT_FORMAT_OPTIONS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_OUTPUT_FORMAT_OPTIONS_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_OUTPUT_FORMAT_OPTIONS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_OUTPUT_FORMAT_OPTIONS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_OUTPUT_FORMAT_OPTIONS_ARBITRARY                   _MK_ENUM_CONST(0)    // //       Output as 8-bit arbitrary data stream
+//       This may be used for compressed JPEG stream
+
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_OUTPUT_FORMAT_OPTIONS_PIXEL                       _MK_ENUM_CONST(1)    // //       Output the normal 1 pixel/clock. Undefined 
+//       LS color bits for RGB_666, RGB_565, RGB_555,
+//       and RGB_444, will be zeroed.
+
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_OUTPUT_FORMAT_OPTIONS_PIXEL_REP                   _MK_ENUM_CONST(2)    // //       Same as PIXEL except MS color bits, for RGB_666, 
+//       RGB_565, RGB_555, and RGB_444, will be 
+//       replicated to their undefined LS bits.
+
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_OUTPUT_FORMAT_OPTIONS_STORE                       _MK_ENUM_CONST(3)
+
+// CSI Pixel Parser A Embedded Data Options 
+//  This specifies how to deal with embedded
+//  data within the specified input stream
+//  assuming that the CSI_PPA_DATA_TYPE is not
+//  embedded data and assuming that embedded
+//  data is not already processed by other
+//  CSI pixel stream processor.       output embedded data as 8-bpp arbitrary
+//       data stream.
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_EMBEDDED_DATA_OPTIONS_SHIFT                       _MK_SHIFT_CONST(20)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_EMBEDDED_DATA_OPTIONS_FIELD                       (_MK_MASK_CONST(0x3) << CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_EMBEDDED_DATA_OPTIONS_SHIFT)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_EMBEDDED_DATA_OPTIONS_RANGE                       21:20
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_EMBEDDED_DATA_OPTIONS_WOFFSET                     0x0
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_EMBEDDED_DATA_OPTIONS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_EMBEDDED_DATA_OPTIONS_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_EMBEDDED_DATA_OPTIONS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_EMBEDDED_DATA_OPTIONS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_EMBEDDED_DATA_OPTIONS_DISCARD                     _MK_ENUM_CONST(0)    // //       discard (throw away) embedded data
+
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_EMBEDDED_DATA_OPTIONS_EMBEDDED                    _MK_ENUM_CONST(1)
+
+// CSI Pixel Parser A Pad Short Line
+//  This specifies how to deal with shorter than
+//  expected line (the number of bytes received
+//  is less than the specified word count)       short line is not padded (will output
+//       less pixels than expected).
+//       This option is not recommended and may
+//       cause other modules that receives CSI
+//       output stream to hang up.
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_PAD_SHORT_LINE_SHIFT                      _MK_SHIFT_CONST(24)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_PAD_SHORT_LINE_FIELD                      (_MK_MASK_CONST(0x3) << CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_PAD_SHORT_LINE_SHIFT)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_PAD_SHORT_LINE_RANGE                      25:24
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_PAD_SHORT_LINE_WOFFSET                    0x0
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_PAD_SHORT_LINE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_PAD_SHORT_LINE_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_PAD_SHORT_LINE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_PAD_SHORT_LINE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_PAD_SHORT_LINE_PAD0S                      _MK_ENUM_CONST(0)    // //       short line is padded by pixel of zeros
+//       such that the expected number of output
+//       pixels is correct. Due to the time
+//       required to do the padding, subsequent
+//       line packet maybe discarded and
+//       therefore may cause a short frame
+//       (total number of lines per frame is
+//       less than expected).
+
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_PAD_SHORT_LINE_PAD1S                      _MK_ENUM_CONST(1)    // //       short line is padded by pixel of ones
+//       such that the expected number of output
+//       pixels is correct. Due to the time
+//       required to do the padding, subsequent
+//       line packet maybe discarded and
+//       therefore may cause a short frame
+//       (total number of lines per frame is
+//       less than expected).
+
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_PAD_SHORT_LINE_NOPAD                      _MK_ENUM_CONST(2)
+
+// CSI Pixel Parser A Packet Header Error Correction Enable
+//  This parameter specifies whether single bit
+//  errors in the packet header will be
+//  automatically corrected, or not.    Single bit errors in the header will not
+//    be corrected. Header ECC check will still
+//    set header ECC status bits and the packet
+//    will be processed by Pixel Parser A. DISABLE
+//    should not be used when processing interleaved
+//    streams (Same stream going to both PPA and PPB).
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_HEADER_EC_ENABLE_SHIFT                    _MK_SHIFT_CONST(27)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_HEADER_EC_ENABLE_FIELD                    (_MK_MASK_CONST(0x1) << CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_HEADER_EC_ENABLE_SHIFT)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_HEADER_EC_ENABLE_RANGE                    27:27
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_HEADER_EC_ENABLE_WOFFSET                  0x0
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_HEADER_EC_ENABLE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_HEADER_EC_ENABLE_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_HEADER_EC_ENABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_HEADER_EC_ENABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_HEADER_EC_ENABLE_ENABLE                   _MK_ENUM_CONST(0)    // //    Single bit errors in the header will be
+//    automatically corrected.
+
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_HEADER_EC_ENABLE_DISABLE                  _MK_ENUM_CONST(1)
+
+// CSI Pixel Parser A Pad Frame
+//  This specifies how to deal with frames that are
+//  shorter (fewer lines) that expected. Short frames
+//  are usually caused by line packets being dropped
+//  because of packet errors. Expected frame height is
+//  specified in PPA_EXP_FRAME_HEIGHT. To do padding the
+//  value in CSI_PPA_WORD_COUNT needs to be set to the
+//  number of input bytes in each line's payload.  Short frames will not be padded out.   
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_PAD_FRAME_SHIFT                   _MK_SHIFT_CONST(28)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_PAD_FRAME_FIELD                   (_MK_MASK_CONST(0x3) << CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_PAD_FRAME_SHIFT)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_PAD_FRAME_RANGE                   29:28
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_PAD_FRAME_WOFFSET                 0x0
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_PAD_FRAME_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_PAD_FRAME_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_PAD_FRAME_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_PAD_FRAME_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_PAD_FRAME_PAD0S                   _MK_ENUM_CONST(0)    // //  Lines of all zeros will be used to pad out frames
+//  that are shorter than expected height. 
+//  PPA_EXP_FRAME_HEIGHT must be programmed to
+//  an appropriate value if this fields is set to PAD0S.
+
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_PAD_FRAME_PAD1S                   _MK_ENUM_CONST(1)    // //  Lines of all ones will be used to pad out frames
+//  that are shorter than expected height.      
+//  PPA_EXP_FRAME_HEIGHT must be programmed to
+//  an appropriate value if this fields is set to PAD1S.
+
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_PAD_FRAME_NOPAD                   _MK_ENUM_CONST(2)
+
+
+// Register CSI_PIXEL_STREAM_A_CONTROL1_0  // CSI Pixel Stream A Control 1
+#define CSI_PIXEL_STREAM_A_CONTROL1_0                   _MK_ADDR_CONST(0x207)
+#define CSI_PIXEL_STREAM_A_CONTROL1_0_WORD_COUNT                        0x1
+#define CSI_PIXEL_STREAM_A_CONTROL1_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL1_0_RESET_MASK                        _MK_MASK_CONST(0xff)
+#define CSI_PIXEL_STREAM_A_CONTROL1_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL1_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL1_0_READ_MASK                         _MK_MASK_CONST(0xff)
+#define CSI_PIXEL_STREAM_A_CONTROL1_0_WRITE_MASK                        _MK_MASK_CONST(0xff)
+// CSI Pixel Parser A Top Field Frame
+//  This parameter specifies the frame number for 
+//  top field detection for interlaced input video
+//  stream. Top Field is indicated when each of the
+//  least significant four bits of the frame number
+//  that has a one in its mask bit matches the 
+//  corresponding bit in this parameter. In other
+//  words, Top Field is detected when the bitwise
+//  AND of  
+// ~(CSI_PPA_TOP_FIELD_FRAME ^ <frame number>) & CSI_PPA_TOP_FIELD_FRAME_MASK
+//  is one. Frame Number is taken from the WC field
+//  of the Frame Start short packet.
+#define CSI_PIXEL_STREAM_A_CONTROL1_0_CSI_PPA_TOP_FIELD_FRAME_SHIFT                     _MK_SHIFT_CONST(0)
+#define CSI_PIXEL_STREAM_A_CONTROL1_0_CSI_PPA_TOP_FIELD_FRAME_FIELD                     (_MK_MASK_CONST(0xf) << CSI_PIXEL_STREAM_A_CONTROL1_0_CSI_PPA_TOP_FIELD_FRAME_SHIFT)
+#define CSI_PIXEL_STREAM_A_CONTROL1_0_CSI_PPA_TOP_FIELD_FRAME_RANGE                     3:0
+#define CSI_PIXEL_STREAM_A_CONTROL1_0_CSI_PPA_TOP_FIELD_FRAME_WOFFSET                   0x0
+#define CSI_PIXEL_STREAM_A_CONTROL1_0_CSI_PPA_TOP_FIELD_FRAME_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL1_0_CSI_PPA_TOP_FIELD_FRAME_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define CSI_PIXEL_STREAM_A_CONTROL1_0_CSI_PPA_TOP_FIELD_FRAME_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL1_0_CSI_PPA_TOP_FIELD_FRAME_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// CSI Pixel Parser A Top Field Frame Mask
+#define CSI_PIXEL_STREAM_A_CONTROL1_0_CSI_PPA_TOP_FIELD_FRAME_MASK_SHIFT                        _MK_SHIFT_CONST(4)
+#define CSI_PIXEL_STREAM_A_CONTROL1_0_CSI_PPA_TOP_FIELD_FRAME_MASK_FIELD                        (_MK_MASK_CONST(0xf) << CSI_PIXEL_STREAM_A_CONTROL1_0_CSI_PPA_TOP_FIELD_FRAME_MASK_SHIFT)
+#define CSI_PIXEL_STREAM_A_CONTROL1_0_CSI_PPA_TOP_FIELD_FRAME_MASK_RANGE                        7:4
+#define CSI_PIXEL_STREAM_A_CONTROL1_0_CSI_PPA_TOP_FIELD_FRAME_MASK_WOFFSET                      0x0
+#define CSI_PIXEL_STREAM_A_CONTROL1_0_CSI_PPA_TOP_FIELD_FRAME_MASK_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL1_0_CSI_PPA_TOP_FIELD_FRAME_MASK_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define CSI_PIXEL_STREAM_A_CONTROL1_0_CSI_PPA_TOP_FIELD_FRAME_MASK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL1_0_CSI_PPA_TOP_FIELD_FRAME_MASK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register CSI_PIXEL_STREAM_A_WORD_COUNT_0  // CSI Pixel Stream A Word Count
+#define CSI_PIXEL_STREAM_A_WORD_COUNT_0                 _MK_ADDR_CONST(0x208)
+#define CSI_PIXEL_STREAM_A_WORD_COUNT_0_WORD_COUNT                      0x1
+#define CSI_PIXEL_STREAM_A_WORD_COUNT_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_WORD_COUNT_0_RESET_MASK                      _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_WORD_COUNT_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_WORD_COUNT_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_WORD_COUNT_0_READ_MASK                       _MK_MASK_CONST(0xffff)
+#define CSI_PIXEL_STREAM_A_WORD_COUNT_0_WRITE_MASK                      _MK_MASK_CONST(0xffff)
+// CSI Pixel Parser A Word Count
+//  This parameter specifies the number of
+//  bytes per line/packet in the case where
+//  Word Count field in packet header is not
+//  used or where packet header is not sent.
+//  This count does not includes the additional
+//  2 bytes of CRC checksum if data CRC check
+//  is enabled. 
+//  When the input stream comes from a CSI camera
+//  port, this parameter must be programmed when 
+//  CSI_PPA_PAD_SHORT_LINE is set to either PAD0S
+//  or PAD1S, no matter whether CSI_PPA_WORD_COUNT_SELECT
+//  is set to REGISTER or HEADER.
+//  When the input stream comes from the host path
+//  or from the VIP path, and the data mode is
+//  PAYLOAD_ONLY, this count must be programmed.
+// Given a line width of N pixels, the programming 
+//  value of this parameters is as follows
+//  --------------------------------------
+//  data format            value
+//  --------------------------------------
+//  YUV420_8               N bytes
+//  YUV420_10              N/4*5 bytes
+//  LEG_YUV420_8           N/2*3 bytes
+//  YUV422_8               N*2 bytes
+//  YUV422_10              N/2*5 bytes
+//  RGB888                 N*3 bytes 
+//  RGB666                 N/4*9 bytes                 
+//  RGB565                 N*2 bytes
+//  RGB555                 N*2 bytes 
+//  RGB444                 N*2 bytes 
+//  RAW6                   N/4*3 bytes
+//  RAW7                   N/8*7 bytes
+//  RAW8                   N bytes 
+//  RAW10                  N/4*5 bytes
+//  RAW12                  N/2*3 bytes
+//  RAW14                  N/4*7 bytes
+//  ---------------------------------------
+#define CSI_PIXEL_STREAM_A_WORD_COUNT_0_CSI_PPA_WORD_COUNT_SHIFT                        _MK_SHIFT_CONST(0)
+#define CSI_PIXEL_STREAM_A_WORD_COUNT_0_CSI_PPA_WORD_COUNT_FIELD                        (_MK_MASK_CONST(0xffff) << CSI_PIXEL_STREAM_A_WORD_COUNT_0_CSI_PPA_WORD_COUNT_SHIFT)
+#define CSI_PIXEL_STREAM_A_WORD_COUNT_0_CSI_PPA_WORD_COUNT_RANGE                        15:0
+#define CSI_PIXEL_STREAM_A_WORD_COUNT_0_CSI_PPA_WORD_COUNT_WOFFSET                      0x0
+#define CSI_PIXEL_STREAM_A_WORD_COUNT_0_CSI_PPA_WORD_COUNT_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_WORD_COUNT_0_CSI_PPA_WORD_COUNT_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_WORD_COUNT_0_CSI_PPA_WORD_COUNT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_WORD_COUNT_0_CSI_PPA_WORD_COUNT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register CSI_PIXEL_STREAM_A_GAP_0  // CSI Pixel Stream A Gap
+#define CSI_PIXEL_STREAM_A_GAP_0                        _MK_ADDR_CONST(0x209)
+#define CSI_PIXEL_STREAM_A_GAP_0_WORD_COUNT                     0x1
+#define CSI_PIXEL_STREAM_A_GAP_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_GAP_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
+#define CSI_PIXEL_STREAM_A_GAP_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_GAP_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_GAP_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define CSI_PIXEL_STREAM_A_GAP_0_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
+// Minium number of viclk cycles from end of 
+// previous line (Video_control = EL_DATA) to start
+// of next line (Video_control = SL).
+// This parameter is to ensure that minimum H-blank
+// time requirement of VI/ISP is satisfied.
+// This field takes effect only when the line gap 
+// of the input stream is less than the specified
+// value.
+#define CSI_PIXEL_STREAM_A_GAP_0_PPA_LINE_MIN_GAP_SHIFT                 _MK_SHIFT_CONST(0)
+#define CSI_PIXEL_STREAM_A_GAP_0_PPA_LINE_MIN_GAP_FIELD                 (_MK_MASK_CONST(0xffff) << CSI_PIXEL_STREAM_A_GAP_0_PPA_LINE_MIN_GAP_SHIFT)
+#define CSI_PIXEL_STREAM_A_GAP_0_PPA_LINE_MIN_GAP_RANGE                 15:0
+#define CSI_PIXEL_STREAM_A_GAP_0_PPA_LINE_MIN_GAP_WOFFSET                       0x0
+#define CSI_PIXEL_STREAM_A_GAP_0_PPA_LINE_MIN_GAP_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_GAP_0_PPA_LINE_MIN_GAP_DEFAULT_MASK                  _MK_MASK_CONST(0xffff)
+#define CSI_PIXEL_STREAM_A_GAP_0_PPA_LINE_MIN_GAP_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_GAP_0_PPA_LINE_MIN_GAP_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Minium number of viclk cycles from end of 
+// frame (Video_control = EF) to start of next
+// frame (Video_control = SF).
+// This parameter is to ensure that minimum V-blank
+// time requirement of VI/ISP is satisfied.
+// This field takes effect only when the frame gap 
+// of the input stream is less than the specified
+// value.
+#define CSI_PIXEL_STREAM_A_GAP_0_PPA_FRAME_MIN_GAP_SHIFT                        _MK_SHIFT_CONST(16)
+#define CSI_PIXEL_STREAM_A_GAP_0_PPA_FRAME_MIN_GAP_FIELD                        (_MK_MASK_CONST(0xffff) << CSI_PIXEL_STREAM_A_GAP_0_PPA_FRAME_MIN_GAP_SHIFT)
+#define CSI_PIXEL_STREAM_A_GAP_0_PPA_FRAME_MIN_GAP_RANGE                        31:16
+#define CSI_PIXEL_STREAM_A_GAP_0_PPA_FRAME_MIN_GAP_WOFFSET                      0x0
+#define CSI_PIXEL_STREAM_A_GAP_0_PPA_FRAME_MIN_GAP_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_GAP_0_PPA_FRAME_MIN_GAP_DEFAULT_MASK                 _MK_MASK_CONST(0xffff)
+#define CSI_PIXEL_STREAM_A_GAP_0_PPA_FRAME_MIN_GAP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_GAP_0_PPA_FRAME_MIN_GAP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register CSI_PIXEL_STREAM_PPA_COMMAND_0  // CSI Pixel Parser A Command
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0                  _MK_ADDR_CONST(0x20a)
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_WORD_COUNT                       0x1
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_RESET_MASK                       _MK_MASK_CONST(0x3)
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_READ_MASK                        _MK_MASK_CONST(0xff17)
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_WRITE_MASK                       _MK_MASK_CONST(0xff17)
+// CSI Pixel Parser A Enable
+//  This parameter controls CSI Pixel Parser A
+//  to start or stop receiving data.       reset (disable immediately)
+//  Enabling the pixel Parser does not enable 
+//  the corresponding input source to receive 
+//  data. If Pixel parser is enabled later than
+//  the  corresponding input source, csi will keep
+//  on rejecting incoming stream, till it encounters
+//  a valid SF. 
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_ENABLE_FIELD                     (_MK_MASK_CONST(0x3) << CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_ENABLE_SHIFT)
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_ENABLE_RANGE                     1:0
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_ENABLE_WOFFSET                   0x0
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_ENABLE_NOP                       _MK_ENUM_CONST(0)    // //       no operation
+
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_ENABLE_ENABLE                    _MK_ENUM_CONST(1)    // //       enable at the next frame start as
+//       specified by the CSI Start Marker
+
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_ENABLE_DISABLE                   _MK_ENUM_CONST(2)    // //       disable after current frame end and before
+//       next frame start.
+
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_ENABLE_RST                       _MK_ENUM_CONST(3)
+
+// CSI Pixel Parser A Single Shot Mode SW should Clear it along with disabling the 
+// CSI_PPA_ENABLE, once a frame is captured
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_SINGLE_SHOT_SHIFT                        _MK_SHIFT_CONST(2)
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_SINGLE_SHOT_FIELD                        (_MK_MASK_CONST(0x1) << CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_SINGLE_SHOT_SHIFT)
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_SINGLE_SHOT_RANGE                        2:2
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_SINGLE_SHOT_WOFFSET                      0x0
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_SINGLE_SHOT_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_SINGLE_SHOT_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_SINGLE_SHOT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_SINGLE_SHOT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_SINGLE_SHOT_DISABLE                      _MK_ENUM_CONST(0)
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_SINGLE_SHOT_ENABLE                       _MK_ENUM_CONST(1)
+
+// CSI Pixel Parser A VSYNC Start Marker  start of frame is indicated when VSYNC signal 
+//  is received. When the input stream is from the
+//  VIP path and the data mode is PACKET, then this
+//  field may be programmed to VSYNC.
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_VSYNC_START_MARKER_SHIFT                 _MK_SHIFT_CONST(4)
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_VSYNC_START_MARKER_FIELD                 (_MK_MASK_CONST(0x1) << CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_VSYNC_START_MARKER_SHIFT)
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_VSYNC_START_MARKER_RANGE                 4:4
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_VSYNC_START_MARKER_WOFFSET                       0x0
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_VSYNC_START_MARKER_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_VSYNC_START_MARKER_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_VSYNC_START_MARKER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_VSYNC_START_MARKER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_VSYNC_START_MARKER_FSPKT                 _MK_ENUM_CONST(0)    // //  Start of frame is indicated when a Frame
+//  Start short packet is received with a frame
+//  number whose least significant four bits are
+//  greater than, or equal to, 
+//  CSI_PPA_START_MARKER_FRAME_MIN and less than,
+//  or equal to, CSI_PPA_START_MARKER_FRAME_MAX.
+//  When the input stream is from a CSI port, or 
+//  from the host path, or from the VIP path and 
+//  the data mode is PAYLOAD_ONLY, then this field
+//  may be programmed to FSPKT.
+
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_VSYNC_START_MARKER_VSYNC                 _MK_ENUM_CONST(1)
+
+// CSI Pixel Parser A Start Marker Minimum
+// Start Frame is indicated when Max condition below
+// is met and the least significant four bits of the
+// frame number are greater than, or equal to, this value.
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_START_MARKER_FRAME_MIN_SHIFT                     _MK_SHIFT_CONST(8)
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_START_MARKER_FRAME_MIN_FIELD                     (_MK_MASK_CONST(0xf) << CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_START_MARKER_FRAME_MIN_SHIFT)
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_START_MARKER_FRAME_MIN_RANGE                     11:8
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_START_MARKER_FRAME_MIN_WOFFSET                   0x0
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_START_MARKER_FRAME_MIN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_START_MARKER_FRAME_MIN_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_START_MARKER_FRAME_MIN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_START_MARKER_FRAME_MIN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// CSI Pixel Parser A Start Marker Maximum
+// Start Frame is indicated when Min condition above
+// is met and the least significant four bits of the
+// frame number are less than, or equal to, this value.
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_START_MARKER_FRAME_MAX_SHIFT                     _MK_SHIFT_CONST(12)
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_START_MARKER_FRAME_MAX_FIELD                     (_MK_MASK_CONST(0xf) << CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_START_MARKER_FRAME_MAX_SHIFT)
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_START_MARKER_FRAME_MAX_RANGE                     15:12
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_START_MARKER_FRAME_MAX_WOFFSET                   0x0
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_START_MARKER_FRAME_MAX_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_START_MARKER_FRAME_MAX_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_START_MARKER_FRAME_MAX_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_START_MARKER_FRAME_MAX_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Reserved address 523 [0x20b] 
+
+// Reserved address 524 [0x20c] 
+
+// Reserved address 525 [0x20d] 
+
+// Reserved address 526 [0x20e] 
+
+// Register CSI_INPUT_STREAM_B_CONTROL_0  // CSI Input Stream B Control
+#define CSI_INPUT_STREAM_B_CONTROL_0                    _MK_ADDR_CONST(0x20f)
+#define CSI_INPUT_STREAM_B_CONTROL_0_WORD_COUNT                         0x1
+#define CSI_INPUT_STREAM_B_CONTROL_0_RESET_VAL                  _MK_MASK_CONST(0x3f0000)
+#define CSI_INPUT_STREAM_B_CONTROL_0_RESET_MASK                         _MK_MASK_CONST(0x7f0013)
+#define CSI_INPUT_STREAM_B_CONTROL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define CSI_INPUT_STREAM_B_CONTROL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CSI_INPUT_STREAM_B_CONTROL_0_READ_MASK                  _MK_MASK_CONST(0x7f0013)
+#define CSI_INPUT_STREAM_B_CONTROL_0_WRITE_MASK                         _MK_MASK_CONST(0x7f0013)
+// CSI-B Data Lane
+//   0= 1 data lane
+//   1= 2 data lanes (not supported on SC17 & SC25)
+//   2= 3 data lanes (not supported on SC17 & SC25)
+//   3= 4 data lanes (not supported on SC17 & SC25)
+#define CSI_INPUT_STREAM_B_CONTROL_0_CSI_B_DATA_LANE_SHIFT                      _MK_SHIFT_CONST(0)
+#define CSI_INPUT_STREAM_B_CONTROL_0_CSI_B_DATA_LANE_FIELD                      (_MK_MASK_CONST(0x3) << CSI_INPUT_STREAM_B_CONTROL_0_CSI_B_DATA_LANE_SHIFT)
+#define CSI_INPUT_STREAM_B_CONTROL_0_CSI_B_DATA_LANE_RANGE                      1:0
+#define CSI_INPUT_STREAM_B_CONTROL_0_CSI_B_DATA_LANE_WOFFSET                    0x0
+#define CSI_INPUT_STREAM_B_CONTROL_0_CSI_B_DATA_LANE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_INPUT_STREAM_B_CONTROL_0_CSI_B_DATA_LANE_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define CSI_INPUT_STREAM_B_CONTROL_0_CSI_B_DATA_LANE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_INPUT_STREAM_B_CONTROL_0_CSI_B_DATA_LANE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Enables skip packet threshold feature. Skip packet feature is enabled.
+#define CSI_INPUT_STREAM_B_CONTROL_0_CSI_B_SKIP_PACKET_THRESHOLD_ENABLE_SHIFT                   _MK_SHIFT_CONST(4)
+#define CSI_INPUT_STREAM_B_CONTROL_0_CSI_B_SKIP_PACKET_THRESHOLD_ENABLE_FIELD                   (_MK_MASK_CONST(0x1) << CSI_INPUT_STREAM_B_CONTROL_0_CSI_B_SKIP_PACKET_THRESHOLD_ENABLE_SHIFT)
+#define CSI_INPUT_STREAM_B_CONTROL_0_CSI_B_SKIP_PACKET_THRESHOLD_ENABLE_RANGE                   4:4
+#define CSI_INPUT_STREAM_B_CONTROL_0_CSI_B_SKIP_PACKET_THRESHOLD_ENABLE_WOFFSET                 0x0
+#define CSI_INPUT_STREAM_B_CONTROL_0_CSI_B_SKIP_PACKET_THRESHOLD_ENABLE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_INPUT_STREAM_B_CONTROL_0_CSI_B_SKIP_PACKET_THRESHOLD_ENABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CSI_INPUT_STREAM_B_CONTROL_0_CSI_B_SKIP_PACKET_THRESHOLD_ENABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_INPUT_STREAM_B_CONTROL_0_CSI_B_SKIP_PACKET_THRESHOLD_ENABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CSI_INPUT_STREAM_B_CONTROL_0_CSI_B_SKIP_PACKET_THRESHOLD_ENABLE_DISABLE                 _MK_ENUM_CONST(0)    // // Skip packet feature is disabled.     
+
+#define CSI_INPUT_STREAM_B_CONTROL_0_CSI_B_SKIP_PACKET_THRESHOLD_ENABLE_ENABLE                  _MK_ENUM_CONST(1)
+
+// CSI-B Skip Packet Threshold
+//  This value is compared against the internal
+//  FIFO that buffer the input streams. A packet
+//  will be skipped (discarded) if the pixel
+//  stream processor is busy (probably due to
+//  padding process of a short line) and the
+//  number of entries in the internal FIFO
+//  exceeds this threshold value. Note that
+//  each entry in the internal FIFO buffer is
+//  four bytes.
+//  To turn off this feature, set the value
+//  to its maximum value (all ones).
+#define CSI_INPUT_STREAM_B_CONTROL_0_CSI_B_SKIP_PACKET_THRESHOLD_SHIFT                  _MK_SHIFT_CONST(16)
+#define CSI_INPUT_STREAM_B_CONTROL_0_CSI_B_SKIP_PACKET_THRESHOLD_FIELD                  (_MK_MASK_CONST(0x7f) << CSI_INPUT_STREAM_B_CONTROL_0_CSI_B_SKIP_PACKET_THRESHOLD_SHIFT)
+#define CSI_INPUT_STREAM_B_CONTROL_0_CSI_B_SKIP_PACKET_THRESHOLD_RANGE                  22:16
+#define CSI_INPUT_STREAM_B_CONTROL_0_CSI_B_SKIP_PACKET_THRESHOLD_WOFFSET                        0x0
+#define CSI_INPUT_STREAM_B_CONTROL_0_CSI_B_SKIP_PACKET_THRESHOLD_DEFAULT                        _MK_MASK_CONST(0x3f)
+#define CSI_INPUT_STREAM_B_CONTROL_0_CSI_B_SKIP_PACKET_THRESHOLD_DEFAULT_MASK                   _MK_MASK_CONST(0x7f)
+#define CSI_INPUT_STREAM_B_CONTROL_0_CSI_B_SKIP_PACKET_THRESHOLD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_INPUT_STREAM_B_CONTROL_0_CSI_B_SKIP_PACKET_THRESHOLD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Reserved address 528 [0x210] 
+
+// Register CSI_PIXEL_STREAM_B_CONTROL0_0  // CSI Pixel Stream A Control 0
+#define CSI_PIXEL_STREAM_B_CONTROL0_0                   _MK_ADDR_CONST(0x211)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_WORD_COUNT                        0x1
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_RESET_MASK                        _MK_MASK_CONST(0x7)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_READ_MASK                         _MK_MASK_CONST(0x3b3ffff7)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_WRITE_MASK                        _MK_MASK_CONST(0x3b3ffff7)
+// CSI Pixel Parser B Stream Source   Host
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_STREAM_SOURCE_SHIFT                       _MK_SHIFT_CONST(0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_STREAM_SOURCE_FIELD                       (_MK_MASK_CONST(0x7) << CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_STREAM_SOURCE_SHIFT)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_STREAM_SOURCE_RANGE                       2:0
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_STREAM_SOURCE_WOFFSET                     0x0
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_STREAM_SOURCE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_STREAM_SOURCE_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_STREAM_SOURCE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_STREAM_SOURCE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_STREAM_SOURCE_CSI_A                       _MK_ENUM_CONST(0)    // //   CSI Interface A
+
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_STREAM_SOURCE_CSI_B                       _MK_ENUM_CONST(1)    // //   CSI Interface B
+
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_STREAM_SOURCE_VI_PORT                     _MK_ENUM_CONST(6)    // //   VI port
+
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_STREAM_SOURCE_HOST                        _MK_ENUM_CONST(7)
+
+// CSI Pixel Parser B Packet Header processing
+//  This specifies whether packet header is
+//  sent in the beginning of packet or not.      Packet header is sent.
+//      This setting should be used if the
+//      stream source is CSI Interface A or B.
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_PACKET_HEADER_SHIFT                       _MK_SHIFT_CONST(4)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_PACKET_HEADER_FIELD                       (_MK_MASK_CONST(0x1) << CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_PACKET_HEADER_SHIFT)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_PACKET_HEADER_RANGE                       4:4
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_PACKET_HEADER_WOFFSET                     0x0
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_PACKET_HEADER_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_PACKET_HEADER_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_PACKET_HEADER_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_PACKET_HEADER_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_PACKET_HEADER_NOT_SENT                    _MK_ENUM_CONST(0)    // //      Packet header is not sent.
+//      This setting should not be used if the
+//      stream source is CSI Interface A or B.
+//      Unless CSI-A, or CSI-B, is operating in a
+//      stream capture debug mode.
+//      In this case, CSI_PPB_DATA_TYPE specifies
+//      the stream data format and the number
+//      of bytes per line/packet is
+//      specified by CSI_PPB_WORD_COUNT.
+//      This implies that a packet footer
+//      is also not sent.  In this case, no 
+//      packet footer CRC check should be performed.
+
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_PACKET_HEADER_SENT                        _MK_ENUM_CONST(1)
+
+// CSI Pixel Parser B Data Identifier (DI) byte processing
+//  This parameter is effective only if packet
+//  header is sent as part of the stream.      Enabled  - Data Identifier byte in
+//      packet header should be compared against
+//      the CSI_PPB_DATA_TYPE and the
+//      CSI_PPB_VIRTUAL_CHANNEL_ID.
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_IDENTIFIER_SHIFT                     _MK_SHIFT_CONST(5)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_IDENTIFIER_FIELD                     (_MK_MASK_CONST(0x1) << CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_IDENTIFIER_SHIFT)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_IDENTIFIER_RANGE                     5:5
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_IDENTIFIER_WOFFSET                   0x0
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_IDENTIFIER_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_IDENTIFIER_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_IDENTIFIER_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_IDENTIFIER_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_IDENTIFIER_DISABLED                  _MK_ENUM_CONST(0)    // //      Disabled - Data Identifier byte in
+//      packet header should be ignored
+//      (not checked against CSI_PPB_DATA_TYPE
+//      and against CSI_PPB_VIRTUAL_CHANNEL_ID).
+//      In this case, CSI_PPB_DATA_TYPE specifies
+//      the stream data format.
+
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_IDENTIFIER_ENABLED                   _MK_ENUM_CONST(1)
+
+// CSI Pixel Parser B Word Count Select
+//  This parameter is effective only if packet
+//  header is sent as part of the stream.      The number of bytes per line is to be
+//      extracted from Word Count field in the
+//      packet header. Note that if the serial
+//      link is not error free, programming this
+//      bit to HEADER may be dangerous because 
+//      the word count information in the header
+//      may be corrupted. 
+//
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_WORD_COUNT_SELECT_SHIFT                   _MK_SHIFT_CONST(6)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_WORD_COUNT_SELECT_FIELD                   (_MK_MASK_CONST(0x1) << CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_WORD_COUNT_SELECT_SHIFT)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_WORD_COUNT_SELECT_RANGE                   6:6
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_WORD_COUNT_SELECT_WOFFSET                 0x0
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_WORD_COUNT_SELECT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_WORD_COUNT_SELECT_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_WORD_COUNT_SELECT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_WORD_COUNT_SELECT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_WORD_COUNT_SELECT_REGISTER                        _MK_ENUM_CONST(0)    // //      Word Count in packet header is ignored
+//      and the number of bytes per line/packet
+//      is specified by CSI_PPB_WORD_COUNT. Payload
+//      CRC check will not be valid if the word
+//      count in CSI_PPB_WORD_COUNT is different 
+//      than the count in the packet header.
+//      It is recommended to always program
+//      this bit to REGISTER and always program
+//      CSI_PPB_WORD_COUNT.
+
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_WORD_COUNT_SELECT_HEADER                  _MK_ENUM_CONST(1)
+
+// CSI Pixel Parser B Data CRC Check
+//  This parameter specifies whether the last
+//  2 bytes of packet should be treated as
+//  CRC checksum and used to perform CRC check
+//  on the payload data. Note that in case there
+//  are 2 bytes of data CRC at the end of the
+//  packet, the packet word count does not
+//  include the CRC bytes.      Data CRC Check is enabled.
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_CRC_CHECK_SHIFT                   _MK_SHIFT_CONST(7)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_CRC_CHECK_FIELD                   (_MK_MASK_CONST(0x1) << CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_CRC_CHECK_SHIFT)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_CRC_CHECK_RANGE                   7:7
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_CRC_CHECK_WOFFSET                 0x0
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_CRC_CHECK_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_CRC_CHECK_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_CRC_CHECK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_CRC_CHECK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_CRC_CHECK_DISABLE                 _MK_ENUM_CONST(0)    // //      Data CRC Check is disabled regardless
+//      of whether there are CRC checksum at
+//      the end of the packet.
+
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_CRC_CHECK_ENABLE                  _MK_ENUM_CONST(1)
+
+// CSI Pixel Parser B Data Type  This is CSI compatible data type as defined
+//  in CSI specification. If the source stream
+//  contains packet headers this value can be compared
+//  to the CSI Data Type value in the 6 LSB of the
+//  CSI Data Identifier (DI) byte. If the source stream
+//  doesn't contain packet headers, or CSI_PPB_DATA_IDENTIFIER
+//  is DISABLED, this value will be used to determine how
+//  the stream will be converted to pixels.
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_TYPE_SHIFT                   _MK_SHIFT_CONST(8)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_TYPE_FIELD                   (_MK_MASK_CONST(0x3f) << CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_TYPE_SHIFT)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_TYPE_RANGE                   13:8
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_TYPE_WOFFSET                 0x0
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_TYPE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_TYPE_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_TYPE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_TYPE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_TYPE_YUV420_8                        _MK_ENUM_CONST(24)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_TYPE_YUV420_10                       _MK_ENUM_CONST(25)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_TYPE_LEG_YUV420_8                    _MK_ENUM_CONST(26)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_TYPE_YUV420CSPS_8                    _MK_ENUM_CONST(28)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_TYPE_YUV420CSPS_10                   _MK_ENUM_CONST(29)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_TYPE_YUV422_8                        _MK_ENUM_CONST(30)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_TYPE_YUV422_10                       _MK_ENUM_CONST(31)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_TYPE_RGB444                  _MK_ENUM_CONST(32)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_TYPE_RGB555                  _MK_ENUM_CONST(33)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_TYPE_RGB565                  _MK_ENUM_CONST(34)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_TYPE_RGB666                  _MK_ENUM_CONST(35)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_TYPE_RGB888                  _MK_ENUM_CONST(36)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_TYPE_RAW6                    _MK_ENUM_CONST(40)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_TYPE_RAW7                    _MK_ENUM_CONST(41)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_TYPE_RAW8                    _MK_ENUM_CONST(42)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_TYPE_RAW10                   _MK_ENUM_CONST(43)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_TYPE_RAW12                   _MK_ENUM_CONST(44)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_TYPE_RAW14                   _MK_ENUM_CONST(45)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_TYPE_ARB_DT1                 _MK_ENUM_CONST(48)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_TYPE_ARB_DT2                 _MK_ENUM_CONST(49)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_TYPE_ARB_DT3                 _MK_ENUM_CONST(50)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_TYPE_ARB_DT4                 _MK_ENUM_CONST(51)
+
+// CSI Pixel Parser B Virtual Channel Identifier  
+//  This is CSI compatible virtual channel
+//  identifier as defined in CSI specification.
+//  If the source stream contains packet headers
+//  and CSI_PPB_DATA_IDENTIFIER is ENABLED this
+//  value will be compared to the CSI Virtual
+//  Channel Identifier value in the 2 MSB of the
+//  CSI Data Identifier (DI) byte. This value will
+//  be ignored if the source stream doesn't contain
+//  packet headers, or CSI_PPB_DATA_IDENTIFIER is 
+//  DISABLED, then this value will be ignored.
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_VIRTUAL_CHANNEL_ID_SHIFT                  _MK_SHIFT_CONST(14)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_VIRTUAL_CHANNEL_ID_FIELD                  (_MK_MASK_CONST(0x3) << CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_VIRTUAL_CHANNEL_ID_SHIFT)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_VIRTUAL_CHANNEL_ID_RANGE                  15:14
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_VIRTUAL_CHANNEL_ID_WOFFSET                        0x0
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_VIRTUAL_CHANNEL_ID_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_VIRTUAL_CHANNEL_ID_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_VIRTUAL_CHANNEL_ID_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_VIRTUAL_CHANNEL_ID_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_VIRTUAL_CHANNEL_ID_ONE                    _MK_ENUM_CONST(0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_VIRTUAL_CHANNEL_ID_TWO                    _MK_ENUM_CONST(1)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_VIRTUAL_CHANNEL_ID_THREE                  _MK_ENUM_CONST(2)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_VIRTUAL_CHANNEL_ID_FOUR                   _MK_ENUM_CONST(3)
+
+// CSI Pixel Parser B Output Format Options
+//  This parameter specifies output data format.       Output for storing RAW data to memory through
+//       ISP. Undefined LS color bits for RGB_666, 
+//       RGB_565, RGB_555, and RGB_444, will be zeroed.
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_OUTPUT_FORMAT_OPTIONS_SHIFT                       _MK_SHIFT_CONST(16)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_OUTPUT_FORMAT_OPTIONS_FIELD                       (_MK_MASK_CONST(0xf) << CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_OUTPUT_FORMAT_OPTIONS_SHIFT)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_OUTPUT_FORMAT_OPTIONS_RANGE                       19:16
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_OUTPUT_FORMAT_OPTIONS_WOFFSET                     0x0
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_OUTPUT_FORMAT_OPTIONS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_OUTPUT_FORMAT_OPTIONS_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_OUTPUT_FORMAT_OPTIONS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_OUTPUT_FORMAT_OPTIONS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_OUTPUT_FORMAT_OPTIONS_ARBITRARY                   _MK_ENUM_CONST(0)    // //       Output as 8-bit arbitrary data stream
+//       This may be used for compressed JPEG stream
+
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_OUTPUT_FORMAT_OPTIONS_PIXEL                       _MK_ENUM_CONST(1)    // //       Output the normal 1 pixel/clock. Undefined 
+//       LS color bits for RGB_666, RGB_565, RGB_555,
+//       and RGB_444, will be zeroed.
+
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_OUTPUT_FORMAT_OPTIONS_PIXEL_REP                   _MK_ENUM_CONST(2)    // //       Same as PIXEL except MS color bits, for RGB_666, 
+//       RGB_565, RGB_555, and RGB_444, will be 
+//       replicated to their undefined LS bits.
+
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_OUTPUT_FORMAT_OPTIONS_STORE                       _MK_ENUM_CONST(3)
+
+// CSI Pixel Parser B Embedded Data Options 
+//  This specifies how to deal with embedded
+//  data within the specified input stream
+//  assuming that the CSI_PPB_DATA_TYPE is not
+//  embedded data and assuming that embedded
+//  data is not already processed by other
+//  CSI pixel stream processor.       output embedded data as 8-bpp arbitrary
+//       data stream.
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_EMBEDDED_DATA_OPTIONS_SHIFT                       _MK_SHIFT_CONST(20)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_EMBEDDED_DATA_OPTIONS_FIELD                       (_MK_MASK_CONST(0x3) << CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_EMBEDDED_DATA_OPTIONS_SHIFT)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_EMBEDDED_DATA_OPTIONS_RANGE                       21:20
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_EMBEDDED_DATA_OPTIONS_WOFFSET                     0x0
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_EMBEDDED_DATA_OPTIONS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_EMBEDDED_DATA_OPTIONS_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_EMBEDDED_DATA_OPTIONS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_EMBEDDED_DATA_OPTIONS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_EMBEDDED_DATA_OPTIONS_DISCARD                     _MK_ENUM_CONST(0)    // //       discard (throw away) embedded data
+
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_EMBEDDED_DATA_OPTIONS_EMBEDDED                    _MK_ENUM_CONST(1)
+
+// CSI Pixel Parser B Pad Short Line
+//  This specifies how to deal with shorter than
+//  expected line (the number of bytes received
+//  is less than the specified word count)       short line is not padded (will output
+//       less pixels than expected).
+//       This option is not recommended and may
+//       cause other modules that receives CSI
+//       output stream to hang up.
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_PAD_SHORT_LINE_SHIFT                      _MK_SHIFT_CONST(24)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_PAD_SHORT_LINE_FIELD                      (_MK_MASK_CONST(0x3) << CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_PAD_SHORT_LINE_SHIFT)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_PAD_SHORT_LINE_RANGE                      25:24
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_PAD_SHORT_LINE_WOFFSET                    0x0
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_PAD_SHORT_LINE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_PAD_SHORT_LINE_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_PAD_SHORT_LINE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_PAD_SHORT_LINE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_PAD_SHORT_LINE_PAD0S                      _MK_ENUM_CONST(0)    // //       short line is padded by pixel of zeros
+//       such that the expected number of output
+//       pixels is correct. Due to the time
+//       required to do the padding, subsequent
+//       line packet maybe discarded and
+//       therefore may cause a short frame
+//       (total number of lines per frame is
+//       less than expected).
+
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_PAD_SHORT_LINE_PAD1S                      _MK_ENUM_CONST(1)    // //       short line is padded by pixel of ones
+//       such that the expected number of output
+//       pixels is correct. Due to the time
+//       required to do the padding, subsequent
+//       line packet maybe discarded and
+//       therefore may cause a short frame
+//       (total number of lines per frame is
+//       less than expected).
+
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_PAD_SHORT_LINE_NOPAD                      _MK_ENUM_CONST(2)
+
+// CSI Pixel Parser B Packet Header Error Correction Enable
+//  This parameter specifies whether single bit
+//  errors in the packet header will be
+//  automatically corrected, or not.    Single bit errors in the header will not
+//    be corrected. Header ECC check will still
+//    set header ECC status bits and the packet
+//    will be processed by Pixel Parser B. DISABLE
+//    should not be used when processing interleaved
+//    streams (Same stream going to both PPA and PPB).
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_HEADER_EC_ENABLE_SHIFT                    _MK_SHIFT_CONST(27)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_HEADER_EC_ENABLE_FIELD                    (_MK_MASK_CONST(0x1) << CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_HEADER_EC_ENABLE_SHIFT)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_HEADER_EC_ENABLE_RANGE                    27:27
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_HEADER_EC_ENABLE_WOFFSET                  0x0
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_HEADER_EC_ENABLE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_HEADER_EC_ENABLE_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_HEADER_EC_ENABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_HEADER_EC_ENABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_HEADER_EC_ENABLE_ENABLE                   _MK_ENUM_CONST(0)    // //    Single bit errors in the header will be
+//    automatically corrected.
+
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_HEADER_EC_ENABLE_DISABLE                  _MK_ENUM_CONST(1)
+
+// CSI Pixel Parser B Pad Frame
+//  This specifies how to deal with frames that are
+//  shorter (fewer lines) that expected. Short frames
+//  are usually caused by line packets being dropped
+//  because of packet errors. Expected frame height is
+//  specified in PPB_EXP_FRAME_HEIGHT. To do padding the
+//  value in CSI_PPB_WORD_COUNT needs to be set to the
+//  number of input bytes in each lines payload.  Short frames will not be padded out.   
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_PAD_FRAME_SHIFT                   _MK_SHIFT_CONST(28)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_PAD_FRAME_FIELD                   (_MK_MASK_CONST(0x3) << CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_PAD_FRAME_SHIFT)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_PAD_FRAME_RANGE                   29:28
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_PAD_FRAME_WOFFSET                 0x0
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_PAD_FRAME_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_PAD_FRAME_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_PAD_FRAME_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_PAD_FRAME_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_PAD_FRAME_PAD0S                   _MK_ENUM_CONST(0)    // //  Lines of all zeros will be used to pad out frames
+//  that are shorter than expected height.   
+//  PPB_EXP_FRAME_HEIGHT must be programmed to
+//  an appropriate value if this fields is set to PAD0S.
+
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_PAD_FRAME_PAD1S                   _MK_ENUM_CONST(1)    // //  Lines of all ones will be used to pad out frames
+//  that are shorter than expected height.      
+//  PPB_EXP_FRAME_HEIGHT must be programmed to
+//  an appropriate value if this fields is set to PAD1S.
+
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_PAD_FRAME_NOPAD                   _MK_ENUM_CONST(2)
+
+
+// Register CSI_PIXEL_STREAM_B_CONTROL1_0  // CSI Pixel Stream B Control 1
+#define CSI_PIXEL_STREAM_B_CONTROL1_0                   _MK_ADDR_CONST(0x212)
+#define CSI_PIXEL_STREAM_B_CONTROL1_0_WORD_COUNT                        0x1
+#define CSI_PIXEL_STREAM_B_CONTROL1_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL1_0_RESET_MASK                        _MK_MASK_CONST(0xff)
+#define CSI_PIXEL_STREAM_B_CONTROL1_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL1_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL1_0_READ_MASK                         _MK_MASK_CONST(0xff)
+#define CSI_PIXEL_STREAM_B_CONTROL1_0_WRITE_MASK                        _MK_MASK_CONST(0xff)
+// CSI Pixel Parser B Top Field Frame
+//  This parameter specifies the frame number for 
+//  top field detection for interlaced input video
+//  stream. Top Field is indicated when each of the
+//  least significant four bits of the frame number
+//  that has a one in its mask bit matches the 
+//  corresponding bit in this parameter. In other
+//  words, Top Field is detected when the bitwise
+//  AND of  
+// ~(CSI_PPB_TOP_FIELD_FRAME ^ <frame number>) & CSI_PPB_TOP_FIELD_FRAME_MASK
+//  is one. Frame Number is taken from the WC field
+//  of the Frame Start short packet.
+#define CSI_PIXEL_STREAM_B_CONTROL1_0_CSI_PPB_TOP_FIELD_FRAME_SHIFT                     _MK_SHIFT_CONST(0)
+#define CSI_PIXEL_STREAM_B_CONTROL1_0_CSI_PPB_TOP_FIELD_FRAME_FIELD                     (_MK_MASK_CONST(0xf) << CSI_PIXEL_STREAM_B_CONTROL1_0_CSI_PPB_TOP_FIELD_FRAME_SHIFT)
+#define CSI_PIXEL_STREAM_B_CONTROL1_0_CSI_PPB_TOP_FIELD_FRAME_RANGE                     3:0
+#define CSI_PIXEL_STREAM_B_CONTROL1_0_CSI_PPB_TOP_FIELD_FRAME_WOFFSET                   0x0
+#define CSI_PIXEL_STREAM_B_CONTROL1_0_CSI_PPB_TOP_FIELD_FRAME_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL1_0_CSI_PPB_TOP_FIELD_FRAME_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define CSI_PIXEL_STREAM_B_CONTROL1_0_CSI_PPB_TOP_FIELD_FRAME_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL1_0_CSI_PPB_TOP_FIELD_FRAME_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// CSI Pixel Parser B Top Field Frame Mask
+#define CSI_PIXEL_STREAM_B_CONTROL1_0_CSI_PPB_TOP_FIELD_FRAME_MASK_SHIFT                        _MK_SHIFT_CONST(4)
+#define CSI_PIXEL_STREAM_B_CONTROL1_0_CSI_PPB_TOP_FIELD_FRAME_MASK_FIELD                        (_MK_MASK_CONST(0xf) << CSI_PIXEL_STREAM_B_CONTROL1_0_CSI_PPB_TOP_FIELD_FRAME_MASK_SHIFT)
+#define CSI_PIXEL_STREAM_B_CONTROL1_0_CSI_PPB_TOP_FIELD_FRAME_MASK_RANGE                        7:4
+#define CSI_PIXEL_STREAM_B_CONTROL1_0_CSI_PPB_TOP_FIELD_FRAME_MASK_WOFFSET                      0x0
+#define CSI_PIXEL_STREAM_B_CONTROL1_0_CSI_PPB_TOP_FIELD_FRAME_MASK_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL1_0_CSI_PPB_TOP_FIELD_FRAME_MASK_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define CSI_PIXEL_STREAM_B_CONTROL1_0_CSI_PPB_TOP_FIELD_FRAME_MASK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL1_0_CSI_PPB_TOP_FIELD_FRAME_MASK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register CSI_PIXEL_STREAM_B_WORD_COUNT_0  // CSI Pixel Stream A Word Count
+#define CSI_PIXEL_STREAM_B_WORD_COUNT_0                 _MK_ADDR_CONST(0x213)
+#define CSI_PIXEL_STREAM_B_WORD_COUNT_0_WORD_COUNT                      0x1
+#define CSI_PIXEL_STREAM_B_WORD_COUNT_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_WORD_COUNT_0_RESET_MASK                      _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_WORD_COUNT_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_WORD_COUNT_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_WORD_COUNT_0_READ_MASK                       _MK_MASK_CONST(0xffff)
+#define CSI_PIXEL_STREAM_B_WORD_COUNT_0_WRITE_MASK                      _MK_MASK_CONST(0xffff)
+// CSI Pixel Parser B Word Count
+//  This parameter specifies the number of
+//  bytes per line/packet in the case where
+//  Word Count field in packet header is not
+//  used or where packet header is not sent.
+//  This count does not includes the additional
+//  2 bytes of CRC checksum if data CRC check
+//  is enabled.
+//  When the input stream comes from a CSI camera
+//  port, this parameter must be programmed when 
+//  CSI_PPB_PAD_SHORT_LINE is set to either PAD0S
+//  or PAD1S, no matter whether CSI_PPB_WORD_COUNT_SELECT
+//  is set to REGISTER or HEADER.
+//  When the input stream comes from the host path
+//  or from the VIP path, and the data mode is
+//  PAYLOAD_ONLY, this count must be programmed.
+// Given a line width of N pixels, the programming 
+//  value of this parameters is as follows
+//  --------------------------------------
+//  data format            value
+//  --------------------------------------
+//  YUV420_8               N bytes
+//  YUV420_10              N/4*5 bytes
+//  LEG_YUV420_8           N/2*3 bytes
+//  YUV422_8               N*2 bytes
+//  YUV422_10              N/2*5 bytes
+//  RGB888                 N*3 bytes 
+//  RGB666                 N/4*9 bytes                 
+//  RGB565                 N*2 bytes
+//  RGB555                 N*2 bytes 
+//  RGB444                 N*2 bytes 
+//  RAW6                   N/4*3 bytes
+//  RAW7                   N/8*7 bytes
+//  RAW8                   N bytes 
+//  RAW10                  N/4*5 bytes
+//  RAW12                  N/2*3 bytes
+//  RAW14                  N/4*7 bytes
+//  ---------------------------------------
+#define CSI_PIXEL_STREAM_B_WORD_COUNT_0_CSI_PPB_WORD_COUNT_SHIFT                        _MK_SHIFT_CONST(0)
+#define CSI_PIXEL_STREAM_B_WORD_COUNT_0_CSI_PPB_WORD_COUNT_FIELD                        (_MK_MASK_CONST(0xffff) << CSI_PIXEL_STREAM_B_WORD_COUNT_0_CSI_PPB_WORD_COUNT_SHIFT)
+#define CSI_PIXEL_STREAM_B_WORD_COUNT_0_CSI_PPB_WORD_COUNT_RANGE                        15:0
+#define CSI_PIXEL_STREAM_B_WORD_COUNT_0_CSI_PPB_WORD_COUNT_WOFFSET                      0x0
+#define CSI_PIXEL_STREAM_B_WORD_COUNT_0_CSI_PPB_WORD_COUNT_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_WORD_COUNT_0_CSI_PPB_WORD_COUNT_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_WORD_COUNT_0_CSI_PPB_WORD_COUNT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_WORD_COUNT_0_CSI_PPB_WORD_COUNT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register CSI_PIXEL_STREAM_B_GAP_0  // CSI Pixel Stream B Gap
+#define CSI_PIXEL_STREAM_B_GAP_0                        _MK_ADDR_CONST(0x214)
+#define CSI_PIXEL_STREAM_B_GAP_0_WORD_COUNT                     0x1
+#define CSI_PIXEL_STREAM_B_GAP_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_GAP_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
+#define CSI_PIXEL_STREAM_B_GAP_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_GAP_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_GAP_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define CSI_PIXEL_STREAM_B_GAP_0_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
+// Minium number of viclk cycles from end of 
+// previous line (Video_control = EL_DATA) to start
+// of next line (Video_control = SL).
+// This parameter is to ensure that minimum H-blank
+// time requirement of VI/ISP is satisfied.
+// This field takes effect only when the line gap 
+// of the input stream is less than the specified
+// value.
+#define CSI_PIXEL_STREAM_B_GAP_0_PPB_LINE_MIN_GAP_SHIFT                 _MK_SHIFT_CONST(0)
+#define CSI_PIXEL_STREAM_B_GAP_0_PPB_LINE_MIN_GAP_FIELD                 (_MK_MASK_CONST(0xffff) << CSI_PIXEL_STREAM_B_GAP_0_PPB_LINE_MIN_GAP_SHIFT)
+#define CSI_PIXEL_STREAM_B_GAP_0_PPB_LINE_MIN_GAP_RANGE                 15:0
+#define CSI_PIXEL_STREAM_B_GAP_0_PPB_LINE_MIN_GAP_WOFFSET                       0x0
+#define CSI_PIXEL_STREAM_B_GAP_0_PPB_LINE_MIN_GAP_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_GAP_0_PPB_LINE_MIN_GAP_DEFAULT_MASK                  _MK_MASK_CONST(0xffff)
+#define CSI_PIXEL_STREAM_B_GAP_0_PPB_LINE_MIN_GAP_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_GAP_0_PPB_LINE_MIN_GAP_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Minium number of viclk cycles from end of 
+// frame (Video_control = EF) to start of next
+// frame (Video_control = SF).
+// This parameter is to ensure that minimum V-blank
+// time requirement of VI/ISP is satisfied.
+// This field takes effect only when the frame gap 
+// of the input stream is less than the specified
+// value.
+#define CSI_PIXEL_STREAM_B_GAP_0_PPB_FRAME_MIN_GAP_SHIFT                        _MK_SHIFT_CONST(16)
+#define CSI_PIXEL_STREAM_B_GAP_0_PPB_FRAME_MIN_GAP_FIELD                        (_MK_MASK_CONST(0xffff) << CSI_PIXEL_STREAM_B_GAP_0_PPB_FRAME_MIN_GAP_SHIFT)
+#define CSI_PIXEL_STREAM_B_GAP_0_PPB_FRAME_MIN_GAP_RANGE                        31:16
+#define CSI_PIXEL_STREAM_B_GAP_0_PPB_FRAME_MIN_GAP_WOFFSET                      0x0
+#define CSI_PIXEL_STREAM_B_GAP_0_PPB_FRAME_MIN_GAP_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_GAP_0_PPB_FRAME_MIN_GAP_DEFAULT_MASK                 _MK_MASK_CONST(0xffff)
+#define CSI_PIXEL_STREAM_B_GAP_0_PPB_FRAME_MIN_GAP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_GAP_0_PPB_FRAME_MIN_GAP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register CSI_PIXEL_STREAM_PPB_COMMAND_0  // CSI Pixel Parser B Command
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0                  _MK_ADDR_CONST(0x215)
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_WORD_COUNT                       0x1
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_RESET_MASK                       _MK_MASK_CONST(0x3)
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_READ_MASK                        _MK_MASK_CONST(0xff17)
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_WRITE_MASK                       _MK_MASK_CONST(0xff17)
+// CSI Pixel Parser B Enable
+//  This parameter controls CSI Pixel Parser B
+//  to start or stop receiving data.       reset (disable immediately)
+//  Enabling the pixel Parser does not enable 
+//  the corresponding input source to receive 
+//  data. If Pixel parser is enabled later than
+//  the  corresponding input source, csi will keep
+//  on rejecting incoming stream, till it encounters
+//  a valid SF.
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_ENABLE_FIELD                     (_MK_MASK_CONST(0x3) << CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_ENABLE_SHIFT)
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_ENABLE_RANGE                     1:0
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_ENABLE_WOFFSET                   0x0
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_ENABLE_NOP                       _MK_ENUM_CONST(0)    // //       no operation
+
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_ENABLE_ENABLE                    _MK_ENUM_CONST(1)    // //       enable at the next frame start as
+//       specified by the CSI Start Marker
+
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_ENABLE_DISABLE                   _MK_ENUM_CONST(2)    // //       disable after current frame end and before
+//       next frame start.
+
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_ENABLE_RST                       _MK_ENUM_CONST(3)
+
+// CSI Pixel Parser B Single Shot Mode SW should Clear it alongwith disabling the 
+// CSI_PPB_ENABLE, once a frame is captured
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_SINGLE_SHOT_SHIFT                        _MK_SHIFT_CONST(2)
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_SINGLE_SHOT_FIELD                        (_MK_MASK_CONST(0x1) << CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_SINGLE_SHOT_SHIFT)
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_SINGLE_SHOT_RANGE                        2:2
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_SINGLE_SHOT_WOFFSET                      0x0
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_SINGLE_SHOT_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_SINGLE_SHOT_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_SINGLE_SHOT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_SINGLE_SHOT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_SINGLE_SHOT_DISABLE                      _MK_ENUM_CONST(0)
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_SINGLE_SHOT_ENABLE                       _MK_ENUM_CONST(1)
+
+// CSI Pixel Parser B VSYNC Start Marker  Start of frame is indicated when VSYNC signal 
+//  is received. When the input stream is from the
+//  VIP path and the data mode is PACKET, then this
+//  field may be programmed to VSYNC.
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_VSYNC_START_MARKER_SHIFT                 _MK_SHIFT_CONST(4)
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_VSYNC_START_MARKER_FIELD                 (_MK_MASK_CONST(0x1) << CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_VSYNC_START_MARKER_SHIFT)
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_VSYNC_START_MARKER_RANGE                 4:4
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_VSYNC_START_MARKER_WOFFSET                       0x0
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_VSYNC_START_MARKER_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_VSYNC_START_MARKER_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_VSYNC_START_MARKER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_VSYNC_START_MARKER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_VSYNC_START_MARKER_FSPKT                 _MK_ENUM_CONST(0)    // //      Start of frame is indicated when a Frame
+//    Start short packet is received with a frame
+//    number who's least significant four bits are
+//    greater than, or equal to, 
+//    CSI_PPB_START_MARKER_FRAME_MIN and less than,
+//    or equal to, CSI_PPB_START_MARKER_FRAME_MAX.
+//  When the input stream is from a CSI port, or 
+//  from the host path, or from the VIP path and 
+//  the data mode is PAYLOAD_ONLY, then this field
+//  may be programmed to FSPKT.
+
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_VSYNC_START_MARKER_VSYNC                 _MK_ENUM_CONST(1)
+
+// CSI Pixel Parser B Start Marker Minimum
+// Start Frame is indicated when Max condition below
+// is met and the least significant four bits of the
+// frame number are greater than, or equal to, this value.
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_START_MARKER_FRAME_MIN_SHIFT                     _MK_SHIFT_CONST(8)
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_START_MARKER_FRAME_MIN_FIELD                     (_MK_MASK_CONST(0xf) << CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_START_MARKER_FRAME_MIN_SHIFT)
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_START_MARKER_FRAME_MIN_RANGE                     11:8
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_START_MARKER_FRAME_MIN_WOFFSET                   0x0
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_START_MARKER_FRAME_MIN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_START_MARKER_FRAME_MIN_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_START_MARKER_FRAME_MIN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_START_MARKER_FRAME_MIN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// CSI Pixel Parser B Start Marker Maximum
+// Start Frame is indicated when Min condition above
+// is met and the least significant four bits of the
+// frame number are less than, or equal to, this value.
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_START_MARKER_FRAME_MAX_SHIFT                     _MK_SHIFT_CONST(12)
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_START_MARKER_FRAME_MAX_FIELD                     (_MK_MASK_CONST(0xf) << CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_START_MARKER_FRAME_MAX_SHIFT)
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_START_MARKER_FRAME_MAX_RANGE                     15:12
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_START_MARKER_FRAME_MAX_WOFFSET                   0x0
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_START_MARKER_FRAME_MAX_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_START_MARKER_FRAME_MAX_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_START_MARKER_FRAME_MAX_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_START_MARKER_FRAME_MAX_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Reserved address 534 [0x216] 
+
+// Reserved address 535 [0x217] 
+
+// Reserved address 536 [0x218] 
+
+// Reserved address 537 [0x219] 
+
+// Register CSI_PHY_CIL_COMMAND_0  // CSI Phy and CIL Command
+#define CSI_PHY_CIL_COMMAND_0                   _MK_ADDR_CONST(0x21a)
+#define CSI_PHY_CIL_COMMAND_0_WORD_COUNT                        0x1
+#define CSI_PHY_CIL_COMMAND_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define CSI_PHY_CIL_COMMAND_0_RESET_MASK                        _MK_MASK_CONST(0x30003)
+#define CSI_PHY_CIL_COMMAND_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define CSI_PHY_CIL_COMMAND_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_PHY_CIL_COMMAND_0_READ_MASK                         _MK_MASK_CONST(0x30003)
+#define CSI_PHY_CIL_COMMAND_0_WRITE_MASK                        _MK_MASK_CONST(0x30003)
+// CSI A Phy and CIL Enable
+//  This parameter controls CSI A Phy and CIL
+//  receiver to start or stop receiving data.    disable (reset)
+#define CSI_PHY_CIL_COMMAND_0_CSI_A_PHY_CIL_ENABLE_SHIFT                        _MK_SHIFT_CONST(0)
+#define CSI_PHY_CIL_COMMAND_0_CSI_A_PHY_CIL_ENABLE_FIELD                        (_MK_MASK_CONST(0x3) << CSI_PHY_CIL_COMMAND_0_CSI_A_PHY_CIL_ENABLE_SHIFT)
+#define CSI_PHY_CIL_COMMAND_0_CSI_A_PHY_CIL_ENABLE_RANGE                        1:0
+#define CSI_PHY_CIL_COMMAND_0_CSI_A_PHY_CIL_ENABLE_WOFFSET                      0x0
+#define CSI_PHY_CIL_COMMAND_0_CSI_A_PHY_CIL_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_PHY_CIL_COMMAND_0_CSI_A_PHY_CIL_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define CSI_PHY_CIL_COMMAND_0_CSI_A_PHY_CIL_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_PHY_CIL_COMMAND_0_CSI_A_PHY_CIL_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CSI_PHY_CIL_COMMAND_0_CSI_A_PHY_CIL_ENABLE_NOP                  _MK_ENUM_CONST(0)    // //    no operation
+
+#define CSI_PHY_CIL_COMMAND_0_CSI_A_PHY_CIL_ENABLE_ENABLE                       _MK_ENUM_CONST(1)    // //    enable
+
+#define CSI_PHY_CIL_COMMAND_0_CSI_A_PHY_CIL_ENABLE_DISABLE                      _MK_ENUM_CONST(2)
+
+// CSI B Phy and CIL Enable
+//  This parameter controls CSI B Phy and CIL
+//  receiver to start or stop receiving data.    disable (reset)
+#define CSI_PHY_CIL_COMMAND_0_CSI_B_PHY_CIL_ENABLE_SHIFT                        _MK_SHIFT_CONST(16)
+#define CSI_PHY_CIL_COMMAND_0_CSI_B_PHY_CIL_ENABLE_FIELD                        (_MK_MASK_CONST(0x3) << CSI_PHY_CIL_COMMAND_0_CSI_B_PHY_CIL_ENABLE_SHIFT)
+#define CSI_PHY_CIL_COMMAND_0_CSI_B_PHY_CIL_ENABLE_RANGE                        17:16
+#define CSI_PHY_CIL_COMMAND_0_CSI_B_PHY_CIL_ENABLE_WOFFSET                      0x0
+#define CSI_PHY_CIL_COMMAND_0_CSI_B_PHY_CIL_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_PHY_CIL_COMMAND_0_CSI_B_PHY_CIL_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define CSI_PHY_CIL_COMMAND_0_CSI_B_PHY_CIL_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_PHY_CIL_COMMAND_0_CSI_B_PHY_CIL_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CSI_PHY_CIL_COMMAND_0_CSI_B_PHY_CIL_ENABLE_NOP                  _MK_ENUM_CONST(0)    // //    no operation
+
+#define CSI_PHY_CIL_COMMAND_0_CSI_B_PHY_CIL_ENABLE_ENABLE                       _MK_ENUM_CONST(1)    // //    enable
+
+#define CSI_PHY_CIL_COMMAND_0_CSI_B_PHY_CIL_ENABLE_DISABLE                      _MK_ENUM_CONST(2)
+
+
+// Register CSI_PHY_CILA_CONTROL0_0  // CSI-A Phy and CIL Control
+#define CSI_PHY_CILA_CONTROL0_0                 _MK_ADDR_CONST(0x21b)
+#define CSI_PHY_CILA_CONTROL0_0_WORD_COUNT                      0x1
+#define CSI_PHY_CILA_CONTROL0_0_RESET_VAL                       _MK_MASK_CONST(0x2)
+#define CSI_PHY_CILA_CONTROL0_0_RESET_MASK                      _MK_MASK_CONST(0x3f)
+#define CSI_PHY_CILA_CONTROL0_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define CSI_PHY_CILA_CONTROL0_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define CSI_PHY_CILA_CONTROL0_0_READ_MASK                       _MK_MASK_CONST(0x3f)
+#define CSI_PHY_CILA_CONTROL0_0_WRITE_MASK                      _MK_MASK_CONST(0x3f)
+// When moving from LP mode to High Speed (LP11->LP01->LP00),
+// this setting determines how many csicil clock cycles (72 MHz
+// lp clock cycles) to wait, after LP00, 
+// before starting to look at the data.
+#define CSI_PHY_CILA_CONTROL0_0_CILA_THS_SETTLE_SHIFT                   _MK_SHIFT_CONST(0)
+#define CSI_PHY_CILA_CONTROL0_0_CILA_THS_SETTLE_FIELD                   (_MK_MASK_CONST(0xf) << CSI_PHY_CILA_CONTROL0_0_CILA_THS_SETTLE_SHIFT)
+#define CSI_PHY_CILA_CONTROL0_0_CILA_THS_SETTLE_RANGE                   3:0
+#define CSI_PHY_CILA_CONTROL0_0_CILA_THS_SETTLE_WOFFSET                 0x0
+#define CSI_PHY_CILA_CONTROL0_0_CILA_THS_SETTLE_DEFAULT                 _MK_MASK_CONST(0x2)
+#define CSI_PHY_CILA_CONTROL0_0_CILA_THS_SETTLE_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define CSI_PHY_CILA_CONTROL0_0_CILA_THS_SETTLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_PHY_CILA_CONTROL0_0_CILA_THS_SETTLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// The LP signals are sampled using csi_cil_clk.
+// Normally this happens on 2 clock edges assuming
+// the clock is running at least 50 Mhz.  If the
+// clock needs to run slower, then this bit can be
+// SET so that the sampling takes place on a single
+// edge (clock rate is 25 Mhz min).  This sampling
+// may not be as reliable so setting this bit is
+// not recommended.
+#define CSI_PHY_CILA_CONTROL0_0_CILA_SINGLE_SAMPLE_SHIFT                        _MK_SHIFT_CONST(4)
+#define CSI_PHY_CILA_CONTROL0_0_CILA_SINGLE_SAMPLE_FIELD                        (_MK_MASK_CONST(0x1) << CSI_PHY_CILA_CONTROL0_0_CILA_SINGLE_SAMPLE_SHIFT)
+#define CSI_PHY_CILA_CONTROL0_0_CILA_SINGLE_SAMPLE_RANGE                        4:4
+#define CSI_PHY_CILA_CONTROL0_0_CILA_SINGLE_SAMPLE_WOFFSET                      0x0
+#define CSI_PHY_CILA_CONTROL0_0_CILA_SINGLE_SAMPLE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_PHY_CILA_CONTROL0_0_CILA_SINGLE_SAMPLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CSI_PHY_CILA_CONTROL0_0_CILA_SINGLE_SAMPLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_PHY_CILA_CONTROL0_0_CILA_SINGLE_SAMPLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// The LP signals should sequence through LP11->LP01->LP00 state,
+// to indicate to CLOCK CIL about the mode switching to HS Rx mode.
+// In case Camera is enabled earlier than CIL , it is highly likely
+// that camera sends this control sequence sooner than cil can detect it.
+// Enabling this bit allows the CLOCK CIL to overlook the LP control sequence
+// and step in HS Rx mode directly looking at LP00 only.
+#define CSI_PHY_CILA_CONTROL0_0_CILA_BYPASS_LP_SEQ_SHIFT                        _MK_SHIFT_CONST(5)
+#define CSI_PHY_CILA_CONTROL0_0_CILA_BYPASS_LP_SEQ_FIELD                        (_MK_MASK_CONST(0x1) << CSI_PHY_CILA_CONTROL0_0_CILA_BYPASS_LP_SEQ_SHIFT)
+#define CSI_PHY_CILA_CONTROL0_0_CILA_BYPASS_LP_SEQ_RANGE                        5:5
+#define CSI_PHY_CILA_CONTROL0_0_CILA_BYPASS_LP_SEQ_WOFFSET                      0x0
+#define CSI_PHY_CILA_CONTROL0_0_CILA_BYPASS_LP_SEQ_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_PHY_CILA_CONTROL0_0_CILA_BYPASS_LP_SEQ_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CSI_PHY_CILA_CONTROL0_0_CILA_BYPASS_LP_SEQ_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_PHY_CILA_CONTROL0_0_CILA_BYPASS_LP_SEQ_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register CSI_PHY_CILB_CONTROL0_0  // CSI-B Phy and CIL Control
+#define CSI_PHY_CILB_CONTROL0_0                 _MK_ADDR_CONST(0x21c)
+#define CSI_PHY_CILB_CONTROL0_0_WORD_COUNT                      0x1
+#define CSI_PHY_CILB_CONTROL0_0_RESET_VAL                       _MK_MASK_CONST(0x2)
+#define CSI_PHY_CILB_CONTROL0_0_RESET_MASK                      _MK_MASK_CONST(0x3f)
+#define CSI_PHY_CILB_CONTROL0_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define CSI_PHY_CILB_CONTROL0_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define CSI_PHY_CILB_CONTROL0_0_READ_MASK                       _MK_MASK_CONST(0x3f)
+#define CSI_PHY_CILB_CONTROL0_0_WRITE_MASK                      _MK_MASK_CONST(0x3f)
+// When moving from LP mode to High Speed (LP11->LP01->LP00),
+// this setting determines how many  csicil clock cycles (72 MHz
+// lp clock cycles) to wait, after LP00,
+// before starting to look at the data.
+#define CSI_PHY_CILB_CONTROL0_0_CILB_THS_SETTLE_SHIFT                   _MK_SHIFT_CONST(0)
+#define CSI_PHY_CILB_CONTROL0_0_CILB_THS_SETTLE_FIELD                   (_MK_MASK_CONST(0xf) << CSI_PHY_CILB_CONTROL0_0_CILB_THS_SETTLE_SHIFT)
+#define CSI_PHY_CILB_CONTROL0_0_CILB_THS_SETTLE_RANGE                   3:0
+#define CSI_PHY_CILB_CONTROL0_0_CILB_THS_SETTLE_WOFFSET                 0x0
+#define CSI_PHY_CILB_CONTROL0_0_CILB_THS_SETTLE_DEFAULT                 _MK_MASK_CONST(0x2)
+#define CSI_PHY_CILB_CONTROL0_0_CILB_THS_SETTLE_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define CSI_PHY_CILB_CONTROL0_0_CILB_THS_SETTLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_PHY_CILB_CONTROL0_0_CILB_THS_SETTLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// see CILA_SINGLE_SAMPLE above
+#define CSI_PHY_CILB_CONTROL0_0_CILB_SINGLE_SAMPLE_SHIFT                        _MK_SHIFT_CONST(4)
+#define CSI_PHY_CILB_CONTROL0_0_CILB_SINGLE_SAMPLE_FIELD                        (_MK_MASK_CONST(0x1) << CSI_PHY_CILB_CONTROL0_0_CILB_SINGLE_SAMPLE_SHIFT)
+#define CSI_PHY_CILB_CONTROL0_0_CILB_SINGLE_SAMPLE_RANGE                        4:4
+#define CSI_PHY_CILB_CONTROL0_0_CILB_SINGLE_SAMPLE_WOFFSET                      0x0
+#define CSI_PHY_CILB_CONTROL0_0_CILB_SINGLE_SAMPLE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_PHY_CILB_CONTROL0_0_CILB_SINGLE_SAMPLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CSI_PHY_CILB_CONTROL0_0_CILB_SINGLE_SAMPLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_PHY_CILB_CONTROL0_0_CILB_SINGLE_SAMPLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// see CILA_BYPASS_LP_SEQ above
+#define CSI_PHY_CILB_CONTROL0_0_CILB_BYPASS_LP_SEQ_SHIFT                        _MK_SHIFT_CONST(5)
+#define CSI_PHY_CILB_CONTROL0_0_CILB_BYPASS_LP_SEQ_FIELD                        (_MK_MASK_CONST(0x1) << CSI_PHY_CILB_CONTROL0_0_CILB_BYPASS_LP_SEQ_SHIFT)
+#define CSI_PHY_CILB_CONTROL0_0_CILB_BYPASS_LP_SEQ_RANGE                        5:5
+#define CSI_PHY_CILB_CONTROL0_0_CILB_BYPASS_LP_SEQ_WOFFSET                      0x0
+#define CSI_PHY_CILB_CONTROL0_0_CILB_BYPASS_LP_SEQ_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_PHY_CILB_CONTROL0_0_CILB_BYPASS_LP_SEQ_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CSI_PHY_CILB_CONTROL0_0_CILB_BYPASS_LP_SEQ_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_PHY_CILB_CONTROL0_0_CILB_BYPASS_LP_SEQ_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Reserved address 541 [0x21d] 
+
+// Register CSI_CSI_PIXEL_PARSER_STATUS_0  // Pixel Parser Status
+// These status bits are cleared to
+// zero when its bit position is written with one. For
+// example write 0x2 to CSI_PIXEL_PARSER_STATUS will 
+// clear only PPA_ILL_WD_CNT.
+#define CSI_CSI_PIXEL_PARSER_STATUS_0                   _MK_ADDR_CONST(0x21e)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_WORD_COUNT                        0x1
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_READ_MASK                         _MK_MASK_CONST(0xcfffcfff)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+// Header Error Corrected, Set when a packet that was
+// processed by PPA has a single bit header error. This error
+// will be detected by the headers ECC, and corrected by
+// it if header error correction is enabled 
+// (CSI_A_HEADER_EC_ENABLE = 0). This flag will be set and 
+// the packet will be processed even if the error is not
+// corrected.
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_HDR_ERR_COR_SHIFT                     _MK_SHIFT_CONST(0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_HDR_ERR_COR_FIELD                     (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_HDR_ERR_COR_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_HDR_ERR_COR_RANGE                     0:0
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_HDR_ERR_COR_WOFFSET                   0x0
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_HDR_ERR_COR_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_HDR_ERR_COR_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_HDR_ERR_COR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_HDR_ERR_COR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Illegal Word Count, set when a line with a word count that
+// doesn't generate an integer number of pixels (Unused bytes
+// at the end of payload) is processed by PPA.
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_ILL_WD_CNT_SHIFT                      _MK_SHIFT_CONST(1)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_ILL_WD_CNT_FIELD                      (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_ILL_WD_CNT_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_ILL_WD_CNT_RANGE                      1:1
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_ILL_WD_CNT_WOFFSET                    0x0
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_ILL_WD_CNT_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_ILL_WD_CNT_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_ILL_WD_CNT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_ILL_WD_CNT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Short Line Processed, Set when a line with a payload that
+// is shorter than its packet header word count is processed
+// by PPA.
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SL_PROCESSED_SHIFT                    _MK_SHIFT_CONST(2)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SL_PROCESSED_FIELD                    (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SL_PROCESSED_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SL_PROCESSED_RANGE                    2:2
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SL_PROCESSED_WOFFSET                  0x0
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SL_PROCESSED_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SL_PROCESSED_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SL_PROCESSED_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SL_PROCESSED_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Short Line Packet Dropped, set when a in coming packet
+// gets dropped because the input FIFO level reaches
+// CSI_A_SKIP_PACKET_THRESHOLD when padding a short line.
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SL_PKT_DROPPED_SHIFT                  _MK_SHIFT_CONST(3)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SL_PKT_DROPPED_FIELD                  (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SL_PKT_DROPPED_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SL_PKT_DROPPED_RANGE                  3:3
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SL_PKT_DROPPED_WOFFSET                        0x0
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SL_PKT_DROPPED_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SL_PKT_DROPPED_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SL_PKT_DROPPED_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SL_PKT_DROPPED_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// PayLoad CRC Error, Set when a packet that was processed by
+// PPA had a payload CRC error.
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_PL_CRC_ERR_SHIFT                      _MK_SHIFT_CONST(4)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_PL_CRC_ERR_FIELD                      (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_PL_CRC_ERR_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_PL_CRC_ERR_RANGE                      4:4
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_PL_CRC_ERR_WOFFSET                    0x0
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_PL_CRC_ERR_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_PL_CRC_ERR_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_PL_CRC_ERR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_PL_CRC_ERR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// FIFO Overflow, set when the fifo that is feeding packets
+// to PPA overflows.
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_FIFO_OVRF_SHIFT                       _MK_SHIFT_CONST(5)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_FIFO_OVRF_FIELD                       (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_FIFO_OVRF_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_FIFO_OVRF_RANGE                       5:5
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_FIFO_OVRF_WOFFSET                     0x0
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_FIFO_OVRF_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_FIFO_OVRF_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_FIFO_OVRF_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_FIFO_OVRF_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Stream Error, set when the control output of PPA doesn't
+// follow the correct sequence. The correct sequence for CSI
+// is: SF -> (SL_DATA or EF), SL_DATA -> (DATA or EL_DATA),
+// DATA -> EL_DATA, EL_DATA -> (SL_DATA or EF), EF -> SF.
+// Stream Errors can be caused by receiving a corrupted
+// stream, or a CSI RTL bug.
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_STMERR_SHIFT                  _MK_SHIFT_CONST(6)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_STMERR_FIELD                  (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_STMERR_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_STMERR_RANGE                  6:6
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_STMERR_WOFFSET                        0x0
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_STMERR_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_STMERR_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_STMERR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_STMERR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Set when CSI-PPA receives a short frame. This bit gets
+// set even if CSI_PPA_PAD_FRAME specifies that short frames
+// are to be padded to the correct line length.
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SHORT_FRAME_SHIFT                     _MK_SHIFT_CONST(7)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SHORT_FRAME_FIELD                     (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SHORT_FRAME_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SHORT_FRAME_RANGE                     7:7
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SHORT_FRAME_WOFFSET                   0x0
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SHORT_FRAME_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SHORT_FRAME_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SHORT_FRAME_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SHORT_FRAME_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Set when CSI-PPA receives a SF when it is expecting an EF.
+// This happens when EF of the frame gets corrupted before arriving CSI.
+// CSI-PPA will insert a fake EF and the drop the current 
+// frame with Correct SF.
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_EXTRA_SF_SHIFT                        _MK_SHIFT_CONST(8)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_EXTRA_SF_FIELD                        (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_EXTRA_SF_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_EXTRA_SF_RANGE                        8:8
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_EXTRA_SF_WOFFSET                      0x0
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_EXTRA_SF_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_EXTRA_SF_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_EXTRA_SF_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_EXTRA_SF_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Set when CSI-PPA receives a request to output a line
+// that is not in the active part of the frame output. That
+// is after EF and before SF, or before start marker is found.
+// The interframe line will not be outputted by the Pixel 
+// Parser.
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_INTERFRAME_LINE_SHIFT                 _MK_SHIFT_CONST(9)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_INTERFRAME_LINE_FIELD                 (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_INTERFRAME_LINE_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_INTERFRAME_LINE_RANGE                 9:9
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_INTERFRAME_LINE_WOFFSET                       0x0
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_INTERFRAME_LINE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_INTERFRAME_LINE_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_INTERFRAME_LINE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_INTERFRAME_LINE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// PPA Spare Status bit. This bit will get set when Pixel Parser
+// A has a line timeout. Line timeout needs to be enabled by setting
+// PPA_ENABLE_LINE_TIMEOUT and programming PPA_MAX_CLOCKS for
+// the MAX clocks between lines.
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SPARE_STATUS_1_SHIFT                  _MK_SHIFT_CONST(10)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SPARE_STATUS_1_FIELD                  (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SPARE_STATUS_1_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SPARE_STATUS_1_RANGE                  10:10
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SPARE_STATUS_1_WOFFSET                        0x0
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SPARE_STATUS_1_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SPARE_STATUS_1_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SPARE_STATUS_1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SPARE_STATUS_1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// PPA Spare Status bit.
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SPARE_STATUS_2_SHIFT                  _MK_SHIFT_CONST(11)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SPARE_STATUS_2_FIELD                  (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SPARE_STATUS_2_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SPARE_STATUS_2_RANGE                  11:11
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SPARE_STATUS_2_WOFFSET                        0x0
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SPARE_STATUS_2_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SPARE_STATUS_2_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SPARE_STATUS_2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SPARE_STATUS_2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Uncorrectable Header Error, Set when header parser A
+// parses a header with a multi bit error. This error will
+// be detected by the headers ECC, but can't be corrected.
+// The packet will be discarded.
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_HPA_UNC_HDR_ERR_SHIFT                     _MK_SHIFT_CONST(14)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_HPA_UNC_HDR_ERR_FIELD                     (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_STATUS_0_HPA_UNC_HDR_ERR_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_HPA_UNC_HDR_ERR_RANGE                     14:14
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_HPA_UNC_HDR_ERR_WOFFSET                   0x0
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_HPA_UNC_HDR_ERR_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_HPA_UNC_HDR_ERR_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_HPA_UNC_HDR_ERR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_HPA_UNC_HDR_ERR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Uncorrectable Header Error, Set when header parser B
+// parses a header with a multi bit error. This error will
+// be detected by the headers ECC, but can't be corrected.
+// The packet will be discarded.a multi bit error. This error will
+// be detected by the headers ECC, but can't be corrected.
+// The packet will be discarded.
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_HPB_UNC_HDR_ERR_SHIFT                     _MK_SHIFT_CONST(15)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_HPB_UNC_HDR_ERR_FIELD                     (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_STATUS_0_HPB_UNC_HDR_ERR_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_HPB_UNC_HDR_ERR_RANGE                     15:15
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_HPB_UNC_HDR_ERR_WOFFSET                   0x0
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_HPB_UNC_HDR_ERR_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_HPB_UNC_HDR_ERR_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_HPB_UNC_HDR_ERR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_HPB_UNC_HDR_ERR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Header Error Corrected, set when a packet that was
+// processed by PPB has a single bit header error. This error
+// will be detected by the headers ECC, and corrected by
+// it if header error correction is enabled 
+// (CSI_B_HEADER_EC_ENABLE = 0). This flag will be set and 
+// the packet will be processed even if the error is not
+// corrected.
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_HDR_ERR_COR_SHIFT                     _MK_SHIFT_CONST(16)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_HDR_ERR_COR_FIELD                     (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_HDR_ERR_COR_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_HDR_ERR_COR_RANGE                     16:16
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_HDR_ERR_COR_WOFFSET                   0x0
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_HDR_ERR_COR_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_HDR_ERR_COR_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_HDR_ERR_COR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_HDR_ERR_COR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Illegal Word Count, set when a line with a word count that
+// doesn't generate an integer number of pixels (Unused bytes
+// at the end of payload) is processed by PPB.
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_ILL_WD_CNT_SHIFT                      _MK_SHIFT_CONST(17)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_ILL_WD_CNT_FIELD                      (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_ILL_WD_CNT_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_ILL_WD_CNT_RANGE                      17:17
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_ILL_WD_CNT_WOFFSET                    0x0
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_ILL_WD_CNT_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_ILL_WD_CNT_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_ILL_WD_CNT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_ILL_WD_CNT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Short Line Processed, Set when a line with a payload that
+// is shorter than its packet header word count is processed
+// by PPB.
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SL_PROCESSED_SHIFT                    _MK_SHIFT_CONST(18)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SL_PROCESSED_FIELD                    (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SL_PROCESSED_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SL_PROCESSED_RANGE                    18:18
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SL_PROCESSED_WOFFSET                  0x0
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SL_PROCESSED_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SL_PROCESSED_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SL_PROCESSED_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SL_PROCESSED_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Short Line Packet Dropped, set when a in coming packet
+// gets dropped because the input FIFO level reaches
+// CSI_B_SKIP_PACKET_THRESHOLD when padding a short line.
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SL_PKT_DROPPED_SHIFT                  _MK_SHIFT_CONST(19)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SL_PKT_DROPPED_FIELD                  (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SL_PKT_DROPPED_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SL_PKT_DROPPED_RANGE                  19:19
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SL_PKT_DROPPED_WOFFSET                        0x0
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SL_PKT_DROPPED_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SL_PKT_DROPPED_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SL_PKT_DROPPED_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SL_PKT_DROPPED_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// PayLoad CRC Error, Set when a packet that was processed
+// by PPB had a payload CRC error.
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_PL_CRC_ERR_SHIFT                      _MK_SHIFT_CONST(20)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_PL_CRC_ERR_FIELD                      (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_PL_CRC_ERR_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_PL_CRC_ERR_RANGE                      20:20
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_PL_CRC_ERR_WOFFSET                    0x0
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_PL_CRC_ERR_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_PL_CRC_ERR_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_PL_CRC_ERR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_PL_CRC_ERR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// FIFO Overflow, set when the fifo that is feeding packets
+// to PPB overflows.
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_FIFO_OVRF_SHIFT                       _MK_SHIFT_CONST(21)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_FIFO_OVRF_FIELD                       (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_FIFO_OVRF_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_FIFO_OVRF_RANGE                       21:21
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_FIFO_OVRF_WOFFSET                     0x0
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_FIFO_OVRF_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_FIFO_OVRF_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_FIFO_OVRF_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_FIFO_OVRF_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Stream Error, set when the control output of PPB doesn't
+// follow the correct sequence. The correct sequence for CSI
+// is: SF -> (SL_DATA or EF), SL_DATA -> (DATA or EL_DATA),
+// DATA -> EL_DATA, EL_DATA -> (SL_DATA or EF), EF -> SF.
+// Stream Errors can be caused by receiving a corrupted
+// stream, or a CSI RTL bug.
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_STMERR_SHIFT                  _MK_SHIFT_CONST(22)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_STMERR_FIELD                  (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_STMERR_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_STMERR_RANGE                  22:22
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_STMERR_WOFFSET                        0x0
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_STMERR_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_STMERR_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_STMERR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_STMERR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Set when CSI-PPB receives a short frame. This bit gets
+// set even if CSI_PPB_PAD_FRAME specifies that short frames
+// are to be padded to the correct line length.
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SHORT_FRAME_SHIFT                     _MK_SHIFT_CONST(23)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SHORT_FRAME_FIELD                     (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SHORT_FRAME_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SHORT_FRAME_RANGE                     23:23
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SHORT_FRAME_WOFFSET                   0x0
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SHORT_FRAME_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SHORT_FRAME_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SHORT_FRAME_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SHORT_FRAME_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Set when CSI-PPB receives a SF when it is expecting an EF. 
+// This happens when EF of the frame gets corrupted before arriving CSI.
+// CSI-PPB will insert a fake EF and the drop the current 
+// frame with Correct SF.
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_EXTRA_SF_SHIFT                        _MK_SHIFT_CONST(24)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_EXTRA_SF_FIELD                        (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_EXTRA_SF_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_EXTRA_SF_RANGE                        24:24
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_EXTRA_SF_WOFFSET                      0x0
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_EXTRA_SF_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_EXTRA_SF_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_EXTRA_SF_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_EXTRA_SF_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Set when CSI-PPB receives a request to output a line
+// that is not in the active part of the frame output. That
+// is after EF and before SF, or before start marker is found.
+// The interframe line will not be outputted by the Pixel 
+// Parser.
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_INTERFRAME_LINE_SHIFT                 _MK_SHIFT_CONST(25)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_INTERFRAME_LINE_FIELD                 (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_INTERFRAME_LINE_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_INTERFRAME_LINE_RANGE                 25:25
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_INTERFRAME_LINE_WOFFSET                       0x0
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_INTERFRAME_LINE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_INTERFRAME_LINE_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_INTERFRAME_LINE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_INTERFRAME_LINE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// PPB Spare Status bit. This bit will get set when Pixel Parser
+// B has a line timeout. Line timeout needs to be enabled by setting
+// PPB_ENABLE_LINE_TIMEOUT and programming PPB_MAX_CLOCKS for
+// the MAX clocks between lines.
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SPARE_STATUS_1_SHIFT                  _MK_SHIFT_CONST(26)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SPARE_STATUS_1_FIELD                  (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SPARE_STATUS_1_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SPARE_STATUS_1_RANGE                  26:26
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SPARE_STATUS_1_WOFFSET                        0x0
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SPARE_STATUS_1_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SPARE_STATUS_1_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SPARE_STATUS_1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SPARE_STATUS_1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// PPB Spare Status bit.
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SPARE_STATUS_2_SHIFT                  _MK_SHIFT_CONST(27)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SPARE_STATUS_2_FIELD                  (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SPARE_STATUS_2_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SPARE_STATUS_2_RANGE                  27:27
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SPARE_STATUS_2_WOFFSET                        0x0
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SPARE_STATUS_2_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SPARE_STATUS_2_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SPARE_STATUS_2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SPARE_STATUS_2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Uncorrectable Header Error, Set when the VI port header
+// parser parses a header with a multi bit error. This error
+// will be detected by the headers ECC, but can't be corrected.
+// The packet will be discarded.
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_HPV_UNC_HDR_ERR_SHIFT                     _MK_SHIFT_CONST(30)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_HPV_UNC_HDR_ERR_FIELD                     (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_STATUS_0_HPV_UNC_HDR_ERR_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_HPV_UNC_HDR_ERR_RANGE                     30:30
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_HPV_UNC_HDR_ERR_WOFFSET                   0x0
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_HPV_UNC_HDR_ERR_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_HPV_UNC_HDR_ERR_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_HPV_UNC_HDR_ERR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_HPV_UNC_HDR_ERR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Uncorrectable Header Error, Set when the Host port header
+// parser parses a header with a multi bit error. This error
+// will be detected by the headers ECC, but can't be corrected.
+// The packet will be discarded.
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_HPH_UNC_HDR_ERR_SHIFT                     _MK_SHIFT_CONST(31)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_HPH_UNC_HDR_ERR_FIELD                     (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_STATUS_0_HPH_UNC_HDR_ERR_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_HPH_UNC_HDR_ERR_RANGE                     31:31
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_HPH_UNC_HDR_ERR_WOFFSET                   0x0
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_HPH_UNC_HDR_ERR_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_HPH_UNC_HDR_ERR_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_HPH_UNC_HDR_ERR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_HPH_UNC_HDR_ERR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register CSI_CSI_CIL_STATUS_0  // CSI Control and Interface Logic Status
+// These status bits are cleared to
+// zero when its bit position is written with one. For
+// example write 0x2 to CSI_CIL_STATUS will clear only
+// CILA_SOT_MB_ERR.
+#define CSI_CSI_CIL_STATUS_0                    _MK_ADDR_CONST(0x21f)
+#define CSI_CSI_CIL_STATUS_0_WORD_COUNT                         0x1
+#define CSI_CSI_CIL_STATUS_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_READ_MASK                  _MK_MASK_CONST(0x1ff81ff)
+#define CSI_CSI_CIL_STATUS_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
+// Start of Transmission Single Bit Error, set when CIL-A 
+// detects a single bit error in one of the 
+// packets Start of Transmission bytes. The packet will be
+// sent to the CSI-A for processing.
+#define CSI_CSI_CIL_STATUS_0_CILA_SOT_SB_ERR_SHIFT                      _MK_SHIFT_CONST(0)
+#define CSI_CSI_CIL_STATUS_0_CILA_SOT_SB_ERR_FIELD                      (_MK_MASK_CONST(0x1) << CSI_CSI_CIL_STATUS_0_CILA_SOT_SB_ERR_SHIFT)
+#define CSI_CSI_CIL_STATUS_0_CILA_SOT_SB_ERR_RANGE                      0:0
+#define CSI_CSI_CIL_STATUS_0_CILA_SOT_SB_ERR_WOFFSET                    0x0
+#define CSI_CSI_CIL_STATUS_0_CILA_SOT_SB_ERR_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILA_SOT_SB_ERR_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILA_SOT_SB_ERR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILA_SOT_SB_ERR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Start of Transmission Multi Bit Error, set when CIL-A
+// detects a multi bit start of transmission byte error in
+// one of the packets SOT bytes. The packet will be discarded.
+#define CSI_CSI_CIL_STATUS_0_CILA_SOT_MB_ERR_SHIFT                      _MK_SHIFT_CONST(1)
+#define CSI_CSI_CIL_STATUS_0_CILA_SOT_MB_ERR_FIELD                      (_MK_MASK_CONST(0x1) << CSI_CSI_CIL_STATUS_0_CILA_SOT_MB_ERR_SHIFT)
+#define CSI_CSI_CIL_STATUS_0_CILA_SOT_MB_ERR_RANGE                      1:1
+#define CSI_CSI_CIL_STATUS_0_CILA_SOT_MB_ERR_WOFFSET                    0x0
+#define CSI_CSI_CIL_STATUS_0_CILA_SOT_MB_ERR_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILA_SOT_MB_ERR_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILA_SOT_MB_ERR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILA_SOT_MB_ERR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Sync Escape Error, set when CIL-A detects that the wrong 
+// (non-multiple of 8) number of bits have been received for
+// an Escape Command, or Data Byte.
+#define CSI_CSI_CIL_STATUS_0_CILA_SYNC_ESC_ERR_SHIFT                    _MK_SHIFT_CONST(2)
+#define CSI_CSI_CIL_STATUS_0_CILA_SYNC_ESC_ERR_FIELD                    (_MK_MASK_CONST(0x1) << CSI_CSI_CIL_STATUS_0_CILA_SYNC_ESC_ERR_SHIFT)
+#define CSI_CSI_CIL_STATUS_0_CILA_SYNC_ESC_ERR_RANGE                    2:2
+#define CSI_CSI_CIL_STATUS_0_CILA_SYNC_ESC_ERR_WOFFSET                  0x0
+#define CSI_CSI_CIL_STATUS_0_CILA_SYNC_ESC_ERR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILA_SYNC_ESC_ERR_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILA_SYNC_ESC_ERR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILA_SYNC_ESC_ERR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Escape Mode Entry Error, set when CIL-A detects an escape
+// mode entry error. The Escape mode command byte will not be
+// received.
+#define CSI_CSI_CIL_STATUS_0_CILA_ESC_ENTRY_ERR_SHIFT                   _MK_SHIFT_CONST(3)
+#define CSI_CSI_CIL_STATUS_0_CILA_ESC_ENTRY_ERR_FIELD                   (_MK_MASK_CONST(0x1) << CSI_CSI_CIL_STATUS_0_CILA_ESC_ENTRY_ERR_SHIFT)
+#define CSI_CSI_CIL_STATUS_0_CILA_ESC_ENTRY_ERR_RANGE                   3:3
+#define CSI_CSI_CIL_STATUS_0_CILA_ESC_ENTRY_ERR_WOFFSET                 0x0
+#define CSI_CSI_CIL_STATUS_0_CILA_ESC_ENTRY_ERR_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILA_ESC_ENTRY_ERR_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILA_ESC_ENTRY_ERR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILA_ESC_ENTRY_ERR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Control Error, set when CIL-A detects LP state 01 or 10
+// followed by a stop state (LP11) instead of transitioning
+// into the Escape mode or Turn Around mode (LP00).
+#define CSI_CSI_CIL_STATUS_0_CILA_CTRL_ERR_SHIFT                        _MK_SHIFT_CONST(4)
+#define CSI_CSI_CIL_STATUS_0_CILA_CTRL_ERR_FIELD                        (_MK_MASK_CONST(0x1) << CSI_CSI_CIL_STATUS_0_CILA_CTRL_ERR_SHIFT)
+#define CSI_CSI_CIL_STATUS_0_CILA_CTRL_ERR_RANGE                        4:4
+#define CSI_CSI_CIL_STATUS_0_CILA_CTRL_ERR_WOFFSET                      0x0
+#define CSI_CSI_CIL_STATUS_0_CILA_CTRL_ERR_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILA_CTRL_ERR_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILA_CTRL_ERR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILA_CTRL_ERR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Escape Mode Command Received, set when CIL-A receives an
+// Escape Mode Command byte. The Command Byte can be read 
+// from bits 7-0 of ESCAPE_MODE_COMMAND.
+#define CSI_CSI_CIL_STATUS_0_CILA_ESC_CMD_REC_SHIFT                     _MK_SHIFT_CONST(5)
+#define CSI_CSI_CIL_STATUS_0_CILA_ESC_CMD_REC_FIELD                     (_MK_MASK_CONST(0x1) << CSI_CSI_CIL_STATUS_0_CILA_ESC_CMD_REC_SHIFT)
+#define CSI_CSI_CIL_STATUS_0_CILA_ESC_CMD_REC_RANGE                     5:5
+#define CSI_CSI_CIL_STATUS_0_CILA_ESC_CMD_REC_WOFFSET                   0x0
+#define CSI_CSI_CIL_STATUS_0_CILA_ESC_CMD_REC_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILA_ESC_CMD_REC_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILA_ESC_CMD_REC_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILA_ESC_CMD_REC_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Escape Mode Data Received, set when CIL-A receives an
+// Escape Mode Data byte. The Data Byte can be read 
+// from bits 7-0 of ESCAPE_MODE_DATA. This status bit will
+// will also be cleared when CILA_ESC_CMD_REC is set.
+#define CSI_CSI_CIL_STATUS_0_CILA_ESC_DATA_REC_SHIFT                    _MK_SHIFT_CONST(6)
+#define CSI_CSI_CIL_STATUS_0_CILA_ESC_DATA_REC_FIELD                    (_MK_MASK_CONST(0x1) << CSI_CSI_CIL_STATUS_0_CILA_ESC_DATA_REC_SHIFT)
+#define CSI_CSI_CIL_STATUS_0_CILA_ESC_DATA_REC_RANGE                    6:6
+#define CSI_CSI_CIL_STATUS_0_CILA_ESC_DATA_REC_WOFFSET                  0x0
+#define CSI_CSI_CIL_STATUS_0_CILA_ESC_DATA_REC_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILA_ESC_DATA_REC_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILA_ESC_DATA_REC_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILA_ESC_DATA_REC_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// CILA Spare Status bit.
+#define CSI_CSI_CIL_STATUS_0_CILA_SPARE_STATUS_1_SHIFT                  _MK_SHIFT_CONST(7)
+#define CSI_CSI_CIL_STATUS_0_CILA_SPARE_STATUS_1_FIELD                  (_MK_MASK_CONST(0x1) << CSI_CSI_CIL_STATUS_0_CILA_SPARE_STATUS_1_SHIFT)
+#define CSI_CSI_CIL_STATUS_0_CILA_SPARE_STATUS_1_RANGE                  7:7
+#define CSI_CSI_CIL_STATUS_0_CILA_SPARE_STATUS_1_WOFFSET                        0x0
+#define CSI_CSI_CIL_STATUS_0_CILA_SPARE_STATUS_1_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILA_SPARE_STATUS_1_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILA_SPARE_STATUS_1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILA_SPARE_STATUS_1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// CILA Spare Status bit.
+#define CSI_CSI_CIL_STATUS_0_CILA_SPARE_STATUS_2_SHIFT                  _MK_SHIFT_CONST(8)
+#define CSI_CSI_CIL_STATUS_0_CILA_SPARE_STATUS_2_FIELD                  (_MK_MASK_CONST(0x1) << CSI_CSI_CIL_STATUS_0_CILA_SPARE_STATUS_2_SHIFT)
+#define CSI_CSI_CIL_STATUS_0_CILA_SPARE_STATUS_2_RANGE                  8:8
+#define CSI_CSI_CIL_STATUS_0_CILA_SPARE_STATUS_2_WOFFSET                        0x0
+#define CSI_CSI_CIL_STATUS_0_CILA_SPARE_STATUS_2_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILA_SPARE_STATUS_2_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILA_SPARE_STATUS_2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILA_SPARE_STATUS_2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// MIPI Auto Calibrate done, set when the auto calibrate 
+// sequence for MIPI pad bricks is done.
+#define CSI_CSI_CIL_STATUS_0_MIPI_AUTO_CAL_DONE_SHIFT                   _MK_SHIFT_CONST(15)
+#define CSI_CSI_CIL_STATUS_0_MIPI_AUTO_CAL_DONE_FIELD                   (_MK_MASK_CONST(0x1) << CSI_CSI_CIL_STATUS_0_MIPI_AUTO_CAL_DONE_SHIFT)
+#define CSI_CSI_CIL_STATUS_0_MIPI_AUTO_CAL_DONE_RANGE                   15:15
+#define CSI_CSI_CIL_STATUS_0_MIPI_AUTO_CAL_DONE_WOFFSET                 0x0
+#define CSI_CSI_CIL_STATUS_0_MIPI_AUTO_CAL_DONE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_MIPI_AUTO_CAL_DONE_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_MIPI_AUTO_CAL_DONE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_MIPI_AUTO_CAL_DONE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Start of Transmission Single Bit Error, set when CIL-B
+// detects a single bit error in one of the packets start
+// of transmission bytes. The packet will be sent to CSI-B
+// for processing.
+#define CSI_CSI_CIL_STATUS_0_CILB_SOT_SB_ERR_SHIFT                      _MK_SHIFT_CONST(16)
+#define CSI_CSI_CIL_STATUS_0_CILB_SOT_SB_ERR_FIELD                      (_MK_MASK_CONST(0x1) << CSI_CSI_CIL_STATUS_0_CILB_SOT_SB_ERR_SHIFT)
+#define CSI_CSI_CIL_STATUS_0_CILB_SOT_SB_ERR_RANGE                      16:16
+#define CSI_CSI_CIL_STATUS_0_CILB_SOT_SB_ERR_WOFFSET                    0x0
+#define CSI_CSI_CIL_STATUS_0_CILB_SOT_SB_ERR_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILB_SOT_SB_ERR_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILB_SOT_SB_ERR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILB_SOT_SB_ERR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Start of Transmission Multi Bit Error, set when CIL-B
+// detects a multi bit start of transmission byte error in
+// one of the packets SOT bytes. The packet will be discarded.
+#define CSI_CSI_CIL_STATUS_0_CILB_SOT_MB_ERR_SHIFT                      _MK_SHIFT_CONST(17)
+#define CSI_CSI_CIL_STATUS_0_CILB_SOT_MB_ERR_FIELD                      (_MK_MASK_CONST(0x1) << CSI_CSI_CIL_STATUS_0_CILB_SOT_MB_ERR_SHIFT)
+#define CSI_CSI_CIL_STATUS_0_CILB_SOT_MB_ERR_RANGE                      17:17
+#define CSI_CSI_CIL_STATUS_0_CILB_SOT_MB_ERR_WOFFSET                    0x0
+#define CSI_CSI_CIL_STATUS_0_CILB_SOT_MB_ERR_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILB_SOT_MB_ERR_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILB_SOT_MB_ERR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILB_SOT_MB_ERR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Sync Escape Error, set when CIL-B detects that the wrong 
+// (non-multiple of 8) number of bits have been received for
+// an Escape Command, or Data Byte.
+#define CSI_CSI_CIL_STATUS_0_CILB_SYNC_ESC_ERR_SHIFT                    _MK_SHIFT_CONST(18)
+#define CSI_CSI_CIL_STATUS_0_CILB_SYNC_ESC_ERR_FIELD                    (_MK_MASK_CONST(0x1) << CSI_CSI_CIL_STATUS_0_CILB_SYNC_ESC_ERR_SHIFT)
+#define CSI_CSI_CIL_STATUS_0_CILB_SYNC_ESC_ERR_RANGE                    18:18
+#define CSI_CSI_CIL_STATUS_0_CILB_SYNC_ESC_ERR_WOFFSET                  0x0
+#define CSI_CSI_CIL_STATUS_0_CILB_SYNC_ESC_ERR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILB_SYNC_ESC_ERR_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILB_SYNC_ESC_ERR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILB_SYNC_ESC_ERR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Escape Mode Entry Error, set when CIL-B detects an Escape
+// Mode Entry Error. The Escape mode command byte will not be
+// received.
+#define CSI_CSI_CIL_STATUS_0_CILB_ESC_ENTRY_ERR_SHIFT                   _MK_SHIFT_CONST(19)
+#define CSI_CSI_CIL_STATUS_0_CILB_ESC_ENTRY_ERR_FIELD                   (_MK_MASK_CONST(0x1) << CSI_CSI_CIL_STATUS_0_CILB_ESC_ENTRY_ERR_SHIFT)
+#define CSI_CSI_CIL_STATUS_0_CILB_ESC_ENTRY_ERR_RANGE                   19:19
+#define CSI_CSI_CIL_STATUS_0_CILB_ESC_ENTRY_ERR_WOFFSET                 0x0
+#define CSI_CSI_CIL_STATUS_0_CILB_ESC_ENTRY_ERR_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILB_ESC_ENTRY_ERR_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILB_ESC_ENTRY_ERR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILB_ESC_ENTRY_ERR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Control Error, set when CIL-B detects LP state 01 or 10
+// followed by a stop state (LP11) instead of transitioning
+// into the Escape mode or Turn Around mode (LP00)..
+#define CSI_CSI_CIL_STATUS_0_CILB_CTRL_ERR_SHIFT                        _MK_SHIFT_CONST(20)
+#define CSI_CSI_CIL_STATUS_0_CILB_CTRL_ERR_FIELD                        (_MK_MASK_CONST(0x1) << CSI_CSI_CIL_STATUS_0_CILB_CTRL_ERR_SHIFT)
+#define CSI_CSI_CIL_STATUS_0_CILB_CTRL_ERR_RANGE                        20:20
+#define CSI_CSI_CIL_STATUS_0_CILB_CTRL_ERR_WOFFSET                      0x0
+#define CSI_CSI_CIL_STATUS_0_CILB_CTRL_ERR_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILB_CTRL_ERR_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILB_CTRL_ERR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILB_CTRL_ERR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Escape Mode Command Received, set when CIL-B receives an
+// Escape Mode Command byte. The Command Byte can be read 
+// from bits 23-16 of ESCAPE_MODE_COMMAND.
+#define CSI_CSI_CIL_STATUS_0_CILB_ESC_CMD_REC_SHIFT                     _MK_SHIFT_CONST(21)
+#define CSI_CSI_CIL_STATUS_0_CILB_ESC_CMD_REC_FIELD                     (_MK_MASK_CONST(0x1) << CSI_CSI_CIL_STATUS_0_CILB_ESC_CMD_REC_SHIFT)
+#define CSI_CSI_CIL_STATUS_0_CILB_ESC_CMD_REC_RANGE                     21:21
+#define CSI_CSI_CIL_STATUS_0_CILB_ESC_CMD_REC_WOFFSET                   0x0
+#define CSI_CSI_CIL_STATUS_0_CILB_ESC_CMD_REC_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILB_ESC_CMD_REC_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILB_ESC_CMD_REC_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILB_ESC_CMD_REC_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Escape Mode Data Received, set when CIL-B receives an
+// Escape Mode Data byte. The Data Byte can be read 
+// from bits 23-16 of ESCAPE_MODE_DATA. This status bit will
+// will also be cleared when CILB_ESC_CMD_REC is set.
+#define CSI_CSI_CIL_STATUS_0_CILB_ESC_DATA_REC_SHIFT                    _MK_SHIFT_CONST(22)
+#define CSI_CSI_CIL_STATUS_0_CILB_ESC_DATA_REC_FIELD                    (_MK_MASK_CONST(0x1) << CSI_CSI_CIL_STATUS_0_CILB_ESC_DATA_REC_SHIFT)
+#define CSI_CSI_CIL_STATUS_0_CILB_ESC_DATA_REC_RANGE                    22:22
+#define CSI_CSI_CIL_STATUS_0_CILB_ESC_DATA_REC_WOFFSET                  0x0
+#define CSI_CSI_CIL_STATUS_0_CILB_ESC_DATA_REC_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILB_ESC_DATA_REC_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILB_ESC_DATA_REC_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILB_ESC_DATA_REC_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// CILB Spare Status bit.
+#define CSI_CSI_CIL_STATUS_0_CILB_SPARE_STATUS_1_SHIFT                  _MK_SHIFT_CONST(23)
+#define CSI_CSI_CIL_STATUS_0_CILB_SPARE_STATUS_1_FIELD                  (_MK_MASK_CONST(0x1) << CSI_CSI_CIL_STATUS_0_CILB_SPARE_STATUS_1_SHIFT)
+#define CSI_CSI_CIL_STATUS_0_CILB_SPARE_STATUS_1_RANGE                  23:23
+#define CSI_CSI_CIL_STATUS_0_CILB_SPARE_STATUS_1_WOFFSET                        0x0
+#define CSI_CSI_CIL_STATUS_0_CILB_SPARE_STATUS_1_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILB_SPARE_STATUS_1_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILB_SPARE_STATUS_1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILB_SPARE_STATUS_1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// CILB Spare Status bit.
+#define CSI_CSI_CIL_STATUS_0_CILB_SPARE_STATUS_2_SHIFT                  _MK_SHIFT_CONST(24)
+#define CSI_CSI_CIL_STATUS_0_CILB_SPARE_STATUS_2_FIELD                  (_MK_MASK_CONST(0x1) << CSI_CSI_CIL_STATUS_0_CILB_SPARE_STATUS_2_SHIFT)
+#define CSI_CSI_CIL_STATUS_0_CILB_SPARE_STATUS_2_RANGE                  24:24
+#define CSI_CSI_CIL_STATUS_0_CILB_SPARE_STATUS_2_WOFFSET                        0x0
+#define CSI_CSI_CIL_STATUS_0_CILB_SPARE_STATUS_2_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILB_SPARE_STATUS_2_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILB_SPARE_STATUS_2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILB_SPARE_STATUS_2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0  // CSI Pixel Parser Interrupt Mask
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0                   _MK_ADDR_CONST(0x220)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_WORD_COUNT                        0x1
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_RESET_MASK                        _MK_MASK_CONST(0xcfffcfff)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_READ_MASK                         _MK_MASK_CONST(0xcfffcfff)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_WRITE_MASK                        _MK_MASK_CONST(0xcfffcfff)
+// Interrupt Mask for PPA_HDR_ERR_COR. Generate an interrupt when PPA_HDR_ERR_COR
+// is set.
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_HDR_ERR_COR_INT_MASK_SHIFT                    _MK_SHIFT_CONST(0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_HDR_ERR_COR_INT_MASK_FIELD                    (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_HDR_ERR_COR_INT_MASK_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_HDR_ERR_COR_INT_MASK_RANGE                    0:0
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_HDR_ERR_COR_INT_MASK_WOFFSET                  0x0
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_HDR_ERR_COR_INT_MASK_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_HDR_ERR_COR_INT_MASK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_HDR_ERR_COR_INT_MASK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_HDR_ERR_COR_INT_MASK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_HDR_ERR_COR_INT_MASK_DISABLED                 _MK_ENUM_CONST(0)    // // Don't generate an interrupt when PPA_HDR_ERR_COR
+// is set.
+
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_HDR_ERR_COR_INT_MASK_ENABLED                  _MK_ENUM_CONST(1)
+
+// Interrupt Mask for PPA_ILL_WD_CNT. Generate an interrupt when PPA_ILL_WD_CNT
+// is set.
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_ILL_WD_CNT_INT_MASK_SHIFT                     _MK_SHIFT_CONST(1)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_ILL_WD_CNT_INT_MASK_FIELD                     (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_ILL_WD_CNT_INT_MASK_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_ILL_WD_CNT_INT_MASK_RANGE                     1:1
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_ILL_WD_CNT_INT_MASK_WOFFSET                   0x0
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_ILL_WD_CNT_INT_MASK_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_ILL_WD_CNT_INT_MASK_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_ILL_WD_CNT_INT_MASK_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_ILL_WD_CNT_INT_MASK_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_ILL_WD_CNT_INT_MASK_DISABLED                  _MK_ENUM_CONST(0)    // // Don't generate an interrupt when PPA_ILL_WD_CNT
+// is set.
+
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_ILL_WD_CNT_INT_MASK_ENABLED                   _MK_ENUM_CONST(1)
+
+// Interrupt Mask for PPA_SL_PROCESSED. Generate an interrupt when PPA_SL_PROCESSED
+// is set.
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SL_PROCESSED_INT_MASK_SHIFT                   _MK_SHIFT_CONST(2)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SL_PROCESSED_INT_MASK_FIELD                   (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SL_PROCESSED_INT_MASK_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SL_PROCESSED_INT_MASK_RANGE                   2:2
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SL_PROCESSED_INT_MASK_WOFFSET                 0x0
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SL_PROCESSED_INT_MASK_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SL_PROCESSED_INT_MASK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SL_PROCESSED_INT_MASK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SL_PROCESSED_INT_MASK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SL_PROCESSED_INT_MASK_DISABLED                        _MK_ENUM_CONST(0)    // // Don't generate an interrupt when PPA_SL_PROCESSED
+// is set.
+
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SL_PROCESSED_INT_MASK_ENABLED                 _MK_ENUM_CONST(1)
+
+// Interrupt Mask for PPA_SL_PKT_DROPPED. Generate an interrupt when PPA_SL_PKT_DROPPED
+// is set.
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SL_PKT_DROPPED_INT_MASK_SHIFT                 _MK_SHIFT_CONST(3)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SL_PKT_DROPPED_INT_MASK_FIELD                 (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SL_PKT_DROPPED_INT_MASK_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SL_PKT_DROPPED_INT_MASK_RANGE                 3:3
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SL_PKT_DROPPED_INT_MASK_WOFFSET                       0x0
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SL_PKT_DROPPED_INT_MASK_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SL_PKT_DROPPED_INT_MASK_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SL_PKT_DROPPED_INT_MASK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SL_PKT_DROPPED_INT_MASK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SL_PKT_DROPPED_INT_MASK_DISABLED                      _MK_ENUM_CONST(0)    // // Don't generate an interrupt when PPA_SL_PKT_DROPPED
+// is set.
+
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SL_PKT_DROPPED_INT_MASK_ENABLED                       _MK_ENUM_CONST(1)
+
+// Interrupt Mask for PPA_PL_CRC_ERR. Generate an interrupt when PPA_PL_CRC_ERR
+// is set.
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_PL_CRC_ERR_INT_MASK_SHIFT                     _MK_SHIFT_CONST(4)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_PL_CRC_ERR_INT_MASK_FIELD                     (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_PL_CRC_ERR_INT_MASK_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_PL_CRC_ERR_INT_MASK_RANGE                     4:4
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_PL_CRC_ERR_INT_MASK_WOFFSET                   0x0
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_PL_CRC_ERR_INT_MASK_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_PL_CRC_ERR_INT_MASK_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_PL_CRC_ERR_INT_MASK_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_PL_CRC_ERR_INT_MASK_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_PL_CRC_ERR_INT_MASK_DISABLED                  _MK_ENUM_CONST(0)    // // Don't generate an interrupt when PPA_PL_CRC_ERR
+// is set.
+
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_PL_CRC_ERR_INT_MASK_ENABLED                   _MK_ENUM_CONST(1)
+
+// Interrupt Mask for PPA_FIFO_OVRF. Generate an interrupt when PPA_FIFO_OVRF
+// is set.
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_FIFO_OVRF_INT_MASK_SHIFT                      _MK_SHIFT_CONST(5)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_FIFO_OVRF_INT_MASK_FIELD                      (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_FIFO_OVRF_INT_MASK_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_FIFO_OVRF_INT_MASK_RANGE                      5:5
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_FIFO_OVRF_INT_MASK_WOFFSET                    0x0
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_FIFO_OVRF_INT_MASK_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_FIFO_OVRF_INT_MASK_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_FIFO_OVRF_INT_MASK_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_FIFO_OVRF_INT_MASK_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_FIFO_OVRF_INT_MASK_DISABLED                   _MK_ENUM_CONST(0)    // // Don't generate an interrupt when PPA_FIFO_OVRF
+// is set.
+
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_FIFO_OVRF_INT_MASK_ENABLED                    _MK_ENUM_CONST(1)
+
+// Interrupt Mask for PPA_STMERR. Generate an interrupt when PPA_STMERR
+// is set.
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_STMERR_INT_MASK_SHIFT                 _MK_SHIFT_CONST(6)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_STMERR_INT_MASK_FIELD                 (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_STMERR_INT_MASK_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_STMERR_INT_MASK_RANGE                 6:6
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_STMERR_INT_MASK_WOFFSET                       0x0
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_STMERR_INT_MASK_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_STMERR_INT_MASK_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_STMERR_INT_MASK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_STMERR_INT_MASK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_STMERR_INT_MASK_DISABLED                      _MK_ENUM_CONST(0)    // // Don't generate an interrupt when PPA_STMERR
+// is set.
+
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_STMERR_INT_MASK_ENABLED                       _MK_ENUM_CONST(1)
+
+// Interrupt Mask for PPA_SHORT_FRAME. Generate an interrupt when PPA_SHORT_FRAME
+// is set.
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SHORT_FRAME_INT_MASK_SHIFT                    _MK_SHIFT_CONST(7)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SHORT_FRAME_INT_MASK_FIELD                    (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SHORT_FRAME_INT_MASK_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SHORT_FRAME_INT_MASK_RANGE                    7:7
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SHORT_FRAME_INT_MASK_WOFFSET                  0x0
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SHORT_FRAME_INT_MASK_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SHORT_FRAME_INT_MASK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SHORT_FRAME_INT_MASK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SHORT_FRAME_INT_MASK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SHORT_FRAME_INT_MASK_DISABLED                 _MK_ENUM_CONST(0)    // // Don't generate an interrupt when PPA_SHORT_FRAME
+// is set.
+
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SHORT_FRAME_INT_MASK_ENABLED                  _MK_ENUM_CONST(1)
+
+// Interrupt Mask for PPA_EXTRA_SF. Generate an interrupt when PPA_EXTRA_SF
+// is set.
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_EXTRA_SF_INT_MASK_SHIFT                       _MK_SHIFT_CONST(8)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_EXTRA_SF_INT_MASK_FIELD                       (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_EXTRA_SF_INT_MASK_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_EXTRA_SF_INT_MASK_RANGE                       8:8
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_EXTRA_SF_INT_MASK_WOFFSET                     0x0
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_EXTRA_SF_INT_MASK_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_EXTRA_SF_INT_MASK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_EXTRA_SF_INT_MASK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_EXTRA_SF_INT_MASK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_EXTRA_SF_INT_MASK_DISABLED                    _MK_ENUM_CONST(0)    // // Don't generate an interrupt when PPA_EXTRA_SF
+// is set.
+
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_EXTRA_SF_INT_MASK_ENABLED                     _MK_ENUM_CONST(1)
+
+// Interrupt Mask for PPA_INTERFRAME_LINE. Generate an interrupt when PPA_INTERFRAME_LINE
+// is set.
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_INTERFRAME_LINE_INT_MASK_SHIFT                        _MK_SHIFT_CONST(9)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_INTERFRAME_LINE_INT_MASK_FIELD                        (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_INTERFRAME_LINE_INT_MASK_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_INTERFRAME_LINE_INT_MASK_RANGE                        9:9
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_INTERFRAME_LINE_INT_MASK_WOFFSET                      0x0
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_INTERFRAME_LINE_INT_MASK_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_INTERFRAME_LINE_INT_MASK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_INTERFRAME_LINE_INT_MASK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_INTERFRAME_LINE_INT_MASK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_INTERFRAME_LINE_INT_MASK_DISABLED                     _MK_ENUM_CONST(0)    // // Don't generate an interrupt when PPA_INTERFRAME_LINE
+// is set.
+
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_INTERFRAME_LINE_INT_MASK_ENABLED                      _MK_ENUM_CONST(1)
+
+// Interrupt Mask for PPA_SPARE_STATUS_1. Generate an interrupt when PPA_SPARE_STATUS_1
+// is set.
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SPARE_STATUS_1_INT_MASK_SHIFT                 _MK_SHIFT_CONST(10)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SPARE_STATUS_1_INT_MASK_FIELD                 (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SPARE_STATUS_1_INT_MASK_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SPARE_STATUS_1_INT_MASK_RANGE                 10:10
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SPARE_STATUS_1_INT_MASK_WOFFSET                       0x0
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SPARE_STATUS_1_INT_MASK_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SPARE_STATUS_1_INT_MASK_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SPARE_STATUS_1_INT_MASK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SPARE_STATUS_1_INT_MASK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SPARE_STATUS_1_INT_MASK_DISABLED                      _MK_ENUM_CONST(0)    // // Don't generate an interrupt when PPA_SPARE_STATUS_1
+// is set.
+
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SPARE_STATUS_1_INT_MASK_ENABLED                       _MK_ENUM_CONST(1)
+
+// Interrupt Mask for PPA_SPARE_STATUS_2. Generate an interrupt when PPA_SPARE_STATUS_2
+// is set.
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SPARE_STATUS_2_INT_MASK_SHIFT                 _MK_SHIFT_CONST(11)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SPARE_STATUS_2_INT_MASK_FIELD                 (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SPARE_STATUS_2_INT_MASK_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SPARE_STATUS_2_INT_MASK_RANGE                 11:11
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SPARE_STATUS_2_INT_MASK_WOFFSET                       0x0
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SPARE_STATUS_2_INT_MASK_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SPARE_STATUS_2_INT_MASK_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SPARE_STATUS_2_INT_MASK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SPARE_STATUS_2_INT_MASK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SPARE_STATUS_2_INT_MASK_DISABLED                      _MK_ENUM_CONST(0)    // // Don't generate an interrupt when PPA_SPARE_STATUS_2
+// is set.
+
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SPARE_STATUS_2_INT_MASK_ENABLED                       _MK_ENUM_CONST(1)
+
+// Interrupt Mask for HPA_UNC_HDR_ERR. Generate an interrupt when HPA_UNC_HDR_ERR
+// is set.
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPA_UNC_HDR_ERR_INT_MASK_SHIFT                    _MK_SHIFT_CONST(14)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPA_UNC_HDR_ERR_INT_MASK_FIELD                    (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPA_UNC_HDR_ERR_INT_MASK_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPA_UNC_HDR_ERR_INT_MASK_RANGE                    14:14
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPA_UNC_HDR_ERR_INT_MASK_WOFFSET                  0x0
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPA_UNC_HDR_ERR_INT_MASK_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPA_UNC_HDR_ERR_INT_MASK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPA_UNC_HDR_ERR_INT_MASK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPA_UNC_HDR_ERR_INT_MASK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPA_UNC_HDR_ERR_INT_MASK_DISABLED                 _MK_ENUM_CONST(0)    // // Don't generate an interrupt when HPA_UNC_HDR_ERR
+// is set.
+
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPA_UNC_HDR_ERR_INT_MASK_ENABLED                  _MK_ENUM_CONST(1)
+
+// Interrupt Mask for HPB_UNC_HDR_ERR. Generate an interrupt when HPB_UNC_HDR_ERR
+// is set.
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPB_UNC_HDR_ERR_INT_MASK_SHIFT                    _MK_SHIFT_CONST(15)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPB_UNC_HDR_ERR_INT_MASK_FIELD                    (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPB_UNC_HDR_ERR_INT_MASK_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPB_UNC_HDR_ERR_INT_MASK_RANGE                    15:15
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPB_UNC_HDR_ERR_INT_MASK_WOFFSET                  0x0
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPB_UNC_HDR_ERR_INT_MASK_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPB_UNC_HDR_ERR_INT_MASK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPB_UNC_HDR_ERR_INT_MASK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPB_UNC_HDR_ERR_INT_MASK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPB_UNC_HDR_ERR_INT_MASK_DISABLED                 _MK_ENUM_CONST(0)    // // Don't generate an interrupt when HPB_UNC_HDR_ERR
+// is set.
+
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPB_UNC_HDR_ERR_INT_MASK_ENABLED                  _MK_ENUM_CONST(1)
+
+// Interrupt Mask for PPB_HDR_ERR_COR. Generate an interrupt when PPB_HDR_ERR_COR
+// is set.
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_HDR_ERR_COR_INT_MASK_SHIFT                    _MK_SHIFT_CONST(16)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_HDR_ERR_COR_INT_MASK_FIELD                    (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_HDR_ERR_COR_INT_MASK_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_HDR_ERR_COR_INT_MASK_RANGE                    16:16
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_HDR_ERR_COR_INT_MASK_WOFFSET                  0x0
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_HDR_ERR_COR_INT_MASK_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_HDR_ERR_COR_INT_MASK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_HDR_ERR_COR_INT_MASK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_HDR_ERR_COR_INT_MASK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_HDR_ERR_COR_INT_MASK_DISABLED                 _MK_ENUM_CONST(0)    // // Don't generate an interrupt when PPB_HDR_ERR_COR
+// is set.
+
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_HDR_ERR_COR_INT_MASK_ENABLED                  _MK_ENUM_CONST(1)
+
+// Interrupt Mask for PPB_ILL_WD_CNT. Generate an interrupt when PPB_ILL_WD_CNT
+// is set.
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_ILL_WD_CNT_INT_MASK_SHIFT                     _MK_SHIFT_CONST(17)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_ILL_WD_CNT_INT_MASK_FIELD                     (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_ILL_WD_CNT_INT_MASK_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_ILL_WD_CNT_INT_MASK_RANGE                     17:17
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_ILL_WD_CNT_INT_MASK_WOFFSET                   0x0
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_ILL_WD_CNT_INT_MASK_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_ILL_WD_CNT_INT_MASK_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_ILL_WD_CNT_INT_MASK_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_ILL_WD_CNT_INT_MASK_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_ILL_WD_CNT_INT_MASK_DISABLED                  _MK_ENUM_CONST(0)    // // Don't generate an interrupt when PPB_ILL_WD_CNT
+// is set.
+
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_ILL_WD_CNT_INT_MASK_ENABLED                   _MK_ENUM_CONST(1)
+
+// Interrupt Mask for PPB_SL_PROCESSED. Generate an interrupt when PPB_SL_PROCESSED
+// is set.
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SL_PROCESSED_INT_MASK_SHIFT                   _MK_SHIFT_CONST(18)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SL_PROCESSED_INT_MASK_FIELD                   (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SL_PROCESSED_INT_MASK_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SL_PROCESSED_INT_MASK_RANGE                   18:18
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SL_PROCESSED_INT_MASK_WOFFSET                 0x0
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SL_PROCESSED_INT_MASK_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SL_PROCESSED_INT_MASK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SL_PROCESSED_INT_MASK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SL_PROCESSED_INT_MASK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SL_PROCESSED_INT_MASK_DISABLED                        _MK_ENUM_CONST(0)    // // Don't generate an interrupt when PPB_SL_PROCESSED
+// is set.
+
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SL_PROCESSED_INT_MASK_ENABLED                 _MK_ENUM_CONST(1)
+
+// Interrupt Mask for PPB_SL_PKT_DROPPED. Generate an interrupt when PPB_SL_PKT_DROPPED
+// is set.
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SL_PKT_DROPPED_INT_MASK_SHIFT                 _MK_SHIFT_CONST(19)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SL_PKT_DROPPED_INT_MASK_FIELD                 (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SL_PKT_DROPPED_INT_MASK_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SL_PKT_DROPPED_INT_MASK_RANGE                 19:19
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SL_PKT_DROPPED_INT_MASK_WOFFSET                       0x0
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SL_PKT_DROPPED_INT_MASK_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SL_PKT_DROPPED_INT_MASK_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SL_PKT_DROPPED_INT_MASK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SL_PKT_DROPPED_INT_MASK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SL_PKT_DROPPED_INT_MASK_DISABLED                      _MK_ENUM_CONST(0)    // // Don't generate an interrupt when PPB_SL_PKT_DROPPED
+// is set.
+
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SL_PKT_DROPPED_INT_MASK_ENABLED                       _MK_ENUM_CONST(1)
+
+// Interrupt Mask for PPB_PL_CRC_ERR. Generate an interrupt when PPB_PL_CRC_ERR
+// is set.
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_PL_CRC_ERR_INT_MASK_SHIFT                     _MK_SHIFT_CONST(20)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_PL_CRC_ERR_INT_MASK_FIELD                     (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_PL_CRC_ERR_INT_MASK_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_PL_CRC_ERR_INT_MASK_RANGE                     20:20
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_PL_CRC_ERR_INT_MASK_WOFFSET                   0x0
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_PL_CRC_ERR_INT_MASK_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_PL_CRC_ERR_INT_MASK_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_PL_CRC_ERR_INT_MASK_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_PL_CRC_ERR_INT_MASK_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_PL_CRC_ERR_INT_MASK_DISABLED                  _MK_ENUM_CONST(0)    // // Don't generate an interrupt when PPB_PL_CRC_ERR
+// is set.
+
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_PL_CRC_ERR_INT_MASK_ENABLED                   _MK_ENUM_CONST(1)
+
+// Interrupt Mask for PPB_FIFO_OVRF. Generate an interrupt when PPB_FIFO_OVRF
+// is set.
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_FIFO_OVRF_INT_MASK_SHIFT                      _MK_SHIFT_CONST(21)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_FIFO_OVRF_INT_MASK_FIELD                      (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_FIFO_OVRF_INT_MASK_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_FIFO_OVRF_INT_MASK_RANGE                      21:21
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_FIFO_OVRF_INT_MASK_WOFFSET                    0x0
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_FIFO_OVRF_INT_MASK_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_FIFO_OVRF_INT_MASK_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_FIFO_OVRF_INT_MASK_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_FIFO_OVRF_INT_MASK_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_FIFO_OVRF_INT_MASK_DISABLED                   _MK_ENUM_CONST(0)    // // Don't generate an interrupt when PPB_FIFO_OVRF
+// is set.
+
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_FIFO_OVRF_INT_MASK_ENABLED                    _MK_ENUM_CONST(1)
+
+// Interrupt Mask for PPB_STMERR. Generate an interrupt when PPB_STMERR
+// is set.
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_STMERR_INT_MASK_SHIFT                 _MK_SHIFT_CONST(22)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_STMERR_INT_MASK_FIELD                 (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_STMERR_INT_MASK_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_STMERR_INT_MASK_RANGE                 22:22
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_STMERR_INT_MASK_WOFFSET                       0x0
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_STMERR_INT_MASK_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_STMERR_INT_MASK_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_STMERR_INT_MASK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_STMERR_INT_MASK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_STMERR_INT_MASK_DISABLED                      _MK_ENUM_CONST(0)    // // Don't generate an interrupt when PPB_STMERR
+// is set.
+
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_STMERR_INT_MASK_ENABLED                       _MK_ENUM_CONST(1)
+
+// Interrupt Mask for PPB_SHORT_FRAME. Generate an interrupt when PPB_SHORT_FRAME
+// is set.
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SHORT_FRAME_INT_MASK_SHIFT                    _MK_SHIFT_CONST(23)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SHORT_FRAME_INT_MASK_FIELD                    (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SHORT_FRAME_INT_MASK_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SHORT_FRAME_INT_MASK_RANGE                    23:23
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SHORT_FRAME_INT_MASK_WOFFSET                  0x0
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SHORT_FRAME_INT_MASK_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SHORT_FRAME_INT_MASK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SHORT_FRAME_INT_MASK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SHORT_FRAME_INT_MASK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SHORT_FRAME_INT_MASK_DISABLED                 _MK_ENUM_CONST(0)    // // Don't generate an interrupt when PPB_SHORT_FRAME
+// is set.
+
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SHORT_FRAME_INT_MASK_ENABLED                  _MK_ENUM_CONST(1)
+
+// Interrupt Mask for PPB_EXTRA_SF. Generate an interrupt when PPB_EXTRA_SF
+// is set.
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_EXTRA_SF_INT_MASK_SHIFT                       _MK_SHIFT_CONST(24)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_EXTRA_SF_INT_MASK_FIELD                       (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_EXTRA_SF_INT_MASK_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_EXTRA_SF_INT_MASK_RANGE                       24:24
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_EXTRA_SF_INT_MASK_WOFFSET                     0x0
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_EXTRA_SF_INT_MASK_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_EXTRA_SF_INT_MASK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_EXTRA_SF_INT_MASK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_EXTRA_SF_INT_MASK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_EXTRA_SF_INT_MASK_DISABLED                    _MK_ENUM_CONST(0)    // // Don't generate an interrupt when PPB_EXTRA_SF
+// is set.
+
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_EXTRA_SF_INT_MASK_ENABLED                     _MK_ENUM_CONST(1)
+
+// Interrupt Mask for PPB_INTERFRAME_LINE. Generate an interrupt when PPB_INTERFRAME_LINE
+// is set.
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_INTERFRAME_LINE_INT_MASK_SHIFT                        _MK_SHIFT_CONST(25)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_INTERFRAME_LINE_INT_MASK_FIELD                        (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_INTERFRAME_LINE_INT_MASK_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_INTERFRAME_LINE_INT_MASK_RANGE                        25:25
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_INTERFRAME_LINE_INT_MASK_WOFFSET                      0x0
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_INTERFRAME_LINE_INT_MASK_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_INTERFRAME_LINE_INT_MASK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_INTERFRAME_LINE_INT_MASK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_INTERFRAME_LINE_INT_MASK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_INTERFRAME_LINE_INT_MASK_DISABLED                     _MK_ENUM_CONST(0)    // // Don't generate an interrupt when PPB_INTERFRAME_LINE
+// is set.
+
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_INTERFRAME_LINE_INT_MASK_ENABLED                      _MK_ENUM_CONST(1)
+
+// Interrupt Mask for PPB_SPARE_STATUS_1. Generate an interrupt when PPB_SPARE_STATUS_1
+// is set.
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SPARE_STATUS_1_INT_MASK_SHIFT                 _MK_SHIFT_CONST(26)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SPARE_STATUS_1_INT_MASK_FIELD                 (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SPARE_STATUS_1_INT_MASK_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SPARE_STATUS_1_INT_MASK_RANGE                 26:26
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SPARE_STATUS_1_INT_MASK_WOFFSET                       0x0
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SPARE_STATUS_1_INT_MASK_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SPARE_STATUS_1_INT_MASK_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SPARE_STATUS_1_INT_MASK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SPARE_STATUS_1_INT_MASK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SPARE_STATUS_1_INT_MASK_DISABLED                      _MK_ENUM_CONST(0)    // // Don't generate an interrupt when PPB_SPARE_STATUS_1
+// is set.
+
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SPARE_STATUS_1_INT_MASK_ENABLED                       _MK_ENUM_CONST(1)
+
+// Interrupt Mask for PPB_SPARE_STATUS_2. Generate an interrupt when PPB_SPARE_STATUS_2
+// is set.
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SPARE_STATUS_2_INT_MASK_SHIFT                 _MK_SHIFT_CONST(27)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SPARE_STATUS_2_INT_MASK_FIELD                 (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SPARE_STATUS_2_INT_MASK_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SPARE_STATUS_2_INT_MASK_RANGE                 27:27
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SPARE_STATUS_2_INT_MASK_WOFFSET                       0x0
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SPARE_STATUS_2_INT_MASK_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SPARE_STATUS_2_INT_MASK_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SPARE_STATUS_2_INT_MASK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SPARE_STATUS_2_INT_MASK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SPARE_STATUS_2_INT_MASK_DISABLED                      _MK_ENUM_CONST(0)    // // Don't generate an interrupt when PPB_SPARE_STATUS_2
+// is set.
+
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SPARE_STATUS_2_INT_MASK_ENABLED                       _MK_ENUM_CONST(1)
+
+// Interrupt Mask for HPV_UNC_HDR_ERR. Generate an interrupt when HPV_UNC_HDR_ERR
+// is set.
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPV_UNC_HDR_ERR_INT_MASK_SHIFT                    _MK_SHIFT_CONST(30)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPV_UNC_HDR_ERR_INT_MASK_FIELD                    (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPV_UNC_HDR_ERR_INT_MASK_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPV_UNC_HDR_ERR_INT_MASK_RANGE                    30:30
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPV_UNC_HDR_ERR_INT_MASK_WOFFSET                  0x0
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPV_UNC_HDR_ERR_INT_MASK_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPV_UNC_HDR_ERR_INT_MASK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPV_UNC_HDR_ERR_INT_MASK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPV_UNC_HDR_ERR_INT_MASK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPV_UNC_HDR_ERR_INT_MASK_DISABLED                 _MK_ENUM_CONST(0)    // // Don't generate an interrupt when HPV_UNC_HDR_ERR
+// is set.
+
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPV_UNC_HDR_ERR_INT_MASK_ENABLED                  _MK_ENUM_CONST(1)
+
+// Interrupt Mask for HPH_UNC_HDR_ERR. Generate an interrupt when HPH_UNC_HDR_ERR
+// is set.
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPH_UNC_HDR_ERR_INT_MASK_SHIFT                    _MK_SHIFT_CONST(31)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPH_UNC_HDR_ERR_INT_MASK_FIELD                    (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPH_UNC_HDR_ERR_INT_MASK_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPH_UNC_HDR_ERR_INT_MASK_RANGE                    31:31
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPH_UNC_HDR_ERR_INT_MASK_WOFFSET                  0x0
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPH_UNC_HDR_ERR_INT_MASK_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPH_UNC_HDR_ERR_INT_MASK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPH_UNC_HDR_ERR_INT_MASK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPH_UNC_HDR_ERR_INT_MASK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPH_UNC_HDR_ERR_INT_MASK_DISABLED                 _MK_ENUM_CONST(0)    // // Don't generate an interrupt when HPH_UNC_HDR_ERR
+// is set.
+
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPH_UNC_HDR_ERR_INT_MASK_ENABLED                  _MK_ENUM_CONST(1)
+
+
+// Register CSI_CSI_CIL_INTERRUPT_MASK_0  // CSI Control and Interface Logic Interrupt Mask
+#define CSI_CSI_CIL_INTERRUPT_MASK_0                    _MK_ADDR_CONST(0x221)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_WORD_COUNT                         0x1
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_RESET_MASK                         _MK_MASK_CONST(0x1ff81ff)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_READ_MASK                  _MK_MASK_CONST(0x1ff81ff)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_WRITE_MASK                         _MK_MASK_CONST(0x1ff81ff)
+// Interrupt Mask for CILA_SOT_SB_ERR. Generate an interrupt when CILA_SOT_SB_ERR
+// is set.
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SOT_SB_ERR_INT_MASK_SHIFT                     _MK_SHIFT_CONST(0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SOT_SB_ERR_INT_MASK_FIELD                     (_MK_MASK_CONST(0x1) << CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SOT_SB_ERR_INT_MASK_SHIFT)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SOT_SB_ERR_INT_MASK_RANGE                     0:0
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SOT_SB_ERR_INT_MASK_WOFFSET                   0x0
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SOT_SB_ERR_INT_MASK_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SOT_SB_ERR_INT_MASK_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SOT_SB_ERR_INT_MASK_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SOT_SB_ERR_INT_MASK_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SOT_SB_ERR_INT_MASK_DISABLED                  _MK_ENUM_CONST(0)    // // Don't generate an interrupt when CILA_SOT_SB_ERR
+// is set.
+
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SOT_SB_ERR_INT_MASK_ENABLED                   _MK_ENUM_CONST(1)
+
+// Interrupt Mask for CILA_SOT_MB_ERR. Generate an interrupt when CILA_SOT_MB_ERR
+// is set.
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SOT_MB_ERR_INT_MASK_SHIFT                     _MK_SHIFT_CONST(1)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SOT_MB_ERR_INT_MASK_FIELD                     (_MK_MASK_CONST(0x1) << CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SOT_MB_ERR_INT_MASK_SHIFT)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SOT_MB_ERR_INT_MASK_RANGE                     1:1
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SOT_MB_ERR_INT_MASK_WOFFSET                   0x0
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SOT_MB_ERR_INT_MASK_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SOT_MB_ERR_INT_MASK_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SOT_MB_ERR_INT_MASK_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SOT_MB_ERR_INT_MASK_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SOT_MB_ERR_INT_MASK_DISABLED                  _MK_ENUM_CONST(0)    // // Don't generate an interrupt when CILA_SOT_MB_ERR
+// is set.
+
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SOT_MB_ERR_INT_MASK_ENABLED                   _MK_ENUM_CONST(1)
+
+// Interrupt Mask for CILA_SYNC_ESC_ERR. Generate an interrupt when CILA_SYNC_ESC_ERR
+// is set.
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SYNC_ESC_ERR_INT_MASK_SHIFT                   _MK_SHIFT_CONST(2)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SYNC_ESC_ERR_INT_MASK_FIELD                   (_MK_MASK_CONST(0x1) << CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SYNC_ESC_ERR_INT_MASK_SHIFT)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SYNC_ESC_ERR_INT_MASK_RANGE                   2:2
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SYNC_ESC_ERR_INT_MASK_WOFFSET                 0x0
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SYNC_ESC_ERR_INT_MASK_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SYNC_ESC_ERR_INT_MASK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SYNC_ESC_ERR_INT_MASK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SYNC_ESC_ERR_INT_MASK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SYNC_ESC_ERR_INT_MASK_DISABLED                        _MK_ENUM_CONST(0)    // // Don't generate an interrupt when CILA_SYNC_ESC_ERR
+// is set.
+
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SYNC_ESC_ERR_INT_MASK_ENABLED                 _MK_ENUM_CONST(1)
+
+// Interrupt Mask for CILA_ESC_ENTRY_ERR. Generate an interrupt when CILA_ESC_ENTRY_ERR
+// is set.
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_ESC_ENTRY_ERR_INT_MASK_SHIFT                  _MK_SHIFT_CONST(3)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_ESC_ENTRY_ERR_INT_MASK_FIELD                  (_MK_MASK_CONST(0x1) << CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_ESC_ENTRY_ERR_INT_MASK_SHIFT)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_ESC_ENTRY_ERR_INT_MASK_RANGE                  3:3
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_ESC_ENTRY_ERR_INT_MASK_WOFFSET                        0x0
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_ESC_ENTRY_ERR_INT_MASK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_ESC_ENTRY_ERR_INT_MASK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_ESC_ENTRY_ERR_INT_MASK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_ESC_ENTRY_ERR_INT_MASK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_ESC_ENTRY_ERR_INT_MASK_DISABLED                       _MK_ENUM_CONST(0)    // // Don't generate an interrupt when CILA_ESC_ENTRY_ERR
+// is set.
+
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_ESC_ENTRY_ERR_INT_MASK_ENABLED                        _MK_ENUM_CONST(1)
+
+// Interrupt Mask for CILA_CTRL_ERR. Generate an interrupt when CILA_CTRL_ERR
+// is set.
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_CTRL_ERR_INT_MASK_SHIFT                       _MK_SHIFT_CONST(4)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_CTRL_ERR_INT_MASK_FIELD                       (_MK_MASK_CONST(0x1) << CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_CTRL_ERR_INT_MASK_SHIFT)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_CTRL_ERR_INT_MASK_RANGE                       4:4
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_CTRL_ERR_INT_MASK_WOFFSET                     0x0
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_CTRL_ERR_INT_MASK_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_CTRL_ERR_INT_MASK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_CTRL_ERR_INT_MASK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_CTRL_ERR_INT_MASK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_CTRL_ERR_INT_MASK_DISABLED                    _MK_ENUM_CONST(0)    // // Don't generate an interrupt when CILA_CTRL_ERR
+// is set.
+
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_CTRL_ERR_INT_MASK_ENABLED                     _MK_ENUM_CONST(1)
+
+// Interrupt Mask for CILA_ESC_CMD_REC. Generate an interrupt when CILA_ESC_CMD_REC
+// is set.
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_ESC_CMD_REC_INT_MASK_SHIFT                    _MK_SHIFT_CONST(5)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_ESC_CMD_REC_INT_MASK_FIELD                    (_MK_MASK_CONST(0x1) << CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_ESC_CMD_REC_INT_MASK_SHIFT)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_ESC_CMD_REC_INT_MASK_RANGE                    5:5
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_ESC_CMD_REC_INT_MASK_WOFFSET                  0x0
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_ESC_CMD_REC_INT_MASK_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_ESC_CMD_REC_INT_MASK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_ESC_CMD_REC_INT_MASK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_ESC_CMD_REC_INT_MASK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_ESC_CMD_REC_INT_MASK_DISABLED                 _MK_ENUM_CONST(0)    // // Don't generate an interrupt when CILA_ESC_CMD_REC
+// is set.
+
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_ESC_CMD_REC_INT_MASK_ENABLED                  _MK_ENUM_CONST(1)
+
+// Interrupt Mask for CILA_ESC_DATA_REC. Generate an interrupt when CILA_ESC_DATA_REC
+// is set.
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_ESC_DATA_REC_INT_MASK_SHIFT                   _MK_SHIFT_CONST(6)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_ESC_DATA_REC_INT_MASK_FIELD                   (_MK_MASK_CONST(0x1) << CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_ESC_DATA_REC_INT_MASK_SHIFT)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_ESC_DATA_REC_INT_MASK_RANGE                   6:6
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_ESC_DATA_REC_INT_MASK_WOFFSET                 0x0
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_ESC_DATA_REC_INT_MASK_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_ESC_DATA_REC_INT_MASK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_ESC_DATA_REC_INT_MASK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_ESC_DATA_REC_INT_MASK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_ESC_DATA_REC_INT_MASK_DISABLED                        _MK_ENUM_CONST(0)    // // Don't generate an interrupt when CILA_ESC_DATA_REC
+// is set.
+
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_ESC_DATA_REC_INT_MASK_ENABLED                 _MK_ENUM_CONST(1)
+
+// Interrupt Mask for CILA_SPARE_STATUS_1. Generate an interrupt when CILA_SPARE_STATUS_1
+// is set.
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SPARE_STATUS_1_INT_MASK_SHIFT                 _MK_SHIFT_CONST(7)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SPARE_STATUS_1_INT_MASK_FIELD                 (_MK_MASK_CONST(0x1) << CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SPARE_STATUS_1_INT_MASK_SHIFT)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SPARE_STATUS_1_INT_MASK_RANGE                 7:7
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SPARE_STATUS_1_INT_MASK_WOFFSET                       0x0
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SPARE_STATUS_1_INT_MASK_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SPARE_STATUS_1_INT_MASK_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SPARE_STATUS_1_INT_MASK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SPARE_STATUS_1_INT_MASK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SPARE_STATUS_1_INT_MASK_DISABLED                      _MK_ENUM_CONST(0)    // // Don't generate an interrupt when CILA_SPARE_STATUS_1
+// is set.
+
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SPARE_STATUS_1_INT_MASK_ENABLED                       _MK_ENUM_CONST(1)
+
+// Interrupt Mask for CILA_SPARE_STATUS_2. Generate an interrupt when CILA_SPARE_STATUS_2
+// is set.
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SPARE_STATUS_2_INT_MASK_SHIFT                 _MK_SHIFT_CONST(8)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SPARE_STATUS_2_INT_MASK_FIELD                 (_MK_MASK_CONST(0x1) << CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SPARE_STATUS_2_INT_MASK_SHIFT)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SPARE_STATUS_2_INT_MASK_RANGE                 8:8
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SPARE_STATUS_2_INT_MASK_WOFFSET                       0x0
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SPARE_STATUS_2_INT_MASK_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SPARE_STATUS_2_INT_MASK_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SPARE_STATUS_2_INT_MASK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SPARE_STATUS_2_INT_MASK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SPARE_STATUS_2_INT_MASK_DISABLED                      _MK_ENUM_CONST(0)    // // Don't generate an interrupt when CILA_SPARE_STATUS_2
+// is set.
+
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SPARE_STATUS_2_INT_MASK_ENABLED                       _MK_ENUM_CONST(1)
+
+// Interrupt Mask for MIPI_AUTO_CAL_DONE. Generate an interrupt when MIPI_AUTO_CAL_DONE
+// is set.
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_MIPI_AUTO_CAL_DONE_INT_MASK_SHIFT                  _MK_SHIFT_CONST(15)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_MIPI_AUTO_CAL_DONE_INT_MASK_FIELD                  (_MK_MASK_CONST(0x1) << CSI_CSI_CIL_INTERRUPT_MASK_0_MIPI_AUTO_CAL_DONE_INT_MASK_SHIFT)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_MIPI_AUTO_CAL_DONE_INT_MASK_RANGE                  15:15
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_MIPI_AUTO_CAL_DONE_INT_MASK_WOFFSET                        0x0
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_MIPI_AUTO_CAL_DONE_INT_MASK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_MIPI_AUTO_CAL_DONE_INT_MASK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_MIPI_AUTO_CAL_DONE_INT_MASK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_MIPI_AUTO_CAL_DONE_INT_MASK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_MIPI_AUTO_CAL_DONE_INT_MASK_DISABLED                       _MK_ENUM_CONST(0)    // // Don't generate an interrupt when MIPI_AUTO_CAL_DONE
+// is set.
+
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_MIPI_AUTO_CAL_DONE_INT_MASK_ENABLED                        _MK_ENUM_CONST(1)
+
+// Interrupt Mask for CILB_SOT_SB_ERR. Generate an interrupt when CILB_SOT_SB_ERR
+// is set.
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SOT_SB_ERR_INT_MASK_SHIFT                     _MK_SHIFT_CONST(16)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SOT_SB_ERR_INT_MASK_FIELD                     (_MK_MASK_CONST(0x1) << CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SOT_SB_ERR_INT_MASK_SHIFT)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SOT_SB_ERR_INT_MASK_RANGE                     16:16
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SOT_SB_ERR_INT_MASK_WOFFSET                   0x0
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SOT_SB_ERR_INT_MASK_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SOT_SB_ERR_INT_MASK_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SOT_SB_ERR_INT_MASK_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SOT_SB_ERR_INT_MASK_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SOT_SB_ERR_INT_MASK_DISABLED                  _MK_ENUM_CONST(0)    // // Don't generate an interrupt when CILB_SOT_SB_ERR
+// is set.
+
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SOT_SB_ERR_INT_MASK_ENABLED                   _MK_ENUM_CONST(1)
+
+// Interrupt Mask for CILB_SOT_MB_ERR. Generate an interrupt when CILB_SOT_MB_ERR
+// is set.
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SOT_MB_ERR_INT_MASK_SHIFT                     _MK_SHIFT_CONST(17)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SOT_MB_ERR_INT_MASK_FIELD                     (_MK_MASK_CONST(0x1) << CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SOT_MB_ERR_INT_MASK_SHIFT)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SOT_MB_ERR_INT_MASK_RANGE                     17:17
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SOT_MB_ERR_INT_MASK_WOFFSET                   0x0
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SOT_MB_ERR_INT_MASK_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SOT_MB_ERR_INT_MASK_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SOT_MB_ERR_INT_MASK_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SOT_MB_ERR_INT_MASK_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SOT_MB_ERR_INT_MASK_DISABLED                  _MK_ENUM_CONST(0)    // // Don't generate an interrupt when CILB_SOT_MB_ERR
+// is set.
+
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SOT_MB_ERR_INT_MASK_ENABLED                   _MK_ENUM_CONST(1)
+
+// Interrupt Mask for CILB_SYNC_ESC_ERR. Generate an interrupt when CILB_SYNC_ESC_ERR
+// is set.
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SYNC_ESC_ERR_INT_MASK_SHIFT                   _MK_SHIFT_CONST(18)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SYNC_ESC_ERR_INT_MASK_FIELD                   (_MK_MASK_CONST(0x1) << CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SYNC_ESC_ERR_INT_MASK_SHIFT)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SYNC_ESC_ERR_INT_MASK_RANGE                   18:18
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SYNC_ESC_ERR_INT_MASK_WOFFSET                 0x0
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SYNC_ESC_ERR_INT_MASK_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SYNC_ESC_ERR_INT_MASK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SYNC_ESC_ERR_INT_MASK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SYNC_ESC_ERR_INT_MASK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SYNC_ESC_ERR_INT_MASK_DISABLED                        _MK_ENUM_CONST(0)    // // Don't generate an interrupt when CILB_SYNC_ESC_ERR
+// is set.
+
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SYNC_ESC_ERR_INT_MASK_ENABLED                 _MK_ENUM_CONST(1)
+
+// Interrupt Mask for CILB_ESC_ENTRY_ERR. Generate an interrupt when CILB_ESC_ENTRY_ERR
+// is set.
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_ESC_ENTRY_ERR_INT_MASK_SHIFT                  _MK_SHIFT_CONST(19)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_ESC_ENTRY_ERR_INT_MASK_FIELD                  (_MK_MASK_CONST(0x1) << CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_ESC_ENTRY_ERR_INT_MASK_SHIFT)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_ESC_ENTRY_ERR_INT_MASK_RANGE                  19:19
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_ESC_ENTRY_ERR_INT_MASK_WOFFSET                        0x0
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_ESC_ENTRY_ERR_INT_MASK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_ESC_ENTRY_ERR_INT_MASK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_ESC_ENTRY_ERR_INT_MASK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_ESC_ENTRY_ERR_INT_MASK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_ESC_ENTRY_ERR_INT_MASK_DISABLED                       _MK_ENUM_CONST(0)    // // Don't generate an interrupt when CILB_ESC_ENTRY_ERR
+// is set.
+
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_ESC_ENTRY_ERR_INT_MASK_ENABLED                        _MK_ENUM_CONST(1)
+
+// Interrupt Mask for CILB_CTRL_ERR. Generate an interrupt when CILB_CTRL_ERR
+// is set.
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_CTRL_ERR_INT_MASK_SHIFT                       _MK_SHIFT_CONST(20)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_CTRL_ERR_INT_MASK_FIELD                       (_MK_MASK_CONST(0x1) << CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_CTRL_ERR_INT_MASK_SHIFT)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_CTRL_ERR_INT_MASK_RANGE                       20:20
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_CTRL_ERR_INT_MASK_WOFFSET                     0x0
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_CTRL_ERR_INT_MASK_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_CTRL_ERR_INT_MASK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_CTRL_ERR_INT_MASK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_CTRL_ERR_INT_MASK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_CTRL_ERR_INT_MASK_DISABLED                    _MK_ENUM_CONST(0)    // // Don't generate an interrupt when CILB_CTRL_ERR
+// is set.
+
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_CTRL_ERR_INT_MASK_ENABLED                     _MK_ENUM_CONST(1)
+
+// Interrupt Mask for CILB_ESC_CMD_REC. Generate an interrupt when CILB_ESC_CMD_REC
+// is set.
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_ESC_CMD_REC_INT_MASK_SHIFT                    _MK_SHIFT_CONST(21)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_ESC_CMD_REC_INT_MASK_FIELD                    (_MK_MASK_CONST(0x1) << CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_ESC_CMD_REC_INT_MASK_SHIFT)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_ESC_CMD_REC_INT_MASK_RANGE                    21:21
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_ESC_CMD_REC_INT_MASK_WOFFSET                  0x0
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_ESC_CMD_REC_INT_MASK_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_ESC_CMD_REC_INT_MASK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_ESC_CMD_REC_INT_MASK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_ESC_CMD_REC_INT_MASK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_ESC_CMD_REC_INT_MASK_DISABLED                 _MK_ENUM_CONST(0)    // // Don't generate an interrupt when CILB_ESC_CMD_REC
+// is set.
+
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_ESC_CMD_REC_INT_MASK_ENABLED                  _MK_ENUM_CONST(1)
+
+// Interrupt Mask for CILB_ESC_DATA_REC. Generate an interrupt when CILB_ESC_DATA_REC
+// is set.
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_ESC_DATA_REC_INT_MASK_SHIFT                   _MK_SHIFT_CONST(22)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_ESC_DATA_REC_INT_MASK_FIELD                   (_MK_MASK_CONST(0x1) << CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_ESC_DATA_REC_INT_MASK_SHIFT)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_ESC_DATA_REC_INT_MASK_RANGE                   22:22
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_ESC_DATA_REC_INT_MASK_WOFFSET                 0x0
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_ESC_DATA_REC_INT_MASK_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_ESC_DATA_REC_INT_MASK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_ESC_DATA_REC_INT_MASK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_ESC_DATA_REC_INT_MASK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_ESC_DATA_REC_INT_MASK_DISABLED                        _MK_ENUM_CONST(0)    // // Don't generate an interrupt when CILB_ESC_DATA_REC
+// is set.
+
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_ESC_DATA_REC_INT_MASK_ENABLED                 _MK_ENUM_CONST(1)
+
+// Interrupt Mask for CILB_SPARE_STATUS_1. Generate an interrupt when CILB_SPARE_STATUS_1
+// is set.
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SPARE_STATUS_1_INT_MASK_SHIFT                 _MK_SHIFT_CONST(23)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SPARE_STATUS_1_INT_MASK_FIELD                 (_MK_MASK_CONST(0x1) << CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SPARE_STATUS_1_INT_MASK_SHIFT)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SPARE_STATUS_1_INT_MASK_RANGE                 23:23
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SPARE_STATUS_1_INT_MASK_WOFFSET                       0x0
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SPARE_STATUS_1_INT_MASK_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SPARE_STATUS_1_INT_MASK_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SPARE_STATUS_1_INT_MASK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SPARE_STATUS_1_INT_MASK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SPARE_STATUS_1_INT_MASK_DISABLED                      _MK_ENUM_CONST(0)    // // Don't generate an interrupt when CILB_SPARE_STATUS_1
+// is set.
+
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SPARE_STATUS_1_INT_MASK_ENABLED                       _MK_ENUM_CONST(1)
+
+// Interrupt Mask for CILB_SPARE_STATUS_2. Generate an interrupt when CILB_SPARE_STATUS_2
+// is set.
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SPARE_STATUS_2_INT_MASK_SHIFT                 _MK_SHIFT_CONST(24)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SPARE_STATUS_2_INT_MASK_FIELD                 (_MK_MASK_CONST(0x1) << CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SPARE_STATUS_2_INT_MASK_SHIFT)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SPARE_STATUS_2_INT_MASK_RANGE                 24:24
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SPARE_STATUS_2_INT_MASK_WOFFSET                       0x0
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SPARE_STATUS_2_INT_MASK_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SPARE_STATUS_2_INT_MASK_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SPARE_STATUS_2_INT_MASK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SPARE_STATUS_2_INT_MASK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SPARE_STATUS_2_INT_MASK_DISABLED                      _MK_ENUM_CONST(0)    // // Don't generate an interrupt when CILB_SPARE_STATUS_2
+// is set.
+
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SPARE_STATUS_2_INT_MASK_ENABLED                       _MK_ENUM_CONST(1)
+
+
+// Register CSI_CSI_READONLY_STATUS_0  // CSI Read Only Status, this register is used to return
+// CSI read only status.
+#define CSI_CSI_READONLY_STATUS_0                       _MK_ADDR_CONST(0x222)
+#define CSI_CSI_READONLY_STATUS_0_WORD_COUNT                    0x1
+#define CSI_CSI_READONLY_STATUS_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define CSI_CSI_READONLY_STATUS_0_RESET_MASK                    _MK_MASK_CONST(0x0)
+#define CSI_CSI_READONLY_STATUS_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_READONLY_STATUS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_READONLY_STATUS_0_READ_MASK                     _MK_MASK_CONST(0xff)
+#define CSI_CSI_READONLY_STATUS_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+// One only when Pixel Parser A is capturing frame data.
+#define CSI_CSI_READONLY_STATUS_0_CSI_PPA_ACTIVE_SHIFT                  _MK_SHIFT_CONST(0)
+#define CSI_CSI_READONLY_STATUS_0_CSI_PPA_ACTIVE_FIELD                  (_MK_MASK_CONST(0x1) << CSI_CSI_READONLY_STATUS_0_CSI_PPA_ACTIVE_SHIFT)
+#define CSI_CSI_READONLY_STATUS_0_CSI_PPA_ACTIVE_RANGE                  0:0
+#define CSI_CSI_READONLY_STATUS_0_CSI_PPA_ACTIVE_WOFFSET                        0x0
+#define CSI_CSI_READONLY_STATUS_0_CSI_PPA_ACTIVE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_READONLY_STATUS_0_CSI_PPA_ACTIVE_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_READONLY_STATUS_0_CSI_PPA_ACTIVE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_CSI_READONLY_STATUS_0_CSI_PPA_ACTIVE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// One only when Pixel Parser B is capturing frame data.
+#define CSI_CSI_READONLY_STATUS_0_CSI_PPB_ACTIVE_SHIFT                  _MK_SHIFT_CONST(1)
+#define CSI_CSI_READONLY_STATUS_0_CSI_PPB_ACTIVE_FIELD                  (_MK_MASK_CONST(0x1) << CSI_CSI_READONLY_STATUS_0_CSI_PPB_ACTIVE_SHIFT)
+#define CSI_CSI_READONLY_STATUS_0_CSI_PPB_ACTIVE_RANGE                  1:1
+#define CSI_CSI_READONLY_STATUS_0_CSI_PPB_ACTIVE_WOFFSET                        0x0
+#define CSI_CSI_READONLY_STATUS_0_CSI_PPB_ACTIVE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_READONLY_STATUS_0_CSI_PPB_ACTIVE_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_READONLY_STATUS_0_CSI_PPB_ACTIVE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_CSI_READONLY_STATUS_0_CSI_PPB_ACTIVE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Reads back CSI's interrupt line. This is being used test
+// the CSI logic that generates interrupt.
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE2_SHIFT                   _MK_SHIFT_CONST(2)
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE2_FIELD                   (_MK_MASK_CONST(0x1) << CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE2_SHIFT)
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE2_RANGE                   2:2
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE2_WOFFSET                 0x0
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE2_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE2_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Spare Read Only status bit
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE3_SHIFT                   _MK_SHIFT_CONST(3)
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE3_FIELD                   (_MK_MASK_CONST(0x1) << CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE3_SHIFT)
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE3_RANGE                   3:3
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE3_WOFFSET                 0x0
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE3_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE3_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE3_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE3_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Spare Read Only status bit
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE4_SHIFT                   _MK_SHIFT_CONST(4)
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE4_FIELD                   (_MK_MASK_CONST(0x1) << CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE4_SHIFT)
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE4_RANGE                   4:4
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE4_WOFFSET                 0x0
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE4_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE4_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE4_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE4_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Spare Read Only status bit
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE5_SHIFT                   _MK_SHIFT_CONST(5)
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE5_FIELD                   (_MK_MASK_CONST(0x1) << CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE5_SHIFT)
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE5_RANGE                   5:5
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE5_WOFFSET                 0x0
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE5_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE5_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE5_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE5_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Spare Read Only status bit
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE6_SHIFT                   _MK_SHIFT_CONST(6)
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE6_FIELD                   (_MK_MASK_CONST(0x1) << CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE6_SHIFT)
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE6_RANGE                   6:6
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE6_WOFFSET                 0x0
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE6_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE6_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE6_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE6_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Spare Read Only status bit
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE7_SHIFT                   _MK_SHIFT_CONST(7)
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE7_FIELD                   (_MK_MASK_CONST(0x1) << CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE7_SHIFT)
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE7_RANGE                   7:7
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE7_WOFFSET                 0x0
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE7_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE7_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE7_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE7_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register CSI_ESCAPE_MODE_COMMAND_0  // Escape Mode Command, this register is used to receive
+// escape mode command bytes from CIL-A and CIL-B.
+#define CSI_ESCAPE_MODE_COMMAND_0                       _MK_ADDR_CONST(0x223)
+#define CSI_ESCAPE_MODE_COMMAND_0_WORD_COUNT                    0x1
+#define CSI_ESCAPE_MODE_COMMAND_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define CSI_ESCAPE_MODE_COMMAND_0_RESET_MASK                    _MK_MASK_CONST(0x0)
+#define CSI_ESCAPE_MODE_COMMAND_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define CSI_ESCAPE_MODE_COMMAND_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CSI_ESCAPE_MODE_COMMAND_0_READ_MASK                     _MK_MASK_CONST(0xff00ff)
+#define CSI_ESCAPE_MODE_COMMAND_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+// CIL-A Escape Mode Command Byte, this is the 8 bit entry
+// command that was received, by CIL-A, during the last 
+// escape Mode sequence. CIL-A monitors Byte Lane 0, only,
+// for escape mode sequences. This command byte can only 
+// be  assummed to be valid when CILA_ESC_CMD_REC status
+// bit is set.
+#define CSI_ESCAPE_MODE_COMMAND_0_CILA_ESC_CMD_BYTE_SHIFT                       _MK_SHIFT_CONST(0)
+#define CSI_ESCAPE_MODE_COMMAND_0_CILA_ESC_CMD_BYTE_FIELD                       (_MK_MASK_CONST(0xff) << CSI_ESCAPE_MODE_COMMAND_0_CILA_ESC_CMD_BYTE_SHIFT)
+#define CSI_ESCAPE_MODE_COMMAND_0_CILA_ESC_CMD_BYTE_RANGE                       7:0
+#define CSI_ESCAPE_MODE_COMMAND_0_CILA_ESC_CMD_BYTE_WOFFSET                     0x0
+#define CSI_ESCAPE_MODE_COMMAND_0_CILA_ESC_CMD_BYTE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_ESCAPE_MODE_COMMAND_0_CILA_ESC_CMD_BYTE_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CSI_ESCAPE_MODE_COMMAND_0_CILA_ESC_CMD_BYTE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_ESCAPE_MODE_COMMAND_0_CILA_ESC_CMD_BYTE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// CIL-B Escape Mode Command Byte, this is the 8 bit entry
+// command that was received, by CIL-B, during the last 
+// escape Mode sequence. This command byte can only be 
+// assummed to be valid when CILB_ESC_CMD_REC status bit
+// is set.
+#define CSI_ESCAPE_MODE_COMMAND_0_CILB_ESC_CMD_BYTE_SHIFT                       _MK_SHIFT_CONST(16)
+#define CSI_ESCAPE_MODE_COMMAND_0_CILB_ESC_CMD_BYTE_FIELD                       (_MK_MASK_CONST(0xff) << CSI_ESCAPE_MODE_COMMAND_0_CILB_ESC_CMD_BYTE_SHIFT)
+#define CSI_ESCAPE_MODE_COMMAND_0_CILB_ESC_CMD_BYTE_RANGE                       23:16
+#define CSI_ESCAPE_MODE_COMMAND_0_CILB_ESC_CMD_BYTE_WOFFSET                     0x0
+#define CSI_ESCAPE_MODE_COMMAND_0_CILB_ESC_CMD_BYTE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_ESCAPE_MODE_COMMAND_0_CILB_ESC_CMD_BYTE_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CSI_ESCAPE_MODE_COMMAND_0_CILB_ESC_CMD_BYTE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_ESCAPE_MODE_COMMAND_0_CILB_ESC_CMD_BYTE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register CSI_ESCAPE_MODE_DATA_0  // Escape Mode Data, this register is used to receive
+// escape mode data bytes from CIL-A and CIL-B.
+#define CSI_ESCAPE_MODE_DATA_0                  _MK_ADDR_CONST(0x224)
+#define CSI_ESCAPE_MODE_DATA_0_WORD_COUNT                       0x1
+#define CSI_ESCAPE_MODE_DATA_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define CSI_ESCAPE_MODE_DATA_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define CSI_ESCAPE_MODE_DATA_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define CSI_ESCAPE_MODE_DATA_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_ESCAPE_MODE_DATA_0_READ_MASK                        _MK_MASK_CONST(0xff00ff)
+#define CSI_ESCAPE_MODE_DATA_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
+// CIL-A Escape Mode Data Byte, when read this field returns
+// the last Escape Mode Data byte that was received by CIL-A.
+// Escape Mode Data bytes are the bytes that are received
+// in Escape Mode after receiving the Escape Mode Command.
+// These bytes can be used to implement MIPI's CSI Specs Low
+// Power Data Transmition. This field is only valid when 
+// the status bit, CILA_ESC_DATA_REC, is set, and will be
+// overwritten by the next Escape Mode data byte if not read
+// before the next byte come in.
+#define CSI_ESCAPE_MODE_DATA_0_CILA_ESC_DATA_BYTE_SHIFT                 _MK_SHIFT_CONST(0)
+#define CSI_ESCAPE_MODE_DATA_0_CILA_ESC_DATA_BYTE_FIELD                 (_MK_MASK_CONST(0xff) << CSI_ESCAPE_MODE_DATA_0_CILA_ESC_DATA_BYTE_SHIFT)
+#define CSI_ESCAPE_MODE_DATA_0_CILA_ESC_DATA_BYTE_RANGE                 7:0
+#define CSI_ESCAPE_MODE_DATA_0_CILA_ESC_DATA_BYTE_WOFFSET                       0x0
+#define CSI_ESCAPE_MODE_DATA_0_CILA_ESC_DATA_BYTE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_ESCAPE_MODE_DATA_0_CILA_ESC_DATA_BYTE_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_ESCAPE_MODE_DATA_0_CILA_ESC_DATA_BYTE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_ESCAPE_MODE_DATA_0_CILA_ESC_DATA_BYTE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// CIL-B Escape Mode Data Byte, when read this field returns
+// the last Escape Mode Data byte that was received by CIL-B.
+// Escape Mode Data bytes are the bytes that are received
+// in Escape Mode after receiving the Escape Mode Command.
+// These bytes can be used to implement MIPI's CSI Specs Low
+// Power Data Transmition. This field is only valid when 
+// the status bit, CILB_ESC_DATA_REC, is set, and will be
+// overwritten by the next Escape Mode data byte if not read
+// before the next byte come in.
+#define CSI_ESCAPE_MODE_DATA_0_CILB_ESC_DATA_BYTE_SHIFT                 _MK_SHIFT_CONST(16)
+#define CSI_ESCAPE_MODE_DATA_0_CILB_ESC_DATA_BYTE_FIELD                 (_MK_MASK_CONST(0xff) << CSI_ESCAPE_MODE_DATA_0_CILB_ESC_DATA_BYTE_SHIFT)
+#define CSI_ESCAPE_MODE_DATA_0_CILB_ESC_DATA_BYTE_RANGE                 23:16
+#define CSI_ESCAPE_MODE_DATA_0_CILB_ESC_DATA_BYTE_WOFFSET                       0x0
+#define CSI_ESCAPE_MODE_DATA_0_CILB_ESC_DATA_BYTE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_ESCAPE_MODE_DATA_0_CILB_ESC_DATA_BYTE_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_ESCAPE_MODE_DATA_0_CILB_ESC_DATA_BYTE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_ESCAPE_MODE_DATA_0_CILB_ESC_DATA_BYTE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register CSI_CILA_PAD_CONFIG0_0  // CIL-A Pad Configuration 0
+#define CSI_CILA_PAD_CONFIG0_0                  _MK_ADDR_CONST(0x225)
+#define CSI_CILA_PAD_CONFIG0_0_WORD_COUNT                       0x1
+#define CSI_CILA_PAD_CONFIG0_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define CSI_CILA_PAD_CONFIG0_0_RESET_MASK                       _MK_MASK_CONST(0x77f1777f)
+#define CSI_CILA_PAD_CONFIG0_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define CSI_CILA_PAD_CONFIG0_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_CILA_PAD_CONFIG0_0_READ_MASK                        _MK_MASK_CONST(0x77f1777f)
+#define CSI_CILA_PAD_CONFIG0_0_WRITE_MASK                       _MK_MASK_CONST(0x77f1777f)
+// Power down for each data bit, including drivers,
+// receivers and contention detectors
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_PDIO_SHIFT                      _MK_SHIFT_CONST(0)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_PDIO_FIELD                      (_MK_MASK_CONST(0x3) << CSI_CILA_PAD_CONFIG0_0_PAD_CILA_PDIO_SHIFT)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_PDIO_RANGE                      1:0
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_PDIO_WOFFSET                    0x0
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_PDIO_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_PDIO_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_PDIO_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_PDIO_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Power down for clock bit, including drivers, 
+// receivers and contention detectors
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_PDIO_CLK_SHIFT                  _MK_SHIFT_CONST(2)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_PDIO_CLK_FIELD                  (_MK_MASK_CONST(0x1) << CSI_CILA_PAD_CONFIG0_0_PAD_CILA_PDIO_CLK_SHIFT)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_PDIO_CLK_RANGE                  2:2
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_PDIO_CLK_WOFFSET                        0x0
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_PDIO_CLK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_PDIO_CLK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_PDIO_CLK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_PDIO_CLK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// HS driver preemphasis enable,1= preemphasis enabled
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_PREEMP_EN_SHIFT                 _MK_SHIFT_CONST(3)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_PREEMP_EN_FIELD                 (_MK_MASK_CONST(0x1) << CSI_CILA_PAD_CONFIG0_0_PAD_CILA_PREEMP_EN_SHIFT)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_PREEMP_EN_RANGE                 3:3
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_PREEMP_EN_WOFFSET                       0x0
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_PREEMP_EN_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_PREEMP_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_PREEMP_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_PREEMP_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Clock bit input delay trimmer, each tap delays 20ps
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_INADJCLK_SHIFT                  _MK_SHIFT_CONST(4)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_INADJCLK_FIELD                  (_MK_MASK_CONST(0x7) << CSI_CILA_PAD_CONFIG0_0_PAD_CILA_INADJCLK_SHIFT)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_INADJCLK_RANGE                  6:4
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_INADJCLK_WOFFSET                        0x0
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_INADJCLK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_INADJCLK_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_INADJCLK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_INADJCLK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// bit 0 input delay trimmer, each tap delays 20ps
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_INADJ0_SHIFT                    _MK_SHIFT_CONST(8)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_INADJ0_FIELD                    (_MK_MASK_CONST(0x7) << CSI_CILA_PAD_CONFIG0_0_PAD_CILA_INADJ0_SHIFT)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_INADJ0_RANGE                    10:8
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_INADJ0_WOFFSET                  0x0
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_INADJ0_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_INADJ0_DEFAULT_MASK                     _MK_MASK_CONST(0x7)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_INADJ0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_INADJ0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// bit 1 input delay trimmer, each tap delays 20ps
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_INADJ1_SHIFT                    _MK_SHIFT_CONST(12)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_INADJ1_FIELD                    (_MK_MASK_CONST(0x7) << CSI_CILA_PAD_CONFIG0_0_PAD_CILA_INADJ1_SHIFT)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_INADJ1_RANGE                    14:12
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_INADJ1_WOFFSET                  0x0
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_INADJ1_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_INADJ1_DEFAULT_MASK                     _MK_MASK_CONST(0x7)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_INADJ1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_INADJ1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Increase bandwidth of differential receiver
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_BANDWD_IN_SHIFT                 _MK_SHIFT_CONST(16)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_BANDWD_IN_FIELD                 (_MK_MASK_CONST(0x1) << CSI_CILA_PAD_CONFIG0_0_PAD_CILA_BANDWD_IN_SHIFT)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_BANDWD_IN_RANGE                 16:16
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_BANDWD_IN_WOFFSET                       0x0
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_BANDWD_IN_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_BANDWD_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_BANDWD_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_BANDWD_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Driver pull up impedance control
+// 00 -> 130ohm, default
+// 01 -> 110ohm
+// 10 -> 130ohm, same as 00
+// 11 -> 150ohm
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_LPUPADJ_SHIFT                   _MK_SHIFT_CONST(20)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_LPUPADJ_FIELD                   (_MK_MASK_CONST(0x3) << CSI_CILA_PAD_CONFIG0_0_PAD_CILA_LPUPADJ_SHIFT)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_LPUPADJ_RANGE                   21:20
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_LPUPADJ_WOFFSET                 0x0
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_LPUPADJ_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_LPUPADJ_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_LPUPADJ_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_LPUPADJ_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Driver pull down impedance control
+// 00 -> 130ohm, default
+// 01 -> 110ohm
+// 10 -> 130ohm, same as 00
+// 11 -> 150ohm
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_LPDNADJ_SHIFT                   _MK_SHIFT_CONST(22)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_LPDNADJ_FIELD                   (_MK_MASK_CONST(0x3) << CSI_CILA_PAD_CONFIG0_0_PAD_CILA_LPDNADJ_SHIFT)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_LPDNADJ_RANGE                   23:22
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_LPDNADJ_WOFFSET                 0x0
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_LPDNADJ_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_LPDNADJ_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_LPDNADJ_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_LPDNADJ_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Pull up slew rate adjust, default 000
+// From 000 -> 011, slew rate increases
+// 100 is the same as 000
+// From 100->111, skew rate decreases.
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_SLEWUPADJ_SHIFT                 _MK_SHIFT_CONST(24)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_SLEWUPADJ_FIELD                 (_MK_MASK_CONST(0x7) << CSI_CILA_PAD_CONFIG0_0_PAD_CILA_SLEWUPADJ_SHIFT)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_SLEWUPADJ_RANGE                 26:24
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_SLEWUPADJ_WOFFSET                       0x0
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_SLEWUPADJ_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_SLEWUPADJ_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_SLEWUPADJ_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_SLEWUPADJ_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Pull down slew rate adjust, default 000
+// From 000 -> 011, slew rate increases
+// 100 is the same as 000
+// From 100->111, skew rate decreases.
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_SLEWDNADJ_SHIFT                 _MK_SHIFT_CONST(28)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_SLEWDNADJ_FIELD                 (_MK_MASK_CONST(0x7) << CSI_CILA_PAD_CONFIG0_0_PAD_CILA_SLEWDNADJ_SHIFT)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_SLEWDNADJ_RANGE                 30:28
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_SLEWDNADJ_WOFFSET                       0x0
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_SLEWDNADJ_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_SLEWDNADJ_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_SLEWDNADJ_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_SLEWDNADJ_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register CSI_CILA_PAD_CONFIG1_0  // CIL-A Pad Configuration 4
+#define CSI_CILA_PAD_CONFIG1_0                  _MK_ADDR_CONST(0x226)
+#define CSI_CILA_PAD_CONFIG1_0_WORD_COUNT                       0x1
+#define CSI_CILA_PAD_CONFIG1_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define CSI_CILA_PAD_CONFIG1_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
+#define CSI_CILA_PAD_CONFIG1_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define CSI_CILA_PAD_CONFIG1_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_CILA_PAD_CONFIG1_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define CSI_CILA_PAD_CONFIG1_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
+// Spare bits for CILA Config
+// PAD_CILA_SPARE[15] is being used to disable 
+// the CSI-A RTL code that blocks fifo pushs 
+// that are past the end of the line packet.
+// 0: disabled, 1: push blocking enabled
+#define CSI_CILA_PAD_CONFIG1_0_PAD_CILA_SPARE_SHIFT                     _MK_SHIFT_CONST(0)
+#define CSI_CILA_PAD_CONFIG1_0_PAD_CILA_SPARE_FIELD                     (_MK_MASK_CONST(0xffff) << CSI_CILA_PAD_CONFIG1_0_PAD_CILA_SPARE_SHIFT)
+#define CSI_CILA_PAD_CONFIG1_0_PAD_CILA_SPARE_RANGE                     15:0
+#define CSI_CILA_PAD_CONFIG1_0_PAD_CILA_SPARE_WOFFSET                   0x0
+#define CSI_CILA_PAD_CONFIG1_0_PAD_CILA_SPARE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_CILA_PAD_CONFIG1_0_PAD_CILA_SPARE_DEFAULT_MASK                      _MK_MASK_CONST(0xffff)
+#define CSI_CILA_PAD_CONFIG1_0_PAD_CILA_SPARE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CILA_PAD_CONFIG1_0_PAD_CILA_SPARE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Spare Read only bits for CILA Config
+#define CSI_CILA_PAD_CONFIG1_0_PAD_CILA_SPARE_RO_SHIFT                  _MK_SHIFT_CONST(16)
+#define CSI_CILA_PAD_CONFIG1_0_PAD_CILA_SPARE_RO_FIELD                  (_MK_MASK_CONST(0xffff) << CSI_CILA_PAD_CONFIG1_0_PAD_CILA_SPARE_RO_SHIFT)
+#define CSI_CILA_PAD_CONFIG1_0_PAD_CILA_SPARE_RO_RANGE                  31:16
+#define CSI_CILA_PAD_CONFIG1_0_PAD_CILA_SPARE_RO_WOFFSET                        0x0
+#define CSI_CILA_PAD_CONFIG1_0_PAD_CILA_SPARE_RO_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CILA_PAD_CONFIG1_0_PAD_CILA_SPARE_RO_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_CILA_PAD_CONFIG1_0_PAD_CILA_SPARE_RO_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_CILA_PAD_CONFIG1_0_PAD_CILA_SPARE_RO_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register CSI_CILB_PAD_CONFIG0_0  // CIL-B Pad Configuration 0
+#define CSI_CILB_PAD_CONFIG0_0                  _MK_ADDR_CONST(0x227)
+#define CSI_CILB_PAD_CONFIG0_0_WORD_COUNT                       0x1
+#define CSI_CILB_PAD_CONFIG0_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define CSI_CILB_PAD_CONFIG0_0_RESET_MASK                       _MK_MASK_CONST(0x77f1077d)
+#define CSI_CILB_PAD_CONFIG0_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define CSI_CILB_PAD_CONFIG0_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_CILB_PAD_CONFIG0_0_READ_MASK                        _MK_MASK_CONST(0x77f1077d)
+#define CSI_CILB_PAD_CONFIG0_0_WRITE_MASK                       _MK_MASK_CONST(0x77f1077d)
+// Power down for each data bit, including drivers,
+// receivers and contention detectors
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_PDIO_SHIFT                      _MK_SHIFT_CONST(0)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_PDIO_FIELD                      (_MK_MASK_CONST(0x1) << CSI_CILB_PAD_CONFIG0_0_PAD_CILB_PDIO_SHIFT)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_PDIO_RANGE                      0:0
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_PDIO_WOFFSET                    0x0
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_PDIO_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_PDIO_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_PDIO_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_PDIO_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Power down for clock bit, including drivers, 
+// receivers and contention detectors
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_PDIO_CLK_SHIFT                  _MK_SHIFT_CONST(2)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_PDIO_CLK_FIELD                  (_MK_MASK_CONST(0x1) << CSI_CILB_PAD_CONFIG0_0_PAD_CILB_PDIO_CLK_SHIFT)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_PDIO_CLK_RANGE                  2:2
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_PDIO_CLK_WOFFSET                        0x0
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_PDIO_CLK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_PDIO_CLK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_PDIO_CLK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_PDIO_CLK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// HS driver preemphasis enable,1= preemphasis enabled
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_PREEMP_EN_SHIFT                 _MK_SHIFT_CONST(3)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_PREEMP_EN_FIELD                 (_MK_MASK_CONST(0x1) << CSI_CILB_PAD_CONFIG0_0_PAD_CILB_PREEMP_EN_SHIFT)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_PREEMP_EN_RANGE                 3:3
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_PREEMP_EN_WOFFSET                       0x0
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_PREEMP_EN_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_PREEMP_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_PREEMP_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_PREEMP_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Clock bit input delay trimmer, each tap delays 20ps
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_INADJCLK_SHIFT                  _MK_SHIFT_CONST(4)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_INADJCLK_FIELD                  (_MK_MASK_CONST(0x7) << CSI_CILB_PAD_CONFIG0_0_PAD_CILB_INADJCLK_SHIFT)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_INADJCLK_RANGE                  6:4
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_INADJCLK_WOFFSET                        0x0
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_INADJCLK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_INADJCLK_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_INADJCLK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_INADJCLK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// bit 0 input delay trimmer, each tap delays 20ps
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_INADJ0_SHIFT                    _MK_SHIFT_CONST(8)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_INADJ0_FIELD                    (_MK_MASK_CONST(0x7) << CSI_CILB_PAD_CONFIG0_0_PAD_CILB_INADJ0_SHIFT)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_INADJ0_RANGE                    10:8
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_INADJ0_WOFFSET                  0x0
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_INADJ0_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_INADJ0_DEFAULT_MASK                     _MK_MASK_CONST(0x7)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_INADJ0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_INADJ0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Increase bandwidth of differential receiver
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_BANDWD_IN_SHIFT                 _MK_SHIFT_CONST(16)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_BANDWD_IN_FIELD                 (_MK_MASK_CONST(0x1) << CSI_CILB_PAD_CONFIG0_0_PAD_CILB_BANDWD_IN_SHIFT)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_BANDWD_IN_RANGE                 16:16
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_BANDWD_IN_WOFFSET                       0x0
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_BANDWD_IN_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_BANDWD_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_BANDWD_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_BANDWD_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Driver pull up impedance control
+// 00 -> 130ohm, default
+// 01 -> 110ohm
+// 10 -> 130ohm, same as 00
+// 11 -> 150ohm
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_LPUPADJ_SHIFT                   _MK_SHIFT_CONST(20)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_LPUPADJ_FIELD                   (_MK_MASK_CONST(0x3) << CSI_CILB_PAD_CONFIG0_0_PAD_CILB_LPUPADJ_SHIFT)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_LPUPADJ_RANGE                   21:20
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_LPUPADJ_WOFFSET                 0x0
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_LPUPADJ_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_LPUPADJ_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_LPUPADJ_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_LPUPADJ_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Driver pull down impedance control
+// 00 -> 130ohm, default
+// 01 -> 110ohm
+// 10 -> 130ohm, same as 00
+// 11 -> 150ohm
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_LPDNADJ_SHIFT                   _MK_SHIFT_CONST(22)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_LPDNADJ_FIELD                   (_MK_MASK_CONST(0x3) << CSI_CILB_PAD_CONFIG0_0_PAD_CILB_LPDNADJ_SHIFT)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_LPDNADJ_RANGE                   23:22
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_LPDNADJ_WOFFSET                 0x0
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_LPDNADJ_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_LPDNADJ_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_LPDNADJ_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_LPDNADJ_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Pull up slew rate adjust, default 000
+// From 000 -> 011, slew rate increases
+// 100 is the same as 000
+// From 100->111, skew rate decreases.
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_SLEWUPADJ_SHIFT                 _MK_SHIFT_CONST(24)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_SLEWUPADJ_FIELD                 (_MK_MASK_CONST(0x7) << CSI_CILB_PAD_CONFIG0_0_PAD_CILB_SLEWUPADJ_SHIFT)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_SLEWUPADJ_RANGE                 26:24
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_SLEWUPADJ_WOFFSET                       0x0
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_SLEWUPADJ_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_SLEWUPADJ_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_SLEWUPADJ_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_SLEWUPADJ_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Pull down slew rate adjust, default 000
+// From 000 -> 011, slew rate increases
+// 100 is the same as 000
+// From 100->111, skew rate decreases.
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_SLEWDNADJ_SHIFT                 _MK_SHIFT_CONST(28)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_SLEWDNADJ_FIELD                 (_MK_MASK_CONST(0x7) << CSI_CILB_PAD_CONFIG0_0_PAD_CILB_SLEWDNADJ_SHIFT)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_SLEWDNADJ_RANGE                 30:28
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_SLEWDNADJ_WOFFSET                       0x0
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_SLEWDNADJ_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_SLEWDNADJ_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_SLEWDNADJ_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_SLEWDNADJ_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register CSI_CILB_PAD_CONFIG1_0  // CIL-B Pad Configuration 4
+#define CSI_CILB_PAD_CONFIG1_0                  _MK_ADDR_CONST(0x228)
+#define CSI_CILB_PAD_CONFIG1_0_WORD_COUNT                       0x1
+#define CSI_CILB_PAD_CONFIG1_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define CSI_CILB_PAD_CONFIG1_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
+#define CSI_CILB_PAD_CONFIG1_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define CSI_CILB_PAD_CONFIG1_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_CILB_PAD_CONFIG1_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define CSI_CILB_PAD_CONFIG1_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
+// Spare bits for CILB Config
+// PAD_CILB_SPARE[15] is being used to disable 
+// the CSI-B RTL code that blocks fifo pushs 
+// that are past the end of the line packet.
+// 0: disabled, 1: push blocking enabled
+#define CSI_CILB_PAD_CONFIG1_0_PAD_CILB_SPARE_SHIFT                     _MK_SHIFT_CONST(0)
+#define CSI_CILB_PAD_CONFIG1_0_PAD_CILB_SPARE_FIELD                     (_MK_MASK_CONST(0xffff) << CSI_CILB_PAD_CONFIG1_0_PAD_CILB_SPARE_SHIFT)
+#define CSI_CILB_PAD_CONFIG1_0_PAD_CILB_SPARE_RANGE                     15:0
+#define CSI_CILB_PAD_CONFIG1_0_PAD_CILB_SPARE_WOFFSET                   0x0
+#define CSI_CILB_PAD_CONFIG1_0_PAD_CILB_SPARE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_CILB_PAD_CONFIG1_0_PAD_CILB_SPARE_DEFAULT_MASK                      _MK_MASK_CONST(0xffff)
+#define CSI_CILB_PAD_CONFIG1_0_PAD_CILB_SPARE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CILB_PAD_CONFIG1_0_PAD_CILB_SPARE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Spare Read only bits for CILB Config
+#define CSI_CILB_PAD_CONFIG1_0_PAD_CILB_SPARE_RO_SHIFT                  _MK_SHIFT_CONST(16)
+#define CSI_CILB_PAD_CONFIG1_0_PAD_CILB_SPARE_RO_FIELD                  (_MK_MASK_CONST(0xffff) << CSI_CILB_PAD_CONFIG1_0_PAD_CILB_SPARE_RO_SHIFT)
+#define CSI_CILB_PAD_CONFIG1_0_PAD_CILB_SPARE_RO_RANGE                  31:16
+#define CSI_CILB_PAD_CONFIG1_0_PAD_CILB_SPARE_RO_WOFFSET                        0x0
+#define CSI_CILB_PAD_CONFIG1_0_PAD_CILB_SPARE_RO_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CILB_PAD_CONFIG1_0_PAD_CILB_SPARE_RO_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_CILB_PAD_CONFIG1_0_PAD_CILB_SPARE_RO_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_CILB_PAD_CONFIG1_0_PAD_CILB_SPARE_RO_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register CSI_CIL_PAD_CONFIG0_0  // CIL Pad Configuration 0
+#define CSI_CIL_PAD_CONFIG0_0                   _MK_ADDR_CONST(0x229)
+#define CSI_CIL_PAD_CONFIG0_0_WORD_COUNT                        0x1
+#define CSI_CIL_PAD_CONFIG0_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define CSI_CIL_PAD_CONFIG0_0_RESET_MASK                        _MK_MASK_CONST(0xff73)
+#define CSI_CIL_PAD_CONFIG0_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define CSI_CIL_PAD_CONFIG0_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_CIL_PAD_CONFIG0_0_READ_MASK                         _MK_MASK_CONST(0xff73)
+#define CSI_CIL_PAD_CONFIG0_0_WRITE_MASK                        _MK_MASK_CONST(0xff73)
+// Bypass bang gap voltage reference
+#define CSI_CIL_PAD_CONFIG0_0_PAD_CIL_VBYPASS_SHIFT                     _MK_SHIFT_CONST(0)
+#define CSI_CIL_PAD_CONFIG0_0_PAD_CIL_VBYPASS_FIELD                     (_MK_MASK_CONST(0x1) << CSI_CIL_PAD_CONFIG0_0_PAD_CIL_VBYPASS_SHIFT)
+#define CSI_CIL_PAD_CONFIG0_0_PAD_CIL_VBYPASS_RANGE                     0:0
+#define CSI_CIL_PAD_CONFIG0_0_PAD_CIL_VBYPASS_WOFFSET                   0x0
+#define CSI_CIL_PAD_CONFIG0_0_PAD_CIL_VBYPASS_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_CIL_PAD_CONFIG0_0_PAD_CIL_VBYPASS_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CSI_CIL_PAD_CONFIG0_0_PAD_CIL_VBYPASS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CIL_PAD_CONFIG0_0_PAD_CIL_VBYPASS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Power down voltage regulator, 1=power down
+#define CSI_CIL_PAD_CONFIG0_0_PAD_CIL_PDVREG_SHIFT                      _MK_SHIFT_CONST(1)
+#define CSI_CIL_PAD_CONFIG0_0_PAD_CIL_PDVREG_FIELD                      (_MK_MASK_CONST(0x1) << CSI_CIL_PAD_CONFIG0_0_PAD_CIL_PDVREG_SHIFT)
+#define CSI_CIL_PAD_CONFIG0_0_PAD_CIL_PDVREG_RANGE                      1:1
+#define CSI_CIL_PAD_CONFIG0_0_PAD_CIL_PDVREG_WOFFSET                    0x0
+#define CSI_CIL_PAD_CONFIG0_0_PAD_CIL_PDVREG_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_CIL_PAD_CONFIG0_0_PAD_CIL_PDVREG_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CSI_CIL_PAD_CONFIG0_0_PAD_CIL_PDVREG_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_CIL_PAD_CONFIG0_0_PAD_CIL_PDVREG_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// VAUXP level adjustment
+// 00 -> no adjustment, default
+// 01 -> 105% 
+// 10 -> 110% 
+// 11 -> 115%
+// 100 -> no adjustment
+// 101 -> 95%
+// 110 -> 90%
+// 111 -> 85%
+#define CSI_CIL_PAD_CONFIG0_0_PAD_CIL_VADJ_SHIFT                        _MK_SHIFT_CONST(4)
+#define CSI_CIL_PAD_CONFIG0_0_PAD_CIL_VADJ_FIELD                        (_MK_MASK_CONST(0x7) << CSI_CIL_PAD_CONFIG0_0_PAD_CIL_VADJ_SHIFT)
+#define CSI_CIL_PAD_CONFIG0_0_PAD_CIL_VADJ_RANGE                        6:4
+#define CSI_CIL_PAD_CONFIG0_0_PAD_CIL_VADJ_WOFFSET                      0x0
+#define CSI_CIL_PAD_CONFIG0_0_PAD_CIL_VADJ_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_CIL_PAD_CONFIG0_0_PAD_CIL_VADJ_DEFAULT_MASK                 _MK_MASK_CONST(0x7)
+#define CSI_CIL_PAD_CONFIG0_0_PAD_CIL_VADJ_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_CIL_PAD_CONFIG0_0_PAD_CIL_VADJ_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Spare bit for CIL BIAS Config
+// PAD_CIL_SPARE[7] is used is being used to flush VI's
+// Y-FIFO when it is being use as a stream source for 
+// one of the Pixel Parsers. Setting PAD_CIL_SPARE[7]
+// to 1 will hold vi2csi_host_stall low. Which will
+// force VI's Y-FIFO to be purged. PAD_CIL_SPARE[7]
+// must be low for the pixel parser to receive source
+// data from VI's Y-FIFO. 
+#define CSI_CIL_PAD_CONFIG0_0_PAD_CIL_SPARE_SHIFT                       _MK_SHIFT_CONST(8)
+#define CSI_CIL_PAD_CONFIG0_0_PAD_CIL_SPARE_FIELD                       (_MK_MASK_CONST(0xff) << CSI_CIL_PAD_CONFIG0_0_PAD_CIL_SPARE_SHIFT)
+#define CSI_CIL_PAD_CONFIG0_0_PAD_CIL_SPARE_RANGE                       15:8
+#define CSI_CIL_PAD_CONFIG0_0_PAD_CIL_SPARE_WOFFSET                     0x0
+#define CSI_CIL_PAD_CONFIG0_0_PAD_CIL_SPARE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_CIL_PAD_CONFIG0_0_PAD_CIL_SPARE_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define CSI_CIL_PAD_CONFIG0_0_PAD_CIL_SPARE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_CIL_PAD_CONFIG0_0_PAD_CIL_SPARE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register CSI_CILA_MIPI_CAL_CONFIG_0  // Calibration settings for CIL-A mipi pads
+#define CSI_CILA_MIPI_CAL_CONFIG_0                      _MK_ADDR_CONST(0x22a)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_WORD_COUNT                   0x1
+#define CSI_CILA_MIPI_CAL_CONFIG_0_RESET_VAL                    _MK_MASK_CONST(0x2a000000)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_RESET_MASK                   _MK_MASK_CONST(0xff1f1f1f)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_READ_MASK                    _MK_MASK_CONST(0xff1f1f1f)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_WRITE_MASK                   _MK_MASK_CONST(0x7f1f1f1f)
+// 2's complement offset for TERMADJ going to channel A
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_TERMOSA_SHIFT                       _MK_SHIFT_CONST(0)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_TERMOSA_FIELD                       (_MK_MASK_CONST(0x1f) << CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_TERMOSA_SHIFT)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_TERMOSA_RANGE                       4:0
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_TERMOSA_WOFFSET                     0x0
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_TERMOSA_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_TERMOSA_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_TERMOSA_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_TERMOSA_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// 2's complement offset for HSPUADJ going to channel A
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPUOSA_SHIFT                       _MK_SHIFT_CONST(8)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPUOSA_FIELD                       (_MK_MASK_CONST(0x1f) << CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPUOSA_SHIFT)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPUOSA_RANGE                       12:8
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPUOSA_WOFFSET                     0x0
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPUOSA_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPUOSA_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPUOSA_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPUOSA_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// 2's complement offset for HSPDADJ going to channel A
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPDOSA_SHIFT                       _MK_SHIFT_CONST(16)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPDOSA_FIELD                       (_MK_MASK_CONST(0x1f) << CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPDOSA_SHIFT)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPDOSA_RANGE                       20:16
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPDOSA_WOFFSET                     0x0
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPDOSA_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPDOSA_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPDOSA_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPDOSA_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Auto Cal calibration step prescale:
+// Set to 00 when calibration step should be 0.1 us
+// Set to 01 when calibration step should be 0.5 us
+// Set to 10 when calibration step should be 1.0 us
+// Set to 11 when calibration step should be 1.5 us
+// this will keep the mipi bias cal step between 0.1-1.5 usec
+// Default set for 1.0 us calibraiton step.
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_PRESCALE_SHIFT                      _MK_SHIFT_CONST(24)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_PRESCALE_FIELD                      (_MK_MASK_CONST(0x3) << CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_PRESCALE_SHIFT)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_PRESCALE_RANGE                      25:24
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_PRESCALE_WOFFSET                    0x0
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_PRESCALE_DEFAULT                    _MK_MASK_CONST(0x2)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_PRESCALE_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_PRESCALE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_PRESCALE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// The DRIVRY & TERMRY signals coming from MIPI Pads are
+// utilized by Calibration state machine for PAD Calibration.
+// The drivry/termry comes from a noisy analog source 
+// and it could have some glitches.
+// The filter in calibsm is sensitive to these noises.
+// If the calibration done status does not show up, we
+// can change the sensitivity of the filter through these bits.
+// Ideally this has to be programmed in a range from 10 to 15.
+// For the case when MIPI_CAL_PRESCALE = 2'b00, this needs to be
+// programmed between 2 to 5.
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_NOISE_FLT_SHIFT                     _MK_SHIFT_CONST(26)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_NOISE_FLT_FIELD                     (_MK_MASK_CONST(0xf) << CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_NOISE_FLT_SHIFT)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_NOISE_FLT_RANGE                     29:26
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_NOISE_FLT_WOFFSET                   0x0
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_NOISE_FLT_DEFAULT                   _MK_MASK_CONST(0xa)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_NOISE_FLT_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_NOISE_FLT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_NOISE_FLT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// When 0 (normal operation), use the above registers
+// as an offset to the Calibration State machine setting
+// for channel A TERMADJ/HSPUADJ/HSPDADJ values to the 
+// Mipi Pads. When 1, use the register values above as
+// the actual value going to channel A TERMADJ/HSPUADJ/HSPDADJ
+// on the Mipi Pads.
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_OVERIDEA_SHIFT                      _MK_SHIFT_CONST(30)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_OVERIDEA_FIELD                      (_MK_MASK_CONST(0x1) << CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_OVERIDEA_SHIFT)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_OVERIDEA_RANGE                      30:30
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_OVERIDEA_WOFFSET                    0x0
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_OVERIDEA_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_OVERIDEA_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_OVERIDEA_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_OVERIDEA_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Writting a one to this bit starts the Calibration State
+// machine.  This bit must be set even if both overrides
+// set in order to latch in the over ride value
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_STARTCAL_SHIFT                      _MK_SHIFT_CONST(31)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_STARTCAL_FIELD                      (_MK_MASK_CONST(0x1) << CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_STARTCAL_SHIFT)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_STARTCAL_RANGE                      31:31
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_STARTCAL_WOFFSET                    0x0
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_STARTCAL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_STARTCAL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_STARTCAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_STARTCAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register CSI_CILB_MIPI_CAL_CONFIG_0  // Calibration settings for CIL-B mipi pads
+#define CSI_CILB_MIPI_CAL_CONFIG_0                      _MK_ADDR_CONST(0x22b)
+#define CSI_CILB_MIPI_CAL_CONFIG_0_WORD_COUNT                   0x1
+#define CSI_CILB_MIPI_CAL_CONFIG_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define CSI_CILB_MIPI_CAL_CONFIG_0_RESET_MASK                   _MK_MASK_CONST(0x401f1f1f)
+#define CSI_CILB_MIPI_CAL_CONFIG_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define CSI_CILB_MIPI_CAL_CONFIG_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CSI_CILB_MIPI_CAL_CONFIG_0_READ_MASK                    _MK_MASK_CONST(0x401f1f1f)
+#define CSI_CILB_MIPI_CAL_CONFIG_0_WRITE_MASK                   _MK_MASK_CONST(0x401f1f1f)
+// 2's complement offset for TERMADJ going to channel B
+#define CSI_CILB_MIPI_CAL_CONFIG_0_MIPI_CAL_TERMOSB_SHIFT                       _MK_SHIFT_CONST(0)
+#define CSI_CILB_MIPI_CAL_CONFIG_0_MIPI_CAL_TERMOSB_FIELD                       (_MK_MASK_CONST(0x1f) << CSI_CILB_MIPI_CAL_CONFIG_0_MIPI_CAL_TERMOSB_SHIFT)
+#define CSI_CILB_MIPI_CAL_CONFIG_0_MIPI_CAL_TERMOSB_RANGE                       4:0
+#define CSI_CILB_MIPI_CAL_CONFIG_0_MIPI_CAL_TERMOSB_WOFFSET                     0x0
+#define CSI_CILB_MIPI_CAL_CONFIG_0_MIPI_CAL_TERMOSB_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_CILB_MIPI_CAL_CONFIG_0_MIPI_CAL_TERMOSB_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define CSI_CILB_MIPI_CAL_CONFIG_0_MIPI_CAL_TERMOSB_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_CILB_MIPI_CAL_CONFIG_0_MIPI_CAL_TERMOSB_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// 2's complement offset for HSPUADJ going to channel B
+#define CSI_CILB_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPUOSB_SHIFT                       _MK_SHIFT_CONST(8)
+#define CSI_CILB_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPUOSB_FIELD                       (_MK_MASK_CONST(0x1f) << CSI_CILB_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPUOSB_SHIFT)
+#define CSI_CILB_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPUOSB_RANGE                       12:8
+#define CSI_CILB_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPUOSB_WOFFSET                     0x0
+#define CSI_CILB_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPUOSB_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_CILB_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPUOSB_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define CSI_CILB_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPUOSB_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_CILB_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPUOSB_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// 2's complement offset for HSPDADJ going to channel B
+#define CSI_CILB_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPDOSB_SHIFT                       _MK_SHIFT_CONST(16)
+#define CSI_CILB_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPDOSB_FIELD                       (_MK_MASK_CONST(0x1f) << CSI_CILB_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPDOSB_SHIFT)
+#define CSI_CILB_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPDOSB_RANGE                       20:16
+#define CSI_CILB_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPDOSB_WOFFSET                     0x0
+#define CSI_CILB_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPDOSB_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_CILB_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPDOSB_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define CSI_CILB_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPDOSB_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_CILB_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPDOSB_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// When 0 (normal operation), use the above registers
+// as an offset to the Calibration State machine setting
+// for channel B TERMADJ/HSPUADJ/HSPDADJ values to the 
+// Mipi Pads. When 1, use the register values above as
+// the actual value going to channel B TERMADJ/HSPUADJ/HSPDADJ
+// on the Mipi Pads.
+// Writting a one to Bit 31 of CILA_MIPI_CAL_CONFIG 
+// (MIPI_CAL_STARTCAL) starts the Calibration State
+// machine.
+#define CSI_CILB_MIPI_CAL_CONFIG_0_MIPI_CAL_OVERIDEB_SHIFT                      _MK_SHIFT_CONST(30)
+#define CSI_CILB_MIPI_CAL_CONFIG_0_MIPI_CAL_OVERIDEB_FIELD                      (_MK_MASK_CONST(0x1) << CSI_CILB_MIPI_CAL_CONFIG_0_MIPI_CAL_OVERIDEB_SHIFT)
+#define CSI_CILB_MIPI_CAL_CONFIG_0_MIPI_CAL_OVERIDEB_RANGE                      30:30
+#define CSI_CILB_MIPI_CAL_CONFIG_0_MIPI_CAL_OVERIDEB_WOFFSET                    0x0
+#define CSI_CILB_MIPI_CAL_CONFIG_0_MIPI_CAL_OVERIDEB_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_CILB_MIPI_CAL_CONFIG_0_MIPI_CAL_OVERIDEB_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CSI_CILB_MIPI_CAL_CONFIG_0_MIPI_CAL_OVERIDEB_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_CILB_MIPI_CAL_CONFIG_0_MIPI_CAL_OVERIDEB_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register CSI_CIL_MIPI_CAL_STATUS_0  // CIL MIPI Calibrate Status
+#define CSI_CIL_MIPI_CAL_STATUS_0                       _MK_ADDR_CONST(0x22c)
+#define CSI_CIL_MIPI_CAL_STATUS_0_WORD_COUNT                    0x1
+#define CSI_CIL_MIPI_CAL_STATUS_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define CSI_CIL_MIPI_CAL_STATUS_0_RESET_MASK                    _MK_MASK_CONST(0x0)
+#define CSI_CIL_MIPI_CAL_STATUS_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define CSI_CIL_MIPI_CAL_STATUS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CSI_CIL_MIPI_CAL_STATUS_0_READ_MASK                     _MK_MASK_CONST(0xff1)
+#define CSI_CIL_MIPI_CAL_STATUS_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+// One when auto calibrate is active.
+#define CSI_CIL_MIPI_CAL_STATUS_0_MIPI_CAL_ACTIVE_SHIFT                 _MK_SHIFT_CONST(0)
+#define CSI_CIL_MIPI_CAL_STATUS_0_MIPI_CAL_ACTIVE_FIELD                 (_MK_MASK_CONST(0x1) << CSI_CIL_MIPI_CAL_STATUS_0_MIPI_CAL_ACTIVE_SHIFT)
+#define CSI_CIL_MIPI_CAL_STATUS_0_MIPI_CAL_ACTIVE_RANGE                 0:0
+#define CSI_CIL_MIPI_CAL_STATUS_0_MIPI_CAL_ACTIVE_WOFFSET                       0x0
+#define CSI_CIL_MIPI_CAL_STATUS_0_MIPI_CAL_ACTIVE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CIL_MIPI_CAL_STATUS_0_MIPI_CAL_ACTIVE_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_CIL_MIPI_CAL_STATUS_0_MIPI_CAL_ACTIVE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_CIL_MIPI_CAL_STATUS_0_MIPI_CAL_ACTIVE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Termination code generated by MIPI auto Calibrate.
+// Valid only after auto calibrate sequence has 
+// completed (MIPI_CAL_ACTIVE == 0).
+#define CSI_CIL_MIPI_CAL_STATUS_0_MIPI_CAL_TERMADJ_SHIFT                        _MK_SHIFT_CONST(4)
+#define CSI_CIL_MIPI_CAL_STATUS_0_MIPI_CAL_TERMADJ_FIELD                        (_MK_MASK_CONST(0xf) << CSI_CIL_MIPI_CAL_STATUS_0_MIPI_CAL_TERMADJ_SHIFT)
+#define CSI_CIL_MIPI_CAL_STATUS_0_MIPI_CAL_TERMADJ_RANGE                        7:4
+#define CSI_CIL_MIPI_CAL_STATUS_0_MIPI_CAL_TERMADJ_WOFFSET                      0x0
+#define CSI_CIL_MIPI_CAL_STATUS_0_MIPI_CAL_TERMADJ_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_CIL_MIPI_CAL_STATUS_0_MIPI_CAL_TERMADJ_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CSI_CIL_MIPI_CAL_STATUS_0_MIPI_CAL_TERMADJ_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_CIL_MIPI_CAL_STATUS_0_MIPI_CAL_TERMADJ_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Driver code generated by MIPI auto Calibrate.
+// Valid only after auto calibrate sequence has 
+// completed (MIPI_CAL_ACTIVE == 0).
+#define CSI_CIL_MIPI_CAL_STATUS_0_MIPI_CAL_DRIVADJ_SHIFT                        _MK_SHIFT_CONST(8)
+#define CSI_CIL_MIPI_CAL_STATUS_0_MIPI_CAL_DRIVADJ_FIELD                        (_MK_MASK_CONST(0xf) << CSI_CIL_MIPI_CAL_STATUS_0_MIPI_CAL_DRIVADJ_SHIFT)
+#define CSI_CIL_MIPI_CAL_STATUS_0_MIPI_CAL_DRIVADJ_RANGE                        11:8
+#define CSI_CIL_MIPI_CAL_STATUS_0_MIPI_CAL_DRIVADJ_WOFFSET                      0x0
+#define CSI_CIL_MIPI_CAL_STATUS_0_MIPI_CAL_DRIVADJ_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_CIL_MIPI_CAL_STATUS_0_MIPI_CAL_DRIVADJ_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CSI_CIL_MIPI_CAL_STATUS_0_MIPI_CAL_DRIVADJ_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_CIL_MIPI_CAL_STATUS_0_MIPI_CAL_DRIVADJ_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register CSI_CLKEN_OVERRIDE_0  
+#define CSI_CLKEN_OVERRIDE_0                    _MK_ADDR_CONST(0x22d)
+#define CSI_CLKEN_OVERRIDE_0_WORD_COUNT                         0x1
+#define CSI_CLKEN_OVERRIDE_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_RESET_MASK                         _MK_MASK_CONST(0x3fff)
+#define CSI_CLKEN_OVERRIDE_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_READ_MASK                  _MK_MASK_CONST(0x3fff)
+#define CSI_CLKEN_OVERRIDE_0_WRITE_MASK                         _MK_MASK_CONST(0x3fff)
+#define CSI_CLKEN_OVERRIDE_0_CSI_CLKEN_OVR_SHIFT                        _MK_SHIFT_CONST(0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_CLKEN_OVR_FIELD                        (_MK_MASK_CONST(0x1) << CSI_CLKEN_OVERRIDE_0_CSI_CLKEN_OVR_SHIFT)
+#define CSI_CLKEN_OVERRIDE_0_CSI_CLKEN_OVR_RANGE                        0:0
+#define CSI_CLKEN_OVERRIDE_0_CSI_CLKEN_OVR_WOFFSET                      0x0
+#define CSI_CLKEN_OVERRIDE_0_CSI_CLKEN_OVR_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_CLKEN_OVR_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CSI_CLKEN_OVERRIDE_0_CSI_CLKEN_OVR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_CLKEN_OVR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_CLKEN_OVR_INIT_ENUM                    CLK_GATED
+#define CSI_CLKEN_OVERRIDE_0_CSI_CLKEN_OVR_CLK_GATED                    _MK_ENUM_CONST(0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_CLKEN_OVR_CLK_ALWAYS_ON                        _MK_ENUM_CONST(1)
+
+#define CSI_CLKEN_OVERRIDE_0_CSI_DBG_CLKEN_OVR_SHIFT                    _MK_SHIFT_CONST(1)
+#define CSI_CLKEN_OVERRIDE_0_CSI_DBG_CLKEN_OVR_FIELD                    (_MK_MASK_CONST(0x1) << CSI_CLKEN_OVERRIDE_0_CSI_DBG_CLKEN_OVR_SHIFT)
+#define CSI_CLKEN_OVERRIDE_0_CSI_DBG_CLKEN_OVR_RANGE                    1:1
+#define CSI_CLKEN_OVERRIDE_0_CSI_DBG_CLKEN_OVR_WOFFSET                  0x0
+#define CSI_CLKEN_OVERRIDE_0_CSI_DBG_CLKEN_OVR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_DBG_CLKEN_OVR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CSI_CLKEN_OVERRIDE_0_CSI_DBG_CLKEN_OVR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_DBG_CLKEN_OVR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_DBG_CLKEN_OVR_INIT_ENUM                        CLK_GATED
+#define CSI_CLKEN_OVERRIDE_0_CSI_DBG_CLKEN_OVR_CLK_GATED                        _MK_ENUM_CONST(0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_DBG_CLKEN_OVR_CLK_ALWAYS_ON                    _MK_ENUM_CONST(1)
+
+#define CSI_CLKEN_OVERRIDE_0_CSI_FV_CLKEN_OVR_SHIFT                     _MK_SHIFT_CONST(2)
+#define CSI_CLKEN_OVERRIDE_0_CSI_FV_CLKEN_OVR_FIELD                     (_MK_MASK_CONST(0x1) << CSI_CLKEN_OVERRIDE_0_CSI_FV_CLKEN_OVR_SHIFT)
+#define CSI_CLKEN_OVERRIDE_0_CSI_FV_CLKEN_OVR_RANGE                     2:2
+#define CSI_CLKEN_OVERRIDE_0_CSI_FV_CLKEN_OVR_WOFFSET                   0x0
+#define CSI_CLKEN_OVERRIDE_0_CSI_FV_CLKEN_OVR_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_FV_CLKEN_OVR_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CSI_CLKEN_OVERRIDE_0_CSI_FV_CLKEN_OVR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_FV_CLKEN_OVR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_FV_CLKEN_OVR_INIT_ENUM                 CLK_GATED
+#define CSI_CLKEN_OVERRIDE_0_CSI_FV_CLKEN_OVR_CLK_GATED                 _MK_ENUM_CONST(0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_FV_CLKEN_OVR_CLK_ALWAYS_ON                     _MK_ENUM_CONST(1)
+
+#define CSI_CLKEN_OVERRIDE_0_CSI_FA_CLKEN_OVR_SHIFT                     _MK_SHIFT_CONST(3)
+#define CSI_CLKEN_OVERRIDE_0_CSI_FA_CLKEN_OVR_FIELD                     (_MK_MASK_CONST(0x1) << CSI_CLKEN_OVERRIDE_0_CSI_FA_CLKEN_OVR_SHIFT)
+#define CSI_CLKEN_OVERRIDE_0_CSI_FA_CLKEN_OVR_RANGE                     3:3
+#define CSI_CLKEN_OVERRIDE_0_CSI_FA_CLKEN_OVR_WOFFSET                   0x0
+#define CSI_CLKEN_OVERRIDE_0_CSI_FA_CLKEN_OVR_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_FA_CLKEN_OVR_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CSI_CLKEN_OVERRIDE_0_CSI_FA_CLKEN_OVR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_FA_CLKEN_OVR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_FA_CLKEN_OVR_INIT_ENUM                 CLK_GATED
+#define CSI_CLKEN_OVERRIDE_0_CSI_FA_CLKEN_OVR_CLK_GATED                 _MK_ENUM_CONST(0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_FA_CLKEN_OVR_CLK_ALWAYS_ON                     _MK_ENUM_CONST(1)
+
+#define CSI_CLKEN_OVERRIDE_0_CSI_FB_CLKEN_OVR_SHIFT                     _MK_SHIFT_CONST(4)
+#define CSI_CLKEN_OVERRIDE_0_CSI_FB_CLKEN_OVR_FIELD                     (_MK_MASK_CONST(0x1) << CSI_CLKEN_OVERRIDE_0_CSI_FB_CLKEN_OVR_SHIFT)
+#define CSI_CLKEN_OVERRIDE_0_CSI_FB_CLKEN_OVR_RANGE                     4:4
+#define CSI_CLKEN_OVERRIDE_0_CSI_FB_CLKEN_OVR_WOFFSET                   0x0
+#define CSI_CLKEN_OVERRIDE_0_CSI_FB_CLKEN_OVR_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_FB_CLKEN_OVR_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CSI_CLKEN_OVERRIDE_0_CSI_FB_CLKEN_OVR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_FB_CLKEN_OVR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_FB_CLKEN_OVR_INIT_ENUM                 CLK_GATED
+#define CSI_CLKEN_OVERRIDE_0_CSI_FB_CLKEN_OVR_CLK_GATED                 _MK_ENUM_CONST(0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_FB_CLKEN_OVR_CLK_ALWAYS_ON                     _MK_ENUM_CONST(1)
+
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPV_CLKEN_OVR_SHIFT                    _MK_SHIFT_CONST(5)
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPV_CLKEN_OVR_FIELD                    (_MK_MASK_CONST(0x1) << CSI_CLKEN_OVERRIDE_0_CSI_HPV_CLKEN_OVR_SHIFT)
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPV_CLKEN_OVR_RANGE                    5:5
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPV_CLKEN_OVR_WOFFSET                  0x0
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPV_CLKEN_OVR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPV_CLKEN_OVR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPV_CLKEN_OVR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPV_CLKEN_OVR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPV_CLKEN_OVR_INIT_ENUM                        CLK_GATED
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPV_CLKEN_OVR_CLK_GATED                        _MK_ENUM_CONST(0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPV_CLKEN_OVR_CLK_ALWAYS_ON                    _MK_ENUM_CONST(1)
+
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPA_CLKEN_OVR_SHIFT                    _MK_SHIFT_CONST(6)
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPA_CLKEN_OVR_FIELD                    (_MK_MASK_CONST(0x1) << CSI_CLKEN_OVERRIDE_0_CSI_HPA_CLKEN_OVR_SHIFT)
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPA_CLKEN_OVR_RANGE                    6:6
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPA_CLKEN_OVR_WOFFSET                  0x0
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPA_CLKEN_OVR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPA_CLKEN_OVR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPA_CLKEN_OVR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPA_CLKEN_OVR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPA_CLKEN_OVR_INIT_ENUM                        CLK_GATED
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPA_CLKEN_OVR_CLK_GATED                        _MK_ENUM_CONST(0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPA_CLKEN_OVR_CLK_ALWAYS_ON                    _MK_ENUM_CONST(1)
+
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPB_CLKEN_OVR_SHIFT                    _MK_SHIFT_CONST(7)
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPB_CLKEN_OVR_FIELD                    (_MK_MASK_CONST(0x1) << CSI_CLKEN_OVERRIDE_0_CSI_HPB_CLKEN_OVR_SHIFT)
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPB_CLKEN_OVR_RANGE                    7:7
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPB_CLKEN_OVR_WOFFSET                  0x0
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPB_CLKEN_OVR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPB_CLKEN_OVR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPB_CLKEN_OVR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPB_CLKEN_OVR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPB_CLKEN_OVR_INIT_ENUM                        CLK_GATED
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPB_CLKEN_OVR_CLK_GATED                        _MK_ENUM_CONST(0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPB_CLKEN_OVR_CLK_ALWAYS_ON                    _MK_ENUM_CONST(1)
+
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPH_CLKEN_OVR_SHIFT                    _MK_SHIFT_CONST(8)
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPH_CLKEN_OVR_FIELD                    (_MK_MASK_CONST(0x1) << CSI_CLKEN_OVERRIDE_0_CSI_HPH_CLKEN_OVR_SHIFT)
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPH_CLKEN_OVR_RANGE                    8:8
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPH_CLKEN_OVR_WOFFSET                  0x0
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPH_CLKEN_OVR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPH_CLKEN_OVR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPH_CLKEN_OVR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPH_CLKEN_OVR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPH_CLKEN_OVR_INIT_ENUM                        CLK_GATED
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPH_CLKEN_OVR_CLK_GATED                        _MK_ENUM_CONST(0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPH_CLKEN_OVR_CLK_ALWAYS_ON                    _MK_ENUM_CONST(1)
+
+#define CSI_CLKEN_OVERRIDE_0_CSI_PPA_CLKEN_OVR_SHIFT                    _MK_SHIFT_CONST(9)
+#define CSI_CLKEN_OVERRIDE_0_CSI_PPA_CLKEN_OVR_FIELD                    (_MK_MASK_CONST(0x1) << CSI_CLKEN_OVERRIDE_0_CSI_PPA_CLKEN_OVR_SHIFT)
+#define CSI_CLKEN_OVERRIDE_0_CSI_PPA_CLKEN_OVR_RANGE                    9:9
+#define CSI_CLKEN_OVERRIDE_0_CSI_PPA_CLKEN_OVR_WOFFSET                  0x0
+#define CSI_CLKEN_OVERRIDE_0_CSI_PPA_CLKEN_OVR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_PPA_CLKEN_OVR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CSI_CLKEN_OVERRIDE_0_CSI_PPA_CLKEN_OVR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_PPA_CLKEN_OVR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_PPA_CLKEN_OVR_INIT_ENUM                        CLK_GATED
+#define CSI_CLKEN_OVERRIDE_0_CSI_PPA_CLKEN_OVR_CLK_GATED                        _MK_ENUM_CONST(0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_PPA_CLKEN_OVR_CLK_ALWAYS_ON                    _MK_ENUM_CONST(1)
+
+#define CSI_CLKEN_OVERRIDE_0_CSI_PPB_CLKEN_OVR_SHIFT                    _MK_SHIFT_CONST(10)
+#define CSI_CLKEN_OVERRIDE_0_CSI_PPB_CLKEN_OVR_FIELD                    (_MK_MASK_CONST(0x1) << CSI_CLKEN_OVERRIDE_0_CSI_PPB_CLKEN_OVR_SHIFT)
+#define CSI_CLKEN_OVERRIDE_0_CSI_PPB_CLKEN_OVR_RANGE                    10:10
+#define CSI_CLKEN_OVERRIDE_0_CSI_PPB_CLKEN_OVR_WOFFSET                  0x0
+#define CSI_CLKEN_OVERRIDE_0_CSI_PPB_CLKEN_OVR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_PPB_CLKEN_OVR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CSI_CLKEN_OVERRIDE_0_CSI_PPB_CLKEN_OVR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_PPB_CLKEN_OVR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_PPB_CLKEN_OVR_INIT_ENUM                        CLK_GATED
+#define CSI_CLKEN_OVERRIDE_0_CSI_PPB_CLKEN_OVR_CLK_GATED                        _MK_ENUM_CONST(0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_PPB_CLKEN_OVR_CLK_ALWAYS_ON                    _MK_ENUM_CONST(1)
+
+#define CSI_CLKEN_OVERRIDE_0_CSI_CILA_CLKEN_OVR_SHIFT                   _MK_SHIFT_CONST(11)
+#define CSI_CLKEN_OVERRIDE_0_CSI_CILA_CLKEN_OVR_FIELD                   (_MK_MASK_CONST(0x1) << CSI_CLKEN_OVERRIDE_0_CSI_CILA_CLKEN_OVR_SHIFT)
+#define CSI_CLKEN_OVERRIDE_0_CSI_CILA_CLKEN_OVR_RANGE                   11:11
+#define CSI_CLKEN_OVERRIDE_0_CSI_CILA_CLKEN_OVR_WOFFSET                 0x0
+#define CSI_CLKEN_OVERRIDE_0_CSI_CILA_CLKEN_OVR_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_CILA_CLKEN_OVR_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CSI_CLKEN_OVERRIDE_0_CSI_CILA_CLKEN_OVR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_CILA_CLKEN_OVR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_CILA_CLKEN_OVR_INIT_ENUM                       CLK_GATED
+#define CSI_CLKEN_OVERRIDE_0_CSI_CILA_CLKEN_OVR_CLK_GATED                       _MK_ENUM_CONST(0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_CILA_CLKEN_OVR_CLK_ALWAYS_ON                   _MK_ENUM_CONST(1)
+
+#define CSI_CLKEN_OVERRIDE_0_CSI_CILB_CLKEN_OVR_SHIFT                   _MK_SHIFT_CONST(12)
+#define CSI_CLKEN_OVERRIDE_0_CSI_CILB_CLKEN_OVR_FIELD                   (_MK_MASK_CONST(0x1) << CSI_CLKEN_OVERRIDE_0_CSI_CILB_CLKEN_OVR_SHIFT)
+#define CSI_CLKEN_OVERRIDE_0_CSI_CILB_CLKEN_OVR_RANGE                   12:12
+#define CSI_CLKEN_OVERRIDE_0_CSI_CILB_CLKEN_OVR_WOFFSET                 0x0
+#define CSI_CLKEN_OVERRIDE_0_CSI_CILB_CLKEN_OVR_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_CILB_CLKEN_OVR_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CSI_CLKEN_OVERRIDE_0_CSI_CILB_CLKEN_OVR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_CILB_CLKEN_OVR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_CILB_CLKEN_OVR_INIT_ENUM                       CLK_GATED
+#define CSI_CLKEN_OVERRIDE_0_CSI_CILB_CLKEN_OVR_CLK_GATED                       _MK_ENUM_CONST(0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_CILB_CLKEN_OVR_CLK_ALWAYS_ON                   _MK_ENUM_CONST(1)
+
+#define CSI_CLKEN_OVERRIDE_0_CSI_CIL_CLKEN_OVR_SHIFT                    _MK_SHIFT_CONST(13)
+#define CSI_CLKEN_OVERRIDE_0_CSI_CIL_CLKEN_OVR_FIELD                    (_MK_MASK_CONST(0x1) << CSI_CLKEN_OVERRIDE_0_CSI_CIL_CLKEN_OVR_SHIFT)
+#define CSI_CLKEN_OVERRIDE_0_CSI_CIL_CLKEN_OVR_RANGE                    13:13
+#define CSI_CLKEN_OVERRIDE_0_CSI_CIL_CLKEN_OVR_WOFFSET                  0x0
+#define CSI_CLKEN_OVERRIDE_0_CSI_CIL_CLKEN_OVR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_CIL_CLKEN_OVR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CSI_CLKEN_OVERRIDE_0_CSI_CIL_CLKEN_OVR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_CIL_CLKEN_OVR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_CIL_CLKEN_OVR_INIT_ENUM                        CLK_GATED
+#define CSI_CLKEN_OVERRIDE_0_CSI_CIL_CLKEN_OVR_CLK_GATED                        _MK_ENUM_CONST(0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_CIL_CLKEN_OVR_CLK_ALWAYS_ON                    _MK_ENUM_CONST(1)
+
+
+// Register CSI_DEBUG_CONTROL_0  // Debug Control
+#define CSI_DEBUG_CONTROL_0                     _MK_ADDR_CONST(0x22e)
+#define CSI_DEBUG_CONTROL_0_WORD_COUNT                  0x1
+#define CSI_DEBUG_CONTROL_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_CONTROL_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define CSI_DEBUG_CONTROL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_CONTROL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_CONTROL_0_READ_MASK                   _MK_MASK_CONST(0xffffff7d)
+#define CSI_DEBUG_CONTROL_0_WRITE_MASK                  _MK_MASK_CONST(0x7f7f7f01)
+// Debug Enable Second level CSI Debug clock is enabled. Debug counters
+// 2, 1 & 0 are powered up.
+#define CSI_DEBUG_CONTROL_0_DEBUG_EN_SHIFT                      _MK_SHIFT_CONST(0)
+#define CSI_DEBUG_CONTROL_0_DEBUG_EN_FIELD                      (_MK_MASK_CONST(0x1) << CSI_DEBUG_CONTROL_0_DEBUG_EN_SHIFT)
+#define CSI_DEBUG_CONTROL_0_DEBUG_EN_RANGE                      0:0
+#define CSI_DEBUG_CONTROL_0_DEBUG_EN_WOFFSET                    0x0
+#define CSI_DEBUG_CONTROL_0_DEBUG_EN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_CONTROL_0_DEBUG_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CSI_DEBUG_CONTROL_0_DEBUG_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_CONTROL_0_DEBUG_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_CONTROL_0_DEBUG_EN_DISABLED                   _MK_ENUM_CONST(0)    // // Debug counters 2, 1 & 0 are powered down. Second level
+// CSI Debug clock is disabled.
+
+#define CSI_DEBUG_CONTROL_0_DEBUG_EN_ENABLED                    _MK_ENUM_CONST(1)
+
+// When CSI-A is operating in a "Header Not Sent mode",
+// writting a 1 to this bit indicates start frame (SF)
+// or end frame (EF) control code. After the pixel parser 
+// is enabled, writing a 1 to this bit will start frame 
+// capture and send start frame (SF) control code. Writing
+// a 1 to this bit again will stop frame capture and send
+// end frame (EF) control code. "Header Not Sent mode" can 
+// be used as a debug mode to capture what the sensor
+// is sending without interpeting the packets. Writing a
+// 1 to this bit continually will generate SF and EF control
+// codes. Note that a wait for MISC_CSI_PPA_FRAME_END syncpt
+// is needed between an EF trigger for the current frame and 
+// an SF trigger for the next frame.
+#define CSI_DEBUG_CONTROL_0_CSIA_DBG_SF_SHIFT                   _MK_SHIFT_CONST(2)
+#define CSI_DEBUG_CONTROL_0_CSIA_DBG_SF_FIELD                   (_MK_MASK_CONST(0x1) << CSI_DEBUG_CONTROL_0_CSIA_DBG_SF_SHIFT)
+#define CSI_DEBUG_CONTROL_0_CSIA_DBG_SF_RANGE                   2:2
+#define CSI_DEBUG_CONTROL_0_CSIA_DBG_SF_WOFFSET                 0x0
+#define CSI_DEBUG_CONTROL_0_CSIA_DBG_SF_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_CONTROL_0_CSIA_DBG_SF_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_CONTROL_0_CSIA_DBG_SF_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_CONTROL_0_CSIA_DBG_SF_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// When CSI-B is operating in a "Header Not Sent mode",
+// writting a 1 to this bit indicates start frame (SF)
+// or end frame (EF) control code. After the pixel parser 
+// is enabled, writing a 1 to this bit will start frame 
+// capture and send start frame (SF) control code. Writing
+// a 1 to this bit again will stop frame capture and send
+// end frame (EF) control code. "Header Not Sent mode" can 
+// be used as a debug mode to capture what the sensor
+// is sending without interpeting the packets. Writing a
+// 1 to this bit continually will generate SF and EF control
+// codes. Note that a wait for MISC_CSI_PPB_FRAME_END syncpt
+// is needed between an EF trigger for the current frame and 
+// an SF trigger for the next frame.
+#define CSI_DEBUG_CONTROL_0_CSIB_DBG_SF_SHIFT                   _MK_SHIFT_CONST(3)
+#define CSI_DEBUG_CONTROL_0_CSIB_DBG_SF_FIELD                   (_MK_MASK_CONST(0x1) << CSI_DEBUG_CONTROL_0_CSIB_DBG_SF_SHIFT)
+#define CSI_DEBUG_CONTROL_0_CSIB_DBG_SF_RANGE                   3:3
+#define CSI_DEBUG_CONTROL_0_CSIB_DBG_SF_WOFFSET                 0x0
+#define CSI_DEBUG_CONTROL_0_CSIB_DBG_SF_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_CONTROL_0_CSIB_DBG_SF_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_CONTROL_0_CSIB_DBG_SF_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_CONTROL_0_CSIB_DBG_SF_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Clear Debug Counter 0, write a one to this bit to clear
+// debug counter 0 and dbg_cnt_rolled_0.
+#define CSI_DEBUG_CONTROL_0_CLR_DBG_CNT_0_SHIFT                 _MK_SHIFT_CONST(4)
+#define CSI_DEBUG_CONTROL_0_CLR_DBG_CNT_0_FIELD                 (_MK_MASK_CONST(0x1) << CSI_DEBUG_CONTROL_0_CLR_DBG_CNT_0_SHIFT)
+#define CSI_DEBUG_CONTROL_0_CLR_DBG_CNT_0_RANGE                 4:4
+#define CSI_DEBUG_CONTROL_0_CLR_DBG_CNT_0_WOFFSET                       0x0
+#define CSI_DEBUG_CONTROL_0_CLR_DBG_CNT_0_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_CONTROL_0_CLR_DBG_CNT_0_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_CONTROL_0_CLR_DBG_CNT_0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_CONTROL_0_CLR_DBG_CNT_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Clear Debug Counter 1, write a one to this bit to clear
+// debug counter 1 and dbg_cnt_rolled_1.
+#define CSI_DEBUG_CONTROL_0_CLR_DBG_CNT_1_SHIFT                 _MK_SHIFT_CONST(5)
+#define CSI_DEBUG_CONTROL_0_CLR_DBG_CNT_1_FIELD                 (_MK_MASK_CONST(0x1) << CSI_DEBUG_CONTROL_0_CLR_DBG_CNT_1_SHIFT)
+#define CSI_DEBUG_CONTROL_0_CLR_DBG_CNT_1_RANGE                 5:5
+#define CSI_DEBUG_CONTROL_0_CLR_DBG_CNT_1_WOFFSET                       0x0
+#define CSI_DEBUG_CONTROL_0_CLR_DBG_CNT_1_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_CONTROL_0_CLR_DBG_CNT_1_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_CONTROL_0_CLR_DBG_CNT_1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_CONTROL_0_CLR_DBG_CNT_1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Clear Debug Counter 2, write a one to this bit to clear
+// debug counter 2 and dbg_cnt_rolled_2.
+#define CSI_DEBUG_CONTROL_0_CLR_DBG_CNT_2_SHIFT                 _MK_SHIFT_CONST(6)
+#define CSI_DEBUG_CONTROL_0_CLR_DBG_CNT_2_FIELD                 (_MK_MASK_CONST(0x1) << CSI_DEBUG_CONTROL_0_CLR_DBG_CNT_2_SHIFT)
+#define CSI_DEBUG_CONTROL_0_CLR_DBG_CNT_2_RANGE                 6:6
+#define CSI_DEBUG_CONTROL_0_CLR_DBG_CNT_2_WOFFSET                       0x0
+#define CSI_DEBUG_CONTROL_0_CLR_DBG_CNT_2_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_CONTROL_0_CLR_DBG_CNT_2_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_CONTROL_0_CLR_DBG_CNT_2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_CONTROL_0_CLR_DBG_CNT_2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Debug Count Select 0, this field selects what will be 
+// counted by debug counter 0.
+// Encodings 00 to 31 selects the set signal for one of 
+// the CSI_PIXEL_PARSER_STATUS register bits. In this case
+// the select encoding of this field is the same as the
+// bit position, in CSI_PIXEL_PARSER_STATUS, of the status
+// bit who's set signal will be used to increment DBG_CNT_0.
+// Encodings 32 to 63 selects the set signal for one of 
+// the CSI_CIL_STATUS status bits. The least significant 
+// 5 bits of this select field give the bit position, in
+// CSI_CIL_STATUS, of the status bit whos set signal pluses
+// will be counted by dbg_cnt_0. Selections for encodings 64
+// to 127 are given below: 
+// 64 - PPA Line packets processed
+// 65 - PPA short packets processed
+// 66 - Total packets processed by PPA
+// 67 - PPA Frame Starts Outputted
+// 68 - PPA Frame Ends Outputted
+// 69 - Reserved encoding
+// 70 - PPB Line packets processed
+// 71 - PPB short packets processed
+// 72 - Total packets processed by PPB
+// 73 - PPB Frame Starts Outputted
+// 74 - PPB Frame Ends Outputted
+// 75 - Reserved encoding
+// 76 - HPA Headers Parsed
+// 77 - HPA Headers Parsed with no ECC Errors
+// 78 - HPB Headers Parsed
+// 79 - HPB Headers Parsed with no ECC Errors
+// 80 - HPV Headers Parsed
+// 81 - HPV Headers Parsed with no ECC Errors
+// 82 - HPH Headers Parsed
+// 83 - HPH Headers Parsed with no ECC Errors
+// 84 - 32 bit words read from vi2csi_host_data
+// 85 to 127 - Reserved encodings
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_SEL_0_SHIFT                 _MK_SHIFT_CONST(8)
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_SEL_0_FIELD                 (_MK_MASK_CONST(0x7f) << CSI_DEBUG_CONTROL_0_DBG_CNT_SEL_0_SHIFT)
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_SEL_0_RANGE                 14:8
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_SEL_0_WOFFSET                       0x0
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_SEL_0_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_SEL_0_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_SEL_0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_SEL_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Set when dbg_cnt_0 is incremented past max count, cleared
+// when clr_dbg_cnt_0 is written with a value of 1.
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_ROLLED_0_SHIFT                      _MK_SHIFT_CONST(15)
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_ROLLED_0_FIELD                      (_MK_MASK_CONST(0x1) << CSI_DEBUG_CONTROL_0_DBG_CNT_ROLLED_0_SHIFT)
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_ROLLED_0_RANGE                      15:15
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_ROLLED_0_WOFFSET                    0x0
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_ROLLED_0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_ROLLED_0_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_ROLLED_0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_ROLLED_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Debug Count Select 1, this field selects what will be 
+// counted by debug counter 1.
+// Encodings 00 to 31 selects the set signal for one of 
+// the CSI_PIXEL_PARSER_STATUS register bits. In this case
+// the select encoding of this field is the same as the
+// bit position, in CSI_PIXEL_PARSER_STATUS, of the status
+// bit who's set signal will be used to increment DBG_CNT_0.
+// Encodings 32 to 63 selects the set signal for one of 
+// the CSI_CIL_STATUS status bits. The least significant 
+// 5 bits of this select field give the bit position, in
+// CSI_CIL_STATUS, of the status bit whos set signal pluses
+// will be counted by dbg_cnt_0. Selections for encodings 64
+// to 127 are given below: 
+// 64 - PPA Line packets processed
+// 65 - PPA short packets processed
+// 66 - Total packets processed by PPA
+// 67 - PPA Frame Starts Outputted
+// 68 - PPA Frame Ends Outputted
+// 69 - Reserved encoding
+// 70 - PPB Line packets processed
+// 71 - PPB short packets processed
+// 72 - Total packets processed by PPB
+// 73 - PPB Frame Starts Outputted
+// 74 - PPB Frame Ends Outputted
+// 75 - Reserved encoding
+// 76 - HPA Headers Parsed
+// 77 - HPA Headers Parsed with no ECC Errors
+// 78 - HPB Headers Parsed
+// 79 - HPB Headers Parsed with no ECC Errors
+// 80 - HPV Headers Parsed
+// 81 - HPV Headers Parsed with no ECC Errors
+// 82 - HPH Headers Parsed
+// 83 - HPH Headers Parsed with no ECC Errors
+// 84 - 32 bit words read from vi2csi_host_data
+// 85 to 127 - Reserved encodings
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_SEL_1_SHIFT                 _MK_SHIFT_CONST(16)
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_SEL_1_FIELD                 (_MK_MASK_CONST(0x7f) << CSI_DEBUG_CONTROL_0_DBG_CNT_SEL_1_SHIFT)
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_SEL_1_RANGE                 22:16
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_SEL_1_WOFFSET                       0x0
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_SEL_1_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_SEL_1_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_SEL_1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_SEL_1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Set when dbg_cnt_1 is incremented past max count, cleared
+// when clr_dbg_cnt_1 is written with a value of 1.
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_ROLLED_1_SHIFT                      _MK_SHIFT_CONST(23)
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_ROLLED_1_FIELD                      (_MK_MASK_CONST(0x1) << CSI_DEBUG_CONTROL_0_DBG_CNT_ROLLED_1_SHIFT)
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_ROLLED_1_RANGE                      23:23
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_ROLLED_1_WOFFSET                    0x0
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_ROLLED_1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_ROLLED_1_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_ROLLED_1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_ROLLED_1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Debug Count Select 2, this field selects what will be 
+// counted by debug counter 2.
+// Encodings 00 to 31 selects the set signal for one of 
+// the CSI_PIXEL_PARSER_STATUS register bits. In this case
+// the select encoding of this field is the same as the
+// bit position, in CSI_PIXEL_PARSER_STATUS, of the status
+// bit who's set signal will be used to increment DBG_CNT_0.
+// Encodings 32 to 63 selects the set signal for one of 
+// the CSI_CIL_STATUS status bits. The least significant 
+// 5 bits of this select field give the bit position, in
+// CSI_CIL_STATUS, of the status bit whos set signal pluses
+// will be counted by dbg_cnt_0. Selections for encodings 64
+// to 127 are given below: 
+// 64 - PPA Line packets processed
+// 65 - PPA short packets processed
+// 66 - Total packets processed by PPA
+// 67 - PPA Frame Starts Outputted
+// 68 - PPA Frame Ends Outputted
+// 69 - Reserved encoding
+// 70 - PPB Line packets processed
+// 71 - PPB short packets processed
+// 72 - Total packets processed by PPB
+// 73 - PPB Frame Starts Outputted
+// 74 - PPB Frame Ends Outputted
+// 75 - Reserved encoding
+// 76 - HPA Headers Parsed
+// 77 - HPA Headers Parsed with no ECC Errors
+// 78 - HPB Headers Parsed
+// 79 - HPB Headers Parsed with no ECC Errors
+// 80 - HPV Headers Parsed
+// 81 - HPV Headers Parsed with no ECC Errors
+// 82 - HPH Headers Parsed
+// 83 - HPH Headers Parsed with no ECC Errors
+// 84 - 32 bit words read from vi2csi_host_data
+// 85 to 127 - Reserved encodings
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_SEL_2_SHIFT                 _MK_SHIFT_CONST(24)
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_SEL_2_FIELD                 (_MK_MASK_CONST(0x7f) << CSI_DEBUG_CONTROL_0_DBG_CNT_SEL_2_SHIFT)
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_SEL_2_RANGE                 30:24
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_SEL_2_WOFFSET                       0x0
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_SEL_2_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_SEL_2_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_SEL_2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_SEL_2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Set when dbg_cnt_2 is incremented past max count, cleared
+// when clr_dbg_cnt_2 is written with a value of 1.
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_ROLLED_2_SHIFT                      _MK_SHIFT_CONST(31)
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_ROLLED_2_FIELD                      (_MK_MASK_CONST(0x1) << CSI_DEBUG_CONTROL_0_DBG_CNT_ROLLED_2_SHIFT)
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_ROLLED_2_RANGE                      31:31
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_ROLLED_2_WOFFSET                    0x0
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_ROLLED_2_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_ROLLED_2_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_ROLLED_2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_ROLLED_2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register CSI_DEBUG_COUNTER_0_0  // Debug Counter 0, this register can be used to count 
+// error conditions or packets processed.
+#define CSI_DEBUG_COUNTER_0_0                   _MK_ADDR_CONST(0x22f)
+#define CSI_DEBUG_COUNTER_0_0_WORD_COUNT                        0x1
+#define CSI_DEBUG_COUNTER_0_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_COUNTER_0_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_COUNTER_0_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_COUNTER_0_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_COUNTER_0_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define CSI_DEBUG_COUNTER_0_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+// When read returns the value of debug counter 0.
+#define CSI_DEBUG_COUNTER_0_0_DBG_CNT_0_SHIFT                   _MK_SHIFT_CONST(0)
+#define CSI_DEBUG_COUNTER_0_0_DBG_CNT_0_FIELD                   (_MK_MASK_CONST(0xffffffff) << CSI_DEBUG_COUNTER_0_0_DBG_CNT_0_SHIFT)
+#define CSI_DEBUG_COUNTER_0_0_DBG_CNT_0_RANGE                   31:0
+#define CSI_DEBUG_COUNTER_0_0_DBG_CNT_0_WOFFSET                 0x0
+#define CSI_DEBUG_COUNTER_0_0_DBG_CNT_0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_COUNTER_0_0_DBG_CNT_0_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_COUNTER_0_0_DBG_CNT_0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_COUNTER_0_0_DBG_CNT_0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register CSI_DEBUG_COUNTER_1_0  // Debug Counter 1, this register can be used to count 
+// error conditions or packets processed.
+#define CSI_DEBUG_COUNTER_1_0                   _MK_ADDR_CONST(0x230)
+#define CSI_DEBUG_COUNTER_1_0_WORD_COUNT                        0x1
+#define CSI_DEBUG_COUNTER_1_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_COUNTER_1_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_COUNTER_1_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_COUNTER_1_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_COUNTER_1_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define CSI_DEBUG_COUNTER_1_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+// When read returns the value of debug counter 1.
+#define CSI_DEBUG_COUNTER_1_0_DBG_CNT_1_SHIFT                   _MK_SHIFT_CONST(0)
+#define CSI_DEBUG_COUNTER_1_0_DBG_CNT_1_FIELD                   (_MK_MASK_CONST(0xffffffff) << CSI_DEBUG_COUNTER_1_0_DBG_CNT_1_SHIFT)
+#define CSI_DEBUG_COUNTER_1_0_DBG_CNT_1_RANGE                   31:0
+#define CSI_DEBUG_COUNTER_1_0_DBG_CNT_1_WOFFSET                 0x0
+#define CSI_DEBUG_COUNTER_1_0_DBG_CNT_1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_COUNTER_1_0_DBG_CNT_1_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_COUNTER_1_0_DBG_CNT_1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_COUNTER_1_0_DBG_CNT_1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register CSI_DEBUG_COUNTER_2_0  // Debug Counter 2, this register can be used to count 
+// error conditions or packets processed.
+#define CSI_DEBUG_COUNTER_2_0                   _MK_ADDR_CONST(0x231)
+#define CSI_DEBUG_COUNTER_2_0_WORD_COUNT                        0x1
+#define CSI_DEBUG_COUNTER_2_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_COUNTER_2_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_COUNTER_2_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_COUNTER_2_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_COUNTER_2_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define CSI_DEBUG_COUNTER_2_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+// When read returns the value of debug counter 2.
+#define CSI_DEBUG_COUNTER_2_0_DBG_CNT_2_SHIFT                   _MK_SHIFT_CONST(0)
+#define CSI_DEBUG_COUNTER_2_0_DBG_CNT_2_FIELD                   (_MK_MASK_CONST(0xffffffff) << CSI_DEBUG_COUNTER_2_0_DBG_CNT_2_SHIFT)
+#define CSI_DEBUG_COUNTER_2_0_DBG_CNT_2_RANGE                   31:0
+#define CSI_DEBUG_COUNTER_2_0_DBG_CNT_2_WOFFSET                 0x0
+#define CSI_DEBUG_COUNTER_2_0_DBG_CNT_2_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_COUNTER_2_0_DBG_CNT_2_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_COUNTER_2_0_DBG_CNT_2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_COUNTER_2_0_DBG_CNT_2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register CSI_PIXEL_STREAM_A_EXPECTED_FRAME_0  // CSI Pixel Stream A Expected Frame
+#define CSI_PIXEL_STREAM_A_EXPECTED_FRAME_0                     _MK_ADDR_CONST(0x232)
+#define CSI_PIXEL_STREAM_A_EXPECTED_FRAME_0_WORD_COUNT                  0x1
+#define CSI_PIXEL_STREAM_A_EXPECTED_FRAME_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_EXPECTED_FRAME_0_RESET_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_EXPECTED_FRAME_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_EXPECTED_FRAME_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_EXPECTED_FRAME_0_READ_MASK                   _MK_MASK_CONST(0x1ffffff1)
+#define CSI_PIXEL_STREAM_A_EXPECTED_FRAME_0_WRITE_MASK                  _MK_MASK_CONST(0x1ffffff1)
+// When set to one enables checking of the time between
+// start line requests from the Header Parser to CSI-PPA.
+// A fake EF will be outputted by CSI-PPA if this time 
+// between line starts exceeds the value in 
+// MAX_CLOCKS_BETWEEN_LINES. Padding lines can be inserted
+// before the fake EF, if the number of lines outputted,
+// when the fake EF is generated is less than the expected
+// frame height. The type of padding is specified using
+// CSI_PPA_PAD_FRAME.
+#define CSI_PIXEL_STREAM_A_EXPECTED_FRAME_0_PPA_ENABLE_LINE_TIMEOUT_SHIFT                       _MK_SHIFT_CONST(0)
+#define CSI_PIXEL_STREAM_A_EXPECTED_FRAME_0_PPA_ENABLE_LINE_TIMEOUT_FIELD                       (_MK_MASK_CONST(0x1) << CSI_PIXEL_STREAM_A_EXPECTED_FRAME_0_PPA_ENABLE_LINE_TIMEOUT_SHIFT)
+#define CSI_PIXEL_STREAM_A_EXPECTED_FRAME_0_PPA_ENABLE_LINE_TIMEOUT_RANGE                       0:0
+#define CSI_PIXEL_STREAM_A_EXPECTED_FRAME_0_PPA_ENABLE_LINE_TIMEOUT_WOFFSET                     0x0
+#define CSI_PIXEL_STREAM_A_EXPECTED_FRAME_0_PPA_ENABLE_LINE_TIMEOUT_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_EXPECTED_FRAME_0_PPA_ENABLE_LINE_TIMEOUT_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_EXPECTED_FRAME_0_PPA_ENABLE_LINE_TIMEOUT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_EXPECTED_FRAME_0_PPA_ENABLE_LINE_TIMEOUT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Maximum Number of viclk clock cycles between line
+// start requests. The value in this field is in terms
+// of 256 viclk clock cycles.
+#define CSI_PIXEL_STREAM_A_EXPECTED_FRAME_0_PPA_MAX_CLOCKS_SHIFT                        _MK_SHIFT_CONST(4)
+#define CSI_PIXEL_STREAM_A_EXPECTED_FRAME_0_PPA_MAX_CLOCKS_FIELD                        (_MK_MASK_CONST(0xfff) << CSI_PIXEL_STREAM_A_EXPECTED_FRAME_0_PPA_MAX_CLOCKS_SHIFT)
+#define CSI_PIXEL_STREAM_A_EXPECTED_FRAME_0_PPA_MAX_CLOCKS_RANGE                        15:4
+#define CSI_PIXEL_STREAM_A_EXPECTED_FRAME_0_PPA_MAX_CLOCKS_WOFFSET                      0x0
+#define CSI_PIXEL_STREAM_A_EXPECTED_FRAME_0_PPA_MAX_CLOCKS_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_EXPECTED_FRAME_0_PPA_MAX_CLOCKS_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_EXPECTED_FRAME_0_PPA_MAX_CLOCKS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_EXPECTED_FRAME_0_PPA_MAX_CLOCKS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// CSI-PPA Expected Frame Height
+// Specifies the expected height of the CSI-PPA frame 
+// output. Padding out of frames that are shorter
+// than this expected height can be specified using
+// CSI_PPA_PAD_FRAME. If CSI_PPA_PAD_FRAME is set to
+// PAD0S or PAD1S, this parameter must be programmed.
+// If CSI_PPA_PAD_FRAME is set to NOPAD, this parameter
+// may not be programmed. 
+// Programmed Value = number of lines
+#define CSI_PIXEL_STREAM_A_EXPECTED_FRAME_0_PPA_EXP_FRAME_HEIGHT_SHIFT                  _MK_SHIFT_CONST(16)
+#define CSI_PIXEL_STREAM_A_EXPECTED_FRAME_0_PPA_EXP_FRAME_HEIGHT_FIELD                  (_MK_MASK_CONST(0x1fff) << CSI_PIXEL_STREAM_A_EXPECTED_FRAME_0_PPA_EXP_FRAME_HEIGHT_SHIFT)
+#define CSI_PIXEL_STREAM_A_EXPECTED_FRAME_0_PPA_EXP_FRAME_HEIGHT_RANGE                  28:16
+#define CSI_PIXEL_STREAM_A_EXPECTED_FRAME_0_PPA_EXP_FRAME_HEIGHT_WOFFSET                        0x0
+#define CSI_PIXEL_STREAM_A_EXPECTED_FRAME_0_PPA_EXP_FRAME_HEIGHT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_EXPECTED_FRAME_0_PPA_EXP_FRAME_HEIGHT_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_EXPECTED_FRAME_0_PPA_EXP_FRAME_HEIGHT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_EXPECTED_FRAME_0_PPA_EXP_FRAME_HEIGHT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register CSI_PIXEL_STREAM_B_EXPECTED_FRAME_0  // CSI Pixel Stream B Expected Frame
+#define CSI_PIXEL_STREAM_B_EXPECTED_FRAME_0                     _MK_ADDR_CONST(0x233)
+#define CSI_PIXEL_STREAM_B_EXPECTED_FRAME_0_WORD_COUNT                  0x1
+#define CSI_PIXEL_STREAM_B_EXPECTED_FRAME_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_EXPECTED_FRAME_0_RESET_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_EXPECTED_FRAME_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_EXPECTED_FRAME_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_EXPECTED_FRAME_0_READ_MASK                   _MK_MASK_CONST(0x1ffffff1)
+#define CSI_PIXEL_STREAM_B_EXPECTED_FRAME_0_WRITE_MASK                  _MK_MASK_CONST(0x1ffffff1)
+// When set to one enables checking of the time between
+// start line requests from the Header Parser to CSI-PPB.
+// A fake EF will be outputted by CSI-PPB if this time 
+// between line starts exceeds the value in 
+// MAX_CLOCKS_BETWEEN_LINES. Padding lines can be inserted
+// before the fake EF, if the number of lines outputted,
+// when the fake EF is generated is less than the expected
+// frame height. The type of padding is specified using
+// CSI_PPB_PAD_FRAME.
+#define CSI_PIXEL_STREAM_B_EXPECTED_FRAME_0_PPB_ENABLE_LINE_TIMEOUT_SHIFT                       _MK_SHIFT_CONST(0)
+#define CSI_PIXEL_STREAM_B_EXPECTED_FRAME_0_PPB_ENABLE_LINE_TIMEOUT_FIELD                       (_MK_MASK_CONST(0x1) << CSI_PIXEL_STREAM_B_EXPECTED_FRAME_0_PPB_ENABLE_LINE_TIMEOUT_SHIFT)
+#define CSI_PIXEL_STREAM_B_EXPECTED_FRAME_0_PPB_ENABLE_LINE_TIMEOUT_RANGE                       0:0
+#define CSI_PIXEL_STREAM_B_EXPECTED_FRAME_0_PPB_ENABLE_LINE_TIMEOUT_WOFFSET                     0x0
+#define CSI_PIXEL_STREAM_B_EXPECTED_FRAME_0_PPB_ENABLE_LINE_TIMEOUT_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_EXPECTED_FRAME_0_PPB_ENABLE_LINE_TIMEOUT_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_EXPECTED_FRAME_0_PPB_ENABLE_LINE_TIMEOUT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_EXPECTED_FRAME_0_PPB_ENABLE_LINE_TIMEOUT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Maximum Number of viclk clock cycles between line
+// start requests. The value in this field is in terms
+// of 256 viclk clock cycles.
+#define CSI_PIXEL_STREAM_B_EXPECTED_FRAME_0_PPB_MAX_CLOCKS_SHIFT                        _MK_SHIFT_CONST(4)
+#define CSI_PIXEL_STREAM_B_EXPECTED_FRAME_0_PPB_MAX_CLOCKS_FIELD                        (_MK_MASK_CONST(0xfff) << CSI_PIXEL_STREAM_B_EXPECTED_FRAME_0_PPB_MAX_CLOCKS_SHIFT)
+#define CSI_PIXEL_STREAM_B_EXPECTED_FRAME_0_PPB_MAX_CLOCKS_RANGE                        15:4
+#define CSI_PIXEL_STREAM_B_EXPECTED_FRAME_0_PPB_MAX_CLOCKS_WOFFSET                      0x0
+#define CSI_PIXEL_STREAM_B_EXPECTED_FRAME_0_PPB_MAX_CLOCKS_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_EXPECTED_FRAME_0_PPB_MAX_CLOCKS_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_EXPECTED_FRAME_0_PPB_MAX_CLOCKS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_EXPECTED_FRAME_0_PPB_MAX_CLOCKS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// CSI-PPB Expected Frame Height
+// Specifies the expected height of the CSI-PPB frame 
+// output. Padding out of frames that are shorter
+// than this expected height can be specified using
+// CSI_PPB_PAD_FRAME. If CSI_PPB_PAD_FRAME is set to
+// PAD0S or PAD1S, this parameter must be programmed.
+// If CSI_PPB_PAD_FRAME is set to NOPAD, this parameter
+// may not be programmed.
+// Programmed Value = number of lines
+#define CSI_PIXEL_STREAM_B_EXPECTED_FRAME_0_PPB_EXP_FRAME_HEIGHT_SHIFT                  _MK_SHIFT_CONST(16)
+#define CSI_PIXEL_STREAM_B_EXPECTED_FRAME_0_PPB_EXP_FRAME_HEIGHT_FIELD                  (_MK_MASK_CONST(0x1fff) << CSI_PIXEL_STREAM_B_EXPECTED_FRAME_0_PPB_EXP_FRAME_HEIGHT_SHIFT)
+#define CSI_PIXEL_STREAM_B_EXPECTED_FRAME_0_PPB_EXP_FRAME_HEIGHT_RANGE                  28:16
+#define CSI_PIXEL_STREAM_B_EXPECTED_FRAME_0_PPB_EXP_FRAME_HEIGHT_WOFFSET                        0x0
+#define CSI_PIXEL_STREAM_B_EXPECTED_FRAME_0_PPB_EXP_FRAME_HEIGHT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_EXPECTED_FRAME_0_PPB_EXP_FRAME_HEIGHT_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_EXPECTED_FRAME_0_PPB_EXP_FRAME_HEIGHT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_EXPECTED_FRAME_0_PPB_EXP_FRAME_HEIGHT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register CSI_DSI_MIPI_CAL_CONFIG_0  // Calibration settings for DSI mipi pad
+#define CSI_DSI_MIPI_CAL_CONFIG_0                       _MK_ADDR_CONST(0x234)
+#define CSI_DSI_MIPI_CAL_CONFIG_0_WORD_COUNT                    0x1
+#define CSI_DSI_MIPI_CAL_CONFIG_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define CSI_DSI_MIPI_CAL_CONFIG_0_RESET_MASK                    _MK_MASK_CONST(0x401f1f1f)
+#define CSI_DSI_MIPI_CAL_CONFIG_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define CSI_DSI_MIPI_CAL_CONFIG_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CSI_DSI_MIPI_CAL_CONFIG_0_READ_MASK                     _MK_MASK_CONST(0x401f1f1f)
+#define CSI_DSI_MIPI_CAL_CONFIG_0_WRITE_MASK                    _MK_MASK_CONST(0x401f1f1f)
+// 2's complement offset for TERMADJ
+#define CSI_DSI_MIPI_CAL_CONFIG_0_MIPI_CAL_TERMOSD_SHIFT                        _MK_SHIFT_CONST(0)
+#define CSI_DSI_MIPI_CAL_CONFIG_0_MIPI_CAL_TERMOSD_FIELD                        (_MK_MASK_CONST(0x1f) << CSI_DSI_MIPI_CAL_CONFIG_0_MIPI_CAL_TERMOSD_SHIFT)
+#define CSI_DSI_MIPI_CAL_CONFIG_0_MIPI_CAL_TERMOSD_RANGE                        4:0
+#define CSI_DSI_MIPI_CAL_CONFIG_0_MIPI_CAL_TERMOSD_WOFFSET                      0x0
+#define CSI_DSI_MIPI_CAL_CONFIG_0_MIPI_CAL_TERMOSD_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_DSI_MIPI_CAL_CONFIG_0_MIPI_CAL_TERMOSD_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define CSI_DSI_MIPI_CAL_CONFIG_0_MIPI_CAL_TERMOSD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_DSI_MIPI_CAL_CONFIG_0_MIPI_CAL_TERMOSD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// 2's complement offset for HSPUADJ
+#define CSI_DSI_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPUOSD_SHIFT                        _MK_SHIFT_CONST(8)
+#define CSI_DSI_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPUOSD_FIELD                        (_MK_MASK_CONST(0x1f) << CSI_DSI_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPUOSD_SHIFT)
+#define CSI_DSI_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPUOSD_RANGE                        12:8
+#define CSI_DSI_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPUOSD_WOFFSET                      0x0
+#define CSI_DSI_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPUOSD_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_DSI_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPUOSD_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define CSI_DSI_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPUOSD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_DSI_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPUOSD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// 2's complement offset for HSPDADJ
+#define CSI_DSI_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPDOSD_SHIFT                        _MK_SHIFT_CONST(16)
+#define CSI_DSI_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPDOSD_FIELD                        (_MK_MASK_CONST(0x1f) << CSI_DSI_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPDOSD_SHIFT)
+#define CSI_DSI_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPDOSD_RANGE                        20:16
+#define CSI_DSI_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPDOSD_WOFFSET                      0x0
+#define CSI_DSI_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPDOSD_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_DSI_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPDOSD_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define CSI_DSI_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPDOSD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_DSI_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPDOSD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// When 0 (normal operation), use the above registers
+// as an offset to the Calibration State machine setting
+// for TERMADJ/HSPUADJ/HSPDADJ values to the 
+// Mipi Pads. When 1, use the register values above as
+// the actual value going to TERMADJ/HSPUADJ/HSPDADJ
+// on the Mipi Pads.
+// Writting a one to Bit 31 of CILA_MIPI_CAL_CONFIG 
+// (MIPI_CAL_STARTCAL) starts the Calibration State
+// machine.
+#define CSI_DSI_MIPI_CAL_CONFIG_0_MIPI_CAL_OVERIDED_SHIFT                       _MK_SHIFT_CONST(30)
+#define CSI_DSI_MIPI_CAL_CONFIG_0_MIPI_CAL_OVERIDED_FIELD                       (_MK_MASK_CONST(0x1) << CSI_DSI_MIPI_CAL_CONFIG_0_MIPI_CAL_OVERIDED_SHIFT)
+#define CSI_DSI_MIPI_CAL_CONFIG_0_MIPI_CAL_OVERIDED_RANGE                       30:30
+#define CSI_DSI_MIPI_CAL_CONFIG_0_MIPI_CAL_OVERIDED_WOFFSET                     0x0
+#define CSI_DSI_MIPI_CAL_CONFIG_0_MIPI_CAL_OVERIDED_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_DSI_MIPI_CAL_CONFIG_0_MIPI_CAL_OVERIDED_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CSI_DSI_MIPI_CAL_CONFIG_0_MIPI_CAL_OVERIDED_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_DSI_MIPI_CAL_CONFIG_0_MIPI_CAL_OVERIDED_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Packet SENSOR2CIL_PKT
+#define SENSOR2CIL_PKT_SIZE 10
+
+// Data
+#define SENSOR2CIL_PKT_BYTE_SHIFT                       _MK_SHIFT_CONST(0)
+#define SENSOR2CIL_PKT_BYTE_FIELD                       (_MK_MASK_CONST(0xff) << SENSOR2CIL_PKT_BYTE_SHIFT)
+#define SENSOR2CIL_PKT_BYTE_RANGE                       _MK_SHIFT_CONST(7):_MK_SHIFT_CONST(0)
+#define SENSOR2CIL_PKT_BYTE_ROW                 0
+
+// Start of frame
+#define SENSOR2CIL_PKT_SOT_SHIFT                        _MK_SHIFT_CONST(8)
+#define SENSOR2CIL_PKT_SOT_FIELD                        (_MK_MASK_CONST(0x1) << SENSOR2CIL_PKT_SOT_SHIFT)
+#define SENSOR2CIL_PKT_SOT_RANGE                        _MK_SHIFT_CONST(8):_MK_SHIFT_CONST(8)
+#define SENSOR2CIL_PKT_SOT_ROW                  0
+
+// End of frame
+#define SENSOR2CIL_PKT_EOT_SHIFT                        _MK_SHIFT_CONST(9)
+#define SENSOR2CIL_PKT_EOT_FIELD                        (_MK_MASK_CONST(0x1) << SENSOR2CIL_PKT_EOT_SHIFT)
+#define SENSOR2CIL_PKT_EOT_RANGE                        _MK_SHIFT_CONST(9):_MK_SHIFT_CONST(9)
+#define SENSOR2CIL_PKT_EOT_ROW                  0
+
+
+// Packet CIL2CSI_PKT
+#define CIL2CSI_PKT_SIZE 8
+
+// Data
+#define CIL2CSI_PKT_BYTE_SHIFT                  _MK_SHIFT_CONST(0)
+#define CIL2CSI_PKT_BYTE_FIELD                  (_MK_MASK_CONST(0xff) << CIL2CSI_PKT_BYTE_SHIFT)
+#define CIL2CSI_PKT_BYTE_RANGE                  _MK_SHIFT_CONST(7):_MK_SHIFT_CONST(0)
+#define CIL2CSI_PKT_BYTE_ROW                    0
+
+
+// Packet VI2CSI_HOST_PKT
+#define VI2CSI_HOST_PKT_SIZE 33
+
+// Data
+#define VI2CSI_HOST_PKT_HOSTDATA_SHIFT                  _MK_SHIFT_CONST(0)
+#define VI2CSI_HOST_PKT_HOSTDATA_FIELD                  (_MK_MASK_CONST(0xffffffff) << VI2CSI_HOST_PKT_HOSTDATA_SHIFT)
+#define VI2CSI_HOST_PKT_HOSTDATA_RANGE                  _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define VI2CSI_HOST_PKT_HOSTDATA_ROW                    0
+
+// End of packet tag, 0: end of packet, 1: valid packet data
+#define VI2CSI_HOST_PKT_TAG_SHIFT                       _MK_SHIFT_CONST(32)
+#define VI2CSI_HOST_PKT_TAG_FIELD                       (_MK_MASK_CONST(0x1) << VI2CSI_HOST_PKT_TAG_SHIFT)
+#define VI2CSI_HOST_PKT_TAG_RANGE                       _MK_SHIFT_CONST(32):_MK_SHIFT_CONST(32)
+#define VI2CSI_HOST_PKT_TAG_ROW                 0
+
+
+// Packet VI2CSI_VIP_PKT
+#define VI2CSI_VIP_PKT_SIZE 16
+
+// Data
+#define VI2CSI_VIP_PKT_VIPDATA_SHIFT                    _MK_SHIFT_CONST(0)
+#define VI2CSI_VIP_PKT_VIPDATA_FIELD                    (_MK_MASK_CONST(0xffff) << VI2CSI_VIP_PKT_VIPDATA_SHIFT)
+#define VI2CSI_VIP_PKT_VIPDATA_RANGE                    _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(0)
+#define VI2CSI_VIP_PKT_VIPDATA_ROW                      0
+
+
+// Packet SENSOR2CIL_TIMING_PKT
+#define SENSOR2CIL_TIMING_PKT_SIZE 73
+
+// 
+#define SENSOR2CIL_TIMING_PKT_LPX_SHIFT                 _MK_SHIFT_CONST(0)
+#define SENSOR2CIL_TIMING_PKT_LPX_FIELD                 (_MK_MASK_CONST(0xff) << SENSOR2CIL_TIMING_PKT_LPX_SHIFT)
+#define SENSOR2CIL_TIMING_PKT_LPX_RANGE                 _MK_SHIFT_CONST(7):_MK_SHIFT_CONST(0)
+#define SENSOR2CIL_TIMING_PKT_LPX_ROW                   0
+
+#define SENSOR2CIL_TIMING_PKT_HS_PREPARE_SHIFT                  _MK_SHIFT_CONST(8)
+#define SENSOR2CIL_TIMING_PKT_HS_PREPARE_FIELD                  (_MK_MASK_CONST(0xff) << SENSOR2CIL_TIMING_PKT_HS_PREPARE_SHIFT)
+#define SENSOR2CIL_TIMING_PKT_HS_PREPARE_RANGE                  _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(8)
+#define SENSOR2CIL_TIMING_PKT_HS_PREPARE_ROW                    0
+
+#define SENSOR2CIL_TIMING_PKT_HS_ZERO_SHIFT                     _MK_SHIFT_CONST(16)
+#define SENSOR2CIL_TIMING_PKT_HS_ZERO_FIELD                     (_MK_MASK_CONST(0xff) << SENSOR2CIL_TIMING_PKT_HS_ZERO_SHIFT)
+#define SENSOR2CIL_TIMING_PKT_HS_ZERO_RANGE                     _MK_SHIFT_CONST(23):_MK_SHIFT_CONST(16)
+#define SENSOR2CIL_TIMING_PKT_HS_ZERO_ROW                       0
+
+#define SENSOR2CIL_TIMING_PKT_HS_TRAIL_SHIFT                    _MK_SHIFT_CONST(24)
+#define SENSOR2CIL_TIMING_PKT_HS_TRAIL_FIELD                    (_MK_MASK_CONST(0xff) << SENSOR2CIL_TIMING_PKT_HS_TRAIL_SHIFT)
+#define SENSOR2CIL_TIMING_PKT_HS_TRAIL_RANGE                    _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(24)
+#define SENSOR2CIL_TIMING_PKT_HS_TRAIL_ROW                      0
+
+#define SENSOR2CIL_TIMING_PKT_CLK_ZERO_SHIFT                    _MK_SHIFT_CONST(32)
+#define SENSOR2CIL_TIMING_PKT_CLK_ZERO_FIELD                    (_MK_MASK_CONST(0xff) << SENSOR2CIL_TIMING_PKT_CLK_ZERO_SHIFT)
+#define SENSOR2CIL_TIMING_PKT_CLK_ZERO_RANGE                    _MK_SHIFT_CONST(39):_MK_SHIFT_CONST(32)
+#define SENSOR2CIL_TIMING_PKT_CLK_ZERO_ROW                      0
+
+#define SENSOR2CIL_TIMING_PKT_CLK_PRE_SHIFT                     _MK_SHIFT_CONST(40)
+#define SENSOR2CIL_TIMING_PKT_CLK_PRE_FIELD                     (_MK_MASK_CONST(0xff) << SENSOR2CIL_TIMING_PKT_CLK_PRE_SHIFT)
+#define SENSOR2CIL_TIMING_PKT_CLK_PRE_RANGE                     _MK_SHIFT_CONST(47):_MK_SHIFT_CONST(40)
+#define SENSOR2CIL_TIMING_PKT_CLK_PRE_ROW                       0
+
+#define SENSOR2CIL_TIMING_PKT_CLK_POST_SHIFT                    _MK_SHIFT_CONST(48)
+#define SENSOR2CIL_TIMING_PKT_CLK_POST_FIELD                    (_MK_MASK_CONST(0xff) << SENSOR2CIL_TIMING_PKT_CLK_POST_SHIFT)
+#define SENSOR2CIL_TIMING_PKT_CLK_POST_RANGE                    _MK_SHIFT_CONST(55):_MK_SHIFT_CONST(48)
+#define SENSOR2CIL_TIMING_PKT_CLK_POST_ROW                      0
+
+#define SENSOR2CIL_TIMING_PKT_CLK_TRAIL_SHIFT                   _MK_SHIFT_CONST(56)
+#define SENSOR2CIL_TIMING_PKT_CLK_TRAIL_FIELD                   (_MK_MASK_CONST(0xff) << SENSOR2CIL_TIMING_PKT_CLK_TRAIL_SHIFT)
+#define SENSOR2CIL_TIMING_PKT_CLK_TRAIL_RANGE                   _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(56)
+#define SENSOR2CIL_TIMING_PKT_CLK_TRAIL_ROW                     0
+
+#define SENSOR2CIL_TIMING_PKT_HS_EXIT_SHIFT                     _MK_SHIFT_CONST(64)
+#define SENSOR2CIL_TIMING_PKT_HS_EXIT_FIELD                     (_MK_MASK_CONST(0xff) << SENSOR2CIL_TIMING_PKT_HS_EXIT_SHIFT)
+#define SENSOR2CIL_TIMING_PKT_HS_EXIT_RANGE                     _MK_SHIFT_CONST(71):_MK_SHIFT_CONST(64)
+#define SENSOR2CIL_TIMING_PKT_HS_EXIT_ROW                       0
+
+// default to use RTL internal
+#define SENSOR2CIL_TIMING_PKT_RANDOM_SHIFT                      _MK_SHIFT_CONST(72)
+#define SENSOR2CIL_TIMING_PKT_RANDOM_FIELD                      (_MK_MASK_CONST(0x1) << SENSOR2CIL_TIMING_PKT_RANDOM_SHIFT)
+#define SENSOR2CIL_TIMING_PKT_RANDOM_RANGE                      _MK_SHIFT_CONST(72):_MK_SHIFT_CONST(72)
+#define SENSOR2CIL_TIMING_PKT_RANDOM_ROW                        0
+
+
+// Packet SENSOR2CIL_COMMAND_PKT
+#define SENSOR2CIL_COMMAND_PKT_SIZE 33
+
+// 
+// NO_OP    =0x0,   
+// ESC_ULPS =0x1, // escape mode: ultra low power state
+// ESC_LPDT =0x2, // escape mode: low power data transmission
+// ESC_RAR  =0x3, // escape mode: remote application reset
+// SOT_ERR  =0x4  // use SOT_CODE for SOT error injection
+// FR_HSCLK =0x5  // set high speed clock free running
+#define SENSOR2CIL_COMMAND_PKT_CMD_SHIFT                        _MK_SHIFT_CONST(0)
+#define SENSOR2CIL_COMMAND_PKT_CMD_FIELD                        (_MK_MASK_CONST(0x1f) << SENSOR2CIL_COMMAND_PKT_CMD_SHIFT)
+#define SENSOR2CIL_COMMAND_PKT_CMD_RANGE                        _MK_SHIFT_CONST(4):_MK_SHIFT_CONST(0)
+#define SENSOR2CIL_COMMAND_PKT_CMD_ROW                  0
+
+// sot or escape delay in esc mode
+#define SENSOR2CIL_COMMAND_PKT_PARAM_SHIFT                      _MK_SHIFT_CONST(5)
+#define SENSOR2CIL_COMMAND_PKT_PARAM_FIELD                      (_MK_MASK_CONST(0xff) << SENSOR2CIL_COMMAND_PKT_PARAM_SHIFT)
+#define SENSOR2CIL_COMMAND_PKT_PARAM_RANGE                      _MK_SHIFT_CONST(12):_MK_SHIFT_CONST(5)
+#define SENSOR2CIL_COMMAND_PKT_PARAM_ROW                        0
+
+#define SENSOR2CIL_COMMAND_PKT_ESC_MODE_ENTRY_SEQ_SHIFT                 _MK_SHIFT_CONST(13)
+#define SENSOR2CIL_COMMAND_PKT_ESC_MODE_ENTRY_SEQ_FIELD                 (_MK_MASK_CONST(0xff) << SENSOR2CIL_COMMAND_PKT_ESC_MODE_ENTRY_SEQ_SHIFT)
+#define SENSOR2CIL_COMMAND_PKT_ESC_MODE_ENTRY_SEQ_RANGE                 _MK_SHIFT_CONST(20):_MK_SHIFT_CONST(13)
+#define SENSOR2CIL_COMMAND_PKT_ESC_MODE_ENTRY_SEQ_ROW                   0
+
+#define SENSOR2CIL_COMMAND_PKT_ESC_MODE_CODE_SHIFT                      _MK_SHIFT_CONST(21)
+#define SENSOR2CIL_COMMAND_PKT_ESC_MODE_CODE_FIELD                      (_MK_MASK_CONST(0xff) << SENSOR2CIL_COMMAND_PKT_ESC_MODE_CODE_SHIFT)
+#define SENSOR2CIL_COMMAND_PKT_ESC_MODE_CODE_RANGE                      _MK_SHIFT_CONST(28):_MK_SHIFT_CONST(21)
+#define SENSOR2CIL_COMMAND_PKT_ESC_MODE_CODE_ROW                        0
+
+#define SENSOR2CIL_COMMAND_PKT_ESC_MODE_WIDTH_SHIFT                     _MK_SHIFT_CONST(29)
+#define SENSOR2CIL_COMMAND_PKT_ESC_MODE_WIDTH_FIELD                     (_MK_MASK_CONST(0xf) << SENSOR2CIL_COMMAND_PKT_ESC_MODE_WIDTH_SHIFT)
+#define SENSOR2CIL_COMMAND_PKT_ESC_MODE_WIDTH_RANGE                     _MK_SHIFT_CONST(32):_MK_SHIFT_CONST(29)
+#define SENSOR2CIL_COMMAND_PKT_ESC_MODE_WIDTH_ROW                       0
+
+
+// Packet CSI_HEADER
+#define CSI_HEADER_SIZE 32
+
+// Data type in packet
+#define CSI_HEADER_DATA_TYPE_SHIFT                      _MK_SHIFT_CONST(0)
+#define CSI_HEADER_DATA_TYPE_FIELD                      (_MK_MASK_CONST(0x3f) << CSI_HEADER_DATA_TYPE_SHIFT)
+#define CSI_HEADER_DATA_TYPE_RANGE                      _MK_SHIFT_CONST(5):_MK_SHIFT_CONST(0)
+#define CSI_HEADER_DATA_TYPE_ROW                        0
+
+// Virtual channel number
+#define CSI_HEADER_VIRTUAL_CHANNEL_SHIFT                        _MK_SHIFT_CONST(6)
+#define CSI_HEADER_VIRTUAL_CHANNEL_FIELD                        (_MK_MASK_CONST(0x3) << CSI_HEADER_VIRTUAL_CHANNEL_SHIFT)
+#define CSI_HEADER_VIRTUAL_CHANNEL_RANGE                        _MK_SHIFT_CONST(7):_MK_SHIFT_CONST(6)
+#define CSI_HEADER_VIRTUAL_CHANNEL_ROW                  0
+
+// Number of bytes in packet payload
+#define CSI_HEADER_WORD_COUNT_SHIFT                     _MK_SHIFT_CONST(8)
+#define CSI_HEADER_WORD_COUNT_FIELD                     (_MK_MASK_CONST(0xffff) << CSI_HEADER_WORD_COUNT_SHIFT)
+#define CSI_HEADER_WORD_COUNT_RANGE                     _MK_SHIFT_CONST(23):_MK_SHIFT_CONST(8)
+#define CSI_HEADER_WORD_COUNT_ROW                       0
+
+// Error correction code for packet
+#define CSI_HEADER_ECC_SHIFT                    _MK_SHIFT_CONST(24)
+#define CSI_HEADER_ECC_FIELD                    (_MK_MASK_CONST(0xff) << CSI_HEADER_ECC_SHIFT)
+#define CSI_HEADER_ECC_RANGE                    _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(24)
+#define CSI_HEADER_ECC_ROW                      0
+
+
+// Packet CSI_RAISE
+#define CSI_RAISE_SIZE 20
+
+#define CSI_RAISE_VECTOR_SHIFT                  _MK_SHIFT_CONST(0)
+#define CSI_RAISE_VECTOR_FIELD                  (_MK_MASK_CONST(0x1f) << CSI_RAISE_VECTOR_SHIFT)
+#define CSI_RAISE_VECTOR_RANGE                  _MK_SHIFT_CONST(4):_MK_SHIFT_CONST(0)
+#define CSI_RAISE_VECTOR_ROW                    0
+
+#define CSI_RAISE_COUNT_SHIFT                   _MK_SHIFT_CONST(8)
+#define CSI_RAISE_COUNT_FIELD                   (_MK_MASK_CONST(0xff) << CSI_RAISE_COUNT_SHIFT)
+#define CSI_RAISE_COUNT_RANGE                   _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(8)
+#define CSI_RAISE_COUNT_ROW                     0
+
+#define CSI_RAISE_CHID_SHIFT                    _MK_SHIFT_CONST(16)
+#define CSI_RAISE_CHID_FIELD                    (_MK_MASK_CONST(0xf) << CSI_RAISE_CHID_SHIFT)
+#define CSI_RAISE_CHID_RANGE                    _MK_SHIFT_CONST(19):_MK_SHIFT_CONST(16)
+#define CSI_RAISE_CHID_ROW                      0
+
+
+// Packet CSI_GENERIC_BYTE
+#define CSI_GENERIC_BYTE_SIZE 72
+
+#define CSI_GENERIC_BYTE_BYTE0_SHIFT                    _MK_SHIFT_CONST(0)
+#define CSI_GENERIC_BYTE_BYTE0_FIELD                    (_MK_MASK_CONST(0xff) << CSI_GENERIC_BYTE_BYTE0_SHIFT)
+#define CSI_GENERIC_BYTE_BYTE0_RANGE                    _MK_SHIFT_CONST(7):_MK_SHIFT_CONST(0)
+#define CSI_GENERIC_BYTE_BYTE0_ROW                      0
+
+#define CSI_GENERIC_BYTE_BYTE1_SHIFT                    _MK_SHIFT_CONST(8)
+#define CSI_GENERIC_BYTE_BYTE1_FIELD                    (_MK_MASK_CONST(0xff) << CSI_GENERIC_BYTE_BYTE1_SHIFT)
+#define CSI_GENERIC_BYTE_BYTE1_RANGE                    _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(8)
+#define CSI_GENERIC_BYTE_BYTE1_ROW                      0
+
+#define CSI_GENERIC_BYTE_BYTE2_SHIFT                    _MK_SHIFT_CONST(16)
+#define CSI_GENERIC_BYTE_BYTE2_FIELD                    (_MK_MASK_CONST(0xff) << CSI_GENERIC_BYTE_BYTE2_SHIFT)
+#define CSI_GENERIC_BYTE_BYTE2_RANGE                    _MK_SHIFT_CONST(23):_MK_SHIFT_CONST(16)
+#define CSI_GENERIC_BYTE_BYTE2_ROW                      0
+
+#define CSI_GENERIC_BYTE_BYTE3_SHIFT                    _MK_SHIFT_CONST(24)
+#define CSI_GENERIC_BYTE_BYTE3_FIELD                    (_MK_MASK_CONST(0xff) << CSI_GENERIC_BYTE_BYTE3_SHIFT)
+#define CSI_GENERIC_BYTE_BYTE3_RANGE                    _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(24)
+#define CSI_GENERIC_BYTE_BYTE3_ROW                      0
+
+#define CSI_GENERIC_BYTE_BYTE4_SHIFT                    _MK_SHIFT_CONST(32)
+#define CSI_GENERIC_BYTE_BYTE4_FIELD                    (_MK_MASK_CONST(0xff) << CSI_GENERIC_BYTE_BYTE4_SHIFT)
+#define CSI_GENERIC_BYTE_BYTE4_RANGE                    _MK_SHIFT_CONST(39):_MK_SHIFT_CONST(32)
+#define CSI_GENERIC_BYTE_BYTE4_ROW                      0
+
+#define CSI_GENERIC_BYTE_BYTE5_SHIFT                    _MK_SHIFT_CONST(40)
+#define CSI_GENERIC_BYTE_BYTE5_FIELD                    (_MK_MASK_CONST(0xff) << CSI_GENERIC_BYTE_BYTE5_SHIFT)
+#define CSI_GENERIC_BYTE_BYTE5_RANGE                    _MK_SHIFT_CONST(47):_MK_SHIFT_CONST(40)
+#define CSI_GENERIC_BYTE_BYTE5_ROW                      0
+
+#define CSI_GENERIC_BYTE_BYTE6_SHIFT                    _MK_SHIFT_CONST(48)
+#define CSI_GENERIC_BYTE_BYTE6_FIELD                    (_MK_MASK_CONST(0xff) << CSI_GENERIC_BYTE_BYTE6_SHIFT)
+#define CSI_GENERIC_BYTE_BYTE6_RANGE                    _MK_SHIFT_CONST(55):_MK_SHIFT_CONST(48)
+#define CSI_GENERIC_BYTE_BYTE6_ROW                      0
+
+#define CSI_GENERIC_BYTE_BYTE7_SHIFT                    _MK_SHIFT_CONST(56)
+#define CSI_GENERIC_BYTE_BYTE7_FIELD                    (_MK_MASK_CONST(0xff) << CSI_GENERIC_BYTE_BYTE7_SHIFT)
+#define CSI_GENERIC_BYTE_BYTE7_RANGE                    _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(56)
+#define CSI_GENERIC_BYTE_BYTE7_ROW                      0
+
+#define CSI_GENERIC_BYTE_BYTE8_SHIFT                    _MK_SHIFT_CONST(64)
+#define CSI_GENERIC_BYTE_BYTE8_FIELD                    (_MK_MASK_CONST(0xff) << CSI_GENERIC_BYTE_BYTE8_SHIFT)
+#define CSI_GENERIC_BYTE_BYTE8_RANGE                    _MK_SHIFT_CONST(71):_MK_SHIFT_CONST(64)
+#define CSI_GENERIC_BYTE_BYTE8_ROW                      0
+
+
+// Packet CSI_RGB_666
+#define CSI_RGB_666_SIZE 72
+
+#define CSI_RGB_666_B0_SHIFT                    _MK_SHIFT_CONST(0)
+#define CSI_RGB_666_B0_FIELD                    (_MK_MASK_CONST(0x3f) << CSI_RGB_666_B0_SHIFT)
+#define CSI_RGB_666_B0_RANGE                    _MK_SHIFT_CONST(5):_MK_SHIFT_CONST(0)
+#define CSI_RGB_666_B0_ROW                      0
+
+#define CSI_RGB_666_G0_SHIFT                    _MK_SHIFT_CONST(6)
+#define CSI_RGB_666_G0_FIELD                    (_MK_MASK_CONST(0x3f) << CSI_RGB_666_G0_SHIFT)
+#define CSI_RGB_666_G0_RANGE                    _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(6)
+#define CSI_RGB_666_G0_ROW                      0
+
+#define CSI_RGB_666_R0_SHIFT                    _MK_SHIFT_CONST(12)
+#define CSI_RGB_666_R0_FIELD                    (_MK_MASK_CONST(0x3f) << CSI_RGB_666_R0_SHIFT)
+#define CSI_RGB_666_R0_RANGE                    _MK_SHIFT_CONST(17):_MK_SHIFT_CONST(12)
+#define CSI_RGB_666_R0_ROW                      0
+
+#define CSI_RGB_666_B1_SHIFT                    _MK_SHIFT_CONST(18)
+#define CSI_RGB_666_B1_FIELD                    (_MK_MASK_CONST(0x3f) << CSI_RGB_666_B1_SHIFT)
+#define CSI_RGB_666_B1_RANGE                    _MK_SHIFT_CONST(23):_MK_SHIFT_CONST(18)
+#define CSI_RGB_666_B1_ROW                      0
+
+#define CSI_RGB_666_G1_SHIFT                    _MK_SHIFT_CONST(24)
+#define CSI_RGB_666_G1_FIELD                    (_MK_MASK_CONST(0x3f) << CSI_RGB_666_G1_SHIFT)
+#define CSI_RGB_666_G1_RANGE                    _MK_SHIFT_CONST(29):_MK_SHIFT_CONST(24)
+#define CSI_RGB_666_G1_ROW                      0
+
+#define CSI_RGB_666_R1_SHIFT                    _MK_SHIFT_CONST(30)
+#define CSI_RGB_666_R1_FIELD                    (_MK_MASK_CONST(0x3f) << CSI_RGB_666_R1_SHIFT)
+#define CSI_RGB_666_R1_RANGE                    _MK_SHIFT_CONST(35):_MK_SHIFT_CONST(30)
+#define CSI_RGB_666_R1_ROW                      0
+
+#define CSI_RGB_666_B2_SHIFT                    _MK_SHIFT_CONST(36)
+#define CSI_RGB_666_B2_FIELD                    (_MK_MASK_CONST(0x3f) << CSI_RGB_666_B2_SHIFT)
+#define CSI_RGB_666_B2_RANGE                    _MK_SHIFT_CONST(41):_MK_SHIFT_CONST(36)
+#define CSI_RGB_666_B2_ROW                      0
+
+#define CSI_RGB_666_G2_SHIFT                    _MK_SHIFT_CONST(42)
+#define CSI_RGB_666_G2_FIELD                    (_MK_MASK_CONST(0x3f) << CSI_RGB_666_G2_SHIFT)
+#define CSI_RGB_666_G2_RANGE                    _MK_SHIFT_CONST(47):_MK_SHIFT_CONST(42)
+#define CSI_RGB_666_G2_ROW                      0
+
+#define CSI_RGB_666_R2_SHIFT                    _MK_SHIFT_CONST(48)
+#define CSI_RGB_666_R2_FIELD                    (_MK_MASK_CONST(0x3f) << CSI_RGB_666_R2_SHIFT)
+#define CSI_RGB_666_R2_RANGE                    _MK_SHIFT_CONST(53):_MK_SHIFT_CONST(48)
+#define CSI_RGB_666_R2_ROW                      0
+
+#define CSI_RGB_666_B3_SHIFT                    _MK_SHIFT_CONST(54)
+#define CSI_RGB_666_B3_FIELD                    (_MK_MASK_CONST(0x3f) << CSI_RGB_666_B3_SHIFT)
+#define CSI_RGB_666_B3_RANGE                    _MK_SHIFT_CONST(59):_MK_SHIFT_CONST(54)
+#define CSI_RGB_666_B3_ROW                      0
+
+#define CSI_RGB_666_G3_SHIFT                    _MK_SHIFT_CONST(60)
+#define CSI_RGB_666_G3_FIELD                    (_MK_MASK_CONST(0x3f) << CSI_RGB_666_G3_SHIFT)
+#define CSI_RGB_666_G3_RANGE                    _MK_SHIFT_CONST(65):_MK_SHIFT_CONST(60)
+#define CSI_RGB_666_G3_ROW                      0
+
+#define CSI_RGB_666_R3_SHIFT                    _MK_SHIFT_CONST(66)
+#define CSI_RGB_666_R3_FIELD                    (_MK_MASK_CONST(0x3f) << CSI_RGB_666_R3_SHIFT)
+#define CSI_RGB_666_R3_RANGE                    _MK_SHIFT_CONST(71):_MK_SHIFT_CONST(66)
+#define CSI_RGB_666_R3_ROW                      0
+
+
+// Packet CSI_RGB_565
+#define CSI_RGB_565_SIZE 16
+
+#define CSI_RGB_565_B0_SHIFT                    _MK_SHIFT_CONST(0)
+#define CSI_RGB_565_B0_FIELD                    (_MK_MASK_CONST(0x1f) << CSI_RGB_565_B0_SHIFT)
+#define CSI_RGB_565_B0_RANGE                    _MK_SHIFT_CONST(4):_MK_SHIFT_CONST(0)
+#define CSI_RGB_565_B0_ROW                      0
+
+#define CSI_RGB_565_G0_SHIFT                    _MK_SHIFT_CONST(5)
+#define CSI_RGB_565_G0_FIELD                    (_MK_MASK_CONST(0x3f) << CSI_RGB_565_G0_SHIFT)
+#define CSI_RGB_565_G0_RANGE                    _MK_SHIFT_CONST(10):_MK_SHIFT_CONST(5)
+#define CSI_RGB_565_G0_ROW                      0
+
+#define CSI_RGB_565_R0_SHIFT                    _MK_SHIFT_CONST(11)
+#define CSI_RGB_565_R0_FIELD                    (_MK_MASK_CONST(0x1f) << CSI_RGB_565_R0_SHIFT)
+#define CSI_RGB_565_R0_RANGE                    _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(11)
+#define CSI_RGB_565_R0_ROW                      0
+
+
+// Packet CSI_RAW_6
+#define CSI_RAW_6_SIZE 24
+
+#define CSI_RAW_6_S0_SHIFT                      _MK_SHIFT_CONST(0)
+#define CSI_RAW_6_S0_FIELD                      (_MK_MASK_CONST(0x3f) << CSI_RAW_6_S0_SHIFT)
+#define CSI_RAW_6_S0_RANGE                      _MK_SHIFT_CONST(5):_MK_SHIFT_CONST(0)
+#define CSI_RAW_6_S0_ROW                        0
+
+#define CSI_RAW_6_S1_SHIFT                      _MK_SHIFT_CONST(6)
+#define CSI_RAW_6_S1_FIELD                      (_MK_MASK_CONST(0x3f) << CSI_RAW_6_S1_SHIFT)
+#define CSI_RAW_6_S1_RANGE                      _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(6)
+#define CSI_RAW_6_S1_ROW                        0
+
+#define CSI_RAW_6_S2_SHIFT                      _MK_SHIFT_CONST(12)
+#define CSI_RAW_6_S2_FIELD                      (_MK_MASK_CONST(0x3f) << CSI_RAW_6_S2_SHIFT)
+#define CSI_RAW_6_S2_RANGE                      _MK_SHIFT_CONST(17):_MK_SHIFT_CONST(12)
+#define CSI_RAW_6_S2_ROW                        0
+
+#define CSI_RAW_6_S3_SHIFT                      _MK_SHIFT_CONST(18)
+#define CSI_RAW_6_S3_FIELD                      (_MK_MASK_CONST(0x3f) << CSI_RAW_6_S3_SHIFT)
+#define CSI_RAW_6_S3_RANGE                      _MK_SHIFT_CONST(23):_MK_SHIFT_CONST(18)
+#define CSI_RAW_6_S3_ROW                        0
+
+
+// Packet CSI_RAW_7
+#define CSI_RAW_7_SIZE 56
+
+#define CSI_RAW_7_S0_SHIFT                      _MK_SHIFT_CONST(0)
+#define CSI_RAW_7_S0_FIELD                      (_MK_MASK_CONST(0x7f) << CSI_RAW_7_S0_SHIFT)
+#define CSI_RAW_7_S0_RANGE                      _MK_SHIFT_CONST(6):_MK_SHIFT_CONST(0)
+#define CSI_RAW_7_S0_ROW                        0
+
+#define CSI_RAW_7_S1_SHIFT                      _MK_SHIFT_CONST(7)
+#define CSI_RAW_7_S1_FIELD                      (_MK_MASK_CONST(0x7f) << CSI_RAW_7_S1_SHIFT)
+#define CSI_RAW_7_S1_RANGE                      _MK_SHIFT_CONST(13):_MK_SHIFT_CONST(7)
+#define CSI_RAW_7_S1_ROW                        0
+
+#define CSI_RAW_7_S2_SHIFT                      _MK_SHIFT_CONST(14)
+#define CSI_RAW_7_S2_FIELD                      (_MK_MASK_CONST(0x7f) << CSI_RAW_7_S2_SHIFT)
+#define CSI_RAW_7_S2_RANGE                      _MK_SHIFT_CONST(20):_MK_SHIFT_CONST(14)
+#define CSI_RAW_7_S2_ROW                        0
+
+#define CSI_RAW_7_S3_SHIFT                      _MK_SHIFT_CONST(21)
+#define CSI_RAW_7_S3_FIELD                      (_MK_MASK_CONST(0x7f) << CSI_RAW_7_S3_SHIFT)
+#define CSI_RAW_7_S3_RANGE                      _MK_SHIFT_CONST(27):_MK_SHIFT_CONST(21)
+#define CSI_RAW_7_S3_ROW                        0
+
+#define CSI_RAW_7_S4_SHIFT                      _MK_SHIFT_CONST(28)
+#define CSI_RAW_7_S4_FIELD                      (_MK_MASK_CONST(0x7f) << CSI_RAW_7_S4_SHIFT)
+#define CSI_RAW_7_S4_RANGE                      _MK_SHIFT_CONST(34):_MK_SHIFT_CONST(28)
+#define CSI_RAW_7_S4_ROW                        0
+
+#define CSI_RAW_7_S5_SHIFT                      _MK_SHIFT_CONST(35)
+#define CSI_RAW_7_S5_FIELD                      (_MK_MASK_CONST(0x7f) << CSI_RAW_7_S5_SHIFT)
+#define CSI_RAW_7_S5_RANGE                      _MK_SHIFT_CONST(41):_MK_SHIFT_CONST(35)
+#define CSI_RAW_7_S5_ROW                        0
+
+#define CSI_RAW_7_S6_SHIFT                      _MK_SHIFT_CONST(42)
+#define CSI_RAW_7_S6_FIELD                      (_MK_MASK_CONST(0x7f) << CSI_RAW_7_S6_SHIFT)
+#define CSI_RAW_7_S6_RANGE                      _MK_SHIFT_CONST(48):_MK_SHIFT_CONST(42)
+#define CSI_RAW_7_S6_ROW                        0
+
+#define CSI_RAW_7_S7_SHIFT                      _MK_SHIFT_CONST(49)
+#define CSI_RAW_7_S7_FIELD                      (_MK_MASK_CONST(0x7f) << CSI_RAW_7_S7_SHIFT)
+#define CSI_RAW_7_S7_RANGE                      _MK_SHIFT_CONST(55):_MK_SHIFT_CONST(49)
+#define CSI_RAW_7_S7_ROW                        0
+
+
+// Packet CSI_RAW_10
+#define CSI_RAW_10_SIZE 40
+
+#define CSI_RAW_10_S0_SHIFT                     _MK_SHIFT_CONST(0)
+#define CSI_RAW_10_S0_FIELD                     (_MK_MASK_CONST(0xff) << CSI_RAW_10_S0_SHIFT)
+#define CSI_RAW_10_S0_RANGE                     _MK_SHIFT_CONST(7):_MK_SHIFT_CONST(0)
+#define CSI_RAW_10_S0_ROW                       0
+
+#define CSI_RAW_10_S1_SHIFT                     _MK_SHIFT_CONST(8)
+#define CSI_RAW_10_S1_FIELD                     (_MK_MASK_CONST(0xff) << CSI_RAW_10_S1_SHIFT)
+#define CSI_RAW_10_S1_RANGE                     _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(8)
+#define CSI_RAW_10_S1_ROW                       0
+
+#define CSI_RAW_10_S2_SHIFT                     _MK_SHIFT_CONST(16)
+#define CSI_RAW_10_S2_FIELD                     (_MK_MASK_CONST(0xff) << CSI_RAW_10_S2_SHIFT)
+#define CSI_RAW_10_S2_RANGE                     _MK_SHIFT_CONST(23):_MK_SHIFT_CONST(16)
+#define CSI_RAW_10_S2_ROW                       0
+
+#define CSI_RAW_10_S3_SHIFT                     _MK_SHIFT_CONST(24)
+#define CSI_RAW_10_S3_FIELD                     (_MK_MASK_CONST(0xff) << CSI_RAW_10_S3_SHIFT)
+#define CSI_RAW_10_S3_RANGE                     _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(24)
+#define CSI_RAW_10_S3_ROW                       0
+
+#define CSI_RAW_10_L0_SHIFT                     _MK_SHIFT_CONST(32)
+#define CSI_RAW_10_L0_FIELD                     (_MK_MASK_CONST(0x3) << CSI_RAW_10_L0_SHIFT)
+#define CSI_RAW_10_L0_RANGE                     _MK_SHIFT_CONST(33):_MK_SHIFT_CONST(32)
+#define CSI_RAW_10_L0_ROW                       0
+
+#define CSI_RAW_10_L1_SHIFT                     _MK_SHIFT_CONST(34)
+#define CSI_RAW_10_L1_FIELD                     (_MK_MASK_CONST(0x3) << CSI_RAW_10_L1_SHIFT)
+#define CSI_RAW_10_L1_RANGE                     _MK_SHIFT_CONST(35):_MK_SHIFT_CONST(34)
+#define CSI_RAW_10_L1_ROW                       0
+
+#define CSI_RAW_10_L2_SHIFT                     _MK_SHIFT_CONST(36)
+#define CSI_RAW_10_L2_FIELD                     (_MK_MASK_CONST(0x3) << CSI_RAW_10_L2_SHIFT)
+#define CSI_RAW_10_L2_RANGE                     _MK_SHIFT_CONST(37):_MK_SHIFT_CONST(36)
+#define CSI_RAW_10_L2_ROW                       0
+
+#define CSI_RAW_10_L3_SHIFT                     _MK_SHIFT_CONST(38)
+#define CSI_RAW_10_L3_FIELD                     (_MK_MASK_CONST(0x3) << CSI_RAW_10_L3_SHIFT)
+#define CSI_RAW_10_L3_RANGE                     _MK_SHIFT_CONST(39):_MK_SHIFT_CONST(38)
+#define CSI_RAW_10_L3_ROW                       0
+
+
+// Packet CSI_RAW_12
+#define CSI_RAW_12_SIZE 24
+
+#define CSI_RAW_12_S0_SHIFT                     _MK_SHIFT_CONST(0)
+#define CSI_RAW_12_S0_FIELD                     (_MK_MASK_CONST(0xff) << CSI_RAW_12_S0_SHIFT)
+#define CSI_RAW_12_S0_RANGE                     _MK_SHIFT_CONST(7):_MK_SHIFT_CONST(0)
+#define CSI_RAW_12_S0_ROW                       0
+
+#define CSI_RAW_12_S1_SHIFT                     _MK_SHIFT_CONST(8)
+#define CSI_RAW_12_S1_FIELD                     (_MK_MASK_CONST(0xff) << CSI_RAW_12_S1_SHIFT)
+#define CSI_RAW_12_S1_RANGE                     _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(8)
+#define CSI_RAW_12_S1_ROW                       0
+
+#define CSI_RAW_12_L0_SHIFT                     _MK_SHIFT_CONST(16)
+#define CSI_RAW_12_L0_FIELD                     (_MK_MASK_CONST(0xf) << CSI_RAW_12_L0_SHIFT)
+#define CSI_RAW_12_L0_RANGE                     _MK_SHIFT_CONST(19):_MK_SHIFT_CONST(16)
+#define CSI_RAW_12_L0_ROW                       0
+
+#define CSI_RAW_12_L1_SHIFT                     _MK_SHIFT_CONST(20)
+#define CSI_RAW_12_L1_FIELD                     (_MK_MASK_CONST(0xf) << CSI_RAW_12_L1_SHIFT)
+#define CSI_RAW_12_L1_RANGE                     _MK_SHIFT_CONST(23):_MK_SHIFT_CONST(20)
+#define CSI_RAW_12_L1_ROW                       0
+
+
+// Packet CSI_RAW_14
+#define CSI_RAW_14_SIZE 56
+
+#define CSI_RAW_14_S0_SHIFT                     _MK_SHIFT_CONST(0)
+#define CSI_RAW_14_S0_FIELD                     (_MK_MASK_CONST(0xff) << CSI_RAW_14_S0_SHIFT)
+#define CSI_RAW_14_S0_RANGE                     _MK_SHIFT_CONST(7):_MK_SHIFT_CONST(0)
+#define CSI_RAW_14_S0_ROW                       0
+
+#define CSI_RAW_14_S1_SHIFT                     _MK_SHIFT_CONST(8)
+#define CSI_RAW_14_S1_FIELD                     (_MK_MASK_CONST(0xff) << CSI_RAW_14_S1_SHIFT)
+#define CSI_RAW_14_S1_RANGE                     _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(8)
+#define CSI_RAW_14_S1_ROW                       0
+
+#define CSI_RAW_14_S2_SHIFT                     _MK_SHIFT_CONST(16)
+#define CSI_RAW_14_S2_FIELD                     (_MK_MASK_CONST(0xff) << CSI_RAW_14_S2_SHIFT)
+#define CSI_RAW_14_S2_RANGE                     _MK_SHIFT_CONST(23):_MK_SHIFT_CONST(16)
+#define CSI_RAW_14_S2_ROW                       0
+
+#define CSI_RAW_14_S3_SHIFT                     _MK_SHIFT_CONST(24)
+#define CSI_RAW_14_S3_FIELD                     (_MK_MASK_CONST(0xff) << CSI_RAW_14_S3_SHIFT)
+#define CSI_RAW_14_S3_RANGE                     _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(24)
+#define CSI_RAW_14_S3_ROW                       0
+
+#define CSI_RAW_14_L0_SHIFT                     _MK_SHIFT_CONST(32)
+#define CSI_RAW_14_L0_FIELD                     (_MK_MASK_CONST(0x3f) << CSI_RAW_14_L0_SHIFT)
+#define CSI_RAW_14_L0_RANGE                     _MK_SHIFT_CONST(37):_MK_SHIFT_CONST(32)
+#define CSI_RAW_14_L0_ROW                       0
+
+#define CSI_RAW_14_L1_SHIFT                     _MK_SHIFT_CONST(38)
+#define CSI_RAW_14_L1_FIELD                     (_MK_MASK_CONST(0x3f) << CSI_RAW_14_L1_SHIFT)
+#define CSI_RAW_14_L1_RANGE                     _MK_SHIFT_CONST(43):_MK_SHIFT_CONST(38)
+#define CSI_RAW_14_L1_ROW                       0
+
+#define CSI_RAW_14_L2_SHIFT                     _MK_SHIFT_CONST(44)
+#define CSI_RAW_14_L2_FIELD                     (_MK_MASK_CONST(0x3f) << CSI_RAW_14_L2_SHIFT)
+#define CSI_RAW_14_L2_RANGE                     _MK_SHIFT_CONST(49):_MK_SHIFT_CONST(44)
+#define CSI_RAW_14_L2_ROW                       0
+
+#define CSI_RAW_14_L3_SHIFT                     _MK_SHIFT_CONST(50)
+#define CSI_RAW_14_L3_FIELD                     (_MK_MASK_CONST(0x3f) << CSI_RAW_14_L3_SHIFT)
+#define CSI_RAW_14_L3_RANGE                     _MK_SHIFT_CONST(55):_MK_SHIFT_CONST(50)
+#define CSI_RAW_14_L3_ROW                       0
+
+#define CSI_DT_SSP_FS   0
+#define CSI_DT_SSP_FE   1
+#define CSI_DT_SSP_LS   2
+#define CSI_DT_SSP_LE   3
+#define CSI_DT_SSP_R1   4
+#define CSI_DT_SSP_R2   5
+#define CSI_DT_SSP_R3   6
+#define CSI_DT_SSP_R4   7
+#define CSI_DT_GSP_G1   8
+#define CSI_DT_GSP_G2   9
+#define CSI_DT_GSP_G3   10
+#define CSI_DT_GSP_G4   11
+#define CSI_DT_GSP_G5   12
+#define CSI_DT_GSP_G6   13
+#define CSI_DT_GSP_G7   14
+#define CSI_DT_GSP_G8   15
+#define CSI_DT_GED_NULL 16
+#define CSI_DT_GED_BLANK        17
+#define CSI_DT_GED_ED   18
+#define CSI_DT_GED_R1   19
+#define CSI_DT_GED_R2   20
+#define CSI_DT_GED_R3   21
+#define CSI_DT_GED_R4   22
+#define CSI_DT_GED_R5   23
+#define CSI_DT_YUV_420_8        24
+#define CSI_DT_YUV_420_10       25
+#define CSI_DT_YUV_420_L_8      26
+#define CSI_DT_YUV_R1   27
+#define CSI_DT_YUV_420_CSPS_8   28
+#define CSI_DT_YUV_420_CSPS_10  29
+#define CSI_DT_YUV_422_8        30
+#define CSI_DT_YUV_422_10       31
+#define CSI_DT_RGB_444  32
+#define CSI_DT_RGB_555  33
+#define CSI_DT_RGB_565  34
+#define CSI_DT_RGB_666  35
+#define CSI_DT_RGB_888  36
+#define CSI_DT_RGB_R1   37
+#define CSI_DT_RGB_R2   38
+#define CSI_DT_RGB_R3   39
+#define CSI_DT_RAW_6    40
+#define CSI_DT_RAW_7    41
+#define CSI_DT_RAW_8    42
+#define CSI_DT_RAW_10   43
+#define CSI_DT_RAW_12   44
+#define CSI_DT_RAW_14   45
+#define CSI_DT_RAW_R1   46
+#define CSI_DT_RAW_R2   47
+#define CSI_DT_UED_U1   48
+#define CSI_DT_UED_U2   49
+#define CSI_DT_UED_U3   50
+#define CSI_DT_UED_U4   51
+#define CSI_DT_UED_R1   52
+#define CSI_DT_UED_R2   53
+#define CSI_DT_UED_R3   54
+#define CSI_DT_UED_R4   55
+
+// Packet D
+#define D_SIZE 6
+
+// SSP = Synchronization Short Packet
+// Reserved
+#define D_T_SHIFT                       _MK_SHIFT_CONST(0)
+#define D_T_FIELD                       (_MK_MASK_CONST(0x3f) << D_T_SHIFT)
+#define D_T_RANGE                       _MK_SHIFT_CONST(5):_MK_SHIFT_CONST(0)
+#define D_T_ROW                 0
+#define D_T_SSP_FS                      _MK_ENUM_CONST(0)    // // Frame Start
+
+#define D_T_SSP_FE                      _MK_ENUM_CONST(1)    // // Frame End
+
+#define D_T_SSP_LS                      _MK_ENUM_CONST(2)    // // Line Start
+
+#define D_T_SSP_LE                      _MK_ENUM_CONST(3)    // // Line End
+
+#define D_T_SSP_R1                      _MK_ENUM_CONST(4)    // // Reserved 1
+
+#define D_T_SSP_R2                      _MK_ENUM_CONST(5)    // // Reserved 2
+
+#define D_T_SSP_R3                      _MK_ENUM_CONST(6)    // // Reserved 3
+
+#define D_T_SSP_R4                      _MK_ENUM_CONST(7)    // // Reserved 4
+// GSP = Generic Short Packet
+
+#define D_T_GSP_G1                      _MK_ENUM_CONST(8)    // // Generic Short Packet Code 1
+
+#define D_T_GSP_G2                      _MK_ENUM_CONST(9)    // // Generic Short Packet Code 2
+
+#define D_T_GSP_G3                      _MK_ENUM_CONST(10)    // // Generic Short Packet Code 3
+
+#define D_T_GSP_G4                      _MK_ENUM_CONST(11)    // // Generic Short Packet Code 4
+
+#define D_T_GSP_G5                      _MK_ENUM_CONST(12)    // // Generic Short Packet Code 5
+
+#define D_T_GSP_G6                      _MK_ENUM_CONST(13)    // // Generic Short Packet Code 6
+
+#define D_T_GSP_G7                      _MK_ENUM_CONST(14)    // // Generic Short Packet Code 7
+
+#define D_T_GSP_G8                      _MK_ENUM_CONST(15)    // // Generic Short Packet Code 8
+// GED = Generic 8-bit Data
+
+#define D_T_GED_NULL                    _MK_ENUM_CONST(16)    // // Null 
+
+#define D_T_GED_BLANK                   _MK_ENUM_CONST(17)    // // Blanking Data 
+
+#define D_T_GED_ED                      _MK_ENUM_CONST(18)    // // Embedded 8-bit non Image Data
+
+#define D_T_GED_R1                      _MK_ENUM_CONST(19)    // // Reserved
+
+#define D_T_GED_R2                      _MK_ENUM_CONST(20)    // // Reserved
+
+#define D_T_GED_R3                      _MK_ENUM_CONST(21)    // // Reserved
+
+#define D_T_GED_R4                      _MK_ENUM_CONST(22)    // // Reserved
+
+#define D_T_GED_R5                      _MK_ENUM_CONST(23)    // // Reserved
+// YUV = YUV Image Data Types
+
+#define D_T_YUV_420_8                   _MK_ENUM_CONST(24)    // // YUV420 8-bit
+
+#define D_T_YUV_420_10                  _MK_ENUM_CONST(25)    // // YUV420 10-bit
+
+#define D_T_YUV_420_L_8                 _MK_ENUM_CONST(26)    // // Legacy YUV420 8-bit
+
+#define D_T_YUV_R1                      _MK_ENUM_CONST(27)    // // Reserved
+
+#define D_T_YUV_420_CSPS_8                      _MK_ENUM_CONST(28)    // // YUV420 8-bit (Chroma Shifted Pixel Sampling)
+
+#define D_T_YUV_420_CSPS_10                     _MK_ENUM_CONST(29)    // // YUV420 10-bit (Chroma Shifted Pixel Sampling)
+
+#define D_T_YUV_422_8                   _MK_ENUM_CONST(30)    // // YUV422 8-bit
+
+#define D_T_YUV_422_10                  _MK_ENUM_CONST(31)    // // YUV422 10-bit
+// RGB = RGB Image Data Types
+
+#define D_T_RGB_444                     _MK_ENUM_CONST(32)    // // RGB444
+
+#define D_T_RGB_555                     _MK_ENUM_CONST(33)    // // RGB555
+
+#define D_T_RGB_565                     _MK_ENUM_CONST(34)    // // RGB565
+
+#define D_T_RGB_666                     _MK_ENUM_CONST(35)    // // RGB666
+
+#define D_T_RGB_888                     _MK_ENUM_CONST(36)    // // RGB888
+
+#define D_T_RGB_R1                      _MK_ENUM_CONST(37)    // // Reserved
+
+#define D_T_RGB_R2                      _MK_ENUM_CONST(38)    // // Reserved
+
+#define D_T_RGB_R3                      _MK_ENUM_CONST(39)    // // Reserved
+// RAW Image Data Types
+
+#define D_T_RAW_6                       _MK_ENUM_CONST(40)    // // RAW6
+
+#define D_T_RAW_7                       _MK_ENUM_CONST(41)    // // RAW7
+
+#define D_T_RAW_8                       _MK_ENUM_CONST(42)    // // RAW8
+
+#define D_T_RAW_10                      _MK_ENUM_CONST(43)    // // RAW10
+
+#define D_T_RAW_12                      _MK_ENUM_CONST(44)    // // RAW12
+
+#define D_T_RAW_14                      _MK_ENUM_CONST(45)    // // RAW14
+
+#define D_T_RAW_R1                      _MK_ENUM_CONST(46)    // // Reserved
+
+#define D_T_RAW_R2                      _MK_ENUM_CONST(47)    // // Reserved
+// UED = User Defined 8-bit Data
+
+#define D_T_UED_U1                      _MK_ENUM_CONST(48)    // // User Defined 8-bit Data Type 1
+
+#define D_T_UED_U2                      _MK_ENUM_CONST(49)    // // User Defined 8-bit Data Type 2
+
+#define D_T_UED_U3                      _MK_ENUM_CONST(50)    // // User Defined 8-bit Data Type 3
+
+#define D_T_UED_U4                      _MK_ENUM_CONST(51)    // // User Defined 8-bit Data Type 4
+
+#define D_T_UED_R1                      _MK_ENUM_CONST(52)    // // Reserved
+
+#define D_T_UED_R2                      _MK_ENUM_CONST(53)    // // Reserved
+
+#define D_T_UED_R3                      _MK_ENUM_CONST(54)    // // Reserved
+
+#define D_T_UED_R4                      _MK_ENUM_CONST(55)
+
+
+//
+// REGISTER LIST
+//
+#define LIST_ARVI_REGS(_op_) \
+_op_(VI_OUT_1_INCR_SYNCPT_0) \
+_op_(VI_OUT_1_INCR_SYNCPT_CNTRL_0) \
+_op_(VI_OUT_1_INCR_SYNCPT_ERROR_0) \
+_op_(VI_OUT_2_INCR_SYNCPT_0) \
+_op_(VI_OUT_2_INCR_SYNCPT_CNTRL_0) \
+_op_(VI_OUT_2_INCR_SYNCPT_ERROR_0) \
+_op_(VI_MISC_INCR_SYNCPT_0) \
+_op_(VI_MISC_INCR_SYNCPT_CNTRL_0) \
+_op_(VI_MISC_INCR_SYNCPT_ERROR_0) \
+_op_(VI_CONT_SYNCPT_OUT_1_0) \
+_op_(VI_CONT_SYNCPT_OUT_2_0) \
+_op_(VI_CONT_SYNCPT_VIP_VSYNC_0) \
+_op_(VI_CONT_SYNCPT_VI2EPP_0) \
+_op_(VI_CONT_SYNCPT_CSI_PPA_FRAME_START_0) \
+_op_(VI_CONT_SYNCPT_CSI_PPA_FRAME_END_0) \
+_op_(VI_CONT_SYNCPT_CSI_PPB_FRAME_START_0) \
+_op_(VI_CONT_SYNCPT_CSI_PPB_FRAME_END_0) \
+_op_(VI_CTXSW_0) \
+_op_(VI_INTSTATUS_0) \
+_op_(VI_VI_INPUT_CONTROL_0) \
+_op_(VI_VI_CORE_CONTROL_0) \
+_op_(VI_VI_FIRST_OUTPUT_CONTROL_0) \
+_op_(VI_VI_SECOND_OUTPUT_CONTROL_0) \
+_op_(VI_HOST_INPUT_FRAME_SIZE_0) \
+_op_(VI_HOST_H_ACTIVE_0) \
+_op_(VI_HOST_V_ACTIVE_0) \
+_op_(VI_VIP_H_ACTIVE_0) \
+_op_(VI_VIP_V_ACTIVE_0) \
+_op_(VI_VI_PEER_CONTROL_0) \
+_op_(VI_VI_DMA_SELECT_0) \
+_op_(VI_HOST_DMA_WRITE_BUFFER_0) \
+_op_(VI_HOST_DMA_BASE_ADDRESS_0) \
+_op_(VI_HOST_DMA_WRITE_BUFFER_STATUS_0) \
+_op_(VI_HOST_DMA_WRITE_PEND_BUFCOUNT_0) \
+_op_(VI_VB0_START_ADDRESS_FIRST_0) \
+_op_(VI_VB0_BASE_ADDRESS_FIRST_0) \
+_op_(VI_VB0_START_ADDRESS_U_0) \
+_op_(VI_VB0_BASE_ADDRESS_U_0) \
+_op_(VI_VB0_START_ADDRESS_V_0) \
+_op_(VI_VB0_BASE_ADDRESS_V_0) \
+_op_(VI_VB0_SCRATCH_ADDRESS_UV_0) \
+_op_(VI_FIRST_OUTPUT_FRAME_SIZE_0) \
+_op_(VI_VB0_COUNT_FIRST_0) \
+_op_(VI_VB0_SIZE_FIRST_0) \
+_op_(VI_VB0_BUFFER_STRIDE_FIRST_0) \
+_op_(VI_VB0_START_ADDRESS_SECOND_0) \
+_op_(VI_VB0_BASE_ADDRESS_SECOND_0) \
+_op_(VI_SECOND_OUTPUT_FRAME_SIZE_0) \
+_op_(VI_VB0_COUNT_SECOND_0) \
+_op_(VI_VB0_SIZE_SECOND_0) \
+_op_(VI_VB0_BUFFER_STRIDE_SECOND_0) \
+_op_(VI_H_LPF_CONTROL_0) \
+_op_(VI_H_DOWNSCALE_CONTROL_0) \
+_op_(VI_V_DOWNSCALE_CONTROL_0) \
+_op_(VI_CSC_Y_0) \
+_op_(VI_CSC_UV_R_0) \
+_op_(VI_CSC_UV_G_0) \
+_op_(VI_CSC_UV_B_0) \
+_op_(VI_CSC_ALPHA_0) \
+_op_(VI_HOST_VSYNC_0) \
+_op_(VI_COMMAND_0) \
+_op_(VI_HOST_FIFO_STATUS_0) \
+_op_(VI_INTERRUPT_MASK_0) \
+_op_(VI_INTERRUPT_TYPE_SELECT_0) \
+_op_(VI_INTERRUPT_POLARITY_SELECT_0) \
+_op_(VI_INTERRUPT_STATUS_0) \
+_op_(VI_VIP_INPUT_STATUS_0) \
+_op_(VI_VIDEO_BUFFER_STATUS_0) \
+_op_(VI_SYNC_OUTPUT_0) \
+_op_(VI_VVS_OUTPUT_DELAY_0) \
+_op_(VI_PWM_CONTROL_0) \
+_op_(VI_PWM_SELECT_PULSE_A_0) \
+_op_(VI_PWM_SELECT_PULSE_B_0) \
+_op_(VI_PWM_SELECT_PULSE_C_0) \
+_op_(VI_PWM_SELECT_PULSE_D_0) \
+_op_(VI_VI_DATA_INPUT_CONTROL_0) \
+_op_(VI_PIN_INPUT_ENABLE_0) \
+_op_(VI_PIN_OUTPUT_ENABLE_0) \
+_op_(VI_PIN_INVERSION_0) \
+_op_(VI_PIN_INPUT_DATA_0) \
+_op_(VI_PIN_OUTPUT_DATA_0) \
+_op_(VI_PIN_OUTPUT_SELECT_0) \
+_op_(VI_RAISE_VIP_BUFFER_FIRST_OUTPUT_0) \
+_op_(VI_RAISE_VIP_FRAME_FIRST_OUTPUT_0) \
+_op_(VI_RAISE_VIP_BUFFER_SECOND_OUTPUT_0) \
+_op_(VI_RAISE_VIP_FRAME_SECOND_OUTPUT_0) \
+_op_(VI_RAISE_HOST_FIRST_OUTPUT_0) \
+_op_(VI_RAISE_HOST_SECOND_OUTPUT_0) \
+_op_(VI_RAISE_EPP_0) \
+_op_(VI_CAMERA_CONTROL_0) \
+_op_(VI_VI_ENABLE_0) \
+_op_(VI_VI_ENABLE_2_0) \
+_op_(VI_VI_RAISE_0) \
+_op_(VI_Y_FIFO_WRITE_0) \
+_op_(VI_U_FIFO_WRITE_0) \
+_op_(VI_V_FIFO_WRITE_0) \
+_op_(VI_VI_MCCIF_FIFOCTRL_0) \
+_op_(VI_TIMEOUT_WCOAL_VI_0) \
+_op_(VI_MCCIF_VIRUV_HP_0) \
+_op_(VI_MCCIF_VIWSB_HP_0) \
+_op_(VI_MCCIF_VIWU_HP_0) \
+_op_(VI_MCCIF_VIWV_HP_0) \
+_op_(VI_MCCIF_VIWY_HP_0) \
+_op_(VI_CSI_PPA_RAISE_FRAME_START_0) \
+_op_(VI_CSI_PPA_RAISE_FRAME_END_0) \
+_op_(VI_CSI_PPB_RAISE_FRAME_START_0) \
+_op_(VI_CSI_PPB_RAISE_FRAME_END_0) \
+_op_(VI_CSI_PPA_H_ACTIVE_0) \
+_op_(VI_CSI_PPA_V_ACTIVE_0) \
+_op_(VI_CSI_PPB_H_ACTIVE_0) \
+_op_(VI_CSI_PPB_V_ACTIVE_0) \
+_op_(VI_ISP_H_ACTIVE_0) \
+_op_(VI_ISP_V_ACTIVE_0) \
+_op_(VI_STREAM_1_RESOURCE_DEFINE_0) \
+_op_(VI_STREAM_2_RESOURCE_DEFINE_0) \
+_op_(VI_RAISE_STREAM_1_DONE_0) \
+_op_(VI_RAISE_STREAM_2_DONE_0) \
+_op_(VI_TS_MODE_0) \
+_op_(VI_TS_CONTROL_0) \
+_op_(VI_TS_PACKET_COUNT_0) \
+_op_(VI_TS_ERROR_COUNT_0) \
+_op_(VI_TS_CPU_FLOW_CTL_0) \
+_op_(VI_VB0_CHROMA_BUFFER_STRIDE_FIRST_0) \
+_op_(VI_VB0_CHROMA_LINE_STRIDE_FIRST_0) \
+_op_(VI_EPP_LINES_PER_BUFFER_0) \
+_op_(VI_BUFFER_RELEASE_OUTPUT1_0) \
+_op_(VI_BUFFER_RELEASE_OUTPUT2_0) \
+_op_(VI_DEBUG_FLOW_CONTROL_COUNTER_OUTPUT1_0) \
+_op_(VI_DEBUG_FLOW_CONTROL_COUNTER_OUTPUT2_0) \
+_op_(VI_TERMINATE_BW_FIRST_0) \
+_op_(VI_TERMINATE_BW_SECOND_0) \
+_op_(VI_VB0_FIRST_BUFFER_ADDR_MODE_0) \
+_op_(VI_VB0_SECOND_BUFFER_ADDR_MODE_0) \
+_op_(VI_RESERVE_0_0) \
+_op_(VI_RESERVE_1_0) \
+_op_(VI_RESERVE_2_0) \
+_op_(VI_RESERVE_3_0) \
+_op_(VI_RESERVE_4_0) \
+_op_(CSI_VI_INPUT_STREAM_CONTROL_0) \
+_op_(CSI_HOST_INPUT_STREAM_CONTROL_0) \
+_op_(CSI_INPUT_STREAM_A_CONTROL_0) \
+_op_(CSI_PIXEL_STREAM_A_CONTROL0_0) \
+_op_(CSI_PIXEL_STREAM_A_CONTROL1_0) \
+_op_(CSI_PIXEL_STREAM_A_WORD_COUNT_0) \
+_op_(CSI_PIXEL_STREAM_A_GAP_0) \
+_op_(CSI_PIXEL_STREAM_PPA_COMMAND_0) \
+_op_(CSI_INPUT_STREAM_B_CONTROL_0) \
+_op_(CSI_PIXEL_STREAM_B_CONTROL0_0) \
+_op_(CSI_PIXEL_STREAM_B_CONTROL1_0) \
+_op_(CSI_PIXEL_STREAM_B_WORD_COUNT_0) \
+_op_(CSI_PIXEL_STREAM_B_GAP_0) \
+_op_(CSI_PIXEL_STREAM_PPB_COMMAND_0) \
+_op_(CSI_PHY_CIL_COMMAND_0) \
+_op_(CSI_PHY_CILA_CONTROL0_0) \
+_op_(CSI_PHY_CILB_CONTROL0_0) \
+_op_(CSI_CSI_PIXEL_PARSER_STATUS_0) \
+_op_(CSI_CSI_CIL_STATUS_0) \
+_op_(CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0) \
+_op_(CSI_CSI_CIL_INTERRUPT_MASK_0) \
+_op_(CSI_CSI_READONLY_STATUS_0) \
+_op_(CSI_ESCAPE_MODE_COMMAND_0) \
+_op_(CSI_ESCAPE_MODE_DATA_0) \
+_op_(CSI_CILA_PAD_CONFIG0_0) \
+_op_(CSI_CILA_PAD_CONFIG1_0) \
+_op_(CSI_CILB_PAD_CONFIG0_0) \
+_op_(CSI_CILB_PAD_CONFIG1_0) \
+_op_(CSI_CIL_PAD_CONFIG0_0) \
+_op_(CSI_CILA_MIPI_CAL_CONFIG_0) \
+_op_(CSI_CILB_MIPI_CAL_CONFIG_0) \
+_op_(CSI_CIL_MIPI_CAL_STATUS_0) \
+_op_(CSI_CLKEN_OVERRIDE_0) \
+_op_(CSI_DEBUG_CONTROL_0) \
+_op_(CSI_DEBUG_COUNTER_0_0) \
+_op_(CSI_DEBUG_COUNTER_1_0) \
+_op_(CSI_DEBUG_COUNTER_2_0) \
+_op_(CSI_PIXEL_STREAM_A_EXPECTED_FRAME_0) \
+_op_(CSI_PIXEL_STREAM_B_EXPECTED_FRAME_0) \
+_op_(CSI_DSI_MIPI_CAL_CONFIG_0)
+
+
+//
+// ADDRESS SPACES
+//
+
+#define BASE_ADDRESS_VI 0x00000000
+#define BASE_ADDRESS_CSI        0x00000200
+
+//
+// ARVI REGISTER BANKS
+//
+
+#define VI0_FIRST_REG 0x0000 // VI_OUT_1_INCR_SYNCPT_0
+#define VI0_LAST_REG 0x0002 // VI_OUT_1_INCR_SYNCPT_ERROR_0
+#define VI1_FIRST_REG 0x0008 // VI_OUT_2_INCR_SYNCPT_0
+#define VI1_LAST_REG 0x000a // VI_OUT_2_INCR_SYNCPT_ERROR_0
+#define VI2_FIRST_REG 0x0010 // VI_MISC_INCR_SYNCPT_0
+#define VI2_LAST_REG 0x0012 // VI_MISC_INCR_SYNCPT_ERROR_0
+#define VI3_FIRST_REG 0x0018 // VI_CONT_SYNCPT_OUT_1_0
+#define VI3_LAST_REG 0x0098 // VI_RESERVE_4_0
+#define CSI0_FIRST_REG 0x0200 // CSI_VI_INPUT_STREAM_CONTROL_0
+#define CSI0_LAST_REG 0x0200 // CSI_VI_INPUT_STREAM_CONTROL_0
+#define CSI1_FIRST_REG 0x0202 // CSI_HOST_INPUT_STREAM_CONTROL_0
+#define CSI1_LAST_REG 0x0202 // CSI_HOST_INPUT_STREAM_CONTROL_0
+#define CSI2_FIRST_REG 0x0204 // CSI_INPUT_STREAM_A_CONTROL_0
+#define CSI2_LAST_REG 0x0204 // CSI_INPUT_STREAM_A_CONTROL_0
+#define CSI3_FIRST_REG 0x0206 // CSI_PIXEL_STREAM_A_CONTROL0_0
+#define CSI3_LAST_REG 0x020a // CSI_PIXEL_STREAM_PPA_COMMAND_0
+#define CSI4_FIRST_REG 0x020f // CSI_INPUT_STREAM_B_CONTROL_0
+#define CSI4_LAST_REG 0x020f // CSI_INPUT_STREAM_B_CONTROL_0
+#define CSI5_FIRST_REG 0x0211 // CSI_PIXEL_STREAM_B_CONTROL0_0
+#define CSI5_LAST_REG 0x0215 // CSI_PIXEL_STREAM_PPB_COMMAND_0
+#define CSI6_FIRST_REG 0x021a // CSI_PHY_CIL_COMMAND_0
+#define CSI6_LAST_REG 0x021c // CSI_PHY_CILB_CONTROL0_0
+#define CSI7_FIRST_REG 0x021e // CSI_CSI_PIXEL_PARSER_STATUS_0
+#define CSI7_LAST_REG 0x0234 // CSI_DSI_MIPI_CAL_CONFIG_0
+
+#ifndef _MK_SHIFT_CONST
+  #define _MK_SHIFT_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_MASK_CONST
+  #define _MK_MASK_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_ENUM_CONST
+  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
+#endif
+#ifndef _MK_ADDR_CONST
+  #define _MK_ADDR_CONST(_constant_) _constant_
+#endif
+
+#endif // ifndef ___ARVI_H_INC_
diff --git a/arch/arm/mach-tegra/include/ap15/project_relocation_table.h b/arch/arm/mach-tegra/include/ap15/project_relocation_table.h
new file mode 100644
index 000000000000..0dea12fce480
--- /dev/null
+++ b/arch/arm/mach-tegra/include/ap15/project_relocation_table.h
@@ -0,0 +1,555 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+#ifndef PROJECT_AP15_RELOCATION_TABLE_SPEC_INC
+#define PROJECT_AP15_RELOCATION_TABLE_SPEC_INC
+
+// ------------------------------------------------------------
+//    hw nvdevids
+// ------------------------------------------------------------
+// Memory Aperture: Internal Memory
+#define NV_DEVID_IMEM                            1
+
+// Memory Aperture: External Memory
+#define NV_DEVID_EMEM                            2
+
+// Memory Aperture: TCRAM
+#define NV_DEVID_TCRAM                           3
+
+// Memory Aperture: IRAM
+#define NV_DEVID_IRAM                            4
+
+// Memory Aperture: NOR FLASH
+#define NV_DEVID_NOR                             5
+
+// Memory Aperture: EXIO
+#define NV_DEVID_EXIO                            6
+
+// Memory Aperture: GART
+#define NV_DEVID_GART                            7
+
+// Device Aperture: Graphics Host (HOST1X)
+#define NV_DEVID_HOST1X                          8
+
+// Device Aperture: ARM PERIPH registers
+#define NV_DEVID_ARM_PERIPH                      9
+
+// Device Aperture: MSELECT
+#define NV_DEVID_MSELECT                         10
+
+// Device Aperture: memory controller
+#define NV_DEVID_MC                              11
+
+// Device Aperture: external memory controller
+#define NV_DEVID_EMC                             12
+
+// Device Aperture: video input
+#define NV_DEVID_VI                              13
+
+// Device Aperture: encoder pre-processor
+#define NV_DEVID_EPP                             14
+
+// Device Aperture: video encoder
+#define NV_DEVID_MPE                             15
+
+// Device Aperture: 3D engine
+#define NV_DEVID_GR3D                            16
+
+// Device Aperture: 2D + SBLT engine
+#define NV_DEVID_GR2D                            17
+
+// Device Aperture: Image Signal Processor
+#define NV_DEVID_ISP                             18
+
+// Device Aperture: DISPLAY
+#define NV_DEVID_DISPLAY                         19
+
+// Device Aperture: UPTAG
+#define NV_DEVID_UPTAG                           20
+
+// Device Aperture - SHR_SEM
+#define NV_DEVID_SHR_SEM                         21
+
+// Device Aperture - ARB_SEM
+#define NV_DEVID_ARB_SEM                         22
+
+// Device Aperture - ARB_PRI
+#define NV_DEVID_ARB_PRI                         23
+
+// Obsoleted for AP15
+#define NV_DEVID_PRI_INTR                        24
+
+// Obsoleted for AP15
+#define NV_DEVID_SEC_INTR                        25
+
+// Device Aperture: Timer Programmable
+#define NV_DEVID_TMR                             26
+
+// Device Aperture: Clock and Reset
+#define NV_DEVID_CAR                             27
+
+// Device Aperture: Flow control
+#define NV_DEVID_FLOW                            28
+
+// Device Aperture: Event
+#define NV_DEVID_EVENT                           29
+
+// Device Aperture: AHB DMA
+#define NV_DEVID_AHB_DMA                         30
+
+// Device Aperture: APB DMA
+#define NV_DEVID_APB_DMA                         31
+
+// Device Aperture: COP Cache Controller
+#define NV_DEVID_COP_CACHE                       32
+
+// Obsolete - use COP_CACHE
+#define NV_DEVID_CC                              32
+
+// Obsolete - use COP_CACHE
+#define NV_DEVID_SYS_REG                         32
+
+// Device Aperture: System Statistic monitor
+#define NV_DEVID_STAT                            33
+
+// Device Aperture: GPIO
+#define NV_DEVID_GPIO                            34
+
+// Device Aperture: Vector Co-Processor 2
+#define NV_DEVID_VCP                             35
+
+// Device Aperture: Arm Vectors
+#define NV_DEVID_VECTOR                          36
+
+// Device: MEM
+#define NV_DEVID_MEM                             37
+
+// Obsolete - use VDE
+#define NV_DEVID_SXE                             38
+
+// Device Aperture: video decoder
+#define NV_DEVID_VDE                             38
+
+// Obsolete - use VDE
+#define NV_DEVID_BSEV                            39
+
+// Obsolete - use VDE
+#define NV_DEVID_MBE                             40
+
+// Obsolete - use VDE
+#define NV_DEVID_PPE                             41
+
+// Obsolete - use VDE
+#define NV_DEVID_MCE                             42
+
+// Obsolete - use VDE
+#define NV_DEVID_TFE                             43
+
+// Obsolete - use VDE
+#define NV_DEVID_PPB                             44
+
+// Obsolete - use VDE
+#define NV_DEVID_VDMA                            45
+
+// Obsolete - use VDE
+#define NV_DEVID_UCQ                             46
+
+// Device Aperture: BSEA (now in AVP cluster)
+#define NV_DEVID_BSEA                            47
+
+// Obsolete - use VDE
+#define NV_DEVID_FRAMEID                         48
+
+// Device Aperture: Misc regs
+#define NV_DEVID_MISC                            49
+
+// Device Aperture: AC97
+#define NV_DEVID_AC97                            50
+
+// Device Aperture: S/P-DIF
+#define NV_DEVID_SPDIF                           51
+
+// Device Aperture: I2S
+#define NV_DEVID_I2S                             52
+
+// Device Aperture: UART
+#define NV_DEVID_UART                            53
+
+// Device Aperture: VFIR
+#define NV_DEVID_VFIR                            54
+
+// Device Aperture: NAND Flash Controller
+#define NV_DEVID_NANDCTRL                        55
+
+// Obsolete - use NANDCTRL
+#define NV_DEVID_NANDFLASH                       55
+
+// Device Aperture: HSMMC
+#define NV_DEVID_HSMMC                           56
+
+// Device Aperture: XIO
+#define NV_DEVID_XIO                             57
+
+// Device Aperture: PWFM
+#define NV_DEVID_PWFM                            58
+
+// Device Aperture: MIPI
+#define NV_DEVID_MIPI_HS                         59
+
+// Device Aperture: I2C
+#define NV_DEVID_I2C                             60
+
+// Device Aperture: TWC
+#define NV_DEVID_TWC                             61
+
+// Device Aperture: SLINK
+#define NV_DEVID_SLINK                           62
+
+// Device Aperture: SLINK4B
+#define NV_DEVID_SLINK4B                         63
+
+// Device Aperture: SPI
+#define NV_DEVID_SPI                             64
+
+// Device Aperture: DVC
+#define NV_DEVID_DVC                             65
+
+// Device Aperture: RTC
+#define NV_DEVID_RTC                             66
+
+// Device Aperture: KeyBoard Controller
+#define NV_DEVID_KBC                             67
+
+// Device Aperture: PMIF
+#define NV_DEVID_PMIF                            68
+
+// Device Aperture: FUSE
+#define NV_DEVID_FUSE                            69
+
+// Device Aperture: L2 Cache Controller
+#define NV_DEVID_CMC                             70
+
+// Device Apertuer: NOR FLASH Controller
+#define NV_DEVID_NOR_REG                         71
+
+// Device Aperture: EIDE
+#define NV_DEVID_EIDE                            72
+
+// Device Aperture: USB
+#define NV_DEVID_USB                             73
+
+// Device Aperture: SDIO
+#define NV_DEVID_SDIO                            74
+
+// Device Aperture: TVO
+#define NV_DEVID_TVO                             75
+
+// Device Aperture: DSI
+#define NV_DEVID_DSI                             76
+
+// Device Aperture: HDMI
+#define NV_DEVID_HDMI                            77
+
+// Device Aperture: Third Interrupt Controller extra registers
+#define NV_DEVID_TRI_INTR                        78
+
+// Device Aperture: Common Interrupt Controller
+#define NV_DEVID_ICTLR                           79
+
+// Non-Aperture Interrupt: DMA TX interrupts
+#define NV_DEVID_DMA_TX_INTR                     80
+
+// Non-Aperture Interrupt: DMA RX interrupts
+#define NV_DEVID_DMA_RX_INTR                     81
+
+// Non-Aperture Interrupt: SW reserved interrupt
+#define NV_DEVID_SW_INTR                         82
+
+// Non-Aperture Interrupt: CPU PMU Interrupt
+#define NV_DEVID_CPU_INTR                        83
+
+// Device Aperture: Timer Free Running MicroSecond
+#define NV_DEVID_TMRUS                           84
+
+// Device Aperture: Interrupt Controller ARB_GNT Registers
+#define NV_DEVID_ICTLR_ARBGNT                    85
+
+// Device Aperture: Interrupt Controller DMA Registers
+#define NV_DEVID_ICTLR_DRQ                       86
+
+// Device Aperture: AHB DMA Channel
+#define NV_DEVID_AHB_DMA_CH                      87
+
+// Device Aperture: APB DMA Channel
+#define NV_DEVID_APB_DMA_CH                      88
+
+// Device Aperture: AHB Arbitration Controller
+#define NV_DEVID_AHB_ARBC                        89
+
+// Obsolete - use AHB_ARBC
+#define NV_DEVID_AHB_ARB_CTRL                    89
+
+// Device Aperture: AHB/APB Debug Bus Registers
+#define NV_DEVID_AHPBDEBUG                       91
+
+// Device Aperture: Secure Boot Register
+#define NV_DEVID_SECURE_BOOT                     92
+
+// Device Aperture: SPROM
+#define NV_DEVID_SPROM                           93
+
+// Memory Aperture: AHB external memory remapping
+#define NV_DEVID_AHB_EMEM                        94
+
+// Non-Aperture Interrupt: External PMU interrupt
+#define NV_DEVID_PMU_EXT                         95
+
+// Device Aperture: AHB EMEM to MC Flush Register
+#define NV_DEVID_PPCS                            96
+
+// Device Aperture: MMU TLB registers for COP/AVP
+#define NV_DEVID_MMU_TLB                         97
+
+// Device Aperture: OVG engine
+#define NV_DEVID_VG                              98
+
+// Device Aperture: CSI
+#define NV_DEVID_CSI                             99
+
+// Device ID for COP
+#define NV_DEVID_AVP                             100
+
+// Device ID for MPCORE
+#define NV_DEVID_CPU                             101
+
+// Device Aperture: ULPI controller
+#define NV_DEVID_ULPI                            102
+
+// Device Aperture: ARM CONFIG registers
+#define NV_DEVID_ARM_CONFIG                      103
+
+// Device Aperture: ARM PL310 (L2 controller)
+#define NV_DEVID_ARM_PL310                       104
+
+// Device Aperture: PCIe
+#define NV_DEVID_PCIE                            105
+
+// Device Aperture: OWR (one wire)
+#define NV_DEVID_OWR                             106
+
+// Device Aperture: AVPUCQ
+#define NV_DEVID_AVPUCQ                          107
+
+// Device Aperture: AVPBSEA (obsolete)
+#define NV_DEVID_AVPBSEA                         108
+
+// Device Aperture: Sync NOR
+#define NV_DEVID_SNOR                            109
+
+// Device Aperture: SDMMC
+#define NV_DEVID_SDMMC                           110
+
+// Device Aperture: KFUSE
+#define NV_DEVID_KFUSE                           111
+
+// Device Aperture: CSITE
+#define NV_DEVID_CSITE                           112
+
+// Non-Aperture Interrupt: ARM Interprocessor Interrupt
+#define NV_DEVID_ARM_IPI                         113
+
+// Device Aperture: ARM Interrupts 0-31
+#define NV_DEVID_ARM_ICTLR                       114
+
+// Device Aperture: IOBIST
+#define NV_DEVID_IOBIST                          115
+
+// Device Aperture: SPEEDO
+#define NV_DEVID_SPEEDO                          116
+
+// Device Aperture: LA
+#define NV_DEVID_LA                              117
+
+// Device Aperture: VS
+#define NV_DEVID_VS                              118
+
+// Device Aperture: VCI
+#define NV_DEVID_VCI                             119
+
+// Device Aperture: APBIF
+#define NV_DEVID_APBIF                           120
+
+// Device Aperture: AHUB
+#define NV_DEVID_AHUB                            121
+
+// Device Aperture: DAM
+#define NV_DEVID_DAM                             122
+
+// ------------------------------------------------------------
+//    hw powergroups
+// ------------------------------------------------------------
+// Always On
+#define NV_POWERGROUP_AO                         0
+
+// Main
+#define NV_POWERGROUP_NPG                        1
+
+// CPU related blocks
+#define NV_POWERGROUP_CPU                        2
+
+// 3D graphics
+#define NV_POWERGROUP_TD                         3
+
+// Video encode engine blocks
+#define NV_POWERGROUP_VE                         4
+
+// PCIe
+#define NV_POWERGROUP_PCIE                       5
+
+// Video decoder
+#define NV_POWERGROUP_VDE                        6
+
+// MPEG encoder
+#define NV_POWERGROUP_MPE                        7
+
+// SW define for Power Group maximum
+#define NV_POWERGROUP_MAX                        8
+
+// non-mapped power group
+#define NV_POWERGROUP_INVALID                    0xffff
+
+// SW table for mapping power group define to register enums (NV_POWERGROUP_INVALID = no mapping)
+//  use as 'int table[NV_POWERGROUP_MAX] = { NV_POWERGROUP_ENUM_TABLE }'
+#define NV_POWERGROUP_ENUM_TABLE                 NV_POWERGROUP_INVALID, NV_POWERGROUP_INVALID, 0, 1, 2, NV_POWERGROUP_INVALID, NV_POWERGROUP_INVALID, NV_POWERGROUP_INVALID
+
+// ------------------------------------------------------------
+//    relocation table data (stored in boot rom)
+// ------------------------------------------------------------
+// relocation table pointer stored at NV_RELOCATION_TABLE_OFFSET
+#define NV_RELOCATION_TABLE_PTR_OFFSET 64
+#define NV_RELOCATION_TABLE_SIZE  472
+#define NV_RELOCATION_TABLE_INIT \
+          0x00000001, 0x00020010, 0x00000000, 0x40000000, 0x005f1010, \
+          0x00000000, 0x00000000, 0x00531010, 0x00000000, 0x00000000, \
+          0x00521010, 0x00000000, 0x00000000, 0x00040010, 0x40000000, \
+          0x00008000, 0x00040010, 0x40008000, 0x00008000, 0x00040010, \
+          0x40010000, 0x00008000, 0x00040010, 0x40018000, 0x00008000, \
+          0x00081010, 0x50000000, 0x00024000, 0x00091020, 0x50040000, \
+          0x00002000, 0x000a1020, 0x50042000, 0x00001000, 0x000f1140, \
+          0x54040000, 0x00040000, 0x00631040, 0x54080000, 0x00040000, \
+          0x000d1140, 0x54080000, 0x00040000, 0x000e1040, 0x540c0000, \
+          0x00040000, 0x00121040, 0x54100000, 0x00040000, 0x00111010, \
+          0x54140000, 0x00040000, 0x00101230, 0x54180000, 0x00040000, \
+          0x00131210, 0x54200000, 0x00040000, 0x00131210, 0x54240000, \
+          0x00040000, 0x004d1110, 0x54280000, 0x00040000, 0x004b1010, \
+          0x542c0000, 0x00040000, 0x004c1010, 0x54300000, 0x00040000, \
+          0x00070010, 0x58000000, 0x01000000, 0x00141010, 0x60000000, \
+          0x00001000, 0x00151010, 0x60001000, 0x00001000, 0x00161010, \
+          0x60002000, 0x00001000, 0x00171010, 0x60003000, 0x00001000, \
+          0x004f1010, 0x60004000, 0x00000040, 0x00551010, 0x60004040, \
+          0x000000c0, 0x004f1110, 0x60004100, 0x00000040, 0x00561010, \
+          0x60004140, 0x00000008, 0x00561110, 0x60004148, 0x00000008, \
+          0x004f1210, 0x60004200, 0x00000040, 0x001a1010, 0x60005000, \
+          0x00000008, 0x001a1010, 0x60005008, 0x00000008, 0x00541010, \
+          0x60005010, 0x00000040, 0x001a1010, 0x60005050, 0x00000008, \
+          0x001a1010, 0x60005058, 0x00000008, 0x001b1110, 0x60006000, \
+          0x00001000, 0x001c1010, 0x60007000, 0x00000014, 0x001e1110, \
+          0x60008000, 0x00001000, 0x00571010, 0x60009000, 0x00000020, \
+          0x00571010, 0x60009020, 0x00000020, 0x00571010, 0x60009040, \
+          0x00000020, 0x00571010, 0x60009060, 0x00000020, 0x001f1010, \
+          0x6000a000, 0x00001000, 0x00581010, 0x6000b000, 0x00000020, \
+          0x00581010, 0x6000b020, 0x00000020, 0x00581010, 0x6000b040, \
+          0x00000020, 0x00581010, 0x6000b060, 0x00000020, 0x00581010, \
+          0x6000b080, 0x00000020, 0x00581010, 0x6000b0a0, 0x00000020, \
+          0x00581010, 0x6000b0c0, 0x00000020, 0x00581010, 0x6000b0e0, \
+          0x00000020, 0x00581010, 0x6000b100, 0x00000020, 0x00581010, \
+          0x6000b120, 0x00000020, 0x00581010, 0x6000b140, 0x00000020, \
+          0x00581010, 0x6000b160, 0x00000020, 0x00581010, 0x6000b180, \
+          0x00000020, 0x00581010, 0x6000b1a0, 0x00000020, 0x00581010, \
+          0x6000b1c0, 0x00000020, 0x00581010, 0x6000b1e0, 0x00000020, \
+          0x00201010, 0x6000c000, 0x00000400, 0x00591010, 0x6000c004, \
+          0x0000010c, 0x005b1010, 0x6000c150, 0x000000a6, 0x005c1010, \
+          0x6000c200, 0x00000004, 0x00211010, 0x6000c400, 0x00000400, \
+          0x00222010, 0x6000d000, 0x00000880, 0x00222010, 0x6000d080, \
+          0x00000880, 0x00222010, 0x6000d100, 0x00000880, 0x00222010, \
+          0x6000d180, 0x00000880, 0x00222010, 0x6000d200, 0x00000880, \
+          0x00222010, 0x6000d280, 0x00000880, 0x00231010, 0x6000e000, \
+          0x00001000, 0x00241010, 0x6000f000, 0x00001000, 0x002f1010, \
+          0x6001a000, 0x00003b00, 0x00261110, 0x6001a000, 0x00003b00, \
+          0x00311110, 0x70000000, 0x00001000, 0x00321010, 0x70002000, \
+          0x00000200, 0x00331010, 0x70002400, 0x00000200, 0x00341010, \
+          0x70002800, 0x00000100, 0x00341010, 0x70002a00, 0x00000100, \
+          0x00351110, 0x70006000, 0x00000040, 0x00351110, 0x70006040, \
+          0x00000040, 0x00361010, 0x70006100, 0x00000100, 0x00351110, \
+          0x70006200, 0x00000100, 0x00371110, 0x70008000, 0x00000100, \
+          0x00381010, 0x70008500, 0x00000100, 0x00391010, 0x70008a00, \
+          0x00000200, 0x003a1010, 0x7000a000, 0x00000100, 0x003b1010, \
+          0x7000b000, 0x00000100, 0x003c1110, 0x7000c000, 0x00000100, \
+          0x003d1010, 0x7000c100, 0x00000100, 0x00401010, 0x7000c380, \
+          0x00000030, 0x003c1110, 0x7000c400, 0x00000100, 0x00411010, \
+          0x7000d000, 0x00000200, 0x003f1010, 0x7000d300, 0x00000100, \
+          0x003e1010, 0x7000d400, 0x00000200, 0x003e1010, 0x7000d600, \
+          0x00000200, 0x003e1010, 0x7000d800, 0x00000200, 0x00421000, \
+          0x7000e000, 0x00000100, 0x00431000, 0x7000e200, 0x00000100, \
+          0x00441000, 0x7000e400, 0x00000100, 0x00461010, 0x7000e800, \
+          0x00000200, 0x005d1010, 0x7000ec00, 0x00000100, 0x000b1010, \
+          0x7000f000, 0x00000400, 0x000c1110, 0x7000f400, 0x00000400, \
+          0x00451110, 0x7000f800, 0x00000400, 0x00050010, 0x80000000, \
+          0x10000000, 0x005e0010, 0x90000000, 0x20000000, 0x00060010, \
+          0xb0000000, 0x08000000, 0x00060010, 0xb8000000, 0x08000000, \
+          0x00481010, 0xc3000000, 0x01000000, 0x00601010, 0xc4000000, \
+          0x00010000, 0x00491110, 0xc5000000, 0x00002000, 0x004a1010, \
+          0xc8000000, 0x00000100, 0x004a1010, 0xc8000100, 0x00000100, \
+          0x00611010, 0xf000f000, 0x00001000, 0x00000000, 0x82100116, \
+          0x81e00218, 0x8210031f, 0xc2100800, 0xa2100801, 0xc2100802, \
+          0xa2100803, 0x82100b04, 0x82100d05, 0x82100e06, 0x82100f07, \
+          0x82101008, 0x82101209, 0x8210130a, 0x8210140b, 0x8210150c, \
+          0xa1c01904, 0xc1c01905, 0xc1c01906, 0xa1c01907, 0xa1c01a1d, \
+          0xc1c01a1c, 0x81e01f1e, 0x81e0201f, 0x81c02200, 0x81c02301, \
+          0x81e02509, 0x81e0260a, 0xa1e0280b, 0xc1e0280c, 0xa1c0291b, \
+          0xc1e0291d, 0xa1c02e1a, 0xc1e02e1c, 0x81e04316, 0x81e04400, \
+          0x81e04501, 0x81e04602, 0x81e04703, 0x81e04817, 0x82104917, \
+          0x81c04a19, 0x81c04d09, 0x81c04d0a, 0x81c04d0b, 0x81c04d0c, \
+          0x81c04d08, 0x81c04d11, 0x82104e10, 0x82104e18, 0x82104f11, \
+          0x81f04f00, 0x81f04f12, 0x82004f00, 0x82004f12, 0x81e0500d, \
+          0x81f05003, 0x81f05004, 0x82005003, 0x82005004, 0x81c0510d, \
+          0x81f05102, 0x81f05101, 0x82005101, 0x82005102, 0x81c05203, \
+          0x81f05206, 0x81f05205, 0x82005205, 0x82005206, 0x81e05304, \
+          0x81f05308, 0x82005308, 0x81e05405, 0x81f05409, 0x82005409, \
+          0x81e05514, 0x81f05511, 0x82005511, 0x81e0560e, 0x81f0560a, \
+          0x8200560a, 0x81c05718, 0x81c05816, 0x81c05910, 0x81e05b0f, \
+          0x81e05c06, 0x81f05c0c, 0x82005c0c, 0x81e05d08, 0x81f05d0b, \
+          0x82005d0b, 0x81e05e07, 0x81f05e07, 0x82005e07, 0x82105f14, \
+          0x81f05f0d, 0x82005f0d, 0x81e06015, 0x81e0611a, 0x81e0621b, \
+          0x82106312, 0x82106413, 0x81c06502, 0x82106615, 0x8210680f, \
+          0x82106a0d, 0x82106b0e, 0x81c07117, 0x81c07314, 0x81c0740e, \
+          0x81c0750f, 0x00000000
+#endif
diff --git a/arch/arm/mach-tegra/include/ap16/arapb_misc.h b/arch/arm/mach-tegra/include/ap16/arapb_misc.h
new file mode 100644
index 000000000000..18bdc777ca9b
--- /dev/null
+++ b/arch/arm/mach-tegra/include/ap16/arapb_misc.h
@@ -0,0 +1,12730 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+//
+// DO NOT EDIT - generated by simspec!
+//
+
+#ifndef ___ARAPB_MISC_H_INC_
+#define ___ARAPB_MISC_H_INC_
+
+// Reserved address 0 [0x0] 
+
+// Reserved address 4 [0x4] 
+
+// Register APB_MISC_PP_STRAPPING_OPT_A_0  
+#define APB_MISC_PP_STRAPPING_OPT_A_0                   _MK_ADDR_CONST(0x8)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_WORD_COUNT                        0x1
+#define APB_MISC_PP_STRAPPING_OPT_A_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_RESET_MASK                        _MK_MASK_CONST(0x101)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_READ_MASK                         _MK_MASK_CONST(0x1c001f1)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_WRITE_MASK                        _MK_MASK_CONST(0x1c001f1)
+// read at power-on reset time from hsmmc_wp strap pad
+// note that BOOT_SRC is only valid in pre-production mode
+#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SRC_USB_RECOVERY_MODE_SHIFT                  _MK_SHIFT_CONST(24)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SRC_USB_RECOVERY_MODE_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SRC_USB_RECOVERY_MODE_SHIFT)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SRC_USB_RECOVERY_MODE_RANGE                  24:24
+#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SRC_USB_RECOVERY_MODE_WOFFSET                        0x0
+#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SRC_USB_RECOVERY_MODE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SRC_USB_RECOVERY_MODE_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SRC_USB_RECOVERY_MODE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SRC_USB_RECOVERY_MODE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SRC_USB_RECOVERY_MODE_IROM                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SRC_USB_RECOVERY_MODE_NOR                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SRC_USB_RECOVERY_MODE_DISABLE                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SRC_USB_RECOVERY_MODE_ENABLE                 _MK_ENUM_CONST(1)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SRC_USB_RECOVERY_MODE_DISABLED                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SRC_USB_RECOVERY_MODE_ENABLED                        _MK_ENUM_CONST(1)
+
+// read at power-on reset time from {nand_cle,nand_ale} strap pads 00=Serial_JTAG, 01=CPU_only, 10=COP_only, 11=Serial_JTAG(same as 00 case)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_ARM_JTAG_SHIFT                    _MK_SHIFT_CONST(22)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_ARM_JTAG_FIELD                    (_MK_MASK_CONST(0x3) << APB_MISC_PP_STRAPPING_OPT_A_0_ARM_JTAG_SHIFT)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_ARM_JTAG_RANGE                    23:22
+#define APB_MISC_PP_STRAPPING_OPT_A_0_ARM_JTAG_WOFFSET                  0x0
+#define APB_MISC_PP_STRAPPING_OPT_A_0_ARM_JTAG_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_ARM_JTAG_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_ARM_JTAG_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_ARM_JTAG_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_ARM_JTAG_SERIAL                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_ARM_JTAG_CPU                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_ARM_JTAG_COP                      _MK_ENUM_CONST(2)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_ARM_JTAG_SERIAL_ALT                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_STRAPPING_OPT_A_0_MIO_WIDTH_SHIFT                   _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_MIO_WIDTH_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_PP_STRAPPING_OPT_A_0_MIO_WIDTH_SHIFT)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_MIO_WIDTH_RANGE                   8:8
+#define APB_MISC_PP_STRAPPING_OPT_A_0_MIO_WIDTH_WOFFSET                 0x0
+#define APB_MISC_PP_STRAPPING_OPT_A_0_MIO_WIDTH_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_MIO_WIDTH_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_MIO_WIDTH_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_MIO_WIDTH_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_MIO_WIDTH_INIT_ENUM                       IS16BIT
+#define APB_MISC_PP_STRAPPING_OPT_A_0_MIO_WIDTH_IS16BIT                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_MIO_WIDTH_IS32BIT                 _MK_ENUM_CONST(1)
+
+// read at power-on reset time from nand_d[3:0] strap pads
+#define APB_MISC_PP_STRAPPING_OPT_A_0_RAM_CODE_SHIFT                    _MK_SHIFT_CONST(4)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_RAM_CODE_FIELD                    (_MK_MASK_CONST(0xf) << APB_MISC_PP_STRAPPING_OPT_A_0_RAM_CODE_SHIFT)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_RAM_CODE_RANGE                    7:4
+#define APB_MISC_PP_STRAPPING_OPT_A_0_RAM_CODE_WOFFSET                  0x0
+#define APB_MISC_PP_STRAPPING_OPT_A_0_RAM_CODE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_RAM_CODE_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_RAM_CODE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_RAM_CODE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_PP_STRAPPING_OPT_A_0_NOR_WIDTH_SHIFT                   _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_NOR_WIDTH_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_PP_STRAPPING_OPT_A_0_NOR_WIDTH_SHIFT)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_NOR_WIDTH_RANGE                   0:0
+#define APB_MISC_PP_STRAPPING_OPT_A_0_NOR_WIDTH_WOFFSET                 0x0
+#define APB_MISC_PP_STRAPPING_OPT_A_0_NOR_WIDTH_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_NOR_WIDTH_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_NOR_WIDTH_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_NOR_WIDTH_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_NOR_WIDTH_INIT_ENUM                       IS16BIT
+#define APB_MISC_PP_STRAPPING_OPT_A_0_NOR_WIDTH_IS16BIT                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_NOR_WIDTH_IS8BIT                  _MK_ENUM_CONST(1)
+
+
+// Reserved address 12 [0xc] 
+
+// Reserved address 16 [0x10] 
+
+// Register APB_MISC_PP_TRISTATE_REG_A_0  
+#define APB_MISC_PP_TRISTATE_REG_A_0                    _MK_ADDR_CONST(0x14)
+#define APB_MISC_PP_TRISTATE_REG_A_0_WORD_COUNT                         0x1
+#define APB_MISC_PP_TRISTATE_REG_A_0_RESET_VAL                  _MK_MASK_CONST(0x11bffff)
+#define APB_MISC_PP_TRISTATE_REG_A_0_RESET_MASK                         _MK_MASK_CONST(0xfffffff)
+#define APB_MISC_PP_TRISTATE_REG_A_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_READ_MASK                  _MK_MASK_CONST(0xfffffff)
+#define APB_MISC_PP_TRISTATE_REG_A_0_WRITE_MASK                         _MK_MASK_CONST(0xfffffff)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCF_SHIFT                       _MK_SHIFT_CONST(27)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCF_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCF_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCF_RANGE                       27:27
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCF_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCF_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCF_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCF_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCF_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCF_INIT_ENUM                   NORMAL
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCF_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCF_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCE_SHIFT                       _MK_SHIFT_CONST(26)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCE_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCE_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCE_RANGE                       26:26
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCE_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCE_INIT_ENUM                   NORMAL
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCE_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCE_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_RM_SHIFT                 _MK_SHIFT_CONST(25)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_RM_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_RM_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_RM_RANGE                 25:25
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_RM_WOFFSET                       0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_RM_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_RM_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_RM_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_RM_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_RM_INIT_ENUM                     NORMAL
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_RM_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_RM_TRISTATE                      _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PTA_SHIFT                        _MK_SHIFT_CONST(24)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PTA_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_PTA_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PTA_RANGE                        24:24
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PTA_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PTA_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PTA_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PTA_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PTA_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PTA_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PTA_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PTA_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PMC_SHIFT                        _MK_SHIFT_CONST(23)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PMC_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_PMC_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PMC_RANGE                        23:23
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PMC_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PMC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PMC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PMC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PMC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PMC_INIT_ENUM                    NORMAL
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PMC_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PMC_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCA_SHIFT                       _MK_SHIFT_CONST(22)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCA_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCA_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCA_RANGE                       22:22
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCA_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCA_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCA_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCA_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCA_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCA_INIT_ENUM                   NORMAL
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCA_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCA_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCB_SHIFT                       _MK_SHIFT_CONST(21)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCB_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCB_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCB_RANGE                       21:21
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCB_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCB_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCB_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCB_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCB_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCB_INIT_ENUM                   NORMAL
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCB_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCB_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRRX_SHIFT                       _MK_SHIFT_CONST(20)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRRX_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_IRRX_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRRX_RANGE                       20:20
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRRX_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRRX_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRRX_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRRX_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRRX_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRRX_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRRX_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRRX_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRTX_SHIFT                       _MK_SHIFT_CONST(19)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRTX_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_IRTX_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRTX_RANGE                       19:19
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRTX_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRTX_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRTX_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRTX_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRTX_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRTX_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRTX_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRTX_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_I2CP_SHIFT                       _MK_SHIFT_CONST(18)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_I2CP_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_I2CP_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_I2CP_RANGE                       18:18
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_I2CP_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_I2CP_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_I2CP_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_I2CP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_I2CP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_I2CP_INIT_ENUM                   NORMAL
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_I2CP_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_I2CP_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPV_SHIFT                        _MK_SHIFT_CONST(17)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPV_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_GPV_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPV_RANGE                        17:17
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPV_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPV_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPV_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPV_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPV_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPV_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPV_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPV_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPU_SHIFT                        _MK_SHIFT_CONST(16)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPU_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_GPU_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPU_RANGE                        16:16
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPU_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPU_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPU_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPU_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPU_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPU_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPU_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPU_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTE_SHIFT                        _MK_SHIFT_CONST(15)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTE_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_DTE_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTE_RANGE                        15:15
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTE_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTE_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTE_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTE_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTE_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTD_SHIFT                        _MK_SHIFT_CONST(14)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTD_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_DTD_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTD_RANGE                        14:14
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTD_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTD_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTD_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTD_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTD_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTD_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTC_SHIFT                        _MK_SHIFT_CONST(13)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTC_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_DTC_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTC_RANGE                        13:13
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTC_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTC_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTC_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTC_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTC_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTB_SHIFT                        _MK_SHIFT_CONST(12)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTB_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_DTB_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTB_RANGE                        12:12
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTB_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTB_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTB_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTB_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTB_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTB_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTB_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTB_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTA_SHIFT                        _MK_SHIFT_CONST(11)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTA_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_DTA_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTA_RANGE                        11:11
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTA_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTA_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTA_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTA_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTA_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTA_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTA_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTA_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP4_SHIFT                       _MK_SHIFT_CONST(10)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP4_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP4_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP4_RANGE                       10:10
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP4_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP4_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP4_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP4_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP4_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP3_SHIFT                       _MK_SHIFT_CONST(9)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP3_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP3_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP3_RANGE                       9:9
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP3_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP3_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP3_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP3_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP3_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP2_SHIFT                       _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP2_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP2_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP2_RANGE                       8:8
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP2_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP2_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP2_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP2_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP2_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP1_SHIFT                       _MK_SHIFT_CONST(7)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP1_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP1_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP1_RANGE                       7:7
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP1_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP1_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP1_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP1_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP1_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CSUS_SHIFT                       _MK_SHIFT_CONST(6)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CSUS_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_CSUS_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CSUS_RANGE                       6:6
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CSUS_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CSUS_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CSUS_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CSUS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CSUS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CSUS_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CSUS_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CSUS_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV2_SHIFT                      _MK_SHIFT_CONST(5)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV2_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV2_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV2_RANGE                      5:5
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV2_WOFFSET                    0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV2_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV2_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV2_INIT_ENUM                  TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV2_NORMAL                     _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV2_TRISTATE                   _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV1_SHIFT                      _MK_SHIFT_CONST(4)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV1_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV1_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV1_RANGE                      4:4
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV1_WOFFSET                    0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV1_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV1_INIT_ENUM                  TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV1_NORMAL                     _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV1_TRISTATE                   _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATD_SHIFT                        _MK_SHIFT_CONST(3)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATD_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_ATD_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATD_RANGE                        3:3
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATD_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATD_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATD_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATD_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATD_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATD_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATC_SHIFT                        _MK_SHIFT_CONST(2)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATC_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_ATC_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATC_RANGE                        2:2
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATC_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATC_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATC_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATC_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATC_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATB_SHIFT                        _MK_SHIFT_CONST(1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATB_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_ATB_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATB_RANGE                        1:1
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATB_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATB_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATB_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATB_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATB_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATB_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATB_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATB_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATA_SHIFT                        _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATA_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_ATA_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATA_RANGE                        0:0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATA_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATA_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATA_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATA_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATA_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATA_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATA_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATA_TRISTATE                     _MK_ENUM_CONST(1)
+
+
+// Register APB_MISC_PP_TRISTATE_REG_B_0  
+#define APB_MISC_PP_TRISTATE_REG_B_0                    _MK_ADDR_CONST(0x18)
+#define APB_MISC_PP_TRISTATE_REG_B_0_WORD_COUNT                         0x1
+#define APB_MISC_PP_TRISTATE_REG_B_0_RESET_VAL                  _MK_MASK_CONST(0x2ffffff)
+#define APB_MISC_PP_TRISTATE_REG_B_0_RESET_MASK                         _MK_MASK_CONST(0x3effffff)
+#define APB_MISC_PP_TRISTATE_REG_B_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_READ_MASK                  _MK_MASK_CONST(0x3effffff)
+#define APB_MISC_PP_TRISTATE_REG_B_0_WRITE_MASK                         _MK_MASK_CONST(0x3effffff)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_XM2S_SHIFT                       _MK_SHIFT_CONST(29)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_XM2S_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_XM2S_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_XM2S_RANGE                       29:29
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_XM2S_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_XM2S_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_XM2S_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_XM2S_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_XM2S_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_XM2S_INIT_ENUM                   NORMAL
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_XM2S_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_XM2S_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_XM2C_SHIFT                       _MK_SHIFT_CONST(28)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_XM2C_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_XM2C_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_XM2C_RANGE                       28:28
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_XM2C_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_XM2C_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_XM2C_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_XM2C_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_XM2C_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_XM2C_INIT_ENUM                   NORMAL
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_XM2C_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_XM2C_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_XM2A_SHIFT                       _MK_SHIFT_CONST(27)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_XM2A_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_XM2A_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_XM2A_RANGE                       27:27
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_XM2A_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_XM2A_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_XM2A_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_XM2A_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_XM2A_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_XM2A_INIT_ENUM                   NORMAL
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_XM2A_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_XM2A_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_KBCC_SHIFT                       _MK_SHIFT_CONST(26)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_KBCC_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_KBCC_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_KBCC_RANGE                       26:26
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_KBCC_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_KBCC_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_KBCC_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_KBCC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_KBCC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_KBCC_INIT_ENUM                   NORMAL
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_KBCC_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_KBCC_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_ATE_SHIFT                        _MK_SHIFT_CONST(25)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_ATE_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_ATE_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_ATE_RANGE                        25:25
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_ATE_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_ATE_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_ATE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_ATE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_ATE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_ATE_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_ATE_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_ATE_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCB_SHIFT                        _MK_SHIFT_CONST(23)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCB_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_UCB_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCB_RANGE                        23:23
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCB_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCB_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCB_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCB_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCB_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCB_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCB_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCB_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCA_SHIFT                        _MK_SHIFT_CONST(22)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCA_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_UCA_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCA_RANGE                        22:22
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCA_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCA_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCA_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCA_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCA_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCA_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCA_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCA_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAD_SHIFT                        _MK_SHIFT_CONST(21)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAD_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_UAD_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAD_RANGE                        21:21
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAD_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAD_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAD_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAD_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAD_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAD_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAC_SHIFT                        _MK_SHIFT_CONST(20)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAC_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_UAC_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAC_RANGE                        20:20
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAC_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAC_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAC_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAC_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAC_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAB_SHIFT                        _MK_SHIFT_CONST(19)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAB_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_UAB_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAB_RANGE                        19:19
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAB_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAB_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAB_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAB_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAB_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAB_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAB_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAB_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAA_SHIFT                        _MK_SHIFT_CONST(18)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAA_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_UAA_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAA_RANGE                        18:18
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAA_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAA_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAA_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAA_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAA_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAA_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAA_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAA_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIH_SHIFT                       _MK_SHIFT_CONST(17)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIH_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIH_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIH_RANGE                       17:17
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIH_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIH_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIH_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIH_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIH_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIH_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIH_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIH_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIG_SHIFT                       _MK_SHIFT_CONST(16)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIG_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIG_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIG_RANGE                       16:16
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIG_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIG_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIG_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIG_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIG_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIG_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIG_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIG_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIF_SHIFT                       _MK_SHIFT_CONST(15)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIF_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIF_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIF_RANGE                       15:15
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIF_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIF_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIF_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIF_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIF_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIF_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIF_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIF_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIE_SHIFT                       _MK_SHIFT_CONST(14)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIE_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIE_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIE_RANGE                       14:14
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIE_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIE_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIE_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIE_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIE_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPID_SHIFT                       _MK_SHIFT_CONST(13)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPID_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_SPID_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPID_RANGE                       13:13
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPID_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPID_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPID_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPID_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPID_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPID_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPID_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPID_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIC_SHIFT                       _MK_SHIFT_CONST(12)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIC_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIC_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIC_RANGE                       12:12
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIC_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIC_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIC_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIC_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIC_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIC_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIB_SHIFT                       _MK_SHIFT_CONST(11)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIB_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIB_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIB_RANGE                       11:11
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIB_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIB_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIB_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIB_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIB_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIB_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIB_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIB_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIA_SHIFT                       _MK_SHIFT_CONST(10)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIA_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIA_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIA_RANGE                       10:10
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIA_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIA_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIA_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIA_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIA_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIA_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIA_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIA_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDO_SHIFT                       _MK_SHIFT_CONST(9)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDO_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDO_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDO_RANGE                       9:9
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDO_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDO_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDO_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDO_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDO_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDO_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDO_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDO_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDI_SHIFT                       _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDI_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDI_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDI_RANGE                       8:8
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDI_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDI_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDI_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDI_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDI_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDI_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDI_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDI_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXK_SHIFT                       _MK_SHIFT_CONST(7)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXK_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXK_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXK_RANGE                       7:7
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXK_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXK_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXK_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXK_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXK_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXD_SHIFT                       _MK_SHIFT_CONST(6)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXD_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXD_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXD_RANGE                       6:6
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXD_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXD_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXD_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXD_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXD_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXD_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXC_SHIFT                       _MK_SHIFT_CONST(5)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXC_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXC_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXC_RANGE                       5:5
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXC_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXC_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXC_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXC_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXC_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXC_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXB_SHIFT                       _MK_SHIFT_CONST(4)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXB_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXB_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXB_RANGE                       4:4
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXB_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXB_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXB_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXB_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXB_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXB_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXB_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXB_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXA_SHIFT                       _MK_SHIFT_CONST(3)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXA_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXA_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXA_RANGE                       3:3
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXA_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXA_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXA_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXA_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXA_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXA_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXA_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXA_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDD_SHIFT                        _MK_SHIFT_CONST(2)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDD_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_SDD_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDD_RANGE                        2:2
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDD_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDD_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDD_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDD_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDD_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDD_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDC_SHIFT                        _MK_SHIFT_CONST(1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDC_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_SDC_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDC_RANGE                        1:1
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDC_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDC_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDC_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDC_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDC_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDB_SHIFT                        _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDB_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_SDB_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDB_RANGE                        0:0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDB_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDB_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDB_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDB_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDB_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDB_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDB_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDB_TRISTATE                     _MK_ENUM_CONST(1)
+
+
+// Register APB_MISC_PP_TRISTATE_REG_C_0  
+#define APB_MISC_PP_TRISTATE_REG_C_0                    _MK_ADDR_CONST(0x1c)
+#define APB_MISC_PP_TRISTATE_REG_C_0_WORD_COUNT                         0x1
+#define APB_MISC_PP_TRISTATE_REG_C_0_RESET_VAL                  _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_TRISTATE_REG_C_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_TRISTATE_REG_C_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_TRISTATE_REG_C_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LCSN_SHIFT                       _MK_SHIFT_CONST(31)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LCSN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LCSN_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LCSN_RANGE                       31:31
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LCSN_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LCSN_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LCSN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LCSN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LCSN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LCSN_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LCSN_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LCSN_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LDC_SHIFT                        _MK_SHIFT_CONST(30)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LDC_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LDC_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LDC_RANGE                        30:30
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LDC_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LDC_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LDC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LDC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LDC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LDC_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LDC_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LDC_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSCK_SHIFT                       _MK_SHIFT_CONST(29)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSCK_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LSCK_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSCK_RANGE                       29:29
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSCK_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSCK_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSCK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSCK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSCK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSCK_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSCK_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSCK_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC1_SHIFT                       _MK_SHIFT_CONST(28)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC1_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC1_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC1_RANGE                       28:28
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC1_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC1_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC1_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC1_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC1_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC0_SHIFT                       _MK_SHIFT_CONST(27)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC0_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC0_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC0_RANGE                       27:27
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC0_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC0_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC0_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC0_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC0_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVS_SHIFT                        _MK_SHIFT_CONST(26)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVS_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LVS_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVS_RANGE                        26:26
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVS_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVS_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVS_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVS_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVS_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVS_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM1_SHIFT                        _MK_SHIFT_CONST(25)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM1_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LM1_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM1_RANGE                        25:25
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM1_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM1_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM1_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM1_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM1_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM1_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM0_SHIFT                        _MK_SHIFT_CONST(24)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM0_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LM0_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM0_RANGE                        24:24
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM0_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM0_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM0_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM0_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM0_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM0_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_HDINT_SHIFT                      _MK_SHIFT_CONST(23)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_HDINT_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_HDINT_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_HDINT_RANGE                      23:23
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_HDINT_WOFFSET                    0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_HDINT_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_HDINT_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_HDINT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_HDINT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_HDINT_INIT_ENUM                  TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_HDINT_NORMAL                     _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_HDINT_TRISTATE                   _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP1_SHIFT                       _MK_SHIFT_CONST(22)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP1_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP1_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP1_RANGE                       22:22
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP1_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP1_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP1_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP1_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP1_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP0_SHIFT                       _MK_SHIFT_CONST(21)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP0_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP0_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP0_RANGE                       21:21
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP0_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP0_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP0_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP0_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP0_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP2_SHIFT                       _MK_SHIFT_CONST(20)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP2_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP2_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP2_RANGE                       20:20
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP2_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP2_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP2_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP2_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP2_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP1_SHIFT                       _MK_SHIFT_CONST(19)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP1_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP1_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP1_RANGE                       19:19
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP1_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP1_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP1_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP1_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP1_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP0_SHIFT                       _MK_SHIFT_CONST(18)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP0_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP0_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP0_RANGE                       18:18
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP0_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP0_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP0_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP0_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP0_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD17_SHIFT                       _MK_SHIFT_CONST(17)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD17_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LD17_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD17_RANGE                       17:17
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD17_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD17_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD17_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD17_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD17_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD17_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD17_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD17_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD16_SHIFT                       _MK_SHIFT_CONST(16)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD16_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LD16_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD16_RANGE                       16:16
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD16_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD16_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD16_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD16_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD16_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD16_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD16_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD16_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD15_SHIFT                       _MK_SHIFT_CONST(15)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD15_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LD15_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD15_RANGE                       15:15
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD15_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD15_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD15_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD15_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD15_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD15_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD15_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD15_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD14_SHIFT                       _MK_SHIFT_CONST(14)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD14_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LD14_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD14_RANGE                       14:14
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD14_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD14_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD14_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD14_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD14_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD14_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD14_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD14_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD13_SHIFT                       _MK_SHIFT_CONST(13)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD13_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LD13_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD13_RANGE                       13:13
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD13_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD13_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD13_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD13_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD13_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD13_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD13_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD13_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD12_SHIFT                       _MK_SHIFT_CONST(12)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD12_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LD12_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD12_RANGE                       12:12
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD12_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD12_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD12_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD12_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD12_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD12_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD12_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD12_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD11_SHIFT                       _MK_SHIFT_CONST(11)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD11_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LD11_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD11_RANGE                       11:11
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD11_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD11_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD11_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD11_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD11_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD11_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD11_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD11_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD10_SHIFT                       _MK_SHIFT_CONST(10)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD10_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LD10_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD10_RANGE                       10:10
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD10_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD10_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD10_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD10_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD10_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD10_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD10_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD10_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD9_SHIFT                        _MK_SHIFT_CONST(9)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD9_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LD9_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD9_RANGE                        9:9
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD9_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD9_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD9_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD9_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD9_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD9_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD9_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD9_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD8_SHIFT                        _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD8_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LD8_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD8_RANGE                        8:8
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD8_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD8_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD8_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD8_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD8_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD8_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD7_SHIFT                        _MK_SHIFT_CONST(7)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD7_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LD7_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD7_RANGE                        7:7
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD7_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD7_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD7_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD7_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD7_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD7_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD6_SHIFT                        _MK_SHIFT_CONST(6)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD6_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LD6_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD6_RANGE                        6:6
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD6_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD6_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD6_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD6_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD6_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD6_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD5_SHIFT                        _MK_SHIFT_CONST(5)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD5_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LD5_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD5_RANGE                        5:5
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD5_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD5_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD5_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD5_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD5_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD5_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD4_SHIFT                        _MK_SHIFT_CONST(4)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD4_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LD4_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD4_RANGE                        4:4
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD4_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD4_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD4_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD4_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD4_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD4_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD3_SHIFT                        _MK_SHIFT_CONST(3)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD3_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LD3_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD3_RANGE                        3:3
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD3_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD3_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD3_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD3_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD3_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD3_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD2_SHIFT                        _MK_SHIFT_CONST(2)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD2_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LD2_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD2_RANGE                        2:2
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD2_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD2_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD2_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD2_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD2_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD2_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD1_SHIFT                        _MK_SHIFT_CONST(1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD1_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LD1_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD1_RANGE                        1:1
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD1_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD1_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD1_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD1_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD1_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD1_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD0_SHIFT                        _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD0_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LD0_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD0_RANGE                        0:0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD0_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD0_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD0_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD0_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD0_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD0_TRISTATE                     _MK_ENUM_CONST(1)
+
+
+// Register APB_MISC_PP_TRISTATE_REG_D_0  
+#define APB_MISC_PP_TRISTATE_REG_D_0                    _MK_ADDR_CONST(0x20)
+#define APB_MISC_PP_TRISTATE_REG_D_0_WORD_COUNT                         0x1
+#define APB_MISC_PP_TRISTATE_REG_D_0_RESET_VAL                  _MK_MASK_CONST(0x11ff)
+#define APB_MISC_PP_TRISTATE_REG_D_0_RESET_MASK                         _MK_MASK_CONST(0x1dff)
+#define APB_MISC_PP_TRISTATE_REG_D_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_READ_MASK                  _MK_MASK_CONST(0x1dff)
+#define APB_MISC_PP_TRISTATE_REG_D_0_WRITE_MASK                         _MK_MASK_CONST(0x1dff)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_DTF_SHIFT                        _MK_SHIFT_CONST(12)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_DTF_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_D_0_Z_DTF_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_DTF_RANGE                        12:12
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_DTF_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_DTF_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_DTF_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_DTF_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_DTF_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_DTF_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_DTF_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_DTF_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_GPU7_SHIFT                       _MK_SHIFT_CONST(11)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_GPU7_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_D_0_Z_GPU7_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_GPU7_RANGE                       11:11
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_GPU7_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_GPU7_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_GPU7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_GPU7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_GPU7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_GPU7_INIT_ENUM                   NORMAL
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_GPU7_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_GPU7_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_KBCD_SHIFT                       _MK_SHIFT_CONST(10)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_KBCD_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_D_0_Z_KBCD_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_KBCD_RANGE                       10:10
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_KBCD_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_KBCD_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_KBCD_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_KBCD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_KBCD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_KBCD_INIT_ENUM                   NORMAL
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_KBCD_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_KBCD_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPP_SHIFT                        _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPP_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_D_0_Z_LPP_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPP_RANGE                        8:8
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPP_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPP_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPP_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPP_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPP_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPP_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LHS_SHIFT                        _MK_SHIFT_CONST(7)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LHS_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_D_0_Z_LHS_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LHS_RANGE                        7:7
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LHS_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LHS_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LHS_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LHS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LHS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LHS_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LHS_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LHS_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LDI_SHIFT                        _MK_SHIFT_CONST(6)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LDI_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_D_0_Z_LDI_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LDI_RANGE                        6:6
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LDI_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LDI_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LDI_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LDI_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LDI_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LDI_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LDI_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LDI_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW2_SHIFT                       _MK_SHIFT_CONST(5)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW2_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW2_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW2_RANGE                       5:5
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW2_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW2_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW2_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW2_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW2_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW1_SHIFT                       _MK_SHIFT_CONST(4)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW1_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW1_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW1_RANGE                       4:4
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW1_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW1_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW1_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW1_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW1_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW0_SHIFT                       _MK_SHIFT_CONST(3)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW0_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW0_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW0_RANGE                       3:3
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW0_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW0_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW0_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW0_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW0_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDI_SHIFT                       _MK_SHIFT_CONST(2)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDI_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDI_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDI_RANGE                       2:2
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDI_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDI_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDI_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDI_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDI_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDI_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDI_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDI_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDA_SHIFT                       _MK_SHIFT_CONST(1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDA_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDA_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDA_RANGE                       1:1
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDA_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDA_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDA_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDA_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDA_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDA_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDA_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDA_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSPI_SHIFT                       _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSPI_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_D_0_Z_LSPI_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSPI_RANGE                       0:0
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSPI_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSPI_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSPI_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSPI_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSPI_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSPI_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSPI_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSPI_TRISTATE                    _MK_ENUM_CONST(1)
+
+
+// Register APB_MISC_PP_CONFIG_CTL_0  
+#define APB_MISC_PP_CONFIG_CTL_0                        _MK_ADDR_CONST(0x24)
+#define APB_MISC_PP_CONFIG_CTL_0_WORD_COUNT                     0x1
+#define APB_MISC_PP_CONFIG_CTL_0_RESET_VAL                      _MK_MASK_CONST(0x40)
+#define APB_MISC_PP_CONFIG_CTL_0_RESET_MASK                     _MK_MASK_CONST(0xc0)
+#define APB_MISC_PP_CONFIG_CTL_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_CONFIG_CTL_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_CONFIG_CTL_0_READ_MASK                      _MK_MASK_CONST(0xc0)
+#define APB_MISC_PP_CONFIG_CTL_0_WRITE_MASK                     _MK_MASK_CONST(0xc0)
+//  0 = Disable ; 1 = Enable RTCK Daisychaining
+#define APB_MISC_PP_CONFIG_CTL_0_TBE_SHIFT                      _MK_SHIFT_CONST(7)
+#define APB_MISC_PP_CONFIG_CTL_0_TBE_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_PP_CONFIG_CTL_0_TBE_SHIFT)
+#define APB_MISC_PP_CONFIG_CTL_0_TBE_RANGE                      7:7
+#define APB_MISC_PP_CONFIG_CTL_0_TBE_WOFFSET                    0x0
+#define APB_MISC_PP_CONFIG_CTL_0_TBE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_CONFIG_CTL_0_TBE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_CONFIG_CTL_0_TBE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_CONFIG_CTL_0_TBE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_CONFIG_CTL_0_TBE_INIT_ENUM                  DISABLE
+#define APB_MISC_PP_CONFIG_CTL_0_TBE_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_CONFIG_CTL_0_TBE_ENABLE                     _MK_ENUM_CONST(1)
+
+//  0 = Disable Debug ; 1 = Enable JTAG DBGEN
+#define APB_MISC_PP_CONFIG_CTL_0_JTAG_SHIFT                     _MK_SHIFT_CONST(6)
+#define APB_MISC_PP_CONFIG_CTL_0_JTAG_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_PP_CONFIG_CTL_0_JTAG_SHIFT)
+#define APB_MISC_PP_CONFIG_CTL_0_JTAG_RANGE                     6:6
+#define APB_MISC_PP_CONFIG_CTL_0_JTAG_WOFFSET                   0x0
+#define APB_MISC_PP_CONFIG_CTL_0_JTAG_DEFAULT                   _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_CONFIG_CTL_0_JTAG_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_CONFIG_CTL_0_JTAG_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_CONFIG_CTL_0_JTAG_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_CONFIG_CTL_0_JTAG_INIT_ENUM                 ENABLE
+#define APB_MISC_PP_CONFIG_CTL_0_JTAG_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_CONFIG_CTL_0_JTAG_ENABLE                    _MK_ENUM_CONST(1)
+
+
+// Register APB_MISC_PP_MISC_USB_OTG_0  
+#define APB_MISC_PP_MISC_USB_OTG_0                      _MK_ADDR_CONST(0x28)
+#define APB_MISC_PP_MISC_USB_OTG_0_WORD_COUNT                   0x1
+#define APB_MISC_PP_MISC_USB_OTG_0_RESET_VAL                    _MK_MASK_CONST(0x1000)
+#define APB_MISC_PP_MISC_USB_OTG_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_MISC_USB_OTG_0_WRITE_MASK                   _MK_MASK_CONST(0xfc7fff29)
+// Wake on Disconnect Enable (device mode)
+// When enabled (1), USB PHY will wakeup
+// from suspend on a disconnect event.
+// Software should only set this bit when
+// the USB PHY is suspended (bit 2 -
+// SUSPENDED = 1).
+// Also, software should clear it after
+// detecting a wakeup event.
+#define APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_DISCON_EN_SHIFT                      _MK_SHIFT_CONST(31)
+#define APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_DISCON_EN_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_DISCON_EN_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_DISCON_EN_RANGE                      31:31
+#define APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_DISCON_EN_WOFFSET                    0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_DISCON_EN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_DISCON_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_DISCON_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_DISCON_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_DISCON_EN_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_DISCON_EN_ENABLE                     _MK_ENUM_CONST(1)
+
+// Wake on Connect Enable (device mode)
+// When enabled (1), USB PHY will wakeup
+// from suspend on a connect event.
+// Software should only set this bit when
+// the USB PHY is suspended (bit 2 -
+// SUSPENDED = 1).
+// Also, software should clear it after
+// detecting a wakeup event.
+#define APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_CNNT_EN_SHIFT                        _MK_SHIFT_CONST(30)
+#define APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_CNNT_EN_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_CNNT_EN_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_CNNT_EN_RANGE                        30:30
+#define APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_CNNT_EN_WOFFSET                      0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_CNNT_EN_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_CNNT_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_CNNT_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_CNNT_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_CNNT_EN_DISABLE                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_CNNT_EN_ENABLE                       _MK_ENUM_CONST(1)
+
+// Debug bus select for USB 
+// Software should not change this.
+#define APB_MISC_PP_MISC_USB_OTG_0_USB_DEBUG_SEL_SHIFT                  _MK_SHIFT_CONST(26)
+#define APB_MISC_PP_MISC_USB_OTG_0_USB_DEBUG_SEL_FIELD                  (_MK_MASK_CONST(0xf) << APB_MISC_PP_MISC_USB_OTG_0_USB_DEBUG_SEL_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_USB_DEBUG_SEL_RANGE                  29:26
+#define APB_MISC_PP_MISC_USB_OTG_0_USB_DEBUG_SEL_WOFFSET                        0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_USB_DEBUG_SEL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_USB_DEBUG_SEL_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
+#define APB_MISC_PP_MISC_USB_OTG_0_USB_DEBUG_SEL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_USB_DEBUG_SEL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// B_SESS_END status from USB PHY.
+// This field is the same as the field
+// B_SESS_END_STS in register USB_PHY_VBUS_SENSORS.
+#define APB_MISC_PP_MISC_USB_OTG_0_B_SESS_END_STS2_SHIFT                        _MK_SHIFT_CONST(25)
+#define APB_MISC_PP_MISC_USB_OTG_0_B_SESS_END_STS2_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_B_SESS_END_STS2_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_B_SESS_END_STS2_RANGE                        25:25
+#define APB_MISC_PP_MISC_USB_OTG_0_B_SESS_END_STS2_WOFFSET                      0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_B_SESS_END_STS2_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_B_SESS_END_STS2_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_B_SESS_END_STS2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_B_SESS_END_STS2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_B_SESS_END_STS2_UNSET                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_B_SESS_END_STS2_SET                  _MK_ENUM_CONST(1)
+
+// A_VBUS_VLD status from USB PHY.
+// This field is the same as the field
+// A_VBUS_VLD_STS in register USB_PHY_VBUS_SENSORS.
+#define APB_MISC_PP_MISC_USB_OTG_0_A_VBUS_VLD_STS2_SHIFT                        _MK_SHIFT_CONST(24)
+#define APB_MISC_PP_MISC_USB_OTG_0_A_VBUS_VLD_STS2_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_A_VBUS_VLD_STS2_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_A_VBUS_VLD_STS2_RANGE                        24:24
+#define APB_MISC_PP_MISC_USB_OTG_0_A_VBUS_VLD_STS2_WOFFSET                      0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_A_VBUS_VLD_STS2_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_A_VBUS_VLD_STS2_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_A_VBUS_VLD_STS2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_A_VBUS_VLD_STS2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_A_VBUS_VLD_STS2_UNSET                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_A_VBUS_VLD_STS2_SET                  _MK_ENUM_CONST(1)
+
+// A_SESS_VLD status from USB PHY.
+// This field is the same as the field
+// A_SESS_VLD_STS in register USB_PHY_VBUS_SENSORS.
+#define APB_MISC_PP_MISC_USB_OTG_0_A_SESS_VLD_STS2_SHIFT                        _MK_SHIFT_CONST(23)
+#define APB_MISC_PP_MISC_USB_OTG_0_A_SESS_VLD_STS2_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_A_SESS_VLD_STS2_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_A_SESS_VLD_STS2_RANGE                        23:23
+#define APB_MISC_PP_MISC_USB_OTG_0_A_SESS_VLD_STS2_WOFFSET                      0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_A_SESS_VLD_STS2_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_A_SESS_VLD_STS2_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_A_SESS_VLD_STS2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_A_SESS_VLD_STS2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_A_SESS_VLD_STS2_UNSET                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_A_SESS_VLD_STS2_SET                  _MK_ENUM_CONST(1)
+
+// Software_B_SESS_END status.
+// Software should write the appropriate
+// value (1/0) to set/unset the B_SESS_END status.
+// This field is the same as the field
+// B_SESS_END_SW_VALUE in register USB_PHY_VBUS_SENSORS.
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_SHIFT                  _MK_SHIFT_CONST(22)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_RANGE                  22:22
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_WOFFSET                        0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_UNSET                  _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_SET                    _MK_ENUM_CONST(1)
+
+// Enable Software Controlled B_SESS_END.
+// Software sets this bit to drive the
+// value in  SW_B_SESS_END to the USB
+// controller.
+// This field is the same as the field
+// B_SESS_END_SW_EN in register USB_PHY_VBUS_SENSORS.
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_EN_SHIFT                       _MK_SHIFT_CONST(21)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_EN_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_EN_RANGE                       21:21
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_EN_WOFFSET                     0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// Software_A_VBUS_VLD status.
+// Software should write the appropriate
+// value (1/0) to set/unset the A_VBUS_VLD status.
+// This field is the same as the field
+// A_VBUS_VLD_SW_VALUE in register USB_PHY_VBUS_SENSORS.
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_SHIFT                  _MK_SHIFT_CONST(20)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_RANGE                  20:20
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_WOFFSET                        0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_UNSET                  _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_SET                    _MK_ENUM_CONST(1)
+
+// Enable Software Controlled A_VBUS_VLD.
+// Software sets this bit to drive the
+// value in SW_A_VBUS_VLD to the USB
+// controller.
+// This field is the same as the field
+// A_VBUS_VLD_SW_EN in register USB_PHY_VBUS_SENSORS.
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_EN_SHIFT                       _MK_SHIFT_CONST(19)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_EN_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_EN_RANGE                       19:19
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_EN_WOFFSET                     0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// Software_A_SESS_VLD status.
+// Software should write the appropriate
+// value (1/0) to set/unset the A_SESS_VLD status.
+// This field is the same as the field
+// A_SESS_VLD_SW_VALUE in register USB_PHY_VBUS_SENSORS.
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_SHIFT                  _MK_SHIFT_CONST(18)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_RANGE                  18:18
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_WOFFSET                        0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_UNSET                  _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_SET                    _MK_ENUM_CONST(1)
+
+// Enable Software Controlled A_SESS_VLD.
+// Software sets this bit to drive the
+// value in SW_A_SESS_VLD to the USB
+// controller.
+// This field is the same as the field
+// A_SESS_VLD_SW_EN in register USB_PHY_VBUS_SENSORS.
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_EN_SHIFT                       _MK_SHIFT_CONST(17)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_EN_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_EN_RANGE                       17:17
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_EN_WOFFSET                     0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// Suspend Set
+// Software must write a 1 to this bit to put the USB PHY in
+// suspend mode. Software should do this only after making sure that
+// the USB is indeed in suspend mode. Setting this bit will stop the
+// PHY clock. Software should write a 0 to clear it.
+// NOTE: It is required that software generate a positive pulse on this
+// bit to guarantee proper operation.
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSP_SET_SHIFT                       _MK_SHIFT_CONST(16)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSP_SET_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_SUSP_SET_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSP_SET_RANGE                       16:16
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSP_SET_WOFFSET                     0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSP_SET_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSP_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSP_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSP_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSP_SET_UNSET                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSP_SET_SET                 _MK_ENUM_CONST(1)
+
+// VBUS Change Interrupt Enable
+// If set, an interrupt will be generated whenever
+// A_SESS_VLD changes value. Software can read the
+// value of A_SESS_VLD from A_SESS_VLD_STS2 bit.
+// This field is the same as the field
+// A_SESS_VLD_INT_EN in register USB_PHY_VBUS_SENSORS.
+#define APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_INT_EN_SHIFT                        _MK_SHIFT_CONST(15)
+#define APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_INT_EN_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_INT_EN_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_INT_EN_RANGE                        15:15
+#define APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_INT_EN_WOFFSET                      0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_INT_EN_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_INT_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_INT_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_INT_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_INT_EN_DISABLE                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_INT_EN_ENABLE                       _MK_ENUM_CONST(1)
+
+// Software controlled OTG_ID.
+// If SW_OTG_ID_EN = 1, then software needs to monitor
+// actual OTG_ID bit used  as a GPIO and based on the value of OTG_ID,
+// it can set this bit.
+// This field is the same as the field
+// ID_SW_VALUE in register USB_PHY_VBUS_WAKEUP_ID.
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_SHIFT                      _MK_SHIFT_CONST(14)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_RANGE                      14:14
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_WOFFSET                    0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_UNSET                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_SET                        _MK_ENUM_CONST(1)
+
+// Reserved
+#define APB_MISC_PP_MISC_USB_OTG_0_RSVD13_SHIFT                 _MK_SHIFT_CONST(13)
+#define APB_MISC_PP_MISC_USB_OTG_0_RSVD13_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_RSVD13_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_RSVD13_RANGE                 13:13
+#define APB_MISC_PP_MISC_USB_OTG_0_RSVD13_WOFFSET                       0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_RSVD13_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_RSVD13_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_RSVD13_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_RSVD13_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// ID pullup enable.
+// This field controls the internal pull-up to
+// OTG_ID pin. Software should set this to
+// 1 if using internal OTG_ID. If software
+// is using a GPIO for OTG_ID, then it
+// can write this to 0.
+#define APB_MISC_PP_MISC_USB_OTG_0_ID_PU_SHIFT                  _MK_SHIFT_CONST(12)
+#define APB_MISC_PP_MISC_USB_OTG_0_ID_PU_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_ID_PU_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_ID_PU_RANGE                  12:12
+#define APB_MISC_PP_MISC_USB_OTG_0_ID_PU_WOFFSET                        0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_ID_PU_DEFAULT                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_ID_PU_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_ID_PU_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_ID_PU_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_ID_PU_DISABLE                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_ID_PU_ENABLE                 _MK_ENUM_CONST(1)
+
+//Suspend Clear
+// Software must write a 1 to this bit to bring the PHY
+// out of suspend mode. This is used when the software stops the PHY
+// clock during suspend and then wants to initiate a resume. Software
+// should also write 0 to clear it.
+// NOTE: It is required that software generate a  positive pulse on this
+// bit to guarantee proper operation.
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSP_CLR_SHIFT                       _MK_SHIFT_CONST(11)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSP_CLR_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_SUSP_CLR_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSP_CLR_RANGE                       11:11
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSP_CLR_WOFFSET                     0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSP_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSP_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSP_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSP_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSP_CLR_UNSET                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSP_CLR_SET                 _MK_ENUM_CONST(1)
+
+// Wake/resume on VBUS change change detect
+// If enabled, the USB PHY will wake up whenever a
+// change in A_SESS_VLD is detected.
+// This should be set only when USB PHY is already
+// suspended.
+#define APB_MISC_PP_MISC_USB_OTG_0_RSM_VBUS_CHG_SHIFT                   _MK_SHIFT_CONST(10)
+#define APB_MISC_PP_MISC_USB_OTG_0_RSM_VBUS_CHG_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_RSM_VBUS_CHG_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_RSM_VBUS_CHG_RANGE                   10:10
+#define APB_MISC_PP_MISC_USB_OTG_0_RSM_VBUS_CHG_WOFFSET                 0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_RSM_VBUS_CHG_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_RSM_VBUS_CHG_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_RSM_VBUS_CHG_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_RSM_VBUS_CHG_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_RSM_VBUS_CHG_DISABLE                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_RSM_VBUS_CHG_ENABLE                  _MK_ENUM_CONST(1)
+
+// Resume/Clock valid interrupt enable
+// If this bit is enabled, interrupt is generated
+// whenever PHY clock becomes valid.
+#define APB_MISC_PP_MISC_USB_OTG_0_RSM_IE_SHIFT                 _MK_SHIFT_CONST(9)
+#define APB_MISC_PP_MISC_USB_OTG_0_RSM_IE_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_RSM_IE_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_RSM_IE_RANGE                 9:9
+#define APB_MISC_PP_MISC_USB_OTG_0_RSM_IE_WOFFSET                       0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_RSM_IE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_RSM_IE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_RSM_IE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_RSM_IE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_RSM_IE_DISABLE                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_RSM_IE_ENABLE                        _MK_ENUM_CONST(1)
+
+// Wake on resume enable
+// If this bit is enabled, USB PHY will wakeup from
+// suspend whenever resume/reset signaling is
+// detected on USB.
+#define APB_MISC_PP_MISC_USB_OTG_0_WK_RSM_EN_SHIFT                      _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_MISC_USB_OTG_0_WK_RSM_EN_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_WK_RSM_EN_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_WK_RSM_EN_RANGE                      8:8
+#define APB_MISC_PP_MISC_USB_OTG_0_WK_RSM_EN_WOFFSET                    0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_WK_RSM_EN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_WK_RSM_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_WK_RSM_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_WK_RSM_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_WK_RSM_EN_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_WK_RSM_EN_ENABLE                     _MK_ENUM_CONST(1)
+
+// PHY clock valid status
+// This bit is set whenever PHY clock becomes valid.
+// It is cleared whenever PHY clock stops.
+#define APB_MISC_PP_MISC_USB_OTG_0_PCLKVLD_SHIFT                        _MK_SHIFT_CONST(7)
+#define APB_MISC_PP_MISC_USB_OTG_0_PCLKVLD_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_PCLKVLD_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_PCLKVLD_RANGE                        7:7
+#define APB_MISC_PP_MISC_USB_OTG_0_PCLKVLD_WOFFSET                      0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_PCLKVLD_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_PCLKVLD_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_PCLKVLD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_PCLKVLD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_PCLKVLD_UNSET                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_PCLKVLD_SET                  _MK_ENUM_CONST(1)
+
+// VBUS change detect
+// This bit is set whenever a change in A_SESS_VLD
+// is detected.
+// Software can read the status of A_SESS_VLD from 
+// A_SESS_VLD_STS2 bit.
+// This field is the same as the field
+// A_SESS_VLD_CHG_DET in register USB_PHY_VBUS_SENSORS.
+#define APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_DET_SHIFT                   _MK_SHIFT_CONST(6)
+#define APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_DET_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_DET_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_DET_RANGE                   6:6
+#define APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_DET_WOFFSET                 0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_DET_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_DET_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_DET_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_DET_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_DET_UNSET                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_DET_SET                     _MK_ENUM_CONST(1)
+
+// Loopback enable
+// Not for normal software use
+#define APB_MISC_PP_MISC_USB_OTG_0_LPBK_EN_SHIFT                        _MK_SHIFT_CONST(5)
+#define APB_MISC_PP_MISC_USB_OTG_0_LPBK_EN_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_LPBK_EN_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_LPBK_EN_RANGE                        5:5
+#define APB_MISC_PP_MISC_USB_OTG_0_LPBK_EN_WOFFSET                      0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_LPBK_EN_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_LPBK_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_LPBK_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_LPBK_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_LPBK_EN_DISABLE                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_LPBK_EN_ENABLE                       _MK_ENUM_CONST(1)
+
+// Real OTG_ID status from the USB PHY.
+// This field is the same as the field
+// ID_STS in register USB_PHY_VBUS_WAKEUP_ID.
+#define APB_MISC_PP_MISC_USB_OTG_0_OTG_ID_SHIFT                 _MK_SHIFT_CONST(4)
+#define APB_MISC_PP_MISC_USB_OTG_0_OTG_ID_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_OTG_ID_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_OTG_ID_RANGE                 4:4
+#define APB_MISC_PP_MISC_USB_OTG_0_OTG_ID_WOFFSET                       0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_OTG_ID_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_OTG_ID_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_OTG_ID_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_OTG_ID_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_OTG_ID_UNSET                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_OTG_ID_SET                   _MK_ENUM_CONST(1)
+
+// Enable Software Controlled OTG_ID
+// If using a GPIO for OTG_ID signal, then
+// software can set this to 1 and write
+// the value from the GPIO to the
+// SW_OTG_ID bit in this register.
+// This field is the same as the field
+// ID_SW_EN in register USB_PHY_VBUS_WAKEUP_ID.
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_EN_SHIFT                   _MK_SHIFT_CONST(3)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_EN_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_EN_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_EN_RANGE                   3:3
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_EN_WOFFSET                 0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_EN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_EN_DISABLE                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_EN_ENABLE                  _MK_ENUM_CONST(1)
+
+// USB PHY suspend status
+// This bit is set to 1 whenver USB is suspended and the PHY clock isnt  available.
+// NOTE: Software should not access any
+// registers in USB controller when this
+// bit is set.
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSPENDED_SHIFT                      _MK_SHIFT_CONST(2)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSPENDED_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_SUSPENDED_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSPENDED_RANGE                      2:2
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSPENDED_WOFFSET                    0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSPENDED_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSPENDED_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSPENDED_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSPENDED_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSPENDED_UNSET                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSPENDED_SET                        _MK_ENUM_CONST(1)
+
+// Static General purpose input coming from ID pin
+#define APB_MISC_PP_MISC_USB_OTG_0_StaticGpi_SHIFT                      _MK_SHIFT_CONST(1)
+#define APB_MISC_PP_MISC_USB_OTG_0_StaticGpi_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_StaticGpi_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_StaticGpi_RANGE                      1:1
+#define APB_MISC_PP_MISC_USB_OTG_0_StaticGpi_WOFFSET                    0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_StaticGpi_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_StaticGpi_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_StaticGpi_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_StaticGpi_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_StaticGpi_UNSET                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_StaticGpi_SET                        _MK_ENUM_CONST(1)
+
+// Polarity of the suspend signal going to USB PHY
+// Software should not change this.
+#define APB_MISC_PP_MISC_USB_OTG_0_SUS_POL_SHIFT                        _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUS_POL_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_SUS_POL_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUS_POL_RANGE                        0:0
+#define APB_MISC_PP_MISC_USB_OTG_0_SUS_POL_WOFFSET                      0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_SUS_POL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUS_POL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUS_POL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUS_POL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUS_POL_ACTIVE_LOW                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUS_POL_ACTIVE_HIGH                  _MK_ENUM_CONST(1)
+
+
+// Register APB_MISC_PP_XMB_CSR_0  
+#define APB_MISC_PP_XMB_CSR_0                   _MK_ADDR_CONST(0x30)
+#define APB_MISC_PP_XMB_CSR_0_WORD_COUNT                        0x1
+#define APB_MISC_PP_XMB_CSR_0_RESET_VAL                         _MK_MASK_CONST(0x58007410)
+#define APB_MISC_PP_XMB_CSR_0_RESET_MASK                        _MK_MASK_CONST(0xde04ffff)
+#define APB_MISC_PP_XMB_CSR_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_CSR_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_CSR_0_READ_MASK                         _MK_MASK_CONST(0xde04ffff)
+#define APB_MISC_PP_XMB_CSR_0_WRITE_MASK                        _MK_MASK_CONST(0x5004ffff)
+// External ROM Busy indicator.
+#define APB_MISC_PP_XMB_CSR_0_ROM_IORDY_IN_SHIFT                        _MK_SHIFT_CONST(31)
+#define APB_MISC_PP_XMB_CSR_0_ROM_IORDY_IN_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_XMB_CSR_0_ROM_IORDY_IN_SHIFT)
+#define APB_MISC_PP_XMB_CSR_0_ROM_IORDY_IN_RANGE                        31:31
+#define APB_MISC_PP_XMB_CSR_0_ROM_IORDY_IN_WOFFSET                      0x0
+#define APB_MISC_PP_XMB_CSR_0_ROM_IORDY_IN_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_CSR_0_ROM_IORDY_IN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_XMB_CSR_0_ROM_IORDY_IN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_CSR_0_ROM_IORDY_IN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// 0 = Write Protected (def)
+#define APB_MISC_PP_XMB_CSR_0_ROM_WE_SHIFT                      _MK_SHIFT_CONST(30)
+#define APB_MISC_PP_XMB_CSR_0_ROM_WE_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_PP_XMB_CSR_0_ROM_WE_SHIFT)
+#define APB_MISC_PP_XMB_CSR_0_ROM_WE_RANGE                      30:30
+#define APB_MISC_PP_XMB_CSR_0_ROM_WE_WOFFSET                    0x0
+#define APB_MISC_PP_XMB_CSR_0_ROM_WE_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_XMB_CSR_0_ROM_WE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_XMB_CSR_0_ROM_WE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_CSR_0_ROM_WE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// 0 = Strobe edge
+#define APB_MISC_PP_XMB_CSR_0_DQM_MASK_MODE_SHIFT                       _MK_SHIFT_CONST(28)
+#define APB_MISC_PP_XMB_CSR_0_DQM_MASK_MODE_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_XMB_CSR_0_DQM_MASK_MODE_SHIFT)
+#define APB_MISC_PP_XMB_CSR_0_DQM_MASK_MODE_RANGE                       28:28
+#define APB_MISC_PP_XMB_CSR_0_DQM_MASK_MODE_WOFFSET                     0x0
+#define APB_MISC_PP_XMB_CSR_0_DQM_MASK_MODE_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_XMB_CSR_0_DQM_MASK_MODE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_XMB_CSR_0_DQM_MASK_MODE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_CSR_0_DQM_MASK_MODE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// 0 = Buffer not empty 1 = Buffer empty (default) (RO  register)
+#define APB_MISC_PP_XMB_CSR_0_AHB_BUF_MT_SHIFT                  _MK_SHIFT_CONST(27)
+#define APB_MISC_PP_XMB_CSR_0_AHB_BUF_MT_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_PP_XMB_CSR_0_AHB_BUF_MT_SHIFT)
+#define APB_MISC_PP_XMB_CSR_0_AHB_BUF_MT_RANGE                  27:27
+#define APB_MISC_PP_XMB_CSR_0_AHB_BUF_MT_WOFFSET                        0x0
+#define APB_MISC_PP_XMB_CSR_0_AHB_BUF_MT_DEFAULT                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_XMB_CSR_0_AHB_BUF_MT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_XMB_CSR_0_AHB_BUF_MT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_CSR_0_AHB_BUF_MT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// 0 = Buffer Not full (default) 1 = Buffer Full (RO  register)
+#define APB_MISC_PP_XMB_CSR_0_AHB_BUF_FULL_SHIFT                        _MK_SHIFT_CONST(26)
+#define APB_MISC_PP_XMB_CSR_0_AHB_BUF_FULL_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_XMB_CSR_0_AHB_BUF_FULL_SHIFT)
+#define APB_MISC_PP_XMB_CSR_0_AHB_BUF_FULL_RANGE                        26:26
+#define APB_MISC_PP_XMB_CSR_0_AHB_BUF_FULL_WOFFSET                      0x0
+#define APB_MISC_PP_XMB_CSR_0_AHB_BUF_FULL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_CSR_0_AHB_BUF_FULL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_XMB_CSR_0_AHB_BUF_FULL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_CSR_0_AHB_BUF_FULL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// 0 = Buffer empty (default) 1 = Buffer full (RO  register)
+#define APB_MISC_PP_XMB_CSR_0_DC_BUF_FULL_SHIFT                 _MK_SHIFT_CONST(25)
+#define APB_MISC_PP_XMB_CSR_0_DC_BUF_FULL_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_PP_XMB_CSR_0_DC_BUF_FULL_SHIFT)
+#define APB_MISC_PP_XMB_CSR_0_DC_BUF_FULL_RANGE                 25:25
+#define APB_MISC_PP_XMB_CSR_0_DC_BUF_FULL_WOFFSET                       0x0
+#define APB_MISC_PP_XMB_CSR_0_DC_BUF_FULL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_CSR_0_DC_BUF_FULL_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_XMB_CSR_0_DC_BUF_FULL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_CSR_0_DC_BUF_FULL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// 0 = don't mask mio_rdy 1 = mask mio_rdy
+#define APB_MISC_PP_XMB_CSR_0_MASK_MIO_RDY_SHIFT                        _MK_SHIFT_CONST(18)
+#define APB_MISC_PP_XMB_CSR_0_MASK_MIO_RDY_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_XMB_CSR_0_MASK_MIO_RDY_SHIFT)
+#define APB_MISC_PP_XMB_CSR_0_MASK_MIO_RDY_RANGE                        18:18
+#define APB_MISC_PP_XMB_CSR_0_MASK_MIO_RDY_WOFFSET                      0x0
+#define APB_MISC_PP_XMB_CSR_0_MASK_MIO_RDY_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_CSR_0_MASK_MIO_RDY_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_XMB_CSR_0_MASK_MIO_RDY_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_CSR_0_MASK_MIO_RDY_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+//  1XXX = Reserved
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_D_SHIFT                   _MK_SHIFT_CONST(12)
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_D_FIELD                   (_MK_MASK_CONST(0xf) << APB_MISC_PP_XMB_CSR_0_XMB_CSN_D_SHIFT)
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_D_RANGE                   15:12
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_D_WOFFSET                 0x0
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_D_DEFAULT                 _MK_MASK_CONST(0x7)
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_D_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_D_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_D_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_D_ROM0                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_D_ROM1                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_D_XMEM1                   _MK_ENUM_CONST(5)
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_D_MIO0                    _MK_ENUM_CONST(6)
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_D_MIO1                    _MK_ENUM_CONST(7)
+
+//  1XXX = Reserved
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_C_SHIFT                   _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_C_FIELD                   (_MK_MASK_CONST(0xf) << APB_MISC_PP_XMB_CSR_0_XMB_CSN_C_SHIFT)
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_C_RANGE                   11:8
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_C_WOFFSET                 0x0
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_C_DEFAULT                 _MK_MASK_CONST(0x4)
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_C_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_C_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_C_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_C_ROM0                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_C_ROM1                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_C_XMEM0                   _MK_ENUM_CONST(4)
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_C_MIO0                    _MK_ENUM_CONST(6)
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_C_MIO1                    _MK_ENUM_CONST(7)
+
+//  1XXX = Reserved
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_B_SHIFT                   _MK_SHIFT_CONST(4)
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_B_FIELD                   (_MK_MASK_CONST(0xf) << APB_MISC_PP_XMB_CSR_0_XMB_CSN_B_SHIFT)
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_B_RANGE                   7:4
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_B_WOFFSET                 0x0
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_B_DEFAULT                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_B_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_B_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_B_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_B_ROM0                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_B_ROM1                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_B_MIO0                    _MK_ENUM_CONST(6)
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_B_MIO1                    _MK_ENUM_CONST(7)
+
+//  1XXX = Reserved
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_A_SHIFT                   _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_A_FIELD                   (_MK_MASK_CONST(0xf) << APB_MISC_PP_XMB_CSR_0_XMB_CSN_A_SHIFT)
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_A_RANGE                   3:0
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_A_WOFFSET                 0x0
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_A_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_A_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_A_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_A_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_A_ROM0                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_A_ROM1                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_A_MIO0                    _MK_ENUM_CONST(6)
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_A_MIO1                    _MK_ENUM_CONST(7)
+
+
+// Register APB_MISC_PP_XMB_NOR_FLASH_CFG_0  
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0                 _MK_ADDR_CONST(0x34)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_WORD_COUNT                      0x1
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_RESET_VAL                       _MK_MASK_CONST(0x1f1f)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_RESET_MASK                      _MK_MASK_CONST(0xc3ff3f3f)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_READ_MASK                       _MK_MASK_CONST(0xc3ff3f3f)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_WRITE_MASK                      _MK_MASK_CONST(0xc3ff3f3f)
+// writing 1 clears nor_muxerr interrupt
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_NOR_MUXERR_INT_CLR_SHIFT                        _MK_SHIFT_CONST(31)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_NOR_MUXERR_INT_CLR_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_XMB_NOR_FLASH_CFG_0_NOR_MUXERR_INT_CLR_SHIFT)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_NOR_MUXERR_INT_CLR_RANGE                        31:31
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_NOR_MUXERR_INT_CLR_WOFFSET                      0x0
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_NOR_MUXERR_INT_CLR_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_NOR_MUXERR_INT_CLR_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_NOR_MUXERR_INT_CLR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_NOR_MUXERR_INT_CLR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// 0 = mask interrupt 1 = don't mask interrupt
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_NOR_MUXERR_INT_MASK_SHIFT                       _MK_SHIFT_CONST(30)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_NOR_MUXERR_INT_MASK_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_XMB_NOR_FLASH_CFG_0_NOR_MUXERR_INT_MASK_SHIFT)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_NOR_MUXERR_INT_MASK_RANGE                       30:30
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_NOR_MUXERR_INT_MASK_WOFFSET                     0x0
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_NOR_MUXERR_INT_MASK_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_NOR_MUXERR_INT_MASK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_NOR_MUXERR_INT_MASK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_NOR_MUXERR_INT_MASK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// NOR minimum transaction time
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_NOR_MIN_TRANS_TIME_SHIFT                        _MK_SHIFT_CONST(16)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_NOR_MIN_TRANS_TIME_FIELD                        (_MK_MASK_CONST(0x3ff) << APB_MISC_PP_XMB_NOR_FLASH_CFG_0_NOR_MIN_TRANS_TIME_SHIFT)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_NOR_MIN_TRANS_TIME_RANGE                        25:16
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_NOR_MIN_TRANS_TIME_WOFFSET                      0x0
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_NOR_MIN_TRANS_TIME_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_NOR_MIN_TRANS_TIME_DEFAULT_MASK                 _MK_MASK_CONST(0x3ff)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_NOR_MIN_TRANS_TIME_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_NOR_MIN_TRANS_TIME_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// ROM Wait cycles after Write. (in SCLK)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_ROM_WR_DEAD_TIME_SHIFT                  _MK_SHIFT_CONST(12)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_ROM_WR_DEAD_TIME_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_XMB_NOR_FLASH_CFG_0_ROM_WR_DEAD_TIME_SHIFT)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_ROM_WR_DEAD_TIME_RANGE                  13:12
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_ROM_WR_DEAD_TIME_WOFFSET                        0x0
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_ROM_WR_DEAD_TIME_DEFAULT                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_ROM_WR_DEAD_TIME_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_ROM_WR_DEAD_TIME_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_ROM_WR_DEAD_TIME_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// ROM Write time (in number of SCLK cycles)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_ROM_WR_TIME_SHIFT                       _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_ROM_WR_TIME_FIELD                       (_MK_MASK_CONST(0xf) << APB_MISC_PP_XMB_NOR_FLASH_CFG_0_ROM_WR_TIME_SHIFT)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_ROM_WR_TIME_RANGE                       11:8
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_ROM_WR_TIME_WOFFSET                     0x0
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_ROM_WR_TIME_DEFAULT                     _MK_MASK_CONST(0xf)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_ROM_WR_TIME_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_ROM_WR_TIME_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_ROM_WR_TIME_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// ROM Wait cycles after Read (in SCLK)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_ROM_RD_DEAD_TIME_SHIFT                  _MK_SHIFT_CONST(4)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_ROM_RD_DEAD_TIME_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_XMB_NOR_FLASH_CFG_0_ROM_RD_DEAD_TIME_SHIFT)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_ROM_RD_DEAD_TIME_RANGE                  5:4
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_ROM_RD_DEAD_TIME_WOFFSET                        0x0
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_ROM_RD_DEAD_TIME_DEFAULT                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_ROM_RD_DEAD_TIME_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_ROM_RD_DEAD_TIME_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_ROM_RD_DEAD_TIME_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// ROM Read time (in number of SCLK cycles)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_ROM_RD_TIME_SHIFT                       _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_ROM_RD_TIME_FIELD                       (_MK_MASK_CONST(0xf) << APB_MISC_PP_XMB_NOR_FLASH_CFG_0_ROM_RD_TIME_SHIFT)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_ROM_RD_TIME_RANGE                       3:0
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_ROM_RD_TIME_WOFFSET                     0x0
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_ROM_RD_TIME_DEFAULT                     _MK_MASK_CONST(0xf)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_ROM_RD_TIME_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_ROM_RD_TIME_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_ROM_RD_TIME_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Reserved address 56 [0x38] 
+
+// Register APB_MISC_PP_XMB_MIO_CFG_0  
+#define APB_MISC_PP_XMB_MIO_CFG_0                       _MK_ADDR_CONST(0x40)
+#define APB_MISC_PP_XMB_MIO_CFG_0_WORD_COUNT                    0x1
+#define APB_MISC_PP_XMB_MIO_CFG_0_RESET_VAL                     _MK_MASK_CONST(0x1f1f1f1f)
+#define APB_MISC_PP_XMB_MIO_CFG_0_RESET_MASK                    _MK_MASK_CONST(0x7f7f7f7f)
+#define APB_MISC_PP_XMB_MIO_CFG_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_MIO_CFG_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_MIO_CFG_0_READ_MASK                     _MK_MASK_CONST(0x7f7f7f7f)
+#define APB_MISC_PP_XMB_MIO_CFG_0_WRITE_MASK                    _MK_MASK_CONST(0x7f7f7f7f)
+// end of a write access and goes low for the start  of another read or write access.
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_B_WR_DEAD_TIME_SHIFT                      _MK_SHIFT_CONST(28)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_B_WR_DEAD_TIME_FIELD                      (_MK_MASK_CONST(0x7) << APB_MISC_PP_XMB_MIO_CFG_0_MIO_B_WR_DEAD_TIME_SHIFT)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_B_WR_DEAD_TIME_RANGE                      30:28
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_B_WR_DEAD_TIME_WOFFSET                    0x0
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_B_WR_DEAD_TIME_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_B_WR_DEAD_TIME_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_B_WR_DEAD_TIME_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_B_WR_DEAD_TIME_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// signal is set low for MIO1. This period extends  beyond the programmed period as long as MIO_RDY signal remains low. MIO_RDY  is connected to a slave wait pin, both active low. As long as this signal is  low, PP5003 maintains all the MIO signals stable, as it waits for the slave  to complete the access. Request is removed after signal goes high.
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_B_WR_TIME_SHIFT                   _MK_SHIFT_CONST(24)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_B_WR_TIME_FIELD                   (_MK_MASK_CONST(0xf) << APB_MISC_PP_XMB_MIO_CFG_0_MIO_B_WR_TIME_SHIFT)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_B_WR_TIME_RANGE                   27:24
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_B_WR_TIME_WOFFSET                 0x0
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_B_WR_TIME_DEFAULT                 _MK_MASK_CONST(0xf)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_B_WR_TIME_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_B_WR_TIME_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_B_WR_TIME_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// start of the following access for MIO1. (The chip  select goes high at the end of a read access and goes low at the start of a  read or write access.)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_B_RD_DEAD_TIME_SHIFT                      _MK_SHIFT_CONST(20)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_B_RD_DEAD_TIME_FIELD                      (_MK_MASK_CONST(0x7) << APB_MISC_PP_XMB_MIO_CFG_0_MIO_B_RD_DEAD_TIME_SHIFT)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_B_RD_DEAD_TIME_RANGE                      22:20
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_B_RD_DEAD_TIME_WOFFSET                    0x0
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_B_RD_DEAD_TIME_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_B_RD_DEAD_TIME_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_B_RD_DEAD_TIME_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_B_RD_DEAD_TIME_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// signal is set low for MIO1. This period extends  beyond the programmed period as long as MIO_RDY signal remains low. MIO_RDY  is connected to a slave wait pin, both active low. As long as this signal is  low, PP5003 maintains all the MIO signals
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_B_RD_TIME_SHIFT                   _MK_SHIFT_CONST(16)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_B_RD_TIME_FIELD                   (_MK_MASK_CONST(0xf) << APB_MISC_PP_XMB_MIO_CFG_0_MIO_B_RD_TIME_SHIFT)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_B_RD_TIME_RANGE                   19:16
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_B_RD_TIME_WOFFSET                 0x0
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_B_RD_TIME_DEFAULT                 _MK_MASK_CONST(0xf)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_B_RD_TIME_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_B_RD_TIME_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_B_RD_TIME_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// the start of the following access (write or read)  for MIO0 . Chip select goes high at the end of a write access and goes low  for the start of another read or write access.
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_A_WR_DEAD_TIME_SHIFT                      _MK_SHIFT_CONST(12)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_A_WR_DEAD_TIME_FIELD                      (_MK_MASK_CONST(0x7) << APB_MISC_PP_XMB_MIO_CFG_0_MIO_A_WR_DEAD_TIME_SHIFT)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_A_WR_DEAD_TIME_RANGE                      14:12
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_A_WR_DEAD_TIME_WOFFSET                    0x0
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_A_WR_DEAD_TIME_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_A_WR_DEAD_TIME_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_A_WR_DEAD_TIME_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_A_WR_DEAD_TIME_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// during a write access for MIO0. This period  extends as long as the MIO_RDY signal remains low.
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_A_WR_TIME_SHIFT                   _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_A_WR_TIME_FIELD                   (_MK_MASK_CONST(0xf) << APB_MISC_PP_XMB_MIO_CFG_0_MIO_A_WR_TIME_SHIFT)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_A_WR_TIME_RANGE                   11:8
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_A_WR_TIME_WOFFSET                 0x0
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_A_WR_TIME_DEFAULT                 _MK_MASK_CONST(0xf)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_A_WR_TIME_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_A_WR_TIME_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_A_WR_TIME_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// start of the following access for MIO0. (The chip  select goes high at the end of a read access and goes low at the start of a  read or write access.)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_A_RD_DEAD_TIME_SHIFT                      _MK_SHIFT_CONST(4)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_A_RD_DEAD_TIME_FIELD                      (_MK_MASK_CONST(0x7) << APB_MISC_PP_XMB_MIO_CFG_0_MIO_A_RD_DEAD_TIME_SHIFT)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_A_RD_DEAD_TIME_RANGE                      6:4
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_A_RD_DEAD_TIME_WOFFSET                    0x0
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_A_RD_DEAD_TIME_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_A_RD_DEAD_TIME_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_A_RD_DEAD_TIME_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_A_RD_DEAD_TIME_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// MIO RDY Indicator. This signal indicates if the  MIO is ready. This also implies that the MIO is not busy with the present  request. The firmware can poll for this to get device status.
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_A_RD_TIME_SHIFT                   _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_A_RD_TIME_FIELD                   (_MK_MASK_CONST(0xf) << APB_MISC_PP_XMB_MIO_CFG_0_MIO_A_RD_TIME_SHIFT)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_A_RD_TIME_RANGE                   3:0
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_A_RD_TIME_WOFFSET                 0x0
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_A_RD_TIME_DEFAULT                 _MK_MASK_CONST(0xf)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_A_RD_TIME_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_A_RD_TIME_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_A_RD_TIME_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Reserved address 68 [0x44] 
+
+// Register APB_MISC_PP_USB_PHY_VCTL_REG_0  
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0                  _MK_ADDR_CONST(0x60)
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_WORD_COUNT                       0x1
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_RESET_VAL                        _MK_MASK_CONST(0x100020)
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_RESET_MASK                       _MK_MASK_CONST(0x10ff3f)
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_READ_MASK                        _MK_MASK_CONST(0x10ff3f)
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_WRITE_MASK                       _MK_MASK_CONST(0x10003f)
+// Unused
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_CLK12_SEL_SHIFT                  _MK_SHIFT_CONST(20)
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_CLK12_SEL_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VCTL_REG_0_CLK12_SEL_SHIFT)
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_CLK12_SEL_RANGE                  20:20
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_CLK12_SEL_WOFFSET                        0x0
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_CLK12_SEL_DEFAULT                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_CLK12_SEL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_CLK12_SEL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_CLK12_SEL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_CLK12_SEL_MHZ_24                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_CLK12_SEL_MHZ_12                 _MK_ENUM_CONST(1)
+
+// Vendor status from PHY. Read only
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_VSTATUS_SHIFT                    _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_VSTATUS_FIELD                    (_MK_MASK_CONST(0xff) << APB_MISC_PP_USB_PHY_VCTL_REG_0_VSTATUS_SHIFT)
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_VSTATUS_RANGE                    15:8
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_VSTATUS_WOFFSET                  0x0
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_VSTATUS_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_VSTATUS_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_VSTATUS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_VSTATUS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Default: 1
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_VLOAD_SHIFT                      _MK_SHIFT_CONST(5)
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_VLOAD_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VCTL_REG_0_VLOAD_SHIFT)
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_VLOAD_RANGE                      5:5
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_VLOAD_WOFFSET                    0x0
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_VLOAD_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_VLOAD_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_VLOAD_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_VLOAD_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_VLOAD_UNSET                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_VLOAD_SET                        _MK_ENUM_CONST(1)
+
+// Default: 0
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_VCONTROL_SHIFT                   _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_VCONTROL_FIELD                   (_MK_MASK_CONST(0x1f) << APB_MISC_PP_USB_PHY_VCTL_REG_0_VCONTROL_SHIFT)
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_VCONTROL_RANGE                   4:0
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_VCONTROL_WOFFSET                 0x0
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_VCONTROL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_VCONTROL_DEFAULT_MASK                    _MK_MASK_CONST(0x1f)
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_VCONTROL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_VCONTROL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_PP_USB_PHY_PARAM_0  
+#define APB_MISC_PP_USB_PHY_PARAM_0                     _MK_ADDR_CONST(0x64)
+#define APB_MISC_PP_USB_PHY_PARAM_0_WORD_COUNT                  0x1
+#define APB_MISC_PP_USB_PHY_PARAM_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_RESET_MASK                  _MK_MASK_CONST(0x3ff9)
+#define APB_MISC_PP_USB_PHY_PARAM_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_READ_MASK                   _MK_MASK_CONST(0x3ff9)
+#define APB_MISC_PP_USB_PHY_PARAM_0_WRITE_MASK                  _MK_MASK_CONST(0x3ff9)
+// Lower 32-bits select.
+// Not intended for software use.
+#define APB_MISC_PP_USB_PHY_PARAM_0_BUF_LOW32BITS_SEL_SHIFT                     _MK_SHIFT_CONST(13)
+#define APB_MISC_PP_USB_PHY_PARAM_0_BUF_LOW32BITS_SEL_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_PARAM_0_BUF_LOW32BITS_SEL_SHIFT)
+#define APB_MISC_PP_USB_PHY_PARAM_0_BUF_LOW32BITS_SEL_RANGE                     13:13
+#define APB_MISC_PP_USB_PHY_PARAM_0_BUF_LOW32BITS_SEL_WOFFSET                   0x0
+#define APB_MISC_PP_USB_PHY_PARAM_0_BUF_LOW32BITS_SEL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_BUF_LOW32BITS_SEL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_PARAM_0_BUF_LOW32BITS_SEL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_BUF_LOW32BITS_SEL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_BUF_LOW32BITS_SEL_UPPER_BITS                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_BUF_LOW32BITS_SEL_LOWER_BITS                        _MK_ENUM_CONST(1)
+
+// Enable reception of test packets
+// Not intended for software use.
+#define APB_MISC_PP_USB_PHY_PARAM_0_RCV_TEST_PKT_SHIFT                  _MK_SHIFT_CONST(12)
+#define APB_MISC_PP_USB_PHY_PARAM_0_RCV_TEST_PKT_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_PARAM_0_RCV_TEST_PKT_SHIFT)
+#define APB_MISC_PP_USB_PHY_PARAM_0_RCV_TEST_PKT_RANGE                  12:12
+#define APB_MISC_PP_USB_PHY_PARAM_0_RCV_TEST_PKT_WOFFSET                        0x0
+#define APB_MISC_PP_USB_PHY_PARAM_0_RCV_TEST_PKT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_RCV_TEST_PKT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_PARAM_0_RCV_TEST_PKT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_RCV_TEST_PKT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_RCV_TEST_PKT_DISABLE                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_RCV_TEST_PKT_ENABLE                 _MK_ENUM_CONST(1)
+
+// Enable transmission of test packets
+// Not intended for software use.
+#define APB_MISC_PP_USB_PHY_PARAM_0_SEND_TEST_PKT_SHIFT                 _MK_SHIFT_CONST(11)
+#define APB_MISC_PP_USB_PHY_PARAM_0_SEND_TEST_PKT_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_PARAM_0_SEND_TEST_PKT_SHIFT)
+#define APB_MISC_PP_USB_PHY_PARAM_0_SEND_TEST_PKT_RANGE                 11:11
+#define APB_MISC_PP_USB_PHY_PARAM_0_SEND_TEST_PKT_WOFFSET                       0x0
+#define APB_MISC_PP_USB_PHY_PARAM_0_SEND_TEST_PKT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_SEND_TEST_PKT_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_PARAM_0_SEND_TEST_PKT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_SEND_TEST_PKT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_SEND_TEST_PKT_DISABLE                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_SEND_TEST_PKT_ENABLE                        _MK_ENUM_CONST(1)
+
+// Enable TEST_J transmission
+// Not intended for software use.
+#define APB_MISC_PP_USB_PHY_PARAM_0_SEND_TEST_K_SHIFT                   _MK_SHIFT_CONST(10)
+#define APB_MISC_PP_USB_PHY_PARAM_0_SEND_TEST_K_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_PARAM_0_SEND_TEST_K_SHIFT)
+#define APB_MISC_PP_USB_PHY_PARAM_0_SEND_TEST_K_RANGE                   10:10
+#define APB_MISC_PP_USB_PHY_PARAM_0_SEND_TEST_K_WOFFSET                 0x0
+#define APB_MISC_PP_USB_PHY_PARAM_0_SEND_TEST_K_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_SEND_TEST_K_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_PARAM_0_SEND_TEST_K_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_SEND_TEST_K_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_SEND_TEST_K_DISABLE                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_SEND_TEST_K_ENABLE                  _MK_ENUM_CONST(1)
+
+// Enable TEST_K transmission
+// Not intended for software use.
+#define APB_MISC_PP_USB_PHY_PARAM_0_SEND_TEST_J_SHIFT                   _MK_SHIFT_CONST(9)
+#define APB_MISC_PP_USB_PHY_PARAM_0_SEND_TEST_J_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_PARAM_0_SEND_TEST_J_SHIFT)
+#define APB_MISC_PP_USB_PHY_PARAM_0_SEND_TEST_J_RANGE                   9:9
+#define APB_MISC_PP_USB_PHY_PARAM_0_SEND_TEST_J_WOFFSET                 0x0
+#define APB_MISC_PP_USB_PHY_PARAM_0_SEND_TEST_J_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_SEND_TEST_J_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_PARAM_0_SEND_TEST_J_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_SEND_TEST_J_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_SEND_TEST_J_DISABLE                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_SEND_TEST_J_ENABLE                  _MK_ENUM_CONST(1)
+
+// If enabled, send SOF with EOP of J, else
+// send SOF with EOP of K
+// Not intended for software use.
+#define APB_MISC_PP_USB_PHY_PARAM_0_TEST_SOF_J_SHIFT                    _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_USB_PHY_PARAM_0_TEST_SOF_J_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_PARAM_0_TEST_SOF_J_SHIFT)
+#define APB_MISC_PP_USB_PHY_PARAM_0_TEST_SOF_J_RANGE                    8:8
+#define APB_MISC_PP_USB_PHY_PARAM_0_TEST_SOF_J_WOFFSET                  0x0
+#define APB_MISC_PP_USB_PHY_PARAM_0_TEST_SOF_J_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_TEST_SOF_J_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_PARAM_0_TEST_SOF_J_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_TEST_SOF_J_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_TEST_SOF_J_DISABLE                  _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_TEST_SOF_J_ENABLE                   _MK_ENUM_CONST(1)
+
+// Unused
+// Not intended for software use.
+#define APB_MISC_PP_USB_PHY_PARAM_0_UTMI_DEBUG_SEL_SHIFT                        _MK_SHIFT_CONST(7)
+#define APB_MISC_PP_USB_PHY_PARAM_0_UTMI_DEBUG_SEL_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_PARAM_0_UTMI_DEBUG_SEL_SHIFT)
+#define APB_MISC_PP_USB_PHY_PARAM_0_UTMI_DEBUG_SEL_RANGE                        7:7
+#define APB_MISC_PP_USB_PHY_PARAM_0_UTMI_DEBUG_SEL_WOFFSET                      0x0
+#define APB_MISC_PP_USB_PHY_PARAM_0_UTMI_DEBUG_SEL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_UTMI_DEBUG_SEL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_PARAM_0_UTMI_DEBUG_SEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_UTMI_DEBUG_SEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_UTMI_DEBUG_SEL_DISABLE                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_UTMI_DEBUG_SEL_ENABLE                       _MK_ENUM_CONST(1)
+
+// Reserved
+#define APB_MISC_PP_USB_PHY_PARAM_0_RSVD6_SHIFT                 _MK_SHIFT_CONST(6)
+#define APB_MISC_PP_USB_PHY_PARAM_0_RSVD6_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_PARAM_0_RSVD6_SHIFT)
+#define APB_MISC_PP_USB_PHY_PARAM_0_RSVD6_RANGE                 6:6
+#define APB_MISC_PP_USB_PHY_PARAM_0_RSVD6_WOFFSET                       0x0
+#define APB_MISC_PP_USB_PHY_PARAM_0_RSVD6_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_RSVD6_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_PARAM_0_RSVD6_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_RSVD6_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Route USB buffers to AHB interface for debug
+// Not intended for software use.
+#define APB_MISC_PP_USB_PHY_PARAM_0_BUF_AHB_IF_SEL_SHIFT                        _MK_SHIFT_CONST(5)
+#define APB_MISC_PP_USB_PHY_PARAM_0_BUF_AHB_IF_SEL_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_PARAM_0_BUF_AHB_IF_SEL_SHIFT)
+#define APB_MISC_PP_USB_PHY_PARAM_0_BUF_AHB_IF_SEL_RANGE                        5:5
+#define APB_MISC_PP_USB_PHY_PARAM_0_BUF_AHB_IF_SEL_WOFFSET                      0x0
+#define APB_MISC_PP_USB_PHY_PARAM_0_BUF_AHB_IF_SEL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_BUF_AHB_IF_SEL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_PARAM_0_BUF_AHB_IF_SEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_BUF_AHB_IF_SEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_BUF_AHB_IF_SEL_DISABLE                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_BUF_AHB_IF_SEL_ENABLE                       _MK_ENUM_CONST(1)
+
+// Vbus_sense control
+// Controls which VBUS sensor input is driven to the controller.
+// 00: Use VBUS_WAKEUP.
+// 01: Use A_SESS_VLD output from the PHY if the PHY clock is available.
+// Otherwise, use VBUS_WAKEUP.
+// 10: Use A_SESS_VLD output from the PHY
+// 11: Use VBUS_WAKEUP.
+#define APB_MISC_PP_USB_PHY_PARAM_0_VS_CTL_SHIFT                        _MK_SHIFT_CONST(3)
+#define APB_MISC_PP_USB_PHY_PARAM_0_VS_CTL_FIELD                        (_MK_MASK_CONST(0x3) << APB_MISC_PP_USB_PHY_PARAM_0_VS_CTL_SHIFT)
+#define APB_MISC_PP_USB_PHY_PARAM_0_VS_CTL_RANGE                        4:3
+#define APB_MISC_PP_USB_PHY_PARAM_0_VS_CTL_WOFFSET                      0x0
+#define APB_MISC_PP_USB_PHY_PARAM_0_VS_CTL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_VS_CTL_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_USB_PHY_PARAM_0_VS_CTL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_VS_CTL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_VS_CTL_VBUS_WAKEUP                  _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_VS_CTL_A_SESS_VLD_OR_VBUS_WAKEUP                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_USB_PHY_PARAM_0_VS_CTL_A_SESS_VLD                   _MK_ENUM_CONST(2)
+#define APB_MISC_PP_USB_PHY_PARAM_0_VS_CTL_VBUS_WAKEUP_1                        _MK_ENUM_CONST(3)
+
+// FS/LS serial interface enable
+// If enabled, use FS/LS serial interface for USB transfers.
+// This mode does not support HS transfers.
+// If disabled, use UTMI interface for USB transfers.
+// This mode supports all transfer speeds - HS/FS/LS.
+#define APB_MISC_PP_USB_PHY_PARAM_0_FS_LS_SER_MODE_SHIFT                        _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_FS_LS_SER_MODE_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_PARAM_0_FS_LS_SER_MODE_SHIFT)
+#define APB_MISC_PP_USB_PHY_PARAM_0_FS_LS_SER_MODE_RANGE                        0:0
+#define APB_MISC_PP_USB_PHY_PARAM_0_FS_LS_SER_MODE_WOFFSET                      0x0
+#define APB_MISC_PP_USB_PHY_PARAM_0_FS_LS_SER_MODE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_FS_LS_SER_MODE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_PARAM_0_FS_LS_SER_MODE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_FS_LS_SER_MODE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_FS_LS_SER_MODE_DISABLE                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_FS_LS_SER_MODE_ENABLE                       _MK_ENUM_CONST(1)
+
+
+// Register APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0  
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0                   _MK_ADDR_CONST(0x68)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_WORD_COUNT                        0x1
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_RESET_MASK                        _MK_MASK_CONST(0x33f3f)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_READ_MASK                         _MK_MASK_CONST(0x33f3f)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+// RX compare fail. Comparison on RX data failed.
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_RXCMF_SHIFT                       _MK_SHIFT_CONST(17)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_RXCMF_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_RXCMF_SHIFT)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_RXCMF_RANGE                       17:17
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_RXCMF_WOFFSET                     0x0
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_RXCMF_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_RXCMF_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_RXCMF_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_RXCMF_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_RXCMF_UNSET                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_RXCMF_SET                 _MK_ENUM_CONST(1)
+
+// Rx valid/Rx validh fail: Indicates that the  Rxvalid/Rxvalidh werent generated according to protocol
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_RXVHF_SHIFT                       _MK_SHIFT_CONST(16)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_RXVHF_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_RXVHF_SHIFT)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_RXVHF_RANGE                       16:16
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_RXVHF_WOFFSET                     0x0
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_RXVHF_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_RXVHF_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_RXVHF_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_RXVHF_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_RXVHF_UNSET                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_RXVHF_SET                 _MK_ENUM_CONST(1)
+
+// Failed packet no: Points to the failed packet no
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_FAIL_PKT_NO_SHIFT                 _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_FAIL_PKT_NO_FIELD                 (_MK_MASK_CONST(0x3f) << APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_FAIL_PKT_NO_SHIFT)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_FAIL_PKT_NO_RANGE                 13:8
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_FAIL_PKT_NO_WOFFSET                       0x0
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_FAIL_PKT_NO_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_FAIL_PKT_NO_DEFAULT_MASK                  _MK_MASK_CONST(0x3f)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_FAIL_PKT_NO_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_FAIL_PKT_NO_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Failed RX byte index: Points to the Rx byte no. in  the current packet which fails
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_FAIL_RX_BYTE_SHIFT                        _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_FAIL_RX_BYTE_FIELD                        (_MK_MASK_CONST(0x3f) << APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_FAIL_RX_BYTE_SHIFT)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_FAIL_RX_BYTE_RANGE                        5:0
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_FAIL_RX_BYTE_WOFFSET                      0x0
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_FAIL_RX_BYTE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_FAIL_RX_BYTE_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_FAIL_RX_BYTE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_FAIL_RX_BYTE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_PP_USB_PHY_SELF_TEST_0  
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0                 _MK_ADDR_CONST(0x6c)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_WORD_COUNT                      0x1
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_RESET_VAL                       _MK_MASK_CONST(0x10150888)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_RESET_MASK                      _MK_MASK_CONST(0x3f3ffbff)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_READ_MASK                       _MK_MASK_CONST(0x3f3ffbff)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_WRITE_MASK                      _MK_MASK_CONST(0x3f3f7bf3)
+// Default: 0x10
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TEST_PKT_CNT_SHIFT                      _MK_SHIFT_CONST(24)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TEST_PKT_CNT_FIELD                      (_MK_MASK_CONST(0x3f) << APB_MISC_PP_USB_PHY_SELF_TEST_0_TEST_PKT_CNT_SHIFT)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TEST_PKT_CNT_RANGE                      29:24
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TEST_PKT_CNT_WOFFSET                    0x0
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TEST_PKT_CNT_DEFAULT                    _MK_MASK_CONST(0x10)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TEST_PKT_CNT_DEFAULT_MASK                       _MK_MASK_CONST(0x3f)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TEST_PKT_CNT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TEST_PKT_CNT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// default: 0x15
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_IPKT_DLY_SHIFT                  _MK_SHIFT_CONST(16)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_IPKT_DLY_FIELD                  (_MK_MASK_CONST(0x3f) << APB_MISC_PP_USB_PHY_SELF_TEST_0_IPKT_DLY_SHIFT)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_IPKT_DLY_RANGE                  21:16
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_IPKT_DLY_WOFFSET                        0x0
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_IPKT_DLY_DEFAULT                        _MK_MASK_CONST(0x15)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_IPKT_DLY_DEFAULT_MASK                   _MK_MASK_CONST(0x3f)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_IPKT_DLY_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_IPKT_DLY_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Status of Disconnect signal from PHY
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_DISCON_SHIFT                    _MK_SHIFT_CONST(15)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_DISCON_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_SELF_TEST_0_DISCON_SHIFT)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_DISCON_RANGE                    15:15
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_DISCON_WOFFSET                  0x0
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_DISCON_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_DISCON_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_DISCON_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_DISCON_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_DISCON_UNSET                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_DISCON_SET                      _MK_ENUM_CONST(1)
+
+// Default: 0
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_SOF_EN_SHIFT                    _MK_SHIFT_CONST(14)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_SOF_EN_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_SELF_TEST_0_SOF_EN_SHIFT)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_SOF_EN_RANGE                    14:14
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_SOF_EN_WOFFSET                  0x0
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_SOF_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_SOF_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_SOF_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_SOF_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_SOF_EN_DISABLE                  _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_SOF_EN_ENABLE                   _MK_ENUM_CONST(1)
+
+// Default: 0
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_DPPD_SHIFT                      _MK_SHIFT_CONST(13)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_DPPD_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_SELF_TEST_0_DPPD_SHIFT)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_DPPD_RANGE                      13:13
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_DPPD_WOFFSET                    0x0
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_DPPD_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_DPPD_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_DPPD_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_DPPD_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_DPPD_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_DPPD_ENABLE                     _MK_ENUM_CONST(1)
+
+// Default: 0
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_DMPD_SHIFT                      _MK_SHIFT_CONST(12)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_DMPD_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_SELF_TEST_0_DMPD_SHIFT)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_DMPD_RANGE                      12:12
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_DMPD_WOFFSET                    0x0
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_DMPD_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_DMPD_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_DMPD_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_DMPD_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_DMPD_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_DMPD_ENABLE                     _MK_ENUM_CONST(1)
+
+// Unused
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_DB16_8_SHIFT                    _MK_SHIFT_CONST(11)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_DB16_8_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_SELF_TEST_0_DB16_8_SHIFT)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_DB16_8_RANGE                    11:11
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_DB16_8_WOFFSET                  0x0
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_DB16_8_DEFAULT                  _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_DB16_8_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_DB16_8_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_DB16_8_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Operational Mode
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_OPMODE_SHIFT                    _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_OPMODE_FIELD                    (_MK_MASK_CONST(0x3) << APB_MISC_PP_USB_PHY_SELF_TEST_0_OPMODE_SHIFT)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_OPMODE_RANGE                    9:8
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_OPMODE_WOFFSET                  0x0
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_OPMODE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_OPMODE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_OPMODE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_OPMODE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Suspend: Default: 1
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_SUSP_SHIFT                      _MK_SHIFT_CONST(7)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_SUSP_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_SELF_TEST_0_SUSP_SHIFT)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_SUSP_RANGE                      7:7
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_SUSP_WOFFSET                    0x0
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_SUSP_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_SUSP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_SUSP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_SUSP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Term_select
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TERM_SHIFT                      _MK_SHIFT_CONST(6)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TERM_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_SELF_TEST_0_TERM_SHIFT)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TERM_RANGE                      6:6
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TERM_WOFFSET                    0x0
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TERM_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TERM_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TERM_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TERM_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// XCVR_select:
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_XCVR_SHIFT                      _MK_SHIFT_CONST(4)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_XCVR_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_USB_PHY_SELF_TEST_0_XCVR_SHIFT)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_XCVR_RANGE                      5:4
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_XCVR_WOFFSET                    0x0
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_XCVR_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_XCVR_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_XCVR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_XCVR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// When test is started, this status signal starts as  1 and is set to 0 if an error is detected. Can be sampled when TSTEND is  asserted.
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTPS_SHIFT                     _MK_SHIFT_CONST(3)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTPS_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTPS_SHIFT)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTPS_RANGE                     3:3
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTPS_WOFFSET                   0x0
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTPS_DEFAULT                   _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTPS_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTPS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTPS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTPS_UNSET                     _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTPS_SET                       _MK_ENUM_CONST(1)
+
+// Goes to 1 when the test finishes. At that time,  TSTPASS is valid and indicates the tests pass/fail status
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTEND_SHIFT                    _MK_SHIFT_CONST(2)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTEND_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTEND_SHIFT)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTEND_RANGE                    2:2
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTEND_WOFFSET                  0x0
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTEND_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTEND_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTEND_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTEND_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTEND_UNSET                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTEND_SET                      _MK_ENUM_CONST(1)
+
+// Sw writes a 1 to start the test. It writes a 0 to  end the test
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTON_SHIFT                     _MK_SHIFT_CONST(1)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTON_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTON_SHIFT)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTON_RANGE                     1:1
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTON_WOFFSET                   0x0
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTON_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTON_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTON_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTON_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTON_UNSET                     _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTON_SET                       _MK_ENUM_CONST(1)
+
+// Default: 0
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTENB_SHIFT                    _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTENB_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTENB_SHIFT)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTENB_RANGE                    0:0
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTENB_WOFFSET                  0x0
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTENB_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTENB_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTENB_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTENB_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTENB_DISABLE                  _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTENB_ENABLE                   _MK_ENUM_CONST(1)
+
+
+// Register APB_MISC_PP_USB_PHY_VBUS_SENSORS_0  
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0                      _MK_ADDR_CONST(0x70)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_WORD_COUNT                   0x1
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_RESET_MASK                   _MK_MASK_CONST(0x3f3f3f3f)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_READ_MASK                    _MK_MASK_CONST(0x3f3f3f3f)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_WRITE_MASK                   _MK_MASK_CONST(0x39393939)
+// A_VBUS_VLD debounce A/B select.
+// Selects between the two debounce values 
+// UTMIP_BIAS_DEBOUNCE_A or
+// UTMIP_BIAS_DEBOUNCE_B from the register
+// UTMIP_DEBOUNCE_CFG0.
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_DEB_SEL_B_SHIFT                   _MK_SHIFT_CONST(29)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_DEB_SEL_B_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_DEB_SEL_B_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_DEB_SEL_B_RANGE                   29:29
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_DEB_SEL_B_WOFFSET                 0x0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_DEB_SEL_B_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_DEB_SEL_B_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_DEB_SEL_B_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_DEB_SEL_B_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_DEB_SEL_B_SEL_A                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_DEB_SEL_B_SEL_B                   _MK_ENUM_CONST(1)
+
+// A_VBUS_VLD software value.
+// Software should write the appropriate
+// value (1/0) to set/unset the A_VBUS_VLD status.
+// This is only valid when A_VBUS_VLD_SW_EN is set.
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_VALUE_SHIFT                    _MK_SHIFT_CONST(28)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_VALUE_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_VALUE_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_VALUE_RANGE                    28:28
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_VALUE_WOFFSET                  0x0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_VALUE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_VALUE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_VALUE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_VALUE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_VALUE_UNSET                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_VALUE_SET                      _MK_ENUM_CONST(1)
+
+// A_VBUS_VLD software enable.
+// Enable Software Controlled A_VBUS_VLD.
+// Software sets this bit to drive the
+// value in A_VBUS_VLD_SW_VALUE to the USB
+// controller.
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_EN_SHIFT                       _MK_SHIFT_CONST(27)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_EN_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_EN_RANGE                       27:27
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_EN_WOFFSET                     0x0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// A_VBUS_VLD status.
+// This is set to 1 whenever A_VBUS_VLD sensor
+// output is 1.
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_STS_SHIFT                 _MK_SHIFT_CONST(26)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_STS_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_STS_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_STS_RANGE                 26:26
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_STS_WOFFSET                       0x0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_STS_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_STS_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_STS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_STS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_STS_UNSET                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_STS_SET                   _MK_ENUM_CONST(1)
+
+// A_VBUS_VLD change detect.
+// This field is set by hardware whenever a change
+// is detected in the value of A_VBUS_VLD.
+// software writes a 1 to clear it
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_CHG_DET_SHIFT                     _MK_SHIFT_CONST(25)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_CHG_DET_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_CHG_DET_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_CHG_DET_RANGE                     25:25
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_CHG_DET_WOFFSET                   0x0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_CHG_DET_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_CHG_DET_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_CHG_DET_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_CHG_DET_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_CHG_DET_UNSET                     _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_CHG_DET_SET                       _MK_ENUM_CONST(1)
+
+// A_VBUS_VLD interrupt enable.
+// If this field is set to 1, an interrupt is
+// generated whenever A_VBUS_VLD_CHG_DET is set to 1.
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_INT_EN_SHIFT                      _MK_SHIFT_CONST(24)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_INT_EN_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_INT_EN_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_INT_EN_RANGE                      24:24
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_INT_EN_WOFFSET                    0x0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_INT_EN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_INT_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_INT_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_INT_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_INT_EN_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_INT_EN_ENABLE                     _MK_ENUM_CONST(1)
+
+// A_SESS_VLD debounce A/B select.
+// Selects between the two debounce values 
+// UTMIP_BIAS_DEBOUNCE_A or
+// UTMIP_BIAS_DEBOUNCE_B from the register
+// UTMIP_DEBOUNCE_CFG0.
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_DEB_SEL_B_SHIFT                   _MK_SHIFT_CONST(21)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_DEB_SEL_B_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_DEB_SEL_B_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_DEB_SEL_B_RANGE                   21:21
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_DEB_SEL_B_WOFFSET                 0x0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_DEB_SEL_B_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_DEB_SEL_B_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_DEB_SEL_B_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_DEB_SEL_B_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_DEB_SEL_B_SEL_A                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_DEB_SEL_B_SEL_B                   _MK_ENUM_CONST(1)
+
+// A_SESS_VLD software value.
+// Software should write the appropriate
+// value (1/0) to set/unset the A_SESS_VLD status.
+// This is only valid when A_SESS_VLD_SW_EN is set.
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_VALUE_SHIFT                    _MK_SHIFT_CONST(20)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_VALUE_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_VALUE_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_VALUE_RANGE                    20:20
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_VALUE_WOFFSET                  0x0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_VALUE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_VALUE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_VALUE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_VALUE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_VALUE_UNSET                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_VALUE_SET                      _MK_ENUM_CONST(1)
+
+// A_SESS_VLD software enable.
+// Enable Software Controlled A_SESS_VLD.
+// Software sets this bit to drive the
+// value in A_SESS_VLD_SW_VALUE to the USB
+// controller.
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_EN_SHIFT                       _MK_SHIFT_CONST(19)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_EN_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_EN_RANGE                       19:19
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_EN_WOFFSET                     0x0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// A_SESS_VLD status.
+// This is set to 1 whenever A_SESS_VLD sensor
+// output is 1.
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_STS_SHIFT                 _MK_SHIFT_CONST(18)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_STS_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_STS_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_STS_RANGE                 18:18
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_STS_WOFFSET                       0x0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_STS_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_STS_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_STS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_STS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_STS_UNSET                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_STS_SET                   _MK_ENUM_CONST(1)
+
+// A_SESS_VLD change detect.
+// This field is set by hardware whenever a change
+// is detected in the value of A_SESS_VLD.
+// software writes a 1 to clear it
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_CHG_DET_SHIFT                     _MK_SHIFT_CONST(17)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_CHG_DET_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_CHG_DET_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_CHG_DET_RANGE                     17:17
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_CHG_DET_WOFFSET                   0x0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_CHG_DET_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_CHG_DET_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_CHG_DET_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_CHG_DET_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_CHG_DET_UNSET                     _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_CHG_DET_SET                       _MK_ENUM_CONST(1)
+
+// A_SESS_VLD interrupt enable.
+// If this field is set to 1, an interrupt is
+// generated whenever A_SESS_VLD_CHG_DET is set to 1.
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_INT_EN_SHIFT                      _MK_SHIFT_CONST(16)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_INT_EN_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_INT_EN_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_INT_EN_RANGE                      16:16
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_INT_EN_WOFFSET                    0x0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_INT_EN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_INT_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_INT_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_INT_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_INT_EN_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_INT_EN_ENABLE                     _MK_ENUM_CONST(1)
+
+// B_SESS_VLD debounce A/B select.
+// Selects between the two debounce values 
+// UTMIP_BIAS_DEBOUNCE_A or
+// UTMIP_BIAS_DEBOUNCE_B from the register
+// UTMIP_DEBOUNCE_CFG0.
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_DEB_SEL_B_SHIFT                   _MK_SHIFT_CONST(13)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_DEB_SEL_B_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_DEB_SEL_B_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_DEB_SEL_B_RANGE                   13:13
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_DEB_SEL_B_WOFFSET                 0x0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_DEB_SEL_B_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_DEB_SEL_B_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_DEB_SEL_B_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_DEB_SEL_B_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_DEB_SEL_B_SEL_A                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_DEB_SEL_B_SEL_B                   _MK_ENUM_CONST(1)
+
+// B_SESS_VLD software value.
+// Software should write the appropriate
+// value (1/0) to set/unset the B_SESS_VLD status.
+// This is only valid when B_SESS_VLD_SW_EN is set.
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_VALUE_SHIFT                    _MK_SHIFT_CONST(12)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_VALUE_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_VALUE_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_VALUE_RANGE                    12:12
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_VALUE_WOFFSET                  0x0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_VALUE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_VALUE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_VALUE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_VALUE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_VALUE_UNSET                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_VALUE_SET                      _MK_ENUM_CONST(1)
+
+// B_SESS_VLD software enable.
+// Enable Software Controlled B_SESS_VLD.
+// Software sets this bit to drive the
+// value in B_SESS_VLD_SW_VALUE to the USB
+// controller.
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_EN_SHIFT                       _MK_SHIFT_CONST(11)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_EN_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_EN_RANGE                       11:11
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_EN_WOFFSET                     0x0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// B_SESS_VLD status.
+// This is set to 1 whenever B_SESS_VLD sensor
+// output is 1.
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_STS_SHIFT                 _MK_SHIFT_CONST(10)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_STS_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_STS_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_STS_RANGE                 10:10
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_STS_WOFFSET                       0x0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_STS_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_STS_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_STS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_STS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_STS_UNSET                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_STS_SET                   _MK_ENUM_CONST(1)
+
+// B_SESS_VLD change detect.
+// This field is set by hardware whenever a change
+// is detected in the value of B_SESS_VLD.
+// software writes a 1 to clear it
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_CHG_DET_SHIFT                     _MK_SHIFT_CONST(9)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_CHG_DET_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_CHG_DET_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_CHG_DET_RANGE                     9:9
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_CHG_DET_WOFFSET                   0x0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_CHG_DET_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_CHG_DET_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_CHG_DET_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_CHG_DET_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_CHG_DET_UNSET                     _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_CHG_DET_SET                       _MK_ENUM_CONST(1)
+
+// B_SESS_VLD interrupt enable.
+// If this field is set to 1, an interrupt is
+// generated whenever B_SESS_VLD_CHG_DET is set to 1.
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_INT_EN_SHIFT                      _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_INT_EN_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_INT_EN_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_INT_EN_RANGE                      8:8
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_INT_EN_WOFFSET                    0x0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_INT_EN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_INT_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_INT_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_INT_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_INT_EN_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_INT_EN_ENABLE                     _MK_ENUM_CONST(1)
+
+// B_SESS_END debounce A/B select
+// Selects between the two debounce values 
+// UTMIP_BIAS_DEBOUNCE_A or
+// UTMIP_BIAS_DEBOUNCE_B from the register
+// UTMIP_DEBOUNCE_CFG0.
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_DEB_SEL_B_SHIFT                   _MK_SHIFT_CONST(5)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_DEB_SEL_B_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_DEB_SEL_B_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_DEB_SEL_B_RANGE                   5:5
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_DEB_SEL_B_WOFFSET                 0x0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_DEB_SEL_B_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_DEB_SEL_B_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_DEB_SEL_B_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_DEB_SEL_B_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_DEB_SEL_B_SEL_A                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_DEB_SEL_B_SEL_B                   _MK_ENUM_CONST(1)
+
+// B_SESS_END software value
+// Software should write the appropriate
+// value (1/0) to set/unset the B_SESS_END status.
+// This is only valid when B_SESS_END_SW_EN is set.
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_VALUE_SHIFT                    _MK_SHIFT_CONST(4)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_VALUE_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_VALUE_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_VALUE_RANGE                    4:4
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_VALUE_WOFFSET                  0x0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_VALUE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_VALUE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_VALUE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_VALUE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_VALUE_UNSET                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_VALUE_SET                      _MK_ENUM_CONST(1)
+
+// B_SESS_END software enable.
+// Enable Software Controlled B_SESS_END
+// Software sets this bit to drive the
+// value in B_SESS_END_SW_VALUE to the USB
+// controller.
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_EN_SHIFT                       _MK_SHIFT_CONST(3)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_EN_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_EN_RANGE                       3:3
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_EN_WOFFSET                     0x0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// B_SESS_END status.
+// This is set to 1 whenever B_SESS_END sensor
+// output is 1.
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_STS_SHIFT                 _MK_SHIFT_CONST(2)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_STS_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_STS_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_STS_RANGE                 2:2
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_STS_WOFFSET                       0x0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_STS_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_STS_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_STS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_STS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_STS_UNSET                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_STS_SET                   _MK_ENUM_CONST(1)
+
+// B_SESS_END change detect.
+// This field is set by hardware whenever a change
+// is detected in the value of B_SESS_END.
+// software writes a 1 to clear it
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_CHG_DET_SHIFT                     _MK_SHIFT_CONST(1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_CHG_DET_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_CHG_DET_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_CHG_DET_RANGE                     1:1
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_CHG_DET_WOFFSET                   0x0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_CHG_DET_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_CHG_DET_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_CHG_DET_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_CHG_DET_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_CHG_DET_UNSET                     _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_CHG_DET_SET                       _MK_ENUM_CONST(1)
+
+// B_SESS_END interrupt enable
+// If this field is set to 1, an interrupt is
+// generated whenever B_SESS_END_CHG_DET is set to 1.
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_INT_EN_SHIFT                      _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_INT_EN_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_INT_EN_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_INT_EN_RANGE                      0:0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_INT_EN_WOFFSET                    0x0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_INT_EN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_INT_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_INT_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_INT_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_INT_EN_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_INT_EN_ENABLE                     _MK_ENUM_CONST(1)
+
+
+// Register APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0  
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0                    _MK_ADDR_CONST(0x74)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_WORD_COUNT                         0x1
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_RESET_VAL                  _MK_MASK_CONST(0x6000000)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_RESET_MASK                         _MK_MASK_CONST(0x3f3f3f3f)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_READ_MASK                  _MK_MASK_CONST(0x3f3f3f3f)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_WRITE_MASK                         _MK_MASK_CONST(0x3f393939)
+// HS Tx to Tx inter-packet delay counter.
+// Software should not change this.
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_IP_DELAY_TX2TX_HS_SHIFT                    _MK_SHIFT_CONST(24)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_IP_DELAY_TX2TX_HS_FIELD                    (_MK_MASK_CONST(0x3f) << APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_IP_DELAY_TX2TX_HS_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_IP_DELAY_TX2TX_HS_RANGE                    29:24
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_IP_DELAY_TX2TX_HS_WOFFSET                  0x0
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_IP_DELAY_TX2TX_HS_DEFAULT                  _MK_MASK_CONST(0x6)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_IP_DELAY_TX2TX_HS_DEFAULT_MASK                     _MK_MASK_CONST(0x3f)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_IP_DELAY_TX2TX_HS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_IP_DELAY_TX2TX_HS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// VDAT_DET debounce A/B select.
+// Selects between the two debounce values 
+// UTMIP_BIAS_DEBOUNCE_A or
+// UTMIP_BIAS_DEBOUNCE_B from the register
+// UTMIP_DEBOUNCE_CFG0.
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_DEB_SEL_B_SHIFT                   _MK_SHIFT_CONST(21)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_DEB_SEL_B_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_DEB_SEL_B_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_DEB_SEL_B_RANGE                   21:21
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_DEB_SEL_B_WOFFSET                 0x0
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_DEB_SEL_B_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_DEB_SEL_B_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_DEB_SEL_B_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_DEB_SEL_B_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_DEB_SEL_B_SEL_A                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_DEB_SEL_B_SEL_B                   _MK_ENUM_CONST(1)
+
+// VDAT_DET software value.
+// Software should write the appropriate
+// value (1/0) to set/unset the VDAT_DET status.
+// This is only valid when VDAT_DET_SW_EN is set.
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_VALUE_SHIFT                    _MK_SHIFT_CONST(20)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_VALUE_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_VALUE_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_VALUE_RANGE                    20:20
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_VALUE_WOFFSET                  0x0
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_VALUE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_VALUE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_VALUE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_VALUE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_VALUE_UNSET                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_VALUE_SET                      _MK_ENUM_CONST(1)
+
+// VDAT_DET software enable.
+// Enable Software Controlled VDAT_DET.
+// Software sets this bit to drive the
+// value in VDAT_DET_SW_VALUE to the USB
+// controller
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_EN_SHIFT                       _MK_SHIFT_CONST(19)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_EN_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_EN_RANGE                       19:19
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_EN_WOFFSET                     0x0
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// VDAT_DET status.
+// This is set to 1 whenever VDAT_DET sensor
+// output is 1.
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_STS_SHIFT                 _MK_SHIFT_CONST(18)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_STS_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_STS_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_STS_RANGE                 18:18
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_STS_WOFFSET                       0x0
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_STS_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_STS_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_STS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_STS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_STS_UNSET                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_STS_SET                   _MK_ENUM_CONST(1)
+
+// VDAT_DET change detect.
+// This field is set by hardware whenever a change
+// is detected in the value of VDAT_DET.
+// software writes a 1 to clear it
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_CHG_DET_SHIFT                     _MK_SHIFT_CONST(17)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_CHG_DET_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_CHG_DET_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_CHG_DET_RANGE                     17:17
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_CHG_DET_WOFFSET                   0x0
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_CHG_DET_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_CHG_DET_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_CHG_DET_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_CHG_DET_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_CHG_DET_UNSET                     _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_CHG_DET_SET                       _MK_ENUM_CONST(1)
+
+// VDAT_DET interrupt enable.
+// If this field is set to 1, an interrupt is
+// generated whenever VDAT_DET_CHG_DET is set to 1.
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_INT_EN_SHIFT                      _MK_SHIFT_CONST(16)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_INT_EN_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_INT_EN_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_INT_EN_RANGE                      16:16
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_INT_EN_WOFFSET                    0x0
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_INT_EN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_INT_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_INT_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_INT_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_INT_EN_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_INT_EN_ENABLE                     _MK_ENUM_CONST(1)
+
+// VBUS_WAKEUP debounce A/B select.
+// Selects between the two debounce values 
+// UTMIP_BIAS_DEBOUNCE_A or
+// UTMIP_BIAS_DEBOUNCE_B from the register
+// UTMIP_DEBOUNCE_CFG0.
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_DEB_SEL_B_SHIFT                        _MK_SHIFT_CONST(13)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_DEB_SEL_B_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_DEB_SEL_B_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_DEB_SEL_B_RANGE                        13:13
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_DEB_SEL_B_WOFFSET                      0x0
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_DEB_SEL_B_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_DEB_SEL_B_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_DEB_SEL_B_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_DEB_SEL_B_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_DEB_SEL_B_SEL_A                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_DEB_SEL_B_SEL_B                        _MK_ENUM_CONST(1)
+
+// VBUS_WAKEUP software value.
+// Software should write the appropriate
+// value (1/0) to set/unset the VBUS_WAKEUP status.
+// This is only valid when VBUS_WAKEUP_SW_EN is set.
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_VALUE_SHIFT                 _MK_SHIFT_CONST(12)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_VALUE_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_VALUE_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_VALUE_RANGE                 12:12
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_VALUE_WOFFSET                       0x0
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_VALUE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_VALUE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_VALUE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_VALUE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_VALUE_UNSET                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_VALUE_SET                   _MK_ENUM_CONST(1)
+
+// VBUS_WAKEUP software enable.
+// Enable Software Controlled VBUS_WAKEUP.
+// Software sets this bit to drive the
+// value in VBUS_WAKEUP_SW_VALUE to the USB
+// controller.
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_EN_SHIFT                    _MK_SHIFT_CONST(11)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_EN_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_EN_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_EN_RANGE                    11:11
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_EN_WOFFSET                  0x0
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_EN_DISABLE                  _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_EN_ENABLE                   _MK_ENUM_CONST(1)
+
+// VBUS_WAKEUP status.
+// This is set to 1 whenever VBUS_WAKEUP sensor
+// output is 1.
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_STS_SHIFT                      _MK_SHIFT_CONST(10)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_STS_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_STS_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_STS_RANGE                      10:10
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_STS_WOFFSET                    0x0
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_STS_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_STS_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_STS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_STS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_STS_UNSET                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_STS_SET                        _MK_ENUM_CONST(1)
+
+// VBUS_WAKEUP change detect.
+// This field is set by hardware whenever a change
+// is detected in the value of VBUS_WAKEUP.
+// software writes a 1 to clear it
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_CHG_DET_SHIFT                  _MK_SHIFT_CONST(9)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_CHG_DET_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_CHG_DET_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_CHG_DET_RANGE                  9:9
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_CHG_DET_WOFFSET                        0x0
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_CHG_DET_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_CHG_DET_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_CHG_DET_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_CHG_DET_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_CHG_DET_UNSET                  _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_CHG_DET_SET                    _MK_ENUM_CONST(1)
+
+// VBUS_WAKEUP interrupt enable
+// If this field is set to 1, an interrupt is
+// generated whenever VBUS_WAKEUP_CHG_DET is set to 1.
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_INT_EN_SHIFT                   _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_INT_EN_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_INT_EN_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_INT_EN_RANGE                   8:8
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_INT_EN_WOFFSET                 0x0
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_INT_EN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_INT_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_INT_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_INT_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_INT_EN_DISABLE                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_INT_EN_ENABLE                  _MK_ENUM_CONST(1)
+
+// ID debounce A/B select.
+// Selects between the two debounce values 
+// UTMIP_BIAS_DEBOUNCE_A or
+// UTMIP_BIAS_DEBOUNCE_B from the register
+// UTMIP_DEBOUNCE_CFG0.
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_DEB_SEL_B_SHIFT                 _MK_SHIFT_CONST(5)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_DEB_SEL_B_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_DEB_SEL_B_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_DEB_SEL_B_RANGE                 5:5
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_DEB_SEL_B_WOFFSET                       0x0
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_DEB_SEL_B_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_DEB_SEL_B_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_DEB_SEL_B_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_DEB_SEL_B_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_DEB_SEL_B_SEL_A                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_DEB_SEL_B_SEL_B                 _MK_ENUM_CONST(1)
+
+// ID software value.
+// Software should write the appropriate
+// value (1/0) to set/unset the ID status.
+// This is only valid when ID_SW_EN is set.
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_VALUE_SHIFT                  _MK_SHIFT_CONST(4)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_VALUE_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_VALUE_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_VALUE_RANGE                  4:4
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_VALUE_WOFFSET                        0x0
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_VALUE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_VALUE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_VALUE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_VALUE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_VALUE_UNSET                  _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_VALUE_SET                    _MK_ENUM_CONST(1)
+
+// ID software enable.
+// Enable Software Controlled ID.
+// Software sets this bit to drive the
+// value in ID_SW_VALUE to the USB
+// controller
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_EN_SHIFT                     _MK_SHIFT_CONST(3)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_EN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_EN_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_EN_RANGE                     3:3
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_EN_WOFFSET                   0x0
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// ID status.
+// This is set to 1 whenever ID sensor
+// output is 1.
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_STS_SHIFT                       _MK_SHIFT_CONST(2)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_STS_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_STS_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_STS_RANGE                       2:2
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_STS_WOFFSET                     0x0
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_STS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_STS_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_STS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_STS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_STS_UNSET                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_STS_SET                 _MK_ENUM_CONST(1)
+
+// ID change detect.
+// This field is set by hardware whenever a change
+// is detected in the value of ID.
+// software writes a 1 to clear it
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_CHG_DET_SHIFT                   _MK_SHIFT_CONST(1)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_CHG_DET_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_CHG_DET_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_CHG_DET_RANGE                   1:1
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_CHG_DET_WOFFSET                 0x0
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_CHG_DET_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_CHG_DET_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_CHG_DET_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_CHG_DET_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_CHG_DET_UNSET                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_CHG_DET_SET                     _MK_ENUM_CONST(1)
+
+// ID interrupt enable.
+// If this field is set to 1, an interrupt is
+// generated whenever ID_CHG_DET is set to 1.
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_INT_EN_SHIFT                    _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_INT_EN_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_INT_EN_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_INT_EN_RANGE                    0:0
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_INT_EN_WOFFSET                  0x0
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_INT_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_INT_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_INT_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_INT_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_INT_EN_DISABLE                  _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_INT_EN_ENABLE                   _MK_ENUM_CONST(1)
+
+
+// Register APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0  
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0                      _MK_ADDR_CONST(0x78)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_WORD_COUNT                   0x1
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_WRITE_MASK                   _MK_MASK_CONST(0xffffff80)
+// Reserved
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_RSVD31_7_SHIFT                       _MK_SHIFT_CONST(7)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_RSVD31_7_FIELD                       (_MK_MASK_CONST(0x1ffffff) << APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_RSVD31_7_SHIFT)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_RSVD31_7_RANGE                       31:7
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_RSVD31_7_WOFFSET                     0x0
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_RSVD31_7_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_RSVD31_7_DEFAULT_MASK                        _MK_MASK_CONST(0x1ffffff)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_RSVD31_7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_RSVD31_7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_RSVD31_7_UNSET                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_RSVD31_7_SET                 _MK_ENUM_CONST(1)
+
+// Avalid alternate status
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_AVALID_ALT_SHIFT                     _MK_SHIFT_CONST(6)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_AVALID_ALT_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_AVALID_ALT_SHIFT)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_AVALID_ALT_RANGE                     6:6
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_AVALID_ALT_WOFFSET                   0x0
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_AVALID_ALT_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_AVALID_ALT_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_AVALID_ALT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_AVALID_ALT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_AVALID_ALT_UNSET                     _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_AVALID_ALT_SET                       _MK_ENUM_CONST(1)
+
+// Bvalid alternate status
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_BVALID_ALT_SHIFT                     _MK_SHIFT_CONST(5)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_BVALID_ALT_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_BVALID_ALT_SHIFT)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_BVALID_ALT_RANGE                     5:5
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_BVALID_ALT_WOFFSET                   0x0
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_BVALID_ALT_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_BVALID_ALT_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_BVALID_ALT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_BVALID_ALT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_BVALID_ALT_UNSET                     _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_BVALID_ALT_SET                       _MK_ENUM_CONST(1)
+
+// ID alternate status
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_ID_DIG_ALT_SHIFT                     _MK_SHIFT_CONST(4)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_ID_DIG_ALT_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_ID_DIG_ALT_SHIFT)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_ID_DIG_ALT_RANGE                     4:4
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_ID_DIG_ALT_WOFFSET                   0x0
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_ID_DIG_ALT_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_ID_DIG_ALT_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_ID_DIG_ALT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_ID_DIG_ALT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_ID_DIG_ALT_UNSET                     _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_ID_DIG_ALT_SET                       _MK_ENUM_CONST(1)
+
+// Session end alternate status
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_SESS_END_ALT_SHIFT                   _MK_SHIFT_CONST(3)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_SESS_END_ALT_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_SESS_END_ALT_SHIFT)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_SESS_END_ALT_RANGE                   3:3
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_SESS_END_ALT_WOFFSET                 0x0
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_SESS_END_ALT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_SESS_END_ALT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_SESS_END_ALT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_SESS_END_ALT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_SESS_END_ALT_UNSET                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_SESS_END_ALT_SET                     _MK_ENUM_CONST(1)
+
+// Static GPI alternate status
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_STATIC_GPI_ALT_SHIFT                 _MK_SHIFT_CONST(2)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_STATIC_GPI_ALT_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_STATIC_GPI_ALT_SHIFT)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_STATIC_GPI_ALT_RANGE                 2:2
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_STATIC_GPI_ALT_WOFFSET                       0x0
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_STATIC_GPI_ALT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_STATIC_GPI_ALT_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_STATIC_GPI_ALT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_STATIC_GPI_ALT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_STATIC_GPI_ALT_UNSET                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_STATIC_GPI_ALT_SET                   _MK_ENUM_CONST(1)
+
+// VBus valid alternate status
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_VBUS_VALID_ALT_SHIFT                 _MK_SHIFT_CONST(1)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_VBUS_VALID_ALT_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_VBUS_VALID_ALT_SHIFT)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_VBUS_VALID_ALT_RANGE                 1:1
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_VBUS_VALID_ALT_WOFFSET                       0x0
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_VBUS_VALID_ALT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_VBUS_VALID_ALT_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_VBUS_VALID_ALT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_VBUS_VALID_ALT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_VBUS_VALID_ALT_UNSET                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_VBUS_VALID_ALT_SET                   _MK_ENUM_CONST(1)
+
+// Vbus wakeup alternate status
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_VBUS_WAKEUP_ALT_SHIFT                        _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_VBUS_WAKEUP_ALT_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_VBUS_WAKEUP_ALT_SHIFT)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_VBUS_WAKEUP_ALT_RANGE                        0:0
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_VBUS_WAKEUP_ALT_WOFFSET                      0x0
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_VBUS_WAKEUP_ALT_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_VBUS_WAKEUP_ALT_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_VBUS_WAKEUP_ALT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_VBUS_WAKEUP_ALT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_VBUS_WAKEUP_ALT_UNSET                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_VBUS_WAKEUP_ALT_SET                  _MK_ENUM_CONST(1)
+
+
+// Register APB_MISC_PP_MISC_SAVE_THE_DAY_0  
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0                 _MK_ADDR_CONST(0x7c)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_WORD_COUNT                      0x1
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Reserved
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_A_SHIFT                    _MK_SHIFT_CONST(24)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_A_FIELD                    (_MK_MASK_CONST(0xff) << APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_A_SHIFT)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_A_RANGE                    31:24
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_A_WOFFSET                  0x0
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_A_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_A_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_A_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_A_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Reserved
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_B_SHIFT                    _MK_SHIFT_CONST(16)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_B_FIELD                    (_MK_MASK_CONST(0xff) << APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_B_SHIFT)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_B_RANGE                    23:16
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_B_WOFFSET                  0x0
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_B_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_B_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_B_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_B_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Reserved
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_C_SHIFT                    _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_C_FIELD                    (_MK_MASK_CONST(0xff) << APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_C_SHIFT)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_C_RANGE                    15:8
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_C_WOFFSET                  0x0
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_C_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_C_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_C_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_C_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Reserved
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_D_SHIFT                    _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_D_FIELD                    (_MK_MASK_CONST(0xff) << APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_D_SHIFT)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_D_RANGE                    7:0
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_D_WOFFSET                  0x0
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_D_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_D_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_D_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_D_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_PP_PIN_MUX_CTL_A_0  
+#define APB_MISC_PP_PIN_MUX_CTL_A_0                     _MK_ADDR_CONST(0x80)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_WORD_COUNT                  0x1
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RSVD_1_SHIFT                        _MK_SHIFT_CONST(30)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RSVD_1_FIELD                        (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_A_0_RSVD_1_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RSVD_1_RANGE                        31:30
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RSVD_1_WOFFSET                      0x0
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RSVD_1_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RSVD_1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RSVD_1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RSVD_1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCE_SEL_SHIFT                      _MK_SHIFT_CONST(28)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCE_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_A_0_KBCE_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCE_SEL_RANGE                      29:28
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCE_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCE_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCE_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCE_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCE_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCE_SEL_KBC                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCE_SEL_RSVD1                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCE_SEL_SDIO1                      _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCE_SEL_RSVD2                      _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCF_SEL_SHIFT                      _MK_SHIFT_CONST(26)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCF_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_A_0_KBCF_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCF_SEL_RANGE                      27:26
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCF_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCF_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCF_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCF_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCF_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCF_SEL_KBC                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCF_SEL_RSVD1                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCF_SEL_RSVD2                      _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCF_SEL_MIO                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATA_SEL_SHIFT                       _MK_SHIFT_CONST(24)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATA_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_A_0_ATA_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATA_SEL_RANGE                       25:24
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATA_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATA_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATA_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATA_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATA_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATA_SEL_IDE                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATA_SEL_NAND                        _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATA_SEL_RSVD                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATA_SEL_NAND_ALT                    _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATC_SEL_SHIFT                       _MK_SHIFT_CONST(22)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATC_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_A_0_ATC_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATC_SEL_RANGE                       23:22
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATC_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATC_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATC_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATC_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATC_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATC_SEL_IDE                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATC_SEL_NAND                        _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATC_SEL_XIO                 _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATC_SEL_RSVD                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATD_SEL_SHIFT                       _MK_SHIFT_CONST(20)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATD_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_A_0_ATD_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATD_SEL_RANGE                       21:20
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATD_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATD_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATD_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATD_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATD_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATD_SEL_IDE                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATD_SEL_NAND                        _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATD_SEL_NAND_ALT                    _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATD_SEL_HSMMC                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RSVD_2_SHIFT                        _MK_SHIFT_CONST(18)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RSVD_2_FIELD                        (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_A_0_RSVD_2_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RSVD_2_RANGE                        19:18
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RSVD_2_WOFFSET                      0x0
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RSVD_2_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RSVD_2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RSVD_2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RSVD_2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATB_SEL_SHIFT                       _MK_SHIFT_CONST(16)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATB_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_A_0_ATB_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATB_SEL_RANGE                       17:16
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATB_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATB_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATB_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATB_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATB_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATB_SEL_IDE                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATB_SEL_NAND                        _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATB_SEL_NAND_ALT                    _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATB_SEL_HSMMC                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RM_SEL_SHIFT                        _MK_SHIFT_CONST(14)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RM_SEL_FIELD                        (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_A_0_RM_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RM_SEL_RANGE                        15:14
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RM_SEL_WOFFSET                      0x0
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RM_SEL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RM_SEL_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RM_SEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RM_SEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RM_SEL_I2C                  _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RM_SEL_RSVD1                        _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RM_SEL_RSVD2                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RM_SEL_RSVD3                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATE_SEL_SHIFT                       _MK_SHIFT_CONST(12)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATE_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_A_0_ATE_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATE_SEL_RANGE                       13:12
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATE_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATE_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATE_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATE_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATE_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATE_SEL_IDE                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATE_SEL_NAND                        _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATE_SEL_NAND_ALT                    _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATE_SEL_HSMMC                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RSVD_3_SHIFT                        _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RSVD_3_FIELD                        (_MK_MASK_CONST(0xf) << APB_MISC_PP_PIN_MUX_CTL_A_0_RSVD_3_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RSVD_3_RANGE                        11:8
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RSVD_3_WOFFSET                      0x0
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RSVD_3_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RSVD_3_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RSVD_3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RSVD_3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAD_SEL_SHIFT                       _MK_SHIFT_CONST(6)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAD_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_A_0_UAD_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAD_SEL_RANGE                       7:6
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAD_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAD_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAD_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAD_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAD_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAD_SEL_IRDA                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAD_SEL_SPDIF                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAD_SEL_UARTA                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAD_SEL_SFLASH                      _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAC_SEL_SHIFT                       _MK_SHIFT_CONST(4)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAC_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_A_0_UAC_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAC_SEL_RANGE                       5:4
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAC_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAC_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAC_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAC_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAC_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAC_SEL_RSVD1                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAC_SEL_RSVD2                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAC_SEL_RSVD3                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAC_SEL_ULPI                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAB_SEL_SHIFT                       _MK_SHIFT_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAB_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_A_0_UAB_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAB_SEL_RANGE                       3:2
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAB_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAB_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAB_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAB_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAB_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAB_SEL_SPI2                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAB_SEL_MIPI_HS                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAB_SEL_UARTA                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAB_SEL_ULPI                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAA_SEL_SHIFT                       _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAA_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_A_0_UAA_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAA_SEL_RANGE                       1:0
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAA_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAA_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAA_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAA_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAA_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAA_SEL_SPI3                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAA_SEL_MIPI_HS                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAA_SEL_UARTA                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAA_SEL_ULPI                        _MK_ENUM_CONST(3)
+
+
+// Register APB_MISC_PP_PIN_MUX_CTL_B_0  
+#define APB_MISC_PP_PIN_MUX_CTL_B_0                     _MK_ADDR_CONST(0x84)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_WORD_COUNT                  0x1
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_RESET_MASK                  _MK_MASK_CONST(0xfcffffff)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_READ_MASK                   _MK_MASK_CONST(0xfcffffff)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_WRITE_MASK                  _MK_MASK_CONST(0xfcffffff)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTE_SEL_SHIFT                       _MK_SHIFT_CONST(30)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTE_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_B_0_DTE_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTE_SEL_RANGE                       31:30
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTE_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTE_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTE_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTE_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTE_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTE_SEL_RSVD1                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTE_SEL_RSVD2                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTE_SEL_VI                  _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTE_SEL_SPI1                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTD_SEL_SHIFT                       _MK_SHIFT_CONST(28)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTD_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_B_0_DTD_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTD_SEL_RANGE                       29:28
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTD_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTD_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTD_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTD_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTD_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTD_SEL_RSVD1                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTD_SEL_SDIO1                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTD_SEL_VI                  _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTD_SEL_RSVD4                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTC_SEL_SHIFT                       _MK_SHIFT_CONST(26)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTC_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_B_0_DTC_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTC_SEL_RANGE                       27:26
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTC_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTC_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTC_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTC_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTC_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTC_SEL_RSVD1                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTC_SEL_RSVD2                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTC_SEL_VI                  _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTC_SEL_RSVD4                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTB_SEL_SHIFT                       _MK_SHIFT_CONST(22)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTB_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_B_0_DTB_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTB_SEL_RANGE                       23:22
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTB_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTB_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTB_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTB_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTB_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTB_SEL_RSVD1                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTB_SEL_RSVD2                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTB_SEL_VI                  _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTB_SEL_SPI1                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTA_SEL_SHIFT                       _MK_SHIFT_CONST(20)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTA_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_B_0_DTA_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTA_SEL_RANGE                       21:20
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTA_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTA_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTA_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTA_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTA_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTA_SEL_RSVD1                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTA_SEL_SDIO1                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTA_SEL_VI                  _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTA_SEL_RSVD4                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCB_SEL_SHIFT                       _MK_SHIFT_CONST(18)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCB_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_B_0_UCB_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCB_SEL_RANGE                       19:18
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCB_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCB_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCB_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCB_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCB_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCB_SEL_PWM0                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCB_SEL_RSVD2                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCB_SEL_RSVD3                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCB_SEL_UARTC                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCA_SEL_SHIFT                       _MK_SHIFT_CONST(16)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCA_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_B_0_UCA_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCA_SEL_RANGE                       17:16
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCA_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCA_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCA_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCA_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCA_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCA_SEL_UARTC                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCA_SEL_RSVD1                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCA_SEL_RSVD2                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCA_SEL_RSVD3                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXK_SEL_SHIFT                      _MK_SHIFT_CONST(14)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXK_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_B_0_SLXK_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXK_SEL_RANGE                      15:14
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXK_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXK_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXK_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXK_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXK_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXK_SEL_SDIO1                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXK_SEL_SLINK4B                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXK_SEL_SDIO2                      _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXK_SEL_SPI2                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXD_SEL_SHIFT                      _MK_SHIFT_CONST(12)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXD_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_B_0_SLXD_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXD_SEL_RANGE                      13:12
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXD_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXD_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXD_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXD_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXD_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXD_SEL_SDIO1                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXD_SEL_SLINK4B                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXD_SEL_SPDIF                      _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXD_SEL_SPI2                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXC_SEL_SHIFT                      _MK_SHIFT_CONST(10)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXC_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_B_0_SLXC_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXC_SEL_RANGE                      11:10
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXC_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXC_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXC_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXC_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXC_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXC_SEL_SDIO1                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXC_SEL_SLINK4B                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXC_SEL_SPDIF                      _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXC_SEL_SPI2                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXB_SEL_SHIFT                      _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXB_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_B_0_SLXB_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXB_SEL_RANGE                      9:8
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXB_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXB_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXB_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXB_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXB_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXB_SEL_SDIO1                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXB_SEL_SLINK4B                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXB_SEL_SDIO2                      _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXB_SEL_SPI2                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXA_SEL_SHIFT                      _MK_SHIFT_CONST(6)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXA_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_B_0_SLXA_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXA_SEL_RANGE                      7:6
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXA_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXA_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXA_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXA_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXA_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXA_SEL_SDIO1                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXA_SEL_SLINK4B                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXA_SEL_SDIO2                      _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXA_SEL_SPI2                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_HDINT_SEL_SHIFT                     _MK_SHIFT_CONST(4)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_HDINT_SEL_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_B_0_HDINT_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_HDINT_SEL_RANGE                     5:4
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_HDINT_SEL_WOFFSET                   0x0
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_HDINT_SEL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_HDINT_SEL_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_HDINT_SEL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_HDINT_SEL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_HDINT_SEL_RSVD1                     _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_HDINT_SEL_DISPLAYA_HSYNC                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_HDINT_SEL_DISPLAYB_HSYNC                    _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_HDINT_SEL_RSVD2                     _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_RSVD_4_SHIFT                        _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_RSVD_4_FIELD                        (_MK_MASK_CONST(0xf) << APB_MISC_PP_PIN_MUX_CTL_B_0_RSVD_4_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_RSVD_4_RANGE                        3:0
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_RSVD_4_WOFFSET                      0x0
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_RSVD_4_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_RSVD_4_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_RSVD_4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_RSVD_4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_PP_PIN_MUX_CTL_C_0  
+#define APB_MISC_PP_PIN_MUX_CTL_C_0                     _MK_ADDR_CONST(0x88)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_WORD_COUNT                  0x1
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_XM2S_SEL_SHIFT                      _MK_SHIFT_CONST(30)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_XM2S_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_C_0_XM2S_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_XM2S_SEL_RANGE                      31:30
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_XM2S_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_XM2S_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_XM2S_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_XM2S_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_XM2S_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_XM2S_SEL_DRAM                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_XM2S_SEL_RSVD2                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_XM2S_SEL_SPI                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_XM2S_SEL_SPROM                      _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_XM2A_SEL_SHIFT                      _MK_SHIFT_CONST(28)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_XM2A_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_C_0_XM2A_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_XM2A_SEL_RANGE                      29:28
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_XM2A_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_XM2A_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_XM2A_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_XM2A_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_XM2A_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_XM2A_SEL_DRAM                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_XM2A_SEL_SPI3                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_XM2A_SEL_SPI                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_XM2A_SEL_SPROM                      _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP4_SEL_SHIFT                      _MK_SHIFT_CONST(26)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP4_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_C_0_DAP4_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP4_SEL_RANGE                      27:26
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP4_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP4_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP4_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP4_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP4_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP4_SEL_DAP4                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP4_SEL_RSVD2                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP4_SEL_RSVD3                      _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP4_SEL_RSVD4                      _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP3_SEL_SHIFT                      _MK_SHIFT_CONST(24)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP3_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_C_0_DAP3_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP3_SEL_RANGE                      25:24
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP3_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP3_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP3_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP3_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP3_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP3_SEL_DAP3                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP3_SEL_RSVD2                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP3_SEL_RSVD3                      _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP3_SEL_RSVD4                      _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP2_SEL_SHIFT                      _MK_SHIFT_CONST(22)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP2_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_C_0_DAP2_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP2_SEL_RANGE                      23:22
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP2_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP2_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP2_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP2_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP2_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP2_SEL_DAP2                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP2_SEL_TWC                        _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP2_SEL_RSVD3                      _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP2_SEL_RSVD4                      _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP1_SEL_SHIFT                      _MK_SHIFT_CONST(20)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP1_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_C_0_DAP1_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP1_SEL_RANGE                      21:20
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP1_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP1_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP1_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP1_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP1_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP1_SEL_DAP1                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP1_SEL_RSVD2                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP1_SEL_RSVD3                      _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP1_SEL_SDIO1                      _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRRX_SEL_SHIFT                      _MK_SHIFT_CONST(18)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRRX_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_C_0_IRRX_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRRX_SEL_RANGE                      19:18
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRRX_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRRX_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRRX_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRRX_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRRX_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRRX_SEL_UARTA                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRRX_SEL_RSVD2                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRRX_SEL_RSVD3                      _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRRX_SEL_UARTB                      _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRTX_SEL_SHIFT                      _MK_SHIFT_CONST(16)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRTX_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_C_0_IRTX_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRTX_SEL_RANGE                      17:16
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRTX_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRTX_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRTX_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRTX_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRTX_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRTX_SEL_UARTA                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRTX_SEL_RSVD2                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRTX_SEL_RSVD3                      _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRTX_SEL_UARTB                      _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCC_SEL_SHIFT                      _MK_SHIFT_CONST(14)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCC_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_C_0_KBCC_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCC_SEL_RANGE                      15:14
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCC_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCC_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCC_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCC_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCC_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCC_SEL_KBC                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCC_SEL_RSVD2                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCC_SEL_RSVD3                      _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCC_SEL_RSVD4                      _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCB_SEL_SHIFT                      _MK_SHIFT_CONST(12)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCB_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_C_0_KBCB_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCB_SEL_RANGE                      13:12
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCB_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCB_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCB_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCB_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCB_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCB_SEL_KBC                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCB_SEL_RSVD2                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCB_SEL_SDIO1                      _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCB_SEL_MIO                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCA_SEL_SHIFT                      _MK_SHIFT_CONST(10)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCA_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_C_0_KBCA_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCA_SEL_RANGE                      11:10
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCA_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCA_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCA_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCA_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCA_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCA_SEL_KBC                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCA_SEL_RSVD2                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCA_SEL_RSVD3                      _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCA_SEL_RSVD4                      _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_I2CP_SEL_SHIFT                      _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_I2CP_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_C_0_I2CP_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_I2CP_SEL_RANGE                      9:8
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_I2CP_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_I2CP_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_I2CP_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_I2CP_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_I2CP_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_I2CP_SEL_I2C                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_I2CP_SEL_RSVD2                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_I2CP_SEL_RSVD3                      _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_I2CP_SEL_RSVD4                      _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CSUS_SEL_SHIFT                      _MK_SHIFT_CONST(6)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CSUS_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_C_0_CSUS_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CSUS_SEL_RANGE                      7:6
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CSUS_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CSUS_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CSUS_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CSUS_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CSUS_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CSUS_SEL_PLLC_OUT1                  _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CSUS_SEL_PLLP_OUT2                  _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CSUS_SEL_PLLP_OUT3                  _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CSUS_SEL_VI_SENSOR_CLK                      _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV2_SEL_SHIFT                     _MK_SHIFT_CONST(4)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV2_SEL_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV2_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV2_SEL_RANGE                     5:4
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV2_SEL_WOFFSET                   0x0
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV2_SEL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV2_SEL_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV2_SEL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV2_SEL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV2_SEL_OSC                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV2_SEL_AHB_CLK                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV2_SEL_APB_CLK                   _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV2_SEL_PLLP_OUT4                 _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV1_SEL_SHIFT                     _MK_SHIFT_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV1_SEL_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV1_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV1_SEL_RANGE                     3:2
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV1_SEL_WOFFSET                   0x0
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV1_SEL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV1_SEL_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV1_SEL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV1_SEL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV1_SEL_OSC                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV1_SEL_PLLA_OUT                  _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV1_SEL_PLLM_OUT1                 _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV1_SEL_AUDIO_SYNC                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CSYS_SEL_SHIFT                      _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CSYS_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_C_0_CSYS_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CSYS_SEL_RANGE                      1:0
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CSYS_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CSYS_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CSYS_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CSYS_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CSYS_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CSYS_SEL_RSVD1                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CSYS_SEL_RSVD2                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CSYS_SEL_RSVD3                      _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CSYS_SEL_RSVD4                      _MK_ENUM_CONST(3)
+
+
+// Register APB_MISC_PP_PIN_MUX_CTL_D_0  
+#define APB_MISC_PP_PIN_MUX_CTL_D_0                     _MK_ADDR_CONST(0x8c)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_WORD_COUNT                  0x1
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIA_SEL_SHIFT                      _MK_SHIFT_CONST(30)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIA_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_D_0_SPIA_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIA_SEL_RANGE                      31:30
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIA_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIA_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIA_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIA_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIA_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIA_SEL_SPI1                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIA_SEL_SPI2                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIA_SEL_SPI3                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIA_SEL_RSVD                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIB_SEL_SHIFT                      _MK_SHIFT_CONST(28)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIB_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_D_0_SPIB_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIB_SEL_RANGE                      29:28
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIB_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIB_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIB_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIB_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIB_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIB_SEL_SPI1                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIB_SEL_SPI2                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIB_SEL_SPI3                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIB_SEL_RSVD                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIC_SEL_SHIFT                      _MK_SHIFT_CONST(26)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIC_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_D_0_SPIC_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIC_SEL_RANGE                      27:26
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIC_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIC_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIC_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIC_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIC_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIC_SEL_SPI1                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIC_SEL_SPI2                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIC_SEL_SPI3                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIC_SEL_RSVD                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPID_SEL_SHIFT                      _MK_SHIFT_CONST(24)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPID_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_D_0_SPID_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPID_SEL_RANGE                      25:24
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPID_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPID_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPID_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPID_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPID_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPID_SEL_SPI2                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPID_SEL_SPI1                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPID_SEL_SPI2_ALT                   _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPID_SEL_RSVD                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIE_SEL_SHIFT                      _MK_SHIFT_CONST(22)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIE_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_D_0_SPIE_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIE_SEL_RANGE                      23:22
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIE_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIE_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIE_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIE_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIE_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIE_SEL_SPI2                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIE_SEL_SPI1                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIE_SEL_SPI2_ALT                   _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIE_SEL_RSVD                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIF_SEL_SHIFT                      _MK_SHIFT_CONST(20)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIF_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_D_0_SPIF_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIF_SEL_RANGE                      21:20
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIF_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIF_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIF_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIF_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIF_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIF_SEL_SPI3                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIF_SEL_SPI1                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIF_SEL_SPI2                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIF_SEL_RSVD                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIG_SEL_SHIFT                      _MK_SHIFT_CONST(18)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIG_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_D_0_SPIG_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIG_SEL_RANGE                      19:18
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIG_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIG_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIG_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIG_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIG_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIG_SEL_SPI3                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIG_SEL_SPI2                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIG_SEL_SPI2_ALT                   _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIG_SEL_I2C                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIH_SEL_SHIFT                      _MK_SHIFT_CONST(16)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIH_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_D_0_SPIH_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIH_SEL_RANGE                      17:16
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIH_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIH_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIH_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIH_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIH_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIH_SEL_SPI3                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIH_SEL_SPI2                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIH_SEL_SPI2_ALT                   _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIH_SEL_I2C                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDD_SEL_SHIFT                       _MK_SHIFT_CONST(14)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDD_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_D_0_SDD_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDD_SEL_RANGE                       15:14
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDD_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDD_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDD_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDD_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDD_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDD_SEL_UARTA                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDD_SEL_PWM                 _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDD_SEL_SDIO2                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDD_SEL_SPI3                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDC_SEL_SHIFT                       _MK_SHIFT_CONST(12)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDC_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_D_0_SDC_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDC_SEL_RANGE                       13:12
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDC_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDC_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDC_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDC_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDC_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDC_SEL_PWM                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDC_SEL_TWC                 _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDC_SEL_SDIO2                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDC_SEL_SPI3                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDB_SEL_SHIFT                       _MK_SHIFT_CONST(10)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDB_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_D_0_SDB_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDB_SEL_RANGE                       11:10
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDB_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDB_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDB_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDB_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDB_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDB_SEL_SDIO2                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDB_SEL_RSVD                        _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDB_SEL_SDIO2_ALT                   _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDB_SEL_RSVD4                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDI_SEL_SHIFT                      _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDI_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_D_0_SPDI_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDI_SEL_RANGE                      9:8
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDI_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDI_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDI_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDI_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDI_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDI_SEL_SPDIF                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDI_SEL_RSVD                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDI_SEL_I2C                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDI_SEL_SDIO1                      _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDO_SEL_SHIFT                      _MK_SHIFT_CONST(6)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDO_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_D_0_SPDO_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDO_SEL_RANGE                      7:6
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDO_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDO_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDO_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDO_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDO_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDO_SEL_SPDIF                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDO_SEL_RSVD                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDO_SEL_I2C                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDO_SEL_SDIO1                      _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPU_SEL_SHIFT                       _MK_SHIFT_CONST(4)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPU_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_D_0_GPU_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPU_SEL_RANGE                       5:4
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPU_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPU_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPU_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPU_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPU_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPU_SEL_RSVD                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPU_SEL_UARTA                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPU_SEL_RSVD3                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPU_SEL_RSVD4                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPV_SEL_SHIFT                       _MK_SHIFT_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPV_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_D_0_GPV_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPV_SEL_RANGE                       3:2
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPV_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPV_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPV_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPV_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPV_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPV_SEL_GPIO_PORT_V                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPV_SEL_RSVD2                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPV_SEL_RSVD3                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPV_SEL_RSVD4                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_DBG_SEL_SHIFT                       _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_DBG_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_D_0_DBG_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_DBG_SEL_RANGE                       1:0
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_DBG_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_DBG_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_DBG_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_DBG_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_DBG_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_DBG_SEL_JTAG                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_DBG_SEL_RSVD2                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_DBG_SEL_RSVD3                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_DBG_SEL_RSVD4                       _MK_ENUM_CONST(3)
+
+
+// Register APB_MISC_PP_PIN_MUX_CTL_E_0  
+#define APB_MISC_PP_PIN_MUX_CTL_E_0                     _MK_ADDR_CONST(0x90)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_WORD_COUNT                  0x1
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVP0_SEL_SHIFT                      _MK_SHIFT_CONST(30)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVP0_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_E_0_LVP0_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVP0_SEL_RANGE                      31:30
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVP0_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVP0_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVP0_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVP0_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVP0_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVP0_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVP0_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVP0_SEL_I2C2                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVP0_SEL_RSVD                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM1_SEL_SHIFT                       _MK_SHIFT_CONST(28)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM1_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_E_0_LM1_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM1_SEL_RANGE                       29:28
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM1_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM1_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM1_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM1_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM1_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM1_SEL_DISPLAYA                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM1_SEL_DISPLAYB                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM1_SEL_I2C2                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM1_SEL_CRT                 _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM0_SEL_SHIFT                       _MK_SHIFT_CONST(26)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM0_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_E_0_LM0_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM0_SEL_RANGE                       27:26
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM0_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM0_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM0_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM0_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM0_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM0_SEL_DISPLAYA                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM0_SEL_DISPLAYB                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM0_SEL_SPI3                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM0_SEL_RSVD                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVS_SEL_SHIFT                       _MK_SHIFT_CONST(24)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVS_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_E_0_LVS_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVS_SEL_RANGE                       25:24
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVS_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVS_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVS_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVS_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVS_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVS_SEL_DISPLAYA                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVS_SEL_DISPLAYB                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVS_SEL_XIO                 _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVS_SEL_CRT                 _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LHS_SEL_SHIFT                       _MK_SHIFT_CONST(22)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LHS_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_E_0_LHS_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LHS_SEL_RANGE                       23:22
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LHS_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LHS_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LHS_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LHS_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LHS_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LHS_SEL_DISPLAYA                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LHS_SEL_DISPLAYB                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LHS_SEL_XIO                 _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LHS_SEL_CRT                 _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC1_SEL_SHIFT                      _MK_SHIFT_CONST(20)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC1_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_E_0_LSC1_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC1_SEL_RANGE                      21:20
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC1_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC1_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC1_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC1_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC1_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC1_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC1_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC1_SEL_SPI3                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC1_SEL_HDMI                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC0_SEL_SHIFT                      _MK_SHIFT_CONST(18)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC0_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_E_0_LSC0_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC0_SEL_RANGE                      19:18
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC0_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC0_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC0_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC0_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC0_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC0_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC0_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC0_SEL_XIO                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC0_SEL_RSVD                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSCK_SEL_SHIFT                      _MK_SHIFT_CONST(16)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSCK_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_E_0_LSCK_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSCK_SEL_RANGE                      17:16
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSCK_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSCK_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSCK_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSCK_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSCK_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSCK_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSCK_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSCK_SEL_SPI3                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSCK_SEL_HDMI                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LDC_SEL_SHIFT                       _MK_SHIFT_CONST(14)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LDC_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_E_0_LDC_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LDC_SEL_RANGE                       15:14
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LDC_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LDC_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LDC_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LDC_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LDC_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LDC_SEL_DISPLAYA                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LDC_SEL_DISPLAYB                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LDC_SEL_RSVD                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LDC_SEL_RSVD4                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LCSN_SEL_SHIFT                      _MK_SHIFT_CONST(12)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LCSN_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_E_0_LCSN_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LCSN_SEL_RANGE                      13:12
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LCSN_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LCSN_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LCSN_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LCSN_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LCSN_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LCSN_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LCSN_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LCSN_SEL_SPI3                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LCSN_SEL_CRT                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSPI_SEL_SHIFT                      _MK_SHIFT_CONST(10)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSPI_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_E_0_LSPI_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSPI_SEL_RANGE                      11:10
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSPI_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSPI_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSPI_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSPI_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSPI_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSPI_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSPI_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSPI_SEL_XIO                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSPI_SEL_RSVD                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDA_SEL_SHIFT                      _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDA_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_E_0_LSDA_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDA_SEL_RANGE                      9:8
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDA_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDA_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDA_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDA_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDA_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDA_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDA_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDA_SEL_SPI3                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDA_SEL_HDMI                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDI_SEL_SHIFT                      _MK_SHIFT_CONST(6)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDI_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_E_0_LSDI_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDI_SEL_RANGE                      7:6
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDI_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDI_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDI_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDI_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDI_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDI_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDI_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDI_SEL_SPI3                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDI_SEL_RSVD                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW2_SEL_SHIFT                      _MK_SHIFT_CONST(4)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW2_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_E_0_LPW2_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW2_SEL_RANGE                      5:4
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW2_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW2_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW2_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW2_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW2_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW2_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW2_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW2_SEL_SPI3                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW2_SEL_HDMI                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW1_SEL_SHIFT                      _MK_SHIFT_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW1_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_E_0_LPW1_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW1_SEL_RANGE                      3:2
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW1_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW1_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW1_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW1_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW1_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW1_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW1_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW1_SEL_RSVD                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW1_SEL_CRT                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW0_SEL_SHIFT                      _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW0_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_E_0_LPW0_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW0_SEL_RANGE                      1:0
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW0_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW0_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW0_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW0_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW0_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW0_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW0_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW0_SEL_SPI3                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW0_SEL_HDMI                       _MK_ENUM_CONST(3)
+
+
+// Register APB_MISC_PP_PIN_MUX_CTL_F_0  
+#define APB_MISC_PP_PIN_MUX_CTL_F_0                     _MK_ADDR_CONST(0x94)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_WORD_COUNT                  0x1
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD15_SEL_SHIFT                      _MK_SHIFT_CONST(30)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD15_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_F_0_LD15_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD15_SEL_RANGE                      31:30
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD15_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD15_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD15_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD15_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD15_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD15_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD15_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD15_SEL_XIO                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD15_SEL_RSVD                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD14_SEL_SHIFT                      _MK_SHIFT_CONST(28)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD14_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_F_0_LD14_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD14_SEL_RANGE                      29:28
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD14_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD14_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD14_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD14_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD14_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD14_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD14_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD14_SEL_XIO                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD14_SEL_RSVD                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD13_SEL_SHIFT                      _MK_SHIFT_CONST(26)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD13_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_F_0_LD13_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD13_SEL_RANGE                      27:26
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD13_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD13_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD13_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD13_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD13_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD13_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD13_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD13_SEL_XIO                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD13_SEL_RSVD                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD12_SEL_SHIFT                      _MK_SHIFT_CONST(24)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD12_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_F_0_LD12_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD12_SEL_RANGE                      25:24
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD12_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD12_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD12_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD12_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD12_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD12_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD12_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD12_SEL_XIO                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD12_SEL_RSVD                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD11_SEL_SHIFT                      _MK_SHIFT_CONST(22)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD11_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_F_0_LD11_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD11_SEL_RANGE                      23:22
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD11_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD11_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD11_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD11_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD11_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD11_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD11_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD11_SEL_XIO                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD11_SEL_RSVD                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD10_SEL_SHIFT                      _MK_SHIFT_CONST(20)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD10_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_F_0_LD10_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD10_SEL_RANGE                      21:20
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD10_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD10_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD10_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD10_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD10_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD10_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD10_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD10_SEL_XIO                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD10_SEL_RSVD                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD9_SEL_SHIFT                       _MK_SHIFT_CONST(18)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD9_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_F_0_LD9_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD9_SEL_RANGE                       19:18
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD9_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD9_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD9_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD9_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD9_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD9_SEL_DISPLAYA                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD9_SEL_DISPLAYB                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD9_SEL_XIO                 _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD9_SEL_RSVD                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD8_SEL_SHIFT                       _MK_SHIFT_CONST(16)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD8_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_F_0_LD8_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD8_SEL_RANGE                       17:16
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD8_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD8_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD8_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD8_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD8_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD8_SEL_DISPLAYA                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD8_SEL_DISPLAYB                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD8_SEL_XIO                 _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD8_SEL_RSVD                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD7_SEL_SHIFT                       _MK_SHIFT_CONST(14)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD7_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_F_0_LD7_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD7_SEL_RANGE                       15:14
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD7_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD7_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD7_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD7_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD7_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD7_SEL_DISPLAYA                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD7_SEL_DISPLAYB                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD7_SEL_XIO                 _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD7_SEL_RSVD                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD6_SEL_SHIFT                       _MK_SHIFT_CONST(12)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD6_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_F_0_LD6_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD6_SEL_RANGE                       13:12
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD6_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD6_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD6_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD6_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD6_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD6_SEL_DISPLAYA                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD6_SEL_DISPLAYB                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD6_SEL_XIO                 _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD6_SEL_RSVD                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD5_SEL_SHIFT                       _MK_SHIFT_CONST(10)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD5_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_F_0_LD5_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD5_SEL_RANGE                       11:10
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD5_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD5_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD5_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD5_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD5_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD5_SEL_DISPLAYA                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD5_SEL_DISPLAYB                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD5_SEL_XIO                 _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD5_SEL_RSVD                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD4_SEL_SHIFT                       _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD4_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_F_0_LD4_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD4_SEL_RANGE                       9:8
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD4_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD4_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD4_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD4_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD4_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD4_SEL_DISPLAYA                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD4_SEL_DISPLAYB                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD4_SEL_XIO                 _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD4_SEL_RSVD                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD3_SEL_SHIFT                       _MK_SHIFT_CONST(6)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD3_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_F_0_LD3_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD3_SEL_RANGE                       7:6
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD3_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD3_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD3_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD3_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD3_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD3_SEL_DISPLAYA                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD3_SEL_DISPLAYB                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD3_SEL_XIO                 _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD3_SEL_RSVD                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD2_SEL_SHIFT                       _MK_SHIFT_CONST(4)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD2_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_F_0_LD2_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD2_SEL_RANGE                       5:4
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD2_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD2_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD2_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD2_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD2_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD2_SEL_DISPLAYA                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD2_SEL_DISPLAYB                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD2_SEL_XIO                 _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD2_SEL_RSVD                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD1_SEL_SHIFT                       _MK_SHIFT_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD1_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_F_0_LD1_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD1_SEL_RANGE                       3:2
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD1_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD1_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD1_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD1_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD1_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD1_SEL_DISPLAYA                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD1_SEL_DISPLAYB                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD1_SEL_XIO                 _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD1_SEL_RSVD                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD0_SEL_SHIFT                       _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD0_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_F_0_LD0_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD0_SEL_RANGE                       1:0
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD0_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD0_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD0_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD0_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD0_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD0_SEL_DISPLAYA                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD0_SEL_DISPLAYB                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD0_SEL_XIO                 _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD0_SEL_RSVD                        _MK_ENUM_CONST(3)
+
+
+// Register APB_MISC_PP_PIN_MUX_CTL_G_0  
+#define APB_MISC_PP_PIN_MUX_CTL_G_0                     _MK_ADDR_CONST(0x98)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_WORD_COUNT                  0x1
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_RESET_MASK                  _MK_MASK_CONST(0xfcffcfff)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_READ_MASK                   _MK_MASK_CONST(0xfcffcfff)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_WRITE_MASK                  _MK_MASK_CONST(0xfcffcfff)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_DTF_SEL_SHIFT                       _MK_SHIFT_CONST(30)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_DTF_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_G_0_DTF_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_DTF_SEL_RANGE                       31:30
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_DTF_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_DTF_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_DTF_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_DTF_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_DTF_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_DTF_SEL_RSVD1                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_DTF_SEL_RSVD2                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_DTF_SEL_VI                  _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_DTF_SEL_I2C2                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_GPU7_SEL_SHIFT                      _MK_SHIFT_CONST(28)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_GPU7_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_G_0_GPU7_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_GPU7_SEL_RANGE                      29:28
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_GPU7_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_GPU7_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_GPU7_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_GPU7_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_GPU7_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_GPU7_SEL_RTCK                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_GPU7_SEL_RSVD1                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_GPU7_SEL_RSVD2                      _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_GPU7_SEL_RSVD3                      _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_KBCD_SEL_SHIFT                      _MK_SHIFT_CONST(26)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_KBCD_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_G_0_KBCD_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_KBCD_SEL_RANGE                      27:26
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_KBCD_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_KBCD_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_KBCD_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_KBCD_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_KBCD_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_KBCD_SEL_KBC                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_KBCD_SEL_RSVD2                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_KBCD_SEL_SDIO1                      _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_KBCD_SEL_MIO                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_PTA_SEL_SHIFT                       _MK_SHIFT_CONST(22)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_PTA_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_G_0_PTA_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_PTA_SEL_RANGE                       23:22
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_PTA_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_PTA_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_PTA_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_PTA_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_PTA_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_PTA_SEL_I2C2                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_PTA_SEL_HDMI                        _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_PTA_SEL_RSVD1                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_PTA_SEL_RSVD2                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_RSVD_5_SHIFT                        _MK_SHIFT_CONST(20)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_RSVD_5_FIELD                        (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_G_0_RSVD_5_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_RSVD_5_RANGE                        21:20
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_RSVD_5_WOFFSET                      0x0
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_RSVD_5_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_RSVD_5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_RSVD_5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_RSVD_5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_PMC_SEL_SHIFT                       _MK_SHIFT_CONST(18)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_PMC_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_G_0_PMC_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_PMC_SEL_RANGE                       19:18
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_PMC_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_PMC_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_PMC_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_PMC_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_PMC_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_PMC_SEL_PWR_ON                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_PMC_SEL_PWR_INTR                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LDI_SEL_SHIFT                       _MK_SHIFT_CONST(16)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LDI_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_G_0_LDI_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LDI_SEL_RANGE                       17:16
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LDI_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LDI_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LDI_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LDI_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LDI_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LDI_SEL_DISPLAYA                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LDI_SEL_DISPLAYB                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LDI_SEL_SPI1                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LDI_SEL_RSVD                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LPP_SEL_SHIFT                       _MK_SHIFT_CONST(14)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LPP_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_G_0_LPP_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LPP_SEL_RANGE                       15:14
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LPP_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LPP_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LPP_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LPP_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LPP_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LPP_SEL_DISPLAYA                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LPP_SEL_DISPLAYB                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LPP_SEL_SPI1                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LPP_SEL_RSVD                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP0_SEL_SHIFT                      _MK_SHIFT_CONST(10)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP0_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_G_0_LHP0_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP0_SEL_RANGE                      11:10
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP0_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP0_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP0_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP0_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP0_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP0_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP0_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP0_SEL_SPI1                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP0_SEL_I2C2                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LVP1_SEL_SHIFT                      _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LVP1_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_G_0_LVP1_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LVP1_SEL_RANGE                      9:8
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LVP1_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LVP1_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LVP1_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LVP1_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LVP1_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LVP1_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LVP1_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LVP1_SEL_SPI1                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LVP1_SEL_I2C2                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP2_SEL_SHIFT                      _MK_SHIFT_CONST(6)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP2_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_G_0_LHP2_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP2_SEL_RANGE                      7:6
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP2_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP2_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP2_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP2_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP2_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP2_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP2_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP2_SEL_SPI1                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP2_SEL_CRT                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP1_SEL_SHIFT                      _MK_SHIFT_CONST(4)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP1_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_G_0_LHP1_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP1_SEL_RANGE                      5:4
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP1_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP1_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP1_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP1_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP1_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP1_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP1_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP1_SEL_SPI1                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP1_SEL_RSVD                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD17_SEL_SHIFT                      _MK_SHIFT_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD17_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_G_0_LD17_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD17_SEL_RANGE                      3:2
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD17_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD17_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD17_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD17_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD17_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD17_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD17_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD17_SEL_RSVD                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD17_SEL_RSVD_ALT                   _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD16_SEL_SHIFT                      _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD16_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_G_0_LD16_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD16_SEL_RANGE                      1:0
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD16_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD16_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD16_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD16_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD16_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD16_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD16_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD16_SEL_XIO                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD16_SEL_RSVD                       _MK_ENUM_CONST(3)
+
+
+// Register APB_MISC_PP_PIN_MUX_CTL_H_0  
+#define APB_MISC_PP_PIN_MUX_CTL_H_0                     _MK_ADDR_CONST(0x9c)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_WORD_COUNT                  0x1
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_RSVD_6_SHIFT                        _MK_SHIFT_CONST(22)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_RSVD_6_FIELD                        (_MK_MASK_CONST(0x3ff) << APB_MISC_PP_PIN_MUX_CTL_H_0_RSVD_6_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_RSVD_6_RANGE                        31:22
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_RSVD_6_WOFFSET                      0x0
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_RSVD_6_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_RSVD_6_DEFAULT_MASK                 _MK_MASK_CONST(0x3ff)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_RSVD_6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_RSVD_6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4M_SEL_SHIFT                     _MK_SHIFT_CONST(21)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4M_SEL_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4M_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4M_SEL_RANGE                     21:21
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4M_SEL_WOFFSET                   0x0
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4M_SEL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4M_SEL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4M_SEL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4M_SEL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4M_SEL_DAP4_SLAVE                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4M_SEL_DAP4_MASTER                       _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3M_SEL_SHIFT                     _MK_SHIFT_CONST(20)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3M_SEL_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3M_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3M_SEL_RANGE                     20:20
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3M_SEL_WOFFSET                   0x0
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3M_SEL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3M_SEL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3M_SEL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3M_SEL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3M_SEL_DAP3_SLAVE                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3M_SEL_DAP3_MASTER                       _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2M_SEL_SHIFT                     _MK_SHIFT_CONST(19)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2M_SEL_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2M_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2M_SEL_RANGE                     19:19
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2M_SEL_WOFFSET                   0x0
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2M_SEL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2M_SEL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2M_SEL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2M_SEL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2M_SEL_DAP2_SLAVE                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2M_SEL_DAP2_MASTER                       _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1M_SEL_SHIFT                     _MK_SHIFT_CONST(18)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1M_SEL_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1M_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1M_SEL_RANGE                     18:18
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1M_SEL_WOFFSET                   0x0
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1M_SEL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1M_SEL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1M_SEL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1M_SEL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1M_SEL_DAP1_SLAVE                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1M_SEL_DAP1_MASTER                       _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC3_SEL_SHIFT                      _MK_SHIFT_CONST(16)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC3_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_H_0_DAC3_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC3_SEL_RANGE                      17:16
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC3_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC3_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC3_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC3_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC3_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC3_SEL_DAP1                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC3_SEL_DAP2                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC3_SEL_DAP3                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC3_SEL_DAP4                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC2_SEL_SHIFT                      _MK_SHIFT_CONST(14)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC2_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_H_0_DAC2_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC2_SEL_RANGE                      15:14
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC2_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC2_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC2_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC2_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC2_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC2_SEL_DAP1                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC2_SEL_DAP2                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC2_SEL_DAP3                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC2_SEL_DAP4                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC1_SEL_SHIFT                      _MK_SHIFT_CONST(12)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC1_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_H_0_DAC1_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC1_SEL_RANGE                      13:12
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC1_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC1_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC1_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC1_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC1_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC1_SEL_DAP1                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC1_SEL_DAP2                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC1_SEL_DAP3                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC1_SEL_DAP4                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4_CNTRL_MUX_SELECT_SHIFT                 _MK_SHIFT_CONST(9)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4_CNTRL_MUX_SELECT_FIELD                 (_MK_MASK_CONST(0x7) << APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4_CNTRL_MUX_SELECT_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4_CNTRL_MUX_SELECT_RANGE                 11:9
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4_CNTRL_MUX_SELECT_WOFFSET                       0x0
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4_CNTRL_MUX_SELECT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4_CNTRL_MUX_SELECT_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4_CNTRL_MUX_SELECT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4_CNTRL_MUX_SELECT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4_CNTRL_MUX_SELECT_DAC1                  _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4_CNTRL_MUX_SELECT_DAC2                  _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4_CNTRL_MUX_SELECT_DAC3                  _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4_CNTRL_MUX_SELECT_RSVD                  _MK_ENUM_CONST(3)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4_CNTRL_MUX_SELECT_DAP1                  _MK_ENUM_CONST(4)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4_CNTRL_MUX_SELECT_DAP2                  _MK_ENUM_CONST(5)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4_CNTRL_MUX_SELECT_DAP3                  _MK_ENUM_CONST(6)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4_CNTRL_MUX_SELECT_RSVD2                 _MK_ENUM_CONST(7)
+
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3_CNTRL_MUX_SELECT_SHIFT                 _MK_SHIFT_CONST(6)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3_CNTRL_MUX_SELECT_FIELD                 (_MK_MASK_CONST(0x7) << APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3_CNTRL_MUX_SELECT_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3_CNTRL_MUX_SELECT_RANGE                 8:6
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3_CNTRL_MUX_SELECT_WOFFSET                       0x0
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3_CNTRL_MUX_SELECT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3_CNTRL_MUX_SELECT_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3_CNTRL_MUX_SELECT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3_CNTRL_MUX_SELECT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3_CNTRL_MUX_SELECT_DAC1                  _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3_CNTRL_MUX_SELECT_DAC2                  _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3_CNTRL_MUX_SELECT_DAC3                  _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3_CNTRL_MUX_SELECT_RSVD1                 _MK_ENUM_CONST(3)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3_CNTRL_MUX_SELECT_DAP1                  _MK_ENUM_CONST(4)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3_CNTRL_MUX_SELECT_DAP2                  _MK_ENUM_CONST(5)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3_CNTRL_MUX_SELECT_RSVD2                 _MK_ENUM_CONST(6)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3_CNTRL_MUX_SELECT_DAP4                  _MK_ENUM_CONST(7)
+
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2_CNTRL_MUX_SELECT_SHIFT                 _MK_SHIFT_CONST(3)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2_CNTRL_MUX_SELECT_FIELD                 (_MK_MASK_CONST(0x7) << APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2_CNTRL_MUX_SELECT_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2_CNTRL_MUX_SELECT_RANGE                 5:3
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2_CNTRL_MUX_SELECT_WOFFSET                       0x0
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2_CNTRL_MUX_SELECT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2_CNTRL_MUX_SELECT_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2_CNTRL_MUX_SELECT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2_CNTRL_MUX_SELECT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2_CNTRL_MUX_SELECT_DAC1                  _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2_CNTRL_MUX_SELECT_DAC2                  _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2_CNTRL_MUX_SELECT_DAC3                  _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2_CNTRL_MUX_SELECT_RSVD1                 _MK_ENUM_CONST(3)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2_CNTRL_MUX_SELECT_DAP1                  _MK_ENUM_CONST(4)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2_CNTRL_MUX_SELECT_RSVD2                 _MK_ENUM_CONST(5)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2_CNTRL_MUX_SELECT_DAP3                  _MK_ENUM_CONST(6)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2_CNTRL_MUX_SELECT_DAP4                  _MK_ENUM_CONST(7)
+
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1_CNTRL_MUX_SELECT_SHIFT                 _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1_CNTRL_MUX_SELECT_FIELD                 (_MK_MASK_CONST(0x7) << APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1_CNTRL_MUX_SELECT_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1_CNTRL_MUX_SELECT_RANGE                 2:0
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1_CNTRL_MUX_SELECT_WOFFSET                       0x0
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1_CNTRL_MUX_SELECT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1_CNTRL_MUX_SELECT_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1_CNTRL_MUX_SELECT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1_CNTRL_MUX_SELECT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1_CNTRL_MUX_SELECT_DAC1                  _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1_CNTRL_MUX_SELECT_DAC2                  _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1_CNTRL_MUX_SELECT_DAC3                  _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1_CNTRL_MUX_SELECT_RSVD1                 _MK_ENUM_CONST(3)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1_CNTRL_MUX_SELECT_RSVD2                 _MK_ENUM_CONST(4)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1_CNTRL_MUX_SELECT_DAP2                  _MK_ENUM_CONST(5)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1_CNTRL_MUX_SELECT_DAP3                  _MK_ENUM_CONST(6)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1_CNTRL_MUX_SELECT_DAP4                  _MK_ENUM_CONST(7)
+
+
+// Register APB_MISC_PP_PULLUPDOWN_REG_A_0  
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0                  _MK_ADDR_CONST(0xa0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_WORD_COUNT                       0x1
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_RESET_VAL                        _MK_MASK_CONST(0x215556aa)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_GPV_PU_PD_SHIFT                  _MK_SHIFT_CONST(30)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_GPV_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_A_0_GPV_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_GPV_PU_PD_RANGE                  31:30
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_GPV_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_GPV_PU_PD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_GPV_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_GPV_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_GPV_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_GPV_PU_PD_INIT_ENUM                      NORMAL
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_GPV_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_GPV_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_GPV_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_GPV_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTF_PU_PD_SHIFT                  _MK_SHIFT_CONST(28)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTF_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_A_0_DTF_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTF_PU_PD_RANGE                  29:28
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTF_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTF_PU_PD_DEFAULT                        _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTF_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTF_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTF_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTF_PU_PD_INIT_ENUM                      PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTF_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTF_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTF_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTF_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTE_PU_PD_SHIFT                  _MK_SHIFT_CONST(26)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTE_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_A_0_DTE_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTE_PU_PD_RANGE                  27:26
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTE_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTE_PU_PD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTE_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTE_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTE_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTE_PU_PD_INIT_ENUM                      NORMAL
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTE_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTE_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTE_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTE_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTD_PU_PD_SHIFT                  _MK_SHIFT_CONST(24)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTD_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_A_0_DTD_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTD_PU_PD_RANGE                  25:24
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTD_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTD_PU_PD_DEFAULT                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTD_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTD_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTD_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTD_PU_PD_INIT_ENUM                      PULL_DOWN
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTD_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTD_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTD_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTD_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTC_PU_PD_SHIFT                  _MK_SHIFT_CONST(22)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTC_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_A_0_DTC_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTC_PU_PD_RANGE                  23:22
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTC_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTC_PU_PD_DEFAULT                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTC_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTC_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTC_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTC_PU_PD_INIT_ENUM                      PULL_DOWN
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTC_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTC_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTC_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTC_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTB_PU_PD_SHIFT                  _MK_SHIFT_CONST(20)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTB_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_A_0_DTB_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTB_PU_PD_RANGE                  21:20
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTB_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTB_PU_PD_DEFAULT                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTB_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTB_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTB_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTB_PU_PD_INIT_ENUM                      PULL_DOWN
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTB_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTB_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTB_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTB_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTA_PU_PD_SHIFT                  _MK_SHIFT_CONST(18)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTA_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_A_0_DTA_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTA_PU_PD_RANGE                  19:18
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTA_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTA_PU_PD_DEFAULT                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTA_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTA_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTA_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTA_PU_PD_INIT_ENUM                      PULL_DOWN
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTA_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTA_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTA_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTA_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP4_PU_PD_SHIFT                 _MK_SHIFT_CONST(16)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP4_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP4_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP4_PU_PD_RANGE                 17:16
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP4_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP4_PU_PD_DEFAULT                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP4_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP4_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP4_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP4_PU_PD_INIT_ENUM                     PULL_DOWN
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP4_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP4_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP4_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP4_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP3_PU_PD_SHIFT                 _MK_SHIFT_CONST(14)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP3_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP3_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP3_PU_PD_RANGE                 15:14
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP3_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP3_PU_PD_DEFAULT                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP3_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP3_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP3_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP3_PU_PD_INIT_ENUM                     PULL_DOWN
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP3_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP3_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP3_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP3_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP2_PU_PD_SHIFT                 _MK_SHIFT_CONST(12)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP2_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP2_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP2_PU_PD_RANGE                 13:12
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP2_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP2_PU_PD_DEFAULT                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP2_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP2_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP2_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP2_PU_PD_INIT_ENUM                     PULL_DOWN
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP2_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP2_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP2_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP2_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP1_PU_PD_SHIFT                 _MK_SHIFT_CONST(10)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP1_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP1_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP1_PU_PD_RANGE                 11:10
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP1_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP1_PU_PD_DEFAULT                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP1_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP1_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP1_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP1_PU_PD_INIT_ENUM                     PULL_DOWN
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP1_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP1_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP1_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP1_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATE_PU_PD_SHIFT                  _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATE_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_A_0_ATE_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATE_PU_PD_RANGE                  9:8
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATE_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATE_PU_PD_DEFAULT                        _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATE_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATE_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATE_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATE_PU_PD_INIT_ENUM                      PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATE_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATE_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATE_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATE_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATD_PU_PD_SHIFT                  _MK_SHIFT_CONST(6)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATD_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_A_0_ATD_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATD_PU_PD_RANGE                  7:6
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATD_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATD_PU_PD_DEFAULT                        _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATD_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATD_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATD_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATD_PU_PD_INIT_ENUM                      PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATD_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATD_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATD_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATD_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATC_PU_PD_SHIFT                  _MK_SHIFT_CONST(4)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATC_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_A_0_ATC_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATC_PU_PD_RANGE                  5:4
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATC_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATC_PU_PD_DEFAULT                        _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATC_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATC_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATC_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATC_PU_PD_INIT_ENUM                      PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATC_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATC_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATC_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATC_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATB_PU_PD_SHIFT                  _MK_SHIFT_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATB_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_A_0_ATB_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATB_PU_PD_RANGE                  3:2
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATB_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATB_PU_PD_DEFAULT                        _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATB_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATB_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATB_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATB_PU_PD_INIT_ENUM                      PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATB_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATB_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATB_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATB_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATA_PU_PD_SHIFT                  _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATA_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_A_0_ATA_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATA_PU_PD_RANGE                  1:0
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATA_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATA_PU_PD_DEFAULT                        _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATA_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATA_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATA_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATA_PU_PD_INIT_ENUM                      PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATA_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATA_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATA_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATA_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+
+// Register APB_MISC_PP_PULLUPDOWN_REG_B_0  
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0                  _MK_ADDR_CONST(0xa4)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_WORD_COUNT                       0x1
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_RESET_VAL                        _MK_MASK_CONST(0x6a8aaaaa)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXK_PU_PD_SHIFT                 _MK_SHIFT_CONST(30)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXK_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXK_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXK_PU_PD_RANGE                 31:30
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXK_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXK_PU_PD_DEFAULT                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXK_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXK_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXK_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXK_PU_PD_INIT_ENUM                     PULL_DOWN
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXK_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXK_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXK_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXK_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXD_PU_PD_SHIFT                 _MK_SHIFT_CONST(28)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXD_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXD_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXD_PU_PD_RANGE                 29:28
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXD_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXD_PU_PD_DEFAULT                       _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXD_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXD_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXD_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXD_PU_PD_INIT_ENUM                     PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXD_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXD_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXD_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXD_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXC_PU_PD_SHIFT                 _MK_SHIFT_CONST(26)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXC_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXC_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXC_PU_PD_RANGE                 27:26
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXC_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXC_PU_PD_DEFAULT                       _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXC_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXC_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXC_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXC_PU_PD_INIT_ENUM                     PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXC_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXC_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXC_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXC_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXB_PU_PD_SHIFT                 _MK_SHIFT_CONST(24)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXB_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXB_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXB_PU_PD_RANGE                 25:24
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXB_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXB_PU_PD_DEFAULT                       _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXB_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXB_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXB_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXB_PU_PD_INIT_ENUM                     PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXB_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXB_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXB_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXB_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXA_PU_PD_SHIFT                 _MK_SHIFT_CONST(22)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXA_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXA_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXA_PU_PD_RANGE                 23:22
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXA_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXA_PU_PD_DEFAULT                       _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXA_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXA_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXA_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXA_PU_PD_INIT_ENUM                     PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXA_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXA_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXA_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXA_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU_PU_PD_SHIFT                  _MK_SHIFT_CONST(20)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU_PU_PD_RANGE                  21:20
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU_PU_PD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU_PU_PD_INIT_ENUM                      NORMAL
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDO_PU_PD_SHIFT                 _MK_SHIFT_CONST(18)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDO_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDO_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDO_PU_PD_RANGE                 19:18
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDO_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDO_PU_PD_DEFAULT                       _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDO_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDO_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDO_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDO_PU_PD_INIT_ENUM                     PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDO_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDO_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDO_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDO_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDI_PU_PD_SHIFT                 _MK_SHIFT_CONST(16)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDI_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDI_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDI_PU_PD_RANGE                 17:16
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDI_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDI_PU_PD_DEFAULT                       _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDI_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDI_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDI_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDI_PU_PD_INIT_ENUM                     PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDI_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDI_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDI_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDI_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCD_PU_PD_SHIFT                 _MK_SHIFT_CONST(14)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCD_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCD_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCD_PU_PD_RANGE                 15:14
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCD_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCD_PU_PD_DEFAULT                       _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCD_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCD_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCD_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCD_PU_PD_INIT_ENUM                     PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCD_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCD_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCD_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCD_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCC_PU_PD_SHIFT                 _MK_SHIFT_CONST(12)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCC_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCC_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCC_PU_PD_RANGE                 13:12
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCC_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCC_PU_PD_DEFAULT                       _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCC_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCC_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCC_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCC_PU_PD_INIT_ENUM                     PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCC_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCC_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCC_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCC_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCB_PU_PD_SHIFT                 _MK_SHIFT_CONST(10)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCB_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCB_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCB_PU_PD_RANGE                 11:10
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCB_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCB_PU_PD_DEFAULT                       _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCB_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCB_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCB_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCB_PU_PD_INIT_ENUM                     PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCB_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCB_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCB_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCB_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCA_PU_PD_SHIFT                 _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCA_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCA_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCA_PU_PD_RANGE                 9:8
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCA_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCA_PU_PD_DEFAULT                       _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCA_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCA_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCA_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCA_PU_PD_INIT_ENUM                     PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCA_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCA_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCA_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCA_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU7_PU_PD_SHIFT                 _MK_SHIFT_CONST(6)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU7_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU7_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU7_PU_PD_RANGE                 7:6
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU7_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU7_PU_PD_DEFAULT                       _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU7_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU7_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU7_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU7_PU_PD_INIT_ENUM                     PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU7_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU7_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU7_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU7_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_PTA_PU_PD_SHIFT                  _MK_SHIFT_CONST(4)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_PTA_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_B_0_PTA_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_PTA_PU_PD_RANGE                  5:4
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_PTA_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_PTA_PU_PD_DEFAULT                        _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_PTA_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_PTA_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_PTA_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_PTA_PU_PD_INIT_ENUM                      PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_PTA_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_PTA_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_PTA_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_PTA_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_I2CP_PU_PD_SHIFT                 _MK_SHIFT_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_I2CP_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_B_0_I2CP_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_I2CP_PU_PD_RANGE                 3:2
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_I2CP_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_I2CP_PU_PD_DEFAULT                       _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_I2CP_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_I2CP_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_I2CP_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_I2CP_PU_PD_INIT_ENUM                     PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_I2CP_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_I2CP_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_I2CP_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_I2CP_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_RM_PU_PD_SHIFT                   _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_RM_PU_PD_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_B_0_RM_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_RM_PU_PD_RANGE                   1:0
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_RM_PU_PD_WOFFSET                 0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_RM_PU_PD_DEFAULT                 _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_RM_PU_PD_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_RM_PU_PD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_RM_PU_PD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_RM_PU_PD_INIT_ENUM                       PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_RM_PU_PD_NORMAL                  _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_RM_PU_PD_PULL_DOWN                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_RM_PU_PD_PULL_UP                 _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_RM_PU_PD_RSVD                    _MK_ENUM_CONST(3)
+
+
+// Register APB_MISC_PP_PULLUPDOWN_REG_C_0  
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0                  _MK_ADDR_CONST(0xa8)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_WORD_COUNT                       0x1
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_RESET_VAL                        _MK_MASK_CONST(0xaa6655)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2S_PU_PD_SHIFT                 _MK_SHIFT_CONST(30)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2S_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2S_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2S_PU_PD_RANGE                 31:30
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2S_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2S_PU_PD_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2S_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2S_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2S_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2S_PU_PD_INIT_ENUM                     NORMAL
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2S_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2S_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2S_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2S_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2D_PU_PD_SHIFT                 _MK_SHIFT_CONST(28)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2D_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2D_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2D_PU_PD_RANGE                 29:28
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2D_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2D_PU_PD_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2D_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2D_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2D_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2D_PU_PD_INIT_ENUM                     NORMAL
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2D_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2D_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2D_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2D_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2C_PU_PD_SHIFT                 _MK_SHIFT_CONST(26)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2C_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2C_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2C_PU_PD_RANGE                 27:26
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2C_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2C_PU_PD_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2C_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2C_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2C_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2C_PU_PD_INIT_ENUM                     NORMAL
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2C_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2C_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2C_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2C_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2A_PU_PD_SHIFT                 _MK_SHIFT_CONST(24)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2A_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2A_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2A_PU_PD_RANGE                 25:24
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2A_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2A_PU_PD_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2A_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2A_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2A_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2A_PU_PD_INIT_ENUM                     NORMAL
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2A_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2A_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2A_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2A_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRRX_PU_PD_SHIFT                 _MK_SHIFT_CONST(22)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRRX_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_C_0_IRRX_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRRX_PU_PD_RANGE                 23:22
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRRX_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRRX_PU_PD_DEFAULT                       _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRRX_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRRX_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRRX_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRRX_PU_PD_INIT_ENUM                     PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRRX_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRRX_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRRX_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRRX_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRTX_PU_PD_SHIFT                 _MK_SHIFT_CONST(20)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRTX_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_C_0_IRTX_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRTX_PU_PD_RANGE                 21:20
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRTX_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRTX_PU_PD_DEFAULT                       _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRTX_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRTX_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRTX_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRTX_PU_PD_INIT_ENUM                     PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRTX_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRTX_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRTX_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRTX_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIH_PU_PD_SHIFT                 _MK_SHIFT_CONST(18)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIH_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIH_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIH_PU_PD_RANGE                 19:18
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIH_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIH_PU_PD_DEFAULT                       _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIH_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIH_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIH_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIH_PU_PD_INIT_ENUM                     PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIH_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIH_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIH_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIH_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIG_PU_PD_SHIFT                 _MK_SHIFT_CONST(16)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIG_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIG_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIG_PU_PD_RANGE                 17:16
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIG_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIG_PU_PD_DEFAULT                       _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIG_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIG_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIG_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIG_PU_PD_INIT_ENUM                     PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIG_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIG_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIG_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIG_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIF_PU_PD_SHIFT                 _MK_SHIFT_CONST(14)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIF_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIF_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIF_PU_PD_RANGE                 15:14
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIF_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIF_PU_PD_DEFAULT                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIF_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIF_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIF_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIF_PU_PD_INIT_ENUM                     PULL_DOWN
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIF_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIF_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIF_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIF_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIE_PU_PD_SHIFT                 _MK_SHIFT_CONST(12)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIE_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIE_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIE_PU_PD_RANGE                 13:12
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIE_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIE_PU_PD_DEFAULT                       _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIE_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIE_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIE_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIE_PU_PD_INIT_ENUM                     PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIE_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIE_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIE_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIE_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPID_PU_PD_SHIFT                 _MK_SHIFT_CONST(10)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPID_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_C_0_SPID_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPID_PU_PD_RANGE                 11:10
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPID_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPID_PU_PD_DEFAULT                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPID_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPID_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPID_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPID_PU_PD_INIT_ENUM                     PULL_DOWN
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPID_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPID_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPID_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPID_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIC_PU_PD_SHIFT                 _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIC_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIC_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIC_PU_PD_RANGE                 9:8
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIC_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIC_PU_PD_DEFAULT                       _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIC_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIC_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIC_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIC_PU_PD_INIT_ENUM                     PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIC_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIC_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIC_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIC_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIB_PU_PD_SHIFT                 _MK_SHIFT_CONST(6)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIB_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIB_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIB_PU_PD_RANGE                 7:6
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIB_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIB_PU_PD_DEFAULT                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIB_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIB_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIB_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIB_PU_PD_INIT_ENUM                     PULL_DOWN
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIB_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIB_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIB_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIB_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIA_PU_PD_SHIFT                 _MK_SHIFT_CONST(4)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIA_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIA_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIA_PU_PD_RANGE                 5:4
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIA_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIA_PU_PD_DEFAULT                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIA_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIA_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIA_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIA_PU_PD_INIT_ENUM                     PULL_DOWN
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIA_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIA_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIA_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIA_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV2_PU_PD_SHIFT                        _MK_SHIFT_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV2_PU_PD_FIELD                        (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV2_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV2_PU_PD_RANGE                        3:2
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV2_PU_PD_WOFFSET                      0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV2_PU_PD_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV2_PU_PD_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV2_PU_PD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV2_PU_PD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV2_PU_PD_INIT_ENUM                    PULL_DOWN
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV2_PU_PD_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV2_PU_PD_PULL_DOWN                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV2_PU_PD_PULL_UP                      _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV2_PU_PD_RSVD                 _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV1_PU_PD_SHIFT                        _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV1_PU_PD_FIELD                        (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV1_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV1_PU_PD_RANGE                        1:0
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV1_PU_PD_WOFFSET                      0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV1_PU_PD_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV1_PU_PD_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV1_PU_PD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV1_PU_PD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV1_PU_PD_INIT_ENUM                    PULL_DOWN
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV1_PU_PD_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV1_PU_PD_PULL_DOWN                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV1_PU_PD_PULL_UP                      _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV1_PU_PD_RSVD                 _MK_ENUM_CONST(3)
+
+
+// Register APB_MISC_PP_PULLUPDOWN_REG_D_0  
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0                  _MK_ADDR_CONST(0xac)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_WORD_COUNT                       0x1
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_RESET_VAL                        _MK_MASK_CONST(0xa8a55a8a)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDD_PU_PD_SHIFT                  _MK_SHIFT_CONST(30)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDD_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_D_0_SDD_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDD_PU_PD_RANGE                  31:30
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDD_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDD_PU_PD_DEFAULT                        _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDD_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDD_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDD_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDD_PU_PD_INIT_ENUM                      PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDD_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDD_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDD_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDD_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDC_PU_PD_SHIFT                  _MK_SHIFT_CONST(28)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDC_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_D_0_SDC_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDC_PU_PD_RANGE                  29:28
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDC_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDC_PU_PD_DEFAULT                        _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDC_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDC_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDC_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDC_PU_PD_INIT_ENUM                      PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDC_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDC_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDC_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDC_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDB_PU_PD_SHIFT                  _MK_SHIFT_CONST(26)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDB_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_D_0_SDB_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDB_PU_PD_RANGE                  27:26
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDB_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDB_PU_PD_DEFAULT                        _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDB_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDB_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDB_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDB_PU_PD_INIT_ENUM                      PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDB_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDB_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDB_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDB_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+// LC_P? for : lcd_pclk, lcd_de, lcd_hsycn, lcd_vsync, lcd_m0, lcd_m1, lcd_vp0, hdmi_int
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_CSUS_PU_PD_SHIFT                 _MK_SHIFT_CONST(24)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_CSUS_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_D_0_CSUS_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_CSUS_PU_PD_RANGE                 25:24
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_CSUS_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_CSUS_PU_PD_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_CSUS_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_CSUS_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_CSUS_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_CSUS_PU_PD_INIT_ENUM                     NORMAL
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_CSUS_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_CSUS_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_CSUS_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_CSUS_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+// LS_P? for : lcd_sdin, lcd_sdout, lcd_wr_, lcd_cs0, lcd_dc0, lcd_sck, lcd_pwr0, lcd_pwr1, lcd_pwr2
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LC_PU_PD_SHIFT                   _MK_SHIFT_CONST(22)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LC_PU_PD_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_D_0_LC_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LC_PU_PD_RANGE                   23:22
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LC_PU_PD_WOFFSET                 0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LC_PU_PD_DEFAULT                 _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LC_PU_PD_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LC_PU_PD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LC_PU_PD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LC_PU_PD_INIT_ENUM                       PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LC_PU_PD_NORMAL                  _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LC_PU_PD_PULL_DOWN                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LC_PU_PD_PULL_UP                 _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LC_PU_PD_RSVD                    _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LS_PU_PD_SHIFT                   _MK_SHIFT_CONST(20)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LS_PU_PD_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_D_0_LS_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LS_PU_PD_RANGE                   21:20
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LS_PU_PD_WOFFSET                 0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LS_PU_PD_DEFAULT                 _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LS_PU_PD_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LS_PU_PD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LS_PU_PD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LS_PU_PD_INIT_ENUM                       PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LS_PU_PD_NORMAL                  _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LS_PU_PD_PULL_DOWN                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LS_PU_PD_PULL_UP                 _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LS_PU_PD_RSVD                    _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD23_22_PU_PD_SHIFT                      _MK_SHIFT_CONST(18)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD23_22_PU_PD_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_D_0_LD23_22_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD23_22_PU_PD_RANGE                      19:18
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD23_22_PU_PD_WOFFSET                    0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD23_22_PU_PD_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD23_22_PU_PD_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD23_22_PU_PD_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD23_22_PU_PD_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD23_22_PU_PD_INIT_ENUM                  PULL_DOWN
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD23_22_PU_PD_NORMAL                     _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD23_22_PU_PD_PULL_DOWN                  _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD23_22_PU_PD_PULL_UP                    _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD23_22_PU_PD_RSVD                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD21_20_PU_PD_SHIFT                      _MK_SHIFT_CONST(16)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD21_20_PU_PD_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_D_0_LD21_20_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD21_20_PU_PD_RANGE                      17:16
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD21_20_PU_PD_WOFFSET                    0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD21_20_PU_PD_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD21_20_PU_PD_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD21_20_PU_PD_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD21_20_PU_PD_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD21_20_PU_PD_INIT_ENUM                  PULL_DOWN
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD21_20_PU_PD_NORMAL                     _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD21_20_PU_PD_PULL_DOWN                  _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD21_20_PU_PD_PULL_UP                    _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD21_20_PU_PD_RSVD                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD19_18_PU_PD_SHIFT                      _MK_SHIFT_CONST(14)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD19_18_PU_PD_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_D_0_LD19_18_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD19_18_PU_PD_RANGE                      15:14
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD19_18_PU_PD_WOFFSET                    0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD19_18_PU_PD_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD19_18_PU_PD_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD19_18_PU_PD_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD19_18_PU_PD_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD19_18_PU_PD_INIT_ENUM                  PULL_DOWN
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD19_18_PU_PD_NORMAL                     _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD19_18_PU_PD_PULL_DOWN                  _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD19_18_PU_PD_PULL_UP                    _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD19_18_PU_PD_RSVD                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD17_0_PU_PD_SHIFT                       _MK_SHIFT_CONST(12)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD17_0_PU_PD_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_D_0_LD17_0_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD17_0_PU_PD_RANGE                       13:12
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD17_0_PU_PD_WOFFSET                     0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD17_0_PU_PD_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD17_0_PU_PD_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD17_0_PU_PD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD17_0_PU_PD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD17_0_PU_PD_INIT_ENUM                   PULL_DOWN
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD17_0_PU_PD_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD17_0_PU_PD_PULL_DOWN                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD17_0_PU_PD_PULL_UP                     _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD17_0_PU_PD_RSVD                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCB_PU_PD_SHIFT                  _MK_SHIFT_CONST(10)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCB_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_D_0_UCB_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCB_PU_PD_RANGE                  11:10
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCB_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCB_PU_PD_DEFAULT                        _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCB_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCB_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCB_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCB_PU_PD_INIT_ENUM                      PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCB_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCB_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCB_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCB_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCA_PU_PD_SHIFT                  _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCA_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_D_0_UCA_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCA_PU_PD_RANGE                  9:8
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCA_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCA_PU_PD_DEFAULT                        _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCA_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCA_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCA_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCA_PU_PD_INIT_ENUM                      PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCA_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCA_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCA_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCA_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAD_PU_PD_SHIFT                  _MK_SHIFT_CONST(6)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAD_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_D_0_UAD_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAD_PU_PD_RANGE                  7:6
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAD_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAD_PU_PD_DEFAULT                        _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAD_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAD_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAD_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAD_PU_PD_INIT_ENUM                      PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAD_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAD_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAD_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAD_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAC_PU_PD_SHIFT                  _MK_SHIFT_CONST(4)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAC_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_D_0_UAC_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAC_PU_PD_RANGE                  5:4
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAC_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAC_PU_PD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAC_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAC_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAC_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAC_PU_PD_INIT_ENUM                      NORMAL
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAC_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAC_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAC_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAC_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAB_PU_PD_SHIFT                  _MK_SHIFT_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAB_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_D_0_UAB_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAB_PU_PD_RANGE                  3:2
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAB_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAB_PU_PD_DEFAULT                        _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAB_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAB_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAB_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAB_PU_PD_INIT_ENUM                      PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAB_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAB_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAB_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAB_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAA_PU_PD_SHIFT                  _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAA_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_D_0_UAA_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAA_PU_PD_RANGE                  1:0
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAA_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAA_PU_PD_DEFAULT                        _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAA_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAA_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAA_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAA_PU_PD_INIT_ENUM                      PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAA_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAA_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAA_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAA_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+
+// Register APB_MISC_PP_PULLUPDOWN_REG_E_0  
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0                  _MK_ADDR_CONST(0xb0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_WORD_COUNT                       0x1
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_RESET_VAL                        _MK_MASK_CONST(0xa)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_RSVD_7_SHIFT                     _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_RSVD_7_FIELD                     (_MK_MASK_CONST(0xffffff) << APB_MISC_PP_PULLUPDOWN_REG_E_0_RSVD_7_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_RSVD_7_RANGE                     31:8
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_RSVD_7_WOFFSET                   0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_RSVD_7_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_RSVD_7_DEFAULT_MASK                      _MK_MASK_CONST(0xffffff)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_RSVD_7_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_RSVD_7_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCB_PU_PD_SHIFT                 _MK_SHIFT_CONST(6)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCB_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCB_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCB_PU_PD_RANGE                 7:6
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCB_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCB_PU_PD_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCB_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCB_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCB_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCB_PU_PD_INIT_ENUM                     NORMAL
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCB_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCB_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCB_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCB_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCA_PU_PD_SHIFT                 _MK_SHIFT_CONST(4)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCA_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCA_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCA_PU_PD_RANGE                 5:4
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCA_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCA_PU_PD_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCA_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCA_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCA_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCA_PU_PD_INIT_ENUM                     NORMAL
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCA_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCA_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCA_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCA_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCE_PU_PD_SHIFT                 _MK_SHIFT_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCE_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCE_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCE_PU_PD_RANGE                 3:2
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCE_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCE_PU_PD_DEFAULT                       _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCE_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCE_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCE_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCE_PU_PD_INIT_ENUM                     PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCE_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCE_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCE_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCE_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCF_PU_PD_SHIFT                 _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCF_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCF_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCF_PU_PD_RANGE                 1:0
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCF_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCF_PU_PD_DEFAULT                       _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCF_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCF_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCF_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCF_PU_PD_INIT_ENUM                     PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCF_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCF_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCF_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCF_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+
+// Register APB_MISC_PP_MISC_USB_CLK_RST_CTL_0  
+#define APB_MISC_PP_MISC_USB_CLK_RST_CTL_0                      _MK_ADDR_CONST(0xb4)
+#define APB_MISC_PP_MISC_USB_CLK_RST_CTL_0_WORD_COUNT                   0x1
+#define APB_MISC_PP_MISC_USB_CLK_RST_CTL_0_RESET_VAL                    _MK_MASK_CONST(0x201)
+#define APB_MISC_PP_MISC_USB_CLK_RST_CTL_0_RESET_MASK                   _MK_MASK_CONST(0x307)
+#define APB_MISC_PP_MISC_USB_CLK_RST_CTL_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_CLK_RST_CTL_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_CLK_RST_CTL_0_READ_MASK                    _MK_MASK_CONST(0x307)
+#define APB_MISC_PP_MISC_USB_CLK_RST_CTL_0_WRITE_MASK                   _MK_MASK_CONST(0x307)
+// Reset (active high) for USB2 controller
+#define APB_MISC_PP_MISC_USB_CLK_RST_CTL_0_MISC_USB2_RST_SHIFT                  _MK_SHIFT_CONST(9)
+#define APB_MISC_PP_MISC_USB_CLK_RST_CTL_0_MISC_USB2_RST_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_CLK_RST_CTL_0_MISC_USB2_RST_SHIFT)
+#define APB_MISC_PP_MISC_USB_CLK_RST_CTL_0_MISC_USB2_RST_RANGE                  9:9
+#define APB_MISC_PP_MISC_USB_CLK_RST_CTL_0_MISC_USB2_RST_WOFFSET                        0x0
+#define APB_MISC_PP_MISC_USB_CLK_RST_CTL_0_MISC_USB2_RST_DEFAULT                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_CLK_RST_CTL_0_MISC_USB2_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_CLK_RST_CTL_0_MISC_USB2_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_CLK_RST_CTL_0_MISC_USB2_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_CLK_RST_CTL_0_MISC_USB2_RST_INIT_ENUM                      ENABLE
+#define APB_MISC_PP_MISC_USB_CLK_RST_CTL_0_MISC_USB2_RST_DISABLE                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_CLK_RST_CTL_0_MISC_USB2_RST_ENABLE                 _MK_ENUM_CONST(1)
+
+// Reset (active high) for USB controller
+#define APB_MISC_PP_MISC_USB_CLK_RST_CTL_0_MISC_USB_RST_SHIFT                   _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_MISC_USB_CLK_RST_CTL_0_MISC_USB_RST_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_CLK_RST_CTL_0_MISC_USB_RST_SHIFT)
+#define APB_MISC_PP_MISC_USB_CLK_RST_CTL_0_MISC_USB_RST_RANGE                   8:8
+#define APB_MISC_PP_MISC_USB_CLK_RST_CTL_0_MISC_USB_RST_WOFFSET                 0x0
+#define APB_MISC_PP_MISC_USB_CLK_RST_CTL_0_MISC_USB_RST_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_CLK_RST_CTL_0_MISC_USB_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_CLK_RST_CTL_0_MISC_USB_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_CLK_RST_CTL_0_MISC_USB_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_CLK_RST_CTL_0_MISC_USB_RST_INIT_ENUM                       DISABLE
+#define APB_MISC_PP_MISC_USB_CLK_RST_CTL_0_MISC_USB_RST_DISABLE                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_CLK_RST_CTL_0_MISC_USB_RST_ENABLE                  _MK_ENUM_CONST(1)
+
+// Clock override for USB2 controller
+#define APB_MISC_PP_MISC_USB_CLK_RST_CTL_0_MISC_USB2_CLK_OVR_ON_SHIFT                   _MK_SHIFT_CONST(2)
+#define APB_MISC_PP_MISC_USB_CLK_RST_CTL_0_MISC_USB2_CLK_OVR_ON_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_CLK_RST_CTL_0_MISC_USB2_CLK_OVR_ON_SHIFT)
+#define APB_MISC_PP_MISC_USB_CLK_RST_CTL_0_MISC_USB2_CLK_OVR_ON_RANGE                   2:2
+#define APB_MISC_PP_MISC_USB_CLK_RST_CTL_0_MISC_USB2_CLK_OVR_ON_WOFFSET                 0x0
+#define APB_MISC_PP_MISC_USB_CLK_RST_CTL_0_MISC_USB2_CLK_OVR_ON_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_CLK_RST_CTL_0_MISC_USB2_CLK_OVR_ON_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_CLK_RST_CTL_0_MISC_USB2_CLK_OVR_ON_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_CLK_RST_CTL_0_MISC_USB2_CLK_OVR_ON_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_CLK_RST_CTL_0_MISC_USB2_CLK_OVR_ON_INIT_ENUM                       DISABLE
+#define APB_MISC_PP_MISC_USB_CLK_RST_CTL_0_MISC_USB2_CLK_OVR_ON_DISABLE                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_CLK_RST_CTL_0_MISC_USB2_CLK_OVR_ON_ENABLE                  _MK_ENUM_CONST(1)
+
+// enable clocks to USB2 controller
+#define APB_MISC_PP_MISC_USB_CLK_RST_CTL_0_MISC_USB2_CE_SHIFT                   _MK_SHIFT_CONST(1)
+#define APB_MISC_PP_MISC_USB_CLK_RST_CTL_0_MISC_USB2_CE_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_CLK_RST_CTL_0_MISC_USB2_CE_SHIFT)
+#define APB_MISC_PP_MISC_USB_CLK_RST_CTL_0_MISC_USB2_CE_RANGE                   1:1
+#define APB_MISC_PP_MISC_USB_CLK_RST_CTL_0_MISC_USB2_CE_WOFFSET                 0x0
+#define APB_MISC_PP_MISC_USB_CLK_RST_CTL_0_MISC_USB2_CE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_CLK_RST_CTL_0_MISC_USB2_CE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_CLK_RST_CTL_0_MISC_USB2_CE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_CLK_RST_CTL_0_MISC_USB2_CE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_CLK_RST_CTL_0_MISC_USB2_CE_INIT_ENUM                       DISABLE
+#define APB_MISC_PP_MISC_USB_CLK_RST_CTL_0_MISC_USB2_CE_DISABLE                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_CLK_RST_CTL_0_MISC_USB2_CE_ENABLE                  _MK_ENUM_CONST(1)
+
+// enable clocks to USB controller
+#define APB_MISC_PP_MISC_USB_CLK_RST_CTL_0_MISC_USB_CE_SHIFT                    _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_MISC_USB_CLK_RST_CTL_0_MISC_USB_CE_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_CLK_RST_CTL_0_MISC_USB_CE_SHIFT)
+#define APB_MISC_PP_MISC_USB_CLK_RST_CTL_0_MISC_USB_CE_RANGE                    0:0
+#define APB_MISC_PP_MISC_USB_CLK_RST_CTL_0_MISC_USB_CE_WOFFSET                  0x0
+#define APB_MISC_PP_MISC_USB_CLK_RST_CTL_0_MISC_USB_CE_DEFAULT                  _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_CLK_RST_CTL_0_MISC_USB_CE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_CLK_RST_CTL_0_MISC_USB_CE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_CLK_RST_CTL_0_MISC_USB_CE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_CLK_RST_CTL_0_MISC_USB_CE_INIT_ENUM                        ENABLE
+#define APB_MISC_PP_MISC_USB_CLK_RST_CTL_0_MISC_USB_CE_DISABLE                  _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_CLK_RST_CTL_0_MISC_USB_CE_ENABLE                   _MK_ENUM_CONST(1)
+
+
+// Register APB_MISC_ASYNC_COREPWRCONFIG_0  
+#define APB_MISC_ASYNC_COREPWRCONFIG_0                  _MK_ADDR_CONST(0x400)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_WORD_COUNT                       0x1
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_RESET_MASK                       _MK_MASK_CONST(0x7)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_READ_MASK                        _MK_MASK_CONST(0x7)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_WRITE_MASK                       _MK_MASK_CONST(0x7)
+// Power is on in TDA/TDB partitions
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_TD_COREPWR_EN_SHIFT                      _MK_SHIFT_CONST(0)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_TD_COREPWR_EN_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_COREPWRCONFIG_0_TD_COREPWR_EN_SHIFT)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_TD_COREPWR_EN_RANGE                      0:0
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_TD_COREPWR_EN_WOFFSET                    0x0
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_TD_COREPWR_EN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_TD_COREPWR_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_TD_COREPWR_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_TD_COREPWR_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_TD_COREPWR_EN_INIT_ENUM                  DISABLE
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_TD_COREPWR_EN_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_TD_COREPWR_EN_ENABLE                     _MK_ENUM_CONST(1)
+
+// Power is on in VE/MPE partitions
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_VE_COREPWR_EN_SHIFT                      _MK_SHIFT_CONST(1)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_VE_COREPWR_EN_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_COREPWRCONFIG_0_VE_COREPWR_EN_SHIFT)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_VE_COREPWR_EN_RANGE                      1:1
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_VE_COREPWR_EN_WOFFSET                    0x0
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_VE_COREPWR_EN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_VE_COREPWR_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_VE_COREPWR_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_VE_COREPWR_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_VE_COREPWR_EN_INIT_ENUM                  DISABLE
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_VE_COREPWR_EN_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_VE_COREPWR_EN_ENABLE                     _MK_ENUM_CONST(1)
+
+// Power is on in CPU partition
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_CPU_COREPWR_EN_SHIFT                     _MK_SHIFT_CONST(2)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_CPU_COREPWR_EN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_COREPWRCONFIG_0_CPU_COREPWR_EN_SHIFT)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_CPU_COREPWR_EN_RANGE                     2:2
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_CPU_COREPWR_EN_WOFFSET                   0x0
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_CPU_COREPWR_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_CPU_COREPWR_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_CPU_COREPWR_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_CPU_COREPWR_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_CPU_COREPWR_EN_INIT_ENUM                 DISABLE
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_CPU_COREPWR_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_CPU_COREPWR_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+
+// Reserved address 1028 [0x404] 
+
+// Register APB_MISC_ASYNC_DLYCTRL_0  
+#define APB_MISC_ASYNC_DLYCTRL_0                        _MK_ADDR_CONST(0x408)
+#define APB_MISC_ASYNC_DLYCTRL_0_WORD_COUNT                     0x1
+#define APB_MISC_ASYNC_DLYCTRL_0_RESET_VAL                      _MK_MASK_CONST(0x8)
+#define APB_MISC_ASYNC_DLYCTRL_0_RESET_MASK                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_ASYNC_DLYCTRL_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_DLYCTRL_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_DLYCTRL_0_READ_MASK                      _MK_MASK_CONST(0x1f)
+#define APB_MISC_ASYNC_DLYCTRL_0_WRITE_MASK                     _MK_MASK_CONST(0x1f)
+// Delay on RDY output.  
+#define APB_MISC_ASYNC_DLYCTRL_0_RDY_DLY_SHIFT                  _MK_SHIFT_CONST(0)
+#define APB_MISC_ASYNC_DLYCTRL_0_RDY_DLY_FIELD                  (_MK_MASK_CONST(0x1f) << APB_MISC_ASYNC_DLYCTRL_0_RDY_DLY_SHIFT)
+#define APB_MISC_ASYNC_DLYCTRL_0_RDY_DLY_RANGE                  4:0
+#define APB_MISC_ASYNC_DLYCTRL_0_RDY_DLY_WOFFSET                        0x0
+#define APB_MISC_ASYNC_DLYCTRL_0_RDY_DLY_DEFAULT                        _MK_MASK_CONST(0x8)
+#define APB_MISC_ASYNC_DLYCTRL_0_RDY_DLY_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define APB_MISC_ASYNC_DLYCTRL_0_RDY_DLY_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_DLYCTRL_0_RDY_DLY_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_ASYNC_CLKMNTREN_0  
+#define APB_MISC_ASYNC_CLKMNTREN_0                      _MK_ADDR_CONST(0x40c)
+#define APB_MISC_ASYNC_CLKMNTREN_0_WORD_COUNT                   0x1
+#define APB_MISC_ASYNC_CLKMNTREN_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_CLKMNTREN_0_RESET_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_CLKMNTREN_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_CLKMNTREN_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_CLKMNTREN_0_READ_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_CLKMNTREN_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
+// clock monitor enable
+#define APB_MISC_ASYNC_CLKMNTREN_0_CLK_MONITOR_EN_SHIFT                 _MK_SHIFT_CONST(0)
+#define APB_MISC_ASYNC_CLKMNTREN_0_CLK_MONITOR_EN_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_CLKMNTREN_0_CLK_MONITOR_EN_SHIFT)
+#define APB_MISC_ASYNC_CLKMNTREN_0_CLK_MONITOR_EN_RANGE                 0:0
+#define APB_MISC_ASYNC_CLKMNTREN_0_CLK_MONITOR_EN_WOFFSET                       0x0
+#define APB_MISC_ASYNC_CLKMNTREN_0_CLK_MONITOR_EN_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_CLKMNTREN_0_CLK_MONITOR_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_CLKMNTREN_0_CLK_MONITOR_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_CLKMNTREN_0_CLK_MONITOR_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_CLKMNTREN_0_CLK_MONITOR_EN_DISABLE                       _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_CLKMNTREN_0_CLK_MONITOR_EN_ENABLE                        _MK_ENUM_CONST(1)
+
+
+// Register APB_MISC_ASYNC_EMCPADEN_0  
+#define APB_MISC_ASYNC_EMCPADEN_0                       _MK_ADDR_CONST(0x410)
+#define APB_MISC_ASYNC_EMCPADEN_0_WORD_COUNT                    0x1
+#define APB_MISC_ASYNC_EMCPADEN_0_RESET_VAL                     _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_EMCPADEN_0_RESET_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_EMCPADEN_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_EMCPADEN_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_EMCPADEN_0_READ_MASK                     _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_EMCPADEN_0_WRITE_MASK                    _MK_MASK_CONST(0x3)
+// outputs enable for EMC pads
+#define APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_OUTPUT_EN_SHIFT                       _MK_SHIFT_CONST(0)
+#define APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_OUTPUT_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_OUTPUT_EN_SHIFT)
+#define APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_OUTPUT_EN_RANGE                       0:0
+#define APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_OUTPUT_EN_WOFFSET                     0x0
+#define APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_OUTPUT_EN_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_OUTPUT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_OUTPUT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_OUTPUT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_OUTPUT_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_OUTPUT_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// inputs enable for EMC pads
+#define APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_INPUT_EN_SHIFT                        _MK_SHIFT_CONST(1)
+#define APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_INPUT_EN_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_INPUT_EN_SHIFT)
+#define APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_INPUT_EN_RANGE                        1:1
+#define APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_INPUT_EN_WOFFSET                      0x0
+#define APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_INPUT_EN_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_INPUT_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_INPUT_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_INPUT_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_INPUT_EN_DISABLE                      _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_INPUT_EN_ENABLE                       _MK_ENUM_CONST(1)
+
+
+// Register APB_MISC_ASYNC_EMCPADCTRL_0  
+#define APB_MISC_ASYNC_EMCPADCTRL_0                     _MK_ADDR_CONST(0x414)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_WORD_COUNT                  0x1
+#define APB_MISC_ASYNC_EMCPADCTRL_0_RESET_VAL                   _MK_MASK_CONST(0xff0f1)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_RESET_MASK                  _MK_MASK_CONST(0x1ff3f3)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_READ_MASK                   _MK_MASK_CONST(0x1ff3f3)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_WRITE_MASK                  _MK_MASK_CONST(0x1ff3f3)
+// EMC 3.3V mode enable
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM_33V_EN_SHIFT                    _MK_SHIFT_CONST(0)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM_33V_EN_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_EMCPADCTRL_0_MEM_33V_EN_SHIFT)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM_33V_EN_RANGE                    0:0
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM_33V_EN_WOFFSET                  0x0
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM_33V_EN_DEFAULT                  _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM_33V_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM_33V_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM_33V_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM_33V_EN_DISABLE                  _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM_33V_EN_ENABLE                   _MK_ENUM_CONST(1)
+
+// EMC vref enable
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM_VREF_EN_SHIFT                   _MK_SHIFT_CONST(1)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM_VREF_EN_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_EMCPADCTRL_0_MEM_VREF_EN_SHIFT)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM_VREF_EN_RANGE                   1:1
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM_VREF_EN_WOFFSET                 0x0
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM_VREF_EN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM_VREF_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM_VREF_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM_VREF_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM_VREF_EN_DISABLE                 _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM_VREF_EN_ENABLE                  _MK_ENUM_CONST(1)
+
+// EMC data pins high speed mode enable
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_DAT_HSM_EN_SHIFT                       _MK_SHIFT_CONST(4)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_DAT_HSM_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_DAT_HSM_EN_SHIFT)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_DAT_HSM_EN_RANGE                       4:4
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_DAT_HSM_EN_WOFFSET                     0x0
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_DAT_HSM_EN_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_DAT_HSM_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_DAT_HSM_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_DAT_HSM_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_DAT_HSM_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_DAT_HSM_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// EMC data pins high speed mode enable
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_DAT_HSM_EN_SHIFT                       _MK_SHIFT_CONST(5)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_DAT_HSM_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_DAT_HSM_EN_SHIFT)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_DAT_HSM_EN_RANGE                       5:5
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_DAT_HSM_EN_WOFFSET                     0x0
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_DAT_HSM_EN_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_DAT_HSM_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_DAT_HSM_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_DAT_HSM_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_DAT_HSM_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_DAT_HSM_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// EMC control pins high speed mode enable
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_CTRL_HSM_EN_SHIFT                      _MK_SHIFT_CONST(6)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_CTRL_HSM_EN_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_CTRL_HSM_EN_SHIFT)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_CTRL_HSM_EN_RANGE                      6:6
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_CTRL_HSM_EN_WOFFSET                    0x0
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_CTRL_HSM_EN_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_CTRL_HSM_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_CTRL_HSM_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_CTRL_HSM_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_CTRL_HSM_EN_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_CTRL_HSM_EN_ENABLE                     _MK_ENUM_CONST(1)
+
+// EMC control pins high speed mode enable
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_CTRL_HSM_EN_SHIFT                      _MK_SHIFT_CONST(7)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_CTRL_HSM_EN_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_CTRL_HSM_EN_SHIFT)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_CTRL_HSM_EN_RANGE                      7:7
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_CTRL_HSM_EN_WOFFSET                    0x0
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_CTRL_HSM_EN_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_CTRL_HSM_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_CTRL_HSM_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_CTRL_HSM_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_CTRL_HSM_EN_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_CTRL_HSM_EN_ENABLE                     _MK_ENUM_CONST(1)
+
+// EMC data pins schmidt enable
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_DAT_SCHMT_EN_SHIFT                     _MK_SHIFT_CONST(8)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_DAT_SCHMT_EN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_DAT_SCHMT_EN_SHIFT)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_DAT_SCHMT_EN_RANGE                     8:8
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_DAT_SCHMT_EN_WOFFSET                   0x0
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_DAT_SCHMT_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_DAT_SCHMT_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_DAT_SCHMT_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_DAT_SCHMT_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_DAT_SCHMT_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_DAT_SCHMT_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// EMC data pins schmidt enable
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_DAT_SCHMT_EN_SHIFT                     _MK_SHIFT_CONST(9)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_DAT_SCHMT_EN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_DAT_SCHMT_EN_SHIFT)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_DAT_SCHMT_EN_RANGE                     9:9
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_DAT_SCHMT_EN_WOFFSET                   0x0
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_DAT_SCHMT_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_DAT_SCHMT_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_DAT_SCHMT_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_DAT_SCHMT_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_DAT_SCHMT_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_DAT_SCHMT_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// EMC data pins low power mode select
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_DAT_LPMD_SHIFT                 _MK_SHIFT_CONST(12)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_DAT_LPMD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_DAT_LPMD_SHIFT)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_DAT_LPMD_RANGE                 13:12
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_DAT_LPMD_WOFFSET                       0x0
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_DAT_LPMD_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_DAT_LPMD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_DAT_LPMD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_DAT_LPMD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// EMC data pins low power mode select
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_DAT_LPMD_SHIFT                 _MK_SHIFT_CONST(14)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_DAT_LPMD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_DAT_LPMD_SHIFT)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_DAT_LPMD_RANGE                 15:14
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_DAT_LPMD_WOFFSET                       0x0
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_DAT_LPMD_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_DAT_LPMD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_DAT_LPMD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_DAT_LPMD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// EMC control pins low power mode select
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_CTRL_LPMD_SHIFT                        _MK_SHIFT_CONST(16)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_CTRL_LPMD_FIELD                        (_MK_MASK_CONST(0x3) << APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_CTRL_LPMD_SHIFT)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_CTRL_LPMD_RANGE                        17:16
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_CTRL_LPMD_WOFFSET                      0x0
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_CTRL_LPMD_DEFAULT                      _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_CTRL_LPMD_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_CTRL_LPMD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_CTRL_LPMD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// EMC control pins low power mode select
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_CTRL_LPMD_SHIFT                        _MK_SHIFT_CONST(18)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_CTRL_LPMD_FIELD                        (_MK_MASK_CONST(0x3) << APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_CTRL_LPMD_SHIFT)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_CTRL_LPMD_RANGE                        19:18
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_CTRL_LPMD_WOFFSET                      0x0
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_CTRL_LPMD_DEFAULT                      _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_CTRL_LPMD_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_CTRL_LPMD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_CTRL_LPMD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// EMC pull-down enable
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM_PULLD_SHIFT                     _MK_SHIFT_CONST(20)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM_PULLD_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_EMCPADCTRL_0_MEM_PULLD_SHIFT)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM_PULLD_RANGE                     20:20
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM_PULLD_WOFFSET                   0x0
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM_PULLD_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM_PULLD_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM_PULLD_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM_PULLD_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM_PULLD_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM_PULLD_ENABLE                    _MK_ENUM_CONST(1)
+
+
+// Register APB_MISC_ASYNC_MEMPADCAL1_0  
+#define APB_MISC_ASYNC_MEMPADCAL1_0                     _MK_ADDR_CONST(0x418)
+#define APB_MISC_ASYNC_MEMPADCAL1_0_WORD_COUNT                  0x1
+#define APB_MISC_ASYNC_MEMPADCAL1_0_RESET_VAL                   _MK_MASK_CONST(0x7f7f)
+#define APB_MISC_ASYNC_MEMPADCAL1_0_RESET_MASK                  _MK_MASK_CONST(0x7f7f)
+#define APB_MISC_ASYNC_MEMPADCAL1_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_MEMPADCAL1_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_MEMPADCAL1_0_READ_MASK                   _MK_MASK_CONST(0x7f7f)
+#define APB_MISC_ASYNC_MEMPADCAL1_0_WRITE_MASK                  _MK_MASK_CONST(0x7f7f)
+#define APB_MISC_ASYNC_MEMPADCAL1_0_MEM_CAL_DRVDN_SHIFT                 _MK_SHIFT_CONST(0)
+#define APB_MISC_ASYNC_MEMPADCAL1_0_MEM_CAL_DRVDN_FIELD                 (_MK_MASK_CONST(0x1f) << APB_MISC_ASYNC_MEMPADCAL1_0_MEM_CAL_DRVDN_SHIFT)
+#define APB_MISC_ASYNC_MEMPADCAL1_0_MEM_CAL_DRVDN_RANGE                 4:0
+#define APB_MISC_ASYNC_MEMPADCAL1_0_MEM_CAL_DRVDN_WOFFSET                       0x0
+#define APB_MISC_ASYNC_MEMPADCAL1_0_MEM_CAL_DRVDN_DEFAULT                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_ASYNC_MEMPADCAL1_0_MEM_CAL_DRVDN_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define APB_MISC_ASYNC_MEMPADCAL1_0_MEM_CAL_DRVDN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_MEMPADCAL1_0_MEM_CAL_DRVDN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_ASYNC_MEMPADCAL1_0_MEM_CAL_DRVDN_SLWR_SHIFT                    _MK_SHIFT_CONST(5)
+#define APB_MISC_ASYNC_MEMPADCAL1_0_MEM_CAL_DRVDN_SLWR_FIELD                    (_MK_MASK_CONST(0x3) << APB_MISC_ASYNC_MEMPADCAL1_0_MEM_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_ASYNC_MEMPADCAL1_0_MEM_CAL_DRVDN_SLWR_RANGE                    6:5
+#define APB_MISC_ASYNC_MEMPADCAL1_0_MEM_CAL_DRVDN_SLWR_WOFFSET                  0x0
+#define APB_MISC_ASYNC_MEMPADCAL1_0_MEM_CAL_DRVDN_SLWR_DEFAULT                  _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_MEMPADCAL1_0_MEM_CAL_DRVDN_SLWR_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_MEMPADCAL1_0_MEM_CAL_DRVDN_SLWR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_MEMPADCAL1_0_MEM_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_ASYNC_MEMPADCAL1_0_MEM_CAL_DRVUP_SHIFT                 _MK_SHIFT_CONST(8)
+#define APB_MISC_ASYNC_MEMPADCAL1_0_MEM_CAL_DRVUP_FIELD                 (_MK_MASK_CONST(0x1f) << APB_MISC_ASYNC_MEMPADCAL1_0_MEM_CAL_DRVUP_SHIFT)
+#define APB_MISC_ASYNC_MEMPADCAL1_0_MEM_CAL_DRVUP_RANGE                 12:8
+#define APB_MISC_ASYNC_MEMPADCAL1_0_MEM_CAL_DRVUP_WOFFSET                       0x0
+#define APB_MISC_ASYNC_MEMPADCAL1_0_MEM_CAL_DRVUP_DEFAULT                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_ASYNC_MEMPADCAL1_0_MEM_CAL_DRVUP_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define APB_MISC_ASYNC_MEMPADCAL1_0_MEM_CAL_DRVUP_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_MEMPADCAL1_0_MEM_CAL_DRVUP_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_ASYNC_MEMPADCAL1_0_MEM_CAL_DRVUP_SLWF_SHIFT                    _MK_SHIFT_CONST(13)
+#define APB_MISC_ASYNC_MEMPADCAL1_0_MEM_CAL_DRVUP_SLWF_FIELD                    (_MK_MASK_CONST(0x3) << APB_MISC_ASYNC_MEMPADCAL1_0_MEM_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_ASYNC_MEMPADCAL1_0_MEM_CAL_DRVUP_SLWF_RANGE                    14:13
+#define APB_MISC_ASYNC_MEMPADCAL1_0_MEM_CAL_DRVUP_SLWF_WOFFSET                  0x0
+#define APB_MISC_ASYNC_MEMPADCAL1_0_MEM_CAL_DRVUP_SLWF_DEFAULT                  _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_MEMPADCAL1_0_MEM_CAL_DRVUP_SLWF_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_MEMPADCAL1_0_MEM_CAL_DRVUP_SLWF_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_MEMPADCAL1_0_MEM_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_ASYNC_LCDPADCTRL_0  
+#define APB_MISC_ASYNC_LCDPADCTRL_0                     _MK_ADDR_CONST(0x41c)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_WORD_COUNT                  0x1
+#define APB_MISC_ASYNC_LCDPADCTRL_0_RESET_VAL                   _MK_MASK_CONST(0xff0f1)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_RESET_MASK                  _MK_MASK_CONST(0xff5f1)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_READ_MASK                   _MK_MASK_CONST(0xff5f1)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_WRITE_MASK                  _MK_MASK_CONST(0xff5f1)
+// LCD 3.3V mode enable
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD_33V_EN_SHIFT                    _MK_SHIFT_CONST(0)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD_33V_EN_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_LCDPADCTRL_0_LCD_33V_EN_SHIFT)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD_33V_EN_RANGE                    0:0
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD_33V_EN_WOFFSET                  0x0
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD_33V_EN_DEFAULT                  _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD_33V_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD_33V_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD_33V_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD_33V_EN_DISABLE                  _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD_33V_EN_ENABLE                   _MK_ENUM_CONST(1)
+
+// LCD data pins high speed mode enable
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD0_DAT_HSM_EN_SHIFT                       _MK_SHIFT_CONST(4)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD0_DAT_HSM_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_LCDPADCTRL_0_LCD0_DAT_HSM_EN_SHIFT)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD0_DAT_HSM_EN_RANGE                       4:4
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD0_DAT_HSM_EN_WOFFSET                     0x0
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD0_DAT_HSM_EN_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD0_DAT_HSM_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD0_DAT_HSM_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD0_DAT_HSM_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD0_DAT_HSM_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD0_DAT_HSM_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// LCD data pins high speed mode enable
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD1_DAT_HSM_EN_SHIFT                       _MK_SHIFT_CONST(5)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD1_DAT_HSM_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_LCDPADCTRL_0_LCD1_DAT_HSM_EN_SHIFT)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD1_DAT_HSM_EN_RANGE                       5:5
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD1_DAT_HSM_EN_WOFFSET                     0x0
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD1_DAT_HSM_EN_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD1_DAT_HSM_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD1_DAT_HSM_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD1_DAT_HSM_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD1_DAT_HSM_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD1_DAT_HSM_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// LCD control pins high speed mode enable
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD0_CTRL_HSM_EN_SHIFT                      _MK_SHIFT_CONST(6)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD0_CTRL_HSM_EN_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_LCDPADCTRL_0_LCD0_CTRL_HSM_EN_SHIFT)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD0_CTRL_HSM_EN_RANGE                      6:6
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD0_CTRL_HSM_EN_WOFFSET                    0x0
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD0_CTRL_HSM_EN_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD0_CTRL_HSM_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD0_CTRL_HSM_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD0_CTRL_HSM_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD0_CTRL_HSM_EN_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD0_CTRL_HSM_EN_ENABLE                     _MK_ENUM_CONST(1)
+
+// LCD control pins high speed mode enable
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD1_CTRL_HSM_EN_SHIFT                      _MK_SHIFT_CONST(7)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD1_CTRL_HSM_EN_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_LCDPADCTRL_0_LCD1_CTRL_HSM_EN_SHIFT)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD1_CTRL_HSM_EN_RANGE                      7:7
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD1_CTRL_HSM_EN_WOFFSET                    0x0
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD1_CTRL_HSM_EN_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD1_CTRL_HSM_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD1_CTRL_HSM_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD1_CTRL_HSM_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD1_CTRL_HSM_EN_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD1_CTRL_HSM_EN_ENABLE                     _MK_ENUM_CONST(1)
+
+// LCD data pins schmidt enable
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD_DAT_SCHMT_EN_SHIFT                      _MK_SHIFT_CONST(8)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD_DAT_SCHMT_EN_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_LCDPADCTRL_0_LCD_DAT_SCHMT_EN_SHIFT)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD_DAT_SCHMT_EN_RANGE                      8:8
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD_DAT_SCHMT_EN_WOFFSET                    0x0
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD_DAT_SCHMT_EN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD_DAT_SCHMT_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD_DAT_SCHMT_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD_DAT_SCHMT_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD_DAT_SCHMT_EN_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD_DAT_SCHMT_EN_ENABLE                     _MK_ENUM_CONST(1)
+
+// LCD control pins schmidt enable
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD_CTRL_SCHMT_EN_SHIFT                     _MK_SHIFT_CONST(10)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD_CTRL_SCHMT_EN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_LCDPADCTRL_0_LCD_CTRL_SCHMT_EN_SHIFT)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD_CTRL_SCHMT_EN_RANGE                     10:10
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD_CTRL_SCHMT_EN_WOFFSET                   0x0
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD_CTRL_SCHMT_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD_CTRL_SCHMT_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD_CTRL_SCHMT_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD_CTRL_SCHMT_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD_CTRL_SCHMT_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD_CTRL_SCHMT_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// LCD data pins low power mode select
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD0_DAT_LPMD_SHIFT                 _MK_SHIFT_CONST(12)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD0_DAT_LPMD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_ASYNC_LCDPADCTRL_0_LCD0_DAT_LPMD_SHIFT)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD0_DAT_LPMD_RANGE                 13:12
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD0_DAT_LPMD_WOFFSET                       0x0
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD0_DAT_LPMD_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD0_DAT_LPMD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD0_DAT_LPMD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD0_DAT_LPMD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// LCD data pins low power mode select
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD1_DAT_LPMD_SHIFT                 _MK_SHIFT_CONST(14)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD1_DAT_LPMD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_ASYNC_LCDPADCTRL_0_LCD1_DAT_LPMD_SHIFT)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD1_DAT_LPMD_RANGE                 15:14
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD1_DAT_LPMD_WOFFSET                       0x0
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD1_DAT_LPMD_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD1_DAT_LPMD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD1_DAT_LPMD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD1_DAT_LPMD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// LCD control pins low power mode select
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD0_CTRL_LPMD_SHIFT                        _MK_SHIFT_CONST(16)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD0_CTRL_LPMD_FIELD                        (_MK_MASK_CONST(0x3) << APB_MISC_ASYNC_LCDPADCTRL_0_LCD0_CTRL_LPMD_SHIFT)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD0_CTRL_LPMD_RANGE                        17:16
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD0_CTRL_LPMD_WOFFSET                      0x0
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD0_CTRL_LPMD_DEFAULT                      _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD0_CTRL_LPMD_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD0_CTRL_LPMD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD0_CTRL_LPMD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// LCD control pins low power mode select
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD1_CTRL_LPMD_SHIFT                        _MK_SHIFT_CONST(18)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD1_CTRL_LPMD_FIELD                        (_MK_MASK_CONST(0x3) << APB_MISC_ASYNC_LCDPADCTRL_0_LCD1_CTRL_LPMD_SHIFT)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD1_CTRL_LPMD_RANGE                        19:18
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD1_CTRL_LPMD_WOFFSET                      0x0
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD1_CTRL_LPMD_DEFAULT                      _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD1_CTRL_LPMD_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD1_CTRL_LPMD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD1_CTRL_LPMD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_ASYNC_LCDPADCAL1_0  
+#define APB_MISC_ASYNC_LCDPADCAL1_0                     _MK_ADDR_CONST(0x420)
+#define APB_MISC_ASYNC_LCDPADCAL1_0_WORD_COUNT                  0x1
+#define APB_MISC_ASYNC_LCDPADCAL1_0_RESET_VAL                   _MK_MASK_CONST(0x7f7f)
+#define APB_MISC_ASYNC_LCDPADCAL1_0_RESET_MASK                  _MK_MASK_CONST(0x7f7f)
+#define APB_MISC_ASYNC_LCDPADCAL1_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_LCDPADCAL1_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_LCDPADCAL1_0_READ_MASK                   _MK_MASK_CONST(0x7f7f)
+#define APB_MISC_ASYNC_LCDPADCAL1_0_WRITE_MASK                  _MK_MASK_CONST(0x7f7f)
+#define APB_MISC_ASYNC_LCDPADCAL1_0_LCD_CAL_DRVDN_SHIFT                 _MK_SHIFT_CONST(0)
+#define APB_MISC_ASYNC_LCDPADCAL1_0_LCD_CAL_DRVDN_FIELD                 (_MK_MASK_CONST(0x1f) << APB_MISC_ASYNC_LCDPADCAL1_0_LCD_CAL_DRVDN_SHIFT)
+#define APB_MISC_ASYNC_LCDPADCAL1_0_LCD_CAL_DRVDN_RANGE                 4:0
+#define APB_MISC_ASYNC_LCDPADCAL1_0_LCD_CAL_DRVDN_WOFFSET                       0x0
+#define APB_MISC_ASYNC_LCDPADCAL1_0_LCD_CAL_DRVDN_DEFAULT                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_ASYNC_LCDPADCAL1_0_LCD_CAL_DRVDN_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define APB_MISC_ASYNC_LCDPADCAL1_0_LCD_CAL_DRVDN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_LCDPADCAL1_0_LCD_CAL_DRVDN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_ASYNC_LCDPADCAL1_0_LCD_CAL_DRVDN_SLWR_SHIFT                    _MK_SHIFT_CONST(5)
+#define APB_MISC_ASYNC_LCDPADCAL1_0_LCD_CAL_DRVDN_SLWR_FIELD                    (_MK_MASK_CONST(0x3) << APB_MISC_ASYNC_LCDPADCAL1_0_LCD_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_ASYNC_LCDPADCAL1_0_LCD_CAL_DRVDN_SLWR_RANGE                    6:5
+#define APB_MISC_ASYNC_LCDPADCAL1_0_LCD_CAL_DRVDN_SLWR_WOFFSET                  0x0
+#define APB_MISC_ASYNC_LCDPADCAL1_0_LCD_CAL_DRVDN_SLWR_DEFAULT                  _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_LCDPADCAL1_0_LCD_CAL_DRVDN_SLWR_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_LCDPADCAL1_0_LCD_CAL_DRVDN_SLWR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_LCDPADCAL1_0_LCD_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_ASYNC_LCDPADCAL1_0_LCD_CAL_DRVUP_SHIFT                 _MK_SHIFT_CONST(8)
+#define APB_MISC_ASYNC_LCDPADCAL1_0_LCD_CAL_DRVUP_FIELD                 (_MK_MASK_CONST(0x1f) << APB_MISC_ASYNC_LCDPADCAL1_0_LCD_CAL_DRVUP_SHIFT)
+#define APB_MISC_ASYNC_LCDPADCAL1_0_LCD_CAL_DRVUP_RANGE                 12:8
+#define APB_MISC_ASYNC_LCDPADCAL1_0_LCD_CAL_DRVUP_WOFFSET                       0x0
+#define APB_MISC_ASYNC_LCDPADCAL1_0_LCD_CAL_DRVUP_DEFAULT                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_ASYNC_LCDPADCAL1_0_LCD_CAL_DRVUP_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define APB_MISC_ASYNC_LCDPADCAL1_0_LCD_CAL_DRVUP_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_LCDPADCAL1_0_LCD_CAL_DRVUP_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_ASYNC_LCDPADCAL1_0_LCD_CAL_DRVUP_SLWF_SHIFT                    _MK_SHIFT_CONST(13)
+#define APB_MISC_ASYNC_LCDPADCAL1_0_LCD_CAL_DRVUP_SLWF_FIELD                    (_MK_MASK_CONST(0x3) << APB_MISC_ASYNC_LCDPADCAL1_0_LCD_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_ASYNC_LCDPADCAL1_0_LCD_CAL_DRVUP_SLWF_RANGE                    14:13
+#define APB_MISC_ASYNC_LCDPADCAL1_0_LCD_CAL_DRVUP_SLWF_WOFFSET                  0x0
+#define APB_MISC_ASYNC_LCDPADCAL1_0_LCD_CAL_DRVUP_SLWF_DEFAULT                  _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_LCDPADCAL1_0_LCD_CAL_DRVUP_SLWF_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_LCDPADCAL1_0_LCD_CAL_DRVUP_SLWF_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_LCDPADCAL1_0_LCD_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_ASYNC_VIPADCTRL_0  
+#define APB_MISC_ASYNC_VIPADCTRL_0                      _MK_ADDR_CONST(0x424)
+#define APB_MISC_ASYNC_VIPADCTRL_0_WORD_COUNT                   0x1
+#define APB_MISC_ASYNC_VIPADCTRL_0_RESET_VAL                    _MK_MASK_CONST(0x33051)
+#define APB_MISC_ASYNC_VIPADCTRL_0_RESET_MASK                   _MK_MASK_CONST(0x33551)
+#define APB_MISC_ASYNC_VIPADCTRL_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_VIPADCTRL_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_VIPADCTRL_0_READ_MASK                    _MK_MASK_CONST(0x33551)
+#define APB_MISC_ASYNC_VIPADCTRL_0_WRITE_MASK                   _MK_MASK_CONST(0x33551)
+// VI 3.3V mode enable
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_33V_EN_SHIFT                      _MK_SHIFT_CONST(0)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_33V_EN_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_VIPADCTRL_0_VI_33V_EN_SHIFT)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_33V_EN_RANGE                      0:0
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_33V_EN_WOFFSET                    0x0
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_33V_EN_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_33V_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_33V_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_33V_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_33V_EN_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_33V_EN_ENABLE                     _MK_ENUM_CONST(1)
+
+// VI data pins high speed mode enable
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_DAT_HSM_EN_SHIFT                  _MK_SHIFT_CONST(4)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_DAT_HSM_EN_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_VIPADCTRL_0_VI_DAT_HSM_EN_SHIFT)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_DAT_HSM_EN_RANGE                  4:4
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_DAT_HSM_EN_WOFFSET                        0x0
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_DAT_HSM_EN_DEFAULT                        _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_DAT_HSM_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_DAT_HSM_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_DAT_HSM_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_DAT_HSM_EN_DISABLE                        _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_DAT_HSM_EN_ENABLE                 _MK_ENUM_CONST(1)
+
+// VI control pins high speed mode enable
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_CTRL_HSM_EN_SHIFT                 _MK_SHIFT_CONST(6)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_CTRL_HSM_EN_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_VIPADCTRL_0_VI_CTRL_HSM_EN_SHIFT)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_CTRL_HSM_EN_RANGE                 6:6
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_CTRL_HSM_EN_WOFFSET                       0x0
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_CTRL_HSM_EN_DEFAULT                       _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_CTRL_HSM_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_CTRL_HSM_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_CTRL_HSM_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_CTRL_HSM_EN_DISABLE                       _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_CTRL_HSM_EN_ENABLE                        _MK_ENUM_CONST(1)
+
+// VI data pins schmidt enable
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_DAT_SCHMT_EN_SHIFT                        _MK_SHIFT_CONST(8)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_DAT_SCHMT_EN_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_VIPADCTRL_0_VI_DAT_SCHMT_EN_SHIFT)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_DAT_SCHMT_EN_RANGE                        8:8
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_DAT_SCHMT_EN_WOFFSET                      0x0
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_DAT_SCHMT_EN_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_DAT_SCHMT_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_DAT_SCHMT_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_DAT_SCHMT_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_DAT_SCHMT_EN_DISABLE                      _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_DAT_SCHMT_EN_ENABLE                       _MK_ENUM_CONST(1)
+
+// VI control pins schmidt enable
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_CTRL_SCHMT_EN_SHIFT                       _MK_SHIFT_CONST(10)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_CTRL_SCHMT_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_VIPADCTRL_0_VI_CTRL_SCHMT_EN_SHIFT)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_CTRL_SCHMT_EN_RANGE                       10:10
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_CTRL_SCHMT_EN_WOFFSET                     0x0
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_CTRL_SCHMT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_CTRL_SCHMT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_CTRL_SCHMT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_CTRL_SCHMT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_CTRL_SCHMT_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_CTRL_SCHMT_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// VI data pins low power mode select
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_DAT_LPMD_SHIFT                    _MK_SHIFT_CONST(12)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_DAT_LPMD_FIELD                    (_MK_MASK_CONST(0x3) << APB_MISC_ASYNC_VIPADCTRL_0_VI_DAT_LPMD_SHIFT)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_DAT_LPMD_RANGE                    13:12
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_DAT_LPMD_WOFFSET                  0x0
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_DAT_LPMD_DEFAULT                  _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_DAT_LPMD_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_DAT_LPMD_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_DAT_LPMD_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// VI control pins low power mode select
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_CTRL_LPMD_SHIFT                   _MK_SHIFT_CONST(16)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_CTRL_LPMD_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_ASYNC_VIPADCTRL_0_VI_CTRL_LPMD_SHIFT)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_CTRL_LPMD_RANGE                   17:16
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_CTRL_LPMD_WOFFSET                 0x0
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_CTRL_LPMD_DEFAULT                 _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_CTRL_LPMD_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_CTRL_LPMD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_CTRL_LPMD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_ASYNC_VIPADCAL1_0  
+#define APB_MISC_ASYNC_VIPADCAL1_0                      _MK_ADDR_CONST(0x428)
+#define APB_MISC_ASYNC_VIPADCAL1_0_WORD_COUNT                   0x1
+#define APB_MISC_ASYNC_VIPADCAL1_0_RESET_VAL                    _MK_MASK_CONST(0x7f7f)
+#define APB_MISC_ASYNC_VIPADCAL1_0_RESET_MASK                   _MK_MASK_CONST(0x7f7f)
+#define APB_MISC_ASYNC_VIPADCAL1_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_VIPADCAL1_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_VIPADCAL1_0_READ_MASK                    _MK_MASK_CONST(0x7f7f)
+#define APB_MISC_ASYNC_VIPADCAL1_0_WRITE_MASK                   _MK_MASK_CONST(0x7f7f)
+#define APB_MISC_ASYNC_VIPADCAL1_0_VI_CAL_DRVDN_SHIFT                   _MK_SHIFT_CONST(0)
+#define APB_MISC_ASYNC_VIPADCAL1_0_VI_CAL_DRVDN_FIELD                   (_MK_MASK_CONST(0x1f) << APB_MISC_ASYNC_VIPADCAL1_0_VI_CAL_DRVDN_SHIFT)
+#define APB_MISC_ASYNC_VIPADCAL1_0_VI_CAL_DRVDN_RANGE                   4:0
+#define APB_MISC_ASYNC_VIPADCAL1_0_VI_CAL_DRVDN_WOFFSET                 0x0
+#define APB_MISC_ASYNC_VIPADCAL1_0_VI_CAL_DRVDN_DEFAULT                 _MK_MASK_CONST(0x1f)
+#define APB_MISC_ASYNC_VIPADCAL1_0_VI_CAL_DRVDN_DEFAULT_MASK                    _MK_MASK_CONST(0x1f)
+#define APB_MISC_ASYNC_VIPADCAL1_0_VI_CAL_DRVDN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_VIPADCAL1_0_VI_CAL_DRVDN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define APB_MISC_ASYNC_VIPADCAL1_0_VI_CAL_DRVDN_SLWR_SHIFT                      _MK_SHIFT_CONST(5)
+#define APB_MISC_ASYNC_VIPADCAL1_0_VI_CAL_DRVDN_SLWR_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_ASYNC_VIPADCAL1_0_VI_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_ASYNC_VIPADCAL1_0_VI_CAL_DRVDN_SLWR_RANGE                      6:5
+#define APB_MISC_ASYNC_VIPADCAL1_0_VI_CAL_DRVDN_SLWR_WOFFSET                    0x0
+#define APB_MISC_ASYNC_VIPADCAL1_0_VI_CAL_DRVDN_SLWR_DEFAULT                    _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_VIPADCAL1_0_VI_CAL_DRVDN_SLWR_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_VIPADCAL1_0_VI_CAL_DRVDN_SLWR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_VIPADCAL1_0_VI_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_ASYNC_VIPADCAL1_0_VI_CAL_DRVUP_SHIFT                   _MK_SHIFT_CONST(8)
+#define APB_MISC_ASYNC_VIPADCAL1_0_VI_CAL_DRVUP_FIELD                   (_MK_MASK_CONST(0x1f) << APB_MISC_ASYNC_VIPADCAL1_0_VI_CAL_DRVUP_SHIFT)
+#define APB_MISC_ASYNC_VIPADCAL1_0_VI_CAL_DRVUP_RANGE                   12:8
+#define APB_MISC_ASYNC_VIPADCAL1_0_VI_CAL_DRVUP_WOFFSET                 0x0
+#define APB_MISC_ASYNC_VIPADCAL1_0_VI_CAL_DRVUP_DEFAULT                 _MK_MASK_CONST(0x1f)
+#define APB_MISC_ASYNC_VIPADCAL1_0_VI_CAL_DRVUP_DEFAULT_MASK                    _MK_MASK_CONST(0x1f)
+#define APB_MISC_ASYNC_VIPADCAL1_0_VI_CAL_DRVUP_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_VIPADCAL1_0_VI_CAL_DRVUP_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define APB_MISC_ASYNC_VIPADCAL1_0_VI_CAL_DRVUP_SLWF_SHIFT                      _MK_SHIFT_CONST(13)
+#define APB_MISC_ASYNC_VIPADCAL1_0_VI_CAL_DRVUP_SLWF_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_ASYNC_VIPADCAL1_0_VI_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_ASYNC_VIPADCAL1_0_VI_CAL_DRVUP_SLWF_RANGE                      14:13
+#define APB_MISC_ASYNC_VIPADCAL1_0_VI_CAL_DRVUP_SLWF_WOFFSET                    0x0
+#define APB_MISC_ASYNC_VIPADCAL1_0_VI_CAL_DRVUP_SLWF_DEFAULT                    _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_VIPADCAL1_0_VI_CAL_DRVUP_SLWF_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_VIPADCAL1_0_VI_CAL_DRVUP_SLWF_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_VIPADCAL1_0_VI_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_ASYNC_VCLKCTRL_0  
+#define APB_MISC_ASYNC_VCLKCTRL_0                       _MK_ADDR_CONST(0x42c)
+#define APB_MISC_ASYNC_VCLKCTRL_0_WORD_COUNT                    0x1
+#define APB_MISC_ASYNC_VCLKCTRL_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_VCLKCTRL_0_RESET_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_VCLKCTRL_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_VCLKCTRL_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_VCLKCTRL_0_READ_MASK                     _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_VCLKCTRL_0_WRITE_MASK                    _MK_MASK_CONST(0x3)
+// VCLK input enable
+#define APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_IE_SHIFT                     _MK_SHIFT_CONST(0)
+#define APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_IE_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_IE_SHIFT)
+#define APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_IE_RANGE                     0:0
+#define APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_IE_WOFFSET                   0x0
+#define APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_IE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_IE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_IE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_IE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_IE_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_IE_ENABLE                    _MK_ENUM_CONST(1)
+
+// VCLK invert enable
+#define APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_INVERSION_SHIFT                      _MK_SHIFT_CONST(1)
+#define APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_INVERSION_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_INVERSION_SHIFT)
+#define APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_INVERSION_RANGE                      1:1
+#define APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_INVERSION_WOFFSET                    0x0
+#define APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_INVERSION_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_INVERSION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_INVERSION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_INVERSION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_INVERSION_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_INVERSION_ENABLE                     _MK_ENUM_CONST(1)
+
+
+// Reserved address 1072 [0x430] 
+
+// Reserved address 1076 [0x434] 
+
+// Register APB_MISC_ASYNC_TVDACVHSYNCCTRL_0  
+#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0                        _MK_ADDR_CONST(0x438)
+#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_WORD_COUNT                     0x1
+#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_RESET_MASK                     _MK_MASK_CONST(0xf)
+#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_READ_MASK                      _MK_MASK_CONST(0xf)
+#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_WRITE_MASK                     _MK_MASK_CONST(0xf)
+#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_TVDAC_HSYNCDLY_SHIFT                   _MK_SHIFT_CONST(0)
+#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_TVDAC_HSYNCDLY_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_TVDAC_HSYNCDLY_SHIFT)
+#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_TVDAC_HSYNCDLY_RANGE                   1:0
+#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_TVDAC_HSYNCDLY_WOFFSET                 0x0
+#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_TVDAC_HSYNCDLY_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_TVDAC_HSYNCDLY_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_TVDAC_HSYNCDLY_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_TVDAC_HSYNCDLY_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_TVDAC_VSYNCDLY_SHIFT                   _MK_SHIFT_CONST(2)
+#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_TVDAC_VSYNCDLY_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_TVDAC_VSYNCDLY_SHIFT)
+#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_TVDAC_VSYNCDLY_RANGE                   3:2
+#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_TVDAC_VSYNCDLY_WOFFSET                 0x0
+#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_TVDAC_VSYNCDLY_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_TVDAC_VSYNCDLY_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_TVDAC_VSYNCDLY_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_TVDAC_VSYNCDLY_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_ASYNC_TVDACCNTL_0  
+#define APB_MISC_ASYNC_TVDACCNTL_0                      _MK_ADDR_CONST(0x43c)
+#define APB_MISC_ASYNC_TVDACCNTL_0_WORD_COUNT                   0x1
+#define APB_MISC_ASYNC_TVDACCNTL_0_RESET_VAL                    _MK_MASK_CONST(0x83b)
+#define APB_MISC_ASYNC_TVDACCNTL_0_RESET_MASK                   _MK_MASK_CONST(0x1effffff)
+#define APB_MISC_ASYNC_TVDACCNTL_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_READ_MASK                    _MK_MASK_CONST(0x1effffff)
+#define APB_MISC_ASYNC_TVDACCNTL_0_WRITE_MASK                   _MK_MASK_CONST(0x1effffff)
+// Power down everything including the band-gap
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_IDDQ_SHIFT                       _MK_SHIFT_CONST(0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_IDDQ_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_TVDACCNTL_0_DAC_IDDQ_SHIFT)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_IDDQ_RANGE                       0:0
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_IDDQ_WOFFSET                     0x0
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_IDDQ_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_IDDQ_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_IDDQ_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_IDDQ_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_IDDQ_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_IDDQ_ENABLE                      _MK_ENUM_CONST(1)
+
+// Power down everything except the band-gap
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_POWERDOWN_SHIFT                  _MK_SHIFT_CONST(1)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_POWERDOWN_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_TVDACCNTL_0_DAC_POWERDOWN_SHIFT)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_POWERDOWN_RANGE                  1:1
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_POWERDOWN_WOFFSET                        0x0
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_POWERDOWN_DEFAULT                        _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_POWERDOWN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_POWERDOWN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_POWERDOWN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_POWERDOWN_DISABLE                        _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_POWERDOWN_ENABLE                 _MK_ENUM_CONST(1)
+
+// Power down everything including the band-gap
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_DETECT_EN_SHIFT                  _MK_SHIFT_CONST(2)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_DETECT_EN_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_TVDACCNTL_0_DAC_DETECT_EN_SHIFT)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_DETECT_EN_RANGE                  2:2
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_DETECT_EN_WOFFSET                        0x0
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_DETECT_EN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_DETECT_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_DETECT_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_DETECT_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_DETECT_EN_DISABLE                        _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_DETECT_EN_ENABLE                 _MK_ENUM_CONST(1)
+
+// Low power (sleep) mode. SHut down OUTR output
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPR_SHIFT                     _MK_SHIFT_CONST(3)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPR_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPR_SHIFT)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPR_RANGE                     3:3
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPR_WOFFSET                   0x0
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPR_DEFAULT                   _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPR_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPR_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPR_ENABLE                    _MK_ENUM_CONST(1)
+
+// Low power (sleep) mode. SHut down OUTG output
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPG_SHIFT                     _MK_SHIFT_CONST(4)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPG_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPG_SHIFT)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPG_RANGE                     4:4
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPG_WOFFSET                   0x0
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPG_DEFAULT                   _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPG_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPG_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPG_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPG_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPG_ENABLE                    _MK_ENUM_CONST(1)
+
+// Low power (sleep) mode. SHut down OUTB output
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPB_SHIFT                     _MK_SHIFT_CONST(5)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPB_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPB_SHIFT)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPB_RANGE                     5:5
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPB_WOFFSET                   0x0
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPB_DEFAULT                   _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPB_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPB_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPB_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPB_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPB_ENABLE                    _MK_ENUM_CONST(1)
+
+// Adjust threshold voltage of comparator inside DAC
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMP_TH_SHIFT                    _MK_SHIFT_CONST(6)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMP_TH_FIELD                    (_MK_MASK_CONST(0x3) << APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMP_TH_SHIFT)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMP_TH_RANGE                    7:6
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMP_TH_WOFFSET                  0x0
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMP_TH_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMP_TH_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMP_TH_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMP_TH_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Turn bandgap averaging on/off
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_AVG_ON_SHIFT                        _MK_SHIFT_CONST(8)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_AVG_ON_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_AVG_ON_SHIFT)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_AVG_ON_RANGE                        8:8
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_AVG_ON_WOFFSET                      0x0
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_AVG_ON_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_AVG_ON_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_AVG_ON_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_AVG_ON_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_AVG_ON_DISABLE                      _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_AVG_ON_ENABLE                       _MK_ENUM_CONST(1)
+
+// To adjust temp coeff
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_CURVE_SHIFT                 _MK_SHIFT_CONST(9)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_CURVE_FIELD                 (_MK_MASK_CONST(0x7) << APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_CURVE_SHIFT)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_CURVE_RANGE                 11:9
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_CURVE_WOFFSET                       0x0
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_CURVE_DEFAULT                       _MK_MASK_CONST(0x4)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_CURVE_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_CURVE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_CURVE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Control bits for bandgap
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_CNTL_SHIFT                  _MK_SHIFT_CONST(12)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_CNTL_FIELD                  (_MK_MASK_CONST(0xf) << APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_CNTL_SHIFT)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_CNTL_RANGE                  15:12
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_CNTL_WOFFSET                        0x0
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_CNTL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_CNTL_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_CNTL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_CNTL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// For debugging. Selects internal analog output to be sent out of VREF pin
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_ATEST_SHIFT                      _MK_SHIFT_CONST(16)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_ATEST_FIELD                      (_MK_MASK_CONST(0x7) << APB_MISC_ASYNC_TVDACCNTL_0_DAC_ATEST_SHIFT)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_ATEST_RANGE                      18:16
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_ATEST_WOFFSET                    0x0
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_ATEST_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_ATEST_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_ATEST_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_ATEST_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Reserved for additional control
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_CNTL_SHIFT                       _MK_SHIFT_CONST(19)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_CNTL_FIELD                       (_MK_MASK_CONST(0x1f) << APB_MISC_ASYNC_TVDACCNTL_0_DAC_CNTL_SHIFT)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_CNTL_RANGE                       23:19
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_CNTL_WOFFSET                     0x0
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_CNTL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_CNTL_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_CNTL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_CNTL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Enable COMPOUTR output
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPR_EN_SHIFT                   _MK_SHIFT_CONST(25)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPR_EN_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPR_EN_SHIFT)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPR_EN_RANGE                   25:25
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPR_EN_WOFFSET                 0x0
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPR_EN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPR_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPR_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPR_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPR_EN_DISABLE                 _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPR_EN_ENABLE                  _MK_ENUM_CONST(1)
+
+// Enable COMPOUTG output
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPG_EN_SHIFT                   _MK_SHIFT_CONST(26)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPG_EN_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPG_EN_SHIFT)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPG_EN_RANGE                   26:26
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPG_EN_WOFFSET                 0x0
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPG_EN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPG_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPG_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPG_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPG_EN_DISABLE                 _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPG_EN_ENABLE                  _MK_ENUM_CONST(1)
+
+// Enable COMPOUTB output
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPB_EN_SHIFT                   _MK_SHIFT_CONST(27)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPB_EN_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPB_EN_SHIFT)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPB_EN_RANGE                   27:27
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPB_EN_WOFFSET                 0x0
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPB_EN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPB_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPB_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPB_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPB_EN_DISABLE                 _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPB_EN_ENABLE                  _MK_ENUM_CONST(1)
+
+// Indicate load status
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_PLUG_OK_SHIFT                    _MK_SHIFT_CONST(28)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_PLUG_OK_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_TVDACCNTL_0_DAC_PLUG_OK_SHIFT)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_PLUG_OK_RANGE                    28:28
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_PLUG_OK_WOFFSET                  0x0
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_PLUG_OK_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_PLUG_OK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_PLUG_OK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_PLUG_OK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_PLUG_OK_UNLOADED                 _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_PLUG_OK_LOADED                   _MK_ENUM_CONST(1)
+
+
+// Register APB_MISC_ASYNC_TVDACSTATUS_0  
+#define APB_MISC_ASYNC_TVDACSTATUS_0                    _MK_ADDR_CONST(0x440)
+#define APB_MISC_ASYNC_TVDACSTATUS_0_WORD_COUNT                         0x1
+#define APB_MISC_ASYNC_TVDACSTATUS_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACSTATUS_0_RESET_MASK                         _MK_MASK_CONST(0x7)
+#define APB_MISC_ASYNC_TVDACSTATUS_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACSTATUS_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACSTATUS_0_READ_MASK                  _MK_MASK_CONST(0x7)
+#define APB_MISC_ASYNC_TVDACSTATUS_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
+// Channel R comparator output for auto-detect
+// 0 = COMPINR > threshold
+// 1 = COMPINR < threshold, or when POWERDOWN==1
+// comparison threshold = 0.325V
+#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTR_SHIFT                 _MK_SHIFT_CONST(0)
+#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTR_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTR_SHIFT)
+#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTR_RANGE                 0:0
+#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTR_WOFFSET                       0x0
+#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTR_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Channel G comparator output for auto-detect
+// 0 = COMPING > threshold
+// 1 = COMPING < threshold, or when POWERDOWN==1
+// comparison threshold = 0.325V
+#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTG_SHIFT                 _MK_SHIFT_CONST(1)
+#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTG_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTG_SHIFT)
+#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTG_RANGE                 1:1
+#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTG_WOFFSET                       0x0
+#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTG_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTG_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTG_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTG_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Channel B comparator output for auto-detect
+// 0 = COMPINB > threshold
+// 1 = COMPINB < threshold, or when POWERDOWN==1
+// comparison threshold = 0.325V
+#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTB_SHIFT                 _MK_SHIFT_CONST(2)
+#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTB_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTB_SHIFT)
+#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTB_RANGE                 2:2
+#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTB_WOFFSET                       0x0
+#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTB_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTB_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTB_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTB_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_ASYNC_TVDACDINCONFIG_0  
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0                 _MK_ADDR_CONST(0x444)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_WORD_COUNT                      0x1
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_RESET_VAL                       _MK_MASK_CONST(0x2)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_RESET_MASK                      _MK_MASK_CONST(0xffffd37)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_READ_MASK                       _MK_MASK_CONST(0xffffd37)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_WRITE_MASK                      _MK_MASK_CONST(0xffffd37)
+// Data Input FIFO threshold
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_FIFO_TH_SHIFT                       _MK_SHIFT_CONST(0)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_FIFO_TH_FIELD                       (_MK_MASK_CONST(0x7) << APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_FIFO_TH_SHIFT)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_FIFO_TH_RANGE                       2:0
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_FIFO_TH_WOFFSET                     0x0
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_FIFO_TH_DEFAULT                     _MK_MASK_CONST(0x2)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_FIFO_TH_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_FIFO_TH_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_FIFO_TH_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// INPUT source for TVDAC
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_SOURCE_SHIFT                        _MK_SHIFT_CONST(4)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_SOURCE_FIELD                        (_MK_MASK_CONST(0x3) << APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_SOURCE_SHIFT)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_SOURCE_RANGE                        5:4
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_SOURCE_WOFFSET                      0x0
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_SOURCE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_SOURCE_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_SOURCE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_SOURCE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_SOURCE_TVDAC_OFF                    _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_SOURCE_TVO                  _MK_ENUM_CONST(1)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_SOURCE_DISPLAY                      _MK_ENUM_CONST(2)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_SOURCE_DISPLAYB                     _MK_ENUM_CONST(3)
+
+// Override DAC DIN inputs
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_DIN_ORIDE_EN_SHIFT                  _MK_SHIFT_CONST(8)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_DIN_ORIDE_EN_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_DIN_ORIDE_EN_SHIFT)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_DIN_ORIDE_EN_RANGE                  8:8
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_DIN_ORIDE_EN_WOFFSET                        0x0
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_DIN_ORIDE_EN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_DIN_ORIDE_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_DIN_ORIDE_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_DIN_ORIDE_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_DIN_ORIDE_EN_DISABLE                        _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_DIN_ORIDE_EN_ENABLE                 _MK_ENUM_CONST(1)
+
+// DIN override
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_DIN_ORIDE_SHIFT                     _MK_SHIFT_CONST(10)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_DIN_ORIDE_FIELD                     (_MK_MASK_CONST(0x3ff) << APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_DIN_ORIDE_SHIFT)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_DIN_ORIDE_RANGE                     19:10
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_DIN_ORIDE_WOFFSET                   0x0
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_DIN_ORIDE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_DIN_ORIDE_DEFAULT_MASK                      _MK_MASK_CONST(0x3ff)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_DIN_ORIDE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_DIN_ORIDE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// AMPIN
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_AMPIN_SHIFT                 _MK_SHIFT_CONST(20)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_AMPIN_FIELD                 (_MK_MASK_CONST(0xff) << APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_AMPIN_SHIFT)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_AMPIN_RANGE                 27:20
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_AMPIN_WOFFSET                       0x0
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_AMPIN_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_AMPIN_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_AMPIN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_AMPIN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_ASYNC_INT_STATUS_0  // Interrupt Status
+//  This reflects status of all pending
+//  interrupts which is valid as long as
+//  the interrupt is not cleared even if the
+//  interrupt is masked. A pending interrupt
+//  can be cleared by writing a '1' to this
+//  the corresponding interrupt status bit
+//  in this register.
+//        0       rt  HGP0_INT_STATUS          // HGP0 Interrupt Status
+//                                             //  (this is cleared on write)
+//                                             //   0= interrupt not pending
+//                                             //   1= interrupt pending
+//        1       rt  HGP1_INT_STATUS          // HGP1 Interrupt Status
+//                                             //  (this is cleared on write)
+//                                             //   0= interrupt not pending
+//                                            //   1= interrupt pending
+//      2       rt  HGP2_INT_STATUS          // HGP2 Interrupt Status
+//                                          //  (this is cleared on write)
+//                                           //   0= interrupt not pending
+//                                           //   1= interrupt pending
+//      4       rt  HGP4_INT_STATUS          // HGP4 Interrupt Status
+//                                           //  (this is cleared on write)
+//                                           //   0= interrupt not pending
+//                                           //   1= interrupt pending
+//      5       rt  HGP5_INT_STATUS          // HGP5 Interrupt Status
+//                                           //  (this is cleared on write)
+//                                           //   0= interrupt not pending
+//                                           //   1= interrupt pending
+//      6       rt  HGP6_INT_STATUS          // HGP6 Interrupt Status
+//                                           //  (this is cleared on write)
+//                                           //   0= interrupt not pending
+//                                           //   1= interrupt pending
+#define APB_MISC_ASYNC_INT_STATUS_0                     _MK_ADDR_CONST(0x448)
+#define APB_MISC_ASYNC_INT_STATUS_0_WORD_COUNT                  0x1
+#define APB_MISC_ASYNC_INT_STATUS_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_STATUS_0_RESET_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_STATUS_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_STATUS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_STATUS_0_READ_MASK                   _MK_MASK_CONST(0x1f80)
+#define APB_MISC_ASYNC_INT_STATUS_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+// HGP7 Interrupt Status
+//  (this is cleared on write)
+//   0= interrupt not pending
+//   1= interrupt pending
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP7_INT_STATUS_SHIFT                       _MK_SHIFT_CONST(7)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP7_INT_STATUS_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_STATUS_0_HGP7_INT_STATUS_SHIFT)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP7_INT_STATUS_RANGE                       7:7
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP7_INT_STATUS_WOFFSET                     0x0
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP7_INT_STATUS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP7_INT_STATUS_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP7_INT_STATUS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP7_INT_STATUS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// HGP8 Interrupt Status
+//  (this is cleared on write)
+//   0= interrupt not pending
+//   1= interrupt pending
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP8_INT_STATUS_SHIFT                       _MK_SHIFT_CONST(8)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP8_INT_STATUS_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_STATUS_0_HGP8_INT_STATUS_SHIFT)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP8_INT_STATUS_RANGE                       8:8
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP8_INT_STATUS_WOFFSET                     0x0
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP8_INT_STATUS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP8_INT_STATUS_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP8_INT_STATUS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP8_INT_STATUS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// HGP9 Interrupt Status
+//  (this is cleared on write)
+//   0= interrupt not pending
+//   1= interrupt pending
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP9_INT_STATUS_SHIFT                       _MK_SHIFT_CONST(9)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP9_INT_STATUS_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_STATUS_0_HGP9_INT_STATUS_SHIFT)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP9_INT_STATUS_RANGE                       9:9
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP9_INT_STATUS_WOFFSET                     0x0
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP9_INT_STATUS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP9_INT_STATUS_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP9_INT_STATUS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP9_INT_STATUS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// HGP10 Interrupt Status
+//  (this is cleared on write)
+//   0= interrupt not pending
+//   1= interrupt pending
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP10_INT_STATUS_SHIFT                      _MK_SHIFT_CONST(10)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP10_INT_STATUS_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_STATUS_0_HGP10_INT_STATUS_SHIFT)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP10_INT_STATUS_RANGE                      10:10
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP10_INT_STATUS_WOFFSET                    0x0
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP10_INT_STATUS_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP10_INT_STATUS_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP10_INT_STATUS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP10_INT_STATUS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// HGP11 Interrupt Status
+//  (this is cleared on write)
+//   0= interrupt not pending
+//   1= interrupt pending
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP11_INT_STATUS_SHIFT                      _MK_SHIFT_CONST(11)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP11_INT_STATUS_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_STATUS_0_HGP11_INT_STATUS_SHIFT)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP11_INT_STATUS_RANGE                      11:11
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP11_INT_STATUS_WOFFSET                    0x0
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP11_INT_STATUS_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP11_INT_STATUS_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP11_INT_STATUS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP11_INT_STATUS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// HGP12 Interrupt Status
+//  (this is cleared on write)
+//   0= interrupt not pending
+//   1= interrupt pending
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP12_INT_STATUS_SHIFT                      _MK_SHIFT_CONST(12)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP12_INT_STATUS_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_STATUS_0_HGP12_INT_STATUS_SHIFT)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP12_INT_STATUS_RANGE                      12:12
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP12_INT_STATUS_WOFFSET                    0x0
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP12_INT_STATUS_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP12_INT_STATUS_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP12_INT_STATUS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP12_INT_STATUS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_ASYNC_INT_MASK_0  // Interrupt Mask
+// Setting bits in this register masked the
+//  corresponding interrupt but does not
+//  clear a pending interrupt and does not
+//  prevent a pending interrupt to be generated.
+//  Masking an interrupt also does not clear
+//  a pending interrupt status and does not
+//  a pending interrupt status to be generated.
+//      0       rw  HGP0_INT_MASK  i=0x0     // HGP0 Interrupt Mask
+//          enum ( MASKED, NOTMASKED )       //   0= interrupt masked
+//                                           //   1= interrupt not masked
+//      1       rw  HGP1_INT_MASK  i=0x0     // HGP1 Interrupt Mask
+//          enum ( MASKED, NOTMASKED )       //   0= interrupt masked
+//                                           //   1= interrupt not masked
+//      2       rw  HGP2_INT_MASK  i=0x0     // HGP2 Interrupt Mask
+//          enum ( MASKED, NOTMASKED )       //   0= interrupt masked
+//                                           //   1= interrupt not masked
+//      4       rw  HGP4_INT_MASK  i=0x0     // HGP4 Interrupt Mask
+//          enum ( MASKED, NOTMASKED )       //   0= interrupt masked
+//                                           //   1= interrupt not masked
+//      5       rw  HGP5_INT_MASK  i=0x0     // HGP5 Interrupt Mask
+//          enum ( MASKED, NOTMASKED )       //   0= interrupt masked
+//                                           //   1= interrupt not masked
+//      6       rw  HGP6_INT_MASK  i=0x0     // HGP6 Interrupt Mask
+//          enum ( MASKED, NOTMASKED )       //   0= interrupt masked
+//                                           //   1= interrupt not masked
+#define APB_MISC_ASYNC_INT_MASK_0                       _MK_ADDR_CONST(0x44c)
+#define APB_MISC_ASYNC_INT_MASK_0_WORD_COUNT                    0x1
+#define APB_MISC_ASYNC_INT_MASK_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_MASK_0_RESET_MASK                    _MK_MASK_CONST(0x1f80)
+#define APB_MISC_ASYNC_INT_MASK_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_MASK_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_MASK_0_READ_MASK                     _MK_MASK_CONST(0x1f80)
+#define APB_MISC_ASYNC_INT_MASK_0_WRITE_MASK                    _MK_MASK_CONST(0x1f80)
+// HGP7 Interrupt Mask   0= interrupt masked
+//   1= interrupt not masked
+#define APB_MISC_ASYNC_INT_MASK_0_HGP7_INT_MASK_SHIFT                   _MK_SHIFT_CONST(7)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP7_INT_MASK_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_MASK_0_HGP7_INT_MASK_SHIFT)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP7_INT_MASK_RANGE                   7:7
+#define APB_MISC_ASYNC_INT_MASK_0_HGP7_INT_MASK_WOFFSET                 0x0
+#define APB_MISC_ASYNC_INT_MASK_0_HGP7_INT_MASK_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP7_INT_MASK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP7_INT_MASK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP7_INT_MASK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP7_INT_MASK_MASKED                  _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP7_INT_MASK_NOTMASKED                       _MK_ENUM_CONST(1)
+
+// HGP8 Interrupt Mask   0= interrupt masked
+//   1= interrupt not masked
+#define APB_MISC_ASYNC_INT_MASK_0_HGP8_INT_MASK_SHIFT                   _MK_SHIFT_CONST(8)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP8_INT_MASK_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_MASK_0_HGP8_INT_MASK_SHIFT)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP8_INT_MASK_RANGE                   8:8
+#define APB_MISC_ASYNC_INT_MASK_0_HGP8_INT_MASK_WOFFSET                 0x0
+#define APB_MISC_ASYNC_INT_MASK_0_HGP8_INT_MASK_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP8_INT_MASK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP8_INT_MASK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP8_INT_MASK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP8_INT_MASK_MASKED                  _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP8_INT_MASK_NOTMASKED                       _MK_ENUM_CONST(1)
+
+// HGP9 Interrupt Mask   0= interrupt masked
+//   1= interrupt not masked
+#define APB_MISC_ASYNC_INT_MASK_0_HGP9_INT_MASK_SHIFT                   _MK_SHIFT_CONST(9)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP9_INT_MASK_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_MASK_0_HGP9_INT_MASK_SHIFT)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP9_INT_MASK_RANGE                   9:9
+#define APB_MISC_ASYNC_INT_MASK_0_HGP9_INT_MASK_WOFFSET                 0x0
+#define APB_MISC_ASYNC_INT_MASK_0_HGP9_INT_MASK_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP9_INT_MASK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP9_INT_MASK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP9_INT_MASK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP9_INT_MASK_MASKED                  _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP9_INT_MASK_NOTMASKED                       _MK_ENUM_CONST(1)
+
+// HGP10 Interrupt Mask   0= interrupt masked
+//   1= interrupt not masked
+#define APB_MISC_ASYNC_INT_MASK_0_HGP10_INT_MASK_SHIFT                  _MK_SHIFT_CONST(10)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP10_INT_MASK_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_MASK_0_HGP10_INT_MASK_SHIFT)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP10_INT_MASK_RANGE                  10:10
+#define APB_MISC_ASYNC_INT_MASK_0_HGP10_INT_MASK_WOFFSET                        0x0
+#define APB_MISC_ASYNC_INT_MASK_0_HGP10_INT_MASK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP10_INT_MASK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP10_INT_MASK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP10_INT_MASK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP10_INT_MASK_MASKED                 _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP10_INT_MASK_NOTMASKED                      _MK_ENUM_CONST(1)
+
+// HGP11 Interrupt Mask   0= interrupt masked
+//   1= interrupt not masked
+#define APB_MISC_ASYNC_INT_MASK_0_HGP11_INT_MASK_SHIFT                  _MK_SHIFT_CONST(11)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP11_INT_MASK_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_MASK_0_HGP11_INT_MASK_SHIFT)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP11_INT_MASK_RANGE                  11:11
+#define APB_MISC_ASYNC_INT_MASK_0_HGP11_INT_MASK_WOFFSET                        0x0
+#define APB_MISC_ASYNC_INT_MASK_0_HGP11_INT_MASK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP11_INT_MASK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP11_INT_MASK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP11_INT_MASK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP11_INT_MASK_MASKED                 _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP11_INT_MASK_NOTMASKED                      _MK_ENUM_CONST(1)
+
+// HGP12 Interrupt Mask   0= interrupt masked
+//   1= interrupt not masked
+#define APB_MISC_ASYNC_INT_MASK_0_HGP12_INT_MASK_SHIFT                  _MK_SHIFT_CONST(12)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP12_INT_MASK_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_MASK_0_HGP12_INT_MASK_SHIFT)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP12_INT_MASK_RANGE                  12:12
+#define APB_MISC_ASYNC_INT_MASK_0_HGP12_INT_MASK_WOFFSET                        0x0
+#define APB_MISC_ASYNC_INT_MASK_0_HGP12_INT_MASK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP12_INT_MASK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP12_INT_MASK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP12_INT_MASK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP12_INT_MASK_MASKED                 _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP12_INT_MASK_NOTMASKED                      _MK_ENUM_CONST(1)
+
+
+// Register APB_MISC_ASYNC_INT_POLARITY_0  // Interrupt Polarity
+//  These bits specify whether a pending interrupt 
+//  is generated on falling edge or on rising edge 
+//  of the corresponding input signal/event.
+//        0       rw  HGP0_INT_POLARITY  i=0x0  // HGP0 Interrupt Polarity
+//      enum ( LOW, HIGH )                    //   0= falling edge interrupt
+//                                            //   1= rising edge interrupt
+//      1       rw  HGP1_INT_POLARITY  i=0x0  // HGP1 Interrupt Polarity
+//      enum ( LOW, HIGH )                    //   0= falling edge interrupt
+//                                            //   1= rising edge interrupt
+//      2       rw  HGP2_INT_POLARITY  i=0x0  // HGP2 Interrupt Polarity
+//      enum ( LOW, HIGH )                    //   0= falling edge interrupt
+//                                            //   1= rising edge interrupt
+//      4       rw  HGP4_INT_POLARITY  i=0x0  // HGP4 Interrupt Polarity
+//      enum ( LOW, HIGH )                    //   0= falling edge interrupt
+//                                            //   1= rising edge interrupt
+//      5       rw  HGP5_INT_POLARITY  i=0x0  // HGP5 Interrupt Polarity
+//      enum ( LOW, HIGH )                    //   0= falling edge interrupt
+//                                            //   1= rising edge interrupt
+//      6       rw  HGP6_INT_POLARITY  i=0x0  // HGP6 Interrupt Polarity
+//      enum ( LOW, HIGH )                    //   0= falling edge interrupt
+//                                            //   1= rising edge interrupt
+#define APB_MISC_ASYNC_INT_POLARITY_0                   _MK_ADDR_CONST(0x450)
+#define APB_MISC_ASYNC_INT_POLARITY_0_WORD_COUNT                        0x1
+#define APB_MISC_ASYNC_INT_POLARITY_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_RESET_MASK                        _MK_MASK_CONST(0x1f80)
+#define APB_MISC_ASYNC_INT_POLARITY_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_READ_MASK                         _MK_MASK_CONST(0x1f80)
+#define APB_MISC_ASYNC_INT_POLARITY_0_WRITE_MASK                        _MK_MASK_CONST(0x1f80)
+// HGP7 Interrupt Polarity   0= falling edge interrupt
+//   1= rising edge interrupt
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP7_INT_POLARITY_SHIFT                   _MK_SHIFT_CONST(7)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP7_INT_POLARITY_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_POLARITY_0_HGP7_INT_POLARITY_SHIFT)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP7_INT_POLARITY_RANGE                   7:7
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP7_INT_POLARITY_WOFFSET                 0x0
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP7_INT_POLARITY_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP7_INT_POLARITY_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP7_INT_POLARITY_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP7_INT_POLARITY_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP7_INT_POLARITY_LOW                     _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP7_INT_POLARITY_HIGH                    _MK_ENUM_CONST(1)
+
+// HGP8 Interrupt Polarity   0= falling edge interrupt
+//   1= rising edge interrupt
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP8_INT_POLARITY_SHIFT                   _MK_SHIFT_CONST(8)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP8_INT_POLARITY_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_POLARITY_0_HGP8_INT_POLARITY_SHIFT)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP8_INT_POLARITY_RANGE                   8:8
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP8_INT_POLARITY_WOFFSET                 0x0
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP8_INT_POLARITY_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP8_INT_POLARITY_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP8_INT_POLARITY_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP8_INT_POLARITY_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP8_INT_POLARITY_LOW                     _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP8_INT_POLARITY_HIGH                    _MK_ENUM_CONST(1)
+
+// HGP9 Interrupt Polarity   0= falling edge interrupt
+//   1= rising edge interrupt
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP9_INT_POLARITY_SHIFT                   _MK_SHIFT_CONST(9)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP9_INT_POLARITY_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_POLARITY_0_HGP9_INT_POLARITY_SHIFT)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP9_INT_POLARITY_RANGE                   9:9
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP9_INT_POLARITY_WOFFSET                 0x0
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP9_INT_POLARITY_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP9_INT_POLARITY_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP9_INT_POLARITY_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP9_INT_POLARITY_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP9_INT_POLARITY_LOW                     _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP9_INT_POLARITY_HIGH                    _MK_ENUM_CONST(1)
+
+// HGP10 Interrupt Polarity   0= falling edge interrupt
+//   1= rising edge interrupt
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP10_INT_POLARITY_SHIFT                  _MK_SHIFT_CONST(10)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP10_INT_POLARITY_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_POLARITY_0_HGP10_INT_POLARITY_SHIFT)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP10_INT_POLARITY_RANGE                  10:10
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP10_INT_POLARITY_WOFFSET                        0x0
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP10_INT_POLARITY_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP10_INT_POLARITY_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP10_INT_POLARITY_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP10_INT_POLARITY_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP10_INT_POLARITY_LOW                    _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP10_INT_POLARITY_HIGH                   _MK_ENUM_CONST(1)
+
+// HGP11 Interrupt Polarity   0= falling edge interrupt
+//   1= rising edge interrupt
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP11_INT_POLARITY_SHIFT                  _MK_SHIFT_CONST(11)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP11_INT_POLARITY_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_POLARITY_0_HGP11_INT_POLARITY_SHIFT)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP11_INT_POLARITY_RANGE                  11:11
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP11_INT_POLARITY_WOFFSET                        0x0
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP11_INT_POLARITY_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP11_INT_POLARITY_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP11_INT_POLARITY_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP11_INT_POLARITY_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP11_INT_POLARITY_LOW                    _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP11_INT_POLARITY_HIGH                   _MK_ENUM_CONST(1)
+
+// HGP12 Interrupt Polarity   0= falling edge interrupt
+//   1= rising edge interrupt
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP12_INT_POLARITY_SHIFT                  _MK_SHIFT_CONST(12)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP12_INT_POLARITY_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_POLARITY_0_HGP12_INT_POLARITY_SHIFT)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP12_INT_POLARITY_RANGE                  12:12
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP12_INT_POLARITY_WOFFSET                        0x0
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP12_INT_POLARITY_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP12_INT_POLARITY_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP12_INT_POLARITY_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP12_INT_POLARITY_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP12_INT_POLARITY_LOW                    _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP12_INT_POLARITY_HIGH                   _MK_ENUM_CONST(1)
+
+
+// Register APB_MISC_ASYNC_INT_TYPE_SELECT_0  // Interrupt Type
+//  These bits specify whether an interrupt 
+//  is generated on an edge of a level type.
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0                        _MK_ADDR_CONST(0x454)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_WORD_COUNT                     0x1
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_RESET_MASK                     _MK_MASK_CONST(0x1f80)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_READ_MASK                      _MK_MASK_CONST(0x1f80)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_WRITE_MASK                     _MK_MASK_CONST(0x1f80)
+// HGP7 Interrupt Type   0= Edge type
+//   1= Level type
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP7_INT_TYPE_SHIFT                    _MK_SHIFT_CONST(7)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP7_INT_TYPE_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP7_INT_TYPE_SHIFT)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP7_INT_TYPE_RANGE                    7:7
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP7_INT_TYPE_WOFFSET                  0x0
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP7_INT_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP7_INT_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP7_INT_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP7_INT_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP7_INT_TYPE_EDGE                     _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP7_INT_TYPE_LEVEL                    _MK_ENUM_CONST(1)
+
+// HGP8 Interrupt Polarity   0= Edge type
+//   1= Level type
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP8_INT_TYPE_SHIFT                    _MK_SHIFT_CONST(8)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP8_INT_TYPE_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP8_INT_TYPE_SHIFT)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP8_INT_TYPE_RANGE                    8:8
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP8_INT_TYPE_WOFFSET                  0x0
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP8_INT_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP8_INT_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP8_INT_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP8_INT_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP8_INT_TYPE_EDGE                     _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP8_INT_TYPE_LEVEL                    _MK_ENUM_CONST(1)
+
+// HGP9 Interrupt Polarity   0= Edge type
+//   1= Level type
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP9_INT_TYPE_SHIFT                    _MK_SHIFT_CONST(9)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP9_INT_TYPE_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP9_INT_TYPE_SHIFT)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP9_INT_TYPE_RANGE                    9:9
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP9_INT_TYPE_WOFFSET                  0x0
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP9_INT_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP9_INT_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP9_INT_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP9_INT_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP9_INT_TYPE_EDGE                     _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP9_INT_TYPE_LEVEL                    _MK_ENUM_CONST(1)
+
+// HGP10 Interrupt Polarity   0= Edge type
+//   1= Level type
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP10_INT_TYPE_SHIFT                   _MK_SHIFT_CONST(10)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP10_INT_TYPE_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP10_INT_TYPE_SHIFT)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP10_INT_TYPE_RANGE                   10:10
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP10_INT_TYPE_WOFFSET                 0x0
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP10_INT_TYPE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP10_INT_TYPE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP10_INT_TYPE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP10_INT_TYPE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP10_INT_TYPE_EDGE                    _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP10_INT_TYPE_LEVEL                   _MK_ENUM_CONST(1)
+
+// HGP11 Interrupt Polarity   0= Edge type
+//   1= Level type
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP11_INT_TYPE_SHIFT                   _MK_SHIFT_CONST(11)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP11_INT_TYPE_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP11_INT_TYPE_SHIFT)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP11_INT_TYPE_RANGE                   11:11
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP11_INT_TYPE_WOFFSET                 0x0
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP11_INT_TYPE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP11_INT_TYPE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP11_INT_TYPE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP11_INT_TYPE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP11_INT_TYPE_EDGE                    _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP11_INT_TYPE_LEVEL                   _MK_ENUM_CONST(1)
+
+// HGP12 Interrupt Polarity   0= Edge type
+//   1= Level type
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP12_INT_TYPE_SHIFT                   _MK_SHIFT_CONST(12)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP12_INT_TYPE_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP12_INT_TYPE_SHIFT)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP12_INT_TYPE_RANGE                   12:12
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP12_INT_TYPE_WOFFSET                 0x0
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP12_INT_TYPE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP12_INT_TYPE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP12_INT_TYPE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP12_INT_TYPE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP12_INT_TYPE_EDGE                    _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP12_INT_TYPE_LEVEL                   _MK_ENUM_CONST(1)
+
+
+// Register APB_MISC_GP_MODEREG_0  
+#define APB_MISC_GP_MODEREG_0                   _MK_ADDR_CONST(0x800)
+#define APB_MISC_GP_MODEREG_0_WORD_COUNT                        0x1
+#define APB_MISC_GP_MODEREG_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_MODEREG_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_MODEREG_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_MODEREG_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_MODEREG_0_READ_MASK                         _MK_MASK_CONST(0x301)
+#define APB_MISC_GP_MODEREG_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+// Standby pad input 1 = STANDBYN is    asserted (low  voltage),                   0 = STANDBYN is desasserted (high voltage)
+#define APB_MISC_GP_MODEREG_0_STANDBY_IE_SHIFT                  _MK_SHIFT_CONST(0)
+#define APB_MISC_GP_MODEREG_0_STANDBY_IE_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_GP_MODEREG_0_STANDBY_IE_SHIFT)
+#define APB_MISC_GP_MODEREG_0_STANDBY_IE_RANGE                  0:0
+#define APB_MISC_GP_MODEREG_0_STANDBY_IE_WOFFSET                        0x0
+#define APB_MISC_GP_MODEREG_0_STANDBY_IE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_MODEREG_0_STANDBY_IE_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_MODEREG_0_STANDBY_IE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_MODEREG_0_STANDBY_IE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_MODEREG_0_STANDBY_IE_DEASSERTED                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_MODEREG_0_STANDBY_IE_ASSERTED                       _MK_ENUM_CONST(1)
+
+// LP-DDR Strap option bit 0.
+#define APB_MISC_GP_MODEREG_0_LPDDR_STRAP0_SHIFT                        _MK_SHIFT_CONST(8)
+#define APB_MISC_GP_MODEREG_0_LPDDR_STRAP0_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_MODEREG_0_LPDDR_STRAP0_SHIFT)
+#define APB_MISC_GP_MODEREG_0_LPDDR_STRAP0_RANGE                        8:8
+#define APB_MISC_GP_MODEREG_0_LPDDR_STRAP0_WOFFSET                      0x0
+#define APB_MISC_GP_MODEREG_0_LPDDR_STRAP0_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_MODEREG_0_LPDDR_STRAP0_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_MODEREG_0_LPDDR_STRAP0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_MODEREG_0_LPDDR_STRAP0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// LP-DDR Strap option bit 1.
+#define APB_MISC_GP_MODEREG_0_LPDDR_STRAP1_SHIFT                        _MK_SHIFT_CONST(9)
+#define APB_MISC_GP_MODEREG_0_LPDDR_STRAP1_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_MODEREG_0_LPDDR_STRAP1_SHIFT)
+#define APB_MISC_GP_MODEREG_0_LPDDR_STRAP1_RANGE                        9:9
+#define APB_MISC_GP_MODEREG_0_LPDDR_STRAP1_WOFFSET                      0x0
+#define APB_MISC_GP_MODEREG_0_LPDDR_STRAP1_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_MODEREG_0_LPDDR_STRAP1_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_MODEREG_0_LPDDR_STRAP1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_MODEREG_0_LPDDR_STRAP1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_HIDREV_0  
+#define APB_MISC_GP_HIDREV_0                    _MK_ADDR_CONST(0x804)
+#define APB_MISC_GP_HIDREV_0_WORD_COUNT                         0x1
+#define APB_MISC_GP_HIDREV_0_RESET_VAL                  _MK_MASK_CONST(0x31617)
+#define APB_MISC_GP_HIDREV_0_RESET_MASK                         _MK_MASK_CONST(0xfffff)
+#define APB_MISC_GP_HIDREV_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_HIDREV_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_HIDREV_0_READ_MASK                  _MK_MASK_CONST(0xfffff)
+#define APB_MISC_GP_HIDREV_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
+// Chip ID family register. There maybe a new HIDFAM code
+// added for MG20 products, this is still being descided.
+#define APB_MISC_GP_HIDREV_0_HIDFAM_SHIFT                       _MK_SHIFT_CONST(0)
+#define APB_MISC_GP_HIDREV_0_HIDFAM_FIELD                       (_MK_MASK_CONST(0xf) << APB_MISC_GP_HIDREV_0_HIDFAM_SHIFT)
+#define APB_MISC_GP_HIDREV_0_HIDFAM_RANGE                       3:0
+#define APB_MISC_GP_HIDREV_0_HIDFAM_WOFFSET                     0x0
+#define APB_MISC_GP_HIDREV_0_HIDFAM_DEFAULT                     _MK_MASK_CONST(0x7)
+#define APB_MISC_GP_HIDREV_0_HIDFAM_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define APB_MISC_GP_HIDREV_0_HIDFAM_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_HIDREV_0_HIDFAM_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_HIDREV_0_HIDFAM_GPU                 _MK_ENUM_CONST(0)
+#define APB_MISC_GP_HIDREV_0_HIDFAM_HANDHELD                    _MK_ENUM_CONST(1)
+#define APB_MISC_GP_HIDREV_0_HIDFAM_BR_CHIPS                    _MK_ENUM_CONST(2)
+#define APB_MISC_GP_HIDREV_0_HIDFAM_CRUSH                       _MK_ENUM_CONST(3)
+#define APB_MISC_GP_HIDREV_0_HIDFAM_MCP                 _MK_ENUM_CONST(4)
+#define APB_MISC_GP_HIDREV_0_HIDFAM_CK                  _MK_ENUM_CONST(5)
+#define APB_MISC_GP_HIDREV_0_HIDFAM_VAIO                        _MK_ENUM_CONST(6)
+#define APB_MISC_GP_HIDREV_0_HIDFAM_HANDHELD_SOC                        _MK_ENUM_CONST(7)
+
+// Chip ID major revision (0: Emulation, 1-15: Silicon)
+#define APB_MISC_GP_HIDREV_0_MAJORREV_SHIFT                     _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_HIDREV_0_MAJORREV_FIELD                     (_MK_MASK_CONST(0xf) << APB_MISC_GP_HIDREV_0_MAJORREV_SHIFT)
+#define APB_MISC_GP_HIDREV_0_MAJORREV_RANGE                     7:4
+#define APB_MISC_GP_HIDREV_0_MAJORREV_WOFFSET                   0x0
+#define APB_MISC_GP_HIDREV_0_MAJORREV_DEFAULT                   _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_HIDREV_0_MAJORREV_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define APB_MISC_GP_HIDREV_0_MAJORREV_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_HIDREV_0_MAJORREV_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_HIDREV_0_MAJORREV_EMULATION                 _MK_ENUM_CONST(0)
+#define APB_MISC_GP_HIDREV_0_MAJORREV_A01                       _MK_ENUM_CONST(1)
+
+// Chip ID
+#define APB_MISC_GP_HIDREV_0_CHIPID_SHIFT                       _MK_SHIFT_CONST(8)
+#define APB_MISC_GP_HIDREV_0_CHIPID_FIELD                       (_MK_MASK_CONST(0xff) << APB_MISC_GP_HIDREV_0_CHIPID_SHIFT)
+#define APB_MISC_GP_HIDREV_0_CHIPID_RANGE                       15:8
+#define APB_MISC_GP_HIDREV_0_CHIPID_WOFFSET                     0x0
+#define APB_MISC_GP_HIDREV_0_CHIPID_DEFAULT                     _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_HIDREV_0_CHIPID_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define APB_MISC_GP_HIDREV_0_CHIPID_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_HIDREV_0_CHIPID_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Chip ID minor revision (IF MAJORREV==0(Emulation) THEN  0: QT, 1:E388 FPGA)
+#define APB_MISC_GP_HIDREV_0_MINORREV_SHIFT                     _MK_SHIFT_CONST(16)
+#define APB_MISC_GP_HIDREV_0_MINORREV_FIELD                     (_MK_MASK_CONST(0xf) << APB_MISC_GP_HIDREV_0_MINORREV_SHIFT)
+#define APB_MISC_GP_HIDREV_0_MINORREV_RANGE                     19:16
+#define APB_MISC_GP_HIDREV_0_MINORREV_WOFFSET                   0x0
+#define APB_MISC_GP_HIDREV_0_MINORREV_DEFAULT                   _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_HIDREV_0_MINORREV_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define APB_MISC_GP_HIDREV_0_MINORREV_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_HIDREV_0_MINORREV_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Reserved address 2056 [0x808] 
+
+// Reserved address 2060 [0x80c] 
+
+// Register APB_MISC_GP_ASDBGREG_0  
+#define APB_MISC_GP_ASDBGREG_0                  _MK_ADDR_CONST(0x810)
+#define APB_MISC_GP_ASDBGREG_0_WORD_COUNT                       0x1
+#define APB_MISC_GP_ASDBGREG_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_RESET_MASK                       _MK_MASK_CONST(0x3ff0ffdf)
+#define APB_MISC_GP_ASDBGREG_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_READ_MASK                        _MK_MASK_CONST(0x3ff0ffdf)
+#define APB_MISC_GP_ASDBGREG_0_WRITE_MASK                       _MK_MASK_CONST(0x3ff0ffdf)
+// Enables iddq (WARNING: Will functionally kill chip)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_IDDQ_EN_SHIFT                    _MK_SHIFT_CONST(0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_IDDQ_EN_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG_0_CFG2TMC_IDDQ_EN_SHIFT)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_IDDQ_EN_RANGE                    0:0
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_IDDQ_EN_WOFFSET                  0x0
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_IDDQ_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_IDDQ_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_IDDQ_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_IDDQ_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_IDDQ_EN_DISABLE                  _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_IDDQ_EN_ENABLE                   _MK_ENUM_CONST(1)
+
+// Enables pullup
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLUP_EN_SHIFT                  _MK_SHIFT_CONST(1)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLUP_EN_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLUP_EN_SHIFT)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLUP_EN_RANGE                  1:1
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLUP_EN_WOFFSET                        0x0
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLUP_EN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLUP_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLUP_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLUP_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLUP_EN_DISABLE                        _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLUP_EN_ENABLE                 _MK_ENUM_CONST(1)
+
+// Enables pulldown
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLDOWN_EN_SHIFT                        _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLDOWN_EN_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLDOWN_EN_SHIFT)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLDOWN_EN_RANGE                        2:2
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLDOWN_EN_WOFFSET                      0x0
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLDOWN_EN_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLDOWN_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLDOWN_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLDOWN_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLDOWN_EN_DISABLE                      _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLDOWN_EN_ENABLE                       _MK_ENUM_CONST(1)
+
+// Enables debug mode
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_DEBUG_ENABLE_SHIFT                       _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_DEBUG_ENABLE_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG_0_CFG2TMC_DEBUG_ENABLE_SHIFT)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_DEBUG_ENABLE_RANGE                       3:3
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_DEBUG_ENABLE_WOFFSET                     0x0
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_DEBUG_ENABLE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_DEBUG_ENABLE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_DEBUG_ENABLE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_DEBUG_ENABLE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_DEBUG_ENABLE_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_DEBUG_ENABLE_ENABLE                      _MK_ENUM_CONST(1)
+
+// Enables performance monitor mode
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PM_ENABLE_SHIFT                  _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PM_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG_0_CFG2TMC_PM_ENABLE_SHIFT)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PM_ENABLE_RANGE                  4:4
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PM_ENABLE_WOFFSET                        0x0
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PM_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PM_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PM_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PM_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PM_ENABLE_DISABLE                        _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PM_ENABLE_ENABLE                 _MK_ENUM_CONST(1)
+
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_CLKBYP_FUNC_SHIFT                        _MK_SHIFT_CONST(6)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_CLKBYP_FUNC_FIELD                        (_MK_MASK_CONST(0x3) << APB_MISC_GP_ASDBGREG_0_CFG2TMC_CLKBYP_FUNC_SHIFT)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_CLKBYP_FUNC_RANGE                        7:6
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_CLKBYP_FUNC_WOFFSET                      0x0
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_CLKBYP_FUNC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_CLKBYP_FUNC_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_CLKBYP_FUNC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_CLKBYP_FUNC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_CLKBYP_FUNC_DISABLE                      _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_CLKBYP_FUNC_ENABLE                       _MK_ENUM_CONST(1)
+
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T1CLK_SHIFT                        _MK_SHIFT_CONST(8)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T1CLK_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T1CLK_SHIFT)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T1CLK_RANGE                        8:8
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T1CLK_WOFFSET                      0x0
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T1CLK_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T1CLK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T1CLK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T1CLK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T1CLK_DISABLE                      _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T1CLK_ENABLE                       _MK_ENUM_CONST(1)
+
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T2CLK_SHIFT                        _MK_SHIFT_CONST(9)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T2CLK_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T2CLK_SHIFT)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T2CLK_RANGE                        9:9
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T2CLK_WOFFSET                      0x0
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T2CLK_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T2CLK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T2CLK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T2CLK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T2CLK_DISABLE                      _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T2CLK_ENABLE                       _MK_ENUM_CONST(1)
+
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T3CLK_SHIFT                        _MK_SHIFT_CONST(10)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T3CLK_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T3CLK_SHIFT)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T3CLK_RANGE                        10:10
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T3CLK_WOFFSET                      0x0
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T3CLK_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T3CLK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T3CLK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T3CLK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T3CLK_DISABLE                      _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T3CLK_ENABLE                       _MK_ENUM_CONST(1)
+
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T4CLK_SHIFT                        _MK_SHIFT_CONST(11)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T4CLK_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T4CLK_SHIFT)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T4CLK_RANGE                        11:11
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T4CLK_WOFFSET                      0x0
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T4CLK_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T4CLK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T4CLK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T4CLK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T4CLK_DISABLE                      _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T4CLK_ENABLE                       _MK_ENUM_CONST(1)
+
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T5CLK_SHIFT                        _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T5CLK_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T5CLK_SHIFT)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T5CLK_RANGE                        12:12
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T5CLK_WOFFSET                      0x0
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T5CLK_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T5CLK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T5CLK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T5CLK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T5CLK_DISABLE                      _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T5CLK_ENABLE                       _MK_ENUM_CONST(1)
+
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T6CLK_SHIFT                        _MK_SHIFT_CONST(13)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T6CLK_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T6CLK_SHIFT)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T6CLK_RANGE                        13:13
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T6CLK_WOFFSET                      0x0
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T6CLK_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T6CLK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T6CLK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T6CLK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T6CLK_DISABLE                      _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T6CLK_ENABLE                       _MK_ENUM_CONST(1)
+
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T7CLK_SHIFT                        _MK_SHIFT_CONST(14)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T7CLK_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T7CLK_SHIFT)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T7CLK_RANGE                        14:14
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T7CLK_WOFFSET                      0x0
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T7CLK_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T7CLK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T7CLK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T7CLK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T7CLK_DISABLE                      _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T7CLK_ENABLE                       _MK_ENUM_CONST(1)
+
+//  Obsolete previously used with host_pad_macros (jmoskal)
+//16      rw  CFG2TMC_SW_BP_WRNCLK      i=0x0
+//    enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_CLK_DIV_SHIFT                      _MK_SHIFT_CONST(15)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_CLK_DIV_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_CLK_DIV_SHIFT)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_CLK_DIV_RANGE                      15:15
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_CLK_DIV_WOFFSET                    0x0
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_CLK_DIV_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_CLK_DIV_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_CLK_DIV_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_CLK_DIV_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_CLK_DIV_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_CLK_DIV_ENABLE                     _MK_ENUM_CONST(1)
+
+// control timing characteristics for the compiled rams
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_EMAA_SHIFT                   _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_EMAA_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_EMAA_SHIFT)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_EMAA_RANGE                   21:20
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_EMAA_WOFFSET                 0x0
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_EMAA_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_EMAA_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_EMAA_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_EMAA_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_EMAA_DISABLE                 _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_EMAA_ENABLE                  _MK_ENUM_CONST(1)
+
+// control write timing characteristics for the compiled RAMDP
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_DP_SHIFT                        _MK_SHIFT_CONST(22)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_DP_FIELD                        (_MK_MASK_CONST(0x3) << APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_DP_SHIFT)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_DP_RANGE                        23:22
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_DP_WOFFSET                      0x0
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_DP_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_DP_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_DP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_DP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// control write timing characteristics for the compiled RAMPDP
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_PDP_SHIFT                       _MK_SHIFT_CONST(24)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_PDP_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_PDP_SHIFT)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_PDP_RANGE                       25:24
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_PDP_WOFFSET                     0x0
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_PDP_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_PDP_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_PDP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_PDP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// control write timing characteristics for the compiled RAMREG
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_REG_SHIFT                       _MK_SHIFT_CONST(26)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_REG_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_REG_SHIFT)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_REG_RANGE                       27:26
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_REG_WOFFSET                     0x0
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_REG_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_REG_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_REG_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_REG_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// control write timing characteristics for the compiled RAMSP
+// ECO 385781, add reset to RAM_SVOP_SP
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_SP_SHIFT                        _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_SP_FIELD                        (_MK_MASK_CONST(0x3) << APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_SP_SHIFT)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_SP_RANGE                        29:28
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_SP_WOFFSET                      0x0
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_SP_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_SP_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_SP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_SP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_RESERVEREG_0  
+#define APB_MISC_GP_RESERVEREG_0                        _MK_ADDR_CONST(0x814)
+#define APB_MISC_GP_RESERVEREG_0_WORD_COUNT                     0x1
+#define APB_MISC_GP_RESERVEREG_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_RESERVEREG_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_GP_RESERVEREG_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_RESERVEREG_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_RESERVEREG_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_GP_RESERVEREG_0_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE0_SHIFT                     _MK_SHIFT_CONST(0)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE0_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_RESERVEREG_0_ECO_RESERVE0_SHIFT)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE0_RANGE                     0:0
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE0_WOFFSET                   0x0
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE0_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE0_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE1_SHIFT                     _MK_SHIFT_CONST(1)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE1_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_RESERVEREG_0_ECO_RESERVE1_SHIFT)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE1_RANGE                     1:1
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE1_WOFFSET                   0x0
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE1_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE1_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE2_SHIFT                     _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE2_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_RESERVEREG_0_ECO_RESERVE2_SHIFT)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE2_RANGE                     2:2
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE2_WOFFSET                   0x0
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE2_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE2_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE3_SHIFT                     _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE3_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_RESERVEREG_0_ECO_RESERVE3_SHIFT)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE3_RANGE                     3:3
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE3_WOFFSET                   0x0
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE3_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE3_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE3_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE3_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE4_SHIFT                     _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE4_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_RESERVEREG_0_ECO_RESERVE4_SHIFT)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE4_RANGE                     4:4
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE4_WOFFSET                   0x0
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE4_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE4_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE4_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE4_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE5_SHIFT                     _MK_SHIFT_CONST(5)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE5_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_RESERVEREG_0_ECO_RESERVE5_SHIFT)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE5_RANGE                     5:5
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE5_WOFFSET                   0x0
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE5_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE5_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE5_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE5_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE6_SHIFT                     _MK_SHIFT_CONST(6)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE6_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_RESERVEREG_0_ECO_RESERVE6_SHIFT)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE6_RANGE                     6:6
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE6_WOFFSET                   0x0
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE6_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE6_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE6_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE6_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE7_SHIFT                     _MK_SHIFT_CONST(7)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE7_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_RESERVEREG_0_ECO_RESERVE7_SHIFT)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE7_RANGE                     7:7
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE7_WOFFSET                   0x0
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE7_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE7_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE7_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE7_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE_B1_SHIFT                   _MK_SHIFT_CONST(8)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE_B1_FIELD                   (_MK_MASK_CONST(0xff) << APB_MISC_GP_RESERVEREG_0_ECO_RESERVE_B1_SHIFT)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE_B1_RANGE                   15:8
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE_B1_WOFFSET                 0x0
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE_B1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE_B1_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE_B1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE_B1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE_B2_SHIFT                   _MK_SHIFT_CONST(16)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE_B2_FIELD                   (_MK_MASK_CONST(0xff) << APB_MISC_GP_RESERVEREG_0_ECO_RESERVE_B2_SHIFT)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE_B2_RANGE                   23:16
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE_B2_WOFFSET                 0x0
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE_B2_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE_B2_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE_B2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE_B2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE_B3_SHIFT                   _MK_SHIFT_CONST(24)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE_B3_FIELD                   (_MK_MASK_CONST(0xff) << APB_MISC_GP_RESERVEREG_0_ECO_RESERVE_B3_SHIFT)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE_B3_RANGE                   31:24
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE_B3_WOFFSET                 0x0
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE_B3_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE_B3_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE_B3_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE_B3_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_OBSCTRL_0  
+#define APB_MISC_GP_OBSCTRL_0                   _MK_ADDR_CONST(0x818)
+#define APB_MISC_GP_OBSCTRL_0_WORD_COUNT                        0x1
+#define APB_MISC_GP_OBSCTRL_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OBSCTRL_0_RESET_MASK                        _MK_MASK_CONST(0x80ffffff)
+#define APB_MISC_GP_OBSCTRL_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OBSCTRL_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OBSCTRL_0_READ_MASK                         _MK_MASK_CONST(0x80ffffff)
+#define APB_MISC_GP_OBSCTRL_0_WRITE_MASK                        _MK_MASK_CONST(0x80ffffff)
+// Module-level mux select for determining which debug signals to send out
+#define APB_MISC_GP_OBSCTRL_0_OBS_SIG_SEL_SHIFT                 _MK_SHIFT_CONST(0)
+#define APB_MISC_GP_OBSCTRL_0_OBS_SIG_SEL_FIELD                 (_MK_MASK_CONST(0xffff) << APB_MISC_GP_OBSCTRL_0_OBS_SIG_SEL_SHIFT)
+#define APB_MISC_GP_OBSCTRL_0_OBS_SIG_SEL_RANGE                 15:0
+#define APB_MISC_GP_OBSCTRL_0_OBS_SIG_SEL_WOFFSET                       0x0
+#define APB_MISC_GP_OBSCTRL_0_OBS_SIG_SEL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OBSCTRL_0_OBS_SIG_SEL_DEFAULT_MASK                  _MK_MASK_CONST(0xffff)
+#define APB_MISC_GP_OBSCTRL_0_OBS_SIG_SEL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OBSCTRL_0_OBS_SIG_SEL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Observation module select
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_SHIFT                 _MK_SHIFT_CONST(16)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_FIELD                 (_MK_MASK_CONST(0xf) << APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_SHIFT)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_RANGE                 19:16
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_WOFFSET                       0x0
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_PMC                   _MK_ENUM_CONST(0)    // // AO partition
+
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_MSELECT                       _MK_ENUM_CONST(0)    // // CPU partition
+
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_CSI                   _MK_ENUM_CONST(0)    // // DIS partition
+
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_CSICIL                        _MK_ENUM_CONST(1)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_DISPLAY                       _MK_ENUM_CONST(2)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_DISPLAYB                      _MK_ENUM_CONST(3)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_DSI                   _MK_ENUM_CONST(4)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_HDMI                  _MK_ENUM_CONST(5)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_TVO                   _MK_ENUM_CONST(6)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_CAR                   _MK_ENUM_CONST(0)    // // GR partition
+
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_CMC                   _MK_ENUM_CONST(1)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_EMC                   _MK_ENUM_CONST(2)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_FUSE                  _MK_ENUM_CONST(3)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_GR2D                  _MK_ENUM_CONST(4)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_HOST1X                        _MK_ENUM_CONST(5)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_MC                    _MK_ENUM_CONST(6)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_MPEA                  _MK_ENUM_CONST(0)    // // MPE partition
+
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_MPEB                  _MK_ENUM_CONST(1)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_MPEC                  _MK_ENUM_CONST(2)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_STRAT12                       _MK_ENUM_CONST(0)    // // STRAT12 partition
+
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_CLIP                  _MK_ENUM_CONST(0)    // // TDA partition
+
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_IDX                   _MK_ENUM_CONST(1)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_SETUP                 _MK_ENUM_CONST(2)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_VPE                   _MK_ENUM_CONST(3)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_ALU                   _MK_ENUM_CONST(0)    // // TDB partition
+
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_ATRAST                        _MK_ENUM_CONST(1)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_DWR                   _MK_ENUM_CONST(2)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_FDC                   _MK_ENUM_CONST(3)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_PSEQ                  _MK_ENUM_CONST(4)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_QRAST                 _MK_ENUM_CONST(5)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_TEX                   _MK_ENUM_CONST(6)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_UVDE                  _MK_ENUM_CONST(0)    // // VDE partition
+
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_EPP                   _MK_ENUM_CONST(0)    // // VE partition
+
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_ISP                   _MK_ENUM_CONST(1)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_VI                    _MK_ENUM_CONST(2)
+
+// Observation partition select
+#define APB_MISC_GP_OBSCTRL_0_OBS_PART_SEL_SHIFT                        _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_OBSCTRL_0_OBS_PART_SEL_FIELD                        (_MK_MASK_CONST(0xf) << APB_MISC_GP_OBSCTRL_0_OBS_PART_SEL_SHIFT)
+#define APB_MISC_GP_OBSCTRL_0_OBS_PART_SEL_RANGE                        23:20
+#define APB_MISC_GP_OBSCTRL_0_OBS_PART_SEL_WOFFSET                      0x0
+#define APB_MISC_GP_OBSCTRL_0_OBS_PART_SEL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OBSCTRL_0_OBS_PART_SEL_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define APB_MISC_GP_OBSCTRL_0_OBS_PART_SEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OBSCTRL_0_OBS_PART_SEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OBSCTRL_0_OBS_PART_SEL_AO                   _MK_ENUM_CONST(0)
+#define APB_MISC_GP_OBSCTRL_0_OBS_PART_SEL_CPU                  _MK_ENUM_CONST(1)
+#define APB_MISC_GP_OBSCTRL_0_OBS_PART_SEL_DIS                  _MK_ENUM_CONST(2)
+#define APB_MISC_GP_OBSCTRL_0_OBS_PART_SEL_GR                   _MK_ENUM_CONST(3)
+#define APB_MISC_GP_OBSCTRL_0_OBS_PART_SEL_MPE                  _MK_ENUM_CONST(4)
+#define APB_MISC_GP_OBSCTRL_0_OBS_PART_SEL_ST                   _MK_ENUM_CONST(5)
+#define APB_MISC_GP_OBSCTRL_0_OBS_PART_SEL_TDA                  _MK_ENUM_CONST(6)
+#define APB_MISC_GP_OBSCTRL_0_OBS_PART_SEL_TDB                  _MK_ENUM_CONST(7)
+#define APB_MISC_GP_OBSCTRL_0_OBS_PART_SEL_VDE                  _MK_ENUM_CONST(8)
+#define APB_MISC_GP_OBSCTRL_0_OBS_PART_SEL_VE                   _MK_ENUM_CONST(9)
+
+// Observation bus enable
+#define APB_MISC_GP_OBSCTRL_0_OBS_EN_SHIFT                      _MK_SHIFT_CONST(31)
+#define APB_MISC_GP_OBSCTRL_0_OBS_EN_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_OBSCTRL_0_OBS_EN_SHIFT)
+#define APB_MISC_GP_OBSCTRL_0_OBS_EN_RANGE                      31:31
+#define APB_MISC_GP_OBSCTRL_0_OBS_EN_WOFFSET                    0x0
+#define APB_MISC_GP_OBSCTRL_0_OBS_EN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OBSCTRL_0_OBS_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_OBSCTRL_0_OBS_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OBSCTRL_0_OBS_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OBSCTRL_0_OBS_EN_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_GP_OBSCTRL_0_OBS_EN_ENABLE                     _MK_ENUM_CONST(1)
+
+
+// Register APB_MISC_GP_OBSDATA_0  
+#define APB_MISC_GP_OBSDATA_0                   _MK_ADDR_CONST(0x81c)
+#define APB_MISC_GP_OBSDATA_0_WORD_COUNT                        0x1
+#define APB_MISC_GP_OBSDATA_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OBSDATA_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OBSDATA_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OBSDATA_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OBSDATA_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_GP_OBSDATA_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+// Observation port data.  This should be the same data that is going out on the observation bus.
+#define APB_MISC_GP_OBSDATA_0_OBS_DATA_SHIFT                    _MK_SHIFT_CONST(0)
+#define APB_MISC_GP_OBSDATA_0_OBS_DATA_FIELD                    (_MK_MASK_CONST(0xffffffff) << APB_MISC_GP_OBSDATA_0_OBS_DATA_SHIFT)
+#define APB_MISC_GP_OBSDATA_0_OBS_DATA_RANGE                    31:0
+#define APB_MISC_GP_OBSDATA_0_OBS_DATA_WOFFSET                  0x0
+#define APB_MISC_GP_OBSDATA_0_OBS_DATA_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OBSDATA_0_OBS_DATA_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OBSDATA_0_OBS_DATA_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OBSDATA_0_OBS_DATA_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_EFUSEREQ_0  
+#define APB_MISC_GP_EFUSEREQ_0                  _MK_ADDR_CONST(0x820)
+#define APB_MISC_GP_EFUSEREQ_0_WORD_COUNT                       0x1
+#define APB_MISC_GP_EFUSEREQ_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EFUSEREQ_0_RESET_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_EFUSEREQ_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EFUSEREQ_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EFUSEREQ_0_READ_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_EFUSEREQ_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_EFUSEREQ_0_EF_RESERVED0_SHIFT                       _MK_SHIFT_CONST(0)
+#define APB_MISC_GP_EFUSEREQ_0_EF_RESERVED0_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_EFUSEREQ_0_EF_RESERVED0_SHIFT)
+#define APB_MISC_GP_EFUSEREQ_0_EF_RESERVED0_RANGE                       0:0
+#define APB_MISC_GP_EFUSEREQ_0_EF_RESERVED0_WOFFSET                     0x0
+#define APB_MISC_GP_EFUSEREQ_0_EF_RESERVED0_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EFUSEREQ_0_EF_RESERVED0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_EFUSEREQ_0_EF_RESERVED0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EFUSEREQ_0_EF_RESERVED0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_EFUSEOFF_0  
+#define APB_MISC_GP_EFUSEOFF_0                  _MK_ADDR_CONST(0x824)
+#define APB_MISC_GP_EFUSEOFF_0_WORD_COUNT                       0x1
+#define APB_MISC_GP_EFUSEOFF_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EFUSEOFF_0_RESET_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_EFUSEOFF_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EFUSEOFF_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EFUSEOFF_0_READ_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_EFUSEOFF_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_EFUSEOFF_0_EF_RESERVED1_SHIFT                       _MK_SHIFT_CONST(0)
+#define APB_MISC_GP_EFUSEOFF_0_EF_RESERVED1_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_EFUSEOFF_0_EF_RESERVED1_SHIFT)
+#define APB_MISC_GP_EFUSEOFF_0_EF_RESERVED1_RANGE                       0:0
+#define APB_MISC_GP_EFUSEOFF_0_EF_RESERVED1_WOFFSET                     0x0
+#define APB_MISC_GP_EFUSEOFF_0_EF_RESERVED1_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EFUSEOFF_0_EF_RESERVED1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_EFUSEOFF_0_EF_RESERVED1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EFUSEOFF_0_EF_RESERVED1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_EFUSEWRDAT_0  
+#define APB_MISC_GP_EFUSEWRDAT_0                        _MK_ADDR_CONST(0x828)
+#define APB_MISC_GP_EFUSEWRDAT_0_WORD_COUNT                     0x1
+#define APB_MISC_GP_EFUSEWRDAT_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EFUSEWRDAT_0_RESET_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_EFUSEWRDAT_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EFUSEWRDAT_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EFUSEWRDAT_0_READ_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_EFUSEWRDAT_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_EFUSEWRDAT_0_EF_RESERVED2_SHIFT                     _MK_SHIFT_CONST(0)
+#define APB_MISC_GP_EFUSEWRDAT_0_EF_RESERVED2_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_EFUSEWRDAT_0_EF_RESERVED2_SHIFT)
+#define APB_MISC_GP_EFUSEWRDAT_0_EF_RESERVED2_RANGE                     0:0
+#define APB_MISC_GP_EFUSEWRDAT_0_EF_RESERVED2_WOFFSET                   0x0
+#define APB_MISC_GP_EFUSEWRDAT_0_EF_RESERVED2_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EFUSEWRDAT_0_EF_RESERVED2_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_EFUSEWRDAT_0_EF_RESERVED2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EFUSEWRDAT_0_EF_RESERVED2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_EFUSERDDAT_0  
+#define APB_MISC_GP_EFUSERDDAT_0                        _MK_ADDR_CONST(0x82c)
+#define APB_MISC_GP_EFUSERDDAT_0_WORD_COUNT                     0x1
+#define APB_MISC_GP_EFUSERDDAT_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EFUSERDDAT_0_RESET_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_EFUSERDDAT_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EFUSERDDAT_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EFUSERDDAT_0_READ_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_EFUSERDDAT_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_EFUSERDDAT_0_EF_RESERVED3_SHIFT                     _MK_SHIFT_CONST(0)
+#define APB_MISC_GP_EFUSERDDAT_0_EF_RESERVED3_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_EFUSERDDAT_0_EF_RESERVED3_SHIFT)
+#define APB_MISC_GP_EFUSERDDAT_0_EF_RESERVED3_RANGE                     0:0
+#define APB_MISC_GP_EFUSERDDAT_0_EF_RESERVED3_WOFFSET                   0x0
+#define APB_MISC_GP_EFUSERDDAT_0_EF_RESERVED3_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EFUSERDDAT_0_EF_RESERVED3_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_EFUSERDDAT_0_EF_RESERVED3_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EFUSERDDAT_0_EF_RESERVED3_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_EFUSEVAL1_0  
+#define APB_MISC_GP_EFUSEVAL1_0                 _MK_ADDR_CONST(0x830)
+#define APB_MISC_GP_EFUSEVAL1_0_WORD_COUNT                      0x1
+#define APB_MISC_GP_EFUSEVAL1_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EFUSEVAL1_0_RESET_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_EFUSEVAL1_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EFUSEVAL1_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EFUSEVAL1_0_READ_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_EFUSEVAL1_0_WRITE_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_EFUSEVAL1_0_EF_RESERVED4_SHIFT                      _MK_SHIFT_CONST(0)
+#define APB_MISC_GP_EFUSEVAL1_0_EF_RESERVED4_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_EFUSEVAL1_0_EF_RESERVED4_SHIFT)
+#define APB_MISC_GP_EFUSEVAL1_0_EF_RESERVED4_RANGE                      0:0
+#define APB_MISC_GP_EFUSEVAL1_0_EF_RESERVED4_WOFFSET                    0x0
+#define APB_MISC_GP_EFUSEVAL1_0_EF_RESERVED4_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EFUSEVAL1_0_EF_RESERVED4_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_EFUSEVAL1_0_EF_RESERVED4_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EFUSEVAL1_0_EF_RESERVED4_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_EFUSEVAL2_0  
+#define APB_MISC_GP_EFUSEVAL2_0                 _MK_ADDR_CONST(0x834)
+#define APB_MISC_GP_EFUSEVAL2_0_WORD_COUNT                      0x1
+#define APB_MISC_GP_EFUSEVAL2_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EFUSEVAL2_0_RESET_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_EFUSEVAL2_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EFUSEVAL2_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EFUSEVAL2_0_READ_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_EFUSEVAL2_0_WRITE_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_EFUSEVAL2_0_EF_RESERVED5_SHIFT                      _MK_SHIFT_CONST(0)
+#define APB_MISC_GP_EFUSEVAL2_0_EF_RESERVED5_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_EFUSEVAL2_0_EF_RESERVED5_SHIFT)
+#define APB_MISC_GP_EFUSEVAL2_0_EF_RESERVED5_RANGE                      0:0
+#define APB_MISC_GP_EFUSEVAL2_0_EF_RESERVED5_WOFFSET                    0x0
+#define APB_MISC_GP_EFUSEVAL2_0_EF_RESERVED5_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EFUSEVAL2_0_EF_RESERVED5_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_EFUSEVAL2_0_EF_RESERVED5_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EFUSEVAL2_0_EF_RESERVED5_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_EFUSEBYPASSID_0  
+#define APB_MISC_GP_EFUSEBYPASSID_0                     _MK_ADDR_CONST(0x838)
+#define APB_MISC_GP_EFUSEBYPASSID_0_WORD_COUNT                  0x1
+#define APB_MISC_GP_EFUSEBYPASSID_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EFUSEBYPASSID_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_EFUSEBYPASSID_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EFUSEBYPASSID_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EFUSEBYPASSID_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_EFUSEBYPASSID_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_EFUSEBYPASSID_0_EF_RESERVED6_SHIFT                  _MK_SHIFT_CONST(0)
+#define APB_MISC_GP_EFUSEBYPASSID_0_EF_RESERVED6_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_GP_EFUSEBYPASSID_0_EF_RESERVED6_SHIFT)
+#define APB_MISC_GP_EFUSEBYPASSID_0_EF_RESERVED6_RANGE                  0:0
+#define APB_MISC_GP_EFUSEBYPASSID_0_EF_RESERVED6_WOFFSET                        0x0
+#define APB_MISC_GP_EFUSEBYPASSID_0_EF_RESERVED6_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EFUSEBYPASSID_0_EF_RESERVED6_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_EFUSEBYPASSID_0_EF_RESERVED6_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EFUSEBYPASSID_0_EF_RESERVED6_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_BRDCLK_TRIM_0  
+#define APB_MISC_GP_BRDCLK_TRIM_0                       _MK_ADDR_CONST(0x83c)
+#define APB_MISC_GP_BRDCLK_TRIM_0_WORD_COUNT                    0x1
+#define APB_MISC_GP_BRDCLK_TRIM_0_RESET_VAL                     _MK_MASK_CONST(0x4)
+#define APB_MISC_GP_BRDCLK_TRIM_0_RESET_MASK                    _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_BRDCLK_TRIM_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_BRDCLK_TRIM_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_BRDCLK_TRIM_0_READ_MASK                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_BRDCLK_TRIM_0_WRITE_MASK                    _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_BRDCLK_TRIM_0_BRDCLKTRIM_SHIFT                      _MK_SHIFT_CONST(0)
+#define APB_MISC_GP_BRDCLK_TRIM_0_BRDCLKTRIM_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_BRDCLK_TRIM_0_BRDCLKTRIM_SHIFT)
+#define APB_MISC_GP_BRDCLK_TRIM_0_BRDCLKTRIM_RANGE                      4:0
+#define APB_MISC_GP_BRDCLK_TRIM_0_BRDCLKTRIM_WOFFSET                    0x0
+#define APB_MISC_GP_BRDCLK_TRIM_0_BRDCLKTRIM_DEFAULT                    _MK_MASK_CONST(0x4)
+#define APB_MISC_GP_BRDCLK_TRIM_0_BRDCLKTRIM_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_BRDCLK_TRIM_0_BRDCLKTRIM_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_BRDCLK_TRIM_0_BRDCLKTRIM_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Reserved address 2112 [0x840] 
+
+// Reserved address 2116 [0x844] 
+
+// Reserved address 2120 [0x848] 
+
+// Reserved address 2124 [0x84c] 
+
+// Reserved address 2128 [0x850] 
+
+// Reserved address 2132 [0x854] 
+
+// Register APB_MISC_GP_ASDBGREG2_0  
+#define APB_MISC_GP_ASDBGREG2_0                 _MK_ADDR_CONST(0x858)
+#define APB_MISC_GP_ASDBGREG2_0_WORD_COUNT                      0x1
+#define APB_MISC_GP_ASDBGREG2_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_RESET_MASK                      _MK_MASK_CONST(0x7ff80)
+#define APB_MISC_GP_ASDBGREG2_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_READ_MASK                       _MK_MASK_CONST(0x7ff80)
+#define APB_MISC_GP_ASDBGREG2_0_WRITE_MASK                      _MK_MASK_CONST(0x7ff80)
+//Enable bypass of functional clock with test clock 8
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T8CLK_SHIFT                       _MK_SHIFT_CONST(7)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T8CLK_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T8CLK_SHIFT)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T8CLK_RANGE                       7:7
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T8CLK_WOFFSET                     0x0
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T8CLK_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T8CLK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T8CLK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T8CLK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T8CLK_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T8CLK_ENABLE                      _MK_ENUM_CONST(1)
+
+//Enable bypass of functional clock with test clock 9
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T9CLK_SHIFT                       _MK_SHIFT_CONST(8)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T9CLK_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T9CLK_SHIFT)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T9CLK_RANGE                       8:8
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T9CLK_WOFFSET                     0x0
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T9CLK_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T9CLK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T9CLK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T9CLK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T9CLK_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T9CLK_ENABLE                      _MK_ENUM_CONST(1)
+
+//Enable bypass of functional clock with test clock 10
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T10CLK_SHIFT                      _MK_SHIFT_CONST(9)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T10CLK_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T10CLK_SHIFT)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T10CLK_RANGE                      9:9
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T10CLK_WOFFSET                    0x0
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T10CLK_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T10CLK_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T10CLK_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T10CLK_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T10CLK_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T10CLK_ENABLE                     _MK_ENUM_CONST(1)
+
+//Enable bypass of functional clock with test clock 11
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T11CLK_SHIFT                      _MK_SHIFT_CONST(10)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T11CLK_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T11CLK_SHIFT)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T11CLK_RANGE                      10:10
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T11CLK_WOFFSET                    0x0
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T11CLK_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T11CLK_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T11CLK_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T11CLK_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T11CLK_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T11CLK_ENABLE                     _MK_ENUM_CONST(1)
+
+//Enable bypass of functional clock with test clock 12
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T12CLK_SHIFT                      _MK_SHIFT_CONST(11)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T12CLK_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T12CLK_SHIFT)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T12CLK_RANGE                      11:11
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T12CLK_WOFFSET                    0x0
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T12CLK_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T12CLK_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T12CLK_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T12CLK_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T12CLK_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T12CLK_ENABLE                     _MK_ENUM_CONST(1)
+
+//Enable bypass of functional clock with test clock 13
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T13CLK_SHIFT                      _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T13CLK_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T13CLK_SHIFT)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T13CLK_RANGE                      12:12
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T13CLK_WOFFSET                    0x0
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T13CLK_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T13CLK_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T13CLK_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T13CLK_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T13CLK_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T13CLK_ENABLE                     _MK_ENUM_CONST(1)
+
+//Enable bypass of functional clock with test clock 14
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T14CLK_SHIFT                      _MK_SHIFT_CONST(13)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T14CLK_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T14CLK_SHIFT)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T14CLK_RANGE                      13:13
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T14CLK_WOFFSET                    0x0
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T14CLK_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T14CLK_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T14CLK_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T14CLK_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T14CLK_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T14CLK_ENABLE                     _MK_ENUM_CONST(1)
+
+//Enable bypass of functional clock with test clock 15
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T15CLK_SHIFT                      _MK_SHIFT_CONST(14)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T15CLK_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T15CLK_SHIFT)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T15CLK_RANGE                      14:14
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T15CLK_WOFFSET                    0x0
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T15CLK_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T15CLK_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T15CLK_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T15CLK_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T15CLK_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T15CLK_ENABLE                     _MK_ENUM_CONST(1)
+
+//Enable bypass of functional clock with test clock 16
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T16CLK_SHIFT                      _MK_SHIFT_CONST(15)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T16CLK_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T16CLK_SHIFT)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T16CLK_RANGE                      15:15
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T16CLK_WOFFSET                    0x0
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T16CLK_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T16CLK_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T16CLK_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T16CLK_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T16CLK_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T16CLK_ENABLE                     _MK_ENUM_CONST(1)
+
+//Enable bypass of functional clock with test clock 17
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T17CLK_SHIFT                      _MK_SHIFT_CONST(16)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T17CLK_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T17CLK_SHIFT)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T17CLK_RANGE                      16:16
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T17CLK_WOFFSET                    0x0
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T17CLK_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T17CLK_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T17CLK_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T17CLK_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T17CLK_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T17CLK_ENABLE                     _MK_ENUM_CONST(1)
+
+//Enable bypass of functional clock with test clock 18
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T18CLK_SHIFT                      _MK_SHIFT_CONST(17)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T18CLK_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T18CLK_SHIFT)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T18CLK_RANGE                      17:17
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T18CLK_WOFFSET                    0x0
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T18CLK_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T18CLK_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T18CLK_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T18CLK_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T18CLK_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T18CLK_ENABLE                     _MK_ENUM_CONST(1)
+
+//Enable bypass of sync Already in NV_car
+//  18       rw  CFG2TMC_OSCFI_BYPASS     i=0x0  //Enable bypass of oscfi
+//            enum ( DISABLE, ENABLE )
+//  19       rw  CFG2TMC_OSCFI_EN         i=0x0  //Enable oscfi refclk
+//      enum ( DISABLE, ENABLE )
+//      enum ( DISABLE, ENABLE )
+//  25:21   rw  CFG2TMC_OSCFI_D           i=0x0  //
+//  31:26   rw  CFG2TMC_OSCFI_S           i=0x0  //
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_SYNC_SHIFT                        _MK_SHIFT_CONST(18)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_SYNC_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_SYNC_SHIFT)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_SYNC_RANGE                        18:18
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_SYNC_WOFFSET                      0x0
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_SYNC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_SYNC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_SYNC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_SYNC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_SYNC_DISABLE                      _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_SYNC_ENABLE                       _MK_ENUM_CONST(1)
+
+
+// Register APB_MISC_GP_EMU_REVID_0  
+#define APB_MISC_GP_EMU_REVID_0                 _MK_ADDR_CONST(0x860)
+#define APB_MISC_GP_EMU_REVID_0_WORD_COUNT                      0x1
+#define APB_MISC_GP_EMU_REVID_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EMU_REVID_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_GP_EMU_REVID_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EMU_REVID_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EMU_REVID_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_GP_EMU_REVID_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
+// USED by emulators to indicate netlist #, 0 for silicon.
+#define APB_MISC_GP_EMU_REVID_0_NETLIST_SHIFT                   _MK_SHIFT_CONST(0)
+#define APB_MISC_GP_EMU_REVID_0_NETLIST_FIELD                   (_MK_MASK_CONST(0xffff) << APB_MISC_GP_EMU_REVID_0_NETLIST_SHIFT)
+#define APB_MISC_GP_EMU_REVID_0_NETLIST_RANGE                   15:0
+#define APB_MISC_GP_EMU_REVID_0_NETLIST_WOFFSET                 0x0
+#define APB_MISC_GP_EMU_REVID_0_NETLIST_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EMU_REVID_0_NETLIST_DEFAULT_MASK                    _MK_MASK_CONST(0xffff)
+#define APB_MISC_GP_EMU_REVID_0_NETLIST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EMU_REVID_0_NETLIST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EMU_REVID_0_NETLIST_INIT_ENUM                       NV_EMUL_NETLIST
+
+// USED by emulators to indicate patch #, 0 for silicon.
+#define APB_MISC_GP_EMU_REVID_0_PATCH_SHIFT                     _MK_SHIFT_CONST(16)
+#define APB_MISC_GP_EMU_REVID_0_PATCH_FIELD                     (_MK_MASK_CONST(0xffff) << APB_MISC_GP_EMU_REVID_0_PATCH_SHIFT)
+#define APB_MISC_GP_EMU_REVID_0_PATCH_RANGE                     31:16
+#define APB_MISC_GP_EMU_REVID_0_PATCH_WOFFSET                   0x0
+#define APB_MISC_GP_EMU_REVID_0_PATCH_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EMU_REVID_0_PATCH_DEFAULT_MASK                      _MK_MASK_CONST(0xffff)
+#define APB_MISC_GP_EMU_REVID_0_PATCH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EMU_REVID_0_PATCH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EMU_REVID_0_PATCH_INIT_ENUM                 NV_EMUL_PATCH
+
+
+// Register APB_MISC_GP_TRANSACTOR_SCRATCH_0  
+#define APB_MISC_GP_TRANSACTOR_SCRATCH_0                        _MK_ADDR_CONST(0x864)
+#define APB_MISC_GP_TRANSACTOR_SCRATCH_0_WORD_COUNT                     0x1
+#define APB_MISC_GP_TRANSACTOR_SCRATCH_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_TRANSACTOR_SCRATCH_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_GP_TRANSACTOR_SCRATCH_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_TRANSACTOR_SCRATCH_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_TRANSACTOR_SCRATCH_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_GP_TRANSACTOR_SCRATCH_0_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
+// used for emulation to determine test results.
+#define APB_MISC_GP_TRANSACTOR_SCRATCH_0_TRANSACTOR_SCRATCH_SHIFT                       _MK_SHIFT_CONST(0)
+#define APB_MISC_GP_TRANSACTOR_SCRATCH_0_TRANSACTOR_SCRATCH_FIELD                       (_MK_MASK_CONST(0xffffffff) << APB_MISC_GP_TRANSACTOR_SCRATCH_0_TRANSACTOR_SCRATCH_SHIFT)
+#define APB_MISC_GP_TRANSACTOR_SCRATCH_0_TRANSACTOR_SCRATCH_RANGE                       31:0
+#define APB_MISC_GP_TRANSACTOR_SCRATCH_0_TRANSACTOR_SCRATCH_WOFFSET                     0x0
+#define APB_MISC_GP_TRANSACTOR_SCRATCH_0_TRANSACTOR_SCRATCH_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_TRANSACTOR_SCRATCH_0_TRANSACTOR_SCRATCH_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_GP_TRANSACTOR_SCRATCH_0_TRANSACTOR_SCRATCH_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_TRANSACTOR_SCRATCH_0_TRANSACTOR_SCRATCH_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_AOCFG1PADCTRL_0  //        0       rw  CFG2TMC_AOCFG1_PULLD_EN i=0x0   // AOCFG1 pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_AOCFG1_PULLU_EN i=0x0   // AOCFG1 pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_AOCFG1PADCTRL_0                     _MK_ADDR_CONST(0x868)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_WORD_COUNT                  0x1
+#define APB_MISC_GP_AOCFG1PADCTRL_0_RESET_VAL                   _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_RESET_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_READ_MASK                   _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_WRITE_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+// AOCFG1 data pins high speed mode enable
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_HSM_EN_SHIFT                 _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_HSM_EN_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_HSM_EN_SHIFT)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_HSM_EN_RANGE                 2:2
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_HSM_EN_WOFFSET                       0x0
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_HSM_EN_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_HSM_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_HSM_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_HSM_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_HSM_EN_DISABLE                       _MK_ENUM_CONST(0)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_HSM_EN_ENABLE                        _MK_ENUM_CONST(1)
+
+// AOCFG1 data pins schmidt enable
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_SCHMT_EN_SHIFT                       _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_SCHMT_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_SCHMT_EN_RANGE                       3:3
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_SCHMT_EN_WOFFSET                     0x0
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_SCHMT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_SCHMT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_SCHMT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_SCHMT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_SCHMT_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_SCHMT_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// AOCFG1 data pins low power mode select
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_LPMD_SHIFT                   _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_LPMD_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_LPMD_SHIFT)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_LPMD_RANGE                   5:4
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_LPMD_WOFFSET                 0x0
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_LPMD_DEFAULT                 _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_LPMD_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_LPMD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_LPMD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVDN_SHIFT                      _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVDN_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVDN_RANGE                      16:12
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVDN_WOFFSET                    0x0
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVDN_DEFAULT                    _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVDN_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVDN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVDN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVUP_SHIFT                      _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVUP_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVUP_RANGE                      24:20
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVUP_WOFFSET                    0x0
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVUP_DEFAULT                    _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVUP_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVUP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVUP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVDN_SLWR_SHIFT                 _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVDN_SLWR_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVDN_SLWR_RANGE                 29:28
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVDN_SLWR_WOFFSET                       0x0
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVDN_SLWR_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVDN_SLWR_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVDN_SLWR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVUP_SLWF_SHIFT                 _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVUP_SLWF_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVUP_SLWF_RANGE                 31:30
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVUP_SLWF_WOFFSET                       0x0
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVUP_SLWF_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVUP_SLWF_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVUP_SLWF_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_AOCFG2PADCTRL_0  //        0       rw  CFG2TMC_AOCFG2_PULLD_EN i=0x0   // AOCFG2 pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_AOCFG2_PULLU_EN i=0x0   // AOCFG2 pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_AOCFG2PADCTRL_0                     _MK_ADDR_CONST(0x86c)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_WORD_COUNT                  0x1
+#define APB_MISC_GP_AOCFG2PADCTRL_0_RESET_VAL                   _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_RESET_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_READ_MASK                   _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_WRITE_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+// AOCFG2 data pins high speed mode enable
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_HSM_EN_SHIFT                 _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_HSM_EN_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_HSM_EN_SHIFT)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_HSM_EN_RANGE                 2:2
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_HSM_EN_WOFFSET                       0x0
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_HSM_EN_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_HSM_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_HSM_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_HSM_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_HSM_EN_DISABLE                       _MK_ENUM_CONST(0)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_HSM_EN_ENABLE                        _MK_ENUM_CONST(1)
+
+// AOCFG2 data pins schmidt enable
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_SCHMT_EN_SHIFT                       _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_SCHMT_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_SCHMT_EN_RANGE                       3:3
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_SCHMT_EN_WOFFSET                     0x0
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_SCHMT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_SCHMT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_SCHMT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_SCHMT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_SCHMT_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_SCHMT_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// AOCFG2 data pins low power mode select
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_LPMD_SHIFT                   _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_LPMD_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_LPMD_SHIFT)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_LPMD_RANGE                   5:4
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_LPMD_WOFFSET                 0x0
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_LPMD_DEFAULT                 _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_LPMD_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_LPMD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_LPMD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVDN_SHIFT                      _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVDN_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVDN_RANGE                      16:12
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVDN_WOFFSET                    0x0
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVDN_DEFAULT                    _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVDN_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVDN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVDN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVUP_SHIFT                      _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVUP_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVUP_RANGE                      24:20
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVUP_WOFFSET                    0x0
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVUP_DEFAULT                    _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVUP_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVUP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVUP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVDN_SLWR_SHIFT                 _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVDN_SLWR_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVDN_SLWR_RANGE                 29:28
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVDN_SLWR_WOFFSET                       0x0
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVDN_SLWR_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVDN_SLWR_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVDN_SLWR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVUP_SLWF_SHIFT                 _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVUP_SLWF_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVUP_SLWF_RANGE                 31:30
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVUP_SLWF_WOFFSET                       0x0
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVUP_SLWF_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVUP_SLWF_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVUP_SLWF_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_ATCFG1PADCTRL_0  //        0       rw  CFG2TMC_ATCFG1_PULLD_EN   i=0x0   // ATCFG1 pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_ATCFG1_PULLU_EN   i=0x0   // ATCFG1 pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_ATCFG1PADCTRL_0                     _MK_ADDR_CONST(0x870)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_WORD_COUNT                  0x1
+#define APB_MISC_GP_ATCFG1PADCTRL_0_RESET_VAL                   _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_RESET_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_READ_MASK                   _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_WRITE_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+// ATCFG1 data pins high speed mode enable
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_HSM_EN_SHIFT                 _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_HSM_EN_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_HSM_EN_SHIFT)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_HSM_EN_RANGE                 2:2
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_HSM_EN_WOFFSET                       0x0
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_HSM_EN_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_HSM_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_HSM_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_HSM_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_HSM_EN_DISABLE                       _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_HSM_EN_ENABLE                        _MK_ENUM_CONST(1)
+
+// ATCFG1 data pins schmidt enable
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_SCHMT_EN_SHIFT                       _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_SCHMT_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_SCHMT_EN_RANGE                       3:3
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_SCHMT_EN_WOFFSET                     0x0
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_SCHMT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_SCHMT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_SCHMT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_SCHMT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_SCHMT_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_SCHMT_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// ATCFG1 data pins low power mode select
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_LPMD_SHIFT                   _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_LPMD_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_LPMD_SHIFT)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_LPMD_RANGE                   5:4
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_LPMD_WOFFSET                 0x0
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_LPMD_DEFAULT                 _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_LPMD_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_LPMD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_LPMD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVDN_SHIFT                      _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVDN_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVDN_RANGE                      16:12
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVDN_WOFFSET                    0x0
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVDN_DEFAULT                    _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVDN_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVDN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVDN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVUP_SHIFT                      _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVUP_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVUP_RANGE                      24:20
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVUP_WOFFSET                    0x0
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVUP_DEFAULT                    _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVUP_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVUP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVUP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVDN_SLWR_SHIFT                 _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVDN_SLWR_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVDN_SLWR_RANGE                 29:28
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVDN_SLWR_WOFFSET                       0x0
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVDN_SLWR_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVDN_SLWR_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVDN_SLWR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVUP_SLWF_SHIFT                 _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVUP_SLWF_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVUP_SLWF_RANGE                 31:30
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVUP_SLWF_WOFFSET                       0x0
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVUP_SLWF_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVUP_SLWF_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVUP_SLWF_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_ATCFG2PADCTRL_0  //        0       rw  CFG2TMC_ATCFG2_PULLD_EN   i=0x0   // ATCFG2 pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_ATCFG2_PULLU_EN   i=0x0   // ATCFG2 pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_ATCFG2PADCTRL_0                     _MK_ADDR_CONST(0x874)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_WORD_COUNT                  0x1
+#define APB_MISC_GP_ATCFG2PADCTRL_0_RESET_VAL                   _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_RESET_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_READ_MASK                   _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_WRITE_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+// ATCFG2 data pins high speed mode enable
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_HSM_EN_SHIFT                 _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_HSM_EN_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_HSM_EN_SHIFT)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_HSM_EN_RANGE                 2:2
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_HSM_EN_WOFFSET                       0x0
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_HSM_EN_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_HSM_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_HSM_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_HSM_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_HSM_EN_DISABLE                       _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_HSM_EN_ENABLE                        _MK_ENUM_CONST(1)
+
+// ATCFG2 data pins schmidt enable
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_SCHMT_EN_SHIFT                       _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_SCHMT_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_SCHMT_EN_RANGE                       3:3
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_SCHMT_EN_WOFFSET                     0x0
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_SCHMT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_SCHMT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_SCHMT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_SCHMT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_SCHMT_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_SCHMT_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// ATCFG2 data pins low power mode select
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_LPMD_SHIFT                   _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_LPMD_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_LPMD_SHIFT)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_LPMD_RANGE                   5:4
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_LPMD_WOFFSET                 0x0
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_LPMD_DEFAULT                 _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_LPMD_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_LPMD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_LPMD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVDN_SHIFT                      _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVDN_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVDN_RANGE                      16:12
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVDN_WOFFSET                    0x0
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVDN_DEFAULT                    _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVDN_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVDN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVDN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVUP_SHIFT                      _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVUP_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVUP_RANGE                      24:20
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVUP_WOFFSET                    0x0
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVUP_DEFAULT                    _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVUP_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVUP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVUP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVDN_SLWR_SHIFT                 _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVDN_SLWR_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVDN_SLWR_RANGE                 29:28
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVDN_SLWR_WOFFSET                       0x0
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVDN_SLWR_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVDN_SLWR_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVDN_SLWR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVUP_SLWF_SHIFT                 _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVUP_SLWF_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVUP_SLWF_RANGE                 31:30
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVUP_SLWF_WOFFSET                       0x0
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVUP_SLWF_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVUP_SLWF_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVUP_SLWF_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_CDEV1CFGPADCTRL_0  //        0       rw  CFG2TMC_CDEV1CFG_PULLD_EN   i=0x0   // CDEV1CFG pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_CDEV1CFG_PULLU_EN   i=0x0   // CDEV1CFG pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0                   _MK_ADDR_CONST(0x878)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_WORD_COUNT                        0x1
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_RESET_VAL                         _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_RESET_MASK                        _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_READ_MASK                         _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_WRITE_MASK                        _MK_MASK_CONST(0xf1f1f03c)
+// CDEV1CFG data pins high speed mode enable
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_HSM_EN_SHIFT                     _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_HSM_EN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_HSM_EN_SHIFT)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_HSM_EN_RANGE                     2:2
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_HSM_EN_WOFFSET                   0x0
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_HSM_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_HSM_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_HSM_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_HSM_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_HSM_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_HSM_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// CDEV1CFG data pins schmidt enable
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_SCHMT_EN_SHIFT                   _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_SCHMT_EN_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_SCHMT_EN_RANGE                   3:3
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_SCHMT_EN_WOFFSET                 0x0
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_SCHMT_EN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_SCHMT_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_SCHMT_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_SCHMT_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_SCHMT_EN_DISABLE                 _MK_ENUM_CONST(0)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_SCHMT_EN_ENABLE                  _MK_ENUM_CONST(1)
+
+// CDEV1CFG data pins low power mode select
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_LPMD_SHIFT                       _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_LPMD_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_LPMD_SHIFT)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_LPMD_RANGE                       5:4
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_LPMD_WOFFSET                     0x0
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_LPMD_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_LPMD_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_LPMD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_LPMD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVDN_SHIFT                  _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVDN_FIELD                  (_MK_MASK_CONST(0x1f) << APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVDN_RANGE                  16:12
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVDN_WOFFSET                        0x0
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVDN_DEFAULT                        _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVDN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVDN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVDN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVUP_SHIFT                  _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVUP_FIELD                  (_MK_MASK_CONST(0x1f) << APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVUP_RANGE                  24:20
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVUP_WOFFSET                        0x0
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVUP_DEFAULT                        _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVUP_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVUP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVUP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVDN_SLWR_SHIFT                     _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVDN_SLWR_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVDN_SLWR_RANGE                     29:28
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVDN_SLWR_WOFFSET                   0x0
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVDN_SLWR_DEFAULT                   _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVDN_SLWR_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVDN_SLWR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVUP_SLWF_SHIFT                     _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVUP_SLWF_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVUP_SLWF_RANGE                     31:30
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVUP_SLWF_WOFFSET                   0x0
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVUP_SLWF_DEFAULT                   _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVUP_SLWF_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVUP_SLWF_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_CDEV2CFGPADCTRL_0  //        0       rw  CFG2TMC_CDEV2CFG_PULLD_EN   i=0x0   // CDEV2CFG pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_CDEV2CFG_PULLU_EN   i=0x0   // CDEV2CFG pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0                   _MK_ADDR_CONST(0x87c)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_WORD_COUNT                        0x1
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_RESET_VAL                         _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_RESET_MASK                        _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_READ_MASK                         _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_WRITE_MASK                        _MK_MASK_CONST(0xf1f1f03c)
+// CDEV2CFG data pins high speed mode enable
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_HSM_EN_SHIFT                     _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_HSM_EN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_HSM_EN_SHIFT)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_HSM_EN_RANGE                     2:2
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_HSM_EN_WOFFSET                   0x0
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_HSM_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_HSM_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_HSM_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_HSM_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_HSM_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_HSM_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// CDEV2CFG data pins schmidt enable
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_SCHMT_EN_SHIFT                   _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_SCHMT_EN_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_SCHMT_EN_RANGE                   3:3
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_SCHMT_EN_WOFFSET                 0x0
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_SCHMT_EN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_SCHMT_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_SCHMT_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_SCHMT_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_SCHMT_EN_DISABLE                 _MK_ENUM_CONST(0)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_SCHMT_EN_ENABLE                  _MK_ENUM_CONST(1)
+
+// CDEV2CFG data pins low power mode select
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_LPMD_SHIFT                       _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_LPMD_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_LPMD_SHIFT)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_LPMD_RANGE                       5:4
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_LPMD_WOFFSET                     0x0
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_LPMD_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_LPMD_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_LPMD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_LPMD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVDN_SHIFT                  _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVDN_FIELD                  (_MK_MASK_CONST(0x1f) << APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVDN_RANGE                  16:12
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVDN_WOFFSET                        0x0
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVDN_DEFAULT                        _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVDN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVDN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVDN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVUP_SHIFT                  _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVUP_FIELD                  (_MK_MASK_CONST(0x1f) << APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVUP_RANGE                  24:20
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVUP_WOFFSET                        0x0
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVUP_DEFAULT                        _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVUP_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVUP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVUP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVDN_SLWR_SHIFT                     _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVDN_SLWR_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVDN_SLWR_RANGE                     29:28
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVDN_SLWR_WOFFSET                   0x0
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVDN_SLWR_DEFAULT                   _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVDN_SLWR_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVDN_SLWR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVUP_SLWF_SHIFT                     _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVUP_SLWF_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVUP_SLWF_RANGE                     31:30
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVUP_SLWF_WOFFSET                   0x0
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVUP_SLWF_DEFAULT                   _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVUP_SLWF_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVUP_SLWF_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_CSUSCFGPADCTRL_0  //        0       rw  CFG2TMC_CSUSCFG_PULLD_EN   i=0x0   // CSUSCFG pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_CSUSCFG_PULLU_EN   i=0x0   // CSUSCFG pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_CSUSCFGPADCTRL_0                    _MK_ADDR_CONST(0x880)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_WORD_COUNT                         0x1
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_RESET_VAL                  _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_RESET_MASK                         _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_READ_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_WRITE_MASK                         _MK_MASK_CONST(0xf1f1f03c)
+// CSUSCFG data pins high speed mode enable
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_HSM_EN_SHIFT                       _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_HSM_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_HSM_EN_SHIFT)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_HSM_EN_RANGE                       2:2
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_HSM_EN_WOFFSET                     0x0
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_HSM_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_HSM_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_HSM_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_HSM_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_HSM_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_HSM_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// CSUSCFG data pins schmidt enable
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_SCHMT_EN_SHIFT                     _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_SCHMT_EN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_SCHMT_EN_RANGE                     3:3
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_SCHMT_EN_WOFFSET                   0x0
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_SCHMT_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_SCHMT_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_SCHMT_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_SCHMT_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_SCHMT_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_SCHMT_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// CSUSCFG data pins low power mode select
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_LPMD_SHIFT                 _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_LPMD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_LPMD_SHIFT)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_LPMD_RANGE                 5:4
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_LPMD_WOFFSET                       0x0
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_LPMD_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_LPMD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_LPMD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_LPMD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVDN_SHIFT                    _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVDN_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVDN_RANGE                    16:12
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVDN_WOFFSET                  0x0
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVDN_DEFAULT                  _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVDN_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVDN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVDN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVUP_SHIFT                    _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVUP_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVUP_RANGE                    24:20
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVUP_WOFFSET                  0x0
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVUP_DEFAULT                  _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVUP_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVUP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVUP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVDN_SLWR_SHIFT                       _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVDN_SLWR_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVDN_SLWR_RANGE                       29:28
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVDN_SLWR_WOFFSET                     0x0
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVDN_SLWR_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVDN_SLWR_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVDN_SLWR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVUP_SLWF_SHIFT                       _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVUP_SLWF_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVUP_SLWF_RANGE                       31:30
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVUP_SLWF_WOFFSET                     0x0
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVUP_SLWF_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVUP_SLWF_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVUP_SLWF_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_DAP1CFGPADCTRL_0  //        0       rw  CFG2TMC_DAP1CFG_PULLD_EN   i=0x0   // DAP1CFG pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_DAP1CFG_PULLU_EN   i=0x0   // DAP1CFG pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_DAP1CFGPADCTRL_0                    _MK_ADDR_CONST(0x884)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_WORD_COUNT                         0x1
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_RESET_VAL                  _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_RESET_MASK                         _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_READ_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_WRITE_MASK                         _MK_MASK_CONST(0xf1f1f03c)
+// DAP1CFG data pins high speed mode enable
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_HSM_EN_SHIFT                       _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_HSM_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_HSM_EN_SHIFT)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_HSM_EN_RANGE                       2:2
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_HSM_EN_WOFFSET                     0x0
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_HSM_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_HSM_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_HSM_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_HSM_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_HSM_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_HSM_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// DAP1CFG data pins schmidt enable
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_SCHMT_EN_SHIFT                     _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_SCHMT_EN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_SCHMT_EN_RANGE                     3:3
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_SCHMT_EN_WOFFSET                   0x0
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_SCHMT_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_SCHMT_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_SCHMT_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_SCHMT_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_SCHMT_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_SCHMT_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// DAP1CFG data pins low power mode select
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_LPMD_SHIFT                 _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_LPMD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_LPMD_SHIFT)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_LPMD_RANGE                 5:4
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_LPMD_WOFFSET                       0x0
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_LPMD_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_LPMD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_LPMD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_LPMD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVDN_SHIFT                    _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVDN_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVDN_RANGE                    16:12
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVDN_WOFFSET                  0x0
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVDN_DEFAULT                  _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVDN_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVDN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVDN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVUP_SHIFT                    _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVUP_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVUP_RANGE                    24:20
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVUP_WOFFSET                  0x0
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVUP_DEFAULT                  _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVUP_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVUP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVUP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVDN_SLWR_SHIFT                       _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVDN_SLWR_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVDN_SLWR_RANGE                       29:28
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVDN_SLWR_WOFFSET                     0x0
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVDN_SLWR_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVDN_SLWR_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVDN_SLWR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVUP_SLWF_SHIFT                       _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVUP_SLWF_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVUP_SLWF_RANGE                       31:30
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVUP_SLWF_WOFFSET                     0x0
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVUP_SLWF_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVUP_SLWF_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVUP_SLWF_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_DAP2CFGPADCTRL_0  //        0       rw  CFG2TMC_DAP2CFG_PULLD_EN   i=0x0   // DAP2CFG pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_DAP2CFG_PULLU_EN   i=0x0   // DAP2CFG pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_DAP2CFGPADCTRL_0                    _MK_ADDR_CONST(0x888)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_WORD_COUNT                         0x1
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_RESET_VAL                  _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_RESET_MASK                         _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_READ_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_WRITE_MASK                         _MK_MASK_CONST(0xf1f1f03c)
+// DAP2CFG data pins high speed mode enable
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_HSM_EN_SHIFT                       _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_HSM_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_HSM_EN_SHIFT)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_HSM_EN_RANGE                       2:2
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_HSM_EN_WOFFSET                     0x0
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_HSM_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_HSM_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_HSM_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_HSM_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_HSM_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_HSM_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// DAP2CFG data pins schmidt enable
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_SCHMT_EN_SHIFT                     _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_SCHMT_EN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_SCHMT_EN_RANGE                     3:3
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_SCHMT_EN_WOFFSET                   0x0
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_SCHMT_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_SCHMT_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_SCHMT_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_SCHMT_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_SCHMT_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_SCHMT_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// DAP2CFG data pins low power mode select
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_LPMD_SHIFT                 _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_LPMD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_LPMD_SHIFT)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_LPMD_RANGE                 5:4
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_LPMD_WOFFSET                       0x0
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_LPMD_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_LPMD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_LPMD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_LPMD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVDN_SHIFT                    _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVDN_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVDN_RANGE                    16:12
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVDN_WOFFSET                  0x0
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVDN_DEFAULT                  _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVDN_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVDN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVDN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVUP_SHIFT                    _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVUP_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVUP_RANGE                    24:20
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVUP_WOFFSET                  0x0
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVUP_DEFAULT                  _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVUP_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVUP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVUP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVDN_SLWR_SHIFT                       _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVDN_SLWR_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVDN_SLWR_RANGE                       29:28
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVDN_SLWR_WOFFSET                     0x0
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVDN_SLWR_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVDN_SLWR_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVDN_SLWR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVUP_SLWF_SHIFT                       _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVUP_SLWF_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVUP_SLWF_RANGE                       31:30
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVUP_SLWF_WOFFSET                     0x0
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVUP_SLWF_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVUP_SLWF_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVUP_SLWF_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_DAP3CFGPADCTRL_0  //        0       rw  CFG2TMC_DAP3CFG_PULLD_EN   i=0x0   // DAP3CFG pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_DAP3CFG_PULLU_EN   i=0x0   // DAP3CFG pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_DAP3CFGPADCTRL_0                    _MK_ADDR_CONST(0x88c)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_WORD_COUNT                         0x1
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_RESET_VAL                  _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_RESET_MASK                         _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_READ_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_WRITE_MASK                         _MK_MASK_CONST(0xf1f1f03c)
+// DAP3CFG data pins high speed mode enable
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_HSM_EN_SHIFT                       _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_HSM_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_HSM_EN_SHIFT)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_HSM_EN_RANGE                       2:2
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_HSM_EN_WOFFSET                     0x0
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_HSM_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_HSM_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_HSM_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_HSM_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_HSM_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_HSM_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// DAP3CFG data pins schmidt enable
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_SCHMT_EN_SHIFT                     _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_SCHMT_EN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_SCHMT_EN_RANGE                     3:3
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_SCHMT_EN_WOFFSET                   0x0
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_SCHMT_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_SCHMT_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_SCHMT_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_SCHMT_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_SCHMT_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_SCHMT_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// DAP3CFG data pins low power mode select
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_LPMD_SHIFT                 _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_LPMD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_LPMD_SHIFT)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_LPMD_RANGE                 5:4
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_LPMD_WOFFSET                       0x0
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_LPMD_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_LPMD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_LPMD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_LPMD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVDN_SHIFT                    _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVDN_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVDN_RANGE                    16:12
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVDN_WOFFSET                  0x0
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVDN_DEFAULT                  _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVDN_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVDN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVDN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVUP_SHIFT                    _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVUP_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVUP_RANGE                    24:20
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVUP_WOFFSET                  0x0
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVUP_DEFAULT                  _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVUP_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVUP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVUP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVDN_SLWR_SHIFT                       _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVDN_SLWR_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVDN_SLWR_RANGE                       29:28
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVDN_SLWR_WOFFSET                     0x0
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVDN_SLWR_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVDN_SLWR_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVDN_SLWR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVUP_SLWF_SHIFT                       _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVUP_SLWF_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVUP_SLWF_RANGE                       31:30
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVUP_SLWF_WOFFSET                     0x0
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVUP_SLWF_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVUP_SLWF_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVUP_SLWF_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_DAP4CFGPADCTRL_0  //        0       rw  CFG2TMC_DAP4CFG_PULLD_EN   i=0x0   // DAP4CFG pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_DAP4CFG_PULLU_EN   i=0x0   // DAP4CFG pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_DAP4CFGPADCTRL_0                    _MK_ADDR_CONST(0x890)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_WORD_COUNT                         0x1
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_RESET_VAL                  _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_RESET_MASK                         _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_READ_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_WRITE_MASK                         _MK_MASK_CONST(0xf1f1f03c)
+// DAP4CFG data pins high speed mode enable
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_HSM_EN_SHIFT                       _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_HSM_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_HSM_EN_SHIFT)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_HSM_EN_RANGE                       2:2
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_HSM_EN_WOFFSET                     0x0
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_HSM_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_HSM_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_HSM_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_HSM_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_HSM_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_HSM_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// DAP4CFG data pins schmidt enable
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_SCHMT_EN_SHIFT                     _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_SCHMT_EN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_SCHMT_EN_RANGE                     3:3
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_SCHMT_EN_WOFFSET                   0x0
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_SCHMT_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_SCHMT_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_SCHMT_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_SCHMT_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_SCHMT_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_SCHMT_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// DAP4CFG data pins low power mode select
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_LPMD_SHIFT                 _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_LPMD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_LPMD_SHIFT)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_LPMD_RANGE                 5:4
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_LPMD_WOFFSET                       0x0
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_LPMD_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_LPMD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_LPMD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_LPMD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVDN_SHIFT                    _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVDN_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVDN_RANGE                    16:12
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVDN_WOFFSET                  0x0
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVDN_DEFAULT                  _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVDN_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVDN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVDN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVUP_SHIFT                    _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVUP_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVUP_RANGE                    24:20
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVUP_WOFFSET                  0x0
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVUP_DEFAULT                  _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVUP_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVUP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVUP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVDN_SLWR_SHIFT                       _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVDN_SLWR_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVDN_SLWR_RANGE                       29:28
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVDN_SLWR_WOFFSET                     0x0
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVDN_SLWR_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVDN_SLWR_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVDN_SLWR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVUP_SLWF_SHIFT                       _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVUP_SLWF_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVUP_SLWF_RANGE                       31:30
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVUP_SLWF_WOFFSET                     0x0
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVUP_SLWF_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVUP_SLWF_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVUP_SLWF_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_DBGCFGPADCTRL_0  //        0       rw  CFG2TMC_DBGCFG_PULLD_EN   i=0x0   // DBGCFG pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_DBGCFG_PULLU_EN   i=0x0   // DBGCFG pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_DBGCFGPADCTRL_0                     _MK_ADDR_CONST(0x894)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_WORD_COUNT                  0x1
+#define APB_MISC_GP_DBGCFGPADCTRL_0_RESET_VAL                   _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_RESET_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_READ_MASK                   _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_WRITE_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+// DBGCFG data pins high speed mode enable
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_HSM_EN_SHIFT                 _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_HSM_EN_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_HSM_EN_SHIFT)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_HSM_EN_RANGE                 2:2
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_HSM_EN_WOFFSET                       0x0
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_HSM_EN_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_HSM_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_HSM_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_HSM_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_HSM_EN_DISABLE                       _MK_ENUM_CONST(0)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_HSM_EN_ENABLE                        _MK_ENUM_CONST(1)
+
+// DBGCFG data pins schmidt enable
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_SCHMT_EN_SHIFT                       _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_SCHMT_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_SCHMT_EN_RANGE                       3:3
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_SCHMT_EN_WOFFSET                     0x0
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_SCHMT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_SCHMT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_SCHMT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_SCHMT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_SCHMT_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_SCHMT_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// DBGCFG data pins low power mode select
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_LPMD_SHIFT                   _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_LPMD_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_LPMD_SHIFT)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_LPMD_RANGE                   5:4
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_LPMD_WOFFSET                 0x0
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_LPMD_DEFAULT                 _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_LPMD_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_LPMD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_LPMD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVDN_SHIFT                      _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVDN_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVDN_RANGE                      16:12
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVDN_WOFFSET                    0x0
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVDN_DEFAULT                    _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVDN_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVDN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVDN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVUP_SHIFT                      _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVUP_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVUP_RANGE                      24:20
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVUP_WOFFSET                    0x0
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVUP_DEFAULT                    _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVUP_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVUP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVUP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVDN_SLWR_SHIFT                 _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVDN_SLWR_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVDN_SLWR_RANGE                 29:28
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVDN_SLWR_WOFFSET                       0x0
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVDN_SLWR_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVDN_SLWR_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVDN_SLWR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVUP_SLWF_SHIFT                 _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVUP_SLWF_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVUP_SLWF_RANGE                 31:30
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVUP_SLWF_WOFFSET                       0x0
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVUP_SLWF_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVUP_SLWF_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVUP_SLWF_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_LCDCFG1PADCTRL_0  //        0       rw  CFG2TMC_LCDCFG1_PULLD_EN   i=0x0   // LCDCFG1 pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_LCDCFG1_PULLU_EN   i=0x0   // LCDCFG1 pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_LCDCFG1PADCTRL_0                    _MK_ADDR_CONST(0x898)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_WORD_COUNT                         0x1
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_RESET_VAL                  _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_RESET_MASK                         _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_READ_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_WRITE_MASK                         _MK_MASK_CONST(0xf1f1f03c)
+// LCDCFG1 data pins high speed mode enable
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_HSM_EN_SHIFT                       _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_HSM_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_HSM_EN_SHIFT)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_HSM_EN_RANGE                       2:2
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_HSM_EN_WOFFSET                     0x0
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_HSM_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_HSM_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_HSM_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_HSM_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_HSM_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_HSM_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// LCDCFG1 data pins schmidt enable
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_SCHMT_EN_SHIFT                     _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_SCHMT_EN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_SCHMT_EN_RANGE                     3:3
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_SCHMT_EN_WOFFSET                   0x0
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_SCHMT_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_SCHMT_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_SCHMT_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_SCHMT_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_SCHMT_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_SCHMT_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// LCDCFG1 data pins low power mode select
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_LPMD_SHIFT                 _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_LPMD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_LPMD_SHIFT)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_LPMD_RANGE                 5:4
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_LPMD_WOFFSET                       0x0
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_LPMD_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_LPMD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_LPMD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_LPMD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVDN_SHIFT                    _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVDN_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVDN_RANGE                    16:12
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVDN_WOFFSET                  0x0
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVDN_DEFAULT                  _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVDN_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVDN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVDN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVUP_SHIFT                    _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVUP_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVUP_RANGE                    24:20
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVUP_WOFFSET                  0x0
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVUP_DEFAULT                  _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVUP_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVUP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVUP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVDN_SLWR_SHIFT                       _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVDN_SLWR_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVDN_SLWR_RANGE                       29:28
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVDN_SLWR_WOFFSET                     0x0
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVDN_SLWR_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVDN_SLWR_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVDN_SLWR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVUP_SLWF_SHIFT                       _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVUP_SLWF_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVUP_SLWF_RANGE                       31:30
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVUP_SLWF_WOFFSET                     0x0
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVUP_SLWF_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVUP_SLWF_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVUP_SLWF_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_LCDCFG2PADCTRL_0  //        0       rw  CFG2TMC_LCDCFG2_PULLD_EN   i=0x0   // LCDCFG2 pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_LCDCFG2_PULLU_EN   i=0x0   // LCDCFG2 pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_LCDCFG2PADCTRL_0                    _MK_ADDR_CONST(0x89c)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_WORD_COUNT                         0x1
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_RESET_VAL                  _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_RESET_MASK                         _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_READ_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_WRITE_MASK                         _MK_MASK_CONST(0xf1f1f03c)
+// LCDCFG2 data pins high speed mode enable
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_HSM_EN_SHIFT                       _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_HSM_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_HSM_EN_SHIFT)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_HSM_EN_RANGE                       2:2
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_HSM_EN_WOFFSET                     0x0
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_HSM_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_HSM_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_HSM_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_HSM_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_HSM_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_HSM_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// LCDCFG2 data pins schmidt enable
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_SCHMT_EN_SHIFT                     _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_SCHMT_EN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_SCHMT_EN_RANGE                     3:3
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_SCHMT_EN_WOFFSET                   0x0
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_SCHMT_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_SCHMT_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_SCHMT_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_SCHMT_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_SCHMT_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_SCHMT_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// LCDCFG2 data pins low power mode select
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_LPMD_SHIFT                 _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_LPMD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_LPMD_SHIFT)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_LPMD_RANGE                 5:4
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_LPMD_WOFFSET                       0x0
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_LPMD_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_LPMD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_LPMD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_LPMD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVDN_SHIFT                    _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVDN_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVDN_RANGE                    16:12
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVDN_WOFFSET                  0x0
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVDN_DEFAULT                  _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVDN_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVDN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVDN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVUP_SHIFT                    _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVUP_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVUP_RANGE                    24:20
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVUP_WOFFSET                  0x0
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVUP_DEFAULT                  _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVUP_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVUP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVUP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVDN_SLWR_SHIFT                       _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVDN_SLWR_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVDN_SLWR_RANGE                       29:28
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVDN_SLWR_WOFFSET                     0x0
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVDN_SLWR_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVDN_SLWR_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVDN_SLWR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVUP_SLWF_SHIFT                       _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVUP_SLWF_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVUP_SLWF_RANGE                       31:30
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVUP_SLWF_WOFFSET                     0x0
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVUP_SLWF_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVUP_SLWF_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVUP_SLWF_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_SDIO2CFGPADCTRL_0  //        0       rw  CFG2TMC_SDIO2CFG_PULLD_EN   i=0x0   // SDIO2CFG pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_SDIO2CFG_PULLU_EN   i=0x0   // SDIO2CFG pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0                   _MK_ADDR_CONST(0x8a0)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_WORD_COUNT                        0x1
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_RESET_VAL                         _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_RESET_MASK                        _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_READ_MASK                         _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_WRITE_MASK                        _MK_MASK_CONST(0xf1f1f03c)
+// SDIO2CFG data pins high speed mode enable
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_HSM_EN_SHIFT                     _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_HSM_EN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_HSM_EN_SHIFT)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_HSM_EN_RANGE                     2:2
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_HSM_EN_WOFFSET                   0x0
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_HSM_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_HSM_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_HSM_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_HSM_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_HSM_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_HSM_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// SDIO2CFG data pins schmidt enable
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_SCHMT_EN_SHIFT                   _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_SCHMT_EN_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_SCHMT_EN_RANGE                   3:3
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_SCHMT_EN_WOFFSET                 0x0
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_SCHMT_EN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_SCHMT_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_SCHMT_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_SCHMT_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_SCHMT_EN_DISABLE                 _MK_ENUM_CONST(0)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_SCHMT_EN_ENABLE                  _MK_ENUM_CONST(1)
+
+// SDIO2CFG data pins low power mode select
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_LPMD_SHIFT                       _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_LPMD_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_LPMD_SHIFT)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_LPMD_RANGE                       5:4
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_LPMD_WOFFSET                     0x0
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_LPMD_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_LPMD_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_LPMD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_LPMD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVDN_SHIFT                  _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVDN_FIELD                  (_MK_MASK_CONST(0x1f) << APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVDN_RANGE                  16:12
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVDN_WOFFSET                        0x0
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVDN_DEFAULT                        _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVDN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVDN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVDN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVUP_SHIFT                  _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVUP_FIELD                  (_MK_MASK_CONST(0x1f) << APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVUP_RANGE                  24:20
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVUP_WOFFSET                        0x0
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVUP_DEFAULT                        _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVUP_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVUP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVUP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVDN_SLWR_SHIFT                     _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVDN_SLWR_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVDN_SLWR_RANGE                     29:28
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVDN_SLWR_WOFFSET                   0x0
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVDN_SLWR_DEFAULT                   _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVDN_SLWR_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVDN_SLWR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVUP_SLWF_SHIFT                     _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVUP_SLWF_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVUP_SLWF_RANGE                     31:30
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVUP_SLWF_WOFFSET                   0x0
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVUP_SLWF_DEFAULT                   _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVUP_SLWF_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVUP_SLWF_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_SDIO3CFGPADCTRL_0  //        0       rw  CFG2TMC_SDIO3CFG_PULLD_EN   i=0x0   // SDIO3CFG pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_SDIO3CFG_PULLU_EN   i=0x0   // SDIO3CFG pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0                   _MK_ADDR_CONST(0x8a4)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_WORD_COUNT                        0x1
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_RESET_VAL                         _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_RESET_MASK                        _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_READ_MASK                         _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_WRITE_MASK                        _MK_MASK_CONST(0xf1f1f03c)
+// SDIO3CFG data pins high speed mode enable
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_HSM_EN_SHIFT                     _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_HSM_EN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_HSM_EN_SHIFT)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_HSM_EN_RANGE                     2:2
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_HSM_EN_WOFFSET                   0x0
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_HSM_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_HSM_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_HSM_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_HSM_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_HSM_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_HSM_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// SDIO3CFG data pins schmidt enable
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_SCHMT_EN_SHIFT                   _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_SCHMT_EN_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_SCHMT_EN_RANGE                   3:3
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_SCHMT_EN_WOFFSET                 0x0
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_SCHMT_EN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_SCHMT_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_SCHMT_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_SCHMT_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_SCHMT_EN_DISABLE                 _MK_ENUM_CONST(0)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_SCHMT_EN_ENABLE                  _MK_ENUM_CONST(1)
+
+// SDIO3CFG data pins low power mode select
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_LPMD_SHIFT                       _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_LPMD_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_LPMD_SHIFT)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_LPMD_RANGE                       5:4
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_LPMD_WOFFSET                     0x0
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_LPMD_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_LPMD_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_LPMD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_LPMD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVDN_SHIFT                  _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVDN_FIELD                  (_MK_MASK_CONST(0x1f) << APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVDN_RANGE                  16:12
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVDN_WOFFSET                        0x0
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVDN_DEFAULT                        _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVDN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVDN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVDN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVUP_SHIFT                  _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVUP_FIELD                  (_MK_MASK_CONST(0x1f) << APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVUP_RANGE                  24:20
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVUP_WOFFSET                        0x0
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVUP_DEFAULT                        _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVUP_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVUP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVUP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVDN_SLWR_SHIFT                     _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVDN_SLWR_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVDN_SLWR_RANGE                     29:28
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVDN_SLWR_WOFFSET                   0x0
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVDN_SLWR_DEFAULT                   _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVDN_SLWR_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVDN_SLWR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVUP_SLWF_SHIFT                     _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVUP_SLWF_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVUP_SLWF_RANGE                     31:30
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVUP_SLWF_WOFFSET                   0x0
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVUP_SLWF_DEFAULT                   _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVUP_SLWF_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVUP_SLWF_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_SPICFGPADCTRL_0  //        0       rw  CFG2TMC_SPICFG_PULLD_EN   i=0x0   // SPICFG pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_SPICFG_PULLU_EN   i=0x0   // SPICFG pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_SPICFGPADCTRL_0                     _MK_ADDR_CONST(0x8a8)
+#define APB_MISC_GP_SPICFGPADCTRL_0_WORD_COUNT                  0x1
+#define APB_MISC_GP_SPICFGPADCTRL_0_RESET_VAL                   _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_SPICFGPADCTRL_0_RESET_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_SPICFGPADCTRL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SPICFGPADCTRL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SPICFGPADCTRL_0_READ_MASK                   _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_SPICFGPADCTRL_0_WRITE_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+// SPICFG data pins high speed mode enable
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_HSM_EN_SHIFT                 _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_HSM_EN_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_HSM_EN_SHIFT)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_HSM_EN_RANGE                 2:2
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_HSM_EN_WOFFSET                       0x0
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_HSM_EN_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_HSM_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_HSM_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_HSM_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_HSM_EN_DISABLE                       _MK_ENUM_CONST(0)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_HSM_EN_ENABLE                        _MK_ENUM_CONST(1)
+
+// SPICFG data pins schmidt enable
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_SCHMT_EN_SHIFT                       _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_SCHMT_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_SCHMT_EN_RANGE                       3:3
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_SCHMT_EN_WOFFSET                     0x0
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_SCHMT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_SCHMT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_SCHMT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_SCHMT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_SCHMT_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_SCHMT_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// SPICFG data pins low power mode select
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_LPMD_SHIFT                   _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_LPMD_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_LPMD_SHIFT)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_LPMD_RANGE                   5:4
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_LPMD_WOFFSET                 0x0
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_LPMD_DEFAULT                 _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_LPMD_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_LPMD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_LPMD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVDN_SHIFT                      _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVDN_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVDN_RANGE                      16:12
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVDN_WOFFSET                    0x0
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVDN_DEFAULT                    _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVDN_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVDN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVDN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVUP_SHIFT                      _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVUP_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVUP_RANGE                      24:20
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVUP_WOFFSET                    0x0
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVUP_DEFAULT                    _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVUP_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVUP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVUP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVDN_SLWR_SHIFT                 _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVDN_SLWR_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVDN_SLWR_RANGE                 29:28
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVDN_SLWR_WOFFSET                       0x0
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVDN_SLWR_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVDN_SLWR_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVDN_SLWR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVUP_SLWF_SHIFT                 _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVUP_SLWF_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVUP_SLWF_RANGE                 31:30
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVUP_SLWF_WOFFSET                       0x0
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVUP_SLWF_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVUP_SLWF_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVUP_SLWF_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_UAACFGPADCTRL_0  //        0       rw  CFG2TMC_UAACFG_PULLD_EN   i=0x0   // UAACFG pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_UAACFG_PULLU_EN   i=0x0   // UAACFG pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_UAACFGPADCTRL_0                     _MK_ADDR_CONST(0x8ac)
+#define APB_MISC_GP_UAACFGPADCTRL_0_WORD_COUNT                  0x1
+#define APB_MISC_GP_UAACFGPADCTRL_0_RESET_VAL                   _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_UAACFGPADCTRL_0_RESET_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_UAACFGPADCTRL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UAACFGPADCTRL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UAACFGPADCTRL_0_READ_MASK                   _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_UAACFGPADCTRL_0_WRITE_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+// UAACFG data pins high speed mode enable
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_HSM_EN_SHIFT                 _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_HSM_EN_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_HSM_EN_SHIFT)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_HSM_EN_RANGE                 2:2
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_HSM_EN_WOFFSET                       0x0
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_HSM_EN_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_HSM_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_HSM_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_HSM_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_HSM_EN_DISABLE                       _MK_ENUM_CONST(0)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_HSM_EN_ENABLE                        _MK_ENUM_CONST(1)
+
+// UAACFG data pins schmidt enable
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_SCHMT_EN_SHIFT                       _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_SCHMT_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_SCHMT_EN_RANGE                       3:3
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_SCHMT_EN_WOFFSET                     0x0
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_SCHMT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_SCHMT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_SCHMT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_SCHMT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_SCHMT_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_SCHMT_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// UAACFG data pins low power mode select
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_LPMD_SHIFT                   _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_LPMD_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_LPMD_SHIFT)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_LPMD_RANGE                   5:4
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_LPMD_WOFFSET                 0x0
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_LPMD_DEFAULT                 _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_LPMD_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_LPMD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_LPMD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVDN_SHIFT                      _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVDN_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVDN_RANGE                      16:12
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVDN_WOFFSET                    0x0
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVDN_DEFAULT                    _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVDN_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVDN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVDN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVUP_SHIFT                      _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVUP_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVUP_RANGE                      24:20
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVUP_WOFFSET                    0x0
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVUP_DEFAULT                    _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVUP_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVUP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVUP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVDN_SLWR_SHIFT                 _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVDN_SLWR_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVDN_SLWR_RANGE                 29:28
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVDN_SLWR_WOFFSET                       0x0
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVDN_SLWR_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVDN_SLWR_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVDN_SLWR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVUP_SLWF_SHIFT                 _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVUP_SLWF_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVUP_SLWF_RANGE                 31:30
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVUP_SLWF_WOFFSET                       0x0
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVUP_SLWF_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVUP_SLWF_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVUP_SLWF_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_UABCFGPADCTRL_0  //        0       rw  CFG2TMC_UABCFG_PULLD_EN   i=0x0   // UABCFG pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_UABCFG_PULLU_EN   i=0x0   // UABCFG pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_UABCFGPADCTRL_0                     _MK_ADDR_CONST(0x8b0)
+#define APB_MISC_GP_UABCFGPADCTRL_0_WORD_COUNT                  0x1
+#define APB_MISC_GP_UABCFGPADCTRL_0_RESET_VAL                   _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_UABCFGPADCTRL_0_RESET_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_UABCFGPADCTRL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UABCFGPADCTRL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UABCFGPADCTRL_0_READ_MASK                   _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_UABCFGPADCTRL_0_WRITE_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+// UABCFG data pins high speed mode enable
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_HSM_EN_SHIFT                 _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_HSM_EN_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_HSM_EN_SHIFT)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_HSM_EN_RANGE                 2:2
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_HSM_EN_WOFFSET                       0x0
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_HSM_EN_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_HSM_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_HSM_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_HSM_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_HSM_EN_DISABLE                       _MK_ENUM_CONST(0)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_HSM_EN_ENABLE                        _MK_ENUM_CONST(1)
+
+// UABCFG data pins schmidt enable
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_SCHMT_EN_SHIFT                       _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_SCHMT_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_SCHMT_EN_RANGE                       3:3
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_SCHMT_EN_WOFFSET                     0x0
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_SCHMT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_SCHMT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_SCHMT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_SCHMT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_SCHMT_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_SCHMT_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// UABCFG data pins low power mode select
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_LPMD_SHIFT                   _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_LPMD_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_LPMD_SHIFT)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_LPMD_RANGE                   5:4
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_LPMD_WOFFSET                 0x0
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_LPMD_DEFAULT                 _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_LPMD_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_LPMD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_LPMD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVDN_SHIFT                      _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVDN_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVDN_RANGE                      16:12
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVDN_WOFFSET                    0x0
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVDN_DEFAULT                    _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVDN_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVDN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVDN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVUP_SHIFT                      _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVUP_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVUP_RANGE                      24:20
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVUP_WOFFSET                    0x0
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVUP_DEFAULT                    _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVUP_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVUP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVUP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVDN_SLWR_SHIFT                 _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVDN_SLWR_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVDN_SLWR_RANGE                 29:28
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVDN_SLWR_WOFFSET                       0x0
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVDN_SLWR_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVDN_SLWR_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVDN_SLWR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVUP_SLWF_SHIFT                 _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVUP_SLWF_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVUP_SLWF_RANGE                 31:30
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVUP_SLWF_WOFFSET                       0x0
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVUP_SLWF_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVUP_SLWF_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVUP_SLWF_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_UART2CFGPADCTRL_0  //        0       rw  CFG2TMC_UART2CFG_PULLD_EN   i=0x0   // UART2CFG pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_UART2CFG_PULLU_EN   i=0x0   // UART2CFG pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_UART2CFGPADCTRL_0                   _MK_ADDR_CONST(0x8b4)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_WORD_COUNT                        0x1
+#define APB_MISC_GP_UART2CFGPADCTRL_0_RESET_VAL                         _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_RESET_MASK                        _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_READ_MASK                         _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_WRITE_MASK                        _MK_MASK_CONST(0xf1f1f03c)
+// UART2CFG data pins high speed mode enable
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_HSM_EN_SHIFT                     _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_HSM_EN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_HSM_EN_SHIFT)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_HSM_EN_RANGE                     2:2
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_HSM_EN_WOFFSET                   0x0
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_HSM_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_HSM_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_HSM_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_HSM_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_HSM_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_HSM_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// UART2CFG data pins schmidt enable
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_SCHMT_EN_SHIFT                   _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_SCHMT_EN_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_SCHMT_EN_RANGE                   3:3
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_SCHMT_EN_WOFFSET                 0x0
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_SCHMT_EN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_SCHMT_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_SCHMT_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_SCHMT_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_SCHMT_EN_DISABLE                 _MK_ENUM_CONST(0)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_SCHMT_EN_ENABLE                  _MK_ENUM_CONST(1)
+
+// UART2CFG data pins low power mode select
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_LPMD_SHIFT                       _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_LPMD_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_LPMD_SHIFT)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_LPMD_RANGE                       5:4
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_LPMD_WOFFSET                     0x0
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_LPMD_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_LPMD_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_LPMD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_LPMD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVDN_SHIFT                  _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVDN_FIELD                  (_MK_MASK_CONST(0x1f) << APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVDN_RANGE                  16:12
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVDN_WOFFSET                        0x0
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVDN_DEFAULT                        _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVDN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVDN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVDN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVUP_SHIFT                  _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVUP_FIELD                  (_MK_MASK_CONST(0x1f) << APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVUP_RANGE                  24:20
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVUP_WOFFSET                        0x0
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVUP_DEFAULT                        _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVUP_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVUP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVUP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVDN_SLWR_SHIFT                     _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVDN_SLWR_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVDN_SLWR_RANGE                     29:28
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVDN_SLWR_WOFFSET                   0x0
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVDN_SLWR_DEFAULT                   _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVDN_SLWR_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVDN_SLWR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVUP_SLWF_SHIFT                     _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVUP_SLWF_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVUP_SLWF_RANGE                     31:30
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVUP_SLWF_WOFFSET                   0x0
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVUP_SLWF_DEFAULT                   _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVUP_SLWF_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVUP_SLWF_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_UART3CFGPADCTRL_0  //        0       rw  CFG2TMC_UART3CFG_PULLD_EN   i=0x0   // UART3CFG pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_UART3CFG_PULLU_EN   i=0x0   // UART3CFG pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_UART3CFGPADCTRL_0                   _MK_ADDR_CONST(0x8b8)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_WORD_COUNT                        0x1
+#define APB_MISC_GP_UART3CFGPADCTRL_0_RESET_VAL                         _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_RESET_MASK                        _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_READ_MASK                         _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_WRITE_MASK                        _MK_MASK_CONST(0xf1f1f03c)
+// UART3CFG data pins high speed mode enable
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_HSM_EN_SHIFT                     _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_HSM_EN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_HSM_EN_SHIFT)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_HSM_EN_RANGE                     2:2
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_HSM_EN_WOFFSET                   0x0
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_HSM_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_HSM_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_HSM_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_HSM_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_HSM_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_HSM_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// UART3CFG data pins schmidt enable
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_SCHMT_EN_SHIFT                   _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_SCHMT_EN_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_SCHMT_EN_RANGE                   3:3
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_SCHMT_EN_WOFFSET                 0x0
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_SCHMT_EN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_SCHMT_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_SCHMT_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_SCHMT_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_SCHMT_EN_DISABLE                 _MK_ENUM_CONST(0)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_SCHMT_EN_ENABLE                  _MK_ENUM_CONST(1)
+
+// UART3CFG data pins low power mode select
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_LPMD_SHIFT                       _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_LPMD_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_LPMD_SHIFT)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_LPMD_RANGE                       5:4
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_LPMD_WOFFSET                     0x0
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_LPMD_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_LPMD_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_LPMD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_LPMD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVDN_SHIFT                  _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVDN_FIELD                  (_MK_MASK_CONST(0x1f) << APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVDN_RANGE                  16:12
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVDN_WOFFSET                        0x0
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVDN_DEFAULT                        _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVDN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVDN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVDN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVUP_SHIFT                  _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVUP_FIELD                  (_MK_MASK_CONST(0x1f) << APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVUP_RANGE                  24:20
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVUP_WOFFSET                        0x0
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVUP_DEFAULT                        _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVUP_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVUP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVUP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVDN_SLWR_SHIFT                     _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVDN_SLWR_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVDN_SLWR_RANGE                     29:28
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVDN_SLWR_WOFFSET                   0x0
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVDN_SLWR_DEFAULT                   _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVDN_SLWR_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVDN_SLWR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVUP_SLWF_SHIFT                     _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVUP_SLWF_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVUP_SLWF_RANGE                     31:30
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVUP_SLWF_WOFFSET                   0x0
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVUP_SLWF_DEFAULT                   _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVUP_SLWF_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVUP_SLWF_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_VICFG1PADCTRL_0  //        0       rw  CFG2TMC_VICFG1_PULLD_EN   i=0x0   // VICFG1 pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_VICFG1_PULLU_EN   i=0x0   // VICFG1 pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_VICFG1PADCTRL_0                     _MK_ADDR_CONST(0x8bc)
+#define APB_MISC_GP_VICFG1PADCTRL_0_WORD_COUNT                  0x1
+#define APB_MISC_GP_VICFG1PADCTRL_0_RESET_VAL                   _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_VICFG1PADCTRL_0_RESET_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_VICFG1PADCTRL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG1PADCTRL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG1PADCTRL_0_READ_MASK                   _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_VICFG1PADCTRL_0_WRITE_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+// VICFG1 data pins high speed mode enable
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_HSM_EN_SHIFT                 _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_HSM_EN_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_HSM_EN_SHIFT)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_HSM_EN_RANGE                 2:2
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_HSM_EN_WOFFSET                       0x0
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_HSM_EN_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_HSM_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_HSM_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_HSM_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_HSM_EN_DISABLE                       _MK_ENUM_CONST(0)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_HSM_EN_ENABLE                        _MK_ENUM_CONST(1)
+
+// VICFG1 data pins schmidt enable
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_SCHMT_EN_SHIFT                       _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_SCHMT_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_SCHMT_EN_RANGE                       3:3
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_SCHMT_EN_WOFFSET                     0x0
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_SCHMT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_SCHMT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_SCHMT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_SCHMT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_SCHMT_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_SCHMT_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// VICFG1 data pins low power mode select
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_LPMD_SHIFT                   _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_LPMD_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_LPMD_SHIFT)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_LPMD_RANGE                   5:4
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_LPMD_WOFFSET                 0x0
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_LPMD_DEFAULT                 _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_LPMD_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_LPMD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_LPMD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVDN_SHIFT                      _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVDN_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVDN_RANGE                      16:12
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVDN_WOFFSET                    0x0
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVDN_DEFAULT                    _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVDN_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVDN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVDN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVUP_SHIFT                      _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVUP_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVUP_RANGE                      24:20
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVUP_WOFFSET                    0x0
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVUP_DEFAULT                    _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVUP_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVUP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVUP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVDN_SLWR_SHIFT                 _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVDN_SLWR_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVDN_SLWR_RANGE                 29:28
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVDN_SLWR_WOFFSET                       0x0
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVDN_SLWR_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVDN_SLWR_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVDN_SLWR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVUP_SLWF_SHIFT                 _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVUP_SLWF_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVUP_SLWF_RANGE                 31:30
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVUP_SLWF_WOFFSET                       0x0
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVUP_SLWF_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVUP_SLWF_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVUP_SLWF_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_VICFG2PADCTRL_0  //        0       rw  CFG2TMC_VICFG2_PULLD_EN   i=0x0   // VICFG2 pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_VICFG2_PULLU_EN   i=0x0   // VICFG2 pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_VICFG2PADCTRL_0                     _MK_ADDR_CONST(0x8c0)
+#define APB_MISC_GP_VICFG2PADCTRL_0_WORD_COUNT                  0x1
+#define APB_MISC_GP_VICFG2PADCTRL_0_RESET_VAL                   _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_VICFG2PADCTRL_0_RESET_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_VICFG2PADCTRL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG2PADCTRL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG2PADCTRL_0_READ_MASK                   _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_VICFG2PADCTRL_0_WRITE_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+// VICFG2 data pins high speed mode enable
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_HSM_EN_SHIFT                 _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_HSM_EN_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_HSM_EN_SHIFT)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_HSM_EN_RANGE                 2:2
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_HSM_EN_WOFFSET                       0x0
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_HSM_EN_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_HSM_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_HSM_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_HSM_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_HSM_EN_DISABLE                       _MK_ENUM_CONST(0)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_HSM_EN_ENABLE                        _MK_ENUM_CONST(1)
+
+// VICFG2 data pins schmidt enable
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_SCHMT_EN_SHIFT                       _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_SCHMT_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_SCHMT_EN_RANGE                       3:3
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_SCHMT_EN_WOFFSET                     0x0
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_SCHMT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_SCHMT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_SCHMT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_SCHMT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_SCHMT_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_SCHMT_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// VICFG2 data pins low power mode select
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_LPMD_SHIFT                   _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_LPMD_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_LPMD_SHIFT)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_LPMD_RANGE                   5:4
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_LPMD_WOFFSET                 0x0
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_LPMD_DEFAULT                 _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_LPMD_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_LPMD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_LPMD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVDN_SHIFT                      _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVDN_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVDN_RANGE                      16:12
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVDN_WOFFSET                    0x0
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVDN_DEFAULT                    _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVDN_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVDN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVDN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVUP_SHIFT                      _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVUP_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVUP_RANGE                      24:20
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVUP_WOFFSET                    0x0
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVUP_DEFAULT                    _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVUP_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVUP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVUP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVDN_SLWR_SHIFT                 _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVDN_SLWR_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVDN_SLWR_RANGE                 29:28
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVDN_SLWR_WOFFSET                       0x0
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVDN_SLWR_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVDN_SLWR_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVDN_SLWR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVUP_SLWF_SHIFT                 _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVUP_SLWF_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVUP_SLWF_RANGE                 31:30
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVUP_SLWF_WOFFSET                       0x0
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVUP_SLWF_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVUP_SLWF_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVUP_SLWF_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_XM2CFGAPADCTRL_0  //        0       rw  CFG2TMC_XM2CFGA_PULLD_EN   i=0x0 // XM2CFGA pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_XM2CFGA_PULLU_EN i=0x0   // XM2CFGA pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_XM2CFGAPADCTRL_0                    _MK_ADDR_CONST(0x8c4)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_WORD_COUNT                         0x1
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_RESET_VAL                  _MK_MASK_CONST(0xf1f1f030)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_RESET_MASK                         _MK_MASK_CONST(0xf1f1f074)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_READ_MASK                  _MK_MASK_CONST(0xf1f1f074)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_WRITE_MASK                         _MK_MASK_CONST(0xf1f1f074)
+// XM2CFGA data pins high speed mode enable        3       rw  CFG2TMC_XM2CFGA_SCHMT_EN i=0x0   // XM2CFGA data pins schmidt enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_HSM_EN_SHIFT                       _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_HSM_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_HSM_EN_SHIFT)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_HSM_EN_RANGE                       2:2
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_HSM_EN_WOFFSET                     0x0
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_HSM_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_HSM_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_HSM_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_HSM_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_HSM_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_HSM_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// XM2CFGA data pins low power mode select
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_LPMD_SHIFT                 _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_LPMD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_LPMD_SHIFT)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_LPMD_RANGE                 5:4
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_LPMD_WOFFSET                       0x0
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_LPMD_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_LPMD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_LPMD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_LPMD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// XM2CFGA data pins vref enable
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_VREF_EN_SHIFT                      _MK_SHIFT_CONST(6)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_VREF_EN_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_VREF_EN_SHIFT)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_VREF_EN_RANGE                      6:6
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_VREF_EN_WOFFSET                    0x0
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_VREF_EN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_VREF_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_VREF_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_VREF_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_VREF_EN_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_VREF_EN_ENABLE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVDN_SHIFT                    _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVDN_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVDN_RANGE                    16:12
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVDN_WOFFSET                  0x0
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVDN_DEFAULT                  _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVDN_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVDN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVDN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVUP_SHIFT                    _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVUP_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVUP_RANGE                    24:20
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVUP_WOFFSET                  0x0
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVUP_DEFAULT                  _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVUP_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVUP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVUP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVDN_SLWR_SHIFT                       _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVDN_SLWR_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVDN_SLWR_RANGE                       29:28
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVDN_SLWR_WOFFSET                     0x0
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVDN_SLWR_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVDN_SLWR_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVDN_SLWR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVUP_SLWF_SHIFT                       _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVUP_SLWF_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVUP_SLWF_RANGE                       31:30
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVUP_SLWF_WOFFSET                     0x0
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVUP_SLWF_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVUP_SLWF_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVUP_SLWF_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_XM2CFGCPADCTRL_0  //        0       rw  CFG2TMC_XM2CFGC_PULLD_EN   i=0x0   // XM2CFGC pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_XM2CFGC_PULLU_EN   i=0x0   // XM2CFGC pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_XM2CFGCPADCTRL_0                    _MK_ADDR_CONST(0x8c8)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_WORD_COUNT                         0x1
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_RESET_VAL                  _MK_MASK_CONST(0xf1f1f030)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_RESET_MASK                         _MK_MASK_CONST(0xf1f1f07c)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_READ_MASK                  _MK_MASK_CONST(0xf1f1f07c)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_WRITE_MASK                         _MK_MASK_CONST(0xf1f1f07c)
+// XM2CFGC data pins high speed mode enable
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_HSM_EN_SHIFT                       _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_HSM_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_HSM_EN_SHIFT)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_HSM_EN_RANGE                       2:2
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_HSM_EN_WOFFSET                     0x0
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_HSM_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_HSM_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_HSM_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_HSM_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_HSM_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_HSM_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// XM2CFGC data pins schmidt enable
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_SCHMT_EN_SHIFT                     _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_SCHMT_EN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_SCHMT_EN_RANGE                     3:3
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_SCHMT_EN_WOFFSET                   0x0
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_SCHMT_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_SCHMT_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_SCHMT_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_SCHMT_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_SCHMT_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_SCHMT_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// XM2CFGC data pins low power mode select
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_LPMD_SHIFT                 _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_LPMD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_LPMD_SHIFT)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_LPMD_RANGE                 5:4
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_LPMD_WOFFSET                       0x0
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_LPMD_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_LPMD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_LPMD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_LPMD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// XM2CFGC data pins vref enable
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_VREF_EN_SHIFT                      _MK_SHIFT_CONST(6)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_VREF_EN_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_VREF_EN_SHIFT)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_VREF_EN_RANGE                      6:6
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_VREF_EN_WOFFSET                    0x0
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_VREF_EN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_VREF_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_VREF_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_VREF_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_VREF_EN_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_VREF_EN_ENABLE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_SHIFT                    _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_RANGE                    16:12
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_WOFFSET                  0x0
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_DEFAULT                  _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_SHIFT                    _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_RANGE                    24:20
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_WOFFSET                  0x0
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_DEFAULT                  _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_SLWR_SHIFT                       _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_SLWR_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_SLWR_RANGE                       29:28
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_SLWR_WOFFSET                     0x0
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_SLWR_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_SLWR_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_SLWR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_SLWF_SHIFT                       _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_SLWF_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_SLWF_RANGE                       31:30
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_SLWF_WOFFSET                     0x0
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_SLWF_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_SLWF_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_SLWF_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_XM2CFGDPADCTRL_0  //        0       rw  CFG2TMC_XM2CFGD_PULLD_EN   i=0x0   // XM2CFGD pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_XM2CFGD_PULLU_EN   i=0x0   // XM2CFGD pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_XM2CFGDPADCTRL_0                    _MK_ADDR_CONST(0x8cc)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_WORD_COUNT                         0x1
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_RESET_VAL                  _MK_MASK_CONST(0xf1f1f030)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_RESET_MASK                         _MK_MASK_CONST(0xf1f1f07c)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_READ_MASK                  _MK_MASK_CONST(0xf1f1f07c)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_WRITE_MASK                         _MK_MASK_CONST(0xf1f1f07c)
+// XM2CFGD data pins high speed mode enable
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_HSM_EN_SHIFT                       _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_HSM_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_HSM_EN_SHIFT)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_HSM_EN_RANGE                       2:2
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_HSM_EN_WOFFSET                     0x0
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_HSM_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_HSM_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_HSM_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_HSM_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_HSM_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_HSM_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// XM2CFGD data pins schmidt enable
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_SCHMT_EN_SHIFT                     _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_SCHMT_EN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_SCHMT_EN_RANGE                     3:3
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_SCHMT_EN_WOFFSET                   0x0
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_SCHMT_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_SCHMT_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_SCHMT_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_SCHMT_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_SCHMT_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_SCHMT_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// XM2CFGD data pins low power mode select
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_LPMD_SHIFT                 _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_LPMD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_LPMD_SHIFT)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_LPMD_RANGE                 5:4
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_LPMD_WOFFSET                       0x0
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_LPMD_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_LPMD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_LPMD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_LPMD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// XM2CFGD data pins vref enable
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_VREF_EN_SHIFT                      _MK_SHIFT_CONST(6)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_VREF_EN_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_VREF_EN_SHIFT)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_VREF_EN_RANGE                      6:6
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_VREF_EN_WOFFSET                    0x0
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_VREF_EN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_VREF_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_VREF_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_VREF_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_VREF_EN_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_VREF_EN_ENABLE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_SHIFT                    _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_RANGE                    16:12
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_WOFFSET                  0x0
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_DEFAULT                  _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_SHIFT                    _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_RANGE                    24:20
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_WOFFSET                  0x0
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_DEFAULT                  _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_SLWR_SHIFT                       _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_SLWR_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_SLWR_RANGE                       29:28
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_SLWR_WOFFSET                     0x0
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_SLWR_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_SLWR_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_SLWR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_SLWF_SHIFT                       _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_SLWF_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_SLWF_RANGE                       31:30
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_SLWF_WOFFSET                     0x0
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_SLWF_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_SLWF_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_SLWF_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_XM2CLKCFGPADCTRL_0  //        0       rw  CFG2TMC_XM2CLKCFG_PULLD_EN   i=0x0   // XM2CLKCFG pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_XM2CLKCFG_PULLU_EN   i=0x0   // XM2CLKCFG pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0                  _MK_ADDR_CONST(0x8d0)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_WORD_COUNT                       0x1
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_RESET_VAL                        _MK_MASK_CONST(0xf1f1f030)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_RESET_MASK                       _MK_MASK_CONST(0xf1f1f07c)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_READ_MASK                        _MK_MASK_CONST(0xf1f1f07c)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_WRITE_MASK                       _MK_MASK_CONST(0xf1f1f07c)
+// XM2CLKCFG data pins high speed mode enable
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_HSM_EN_SHIFT                   _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_HSM_EN_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_HSM_EN_SHIFT)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_HSM_EN_RANGE                   2:2
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_HSM_EN_WOFFSET                 0x0
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_HSM_EN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_HSM_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_HSM_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_HSM_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_HSM_EN_DISABLE                 _MK_ENUM_CONST(0)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_HSM_EN_ENABLE                  _MK_ENUM_CONST(1)
+
+// XM2CLKCFG data pins schmidt enable
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_SCHMT_EN_SHIFT                 _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_SCHMT_EN_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_SCHMT_EN_RANGE                 3:3
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_SCHMT_EN_WOFFSET                       0x0
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_SCHMT_EN_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_SCHMT_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_SCHMT_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_SCHMT_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_SCHMT_EN_DISABLE                       _MK_ENUM_CONST(0)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_SCHMT_EN_ENABLE                        _MK_ENUM_CONST(1)
+
+// XM2CLKCFG data pins low power mode select
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_LPMD_SHIFT                     _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_LPMD_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_LPMD_SHIFT)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_LPMD_RANGE                     5:4
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_LPMD_WOFFSET                   0x0
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_LPMD_DEFAULT                   _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_LPMD_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_LPMD_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_LPMD_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// XM2CLKCFG data pins vref enable
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_VREF_EN_SHIFT                  _MK_SHIFT_CONST(6)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_VREF_EN_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_VREF_EN_SHIFT)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_VREF_EN_RANGE                  6:6
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_VREF_EN_WOFFSET                        0x0
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_VREF_EN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_VREF_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_VREF_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_VREF_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_VREF_EN_DISABLE                        _MK_ENUM_CONST(0)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_VREF_EN_ENABLE                 _MK_ENUM_CONST(1)
+
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVDN_SHIFT                        _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVDN_FIELD                        (_MK_MASK_CONST(0x1f) << APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVDN_RANGE                        16:12
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVDN_WOFFSET                      0x0
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVDN_DEFAULT                      _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVDN_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVDN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVDN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVUP_SHIFT                        _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVUP_FIELD                        (_MK_MASK_CONST(0x1f) << APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVUP_RANGE                        24:20
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVUP_WOFFSET                      0x0
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVUP_DEFAULT                      _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVUP_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVUP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVUP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVDN_SLWR_SHIFT                   _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVDN_SLWR_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVDN_SLWR_RANGE                   29:28
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVDN_SLWR_WOFFSET                 0x0
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVDN_SLWR_DEFAULT                 _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVDN_SLWR_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVDN_SLWR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVUP_SLWF_SHIFT                   _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVUP_SLWF_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVUP_SLWF_RANGE                   31:30
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVUP_SLWF_WOFFSET                 0x0
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVUP_SLWF_DEFAULT                 _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVUP_SLWF_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVUP_SLWF_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_MEMCOMPPADCTRL_0  //        0       rw  CFG2TMC_MEM_COMP_EN_COMP    i=0x0   // compensation enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_MEMCOMPPADCTRL_0                    _MK_ADDR_CONST(0x8d4)
+#define APB_MISC_GP_MEMCOMPPADCTRL_0_WORD_COUNT                         0x1
+#define APB_MISC_GP_MEMCOMPPADCTRL_0_RESET_VAL                  _MK_MASK_CONST(0x1f1f000)
+#define APB_MISC_GP_MEMCOMPPADCTRL_0_RESET_MASK                         _MK_MASK_CONST(0x1f1f004)
+#define APB_MISC_GP_MEMCOMPPADCTRL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_MEMCOMPPADCTRL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_MEMCOMPPADCTRL_0_READ_MASK                  _MK_MASK_CONST(0x1f1f004)
+#define APB_MISC_GP_MEMCOMPPADCTRL_0_WRITE_MASK                         _MK_MASK_CONST(0x1f1f004)
+// high speed mode enable
+#define APB_MISC_GP_MEMCOMPPADCTRL_0_MEM_E_HSM_SHIFT                    _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_MEMCOMPPADCTRL_0_MEM_E_HSM_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_GP_MEMCOMPPADCTRL_0_MEM_E_HSM_SHIFT)
+#define APB_MISC_GP_MEMCOMPPADCTRL_0_MEM_E_HSM_RANGE                    2:2
+#define APB_MISC_GP_MEMCOMPPADCTRL_0_MEM_E_HSM_WOFFSET                  0x0
+#define APB_MISC_GP_MEMCOMPPADCTRL_0_MEM_E_HSM_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_MEMCOMPPADCTRL_0_MEM_E_HSM_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_MEMCOMPPADCTRL_0_MEM_E_HSM_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_MEMCOMPPADCTRL_0_MEM_E_HSM_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_MEMCOMPPADCTRL_0_MEM_E_HSM_DISABLE                  _MK_ENUM_CONST(0)
+#define APB_MISC_GP_MEMCOMPPADCTRL_0_MEM_E_HSM_ENABLE                   _MK_ENUM_CONST(1)
+
+#define APB_MISC_GP_MEMCOMPPADCTRL_0_MEM2COMPPAD_DRVDN_SHIFT                    _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_MEMCOMPPADCTRL_0_MEM2COMPPAD_DRVDN_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_MEMCOMPPADCTRL_0_MEM2COMPPAD_DRVDN_SHIFT)
+#define APB_MISC_GP_MEMCOMPPADCTRL_0_MEM2COMPPAD_DRVDN_RANGE                    16:12
+#define APB_MISC_GP_MEMCOMPPADCTRL_0_MEM2COMPPAD_DRVDN_WOFFSET                  0x0
+#define APB_MISC_GP_MEMCOMPPADCTRL_0_MEM2COMPPAD_DRVDN_DEFAULT                  _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_MEMCOMPPADCTRL_0_MEM2COMPPAD_DRVDN_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_MEMCOMPPADCTRL_0_MEM2COMPPAD_DRVDN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_MEMCOMPPADCTRL_0_MEM2COMPPAD_DRVDN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_MEMCOMPPADCTRL_0_MEM2COMPPAD_DRVUP_SHIFT                    _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_MEMCOMPPADCTRL_0_MEM2COMPPAD_DRVUP_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_MEMCOMPPADCTRL_0_MEM2COMPPAD_DRVUP_SHIFT)
+#define APB_MISC_GP_MEMCOMPPADCTRL_0_MEM2COMPPAD_DRVUP_RANGE                    24:20
+#define APB_MISC_GP_MEMCOMPPADCTRL_0_MEM2COMPPAD_DRVUP_WOFFSET                  0x0
+#define APB_MISC_GP_MEMCOMPPADCTRL_0_MEM2COMPPAD_DRVUP_DEFAULT                  _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_MEMCOMPPADCTRL_0_MEM2COMPPAD_DRVUP_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_MEMCOMPPADCTRL_0_MEM2COMPPAD_DRVUP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_MEMCOMPPADCTRL_0_MEM2COMPPAD_DRVUP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_PADCTL_DFT_0  
+#define APB_MISC_GP_PADCTL_DFT_0                        _MK_ADDR_CONST(0x8d8)
+#define APB_MISC_GP_PADCTL_DFT_0_WORD_COUNT                     0x1
+#define APB_MISC_GP_PADCTL_DFT_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_PADCTL_DFT_0_RESET_MASK                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_PADCTL_DFT_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_PADCTL_DFT_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_PADCTL_DFT_0_READ_MASK                      _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_PADCTL_DFT_0_WRITE_MASK                     _MK_MASK_CONST(0x3)
+// Enable pin-shorting for tester mode pin-shorting
+#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_EN_SHIFT                      _MK_SHIFT_CONST(0)
+#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_EN_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_PADCTL_DFT_0_PINSHORT_EN_SHIFT)
+#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_EN_RANGE                      0:0
+#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_EN_WOFFSET                    0x0
+#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_EN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_EN_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_EN_ENABLE                     _MK_ENUM_CONST(1)
+
+// Select which pins are used for test-mode observe
+#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_SEL_SHIFT                     _MK_SHIFT_CONST(1)
+#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_SEL_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_PADCTL_DFT_0_PINSHORT_SEL_SHIFT)
+#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_SEL_RANGE                     1:1
+#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_SEL_WOFFSET                   0x0
+#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_SEL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_SEL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_SEL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_SEL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_UTMIP_PLL_CFG0_0  // USB_PHY PLL Configuration Register 0
+//
+// The data sampling frequency relies on a 960MHz clock, so the goal of the PLL is to have:
+// In_Frequency*(PLL_VCOMULTBY2+1)*(PLL_NDIV/PLL_MDIV) = 960MHz
+//
+// With a 12MHz input from PLL_U, the default setting of 
+// PLL_VCOMULTBY2=1, PLL_NDIV=40 and PLL_MDIV=1 results in a correct output.
+#define APB_MISC_UTMIP_PLL_CFG0_0                       _MK_ADDR_CONST(0xa00)
+#define APB_MISC_UTMIP_PLL_CFG0_0_WORD_COUNT                    0x1
+#define APB_MISC_UTMIP_PLL_CFG0_0_RESET_VAL                     _MK_MASK_CONST(0x280180)
+#define APB_MISC_UTMIP_PLL_CFG0_0_RESET_MASK                    _MK_MASK_CONST(0x7fffffff)
+#define APB_MISC_UTMIP_PLL_CFG0_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG0_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG0_0_READ_MASK                     _MK_MASK_CONST(0x7fffffff)
+#define APB_MISC_UTMIP_PLL_CFG0_0_WRITE_MASK                    _MK_MASK_CONST(0x7fffffff)
+// LOCK_ENABLE input of USB_PHY PLL.
+// Normally only used during test. See cell specification.
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKENABLE_SHIFT                    _MK_SHIFT_CONST(0)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKENABLE_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKENABLE_SHIFT)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKENABLE_RANGE                    0:0
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKENABLE_WOFFSET                  0x0
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKENABLE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKENABLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKENABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKENABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// LOCKSEL[5:0] input of USB_PHY PLL.
+// Used in test modes only. See cell specification.
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKSEL_SHIFT                       _MK_SHIFT_CONST(1)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKSEL_FIELD                       (_MK_MASK_CONST(0x3f) << APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKSEL_SHIFT)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKSEL_RANGE                       6:1
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKSEL_WOFFSET                     0x0
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKSEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKSEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3f)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKSEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKSEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// VCOMULTBY2 control of the UTMIP PHY PLL.
+// Recommended setting is on. Additional divide by 2 on the 
+// VCO feedback. Which is setting the bit to 1. See cell spec.
+//
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_VCOMULTBY2_SHIFT                    _MK_SHIFT_CONST(7)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_VCOMULTBY2_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_VCOMULTBY2_SHIFT)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_VCOMULTBY2_RANGE                    7:7
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_VCOMULTBY2_WOFFSET                  0x0
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_VCOMULTBY2_DEFAULT                  _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_VCOMULTBY2_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_VCOMULTBY2_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_VCOMULTBY2_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// MDIV[7:0] input of the USB_PHY PLL. This is the predivide on the PLL. 
+// 0x0 is not allowed. See cell specification.
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_MDIV_SHIFT                  _MK_SHIFT_CONST(8)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_MDIV_FIELD                  (_MK_MASK_CONST(0xff) << APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_MDIV_SHIFT)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_MDIV_RANGE                  15:8
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_MDIV_WOFFSET                        0x0
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_MDIV_DEFAULT                        _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_MDIV_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_MDIV_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_MDIV_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// NDIV[7:0] input of USB_PHY PLL. 
+// This is the feedback divider on the VCO feedback. 
+// 0x0 is not allowed. See cell specification.
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_NDIV_SHIFT                  _MK_SHIFT_CONST(16)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_NDIV_FIELD                  (_MK_MASK_CONST(0xff) << APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_NDIV_SHIFT)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_NDIV_RANGE                  23:16
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_NDIV_WOFFSET                        0x0
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_NDIV_DEFAULT                        _MK_MASK_CONST(0x28)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_NDIV_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_NDIV_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_NDIV_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// PDIV[2:0] input of the USB_PHY PLL.
+// Reserved. Keep at 0x0. Currently there is no post divider on this PLL. 
+// See cell specification.
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIV_SHIFT                  _MK_SHIFT_CONST(24)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIV_FIELD                  (_MK_MASK_CONST(0x7) << APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIV_SHIFT)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIV_RANGE                  26:24
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIV_WOFFSET                        0x0
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIV_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIV_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIV_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIV_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// PDIVRST of the UTMIP PHY PLL.
+// Reserved. Keep at 0x0. Currently there is no post divider on this PLL. 
+// See cell specification.
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIVRST_SHIFT                       _MK_SHIFT_CONST(27)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIVRST_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIVRST_SHIFT)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIVRST_RANGE                       27:27
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIVRST_WOFFSET                     0x0
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIVRST_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIVRST_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIVRST_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIVRST_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Selects which of the eight 60MHz clock phases to produce at the output 
+// of the USB PHY PLL. This is for a test mode. See cell specification.
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_SELECT_SHIFT                        _MK_SHIFT_CONST(28)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_SELECT_FIELD                        (_MK_MASK_CONST(0x7) << APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_SELECT_SHIFT)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_SELECT_RANGE                        30:28
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_SELECT_WOFFSET                      0x0
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_SELECT_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_SELECT_DEFAULT_MASK                 _MK_MASK_CONST(0x7)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_SELECT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_SELECT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_UTMIP_PLL_CFG1_0  // UTMIP PLL and PLLU configuration register 1
+#define APB_MISC_UTMIP_PLL_CFG1_0                       _MK_ADDR_CONST(0xa04)
+#define APB_MISC_UTMIP_PLL_CFG1_0_WORD_COUNT                    0x1
+#define APB_MISC_UTMIP_PLL_CFG1_0_RESET_VAL                     _MK_MASK_CONST(0x182000c0)
+#define APB_MISC_UTMIP_PLL_CFG1_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_UTMIP_PLL_CFG1_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG1_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG1_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_UTMIP_PLL_CFG1_0_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
+// Determines the time to wait until the output of USB_PHY PLL is considered stable. 
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_XTAL_FREQ_COUNT_SHIFT                   _MK_SHIFT_CONST(0)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_XTAL_FREQ_COUNT_FIELD                   (_MK_MASK_CONST(0xfff) << APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_XTAL_FREQ_COUNT_SHIFT)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_XTAL_FREQ_COUNT_RANGE                   11:0
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_XTAL_FREQ_COUNT_WOFFSET                 0x0
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_XTAL_FREQ_COUNT_DEFAULT                 _MK_MASK_CONST(0xc0)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_XTAL_FREQ_COUNT_DEFAULT_MASK                    _MK_MASK_CONST(0xfff)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_XTAL_FREQ_COUNT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_XTAL_FREQ_COUNT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Force USB_PHY PLL pll_active input off. (Overrides FORCE_PLL_ACTIVE_POWERUP.)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERDOWN_SHIFT                        _MK_SHIFT_CONST(12)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERDOWN_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERDOWN_SHIFT)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERDOWN_RANGE                        12:12
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERDOWN_WOFFSET                      0x0
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERDOWN_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERDOWN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERDOWN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERDOWN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Force USB_PHY PLL pll_active input on. 
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERUP_SHIFT                  _MK_SHIFT_CONST(13)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERUP_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERUP_SHIFT)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERUP_RANGE                  13:13
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERUP_WOFFSET                        0x0
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERUP_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERUP_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERUP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERUP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Force USB_PHY PLL pll_enable input off. (Overrides FORCE_PLL_ENABLE_POWERUP.)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERDOWN_SHIFT                        _MK_SHIFT_CONST(14)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERDOWN_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERDOWN_SHIFT)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERDOWN_RANGE                        14:14
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERDOWN_WOFFSET                      0x0
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERDOWN_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERDOWN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERDOWN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERDOWN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Force USB_PHY PLL pll_enable input on. 
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERUP_SHIFT                  _MK_SHIFT_CONST(15)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERUP_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERUP_SHIFT)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERUP_RANGE                  15:15
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERUP_WOFFSET                        0x0
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERUP_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERUP_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERUP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERUP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Force PLL_U into power down. (Overrides FORCE_PLLU_POWERUP.)  
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERDOWN_SHIFT                      _MK_SHIFT_CONST(16)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERDOWN_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERDOWN_SHIFT)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERDOWN_RANGE                      16:16
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERDOWN_WOFFSET                    0x0
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERDOWN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERDOWN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERDOWN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERDOWN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Force PLL_U into power up.
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERUP_SHIFT                        _MK_SHIFT_CONST(17)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERUP_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERUP_SHIFT)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERUP_RANGE                        17:17
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERUP_WOFFSET                      0x0
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERUP_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERUP_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERUP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERUP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// SETUP[8:0] input of USB_PHY PLL.
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_PLL_SETUP_SHIFT                 _MK_SHIFT_CONST(18)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_PLL_SETUP_FIELD                 (_MK_MASK_CONST(0x1ff) << APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_PLL_SETUP_SHIFT)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_PLL_SETUP_RANGE                 26:18
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_PLL_SETUP_WOFFSET                       0x0
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_PLL_SETUP_DEFAULT                       _MK_MASK_CONST(0x8)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_PLL_SETUP_DEFAULT_MASK                  _MK_MASK_CONST(0x1ff)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_PLL_SETUP_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_PLL_SETUP_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Controls the wait time to enable PLL_U when coming out of suspend or reset.
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT                     _MK_SHIFT_CONST(27)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_PLLU_ENABLE_DLY_COUNT_FIELD                     (_MK_MASK_CONST(0x1f) << APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_PLLU_ENABLE_DLY_COUNT_RANGE                     31:27
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_PLLU_ENABLE_DLY_COUNT_WOFFSET                   0x0
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_PLLU_ENABLE_DLY_COUNT_DEFAULT                   _MK_MASK_CONST(0x3)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_PLLU_ENABLE_DLY_COUNT_DEFAULT_MASK                      _MK_MASK_CONST(0x1f)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_PLLU_ENABLE_DLY_COUNT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_PLLU_ENABLE_DLY_COUNT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_UTMIP_XCVR_CFG0_0  // UTMIP transceiver cell configuration register 0
+#define APB_MISC_UTMIP_XCVR_CFG0_0                      _MK_ADDR_CONST(0xa08)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_WORD_COUNT                   0x1
+#define APB_MISC_UTMIP_XCVR_CFG0_0_RESET_VAL                    _MK_MASK_CONST(0x250a)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_RESET_MASK                   _MK_MASK_CONST(0xfffff)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_READ_MASK                    _MK_MASK_CONST(0xfffff)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_WRITE_MASK                   _MK_MASK_CONST(0xfffff)
+// SETUP[3:0] input of XCVR cell. HS driver output control.
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_SETUP_SHIFT                       _MK_SHIFT_CONST(0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_SETUP_FIELD                       (_MK_MASK_CONST(0xf) << APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_SETUP_SHIFT)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_SETUP_RANGE                       3:0
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_SETUP_WOFFSET                     0x0
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_SETUP_DEFAULT                     _MK_MASK_CONST(0xa)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_SETUP_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_SETUP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_SETUP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// HS slew rate control.
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSSLEW_SHIFT                      _MK_SHIFT_CONST(4)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSSLEW_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSSLEW_SHIFT)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSSLEW_RANGE                      5:4
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSSLEW_WOFFSET                    0x0
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSSLEW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSSLEW_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSSLEW_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSSLEW_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// FS slew rate control.
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_FSSLEW_SHIFT                      _MK_SHIFT_CONST(6)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_FSSLEW_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_FSSLEW_SHIFT)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_FSSLEW_RANGE                      7:6
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_FSSLEW_WOFFSET                    0x0
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_FSSLEW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_FSSLEW_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_FSSLEW_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_FSSLEW_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// LS rising slew rate control.
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSRSLEW_SHIFT                     _MK_SHIFT_CONST(8)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSRSLEW_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSRSLEW_SHIFT)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSRSLEW_RANGE                     9:8
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSRSLEW_WOFFSET                   0x0
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSRSLEW_DEFAULT                   _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSRSLEW_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSRSLEW_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSRSLEW_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// LS falling slew rate control.
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSFSLEW_SHIFT                     _MK_SHIFT_CONST(10)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSFSLEW_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSFSLEW_SHIFT)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSFSLEW_RANGE                     11:10
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSFSLEW_WOFFSET                   0x0
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSFSLEW_DEFAULT                   _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSFSLEW_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSFSLEW_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSFSLEW_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Internal loopback inside XCVR cell. Used for IOBIST.
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSLOOPBACK_SHIFT                  _MK_SHIFT_CONST(12)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSLOOPBACK_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSLOOPBACK_SHIFT)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSLOOPBACK_RANGE                  12:12
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSLOOPBACK_WOFFSET                        0x0
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSLOOPBACK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSLOOPBACK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSLOOPBACK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSLOOPBACK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Enable HS termination.
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_TERMEN_SHIFT                      _MK_SHIFT_CONST(13)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_TERMEN_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_TERMEN_SHIFT)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_TERMEN_RANGE                      13:13
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_TERMEN_WOFFSET                    0x0
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_TERMEN_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_TERMEN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_TERMEN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_TERMEN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Force PD input into power down. (Overrides FORCE_PD_POWERUP.)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERDOWN_SHIFT                       _MK_SHIFT_CONST(14)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERDOWN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERDOWN_SHIFT)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERDOWN_RANGE                       14:14
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERDOWN_WOFFSET                     0x0
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERDOWN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERDOWN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERDOWN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERDOWN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Force PD input into power up. 
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERUP_SHIFT                 _MK_SHIFT_CONST(15)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERUP_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERUP_SHIFT)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERUP_RANGE                 15:15
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERUP_WOFFSET                       0x0
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERUP_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERUP_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERUP_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERUP_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Force PD2 input into power down. (Overrides FORCE_PD2_POWERUP.)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERDOWN_SHIFT                      _MK_SHIFT_CONST(16)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERDOWN_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERDOWN_SHIFT)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERDOWN_RANGE                      16:16
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERDOWN_WOFFSET                    0x0
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERDOWN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERDOWN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERDOWN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERDOWN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Force PD2 input into power up.
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERUP_SHIFT                        _MK_SHIFT_CONST(17)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERUP_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERUP_SHIFT)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERUP_RANGE                        17:17
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERUP_WOFFSET                      0x0
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERUP_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERUP_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERUP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERUP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Force PDZI input into power down. (Overrides FORCE_PDZI_POWERUP.)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERDOWN_SHIFT                     _MK_SHIFT_CONST(18)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERDOWN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERDOWN_SHIFT)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERDOWN_RANGE                     18:18
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERDOWN_WOFFSET                   0x0
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERDOWN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERDOWN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERDOWN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERDOWN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Force PDZI input into power up.
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERUP_SHIFT                       _MK_SHIFT_CONST(19)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERUP_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERUP_SHIFT)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERUP_RANGE                       19:19
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERUP_WOFFSET                     0x0
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERUP_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERUP_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERUP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERUP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_UTMIP_BIAS_CFG0_0  // UTMIP Bias cell configuration register 0
+#define APB_MISC_UTMIP_BIAS_CFG0_0                      _MK_ADDR_CONST(0xa0c)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_WORD_COUNT                   0x1
+#define APB_MISC_UTMIP_BIAS_CFG0_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_RESET_MASK                   _MK_MASK_CONST(0xffffff)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_READ_MASK                    _MK_MASK_CONST(0xffffff)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_WRITE_MASK                   _MK_MASK_CONST(0xffffff)
+// HS squelch detector level.
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSSQUELCH_LEVEL_SHIFT                  _MK_SHIFT_CONST(0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSSQUELCH_LEVEL_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSSQUELCH_LEVEL_SHIFT)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSSQUELCH_LEVEL_RANGE                  1:0
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSSQUELCH_LEVEL_WOFFSET                        0x0
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSSQUELCH_LEVEL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSSQUELCH_LEVEL_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSSQUELCH_LEVEL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSSQUELCH_LEVEL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// HS disconnect detector level.
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSDISCON_LEVEL_SHIFT                   _MK_SHIFT_CONST(2)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSDISCON_LEVEL_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSDISCON_LEVEL_SHIFT)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSDISCON_LEVEL_RANGE                   3:2
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSDISCON_LEVEL_WOFFSET                 0x0
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSDISCON_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSDISCON_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSDISCON_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSDISCON_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// HS chirp detector level.
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSCHIRP_LEVEL_SHIFT                    _MK_SHIFT_CONST(4)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSCHIRP_LEVEL_FIELD                    (_MK_MASK_CONST(0x3) << APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSCHIRP_LEVEL_SHIFT)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSCHIRP_LEVEL_RANGE                    5:4
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSCHIRP_LEVEL_WOFFSET                  0x0
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSCHIRP_LEVEL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSCHIRP_LEVEL_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSCHIRP_LEVEL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSCHIRP_LEVEL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// SessionEnd detector level.
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_SESS_LEVEL_LEVEL_SHIFT                 _MK_SHIFT_CONST(6)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_SESS_LEVEL_LEVEL_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_SESS_LEVEL_LEVEL_SHIFT)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_SESS_LEVEL_LEVEL_RANGE                 7:6
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_SESS_LEVEL_LEVEL_WOFFSET                       0x0
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_SESS_LEVEL_LEVEL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_SESS_LEVEL_LEVEL_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_SESS_LEVEL_LEVEL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_SESS_LEVEL_LEVEL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Vbus detector level.
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_VBUS_LEVEL_LEVEL_SHIFT                 _MK_SHIFT_CONST(8)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_VBUS_LEVEL_LEVEL_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_VBUS_LEVEL_LEVEL_SHIFT)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_VBUS_LEVEL_LEVEL_RANGE                 9:8
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_VBUS_LEVEL_LEVEL_WOFFSET                       0x0
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_VBUS_LEVEL_LEVEL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_VBUS_LEVEL_LEVEL_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_VBUS_LEVEL_LEVEL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_VBUS_LEVEL_LEVEL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Power down bias circuit.
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_BIASPD_SHIFT                   _MK_SHIFT_CONST(10)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_BIASPD_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_BIASPD_SHIFT)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_BIASPD_RANGE                   10:10
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_BIASPD_WOFFSET                 0x0
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_BIASPD_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_BIASPD_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_BIASPD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_BIASPD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Power down OTG circuit.
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_OTGPD_SHIFT                    _MK_SHIFT_CONST(11)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_OTGPD_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_OTGPD_SHIFT)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_OTGPD_RANGE                    11:11
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_OTGPD_WOFFSET                  0x0
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_OTGPD_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_OTGPD_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_OTGPD_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_OTGPD_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Active 1.5K pullup control offset.
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_PULLUP_OFFSET_SHIFT                     _MK_SHIFT_CONST(12)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_PULLUP_OFFSET_FIELD                     (_MK_MASK_CONST(0x7) << APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_PULLUP_OFFSET_SHIFT)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_PULLUP_OFFSET_RANGE                     14:12
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_PULLUP_OFFSET_WOFFSET                   0x0
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_PULLUP_OFFSET_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_PULLUP_OFFSET_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_PULLUP_OFFSET_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_PULLUP_OFFSET_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Active termination control offset.
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_TERM_OFFSET_SHIFT                       _MK_SHIFT_CONST(15)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_TERM_OFFSET_FIELD                       (_MK_MASK_CONST(0x7) << APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_TERM_OFFSET_SHIFT)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_TERM_OFFSET_RANGE                       17:15
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_TERM_OFFSET_WOFFSET                     0x0
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_TERM_OFFSET_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_TERM_OFFSET_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_TERM_OFFSET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_TERM_OFFSET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// 0: StaticGpi = IdDig. 1: StaticGpi = GPI_VAL.
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_GPI_SEL_SHIFT                  _MK_SHIFT_CONST(18)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_GPI_SEL_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_GPI_SEL_SHIFT)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_GPI_SEL_RANGE                  18:18
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_GPI_SEL_WOFFSET                        0x0
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_GPI_SEL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_GPI_SEL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_GPI_SEL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_GPI_SEL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// See GPI_SEL.
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_GPI_VAL_SHIFT                  _MK_SHIFT_CONST(19)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_GPI_VAL_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_GPI_VAL_SHIFT)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_GPI_VAL_RANGE                  19:19
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_GPI_VAL_WOFFSET                        0x0
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_GPI_VAL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_GPI_VAL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_GPI_VAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_GPI_VAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// 0: IdDig = IdDig. 1: IdDig = IDDIG_VAL.
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_SEL_SHIFT                        _MK_SHIFT_CONST(20)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_SEL_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_SEL_SHIFT)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_SEL_RANGE                        20:20
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_SEL_WOFFSET                      0x0
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_SEL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_SEL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_SEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_SEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// See IDDIG_SEL.
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_VAL_SHIFT                        _MK_SHIFT_CONST(21)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_VAL_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_VAL_SHIFT)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_VAL_RANGE                        21:21
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_VAL_WOFFSET                      0x0
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_VAL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_VAL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_VAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_VAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// 0: IDPD = ~IdPullup. 1: IDPD = IDPD_VAL.
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_SEL_SHIFT                 _MK_SHIFT_CONST(22)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_SEL_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_SEL_SHIFT)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_SEL_RANGE                 22:22
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_SEL_WOFFSET                       0x0
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_SEL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_SEL_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_SEL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_SEL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// See IDPD_SEL.
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_VAL_SHIFT                 _MK_SHIFT_CONST(23)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_VAL_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_VAL_SHIFT)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_VAL_RANGE                 23:23
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_VAL_WOFFSET                       0x0
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_VAL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_VAL_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_VAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_VAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_UTMIP_HSRX_CFG0_0  // UTMIP High speed receive config 0 
+#define APB_MISC_UTMIP_HSRX_CFG0_0                      _MK_ADDR_CONST(0xa10)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_WORD_COUNT                   0x1
+#define APB_MISC_UTMIP_HSRX_CFG0_0_RESET_VAL                    _MK_MASK_CONST(0x91653400)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
+// Require 4 sync pattern transitions (01) instead of 3
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_USE4SYNC_TRAN_SHIFT                    _MK_SHIFT_CONST(0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_USE4SYNC_TRAN_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_USE4SYNC_TRAN_SHIFT)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_USE4SYNC_TRAN_RANGE                    0:0
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_USE4SYNC_TRAN_WOFFSET                  0x0
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_USE4SYNC_TRAN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_USE4SYNC_TRAN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_USE4SYNC_TRAN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_USE4SYNC_TRAN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Sync pattern detection needs 3 consecutive samples instead of 4
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_THREE_SYNCBITS_SHIFT                   _MK_SHIFT_CONST(1)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_THREE_SYNCBITS_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_THREE_SYNCBITS_SHIFT)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_THREE_SYNCBITS_RANGE                   1:1
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_THREE_SYNCBITS_WOFFSET                 0x0
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_THREE_SYNCBITS_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_THREE_SYNCBITS_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_THREE_SYNCBITS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_THREE_SYNCBITS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Based on incoming edges and current sampling position, adjust phase
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PHASE_ADJUST_SHIFT                     _MK_SHIFT_CONST(2)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PHASE_ADJUST_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PHASE_ADJUST_SHIFT)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PHASE_ADJUST_RANGE                     3:2
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PHASE_ADJUST_WOFFSET                   0x0
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PHASE_ADJUST_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PHASE_ADJUST_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PHASE_ADJUST_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PHASE_ADJUST_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Retime the path. 
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_INERTIA_SHIFT                   _MK_SHIFT_CONST(4)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_INERTIA_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_INERTIA_SHIFT)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_INERTIA_RANGE                   5:4
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_INERTIA_WOFFSET                 0x0
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_INERTIA_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_INERTIA_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_INERTIA_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_INERTIA_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Pass through the feedback, do not block it.
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PASS_FEEDBACK_SHIFT                    _MK_SHIFT_CONST(6)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PASS_FEEDBACK_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PASS_FEEDBACK_SHIFT)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PASS_FEEDBACK_RANGE                    6:6
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PASS_FEEDBACK_WOFFSET                  0x0
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PASS_FEEDBACK_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PASS_FEEDBACK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PASS_FEEDBACK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PASS_FEEDBACK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// When in Chirp Mode, allow chirp rx data through
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PASS_CHIRP_SHIFT                       _MK_SHIFT_CONST(7)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PASS_CHIRP_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PASS_CHIRP_SHIFT)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PASS_CHIRP_RANGE                       7:7
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PASS_CHIRP_WOFFSET                     0x0
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PASS_CHIRP_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PASS_CHIRP_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PASS_CHIRP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PASS_CHIRP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Do not declare underrun errors
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_UNDERRUN_DISABLE_SHIFT                 _MK_SHIFT_CONST(8)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_UNDERRUN_DISABLE_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_UNDERRUN_DISABLE_SHIFT)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_UNDERRUN_DISABLE_RANGE                 8:8
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_UNDERRUN_DISABLE_WOFFSET                       0x0
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_UNDERRUN_DISABLE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_UNDERRUN_DISABLE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_UNDERRUN_DISABLE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_UNDERRUN_DISABLE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Do not declare overrun errors until overflow of FIFO
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_OVERRUN_DISABLE_SHIFT                  _MK_SHIFT_CONST(9)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_OVERRUN_DISABLE_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_OVERRUN_DISABLE_SHIFT)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_OVERRUN_DISABLE_RANGE                  9:9
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_OVERRUN_DISABLE_WOFFSET                        0x0
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_OVERRUN_DISABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_OVERRUN_DISABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_OVERRUN_DISABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_OVERRUN_DISABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Depth of elastic input store
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_LIMIT_SHIFT                    _MK_SHIFT_CONST(10)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_LIMIT_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_LIMIT_SHIFT)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_LIMIT_RANGE                    14:10
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_LIMIT_WOFFSET                  0x0
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_LIMIT_DEFAULT                  _MK_MASK_CONST(0xd)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_LIMIT_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_LIMIT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_LIMIT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Number of cycles of idle to declare IDLE. 
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_IDLE_WAIT_SHIFT                        _MK_SHIFT_CONST(15)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_IDLE_WAIT_FIELD                        (_MK_MASK_CONST(0x1f) << APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_IDLE_WAIT_SHIFT)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_IDLE_WAIT_RANGE                        19:15
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_IDLE_WAIT_WOFFSET                      0x0
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_IDLE_WAIT_DEFAULT                      _MK_MASK_CONST(0xa)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_IDLE_WAIT_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_IDLE_WAIT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_IDLE_WAIT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Do not strip incoming data
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_NO_STRIPPING_SHIFT                     _MK_SHIFT_CONST(20)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_NO_STRIPPING_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_NO_STRIPPING_SHIFT)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_NO_STRIPPING_RANGE                     20:20
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_NO_STRIPPING_WOFFSET                   0x0
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_NO_STRIPPING_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_NO_STRIPPING_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_NO_STRIPPING_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_NO_STRIPPING_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Limit the delay of the squelch at EOP time
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_SQUELCH_EOP_DLY_SHIFT                  _MK_SHIFT_CONST(21)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_SQUELCH_EOP_DLY_FIELD                  (_MK_MASK_CONST(0x7) << APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_SQUELCH_EOP_DLY_SHIFT)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_SQUELCH_EOP_DLY_RANGE                  23:21
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_SQUELCH_EOP_DLY_WOFFSET                        0x0
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_SQUELCH_EOP_DLY_DEFAULT                        _MK_MASK_CONST(0x3)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_SQUELCH_EOP_DLY_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_SQUELCH_EOP_DLY_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_SQUELCH_EOP_DLY_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// The number of (edges-1) needed to move the sampling point
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_UPDN_DIV_SHIFT                  _MK_SHIFT_CONST(24)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_UPDN_DIV_FIELD                  (_MK_MASK_CONST(0xf) << APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_UPDN_DIV_SHIFT)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_UPDN_DIV_RANGE                  27:24
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_UPDN_DIV_WOFFSET                        0x0
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_UPDN_DIV_DEFAULT                        _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_UPDN_DIV_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_UPDN_DIV_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_UPDN_DIV_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Realign the inertia counters on a new packet
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_REALIGN_ON_NEW_PKT_SHIFT                       _MK_SHIFT_CONST(28)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_REALIGN_ON_NEW_PKT_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_REALIGN_ON_NEW_PKT_SHIFT)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_REALIGN_ON_NEW_PKT_RANGE                       28:28
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_REALIGN_ON_NEW_PKT_WOFFSET                     0x0
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_REALIGN_ON_NEW_PKT_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_REALIGN_ON_NEW_PKT_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_REALIGN_ON_NEW_PKT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_REALIGN_ON_NEW_PKT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Allow consecutive ups and downs on the bits, debug only, set to 0.
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ALLOW_CONSEC_UPDN_SHIFT                        _MK_SHIFT_CONST(29)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ALLOW_CONSEC_UPDN_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ALLOW_CONSEC_UPDN_SHIFT)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ALLOW_CONSEC_UPDN_RANGE                        29:29
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ALLOW_CONSEC_UPDN_WOFFSET                      0x0
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ALLOW_CONSEC_UPDN_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ALLOW_CONSEC_UPDN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ALLOW_CONSEC_UPDN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ALLOW_CONSEC_UPDN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Keep the stay alive pattern on active
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_KEEP_PATT_ON_ACTIVE_SHIFT                      _MK_SHIFT_CONST(30)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_KEEP_PATT_ON_ACTIVE_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_KEEP_PATT_ON_ACTIVE_SHIFT)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_KEEP_PATT_ON_ACTIVE_RANGE                      31:30
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_KEEP_PATT_ON_ACTIVE_WOFFSET                    0x0
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_KEEP_PATT_ON_ACTIVE_DEFAULT                    _MK_MASK_CONST(0x2)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_KEEP_PATT_ON_ACTIVE_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_KEEP_PATT_ON_ACTIVE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_KEEP_PATT_ON_ACTIVE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_UTMIP_HSRX_CFG1_0  // UTMIP High speed receive config 1
+#define APB_MISC_UTMIP_HSRX_CFG1_0                      _MK_ADDR_CONST(0xa14)
+#define APB_MISC_UTMIP_HSRX_CFG1_0_WORD_COUNT                   0x1
+#define APB_MISC_UTMIP_HSRX_CFG1_0_RESET_VAL                    _MK_MASK_CONST(0x13)
+#define APB_MISC_UTMIP_HSRX_CFG1_0_RESET_MASK                   _MK_MASK_CONST(0x3f)
+#define APB_MISC_UTMIP_HSRX_CFG1_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG1_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG1_0_READ_MASK                    _MK_MASK_CONST(0x3f)
+#define APB_MISC_UTMIP_HSRX_CFG1_0_WRITE_MASK                   _MK_MASK_CONST(0x3f)
+// Allow Keep Alive packets 
+#define APB_MISC_UTMIP_HSRX_CFG1_0_UTMIP_HS_ALLOW_KEEP_ALIVE_SHIFT                      _MK_SHIFT_CONST(0)
+#define APB_MISC_UTMIP_HSRX_CFG1_0_UTMIP_HS_ALLOW_KEEP_ALIVE_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_HSRX_CFG1_0_UTMIP_HS_ALLOW_KEEP_ALIVE_SHIFT)
+#define APB_MISC_UTMIP_HSRX_CFG1_0_UTMIP_HS_ALLOW_KEEP_ALIVE_RANGE                      0:0
+#define APB_MISC_UTMIP_HSRX_CFG1_0_UTMIP_HS_ALLOW_KEEP_ALIVE_WOFFSET                    0x0
+#define APB_MISC_UTMIP_HSRX_CFG1_0_UTMIP_HS_ALLOW_KEEP_ALIVE_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_HSRX_CFG1_0_UTMIP_HS_ALLOW_KEEP_ALIVE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_HSRX_CFG1_0_UTMIP_HS_ALLOW_KEEP_ALIVE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG1_0_UTMIP_HS_ALLOW_KEEP_ALIVE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// How long to wait before start of sync launches RxActive
+#define APB_MISC_UTMIP_HSRX_CFG1_0_UTMIP_HS_SYNC_START_DLY_SHIFT                        _MK_SHIFT_CONST(1)
+#define APB_MISC_UTMIP_HSRX_CFG1_0_UTMIP_HS_SYNC_START_DLY_FIELD                        (_MK_MASK_CONST(0x1f) << APB_MISC_UTMIP_HSRX_CFG1_0_UTMIP_HS_SYNC_START_DLY_SHIFT)
+#define APB_MISC_UTMIP_HSRX_CFG1_0_UTMIP_HS_SYNC_START_DLY_RANGE                        5:1
+#define APB_MISC_UTMIP_HSRX_CFG1_0_UTMIP_HS_SYNC_START_DLY_WOFFSET                      0x0
+#define APB_MISC_UTMIP_HSRX_CFG1_0_UTMIP_HS_SYNC_START_DLY_DEFAULT                      _MK_MASK_CONST(0x9)
+#define APB_MISC_UTMIP_HSRX_CFG1_0_UTMIP_HS_SYNC_START_DLY_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define APB_MISC_UTMIP_HSRX_CFG1_0_UTMIP_HS_SYNC_START_DLY_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG1_0_UTMIP_HS_SYNC_START_DLY_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_UTMIP_FSLSRX_CFG0_0  // UTMIP full and Low speed receive config 0
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0                    _MK_ADDR_CONST(0xa18)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_WORD_COUNT                         0x1
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_RESET_VAL                  _MK_MASK_CONST(0xfd548429)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+// Give up on packet if a long sequence of J 
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_LIMIT_SHIFT                  _MK_SHIFT_CONST(0)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_LIMIT_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_LIMIT_SHIFT)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_LIMIT_RANGE                  0:0
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_LIMIT_WOFFSET                        0x0
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_LIMIT_DEFAULT                        _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_LIMIT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_LIMIT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_LIMIT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// 20 bits of idle should end the packet if FsLsIdleCountLimitCfg=1.
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_MAX_SHIFT                    _MK_SHIFT_CONST(1)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_MAX_FIELD                    (_MK_MASK_CONST(0x3f) << APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_MAX_SHIFT)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_MAX_RANGE                    6:1
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_MAX_WOFFSET                  0x0
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_MAX_DEFAULT                  _MK_MASK_CONST(0x14)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_MAX_DEFAULT_MASK                     _MK_MASK_CONST(0x3f)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_MAX_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_MAX_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Enable the reset of the state machine on extended SE0
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_LIMIT_SHIFT                   _MK_SHIFT_CONST(7)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_LIMIT_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_LIMIT_SHIFT)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_LIMIT_RANGE                   7:7
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_LIMIT_WOFFSET                 0x0
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_LIMIT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_LIMIT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_LIMIT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_LIMIT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// 4 bits of of SEO should exceed the time limit
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_MAX_SHIFT                     _MK_SHIFT_CONST(8)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_MAX_FIELD                     (_MK_MASK_CONST(0x3f) << APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_MAX_SHIFT)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_MAX_RANGE                     13:8
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_MAX_WOFFSET                   0x0
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_MAX_DEFAULT                   _MK_MASK_CONST(0x4)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_MAX_DEFAULT_MASK                      _MK_MASK_CONST(0x3f)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_MAX_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_MAX_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Require a full sync pattern to declare the data received
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_ACTIVE_ON_FULL_SYNC_SHIFT                       _MK_SHIFT_CONST(14)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_ACTIVE_ON_FULL_SYNC_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_ACTIVE_ON_FULL_SYNC_SHIFT)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_ACTIVE_ON_FULL_SYNC_RANGE                       14:14
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_ACTIVE_ON_FULL_SYNC_WOFFSET                     0x0
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_ACTIVE_ON_FULL_SYNC_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_ACTIVE_ON_FULL_SYNC_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_ACTIVE_ON_FULL_SYNC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_ACTIVE_ON_FULL_SYNC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Limit the number of bit times a K can last
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_LIMIT_SHIFT                      _MK_SHIFT_CONST(15)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_LIMIT_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_LIMIT_SHIFT)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_LIMIT_RANGE                      15:15
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_LIMIT_WOFFSET                    0x0
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_LIMIT_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_LIMIT_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_LIMIT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_LIMIT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Number of K bits in question
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_MAX_SHIFT                        _MK_SHIFT_CONST(16)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_MAX_FIELD                        (_MK_MASK_CONST(0x3f) << APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_MAX_SHIFT)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_MAX_RANGE                        21:16
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_MAX_WOFFSET                      0x0
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_MAX_DEFAULT                      _MK_MASK_CONST(0x14)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_MAX_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_MAX_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_MAX_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Only look for transitioning out of EOP
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_EOP_ENDS_AT_SE0_SHIFT                   _MK_SHIFT_CONST(22)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_EOP_ENDS_AT_SE0_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_EOP_ENDS_AT_SE0_SHIFT)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_EOP_ENDS_AT_SE0_RANGE                   22:22
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_EOP_ENDS_AT_SE0_WOFFSET                 0x0
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_EOP_ENDS_AT_SE0_DEFAULT                 _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_EOP_ENDS_AT_SE0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_EOP_ENDS_AT_SE0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_EOP_ENDS_AT_SE0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Do not allow >= dribble bits 
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_LWR_DRIBBLE_SIZE_SHIFT                  _MK_SHIFT_CONST(23)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_LWR_DRIBBLE_SIZE_FIELD                  (_MK_MASK_CONST(0x7) << APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_LWR_DRIBBLE_SIZE_SHIFT)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_LWR_DRIBBLE_SIZE_RANGE                  25:23
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_LWR_DRIBBLE_SIZE_WOFFSET                        0x0
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_LWR_DRIBBLE_SIZE_DEFAULT                        _MK_MASK_CONST(0x2)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_LWR_DRIBBLE_SIZE_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_LWR_DRIBBLE_SIZE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_LWR_DRIBBLE_SIZE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Do not allow <= dribble bits
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_UPR_DRIBBLE_SIZE_SHIFT                  _MK_SHIFT_CONST(26)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_UPR_DRIBBLE_SIZE_FIELD                  (_MK_MASK_CONST(0x7) << APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_UPR_DRIBBLE_SIZE_SHIFT)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_UPR_DRIBBLE_SIZE_RANGE                  28:26
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_UPR_DRIBBLE_SIZE_WOFFSET                        0x0
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_UPR_DRIBBLE_SIZE_DEFAULT                        _MK_MASK_CONST(0x7)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_UPR_DRIBBLE_SIZE_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_UPR_DRIBBLE_SIZE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_UPR_DRIBBLE_SIZE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SERIAL_SE0_RCV_SHIFT                    _MK_SHIFT_CONST(29)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SERIAL_SE0_RCV_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SERIAL_SE0_RCV_SHIFT)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SERIAL_SE0_RCV_RANGE                    29:29
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SERIAL_SE0_RCV_WOFFSET                  0x0
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SERIAL_SE0_RCV_DEFAULT                  _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SERIAL_SE0_RCV_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SERIAL_SE0_RCV_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SERIAL_SE0_RCV_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Filter SE1
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_FILTER_SHIFT                        _MK_SHIFT_CONST(30)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_FILTER_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_FILTER_SHIFT)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_FILTER_RANGE                        30:30
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_FILTER_WOFFSET                      0x0
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_FILTER_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_FILTER_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_FILTER_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_FILTER_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// One SE1, don't allow dribble
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_DRIBBLE_FILTER_SHIFT                        _MK_SHIFT_CONST(31)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_DRIBBLE_FILTER_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_DRIBBLE_FILTER_SHIFT)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_DRIBBLE_FILTER_RANGE                        31:31
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_DRIBBLE_FILTER_WOFFSET                      0x0
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_DRIBBLE_FILTER_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_DRIBBLE_FILTER_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_DRIBBLE_FILTER_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_DRIBBLE_FILTER_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_UTMIP_FSLSRX_CFG1_0  // UTMIP full and Low speed receive config 1
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0                    _MK_ADDR_CONST(0xa1c)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_WORD_COUNT                         0x1
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_RESET_VAL                  _MK_MASK_CONST(0x2267400)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_RESET_MASK                         _MK_MASK_CONST(0x7ffffff)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_READ_MASK                  _MK_MASK_CONST(0x7ffffff)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_WRITE_MASK                         _MK_MASK_CONST(0x7ffffff)
+// Whether full speed EOP  is determined within 3(0) or 4(1) 60MHz cycles
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_EOP_LENGTH_SHIFT                  _MK_SHIFT_CONST(0)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_EOP_LENGTH_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_EOP_LENGTH_SHIFT)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_EOP_LENGTH_RANGE                  0:0
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_EOP_LENGTH_WOFFSET                        0x0
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_EOP_LENGTH_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_EOP_LENGTH_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_EOP_LENGTH_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_EOP_LENGTH_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Whether full speed uses debouncing
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_DEBOUNCE_SHIFT                    _MK_SHIFT_CONST(1)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_DEBOUNCE_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_DEBOUNCE_SHIFT)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_DEBOUNCE_RANGE                    1:1
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_DEBOUNCE_WOFFSET                  0x0
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_DEBOUNCE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_DEBOUNCE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_DEBOUNCE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_DEBOUNCE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Only look for a KK pattern, instead of KJKK
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_WEAK_SYNC_SHIFT                   _MK_SHIFT_CONST(2)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_WEAK_SYNC_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_WEAK_SYNC_SHIFT)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_WEAK_SYNC_RANGE                   2:2
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_WEAK_SYNC_WOFFSET                 0x0
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_WEAK_SYNC_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_WEAK_SYNC_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_WEAK_SYNC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_WEAK_SYNC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Allow for large dribble in full speed mode
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_LENIENT_DRIBBLE_SHIFT                     _MK_SHIFT_CONST(3)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_LENIENT_DRIBBLE_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_LENIENT_DRIBBLE_SHIFT)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_LENIENT_DRIBBLE_RANGE                     3:3
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_LENIENT_DRIBBLE_WOFFSET                   0x0
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_LENIENT_DRIBBLE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_LENIENT_DRIBBLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_LENIENT_DRIBBLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_LENIENT_DRIBBLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Allow for large dribble in low  speed mode
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_LENIENT_DRIBBLE_SHIFT                     _MK_SHIFT_CONST(4)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_LENIENT_DRIBBLE_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_LENIENT_DRIBBLE_SHIFT)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_LENIENT_DRIBBLE_RANGE                     4:4
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_LENIENT_DRIBBLE_WOFFSET                   0x0
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_LENIENT_DRIBBLE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_LENIENT_DRIBBLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_LENIENT_DRIBBLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_LENIENT_DRIBBLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Only for this number of 60MHz of SEO and Idle to end packet
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_SE0_COUNT_SHIFT                   _MK_SHIFT_CONST(5)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_SE0_COUNT_FIELD                   (_MK_MASK_CONST(0x3f) << APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_SE0_COUNT_SHIFT)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_SE0_COUNT_RANGE                   10:5
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_SE0_COUNT_WOFFSET                 0x0
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_SE0_COUNT_DEFAULT                 _MK_MASK_CONST(0x20)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_SE0_COUNT_DEFAULT_MASK                    _MK_MASK_CONST(0x3f)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_SE0_COUNT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_SE0_COUNT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Number of SEO clock cycles to block bit extraction
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EOP_START_COUNT_SHIFT                     _MK_SHIFT_CONST(11)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EOP_START_COUNT_FIELD                     (_MK_MASK_CONST(0x3f) << APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EOP_START_COUNT_SHIFT)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EOP_START_COUNT_RANGE                     16:11
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EOP_START_COUNT_WOFFSET                   0x0
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EOP_START_COUNT_DEFAULT                   _MK_MASK_CONST(0xe)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EOP_START_COUNT_DEFAULT_MASK                      _MK_MASK_CONST(0x3f)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EOP_START_COUNT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EOP_START_COUNT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Phase count on which LS bits are extracted
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EXTRACTION_COUNT_SHIFT                    _MK_SHIFT_CONST(17)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EXTRACTION_COUNT_FIELD                    (_MK_MASK_CONST(0x3f) << APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EXTRACTION_COUNT_SHIFT)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EXTRACTION_COUNT_RANGE                    22:17
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EXTRACTION_COUNT_WOFFSET                  0x0
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EXTRACTION_COUNT_DEFAULT                  _MK_MASK_CONST(0x13)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EXTRACTION_COUNT_DEFAULT_MASK                     _MK_MASK_CONST(0x3f)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EXTRACTION_COUNT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EXTRACTION_COUNT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Number of clock cycle of LS stable
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_BOUNCE_LENGTH_SHIFT                       _MK_SHIFT_CONST(23)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_BOUNCE_LENGTH_FIELD                       (_MK_MASK_CONST(0x7) << APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_BOUNCE_LENGTH_SHIFT)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_BOUNCE_LENGTH_RANGE                       25:23
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_BOUNCE_LENGTH_WOFFSET                     0x0
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_BOUNCE_LENGTH_DEFAULT                     _MK_MASK_CONST(0x4)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_BOUNCE_LENGTH_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_BOUNCE_LENGTH_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_BOUNCE_LENGTH_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Assumes line state filtering table is inclusive, not exclusive
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_EARLY_LINE_STATE_FILTER_SHIFT                        _MK_SHIFT_CONST(26)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_EARLY_LINE_STATE_FILTER_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_EARLY_LINE_STATE_FILTER_SHIFT)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_EARLY_LINE_STATE_FILTER_RANGE                        26:26
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_EARLY_LINE_STATE_FILTER_WOFFSET                      0x0
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_EARLY_LINE_STATE_FILTER_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_EARLY_LINE_STATE_FILTER_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_EARLY_LINE_STATE_FILTER_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_EARLY_LINE_STATE_FILTER_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_UTMIP_TX_CFG0_0  // UTMIP transmit config signals 
+#define APB_MISC_UTMIP_TX_CFG0_0                        _MK_ADDR_CONST(0xa20)
+#define APB_MISC_UTMIP_TX_CFG0_0_WORD_COUNT                     0x1
+#define APB_MISC_UTMIP_TX_CFG0_0_RESET_VAL                      _MK_MASK_CONST(0x90200)
+#define APB_MISC_UTMIP_TX_CFG0_0_RESET_MASK                     _MK_MASK_CONST(0xfffff)
+#define APB_MISC_UTMIP_TX_CFG0_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_READ_MASK                      _MK_MASK_CONST(0xfffff)
+#define APB_MISC_UTMIP_TX_CFG0_0_WRITE_MASK                     _MK_MASK_CONST(0xfffff)
+// Do not sent SYNC or EOP
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_SYNC_NO_EOP_SHIFT                     _MK_SHIFT_CONST(0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_SYNC_NO_EOP_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_SYNC_NO_EOP_SHIFT)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_SYNC_NO_EOP_RANGE                     0:0
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_SYNC_NO_EOP_WOFFSET                   0x0
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_SYNC_NO_EOP_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_SYNC_NO_EOP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_SYNC_NO_EOP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_SYNC_NO_EOP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// No encoding, static programming
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_ENCODING_SHIFT                        _MK_SHIFT_CONST(1)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_ENCODING_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_ENCODING_SHIFT)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_ENCODING_RANGE                        1:1
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_ENCODING_WOFFSET                      0x0
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_ENCODING_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_ENCODING_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_ENCODING_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_ENCODING_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// No bit stuffing, static programming
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_STUFFING_SHIFT                        _MK_SHIFT_CONST(2)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_STUFFING_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_STUFFING_SHIFT)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_STUFFING_RANGE                        2:2
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_STUFFING_WOFFSET                      0x0
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_STUFFING_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_STUFFING_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_STUFFING_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_STUFFING_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Sof when OpMode 2 -- not likely, for Chirp
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_ENCODE_SHIFT                   _MK_SHIFT_CONST(3)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_ENCODE_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_ENCODE_SHIFT)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_ENCODE_RANGE                   3:3
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_ENCODE_WOFFSET                 0x0
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_ENCODE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_ENCODE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_ENCODE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_ENCODE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Sof when OpMode 3 -- perhaps, when sending controller made packets
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_STUFF_SHIFT                    _MK_SHIFT_CONST(4)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_STUFF_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_STUFF_SHIFT)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_STUFF_RANGE                    4:4
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_STUFF_WOFFSET                  0x0
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_STUFF_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_STUFF_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_STUFF_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_STUFF_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// SIE, not macrocell, detects LineState change to resume
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SIE_RESUME_ON_LINESTATE_SHIFT                    _MK_SHIFT_CONST(5)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SIE_RESUME_ON_LINESTATE_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SIE_RESUME_ON_LINESTATE_SHIFT)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SIE_RESUME_ON_LINESTATE_RANGE                    5:5
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SIE_RESUME_ON_LINESTATE_WOFFSET                  0x0
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SIE_RESUME_ON_LINESTATE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SIE_RESUME_ON_LINESTATE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SIE_RESUME_ON_LINESTATE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SIE_RESUME_ON_LINESTATE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// output enable turns on  1 cycle before
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_PREAMBLE_OUTPUT_ENABLE_SHIFT                  _MK_SHIFT_CONST(6)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_PREAMBLE_OUTPUT_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_PREAMBLE_OUTPUT_ENABLE_SHIFT)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_PREAMBLE_OUTPUT_ENABLE_RANGE                  6:6
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_PREAMBLE_OUTPUT_ENABLE_WOFFSET                        0x0
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_PREAMBLE_OUTPUT_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_PREAMBLE_OUTPUT_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_PREAMBLE_OUTPUT_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_PREAMBLE_OUTPUT_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// output enable turns off 1 cycle after
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_POSTAMBLE_OUTPUT_ENABLE_SHIFT                 _MK_SHIFT_CONST(7)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_POSTAMBLE_OUTPUT_ENABLE_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_POSTAMBLE_OUTPUT_ENABLE_SHIFT)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_POSTAMBLE_OUTPUT_ENABLE_RANGE                 7:7
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_POSTAMBLE_OUTPUT_ENABLE_WOFFSET                       0x0
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_POSTAMBLE_OUTPUT_ENABLE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_POSTAMBLE_OUTPUT_ENABLE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_POSTAMBLE_OUTPUT_ENABLE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_POSTAMBLE_OUTPUT_ENABLE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Disable high speed disconnect
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_DISABLE_SHIFT                  _MK_SHIFT_CONST(8)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_DISABLE_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_DISABLE_SHIFT)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_DISABLE_RANGE                  8:8
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_DISABLE_WOFFSET                        0x0
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_DISABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_DISABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_DISABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_DISABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Only check during EOP
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_EOP_ONLY_SHIFT                 _MK_SHIFT_CONST(9)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_EOP_ONLY_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_EOP_ONLY_SHIFT)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_EOP_ONLY_RANGE                 9:9
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_EOP_ONLY_WOFFSET                       0x0
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_EOP_ONLY_DEFAULT                       _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_EOP_ONLY_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_EOP_ONLY_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_EOP_ONLY_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_TX_IPG_DLY_SHIFT                      _MK_SHIFT_CONST(10)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_TX_IPG_DLY_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_TX_IPG_DLY_SHIFT)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_TX_IPG_DLY_RANGE                      14:10
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_TX_IPG_DLY_WOFFSET                    0x0
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_TX_IPG_DLY_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_TX_IPG_DLY_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_TX_IPG_DLY_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_TX_IPG_DLY_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_READY_WAIT_FOR_VALID_SHIFT                    _MK_SHIFT_CONST(15)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_READY_WAIT_FOR_VALID_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_READY_WAIT_FOR_VALID_SHIFT)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_READY_WAIT_FOR_VALID_RANGE                    15:15
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_READY_WAIT_FOR_VALID_WOFFSET                  0x0
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_READY_WAIT_FOR_VALID_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_READY_WAIT_FOR_VALID_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_READY_WAIT_FOR_VALID_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_READY_WAIT_FOR_VALID_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Allow SOP to be source of transmit error stuffing
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FSLS_ALLOW_SOP_TX_STUFF_ERR_SHIFT                        _MK_SHIFT_CONST(16)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FSLS_ALLOW_SOP_TX_STUFF_ERR_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FSLS_ALLOW_SOP_TX_STUFF_ERR_SHIFT)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FSLS_ALLOW_SOP_TX_STUFF_ERR_RANGE                        16:16
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FSLS_ALLOW_SOP_TX_STUFF_ERR_WOFFSET                      0x0
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FSLS_ALLOW_SOP_TX_STUFF_ERR_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FSLS_ALLOW_SOP_TX_STUFF_ERR_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FSLS_ALLOW_SOP_TX_STUFF_ERR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FSLS_ALLOW_SOP_TX_STUFF_ERR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// output enable turns on  1/2 cycle before
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_OUTPUT_ENABLE_SHIFT                  _MK_SHIFT_CONST(17)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_OUTPUT_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_OUTPUT_ENABLE_SHIFT)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_OUTPUT_ENABLE_RANGE                  17:17
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_OUTPUT_ENABLE_WOFFSET                        0x0
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_OUTPUT_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_OUTPUT_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_OUTPUT_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_OUTPUT_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// output enable turns off 1/2 cycle after 
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_POSTAMBLE_OUTPUT_ENABLE_SHIFT                 _MK_SHIFT_CONST(18)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_POSTAMBLE_OUTPUT_ENABLE_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_POSTAMBLE_OUTPUT_ENABLE_SHIFT)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_POSTAMBLE_OUTPUT_ENABLE_RANGE                 18:18
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_POSTAMBLE_OUTPUT_ENABLE_WOFFSET                       0x0
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_POSTAMBLE_OUTPUT_ENABLE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_POSTAMBLE_OUTPUT_ENABLE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_POSTAMBLE_OUTPUT_ENABLE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_POSTAMBLE_OUTPUT_ENABLE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// output enable sends an initial J before sync pattern
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_J_SHIFT                      _MK_SHIFT_CONST(19)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_J_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_J_SHIFT)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_J_RANGE                      19:19
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_J_WOFFSET                    0x0
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_J_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_J_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_J_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_J_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_UTMIP_MISC_CFG0_0  // UTMIP miscellaneous configurations
+#define APB_MISC_UTMIP_MISC_CFG0_0                      _MK_ADDR_CONST(0xa24)
+#define APB_MISC_UTMIP_MISC_CFG0_0_WORD_COUNT                   0x1
+#define APB_MISC_UTMIP_MISC_CFG0_0_RESET_VAL                    _MK_MASK_CONST(0x3e00078)
+#define APB_MISC_UTMIP_MISC_CFG0_0_RESET_MASK                   _MK_MASK_CONST(0x7fffffff)
+#define APB_MISC_UTMIP_MISC_CFG0_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_READ_MASK                    _MK_MASK_CONST(0x7fffffff)
+#define APB_MISC_UTMIP_MISC_CFG0_0_WRITE_MASK                   _MK_MASK_CONST(0x7fffffff)
+// Use combinational terminations or synced through CLKXTAL
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_COMB_TERMS_SHIFT                       _MK_SHIFT_CONST(0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_COMB_TERMS_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_COMB_TERMS_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_COMB_TERMS_RANGE                       0:0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_COMB_TERMS_WOFFSET                     0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_COMB_TERMS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_COMB_TERMS_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_COMB_TERMS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_COMB_TERMS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Use free running terminations at all time
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_ALWAYS_FREE_RUNNING_TERMS_SHIFT                        _MK_SHIFT_CONST(1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_ALWAYS_FREE_RUNNING_TERMS_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_ALWAYS_FREE_RUNNING_TERMS_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_ALWAYS_FREE_RUNNING_TERMS_RANGE                        1:1
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_ALWAYS_FREE_RUNNING_TERMS_WOFFSET                      0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_ALWAYS_FREE_RUNNING_TERMS_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_ALWAYS_FREE_RUNNING_TERMS_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_ALWAYS_FREE_RUNNING_TERMS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_ALWAYS_FREE_RUNNING_TERMS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Ignore free running terminations, even when no clock
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_NEVER_FREE_RUNNING_TERMS_SHIFT                 _MK_SHIFT_CONST(2)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_NEVER_FREE_RUNNING_TERMS_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_NEVER_FREE_RUNNING_TERMS_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_NEVER_FREE_RUNNING_TERMS_RANGE                 2:2
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_NEVER_FREE_RUNNING_TERMS_WOFFSET                       0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_NEVER_FREE_RUNNING_TERMS_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_NEVER_FREE_RUNNING_TERMS_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_NEVER_FREE_RUNNING_TERMS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_NEVER_FREE_RUNNING_TERMS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Don't use free running terminations during suspend.
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_NO_FREE_ON_SUSPEND_SHIFT                       _MK_SHIFT_CONST(3)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_NO_FREE_ON_SUSPEND_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_NO_FREE_ON_SUSPEND_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_NO_FREE_ON_SUSPEND_RANGE                       3:3
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_NO_FREE_ON_SUSPEND_WOFFSET                     0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_NO_FREE_ON_SUSPEND_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_NO_FREE_ON_SUSPEND_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_NO_FREE_ON_SUSPEND_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_NO_FREE_ON_SUSPEND_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Determines if all signal need to be stable to not change a config.
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_STABLE_ALL_SHIFT                       _MK_SHIFT_CONST(4)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_STABLE_ALL_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_STABLE_ALL_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_STABLE_ALL_RANGE                       4:4
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_STABLE_ALL_WOFFSET                     0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_STABLE_ALL_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_STABLE_ALL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_STABLE_ALL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_STABLE_ALL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Number of cycles of crystal clock of signal not changing to consider stable.
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_STABLE_COUNT_SHIFT                     _MK_SHIFT_CONST(5)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_STABLE_COUNT_FIELD                     (_MK_MASK_CONST(0x7) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_STABLE_COUNT_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_STABLE_COUNT_RANGE                     7:5
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_STABLE_COUNT_WOFFSET                   0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_STABLE_COUNT_DEFAULT                   _MK_MASK_CONST(0x3)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_STABLE_COUNT_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_STABLE_COUNT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_STABLE_COUNT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Force DM pulldown active.
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DM_SHIFT                  _MK_SHIFT_CONST(8)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DM_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DM_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DM_RANGE                  8:8
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DM_WOFFSET                        0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DM_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DM_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Force DP pulldown active.
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DP_SHIFT                  _MK_SHIFT_CONST(9)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DP_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DP_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DP_RANGE                  9:9
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DP_WOFFSET                        0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DP_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DP_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Force DM pullup active.      
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DM_SHIFT                  _MK_SHIFT_CONST(10)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DM_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DM_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DM_RANGE                  10:10
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DM_WOFFSET                        0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DM_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DM_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Force DP pullup active.
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DP_SHIFT                  _MK_SHIFT_CONST(11)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DP_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DP_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DP_RANGE                  11:11
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DP_WOFFSET                        0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DP_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DP_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Force DM pulldown inactive. (Overrides FORCE_PULLDN_DM.)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DM_SHIFT                        _MK_SHIFT_CONST(12)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DM_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DM_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DM_RANGE                        12:12
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DM_WOFFSET                      0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DM_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DM_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DM_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DM_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Force DP pulldown inactive. (Overrides FORCE_PULLDN_DP.)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DP_SHIFT                        _MK_SHIFT_CONST(13)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DP_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DP_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DP_RANGE                        13:13
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DP_WOFFSET                      0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DP_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DP_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Force DM pullup inactive. (Overrides FORCE_PULLUP_DM.)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DM_SHIFT                        _MK_SHIFT_CONST(14)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DM_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DM_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DM_RANGE                        14:14
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DM_WOFFSET                      0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DM_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DM_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DM_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DM_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Force DP pullup inactive. (Overrides FORCE_PULLUP_DP.)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DP_SHIFT                        _MK_SHIFT_CONST(15)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DP_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DP_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DP_RANGE                        15:15
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DP_WOFFSET                      0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DP_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DP_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Force HS termination active.
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_TERM_SHIFT                    _MK_SHIFT_CONST(16)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_TERM_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_TERM_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_TERM_RANGE                    16:16
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_TERM_WOFFSET                  0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_TERM_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_TERM_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_TERM_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_TERM_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Force HS termination inactive.
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_HS_TERM_SHIFT                  _MK_SHIFT_CONST(17)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_HS_TERM_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_HS_TERM_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_HS_TERM_RANGE                  17:17
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_HS_TERM_WOFFSET                        0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_HS_TERM_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_HS_TERM_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_HS_TERM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_HS_TERM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Force HS clock always on.
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_CLOCK_ON_SHIFT                        _MK_SHIFT_CONST(18)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_CLOCK_ON_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_CLOCK_ON_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_CLOCK_ON_RANGE                        18:18
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_CLOCK_ON_WOFFSET                      0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_CLOCK_ON_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_CLOCK_ON_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_CLOCK_ON_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_CLOCK_ON_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Force error insertion into RX path. (Used for IOBIST.)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_INJECT_ERROR_TYPE_SHIFT                        _MK_SHIFT_CONST(19)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_INJECT_ERROR_TYPE_FIELD                        (_MK_MASK_CONST(0x3) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_INJECT_ERROR_TYPE_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_INJECT_ERROR_TYPE_RANGE                        20:19
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_INJECT_ERROR_TYPE_WOFFSET                      0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_INJECT_ERROR_TYPE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_INJECT_ERROR_TYPE_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_INJECT_ERROR_TYPE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_INJECT_ERROR_TYPE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_INJECT_ERROR_TYPE_DISABLE                      _MK_ENUM_CONST(0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_INJECT_ERROR_TYPE_BIT_ERR                      _MK_ENUM_CONST(1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_INJECT_ERROR_TYPE_RX_ERR                       _MK_ENUM_CONST(2)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_INJECT_ERROR_TYPE_BIT_RX_ERR                   _MK_ENUM_CONST(3)
+
+// Don't block changes for 4ms when going from LS to FS (should not happen)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_LS_TO_FS_SKIP_4MS_SHIFT                        _MK_SHIFT_CONST(21)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_LS_TO_FS_SKIP_4MS_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_LS_TO_FS_SKIP_4MS_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_LS_TO_FS_SKIP_4MS_RANGE                        21:21
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_LS_TO_FS_SKIP_4MS_WOFFSET                      0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_LS_TO_FS_SKIP_4MS_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_LS_TO_FS_SKIP_4MS_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_LS_TO_FS_SKIP_4MS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_LS_TO_FS_SKIP_4MS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Suspend exit requires edge or simply a value...
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_SUSPEND_EXIT_ON_EDGE_SHIFT                     _MK_SHIFT_CONST(22)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_SUSPEND_EXIT_ON_EDGE_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_SUSPEND_EXIT_ON_EDGE_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_SUSPEND_EXIT_ON_EDGE_RANGE                     22:22
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_SUSPEND_EXIT_ON_EDGE_WOFFSET                   0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_SUSPEND_EXIT_ON_EDGE_DEFAULT                   _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_SUSPEND_EXIT_ON_EDGE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_SUSPEND_EXIT_ON_EDGE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_SUSPEND_EXIT_ON_EDGE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_FS_DISABLE_ON_DEV_CHIRP_SHIFT                    _MK_SHIFT_CONST(23)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_FS_DISABLE_ON_DEV_CHIRP_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_FS_DISABLE_ON_DEV_CHIRP_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_FS_DISABLE_ON_DEV_CHIRP_RANGE                    23:23
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_FS_DISABLE_ON_DEV_CHIRP_WOFFSET                  0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_FS_DISABLE_ON_DEV_CHIRP_DEFAULT                  _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_FS_DISABLE_ON_DEV_CHIRP_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_FS_DISABLE_ON_DEV_CHIRP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_FS_DISABLE_ON_DEV_CHIRP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_ALLOW_LS_ON_SOFT_DISCON_SHIFT                  _MK_SHIFT_CONST(24)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_ALLOW_LS_ON_SOFT_DISCON_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_ALLOW_LS_ON_SOFT_DISCON_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_ALLOW_LS_ON_SOFT_DISCON_RANGE                  24:24
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_ALLOW_LS_ON_SOFT_DISCON_WOFFSET                        0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_ALLOW_LS_ON_SOFT_DISCON_DEFAULT                        _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_ALLOW_LS_ON_SOFT_DISCON_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_ALLOW_LS_ON_SOFT_DISCON_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_ALLOW_LS_ON_SOFT_DISCON_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_KEEP_XCVR_PD_ON_SOFT_DISCON_SHIFT                      _MK_SHIFT_CONST(25)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_KEEP_XCVR_PD_ON_SOFT_DISCON_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_KEEP_XCVR_PD_ON_SOFT_DISCON_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_KEEP_XCVR_PD_ON_SOFT_DISCON_RANGE                      25:25
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_KEEP_XCVR_PD_ON_SOFT_DISCON_WOFFSET                    0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_KEEP_XCVR_PD_ON_SOFT_DISCON_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_KEEP_XCVR_PD_ON_SOFT_DISCON_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_KEEP_XCVR_PD_ON_SOFT_DISCON_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_KEEP_XCVR_PD_ON_SOFT_DISCON_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Use DP/DM as obs bus
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_SHIFT                     _MK_SHIFT_CONST(26)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_RANGE                     26:26
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_WOFFSET                   0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Select DP/DM obs signals
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_SEL_SHIFT                 _MK_SHIFT_CONST(27)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_SEL_FIELD                 (_MK_MASK_CONST(0xf) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_SEL_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_SEL_RANGE                 30:27
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_SEL_WOFFSET                       0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_SEL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_SEL_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_SEL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_SEL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_UTMIP_MISC_CFG1_0  // UTMIP miscellaneous configurations
+#define APB_MISC_UTMIP_MISC_CFG1_0                      _MK_ADDR_CONST(0xa28)
+#define APB_MISC_UTMIP_MISC_CFG1_0_WORD_COUNT                   0x1
+#define APB_MISC_UTMIP_MISC_CFG1_0_RESET_VAL                    _MK_MASK_CONST(0x198024)
+#define APB_MISC_UTMIP_MISC_CFG1_0_RESET_MASK                   _MK_MASK_CONST(0x3fffffff)
+#define APB_MISC_UTMIP_MISC_CFG1_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_READ_MASK                    _MK_MASK_CONST(0x3fffffff)
+#define APB_MISC_UTMIP_MISC_CFG1_0_WRITE_MASK                   _MK_MASK_CONST(0x3fffffff)
+// Bit 0: 0: 0xa5 -> treat as KeepAlive 
+//        1: treat as regular packet 
+// Bit 1: 0: Turn on FS EOP detection
+//        1: Turn off FS EOP detection
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_XCVRSEL3_SHIFT                 _MK_SHIFT_CONST(0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_XCVRSEL3_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_XCVRSEL3_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_XCVRSEL3_RANGE                 1:0
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_XCVRSEL3_WOFFSET                       0x0
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_XCVRSEL3_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_XCVRSEL3_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_XCVRSEL3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_XCVRSEL3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_SUSPEND_TERMSEL_SHIFT                  _MK_SHIFT_CONST(2)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_SUSPEND_TERMSEL_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_SUSPEND_TERMSEL_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_SUSPEND_TERMSEL_RANGE                  2:2
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_SUSPEND_TERMSEL_WOFFSET                        0x0
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_SUSPEND_TERMSEL_DEFAULT                        _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_SUSPEND_TERMSEL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_SUSPEND_TERMSEL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_SUSPEND_TERMSEL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FLIP_FSLS_POLARITY_SHIFT                       _MK_SHIFT_CONST(3)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FLIP_FSLS_POLARITY_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FLIP_FSLS_POLARITY_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FLIP_FSLS_POLARITY_RANGE                       3:3
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FLIP_FSLS_POLARITY_WOFFSET                     0x0
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FLIP_FSLS_POLARITY_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FLIP_FSLS_POLARITY_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FLIP_FSLS_POLARITY_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FLIP_FSLS_POLARITY_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_EN_SHIFT                  _MK_SHIFT_CONST(4)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_EN_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_EN_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_EN_RANGE                  4:4
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_EN_WOFFSET                        0x0
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_EN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_CLR_SHIFT                 _MK_SHIFT_CONST(5)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_CLR_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_CLR_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_CLR_RANGE                 5:5
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_CLR_WOFFSET                       0x0
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_CLR_DEFAULT                       _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_CLR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_CLR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_CLR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// WRONG! This should be 1ms -> 0x50
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PLLU_STABLE_COUNT_SHIFT                        _MK_SHIFT_CONST(6)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PLLU_STABLE_COUNT_FIELD                        (_MK_MASK_CONST(0xfff) << APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PLLU_STABLE_COUNT_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PLLU_STABLE_COUNT_RANGE                        17:6
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PLLU_STABLE_COUNT_WOFFSET                      0x0
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PLLU_STABLE_COUNT_DEFAULT                      _MK_MASK_CONST(0x600)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PLLU_STABLE_COUNT_DEFAULT_MASK                 _MK_MASK_CONST(0xfff)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PLLU_STABLE_COUNT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PLLU_STABLE_COUNT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// 5 us / (1/19.2MHz) = 96 / 16 = 6
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT                     _MK_SHIFT_CONST(18)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PLL_ACTIVE_DLY_COUNT_FIELD                     (_MK_MASK_CONST(0x1f) << APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PLL_ACTIVE_DLY_COUNT_RANGE                     22:18
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PLL_ACTIVE_DLY_COUNT_WOFFSET                   0x0
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PLL_ACTIVE_DLY_COUNT_DEFAULT                   _MK_MASK_CONST(0x6)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PLL_ACTIVE_DLY_COUNT_DEFAULT_MASK                      _MK_MASK_CONST(0x1f)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PLL_ACTIVE_DLY_COUNT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PLL_ACTIVE_DLY_COUNT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FORCE_IOBIST_CLK_ON_SHIFT                      _MK_SHIFT_CONST(23)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FORCE_IOBIST_CLK_ON_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FORCE_IOBIST_CLK_ON_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FORCE_IOBIST_CLK_ON_RANGE                      23:23
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FORCE_IOBIST_CLK_ON_WOFFSET                    0x0
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FORCE_IOBIST_CLK_ON_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FORCE_IOBIST_CLK_ON_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FORCE_IOBIST_CLK_ON_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FORCE_IOBIST_CLK_ON_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FSLS_TDM_SHIFT                 _MK_SHIFT_CONST(24)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FSLS_TDM_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FSLS_TDM_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FSLS_TDM_RANGE                 24:24
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FSLS_TDM_WOFFSET                       0x0
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FSLS_TDM_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FSLS_TDM_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FSLS_TDM_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FSLS_TDM_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_OBS_SEL_SHIFT                  _MK_SHIFT_CONST(25)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_OBS_SEL_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_OBS_SEL_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_OBS_SEL_RANGE                  26:25
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_OBS_SEL_WOFFSET                        0x0
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_OBS_SEL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_OBS_SEL_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_OBS_SEL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_OBS_SEL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// 0: Use FS filtering on line state when XcvrSel=3
+// 1: Use LS filtering on line state when XcvrSel=3
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_XCVRSEL3_SHIFT                       _MK_SHIFT_CONST(27)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_XCVRSEL3_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_XCVRSEL3_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_XCVRSEL3_RANGE                       27:27
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_XCVRSEL3_WOFFSET                     0x0
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_XCVRSEL3_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_XCVRSEL3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_XCVRSEL3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_XCVRSEL3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Use neg edge sync for linestate
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_NEG_SHIFT                    _MK_SHIFT_CONST(28)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_NEG_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_NEG_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_NEG_RANGE                    28:28
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_NEG_WOFFSET                  0x0
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_NEG_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_NEG_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_NEG_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_NEG_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Bypass LineState reclocking logic
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_BYPASS_SHIFT                 _MK_SHIFT_CONST(29)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_BYPASS_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_BYPASS_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_BYPASS_RANGE                 29:29
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_BYPASS_WOFFSET                       0x0
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_BYPASS_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_BYPASS_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_BYPASS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_BYPASS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_UTMIP_DEBOUNCE_CFG0_0  // UTMIP Avalid and Bvalid debounce
+#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0                  _MK_ADDR_CONST(0xa2c)
+#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_WORD_COUNT                       0x1
+#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_RESET_VAL                        _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+// simulation value -- Used for interrupts
+#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_A_SHIFT                      _MK_SHIFT_CONST(0)
+#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_A_FIELD                      (_MK_MASK_CONST(0xffff) << APB_MISC_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_A_SHIFT)
+#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_A_RANGE                      15:0
+#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_A_WOFFSET                    0x0
+#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_A_DEFAULT                    _MK_MASK_CONST(0xffff)
+#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_A_DEFAULT_MASK                       _MK_MASK_CONST(0xffff)
+#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_A_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_A_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// simulation value -- Used for interrupts
+#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_B_SHIFT                      _MK_SHIFT_CONST(16)
+#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_B_FIELD                      (_MK_MASK_CONST(0xffff) << APB_MISC_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_B_SHIFT)
+#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_B_RANGE                      31:16
+#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_B_WOFFSET                    0x0
+#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_B_DEFAULT                    _MK_MASK_CONST(0xffff)
+#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_B_DEFAULT_MASK                       _MK_MASK_CONST(0xffff)
+#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_B_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_B_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_UTMIP_BAT_CHRG_CFG0_0  // UTMIP battery charger configuration
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0                  _MK_ADDR_CONST(0xa30)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_WORD_COUNT                       0x1
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_RESET_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_READ_MASK                        _MK_MASK_CONST(0x1f)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_WRITE_MASK                       _MK_MASK_CONST(0x1f)
+// Power down charger circuit
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_PD_CHRG_SHIFT                      _MK_SHIFT_CONST(0)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_PD_CHRG_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_PD_CHRG_SHIFT)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_PD_CHRG_RANGE                      0:0
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_PD_CHRG_WOFFSET                    0x0
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_PD_CHRG_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_PD_CHRG_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_PD_CHRG_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_PD_CHRG_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SINK_EN_SHIFT                   _MK_SHIFT_CONST(1)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SINK_EN_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SINK_EN_SHIFT)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SINK_EN_RANGE                   1:1
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SINK_EN_WOFFSET                 0x0
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SINK_EN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SINK_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SINK_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SINK_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SINK_EN_SHIFT                   _MK_SHIFT_CONST(2)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SINK_EN_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SINK_EN_SHIFT)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SINK_EN_RANGE                   2:2
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SINK_EN_WOFFSET                 0x0
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SINK_EN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SINK_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SINK_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SINK_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SRC_EN_SHIFT                    _MK_SHIFT_CONST(3)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SRC_EN_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SRC_EN_SHIFT)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SRC_EN_RANGE                    3:3
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SRC_EN_WOFFSET                  0x0
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SRC_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SRC_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SRC_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SRC_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SRC_EN_SHIFT                    _MK_SHIFT_CONST(4)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SRC_EN_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SRC_EN_SHIFT)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SRC_EN_RANGE                    4:4
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SRC_EN_WOFFSET                  0x0
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SRC_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SRC_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SRC_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SRC_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_UTMIP_SPARE_CFG0_0  // Utmip spare configuration bits 
+#define APB_MISC_UTMIP_SPARE_CFG0_0                     _MK_ADDR_CONST(0xa34)
+#define APB_MISC_UTMIP_SPARE_CFG0_0_WORD_COUNT                  0x1
+#define APB_MISC_UTMIP_SPARE_CFG0_0_RESET_VAL                   _MK_MASK_CONST(0xffff0000)
+#define APB_MISC_UTMIP_SPARE_CFG0_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_UTMIP_SPARE_CFG0_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_SPARE_CFG0_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_SPARE_CFG0_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_UTMIP_SPARE_CFG0_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+// Spare register bits
+// 0: HS_RX_IPG_ERROR_ENABLE
+// 1: HS_RX_FLUSH_ALAP. Flush as late as possible
+// 2: HS_RX_LATE_SQUELCH. Delay Squelch by 1 CLK480 cycle.
+//  4: ulpi input signals delay trimmer trigger. Toggling the value from 0 to 1 or from 1 to 0 will
+//     load the value of bits 6:5 into the trimmer.
+//  7:5: ulpi input signals delay trimmer value. Default is 000. Actual value won't be updated until after
+//     bit 4 is toggled.
+//  9: Select the 60Mhz source of the ulpis2s clock. When 0, the output of the USBPHY PLL in the Utmip
+//     block is selected. When 1, the output of PLL_U is used. The preference is to set it to 1 because then
+//     the USBPHY PLL can be shut down when the UTMIP phy is not in use. In that mode, however, PLL_U should be
+//     programmed to an output clock of 60Mhz instead of 12 Mhz.
+// 10: Select shadow feedback path. When 0, this selects that output straight from the ulpi_clock_out delay trimmer.
+//     When set to 1, it selects the output from the ULPI_CLOCK_LBK shadow pad. In production, the preference is to use
+//     1 since it will better match delays through the real clock path.
+// 11: E_INPUT control of ULPI_CLOCK_LBK pad. Enable input stage of the shadow pad. This should be set
+//     to 1 when we're using the shadow pad and LPBK (bit 15) is not set to 1.
+// 12: Enable LPBK of GP3_PV[0] (this is the real ULPI clock output). This will normally never
+//     be used due to reflections on the PCB, so it should be left to 0.
+// 13: Ulpi data pinmux bypass. When set to 1, the ulpi_data/ulpi_nxt/ulpi_dir/ulpi_stp signals to the pads will bypass 
+//     the pinmux logic and use a dedicated mux.
+//     This should always be set to 1 when using ULPI link or ULPI null. It should be set to 0 when using GPIO's or other
+//     interfaces.
+// 14: Ulpi clock pinmux bypass. Same as bit 13, but for the clock output. Only relevant for ulpi null since the clock is an
+//     input for ulpi link.
+// 15: Enable LPBK of ULPI_CLOCK_LBK pad. By default this is set to 0 so the real output/input stage
+//     of the pad is used. There's little reason to program this to 1.
+// 20:16: ulpi_shadow output delay trimmer. Trimmer to delay the signal that goes to the shadow path. 
+//     Only used during ulpi null.
+// 21: Output enable of ULPI_CLOCK_LBK pad. Active low. Default is 1, so the output stage is disabled.
+//     Must be programmed to 0 when using the shadow pad.
+// 26:22: ulpi pre clock delay trimmer: Trimmer to delay the signal that goes out to the real ULPI clock pad.
+//     Only used during ulpi null.
+// 27: Bypass 60Mhz Div5: when 1, bypasses the Div5 logic that's at the output of PLLU that's going into the Utmip phy.
+//     This means that PLLU is supposed to be programmed in 12Mhz mode. In this case, bit 9 should set to 0 to ensure that
+//     the null phy gets a 60Mhz clock that's created from USBPHY PLL. When set to 0, the PLLU should be programmed to 
+//     generate 60Mhz and the ulpi null clock should come straight from PLLU.
+// 28: ulpi input signals delay trimmer trigger. Toggling the value from 0 to 1 or from 1 to 0 will
+//     load the value of bits 6:5 into the trimmer.
+// 31:29: ulpi input signals delay trimmer value. Default is 000. Actual value won't be updated until after
+//     bit 4 is toggled.
+#define APB_MISC_UTMIP_SPARE_CFG0_0_UTMIP_SPARE_SHIFT                   _MK_SHIFT_CONST(0)
+#define APB_MISC_UTMIP_SPARE_CFG0_0_UTMIP_SPARE_FIELD                   (_MK_MASK_CONST(0xffffffff) << APB_MISC_UTMIP_SPARE_CFG0_0_UTMIP_SPARE_SHIFT)
+#define APB_MISC_UTMIP_SPARE_CFG0_0_UTMIP_SPARE_RANGE                   31:0
+#define APB_MISC_UTMIP_SPARE_CFG0_0_UTMIP_SPARE_WOFFSET                 0x0
+#define APB_MISC_UTMIP_SPARE_CFG0_0_UTMIP_SPARE_DEFAULT                 _MK_MASK_CONST(0xffff0000)
+#define APB_MISC_UTMIP_SPARE_CFG0_0_UTMIP_SPARE_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_UTMIP_SPARE_CFG0_0_UTMIP_SPARE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_SPARE_CFG0_0_UTMIP_SPARE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_SPARE_CFG0_0_UTMIP_SPARE_INIT_ENUM                       -65536
+
+
+//
+// REGISTER LIST
+//
+#define LIST_ARAPB_MISC_REGS(_op_) \
+_op_(APB_MISC_PP_STRAPPING_OPT_A_0) \
+_op_(APB_MISC_PP_TRISTATE_REG_A_0) \
+_op_(APB_MISC_PP_TRISTATE_REG_B_0) \
+_op_(APB_MISC_PP_TRISTATE_REG_C_0) \
+_op_(APB_MISC_PP_TRISTATE_REG_D_0) \
+_op_(APB_MISC_PP_CONFIG_CTL_0) \
+_op_(APB_MISC_PP_MISC_USB_OTG_0) \
+_op_(APB_MISC_PP_XMB_CSR_0) \
+_op_(APB_MISC_PP_XMB_NOR_FLASH_CFG_0) \
+_op_(APB_MISC_PP_XMB_MIO_CFG_0) \
+_op_(APB_MISC_PP_USB_PHY_VCTL_REG_0) \
+_op_(APB_MISC_PP_USB_PHY_PARAM_0) \
+_op_(APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0) \
+_op_(APB_MISC_PP_USB_PHY_SELF_TEST_0) \
+_op_(APB_MISC_PP_USB_PHY_VBUS_SENSORS_0) \
+_op_(APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0) \
+_op_(APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0) \
+_op_(APB_MISC_PP_MISC_SAVE_THE_DAY_0) \
+_op_(APB_MISC_PP_PIN_MUX_CTL_A_0) \
+_op_(APB_MISC_PP_PIN_MUX_CTL_B_0) \
+_op_(APB_MISC_PP_PIN_MUX_CTL_C_0) \
+_op_(APB_MISC_PP_PIN_MUX_CTL_D_0) \
+_op_(APB_MISC_PP_PIN_MUX_CTL_E_0) \
+_op_(APB_MISC_PP_PIN_MUX_CTL_F_0) \
+_op_(APB_MISC_PP_PIN_MUX_CTL_G_0) \
+_op_(APB_MISC_PP_PIN_MUX_CTL_H_0) \
+_op_(APB_MISC_PP_PULLUPDOWN_REG_A_0) \
+_op_(APB_MISC_PP_PULLUPDOWN_REG_B_0) \
+_op_(APB_MISC_PP_PULLUPDOWN_REG_C_0) \
+_op_(APB_MISC_PP_PULLUPDOWN_REG_D_0) \
+_op_(APB_MISC_PP_PULLUPDOWN_REG_E_0) \
+_op_(APB_MISC_PP_MISC_USB_CLK_RST_CTL_0) \
+_op_(APB_MISC_ASYNC_COREPWRCONFIG_0) \
+_op_(APB_MISC_ASYNC_DLYCTRL_0) \
+_op_(APB_MISC_ASYNC_CLKMNTREN_0) \
+_op_(APB_MISC_ASYNC_EMCPADEN_0) \
+_op_(APB_MISC_ASYNC_EMCPADCTRL_0) \
+_op_(APB_MISC_ASYNC_MEMPADCAL1_0) \
+_op_(APB_MISC_ASYNC_LCDPADCTRL_0) \
+_op_(APB_MISC_ASYNC_LCDPADCAL1_0) \
+_op_(APB_MISC_ASYNC_VIPADCTRL_0) \
+_op_(APB_MISC_ASYNC_VIPADCAL1_0) \
+_op_(APB_MISC_ASYNC_VCLKCTRL_0) \
+_op_(APB_MISC_ASYNC_TVDACVHSYNCCTRL_0) \
+_op_(APB_MISC_ASYNC_TVDACCNTL_0) \
+_op_(APB_MISC_ASYNC_TVDACSTATUS_0) \
+_op_(APB_MISC_ASYNC_TVDACDINCONFIG_0) \
+_op_(APB_MISC_ASYNC_INT_STATUS_0) \
+_op_(APB_MISC_ASYNC_INT_MASK_0) \
+_op_(APB_MISC_ASYNC_INT_POLARITY_0) \
+_op_(APB_MISC_ASYNC_INT_TYPE_SELECT_0) \
+_op_(APB_MISC_GP_MODEREG_0) \
+_op_(APB_MISC_GP_HIDREV_0) \
+_op_(APB_MISC_GP_ASDBGREG_0) \
+_op_(APB_MISC_GP_RESERVEREG_0) \
+_op_(APB_MISC_GP_OBSCTRL_0) \
+_op_(APB_MISC_GP_OBSDATA_0) \
+_op_(APB_MISC_GP_EFUSEREQ_0) \
+_op_(APB_MISC_GP_EFUSEOFF_0) \
+_op_(APB_MISC_GP_EFUSEWRDAT_0) \
+_op_(APB_MISC_GP_EFUSERDDAT_0) \
+_op_(APB_MISC_GP_EFUSEVAL1_0) \
+_op_(APB_MISC_GP_EFUSEVAL2_0) \
+_op_(APB_MISC_GP_EFUSEBYPASSID_0) \
+_op_(APB_MISC_GP_BRDCLK_TRIM_0) \
+_op_(APB_MISC_GP_ASDBGREG2_0) \
+_op_(APB_MISC_GP_EMU_REVID_0) \
+_op_(APB_MISC_GP_TRANSACTOR_SCRATCH_0) \
+_op_(APB_MISC_GP_AOCFG1PADCTRL_0) \
+_op_(APB_MISC_GP_AOCFG2PADCTRL_0) \
+_op_(APB_MISC_GP_ATCFG1PADCTRL_0) \
+_op_(APB_MISC_GP_ATCFG2PADCTRL_0) \
+_op_(APB_MISC_GP_CDEV1CFGPADCTRL_0) \
+_op_(APB_MISC_GP_CDEV2CFGPADCTRL_0) \
+_op_(APB_MISC_GP_CSUSCFGPADCTRL_0) \
+_op_(APB_MISC_GP_DAP1CFGPADCTRL_0) \
+_op_(APB_MISC_GP_DAP2CFGPADCTRL_0) \
+_op_(APB_MISC_GP_DAP3CFGPADCTRL_0) \
+_op_(APB_MISC_GP_DAP4CFGPADCTRL_0) \
+_op_(APB_MISC_GP_DBGCFGPADCTRL_0) \
+_op_(APB_MISC_GP_LCDCFG1PADCTRL_0) \
+_op_(APB_MISC_GP_LCDCFG2PADCTRL_0) \
+_op_(APB_MISC_GP_SDIO2CFGPADCTRL_0) \
+_op_(APB_MISC_GP_SDIO3CFGPADCTRL_0) \
+_op_(APB_MISC_GP_SPICFGPADCTRL_0) \
+_op_(APB_MISC_GP_UAACFGPADCTRL_0) \
+_op_(APB_MISC_GP_UABCFGPADCTRL_0) \
+_op_(APB_MISC_GP_UART2CFGPADCTRL_0) \
+_op_(APB_MISC_GP_UART3CFGPADCTRL_0) \
+_op_(APB_MISC_GP_VICFG1PADCTRL_0) \
+_op_(APB_MISC_GP_VICFG2PADCTRL_0) \
+_op_(APB_MISC_GP_XM2CFGAPADCTRL_0) \
+_op_(APB_MISC_GP_XM2CFGCPADCTRL_0) \
+_op_(APB_MISC_GP_XM2CFGDPADCTRL_0) \
+_op_(APB_MISC_GP_XM2CLKCFGPADCTRL_0) \
+_op_(APB_MISC_GP_MEMCOMPPADCTRL_0) \
+_op_(APB_MISC_GP_PADCTL_DFT_0) \
+_op_(APB_MISC_UTMIP_PLL_CFG0_0) \
+_op_(APB_MISC_UTMIP_PLL_CFG1_0) \
+_op_(APB_MISC_UTMIP_XCVR_CFG0_0) \
+_op_(APB_MISC_UTMIP_BIAS_CFG0_0) \
+_op_(APB_MISC_UTMIP_HSRX_CFG0_0) \
+_op_(APB_MISC_UTMIP_HSRX_CFG1_0) \
+_op_(APB_MISC_UTMIP_FSLSRX_CFG0_0) \
+_op_(APB_MISC_UTMIP_FSLSRX_CFG1_0) \
+_op_(APB_MISC_UTMIP_TX_CFG0_0) \
+_op_(APB_MISC_UTMIP_MISC_CFG0_0) \
+_op_(APB_MISC_UTMIP_MISC_CFG1_0) \
+_op_(APB_MISC_UTMIP_DEBOUNCE_CFG0_0) \
+_op_(APB_MISC_UTMIP_BAT_CHRG_CFG0_0) \
+_op_(APB_MISC_UTMIP_SPARE_CFG0_0)
+
+
+//
+// ADDRESS SPACES
+//
+
+#define BASE_ADDRESS_APB_MISC   0x00000000
+#define BASE_ADDRESS_APB_MISC_PP        0x00000000
+#define BASE_ADDRESS_APB_MISC_ASYNC     0x00000400
+#define BASE_ADDRESS_APB_MISC_GP        0x00000800
+#define BASE_ADDRESS_APB_MISC_UTMIP     0x00000a00
+
+//
+// ARAPB_MISC REGISTER BANKS
+//
+
+#define APB_MISC_PP0_FIRST_REG 0x0008 // APB_MISC_PP_STRAPPING_OPT_A_0
+#define APB_MISC_PP0_LAST_REG 0x0008 // APB_MISC_PP_STRAPPING_OPT_A_0
+#define APB_MISC_PP1_FIRST_REG 0x0014 // APB_MISC_PP_TRISTATE_REG_A_0
+#define APB_MISC_PP1_LAST_REG 0x0028 // APB_MISC_PP_MISC_USB_OTG_0
+#define APB_MISC_PP2_FIRST_REG 0x0030 // APB_MISC_PP_XMB_CSR_0
+#define APB_MISC_PP2_LAST_REG 0x0034 // APB_MISC_PP_XMB_NOR_FLASH_CFG_0
+#define APB_MISC_PP3_FIRST_REG 0x0040 // APB_MISC_PP_XMB_MIO_CFG_0
+#define APB_MISC_PP3_LAST_REG 0x0040 // APB_MISC_PP_XMB_MIO_CFG_0
+#define APB_MISC_PP4_FIRST_REG 0x0060 // APB_MISC_PP_USB_PHY_VCTL_REG_0
+#define APB_MISC_PP4_LAST_REG 0x00b4 // APB_MISC_PP_MISC_USB_CLK_RST_CTL_0
+#define APB_MISC_ASYNC0_FIRST_REG 0x0400 // APB_MISC_ASYNC_COREPWRCONFIG_0
+#define APB_MISC_ASYNC0_LAST_REG 0x0400 // APB_MISC_ASYNC_COREPWRCONFIG_0
+#define APB_MISC_ASYNC1_FIRST_REG 0x0408 // APB_MISC_ASYNC_DLYCTRL_0
+#define APB_MISC_ASYNC1_LAST_REG 0x042c // APB_MISC_ASYNC_VCLKCTRL_0
+#define APB_MISC_ASYNC2_FIRST_REG 0x0438 // APB_MISC_ASYNC_TVDACVHSYNCCTRL_0
+#define APB_MISC_ASYNC2_LAST_REG 0x0454 // APB_MISC_ASYNC_INT_TYPE_SELECT_0
+#define APB_MISC_GP0_FIRST_REG 0x0800 // APB_MISC_GP_MODEREG_0
+#define APB_MISC_GP0_LAST_REG 0x0804 // APB_MISC_GP_HIDREV_0
+#define APB_MISC_GP1_FIRST_REG 0x0810 // APB_MISC_GP_ASDBGREG_0
+#define APB_MISC_GP1_LAST_REG 0x083c // APB_MISC_GP_BRDCLK_TRIM_0
+#define APB_MISC_GP2_FIRST_REG 0x0858 // APB_MISC_GP_ASDBGREG2_0
+#define APB_MISC_GP2_LAST_REG 0x0858 // APB_MISC_GP_ASDBGREG2_0
+#define APB_MISC_GP3_FIRST_REG 0x0860 // APB_MISC_GP_EMU_REVID_0
+#define APB_MISC_GP3_LAST_REG 0x08d8 // APB_MISC_GP_PADCTL_DFT_0
+#define APB_MISC_UTMIP0_FIRST_REG 0x0a00 // APB_MISC_UTMIP_PLL_CFG0_0
+#define APB_MISC_UTMIP0_LAST_REG 0x0a34 // APB_MISC_UTMIP_SPARE_CFG0_0
+
+#ifndef _MK_SHIFT_CONST
+  #define _MK_SHIFT_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_MASK_CONST
+  #define _MK_MASK_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_ENUM_CONST
+  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
+#endif
+#ifndef _MK_ADDR_CONST
+  #define _MK_ADDR_CONST(_constant_) _constant_
+#endif
+
+#endif // ifndef ___ARAPB_MISC_H_INC_
diff --git a/arch/arm/mach-tegra/include/ap16/project_relocation_table.h b/arch/arm/mach-tegra/include/ap16/project_relocation_table.h
new file mode 100644
index 000000000000..a03e048e0149
--- /dev/null
+++ b/arch/arm/mach-tegra/include/ap16/project_relocation_table.h
@@ -0,0 +1,556 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+#ifndef PROJECT_AP15_RELOCATION_TABLE_SPEC_INC
+#define PROJECT_AP15_RELOCATION_TABLE_SPEC_INC
+
+// ------------------------------------------------------------
+//    hw nvdevids
+// ------------------------------------------------------------
+// Memory Aperture: Internal Memory
+#define NV_DEVID_IMEM                            1
+
+// Memory Aperture: External Memory
+#define NV_DEVID_EMEM                            2
+
+// Memory Aperture: TCRAM
+#define NV_DEVID_TCRAM                           3
+
+// Memory Aperture: IRAM
+#define NV_DEVID_IRAM                            4
+
+// Memory Aperture: NOR FLASH
+#define NV_DEVID_NOR                             5
+
+// Memory Aperture: EXIO
+#define NV_DEVID_EXIO                            6
+
+// Memory Aperture: GART
+#define NV_DEVID_GART                            7
+
+// Device Aperture: Graphics Host (HOST1X)
+#define NV_DEVID_HOST1X                          8
+
+// Device Aperture: ARM PERIPH registers
+#define NV_DEVID_ARM_PERIPH                      9
+
+// Device Aperture: MSELECT
+#define NV_DEVID_MSELECT                         10
+
+// Device Aperture: memory controller
+#define NV_DEVID_MC                              11
+
+// Device Aperture: external memory controller
+#define NV_DEVID_EMC                             12
+
+// Device Aperture: video input
+#define NV_DEVID_VI                              13
+
+// Device Aperture: encoder pre-processor
+#define NV_DEVID_EPP                             14
+
+// Device Aperture: video encoder
+#define NV_DEVID_MPE                             15
+
+// Device Aperture: 3D engine
+#define NV_DEVID_GR3D                            16
+
+// Device Aperture: 2D + SBLT engine
+#define NV_DEVID_GR2D                            17
+
+// Device Aperture: Image Signal Processor
+#define NV_DEVID_ISP                             18
+
+// Device Aperture: DISPLAY
+#define NV_DEVID_DISPLAY                         19
+
+// Device Aperture: UPTAG
+#define NV_DEVID_UPTAG                           20
+
+// Device Aperture - SHR_SEM
+#define NV_DEVID_SHR_SEM                         21
+
+// Device Aperture - ARB_SEM
+#define NV_DEVID_ARB_SEM                         22
+
+// Device Aperture - ARB_PRI
+#define NV_DEVID_ARB_PRI                         23
+
+// Obsoleted for AP15
+#define NV_DEVID_PRI_INTR                        24
+
+// Obsoleted for AP15
+#define NV_DEVID_SEC_INTR                        25
+
+// Device Aperture: Timer Programmable
+#define NV_DEVID_TMR                             26
+
+// Device Aperture: Clock and Reset
+#define NV_DEVID_CAR                             27
+
+// Device Aperture: Flow control
+#define NV_DEVID_FLOW                            28
+
+// Device Aperture: Event
+#define NV_DEVID_EVENT                           29
+
+// Device Aperture: AHB DMA
+#define NV_DEVID_AHB_DMA                         30
+
+// Device Aperture: APB DMA
+#define NV_DEVID_APB_DMA                         31
+
+// Device Aperture: COP Cache Controller
+#define NV_DEVID_COP_CACHE                       32
+
+// Obsolete - use COP_CACHE
+#define NV_DEVID_CC                              32
+
+// Obsolete - use COP_CACHE
+#define NV_DEVID_SYS_REG                         32
+
+// Device Aperture: System Statistic monitor
+#define NV_DEVID_STAT                            33
+
+// Device Aperture: GPIO
+#define NV_DEVID_GPIO                            34
+
+// Device Aperture: Vector Co-Processor 2
+#define NV_DEVID_VCP                             35
+
+// Device Aperture: Arm Vectors
+#define NV_DEVID_VECTOR                          36
+
+// Device: MEM
+#define NV_DEVID_MEM                             37
+
+// Obsolete - use VDE
+#define NV_DEVID_SXE                             38
+
+// Device Aperture: video decoder
+#define NV_DEVID_VDE                             38
+
+// Obsolete - use VDE
+#define NV_DEVID_BSEV                            39
+
+// Obsolete - use VDE
+#define NV_DEVID_MBE                             40
+
+// Obsolete - use VDE
+#define NV_DEVID_PPE                             41
+
+// Obsolete - use VDE
+#define NV_DEVID_MCE                             42
+
+// Obsolete - use VDE
+#define NV_DEVID_TFE                             43
+
+// Obsolete - use VDE
+#define NV_DEVID_PPB                             44
+
+// Obsolete - use VDE
+#define NV_DEVID_VDMA                            45
+
+// Obsolete - use VDE
+#define NV_DEVID_UCQ                             46
+
+// Device Aperture: BSEA (now in AVP cluster)
+#define NV_DEVID_BSEA                            47
+
+// Obsolete - use VDE
+#define NV_DEVID_FRAMEID                         48
+
+// Device Aperture: Misc regs
+#define NV_DEVID_MISC                            49
+
+// Device Aperture: AC97
+#define NV_DEVID_AC97                            50
+
+// Device Aperture: S/P-DIF
+#define NV_DEVID_SPDIF                           51
+
+// Device Aperture: I2S
+#define NV_DEVID_I2S                             52
+
+// Device Aperture: UART
+#define NV_DEVID_UART                            53
+
+// Device Aperture: VFIR
+#define NV_DEVID_VFIR                            54
+
+// Device Aperture: NAND Flash Controller
+#define NV_DEVID_NANDCTRL                        55
+
+// Obsolete - use NANDCTRL
+#define NV_DEVID_NANDFLASH                       55
+
+// Device Aperture: HSMMC
+#define NV_DEVID_HSMMC                           56
+
+// Device Aperture: XIO
+#define NV_DEVID_XIO                             57
+
+// Device Aperture: PWFM
+#define NV_DEVID_PWFM                            58
+
+// Device Aperture: MIPI
+#define NV_DEVID_MIPI_HS                         59
+
+// Device Aperture: I2C
+#define NV_DEVID_I2C                             60
+
+// Device Aperture: TWC
+#define NV_DEVID_TWC                             61
+
+// Device Aperture: SLINK
+#define NV_DEVID_SLINK                           62
+
+// Device Aperture: SLINK4B
+#define NV_DEVID_SLINK4B                         63
+
+// Device Aperture: SPI
+#define NV_DEVID_SPI                             64
+
+// Device Aperture: DVC
+#define NV_DEVID_DVC                             65
+
+// Device Aperture: RTC
+#define NV_DEVID_RTC                             66
+
+// Device Aperture: KeyBoard Controller
+#define NV_DEVID_KBC                             67
+
+// Device Aperture: PMIF
+#define NV_DEVID_PMIF                            68
+
+// Device Aperture: FUSE
+#define NV_DEVID_FUSE                            69
+
+// Device Aperture: L2 Cache Controller
+#define NV_DEVID_CMC                             70
+
+// Device Apertuer: NOR FLASH Controller
+#define NV_DEVID_NOR_REG                         71
+
+// Device Aperture: EIDE
+#define NV_DEVID_EIDE                            72
+
+// Device Aperture: USB
+#define NV_DEVID_USB                             73
+
+// Device Aperture: SDIO
+#define NV_DEVID_SDIO                            74
+
+// Device Aperture: TVO
+#define NV_DEVID_TVO                             75
+
+// Device Aperture: DSI
+#define NV_DEVID_DSI                             76
+
+// Device Aperture: HDMI
+#define NV_DEVID_HDMI                            77
+
+// Device Aperture: Third Interrupt Controller extra registers
+#define NV_DEVID_TRI_INTR                        78
+
+// Device Aperture: Common Interrupt Controller
+#define NV_DEVID_ICTLR                           79
+
+// Non-Aperture Interrupt: DMA TX interrupts
+#define NV_DEVID_DMA_TX_INTR                     80
+
+// Non-Aperture Interrupt: DMA RX interrupts
+#define NV_DEVID_DMA_RX_INTR                     81
+
+// Non-Aperture Interrupt: SW reserved interrupt
+#define NV_DEVID_SW_INTR                         82
+
+// Non-Aperture Interrupt: CPU PMU Interrupt
+#define NV_DEVID_CPU_INTR                        83
+
+// Device Aperture: Timer Free Running MicroSecond
+#define NV_DEVID_TMRUS                           84
+
+// Device Aperture: Interrupt Controller ARB_GNT Registers
+#define NV_DEVID_ICTLR_ARBGNT                    85
+
+// Device Aperture: Interrupt Controller DMA Registers
+#define NV_DEVID_ICTLR_DRQ                       86
+
+// Device Aperture: AHB DMA Channel
+#define NV_DEVID_AHB_DMA_CH                      87
+
+// Device Aperture: APB DMA Channel
+#define NV_DEVID_APB_DMA_CH                      88
+
+// Device Aperture: AHB Arbitration Controller
+#define NV_DEVID_AHB_ARBC                        89
+
+// Obsolete - use AHB_ARBC
+#define NV_DEVID_AHB_ARB_CTRL                    89
+
+// Device Aperture: AHB/APB Debug Bus Registers
+#define NV_DEVID_AHPBDEBUG                       91
+
+// Device Aperture: Secure Boot Register
+#define NV_DEVID_SECURE_BOOT                     92
+
+// Device Aperture: SPROM
+#define NV_DEVID_SPROM                           93
+
+// Memory Aperture: AHB external memory remapping
+#define NV_DEVID_AHB_EMEM                        94
+
+// Non-Aperture Interrupt: External PMU interrupt
+#define NV_DEVID_PMU_EXT                         95
+
+// Device Aperture: AHB EMEM to MC Flush Register
+#define NV_DEVID_PPCS                            96
+
+// Device Aperture: MMU TLB registers for COP/AVP
+#define NV_DEVID_MMU_TLB                         97
+
+// Device Aperture: OVG engine
+#define NV_DEVID_VG                              98
+
+// Device Aperture: CSI
+#define NV_DEVID_CSI                             99
+
+// Device ID for COP
+#define NV_DEVID_AVP                             100
+
+// Device ID for MPCORE
+#define NV_DEVID_CPU                             101
+
+// Device Aperture: ULPI controller
+#define NV_DEVID_ULPI                            102
+
+// Device Aperture: ARM CONFIG registers
+#define NV_DEVID_ARM_CONFIG                      103
+
+// Device Aperture: ARM PL310 (L2 controller)
+#define NV_DEVID_ARM_PL310                       104
+
+// Device Aperture: PCIe
+#define NV_DEVID_PCIE                            105
+
+// Device Aperture: OWR (one wire)
+#define NV_DEVID_OWR                             106
+
+// Device Aperture: AVPUCQ
+#define NV_DEVID_AVPUCQ                          107
+
+// Device Aperture: AVPBSEA (obsolete)
+#define NV_DEVID_AVPBSEA                         108
+
+// Device Aperture: Sync NOR
+#define NV_DEVID_SNOR                            109
+
+// Device Aperture: SDMMC
+#define NV_DEVID_SDMMC                           110
+
+// Device Aperture: KFUSE
+#define NV_DEVID_KFUSE                           111
+
+// Device Aperture: CSITE
+#define NV_DEVID_CSITE                           112
+
+// Non-Aperture Interrupt: ARM Interprocessor Interrupt
+#define NV_DEVID_ARM_IPI                         113
+
+// Device Aperture: ARM Interrupts 0-31
+#define NV_DEVID_ARM_ICTLR                       114
+
+// Device Aperture: IOBIST
+#define NV_DEVID_IOBIST                          115
+
+// Device Aperture: SPEEDO
+#define NV_DEVID_SPEEDO                          116
+
+// Device Aperture: LA
+#define NV_DEVID_LA                              117
+
+// Device Aperture: VS
+#define NV_DEVID_VS                              118
+
+// Device Aperture: VCI
+#define NV_DEVID_VCI                             119
+
+// Device Aperture: APBIF
+#define NV_DEVID_APBIF                           120
+
+// Device Aperture: AHUB
+#define NV_DEVID_AHUB                            121
+
+// Device Aperture: DAM
+#define NV_DEVID_DAM                             122
+
+// ------------------------------------------------------------
+//    hw powergroups
+// ------------------------------------------------------------
+// Always On
+#define NV_POWERGROUP_AO                         0
+
+// Main
+#define NV_POWERGROUP_NPG                        1
+
+// CPU related blocks
+#define NV_POWERGROUP_CPU                        2
+
+// 3D graphics
+#define NV_POWERGROUP_TD                         3
+
+// Video encode engine blocks
+#define NV_POWERGROUP_VE                         4
+
+// PCIe
+#define NV_POWERGROUP_PCIE                       5
+
+// Video decoder
+#define NV_POWERGROUP_VDE                        6
+
+// MPEG encoder
+#define NV_POWERGROUP_MPE                        7
+
+// SW define for Power Group maximum
+#define NV_POWERGROUP_MAX                        8
+
+// non-mapped power group
+#define NV_POWERGROUP_INVALID                    0xffff
+
+// SW table for mapping power group define to register enums (NV_POWERGROUP_INVALID = no mapping)
+//  use as 'int table[NV_POWERGROUP_MAX] = { NV_POWERGROUP_ENUM_TABLE }'
+#define NV_POWERGROUP_ENUM_TABLE                 NV_POWERGROUP_INVALID, NV_POWERGROUP_INVALID, 0, 1, 2, NV_POWERGROUP_INVALID, NV_POWERGROUP_INVALID, NV_POWERGROUP_INVALID
+
+// ------------------------------------------------------------
+//    relocation table data (stored in boot rom)
+// ------------------------------------------------------------
+// relocation table pointer stored at NV_RELOCATION_TABLE_OFFSET
+#define NV_RELOCATION_TABLE_PTR_OFFSET 64
+#define NV_RELOCATION_TABLE_SIZE  476
+#define NV_RELOCATION_TABLE_INIT \
+          0x00000001, 0x00020010, 0x00000000, 0x40000000, 0x005f1010, \
+          0x00000000, 0x00000000, 0x00531010, 0x00000000, 0x00000000, \
+          0x00521010, 0x00000000, 0x00000000, 0x00040010, 0x40000000, \
+          0x00008000, 0x00040010, 0x40008000, 0x00008000, 0x00040010, \
+          0x40010000, 0x00008000, 0x00040010, 0x40018000, 0x00008000, \
+          0x00081010, 0x50000000, 0x00024000, 0x00091020, 0x50040000, \
+          0x00002000, 0x000a1020, 0x50042000, 0x00001000, 0x000f1140, \
+          0x54040000, 0x00040000, 0x00631040, 0x54080000, 0x00040000, \
+          0x000d1140, 0x54080000, 0x00040000, 0x000e1040, 0x540c0000, \
+          0x00040000, 0x00121040, 0x54100000, 0x00040000, 0x00111010, \
+          0x54140000, 0x00040000, 0x00101230, 0x54180000, 0x00040000, \
+          0x00131310, 0x54200000, 0x00040000, 0x00131310, 0x54240000, \
+          0x00040000, 0x004d1210, 0x54280000, 0x00040000, 0x004b1010, \
+          0x542c0000, 0x00040000, 0x004c1110, 0x54300000, 0x00040000, \
+          0x00070010, 0x58000000, 0x01000000, 0x00141010, 0x60000000, \
+          0x00001000, 0x00151010, 0x60001000, 0x00001000, 0x00161010, \
+          0x60002000, 0x00001000, 0x00171010, 0x60003000, 0x00001000, \
+          0x004f1010, 0x60004000, 0x00000040, 0x00551010, 0x60004040, \
+          0x000000c0, 0x004f1110, 0x60004100, 0x00000040, 0x00561010, \
+          0x60004140, 0x00000008, 0x00561110, 0x60004148, 0x00000008, \
+          0x004f1210, 0x60004200, 0x00000040, 0x001a1010, 0x60005000, \
+          0x00000008, 0x001a1010, 0x60005008, 0x00000008, 0x00541010, \
+          0x60005010, 0x00000040, 0x001a1010, 0x60005050, 0x00000008, \
+          0x001a1010, 0x60005058, 0x00000008, 0x001b1110, 0x60006000, \
+          0x00001000, 0x001c1010, 0x60007000, 0x00000014, 0x001e1110, \
+          0x60008000, 0x00001000, 0x00571010, 0x60009000, 0x00000020, \
+          0x00571010, 0x60009020, 0x00000020, 0x00571010, 0x60009040, \
+          0x00000020, 0x00571010, 0x60009060, 0x00000020, 0x001f1010, \
+          0x6000a000, 0x00001000, 0x00581010, 0x6000b000, 0x00000020, \
+          0x00581010, 0x6000b020, 0x00000020, 0x00581010, 0x6000b040, \
+          0x00000020, 0x00581010, 0x6000b060, 0x00000020, 0x00581010, \
+          0x6000b080, 0x00000020, 0x00581010, 0x6000b0a0, 0x00000020, \
+          0x00581010, 0x6000b0c0, 0x00000020, 0x00581010, 0x6000b0e0, \
+          0x00000020, 0x00581010, 0x6000b100, 0x00000020, 0x00581010, \
+          0x6000b120, 0x00000020, 0x00581010, 0x6000b140, 0x00000020, \
+          0x00581010, 0x6000b160, 0x00000020, 0x00581010, 0x6000b180, \
+          0x00000020, 0x00581010, 0x6000b1a0, 0x00000020, 0x00581010, \
+          0x6000b1c0, 0x00000020, 0x00581010, 0x6000b1e0, 0x00000020, \
+          0x00201010, 0x6000c000, 0x00000400, 0x00591010, 0x6000c004, \
+          0x0000010c, 0x005b1010, 0x6000c150, 0x000000a6, 0x005c1010, \
+          0x6000c200, 0x00000004, 0x00211010, 0x6000c400, 0x00000400, \
+          0x00222010, 0x6000d000, 0x00000880, 0x00222010, 0x6000d080, \
+          0x00000880, 0x00222010, 0x6000d100, 0x00000880, 0x00222010, \
+          0x6000d180, 0x00000880, 0x00222010, 0x6000d200, 0x00000880, \
+          0x00222010, 0x6000d280, 0x00000880, 0x00231010, 0x6000e000, \
+          0x00001000, 0x00241010, 0x6000f000, 0x00001000, 0x002f1010, \
+          0x6001a000, 0x00003b00, 0x00261210, 0x6001a000, 0x00003b00, \
+          0x00311210, 0x70000000, 0x00001000, 0x00321010, 0x70002000, \
+          0x00000200, 0x00331010, 0x70002400, 0x00000200, 0x00341010, \
+          0x70002800, 0x00000100, 0x00341010, 0x70002a00, 0x00000100, \
+          0x00351110, 0x70006000, 0x00000040, 0x00351110, 0x70006040, \
+          0x00000040, 0x00361010, 0x70006100, 0x00000100, 0x00351110, \
+          0x70006200, 0x00000100, 0x00371110, 0x70008000, 0x00000100, \
+          0x00381010, 0x70008500, 0x00000100, 0x00391010, 0x70008a00, \
+          0x00000200, 0x003a1010, 0x7000a000, 0x00000100, 0x003b1010, \
+          0x7000b000, 0x00000100, 0x003c1110, 0x7000c000, 0x00000100, \
+          0x003d1010, 0x7000c100, 0x00000100, 0x00401010, 0x7000c380, \
+          0x00000030, 0x003c1110, 0x7000c400, 0x00000100, 0x00411010, \
+          0x7000d000, 0x00000200, 0x003f1010, 0x7000d300, 0x00000100, \
+          0x003e1010, 0x7000d400, 0x00000200, 0x003e1010, 0x7000d600, \
+          0x00000200, 0x003e1010, 0x7000d800, 0x00000200, 0x00421100, \
+          0x7000e000, 0x00000100, 0x00431100, 0x7000e200, 0x00000100, \
+          0x00441100, 0x7000e400, 0x00000100, 0x00461010, 0x7000e800, \
+          0x00000200, 0x005d1010, 0x7000ec00, 0x00000100, 0x000b1010, \
+          0x7000f000, 0x00000400, 0x000c1110, 0x7000f400, 0x00000400, \
+          0x00451210, 0x7000f800, 0x00000400, 0x00050010, 0x80000000, \
+          0x10000000, 0x005e0010, 0x90000000, 0x20000000, 0x00060010, \
+          0xb0000000, 0x08000000, 0x00060010, 0xb8000000, 0x08000000, \
+          0x00481010, 0xc3000000, 0x01000000, 0x00601010, 0xc4000000, \
+          0x00010000, 0x00491210, 0xc5000000, 0x00004000, 0x00491310, \
+          0xc5004000, 0x00004000, 0x004a1010, 0xc8000000, 0x00000100, \
+          0x004a1010, 0xc8000100, 0x00000100, 0x00611010, 0xf000f000, \
+          0x00001000, 0x00000000, 0x82100116, 0x81e00218, 0x8210031f, \
+          0xc2100800, 0xa2100801, 0xc2100802, 0xa2100803, 0x82100b04, \
+          0x82100d05, 0x82100e06, 0x82100f07, 0x82101008, 0x82101209, \
+          0x8210130a, 0x8210140b, 0x8210150c, 0xa1c01904, 0xc1c01905, \
+          0xc1c01906, 0xa1c01907, 0xa1c01a1d, 0xc1c01a1c, 0x81e01f1e, \
+          0x81e0201f, 0x81c02200, 0x81c02301, 0x81e02509, 0x81e0260a, \
+          0xa1e0280b, 0xc1e0280c, 0xa1c0291b, 0xc1e0291d, 0xa1c02e1a, \
+          0xc1e02e1c, 0x81e04316, 0x81e04400, 0x81e04501, 0x81e04602, \
+          0x81e04703, 0x81e04817, 0x82104917, 0x81c04a19, 0x81c04d09, \
+          0x81c04d0a, 0x81c04d0b, 0x81c04d0c, 0x81c04d08, 0x81c04d11, \
+          0x82104e10, 0x82104e18, 0x82104f11, 0x81f04f00, 0x81f04f12, \
+          0x82004f00, 0x82004f12, 0x81e0500d, 0x81f05003, 0x81f05004, \
+          0x82005003, 0x82005004, 0x81c0510d, 0x81f05102, 0x81f05101, \
+          0x82005101, 0x82005102, 0x81c05203, 0x81f05206, 0x81f05205, \
+          0x82005205, 0x82005206, 0x81e05304, 0x81f05308, 0x82005308, \
+          0x81e05405, 0x81f05409, 0x82005409, 0x81e05514, 0x81f05511, \
+          0x82005511, 0x81e0560e, 0x81f0560a, 0x8200560a, 0x81c05718, \
+          0x81c05816, 0x81c05910, 0x81e05b0f, 0x81e05c06, 0x81f05c0c, \
+          0x82005c0c, 0x81e05d08, 0x81f05d0b, 0x82005d0b, 0x81e05e07, \
+          0x81f05e07, 0x82005e07, 0x82105f14, 0x81f05f0d, 0x82005f0d, \
+          0x81e06015, 0x81e0611a, 0x81e0621b, 0x82106312, 0x82106413, \
+          0x81c06502, 0x82106615, 0x8210680f, 0x82106a0d, 0x82106b0e, \
+          0x81c07117, 0x81c07314, 0x81c07415, 0x81c0750e, 0x81c0760f, \
+          0x00000000
+#endif
diff --git a/arch/arm/mach-tegra/include/ap20/arahb_arbc.h b/arch/arm/mach-tegra/include/ap20/arahb_arbc.h
new file mode 100644
index 000000000000..a080ae40d835
--- /dev/null
+++ b/arch/arm/mach-tegra/include/ap20/arahb_arbc.h
@@ -0,0 +1,3739 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+//
+// DO NOT EDIT - generated by simspec!
+//
+
+#ifndef ___ARAHB_ARBC_H_INC_
+#define ___ARAHB_ARBC_H_INC_
+
+// Register AHB_ARBITRATION_DISABLE_0  
+#define AHB_ARBITRATION_DISABLE_0                       _MK_ADDR_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_SECURE                        0x0
+#define AHB_ARBITRATION_DISABLE_0_WORD_COUNT                    0x1
+#define AHB_ARBITRATION_DISABLE_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_RESET_MASK                    _MK_MASK_CONST(0x801f3fff)
+#define AHB_ARBITRATION_DISABLE_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_READ_MASK                     _MK_MASK_CONST(0x801f3fff)
+#define AHB_ARBITRATION_DISABLE_0_WRITE_MASK                    _MK_MASK_CONST(0x801f3fff)
+//  1 = disable bus parking.
+#define AHB_ARBITRATION_DISABLE_0_DIS_BUS_PARK_SHIFT                    _MK_SHIFT_CONST(31)
+#define AHB_ARBITRATION_DISABLE_0_DIS_BUS_PARK_FIELD                    (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_DISABLE_0_DIS_BUS_PARK_SHIFT)
+#define AHB_ARBITRATION_DISABLE_0_DIS_BUS_PARK_RANGE                    31:31
+#define AHB_ARBITRATION_DISABLE_0_DIS_BUS_PARK_WOFFSET                  0x0
+#define AHB_ARBITRATION_DISABLE_0_DIS_BUS_PARK_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_DIS_BUS_PARK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_DISABLE_0_DIS_BUS_PARK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_DIS_BUS_PARK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_DIS_BUS_PARK_ENABLE                   _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_DISABLE_0_DIS_BUS_PARK_DISABLE                  _MK_ENUM_CONST(1)
+
+//  1 = disable SDMMC3 from arbitration.
+#define AHB_ARBITRATION_DISABLE_0_SDMMC3_SHIFT                  _MK_SHIFT_CONST(20)
+#define AHB_ARBITRATION_DISABLE_0_SDMMC3_FIELD                  (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_DISABLE_0_SDMMC3_SHIFT)
+#define AHB_ARBITRATION_DISABLE_0_SDMMC3_RANGE                  20:20
+#define AHB_ARBITRATION_DISABLE_0_SDMMC3_WOFFSET                        0x0
+#define AHB_ARBITRATION_DISABLE_0_SDMMC3_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_SDMMC3_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_DISABLE_0_SDMMC3_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_SDMMC3_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_SDMMC3_ENABLE                 _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_DISABLE_0_SDMMC3_DISABLE                        _MK_ENUM_CONST(1)
+
+//  1 = disable SDMMC2 from arbitration.
+#define AHB_ARBITRATION_DISABLE_0_SDMMC2_SHIFT                  _MK_SHIFT_CONST(19)
+#define AHB_ARBITRATION_DISABLE_0_SDMMC2_FIELD                  (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_DISABLE_0_SDMMC2_SHIFT)
+#define AHB_ARBITRATION_DISABLE_0_SDMMC2_RANGE                  19:19
+#define AHB_ARBITRATION_DISABLE_0_SDMMC2_WOFFSET                        0x0
+#define AHB_ARBITRATION_DISABLE_0_SDMMC2_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_SDMMC2_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_DISABLE_0_SDMMC2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_SDMMC2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_SDMMC2_ENABLE                 _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_DISABLE_0_SDMMC2_DISABLE                        _MK_ENUM_CONST(1)
+
+//  1 = disable USB2 from arbitration.
+#define AHB_ARBITRATION_DISABLE_0_USB2_SHIFT                    _MK_SHIFT_CONST(18)
+#define AHB_ARBITRATION_DISABLE_0_USB2_FIELD                    (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_DISABLE_0_USB2_SHIFT)
+#define AHB_ARBITRATION_DISABLE_0_USB2_RANGE                    18:18
+#define AHB_ARBITRATION_DISABLE_0_USB2_WOFFSET                  0x0
+#define AHB_ARBITRATION_DISABLE_0_USB2_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_USB2_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_DISABLE_0_USB2_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_USB2_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_USB2_ENABLE                   _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_DISABLE_0_USB2_DISABLE                  _MK_ENUM_CONST(1)
+
+//  1 = disable USB3 from arbitration.
+#define AHB_ARBITRATION_DISABLE_0_USB3_SHIFT                    _MK_SHIFT_CONST(17)
+#define AHB_ARBITRATION_DISABLE_0_USB3_FIELD                    (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_DISABLE_0_USB3_SHIFT)
+#define AHB_ARBITRATION_DISABLE_0_USB3_RANGE                    17:17
+#define AHB_ARBITRATION_DISABLE_0_USB3_WOFFSET                  0x0
+#define AHB_ARBITRATION_DISABLE_0_USB3_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_USB3_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_DISABLE_0_USB3_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_USB3_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_USB3_ENABLE                   _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_DISABLE_0_USB3_DISABLE                  _MK_ENUM_CONST(1)
+
+//  1 = disable BSEA from arbitration.
+#define AHB_ARBITRATION_DISABLE_0_BSEA_SHIFT                    _MK_SHIFT_CONST(16)
+#define AHB_ARBITRATION_DISABLE_0_BSEA_FIELD                    (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_DISABLE_0_BSEA_SHIFT)
+#define AHB_ARBITRATION_DISABLE_0_BSEA_RANGE                    16:16
+#define AHB_ARBITRATION_DISABLE_0_BSEA_WOFFSET                  0x0
+#define AHB_ARBITRATION_DISABLE_0_BSEA_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_BSEA_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_DISABLE_0_BSEA_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_BSEA_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_BSEA_ENABLE                   _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_DISABLE_0_BSEA_DISABLE                  _MK_ENUM_CONST(1)
+
+//  1 = disable BSEV from arbitration.
+#define AHB_ARBITRATION_DISABLE_0_BSEV_SHIFT                    _MK_SHIFT_CONST(13)
+#define AHB_ARBITRATION_DISABLE_0_BSEV_FIELD                    (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_DISABLE_0_BSEV_SHIFT)
+#define AHB_ARBITRATION_DISABLE_0_BSEV_RANGE                    13:13
+#define AHB_ARBITRATION_DISABLE_0_BSEV_WOFFSET                  0x0
+#define AHB_ARBITRATION_DISABLE_0_BSEV_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_BSEV_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_DISABLE_0_BSEV_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_BSEV_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_BSEV_ENABLE                   _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_DISABLE_0_BSEV_DISABLE                  _MK_ENUM_CONST(1)
+
+//  1 = disable SDMMC4 from arbitration.
+#define AHB_ARBITRATION_DISABLE_0_SDMMC4_SHIFT                  _MK_SHIFT_CONST(12)
+#define AHB_ARBITRATION_DISABLE_0_SDMMC4_FIELD                  (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_DISABLE_0_SDMMC4_SHIFT)
+#define AHB_ARBITRATION_DISABLE_0_SDMMC4_RANGE                  12:12
+#define AHB_ARBITRATION_DISABLE_0_SDMMC4_WOFFSET                        0x0
+#define AHB_ARBITRATION_DISABLE_0_SDMMC4_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_SDMMC4_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_DISABLE_0_SDMMC4_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_SDMMC4_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_SDMMC4_ENABLE                 _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_DISABLE_0_SDMMC4_DISABLE                        _MK_ENUM_CONST(1)
+
+//  1 = disable SNOR from arbitration.
+#define AHB_ARBITRATION_DISABLE_0_SNOR_SHIFT                    _MK_SHIFT_CONST(11)
+#define AHB_ARBITRATION_DISABLE_0_SNOR_FIELD                    (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_DISABLE_0_SNOR_SHIFT)
+#define AHB_ARBITRATION_DISABLE_0_SNOR_RANGE                    11:11
+#define AHB_ARBITRATION_DISABLE_0_SNOR_WOFFSET                  0x0
+#define AHB_ARBITRATION_DISABLE_0_SNOR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_SNOR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_DISABLE_0_SNOR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_SNOR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_SNOR_ENABLE                   _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_DISABLE_0_SNOR_DISABLE                  _MK_ENUM_CONST(1)
+
+//  1 = disable NAND from arbitration.
+#define AHB_ARBITRATION_DISABLE_0_NAND_SHIFT                    _MK_SHIFT_CONST(10)
+#define AHB_ARBITRATION_DISABLE_0_NAND_FIELD                    (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_DISABLE_0_NAND_SHIFT)
+#define AHB_ARBITRATION_DISABLE_0_NAND_RANGE                    10:10
+#define AHB_ARBITRATION_DISABLE_0_NAND_WOFFSET                  0x0
+#define AHB_ARBITRATION_DISABLE_0_NAND_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_NAND_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_DISABLE_0_NAND_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_NAND_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_NAND_ENABLE                   _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_DISABLE_0_NAND_DISABLE                  _MK_ENUM_CONST(1)
+
+//  1 = disable SDMMC1 from arbitration.
+#define AHB_ARBITRATION_DISABLE_0_SDMMC1_SHIFT                  _MK_SHIFT_CONST(9)
+#define AHB_ARBITRATION_DISABLE_0_SDMMC1_FIELD                  (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_DISABLE_0_SDMMC1_SHIFT)
+#define AHB_ARBITRATION_DISABLE_0_SDMMC1_RANGE                  9:9
+#define AHB_ARBITRATION_DISABLE_0_SDMMC1_WOFFSET                        0x0
+#define AHB_ARBITRATION_DISABLE_0_SDMMC1_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_SDMMC1_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_DISABLE_0_SDMMC1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_SDMMC1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_SDMMC1_ENABLE                 _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_DISABLE_0_SDMMC1_DISABLE                        _MK_ENUM_CONST(1)
+
+//  1 = disable XIO from arbitration.
+#define AHB_ARBITRATION_DISABLE_0_XIO_SHIFT                     _MK_SHIFT_CONST(8)
+#define AHB_ARBITRATION_DISABLE_0_XIO_FIELD                     (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_DISABLE_0_XIO_SHIFT)
+#define AHB_ARBITRATION_DISABLE_0_XIO_RANGE                     8:8
+#define AHB_ARBITRATION_DISABLE_0_XIO_WOFFSET                   0x0
+#define AHB_ARBITRATION_DISABLE_0_XIO_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_XIO_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_DISABLE_0_XIO_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_XIO_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_XIO_ENABLE                    _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_DISABLE_0_XIO_DISABLE                   _MK_ENUM_CONST(1)
+
+//  1 = disable APB-DMA from arbitration.
+#define AHB_ARBITRATION_DISABLE_0_APBDMA_SHIFT                  _MK_SHIFT_CONST(7)
+#define AHB_ARBITRATION_DISABLE_0_APBDMA_FIELD                  (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_DISABLE_0_APBDMA_SHIFT)
+#define AHB_ARBITRATION_DISABLE_0_APBDMA_RANGE                  7:7
+#define AHB_ARBITRATION_DISABLE_0_APBDMA_WOFFSET                        0x0
+#define AHB_ARBITRATION_DISABLE_0_APBDMA_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_APBDMA_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_DISABLE_0_APBDMA_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_APBDMA_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_APBDMA_ENABLE                 _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_DISABLE_0_APBDMA_DISABLE                        _MK_ENUM_CONST(1)
+
+//  1 = disable USB from arbitration.
+#define AHB_ARBITRATION_DISABLE_0_USB_SHIFT                     _MK_SHIFT_CONST(6)
+#define AHB_ARBITRATION_DISABLE_0_USB_FIELD                     (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_DISABLE_0_USB_SHIFT)
+#define AHB_ARBITRATION_DISABLE_0_USB_RANGE                     6:6
+#define AHB_ARBITRATION_DISABLE_0_USB_WOFFSET                   0x0
+#define AHB_ARBITRATION_DISABLE_0_USB_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_USB_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_DISABLE_0_USB_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_USB_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_USB_ENABLE                    _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_DISABLE_0_USB_DISABLE                   _MK_ENUM_CONST(1)
+
+//  1 = disable AHB-DMA from arbitration.
+#define AHB_ARBITRATION_DISABLE_0_AHBDMA_SHIFT                  _MK_SHIFT_CONST(5)
+#define AHB_ARBITRATION_DISABLE_0_AHBDMA_FIELD                  (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_DISABLE_0_AHBDMA_SHIFT)
+#define AHB_ARBITRATION_DISABLE_0_AHBDMA_RANGE                  5:5
+#define AHB_ARBITRATION_DISABLE_0_AHBDMA_WOFFSET                        0x0
+#define AHB_ARBITRATION_DISABLE_0_AHBDMA_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_AHBDMA_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_DISABLE_0_AHBDMA_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_AHBDMA_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_AHBDMA_ENABLE                 _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_DISABLE_0_AHBDMA_DISABLE                        _MK_ENUM_CONST(1)
+
+//  1 = disable EIDE from arbitration.
+#define AHB_ARBITRATION_DISABLE_0_EIDE_SHIFT                    _MK_SHIFT_CONST(4)
+#define AHB_ARBITRATION_DISABLE_0_EIDE_FIELD                    (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_DISABLE_0_EIDE_SHIFT)
+#define AHB_ARBITRATION_DISABLE_0_EIDE_RANGE                    4:4
+#define AHB_ARBITRATION_DISABLE_0_EIDE_WOFFSET                  0x0
+#define AHB_ARBITRATION_DISABLE_0_EIDE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_EIDE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_DISABLE_0_EIDE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_EIDE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_EIDE_ENABLE                   _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_DISABLE_0_EIDE_DISABLE                  _MK_ENUM_CONST(1)
+
+//  1 = disable CoreSight from arbitration.
+#define AHB_ARBITRATION_DISABLE_0_CSITE_SHIFT                   _MK_SHIFT_CONST(3)
+#define AHB_ARBITRATION_DISABLE_0_CSITE_FIELD                   (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_DISABLE_0_CSITE_SHIFT)
+#define AHB_ARBITRATION_DISABLE_0_CSITE_RANGE                   3:3
+#define AHB_ARBITRATION_DISABLE_0_CSITE_WOFFSET                 0x0
+#define AHB_ARBITRATION_DISABLE_0_CSITE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_CSITE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_DISABLE_0_CSITE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_CSITE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_CSITE_ENABLE                  _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_DISABLE_0_CSITE_DISABLE                 _MK_ENUM_CONST(1)
+
+//  1 = disable VCP from arbitration.
+#define AHB_ARBITRATION_DISABLE_0_VCP_SHIFT                     _MK_SHIFT_CONST(2)
+#define AHB_ARBITRATION_DISABLE_0_VCP_FIELD                     (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_DISABLE_0_VCP_SHIFT)
+#define AHB_ARBITRATION_DISABLE_0_VCP_RANGE                     2:2
+#define AHB_ARBITRATION_DISABLE_0_VCP_WOFFSET                   0x0
+#define AHB_ARBITRATION_DISABLE_0_VCP_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_VCP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_DISABLE_0_VCP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_VCP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_VCP_ENABLE                    _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_DISABLE_0_VCP_DISABLE                   _MK_ENUM_CONST(1)
+
+//  1 = disable COP from arbitration.
+#define AHB_ARBITRATION_DISABLE_0_COP_SHIFT                     _MK_SHIFT_CONST(1)
+#define AHB_ARBITRATION_DISABLE_0_COP_FIELD                     (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_DISABLE_0_COP_SHIFT)
+#define AHB_ARBITRATION_DISABLE_0_COP_RANGE                     1:1
+#define AHB_ARBITRATION_DISABLE_0_COP_WOFFSET                   0x0
+#define AHB_ARBITRATION_DISABLE_0_COP_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_COP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_DISABLE_0_COP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_COP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_COP_ENABLE                    _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_DISABLE_0_COP_DISABLE                   _MK_ENUM_CONST(1)
+
+//  1 = disable CPU from arbitration.
+#define AHB_ARBITRATION_DISABLE_0_CPU_SHIFT                     _MK_SHIFT_CONST(0)
+#define AHB_ARBITRATION_DISABLE_0_CPU_FIELD                     (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_DISABLE_0_CPU_SHIFT)
+#define AHB_ARBITRATION_DISABLE_0_CPU_RANGE                     0:0
+#define AHB_ARBITRATION_DISABLE_0_CPU_WOFFSET                   0x0
+#define AHB_ARBITRATION_DISABLE_0_CPU_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_CPU_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_DISABLE_0_CPU_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_CPU_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_CPU_ENABLE                    _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_DISABLE_0_CPU_DISABLE                   _MK_ENUM_CONST(1)
+
+
+// Register AHB_ARBITRATION_PRIORITY_CTRL_0  ///////////////////////////////////////////////////////////////////////////////////////////////////////////////
+//
+//  The AHB arbiter implements a 2-level priority scheme.  In the 1st level, arbitration is determined between
+//  the high and low priority group according to the priority weight; the higher the weight, the higher the
+//  winning rate of the high priority group.  In the 2nd level, within each of the high/low priority group, 
+//  arbitration is determined in a round-robin fashion.
+//
+///////////////////////////////////////////////////////////////////////////////////////////////////////////////
+#define AHB_ARBITRATION_PRIORITY_CTRL_0                 _MK_ADDR_CONST(0x4)
+#define AHB_ARBITRATION_PRIORITY_CTRL_0_SECURE                  0x0
+#define AHB_ARBITRATION_PRIORITY_CTRL_0_WORD_COUNT                      0x1
+#define AHB_ARBITRATION_PRIORITY_CTRL_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_PRIORITY_CTRL_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define AHB_ARBITRATION_PRIORITY_CTRL_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_PRIORITY_CTRL_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_PRIORITY_CTRL_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define AHB_ARBITRATION_PRIORITY_CTRL_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// AHB priority weight count. This 3-bit field is  use to control 
+// the amount of attention (weight) giving to the high priority 
+// group before switching to the low priority group.
+#define AHB_ARBITRATION_PRIORITY_CTRL_0_AHB_PRIORITY_WEIGHT_SHIFT                       _MK_SHIFT_CONST(29)
+#define AHB_ARBITRATION_PRIORITY_CTRL_0_AHB_PRIORITY_WEIGHT_FIELD                       (_MK_MASK_CONST(0x7) << AHB_ARBITRATION_PRIORITY_CTRL_0_AHB_PRIORITY_WEIGHT_SHIFT)
+#define AHB_ARBITRATION_PRIORITY_CTRL_0_AHB_PRIORITY_WEIGHT_RANGE                       31:29
+#define AHB_ARBITRATION_PRIORITY_CTRL_0_AHB_PRIORITY_WEIGHT_WOFFSET                     0x0
+#define AHB_ARBITRATION_PRIORITY_CTRL_0_AHB_PRIORITY_WEIGHT_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_PRIORITY_CTRL_0_AHB_PRIORITY_WEIGHT_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
+#define AHB_ARBITRATION_PRIORITY_CTRL_0_AHB_PRIORITY_WEIGHT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_PRIORITY_CTRL_0_AHB_PRIORITY_WEIGHT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+//  0 = low priority
+#define AHB_ARBITRATION_PRIORITY_CTRL_0_AHB_PRIORITY_SELECT_SHIFT                       _MK_SHIFT_CONST(0)
+#define AHB_ARBITRATION_PRIORITY_CTRL_0_AHB_PRIORITY_SELECT_FIELD                       (_MK_MASK_CONST(0x1fffffff) << AHB_ARBITRATION_PRIORITY_CTRL_0_AHB_PRIORITY_SELECT_SHIFT)
+#define AHB_ARBITRATION_PRIORITY_CTRL_0_AHB_PRIORITY_SELECT_RANGE                       28:0
+#define AHB_ARBITRATION_PRIORITY_CTRL_0_AHB_PRIORITY_SELECT_WOFFSET                     0x0
+#define AHB_ARBITRATION_PRIORITY_CTRL_0_AHB_PRIORITY_SELECT_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_PRIORITY_CTRL_0_AHB_PRIORITY_SELECT_DEFAULT_MASK                        _MK_MASK_CONST(0x1fffffff)
+#define AHB_ARBITRATION_PRIORITY_CTRL_0_AHB_PRIORITY_SELECT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_PRIORITY_CTRL_0_AHB_PRIORITY_SELECT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register AHB_ARBITRATION_USR_PROTECT_0  
+#define AHB_ARBITRATION_USR_PROTECT_0                   _MK_ADDR_CONST(0x8)
+#define AHB_ARBITRATION_USR_PROTECT_0_SECURE                    0x0
+#define AHB_ARBITRATION_USR_PROTECT_0_WORD_COUNT                        0x1
+#define AHB_ARBITRATION_USR_PROTECT_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_USR_PROTECT_0_RESET_MASK                        _MK_MASK_CONST(0x1ff)
+#define AHB_ARBITRATION_USR_PROTECT_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_USR_PROTECT_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_USR_PROTECT_0_READ_MASK                         _MK_MASK_CONST(0x1ff)
+#define AHB_ARBITRATION_USR_PROTECT_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+// Abort on USR mode access to Cache memory space
+#define AHB_ARBITRATION_USR_PROTECT_0_CACHE_SHIFT                       _MK_SHIFT_CONST(8)
+#define AHB_ARBITRATION_USR_PROTECT_0_CACHE_FIELD                       (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_USR_PROTECT_0_CACHE_SHIFT)
+#define AHB_ARBITRATION_USR_PROTECT_0_CACHE_RANGE                       8:8
+#define AHB_ARBITRATION_USR_PROTECT_0_CACHE_WOFFSET                     0x0
+#define AHB_ARBITRATION_USR_PROTECT_0_CACHE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_USR_PROTECT_0_CACHE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_USR_PROTECT_0_CACHE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_USR_PROTECT_0_CACHE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_USR_PROTECT_0_CACHE_ABT_DIS                     _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_USR_PROTECT_0_CACHE_ABT_EN                      _MK_ENUM_CONST(1)
+
+// Abort on USR mode access to internal ROM memory  space
+#define AHB_ARBITRATION_USR_PROTECT_0_ROM_SHIFT                 _MK_SHIFT_CONST(7)
+#define AHB_ARBITRATION_USR_PROTECT_0_ROM_FIELD                 (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_USR_PROTECT_0_ROM_SHIFT)
+#define AHB_ARBITRATION_USR_PROTECT_0_ROM_RANGE                 7:7
+#define AHB_ARBITRATION_USR_PROTECT_0_ROM_WOFFSET                       0x0
+#define AHB_ARBITRATION_USR_PROTECT_0_ROM_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_USR_PROTECT_0_ROM_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_USR_PROTECT_0_ROM_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_USR_PROTECT_0_ROM_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_USR_PROTECT_0_ROM_ABT_DIS                       _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_USR_PROTECT_0_ROM_ABT_EN                        _MK_ENUM_CONST(1)
+
+// Abort on USR mode access to APB memory space
+#define AHB_ARBITRATION_USR_PROTECT_0_APB_SHIFT                 _MK_SHIFT_CONST(6)
+#define AHB_ARBITRATION_USR_PROTECT_0_APB_FIELD                 (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_USR_PROTECT_0_APB_SHIFT)
+#define AHB_ARBITRATION_USR_PROTECT_0_APB_RANGE                 6:6
+#define AHB_ARBITRATION_USR_PROTECT_0_APB_WOFFSET                       0x0
+#define AHB_ARBITRATION_USR_PROTECT_0_APB_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_USR_PROTECT_0_APB_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_USR_PROTECT_0_APB_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_USR_PROTECT_0_APB_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_USR_PROTECT_0_APB_ABT_DIS                       _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_USR_PROTECT_0_APB_ABT_EN                        _MK_ENUM_CONST(1)
+
+// Abort on USR mode access to AHB memory space
+#define AHB_ARBITRATION_USR_PROTECT_0_AHB_SHIFT                 _MK_SHIFT_CONST(5)
+#define AHB_ARBITRATION_USR_PROTECT_0_AHB_FIELD                 (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_USR_PROTECT_0_AHB_SHIFT)
+#define AHB_ARBITRATION_USR_PROTECT_0_AHB_RANGE                 5:5
+#define AHB_ARBITRATION_USR_PROTECT_0_AHB_WOFFSET                       0x0
+#define AHB_ARBITRATION_USR_PROTECT_0_AHB_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_USR_PROTECT_0_AHB_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_USR_PROTECT_0_AHB_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_USR_PROTECT_0_AHB_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_USR_PROTECT_0_AHB_ABT_DIS                       _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_USR_PROTECT_0_AHB_ABT_EN                        _MK_ENUM_CONST(1)
+
+// Abort on USR mode access to PPSB memory space
+#define AHB_ARBITRATION_USR_PROTECT_0_PPSB_SHIFT                        _MK_SHIFT_CONST(4)
+#define AHB_ARBITRATION_USR_PROTECT_0_PPSB_FIELD                        (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_USR_PROTECT_0_PPSB_SHIFT)
+#define AHB_ARBITRATION_USR_PROTECT_0_PPSB_RANGE                        4:4
+#define AHB_ARBITRATION_USR_PROTECT_0_PPSB_WOFFSET                      0x0
+#define AHB_ARBITRATION_USR_PROTECT_0_PPSB_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_USR_PROTECT_0_PPSB_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_USR_PROTECT_0_PPSB_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_USR_PROTECT_0_PPSB_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_USR_PROTECT_0_PPSB_ABT_DIS                      _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_USR_PROTECT_0_PPSB_ABT_EN                       _MK_ENUM_CONST(1)
+
+// Abort on USR mode access to iRAMd memory space
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMD_SHIFT                       _MK_SHIFT_CONST(3)
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMD_FIELD                       (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_USR_PROTECT_0_IRAMD_SHIFT)
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMD_RANGE                       3:3
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMD_WOFFSET                     0x0
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMD_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMD_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMD_ABT_DIS                     _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMD_ABT_EN                      _MK_ENUM_CONST(1)
+
+// Abort on USR mode access to iRAMc memory space
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMC_SHIFT                       _MK_SHIFT_CONST(2)
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMC_FIELD                       (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_USR_PROTECT_0_IRAMC_SHIFT)
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMC_RANGE                       2:2
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMC_WOFFSET                     0x0
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMC_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMC_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMC_ABT_DIS                     _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMC_ABT_EN                      _MK_ENUM_CONST(1)
+
+// Abort on USR mode access to iRAMb memory space
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMB_SHIFT                       _MK_SHIFT_CONST(1)
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMB_FIELD                       (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_USR_PROTECT_0_IRAMB_SHIFT)
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMB_RANGE                       1:1
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMB_WOFFSET                     0x0
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMB_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMB_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMB_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMB_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMB_ABT_DIS                     _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMB_ABT_EN                      _MK_ENUM_CONST(1)
+
+// Abort on USR mode access to iRAMa memory space
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMA_SHIFT                       _MK_SHIFT_CONST(0)
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMA_FIELD                       (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_USR_PROTECT_0_IRAMA_SHIFT)
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMA_RANGE                       0:0
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMA_WOFFSET                     0x0
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMA_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMA_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMA_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMA_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMA_ABT_DIS                     _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMA_ABT_EN                      _MK_ENUM_CONST(1)
+
+
+// Register AHB_GIZMO_AHB_MEM_0  
+#define AHB_GIZMO_AHB_MEM_0                     _MK_ADDR_CONST(0xc)
+#define AHB_GIZMO_AHB_MEM_0_SECURE                      0x0
+#define AHB_GIZMO_AHB_MEM_0_WORD_COUNT                  0x1
+#define AHB_GIZMO_AHB_MEM_0_RESET_VAL                   _MK_MASK_CONST(0x200c1)
+#define AHB_GIZMO_AHB_MEM_0_RESET_MASK                  _MK_MASK_CONST(0xff0700c7)
+#define AHB_GIZMO_AHB_MEM_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_MEM_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_MEM_0_READ_MASK                   _MK_MASK_CONST(0xff0700c7)
+#define AHB_GIZMO_AHB_MEM_0_WRITE_MASK                  _MK_MASK_CONST(0xff0700c7)
+// AHB master request negate count. This is an 8-bit counter use to indicate 
+// the minimum number of clk count between requests from  this AHB master.
+#define AHB_GIZMO_AHB_MEM_0_REQ_NEG_CNT_SHIFT                   _MK_SHIFT_CONST(24)
+#define AHB_GIZMO_AHB_MEM_0_REQ_NEG_CNT_FIELD                   (_MK_MASK_CONST(0xff) << AHB_GIZMO_AHB_MEM_0_REQ_NEG_CNT_SHIFT)
+#define AHB_GIZMO_AHB_MEM_0_REQ_NEG_CNT_RANGE                   31:24
+#define AHB_GIZMO_AHB_MEM_0_REQ_NEG_CNT_WOFFSET                 0x0
+#define AHB_GIZMO_AHB_MEM_0_REQ_NEG_CNT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_MEM_0_REQ_NEG_CNT_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define AHB_GIZMO_AHB_MEM_0_REQ_NEG_CNT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_MEM_0_REQ_NEG_CNT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// AHB master gizmo (AHB-DMA) - Start AHB write request immediately 
+// 1 = start the AHB write request immediately as soon as the device 
+// has put one write data in hte AHB gizmos queue. 0 = start the AHB 
+// write request only when all the  write data has transferred from 
+// the device to the AHB gizmos queue.
+#define AHB_GIZMO_AHB_MEM_0_IMMEDIATE_SHIFT                     _MK_SHIFT_CONST(18)
+#define AHB_GIZMO_AHB_MEM_0_IMMEDIATE_FIELD                     (_MK_MASK_CONST(0x1) << AHB_GIZMO_AHB_MEM_0_IMMEDIATE_SHIFT)
+#define AHB_GIZMO_AHB_MEM_0_IMMEDIATE_RANGE                     18:18
+#define AHB_GIZMO_AHB_MEM_0_IMMEDIATE_WOFFSET                   0x0
+#define AHB_GIZMO_AHB_MEM_0_IMMEDIATE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_MEM_0_IMMEDIATE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_AHB_MEM_0_IMMEDIATE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_MEM_0_IMMEDIATE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_MEM_0_IMMEDIATE_DISABLE                   _MK_ENUM_CONST(0)
+#define AHB_GIZMO_AHB_MEM_0_IMMEDIATE_ENABLE                    _MK_ENUM_CONST(1)
+
+// AHB master gizmo (AHB-DMA) - Maximum 
+// allowed AHB burst size. 
+// 00 = single transfer. 
+// 01 = burst-of-4. 
+// 10 = burst-of-8 
+// 11 = burst-of-16.
+#define AHB_GIZMO_AHB_MEM_0_MAX_AHB_BURSTSIZE_SHIFT                     _MK_SHIFT_CONST(16)
+#define AHB_GIZMO_AHB_MEM_0_MAX_AHB_BURSTSIZE_FIELD                     (_MK_MASK_CONST(0x3) << AHB_GIZMO_AHB_MEM_0_MAX_AHB_BURSTSIZE_SHIFT)
+#define AHB_GIZMO_AHB_MEM_0_MAX_AHB_BURSTSIZE_RANGE                     17:16
+#define AHB_GIZMO_AHB_MEM_0_MAX_AHB_BURSTSIZE_WOFFSET                   0x0
+#define AHB_GIZMO_AHB_MEM_0_MAX_AHB_BURSTSIZE_DEFAULT                   _MK_MASK_CONST(0x2)
+#define AHB_GIZMO_AHB_MEM_0_MAX_AHB_BURSTSIZE_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define AHB_GIZMO_AHB_MEM_0_MAX_AHB_BURSTSIZE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_MEM_0_MAX_AHB_BURSTSIZE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_MEM_0_MAX_AHB_BURSTSIZE_DMA_BURST_1WORDS                  _MK_ENUM_CONST(0)
+#define AHB_GIZMO_AHB_MEM_0_MAX_AHB_BURSTSIZE_DMA_BURST_4WORDS                  _MK_ENUM_CONST(1)
+#define AHB_GIZMO_AHB_MEM_0_MAX_AHB_BURSTSIZE_DMA_BURST_8WORDS                  _MK_ENUM_CONST(2)
+#define AHB_GIZMO_AHB_MEM_0_MAX_AHB_BURSTSIZE_DMA_BURST_16WORDS                 _MK_ENUM_CONST(3)
+
+// AHB slave gizmo (memory controller)-Dont split AHB write transaction 1 = dont 
+// split AHB write transaction  ever. 0 (and enable_split=1) = allow AHB write 
+// transaction to be split.
+#define AHB_GIZMO_AHB_MEM_0_DONT_SPLIT_AHB_WR_SHIFT                     _MK_SHIFT_CONST(7)
+#define AHB_GIZMO_AHB_MEM_0_DONT_SPLIT_AHB_WR_FIELD                     (_MK_MASK_CONST(0x1) << AHB_GIZMO_AHB_MEM_0_DONT_SPLIT_AHB_WR_SHIFT)
+#define AHB_GIZMO_AHB_MEM_0_DONT_SPLIT_AHB_WR_RANGE                     7:7
+#define AHB_GIZMO_AHB_MEM_0_DONT_SPLIT_AHB_WR_WOFFSET                   0x0
+#define AHB_GIZMO_AHB_MEM_0_DONT_SPLIT_AHB_WR_DEFAULT                   _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_AHB_MEM_0_DONT_SPLIT_AHB_WR_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_AHB_MEM_0_DONT_SPLIT_AHB_WR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_MEM_0_DONT_SPLIT_AHB_WR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_MEM_0_DONT_SPLIT_AHB_WR_ENABLE                    _MK_ENUM_CONST(0)
+#define AHB_GIZMO_AHB_MEM_0_DONT_SPLIT_AHB_WR_DISABLE                   _MK_ENUM_CONST(1)
+
+// AHB slave gizmo (memory controller ) - Accept AHB write request 
+// always. 1= always accept AHB write request without checking 
+// whether there is room in the queue to store the write data.Bypass 
+// Memory Controller AHB slave gizmo write queue. 0 = accept AHB 
+// write request only when theres  enough room in the queue to store 
+// all the write data. Memory controller AHB  slave gizmos write queue 
+// is used in this case.
+#define AHB_GIZMO_AHB_MEM_0_ACCEPT_AHB_WR_ALWAYS_SHIFT                  _MK_SHIFT_CONST(6)
+#define AHB_GIZMO_AHB_MEM_0_ACCEPT_AHB_WR_ALWAYS_FIELD                  (_MK_MASK_CONST(0x1) << AHB_GIZMO_AHB_MEM_0_ACCEPT_AHB_WR_ALWAYS_SHIFT)
+#define AHB_GIZMO_AHB_MEM_0_ACCEPT_AHB_WR_ALWAYS_RANGE                  6:6
+#define AHB_GIZMO_AHB_MEM_0_ACCEPT_AHB_WR_ALWAYS_WOFFSET                        0x0
+#define AHB_GIZMO_AHB_MEM_0_ACCEPT_AHB_WR_ALWAYS_DEFAULT                        _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_AHB_MEM_0_ACCEPT_AHB_WR_ALWAYS_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_AHB_MEM_0_ACCEPT_AHB_WR_ALWAYS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_MEM_0_ACCEPT_AHB_WR_ALWAYS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_MEM_0_ACCEPT_AHB_WR_ALWAYS_ACCEPT_ON_CHECK                        _MK_ENUM_CONST(0)
+#define AHB_GIZMO_AHB_MEM_0_ACCEPT_AHB_WR_ALWAYS_ACCEPT_ON_NOCHECK                      _MK_ENUM_CONST(1)
+
+// AHB slave gizmo - Enable fast re-arbitration. 1 = allow AHB master re-arbitration as 
+// soon as the device returns one read data into the gizmos queue. 0 = allow AHB master 
+// re-arbitration only when the  device returns all read data into the gizmos queue.
+#define AHB_GIZMO_AHB_MEM_0_ENB_FAST_REARBITRATE_SHIFT                  _MK_SHIFT_CONST(2)
+#define AHB_GIZMO_AHB_MEM_0_ENB_FAST_REARBITRATE_FIELD                  (_MK_MASK_CONST(0x1) << AHB_GIZMO_AHB_MEM_0_ENB_FAST_REARBITRATE_SHIFT)
+#define AHB_GIZMO_AHB_MEM_0_ENB_FAST_REARBITRATE_RANGE                  2:2
+#define AHB_GIZMO_AHB_MEM_0_ENB_FAST_REARBITRATE_WOFFSET                        0x0
+#define AHB_GIZMO_AHB_MEM_0_ENB_FAST_REARBITRATE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_MEM_0_ENB_FAST_REARBITRATE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_AHB_MEM_0_ENB_FAST_REARBITRATE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_MEM_0_ENB_FAST_REARBITRATE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_MEM_0_ENB_FAST_REARBITRATE_DISABLE                        _MK_ENUM_CONST(0)
+#define AHB_GIZMO_AHB_MEM_0_ENB_FAST_REARBITRATE_ENABLE                 _MK_ENUM_CONST(1)
+
+// AHB slave gizmo (memory controller ) - Foce all AHB transaction to single 
+// data request transaction 1 = force to single data transaction always.  
+// 0 = dont force to single data transaction.
+#define AHB_GIZMO_AHB_MEM_0_FORCE_TO_AHB_SINGLE_SHIFT                   _MK_SHIFT_CONST(1)
+#define AHB_GIZMO_AHB_MEM_0_FORCE_TO_AHB_SINGLE_FIELD                   (_MK_MASK_CONST(0x1) << AHB_GIZMO_AHB_MEM_0_FORCE_TO_AHB_SINGLE_SHIFT)
+#define AHB_GIZMO_AHB_MEM_0_FORCE_TO_AHB_SINGLE_RANGE                   1:1
+#define AHB_GIZMO_AHB_MEM_0_FORCE_TO_AHB_SINGLE_WOFFSET                 0x0
+#define AHB_GIZMO_AHB_MEM_0_FORCE_TO_AHB_SINGLE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_MEM_0_FORCE_TO_AHB_SINGLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_AHB_MEM_0_FORCE_TO_AHB_SINGLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_MEM_0_FORCE_TO_AHB_SINGLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_MEM_0_FORCE_TO_AHB_SINGLE_NOT_SINGLE_DATA                 _MK_ENUM_CONST(0)
+#define AHB_GIZMO_AHB_MEM_0_FORCE_TO_AHB_SINGLE_SINGLE_DATA                     _MK_ENUM_CONST(1)
+
+// AHB slave gizmo (memory controller ) - Enable splitting AHB transaction. 
+// 1 = enable 0 = disable.
+#define AHB_GIZMO_AHB_MEM_0_ENABLE_SPLIT_SHIFT                  _MK_SHIFT_CONST(0)
+#define AHB_GIZMO_AHB_MEM_0_ENABLE_SPLIT_FIELD                  (_MK_MASK_CONST(0x1) << AHB_GIZMO_AHB_MEM_0_ENABLE_SPLIT_SHIFT)
+#define AHB_GIZMO_AHB_MEM_0_ENABLE_SPLIT_RANGE                  0:0
+#define AHB_GIZMO_AHB_MEM_0_ENABLE_SPLIT_WOFFSET                        0x0
+#define AHB_GIZMO_AHB_MEM_0_ENABLE_SPLIT_DEFAULT                        _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_AHB_MEM_0_ENABLE_SPLIT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_AHB_MEM_0_ENABLE_SPLIT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_MEM_0_ENABLE_SPLIT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_MEM_0_ENABLE_SPLIT_DISABLE                        _MK_ENUM_CONST(0)
+#define AHB_GIZMO_AHB_MEM_0_ENABLE_SPLIT_ENABLE                 _MK_ENUM_CONST(1)
+
+
+// Register AHB_GIZMO_APB_DMA_0  
+#define AHB_GIZMO_APB_DMA_0                     _MK_ADDR_CONST(0x10)
+#define AHB_GIZMO_APB_DMA_0_SECURE                      0x0
+#define AHB_GIZMO_APB_DMA_0_WORD_COUNT                  0x1
+#define AHB_GIZMO_APB_DMA_0_RESET_VAL                   _MK_MASK_CONST(0xa0000)
+#define AHB_GIZMO_APB_DMA_0_RESET_MASK                  _MK_MASK_CONST(0xff0f0000)
+#define AHB_GIZMO_APB_DMA_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_APB_DMA_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_APB_DMA_0_READ_MASK                   _MK_MASK_CONST(0xff0f0000)
+#define AHB_GIZMO_APB_DMA_0_WRITE_MASK                  _MK_MASK_CONST(0xff0f0000)
+// AHB master request negate count. This is an 8-bit  counter use to indicate 
+// the minimum number of clk count between requests from  this AHB master.
+#define AHB_GIZMO_APB_DMA_0_REQ_NEG_CNT_SHIFT                   _MK_SHIFT_CONST(24)
+#define AHB_GIZMO_APB_DMA_0_REQ_NEG_CNT_FIELD                   (_MK_MASK_CONST(0xff) << AHB_GIZMO_APB_DMA_0_REQ_NEG_CNT_SHIFT)
+#define AHB_GIZMO_APB_DMA_0_REQ_NEG_CNT_RANGE                   31:24
+#define AHB_GIZMO_APB_DMA_0_REQ_NEG_CNT_WOFFSET                 0x0
+#define AHB_GIZMO_APB_DMA_0_REQ_NEG_CNT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_APB_DMA_0_REQ_NEG_CNT_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define AHB_GIZMO_APB_DMA_0_REQ_NEG_CNT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_APB_DMA_0_REQ_NEG_CNT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// AHB master gizmo - Pack all AHB read data.  1 = wait for all 
+// requested read data to be in the AHB gizmos queue before returning 
+// the data back to the IP. 0 = transfer each read data from the AHB 
+// to the IP  immediately.
+#define AHB_GIZMO_APB_DMA_0_RD_DATA_SHIFT                       _MK_SHIFT_CONST(19)
+#define AHB_GIZMO_APB_DMA_0_RD_DATA_FIELD                       (_MK_MASK_CONST(0x1) << AHB_GIZMO_APB_DMA_0_RD_DATA_SHIFT)
+#define AHB_GIZMO_APB_DMA_0_RD_DATA_RANGE                       19:19
+#define AHB_GIZMO_APB_DMA_0_RD_DATA_WOFFSET                     0x0
+#define AHB_GIZMO_APB_DMA_0_RD_DATA_DEFAULT                     _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_APB_DMA_0_RD_DATA_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_APB_DMA_0_RD_DATA_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_APB_DMA_0_RD_DATA_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_APB_DMA_0_RD_DATA_NO_WAIT                     _MK_ENUM_CONST(0)
+#define AHB_GIZMO_APB_DMA_0_RD_DATA_WAIT                        _MK_ENUM_CONST(1)
+
+// AHB master gizmo (AHB-DMA) - Start AHB write request immediately.  
+// 1 = start the AHB write request immediately as soon as the device has 
+// put one write data in the AHB gizmos queue. 0 = start the AHB write 
+// request only when all the  write data has transferred from the device 
+// to the AHB gizmos queue.
+#define AHB_GIZMO_APB_DMA_0_IMMEDIATE_SHIFT                     _MK_SHIFT_CONST(18)
+#define AHB_GIZMO_APB_DMA_0_IMMEDIATE_FIELD                     (_MK_MASK_CONST(0x1) << AHB_GIZMO_APB_DMA_0_IMMEDIATE_SHIFT)
+#define AHB_GIZMO_APB_DMA_0_IMMEDIATE_RANGE                     18:18
+#define AHB_GIZMO_APB_DMA_0_IMMEDIATE_WOFFSET                   0x0
+#define AHB_GIZMO_APB_DMA_0_IMMEDIATE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_APB_DMA_0_IMMEDIATE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_APB_DMA_0_IMMEDIATE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_APB_DMA_0_IMMEDIATE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_APB_DMA_0_IMMEDIATE_DISABLE                   _MK_ENUM_CONST(0)
+#define AHB_GIZMO_APB_DMA_0_IMMEDIATE_ENABLE                    _MK_ENUM_CONST(1)
+
+// AHB master gizmo - Maximum allowed 
+// AHB burst size.  
+// 00 = single transfer.  
+// 01 = burst-of-4.  
+// 10 = burst-of-8. 
+// 11 = burst-of-16.
+#define AHB_GIZMO_APB_DMA_0_MAX_AHB_BURSTSIZE_SHIFT                     _MK_SHIFT_CONST(16)
+#define AHB_GIZMO_APB_DMA_0_MAX_AHB_BURSTSIZE_FIELD                     (_MK_MASK_CONST(0x3) << AHB_GIZMO_APB_DMA_0_MAX_AHB_BURSTSIZE_SHIFT)
+#define AHB_GIZMO_APB_DMA_0_MAX_AHB_BURSTSIZE_RANGE                     17:16
+#define AHB_GIZMO_APB_DMA_0_MAX_AHB_BURSTSIZE_WOFFSET                   0x0
+#define AHB_GIZMO_APB_DMA_0_MAX_AHB_BURSTSIZE_DEFAULT                   _MK_MASK_CONST(0x2)
+#define AHB_GIZMO_APB_DMA_0_MAX_AHB_BURSTSIZE_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define AHB_GIZMO_APB_DMA_0_MAX_AHB_BURSTSIZE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_APB_DMA_0_MAX_AHB_BURSTSIZE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_APB_DMA_0_MAX_AHB_BURSTSIZE_DMA_BURST_1WORDS                  _MK_ENUM_CONST(0)
+#define AHB_GIZMO_APB_DMA_0_MAX_AHB_BURSTSIZE_DMA_BURST_4WORDS                  _MK_ENUM_CONST(1)
+#define AHB_GIZMO_APB_DMA_0_MAX_AHB_BURSTSIZE_DMA_BURST_8WORDS                  _MK_ENUM_CONST(2)
+#define AHB_GIZMO_APB_DMA_0_MAX_AHB_BURSTSIZE_DMA_BURST_16WORDS                 _MK_ENUM_CONST(3)
+
+
+// Reserved address 20 [0x14] 
+
+// Register AHB_GIZMO_IDE_0  
+#define AHB_GIZMO_IDE_0                 _MK_ADDR_CONST(0x18)
+#define AHB_GIZMO_IDE_0_SECURE                  0x0
+#define AHB_GIZMO_IDE_0_WORD_COUNT                      0x1
+#define AHB_GIZMO_IDE_0_RESET_VAL                       _MK_MASK_CONST(0x200bf)
+#define AHB_GIZMO_IDE_0_RESET_MASK                      _MK_MASK_CONST(0xff0f00ff)
+#define AHB_GIZMO_IDE_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_IDE_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_IDE_0_READ_MASK                       _MK_MASK_CONST(0xff0f00ff)
+#define AHB_GIZMO_IDE_0_WRITE_MASK                      _MK_MASK_CONST(0xff0f00ff)
+// AHB master request negate count. This is an 8-bit  counter use to indicate the minimum number of clk 
+// count between requests from  this AHB master.
+#define AHB_GIZMO_IDE_0_REQ_NEG_CNT_SHIFT                       _MK_SHIFT_CONST(24)
+#define AHB_GIZMO_IDE_0_REQ_NEG_CNT_FIELD                       (_MK_MASK_CONST(0xff) << AHB_GIZMO_IDE_0_REQ_NEG_CNT_SHIFT)
+#define AHB_GIZMO_IDE_0_REQ_NEG_CNT_RANGE                       31:24
+#define AHB_GIZMO_IDE_0_REQ_NEG_CNT_WOFFSET                     0x0
+#define AHB_GIZMO_IDE_0_REQ_NEG_CNT_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_IDE_0_REQ_NEG_CNT_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define AHB_GIZMO_IDE_0_REQ_NEG_CNT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_IDE_0_REQ_NEG_CNT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// AHB master gizmo - Pack all AHB read data.  1 = wait for all requested read data 
+// to be in the AHB gizmos queue before returning the data back to the IP. 0 = transfer 
+// each read data from the AHB to the IP  immediately.
+#define AHB_GIZMO_IDE_0_RD_DATA_SHIFT                   _MK_SHIFT_CONST(19)
+#define AHB_GIZMO_IDE_0_RD_DATA_FIELD                   (_MK_MASK_CONST(0x1) << AHB_GIZMO_IDE_0_RD_DATA_SHIFT)
+#define AHB_GIZMO_IDE_0_RD_DATA_RANGE                   19:19
+#define AHB_GIZMO_IDE_0_RD_DATA_WOFFSET                 0x0
+#define AHB_GIZMO_IDE_0_RD_DATA_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_IDE_0_RD_DATA_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_IDE_0_RD_DATA_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_IDE_0_RD_DATA_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_IDE_0_RD_DATA_NO_WAIT                 _MK_ENUM_CONST(0)
+#define AHB_GIZMO_IDE_0_RD_DATA_WAIT                    _MK_ENUM_CONST(1)
+
+// AHB master gizmo (AHB-DMA) - Start AHB write request immediately.  1 = start the 
+// AHB write request immediately as soon as the device has put one write data in the 
+// AHB gizmos queue. 0 = start the AHB write request only when all the  write data 
+// has transferred from the device to the AHB gizmos queue.
+#define AHB_GIZMO_IDE_0_IMMEDIATE_SHIFT                 _MK_SHIFT_CONST(18)
+#define AHB_GIZMO_IDE_0_IMMEDIATE_FIELD                 (_MK_MASK_CONST(0x1) << AHB_GIZMO_IDE_0_IMMEDIATE_SHIFT)
+#define AHB_GIZMO_IDE_0_IMMEDIATE_RANGE                 18:18
+#define AHB_GIZMO_IDE_0_IMMEDIATE_WOFFSET                       0x0
+#define AHB_GIZMO_IDE_0_IMMEDIATE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_IDE_0_IMMEDIATE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_IDE_0_IMMEDIATE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_IDE_0_IMMEDIATE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_IDE_0_IMMEDIATE_DISABLE                       _MK_ENUM_CONST(0)
+#define AHB_GIZMO_IDE_0_IMMEDIATE_ENABLE                        _MK_ENUM_CONST(1)
+
+// AHB master gizmo - Maximum 
+// allowed AHB burst size.  
+// 00 = single transfer.  
+// 01 = burst-of-4.  
+// 10 = burst-of-8. 
+// 11 = burst-of-16.
+#define AHB_GIZMO_IDE_0_MAX_AHB_BURSTSIZE_SHIFT                 _MK_SHIFT_CONST(16)
+#define AHB_GIZMO_IDE_0_MAX_AHB_BURSTSIZE_FIELD                 (_MK_MASK_CONST(0x3) << AHB_GIZMO_IDE_0_MAX_AHB_BURSTSIZE_SHIFT)
+#define AHB_GIZMO_IDE_0_MAX_AHB_BURSTSIZE_RANGE                 17:16
+#define AHB_GIZMO_IDE_0_MAX_AHB_BURSTSIZE_WOFFSET                       0x0
+#define AHB_GIZMO_IDE_0_MAX_AHB_BURSTSIZE_DEFAULT                       _MK_MASK_CONST(0x2)
+#define AHB_GIZMO_IDE_0_MAX_AHB_BURSTSIZE_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define AHB_GIZMO_IDE_0_MAX_AHB_BURSTSIZE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_IDE_0_MAX_AHB_BURSTSIZE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_IDE_0_MAX_AHB_BURSTSIZE_DMA_BURST_1WORDS                      _MK_ENUM_CONST(0)
+#define AHB_GIZMO_IDE_0_MAX_AHB_BURSTSIZE_DMA_BURST_4WORDS                      _MK_ENUM_CONST(1)
+#define AHB_GIZMO_IDE_0_MAX_AHB_BURSTSIZE_DMA_BURST_8WORDS                      _MK_ENUM_CONST(2)
+#define AHB_GIZMO_IDE_0_MAX_AHB_BURSTSIZE_DMA_BURST_16WORDS                     _MK_ENUM_CONST(3)
+
+// AHB slave gizmo - Dont split AHB write transaction.  1 = dont split AHB write transaction 
+// ever. 0 (and enable_split=1) = allow AHB write  transaction to be split.
+#define AHB_GIZMO_IDE_0_DONT_SPLIT_AHB_WR_SHIFT                 _MK_SHIFT_CONST(7)
+#define AHB_GIZMO_IDE_0_DONT_SPLIT_AHB_WR_FIELD                 (_MK_MASK_CONST(0x1) << AHB_GIZMO_IDE_0_DONT_SPLIT_AHB_WR_SHIFT)
+#define AHB_GIZMO_IDE_0_DONT_SPLIT_AHB_WR_RANGE                 7:7
+#define AHB_GIZMO_IDE_0_DONT_SPLIT_AHB_WR_WOFFSET                       0x0
+#define AHB_GIZMO_IDE_0_DONT_SPLIT_AHB_WR_DEFAULT                       _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_IDE_0_DONT_SPLIT_AHB_WR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_IDE_0_DONT_SPLIT_AHB_WR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_IDE_0_DONT_SPLIT_AHB_WR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_IDE_0_DONT_SPLIT_AHB_WR_ENABLE                        _MK_ENUM_CONST(0)
+#define AHB_GIZMO_IDE_0_DONT_SPLIT_AHB_WR_DISABLE                       _MK_ENUM_CONST(1)
+
+// AHB slave gizmo - Accept AHB write request always.  1 = always accept 
+// AHB write request without checking whether there is room in the queue 
+// to store the write data. 0 = accept AHB write request only when theres  
+// enough room in the queue to store all the write data.
+#define AHB_GIZMO_IDE_0_ACCEPT_AHB_WR_ALWAYS_SHIFT                      _MK_SHIFT_CONST(6)
+#define AHB_GIZMO_IDE_0_ACCEPT_AHB_WR_ALWAYS_FIELD                      (_MK_MASK_CONST(0x1) << AHB_GIZMO_IDE_0_ACCEPT_AHB_WR_ALWAYS_SHIFT)
+#define AHB_GIZMO_IDE_0_ACCEPT_AHB_WR_ALWAYS_RANGE                      6:6
+#define AHB_GIZMO_IDE_0_ACCEPT_AHB_WR_ALWAYS_WOFFSET                    0x0
+#define AHB_GIZMO_IDE_0_ACCEPT_AHB_WR_ALWAYS_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_IDE_0_ACCEPT_AHB_WR_ALWAYS_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_IDE_0_ACCEPT_AHB_WR_ALWAYS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_IDE_0_ACCEPT_AHB_WR_ALWAYS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_IDE_0_ACCEPT_AHB_WR_ALWAYS_ACCEPT_ON_CHECK                    _MK_ENUM_CONST(0)
+#define AHB_GIZMO_IDE_0_ACCEPT_AHB_WR_ALWAYS_ACCEPT_ON_NOCHECK                  _MK_ENUM_CONST(1)
+
+// AHB slave gizmo  Maximum allowed IP 
+// burst size.  
+// 00 = single transfer.  
+// 01 = burst-of-4.  
+// 10 = burst-of-8.
+// 11 = burst-of-16.
+#define AHB_GIZMO_IDE_0_MAX_IP_BURSTSIZE_SHIFT                  _MK_SHIFT_CONST(4)
+#define AHB_GIZMO_IDE_0_MAX_IP_BURSTSIZE_FIELD                  (_MK_MASK_CONST(0x3) << AHB_GIZMO_IDE_0_MAX_IP_BURSTSIZE_SHIFT)
+#define AHB_GIZMO_IDE_0_MAX_IP_BURSTSIZE_RANGE                  5:4
+#define AHB_GIZMO_IDE_0_MAX_IP_BURSTSIZE_WOFFSET                        0x0
+#define AHB_GIZMO_IDE_0_MAX_IP_BURSTSIZE_DEFAULT                        _MK_MASK_CONST(0x3)
+#define AHB_GIZMO_IDE_0_MAX_IP_BURSTSIZE_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define AHB_GIZMO_IDE_0_MAX_IP_BURSTSIZE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_IDE_0_MAX_IP_BURSTSIZE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_IDE_0_MAX_IP_BURSTSIZE_DMA_BURST_1WORDS                       _MK_ENUM_CONST(0)
+#define AHB_GIZMO_IDE_0_MAX_IP_BURSTSIZE_DMA_BURST_4WORDS                       _MK_ENUM_CONST(1)
+#define AHB_GIZMO_IDE_0_MAX_IP_BURSTSIZE_DMA_BURST_8WORDS                       _MK_ENUM_CONST(2)
+#define AHB_GIZMO_IDE_0_MAX_IP_BURSTSIZE_DMA_BURST_16WORDS                      _MK_ENUM_CONST(3)
+
+// AHB slave gizmo  Start write request to device immediately.  1 = start write request on the device side as soon 
+// as the AHB master puts data into the gizmos queue. 0 = start the device write request only when the  AHB master 
+// has placed all write data into the gizmos queue.
+#define AHB_GIZMO_IDE_0_IP_WR_REQ_IMMEDIATE_SHIFT                       _MK_SHIFT_CONST(3)
+#define AHB_GIZMO_IDE_0_IP_WR_REQ_IMMEDIATE_FIELD                       (_MK_MASK_CONST(0x1) << AHB_GIZMO_IDE_0_IP_WR_REQ_IMMEDIATE_SHIFT)
+#define AHB_GIZMO_IDE_0_IP_WR_REQ_IMMEDIATE_RANGE                       3:3
+#define AHB_GIZMO_IDE_0_IP_WR_REQ_IMMEDIATE_WOFFSET                     0x0
+#define AHB_GIZMO_IDE_0_IP_WR_REQ_IMMEDIATE_DEFAULT                     _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_IDE_0_IP_WR_REQ_IMMEDIATE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_IDE_0_IP_WR_REQ_IMMEDIATE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_IDE_0_IP_WR_REQ_IMMEDIATE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// AHB slave gizmo - Enable fast re-arbitration.  1 = allow AHB master re-arbitration as soon 
+// as the device returns one read data into the gizmos queue.0 = allow AHB master re-arbitration 
+// only when the  device returns all read data into the gizmos queue.
+#define AHB_GIZMO_IDE_0_ENB_FAST_REARBITRATE_SHIFT                      _MK_SHIFT_CONST(2)
+#define AHB_GIZMO_IDE_0_ENB_FAST_REARBITRATE_FIELD                      (_MK_MASK_CONST(0x1) << AHB_GIZMO_IDE_0_ENB_FAST_REARBITRATE_SHIFT)
+#define AHB_GIZMO_IDE_0_ENB_FAST_REARBITRATE_RANGE                      2:2
+#define AHB_GIZMO_IDE_0_ENB_FAST_REARBITRATE_WOFFSET                    0x0
+#define AHB_GIZMO_IDE_0_ENB_FAST_REARBITRATE_DEFAULT                    _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_IDE_0_ENB_FAST_REARBITRATE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_IDE_0_ENB_FAST_REARBITRATE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_IDE_0_ENB_FAST_REARBITRATE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_IDE_0_ENB_FAST_REARBITRATE_DISABLE                    _MK_ENUM_CONST(0)
+#define AHB_GIZMO_IDE_0_ENB_FAST_REARBITRATE_ENABLE                     _MK_ENUM_CONST(1)
+
+// AHB slave gizmo - Force all AHB transaction to single data request transaction.  
+// 1 = force to single data transaction always. 
+// 0 = dont force to single data  transaction.
+#define AHB_GIZMO_IDE_0_FORCE_TO_AHB_SINGLE_SHIFT                       _MK_SHIFT_CONST(1)
+#define AHB_GIZMO_IDE_0_FORCE_TO_AHB_SINGLE_FIELD                       (_MK_MASK_CONST(0x1) << AHB_GIZMO_IDE_0_FORCE_TO_AHB_SINGLE_SHIFT)
+#define AHB_GIZMO_IDE_0_FORCE_TO_AHB_SINGLE_RANGE                       1:1
+#define AHB_GIZMO_IDE_0_FORCE_TO_AHB_SINGLE_WOFFSET                     0x0
+#define AHB_GIZMO_IDE_0_FORCE_TO_AHB_SINGLE_DEFAULT                     _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_IDE_0_FORCE_TO_AHB_SINGLE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_IDE_0_FORCE_TO_AHB_SINGLE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_IDE_0_FORCE_TO_AHB_SINGLE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_IDE_0_FORCE_TO_AHB_SINGLE_NOT_SINGLE_DATA                     _MK_ENUM_CONST(0)
+#define AHB_GIZMO_IDE_0_FORCE_TO_AHB_SINGLE_SINGLE_DATA                 _MK_ENUM_CONST(1)
+
+// AHB slave gizmo - Enable splitting AHB transactions.  1 = enable, 0 = disable.
+#define AHB_GIZMO_IDE_0_ENABLE_SPLIT_SHIFT                      _MK_SHIFT_CONST(0)
+#define AHB_GIZMO_IDE_0_ENABLE_SPLIT_FIELD                      (_MK_MASK_CONST(0x1) << AHB_GIZMO_IDE_0_ENABLE_SPLIT_SHIFT)
+#define AHB_GIZMO_IDE_0_ENABLE_SPLIT_RANGE                      0:0
+#define AHB_GIZMO_IDE_0_ENABLE_SPLIT_WOFFSET                    0x0
+#define AHB_GIZMO_IDE_0_ENABLE_SPLIT_DEFAULT                    _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_IDE_0_ENABLE_SPLIT_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_IDE_0_ENABLE_SPLIT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_IDE_0_ENABLE_SPLIT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_IDE_0_ENABLE_SPLIT_DISABLE                    _MK_ENUM_CONST(0)
+#define AHB_GIZMO_IDE_0_ENABLE_SPLIT_ENABLE                     _MK_ENUM_CONST(1)
+
+
+// Register AHB_GIZMO_USB_0  
+#define AHB_GIZMO_USB_0                 _MK_ADDR_CONST(0x1c)
+#define AHB_GIZMO_USB_0_SECURE                  0x0
+#define AHB_GIZMO_USB_0_WORD_COUNT                      0x1
+#define AHB_GIZMO_USB_0_RESET_VAL                       _MK_MASK_CONST(0x20083)
+#define AHB_GIZMO_USB_0_RESET_MASK                      _MK_MASK_CONST(0xff0f00cf)
+#define AHB_GIZMO_USB_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB_0_READ_MASK                       _MK_MASK_CONST(0xff0f00cf)
+#define AHB_GIZMO_USB_0_WRITE_MASK                      _MK_MASK_CONST(0xff0f00cf)
+// AHB master request negate count. This is an 8-bit  counter use to indicate the minimum number of clk count 
+// between requests from  this AHB master.
+#define AHB_GIZMO_USB_0_REQ_NEG_CNT_SHIFT                       _MK_SHIFT_CONST(24)
+#define AHB_GIZMO_USB_0_REQ_NEG_CNT_FIELD                       (_MK_MASK_CONST(0xff) << AHB_GIZMO_USB_0_REQ_NEG_CNT_SHIFT)
+#define AHB_GIZMO_USB_0_REQ_NEG_CNT_RANGE                       31:24
+#define AHB_GIZMO_USB_0_REQ_NEG_CNT_WOFFSET                     0x0
+#define AHB_GIZMO_USB_0_REQ_NEG_CNT_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB_0_REQ_NEG_CNT_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define AHB_GIZMO_USB_0_REQ_NEG_CNT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB_0_REQ_NEG_CNT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// AHB master gizmo - Pack all AHB read data.  1 = wait for all requested read data to be in 
+// the AHB gizmos queue before returning the data back to the IP. 0 = transfer each read data 
+// from the AHB to the IP  immediately.
+#define AHB_GIZMO_USB_0_RD_DATA_SHIFT                   _MK_SHIFT_CONST(19)
+#define AHB_GIZMO_USB_0_RD_DATA_FIELD                   (_MK_MASK_CONST(0x1) << AHB_GIZMO_USB_0_RD_DATA_SHIFT)
+#define AHB_GIZMO_USB_0_RD_DATA_RANGE                   19:19
+#define AHB_GIZMO_USB_0_RD_DATA_WOFFSET                 0x0
+#define AHB_GIZMO_USB_0_RD_DATA_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB_0_RD_DATA_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_USB_0_RD_DATA_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB_0_RD_DATA_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB_0_RD_DATA_NO_WAIT                 _MK_ENUM_CONST(0)
+#define AHB_GIZMO_USB_0_RD_DATA_WAIT                    _MK_ENUM_CONST(1)
+
+// AHB master gizmo (AHB-DMA) - Start AHB write request immediately.  1 = start the AHB 
+// write request immediately as soon as the device has put one write data in the AHB gizmos 
+// queue. 0 = start the AHB write request only when all the  write data has transferred 
+// from the device to the AHB gizmos queue.
+#define AHB_GIZMO_USB_0_IMMEDIATE_SHIFT                 _MK_SHIFT_CONST(18)
+#define AHB_GIZMO_USB_0_IMMEDIATE_FIELD                 (_MK_MASK_CONST(0x1) << AHB_GIZMO_USB_0_IMMEDIATE_SHIFT)
+#define AHB_GIZMO_USB_0_IMMEDIATE_RANGE                 18:18
+#define AHB_GIZMO_USB_0_IMMEDIATE_WOFFSET                       0x0
+#define AHB_GIZMO_USB_0_IMMEDIATE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB_0_IMMEDIATE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_USB_0_IMMEDIATE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB_0_IMMEDIATE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB_0_IMMEDIATE_DISABLE                       _MK_ENUM_CONST(0)
+#define AHB_GIZMO_USB_0_IMMEDIATE_ENABLE                        _MK_ENUM_CONST(1)
+
+// AHB master gizmo - Maximum allowed 
+// AHB burst size.  
+// 00 = single transfer.  
+// 01 = burst-of-4.  
+// 10 = burst-of-8. 
+// 11 = burst-of-16.
+#define AHB_GIZMO_USB_0_MAX_AHB_BURSTSIZE_SHIFT                 _MK_SHIFT_CONST(16)
+#define AHB_GIZMO_USB_0_MAX_AHB_BURSTSIZE_FIELD                 (_MK_MASK_CONST(0x3) << AHB_GIZMO_USB_0_MAX_AHB_BURSTSIZE_SHIFT)
+#define AHB_GIZMO_USB_0_MAX_AHB_BURSTSIZE_RANGE                 17:16
+#define AHB_GIZMO_USB_0_MAX_AHB_BURSTSIZE_WOFFSET                       0x0
+#define AHB_GIZMO_USB_0_MAX_AHB_BURSTSIZE_DEFAULT                       _MK_MASK_CONST(0x2)
+#define AHB_GIZMO_USB_0_MAX_AHB_BURSTSIZE_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define AHB_GIZMO_USB_0_MAX_AHB_BURSTSIZE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB_0_MAX_AHB_BURSTSIZE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB_0_MAX_AHB_BURSTSIZE_DMA_BURST_1WORDS                      _MK_ENUM_CONST(0)
+#define AHB_GIZMO_USB_0_MAX_AHB_BURSTSIZE_DMA_BURST_4WORDS                      _MK_ENUM_CONST(1)
+#define AHB_GIZMO_USB_0_MAX_AHB_BURSTSIZE_DMA_BURST_8WORDS                      _MK_ENUM_CONST(2)
+#define AHB_GIZMO_USB_0_MAX_AHB_BURSTSIZE_DMA_BURST_16WORDS                     _MK_ENUM_CONST(3)
+
+// AHB slave gizmo - Dont split AHB write transaction.  1 = dont split AHB write transaction 
+// ever. 0 (and enable_split=1) = allow AHB write  transaction to be split.
+#define AHB_GIZMO_USB_0_DONT_SPLIT_AHB_WR_SHIFT                 _MK_SHIFT_CONST(7)
+#define AHB_GIZMO_USB_0_DONT_SPLIT_AHB_WR_FIELD                 (_MK_MASK_CONST(0x1) << AHB_GIZMO_USB_0_DONT_SPLIT_AHB_WR_SHIFT)
+#define AHB_GIZMO_USB_0_DONT_SPLIT_AHB_WR_RANGE                 7:7
+#define AHB_GIZMO_USB_0_DONT_SPLIT_AHB_WR_WOFFSET                       0x0
+#define AHB_GIZMO_USB_0_DONT_SPLIT_AHB_WR_DEFAULT                       _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_USB_0_DONT_SPLIT_AHB_WR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_USB_0_DONT_SPLIT_AHB_WR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB_0_DONT_SPLIT_AHB_WR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB_0_DONT_SPLIT_AHB_WR_ENABLE                        _MK_ENUM_CONST(0)
+#define AHB_GIZMO_USB_0_DONT_SPLIT_AHB_WR_DISABLE                       _MK_ENUM_CONST(1)
+
+// AHB slave gizmo - Accept AHB write request always.  1 = always accept 
+// AHB write request without checking whether there is room in the queue 
+// to store the write data. 0 = accept AHB write request only when theres  
+// enough room in the queue to store all the write data.
+#define AHB_GIZMO_USB_0_ACCEPT_AHB_WR_ALWAYS_SHIFT                      _MK_SHIFT_CONST(6)
+#define AHB_GIZMO_USB_0_ACCEPT_AHB_WR_ALWAYS_FIELD                      (_MK_MASK_CONST(0x1) << AHB_GIZMO_USB_0_ACCEPT_AHB_WR_ALWAYS_SHIFT)
+#define AHB_GIZMO_USB_0_ACCEPT_AHB_WR_ALWAYS_RANGE                      6:6
+#define AHB_GIZMO_USB_0_ACCEPT_AHB_WR_ALWAYS_WOFFSET                    0x0
+#define AHB_GIZMO_USB_0_ACCEPT_AHB_WR_ALWAYS_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB_0_ACCEPT_AHB_WR_ALWAYS_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_USB_0_ACCEPT_AHB_WR_ALWAYS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB_0_ACCEPT_AHB_WR_ALWAYS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB_0_ACCEPT_AHB_WR_ALWAYS_ACCEPT_ON_CHECK                    _MK_ENUM_CONST(0)
+#define AHB_GIZMO_USB_0_ACCEPT_AHB_WR_ALWAYS_ACCEPT_ON_NOCHECK                  _MK_ENUM_CONST(1)
+
+// AHB slave gizmo  Start write request to device immediately.  1 = start write request on 
+// the device side as soon as the AHB master puts data into the gizmos queue. 0 = start the 
+// device write request only when the  AHB master has placed all write data into the gizmos 
+// queue.
+#define AHB_GIZMO_USB_0_IP_WR_REQ_IMMEDIATE_SHIFT                       _MK_SHIFT_CONST(3)
+#define AHB_GIZMO_USB_0_IP_WR_REQ_IMMEDIATE_FIELD                       (_MK_MASK_CONST(0x1) << AHB_GIZMO_USB_0_IP_WR_REQ_IMMEDIATE_SHIFT)
+#define AHB_GIZMO_USB_0_IP_WR_REQ_IMMEDIATE_RANGE                       3:3
+#define AHB_GIZMO_USB_0_IP_WR_REQ_IMMEDIATE_WOFFSET                     0x0
+#define AHB_GIZMO_USB_0_IP_WR_REQ_IMMEDIATE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB_0_IP_WR_REQ_IMMEDIATE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_USB_0_IP_WR_REQ_IMMEDIATE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB_0_IP_WR_REQ_IMMEDIATE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB_0_IP_WR_REQ_IMMEDIATE_DISABLE                     _MK_ENUM_CONST(0)
+#define AHB_GIZMO_USB_0_IP_WR_REQ_IMMEDIATE_ENABLE                      _MK_ENUM_CONST(1)
+
+// AHB slave gizmo - Enable fast re-arbitration.  1 = allow AHB master re-arbitration as soon 
+// as the device returns one read data into the gizmos queue. 0 = allow AHB master 
+// re-arbitration only when the  device returns all read data into the gizmos queue.
+#define AHB_GIZMO_USB_0_ENB_FAST_REARBITRATE_SHIFT                      _MK_SHIFT_CONST(2)
+#define AHB_GIZMO_USB_0_ENB_FAST_REARBITRATE_FIELD                      (_MK_MASK_CONST(0x1) << AHB_GIZMO_USB_0_ENB_FAST_REARBITRATE_SHIFT)
+#define AHB_GIZMO_USB_0_ENB_FAST_REARBITRATE_RANGE                      2:2
+#define AHB_GIZMO_USB_0_ENB_FAST_REARBITRATE_WOFFSET                    0x0
+#define AHB_GIZMO_USB_0_ENB_FAST_REARBITRATE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB_0_ENB_FAST_REARBITRATE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_USB_0_ENB_FAST_REARBITRATE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB_0_ENB_FAST_REARBITRATE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB_0_ENB_FAST_REARBITRATE_DISABLE                    _MK_ENUM_CONST(0)
+#define AHB_GIZMO_USB_0_ENB_FAST_REARBITRATE_ENABLE                     _MK_ENUM_CONST(1)
+
+// AHB slave gizmo - Force all AHB transaction to single data request transaction.  
+// 1 = force to single data transaction always. 
+// 0 = dont force to single data transaction.
+#define AHB_GIZMO_USB_0_FORCE_TO_AHB_SINGLE_SHIFT                       _MK_SHIFT_CONST(1)
+#define AHB_GIZMO_USB_0_FORCE_TO_AHB_SINGLE_FIELD                       (_MK_MASK_CONST(0x1) << AHB_GIZMO_USB_0_FORCE_TO_AHB_SINGLE_SHIFT)
+#define AHB_GIZMO_USB_0_FORCE_TO_AHB_SINGLE_RANGE                       1:1
+#define AHB_GIZMO_USB_0_FORCE_TO_AHB_SINGLE_WOFFSET                     0x0
+#define AHB_GIZMO_USB_0_FORCE_TO_AHB_SINGLE_DEFAULT                     _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_USB_0_FORCE_TO_AHB_SINGLE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_USB_0_FORCE_TO_AHB_SINGLE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB_0_FORCE_TO_AHB_SINGLE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB_0_FORCE_TO_AHB_SINGLE_NOT_SINGLE_DATA                     _MK_ENUM_CONST(0)
+#define AHB_GIZMO_USB_0_FORCE_TO_AHB_SINGLE_SINGLE_DATA                 _MK_ENUM_CONST(1)
+
+//AHB slave gizmo - Enable splitting AHB transactions.  1 = enable  0 = disable
+#define AHB_GIZMO_USB_0_ENABLE_SPLIT_SHIFT                      _MK_SHIFT_CONST(0)
+#define AHB_GIZMO_USB_0_ENABLE_SPLIT_FIELD                      (_MK_MASK_CONST(0x1) << AHB_GIZMO_USB_0_ENABLE_SPLIT_SHIFT)
+#define AHB_GIZMO_USB_0_ENABLE_SPLIT_RANGE                      0:0
+#define AHB_GIZMO_USB_0_ENABLE_SPLIT_WOFFSET                    0x0
+#define AHB_GIZMO_USB_0_ENABLE_SPLIT_DEFAULT                    _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_USB_0_ENABLE_SPLIT_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_USB_0_ENABLE_SPLIT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB_0_ENABLE_SPLIT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB_0_ENABLE_SPLIT_DISABLE                    _MK_ENUM_CONST(0)
+#define AHB_GIZMO_USB_0_ENABLE_SPLIT_ENABLE                     _MK_ENUM_CONST(1)
+
+
+// Register AHB_GIZMO_AHB_XBAR_BRIDGE_0  
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0                     _MK_ADDR_CONST(0x20)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_SECURE                      0x0
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_WORD_COUNT                  0x1
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_RESET_VAL                   _MK_MASK_CONST(0x8d)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_RESET_MASK                  _MK_MASK_CONST(0xff)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_READ_MASK                   _MK_MASK_CONST(0xff)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
+// AHB slave gizmo - Dont split AHB write transaction.  1 = dont split AHB write transaction ever. 
+// 0 (and enable_split=1) = allow AHB write  transaction to be split.
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_DONT_SPLIT_AHB_WR_SHIFT                     _MK_SHIFT_CONST(7)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_DONT_SPLIT_AHB_WR_FIELD                     (_MK_MASK_CONST(0x1) << AHB_GIZMO_AHB_XBAR_BRIDGE_0_DONT_SPLIT_AHB_WR_SHIFT)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_DONT_SPLIT_AHB_WR_RANGE                     7:7
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_DONT_SPLIT_AHB_WR_WOFFSET                   0x0
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_DONT_SPLIT_AHB_WR_DEFAULT                   _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_DONT_SPLIT_AHB_WR_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_DONT_SPLIT_AHB_WR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_DONT_SPLIT_AHB_WR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_DONT_SPLIT_AHB_WR_ENABLE                    _MK_ENUM_CONST(0)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_DONT_SPLIT_AHB_WR_DISABLE                   _MK_ENUM_CONST(1)
+
+// AHB slave gizmo - Accept AHB write request always.  1 = always accept AHB write 
+// request without checking whether there is room in the queue to store the write 
+// data. 0 = accept AHB write request only when theres  enough room in the queue 
+// to store all the write data.
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_ACCEPT_AHB_WR_ALWAYS_SHIFT                  _MK_SHIFT_CONST(6)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_ACCEPT_AHB_WR_ALWAYS_FIELD                  (_MK_MASK_CONST(0x1) << AHB_GIZMO_AHB_XBAR_BRIDGE_0_ACCEPT_AHB_WR_ALWAYS_SHIFT)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_ACCEPT_AHB_WR_ALWAYS_RANGE                  6:6
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_ACCEPT_AHB_WR_ALWAYS_WOFFSET                        0x0
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_ACCEPT_AHB_WR_ALWAYS_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_ACCEPT_AHB_WR_ALWAYS_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_ACCEPT_AHB_WR_ALWAYS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_ACCEPT_AHB_WR_ALWAYS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_ACCEPT_AHB_WR_ALWAYS_ACCEPT_ON_CHECK                        _MK_ENUM_CONST(0)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_ACCEPT_AHB_WR_ALWAYS_ACCEPT_ON_NOCHECK                      _MK_ENUM_CONST(1)
+
+// AHB slave gizmo - Maximum allowed IP burst 
+// size.  
+// 00 = single transfer.  
+// 01 = burst-of-4.  
+// 10 = burst-of-8.  
+// 11 = burst-of-16.
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_MAX_IP_BURSTSIZE_SHIFT                      _MK_SHIFT_CONST(4)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_MAX_IP_BURSTSIZE_FIELD                      (_MK_MASK_CONST(0x3) << AHB_GIZMO_AHB_XBAR_BRIDGE_0_MAX_IP_BURSTSIZE_SHIFT)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_MAX_IP_BURSTSIZE_RANGE                      5:4
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_MAX_IP_BURSTSIZE_WOFFSET                    0x0
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_MAX_IP_BURSTSIZE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_MAX_IP_BURSTSIZE_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_MAX_IP_BURSTSIZE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_MAX_IP_BURSTSIZE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_MAX_IP_BURSTSIZE_DMA_BURST_1WORDS                   _MK_ENUM_CONST(0)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_MAX_IP_BURSTSIZE_DMA_BURST_4WORDS                   _MK_ENUM_CONST(1)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_MAX_IP_BURSTSIZE_DMA_BURST_8WORDS                   _MK_ENUM_CONST(2)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_MAX_IP_BURSTSIZE_DMA_BURST_16WORDS                  _MK_ENUM_CONST(3)
+
+// AHB slave gizmo - Start write request to device immediately.  1 = start write request on the 
+// device side as soon as the AHB master puts data into the gizmos queue.  0 = start the device 
+// write request only when the  AHB master has placed all write data into the gizmos queue.
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_IMMEDIATE_SHIFT                     _MK_SHIFT_CONST(3)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_IMMEDIATE_FIELD                     (_MK_MASK_CONST(0x1) << AHB_GIZMO_AHB_XBAR_BRIDGE_0_IMMEDIATE_SHIFT)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_IMMEDIATE_RANGE                     3:3
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_IMMEDIATE_WOFFSET                   0x0
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_IMMEDIATE_DEFAULT                   _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_IMMEDIATE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_IMMEDIATE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_IMMEDIATE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_IMMEDIATE_DISABLE                   _MK_ENUM_CONST(0)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_IMMEDIATE_ENABLE                    _MK_ENUM_CONST(1)
+
+// AHB slave gizmo - Enable fast re-arbitration.  1 = allow AHB master re-arbitration as soon as 
+// the device returns one read data into the gizmos queue.  0 = allow AHB master re-arbitration 
+// only when the  device returns all read data into the gizmos queue.
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_ENB_FAST_REARBITRATE_SHIFT                  _MK_SHIFT_CONST(2)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_ENB_FAST_REARBITRATE_FIELD                  (_MK_MASK_CONST(0x1) << AHB_GIZMO_AHB_XBAR_BRIDGE_0_ENB_FAST_REARBITRATE_SHIFT)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_ENB_FAST_REARBITRATE_RANGE                  2:2
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_ENB_FAST_REARBITRATE_WOFFSET                        0x0
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_ENB_FAST_REARBITRATE_DEFAULT                        _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_ENB_FAST_REARBITRATE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_ENB_FAST_REARBITRATE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_ENB_FAST_REARBITRATE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_ENB_FAST_REARBITRATE_DISABLE                        _MK_ENUM_CONST(0)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_ENB_FAST_REARBITRATE_ENABLE                 _MK_ENUM_CONST(1)
+
+// AHB slave gizmo - Force all AHB transaction to single data request transaction.  
+// 1 = force to single data transaction always.  
+// 0 = dont force to single data  transaction.
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_FORCE_TO_AHB_SINGLE_SHIFT                   _MK_SHIFT_CONST(1)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_FORCE_TO_AHB_SINGLE_FIELD                   (_MK_MASK_CONST(0x1) << AHB_GIZMO_AHB_XBAR_BRIDGE_0_FORCE_TO_AHB_SINGLE_SHIFT)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_FORCE_TO_AHB_SINGLE_RANGE                   1:1
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_FORCE_TO_AHB_SINGLE_WOFFSET                 0x0
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_FORCE_TO_AHB_SINGLE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_FORCE_TO_AHB_SINGLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_FORCE_TO_AHB_SINGLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_FORCE_TO_AHB_SINGLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_FORCE_TO_AHB_SINGLE_NOT_SINGLE_DATA                 _MK_ENUM_CONST(0)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_FORCE_TO_AHB_SINGLE_SINGLE_DATA                     _MK_ENUM_CONST(1)
+
+// AHB slave gizmo - Enable splitting AHB transactions.  1 = enable 0 = disable
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_ENABLE_SPLIT_SHIFT                  _MK_SHIFT_CONST(0)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_ENABLE_SPLIT_FIELD                  (_MK_MASK_CONST(0x1) << AHB_GIZMO_AHB_XBAR_BRIDGE_0_ENABLE_SPLIT_SHIFT)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_ENABLE_SPLIT_RANGE                  0:0
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_ENABLE_SPLIT_WOFFSET                        0x0
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_ENABLE_SPLIT_DEFAULT                        _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_ENABLE_SPLIT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_ENABLE_SPLIT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_ENABLE_SPLIT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_ENABLE_SPLIT_DISABLE                        _MK_ENUM_CONST(0)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_ENABLE_SPLIT_ENABLE                 _MK_ENUM_CONST(1)
+
+
+// Register AHB_GIZMO_CPU_AHB_BRIDGE_0  
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0                      _MK_ADDR_CONST(0x24)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_SECURE                       0x0
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_WORD_COUNT                   0x1
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_RESET_VAL                    _MK_MASK_CONST(0x60000)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_RESET_MASK                   _MK_MASK_CONST(0xff0f0000)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_READ_MASK                    _MK_MASK_CONST(0xff0f0000)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_WRITE_MASK                   _MK_MASK_CONST(0xff0f0000)
+// AHB master request negate count. This is an 8-bit  counter use to indicate the minimum number of clk count between requests from  this AHB master.
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_REQ_NEG_CNT_SHIFT                    _MK_SHIFT_CONST(24)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_REQ_NEG_CNT_FIELD                    (_MK_MASK_CONST(0xff) << AHB_GIZMO_CPU_AHB_BRIDGE_0_REQ_NEG_CNT_SHIFT)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_REQ_NEG_CNT_RANGE                    31:24
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_REQ_NEG_CNT_WOFFSET                  0x0
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_REQ_NEG_CNT_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_REQ_NEG_CNT_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_REQ_NEG_CNT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_REQ_NEG_CNT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// AHB master gizmo - Pack all AHB read data.  1 = wait for all requested read data to be in the 
+// AHB gizmos queue before returning the data back to the IP.  0 = transfer each read data from 
+// the AHB to the IP  immediately.
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_RD_DATA_SHIFT                        _MK_SHIFT_CONST(19)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_RD_DATA_FIELD                        (_MK_MASK_CONST(0x1) << AHB_GIZMO_CPU_AHB_BRIDGE_0_RD_DATA_SHIFT)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_RD_DATA_RANGE                        19:19
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_RD_DATA_WOFFSET                      0x0
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_RD_DATA_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_RD_DATA_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_RD_DATA_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_RD_DATA_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_RD_DATA_NO_WAIT                      _MK_ENUM_CONST(0)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_RD_DATA_WAIT                 _MK_ENUM_CONST(1)
+
+// AHB master gizmo (AHB-DMA) - Start AHB write request immediately.  1 = start the AHB write 
+// request immediately as soon as the device  has put one write data in the AHB gizmos queue.  
+// 0 = start the AHB write request only when all the  write data has transferred from the 
+// device to the AHB gizmos queue.
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_IMMEDIATE_SHIFT                      _MK_SHIFT_CONST(18)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_IMMEDIATE_FIELD                      (_MK_MASK_CONST(0x1) << AHB_GIZMO_CPU_AHB_BRIDGE_0_IMMEDIATE_SHIFT)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_IMMEDIATE_RANGE                      18:18
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_IMMEDIATE_WOFFSET                    0x0
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_IMMEDIATE_DEFAULT                    _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_IMMEDIATE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_IMMEDIATE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_IMMEDIATE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_IMMEDIATE_DISABLE                    _MK_ENUM_CONST(0)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_IMMEDIATE_ENABLE                     _MK_ENUM_CONST(1)
+
+// AHB master gizmo - Maximum allowed AHB 
+// burst size.  
+// 00 = single transfer.  
+// 01 = burst-of-4.  
+// 10 = burst-of-8.  
+// 11 = burst-of-16.
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_SHIFT                      _MK_SHIFT_CONST(16)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_FIELD                      (_MK_MASK_CONST(0x3) << AHB_GIZMO_CPU_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_SHIFT)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_RANGE                      17:16
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_WOFFSET                    0x0
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_DEFAULT                    _MK_MASK_CONST(0x2)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_DMA_BURST_1WORDS                   _MK_ENUM_CONST(0)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_DMA_BURST_4WORDS                   _MK_ENUM_CONST(1)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_DMA_BURST_8WORDS                   _MK_ENUM_CONST(2)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_DMA_BURST_16WORDS                  _MK_ENUM_CONST(3)
+
+
+// Register AHB_GIZMO_COP_AHB_BRIDGE_0  
+#define AHB_GIZMO_COP_AHB_BRIDGE_0                      _MK_ADDR_CONST(0x28)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_SECURE                       0x0
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_WORD_COUNT                   0x1
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_RESET_VAL                    _MK_MASK_CONST(0x60000)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_RESET_MASK                   _MK_MASK_CONST(0xff0f0000)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_READ_MASK                    _MK_MASK_CONST(0xff0f0000)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_WRITE_MASK                   _MK_MASK_CONST(0xff0f0000)
+// AHB master request negate count. This is an 8-bit  counter use to indicate the minimum number of clk count between requests from  this AHB master.
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_REQ_NEG_CNT_SHIFT                    _MK_SHIFT_CONST(24)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_REQ_NEG_CNT_FIELD                    (_MK_MASK_CONST(0xff) << AHB_GIZMO_COP_AHB_BRIDGE_0_REQ_NEG_CNT_SHIFT)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_REQ_NEG_CNT_RANGE                    31:24
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_REQ_NEG_CNT_WOFFSET                  0x0
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_REQ_NEG_CNT_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_REQ_NEG_CNT_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_REQ_NEG_CNT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_REQ_NEG_CNT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// AHB master gizmo - Pack all AHB read data.  1 = wait for all requested read data to be in the 
+// AHB gizmos queue before returning the data back to the IP.  0 = transfer each read data from 
+// the AHB to the IP  immediately.
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_RD_DATA_SHIFT                        _MK_SHIFT_CONST(19)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_RD_DATA_FIELD                        (_MK_MASK_CONST(0x1) << AHB_GIZMO_COP_AHB_BRIDGE_0_RD_DATA_SHIFT)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_RD_DATA_RANGE                        19:19
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_RD_DATA_WOFFSET                      0x0
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_RD_DATA_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_RD_DATA_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_RD_DATA_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_RD_DATA_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_RD_DATA_NO_WAIT                      _MK_ENUM_CONST(0)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_RD_DATA_WAIT                 _MK_ENUM_CONST(1)
+
+// AHB master gizmo (AHB-DMA) - Start AHB write request immediately.  1 = start the AHB write 
+// request immediately as soon as the device  has put one write data in the AHB gizmos queue.  
+// 0 = start the AHB write request only when all the  write data has transferred from the 
+// device to the AHB gizmos queue.
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_IMMEDIATE_SHIFT                      _MK_SHIFT_CONST(18)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_IMMEDIATE_FIELD                      (_MK_MASK_CONST(0x1) << AHB_GIZMO_COP_AHB_BRIDGE_0_IMMEDIATE_SHIFT)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_IMMEDIATE_RANGE                      18:18
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_IMMEDIATE_WOFFSET                    0x0
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_IMMEDIATE_DEFAULT                    _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_IMMEDIATE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_IMMEDIATE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_IMMEDIATE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_IMMEDIATE_DISABLE                    _MK_ENUM_CONST(0)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_IMMEDIATE_ENABLE                     _MK_ENUM_CONST(1)
+
+// AHB master gizmo - Maximum allowed AHB 
+// burst size.  
+// 00 = single transfer.  
+// 01 = burst-of-4.  
+// 10 = burst-of-8.  
+// 11 = burst-of-16.
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_SHIFT                      _MK_SHIFT_CONST(16)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_FIELD                      (_MK_MASK_CONST(0x3) << AHB_GIZMO_COP_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_SHIFT)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_RANGE                      17:16
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_WOFFSET                    0x0
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_DEFAULT                    _MK_MASK_CONST(0x2)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_DMA_BURST_1WORDS                   _MK_ENUM_CONST(0)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_DMA_BURST_4WORDS                   _MK_ENUM_CONST(1)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_DMA_BURST_8WORDS                   _MK_ENUM_CONST(2)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_DMA_BURST_16WORDS                  _MK_ENUM_CONST(3)
+
+
+// Register AHB_GIZMO_XBAR_APB_CTLR_0  
+#define AHB_GIZMO_XBAR_APB_CTLR_0                       _MK_ADDR_CONST(0x2c)
+#define AHB_GIZMO_XBAR_APB_CTLR_0_SECURE                        0x0
+#define AHB_GIZMO_XBAR_APB_CTLR_0_WORD_COUNT                    0x1
+#define AHB_GIZMO_XBAR_APB_CTLR_0_RESET_VAL                     _MK_MASK_CONST(0x8)
+#define AHB_GIZMO_XBAR_APB_CTLR_0_RESET_MASK                    _MK_MASK_CONST(0x38)
+#define AHB_GIZMO_XBAR_APB_CTLR_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_XBAR_APB_CTLR_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_XBAR_APB_CTLR_0_READ_MASK                     _MK_MASK_CONST(0x38)
+#define AHB_GIZMO_XBAR_APB_CTLR_0_WRITE_MASK                    _MK_MASK_CONST(0x38)
+// AHB slave gizmo - Maximum allowed IP 
+// burst size.  
+// 00 = single transfer.  
+// 01 = burst-of-4.  
+// 10 = burst-of-8.  
+// 11 = burst-of-16.
+#define AHB_GIZMO_XBAR_APB_CTLR_0_MAX_IP_BURSTSIZE_SHIFT                        _MK_SHIFT_CONST(4)
+#define AHB_GIZMO_XBAR_APB_CTLR_0_MAX_IP_BURSTSIZE_FIELD                        (_MK_MASK_CONST(0x3) << AHB_GIZMO_XBAR_APB_CTLR_0_MAX_IP_BURSTSIZE_SHIFT)
+#define AHB_GIZMO_XBAR_APB_CTLR_0_MAX_IP_BURSTSIZE_RANGE                        5:4
+#define AHB_GIZMO_XBAR_APB_CTLR_0_MAX_IP_BURSTSIZE_WOFFSET                      0x0
+#define AHB_GIZMO_XBAR_APB_CTLR_0_MAX_IP_BURSTSIZE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_XBAR_APB_CTLR_0_MAX_IP_BURSTSIZE_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define AHB_GIZMO_XBAR_APB_CTLR_0_MAX_IP_BURSTSIZE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_XBAR_APB_CTLR_0_MAX_IP_BURSTSIZE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_XBAR_APB_CTLR_0_MAX_IP_BURSTSIZE_DMA_BURST_1WORDS                     _MK_ENUM_CONST(0)
+#define AHB_GIZMO_XBAR_APB_CTLR_0_MAX_IP_BURSTSIZE_DMA_BURST_4WORDS                     _MK_ENUM_CONST(1)
+#define AHB_GIZMO_XBAR_APB_CTLR_0_MAX_IP_BURSTSIZE_DMA_BURST_8WORDS                     _MK_ENUM_CONST(2)
+#define AHB_GIZMO_XBAR_APB_CTLR_0_MAX_IP_BURSTSIZE_DMA_BURST_16WORDS                    _MK_ENUM_CONST(3)
+
+// AHB slave gizmo - Start write request to device immediately.  1 = start write request on 
+// the device side as soon as the AHB master puts data into the gizmos queue.  0 = start 
+// the device write request only when the  AHB master has placed all write data into the 
+// gizmos queue.
+#define AHB_GIZMO_XBAR_APB_CTLR_0_IMMEDIATE_SHIFT                       _MK_SHIFT_CONST(3)
+#define AHB_GIZMO_XBAR_APB_CTLR_0_IMMEDIATE_FIELD                       (_MK_MASK_CONST(0x1) << AHB_GIZMO_XBAR_APB_CTLR_0_IMMEDIATE_SHIFT)
+#define AHB_GIZMO_XBAR_APB_CTLR_0_IMMEDIATE_RANGE                       3:3
+#define AHB_GIZMO_XBAR_APB_CTLR_0_IMMEDIATE_WOFFSET                     0x0
+#define AHB_GIZMO_XBAR_APB_CTLR_0_IMMEDIATE_DEFAULT                     _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_XBAR_APB_CTLR_0_IMMEDIATE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_XBAR_APB_CTLR_0_IMMEDIATE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_XBAR_APB_CTLR_0_IMMEDIATE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_XBAR_APB_CTLR_0_IMMEDIATE_DISABLE                     _MK_ENUM_CONST(0)
+#define AHB_GIZMO_XBAR_APB_CTLR_0_IMMEDIATE_ENABLE                      _MK_ENUM_CONST(1)
+
+
+// Register AHB_GIZMO_VCP_AHB_BRIDGE_0  
+#define AHB_GIZMO_VCP_AHB_BRIDGE_0                      _MK_ADDR_CONST(0x30)
+#define AHB_GIZMO_VCP_AHB_BRIDGE_0_SECURE                       0x0
+#define AHB_GIZMO_VCP_AHB_BRIDGE_0_WORD_COUNT                   0x1
+#define AHB_GIZMO_VCP_AHB_BRIDGE_0_RESET_VAL                    _MK_MASK_CONST(0x60000)
+#define AHB_GIZMO_VCP_AHB_BRIDGE_0_RESET_MASK                   _MK_MASK_CONST(0xff0f0000)
+#define AHB_GIZMO_VCP_AHB_BRIDGE_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_VCP_AHB_BRIDGE_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_VCP_AHB_BRIDGE_0_READ_MASK                    _MK_MASK_CONST(0xff0f0000)
+#define AHB_GIZMO_VCP_AHB_BRIDGE_0_WRITE_MASK                   _MK_MASK_CONST(0xff0f0000)
+// AHB master request negate count. This is an 8-bit  counter use to indicate the minimum number of clk count between requests from  this AHB master.
+#define AHB_GIZMO_VCP_AHB_BRIDGE_0_REQ_NEG_CNT_SHIFT                    _MK_SHIFT_CONST(24)
+#define AHB_GIZMO_VCP_AHB_BRIDGE_0_REQ_NEG_CNT_FIELD                    (_MK_MASK_CONST(0xff) << AHB_GIZMO_VCP_AHB_BRIDGE_0_REQ_NEG_CNT_SHIFT)
+#define AHB_GIZMO_VCP_AHB_BRIDGE_0_REQ_NEG_CNT_RANGE                    31:24
+#define AHB_GIZMO_VCP_AHB_BRIDGE_0_REQ_NEG_CNT_WOFFSET                  0x0
+#define AHB_GIZMO_VCP_AHB_BRIDGE_0_REQ_NEG_CNT_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_VCP_AHB_BRIDGE_0_REQ_NEG_CNT_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
+#define AHB_GIZMO_VCP_AHB_BRIDGE_0_REQ_NEG_CNT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_VCP_AHB_BRIDGE_0_REQ_NEG_CNT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+//AHB master gizmo - Pack all AHB read data.  1 = wait for all requested read data to be in the AHB gizmos queue before returning the data back to the IP.  0 = transfer each read data from the AHB to the IP  immediately.
+#define AHB_GIZMO_VCP_AHB_BRIDGE_0_RD_DATA_SHIFT                        _MK_SHIFT_CONST(19)
+#define AHB_GIZMO_VCP_AHB_BRIDGE_0_RD_DATA_FIELD                        (_MK_MASK_CONST(0x1) << AHB_GIZMO_VCP_AHB_BRIDGE_0_RD_DATA_SHIFT)
+#define AHB_GIZMO_VCP_AHB_BRIDGE_0_RD_DATA_RANGE                        19:19
+#define AHB_GIZMO_VCP_AHB_BRIDGE_0_RD_DATA_WOFFSET                      0x0
+#define AHB_GIZMO_VCP_AHB_BRIDGE_0_RD_DATA_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_VCP_AHB_BRIDGE_0_RD_DATA_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_VCP_AHB_BRIDGE_0_RD_DATA_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_VCP_AHB_BRIDGE_0_RD_DATA_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_VCP_AHB_BRIDGE_0_RD_DATA_NO_WAIT                      _MK_ENUM_CONST(0)
+#define AHB_GIZMO_VCP_AHB_BRIDGE_0_RD_DATA_WAIT                 _MK_ENUM_CONST(1)
+
+//AHB master gizmo (AHB-DMA) - Start AHB write request immediately.  1 = start the AHB write request immediately as soon as the device  has put one write data in the AHB gizmos queue.  0 = start the AHB write request only when all the  write data has transferred from the device to the AHB gizmos queue.
+#define AHB_GIZMO_VCP_AHB_BRIDGE_0_IMMEDIATE_SHIFT                      _MK_SHIFT_CONST(18)
+#define AHB_GIZMO_VCP_AHB_BRIDGE_0_IMMEDIATE_FIELD                      (_MK_MASK_CONST(0x1) << AHB_GIZMO_VCP_AHB_BRIDGE_0_IMMEDIATE_SHIFT)
+#define AHB_GIZMO_VCP_AHB_BRIDGE_0_IMMEDIATE_RANGE                      18:18
+#define AHB_GIZMO_VCP_AHB_BRIDGE_0_IMMEDIATE_WOFFSET                    0x0
+#define AHB_GIZMO_VCP_AHB_BRIDGE_0_IMMEDIATE_DEFAULT                    _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_VCP_AHB_BRIDGE_0_IMMEDIATE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_VCP_AHB_BRIDGE_0_IMMEDIATE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_VCP_AHB_BRIDGE_0_IMMEDIATE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_VCP_AHB_BRIDGE_0_IMMEDIATE_DISABLE                    _MK_ENUM_CONST(0)
+#define AHB_GIZMO_VCP_AHB_BRIDGE_0_IMMEDIATE_ENABLE                     _MK_ENUM_CONST(1)
+
+//AHB master gizmo - Maximum allowed AHB burst size.  00 = single transfer.  01 = burst-of-4.  10 = burst-of-8.  11 = burst-of-16.
+#define AHB_GIZMO_VCP_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_SHIFT                      _MK_SHIFT_CONST(16)
+#define AHB_GIZMO_VCP_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_FIELD                      (_MK_MASK_CONST(0x3) << AHB_GIZMO_VCP_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_SHIFT)
+#define AHB_GIZMO_VCP_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_RANGE                      17:16
+#define AHB_GIZMO_VCP_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_WOFFSET                    0x0
+#define AHB_GIZMO_VCP_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_DEFAULT                    _MK_MASK_CONST(0x2)
+#define AHB_GIZMO_VCP_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define AHB_GIZMO_VCP_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_VCP_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_VCP_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_DMA_BURST_1WORDS                   _MK_ENUM_CONST(0)
+#define AHB_GIZMO_VCP_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_DMA_BURST_4WORDS                   _MK_ENUM_CONST(1)
+#define AHB_GIZMO_VCP_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_DMA_BURST_8WORDS                   _MK_ENUM_CONST(2)
+#define AHB_GIZMO_VCP_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_DMA_BURST_16WORDS                  _MK_ENUM_CONST(3)
+
+
+// Reserved address 52 [0x34] 
+
+// Reserved address 56 [0x38] 
+
+// Register AHB_GIZMO_NAND_0  
+#define AHB_GIZMO_NAND_0                        _MK_ADDR_CONST(0x3c)
+#define AHB_GIZMO_NAND_0_SECURE                         0x0
+#define AHB_GIZMO_NAND_0_WORD_COUNT                     0x1
+#define AHB_GIZMO_NAND_0_RESET_VAL                      _MK_MASK_CONST(0xa0000)
+#define AHB_GIZMO_NAND_0_RESET_MASK                     _MK_MASK_CONST(0xff0f0000)
+#define AHB_GIZMO_NAND_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_NAND_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_NAND_0_READ_MASK                      _MK_MASK_CONST(0xff0f0000)
+#define AHB_GIZMO_NAND_0_WRITE_MASK                     _MK_MASK_CONST(0xff0f0000)
+// AHB master request negate count. This is an 8-bit  counter use to indicate the minimum number of clk count 
+// between requests from  this AHB master.
+#define AHB_GIZMO_NAND_0_REQ_NEG_CNT_SHIFT                      _MK_SHIFT_CONST(24)
+#define AHB_GIZMO_NAND_0_REQ_NEG_CNT_FIELD                      (_MK_MASK_CONST(0xff) << AHB_GIZMO_NAND_0_REQ_NEG_CNT_SHIFT)
+#define AHB_GIZMO_NAND_0_REQ_NEG_CNT_RANGE                      31:24
+#define AHB_GIZMO_NAND_0_REQ_NEG_CNT_WOFFSET                    0x0
+#define AHB_GIZMO_NAND_0_REQ_NEG_CNT_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_NAND_0_REQ_NEG_CNT_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
+#define AHB_GIZMO_NAND_0_REQ_NEG_CNT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_NAND_0_REQ_NEG_CNT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// AHB master gizmo - Pack all AHB read data.  1 = wait for all requested read data to be 
+// in the AHB gizmos queue before returning the data back to the IP.  0 = transfer each read 
+// data from the AHB to the IP  immediately.
+#define AHB_GIZMO_NAND_0_RD_DATA_SHIFT                  _MK_SHIFT_CONST(19)
+#define AHB_GIZMO_NAND_0_RD_DATA_FIELD                  (_MK_MASK_CONST(0x1) << AHB_GIZMO_NAND_0_RD_DATA_SHIFT)
+#define AHB_GIZMO_NAND_0_RD_DATA_RANGE                  19:19
+#define AHB_GIZMO_NAND_0_RD_DATA_WOFFSET                        0x0
+#define AHB_GIZMO_NAND_0_RD_DATA_DEFAULT                        _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_NAND_0_RD_DATA_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_NAND_0_RD_DATA_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_NAND_0_RD_DATA_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_NAND_0_RD_DATA_NO_WAIT                        _MK_ENUM_CONST(0)
+#define AHB_GIZMO_NAND_0_RD_DATA_WAIT                   _MK_ENUM_CONST(1)
+
+// AHB master gizmo (AHB-DMA) - Start AHB write request immediately.  1 = start the AHB 
+// write request immediately as soon as the device  has put one write data in the AHB 
+// gizmos queue.  0 = start the AHB write request only when all the  write data has 
+// transferred from the device to the AHB gizmos queue.
+#define AHB_GIZMO_NAND_0_IMMEDIATE_SHIFT                        _MK_SHIFT_CONST(18)
+#define AHB_GIZMO_NAND_0_IMMEDIATE_FIELD                        (_MK_MASK_CONST(0x1) << AHB_GIZMO_NAND_0_IMMEDIATE_SHIFT)
+#define AHB_GIZMO_NAND_0_IMMEDIATE_RANGE                        18:18
+#define AHB_GIZMO_NAND_0_IMMEDIATE_WOFFSET                      0x0
+#define AHB_GIZMO_NAND_0_IMMEDIATE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_NAND_0_IMMEDIATE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_NAND_0_IMMEDIATE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_NAND_0_IMMEDIATE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_NAND_0_IMMEDIATE_DISABLE                      _MK_ENUM_CONST(0)
+#define AHB_GIZMO_NAND_0_IMMEDIATE_ENABLE                       _MK_ENUM_CONST(1)
+
+// AHB master gizmo - Maximum allowed 
+// AHB burst size.  
+// 00 = single transfer.  
+// 01 = burst-of-4.  
+// 10 = burst-of-8.  
+// 11 = burst-of-16.
+#define AHB_GIZMO_NAND_0_MAX_AHB_BURSTSIZE_SHIFT                        _MK_SHIFT_CONST(16)
+#define AHB_GIZMO_NAND_0_MAX_AHB_BURSTSIZE_FIELD                        (_MK_MASK_CONST(0x3) << AHB_GIZMO_NAND_0_MAX_AHB_BURSTSIZE_SHIFT)
+#define AHB_GIZMO_NAND_0_MAX_AHB_BURSTSIZE_RANGE                        17:16
+#define AHB_GIZMO_NAND_0_MAX_AHB_BURSTSIZE_WOFFSET                      0x0
+#define AHB_GIZMO_NAND_0_MAX_AHB_BURSTSIZE_DEFAULT                      _MK_MASK_CONST(0x2)
+#define AHB_GIZMO_NAND_0_MAX_AHB_BURSTSIZE_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define AHB_GIZMO_NAND_0_MAX_AHB_BURSTSIZE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_NAND_0_MAX_AHB_BURSTSIZE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_NAND_0_MAX_AHB_BURSTSIZE_DMA_BURST_1WORDS                     _MK_ENUM_CONST(0)
+#define AHB_GIZMO_NAND_0_MAX_AHB_BURSTSIZE_DMA_BURST_4WORDS                     _MK_ENUM_CONST(1)
+#define AHB_GIZMO_NAND_0_MAX_AHB_BURSTSIZE_DMA_BURST_8WORDS                     _MK_ENUM_CONST(2)
+#define AHB_GIZMO_NAND_0_MAX_AHB_BURSTSIZE_DMA_BURST_16WORDS                    _MK_ENUM_CONST(3)
+
+
+// Reserved address 64 [0x40] 
+
+// Register AHB_GIZMO_SDMMC4_0  
+#define AHB_GIZMO_SDMMC4_0                      _MK_ADDR_CONST(0x44)
+#define AHB_GIZMO_SDMMC4_0_SECURE                       0x0
+#define AHB_GIZMO_SDMMC4_0_WORD_COUNT                   0x1
+#define AHB_GIZMO_SDMMC4_0_RESET_VAL                    _MK_MASK_CONST(0x20087)
+#define AHB_GIZMO_SDMMC4_0_RESET_MASK                   _MK_MASK_CONST(0xff0700c7)
+#define AHB_GIZMO_SDMMC4_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC4_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC4_0_READ_MASK                    _MK_MASK_CONST(0xff0700c7)
+#define AHB_GIZMO_SDMMC4_0_WRITE_MASK                   _MK_MASK_CONST(0xff0700c7)
+// AHB master request negate count. This is an 8-bit  counter use to indicate the minimum number of clk count between requests from  this AHB master.
+#define AHB_GIZMO_SDMMC4_0_REQ_NEG_CNT_SHIFT                    _MK_SHIFT_CONST(24)
+#define AHB_GIZMO_SDMMC4_0_REQ_NEG_CNT_FIELD                    (_MK_MASK_CONST(0xff) << AHB_GIZMO_SDMMC4_0_REQ_NEG_CNT_SHIFT)
+#define AHB_GIZMO_SDMMC4_0_REQ_NEG_CNT_RANGE                    31:24
+#define AHB_GIZMO_SDMMC4_0_REQ_NEG_CNT_WOFFSET                  0x0
+#define AHB_GIZMO_SDMMC4_0_REQ_NEG_CNT_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC4_0_REQ_NEG_CNT_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
+#define AHB_GIZMO_SDMMC4_0_REQ_NEG_CNT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC4_0_REQ_NEG_CNT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+//AHB master gizmo - Start AHB write request immediately.  1 = start the AHB write request immediately as soon as the device puts data in the AHB gizmos queue.  0 = start the AHB write request only when all the  write data has transferred from the device to the AHB gizmos queue.
+#define AHB_GIZMO_SDMMC4_0_IMMEDIATE_SHIFT                      _MK_SHIFT_CONST(18)
+#define AHB_GIZMO_SDMMC4_0_IMMEDIATE_FIELD                      (_MK_MASK_CONST(0x1) << AHB_GIZMO_SDMMC4_0_IMMEDIATE_SHIFT)
+#define AHB_GIZMO_SDMMC4_0_IMMEDIATE_RANGE                      18:18
+#define AHB_GIZMO_SDMMC4_0_IMMEDIATE_WOFFSET                    0x0
+#define AHB_GIZMO_SDMMC4_0_IMMEDIATE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC4_0_IMMEDIATE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_SDMMC4_0_IMMEDIATE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC4_0_IMMEDIATE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC4_0_IMMEDIATE_DISABLE                    _MK_ENUM_CONST(0)
+#define AHB_GIZMO_SDMMC4_0_IMMEDIATE_ENABLE                     _MK_ENUM_CONST(1)
+
+//AHB master gizmo - Maximum allowed AHB burst size.  00 = single transfer.  01 = burst-of-4.  10 = burst-of-8.  11 = burst-of-16.
+#define AHB_GIZMO_SDMMC4_0_MAX_AHB_BURSTSIZE_SHIFT                      _MK_SHIFT_CONST(16)
+#define AHB_GIZMO_SDMMC4_0_MAX_AHB_BURSTSIZE_FIELD                      (_MK_MASK_CONST(0x3) << AHB_GIZMO_SDMMC4_0_MAX_AHB_BURSTSIZE_SHIFT)
+#define AHB_GIZMO_SDMMC4_0_MAX_AHB_BURSTSIZE_RANGE                      17:16
+#define AHB_GIZMO_SDMMC4_0_MAX_AHB_BURSTSIZE_WOFFSET                    0x0
+#define AHB_GIZMO_SDMMC4_0_MAX_AHB_BURSTSIZE_DEFAULT                    _MK_MASK_CONST(0x2)
+#define AHB_GIZMO_SDMMC4_0_MAX_AHB_BURSTSIZE_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define AHB_GIZMO_SDMMC4_0_MAX_AHB_BURSTSIZE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC4_0_MAX_AHB_BURSTSIZE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC4_0_MAX_AHB_BURSTSIZE_DMA_BURST_1WORDS                   _MK_ENUM_CONST(0)
+#define AHB_GIZMO_SDMMC4_0_MAX_AHB_BURSTSIZE_DMA_BURST_4WORDS                   _MK_ENUM_CONST(1)
+#define AHB_GIZMO_SDMMC4_0_MAX_AHB_BURSTSIZE_DMA_BURST_8WORDS                   _MK_ENUM_CONST(2)
+#define AHB_GIZMO_SDMMC4_0_MAX_AHB_BURSTSIZE_DMA_BURST_16WORDS                  _MK_ENUM_CONST(3)
+
+//AHB slave gizmo - Dont split AHB write transaction.  1 = dont split AHB write transaction ever. 0 (and enable_split=1) = allow AHB write  transaction to be split.
+#define AHB_GIZMO_SDMMC4_0_DONT_SPLIT_AHB_WR_SHIFT                      _MK_SHIFT_CONST(7)
+#define AHB_GIZMO_SDMMC4_0_DONT_SPLIT_AHB_WR_FIELD                      (_MK_MASK_CONST(0x1) << AHB_GIZMO_SDMMC4_0_DONT_SPLIT_AHB_WR_SHIFT)
+#define AHB_GIZMO_SDMMC4_0_DONT_SPLIT_AHB_WR_RANGE                      7:7
+#define AHB_GIZMO_SDMMC4_0_DONT_SPLIT_AHB_WR_WOFFSET                    0x0
+#define AHB_GIZMO_SDMMC4_0_DONT_SPLIT_AHB_WR_DEFAULT                    _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_SDMMC4_0_DONT_SPLIT_AHB_WR_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_SDMMC4_0_DONT_SPLIT_AHB_WR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC4_0_DONT_SPLIT_AHB_WR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC4_0_DONT_SPLIT_AHB_WR_ENABLE                     _MK_ENUM_CONST(0)
+#define AHB_GIZMO_SDMMC4_0_DONT_SPLIT_AHB_WR_DISABLE                    _MK_ENUM_CONST(1)
+
+//AHB slave gizmo - Accept AHB write request always.  1 = always accept AHB write request without checking whether there is room in the queue to store the write data. 0 = accept AHB write request only when theres  enough room in the queue to store all the write data.
+#define AHB_GIZMO_SDMMC4_0_ACCEPT_AHB_WR_ALWAYS_SHIFT                   _MK_SHIFT_CONST(6)
+#define AHB_GIZMO_SDMMC4_0_ACCEPT_AHB_WR_ALWAYS_FIELD                   (_MK_MASK_CONST(0x1) << AHB_GIZMO_SDMMC4_0_ACCEPT_AHB_WR_ALWAYS_SHIFT)
+#define AHB_GIZMO_SDMMC4_0_ACCEPT_AHB_WR_ALWAYS_RANGE                   6:6
+#define AHB_GIZMO_SDMMC4_0_ACCEPT_AHB_WR_ALWAYS_WOFFSET                 0x0
+#define AHB_GIZMO_SDMMC4_0_ACCEPT_AHB_WR_ALWAYS_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC4_0_ACCEPT_AHB_WR_ALWAYS_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_SDMMC4_0_ACCEPT_AHB_WR_ALWAYS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC4_0_ACCEPT_AHB_WR_ALWAYS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC4_0_ACCEPT_AHB_WR_ALWAYS_ACCEPT_ON_CHECK                 _MK_ENUM_CONST(0)
+#define AHB_GIZMO_SDMMC4_0_ACCEPT_AHB_WR_ALWAYS_ACCEPT_ON_NOCHECK                       _MK_ENUM_CONST(1)
+
+//AHB slave gizmo - Enable fast re-arbitration.  1 = allow AHB master re-arbitration as soon as the device returns one read data into the gizmos queue. 0 = allow AHB master re-arbitration only when the  device returns all read data into the gizmos queue.
+#define AHB_GIZMO_SDMMC4_0_ENB_FAST_REARBITRATE_SHIFT                   _MK_SHIFT_CONST(2)
+#define AHB_GIZMO_SDMMC4_0_ENB_FAST_REARBITRATE_FIELD                   (_MK_MASK_CONST(0x1) << AHB_GIZMO_SDMMC4_0_ENB_FAST_REARBITRATE_SHIFT)
+#define AHB_GIZMO_SDMMC4_0_ENB_FAST_REARBITRATE_RANGE                   2:2
+#define AHB_GIZMO_SDMMC4_0_ENB_FAST_REARBITRATE_WOFFSET                 0x0
+#define AHB_GIZMO_SDMMC4_0_ENB_FAST_REARBITRATE_DEFAULT                 _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_SDMMC4_0_ENB_FAST_REARBITRATE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_SDMMC4_0_ENB_FAST_REARBITRATE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC4_0_ENB_FAST_REARBITRATE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC4_0_ENB_FAST_REARBITRATE_DISABLE                 _MK_ENUM_CONST(0)
+#define AHB_GIZMO_SDMMC4_0_ENB_FAST_REARBITRATE_ENABLE                  _MK_ENUM_CONST(1)
+
+//AHB slave gizmo - Force all AHB transaction to single data request transaction.  1 = force to single data transaction always. 0 = dont force to single data transaction.
+#define AHB_GIZMO_SDMMC4_0_FORCE_TO_AHB_SINGLE_SHIFT                    _MK_SHIFT_CONST(1)
+#define AHB_GIZMO_SDMMC4_0_FORCE_TO_AHB_SINGLE_FIELD                    (_MK_MASK_CONST(0x1) << AHB_GIZMO_SDMMC4_0_FORCE_TO_AHB_SINGLE_SHIFT)
+#define AHB_GIZMO_SDMMC4_0_FORCE_TO_AHB_SINGLE_RANGE                    1:1
+#define AHB_GIZMO_SDMMC4_0_FORCE_TO_AHB_SINGLE_WOFFSET                  0x0
+#define AHB_GIZMO_SDMMC4_0_FORCE_TO_AHB_SINGLE_DEFAULT                  _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_SDMMC4_0_FORCE_TO_AHB_SINGLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_SDMMC4_0_FORCE_TO_AHB_SINGLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC4_0_FORCE_TO_AHB_SINGLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC4_0_FORCE_TO_AHB_SINGLE_NOT_SINGLE_DATA                  _MK_ENUM_CONST(0)
+#define AHB_GIZMO_SDMMC4_0_FORCE_TO_AHB_SINGLE_SINGLE_DATA                      _MK_ENUM_CONST(1)
+
+//AHB slave gizmo - Enable splitting AHB transactions.  1 = enable  0 = disable
+#define AHB_GIZMO_SDMMC4_0_ENABLE_SPLIT_SHIFT                   _MK_SHIFT_CONST(0)
+#define AHB_GIZMO_SDMMC4_0_ENABLE_SPLIT_FIELD                   (_MK_MASK_CONST(0x1) << AHB_GIZMO_SDMMC4_0_ENABLE_SPLIT_SHIFT)
+#define AHB_GIZMO_SDMMC4_0_ENABLE_SPLIT_RANGE                   0:0
+#define AHB_GIZMO_SDMMC4_0_ENABLE_SPLIT_WOFFSET                 0x0
+#define AHB_GIZMO_SDMMC4_0_ENABLE_SPLIT_DEFAULT                 _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_SDMMC4_0_ENABLE_SPLIT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_SDMMC4_0_ENABLE_SPLIT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC4_0_ENABLE_SPLIT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC4_0_ENABLE_SPLIT_DISABLE                 _MK_ENUM_CONST(0)
+#define AHB_GIZMO_SDMMC4_0_ENABLE_SPLIT_ENABLE                  _MK_ENUM_CONST(1)
+
+
+// Register AHB_GIZMO_XIO_0  
+#define AHB_GIZMO_XIO_0                 _MK_ADDR_CONST(0x48)
+#define AHB_GIZMO_XIO_0_SECURE                  0x0
+#define AHB_GIZMO_XIO_0_WORD_COUNT                      0x1
+#define AHB_GIZMO_XIO_0_RESET_VAL                       _MK_MASK_CONST(0x40000)
+#define AHB_GIZMO_XIO_0_RESET_MASK                      _MK_MASK_CONST(0xff0f0000)
+#define AHB_GIZMO_XIO_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_XIO_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_XIO_0_READ_MASK                       _MK_MASK_CONST(0xff0f0000)
+#define AHB_GIZMO_XIO_0_WRITE_MASK                      _MK_MASK_CONST(0xff0f0000)
+// AHB master request negate count. This is an 8-bit  counter use to indicate the minimum number of clk count 
+// between requests from  this AHB master.
+#define AHB_GIZMO_XIO_0_REQ_NEG_CNT_SHIFT                       _MK_SHIFT_CONST(24)
+#define AHB_GIZMO_XIO_0_REQ_NEG_CNT_FIELD                       (_MK_MASK_CONST(0xff) << AHB_GIZMO_XIO_0_REQ_NEG_CNT_SHIFT)
+#define AHB_GIZMO_XIO_0_REQ_NEG_CNT_RANGE                       31:24
+#define AHB_GIZMO_XIO_0_REQ_NEG_CNT_WOFFSET                     0x0
+#define AHB_GIZMO_XIO_0_REQ_NEG_CNT_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_XIO_0_REQ_NEG_CNT_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define AHB_GIZMO_XIO_0_REQ_NEG_CNT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_XIO_0_REQ_NEG_CNT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// AHB master gizmo - Pack all AHB read data.  1 = wait for all requested read data to be 
+// in the AHB gizmos queue before returning the data back to the IP.  0 = transfer each read 
+// data from the AHB to the IP  immediately.
+#define AHB_GIZMO_XIO_0_RD_DATA_SHIFT                   _MK_SHIFT_CONST(19)
+#define AHB_GIZMO_XIO_0_RD_DATA_FIELD                   (_MK_MASK_CONST(0x1) << AHB_GIZMO_XIO_0_RD_DATA_SHIFT)
+#define AHB_GIZMO_XIO_0_RD_DATA_RANGE                   19:19
+#define AHB_GIZMO_XIO_0_RD_DATA_WOFFSET                 0x0
+#define AHB_GIZMO_XIO_0_RD_DATA_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_XIO_0_RD_DATA_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_XIO_0_RD_DATA_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_XIO_0_RD_DATA_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_XIO_0_RD_DATA_NO_WAIT                 _MK_ENUM_CONST(0)
+#define AHB_GIZMO_XIO_0_RD_DATA_WAIT                    _MK_ENUM_CONST(1)
+
+// AHB master gizmo (AHB-DMA) - Start AHB write request immediately.  1 = start the AHB 
+// write request immediately as soon as the device  has put one write data in the AHB 
+// gizmos queue.  0 = start the AHB write request only when all the  write data has 
+// transferred from the device to the AHB gizmos queue.
+#define AHB_GIZMO_XIO_0_IMMEDIATE_SHIFT                 _MK_SHIFT_CONST(18)
+#define AHB_GIZMO_XIO_0_IMMEDIATE_FIELD                 (_MK_MASK_CONST(0x1) << AHB_GIZMO_XIO_0_IMMEDIATE_SHIFT)
+#define AHB_GIZMO_XIO_0_IMMEDIATE_RANGE                 18:18
+#define AHB_GIZMO_XIO_0_IMMEDIATE_WOFFSET                       0x0
+#define AHB_GIZMO_XIO_0_IMMEDIATE_DEFAULT                       _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_XIO_0_IMMEDIATE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_XIO_0_IMMEDIATE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_XIO_0_IMMEDIATE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_XIO_0_IMMEDIATE_DISABLE                       _MK_ENUM_CONST(0)
+#define AHB_GIZMO_XIO_0_IMMEDIATE_ENABLE                        _MK_ENUM_CONST(1)
+
+// AHB master gizmo - Maximum allowed 
+// AHB burst size.  
+// 00 = single transfer.  
+// 01 = burst-of-4.  
+// 10 = burst-of-8.  
+// 11 = burst-of-16.
+#define AHB_GIZMO_XIO_0_MAX_AHB_BURSTSIZE_SHIFT                 _MK_SHIFT_CONST(16)
+#define AHB_GIZMO_XIO_0_MAX_AHB_BURSTSIZE_FIELD                 (_MK_MASK_CONST(0x3) << AHB_GIZMO_XIO_0_MAX_AHB_BURSTSIZE_SHIFT)
+#define AHB_GIZMO_XIO_0_MAX_AHB_BURSTSIZE_RANGE                 17:16
+#define AHB_GIZMO_XIO_0_MAX_AHB_BURSTSIZE_WOFFSET                       0x0
+#define AHB_GIZMO_XIO_0_MAX_AHB_BURSTSIZE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_XIO_0_MAX_AHB_BURSTSIZE_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define AHB_GIZMO_XIO_0_MAX_AHB_BURSTSIZE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_XIO_0_MAX_AHB_BURSTSIZE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_XIO_0_MAX_AHB_BURSTSIZE_DMA_BURST_1WORDS                      _MK_ENUM_CONST(0)
+#define AHB_GIZMO_XIO_0_MAX_AHB_BURSTSIZE_DMA_BURST_4WORDS                      _MK_ENUM_CONST(1)
+#define AHB_GIZMO_XIO_0_MAX_AHB_BURSTSIZE_DMA_BURST_8WORDS                      _MK_ENUM_CONST(2)
+#define AHB_GIZMO_XIO_0_MAX_AHB_BURSTSIZE_DMA_BURST_16WORDS                     _MK_ENUM_CONST(3)
+
+
+// Reserved address 76 [0x4c] 
+
+// Reserved address 80 [0x50] 
+
+// Reserved address 84 [0x54] 
+
+// Reserved address 88 [0x58] 
+
+// Reserved address 92 [0x5c] 
+
+// Register AHB_GIZMO_BSEV_0  
+#define AHB_GIZMO_BSEV_0                        _MK_ADDR_CONST(0x60)
+#define AHB_GIZMO_BSEV_0_SECURE                         0x0
+#define AHB_GIZMO_BSEV_0_WORD_COUNT                     0x1
+#define AHB_GIZMO_BSEV_0_RESET_VAL                      _MK_MASK_CONST(0x20000)
+#define AHB_GIZMO_BSEV_0_RESET_MASK                     _MK_MASK_CONST(0xff0f0000)
+#define AHB_GIZMO_BSEV_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_BSEV_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_BSEV_0_READ_MASK                      _MK_MASK_CONST(0xff0f0000)
+#define AHB_GIZMO_BSEV_0_WRITE_MASK                     _MK_MASK_CONST(0xff0f0000)
+// AHB master request negate count. This is an 8-bit  counter use to indicate the minimum number of clk count 
+// between requests from  this AHB master.
+#define AHB_GIZMO_BSEV_0_REQ_NEG_CNT_SHIFT                      _MK_SHIFT_CONST(24)
+#define AHB_GIZMO_BSEV_0_REQ_NEG_CNT_FIELD                      (_MK_MASK_CONST(0xff) << AHB_GIZMO_BSEV_0_REQ_NEG_CNT_SHIFT)
+#define AHB_GIZMO_BSEV_0_REQ_NEG_CNT_RANGE                      31:24
+#define AHB_GIZMO_BSEV_0_REQ_NEG_CNT_WOFFSET                    0x0
+#define AHB_GIZMO_BSEV_0_REQ_NEG_CNT_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_BSEV_0_REQ_NEG_CNT_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
+#define AHB_GIZMO_BSEV_0_REQ_NEG_CNT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_BSEV_0_REQ_NEG_CNT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// AHB master gizmo - Pack all AHB read data.  1 = wait for all requested read data to be 
+// in the AHB gizmos queue before returning the data back to the IP.  0 = transfer each read 
+// data from the AHB to the IP  immediately.
+#define AHB_GIZMO_BSEV_0_RD_DATA_SHIFT                  _MK_SHIFT_CONST(19)
+#define AHB_GIZMO_BSEV_0_RD_DATA_FIELD                  (_MK_MASK_CONST(0x1) << AHB_GIZMO_BSEV_0_RD_DATA_SHIFT)
+#define AHB_GIZMO_BSEV_0_RD_DATA_RANGE                  19:19
+#define AHB_GIZMO_BSEV_0_RD_DATA_WOFFSET                        0x0
+#define AHB_GIZMO_BSEV_0_RD_DATA_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_BSEV_0_RD_DATA_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_BSEV_0_RD_DATA_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_BSEV_0_RD_DATA_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_BSEV_0_RD_DATA_NO_WAIT                        _MK_ENUM_CONST(0)
+#define AHB_GIZMO_BSEV_0_RD_DATA_WAIT                   _MK_ENUM_CONST(1)
+
+// AHB master gizmo (AHB-DMA) - Start AHB write request immediately.  1 = start the AHB 
+// write request immediately as soon as the device  has put one write data in the AHB 
+// gizmos queue.  0 = start the AHB write request only when all the  write data has 
+// transferred from the device to the AHB gizmos queue. !!THIS SHOULD NEVER BE SET TO 
+// ENABLE!! (BSEV requires this bit to be 0) 
+#define AHB_GIZMO_BSEV_0_IMMEDIATE_SHIFT                        _MK_SHIFT_CONST(18)
+#define AHB_GIZMO_BSEV_0_IMMEDIATE_FIELD                        (_MK_MASK_CONST(0x1) << AHB_GIZMO_BSEV_0_IMMEDIATE_SHIFT)
+#define AHB_GIZMO_BSEV_0_IMMEDIATE_RANGE                        18:18
+#define AHB_GIZMO_BSEV_0_IMMEDIATE_WOFFSET                      0x0
+#define AHB_GIZMO_BSEV_0_IMMEDIATE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_BSEV_0_IMMEDIATE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_BSEV_0_IMMEDIATE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_BSEV_0_IMMEDIATE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_BSEV_0_IMMEDIATE_DISABLE                      _MK_ENUM_CONST(0)
+#define AHB_GIZMO_BSEV_0_IMMEDIATE_ENABLE                       _MK_ENUM_CONST(1)
+
+// AHB master gizmo - Maximum 
+// allowed AHB burst size.  
+// 00 = single transfer.  
+// 01 = burst-of-4.  
+// 10 = burst-of-8.
+// 11 = burst-of-16.
+#define AHB_GIZMO_BSEV_0_MAX_AHB_BURSTSIZE_SHIFT                        _MK_SHIFT_CONST(16)
+#define AHB_GIZMO_BSEV_0_MAX_AHB_BURSTSIZE_FIELD                        (_MK_MASK_CONST(0x3) << AHB_GIZMO_BSEV_0_MAX_AHB_BURSTSIZE_SHIFT)
+#define AHB_GIZMO_BSEV_0_MAX_AHB_BURSTSIZE_RANGE                        17:16
+#define AHB_GIZMO_BSEV_0_MAX_AHB_BURSTSIZE_WOFFSET                      0x0
+#define AHB_GIZMO_BSEV_0_MAX_AHB_BURSTSIZE_DEFAULT                      _MK_MASK_CONST(0x2)
+#define AHB_GIZMO_BSEV_0_MAX_AHB_BURSTSIZE_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define AHB_GIZMO_BSEV_0_MAX_AHB_BURSTSIZE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_BSEV_0_MAX_AHB_BURSTSIZE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_BSEV_0_MAX_AHB_BURSTSIZE_DMA_BURST_1WORDS                     _MK_ENUM_CONST(0)
+#define AHB_GIZMO_BSEV_0_MAX_AHB_BURSTSIZE_DMA_BURST_4WORDS                     _MK_ENUM_CONST(1)
+#define AHB_GIZMO_BSEV_0_MAX_AHB_BURSTSIZE_DMA_BURST_8WORDS                     _MK_ENUM_CONST(2)
+#define AHB_GIZMO_BSEV_0_MAX_AHB_BURSTSIZE_DMA_BURST_16WORDS                    _MK_ENUM_CONST(3)
+
+
+// Reserved address 100 [0x64] 
+
+// Reserved address 104 [0x68] 
+
+// Reserved address 108 [0x6c] 
+
+// Register AHB_GIZMO_BSEA_0  
+#define AHB_GIZMO_BSEA_0                        _MK_ADDR_CONST(0x70)
+#define AHB_GIZMO_BSEA_0_SECURE                         0x0
+#define AHB_GIZMO_BSEA_0_WORD_COUNT                     0x1
+#define AHB_GIZMO_BSEA_0_RESET_VAL                      _MK_MASK_CONST(0x20000)
+#define AHB_GIZMO_BSEA_0_RESET_MASK                     _MK_MASK_CONST(0xff070000)
+#define AHB_GIZMO_BSEA_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_BSEA_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_BSEA_0_READ_MASK                      _MK_MASK_CONST(0xff070000)
+#define AHB_GIZMO_BSEA_0_WRITE_MASK                     _MK_MASK_CONST(0xff070000)
+// AHB master request negate count. This is an 8-bit  counter use to indicate the minimum number of clk count 
+// between requests from  this AHB master.
+#define AHB_GIZMO_BSEA_0_REQ_NEG_CNT_SHIFT                      _MK_SHIFT_CONST(24)
+#define AHB_GIZMO_BSEA_0_REQ_NEG_CNT_FIELD                      (_MK_MASK_CONST(0xff) << AHB_GIZMO_BSEA_0_REQ_NEG_CNT_SHIFT)
+#define AHB_GIZMO_BSEA_0_REQ_NEG_CNT_RANGE                      31:24
+#define AHB_GIZMO_BSEA_0_REQ_NEG_CNT_WOFFSET                    0x0
+#define AHB_GIZMO_BSEA_0_REQ_NEG_CNT_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_BSEA_0_REQ_NEG_CNT_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
+#define AHB_GIZMO_BSEA_0_REQ_NEG_CNT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_BSEA_0_REQ_NEG_CNT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// AHB master gizmo - Start AHB write request immediately.  1 = start the AHB 
+// write request immediately as soon as the device puts data in the AHB gizmos 
+// queue.  0 = start the AHB write request only when all the  write data has 
+// transferred from the device to the AHB gizmos queue.  !!THIS SHOULD NEVER BE 
+// SET TO ENABLE!! (BSEV requires this bit to be 0) 
+#define AHB_GIZMO_BSEA_0_IMMEDIATE_SHIFT                        _MK_SHIFT_CONST(18)
+#define AHB_GIZMO_BSEA_0_IMMEDIATE_FIELD                        (_MK_MASK_CONST(0x1) << AHB_GIZMO_BSEA_0_IMMEDIATE_SHIFT)
+#define AHB_GIZMO_BSEA_0_IMMEDIATE_RANGE                        18:18
+#define AHB_GIZMO_BSEA_0_IMMEDIATE_WOFFSET                      0x0
+#define AHB_GIZMO_BSEA_0_IMMEDIATE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_BSEA_0_IMMEDIATE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_BSEA_0_IMMEDIATE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_BSEA_0_IMMEDIATE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_BSEA_0_IMMEDIATE_DISABLE                      _MK_ENUM_CONST(0)
+#define AHB_GIZMO_BSEA_0_IMMEDIATE_ENABLE                       _MK_ENUM_CONST(1)
+
+// AHB master gizmo - Maximum 
+// allowed AHB burst size.  
+// 00 = single transfer.  
+// 01 = burst-of-4.  
+// 10 = burst-of-8.  
+// 11 = burst-of-16.
+#define AHB_GIZMO_BSEA_0_MAX_AHB_BURSTSIZE_SHIFT                        _MK_SHIFT_CONST(16)
+#define AHB_GIZMO_BSEA_0_MAX_AHB_BURSTSIZE_FIELD                        (_MK_MASK_CONST(0x3) << AHB_GIZMO_BSEA_0_MAX_AHB_BURSTSIZE_SHIFT)
+#define AHB_GIZMO_BSEA_0_MAX_AHB_BURSTSIZE_RANGE                        17:16
+#define AHB_GIZMO_BSEA_0_MAX_AHB_BURSTSIZE_WOFFSET                      0x0
+#define AHB_GIZMO_BSEA_0_MAX_AHB_BURSTSIZE_DEFAULT                      _MK_MASK_CONST(0x2)
+#define AHB_GIZMO_BSEA_0_MAX_AHB_BURSTSIZE_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define AHB_GIZMO_BSEA_0_MAX_AHB_BURSTSIZE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_BSEA_0_MAX_AHB_BURSTSIZE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_BSEA_0_MAX_AHB_BURSTSIZE_DMA_BURST_1WORDS                     _MK_ENUM_CONST(0)
+#define AHB_GIZMO_BSEA_0_MAX_AHB_BURSTSIZE_DMA_BURST_4WORDS                     _MK_ENUM_CONST(1)
+#define AHB_GIZMO_BSEA_0_MAX_AHB_BURSTSIZE_DMA_BURST_8WORDS                     _MK_ENUM_CONST(2)
+#define AHB_GIZMO_BSEA_0_MAX_AHB_BURSTSIZE_DMA_BURST_16WORDS                    _MK_ENUM_CONST(3)
+
+
+// Register AHB_GIZMO_NOR_0  
+#define AHB_GIZMO_NOR_0                 _MK_ADDR_CONST(0x74)
+#define AHB_GIZMO_NOR_0_SECURE                  0x0
+#define AHB_GIZMO_NOR_0_WORD_COUNT                      0x1
+#define AHB_GIZMO_NOR_0_RESET_VAL                       _MK_MASK_CONST(0x85)
+#define AHB_GIZMO_NOR_0_RESET_MASK                      _MK_MASK_CONST(0xc7)
+#define AHB_GIZMO_NOR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_NOR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_NOR_0_READ_MASK                       _MK_MASK_CONST(0xc7)
+#define AHB_GIZMO_NOR_0_WRITE_MASK                      _MK_MASK_CONST(0xc7)
+// AHB slave gizmo - Dont split AHB write transaction.  1 = dont split AHB 
+// write transaction ever. 0 (and enable_split=1) = allow AHB write  
+// transaction to be split.
+#define AHB_GIZMO_NOR_0_DONT_SPLIT_AHB_WR_SHIFT                 _MK_SHIFT_CONST(7)
+#define AHB_GIZMO_NOR_0_DONT_SPLIT_AHB_WR_FIELD                 (_MK_MASK_CONST(0x1) << AHB_GIZMO_NOR_0_DONT_SPLIT_AHB_WR_SHIFT)
+#define AHB_GIZMO_NOR_0_DONT_SPLIT_AHB_WR_RANGE                 7:7
+#define AHB_GIZMO_NOR_0_DONT_SPLIT_AHB_WR_WOFFSET                       0x0
+#define AHB_GIZMO_NOR_0_DONT_SPLIT_AHB_WR_DEFAULT                       _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_NOR_0_DONT_SPLIT_AHB_WR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_NOR_0_DONT_SPLIT_AHB_WR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_NOR_0_DONT_SPLIT_AHB_WR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_NOR_0_DONT_SPLIT_AHB_WR_ENABLE                        _MK_ENUM_CONST(0)
+#define AHB_GIZMO_NOR_0_DONT_SPLIT_AHB_WR_DISABLE                       _MK_ENUM_CONST(1)
+
+// AHB slave gizmo - Accept AHB write request always.  
+// 1 = always accept AHB write request without checking whether 
+// there is room in the queue to store the write data. 0 = accept 
+// AHB write request only when theres  enough room in the queue 
+// to store all the write data.
+#define AHB_GIZMO_NOR_0_ACCEPT_AHB_WR_ALWAYS_SHIFT                      _MK_SHIFT_CONST(6)
+#define AHB_GIZMO_NOR_0_ACCEPT_AHB_WR_ALWAYS_FIELD                      (_MK_MASK_CONST(0x1) << AHB_GIZMO_NOR_0_ACCEPT_AHB_WR_ALWAYS_SHIFT)
+#define AHB_GIZMO_NOR_0_ACCEPT_AHB_WR_ALWAYS_RANGE                      6:6
+#define AHB_GIZMO_NOR_0_ACCEPT_AHB_WR_ALWAYS_WOFFSET                    0x0
+#define AHB_GIZMO_NOR_0_ACCEPT_AHB_WR_ALWAYS_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_NOR_0_ACCEPT_AHB_WR_ALWAYS_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_NOR_0_ACCEPT_AHB_WR_ALWAYS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_NOR_0_ACCEPT_AHB_WR_ALWAYS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_NOR_0_ACCEPT_AHB_WR_ALWAYS_ACCEPT_ON_CHECK                    _MK_ENUM_CONST(0)
+#define AHB_GIZMO_NOR_0_ACCEPT_AHB_WR_ALWAYS_ACCEPT_ON_NOCHECK                  _MK_ENUM_CONST(1)
+
+// AHB slave gizmo - Enable fast re-arbitration.  1 = allow AHB master 
+// re-arbitration as soon as the device returns one read data into the gizmos 
+// queue.  0 = allow AHB master re-arbitration only when the  device returns all 
+// read data into the gizmos queue.
+#define AHB_GIZMO_NOR_0_ENB_FAST_REARBITRATE_SHIFT                      _MK_SHIFT_CONST(2)
+#define AHB_GIZMO_NOR_0_ENB_FAST_REARBITRATE_FIELD                      (_MK_MASK_CONST(0x1) << AHB_GIZMO_NOR_0_ENB_FAST_REARBITRATE_SHIFT)
+#define AHB_GIZMO_NOR_0_ENB_FAST_REARBITRATE_RANGE                      2:2
+#define AHB_GIZMO_NOR_0_ENB_FAST_REARBITRATE_WOFFSET                    0x0
+#define AHB_GIZMO_NOR_0_ENB_FAST_REARBITRATE_DEFAULT                    _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_NOR_0_ENB_FAST_REARBITRATE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_NOR_0_ENB_FAST_REARBITRATE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_NOR_0_ENB_FAST_REARBITRATE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_NOR_0_ENB_FAST_REARBITRATE_DISABLE                    _MK_ENUM_CONST(0)
+#define AHB_GIZMO_NOR_0_ENB_FAST_REARBITRATE_ENABLE                     _MK_ENUM_CONST(1)
+
+// AHB slave gizmo - Force all AHB transaction to single data request 
+// transaction.  1 = force to single data transaction always.  
+// 0 = dont force to single data  transaction.
+#define AHB_GIZMO_NOR_0_FORCE_TO_AHB_SINGLE_SHIFT                       _MK_SHIFT_CONST(1)
+#define AHB_GIZMO_NOR_0_FORCE_TO_AHB_SINGLE_FIELD                       (_MK_MASK_CONST(0x1) << AHB_GIZMO_NOR_0_FORCE_TO_AHB_SINGLE_SHIFT)
+#define AHB_GIZMO_NOR_0_FORCE_TO_AHB_SINGLE_RANGE                       1:1
+#define AHB_GIZMO_NOR_0_FORCE_TO_AHB_SINGLE_WOFFSET                     0x0
+#define AHB_GIZMO_NOR_0_FORCE_TO_AHB_SINGLE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_NOR_0_FORCE_TO_AHB_SINGLE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_NOR_0_FORCE_TO_AHB_SINGLE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_NOR_0_FORCE_TO_AHB_SINGLE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_NOR_0_FORCE_TO_AHB_SINGLE_NOT_SINGLE_DATA                     _MK_ENUM_CONST(0)
+#define AHB_GIZMO_NOR_0_FORCE_TO_AHB_SINGLE_SINGLE_DATA                 _MK_ENUM_CONST(1)
+
+// AHB slave gizmo - Enable splitting AHB transactions.  1 = enable 0 = disable
+#define AHB_GIZMO_NOR_0_ENABLE_SPLIT_SHIFT                      _MK_SHIFT_CONST(0)
+#define AHB_GIZMO_NOR_0_ENABLE_SPLIT_FIELD                      (_MK_MASK_CONST(0x1) << AHB_GIZMO_NOR_0_ENABLE_SPLIT_SHIFT)
+#define AHB_GIZMO_NOR_0_ENABLE_SPLIT_RANGE                      0:0
+#define AHB_GIZMO_NOR_0_ENABLE_SPLIT_WOFFSET                    0x0
+#define AHB_GIZMO_NOR_0_ENABLE_SPLIT_DEFAULT                    _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_NOR_0_ENABLE_SPLIT_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_NOR_0_ENABLE_SPLIT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_NOR_0_ENABLE_SPLIT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_NOR_0_ENABLE_SPLIT_DISABLE                    _MK_ENUM_CONST(0)
+#define AHB_GIZMO_NOR_0_ENABLE_SPLIT_ENABLE                     _MK_ENUM_CONST(1)
+
+
+// Register AHB_GIZMO_USB2_0  
+#define AHB_GIZMO_USB2_0                        _MK_ADDR_CONST(0x78)
+#define AHB_GIZMO_USB2_0_SECURE                         0x0
+#define AHB_GIZMO_USB2_0_WORD_COUNT                     0x1
+#define AHB_GIZMO_USB2_0_RESET_VAL                      _MK_MASK_CONST(0x20087)
+#define AHB_GIZMO_USB2_0_RESET_MASK                     _MK_MASK_CONST(0xff0700c7)
+#define AHB_GIZMO_USB2_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB2_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB2_0_READ_MASK                      _MK_MASK_CONST(0xff0700c7)
+#define AHB_GIZMO_USB2_0_WRITE_MASK                     _MK_MASK_CONST(0xff0700c7)
+// AHB master request negate count. This is an 8-bit  counter use to indicate the minimum number of clk count between requests from  this AHB master.
+#define AHB_GIZMO_USB2_0_REQ_NEG_CNT_SHIFT                      _MK_SHIFT_CONST(24)
+#define AHB_GIZMO_USB2_0_REQ_NEG_CNT_FIELD                      (_MK_MASK_CONST(0xff) << AHB_GIZMO_USB2_0_REQ_NEG_CNT_SHIFT)
+#define AHB_GIZMO_USB2_0_REQ_NEG_CNT_RANGE                      31:24
+#define AHB_GIZMO_USB2_0_REQ_NEG_CNT_WOFFSET                    0x0
+#define AHB_GIZMO_USB2_0_REQ_NEG_CNT_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB2_0_REQ_NEG_CNT_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
+#define AHB_GIZMO_USB2_0_REQ_NEG_CNT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB2_0_REQ_NEG_CNT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+//AHB master gizmo - Start AHB write request immediately.  1 = start the AHB write request immediately as soon as the device puts data in the AHB gizmos queue.  0 = start the AHB write request only when all the  write data has transferred from the device to the AHB gizmos queue.
+#define AHB_GIZMO_USB2_0_IMMEDIATE_SHIFT                        _MK_SHIFT_CONST(18)
+#define AHB_GIZMO_USB2_0_IMMEDIATE_FIELD                        (_MK_MASK_CONST(0x1) << AHB_GIZMO_USB2_0_IMMEDIATE_SHIFT)
+#define AHB_GIZMO_USB2_0_IMMEDIATE_RANGE                        18:18
+#define AHB_GIZMO_USB2_0_IMMEDIATE_WOFFSET                      0x0
+#define AHB_GIZMO_USB2_0_IMMEDIATE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB2_0_IMMEDIATE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_USB2_0_IMMEDIATE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB2_0_IMMEDIATE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB2_0_IMMEDIATE_DISABLE                      _MK_ENUM_CONST(0)
+#define AHB_GIZMO_USB2_0_IMMEDIATE_ENABLE                       _MK_ENUM_CONST(1)
+
+//AHB master gizmo - Maximum allowed AHB burst size.  00 = single transfer.  01 = burst-of-4.  10 = burst-of-8.  11 = burst-of-16.
+#define AHB_GIZMO_USB2_0_MAX_AHB_BURSTSIZE_SHIFT                        _MK_SHIFT_CONST(16)
+#define AHB_GIZMO_USB2_0_MAX_AHB_BURSTSIZE_FIELD                        (_MK_MASK_CONST(0x3) << AHB_GIZMO_USB2_0_MAX_AHB_BURSTSIZE_SHIFT)
+#define AHB_GIZMO_USB2_0_MAX_AHB_BURSTSIZE_RANGE                        17:16
+#define AHB_GIZMO_USB2_0_MAX_AHB_BURSTSIZE_WOFFSET                      0x0
+#define AHB_GIZMO_USB2_0_MAX_AHB_BURSTSIZE_DEFAULT                      _MK_MASK_CONST(0x2)
+#define AHB_GIZMO_USB2_0_MAX_AHB_BURSTSIZE_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define AHB_GIZMO_USB2_0_MAX_AHB_BURSTSIZE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB2_0_MAX_AHB_BURSTSIZE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB2_0_MAX_AHB_BURSTSIZE_DMA_BURST_1WORDS                     _MK_ENUM_CONST(0)
+#define AHB_GIZMO_USB2_0_MAX_AHB_BURSTSIZE_DMA_BURST_4WORDS                     _MK_ENUM_CONST(1)
+#define AHB_GIZMO_USB2_0_MAX_AHB_BURSTSIZE_DMA_BURST_8WORDS                     _MK_ENUM_CONST(2)
+#define AHB_GIZMO_USB2_0_MAX_AHB_BURSTSIZE_DMA_BURST_16WORDS                    _MK_ENUM_CONST(3)
+
+//AHB slave gizmo - Dont split AHB write transaction.  1 = dont split AHB write transaction ever. 0 (and enable_split=1) = allow AHB write  transaction to be split.
+#define AHB_GIZMO_USB2_0_DONT_SPLIT_AHB_WR_SHIFT                        _MK_SHIFT_CONST(7)
+#define AHB_GIZMO_USB2_0_DONT_SPLIT_AHB_WR_FIELD                        (_MK_MASK_CONST(0x1) << AHB_GIZMO_USB2_0_DONT_SPLIT_AHB_WR_SHIFT)
+#define AHB_GIZMO_USB2_0_DONT_SPLIT_AHB_WR_RANGE                        7:7
+#define AHB_GIZMO_USB2_0_DONT_SPLIT_AHB_WR_WOFFSET                      0x0
+#define AHB_GIZMO_USB2_0_DONT_SPLIT_AHB_WR_DEFAULT                      _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_USB2_0_DONT_SPLIT_AHB_WR_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_USB2_0_DONT_SPLIT_AHB_WR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB2_0_DONT_SPLIT_AHB_WR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB2_0_DONT_SPLIT_AHB_WR_ENABLE                       _MK_ENUM_CONST(0)
+#define AHB_GIZMO_USB2_0_DONT_SPLIT_AHB_WR_DISABLE                      _MK_ENUM_CONST(1)
+
+//AHB slave gizmo - Accept AHB write request always.  1 = always accept AHB write request without checking whether there is room in the queue to store the write data. 0 = accept AHB write request only when theres  enough room in the queue to store all the write data.
+#define AHB_GIZMO_USB2_0_ACCEPT_AHB_WR_ALWAYS_SHIFT                     _MK_SHIFT_CONST(6)
+#define AHB_GIZMO_USB2_0_ACCEPT_AHB_WR_ALWAYS_FIELD                     (_MK_MASK_CONST(0x1) << AHB_GIZMO_USB2_0_ACCEPT_AHB_WR_ALWAYS_SHIFT)
+#define AHB_GIZMO_USB2_0_ACCEPT_AHB_WR_ALWAYS_RANGE                     6:6
+#define AHB_GIZMO_USB2_0_ACCEPT_AHB_WR_ALWAYS_WOFFSET                   0x0
+#define AHB_GIZMO_USB2_0_ACCEPT_AHB_WR_ALWAYS_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB2_0_ACCEPT_AHB_WR_ALWAYS_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_USB2_0_ACCEPT_AHB_WR_ALWAYS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB2_0_ACCEPT_AHB_WR_ALWAYS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB2_0_ACCEPT_AHB_WR_ALWAYS_ACCEPT_ON_CHECK                   _MK_ENUM_CONST(0)
+#define AHB_GIZMO_USB2_0_ACCEPT_AHB_WR_ALWAYS_ACCEPT_ON_NOCHECK                 _MK_ENUM_CONST(1)
+
+//AHB slave gizmo - Enable fast re-arbitration.  1 = allow AHB master re-arbitration as soon as the device returns one read data into the gizmos queue. 0 = allow AHB master re-arbitration only when the  device returns all read data into the gizmos queue.
+#define AHB_GIZMO_USB2_0_ENB_FAST_REARBITRATE_SHIFT                     _MK_SHIFT_CONST(2)
+#define AHB_GIZMO_USB2_0_ENB_FAST_REARBITRATE_FIELD                     (_MK_MASK_CONST(0x1) << AHB_GIZMO_USB2_0_ENB_FAST_REARBITRATE_SHIFT)
+#define AHB_GIZMO_USB2_0_ENB_FAST_REARBITRATE_RANGE                     2:2
+#define AHB_GIZMO_USB2_0_ENB_FAST_REARBITRATE_WOFFSET                   0x0
+#define AHB_GIZMO_USB2_0_ENB_FAST_REARBITRATE_DEFAULT                   _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_USB2_0_ENB_FAST_REARBITRATE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_USB2_0_ENB_FAST_REARBITRATE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB2_0_ENB_FAST_REARBITRATE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB2_0_ENB_FAST_REARBITRATE_DISABLE                   _MK_ENUM_CONST(0)
+#define AHB_GIZMO_USB2_0_ENB_FAST_REARBITRATE_ENABLE                    _MK_ENUM_CONST(1)
+
+//AHB slave gizmo - Force all AHB transaction to single data request transaction.  1 = force to single data transaction always. 0 = dont force to single data transaction.
+#define AHB_GIZMO_USB2_0_FORCE_TO_AHB_SINGLE_SHIFT                      _MK_SHIFT_CONST(1)
+#define AHB_GIZMO_USB2_0_FORCE_TO_AHB_SINGLE_FIELD                      (_MK_MASK_CONST(0x1) << AHB_GIZMO_USB2_0_FORCE_TO_AHB_SINGLE_SHIFT)
+#define AHB_GIZMO_USB2_0_FORCE_TO_AHB_SINGLE_RANGE                      1:1
+#define AHB_GIZMO_USB2_0_FORCE_TO_AHB_SINGLE_WOFFSET                    0x0
+#define AHB_GIZMO_USB2_0_FORCE_TO_AHB_SINGLE_DEFAULT                    _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_USB2_0_FORCE_TO_AHB_SINGLE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_USB2_0_FORCE_TO_AHB_SINGLE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB2_0_FORCE_TO_AHB_SINGLE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB2_0_FORCE_TO_AHB_SINGLE_NOT_SINGLE_DATA                    _MK_ENUM_CONST(0)
+#define AHB_GIZMO_USB2_0_FORCE_TO_AHB_SINGLE_SINGLE_DATA                        _MK_ENUM_CONST(1)
+
+//AHB slave gizmo - Enable splitting AHB transactions.  1 = enable  0 = disable
+#define AHB_GIZMO_USB2_0_ENABLE_SPLIT_SHIFT                     _MK_SHIFT_CONST(0)
+#define AHB_GIZMO_USB2_0_ENABLE_SPLIT_FIELD                     (_MK_MASK_CONST(0x1) << AHB_GIZMO_USB2_0_ENABLE_SPLIT_SHIFT)
+#define AHB_GIZMO_USB2_0_ENABLE_SPLIT_RANGE                     0:0
+#define AHB_GIZMO_USB2_0_ENABLE_SPLIT_WOFFSET                   0x0
+#define AHB_GIZMO_USB2_0_ENABLE_SPLIT_DEFAULT                   _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_USB2_0_ENABLE_SPLIT_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_USB2_0_ENABLE_SPLIT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB2_0_ENABLE_SPLIT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB2_0_ENABLE_SPLIT_DISABLE                   _MK_ENUM_CONST(0)
+#define AHB_GIZMO_USB2_0_ENABLE_SPLIT_ENABLE                    _MK_ENUM_CONST(1)
+
+
+// Register AHB_GIZMO_USB3_0  
+#define AHB_GIZMO_USB3_0                        _MK_ADDR_CONST(0x7c)
+#define AHB_GIZMO_USB3_0_SECURE                         0x0
+#define AHB_GIZMO_USB3_0_WORD_COUNT                     0x1
+#define AHB_GIZMO_USB3_0_RESET_VAL                      _MK_MASK_CONST(0x20087)
+#define AHB_GIZMO_USB3_0_RESET_MASK                     _MK_MASK_CONST(0xff0700c7)
+#define AHB_GIZMO_USB3_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB3_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB3_0_READ_MASK                      _MK_MASK_CONST(0xff0700c7)
+#define AHB_GIZMO_USB3_0_WRITE_MASK                     _MK_MASK_CONST(0xff0700c7)
+// AHB master request negate count. This is an 8-bit  counter use to indicate the minimum number of clk count between requests from  this AHB master.
+#define AHB_GIZMO_USB3_0_REQ_NEG_CNT_SHIFT                      _MK_SHIFT_CONST(24)
+#define AHB_GIZMO_USB3_0_REQ_NEG_CNT_FIELD                      (_MK_MASK_CONST(0xff) << AHB_GIZMO_USB3_0_REQ_NEG_CNT_SHIFT)
+#define AHB_GIZMO_USB3_0_REQ_NEG_CNT_RANGE                      31:24
+#define AHB_GIZMO_USB3_0_REQ_NEG_CNT_WOFFSET                    0x0
+#define AHB_GIZMO_USB3_0_REQ_NEG_CNT_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB3_0_REQ_NEG_CNT_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
+#define AHB_GIZMO_USB3_0_REQ_NEG_CNT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB3_0_REQ_NEG_CNT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+//AHB master gizmo - Start AHB write request immediately.  1 = start the AHB write request immediately as soon as the device puts data in the AHB gizmos queue.  0 = start the AHB write request only when all the  write data has transferred from the device to the AHB gizmos queue.
+#define AHB_GIZMO_USB3_0_IMMEDIATE_SHIFT                        _MK_SHIFT_CONST(18)
+#define AHB_GIZMO_USB3_0_IMMEDIATE_FIELD                        (_MK_MASK_CONST(0x1) << AHB_GIZMO_USB3_0_IMMEDIATE_SHIFT)
+#define AHB_GIZMO_USB3_0_IMMEDIATE_RANGE                        18:18
+#define AHB_GIZMO_USB3_0_IMMEDIATE_WOFFSET                      0x0
+#define AHB_GIZMO_USB3_0_IMMEDIATE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB3_0_IMMEDIATE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_USB3_0_IMMEDIATE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB3_0_IMMEDIATE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB3_0_IMMEDIATE_DISABLE                      _MK_ENUM_CONST(0)
+#define AHB_GIZMO_USB3_0_IMMEDIATE_ENABLE                       _MK_ENUM_CONST(1)
+
+//AHB master gizmo - Maximum allowed AHB burst size.  00 = single transfer.  01 = burst-of-4.  10 = burst-of-8.  11 = burst-of-16.
+#define AHB_GIZMO_USB3_0_MAX_AHB_BURSTSIZE_SHIFT                        _MK_SHIFT_CONST(16)
+#define AHB_GIZMO_USB3_0_MAX_AHB_BURSTSIZE_FIELD                        (_MK_MASK_CONST(0x3) << AHB_GIZMO_USB3_0_MAX_AHB_BURSTSIZE_SHIFT)
+#define AHB_GIZMO_USB3_0_MAX_AHB_BURSTSIZE_RANGE                        17:16
+#define AHB_GIZMO_USB3_0_MAX_AHB_BURSTSIZE_WOFFSET                      0x0
+#define AHB_GIZMO_USB3_0_MAX_AHB_BURSTSIZE_DEFAULT                      _MK_MASK_CONST(0x2)
+#define AHB_GIZMO_USB3_0_MAX_AHB_BURSTSIZE_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define AHB_GIZMO_USB3_0_MAX_AHB_BURSTSIZE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB3_0_MAX_AHB_BURSTSIZE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB3_0_MAX_AHB_BURSTSIZE_DMA_BURST_1WORDS                     _MK_ENUM_CONST(0)
+#define AHB_GIZMO_USB3_0_MAX_AHB_BURSTSIZE_DMA_BURST_4WORDS                     _MK_ENUM_CONST(1)
+#define AHB_GIZMO_USB3_0_MAX_AHB_BURSTSIZE_DMA_BURST_8WORDS                     _MK_ENUM_CONST(2)
+#define AHB_GIZMO_USB3_0_MAX_AHB_BURSTSIZE_DMA_BURST_16WORDS                    _MK_ENUM_CONST(3)
+
+//AHB slave gizmo - Dont split AHB write transaction.  1 = dont split AHB write transaction ever. 0 (and enable_split=1) = allow AHB write  transaction to be split.
+#define AHB_GIZMO_USB3_0_DONT_SPLIT_AHB_WR_SHIFT                        _MK_SHIFT_CONST(7)
+#define AHB_GIZMO_USB3_0_DONT_SPLIT_AHB_WR_FIELD                        (_MK_MASK_CONST(0x1) << AHB_GIZMO_USB3_0_DONT_SPLIT_AHB_WR_SHIFT)
+#define AHB_GIZMO_USB3_0_DONT_SPLIT_AHB_WR_RANGE                        7:7
+#define AHB_GIZMO_USB3_0_DONT_SPLIT_AHB_WR_WOFFSET                      0x0
+#define AHB_GIZMO_USB3_0_DONT_SPLIT_AHB_WR_DEFAULT                      _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_USB3_0_DONT_SPLIT_AHB_WR_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_USB3_0_DONT_SPLIT_AHB_WR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB3_0_DONT_SPLIT_AHB_WR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB3_0_DONT_SPLIT_AHB_WR_ENABLE                       _MK_ENUM_CONST(0)
+#define AHB_GIZMO_USB3_0_DONT_SPLIT_AHB_WR_DISABLE                      _MK_ENUM_CONST(1)
+
+//AHB slave gizmo - Accept AHB write request always.  1 = always accept AHB write request without checking whether there is room in the queue to store the write data. 0 = accept AHB write request only when theres  enough room in the queue to store all the write data.
+#define AHB_GIZMO_USB3_0_ACCEPT_AHB_WR_ALWAYS_SHIFT                     _MK_SHIFT_CONST(6)
+#define AHB_GIZMO_USB3_0_ACCEPT_AHB_WR_ALWAYS_FIELD                     (_MK_MASK_CONST(0x1) << AHB_GIZMO_USB3_0_ACCEPT_AHB_WR_ALWAYS_SHIFT)
+#define AHB_GIZMO_USB3_0_ACCEPT_AHB_WR_ALWAYS_RANGE                     6:6
+#define AHB_GIZMO_USB3_0_ACCEPT_AHB_WR_ALWAYS_WOFFSET                   0x0
+#define AHB_GIZMO_USB3_0_ACCEPT_AHB_WR_ALWAYS_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB3_0_ACCEPT_AHB_WR_ALWAYS_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_USB3_0_ACCEPT_AHB_WR_ALWAYS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB3_0_ACCEPT_AHB_WR_ALWAYS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB3_0_ACCEPT_AHB_WR_ALWAYS_ACCEPT_ON_CHECK                   _MK_ENUM_CONST(0)
+#define AHB_GIZMO_USB3_0_ACCEPT_AHB_WR_ALWAYS_ACCEPT_ON_NOCHECK                 _MK_ENUM_CONST(1)
+
+//AHB slave gizmo - Enable fast re-arbitration.  1 = allow AHB master re-arbitration as soon as the device returns one read data into the gizmos queue. 0 = allow AHB master re-arbitration only when the  device returns all read data into the gizmos queue.
+#define AHB_GIZMO_USB3_0_ENB_FAST_REARBITRATE_SHIFT                     _MK_SHIFT_CONST(2)
+#define AHB_GIZMO_USB3_0_ENB_FAST_REARBITRATE_FIELD                     (_MK_MASK_CONST(0x1) << AHB_GIZMO_USB3_0_ENB_FAST_REARBITRATE_SHIFT)
+#define AHB_GIZMO_USB3_0_ENB_FAST_REARBITRATE_RANGE                     2:2
+#define AHB_GIZMO_USB3_0_ENB_FAST_REARBITRATE_WOFFSET                   0x0
+#define AHB_GIZMO_USB3_0_ENB_FAST_REARBITRATE_DEFAULT                   _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_USB3_0_ENB_FAST_REARBITRATE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_USB3_0_ENB_FAST_REARBITRATE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB3_0_ENB_FAST_REARBITRATE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB3_0_ENB_FAST_REARBITRATE_DISABLE                   _MK_ENUM_CONST(0)
+#define AHB_GIZMO_USB3_0_ENB_FAST_REARBITRATE_ENABLE                    _MK_ENUM_CONST(1)
+
+//AHB slave gizmo - Force all AHB transaction to single data request transaction.  1 = force to single data transaction always. 0 = dont force to single data transaction.
+#define AHB_GIZMO_USB3_0_FORCE_TO_AHB_SINGLE_SHIFT                      _MK_SHIFT_CONST(1)
+#define AHB_GIZMO_USB3_0_FORCE_TO_AHB_SINGLE_FIELD                      (_MK_MASK_CONST(0x1) << AHB_GIZMO_USB3_0_FORCE_TO_AHB_SINGLE_SHIFT)
+#define AHB_GIZMO_USB3_0_FORCE_TO_AHB_SINGLE_RANGE                      1:1
+#define AHB_GIZMO_USB3_0_FORCE_TO_AHB_SINGLE_WOFFSET                    0x0
+#define AHB_GIZMO_USB3_0_FORCE_TO_AHB_SINGLE_DEFAULT                    _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_USB3_0_FORCE_TO_AHB_SINGLE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_USB3_0_FORCE_TO_AHB_SINGLE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB3_0_FORCE_TO_AHB_SINGLE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB3_0_FORCE_TO_AHB_SINGLE_NOT_SINGLE_DATA                    _MK_ENUM_CONST(0)
+#define AHB_GIZMO_USB3_0_FORCE_TO_AHB_SINGLE_SINGLE_DATA                        _MK_ENUM_CONST(1)
+
+//AHB slave gizmo - Enable splitting AHB transactions.  1 = enable  0 = disable
+#define AHB_GIZMO_USB3_0_ENABLE_SPLIT_SHIFT                     _MK_SHIFT_CONST(0)
+#define AHB_GIZMO_USB3_0_ENABLE_SPLIT_FIELD                     (_MK_MASK_CONST(0x1) << AHB_GIZMO_USB3_0_ENABLE_SPLIT_SHIFT)
+#define AHB_GIZMO_USB3_0_ENABLE_SPLIT_RANGE                     0:0
+#define AHB_GIZMO_USB3_0_ENABLE_SPLIT_WOFFSET                   0x0
+#define AHB_GIZMO_USB3_0_ENABLE_SPLIT_DEFAULT                   _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_USB3_0_ENABLE_SPLIT_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_USB3_0_ENABLE_SPLIT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB3_0_ENABLE_SPLIT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB3_0_ENABLE_SPLIT_DISABLE                   _MK_ENUM_CONST(0)
+#define AHB_GIZMO_USB3_0_ENABLE_SPLIT_ENABLE                    _MK_ENUM_CONST(1)
+
+
+// Register AHB_GIZMO_SDMMC1_0  
+#define AHB_GIZMO_SDMMC1_0                      _MK_ADDR_CONST(0x80)
+#define AHB_GIZMO_SDMMC1_0_SECURE                       0x0
+#define AHB_GIZMO_SDMMC1_0_WORD_COUNT                   0x1
+#define AHB_GIZMO_SDMMC1_0_RESET_VAL                    _MK_MASK_CONST(0x20087)
+#define AHB_GIZMO_SDMMC1_0_RESET_MASK                   _MK_MASK_CONST(0xff0700c7)
+#define AHB_GIZMO_SDMMC1_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC1_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC1_0_READ_MASK                    _MK_MASK_CONST(0xff0700c7)
+#define AHB_GIZMO_SDMMC1_0_WRITE_MASK                   _MK_MASK_CONST(0xff0700c7)
+// AHB master request negate count. This is an 8-bit  counter use to indicate the minimum number of clk count between requests from  this AHB master.
+#define AHB_GIZMO_SDMMC1_0_REQ_NEG_CNT_SHIFT                    _MK_SHIFT_CONST(24)
+#define AHB_GIZMO_SDMMC1_0_REQ_NEG_CNT_FIELD                    (_MK_MASK_CONST(0xff) << AHB_GIZMO_SDMMC1_0_REQ_NEG_CNT_SHIFT)
+#define AHB_GIZMO_SDMMC1_0_REQ_NEG_CNT_RANGE                    31:24
+#define AHB_GIZMO_SDMMC1_0_REQ_NEG_CNT_WOFFSET                  0x0
+#define AHB_GIZMO_SDMMC1_0_REQ_NEG_CNT_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC1_0_REQ_NEG_CNT_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
+#define AHB_GIZMO_SDMMC1_0_REQ_NEG_CNT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC1_0_REQ_NEG_CNT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+//AHB master gizmo - Start AHB write request immediately.  1 = start the AHB write request immediately as soon as the device puts data in the AHB gizmos queue.  0 = start the AHB write request only when all the  write data has transferred from the device to the AHB gizmos queue.
+#define AHB_GIZMO_SDMMC1_0_IMMEDIATE_SHIFT                      _MK_SHIFT_CONST(18)
+#define AHB_GIZMO_SDMMC1_0_IMMEDIATE_FIELD                      (_MK_MASK_CONST(0x1) << AHB_GIZMO_SDMMC1_0_IMMEDIATE_SHIFT)
+#define AHB_GIZMO_SDMMC1_0_IMMEDIATE_RANGE                      18:18
+#define AHB_GIZMO_SDMMC1_0_IMMEDIATE_WOFFSET                    0x0
+#define AHB_GIZMO_SDMMC1_0_IMMEDIATE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC1_0_IMMEDIATE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_SDMMC1_0_IMMEDIATE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC1_0_IMMEDIATE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC1_0_IMMEDIATE_DISABLE                    _MK_ENUM_CONST(0)
+#define AHB_GIZMO_SDMMC1_0_IMMEDIATE_ENABLE                     _MK_ENUM_CONST(1)
+
+//AHB master gizmo - Maximum allowed AHB burst size.  00 = single transfer.  01 = burst-of-4.  10 = burst-of-8.  11 = burst-of-16.
+#define AHB_GIZMO_SDMMC1_0_MAX_AHB_BURSTSIZE_SHIFT                      _MK_SHIFT_CONST(16)
+#define AHB_GIZMO_SDMMC1_0_MAX_AHB_BURSTSIZE_FIELD                      (_MK_MASK_CONST(0x3) << AHB_GIZMO_SDMMC1_0_MAX_AHB_BURSTSIZE_SHIFT)
+#define AHB_GIZMO_SDMMC1_0_MAX_AHB_BURSTSIZE_RANGE                      17:16
+#define AHB_GIZMO_SDMMC1_0_MAX_AHB_BURSTSIZE_WOFFSET                    0x0
+#define AHB_GIZMO_SDMMC1_0_MAX_AHB_BURSTSIZE_DEFAULT                    _MK_MASK_CONST(0x2)
+#define AHB_GIZMO_SDMMC1_0_MAX_AHB_BURSTSIZE_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define AHB_GIZMO_SDMMC1_0_MAX_AHB_BURSTSIZE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC1_0_MAX_AHB_BURSTSIZE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC1_0_MAX_AHB_BURSTSIZE_DMA_BURST_1WORDS                   _MK_ENUM_CONST(0)
+#define AHB_GIZMO_SDMMC1_0_MAX_AHB_BURSTSIZE_DMA_BURST_4WORDS                   _MK_ENUM_CONST(1)
+#define AHB_GIZMO_SDMMC1_0_MAX_AHB_BURSTSIZE_DMA_BURST_8WORDS                   _MK_ENUM_CONST(2)
+#define AHB_GIZMO_SDMMC1_0_MAX_AHB_BURSTSIZE_DMA_BURST_16WORDS                  _MK_ENUM_CONST(3)
+
+//AHB slave gizmo - Dont split AHB write transaction.  1 = dont split AHB write transaction ever. 0 (and enable_split=1) = allow AHB write  transaction to be split.
+#define AHB_GIZMO_SDMMC1_0_DONT_SPLIT_AHB_WR_SHIFT                      _MK_SHIFT_CONST(7)
+#define AHB_GIZMO_SDMMC1_0_DONT_SPLIT_AHB_WR_FIELD                      (_MK_MASK_CONST(0x1) << AHB_GIZMO_SDMMC1_0_DONT_SPLIT_AHB_WR_SHIFT)
+#define AHB_GIZMO_SDMMC1_0_DONT_SPLIT_AHB_WR_RANGE                      7:7
+#define AHB_GIZMO_SDMMC1_0_DONT_SPLIT_AHB_WR_WOFFSET                    0x0
+#define AHB_GIZMO_SDMMC1_0_DONT_SPLIT_AHB_WR_DEFAULT                    _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_SDMMC1_0_DONT_SPLIT_AHB_WR_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_SDMMC1_0_DONT_SPLIT_AHB_WR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC1_0_DONT_SPLIT_AHB_WR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC1_0_DONT_SPLIT_AHB_WR_ENABLE                     _MK_ENUM_CONST(0)
+#define AHB_GIZMO_SDMMC1_0_DONT_SPLIT_AHB_WR_DISABLE                    _MK_ENUM_CONST(1)
+
+//AHB slave gizmo - Accept AHB write request always.  1 = always accept AHB write request without checking whether there is room in the queue to store the write data. 0 = accept AHB write request only when theres  enough room in the queue to store all the write data.
+#define AHB_GIZMO_SDMMC1_0_ACCEPT_AHB_WR_ALWAYS_SHIFT                   _MK_SHIFT_CONST(6)
+#define AHB_GIZMO_SDMMC1_0_ACCEPT_AHB_WR_ALWAYS_FIELD                   (_MK_MASK_CONST(0x1) << AHB_GIZMO_SDMMC1_0_ACCEPT_AHB_WR_ALWAYS_SHIFT)
+#define AHB_GIZMO_SDMMC1_0_ACCEPT_AHB_WR_ALWAYS_RANGE                   6:6
+#define AHB_GIZMO_SDMMC1_0_ACCEPT_AHB_WR_ALWAYS_WOFFSET                 0x0
+#define AHB_GIZMO_SDMMC1_0_ACCEPT_AHB_WR_ALWAYS_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC1_0_ACCEPT_AHB_WR_ALWAYS_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_SDMMC1_0_ACCEPT_AHB_WR_ALWAYS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC1_0_ACCEPT_AHB_WR_ALWAYS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC1_0_ACCEPT_AHB_WR_ALWAYS_ACCEPT_ON_CHECK                 _MK_ENUM_CONST(0)
+#define AHB_GIZMO_SDMMC1_0_ACCEPT_AHB_WR_ALWAYS_ACCEPT_ON_NOCHECK                       _MK_ENUM_CONST(1)
+
+//AHB slave gizmo - Enable fast re-arbitration.  1 = allow AHB master re-arbitration as soon as the device returns one read data into the gizmos queue. 0 = allow AHB master re-arbitration only when the  device returns all read data into the gizmos queue.
+#define AHB_GIZMO_SDMMC1_0_ENB_FAST_REARBITRATE_SHIFT                   _MK_SHIFT_CONST(2)
+#define AHB_GIZMO_SDMMC1_0_ENB_FAST_REARBITRATE_FIELD                   (_MK_MASK_CONST(0x1) << AHB_GIZMO_SDMMC1_0_ENB_FAST_REARBITRATE_SHIFT)
+#define AHB_GIZMO_SDMMC1_0_ENB_FAST_REARBITRATE_RANGE                   2:2
+#define AHB_GIZMO_SDMMC1_0_ENB_FAST_REARBITRATE_WOFFSET                 0x0
+#define AHB_GIZMO_SDMMC1_0_ENB_FAST_REARBITRATE_DEFAULT                 _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_SDMMC1_0_ENB_FAST_REARBITRATE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_SDMMC1_0_ENB_FAST_REARBITRATE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC1_0_ENB_FAST_REARBITRATE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC1_0_ENB_FAST_REARBITRATE_DISABLE                 _MK_ENUM_CONST(0)
+#define AHB_GIZMO_SDMMC1_0_ENB_FAST_REARBITRATE_ENABLE                  _MK_ENUM_CONST(1)
+
+//AHB slave gizmo - Force all AHB transaction to single data request transaction.  1 = force to single data transaction always. 0 = dont force to single data transaction.
+#define AHB_GIZMO_SDMMC1_0_FORCE_TO_AHB_SINGLE_SHIFT                    _MK_SHIFT_CONST(1)
+#define AHB_GIZMO_SDMMC1_0_FORCE_TO_AHB_SINGLE_FIELD                    (_MK_MASK_CONST(0x1) << AHB_GIZMO_SDMMC1_0_FORCE_TO_AHB_SINGLE_SHIFT)
+#define AHB_GIZMO_SDMMC1_0_FORCE_TO_AHB_SINGLE_RANGE                    1:1
+#define AHB_GIZMO_SDMMC1_0_FORCE_TO_AHB_SINGLE_WOFFSET                  0x0
+#define AHB_GIZMO_SDMMC1_0_FORCE_TO_AHB_SINGLE_DEFAULT                  _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_SDMMC1_0_FORCE_TO_AHB_SINGLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_SDMMC1_0_FORCE_TO_AHB_SINGLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC1_0_FORCE_TO_AHB_SINGLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC1_0_FORCE_TO_AHB_SINGLE_NOT_SINGLE_DATA                  _MK_ENUM_CONST(0)
+#define AHB_GIZMO_SDMMC1_0_FORCE_TO_AHB_SINGLE_SINGLE_DATA                      _MK_ENUM_CONST(1)
+
+//AHB slave gizmo - Enable splitting AHB transactions.  1 = enable  0 = disable
+#define AHB_GIZMO_SDMMC1_0_ENABLE_SPLIT_SHIFT                   _MK_SHIFT_CONST(0)
+#define AHB_GIZMO_SDMMC1_0_ENABLE_SPLIT_FIELD                   (_MK_MASK_CONST(0x1) << AHB_GIZMO_SDMMC1_0_ENABLE_SPLIT_SHIFT)
+#define AHB_GIZMO_SDMMC1_0_ENABLE_SPLIT_RANGE                   0:0
+#define AHB_GIZMO_SDMMC1_0_ENABLE_SPLIT_WOFFSET                 0x0
+#define AHB_GIZMO_SDMMC1_0_ENABLE_SPLIT_DEFAULT                 _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_SDMMC1_0_ENABLE_SPLIT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_SDMMC1_0_ENABLE_SPLIT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC1_0_ENABLE_SPLIT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC1_0_ENABLE_SPLIT_DISABLE                 _MK_ENUM_CONST(0)
+#define AHB_GIZMO_SDMMC1_0_ENABLE_SPLIT_ENABLE                  _MK_ENUM_CONST(1)
+
+
+// Register AHB_GIZMO_SDMMC2_0  
+#define AHB_GIZMO_SDMMC2_0                      _MK_ADDR_CONST(0x84)
+#define AHB_GIZMO_SDMMC2_0_SECURE                       0x0
+#define AHB_GIZMO_SDMMC2_0_WORD_COUNT                   0x1
+#define AHB_GIZMO_SDMMC2_0_RESET_VAL                    _MK_MASK_CONST(0x20087)
+#define AHB_GIZMO_SDMMC2_0_RESET_MASK                   _MK_MASK_CONST(0xff0700c7)
+#define AHB_GIZMO_SDMMC2_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC2_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC2_0_READ_MASK                    _MK_MASK_CONST(0xff0700c7)
+#define AHB_GIZMO_SDMMC2_0_WRITE_MASK                   _MK_MASK_CONST(0xff0700c7)
+// AHB master request negate count. This is an 8-bit  counter use to indicate the minimum number of clk count between requests from  this AHB master.
+#define AHB_GIZMO_SDMMC2_0_REQ_NEG_CNT_SHIFT                    _MK_SHIFT_CONST(24)
+#define AHB_GIZMO_SDMMC2_0_REQ_NEG_CNT_FIELD                    (_MK_MASK_CONST(0xff) << AHB_GIZMO_SDMMC2_0_REQ_NEG_CNT_SHIFT)
+#define AHB_GIZMO_SDMMC2_0_REQ_NEG_CNT_RANGE                    31:24
+#define AHB_GIZMO_SDMMC2_0_REQ_NEG_CNT_WOFFSET                  0x0
+#define AHB_GIZMO_SDMMC2_0_REQ_NEG_CNT_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC2_0_REQ_NEG_CNT_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
+#define AHB_GIZMO_SDMMC2_0_REQ_NEG_CNT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC2_0_REQ_NEG_CNT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+//AHB master gizmo - Start AHB write request immediately.  1 = start the AHB write request immediately as soon as the device puts data in the AHB gizmos queue.  0 = start the AHB write request only when all the  write data has transferred from the device to the AHB gizmos queue.
+#define AHB_GIZMO_SDMMC2_0_IMMEDIATE_SHIFT                      _MK_SHIFT_CONST(18)
+#define AHB_GIZMO_SDMMC2_0_IMMEDIATE_FIELD                      (_MK_MASK_CONST(0x1) << AHB_GIZMO_SDMMC2_0_IMMEDIATE_SHIFT)
+#define AHB_GIZMO_SDMMC2_0_IMMEDIATE_RANGE                      18:18
+#define AHB_GIZMO_SDMMC2_0_IMMEDIATE_WOFFSET                    0x0
+#define AHB_GIZMO_SDMMC2_0_IMMEDIATE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC2_0_IMMEDIATE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_SDMMC2_0_IMMEDIATE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC2_0_IMMEDIATE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC2_0_IMMEDIATE_DISABLE                    _MK_ENUM_CONST(0)
+#define AHB_GIZMO_SDMMC2_0_IMMEDIATE_ENABLE                     _MK_ENUM_CONST(1)
+
+//AHB master gizmo - Maximum allowed AHB burst size.  00 = single transfer.  01 = burst-of-4.  10 = burst-of-8.  11 = burst-of-16.
+#define AHB_GIZMO_SDMMC2_0_MAX_AHB_BURSTSIZE_SHIFT                      _MK_SHIFT_CONST(16)
+#define AHB_GIZMO_SDMMC2_0_MAX_AHB_BURSTSIZE_FIELD                      (_MK_MASK_CONST(0x3) << AHB_GIZMO_SDMMC2_0_MAX_AHB_BURSTSIZE_SHIFT)
+#define AHB_GIZMO_SDMMC2_0_MAX_AHB_BURSTSIZE_RANGE                      17:16
+#define AHB_GIZMO_SDMMC2_0_MAX_AHB_BURSTSIZE_WOFFSET                    0x0
+#define AHB_GIZMO_SDMMC2_0_MAX_AHB_BURSTSIZE_DEFAULT                    _MK_MASK_CONST(0x2)
+#define AHB_GIZMO_SDMMC2_0_MAX_AHB_BURSTSIZE_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define AHB_GIZMO_SDMMC2_0_MAX_AHB_BURSTSIZE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC2_0_MAX_AHB_BURSTSIZE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC2_0_MAX_AHB_BURSTSIZE_DMA_BURST_1WORDS                   _MK_ENUM_CONST(0)
+#define AHB_GIZMO_SDMMC2_0_MAX_AHB_BURSTSIZE_DMA_BURST_4WORDS                   _MK_ENUM_CONST(1)
+#define AHB_GIZMO_SDMMC2_0_MAX_AHB_BURSTSIZE_DMA_BURST_8WORDS                   _MK_ENUM_CONST(2)
+#define AHB_GIZMO_SDMMC2_0_MAX_AHB_BURSTSIZE_DMA_BURST_16WORDS                  _MK_ENUM_CONST(3)
+
+//AHB slave gizmo - Dont split AHB write transaction.  1 = dont split AHB write transaction ever. 0 (and enable_split=1) = allow AHB write  transaction to be split.
+#define AHB_GIZMO_SDMMC2_0_DONT_SPLIT_AHB_WR_SHIFT                      _MK_SHIFT_CONST(7)
+#define AHB_GIZMO_SDMMC2_0_DONT_SPLIT_AHB_WR_FIELD                      (_MK_MASK_CONST(0x1) << AHB_GIZMO_SDMMC2_0_DONT_SPLIT_AHB_WR_SHIFT)
+#define AHB_GIZMO_SDMMC2_0_DONT_SPLIT_AHB_WR_RANGE                      7:7
+#define AHB_GIZMO_SDMMC2_0_DONT_SPLIT_AHB_WR_WOFFSET                    0x0
+#define AHB_GIZMO_SDMMC2_0_DONT_SPLIT_AHB_WR_DEFAULT                    _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_SDMMC2_0_DONT_SPLIT_AHB_WR_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_SDMMC2_0_DONT_SPLIT_AHB_WR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC2_0_DONT_SPLIT_AHB_WR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC2_0_DONT_SPLIT_AHB_WR_ENABLE                     _MK_ENUM_CONST(0)
+#define AHB_GIZMO_SDMMC2_0_DONT_SPLIT_AHB_WR_DISABLE                    _MK_ENUM_CONST(1)
+
+//AHB slave gizmo - Accept AHB write request always.  1 = always accept AHB write request without checking whether there is room in the queue to store the write data. 0 = accept AHB write request only when theres  enough room in the queue to store all the write data.
+#define AHB_GIZMO_SDMMC2_0_ACCEPT_AHB_WR_ALWAYS_SHIFT                   _MK_SHIFT_CONST(6)
+#define AHB_GIZMO_SDMMC2_0_ACCEPT_AHB_WR_ALWAYS_FIELD                   (_MK_MASK_CONST(0x1) << AHB_GIZMO_SDMMC2_0_ACCEPT_AHB_WR_ALWAYS_SHIFT)
+#define AHB_GIZMO_SDMMC2_0_ACCEPT_AHB_WR_ALWAYS_RANGE                   6:6
+#define AHB_GIZMO_SDMMC2_0_ACCEPT_AHB_WR_ALWAYS_WOFFSET                 0x0
+#define AHB_GIZMO_SDMMC2_0_ACCEPT_AHB_WR_ALWAYS_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC2_0_ACCEPT_AHB_WR_ALWAYS_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_SDMMC2_0_ACCEPT_AHB_WR_ALWAYS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC2_0_ACCEPT_AHB_WR_ALWAYS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC2_0_ACCEPT_AHB_WR_ALWAYS_ACCEPT_ON_CHECK                 _MK_ENUM_CONST(0)
+#define AHB_GIZMO_SDMMC2_0_ACCEPT_AHB_WR_ALWAYS_ACCEPT_ON_NOCHECK                       _MK_ENUM_CONST(1)
+
+//AHB slave gizmo - Enable fast re-arbitration.  1 = allow AHB master re-arbitration as soon as the device returns one read data into the gizmos queue. 0 = allow AHB master re-arbitration only when the  device returns all read data into the gizmos queue.
+#define AHB_GIZMO_SDMMC2_0_ENB_FAST_REARBITRATE_SHIFT                   _MK_SHIFT_CONST(2)
+#define AHB_GIZMO_SDMMC2_0_ENB_FAST_REARBITRATE_FIELD                   (_MK_MASK_CONST(0x1) << AHB_GIZMO_SDMMC2_0_ENB_FAST_REARBITRATE_SHIFT)
+#define AHB_GIZMO_SDMMC2_0_ENB_FAST_REARBITRATE_RANGE                   2:2
+#define AHB_GIZMO_SDMMC2_0_ENB_FAST_REARBITRATE_WOFFSET                 0x0
+#define AHB_GIZMO_SDMMC2_0_ENB_FAST_REARBITRATE_DEFAULT                 _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_SDMMC2_0_ENB_FAST_REARBITRATE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_SDMMC2_0_ENB_FAST_REARBITRATE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC2_0_ENB_FAST_REARBITRATE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC2_0_ENB_FAST_REARBITRATE_DISABLE                 _MK_ENUM_CONST(0)
+#define AHB_GIZMO_SDMMC2_0_ENB_FAST_REARBITRATE_ENABLE                  _MK_ENUM_CONST(1)
+
+//AHB slave gizmo - Force all AHB transaction to single data request transaction.  1 = force to single data transaction always. 0 = dont force to single data transaction.
+#define AHB_GIZMO_SDMMC2_0_FORCE_TO_AHB_SINGLE_SHIFT                    _MK_SHIFT_CONST(1)
+#define AHB_GIZMO_SDMMC2_0_FORCE_TO_AHB_SINGLE_FIELD                    (_MK_MASK_CONST(0x1) << AHB_GIZMO_SDMMC2_0_FORCE_TO_AHB_SINGLE_SHIFT)
+#define AHB_GIZMO_SDMMC2_0_FORCE_TO_AHB_SINGLE_RANGE                    1:1
+#define AHB_GIZMO_SDMMC2_0_FORCE_TO_AHB_SINGLE_WOFFSET                  0x0
+#define AHB_GIZMO_SDMMC2_0_FORCE_TO_AHB_SINGLE_DEFAULT                  _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_SDMMC2_0_FORCE_TO_AHB_SINGLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_SDMMC2_0_FORCE_TO_AHB_SINGLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC2_0_FORCE_TO_AHB_SINGLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC2_0_FORCE_TO_AHB_SINGLE_NOT_SINGLE_DATA                  _MK_ENUM_CONST(0)
+#define AHB_GIZMO_SDMMC2_0_FORCE_TO_AHB_SINGLE_SINGLE_DATA                      _MK_ENUM_CONST(1)
+
+//AHB slave gizmo - Enable splitting AHB transactions.  1 = enable  0 = disable
+#define AHB_GIZMO_SDMMC2_0_ENABLE_SPLIT_SHIFT                   _MK_SHIFT_CONST(0)
+#define AHB_GIZMO_SDMMC2_0_ENABLE_SPLIT_FIELD                   (_MK_MASK_CONST(0x1) << AHB_GIZMO_SDMMC2_0_ENABLE_SPLIT_SHIFT)
+#define AHB_GIZMO_SDMMC2_0_ENABLE_SPLIT_RANGE                   0:0
+#define AHB_GIZMO_SDMMC2_0_ENABLE_SPLIT_WOFFSET                 0x0
+#define AHB_GIZMO_SDMMC2_0_ENABLE_SPLIT_DEFAULT                 _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_SDMMC2_0_ENABLE_SPLIT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_SDMMC2_0_ENABLE_SPLIT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC2_0_ENABLE_SPLIT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC2_0_ENABLE_SPLIT_DISABLE                 _MK_ENUM_CONST(0)
+#define AHB_GIZMO_SDMMC2_0_ENABLE_SPLIT_ENABLE                  _MK_ENUM_CONST(1)
+
+
+// Register AHB_GIZMO_SDMMC3_0  
+#define AHB_GIZMO_SDMMC3_0                      _MK_ADDR_CONST(0x88)
+#define AHB_GIZMO_SDMMC3_0_SECURE                       0x0
+#define AHB_GIZMO_SDMMC3_0_WORD_COUNT                   0x1
+#define AHB_GIZMO_SDMMC3_0_RESET_VAL                    _MK_MASK_CONST(0x20087)
+#define AHB_GIZMO_SDMMC3_0_RESET_MASK                   _MK_MASK_CONST(0xff0700c7)
+#define AHB_GIZMO_SDMMC3_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC3_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC3_0_READ_MASK                    _MK_MASK_CONST(0xff0700c7)
+#define AHB_GIZMO_SDMMC3_0_WRITE_MASK                   _MK_MASK_CONST(0xff0700c7)
+// AHB master request negate count. This is an 8-bit  counter use to indicate the minimum number of clk count between requests from  this AHB master.
+#define AHB_GIZMO_SDMMC3_0_REQ_NEG_CNT_SHIFT                    _MK_SHIFT_CONST(24)
+#define AHB_GIZMO_SDMMC3_0_REQ_NEG_CNT_FIELD                    (_MK_MASK_CONST(0xff) << AHB_GIZMO_SDMMC3_0_REQ_NEG_CNT_SHIFT)
+#define AHB_GIZMO_SDMMC3_0_REQ_NEG_CNT_RANGE                    31:24
+#define AHB_GIZMO_SDMMC3_0_REQ_NEG_CNT_WOFFSET                  0x0
+#define AHB_GIZMO_SDMMC3_0_REQ_NEG_CNT_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC3_0_REQ_NEG_CNT_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
+#define AHB_GIZMO_SDMMC3_0_REQ_NEG_CNT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC3_0_REQ_NEG_CNT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+//AHB master gizmo - Start AHB write request immediately.  1 = start the AHB write request immediately as soon as the device puts data in the AHB gizmos queue.  0 = start the AHB write request only when all the  write data has transferred from the device to the AHB gizmos queue.
+#define AHB_GIZMO_SDMMC3_0_IMMEDIATE_SHIFT                      _MK_SHIFT_CONST(18)
+#define AHB_GIZMO_SDMMC3_0_IMMEDIATE_FIELD                      (_MK_MASK_CONST(0x1) << AHB_GIZMO_SDMMC3_0_IMMEDIATE_SHIFT)
+#define AHB_GIZMO_SDMMC3_0_IMMEDIATE_RANGE                      18:18
+#define AHB_GIZMO_SDMMC3_0_IMMEDIATE_WOFFSET                    0x0
+#define AHB_GIZMO_SDMMC3_0_IMMEDIATE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC3_0_IMMEDIATE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_SDMMC3_0_IMMEDIATE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC3_0_IMMEDIATE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC3_0_IMMEDIATE_DISABLE                    _MK_ENUM_CONST(0)
+#define AHB_GIZMO_SDMMC3_0_IMMEDIATE_ENABLE                     _MK_ENUM_CONST(1)
+
+//AHB master gizmo - Maximum allowed AHB burst size.  00 = single transfer.  01 = burst-of-4.  10 = burst-of-8.  11 = burst-of-16.
+#define AHB_GIZMO_SDMMC3_0_MAX_AHB_BURSTSIZE_SHIFT                      _MK_SHIFT_CONST(16)
+#define AHB_GIZMO_SDMMC3_0_MAX_AHB_BURSTSIZE_FIELD                      (_MK_MASK_CONST(0x3) << AHB_GIZMO_SDMMC3_0_MAX_AHB_BURSTSIZE_SHIFT)
+#define AHB_GIZMO_SDMMC3_0_MAX_AHB_BURSTSIZE_RANGE                      17:16
+#define AHB_GIZMO_SDMMC3_0_MAX_AHB_BURSTSIZE_WOFFSET                    0x0
+#define AHB_GIZMO_SDMMC3_0_MAX_AHB_BURSTSIZE_DEFAULT                    _MK_MASK_CONST(0x2)
+#define AHB_GIZMO_SDMMC3_0_MAX_AHB_BURSTSIZE_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define AHB_GIZMO_SDMMC3_0_MAX_AHB_BURSTSIZE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC3_0_MAX_AHB_BURSTSIZE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC3_0_MAX_AHB_BURSTSIZE_DMA_BURST_1WORDS                   _MK_ENUM_CONST(0)
+#define AHB_GIZMO_SDMMC3_0_MAX_AHB_BURSTSIZE_DMA_BURST_4WORDS                   _MK_ENUM_CONST(1)
+#define AHB_GIZMO_SDMMC3_0_MAX_AHB_BURSTSIZE_DMA_BURST_8WORDS                   _MK_ENUM_CONST(2)
+#define AHB_GIZMO_SDMMC3_0_MAX_AHB_BURSTSIZE_DMA_BURST_16WORDS                  _MK_ENUM_CONST(3)
+
+//AHB slave gizmo - Dont split AHB write transaction.  1 = dont split AHB write transaction ever. 0 (and enable_split=1) = allow AHB write  transaction to be split.
+#define AHB_GIZMO_SDMMC3_0_DONT_SPLIT_AHB_WR_SHIFT                      _MK_SHIFT_CONST(7)
+#define AHB_GIZMO_SDMMC3_0_DONT_SPLIT_AHB_WR_FIELD                      (_MK_MASK_CONST(0x1) << AHB_GIZMO_SDMMC3_0_DONT_SPLIT_AHB_WR_SHIFT)
+#define AHB_GIZMO_SDMMC3_0_DONT_SPLIT_AHB_WR_RANGE                      7:7
+#define AHB_GIZMO_SDMMC3_0_DONT_SPLIT_AHB_WR_WOFFSET                    0x0
+#define AHB_GIZMO_SDMMC3_0_DONT_SPLIT_AHB_WR_DEFAULT                    _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_SDMMC3_0_DONT_SPLIT_AHB_WR_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_SDMMC3_0_DONT_SPLIT_AHB_WR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC3_0_DONT_SPLIT_AHB_WR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC3_0_DONT_SPLIT_AHB_WR_ENABLE                     _MK_ENUM_CONST(0)
+#define AHB_GIZMO_SDMMC3_0_DONT_SPLIT_AHB_WR_DISABLE                    _MK_ENUM_CONST(1)
+
+//AHB slave gizmo - Accept AHB write request always.  1 = always accept AHB write request without checking whether there is room in the queue to store the write data. 0 = accept AHB write request only when theres  enough room in the queue to store all the write data.
+#define AHB_GIZMO_SDMMC3_0_ACCEPT_AHB_WR_ALWAYS_SHIFT                   _MK_SHIFT_CONST(6)
+#define AHB_GIZMO_SDMMC3_0_ACCEPT_AHB_WR_ALWAYS_FIELD                   (_MK_MASK_CONST(0x1) << AHB_GIZMO_SDMMC3_0_ACCEPT_AHB_WR_ALWAYS_SHIFT)
+#define AHB_GIZMO_SDMMC3_0_ACCEPT_AHB_WR_ALWAYS_RANGE                   6:6
+#define AHB_GIZMO_SDMMC3_0_ACCEPT_AHB_WR_ALWAYS_WOFFSET                 0x0
+#define AHB_GIZMO_SDMMC3_0_ACCEPT_AHB_WR_ALWAYS_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC3_0_ACCEPT_AHB_WR_ALWAYS_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_SDMMC3_0_ACCEPT_AHB_WR_ALWAYS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC3_0_ACCEPT_AHB_WR_ALWAYS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC3_0_ACCEPT_AHB_WR_ALWAYS_ACCEPT_ON_CHECK                 _MK_ENUM_CONST(0)
+#define AHB_GIZMO_SDMMC3_0_ACCEPT_AHB_WR_ALWAYS_ACCEPT_ON_NOCHECK                       _MK_ENUM_CONST(1)
+
+//AHB slave gizmo - Enable fast re-arbitration.  1 = allow AHB master re-arbitration as soon as the device returns one read data into the gizmos queue. 0 = allow AHB master re-arbitration only when the  device returns all read data into the gizmos queue.
+#define AHB_GIZMO_SDMMC3_0_ENB_FAST_REARBITRATE_SHIFT                   _MK_SHIFT_CONST(2)
+#define AHB_GIZMO_SDMMC3_0_ENB_FAST_REARBITRATE_FIELD                   (_MK_MASK_CONST(0x1) << AHB_GIZMO_SDMMC3_0_ENB_FAST_REARBITRATE_SHIFT)
+#define AHB_GIZMO_SDMMC3_0_ENB_FAST_REARBITRATE_RANGE                   2:2
+#define AHB_GIZMO_SDMMC3_0_ENB_FAST_REARBITRATE_WOFFSET                 0x0
+#define AHB_GIZMO_SDMMC3_0_ENB_FAST_REARBITRATE_DEFAULT                 _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_SDMMC3_0_ENB_FAST_REARBITRATE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_SDMMC3_0_ENB_FAST_REARBITRATE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC3_0_ENB_FAST_REARBITRATE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC3_0_ENB_FAST_REARBITRATE_DISABLE                 _MK_ENUM_CONST(0)
+#define AHB_GIZMO_SDMMC3_0_ENB_FAST_REARBITRATE_ENABLE                  _MK_ENUM_CONST(1)
+
+//AHB slave gizmo - Force all AHB transaction to single data request transaction.  1 = force to single data transaction always. 0 = dont force to single data transaction.
+#define AHB_GIZMO_SDMMC3_0_FORCE_TO_AHB_SINGLE_SHIFT                    _MK_SHIFT_CONST(1)
+#define AHB_GIZMO_SDMMC3_0_FORCE_TO_AHB_SINGLE_FIELD                    (_MK_MASK_CONST(0x1) << AHB_GIZMO_SDMMC3_0_FORCE_TO_AHB_SINGLE_SHIFT)
+#define AHB_GIZMO_SDMMC3_0_FORCE_TO_AHB_SINGLE_RANGE                    1:1
+#define AHB_GIZMO_SDMMC3_0_FORCE_TO_AHB_SINGLE_WOFFSET                  0x0
+#define AHB_GIZMO_SDMMC3_0_FORCE_TO_AHB_SINGLE_DEFAULT                  _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_SDMMC3_0_FORCE_TO_AHB_SINGLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_SDMMC3_0_FORCE_TO_AHB_SINGLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC3_0_FORCE_TO_AHB_SINGLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC3_0_FORCE_TO_AHB_SINGLE_NOT_SINGLE_DATA                  _MK_ENUM_CONST(0)
+#define AHB_GIZMO_SDMMC3_0_FORCE_TO_AHB_SINGLE_SINGLE_DATA                      _MK_ENUM_CONST(1)
+
+//AHB slave gizmo - Enable splitting AHB transactions.  1 = enable  0 = disable
+#define AHB_GIZMO_SDMMC3_0_ENABLE_SPLIT_SHIFT                   _MK_SHIFT_CONST(0)
+#define AHB_GIZMO_SDMMC3_0_ENABLE_SPLIT_FIELD                   (_MK_MASK_CONST(0x1) << AHB_GIZMO_SDMMC3_0_ENABLE_SPLIT_SHIFT)
+#define AHB_GIZMO_SDMMC3_0_ENABLE_SPLIT_RANGE                   0:0
+#define AHB_GIZMO_SDMMC3_0_ENABLE_SPLIT_WOFFSET                 0x0
+#define AHB_GIZMO_SDMMC3_0_ENABLE_SPLIT_DEFAULT                 _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_SDMMC3_0_ENABLE_SPLIT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_SDMMC3_0_ENABLE_SPLIT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC3_0_ENABLE_SPLIT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC3_0_ENABLE_SPLIT_DISABLE                 _MK_ENUM_CONST(0)
+#define AHB_GIZMO_SDMMC3_0_ENABLE_SPLIT_ENABLE                  _MK_ENUM_CONST(1)
+
+
+// Reserved address 140 [0x8c] 
+
+// Reserved address 144 [0x90] 
+
+// Reserved address 148 [0x94] 
+
+// Reserved address 152 [0x98] 
+
+// Reserved address 156 [0x9c] 
+
+// Reserved address 160 [0xa0] 
+
+// Reserved address 164 [0xa4] 
+
+// Reserved address 168 [0xa8] 
+
+// Reserved address 172 [0xac] 
+
+// Reserved address 176 [0xb0] 
+
+// Reserved address 180 [0xb4] 
+
+// Reserved address 184 [0xb8] 
+
+// Reserved address 188 [0xbc] 
+
+// Reserved address 192 [0xc0] 
+
+// Reserved address 196 [0xc4] 
+
+// Reserved address 200 [0xc8] 
+
+// Reserved address 204 [0xcc] 
+
+// Reserved address 208 [0xd0] 
+
+// Reserved address 212 [0xd4] 
+
+// Register AHB_AHB_MEM_PREFETCH_CFG_X_0  
+#define AHB_AHB_MEM_PREFETCH_CFG_X_0                    _MK_ADDR_CONST(0xd8)
+#define AHB_AHB_MEM_PREFETCH_CFG_X_0_SECURE                     0x0
+#define AHB_AHB_MEM_PREFETCH_CFG_X_0_WORD_COUNT                         0x1
+#define AHB_AHB_MEM_PREFETCH_CFG_X_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG_X_0_RESET_MASK                         _MK_MASK_CONST(0xf)
+#define AHB_AHB_MEM_PREFETCH_CFG_X_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG_X_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG_X_0_READ_MASK                  _MK_MASK_CONST(0xf)
+#define AHB_AHB_MEM_PREFETCH_CFG_X_0_WRITE_MASK                         _MK_MASK_CONST(0xf)
+// 
+#define AHB_AHB_MEM_PREFETCH_CFG_X_0_DISABLE_CHECK_SIZE_MASTER1_SHIFT                   _MK_SHIFT_CONST(0)
+#define AHB_AHB_MEM_PREFETCH_CFG_X_0_DISABLE_CHECK_SIZE_MASTER1_FIELD                   (_MK_MASK_CONST(0x1) << AHB_AHB_MEM_PREFETCH_CFG_X_0_DISABLE_CHECK_SIZE_MASTER1_SHIFT)
+#define AHB_AHB_MEM_PREFETCH_CFG_X_0_DISABLE_CHECK_SIZE_MASTER1_RANGE                   0:0
+#define AHB_AHB_MEM_PREFETCH_CFG_X_0_DISABLE_CHECK_SIZE_MASTER1_WOFFSET                 0x0
+#define AHB_AHB_MEM_PREFETCH_CFG_X_0_DISABLE_CHECK_SIZE_MASTER1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG_X_0_DISABLE_CHECK_SIZE_MASTER1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define AHB_AHB_MEM_PREFETCH_CFG_X_0_DISABLE_CHECK_SIZE_MASTER1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG_X_0_DISABLE_CHECK_SIZE_MASTER1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// 
+#define AHB_AHB_MEM_PREFETCH_CFG_X_0_DISABLE_CHECK_SIZE_MASTER2_SHIFT                   _MK_SHIFT_CONST(1)
+#define AHB_AHB_MEM_PREFETCH_CFG_X_0_DISABLE_CHECK_SIZE_MASTER2_FIELD                   (_MK_MASK_CONST(0x1) << AHB_AHB_MEM_PREFETCH_CFG_X_0_DISABLE_CHECK_SIZE_MASTER2_SHIFT)
+#define AHB_AHB_MEM_PREFETCH_CFG_X_0_DISABLE_CHECK_SIZE_MASTER2_RANGE                   1:1
+#define AHB_AHB_MEM_PREFETCH_CFG_X_0_DISABLE_CHECK_SIZE_MASTER2_WOFFSET                 0x0
+#define AHB_AHB_MEM_PREFETCH_CFG_X_0_DISABLE_CHECK_SIZE_MASTER2_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG_X_0_DISABLE_CHECK_SIZE_MASTER2_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define AHB_AHB_MEM_PREFETCH_CFG_X_0_DISABLE_CHECK_SIZE_MASTER2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG_X_0_DISABLE_CHECK_SIZE_MASTER2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// 
+#define AHB_AHB_MEM_PREFETCH_CFG_X_0_DISABLE_CHECK_SIZE_MASTER3_SHIFT                   _MK_SHIFT_CONST(2)
+#define AHB_AHB_MEM_PREFETCH_CFG_X_0_DISABLE_CHECK_SIZE_MASTER3_FIELD                   (_MK_MASK_CONST(0x1) << AHB_AHB_MEM_PREFETCH_CFG_X_0_DISABLE_CHECK_SIZE_MASTER3_SHIFT)
+#define AHB_AHB_MEM_PREFETCH_CFG_X_0_DISABLE_CHECK_SIZE_MASTER3_RANGE                   2:2
+#define AHB_AHB_MEM_PREFETCH_CFG_X_0_DISABLE_CHECK_SIZE_MASTER3_WOFFSET                 0x0
+#define AHB_AHB_MEM_PREFETCH_CFG_X_0_DISABLE_CHECK_SIZE_MASTER3_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG_X_0_DISABLE_CHECK_SIZE_MASTER3_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define AHB_AHB_MEM_PREFETCH_CFG_X_0_DISABLE_CHECK_SIZE_MASTER3_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG_X_0_DISABLE_CHECK_SIZE_MASTER3_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// 
+#define AHB_AHB_MEM_PREFETCH_CFG_X_0_DISABLE_CHECK_SIZE_MASTER4_SHIFT                   _MK_SHIFT_CONST(3)
+#define AHB_AHB_MEM_PREFETCH_CFG_X_0_DISABLE_CHECK_SIZE_MASTER4_FIELD                   (_MK_MASK_CONST(0x1) << AHB_AHB_MEM_PREFETCH_CFG_X_0_DISABLE_CHECK_SIZE_MASTER4_SHIFT)
+#define AHB_AHB_MEM_PREFETCH_CFG_X_0_DISABLE_CHECK_SIZE_MASTER4_RANGE                   3:3
+#define AHB_AHB_MEM_PREFETCH_CFG_X_0_DISABLE_CHECK_SIZE_MASTER4_WOFFSET                 0x0
+#define AHB_AHB_MEM_PREFETCH_CFG_X_0_DISABLE_CHECK_SIZE_MASTER4_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG_X_0_DISABLE_CHECK_SIZE_MASTER4_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define AHB_AHB_MEM_PREFETCH_CFG_X_0_DISABLE_CHECK_SIZE_MASTER4_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG_X_0_DISABLE_CHECK_SIZE_MASTER4_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register AHB_ARBITRATION_XBAR_CTRL_0  
+#define AHB_ARBITRATION_XBAR_CTRL_0                     _MK_ADDR_CONST(0xdc)
+#define AHB_ARBITRATION_XBAR_CTRL_0_SECURE                      0x0
+#define AHB_ARBITRATION_XBAR_CTRL_0_WORD_COUNT                  0x1
+#define AHB_ARBITRATION_XBAR_CTRL_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_XBAR_CTRL_0_RESET_MASK                  _MK_MASK_CONST(0x10003)
+#define AHB_ARBITRATION_XBAR_CTRL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_XBAR_CTRL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_XBAR_CTRL_0_READ_MASK                   _MK_MASK_CONST(0x10003)
+#define AHB_ARBITRATION_XBAR_CTRL_0_WRITE_MASK                  _MK_MASK_CONST(0x10003)
+// SW should set this bit when memory has been initialized
+#define AHB_ARBITRATION_XBAR_CTRL_0_MEM_INIT_DONE_SHIFT                 _MK_SHIFT_CONST(16)
+#define AHB_ARBITRATION_XBAR_CTRL_0_MEM_INIT_DONE_FIELD                 (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_XBAR_CTRL_0_MEM_INIT_DONE_SHIFT)
+#define AHB_ARBITRATION_XBAR_CTRL_0_MEM_INIT_DONE_RANGE                 16:16
+#define AHB_ARBITRATION_XBAR_CTRL_0_MEM_INIT_DONE_WOFFSET                       0x0
+#define AHB_ARBITRATION_XBAR_CTRL_0_MEM_INIT_DONE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_XBAR_CTRL_0_MEM_INIT_DONE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_XBAR_CTRL_0_MEM_INIT_DONE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_XBAR_CTRL_0_MEM_INIT_DONE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_XBAR_CTRL_0_MEM_INIT_DONE_NOT_DONE                      _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_XBAR_CTRL_0_MEM_INIT_DONE_DONE                  _MK_ENUM_CONST(1)
+
+// By default CPU accesses to IRAMs will be held if  there are any pending requests from the AHB to the 
+// IRAMs. This is done to  avoid data coherency issues. If SW handles coherency then this can be turned  
+// off to improve performance.SW writes to modify
+#define AHB_ARBITRATION_XBAR_CTRL_0_HOLD_DIS_SHIFT                      _MK_SHIFT_CONST(1)
+#define AHB_ARBITRATION_XBAR_CTRL_0_HOLD_DIS_FIELD                      (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_XBAR_CTRL_0_HOLD_DIS_SHIFT)
+#define AHB_ARBITRATION_XBAR_CTRL_0_HOLD_DIS_RANGE                      1:1
+#define AHB_ARBITRATION_XBAR_CTRL_0_HOLD_DIS_WOFFSET                    0x0
+#define AHB_ARBITRATION_XBAR_CTRL_0_HOLD_DIS_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_XBAR_CTRL_0_HOLD_DIS_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_XBAR_CTRL_0_HOLD_DIS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_XBAR_CTRL_0_HOLD_DIS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_XBAR_CTRL_0_HOLD_DIS_ENABLE                     _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_XBAR_CTRL_0_HOLD_DIS_DISABLE                    _MK_ENUM_CONST(1)
+
+// SW writes to modify
+#define AHB_ARBITRATION_XBAR_CTRL_0_POST_DIS_SHIFT                      _MK_SHIFT_CONST(0)
+#define AHB_ARBITRATION_XBAR_CTRL_0_POST_DIS_FIELD                      (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_XBAR_CTRL_0_POST_DIS_SHIFT)
+#define AHB_ARBITRATION_XBAR_CTRL_0_POST_DIS_RANGE                      0:0
+#define AHB_ARBITRATION_XBAR_CTRL_0_POST_DIS_WOFFSET                    0x0
+#define AHB_ARBITRATION_XBAR_CTRL_0_POST_DIS_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_XBAR_CTRL_0_POST_DIS_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_XBAR_CTRL_0_POST_DIS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_XBAR_CTRL_0_POST_DIS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_XBAR_CTRL_0_POST_DIS_ENABLE                     _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_XBAR_CTRL_0_POST_DIS_DISABLE                    _MK_ENUM_CONST(1)
+
+
+// Register AHB_AHB_MEM_PREFETCH_CFG3_0  
+#define AHB_AHB_MEM_PREFETCH_CFG3_0                     _MK_ADDR_CONST(0xe0)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_SECURE                      0x0
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_WORD_COUNT                  0x1
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_RESET_VAL                   _MK_MASK_CONST(0x14800800)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_WRITE_MASK                  _MK_MASK_CONST(0xffe0ffff)
+// 1=enable 0=disable
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_ENABLE_SHIFT                        _MK_SHIFT_CONST(31)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_ENABLE_FIELD                        (_MK_MASK_CONST(0x1) << AHB_AHB_MEM_PREFETCH_CFG3_0_ENABLE_SHIFT)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_ENABLE_RANGE                        31:31
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_ENABLE_WOFFSET                      0x0
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// AHBDMA master
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_AHB_MST_ID_SHIFT                    _MK_SHIFT_CONST(26)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_AHB_MST_ID_FIELD                    (_MK_MASK_CONST(0x1f) << AHB_AHB_MEM_PREFETCH_CFG3_0_AHB_MST_ID_SHIFT)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_AHB_MST_ID_RANGE                    30:26
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_AHB_MST_ID_WOFFSET                  0x0
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_AHB_MST_ID_DEFAULT                  _MK_MASK_CONST(0x5)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_AHB_MST_ID_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_AHB_MST_ID_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_AHB_MST_ID_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_AHB_MST_ID_CPU                      _MK_ENUM_CONST(0)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_AHB_MST_ID_COP                      _MK_ENUM_CONST(1)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_AHB_MST_ID_VCP                      _MK_ENUM_CONST(2)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_AHB_MST_ID_UNUSED_03                        _MK_ENUM_CONST(3)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_AHB_MST_ID_IDE                      _MK_ENUM_CONST(4)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_AHB_MST_ID_AHBDMA                   _MK_ENUM_CONST(5)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_AHB_MST_ID_USB                      _MK_ENUM_CONST(6)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_AHB_MST_ID_APBDMA                   _MK_ENUM_CONST(7)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_AHB_MST_ID_XIO                      _MK_ENUM_CONST(8)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_AHB_MST_ID_SDIO1                    _MK_ENUM_CONST(9)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_AHB_MST_ID_SDMMC1                   _MK_ENUM_CONST(9)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_AHB_MST_ID_NAND_FLASH                       _MK_ENUM_CONST(10)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_AHB_MST_ID_SNOR                     _MK_ENUM_CONST(11)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_AHB_MST_ID_HSMMC                    _MK_ENUM_CONST(12)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_AHB_MST_ID_BSEV                     _MK_ENUM_CONST(13)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_AHB_MST_ID_UNUSED_0E                        _MK_ENUM_CONST(14)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_AHB_MST_ID_UNUSED_0F                        _MK_ENUM_CONST(15)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_AHB_MST_ID_SDMMC4                   _MK_ENUM_CONST(12)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_AHB_MST_ID_BSEA                     _MK_ENUM_CONST(16)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_AHB_MST_ID_USB3                     _MK_ENUM_CONST(17)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_AHB_MST_ID_USB2                     _MK_ENUM_CONST(18)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_AHB_MST_ID_SDIO2                    _MK_ENUM_CONST(19)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_AHB_MST_ID_SDMMC2                   _MK_ENUM_CONST(19)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_AHB_MST_ID_SDMMC3                   _MK_ENUM_CONST(20)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_AHB_MST_ID_UNUSED_15                        _MK_ENUM_CONST(21)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_AHB_MST_ID_UNUSED_16                        _MK_ENUM_CONST(22)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_AHB_MST_ID_UNUSED_17                        _MK_ENUM_CONST(23)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_AHB_MST_ID_UNUSED_18                        _MK_ENUM_CONST(24)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_AHB_MST_ID_UNUSED_19                        _MK_ENUM_CONST(25)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_AHB_MST_ID_UNUSED_1A                        _MK_ENUM_CONST(26)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_AHB_MST_ID_UNUSED_1B                        _MK_ENUM_CONST(27)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_AHB_MST_ID_UNUSED_1C                        _MK_ENUM_CONST(28)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_AHB_MST_ID_UNUSED_1D                        _MK_ENUM_CONST(29)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_AHB_MST_ID_UNUSED_1E                        _MK_ENUM_CONST(30)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_AHB_MST_ID_UNUSED_1F                        _MK_ENUM_CONST(31)
+
+// 2^(n+4) byte boundary. any value >16 will use n=16
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_ADDR_BNDRY_SHIFT                    _MK_SHIFT_CONST(21)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_ADDR_BNDRY_FIELD                    (_MK_MASK_CONST(0x1f) << AHB_AHB_MEM_PREFETCH_CFG3_0_ADDR_BNDRY_SHIFT)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_ADDR_BNDRY_RANGE                    25:21
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_ADDR_BNDRY_WOFFSET                  0x0
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_ADDR_BNDRY_DEFAULT                  _MK_MASK_CONST(0x4)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_ADDR_BNDRY_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_ADDR_BNDRY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_ADDR_BNDRY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// not used for AP-20 and beyond (last used in AP15)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_SPEC_THROTTLE_SHIFT                 _MK_SHIFT_CONST(16)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_SPEC_THROTTLE_FIELD                 (_MK_MASK_CONST(0x1f) << AHB_AHB_MEM_PREFETCH_CFG3_0_SPEC_THROTTLE_SHIFT)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_SPEC_THROTTLE_RANGE                 20:16
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_SPEC_THROTTLE_WOFFSET                       0x0
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_SPEC_THROTTLE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_SPEC_THROTTLE_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_SPEC_THROTTLE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_SPEC_THROTTLE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// 2048 cycles
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_INACTIVITY_TIMEOUT_SHIFT                    _MK_SHIFT_CONST(0)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_INACTIVITY_TIMEOUT_FIELD                    (_MK_MASK_CONST(0xffff) << AHB_AHB_MEM_PREFETCH_CFG3_0_INACTIVITY_TIMEOUT_SHIFT)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_INACTIVITY_TIMEOUT_RANGE                    15:0
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_INACTIVITY_TIMEOUT_WOFFSET                  0x0
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_INACTIVITY_TIMEOUT_DEFAULT                  _MK_MASK_CONST(0x800)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_INACTIVITY_TIMEOUT_DEFAULT_MASK                     _MK_MASK_CONST(0xffff)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_INACTIVITY_TIMEOUT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_INACTIVITY_TIMEOUT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register AHB_AHB_MEM_PREFETCH_CFG4_0  
+#define AHB_AHB_MEM_PREFETCH_CFG4_0                     _MK_ADDR_CONST(0xe4)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_SECURE                      0x0
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_WORD_COUNT                  0x1
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_RESET_VAL                   _MK_MASK_CONST(0x14800800)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_WRITE_MASK                  _MK_MASK_CONST(0xffe0ffff)
+// 1=enable 0=disable
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_ENABLE_SHIFT                        _MK_SHIFT_CONST(31)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_ENABLE_FIELD                        (_MK_MASK_CONST(0x1) << AHB_AHB_MEM_PREFETCH_CFG4_0_ENABLE_SHIFT)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_ENABLE_RANGE                        31:31
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_ENABLE_WOFFSET                      0x0
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// AHBDMA master
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_AHB_MST_ID_SHIFT                    _MK_SHIFT_CONST(26)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_AHB_MST_ID_FIELD                    (_MK_MASK_CONST(0x1f) << AHB_AHB_MEM_PREFETCH_CFG4_0_AHB_MST_ID_SHIFT)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_AHB_MST_ID_RANGE                    30:26
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_AHB_MST_ID_WOFFSET                  0x0
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_AHB_MST_ID_DEFAULT                  _MK_MASK_CONST(0x5)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_AHB_MST_ID_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_AHB_MST_ID_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_AHB_MST_ID_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_AHB_MST_ID_CPU                      _MK_ENUM_CONST(0)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_AHB_MST_ID_COP                      _MK_ENUM_CONST(1)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_AHB_MST_ID_VCP                      _MK_ENUM_CONST(2)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_AHB_MST_ID_UNUSED_03                        _MK_ENUM_CONST(3)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_AHB_MST_ID_IDE                      _MK_ENUM_CONST(4)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_AHB_MST_ID_AHBDMA                   _MK_ENUM_CONST(5)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_AHB_MST_ID_USB                      _MK_ENUM_CONST(6)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_AHB_MST_ID_APBDMA                   _MK_ENUM_CONST(7)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_AHB_MST_ID_XIO                      _MK_ENUM_CONST(8)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_AHB_MST_ID_SDIO1                    _MK_ENUM_CONST(9)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_AHB_MST_ID_SDMMC1                   _MK_ENUM_CONST(9)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_AHB_MST_ID_NAND_FLASH                       _MK_ENUM_CONST(10)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_AHB_MST_ID_SNOR                     _MK_ENUM_CONST(11)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_AHB_MST_ID_HSMMC                    _MK_ENUM_CONST(12)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_AHB_MST_ID_BSEV                     _MK_ENUM_CONST(13)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_AHB_MST_ID_UNUSED_0E                        _MK_ENUM_CONST(14)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_AHB_MST_ID_UNUSED_0F                        _MK_ENUM_CONST(15)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_AHB_MST_ID_SDMMC4                   _MK_ENUM_CONST(12)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_AHB_MST_ID_BSEA                     _MK_ENUM_CONST(16)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_AHB_MST_ID_USB3                     _MK_ENUM_CONST(17)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_AHB_MST_ID_USB2                     _MK_ENUM_CONST(18)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_AHB_MST_ID_SDIO2                    _MK_ENUM_CONST(19)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_AHB_MST_ID_SDMMC2                   _MK_ENUM_CONST(19)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_AHB_MST_ID_SDMMC3                   _MK_ENUM_CONST(20)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_AHB_MST_ID_UNUSED_15                        _MK_ENUM_CONST(21)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_AHB_MST_ID_UNUSED_16                        _MK_ENUM_CONST(22)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_AHB_MST_ID_UNUSED_17                        _MK_ENUM_CONST(23)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_AHB_MST_ID_UNUSED_18                        _MK_ENUM_CONST(24)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_AHB_MST_ID_UNUSED_19                        _MK_ENUM_CONST(25)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_AHB_MST_ID_UNUSED_1A                        _MK_ENUM_CONST(26)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_AHB_MST_ID_UNUSED_1B                        _MK_ENUM_CONST(27)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_AHB_MST_ID_UNUSED_1C                        _MK_ENUM_CONST(28)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_AHB_MST_ID_UNUSED_1D                        _MK_ENUM_CONST(29)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_AHB_MST_ID_UNUSED_1E                        _MK_ENUM_CONST(30)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_AHB_MST_ID_UNUSED_1F                        _MK_ENUM_CONST(31)
+
+// 2^(n+4) byte boundary. any value >16 will use n=16
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_ADDR_BNDRY_SHIFT                    _MK_SHIFT_CONST(21)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_ADDR_BNDRY_FIELD                    (_MK_MASK_CONST(0x1f) << AHB_AHB_MEM_PREFETCH_CFG4_0_ADDR_BNDRY_SHIFT)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_ADDR_BNDRY_RANGE                    25:21
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_ADDR_BNDRY_WOFFSET                  0x0
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_ADDR_BNDRY_DEFAULT                  _MK_MASK_CONST(0x4)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_ADDR_BNDRY_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_ADDR_BNDRY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_ADDR_BNDRY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// not used for AP-20 and beyond (last used in AP15)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_SPEC_THROTTLE_SHIFT                 _MK_SHIFT_CONST(16)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_SPEC_THROTTLE_FIELD                 (_MK_MASK_CONST(0x1f) << AHB_AHB_MEM_PREFETCH_CFG4_0_SPEC_THROTTLE_SHIFT)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_SPEC_THROTTLE_RANGE                 20:16
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_SPEC_THROTTLE_WOFFSET                       0x0
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_SPEC_THROTTLE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_SPEC_THROTTLE_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_SPEC_THROTTLE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_SPEC_THROTTLE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// 2048 cycles
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_INACTIVITY_TIMEOUT_SHIFT                    _MK_SHIFT_CONST(0)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_INACTIVITY_TIMEOUT_FIELD                    (_MK_MASK_CONST(0xffff) << AHB_AHB_MEM_PREFETCH_CFG4_0_INACTIVITY_TIMEOUT_SHIFT)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_INACTIVITY_TIMEOUT_RANGE                    15:0
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_INACTIVITY_TIMEOUT_WOFFSET                  0x0
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_INACTIVITY_TIMEOUT_DEFAULT                  _MK_MASK_CONST(0x800)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_INACTIVITY_TIMEOUT_DEFAULT_MASK                     _MK_MASK_CONST(0xffff)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_INACTIVITY_TIMEOUT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_INACTIVITY_TIMEOUT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register AHB_AVP_PPCS_RD_COH_STATUS_0  
+#define AHB_AVP_PPCS_RD_COH_STATUS_0                    _MK_ADDR_CONST(0xe8)
+#define AHB_AVP_PPCS_RD_COH_STATUS_0_SECURE                     0x0
+#define AHB_AVP_PPCS_RD_COH_STATUS_0_WORD_COUNT                         0x1
+#define AHB_AVP_PPCS_RD_COH_STATUS_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define AHB_AVP_PPCS_RD_COH_STATUS_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define AHB_AVP_PPCS_RD_COH_STATUS_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define AHB_AVP_PPCS_RD_COH_STATUS_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AHB_AVP_PPCS_RD_COH_STATUS_0_READ_MASK                  _MK_MASK_CONST(0x10001)
+#define AHB_AVP_PPCS_RD_COH_STATUS_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
+#define AHB_AVP_PPCS_RD_COH_STATUS_0_RDS_OUTSTANDING_SHIFT                      _MK_SHIFT_CONST(16)
+#define AHB_AVP_PPCS_RD_COH_STATUS_0_RDS_OUTSTANDING_FIELD                      (_MK_MASK_CONST(0x1) << AHB_AVP_PPCS_RD_COH_STATUS_0_RDS_OUTSTANDING_SHIFT)
+#define AHB_AVP_PPCS_RD_COH_STATUS_0_RDS_OUTSTANDING_RANGE                      16:16
+#define AHB_AVP_PPCS_RD_COH_STATUS_0_RDS_OUTSTANDING_WOFFSET                    0x0
+#define AHB_AVP_PPCS_RD_COH_STATUS_0_RDS_OUTSTANDING_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_AVP_PPCS_RD_COH_STATUS_0_RDS_OUTSTANDING_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define AHB_AVP_PPCS_RD_COH_STATUS_0_RDS_OUTSTANDING_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_AVP_PPCS_RD_COH_STATUS_0_RDS_OUTSTANDING_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define AHB_AVP_PPCS_RD_COH_STATUS_0_WRS_OUTSTANDING_SHIFT                      _MK_SHIFT_CONST(0)
+#define AHB_AVP_PPCS_RD_COH_STATUS_0_WRS_OUTSTANDING_FIELD                      (_MK_MASK_CONST(0x1) << AHB_AVP_PPCS_RD_COH_STATUS_0_WRS_OUTSTANDING_SHIFT)
+#define AHB_AVP_PPCS_RD_COH_STATUS_0_WRS_OUTSTANDING_RANGE                      0:0
+#define AHB_AVP_PPCS_RD_COH_STATUS_0_WRS_OUTSTANDING_WOFFSET                    0x0
+#define AHB_AVP_PPCS_RD_COH_STATUS_0_WRS_OUTSTANDING_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_AVP_PPCS_RD_COH_STATUS_0_WRS_OUTSTANDING_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define AHB_AVP_PPCS_RD_COH_STATUS_0_WRS_OUTSTANDING_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_AVP_PPCS_RD_COH_STATUS_0_WRS_OUTSTANDING_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register AHB_AHB_MEM_PREFETCH_CFG1_0  
+#define AHB_AHB_MEM_PREFETCH_CFG1_0                     _MK_ADDR_CONST(0xec)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_SECURE                      0x0
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_WORD_COUNT                  0x1
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_RESET_VAL                   _MK_MASK_CONST(0x14800800)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_WRITE_MASK                  _MK_MASK_CONST(0xffe0ffff)
+// 1=enable 0=disable
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_ENABLE_SHIFT                        _MK_SHIFT_CONST(31)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_ENABLE_FIELD                        (_MK_MASK_CONST(0x1) << AHB_AHB_MEM_PREFETCH_CFG1_0_ENABLE_SHIFT)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_ENABLE_RANGE                        31:31
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_ENABLE_WOFFSET                      0x0
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// AHBDMA master
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_SHIFT                    _MK_SHIFT_CONST(26)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_FIELD                    (_MK_MASK_CONST(0x1f) << AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_SHIFT)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_RANGE                    30:26
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_WOFFSET                  0x0
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_DEFAULT                  _MK_MASK_CONST(0x5)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_CPU                      _MK_ENUM_CONST(0)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_COP                      _MK_ENUM_CONST(1)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_VCP                      _MK_ENUM_CONST(2)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_UNUSED_03                        _MK_ENUM_CONST(3)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_IDE                      _MK_ENUM_CONST(4)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_AHBDMA                   _MK_ENUM_CONST(5)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_USB                      _MK_ENUM_CONST(6)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_APBDMA                   _MK_ENUM_CONST(7)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_XIO                      _MK_ENUM_CONST(8)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_SDIO1                    _MK_ENUM_CONST(9)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_SDMMC1                   _MK_ENUM_CONST(9)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_NAND_FLASH                       _MK_ENUM_CONST(10)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_SNOR                     _MK_ENUM_CONST(11)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_HSMMC                    _MK_ENUM_CONST(12)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_BSEV                     _MK_ENUM_CONST(13)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_UNUSED_0E                        _MK_ENUM_CONST(14)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_UNUSED_0F                        _MK_ENUM_CONST(15)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_SDMMC4                   _MK_ENUM_CONST(12)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_BSEA                     _MK_ENUM_CONST(16)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_USB3                     _MK_ENUM_CONST(17)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_USB2                     _MK_ENUM_CONST(18)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_SDIO2                    _MK_ENUM_CONST(19)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_SDMMC2                   _MK_ENUM_CONST(19)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_SDMMC3                   _MK_ENUM_CONST(20)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_UNUSED_15                        _MK_ENUM_CONST(21)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_UNUSED_16                        _MK_ENUM_CONST(22)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_UNUSED_17                        _MK_ENUM_CONST(23)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_UNUSED_18                        _MK_ENUM_CONST(24)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_UNUSED_19                        _MK_ENUM_CONST(25)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_UNUSED_1A                        _MK_ENUM_CONST(26)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_UNUSED_1B                        _MK_ENUM_CONST(27)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_UNUSED_1C                        _MK_ENUM_CONST(28)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_UNUSED_1D                        _MK_ENUM_CONST(29)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_UNUSED_1E                        _MK_ENUM_CONST(30)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_UNUSED_1F                        _MK_ENUM_CONST(31)
+
+// 2^(n+4) byte boundary. any value >16 will use n=16
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_ADDR_BNDRY_SHIFT                    _MK_SHIFT_CONST(21)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_ADDR_BNDRY_FIELD                    (_MK_MASK_CONST(0x1f) << AHB_AHB_MEM_PREFETCH_CFG1_0_ADDR_BNDRY_SHIFT)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_ADDR_BNDRY_RANGE                    25:21
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_ADDR_BNDRY_WOFFSET                  0x0
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_ADDR_BNDRY_DEFAULT                  _MK_MASK_CONST(0x4)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_ADDR_BNDRY_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_ADDR_BNDRY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_ADDR_BNDRY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// not used for AP-20 and beyond (last used in AP15)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_SPEC_THROTTLE_SHIFT                 _MK_SHIFT_CONST(16)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_SPEC_THROTTLE_FIELD                 (_MK_MASK_CONST(0x1f) << AHB_AHB_MEM_PREFETCH_CFG1_0_SPEC_THROTTLE_SHIFT)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_SPEC_THROTTLE_RANGE                 20:16
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_SPEC_THROTTLE_WOFFSET                       0x0
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_SPEC_THROTTLE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_SPEC_THROTTLE_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_SPEC_THROTTLE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_SPEC_THROTTLE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// 2048 cycles
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_INACTIVITY_TIMEOUT_SHIFT                    _MK_SHIFT_CONST(0)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_INACTIVITY_TIMEOUT_FIELD                    (_MK_MASK_CONST(0xffff) << AHB_AHB_MEM_PREFETCH_CFG1_0_INACTIVITY_TIMEOUT_SHIFT)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_INACTIVITY_TIMEOUT_RANGE                    15:0
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_INACTIVITY_TIMEOUT_WOFFSET                  0x0
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_INACTIVITY_TIMEOUT_DEFAULT                  _MK_MASK_CONST(0x800)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_INACTIVITY_TIMEOUT_DEFAULT_MASK                     _MK_MASK_CONST(0xffff)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_INACTIVITY_TIMEOUT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_INACTIVITY_TIMEOUT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register AHB_AHB_MEM_PREFETCH_CFG2_0  
+#define AHB_AHB_MEM_PREFETCH_CFG2_0                     _MK_ADDR_CONST(0xf0)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_SECURE                      0x0
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_WORD_COUNT                  0x1
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_RESET_VAL                   _MK_MASK_CONST(0x18800800)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_WRITE_MASK                  _MK_MASK_CONST(0xffe0ffff)
+// 1=enable 0=disable
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_ENABLE_SHIFT                        _MK_SHIFT_CONST(31)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_ENABLE_FIELD                        (_MK_MASK_CONST(0x1) << AHB_AHB_MEM_PREFETCH_CFG2_0_ENABLE_SHIFT)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_ENABLE_RANGE                        31:31
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_ENABLE_WOFFSET                      0x0
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// USB
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_SHIFT                    _MK_SHIFT_CONST(26)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_FIELD                    (_MK_MASK_CONST(0x1f) << AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_SHIFT)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_RANGE                    30:26
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_WOFFSET                  0x0
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_DEFAULT                  _MK_MASK_CONST(0x6)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_CPU                      _MK_ENUM_CONST(0)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_COP                      _MK_ENUM_CONST(1)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_VCP                      _MK_ENUM_CONST(2)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_UNUSED_03                        _MK_ENUM_CONST(3)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_IDE                      _MK_ENUM_CONST(4)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_AHBDMA                   _MK_ENUM_CONST(5)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_USB                      _MK_ENUM_CONST(6)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_APBDMA                   _MK_ENUM_CONST(7)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_XIO                      _MK_ENUM_CONST(8)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_SDIO1                    _MK_ENUM_CONST(9)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_SDMMC1                   _MK_ENUM_CONST(9)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_NAND_FLASH                       _MK_ENUM_CONST(10)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_SNOR                     _MK_ENUM_CONST(11)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_HSMMC                    _MK_ENUM_CONST(12)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_BSEV                     _MK_ENUM_CONST(13)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_UNUSED_0E                        _MK_ENUM_CONST(14)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_UNUSED_0F                        _MK_ENUM_CONST(15)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_SDMMC4                   _MK_ENUM_CONST(12)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_BSEA                     _MK_ENUM_CONST(16)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_USB3                     _MK_ENUM_CONST(17)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_USB2                     _MK_ENUM_CONST(18)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_SDIO2                    _MK_ENUM_CONST(19)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_SDMMC2                   _MK_ENUM_CONST(19)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_SDMMC3                   _MK_ENUM_CONST(20)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_UNUSED_15                        _MK_ENUM_CONST(21)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_UNUSED_16                        _MK_ENUM_CONST(22)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_UNUSED_17                        _MK_ENUM_CONST(23)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_UNUSED_18                        _MK_ENUM_CONST(24)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_UNUSED_19                        _MK_ENUM_CONST(25)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_UNUSED_1A                        _MK_ENUM_CONST(26)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_UNUSED_1B                        _MK_ENUM_CONST(27)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_UNUSED_1C                        _MK_ENUM_CONST(28)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_UNUSED_1D                        _MK_ENUM_CONST(29)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_UNUSED_1E                        _MK_ENUM_CONST(30)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_UNUSED_1F                        _MK_ENUM_CONST(31)
+
+// 2^(n+4) byte boundary. any value >16 will use n=16
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_ADDR_BNDRY_SHIFT                    _MK_SHIFT_CONST(21)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_ADDR_BNDRY_FIELD                    (_MK_MASK_CONST(0x1f) << AHB_AHB_MEM_PREFETCH_CFG2_0_ADDR_BNDRY_SHIFT)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_ADDR_BNDRY_RANGE                    25:21
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_ADDR_BNDRY_WOFFSET                  0x0
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_ADDR_BNDRY_DEFAULT                  _MK_MASK_CONST(0x4)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_ADDR_BNDRY_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_ADDR_BNDRY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_ADDR_BNDRY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// not used for AP-20 and beyond (last used in AP15)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_SPEC_THROTTLE_SHIFT                 _MK_SHIFT_CONST(16)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_SPEC_THROTTLE_FIELD                 (_MK_MASK_CONST(0x1f) << AHB_AHB_MEM_PREFETCH_CFG2_0_SPEC_THROTTLE_SHIFT)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_SPEC_THROTTLE_RANGE                 20:16
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_SPEC_THROTTLE_WOFFSET                       0x0
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_SPEC_THROTTLE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_SPEC_THROTTLE_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_SPEC_THROTTLE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_SPEC_THROTTLE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// 
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_INACTIVITY_TIMEOUT_SHIFT                    _MK_SHIFT_CONST(0)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_INACTIVITY_TIMEOUT_FIELD                    (_MK_MASK_CONST(0xffff) << AHB_AHB_MEM_PREFETCH_CFG2_0_INACTIVITY_TIMEOUT_SHIFT)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_INACTIVITY_TIMEOUT_RANGE                    15:0
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_INACTIVITY_TIMEOUT_WOFFSET                  0x0
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_INACTIVITY_TIMEOUT_DEFAULT                  _MK_MASK_CONST(0x800)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_INACTIVITY_TIMEOUT_DEFAULT_MASK                     _MK_MASK_CONST(0xffff)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_INACTIVITY_TIMEOUT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_INACTIVITY_TIMEOUT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register AHB_AHBSLVMEM_STATUS_0  
+#define AHB_AHBSLVMEM_STATUS_0                  _MK_ADDR_CONST(0xf4)
+#define AHB_AHBSLVMEM_STATUS_0_SECURE                   0x0
+#define AHB_AHBSLVMEM_STATUS_0_WORD_COUNT                       0x1
+#define AHB_AHBSLVMEM_STATUS_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define AHB_AHBSLVMEM_STATUS_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define AHB_AHBSLVMEM_STATUS_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define AHB_AHBSLVMEM_STATUS_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define AHB_AHBSLVMEM_STATUS_0_READ_MASK                        _MK_MASK_CONST(0x3)
+#define AHB_AHBSLVMEM_STATUS_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
+#define AHB_AHBSLVMEM_STATUS_0_PPCS_RDS_OUTSTANDING_SHIFT                       _MK_SHIFT_CONST(1)
+#define AHB_AHBSLVMEM_STATUS_0_PPCS_RDS_OUTSTANDING_FIELD                       (_MK_MASK_CONST(0x1) << AHB_AHBSLVMEM_STATUS_0_PPCS_RDS_OUTSTANDING_SHIFT)
+#define AHB_AHBSLVMEM_STATUS_0_PPCS_RDS_OUTSTANDING_RANGE                       1:1
+#define AHB_AHBSLVMEM_STATUS_0_PPCS_RDS_OUTSTANDING_WOFFSET                     0x0
+#define AHB_AHBSLVMEM_STATUS_0_PPCS_RDS_OUTSTANDING_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_AHBSLVMEM_STATUS_0_PPCS_RDS_OUTSTANDING_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define AHB_AHBSLVMEM_STATUS_0_PPCS_RDS_OUTSTANDING_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_AHBSLVMEM_STATUS_0_PPCS_RDS_OUTSTANDING_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define AHB_AHBSLVMEM_STATUS_0_GIZMO_IP_RDQUE_EMPTY_SHIFT                       _MK_SHIFT_CONST(0)
+#define AHB_AHBSLVMEM_STATUS_0_GIZMO_IP_RDQUE_EMPTY_FIELD                       (_MK_MASK_CONST(0x1) << AHB_AHBSLVMEM_STATUS_0_GIZMO_IP_RDQUE_EMPTY_SHIFT)
+#define AHB_AHBSLVMEM_STATUS_0_GIZMO_IP_RDQUE_EMPTY_RANGE                       0:0
+#define AHB_AHBSLVMEM_STATUS_0_GIZMO_IP_RDQUE_EMPTY_WOFFSET                     0x0
+#define AHB_AHBSLVMEM_STATUS_0_GIZMO_IP_RDQUE_EMPTY_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_AHBSLVMEM_STATUS_0_GIZMO_IP_RDQUE_EMPTY_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define AHB_AHBSLVMEM_STATUS_0_GIZMO_IP_RDQUE_EMPTY_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_AHBSLVMEM_STATUS_0_GIZMO_IP_RDQUE_EMPTY_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID_0  
+#define AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID_0                  _MK_ADDR_CONST(0xf8)
+#define AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID_0_SECURE                   0x0
+#define AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID_0_WORD_COUNT                       0x1
+#define AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID_0_RESET_MASK                       _MK_MASK_CONST(0x7fffffff)
+#define AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID_0_READ_MASK                        _MK_MASK_CONST(0x7fffffff)
+#define AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID_0_WRITE_MASK                       _MK_MASK_CONST(0x7fffffff)
+// 0 = there is no write data in the write queue from  that AHB master.
+#define AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID_0_AHB_MASTER_ID_SHIFT                      _MK_SHIFT_CONST(0)
+#define AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID_0_AHB_MASTER_ID_FIELD                      (_MK_MASK_CONST(0x7fffffff) << AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID_0_AHB_MASTER_ID_SHIFT)
+#define AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID_0_AHB_MASTER_ID_RANGE                      30:0
+#define AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID_0_AHB_MASTER_ID_WOFFSET                    0x0
+#define AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID_0_AHB_MASTER_ID_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID_0_AHB_MASTER_ID_DEFAULT_MASK                       _MK_MASK_CONST(0x7fffffff)
+#define AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID_0_AHB_MASTER_ID_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID_0_AHB_MASTER_ID_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register AHB_ARBITRATION_CPU_ABORT_INFO_0  
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0                        _MK_ADDR_CONST(0xfc)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_SECURE                         0x0
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_WORD_COUNT                     0x1
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_RESET_MASK                     _MK_MASK_CONST(0xffff)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_READ_MASK                      _MK_MASK_CONST(0xffff)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
+// Abort occurred due to an iRAMa protection  violation
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMA_SHIFT                    _MK_SHIFT_CONST(15)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMA_FIELD                    (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMA_SHIFT)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMA_RANGE                    15:15
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMA_WOFFSET                  0x0
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMA_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMA_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMA_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMA_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMA_ABT_DIS                  _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMA_ABT_EN                   _MK_ENUM_CONST(1)
+
+// Abort occurred due to an iRAMb protection  violation
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMB_SHIFT                    _MK_SHIFT_CONST(14)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMB_FIELD                    (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMB_SHIFT)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMB_RANGE                    14:14
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMB_WOFFSET                  0x0
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMB_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMB_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMB_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMB_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMB_ABT_DIS                  _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMB_ABT_EN                   _MK_ENUM_CONST(1)
+
+// Abort occurred due to an iRAMc protection  violation
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMC_SHIFT                    _MK_SHIFT_CONST(13)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMC_FIELD                    (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMC_SHIFT)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMC_RANGE                    13:13
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMC_WOFFSET                  0x0
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMC_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMC_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMC_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMC_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMC_ABT_DIS                  _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMC_ABT_EN                   _MK_ENUM_CONST(1)
+
+// Abort occurred due to an iRAMd protection  violation
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMD_SHIFT                    _MK_SHIFT_CONST(12)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMD_FIELD                    (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMD_SHIFT)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMD_RANGE                    12:12
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMD_WOFFSET                  0x0
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMD_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMD_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMD_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMD_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMD_ABT_DIS                  _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMD_ABT_EN                   _MK_ENUM_CONST(1)
+
+// Abort occurred due to an access to invalid iRAM  address space
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_INV_IRAM_SHIFT                 _MK_SHIFT_CONST(11)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_INV_IRAM_FIELD                 (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_CPU_ABORT_INFO_0_INV_IRAM_SHIFT)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_INV_IRAM_RANGE                 11:11
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_INV_IRAM_WOFFSET                       0x0
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_INV_IRAM_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_INV_IRAM_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_INV_IRAM_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_INV_IRAM_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_INV_IRAM_ABT_DIS                       _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_INV_IRAM_ABT_EN                        _MK_ENUM_CONST(1)
+
+// Abort occurred due to a PPSB protection violation
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_PPSB_SHIFT                     _MK_SHIFT_CONST(10)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_PPSB_FIELD                     (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_CPU_ABORT_INFO_0_PPSB_SHIFT)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_PPSB_RANGE                     10:10
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_PPSB_WOFFSET                   0x0
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_PPSB_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_PPSB_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_PPSB_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_PPSB_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_PPSB_ABT_DIS                   _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_PPSB_ABT_EN                    _MK_ENUM_CONST(1)
+
+// Abort occurred due to an APB protection violation
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_APB_SHIFT                      _MK_SHIFT_CONST(9)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_APB_FIELD                      (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_CPU_ABORT_INFO_0_APB_SHIFT)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_APB_RANGE                      9:9
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_APB_WOFFSET                    0x0
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_APB_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_APB_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_APB_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_APB_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_APB_ABT_DIS                    _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_APB_ABT_EN                     _MK_ENUM_CONST(1)
+
+// Abort occurred due to an AHB protection violation
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_AHB_SHIFT                      _MK_SHIFT_CONST(8)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_AHB_FIELD                      (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_CPU_ABORT_INFO_0_AHB_SHIFT)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_AHB_RANGE                      8:8
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_AHB_WOFFSET                    0x0
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_AHB_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_AHB_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_AHB_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_AHB_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_AHB_ABT_DIS                    _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_AHB_ABT_EN                     _MK_ENUM_CONST(1)
+
+// Abort occurred due to a Cache protection violation
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_CACHE_SHIFT                    _MK_SHIFT_CONST(7)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_CACHE_FIELD                    (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_CPU_ABORT_INFO_0_CACHE_SHIFT)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_CACHE_RANGE                    7:7
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_CACHE_WOFFSET                  0x0
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_CACHE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_CACHE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_CACHE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_CACHE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_CACHE_ABT_DIS                  _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_CACHE_ABT_EN                   _MK_ENUM_CONST(1)
+
+// TRUE for any protection violation
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_PROTECTION_SHIFT                       _MK_SHIFT_CONST(6)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_PROTECTION_FIELD                       (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_CPU_ABORT_INFO_0_PROTECTION_SHIFT)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_PROTECTION_RANGE                       6:6
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_PROTECTION_WOFFSET                     0x0
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_PROTECTION_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_PROTECTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_PROTECTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_PROTECTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_PROTECTION_ABT_DIS                     _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_PROTECTION_ABT_EN                      _MK_ENUM_CONST(1)
+
+// TRUE for abort caused by Misalignment (i.e. word  access at odd byte address)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_ALIGN_SHIFT                    _MK_SHIFT_CONST(5)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_ALIGN_FIELD                    (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_CPU_ABORT_INFO_0_ALIGN_SHIFT)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_ALIGN_RANGE                    5:5
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_ALIGN_WOFFSET                  0x0
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_ALIGN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_ALIGN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_ALIGN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_ALIGN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_ALIGN_ABT_DIS                  _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_ALIGN_ABT_EN                   _MK_ENUM_CONST(1)
+
+// TRUE for abort caused by Bad Size (i.e. word  access at odd byte address)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_BADSIZE_SHIFT                  _MK_SHIFT_CONST(4)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_BADSIZE_FIELD                  (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_CPU_ABORT_INFO_0_BADSIZE_SHIFT)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_BADSIZE_RANGE                  4:4
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_BADSIZE_WOFFSET                        0x0
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_BADSIZE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_BADSIZE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_BADSIZE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_BADSIZE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_BADSIZE_ABT_DIS                        _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_BADSIZE_ABT_EN                 _MK_ENUM_CONST(1)
+
+// Aborted transaction was a Write
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_WRITE_SHIFT                    _MK_SHIFT_CONST(3)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_WRITE_FIELD                    (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_CPU_ABORT_INFO_0_WRITE_SHIFT)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_WRITE_RANGE                    3:3
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_WRITE_WOFFSET                  0x0
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_WRITE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_WRITE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_WRITE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_WRITE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_WRITE_ABT_DIS                  _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_WRITE_ABT_EN                   _MK_ENUM_CONST(1)
+
+// Aborted transaction was a Data access
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_DATA_SHIFT                     _MK_SHIFT_CONST(2)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_DATA_FIELD                     (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_CPU_ABORT_INFO_0_DATA_SHIFT)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_DATA_RANGE                     2:2
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_DATA_WOFFSET                   0x0
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_DATA_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_DATA_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_DATA_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_DATA_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_DATA_ABT_DIS                   _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_DATA_ABT_EN                    _MK_ENUM_CONST(1)
+
+// Aborted transaction Request Size 00=byte,  01=hword, 10=word
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_SIZE_SHIFT                     _MK_SHIFT_CONST(0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_SIZE_FIELD                     (_MK_MASK_CONST(0x3) << AHB_ARBITRATION_CPU_ABORT_INFO_0_SIZE_SHIFT)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_SIZE_RANGE                     1:0
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_SIZE_WOFFSET                   0x0
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_SIZE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_SIZE_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_SIZE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_SIZE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_SIZE_BYTE_ABT                  _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_SIZE_HWORD_ABT                 _MK_ENUM_CONST(1)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_SIZE_WORD_ABT                  _MK_ENUM_CONST(2)
+
+
+// Register AHB_ARBITRATION_CPU_ABORT_ADDR_0  
+#define AHB_ARBITRATION_CPU_ABORT_ADDR_0                        _MK_ADDR_CONST(0x100)
+#define AHB_ARBITRATION_CPU_ABORT_ADDR_0_SECURE                         0x0
+#define AHB_ARBITRATION_CPU_ABORT_ADDR_0_WORD_COUNT                     0x1
+#define AHB_ARBITRATION_CPU_ABORT_ADDR_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_ADDR_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
+#define AHB_ARBITRATION_CPU_ABORT_ADDR_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_ADDR_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_ADDR_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define AHB_ARBITRATION_CPU_ABORT_ADDR_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
+// Instruction Address which caused the abort
+#define AHB_ARBITRATION_CPU_ABORT_ADDR_0_ADDR_SHIFT                     _MK_SHIFT_CONST(0)
+#define AHB_ARBITRATION_CPU_ABORT_ADDR_0_ADDR_FIELD                     (_MK_MASK_CONST(0xffffffff) << AHB_ARBITRATION_CPU_ABORT_ADDR_0_ADDR_SHIFT)
+#define AHB_ARBITRATION_CPU_ABORT_ADDR_0_ADDR_RANGE                     31:0
+#define AHB_ARBITRATION_CPU_ABORT_ADDR_0_ADDR_WOFFSET                   0x0
+#define AHB_ARBITRATION_CPU_ABORT_ADDR_0_ADDR_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_ADDR_0_ADDR_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define AHB_ARBITRATION_CPU_ABORT_ADDR_0_ADDR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_ADDR_0_ADDR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register AHB_ARBITRATION_COP_ABORT_INFO_0  
+#define AHB_ARBITRATION_COP_ABORT_INFO_0                        _MK_ADDR_CONST(0x104)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_SECURE                         0x0
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_WORD_COUNT                     0x1
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_RESET_MASK                     _MK_MASK_CONST(0xe7ff)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_READ_MASK                      _MK_MASK_CONST(0xe7ff)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
+// Abort occurred due to an iRAMa protection  violation
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMA_SHIFT                    _MK_SHIFT_CONST(15)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMA_FIELD                    (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMA_SHIFT)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMA_RANGE                    15:15
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMA_WOFFSET                  0x0
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMA_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMA_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMA_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMA_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMA_ABT_DIS                  _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMA_ABT_EN                   _MK_ENUM_CONST(1)
+
+// Abort occurred due to an iRAMb protection  violation
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMB_SHIFT                    _MK_SHIFT_CONST(14)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMB_FIELD                    (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMB_SHIFT)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMB_RANGE                    14:14
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMB_WOFFSET                  0x0
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMB_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMB_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMB_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMB_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMB_ABT_DIS                  _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMB_ABT_EN                   _MK_ENUM_CONST(1)
+
+// Abort occurred due to an iRAMc protection  violation
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMC_SHIFT                    _MK_SHIFT_CONST(13)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMC_FIELD                    (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMC_SHIFT)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMC_RANGE                    13:13
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMC_WOFFSET                  0x0
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMC_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMC_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMC_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMC_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMC_ABT_DIS                  _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMC_ABT_EN                   _MK_ENUM_CONST(1)
+
+// Abort occurred due to a PPSB protection violation
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_PPSB_SHIFT                     _MK_SHIFT_CONST(10)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_PPSB_FIELD                     (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_COP_ABORT_INFO_0_PPSB_SHIFT)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_PPSB_RANGE                     10:10
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_PPSB_WOFFSET                   0x0
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_PPSB_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_PPSB_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_PPSB_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_PPSB_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_PPSB_ABT_DIS                   _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_PPSB_ABT_EN                    _MK_ENUM_CONST(1)
+
+// Abort occurred due to an APB protection violation
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_APB_SHIFT                      _MK_SHIFT_CONST(9)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_APB_FIELD                      (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_COP_ABORT_INFO_0_APB_SHIFT)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_APB_RANGE                      9:9
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_APB_WOFFSET                    0x0
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_APB_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_APB_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_APB_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_APB_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_APB_ABT_DIS                    _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_APB_ABT_EN                     _MK_ENUM_CONST(1)
+
+// Abort occurred due to an AHB protection violation
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_AHB_SHIFT                      _MK_SHIFT_CONST(8)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_AHB_FIELD                      (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_COP_ABORT_INFO_0_AHB_SHIFT)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_AHB_RANGE                      8:8
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_AHB_WOFFSET                    0x0
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_AHB_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_AHB_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_AHB_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_AHB_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_AHB_ABT_DIS                    _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_AHB_ABT_EN                     _MK_ENUM_CONST(1)
+
+// Abort occurred due to a Cache protection violation
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_CACHE_SHIFT                    _MK_SHIFT_CONST(7)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_CACHE_FIELD                    (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_COP_ABORT_INFO_0_CACHE_SHIFT)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_CACHE_RANGE                    7:7
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_CACHE_WOFFSET                  0x0
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_CACHE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_CACHE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_CACHE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_CACHE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_CACHE_ABT_DIS                  _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_CACHE_ABT_EN                   _MK_ENUM_CONST(1)
+
+// TRUE for any protection violation
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_PROTECTION_SHIFT                       _MK_SHIFT_CONST(6)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_PROTECTION_FIELD                       (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_COP_ABORT_INFO_0_PROTECTION_SHIFT)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_PROTECTION_RANGE                       6:6
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_PROTECTION_WOFFSET                     0x0
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_PROTECTION_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_PROTECTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_PROTECTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_PROTECTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_PROTECTION_ABT_DIS                     _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_PROTECTION_ABT_EN                      _MK_ENUM_CONST(1)
+
+// TRUE for abort caused by Misalignment (i.e. word  access at odd byte address)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_ALIGN_SHIFT                    _MK_SHIFT_CONST(5)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_ALIGN_FIELD                    (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_COP_ABORT_INFO_0_ALIGN_SHIFT)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_ALIGN_RANGE                    5:5
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_ALIGN_WOFFSET                  0x0
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_ALIGN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_ALIGN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_ALIGN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_ALIGN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_ALIGN_ABT_DIS                  _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_ALIGN_ABT_EN                   _MK_ENUM_CONST(1)
+
+// TRUE for abort caused by Bad Size (i.e. word  access at odd byte address)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_BADSIZE_SHIFT                  _MK_SHIFT_CONST(4)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_BADSIZE_FIELD                  (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_COP_ABORT_INFO_0_BADSIZE_SHIFT)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_BADSIZE_RANGE                  4:4
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_BADSIZE_WOFFSET                        0x0
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_BADSIZE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_BADSIZE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_BADSIZE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_BADSIZE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_BADSIZE_ABT_DIS                        _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_BADSIZE_ABT_EN                 _MK_ENUM_CONST(1)
+
+// Aborted transaction was a Write
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_WRITE_SHIFT                    _MK_SHIFT_CONST(3)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_WRITE_FIELD                    (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_COP_ABORT_INFO_0_WRITE_SHIFT)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_WRITE_RANGE                    3:3
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_WRITE_WOFFSET                  0x0
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_WRITE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_WRITE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_WRITE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_WRITE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_WRITE_ABT_DIS                  _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_WRITE_ABT_EN                   _MK_ENUM_CONST(1)
+
+// Aborted transaction was a Data access
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_DATA_SHIFT                     _MK_SHIFT_CONST(2)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_DATA_FIELD                     (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_COP_ABORT_INFO_0_DATA_SHIFT)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_DATA_RANGE                     2:2
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_DATA_WOFFSET                   0x0
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_DATA_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_DATA_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_DATA_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_DATA_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_DATA_ABT_DIS                   _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_DATA_ABT_EN                    _MK_ENUM_CONST(1)
+
+// Aborted transaction Request Size 00=byte,  01=hword, 10=word
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_SIZE_SHIFT                     _MK_SHIFT_CONST(0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_SIZE_FIELD                     (_MK_MASK_CONST(0x3) << AHB_ARBITRATION_COP_ABORT_INFO_0_SIZE_SHIFT)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_SIZE_RANGE                     1:0
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_SIZE_WOFFSET                   0x0
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_SIZE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_SIZE_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_SIZE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_SIZE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_SIZE_BYTE_ABT                  _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_SIZE_HWORD_ABT                 _MK_ENUM_CONST(1)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_SIZE_WORD_ABT                  _MK_ENUM_CONST(2)
+
+
+// Register AHB_ARBITRATION_COP_ABORT_ADDR_0  
+#define AHB_ARBITRATION_COP_ABORT_ADDR_0                        _MK_ADDR_CONST(0x108)
+#define AHB_ARBITRATION_COP_ABORT_ADDR_0_SECURE                         0x0
+#define AHB_ARBITRATION_COP_ABORT_ADDR_0_WORD_COUNT                     0x1
+#define AHB_ARBITRATION_COP_ABORT_ADDR_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_ADDR_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
+#define AHB_ARBITRATION_COP_ABORT_ADDR_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_ADDR_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_ADDR_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define AHB_ARBITRATION_COP_ABORT_ADDR_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
+// Instruction Address which caused the abort
+#define AHB_ARBITRATION_COP_ABORT_ADDR_0_ADDR_SHIFT                     _MK_SHIFT_CONST(0)
+#define AHB_ARBITRATION_COP_ABORT_ADDR_0_ADDR_FIELD                     (_MK_MASK_CONST(0xffffffff) << AHB_ARBITRATION_COP_ABORT_ADDR_0_ADDR_SHIFT)
+#define AHB_ARBITRATION_COP_ABORT_ADDR_0_ADDR_RANGE                     31:0
+#define AHB_ARBITRATION_COP_ABORT_ADDR_0_ADDR_WOFFSET                   0x0
+#define AHB_ARBITRATION_COP_ABORT_ADDR_0_ADDR_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_ADDR_0_ADDR_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define AHB_ARBITRATION_COP_ABORT_ADDR_0_ADDR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_ADDR_0_ADDR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Reserved address 268 [0x10c] 
+
+// Reserved address 272 [0x110] 
+
+// Reserved address 276 [0x114] 
+
+// Reserved address 280 [0x118] 
+
+// Reserved address 284 [0x11c] 
+
+// Reserved address 288 [0x120] 
+
+// Reserved address 292 [0x124] 
+
+// Reserved address 296 [0x128] 
+
+// Reserved address 300 [0x12c] 
+
+// Reserved address 304 [0x130] 
+
+// Reserved address 308 [0x134] 
+
+// Reserved address 312 [0x138] 
+
+// Reserved address 316 [0x13c] 
+
+// Reserved address 320 [0x140] 
+
+// Reserved address 324 [0x144] 
+
+// Reserved address 328 [0x148] 
+
+// Reserved address 332 [0x14c] 
+
+// Reserved address 336 [0x150] 
+
+// Reserved address 340 [0x154] 
+
+// Reserved address 344 [0x158] 
+
+// Reserved address 348 [0x15c] 
+
+// Reserved address 352 [0x160] 
+
+// Reserved address 356 [0x164] 
+
+// Reserved address 360 [0x168] 
+
+// Reserved address 364 [0x16c] 
+
+// Reserved address 368 [0x170] 
+
+// Reserved address 372 [0x174] 
+
+// Reserved address 376 [0x178] 
+
+// Reserved address 380 [0x17c] 
+
+// Reserved address 384 [0x180] 
+
+// Reserved address 388 [0x184] 
+
+// Reserved address 392 [0x188] 
+
+// Reserved address 396 [0x18c] 
+
+// Reserved address 400 [0x190] 
+
+// Reserved address 404 [0x194] 
+
+// Reserved address 408 [0x198] 
+
+// Reserved address 412 [0x19c] 
+
+// Reserved address 416 [0x1a0] 
+
+// Reserved address 420 [0x1a4] 
+
+// Reserved address 424 [0x1a8] 
+
+// Reserved address 428 [0x1ac] 
+
+// Reserved address 432 [0x1b0] 
+
+// Reserved address 436 [0x1b4] 
+
+// Reserved address 440 [0x1b8] 
+
+// Reserved address 444 [0x1bc] 
+
+// Reserved address 448 [0x1c0] 
+
+// Reserved address 452 [0x1c4] 
+
+// Reserved address 456 [0x1c8] 
+
+// Reserved address 460 [0x1cc] 
+
+// Reserved address 464 [0x1d0] 
+
+// Reserved address 468 [0x1d4] 
+
+// Reserved address 472 [0x1d8] 
+
+// Reserved address 476 [0x1dc] 
+
+// Reserved address 480 [0x1e0] 
+
+// Reserved address 484 [0x1e4] 
+
+// Reserved address 488 [0x1e8] 
+
+// Reserved address 492 [0x1ec] 
+
+// Reserved address 496 [0x1f0] 
+
+// Reserved address 500 [0x1f4] 
+
+// Reserved address 504 [0x1f8] 
+
+// Reserved address 508 [0x1fc] 
+
+// Reserved address 512 [0x200] 
+
+// Reserved address 516 [0x204] 
+
+// Reserved address 520 [0x208] 
+
+// Reserved address 524 [0x20c] 
+
+// Reserved address 528 [0x210] 
+
+// Reserved address 532 [0x214] 
+
+// Reserved address 536 [0x218] 
+
+// Reserved address 540 [0x21c] 
+
+// Reserved address 544 [0x220] 
+
+// Reserved address 548 [0x224] 
+
+// Reserved address 552 [0x228] 
+
+// Reserved address 556 [0x22c] 
+
+// Reserved address 560 [0x230] 
+
+// Reserved address 564 [0x234] 
+
+// Reserved address 568 [0x238] 
+
+// Register AHB_AVPC_MCCIF_FIFOCTRL_0  
+#define AHB_AVPC_MCCIF_FIFOCTRL_0                       _MK_ADDR_CONST(0x23c)
+#define AHB_AVPC_MCCIF_FIFOCTRL_0_SECURE                        0x0
+#define AHB_AVPC_MCCIF_FIFOCTRL_0_WORD_COUNT                    0x1
+#define AHB_AVPC_MCCIF_FIFOCTRL_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define AHB_AVPC_MCCIF_FIFOCTRL_0_RESET_MASK                    _MK_MASK_CONST(0xf)
+#define AHB_AVPC_MCCIF_FIFOCTRL_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define AHB_AVPC_MCCIF_FIFOCTRL_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define AHB_AVPC_MCCIF_FIFOCTRL_0_READ_MASK                     _MK_MASK_CONST(0xf)
+#define AHB_AVPC_MCCIF_FIFOCTRL_0_WRITE_MASK                    _MK_MASK_CONST(0xf)
+#define AHB_AVPC_MCCIF_FIFOCTRL_0_AVPC_MCCIF_WRCL_MCLE2X_SHIFT                  _MK_SHIFT_CONST(0)
+#define AHB_AVPC_MCCIF_FIFOCTRL_0_AVPC_MCCIF_WRCL_MCLE2X_FIELD                  (_MK_MASK_CONST(0x1) << AHB_AVPC_MCCIF_FIFOCTRL_0_AVPC_MCCIF_WRCL_MCLE2X_SHIFT)
+#define AHB_AVPC_MCCIF_FIFOCTRL_0_AVPC_MCCIF_WRCL_MCLE2X_RANGE                  0:0
+#define AHB_AVPC_MCCIF_FIFOCTRL_0_AVPC_MCCIF_WRCL_MCLE2X_WOFFSET                        0x0
+#define AHB_AVPC_MCCIF_FIFOCTRL_0_AVPC_MCCIF_WRCL_MCLE2X_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_AVPC_MCCIF_FIFOCTRL_0_AVPC_MCCIF_WRCL_MCLE2X_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define AHB_AVPC_MCCIF_FIFOCTRL_0_AVPC_MCCIF_WRCL_MCLE2X_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_AVPC_MCCIF_FIFOCTRL_0_AVPC_MCCIF_WRCL_MCLE2X_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define AHB_AVPC_MCCIF_FIFOCTRL_0_AVPC_MCCIF_WRCL_MCLE2X_INIT_ENUM                      DISABLE
+#define AHB_AVPC_MCCIF_FIFOCTRL_0_AVPC_MCCIF_WRCL_MCLE2X_DISABLE                        _MK_ENUM_CONST(0)
+#define AHB_AVPC_MCCIF_FIFOCTRL_0_AVPC_MCCIF_WRCL_MCLE2X_ENABLE                 _MK_ENUM_CONST(1)
+
+#define AHB_AVPC_MCCIF_FIFOCTRL_0_AVPC_MCCIF_RDMC_RDFAST_SHIFT                  _MK_SHIFT_CONST(1)
+#define AHB_AVPC_MCCIF_FIFOCTRL_0_AVPC_MCCIF_RDMC_RDFAST_FIELD                  (_MK_MASK_CONST(0x1) << AHB_AVPC_MCCIF_FIFOCTRL_0_AVPC_MCCIF_RDMC_RDFAST_SHIFT)
+#define AHB_AVPC_MCCIF_FIFOCTRL_0_AVPC_MCCIF_RDMC_RDFAST_RANGE                  1:1
+#define AHB_AVPC_MCCIF_FIFOCTRL_0_AVPC_MCCIF_RDMC_RDFAST_WOFFSET                        0x0
+#define AHB_AVPC_MCCIF_FIFOCTRL_0_AVPC_MCCIF_RDMC_RDFAST_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_AVPC_MCCIF_FIFOCTRL_0_AVPC_MCCIF_RDMC_RDFAST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define AHB_AVPC_MCCIF_FIFOCTRL_0_AVPC_MCCIF_RDMC_RDFAST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_AVPC_MCCIF_FIFOCTRL_0_AVPC_MCCIF_RDMC_RDFAST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define AHB_AVPC_MCCIF_FIFOCTRL_0_AVPC_MCCIF_RDMC_RDFAST_INIT_ENUM                      DISABLE
+#define AHB_AVPC_MCCIF_FIFOCTRL_0_AVPC_MCCIF_RDMC_RDFAST_DISABLE                        _MK_ENUM_CONST(0)
+#define AHB_AVPC_MCCIF_FIFOCTRL_0_AVPC_MCCIF_RDMC_RDFAST_ENABLE                 _MK_ENUM_CONST(1)
+
+#define AHB_AVPC_MCCIF_FIFOCTRL_0_AVPC_MCCIF_WRMC_CLLE2X_SHIFT                  _MK_SHIFT_CONST(2)
+#define AHB_AVPC_MCCIF_FIFOCTRL_0_AVPC_MCCIF_WRMC_CLLE2X_FIELD                  (_MK_MASK_CONST(0x1) << AHB_AVPC_MCCIF_FIFOCTRL_0_AVPC_MCCIF_WRMC_CLLE2X_SHIFT)
+#define AHB_AVPC_MCCIF_FIFOCTRL_0_AVPC_MCCIF_WRMC_CLLE2X_RANGE                  2:2
+#define AHB_AVPC_MCCIF_FIFOCTRL_0_AVPC_MCCIF_WRMC_CLLE2X_WOFFSET                        0x0
+#define AHB_AVPC_MCCIF_FIFOCTRL_0_AVPC_MCCIF_WRMC_CLLE2X_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_AVPC_MCCIF_FIFOCTRL_0_AVPC_MCCIF_WRMC_CLLE2X_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define AHB_AVPC_MCCIF_FIFOCTRL_0_AVPC_MCCIF_WRMC_CLLE2X_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_AVPC_MCCIF_FIFOCTRL_0_AVPC_MCCIF_WRMC_CLLE2X_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define AHB_AVPC_MCCIF_FIFOCTRL_0_AVPC_MCCIF_WRMC_CLLE2X_INIT_ENUM                      DISABLE
+#define AHB_AVPC_MCCIF_FIFOCTRL_0_AVPC_MCCIF_WRMC_CLLE2X_DISABLE                        _MK_ENUM_CONST(0)
+#define AHB_AVPC_MCCIF_FIFOCTRL_0_AVPC_MCCIF_WRMC_CLLE2X_ENABLE                 _MK_ENUM_CONST(1)
+
+#define AHB_AVPC_MCCIF_FIFOCTRL_0_AVPC_MCCIF_RDCL_RDFAST_SHIFT                  _MK_SHIFT_CONST(3)
+#define AHB_AVPC_MCCIF_FIFOCTRL_0_AVPC_MCCIF_RDCL_RDFAST_FIELD                  (_MK_MASK_CONST(0x1) << AHB_AVPC_MCCIF_FIFOCTRL_0_AVPC_MCCIF_RDCL_RDFAST_SHIFT)
+#define AHB_AVPC_MCCIF_FIFOCTRL_0_AVPC_MCCIF_RDCL_RDFAST_RANGE                  3:3
+#define AHB_AVPC_MCCIF_FIFOCTRL_0_AVPC_MCCIF_RDCL_RDFAST_WOFFSET                        0x0
+#define AHB_AVPC_MCCIF_FIFOCTRL_0_AVPC_MCCIF_RDCL_RDFAST_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_AVPC_MCCIF_FIFOCTRL_0_AVPC_MCCIF_RDCL_RDFAST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define AHB_AVPC_MCCIF_FIFOCTRL_0_AVPC_MCCIF_RDCL_RDFAST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_AVPC_MCCIF_FIFOCTRL_0_AVPC_MCCIF_RDCL_RDFAST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define AHB_AVPC_MCCIF_FIFOCTRL_0_AVPC_MCCIF_RDCL_RDFAST_INIT_ENUM                      DISABLE
+#define AHB_AVPC_MCCIF_FIFOCTRL_0_AVPC_MCCIF_RDCL_RDFAST_DISABLE                        _MK_ENUM_CONST(0)
+#define AHB_AVPC_MCCIF_FIFOCTRL_0_AVPC_MCCIF_RDCL_RDFAST_ENABLE                 _MK_ENUM_CONST(1)
+
+
+// Reserved address 573 [0x23d] 
+
+// Reserved address 574 [0x23e] 
+
+// Reserved address 575 [0x23f] 
+
+// Register AHB_TIMEOUT_WCOAL_AVPC_0  
+#define AHB_TIMEOUT_WCOAL_AVPC_0                        _MK_ADDR_CONST(0x240)
+#define AHB_TIMEOUT_WCOAL_AVPC_0_SECURE                         0x0
+#define AHB_TIMEOUT_WCOAL_AVPC_0_WORD_COUNT                     0x1
+#define AHB_TIMEOUT_WCOAL_AVPC_0_RESET_VAL                      _MK_MASK_CONST(0x32)
+#define AHB_TIMEOUT_WCOAL_AVPC_0_RESET_MASK                     _MK_MASK_CONST(0xff)
+#define AHB_TIMEOUT_WCOAL_AVPC_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define AHB_TIMEOUT_WCOAL_AVPC_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define AHB_TIMEOUT_WCOAL_AVPC_0_READ_MASK                      _MK_MASK_CONST(0xff)
+#define AHB_TIMEOUT_WCOAL_AVPC_0_WRITE_MASK                     _MK_MASK_CONST(0xff)
+#define AHB_TIMEOUT_WCOAL_AVPC_0_AVPCARM7W_WCOAL_TMVAL_SHIFT                    _MK_SHIFT_CONST(0)
+#define AHB_TIMEOUT_WCOAL_AVPC_0_AVPCARM7W_WCOAL_TMVAL_FIELD                    (_MK_MASK_CONST(0xff) << AHB_TIMEOUT_WCOAL_AVPC_0_AVPCARM7W_WCOAL_TMVAL_SHIFT)
+#define AHB_TIMEOUT_WCOAL_AVPC_0_AVPCARM7W_WCOAL_TMVAL_RANGE                    7:0
+#define AHB_TIMEOUT_WCOAL_AVPC_0_AVPCARM7W_WCOAL_TMVAL_WOFFSET                  0x0
+#define AHB_TIMEOUT_WCOAL_AVPC_0_AVPCARM7W_WCOAL_TMVAL_DEFAULT                  _MK_MASK_CONST(0x32)
+#define AHB_TIMEOUT_WCOAL_AVPC_0_AVPCARM7W_WCOAL_TMVAL_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
+#define AHB_TIMEOUT_WCOAL_AVPC_0_AVPCARM7W_WCOAL_TMVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_TIMEOUT_WCOAL_AVPC_0_AVPCARM7W_WCOAL_TMVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Reserved address 577 [0x241] 
+
+// Reserved address 578 [0x242] 
+
+// Reserved address 579 [0x243] 
+
+// Reserved address 580 [0x244] 
+
+// Reserved address 581 [0x245] 
+
+// Reserved address 582 [0x246] 
+
+// Reserved address 583 [0x247] 
+
+// Reserved address 584 [0x248] 
+
+// Reserved address 585 [0x249] 
+
+// Reserved address 586 [0x24a] 
+
+// Reserved address 587 [0x24b] 
+
+// Reserved address 588 [0x24c] 
+
+// Reserved address 589 [0x24d] 
+
+// Reserved address 590 [0x24e] 
+
+// Reserved address 591 [0x24f] 
+
+// Reserved address 592 [0x250] 
+
+// Reserved address 593 [0x251] 
+
+// Reserved address 594 [0x252] 
+
+// Reserved address 595 [0x253] 
+
+// Reserved address 596 [0x254] 
+
+// Reserved address 597 [0x255] 
+
+// Reserved address 598 [0x256] 
+
+// Reserved address 599 [0x257] 
+
+// Reserved address 600 [0x258] 
+
+// Reserved address 601 [0x259] 
+
+// Reserved address 602 [0x25a] 
+
+// Reserved address 603 [0x25b] 
+
+// Reserved address 604 [0x25c] 
+
+// Reserved address 605 [0x25d] 
+
+// Reserved address 606 [0x25e] 
+
+// Reserved address 607 [0x25f] 
+
+// Reserved address 608 [0x260] 
+
+// Reserved address 609 [0x261] 
+
+// Reserved address 610 [0x262] 
+
+// Reserved address 611 [0x263] 
+
+//
+// REGISTER LIST
+//
+#define LIST_ARAHB_ARBC_REGS(_op_) \
+_op_(AHB_ARBITRATION_DISABLE_0) \
+_op_(AHB_ARBITRATION_PRIORITY_CTRL_0) \
+_op_(AHB_ARBITRATION_USR_PROTECT_0) \
+_op_(AHB_GIZMO_AHB_MEM_0) \
+_op_(AHB_GIZMO_APB_DMA_0) \
+_op_(AHB_GIZMO_IDE_0) \
+_op_(AHB_GIZMO_USB_0) \
+_op_(AHB_GIZMO_AHB_XBAR_BRIDGE_0) \
+_op_(AHB_GIZMO_CPU_AHB_BRIDGE_0) \
+_op_(AHB_GIZMO_COP_AHB_BRIDGE_0) \
+_op_(AHB_GIZMO_XBAR_APB_CTLR_0) \
+_op_(AHB_GIZMO_VCP_AHB_BRIDGE_0) \
+_op_(AHB_GIZMO_NAND_0) \
+_op_(AHB_GIZMO_SDMMC4_0) \
+_op_(AHB_GIZMO_XIO_0) \
+_op_(AHB_GIZMO_BSEV_0) \
+_op_(AHB_GIZMO_BSEA_0) \
+_op_(AHB_GIZMO_NOR_0) \
+_op_(AHB_GIZMO_USB2_0) \
+_op_(AHB_GIZMO_USB3_0) \
+_op_(AHB_GIZMO_SDMMC1_0) \
+_op_(AHB_GIZMO_SDMMC2_0) \
+_op_(AHB_GIZMO_SDMMC3_0) \
+_op_(AHB_AHB_MEM_PREFETCH_CFG_X_0) \
+_op_(AHB_ARBITRATION_XBAR_CTRL_0) \
+_op_(AHB_AHB_MEM_PREFETCH_CFG3_0) \
+_op_(AHB_AHB_MEM_PREFETCH_CFG4_0) \
+_op_(AHB_AVP_PPCS_RD_COH_STATUS_0) \
+_op_(AHB_AHB_MEM_PREFETCH_CFG1_0) \
+_op_(AHB_AHB_MEM_PREFETCH_CFG2_0) \
+_op_(AHB_AHBSLVMEM_STATUS_0) \
+_op_(AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID_0) \
+_op_(AHB_ARBITRATION_CPU_ABORT_INFO_0) \
+_op_(AHB_ARBITRATION_CPU_ABORT_ADDR_0) \
+_op_(AHB_ARBITRATION_COP_ABORT_INFO_0) \
+_op_(AHB_ARBITRATION_COP_ABORT_ADDR_0) \
+_op_(AHB_AVPC_MCCIF_FIFOCTRL_0) \
+_op_(AHB_TIMEOUT_WCOAL_AVPC_0)
+
+
+//
+// ADDRESS SPACES
+//
+
+#define BASE_ADDRESS_AHB        0x00000000
+
+//
+// ARAHB_ARBC REGISTER BANKS
+//
+
+#define AHB0_FIRST_REG 0x0000 // AHB_ARBITRATION_DISABLE_0
+#define AHB0_LAST_REG 0x0010 // AHB_GIZMO_APB_DMA_0
+#define AHB1_FIRST_REG 0x0018 // AHB_GIZMO_IDE_0
+#define AHB1_LAST_REG 0x0030 // AHB_GIZMO_VCP_AHB_BRIDGE_0
+#define AHB2_FIRST_REG 0x003c // AHB_GIZMO_NAND_0
+#define AHB2_LAST_REG 0x003c // AHB_GIZMO_NAND_0
+#define AHB3_FIRST_REG 0x0044 // AHB_GIZMO_SDMMC4_0
+#define AHB3_LAST_REG 0x0048 // AHB_GIZMO_XIO_0
+#define AHB4_FIRST_REG 0x0060 // AHB_GIZMO_BSEV_0
+#define AHB4_LAST_REG 0x0060 // AHB_GIZMO_BSEV_0
+#define AHB5_FIRST_REG 0x0070 // AHB_GIZMO_BSEA_0
+#define AHB5_LAST_REG 0x0088 // AHB_GIZMO_SDMMC3_0
+#define AHB6_FIRST_REG 0x00d8 // AHB_AHB_MEM_PREFETCH_CFG_X_0
+#define AHB6_LAST_REG 0x0108 // AHB_ARBITRATION_COP_ABORT_ADDR_0
+#define AHB7_FIRST_REG 0x023c // AHB_AVPC_MCCIF_FIFOCTRL_0
+#define AHB7_LAST_REG 0x023c // AHB_AVPC_MCCIF_FIFOCTRL_0
+#define AHB8_FIRST_REG 0x0240 // AHB_TIMEOUT_WCOAL_AVPC_0
+#define AHB8_LAST_REG 0x0240 // AHB_TIMEOUT_WCOAL_AVPC_0
+
+#ifndef _MK_SHIFT_CONST
+  #define _MK_SHIFT_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_MASK_CONST
+  #define _MK_MASK_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_ENUM_CONST
+  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
+#endif
+#ifndef _MK_ADDR_CONST
+  #define _MK_ADDR_CONST(_constant_) _constant_
+#endif
+
+#endif // ifndef ___ARAHB_ARBC_H_INC_
diff --git a/arch/arm/mach-tegra/include/ap20/arapb_misc.h b/arch/arm/mach-tegra/include/ap20/arapb_misc.h
new file mode 100644
index 000000000000..e1e57e96bfc6
--- /dev/null
+++ b/arch/arm/mach-tegra/include/ap20/arapb_misc.h
@@ -0,0 +1,15362 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+//
+// DO NOT EDIT - generated by simspec!
+//
+
+#ifndef ___ARAPB_MISC_H_INC_
+#define ___ARAPB_MISC_H_INC_
+
+// Reserved address 0 [0x0] 
+
+// Reserved address 4 [0x4] 
+
+// Register APB_MISC_PP_STRAPPING_OPT_A_0  
+#define APB_MISC_PP_STRAPPING_OPT_A_0                   _MK_ADDR_CONST(0x8)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_SECURE                    0x0
+#define APB_MISC_PP_STRAPPING_OPT_A_0_WORD_COUNT                        0x1
+#define APB_MISC_PP_STRAPPING_OPT_A_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_RESET_MASK                        _MK_MASK_CONST(0x101)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_READ_MASK                         _MK_MASK_CONST(0x3fc001f1)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_WRITE_MASK                        _MK_MASK_CONST(0x3fc001f1)
+// read at power-on reset time from gmi_ad[15:12] strap pads.
+#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SELECT_SHIFT                 _MK_SHIFT_CONST(26)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SELECT_FIELD                 (_MK_MASK_CONST(0xf) << APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SELECT_SHIFT)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SELECT_RANGE                 29:26
+#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SELECT_WOFFSET                       0x0
+#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SELECT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SELECT_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SELECT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SELECT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// read at power-on reset time from gmi_hior strap pad
+#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SRC_USB_RECOVERY_MODE_SHIFT                  _MK_SHIFT_CONST(25)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SRC_USB_RECOVERY_MODE_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SRC_USB_RECOVERY_MODE_SHIFT)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SRC_USB_RECOVERY_MODE_RANGE                  25:25
+#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SRC_USB_RECOVERY_MODE_WOFFSET                        0x0
+#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SRC_USB_RECOVERY_MODE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SRC_USB_RECOVERY_MODE_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SRC_USB_RECOVERY_MODE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SRC_USB_RECOVERY_MODE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SRC_USB_RECOVERY_MODE_DISABLED                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SRC_USB_RECOVERY_MODE_ENABLED                        _MK_ENUM_CONST(1)
+
+// read at power-on reset time from gmi_hiow strap pad
+#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SRC_NOR_BOOT_SHIFT                   _MK_SHIFT_CONST(24)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SRC_NOR_BOOT_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SRC_NOR_BOOT_SHIFT)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SRC_NOR_BOOT_RANGE                   24:24
+#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SRC_NOR_BOOT_WOFFSET                 0x0
+#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SRC_NOR_BOOT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SRC_NOR_BOOT_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SRC_NOR_BOOT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SRC_NOR_BOOT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SRC_NOR_BOOT_IROM                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SRC_NOR_BOOT_NOR                     _MK_ENUM_CONST(1)
+
+// read at power-on reset time from {gmi_clk,gmi_adv_n} strap pads 00=Serial_JTAG, 01=CPU_only, 10=COP_only, 11=Serial_JTAG(same as 00 case)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_ARM_JTAG_SHIFT                    _MK_SHIFT_CONST(22)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_ARM_JTAG_FIELD                    (_MK_MASK_CONST(0x3) << APB_MISC_PP_STRAPPING_OPT_A_0_ARM_JTAG_SHIFT)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_ARM_JTAG_RANGE                    23:22
+#define APB_MISC_PP_STRAPPING_OPT_A_0_ARM_JTAG_WOFFSET                  0x0
+#define APB_MISC_PP_STRAPPING_OPT_A_0_ARM_JTAG_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_ARM_JTAG_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_ARM_JTAG_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_ARM_JTAG_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_ARM_JTAG_SERIAL                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_ARM_JTAG_CPU                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_ARM_JTAG_COP                      _MK_ENUM_CONST(2)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_ARM_JTAG_SERIAL_ALT                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_STRAPPING_OPT_A_0_MIO_WIDTH_SHIFT                   _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_MIO_WIDTH_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_PP_STRAPPING_OPT_A_0_MIO_WIDTH_SHIFT)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_MIO_WIDTH_RANGE                   8:8
+#define APB_MISC_PP_STRAPPING_OPT_A_0_MIO_WIDTH_WOFFSET                 0x0
+#define APB_MISC_PP_STRAPPING_OPT_A_0_MIO_WIDTH_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_MIO_WIDTH_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_MIO_WIDTH_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_MIO_WIDTH_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_MIO_WIDTH_INIT_ENUM                       RSVD1
+#define APB_MISC_PP_STRAPPING_OPT_A_0_MIO_WIDTH_RSVD1                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_MIO_WIDTH_RSVD2                   _MK_ENUM_CONST(1)
+
+// read at power-on reset time from gmi_ad[7:4] strap pads
+// In emulation (HIDREV_MAJORREV==0), this field indicates the RAM type connected.
+// For   QT (HIDREV_MINORREV==0): 0=SIM, 1=DDR, 2=DDR2, 3=LPDDR2
+// For FPGA (HIDREV_MINORREV==1): 0=SIM, 1=DDR, 2=DDR2, 3=LPDDR2
+#define APB_MISC_PP_STRAPPING_OPT_A_0_RAM_CODE_SHIFT                    _MK_SHIFT_CONST(4)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_RAM_CODE_FIELD                    (_MK_MASK_CONST(0xf) << APB_MISC_PP_STRAPPING_OPT_A_0_RAM_CODE_SHIFT)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_RAM_CODE_RANGE                    7:4
+#define APB_MISC_PP_STRAPPING_OPT_A_0_RAM_CODE_WOFFSET                  0x0
+#define APB_MISC_PP_STRAPPING_OPT_A_0_RAM_CODE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_RAM_CODE_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_RAM_CODE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_RAM_CODE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_PP_STRAPPING_OPT_A_0_NOR_WIDTH_SHIFT                   _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_NOR_WIDTH_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_PP_STRAPPING_OPT_A_0_NOR_WIDTH_SHIFT)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_NOR_WIDTH_RANGE                   0:0
+#define APB_MISC_PP_STRAPPING_OPT_A_0_NOR_WIDTH_WOFFSET                 0x0
+#define APB_MISC_PP_STRAPPING_OPT_A_0_NOR_WIDTH_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_NOR_WIDTH_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_NOR_WIDTH_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_NOR_WIDTH_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_NOR_WIDTH_INIT_ENUM                       RSVD1
+#define APB_MISC_PP_STRAPPING_OPT_A_0_NOR_WIDTH_RSVD1                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_NOR_WIDTH_RSVD2                   _MK_ENUM_CONST(1)
+
+
+// Reserved address 12 [0xc] 
+
+// Reserved address 16 [0x10] 
+
+// Register APB_MISC_PP_TRISTATE_REG_A_0  
+#define APB_MISC_PP_TRISTATE_REG_A_0                    _MK_ADDR_CONST(0x14)
+#define APB_MISC_PP_TRISTATE_REG_A_0_SECURE                     0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_WORD_COUNT                         0x1
+#define APB_MISC_PP_TRISTATE_REG_A_0_RESET_VAL                  _MK_MASK_CONST(0xc01bfff0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_TRISTATE_REG_A_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_TRISTATE_REG_A_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_OWC_SHIFT                        _MK_SHIFT_CONST(31)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_OWC_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_OWC_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_OWC_RANGE                        31:31
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_OWC_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_OWC_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_OWC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_OWC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_OWC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_OWC_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_OWC_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_OWC_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_SDIO1_SHIFT                      _MK_SHIFT_CONST(30)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_SDIO1_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_SDIO1_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_SDIO1_RANGE                      30:30
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_SDIO1_WOFFSET                    0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_SDIO1_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_SDIO1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_SDIO1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_SDIO1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_SDIO1_INIT_ENUM                  TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_SDIO1_NORMAL                     _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_SDIO1_TRISTATE                   _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GMC_SHIFT                        _MK_SHIFT_CONST(29)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GMC_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_GMC_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GMC_RANGE                        29:29
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GMC_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GMC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GMC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GMC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GMC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GMC_INIT_ENUM                    NORMAL
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GMC_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GMC_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GMA_SHIFT                        _MK_SHIFT_CONST(28)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GMA_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_GMA_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GMA_RANGE                        28:28
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GMA_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GMA_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GMA_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GMA_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GMA_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GMA_INIT_ENUM                    NORMAL
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GMA_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GMA_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCF_SHIFT                       _MK_SHIFT_CONST(27)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCF_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCF_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCF_RANGE                       27:27
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCF_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCF_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCF_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCF_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCF_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCF_INIT_ENUM                   NORMAL
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCF_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCF_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCE_SHIFT                       _MK_SHIFT_CONST(26)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCE_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCE_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCE_RANGE                       26:26
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCE_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCE_INIT_ENUM                   NORMAL
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCE_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCE_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_RM_SHIFT                 _MK_SHIFT_CONST(25)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_RM_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_RM_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_RM_RANGE                 25:25
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_RM_WOFFSET                       0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_RM_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_RM_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_RM_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_RM_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_RM_INIT_ENUM                     NORMAL
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_RM_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_RM_TRISTATE                      _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PTA_SHIFT                        _MK_SHIFT_CONST(24)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PTA_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_PTA_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PTA_RANGE                        24:24
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PTA_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PTA_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PTA_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PTA_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PTA_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PTA_INIT_ENUM                    NORMAL
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PTA_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PTA_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PMC_SHIFT                        _MK_SHIFT_CONST(23)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PMC_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_PMC_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PMC_RANGE                        23:23
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PMC_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PMC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PMC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PMC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PMC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PMC_INIT_ENUM                    NORMAL
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PMC_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PMC_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCA_SHIFT                       _MK_SHIFT_CONST(22)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCA_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCA_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCA_RANGE                       22:22
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCA_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCA_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCA_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCA_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCA_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCA_INIT_ENUM                   NORMAL
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCA_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCA_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCB_SHIFT                       _MK_SHIFT_CONST(21)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCB_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCB_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCB_RANGE                       21:21
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCB_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCB_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCB_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCB_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCB_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCB_INIT_ENUM                   NORMAL
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCB_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCB_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRRX_SHIFT                       _MK_SHIFT_CONST(20)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRRX_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_IRRX_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRRX_RANGE                       20:20
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRRX_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRRX_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRRX_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRRX_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRRX_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRRX_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRRX_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRRX_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRTX_SHIFT                       _MK_SHIFT_CONST(19)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRTX_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_IRTX_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRTX_RANGE                       19:19
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRTX_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRTX_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRTX_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRTX_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRTX_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRTX_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRTX_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRTX_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_I2CP_SHIFT                       _MK_SHIFT_CONST(18)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_I2CP_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_I2CP_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_I2CP_RANGE                       18:18
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_I2CP_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_I2CP_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_I2CP_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_I2CP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_I2CP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_I2CP_INIT_ENUM                   NORMAL
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_I2CP_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_I2CP_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPV_SHIFT                        _MK_SHIFT_CONST(17)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPV_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_GPV_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPV_RANGE                        17:17
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPV_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPV_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPV_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPV_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPV_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPV_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPV_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPV_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPU_SHIFT                        _MK_SHIFT_CONST(16)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPU_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_GPU_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPU_RANGE                        16:16
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPU_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPU_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPU_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPU_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPU_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPU_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPU_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPU_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTE_SHIFT                        _MK_SHIFT_CONST(15)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTE_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_DTE_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTE_RANGE                        15:15
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTE_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTE_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTE_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTE_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTE_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTD_SHIFT                        _MK_SHIFT_CONST(14)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTD_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_DTD_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTD_RANGE                        14:14
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTD_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTD_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTD_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTD_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTD_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTD_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTC_SHIFT                        _MK_SHIFT_CONST(13)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTC_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_DTC_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTC_RANGE                        13:13
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTC_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTC_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTC_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTC_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTC_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTB_SHIFT                        _MK_SHIFT_CONST(12)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTB_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_DTB_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTB_RANGE                        12:12
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTB_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTB_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTB_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTB_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTB_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTB_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTB_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTB_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTA_SHIFT                        _MK_SHIFT_CONST(11)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTA_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_DTA_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTA_RANGE                        11:11
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTA_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTA_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTA_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTA_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTA_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTA_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTA_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTA_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP4_SHIFT                       _MK_SHIFT_CONST(10)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP4_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP4_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP4_RANGE                       10:10
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP4_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP4_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP4_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP4_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP4_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP3_SHIFT                       _MK_SHIFT_CONST(9)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP3_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP3_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP3_RANGE                       9:9
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP3_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP3_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP3_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP3_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP3_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP2_SHIFT                       _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP2_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP2_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP2_RANGE                       8:8
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP2_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP2_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP2_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP2_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP2_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP1_SHIFT                       _MK_SHIFT_CONST(7)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP1_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP1_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP1_RANGE                       7:7
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP1_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP1_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP1_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP1_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP1_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CSUS_SHIFT                       _MK_SHIFT_CONST(6)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CSUS_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_CSUS_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CSUS_RANGE                       6:6
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CSUS_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CSUS_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CSUS_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CSUS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CSUS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CSUS_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CSUS_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CSUS_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV2_SHIFT                      _MK_SHIFT_CONST(5)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV2_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV2_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV2_RANGE                      5:5
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV2_WOFFSET                    0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV2_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV2_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV2_INIT_ENUM                  TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV2_NORMAL                     _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV2_TRISTATE                   _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV1_SHIFT                      _MK_SHIFT_CONST(4)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV1_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV1_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV1_RANGE                      4:4
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV1_WOFFSET                    0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV1_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV1_INIT_ENUM                  TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV1_NORMAL                     _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV1_TRISTATE                   _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATD_SHIFT                        _MK_SHIFT_CONST(3)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATD_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_ATD_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATD_RANGE                        3:3
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATD_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATD_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATD_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATD_INIT_ENUM                    NORMAL
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATD_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATD_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATC_SHIFT                        _MK_SHIFT_CONST(2)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATC_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_ATC_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATC_RANGE                        2:2
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATC_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATC_INIT_ENUM                    NORMAL
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATC_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATC_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATB_SHIFT                        _MK_SHIFT_CONST(1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATB_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_ATB_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATB_RANGE                        1:1
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATB_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATB_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATB_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATB_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATB_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATB_INIT_ENUM                    NORMAL
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATB_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATB_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATA_SHIFT                        _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATA_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_ATA_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATA_RANGE                        0:0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATA_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATA_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATA_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATA_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATA_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATA_INIT_ENUM                    NORMAL
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATA_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATA_TRISTATE                     _MK_ENUM_CONST(1)
+
+
+// Register APB_MISC_PP_TRISTATE_REG_B_0  
+#define APB_MISC_PP_TRISTATE_REG_B_0                    _MK_ADDR_CONST(0x18)
+#define APB_MISC_PP_TRISTATE_REG_B_0_SECURE                     0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_WORD_COUNT                         0x1
+#define APB_MISC_PP_TRISTATE_REG_B_0_RESET_VAL                  _MK_MASK_CONST(0xffefee)
+#define APB_MISC_PP_TRISTATE_REG_B_0_RESET_MASK                         _MK_MASK_CONST(0xe6ffffef)
+#define APB_MISC_PP_TRISTATE_REG_B_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_READ_MASK                  _MK_MASK_CONST(0xe6ffffef)
+#define APB_MISC_PP_TRISTATE_REG_B_0_WRITE_MASK                         _MK_MASK_CONST(0xe6ffffef)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_DDC_SHIFT                        _MK_SHIFT_CONST(31)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_DDC_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_DDC_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_DDC_RANGE                        31:31
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_DDC_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_DDC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_DDC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_DDC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_DDC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_DDC_INIT_ENUM                    NORMAL
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_DDC_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_DDC_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_GMD_SHIFT                        _MK_SHIFT_CONST(30)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_GMD_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_GMD_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_GMD_RANGE                        30:30
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_GMD_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_GMD_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_GMD_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_GMD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_GMD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_GMD_INIT_ENUM                    NORMAL
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_GMD_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_GMD_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_GMB_SHIFT                        _MK_SHIFT_CONST(29)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_GMB_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_GMB_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_GMB_RANGE                        29:29
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_GMB_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_GMB_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_GMB_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_GMB_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_GMB_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_GMB_INIT_ENUM                    NORMAL
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_GMB_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_GMB_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_KBCC_SHIFT                       _MK_SHIFT_CONST(26)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_KBCC_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_KBCC_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_KBCC_RANGE                       26:26
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_KBCC_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_KBCC_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_KBCC_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_KBCC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_KBCC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_KBCC_INIT_ENUM                   NORMAL
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_KBCC_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_KBCC_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_ATE_SHIFT                        _MK_SHIFT_CONST(25)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_ATE_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_ATE_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_ATE_RANGE                        25:25
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_ATE_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_ATE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_ATE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_ATE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_ATE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_ATE_INIT_ENUM                    NORMAL
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_ATE_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_ATE_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCB_SHIFT                        _MK_SHIFT_CONST(23)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCB_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_UCB_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCB_RANGE                        23:23
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCB_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCB_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCB_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCB_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCB_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCB_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCB_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCB_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCA_SHIFT                        _MK_SHIFT_CONST(22)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCA_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_UCA_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCA_RANGE                        22:22
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCA_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCA_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCA_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCA_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCA_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCA_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCA_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCA_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAD_SHIFT                        _MK_SHIFT_CONST(21)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAD_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_UAD_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAD_RANGE                        21:21
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAD_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAD_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAD_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAD_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAD_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAD_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAC_SHIFT                        _MK_SHIFT_CONST(20)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAC_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_UAC_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAC_RANGE                        20:20
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAC_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAC_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAC_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAC_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAC_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAB_SHIFT                        _MK_SHIFT_CONST(19)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAB_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_UAB_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAB_RANGE                        19:19
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAB_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAB_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAB_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAB_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAB_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAB_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAB_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAB_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAA_SHIFT                        _MK_SHIFT_CONST(18)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAA_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_UAA_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAA_RANGE                        18:18
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAA_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAA_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAA_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAA_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAA_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAA_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAA_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAA_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIH_SHIFT                       _MK_SHIFT_CONST(17)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIH_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIH_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIH_RANGE                       17:17
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIH_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIH_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIH_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIH_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIH_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIH_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIH_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIH_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIG_SHIFT                       _MK_SHIFT_CONST(16)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIG_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIG_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIG_RANGE                       16:16
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIG_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIG_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIG_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIG_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIG_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIG_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIG_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIG_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIF_SHIFT                       _MK_SHIFT_CONST(15)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIF_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIF_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIF_RANGE                       15:15
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIF_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIF_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIF_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIF_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIF_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIF_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIF_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIF_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIE_SHIFT                       _MK_SHIFT_CONST(14)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIE_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIE_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIE_RANGE                       14:14
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIE_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIE_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIE_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIE_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIE_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPID_SHIFT                       _MK_SHIFT_CONST(13)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPID_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_SPID_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPID_RANGE                       13:13
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPID_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPID_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPID_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPID_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPID_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPID_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPID_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPID_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIC_SHIFT                       _MK_SHIFT_CONST(12)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIC_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIC_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIC_RANGE                       12:12
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIC_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIC_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIC_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIC_INIT_ENUM                   NORMAL
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIC_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIC_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIB_SHIFT                       _MK_SHIFT_CONST(11)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIB_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIB_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIB_RANGE                       11:11
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIB_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIB_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIB_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIB_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIB_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIB_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIB_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIB_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIA_SHIFT                       _MK_SHIFT_CONST(10)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIA_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIA_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIA_RANGE                       10:10
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIA_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIA_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIA_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIA_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIA_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIA_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIA_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIA_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDO_SHIFT                       _MK_SHIFT_CONST(9)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDO_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDO_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDO_RANGE                       9:9
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDO_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDO_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDO_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDO_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDO_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDO_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDO_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDO_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDI_SHIFT                       _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDI_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDI_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDI_RANGE                       8:8
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDI_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDI_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDI_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDI_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDI_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDI_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDI_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDI_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXK_SHIFT                       _MK_SHIFT_CONST(7)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXK_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXK_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXK_RANGE                       7:7
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXK_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXK_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXK_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXK_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXK_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXD_SHIFT                       _MK_SHIFT_CONST(6)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXD_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXD_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXD_RANGE                       6:6
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXD_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXD_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXD_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXD_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXD_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXD_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXC_SHIFT                       _MK_SHIFT_CONST(5)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXC_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXC_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXC_RANGE                       5:5
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXC_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXC_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXC_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXC_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXC_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXC_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXA_SHIFT                       _MK_SHIFT_CONST(3)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXA_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXA_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXA_RANGE                       3:3
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXA_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXA_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXA_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXA_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXA_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXA_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXA_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXA_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDD_SHIFT                        _MK_SHIFT_CONST(2)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDD_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_SDD_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDD_RANGE                        2:2
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDD_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDD_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDD_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDD_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDD_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDD_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDC_SHIFT                        _MK_SHIFT_CONST(1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDC_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_SDC_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDC_RANGE                        1:1
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDC_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDC_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDC_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDC_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDC_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_GME_SHIFT                        _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_GME_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_GME_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_GME_RANGE                        0:0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_GME_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_GME_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_GME_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_GME_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_GME_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_GME_INIT_ENUM                    NORMAL
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_GME_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_GME_TRISTATE                     _MK_ENUM_CONST(1)
+
+
+// Register APB_MISC_PP_TRISTATE_REG_C_0  
+#define APB_MISC_PP_TRISTATE_REG_C_0                    _MK_ADDR_CONST(0x1c)
+#define APB_MISC_PP_TRISTATE_REG_C_0_SECURE                     0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_WORD_COUNT                         0x1
+#define APB_MISC_PP_TRISTATE_REG_C_0_RESET_VAL                  _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_TRISTATE_REG_C_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_TRISTATE_REG_C_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_TRISTATE_REG_C_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LCSN_SHIFT                       _MK_SHIFT_CONST(31)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LCSN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LCSN_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LCSN_RANGE                       31:31
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LCSN_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LCSN_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LCSN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LCSN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LCSN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LCSN_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LCSN_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LCSN_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LDC_SHIFT                        _MK_SHIFT_CONST(30)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LDC_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LDC_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LDC_RANGE                        30:30
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LDC_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LDC_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LDC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LDC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LDC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LDC_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LDC_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LDC_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSCK_SHIFT                       _MK_SHIFT_CONST(29)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSCK_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LSCK_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSCK_RANGE                       29:29
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSCK_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSCK_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSCK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSCK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSCK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSCK_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSCK_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSCK_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC1_SHIFT                       _MK_SHIFT_CONST(28)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC1_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC1_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC1_RANGE                       28:28
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC1_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC1_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC1_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC1_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC1_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC0_SHIFT                       _MK_SHIFT_CONST(27)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC0_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC0_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC0_RANGE                       27:27
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC0_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC0_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC0_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC0_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC0_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVS_SHIFT                        _MK_SHIFT_CONST(26)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVS_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LVS_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVS_RANGE                        26:26
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVS_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVS_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVS_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVS_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVS_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVS_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM1_SHIFT                        _MK_SHIFT_CONST(25)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM1_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LM1_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM1_RANGE                        25:25
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM1_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM1_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM1_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM1_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM1_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM1_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM0_SHIFT                        _MK_SHIFT_CONST(24)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM0_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LM0_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM0_RANGE                        24:24
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM0_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM0_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM0_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM0_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM0_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM0_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_HDINT_SHIFT                      _MK_SHIFT_CONST(23)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_HDINT_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_HDINT_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_HDINT_RANGE                      23:23
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_HDINT_WOFFSET                    0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_HDINT_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_HDINT_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_HDINT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_HDINT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_HDINT_INIT_ENUM                  TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_HDINT_NORMAL                     _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_HDINT_TRISTATE                   _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP1_SHIFT                       _MK_SHIFT_CONST(22)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP1_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP1_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP1_RANGE                       22:22
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP1_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP1_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP1_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP1_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP1_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP0_SHIFT                       _MK_SHIFT_CONST(21)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP0_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP0_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP0_RANGE                       21:21
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP0_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP0_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP0_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP0_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP0_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP2_SHIFT                       _MK_SHIFT_CONST(20)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP2_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP2_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP2_RANGE                       20:20
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP2_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP2_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP2_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP2_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP2_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP1_SHIFT                       _MK_SHIFT_CONST(19)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP1_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP1_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP1_RANGE                       19:19
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP1_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP1_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP1_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP1_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP1_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP0_SHIFT                       _MK_SHIFT_CONST(18)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP0_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP0_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP0_RANGE                       18:18
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP0_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP0_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP0_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP0_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP0_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD17_SHIFT                       _MK_SHIFT_CONST(17)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD17_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LD17_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD17_RANGE                       17:17
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD17_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD17_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD17_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD17_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD17_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD17_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD17_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD17_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD16_SHIFT                       _MK_SHIFT_CONST(16)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD16_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LD16_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD16_RANGE                       16:16
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD16_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD16_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD16_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD16_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD16_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD16_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD16_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD16_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD15_SHIFT                       _MK_SHIFT_CONST(15)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD15_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LD15_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD15_RANGE                       15:15
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD15_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD15_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD15_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD15_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD15_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD15_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD15_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD15_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD14_SHIFT                       _MK_SHIFT_CONST(14)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD14_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LD14_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD14_RANGE                       14:14
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD14_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD14_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD14_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD14_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD14_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD14_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD14_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD14_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD13_SHIFT                       _MK_SHIFT_CONST(13)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD13_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LD13_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD13_RANGE                       13:13
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD13_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD13_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD13_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD13_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD13_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD13_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD13_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD13_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD12_SHIFT                       _MK_SHIFT_CONST(12)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD12_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LD12_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD12_RANGE                       12:12
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD12_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD12_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD12_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD12_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD12_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD12_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD12_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD12_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD11_SHIFT                       _MK_SHIFT_CONST(11)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD11_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LD11_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD11_RANGE                       11:11
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD11_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD11_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD11_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD11_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD11_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD11_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD11_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD11_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD10_SHIFT                       _MK_SHIFT_CONST(10)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD10_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LD10_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD10_RANGE                       10:10
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD10_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD10_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD10_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD10_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD10_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD10_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD10_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD10_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD9_SHIFT                        _MK_SHIFT_CONST(9)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD9_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LD9_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD9_RANGE                        9:9
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD9_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD9_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD9_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD9_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD9_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD9_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD9_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD9_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD8_SHIFT                        _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD8_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LD8_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD8_RANGE                        8:8
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD8_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD8_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD8_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD8_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD8_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD8_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD7_SHIFT                        _MK_SHIFT_CONST(7)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD7_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LD7_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD7_RANGE                        7:7
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD7_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD7_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD7_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD7_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD7_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD7_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD6_SHIFT                        _MK_SHIFT_CONST(6)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD6_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LD6_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD6_RANGE                        6:6
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD6_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD6_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD6_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD6_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD6_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD6_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD5_SHIFT                        _MK_SHIFT_CONST(5)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD5_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LD5_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD5_RANGE                        5:5
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD5_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD5_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD5_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD5_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD5_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD5_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD4_SHIFT                        _MK_SHIFT_CONST(4)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD4_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LD4_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD4_RANGE                        4:4
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD4_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD4_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD4_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD4_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD4_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD4_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD3_SHIFT                        _MK_SHIFT_CONST(3)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD3_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LD3_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD3_RANGE                        3:3
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD3_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD3_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD3_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD3_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD3_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD3_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD2_SHIFT                        _MK_SHIFT_CONST(2)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD2_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LD2_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD2_RANGE                        2:2
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD2_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD2_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD2_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD2_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD2_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD2_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD1_SHIFT                        _MK_SHIFT_CONST(1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD1_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LD1_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD1_RANGE                        1:1
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD1_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD1_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD1_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD1_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD1_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD1_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD0_SHIFT                        _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD0_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LD0_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD0_RANGE                        0:0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD0_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD0_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD0_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD0_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD0_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD0_TRISTATE                     _MK_ENUM_CONST(1)
+
+
+// Register APB_MISC_PP_TRISTATE_REG_D_0  
+#define APB_MISC_PP_TRISTATE_REG_D_0                    _MK_ADDR_CONST(0x20)
+#define APB_MISC_PP_TRISTATE_REG_D_0_SECURE                     0x0
+#define APB_MISC_PP_TRISTATE_REG_D_0_WORD_COUNT                         0x1
+#define APB_MISC_PP_TRISTATE_REG_D_0_RESET_VAL                  _MK_MASK_CONST(0xf1ff)
+#define APB_MISC_PP_TRISTATE_REG_D_0_RESET_MASK                         _MK_MASK_CONST(0xfdff)
+#define APB_MISC_PP_TRISTATE_REG_D_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_READ_MASK                  _MK_MASK_CONST(0xfdff)
+#define APB_MISC_PP_TRISTATE_REG_D_0_WRITE_MASK                         _MK_MASK_CONST(0xfdff)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_SDB_SHIFT                        _MK_SHIFT_CONST(15)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_SDB_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_D_0_Z_SDB_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_SDB_RANGE                        15:15
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_SDB_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_SDB_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_SDB_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_SDB_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_SDB_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_SDB_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_SDB_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_SDB_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_CRTP_SHIFT                       _MK_SHIFT_CONST(14)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_CRTP_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_D_0_Z_CRTP_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_CRTP_RANGE                       14:14
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_CRTP_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_CRTP_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_CRTP_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_CRTP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_CRTP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_CRTP_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_CRTP_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_CRTP_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_UDA_SHIFT                        _MK_SHIFT_CONST(13)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_UDA_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_D_0_Z_UDA_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_UDA_RANGE                        13:13
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_UDA_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_UDA_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_UDA_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_UDA_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_UDA_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_UDA_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_UDA_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_UDA_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_DTF_SHIFT                        _MK_SHIFT_CONST(12)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_DTF_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_D_0_Z_DTF_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_DTF_RANGE                        12:12
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_DTF_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_DTF_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_DTF_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_DTF_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_DTF_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_DTF_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_DTF_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_DTF_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_GPU7_SHIFT                       _MK_SHIFT_CONST(11)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_GPU7_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_D_0_Z_GPU7_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_GPU7_RANGE                       11:11
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_GPU7_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_GPU7_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_GPU7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_GPU7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_GPU7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_GPU7_INIT_ENUM                   NORMAL
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_GPU7_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_GPU7_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_KBCD_SHIFT                       _MK_SHIFT_CONST(10)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_KBCD_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_D_0_Z_KBCD_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_KBCD_RANGE                       10:10
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_KBCD_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_KBCD_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_KBCD_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_KBCD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_KBCD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_KBCD_INIT_ENUM                   NORMAL
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_KBCD_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_KBCD_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPP_SHIFT                        _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPP_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_D_0_Z_LPP_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPP_RANGE                        8:8
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPP_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPP_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPP_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPP_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPP_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPP_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LHS_SHIFT                        _MK_SHIFT_CONST(7)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LHS_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_D_0_Z_LHS_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LHS_RANGE                        7:7
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LHS_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LHS_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LHS_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LHS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LHS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LHS_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LHS_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LHS_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LDI_SHIFT                        _MK_SHIFT_CONST(6)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LDI_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_D_0_Z_LDI_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LDI_RANGE                        6:6
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LDI_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LDI_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LDI_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LDI_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LDI_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LDI_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LDI_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LDI_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW2_SHIFT                       _MK_SHIFT_CONST(5)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW2_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW2_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW2_RANGE                       5:5
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW2_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW2_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW2_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW2_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW2_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW1_SHIFT                       _MK_SHIFT_CONST(4)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW1_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW1_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW1_RANGE                       4:4
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW1_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW1_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW1_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW1_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW1_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW0_SHIFT                       _MK_SHIFT_CONST(3)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW0_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW0_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW0_RANGE                       3:3
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW0_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW0_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW0_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW0_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW0_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDI_SHIFT                       _MK_SHIFT_CONST(2)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDI_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDI_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDI_RANGE                       2:2
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDI_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDI_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDI_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDI_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDI_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDI_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDI_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDI_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDA_SHIFT                       _MK_SHIFT_CONST(1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDA_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDA_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDA_RANGE                       1:1
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDA_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDA_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDA_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDA_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDA_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDA_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDA_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDA_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSPI_SHIFT                       _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSPI_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_D_0_Z_LSPI_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSPI_RANGE                       0:0
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSPI_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSPI_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSPI_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSPI_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSPI_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSPI_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSPI_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSPI_TRISTATE                    _MK_ENUM_CONST(1)
+
+
+// Register APB_MISC_PP_CONFIG_CTL_0  
+#define APB_MISC_PP_CONFIG_CTL_0                        _MK_ADDR_CONST(0x24)
+#define APB_MISC_PP_CONFIG_CTL_0_SECURE                         0x0
+#define APB_MISC_PP_CONFIG_CTL_0_WORD_COUNT                     0x1
+#define APB_MISC_PP_CONFIG_CTL_0_RESET_VAL                      _MK_MASK_CONST(0x40)
+#define APB_MISC_PP_CONFIG_CTL_0_RESET_MASK                     _MK_MASK_CONST(0xc0)
+#define APB_MISC_PP_CONFIG_CTL_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_CONFIG_CTL_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_CONFIG_CTL_0_READ_MASK                      _MK_MASK_CONST(0xc0)
+#define APB_MISC_PP_CONFIG_CTL_0_WRITE_MASK                     _MK_MASK_CONST(0xc0)
+//  0 = Disable ; 1 = Enable RTCK Daisychaining
+#define APB_MISC_PP_CONFIG_CTL_0_TBE_SHIFT                      _MK_SHIFT_CONST(7)
+#define APB_MISC_PP_CONFIG_CTL_0_TBE_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_PP_CONFIG_CTL_0_TBE_SHIFT)
+#define APB_MISC_PP_CONFIG_CTL_0_TBE_RANGE                      7:7
+#define APB_MISC_PP_CONFIG_CTL_0_TBE_WOFFSET                    0x0
+#define APB_MISC_PP_CONFIG_CTL_0_TBE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_CONFIG_CTL_0_TBE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_CONFIG_CTL_0_TBE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_CONFIG_CTL_0_TBE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_CONFIG_CTL_0_TBE_INIT_ENUM                  DISABLE
+#define APB_MISC_PP_CONFIG_CTL_0_TBE_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_CONFIG_CTL_0_TBE_ENABLE                     _MK_ENUM_CONST(1)
+
+//  0 = Disable Debug ; 1 = Enable JTAG DBGEN
+#define APB_MISC_PP_CONFIG_CTL_0_JTAG_SHIFT                     _MK_SHIFT_CONST(6)
+#define APB_MISC_PP_CONFIG_CTL_0_JTAG_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_PP_CONFIG_CTL_0_JTAG_SHIFT)
+#define APB_MISC_PP_CONFIG_CTL_0_JTAG_RANGE                     6:6
+#define APB_MISC_PP_CONFIG_CTL_0_JTAG_WOFFSET                   0x0
+#define APB_MISC_PP_CONFIG_CTL_0_JTAG_DEFAULT                   _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_CONFIG_CTL_0_JTAG_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_CONFIG_CTL_0_JTAG_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_CONFIG_CTL_0_JTAG_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_CONFIG_CTL_0_JTAG_INIT_ENUM                 ENABLE
+#define APB_MISC_PP_CONFIG_CTL_0_JTAG_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_CONFIG_CTL_0_JTAG_ENABLE                    _MK_ENUM_CONST(1)
+
+
+// Register APB_MISC_PP_MISC_USB_OTG_0  
+#define APB_MISC_PP_MISC_USB_OTG_0                      _MK_ADDR_CONST(0x28)
+#define APB_MISC_PP_MISC_USB_OTG_0_SECURE                       0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_WORD_COUNT                   0x1
+#define APB_MISC_PP_MISC_USB_OTG_0_RESET_VAL                    _MK_MASK_CONST(0x1000)
+#define APB_MISC_PP_MISC_USB_OTG_0_RESET_MASK                   _MK_MASK_CONST(0xc3ffffff)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_READ_MASK                    _MK_MASK_CONST(0xc3ffffff)
+#define APB_MISC_PP_MISC_USB_OTG_0_WRITE_MASK                   _MK_MASK_CONST(0xc07fff29)
+// Wake on Disconnect Enable (device mode)
+// When enabled (1), USB PHY will wakeup
+// from suspend on a disconnect event.
+#define APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_DISCON_EN_SHIFT                      _MK_SHIFT_CONST(31)
+#define APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_DISCON_EN_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_DISCON_EN_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_DISCON_EN_RANGE                      31:31
+#define APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_DISCON_EN_WOFFSET                    0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_DISCON_EN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_DISCON_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_DISCON_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_DISCON_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_DISCON_EN_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_DISCON_EN_ENABLE                     _MK_ENUM_CONST(1)
+
+// Wake on Connect Enable (device mode)
+// When enabled (1), USB PHY will wakeup
+// from suspend on a connect event.
+#define APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_CNNT_EN_SHIFT                        _MK_SHIFT_CONST(30)
+#define APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_CNNT_EN_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_CNNT_EN_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_CNNT_EN_RANGE                        30:30
+#define APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_CNNT_EN_WOFFSET                      0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_CNNT_EN_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_CNNT_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_CNNT_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_CNNT_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_CNNT_EN_DISABLE                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_CNNT_EN_ENABLE                       _MK_ENUM_CONST(1)
+
+// B_SESS_END status from USB PHY.
+// This field is the same as the field
+// B_SESS_END_STS in register USB_PHY_VBUS_SENSORS.
+#define APB_MISC_PP_MISC_USB_OTG_0_B_SESS_END_STS2_SHIFT                        _MK_SHIFT_CONST(25)
+#define APB_MISC_PP_MISC_USB_OTG_0_B_SESS_END_STS2_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_B_SESS_END_STS2_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_B_SESS_END_STS2_RANGE                        25:25
+#define APB_MISC_PP_MISC_USB_OTG_0_B_SESS_END_STS2_WOFFSET                      0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_B_SESS_END_STS2_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_B_SESS_END_STS2_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_B_SESS_END_STS2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_B_SESS_END_STS2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_B_SESS_END_STS2_UNSET                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_B_SESS_END_STS2_SET                  _MK_ENUM_CONST(1)
+
+// A_VBUS_VLD status from USB PHY.
+// This field is the same as the field
+// A_VBUS_VLD_STS in register USB_PHY_VBUS_SENSORS.
+#define APB_MISC_PP_MISC_USB_OTG_0_A_VBUS_VLD_STS2_SHIFT                        _MK_SHIFT_CONST(24)
+#define APB_MISC_PP_MISC_USB_OTG_0_A_VBUS_VLD_STS2_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_A_VBUS_VLD_STS2_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_A_VBUS_VLD_STS2_RANGE                        24:24
+#define APB_MISC_PP_MISC_USB_OTG_0_A_VBUS_VLD_STS2_WOFFSET                      0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_A_VBUS_VLD_STS2_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_A_VBUS_VLD_STS2_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_A_VBUS_VLD_STS2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_A_VBUS_VLD_STS2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_A_VBUS_VLD_STS2_UNSET                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_A_VBUS_VLD_STS2_SET                  _MK_ENUM_CONST(1)
+
+// A_SESS_VLD status from USB PHY.
+// This field is the same as the field
+// A_SESS_VLD_STS in register USB_PHY_VBUS_SENSORS.
+#define APB_MISC_PP_MISC_USB_OTG_0_A_SESS_VLD_STS2_SHIFT                        _MK_SHIFT_CONST(23)
+#define APB_MISC_PP_MISC_USB_OTG_0_A_SESS_VLD_STS2_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_A_SESS_VLD_STS2_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_A_SESS_VLD_STS2_RANGE                        23:23
+#define APB_MISC_PP_MISC_USB_OTG_0_A_SESS_VLD_STS2_WOFFSET                      0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_A_SESS_VLD_STS2_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_A_SESS_VLD_STS2_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_A_SESS_VLD_STS2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_A_SESS_VLD_STS2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_A_SESS_VLD_STS2_UNSET                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_A_SESS_VLD_STS2_SET                  _MK_ENUM_CONST(1)
+
+// Software_B_SESS_END status.
+// Software should write the appropriate
+// value (1/0) to set/unset the B_SESS_END status.
+// This field is the same as the field
+// B_SESS_END_SW_VALUE in register USB_PHY_VBUS_SENSORS.
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_SHIFT                  _MK_SHIFT_CONST(22)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_RANGE                  22:22
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_WOFFSET                        0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_UNSET                  _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_SET                    _MK_ENUM_CONST(1)
+
+// Enable Software Controlled B_SESS_END.
+// Software sets this bit to drive the
+// value in  SW_B_SESS_END to the USB
+// controller
+// This field is the same as the field
+// B_SESS_END_SW_EN in register USB_PHY_VBUS_SENSORS.
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_EN_SHIFT                       _MK_SHIFT_CONST(21)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_EN_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_EN_RANGE                       21:21
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_EN_WOFFSET                     0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// Software_A_VBUS_VLD status.
+// Software should write the appropriate
+// value (1/0) to set/unset the A_VBUS_VLD status.
+// This field is the same as the field
+// A_VBUS_VLD_SW_VALUE in register USB_PHY_VBUS_SENSORS.
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_SHIFT                  _MK_SHIFT_CONST(20)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_RANGE                  20:20
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_WOFFSET                        0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_UNSET                  _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_SET                    _MK_ENUM_CONST(1)
+
+// Enable Software Controlled A_VBUS_VLD.
+// Software sets this bit to drive the
+// value in SW_A_VBUS_VLD to the USB
+// controller.
+// This field is the same as the field
+// A_VBUS_VLD_SW_EN in register USB_PHY_VBUS_SENSORS.
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_EN_SHIFT                       _MK_SHIFT_CONST(19)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_EN_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_EN_RANGE                       19:19
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_EN_WOFFSET                     0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// Software_A_SESS_VLD status.
+// Software should write the appropriate
+// value (1/0) to set/unset the A_SESS_VLD status.
+// This field is the same as the field
+// A_SESS_VLD_SW_VALUE in register USB_PHY_VBUS_SENSORS.
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_SHIFT                  _MK_SHIFT_CONST(18)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_RANGE                  18:18
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_WOFFSET                        0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_UNSET                  _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_SET                    _MK_ENUM_CONST(1)
+
+// Enable Software Controlled A_SESS_VLD.
+// Software sets this bit to drive the
+// value in SW_A_SESS_VLD to the USB
+// controller.
+// This field is the same as the field
+// A_SESS_VLD_SW_EN in register USB_PHY_VBUS_SENSORS.
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_EN_SHIFT                       _MK_SHIFT_CONST(17)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_EN_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_EN_RANGE                       17:17
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_EN_WOFFSET                     0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// Suspend Set
+// Software must write a 1 to this bit to put the USB PHY in
+// suspend mode. Software should do this only after making sure that
+// the USB is indeed in suspend mode. Setting this bit will stop the
+// PHY clock. Software should write a 0 to clear it.
+// NOTE: It is required that software generate a positive pulse on this
+// bit to guarantee proper operation.
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSP_SET_SHIFT                       _MK_SHIFT_CONST(16)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSP_SET_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_SUSP_SET_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSP_SET_RANGE                       16:16
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSP_SET_WOFFSET                     0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSP_SET_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSP_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSP_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSP_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSP_SET_UNSET                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSP_SET_SET                 _MK_ENUM_CONST(1)
+
+// VBUS Change Interrupt Enable
+// If set, an interrupt will be generated whenever
+// A_SESS_VLD changes value. Software can read the
+// value of A_SESS_VLD from A_SESS_VLD_STS2 bit.
+// This field is the same as the field
+// A_SESS_VLD_INT_EN in register USB_PHY_VBUS_SENSORS.
+#define APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_INT_EN_SHIFT                        _MK_SHIFT_CONST(15)
+#define APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_INT_EN_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_INT_EN_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_INT_EN_RANGE                        15:15
+#define APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_INT_EN_WOFFSET                      0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_INT_EN_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_INT_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_INT_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_INT_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_INT_EN_DISABLE                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_INT_EN_ENABLE                       _MK_ENUM_CONST(1)
+
+// Software controlled OTG_ID.
+// If SW_OTG_ID_EN = 1, then software needs to monitor
+// actual OTG_ID bit used  as a GPIO and based on the value of OTG_ID,
+// it can set this bit.
+// This field is the same as the field
+// ID_SW_VALUE in register USB_PHY_VBUS_WAKEUP_ID.
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_SHIFT                      _MK_SHIFT_CONST(14)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_RANGE                      14:14
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_WOFFSET                    0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_UNSET                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_SET                        _MK_ENUM_CONST(1)
+
+// Reserved
+#define APB_MISC_PP_MISC_USB_OTG_0_RSVD13_SHIFT                 _MK_SHIFT_CONST(13)
+#define APB_MISC_PP_MISC_USB_OTG_0_RSVD13_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_RSVD13_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_RSVD13_RANGE                 13:13
+#define APB_MISC_PP_MISC_USB_OTG_0_RSVD13_WOFFSET                       0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_RSVD13_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_RSVD13_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_RSVD13_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_RSVD13_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// ID pullup enable.
+// This field controls the internal pull-up to
+// OTG_ID pin. Software should set this to
+// 1 if using internal OTG_ID. If software
+// is using a GPIO for OTG_ID, then it
+// can write this to 0.
+#define APB_MISC_PP_MISC_USB_OTG_0_ID_PU_SHIFT                  _MK_SHIFT_CONST(12)
+#define APB_MISC_PP_MISC_USB_OTG_0_ID_PU_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_ID_PU_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_ID_PU_RANGE                  12:12
+#define APB_MISC_PP_MISC_USB_OTG_0_ID_PU_WOFFSET                        0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_ID_PU_DEFAULT                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_ID_PU_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_ID_PU_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_ID_PU_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_ID_PU_DISABLE                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_ID_PU_ENABLE                 _MK_ENUM_CONST(1)
+
+//Suspend Clear
+// Software must write a 1 to this bit to bring the PHY
+// out of suspend mode. This is used when the software stops the PHY
+// clock during suspend and then wants to initiate a resume. Software
+// should also write 0 to clear it.
+// NOTE: It is required that software generate a  positive pulse on this
+// bit to guarantee proper operation.
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSP_CLR_SHIFT                       _MK_SHIFT_CONST(11)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSP_CLR_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_SUSP_CLR_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSP_CLR_RANGE                       11:11
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSP_CLR_WOFFSET                     0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSP_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSP_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSP_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSP_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSP_CLR_UNSET                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSP_CLR_SET                 _MK_ENUM_CONST(1)
+
+// Wake/resume on VBUS change change detect
+// If enabled, the USB PHY will wake up whenever a
+// change in A_SESS_VLD is detected.
+// This should be set only when USB PHY is already
+// suspended.
+#define APB_MISC_PP_MISC_USB_OTG_0_RSM_VBUS_CHG_SHIFT                   _MK_SHIFT_CONST(10)
+#define APB_MISC_PP_MISC_USB_OTG_0_RSM_VBUS_CHG_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_RSM_VBUS_CHG_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_RSM_VBUS_CHG_RANGE                   10:10
+#define APB_MISC_PP_MISC_USB_OTG_0_RSM_VBUS_CHG_WOFFSET                 0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_RSM_VBUS_CHG_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_RSM_VBUS_CHG_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_RSM_VBUS_CHG_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_RSM_VBUS_CHG_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_RSM_VBUS_CHG_DISABLE                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_RSM_VBUS_CHG_ENABLE                  _MK_ENUM_CONST(1)
+
+// Resume/Clock valid interrupt enable
+// If this bit is enabled, interrupt is generated
+// whenever PHY clock becomes valid.
+#define APB_MISC_PP_MISC_USB_OTG_0_RSM_IE_SHIFT                 _MK_SHIFT_CONST(9)
+#define APB_MISC_PP_MISC_USB_OTG_0_RSM_IE_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_RSM_IE_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_RSM_IE_RANGE                 9:9
+#define APB_MISC_PP_MISC_USB_OTG_0_RSM_IE_WOFFSET                       0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_RSM_IE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_RSM_IE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_RSM_IE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_RSM_IE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_RSM_IE_DISABLE                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_RSM_IE_ENABLE                        _MK_ENUM_CONST(1)
+
+// Wake on resume enable
+// If this bit is enabled, USB PHY will wakeup from
+// suspend whenever resume/reset signaling is
+// detected on USB.
+#define APB_MISC_PP_MISC_USB_OTG_0_WK_RSM_EN_SHIFT                      _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_MISC_USB_OTG_0_WK_RSM_EN_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_WK_RSM_EN_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_WK_RSM_EN_RANGE                      8:8
+#define APB_MISC_PP_MISC_USB_OTG_0_WK_RSM_EN_WOFFSET                    0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_WK_RSM_EN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_WK_RSM_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_WK_RSM_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_WK_RSM_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_WK_RSM_EN_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_WK_RSM_EN_ENABLE                     _MK_ENUM_CONST(1)
+
+// PHY clock valid status
+// This bit is set whenever PHY clock becomes valid.
+// It is cleared whenever PHY clock stops.
+#define APB_MISC_PP_MISC_USB_OTG_0_PCLKVLD_SHIFT                        _MK_SHIFT_CONST(7)
+#define APB_MISC_PP_MISC_USB_OTG_0_PCLKVLD_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_PCLKVLD_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_PCLKVLD_RANGE                        7:7
+#define APB_MISC_PP_MISC_USB_OTG_0_PCLKVLD_WOFFSET                      0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_PCLKVLD_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_PCLKVLD_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_PCLKVLD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_PCLKVLD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_PCLKVLD_UNSET                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_PCLKVLD_SET                  _MK_ENUM_CONST(1)
+
+// VBUS change detect
+// This bit is set whenever a change in A_SESS_VLD
+// is detected.
+// Software can read the status of A_SESS_VLD from 
+// A_SESS_VLD_STS2 bit.
+// This field is the same as the field
+// A_SESS_VLD_CHG_DET in register USB_PHY_VBUS_SENSORS.
+#define APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_DET_SHIFT                   _MK_SHIFT_CONST(6)
+#define APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_DET_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_DET_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_DET_RANGE                   6:6
+#define APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_DET_WOFFSET                 0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_DET_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_DET_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_DET_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_DET_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_DET_UNSET                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_DET_SET                     _MK_ENUM_CONST(1)
+
+// Loopback enable
+// Not for normal software use
+#define APB_MISC_PP_MISC_USB_OTG_0_LPBK_EN_SHIFT                        _MK_SHIFT_CONST(5)
+#define APB_MISC_PP_MISC_USB_OTG_0_LPBK_EN_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_LPBK_EN_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_LPBK_EN_RANGE                        5:5
+#define APB_MISC_PP_MISC_USB_OTG_0_LPBK_EN_WOFFSET                      0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_LPBK_EN_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_LPBK_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_LPBK_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_LPBK_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_LPBK_EN_DISABLE                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_LPBK_EN_ENABLE                       _MK_ENUM_CONST(1)
+
+// Real OTG_ID status from the USB PHY.
+// This field is the same as the field
+// ID_STS in register USB_PHY_VBUS_WAKEUP_ID.
+#define APB_MISC_PP_MISC_USB_OTG_0_OTG_ID_SHIFT                 _MK_SHIFT_CONST(4)
+#define APB_MISC_PP_MISC_USB_OTG_0_OTG_ID_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_OTG_ID_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_OTG_ID_RANGE                 4:4
+#define APB_MISC_PP_MISC_USB_OTG_0_OTG_ID_WOFFSET                       0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_OTG_ID_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_OTG_ID_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_OTG_ID_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_OTG_ID_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_OTG_ID_UNSET                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_OTG_ID_SET                   _MK_ENUM_CONST(1)
+
+// Enable Software Controlled OTG_ID
+// If using a GPIO for OTG_ID signal, then
+// software can set this to 1 and write
+// the value from the GPIO to the
+// SW_OTG_ID bit in this register.
+// This field is the same as the field
+// ID_SW_EN in register USB_PHY_VBUS_WAKEUP_ID.
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_EN_SHIFT                   _MK_SHIFT_CONST(3)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_EN_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_EN_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_EN_RANGE                   3:3
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_EN_WOFFSET                 0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_EN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_EN_DISABLE                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_EN_ENABLE                  _MK_ENUM_CONST(1)
+
+// USB PHY suspend status
+// This bit is set to 1 whenver USB is suspended and the PHY clock isnt  available.
+// NOTE: Software should not access any
+// registers in USB controller when this
+// bit is set.
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSPENDED_SHIFT                      _MK_SHIFT_CONST(2)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSPENDED_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_SUSPENDED_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSPENDED_RANGE                      2:2
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSPENDED_WOFFSET                    0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSPENDED_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSPENDED_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSPENDED_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSPENDED_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSPENDED_UNSET                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSPENDED_SET                        _MK_ENUM_CONST(1)
+
+// Static General purpose input coming from ID pin
+#define APB_MISC_PP_MISC_USB_OTG_0_StaticGpi_SHIFT                      _MK_SHIFT_CONST(1)
+#define APB_MISC_PP_MISC_USB_OTG_0_StaticGpi_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_StaticGpi_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_StaticGpi_RANGE                      1:1
+#define APB_MISC_PP_MISC_USB_OTG_0_StaticGpi_WOFFSET                    0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_StaticGpi_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_StaticGpi_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_StaticGpi_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_StaticGpi_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_StaticGpi_UNSET                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_StaticGpi_SET                        _MK_ENUM_CONST(1)
+
+// Polarity of the suspend signal going to USB PHY
+// Software should not change this.
+#define APB_MISC_PP_MISC_USB_OTG_0_SUS_POL_SHIFT                        _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUS_POL_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_SUS_POL_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUS_POL_RANGE                        0:0
+#define APB_MISC_PP_MISC_USB_OTG_0_SUS_POL_WOFFSET                      0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_SUS_POL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUS_POL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUS_POL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUS_POL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUS_POL_ACTIVE_LOW                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUS_POL_ACTIVE_HIGH                  _MK_ENUM_CONST(1)
+
+
+// Reserved address 48 [0x30] 
+
+// Reserved address 52 [0x34] 
+
+// Reserved address 56 [0x38] 
+
+// Reserved address 64 [0x40] 
+
+// Reserved address 68 [0x44] 
+
+// Reserved address 96 [0x60] 
+
+// Register APB_MISC_PP_USB_PHY_PARAM_0  
+#define APB_MISC_PP_USB_PHY_PARAM_0                     _MK_ADDR_CONST(0x64)
+#define APB_MISC_PP_USB_PHY_PARAM_0_SECURE                      0x0
+#define APB_MISC_PP_USB_PHY_PARAM_0_WORD_COUNT                  0x1
+#define APB_MISC_PP_USB_PHY_PARAM_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_RESET_MASK                  _MK_MASK_CONST(0x18)
+#define APB_MISC_PP_USB_PHY_PARAM_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_READ_MASK                   _MK_MASK_CONST(0x18)
+#define APB_MISC_PP_USB_PHY_PARAM_0_WRITE_MASK                  _MK_MASK_CONST(0x18)
+// Vbus_sense control
+// Controls which VBUS sensor input is driven to the controller.
+// 00: Use VBUS_WAKEUP.
+// 01: Use (A_SESS_VLD || B_SESS_VLD) output from the PHY if the PHY clock is available.
+// Otherwise, use VBUS_WAKEUP.
+// 10: Use (A_SESS_VLD || B_SESS_VLD) output from the PHY
+// 11: Use A_SESS_VLD output from the PHY
+#define APB_MISC_PP_USB_PHY_PARAM_0_VS_CTL_SHIFT                        _MK_SHIFT_CONST(3)
+#define APB_MISC_PP_USB_PHY_PARAM_0_VS_CTL_FIELD                        (_MK_MASK_CONST(0x3) << APB_MISC_PP_USB_PHY_PARAM_0_VS_CTL_SHIFT)
+#define APB_MISC_PP_USB_PHY_PARAM_0_VS_CTL_RANGE                        4:3
+#define APB_MISC_PP_USB_PHY_PARAM_0_VS_CTL_WOFFSET                      0x0
+#define APB_MISC_PP_USB_PHY_PARAM_0_VS_CTL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_VS_CTL_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_USB_PHY_PARAM_0_VS_CTL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_VS_CTL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_VS_CTL_VBUS_WAKEUP                  _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_VS_CTL_AB_SESS_VLD_OR_VBUS_WAKEUP                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_USB_PHY_PARAM_0_VS_CTL_AB_SESS_VLD                  _MK_ENUM_CONST(2)
+#define APB_MISC_PP_USB_PHY_PARAM_0_VS_CTL_A_SESS_VLD                   _MK_ENUM_CONST(3)
+
+
+// Reserved address 104 [0x68] 
+
+// Reserved address 108 [0x6c] 
+
+// Register APB_MISC_PP_USB_PHY_VBUS_SENSORS_0  
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0                      _MK_ADDR_CONST(0x70)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_SECURE                       0x0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_WORD_COUNT                   0x1
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_RESET_MASK                   _MK_MASK_CONST(0x3f3f3f3f)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_READ_MASK                    _MK_MASK_CONST(0x3f3f3f3f)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_WRITE_MASK                   _MK_MASK_CONST(0x39393939)
+// A_VBUS_VLD debounce A/B select.
+// Selects between the two debounce values 
+// UTMIP_BIAS_DEBOUNCE_A or
+// UTMIP_BIAS_DEBOUNCE_B from the register
+// UTMIP_DEBOUNCE_CFG0.
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_DEB_SEL_B_SHIFT                   _MK_SHIFT_CONST(29)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_DEB_SEL_B_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_DEB_SEL_B_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_DEB_SEL_B_RANGE                   29:29
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_DEB_SEL_B_WOFFSET                 0x0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_DEB_SEL_B_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_DEB_SEL_B_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_DEB_SEL_B_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_DEB_SEL_B_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_DEB_SEL_B_SEL_A                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_DEB_SEL_B_SEL_B                   _MK_ENUM_CONST(1)
+
+// A_VBUS_VLD software value.
+// Software should write the appropriate
+// value (1/0) to set/unset the A_VBUS_VLD status.
+// This is only valid when A_VBUS_VLD_SW_EN is set.
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_VALUE_SHIFT                    _MK_SHIFT_CONST(28)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_VALUE_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_VALUE_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_VALUE_RANGE                    28:28
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_VALUE_WOFFSET                  0x0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_VALUE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_VALUE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_VALUE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_VALUE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_VALUE_UNSET                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_VALUE_SET                      _MK_ENUM_CONST(1)
+
+// A_VBUS_VLD software enable.
+// Enable Software Controlled A_VBUS_VLD.
+// Software sets this bit to drive the
+// value in A_VBUS_VLD_SW_VALUE to the USB
+// controller.
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_EN_SHIFT                       _MK_SHIFT_CONST(27)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_EN_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_EN_RANGE                       27:27
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_EN_WOFFSET                     0x0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// A_VBUS_VLD status.
+// This is set to 1 whenever A_VBUS_VLD sensor
+// output is 1.
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_STS_SHIFT                 _MK_SHIFT_CONST(26)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_STS_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_STS_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_STS_RANGE                 26:26
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_STS_WOFFSET                       0x0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_STS_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_STS_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_STS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_STS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_STS_UNSET                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_STS_SET                   _MK_ENUM_CONST(1)
+
+// A_VBUS_VLD change detect.
+// This field is set by hardware whenever a change
+// is detected in the value of A_VBUS_VLD.
+// software writes a 1 to clear it
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_CHG_DET_SHIFT                     _MK_SHIFT_CONST(25)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_CHG_DET_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_CHG_DET_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_CHG_DET_RANGE                     25:25
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_CHG_DET_WOFFSET                   0x0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_CHG_DET_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_CHG_DET_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_CHG_DET_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_CHG_DET_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_CHG_DET_UNSET                     _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_CHG_DET_SET                       _MK_ENUM_CONST(1)
+
+// A_VBUS_VLD interrupt enable.
+// If this field is set to 1, an interrupt is
+// generated whenever A_VBUS_VLD_CHG_DET is set to 1.
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_INT_EN_SHIFT                      _MK_SHIFT_CONST(24)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_INT_EN_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_INT_EN_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_INT_EN_RANGE                      24:24
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_INT_EN_WOFFSET                    0x0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_INT_EN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_INT_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_INT_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_INT_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_INT_EN_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_INT_EN_ENABLE                     _MK_ENUM_CONST(1)
+
+// A_SESS_VLD debounce A/B select.
+// Selects between the two debounce values 
+// UTMIP_BIAS_DEBOUNCE_A or
+// UTMIP_BIAS_DEBOUNCE_B from the register
+// UTMIP_DEBOUNCE_CFG0.
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_DEB_SEL_B_SHIFT                   _MK_SHIFT_CONST(21)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_DEB_SEL_B_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_DEB_SEL_B_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_DEB_SEL_B_RANGE                   21:21
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_DEB_SEL_B_WOFFSET                 0x0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_DEB_SEL_B_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_DEB_SEL_B_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_DEB_SEL_B_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_DEB_SEL_B_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_DEB_SEL_B_SEL_A                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_DEB_SEL_B_SEL_B                   _MK_ENUM_CONST(1)
+
+// A_SESS_VLD software value.
+// Software should write the appropriate
+// value (1/0) to set/unset the A_SESS_VLD status.
+// This is only valid when A_SESS_VLD_SW_EN is set.
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_VALUE_SHIFT                    _MK_SHIFT_CONST(20)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_VALUE_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_VALUE_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_VALUE_RANGE                    20:20
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_VALUE_WOFFSET                  0x0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_VALUE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_VALUE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_VALUE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_VALUE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_VALUE_UNSET                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_VALUE_SET                      _MK_ENUM_CONST(1)
+
+// A_SESS_VLD software enable.
+// Enable Software Controlled A_SESS_VLD.
+// Software sets this bit to drive the
+// value in A_SESS_VLD_SW_VALUE to the USB
+// controller.
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_EN_SHIFT                       _MK_SHIFT_CONST(19)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_EN_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_EN_RANGE                       19:19
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_EN_WOFFSET                     0x0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// A_SESS_VLD status.
+// This is set to 1 whenever A_SESS_VLD sensor
+// output is 1.
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_STS_SHIFT                 _MK_SHIFT_CONST(18)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_STS_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_STS_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_STS_RANGE                 18:18
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_STS_WOFFSET                       0x0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_STS_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_STS_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_STS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_STS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_STS_UNSET                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_STS_SET                   _MK_ENUM_CONST(1)
+
+// A_SESS_VLD change detect.
+// This field is set by hardware whenever a change
+// is detected in the value of A_SESS_VLD.
+// software writes a 1 to clear it
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_CHG_DET_SHIFT                     _MK_SHIFT_CONST(17)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_CHG_DET_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_CHG_DET_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_CHG_DET_RANGE                     17:17
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_CHG_DET_WOFFSET                   0x0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_CHG_DET_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_CHG_DET_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_CHG_DET_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_CHG_DET_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_CHG_DET_UNSET                     _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_CHG_DET_SET                       _MK_ENUM_CONST(1)
+
+// A_SESS_VLD interrupt enable.
+// If this field is set to 1, an interrupt is
+// generated whenever A_SESS_VLD_CHG_DET is set to 1.
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_INT_EN_SHIFT                      _MK_SHIFT_CONST(16)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_INT_EN_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_INT_EN_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_INT_EN_RANGE                      16:16
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_INT_EN_WOFFSET                    0x0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_INT_EN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_INT_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_INT_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_INT_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_INT_EN_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_INT_EN_ENABLE                     _MK_ENUM_CONST(1)
+
+// B_SESS_VLD debounce A/B select.
+// Selects between the two debounce values 
+// UTMIP_BIAS_DEBOUNCE_A or
+// UTMIP_BIAS_DEBOUNCE_B from the register
+// UTMIP_DEBOUNCE_CFG0.
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_DEB_SEL_B_SHIFT                   _MK_SHIFT_CONST(13)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_DEB_SEL_B_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_DEB_SEL_B_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_DEB_SEL_B_RANGE                   13:13
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_DEB_SEL_B_WOFFSET                 0x0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_DEB_SEL_B_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_DEB_SEL_B_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_DEB_SEL_B_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_DEB_SEL_B_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_DEB_SEL_B_SEL_A                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_DEB_SEL_B_SEL_B                   _MK_ENUM_CONST(1)
+
+// B_SESS_VLD software value.
+// Software should write the appropriate
+// value (1/0) to set/unset the B_SESS_VLD status.
+// This is only valid when B_SESS_VLD_SW_EN is set.
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_VALUE_SHIFT                    _MK_SHIFT_CONST(12)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_VALUE_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_VALUE_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_VALUE_RANGE                    12:12
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_VALUE_WOFFSET                  0x0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_VALUE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_VALUE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_VALUE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_VALUE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_VALUE_UNSET                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_VALUE_SET                      _MK_ENUM_CONST(1)
+
+// B_SESS_VLD software enable.
+// Enable Software Controlled B_SESS_VLD.
+// Software sets this bit to drive the
+// value in B_SESS_VLD_SW_VALUE to the USB
+// controller.
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_EN_SHIFT                       _MK_SHIFT_CONST(11)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_EN_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_EN_RANGE                       11:11
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_EN_WOFFSET                     0x0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// B_SESS_VLD status.
+// This is set to 1 whenever B_SESS_VLD sensor
+// output is 1.
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_STS_SHIFT                 _MK_SHIFT_CONST(10)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_STS_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_STS_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_STS_RANGE                 10:10
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_STS_WOFFSET                       0x0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_STS_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_STS_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_STS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_STS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_STS_UNSET                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_STS_SET                   _MK_ENUM_CONST(1)
+
+// B_SESS_VLD change detect.
+// This field is set by hardware whenever a change
+// is detected in the value of B_SESS_VLD.
+// software writes a 1 to clear it
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_CHG_DET_SHIFT                     _MK_SHIFT_CONST(9)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_CHG_DET_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_CHG_DET_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_CHG_DET_RANGE                     9:9
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_CHG_DET_WOFFSET                   0x0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_CHG_DET_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_CHG_DET_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_CHG_DET_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_CHG_DET_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_CHG_DET_UNSET                     _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_CHG_DET_SET                       _MK_ENUM_CONST(1)
+
+// B_SESS_VLD interrupt enable.
+// If this field is set to 1, an interrupt is
+// generated whenever B_SESS_VLD_CHG_DET is set to 1.
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_INT_EN_SHIFT                      _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_INT_EN_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_INT_EN_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_INT_EN_RANGE                      8:8
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_INT_EN_WOFFSET                    0x0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_INT_EN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_INT_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_INT_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_INT_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_INT_EN_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_INT_EN_ENABLE                     _MK_ENUM_CONST(1)
+
+// B_SESS_END debounce A/B select
+// Selects between the two debounce values 
+// UTMIP_BIAS_DEBOUNCE_A or
+// UTMIP_BIAS_DEBOUNCE_B from the register
+// UTMIP_DEBOUNCE_CFG0.
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_DEB_SEL_B_SHIFT                   _MK_SHIFT_CONST(5)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_DEB_SEL_B_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_DEB_SEL_B_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_DEB_SEL_B_RANGE                   5:5
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_DEB_SEL_B_WOFFSET                 0x0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_DEB_SEL_B_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_DEB_SEL_B_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_DEB_SEL_B_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_DEB_SEL_B_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_DEB_SEL_B_SEL_A                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_DEB_SEL_B_SEL_B                   _MK_ENUM_CONST(1)
+
+// B_SESS_END software value
+// Software should write the appropriate
+// value (1/0) to set/unset the B_SESS_END status.
+// This is only valid when B_SESS_END_SW_EN is set.
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_VALUE_SHIFT                    _MK_SHIFT_CONST(4)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_VALUE_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_VALUE_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_VALUE_RANGE                    4:4
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_VALUE_WOFFSET                  0x0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_VALUE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_VALUE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_VALUE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_VALUE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_VALUE_UNSET                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_VALUE_SET                      _MK_ENUM_CONST(1)
+
+// B_SESS_END software enable.
+// Enable Software Controlled B_SESS_END
+// Software sets this bit to drive the
+// value in B_SESS_END_SW_VALUE to the USB
+// controller.
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_EN_SHIFT                       _MK_SHIFT_CONST(3)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_EN_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_EN_RANGE                       3:3
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_EN_WOFFSET                     0x0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// B_SESS_END status.
+// This is set to 1 whenever B_SESS_END sensor
+// output is 1.
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_STS_SHIFT                 _MK_SHIFT_CONST(2)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_STS_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_STS_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_STS_RANGE                 2:2
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_STS_WOFFSET                       0x0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_STS_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_STS_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_STS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_STS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_STS_UNSET                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_STS_SET                   _MK_ENUM_CONST(1)
+
+// B_SESS_END change detect.
+// This field is set by hardware whenever a change
+// is detected in the value of B_SESS_END.
+// software writes a 1 to clear it
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_CHG_DET_SHIFT                     _MK_SHIFT_CONST(1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_CHG_DET_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_CHG_DET_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_CHG_DET_RANGE                     1:1
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_CHG_DET_WOFFSET                   0x0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_CHG_DET_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_CHG_DET_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_CHG_DET_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_CHG_DET_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_CHG_DET_UNSET                     _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_CHG_DET_SET                       _MK_ENUM_CONST(1)
+
+// B_SESS_END interrupt enable
+// If this field is set to 1, an interrupt is
+// generated whenever B_SESS_END_CHG_DET is set to 1.
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_INT_EN_SHIFT                      _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_INT_EN_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_INT_EN_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_INT_EN_RANGE                      0:0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_INT_EN_WOFFSET                    0x0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_INT_EN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_INT_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_INT_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_INT_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_INT_EN_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_INT_EN_ENABLE                     _MK_ENUM_CONST(1)
+
+
+// Register APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0  
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0                    _MK_ADDR_CONST(0x74)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_SECURE                     0x0
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_WORD_COUNT                         0x1
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_RESET_VAL                  _MK_MASK_CONST(0x6000000)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_RESET_MASK                         _MK_MASK_CONST(0x3f3f3f3f)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_READ_MASK                  _MK_MASK_CONST(0x3f3f3f3f)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_WRITE_MASK                         _MK_MASK_CONST(0x3f393939)
+// HS Tx to Tx inter-packet delay counter.
+// Software should not change this.
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_IP_DELAY_TX2TX_HS_SHIFT                    _MK_SHIFT_CONST(24)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_IP_DELAY_TX2TX_HS_FIELD                    (_MK_MASK_CONST(0x3f) << APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_IP_DELAY_TX2TX_HS_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_IP_DELAY_TX2TX_HS_RANGE                    29:24
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_IP_DELAY_TX2TX_HS_WOFFSET                  0x0
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_IP_DELAY_TX2TX_HS_DEFAULT                  _MK_MASK_CONST(0x6)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_IP_DELAY_TX2TX_HS_DEFAULT_MASK                     _MK_MASK_CONST(0x3f)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_IP_DELAY_TX2TX_HS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_IP_DELAY_TX2TX_HS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// VDAT_DET debounce A/B select.
+// Selects between the two debounce values 
+// UTMIP_BIAS_DEBOUNCE_A or
+// UTMIP_BIAS_DEBOUNCE_B from the register
+// UTMIP_DEBOUNCE_CFG0.
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_DEB_SEL_B_SHIFT                   _MK_SHIFT_CONST(21)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_DEB_SEL_B_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_DEB_SEL_B_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_DEB_SEL_B_RANGE                   21:21
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_DEB_SEL_B_WOFFSET                 0x0
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_DEB_SEL_B_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_DEB_SEL_B_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_DEB_SEL_B_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_DEB_SEL_B_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_DEB_SEL_B_SEL_A                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_DEB_SEL_B_SEL_B                   _MK_ENUM_CONST(1)
+
+// VDAT_DET software value.
+// Software should write the appropriate
+// value (1/0) to set/unset the VDAT_DET status.
+// This is only valid when VDAT_DET_SW_EN is set.
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_VALUE_SHIFT                    _MK_SHIFT_CONST(20)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_VALUE_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_VALUE_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_VALUE_RANGE                    20:20
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_VALUE_WOFFSET                  0x0
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_VALUE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_VALUE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_VALUE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_VALUE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_VALUE_UNSET                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_VALUE_SET                      _MK_ENUM_CONST(1)
+
+// VDAT_DET software enable.
+// Enable Software Controlled VDAT_DET.
+// Software sets this bit to drive the
+// value in VDAT_DET_SW_VALUE to the USB
+// controller
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_EN_SHIFT                       _MK_SHIFT_CONST(19)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_EN_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_EN_RANGE                       19:19
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_EN_WOFFSET                     0x0
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// VDAT_DET status.
+// This is set to 1 whenever VDAT_DET sensor
+// output is 1.
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_STS_SHIFT                 _MK_SHIFT_CONST(18)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_STS_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_STS_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_STS_RANGE                 18:18
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_STS_WOFFSET                       0x0
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_STS_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_STS_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_STS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_STS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_STS_UNSET                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_STS_SET                   _MK_ENUM_CONST(1)
+
+// VDAT_DET change detect.
+// This field is set by hardware whenever a change
+// is detected in the value of VDAT_DET.
+// software writes a 1 to clear it
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_CHG_DET_SHIFT                     _MK_SHIFT_CONST(17)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_CHG_DET_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_CHG_DET_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_CHG_DET_RANGE                     17:17
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_CHG_DET_WOFFSET                   0x0
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_CHG_DET_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_CHG_DET_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_CHG_DET_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_CHG_DET_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_CHG_DET_UNSET                     _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_CHG_DET_SET                       _MK_ENUM_CONST(1)
+
+// VDAT_DET interrupt enable.
+// If this field is set to 1, an interrupt is
+// generated whenever VDAT_DET_CHG_DET is set to 1.
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_INT_EN_SHIFT                      _MK_SHIFT_CONST(16)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_INT_EN_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_INT_EN_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_INT_EN_RANGE                      16:16
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_INT_EN_WOFFSET                    0x0
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_INT_EN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_INT_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_INT_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_INT_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_INT_EN_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_INT_EN_ENABLE                     _MK_ENUM_CONST(1)
+
+// VBUS_WAKEUP debounce A/B select.
+// Selects between the two debounce values 
+// UTMIP_BIAS_DEBOUNCE_A or
+// UTMIP_BIAS_DEBOUNCE_B from the register
+// UTMIP_DEBOUNCE_CFG0.
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_DEB_SEL_B_SHIFT                        _MK_SHIFT_CONST(13)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_DEB_SEL_B_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_DEB_SEL_B_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_DEB_SEL_B_RANGE                        13:13
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_DEB_SEL_B_WOFFSET                      0x0
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_DEB_SEL_B_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_DEB_SEL_B_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_DEB_SEL_B_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_DEB_SEL_B_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_DEB_SEL_B_SEL_A                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_DEB_SEL_B_SEL_B                        _MK_ENUM_CONST(1)
+
+// VBUS_WAKEUP software value.
+// Software should write the appropriate
+// value (1/0) to set/unset the VBUS_WAKEUP status.
+// This is only valid when VBUS_WAKEUP_SW_EN is set.
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_VALUE_SHIFT                 _MK_SHIFT_CONST(12)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_VALUE_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_VALUE_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_VALUE_RANGE                 12:12
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_VALUE_WOFFSET                       0x0
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_VALUE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_VALUE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_VALUE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_VALUE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_VALUE_UNSET                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_VALUE_SET                   _MK_ENUM_CONST(1)
+
+// VBUS_WAKEUP software enable.
+// Enable Software Controlled VBUS_WAKEUP.
+// Software sets this bit to drive the
+// value in VBUS_WAKEUP_SW_VALUE to the USB
+// controller.
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_EN_SHIFT                    _MK_SHIFT_CONST(11)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_EN_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_EN_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_EN_RANGE                    11:11
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_EN_WOFFSET                  0x0
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_EN_DISABLE                  _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_EN_ENABLE                   _MK_ENUM_CONST(1)
+
+// VBUS_WAKEUP status.
+// This is set to 1 whenever VBUS_WAKEUP sensor
+// output is 1.
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_STS_SHIFT                      _MK_SHIFT_CONST(10)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_STS_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_STS_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_STS_RANGE                      10:10
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_STS_WOFFSET                    0x0
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_STS_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_STS_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_STS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_STS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_STS_UNSET                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_STS_SET                        _MK_ENUM_CONST(1)
+
+// VBUS_WAKEUP change detect.
+// This field is set by hardware whenever a change
+// is detected in the value of VBUS_WAKEUP.
+// software writes a 1 to clear it
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_CHG_DET_SHIFT                  _MK_SHIFT_CONST(9)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_CHG_DET_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_CHG_DET_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_CHG_DET_RANGE                  9:9
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_CHG_DET_WOFFSET                        0x0
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_CHG_DET_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_CHG_DET_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_CHG_DET_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_CHG_DET_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_CHG_DET_UNSET                  _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_CHG_DET_SET                    _MK_ENUM_CONST(1)
+
+// VBUS_WAKEUP interrupt enable
+// If this field is set to 1, an interrupt is
+// generated whenever VBUS_WAKEUP_CHG_DET is set to 1.
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_INT_EN_SHIFT                   _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_INT_EN_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_INT_EN_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_INT_EN_RANGE                   8:8
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_INT_EN_WOFFSET                 0x0
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_INT_EN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_INT_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_INT_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_INT_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_INT_EN_DISABLE                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_INT_EN_ENABLE                  _MK_ENUM_CONST(1)
+
+// ID debounce A/B select.
+// Selects between the two debounce values 
+// UTMIP_BIAS_DEBOUNCE_A or
+// UTMIP_BIAS_DEBOUNCE_B from the register
+// UTMIP_DEBOUNCE_CFG0.
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_DEB_SEL_B_SHIFT                 _MK_SHIFT_CONST(5)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_DEB_SEL_B_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_DEB_SEL_B_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_DEB_SEL_B_RANGE                 5:5
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_DEB_SEL_B_WOFFSET                       0x0
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_DEB_SEL_B_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_DEB_SEL_B_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_DEB_SEL_B_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_DEB_SEL_B_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_DEB_SEL_B_SEL_A                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_DEB_SEL_B_SEL_B                 _MK_ENUM_CONST(1)
+
+// ID software value.
+// Software should write the appropriate
+// value (1/0) to set/unset the ID status.
+// This is only valid when ID_SW_EN is set.
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_VALUE_SHIFT                  _MK_SHIFT_CONST(4)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_VALUE_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_VALUE_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_VALUE_RANGE                  4:4
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_VALUE_WOFFSET                        0x0
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_VALUE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_VALUE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_VALUE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_VALUE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_VALUE_UNSET                  _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_VALUE_SET                    _MK_ENUM_CONST(1)
+
+// ID software enable.
+// Enable Software Controlled ID.
+// Software sets this bit to drive the
+// value in ID_SW_VALUE to the USB
+// controller
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_EN_SHIFT                     _MK_SHIFT_CONST(3)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_EN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_EN_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_EN_RANGE                     3:3
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_EN_WOFFSET                   0x0
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// ID status.
+// This is set to 1 whenever ID sensor
+// output is 1.
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_STS_SHIFT                       _MK_SHIFT_CONST(2)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_STS_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_STS_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_STS_RANGE                       2:2
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_STS_WOFFSET                     0x0
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_STS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_STS_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_STS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_STS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_STS_UNSET                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_STS_SET                 _MK_ENUM_CONST(1)
+
+// ID change detect.
+// This field is set by hardware whenever a change
+// is detected in the value of ID.
+// software writes a 1 to clear it
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_CHG_DET_SHIFT                   _MK_SHIFT_CONST(1)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_CHG_DET_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_CHG_DET_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_CHG_DET_RANGE                   1:1
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_CHG_DET_WOFFSET                 0x0
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_CHG_DET_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_CHG_DET_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_CHG_DET_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_CHG_DET_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_CHG_DET_UNSET                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_CHG_DET_SET                     _MK_ENUM_CONST(1)
+
+// ID interrupt enable.
+// If this field is set to 1, an interrupt is
+// generated whenever ID_CHG_DET is set to 1.
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_INT_EN_SHIFT                    _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_INT_EN_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_INT_EN_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_INT_EN_RANGE                    0:0
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_INT_EN_WOFFSET                  0x0
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_INT_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_INT_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_INT_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_INT_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_INT_EN_DISABLE                  _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_INT_EN_ENABLE                   _MK_ENUM_CONST(1)
+
+
+// Register APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0  
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0                      _MK_ADDR_CONST(0x78)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_SECURE                       0x0
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_WORD_COUNT                   0x1
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_RESET_MASK                   _MK_MASK_CONST(0x7f)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_READ_MASK                    _MK_MASK_CONST(0x7f)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
+// A_SESS_VLD alternate status
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_A_SESS_VLD_ALT_SHIFT                 _MK_SHIFT_CONST(6)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_A_SESS_VLD_ALT_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_A_SESS_VLD_ALT_SHIFT)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_A_SESS_VLD_ALT_RANGE                 6:6
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_A_SESS_VLD_ALT_WOFFSET                       0x0
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_A_SESS_VLD_ALT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_A_SESS_VLD_ALT_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_A_SESS_VLD_ALT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_A_SESS_VLD_ALT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_A_SESS_VLD_ALT_UNSET                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_A_SESS_VLD_ALT_SET                   _MK_ENUM_CONST(1)
+
+// B_SESS_VLD alternate status
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_B_SESS_VLD_ALT_SHIFT                 _MK_SHIFT_CONST(5)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_B_SESS_VLD_ALT_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_B_SESS_VLD_ALT_SHIFT)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_B_SESS_VLD_ALT_RANGE                 5:5
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_B_SESS_VLD_ALT_WOFFSET                       0x0
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_B_SESS_VLD_ALT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_B_SESS_VLD_ALT_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_B_SESS_VLD_ALT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_B_SESS_VLD_ALT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_B_SESS_VLD_ALT_UNSET                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_B_SESS_VLD_ALT_SET                   _MK_ENUM_CONST(1)
+
+// ID alternate status
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_ID_DIG_ALT_SHIFT                     _MK_SHIFT_CONST(4)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_ID_DIG_ALT_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_ID_DIG_ALT_SHIFT)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_ID_DIG_ALT_RANGE                     4:4
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_ID_DIG_ALT_WOFFSET                   0x0
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_ID_DIG_ALT_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_ID_DIG_ALT_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_ID_DIG_ALT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_ID_DIG_ALT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_ID_DIG_ALT_UNSET                     _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_ID_DIG_ALT_SET                       _MK_ENUM_CONST(1)
+
+// B_SESS_END alternate status
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_B_SESS_END_ALT_SHIFT                 _MK_SHIFT_CONST(3)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_B_SESS_END_ALT_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_B_SESS_END_ALT_SHIFT)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_B_SESS_END_ALT_RANGE                 3:3
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_B_SESS_END_ALT_WOFFSET                       0x0
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_B_SESS_END_ALT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_B_SESS_END_ALT_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_B_SESS_END_ALT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_B_SESS_END_ALT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_B_SESS_END_ALT_UNSET                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_B_SESS_END_ALT_SET                   _MK_ENUM_CONST(1)
+
+// Static GPI alternate status
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_STATIC_GPI_ALT_SHIFT                 _MK_SHIFT_CONST(2)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_STATIC_GPI_ALT_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_STATIC_GPI_ALT_SHIFT)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_STATIC_GPI_ALT_RANGE                 2:2
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_STATIC_GPI_ALT_WOFFSET                       0x0
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_STATIC_GPI_ALT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_STATIC_GPI_ALT_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_STATIC_GPI_ALT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_STATIC_GPI_ALT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_STATIC_GPI_ALT_UNSET                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_STATIC_GPI_ALT_SET                   _MK_ENUM_CONST(1)
+
+// A_VBUS_VLD alternate status
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_A_VBUS_VLD_ALT_SHIFT                 _MK_SHIFT_CONST(1)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_A_VBUS_VLD_ALT_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_A_VBUS_VLD_ALT_SHIFT)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_A_VBUS_VLD_ALT_RANGE                 1:1
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_A_VBUS_VLD_ALT_WOFFSET                       0x0
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_A_VBUS_VLD_ALT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_A_VBUS_VLD_ALT_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_A_VBUS_VLD_ALT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_A_VBUS_VLD_ALT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_A_VBUS_VLD_ALT_UNSET                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_A_VBUS_VLD_ALT_SET                   _MK_ENUM_CONST(1)
+
+// Vbus wakeup alternate status
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_VBUS_WAKEUP_ALT_SHIFT                        _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_VBUS_WAKEUP_ALT_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_VBUS_WAKEUP_ALT_SHIFT)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_VBUS_WAKEUP_ALT_RANGE                        0:0
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_VBUS_WAKEUP_ALT_WOFFSET                      0x0
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_VBUS_WAKEUP_ALT_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_VBUS_WAKEUP_ALT_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_VBUS_WAKEUP_ALT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_VBUS_WAKEUP_ALT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_VBUS_WAKEUP_ALT_UNSET                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_VBUS_WAKEUP_ALT_SET                  _MK_ENUM_CONST(1)
+
+
+// Register APB_MISC_PP_MISC_SAVE_THE_DAY_0  
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0                 _MK_ADDR_CONST(0x7c)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SECURE                  0x0
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_WORD_COUNT                      0x1
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Reserved
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_A_SHIFT                    _MK_SHIFT_CONST(24)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_A_FIELD                    (_MK_MASK_CONST(0xff) << APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_A_SHIFT)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_A_RANGE                    31:24
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_A_WOFFSET                  0x0
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_A_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_A_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_A_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_A_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Reserved
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_B_SHIFT                    _MK_SHIFT_CONST(16)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_B_FIELD                    (_MK_MASK_CONST(0xff) << APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_B_SHIFT)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_B_RANGE                    23:16
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_B_WOFFSET                  0x0
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_B_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_B_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_B_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_B_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Reserved
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_C_SHIFT                    _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_C_FIELD                    (_MK_MASK_CONST(0xff) << APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_C_SHIFT)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_C_RANGE                    15:8
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_C_WOFFSET                  0x0
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_C_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_C_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_C_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_C_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Reserved
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_D_SHIFT                    _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_D_FIELD                    (_MK_MASK_CONST(0xff) << APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_D_SHIFT)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_D_RANGE                    7:0
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_D_WOFFSET                  0x0
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_D_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_D_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_D_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_D_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_PP_PIN_MUX_CTL_A_0  
+#define APB_MISC_PP_PIN_MUX_CTL_A_0                     _MK_ADDR_CONST(0x80)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_SECURE                      0x0
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_WORD_COUNT                  0x1
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RESET_VAL                   _MK_MASK_CONST(0x2a22000)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RESET_MASK                  _MK_MASK_CONST(0xfff3f3ff)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_READ_MASK                   _MK_MASK_CONST(0xfff3f3ff)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_WRITE_MASK                  _MK_MASK_CONST(0xfff3f3ff)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_SDIO1_SEL_SHIFT                     _MK_SHIFT_CONST(30)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_SDIO1_SEL_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_A_0_SDIO1_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_SDIO1_SEL_RANGE                     31:30
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_SDIO1_SEL_WOFFSET                   0x0
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_SDIO1_SEL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_SDIO1_SEL_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_SDIO1_SEL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_SDIO1_SEL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_SDIO1_SEL_SDIO1                     _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_SDIO1_SEL_RSVD1                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_SDIO1_SEL_UARTE                     _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_SDIO1_SEL_UARTA                     _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCE_SEL_SHIFT                      _MK_SHIFT_CONST(28)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCE_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_A_0_KBCE_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCE_SEL_RANGE                      29:28
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCE_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCE_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCE_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCE_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCE_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCE_SEL_KBC                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCE_SEL_NAND                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCE_SEL_OWR                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCE_SEL_RSVD2                      _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCF_SEL_SHIFT                      _MK_SHIFT_CONST(26)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCF_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_A_0_KBCF_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCF_SEL_RANGE                      27:26
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCF_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCF_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCF_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCF_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCF_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCF_SEL_KBC                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCF_SEL_NAND                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCF_SEL_TRACE                      _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCF_SEL_MIO                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATA_SEL_SHIFT                       _MK_SHIFT_CONST(24)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATA_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_A_0_ATA_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATA_SEL_RANGE                       25:24
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATA_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATA_SEL_DEFAULT                     _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATA_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATA_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATA_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATA_SEL_IDE                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATA_SEL_NAND                        _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATA_SEL_GMI                 _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATA_SEL_RSVD                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATC_SEL_SHIFT                       _MK_SHIFT_CONST(22)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATC_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_A_0_ATC_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATC_SEL_RANGE                       23:22
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATC_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATC_SEL_DEFAULT                     _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATC_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATC_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATC_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATC_SEL_IDE                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATC_SEL_NAND                        _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATC_SEL_GMI                 _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATC_SEL_SDIO4                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATD_SEL_SHIFT                       _MK_SHIFT_CONST(20)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATD_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_A_0_ATD_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATD_SEL_RANGE                       21:20
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATD_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATD_SEL_DEFAULT                     _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATD_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATD_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATD_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATD_SEL_IDE                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATD_SEL_NAND                        _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATD_SEL_GMI                 _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATD_SEL_SDIO4                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATB_SEL_SHIFT                       _MK_SHIFT_CONST(16)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATB_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_A_0_ATB_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATB_SEL_RANGE                       17:16
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATB_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATB_SEL_DEFAULT                     _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATB_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATB_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATB_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATB_SEL_IDE                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATB_SEL_NAND                        _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATB_SEL_GMI                 _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATB_SEL_SDIO4                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RM_SEL_SHIFT                        _MK_SHIFT_CONST(14)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RM_SEL_FIELD                        (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_A_0_RM_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RM_SEL_RANGE                        15:14
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RM_SEL_WOFFSET                      0x0
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RM_SEL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RM_SEL_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RM_SEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RM_SEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RM_SEL_I2C                  _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RM_SEL_RSVD1                        _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RM_SEL_RSVD2                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RM_SEL_RSVD3                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATE_SEL_SHIFT                       _MK_SHIFT_CONST(12)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATE_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_A_0_ATE_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATE_SEL_RANGE                       13:12
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATE_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATE_SEL_DEFAULT                     _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATE_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATE_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATE_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATE_SEL_IDE                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATE_SEL_NAND                        _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATE_SEL_GMI                 _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATE_SEL_RSVD                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UDA_SEL_SHIFT                       _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UDA_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_A_0_UDA_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UDA_SEL_RANGE                       9:8
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UDA_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UDA_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UDA_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UDA_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UDA_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UDA_SEL_SPI1                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UDA_SEL_RSVD                        _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UDA_SEL_UARTD                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UDA_SEL_ULPI                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAD_SEL_SHIFT                       _MK_SHIFT_CONST(6)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAD_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_A_0_UAD_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAD_SEL_RANGE                       7:6
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAD_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAD_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAD_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAD_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAD_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAD_SEL_IRDA                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAD_SEL_SPDIF                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAD_SEL_UARTA                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAD_SEL_SPI4                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAC_SEL_SHIFT                       _MK_SHIFT_CONST(4)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAC_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_A_0_UAC_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAC_SEL_RANGE                       5:4
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAC_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAC_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAC_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAC_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAC_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAC_SEL_OWR                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAC_SEL_RSVD2                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAC_SEL_RSVD3                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAC_SEL_RSVD4                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAB_SEL_SHIFT                       _MK_SHIFT_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAB_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_A_0_UAB_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAB_SEL_RANGE                       3:2
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAB_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAB_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAB_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAB_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAB_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAB_SEL_SPI2                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAB_SEL_MIPI_HS                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAB_SEL_UARTA                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAB_SEL_ULPI                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAA_SEL_SHIFT                       _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAA_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_A_0_UAA_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAA_SEL_RANGE                       1:0
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAA_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAA_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAA_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAA_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAA_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAA_SEL_SPI3                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAA_SEL_MIPI_HS                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAA_SEL_UARTA                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAA_SEL_ULPI                        _MK_ENUM_CONST(3)
+
+
+// Register APB_MISC_PP_PIN_MUX_CTL_B_0  
+#define APB_MISC_PP_PIN_MUX_CTL_B_0                     _MK_ADDR_CONST(0x84)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SECURE                      0x0
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_WORD_COUNT                  0x1
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_RESET_VAL                   _MK_MASK_CONST(0xa140a)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_RESET_MASK                  _MK_MASK_CONST(0xfcffffff)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_READ_MASK                   _MK_MASK_CONST(0xfcffffff)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_WRITE_MASK                  _MK_MASK_CONST(0xfcffffff)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTE_SEL_SHIFT                       _MK_SHIFT_CONST(30)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTE_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_B_0_DTE_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTE_SEL_RANGE                       31:30
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTE_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTE_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTE_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTE_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTE_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTE_SEL_RSVD1                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTE_SEL_RSVD2                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTE_SEL_VI                  _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTE_SEL_SPI1                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTD_SEL_SHIFT                       _MK_SHIFT_CONST(28)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTD_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_B_0_DTD_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTD_SEL_RANGE                       29:28
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTD_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTD_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTD_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTD_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTD_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTD_SEL_RSVD1                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTD_SEL_SDIO2                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTD_SEL_VI                  _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTD_SEL_RSVD4                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTC_SEL_SHIFT                       _MK_SHIFT_CONST(26)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTC_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_B_0_DTC_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTC_SEL_RANGE                       27:26
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTC_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTC_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTC_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTC_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTC_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTC_SEL_RSVD1                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTC_SEL_RSVD2                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTC_SEL_VI                  _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTC_SEL_RSVD4                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTB_SEL_SHIFT                       _MK_SHIFT_CONST(22)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTB_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_B_0_DTB_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTB_SEL_RANGE                       23:22
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTB_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTB_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTB_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTB_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTB_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTB_SEL_RSVD1                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTB_SEL_RSVD2                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTB_SEL_VI                  _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTB_SEL_SPI1                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTA_SEL_SHIFT                       _MK_SHIFT_CONST(20)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTA_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_B_0_DTA_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTA_SEL_RANGE                       21:20
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTA_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTA_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTA_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTA_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTA_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTA_SEL_RSVD1                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTA_SEL_SDIO2                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTA_SEL_VI                  _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTA_SEL_RSVD4                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCB_SEL_SHIFT                       _MK_SHIFT_CONST(18)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCB_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_B_0_UCB_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCB_SEL_RANGE                       19:18
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCB_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCB_SEL_DEFAULT                     _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCB_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCB_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCB_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCB_SEL_UARTC                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCB_SEL_PWM                 _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCB_SEL_GMI                 _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCB_SEL_RSVD4                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCA_SEL_SHIFT                       _MK_SHIFT_CONST(16)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCA_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_B_0_UCA_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCA_SEL_RANGE                       17:16
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCA_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCA_SEL_DEFAULT                     _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCA_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCA_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCA_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCA_SEL_UARTC                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCA_SEL_RSVD2                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCA_SEL_GMI                 _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCA_SEL_RSVD4                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXK_SEL_SHIFT                      _MK_SHIFT_CONST(14)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXK_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_B_0_SLXK_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXK_SEL_RANGE                      15:14
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXK_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXK_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXK_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXK_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXK_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXK_SEL_PCIE                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXK_SEL_SPI4                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXK_SEL_SDIO3                      _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXK_SEL_SPI2                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXD_SEL_SHIFT                      _MK_SHIFT_CONST(12)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXD_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_B_0_SLXD_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXD_SEL_RANGE                      13:12
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXD_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXD_SEL_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXD_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXD_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXD_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXD_SEL_SPDIF                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXD_SEL_SPI4                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXD_SEL_SDIO3                      _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXD_SEL_SPI2                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXC_SEL_SHIFT                      _MK_SHIFT_CONST(10)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXC_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_B_0_SLXC_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXC_SEL_RANGE                      11:10
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXC_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXC_SEL_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXC_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXC_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXC_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXC_SEL_SPDIF                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXC_SEL_SPI4                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXC_SEL_SDIO3                      _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXC_SEL_SPI2                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_OWC_SEL_SHIFT                       _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_OWC_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_B_0_OWC_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_OWC_SEL_RANGE                       9:8
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_OWC_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_OWC_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_OWC_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_OWC_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_OWC_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_OWC_SEL_OWR                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_OWC_SEL_RSVD1                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_OWC_SEL_RSVD2                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_OWC_SEL_RSVD3                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXA_SEL_SHIFT                      _MK_SHIFT_CONST(6)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXA_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_B_0_SLXA_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXA_SEL_RANGE                      7:6
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXA_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXA_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXA_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXA_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXA_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXA_SEL_PCIE                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXA_SEL_SPI4                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXA_SEL_SDIO3                      _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXA_SEL_SPI2                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_HDINT_SEL_SHIFT                     _MK_SHIFT_CONST(4)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_HDINT_SEL_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_B_0_HDINT_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_HDINT_SEL_RANGE                     5:4
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_HDINT_SEL_WOFFSET                   0x0
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_HDINT_SEL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_HDINT_SEL_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_HDINT_SEL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_HDINT_SEL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_HDINT_SEL_HDMI                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_HDINT_SEL_RSVD2                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_HDINT_SEL_RSVD3                     _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_HDINT_SEL_RSVD4                     _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_GMC_SEL_SHIFT                       _MK_SHIFT_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_GMC_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_B_0_GMC_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_GMC_SEL_RANGE                       3:2
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_GMC_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_GMC_SEL_DEFAULT                     _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_GMC_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_GMC_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_GMC_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_GMC_SEL_UARTD                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_GMC_SEL_SPI4                        _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_GMC_SEL_GMI                 _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_GMC_SEL_SFLASH                      _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_GMA_SEL_SHIFT                       _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_GMA_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_B_0_GMA_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_GMA_SEL_RANGE                       1:0
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_GMA_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_GMA_SEL_DEFAULT                     _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_GMA_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_GMA_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_GMA_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_GMA_SEL_UARTE                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_GMA_SEL_SPI3                        _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_GMA_SEL_GMI                 _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_GMA_SEL_SDIO4                       _MK_ENUM_CONST(3)
+
+
+// Register APB_MISC_PP_PIN_MUX_CTL_C_0  
+#define APB_MISC_PP_PIN_MUX_CTL_C_0                     _MK_ADDR_CONST(0x88)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_SECURE                      0x0
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_WORD_COUNT                  0x1
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_RESET_VAL                   _MK_MASK_CONST(0xa8ca0000)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_GMD_SEL_SHIFT                       _MK_SHIFT_CONST(30)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_GMD_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_C_0_GMD_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_GMD_SEL_RANGE                       31:30
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_GMD_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_GMD_SEL_DEFAULT                     _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_GMD_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_GMD_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_GMD_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_GMD_SEL_RSVD1                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_GMD_SEL_NAND                        _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_GMD_SEL_GMI                 _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_GMD_SEL_SFLASH                      _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_GMB_SEL_SHIFT                       _MK_SHIFT_CONST(28)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_GMB_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_C_0_GMB_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_GMB_SEL_RANGE                       29:28
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_GMB_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_GMB_SEL_DEFAULT                     _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_GMB_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_GMB_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_GMB_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_GMB_SEL_IDE                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_GMB_SEL_NAND                        _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_GMB_SEL_GMI                 _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_GMB_SEL_GMI_INT                     _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP4_SEL_SHIFT                      _MK_SHIFT_CONST(26)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP4_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_C_0_DAP4_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP4_SEL_RANGE                      27:26
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP4_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP4_SEL_DEFAULT                    _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP4_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP4_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP4_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP4_SEL_DAP4                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP4_SEL_RSVD2                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP4_SEL_GMI                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP4_SEL_RSVD4                      _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP3_SEL_SHIFT                      _MK_SHIFT_CONST(24)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP3_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_C_0_DAP3_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP3_SEL_RANGE                      25:24
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP3_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP3_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP3_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP3_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP3_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP3_SEL_DAP3                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP3_SEL_RSVD2                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP3_SEL_RSVD3                      _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP3_SEL_RSVD4                      _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP2_SEL_SHIFT                      _MK_SHIFT_CONST(22)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP2_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_C_0_DAP2_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP2_SEL_RANGE                      23:22
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP2_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP2_SEL_DEFAULT                    _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP2_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP2_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP2_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP2_SEL_DAP2                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP2_SEL_TWC                        _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP2_SEL_RSVD3                      _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP2_SEL_GMI                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP1_SEL_SHIFT                      _MK_SHIFT_CONST(20)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP1_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_C_0_DAP1_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP1_SEL_RANGE                      21:20
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP1_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP1_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP1_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP1_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP1_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP1_SEL_DAP1                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP1_SEL_RSVD2                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP1_SEL_GMI                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP1_SEL_SDIO2                      _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRRX_SEL_SHIFT                      _MK_SHIFT_CONST(18)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRRX_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_C_0_IRRX_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRRX_SEL_RANGE                      19:18
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRRX_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRRX_SEL_DEFAULT                    _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRRX_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRRX_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRRX_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRRX_SEL_UARTA                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRRX_SEL_UARTB                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRRX_SEL_GMI                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRRX_SEL_SPI4                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRTX_SEL_SHIFT                      _MK_SHIFT_CONST(16)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRTX_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_C_0_IRTX_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRTX_SEL_RANGE                      17:16
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRTX_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRTX_SEL_DEFAULT                    _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRTX_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRTX_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRTX_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRTX_SEL_UARTA                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRTX_SEL_UARTB                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRTX_SEL_GMI                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRTX_SEL_SPI4                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCC_SEL_SHIFT                      _MK_SHIFT_CONST(14)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCC_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_C_0_KBCC_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCC_SEL_RANGE                      15:14
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCC_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCC_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCC_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCC_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCC_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCC_SEL_KBC                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCC_SEL_NAND                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCC_SEL_TRACE                      _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCC_SEL_EMC_TEST1_DLL                      _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCB_SEL_SHIFT                      _MK_SHIFT_CONST(12)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCB_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_C_0_KBCB_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCB_SEL_RANGE                      13:12
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCB_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCB_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCB_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCB_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCB_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCB_SEL_KBC                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCB_SEL_NAND                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCB_SEL_SDIO2                      _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCB_SEL_MIO                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCA_SEL_SHIFT                      _MK_SHIFT_CONST(10)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCA_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_C_0_KBCA_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCA_SEL_RANGE                      11:10
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCA_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCA_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCA_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCA_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCA_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCA_SEL_KBC                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCA_SEL_NAND                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCA_SEL_SDIO2                      _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCA_SEL_EMC_TEST0_DLL                      _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_I2CP_SEL_SHIFT                      _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_I2CP_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_C_0_I2CP_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_I2CP_SEL_RANGE                      9:8
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_I2CP_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_I2CP_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_I2CP_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_I2CP_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_I2CP_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_I2CP_SEL_I2C                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_I2CP_SEL_RSVD2                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_I2CP_SEL_RSVD3                      _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_I2CP_SEL_RSVD4                      _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CSUS_SEL_SHIFT                      _MK_SHIFT_CONST(6)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CSUS_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_C_0_CSUS_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CSUS_SEL_RANGE                      7:6
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CSUS_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CSUS_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CSUS_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CSUS_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CSUS_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CSUS_SEL_PLLC_OUT1                  _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CSUS_SEL_PLLP_OUT2                  _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CSUS_SEL_PLLP_OUT3                  _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CSUS_SEL_VI_SENSOR_CLK                      _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV2_SEL_SHIFT                     _MK_SHIFT_CONST(4)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV2_SEL_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV2_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV2_SEL_RANGE                     5:4
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV2_SEL_WOFFSET                   0x0
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV2_SEL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV2_SEL_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV2_SEL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV2_SEL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV2_SEL_OSC                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV2_SEL_AHB_CLK                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV2_SEL_APB_CLK                   _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV2_SEL_PLLP_OUT4                 _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV1_SEL_SHIFT                     _MK_SHIFT_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV1_SEL_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV1_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV1_SEL_RANGE                     3:2
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV1_SEL_WOFFSET                   0x0
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV1_SEL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV1_SEL_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV1_SEL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV1_SEL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV1_SEL_OSC                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV1_SEL_PLLA_OUT                  _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV1_SEL_PLLM_OUT1                 _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV1_SEL_AUDIO_SYNC                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DDC_SEL_SHIFT                       _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DDC_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_C_0_DDC_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DDC_SEL_RANGE                       1:0
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DDC_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DDC_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DDC_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DDC_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DDC_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DDC_SEL_I2C2                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DDC_SEL_RSVD1                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DDC_SEL_RSVD2                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DDC_SEL_RSVD3                       _MK_ENUM_CONST(3)
+
+
+// Register APB_MISC_PP_PIN_MUX_CTL_D_0  
+#define APB_MISC_PP_PIN_MUX_CTL_D_0                     _MK_ADDR_CONST(0x8c)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SECURE                      0x0
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_WORD_COUNT                  0x1
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_RESET_VAL                   _MK_MASK_CONST(0xffc00022)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIA_SEL_SHIFT                      _MK_SHIFT_CONST(30)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIA_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_D_0_SPIA_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIA_SEL_RANGE                      31:30
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIA_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIA_SEL_DEFAULT                    _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIA_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIA_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIA_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIA_SEL_SPI1                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIA_SEL_SPI2                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIA_SEL_SPI3                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIA_SEL_GMI                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIB_SEL_SHIFT                      _MK_SHIFT_CONST(28)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIB_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_D_0_SPIB_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIB_SEL_RANGE                      29:28
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIB_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIB_SEL_DEFAULT                    _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIB_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIB_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIB_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIB_SEL_SPI1                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIB_SEL_SPI2                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIB_SEL_SPI3                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIB_SEL_GMI                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIC_SEL_SHIFT                      _MK_SHIFT_CONST(26)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIC_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_D_0_SPIC_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIC_SEL_RANGE                      27:26
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIC_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIC_SEL_DEFAULT                    _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIC_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIC_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIC_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIC_SEL_SPI1                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIC_SEL_SPI2                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIC_SEL_SPI3                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIC_SEL_GMI                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPID_SEL_SHIFT                      _MK_SHIFT_CONST(24)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPID_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_D_0_SPID_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPID_SEL_RANGE                      25:24
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPID_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPID_SEL_DEFAULT                    _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPID_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPID_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPID_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPID_SEL_SPI2                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPID_SEL_SPI1                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPID_SEL_SPI2_ALT                   _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPID_SEL_GMI                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIE_SEL_SHIFT                      _MK_SHIFT_CONST(22)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIE_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_D_0_SPIE_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIE_SEL_RANGE                      23:22
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIE_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIE_SEL_DEFAULT                    _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIE_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIE_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIE_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIE_SEL_SPI2                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIE_SEL_SPI1                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIE_SEL_SPI2_ALT                   _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIE_SEL_GMI                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIF_SEL_SHIFT                      _MK_SHIFT_CONST(20)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIF_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_D_0_SPIF_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIF_SEL_RANGE                      21:20
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIF_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIF_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIF_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIF_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIF_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIF_SEL_SPI3                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIF_SEL_SPI1                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIF_SEL_SPI2                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIF_SEL_RSVD                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIG_SEL_SHIFT                      _MK_SHIFT_CONST(18)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIG_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_D_0_SPIG_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIG_SEL_RANGE                      19:18
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIG_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIG_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIG_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIG_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIG_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIG_SEL_SPI3                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIG_SEL_SPI2                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIG_SEL_SPI2_ALT                   _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIG_SEL_I2C                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIH_SEL_SHIFT                      _MK_SHIFT_CONST(16)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIH_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_D_0_SPIH_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIH_SEL_RANGE                      17:16
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIH_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIH_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIH_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIH_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIH_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIH_SEL_SPI3                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIH_SEL_SPI2                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIH_SEL_SPI2_ALT                   _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIH_SEL_I2C                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDD_SEL_SHIFT                       _MK_SHIFT_CONST(14)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDD_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_D_0_SDD_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDD_SEL_RANGE                       15:14
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDD_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDD_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDD_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDD_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDD_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDD_SEL_UARTA                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDD_SEL_PWM                 _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDD_SEL_SDIO3                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDD_SEL_SPI3                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDC_SEL_SHIFT                       _MK_SHIFT_CONST(12)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDC_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_D_0_SDC_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDC_SEL_RANGE                       13:12
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDC_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDC_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDC_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDC_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDC_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDC_SEL_PWM                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDC_SEL_TWC                 _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDC_SEL_SDIO3                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDC_SEL_SPI3                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDB_SEL_SHIFT                       _MK_SHIFT_CONST(10)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDB_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_D_0_SDB_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDB_SEL_RANGE                       11:10
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDB_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDB_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDB_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDB_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDB_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDB_SEL_UARTA                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDB_SEL_PWM                 _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDB_SEL_SDIO3                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDB_SEL_SPI2                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDI_SEL_SHIFT                      _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDI_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_D_0_SPDI_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDI_SEL_RANGE                      9:8
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDI_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDI_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDI_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDI_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDI_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDI_SEL_SPDIF                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDI_SEL_RSVD                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDI_SEL_I2C                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDI_SEL_SDIO2                      _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDO_SEL_SHIFT                      _MK_SHIFT_CONST(6)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDO_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_D_0_SPDO_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDO_SEL_RANGE                      7:6
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDO_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDO_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDO_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDO_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDO_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDO_SEL_SPDIF                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDO_SEL_RSVD                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDO_SEL_I2C                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDO_SEL_SDIO2                      _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPU_SEL_SHIFT                       _MK_SHIFT_CONST(4)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPU_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_D_0_GPU_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPU_SEL_RANGE                       5:4
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPU_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPU_SEL_DEFAULT                     _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPU_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPU_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPU_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPU_SEL_PWM                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPU_SEL_UARTA                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPU_SEL_GMI                 _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPU_SEL_RSVD4                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPV_SEL_SHIFT                       _MK_SHIFT_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPV_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_D_0_GPV_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPV_SEL_RANGE                       3:2
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPV_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPV_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPV_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPV_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPV_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPV_SEL_PCIE                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPV_SEL_RSVD2                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPV_SEL_RSVD3                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPV_SEL_RSVD4                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GME_SEL_SHIFT                       _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GME_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_D_0_GME_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GME_SEL_RANGE                       1:0
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GME_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GME_SEL_DEFAULT                     _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GME_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GME_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GME_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GME_SEL_RSVD1                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GME_SEL_DAP5                        _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GME_SEL_GMI                 _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GME_SEL_SDIO4                       _MK_ENUM_CONST(3)
+
+
+// Register APB_MISC_PP_PIN_MUX_CTL_E_0  
+#define APB_MISC_PP_PIN_MUX_CTL_E_0                     _MK_ADDR_CONST(0x90)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_SECURE                      0x0
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_WORD_COUNT                  0x1
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVP0_SEL_SHIFT                      _MK_SHIFT_CONST(30)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVP0_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_E_0_LVP0_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVP0_SEL_RANGE                      31:30
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVP0_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVP0_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVP0_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVP0_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVP0_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVP0_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVP0_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVP0_SEL_RSVD3                      _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVP0_SEL_RSVD                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM1_SEL_SHIFT                       _MK_SHIFT_CONST(28)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM1_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_E_0_LM1_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM1_SEL_RANGE                       29:28
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM1_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM1_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM1_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM1_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM1_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM1_SEL_DISPLAYA                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM1_SEL_DISPLAYB                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM1_SEL_RSVD3                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM1_SEL_CRT                 _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM0_SEL_SHIFT                       _MK_SHIFT_CONST(26)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM0_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_E_0_LM0_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM0_SEL_RANGE                       27:26
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM0_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM0_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM0_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM0_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM0_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM0_SEL_DISPLAYA                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM0_SEL_DISPLAYB                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM0_SEL_SPI3                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM0_SEL_RSVD                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVS_SEL_SHIFT                       _MK_SHIFT_CONST(24)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVS_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_E_0_LVS_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVS_SEL_RANGE                       25:24
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVS_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVS_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVS_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVS_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVS_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVS_SEL_DISPLAYA                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVS_SEL_DISPLAYB                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVS_SEL_XIO                 _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVS_SEL_RSVD                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LHS_SEL_SHIFT                       _MK_SHIFT_CONST(22)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LHS_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_E_0_LHS_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LHS_SEL_RANGE                       23:22
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LHS_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LHS_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LHS_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LHS_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LHS_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LHS_SEL_DISPLAYA                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LHS_SEL_DISPLAYB                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LHS_SEL_XIO                 _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LHS_SEL_RSVD                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC1_SEL_SHIFT                      _MK_SHIFT_CONST(20)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC1_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_E_0_LSC1_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC1_SEL_RANGE                      21:20
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC1_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC1_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC1_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC1_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC1_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC1_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC1_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC1_SEL_SPI3                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC1_SEL_HDMI                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC0_SEL_SHIFT                      _MK_SHIFT_CONST(18)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC0_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_E_0_LSC0_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC0_SEL_RANGE                      19:18
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC0_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC0_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC0_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC0_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC0_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC0_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC0_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC0_SEL_XIO                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC0_SEL_RSVD                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSCK_SEL_SHIFT                      _MK_SHIFT_CONST(16)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSCK_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_E_0_LSCK_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSCK_SEL_RANGE                      17:16
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSCK_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSCK_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSCK_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSCK_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSCK_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSCK_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSCK_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSCK_SEL_SPI3                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSCK_SEL_HDMI                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LDC_SEL_SHIFT                       _MK_SHIFT_CONST(14)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LDC_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_E_0_LDC_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LDC_SEL_RANGE                       15:14
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LDC_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LDC_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LDC_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LDC_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LDC_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LDC_SEL_DISPLAYA                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LDC_SEL_DISPLAYB                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LDC_SEL_RSVD                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LDC_SEL_RSVD4                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LCSN_SEL_SHIFT                      _MK_SHIFT_CONST(12)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LCSN_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_E_0_LCSN_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LCSN_SEL_RANGE                      13:12
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LCSN_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LCSN_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LCSN_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LCSN_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LCSN_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LCSN_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LCSN_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LCSN_SEL_SPI3                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LCSN_SEL_RSVD4                      _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSPI_SEL_SHIFT                      _MK_SHIFT_CONST(10)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSPI_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_E_0_LSPI_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSPI_SEL_RANGE                      11:10
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSPI_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSPI_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSPI_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSPI_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSPI_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSPI_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSPI_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSPI_SEL_XIO                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSPI_SEL_HDMI                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDA_SEL_SHIFT                      _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDA_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_E_0_LSDA_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDA_SEL_RANGE                      9:8
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDA_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDA_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDA_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDA_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDA_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDA_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDA_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDA_SEL_SPI3                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDA_SEL_HDMI                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDI_SEL_SHIFT                      _MK_SHIFT_CONST(6)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDI_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_E_0_LSDI_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDI_SEL_RANGE                      7:6
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDI_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDI_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDI_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDI_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDI_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDI_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDI_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDI_SEL_SPI3                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDI_SEL_RSVD                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW2_SEL_SHIFT                      _MK_SHIFT_CONST(4)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW2_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_E_0_LPW2_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW2_SEL_RANGE                      5:4
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW2_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW2_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW2_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW2_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW2_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW2_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW2_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW2_SEL_SPI3                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW2_SEL_HDMI                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW1_SEL_SHIFT                      _MK_SHIFT_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW1_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_E_0_LPW1_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW1_SEL_RANGE                      3:2
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW1_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW1_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW1_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW1_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW1_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW1_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW1_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW1_SEL_RSVD                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW1_SEL_RSVD4                      _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW0_SEL_SHIFT                      _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW0_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_E_0_LPW0_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW0_SEL_RANGE                      1:0
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW0_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW0_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW0_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW0_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW0_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW0_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW0_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW0_SEL_SPI3                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW0_SEL_HDMI                       _MK_ENUM_CONST(3)
+
+
+// Register APB_MISC_PP_PIN_MUX_CTL_F_0  
+#define APB_MISC_PP_PIN_MUX_CTL_F_0                     _MK_ADDR_CONST(0x94)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_SECURE                      0x0
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_WORD_COUNT                  0x1
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD15_SEL_SHIFT                      _MK_SHIFT_CONST(30)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD15_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_F_0_LD15_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD15_SEL_RANGE                      31:30
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD15_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD15_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD15_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD15_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD15_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD15_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD15_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD15_SEL_XIO                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD15_SEL_RSVD                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD14_SEL_SHIFT                      _MK_SHIFT_CONST(28)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD14_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_F_0_LD14_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD14_SEL_RANGE                      29:28
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD14_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD14_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD14_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD14_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD14_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD14_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD14_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD14_SEL_XIO                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD14_SEL_RSVD                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD13_SEL_SHIFT                      _MK_SHIFT_CONST(26)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD13_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_F_0_LD13_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD13_SEL_RANGE                      27:26
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD13_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD13_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD13_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD13_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD13_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD13_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD13_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD13_SEL_XIO                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD13_SEL_RSVD                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD12_SEL_SHIFT                      _MK_SHIFT_CONST(24)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD12_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_F_0_LD12_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD12_SEL_RANGE                      25:24
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD12_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD12_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD12_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD12_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD12_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD12_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD12_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD12_SEL_XIO                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD12_SEL_RSVD                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD11_SEL_SHIFT                      _MK_SHIFT_CONST(22)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD11_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_F_0_LD11_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD11_SEL_RANGE                      23:22
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD11_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD11_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD11_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD11_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD11_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD11_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD11_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD11_SEL_XIO                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD11_SEL_RSVD                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD10_SEL_SHIFT                      _MK_SHIFT_CONST(20)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD10_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_F_0_LD10_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD10_SEL_RANGE                      21:20
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD10_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD10_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD10_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD10_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD10_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD10_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD10_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD10_SEL_XIO                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD10_SEL_RSVD                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD9_SEL_SHIFT                       _MK_SHIFT_CONST(18)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD9_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_F_0_LD9_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD9_SEL_RANGE                       19:18
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD9_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD9_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD9_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD9_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD9_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD9_SEL_DISPLAYA                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD9_SEL_DISPLAYB                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD9_SEL_XIO                 _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD9_SEL_RSVD                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD8_SEL_SHIFT                       _MK_SHIFT_CONST(16)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD8_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_F_0_LD8_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD8_SEL_RANGE                       17:16
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD8_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD8_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD8_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD8_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD8_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD8_SEL_DISPLAYA                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD8_SEL_DISPLAYB                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD8_SEL_XIO                 _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD8_SEL_RSVD                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD7_SEL_SHIFT                       _MK_SHIFT_CONST(14)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD7_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_F_0_LD7_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD7_SEL_RANGE                       15:14
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD7_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD7_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD7_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD7_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD7_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD7_SEL_DISPLAYA                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD7_SEL_DISPLAYB                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD7_SEL_XIO                 _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD7_SEL_RSVD                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD6_SEL_SHIFT                       _MK_SHIFT_CONST(12)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD6_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_F_0_LD6_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD6_SEL_RANGE                       13:12
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD6_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD6_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD6_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD6_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD6_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD6_SEL_DISPLAYA                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD6_SEL_DISPLAYB                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD6_SEL_XIO                 _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD6_SEL_RSVD                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD5_SEL_SHIFT                       _MK_SHIFT_CONST(10)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD5_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_F_0_LD5_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD5_SEL_RANGE                       11:10
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD5_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD5_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD5_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD5_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD5_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD5_SEL_DISPLAYA                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD5_SEL_DISPLAYB                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD5_SEL_XIO                 _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD5_SEL_RSVD                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD4_SEL_SHIFT                       _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD4_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_F_0_LD4_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD4_SEL_RANGE                       9:8
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD4_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD4_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD4_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD4_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD4_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD4_SEL_DISPLAYA                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD4_SEL_DISPLAYB                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD4_SEL_XIO                 _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD4_SEL_RSVD                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD3_SEL_SHIFT                       _MK_SHIFT_CONST(6)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD3_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_F_0_LD3_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD3_SEL_RANGE                       7:6
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD3_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD3_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD3_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD3_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD3_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD3_SEL_DISPLAYA                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD3_SEL_DISPLAYB                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD3_SEL_XIO                 _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD3_SEL_RSVD                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD2_SEL_SHIFT                       _MK_SHIFT_CONST(4)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD2_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_F_0_LD2_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD2_SEL_RANGE                       5:4
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD2_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD2_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD2_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD2_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD2_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD2_SEL_DISPLAYA                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD2_SEL_DISPLAYB                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD2_SEL_XIO                 _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD2_SEL_RSVD                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD1_SEL_SHIFT                       _MK_SHIFT_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD1_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_F_0_LD1_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD1_SEL_RANGE                       3:2
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD1_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD1_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD1_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD1_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD1_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD1_SEL_DISPLAYA                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD1_SEL_DISPLAYB                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD1_SEL_XIO                 _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD1_SEL_RSVD                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD0_SEL_SHIFT                       _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD0_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_F_0_LD0_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD0_SEL_RANGE                       1:0
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD0_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD0_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD0_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD0_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD0_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD0_SEL_DISPLAYA                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD0_SEL_DISPLAYB                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD0_SEL_XIO                 _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD0_SEL_RSVD                        _MK_ENUM_CONST(3)
+
+
+// Register APB_MISC_PP_PIN_MUX_CTL_G_0  
+#define APB_MISC_PP_PIN_MUX_CTL_G_0                     _MK_ADDR_CONST(0x98)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_SECURE                      0x0
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_WORD_COUNT                  0x1
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_RESET_MASK                  _MK_MASK_CONST(0xfcffcfff)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_READ_MASK                   _MK_MASK_CONST(0xfcffcfff)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_WRITE_MASK                  _MK_MASK_CONST(0xfcffcfff)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_DTF_SEL_SHIFT                       _MK_SHIFT_CONST(30)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_DTF_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_G_0_DTF_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_DTF_SEL_RANGE                       31:30
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_DTF_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_DTF_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_DTF_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_DTF_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_DTF_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_DTF_SEL_I2C3                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_DTF_SEL_RSVD2                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_DTF_SEL_VI                  _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_DTF_SEL_RSVD4                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_GPU7_SEL_SHIFT                      _MK_SHIFT_CONST(28)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_GPU7_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_G_0_GPU7_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_GPU7_SEL_RANGE                      29:28
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_GPU7_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_GPU7_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_GPU7_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_GPU7_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_GPU7_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_GPU7_SEL_RTCK                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_GPU7_SEL_RSVD1                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_GPU7_SEL_RSVD2                      _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_GPU7_SEL_RSVD3                      _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_KBCD_SEL_SHIFT                      _MK_SHIFT_CONST(26)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_KBCD_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_G_0_KBCD_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_KBCD_SEL_RANGE                      27:26
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_KBCD_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_KBCD_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_KBCD_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_KBCD_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_KBCD_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_KBCD_SEL_KBC                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_KBCD_SEL_NAND                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_KBCD_SEL_SDIO2                      _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_KBCD_SEL_MIO                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_PTA_SEL_SHIFT                       _MK_SHIFT_CONST(22)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_PTA_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_G_0_PTA_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_PTA_SEL_RANGE                       23:22
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_PTA_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_PTA_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_PTA_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_PTA_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_PTA_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_PTA_SEL_I2C2                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_PTA_SEL_HDMI                        _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_PTA_SEL_GMI                 _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_PTA_SEL_RSVD3                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_CRTP_SEL_SHIFT                      _MK_SHIFT_CONST(20)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_CRTP_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_G_0_CRTP_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_CRTP_SEL_RANGE                      21:20
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_CRTP_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_CRTP_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_CRTP_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_CRTP_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_CRTP_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_CRTP_SEL_CRT                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_CRTP_SEL_RSVD2                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_CRTP_SEL_RSVD3                      _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_CRTP_SEL_RSVD4                      _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_PMC_SEL_SHIFT                       _MK_SHIFT_CONST(18)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_PMC_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_G_0_PMC_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_PMC_SEL_RANGE                       19:18
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_PMC_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_PMC_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_PMC_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_PMC_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_PMC_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_PMC_SEL_PWR_ON                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_PMC_SEL_PWR_INTR                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LDI_SEL_SHIFT                       _MK_SHIFT_CONST(16)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LDI_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_G_0_LDI_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LDI_SEL_RANGE                       17:16
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LDI_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LDI_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LDI_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LDI_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LDI_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LDI_SEL_DISPLAYA                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LDI_SEL_DISPLAYB                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LDI_SEL_RSVD3                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LDI_SEL_RSVD                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LPP_SEL_SHIFT                       _MK_SHIFT_CONST(14)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LPP_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_G_0_LPP_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LPP_SEL_RANGE                       15:14
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LPP_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LPP_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LPP_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LPP_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LPP_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LPP_SEL_DISPLAYA                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LPP_SEL_DISPLAYB                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LPP_SEL_RSVD3                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LPP_SEL_RSVD                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP0_SEL_SHIFT                      _MK_SHIFT_CONST(10)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP0_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_G_0_LHP0_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP0_SEL_RANGE                      11:10
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP0_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP0_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP0_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP0_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP0_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP0_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP0_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP0_SEL_RSVD3                      _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP0_SEL_RSVD4                      _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LVP1_SEL_SHIFT                      _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LVP1_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_G_0_LVP1_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LVP1_SEL_RANGE                      9:8
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LVP1_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LVP1_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LVP1_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LVP1_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LVP1_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LVP1_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LVP1_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LVP1_SEL_RSVD3                      _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LVP1_SEL_RSVD4                      _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP2_SEL_SHIFT                      _MK_SHIFT_CONST(6)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP2_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_G_0_LHP2_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP2_SEL_RANGE                      7:6
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP2_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP2_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP2_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP2_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP2_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP2_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP2_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP2_SEL_RSVD3                      _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP2_SEL_RSVD4                      _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP1_SEL_SHIFT                      _MK_SHIFT_CONST(4)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP1_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_G_0_LHP1_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP1_SEL_RANGE                      5:4
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP1_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP1_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP1_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP1_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP1_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP1_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP1_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP1_SEL_RSVD3                      _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP1_SEL_RSVD                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD17_SEL_SHIFT                      _MK_SHIFT_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD17_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_G_0_LD17_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD17_SEL_RANGE                      3:2
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD17_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD17_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD17_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD17_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD17_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD17_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD17_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD17_SEL_RSVD                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD17_SEL_RSVD4                      _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD16_SEL_SHIFT                      _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD16_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_G_0_LD16_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD16_SEL_RANGE                      1:0
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD16_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD16_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD16_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD16_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD16_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD16_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD16_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD16_SEL_XIO                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD16_SEL_RSVD                       _MK_ENUM_CONST(3)
+
+
+// Register APB_MISC_PP_PIN_MUX_CTL_H_0  
+#define APB_MISC_PP_PIN_MUX_CTL_H_0                     _MK_ADDR_CONST(0x9c)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_SECURE                      0x0
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_WORD_COUNT                  0x1
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_RESET_MASK                  _MK_MASK_CONST(0x3fffff)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_READ_MASK                   _MK_MASK_CONST(0x3fffff)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_WRITE_MASK                  _MK_MASK_CONST(0x3fffff)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4M_SEL_SHIFT                     _MK_SHIFT_CONST(21)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4M_SEL_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4M_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4M_SEL_RANGE                     21:21
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4M_SEL_WOFFSET                   0x0
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4M_SEL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4M_SEL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4M_SEL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4M_SEL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4M_SEL_DAP4_SLAVE                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4M_SEL_DAP4_MASTER                       _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3M_SEL_SHIFT                     _MK_SHIFT_CONST(20)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3M_SEL_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3M_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3M_SEL_RANGE                     20:20
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3M_SEL_WOFFSET                   0x0
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3M_SEL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3M_SEL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3M_SEL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3M_SEL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3M_SEL_DAP3_SLAVE                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3M_SEL_DAP3_MASTER                       _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2M_SEL_SHIFT                     _MK_SHIFT_CONST(19)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2M_SEL_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2M_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2M_SEL_RANGE                     19:19
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2M_SEL_WOFFSET                   0x0
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2M_SEL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2M_SEL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2M_SEL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2M_SEL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2M_SEL_DAP2_SLAVE                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2M_SEL_DAP2_MASTER                       _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1M_SEL_SHIFT                     _MK_SHIFT_CONST(18)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1M_SEL_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1M_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1M_SEL_RANGE                     18:18
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1M_SEL_WOFFSET                   0x0
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1M_SEL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1M_SEL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1M_SEL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1M_SEL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1M_SEL_DAP1_SLAVE                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1M_SEL_DAP1_MASTER                       _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC3_SEL_SHIFT                      _MK_SHIFT_CONST(16)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC3_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_H_0_DAC3_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC3_SEL_RANGE                      17:16
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC3_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC3_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC3_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC3_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC3_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC3_SEL_DAP1                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC3_SEL_DAP2                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC3_SEL_DAP3                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC3_SEL_DAP4                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC2_SEL_SHIFT                      _MK_SHIFT_CONST(14)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC2_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_H_0_DAC2_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC2_SEL_RANGE                      15:14
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC2_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC2_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC2_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC2_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC2_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC2_SEL_DAP1                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC2_SEL_DAP2                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC2_SEL_DAP3                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC2_SEL_DAP4                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC1_SEL_SHIFT                      _MK_SHIFT_CONST(12)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC1_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_H_0_DAC1_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC1_SEL_RANGE                      13:12
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC1_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC1_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC1_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC1_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC1_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC1_SEL_DAP1                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC1_SEL_DAP2                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC1_SEL_DAP3                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC1_SEL_DAP4                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4_CNTRL_MUX_SELECT_SHIFT                 _MK_SHIFT_CONST(9)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4_CNTRL_MUX_SELECT_FIELD                 (_MK_MASK_CONST(0x7) << APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4_CNTRL_MUX_SELECT_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4_CNTRL_MUX_SELECT_RANGE                 11:9
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4_CNTRL_MUX_SELECT_WOFFSET                       0x0
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4_CNTRL_MUX_SELECT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4_CNTRL_MUX_SELECT_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4_CNTRL_MUX_SELECT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4_CNTRL_MUX_SELECT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4_CNTRL_MUX_SELECT_DAC1                  _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4_CNTRL_MUX_SELECT_DAC2                  _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4_CNTRL_MUX_SELECT_DAC3                  _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4_CNTRL_MUX_SELECT_RSVD                  _MK_ENUM_CONST(3)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4_CNTRL_MUX_SELECT_DAP1                  _MK_ENUM_CONST(4)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4_CNTRL_MUX_SELECT_DAP2                  _MK_ENUM_CONST(5)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4_CNTRL_MUX_SELECT_DAP3                  _MK_ENUM_CONST(6)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4_CNTRL_MUX_SELECT_RSVD2                 _MK_ENUM_CONST(7)
+
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3_CNTRL_MUX_SELECT_SHIFT                 _MK_SHIFT_CONST(6)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3_CNTRL_MUX_SELECT_FIELD                 (_MK_MASK_CONST(0x7) << APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3_CNTRL_MUX_SELECT_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3_CNTRL_MUX_SELECT_RANGE                 8:6
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3_CNTRL_MUX_SELECT_WOFFSET                       0x0
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3_CNTRL_MUX_SELECT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3_CNTRL_MUX_SELECT_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3_CNTRL_MUX_SELECT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3_CNTRL_MUX_SELECT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3_CNTRL_MUX_SELECT_DAC1                  _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3_CNTRL_MUX_SELECT_DAC2                  _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3_CNTRL_MUX_SELECT_DAC3                  _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3_CNTRL_MUX_SELECT_RSVD1                 _MK_ENUM_CONST(3)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3_CNTRL_MUX_SELECT_DAP1                  _MK_ENUM_CONST(4)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3_CNTRL_MUX_SELECT_DAP2                  _MK_ENUM_CONST(5)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3_CNTRL_MUX_SELECT_RSVD2                 _MK_ENUM_CONST(6)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3_CNTRL_MUX_SELECT_DAP4                  _MK_ENUM_CONST(7)
+
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2_CNTRL_MUX_SELECT_SHIFT                 _MK_SHIFT_CONST(3)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2_CNTRL_MUX_SELECT_FIELD                 (_MK_MASK_CONST(0x7) << APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2_CNTRL_MUX_SELECT_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2_CNTRL_MUX_SELECT_RANGE                 5:3
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2_CNTRL_MUX_SELECT_WOFFSET                       0x0
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2_CNTRL_MUX_SELECT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2_CNTRL_MUX_SELECT_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2_CNTRL_MUX_SELECT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2_CNTRL_MUX_SELECT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2_CNTRL_MUX_SELECT_DAC1                  _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2_CNTRL_MUX_SELECT_DAC2                  _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2_CNTRL_MUX_SELECT_DAC3                  _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2_CNTRL_MUX_SELECT_RSVD1                 _MK_ENUM_CONST(3)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2_CNTRL_MUX_SELECT_DAP1                  _MK_ENUM_CONST(4)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2_CNTRL_MUX_SELECT_RSVD2                 _MK_ENUM_CONST(5)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2_CNTRL_MUX_SELECT_DAP3                  _MK_ENUM_CONST(6)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2_CNTRL_MUX_SELECT_DAP4                  _MK_ENUM_CONST(7)
+
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1_CNTRL_MUX_SELECT_SHIFT                 _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1_CNTRL_MUX_SELECT_FIELD                 (_MK_MASK_CONST(0x7) << APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1_CNTRL_MUX_SELECT_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1_CNTRL_MUX_SELECT_RANGE                 2:0
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1_CNTRL_MUX_SELECT_WOFFSET                       0x0
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1_CNTRL_MUX_SELECT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1_CNTRL_MUX_SELECT_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1_CNTRL_MUX_SELECT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1_CNTRL_MUX_SELECT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1_CNTRL_MUX_SELECT_DAC1                  _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1_CNTRL_MUX_SELECT_DAC2                  _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1_CNTRL_MUX_SELECT_DAC3                  _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1_CNTRL_MUX_SELECT_RSVD1                 _MK_ENUM_CONST(3)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1_CNTRL_MUX_SELECT_RSVD2                 _MK_ENUM_CONST(4)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1_CNTRL_MUX_SELECT_DAP2                  _MK_ENUM_CONST(5)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1_CNTRL_MUX_SELECT_DAP3                  _MK_ENUM_CONST(6)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1_CNTRL_MUX_SELECT_DAP4                  _MK_ENUM_CONST(7)
+
+
+// Register APB_MISC_PP_PULLUPDOWN_REG_A_0  
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0                  _MK_ADDR_CONST(0xa0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_SECURE                   0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_WORD_COUNT                       0x1
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_RESET_VAL                        _MK_MASK_CONST(0x215556aa)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_GPV_PU_PD_SHIFT                  _MK_SHIFT_CONST(30)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_GPV_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_A_0_GPV_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_GPV_PU_PD_RANGE                  31:30
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_GPV_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_GPV_PU_PD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_GPV_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_GPV_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_GPV_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_GPV_PU_PD_INIT_ENUM                      NORMAL
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_GPV_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_GPV_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_GPV_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_GPV_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTF_PU_PD_SHIFT                  _MK_SHIFT_CONST(28)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTF_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_A_0_DTF_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTF_PU_PD_RANGE                  29:28
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTF_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTF_PU_PD_DEFAULT                        _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTF_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTF_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTF_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTF_PU_PD_INIT_ENUM                      PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTF_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTF_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTF_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTF_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTE_PU_PD_SHIFT                  _MK_SHIFT_CONST(26)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTE_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_A_0_DTE_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTE_PU_PD_RANGE                  27:26
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTE_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTE_PU_PD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTE_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTE_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTE_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTE_PU_PD_INIT_ENUM                      NORMAL
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTE_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTE_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTE_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTE_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTD_PU_PD_SHIFT                  _MK_SHIFT_CONST(24)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTD_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_A_0_DTD_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTD_PU_PD_RANGE                  25:24
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTD_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTD_PU_PD_DEFAULT                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTD_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTD_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTD_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTD_PU_PD_INIT_ENUM                      PULL_DOWN
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTD_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTD_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTD_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTD_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTC_PU_PD_SHIFT                  _MK_SHIFT_CONST(22)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTC_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_A_0_DTC_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTC_PU_PD_RANGE                  23:22
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTC_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTC_PU_PD_DEFAULT                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTC_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTC_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTC_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTC_PU_PD_INIT_ENUM                      PULL_DOWN
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTC_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTC_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTC_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTC_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTB_PU_PD_SHIFT                  _MK_SHIFT_CONST(20)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTB_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_A_0_DTB_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTB_PU_PD_RANGE                  21:20
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTB_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTB_PU_PD_DEFAULT                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTB_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTB_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTB_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTB_PU_PD_INIT_ENUM                      PULL_DOWN
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTB_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTB_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTB_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTB_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTA_PU_PD_SHIFT                  _MK_SHIFT_CONST(18)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTA_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_A_0_DTA_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTA_PU_PD_RANGE                  19:18
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTA_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTA_PU_PD_DEFAULT                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTA_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTA_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTA_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTA_PU_PD_INIT_ENUM                      PULL_DOWN
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTA_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTA_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTA_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTA_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP4_PU_PD_SHIFT                 _MK_SHIFT_CONST(16)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP4_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP4_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP4_PU_PD_RANGE                 17:16
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP4_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP4_PU_PD_DEFAULT                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP4_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP4_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP4_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP4_PU_PD_INIT_ENUM                     PULL_DOWN
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP4_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP4_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP4_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP4_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP3_PU_PD_SHIFT                 _MK_SHIFT_CONST(14)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP3_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP3_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP3_PU_PD_RANGE                 15:14
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP3_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP3_PU_PD_DEFAULT                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP3_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP3_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP3_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP3_PU_PD_INIT_ENUM                     PULL_DOWN
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP3_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP3_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP3_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP3_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP2_PU_PD_SHIFT                 _MK_SHIFT_CONST(12)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP2_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP2_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP2_PU_PD_RANGE                 13:12
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP2_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP2_PU_PD_DEFAULT                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP2_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP2_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP2_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP2_PU_PD_INIT_ENUM                     PULL_DOWN
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP2_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP2_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP2_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP2_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP1_PU_PD_SHIFT                 _MK_SHIFT_CONST(10)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP1_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP1_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP1_PU_PD_RANGE                 11:10
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP1_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP1_PU_PD_DEFAULT                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP1_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP1_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP1_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP1_PU_PD_INIT_ENUM                     PULL_DOWN
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP1_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP1_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP1_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP1_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATE_PU_PD_SHIFT                  _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATE_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_A_0_ATE_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATE_PU_PD_RANGE                  9:8
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATE_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATE_PU_PD_DEFAULT                        _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATE_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATE_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATE_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATE_PU_PD_INIT_ENUM                      PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATE_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATE_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATE_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATE_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATD_PU_PD_SHIFT                  _MK_SHIFT_CONST(6)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATD_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_A_0_ATD_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATD_PU_PD_RANGE                  7:6
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATD_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATD_PU_PD_DEFAULT                        _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATD_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATD_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATD_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATD_PU_PD_INIT_ENUM                      PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATD_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATD_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATD_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATD_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATC_PU_PD_SHIFT                  _MK_SHIFT_CONST(4)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATC_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_A_0_ATC_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATC_PU_PD_RANGE                  5:4
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATC_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATC_PU_PD_DEFAULT                        _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATC_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATC_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATC_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATC_PU_PD_INIT_ENUM                      PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATC_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATC_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATC_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATC_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATB_PU_PD_SHIFT                  _MK_SHIFT_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATB_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_A_0_ATB_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATB_PU_PD_RANGE                  3:2
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATB_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATB_PU_PD_DEFAULT                        _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATB_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATB_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATB_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATB_PU_PD_INIT_ENUM                      PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATB_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATB_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATB_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATB_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATA_PU_PD_SHIFT                  _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATA_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_A_0_ATA_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATA_PU_PD_RANGE                  1:0
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATA_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATA_PU_PD_DEFAULT                        _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATA_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATA_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATA_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATA_PU_PD_INIT_ENUM                      PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATA_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATA_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATA_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATA_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+
+// Register APB_MISC_PP_PULLUPDOWN_REG_B_0  
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0                  _MK_ADDR_CONST(0xa4)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SECURE                   0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_WORD_COUNT                       0x1
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_RESET_VAL                        _MK_MASK_CONST(0x6a8865aa)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXK_PU_PD_SHIFT                 _MK_SHIFT_CONST(30)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXK_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXK_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXK_PU_PD_RANGE                 31:30
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXK_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXK_PU_PD_DEFAULT                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXK_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXK_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXK_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXK_PU_PD_INIT_ENUM                     PULL_DOWN
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXK_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXK_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXK_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXK_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXD_PU_PD_SHIFT                 _MK_SHIFT_CONST(28)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXD_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXD_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXD_PU_PD_RANGE                 29:28
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXD_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXD_PU_PD_DEFAULT                       _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXD_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXD_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXD_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXD_PU_PD_INIT_ENUM                     PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXD_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXD_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXD_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXD_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXC_PU_PD_SHIFT                 _MK_SHIFT_CONST(26)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXC_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXC_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXC_PU_PD_RANGE                 27:26
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXC_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXC_PU_PD_DEFAULT                       _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXC_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXC_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXC_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXC_PU_PD_INIT_ENUM                     PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXC_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXC_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXC_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXC_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_CRTP_PU_PD_SHIFT                 _MK_SHIFT_CONST(24)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_CRTP_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_B_0_CRTP_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_CRTP_PU_PD_RANGE                 25:24
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_CRTP_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_CRTP_PU_PD_DEFAULT                       _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_CRTP_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_CRTP_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_CRTP_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_CRTP_PU_PD_INIT_ENUM                     PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_CRTP_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_CRTP_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_CRTP_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_CRTP_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXA_PU_PD_SHIFT                 _MK_SHIFT_CONST(22)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXA_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXA_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXA_PU_PD_RANGE                 23:22
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXA_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXA_PU_PD_DEFAULT                       _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXA_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXA_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXA_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXA_PU_PD_INIT_ENUM                     PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXA_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXA_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXA_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXA_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU_PU_PD_SHIFT                  _MK_SHIFT_CONST(20)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU_PU_PD_RANGE                  21:20
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU_PU_PD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU_PU_PD_INIT_ENUM                      NORMAL
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDO_PU_PD_SHIFT                 _MK_SHIFT_CONST(18)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDO_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDO_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDO_PU_PD_RANGE                 19:18
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDO_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDO_PU_PD_DEFAULT                       _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDO_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDO_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDO_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDO_PU_PD_INIT_ENUM                     PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDO_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDO_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDO_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDO_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDI_PU_PD_SHIFT                 _MK_SHIFT_CONST(16)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDI_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDI_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDI_PU_PD_RANGE                 17:16
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDI_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDI_PU_PD_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDI_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDI_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDI_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDI_PU_PD_INIT_ENUM                     NORMAL
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDI_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDI_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDI_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDI_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCD_PU_PD_SHIFT                 _MK_SHIFT_CONST(14)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCD_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCD_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCD_PU_PD_RANGE                 15:14
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCD_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCD_PU_PD_DEFAULT                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCD_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCD_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCD_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCD_PU_PD_INIT_ENUM                     PULL_DOWN
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCD_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCD_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCD_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCD_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCC_PU_PD_SHIFT                 _MK_SHIFT_CONST(12)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCC_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCC_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCC_PU_PD_RANGE                 13:12
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCC_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCC_PU_PD_DEFAULT                       _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCC_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCC_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCC_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCC_PU_PD_INIT_ENUM                     PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCC_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCC_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCC_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCC_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCB_PU_PD_SHIFT                 _MK_SHIFT_CONST(10)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCB_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCB_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCB_PU_PD_RANGE                 11:10
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCB_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCB_PU_PD_DEFAULT                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCB_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCB_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCB_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCB_PU_PD_INIT_ENUM                     PULL_DOWN
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCB_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCB_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCB_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCB_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCA_PU_PD_SHIFT                 _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCA_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCA_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCA_PU_PD_RANGE                 9:8
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCA_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCA_PU_PD_DEFAULT                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCA_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCA_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCA_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCA_PU_PD_INIT_ENUM                     PULL_DOWN
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCA_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCA_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCA_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCA_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU7_PU_PD_SHIFT                 _MK_SHIFT_CONST(6)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU7_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU7_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU7_PU_PD_RANGE                 7:6
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU7_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU7_PU_PD_DEFAULT                       _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU7_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU7_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU7_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU7_PU_PD_INIT_ENUM                     PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU7_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU7_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU7_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU7_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_PTA_PU_PD_SHIFT                  _MK_SHIFT_CONST(4)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_PTA_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_B_0_PTA_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_PTA_PU_PD_RANGE                  5:4
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_PTA_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_PTA_PU_PD_DEFAULT                        _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_PTA_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_PTA_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_PTA_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_PTA_PU_PD_INIT_ENUM                      PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_PTA_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_PTA_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_PTA_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_PTA_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_I2CP_PU_PD_SHIFT                 _MK_SHIFT_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_I2CP_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_B_0_I2CP_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_I2CP_PU_PD_RANGE                 3:2
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_I2CP_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_I2CP_PU_PD_DEFAULT                       _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_I2CP_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_I2CP_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_I2CP_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_I2CP_PU_PD_INIT_ENUM                     PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_I2CP_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_I2CP_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_I2CP_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_I2CP_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_RM_PU_PD_SHIFT                   _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_RM_PU_PD_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_B_0_RM_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_RM_PU_PD_RANGE                   1:0
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_RM_PU_PD_WOFFSET                 0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_RM_PU_PD_DEFAULT                 _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_RM_PU_PD_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_RM_PU_PD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_RM_PU_PD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_RM_PU_PD_INIT_ENUM                       PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_RM_PU_PD_NORMAL                  _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_RM_PU_PD_PULL_DOWN                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_RM_PU_PD_PULL_UP                 _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_RM_PU_PD_RSVD                    _MK_ENUM_CONST(3)
+
+
+// Register APB_MISC_PP_PULLUPDOWN_REG_C_0  
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0                  _MK_ADDR_CONST(0xa8)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SECURE                   0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_WORD_COUNT                       0x1
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_RESET_VAL                        _MK_MASK_CONST(0xaa6655)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_RESET_MASK                       _MK_MASK_CONST(0xf3ffffff)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_READ_MASK                        _MK_MASK_CONST(0xf3ffffff)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_WRITE_MASK                       _MK_MASK_CONST(0xf3ffffff)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2C_PU_PD_SHIFT                 _MK_SHIFT_CONST(30)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2C_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2C_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2C_PU_PD_RANGE                 31:30
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2C_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2C_PU_PD_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2C_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2C_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2C_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2C_PU_PD_INIT_ENUM                     NORMAL
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2C_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2C_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2C_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2C_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2D_PU_PD_SHIFT                 _MK_SHIFT_CONST(28)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2D_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2D_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2D_PU_PD_RANGE                 29:28
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2D_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2D_PU_PD_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2D_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2D_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2D_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2D_PU_PD_INIT_ENUM                     NORMAL
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2D_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2D_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2D_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2D_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_GME_PU_PD_SHIFT                  _MK_SHIFT_CONST(24)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_GME_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_C_0_GME_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_GME_PU_PD_RANGE                  25:24
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_GME_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_GME_PU_PD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_GME_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_GME_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_GME_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_GME_PU_PD_INIT_ENUM                      NORMAL
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_GME_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_GME_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_GME_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_GME_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRRX_PU_PD_SHIFT                 _MK_SHIFT_CONST(22)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRRX_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_C_0_IRRX_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRRX_PU_PD_RANGE                 23:22
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRRX_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRRX_PU_PD_DEFAULT                       _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRRX_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRRX_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRRX_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRRX_PU_PD_INIT_ENUM                     PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRRX_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRRX_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRRX_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRRX_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRTX_PU_PD_SHIFT                 _MK_SHIFT_CONST(20)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRTX_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_C_0_IRTX_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRTX_PU_PD_RANGE                 21:20
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRTX_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRTX_PU_PD_DEFAULT                       _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRTX_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRTX_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRTX_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRTX_PU_PD_INIT_ENUM                     PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRTX_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRTX_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRTX_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRTX_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIH_PU_PD_SHIFT                 _MK_SHIFT_CONST(18)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIH_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIH_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIH_PU_PD_RANGE                 19:18
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIH_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIH_PU_PD_DEFAULT                       _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIH_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIH_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIH_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIH_PU_PD_INIT_ENUM                     PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIH_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIH_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIH_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIH_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIG_PU_PD_SHIFT                 _MK_SHIFT_CONST(16)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIG_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIG_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIG_PU_PD_RANGE                 17:16
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIG_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIG_PU_PD_DEFAULT                       _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIG_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIG_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIG_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIG_PU_PD_INIT_ENUM                     PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIG_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIG_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIG_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIG_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIF_PU_PD_SHIFT                 _MK_SHIFT_CONST(14)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIF_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIF_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIF_PU_PD_RANGE                 15:14
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIF_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIF_PU_PD_DEFAULT                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIF_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIF_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIF_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIF_PU_PD_INIT_ENUM                     PULL_DOWN
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIF_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIF_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIF_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIF_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIE_PU_PD_SHIFT                 _MK_SHIFT_CONST(12)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIE_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIE_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIE_PU_PD_RANGE                 13:12
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIE_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIE_PU_PD_DEFAULT                       _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIE_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIE_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIE_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIE_PU_PD_INIT_ENUM                     PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIE_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIE_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIE_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIE_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPID_PU_PD_SHIFT                 _MK_SHIFT_CONST(10)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPID_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_C_0_SPID_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPID_PU_PD_RANGE                 11:10
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPID_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPID_PU_PD_DEFAULT                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPID_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPID_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPID_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPID_PU_PD_INIT_ENUM                     PULL_DOWN
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPID_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPID_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPID_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPID_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIC_PU_PD_SHIFT                 _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIC_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIC_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIC_PU_PD_RANGE                 9:8
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIC_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIC_PU_PD_DEFAULT                       _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIC_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIC_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIC_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIC_PU_PD_INIT_ENUM                     PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIC_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIC_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIC_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIC_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIB_PU_PD_SHIFT                 _MK_SHIFT_CONST(6)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIB_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIB_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIB_PU_PD_RANGE                 7:6
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIB_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIB_PU_PD_DEFAULT                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIB_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIB_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIB_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIB_PU_PD_INIT_ENUM                     PULL_DOWN
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIB_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIB_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIB_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIB_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIA_PU_PD_SHIFT                 _MK_SHIFT_CONST(4)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIA_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIA_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIA_PU_PD_RANGE                 5:4
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIA_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIA_PU_PD_DEFAULT                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIA_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIA_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIA_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIA_PU_PD_INIT_ENUM                     PULL_DOWN
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIA_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIA_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIA_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIA_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV2_PU_PD_SHIFT                        _MK_SHIFT_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV2_PU_PD_FIELD                        (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV2_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV2_PU_PD_RANGE                        3:2
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV2_PU_PD_WOFFSET                      0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV2_PU_PD_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV2_PU_PD_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV2_PU_PD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV2_PU_PD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV2_PU_PD_INIT_ENUM                    PULL_DOWN
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV2_PU_PD_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV2_PU_PD_PULL_DOWN                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV2_PU_PD_PULL_UP                      _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV2_PU_PD_RSVD                 _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV1_PU_PD_SHIFT                        _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV1_PU_PD_FIELD                        (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV1_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV1_PU_PD_RANGE                        1:0
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV1_PU_PD_WOFFSET                      0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV1_PU_PD_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV1_PU_PD_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV1_PU_PD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV1_PU_PD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV1_PU_PD_INIT_ENUM                    PULL_DOWN
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV1_PU_PD_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV1_PU_PD_PULL_DOWN                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV1_PU_PD_PULL_UP                      _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV1_PU_PD_RSVD                 _MK_ENUM_CONST(3)
+
+
+// Register APB_MISC_PP_PULLUPDOWN_REG_D_0  
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0                  _MK_ADDR_CONST(0xac)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SECURE                   0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_WORD_COUNT                       0x1
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_RESET_VAL                        _MK_MASK_CONST(0xa1a55a8a)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDD_PU_PD_SHIFT                  _MK_SHIFT_CONST(30)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDD_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_D_0_SDD_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDD_PU_PD_RANGE                  31:30
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDD_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDD_PU_PD_DEFAULT                        _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDD_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDD_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDD_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDD_PU_PD_INIT_ENUM                      PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDD_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDD_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDD_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDD_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDC_PU_PD_SHIFT                  _MK_SHIFT_CONST(28)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDC_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_D_0_SDC_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDC_PU_PD_RANGE                  29:28
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDC_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDC_PU_PD_DEFAULT                        _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDC_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDC_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDC_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDC_PU_PD_INIT_ENUM                      PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDC_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDC_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDC_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDC_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_DDRC_PU_PD_SHIFT                 _MK_SHIFT_CONST(26)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_DDRC_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_D_0_DDRC_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_DDRC_PU_PD_RANGE                 27:26
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_DDRC_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_DDRC_PU_PD_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_DDRC_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_DDRC_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_DDRC_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_DDRC_PU_PD_INIT_ENUM                     NORMAL
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_DDRC_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_DDRC_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_DDRC_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_DDRC_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+// LC_P? for : lcd_pclk, lcd_de, lcd_hsycn, lcd_vsync, lcd_m0, lcd_m1, lcd_vp0, hdmi_int
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_CSUS_PU_PD_SHIFT                 _MK_SHIFT_CONST(24)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_CSUS_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_D_0_CSUS_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_CSUS_PU_PD_RANGE                 25:24
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_CSUS_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_CSUS_PU_PD_DEFAULT                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_CSUS_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_CSUS_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_CSUS_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_CSUS_PU_PD_INIT_ENUM                     PULL_DOWN
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_CSUS_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_CSUS_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_CSUS_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_CSUS_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+// LS_P? for : lcd_sdin, lcd_sdout, lcd_wr_, lcd_cs0, lcd_dc0, lcd_sck, lcd_pwr0, lcd_pwr1, lcd_pwr2
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LC_PU_PD_SHIFT                   _MK_SHIFT_CONST(22)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LC_PU_PD_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_D_0_LC_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LC_PU_PD_RANGE                   23:22
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LC_PU_PD_WOFFSET                 0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LC_PU_PD_DEFAULT                 _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LC_PU_PD_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LC_PU_PD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LC_PU_PD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LC_PU_PD_INIT_ENUM                       PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LC_PU_PD_NORMAL                  _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LC_PU_PD_PULL_DOWN                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LC_PU_PD_PULL_UP                 _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LC_PU_PD_RSVD                    _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LS_PU_PD_SHIFT                   _MK_SHIFT_CONST(20)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LS_PU_PD_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_D_0_LS_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LS_PU_PD_RANGE                   21:20
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LS_PU_PD_WOFFSET                 0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LS_PU_PD_DEFAULT                 _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LS_PU_PD_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LS_PU_PD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LS_PU_PD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LS_PU_PD_INIT_ENUM                       PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LS_PU_PD_NORMAL                  _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LS_PU_PD_PULL_DOWN                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LS_PU_PD_PULL_UP                 _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LS_PU_PD_RSVD                    _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD23_22_PU_PD_SHIFT                      _MK_SHIFT_CONST(18)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD23_22_PU_PD_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_D_0_LD23_22_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD23_22_PU_PD_RANGE                      19:18
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD23_22_PU_PD_WOFFSET                    0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD23_22_PU_PD_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD23_22_PU_PD_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD23_22_PU_PD_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD23_22_PU_PD_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD23_22_PU_PD_INIT_ENUM                  PULL_DOWN
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD23_22_PU_PD_NORMAL                     _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD23_22_PU_PD_PULL_DOWN                  _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD23_22_PU_PD_PULL_UP                    _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD23_22_PU_PD_RSVD                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD21_20_PU_PD_SHIFT                      _MK_SHIFT_CONST(16)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD21_20_PU_PD_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_D_0_LD21_20_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD21_20_PU_PD_RANGE                      17:16
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD21_20_PU_PD_WOFFSET                    0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD21_20_PU_PD_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD21_20_PU_PD_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD21_20_PU_PD_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD21_20_PU_PD_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD21_20_PU_PD_INIT_ENUM                  PULL_DOWN
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD21_20_PU_PD_NORMAL                     _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD21_20_PU_PD_PULL_DOWN                  _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD21_20_PU_PD_PULL_UP                    _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD21_20_PU_PD_RSVD                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD19_18_PU_PD_SHIFT                      _MK_SHIFT_CONST(14)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD19_18_PU_PD_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_D_0_LD19_18_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD19_18_PU_PD_RANGE                      15:14
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD19_18_PU_PD_WOFFSET                    0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD19_18_PU_PD_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD19_18_PU_PD_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD19_18_PU_PD_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD19_18_PU_PD_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD19_18_PU_PD_INIT_ENUM                  PULL_DOWN
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD19_18_PU_PD_NORMAL                     _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD19_18_PU_PD_PULL_DOWN                  _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD19_18_PU_PD_PULL_UP                    _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD19_18_PU_PD_RSVD                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD17_0_PU_PD_SHIFT                       _MK_SHIFT_CONST(12)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD17_0_PU_PD_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_D_0_LD17_0_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD17_0_PU_PD_RANGE                       13:12
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD17_0_PU_PD_WOFFSET                     0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD17_0_PU_PD_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD17_0_PU_PD_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD17_0_PU_PD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD17_0_PU_PD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD17_0_PU_PD_INIT_ENUM                   PULL_DOWN
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD17_0_PU_PD_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD17_0_PU_PD_PULL_DOWN                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD17_0_PU_PD_PULL_UP                     _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD17_0_PU_PD_RSVD                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCB_PU_PD_SHIFT                  _MK_SHIFT_CONST(10)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCB_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_D_0_UCB_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCB_PU_PD_RANGE                  11:10
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCB_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCB_PU_PD_DEFAULT                        _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCB_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCB_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCB_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCB_PU_PD_INIT_ENUM                      PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCB_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCB_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCB_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCB_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCA_PU_PD_SHIFT                  _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCA_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_D_0_UCA_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCA_PU_PD_RANGE                  9:8
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCA_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCA_PU_PD_DEFAULT                        _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCA_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCA_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCA_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCA_PU_PD_INIT_ENUM                      PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCA_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCA_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCA_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCA_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAD_PU_PD_SHIFT                  _MK_SHIFT_CONST(6)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAD_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_D_0_UAD_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAD_PU_PD_RANGE                  7:6
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAD_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAD_PU_PD_DEFAULT                        _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAD_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAD_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAD_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAD_PU_PD_INIT_ENUM                      PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAD_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAD_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAD_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAD_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAC_PU_PD_SHIFT                  _MK_SHIFT_CONST(4)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAC_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_D_0_UAC_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAC_PU_PD_RANGE                  5:4
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAC_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAC_PU_PD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAC_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAC_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAC_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAC_PU_PD_INIT_ENUM                      NORMAL
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAC_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAC_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAC_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAC_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAB_PU_PD_SHIFT                  _MK_SHIFT_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAB_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_D_0_UAB_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAB_PU_PD_RANGE                  3:2
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAB_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAB_PU_PD_DEFAULT                        _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAB_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAB_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAB_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAB_PU_PD_INIT_ENUM                      PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAB_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAB_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAB_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAB_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAA_PU_PD_SHIFT                  _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAA_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_D_0_UAA_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAA_PU_PD_RANGE                  1:0
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAA_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAA_PU_PD_DEFAULT                        _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAA_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAA_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAA_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAA_PU_PD_INIT_ENUM                      PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAA_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAA_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAA_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAA_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+
+// Register APB_MISC_PP_PULLUPDOWN_REG_E_0  
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0                  _MK_ADDR_CONST(0xb0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_SECURE                   0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_WORD_COUNT                       0x1
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_RESET_VAL                        _MK_MASK_CONST(0xa008000a)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_OWC_PU_PD_SHIFT                  _MK_SHIFT_CONST(30)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_OWC_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_E_0_OWC_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_OWC_PU_PD_RANGE                  31:30
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_OWC_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_OWC_PU_PD_DEFAULT                        _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_OWC_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_OWC_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_OWC_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_OWC_PU_PD_INIT_ENUM                      PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_OWC_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_OWC_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_OWC_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_OWC_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_DDC_PU_PD_SHIFT                  _MK_SHIFT_CONST(28)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_DDC_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_E_0_DDC_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_DDC_PU_PD_RANGE                  29:28
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_DDC_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_DDC_PU_PD_DEFAULT                        _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_DDC_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_DDC_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_DDC_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_DDC_PU_PD_INIT_ENUM                      PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_DDC_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_DDC_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_DDC_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_DDC_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMD_PU_PD_SHIFT                  _MK_SHIFT_CONST(26)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMD_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_E_0_GMD_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMD_PU_PD_RANGE                  27:26
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMD_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMD_PU_PD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMD_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMD_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMD_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMD_PU_PD_INIT_ENUM                      NORMAL
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMD_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMD_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMD_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMD_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMC_PU_PD_SHIFT                  _MK_SHIFT_CONST(24)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMC_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_E_0_GMC_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMC_PU_PD_RANGE                  25:24
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMC_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMC_PU_PD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMC_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMC_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMC_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMC_PU_PD_INIT_ENUM                      NORMAL
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMC_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMC_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMC_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMC_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMB_PU_PD_SHIFT                  _MK_SHIFT_CONST(22)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMB_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_E_0_GMB_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMB_PU_PD_RANGE                  23:22
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMB_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMB_PU_PD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMB_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMB_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMB_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMB_PU_PD_INIT_ENUM                      NORMAL
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMB_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMB_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMB_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMB_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMA_PU_PD_SHIFT                  _MK_SHIFT_CONST(20)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMA_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_E_0_GMA_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMA_PU_PD_RANGE                  21:20
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMA_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMA_PU_PD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMA_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMA_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMA_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMA_PU_PD_INIT_ENUM                      NORMAL
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMA_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMA_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMA_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMA_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_SDIO1_PU_PD_SHIFT                        _MK_SHIFT_CONST(18)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_SDIO1_PU_PD_FIELD                        (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_E_0_SDIO1_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_SDIO1_PU_PD_RANGE                        19:18
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_SDIO1_PU_PD_WOFFSET                      0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_SDIO1_PU_PD_DEFAULT                      _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_SDIO1_PU_PD_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_SDIO1_PU_PD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_SDIO1_PU_PD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_SDIO1_PU_PD_INIT_ENUM                    PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_SDIO1_PU_PD_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_SDIO1_PU_PD_PULL_DOWN                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_SDIO1_PU_PD_PULL_UP                      _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_SDIO1_PU_PD_RSVD                 _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_UDA_PU_PD_SHIFT                  _MK_SHIFT_CONST(16)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_UDA_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_E_0_UDA_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_UDA_PU_PD_RANGE                  17:16
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_UDA_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_UDA_PU_PD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_UDA_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_UDA_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_UDA_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_UDA_PU_PD_INIT_ENUM                      NORMAL
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_UDA_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_UDA_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_UDA_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_UDA_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_CK32_PU_PD_SHIFT                 _MK_SHIFT_CONST(14)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_CK32_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_E_0_CK32_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_CK32_PU_PD_RANGE                 15:14
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_CK32_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_CK32_PU_PD_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_CK32_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_CK32_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_CK32_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_CK32_PU_PD_INIT_ENUM                     NORMAL
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_CK32_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_CK32_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_CK32_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_CK32_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCE_PU_PD_SHIFT                 _MK_SHIFT_CONST(12)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCE_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCE_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCE_PU_PD_RANGE                 13:12
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCE_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCE_PU_PD_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCE_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCE_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCE_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCE_PU_PD_INIT_ENUM                     NORMAL
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCE_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCE_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCE_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCE_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCD_PU_PD_SHIFT                 _MK_SHIFT_CONST(10)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCD_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCD_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCD_PU_PD_RANGE                 11:10
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCD_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCD_PU_PD_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCD_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCD_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCD_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCD_PU_PD_INIT_ENUM                     NORMAL
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCD_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCD_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCD_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCD_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCC_PU_PD_SHIFT                 _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCC_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCC_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCC_PU_PD_RANGE                 9:8
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCC_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCC_PU_PD_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCC_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCC_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCC_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCC_PU_PD_INIT_ENUM                     NORMAL
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCC_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCC_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCC_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCC_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCB_PU_PD_SHIFT                 _MK_SHIFT_CONST(6)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCB_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCB_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCB_PU_PD_RANGE                 7:6
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCB_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCB_PU_PD_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCB_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCB_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCB_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCB_PU_PD_INIT_ENUM                     NORMAL
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCB_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCB_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCB_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCB_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCA_PU_PD_SHIFT                 _MK_SHIFT_CONST(4)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCA_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCA_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCA_PU_PD_RANGE                 5:4
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCA_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCA_PU_PD_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCA_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCA_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCA_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCA_PU_PD_INIT_ENUM                     NORMAL
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCA_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCA_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCA_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCA_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCE_PU_PD_SHIFT                 _MK_SHIFT_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCE_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCE_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCE_PU_PD_RANGE                 3:2
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCE_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCE_PU_PD_DEFAULT                       _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCE_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCE_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCE_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCE_PU_PD_INIT_ENUM                     PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCE_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCE_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCE_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCE_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCF_PU_PD_SHIFT                 _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCF_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCF_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCF_PU_PD_RANGE                 1:0
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCF_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCF_PU_PD_DEFAULT                       _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCF_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCF_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCF_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCF_PU_PD_INIT_ENUM                     PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCF_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCF_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCF_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCF_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+
+// Register APB_MISC_ASYNC_COREPWRCONFIG_0  
+#define APB_MISC_ASYNC_COREPWRCONFIG_0                  _MK_ADDR_CONST(0x400)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_SECURE                   0x0
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_WORD_COUNT                       0x1
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_RESET_MASK                       _MK_MASK_CONST(0x7)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_READ_MASK                        _MK_MASK_CONST(0x7)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_WRITE_MASK                       _MK_MASK_CONST(0x7)
+// Power is on in TDA/TDB partitions
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_TD_COREPWR_EN_SHIFT                      _MK_SHIFT_CONST(0)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_TD_COREPWR_EN_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_COREPWRCONFIG_0_TD_COREPWR_EN_SHIFT)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_TD_COREPWR_EN_RANGE                      0:0
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_TD_COREPWR_EN_WOFFSET                    0x0
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_TD_COREPWR_EN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_TD_COREPWR_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_TD_COREPWR_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_TD_COREPWR_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_TD_COREPWR_EN_INIT_ENUM                  DISABLE
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_TD_COREPWR_EN_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_TD_COREPWR_EN_ENABLE                     _MK_ENUM_CONST(1)
+
+// Power is on in VE/MPE partitions
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_VE_COREPWR_EN_SHIFT                      _MK_SHIFT_CONST(1)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_VE_COREPWR_EN_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_COREPWRCONFIG_0_VE_COREPWR_EN_SHIFT)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_VE_COREPWR_EN_RANGE                      1:1
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_VE_COREPWR_EN_WOFFSET                    0x0
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_VE_COREPWR_EN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_VE_COREPWR_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_VE_COREPWR_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_VE_COREPWR_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_VE_COREPWR_EN_INIT_ENUM                  DISABLE
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_VE_COREPWR_EN_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_VE_COREPWR_EN_ENABLE                     _MK_ENUM_CONST(1)
+
+// Power is on in CPU partition
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_CPU_COREPWR_EN_SHIFT                     _MK_SHIFT_CONST(2)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_CPU_COREPWR_EN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_COREPWRCONFIG_0_CPU_COREPWR_EN_SHIFT)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_CPU_COREPWR_EN_RANGE                     2:2
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_CPU_COREPWR_EN_WOFFSET                   0x0
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_CPU_COREPWR_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_CPU_COREPWR_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_CPU_COREPWR_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_CPU_COREPWR_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_CPU_COREPWR_EN_INIT_ENUM                 DISABLE
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_CPU_COREPWR_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_CPU_COREPWR_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+
+// Reserved address 1028 [0x404] 
+
+// Reserved address 1032 [0x408] 
+
+// Reserved address 1036 [0x40c] 
+
+// Register APB_MISC_ASYNC_EMCPADEN_0  
+#define APB_MISC_ASYNC_EMCPADEN_0                       _MK_ADDR_CONST(0x410)
+#define APB_MISC_ASYNC_EMCPADEN_0_SECURE                        0x0
+#define APB_MISC_ASYNC_EMCPADEN_0_WORD_COUNT                    0x1
+#define APB_MISC_ASYNC_EMCPADEN_0_RESET_VAL                     _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_EMCPADEN_0_RESET_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_EMCPADEN_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_EMCPADEN_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_EMCPADEN_0_READ_MASK                     _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_EMCPADEN_0_WRITE_MASK                    _MK_MASK_CONST(0x3)
+// outputs enable for EMC pads
+#define APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_OUTPUT_EN_SHIFT                       _MK_SHIFT_CONST(0)
+#define APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_OUTPUT_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_OUTPUT_EN_SHIFT)
+#define APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_OUTPUT_EN_RANGE                       0:0
+#define APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_OUTPUT_EN_WOFFSET                     0x0
+#define APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_OUTPUT_EN_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_OUTPUT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_OUTPUT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_OUTPUT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_OUTPUT_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_OUTPUT_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// inputs enable for EMC pads
+#define APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_INPUT_EN_SHIFT                        _MK_SHIFT_CONST(1)
+#define APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_INPUT_EN_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_INPUT_EN_SHIFT)
+#define APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_INPUT_EN_RANGE                        1:1
+#define APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_INPUT_EN_WOFFSET                      0x0
+#define APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_INPUT_EN_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_INPUT_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_INPUT_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_INPUT_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_INPUT_EN_DISABLE                      _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_INPUT_EN_ENABLE                       _MK_ENUM_CONST(1)
+
+
+// Reserved address 1044 [0x414] 
+
+// Reserved address 1048 [0x418] 
+
+// Reserved address 1052 [0x41c] 
+
+// Reserved address 1056 [0x420] 
+
+// Reserved address 1060 [0x424] 
+
+// Reserved address 1064 [0x428] 
+
+// Register APB_MISC_ASYNC_VCLKCTRL_0  
+#define APB_MISC_ASYNC_VCLKCTRL_0                       _MK_ADDR_CONST(0x42c)
+#define APB_MISC_ASYNC_VCLKCTRL_0_SECURE                        0x0
+#define APB_MISC_ASYNC_VCLKCTRL_0_WORD_COUNT                    0x1
+#define APB_MISC_ASYNC_VCLKCTRL_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_VCLKCTRL_0_RESET_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_VCLKCTRL_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_VCLKCTRL_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_VCLKCTRL_0_READ_MASK                     _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_VCLKCTRL_0_WRITE_MASK                    _MK_MASK_CONST(0x3)
+// VCLK input enable
+#define APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_IE_SHIFT                     _MK_SHIFT_CONST(0)
+#define APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_IE_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_IE_SHIFT)
+#define APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_IE_RANGE                     0:0
+#define APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_IE_WOFFSET                   0x0
+#define APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_IE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_IE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_IE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_IE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_IE_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_IE_ENABLE                    _MK_ENUM_CONST(1)
+
+// VCLK invert enable
+#define APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_INVERSION_SHIFT                      _MK_SHIFT_CONST(1)
+#define APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_INVERSION_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_INVERSION_SHIFT)
+#define APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_INVERSION_RANGE                      1:1
+#define APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_INVERSION_WOFFSET                    0x0
+#define APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_INVERSION_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_INVERSION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_INVERSION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_INVERSION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_INVERSION_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_INVERSION_ENABLE                     _MK_ENUM_CONST(1)
+
+
+// Reserved address 1072 [0x430] 
+
+// Reserved address 1076 [0x434] 
+
+// Register APB_MISC_ASYNC_TVDACVHSYNCCTRL_0  
+#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0                        _MK_ADDR_CONST(0x438)
+#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_SECURE                         0x0
+#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_WORD_COUNT                     0x1
+#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_RESET_MASK                     _MK_MASK_CONST(0xf)
+#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_READ_MASK                      _MK_MASK_CONST(0xf)
+#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_WRITE_MASK                     _MK_MASK_CONST(0xf)
+#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_TVDAC_HSYNCDLY_SHIFT                   _MK_SHIFT_CONST(0)
+#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_TVDAC_HSYNCDLY_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_TVDAC_HSYNCDLY_SHIFT)
+#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_TVDAC_HSYNCDLY_RANGE                   1:0
+#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_TVDAC_HSYNCDLY_WOFFSET                 0x0
+#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_TVDAC_HSYNCDLY_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_TVDAC_HSYNCDLY_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_TVDAC_HSYNCDLY_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_TVDAC_HSYNCDLY_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_TVDAC_VSYNCDLY_SHIFT                   _MK_SHIFT_CONST(2)
+#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_TVDAC_VSYNCDLY_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_TVDAC_VSYNCDLY_SHIFT)
+#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_TVDAC_VSYNCDLY_RANGE                   3:2
+#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_TVDAC_VSYNCDLY_WOFFSET                 0x0
+#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_TVDAC_VSYNCDLY_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_TVDAC_VSYNCDLY_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_TVDAC_VSYNCDLY_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_TVDAC_VSYNCDLY_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_ASYNC_TVDACCNTL_0  
+#define APB_MISC_ASYNC_TVDACCNTL_0                      _MK_ADDR_CONST(0x43c)
+#define APB_MISC_ASYNC_TVDACCNTL_0_SECURE                       0x0
+#define APB_MISC_ASYNC_TVDACCNTL_0_WORD_COUNT                   0x1
+#define APB_MISC_ASYNC_TVDACCNTL_0_RESET_VAL                    _MK_MASK_CONST(0x83b)
+#define APB_MISC_ASYNC_TVDACCNTL_0_RESET_MASK                   _MK_MASK_CONST(0x1effffff)
+#define APB_MISC_ASYNC_TVDACCNTL_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_READ_MASK                    _MK_MASK_CONST(0x1effffff)
+#define APB_MISC_ASYNC_TVDACCNTL_0_WRITE_MASK                   _MK_MASK_CONST(0x1effffff)
+// Power down everything including the band-gap
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_IDDQ_SHIFT                       _MK_SHIFT_CONST(0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_IDDQ_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_TVDACCNTL_0_DAC_IDDQ_SHIFT)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_IDDQ_RANGE                       0:0
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_IDDQ_WOFFSET                     0x0
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_IDDQ_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_IDDQ_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_IDDQ_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_IDDQ_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_IDDQ_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_IDDQ_ENABLE                      _MK_ENUM_CONST(1)
+
+// Power down everything except the band-gap
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_POWERDOWN_SHIFT                  _MK_SHIFT_CONST(1)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_POWERDOWN_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_TVDACCNTL_0_DAC_POWERDOWN_SHIFT)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_POWERDOWN_RANGE                  1:1
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_POWERDOWN_WOFFSET                        0x0
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_POWERDOWN_DEFAULT                        _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_POWERDOWN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_POWERDOWN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_POWERDOWN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_POWERDOWN_DISABLE                        _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_POWERDOWN_ENABLE                 _MK_ENUM_CONST(1)
+
+// Power down everything including the band-gap
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_DETECT_EN_SHIFT                  _MK_SHIFT_CONST(2)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_DETECT_EN_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_TVDACCNTL_0_DAC_DETECT_EN_SHIFT)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_DETECT_EN_RANGE                  2:2
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_DETECT_EN_WOFFSET                        0x0
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_DETECT_EN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_DETECT_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_DETECT_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_DETECT_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_DETECT_EN_DISABLE                        _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_DETECT_EN_ENABLE                 _MK_ENUM_CONST(1)
+
+// Low power (sleep) mode. SHut down OUTR output
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPR_SHIFT                     _MK_SHIFT_CONST(3)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPR_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPR_SHIFT)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPR_RANGE                     3:3
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPR_WOFFSET                   0x0
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPR_DEFAULT                   _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPR_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPR_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPR_ENABLE                    _MK_ENUM_CONST(1)
+
+// Low power (sleep) mode. SHut down OUTG output
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPG_SHIFT                     _MK_SHIFT_CONST(4)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPG_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPG_SHIFT)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPG_RANGE                     4:4
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPG_WOFFSET                   0x0
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPG_DEFAULT                   _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPG_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPG_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPG_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPG_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPG_ENABLE                    _MK_ENUM_CONST(1)
+
+// Low power (sleep) mode. SHut down OUTB output
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPB_SHIFT                     _MK_SHIFT_CONST(5)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPB_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPB_SHIFT)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPB_RANGE                     5:5
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPB_WOFFSET                   0x0
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPB_DEFAULT                   _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPB_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPB_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPB_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPB_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPB_ENABLE                    _MK_ENUM_CONST(1)
+
+// Adjust threshold voltage of comparator inside DAC
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMP_TH_SHIFT                    _MK_SHIFT_CONST(6)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMP_TH_FIELD                    (_MK_MASK_CONST(0x3) << APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMP_TH_SHIFT)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMP_TH_RANGE                    7:6
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMP_TH_WOFFSET                  0x0
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMP_TH_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMP_TH_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMP_TH_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMP_TH_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Turn bandgap averaging on/off
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_AVG_ON_SHIFT                        _MK_SHIFT_CONST(8)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_AVG_ON_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_AVG_ON_SHIFT)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_AVG_ON_RANGE                        8:8
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_AVG_ON_WOFFSET                      0x0
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_AVG_ON_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_AVG_ON_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_AVG_ON_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_AVG_ON_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_AVG_ON_DISABLE                      _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_AVG_ON_ENABLE                       _MK_ENUM_CONST(1)
+
+// To adjust temp coeff
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_CURVE_SHIFT                 _MK_SHIFT_CONST(9)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_CURVE_FIELD                 (_MK_MASK_CONST(0x7) << APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_CURVE_SHIFT)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_CURVE_RANGE                 11:9
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_CURVE_WOFFSET                       0x0
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_CURVE_DEFAULT                       _MK_MASK_CONST(0x4)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_CURVE_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_CURVE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_CURVE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Control bits for bandgap
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_CNTL_SHIFT                  _MK_SHIFT_CONST(12)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_CNTL_FIELD                  (_MK_MASK_CONST(0xf) << APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_CNTL_SHIFT)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_CNTL_RANGE                  15:12
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_CNTL_WOFFSET                        0x0
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_CNTL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_CNTL_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_CNTL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_CNTL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// For debugging. Selects internal analog output to be sent out of VREF pin
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_ATEST_SHIFT                      _MK_SHIFT_CONST(16)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_ATEST_FIELD                      (_MK_MASK_CONST(0x7) << APB_MISC_ASYNC_TVDACCNTL_0_DAC_ATEST_SHIFT)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_ATEST_RANGE                      18:16
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_ATEST_WOFFSET                    0x0
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_ATEST_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_ATEST_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_ATEST_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_ATEST_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Reserved for additional control
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_CNTL_SHIFT                       _MK_SHIFT_CONST(19)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_CNTL_FIELD                       (_MK_MASK_CONST(0x1f) << APB_MISC_ASYNC_TVDACCNTL_0_DAC_CNTL_SHIFT)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_CNTL_RANGE                       23:19
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_CNTL_WOFFSET                     0x0
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_CNTL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_CNTL_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_CNTL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_CNTL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Enable COMPOUTR output
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPR_EN_SHIFT                   _MK_SHIFT_CONST(25)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPR_EN_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPR_EN_SHIFT)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPR_EN_RANGE                   25:25
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPR_EN_WOFFSET                 0x0
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPR_EN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPR_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPR_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPR_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPR_EN_DISABLE                 _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPR_EN_ENABLE                  _MK_ENUM_CONST(1)
+
+// Enable COMPOUTG output
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPG_EN_SHIFT                   _MK_SHIFT_CONST(26)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPG_EN_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPG_EN_SHIFT)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPG_EN_RANGE                   26:26
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPG_EN_WOFFSET                 0x0
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPG_EN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPG_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPG_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPG_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPG_EN_DISABLE                 _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPG_EN_ENABLE                  _MK_ENUM_CONST(1)
+
+// Enable COMPOUTB output
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPB_EN_SHIFT                   _MK_SHIFT_CONST(27)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPB_EN_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPB_EN_SHIFT)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPB_EN_RANGE                   27:27
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPB_EN_WOFFSET                 0x0
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPB_EN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPB_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPB_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPB_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPB_EN_DISABLE                 _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPB_EN_ENABLE                  _MK_ENUM_CONST(1)
+
+// Indicate load status
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_PLUG_OK_SHIFT                    _MK_SHIFT_CONST(28)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_PLUG_OK_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_TVDACCNTL_0_DAC_PLUG_OK_SHIFT)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_PLUG_OK_RANGE                    28:28
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_PLUG_OK_WOFFSET                  0x0
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_PLUG_OK_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_PLUG_OK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_PLUG_OK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_PLUG_OK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_PLUG_OK_UNLOADED                 _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_PLUG_OK_LOADED                   _MK_ENUM_CONST(1)
+
+
+// Register APB_MISC_ASYNC_TVDACSTATUS_0  
+#define APB_MISC_ASYNC_TVDACSTATUS_0                    _MK_ADDR_CONST(0x440)
+#define APB_MISC_ASYNC_TVDACSTATUS_0_SECURE                     0x0
+#define APB_MISC_ASYNC_TVDACSTATUS_0_WORD_COUNT                         0x1
+#define APB_MISC_ASYNC_TVDACSTATUS_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACSTATUS_0_RESET_MASK                         _MK_MASK_CONST(0x7)
+#define APB_MISC_ASYNC_TVDACSTATUS_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACSTATUS_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACSTATUS_0_READ_MASK                  _MK_MASK_CONST(0x7)
+#define APB_MISC_ASYNC_TVDACSTATUS_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
+// Channel R comparator output for auto-detect
+// 0 = COMPINR > threshold
+// 1 = COMPINR < threshold, or when POWERDOWN==1
+// comparison threshold = 0.325V
+#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTR_SHIFT                 _MK_SHIFT_CONST(0)
+#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTR_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTR_SHIFT)
+#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTR_RANGE                 0:0
+#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTR_WOFFSET                       0x0
+#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTR_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Channel G comparator output for auto-detect
+// 0 = COMPING > threshold
+// 1 = COMPING < threshold, or when POWERDOWN==1
+// comparison threshold = 0.325V
+#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTG_SHIFT                 _MK_SHIFT_CONST(1)
+#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTG_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTG_SHIFT)
+#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTG_RANGE                 1:1
+#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTG_WOFFSET                       0x0
+#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTG_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTG_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTG_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTG_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Channel B comparator output for auto-detect
+// 0 = COMPINB > threshold
+// 1 = COMPINB < threshold, or when POWERDOWN==1
+// comparison threshold = 0.325V
+#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTB_SHIFT                 _MK_SHIFT_CONST(2)
+#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTB_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTB_SHIFT)
+#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTB_RANGE                 2:2
+#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTB_WOFFSET                       0x0
+#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTB_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTB_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTB_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTB_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_ASYNC_TVDACDINCONFIG_0  
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0                 _MK_ADDR_CONST(0x444)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_SECURE                  0x0
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_WORD_COUNT                      0x1
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_RESET_VAL                       _MK_MASK_CONST(0x2)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_RESET_MASK                      _MK_MASK_CONST(0xffffd37)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_READ_MASK                       _MK_MASK_CONST(0xffffd37)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_WRITE_MASK                      _MK_MASK_CONST(0xffffd37)
+// Data Input FIFO threshold
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_FIFO_TH_SHIFT                       _MK_SHIFT_CONST(0)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_FIFO_TH_FIELD                       (_MK_MASK_CONST(0x7) << APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_FIFO_TH_SHIFT)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_FIFO_TH_RANGE                       2:0
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_FIFO_TH_WOFFSET                     0x0
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_FIFO_TH_DEFAULT                     _MK_MASK_CONST(0x2)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_FIFO_TH_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_FIFO_TH_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_FIFO_TH_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// INPUT source for TVDAC
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_SOURCE_SHIFT                        _MK_SHIFT_CONST(4)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_SOURCE_FIELD                        (_MK_MASK_CONST(0x3) << APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_SOURCE_SHIFT)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_SOURCE_RANGE                        5:4
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_SOURCE_WOFFSET                      0x0
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_SOURCE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_SOURCE_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_SOURCE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_SOURCE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_SOURCE_TVDAC_OFF                    _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_SOURCE_TVO                  _MK_ENUM_CONST(1)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_SOURCE_DISPLAY                      _MK_ENUM_CONST(2)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_SOURCE_DISPLAYB                     _MK_ENUM_CONST(3)
+
+// Override DAC DIN inputs
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_DIN_ORIDE_EN_SHIFT                  _MK_SHIFT_CONST(8)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_DIN_ORIDE_EN_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_DIN_ORIDE_EN_SHIFT)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_DIN_ORIDE_EN_RANGE                  8:8
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_DIN_ORIDE_EN_WOFFSET                        0x0
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_DIN_ORIDE_EN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_DIN_ORIDE_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_DIN_ORIDE_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_DIN_ORIDE_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_DIN_ORIDE_EN_DISABLE                        _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_DIN_ORIDE_EN_ENABLE                 _MK_ENUM_CONST(1)
+
+// DIN override
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_DIN_ORIDE_SHIFT                     _MK_SHIFT_CONST(10)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_DIN_ORIDE_FIELD                     (_MK_MASK_CONST(0x3ff) << APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_DIN_ORIDE_SHIFT)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_DIN_ORIDE_RANGE                     19:10
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_DIN_ORIDE_WOFFSET                   0x0
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_DIN_ORIDE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_DIN_ORIDE_DEFAULT_MASK                      _MK_MASK_CONST(0x3ff)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_DIN_ORIDE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_DIN_ORIDE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// AMPIN
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_AMPIN_SHIFT                 _MK_SHIFT_CONST(20)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_AMPIN_FIELD                 (_MK_MASK_CONST(0xff) << APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_AMPIN_SHIFT)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_AMPIN_RANGE                 27:20
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_AMPIN_WOFFSET                       0x0
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_AMPIN_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_AMPIN_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_AMPIN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_AMPIN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_ASYNC_INT_STATUS_0  // Interrupt Status
+//  This reflects status of all pending
+//  interrupts which is valid as long as
+//  the interrupt is not cleared even if the
+//  interrupt is masked. A pending interrupt
+//  can be cleared by writing a '1' to this
+//  the corresponding interrupt status bit
+//  in this register.
+//        0       rt  HGP0_INT_STATUS          // HGP0 Interrupt Status
+//                                             //  (this is cleared on write)
+//                                             //   0= interrupt not pending
+//                                             //   1= interrupt pending
+//        1       rt  HGP1_INT_STATUS          // HGP1 Interrupt Status
+//                                             //  (this is cleared on write)
+//                                             //   0= interrupt not pending
+//                                            //   1= interrupt pending
+//      2       rt  HGP2_INT_STATUS          // HGP2 Interrupt Status
+//                                          //  (this is cleared on write)
+//                                           //   0= interrupt not pending
+//                                           //   1= interrupt pending
+//      4       rt  HGP4_INT_STATUS          // HGP4 Interrupt Status
+//                                           //  (this is cleared on write)
+//                                           //   0= interrupt not pending
+//                                           //   1= interrupt pending
+//      5       rt  HGP5_INT_STATUS          // HGP5 Interrupt Status
+//                                           //  (this is cleared on write)
+//                                           //   0= interrupt not pending
+//                                           //   1= interrupt pending
+//      6       rt  HGP6_INT_STATUS          // HGP6 Interrupt Status
+//                                           //  (this is cleared on write)
+//                                           //   0= interrupt not pending
+//                                           //   1= interrupt pending
+#define APB_MISC_ASYNC_INT_STATUS_0                     _MK_ADDR_CONST(0x448)
+#define APB_MISC_ASYNC_INT_STATUS_0_SECURE                      0x0
+#define APB_MISC_ASYNC_INT_STATUS_0_WORD_COUNT                  0x1
+#define APB_MISC_ASYNC_INT_STATUS_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_STATUS_0_RESET_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_STATUS_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_STATUS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_STATUS_0_READ_MASK                   _MK_MASK_CONST(0x1f80)
+#define APB_MISC_ASYNC_INT_STATUS_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+// HGP7 Interrupt Status
+//  (this is cleared on write)
+//   0= interrupt not pending
+//   1= interrupt pending
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP7_INT_STATUS_SHIFT                       _MK_SHIFT_CONST(7)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP7_INT_STATUS_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_STATUS_0_HGP7_INT_STATUS_SHIFT)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP7_INT_STATUS_RANGE                       7:7
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP7_INT_STATUS_WOFFSET                     0x0
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP7_INT_STATUS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP7_INT_STATUS_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP7_INT_STATUS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP7_INT_STATUS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// HGP8 Interrupt Status
+//  (this is cleared on write)
+//   0= interrupt not pending
+//   1= interrupt pending
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP8_INT_STATUS_SHIFT                       _MK_SHIFT_CONST(8)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP8_INT_STATUS_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_STATUS_0_HGP8_INT_STATUS_SHIFT)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP8_INT_STATUS_RANGE                       8:8
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP8_INT_STATUS_WOFFSET                     0x0
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP8_INT_STATUS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP8_INT_STATUS_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP8_INT_STATUS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP8_INT_STATUS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// HGP9 Interrupt Status
+//  (this is cleared on write)
+//   0= interrupt not pending
+//   1= interrupt pending
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP9_INT_STATUS_SHIFT                       _MK_SHIFT_CONST(9)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP9_INT_STATUS_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_STATUS_0_HGP9_INT_STATUS_SHIFT)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP9_INT_STATUS_RANGE                       9:9
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP9_INT_STATUS_WOFFSET                     0x0
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP9_INT_STATUS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP9_INT_STATUS_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP9_INT_STATUS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP9_INT_STATUS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// HGP10 Interrupt Status
+//  (this is cleared on write)
+//   0= interrupt not pending
+//   1= interrupt pending
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP10_INT_STATUS_SHIFT                      _MK_SHIFT_CONST(10)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP10_INT_STATUS_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_STATUS_0_HGP10_INT_STATUS_SHIFT)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP10_INT_STATUS_RANGE                      10:10
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP10_INT_STATUS_WOFFSET                    0x0
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP10_INT_STATUS_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP10_INT_STATUS_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP10_INT_STATUS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP10_INT_STATUS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// HGP11 Interrupt Status
+//  (this is cleared on write)
+//   0= interrupt not pending
+//   1= interrupt pending
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP11_INT_STATUS_SHIFT                      _MK_SHIFT_CONST(11)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP11_INT_STATUS_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_STATUS_0_HGP11_INT_STATUS_SHIFT)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP11_INT_STATUS_RANGE                      11:11
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP11_INT_STATUS_WOFFSET                    0x0
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP11_INT_STATUS_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP11_INT_STATUS_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP11_INT_STATUS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP11_INT_STATUS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// HGP12 Interrupt Status
+//  (this is cleared on write)
+//   0= interrupt not pending
+//   1= interrupt pending
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP12_INT_STATUS_SHIFT                      _MK_SHIFT_CONST(12)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP12_INT_STATUS_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_STATUS_0_HGP12_INT_STATUS_SHIFT)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP12_INT_STATUS_RANGE                      12:12
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP12_INT_STATUS_WOFFSET                    0x0
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP12_INT_STATUS_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP12_INT_STATUS_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP12_INT_STATUS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP12_INT_STATUS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_ASYNC_INT_MASK_0  // Interrupt Mask
+// Setting bits in this register masked the
+//  corresponding interrupt but does not
+//  clear a pending interrupt and does not
+//  prevent a pending interrupt to be generated.
+//  Masking an interrupt also does not clear
+//  a pending interrupt status and does not
+//  a pending interrupt status to be generated.
+//      0       rw  HGP0_INT_MASK  i=0x0     // HGP0 Interrupt Mask
+//          enum ( MASKED, NOTMASKED )       //   0= interrupt masked
+//                                           //   1= interrupt not masked
+//      1       rw  HGP1_INT_MASK  i=0x0     // HGP1 Interrupt Mask
+//          enum ( MASKED, NOTMASKED )       //   0= interrupt masked
+//                                           //   1= interrupt not masked
+//      2       rw  HGP2_INT_MASK  i=0x0     // HGP2 Interrupt Mask
+//          enum ( MASKED, NOTMASKED )       //   0= interrupt masked
+//                                           //   1= interrupt not masked
+//      4       rw  HGP4_INT_MASK  i=0x0     // HGP4 Interrupt Mask
+//          enum ( MASKED, NOTMASKED )       //   0= interrupt masked
+//                                           //   1= interrupt not masked
+//      5       rw  HGP5_INT_MASK  i=0x0     // HGP5 Interrupt Mask
+//          enum ( MASKED, NOTMASKED )       //   0= interrupt masked
+//                                           //   1= interrupt not masked
+//      6       rw  HGP6_INT_MASK  i=0x0     // HGP6 Interrupt Mask
+//          enum ( MASKED, NOTMASKED )       //   0= interrupt masked
+//                                           //   1= interrupt not masked
+#define APB_MISC_ASYNC_INT_MASK_0                       _MK_ADDR_CONST(0x44c)
+#define APB_MISC_ASYNC_INT_MASK_0_SECURE                        0x0
+#define APB_MISC_ASYNC_INT_MASK_0_WORD_COUNT                    0x1
+#define APB_MISC_ASYNC_INT_MASK_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_MASK_0_RESET_MASK                    _MK_MASK_CONST(0x1f80)
+#define APB_MISC_ASYNC_INT_MASK_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_MASK_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_MASK_0_READ_MASK                     _MK_MASK_CONST(0x1f80)
+#define APB_MISC_ASYNC_INT_MASK_0_WRITE_MASK                    _MK_MASK_CONST(0x1f80)
+// HGP7 Interrupt Mask   0= interrupt masked
+//   1= interrupt not masked
+#define APB_MISC_ASYNC_INT_MASK_0_HGP7_INT_MASK_SHIFT                   _MK_SHIFT_CONST(7)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP7_INT_MASK_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_MASK_0_HGP7_INT_MASK_SHIFT)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP7_INT_MASK_RANGE                   7:7
+#define APB_MISC_ASYNC_INT_MASK_0_HGP7_INT_MASK_WOFFSET                 0x0
+#define APB_MISC_ASYNC_INT_MASK_0_HGP7_INT_MASK_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP7_INT_MASK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP7_INT_MASK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP7_INT_MASK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP7_INT_MASK_MASKED                  _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP7_INT_MASK_NOTMASKED                       _MK_ENUM_CONST(1)
+
+// HGP8 Interrupt Mask   0= interrupt masked
+//   1= interrupt not masked
+#define APB_MISC_ASYNC_INT_MASK_0_HGP8_INT_MASK_SHIFT                   _MK_SHIFT_CONST(8)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP8_INT_MASK_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_MASK_0_HGP8_INT_MASK_SHIFT)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP8_INT_MASK_RANGE                   8:8
+#define APB_MISC_ASYNC_INT_MASK_0_HGP8_INT_MASK_WOFFSET                 0x0
+#define APB_MISC_ASYNC_INT_MASK_0_HGP8_INT_MASK_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP8_INT_MASK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP8_INT_MASK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP8_INT_MASK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP8_INT_MASK_MASKED                  _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP8_INT_MASK_NOTMASKED                       _MK_ENUM_CONST(1)
+
+// HGP9 Interrupt Mask   0= interrupt masked
+//   1= interrupt not masked
+#define APB_MISC_ASYNC_INT_MASK_0_HGP9_INT_MASK_SHIFT                   _MK_SHIFT_CONST(9)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP9_INT_MASK_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_MASK_0_HGP9_INT_MASK_SHIFT)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP9_INT_MASK_RANGE                   9:9
+#define APB_MISC_ASYNC_INT_MASK_0_HGP9_INT_MASK_WOFFSET                 0x0
+#define APB_MISC_ASYNC_INT_MASK_0_HGP9_INT_MASK_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP9_INT_MASK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP9_INT_MASK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP9_INT_MASK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP9_INT_MASK_MASKED                  _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP9_INT_MASK_NOTMASKED                       _MK_ENUM_CONST(1)
+
+// HGP10 Interrupt Mask   0= interrupt masked
+//   1= interrupt not masked
+#define APB_MISC_ASYNC_INT_MASK_0_HGP10_INT_MASK_SHIFT                  _MK_SHIFT_CONST(10)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP10_INT_MASK_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_MASK_0_HGP10_INT_MASK_SHIFT)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP10_INT_MASK_RANGE                  10:10
+#define APB_MISC_ASYNC_INT_MASK_0_HGP10_INT_MASK_WOFFSET                        0x0
+#define APB_MISC_ASYNC_INT_MASK_0_HGP10_INT_MASK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP10_INT_MASK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP10_INT_MASK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP10_INT_MASK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP10_INT_MASK_MASKED                 _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP10_INT_MASK_NOTMASKED                      _MK_ENUM_CONST(1)
+
+// HGP11 Interrupt Mask   0= interrupt masked
+//   1= interrupt not masked
+#define APB_MISC_ASYNC_INT_MASK_0_HGP11_INT_MASK_SHIFT                  _MK_SHIFT_CONST(11)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP11_INT_MASK_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_MASK_0_HGP11_INT_MASK_SHIFT)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP11_INT_MASK_RANGE                  11:11
+#define APB_MISC_ASYNC_INT_MASK_0_HGP11_INT_MASK_WOFFSET                        0x0
+#define APB_MISC_ASYNC_INT_MASK_0_HGP11_INT_MASK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP11_INT_MASK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP11_INT_MASK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP11_INT_MASK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP11_INT_MASK_MASKED                 _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP11_INT_MASK_NOTMASKED                      _MK_ENUM_CONST(1)
+
+// HGP12 Interrupt Mask   0= interrupt masked
+//   1= interrupt not masked
+#define APB_MISC_ASYNC_INT_MASK_0_HGP12_INT_MASK_SHIFT                  _MK_SHIFT_CONST(12)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP12_INT_MASK_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_MASK_0_HGP12_INT_MASK_SHIFT)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP12_INT_MASK_RANGE                  12:12
+#define APB_MISC_ASYNC_INT_MASK_0_HGP12_INT_MASK_WOFFSET                        0x0
+#define APB_MISC_ASYNC_INT_MASK_0_HGP12_INT_MASK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP12_INT_MASK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP12_INT_MASK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP12_INT_MASK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP12_INT_MASK_MASKED                 _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP12_INT_MASK_NOTMASKED                      _MK_ENUM_CONST(1)
+
+
+// Register APB_MISC_ASYNC_INT_POLARITY_0  // Interrupt Polarity
+//  These bits specify whether a pending interrupt 
+//  is generated on falling edge or on rising edge 
+//  of the corresponding input signal/event.
+//        0       rw  HGP0_INT_POLARITY  i=0x0  // HGP0 Interrupt Polarity
+//      enum ( LOW, HIGH )                    //   0= falling edge interrupt
+//                                            //   1= rising edge interrupt
+//      1       rw  HGP1_INT_POLARITY  i=0x0  // HGP1 Interrupt Polarity
+//      enum ( LOW, HIGH )                    //   0= falling edge interrupt
+//                                            //   1= rising edge interrupt
+//      2       rw  HGP2_INT_POLARITY  i=0x0  // HGP2 Interrupt Polarity
+//      enum ( LOW, HIGH )                    //   0= falling edge interrupt
+//                                            //   1= rising edge interrupt
+//      4       rw  HGP4_INT_POLARITY  i=0x0  // HGP4 Interrupt Polarity
+//      enum ( LOW, HIGH )                    //   0= falling edge interrupt
+//                                            //   1= rising edge interrupt
+//      5       rw  HGP5_INT_POLARITY  i=0x0  // HGP5 Interrupt Polarity
+//      enum ( LOW, HIGH )                    //   0= falling edge interrupt
+//                                            //   1= rising edge interrupt
+//      6       rw  HGP6_INT_POLARITY  i=0x0  // HGP6 Interrupt Polarity
+//      enum ( LOW, HIGH )                    //   0= falling edge interrupt
+//                                            //   1= rising edge interrupt
+#define APB_MISC_ASYNC_INT_POLARITY_0                   _MK_ADDR_CONST(0x450)
+#define APB_MISC_ASYNC_INT_POLARITY_0_SECURE                    0x0
+#define APB_MISC_ASYNC_INT_POLARITY_0_WORD_COUNT                        0x1
+#define APB_MISC_ASYNC_INT_POLARITY_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_RESET_MASK                        _MK_MASK_CONST(0x1f80)
+#define APB_MISC_ASYNC_INT_POLARITY_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_READ_MASK                         _MK_MASK_CONST(0x1f80)
+#define APB_MISC_ASYNC_INT_POLARITY_0_WRITE_MASK                        _MK_MASK_CONST(0x1f80)
+// HGP7 Interrupt Polarity   0= falling edge interrupt
+//   1= rising edge interrupt
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP7_INT_POLARITY_SHIFT                   _MK_SHIFT_CONST(7)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP7_INT_POLARITY_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_POLARITY_0_HGP7_INT_POLARITY_SHIFT)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP7_INT_POLARITY_RANGE                   7:7
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP7_INT_POLARITY_WOFFSET                 0x0
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP7_INT_POLARITY_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP7_INT_POLARITY_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP7_INT_POLARITY_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP7_INT_POLARITY_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP7_INT_POLARITY_LOW                     _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP7_INT_POLARITY_HIGH                    _MK_ENUM_CONST(1)
+
+// HGP8 Interrupt Polarity   0= falling edge interrupt
+//   1= rising edge interrupt
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP8_INT_POLARITY_SHIFT                   _MK_SHIFT_CONST(8)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP8_INT_POLARITY_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_POLARITY_0_HGP8_INT_POLARITY_SHIFT)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP8_INT_POLARITY_RANGE                   8:8
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP8_INT_POLARITY_WOFFSET                 0x0
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP8_INT_POLARITY_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP8_INT_POLARITY_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP8_INT_POLARITY_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP8_INT_POLARITY_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP8_INT_POLARITY_LOW                     _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP8_INT_POLARITY_HIGH                    _MK_ENUM_CONST(1)
+
+// HGP9 Interrupt Polarity   0= falling edge interrupt
+//   1= rising edge interrupt
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP9_INT_POLARITY_SHIFT                   _MK_SHIFT_CONST(9)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP9_INT_POLARITY_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_POLARITY_0_HGP9_INT_POLARITY_SHIFT)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP9_INT_POLARITY_RANGE                   9:9
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP9_INT_POLARITY_WOFFSET                 0x0
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP9_INT_POLARITY_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP9_INT_POLARITY_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP9_INT_POLARITY_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP9_INT_POLARITY_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP9_INT_POLARITY_LOW                     _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP9_INT_POLARITY_HIGH                    _MK_ENUM_CONST(1)
+
+// HGP10 Interrupt Polarity   0= falling edge interrupt
+//   1= rising edge interrupt
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP10_INT_POLARITY_SHIFT                  _MK_SHIFT_CONST(10)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP10_INT_POLARITY_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_POLARITY_0_HGP10_INT_POLARITY_SHIFT)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP10_INT_POLARITY_RANGE                  10:10
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP10_INT_POLARITY_WOFFSET                        0x0
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP10_INT_POLARITY_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP10_INT_POLARITY_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP10_INT_POLARITY_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP10_INT_POLARITY_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP10_INT_POLARITY_LOW                    _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP10_INT_POLARITY_HIGH                   _MK_ENUM_CONST(1)
+
+// HGP11 Interrupt Polarity   0= falling edge interrupt
+//   1= rising edge interrupt
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP11_INT_POLARITY_SHIFT                  _MK_SHIFT_CONST(11)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP11_INT_POLARITY_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_POLARITY_0_HGP11_INT_POLARITY_SHIFT)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP11_INT_POLARITY_RANGE                  11:11
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP11_INT_POLARITY_WOFFSET                        0x0
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP11_INT_POLARITY_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP11_INT_POLARITY_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP11_INT_POLARITY_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP11_INT_POLARITY_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP11_INT_POLARITY_LOW                    _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP11_INT_POLARITY_HIGH                   _MK_ENUM_CONST(1)
+
+// HGP12 Interrupt Polarity   0= falling edge interrupt
+//   1= rising edge interrupt
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP12_INT_POLARITY_SHIFT                  _MK_SHIFT_CONST(12)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP12_INT_POLARITY_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_POLARITY_0_HGP12_INT_POLARITY_SHIFT)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP12_INT_POLARITY_RANGE                  12:12
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP12_INT_POLARITY_WOFFSET                        0x0
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP12_INT_POLARITY_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP12_INT_POLARITY_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP12_INT_POLARITY_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP12_INT_POLARITY_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP12_INT_POLARITY_LOW                    _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP12_INT_POLARITY_HIGH                   _MK_ENUM_CONST(1)
+
+
+// Register APB_MISC_ASYNC_INT_TYPE_SELECT_0  // Interrupt Type
+//  These bits specify whether an interrupt 
+//  is generated on an edge of a level type.
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0                        _MK_ADDR_CONST(0x454)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_SECURE                         0x0
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_WORD_COUNT                     0x1
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_RESET_MASK                     _MK_MASK_CONST(0x1f80)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_READ_MASK                      _MK_MASK_CONST(0x1f80)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_WRITE_MASK                     _MK_MASK_CONST(0x1f80)
+// HGP7 Interrupt Type   0= Edge type
+//   1= Level type
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP7_INT_TYPE_SHIFT                    _MK_SHIFT_CONST(7)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP7_INT_TYPE_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP7_INT_TYPE_SHIFT)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP7_INT_TYPE_RANGE                    7:7
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP7_INT_TYPE_WOFFSET                  0x0
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP7_INT_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP7_INT_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP7_INT_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP7_INT_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP7_INT_TYPE_EDGE                     _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP7_INT_TYPE_LEVEL                    _MK_ENUM_CONST(1)
+
+// HGP8 Interrupt Polarity   0= Edge type
+//   1= Level type
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP8_INT_TYPE_SHIFT                    _MK_SHIFT_CONST(8)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP8_INT_TYPE_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP8_INT_TYPE_SHIFT)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP8_INT_TYPE_RANGE                    8:8
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP8_INT_TYPE_WOFFSET                  0x0
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP8_INT_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP8_INT_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP8_INT_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP8_INT_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP8_INT_TYPE_EDGE                     _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP8_INT_TYPE_LEVEL                    _MK_ENUM_CONST(1)
+
+// HGP9 Interrupt Polarity   0= Edge type
+//   1= Level type
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP9_INT_TYPE_SHIFT                    _MK_SHIFT_CONST(9)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP9_INT_TYPE_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP9_INT_TYPE_SHIFT)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP9_INT_TYPE_RANGE                    9:9
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP9_INT_TYPE_WOFFSET                  0x0
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP9_INT_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP9_INT_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP9_INT_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP9_INT_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP9_INT_TYPE_EDGE                     _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP9_INT_TYPE_LEVEL                    _MK_ENUM_CONST(1)
+
+// HGP10 Interrupt Polarity   0= Edge type
+//   1= Level type
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP10_INT_TYPE_SHIFT                   _MK_SHIFT_CONST(10)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP10_INT_TYPE_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP10_INT_TYPE_SHIFT)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP10_INT_TYPE_RANGE                   10:10
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP10_INT_TYPE_WOFFSET                 0x0
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP10_INT_TYPE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP10_INT_TYPE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP10_INT_TYPE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP10_INT_TYPE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP10_INT_TYPE_EDGE                    _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP10_INT_TYPE_LEVEL                   _MK_ENUM_CONST(1)
+
+// HGP11 Interrupt Polarity   0= Edge type
+//   1= Level type
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP11_INT_TYPE_SHIFT                   _MK_SHIFT_CONST(11)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP11_INT_TYPE_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP11_INT_TYPE_SHIFT)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP11_INT_TYPE_RANGE                   11:11
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP11_INT_TYPE_WOFFSET                 0x0
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP11_INT_TYPE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP11_INT_TYPE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP11_INT_TYPE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP11_INT_TYPE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP11_INT_TYPE_EDGE                    _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP11_INT_TYPE_LEVEL                   _MK_ENUM_CONST(1)
+
+// HGP12 Interrupt Polarity   0= Edge type
+//   1= Level type
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP12_INT_TYPE_SHIFT                   _MK_SHIFT_CONST(12)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP12_INT_TYPE_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP12_INT_TYPE_SHIFT)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP12_INT_TYPE_RANGE                   12:12
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP12_INT_TYPE_WOFFSET                 0x0
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP12_INT_TYPE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP12_INT_TYPE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP12_INT_TYPE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP12_INT_TYPE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP12_INT_TYPE_EDGE                    _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP12_INT_TYPE_LEVEL                   _MK_ENUM_CONST(1)
+
+
+// Register APB_MISC_GP_MODEREG_0  
+#define APB_MISC_GP_MODEREG_0                   _MK_ADDR_CONST(0x800)
+#define APB_MISC_GP_MODEREG_0_SECURE                    0x0
+#define APB_MISC_GP_MODEREG_0_WORD_COUNT                        0x1
+#define APB_MISC_GP_MODEREG_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_MODEREG_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_MODEREG_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_MODEREG_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_MODEREG_0_READ_MASK                         _MK_MASK_CONST(0x301)
+#define APB_MISC_GP_MODEREG_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+// Standby pad input 1 = STANDBYN is    asserted (low  voltage),                   0 = STANDBYN is desasserted (high voltage)
+#define APB_MISC_GP_MODEREG_0_STANDBY_IE_SHIFT                  _MK_SHIFT_CONST(0)
+#define APB_MISC_GP_MODEREG_0_STANDBY_IE_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_GP_MODEREG_0_STANDBY_IE_SHIFT)
+#define APB_MISC_GP_MODEREG_0_STANDBY_IE_RANGE                  0:0
+#define APB_MISC_GP_MODEREG_0_STANDBY_IE_WOFFSET                        0x0
+#define APB_MISC_GP_MODEREG_0_STANDBY_IE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_MODEREG_0_STANDBY_IE_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_MODEREG_0_STANDBY_IE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_MODEREG_0_STANDBY_IE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_MODEREG_0_STANDBY_IE_DEASSERTED                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_MODEREG_0_STANDBY_IE_ASSERTED                       _MK_ENUM_CONST(1)
+
+// LP-DDR Strap option bit 0.
+#define APB_MISC_GP_MODEREG_0_LPDDR_STRAP0_SHIFT                        _MK_SHIFT_CONST(8)
+#define APB_MISC_GP_MODEREG_0_LPDDR_STRAP0_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_MODEREG_0_LPDDR_STRAP0_SHIFT)
+#define APB_MISC_GP_MODEREG_0_LPDDR_STRAP0_RANGE                        8:8
+#define APB_MISC_GP_MODEREG_0_LPDDR_STRAP0_WOFFSET                      0x0
+#define APB_MISC_GP_MODEREG_0_LPDDR_STRAP0_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_MODEREG_0_LPDDR_STRAP0_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_MODEREG_0_LPDDR_STRAP0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_MODEREG_0_LPDDR_STRAP0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// LP-DDR Strap option bit 1.
+#define APB_MISC_GP_MODEREG_0_LPDDR_STRAP1_SHIFT                        _MK_SHIFT_CONST(9)
+#define APB_MISC_GP_MODEREG_0_LPDDR_STRAP1_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_MODEREG_0_LPDDR_STRAP1_SHIFT)
+#define APB_MISC_GP_MODEREG_0_LPDDR_STRAP1_RANGE                        9:9
+#define APB_MISC_GP_MODEREG_0_LPDDR_STRAP1_WOFFSET                      0x0
+#define APB_MISC_GP_MODEREG_0_LPDDR_STRAP1_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_MODEREG_0_LPDDR_STRAP1_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_MODEREG_0_LPDDR_STRAP1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_MODEREG_0_LPDDR_STRAP1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_HIDREV_0  
+#define APB_MISC_GP_HIDREV_0                    _MK_ADDR_CONST(0x804)
+#define APB_MISC_GP_HIDREV_0_SECURE                     0x0
+#define APB_MISC_GP_HIDREV_0_WORD_COUNT                         0x1
+#define APB_MISC_GP_HIDREV_0_RESET_VAL                  _MK_MASK_CONST(0x22017)
+#define APB_MISC_GP_HIDREV_0_RESET_MASK                         _MK_MASK_CONST(0xfffff)
+#define APB_MISC_GP_HIDREV_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_HIDREV_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_HIDREV_0_READ_MASK                  _MK_MASK_CONST(0xfffff)
+#define APB_MISC_GP_HIDREV_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
+// Chip ID family register. There maybe a new HIDFAM code
+// added for MG20 products, this is still being descided.
+#define APB_MISC_GP_HIDREV_0_HIDFAM_SHIFT                       _MK_SHIFT_CONST(0)
+#define APB_MISC_GP_HIDREV_0_HIDFAM_FIELD                       (_MK_MASK_CONST(0xf) << APB_MISC_GP_HIDREV_0_HIDFAM_SHIFT)
+#define APB_MISC_GP_HIDREV_0_HIDFAM_RANGE                       3:0
+#define APB_MISC_GP_HIDREV_0_HIDFAM_WOFFSET                     0x0
+#define APB_MISC_GP_HIDREV_0_HIDFAM_DEFAULT                     _MK_MASK_CONST(0x7)
+#define APB_MISC_GP_HIDREV_0_HIDFAM_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define APB_MISC_GP_HIDREV_0_HIDFAM_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_HIDREV_0_HIDFAM_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_HIDREV_0_HIDFAM_GPU                 _MK_ENUM_CONST(0)
+#define APB_MISC_GP_HIDREV_0_HIDFAM_HANDHELD                    _MK_ENUM_CONST(1)
+#define APB_MISC_GP_HIDREV_0_HIDFAM_BR_CHIPS                    _MK_ENUM_CONST(2)
+#define APB_MISC_GP_HIDREV_0_HIDFAM_CRUSH                       _MK_ENUM_CONST(3)
+#define APB_MISC_GP_HIDREV_0_HIDFAM_MCP                 _MK_ENUM_CONST(4)
+#define APB_MISC_GP_HIDREV_0_HIDFAM_CK                  _MK_ENUM_CONST(5)
+#define APB_MISC_GP_HIDREV_0_HIDFAM_VAIO                        _MK_ENUM_CONST(6)
+#define APB_MISC_GP_HIDREV_0_HIDFAM_HANDHELD_SOC                        _MK_ENUM_CONST(7)
+
+// Chip ID major revision (0: Emulation, 1-15: Silicon)
+#define APB_MISC_GP_HIDREV_0_MAJORREV_SHIFT                     _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_HIDREV_0_MAJORREV_FIELD                     (_MK_MASK_CONST(0xf) << APB_MISC_GP_HIDREV_0_MAJORREV_SHIFT)
+#define APB_MISC_GP_HIDREV_0_MAJORREV_RANGE                     7:4
+#define APB_MISC_GP_HIDREV_0_MAJORREV_WOFFSET                   0x0
+#define APB_MISC_GP_HIDREV_0_MAJORREV_DEFAULT                   _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_HIDREV_0_MAJORREV_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define APB_MISC_GP_HIDREV_0_MAJORREV_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_HIDREV_0_MAJORREV_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_HIDREV_0_MAJORREV_EMULATION                 _MK_ENUM_CONST(0)
+#define APB_MISC_GP_HIDREV_0_MAJORREV_A01                       _MK_ENUM_CONST(1)
+
+// Chip ID
+#define APB_MISC_GP_HIDREV_0_CHIPID_SHIFT                       _MK_SHIFT_CONST(8)
+#define APB_MISC_GP_HIDREV_0_CHIPID_FIELD                       (_MK_MASK_CONST(0xff) << APB_MISC_GP_HIDREV_0_CHIPID_SHIFT)
+#define APB_MISC_GP_HIDREV_0_CHIPID_RANGE                       15:8
+#define APB_MISC_GP_HIDREV_0_CHIPID_WOFFSET                     0x0
+#define APB_MISC_GP_HIDREV_0_CHIPID_DEFAULT                     _MK_MASK_CONST(0x20)
+#define APB_MISC_GP_HIDREV_0_CHIPID_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define APB_MISC_GP_HIDREV_0_CHIPID_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_HIDREV_0_CHIPID_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Chip ID minor revision (IF MAJORREV==0(Emulation) THEN  0: QT, 1:E388 FPGA)
+#define APB_MISC_GP_HIDREV_0_MINORREV_SHIFT                     _MK_SHIFT_CONST(16)
+#define APB_MISC_GP_HIDREV_0_MINORREV_FIELD                     (_MK_MASK_CONST(0xf) << APB_MISC_GP_HIDREV_0_MINORREV_SHIFT)
+#define APB_MISC_GP_HIDREV_0_MINORREV_RANGE                     19:16
+#define APB_MISC_GP_HIDREV_0_MINORREV_WOFFSET                   0x0
+#define APB_MISC_GP_HIDREV_0_MINORREV_DEFAULT                   _MK_MASK_CONST(0x2)
+#define APB_MISC_GP_HIDREV_0_MINORREV_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define APB_MISC_GP_HIDREV_0_MINORREV_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_HIDREV_0_MINORREV_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Reserved address 2056 [0x808] 
+
+// Reserved address 2060 [0x80c] 
+
+// Register APB_MISC_GP_ASDBGREG_0  
+#define APB_MISC_GP_ASDBGREG_0                  _MK_ADDR_CONST(0x810)
+#define APB_MISC_GP_ASDBGREG_0_SECURE                   0x0
+#define APB_MISC_GP_ASDBGREG_0_WORD_COUNT                       0x1
+#define APB_MISC_GP_ASDBGREG_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_RESET_MASK                       _MK_MASK_CONST(0x3ff0ffdf)
+#define APB_MISC_GP_ASDBGREG_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_READ_MASK                        _MK_MASK_CONST(0x3ff0ffdf)
+#define APB_MISC_GP_ASDBGREG_0_WRITE_MASK                       _MK_MASK_CONST(0x3ff0ffdf)
+// Enables iddq (WARNING: Will functionally kill chip)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_IDDQ_EN_SHIFT                    _MK_SHIFT_CONST(0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_IDDQ_EN_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG_0_CFG2TMC_IDDQ_EN_SHIFT)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_IDDQ_EN_RANGE                    0:0
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_IDDQ_EN_WOFFSET                  0x0
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_IDDQ_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_IDDQ_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_IDDQ_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_IDDQ_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_IDDQ_EN_DISABLE                  _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_IDDQ_EN_ENABLE                   _MK_ENUM_CONST(1)
+
+// Enables pullup
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLUP_EN_SHIFT                  _MK_SHIFT_CONST(1)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLUP_EN_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLUP_EN_SHIFT)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLUP_EN_RANGE                  1:1
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLUP_EN_WOFFSET                        0x0
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLUP_EN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLUP_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLUP_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLUP_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLUP_EN_DISABLE                        _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLUP_EN_ENABLE                 _MK_ENUM_CONST(1)
+
+// Enables pulldown
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLDOWN_EN_SHIFT                        _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLDOWN_EN_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLDOWN_EN_SHIFT)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLDOWN_EN_RANGE                        2:2
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLDOWN_EN_WOFFSET                      0x0
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLDOWN_EN_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLDOWN_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLDOWN_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLDOWN_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLDOWN_EN_DISABLE                      _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLDOWN_EN_ENABLE                       _MK_ENUM_CONST(1)
+
+// Enables debug mode
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_DEBUG_ENABLE_SHIFT                       _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_DEBUG_ENABLE_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG_0_CFG2TMC_DEBUG_ENABLE_SHIFT)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_DEBUG_ENABLE_RANGE                       3:3
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_DEBUG_ENABLE_WOFFSET                     0x0
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_DEBUG_ENABLE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_DEBUG_ENABLE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_DEBUG_ENABLE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_DEBUG_ENABLE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_DEBUG_ENABLE_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_DEBUG_ENABLE_ENABLE                      _MK_ENUM_CONST(1)
+
+// Enables performance monitor mode
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PM_ENABLE_SHIFT                  _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PM_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG_0_CFG2TMC_PM_ENABLE_SHIFT)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PM_ENABLE_RANGE                  4:4
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PM_ENABLE_WOFFSET                        0x0
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PM_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PM_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PM_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PM_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PM_ENABLE_DISABLE                        _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PM_ENABLE_ENABLE                 _MK_ENUM_CONST(1)
+
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_CLKBYP_FUNC_SHIFT                        _MK_SHIFT_CONST(6)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_CLKBYP_FUNC_FIELD                        (_MK_MASK_CONST(0x3) << APB_MISC_GP_ASDBGREG_0_CFG2TMC_CLKBYP_FUNC_SHIFT)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_CLKBYP_FUNC_RANGE                        7:6
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_CLKBYP_FUNC_WOFFSET                      0x0
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_CLKBYP_FUNC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_CLKBYP_FUNC_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_CLKBYP_FUNC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_CLKBYP_FUNC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_CLKBYP_FUNC_DISABLE                      _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_CLKBYP_FUNC_ENABLE                       _MK_ENUM_CONST(1)
+
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T1CLK_SHIFT                        _MK_SHIFT_CONST(8)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T1CLK_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T1CLK_SHIFT)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T1CLK_RANGE                        8:8
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T1CLK_WOFFSET                      0x0
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T1CLK_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T1CLK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T1CLK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T1CLK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T1CLK_DISABLE                      _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T1CLK_ENABLE                       _MK_ENUM_CONST(1)
+
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T2CLK_SHIFT                        _MK_SHIFT_CONST(9)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T2CLK_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T2CLK_SHIFT)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T2CLK_RANGE                        9:9
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T2CLK_WOFFSET                      0x0
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T2CLK_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T2CLK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T2CLK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T2CLK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T2CLK_DISABLE                      _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T2CLK_ENABLE                       _MK_ENUM_CONST(1)
+
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T3CLK_SHIFT                        _MK_SHIFT_CONST(10)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T3CLK_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T3CLK_SHIFT)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T3CLK_RANGE                        10:10
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T3CLK_WOFFSET                      0x0
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T3CLK_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T3CLK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T3CLK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T3CLK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T3CLK_DISABLE                      _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T3CLK_ENABLE                       _MK_ENUM_CONST(1)
+
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T4CLK_SHIFT                        _MK_SHIFT_CONST(11)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T4CLK_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T4CLK_SHIFT)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T4CLK_RANGE                        11:11
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T4CLK_WOFFSET                      0x0
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T4CLK_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T4CLK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T4CLK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T4CLK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T4CLK_DISABLE                      _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T4CLK_ENABLE                       _MK_ENUM_CONST(1)
+
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T5CLK_SHIFT                        _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T5CLK_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T5CLK_SHIFT)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T5CLK_RANGE                        12:12
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T5CLK_WOFFSET                      0x0
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T5CLK_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T5CLK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T5CLK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T5CLK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T5CLK_DISABLE                      _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T5CLK_ENABLE                       _MK_ENUM_CONST(1)
+
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T6CLK_SHIFT                        _MK_SHIFT_CONST(13)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T6CLK_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T6CLK_SHIFT)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T6CLK_RANGE                        13:13
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T6CLK_WOFFSET                      0x0
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T6CLK_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T6CLK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T6CLK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T6CLK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T6CLK_DISABLE                      _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T6CLK_ENABLE                       _MK_ENUM_CONST(1)
+
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T7CLK_SHIFT                        _MK_SHIFT_CONST(14)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T7CLK_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T7CLK_SHIFT)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T7CLK_RANGE                        14:14
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T7CLK_WOFFSET                      0x0
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T7CLK_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T7CLK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T7CLK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T7CLK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T7CLK_DISABLE                      _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T7CLK_ENABLE                       _MK_ENUM_CONST(1)
+
+//  Obsolete previously used with host_pad_macros (jmoskal)
+//16      rw  CFG2TMC_SW_BP_WRNCLK      i=0x0
+//    enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_CLK_DIV_SHIFT                      _MK_SHIFT_CONST(15)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_CLK_DIV_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_CLK_DIV_SHIFT)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_CLK_DIV_RANGE                      15:15
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_CLK_DIV_WOFFSET                    0x0
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_CLK_DIV_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_CLK_DIV_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_CLK_DIV_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_CLK_DIV_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_CLK_DIV_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_CLK_DIV_ENABLE                     _MK_ENUM_CONST(1)
+
+// control timing characteristics for the compiled rams
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_EMAA_SHIFT                   _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_EMAA_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_EMAA_SHIFT)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_EMAA_RANGE                   21:20
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_EMAA_WOFFSET                 0x0
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_EMAA_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_EMAA_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_EMAA_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_EMAA_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_EMAA_DISABLE                 _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_EMAA_ENABLE                  _MK_ENUM_CONST(1)
+
+// control write timing characteristics for the compiled RAMDP
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_DP_SHIFT                        _MK_SHIFT_CONST(22)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_DP_FIELD                        (_MK_MASK_CONST(0x3) << APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_DP_SHIFT)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_DP_RANGE                        23:22
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_DP_WOFFSET                      0x0
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_DP_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_DP_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_DP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_DP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// control write timing characteristics for the compiled RAMPDP
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_PDP_SHIFT                       _MK_SHIFT_CONST(24)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_PDP_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_PDP_SHIFT)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_PDP_RANGE                       25:24
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_PDP_WOFFSET                     0x0
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_PDP_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_PDP_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_PDP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_PDP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// control write timing characteristics for the compiled RAMREG
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_REG_SHIFT                       _MK_SHIFT_CONST(26)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_REG_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_REG_SHIFT)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_REG_RANGE                       27:26
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_REG_WOFFSET                     0x0
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_REG_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_REG_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_REG_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_REG_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// control write timing characteristics for the compiled RAMSP
+// ECO 385781, add reset to RAM_SVOP_SP
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_SP_SHIFT                        _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_SP_FIELD                        (_MK_MASK_CONST(0x3) << APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_SP_SHIFT)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_SP_RANGE                        29:28
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_SP_WOFFSET                      0x0
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_SP_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_SP_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_SP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_SP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Reserved address 2068 [0x814] 
+
+// Register APB_MISC_GP_OBSCTRL_0  
+#define APB_MISC_GP_OBSCTRL_0                   _MK_ADDR_CONST(0x818)
+#define APB_MISC_GP_OBSCTRL_0_SECURE                    0x0
+#define APB_MISC_GP_OBSCTRL_0_WORD_COUNT                        0x1
+#define APB_MISC_GP_OBSCTRL_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OBSCTRL_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_GP_OBSCTRL_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OBSCTRL_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OBSCTRL_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_GP_OBSCTRL_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
+// Module-level mux select for determining which debug signals to send out
+#define APB_MISC_GP_OBSCTRL_0_OBS_SIG_SEL_SHIFT                 _MK_SHIFT_CONST(0)
+#define APB_MISC_GP_OBSCTRL_0_OBS_SIG_SEL_FIELD                 (_MK_MASK_CONST(0xffff) << APB_MISC_GP_OBSCTRL_0_OBS_SIG_SEL_SHIFT)
+#define APB_MISC_GP_OBSCTRL_0_OBS_SIG_SEL_RANGE                 15:0
+#define APB_MISC_GP_OBSCTRL_0_OBS_SIG_SEL_WOFFSET                       0x0
+#define APB_MISC_GP_OBSCTRL_0_OBS_SIG_SEL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OBSCTRL_0_OBS_SIG_SEL_DEFAULT_MASK                  _MK_MASK_CONST(0xffff)
+#define APB_MISC_GP_OBSCTRL_0_OBS_SIG_SEL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OBSCTRL_0_OBS_SIG_SEL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Observation module select
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_SHIFT                 _MK_SHIFT_CONST(16)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_FIELD                 (_MK_MASK_CONST(0xf) << APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_SHIFT)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_RANGE                 19:16
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_WOFFSET                       0x0
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_PMC                   _MK_ENUM_CONST(0)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_UAVP                  _MK_ENUM_CONST(0)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_CSI                   _MK_ENUM_CONST(0)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_CSICIL                        _MK_ENUM_CONST(1)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_DISPLAY                       _MK_ENUM_CONST(2)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_DISPLAYB                      _MK_ENUM_CONST(3)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_DSI                   _MK_ENUM_CONST(4)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_HDMI                  _MK_ENUM_CONST(5)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_TVO                   _MK_ENUM_CONST(6)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_CAR                   _MK_ENUM_CONST(0)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_EMC                   _MK_ENUM_CONST(1)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_GR2D                  _MK_ENUM_CONST(2)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_HOST1X                        _MK_ENUM_CONST(3)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_MC                    _MK_ENUM_CONST(4)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_MSELECT                       _MK_ENUM_CONST(5)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_STRAT12                       _MK_ENUM_CONST(0)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_FUSE                  _MK_ENUM_CONST(1)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_KFUSE                 _MK_ENUM_CONST(2)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_CSITE                 _MK_ENUM_CONST(3)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_CLIP                  _MK_ENUM_CONST(0)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_IDX                   _MK_ENUM_CONST(1)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_SETUP                 _MK_ENUM_CONST(2)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_VPE                   _MK_ENUM_CONST(3)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_ALU                   _MK_ENUM_CONST(0)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_ATRAST                        _MK_ENUM_CONST(1)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_DWR                   _MK_ENUM_CONST(2)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_FDC                   _MK_ENUM_CONST(3)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_PSEQ                  _MK_ENUM_CONST(4)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_QRAST                 _MK_ENUM_CONST(5)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_TEX                   _MK_ENUM_CONST(6)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_MPEA                  _MK_ENUM_CONST(0)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_MPEB                  _MK_ENUM_CONST(1)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_MPEC                  _MK_ENUM_CONST(2)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_UVDE                  _MK_ENUM_CONST(0)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_EPP                   _MK_ENUM_CONST(0)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_ISP                   _MK_ENUM_CONST(1)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_VI                    _MK_ENUM_CONST(2)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_PCIE2                 _MK_ENUM_CONST(0)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_AFI                   _MK_ENUM_CONST(1)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_USB                   _MK_ENUM_CONST(0)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_USB2                  _MK_ENUM_CONST(1)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_USB3                  _MK_ENUM_CONST(2)
+
+// Observation partition select
+#define APB_MISC_GP_OBSCTRL_0_OBS_PART_SEL_SHIFT                        _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_OBSCTRL_0_OBS_PART_SEL_FIELD                        (_MK_MASK_CONST(0xf) << APB_MISC_GP_OBSCTRL_0_OBS_PART_SEL_SHIFT)
+#define APB_MISC_GP_OBSCTRL_0_OBS_PART_SEL_RANGE                        23:20
+#define APB_MISC_GP_OBSCTRL_0_OBS_PART_SEL_WOFFSET                      0x0
+#define APB_MISC_GP_OBSCTRL_0_OBS_PART_SEL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OBSCTRL_0_OBS_PART_SEL_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define APB_MISC_GP_OBSCTRL_0_OBS_PART_SEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OBSCTRL_0_OBS_PART_SEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OBSCTRL_0_OBS_PART_SEL_AO                   _MK_ENUM_CONST(0)
+#define APB_MISC_GP_OBSCTRL_0_OBS_PART_SEL_AVP                  _MK_ENUM_CONST(1)
+#define APB_MISC_GP_OBSCTRL_0_OBS_PART_SEL_DIS                  _MK_ENUM_CONST(2)
+#define APB_MISC_GP_OBSCTRL_0_OBS_PART_SEL_GR                   _MK_ENUM_CONST(3)
+#define APB_MISC_GP_OBSCTRL_0_OBS_PART_SEL_MPE                  _MK_ENUM_CONST(4)
+#define APB_MISC_GP_OBSCTRL_0_OBS_PART_SEL_PCX                  _MK_ENUM_CONST(5)
+#define APB_MISC_GP_OBSCTRL_0_OBS_PART_SEL_ST                   _MK_ENUM_CONST(6)
+#define APB_MISC_GP_OBSCTRL_0_OBS_PART_SEL_TDA                  _MK_ENUM_CONST(7)
+#define APB_MISC_GP_OBSCTRL_0_OBS_PART_SEL_TDB                  _MK_ENUM_CONST(8)
+#define APB_MISC_GP_OBSCTRL_0_OBS_PART_SEL_VE                   _MK_ENUM_CONST(9)
+#define APB_MISC_GP_OBSCTRL_0_OBS_PART_SEL_VDE                  _MK_ENUM_CONST(10)
+#define APB_MISC_GP_OBSCTRL_0_OBS_PART_SEL_USX                  _MK_ENUM_CONST(11)
+
+// Module internal mux select
+#define APB_MISC_GP_OBSCTRL_0_OBS_SIG_INT_SEL_SHIFT                     _MK_SHIFT_CONST(24)
+#define APB_MISC_GP_OBSCTRL_0_OBS_SIG_INT_SEL_FIELD                     (_MK_MASK_CONST(0x7f) << APB_MISC_GP_OBSCTRL_0_OBS_SIG_INT_SEL_SHIFT)
+#define APB_MISC_GP_OBSCTRL_0_OBS_SIG_INT_SEL_RANGE                     30:24
+#define APB_MISC_GP_OBSCTRL_0_OBS_SIG_INT_SEL_WOFFSET                   0x0
+#define APB_MISC_GP_OBSCTRL_0_OBS_SIG_INT_SEL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OBSCTRL_0_OBS_SIG_INT_SEL_DEFAULT_MASK                      _MK_MASK_CONST(0x7f)
+#define APB_MISC_GP_OBSCTRL_0_OBS_SIG_INT_SEL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OBSCTRL_0_OBS_SIG_INT_SEL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Observation bus enable
+#define APB_MISC_GP_OBSCTRL_0_OBS_EN_SHIFT                      _MK_SHIFT_CONST(31)
+#define APB_MISC_GP_OBSCTRL_0_OBS_EN_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_OBSCTRL_0_OBS_EN_SHIFT)
+#define APB_MISC_GP_OBSCTRL_0_OBS_EN_RANGE                      31:31
+#define APB_MISC_GP_OBSCTRL_0_OBS_EN_WOFFSET                    0x0
+#define APB_MISC_GP_OBSCTRL_0_OBS_EN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OBSCTRL_0_OBS_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_OBSCTRL_0_OBS_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OBSCTRL_0_OBS_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OBSCTRL_0_OBS_EN_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_GP_OBSCTRL_0_OBS_EN_ENABLE                     _MK_ENUM_CONST(1)
+
+
+// Register APB_MISC_GP_OBSDATA_0  
+#define APB_MISC_GP_OBSDATA_0                   _MK_ADDR_CONST(0x81c)
+#define APB_MISC_GP_OBSDATA_0_SECURE                    0x0
+#define APB_MISC_GP_OBSDATA_0_WORD_COUNT                        0x1
+#define APB_MISC_GP_OBSDATA_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OBSDATA_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OBSDATA_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OBSDATA_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OBSDATA_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_GP_OBSDATA_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+// Observation port data.  This should be the same data that is going out on the observation bus.
+#define APB_MISC_GP_OBSDATA_0_OBS_DATA_SHIFT                    _MK_SHIFT_CONST(0)
+#define APB_MISC_GP_OBSDATA_0_OBS_DATA_FIELD                    (_MK_MASK_CONST(0xffffffff) << APB_MISC_GP_OBSDATA_0_OBS_DATA_SHIFT)
+#define APB_MISC_GP_OBSDATA_0_OBS_DATA_RANGE                    31:0
+#define APB_MISC_GP_OBSDATA_0_OBS_DATA_WOFFSET                  0x0
+#define APB_MISC_GP_OBSDATA_0_OBS_DATA_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OBSDATA_0_OBS_DATA_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OBSDATA_0_OBS_DATA_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OBSDATA_0_OBS_DATA_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Reserved address 2080 [0x820] 
+
+// Reserved address 2084 [0x824] 
+
+// Reserved address 2088 [0x828] 
+
+// Reserved address 2092 [0x82c] 
+
+// Reserved address 2096 [0x830] 
+
+// Reserved address 2100 [0x834] 
+
+// Reserved address 2104 [0x838] 
+
+// Reserved address 2108 [0x83c] 
+
+// Reserved address 2112 [0x840] 
+
+// Reserved address 2116 [0x844] 
+
+// Reserved address 2120 [0x848] 
+
+// Reserved address 2124 [0x84c] 
+
+// Reserved address 2128 [0x850] 
+
+// Reserved address 2132 [0x854] 
+
+// Register APB_MISC_GP_ASDBGREG2_0  
+#define APB_MISC_GP_ASDBGREG2_0                 _MK_ADDR_CONST(0x858)
+#define APB_MISC_GP_ASDBGREG2_0_SECURE                  0x0
+#define APB_MISC_GP_ASDBGREG2_0_WORD_COUNT                      0x1
+#define APB_MISC_GP_ASDBGREG2_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_RESET_MASK                      _MK_MASK_CONST(0x7ff80)
+#define APB_MISC_GP_ASDBGREG2_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_READ_MASK                       _MK_MASK_CONST(0x7ff80)
+#define APB_MISC_GP_ASDBGREG2_0_WRITE_MASK                      _MK_MASK_CONST(0x7ff80)
+//Enable bypass of functional clock with test clock 8
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T8CLK_SHIFT                       _MK_SHIFT_CONST(7)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T8CLK_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T8CLK_SHIFT)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T8CLK_RANGE                       7:7
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T8CLK_WOFFSET                     0x0
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T8CLK_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T8CLK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T8CLK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T8CLK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T8CLK_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T8CLK_ENABLE                      _MK_ENUM_CONST(1)
+
+//Enable bypass of functional clock with test clock 9
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T9CLK_SHIFT                       _MK_SHIFT_CONST(8)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T9CLK_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T9CLK_SHIFT)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T9CLK_RANGE                       8:8
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T9CLK_WOFFSET                     0x0
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T9CLK_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T9CLK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T9CLK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T9CLK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T9CLK_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T9CLK_ENABLE                      _MK_ENUM_CONST(1)
+
+//Enable bypass of functional clock with test clock 10
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T10CLK_SHIFT                      _MK_SHIFT_CONST(9)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T10CLK_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T10CLK_SHIFT)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T10CLK_RANGE                      9:9
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T10CLK_WOFFSET                    0x0
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T10CLK_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T10CLK_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T10CLK_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T10CLK_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T10CLK_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T10CLK_ENABLE                     _MK_ENUM_CONST(1)
+
+//Enable bypass of functional clock with test clock 11
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T11CLK_SHIFT                      _MK_SHIFT_CONST(10)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T11CLK_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T11CLK_SHIFT)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T11CLK_RANGE                      10:10
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T11CLK_WOFFSET                    0x0
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T11CLK_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T11CLK_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T11CLK_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T11CLK_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T11CLK_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T11CLK_ENABLE                     _MK_ENUM_CONST(1)
+
+//Enable bypass of functional clock with test clock 12
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T12CLK_SHIFT                      _MK_SHIFT_CONST(11)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T12CLK_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T12CLK_SHIFT)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T12CLK_RANGE                      11:11
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T12CLK_WOFFSET                    0x0
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T12CLK_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T12CLK_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T12CLK_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T12CLK_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T12CLK_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T12CLK_ENABLE                     _MK_ENUM_CONST(1)
+
+//Enable bypass of functional clock with test clock 13
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T13CLK_SHIFT                      _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T13CLK_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T13CLK_SHIFT)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T13CLK_RANGE                      12:12
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T13CLK_WOFFSET                    0x0
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T13CLK_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T13CLK_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T13CLK_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T13CLK_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T13CLK_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T13CLK_ENABLE                     _MK_ENUM_CONST(1)
+
+//Enable bypass of functional clock with test clock 14
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T14CLK_SHIFT                      _MK_SHIFT_CONST(13)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T14CLK_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T14CLK_SHIFT)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T14CLK_RANGE                      13:13
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T14CLK_WOFFSET                    0x0
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T14CLK_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T14CLK_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T14CLK_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T14CLK_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T14CLK_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T14CLK_ENABLE                     _MK_ENUM_CONST(1)
+
+//Enable bypass of functional clock with test clock 15
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T15CLK_SHIFT                      _MK_SHIFT_CONST(14)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T15CLK_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T15CLK_SHIFT)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T15CLK_RANGE                      14:14
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T15CLK_WOFFSET                    0x0
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T15CLK_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T15CLK_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T15CLK_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T15CLK_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T15CLK_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T15CLK_ENABLE                     _MK_ENUM_CONST(1)
+
+//Enable bypass of functional clock with test clock 16
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T16CLK_SHIFT                      _MK_SHIFT_CONST(15)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T16CLK_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T16CLK_SHIFT)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T16CLK_RANGE                      15:15
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T16CLK_WOFFSET                    0x0
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T16CLK_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T16CLK_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T16CLK_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T16CLK_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T16CLK_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T16CLK_ENABLE                     _MK_ENUM_CONST(1)
+
+//Enable bypass of functional clock with test clock 17
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T17CLK_SHIFT                      _MK_SHIFT_CONST(16)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T17CLK_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T17CLK_SHIFT)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T17CLK_RANGE                      16:16
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T17CLK_WOFFSET                    0x0
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T17CLK_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T17CLK_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T17CLK_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T17CLK_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T17CLK_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T17CLK_ENABLE                     _MK_ENUM_CONST(1)
+
+//Enable bypass of functional clock with test clock 18
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T18CLK_SHIFT                      _MK_SHIFT_CONST(17)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T18CLK_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T18CLK_SHIFT)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T18CLK_RANGE                      17:17
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T18CLK_WOFFSET                    0x0
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T18CLK_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T18CLK_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T18CLK_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T18CLK_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T18CLK_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T18CLK_ENABLE                     _MK_ENUM_CONST(1)
+
+//Enable bypass of sync Already in NV_car
+//  18       rw  CFG2TMC_OSCFI_BYPASS     i=0x0  //Enable bypass of oscfi
+//            enum ( DISABLE, ENABLE )
+//  19       rw  CFG2TMC_OSCFI_EN         i=0x0  //Enable oscfi refclk
+//      enum ( DISABLE, ENABLE )
+//      enum ( DISABLE, ENABLE )
+//  25:21   rw  CFG2TMC_OSCFI_D           i=0x0  //
+//  31:26   rw  CFG2TMC_OSCFI_S           i=0x0  //
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_SYNC_SHIFT                        _MK_SHIFT_CONST(18)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_SYNC_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_SYNC_SHIFT)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_SYNC_RANGE                        18:18
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_SYNC_WOFFSET                      0x0
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_SYNC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_SYNC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_SYNC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_SYNC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_SYNC_DISABLE                      _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_SYNC_ENABLE                       _MK_ENUM_CONST(1)
+
+
+// Register APB_MISC_GP_ASDBGREG3_0  
+#define APB_MISC_GP_ASDBGREG3_0                 _MK_ADDR_CONST(0x85c)
+#define APB_MISC_GP_ASDBGREG3_0_SECURE                  0x0
+#define APB_MISC_GP_ASDBGREG3_0_WORD_COUNT                      0x1
+#define APB_MISC_GP_ASDBGREG3_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG3_0_RESET_MASK                      _MK_MASK_CONST(0x3ff)
+#define APB_MISC_GP_ASDBGREG3_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG3_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG3_0_READ_MASK                       _MK_MASK_CONST(0x3ff)
+#define APB_MISC_GP_ASDBGREG3_0_WRITE_MASK                      _MK_MASK_CONST(0x3ff)
+// control write timing characteristics for the L1 idata and ddata rams
+#define APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_L1DATA_SHIFT                   _MK_SHIFT_CONST(0)
+#define APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_L1DATA_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_L1DATA_SHIFT)
+#define APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_L1DATA_RANGE                   1:0
+#define APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_L1DATA_WOFFSET                 0x0
+#define APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_L1DATA_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_L1DATA_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_L1DATA_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_L1DATA_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// control write timing characteristics for the L1 itag  and dtag rams 
+#define APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_L1TAG_SHIFT                    _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_L1TAG_FIELD                    (_MK_MASK_CONST(0x3) << APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_L1TAG_SHIFT)
+#define APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_L1TAG_RANGE                    3:2
+#define APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_L1TAG_WOFFSET                  0x0
+#define APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_L1TAG_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_L1TAG_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_L1TAG_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_L1TAG_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// control write timing characteristics for the L2 (SCU) data rams
+#define APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_L2DATA_SHIFT                   _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_L2DATA_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_L2DATA_SHIFT)
+#define APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_L2DATA_RANGE                   5:4
+#define APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_L2DATA_WOFFSET                 0x0
+#define APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_L2DATA_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_L2DATA_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_L2DATA_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_L2DATA_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// control write timing characteristics for the L2 (SCU) tag  rams 
+#define APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_L2TAG_SHIFT                    _MK_SHIFT_CONST(6)
+#define APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_L2TAG_FIELD                    (_MK_MASK_CONST(0x3) << APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_L2TAG_SHIFT)
+#define APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_L2TAG_RANGE                    7:6
+#define APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_L2TAG_WOFFSET                  0x0
+#define APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_L2TAG_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_L2TAG_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_L2TAG_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_L2TAG_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// control write timing characteristics for the irams  
+#define APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_IRAM_SHIFT                     _MK_SHIFT_CONST(8)
+#define APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_IRAM_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_IRAM_SHIFT)
+#define APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_IRAM_RANGE                     9:8
+#define APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_IRAM_WOFFSET                   0x0
+#define APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_IRAM_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_IRAM_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_IRAM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_IRAM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_EMU_REVID_0  
+#define APB_MISC_GP_EMU_REVID_0                 _MK_ADDR_CONST(0x860)
+#define APB_MISC_GP_EMU_REVID_0_SECURE                  0x0
+#define APB_MISC_GP_EMU_REVID_0_WORD_COUNT                      0x1
+#define APB_MISC_GP_EMU_REVID_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EMU_REVID_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_GP_EMU_REVID_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EMU_REVID_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EMU_REVID_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_GP_EMU_REVID_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
+// USED by emulators to indicate netlist #, 0 for silicon.
+#define APB_MISC_GP_EMU_REVID_0_NETLIST_SHIFT                   _MK_SHIFT_CONST(0)
+#define APB_MISC_GP_EMU_REVID_0_NETLIST_FIELD                   (_MK_MASK_CONST(0xffff) << APB_MISC_GP_EMU_REVID_0_NETLIST_SHIFT)
+#define APB_MISC_GP_EMU_REVID_0_NETLIST_RANGE                   15:0
+#define APB_MISC_GP_EMU_REVID_0_NETLIST_WOFFSET                 0x0
+#define APB_MISC_GP_EMU_REVID_0_NETLIST_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EMU_REVID_0_NETLIST_DEFAULT_MASK                    _MK_MASK_CONST(0xffff)
+#define APB_MISC_GP_EMU_REVID_0_NETLIST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EMU_REVID_0_NETLIST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EMU_REVID_0_NETLIST_INIT_ENUM                       NV_EMUL_NETLIST
+
+// USED by emulators to indicate patch #, 0 for silicon.
+#define APB_MISC_GP_EMU_REVID_0_PATCH_SHIFT                     _MK_SHIFT_CONST(16)
+#define APB_MISC_GP_EMU_REVID_0_PATCH_FIELD                     (_MK_MASK_CONST(0xffff) << APB_MISC_GP_EMU_REVID_0_PATCH_SHIFT)
+#define APB_MISC_GP_EMU_REVID_0_PATCH_RANGE                     31:16
+#define APB_MISC_GP_EMU_REVID_0_PATCH_WOFFSET                   0x0
+#define APB_MISC_GP_EMU_REVID_0_PATCH_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EMU_REVID_0_PATCH_DEFAULT_MASK                      _MK_MASK_CONST(0xffff)
+#define APB_MISC_GP_EMU_REVID_0_PATCH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EMU_REVID_0_PATCH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EMU_REVID_0_PATCH_INIT_ENUM                 NV_EMUL_PATCH
+
+
+// Register APB_MISC_GP_TRANSACTOR_SCRATCH_0  
+#define APB_MISC_GP_TRANSACTOR_SCRATCH_0                        _MK_ADDR_CONST(0x864)
+#define APB_MISC_GP_TRANSACTOR_SCRATCH_0_SECURE                         0x0
+#define APB_MISC_GP_TRANSACTOR_SCRATCH_0_WORD_COUNT                     0x1
+#define APB_MISC_GP_TRANSACTOR_SCRATCH_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_TRANSACTOR_SCRATCH_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_GP_TRANSACTOR_SCRATCH_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_TRANSACTOR_SCRATCH_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_TRANSACTOR_SCRATCH_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_GP_TRANSACTOR_SCRATCH_0_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
+// used for emulation to determine test results. USE CPU specific registers below.
+#define APB_MISC_GP_TRANSACTOR_SCRATCH_0_TRANSACTOR_SCRATCH_SHIFT                       _MK_SHIFT_CONST(0)
+#define APB_MISC_GP_TRANSACTOR_SCRATCH_0_TRANSACTOR_SCRATCH_FIELD                       (_MK_MASK_CONST(0xffffffff) << APB_MISC_GP_TRANSACTOR_SCRATCH_0_TRANSACTOR_SCRATCH_SHIFT)
+#define APB_MISC_GP_TRANSACTOR_SCRATCH_0_TRANSACTOR_SCRATCH_RANGE                       31:0
+#define APB_MISC_GP_TRANSACTOR_SCRATCH_0_TRANSACTOR_SCRATCH_WOFFSET                     0x0
+#define APB_MISC_GP_TRANSACTOR_SCRATCH_0_TRANSACTOR_SCRATCH_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_TRANSACTOR_SCRATCH_0_TRANSACTOR_SCRATCH_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_GP_TRANSACTOR_SCRATCH_0_TRANSACTOR_SCRATCH_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_TRANSACTOR_SCRATCH_0_TRANSACTOR_SCRATCH_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_AOCFG1PADCTRL_0  //        0       rw  CFG2TMC_AOCFG1_PULLD_EN i=0x0   // AOCFG1 pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_AOCFG1_PULLU_EN i=0x0   // AOCFG1 pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_AOCFG1PADCTRL_0                     _MK_ADDR_CONST(0x868)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_SECURE                      0x0
+#define APB_MISC_GP_AOCFG1PADCTRL_0_WORD_COUNT                  0x1
+#define APB_MISC_GP_AOCFG1PADCTRL_0_RESET_VAL                   _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_RESET_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_READ_MASK                   _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_WRITE_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+// AOCFG1 data pins high speed mode enable
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_HSM_EN_SHIFT                 _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_HSM_EN_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_HSM_EN_SHIFT)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_HSM_EN_RANGE                 2:2
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_HSM_EN_WOFFSET                       0x0
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_HSM_EN_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_HSM_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_HSM_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_HSM_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_HSM_EN_DISABLE                       _MK_ENUM_CONST(0)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_HSM_EN_ENABLE                        _MK_ENUM_CONST(1)
+
+// AOCFG1 data pins schmidt enable
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_SCHMT_EN_SHIFT                       _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_SCHMT_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_SCHMT_EN_RANGE                       3:3
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_SCHMT_EN_WOFFSET                     0x0
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_SCHMT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_SCHMT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_SCHMT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_SCHMT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_SCHMT_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_SCHMT_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// AOCFG1 data pins low power mode select
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_LPMD_SHIFT                   _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_LPMD_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_LPMD_SHIFT)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_LPMD_RANGE                   5:4
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_LPMD_WOFFSET                 0x0
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_LPMD_DEFAULT                 _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_LPMD_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_LPMD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_LPMD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVDN_SHIFT                      _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVDN_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVDN_RANGE                      16:12
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVDN_WOFFSET                    0x0
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVDN_DEFAULT                    _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVDN_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVDN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVDN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVUP_SHIFT                      _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVUP_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVUP_RANGE                      24:20
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVUP_WOFFSET                    0x0
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVUP_DEFAULT                    _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVUP_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVUP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVUP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVDN_SLWR_SHIFT                 _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVDN_SLWR_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVDN_SLWR_RANGE                 29:28
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVDN_SLWR_WOFFSET                       0x0
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVDN_SLWR_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVDN_SLWR_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVDN_SLWR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVUP_SLWF_SHIFT                 _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVUP_SLWF_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVUP_SLWF_RANGE                 31:30
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVUP_SLWF_WOFFSET                       0x0
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVUP_SLWF_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVUP_SLWF_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVUP_SLWF_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_AOCFG2PADCTRL_0  //        0       rw  CFG2TMC_AOCFG2_PULLD_EN i=0x0   // AOCFG2 pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_AOCFG2_PULLU_EN i=0x0   // AOCFG2 pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_AOCFG2PADCTRL_0                     _MK_ADDR_CONST(0x86c)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_SECURE                      0x0
+#define APB_MISC_GP_AOCFG2PADCTRL_0_WORD_COUNT                  0x1
+#define APB_MISC_GP_AOCFG2PADCTRL_0_RESET_VAL                   _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_RESET_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_READ_MASK                   _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_WRITE_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+// AOCFG2 data pins high speed mode enable
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_HSM_EN_SHIFT                 _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_HSM_EN_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_HSM_EN_SHIFT)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_HSM_EN_RANGE                 2:2
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_HSM_EN_WOFFSET                       0x0
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_HSM_EN_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_HSM_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_HSM_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_HSM_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_HSM_EN_DISABLE                       _MK_ENUM_CONST(0)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_HSM_EN_ENABLE                        _MK_ENUM_CONST(1)
+
+// AOCFG2 data pins schmidt enable
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_SCHMT_EN_SHIFT                       _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_SCHMT_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_SCHMT_EN_RANGE                       3:3
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_SCHMT_EN_WOFFSET                     0x0
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_SCHMT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_SCHMT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_SCHMT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_SCHMT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_SCHMT_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_SCHMT_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// AOCFG2 data pins low power mode select
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_LPMD_SHIFT                   _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_LPMD_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_LPMD_SHIFT)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_LPMD_RANGE                   5:4
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_LPMD_WOFFSET                 0x0
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_LPMD_DEFAULT                 _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_LPMD_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_LPMD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_LPMD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVDN_SHIFT                      _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVDN_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVDN_RANGE                      16:12
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVDN_WOFFSET                    0x0
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVDN_DEFAULT                    _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVDN_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVDN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVDN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVUP_SHIFT                      _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVUP_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVUP_RANGE                      24:20
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVUP_WOFFSET                    0x0
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVUP_DEFAULT                    _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVUP_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVUP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVUP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVDN_SLWR_SHIFT                 _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVDN_SLWR_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVDN_SLWR_RANGE                 29:28
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVDN_SLWR_WOFFSET                       0x0
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVDN_SLWR_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVDN_SLWR_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVDN_SLWR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVUP_SLWF_SHIFT                 _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVUP_SLWF_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVUP_SLWF_RANGE                 31:30
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVUP_SLWF_WOFFSET                       0x0
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVUP_SLWF_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVUP_SLWF_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVUP_SLWF_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_ATCFG1PADCTRL_0  //        0       rw  CFG2TMC_ATCFG1_PULLD_EN   i=0x0   // ATCFG1 pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_ATCFG1_PULLU_EN   i=0x0   // ATCFG1 pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_ATCFG1PADCTRL_0                     _MK_ADDR_CONST(0x870)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_SECURE                      0x0
+#define APB_MISC_GP_ATCFG1PADCTRL_0_WORD_COUNT                  0x1
+#define APB_MISC_GP_ATCFG1PADCTRL_0_RESET_VAL                   _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_RESET_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_READ_MASK                   _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_WRITE_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+// ATCFG1 data pins high speed mode enable
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_HSM_EN_SHIFT                 _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_HSM_EN_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_HSM_EN_SHIFT)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_HSM_EN_RANGE                 2:2
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_HSM_EN_WOFFSET                       0x0
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_HSM_EN_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_HSM_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_HSM_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_HSM_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_HSM_EN_DISABLE                       _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_HSM_EN_ENABLE                        _MK_ENUM_CONST(1)
+
+// ATCFG1 data pins schmidt enable
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_SCHMT_EN_SHIFT                       _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_SCHMT_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_SCHMT_EN_RANGE                       3:3
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_SCHMT_EN_WOFFSET                     0x0
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_SCHMT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_SCHMT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_SCHMT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_SCHMT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_SCHMT_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_SCHMT_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// ATCFG1 data pins low power mode select
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_LPMD_SHIFT                   _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_LPMD_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_LPMD_SHIFT)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_LPMD_RANGE                   5:4
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_LPMD_WOFFSET                 0x0
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_LPMD_DEFAULT                 _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_LPMD_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_LPMD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_LPMD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVDN_SHIFT                      _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVDN_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVDN_RANGE                      16:12
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVDN_WOFFSET                    0x0
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVDN_DEFAULT                    _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVDN_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVDN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVDN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVUP_SHIFT                      _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVUP_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVUP_RANGE                      24:20
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVUP_WOFFSET                    0x0
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVUP_DEFAULT                    _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVUP_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVUP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVUP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVDN_SLWR_SHIFT                 _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVDN_SLWR_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVDN_SLWR_RANGE                 29:28
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVDN_SLWR_WOFFSET                       0x0
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVDN_SLWR_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVDN_SLWR_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVDN_SLWR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVUP_SLWF_SHIFT                 _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVUP_SLWF_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVUP_SLWF_RANGE                 31:30
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVUP_SLWF_WOFFSET                       0x0
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVUP_SLWF_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVUP_SLWF_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVUP_SLWF_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_ATCFG2PADCTRL_0  //        0       rw  CFG2TMC_ATCFG2_PULLD_EN   i=0x0   // ATCFG2 pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_ATCFG2_PULLU_EN   i=0x0   // ATCFG2 pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_ATCFG2PADCTRL_0                     _MK_ADDR_CONST(0x874)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_SECURE                      0x0
+#define APB_MISC_GP_ATCFG2PADCTRL_0_WORD_COUNT                  0x1
+#define APB_MISC_GP_ATCFG2PADCTRL_0_RESET_VAL                   _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_RESET_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_READ_MASK                   _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_WRITE_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+// ATCFG2 data pins high speed mode enable
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_HSM_EN_SHIFT                 _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_HSM_EN_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_HSM_EN_SHIFT)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_HSM_EN_RANGE                 2:2
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_HSM_EN_WOFFSET                       0x0
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_HSM_EN_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_HSM_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_HSM_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_HSM_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_HSM_EN_DISABLE                       _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_HSM_EN_ENABLE                        _MK_ENUM_CONST(1)
+
+// ATCFG2 data pins schmidt enable
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_SCHMT_EN_SHIFT                       _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_SCHMT_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_SCHMT_EN_RANGE                       3:3
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_SCHMT_EN_WOFFSET                     0x0
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_SCHMT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_SCHMT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_SCHMT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_SCHMT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_SCHMT_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_SCHMT_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// ATCFG2 data pins low power mode select
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_LPMD_SHIFT                   _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_LPMD_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_LPMD_SHIFT)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_LPMD_RANGE                   5:4
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_LPMD_WOFFSET                 0x0
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_LPMD_DEFAULT                 _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_LPMD_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_LPMD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_LPMD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVDN_SHIFT                      _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVDN_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVDN_RANGE                      16:12
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVDN_WOFFSET                    0x0
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVDN_DEFAULT                    _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVDN_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVDN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVDN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVUP_SHIFT                      _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVUP_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVUP_RANGE                      24:20
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVUP_WOFFSET                    0x0
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVUP_DEFAULT                    _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVUP_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVUP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVUP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVDN_SLWR_SHIFT                 _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVDN_SLWR_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVDN_SLWR_RANGE                 29:28
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVDN_SLWR_WOFFSET                       0x0
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVDN_SLWR_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVDN_SLWR_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVDN_SLWR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVUP_SLWF_SHIFT                 _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVUP_SLWF_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVUP_SLWF_RANGE                 31:30
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVUP_SLWF_WOFFSET                       0x0
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVUP_SLWF_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVUP_SLWF_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVUP_SLWF_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_CDEV1CFGPADCTRL_0  //        0       rw  CFG2TMC_CDEV1CFG_PULLD_EN   i=0x0   // CDEV1CFG pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_CDEV1CFG_PULLU_EN   i=0x0   // CDEV1CFG pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0                   _MK_ADDR_CONST(0x878)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_SECURE                    0x0
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_WORD_COUNT                        0x1
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_RESET_VAL                         _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_RESET_MASK                        _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_READ_MASK                         _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_WRITE_MASK                        _MK_MASK_CONST(0xf1f1f03c)
+// CDEV1CFG data pins high speed mode enable
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_HSM_EN_SHIFT                     _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_HSM_EN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_HSM_EN_SHIFT)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_HSM_EN_RANGE                     2:2
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_HSM_EN_WOFFSET                   0x0
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_HSM_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_HSM_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_HSM_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_HSM_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_HSM_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_HSM_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// CDEV1CFG data pins schmidt enable
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_SCHMT_EN_SHIFT                   _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_SCHMT_EN_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_SCHMT_EN_RANGE                   3:3
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_SCHMT_EN_WOFFSET                 0x0
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_SCHMT_EN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_SCHMT_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_SCHMT_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_SCHMT_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_SCHMT_EN_DISABLE                 _MK_ENUM_CONST(0)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_SCHMT_EN_ENABLE                  _MK_ENUM_CONST(1)
+
+// CDEV1CFG data pins low power mode select
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_LPMD_SHIFT                       _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_LPMD_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_LPMD_SHIFT)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_LPMD_RANGE                       5:4
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_LPMD_WOFFSET                     0x0
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_LPMD_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_LPMD_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_LPMD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_LPMD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVDN_SHIFT                  _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVDN_FIELD                  (_MK_MASK_CONST(0x1f) << APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVDN_RANGE                  16:12
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVDN_WOFFSET                        0x0
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVDN_DEFAULT                        _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVDN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVDN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVDN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVUP_SHIFT                  _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVUP_FIELD                  (_MK_MASK_CONST(0x1f) << APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVUP_RANGE                  24:20
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVUP_WOFFSET                        0x0
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVUP_DEFAULT                        _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVUP_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVUP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVUP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVDN_SLWR_SHIFT                     _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVDN_SLWR_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVDN_SLWR_RANGE                     29:28
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVDN_SLWR_WOFFSET                   0x0
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVDN_SLWR_DEFAULT                   _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVDN_SLWR_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVDN_SLWR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVUP_SLWF_SHIFT                     _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVUP_SLWF_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVUP_SLWF_RANGE                     31:30
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVUP_SLWF_WOFFSET                   0x0
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVUP_SLWF_DEFAULT                   _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVUP_SLWF_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVUP_SLWF_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_CDEV2CFGPADCTRL_0  //        0       rw  CFG2TMC_CDEV2CFG_PULLD_EN   i=0x0   // CDEV2CFG pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_CDEV2CFG_PULLU_EN   i=0x0   // CDEV2CFG pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0                   _MK_ADDR_CONST(0x87c)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_SECURE                    0x0
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_WORD_COUNT                        0x1
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_RESET_VAL                         _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_RESET_MASK                        _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_READ_MASK                         _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_WRITE_MASK                        _MK_MASK_CONST(0xf1f1f03c)
+// CDEV2CFG data pins high speed mode enable
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_HSM_EN_SHIFT                     _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_HSM_EN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_HSM_EN_SHIFT)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_HSM_EN_RANGE                     2:2
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_HSM_EN_WOFFSET                   0x0
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_HSM_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_HSM_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_HSM_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_HSM_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_HSM_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_HSM_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// CDEV2CFG data pins schmidt enable
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_SCHMT_EN_SHIFT                   _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_SCHMT_EN_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_SCHMT_EN_RANGE                   3:3
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_SCHMT_EN_WOFFSET                 0x0
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_SCHMT_EN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_SCHMT_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_SCHMT_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_SCHMT_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_SCHMT_EN_DISABLE                 _MK_ENUM_CONST(0)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_SCHMT_EN_ENABLE                  _MK_ENUM_CONST(1)
+
+// CDEV2CFG data pins low power mode select
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_LPMD_SHIFT                       _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_LPMD_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_LPMD_SHIFT)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_LPMD_RANGE                       5:4
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_LPMD_WOFFSET                     0x0
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_LPMD_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_LPMD_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_LPMD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_LPMD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVDN_SHIFT                  _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVDN_FIELD                  (_MK_MASK_CONST(0x1f) << APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVDN_RANGE                  16:12
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVDN_WOFFSET                        0x0
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVDN_DEFAULT                        _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVDN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVDN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVDN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVUP_SHIFT                  _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVUP_FIELD                  (_MK_MASK_CONST(0x1f) << APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVUP_RANGE                  24:20
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVUP_WOFFSET                        0x0
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVUP_DEFAULT                        _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVUP_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVUP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVUP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVDN_SLWR_SHIFT                     _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVDN_SLWR_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVDN_SLWR_RANGE                     29:28
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVDN_SLWR_WOFFSET                   0x0
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVDN_SLWR_DEFAULT                   _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVDN_SLWR_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVDN_SLWR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVUP_SLWF_SHIFT                     _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVUP_SLWF_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVUP_SLWF_RANGE                     31:30
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVUP_SLWF_WOFFSET                   0x0
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVUP_SLWF_DEFAULT                   _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVUP_SLWF_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVUP_SLWF_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_CSUSCFGPADCTRL_0  //        0       rw  CFG2TMC_CSUSCFG_PULLD_EN   i=0x0   // CSUSCFG pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_CSUSCFG_PULLU_EN   i=0x0   // CSUSCFG pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_CSUSCFGPADCTRL_0                    _MK_ADDR_CONST(0x880)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_SECURE                     0x0
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_WORD_COUNT                         0x1
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_RESET_VAL                  _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_RESET_MASK                         _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_READ_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_WRITE_MASK                         _MK_MASK_CONST(0xf1f1f03c)
+// CSUSCFG data pins high speed mode enable
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_HSM_EN_SHIFT                       _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_HSM_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_HSM_EN_SHIFT)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_HSM_EN_RANGE                       2:2
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_HSM_EN_WOFFSET                     0x0
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_HSM_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_HSM_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_HSM_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_HSM_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_HSM_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_HSM_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// CSUSCFG data pins schmidt enable
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_SCHMT_EN_SHIFT                     _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_SCHMT_EN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_SCHMT_EN_RANGE                     3:3
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_SCHMT_EN_WOFFSET                   0x0
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_SCHMT_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_SCHMT_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_SCHMT_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_SCHMT_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_SCHMT_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_SCHMT_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// CSUSCFG data pins low power mode select
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_LPMD_SHIFT                 _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_LPMD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_LPMD_SHIFT)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_LPMD_RANGE                 5:4
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_LPMD_WOFFSET                       0x0
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_LPMD_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_LPMD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_LPMD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_LPMD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVDN_SHIFT                    _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVDN_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVDN_RANGE                    16:12
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVDN_WOFFSET                  0x0
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVDN_DEFAULT                  _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVDN_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVDN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVDN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVUP_SHIFT                    _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVUP_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVUP_RANGE                    24:20
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVUP_WOFFSET                  0x0
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVUP_DEFAULT                  _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVUP_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVUP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVUP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVDN_SLWR_SHIFT                       _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVDN_SLWR_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVDN_SLWR_RANGE                       29:28
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVDN_SLWR_WOFFSET                     0x0
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVDN_SLWR_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVDN_SLWR_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVDN_SLWR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVUP_SLWF_SHIFT                       _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVUP_SLWF_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVUP_SLWF_RANGE                       31:30
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVUP_SLWF_WOFFSET                     0x0
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVUP_SLWF_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVUP_SLWF_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVUP_SLWF_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_DAP1CFGPADCTRL_0  //        0       rw  CFG2TMC_DAP1CFG_PULLD_EN   i=0x0   // DAP1CFG pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_DAP1CFG_PULLU_EN   i=0x0   // DAP1CFG pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_DAP1CFGPADCTRL_0                    _MK_ADDR_CONST(0x884)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_SECURE                     0x0
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_WORD_COUNT                         0x1
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_RESET_VAL                  _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_RESET_MASK                         _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_READ_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_WRITE_MASK                         _MK_MASK_CONST(0xf1f1f03c)
+// DAP1CFG data pins high speed mode enable
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_HSM_EN_SHIFT                       _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_HSM_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_HSM_EN_SHIFT)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_HSM_EN_RANGE                       2:2
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_HSM_EN_WOFFSET                     0x0
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_HSM_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_HSM_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_HSM_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_HSM_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_HSM_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_HSM_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// DAP1CFG data pins schmidt enable
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_SCHMT_EN_SHIFT                     _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_SCHMT_EN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_SCHMT_EN_RANGE                     3:3
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_SCHMT_EN_WOFFSET                   0x0
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_SCHMT_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_SCHMT_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_SCHMT_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_SCHMT_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_SCHMT_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_SCHMT_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// DAP1CFG data pins low power mode select
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_LPMD_SHIFT                 _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_LPMD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_LPMD_SHIFT)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_LPMD_RANGE                 5:4
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_LPMD_WOFFSET                       0x0
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_LPMD_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_LPMD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_LPMD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_LPMD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVDN_SHIFT                    _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVDN_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVDN_RANGE                    16:12
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVDN_WOFFSET                  0x0
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVDN_DEFAULT                  _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVDN_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVDN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVDN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVUP_SHIFT                    _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVUP_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVUP_RANGE                    24:20
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVUP_WOFFSET                  0x0
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVUP_DEFAULT                  _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVUP_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVUP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVUP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVDN_SLWR_SHIFT                       _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVDN_SLWR_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVDN_SLWR_RANGE                       29:28
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVDN_SLWR_WOFFSET                     0x0
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVDN_SLWR_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVDN_SLWR_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVDN_SLWR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVUP_SLWF_SHIFT                       _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVUP_SLWF_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVUP_SLWF_RANGE                       31:30
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVUP_SLWF_WOFFSET                     0x0
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVUP_SLWF_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVUP_SLWF_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVUP_SLWF_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_DAP2CFGPADCTRL_0  //        0       rw  CFG2TMC_DAP2CFG_PULLD_EN   i=0x0   // DAP2CFG pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_DAP2CFG_PULLU_EN   i=0x0   // DAP2CFG pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_DAP2CFGPADCTRL_0                    _MK_ADDR_CONST(0x888)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_SECURE                     0x0
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_WORD_COUNT                         0x1
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_RESET_VAL                  _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_RESET_MASK                         _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_READ_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_WRITE_MASK                         _MK_MASK_CONST(0xf1f1f03c)
+// DAP2CFG data pins high speed mode enable
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_HSM_EN_SHIFT                       _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_HSM_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_HSM_EN_SHIFT)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_HSM_EN_RANGE                       2:2
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_HSM_EN_WOFFSET                     0x0
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_HSM_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_HSM_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_HSM_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_HSM_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_HSM_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_HSM_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// DAP2CFG data pins schmidt enable
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_SCHMT_EN_SHIFT                     _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_SCHMT_EN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_SCHMT_EN_RANGE                     3:3
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_SCHMT_EN_WOFFSET                   0x0
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_SCHMT_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_SCHMT_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_SCHMT_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_SCHMT_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_SCHMT_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_SCHMT_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// DAP2CFG data pins low power mode select
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_LPMD_SHIFT                 _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_LPMD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_LPMD_SHIFT)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_LPMD_RANGE                 5:4
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_LPMD_WOFFSET                       0x0
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_LPMD_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_LPMD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_LPMD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_LPMD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVDN_SHIFT                    _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVDN_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVDN_RANGE                    16:12
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVDN_WOFFSET                  0x0
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVDN_DEFAULT                  _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVDN_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVDN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVDN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVUP_SHIFT                    _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVUP_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVUP_RANGE                    24:20
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVUP_WOFFSET                  0x0
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVUP_DEFAULT                  _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVUP_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVUP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVUP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVDN_SLWR_SHIFT                       _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVDN_SLWR_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVDN_SLWR_RANGE                       29:28
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVDN_SLWR_WOFFSET                     0x0
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVDN_SLWR_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVDN_SLWR_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVDN_SLWR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVUP_SLWF_SHIFT                       _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVUP_SLWF_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVUP_SLWF_RANGE                       31:30
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVUP_SLWF_WOFFSET                     0x0
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVUP_SLWF_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVUP_SLWF_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVUP_SLWF_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_DAP3CFGPADCTRL_0  //        0       rw  CFG2TMC_DAP3CFG_PULLD_EN   i=0x0   // DAP3CFG pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_DAP3CFG_PULLU_EN   i=0x0   // DAP3CFG pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_DAP3CFGPADCTRL_0                    _MK_ADDR_CONST(0x88c)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_SECURE                     0x0
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_WORD_COUNT                         0x1
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_RESET_VAL                  _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_RESET_MASK                         _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_READ_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_WRITE_MASK                         _MK_MASK_CONST(0xf1f1f03c)
+// DAP3CFG data pins high speed mode enable
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_HSM_EN_SHIFT                       _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_HSM_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_HSM_EN_SHIFT)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_HSM_EN_RANGE                       2:2
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_HSM_EN_WOFFSET                     0x0
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_HSM_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_HSM_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_HSM_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_HSM_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_HSM_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_HSM_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// DAP3CFG data pins schmidt enable
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_SCHMT_EN_SHIFT                     _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_SCHMT_EN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_SCHMT_EN_RANGE                     3:3
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_SCHMT_EN_WOFFSET                   0x0
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_SCHMT_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_SCHMT_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_SCHMT_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_SCHMT_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_SCHMT_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_SCHMT_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// DAP3CFG data pins low power mode select
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_LPMD_SHIFT                 _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_LPMD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_LPMD_SHIFT)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_LPMD_RANGE                 5:4
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_LPMD_WOFFSET                       0x0
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_LPMD_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_LPMD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_LPMD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_LPMD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVDN_SHIFT                    _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVDN_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVDN_RANGE                    16:12
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVDN_WOFFSET                  0x0
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVDN_DEFAULT                  _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVDN_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVDN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVDN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVUP_SHIFT                    _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVUP_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVUP_RANGE                    24:20
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVUP_WOFFSET                  0x0
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVUP_DEFAULT                  _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVUP_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVUP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVUP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVDN_SLWR_SHIFT                       _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVDN_SLWR_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVDN_SLWR_RANGE                       29:28
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVDN_SLWR_WOFFSET                     0x0
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVDN_SLWR_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVDN_SLWR_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVDN_SLWR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVUP_SLWF_SHIFT                       _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVUP_SLWF_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVUP_SLWF_RANGE                       31:30
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVUP_SLWF_WOFFSET                     0x0
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVUP_SLWF_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVUP_SLWF_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVUP_SLWF_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_DAP4CFGPADCTRL_0  //        0       rw  CFG2TMC_DAP4CFG_PULLD_EN   i=0x0   // DAP4CFG pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_DAP4CFG_PULLU_EN   i=0x0   // DAP4CFG pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_DAP4CFGPADCTRL_0                    _MK_ADDR_CONST(0x890)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_SECURE                     0x0
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_WORD_COUNT                         0x1
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_RESET_VAL                  _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_RESET_MASK                         _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_READ_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_WRITE_MASK                         _MK_MASK_CONST(0xf1f1f03c)
+// DAP4CFG data pins high speed mode enable
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_HSM_EN_SHIFT                       _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_HSM_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_HSM_EN_SHIFT)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_HSM_EN_RANGE                       2:2
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_HSM_EN_WOFFSET                     0x0
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_HSM_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_HSM_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_HSM_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_HSM_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_HSM_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_HSM_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// DAP4CFG data pins schmidt enable
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_SCHMT_EN_SHIFT                     _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_SCHMT_EN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_SCHMT_EN_RANGE                     3:3
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_SCHMT_EN_WOFFSET                   0x0
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_SCHMT_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_SCHMT_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_SCHMT_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_SCHMT_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_SCHMT_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_SCHMT_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// DAP4CFG data pins low power mode select
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_LPMD_SHIFT                 _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_LPMD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_LPMD_SHIFT)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_LPMD_RANGE                 5:4
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_LPMD_WOFFSET                       0x0
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_LPMD_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_LPMD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_LPMD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_LPMD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVDN_SHIFT                    _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVDN_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVDN_RANGE                    16:12
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVDN_WOFFSET                  0x0
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVDN_DEFAULT                  _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVDN_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVDN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVDN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVUP_SHIFT                    _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVUP_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVUP_RANGE                    24:20
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVUP_WOFFSET                  0x0
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVUP_DEFAULT                  _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVUP_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVUP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVUP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVDN_SLWR_SHIFT                       _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVDN_SLWR_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVDN_SLWR_RANGE                       29:28
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVDN_SLWR_WOFFSET                     0x0
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVDN_SLWR_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVDN_SLWR_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVDN_SLWR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVUP_SLWF_SHIFT                       _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVUP_SLWF_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVUP_SLWF_RANGE                       31:30
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVUP_SLWF_WOFFSET                     0x0
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVUP_SLWF_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVUP_SLWF_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVUP_SLWF_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_DBGCFGPADCTRL_0  //        0       rw  CFG2TMC_DBGCFG_PULLD_EN   i=0x0   // DBGCFG pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_DBGCFG_PULLU_EN   i=0x0   // DBGCFG pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_DBGCFGPADCTRL_0                     _MK_ADDR_CONST(0x894)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_SECURE                      0x0
+#define APB_MISC_GP_DBGCFGPADCTRL_0_WORD_COUNT                  0x1
+#define APB_MISC_GP_DBGCFGPADCTRL_0_RESET_VAL                   _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_RESET_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_READ_MASK                   _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_WRITE_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+// DBGCFG data pins high speed mode enable
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_HSM_EN_SHIFT                 _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_HSM_EN_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_HSM_EN_SHIFT)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_HSM_EN_RANGE                 2:2
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_HSM_EN_WOFFSET                       0x0
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_HSM_EN_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_HSM_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_HSM_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_HSM_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_HSM_EN_DISABLE                       _MK_ENUM_CONST(0)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_HSM_EN_ENABLE                        _MK_ENUM_CONST(1)
+
+// DBGCFG data pins schmidt enable
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_SCHMT_EN_SHIFT                       _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_SCHMT_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_SCHMT_EN_RANGE                       3:3
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_SCHMT_EN_WOFFSET                     0x0
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_SCHMT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_SCHMT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_SCHMT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_SCHMT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_SCHMT_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_SCHMT_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// DBGCFG data pins low power mode select
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_LPMD_SHIFT                   _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_LPMD_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_LPMD_SHIFT)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_LPMD_RANGE                   5:4
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_LPMD_WOFFSET                 0x0
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_LPMD_DEFAULT                 _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_LPMD_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_LPMD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_LPMD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVDN_SHIFT                      _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVDN_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVDN_RANGE                      16:12
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVDN_WOFFSET                    0x0
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVDN_DEFAULT                    _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVDN_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVDN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVDN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVUP_SHIFT                      _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVUP_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVUP_RANGE                      24:20
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVUP_WOFFSET                    0x0
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVUP_DEFAULT                    _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVUP_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVUP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVUP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVDN_SLWR_SHIFT                 _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVDN_SLWR_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVDN_SLWR_RANGE                 29:28
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVDN_SLWR_WOFFSET                       0x0
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVDN_SLWR_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVDN_SLWR_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVDN_SLWR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVUP_SLWF_SHIFT                 _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVUP_SLWF_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVUP_SLWF_RANGE                 31:30
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVUP_SLWF_WOFFSET                       0x0
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVUP_SLWF_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVUP_SLWF_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVUP_SLWF_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_LCDCFG1PADCTRL_0  //        0       rw  CFG2TMC_LCDCFG1_PULLD_EN   i=0x0   // LCDCFG1 pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_LCDCFG1_PULLU_EN   i=0x0   // LCDCFG1 pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_LCDCFG1PADCTRL_0                    _MK_ADDR_CONST(0x898)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_SECURE                     0x0
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_WORD_COUNT                         0x1
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_RESET_VAL                  _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_RESET_MASK                         _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_READ_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_WRITE_MASK                         _MK_MASK_CONST(0xf1f1f03c)
+// LCDCFG1 data pins high speed mode enable
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_HSM_EN_SHIFT                       _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_HSM_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_HSM_EN_SHIFT)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_HSM_EN_RANGE                       2:2
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_HSM_EN_WOFFSET                     0x0
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_HSM_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_HSM_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_HSM_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_HSM_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_HSM_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_HSM_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// LCDCFG1 data pins schmidt enable
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_SCHMT_EN_SHIFT                     _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_SCHMT_EN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_SCHMT_EN_RANGE                     3:3
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_SCHMT_EN_WOFFSET                   0x0
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_SCHMT_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_SCHMT_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_SCHMT_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_SCHMT_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_SCHMT_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_SCHMT_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// LCDCFG1 data pins low power mode select
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_LPMD_SHIFT                 _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_LPMD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_LPMD_SHIFT)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_LPMD_RANGE                 5:4
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_LPMD_WOFFSET                       0x0
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_LPMD_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_LPMD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_LPMD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_LPMD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVDN_SHIFT                    _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVDN_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVDN_RANGE                    16:12
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVDN_WOFFSET                  0x0
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVDN_DEFAULT                  _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVDN_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVDN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVDN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVUP_SHIFT                    _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVUP_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVUP_RANGE                    24:20
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVUP_WOFFSET                  0x0
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVUP_DEFAULT                  _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVUP_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVUP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVUP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVDN_SLWR_SHIFT                       _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVDN_SLWR_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVDN_SLWR_RANGE                       29:28
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVDN_SLWR_WOFFSET                     0x0
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVDN_SLWR_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVDN_SLWR_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVDN_SLWR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVUP_SLWF_SHIFT                       _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVUP_SLWF_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVUP_SLWF_RANGE                       31:30
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVUP_SLWF_WOFFSET                     0x0
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVUP_SLWF_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVUP_SLWF_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVUP_SLWF_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_LCDCFG2PADCTRL_0  //        0       rw  CFG2TMC_LCDCFG2_PULLD_EN   i=0x0   // LCDCFG2 pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_LCDCFG2_PULLU_EN   i=0x0   // LCDCFG2 pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_LCDCFG2PADCTRL_0                    _MK_ADDR_CONST(0x89c)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_SECURE                     0x0
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_WORD_COUNT                         0x1
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_RESET_VAL                  _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_RESET_MASK                         _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_READ_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_WRITE_MASK                         _MK_MASK_CONST(0xf1f1f03c)
+// LCDCFG2 data pins high speed mode enable
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_HSM_EN_SHIFT                       _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_HSM_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_HSM_EN_SHIFT)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_HSM_EN_RANGE                       2:2
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_HSM_EN_WOFFSET                     0x0
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_HSM_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_HSM_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_HSM_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_HSM_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_HSM_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_HSM_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// LCDCFG2 data pins schmidt enable
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_SCHMT_EN_SHIFT                     _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_SCHMT_EN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_SCHMT_EN_RANGE                     3:3
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_SCHMT_EN_WOFFSET                   0x0
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_SCHMT_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_SCHMT_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_SCHMT_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_SCHMT_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_SCHMT_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_SCHMT_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// LCDCFG2 data pins low power mode select
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_LPMD_SHIFT                 _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_LPMD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_LPMD_SHIFT)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_LPMD_RANGE                 5:4
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_LPMD_WOFFSET                       0x0
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_LPMD_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_LPMD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_LPMD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_LPMD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVDN_SHIFT                    _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVDN_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVDN_RANGE                    16:12
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVDN_WOFFSET                  0x0
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVDN_DEFAULT                  _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVDN_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVDN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVDN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVUP_SHIFT                    _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVUP_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVUP_RANGE                    24:20
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVUP_WOFFSET                  0x0
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVUP_DEFAULT                  _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVUP_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVUP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVUP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVDN_SLWR_SHIFT                       _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVDN_SLWR_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVDN_SLWR_RANGE                       29:28
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVDN_SLWR_WOFFSET                     0x0
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVDN_SLWR_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVDN_SLWR_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVDN_SLWR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVUP_SLWF_SHIFT                       _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVUP_SLWF_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVUP_SLWF_RANGE                       31:30
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVUP_SLWF_WOFFSET                     0x0
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVUP_SLWF_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVUP_SLWF_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVUP_SLWF_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_SDIO2CFGPADCTRL_0  //        0       rw  CFG2TMC_SDIO2CFG_PULLD_EN   i=0x0   // SDIO2CFG pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_SDIO2CFG_PULLU_EN   i=0x0   // SDIO2CFG pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0                   _MK_ADDR_CONST(0x8a0)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_SECURE                    0x0
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_WORD_COUNT                        0x1
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_RESET_VAL                         _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_RESET_MASK                        _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_READ_MASK                         _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_WRITE_MASK                        _MK_MASK_CONST(0xf1f1f03c)
+// SDIO2CFG data pins high speed mode enable
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_HSM_EN_SHIFT                     _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_HSM_EN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_HSM_EN_SHIFT)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_HSM_EN_RANGE                     2:2
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_HSM_EN_WOFFSET                   0x0
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_HSM_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_HSM_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_HSM_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_HSM_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_HSM_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_HSM_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// SDIO2CFG data pins schmidt enable
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_SCHMT_EN_SHIFT                   _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_SCHMT_EN_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_SCHMT_EN_RANGE                   3:3
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_SCHMT_EN_WOFFSET                 0x0
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_SCHMT_EN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_SCHMT_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_SCHMT_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_SCHMT_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_SCHMT_EN_DISABLE                 _MK_ENUM_CONST(0)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_SCHMT_EN_ENABLE                  _MK_ENUM_CONST(1)
+
+// SDIO2CFG data pins low power mode select
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_LPMD_SHIFT                       _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_LPMD_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_LPMD_SHIFT)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_LPMD_RANGE                       5:4
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_LPMD_WOFFSET                     0x0
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_LPMD_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_LPMD_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_LPMD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_LPMD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVDN_SHIFT                  _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVDN_FIELD                  (_MK_MASK_CONST(0x1f) << APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVDN_RANGE                  16:12
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVDN_WOFFSET                        0x0
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVDN_DEFAULT                        _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVDN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVDN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVDN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVUP_SHIFT                  _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVUP_FIELD                  (_MK_MASK_CONST(0x1f) << APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVUP_RANGE                  24:20
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVUP_WOFFSET                        0x0
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVUP_DEFAULT                        _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVUP_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVUP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVUP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVDN_SLWR_SHIFT                     _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVDN_SLWR_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVDN_SLWR_RANGE                     29:28
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVDN_SLWR_WOFFSET                   0x0
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVDN_SLWR_DEFAULT                   _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVDN_SLWR_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVDN_SLWR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVUP_SLWF_SHIFT                     _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVUP_SLWF_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVUP_SLWF_RANGE                     31:30
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVUP_SLWF_WOFFSET                   0x0
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVUP_SLWF_DEFAULT                   _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVUP_SLWF_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVUP_SLWF_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_SDIO3CFGPADCTRL_0  //        0       rw  CFG2TMC_SDIO3CFG_PULLD_EN   i=0x0   // SDIO3CFG pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_SDIO3CFG_PULLU_EN   i=0x0   // SDIO3CFG pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0                   _MK_ADDR_CONST(0x8a4)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_SECURE                    0x0
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_WORD_COUNT                        0x1
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_RESET_VAL                         _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_RESET_MASK                        _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_READ_MASK                         _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_WRITE_MASK                        _MK_MASK_CONST(0xf1f1f03c)
+// SDIO3CFG data pins high speed mode enable
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_HSM_EN_SHIFT                     _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_HSM_EN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_HSM_EN_SHIFT)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_HSM_EN_RANGE                     2:2
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_HSM_EN_WOFFSET                   0x0
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_HSM_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_HSM_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_HSM_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_HSM_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_HSM_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_HSM_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// SDIO3CFG data pins schmidt enable
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_SCHMT_EN_SHIFT                   _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_SCHMT_EN_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_SCHMT_EN_RANGE                   3:3
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_SCHMT_EN_WOFFSET                 0x0
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_SCHMT_EN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_SCHMT_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_SCHMT_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_SCHMT_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_SCHMT_EN_DISABLE                 _MK_ENUM_CONST(0)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_SCHMT_EN_ENABLE                  _MK_ENUM_CONST(1)
+
+// SDIO3CFG data pins low power mode select
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_LPMD_SHIFT                       _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_LPMD_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_LPMD_SHIFT)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_LPMD_RANGE                       5:4
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_LPMD_WOFFSET                     0x0
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_LPMD_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_LPMD_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_LPMD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_LPMD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVDN_SHIFT                  _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVDN_FIELD                  (_MK_MASK_CONST(0x1f) << APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVDN_RANGE                  16:12
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVDN_WOFFSET                        0x0
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVDN_DEFAULT                        _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVDN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVDN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVDN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVUP_SHIFT                  _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVUP_FIELD                  (_MK_MASK_CONST(0x1f) << APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVUP_RANGE                  24:20
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVUP_WOFFSET                        0x0
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVUP_DEFAULT                        _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVUP_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVUP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVUP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVDN_SLWR_SHIFT                     _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVDN_SLWR_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVDN_SLWR_RANGE                     29:28
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVDN_SLWR_WOFFSET                   0x0
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVDN_SLWR_DEFAULT                   _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVDN_SLWR_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVDN_SLWR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVUP_SLWF_SHIFT                     _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVUP_SLWF_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVUP_SLWF_RANGE                     31:30
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVUP_SLWF_WOFFSET                   0x0
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVUP_SLWF_DEFAULT                   _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVUP_SLWF_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVUP_SLWF_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_SPICFGPADCTRL_0  //        0       rw  CFG2TMC_SPICFG_PULLD_EN   i=0x0   // SPICFG pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_SPICFG_PULLU_EN   i=0x0   // SPICFG pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_SPICFGPADCTRL_0                     _MK_ADDR_CONST(0x8a8)
+#define APB_MISC_GP_SPICFGPADCTRL_0_SECURE                      0x0
+#define APB_MISC_GP_SPICFGPADCTRL_0_WORD_COUNT                  0x1
+#define APB_MISC_GP_SPICFGPADCTRL_0_RESET_VAL                   _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_SPICFGPADCTRL_0_RESET_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_SPICFGPADCTRL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SPICFGPADCTRL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SPICFGPADCTRL_0_READ_MASK                   _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_SPICFGPADCTRL_0_WRITE_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+// SPICFG data pins high speed mode enable
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_HSM_EN_SHIFT                 _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_HSM_EN_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_HSM_EN_SHIFT)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_HSM_EN_RANGE                 2:2
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_HSM_EN_WOFFSET                       0x0
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_HSM_EN_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_HSM_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_HSM_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_HSM_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_HSM_EN_DISABLE                       _MK_ENUM_CONST(0)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_HSM_EN_ENABLE                        _MK_ENUM_CONST(1)
+
+// SPICFG data pins schmidt enable
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_SCHMT_EN_SHIFT                       _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_SCHMT_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_SCHMT_EN_RANGE                       3:3
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_SCHMT_EN_WOFFSET                     0x0
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_SCHMT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_SCHMT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_SCHMT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_SCHMT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_SCHMT_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_SCHMT_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// SPICFG data pins low power mode select
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_LPMD_SHIFT                   _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_LPMD_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_LPMD_SHIFT)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_LPMD_RANGE                   5:4
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_LPMD_WOFFSET                 0x0
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_LPMD_DEFAULT                 _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_LPMD_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_LPMD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_LPMD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVDN_SHIFT                      _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVDN_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVDN_RANGE                      16:12
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVDN_WOFFSET                    0x0
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVDN_DEFAULT                    _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVDN_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVDN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVDN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVUP_SHIFT                      _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVUP_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVUP_RANGE                      24:20
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVUP_WOFFSET                    0x0
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVUP_DEFAULT                    _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVUP_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVUP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVUP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVDN_SLWR_SHIFT                 _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVDN_SLWR_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVDN_SLWR_RANGE                 29:28
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVDN_SLWR_WOFFSET                       0x0
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVDN_SLWR_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVDN_SLWR_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVDN_SLWR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVUP_SLWF_SHIFT                 _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVUP_SLWF_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVUP_SLWF_RANGE                 31:30
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVUP_SLWF_WOFFSET                       0x0
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVUP_SLWF_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVUP_SLWF_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVUP_SLWF_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_UAACFGPADCTRL_0  //        0       rw  CFG2TMC_UAACFG_PULLD_EN   i=0x0   // UAACFG pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_UAACFG_PULLU_EN   i=0x0   // UAACFG pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_UAACFGPADCTRL_0                     _MK_ADDR_CONST(0x8ac)
+#define APB_MISC_GP_UAACFGPADCTRL_0_SECURE                      0x0
+#define APB_MISC_GP_UAACFGPADCTRL_0_WORD_COUNT                  0x1
+#define APB_MISC_GP_UAACFGPADCTRL_0_RESET_VAL                   _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_UAACFGPADCTRL_0_RESET_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_UAACFGPADCTRL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UAACFGPADCTRL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UAACFGPADCTRL_0_READ_MASK                   _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_UAACFGPADCTRL_0_WRITE_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+// UAACFG data pins high speed mode enable
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_HSM_EN_SHIFT                 _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_HSM_EN_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_HSM_EN_SHIFT)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_HSM_EN_RANGE                 2:2
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_HSM_EN_WOFFSET                       0x0
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_HSM_EN_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_HSM_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_HSM_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_HSM_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_HSM_EN_DISABLE                       _MK_ENUM_CONST(0)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_HSM_EN_ENABLE                        _MK_ENUM_CONST(1)
+
+// UAACFG data pins schmidt enable
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_SCHMT_EN_SHIFT                       _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_SCHMT_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_SCHMT_EN_RANGE                       3:3
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_SCHMT_EN_WOFFSET                     0x0
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_SCHMT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_SCHMT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_SCHMT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_SCHMT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_SCHMT_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_SCHMT_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// UAACFG data pins low power mode select
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_LPMD_SHIFT                   _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_LPMD_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_LPMD_SHIFT)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_LPMD_RANGE                   5:4
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_LPMD_WOFFSET                 0x0
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_LPMD_DEFAULT                 _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_LPMD_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_LPMD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_LPMD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVDN_SHIFT                      _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVDN_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVDN_RANGE                      16:12
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVDN_WOFFSET                    0x0
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVDN_DEFAULT                    _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVDN_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVDN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVDN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVUP_SHIFT                      _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVUP_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVUP_RANGE                      24:20
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVUP_WOFFSET                    0x0
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVUP_DEFAULT                    _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVUP_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVUP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVUP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVDN_SLWR_SHIFT                 _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVDN_SLWR_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVDN_SLWR_RANGE                 29:28
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVDN_SLWR_WOFFSET                       0x0
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVDN_SLWR_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVDN_SLWR_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVDN_SLWR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVUP_SLWF_SHIFT                 _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVUP_SLWF_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVUP_SLWF_RANGE                 31:30
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVUP_SLWF_WOFFSET                       0x0
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVUP_SLWF_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVUP_SLWF_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVUP_SLWF_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_UABCFGPADCTRL_0  //        0       rw  CFG2TMC_UABCFG_PULLD_EN   i=0x0   // UABCFG pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_UABCFG_PULLU_EN   i=0x0   // UABCFG pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_UABCFGPADCTRL_0                     _MK_ADDR_CONST(0x8b0)
+#define APB_MISC_GP_UABCFGPADCTRL_0_SECURE                      0x0
+#define APB_MISC_GP_UABCFGPADCTRL_0_WORD_COUNT                  0x1
+#define APB_MISC_GP_UABCFGPADCTRL_0_RESET_VAL                   _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_UABCFGPADCTRL_0_RESET_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_UABCFGPADCTRL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UABCFGPADCTRL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UABCFGPADCTRL_0_READ_MASK                   _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_UABCFGPADCTRL_0_WRITE_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+// UABCFG data pins high speed mode enable
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_HSM_EN_SHIFT                 _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_HSM_EN_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_HSM_EN_SHIFT)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_HSM_EN_RANGE                 2:2
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_HSM_EN_WOFFSET                       0x0
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_HSM_EN_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_HSM_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_HSM_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_HSM_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_HSM_EN_DISABLE                       _MK_ENUM_CONST(0)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_HSM_EN_ENABLE                        _MK_ENUM_CONST(1)
+
+// UABCFG data pins schmidt enable
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_SCHMT_EN_SHIFT                       _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_SCHMT_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_SCHMT_EN_RANGE                       3:3
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_SCHMT_EN_WOFFSET                     0x0
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_SCHMT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_SCHMT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_SCHMT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_SCHMT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_SCHMT_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_SCHMT_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// UABCFG data pins low power mode select
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_LPMD_SHIFT                   _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_LPMD_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_LPMD_SHIFT)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_LPMD_RANGE                   5:4
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_LPMD_WOFFSET                 0x0
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_LPMD_DEFAULT                 _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_LPMD_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_LPMD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_LPMD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVDN_SHIFT                      _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVDN_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVDN_RANGE                      16:12
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVDN_WOFFSET                    0x0
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVDN_DEFAULT                    _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVDN_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVDN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVDN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVUP_SHIFT                      _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVUP_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVUP_RANGE                      24:20
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVUP_WOFFSET                    0x0
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVUP_DEFAULT                    _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVUP_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVUP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVUP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVDN_SLWR_SHIFT                 _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVDN_SLWR_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVDN_SLWR_RANGE                 29:28
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVDN_SLWR_WOFFSET                       0x0
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVDN_SLWR_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVDN_SLWR_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVDN_SLWR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVUP_SLWF_SHIFT                 _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVUP_SLWF_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVUP_SLWF_RANGE                 31:30
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVUP_SLWF_WOFFSET                       0x0
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVUP_SLWF_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVUP_SLWF_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVUP_SLWF_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_UART2CFGPADCTRL_0  //        0       rw  CFG2TMC_UART2CFG_PULLD_EN   i=0x0   // UART2CFG pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_UART2CFG_PULLU_EN   i=0x0   // UART2CFG pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_UART2CFGPADCTRL_0                   _MK_ADDR_CONST(0x8b4)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_SECURE                    0x0
+#define APB_MISC_GP_UART2CFGPADCTRL_0_WORD_COUNT                        0x1
+#define APB_MISC_GP_UART2CFGPADCTRL_0_RESET_VAL                         _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_RESET_MASK                        _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_READ_MASK                         _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_WRITE_MASK                        _MK_MASK_CONST(0xf1f1f03c)
+// UART2CFG data pins high speed mode enable
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_HSM_EN_SHIFT                     _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_HSM_EN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_HSM_EN_SHIFT)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_HSM_EN_RANGE                     2:2
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_HSM_EN_WOFFSET                   0x0
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_HSM_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_HSM_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_HSM_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_HSM_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_HSM_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_HSM_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// UART2CFG data pins schmidt enable
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_SCHMT_EN_SHIFT                   _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_SCHMT_EN_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_SCHMT_EN_RANGE                   3:3
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_SCHMT_EN_WOFFSET                 0x0
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_SCHMT_EN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_SCHMT_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_SCHMT_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_SCHMT_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_SCHMT_EN_DISABLE                 _MK_ENUM_CONST(0)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_SCHMT_EN_ENABLE                  _MK_ENUM_CONST(1)
+
+// UART2CFG data pins low power mode select
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_LPMD_SHIFT                       _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_LPMD_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_LPMD_SHIFT)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_LPMD_RANGE                       5:4
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_LPMD_WOFFSET                     0x0
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_LPMD_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_LPMD_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_LPMD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_LPMD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVDN_SHIFT                  _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVDN_FIELD                  (_MK_MASK_CONST(0x1f) << APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVDN_RANGE                  16:12
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVDN_WOFFSET                        0x0
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVDN_DEFAULT                        _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVDN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVDN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVDN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVUP_SHIFT                  _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVUP_FIELD                  (_MK_MASK_CONST(0x1f) << APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVUP_RANGE                  24:20
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVUP_WOFFSET                        0x0
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVUP_DEFAULT                        _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVUP_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVUP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVUP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVDN_SLWR_SHIFT                     _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVDN_SLWR_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVDN_SLWR_RANGE                     29:28
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVDN_SLWR_WOFFSET                   0x0
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVDN_SLWR_DEFAULT                   _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVDN_SLWR_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVDN_SLWR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVUP_SLWF_SHIFT                     _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVUP_SLWF_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVUP_SLWF_RANGE                     31:30
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVUP_SLWF_WOFFSET                   0x0
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVUP_SLWF_DEFAULT                   _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVUP_SLWF_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVUP_SLWF_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_UART3CFGPADCTRL_0  //        0       rw  CFG2TMC_UART3CFG_PULLD_EN   i=0x0   // UART3CFG pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_UART3CFG_PULLU_EN   i=0x0   // UART3CFG pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_UART3CFGPADCTRL_0                   _MK_ADDR_CONST(0x8b8)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_SECURE                    0x0
+#define APB_MISC_GP_UART3CFGPADCTRL_0_WORD_COUNT                        0x1
+#define APB_MISC_GP_UART3CFGPADCTRL_0_RESET_VAL                         _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_RESET_MASK                        _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_READ_MASK                         _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_WRITE_MASK                        _MK_MASK_CONST(0xf1f1f03c)
+// UART3CFG data pins high speed mode enable
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_HSM_EN_SHIFT                     _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_HSM_EN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_HSM_EN_SHIFT)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_HSM_EN_RANGE                     2:2
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_HSM_EN_WOFFSET                   0x0
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_HSM_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_HSM_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_HSM_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_HSM_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_HSM_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_HSM_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// UART3CFG data pins schmidt enable
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_SCHMT_EN_SHIFT                   _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_SCHMT_EN_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_SCHMT_EN_RANGE                   3:3
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_SCHMT_EN_WOFFSET                 0x0
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_SCHMT_EN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_SCHMT_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_SCHMT_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_SCHMT_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_SCHMT_EN_DISABLE                 _MK_ENUM_CONST(0)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_SCHMT_EN_ENABLE                  _MK_ENUM_CONST(1)
+
+// UART3CFG data pins low power mode select
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_LPMD_SHIFT                       _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_LPMD_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_LPMD_SHIFT)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_LPMD_RANGE                       5:4
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_LPMD_WOFFSET                     0x0
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_LPMD_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_LPMD_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_LPMD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_LPMD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVDN_SHIFT                  _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVDN_FIELD                  (_MK_MASK_CONST(0x1f) << APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVDN_RANGE                  16:12
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVDN_WOFFSET                        0x0
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVDN_DEFAULT                        _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVDN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVDN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVDN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVUP_SHIFT                  _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVUP_FIELD                  (_MK_MASK_CONST(0x1f) << APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVUP_RANGE                  24:20
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVUP_WOFFSET                        0x0
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVUP_DEFAULT                        _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVUP_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVUP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVUP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVDN_SLWR_SHIFT                     _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVDN_SLWR_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVDN_SLWR_RANGE                     29:28
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVDN_SLWR_WOFFSET                   0x0
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVDN_SLWR_DEFAULT                   _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVDN_SLWR_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVDN_SLWR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVUP_SLWF_SHIFT                     _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVUP_SLWF_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVUP_SLWF_RANGE                     31:30
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVUP_SLWF_WOFFSET                   0x0
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVUP_SLWF_DEFAULT                   _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVUP_SLWF_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVUP_SLWF_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_VICFG1PADCTRL_0  //        0       rw  CFG2TMC_VICFG1_PULLD_EN   i=0x0   // VICFG1 pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_VICFG1_PULLU_EN   i=0x0   // VICFG1 pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_VICFG1PADCTRL_0                     _MK_ADDR_CONST(0x8bc)
+#define APB_MISC_GP_VICFG1PADCTRL_0_SECURE                      0x0
+#define APB_MISC_GP_VICFG1PADCTRL_0_WORD_COUNT                  0x1
+#define APB_MISC_GP_VICFG1PADCTRL_0_RESET_VAL                   _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_VICFG1PADCTRL_0_RESET_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_VICFG1PADCTRL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG1PADCTRL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG1PADCTRL_0_READ_MASK                   _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_VICFG1PADCTRL_0_WRITE_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+// VICFG1 data pins high speed mode enable
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_HSM_EN_SHIFT                 _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_HSM_EN_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_HSM_EN_SHIFT)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_HSM_EN_RANGE                 2:2
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_HSM_EN_WOFFSET                       0x0
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_HSM_EN_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_HSM_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_HSM_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_HSM_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_HSM_EN_DISABLE                       _MK_ENUM_CONST(0)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_HSM_EN_ENABLE                        _MK_ENUM_CONST(1)
+
+// VICFG1 data pins schmidt enable
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_SCHMT_EN_SHIFT                       _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_SCHMT_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_SCHMT_EN_RANGE                       3:3
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_SCHMT_EN_WOFFSET                     0x0
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_SCHMT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_SCHMT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_SCHMT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_SCHMT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_SCHMT_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_SCHMT_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// VICFG1 data pins low power mode select
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_LPMD_SHIFT                   _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_LPMD_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_LPMD_SHIFT)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_LPMD_RANGE                   5:4
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_LPMD_WOFFSET                 0x0
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_LPMD_DEFAULT                 _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_LPMD_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_LPMD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_LPMD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVDN_SHIFT                      _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVDN_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVDN_RANGE                      16:12
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVDN_WOFFSET                    0x0
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVDN_DEFAULT                    _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVDN_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVDN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVDN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVUP_SHIFT                      _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVUP_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVUP_RANGE                      24:20
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVUP_WOFFSET                    0x0
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVUP_DEFAULT                    _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVUP_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVUP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVUP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVDN_SLWR_SHIFT                 _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVDN_SLWR_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVDN_SLWR_RANGE                 29:28
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVDN_SLWR_WOFFSET                       0x0
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVDN_SLWR_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVDN_SLWR_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVDN_SLWR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVUP_SLWF_SHIFT                 _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVUP_SLWF_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVUP_SLWF_RANGE                 31:30
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVUP_SLWF_WOFFSET                       0x0
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVUP_SLWF_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVUP_SLWF_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVUP_SLWF_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_VICFG2PADCTRL_0  //        0       rw  CFG2TMC_VICFG2_PULLD_EN   i=0x0   // VICFG2 pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_VICFG2_PULLU_EN   i=0x0   // VICFG2 pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_VICFG2PADCTRL_0                     _MK_ADDR_CONST(0x8c0)
+#define APB_MISC_GP_VICFG2PADCTRL_0_SECURE                      0x0
+#define APB_MISC_GP_VICFG2PADCTRL_0_WORD_COUNT                  0x1
+#define APB_MISC_GP_VICFG2PADCTRL_0_RESET_VAL                   _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_VICFG2PADCTRL_0_RESET_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_VICFG2PADCTRL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG2PADCTRL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG2PADCTRL_0_READ_MASK                   _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_VICFG2PADCTRL_0_WRITE_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+// VICFG2 data pins high speed mode enable
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_HSM_EN_SHIFT                 _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_HSM_EN_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_HSM_EN_SHIFT)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_HSM_EN_RANGE                 2:2
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_HSM_EN_WOFFSET                       0x0
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_HSM_EN_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_HSM_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_HSM_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_HSM_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_HSM_EN_DISABLE                       _MK_ENUM_CONST(0)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_HSM_EN_ENABLE                        _MK_ENUM_CONST(1)
+
+// VICFG2 data pins schmidt enable
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_SCHMT_EN_SHIFT                       _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_SCHMT_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_SCHMT_EN_RANGE                       3:3
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_SCHMT_EN_WOFFSET                     0x0
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_SCHMT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_SCHMT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_SCHMT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_SCHMT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_SCHMT_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_SCHMT_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// VICFG2 data pins low power mode select
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_LPMD_SHIFT                   _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_LPMD_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_LPMD_SHIFT)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_LPMD_RANGE                   5:4
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_LPMD_WOFFSET                 0x0
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_LPMD_DEFAULT                 _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_LPMD_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_LPMD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_LPMD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVDN_SHIFT                      _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVDN_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVDN_RANGE                      16:12
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVDN_WOFFSET                    0x0
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVDN_DEFAULT                    _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVDN_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVDN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVDN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVUP_SHIFT                      _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVUP_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVUP_RANGE                      24:20
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVUP_WOFFSET                    0x0
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVUP_DEFAULT                    _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVUP_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVUP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVUP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVDN_SLWR_SHIFT                 _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVDN_SLWR_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVDN_SLWR_RANGE                 29:28
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVDN_SLWR_WOFFSET                       0x0
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVDN_SLWR_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVDN_SLWR_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVDN_SLWR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVUP_SLWF_SHIFT                 _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVUP_SLWF_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVUP_SLWF_RANGE                 31:30
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVUP_SLWF_WOFFSET                       0x0
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVUP_SLWF_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVUP_SLWF_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVUP_SLWF_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_XM2CFGAPADCTRL_0  //        0       rw  CFG2TMC_XM2CFGA_PULLD_EN   i=0x0 // XM2CFGA pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_XM2CFGA_PULLU_EN i=0x0   // XM2CFGA pullup mode enable
+//            enum ( DISABLE, ENABLE )
+//        3       rw  CFG2TMC_XM2CFGA_RX_FT_REC_EN i=0x0   
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_XM2CFGAPADCTRL_0                    _MK_ADDR_CONST(0x8c4)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_SECURE                     0x0
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_WORD_COUNT                         0x1
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_RESET_VAL                  _MK_MASK_CONST(0xffffc000)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_RESET_MASK                         _MK_MASK_CONST(0xffffc070)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_READ_MASK                  _MK_MASK_CONST(0xffffc070)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_WRITE_MASK                         _MK_MASK_CONST(0xffffc070)
+// XM2CFGA data pins bypass outbound flop enable
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_BYPASS_EN_SHIFT                    _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_BYPASS_EN_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_BYPASS_EN_SHIFT)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_BYPASS_EN_RANGE                    4:4
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_BYPASS_EN_WOFFSET                  0x0
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_BYPASS_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_BYPASS_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_BYPASS_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_BYPASS_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_BYPASS_EN_DISABLE                  _MK_ENUM_CONST(0)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_BYPASS_EN_ENABLE                   _MK_ENUM_CONST(1)
+
+// XM2CFGA data pins preemp enable
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_PREEMP_EN_SHIFT                    _MK_SHIFT_CONST(5)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_PREEMP_EN_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_PREEMP_EN_SHIFT)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_PREEMP_EN_RANGE                    5:5
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_PREEMP_EN_WOFFSET                  0x0
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_PREEMP_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_PREEMP_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_PREEMP_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_PREEMP_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_PREEMP_EN_DISABLE                  _MK_ENUM_CONST(0)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_PREEMP_EN_ENABLE                   _MK_ENUM_CONST(1)
+
+// pad clk_sel  (ma bits get this value inverted in lpddr2 mode)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CLK_SEL_SHIFT                      _MK_SHIFT_CONST(6)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CLK_SEL_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CLK_SEL_SHIFT)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CLK_SEL_RANGE                      6:6
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CLK_SEL_WOFFSET                    0x0
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CLK_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CLK_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CLK_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CLK_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVDN_SHIFT                    _MK_SHIFT_CONST(14)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVDN_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVDN_RANGE                    18:14
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVDN_WOFFSET                  0x0
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVDN_DEFAULT                  _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVDN_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVDN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVDN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVUP_SHIFT                    _MK_SHIFT_CONST(19)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVUP_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVUP_RANGE                    23:19
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVUP_WOFFSET                  0x0
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVUP_DEFAULT                  _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVUP_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVUP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVUP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVDN_SLWR_SHIFT                       _MK_SHIFT_CONST(24)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVDN_SLWR_FIELD                       (_MK_MASK_CONST(0xf) << APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVDN_SLWR_RANGE                       27:24
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVDN_SLWR_WOFFSET                     0x0
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVDN_SLWR_DEFAULT                     _MK_MASK_CONST(0xf)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVDN_SLWR_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVDN_SLWR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVUP_SLWF_SHIFT                       _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVUP_SLWF_FIELD                       (_MK_MASK_CONST(0xf) << APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVUP_SLWF_RANGE                       31:28
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVUP_SLWF_WOFFSET                     0x0
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVUP_SLWF_DEFAULT                     _MK_MASK_CONST(0xf)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVUP_SLWF_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVUP_SLWF_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_XM2CFGCPADCTRL_0  //        0       rw  CFG2TMC_XM2CFGC_PULLD_EN   i=0x0   // XM2CFGC pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_XM2CFGC_PULLU_EN   i=0x0   // XM2CFGC pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_XM2CFGCPADCTRL_0                    _MK_ADDR_CONST(0x8c8)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_SECURE                     0x0
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_WORD_COUNT                         0x1
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_RESET_VAL                  _MK_MASK_CONST(0xfffffff0)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_RESET_MASK                         _MK_MASK_CONST(0xfffffff8)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_READ_MASK                  _MK_MASK_CONST(0xfffffff8)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_WRITE_MASK                         _MK_MASK_CONST(0xfffffff8)
+// XM2CFGD data pins schmidt enable
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_SCHMT_EN_SHIFT                     _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_SCHMT_EN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_SCHMT_EN_RANGE                     3:3
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_SCHMT_EN_WOFFSET                   0x0
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_SCHMT_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_SCHMT_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_SCHMT_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_SCHMT_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_SCHMT_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_SCHMT_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_TERM_SHIFT                       _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_TERM_FIELD                       (_MK_MASK_CONST(0x1f) << APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_TERM_SHIFT)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_TERM_RANGE                       8:4
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_TERM_WOFFSET                     0x0
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_TERM_DEFAULT                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_TERM_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_TERM_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_TERM_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_TERM_SHIFT                       _MK_SHIFT_CONST(9)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_TERM_FIELD                       (_MK_MASK_CONST(0x1f) << APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_TERM_SHIFT)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_TERM_RANGE                       13:9
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_TERM_WOFFSET                     0x0
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_TERM_DEFAULT                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_TERM_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_TERM_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_TERM_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_SHIFT                    _MK_SHIFT_CONST(14)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_RANGE                    18:14
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_WOFFSET                  0x0
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_DEFAULT                  _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_SHIFT                    _MK_SHIFT_CONST(19)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_RANGE                    23:19
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_WOFFSET                  0x0
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_DEFAULT                  _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_SLWR_SHIFT                       _MK_SHIFT_CONST(24)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_SLWR_FIELD                       (_MK_MASK_CONST(0xf) << APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_SLWR_RANGE                       27:24
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_SLWR_WOFFSET                     0x0
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_SLWR_DEFAULT                     _MK_MASK_CONST(0xf)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_SLWR_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_SLWR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_SLWF_SHIFT                       _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_SLWF_FIELD                       (_MK_MASK_CONST(0xf) << APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_SLWF_RANGE                       31:28
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_SLWF_WOFFSET                     0x0
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_SLWF_DEFAULT                     _MK_MASK_CONST(0xf)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_SLWF_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_SLWF_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_XM2CFGDPADCTRL_0  //        0       rw  CFG2TMC_XM2CFGD_PULLD_EN   i=0x0   // XM2CFGD pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_XM2CFGD_PULLU_EN   i=0x0   // XM2CFGD pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_XM2CFGDPADCTRL_0                    _MK_ADDR_CONST(0x8cc)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_SECURE                     0x0
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_WORD_COUNT                         0x1
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_RESET_VAL                  _MK_MASK_CONST(0xfffffff0)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_RESET_MASK                         _MK_MASK_CONST(0xfffffff8)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_READ_MASK                  _MK_MASK_CONST(0xfffffff8)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_WRITE_MASK                         _MK_MASK_CONST(0xfffffff8)
+// XM2CFGD data pins schmidt enable
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_SCHMT_EN_SHIFT                     _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_SCHMT_EN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_SCHMT_EN_RANGE                     3:3
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_SCHMT_EN_WOFFSET                   0x0
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_SCHMT_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_SCHMT_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_SCHMT_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_SCHMT_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_SCHMT_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_SCHMT_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_TERM_SHIFT                       _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_TERM_FIELD                       (_MK_MASK_CONST(0x1f) << APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_TERM_SHIFT)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_TERM_RANGE                       8:4
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_TERM_WOFFSET                     0x0
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_TERM_DEFAULT                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_TERM_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_TERM_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_TERM_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_TERM_SHIFT                       _MK_SHIFT_CONST(9)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_TERM_FIELD                       (_MK_MASK_CONST(0x1f) << APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_TERM_SHIFT)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_TERM_RANGE                       13:9
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_TERM_WOFFSET                     0x0
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_TERM_DEFAULT                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_TERM_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_TERM_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_TERM_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_SHIFT                    _MK_SHIFT_CONST(14)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_RANGE                    18:14
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_WOFFSET                  0x0
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_DEFAULT                  _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_SHIFT                    _MK_SHIFT_CONST(19)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_RANGE                    23:19
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_WOFFSET                  0x0
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_DEFAULT                  _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_SLWR_SHIFT                       _MK_SHIFT_CONST(24)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_SLWR_FIELD                       (_MK_MASK_CONST(0xf) << APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_SLWR_RANGE                       27:24
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_SLWR_WOFFSET                     0x0
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_SLWR_DEFAULT                     _MK_MASK_CONST(0xf)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_SLWR_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_SLWR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_SLWF_SHIFT                       _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_SLWF_FIELD                       (_MK_MASK_CONST(0xf) << APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_SLWF_RANGE                       31:28
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_SLWF_WOFFSET                     0x0
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_SLWF_DEFAULT                     _MK_MASK_CONST(0xf)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_SLWF_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_SLWF_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_XM2CLKCFGPADCTRL_0  //        0       rw  CFG2TMC_XM2CLKCFG_PULLD_EN   i=0x0   // XM2CLKCFG pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_XM2CLKCFG_PULLU_EN   i=0x0   // XM2CLKCFG pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0                  _MK_ADDR_CONST(0x8d0)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_SECURE                   0x0
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_WORD_COUNT                       0x1
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_RESET_VAL                        _MK_MASK_CONST(0xffffc002)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_RESET_MASK                       _MK_MASK_CONST(0xffffc00e)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_READ_MASK                        _MK_MASK_CONST(0xffffc00e)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_WRITE_MASK                       _MK_MASK_CONST(0xffffc00e)
+// XM2 bypass outbound flop enable
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_BYPASS_EN_SHIFT                        _MK_SHIFT_CONST(1)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_BYPASS_EN_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_BYPASS_EN_SHIFT)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_BYPASS_EN_RANGE                        1:1
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_BYPASS_EN_WOFFSET                      0x0
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_BYPASS_EN_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_BYPASS_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_BYPASS_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_BYPASS_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_BYPASS_EN_DISABLE                      _MK_ENUM_CONST(0)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_BYPASS_EN_ENABLE                       _MK_ENUM_CONST(1)
+
+// preemp enable
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_PREEMP_EN_SHIFT                        _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_PREEMP_EN_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_PREEMP_EN_SHIFT)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_PREEMP_EN_RANGE                        2:2
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_PREEMP_EN_WOFFSET                      0x0
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_PREEMP_EN_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_PREEMP_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_PREEMP_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_PREEMP_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_PREEMP_EN_DISABLE                      _MK_ENUM_CONST(0)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_PREEMP_EN_ENABLE                       _MK_ENUM_CONST(1)
+
+// XM2CLKCFG bypass drvdn/up calibration 
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_BYPASS_EN_SHIFT                    _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_BYPASS_EN_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_BYPASS_EN_SHIFT)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_BYPASS_EN_RANGE                    3:3
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_BYPASS_EN_WOFFSET                  0x0
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_BYPASS_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_BYPASS_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_BYPASS_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_BYPASS_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_BYPASS_EN_DISABLE                  _MK_ENUM_CONST(0)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_BYPASS_EN_ENABLE                   _MK_ENUM_CONST(1)
+
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVDN_SHIFT                        _MK_SHIFT_CONST(14)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVDN_FIELD                        (_MK_MASK_CONST(0x1f) << APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVDN_RANGE                        18:14
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVDN_WOFFSET                      0x0
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVDN_DEFAULT                      _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVDN_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVDN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVDN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVUP_SHIFT                        _MK_SHIFT_CONST(19)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVUP_FIELD                        (_MK_MASK_CONST(0x1f) << APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVUP_RANGE                        23:19
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVUP_WOFFSET                      0x0
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVUP_DEFAULT                      _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVUP_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVUP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVUP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVDN_SLWR_SHIFT                   _MK_SHIFT_CONST(24)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVDN_SLWR_FIELD                   (_MK_MASK_CONST(0xf) << APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVDN_SLWR_RANGE                   27:24
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVDN_SLWR_WOFFSET                 0x0
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVDN_SLWR_DEFAULT                 _MK_MASK_CONST(0xf)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVDN_SLWR_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVDN_SLWR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVUP_SLWF_SHIFT                   _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVUP_SLWF_FIELD                   (_MK_MASK_CONST(0xf) << APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVUP_SLWF_RANGE                   31:28
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVUP_SLWF_WOFFSET                 0x0
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVUP_SLWF_DEFAULT                 _MK_MASK_CONST(0xf)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVUP_SLWF_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVUP_SLWF_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_XM2COMPPADCTRL_0  
+#define APB_MISC_GP_XM2COMPPADCTRL_0                    _MK_ADDR_CONST(0x8d4)
+#define APB_MISC_GP_XM2COMPPADCTRL_0_SECURE                     0x0
+#define APB_MISC_GP_XM2COMPPADCTRL_0_WORD_COUNT                         0x1
+#define APB_MISC_GP_XM2COMPPADCTRL_0_RESET_VAL                  _MK_MASK_CONST(0x1f1f008)
+#define APB_MISC_GP_XM2COMPPADCTRL_0_RESET_MASK                         _MK_MASK_CONST(0x1f1f0ff)
+#define APB_MISC_GP_XM2COMPPADCTRL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2COMPPADCTRL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2COMPPADCTRL_0_READ_MASK                  _MK_MASK_CONST(0x1f1f0ff)
+#define APB_MISC_GP_XM2COMPPADCTRL_0_WRITE_MASK                         _MK_MASK_CONST(0x1f1f0ff)
+#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_VREF_SEL_SHIFT                     _MK_SHIFT_CONST(0)
+#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_VREF_SEL_FIELD                     (_MK_MASK_CONST(0xf) << APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_VREF_SEL_SHIFT)
+#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_VREF_SEL_RANGE                     3:0
+#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_VREF_SEL_WOFFSET                   0x0
+#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_VREF_SEL_DEFAULT                   _MK_MASK_CONST(0x8)
+#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_VREF_SEL_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_VREF_SEL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_VREF_SEL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_TESTOUT_EN_SHIFT                   _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_TESTOUT_EN_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_TESTOUT_EN_SHIFT)
+#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_TESTOUT_EN_RANGE                   4:4
+#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_TESTOUT_EN_WOFFSET                 0x0
+#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_TESTOUT_EN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_TESTOUT_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_TESTOUT_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_TESTOUT_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_TESTOUT_EN_DISABLE                 _MK_ENUM_CONST(0)
+#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_TESTOUT_EN_ENABLE                  _MK_ENUM_CONST(1)
+
+#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_BIAS_SEL_SHIFT                     _MK_SHIFT_CONST(5)
+#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_BIAS_SEL_FIELD                     (_MK_MASK_CONST(0x7) << APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_BIAS_SEL_SHIFT)
+#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_BIAS_SEL_RANGE                     7:5
+#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_BIAS_SEL_WOFFSET                   0x0
+#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_BIAS_SEL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_BIAS_SEL_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_BIAS_SEL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_BIAS_SEL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_DRVDN_SHIFT                        _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_DRVDN_FIELD                        (_MK_MASK_CONST(0x1f) << APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_DRVDN_SHIFT)
+#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_DRVDN_RANGE                        16:12
+#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_DRVDN_WOFFSET                      0x0
+#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_DRVDN_DEFAULT                      _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_DRVDN_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_DRVDN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_DRVDN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_DRVUP_SHIFT                        _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_DRVUP_FIELD                        (_MK_MASK_CONST(0x1f) << APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_DRVUP_SHIFT)
+#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_DRVUP_RANGE                        24:20
+#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_DRVUP_WOFFSET                      0x0
+#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_DRVUP_DEFAULT                      _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_DRVUP_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_DRVUP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_DRVUP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_XM2VTTGENPADCTRL_0  
+#define APB_MISC_GP_XM2VTTGENPADCTRL_0                  _MK_ADDR_CONST(0x8d8)
+#define APB_MISC_GP_XM2VTTGENPADCTRL_0_SECURE                   0x0
+#define APB_MISC_GP_XM2VTTGENPADCTRL_0_WORD_COUNT                       0x1
+#define APB_MISC_GP_XM2VTTGENPADCTRL_0_RESET_VAL                        _MK_MASK_CONST(0x5500)
+#define APB_MISC_GP_XM2VTTGENPADCTRL_0_RESET_MASK                       _MK_MASK_CONST(0x7077701)
+#define APB_MISC_GP_XM2VTTGENPADCTRL_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2VTTGENPADCTRL_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2VTTGENPADCTRL_0_READ_MASK                        _MK_MASK_CONST(0x7077703)
+#define APB_MISC_GP_XM2VTTGENPADCTRL_0_WRITE_MASK                       _MK_MASK_CONST(0x7077703)
+#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_SHORT_SHIFT                    _MK_SHIFT_CONST(0)
+#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_SHORT_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_SHORT_SHIFT)
+#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_SHORT_RANGE                    0:0
+#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_SHORT_WOFFSET                  0x0
+#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_SHORT_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_SHORT_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_SHORT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_SHORT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// dummy pin
+#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_SHORT_PWRGND_SHIFT                     _MK_SHIFT_CONST(1)
+#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_SHORT_PWRGND_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_SHORT_PWRGND_SHIFT)
+#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_SHORT_PWRGND_RANGE                     1:1
+#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_SHORT_PWRGND_WOFFSET                   0x0
+#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_SHORT_PWRGND_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_SHORT_PWRGND_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_SHORT_PWRGND_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_SHORT_PWRGND_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_VCLAMP_LEVEL_SHIFT                     _MK_SHIFT_CONST(8)
+#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_VCLAMP_LEVEL_FIELD                     (_MK_MASK_CONST(0x7) << APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_VCLAMP_LEVEL_SHIFT)
+#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_VCLAMP_LEVEL_RANGE                     10:8
+#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_VCLAMP_LEVEL_WOFFSET                   0x0
+#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_VCLAMP_LEVEL_DEFAULT                   _MK_MASK_CONST(0x5)
+#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_VCLAMP_LEVEL_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_VCLAMP_LEVEL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_VCLAMP_LEVEL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_VAUXP_LEVEL_SHIFT                      _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_VAUXP_LEVEL_FIELD                      (_MK_MASK_CONST(0x7) << APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_VAUXP_LEVEL_SHIFT)
+#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_VAUXP_LEVEL_RANGE                      14:12
+#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_VAUXP_LEVEL_WOFFSET                    0x0
+#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_VAUXP_LEVEL_DEFAULT                    _MK_MASK_CONST(0x5)
+#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_VAUXP_LEVEL_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_VAUXP_LEVEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_VAUXP_LEVEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_CAL_DRVDN_SHIFT                        _MK_SHIFT_CONST(16)
+#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_CAL_DRVDN_FIELD                        (_MK_MASK_CONST(0x7) << APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_CAL_DRVDN_RANGE                        18:16
+#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_CAL_DRVDN_WOFFSET                      0x0
+#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_CAL_DRVDN_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_CAL_DRVDN_DEFAULT_MASK                 _MK_MASK_CONST(0x7)
+#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_CAL_DRVDN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_CAL_DRVDN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_CAL_DRVUP_SHIFT                        _MK_SHIFT_CONST(24)
+#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_CAL_DRVUP_FIELD                        (_MK_MASK_CONST(0x7) << APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_CAL_DRVUP_RANGE                        26:24
+#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_CAL_DRVUP_WOFFSET                      0x0
+#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_CAL_DRVUP_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_CAL_DRVUP_DEFAULT_MASK                 _MK_MASK_CONST(0x7)
+#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_CAL_DRVUP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_CAL_DRVUP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_PADCTL_DFT_0  
+#define APB_MISC_GP_PADCTL_DFT_0                        _MK_ADDR_CONST(0x8dc)
+#define APB_MISC_GP_PADCTL_DFT_0_SECURE                         0x0
+#define APB_MISC_GP_PADCTL_DFT_0_WORD_COUNT                     0x1
+#define APB_MISC_GP_PADCTL_DFT_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_PADCTL_DFT_0_RESET_MASK                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_PADCTL_DFT_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_PADCTL_DFT_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_PADCTL_DFT_0_READ_MASK                      _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_PADCTL_DFT_0_WRITE_MASK                     _MK_MASK_CONST(0x3)
+// Enable pin-shorting for tester mode pin-shorting
+#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_EN_SHIFT                      _MK_SHIFT_CONST(0)
+#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_EN_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_PADCTL_DFT_0_PINSHORT_EN_SHIFT)
+#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_EN_RANGE                      0:0
+#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_EN_WOFFSET                    0x0
+#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_EN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_EN_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_EN_ENABLE                     _MK_ENUM_CONST(1)
+
+// Select which pins are used for test-mode observe
+#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_SEL_SHIFT                     _MK_SHIFT_CONST(1)
+#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_SEL_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_PADCTL_DFT_0_PINSHORT_SEL_SHIFT)
+#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_SEL_RANGE                     1:1
+#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_SEL_WOFFSET                   0x0
+#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_SEL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_SEL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_SEL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_SEL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_SDIO1CFGPADCTRL_0  //        0       rw  CFG2TMC_SDIO1CFG_PULLD_EN   i=0x0   // SDIO3CFG pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_SDIO1CFG_PULLU_EN   i=0x0   // SDIO3CFG pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0                   _MK_ADDR_CONST(0x8e0)
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_SECURE                    0x0
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_WORD_COUNT                        0x1
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_RESET_VAL                         _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_RESET_MASK                        _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_READ_MASK                         _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_WRITE_MASK                        _MK_MASK_CONST(0xf1f1f03c)
+// SDIO3CFG data pins high speed mode enable
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_HSM_EN_SHIFT                     _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_HSM_EN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_HSM_EN_SHIFT)
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_HSM_EN_RANGE                     2:2
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_HSM_EN_WOFFSET                   0x0
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_HSM_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_HSM_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_HSM_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_HSM_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_HSM_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_HSM_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// SDIO3CFG data pins schmidt enable
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_SCHMT_EN_SHIFT                   _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_SCHMT_EN_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_SCHMT_EN_RANGE                   3:3
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_SCHMT_EN_WOFFSET                 0x0
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_SCHMT_EN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_SCHMT_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_SCHMT_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_SCHMT_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_SCHMT_EN_DISABLE                 _MK_ENUM_CONST(0)
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_SCHMT_EN_ENABLE                  _MK_ENUM_CONST(1)
+
+// SDIO3CFG data pins low power mode select
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_LPMD_SHIFT                       _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_LPMD_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_LPMD_SHIFT)
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_LPMD_RANGE                       5:4
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_LPMD_WOFFSET                     0x0
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_LPMD_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_LPMD_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_LPMD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_LPMD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_CAL_DRVDN_SHIFT                  _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_CAL_DRVDN_FIELD                  (_MK_MASK_CONST(0x1f) << APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_CAL_DRVDN_RANGE                  16:12
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_CAL_DRVDN_WOFFSET                        0x0
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_CAL_DRVDN_DEFAULT                        _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_CAL_DRVDN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_CAL_DRVDN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_CAL_DRVDN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_CAL_DRVUP_SHIFT                  _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_CAL_DRVUP_FIELD                  (_MK_MASK_CONST(0x1f) << APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_CAL_DRVUP_RANGE                  24:20
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_CAL_DRVUP_WOFFSET                        0x0
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_CAL_DRVUP_DEFAULT                        _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_CAL_DRVUP_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_CAL_DRVUP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_CAL_DRVUP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_CAL_DRVDN_SLWR_SHIFT                     _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_CAL_DRVDN_SLWR_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_CAL_DRVDN_SLWR_RANGE                     29:28
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_CAL_DRVDN_SLWR_WOFFSET                   0x0
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_CAL_DRVDN_SLWR_DEFAULT                   _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_CAL_DRVDN_SLWR_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_CAL_DRVDN_SLWR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_CAL_DRVUP_SLWF_SHIFT                     _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_CAL_DRVUP_SLWF_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_CAL_DRVUP_SLWF_RANGE                     31:30
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_CAL_DRVUP_SLWF_WOFFSET                   0x0
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_CAL_DRVUP_SLWF_DEFAULT                   _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_CAL_DRVUP_SLWF_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_CAL_DRVUP_SLWF_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_XM2CFGCPADCTRL2_0  
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0                   _MK_ADDR_CONST(0x8e4)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_SECURE                    0x0
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_WORD_COUNT                        0x1
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_RESET_VAL                         _MK_MASK_CONST(0x8080042)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_RESET_MASK                        _MK_MASK_CONST(0xf0f00ff)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_READ_MASK                         _MK_MASK_CONST(0xf0f00ff)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_WRITE_MASK                        _MK_MASK_CONST(0xf0f00ff)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_RX_FT_REC_EN_SHIFT                        _MK_SHIFT_CONST(0)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_RX_FT_REC_EN_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_RX_FT_REC_EN_SHIFT)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_RX_FT_REC_EN_RANGE                        0:0
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_RX_FT_REC_EN_WOFFSET                      0x0
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_RX_FT_REC_EN_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_RX_FT_REC_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_RX_FT_REC_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_RX_FT_REC_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_RX_FT_REC_EN_DISABLE                      _MK_ENUM_CONST(0)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_RX_FT_REC_EN_ENABLE                       _MK_ENUM_CONST(1)
+
+// XM2CFGD data pins bypass outbound flop enable
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_BYPASS_EN_SHIFT                   _MK_SHIFT_CONST(1)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_BYPASS_EN_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_BYPASS_EN_SHIFT)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_BYPASS_EN_RANGE                   1:1
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_BYPASS_EN_WOFFSET                 0x0
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_BYPASS_EN_DEFAULT                 _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_BYPASS_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_BYPASS_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_BYPASS_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_BYPASS_EN_DISABLE                 _MK_ENUM_CONST(0)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_BYPASS_EN_ENABLE                  _MK_ENUM_CONST(1)
+
+// XM2CFGD data pins preemp enable
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_PREEMP_EN_SHIFT                   _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_PREEMP_EN_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_PREEMP_EN_SHIFT)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_PREEMP_EN_RANGE                   2:2
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_PREEMP_EN_WOFFSET                 0x0
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_PREEMP_EN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_PREEMP_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_PREEMP_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_PREEMP_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_PREEMP_EN_DISABLE                 _MK_ENUM_CONST(0)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_PREEMP_EN_ENABLE                  _MK_ENUM_CONST(1)
+
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_CTT_HIZ_EN_SHIFT                  _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_CTT_HIZ_EN_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_CTT_HIZ_EN_SHIFT)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_CTT_HIZ_EN_RANGE                  3:3
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_CTT_HIZ_EN_WOFFSET                        0x0
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_CTT_HIZ_EN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_CTT_HIZ_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_CTT_HIZ_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_CTT_HIZ_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_CTT_HIZ_EN_DISABLE                        _MK_ENUM_CONST(0)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_CTT_HIZ_EN_ENABLE                 _MK_ENUM_CONST(1)
+
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQS_EN_SHIFT                 _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQS_EN_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQS_EN_SHIFT)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQS_EN_RANGE                 4:4
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQS_EN_WOFFSET                       0x0
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQS_EN_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQS_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQS_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQS_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQS_EN_DISABLE                       _MK_ENUM_CONST(0)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQS_EN_ENABLE                        _MK_ENUM_CONST(1)
+
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQ_EN_SHIFT                  _MK_SHIFT_CONST(5)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQ_EN_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQ_EN_SHIFT)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQ_EN_RANGE                  5:5
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQ_EN_WOFFSET                        0x0
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQ_EN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQ_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQ_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQ_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQ_EN_DISABLE                        _MK_ENUM_CONST(0)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQ_EN_ENABLE                 _MK_ENUM_CONST(1)
+
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_CLKSEL_DQ_SHIFT                   _MK_SHIFT_CONST(6)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_CLKSEL_DQ_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_CLKSEL_DQ_SHIFT)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_CLKSEL_DQ_RANGE                   6:6
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_CLKSEL_DQ_WOFFSET                 0x0
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_CLKSEL_DQ_DEFAULT                 _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_CLKSEL_DQ_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_CLKSEL_DQ_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_CLKSEL_DQ_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_CLKSEL_DQS_SHIFT                  _MK_SHIFT_CONST(7)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_CLKSEL_DQS_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_CLKSEL_DQS_SHIFT)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_CLKSEL_DQS_RANGE                  7:7
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_CLKSEL_DQS_WOFFSET                        0x0
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_CLKSEL_DQS_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_CLKSEL_DQS_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_CLKSEL_DQS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_CLKSEL_DQS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQS_SHIFT                    _MK_SHIFT_CONST(16)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQS_FIELD                    (_MK_MASK_CONST(0xf) << APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQS_SHIFT)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQS_RANGE                    19:16
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQS_WOFFSET                  0x0
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQS_DEFAULT                  _MK_MASK_CONST(0x8)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQS_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQ_SHIFT                     _MK_SHIFT_CONST(24)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQ_FIELD                     (_MK_MASK_CONST(0xf) << APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQ_SHIFT)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQ_RANGE                     27:24
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQ_WOFFSET                   0x0
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQ_DEFAULT                   _MK_MASK_CONST(0x8)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQ_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_XM2CFGDPADCTRL2_0  
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0                   _MK_ADDR_CONST(0x8e8)
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_SECURE                    0x0
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_WORD_COUNT                        0x1
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_RESET_VAL                         _MK_MASK_CONST(0x2)
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_RESET_MASK                        _MK_MASK_CONST(0x7777000f)
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_READ_MASK                         _MK_MASK_CONST(0x7777000f)
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_WRITE_MASK                        _MK_MASK_CONST(0x7777000f)
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_RX_FT_REC_EN_SHIFT                        _MK_SHIFT_CONST(0)
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_RX_FT_REC_EN_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_RX_FT_REC_EN_SHIFT)
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_RX_FT_REC_EN_RANGE                        0:0
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_RX_FT_REC_EN_WOFFSET                      0x0
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_RX_FT_REC_EN_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_RX_FT_REC_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_RX_FT_REC_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_RX_FT_REC_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_RX_FT_REC_EN_DISABLE                      _MK_ENUM_CONST(0)
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_RX_FT_REC_EN_ENABLE                       _MK_ENUM_CONST(1)
+
+// XM2CFGD data pins bypass outbound flop enable
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_BYPASS_EN_SHIFT                   _MK_SHIFT_CONST(1)
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_BYPASS_EN_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_BYPASS_EN_SHIFT)
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_BYPASS_EN_RANGE                   1:1
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_BYPASS_EN_WOFFSET                 0x0
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_BYPASS_EN_DEFAULT                 _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_BYPASS_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_BYPASS_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_BYPASS_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_BYPASS_EN_DISABLE                 _MK_ENUM_CONST(0)
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_BYPASS_EN_ENABLE                  _MK_ENUM_CONST(1)
+
+// XM2CFGD data pins preemp enable
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_PREEMP_EN_SHIFT                   _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_PREEMP_EN_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_PREEMP_EN_SHIFT)
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_PREEMP_EN_RANGE                   2:2
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_PREEMP_EN_WOFFSET                 0x0
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_PREEMP_EN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_PREEMP_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_PREEMP_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_PREEMP_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_PREEMP_EN_DISABLE                 _MK_ENUM_CONST(0)
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_PREEMP_EN_ENABLE                  _MK_ENUM_CONST(1)
+
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_CTT_HIZ_EN_SHIFT                  _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_CTT_HIZ_EN_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_CTT_HIZ_EN_SHIFT)
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_CTT_HIZ_EN_RANGE                  3:3
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_CTT_HIZ_EN_WOFFSET                        0x0
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_CTT_HIZ_EN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_CTT_HIZ_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_CTT_HIZ_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_CTT_HIZ_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_CTT_HIZ_EN_DISABLE                        _MK_ENUM_CONST(0)
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_CTT_HIZ_EN_ENABLE                 _MK_ENUM_CONST(1)
+
+//delay trim for byte 0
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD0_DLYIN_TRM_SHIFT                  _MK_SHIFT_CONST(16)
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD0_DLYIN_TRM_FIELD                  (_MK_MASK_CONST(0x7) << APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD0_DLYIN_TRM_SHIFT)
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD0_DLYIN_TRM_RANGE                  18:16
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD0_DLYIN_TRM_WOFFSET                        0x0
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD0_DLYIN_TRM_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD0_DLYIN_TRM_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD0_DLYIN_TRM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD0_DLYIN_TRM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//delay trim for byte 1
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD1_DLYIN_TRM_SHIFT                  _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD1_DLYIN_TRM_FIELD                  (_MK_MASK_CONST(0x7) << APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD1_DLYIN_TRM_SHIFT)
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD1_DLYIN_TRM_RANGE                  22:20
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD1_DLYIN_TRM_WOFFSET                        0x0
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD1_DLYIN_TRM_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD1_DLYIN_TRM_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD1_DLYIN_TRM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD1_DLYIN_TRM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//delay trim for byte 2
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD2_DLYIN_TRM_SHIFT                  _MK_SHIFT_CONST(24)
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD2_DLYIN_TRM_FIELD                  (_MK_MASK_CONST(0x7) << APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD2_DLYIN_TRM_SHIFT)
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD2_DLYIN_TRM_RANGE                  26:24
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD2_DLYIN_TRM_WOFFSET                        0x0
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD2_DLYIN_TRM_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD2_DLYIN_TRM_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD2_DLYIN_TRM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD2_DLYIN_TRM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//delay trim for byte 3
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD3_DLYIN_TRM_SHIFT                  _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD3_DLYIN_TRM_FIELD                  (_MK_MASK_CONST(0x7) << APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD3_DLYIN_TRM_SHIFT)
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD3_DLYIN_TRM_RANGE                  30:28
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD3_DLYIN_TRM_WOFFSET                        0x0
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD3_DLYIN_TRM_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD3_DLYIN_TRM_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD3_DLYIN_TRM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD3_DLYIN_TRM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_CRTCFGPADCTRL_0  //        0       rw  CFG2TMC_CRTCFG_PULLD_EN   i=0x0   // SDIO3CFG pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_CRTCFG_PULLU_EN   i=0x0   // SDIO3CFG pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_CRTCFGPADCTRL_0                     _MK_ADDR_CONST(0x8ec)
+#define APB_MISC_GP_CRTCFGPADCTRL_0_SECURE                      0x0
+#define APB_MISC_GP_CRTCFGPADCTRL_0_WORD_COUNT                  0x1
+#define APB_MISC_GP_CRTCFGPADCTRL_0_RESET_VAL                   _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_CRTCFGPADCTRL_0_RESET_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_CRTCFGPADCTRL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CRTCFGPADCTRL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CRTCFGPADCTRL_0_READ_MASK                   _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_CRTCFGPADCTRL_0_WRITE_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+// SDIO3CFG data pins high speed mode enable
+#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_HSM_EN_SHIFT                 _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_HSM_EN_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_HSM_EN_SHIFT)
+#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_HSM_EN_RANGE                 2:2
+#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_HSM_EN_WOFFSET                       0x0
+#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_HSM_EN_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_HSM_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_HSM_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_HSM_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_HSM_EN_DISABLE                       _MK_ENUM_CONST(0)
+#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_HSM_EN_ENABLE                        _MK_ENUM_CONST(1)
+
+// SDIO3CFG data pins schmidt enable
+#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_SCHMT_EN_SHIFT                       _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_SCHMT_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_SCHMT_EN_RANGE                       3:3
+#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_SCHMT_EN_WOFFSET                     0x0
+#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_SCHMT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_SCHMT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_SCHMT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_SCHMT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_SCHMT_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_SCHMT_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// SDIO3CFG data pins low power mode select
+#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_LPMD_SHIFT                   _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_LPMD_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_LPMD_SHIFT)
+#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_LPMD_RANGE                   5:4
+#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_LPMD_WOFFSET                 0x0
+#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_LPMD_DEFAULT                 _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_LPMD_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_LPMD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_LPMD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_CAL_DRVDN_SHIFT                      _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_CAL_DRVDN_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_CAL_DRVDN_RANGE                      16:12
+#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_CAL_DRVDN_WOFFSET                    0x0
+#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_CAL_DRVDN_DEFAULT                    _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_CAL_DRVDN_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_CAL_DRVDN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_CAL_DRVDN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_CAL_DRVUP_SHIFT                      _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_CAL_DRVUP_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_CAL_DRVUP_RANGE                      24:20
+#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_CAL_DRVUP_WOFFSET                    0x0
+#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_CAL_DRVUP_DEFAULT                    _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_CAL_DRVUP_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_CAL_DRVUP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_CAL_DRVUP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_CAL_DRVDN_SLWR_SHIFT                 _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_CAL_DRVDN_SLWR_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_CAL_DRVDN_SLWR_RANGE                 29:28
+#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_CAL_DRVDN_SLWR_WOFFSET                       0x0
+#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_CAL_DRVDN_SLWR_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_CAL_DRVDN_SLWR_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_CAL_DRVDN_SLWR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_CAL_DRVUP_SLWF_SHIFT                 _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_CAL_DRVUP_SLWF_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_CAL_DRVUP_SLWF_RANGE                 31:30
+#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_CAL_DRVUP_SLWF_WOFFSET                       0x0
+#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_CAL_DRVUP_SLWF_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_CAL_DRVUP_SLWF_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_CAL_DRVUP_SLWF_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_DDCCFGPADCTRL_0  //        0       rw  CFG2TMC_DDCCFG_PULLD_EN   i=0x0   // SDIO3CFG pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_DDCCFG_PULLU_EN   i=0x0   // SDIO3CFG pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_DDCCFGPADCTRL_0                     _MK_ADDR_CONST(0x8f0)
+#define APB_MISC_GP_DDCCFGPADCTRL_0_SECURE                      0x0
+#define APB_MISC_GP_DDCCFGPADCTRL_0_WORD_COUNT                  0x1
+#define APB_MISC_GP_DDCCFGPADCTRL_0_RESET_VAL                   _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_DDCCFGPADCTRL_0_RESET_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_DDCCFGPADCTRL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DDCCFGPADCTRL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DDCCFGPADCTRL_0_READ_MASK                   _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_DDCCFGPADCTRL_0_WRITE_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+// SDIO3CFG data pins high speed mode enable
+#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_HSM_EN_SHIFT                 _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_HSM_EN_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_HSM_EN_SHIFT)
+#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_HSM_EN_RANGE                 2:2
+#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_HSM_EN_WOFFSET                       0x0
+#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_HSM_EN_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_HSM_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_HSM_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_HSM_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_HSM_EN_DISABLE                       _MK_ENUM_CONST(0)
+#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_HSM_EN_ENABLE                        _MK_ENUM_CONST(1)
+
+// SDIO3CFG data pins schmidt enable
+#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_SCHMT_EN_SHIFT                       _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_SCHMT_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_SCHMT_EN_RANGE                       3:3
+#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_SCHMT_EN_WOFFSET                     0x0
+#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_SCHMT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_SCHMT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_SCHMT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_SCHMT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_SCHMT_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_SCHMT_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// SDIO3CFG data pins low power mode select
+#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_LPMD_SHIFT                   _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_LPMD_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_LPMD_SHIFT)
+#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_LPMD_RANGE                   5:4
+#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_LPMD_WOFFSET                 0x0
+#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_LPMD_DEFAULT                 _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_LPMD_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_LPMD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_LPMD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_CAL_DRVDN_SHIFT                      _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_CAL_DRVDN_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_CAL_DRVDN_RANGE                      16:12
+#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_CAL_DRVDN_WOFFSET                    0x0
+#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_CAL_DRVDN_DEFAULT                    _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_CAL_DRVDN_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_CAL_DRVDN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_CAL_DRVDN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_CAL_DRVUP_SHIFT                      _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_CAL_DRVUP_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_CAL_DRVUP_RANGE                      24:20
+#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_CAL_DRVUP_WOFFSET                    0x0
+#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_CAL_DRVUP_DEFAULT                    _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_CAL_DRVUP_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_CAL_DRVUP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_CAL_DRVUP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_CAL_DRVDN_SLWR_SHIFT                 _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_CAL_DRVDN_SLWR_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_CAL_DRVDN_SLWR_RANGE                 29:28
+#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_CAL_DRVDN_SLWR_WOFFSET                       0x0
+#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_CAL_DRVDN_SLWR_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_CAL_DRVDN_SLWR_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_CAL_DRVDN_SLWR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_CAL_DRVUP_SLWF_SHIFT                 _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_CAL_DRVUP_SLWF_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_CAL_DRVUP_SLWF_RANGE                 31:30
+#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_CAL_DRVUP_SLWF_WOFFSET                       0x0
+#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_CAL_DRVUP_SLWF_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_CAL_DRVUP_SLWF_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_CAL_DRVUP_SLWF_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_GMACFGPADCTRL_0  //        0       rw  CFG2TMC_GMACFG_PULLD_EN   i=0x0   // SDIO3CFG pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_GMACFG_PULLU_EN   i=0x0   // SDIO3CFG pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_GMACFGPADCTRL_0                     _MK_ADDR_CONST(0x8f4)
+#define APB_MISC_GP_GMACFGPADCTRL_0_SECURE                      0x0
+#define APB_MISC_GP_GMACFGPADCTRL_0_WORD_COUNT                  0x1
+#define APB_MISC_GP_GMACFGPADCTRL_0_RESET_VAL                   _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_GMACFGPADCTRL_0_RESET_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_GMACFGPADCTRL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMACFGPADCTRL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMACFGPADCTRL_0_READ_MASK                   _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_GMACFGPADCTRL_0_WRITE_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+// SDIO3CFG data pins high speed mode enable
+#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_HSM_EN_SHIFT                 _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_HSM_EN_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_HSM_EN_SHIFT)
+#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_HSM_EN_RANGE                 2:2
+#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_HSM_EN_WOFFSET                       0x0
+#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_HSM_EN_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_HSM_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_HSM_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_HSM_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_HSM_EN_DISABLE                       _MK_ENUM_CONST(0)
+#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_HSM_EN_ENABLE                        _MK_ENUM_CONST(1)
+
+// SDIO3CFG data pins schmidt enable
+#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_SCHMT_EN_SHIFT                       _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_SCHMT_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_SCHMT_EN_RANGE                       3:3
+#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_SCHMT_EN_WOFFSET                     0x0
+#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_SCHMT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_SCHMT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_SCHMT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_SCHMT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_SCHMT_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_SCHMT_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// SDIO3CFG data pins low power mode select
+#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_LPMD_SHIFT                   _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_LPMD_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_LPMD_SHIFT)
+#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_LPMD_RANGE                   5:4
+#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_LPMD_WOFFSET                 0x0
+#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_LPMD_DEFAULT                 _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_LPMD_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_LPMD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_LPMD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_CAL_DRVDN_SHIFT                      _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_CAL_DRVDN_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_CAL_DRVDN_RANGE                      16:12
+#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_CAL_DRVDN_WOFFSET                    0x0
+#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_CAL_DRVDN_DEFAULT                    _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_CAL_DRVDN_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_CAL_DRVDN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_CAL_DRVDN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_CAL_DRVUP_SHIFT                      _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_CAL_DRVUP_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_CAL_DRVUP_RANGE                      24:20
+#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_CAL_DRVUP_WOFFSET                    0x0
+#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_CAL_DRVUP_DEFAULT                    _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_CAL_DRVUP_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_CAL_DRVUP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_CAL_DRVUP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_CAL_DRVDN_SLWR_SHIFT                 _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_CAL_DRVDN_SLWR_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_CAL_DRVDN_SLWR_RANGE                 29:28
+#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_CAL_DRVDN_SLWR_WOFFSET                       0x0
+#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_CAL_DRVDN_SLWR_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_CAL_DRVDN_SLWR_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_CAL_DRVDN_SLWR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_CAL_DRVUP_SLWF_SHIFT                 _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_CAL_DRVUP_SLWF_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_CAL_DRVUP_SLWF_RANGE                 31:30
+#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_CAL_DRVUP_SLWF_WOFFSET                       0x0
+#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_CAL_DRVUP_SLWF_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_CAL_DRVUP_SLWF_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_CAL_DRVUP_SLWF_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_GMBCFGPADCTRL_0  //        0       rw  CFG2TMC_GMBCFG_PULLD_EN   i=0x0   // SDIO3CFG pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_GMBCFG_PULLU_EN   i=0x0   // SDIO3CFG pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_GMBCFGPADCTRL_0                     _MK_ADDR_CONST(0x8f8)
+#define APB_MISC_GP_GMBCFGPADCTRL_0_SECURE                      0x0
+#define APB_MISC_GP_GMBCFGPADCTRL_0_WORD_COUNT                  0x1
+#define APB_MISC_GP_GMBCFGPADCTRL_0_RESET_VAL                   _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_GMBCFGPADCTRL_0_RESET_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_GMBCFGPADCTRL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMBCFGPADCTRL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMBCFGPADCTRL_0_READ_MASK                   _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_GMBCFGPADCTRL_0_WRITE_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+// SDIO3CFG data pins high speed mode enable
+#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_HSM_EN_SHIFT                 _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_HSM_EN_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_HSM_EN_SHIFT)
+#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_HSM_EN_RANGE                 2:2
+#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_HSM_EN_WOFFSET                       0x0
+#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_HSM_EN_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_HSM_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_HSM_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_HSM_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_HSM_EN_DISABLE                       _MK_ENUM_CONST(0)
+#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_HSM_EN_ENABLE                        _MK_ENUM_CONST(1)
+
+// SDIO3CFG data pins schmidt enable
+#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_SCHMT_EN_SHIFT                       _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_SCHMT_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_SCHMT_EN_RANGE                       3:3
+#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_SCHMT_EN_WOFFSET                     0x0
+#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_SCHMT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_SCHMT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_SCHMT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_SCHMT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_SCHMT_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_SCHMT_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// SDIO3CFG data pins low power mode select
+#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_LPMD_SHIFT                   _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_LPMD_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_LPMD_SHIFT)
+#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_LPMD_RANGE                   5:4
+#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_LPMD_WOFFSET                 0x0
+#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_LPMD_DEFAULT                 _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_LPMD_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_LPMD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_LPMD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_CAL_DRVDN_SHIFT                      _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_CAL_DRVDN_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_CAL_DRVDN_RANGE                      16:12
+#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_CAL_DRVDN_WOFFSET                    0x0
+#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_CAL_DRVDN_DEFAULT                    _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_CAL_DRVDN_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_CAL_DRVDN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_CAL_DRVDN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_CAL_DRVUP_SHIFT                      _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_CAL_DRVUP_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_CAL_DRVUP_RANGE                      24:20
+#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_CAL_DRVUP_WOFFSET                    0x0
+#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_CAL_DRVUP_DEFAULT                    _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_CAL_DRVUP_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_CAL_DRVUP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_CAL_DRVUP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_CAL_DRVDN_SLWR_SHIFT                 _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_CAL_DRVDN_SLWR_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_CAL_DRVDN_SLWR_RANGE                 29:28
+#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_CAL_DRVDN_SLWR_WOFFSET                       0x0
+#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_CAL_DRVDN_SLWR_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_CAL_DRVDN_SLWR_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_CAL_DRVDN_SLWR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_CAL_DRVUP_SLWF_SHIFT                 _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_CAL_DRVUP_SLWF_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_CAL_DRVUP_SLWF_RANGE                 31:30
+#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_CAL_DRVUP_SLWF_WOFFSET                       0x0
+#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_CAL_DRVUP_SLWF_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_CAL_DRVUP_SLWF_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_CAL_DRVUP_SLWF_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_GMCCFGPADCTRL_0  //        0       rw  CFG2TMC_GMCCFG_PULLD_EN   i=0x0   // SDIO3CFG pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_GMCCFG_PULLU_EN   i=0x0   // SDIO3CFG pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_GMCCFGPADCTRL_0                     _MK_ADDR_CONST(0x8fc)
+#define APB_MISC_GP_GMCCFGPADCTRL_0_SECURE                      0x0
+#define APB_MISC_GP_GMCCFGPADCTRL_0_WORD_COUNT                  0x1
+#define APB_MISC_GP_GMCCFGPADCTRL_0_RESET_VAL                   _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_GMCCFGPADCTRL_0_RESET_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_GMCCFGPADCTRL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMCCFGPADCTRL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMCCFGPADCTRL_0_READ_MASK                   _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_GMCCFGPADCTRL_0_WRITE_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+// SDIO3CFG data pins high speed mode enable
+#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_HSM_EN_SHIFT                 _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_HSM_EN_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_HSM_EN_SHIFT)
+#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_HSM_EN_RANGE                 2:2
+#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_HSM_EN_WOFFSET                       0x0
+#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_HSM_EN_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_HSM_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_HSM_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_HSM_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_HSM_EN_DISABLE                       _MK_ENUM_CONST(0)
+#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_HSM_EN_ENABLE                        _MK_ENUM_CONST(1)
+
+// SDIO3CFG data pins schmidt enable
+#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_SCHMT_EN_SHIFT                       _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_SCHMT_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_SCHMT_EN_RANGE                       3:3
+#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_SCHMT_EN_WOFFSET                     0x0
+#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_SCHMT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_SCHMT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_SCHMT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_SCHMT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_SCHMT_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_SCHMT_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// SDIO3CFG data pins low power mode select
+#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_LPMD_SHIFT                   _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_LPMD_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_LPMD_SHIFT)
+#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_LPMD_RANGE                   5:4
+#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_LPMD_WOFFSET                 0x0
+#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_LPMD_DEFAULT                 _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_LPMD_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_LPMD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_LPMD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_CAL_DRVDN_SHIFT                      _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_CAL_DRVDN_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_CAL_DRVDN_RANGE                      16:12
+#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_CAL_DRVDN_WOFFSET                    0x0
+#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_CAL_DRVDN_DEFAULT                    _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_CAL_DRVDN_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_CAL_DRVDN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_CAL_DRVDN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_CAL_DRVUP_SHIFT                      _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_CAL_DRVUP_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_CAL_DRVUP_RANGE                      24:20
+#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_CAL_DRVUP_WOFFSET                    0x0
+#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_CAL_DRVUP_DEFAULT                    _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_CAL_DRVUP_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_CAL_DRVUP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_CAL_DRVUP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_CAL_DRVDN_SLWR_SHIFT                 _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_CAL_DRVDN_SLWR_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_CAL_DRVDN_SLWR_RANGE                 29:28
+#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_CAL_DRVDN_SLWR_WOFFSET                       0x0
+#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_CAL_DRVDN_SLWR_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_CAL_DRVDN_SLWR_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_CAL_DRVDN_SLWR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_CAL_DRVUP_SLWF_SHIFT                 _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_CAL_DRVUP_SLWF_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_CAL_DRVUP_SLWF_RANGE                 31:30
+#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_CAL_DRVUP_SLWF_WOFFSET                       0x0
+#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_CAL_DRVUP_SLWF_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_CAL_DRVUP_SLWF_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_CAL_DRVUP_SLWF_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_GMDCFGPADCTRL_0  //        0       rw  CFG2TMC_GMDCFG_PULLD_EN   i=0x0   // SDIO3CFG pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_GMDCFG_PULLU_EN   i=0x0   // SDIO3CFG pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_GMDCFGPADCTRL_0                     _MK_ADDR_CONST(0x900)
+#define APB_MISC_GP_GMDCFGPADCTRL_0_SECURE                      0x0
+#define APB_MISC_GP_GMDCFGPADCTRL_0_WORD_COUNT                  0x1
+#define APB_MISC_GP_GMDCFGPADCTRL_0_RESET_VAL                   _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_GMDCFGPADCTRL_0_RESET_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_GMDCFGPADCTRL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMDCFGPADCTRL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMDCFGPADCTRL_0_READ_MASK                   _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_GMDCFGPADCTRL_0_WRITE_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+// SDIO3CFG data pins high speed mode enable
+#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_HSM_EN_SHIFT                 _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_HSM_EN_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_HSM_EN_SHIFT)
+#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_HSM_EN_RANGE                 2:2
+#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_HSM_EN_WOFFSET                       0x0
+#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_HSM_EN_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_HSM_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_HSM_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_HSM_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_HSM_EN_DISABLE                       _MK_ENUM_CONST(0)
+#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_HSM_EN_ENABLE                        _MK_ENUM_CONST(1)
+
+// SDIO3CFG data pins schmidt enable
+#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_SCHMT_EN_SHIFT                       _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_SCHMT_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_SCHMT_EN_RANGE                       3:3
+#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_SCHMT_EN_WOFFSET                     0x0
+#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_SCHMT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_SCHMT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_SCHMT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_SCHMT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_SCHMT_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_SCHMT_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// SDIO3CFG data pins low power mode select
+#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_LPMD_SHIFT                   _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_LPMD_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_LPMD_SHIFT)
+#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_LPMD_RANGE                   5:4
+#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_LPMD_WOFFSET                 0x0
+#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_LPMD_DEFAULT                 _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_LPMD_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_LPMD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_LPMD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_CAL_DRVDN_SHIFT                      _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_CAL_DRVDN_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_CAL_DRVDN_RANGE                      16:12
+#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_CAL_DRVDN_WOFFSET                    0x0
+#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_CAL_DRVDN_DEFAULT                    _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_CAL_DRVDN_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_CAL_DRVDN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_CAL_DRVDN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_CAL_DRVUP_SHIFT                      _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_CAL_DRVUP_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_CAL_DRVUP_RANGE                      24:20
+#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_CAL_DRVUP_WOFFSET                    0x0
+#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_CAL_DRVUP_DEFAULT                    _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_CAL_DRVUP_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_CAL_DRVUP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_CAL_DRVUP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_CAL_DRVDN_SLWR_SHIFT                 _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_CAL_DRVDN_SLWR_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_CAL_DRVDN_SLWR_RANGE                 29:28
+#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_CAL_DRVDN_SLWR_WOFFSET                       0x0
+#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_CAL_DRVDN_SLWR_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_CAL_DRVDN_SLWR_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_CAL_DRVDN_SLWR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_CAL_DRVUP_SLWF_SHIFT                 _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_CAL_DRVUP_SLWF_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_CAL_DRVUP_SLWF_RANGE                 31:30
+#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_CAL_DRVUP_SLWF_WOFFSET                       0x0
+#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_CAL_DRVUP_SLWF_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_CAL_DRVUP_SLWF_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_CAL_DRVUP_SLWF_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_GMECFGPADCTRL_0  //        0       rw  CFG2TMC_GMECFG_PULLD_EN   i=0x0   // SDIO3CFG pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_GMECFG_PULLU_EN   i=0x0   // SDIO3CFG pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_GMECFGPADCTRL_0                     _MK_ADDR_CONST(0x904)
+#define APB_MISC_GP_GMECFGPADCTRL_0_SECURE                      0x0
+#define APB_MISC_GP_GMECFGPADCTRL_0_WORD_COUNT                  0x1
+#define APB_MISC_GP_GMECFGPADCTRL_0_RESET_VAL                   _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_GMECFGPADCTRL_0_RESET_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_GMECFGPADCTRL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMECFGPADCTRL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMECFGPADCTRL_0_READ_MASK                   _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_GMECFGPADCTRL_0_WRITE_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+// SDIO3CFG data pins high speed mode enable
+#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_HSM_EN_SHIFT                 _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_HSM_EN_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_HSM_EN_SHIFT)
+#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_HSM_EN_RANGE                 2:2
+#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_HSM_EN_WOFFSET                       0x0
+#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_HSM_EN_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_HSM_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_HSM_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_HSM_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_HSM_EN_DISABLE                       _MK_ENUM_CONST(0)
+#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_HSM_EN_ENABLE                        _MK_ENUM_CONST(1)
+
+// SDIO3CFG data pins schmidt enable
+#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_SCHMT_EN_SHIFT                       _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_SCHMT_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_SCHMT_EN_RANGE                       3:3
+#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_SCHMT_EN_WOFFSET                     0x0
+#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_SCHMT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_SCHMT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_SCHMT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_SCHMT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_SCHMT_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_SCHMT_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// SDIO3CFG data pins low power mode select
+#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_LPMD_SHIFT                   _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_LPMD_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_LPMD_SHIFT)
+#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_LPMD_RANGE                   5:4
+#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_LPMD_WOFFSET                 0x0
+#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_LPMD_DEFAULT                 _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_LPMD_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_LPMD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_LPMD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_CAL_DRVDN_SHIFT                      _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_CAL_DRVDN_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_CAL_DRVDN_RANGE                      16:12
+#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_CAL_DRVDN_WOFFSET                    0x0
+#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_CAL_DRVDN_DEFAULT                    _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_CAL_DRVDN_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_CAL_DRVDN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_CAL_DRVDN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_CAL_DRVUP_SHIFT                      _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_CAL_DRVUP_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_CAL_DRVUP_RANGE                      24:20
+#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_CAL_DRVUP_WOFFSET                    0x0
+#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_CAL_DRVUP_DEFAULT                    _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_CAL_DRVUP_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_CAL_DRVUP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_CAL_DRVUP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_CAL_DRVDN_SLWR_SHIFT                 _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_CAL_DRVDN_SLWR_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_CAL_DRVDN_SLWR_RANGE                 29:28
+#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_CAL_DRVDN_SLWR_WOFFSET                       0x0
+#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_CAL_DRVDN_SLWR_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_CAL_DRVDN_SLWR_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_CAL_DRVDN_SLWR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_CAL_DRVUP_SLWF_SHIFT                 _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_CAL_DRVUP_SLWF_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_CAL_DRVUP_SLWF_RANGE                 31:30
+#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_CAL_DRVUP_SLWF_WOFFSET                       0x0
+#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_CAL_DRVUP_SLWF_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_CAL_DRVUP_SLWF_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_CAL_DRVUP_SLWF_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_OWRCFGPADCTRL_0  //        0       rw  CFG2TMC_OWRCFG_PULLD_EN   i=0x0   // SDIO3CFG pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_OWRCFG_PULLU_EN   i=0x0   // SDIO3CFG pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_OWRCFGPADCTRL_0                     _MK_ADDR_CONST(0x908)
+#define APB_MISC_GP_OWRCFGPADCTRL_0_SECURE                      0x0
+#define APB_MISC_GP_OWRCFGPADCTRL_0_WORD_COUNT                  0x1
+#define APB_MISC_GP_OWRCFGPADCTRL_0_RESET_VAL                   _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_OWRCFGPADCTRL_0_RESET_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_OWRCFGPADCTRL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OWRCFGPADCTRL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OWRCFGPADCTRL_0_READ_MASK                   _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_OWRCFGPADCTRL_0_WRITE_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+// SDIO3CFG data pins high speed mode enable
+#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_HSM_EN_SHIFT                 _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_HSM_EN_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_HSM_EN_SHIFT)
+#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_HSM_EN_RANGE                 2:2
+#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_HSM_EN_WOFFSET                       0x0
+#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_HSM_EN_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_HSM_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_HSM_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_HSM_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_HSM_EN_DISABLE                       _MK_ENUM_CONST(0)
+#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_HSM_EN_ENABLE                        _MK_ENUM_CONST(1)
+
+// SDIO3CFG data pins schmidt enable
+#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_SCHMT_EN_SHIFT                       _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_SCHMT_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_SCHMT_EN_RANGE                       3:3
+#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_SCHMT_EN_WOFFSET                     0x0
+#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_SCHMT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_SCHMT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_SCHMT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_SCHMT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_SCHMT_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_SCHMT_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// SDIO3CFG data pins low power mode select
+#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_LPMD_SHIFT                   _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_LPMD_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_LPMD_SHIFT)
+#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_LPMD_RANGE                   5:4
+#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_LPMD_WOFFSET                 0x0
+#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_LPMD_DEFAULT                 _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_LPMD_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_LPMD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_LPMD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_CAL_DRVDN_SHIFT                      _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_CAL_DRVDN_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_CAL_DRVDN_RANGE                      16:12
+#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_CAL_DRVDN_WOFFSET                    0x0
+#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_CAL_DRVDN_DEFAULT                    _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_CAL_DRVDN_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_CAL_DRVDN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_CAL_DRVDN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_CAL_DRVUP_SHIFT                      _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_CAL_DRVUP_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_CAL_DRVUP_RANGE                      24:20
+#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_CAL_DRVUP_WOFFSET                    0x0
+#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_CAL_DRVUP_DEFAULT                    _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_CAL_DRVUP_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_CAL_DRVUP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_CAL_DRVUP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_CAL_DRVDN_SLWR_SHIFT                 _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_CAL_DRVDN_SLWR_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_CAL_DRVDN_SLWR_RANGE                 29:28
+#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_CAL_DRVDN_SLWR_WOFFSET                       0x0
+#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_CAL_DRVDN_SLWR_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_CAL_DRVDN_SLWR_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_CAL_DRVDN_SLWR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_CAL_DRVUP_SLWF_SHIFT                 _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_CAL_DRVUP_SLWF_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_CAL_DRVUP_SLWF_RANGE                 31:30
+#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_CAL_DRVUP_SLWF_WOFFSET                       0x0
+#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_CAL_DRVUP_SLWF_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_CAL_DRVUP_SLWF_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_CAL_DRVUP_SLWF_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_UADCFGPADCTRL_0  //        0       rw  CFG2TMC_UDACFG_PULLD_EN   i=0x0   // SDIO3CFG pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_UDACFG_PULLU_EN   i=0x0   // SDIO3CFG pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_UADCFGPADCTRL_0                     _MK_ADDR_CONST(0x90c)
+#define APB_MISC_GP_UADCFGPADCTRL_0_SECURE                      0x0
+#define APB_MISC_GP_UADCFGPADCTRL_0_WORD_COUNT                  0x1
+#define APB_MISC_GP_UADCFGPADCTRL_0_RESET_VAL                   _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_UADCFGPADCTRL_0_RESET_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_UADCFGPADCTRL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UADCFGPADCTRL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UADCFGPADCTRL_0_READ_MASK                   _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_UADCFGPADCTRL_0_WRITE_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+// SDIO3CFG data pins high speed mode enable
+#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_HSM_EN_SHIFT                 _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_HSM_EN_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_HSM_EN_SHIFT)
+#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_HSM_EN_RANGE                 2:2
+#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_HSM_EN_WOFFSET                       0x0
+#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_HSM_EN_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_HSM_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_HSM_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_HSM_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_HSM_EN_DISABLE                       _MK_ENUM_CONST(0)
+#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_HSM_EN_ENABLE                        _MK_ENUM_CONST(1)
+
+// SDIO3CFG data pins schmidt enable
+#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_SCHMT_EN_SHIFT                       _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_SCHMT_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_SCHMT_EN_RANGE                       3:3
+#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_SCHMT_EN_WOFFSET                     0x0
+#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_SCHMT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_SCHMT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_SCHMT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_SCHMT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_SCHMT_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_SCHMT_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// SDIO3CFG data pins low power mode select
+#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_LPMD_SHIFT                   _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_LPMD_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_LPMD_SHIFT)
+#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_LPMD_RANGE                   5:4
+#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_LPMD_WOFFSET                 0x0
+#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_LPMD_DEFAULT                 _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_LPMD_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_LPMD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_LPMD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_CAL_DRVDN_SHIFT                      _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_CAL_DRVDN_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_CAL_DRVDN_RANGE                      16:12
+#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_CAL_DRVDN_WOFFSET                    0x0
+#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_CAL_DRVDN_DEFAULT                    _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_CAL_DRVDN_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_CAL_DRVDN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_CAL_DRVDN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_CAL_DRVUP_SHIFT                      _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_CAL_DRVUP_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_CAL_DRVUP_RANGE                      24:20
+#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_CAL_DRVUP_WOFFSET                    0x0
+#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_CAL_DRVUP_DEFAULT                    _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_CAL_DRVUP_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_CAL_DRVUP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_CAL_DRVUP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_CAL_DRVDN_SLWR_SHIFT                 _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_CAL_DRVDN_SLWR_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_CAL_DRVDN_SLWR_RANGE                 29:28
+#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_CAL_DRVDN_SLWR_WOFFSET                       0x0
+#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_CAL_DRVDN_SLWR_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_CAL_DRVDN_SLWR_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_CAL_DRVDN_SLWR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_CAL_DRVUP_SLWF_SHIFT                 _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_CAL_DRVUP_SLWF_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_CAL_DRVUP_SLWF_RANGE                 31:30
+#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_CAL_DRVUP_SLWF_WOFFSET                       0x0
+#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_CAL_DRVUP_SLWF_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_CAL_DRVUP_SLWF_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_CAL_DRVUP_SLWF_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_AVP_TRANSACTOR_SCRATCH_0  
+#define APB_MISC_GP_AVP_TRANSACTOR_SCRATCH_0                    _MK_ADDR_CONST(0x920)
+#define APB_MISC_GP_AVP_TRANSACTOR_SCRATCH_0_SECURE                     0x0
+#define APB_MISC_GP_AVP_TRANSACTOR_SCRATCH_0_WORD_COUNT                         0x1
+#define APB_MISC_GP_AVP_TRANSACTOR_SCRATCH_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AVP_TRANSACTOR_SCRATCH_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_GP_AVP_TRANSACTOR_SCRATCH_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AVP_TRANSACTOR_SCRATCH_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AVP_TRANSACTOR_SCRATCH_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_GP_AVP_TRANSACTOR_SCRATCH_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+// used for emulation to determine test results.
+#define APB_MISC_GP_AVP_TRANSACTOR_SCRATCH_0_AVP_TRANSACTOR_SCRATCH_SHIFT                       _MK_SHIFT_CONST(0)
+#define APB_MISC_GP_AVP_TRANSACTOR_SCRATCH_0_AVP_TRANSACTOR_SCRATCH_FIELD                       (_MK_MASK_CONST(0xffffffff) << APB_MISC_GP_AVP_TRANSACTOR_SCRATCH_0_AVP_TRANSACTOR_SCRATCH_SHIFT)
+#define APB_MISC_GP_AVP_TRANSACTOR_SCRATCH_0_AVP_TRANSACTOR_SCRATCH_RANGE                       31:0
+#define APB_MISC_GP_AVP_TRANSACTOR_SCRATCH_0_AVP_TRANSACTOR_SCRATCH_WOFFSET                     0x0
+#define APB_MISC_GP_AVP_TRANSACTOR_SCRATCH_0_AVP_TRANSACTOR_SCRATCH_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AVP_TRANSACTOR_SCRATCH_0_AVP_TRANSACTOR_SCRATCH_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_GP_AVP_TRANSACTOR_SCRATCH_0_AVP_TRANSACTOR_SCRATCH_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AVP_TRANSACTOR_SCRATCH_0_AVP_TRANSACTOR_SCRATCH_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_CPU0_TRANSACTOR_SCRATCH_0  
+#define APB_MISC_GP_CPU0_TRANSACTOR_SCRATCH_0                   _MK_ADDR_CONST(0x924)
+#define APB_MISC_GP_CPU0_TRANSACTOR_SCRATCH_0_SECURE                    0x0
+#define APB_MISC_GP_CPU0_TRANSACTOR_SCRATCH_0_WORD_COUNT                        0x1
+#define APB_MISC_GP_CPU0_TRANSACTOR_SCRATCH_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CPU0_TRANSACTOR_SCRATCH_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_GP_CPU0_TRANSACTOR_SCRATCH_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CPU0_TRANSACTOR_SCRATCH_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CPU0_TRANSACTOR_SCRATCH_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_GP_CPU0_TRANSACTOR_SCRATCH_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
+// used for emulation to determine test results.
+#define APB_MISC_GP_CPU0_TRANSACTOR_SCRATCH_0_CPU0_TRANSACTOR_SCRATCH_SHIFT                     _MK_SHIFT_CONST(0)
+#define APB_MISC_GP_CPU0_TRANSACTOR_SCRATCH_0_CPU0_TRANSACTOR_SCRATCH_FIELD                     (_MK_MASK_CONST(0xffffffff) << APB_MISC_GP_CPU0_TRANSACTOR_SCRATCH_0_CPU0_TRANSACTOR_SCRATCH_SHIFT)
+#define APB_MISC_GP_CPU0_TRANSACTOR_SCRATCH_0_CPU0_TRANSACTOR_SCRATCH_RANGE                     31:0
+#define APB_MISC_GP_CPU0_TRANSACTOR_SCRATCH_0_CPU0_TRANSACTOR_SCRATCH_WOFFSET                   0x0
+#define APB_MISC_GP_CPU0_TRANSACTOR_SCRATCH_0_CPU0_TRANSACTOR_SCRATCH_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CPU0_TRANSACTOR_SCRATCH_0_CPU0_TRANSACTOR_SCRATCH_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_GP_CPU0_TRANSACTOR_SCRATCH_0_CPU0_TRANSACTOR_SCRATCH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CPU0_TRANSACTOR_SCRATCH_0_CPU0_TRANSACTOR_SCRATCH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_CPU1_TRANSACTOR_SCRATCH_0  
+#define APB_MISC_GP_CPU1_TRANSACTOR_SCRATCH_0                   _MK_ADDR_CONST(0x928)
+#define APB_MISC_GP_CPU1_TRANSACTOR_SCRATCH_0_SECURE                    0x0
+#define APB_MISC_GP_CPU1_TRANSACTOR_SCRATCH_0_WORD_COUNT                        0x1
+#define APB_MISC_GP_CPU1_TRANSACTOR_SCRATCH_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CPU1_TRANSACTOR_SCRATCH_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_GP_CPU1_TRANSACTOR_SCRATCH_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CPU1_TRANSACTOR_SCRATCH_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CPU1_TRANSACTOR_SCRATCH_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_GP_CPU1_TRANSACTOR_SCRATCH_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
+// used for emulation to determine test results.
+#define APB_MISC_GP_CPU1_TRANSACTOR_SCRATCH_0_CPU1_TRANSACTOR_SCRATCH_SHIFT                     _MK_SHIFT_CONST(0)
+#define APB_MISC_GP_CPU1_TRANSACTOR_SCRATCH_0_CPU1_TRANSACTOR_SCRATCH_FIELD                     (_MK_MASK_CONST(0xffffffff) << APB_MISC_GP_CPU1_TRANSACTOR_SCRATCH_0_CPU1_TRANSACTOR_SCRATCH_SHIFT)
+#define APB_MISC_GP_CPU1_TRANSACTOR_SCRATCH_0_CPU1_TRANSACTOR_SCRATCH_RANGE                     31:0
+#define APB_MISC_GP_CPU1_TRANSACTOR_SCRATCH_0_CPU1_TRANSACTOR_SCRATCH_WOFFSET                   0x0
+#define APB_MISC_GP_CPU1_TRANSACTOR_SCRATCH_0_CPU1_TRANSACTOR_SCRATCH_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CPU1_TRANSACTOR_SCRATCH_0_CPU1_TRANSACTOR_SCRATCH_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_GP_CPU1_TRANSACTOR_SCRATCH_0_CPU1_TRANSACTOR_SCRATCH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CPU1_TRANSACTOR_SCRATCH_0_CPU1_TRANSACTOR_SCRATCH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_DEV_PRESENT0_0  
+#define APB_MISC_GP_DEV_PRESENT0_0                      _MK_ADDR_CONST(0x92c)
+#define APB_MISC_GP_DEV_PRESENT0_0_SECURE                       0x0
+#define APB_MISC_GP_DEV_PRESENT0_0_WORD_COUNT                   0x1
+#define APB_MISC_GP_DEV_PRESENT0_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_RESET_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_GP_DEV_PRESENT0_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EMEM_SHIFT                       _MK_SHIFT_CONST(0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EMEM_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EMEM_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EMEM_RANGE                       0:0
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EMEM_WOFFSET                     0x0
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EMEM_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EMEM_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EMEM_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EMEM_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_IRAM_A_SHIFT                     _MK_SHIFT_CONST(1)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_IRAM_A_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_IRAM_A_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_IRAM_A_RANGE                     1:1
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_IRAM_A_WOFFSET                   0x0
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_IRAM_A_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_IRAM_A_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_IRAM_A_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_IRAM_A_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_IRAM_B_SHIFT                     _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_IRAM_B_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_IRAM_B_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_IRAM_B_RANGE                     2:2
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_IRAM_B_WOFFSET                   0x0
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_IRAM_B_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_IRAM_B_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_IRAM_B_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_IRAM_B_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_IRAM_C_SHIFT                     _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_IRAM_C_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_IRAM_C_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_IRAM_C_RANGE                     3:3
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_IRAM_C_WOFFSET                   0x0
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_IRAM_C_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_IRAM_C_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_IRAM_C_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_IRAM_C_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_IRAM_D_SHIFT                     _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_IRAM_D_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_IRAM_D_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_IRAM_D_RANGE                     4:4
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_IRAM_D_WOFFSET                   0x0
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_IRAM_D_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_IRAM_D_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_IRAM_D_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_IRAM_D_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_NOR_SHIFT                        _MK_SHIFT_CONST(5)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_NOR_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_NOR_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_NOR_RANGE                        5:5
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_NOR_WOFFSET                      0x0
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_NOR_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_NOR_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_NOR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_NOR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EXIO1_SHIFT                      _MK_SHIFT_CONST(6)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EXIO1_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EXIO1_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EXIO1_RANGE                      6:6
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EXIO1_WOFFSET                    0x0
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EXIO1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EXIO1_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EXIO1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EXIO1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EXIO2_SHIFT                      _MK_SHIFT_CONST(7)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EXIO2_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EXIO2_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EXIO2_RANGE                      7:7
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EXIO2_WOFFSET                    0x0
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EXIO2_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EXIO2_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EXIO2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EXIO2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_GART_SHIFT                       _MK_SHIFT_CONST(8)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_GART_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_GART_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_GART_RANGE                       8:8
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_GART_WOFFSET                     0x0
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_GART_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_GART_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_GART_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_GART_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_HOST1X_SHIFT                     _MK_SHIFT_CONST(9)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_HOST1X_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_HOST1X_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_HOST1X_RANGE                     9:9
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_HOST1X_WOFFSET                   0x0
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_HOST1X_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_HOST1X_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_HOST1X_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_HOST1X_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_ARM_PERIPH_SHIFT                 _MK_SHIFT_CONST(10)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_ARM_PERIPH_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_ARM_PERIPH_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_ARM_PERIPH_RANGE                 10:10
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_ARM_PERIPH_WOFFSET                       0x0
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_ARM_PERIPH_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_ARM_PERIPH_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_ARM_PERIPH_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_ARM_PERIPH_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_MSELECT_SHIFT                    _MK_SHIFT_CONST(11)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_MSELECT_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_MSELECT_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_MSELECT_RANGE                    11:11
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_MSELECT_WOFFSET                  0x0
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_MSELECT_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_MSELECT_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_MSELECT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_MSELECT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_MC_SHIFT                 _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_MC_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_MC_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_MC_RANGE                 12:12
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_MC_WOFFSET                       0x0
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_MC_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_MC_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_MC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_MC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EMC_SHIFT                        _MK_SHIFT_CONST(13)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EMC_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EMC_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EMC_RANGE                        13:13
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EMC_WOFFSET                      0x0
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EMC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EMC_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EMC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EMC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_VI_SHIFT                 _MK_SHIFT_CONST(14)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_VI_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_VI_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_VI_RANGE                 14:14
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_VI_WOFFSET                       0x0
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_VI_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_VI_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_VI_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_VI_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EPP_SHIFT                        _MK_SHIFT_CONST(15)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EPP_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EPP_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EPP_RANGE                        15:15
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EPP_WOFFSET                      0x0
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EPP_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EPP_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EPP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EPP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_MPE_SHIFT                        _MK_SHIFT_CONST(16)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_MPE_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_MPE_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_MPE_RANGE                        16:16
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_MPE_WOFFSET                      0x0
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_MPE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_MPE_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_MPE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_MPE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_GR3D_SHIFT                       _MK_SHIFT_CONST(17)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_GR3D_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_GR3D_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_GR3D_RANGE                       17:17
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_GR3D_WOFFSET                     0x0
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_GR3D_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_GR3D_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_GR3D_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_GR3D_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_GR2D_SHIFT                       _MK_SHIFT_CONST(18)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_GR2D_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_GR2D_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_GR2D_RANGE                       18:18
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_GR2D_WOFFSET                     0x0
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_GR2D_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_GR2D_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_GR2D_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_GR2D_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_ISP_SHIFT                        _MK_SHIFT_CONST(19)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_ISP_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_ISP_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_ISP_RANGE                        19:19
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_ISP_WOFFSET                      0x0
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_ISP_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_ISP_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_ISP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_ISP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_DISPLAY_SHIFT                    _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_DISPLAY_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_DISPLAY_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_DISPLAY_RANGE                    20:20
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_DISPLAY_WOFFSET                  0x0
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_DISPLAY_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_DISPLAY_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_DISPLAY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_DISPLAY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_DISPLAYB_SHIFT                   _MK_SHIFT_CONST(21)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_DISPLAYB_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_DISPLAYB_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_DISPLAYB_RANGE                   21:21
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_DISPLAYB_WOFFSET                 0x0
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_DISPLAYB_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_DISPLAYB_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_DISPLAYB_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_DISPLAYB_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_UPTAG_SHIFT                      _MK_SHIFT_CONST(22)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_UPTAG_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_UPTAG_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_UPTAG_RANGE                      22:22
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_UPTAG_WOFFSET                    0x0
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_UPTAG_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_UPTAG_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_UPTAG_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_UPTAG_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_SHR_SEM_SHIFT                    _MK_SHIFT_CONST(23)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_SHR_SEM_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_SHR_SEM_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_SHR_SEM_RANGE                    23:23
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_SHR_SEM_WOFFSET                  0x0
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_SHR_SEM_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_SHR_SEM_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_SHR_SEM_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_SHR_SEM_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_ARB_SEM_SHIFT                    _MK_SHIFT_CONST(24)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_ARB_SEM_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_ARB_SEM_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_ARB_SEM_RANGE                    24:24
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_ARB_SEM_WOFFSET                  0x0
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_ARB_SEM_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_ARB_SEM_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_ARB_SEM_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_ARB_SEM_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_ARB_PRI_SHIFT                    _MK_SHIFT_CONST(25)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_ARB_PRI_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_ARB_PRI_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_ARB_PRI_RANGE                    25:25
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_ARB_PRI_WOFFSET                  0x0
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_ARB_PRI_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_ARB_PRI_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_ARB_PRI_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_ARB_PRI_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_TMR1_SHIFT                       _MK_SHIFT_CONST(26)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_TMR1_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_TMR1_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_TMR1_RANGE                       26:26
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_TMR1_WOFFSET                     0x0
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_TMR1_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_TMR1_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_TMR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_TMR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_TMR2_SHIFT                       _MK_SHIFT_CONST(27)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_TMR2_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_TMR2_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_TMR2_RANGE                       27:27
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_TMR2_WOFFSET                     0x0
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_TMR2_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_TMR2_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_TMR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_TMR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_TMR3_SHIFT                       _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_TMR3_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_TMR3_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_TMR3_RANGE                       28:28
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_TMR3_WOFFSET                     0x0
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_TMR3_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_TMR3_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_TMR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_TMR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_TMR4_SHIFT                       _MK_SHIFT_CONST(29)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_TMR4_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_TMR4_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_TMR4_RANGE                       29:29
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_TMR4_WOFFSET                     0x0
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_TMR4_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_TMR4_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_TMR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_TMR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_CAR_SHIFT                        _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_CAR_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_CAR_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_CAR_RANGE                        30:30
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_CAR_WOFFSET                      0x0
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_CAR_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_CAR_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_CAR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_CAR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_FLOW_SHIFT                       _MK_SHIFT_CONST(31)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_FLOW_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_FLOW_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_FLOW_RANGE                       31:31
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_FLOW_WOFFSET                     0x0
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_FLOW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_FLOW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_FLOW_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_FLOW_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_DEV_PRESENT1_0  
+#define APB_MISC_GP_DEV_PRESENT1_0                      _MK_ADDR_CONST(0x930)
+#define APB_MISC_GP_DEV_PRESENT1_0_SECURE                       0x0
+#define APB_MISC_GP_DEV_PRESENT1_0_WORD_COUNT                   0x1
+#define APB_MISC_GP_DEV_PRESENT1_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_RESET_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_GP_DEV_PRESENT1_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_AHB_DMA_SHIFT                    _MK_SHIFT_CONST(0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_AHB_DMA_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_AHB_DMA_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_AHB_DMA_RANGE                    0:0
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_AHB_DMA_WOFFSET                  0x0
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_AHB_DMA_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_AHB_DMA_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_AHB_DMA_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_AHB_DMA_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_APB_DMA_SHIFT                    _MK_SHIFT_CONST(1)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_APB_DMA_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_APB_DMA_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_APB_DMA_RANGE                    1:1
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_APB_DMA_WOFFSET                  0x0
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_APB_DMA_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_APB_DMA_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_APB_DMA_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_APB_DMA_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_COP_CACHE_SHIFT                  _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_COP_CACHE_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_COP_CACHE_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_COP_CACHE_RANGE                  2:2
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_COP_CACHE_WOFFSET                        0x0
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_COP_CACHE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_COP_CACHE_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_COP_CACHE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_COP_CACHE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_STAT_SHIFT                       _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_STAT_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_STAT_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_STAT_RANGE                       3:3
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_STAT_WOFFSET                     0x0
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_STAT_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_STAT_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_STAT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_STAT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO1_SHIFT                      _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO1_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO1_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO1_RANGE                      4:4
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO1_WOFFSET                    0x0
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO1_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO2_SHIFT                      _MK_SHIFT_CONST(5)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO2_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO2_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO2_RANGE                      5:5
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO2_WOFFSET                    0x0
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO2_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO2_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO3_SHIFT                      _MK_SHIFT_CONST(6)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO3_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO3_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO3_RANGE                      6:6
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO3_WOFFSET                    0x0
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO3_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO3_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO4_SHIFT                      _MK_SHIFT_CONST(7)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO4_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO4_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO4_RANGE                      7:7
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO4_WOFFSET                    0x0
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO4_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO4_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO4_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO4_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO5_SHIFT                      _MK_SHIFT_CONST(8)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO5_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO5_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO5_RANGE                      8:8
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO5_WOFFSET                    0x0
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO5_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO5_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO5_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO5_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO6_SHIFT                      _MK_SHIFT_CONST(9)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO6_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO6_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO6_RANGE                      9:9
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO6_WOFFSET                    0x0
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO6_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO6_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO6_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO6_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO7_SHIFT                      _MK_SHIFT_CONST(10)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO7_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO7_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO7_RANGE                      10:10
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO7_WOFFSET                    0x0
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO7_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO7_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO7_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO7_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_VCP_SHIFT                        _MK_SHIFT_CONST(11)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_VCP_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_VCP_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_VCP_RANGE                        11:11
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_VCP_WOFFSET                      0x0
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_VCP_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_VCP_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_VCP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_VCP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_VECTOR_SHIFT                     _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_VECTOR_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_VECTOR_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_VECTOR_RANGE                     12:12
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_VECTOR_WOFFSET                   0x0
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_VECTOR_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_VECTOR_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_VECTOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_VECTOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_VDE_SHIFT                        _MK_SHIFT_CONST(13)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_VDE_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_VDE_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_VDE_RANGE                        13:13
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_VDE_WOFFSET                      0x0
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_VDE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_VDE_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_VDE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_VDE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_BSEA_SHIFT                       _MK_SHIFT_CONST(14)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_BSEA_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_BSEA_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_BSEA_RANGE                       14:14
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_BSEA_WOFFSET                     0x0
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_BSEA_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_BSEA_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_BSEA_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_BSEA_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_MISC_SHIFT                       _MK_SHIFT_CONST(15)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_MISC_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_MISC_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_MISC_RANGE                       15:15
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_MISC_WOFFSET                     0x0
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_MISC_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_MISC_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_MISC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_MISC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_AC97_SHIFT                       _MK_SHIFT_CONST(16)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_AC97_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_AC97_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_AC97_RANGE                       16:16
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_AC97_WOFFSET                     0x0
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_AC97_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_AC97_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_AC97_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_AC97_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_SPDIF_SHIFT                      _MK_SHIFT_CONST(17)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_SPDIF_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_SPDIF_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_SPDIF_RANGE                      17:17
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_SPDIF_WOFFSET                    0x0
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_SPDIF_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_SPDIF_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_SPDIF_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_SPDIF_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_I2S1_SHIFT                       _MK_SHIFT_CONST(18)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_I2S1_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_I2S1_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_I2S1_RANGE                       18:18
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_I2S1_WOFFSET                     0x0
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_I2S1_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_I2S1_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_I2S1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_I2S1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_I2S2_SHIFT                       _MK_SHIFT_CONST(19)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_I2S2_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_I2S2_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_I2S2_RANGE                       19:19
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_I2S2_WOFFSET                     0x0
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_I2S2_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_I2S2_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_I2S2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_I2S2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTA_SHIFT                      _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTA_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTA_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTA_RANGE                      20:20
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTA_WOFFSET                    0x0
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTA_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTA_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTA_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTA_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTB_SHIFT                      _MK_SHIFT_CONST(21)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTB_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTB_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTB_RANGE                      21:21
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTB_WOFFSET                    0x0
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTB_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTB_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTB_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTB_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTC_SHIFT                      _MK_SHIFT_CONST(22)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTC_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTC_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTC_RANGE                      22:22
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTC_WOFFSET                    0x0
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTC_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTC_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTC_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTC_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTD_SHIFT                      _MK_SHIFT_CONST(23)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTD_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTD_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTD_RANGE                      23:23
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTD_WOFFSET                    0x0
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTD_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTD_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTD_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTD_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTE_SHIFT                      _MK_SHIFT_CONST(24)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTE_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTE_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTE_RANGE                      24:24
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTE_WOFFSET                    0x0
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTE_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_VFIR_SHIFT                       _MK_SHIFT_CONST(25)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_VFIR_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_VFIR_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_VFIR_RANGE                       25:25
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_VFIR_WOFFSET                     0x0
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_VFIR_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_VFIR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_VFIR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_VFIR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_NANDCTRL_SHIFT                   _MK_SHIFT_CONST(26)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_NANDCTRL_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_NANDCTRL_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_NANDCTRL_RANGE                   26:26
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_NANDCTRL_WOFFSET                 0x0
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_NANDCTRL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_NANDCTRL_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_NANDCTRL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_NANDCTRL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_HSMMC_SHIFT                      _MK_SHIFT_CONST(27)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_HSMMC_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_HSMMC_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_HSMMC_RANGE                      27:27
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_HSMMC_WOFFSET                    0x0
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_HSMMC_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_HSMMC_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_HSMMC_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_HSMMC_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_XIO_SHIFT                        _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_XIO_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_XIO_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_XIO_RANGE                        28:28
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_XIO_WOFFSET                      0x0
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_XIO_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_XIO_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_XIO_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_XIO_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_PWFM_SHIFT                       _MK_SHIFT_CONST(29)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_PWFM_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_PWFM_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_PWFM_RANGE                       29:29
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_PWFM_WOFFSET                     0x0
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_PWFM_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_PWFM_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_PWFM_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_PWFM_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_MIPI_HS_SHIFT                    _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_MIPI_HS_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_MIPI_HS_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_MIPI_HS_RANGE                    30:30
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_MIPI_HS_WOFFSET                  0x0
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_MIPI_HS_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_MIPI_HS_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_MIPI_HS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_MIPI_HS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_I2C_SHIFT                        _MK_SHIFT_CONST(31)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_I2C_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_I2C_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_I2C_RANGE                        31:31
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_I2C_WOFFSET                      0x0
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_I2C_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_I2C_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_I2C_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_I2C_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_DEV_PRESENT2_0  
+#define APB_MISC_GP_DEV_PRESENT2_0                      _MK_ADDR_CONST(0x934)
+#define APB_MISC_GP_DEV_PRESENT2_0_SECURE                       0x0
+#define APB_MISC_GP_DEV_PRESENT2_0_WORD_COUNT                   0x1
+#define APB_MISC_GP_DEV_PRESENT2_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_RESET_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_GP_DEV_PRESENT2_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_I2C2_SHIFT                       _MK_SHIFT_CONST(0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_I2C2_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_I2C2_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_I2C2_RANGE                       0:0
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_I2C2_WOFFSET                     0x0
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_I2C2_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_I2C2_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_I2C2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_I2C2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_I2C3_SHIFT                       _MK_SHIFT_CONST(1)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_I2C3_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_I2C3_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_I2C3_RANGE                       1:1
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_I2C3_WOFFSET                     0x0
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_I2C3_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_I2C3_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_I2C3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_I2C3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_TWC_SHIFT                        _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_TWC_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_TWC_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_TWC_RANGE                        2:2
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_TWC_WOFFSET                      0x0
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_TWC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_TWC_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_TWC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_TWC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SBC1_SHIFT                       _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SBC1_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SBC1_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SBC1_RANGE                       3:3
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SBC1_WOFFSET                     0x0
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SBC1_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SBC1_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SBC1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SBC1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SBC2_SHIFT                       _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SBC2_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SBC2_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SBC2_RANGE                       4:4
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SBC2_WOFFSET                     0x0
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SBC2_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SBC2_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SBC2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SBC2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SBC3_SHIFT                       _MK_SHIFT_CONST(5)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SBC3_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SBC3_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SBC3_RANGE                       5:5
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SBC3_WOFFSET                     0x0
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SBC3_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SBC3_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SBC3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SBC3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SBC4_SHIFT                       _MK_SHIFT_CONST(6)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SBC4_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SBC4_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SBC4_RANGE                       6:6
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SBC4_WOFFSET                     0x0
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SBC4_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SBC4_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SBC4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SBC4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SPI_SHIFT                        _MK_SHIFT_CONST(7)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SPI_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SPI_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SPI_RANGE                        7:7
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SPI_WOFFSET                      0x0
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SPI_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SPI_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SPI_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SPI_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_DVC_SHIFT                        _MK_SHIFT_CONST(8)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_DVC_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_DVC_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_DVC_RANGE                        8:8
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_DVC_WOFFSET                      0x0
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_DVC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_DVC_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_DVC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_DVC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_RTC_SHIFT                        _MK_SHIFT_CONST(9)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_RTC_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_RTC_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_RTC_RANGE                        9:9
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_RTC_WOFFSET                      0x0
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_RTC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_RTC_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_RTC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_RTC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_KBC_SHIFT                        _MK_SHIFT_CONST(10)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_KBC_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_KBC_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_KBC_RANGE                        10:10
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_KBC_WOFFSET                      0x0
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_KBC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_KBC_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_KBC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_KBC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_PMC_SHIFT                        _MK_SHIFT_CONST(11)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_PMC_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_PMC_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_PMC_RANGE                        11:11
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_PMC_WOFFSET                      0x0
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_PMC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_PMC_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_PMC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_PMC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_FUSE_SHIFT                       _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_FUSE_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_FUSE_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_FUSE_RANGE                       12:12
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_FUSE_WOFFSET                     0x0
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_FUSE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_FUSE_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_FUSE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_FUSE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_EIDE_SHIFT                       _MK_SHIFT_CONST(13)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_EIDE_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_EIDE_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_EIDE_RANGE                       13:13
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_EIDE_WOFFSET                     0x0
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_EIDE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_EIDE_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_EIDE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_EIDE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_USB_SHIFT                        _MK_SHIFT_CONST(14)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_USB_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_USB_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_USB_RANGE                        14:14
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_USB_WOFFSET                      0x0
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_USB_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_USB_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_USB_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_USB_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_USB2_SHIFT                       _MK_SHIFT_CONST(15)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_USB2_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_USB2_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_USB2_RANGE                       15:15
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_USB2_WOFFSET                     0x0
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_USB2_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_USB2_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_USB2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_USB2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_USB3_SHIFT                       _MK_SHIFT_CONST(16)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_USB3_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_USB3_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_USB3_RANGE                       16:16
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_USB3_WOFFSET                     0x0
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_USB3_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_USB3_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_USB3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_USB3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_TVO_SHIFT                        _MK_SHIFT_CONST(17)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_TVO_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_TVO_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_TVO_RANGE                        17:17
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_TVO_WOFFSET                      0x0
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_TVO_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_TVO_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_TVO_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_TVO_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_DSI_SHIFT                        _MK_SHIFT_CONST(18)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_DSI_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_DSI_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_DSI_RANGE                        18:18
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_DSI_WOFFSET                      0x0
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_DSI_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_DSI_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_DSI_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_DSI_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_HDMI_SHIFT                       _MK_SHIFT_CONST(19)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_HDMI_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_HDMI_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_HDMI_RANGE                       19:19
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_HDMI_WOFFSET                     0x0
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_HDMI_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_HDMI_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_HDMI_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_HDMI_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_PRI_ICTLR_SHIFT                  _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_PRI_ICTLR_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_PRI_ICTLR_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_PRI_ICTLR_RANGE                  20:20
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_PRI_ICTLR_WOFFSET                        0x0
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_PRI_ICTLR_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_PRI_ICTLR_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_PRI_ICTLR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_PRI_ICTLR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SEC_ICTLR_SHIFT                  _MK_SHIFT_CONST(21)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SEC_ICTLR_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SEC_ICTLR_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SEC_ICTLR_RANGE                  21:21
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SEC_ICTLR_WOFFSET                        0x0
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SEC_ICTLR_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SEC_ICTLR_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SEC_ICTLR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SEC_ICTLR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_TRI_ICTLR_SHIFT                  _MK_SHIFT_CONST(22)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_TRI_ICTLR_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_TRI_ICTLR_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_TRI_ICTLR_RANGE                  22:22
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_TRI_ICTLR_WOFFSET                        0x0
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_TRI_ICTLR_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_TRI_ICTLR_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_TRI_ICTLR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_TRI_ICTLR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_QUAD_ICTLR_SHIFT                 _MK_SHIFT_CONST(23)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_QUAD_ICTLR_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_QUAD_ICTLR_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_QUAD_ICTLR_RANGE                 23:23
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_QUAD_ICTLR_WOFFSET                       0x0
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_QUAD_ICTLR_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_QUAD_ICTLR_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_QUAD_ICTLR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_QUAD_ICTLR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SW_INTR_SHIFT                    _MK_SHIFT_CONST(24)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SW_INTR_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SW_INTR_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SW_INTR_RANGE                    24:24
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SW_INTR_WOFFSET                  0x0
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SW_INTR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SW_INTR_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SW_INTR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SW_INTR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_CPU0_PMU_INTR_SHIFT                      _MK_SHIFT_CONST(25)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_CPU0_PMU_INTR_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_CPU0_PMU_INTR_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_CPU0_PMU_INTR_RANGE                      25:25
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_CPU0_PMU_INTR_WOFFSET                    0x0
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_CPU0_PMU_INTR_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_CPU0_PMU_INTR_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_CPU0_PMU_INTR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_CPU0_PMU_INTR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_CPU1_PMU_INTR_SHIFT                      _MK_SHIFT_CONST(26)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_CPU1_PMU_INTR_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_CPU1_PMU_INTR_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_CPU1_PMU_INTR_RANGE                      26:26
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_CPU1_PMU_INTR_WOFFSET                    0x0
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_CPU1_PMU_INTR_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_CPU1_PMU_INTR_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_CPU1_PMU_INTR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_CPU1_PMU_INTR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_TMRUS_SHIFT                      _MK_SHIFT_CONST(27)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_TMRUS_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_TMRUS_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_TMRUS_RANGE                      27:27
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_TMRUS_WOFFSET                    0x0
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_TMRUS_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_TMRUS_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_TMRUS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_TMRUS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_PRI_ICTLR_ARBGNT_SHIFT                   _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_PRI_ICTLR_ARBGNT_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_PRI_ICTLR_ARBGNT_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_PRI_ICTLR_ARBGNT_RANGE                   28:28
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_PRI_ICTLR_ARBGNT_WOFFSET                 0x0
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_PRI_ICTLR_ARBGNT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_PRI_ICTLR_ARBGNT_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_PRI_ICTLR_ARBGNT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_PRI_ICTLR_ARBGNT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SEC_ICTLR_DRQ_TX_SHIFT                   _MK_SHIFT_CONST(29)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SEC_ICTLR_DRQ_TX_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SEC_ICTLR_DRQ_TX_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SEC_ICTLR_DRQ_TX_RANGE                   29:29
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SEC_ICTLR_DRQ_TX_WOFFSET                 0x0
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SEC_ICTLR_DRQ_TX_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SEC_ICTLR_DRQ_TX_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SEC_ICTLR_DRQ_TX_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SEC_ICTLR_DRQ_TX_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SEC_ICTLR_DRQ_RX_SHIFT                   _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SEC_ICTLR_DRQ_RX_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SEC_ICTLR_DRQ_RX_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SEC_ICTLR_DRQ_RX_RANGE                   30:30
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SEC_ICTLR_DRQ_RX_WOFFSET                 0x0
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SEC_ICTLR_DRQ_RX_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SEC_ICTLR_DRQ_RX_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SEC_ICTLR_DRQ_RX_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SEC_ICTLR_DRQ_RX_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_AHB_DMA_CH0_SHIFT                        _MK_SHIFT_CONST(31)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_AHB_DMA_CH0_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_AHB_DMA_CH0_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_AHB_DMA_CH0_RANGE                        31:31
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_AHB_DMA_CH0_WOFFSET                      0x0
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_AHB_DMA_CH0_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_AHB_DMA_CH0_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_AHB_DMA_CH0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_AHB_DMA_CH0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_DEV_PRESENT3_0  
+#define APB_MISC_GP_DEV_PRESENT3_0                      _MK_ADDR_CONST(0x938)
+#define APB_MISC_GP_DEV_PRESENT3_0_SECURE                       0x0
+#define APB_MISC_GP_DEV_PRESENT3_0_WORD_COUNT                   0x1
+#define APB_MISC_GP_DEV_PRESENT3_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_RESET_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_GP_DEV_PRESENT3_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_DMA_CH1_SHIFT                        _MK_SHIFT_CONST(0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_DMA_CH1_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_DMA_CH1_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_DMA_CH1_RANGE                        0:0
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_DMA_CH1_WOFFSET                      0x0
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_DMA_CH1_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_DMA_CH1_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_DMA_CH1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_DMA_CH1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_DMA_CH2_SHIFT                        _MK_SHIFT_CONST(1)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_DMA_CH2_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_DMA_CH2_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_DMA_CH2_RANGE                        1:1
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_DMA_CH2_WOFFSET                      0x0
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_DMA_CH2_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_DMA_CH2_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_DMA_CH2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_DMA_CH2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_DMA_CH3_SHIFT                        _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_DMA_CH3_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_DMA_CH3_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_DMA_CH3_RANGE                        2:2
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_DMA_CH3_WOFFSET                      0x0
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_DMA_CH3_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_DMA_CH3_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_DMA_CH3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_DMA_CH3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH0_SHIFT                        _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH0_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH0_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH0_RANGE                        3:3
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH0_WOFFSET                      0x0
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH0_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH0_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH1_SHIFT                        _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH1_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH1_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH1_RANGE                        4:4
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH1_WOFFSET                      0x0
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH1_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH1_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH2_SHIFT                        _MK_SHIFT_CONST(5)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH2_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH2_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH2_RANGE                        5:5
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH2_WOFFSET                      0x0
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH2_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH2_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH3_SHIFT                        _MK_SHIFT_CONST(6)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH3_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH3_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH3_RANGE                        6:6
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH3_WOFFSET                      0x0
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH3_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH3_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH4_SHIFT                        _MK_SHIFT_CONST(7)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH4_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH4_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH4_RANGE                        7:7
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH4_WOFFSET                      0x0
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH4_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH4_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH5_SHIFT                        _MK_SHIFT_CONST(8)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH5_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH5_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH5_RANGE                        8:8
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH5_WOFFSET                      0x0
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH5_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH5_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH6_SHIFT                        _MK_SHIFT_CONST(9)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH6_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH6_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH6_RANGE                        9:9
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH6_WOFFSET                      0x0
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH6_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH6_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH7_SHIFT                        _MK_SHIFT_CONST(10)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH7_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH7_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH7_RANGE                        10:10
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH7_WOFFSET                      0x0
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH7_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH7_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH8_SHIFT                        _MK_SHIFT_CONST(11)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH8_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH8_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH8_RANGE                        11:11
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH8_WOFFSET                      0x0
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH8_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH8_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH9_SHIFT                        _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH9_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH9_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH9_RANGE                        12:12
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH9_WOFFSET                      0x0
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH9_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH9_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH9_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH9_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH10_SHIFT                       _MK_SHIFT_CONST(13)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH10_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH10_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH10_RANGE                       13:13
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH10_WOFFSET                     0x0
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH10_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH10_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH10_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH10_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH11_SHIFT                       _MK_SHIFT_CONST(14)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH11_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH11_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH11_RANGE                       14:14
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH11_WOFFSET                     0x0
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH11_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH11_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH11_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH11_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH12_SHIFT                       _MK_SHIFT_CONST(15)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH12_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH12_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH12_RANGE                       15:15
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH12_WOFFSET                     0x0
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH12_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH12_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH12_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH12_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH13_SHIFT                       _MK_SHIFT_CONST(16)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH13_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH13_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH13_RANGE                       16:16
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH13_WOFFSET                     0x0
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH13_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH13_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH13_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH13_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH14_SHIFT                       _MK_SHIFT_CONST(17)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH14_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH14_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH14_RANGE                       17:17
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH14_WOFFSET                     0x0
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH14_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH14_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH14_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH14_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH15_SHIFT                       _MK_SHIFT_CONST(18)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH15_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH15_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH15_RANGE                       18:18
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH15_WOFFSET                     0x0
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH15_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH15_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH15_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH15_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_ARBC_SHIFT                   _MK_SHIFT_CONST(19)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_ARBC_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_ARBC_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_ARBC_RANGE                   19:19
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_ARBC_WOFFSET                 0x0
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_ARBC_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_ARBC_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_ARBC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_ARBC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHPBDEBUG_SHIFT                  _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHPBDEBUG_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHPBDEBUG_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHPBDEBUG_RANGE                  20:20
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHPBDEBUG_WOFFSET                        0x0
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHPBDEBUG_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHPBDEBUG_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHPBDEBUG_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHPBDEBUG_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_SECURE_BOOT_SHIFT                        _MK_SHIFT_CONST(21)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_SECURE_BOOT_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_SECURE_BOOT_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_SECURE_BOOT_RANGE                        21:21
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_SECURE_BOOT_WOFFSET                      0x0
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_SECURE_BOOT_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_SECURE_BOOT_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_SECURE_BOOT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_SECURE_BOOT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_EMEM_SHIFT                   _MK_SHIFT_CONST(22)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_EMEM_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_EMEM_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_EMEM_RANGE                   22:22
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_EMEM_WOFFSET                 0x0
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_EMEM_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_EMEM_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_EMEM_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_EMEM_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_PMU_EXT_SHIFT                    _MK_SHIFT_CONST(23)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_PMU_EXT_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_PMU_EXT_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_PMU_EXT_RANGE                    23:23
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_PMU_EXT_WOFFSET                  0x0
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_PMU_EXT_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_PMU_EXT_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_PMU_EXT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_PMU_EXT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_PPCS_SHIFT                       _MK_SHIFT_CONST(24)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_PPCS_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_PPCS_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_PPCS_RANGE                       24:24
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_PPCS_WOFFSET                     0x0
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_PPCS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_PPCS_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_PPCS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_PPCS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_MMU_TLB_SHIFT                    _MK_SHIFT_CONST(25)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_MMU_TLB_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_MMU_TLB_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_MMU_TLB_RANGE                    25:25
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_MMU_TLB_WOFFSET                  0x0
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_MMU_TLB_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_MMU_TLB_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_MMU_TLB_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_MMU_TLB_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_CSI_SHIFT                        _MK_SHIFT_CONST(26)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_CSI_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_CSI_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_CSI_RANGE                        26:26
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_CSI_WOFFSET                      0x0
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_CSI_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_CSI_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_CSI_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_CSI_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_ARM_PL310_SHIFT                  _MK_SHIFT_CONST(27)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_ARM_PL310_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_ARM_PL310_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_ARM_PL310_RANGE                  27:27
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_ARM_PL310_WOFFSET                        0x0
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_ARM_PL310_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_ARM_PL310_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_ARM_PL310_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_ARM_PL310_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_PCIE_SHIFT                       _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_PCIE_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_PCIE_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_PCIE_RANGE                       28:28
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_PCIE_WOFFSET                     0x0
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_PCIE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_PCIE_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_PCIE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_PCIE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_OWR_SHIFT                        _MK_SHIFT_CONST(29)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_OWR_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_OWR_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_OWR_RANGE                        29:29
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_OWR_WOFFSET                      0x0
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_OWR_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_OWR_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_OWR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_OWR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AVPUCQ_SHIFT                     _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AVPUCQ_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AVPUCQ_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AVPUCQ_RANGE                     30:30
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AVPUCQ_WOFFSET                   0x0
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AVPUCQ_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AVPUCQ_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AVPUCQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AVPUCQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_SNOR_SHIFT                       _MK_SHIFT_CONST(31)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_SNOR_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_SNOR_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_SNOR_RANGE                       31:31
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_SNOR_WOFFSET                     0x0
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_SNOR_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_SNOR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_SNOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_SNOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_DEV_PRESENT4_0  
+#define APB_MISC_GP_DEV_PRESENT4_0                      _MK_ADDR_CONST(0x93c)
+#define APB_MISC_GP_DEV_PRESENT4_0_SECURE                       0x0
+#define APB_MISC_GP_DEV_PRESENT4_0_WORD_COUNT                   0x1
+#define APB_MISC_GP_DEV_PRESENT4_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_RESET_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_READ_MASK                    _MK_MASK_CONST(0x7fffffff)
+#define APB_MISC_GP_DEV_PRESENT4_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SDMMC1_SHIFT                     _MK_SHIFT_CONST(0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SDMMC1_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SDMMC1_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SDMMC1_RANGE                     0:0
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SDMMC1_WOFFSET                   0x0
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SDMMC1_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SDMMC1_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SDMMC1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SDMMC1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SDMMC2_SHIFT                     _MK_SHIFT_CONST(1)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SDMMC2_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SDMMC2_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SDMMC2_RANGE                     1:1
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SDMMC2_WOFFSET                   0x0
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SDMMC2_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SDMMC2_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SDMMC2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SDMMC2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SDMMC3_SHIFT                     _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SDMMC3_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SDMMC3_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SDMMC3_RANGE                     2:2
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SDMMC3_WOFFSET                   0x0
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SDMMC3_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SDMMC3_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SDMMC3_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SDMMC3_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SDMMC4_SHIFT                     _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SDMMC4_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SDMMC4_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SDMMC4_RANGE                     3:3
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SDMMC4_WOFFSET                   0x0
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SDMMC4_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SDMMC4_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SDMMC4_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SDMMC4_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_KFUSE_SHIFT                      _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_KFUSE_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_KFUSE_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_KFUSE_RANGE                      4:4
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_KFUSE_WOFFSET                    0x0
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_KFUSE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_KFUSE_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_KFUSE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_KFUSE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_CSITE_SHIFT                      _MK_SHIFT_CONST(5)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_CSITE_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_CSITE_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_CSITE_RANGE                      5:5
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_CSITE_WOFFSET                    0x0
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_CSITE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_CSITE_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_CSITE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_CSITE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI0_SHIFT                       _MK_SHIFT_CONST(6)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI0_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI0_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI0_RANGE                       6:6
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI0_WOFFSET                     0x0
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI0_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI0_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI1_SHIFT                       _MK_SHIFT_CONST(7)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI1_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI1_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI1_RANGE                       7:7
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI1_WOFFSET                     0x0
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI1_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI1_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI2_SHIFT                       _MK_SHIFT_CONST(8)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI2_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI2_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI2_RANGE                       8:8
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI2_WOFFSET                     0x0
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI2_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI2_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI3_SHIFT                       _MK_SHIFT_CONST(9)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI3_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI3_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI3_RANGE                       9:9
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI3_WOFFSET                     0x0
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI3_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI3_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI4_SHIFT                       _MK_SHIFT_CONST(10)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI4_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI4_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI4_RANGE                       10:10
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI4_WOFFSET                     0x0
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI4_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI4_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI5_SHIFT                       _MK_SHIFT_CONST(11)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI5_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI5_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI5_RANGE                       11:11
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI5_WOFFSET                     0x0
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI5_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI5_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI6_SHIFT                       _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI6_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI6_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI6_RANGE                       12:12
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI6_WOFFSET                     0x0
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI6_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI6_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI7_SHIFT                       _MK_SHIFT_CONST(13)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI7_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI7_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI7_RANGE                       13:13
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI7_WOFFSET                     0x0
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI7_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI7_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI8_SHIFT                       _MK_SHIFT_CONST(14)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI8_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI8_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI8_RANGE                       14:14
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI8_WOFFSET                     0x0
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI8_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI8_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI8_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI8_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI9_SHIFT                       _MK_SHIFT_CONST(15)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI9_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI9_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI9_RANGE                       15:15
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI9_WOFFSET                     0x0
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI9_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI9_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI9_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI9_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI10_SHIFT                      _MK_SHIFT_CONST(16)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI10_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI10_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI10_RANGE                      16:16
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI10_WOFFSET                    0x0
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI10_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI10_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI10_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI10_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI11_SHIFT                      _MK_SHIFT_CONST(17)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI11_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI11_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI11_RANGE                      17:17
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI11_WOFFSET                    0x0
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI11_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI11_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI11_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI11_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI12_SHIFT                      _MK_SHIFT_CONST(18)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI12_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI12_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI12_RANGE                      18:18
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI12_WOFFSET                    0x0
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI12_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI12_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI12_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI12_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI13_SHIFT                      _MK_SHIFT_CONST(19)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI13_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI13_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI13_RANGE                      19:19
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI13_WOFFSET                    0x0
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI13_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI13_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI13_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI13_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI14_SHIFT                      _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI14_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI14_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI14_RANGE                      20:20
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI14_WOFFSET                    0x0
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI14_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI14_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI14_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI14_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI15_SHIFT                      _MK_SHIFT_CONST(21)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI15_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI15_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI15_RANGE                      21:21
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI15_WOFFSET                    0x0
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI15_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI15_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI15_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI15_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_ARM_ICTLR_SHIFT                  _MK_SHIFT_CONST(22)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_ARM_ICTLR_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_ARM_ICTLR_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_ARM_ICTLR_RANGE                  22:22
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_ARM_ICTLR_WOFFSET                        0x0
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_ARM_ICTLR_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_ARM_ICTLR_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_ARM_ICTLR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_ARM_ICTLR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_HDMI_IOBIST_SHIFT                        _MK_SHIFT_CONST(23)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_HDMI_IOBIST_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_HDMI_IOBIST_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_HDMI_IOBIST_RANGE                        23:23
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_HDMI_IOBIST_WOFFSET                      0x0
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_HDMI_IOBIST_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_HDMI_IOBIST_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_HDMI_IOBIST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_HDMI_IOBIST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_MIPI_IOBIST_SHIFT                        _MK_SHIFT_CONST(24)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_MIPI_IOBIST_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_MIPI_IOBIST_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_MIPI_IOBIST_RANGE                        24:24
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_MIPI_IOBIST_WOFFSET                      0x0
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_MIPI_IOBIST_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_MIPI_IOBIST_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_MIPI_IOBIST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_MIPI_IOBIST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_PCIE_X2_IOBIST_SHIFT                     _MK_SHIFT_CONST(25)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_PCIE_X2_IOBIST_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_PCIE_X2_IOBIST_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_PCIE_X2_IOBIST_RANGE                     25:25
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_PCIE_X2_IOBIST_WOFFSET                   0x0
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_PCIE_X2_IOBIST_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_PCIE_X2_IOBIST_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_PCIE_X2_IOBIST_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_PCIE_X2_IOBIST_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_PCIE_X4_IOBIST_SHIFT                     _MK_SHIFT_CONST(26)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_PCIE_X4_IOBIST_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_PCIE_X4_IOBIST_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_PCIE_X4_IOBIST_RANGE                     26:26
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_PCIE_X4_IOBIST_WOFFSET                   0x0
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_PCIE_X4_IOBIST_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_PCIE_X4_IOBIST_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_PCIE_X4_IOBIST_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_PCIE_X4_IOBIST_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_LPDDR2_IOBIST_SHIFT                      _MK_SHIFT_CONST(27)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_LPDDR2_IOBIST_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_LPDDR2_IOBIST_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_LPDDR2_IOBIST_RANGE                      27:27
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_LPDDR2_IOBIST_WOFFSET                    0x0
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_LPDDR2_IOBIST_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_LPDDR2_IOBIST_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_LPDDR2_IOBIST_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_LPDDR2_IOBIST_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SPEEDO_0_SHIFT                   _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SPEEDO_0_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SPEEDO_0_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SPEEDO_0_RANGE                   28:28
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SPEEDO_0_WOFFSET                 0x0
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SPEEDO_0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SPEEDO_0_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SPEEDO_0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SPEEDO_0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SPEEDO_1_SHIFT                   _MK_SHIFT_CONST(29)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SPEEDO_1_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SPEEDO_1_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SPEEDO_1_RANGE                   29:29
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SPEEDO_1_WOFFSET                 0x0
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SPEEDO_1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SPEEDO_1_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SPEEDO_1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SPEEDO_1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_LA_SHIFT                 _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_LA_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_LA_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_LA_RANGE                 30:30
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_LA_WOFFSET                       0x0
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_LA_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_LA_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_LA_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_LA_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_L2EMU_ADDR_0  
+#define APB_MISC_GP_L2EMU_ADDR_0                        _MK_ADDR_CONST(0x940)
+#define APB_MISC_GP_L2EMU_ADDR_0_SECURE                         0x0
+#define APB_MISC_GP_L2EMU_ADDR_0_WORD_COUNT                     0x1
+#define APB_MISC_GP_L2EMU_ADDR_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_ADDR_0_RESET_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_ADDR_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_ADDR_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_ADDR_0_READ_MASK                      _MK_MASK_CONST(0x7fff)
+#define APB_MISC_GP_L2EMU_ADDR_0_WRITE_MASK                     _MK_MASK_CONST(0x7fff)
+// 256-bit aligned cache address
+#define APB_MISC_GP_L2EMU_ADDR_0_L2EMU_ADDR_SHIFT                       _MK_SHIFT_CONST(0)
+#define APB_MISC_GP_L2EMU_ADDR_0_L2EMU_ADDR_FIELD                       (_MK_MASK_CONST(0x7fff) << APB_MISC_GP_L2EMU_ADDR_0_L2EMU_ADDR_SHIFT)
+#define APB_MISC_GP_L2EMU_ADDR_0_L2EMU_ADDR_RANGE                       14:0
+#define APB_MISC_GP_L2EMU_ADDR_0_L2EMU_ADDR_WOFFSET                     0x0
+#define APB_MISC_GP_L2EMU_ADDR_0_L2EMU_ADDR_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_ADDR_0_L2EMU_ADDR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_ADDR_0_L2EMU_ADDR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_ADDR_0_L2EMU_ADDR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_L2EMU_BE_0  
+#define APB_MISC_GP_L2EMU_BE_0                  _MK_ADDR_CONST(0x944)
+#define APB_MISC_GP_L2EMU_BE_0_SECURE                   0x0
+#define APB_MISC_GP_L2EMU_BE_0_WORD_COUNT                       0x1
+#define APB_MISC_GP_L2EMU_BE_0_RESET_VAL                        _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_GP_L2EMU_BE_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_GP_L2EMU_BE_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_BE_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_BE_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_GP_L2EMU_BE_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+// byte enables
+#define APB_MISC_GP_L2EMU_BE_0_L2EMU_BE_SHIFT                   _MK_SHIFT_CONST(0)
+#define APB_MISC_GP_L2EMU_BE_0_L2EMU_BE_FIELD                   (_MK_MASK_CONST(0xffffffff) << APB_MISC_GP_L2EMU_BE_0_L2EMU_BE_SHIFT)
+#define APB_MISC_GP_L2EMU_BE_0_L2EMU_BE_RANGE                   31:0
+#define APB_MISC_GP_L2EMU_BE_0_L2EMU_BE_WOFFSET                 0x0
+#define APB_MISC_GP_L2EMU_BE_0_L2EMU_BE_DEFAULT                 _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_GP_L2EMU_BE_0_L2EMU_BE_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_GP_L2EMU_BE_0_L2EMU_BE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_BE_0_L2EMU_BE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_BE_0_L2EMU_BE_INIT_ENUM                       -1
+
+
+// Register APB_MISC_GP_L2EMU_DATA0_0  
+#define APB_MISC_GP_L2EMU_DATA0_0                       _MK_ADDR_CONST(0x948)
+#define APB_MISC_GP_L2EMU_DATA0_0_SECURE                        0x0
+#define APB_MISC_GP_L2EMU_DATA0_0_WORD_COUNT                    0x1
+#define APB_MISC_GP_L2EMU_DATA0_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_DATA0_0_RESET_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_DATA0_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_DATA0_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_DATA0_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_GP_L2EMU_DATA0_0_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
+// data word 0
+#define APB_MISC_GP_L2EMU_DATA0_0_L2EMU_DATA0_SHIFT                     _MK_SHIFT_CONST(0)
+#define APB_MISC_GP_L2EMU_DATA0_0_L2EMU_DATA0_FIELD                     (_MK_MASK_CONST(0xffffffff) << APB_MISC_GP_L2EMU_DATA0_0_L2EMU_DATA0_SHIFT)
+#define APB_MISC_GP_L2EMU_DATA0_0_L2EMU_DATA0_RANGE                     31:0
+#define APB_MISC_GP_L2EMU_DATA0_0_L2EMU_DATA0_WOFFSET                   0x0
+#define APB_MISC_GP_L2EMU_DATA0_0_L2EMU_DATA0_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_DATA0_0_L2EMU_DATA0_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_DATA0_0_L2EMU_DATA0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_DATA0_0_L2EMU_DATA0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_L2EMU_DATA1_0  
+#define APB_MISC_GP_L2EMU_DATA1_0                       _MK_ADDR_CONST(0x94c)
+#define APB_MISC_GP_L2EMU_DATA1_0_SECURE                        0x0
+#define APB_MISC_GP_L2EMU_DATA1_0_WORD_COUNT                    0x1
+#define APB_MISC_GP_L2EMU_DATA1_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_DATA1_0_RESET_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_DATA1_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_DATA1_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_DATA1_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_GP_L2EMU_DATA1_0_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
+// data word 1
+#define APB_MISC_GP_L2EMU_DATA1_0_L2EMU_DATA1_SHIFT                     _MK_SHIFT_CONST(0)
+#define APB_MISC_GP_L2EMU_DATA1_0_L2EMU_DATA1_FIELD                     (_MK_MASK_CONST(0xffffffff) << APB_MISC_GP_L2EMU_DATA1_0_L2EMU_DATA1_SHIFT)
+#define APB_MISC_GP_L2EMU_DATA1_0_L2EMU_DATA1_RANGE                     31:0
+#define APB_MISC_GP_L2EMU_DATA1_0_L2EMU_DATA1_WOFFSET                   0x0
+#define APB_MISC_GP_L2EMU_DATA1_0_L2EMU_DATA1_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_DATA1_0_L2EMU_DATA1_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_DATA1_0_L2EMU_DATA1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_DATA1_0_L2EMU_DATA1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_L2EMU_DATA2_0  
+#define APB_MISC_GP_L2EMU_DATA2_0                       _MK_ADDR_CONST(0x950)
+#define APB_MISC_GP_L2EMU_DATA2_0_SECURE                        0x0
+#define APB_MISC_GP_L2EMU_DATA2_0_WORD_COUNT                    0x1
+#define APB_MISC_GP_L2EMU_DATA2_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_DATA2_0_RESET_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_DATA2_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_DATA2_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_DATA2_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_GP_L2EMU_DATA2_0_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
+// data word 2
+#define APB_MISC_GP_L2EMU_DATA2_0_L2EMU_DATA2_SHIFT                     _MK_SHIFT_CONST(0)
+#define APB_MISC_GP_L2EMU_DATA2_0_L2EMU_DATA2_FIELD                     (_MK_MASK_CONST(0xffffffff) << APB_MISC_GP_L2EMU_DATA2_0_L2EMU_DATA2_SHIFT)
+#define APB_MISC_GP_L2EMU_DATA2_0_L2EMU_DATA2_RANGE                     31:0
+#define APB_MISC_GP_L2EMU_DATA2_0_L2EMU_DATA2_WOFFSET                   0x0
+#define APB_MISC_GP_L2EMU_DATA2_0_L2EMU_DATA2_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_DATA2_0_L2EMU_DATA2_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_DATA2_0_L2EMU_DATA2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_DATA2_0_L2EMU_DATA2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_L2EMU_DATA3_0  
+#define APB_MISC_GP_L2EMU_DATA3_0                       _MK_ADDR_CONST(0x954)
+#define APB_MISC_GP_L2EMU_DATA3_0_SECURE                        0x0
+#define APB_MISC_GP_L2EMU_DATA3_0_WORD_COUNT                    0x1
+#define APB_MISC_GP_L2EMU_DATA3_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_DATA3_0_RESET_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_DATA3_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_DATA3_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_DATA3_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_GP_L2EMU_DATA3_0_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
+// data word 3
+#define APB_MISC_GP_L2EMU_DATA3_0_L2EMU_DATA3_SHIFT                     _MK_SHIFT_CONST(0)
+#define APB_MISC_GP_L2EMU_DATA3_0_L2EMU_DATA3_FIELD                     (_MK_MASK_CONST(0xffffffff) << APB_MISC_GP_L2EMU_DATA3_0_L2EMU_DATA3_SHIFT)
+#define APB_MISC_GP_L2EMU_DATA3_0_L2EMU_DATA3_RANGE                     31:0
+#define APB_MISC_GP_L2EMU_DATA3_0_L2EMU_DATA3_WOFFSET                   0x0
+#define APB_MISC_GP_L2EMU_DATA3_0_L2EMU_DATA3_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_DATA3_0_L2EMU_DATA3_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_DATA3_0_L2EMU_DATA3_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_DATA3_0_L2EMU_DATA3_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_L2EMU_DATA4_0  
+#define APB_MISC_GP_L2EMU_DATA4_0                       _MK_ADDR_CONST(0x958)
+#define APB_MISC_GP_L2EMU_DATA4_0_SECURE                        0x0
+#define APB_MISC_GP_L2EMU_DATA4_0_WORD_COUNT                    0x1
+#define APB_MISC_GP_L2EMU_DATA4_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_DATA4_0_RESET_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_DATA4_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_DATA4_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_DATA4_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_GP_L2EMU_DATA4_0_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
+// data word 4
+#define APB_MISC_GP_L2EMU_DATA4_0_L2EMU_DATA4_SHIFT                     _MK_SHIFT_CONST(0)
+#define APB_MISC_GP_L2EMU_DATA4_0_L2EMU_DATA4_FIELD                     (_MK_MASK_CONST(0xffffffff) << APB_MISC_GP_L2EMU_DATA4_0_L2EMU_DATA4_SHIFT)
+#define APB_MISC_GP_L2EMU_DATA4_0_L2EMU_DATA4_RANGE                     31:0
+#define APB_MISC_GP_L2EMU_DATA4_0_L2EMU_DATA4_WOFFSET                   0x0
+#define APB_MISC_GP_L2EMU_DATA4_0_L2EMU_DATA4_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_DATA4_0_L2EMU_DATA4_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_DATA4_0_L2EMU_DATA4_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_DATA4_0_L2EMU_DATA4_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_L2EMU_DATA5_0  
+#define APB_MISC_GP_L2EMU_DATA5_0                       _MK_ADDR_CONST(0x95c)
+#define APB_MISC_GP_L2EMU_DATA5_0_SECURE                        0x0
+#define APB_MISC_GP_L2EMU_DATA5_0_WORD_COUNT                    0x1
+#define APB_MISC_GP_L2EMU_DATA5_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_DATA5_0_RESET_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_DATA5_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_DATA5_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_DATA5_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_GP_L2EMU_DATA5_0_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
+// data word 5
+#define APB_MISC_GP_L2EMU_DATA5_0_L2EMU_DATA5_SHIFT                     _MK_SHIFT_CONST(0)
+#define APB_MISC_GP_L2EMU_DATA5_0_L2EMU_DATA5_FIELD                     (_MK_MASK_CONST(0xffffffff) << APB_MISC_GP_L2EMU_DATA5_0_L2EMU_DATA5_SHIFT)
+#define APB_MISC_GP_L2EMU_DATA5_0_L2EMU_DATA5_RANGE                     31:0
+#define APB_MISC_GP_L2EMU_DATA5_0_L2EMU_DATA5_WOFFSET                   0x0
+#define APB_MISC_GP_L2EMU_DATA5_0_L2EMU_DATA5_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_DATA5_0_L2EMU_DATA5_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_DATA5_0_L2EMU_DATA5_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_DATA5_0_L2EMU_DATA5_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_L2EMU_DATA6_0  
+#define APB_MISC_GP_L2EMU_DATA6_0                       _MK_ADDR_CONST(0x960)
+#define APB_MISC_GP_L2EMU_DATA6_0_SECURE                        0x0
+#define APB_MISC_GP_L2EMU_DATA6_0_WORD_COUNT                    0x1
+#define APB_MISC_GP_L2EMU_DATA6_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_DATA6_0_RESET_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_DATA6_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_DATA6_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_DATA6_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_GP_L2EMU_DATA6_0_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
+// data word 6
+#define APB_MISC_GP_L2EMU_DATA6_0_L2EMU_DATA6_SHIFT                     _MK_SHIFT_CONST(0)
+#define APB_MISC_GP_L2EMU_DATA6_0_L2EMU_DATA6_FIELD                     (_MK_MASK_CONST(0xffffffff) << APB_MISC_GP_L2EMU_DATA6_0_L2EMU_DATA6_SHIFT)
+#define APB_MISC_GP_L2EMU_DATA6_0_L2EMU_DATA6_RANGE                     31:0
+#define APB_MISC_GP_L2EMU_DATA6_0_L2EMU_DATA6_WOFFSET                   0x0
+#define APB_MISC_GP_L2EMU_DATA6_0_L2EMU_DATA6_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_DATA6_0_L2EMU_DATA6_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_DATA6_0_L2EMU_DATA6_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_DATA6_0_L2EMU_DATA6_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_L2EMU_DATA7_0  
+#define APB_MISC_GP_L2EMU_DATA7_0                       _MK_ADDR_CONST(0x964)
+#define APB_MISC_GP_L2EMU_DATA7_0_SECURE                        0x0
+#define APB_MISC_GP_L2EMU_DATA7_0_WORD_COUNT                    0x1
+#define APB_MISC_GP_L2EMU_DATA7_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_DATA7_0_RESET_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_DATA7_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_DATA7_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_DATA7_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_GP_L2EMU_DATA7_0_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
+// data word 7
+#define APB_MISC_GP_L2EMU_DATA7_0_L2EMU_DATA7_SHIFT                     _MK_SHIFT_CONST(0)
+#define APB_MISC_GP_L2EMU_DATA7_0_L2EMU_DATA7_FIELD                     (_MK_MASK_CONST(0xffffffff) << APB_MISC_GP_L2EMU_DATA7_0_L2EMU_DATA7_SHIFT)
+#define APB_MISC_GP_L2EMU_DATA7_0_L2EMU_DATA7_RANGE                     31:0
+#define APB_MISC_GP_L2EMU_DATA7_0_L2EMU_DATA7_WOFFSET                   0x0
+#define APB_MISC_GP_L2EMU_DATA7_0_L2EMU_DATA7_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_DATA7_0_L2EMU_DATA7_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_DATA7_0_L2EMU_DATA7_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_DATA7_0_L2EMU_DATA7_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_L2EMU_READ_0  
+#define APB_MISC_GP_L2EMU_READ_0                        _MK_ADDR_CONST(0x968)
+#define APB_MISC_GP_L2EMU_READ_0_SECURE                         0x0
+#define APB_MISC_GP_L2EMU_READ_0_WORD_COUNT                     0x1
+#define APB_MISC_GP_L2EMU_READ_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_READ_0_RESET_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_READ_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_READ_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_READ_0_READ_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_L2EMU_READ_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
+// trigger cache line read
+#define APB_MISC_GP_L2EMU_READ_0_L2EMU_READ_SHIFT                       _MK_SHIFT_CONST(0)
+#define APB_MISC_GP_L2EMU_READ_0_L2EMU_READ_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_L2EMU_READ_0_L2EMU_READ_SHIFT)
+#define APB_MISC_GP_L2EMU_READ_0_L2EMU_READ_RANGE                       0:0
+#define APB_MISC_GP_L2EMU_READ_0_L2EMU_READ_WOFFSET                     0x0
+#define APB_MISC_GP_L2EMU_READ_0_L2EMU_READ_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_READ_0_L2EMU_READ_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_READ_0_L2EMU_READ_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_READ_0_L2EMU_READ_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_L2EMU_WRITE_0  
+#define APB_MISC_GP_L2EMU_WRITE_0                       _MK_ADDR_CONST(0x96c)
+#define APB_MISC_GP_L2EMU_WRITE_0_SECURE                        0x0
+#define APB_MISC_GP_L2EMU_WRITE_0_WORD_COUNT                    0x1
+#define APB_MISC_GP_L2EMU_WRITE_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_WRITE_0_RESET_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_WRITE_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_WRITE_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_WRITE_0_READ_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_L2EMU_WRITE_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
+// trigger cache line write
+#define APB_MISC_GP_L2EMU_WRITE_0_L2EMU_WRITE_SHIFT                     _MK_SHIFT_CONST(0)
+#define APB_MISC_GP_L2EMU_WRITE_0_L2EMU_WRITE_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_L2EMU_WRITE_0_L2EMU_WRITE_SHIFT)
+#define APB_MISC_GP_L2EMU_WRITE_0_L2EMU_WRITE_RANGE                     0:0
+#define APB_MISC_GP_L2EMU_WRITE_0_L2EMU_WRITE_WOFFSET                   0x0
+#define APB_MISC_GP_L2EMU_WRITE_0_L2EMU_WRITE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_WRITE_0_L2EMU_WRITE_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_WRITE_0_L2EMU_WRITE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_WRITE_0_L2EMU_WRITE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_UTMIP_PLL_CFG0_0  // USB_PHY PLL Configuration Register 0
+//
+// The data sampling frequency relies on a 960MHz clock, so the goal of the PLL is to have:
+// In_Frequency*(PLL_VCOMULTBY2+1)*(PLL_NDIV/PLL_MDIV) = 960MHz
+//
+// With a 12MHz input from PLL_U, the default setting of 
+// PLL_VCOMULTBY2=1, PLL_NDIV=40 and PLL_MDIV=1 results in a correct output.
+#define APB_MISC_UTMIP_PLL_CFG0_0                       _MK_ADDR_CONST(0xa00)
+#define APB_MISC_UTMIP_PLL_CFG0_0_SECURE                        0x0
+#define APB_MISC_UTMIP_PLL_CFG0_0_WORD_COUNT                    0x1
+#define APB_MISC_UTMIP_PLL_CFG0_0_RESET_VAL                     _MK_MASK_CONST(0x280180)
+#define APB_MISC_UTMIP_PLL_CFG0_0_RESET_MASK                    _MK_MASK_CONST(0x7fffffff)
+#define APB_MISC_UTMIP_PLL_CFG0_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG0_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG0_0_READ_MASK                     _MK_MASK_CONST(0x7fffffff)
+#define APB_MISC_UTMIP_PLL_CFG0_0_WRITE_MASK                    _MK_MASK_CONST(0x7fffffff)
+// LOCK_ENABLE input of USB_PHY PLL.
+// Normally only used during test. See cell specification.
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKENABLE_SHIFT                    _MK_SHIFT_CONST(0)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKENABLE_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKENABLE_SHIFT)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKENABLE_RANGE                    0:0
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKENABLE_WOFFSET                  0x0
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKENABLE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKENABLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKENABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKENABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// LOCKSEL[5:0] input of USB_PHY PLL.
+// Used in test modes only. See cell specification.
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKSEL_SHIFT                       _MK_SHIFT_CONST(1)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKSEL_FIELD                       (_MK_MASK_CONST(0x3f) << APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKSEL_SHIFT)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKSEL_RANGE                       6:1
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKSEL_WOFFSET                     0x0
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKSEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKSEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3f)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKSEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKSEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// VCOMULTBY2 control of the UTMIP PHY PLL.
+// Recommended setting is on. Additional divide by 2 on the 
+// VCO feedback. Which is setting the bit to 1. See cell spec.
+//
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_VCOMULTBY2_SHIFT                    _MK_SHIFT_CONST(7)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_VCOMULTBY2_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_VCOMULTBY2_SHIFT)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_VCOMULTBY2_RANGE                    7:7
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_VCOMULTBY2_WOFFSET                  0x0
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_VCOMULTBY2_DEFAULT                  _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_VCOMULTBY2_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_VCOMULTBY2_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_VCOMULTBY2_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// MDIV[7:0] input of the USB_PHY PLL. This is the predivide on the PLL. 
+// 0x0 is not allowed. See cell specification.
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_MDIV_SHIFT                  _MK_SHIFT_CONST(8)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_MDIV_FIELD                  (_MK_MASK_CONST(0xff) << APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_MDIV_SHIFT)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_MDIV_RANGE                  15:8
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_MDIV_WOFFSET                        0x0
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_MDIV_DEFAULT                        _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_MDIV_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_MDIV_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_MDIV_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// NDIV[7:0] input of USB_PHY PLL. 
+// This is the feedback divider on the VCO feedback. 
+// 0x0 is not allowed. See cell specification.
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_NDIV_SHIFT                  _MK_SHIFT_CONST(16)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_NDIV_FIELD                  (_MK_MASK_CONST(0xff) << APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_NDIV_SHIFT)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_NDIV_RANGE                  23:16
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_NDIV_WOFFSET                        0x0
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_NDIV_DEFAULT                        _MK_MASK_CONST(0x28)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_NDIV_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_NDIV_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_NDIV_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// PDIV[2:0] input of the USB_PHY PLL.
+// Reserved. Keep at 0x0. Currently there is no post divider on this PLL. 
+// See cell specification.
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIV_SHIFT                  _MK_SHIFT_CONST(24)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIV_FIELD                  (_MK_MASK_CONST(0x7) << APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIV_SHIFT)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIV_RANGE                  26:24
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIV_WOFFSET                        0x0
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIV_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIV_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIV_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIV_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// PDIVRST of the UTMIP PHY PLL.
+// Reserved. Keep at 0x0. Currently there is no post divider on this PLL. 
+// See cell specification.
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIVRST_SHIFT                       _MK_SHIFT_CONST(27)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIVRST_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIVRST_SHIFT)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIVRST_RANGE                       27:27
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIVRST_WOFFSET                     0x0
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIVRST_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIVRST_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIVRST_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIVRST_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Selects which of the eight 60MHz clock phases to produce at the output 
+// of the USB PHY PLL. This is for a test mode. See cell specification.
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_SELECT_SHIFT                        _MK_SHIFT_CONST(28)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_SELECT_FIELD                        (_MK_MASK_CONST(0x7) << APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_SELECT_SHIFT)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_SELECT_RANGE                        30:28
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_SELECT_WOFFSET                      0x0
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_SELECT_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_SELECT_DEFAULT_MASK                 _MK_MASK_CONST(0x7)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_SELECT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_SELECT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_UTMIP_PLL_CFG1_0  // UTMIP PLL and PLLU configuration register 1
+#define APB_MISC_UTMIP_PLL_CFG1_0                       _MK_ADDR_CONST(0xa04)
+#define APB_MISC_UTMIP_PLL_CFG1_0_SECURE                        0x0
+#define APB_MISC_UTMIP_PLL_CFG1_0_WORD_COUNT                    0x1
+#define APB_MISC_UTMIP_PLL_CFG1_0_RESET_VAL                     _MK_MASK_CONST(0x182000c0)
+#define APB_MISC_UTMIP_PLL_CFG1_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_UTMIP_PLL_CFG1_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG1_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG1_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_UTMIP_PLL_CFG1_0_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
+// Determines the time to wait until the output of USB_PHY PLL is considered stable. 
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_XTAL_FREQ_COUNT_SHIFT                   _MK_SHIFT_CONST(0)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_XTAL_FREQ_COUNT_FIELD                   (_MK_MASK_CONST(0xfff) << APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_XTAL_FREQ_COUNT_SHIFT)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_XTAL_FREQ_COUNT_RANGE                   11:0
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_XTAL_FREQ_COUNT_WOFFSET                 0x0
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_XTAL_FREQ_COUNT_DEFAULT                 _MK_MASK_CONST(0xc0)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_XTAL_FREQ_COUNT_DEFAULT_MASK                    _MK_MASK_CONST(0xfff)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_XTAL_FREQ_COUNT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_XTAL_FREQ_COUNT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Force USB_PHY PLL pll_active input off. (Overrides FORCE_PLL_ACTIVE_POWERUP.)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERDOWN_SHIFT                        _MK_SHIFT_CONST(12)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERDOWN_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERDOWN_SHIFT)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERDOWN_RANGE                        12:12
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERDOWN_WOFFSET                      0x0
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERDOWN_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERDOWN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERDOWN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERDOWN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Force USB_PHY PLL pll_active input on. 
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERUP_SHIFT                  _MK_SHIFT_CONST(13)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERUP_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERUP_SHIFT)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERUP_RANGE                  13:13
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERUP_WOFFSET                        0x0
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERUP_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERUP_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERUP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERUP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Force USB_PHY PLL pll_enable input off. (Overrides FORCE_PLL_ENABLE_POWERUP.)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERDOWN_SHIFT                        _MK_SHIFT_CONST(14)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERDOWN_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERDOWN_SHIFT)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERDOWN_RANGE                        14:14
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERDOWN_WOFFSET                      0x0
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERDOWN_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERDOWN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERDOWN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERDOWN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Force USB_PHY PLL pll_enable input on. 
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERUP_SHIFT                  _MK_SHIFT_CONST(15)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERUP_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERUP_SHIFT)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERUP_RANGE                  15:15
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERUP_WOFFSET                        0x0
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERUP_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERUP_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERUP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERUP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Force PLL_U into power down. (Overrides FORCE_PLLU_POWERUP.)  
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERDOWN_SHIFT                      _MK_SHIFT_CONST(16)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERDOWN_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERDOWN_SHIFT)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERDOWN_RANGE                      16:16
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERDOWN_WOFFSET                    0x0
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERDOWN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERDOWN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERDOWN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERDOWN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Force PLL_U into power up.
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERUP_SHIFT                        _MK_SHIFT_CONST(17)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERUP_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERUP_SHIFT)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERUP_RANGE                        17:17
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERUP_WOFFSET                      0x0
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERUP_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERUP_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERUP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERUP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// SETUP[8:0] input of USB_PHY PLL.
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_PLL_SETUP_SHIFT                 _MK_SHIFT_CONST(18)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_PLL_SETUP_FIELD                 (_MK_MASK_CONST(0x1ff) << APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_PLL_SETUP_SHIFT)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_PLL_SETUP_RANGE                 26:18
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_PLL_SETUP_WOFFSET                       0x0
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_PLL_SETUP_DEFAULT                       _MK_MASK_CONST(0x8)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_PLL_SETUP_DEFAULT_MASK                  _MK_MASK_CONST(0x1ff)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_PLL_SETUP_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_PLL_SETUP_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Controls the wait time to enable PLL_U when coming out of suspend or reset.
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT                     _MK_SHIFT_CONST(27)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_PLLU_ENABLE_DLY_COUNT_FIELD                     (_MK_MASK_CONST(0x1f) << APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_PLLU_ENABLE_DLY_COUNT_RANGE                     31:27
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_PLLU_ENABLE_DLY_COUNT_WOFFSET                   0x0
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_PLLU_ENABLE_DLY_COUNT_DEFAULT                   _MK_MASK_CONST(0x3)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_PLLU_ENABLE_DLY_COUNT_DEFAULT_MASK                      _MK_MASK_CONST(0x1f)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_PLLU_ENABLE_DLY_COUNT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_PLLU_ENABLE_DLY_COUNT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_UTMIP_XCVR_CFG0_0  // UTMIP transceiver cell configuration register 0
+#define APB_MISC_UTMIP_XCVR_CFG0_0                      _MK_ADDR_CONST(0xa08)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_SECURE                       0x0
+#define APB_MISC_UTMIP_XCVR_CFG0_0_WORD_COUNT                   0x1
+#define APB_MISC_UTMIP_XCVR_CFG0_0_RESET_VAL                    _MK_MASK_CONST(0x20202500)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
+// SETUP[3:0] input of XCVR cell. HS driver output control. 4 LSBs.
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_SETUP_SHIFT                       _MK_SHIFT_CONST(0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_SETUP_FIELD                       (_MK_MASK_CONST(0xf) << APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_SETUP_SHIFT)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_SETUP_RANGE                       3:0
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_SETUP_WOFFSET                     0x0
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_SETUP_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_SETUP_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_SETUP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_SETUP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// HS slew rate control. The two LSBs.
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSSLEW_SHIFT                      _MK_SHIFT_CONST(4)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSSLEW_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSSLEW_SHIFT)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSSLEW_RANGE                      5:4
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSSLEW_WOFFSET                    0x0
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSSLEW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSSLEW_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSSLEW_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSSLEW_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// FS slew rate control.
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_FSSLEW_SHIFT                      _MK_SHIFT_CONST(6)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_FSSLEW_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_FSSLEW_SHIFT)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_FSSLEW_RANGE                      7:6
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_FSSLEW_WOFFSET                    0x0
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_FSSLEW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_FSSLEW_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_FSSLEW_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_FSSLEW_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// LS rising slew rate control.
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSRSLEW_SHIFT                     _MK_SHIFT_CONST(8)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSRSLEW_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSRSLEW_SHIFT)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSRSLEW_RANGE                     9:8
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSRSLEW_WOFFSET                   0x0
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSRSLEW_DEFAULT                   _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSRSLEW_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSRSLEW_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSRSLEW_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// LS falling slew rate control.
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSFSLEW_SHIFT                     _MK_SHIFT_CONST(10)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSFSLEW_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSFSLEW_SHIFT)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSFSLEW_RANGE                     11:10
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSFSLEW_WOFFSET                   0x0
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSFSLEW_DEFAULT                   _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSFSLEW_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSFSLEW_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSFSLEW_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Internal loopback inside XCVR cell. Used for IOBIST.
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSLOOPBACK_SHIFT                  _MK_SHIFT_CONST(12)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSLOOPBACK_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSLOOPBACK_SHIFT)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSLOOPBACK_RANGE                  12:12
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSLOOPBACK_WOFFSET                        0x0
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSLOOPBACK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSLOOPBACK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSLOOPBACK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSLOOPBACK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Enable HS termination.
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_TERMEN_SHIFT                      _MK_SHIFT_CONST(13)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_TERMEN_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_TERMEN_SHIFT)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_TERMEN_RANGE                      13:13
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_TERMEN_WOFFSET                    0x0
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_TERMEN_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_TERMEN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_TERMEN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_TERMEN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Force PD input into power down. (Overrides FORCE_PD_POWERUP.)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERDOWN_SHIFT                       _MK_SHIFT_CONST(14)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERDOWN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERDOWN_SHIFT)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERDOWN_RANGE                       14:14
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERDOWN_WOFFSET                     0x0
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERDOWN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERDOWN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERDOWN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERDOWN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Force PD input into power up. 
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERUP_SHIFT                 _MK_SHIFT_CONST(15)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERUP_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERUP_SHIFT)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERUP_RANGE                 15:15
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERUP_WOFFSET                       0x0
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERUP_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERUP_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERUP_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERUP_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Force PD2 input into power down. (Overrides FORCE_PD2_POWERUP.)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERDOWN_SHIFT                      _MK_SHIFT_CONST(16)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERDOWN_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERDOWN_SHIFT)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERDOWN_RANGE                      16:16
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERDOWN_WOFFSET                    0x0
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERDOWN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERDOWN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERDOWN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERDOWN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Force PD2 input into power up.
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERUP_SHIFT                        _MK_SHIFT_CONST(17)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERUP_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERUP_SHIFT)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERUP_RANGE                        17:17
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERUP_WOFFSET                      0x0
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERUP_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERUP_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERUP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERUP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Force PDZI input into power down. (Overrides FORCE_PDZI_POWERUP.)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERDOWN_SHIFT                     _MK_SHIFT_CONST(18)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERDOWN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERDOWN_SHIFT)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERDOWN_RANGE                     18:18
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERDOWN_WOFFSET                   0x0
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERDOWN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERDOWN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERDOWN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERDOWN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Force PDZI input into power up.
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERUP_SHIFT                       _MK_SHIFT_CONST(19)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERUP_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERUP_SHIFT)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERUP_RANGE                       19:19
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERUP_WOFFSET                     0x0
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERUP_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERUP_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERUP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERUP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Disconnect method on the usb transceiver pad
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_DISCON_METHOD_SHIFT                       _MK_SHIFT_CONST(20)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_DISCON_METHOD_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_DISCON_METHOD_SHIFT)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_DISCON_METHOD_RANGE                       20:20
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_DISCON_METHOD_WOFFSET                     0x0
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_DISCON_METHOD_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_DISCON_METHOD_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_DISCON_METHOD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_DISCON_METHOD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Low speed bias selection method for usb transceiver pad
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSBIAS_SEL_SHIFT                  _MK_SHIFT_CONST(21)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSBIAS_SEL_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSBIAS_SEL_SHIFT)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSBIAS_SEL_RANGE                  21:21
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSBIAS_SEL_WOFFSET                        0x0
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSBIAS_SEL_DEFAULT                        _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSBIAS_SEL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSBIAS_SEL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSBIAS_SEL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Most significant bits of SETUP.
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_SETUP_MSB_SHIFT                   _MK_SHIFT_CONST(22)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_SETUP_MSB_FIELD                   (_MK_MASK_CONST(0x7) << APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_SETUP_MSB_SHIFT)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_SETUP_MSB_RANGE                   24:22
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_SETUP_MSB_WOFFSET                 0x0
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_SETUP_MSB_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_SETUP_MSB_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_SETUP_MSB_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_SETUP_MSB_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Most significant bits of HS_SLEW.
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSSLEW_MSB_SHIFT                  _MK_SHIFT_CONST(25)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSSLEW_MSB_FIELD                  (_MK_MASK_CONST(0x7f) << APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSSLEW_MSB_SHIFT)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSSLEW_MSB_RANGE                  31:25
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSSLEW_MSB_WOFFSET                        0x0
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSSLEW_MSB_DEFAULT                        _MK_MASK_CONST(0x10)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSSLEW_MSB_DEFAULT_MASK                   _MK_MASK_CONST(0x7f)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSSLEW_MSB_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSSLEW_MSB_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_UTMIP_BIAS_CFG0_0  // UTMIP Bias cell configuration register 0
+#define APB_MISC_UTMIP_BIAS_CFG0_0                      _MK_ADDR_CONST(0xa0c)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_SECURE                       0x0
+#define APB_MISC_UTMIP_BIAS_CFG0_0_WORD_COUNT                   0x1
+#define APB_MISC_UTMIP_BIAS_CFG0_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_RESET_MASK                   _MK_MASK_CONST(0x1ffffff)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_READ_MASK                    _MK_MASK_CONST(0x1ffffff)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_WRITE_MASK                   _MK_MASK_CONST(0x1ffffff)
+// HS squelch detector level.
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSSQUELCH_LEVEL_SHIFT                  _MK_SHIFT_CONST(0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSSQUELCH_LEVEL_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSSQUELCH_LEVEL_SHIFT)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSSQUELCH_LEVEL_RANGE                  1:0
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSSQUELCH_LEVEL_WOFFSET                        0x0
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSSQUELCH_LEVEL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSSQUELCH_LEVEL_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSSQUELCH_LEVEL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSSQUELCH_LEVEL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// HS disconnect detector level.
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSDISCON_LEVEL_SHIFT                   _MK_SHIFT_CONST(2)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSDISCON_LEVEL_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSDISCON_LEVEL_SHIFT)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSDISCON_LEVEL_RANGE                   3:2
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSDISCON_LEVEL_WOFFSET                 0x0
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSDISCON_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSDISCON_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSDISCON_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSDISCON_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// HS chirp detector level.
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSCHIRP_LEVEL_SHIFT                    _MK_SHIFT_CONST(4)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSCHIRP_LEVEL_FIELD                    (_MK_MASK_CONST(0x3) << APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSCHIRP_LEVEL_SHIFT)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSCHIRP_LEVEL_RANGE                    5:4
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSCHIRP_LEVEL_WOFFSET                  0x0
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSCHIRP_LEVEL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSCHIRP_LEVEL_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSCHIRP_LEVEL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSCHIRP_LEVEL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// SessionEnd detector level.
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_SESS_LEVEL_LEVEL_SHIFT                 _MK_SHIFT_CONST(6)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_SESS_LEVEL_LEVEL_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_SESS_LEVEL_LEVEL_SHIFT)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_SESS_LEVEL_LEVEL_RANGE                 7:6
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_SESS_LEVEL_LEVEL_WOFFSET                       0x0
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_SESS_LEVEL_LEVEL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_SESS_LEVEL_LEVEL_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_SESS_LEVEL_LEVEL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_SESS_LEVEL_LEVEL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Vbus detector level.
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_VBUS_LEVEL_LEVEL_SHIFT                 _MK_SHIFT_CONST(8)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_VBUS_LEVEL_LEVEL_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_VBUS_LEVEL_LEVEL_SHIFT)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_VBUS_LEVEL_LEVEL_RANGE                 9:8
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_VBUS_LEVEL_LEVEL_WOFFSET                       0x0
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_VBUS_LEVEL_LEVEL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_VBUS_LEVEL_LEVEL_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_VBUS_LEVEL_LEVEL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_VBUS_LEVEL_LEVEL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Power down bias circuit.
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_BIASPD_SHIFT                   _MK_SHIFT_CONST(10)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_BIASPD_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_BIASPD_SHIFT)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_BIASPD_RANGE                   10:10
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_BIASPD_WOFFSET                 0x0
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_BIASPD_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_BIASPD_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_BIASPD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_BIASPD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Power down OTG circuit.
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_OTGPD_SHIFT                    _MK_SHIFT_CONST(11)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_OTGPD_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_OTGPD_SHIFT)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_OTGPD_RANGE                    11:11
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_OTGPD_WOFFSET                  0x0
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_OTGPD_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_OTGPD_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_OTGPD_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_OTGPD_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Active 1.5K pullup control offset.
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_PULLUP_OFFSET_SHIFT                     _MK_SHIFT_CONST(12)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_PULLUP_OFFSET_FIELD                     (_MK_MASK_CONST(0x7) << APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_PULLUP_OFFSET_SHIFT)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_PULLUP_OFFSET_RANGE                     14:12
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_PULLUP_OFFSET_WOFFSET                   0x0
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_PULLUP_OFFSET_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_PULLUP_OFFSET_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_PULLUP_OFFSET_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_PULLUP_OFFSET_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Active termination control offset.
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_TERM_OFFSET_SHIFT                       _MK_SHIFT_CONST(15)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_TERM_OFFSET_FIELD                       (_MK_MASK_CONST(0x7) << APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_TERM_OFFSET_SHIFT)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_TERM_OFFSET_RANGE                       17:15
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_TERM_OFFSET_WOFFSET                     0x0
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_TERM_OFFSET_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_TERM_OFFSET_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_TERM_OFFSET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_TERM_OFFSET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// 0: StaticGpi = IdDig. 1: StaticGpi = GPI_VAL.
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_GPI_SEL_SHIFT                  _MK_SHIFT_CONST(18)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_GPI_SEL_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_GPI_SEL_SHIFT)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_GPI_SEL_RANGE                  18:18
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_GPI_SEL_WOFFSET                        0x0
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_GPI_SEL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_GPI_SEL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_GPI_SEL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_GPI_SEL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// See GPI_SEL.
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_GPI_VAL_SHIFT                  _MK_SHIFT_CONST(19)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_GPI_VAL_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_GPI_VAL_SHIFT)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_GPI_VAL_RANGE                  19:19
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_GPI_VAL_WOFFSET                        0x0
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_GPI_VAL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_GPI_VAL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_GPI_VAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_GPI_VAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// 0: IdDig = IdDig. 1: IdDig = IDDIG_VAL.
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_SEL_SHIFT                        _MK_SHIFT_CONST(20)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_SEL_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_SEL_SHIFT)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_SEL_RANGE                        20:20
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_SEL_WOFFSET                      0x0
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_SEL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_SEL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_SEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_SEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// See IDDIG_SEL.
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_VAL_SHIFT                        _MK_SHIFT_CONST(21)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_VAL_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_VAL_SHIFT)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_VAL_RANGE                        21:21
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_VAL_WOFFSET                      0x0
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_VAL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_VAL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_VAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_VAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// 0: IDPD = ~IdPullup. 1: IDPD = IDPD_VAL.
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_SEL_SHIFT                 _MK_SHIFT_CONST(22)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_SEL_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_SEL_SHIFT)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_SEL_RANGE                 22:22
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_SEL_WOFFSET                       0x0
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_SEL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_SEL_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_SEL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_SEL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// See IDPD_SEL.
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_VAL_SHIFT                 _MK_SHIFT_CONST(23)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_VAL_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_VAL_SHIFT)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_VAL_RANGE                 23:23
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_VAL_WOFFSET                       0x0
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_VAL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_VAL_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_VAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_VAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Most significant bit of UTMIP_HSDISCON_LEVEL, bit 2
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSDISCON_LEVEL_MSB_SHIFT                       _MK_SHIFT_CONST(24)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSDISCON_LEVEL_MSB_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSDISCON_LEVEL_MSB_SHIFT)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSDISCON_LEVEL_MSB_RANGE                       24:24
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSDISCON_LEVEL_MSB_WOFFSET                     0x0
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSDISCON_LEVEL_MSB_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSDISCON_LEVEL_MSB_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSDISCON_LEVEL_MSB_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSDISCON_LEVEL_MSB_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_UTMIP_HSRX_CFG0_0  // UTMIP High speed receive config 0 
+#define APB_MISC_UTMIP_HSRX_CFG0_0                      _MK_ADDR_CONST(0xa10)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_SECURE                       0x0
+#define APB_MISC_UTMIP_HSRX_CFG0_0_WORD_COUNT                   0x1
+#define APB_MISC_UTMIP_HSRX_CFG0_0_RESET_VAL                    _MK_MASK_CONST(0x91653400)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
+// Require 4 sync pattern transitions (01) instead of 3
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_USE4SYNC_TRAN_SHIFT                    _MK_SHIFT_CONST(0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_USE4SYNC_TRAN_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_USE4SYNC_TRAN_SHIFT)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_USE4SYNC_TRAN_RANGE                    0:0
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_USE4SYNC_TRAN_WOFFSET                  0x0
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_USE4SYNC_TRAN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_USE4SYNC_TRAN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_USE4SYNC_TRAN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_USE4SYNC_TRAN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Sync pattern detection needs 3 consecutive samples instead of 4
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_THREE_SYNCBITS_SHIFT                   _MK_SHIFT_CONST(1)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_THREE_SYNCBITS_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_THREE_SYNCBITS_SHIFT)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_THREE_SYNCBITS_RANGE                   1:1
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_THREE_SYNCBITS_WOFFSET                 0x0
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_THREE_SYNCBITS_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_THREE_SYNCBITS_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_THREE_SYNCBITS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_THREE_SYNCBITS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Based on incoming edges and current sampling position, adjust phase
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PHASE_ADJUST_SHIFT                     _MK_SHIFT_CONST(2)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PHASE_ADJUST_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PHASE_ADJUST_SHIFT)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PHASE_ADJUST_RANGE                     3:2
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PHASE_ADJUST_WOFFSET                   0x0
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PHASE_ADJUST_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PHASE_ADJUST_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PHASE_ADJUST_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PHASE_ADJUST_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Retime the path. 
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_INERTIA_SHIFT                   _MK_SHIFT_CONST(4)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_INERTIA_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_INERTIA_SHIFT)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_INERTIA_RANGE                   5:4
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_INERTIA_WOFFSET                 0x0
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_INERTIA_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_INERTIA_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_INERTIA_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_INERTIA_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Pass through the feedback, do not block it.
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PASS_FEEDBACK_SHIFT                    _MK_SHIFT_CONST(6)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PASS_FEEDBACK_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PASS_FEEDBACK_SHIFT)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PASS_FEEDBACK_RANGE                    6:6
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PASS_FEEDBACK_WOFFSET                  0x0
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PASS_FEEDBACK_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PASS_FEEDBACK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PASS_FEEDBACK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PASS_FEEDBACK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// When in Chirp Mode, allow chirp rx data through
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PASS_CHIRP_SHIFT                       _MK_SHIFT_CONST(7)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PASS_CHIRP_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PASS_CHIRP_SHIFT)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PASS_CHIRP_RANGE                       7:7
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PASS_CHIRP_WOFFSET                     0x0
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PASS_CHIRP_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PASS_CHIRP_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PASS_CHIRP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PASS_CHIRP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Do not declare underrun errors
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_UNDERRUN_DISABLE_SHIFT                 _MK_SHIFT_CONST(8)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_UNDERRUN_DISABLE_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_UNDERRUN_DISABLE_SHIFT)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_UNDERRUN_DISABLE_RANGE                 8:8
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_UNDERRUN_DISABLE_WOFFSET                       0x0
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_UNDERRUN_DISABLE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_UNDERRUN_DISABLE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_UNDERRUN_DISABLE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_UNDERRUN_DISABLE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Do not declare overrun errors until overflow of FIFO
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_OVERRUN_DISABLE_SHIFT                  _MK_SHIFT_CONST(9)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_OVERRUN_DISABLE_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_OVERRUN_DISABLE_SHIFT)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_OVERRUN_DISABLE_RANGE                  9:9
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_OVERRUN_DISABLE_WOFFSET                        0x0
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_OVERRUN_DISABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_OVERRUN_DISABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_OVERRUN_DISABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_OVERRUN_DISABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Depth of elastic input store
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_LIMIT_SHIFT                    _MK_SHIFT_CONST(10)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_LIMIT_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_LIMIT_SHIFT)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_LIMIT_RANGE                    14:10
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_LIMIT_WOFFSET                  0x0
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_LIMIT_DEFAULT                  _MK_MASK_CONST(0xd)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_LIMIT_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_LIMIT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_LIMIT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Number of cycles of idle to declare IDLE. 
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_IDLE_WAIT_SHIFT                        _MK_SHIFT_CONST(15)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_IDLE_WAIT_FIELD                        (_MK_MASK_CONST(0x1f) << APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_IDLE_WAIT_SHIFT)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_IDLE_WAIT_RANGE                        19:15
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_IDLE_WAIT_WOFFSET                      0x0
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_IDLE_WAIT_DEFAULT                      _MK_MASK_CONST(0xa)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_IDLE_WAIT_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_IDLE_WAIT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_IDLE_WAIT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Do not strip incoming data
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_NO_STRIPPING_SHIFT                     _MK_SHIFT_CONST(20)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_NO_STRIPPING_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_NO_STRIPPING_SHIFT)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_NO_STRIPPING_RANGE                     20:20
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_NO_STRIPPING_WOFFSET                   0x0
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_NO_STRIPPING_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_NO_STRIPPING_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_NO_STRIPPING_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_NO_STRIPPING_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Limit the delay of the squelch at EOP time
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_SQUELCH_EOP_DLY_SHIFT                  _MK_SHIFT_CONST(21)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_SQUELCH_EOP_DLY_FIELD                  (_MK_MASK_CONST(0x7) << APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_SQUELCH_EOP_DLY_SHIFT)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_SQUELCH_EOP_DLY_RANGE                  23:21
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_SQUELCH_EOP_DLY_WOFFSET                        0x0
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_SQUELCH_EOP_DLY_DEFAULT                        _MK_MASK_CONST(0x3)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_SQUELCH_EOP_DLY_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_SQUELCH_EOP_DLY_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_SQUELCH_EOP_DLY_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// The number of (edges-1) needed to move the sampling point
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_UPDN_DIV_SHIFT                  _MK_SHIFT_CONST(24)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_UPDN_DIV_FIELD                  (_MK_MASK_CONST(0xf) << APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_UPDN_DIV_SHIFT)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_UPDN_DIV_RANGE                  27:24
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_UPDN_DIV_WOFFSET                        0x0
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_UPDN_DIV_DEFAULT                        _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_UPDN_DIV_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_UPDN_DIV_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_UPDN_DIV_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Realign the inertia counters on a new packet
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_REALIGN_ON_NEW_PKT_SHIFT                       _MK_SHIFT_CONST(28)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_REALIGN_ON_NEW_PKT_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_REALIGN_ON_NEW_PKT_SHIFT)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_REALIGN_ON_NEW_PKT_RANGE                       28:28
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_REALIGN_ON_NEW_PKT_WOFFSET                     0x0
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_REALIGN_ON_NEW_PKT_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_REALIGN_ON_NEW_PKT_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_REALIGN_ON_NEW_PKT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_REALIGN_ON_NEW_PKT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Allow consecutive ups and downs on the bits, debug only, set to 0.
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ALLOW_CONSEC_UPDN_SHIFT                        _MK_SHIFT_CONST(29)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ALLOW_CONSEC_UPDN_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ALLOW_CONSEC_UPDN_SHIFT)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ALLOW_CONSEC_UPDN_RANGE                        29:29
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ALLOW_CONSEC_UPDN_WOFFSET                      0x0
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ALLOW_CONSEC_UPDN_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ALLOW_CONSEC_UPDN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ALLOW_CONSEC_UPDN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ALLOW_CONSEC_UPDN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Keep the stay alive pattern on active
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_KEEP_PATT_ON_ACTIVE_SHIFT                      _MK_SHIFT_CONST(30)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_KEEP_PATT_ON_ACTIVE_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_KEEP_PATT_ON_ACTIVE_SHIFT)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_KEEP_PATT_ON_ACTIVE_RANGE                      31:30
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_KEEP_PATT_ON_ACTIVE_WOFFSET                    0x0
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_KEEP_PATT_ON_ACTIVE_DEFAULT                    _MK_MASK_CONST(0x2)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_KEEP_PATT_ON_ACTIVE_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_KEEP_PATT_ON_ACTIVE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_KEEP_PATT_ON_ACTIVE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_UTMIP_HSRX_CFG1_0  // UTMIP High speed receive config 1
+#define APB_MISC_UTMIP_HSRX_CFG1_0                      _MK_ADDR_CONST(0xa14)
+#define APB_MISC_UTMIP_HSRX_CFG1_0_SECURE                       0x0
+#define APB_MISC_UTMIP_HSRX_CFG1_0_WORD_COUNT                   0x1
+#define APB_MISC_UTMIP_HSRX_CFG1_0_RESET_VAL                    _MK_MASK_CONST(0x13)
+#define APB_MISC_UTMIP_HSRX_CFG1_0_RESET_MASK                   _MK_MASK_CONST(0x3f)
+#define APB_MISC_UTMIP_HSRX_CFG1_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG1_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG1_0_READ_MASK                    _MK_MASK_CONST(0x3f)
+#define APB_MISC_UTMIP_HSRX_CFG1_0_WRITE_MASK                   _MK_MASK_CONST(0x3f)
+// Allow Keep Alive packets 
+#define APB_MISC_UTMIP_HSRX_CFG1_0_UTMIP_HS_ALLOW_KEEP_ALIVE_SHIFT                      _MK_SHIFT_CONST(0)
+#define APB_MISC_UTMIP_HSRX_CFG1_0_UTMIP_HS_ALLOW_KEEP_ALIVE_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_HSRX_CFG1_0_UTMIP_HS_ALLOW_KEEP_ALIVE_SHIFT)
+#define APB_MISC_UTMIP_HSRX_CFG1_0_UTMIP_HS_ALLOW_KEEP_ALIVE_RANGE                      0:0
+#define APB_MISC_UTMIP_HSRX_CFG1_0_UTMIP_HS_ALLOW_KEEP_ALIVE_WOFFSET                    0x0
+#define APB_MISC_UTMIP_HSRX_CFG1_0_UTMIP_HS_ALLOW_KEEP_ALIVE_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_HSRX_CFG1_0_UTMIP_HS_ALLOW_KEEP_ALIVE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_HSRX_CFG1_0_UTMIP_HS_ALLOW_KEEP_ALIVE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG1_0_UTMIP_HS_ALLOW_KEEP_ALIVE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// How long to wait before start of sync launches RxActive
+#define APB_MISC_UTMIP_HSRX_CFG1_0_UTMIP_HS_SYNC_START_DLY_SHIFT                        _MK_SHIFT_CONST(1)
+#define APB_MISC_UTMIP_HSRX_CFG1_0_UTMIP_HS_SYNC_START_DLY_FIELD                        (_MK_MASK_CONST(0x1f) << APB_MISC_UTMIP_HSRX_CFG1_0_UTMIP_HS_SYNC_START_DLY_SHIFT)
+#define APB_MISC_UTMIP_HSRX_CFG1_0_UTMIP_HS_SYNC_START_DLY_RANGE                        5:1
+#define APB_MISC_UTMIP_HSRX_CFG1_0_UTMIP_HS_SYNC_START_DLY_WOFFSET                      0x0
+#define APB_MISC_UTMIP_HSRX_CFG1_0_UTMIP_HS_SYNC_START_DLY_DEFAULT                      _MK_MASK_CONST(0x9)
+#define APB_MISC_UTMIP_HSRX_CFG1_0_UTMIP_HS_SYNC_START_DLY_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define APB_MISC_UTMIP_HSRX_CFG1_0_UTMIP_HS_SYNC_START_DLY_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG1_0_UTMIP_HS_SYNC_START_DLY_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_UTMIP_FSLSRX_CFG0_0  // UTMIP full and Low speed receive config 0
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0                    _MK_ADDR_CONST(0xa18)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_SECURE                     0x0
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_WORD_COUNT                         0x1
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_RESET_VAL                  _MK_MASK_CONST(0xfd548429)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+// Give up on packet if a long sequence of J 
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_LIMIT_SHIFT                  _MK_SHIFT_CONST(0)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_LIMIT_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_LIMIT_SHIFT)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_LIMIT_RANGE                  0:0
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_LIMIT_WOFFSET                        0x0
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_LIMIT_DEFAULT                        _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_LIMIT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_LIMIT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_LIMIT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// 20 bits of idle should end the packet if FsLsIdleCountLimitCfg=1.
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_MAX_SHIFT                    _MK_SHIFT_CONST(1)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_MAX_FIELD                    (_MK_MASK_CONST(0x3f) << APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_MAX_SHIFT)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_MAX_RANGE                    6:1
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_MAX_WOFFSET                  0x0
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_MAX_DEFAULT                  _MK_MASK_CONST(0x14)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_MAX_DEFAULT_MASK                     _MK_MASK_CONST(0x3f)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_MAX_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_MAX_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Enable the reset of the state machine on extended SE0
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_LIMIT_SHIFT                   _MK_SHIFT_CONST(7)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_LIMIT_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_LIMIT_SHIFT)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_LIMIT_RANGE                   7:7
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_LIMIT_WOFFSET                 0x0
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_LIMIT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_LIMIT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_LIMIT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_LIMIT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// 4 bits of of SEO should exceed the time limit
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_MAX_SHIFT                     _MK_SHIFT_CONST(8)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_MAX_FIELD                     (_MK_MASK_CONST(0x3f) << APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_MAX_SHIFT)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_MAX_RANGE                     13:8
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_MAX_WOFFSET                   0x0
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_MAX_DEFAULT                   _MK_MASK_CONST(0x4)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_MAX_DEFAULT_MASK                      _MK_MASK_CONST(0x3f)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_MAX_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_MAX_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Require a full sync pattern to declare the data received
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_ACTIVE_ON_FULL_SYNC_SHIFT                       _MK_SHIFT_CONST(14)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_ACTIVE_ON_FULL_SYNC_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_ACTIVE_ON_FULL_SYNC_SHIFT)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_ACTIVE_ON_FULL_SYNC_RANGE                       14:14
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_ACTIVE_ON_FULL_SYNC_WOFFSET                     0x0
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_ACTIVE_ON_FULL_SYNC_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_ACTIVE_ON_FULL_SYNC_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_ACTIVE_ON_FULL_SYNC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_ACTIVE_ON_FULL_SYNC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Limit the number of bit times a K can last
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_LIMIT_SHIFT                      _MK_SHIFT_CONST(15)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_LIMIT_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_LIMIT_SHIFT)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_LIMIT_RANGE                      15:15
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_LIMIT_WOFFSET                    0x0
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_LIMIT_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_LIMIT_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_LIMIT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_LIMIT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Number of K bits in question
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_MAX_SHIFT                        _MK_SHIFT_CONST(16)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_MAX_FIELD                        (_MK_MASK_CONST(0x3f) << APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_MAX_SHIFT)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_MAX_RANGE                        21:16
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_MAX_WOFFSET                      0x0
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_MAX_DEFAULT                      _MK_MASK_CONST(0x14)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_MAX_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_MAX_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_MAX_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Only look for transitioning out of EOP
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_EOP_ENDS_AT_SE0_SHIFT                   _MK_SHIFT_CONST(22)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_EOP_ENDS_AT_SE0_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_EOP_ENDS_AT_SE0_SHIFT)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_EOP_ENDS_AT_SE0_RANGE                   22:22
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_EOP_ENDS_AT_SE0_WOFFSET                 0x0
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_EOP_ENDS_AT_SE0_DEFAULT                 _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_EOP_ENDS_AT_SE0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_EOP_ENDS_AT_SE0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_EOP_ENDS_AT_SE0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Do not allow >= dribble bits 
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_LWR_DRIBBLE_SIZE_SHIFT                  _MK_SHIFT_CONST(23)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_LWR_DRIBBLE_SIZE_FIELD                  (_MK_MASK_CONST(0x7) << APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_LWR_DRIBBLE_SIZE_SHIFT)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_LWR_DRIBBLE_SIZE_RANGE                  25:23
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_LWR_DRIBBLE_SIZE_WOFFSET                        0x0
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_LWR_DRIBBLE_SIZE_DEFAULT                        _MK_MASK_CONST(0x2)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_LWR_DRIBBLE_SIZE_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_LWR_DRIBBLE_SIZE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_LWR_DRIBBLE_SIZE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Do not allow <= dribble bits
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_UPR_DRIBBLE_SIZE_SHIFT                  _MK_SHIFT_CONST(26)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_UPR_DRIBBLE_SIZE_FIELD                  (_MK_MASK_CONST(0x7) << APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_UPR_DRIBBLE_SIZE_SHIFT)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_UPR_DRIBBLE_SIZE_RANGE                  28:26
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_UPR_DRIBBLE_SIZE_WOFFSET                        0x0
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_UPR_DRIBBLE_SIZE_DEFAULT                        _MK_MASK_CONST(0x7)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_UPR_DRIBBLE_SIZE_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_UPR_DRIBBLE_SIZE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_UPR_DRIBBLE_SIZE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SERIAL_SE0_RCV_SHIFT                    _MK_SHIFT_CONST(29)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SERIAL_SE0_RCV_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SERIAL_SE0_RCV_SHIFT)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SERIAL_SE0_RCV_RANGE                    29:29
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SERIAL_SE0_RCV_WOFFSET                  0x0
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SERIAL_SE0_RCV_DEFAULT                  _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SERIAL_SE0_RCV_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SERIAL_SE0_RCV_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SERIAL_SE0_RCV_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Filter SE1
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_FILTER_SHIFT                        _MK_SHIFT_CONST(30)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_FILTER_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_FILTER_SHIFT)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_FILTER_RANGE                        30:30
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_FILTER_WOFFSET                      0x0
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_FILTER_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_FILTER_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_FILTER_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_FILTER_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// One SE1, don't allow dribble
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_DRIBBLE_FILTER_SHIFT                        _MK_SHIFT_CONST(31)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_DRIBBLE_FILTER_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_DRIBBLE_FILTER_SHIFT)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_DRIBBLE_FILTER_RANGE                        31:31
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_DRIBBLE_FILTER_WOFFSET                      0x0
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_DRIBBLE_FILTER_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_DRIBBLE_FILTER_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_DRIBBLE_FILTER_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_DRIBBLE_FILTER_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_UTMIP_FSLSRX_CFG1_0  // UTMIP full and Low speed receive config 1
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0                    _MK_ADDR_CONST(0xa1c)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_SECURE                     0x0
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_WORD_COUNT                         0x1
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_RESET_VAL                  _MK_MASK_CONST(0x2267400)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_RESET_MASK                         _MK_MASK_CONST(0x7ffffff)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_READ_MASK                  _MK_MASK_CONST(0x7ffffff)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_WRITE_MASK                         _MK_MASK_CONST(0x7ffffff)
+// Whether full speed EOP  is determined within 3(0) or 4(1) 60MHz cycles
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_EOP_LENGTH_SHIFT                  _MK_SHIFT_CONST(0)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_EOP_LENGTH_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_EOP_LENGTH_SHIFT)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_EOP_LENGTH_RANGE                  0:0
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_EOP_LENGTH_WOFFSET                        0x0
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_EOP_LENGTH_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_EOP_LENGTH_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_EOP_LENGTH_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_EOP_LENGTH_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Whether full speed uses debouncing
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_DEBOUNCE_SHIFT                    _MK_SHIFT_CONST(1)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_DEBOUNCE_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_DEBOUNCE_SHIFT)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_DEBOUNCE_RANGE                    1:1
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_DEBOUNCE_WOFFSET                  0x0
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_DEBOUNCE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_DEBOUNCE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_DEBOUNCE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_DEBOUNCE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Only look for a KK pattern, instead of KJKK
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_WEAK_SYNC_SHIFT                   _MK_SHIFT_CONST(2)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_WEAK_SYNC_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_WEAK_SYNC_SHIFT)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_WEAK_SYNC_RANGE                   2:2
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_WEAK_SYNC_WOFFSET                 0x0
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_WEAK_SYNC_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_WEAK_SYNC_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_WEAK_SYNC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_WEAK_SYNC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Allow for large dribble in full speed mode
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_LENIENT_DRIBBLE_SHIFT                     _MK_SHIFT_CONST(3)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_LENIENT_DRIBBLE_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_LENIENT_DRIBBLE_SHIFT)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_LENIENT_DRIBBLE_RANGE                     3:3
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_LENIENT_DRIBBLE_WOFFSET                   0x0
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_LENIENT_DRIBBLE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_LENIENT_DRIBBLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_LENIENT_DRIBBLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_LENIENT_DRIBBLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Allow for large dribble in low  speed mode
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_LENIENT_DRIBBLE_SHIFT                     _MK_SHIFT_CONST(4)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_LENIENT_DRIBBLE_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_LENIENT_DRIBBLE_SHIFT)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_LENIENT_DRIBBLE_RANGE                     4:4
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_LENIENT_DRIBBLE_WOFFSET                   0x0
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_LENIENT_DRIBBLE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_LENIENT_DRIBBLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_LENIENT_DRIBBLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_LENIENT_DRIBBLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Only for this number of 60MHz of SEO and Idle to end packet
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_SE0_COUNT_SHIFT                   _MK_SHIFT_CONST(5)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_SE0_COUNT_FIELD                   (_MK_MASK_CONST(0x3f) << APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_SE0_COUNT_SHIFT)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_SE0_COUNT_RANGE                   10:5
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_SE0_COUNT_WOFFSET                 0x0
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_SE0_COUNT_DEFAULT                 _MK_MASK_CONST(0x20)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_SE0_COUNT_DEFAULT_MASK                    _MK_MASK_CONST(0x3f)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_SE0_COUNT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_SE0_COUNT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Number of SEO clock cycles to block bit extraction
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EOP_START_COUNT_SHIFT                     _MK_SHIFT_CONST(11)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EOP_START_COUNT_FIELD                     (_MK_MASK_CONST(0x3f) << APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EOP_START_COUNT_SHIFT)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EOP_START_COUNT_RANGE                     16:11
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EOP_START_COUNT_WOFFSET                   0x0
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EOP_START_COUNT_DEFAULT                   _MK_MASK_CONST(0xe)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EOP_START_COUNT_DEFAULT_MASK                      _MK_MASK_CONST(0x3f)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EOP_START_COUNT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EOP_START_COUNT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Phase count on which LS bits are extracted
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EXTRACTION_COUNT_SHIFT                    _MK_SHIFT_CONST(17)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EXTRACTION_COUNT_FIELD                    (_MK_MASK_CONST(0x3f) << APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EXTRACTION_COUNT_SHIFT)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EXTRACTION_COUNT_RANGE                    22:17
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EXTRACTION_COUNT_WOFFSET                  0x0
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EXTRACTION_COUNT_DEFAULT                  _MK_MASK_CONST(0x13)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EXTRACTION_COUNT_DEFAULT_MASK                     _MK_MASK_CONST(0x3f)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EXTRACTION_COUNT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EXTRACTION_COUNT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Number of clock cycle of LS stable
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_BOUNCE_LENGTH_SHIFT                       _MK_SHIFT_CONST(23)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_BOUNCE_LENGTH_FIELD                       (_MK_MASK_CONST(0x7) << APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_BOUNCE_LENGTH_SHIFT)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_BOUNCE_LENGTH_RANGE                       25:23
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_BOUNCE_LENGTH_WOFFSET                     0x0
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_BOUNCE_LENGTH_DEFAULT                     _MK_MASK_CONST(0x4)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_BOUNCE_LENGTH_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_BOUNCE_LENGTH_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_BOUNCE_LENGTH_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Assumes line state filtering table is inclusive, not exclusive
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_EARLY_LINE_STATE_FILTER_SHIFT                        _MK_SHIFT_CONST(26)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_EARLY_LINE_STATE_FILTER_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_EARLY_LINE_STATE_FILTER_SHIFT)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_EARLY_LINE_STATE_FILTER_RANGE                        26:26
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_EARLY_LINE_STATE_FILTER_WOFFSET                      0x0
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_EARLY_LINE_STATE_FILTER_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_EARLY_LINE_STATE_FILTER_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_EARLY_LINE_STATE_FILTER_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_EARLY_LINE_STATE_FILTER_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_UTMIP_TX_CFG0_0  // UTMIP transmit config signals 
+#define APB_MISC_UTMIP_TX_CFG0_0                        _MK_ADDR_CONST(0xa20)
+#define APB_MISC_UTMIP_TX_CFG0_0_SECURE                         0x0
+#define APB_MISC_UTMIP_TX_CFG0_0_WORD_COUNT                     0x1
+#define APB_MISC_UTMIP_TX_CFG0_0_RESET_VAL                      _MK_MASK_CONST(0x10200)
+#define APB_MISC_UTMIP_TX_CFG0_0_RESET_MASK                     _MK_MASK_CONST(0xfffff)
+#define APB_MISC_UTMIP_TX_CFG0_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_READ_MASK                      _MK_MASK_CONST(0xfffff)
+#define APB_MISC_UTMIP_TX_CFG0_0_WRITE_MASK                     _MK_MASK_CONST(0xfffff)
+// Do not sent SYNC or EOP
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_SYNC_NO_EOP_SHIFT                     _MK_SHIFT_CONST(0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_SYNC_NO_EOP_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_SYNC_NO_EOP_SHIFT)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_SYNC_NO_EOP_RANGE                     0:0
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_SYNC_NO_EOP_WOFFSET                   0x0
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_SYNC_NO_EOP_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_SYNC_NO_EOP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_SYNC_NO_EOP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_SYNC_NO_EOP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// No encoding, static programming
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_ENCODING_SHIFT                        _MK_SHIFT_CONST(1)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_ENCODING_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_ENCODING_SHIFT)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_ENCODING_RANGE                        1:1
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_ENCODING_WOFFSET                      0x0
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_ENCODING_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_ENCODING_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_ENCODING_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_ENCODING_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// No bit stuffing, static programming
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_STUFFING_SHIFT                        _MK_SHIFT_CONST(2)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_STUFFING_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_STUFFING_SHIFT)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_STUFFING_RANGE                        2:2
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_STUFFING_WOFFSET                      0x0
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_STUFFING_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_STUFFING_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_STUFFING_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_STUFFING_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Sof when OpMode 2 -- not likely, for Chirp
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_ENCODE_SHIFT                   _MK_SHIFT_CONST(3)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_ENCODE_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_ENCODE_SHIFT)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_ENCODE_RANGE                   3:3
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_ENCODE_WOFFSET                 0x0
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_ENCODE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_ENCODE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_ENCODE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_ENCODE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Sof when OpMode 3 -- perhaps, when sending controller made packets
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_STUFF_SHIFT                    _MK_SHIFT_CONST(4)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_STUFF_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_STUFF_SHIFT)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_STUFF_RANGE                    4:4
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_STUFF_WOFFSET                  0x0
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_STUFF_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_STUFF_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_STUFF_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_STUFF_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// SIE, not macrocell, detects LineState change to resume
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SIE_RESUME_ON_LINESTATE_SHIFT                    _MK_SHIFT_CONST(5)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SIE_RESUME_ON_LINESTATE_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SIE_RESUME_ON_LINESTATE_SHIFT)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SIE_RESUME_ON_LINESTATE_RANGE                    5:5
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SIE_RESUME_ON_LINESTATE_WOFFSET                  0x0
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SIE_RESUME_ON_LINESTATE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SIE_RESUME_ON_LINESTATE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SIE_RESUME_ON_LINESTATE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SIE_RESUME_ON_LINESTATE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// output enable turns on  1 cycle before
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_PREAMBLE_OUTPUT_ENABLE_SHIFT                  _MK_SHIFT_CONST(6)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_PREAMBLE_OUTPUT_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_PREAMBLE_OUTPUT_ENABLE_SHIFT)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_PREAMBLE_OUTPUT_ENABLE_RANGE                  6:6
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_PREAMBLE_OUTPUT_ENABLE_WOFFSET                        0x0
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_PREAMBLE_OUTPUT_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_PREAMBLE_OUTPUT_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_PREAMBLE_OUTPUT_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_PREAMBLE_OUTPUT_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// output enable turns off 1 cycle after
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_POSTAMBLE_OUTPUT_ENABLE_SHIFT                 _MK_SHIFT_CONST(7)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_POSTAMBLE_OUTPUT_ENABLE_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_POSTAMBLE_OUTPUT_ENABLE_SHIFT)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_POSTAMBLE_OUTPUT_ENABLE_RANGE                 7:7
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_POSTAMBLE_OUTPUT_ENABLE_WOFFSET                       0x0
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_POSTAMBLE_OUTPUT_ENABLE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_POSTAMBLE_OUTPUT_ENABLE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_POSTAMBLE_OUTPUT_ENABLE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_POSTAMBLE_OUTPUT_ENABLE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Disable high speed disconnect
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_DISABLE_SHIFT                  _MK_SHIFT_CONST(8)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_DISABLE_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_DISABLE_SHIFT)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_DISABLE_RANGE                  8:8
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_DISABLE_WOFFSET                        0x0
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_DISABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_DISABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_DISABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_DISABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Only check during EOP
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_EOP_ONLY_SHIFT                 _MK_SHIFT_CONST(9)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_EOP_ONLY_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_EOP_ONLY_SHIFT)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_EOP_ONLY_RANGE                 9:9
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_EOP_ONLY_WOFFSET                       0x0
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_EOP_ONLY_DEFAULT                       _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_EOP_ONLY_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_EOP_ONLY_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_EOP_ONLY_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_TX_IPG_DLY_SHIFT                      _MK_SHIFT_CONST(10)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_TX_IPG_DLY_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_TX_IPG_DLY_SHIFT)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_TX_IPG_DLY_RANGE                      14:10
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_TX_IPG_DLY_WOFFSET                    0x0
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_TX_IPG_DLY_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_TX_IPG_DLY_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_TX_IPG_DLY_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_TX_IPG_DLY_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_READY_WAIT_FOR_VALID_SHIFT                    _MK_SHIFT_CONST(15)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_READY_WAIT_FOR_VALID_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_READY_WAIT_FOR_VALID_SHIFT)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_READY_WAIT_FOR_VALID_RANGE                    15:15
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_READY_WAIT_FOR_VALID_WOFFSET                  0x0
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_READY_WAIT_FOR_VALID_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_READY_WAIT_FOR_VALID_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_READY_WAIT_FOR_VALID_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_READY_WAIT_FOR_VALID_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Allow SOP to be source of transmit error stuffing
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FSLS_ALLOW_SOP_TX_STUFF_ERR_SHIFT                        _MK_SHIFT_CONST(16)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FSLS_ALLOW_SOP_TX_STUFF_ERR_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FSLS_ALLOW_SOP_TX_STUFF_ERR_SHIFT)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FSLS_ALLOW_SOP_TX_STUFF_ERR_RANGE                        16:16
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FSLS_ALLOW_SOP_TX_STUFF_ERR_WOFFSET                      0x0
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FSLS_ALLOW_SOP_TX_STUFF_ERR_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FSLS_ALLOW_SOP_TX_STUFF_ERR_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FSLS_ALLOW_SOP_TX_STUFF_ERR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FSLS_ALLOW_SOP_TX_STUFF_ERR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// output enable turns on  1/2 cycle before
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_OUTPUT_ENABLE_SHIFT                  _MK_SHIFT_CONST(17)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_OUTPUT_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_OUTPUT_ENABLE_SHIFT)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_OUTPUT_ENABLE_RANGE                  17:17
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_OUTPUT_ENABLE_WOFFSET                        0x0
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_OUTPUT_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_OUTPUT_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_OUTPUT_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_OUTPUT_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// output enable turns off 1/2 cycle after 
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_POSTAMBLE_OUTPUT_ENABLE_SHIFT                 _MK_SHIFT_CONST(18)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_POSTAMBLE_OUTPUT_ENABLE_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_POSTAMBLE_OUTPUT_ENABLE_SHIFT)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_POSTAMBLE_OUTPUT_ENABLE_RANGE                 18:18
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_POSTAMBLE_OUTPUT_ENABLE_WOFFSET                       0x0
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_POSTAMBLE_OUTPUT_ENABLE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_POSTAMBLE_OUTPUT_ENABLE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_POSTAMBLE_OUTPUT_ENABLE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_POSTAMBLE_OUTPUT_ENABLE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// output enable sends an initial J before sync pattern
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_J_SHIFT                      _MK_SHIFT_CONST(19)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_J_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_J_SHIFT)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_J_RANGE                      19:19
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_J_WOFFSET                    0x0
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_J_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_J_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_J_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_J_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_UTMIP_MISC_CFG0_0  // UTMIP miscellaneous configurations
+#define APB_MISC_UTMIP_MISC_CFG0_0                      _MK_ADDR_CONST(0xa24)
+#define APB_MISC_UTMIP_MISC_CFG0_0_SECURE                       0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_WORD_COUNT                   0x1
+#define APB_MISC_UTMIP_MISC_CFG0_0_RESET_VAL                    _MK_MASK_CONST(0x3e00078)
+#define APB_MISC_UTMIP_MISC_CFG0_0_RESET_MASK                   _MK_MASK_CONST(0x7fffffff)
+#define APB_MISC_UTMIP_MISC_CFG0_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_READ_MASK                    _MK_MASK_CONST(0x7fffffff)
+#define APB_MISC_UTMIP_MISC_CFG0_0_WRITE_MASK                   _MK_MASK_CONST(0x7fffffff)
+// Use combinational terminations or synced through CLKXTAL
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_COMB_TERMS_SHIFT                       _MK_SHIFT_CONST(0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_COMB_TERMS_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_COMB_TERMS_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_COMB_TERMS_RANGE                       0:0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_COMB_TERMS_WOFFSET                     0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_COMB_TERMS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_COMB_TERMS_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_COMB_TERMS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_COMB_TERMS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Use free running terminations at all time
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_ALWAYS_FREE_RUNNING_TERMS_SHIFT                        _MK_SHIFT_CONST(1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_ALWAYS_FREE_RUNNING_TERMS_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_ALWAYS_FREE_RUNNING_TERMS_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_ALWAYS_FREE_RUNNING_TERMS_RANGE                        1:1
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_ALWAYS_FREE_RUNNING_TERMS_WOFFSET                      0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_ALWAYS_FREE_RUNNING_TERMS_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_ALWAYS_FREE_RUNNING_TERMS_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_ALWAYS_FREE_RUNNING_TERMS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_ALWAYS_FREE_RUNNING_TERMS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Ignore free running terminations, even when no clock
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_NEVER_FREE_RUNNING_TERMS_SHIFT                 _MK_SHIFT_CONST(2)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_NEVER_FREE_RUNNING_TERMS_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_NEVER_FREE_RUNNING_TERMS_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_NEVER_FREE_RUNNING_TERMS_RANGE                 2:2
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_NEVER_FREE_RUNNING_TERMS_WOFFSET                       0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_NEVER_FREE_RUNNING_TERMS_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_NEVER_FREE_RUNNING_TERMS_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_NEVER_FREE_RUNNING_TERMS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_NEVER_FREE_RUNNING_TERMS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Don't use free running terminations during suspend.
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_NO_FREE_ON_SUSPEND_SHIFT                       _MK_SHIFT_CONST(3)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_NO_FREE_ON_SUSPEND_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_NO_FREE_ON_SUSPEND_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_NO_FREE_ON_SUSPEND_RANGE                       3:3
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_NO_FREE_ON_SUSPEND_WOFFSET                     0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_NO_FREE_ON_SUSPEND_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_NO_FREE_ON_SUSPEND_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_NO_FREE_ON_SUSPEND_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_NO_FREE_ON_SUSPEND_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Determines if all signal need to be stable to not change a config.
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_STABLE_ALL_SHIFT                       _MK_SHIFT_CONST(4)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_STABLE_ALL_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_STABLE_ALL_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_STABLE_ALL_RANGE                       4:4
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_STABLE_ALL_WOFFSET                     0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_STABLE_ALL_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_STABLE_ALL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_STABLE_ALL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_STABLE_ALL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Number of cycles of crystal clock of signal not changing to consider stable.
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_STABLE_COUNT_SHIFT                     _MK_SHIFT_CONST(5)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_STABLE_COUNT_FIELD                     (_MK_MASK_CONST(0x7) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_STABLE_COUNT_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_STABLE_COUNT_RANGE                     7:5
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_STABLE_COUNT_WOFFSET                   0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_STABLE_COUNT_DEFAULT                   _MK_MASK_CONST(0x3)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_STABLE_COUNT_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_STABLE_COUNT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_STABLE_COUNT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Force DM pulldown active.
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DM_SHIFT                  _MK_SHIFT_CONST(8)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DM_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DM_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DM_RANGE                  8:8
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DM_WOFFSET                        0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DM_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DM_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Force DP pulldown active.
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DP_SHIFT                  _MK_SHIFT_CONST(9)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DP_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DP_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DP_RANGE                  9:9
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DP_WOFFSET                        0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DP_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DP_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Force DM pullup active.      
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DM_SHIFT                  _MK_SHIFT_CONST(10)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DM_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DM_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DM_RANGE                  10:10
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DM_WOFFSET                        0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DM_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DM_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Force DP pullup active.
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DP_SHIFT                  _MK_SHIFT_CONST(11)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DP_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DP_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DP_RANGE                  11:11
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DP_WOFFSET                        0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DP_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DP_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Force DM pulldown inactive. (Overrides FORCE_PULLDN_DM.)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DM_SHIFT                        _MK_SHIFT_CONST(12)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DM_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DM_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DM_RANGE                        12:12
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DM_WOFFSET                      0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DM_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DM_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DM_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DM_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Force DP pulldown inactive. (Overrides FORCE_PULLDN_DP.)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DP_SHIFT                        _MK_SHIFT_CONST(13)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DP_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DP_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DP_RANGE                        13:13
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DP_WOFFSET                      0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DP_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DP_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Force DM pullup inactive. (Overrides FORCE_PULLUP_DM.)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DM_SHIFT                        _MK_SHIFT_CONST(14)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DM_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DM_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DM_RANGE                        14:14
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DM_WOFFSET                      0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DM_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DM_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DM_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DM_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Force DP pullup inactive. (Overrides FORCE_PULLUP_DP.)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DP_SHIFT                        _MK_SHIFT_CONST(15)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DP_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DP_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DP_RANGE                        15:15
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DP_WOFFSET                      0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DP_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DP_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Force HS termination active.
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_TERM_SHIFT                    _MK_SHIFT_CONST(16)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_TERM_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_TERM_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_TERM_RANGE                    16:16
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_TERM_WOFFSET                  0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_TERM_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_TERM_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_TERM_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_TERM_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Force HS termination inactive.
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_HS_TERM_SHIFT                  _MK_SHIFT_CONST(17)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_HS_TERM_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_HS_TERM_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_HS_TERM_RANGE                  17:17
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_HS_TERM_WOFFSET                        0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_HS_TERM_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_HS_TERM_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_HS_TERM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_HS_TERM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Force HS clock always on.
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_CLOCK_ON_SHIFT                        _MK_SHIFT_CONST(18)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_CLOCK_ON_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_CLOCK_ON_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_CLOCK_ON_RANGE                        18:18
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_CLOCK_ON_WOFFSET                      0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_CLOCK_ON_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_CLOCK_ON_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_CLOCK_ON_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_CLOCK_ON_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Force error insertion into RX path. (Used for IOBIST.)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_INJECT_ERROR_TYPE_SHIFT                        _MK_SHIFT_CONST(19)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_INJECT_ERROR_TYPE_FIELD                        (_MK_MASK_CONST(0x3) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_INJECT_ERROR_TYPE_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_INJECT_ERROR_TYPE_RANGE                        20:19
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_INJECT_ERROR_TYPE_WOFFSET                      0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_INJECT_ERROR_TYPE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_INJECT_ERROR_TYPE_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_INJECT_ERROR_TYPE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_INJECT_ERROR_TYPE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_INJECT_ERROR_TYPE_DISABLE                      _MK_ENUM_CONST(0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_INJECT_ERROR_TYPE_BIT_ERR                      _MK_ENUM_CONST(1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_INJECT_ERROR_TYPE_RX_ERR                       _MK_ENUM_CONST(2)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_INJECT_ERROR_TYPE_BIT_RX_ERR                   _MK_ENUM_CONST(3)
+
+// Don't block changes for 4ms when going from LS to FS (should not happen)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_LS_TO_FS_SKIP_4MS_SHIFT                        _MK_SHIFT_CONST(21)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_LS_TO_FS_SKIP_4MS_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_LS_TO_FS_SKIP_4MS_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_LS_TO_FS_SKIP_4MS_RANGE                        21:21
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_LS_TO_FS_SKIP_4MS_WOFFSET                      0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_LS_TO_FS_SKIP_4MS_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_LS_TO_FS_SKIP_4MS_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_LS_TO_FS_SKIP_4MS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_LS_TO_FS_SKIP_4MS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Suspend exit requires edge or simply a value...
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_SUSPEND_EXIT_ON_EDGE_SHIFT                     _MK_SHIFT_CONST(22)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_SUSPEND_EXIT_ON_EDGE_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_SUSPEND_EXIT_ON_EDGE_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_SUSPEND_EXIT_ON_EDGE_RANGE                     22:22
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_SUSPEND_EXIT_ON_EDGE_WOFFSET                   0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_SUSPEND_EXIT_ON_EDGE_DEFAULT                   _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_SUSPEND_EXIT_ON_EDGE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_SUSPEND_EXIT_ON_EDGE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_SUSPEND_EXIT_ON_EDGE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_FS_DISABLE_ON_DEV_CHIRP_SHIFT                    _MK_SHIFT_CONST(23)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_FS_DISABLE_ON_DEV_CHIRP_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_FS_DISABLE_ON_DEV_CHIRP_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_FS_DISABLE_ON_DEV_CHIRP_RANGE                    23:23
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_FS_DISABLE_ON_DEV_CHIRP_WOFFSET                  0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_FS_DISABLE_ON_DEV_CHIRP_DEFAULT                  _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_FS_DISABLE_ON_DEV_CHIRP_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_FS_DISABLE_ON_DEV_CHIRP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_FS_DISABLE_ON_DEV_CHIRP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_ALLOW_LS_ON_SOFT_DISCON_SHIFT                  _MK_SHIFT_CONST(24)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_ALLOW_LS_ON_SOFT_DISCON_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_ALLOW_LS_ON_SOFT_DISCON_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_ALLOW_LS_ON_SOFT_DISCON_RANGE                  24:24
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_ALLOW_LS_ON_SOFT_DISCON_WOFFSET                        0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_ALLOW_LS_ON_SOFT_DISCON_DEFAULT                        _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_ALLOW_LS_ON_SOFT_DISCON_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_ALLOW_LS_ON_SOFT_DISCON_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_ALLOW_LS_ON_SOFT_DISCON_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_KEEP_XCVR_PD_ON_SOFT_DISCON_SHIFT                      _MK_SHIFT_CONST(25)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_KEEP_XCVR_PD_ON_SOFT_DISCON_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_KEEP_XCVR_PD_ON_SOFT_DISCON_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_KEEP_XCVR_PD_ON_SOFT_DISCON_RANGE                      25:25
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_KEEP_XCVR_PD_ON_SOFT_DISCON_WOFFSET                    0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_KEEP_XCVR_PD_ON_SOFT_DISCON_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_KEEP_XCVR_PD_ON_SOFT_DISCON_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_KEEP_XCVR_PD_ON_SOFT_DISCON_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_KEEP_XCVR_PD_ON_SOFT_DISCON_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Use DP/DM as obs bus
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_SHIFT                     _MK_SHIFT_CONST(26)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_RANGE                     26:26
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_WOFFSET                   0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Select DP/DM obs signals
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_SEL_SHIFT                 _MK_SHIFT_CONST(27)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_SEL_FIELD                 (_MK_MASK_CONST(0xf) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_SEL_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_SEL_RANGE                 30:27
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_SEL_WOFFSET                       0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_SEL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_SEL_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_SEL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_SEL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_UTMIP_MISC_CFG1_0  // UTMIP miscellaneous configurations
+#define APB_MISC_UTMIP_MISC_CFG1_0                      _MK_ADDR_CONST(0xa28)
+#define APB_MISC_UTMIP_MISC_CFG1_0_SECURE                       0x0
+#define APB_MISC_UTMIP_MISC_CFG1_0_WORD_COUNT                   0x1
+#define APB_MISC_UTMIP_MISC_CFG1_0_RESET_VAL                    _MK_MASK_CONST(0x40198024)
+#define APB_MISC_UTMIP_MISC_CFG1_0_RESET_MASK                   _MK_MASK_CONST(0x7fffffff)
+#define APB_MISC_UTMIP_MISC_CFG1_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_READ_MASK                    _MK_MASK_CONST(0x7fffffff)
+#define APB_MISC_UTMIP_MISC_CFG1_0_WRITE_MASK                   _MK_MASK_CONST(0x7fffffff)
+// Bit 0: 0: 0xa5 -> treat as KeepAlive 
+//        1: treat as regular packet 
+// Bit 1: 0: Turn on FS EOP detection
+//        1: Turn off FS EOP detection
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_XCVRSEL3_SHIFT                 _MK_SHIFT_CONST(0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_XCVRSEL3_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_XCVRSEL3_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_XCVRSEL3_RANGE                 1:0
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_XCVRSEL3_WOFFSET                       0x0
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_XCVRSEL3_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_XCVRSEL3_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_XCVRSEL3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_XCVRSEL3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_SUSPEND_TERMSEL_SHIFT                  _MK_SHIFT_CONST(2)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_SUSPEND_TERMSEL_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_SUSPEND_TERMSEL_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_SUSPEND_TERMSEL_RANGE                  2:2
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_SUSPEND_TERMSEL_WOFFSET                        0x0
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_SUSPEND_TERMSEL_DEFAULT                        _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_SUSPEND_TERMSEL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_SUSPEND_TERMSEL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_SUSPEND_TERMSEL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FLIP_FSLS_POLARITY_SHIFT                       _MK_SHIFT_CONST(3)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FLIP_FSLS_POLARITY_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FLIP_FSLS_POLARITY_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FLIP_FSLS_POLARITY_RANGE                       3:3
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FLIP_FSLS_POLARITY_WOFFSET                     0x0
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FLIP_FSLS_POLARITY_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FLIP_FSLS_POLARITY_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FLIP_FSLS_POLARITY_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FLIP_FSLS_POLARITY_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_EN_SHIFT                  _MK_SHIFT_CONST(4)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_EN_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_EN_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_EN_RANGE                  4:4
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_EN_WOFFSET                        0x0
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_EN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_CLR_SHIFT                 _MK_SHIFT_CONST(5)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_CLR_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_CLR_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_CLR_RANGE                 5:5
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_CLR_WOFFSET                       0x0
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_CLR_DEFAULT                       _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_CLR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_CLR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_CLR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// WRONG! This should be 1ms -> 0x50
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PLLU_STABLE_COUNT_SHIFT                        _MK_SHIFT_CONST(6)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PLLU_STABLE_COUNT_FIELD                        (_MK_MASK_CONST(0xfff) << APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PLLU_STABLE_COUNT_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PLLU_STABLE_COUNT_RANGE                        17:6
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PLLU_STABLE_COUNT_WOFFSET                      0x0
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PLLU_STABLE_COUNT_DEFAULT                      _MK_MASK_CONST(0x600)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PLLU_STABLE_COUNT_DEFAULT_MASK                 _MK_MASK_CONST(0xfff)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PLLU_STABLE_COUNT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PLLU_STABLE_COUNT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// 5 us / (1/19.2MHz) = 96 / 16 = 6
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT                     _MK_SHIFT_CONST(18)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PLL_ACTIVE_DLY_COUNT_FIELD                     (_MK_MASK_CONST(0x1f) << APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PLL_ACTIVE_DLY_COUNT_RANGE                     22:18
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PLL_ACTIVE_DLY_COUNT_WOFFSET                   0x0
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PLL_ACTIVE_DLY_COUNT_DEFAULT                   _MK_MASK_CONST(0x6)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PLL_ACTIVE_DLY_COUNT_DEFAULT_MASK                      _MK_MASK_CONST(0x1f)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PLL_ACTIVE_DLY_COUNT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PLL_ACTIVE_DLY_COUNT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FORCE_IOBIST_CLK_ON_SHIFT                      _MK_SHIFT_CONST(23)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FORCE_IOBIST_CLK_ON_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FORCE_IOBIST_CLK_ON_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FORCE_IOBIST_CLK_ON_RANGE                      23:23
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FORCE_IOBIST_CLK_ON_WOFFSET                    0x0
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FORCE_IOBIST_CLK_ON_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FORCE_IOBIST_CLK_ON_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FORCE_IOBIST_CLK_ON_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FORCE_IOBIST_CLK_ON_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FSLS_TDM_SHIFT                 _MK_SHIFT_CONST(24)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FSLS_TDM_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FSLS_TDM_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FSLS_TDM_RANGE                 24:24
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FSLS_TDM_WOFFSET                       0x0
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FSLS_TDM_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FSLS_TDM_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FSLS_TDM_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FSLS_TDM_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_OBS_SEL_SHIFT                  _MK_SHIFT_CONST(25)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_OBS_SEL_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_OBS_SEL_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_OBS_SEL_RANGE                  26:25
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_OBS_SEL_WOFFSET                        0x0
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_OBS_SEL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_OBS_SEL_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_OBS_SEL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_OBS_SEL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// 0: Use FS filtering on line state when XcvrSel=3
+// 1: Use LS filtering on line state when XcvrSel=3
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_XCVRSEL3_SHIFT                       _MK_SHIFT_CONST(27)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_XCVRSEL3_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_XCVRSEL3_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_XCVRSEL3_RANGE                       27:27
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_XCVRSEL3_WOFFSET                     0x0
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_XCVRSEL3_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_XCVRSEL3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_XCVRSEL3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_XCVRSEL3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Use neg edge sync for linestate
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_NEG_SHIFT                    _MK_SHIFT_CONST(28)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_NEG_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_NEG_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_NEG_RANGE                    28:28
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_NEG_WOFFSET                  0x0
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_NEG_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_NEG_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_NEG_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_NEG_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Bypass LineState reclocking logic
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_BYPASS_SHIFT                 _MK_SHIFT_CONST(29)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_BYPASS_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_BYPASS_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_BYPASS_RANGE                 29:29
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_BYPASS_WOFFSET                       0x0
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_BYPASS_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_BYPASS_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_BYPASS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_BYPASS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Selects whether to enable the crystal clock in the module.
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PHY_XTAL_CLOCKEN_SHIFT                 _MK_SHIFT_CONST(30)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PHY_XTAL_CLOCKEN_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PHY_XTAL_CLOCKEN_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PHY_XTAL_CLOCKEN_RANGE                 30:30
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PHY_XTAL_CLOCKEN_WOFFSET                       0x0
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PHY_XTAL_CLOCKEN_DEFAULT                       _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PHY_XTAL_CLOCKEN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PHY_XTAL_CLOCKEN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PHY_XTAL_CLOCKEN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_UTMIP_DEBOUNCE_CFG0_0  // UTMIP Avalid and Bvalid debounce
+#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0                  _MK_ADDR_CONST(0xa2c)
+#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_SECURE                   0x0
+#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_WORD_COUNT                       0x1
+#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_RESET_VAL                        _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+// simulation value -- Used for interrupts
+#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_A_SHIFT                      _MK_SHIFT_CONST(0)
+#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_A_FIELD                      (_MK_MASK_CONST(0xffff) << APB_MISC_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_A_SHIFT)
+#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_A_RANGE                      15:0
+#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_A_WOFFSET                    0x0
+#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_A_DEFAULT                    _MK_MASK_CONST(0xffff)
+#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_A_DEFAULT_MASK                       _MK_MASK_CONST(0xffff)
+#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_A_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_A_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// simulation value -- Used for interrupts
+#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_B_SHIFT                      _MK_SHIFT_CONST(16)
+#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_B_FIELD                      (_MK_MASK_CONST(0xffff) << APB_MISC_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_B_SHIFT)
+#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_B_RANGE                      31:16
+#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_B_WOFFSET                    0x0
+#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_B_DEFAULT                    _MK_MASK_CONST(0xffff)
+#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_B_DEFAULT_MASK                       _MK_MASK_CONST(0xffff)
+#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_B_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_B_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_UTMIP_BAT_CHRG_CFG0_0  // UTMIP battery charger configuration
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0                  _MK_ADDR_CONST(0xa30)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_SECURE                   0x0
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_WORD_COUNT                       0x1
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_RESET_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_READ_MASK                        _MK_MASK_CONST(0x1f)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_WRITE_MASK                       _MK_MASK_CONST(0x1f)
+// Power down charger circuit
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_PD_CHRG_SHIFT                      _MK_SHIFT_CONST(0)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_PD_CHRG_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_PD_CHRG_SHIFT)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_PD_CHRG_RANGE                      0:0
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_PD_CHRG_WOFFSET                    0x0
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_PD_CHRG_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_PD_CHRG_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_PD_CHRG_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_PD_CHRG_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SINK_EN_SHIFT                   _MK_SHIFT_CONST(1)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SINK_EN_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SINK_EN_SHIFT)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SINK_EN_RANGE                   1:1
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SINK_EN_WOFFSET                 0x0
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SINK_EN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SINK_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SINK_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SINK_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SINK_EN_SHIFT                   _MK_SHIFT_CONST(2)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SINK_EN_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SINK_EN_SHIFT)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SINK_EN_RANGE                   2:2
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SINK_EN_WOFFSET                 0x0
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SINK_EN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SINK_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SINK_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SINK_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SRC_EN_SHIFT                    _MK_SHIFT_CONST(3)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SRC_EN_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SRC_EN_SHIFT)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SRC_EN_RANGE                    3:3
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SRC_EN_WOFFSET                  0x0
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SRC_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SRC_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SRC_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SRC_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SRC_EN_SHIFT                    _MK_SHIFT_CONST(4)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SRC_EN_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SRC_EN_SHIFT)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SRC_EN_RANGE                    4:4
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SRC_EN_WOFFSET                  0x0
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SRC_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SRC_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SRC_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SRC_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_UTMIP_SPARE_CFG0_0  // Utmip spare configuration bits 
+#define APB_MISC_UTMIP_SPARE_CFG0_0                     _MK_ADDR_CONST(0xa34)
+#define APB_MISC_UTMIP_SPARE_CFG0_0_SECURE                      0x0
+#define APB_MISC_UTMIP_SPARE_CFG0_0_WORD_COUNT                  0x1
+#define APB_MISC_UTMIP_SPARE_CFG0_0_RESET_VAL                   _MK_MASK_CONST(0xffff0000)
+#define APB_MISC_UTMIP_SPARE_CFG0_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_UTMIP_SPARE_CFG0_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_SPARE_CFG0_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_SPARE_CFG0_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_UTMIP_SPARE_CFG0_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+// Spare register bits
+// 0: HS_RX_IPG_ERROR_ENABLE
+// 1: HS_RX_FLUSH_ALAP. Flush as late as possible
+// 2: HS_RX_LATE_SQUELCH. Delay Squelch by 1 CLK480 cycle.
+// 3: FUSE_SETUP_SEL. Select between regular CFG value and JTAG values for UX_SETUP
+// 31 to 4: Reserved
+#define APB_MISC_UTMIP_SPARE_CFG0_0_UTMIP_SPARE_SHIFT                   _MK_SHIFT_CONST(0)
+#define APB_MISC_UTMIP_SPARE_CFG0_0_UTMIP_SPARE_FIELD                   (_MK_MASK_CONST(0xffffffff) << APB_MISC_UTMIP_SPARE_CFG0_0_UTMIP_SPARE_SHIFT)
+#define APB_MISC_UTMIP_SPARE_CFG0_0_UTMIP_SPARE_RANGE                   31:0
+#define APB_MISC_UTMIP_SPARE_CFG0_0_UTMIP_SPARE_WOFFSET                 0x0
+#define APB_MISC_UTMIP_SPARE_CFG0_0_UTMIP_SPARE_DEFAULT                 _MK_MASK_CONST(0xffff0000)
+#define APB_MISC_UTMIP_SPARE_CFG0_0_UTMIP_SPARE_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_UTMIP_SPARE_CFG0_0_UTMIP_SPARE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_SPARE_CFG0_0_UTMIP_SPARE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_SPARE_CFG0_0_UTMIP_SPARE_INIT_ENUM                       -65536
+
+
+// Register APB_MISC_UTMIP_XCVR_CFG1_0  // UTMIP transceiver cell configuration register 1
+#define APB_MISC_UTMIP_XCVR_CFG1_0                      _MK_ADDR_CONST(0xa38)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_SECURE                       0x0
+#define APB_MISC_UTMIP_XCVR_CFG1_0_WORD_COUNT                   0x1
+#define APB_MISC_UTMIP_XCVR_CFG1_0_RESET_VAL                    _MK_MASK_CONST(0x822a)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_RESET_MASK                   _MK_MASK_CONST(0xffffff)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_READ_MASK                    _MK_MASK_CONST(0xffffff)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_WRITE_MASK                   _MK_MASK_CONST(0xffffff)
+// Force PDDISC input into power down. (Overrides FORCE_PDDISC_POWERUP.)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDISC_POWERDOWN_SHIFT                   _MK_SHIFT_CONST(0)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDISC_POWERDOWN_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDISC_POWERDOWN_SHIFT)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDISC_POWERDOWN_RANGE                   0:0
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDISC_POWERDOWN_WOFFSET                 0x0
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDISC_POWERDOWN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDISC_POWERDOWN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDISC_POWERDOWN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDISC_POWERDOWN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Force PDDISC input into power up.
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDISC_POWERUP_SHIFT                     _MK_SHIFT_CONST(1)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDISC_POWERUP_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDISC_POWERUP_SHIFT)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDISC_POWERUP_RANGE                     1:1
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDISC_POWERUP_WOFFSET                   0x0
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDISC_POWERUP_DEFAULT                   _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDISC_POWERUP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDISC_POWERUP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDISC_POWERUP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Force PDCHRP input input into power down. (Overrides FORCE_PDCHRP_POWERUP.)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDCHRP_POWERDOWN_SHIFT                   _MK_SHIFT_CONST(2)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDCHRP_POWERDOWN_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDCHRP_POWERDOWN_SHIFT)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDCHRP_POWERDOWN_RANGE                   2:2
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDCHRP_POWERDOWN_WOFFSET                 0x0
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDCHRP_POWERDOWN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDCHRP_POWERDOWN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDCHRP_POWERDOWN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDCHRP_POWERDOWN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Force PDCHRP input into power up.
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDCHRP_POWERUP_SHIFT                     _MK_SHIFT_CONST(3)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDCHRP_POWERUP_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDCHRP_POWERUP_SHIFT)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDCHRP_POWERUP_RANGE                     3:3
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDCHRP_POWERUP_WOFFSET                   0x0
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDCHRP_POWERUP_DEFAULT                   _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDCHRP_POWERUP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDCHRP_POWERUP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDCHRP_POWERUP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Force PDDR input input into power down. (Overrides FORCE_PDDR_POWERUP.)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDR_POWERDOWN_SHIFT                     _MK_SHIFT_CONST(4)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDR_POWERDOWN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDR_POWERDOWN_SHIFT)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDR_POWERDOWN_RANGE                     4:4
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDR_POWERDOWN_WOFFSET                   0x0
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDR_POWERDOWN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDR_POWERDOWN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDR_POWERDOWN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDR_POWERDOWN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Force PDDR input into power up.
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDR_POWERUP_SHIFT                       _MK_SHIFT_CONST(5)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDR_POWERUP_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDR_POWERUP_SHIFT)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDR_POWERUP_RANGE                       5:5
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDR_POWERUP_WOFFSET                     0x0
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDR_POWERUP_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDR_POWERUP_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDR_POWERUP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDR_POWERUP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Encoded value to use on TCTRL when software override is enabled, 0 to 16 only
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_TCTRL_SW_VAL_SHIFT                     _MK_SHIFT_CONST(6)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_TCTRL_SW_VAL_FIELD                     (_MK_MASK_CONST(0x1f) << APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_TCTRL_SW_VAL_SHIFT)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_TCTRL_SW_VAL_RANGE                     10:6
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_TCTRL_SW_VAL_WOFFSET                   0x0
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_TCTRL_SW_VAL_DEFAULT                   _MK_MASK_CONST(0x8)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_TCTRL_SW_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1f)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_TCTRL_SW_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_TCTRL_SW_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Use a software override on TCTRL instead of automatic bias control
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_TCTRL_SW_SET_SHIFT                     _MK_SHIFT_CONST(11)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_TCTRL_SW_SET_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_TCTRL_SW_SET_SHIFT)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_TCTRL_SW_SET_RANGE                     11:11
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_TCTRL_SW_SET_WOFFSET                   0x0
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_TCTRL_SW_SET_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_TCTRL_SW_SET_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_TCTRL_SW_SET_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_TCTRL_SW_SET_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Encoded value to use on RCTRL when software override is enabled, 0 to 16 only
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_RCTRL_SW_VAL_SHIFT                     _MK_SHIFT_CONST(12)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_RCTRL_SW_VAL_FIELD                     (_MK_MASK_CONST(0x1f) << APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_RCTRL_SW_VAL_SHIFT)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_RCTRL_SW_VAL_RANGE                     16:12
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_RCTRL_SW_VAL_WOFFSET                   0x0
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_RCTRL_SW_VAL_DEFAULT                   _MK_MASK_CONST(0x8)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_RCTRL_SW_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1f)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_RCTRL_SW_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_RCTRL_SW_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Use a software override on RCTRL instead of automatic bias control
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_RCTRL_SW_SET_SHIFT                     _MK_SHIFT_CONST(17)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_RCTRL_SW_SET_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_RCTRL_SW_SET_SHIFT)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_RCTRL_SW_SET_RANGE                     17:17
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_RCTRL_SW_SET_WOFFSET                   0x0
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_RCTRL_SW_SET_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_RCTRL_SW_SET_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_RCTRL_SW_SET_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_RCTRL_SW_SET_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Range adjusment on terminations.
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_XCVR_TERM_RANGE_ADJ_SHIFT                      _MK_SHIFT_CONST(18)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_XCVR_TERM_RANGE_ADJ_FIELD                      (_MK_MASK_CONST(0xf) << APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_XCVR_TERM_RANGE_ADJ_SHIFT)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_XCVR_TERM_RANGE_ADJ_RANGE                      21:18
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_XCVR_TERM_RANGE_ADJ_WOFFSET                    0x0
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_XCVR_TERM_RANGE_ADJ_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_XCVR_TERM_RANGE_ADJ_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_XCVR_TERM_RANGE_ADJ_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_XCVR_TERM_RANGE_ADJ_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Spare bits for usb transceiver pad ECO.
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_XCVR_SPARE_SHIFT                       _MK_SHIFT_CONST(22)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_XCVR_SPARE_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_XCVR_SPARE_SHIFT)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_XCVR_SPARE_RANGE                       23:22
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_XCVR_SPARE_WOFFSET                     0x0
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_XCVR_SPARE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_XCVR_SPARE_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_XCVR_SPARE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_XCVR_SPARE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_UTMIP_BIAS_CFG1_0  // UTMIP Bias cell configuration register 1
+#define APB_MISC_UTMIP_BIAS_CFG1_0                      _MK_ADDR_CONST(0xa3c)
+#define APB_MISC_UTMIP_BIAS_CFG1_0_SECURE                       0x0
+#define APB_MISC_UTMIP_BIAS_CFG1_0_WORD_COUNT                   0x1
+#define APB_MISC_UTMIP_BIAS_CFG1_0_RESET_VAL                    _MK_MASK_CONST(0x2a)
+#define APB_MISC_UTMIP_BIAS_CFG1_0_RESET_MASK                   _MK_MASK_CONST(0x3fff)
+#define APB_MISC_UTMIP_BIAS_CFG1_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG1_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG1_0_READ_MASK                    _MK_MASK_CONST(0x3fff)
+#define APB_MISC_UTMIP_BIAS_CFG1_0_WRITE_MASK                   _MK_MASK_CONST(0x3fff)
+// Force PDTRK input into power down. (Overrides FORCE_PDTRK_POWERUP.)
+#define APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_FORCE_PDTRK_POWERDOWN_SHIFT                    _MK_SHIFT_CONST(0)
+#define APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_FORCE_PDTRK_POWERDOWN_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_FORCE_PDTRK_POWERDOWN_SHIFT)
+#define APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_FORCE_PDTRK_POWERDOWN_RANGE                    0:0
+#define APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_FORCE_PDTRK_POWERDOWN_WOFFSET                  0x0
+#define APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_FORCE_PDTRK_POWERDOWN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_FORCE_PDTRK_POWERDOWN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_FORCE_PDTRK_POWERDOWN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_FORCE_PDTRK_POWERDOWN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Force PDTRK input into power up.
+#define APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_FORCE_PDTRK_POWERUP_SHIFT                      _MK_SHIFT_CONST(1)
+#define APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_FORCE_PDTRK_POWERUP_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_FORCE_PDTRK_POWERUP_SHIFT)
+#define APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_FORCE_PDTRK_POWERUP_RANGE                      1:1
+#define APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_FORCE_PDTRK_POWERUP_WOFFSET                    0x0
+#define APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_FORCE_PDTRK_POWERUP_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_FORCE_PDTRK_POWERUP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_FORCE_PDTRK_POWERUP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_FORCE_PDTRK_POWERUP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Force VBUS_WAKEUP input into power down.
+#define APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_VBUS_WAKEUP_POWERDOWN_SHIFT                    _MK_SHIFT_CONST(2)
+#define APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_VBUS_WAKEUP_POWERDOWN_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_VBUS_WAKEUP_POWERDOWN_SHIFT)
+#define APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_VBUS_WAKEUP_POWERDOWN_RANGE                    2:2
+#define APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_VBUS_WAKEUP_POWERDOWN_WOFFSET                  0x0
+#define APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_VBUS_WAKEUP_POWERDOWN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_VBUS_WAKEUP_POWERDOWN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_VBUS_WAKEUP_POWERDOWN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_VBUS_WAKEUP_POWERDOWN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Control the BIAS cell power down lag. The lag should be 20us. For a Xtal clock of 13MHz it should be set a 5. 
+#define APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_BIAS_PDTRK_COUNT_SHIFT                 _MK_SHIFT_CONST(3)
+#define APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_BIAS_PDTRK_COUNT_FIELD                 (_MK_MASK_CONST(0x1f) << APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_BIAS_PDTRK_COUNT_SHIFT)
+#define APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_BIAS_PDTRK_COUNT_RANGE                 7:3
+#define APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_BIAS_PDTRK_COUNT_WOFFSET                       0x0
+#define APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_BIAS_PDTRK_COUNT_DEFAULT                       _MK_MASK_CONST(0x5)
+#define APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_BIAS_PDTRK_COUNT_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_BIAS_PDTRK_COUNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_BIAS_PDTRK_COUNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Debouncer time scaling, factor-1 to slow down debouncing by. So 0 is 1, 1 is 2, etc.
+#define APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_BIAS_DEBOUNCE_TIMESCALE_SHIFT                  _MK_SHIFT_CONST(8)
+#define APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_BIAS_DEBOUNCE_TIMESCALE_FIELD                  (_MK_MASK_CONST(0x3f) << APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_BIAS_DEBOUNCE_TIMESCALE_SHIFT)
+#define APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_BIAS_DEBOUNCE_TIMESCALE_RANGE                  13:8
+#define APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_BIAS_DEBOUNCE_TIMESCALE_WOFFSET                        0x0
+#define APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_BIAS_DEBOUNCE_TIMESCALE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_BIAS_DEBOUNCE_TIMESCALE_DEFAULT_MASK                   _MK_MASK_CONST(0x3f)
+#define APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_BIAS_DEBOUNCE_TIMESCALE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_BIAS_DEBOUNCE_TIMESCALE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_UTMIP_BIAS_STS0_0  // UTMIP Bias cell status register 0
+#define APB_MISC_UTMIP_BIAS_STS0_0                      _MK_ADDR_CONST(0xa40)
+#define APB_MISC_UTMIP_BIAS_STS0_0_SECURE                       0x0
+#define APB_MISC_UTMIP_BIAS_STS0_0_WORD_COUNT                   0x1
+#define APB_MISC_UTMIP_BIAS_STS0_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_STS0_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_UTMIP_BIAS_STS0_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_STS0_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_STS0_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_UTMIP_BIAS_STS0_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
+// Thermal encoding output from USB bias pad. 
+#define APB_MISC_UTMIP_BIAS_STS0_0_UTMIP_RCTRL_SHIFT                    _MK_SHIFT_CONST(0)
+#define APB_MISC_UTMIP_BIAS_STS0_0_UTMIP_RCTRL_FIELD                    (_MK_MASK_CONST(0xffff) << APB_MISC_UTMIP_BIAS_STS0_0_UTMIP_RCTRL_SHIFT)
+#define APB_MISC_UTMIP_BIAS_STS0_0_UTMIP_RCTRL_RANGE                    15:0
+#define APB_MISC_UTMIP_BIAS_STS0_0_UTMIP_RCTRL_WOFFSET                  0x0
+#define APB_MISC_UTMIP_BIAS_STS0_0_UTMIP_RCTRL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_STS0_0_UTMIP_RCTRL_DEFAULT_MASK                     _MK_MASK_CONST(0xffff)
+#define APB_MISC_UTMIP_BIAS_STS0_0_UTMIP_RCTRL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_STS0_0_UTMIP_RCTRL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Thermal encoding output from USB bias pad. 
+#define APB_MISC_UTMIP_BIAS_STS0_0_UTMIP_TCTRL_SHIFT                    _MK_SHIFT_CONST(16)
+#define APB_MISC_UTMIP_BIAS_STS0_0_UTMIP_TCTRL_FIELD                    (_MK_MASK_CONST(0xffff) << APB_MISC_UTMIP_BIAS_STS0_0_UTMIP_TCTRL_SHIFT)
+#define APB_MISC_UTMIP_BIAS_STS0_0_UTMIP_TCTRL_RANGE                    31:16
+#define APB_MISC_UTMIP_BIAS_STS0_0_UTMIP_TCTRL_WOFFSET                  0x0
+#define APB_MISC_UTMIP_BIAS_STS0_0_UTMIP_TCTRL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_STS0_0_UTMIP_TCTRL_DEFAULT_MASK                     _MK_MASK_CONST(0xffff)
+#define APB_MISC_UTMIP_BIAS_STS0_0_UTMIP_TCTRL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_STS0_0_UTMIP_TCTRL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_DAS_DAP_CTRL_SEL_0  
+#define APB_MISC_DAS_DAP_CTRL_SEL_0                     _MK_ADDR_CONST(0xc00)
+#define APB_MISC_DAS_DAP_CTRL_SEL_0_SECURE                      0x0
+#define APB_MISC_DAS_DAP_CTRL_SEL_0_WORD_COUNT                  0x1
+#define APB_MISC_DAS_DAP_CTRL_SEL_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_0_RESET_MASK                  _MK_MASK_CONST(0xe000001f)
+#define APB_MISC_DAS_DAP_CTRL_SEL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_0_READ_MASK                   _MK_MASK_CONST(0xe000001f)
+#define APB_MISC_DAS_DAP_CTRL_SEL_0_WRITE_MASK                  _MK_MASK_CONST(0xe000001f)
+//This bit is programmed to put particular DAP is either in master or slave mode when two or more DAPs are in by-pass mode.
+#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_MS_SEL_SHIFT                    _MK_SHIFT_CONST(31)
+#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_MS_SEL_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_MS_SEL_SHIFT)
+#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_MS_SEL_RANGE                    31:31
+#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_MS_SEL_WOFFSET                  0x0
+#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_MS_SEL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_MS_SEL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_MS_SEL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_MS_SEL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_MS_SEL_SLAVE                    _MK_ENUM_CONST(0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_MS_SEL_MASTER                   _MK_ENUM_CONST(1)
+
+//To program sdata1 in either tx or rx mode when two or more DAPs are in by-pass mode
+#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_SDATA1_TX_RX_SHIFT                      _MK_SHIFT_CONST(30)
+#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_SDATA1_TX_RX_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_SDATA1_TX_RX_SHIFT)
+#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_SDATA1_TX_RX_RANGE                      30:30
+#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_SDATA1_TX_RX_WOFFSET                    0x0
+#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_SDATA1_TX_RX_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_SDATA1_TX_RX_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_SDATA1_TX_RX_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_SDATA1_TX_RX_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_SDATA1_TX_RX_TX                 _MK_ENUM_CONST(0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_SDATA1_TX_RX_RX                 _MK_ENUM_CONST(1)
+
+//To program sdata2 in either tx or rx mode when two or more DAPs are in by-pass mode
+#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_SDATA2_RX_TX_SHIFT                      _MK_SHIFT_CONST(29)
+#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_SDATA2_RX_TX_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_SDATA2_RX_TX_SHIFT)
+#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_SDATA2_RX_TX_RANGE                      29:29
+#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_SDATA2_RX_TX_WOFFSET                    0x0
+#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_SDATA2_RX_TX_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_SDATA2_RX_TX_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_SDATA2_RX_TX_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_SDATA2_RX_TX_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_SDATA2_RX_TX_RX                 _MK_ENUM_CONST(0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_SDATA2_RX_TX_TX                 _MK_ENUM_CONST(1)
+
+//DAP selection bits to select one of the three DACs or one of the five DAPs
+#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_CTRL_SEL_SHIFT                  _MK_SHIFT_CONST(0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_CTRL_SEL_FIELD                  (_MK_MASK_CONST(0x1f) << APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_CTRL_SEL_SHIFT)
+#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_CTRL_SEL_RANGE                  4:0
+#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_CTRL_SEL_WOFFSET                        0x0
+#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_CTRL_SEL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_CTRL_SEL_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_CTRL_SEL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_CTRL_SEL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_CTRL_SEL_DAC1                   _MK_ENUM_CONST(0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_CTRL_SEL_DAC2                   _MK_ENUM_CONST(1)
+#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_CTRL_SEL_DAC3                   _MK_ENUM_CONST(2)
+#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_CTRL_SEL_DAP1                   _MK_ENUM_CONST(16)
+#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_CTRL_SEL_DAP2                   _MK_ENUM_CONST(17)
+#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_CTRL_SEL_DAP3                   _MK_ENUM_CONST(18)
+#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_CTRL_SEL_DAP4                   _MK_ENUM_CONST(19)
+#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_CTRL_SEL_DAP5                   _MK_ENUM_CONST(20)
+
+
+// Register APB_MISC_DAS_DAP_CTRL_SEL  
+#define APB_MISC_DAS_DAP_CTRL_SEL                       _MK_ADDR_CONST(0xc00)
+#define APB_MISC_DAS_DAP_CTRL_SEL_SECURE                        0x0
+#define APB_MISC_DAS_DAP_CTRL_SEL_WORD_COUNT                    0x1
+#define APB_MISC_DAS_DAP_CTRL_SEL_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_RESET_MASK                    _MK_MASK_CONST(0xe000001f)
+#define APB_MISC_DAS_DAP_CTRL_SEL_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_READ_MASK                     _MK_MASK_CONST(0xe000001f)
+#define APB_MISC_DAS_DAP_CTRL_SEL_WRITE_MASK                    _MK_MASK_CONST(0xe000001f)
+//This bit is programmed to put particular DAP is either in master or slave mode when two or more DAPs are in by-pass mode.
+#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_MS_SEL_SHIFT                      _MK_SHIFT_CONST(31)
+#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_MS_SEL_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_DAS_DAP_CTRL_SEL_DAP_MS_SEL_SHIFT)
+#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_MS_SEL_RANGE                      31:31
+#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_MS_SEL_WOFFSET                    0x0
+#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_MS_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_MS_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_MS_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_MS_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_MS_SEL_SLAVE                      _MK_ENUM_CONST(0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_MS_SEL_MASTER                     _MK_ENUM_CONST(1)
+
+//To program sdata1 in either tx or rx mode when two or more DAPs are in by-pass mode
+#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_SDATA1_TX_RX_SHIFT                        _MK_SHIFT_CONST(30)
+#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_SDATA1_TX_RX_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_DAS_DAP_CTRL_SEL_DAP_SDATA1_TX_RX_SHIFT)
+#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_SDATA1_TX_RX_RANGE                        30:30
+#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_SDATA1_TX_RX_WOFFSET                      0x0
+#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_SDATA1_TX_RX_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_SDATA1_TX_RX_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_SDATA1_TX_RX_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_SDATA1_TX_RX_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_SDATA1_TX_RX_TX                   _MK_ENUM_CONST(0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_SDATA1_TX_RX_RX                   _MK_ENUM_CONST(1)
+
+//To program sdata2 in either tx or rx mode when two or more DAPs are in by-pass mode
+#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_SDATA2_RX_TX_SHIFT                        _MK_SHIFT_CONST(29)
+#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_SDATA2_RX_TX_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_DAS_DAP_CTRL_SEL_DAP_SDATA2_RX_TX_SHIFT)
+#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_SDATA2_RX_TX_RANGE                        29:29
+#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_SDATA2_RX_TX_WOFFSET                      0x0
+#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_SDATA2_RX_TX_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_SDATA2_RX_TX_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_SDATA2_RX_TX_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_SDATA2_RX_TX_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_SDATA2_RX_TX_RX                   _MK_ENUM_CONST(0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_SDATA2_RX_TX_TX                   _MK_ENUM_CONST(1)
+
+//DAP selection bits to select one of the three DACs or one of the five DAPs
+#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL_SHIFT                    _MK_SHIFT_CONST(0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL_SHIFT)
+#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL_RANGE                    4:0
+#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL_WOFFSET                  0x0
+#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL_DAC1                     _MK_ENUM_CONST(0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL_DAC2                     _MK_ENUM_CONST(1)
+#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL_DAC3                     _MK_ENUM_CONST(2)
+#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL_DAP1                     _MK_ENUM_CONST(16)
+#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL_DAP2                     _MK_ENUM_CONST(17)
+#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL_DAP3                     _MK_ENUM_CONST(18)
+#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL_DAP4                     _MK_ENUM_CONST(19)
+#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL_DAP5                     _MK_ENUM_CONST(20)
+
+
+// Register APB_MISC_DAS_DAP_CTRL_SEL_1  
+#define APB_MISC_DAS_DAP_CTRL_SEL_1                     _MK_ADDR_CONST(0xc04)
+#define APB_MISC_DAS_DAP_CTRL_SEL_1_SECURE                      0x0
+#define APB_MISC_DAS_DAP_CTRL_SEL_1_WORD_COUNT                  0x1
+#define APB_MISC_DAS_DAP_CTRL_SEL_1_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_1_RESET_MASK                  _MK_MASK_CONST(0xe000001f)
+#define APB_MISC_DAS_DAP_CTRL_SEL_1_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_1_READ_MASK                   _MK_MASK_CONST(0xe000001f)
+#define APB_MISC_DAS_DAP_CTRL_SEL_1_WRITE_MASK                  _MK_MASK_CONST(0xe000001f)
+//This bit is programmed to put particular DAP is either in master or slave mode when two or more DAPs are in by-pass mode.
+#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_MS_SEL_SHIFT                    _MK_SHIFT_CONST(31)
+#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_MS_SEL_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_MS_SEL_SHIFT)
+#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_MS_SEL_RANGE                    31:31
+#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_MS_SEL_WOFFSET                  0x0
+#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_MS_SEL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_MS_SEL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_MS_SEL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_MS_SEL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_MS_SEL_SLAVE                    _MK_ENUM_CONST(0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_MS_SEL_MASTER                   _MK_ENUM_CONST(1)
+
+//To program sdata1 in either tx or rx mode when two or more DAPs are in by-pass mode
+#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_SDATA1_TX_RX_SHIFT                      _MK_SHIFT_CONST(30)
+#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_SDATA1_TX_RX_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_SDATA1_TX_RX_SHIFT)
+#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_SDATA1_TX_RX_RANGE                      30:30
+#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_SDATA1_TX_RX_WOFFSET                    0x0
+#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_SDATA1_TX_RX_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_SDATA1_TX_RX_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_SDATA1_TX_RX_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_SDATA1_TX_RX_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_SDATA1_TX_RX_TX                 _MK_ENUM_CONST(0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_SDATA1_TX_RX_RX                 _MK_ENUM_CONST(1)
+
+//To program sdata2 in either tx or rx mode when two or more DAPs are in by-pass mode
+#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_SDATA2_RX_TX_SHIFT                      _MK_SHIFT_CONST(29)
+#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_SDATA2_RX_TX_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_SDATA2_RX_TX_SHIFT)
+#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_SDATA2_RX_TX_RANGE                      29:29
+#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_SDATA2_RX_TX_WOFFSET                    0x0
+#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_SDATA2_RX_TX_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_SDATA2_RX_TX_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_SDATA2_RX_TX_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_SDATA2_RX_TX_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_SDATA2_RX_TX_RX                 _MK_ENUM_CONST(0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_SDATA2_RX_TX_TX                 _MK_ENUM_CONST(1)
+
+//DAP selection bits to select one of the three DACs or one of the five DAPs
+#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_CTRL_SEL_SHIFT                  _MK_SHIFT_CONST(0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_CTRL_SEL_FIELD                  (_MK_MASK_CONST(0x1f) << APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_CTRL_SEL_SHIFT)
+#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_CTRL_SEL_RANGE                  4:0
+#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_CTRL_SEL_WOFFSET                        0x0
+#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_CTRL_SEL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_CTRL_SEL_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_CTRL_SEL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_CTRL_SEL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_CTRL_SEL_DAC1                   _MK_ENUM_CONST(0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_CTRL_SEL_DAC2                   _MK_ENUM_CONST(1)
+#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_CTRL_SEL_DAC3                   _MK_ENUM_CONST(2)
+#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_CTRL_SEL_DAP1                   _MK_ENUM_CONST(16)
+#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_CTRL_SEL_DAP2                   _MK_ENUM_CONST(17)
+#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_CTRL_SEL_DAP3                   _MK_ENUM_CONST(18)
+#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_CTRL_SEL_DAP4                   _MK_ENUM_CONST(19)
+#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_CTRL_SEL_DAP5                   _MK_ENUM_CONST(20)
+
+
+// Register APB_MISC_DAS_DAP_CTRL_SEL_2  
+#define APB_MISC_DAS_DAP_CTRL_SEL_2                     _MK_ADDR_CONST(0xc08)
+#define APB_MISC_DAS_DAP_CTRL_SEL_2_SECURE                      0x0
+#define APB_MISC_DAS_DAP_CTRL_SEL_2_WORD_COUNT                  0x1
+#define APB_MISC_DAS_DAP_CTRL_SEL_2_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_2_RESET_MASK                  _MK_MASK_CONST(0xe000001f)
+#define APB_MISC_DAS_DAP_CTRL_SEL_2_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_2_READ_MASK                   _MK_MASK_CONST(0xe000001f)
+#define APB_MISC_DAS_DAP_CTRL_SEL_2_WRITE_MASK                  _MK_MASK_CONST(0xe000001f)
+//This bit is programmed to put particular DAP is either in master or slave mode when two or more DAPs are in by-pass mode.
+#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_MS_SEL_SHIFT                    _MK_SHIFT_CONST(31)
+#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_MS_SEL_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_MS_SEL_SHIFT)
+#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_MS_SEL_RANGE                    31:31
+#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_MS_SEL_WOFFSET                  0x0
+#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_MS_SEL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_MS_SEL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_MS_SEL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_MS_SEL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_MS_SEL_SLAVE                    _MK_ENUM_CONST(0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_MS_SEL_MASTER                   _MK_ENUM_CONST(1)
+
+//To program sdata1 in either tx or rx mode when two or more DAPs are in by-pass mode
+#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_SDATA1_TX_RX_SHIFT                      _MK_SHIFT_CONST(30)
+#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_SDATA1_TX_RX_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_SDATA1_TX_RX_SHIFT)
+#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_SDATA1_TX_RX_RANGE                      30:30
+#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_SDATA1_TX_RX_WOFFSET                    0x0
+#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_SDATA1_TX_RX_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_SDATA1_TX_RX_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_SDATA1_TX_RX_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_SDATA1_TX_RX_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_SDATA1_TX_RX_TX                 _MK_ENUM_CONST(0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_SDATA1_TX_RX_RX                 _MK_ENUM_CONST(1)
+
+//To program sdata2 in either tx or rx mode when two or more DAPs are in by-pass mode
+#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_SDATA2_RX_TX_SHIFT                      _MK_SHIFT_CONST(29)
+#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_SDATA2_RX_TX_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_SDATA2_RX_TX_SHIFT)
+#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_SDATA2_RX_TX_RANGE                      29:29
+#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_SDATA2_RX_TX_WOFFSET                    0x0
+#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_SDATA2_RX_TX_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_SDATA2_RX_TX_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_SDATA2_RX_TX_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_SDATA2_RX_TX_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_SDATA2_RX_TX_RX                 _MK_ENUM_CONST(0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_SDATA2_RX_TX_TX                 _MK_ENUM_CONST(1)
+
+//DAP selection bits to select one of the three DACs or one of the five DAPs
+#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_CTRL_SEL_SHIFT                  _MK_SHIFT_CONST(0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_CTRL_SEL_FIELD                  (_MK_MASK_CONST(0x1f) << APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_CTRL_SEL_SHIFT)
+#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_CTRL_SEL_RANGE                  4:0
+#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_CTRL_SEL_WOFFSET                        0x0
+#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_CTRL_SEL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_CTRL_SEL_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_CTRL_SEL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_CTRL_SEL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_CTRL_SEL_DAC1                   _MK_ENUM_CONST(0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_CTRL_SEL_DAC2                   _MK_ENUM_CONST(1)
+#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_CTRL_SEL_DAC3                   _MK_ENUM_CONST(2)
+#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_CTRL_SEL_DAP1                   _MK_ENUM_CONST(16)
+#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_CTRL_SEL_DAP2                   _MK_ENUM_CONST(17)
+#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_CTRL_SEL_DAP3                   _MK_ENUM_CONST(18)
+#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_CTRL_SEL_DAP4                   _MK_ENUM_CONST(19)
+#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_CTRL_SEL_DAP5                   _MK_ENUM_CONST(20)
+
+
+// Register APB_MISC_DAS_DAP_CTRL_SEL_3  
+#define APB_MISC_DAS_DAP_CTRL_SEL_3                     _MK_ADDR_CONST(0xc0c)
+#define APB_MISC_DAS_DAP_CTRL_SEL_3_SECURE                      0x0
+#define APB_MISC_DAS_DAP_CTRL_SEL_3_WORD_COUNT                  0x1
+#define APB_MISC_DAS_DAP_CTRL_SEL_3_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_3_RESET_MASK                  _MK_MASK_CONST(0xe000001f)
+#define APB_MISC_DAS_DAP_CTRL_SEL_3_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_3_READ_MASK                   _MK_MASK_CONST(0xe000001f)
+#define APB_MISC_DAS_DAP_CTRL_SEL_3_WRITE_MASK                  _MK_MASK_CONST(0xe000001f)
+//This bit is programmed to put particular DAP is either in master or slave mode when two or more DAPs are in by-pass mode.
+#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_MS_SEL_SHIFT                    _MK_SHIFT_CONST(31)
+#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_MS_SEL_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_MS_SEL_SHIFT)
+#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_MS_SEL_RANGE                    31:31
+#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_MS_SEL_WOFFSET                  0x0
+#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_MS_SEL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_MS_SEL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_MS_SEL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_MS_SEL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_MS_SEL_SLAVE                    _MK_ENUM_CONST(0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_MS_SEL_MASTER                   _MK_ENUM_CONST(1)
+
+//To program sdata1 in either tx or rx mode when two or more DAPs are in by-pass mode
+#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_SDATA1_TX_RX_SHIFT                      _MK_SHIFT_CONST(30)
+#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_SDATA1_TX_RX_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_SDATA1_TX_RX_SHIFT)
+#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_SDATA1_TX_RX_RANGE                      30:30
+#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_SDATA1_TX_RX_WOFFSET                    0x0
+#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_SDATA1_TX_RX_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_SDATA1_TX_RX_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_SDATA1_TX_RX_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_SDATA1_TX_RX_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_SDATA1_TX_RX_TX                 _MK_ENUM_CONST(0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_SDATA1_TX_RX_RX                 _MK_ENUM_CONST(1)
+
+//To program sdata2 in either tx or rx mode when two or more DAPs are in by-pass mode
+#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_SDATA2_RX_TX_SHIFT                      _MK_SHIFT_CONST(29)
+#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_SDATA2_RX_TX_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_SDATA2_RX_TX_SHIFT)
+#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_SDATA2_RX_TX_RANGE                      29:29
+#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_SDATA2_RX_TX_WOFFSET                    0x0
+#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_SDATA2_RX_TX_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_SDATA2_RX_TX_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_SDATA2_RX_TX_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_SDATA2_RX_TX_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_SDATA2_RX_TX_RX                 _MK_ENUM_CONST(0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_SDATA2_RX_TX_TX                 _MK_ENUM_CONST(1)
+
+//DAP selection bits to select one of the three DACs or one of the five DAPs
+#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_CTRL_SEL_SHIFT                  _MK_SHIFT_CONST(0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_CTRL_SEL_FIELD                  (_MK_MASK_CONST(0x1f) << APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_CTRL_SEL_SHIFT)
+#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_CTRL_SEL_RANGE                  4:0
+#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_CTRL_SEL_WOFFSET                        0x0
+#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_CTRL_SEL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_CTRL_SEL_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_CTRL_SEL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_CTRL_SEL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_CTRL_SEL_DAC1                   _MK_ENUM_CONST(0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_CTRL_SEL_DAC2                   _MK_ENUM_CONST(1)
+#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_CTRL_SEL_DAC3                   _MK_ENUM_CONST(2)
+#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_CTRL_SEL_DAP1                   _MK_ENUM_CONST(16)
+#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_CTRL_SEL_DAP2                   _MK_ENUM_CONST(17)
+#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_CTRL_SEL_DAP3                   _MK_ENUM_CONST(18)
+#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_CTRL_SEL_DAP4                   _MK_ENUM_CONST(19)
+#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_CTRL_SEL_DAP5                   _MK_ENUM_CONST(20)
+
+
+// Register APB_MISC_DAS_DAP_CTRL_SEL_4  
+#define APB_MISC_DAS_DAP_CTRL_SEL_4                     _MK_ADDR_CONST(0xc10)
+#define APB_MISC_DAS_DAP_CTRL_SEL_4_SECURE                      0x0
+#define APB_MISC_DAS_DAP_CTRL_SEL_4_WORD_COUNT                  0x1
+#define APB_MISC_DAS_DAP_CTRL_SEL_4_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_4_RESET_MASK                  _MK_MASK_CONST(0xe000001f)
+#define APB_MISC_DAS_DAP_CTRL_SEL_4_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_4_READ_MASK                   _MK_MASK_CONST(0xe000001f)
+#define APB_MISC_DAS_DAP_CTRL_SEL_4_WRITE_MASK                  _MK_MASK_CONST(0xe000001f)
+//This bit is programmed to put particular DAP is either in master or slave mode when two or more DAPs are in by-pass mode.
+#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_MS_SEL_SHIFT                    _MK_SHIFT_CONST(31)
+#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_MS_SEL_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_MS_SEL_SHIFT)
+#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_MS_SEL_RANGE                    31:31
+#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_MS_SEL_WOFFSET                  0x0
+#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_MS_SEL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_MS_SEL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_MS_SEL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_MS_SEL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_MS_SEL_SLAVE                    _MK_ENUM_CONST(0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_MS_SEL_MASTER                   _MK_ENUM_CONST(1)
+
+//To program sdata1 in either tx or rx mode when two or more DAPs are in by-pass mode
+#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_SDATA1_TX_RX_SHIFT                      _MK_SHIFT_CONST(30)
+#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_SDATA1_TX_RX_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_SDATA1_TX_RX_SHIFT)
+#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_SDATA1_TX_RX_RANGE                      30:30
+#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_SDATA1_TX_RX_WOFFSET                    0x0
+#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_SDATA1_TX_RX_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_SDATA1_TX_RX_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_SDATA1_TX_RX_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_SDATA1_TX_RX_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_SDATA1_TX_RX_TX                 _MK_ENUM_CONST(0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_SDATA1_TX_RX_RX                 _MK_ENUM_CONST(1)
+
+//To program sdata2 in either tx or rx mode when two or more DAPs are in by-pass mode
+#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_SDATA2_RX_TX_SHIFT                      _MK_SHIFT_CONST(29)
+#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_SDATA2_RX_TX_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_SDATA2_RX_TX_SHIFT)
+#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_SDATA2_RX_TX_RANGE                      29:29
+#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_SDATA2_RX_TX_WOFFSET                    0x0
+#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_SDATA2_RX_TX_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_SDATA2_RX_TX_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_SDATA2_RX_TX_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_SDATA2_RX_TX_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_SDATA2_RX_TX_RX                 _MK_ENUM_CONST(0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_SDATA2_RX_TX_TX                 _MK_ENUM_CONST(1)
+
+//DAP selection bits to select one of the three DACs or one of the five DAPs
+#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_CTRL_SEL_SHIFT                  _MK_SHIFT_CONST(0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_CTRL_SEL_FIELD                  (_MK_MASK_CONST(0x1f) << APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_CTRL_SEL_SHIFT)
+#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_CTRL_SEL_RANGE                  4:0
+#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_CTRL_SEL_WOFFSET                        0x0
+#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_CTRL_SEL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_CTRL_SEL_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_CTRL_SEL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_CTRL_SEL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_CTRL_SEL_DAC1                   _MK_ENUM_CONST(0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_CTRL_SEL_DAC2                   _MK_ENUM_CONST(1)
+#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_CTRL_SEL_DAC3                   _MK_ENUM_CONST(2)
+#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_CTRL_SEL_DAP1                   _MK_ENUM_CONST(16)
+#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_CTRL_SEL_DAP2                   _MK_ENUM_CONST(17)
+#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_CTRL_SEL_DAP3                   _MK_ENUM_CONST(18)
+#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_CTRL_SEL_DAP4                   _MK_ENUM_CONST(19)
+#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_CTRL_SEL_DAP5                   _MK_ENUM_CONST(20)
+
+
+// Reserved address 3092 [0xc14] 
+
+// Reserved address 3096 [0xc18] 
+
+// Reserved address 3100 [0xc1c] 
+
+// Reserved address 3104 [0xc20] 
+
+// Reserved address 3108 [0xc24] 
+
+// Reserved address 3112 [0xc28] 
+
+// Reserved address 3116 [0xc2c] 
+
+// Reserved address 3120 [0xc30] 
+
+// Reserved address 3124 [0xc34] 
+
+// Reserved address 3128 [0xc38] 
+
+// Reserved address 3132 [0xc3c] 
+
+// Register APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0  
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0                   _MK_ADDR_CONST(0xc40)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_SECURE                    0x0
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_WORD_COUNT                        0x1
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_RESET_MASK                        _MK_MASK_CONST(0xff00000f)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_READ_MASK                         _MK_MASK_CONST(0xff00000f)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_WRITE_MASK                        _MK_MASK_CONST(0xff00000f)
+//These bits are to control the selection of sdata2 input for DACs. 
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_SDATA2_SEL_SHIFT                      _MK_SHIFT_CONST(28)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_SDATA2_SEL_FIELD                      (_MK_MASK_CONST(0xf) << APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_SDATA2_SEL_SHIFT)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_SDATA2_SEL_RANGE                      31:28
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_SDATA2_SEL_WOFFSET                    0x0
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_SDATA2_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_SDATA2_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_SDATA2_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_SDATA2_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_SDATA2_SEL_DAP1                       _MK_ENUM_CONST(0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_SDATA2_SEL_DAP2                       _MK_ENUM_CONST(1)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_SDATA2_SEL_DAP3                       _MK_ENUM_CONST(2)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_SDATA2_SEL_DAP4                       _MK_ENUM_CONST(3)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_SDATA2_SEL_DAP5                       _MK_ENUM_CONST(4)
+
+//These bits are to control the selection of sdata1 input for DACs.
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_SDATA1_SEL_SHIFT                      _MK_SHIFT_CONST(24)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_SDATA1_SEL_FIELD                      (_MK_MASK_CONST(0xf) << APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_SDATA1_SEL_SHIFT)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_SDATA1_SEL_RANGE                      27:24
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_SDATA1_SEL_WOFFSET                    0x0
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_SDATA1_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_SDATA1_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_SDATA1_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_SDATA1_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_SDATA1_SEL_DAP1                       _MK_ENUM_CONST(0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_SDATA1_SEL_DAP2                       _MK_ENUM_CONST(1)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_SDATA1_SEL_DAP3                       _MK_ENUM_CONST(2)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_SDATA1_SEL_DAP4                       _MK_ENUM_CONST(3)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_SDATA1_SEL_DAP5                       _MK_ENUM_CONST(4)
+
+//These bits are to control the selection of bit clock and fsync for DACs.
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_CLK_SEL_SHIFT                 _MK_SHIFT_CONST(0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_CLK_SEL_FIELD                 (_MK_MASK_CONST(0xf) << APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_CLK_SEL_SHIFT)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_CLK_SEL_RANGE                 3:0
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_CLK_SEL_WOFFSET                       0x0
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_CLK_SEL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_CLK_SEL_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_CLK_SEL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_CLK_SEL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_CLK_SEL_DAP1                  _MK_ENUM_CONST(0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_CLK_SEL_DAP2                  _MK_ENUM_CONST(1)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_CLK_SEL_DAP3                  _MK_ENUM_CONST(2)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_CLK_SEL_DAP4                  _MK_ENUM_CONST(3)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_CLK_SEL_DAP5                  _MK_ENUM_CONST(4)
+
+
+// Register APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL  
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL                     _MK_ADDR_CONST(0xc40)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_SECURE                      0x0
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_WORD_COUNT                  0x1
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_RESET_MASK                  _MK_MASK_CONST(0xff00000f)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_READ_MASK                   _MK_MASK_CONST(0xff00000f)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_WRITE_MASK                  _MK_MASK_CONST(0xff00000f)
+//These bits are to control the selection of sdata2 input for DACs. 
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA2_SEL_SHIFT                        _MK_SHIFT_CONST(28)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA2_SEL_FIELD                        (_MK_MASK_CONST(0xf) << APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA2_SEL_SHIFT)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA2_SEL_RANGE                        31:28
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA2_SEL_WOFFSET                      0x0
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA2_SEL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA2_SEL_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA2_SEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA2_SEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA2_SEL_DAP1                 _MK_ENUM_CONST(0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA2_SEL_DAP2                 _MK_ENUM_CONST(1)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA2_SEL_DAP3                 _MK_ENUM_CONST(2)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA2_SEL_DAP4                 _MK_ENUM_CONST(3)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA2_SEL_DAP5                 _MK_ENUM_CONST(4)
+
+//These bits are to control the selection of sdata1 input for DACs.
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA1_SEL_SHIFT                        _MK_SHIFT_CONST(24)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA1_SEL_FIELD                        (_MK_MASK_CONST(0xf) << APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA1_SEL_SHIFT)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA1_SEL_RANGE                        27:24
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA1_SEL_WOFFSET                      0x0
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA1_SEL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA1_SEL_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA1_SEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA1_SEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA1_SEL_DAP1                 _MK_ENUM_CONST(0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA1_SEL_DAP2                 _MK_ENUM_CONST(1)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA1_SEL_DAP3                 _MK_ENUM_CONST(2)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA1_SEL_DAP4                 _MK_ENUM_CONST(3)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA1_SEL_DAP5                 _MK_ENUM_CONST(4)
+
+//These bits are to control the selection of bit clock and fsync for DACs.
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_CLK_SEL_SHIFT                   _MK_SHIFT_CONST(0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_CLK_SEL_FIELD                   (_MK_MASK_CONST(0xf) << APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_CLK_SEL_SHIFT)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_CLK_SEL_RANGE                   3:0
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_CLK_SEL_WOFFSET                 0x0
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_CLK_SEL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_CLK_SEL_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_CLK_SEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_CLK_SEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_CLK_SEL_DAP1                    _MK_ENUM_CONST(0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_CLK_SEL_DAP2                    _MK_ENUM_CONST(1)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_CLK_SEL_DAP3                    _MK_ENUM_CONST(2)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_CLK_SEL_DAP4                    _MK_ENUM_CONST(3)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_CLK_SEL_DAP5                    _MK_ENUM_CONST(4)
+
+
+// Register APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1  
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1                   _MK_ADDR_CONST(0xc44)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_SECURE                    0x0
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_WORD_COUNT                        0x1
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_RESET_MASK                        _MK_MASK_CONST(0xff00000f)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_READ_MASK                         _MK_MASK_CONST(0xff00000f)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_WRITE_MASK                        _MK_MASK_CONST(0xff00000f)
+//These bits are to control the selection of sdata2 input for DACs. 
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_SDATA2_SEL_SHIFT                      _MK_SHIFT_CONST(28)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_SDATA2_SEL_FIELD                      (_MK_MASK_CONST(0xf) << APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_SDATA2_SEL_SHIFT)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_SDATA2_SEL_RANGE                      31:28
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_SDATA2_SEL_WOFFSET                    0x0
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_SDATA2_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_SDATA2_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_SDATA2_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_SDATA2_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_SDATA2_SEL_DAP1                       _MK_ENUM_CONST(0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_SDATA2_SEL_DAP2                       _MK_ENUM_CONST(1)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_SDATA2_SEL_DAP3                       _MK_ENUM_CONST(2)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_SDATA2_SEL_DAP4                       _MK_ENUM_CONST(3)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_SDATA2_SEL_DAP5                       _MK_ENUM_CONST(4)
+
+//These bits are to control the selection of sdata1 input for DACs.
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_SDATA1_SEL_SHIFT                      _MK_SHIFT_CONST(24)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_SDATA1_SEL_FIELD                      (_MK_MASK_CONST(0xf) << APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_SDATA1_SEL_SHIFT)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_SDATA1_SEL_RANGE                      27:24
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_SDATA1_SEL_WOFFSET                    0x0
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_SDATA1_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_SDATA1_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_SDATA1_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_SDATA1_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_SDATA1_SEL_DAP1                       _MK_ENUM_CONST(0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_SDATA1_SEL_DAP2                       _MK_ENUM_CONST(1)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_SDATA1_SEL_DAP3                       _MK_ENUM_CONST(2)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_SDATA1_SEL_DAP4                       _MK_ENUM_CONST(3)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_SDATA1_SEL_DAP5                       _MK_ENUM_CONST(4)
+
+//These bits are to control the selection of bit clock and fsync for DACs.
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_CLK_SEL_SHIFT                 _MK_SHIFT_CONST(0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_CLK_SEL_FIELD                 (_MK_MASK_CONST(0xf) << APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_CLK_SEL_SHIFT)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_CLK_SEL_RANGE                 3:0
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_CLK_SEL_WOFFSET                       0x0
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_CLK_SEL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_CLK_SEL_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_CLK_SEL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_CLK_SEL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_CLK_SEL_DAP1                  _MK_ENUM_CONST(0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_CLK_SEL_DAP2                  _MK_ENUM_CONST(1)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_CLK_SEL_DAP3                  _MK_ENUM_CONST(2)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_CLK_SEL_DAP4                  _MK_ENUM_CONST(3)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_CLK_SEL_DAP5                  _MK_ENUM_CONST(4)
+
+
+// Register APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2  
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2                   _MK_ADDR_CONST(0xc48)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_SECURE                    0x0
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_WORD_COUNT                        0x1
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_RESET_MASK                        _MK_MASK_CONST(0xff00000f)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_READ_MASK                         _MK_MASK_CONST(0xff00000f)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_WRITE_MASK                        _MK_MASK_CONST(0xff00000f)
+//These bits are to control the selection of sdata2 input for DACs. 
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_SDATA2_SEL_SHIFT                      _MK_SHIFT_CONST(28)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_SDATA2_SEL_FIELD                      (_MK_MASK_CONST(0xf) << APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_SDATA2_SEL_SHIFT)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_SDATA2_SEL_RANGE                      31:28
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_SDATA2_SEL_WOFFSET                    0x0
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_SDATA2_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_SDATA2_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_SDATA2_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_SDATA2_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_SDATA2_SEL_DAP1                       _MK_ENUM_CONST(0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_SDATA2_SEL_DAP2                       _MK_ENUM_CONST(1)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_SDATA2_SEL_DAP3                       _MK_ENUM_CONST(2)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_SDATA2_SEL_DAP4                       _MK_ENUM_CONST(3)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_SDATA2_SEL_DAP5                       _MK_ENUM_CONST(4)
+
+//These bits are to control the selection of sdata1 input for DACs.
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_SDATA1_SEL_SHIFT                      _MK_SHIFT_CONST(24)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_SDATA1_SEL_FIELD                      (_MK_MASK_CONST(0xf) << APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_SDATA1_SEL_SHIFT)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_SDATA1_SEL_RANGE                      27:24
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_SDATA1_SEL_WOFFSET                    0x0
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_SDATA1_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_SDATA1_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_SDATA1_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_SDATA1_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_SDATA1_SEL_DAP1                       _MK_ENUM_CONST(0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_SDATA1_SEL_DAP2                       _MK_ENUM_CONST(1)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_SDATA1_SEL_DAP3                       _MK_ENUM_CONST(2)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_SDATA1_SEL_DAP4                       _MK_ENUM_CONST(3)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_SDATA1_SEL_DAP5                       _MK_ENUM_CONST(4)
+
+//These bits are to control the selection of bit clock and fsync for DACs.
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_CLK_SEL_SHIFT                 _MK_SHIFT_CONST(0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_CLK_SEL_FIELD                 (_MK_MASK_CONST(0xf) << APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_CLK_SEL_SHIFT)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_CLK_SEL_RANGE                 3:0
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_CLK_SEL_WOFFSET                       0x0
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_CLK_SEL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_CLK_SEL_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_CLK_SEL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_CLK_SEL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_CLK_SEL_DAP1                  _MK_ENUM_CONST(0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_CLK_SEL_DAP2                  _MK_ENUM_CONST(1)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_CLK_SEL_DAP3                  _MK_ENUM_CONST(2)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_CLK_SEL_DAP4                  _MK_ENUM_CONST(3)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_CLK_SEL_DAP5                  _MK_ENUM_CONST(4)
+
+
+// Reserved address 3148 [0xc4c] 
+
+// Reserved address 3152 [0xc50] 
+
+// Reserved address 3156 [0xc54] 
+
+// Reserved address 3160 [0xc58] 
+
+// Reserved address 3164 [0xc5c] 
+
+// Reserved address 3168 [0xc60] 
+
+// Reserved address 3172 [0xc64] 
+
+// Reserved address 3176 [0xc68] 
+
+// Reserved address 3180 [0xc6c] 
+
+// Reserved address 3184 [0xc70] 
+
+// Reserved address 3188 [0xc74] 
+
+// Reserved address 3192 [0xc78] 
+
+// Reserved address 3196 [0xc7c] 
+
+//
+// REGISTER LIST
+//
+#define LIST_ARAPB_MISC_REGS(_op_) \
+_op_(APB_MISC_PP_STRAPPING_OPT_A_0) \
+_op_(APB_MISC_PP_TRISTATE_REG_A_0) \
+_op_(APB_MISC_PP_TRISTATE_REG_B_0) \
+_op_(APB_MISC_PP_TRISTATE_REG_C_0) \
+_op_(APB_MISC_PP_TRISTATE_REG_D_0) \
+_op_(APB_MISC_PP_CONFIG_CTL_0) \
+_op_(APB_MISC_PP_MISC_USB_OTG_0) \
+_op_(APB_MISC_PP_USB_PHY_PARAM_0) \
+_op_(APB_MISC_PP_USB_PHY_VBUS_SENSORS_0) \
+_op_(APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0) \
+_op_(APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0) \
+_op_(APB_MISC_PP_MISC_SAVE_THE_DAY_0) \
+_op_(APB_MISC_PP_PIN_MUX_CTL_A_0) \
+_op_(APB_MISC_PP_PIN_MUX_CTL_B_0) \
+_op_(APB_MISC_PP_PIN_MUX_CTL_C_0) \
+_op_(APB_MISC_PP_PIN_MUX_CTL_D_0) \
+_op_(APB_MISC_PP_PIN_MUX_CTL_E_0) \
+_op_(APB_MISC_PP_PIN_MUX_CTL_F_0) \
+_op_(APB_MISC_PP_PIN_MUX_CTL_G_0) \
+_op_(APB_MISC_PP_PIN_MUX_CTL_H_0) \
+_op_(APB_MISC_PP_PULLUPDOWN_REG_A_0) \
+_op_(APB_MISC_PP_PULLUPDOWN_REG_B_0) \
+_op_(APB_MISC_PP_PULLUPDOWN_REG_C_0) \
+_op_(APB_MISC_PP_PULLUPDOWN_REG_D_0) \
+_op_(APB_MISC_PP_PULLUPDOWN_REG_E_0) \
+_op_(APB_MISC_ASYNC_COREPWRCONFIG_0) \
+_op_(APB_MISC_ASYNC_EMCPADEN_0) \
+_op_(APB_MISC_ASYNC_VCLKCTRL_0) \
+_op_(APB_MISC_ASYNC_TVDACVHSYNCCTRL_0) \
+_op_(APB_MISC_ASYNC_TVDACCNTL_0) \
+_op_(APB_MISC_ASYNC_TVDACSTATUS_0) \
+_op_(APB_MISC_ASYNC_TVDACDINCONFIG_0) \
+_op_(APB_MISC_ASYNC_INT_STATUS_0) \
+_op_(APB_MISC_ASYNC_INT_MASK_0) \
+_op_(APB_MISC_ASYNC_INT_POLARITY_0) \
+_op_(APB_MISC_ASYNC_INT_TYPE_SELECT_0) \
+_op_(APB_MISC_GP_MODEREG_0) \
+_op_(APB_MISC_GP_HIDREV_0) \
+_op_(APB_MISC_GP_ASDBGREG_0) \
+_op_(APB_MISC_GP_OBSCTRL_0) \
+_op_(APB_MISC_GP_OBSDATA_0) \
+_op_(APB_MISC_GP_ASDBGREG2_0) \
+_op_(APB_MISC_GP_ASDBGREG3_0) \
+_op_(APB_MISC_GP_EMU_REVID_0) \
+_op_(APB_MISC_GP_TRANSACTOR_SCRATCH_0) \
+_op_(APB_MISC_GP_AOCFG1PADCTRL_0) \
+_op_(APB_MISC_GP_AOCFG2PADCTRL_0) \
+_op_(APB_MISC_GP_ATCFG1PADCTRL_0) \
+_op_(APB_MISC_GP_ATCFG2PADCTRL_0) \
+_op_(APB_MISC_GP_CDEV1CFGPADCTRL_0) \
+_op_(APB_MISC_GP_CDEV2CFGPADCTRL_0) \
+_op_(APB_MISC_GP_CSUSCFGPADCTRL_0) \
+_op_(APB_MISC_GP_DAP1CFGPADCTRL_0) \
+_op_(APB_MISC_GP_DAP2CFGPADCTRL_0) \
+_op_(APB_MISC_GP_DAP3CFGPADCTRL_0) \
+_op_(APB_MISC_GP_DAP4CFGPADCTRL_0) \
+_op_(APB_MISC_GP_DBGCFGPADCTRL_0) \
+_op_(APB_MISC_GP_LCDCFG1PADCTRL_0) \
+_op_(APB_MISC_GP_LCDCFG2PADCTRL_0) \
+_op_(APB_MISC_GP_SDIO2CFGPADCTRL_0) \
+_op_(APB_MISC_GP_SDIO3CFGPADCTRL_0) \
+_op_(APB_MISC_GP_SPICFGPADCTRL_0) \
+_op_(APB_MISC_GP_UAACFGPADCTRL_0) \
+_op_(APB_MISC_GP_UABCFGPADCTRL_0) \
+_op_(APB_MISC_GP_UART2CFGPADCTRL_0) \
+_op_(APB_MISC_GP_UART3CFGPADCTRL_0) \
+_op_(APB_MISC_GP_VICFG1PADCTRL_0) \
+_op_(APB_MISC_GP_VICFG2PADCTRL_0) \
+_op_(APB_MISC_GP_XM2CFGAPADCTRL_0) \
+_op_(APB_MISC_GP_XM2CFGCPADCTRL_0) \
+_op_(APB_MISC_GP_XM2CFGDPADCTRL_0) \
+_op_(APB_MISC_GP_XM2CLKCFGPADCTRL_0) \
+_op_(APB_MISC_GP_XM2COMPPADCTRL_0) \
+_op_(APB_MISC_GP_XM2VTTGENPADCTRL_0) \
+_op_(APB_MISC_GP_PADCTL_DFT_0) \
+_op_(APB_MISC_GP_SDIO1CFGPADCTRL_0) \
+_op_(APB_MISC_GP_XM2CFGCPADCTRL2_0) \
+_op_(APB_MISC_GP_XM2CFGDPADCTRL2_0) \
+_op_(APB_MISC_GP_CRTCFGPADCTRL_0) \
+_op_(APB_MISC_GP_DDCCFGPADCTRL_0) \
+_op_(APB_MISC_GP_GMACFGPADCTRL_0) \
+_op_(APB_MISC_GP_GMBCFGPADCTRL_0) \
+_op_(APB_MISC_GP_GMCCFGPADCTRL_0) \
+_op_(APB_MISC_GP_GMDCFGPADCTRL_0) \
+_op_(APB_MISC_GP_GMECFGPADCTRL_0) \
+_op_(APB_MISC_GP_OWRCFGPADCTRL_0) \
+_op_(APB_MISC_GP_UADCFGPADCTRL_0) \
+_op_(APB_MISC_GP_AVP_TRANSACTOR_SCRATCH_0) \
+_op_(APB_MISC_GP_CPU0_TRANSACTOR_SCRATCH_0) \
+_op_(APB_MISC_GP_CPU1_TRANSACTOR_SCRATCH_0) \
+_op_(APB_MISC_GP_DEV_PRESENT0_0) \
+_op_(APB_MISC_GP_DEV_PRESENT1_0) \
+_op_(APB_MISC_GP_DEV_PRESENT2_0) \
+_op_(APB_MISC_GP_DEV_PRESENT3_0) \
+_op_(APB_MISC_GP_DEV_PRESENT4_0) \
+_op_(APB_MISC_GP_L2EMU_ADDR_0) \
+_op_(APB_MISC_GP_L2EMU_BE_0) \
+_op_(APB_MISC_GP_L2EMU_DATA0_0) \
+_op_(APB_MISC_GP_L2EMU_DATA1_0) \
+_op_(APB_MISC_GP_L2EMU_DATA2_0) \
+_op_(APB_MISC_GP_L2EMU_DATA3_0) \
+_op_(APB_MISC_GP_L2EMU_DATA4_0) \
+_op_(APB_MISC_GP_L2EMU_DATA5_0) \
+_op_(APB_MISC_GP_L2EMU_DATA6_0) \
+_op_(APB_MISC_GP_L2EMU_DATA7_0) \
+_op_(APB_MISC_GP_L2EMU_READ_0) \
+_op_(APB_MISC_GP_L2EMU_WRITE_0) \
+_op_(APB_MISC_UTMIP_PLL_CFG0_0) \
+_op_(APB_MISC_UTMIP_PLL_CFG1_0) \
+_op_(APB_MISC_UTMIP_XCVR_CFG0_0) \
+_op_(APB_MISC_UTMIP_BIAS_CFG0_0) \
+_op_(APB_MISC_UTMIP_HSRX_CFG0_0) \
+_op_(APB_MISC_UTMIP_HSRX_CFG1_0) \
+_op_(APB_MISC_UTMIP_FSLSRX_CFG0_0) \
+_op_(APB_MISC_UTMIP_FSLSRX_CFG1_0) \
+_op_(APB_MISC_UTMIP_TX_CFG0_0) \
+_op_(APB_MISC_UTMIP_MISC_CFG0_0) \
+_op_(APB_MISC_UTMIP_MISC_CFG1_0) \
+_op_(APB_MISC_UTMIP_DEBOUNCE_CFG0_0) \
+_op_(APB_MISC_UTMIP_BAT_CHRG_CFG0_0) \
+_op_(APB_MISC_UTMIP_SPARE_CFG0_0) \
+_op_(APB_MISC_UTMIP_XCVR_CFG1_0) \
+_op_(APB_MISC_UTMIP_BIAS_CFG1_0) \
+_op_(APB_MISC_UTMIP_BIAS_STS0_0) \
+_op_(APB_MISC_DAS_DAP_CTRL_SEL_0) \
+_op_(APB_MISC_DAS_DAP_CTRL_SEL) \
+_op_(APB_MISC_DAS_DAP_CTRL_SEL_1) \
+_op_(APB_MISC_DAS_DAP_CTRL_SEL_2) \
+_op_(APB_MISC_DAS_DAP_CTRL_SEL_3) \
+_op_(APB_MISC_DAS_DAP_CTRL_SEL_4) \
+_op_(APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0) \
+_op_(APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL) \
+_op_(APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1) \
+_op_(APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2)
+
+
+//
+// ADDRESS SPACES
+//
+
+#define BASE_ADDRESS_APB_MISC   0x00000000
+#define BASE_ADDRESS_APB_MISC_PP        0x00000000
+#define BASE_ADDRESS_APB_MISC_ASYNC     0x00000400
+#define BASE_ADDRESS_APB_MISC_GP        0x00000800
+#define BASE_ADDRESS_APB_MISC_UTMIP     0x00000a00
+#define BASE_ADDRESS_APB_MISC_DAS       0x00000c00
+
+//
+// ARAPB_MISC REGISTER BANKS
+//
+
+#define APB_MISC_PP0_FIRST_REG 0x0008 // APB_MISC_PP_STRAPPING_OPT_A_0
+#define APB_MISC_PP0_LAST_REG 0x0008 // APB_MISC_PP_STRAPPING_OPT_A_0
+#define APB_MISC_PP1_FIRST_REG 0x0014 // APB_MISC_PP_TRISTATE_REG_A_0
+#define APB_MISC_PP1_LAST_REG 0x0028 // APB_MISC_PP_MISC_USB_OTG_0
+#define APB_MISC_PP2_FIRST_REG 0x0064 // APB_MISC_PP_USB_PHY_PARAM_0
+#define APB_MISC_PP2_LAST_REG 0x0064 // APB_MISC_PP_USB_PHY_PARAM_0
+#define APB_MISC_PP3_FIRST_REG 0x0070 // APB_MISC_PP_USB_PHY_VBUS_SENSORS_0
+#define APB_MISC_PP3_LAST_REG 0x00b0 // APB_MISC_PP_PULLUPDOWN_REG_E_0
+#define APB_MISC_ASYNC0_FIRST_REG 0x0400 // APB_MISC_ASYNC_COREPWRCONFIG_0
+#define APB_MISC_ASYNC0_LAST_REG 0x0400 // APB_MISC_ASYNC_COREPWRCONFIG_0
+#define APB_MISC_ASYNC1_FIRST_REG 0x0410 // APB_MISC_ASYNC_EMCPADEN_0
+#define APB_MISC_ASYNC1_LAST_REG 0x0410 // APB_MISC_ASYNC_EMCPADEN_0
+#define APB_MISC_ASYNC2_FIRST_REG 0x042c // APB_MISC_ASYNC_VCLKCTRL_0
+#define APB_MISC_ASYNC2_LAST_REG 0x042c // APB_MISC_ASYNC_VCLKCTRL_0
+#define APB_MISC_ASYNC3_FIRST_REG 0x0438 // APB_MISC_ASYNC_TVDACVHSYNCCTRL_0
+#define APB_MISC_ASYNC3_LAST_REG 0x0454 // APB_MISC_ASYNC_INT_TYPE_SELECT_0
+#define APB_MISC_GP0_FIRST_REG 0x0800 // APB_MISC_GP_MODEREG_0
+#define APB_MISC_GP0_LAST_REG 0x0804 // APB_MISC_GP_HIDREV_0
+#define APB_MISC_GP1_FIRST_REG 0x0810 // APB_MISC_GP_ASDBGREG_0
+#define APB_MISC_GP1_LAST_REG 0x0810 // APB_MISC_GP_ASDBGREG_0
+#define APB_MISC_GP2_FIRST_REG 0x0818 // APB_MISC_GP_OBSCTRL_0
+#define APB_MISC_GP2_LAST_REG 0x081c // APB_MISC_GP_OBSDATA_0
+#define APB_MISC_GP3_FIRST_REG 0x0858 // APB_MISC_GP_ASDBGREG2_0
+#define APB_MISC_GP3_LAST_REG 0x090c // APB_MISC_GP_UADCFGPADCTRL_0
+#define APB_MISC_GP4_FIRST_REG 0x0920 // APB_MISC_GP_AVP_TRANSACTOR_SCRATCH_0
+#define APB_MISC_GP4_LAST_REG 0x096c // APB_MISC_GP_L2EMU_WRITE_0
+#define APB_MISC_UTMIP0_FIRST_REG 0x0a00 // APB_MISC_UTMIP_PLL_CFG0_0
+#define APB_MISC_UTMIP0_LAST_REG 0x0a40 // APB_MISC_UTMIP_BIAS_STS0_0
+#define APB_MISC_DAS0_FIRST_REG 0x0c00 // APB_MISC_DAS_DAP_CTRL_SEL_0
+#define APB_MISC_DAS0_LAST_REG 0x0c10 // APB_MISC_DAS_DAP_CTRL_SEL_4
+#define APB_MISC_DAS1_FIRST_REG 0x0c40 // APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0
+#define APB_MISC_DAS1_LAST_REG 0x0c48 // APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2
+
+#ifndef _MK_SHIFT_CONST
+  #define _MK_SHIFT_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_MASK_CONST
+  #define _MK_MASK_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_ENUM_CONST
+  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
+#endif
+#ifndef _MK_ADDR_CONST
+  #define _MK_ADDR_CONST(_constant_) _constant_
+#endif
+
+#endif // ifndef ___ARAPB_MISC_H_INC_
diff --git a/arch/arm/mach-tegra/include/ap20/arapbdma.h b/arch/arm/mach-tegra/include/ap20/arapbdma.h
new file mode 100644
index 000000000000..2a475f7e9981
--- /dev/null
+++ b/arch/arm/mach-tegra/include/ap20/arapbdma.h
@@ -0,0 +1,2666 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+//
+// DO NOT EDIT - generated by simspec!
+//
+
+#ifndef ___ARAPBDMA_H_INC_
+#define ___ARAPBDMA_H_INC_
+
+// Register APBDMA_COMMAND_0  
+#define APBDMA_COMMAND_0                        _MK_ADDR_CONST(0x0)
+#define APBDMA_COMMAND_0_SECURE                         0x0
+#define APBDMA_COMMAND_0_WORD_COUNT                     0x1
+#define APBDMA_COMMAND_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define APBDMA_COMMAND_0_RESET_MASK                     _MK_MASK_CONST(0x80000000)
+#define APBDMA_COMMAND_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define APBDMA_COMMAND_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_COMMAND_0_READ_MASK                      _MK_MASK_CONST(0x80000000)
+#define APBDMA_COMMAND_0_WRITE_MASK                     _MK_MASK_CONST(0x80000000)
+// Enables Global APB-DMA  
+#define APBDMA_COMMAND_0_GEN_SHIFT                      _MK_SHIFT_CONST(31)
+#define APBDMA_COMMAND_0_GEN_FIELD                      (_MK_MASK_CONST(0x1) << APBDMA_COMMAND_0_GEN_SHIFT)
+#define APBDMA_COMMAND_0_GEN_RANGE                      31:31
+#define APBDMA_COMMAND_0_GEN_WOFFSET                    0x0
+#define APBDMA_COMMAND_0_GEN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_COMMAND_0_GEN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMA_COMMAND_0_GEN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_COMMAND_0_GEN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMA_COMMAND_0_GEN_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDMA_COMMAND_0_GEN_ENABLE                     _MK_ENUM_CONST(1)
+
+
+// Register APBDMA_STATUS_0  
+#define APBDMA_STATUS_0                 _MK_ADDR_CONST(0x4)
+#define APBDMA_STATUS_0_SECURE                  0x0
+#define APBDMA_STATUS_0_WORD_COUNT                      0x1
+#define APBDMA_STATUS_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define APBDMA_STATUS_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define APBDMA_STATUS_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
+// DMA channel15  status 
+#define APBDMA_STATUS_0_BSY_15_SHIFT                    _MK_SHIFT_CONST(31)
+#define APBDMA_STATUS_0_BSY_15_FIELD                    (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_BSY_15_SHIFT)
+#define APBDMA_STATUS_0_BSY_15_RANGE                    31:31
+#define APBDMA_STATUS_0_BSY_15_WOFFSET                  0x0
+#define APBDMA_STATUS_0_BSY_15_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_15_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_BSY_15_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_15_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_15_NOT_BUSY                 _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_BSY_15_BUSY                     _MK_ENUM_CONST(1)
+
+// DMA channel14  status
+#define APBDMA_STATUS_0_BSY_14_SHIFT                    _MK_SHIFT_CONST(30)
+#define APBDMA_STATUS_0_BSY_14_FIELD                    (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_BSY_14_SHIFT)
+#define APBDMA_STATUS_0_BSY_14_RANGE                    30:30
+#define APBDMA_STATUS_0_BSY_14_WOFFSET                  0x0
+#define APBDMA_STATUS_0_BSY_14_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_14_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_BSY_14_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_14_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_14_NOT_BUSY                 _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_BSY_14_BUSY                     _MK_ENUM_CONST(1)
+
+// DMA channel13  status 
+#define APBDMA_STATUS_0_BSY_13_SHIFT                    _MK_SHIFT_CONST(29)
+#define APBDMA_STATUS_0_BSY_13_FIELD                    (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_BSY_13_SHIFT)
+#define APBDMA_STATUS_0_BSY_13_RANGE                    29:29
+#define APBDMA_STATUS_0_BSY_13_WOFFSET                  0x0
+#define APBDMA_STATUS_0_BSY_13_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_13_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_BSY_13_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_13_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_13_NOT_BUSY                 _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_BSY_13_BUSY                     _MK_ENUM_CONST(1)
+
+// DMA channel12  status 
+#define APBDMA_STATUS_0_BSY_12_SHIFT                    _MK_SHIFT_CONST(28)
+#define APBDMA_STATUS_0_BSY_12_FIELD                    (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_BSY_12_SHIFT)
+#define APBDMA_STATUS_0_BSY_12_RANGE                    28:28
+#define APBDMA_STATUS_0_BSY_12_WOFFSET                  0x0
+#define APBDMA_STATUS_0_BSY_12_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_12_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_BSY_12_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_12_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_12_NOT_BUSY                 _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_BSY_12_BUSY                     _MK_ENUM_CONST(1)
+
+// DMA channel11  status 
+#define APBDMA_STATUS_0_BSY_11_SHIFT                    _MK_SHIFT_CONST(27)
+#define APBDMA_STATUS_0_BSY_11_FIELD                    (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_BSY_11_SHIFT)
+#define APBDMA_STATUS_0_BSY_11_RANGE                    27:27
+#define APBDMA_STATUS_0_BSY_11_WOFFSET                  0x0
+#define APBDMA_STATUS_0_BSY_11_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_11_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_BSY_11_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_11_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_11_NOT_BUSY                 _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_BSY_11_BUSY                     _MK_ENUM_CONST(1)
+
+// DMA channel10  status
+#define APBDMA_STATUS_0_BSY_10_SHIFT                    _MK_SHIFT_CONST(26)
+#define APBDMA_STATUS_0_BSY_10_FIELD                    (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_BSY_10_SHIFT)
+#define APBDMA_STATUS_0_BSY_10_RANGE                    26:26
+#define APBDMA_STATUS_0_BSY_10_WOFFSET                  0x0
+#define APBDMA_STATUS_0_BSY_10_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_10_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_BSY_10_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_10_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_10_NOT_BUSY                 _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_BSY_10_BUSY                     _MK_ENUM_CONST(1)
+
+// DMA channel9  status 
+#define APBDMA_STATUS_0_BSY_9_SHIFT                     _MK_SHIFT_CONST(25)
+#define APBDMA_STATUS_0_BSY_9_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_BSY_9_SHIFT)
+#define APBDMA_STATUS_0_BSY_9_RANGE                     25:25
+#define APBDMA_STATUS_0_BSY_9_WOFFSET                   0x0
+#define APBDMA_STATUS_0_BSY_9_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_9_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_BSY_9_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_9_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_9_NOT_BUSY                  _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_BSY_9_BUSY                      _MK_ENUM_CONST(1)
+
+// DMA channel8  status 
+#define APBDMA_STATUS_0_BSY_8_SHIFT                     _MK_SHIFT_CONST(24)
+#define APBDMA_STATUS_0_BSY_8_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_BSY_8_SHIFT)
+#define APBDMA_STATUS_0_BSY_8_RANGE                     24:24
+#define APBDMA_STATUS_0_BSY_8_WOFFSET                   0x0
+#define APBDMA_STATUS_0_BSY_8_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_8_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_BSY_8_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_8_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_8_NOT_BUSY                  _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_BSY_8_BUSY                      _MK_ENUM_CONST(1)
+
+// DMA channel7  status 
+#define APBDMA_STATUS_0_BSY_7_SHIFT                     _MK_SHIFT_CONST(23)
+#define APBDMA_STATUS_0_BSY_7_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_BSY_7_SHIFT)
+#define APBDMA_STATUS_0_BSY_7_RANGE                     23:23
+#define APBDMA_STATUS_0_BSY_7_WOFFSET                   0x0
+#define APBDMA_STATUS_0_BSY_7_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_7_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_BSY_7_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_7_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_7_NOT_BUSY                  _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_BSY_7_BUSY                      _MK_ENUM_CONST(1)
+
+// DMA channel6  status 
+#define APBDMA_STATUS_0_BSY_6_SHIFT                     _MK_SHIFT_CONST(22)
+#define APBDMA_STATUS_0_BSY_6_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_BSY_6_SHIFT)
+#define APBDMA_STATUS_0_BSY_6_RANGE                     22:22
+#define APBDMA_STATUS_0_BSY_6_WOFFSET                   0x0
+#define APBDMA_STATUS_0_BSY_6_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_6_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_BSY_6_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_6_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_6_NOT_BUSY                  _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_BSY_6_BUSY                      _MK_ENUM_CONST(1)
+
+// DMA channel5  status 
+#define APBDMA_STATUS_0_BSY_5_SHIFT                     _MK_SHIFT_CONST(21)
+#define APBDMA_STATUS_0_BSY_5_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_BSY_5_SHIFT)
+#define APBDMA_STATUS_0_BSY_5_RANGE                     21:21
+#define APBDMA_STATUS_0_BSY_5_WOFFSET                   0x0
+#define APBDMA_STATUS_0_BSY_5_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_5_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_BSY_5_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_5_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_5_NOT_BUSY                  _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_BSY_5_BUSY                      _MK_ENUM_CONST(1)
+
+// DMA channel4  status 
+#define APBDMA_STATUS_0_BSY_4_SHIFT                     _MK_SHIFT_CONST(20)
+#define APBDMA_STATUS_0_BSY_4_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_BSY_4_SHIFT)
+#define APBDMA_STATUS_0_BSY_4_RANGE                     20:20
+#define APBDMA_STATUS_0_BSY_4_WOFFSET                   0x0
+#define APBDMA_STATUS_0_BSY_4_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_4_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_BSY_4_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_4_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_4_NOT_BUSY                  _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_BSY_4_BUSY                      _MK_ENUM_CONST(1)
+
+// DMA channel3  status 
+#define APBDMA_STATUS_0_BSY_3_SHIFT                     _MK_SHIFT_CONST(19)
+#define APBDMA_STATUS_0_BSY_3_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_BSY_3_SHIFT)
+#define APBDMA_STATUS_0_BSY_3_RANGE                     19:19
+#define APBDMA_STATUS_0_BSY_3_WOFFSET                   0x0
+#define APBDMA_STATUS_0_BSY_3_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_3_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_BSY_3_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_3_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_3_NOT_BUSY                  _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_BSY_3_BUSY                      _MK_ENUM_CONST(1)
+
+// DMA channel2  status 
+#define APBDMA_STATUS_0_BSY_2_SHIFT                     _MK_SHIFT_CONST(18)
+#define APBDMA_STATUS_0_BSY_2_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_BSY_2_SHIFT)
+#define APBDMA_STATUS_0_BSY_2_RANGE                     18:18
+#define APBDMA_STATUS_0_BSY_2_WOFFSET                   0x0
+#define APBDMA_STATUS_0_BSY_2_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_2_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_BSY_2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_2_NOT_BUSY                  _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_BSY_2_BUSY                      _MK_ENUM_CONST(1)
+
+// DMA channel1  status 
+#define APBDMA_STATUS_0_BSY_1_SHIFT                     _MK_SHIFT_CONST(17)
+#define APBDMA_STATUS_0_BSY_1_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_BSY_1_SHIFT)
+#define APBDMA_STATUS_0_BSY_1_RANGE                     17:17
+#define APBDMA_STATUS_0_BSY_1_WOFFSET                   0x0
+#define APBDMA_STATUS_0_BSY_1_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_1_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_BSY_1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_1_NOT_BUSY                  _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_BSY_1_BUSY                      _MK_ENUM_CONST(1)
+
+// DMA channel0  status 
+#define APBDMA_STATUS_0_BSY_0_SHIFT                     _MK_SHIFT_CONST(16)
+#define APBDMA_STATUS_0_BSY_0_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_BSY_0_SHIFT)
+#define APBDMA_STATUS_0_BSY_0_RANGE                     16:16
+#define APBDMA_STATUS_0_BSY_0_WOFFSET                   0x0
+#define APBDMA_STATUS_0_BSY_0_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_0_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_BSY_0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_0_NOT_BUSY                  _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_BSY_0_BUSY                      _MK_ENUM_CONST(1)
+
+// DMA channel15 Interrupt Status
+#define APBDMA_STATUS_0_ISE_EOC_15_SHIFT                        _MK_SHIFT_CONST(15)
+#define APBDMA_STATUS_0_ISE_EOC_15_FIELD                        (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_ISE_EOC_15_SHIFT)
+#define APBDMA_STATUS_0_ISE_EOC_15_RANGE                        15:15
+#define APBDMA_STATUS_0_ISE_EOC_15_WOFFSET                      0x0
+#define APBDMA_STATUS_0_ISE_EOC_15_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_15_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_ISE_EOC_15_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_15_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_15_NOT_ACTIVE                   _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_ISE_EOC_15_ACTIVE                       _MK_ENUM_CONST(1)
+
+// DMA channel14 Interrupt Status 
+#define APBDMA_STATUS_0_ISE_EOC_14_SHIFT                        _MK_SHIFT_CONST(14)
+#define APBDMA_STATUS_0_ISE_EOC_14_FIELD                        (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_ISE_EOC_14_SHIFT)
+#define APBDMA_STATUS_0_ISE_EOC_14_RANGE                        14:14
+#define APBDMA_STATUS_0_ISE_EOC_14_WOFFSET                      0x0
+#define APBDMA_STATUS_0_ISE_EOC_14_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_14_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_ISE_EOC_14_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_14_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_14_NOT_ACTIVE                   _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_ISE_EOC_14_ACTIVE                       _MK_ENUM_CONST(1)
+
+// DMA channel13 Interrupt Status 
+#define APBDMA_STATUS_0_ISE_EOC_13_SHIFT                        _MK_SHIFT_CONST(13)
+#define APBDMA_STATUS_0_ISE_EOC_13_FIELD                        (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_ISE_EOC_13_SHIFT)
+#define APBDMA_STATUS_0_ISE_EOC_13_RANGE                        13:13
+#define APBDMA_STATUS_0_ISE_EOC_13_WOFFSET                      0x0
+#define APBDMA_STATUS_0_ISE_EOC_13_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_13_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_ISE_EOC_13_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_13_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_13_NOT_ACTIVE                   _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_ISE_EOC_13_ACTIVE                       _MK_ENUM_CONST(1)
+
+// DMA channel12 Interrupt Status 
+#define APBDMA_STATUS_0_ISE_EOC_12_SHIFT                        _MK_SHIFT_CONST(12)
+#define APBDMA_STATUS_0_ISE_EOC_12_FIELD                        (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_ISE_EOC_12_SHIFT)
+#define APBDMA_STATUS_0_ISE_EOC_12_RANGE                        12:12
+#define APBDMA_STATUS_0_ISE_EOC_12_WOFFSET                      0x0
+#define APBDMA_STATUS_0_ISE_EOC_12_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_12_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_ISE_EOC_12_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_12_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_12_NOT_ACTIVE                   _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_ISE_EOC_12_ACTIVE                       _MK_ENUM_CONST(1)
+
+// DMA channel11 Interrupt Status 
+#define APBDMA_STATUS_0_ISE_EOC_11_SHIFT                        _MK_SHIFT_CONST(11)
+#define APBDMA_STATUS_0_ISE_EOC_11_FIELD                        (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_ISE_EOC_11_SHIFT)
+#define APBDMA_STATUS_0_ISE_EOC_11_RANGE                        11:11
+#define APBDMA_STATUS_0_ISE_EOC_11_WOFFSET                      0x0
+#define APBDMA_STATUS_0_ISE_EOC_11_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_11_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_ISE_EOC_11_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_11_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_11_NOT_ACTIVE                   _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_ISE_EOC_11_ACTIVE                       _MK_ENUM_CONST(1)
+
+// DMA channel10 Interrupt Status
+#define APBDMA_STATUS_0_ISE_EOC_10_SHIFT                        _MK_SHIFT_CONST(10)
+#define APBDMA_STATUS_0_ISE_EOC_10_FIELD                        (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_ISE_EOC_10_SHIFT)
+#define APBDMA_STATUS_0_ISE_EOC_10_RANGE                        10:10
+#define APBDMA_STATUS_0_ISE_EOC_10_WOFFSET                      0x0
+#define APBDMA_STATUS_0_ISE_EOC_10_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_10_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_ISE_EOC_10_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_10_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_10_NOT_ACTIVE                   _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_ISE_EOC_10_ACTIVE                       _MK_ENUM_CONST(1)
+
+// DMA channel9  Interrupt Status 
+#define APBDMA_STATUS_0_ISE_EOC_9_SHIFT                 _MK_SHIFT_CONST(9)
+#define APBDMA_STATUS_0_ISE_EOC_9_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_ISE_EOC_9_SHIFT)
+#define APBDMA_STATUS_0_ISE_EOC_9_RANGE                 9:9
+#define APBDMA_STATUS_0_ISE_EOC_9_WOFFSET                       0x0
+#define APBDMA_STATUS_0_ISE_EOC_9_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_9_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_ISE_EOC_9_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_9_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_9_NOT_ACTIVE                    _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_ISE_EOC_9_ACTIVE                        _MK_ENUM_CONST(1)
+
+// DMA channel8  Interrupt Status 
+#define APBDMA_STATUS_0_ISE_EOC_8_SHIFT                 _MK_SHIFT_CONST(8)
+#define APBDMA_STATUS_0_ISE_EOC_8_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_ISE_EOC_8_SHIFT)
+#define APBDMA_STATUS_0_ISE_EOC_8_RANGE                 8:8
+#define APBDMA_STATUS_0_ISE_EOC_8_WOFFSET                       0x0
+#define APBDMA_STATUS_0_ISE_EOC_8_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_8_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_ISE_EOC_8_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_8_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_8_NOT_ACTIVE                    _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_ISE_EOC_8_ACTIVE                        _MK_ENUM_CONST(1)
+
+// DMA channel7  Interrupt Status 
+#define APBDMA_STATUS_0_ISE_EOC_7_SHIFT                 _MK_SHIFT_CONST(7)
+#define APBDMA_STATUS_0_ISE_EOC_7_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_ISE_EOC_7_SHIFT)
+#define APBDMA_STATUS_0_ISE_EOC_7_RANGE                 7:7
+#define APBDMA_STATUS_0_ISE_EOC_7_WOFFSET                       0x0
+#define APBDMA_STATUS_0_ISE_EOC_7_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_7_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_ISE_EOC_7_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_7_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_7_NOT_ACTIVE                    _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_ISE_EOC_7_ACTIVE                        _MK_ENUM_CONST(1)
+
+// DMA channel6  Interrupt Status 
+#define APBDMA_STATUS_0_ISE_EOC_6_SHIFT                 _MK_SHIFT_CONST(6)
+#define APBDMA_STATUS_0_ISE_EOC_6_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_ISE_EOC_6_SHIFT)
+#define APBDMA_STATUS_0_ISE_EOC_6_RANGE                 6:6
+#define APBDMA_STATUS_0_ISE_EOC_6_WOFFSET                       0x0
+#define APBDMA_STATUS_0_ISE_EOC_6_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_6_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_ISE_EOC_6_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_6_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_6_NOT_ACTIVE                    _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_ISE_EOC_6_ACTIVE                        _MK_ENUM_CONST(1)
+
+// DMA channel5  Interrupt Status 
+#define APBDMA_STATUS_0_ISE_EOC_5_SHIFT                 _MK_SHIFT_CONST(5)
+#define APBDMA_STATUS_0_ISE_EOC_5_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_ISE_EOC_5_SHIFT)
+#define APBDMA_STATUS_0_ISE_EOC_5_RANGE                 5:5
+#define APBDMA_STATUS_0_ISE_EOC_5_WOFFSET                       0x0
+#define APBDMA_STATUS_0_ISE_EOC_5_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_5_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_ISE_EOC_5_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_5_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_5_NOT_ACTIVE                    _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_ISE_EOC_5_ACTIVE                        _MK_ENUM_CONST(1)
+
+// DMA channel4  Interrupt Status 
+#define APBDMA_STATUS_0_ISE_EOC_4_SHIFT                 _MK_SHIFT_CONST(4)
+#define APBDMA_STATUS_0_ISE_EOC_4_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_ISE_EOC_4_SHIFT)
+#define APBDMA_STATUS_0_ISE_EOC_4_RANGE                 4:4
+#define APBDMA_STATUS_0_ISE_EOC_4_WOFFSET                       0x0
+#define APBDMA_STATUS_0_ISE_EOC_4_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_4_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_ISE_EOC_4_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_4_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_4_NOT_ACTIVE                    _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_ISE_EOC_4_ACTIVE                        _MK_ENUM_CONST(1)
+
+// DMA channel3  Interrupt Status 
+#define APBDMA_STATUS_0_ISE_EOC_3_SHIFT                 _MK_SHIFT_CONST(3)
+#define APBDMA_STATUS_0_ISE_EOC_3_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_ISE_EOC_3_SHIFT)
+#define APBDMA_STATUS_0_ISE_EOC_3_RANGE                 3:3
+#define APBDMA_STATUS_0_ISE_EOC_3_WOFFSET                       0x0
+#define APBDMA_STATUS_0_ISE_EOC_3_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_3_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_ISE_EOC_3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_3_NOT_ACTIVE                    _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_ISE_EOC_3_ACTIVE                        _MK_ENUM_CONST(1)
+
+// DMA channel2  Interrupt Status 
+#define APBDMA_STATUS_0_ISE_EOC_2_SHIFT                 _MK_SHIFT_CONST(2)
+#define APBDMA_STATUS_0_ISE_EOC_2_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_ISE_EOC_2_SHIFT)
+#define APBDMA_STATUS_0_ISE_EOC_2_RANGE                 2:2
+#define APBDMA_STATUS_0_ISE_EOC_2_WOFFSET                       0x0
+#define APBDMA_STATUS_0_ISE_EOC_2_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_2_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_ISE_EOC_2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_2_NOT_ACTIVE                    _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_ISE_EOC_2_ACTIVE                        _MK_ENUM_CONST(1)
+
+// DMA channel1  Interrupt Status 
+#define APBDMA_STATUS_0_ISE_EOC_1_SHIFT                 _MK_SHIFT_CONST(1)
+#define APBDMA_STATUS_0_ISE_EOC_1_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_ISE_EOC_1_SHIFT)
+#define APBDMA_STATUS_0_ISE_EOC_1_RANGE                 1:1
+#define APBDMA_STATUS_0_ISE_EOC_1_WOFFSET                       0x0
+#define APBDMA_STATUS_0_ISE_EOC_1_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_1_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_ISE_EOC_1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_1_NOT_ACTIVE                    _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_ISE_EOC_1_ACTIVE                        _MK_ENUM_CONST(1)
+
+// DMA channel0  Interrupt Status 
+#define APBDMA_STATUS_0_ISE_EOC_0_SHIFT                 _MK_SHIFT_CONST(0)
+#define APBDMA_STATUS_0_ISE_EOC_0_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_ISE_EOC_0_SHIFT)
+#define APBDMA_STATUS_0_ISE_EOC_0_RANGE                 0:0
+#define APBDMA_STATUS_0_ISE_EOC_0_WOFFSET                       0x0
+#define APBDMA_STATUS_0_ISE_EOC_0_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_0_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_ISE_EOC_0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_0_NOT_ACTIVE                    _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_ISE_EOC_0_ACTIVE                        _MK_ENUM_CONST(1)
+
+
+// Register APBDMA_REQUESTORS_TX_0  
+#define APBDMA_REQUESTORS_TX_0                  _MK_ADDR_CONST(0x8)
+#define APBDMA_REQUESTORS_TX_0_SECURE                   0x0
+#define APBDMA_REQUESTORS_TX_0_WORD_COUNT                       0x1
+#define APBDMA_REQUESTORS_TX_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_RESET_MASK                       _MK_MASK_CONST(0x3ffffff)
+#define APBDMA_REQUESTORS_TX_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_READ_MASK                        _MK_MASK_CONST(0x3ffffff)
+#define APBDMA_REQUESTORS_TX_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
+// OWR-I2C
+#define APBDMA_REQUESTORS_TX_0_OWR_SHIFT                        _MK_SHIFT_CONST(25)
+#define APBDMA_REQUESTORS_TX_0_OWR_FIELD                        (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_TX_0_OWR_SHIFT)
+#define APBDMA_REQUESTORS_TX_0_OWR_RANGE                        25:25
+#define APBDMA_REQUESTORS_TX_0_OWR_WOFFSET                      0x0
+#define APBDMA_REQUESTORS_TX_0_OWR_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_OWR_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_TX_0_OWR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_OWR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_OWR_NOT_ACTIVE                   _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_TX_0_OWR_ACTIVE                       _MK_ENUM_CONST(1)
+
+// DVC-I2C
+#define APBDMA_REQUESTORS_TX_0_DVC_I2C_SHIFT                    _MK_SHIFT_CONST(24)
+#define APBDMA_REQUESTORS_TX_0_DVC_I2C_FIELD                    (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_TX_0_DVC_I2C_SHIFT)
+#define APBDMA_REQUESTORS_TX_0_DVC_I2C_RANGE                    24:24
+#define APBDMA_REQUESTORS_TX_0_DVC_I2C_WOFFSET                  0x0
+#define APBDMA_REQUESTORS_TX_0_DVC_I2C_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_DVC_I2C_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_TX_0_DVC_I2C_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_DVC_I2C_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_DVC_I2C_NOT_ACTIVE                       _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_TX_0_DVC_I2C_ACTIVE                   _MK_ENUM_CONST(1)
+
+// I2C3 
+#define APBDMA_REQUESTORS_TX_0_I2C_3_SHIFT                      _MK_SHIFT_CONST(23)
+#define APBDMA_REQUESTORS_TX_0_I2C_3_FIELD                      (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_TX_0_I2C_3_SHIFT)
+#define APBDMA_REQUESTORS_TX_0_I2C_3_RANGE                      23:23
+#define APBDMA_REQUESTORS_TX_0_I2C_3_WOFFSET                    0x0
+#define APBDMA_REQUESTORS_TX_0_I2C_3_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_I2C_3_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_TX_0_I2C_3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_I2C_3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_I2C_3_NOT_ACTIVE                 _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_TX_0_I2C_3_ACTIVE                     _MK_ENUM_CONST(1)
+
+// I2C2 
+#define APBDMA_REQUESTORS_TX_0_I2C_2_SHIFT                      _MK_SHIFT_CONST(22)
+#define APBDMA_REQUESTORS_TX_0_I2C_2_FIELD                      (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_TX_0_I2C_2_SHIFT)
+#define APBDMA_REQUESTORS_TX_0_I2C_2_RANGE                      22:22
+#define APBDMA_REQUESTORS_TX_0_I2C_2_WOFFSET                    0x0
+#define APBDMA_REQUESTORS_TX_0_I2C_2_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_I2C_2_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_TX_0_I2C_2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_I2C_2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_I2C_2_NOT_ACTIVE                 _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_TX_0_I2C_2_ACTIVE                     _MK_ENUM_CONST(1)
+
+// I2C1 
+#define APBDMA_REQUESTORS_TX_0_I2C_1_SHIFT                      _MK_SHIFT_CONST(21)
+#define APBDMA_REQUESTORS_TX_0_I2C_1_FIELD                      (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_TX_0_I2C_1_SHIFT)
+#define APBDMA_REQUESTORS_TX_0_I2C_1_RANGE                      21:21
+#define APBDMA_REQUESTORS_TX_0_I2C_1_WOFFSET                    0x0
+#define APBDMA_REQUESTORS_TX_0_I2C_1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_I2C_1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_TX_0_I2C_1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_I2C_1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_I2C_1_NOT_ACTIVE                 _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_TX_0_I2C_1_ACTIVE                     _MK_ENUM_CONST(1)
+
+// UARTE 
+#define APBDMA_REQUESTORS_TX_0_UART_E_SHIFT                     _MK_SHIFT_CONST(20)
+#define APBDMA_REQUESTORS_TX_0_UART_E_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_TX_0_UART_E_SHIFT)
+#define APBDMA_REQUESTORS_TX_0_UART_E_RANGE                     20:20
+#define APBDMA_REQUESTORS_TX_0_UART_E_WOFFSET                   0x0
+#define APBDMA_REQUESTORS_TX_0_UART_E_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_UART_E_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_TX_0_UART_E_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_UART_E_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_UART_E_NOT_ACTIVE                        _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_TX_0_UART_E_ACTIVE                    _MK_ENUM_CONST(1)
+
+// UARTD 
+#define APBDMA_REQUESTORS_TX_0_UART_D_SHIFT                     _MK_SHIFT_CONST(19)
+#define APBDMA_REQUESTORS_TX_0_UART_D_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_TX_0_UART_D_SHIFT)
+#define APBDMA_REQUESTORS_TX_0_UART_D_RANGE                     19:19
+#define APBDMA_REQUESTORS_TX_0_UART_D_WOFFSET                   0x0
+#define APBDMA_REQUESTORS_TX_0_UART_D_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_UART_D_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_TX_0_UART_D_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_UART_D_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_UART_D_NOT_ACTIVE                        _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_TX_0_UART_D_ACTIVE                    _MK_ENUM_CONST(1)
+
+// SLINK 2B-4
+#define APBDMA_REQUESTORS_TX_0_SL2B4_SHIFT                      _MK_SHIFT_CONST(18)
+#define APBDMA_REQUESTORS_TX_0_SL2B4_FIELD                      (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_TX_0_SL2B4_SHIFT)
+#define APBDMA_REQUESTORS_TX_0_SL2B4_RANGE                      18:18
+#define APBDMA_REQUESTORS_TX_0_SL2B4_WOFFSET                    0x0
+#define APBDMA_REQUESTORS_TX_0_SL2B4_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_SL2B4_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_TX_0_SL2B4_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_SL2B4_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_SL2B4_NOT_ACTIVE                 _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_TX_0_SL2B4_ACTIVE                     _MK_ENUM_CONST(1)
+
+// SLINK 2B-3
+#define APBDMA_REQUESTORS_TX_0_SL2B3_SHIFT                      _MK_SHIFT_CONST(17)
+#define APBDMA_REQUESTORS_TX_0_SL2B3_FIELD                      (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_TX_0_SL2B3_SHIFT)
+#define APBDMA_REQUESTORS_TX_0_SL2B3_RANGE                      17:17
+#define APBDMA_REQUESTORS_TX_0_SL2B3_WOFFSET                    0x0
+#define APBDMA_REQUESTORS_TX_0_SL2B3_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_SL2B3_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_TX_0_SL2B3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_SL2B3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_SL2B3_NOT_ACTIVE                 _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_TX_0_SL2B3_ACTIVE                     _MK_ENUM_CONST(1)
+
+// SLINK 2B-2
+#define APBDMA_REQUESTORS_TX_0_SL2B2_SHIFT                      _MK_SHIFT_CONST(16)
+#define APBDMA_REQUESTORS_TX_0_SL2B2_FIELD                      (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_TX_0_SL2B2_SHIFT)
+#define APBDMA_REQUESTORS_TX_0_SL2B2_RANGE                      16:16
+#define APBDMA_REQUESTORS_TX_0_SL2B2_WOFFSET                    0x0
+#define APBDMA_REQUESTORS_TX_0_SL2B2_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_SL2B2_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_TX_0_SL2B2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_SL2B2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_SL2B2_NOT_ACTIVE                 _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_TX_0_SL2B2_ACTIVE                     _MK_ENUM_CONST(1)
+
+// SLINK 2B-1
+#define APBDMA_REQUESTORS_TX_0_SL2B1_SHIFT                      _MK_SHIFT_CONST(15)
+#define APBDMA_REQUESTORS_TX_0_SL2B1_FIELD                      (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_TX_0_SL2B1_SHIFT)
+#define APBDMA_REQUESTORS_TX_0_SL2B1_RANGE                      15:15
+#define APBDMA_REQUESTORS_TX_0_SL2B1_WOFFSET                    0x0
+#define APBDMA_REQUESTORS_TX_0_SL2B1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_SL2B1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_TX_0_SL2B1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_SL2B1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_SL2B1_NOT_ACTIVE                 _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_TX_0_SL2B1_ACTIVE                     _MK_ENUM_CONST(1)
+
+// SLINK 4B
+#define APBDMA_REQUESTORS_TX_0_RSVD_SHIFT                       _MK_SHIFT_CONST(14)
+#define APBDMA_REQUESTORS_TX_0_RSVD_FIELD                       (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_TX_0_RSVD_SHIFT)
+#define APBDMA_REQUESTORS_TX_0_RSVD_RANGE                       14:14
+#define APBDMA_REQUESTORS_TX_0_RSVD_WOFFSET                     0x0
+#define APBDMA_REQUESTORS_TX_0_RSVD_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_RSVD_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_TX_0_RSVD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_RSVD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_RSVD_NOT_ACTIVE                  _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_TX_0_RSVD_ACTIVE                      _MK_ENUM_CONST(1)
+
+// ACModem
+#define APBDMA_REQUESTORS_TX_0_ACModem_SHIFT                    _MK_SHIFT_CONST(13)
+#define APBDMA_REQUESTORS_TX_0_ACModem_FIELD                    (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_TX_0_ACModem_SHIFT)
+#define APBDMA_REQUESTORS_TX_0_ACModem_RANGE                    13:13
+#define APBDMA_REQUESTORS_TX_0_ACModem_WOFFSET                  0x0
+#define APBDMA_REQUESTORS_TX_0_ACModem_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_ACModem_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_TX_0_ACModem_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_ACModem_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_ACModem_NOT_ACTIVE                       _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_TX_0_ACModem_ACTIVE                   _MK_ENUM_CONST(1)
+
+// AC97
+#define APBDMA_REQUESTORS_TX_0_AC97_SHIFT                       _MK_SHIFT_CONST(12)
+#define APBDMA_REQUESTORS_TX_0_AC97_FIELD                       (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_TX_0_AC97_SHIFT)
+#define APBDMA_REQUESTORS_TX_0_AC97_RANGE                       12:12
+#define APBDMA_REQUESTORS_TX_0_AC97_WOFFSET                     0x0
+#define APBDMA_REQUESTORS_TX_0_AC97_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_AC97_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_TX_0_AC97_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_AC97_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_AC97_NOT_ACTIVE                  _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_TX_0_AC97_ACTIVE                      _MK_ENUM_CONST(1)
+
+// SPI Controller
+#define APBDMA_REQUESTORS_TX_0_SPI_SHIFT                        _MK_SHIFT_CONST(11)
+#define APBDMA_REQUESTORS_TX_0_SPI_FIELD                        (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_TX_0_SPI_SHIFT)
+#define APBDMA_REQUESTORS_TX_0_SPI_RANGE                        11:11
+#define APBDMA_REQUESTORS_TX_0_SPI_WOFFSET                      0x0
+#define APBDMA_REQUESTORS_TX_0_SPI_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_SPI_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_TX_0_SPI_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_SPI_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_SPI_NOT_ACTIVE                   _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_TX_0_SPI_ACTIVE                       _MK_ENUM_CONST(1)
+
+// UART C
+#define APBDMA_REQUESTORS_TX_0_UART_C_SHIFT                     _MK_SHIFT_CONST(10)
+#define APBDMA_REQUESTORS_TX_0_UART_C_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_TX_0_UART_C_SHIFT)
+#define APBDMA_REQUESTORS_TX_0_UART_C_RANGE                     10:10
+#define APBDMA_REQUESTORS_TX_0_UART_C_WOFFSET                   0x0
+#define APBDMA_REQUESTORS_TX_0_UART_C_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_UART_C_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_TX_0_UART_C_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_UART_C_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_UART_C_NOT_ACTIVE                        _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_TX_0_UART_C_ACTIVE                    _MK_ENUM_CONST(1)
+
+// UART B (VFIR)
+#define APBDMA_REQUESTORS_TX_0_UART_B_SHIFT                     _MK_SHIFT_CONST(9)
+#define APBDMA_REQUESTORS_TX_0_UART_B_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_TX_0_UART_B_SHIFT)
+#define APBDMA_REQUESTORS_TX_0_UART_B_RANGE                     9:9
+#define APBDMA_REQUESTORS_TX_0_UART_B_WOFFSET                   0x0
+#define APBDMA_REQUESTORS_TX_0_UART_B_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_UART_B_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_TX_0_UART_B_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_UART_B_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_UART_B_NOT_ACTIVE                        _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_TX_0_UART_B_ACTIVE                    _MK_ENUM_CONST(1)
+
+// UART A
+#define APBDMA_REQUESTORS_TX_0_UART_A_SHIFT                     _MK_SHIFT_CONST(8)
+#define APBDMA_REQUESTORS_TX_0_UART_A_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_TX_0_UART_A_SHIFT)
+#define APBDMA_REQUESTORS_TX_0_UART_A_RANGE                     8:8
+#define APBDMA_REQUESTORS_TX_0_UART_A_WOFFSET                   0x0
+#define APBDMA_REQUESTORS_TX_0_UART_A_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_UART_A_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_TX_0_UART_A_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_UART_A_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_UART_A_NOT_ACTIVE                        _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_TX_0_UART_A_ACTIVE                    _MK_ENUM_CONST(1)
+
+// I2S2 Tx Output FIFO1 (Play) (Peripheral initiated DMA request) 1 = Activate DMA transfer 0 = NOP
+#define APBDMA_REQUESTORS_TX_0_I2S2_1_SHIFT                     _MK_SHIFT_CONST(7)
+#define APBDMA_REQUESTORS_TX_0_I2S2_1_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_TX_0_I2S2_1_SHIFT)
+#define APBDMA_REQUESTORS_TX_0_I2S2_1_RANGE                     7:7
+#define APBDMA_REQUESTORS_TX_0_I2S2_1_WOFFSET                   0x0
+#define APBDMA_REQUESTORS_TX_0_I2S2_1_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_I2S2_1_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_TX_0_I2S2_1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_I2S2_1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_I2S2_1_NOT_ACTIVE                        _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_TX_0_I2S2_1_ACTIVE                    _MK_ENUM_CONST(1)
+
+// I2S2 Tx Output FIFO2 (Play) (Peripheral initiated DMA request) 1 = Activate DMA transfer 0 = NOP
+#define APBDMA_REQUESTORS_TX_0_I2S2_2_SHIFT                     _MK_SHIFT_CONST(6)
+#define APBDMA_REQUESTORS_TX_0_I2S2_2_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_TX_0_I2S2_2_SHIFT)
+#define APBDMA_REQUESTORS_TX_0_I2S2_2_RANGE                     6:6
+#define APBDMA_REQUESTORS_TX_0_I2S2_2_WOFFSET                   0x0
+#define APBDMA_REQUESTORS_TX_0_I2S2_2_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_I2S2_2_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_TX_0_I2S2_2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_I2S2_2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_I2S2_2_NOT_ACTIVE                        _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_TX_0_I2S2_2_ACTIVE                    _MK_ENUM_CONST(1)
+
+// MIPI Rx Input FIFO.
+#define APBDMA_REQUESTORS_TX_0_MIPI_SHIFT                       _MK_SHIFT_CONST(5)
+#define APBDMA_REQUESTORS_TX_0_MIPI_FIELD                       (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_TX_0_MIPI_SHIFT)
+#define APBDMA_REQUESTORS_TX_0_MIPI_RANGE                       5:5
+#define APBDMA_REQUESTORS_TX_0_MIPI_WOFFSET                     0x0
+#define APBDMA_REQUESTORS_TX_0_MIPI_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_MIPI_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_TX_0_MIPI_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_MIPI_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// EBU USR Output (Peripheral initiated DMA request) 1 = Activate DMA transfer 0 = NOP
+#define APBDMA_REQUESTORS_TX_0_UI_I_SHIFT                       _MK_SHIFT_CONST(4)
+#define APBDMA_REQUESTORS_TX_0_UI_I_FIELD                       (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_TX_0_UI_I_SHIFT)
+#define APBDMA_REQUESTORS_TX_0_UI_I_RANGE                       4:4
+#define APBDMA_REQUESTORS_TX_0_UI_I_WOFFSET                     0x0
+#define APBDMA_REQUESTORS_TX_0_UI_I_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_UI_I_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_TX_0_UI_I_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_UI_I_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_UI_I_NOT_ACTIVE                  _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_TX_0_UI_I_ACTIVE                      _MK_ENUM_CONST(1)
+
+// SPDIF Output FIFO (Rx) (Peripheral initiated DMA request) 1 = Activate DMA transfer 0 = NOP
+#define APBDMA_REQUESTORS_TX_0_SPD_I_SHIFT                      _MK_SHIFT_CONST(3)
+#define APBDMA_REQUESTORS_TX_0_SPD_I_FIELD                      (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_TX_0_SPD_I_SHIFT)
+#define APBDMA_REQUESTORS_TX_0_SPD_I_RANGE                      3:3
+#define APBDMA_REQUESTORS_TX_0_SPD_I_WOFFSET                    0x0
+#define APBDMA_REQUESTORS_TX_0_SPD_I_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_SPD_I_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_TX_0_SPD_I_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_SPD_I_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_SPD_I_NOT_ACTIVE                 _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_TX_0_SPD_I_ACTIVE                     _MK_ENUM_CONST(1)
+
+// I2S Tx Output FIFO1 (Record) (Peripheral initiated DMA request) 1 = Activate DMA transfer0 = NOP
+#define APBDMA_REQUESTORS_TX_0_I2S_1_SHIFT                      _MK_SHIFT_CONST(2)
+#define APBDMA_REQUESTORS_TX_0_I2S_1_FIELD                      (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_TX_0_I2S_1_SHIFT)
+#define APBDMA_REQUESTORS_TX_0_I2S_1_RANGE                      2:2
+#define APBDMA_REQUESTORS_TX_0_I2S_1_WOFFSET                    0x0
+#define APBDMA_REQUESTORS_TX_0_I2S_1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_I2S_1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_TX_0_I2S_1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_I2S_1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_I2S_1_NOT_ACTIVE                 _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_TX_0_I2S_1_ACTIVE                     _MK_ENUM_CONST(1)
+
+// I2S Tx Output FIFO2 (Play) (Peripheral initiated DMA request) 1 = Activate DMA transfer0 = NOP
+#define APBDMA_REQUESTORS_TX_0_I2S_2_SHIFT                      _MK_SHIFT_CONST(1)
+#define APBDMA_REQUESTORS_TX_0_I2S_2_FIELD                      (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_TX_0_I2S_2_SHIFT)
+#define APBDMA_REQUESTORS_TX_0_I2S_2_RANGE                      1:1
+#define APBDMA_REQUESTORS_TX_0_I2S_2_WOFFSET                    0x0
+#define APBDMA_REQUESTORS_TX_0_I2S_2_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_I2S_2_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_TX_0_I2S_2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_I2S_2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_I2S_2_NOT_ACTIVE                 _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_TX_0_I2S_2_ACTIVE                     _MK_ENUM_CONST(1)
+
+// Enables counter request.
+#define APBDMA_REQUESTORS_TX_0_CNTR_REQ_SHIFT                   _MK_SHIFT_CONST(0)
+#define APBDMA_REQUESTORS_TX_0_CNTR_REQ_FIELD                   (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_TX_0_CNTR_REQ_SHIFT)
+#define APBDMA_REQUESTORS_TX_0_CNTR_REQ_RANGE                   0:0
+#define APBDMA_REQUESTORS_TX_0_CNTR_REQ_WOFFSET                 0x0
+#define APBDMA_REQUESTORS_TX_0_CNTR_REQ_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_CNTR_REQ_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_TX_0_CNTR_REQ_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_CNTR_REQ_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_CNTR_REQ_NOT_ACTIVE                      _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_TX_0_CNTR_REQ_ACTIVE                  _MK_ENUM_CONST(1)
+
+
+// Register APBDMA_REQUESTORS_RX_0  
+#define APBDMA_REQUESTORS_RX_0                  _MK_ADDR_CONST(0xc)
+#define APBDMA_REQUESTORS_RX_0_SECURE                   0x0
+#define APBDMA_REQUESTORS_RX_0_WORD_COUNT                       0x1
+#define APBDMA_REQUESTORS_RX_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_RESET_MASK                       _MK_MASK_CONST(0x3ffbfff)
+#define APBDMA_REQUESTORS_RX_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_READ_MASK                        _MK_MASK_CONST(0x3ffffff)
+#define APBDMA_REQUESTORS_RX_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
+// OWR-I2C
+#define APBDMA_REQUESTORS_RX_0_OWR_SHIFT                        _MK_SHIFT_CONST(25)
+#define APBDMA_REQUESTORS_RX_0_OWR_FIELD                        (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_RX_0_OWR_SHIFT)
+#define APBDMA_REQUESTORS_RX_0_OWR_RANGE                        25:25
+#define APBDMA_REQUESTORS_RX_0_OWR_WOFFSET                      0x0
+#define APBDMA_REQUESTORS_RX_0_OWR_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_OWR_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_RX_0_OWR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_OWR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_OWR_NOT_ACTIVE                   _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_RX_0_OWR_ACTIVE                       _MK_ENUM_CONST(1)
+
+// DVC-I2C
+#define APBDMA_REQUESTORS_RX_0_DVC_I2C_SHIFT                    _MK_SHIFT_CONST(24)
+#define APBDMA_REQUESTORS_RX_0_DVC_I2C_FIELD                    (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_RX_0_DVC_I2C_SHIFT)
+#define APBDMA_REQUESTORS_RX_0_DVC_I2C_RANGE                    24:24
+#define APBDMA_REQUESTORS_RX_0_DVC_I2C_WOFFSET                  0x0
+#define APBDMA_REQUESTORS_RX_0_DVC_I2C_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_DVC_I2C_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_RX_0_DVC_I2C_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_DVC_I2C_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_DVC_I2C_NOT_ACTIVE                       _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_RX_0_DVC_I2C_ACTIVE                   _MK_ENUM_CONST(1)
+
+// I2C3 
+#define APBDMA_REQUESTORS_RX_0_I2C_3_SHIFT                      _MK_SHIFT_CONST(23)
+#define APBDMA_REQUESTORS_RX_0_I2C_3_FIELD                      (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_RX_0_I2C_3_SHIFT)
+#define APBDMA_REQUESTORS_RX_0_I2C_3_RANGE                      23:23
+#define APBDMA_REQUESTORS_RX_0_I2C_3_WOFFSET                    0x0
+#define APBDMA_REQUESTORS_RX_0_I2C_3_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_I2C_3_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_RX_0_I2C_3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_I2C_3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_I2C_3_NOT_ACTIVE                 _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_RX_0_I2C_3_ACTIVE                     _MK_ENUM_CONST(1)
+
+// I2C2 
+#define APBDMA_REQUESTORS_RX_0_I2C_2_SHIFT                      _MK_SHIFT_CONST(22)
+#define APBDMA_REQUESTORS_RX_0_I2C_2_FIELD                      (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_RX_0_I2C_2_SHIFT)
+#define APBDMA_REQUESTORS_RX_0_I2C_2_RANGE                      22:22
+#define APBDMA_REQUESTORS_RX_0_I2C_2_WOFFSET                    0x0
+#define APBDMA_REQUESTORS_RX_0_I2C_2_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_I2C_2_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_RX_0_I2C_2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_I2C_2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_I2C_2_NOT_ACTIVE                 _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_RX_0_I2C_2_ACTIVE                     _MK_ENUM_CONST(1)
+
+// I2C1 
+#define APBDMA_REQUESTORS_RX_0_I2C_1_SHIFT                      _MK_SHIFT_CONST(21)
+#define APBDMA_REQUESTORS_RX_0_I2C_1_FIELD                      (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_RX_0_I2C_1_SHIFT)
+#define APBDMA_REQUESTORS_RX_0_I2C_1_RANGE                      21:21
+#define APBDMA_REQUESTORS_RX_0_I2C_1_WOFFSET                    0x0
+#define APBDMA_REQUESTORS_RX_0_I2C_1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_I2C_1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_RX_0_I2C_1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_I2C_1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_I2C_1_NOT_ACTIVE                 _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_RX_0_I2C_1_ACTIVE                     _MK_ENUM_CONST(1)
+
+// UARTE 
+#define APBDMA_REQUESTORS_RX_0_UART_E_SHIFT                     _MK_SHIFT_CONST(20)
+#define APBDMA_REQUESTORS_RX_0_UART_E_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_RX_0_UART_E_SHIFT)
+#define APBDMA_REQUESTORS_RX_0_UART_E_RANGE                     20:20
+#define APBDMA_REQUESTORS_RX_0_UART_E_WOFFSET                   0x0
+#define APBDMA_REQUESTORS_RX_0_UART_E_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_UART_E_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_RX_0_UART_E_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_UART_E_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_UART_E_NOT_ACTIVE                        _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_RX_0_UART_E_ACTIVE                    _MK_ENUM_CONST(1)
+
+// UARTD 
+#define APBDMA_REQUESTORS_RX_0_UART_D_SHIFT                     _MK_SHIFT_CONST(19)
+#define APBDMA_REQUESTORS_RX_0_UART_D_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_RX_0_UART_D_SHIFT)
+#define APBDMA_REQUESTORS_RX_0_UART_D_RANGE                     19:19
+#define APBDMA_REQUESTORS_RX_0_UART_D_WOFFSET                   0x0
+#define APBDMA_REQUESTORS_RX_0_UART_D_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_UART_D_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_RX_0_UART_D_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_UART_D_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_UART_D_NOT_ACTIVE                        _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_RX_0_UART_D_ACTIVE                    _MK_ENUM_CONST(1)
+
+// SLINK 2B-4
+#define APBDMA_REQUESTORS_RX_0_SL2B4_SHIFT                      _MK_SHIFT_CONST(18)
+#define APBDMA_REQUESTORS_RX_0_SL2B4_FIELD                      (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_RX_0_SL2B4_SHIFT)
+#define APBDMA_REQUESTORS_RX_0_SL2B4_RANGE                      18:18
+#define APBDMA_REQUESTORS_RX_0_SL2B4_WOFFSET                    0x0
+#define APBDMA_REQUESTORS_RX_0_SL2B4_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_SL2B4_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_RX_0_SL2B4_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_SL2B4_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_SL2B4_NOT_ACTIVE                 _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_RX_0_SL2B4_ACTIVE                     _MK_ENUM_CONST(1)
+
+// SLINK 2B-3
+#define APBDMA_REQUESTORS_RX_0_SL2B3_SHIFT                      _MK_SHIFT_CONST(17)
+#define APBDMA_REQUESTORS_RX_0_SL2B3_FIELD                      (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_RX_0_SL2B3_SHIFT)
+#define APBDMA_REQUESTORS_RX_0_SL2B3_RANGE                      17:17
+#define APBDMA_REQUESTORS_RX_0_SL2B3_WOFFSET                    0x0
+#define APBDMA_REQUESTORS_RX_0_SL2B3_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_SL2B3_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_RX_0_SL2B3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_SL2B3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_SL2B3_NOT_ACTIVE                 _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_RX_0_SL2B3_ACTIVE                     _MK_ENUM_CONST(1)
+
+// SLINK 2B-2
+#define APBDMA_REQUESTORS_RX_0_SL2B2_SHIFT                      _MK_SHIFT_CONST(16)
+#define APBDMA_REQUESTORS_RX_0_SL2B2_FIELD                      (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_RX_0_SL2B2_SHIFT)
+#define APBDMA_REQUESTORS_RX_0_SL2B2_RANGE                      16:16
+#define APBDMA_REQUESTORS_RX_0_SL2B2_WOFFSET                    0x0
+#define APBDMA_REQUESTORS_RX_0_SL2B2_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_SL2B2_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_RX_0_SL2B2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_SL2B2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_SL2B2_NOT_ACTIVE                 _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_RX_0_SL2B2_ACTIVE                     _MK_ENUM_CONST(1)
+
+// SLINK 2B-1
+#define APBDMA_REQUESTORS_RX_0_SL2B1_SHIFT                      _MK_SHIFT_CONST(15)
+#define APBDMA_REQUESTORS_RX_0_SL2B1_FIELD                      (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_RX_0_SL2B1_SHIFT)
+#define APBDMA_REQUESTORS_RX_0_SL2B1_RANGE                      15:15
+#define APBDMA_REQUESTORS_RX_0_SL2B1_WOFFSET                    0x0
+#define APBDMA_REQUESTORS_RX_0_SL2B1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_SL2B1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_RX_0_SL2B1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_SL2B1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_SL2B1_NOT_ACTIVE                 _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_RX_0_SL2B1_ACTIVE                     _MK_ENUM_CONST(1)
+
+#define APBDMA_REQUESTORS_RX_0_RSVD_SHIFT                       _MK_SHIFT_CONST(14)
+#define APBDMA_REQUESTORS_RX_0_RSVD_FIELD                       (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_RX_0_RSVD_SHIFT)
+#define APBDMA_REQUESTORS_RX_0_RSVD_RANGE                       14:14
+#define APBDMA_REQUESTORS_RX_0_RSVD_WOFFSET                     0x0
+#define APBDMA_REQUESTORS_RX_0_RSVD_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_RSVD_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_RSVD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_RSVD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// ACModem
+#define APBDMA_REQUESTORS_RX_0_ACModem_SHIFT                    _MK_SHIFT_CONST(13)
+#define APBDMA_REQUESTORS_RX_0_ACModem_FIELD                    (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_RX_0_ACModem_SHIFT)
+#define APBDMA_REQUESTORS_RX_0_ACModem_RANGE                    13:13
+#define APBDMA_REQUESTORS_RX_0_ACModem_WOFFSET                  0x0
+#define APBDMA_REQUESTORS_RX_0_ACModem_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_ACModem_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_RX_0_ACModem_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_ACModem_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_ACModem_NOT_ACTIVE                       _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_RX_0_ACModem_ACTIVE                   _MK_ENUM_CONST(1)
+
+// AC97
+#define APBDMA_REQUESTORS_RX_0_AC97_SHIFT                       _MK_SHIFT_CONST(12)
+#define APBDMA_REQUESTORS_RX_0_AC97_FIELD                       (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_RX_0_AC97_SHIFT)
+#define APBDMA_REQUESTORS_RX_0_AC97_RANGE                       12:12
+#define APBDMA_REQUESTORS_RX_0_AC97_WOFFSET                     0x0
+#define APBDMA_REQUESTORS_RX_0_AC97_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_AC97_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_RX_0_AC97_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_AC97_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_AC97_NOT_ACTIVE                  _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_RX_0_AC97_ACTIVE                      _MK_ENUM_CONST(1)
+
+// SPI Controller
+#define APBDMA_REQUESTORS_RX_0_SPI_SHIFT                        _MK_SHIFT_CONST(11)
+#define APBDMA_REQUESTORS_RX_0_SPI_FIELD                        (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_RX_0_SPI_SHIFT)
+#define APBDMA_REQUESTORS_RX_0_SPI_RANGE                        11:11
+#define APBDMA_REQUESTORS_RX_0_SPI_WOFFSET                      0x0
+#define APBDMA_REQUESTORS_RX_0_SPI_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_SPI_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_RX_0_SPI_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_SPI_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_SPI_NOT_ACTIVE                   _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_RX_0_SPI_ACTIVE                       _MK_ENUM_CONST(1)
+
+// UART C
+#define APBDMA_REQUESTORS_RX_0_UART_C_SHIFT                     _MK_SHIFT_CONST(10)
+#define APBDMA_REQUESTORS_RX_0_UART_C_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_RX_0_UART_C_SHIFT)
+#define APBDMA_REQUESTORS_RX_0_UART_C_RANGE                     10:10
+#define APBDMA_REQUESTORS_RX_0_UART_C_WOFFSET                   0x0
+#define APBDMA_REQUESTORS_RX_0_UART_C_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_UART_C_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_RX_0_UART_C_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_UART_C_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_UART_C_NOT_ACTIVE                        _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_RX_0_UART_C_ACTIVE                    _MK_ENUM_CONST(1)
+
+// UART B (VFIR)
+#define APBDMA_REQUESTORS_RX_0_UART_B_SHIFT                     _MK_SHIFT_CONST(9)
+#define APBDMA_REQUESTORS_RX_0_UART_B_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_RX_0_UART_B_SHIFT)
+#define APBDMA_REQUESTORS_RX_0_UART_B_RANGE                     9:9
+#define APBDMA_REQUESTORS_RX_0_UART_B_WOFFSET                   0x0
+#define APBDMA_REQUESTORS_RX_0_UART_B_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_UART_B_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_RX_0_UART_B_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_UART_B_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_UART_B_NOT_ACTIVE                        _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_RX_0_UART_B_ACTIVE                    _MK_ENUM_CONST(1)
+
+// UART A
+#define APBDMA_REQUESTORS_RX_0_UART_A_SHIFT                     _MK_SHIFT_CONST(8)
+#define APBDMA_REQUESTORS_RX_0_UART_A_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_RX_0_UART_A_SHIFT)
+#define APBDMA_REQUESTORS_RX_0_UART_A_RANGE                     8:8
+#define APBDMA_REQUESTORS_RX_0_UART_A_WOFFSET                   0x0
+#define APBDMA_REQUESTORS_RX_0_UART_A_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_UART_A_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_RX_0_UART_A_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_UART_A_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_UART_A_NOT_ACTIVE                        _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_RX_0_UART_A_ACTIVE                    _MK_ENUM_CONST(1)
+
+// I2S2 Rx Input FIFO2 (Peripheral initiated DMA request) 1 = Activate DMA transfer 0 = NOP
+#define APBDMA_REQUESTORS_RX_0_I2S2_2_SHIFT                     _MK_SHIFT_CONST(7)
+#define APBDMA_REQUESTORS_RX_0_I2S2_2_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_RX_0_I2S2_2_SHIFT)
+#define APBDMA_REQUESTORS_RX_0_I2S2_2_RANGE                     7:7
+#define APBDMA_REQUESTORS_RX_0_I2S2_2_WOFFSET                   0x0
+#define APBDMA_REQUESTORS_RX_0_I2S2_2_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_I2S2_2_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_RX_0_I2S2_2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_I2S2_2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_I2S2_2_NOT_ACTIVE                        _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_RX_0_I2S2_2_ACTIVE                    _MK_ENUM_CONST(1)
+
+// I2S2 Rx Input FIFO1 (Peripheral initiated DMA request) 1 = Activate DMA transfer 0 = NOP
+#define APBDMA_REQUESTORS_RX_0_I2S2_1_SHIFT                     _MK_SHIFT_CONST(6)
+#define APBDMA_REQUESTORS_RX_0_I2S2_1_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_RX_0_I2S2_1_SHIFT)
+#define APBDMA_REQUESTORS_RX_0_I2S2_1_RANGE                     6:6
+#define APBDMA_REQUESTORS_RX_0_I2S2_1_WOFFSET                   0x0
+#define APBDMA_REQUESTORS_RX_0_I2S2_1_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_I2S2_1_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_RX_0_I2S2_1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_I2S2_1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_I2S2_1_NOT_ACTIVE                        _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_RX_0_I2S2_1_ACTIVE                    _MK_ENUM_CONST(1)
+
+// MIPI Rx Input FIFO.
+#define APBDMA_REQUESTORS_RX_0_MIPI_SHIFT                       _MK_SHIFT_CONST(5)
+#define APBDMA_REQUESTORS_RX_0_MIPI_FIELD                       (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_RX_0_MIPI_SHIFT)
+#define APBDMA_REQUESTORS_RX_0_MIPI_RANGE                       5:5
+#define APBDMA_REQUESTORS_RX_0_MIPI_WOFFSET                     0x0
+#define APBDMA_REQUESTORS_RX_0_MIPI_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_MIPI_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_RX_0_MIPI_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_MIPI_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// EBU+SPDIF USR Input (Peripheral initiated DMA request) 1 = Activate DMA transfer 0 = NOP
+#define APBDMA_REQUESTORS_RX_0_UI_I_SHIFT                       _MK_SHIFT_CONST(4)
+#define APBDMA_REQUESTORS_RX_0_UI_I_FIELD                       (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_RX_0_UI_I_SHIFT)
+#define APBDMA_REQUESTORS_RX_0_UI_I_RANGE                       4:4
+#define APBDMA_REQUESTORS_RX_0_UI_I_WOFFSET                     0x0
+#define APBDMA_REQUESTORS_RX_0_UI_I_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_UI_I_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_RX_0_UI_I_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_UI_I_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_UI_I_NOT_ACTIVE                  _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_RX_0_UI_I_ACTIVE                      _MK_ENUM_CONST(1)
+
+// SPDIF Input FIFO (Rx) (Peripheral initiated DMA request) 1 = Activate DMA transfer 0 = NOP
+#define APBDMA_REQUESTORS_RX_0_SPD_I_SHIFT                      _MK_SHIFT_CONST(3)
+#define APBDMA_REQUESTORS_RX_0_SPD_I_FIELD                      (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_RX_0_SPD_I_SHIFT)
+#define APBDMA_REQUESTORS_RX_0_SPD_I_RANGE                      3:3
+#define APBDMA_REQUESTORS_RX_0_SPD_I_WOFFSET                    0x0
+#define APBDMA_REQUESTORS_RX_0_SPD_I_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_SPD_I_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_RX_0_SPD_I_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_SPD_I_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_SPD_I_NOT_ACTIVE                 _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_RX_0_SPD_I_ACTIVE                     _MK_ENUM_CONST(1)
+
+//  I2S Rx Input FIFO2 (Peripheral initiated DMA request) 1 = Activate DMA transfer0 = NOP
+#define APBDMA_REQUESTORS_RX_0_I2S_2_SHIFT                      _MK_SHIFT_CONST(2)
+#define APBDMA_REQUESTORS_RX_0_I2S_2_FIELD                      (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_RX_0_I2S_2_SHIFT)
+#define APBDMA_REQUESTORS_RX_0_I2S_2_RANGE                      2:2
+#define APBDMA_REQUESTORS_RX_0_I2S_2_WOFFSET                    0x0
+#define APBDMA_REQUESTORS_RX_0_I2S_2_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_I2S_2_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_RX_0_I2S_2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_I2S_2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_I2S_2_NOT_ACTIVE                 _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_RX_0_I2S_2_ACTIVE                     _MK_ENUM_CONST(1)
+
+//  I2S Rx Input FIFO1 (Peripheral initiated DMA request) 1 = Activate DMA transfer0 = NOP
+#define APBDMA_REQUESTORS_RX_0_I2S_1_SHIFT                      _MK_SHIFT_CONST(1)
+#define APBDMA_REQUESTORS_RX_0_I2S_1_FIELD                      (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_RX_0_I2S_1_SHIFT)
+#define APBDMA_REQUESTORS_RX_0_I2S_1_RANGE                      1:1
+#define APBDMA_REQUESTORS_RX_0_I2S_1_WOFFSET                    0x0
+#define APBDMA_REQUESTORS_RX_0_I2S_1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_I2S_1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_RX_0_I2S_1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_I2S_1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_I2S_1_NOT_ACTIVE                 _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_RX_0_I2S_1_ACTIVE                     _MK_ENUM_CONST(1)
+
+//  indicates Enabled counter request or not 
+#define APBDMA_REQUESTORS_RX_0_CNTR_REQ_SHIFT                   _MK_SHIFT_CONST(0)
+#define APBDMA_REQUESTORS_RX_0_CNTR_REQ_FIELD                   (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_RX_0_CNTR_REQ_SHIFT)
+#define APBDMA_REQUESTORS_RX_0_CNTR_REQ_RANGE                   0:0
+#define APBDMA_REQUESTORS_RX_0_CNTR_REQ_WOFFSET                 0x0
+#define APBDMA_REQUESTORS_RX_0_CNTR_REQ_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_CNTR_REQ_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_RX_0_CNTR_REQ_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_CNTR_REQ_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_CNTR_REQ_NOT_ACTIVE                      _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_RX_0_CNTR_REQ_ACTIVE                  _MK_ENUM_CONST(1)
+
+
+// Register APBDMA_CNTRL_REG_0  
+#define APBDMA_CNTRL_REG_0                      _MK_ADDR_CONST(0x10)
+#define APBDMA_CNTRL_REG_0_SECURE                       0x0
+#define APBDMA_CNTRL_REG_0_WORD_COUNT                   0x1
+#define APBDMA_CNTRL_REG_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define APBDMA_CNTRL_REG_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
+#define APBDMA_CNTRL_REG_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
+// Enable the channel15 count
+#define APBDMA_CNTRL_REG_0_CH15_CNT_EN_SHIFT                    _MK_SHIFT_CONST(31)
+#define APBDMA_CNTRL_REG_0_CH15_CNT_EN_FIELD                    (_MK_MASK_CONST(0x1) << APBDMA_CNTRL_REG_0_CH15_CNT_EN_SHIFT)
+#define APBDMA_CNTRL_REG_0_CH15_CNT_EN_RANGE                    31:31
+#define APBDMA_CNTRL_REG_0_CH15_CNT_EN_WOFFSET                  0x0
+#define APBDMA_CNTRL_REG_0_CH15_CNT_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH15_CNT_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMA_CNTRL_REG_0_CH15_CNT_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH15_CNT_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH15_CNT_EN_DISABLE                  _MK_ENUM_CONST(0)
+#define APBDMA_CNTRL_REG_0_CH15_CNT_EN_ENABLE                   _MK_ENUM_CONST(1)
+
+// Enable the channel14 count
+#define APBDMA_CNTRL_REG_0_CH14_CNT_EN_SHIFT                    _MK_SHIFT_CONST(30)
+#define APBDMA_CNTRL_REG_0_CH14_CNT_EN_FIELD                    (_MK_MASK_CONST(0x1) << APBDMA_CNTRL_REG_0_CH14_CNT_EN_SHIFT)
+#define APBDMA_CNTRL_REG_0_CH14_CNT_EN_RANGE                    30:30
+#define APBDMA_CNTRL_REG_0_CH14_CNT_EN_WOFFSET                  0x0
+#define APBDMA_CNTRL_REG_0_CH14_CNT_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH14_CNT_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMA_CNTRL_REG_0_CH14_CNT_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH14_CNT_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH14_CNT_EN_DISABLE                  _MK_ENUM_CONST(0)
+#define APBDMA_CNTRL_REG_0_CH14_CNT_EN_ENABLE                   _MK_ENUM_CONST(1)
+
+// Enable the channel13 count
+#define APBDMA_CNTRL_REG_0_CH13_CNT_EN_SHIFT                    _MK_SHIFT_CONST(29)
+#define APBDMA_CNTRL_REG_0_CH13_CNT_EN_FIELD                    (_MK_MASK_CONST(0x1) << APBDMA_CNTRL_REG_0_CH13_CNT_EN_SHIFT)
+#define APBDMA_CNTRL_REG_0_CH13_CNT_EN_RANGE                    29:29
+#define APBDMA_CNTRL_REG_0_CH13_CNT_EN_WOFFSET                  0x0
+#define APBDMA_CNTRL_REG_0_CH13_CNT_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH13_CNT_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMA_CNTRL_REG_0_CH13_CNT_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH13_CNT_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH13_CNT_EN_DISABLE                  _MK_ENUM_CONST(0)
+#define APBDMA_CNTRL_REG_0_CH13_CNT_EN_ENABLE                   _MK_ENUM_CONST(1)
+
+// Enable the channel12 count
+#define APBDMA_CNTRL_REG_0_CH12_CNT_EN_SHIFT                    _MK_SHIFT_CONST(28)
+#define APBDMA_CNTRL_REG_0_CH12_CNT_EN_FIELD                    (_MK_MASK_CONST(0x1) << APBDMA_CNTRL_REG_0_CH12_CNT_EN_SHIFT)
+#define APBDMA_CNTRL_REG_0_CH12_CNT_EN_RANGE                    28:28
+#define APBDMA_CNTRL_REG_0_CH12_CNT_EN_WOFFSET                  0x0
+#define APBDMA_CNTRL_REG_0_CH12_CNT_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH12_CNT_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMA_CNTRL_REG_0_CH12_CNT_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH12_CNT_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH12_CNT_EN_DISABLE                  _MK_ENUM_CONST(0)
+#define APBDMA_CNTRL_REG_0_CH12_CNT_EN_ENABLE                   _MK_ENUM_CONST(1)
+
+// Enable the channel11 count
+#define APBDMA_CNTRL_REG_0_CH11_CNT_EN_SHIFT                    _MK_SHIFT_CONST(27)
+#define APBDMA_CNTRL_REG_0_CH11_CNT_EN_FIELD                    (_MK_MASK_CONST(0x1) << APBDMA_CNTRL_REG_0_CH11_CNT_EN_SHIFT)
+#define APBDMA_CNTRL_REG_0_CH11_CNT_EN_RANGE                    27:27
+#define APBDMA_CNTRL_REG_0_CH11_CNT_EN_WOFFSET                  0x0
+#define APBDMA_CNTRL_REG_0_CH11_CNT_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH11_CNT_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMA_CNTRL_REG_0_CH11_CNT_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH11_CNT_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH11_CNT_EN_DISABLE                  _MK_ENUM_CONST(0)
+#define APBDMA_CNTRL_REG_0_CH11_CNT_EN_ENABLE                   _MK_ENUM_CONST(1)
+
+// Enable the channel10 count
+#define APBDMA_CNTRL_REG_0_CH10_CNT_EN_SHIFT                    _MK_SHIFT_CONST(26)
+#define APBDMA_CNTRL_REG_0_CH10_CNT_EN_FIELD                    (_MK_MASK_CONST(0x1) << APBDMA_CNTRL_REG_0_CH10_CNT_EN_SHIFT)
+#define APBDMA_CNTRL_REG_0_CH10_CNT_EN_RANGE                    26:26
+#define APBDMA_CNTRL_REG_0_CH10_CNT_EN_WOFFSET                  0x0
+#define APBDMA_CNTRL_REG_0_CH10_CNT_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH10_CNT_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMA_CNTRL_REG_0_CH10_CNT_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH10_CNT_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH10_CNT_EN_DISABLE                  _MK_ENUM_CONST(0)
+#define APBDMA_CNTRL_REG_0_CH10_CNT_EN_ENABLE                   _MK_ENUM_CONST(1)
+
+// Enable the channel9 count
+#define APBDMA_CNTRL_REG_0_CH9_CNT_EN_SHIFT                     _MK_SHIFT_CONST(25)
+#define APBDMA_CNTRL_REG_0_CH9_CNT_EN_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_CNTRL_REG_0_CH9_CNT_EN_SHIFT)
+#define APBDMA_CNTRL_REG_0_CH9_CNT_EN_RANGE                     25:25
+#define APBDMA_CNTRL_REG_0_CH9_CNT_EN_WOFFSET                   0x0
+#define APBDMA_CNTRL_REG_0_CH9_CNT_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH9_CNT_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_CNTRL_REG_0_CH9_CNT_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH9_CNT_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH9_CNT_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMA_CNTRL_REG_0_CH9_CNT_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// Enable the channel8 count
+#define APBDMA_CNTRL_REG_0_CH8_CNT_EN_SHIFT                     _MK_SHIFT_CONST(24)
+#define APBDMA_CNTRL_REG_0_CH8_CNT_EN_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_CNTRL_REG_0_CH8_CNT_EN_SHIFT)
+#define APBDMA_CNTRL_REG_0_CH8_CNT_EN_RANGE                     24:24
+#define APBDMA_CNTRL_REG_0_CH8_CNT_EN_WOFFSET                   0x0
+#define APBDMA_CNTRL_REG_0_CH8_CNT_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH8_CNT_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_CNTRL_REG_0_CH8_CNT_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH8_CNT_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH8_CNT_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMA_CNTRL_REG_0_CH8_CNT_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// Enable the channel7 count
+#define APBDMA_CNTRL_REG_0_CH7_CNT_EN_SHIFT                     _MK_SHIFT_CONST(23)
+#define APBDMA_CNTRL_REG_0_CH7_CNT_EN_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_CNTRL_REG_0_CH7_CNT_EN_SHIFT)
+#define APBDMA_CNTRL_REG_0_CH7_CNT_EN_RANGE                     23:23
+#define APBDMA_CNTRL_REG_0_CH7_CNT_EN_WOFFSET                   0x0
+#define APBDMA_CNTRL_REG_0_CH7_CNT_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH7_CNT_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_CNTRL_REG_0_CH7_CNT_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH7_CNT_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH7_CNT_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMA_CNTRL_REG_0_CH7_CNT_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// Enable the channel6 count
+#define APBDMA_CNTRL_REG_0_CH6_CNT_EN_SHIFT                     _MK_SHIFT_CONST(22)
+#define APBDMA_CNTRL_REG_0_CH6_CNT_EN_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_CNTRL_REG_0_CH6_CNT_EN_SHIFT)
+#define APBDMA_CNTRL_REG_0_CH6_CNT_EN_RANGE                     22:22
+#define APBDMA_CNTRL_REG_0_CH6_CNT_EN_WOFFSET                   0x0
+#define APBDMA_CNTRL_REG_0_CH6_CNT_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH6_CNT_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_CNTRL_REG_0_CH6_CNT_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH6_CNT_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH6_CNT_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMA_CNTRL_REG_0_CH6_CNT_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// Enable the channel5 count
+#define APBDMA_CNTRL_REG_0_CH5_CNT_EN_SHIFT                     _MK_SHIFT_CONST(21)
+#define APBDMA_CNTRL_REG_0_CH5_CNT_EN_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_CNTRL_REG_0_CH5_CNT_EN_SHIFT)
+#define APBDMA_CNTRL_REG_0_CH5_CNT_EN_RANGE                     21:21
+#define APBDMA_CNTRL_REG_0_CH5_CNT_EN_WOFFSET                   0x0
+#define APBDMA_CNTRL_REG_0_CH5_CNT_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH5_CNT_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_CNTRL_REG_0_CH5_CNT_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH5_CNT_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH5_CNT_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMA_CNTRL_REG_0_CH5_CNT_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// Enable the channel4 count
+#define APBDMA_CNTRL_REG_0_CH4_CNT_EN_SHIFT                     _MK_SHIFT_CONST(20)
+#define APBDMA_CNTRL_REG_0_CH4_CNT_EN_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_CNTRL_REG_0_CH4_CNT_EN_SHIFT)
+#define APBDMA_CNTRL_REG_0_CH4_CNT_EN_RANGE                     20:20
+#define APBDMA_CNTRL_REG_0_CH4_CNT_EN_WOFFSET                   0x0
+#define APBDMA_CNTRL_REG_0_CH4_CNT_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH4_CNT_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_CNTRL_REG_0_CH4_CNT_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH4_CNT_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH4_CNT_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMA_CNTRL_REG_0_CH4_CNT_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// Enable the channel3 count
+#define APBDMA_CNTRL_REG_0_CH3_CNT_EN_SHIFT                     _MK_SHIFT_CONST(19)
+#define APBDMA_CNTRL_REG_0_CH3_CNT_EN_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_CNTRL_REG_0_CH3_CNT_EN_SHIFT)
+#define APBDMA_CNTRL_REG_0_CH3_CNT_EN_RANGE                     19:19
+#define APBDMA_CNTRL_REG_0_CH3_CNT_EN_WOFFSET                   0x0
+#define APBDMA_CNTRL_REG_0_CH3_CNT_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH3_CNT_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_CNTRL_REG_0_CH3_CNT_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH3_CNT_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH3_CNT_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMA_CNTRL_REG_0_CH3_CNT_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// Enable the channel2 count
+#define APBDMA_CNTRL_REG_0_CH2_CNT_EN_SHIFT                     _MK_SHIFT_CONST(18)
+#define APBDMA_CNTRL_REG_0_CH2_CNT_EN_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_CNTRL_REG_0_CH2_CNT_EN_SHIFT)
+#define APBDMA_CNTRL_REG_0_CH2_CNT_EN_RANGE                     18:18
+#define APBDMA_CNTRL_REG_0_CH2_CNT_EN_WOFFSET                   0x0
+#define APBDMA_CNTRL_REG_0_CH2_CNT_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH2_CNT_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_CNTRL_REG_0_CH2_CNT_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH2_CNT_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH2_CNT_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMA_CNTRL_REG_0_CH2_CNT_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// Enable the channel1 count
+#define APBDMA_CNTRL_REG_0_CH1_CNT_EN_SHIFT                     _MK_SHIFT_CONST(17)
+#define APBDMA_CNTRL_REG_0_CH1_CNT_EN_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_CNTRL_REG_0_CH1_CNT_EN_SHIFT)
+#define APBDMA_CNTRL_REG_0_CH1_CNT_EN_RANGE                     17:17
+#define APBDMA_CNTRL_REG_0_CH1_CNT_EN_WOFFSET                   0x0
+#define APBDMA_CNTRL_REG_0_CH1_CNT_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH1_CNT_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_CNTRL_REG_0_CH1_CNT_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH1_CNT_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH1_CNT_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMA_CNTRL_REG_0_CH1_CNT_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// Enable the channel0 count
+#define APBDMA_CNTRL_REG_0_CH0_CNT_EN_SHIFT                     _MK_SHIFT_CONST(16)
+#define APBDMA_CNTRL_REG_0_CH0_CNT_EN_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_CNTRL_REG_0_CH0_CNT_EN_SHIFT)
+#define APBDMA_CNTRL_REG_0_CH0_CNT_EN_RANGE                     16:16
+#define APBDMA_CNTRL_REG_0_CH0_CNT_EN_WOFFSET                   0x0
+#define APBDMA_CNTRL_REG_0_CH0_CNT_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH0_CNT_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_CNTRL_REG_0_CH0_CNT_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH0_CNT_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH0_CNT_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMA_CNTRL_REG_0_CH0_CNT_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// DMA COUNT Value.
+#define APBDMA_CNTRL_REG_0_COUNT_VALUE_SHIFT                    _MK_SHIFT_CONST(0)
+#define APBDMA_CNTRL_REG_0_COUNT_VALUE_FIELD                    (_MK_MASK_CONST(0xffff) << APBDMA_CNTRL_REG_0_COUNT_VALUE_SHIFT)
+#define APBDMA_CNTRL_REG_0_COUNT_VALUE_RANGE                    15:0
+#define APBDMA_CNTRL_REG_0_COUNT_VALUE_WOFFSET                  0x0
+#define APBDMA_CNTRL_REG_0_COUNT_VALUE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_COUNT_VALUE_DEFAULT_MASK                     _MK_MASK_CONST(0xffff)
+#define APBDMA_CNTRL_REG_0_COUNT_VALUE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_COUNT_VALUE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register APBDMA_IRQ_STA_CPU_0  
+#define APBDMA_IRQ_STA_CPU_0                    _MK_ADDR_CONST(0x14)
+#define APBDMA_IRQ_STA_CPU_0_SECURE                     0x0
+#define APBDMA_IRQ_STA_CPU_0_WORD_COUNT                         0x1
+#define APBDMA_IRQ_STA_CPU_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_RESET_MASK                         _MK_MASK_CONST(0xffff)
+#define APBDMA_IRQ_STA_CPU_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_READ_MASK                  _MK_MASK_CONST(0xffff)
+#define APBDMA_IRQ_STA_CPU_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
+// Gathers all the after-masking CPU directed IRQ status bits from channel15 
+#define APBDMA_IRQ_STA_CPU_0_CH15_SHIFT                 _MK_SHIFT_CONST(15)
+#define APBDMA_IRQ_STA_CPU_0_CH15_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_CPU_0_CH15_SHIFT)
+#define APBDMA_IRQ_STA_CPU_0_CH15_RANGE                 15:15
+#define APBDMA_IRQ_STA_CPU_0_CH15_WOFFSET                       0x0
+#define APBDMA_IRQ_STA_CPU_0_CH15_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH15_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_CPU_0_CH15_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH15_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH15_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_CPU_0_CH15_ENABLE                        _MK_ENUM_CONST(1)
+
+// Gathers all the after-masking CPU directed IRQ status bits from channel14 
+#define APBDMA_IRQ_STA_CPU_0_CH14_SHIFT                 _MK_SHIFT_CONST(14)
+#define APBDMA_IRQ_STA_CPU_0_CH14_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_CPU_0_CH14_SHIFT)
+#define APBDMA_IRQ_STA_CPU_0_CH14_RANGE                 14:14
+#define APBDMA_IRQ_STA_CPU_0_CH14_WOFFSET                       0x0
+#define APBDMA_IRQ_STA_CPU_0_CH14_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH14_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_CPU_0_CH14_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH14_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH14_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_CPU_0_CH14_ENABLE                        _MK_ENUM_CONST(1)
+
+// Gathers all the after-masking CPU directed IRQ status bits from channel13 
+#define APBDMA_IRQ_STA_CPU_0_CH13_SHIFT                 _MK_SHIFT_CONST(13)
+#define APBDMA_IRQ_STA_CPU_0_CH13_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_CPU_0_CH13_SHIFT)
+#define APBDMA_IRQ_STA_CPU_0_CH13_RANGE                 13:13
+#define APBDMA_IRQ_STA_CPU_0_CH13_WOFFSET                       0x0
+#define APBDMA_IRQ_STA_CPU_0_CH13_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH13_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_CPU_0_CH13_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH13_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH13_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_CPU_0_CH13_ENABLE                        _MK_ENUM_CONST(1)
+
+// Gathers all the after-masking CPU directed IRQ status bits from channel12 
+#define APBDMA_IRQ_STA_CPU_0_CH12_SHIFT                 _MK_SHIFT_CONST(12)
+#define APBDMA_IRQ_STA_CPU_0_CH12_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_CPU_0_CH12_SHIFT)
+#define APBDMA_IRQ_STA_CPU_0_CH12_RANGE                 12:12
+#define APBDMA_IRQ_STA_CPU_0_CH12_WOFFSET                       0x0
+#define APBDMA_IRQ_STA_CPU_0_CH12_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH12_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_CPU_0_CH12_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH12_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH12_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_CPU_0_CH12_ENABLE                        _MK_ENUM_CONST(1)
+
+// Gathers all the after-masking CPU directed IRQ status bits from channel11 
+#define APBDMA_IRQ_STA_CPU_0_CH11_SHIFT                 _MK_SHIFT_CONST(11)
+#define APBDMA_IRQ_STA_CPU_0_CH11_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_CPU_0_CH11_SHIFT)
+#define APBDMA_IRQ_STA_CPU_0_CH11_RANGE                 11:11
+#define APBDMA_IRQ_STA_CPU_0_CH11_WOFFSET                       0x0
+#define APBDMA_IRQ_STA_CPU_0_CH11_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH11_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_CPU_0_CH11_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH11_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH11_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_CPU_0_CH11_ENABLE                        _MK_ENUM_CONST(1)
+
+// Gathers all the after-masking CPU directed IRQ status bits from channel10 
+#define APBDMA_IRQ_STA_CPU_0_CH10_SHIFT                 _MK_SHIFT_CONST(10)
+#define APBDMA_IRQ_STA_CPU_0_CH10_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_CPU_0_CH10_SHIFT)
+#define APBDMA_IRQ_STA_CPU_0_CH10_RANGE                 10:10
+#define APBDMA_IRQ_STA_CPU_0_CH10_WOFFSET                       0x0
+#define APBDMA_IRQ_STA_CPU_0_CH10_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH10_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_CPU_0_CH10_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH10_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH10_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_CPU_0_CH10_ENABLE                        _MK_ENUM_CONST(1)
+
+// Gathers all the after-masking CPU directed IRQ status bits from channel9 
+#define APBDMA_IRQ_STA_CPU_0_CH9_SHIFT                  _MK_SHIFT_CONST(9)
+#define APBDMA_IRQ_STA_CPU_0_CH9_FIELD                  (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_CPU_0_CH9_SHIFT)
+#define APBDMA_IRQ_STA_CPU_0_CH9_RANGE                  9:9
+#define APBDMA_IRQ_STA_CPU_0_CH9_WOFFSET                        0x0
+#define APBDMA_IRQ_STA_CPU_0_CH9_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH9_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_CPU_0_CH9_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH9_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH9_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_CPU_0_CH9_ENABLE                 _MK_ENUM_CONST(1)
+
+// Gathers all the after-masking CPU directed IRQ status bits from channel8 
+#define APBDMA_IRQ_STA_CPU_0_CH8_SHIFT                  _MK_SHIFT_CONST(8)
+#define APBDMA_IRQ_STA_CPU_0_CH8_FIELD                  (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_CPU_0_CH8_SHIFT)
+#define APBDMA_IRQ_STA_CPU_0_CH8_RANGE                  8:8
+#define APBDMA_IRQ_STA_CPU_0_CH8_WOFFSET                        0x0
+#define APBDMA_IRQ_STA_CPU_0_CH8_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH8_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_CPU_0_CH8_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH8_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH8_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_CPU_0_CH8_ENABLE                 _MK_ENUM_CONST(1)
+
+// Gathers all the after-masking CPU directed IRQ status bits from channel7 
+#define APBDMA_IRQ_STA_CPU_0_CH7_SHIFT                  _MK_SHIFT_CONST(7)
+#define APBDMA_IRQ_STA_CPU_0_CH7_FIELD                  (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_CPU_0_CH7_SHIFT)
+#define APBDMA_IRQ_STA_CPU_0_CH7_RANGE                  7:7
+#define APBDMA_IRQ_STA_CPU_0_CH7_WOFFSET                        0x0
+#define APBDMA_IRQ_STA_CPU_0_CH7_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH7_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_CPU_0_CH7_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH7_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH7_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_CPU_0_CH7_ENABLE                 _MK_ENUM_CONST(1)
+
+// Gathers all the after-masking CPU directed IRQ status bits from channel6 
+#define APBDMA_IRQ_STA_CPU_0_CH6_SHIFT                  _MK_SHIFT_CONST(6)
+#define APBDMA_IRQ_STA_CPU_0_CH6_FIELD                  (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_CPU_0_CH6_SHIFT)
+#define APBDMA_IRQ_STA_CPU_0_CH6_RANGE                  6:6
+#define APBDMA_IRQ_STA_CPU_0_CH6_WOFFSET                        0x0
+#define APBDMA_IRQ_STA_CPU_0_CH6_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH6_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_CPU_0_CH6_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH6_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH6_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_CPU_0_CH6_ENABLE                 _MK_ENUM_CONST(1)
+
+// Gathers all the after-masking CPU directed IRQ status bits from channel5 
+#define APBDMA_IRQ_STA_CPU_0_CH5_SHIFT                  _MK_SHIFT_CONST(5)
+#define APBDMA_IRQ_STA_CPU_0_CH5_FIELD                  (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_CPU_0_CH5_SHIFT)
+#define APBDMA_IRQ_STA_CPU_0_CH5_RANGE                  5:5
+#define APBDMA_IRQ_STA_CPU_0_CH5_WOFFSET                        0x0
+#define APBDMA_IRQ_STA_CPU_0_CH5_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH5_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_CPU_0_CH5_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH5_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH5_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_CPU_0_CH5_ENABLE                 _MK_ENUM_CONST(1)
+
+// Gathers all the after-masking CPU directed IRQ status bits from channel4 
+#define APBDMA_IRQ_STA_CPU_0_CH4_SHIFT                  _MK_SHIFT_CONST(4)
+#define APBDMA_IRQ_STA_CPU_0_CH4_FIELD                  (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_CPU_0_CH4_SHIFT)
+#define APBDMA_IRQ_STA_CPU_0_CH4_RANGE                  4:4
+#define APBDMA_IRQ_STA_CPU_0_CH4_WOFFSET                        0x0
+#define APBDMA_IRQ_STA_CPU_0_CH4_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH4_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_CPU_0_CH4_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH4_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH4_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_CPU_0_CH4_ENABLE                 _MK_ENUM_CONST(1)
+
+// Gathers all the after-masking CPU directed IRQ status bits from channel3 
+#define APBDMA_IRQ_STA_CPU_0_CH3_SHIFT                  _MK_SHIFT_CONST(3)
+#define APBDMA_IRQ_STA_CPU_0_CH3_FIELD                  (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_CPU_0_CH3_SHIFT)
+#define APBDMA_IRQ_STA_CPU_0_CH3_RANGE                  3:3
+#define APBDMA_IRQ_STA_CPU_0_CH3_WOFFSET                        0x0
+#define APBDMA_IRQ_STA_CPU_0_CH3_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH3_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_CPU_0_CH3_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH3_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH3_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_CPU_0_CH3_ENABLE                 _MK_ENUM_CONST(1)
+
+// Gathers all the after-masking CPU directed IRQ status bits from channel2 
+#define APBDMA_IRQ_STA_CPU_0_CH2_SHIFT                  _MK_SHIFT_CONST(2)
+#define APBDMA_IRQ_STA_CPU_0_CH2_FIELD                  (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_CPU_0_CH2_SHIFT)
+#define APBDMA_IRQ_STA_CPU_0_CH2_RANGE                  2:2
+#define APBDMA_IRQ_STA_CPU_0_CH2_WOFFSET                        0x0
+#define APBDMA_IRQ_STA_CPU_0_CH2_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH2_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_CPU_0_CH2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH2_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_CPU_0_CH2_ENABLE                 _MK_ENUM_CONST(1)
+
+// Gathers all the after-masking CPU directed IRQ status bits from channel1 
+#define APBDMA_IRQ_STA_CPU_0_CH1_SHIFT                  _MK_SHIFT_CONST(1)
+#define APBDMA_IRQ_STA_CPU_0_CH1_FIELD                  (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_CPU_0_CH1_SHIFT)
+#define APBDMA_IRQ_STA_CPU_0_CH1_RANGE                  1:1
+#define APBDMA_IRQ_STA_CPU_0_CH1_WOFFSET                        0x0
+#define APBDMA_IRQ_STA_CPU_0_CH1_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH1_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_CPU_0_CH1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH1_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_CPU_0_CH1_ENABLE                 _MK_ENUM_CONST(1)
+
+// Gathers all the after-masking CPU directed IRQ status bits from channel0 
+#define APBDMA_IRQ_STA_CPU_0_CH0_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDMA_IRQ_STA_CPU_0_CH0_FIELD                  (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_CPU_0_CH0_SHIFT)
+#define APBDMA_IRQ_STA_CPU_0_CH0_RANGE                  0:0
+#define APBDMA_IRQ_STA_CPU_0_CH0_WOFFSET                        0x0
+#define APBDMA_IRQ_STA_CPU_0_CH0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH0_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_CPU_0_CH0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH0_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_CPU_0_CH0_ENABLE                 _MK_ENUM_CONST(1)
+
+
+// Register APBDMA_IRQ_STA_COP_0  
+#define APBDMA_IRQ_STA_COP_0                    _MK_ADDR_CONST(0x18)
+#define APBDMA_IRQ_STA_COP_0_SECURE                     0x0
+#define APBDMA_IRQ_STA_COP_0_WORD_COUNT                         0x1
+#define APBDMA_IRQ_STA_COP_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_RESET_MASK                         _MK_MASK_CONST(0xffff)
+#define APBDMA_IRQ_STA_COP_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_READ_MASK                  _MK_MASK_CONST(0xffff)
+#define APBDMA_IRQ_STA_COP_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
+// Gathers all the after-masking COP directed IRQ status bits from channel15 
+#define APBDMA_IRQ_STA_COP_0_CH15_SHIFT                 _MK_SHIFT_CONST(15)
+#define APBDMA_IRQ_STA_COP_0_CH15_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_COP_0_CH15_SHIFT)
+#define APBDMA_IRQ_STA_COP_0_CH15_RANGE                 15:15
+#define APBDMA_IRQ_STA_COP_0_CH15_WOFFSET                       0x0
+#define APBDMA_IRQ_STA_COP_0_CH15_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH15_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_COP_0_CH15_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH15_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH15_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_COP_0_CH15_ENABLE                        _MK_ENUM_CONST(1)
+
+// Gathers all the after-masking COP directed IRQ status bits from channel14 
+#define APBDMA_IRQ_STA_COP_0_CH14_SHIFT                 _MK_SHIFT_CONST(14)
+#define APBDMA_IRQ_STA_COP_0_CH14_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_COP_0_CH14_SHIFT)
+#define APBDMA_IRQ_STA_COP_0_CH14_RANGE                 14:14
+#define APBDMA_IRQ_STA_COP_0_CH14_WOFFSET                       0x0
+#define APBDMA_IRQ_STA_COP_0_CH14_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH14_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_COP_0_CH14_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH14_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH14_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_COP_0_CH14_ENABLE                        _MK_ENUM_CONST(1)
+
+// Gathers all the after-masking COP directed IRQ status bits from channel13 
+#define APBDMA_IRQ_STA_COP_0_CH13_SHIFT                 _MK_SHIFT_CONST(13)
+#define APBDMA_IRQ_STA_COP_0_CH13_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_COP_0_CH13_SHIFT)
+#define APBDMA_IRQ_STA_COP_0_CH13_RANGE                 13:13
+#define APBDMA_IRQ_STA_COP_0_CH13_WOFFSET                       0x0
+#define APBDMA_IRQ_STA_COP_0_CH13_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH13_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_COP_0_CH13_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH13_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH13_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_COP_0_CH13_ENABLE                        _MK_ENUM_CONST(1)
+
+// Gathers all the after-masking COP directed IRQ status bits from channel12 
+#define APBDMA_IRQ_STA_COP_0_CH12_SHIFT                 _MK_SHIFT_CONST(12)
+#define APBDMA_IRQ_STA_COP_0_CH12_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_COP_0_CH12_SHIFT)
+#define APBDMA_IRQ_STA_COP_0_CH12_RANGE                 12:12
+#define APBDMA_IRQ_STA_COP_0_CH12_WOFFSET                       0x0
+#define APBDMA_IRQ_STA_COP_0_CH12_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH12_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_COP_0_CH12_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH12_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH12_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_COP_0_CH12_ENABLE                        _MK_ENUM_CONST(1)
+
+// Gathers all the after-masking COP directed IRQ status bits from channel11 
+#define APBDMA_IRQ_STA_COP_0_CH11_SHIFT                 _MK_SHIFT_CONST(11)
+#define APBDMA_IRQ_STA_COP_0_CH11_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_COP_0_CH11_SHIFT)
+#define APBDMA_IRQ_STA_COP_0_CH11_RANGE                 11:11
+#define APBDMA_IRQ_STA_COP_0_CH11_WOFFSET                       0x0
+#define APBDMA_IRQ_STA_COP_0_CH11_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH11_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_COP_0_CH11_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH11_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH11_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_COP_0_CH11_ENABLE                        _MK_ENUM_CONST(1)
+
+// Gathers all the after-masking COP directed IRQ status bits from channel10 
+#define APBDMA_IRQ_STA_COP_0_CH10_SHIFT                 _MK_SHIFT_CONST(10)
+#define APBDMA_IRQ_STA_COP_0_CH10_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_COP_0_CH10_SHIFT)
+#define APBDMA_IRQ_STA_COP_0_CH10_RANGE                 10:10
+#define APBDMA_IRQ_STA_COP_0_CH10_WOFFSET                       0x0
+#define APBDMA_IRQ_STA_COP_0_CH10_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH10_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_COP_0_CH10_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH10_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH10_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_COP_0_CH10_ENABLE                        _MK_ENUM_CONST(1)
+
+// Gathers all the after-masking COP directed IRQ status bits from channel9 
+#define APBDMA_IRQ_STA_COP_0_CH9_SHIFT                  _MK_SHIFT_CONST(9)
+#define APBDMA_IRQ_STA_COP_0_CH9_FIELD                  (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_COP_0_CH9_SHIFT)
+#define APBDMA_IRQ_STA_COP_0_CH9_RANGE                  9:9
+#define APBDMA_IRQ_STA_COP_0_CH9_WOFFSET                        0x0
+#define APBDMA_IRQ_STA_COP_0_CH9_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH9_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_COP_0_CH9_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH9_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH9_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_COP_0_CH9_ENABLE                 _MK_ENUM_CONST(1)
+
+// Gathers all the after-masking COP directed IRQ status bits from channel8 
+#define APBDMA_IRQ_STA_COP_0_CH8_SHIFT                  _MK_SHIFT_CONST(8)
+#define APBDMA_IRQ_STA_COP_0_CH8_FIELD                  (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_COP_0_CH8_SHIFT)
+#define APBDMA_IRQ_STA_COP_0_CH8_RANGE                  8:8
+#define APBDMA_IRQ_STA_COP_0_CH8_WOFFSET                        0x0
+#define APBDMA_IRQ_STA_COP_0_CH8_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH8_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_COP_0_CH8_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH8_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH8_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_COP_0_CH8_ENABLE                 _MK_ENUM_CONST(1)
+
+// Gathers all the after-masking COP directed IRQ status bits from channel7 
+#define APBDMA_IRQ_STA_COP_0_CH7_SHIFT                  _MK_SHIFT_CONST(7)
+#define APBDMA_IRQ_STA_COP_0_CH7_FIELD                  (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_COP_0_CH7_SHIFT)
+#define APBDMA_IRQ_STA_COP_0_CH7_RANGE                  7:7
+#define APBDMA_IRQ_STA_COP_0_CH7_WOFFSET                        0x0
+#define APBDMA_IRQ_STA_COP_0_CH7_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH7_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_COP_0_CH7_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH7_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH7_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_COP_0_CH7_ENABLE                 _MK_ENUM_CONST(1)
+
+// Gathers all the after-masking COP directed IRQ status bits from channel6 
+#define APBDMA_IRQ_STA_COP_0_CH6_SHIFT                  _MK_SHIFT_CONST(6)
+#define APBDMA_IRQ_STA_COP_0_CH6_FIELD                  (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_COP_0_CH6_SHIFT)
+#define APBDMA_IRQ_STA_COP_0_CH6_RANGE                  6:6
+#define APBDMA_IRQ_STA_COP_0_CH6_WOFFSET                        0x0
+#define APBDMA_IRQ_STA_COP_0_CH6_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH6_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_COP_0_CH6_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH6_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH6_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_COP_0_CH6_ENABLE                 _MK_ENUM_CONST(1)
+
+// Gathers all the after-masking COP directed IRQ status bits from channel5 
+#define APBDMA_IRQ_STA_COP_0_CH5_SHIFT                  _MK_SHIFT_CONST(5)
+#define APBDMA_IRQ_STA_COP_0_CH5_FIELD                  (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_COP_0_CH5_SHIFT)
+#define APBDMA_IRQ_STA_COP_0_CH5_RANGE                  5:5
+#define APBDMA_IRQ_STA_COP_0_CH5_WOFFSET                        0x0
+#define APBDMA_IRQ_STA_COP_0_CH5_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH5_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_COP_0_CH5_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH5_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH5_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_COP_0_CH5_ENABLE                 _MK_ENUM_CONST(1)
+
+// Gathers all the after-masking COP directed IRQ status bits from channel4 
+#define APBDMA_IRQ_STA_COP_0_CH4_SHIFT                  _MK_SHIFT_CONST(4)
+#define APBDMA_IRQ_STA_COP_0_CH4_FIELD                  (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_COP_0_CH4_SHIFT)
+#define APBDMA_IRQ_STA_COP_0_CH4_RANGE                  4:4
+#define APBDMA_IRQ_STA_COP_0_CH4_WOFFSET                        0x0
+#define APBDMA_IRQ_STA_COP_0_CH4_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH4_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_COP_0_CH4_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH4_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH4_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_COP_0_CH4_ENABLE                 _MK_ENUM_CONST(1)
+
+// Gathers all the after-masking COP directed IRQ status bits from channel3 
+#define APBDMA_IRQ_STA_COP_0_CH3_SHIFT                  _MK_SHIFT_CONST(3)
+#define APBDMA_IRQ_STA_COP_0_CH3_FIELD                  (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_COP_0_CH3_SHIFT)
+#define APBDMA_IRQ_STA_COP_0_CH3_RANGE                  3:3
+#define APBDMA_IRQ_STA_COP_0_CH3_WOFFSET                        0x0
+#define APBDMA_IRQ_STA_COP_0_CH3_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH3_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_COP_0_CH3_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH3_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH3_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_COP_0_CH3_ENABLE                 _MK_ENUM_CONST(1)
+
+// Gathers all the after-masking COP directed IRQ status bits from channel2 
+#define APBDMA_IRQ_STA_COP_0_CH2_SHIFT                  _MK_SHIFT_CONST(2)
+#define APBDMA_IRQ_STA_COP_0_CH2_FIELD                  (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_COP_0_CH2_SHIFT)
+#define APBDMA_IRQ_STA_COP_0_CH2_RANGE                  2:2
+#define APBDMA_IRQ_STA_COP_0_CH2_WOFFSET                        0x0
+#define APBDMA_IRQ_STA_COP_0_CH2_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH2_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_COP_0_CH2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH2_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_COP_0_CH2_ENABLE                 _MK_ENUM_CONST(1)
+
+// Gathers all the after-masking COP directed IRQ status bits from channel1 
+#define APBDMA_IRQ_STA_COP_0_CH1_SHIFT                  _MK_SHIFT_CONST(1)
+#define APBDMA_IRQ_STA_COP_0_CH1_FIELD                  (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_COP_0_CH1_SHIFT)
+#define APBDMA_IRQ_STA_COP_0_CH1_RANGE                  1:1
+#define APBDMA_IRQ_STA_COP_0_CH1_WOFFSET                        0x0
+#define APBDMA_IRQ_STA_COP_0_CH1_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH1_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_COP_0_CH1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH1_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_COP_0_CH1_ENABLE                 _MK_ENUM_CONST(1)
+
+// Gathers all the after-masking COP directed IRQ status bits from channel0 
+#define APBDMA_IRQ_STA_COP_0_CH0_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDMA_IRQ_STA_COP_0_CH0_FIELD                  (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_COP_0_CH0_SHIFT)
+#define APBDMA_IRQ_STA_COP_0_CH0_RANGE                  0:0
+#define APBDMA_IRQ_STA_COP_0_CH0_WOFFSET                        0x0
+#define APBDMA_IRQ_STA_COP_0_CH0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH0_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_COP_0_CH0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH0_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_COP_0_CH0_ENABLE                 _MK_ENUM_CONST(1)
+
+
+// Register APBDMA_IRQ_MASK_0  
+#define APBDMA_IRQ_MASK_0                       _MK_ADDR_CONST(0x1c)
+#define APBDMA_IRQ_MASK_0_SECURE                        0x0
+#define APBDMA_IRQ_MASK_0_WORD_COUNT                    0x1
+#define APBDMA_IRQ_MASK_0_RESET_VAL                     _MK_MASK_CONST(0xffff)
+#define APBDMA_IRQ_MASK_0_RESET_MASK                    _MK_MASK_CONST(0xffff)
+#define APBDMA_IRQ_MASK_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_READ_MASK                     _MK_MASK_CONST(0xffff)
+#define APBDMA_IRQ_MASK_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+// Each bit allows the associated channel15 IRQ to propagate when '1' 
+#define APBDMA_IRQ_MASK_0_CH15_SHIFT                    _MK_SHIFT_CONST(15)
+#define APBDMA_IRQ_MASK_0_CH15_FIELD                    (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_0_CH15_SHIFT)
+#define APBDMA_IRQ_MASK_0_CH15_RANGE                    15:15
+#define APBDMA_IRQ_MASK_0_CH15_WOFFSET                  0x0
+#define APBDMA_IRQ_MASK_0_CH15_DEFAULT                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH15_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH15_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH15_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH15_DISABLE                  _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_0_CH15_ENABLE                   _MK_ENUM_CONST(1)
+
+// Each bit allows the associated channel14 IRQ to propagate when '1' 
+#define APBDMA_IRQ_MASK_0_CH14_SHIFT                    _MK_SHIFT_CONST(14)
+#define APBDMA_IRQ_MASK_0_CH14_FIELD                    (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_0_CH14_SHIFT)
+#define APBDMA_IRQ_MASK_0_CH14_RANGE                    14:14
+#define APBDMA_IRQ_MASK_0_CH14_WOFFSET                  0x0
+#define APBDMA_IRQ_MASK_0_CH14_DEFAULT                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH14_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH14_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH14_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH14_DISABLE                  _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_0_CH14_ENABLE                   _MK_ENUM_CONST(1)
+
+// Each bit allows the associated channel13 IRQ to propagate when '1' 
+#define APBDMA_IRQ_MASK_0_CH13_SHIFT                    _MK_SHIFT_CONST(13)
+#define APBDMA_IRQ_MASK_0_CH13_FIELD                    (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_0_CH13_SHIFT)
+#define APBDMA_IRQ_MASK_0_CH13_RANGE                    13:13
+#define APBDMA_IRQ_MASK_0_CH13_WOFFSET                  0x0
+#define APBDMA_IRQ_MASK_0_CH13_DEFAULT                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH13_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH13_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH13_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH13_DISABLE                  _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_0_CH13_ENABLE                   _MK_ENUM_CONST(1)
+
+// Each bit allows the associated channel12 IRQ to propagate when '1' 
+#define APBDMA_IRQ_MASK_0_CH12_SHIFT                    _MK_SHIFT_CONST(12)
+#define APBDMA_IRQ_MASK_0_CH12_FIELD                    (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_0_CH12_SHIFT)
+#define APBDMA_IRQ_MASK_0_CH12_RANGE                    12:12
+#define APBDMA_IRQ_MASK_0_CH12_WOFFSET                  0x0
+#define APBDMA_IRQ_MASK_0_CH12_DEFAULT                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH12_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH12_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH12_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH12_DISABLE                  _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_0_CH12_ENABLE                   _MK_ENUM_CONST(1)
+
+// Each bit allows the associated channel11 IRQ to propagate when '1' 
+#define APBDMA_IRQ_MASK_0_CH11_SHIFT                    _MK_SHIFT_CONST(11)
+#define APBDMA_IRQ_MASK_0_CH11_FIELD                    (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_0_CH11_SHIFT)
+#define APBDMA_IRQ_MASK_0_CH11_RANGE                    11:11
+#define APBDMA_IRQ_MASK_0_CH11_WOFFSET                  0x0
+#define APBDMA_IRQ_MASK_0_CH11_DEFAULT                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH11_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH11_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH11_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH11_DISABLE                  _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_0_CH11_ENABLE                   _MK_ENUM_CONST(1)
+
+// Each bit allows the associated channel10 IRQ to propagate when '1' 
+#define APBDMA_IRQ_MASK_0_CH10_SHIFT                    _MK_SHIFT_CONST(10)
+#define APBDMA_IRQ_MASK_0_CH10_FIELD                    (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_0_CH10_SHIFT)
+#define APBDMA_IRQ_MASK_0_CH10_RANGE                    10:10
+#define APBDMA_IRQ_MASK_0_CH10_WOFFSET                  0x0
+#define APBDMA_IRQ_MASK_0_CH10_DEFAULT                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH10_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH10_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH10_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH10_DISABLE                  _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_0_CH10_ENABLE                   _MK_ENUM_CONST(1)
+
+// Each bit allows the associated channel9 IRQ to propagate when '1' 
+#define APBDMA_IRQ_MASK_0_CH9_SHIFT                     _MK_SHIFT_CONST(9)
+#define APBDMA_IRQ_MASK_0_CH9_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_0_CH9_SHIFT)
+#define APBDMA_IRQ_MASK_0_CH9_RANGE                     9:9
+#define APBDMA_IRQ_MASK_0_CH9_WOFFSET                   0x0
+#define APBDMA_IRQ_MASK_0_CH9_DEFAULT                   _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH9_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH9_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH9_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH9_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_0_CH9_ENABLE                    _MK_ENUM_CONST(1)
+
+// Each bit allows the associated channel8 IRQ to propagate when '1' 
+#define APBDMA_IRQ_MASK_0_CH8_SHIFT                     _MK_SHIFT_CONST(8)
+#define APBDMA_IRQ_MASK_0_CH8_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_0_CH8_SHIFT)
+#define APBDMA_IRQ_MASK_0_CH8_RANGE                     8:8
+#define APBDMA_IRQ_MASK_0_CH8_WOFFSET                   0x0
+#define APBDMA_IRQ_MASK_0_CH8_DEFAULT                   _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH8_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH8_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH8_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH8_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_0_CH8_ENABLE                    _MK_ENUM_CONST(1)
+
+// Each bit allows the associated channel7 IRQ to propagate when '1' 
+#define APBDMA_IRQ_MASK_0_CH7_SHIFT                     _MK_SHIFT_CONST(7)
+#define APBDMA_IRQ_MASK_0_CH7_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_0_CH7_SHIFT)
+#define APBDMA_IRQ_MASK_0_CH7_RANGE                     7:7
+#define APBDMA_IRQ_MASK_0_CH7_WOFFSET                   0x0
+#define APBDMA_IRQ_MASK_0_CH7_DEFAULT                   _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH7_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH7_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH7_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH7_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_0_CH7_ENABLE                    _MK_ENUM_CONST(1)
+
+// Each bit allows the associated channel6 IRQ to propagate when '1' 
+#define APBDMA_IRQ_MASK_0_CH6_SHIFT                     _MK_SHIFT_CONST(6)
+#define APBDMA_IRQ_MASK_0_CH6_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_0_CH6_SHIFT)
+#define APBDMA_IRQ_MASK_0_CH6_RANGE                     6:6
+#define APBDMA_IRQ_MASK_0_CH6_WOFFSET                   0x0
+#define APBDMA_IRQ_MASK_0_CH6_DEFAULT                   _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH6_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH6_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH6_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH6_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_0_CH6_ENABLE                    _MK_ENUM_CONST(1)
+
+// Each bit allows the associated channel5 IRQ to propagate when '1' 
+#define APBDMA_IRQ_MASK_0_CH5_SHIFT                     _MK_SHIFT_CONST(5)
+#define APBDMA_IRQ_MASK_0_CH5_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_0_CH5_SHIFT)
+#define APBDMA_IRQ_MASK_0_CH5_RANGE                     5:5
+#define APBDMA_IRQ_MASK_0_CH5_WOFFSET                   0x0
+#define APBDMA_IRQ_MASK_0_CH5_DEFAULT                   _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH5_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH5_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH5_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH5_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_0_CH5_ENABLE                    _MK_ENUM_CONST(1)
+
+// Each bit allows the associated channel4 IRQ to propagate when '1' 
+#define APBDMA_IRQ_MASK_0_CH4_SHIFT                     _MK_SHIFT_CONST(4)
+#define APBDMA_IRQ_MASK_0_CH4_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_0_CH4_SHIFT)
+#define APBDMA_IRQ_MASK_0_CH4_RANGE                     4:4
+#define APBDMA_IRQ_MASK_0_CH4_WOFFSET                   0x0
+#define APBDMA_IRQ_MASK_0_CH4_DEFAULT                   _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH4_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH4_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH4_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH4_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_0_CH4_ENABLE                    _MK_ENUM_CONST(1)
+
+// Each bit allows the associated channel3 IRQ to propagate when '1' 
+#define APBDMA_IRQ_MASK_0_CH3_SHIFT                     _MK_SHIFT_CONST(3)
+#define APBDMA_IRQ_MASK_0_CH3_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_0_CH3_SHIFT)
+#define APBDMA_IRQ_MASK_0_CH3_RANGE                     3:3
+#define APBDMA_IRQ_MASK_0_CH3_WOFFSET                   0x0
+#define APBDMA_IRQ_MASK_0_CH3_DEFAULT                   _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH3_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH3_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH3_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH3_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_0_CH3_ENABLE                    _MK_ENUM_CONST(1)
+
+// Each bit allows the associated channel2 IRQ to propagate when '1' 
+#define APBDMA_IRQ_MASK_0_CH2_SHIFT                     _MK_SHIFT_CONST(2)
+#define APBDMA_IRQ_MASK_0_CH2_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_0_CH2_SHIFT)
+#define APBDMA_IRQ_MASK_0_CH2_RANGE                     2:2
+#define APBDMA_IRQ_MASK_0_CH2_WOFFSET                   0x0
+#define APBDMA_IRQ_MASK_0_CH2_DEFAULT                   _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH2_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH2_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_0_CH2_ENABLE                    _MK_ENUM_CONST(1)
+
+// Each bit allows the associated channel1 IRQ to propagate when '1' 
+#define APBDMA_IRQ_MASK_0_CH1_SHIFT                     _MK_SHIFT_CONST(1)
+#define APBDMA_IRQ_MASK_0_CH1_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_0_CH1_SHIFT)
+#define APBDMA_IRQ_MASK_0_CH1_RANGE                     1:1
+#define APBDMA_IRQ_MASK_0_CH1_WOFFSET                   0x0
+#define APBDMA_IRQ_MASK_0_CH1_DEFAULT                   _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH1_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH1_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_0_CH1_ENABLE                    _MK_ENUM_CONST(1)
+
+// Each bit allows the associated channel0 IRQ to propagate when '1' 
+#define APBDMA_IRQ_MASK_0_CH0_SHIFT                     _MK_SHIFT_CONST(0)
+#define APBDMA_IRQ_MASK_0_CH0_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_0_CH0_SHIFT)
+#define APBDMA_IRQ_MASK_0_CH0_RANGE                     0:0
+#define APBDMA_IRQ_MASK_0_CH0_WOFFSET                   0x0
+#define APBDMA_IRQ_MASK_0_CH0_DEFAULT                   _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH0_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH0_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_0_CH0_ENABLE                    _MK_ENUM_CONST(1)
+
+
+// Register APBDMA_IRQ_MASK_SET_0  
+#define APBDMA_IRQ_MASK_SET_0                   _MK_ADDR_CONST(0x20)
+#define APBDMA_IRQ_MASK_SET_0_SECURE                    0x0
+#define APBDMA_IRQ_MASK_SET_0_WORD_COUNT                        0x1
+#define APBDMA_IRQ_MASK_SET_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_RESET_MASK                        _MK_MASK_CONST(0xffff)
+#define APBDMA_IRQ_MASK_SET_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_READ_MASK                         _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_WRITE_MASK                        _MK_MASK_CONST(0xffff)
+// Sets the Mask Register
+#define APBDMA_IRQ_MASK_SET_0_CH15_SHIFT                        _MK_SHIFT_CONST(15)
+#define APBDMA_IRQ_MASK_SET_0_CH15_FIELD                        (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_SET_0_CH15_SHIFT)
+#define APBDMA_IRQ_MASK_SET_0_CH15_RANGE                        15:15
+#define APBDMA_IRQ_MASK_SET_0_CH15_WOFFSET                      0x0
+#define APBDMA_IRQ_MASK_SET_0_CH15_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH15_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_SET_0_CH15_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH15_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH15_DISABLE                      _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_SET_0_CH15_ENABLE                       _MK_ENUM_CONST(1)
+
+// Sets the Mask Register
+#define APBDMA_IRQ_MASK_SET_0_CH14_SHIFT                        _MK_SHIFT_CONST(14)
+#define APBDMA_IRQ_MASK_SET_0_CH14_FIELD                        (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_SET_0_CH14_SHIFT)
+#define APBDMA_IRQ_MASK_SET_0_CH14_RANGE                        14:14
+#define APBDMA_IRQ_MASK_SET_0_CH14_WOFFSET                      0x0
+#define APBDMA_IRQ_MASK_SET_0_CH14_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH14_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_SET_0_CH14_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH14_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH14_DISABLE                      _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_SET_0_CH14_ENABLE                       _MK_ENUM_CONST(1)
+
+// Sets the Mask Register
+#define APBDMA_IRQ_MASK_SET_0_CH13_SHIFT                        _MK_SHIFT_CONST(13)
+#define APBDMA_IRQ_MASK_SET_0_CH13_FIELD                        (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_SET_0_CH13_SHIFT)
+#define APBDMA_IRQ_MASK_SET_0_CH13_RANGE                        13:13
+#define APBDMA_IRQ_MASK_SET_0_CH13_WOFFSET                      0x0
+#define APBDMA_IRQ_MASK_SET_0_CH13_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH13_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_SET_0_CH13_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH13_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH13_DISABLE                      _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_SET_0_CH13_ENABLE                       _MK_ENUM_CONST(1)
+
+// Sets the Mask Register
+#define APBDMA_IRQ_MASK_SET_0_CH12_SHIFT                        _MK_SHIFT_CONST(12)
+#define APBDMA_IRQ_MASK_SET_0_CH12_FIELD                        (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_SET_0_CH12_SHIFT)
+#define APBDMA_IRQ_MASK_SET_0_CH12_RANGE                        12:12
+#define APBDMA_IRQ_MASK_SET_0_CH12_WOFFSET                      0x0
+#define APBDMA_IRQ_MASK_SET_0_CH12_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH12_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_SET_0_CH12_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH12_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH12_DISABLE                      _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_SET_0_CH12_ENABLE                       _MK_ENUM_CONST(1)
+
+// Sets the Mask Register
+#define APBDMA_IRQ_MASK_SET_0_CH11_SHIFT                        _MK_SHIFT_CONST(11)
+#define APBDMA_IRQ_MASK_SET_0_CH11_FIELD                        (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_SET_0_CH11_SHIFT)
+#define APBDMA_IRQ_MASK_SET_0_CH11_RANGE                        11:11
+#define APBDMA_IRQ_MASK_SET_0_CH11_WOFFSET                      0x0
+#define APBDMA_IRQ_MASK_SET_0_CH11_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH11_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_SET_0_CH11_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH11_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH11_DISABLE                      _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_SET_0_CH11_ENABLE                       _MK_ENUM_CONST(1)
+
+// Sets the Mask Register
+#define APBDMA_IRQ_MASK_SET_0_CH10_SHIFT                        _MK_SHIFT_CONST(10)
+#define APBDMA_IRQ_MASK_SET_0_CH10_FIELD                        (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_SET_0_CH10_SHIFT)
+#define APBDMA_IRQ_MASK_SET_0_CH10_RANGE                        10:10
+#define APBDMA_IRQ_MASK_SET_0_CH10_WOFFSET                      0x0
+#define APBDMA_IRQ_MASK_SET_0_CH10_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH10_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_SET_0_CH10_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH10_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH10_DISABLE                      _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_SET_0_CH10_ENABLE                       _MK_ENUM_CONST(1)
+
+// Sets the Mask Register
+#define APBDMA_IRQ_MASK_SET_0_CH9_SHIFT                 _MK_SHIFT_CONST(9)
+#define APBDMA_IRQ_MASK_SET_0_CH9_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_SET_0_CH9_SHIFT)
+#define APBDMA_IRQ_MASK_SET_0_CH9_RANGE                 9:9
+#define APBDMA_IRQ_MASK_SET_0_CH9_WOFFSET                       0x0
+#define APBDMA_IRQ_MASK_SET_0_CH9_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH9_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_SET_0_CH9_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH9_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH9_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_SET_0_CH9_ENABLE                        _MK_ENUM_CONST(1)
+
+// Sets the Mask Register
+#define APBDMA_IRQ_MASK_SET_0_CH8_SHIFT                 _MK_SHIFT_CONST(8)
+#define APBDMA_IRQ_MASK_SET_0_CH8_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_SET_0_CH8_SHIFT)
+#define APBDMA_IRQ_MASK_SET_0_CH8_RANGE                 8:8
+#define APBDMA_IRQ_MASK_SET_0_CH8_WOFFSET                       0x0
+#define APBDMA_IRQ_MASK_SET_0_CH8_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH8_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_SET_0_CH8_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH8_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH8_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_SET_0_CH8_ENABLE                        _MK_ENUM_CONST(1)
+
+// Sets the Mask Register
+#define APBDMA_IRQ_MASK_SET_0_CH7_SHIFT                 _MK_SHIFT_CONST(7)
+#define APBDMA_IRQ_MASK_SET_0_CH7_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_SET_0_CH7_SHIFT)
+#define APBDMA_IRQ_MASK_SET_0_CH7_RANGE                 7:7
+#define APBDMA_IRQ_MASK_SET_0_CH7_WOFFSET                       0x0
+#define APBDMA_IRQ_MASK_SET_0_CH7_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH7_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_SET_0_CH7_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH7_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH7_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_SET_0_CH7_ENABLE                        _MK_ENUM_CONST(1)
+
+// Sets the Mask Register
+#define APBDMA_IRQ_MASK_SET_0_CH6_SHIFT                 _MK_SHIFT_CONST(6)
+#define APBDMA_IRQ_MASK_SET_0_CH6_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_SET_0_CH6_SHIFT)
+#define APBDMA_IRQ_MASK_SET_0_CH6_RANGE                 6:6
+#define APBDMA_IRQ_MASK_SET_0_CH6_WOFFSET                       0x0
+#define APBDMA_IRQ_MASK_SET_0_CH6_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH6_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_SET_0_CH6_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH6_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH6_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_SET_0_CH6_ENABLE                        _MK_ENUM_CONST(1)
+
+// Sets the Mask Register
+#define APBDMA_IRQ_MASK_SET_0_CH5_SHIFT                 _MK_SHIFT_CONST(5)
+#define APBDMA_IRQ_MASK_SET_0_CH5_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_SET_0_CH5_SHIFT)
+#define APBDMA_IRQ_MASK_SET_0_CH5_RANGE                 5:5
+#define APBDMA_IRQ_MASK_SET_0_CH5_WOFFSET                       0x0
+#define APBDMA_IRQ_MASK_SET_0_CH5_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH5_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_SET_0_CH5_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH5_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH5_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_SET_0_CH5_ENABLE                        _MK_ENUM_CONST(1)
+
+// Sets the Mask Register
+#define APBDMA_IRQ_MASK_SET_0_CH4_SHIFT                 _MK_SHIFT_CONST(4)
+#define APBDMA_IRQ_MASK_SET_0_CH4_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_SET_0_CH4_SHIFT)
+#define APBDMA_IRQ_MASK_SET_0_CH4_RANGE                 4:4
+#define APBDMA_IRQ_MASK_SET_0_CH4_WOFFSET                       0x0
+#define APBDMA_IRQ_MASK_SET_0_CH4_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH4_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_SET_0_CH4_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH4_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH4_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_SET_0_CH4_ENABLE                        _MK_ENUM_CONST(1)
+
+// Sets the Mask Register
+#define APBDMA_IRQ_MASK_SET_0_CH3_SHIFT                 _MK_SHIFT_CONST(3)
+#define APBDMA_IRQ_MASK_SET_0_CH3_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_SET_0_CH3_SHIFT)
+#define APBDMA_IRQ_MASK_SET_0_CH3_RANGE                 3:3
+#define APBDMA_IRQ_MASK_SET_0_CH3_WOFFSET                       0x0
+#define APBDMA_IRQ_MASK_SET_0_CH3_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH3_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_SET_0_CH3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH3_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_SET_0_CH3_ENABLE                        _MK_ENUM_CONST(1)
+
+// Sets the Mask Register
+#define APBDMA_IRQ_MASK_SET_0_CH2_SHIFT                 _MK_SHIFT_CONST(2)
+#define APBDMA_IRQ_MASK_SET_0_CH2_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_SET_0_CH2_SHIFT)
+#define APBDMA_IRQ_MASK_SET_0_CH2_RANGE                 2:2
+#define APBDMA_IRQ_MASK_SET_0_CH2_WOFFSET                       0x0
+#define APBDMA_IRQ_MASK_SET_0_CH2_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH2_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_SET_0_CH2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH2_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_SET_0_CH2_ENABLE                        _MK_ENUM_CONST(1)
+
+// Sets the Mask Register
+#define APBDMA_IRQ_MASK_SET_0_CH1_SHIFT                 _MK_SHIFT_CONST(1)
+#define APBDMA_IRQ_MASK_SET_0_CH1_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_SET_0_CH1_SHIFT)
+#define APBDMA_IRQ_MASK_SET_0_CH1_RANGE                 1:1
+#define APBDMA_IRQ_MASK_SET_0_CH1_WOFFSET                       0x0
+#define APBDMA_IRQ_MASK_SET_0_CH1_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH1_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_SET_0_CH1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH1_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_SET_0_CH1_ENABLE                        _MK_ENUM_CONST(1)
+
+// Sets the Mask Register
+#define APBDMA_IRQ_MASK_SET_0_CH0_SHIFT                 _MK_SHIFT_CONST(0)
+#define APBDMA_IRQ_MASK_SET_0_CH0_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_SET_0_CH0_SHIFT)
+#define APBDMA_IRQ_MASK_SET_0_CH0_RANGE                 0:0
+#define APBDMA_IRQ_MASK_SET_0_CH0_WOFFSET                       0x0
+#define APBDMA_IRQ_MASK_SET_0_CH0_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH0_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_SET_0_CH0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH0_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_SET_0_CH0_ENABLE                        _MK_ENUM_CONST(1)
+
+
+// Register APBDMA_IRQ_MASK_CLR_0  
+#define APBDMA_IRQ_MASK_CLR_0                   _MK_ADDR_CONST(0x24)
+#define APBDMA_IRQ_MASK_CLR_0_SECURE                    0x0
+#define APBDMA_IRQ_MASK_CLR_0_WORD_COUNT                        0x1
+#define APBDMA_IRQ_MASK_CLR_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_RESET_MASK                        _MK_MASK_CONST(0xffff)
+#define APBDMA_IRQ_MASK_CLR_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_READ_MASK                         _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_WRITE_MASK                        _MK_MASK_CONST(0xffff)
+// Clears the Mask Register
+#define APBDMA_IRQ_MASK_CLR_0_CH15_SHIFT                        _MK_SHIFT_CONST(15)
+#define APBDMA_IRQ_MASK_CLR_0_CH15_FIELD                        (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_CLR_0_CH15_SHIFT)
+#define APBDMA_IRQ_MASK_CLR_0_CH15_RANGE                        15:15
+#define APBDMA_IRQ_MASK_CLR_0_CH15_WOFFSET                      0x0
+#define APBDMA_IRQ_MASK_CLR_0_CH15_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH15_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_CLR_0_CH15_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH15_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH15_DISABLE                      _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_CLR_0_CH15_ENABLE                       _MK_ENUM_CONST(1)
+
+// Clears the Mask Register
+#define APBDMA_IRQ_MASK_CLR_0_CH14_SHIFT                        _MK_SHIFT_CONST(14)
+#define APBDMA_IRQ_MASK_CLR_0_CH14_FIELD                        (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_CLR_0_CH14_SHIFT)
+#define APBDMA_IRQ_MASK_CLR_0_CH14_RANGE                        14:14
+#define APBDMA_IRQ_MASK_CLR_0_CH14_WOFFSET                      0x0
+#define APBDMA_IRQ_MASK_CLR_0_CH14_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH14_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_CLR_0_CH14_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH14_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH14_DISABLE                      _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_CLR_0_CH14_ENABLE                       _MK_ENUM_CONST(1)
+
+// Clears the Mask Register
+#define APBDMA_IRQ_MASK_CLR_0_CH13_SHIFT                        _MK_SHIFT_CONST(13)
+#define APBDMA_IRQ_MASK_CLR_0_CH13_FIELD                        (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_CLR_0_CH13_SHIFT)
+#define APBDMA_IRQ_MASK_CLR_0_CH13_RANGE                        13:13
+#define APBDMA_IRQ_MASK_CLR_0_CH13_WOFFSET                      0x0
+#define APBDMA_IRQ_MASK_CLR_0_CH13_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH13_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_CLR_0_CH13_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH13_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH13_DISABLE                      _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_CLR_0_CH13_ENABLE                       _MK_ENUM_CONST(1)
+
+// Clears the Mask Register
+#define APBDMA_IRQ_MASK_CLR_0_CH12_SHIFT                        _MK_SHIFT_CONST(12)
+#define APBDMA_IRQ_MASK_CLR_0_CH12_FIELD                        (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_CLR_0_CH12_SHIFT)
+#define APBDMA_IRQ_MASK_CLR_0_CH12_RANGE                        12:12
+#define APBDMA_IRQ_MASK_CLR_0_CH12_WOFFSET                      0x0
+#define APBDMA_IRQ_MASK_CLR_0_CH12_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH12_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_CLR_0_CH12_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH12_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH12_DISABLE                      _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_CLR_0_CH12_ENABLE                       _MK_ENUM_CONST(1)
+
+// Clears the Mask Register
+#define APBDMA_IRQ_MASK_CLR_0_CH11_SHIFT                        _MK_SHIFT_CONST(11)
+#define APBDMA_IRQ_MASK_CLR_0_CH11_FIELD                        (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_CLR_0_CH11_SHIFT)
+#define APBDMA_IRQ_MASK_CLR_0_CH11_RANGE                        11:11
+#define APBDMA_IRQ_MASK_CLR_0_CH11_WOFFSET                      0x0
+#define APBDMA_IRQ_MASK_CLR_0_CH11_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH11_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_CLR_0_CH11_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH11_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH11_DISABLE                      _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_CLR_0_CH11_ENABLE                       _MK_ENUM_CONST(1)
+
+// Clears the Mask Register
+#define APBDMA_IRQ_MASK_CLR_0_CH10_SHIFT                        _MK_SHIFT_CONST(10)
+#define APBDMA_IRQ_MASK_CLR_0_CH10_FIELD                        (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_CLR_0_CH10_SHIFT)
+#define APBDMA_IRQ_MASK_CLR_0_CH10_RANGE                        10:10
+#define APBDMA_IRQ_MASK_CLR_0_CH10_WOFFSET                      0x0
+#define APBDMA_IRQ_MASK_CLR_0_CH10_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH10_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_CLR_0_CH10_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH10_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH10_DISABLE                      _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_CLR_0_CH10_ENABLE                       _MK_ENUM_CONST(1)
+
+// Clears the Mask Register
+#define APBDMA_IRQ_MASK_CLR_0_CH9_SHIFT                 _MK_SHIFT_CONST(9)
+#define APBDMA_IRQ_MASK_CLR_0_CH9_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_CLR_0_CH9_SHIFT)
+#define APBDMA_IRQ_MASK_CLR_0_CH9_RANGE                 9:9
+#define APBDMA_IRQ_MASK_CLR_0_CH9_WOFFSET                       0x0
+#define APBDMA_IRQ_MASK_CLR_0_CH9_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH9_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_CLR_0_CH9_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH9_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH9_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_CLR_0_CH9_ENABLE                        _MK_ENUM_CONST(1)
+
+// Clears the Mask Register
+#define APBDMA_IRQ_MASK_CLR_0_CH8_SHIFT                 _MK_SHIFT_CONST(8)
+#define APBDMA_IRQ_MASK_CLR_0_CH8_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_CLR_0_CH8_SHIFT)
+#define APBDMA_IRQ_MASK_CLR_0_CH8_RANGE                 8:8
+#define APBDMA_IRQ_MASK_CLR_0_CH8_WOFFSET                       0x0
+#define APBDMA_IRQ_MASK_CLR_0_CH8_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH8_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_CLR_0_CH8_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH8_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH8_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_CLR_0_CH8_ENABLE                        _MK_ENUM_CONST(1)
+
+// Clears the Mask Register
+#define APBDMA_IRQ_MASK_CLR_0_CH7_SHIFT                 _MK_SHIFT_CONST(7)
+#define APBDMA_IRQ_MASK_CLR_0_CH7_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_CLR_0_CH7_SHIFT)
+#define APBDMA_IRQ_MASK_CLR_0_CH7_RANGE                 7:7
+#define APBDMA_IRQ_MASK_CLR_0_CH7_WOFFSET                       0x0
+#define APBDMA_IRQ_MASK_CLR_0_CH7_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH7_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_CLR_0_CH7_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH7_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH7_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_CLR_0_CH7_ENABLE                        _MK_ENUM_CONST(1)
+
+// Clears the Mask Register
+#define APBDMA_IRQ_MASK_CLR_0_CH6_SHIFT                 _MK_SHIFT_CONST(6)
+#define APBDMA_IRQ_MASK_CLR_0_CH6_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_CLR_0_CH6_SHIFT)
+#define APBDMA_IRQ_MASK_CLR_0_CH6_RANGE                 6:6
+#define APBDMA_IRQ_MASK_CLR_0_CH6_WOFFSET                       0x0
+#define APBDMA_IRQ_MASK_CLR_0_CH6_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH6_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_CLR_0_CH6_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH6_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH6_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_CLR_0_CH6_ENABLE                        _MK_ENUM_CONST(1)
+
+// Clears the Mask Register
+#define APBDMA_IRQ_MASK_CLR_0_CH5_SHIFT                 _MK_SHIFT_CONST(5)
+#define APBDMA_IRQ_MASK_CLR_0_CH5_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_CLR_0_CH5_SHIFT)
+#define APBDMA_IRQ_MASK_CLR_0_CH5_RANGE                 5:5
+#define APBDMA_IRQ_MASK_CLR_0_CH5_WOFFSET                       0x0
+#define APBDMA_IRQ_MASK_CLR_0_CH5_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH5_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_CLR_0_CH5_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH5_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH5_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_CLR_0_CH5_ENABLE                        _MK_ENUM_CONST(1)
+
+// Clears the Mask Register
+#define APBDMA_IRQ_MASK_CLR_0_CH4_SHIFT                 _MK_SHIFT_CONST(4)
+#define APBDMA_IRQ_MASK_CLR_0_CH4_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_CLR_0_CH4_SHIFT)
+#define APBDMA_IRQ_MASK_CLR_0_CH4_RANGE                 4:4
+#define APBDMA_IRQ_MASK_CLR_0_CH4_WOFFSET                       0x0
+#define APBDMA_IRQ_MASK_CLR_0_CH4_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH4_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_CLR_0_CH4_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH4_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH4_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_CLR_0_CH4_ENABLE                        _MK_ENUM_CONST(1)
+
+// Clears the Mask Register
+#define APBDMA_IRQ_MASK_CLR_0_CH3_SHIFT                 _MK_SHIFT_CONST(3)
+#define APBDMA_IRQ_MASK_CLR_0_CH3_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_CLR_0_CH3_SHIFT)
+#define APBDMA_IRQ_MASK_CLR_0_CH3_RANGE                 3:3
+#define APBDMA_IRQ_MASK_CLR_0_CH3_WOFFSET                       0x0
+#define APBDMA_IRQ_MASK_CLR_0_CH3_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH3_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_CLR_0_CH3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH3_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_CLR_0_CH3_ENABLE                        _MK_ENUM_CONST(1)
+
+// Clears the Mask Register
+#define APBDMA_IRQ_MASK_CLR_0_CH2_SHIFT                 _MK_SHIFT_CONST(2)
+#define APBDMA_IRQ_MASK_CLR_0_CH2_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_CLR_0_CH2_SHIFT)
+#define APBDMA_IRQ_MASK_CLR_0_CH2_RANGE                 2:2
+#define APBDMA_IRQ_MASK_CLR_0_CH2_WOFFSET                       0x0
+#define APBDMA_IRQ_MASK_CLR_0_CH2_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH2_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_CLR_0_CH2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH2_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_CLR_0_CH2_ENABLE                        _MK_ENUM_CONST(1)
+
+// Clears the Mask Register
+#define APBDMA_IRQ_MASK_CLR_0_CH1_SHIFT                 _MK_SHIFT_CONST(1)
+#define APBDMA_IRQ_MASK_CLR_0_CH1_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_CLR_0_CH1_SHIFT)
+#define APBDMA_IRQ_MASK_CLR_0_CH1_RANGE                 1:1
+#define APBDMA_IRQ_MASK_CLR_0_CH1_WOFFSET                       0x0
+#define APBDMA_IRQ_MASK_CLR_0_CH1_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH1_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_CLR_0_CH1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH1_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_CLR_0_CH1_ENABLE                        _MK_ENUM_CONST(1)
+
+// Clears the Mask Register
+#define APBDMA_IRQ_MASK_CLR_0_CH0_SHIFT                 _MK_SHIFT_CONST(0)
+#define APBDMA_IRQ_MASK_CLR_0_CH0_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_CLR_0_CH0_SHIFT)
+#define APBDMA_IRQ_MASK_CLR_0_CH0_RANGE                 0:0
+#define APBDMA_IRQ_MASK_CLR_0_CH0_WOFFSET                       0x0
+#define APBDMA_IRQ_MASK_CLR_0_CH0_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH0_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_CLR_0_CH0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH0_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_CLR_0_CH0_ENABLE                        _MK_ENUM_CONST(1)
+
+
+// Register APBDMA_TRIG_REG_0  
+#define APBDMA_TRIG_REG_0                       _MK_ADDR_CONST(0x28)
+#define APBDMA_TRIG_REG_0_SECURE                        0x0
+#define APBDMA_TRIG_REG_0_WORD_COUNT                    0x1
+#define APBDMA_TRIG_REG_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_RESET_MASK                    _MK_MASK_CONST(0x1fffffe)
+#define APBDMA_TRIG_REG_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_READ_MASK                     _MK_MASK_CONST(0x1fffffe)
+#define APBDMA_TRIG_REG_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+// EOC-15 Initiated DMA Request after transfer completion 
+#define APBDMA_TRIG_REG_0_APB_15_SHIFT                  _MK_SHIFT_CONST(24)
+#define APBDMA_TRIG_REG_0_APB_15_FIELD                  (_MK_MASK_CONST(0x1) << APBDMA_TRIG_REG_0_APB_15_SHIFT)
+#define APBDMA_TRIG_REG_0_APB_15_RANGE                  24:24
+#define APBDMA_TRIG_REG_0_APB_15_WOFFSET                        0x0
+#define APBDMA_TRIG_REG_0_APB_15_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_15_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMA_TRIG_REG_0_APB_15_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_15_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_15_NOT_ACTIVE                     _MK_ENUM_CONST(0)
+#define APBDMA_TRIG_REG_0_APB_15_ACTIVE                 _MK_ENUM_CONST(1)
+
+// EOC-14 Initiated DMA Request after transfer completion
+#define APBDMA_TRIG_REG_0_APB_14_SHIFT                  _MK_SHIFT_CONST(23)
+#define APBDMA_TRIG_REG_0_APB_14_FIELD                  (_MK_MASK_CONST(0x1) << APBDMA_TRIG_REG_0_APB_14_SHIFT)
+#define APBDMA_TRIG_REG_0_APB_14_RANGE                  23:23
+#define APBDMA_TRIG_REG_0_APB_14_WOFFSET                        0x0
+#define APBDMA_TRIG_REG_0_APB_14_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_14_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMA_TRIG_REG_0_APB_14_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_14_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_14_NOT_ACTIVE                     _MK_ENUM_CONST(0)
+#define APBDMA_TRIG_REG_0_APB_14_ACTIVE                 _MK_ENUM_CONST(1)
+
+// EOC-13 Initiated DMA Request after transfer completion
+#define APBDMA_TRIG_REG_0_APB_13_SHIFT                  _MK_SHIFT_CONST(22)
+#define APBDMA_TRIG_REG_0_APB_13_FIELD                  (_MK_MASK_CONST(0x1) << APBDMA_TRIG_REG_0_APB_13_SHIFT)
+#define APBDMA_TRIG_REG_0_APB_13_RANGE                  22:22
+#define APBDMA_TRIG_REG_0_APB_13_WOFFSET                        0x0
+#define APBDMA_TRIG_REG_0_APB_13_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_13_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMA_TRIG_REG_0_APB_13_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_13_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_13_NOT_ACTIVE                     _MK_ENUM_CONST(0)
+#define APBDMA_TRIG_REG_0_APB_13_ACTIVE                 _MK_ENUM_CONST(1)
+
+// EOC-12 Initiated DMA Request after transfer completion
+#define APBDMA_TRIG_REG_0_APB_12_SHIFT                  _MK_SHIFT_CONST(21)
+#define APBDMA_TRIG_REG_0_APB_12_FIELD                  (_MK_MASK_CONST(0x1) << APBDMA_TRIG_REG_0_APB_12_SHIFT)
+#define APBDMA_TRIG_REG_0_APB_12_RANGE                  21:21
+#define APBDMA_TRIG_REG_0_APB_12_WOFFSET                        0x0
+#define APBDMA_TRIG_REG_0_APB_12_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_12_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMA_TRIG_REG_0_APB_12_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_12_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_12_NOT_ACTIVE                     _MK_ENUM_CONST(0)
+#define APBDMA_TRIG_REG_0_APB_12_ACTIVE                 _MK_ENUM_CONST(1)
+
+// EOC-11 Initiated DMA Request after transfer completion
+#define APBDMA_TRIG_REG_0_APB_11_SHIFT                  _MK_SHIFT_CONST(20)
+#define APBDMA_TRIG_REG_0_APB_11_FIELD                  (_MK_MASK_CONST(0x1) << APBDMA_TRIG_REG_0_APB_11_SHIFT)
+#define APBDMA_TRIG_REG_0_APB_11_RANGE                  20:20
+#define APBDMA_TRIG_REG_0_APB_11_WOFFSET                        0x0
+#define APBDMA_TRIG_REG_0_APB_11_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_11_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMA_TRIG_REG_0_APB_11_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_11_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_11_NOT_ACTIVE                     _MK_ENUM_CONST(0)
+#define APBDMA_TRIG_REG_0_APB_11_ACTIVE                 _MK_ENUM_CONST(1)
+
+// EOC-10 Initiated DMA Request after transfer completion
+#define APBDMA_TRIG_REG_0_APB_10_SHIFT                  _MK_SHIFT_CONST(19)
+#define APBDMA_TRIG_REG_0_APB_10_FIELD                  (_MK_MASK_CONST(0x1) << APBDMA_TRIG_REG_0_APB_10_SHIFT)
+#define APBDMA_TRIG_REG_0_APB_10_RANGE                  19:19
+#define APBDMA_TRIG_REG_0_APB_10_WOFFSET                        0x0
+#define APBDMA_TRIG_REG_0_APB_10_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_10_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMA_TRIG_REG_0_APB_10_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_10_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_10_NOT_ACTIVE                     _MK_ENUM_CONST(0)
+#define APBDMA_TRIG_REG_0_APB_10_ACTIVE                 _MK_ENUM_CONST(1)
+
+// EOC-9 Initiated DMA Request after transfer completion
+#define APBDMA_TRIG_REG_0_APB_9_SHIFT                   _MK_SHIFT_CONST(18)
+#define APBDMA_TRIG_REG_0_APB_9_FIELD                   (_MK_MASK_CONST(0x1) << APBDMA_TRIG_REG_0_APB_9_SHIFT)
+#define APBDMA_TRIG_REG_0_APB_9_RANGE                   18:18
+#define APBDMA_TRIG_REG_0_APB_9_WOFFSET                 0x0
+#define APBDMA_TRIG_REG_0_APB_9_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_9_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMA_TRIG_REG_0_APB_9_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_9_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_9_NOT_ACTIVE                      _MK_ENUM_CONST(0)
+#define APBDMA_TRIG_REG_0_APB_9_ACTIVE                  _MK_ENUM_CONST(1)
+
+// EOC-8 Initiated DMA Request after transfer completion
+#define APBDMA_TRIG_REG_0_APB_8_SHIFT                   _MK_SHIFT_CONST(17)
+#define APBDMA_TRIG_REG_0_APB_8_FIELD                   (_MK_MASK_CONST(0x1) << APBDMA_TRIG_REG_0_APB_8_SHIFT)
+#define APBDMA_TRIG_REG_0_APB_8_RANGE                   17:17
+#define APBDMA_TRIG_REG_0_APB_8_WOFFSET                 0x0
+#define APBDMA_TRIG_REG_0_APB_8_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_8_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMA_TRIG_REG_0_APB_8_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_8_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_8_NOT_ACTIVE                      _MK_ENUM_CONST(0)
+#define APBDMA_TRIG_REG_0_APB_8_ACTIVE                  _MK_ENUM_CONST(1)
+
+// EOC-7 Initiated DMA Request after transfer completion
+#define APBDMA_TRIG_REG_0_APB_7_SHIFT                   _MK_SHIFT_CONST(16)
+#define APBDMA_TRIG_REG_0_APB_7_FIELD                   (_MK_MASK_CONST(0x1) << APBDMA_TRIG_REG_0_APB_7_SHIFT)
+#define APBDMA_TRIG_REG_0_APB_7_RANGE                   16:16
+#define APBDMA_TRIG_REG_0_APB_7_WOFFSET                 0x0
+#define APBDMA_TRIG_REG_0_APB_7_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_7_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMA_TRIG_REG_0_APB_7_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_7_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_7_NOT_ACTIVE                      _MK_ENUM_CONST(0)
+#define APBDMA_TRIG_REG_0_APB_7_ACTIVE                  _MK_ENUM_CONST(1)
+
+// EOC-6 Initiated DMA Request after transfer completion
+#define APBDMA_TRIG_REG_0_APB_6_SHIFT                   _MK_SHIFT_CONST(15)
+#define APBDMA_TRIG_REG_0_APB_6_FIELD                   (_MK_MASK_CONST(0x1) << APBDMA_TRIG_REG_0_APB_6_SHIFT)
+#define APBDMA_TRIG_REG_0_APB_6_RANGE                   15:15
+#define APBDMA_TRIG_REG_0_APB_6_WOFFSET                 0x0
+#define APBDMA_TRIG_REG_0_APB_6_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_6_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMA_TRIG_REG_0_APB_6_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_6_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_6_NOT_ACTIVE                      _MK_ENUM_CONST(0)
+#define APBDMA_TRIG_REG_0_APB_6_ACTIVE                  _MK_ENUM_CONST(1)
+
+// EOC-5 Initiated DMA Request after transfer completion
+#define APBDMA_TRIG_REG_0_APB_5_SHIFT                   _MK_SHIFT_CONST(14)
+#define APBDMA_TRIG_REG_0_APB_5_FIELD                   (_MK_MASK_CONST(0x1) << APBDMA_TRIG_REG_0_APB_5_SHIFT)
+#define APBDMA_TRIG_REG_0_APB_5_RANGE                   14:14
+#define APBDMA_TRIG_REG_0_APB_5_WOFFSET                 0x0
+#define APBDMA_TRIG_REG_0_APB_5_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_5_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMA_TRIG_REG_0_APB_5_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_5_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_5_NOT_ACTIVE                      _MK_ENUM_CONST(0)
+#define APBDMA_TRIG_REG_0_APB_5_ACTIVE                  _MK_ENUM_CONST(1)
+
+// EOC-4 Initiated DMA Request after transfer completion
+#define APBDMA_TRIG_REG_0_APB_4_SHIFT                   _MK_SHIFT_CONST(13)
+#define APBDMA_TRIG_REG_0_APB_4_FIELD                   (_MK_MASK_CONST(0x1) << APBDMA_TRIG_REG_0_APB_4_SHIFT)
+#define APBDMA_TRIG_REG_0_APB_4_RANGE                   13:13
+#define APBDMA_TRIG_REG_0_APB_4_WOFFSET                 0x0
+#define APBDMA_TRIG_REG_0_APB_4_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_4_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMA_TRIG_REG_0_APB_4_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_4_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_4_NOT_ACTIVE                      _MK_ENUM_CONST(0)
+#define APBDMA_TRIG_REG_0_APB_4_ACTIVE                  _MK_ENUM_CONST(1)
+
+// EOC-3 Initiated DMA Request after transfer completion
+#define APBDMA_TRIG_REG_0_APB_3_SHIFT                   _MK_SHIFT_CONST(12)
+#define APBDMA_TRIG_REG_0_APB_3_FIELD                   (_MK_MASK_CONST(0x1) << APBDMA_TRIG_REG_0_APB_3_SHIFT)
+#define APBDMA_TRIG_REG_0_APB_3_RANGE                   12:12
+#define APBDMA_TRIG_REG_0_APB_3_WOFFSET                 0x0
+#define APBDMA_TRIG_REG_0_APB_3_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_3_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMA_TRIG_REG_0_APB_3_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_3_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_3_NOT_ACTIVE                      _MK_ENUM_CONST(0)
+#define APBDMA_TRIG_REG_0_APB_3_ACTIVE                  _MK_ENUM_CONST(1)
+
+// EOC-2 Initiated DMA Request after transfer completion
+#define APBDMA_TRIG_REG_0_APB_2_SHIFT                   _MK_SHIFT_CONST(11)
+#define APBDMA_TRIG_REG_0_APB_2_FIELD                   (_MK_MASK_CONST(0x1) << APBDMA_TRIG_REG_0_APB_2_SHIFT)
+#define APBDMA_TRIG_REG_0_APB_2_RANGE                   11:11
+#define APBDMA_TRIG_REG_0_APB_2_WOFFSET                 0x0
+#define APBDMA_TRIG_REG_0_APB_2_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_2_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMA_TRIG_REG_0_APB_2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_2_NOT_ACTIVE                      _MK_ENUM_CONST(0)
+#define APBDMA_TRIG_REG_0_APB_2_ACTIVE                  _MK_ENUM_CONST(1)
+
+// EOC-1 Initiated DMA Request after transfer completion
+#define APBDMA_TRIG_REG_0_APB_1_SHIFT                   _MK_SHIFT_CONST(10)
+#define APBDMA_TRIG_REG_0_APB_1_FIELD                   (_MK_MASK_CONST(0x1) << APBDMA_TRIG_REG_0_APB_1_SHIFT)
+#define APBDMA_TRIG_REG_0_APB_1_RANGE                   10:10
+#define APBDMA_TRIG_REG_0_APB_1_WOFFSET                 0x0
+#define APBDMA_TRIG_REG_0_APB_1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMA_TRIG_REG_0_APB_1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_1_NOT_ACTIVE                      _MK_ENUM_CONST(0)
+#define APBDMA_TRIG_REG_0_APB_1_ACTIVE                  _MK_ENUM_CONST(1)
+
+// EOC-0 Initiated DMA Request after transfer completion
+#define APBDMA_TRIG_REG_0_APB_0_SHIFT                   _MK_SHIFT_CONST(9)
+#define APBDMA_TRIG_REG_0_APB_0_FIELD                   (_MK_MASK_CONST(0x1) << APBDMA_TRIG_REG_0_APB_0_SHIFT)
+#define APBDMA_TRIG_REG_0_APB_0_RANGE                   9:9
+#define APBDMA_TRIG_REG_0_APB_0_WOFFSET                 0x0
+#define APBDMA_TRIG_REG_0_APB_0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMA_TRIG_REG_0_APB_0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_0_NOT_ACTIVE                      _MK_ENUM_CONST(0)
+#define APBDMA_TRIG_REG_0_APB_0_ACTIVE                  _MK_ENUM_CONST(1)
+
+// Trigger select from Timer (Hardware initiated DMA request) 
+#define APBDMA_TRIG_REG_0_TMR2_SHIFT                    _MK_SHIFT_CONST(8)
+#define APBDMA_TRIG_REG_0_TMR2_FIELD                    (_MK_MASK_CONST(0x1) << APBDMA_TRIG_REG_0_TMR2_SHIFT)
+#define APBDMA_TRIG_REG_0_TMR2_RANGE                    8:8
+#define APBDMA_TRIG_REG_0_TMR2_WOFFSET                  0x0
+#define APBDMA_TRIG_REG_0_TMR2_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_TMR2_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMA_TRIG_REG_0_TMR2_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_TMR2_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_TMR2_NOT_ACTIVE                       _MK_ENUM_CONST(0)
+#define APBDMA_TRIG_REG_0_TMR2_ACTIVE                   _MK_ENUM_CONST(1)
+
+// Trigger select from Timer (Hardware initiated DMA request) 
+#define APBDMA_TRIG_REG_0_TMR1_SHIFT                    _MK_SHIFT_CONST(7)
+#define APBDMA_TRIG_REG_0_TMR1_FIELD                    (_MK_MASK_CONST(0x1) << APBDMA_TRIG_REG_0_TMR1_SHIFT)
+#define APBDMA_TRIG_REG_0_TMR1_RANGE                    7:7
+#define APBDMA_TRIG_REG_0_TMR1_WOFFSET                  0x0
+#define APBDMA_TRIG_REG_0_TMR1_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_TMR1_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMA_TRIG_REG_0_TMR1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_TMR1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_TMR1_NOT_ACTIVE                       _MK_ENUM_CONST(0)
+#define APBDMA_TRIG_REG_0_TMR1_ACTIVE                   _MK_ENUM_CONST(1)
+
+// XRQ.B (GPIOB) (Hardware initiated DMA request) 
+#define APBDMA_TRIG_REG_0_XRQ_B_SHIFT                   _MK_SHIFT_CONST(6)
+#define APBDMA_TRIG_REG_0_XRQ_B_FIELD                   (_MK_MASK_CONST(0x1) << APBDMA_TRIG_REG_0_XRQ_B_SHIFT)
+#define APBDMA_TRIG_REG_0_XRQ_B_RANGE                   6:6
+#define APBDMA_TRIG_REG_0_XRQ_B_WOFFSET                 0x0
+#define APBDMA_TRIG_REG_0_XRQ_B_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_XRQ_B_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMA_TRIG_REG_0_XRQ_B_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_XRQ_B_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_XRQ_B_NOT_ACTIVE                      _MK_ENUM_CONST(0)
+#define APBDMA_TRIG_REG_0_XRQ_B_ACTIVE                  _MK_ENUM_CONST(1)
+
+// XRQ.A (GPIOA) (Hardware initiated DMA request) 
+#define APBDMA_TRIG_REG_0_XRQ_A_SHIFT                   _MK_SHIFT_CONST(5)
+#define APBDMA_TRIG_REG_0_XRQ_A_FIELD                   (_MK_MASK_CONST(0x1) << APBDMA_TRIG_REG_0_XRQ_A_SHIFT)
+#define APBDMA_TRIG_REG_0_XRQ_A_RANGE                   5:5
+#define APBDMA_TRIG_REG_0_XRQ_A_WOFFSET                 0x0
+#define APBDMA_TRIG_REG_0_XRQ_A_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_XRQ_A_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMA_TRIG_REG_0_XRQ_A_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_XRQ_A_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_XRQ_A_NOT_ACTIVE                      _MK_ENUM_CONST(0)
+#define APBDMA_TRIG_REG_0_XRQ_A_ACTIVE                  _MK_ENUM_CONST(1)
+
+// Semaphore requests SW initiated DMA request
+#define APBDMA_TRIG_REG_0_SMP_27_SHIFT                  _MK_SHIFT_CONST(4)
+#define APBDMA_TRIG_REG_0_SMP_27_FIELD                  (_MK_MASK_CONST(0x1) << APBDMA_TRIG_REG_0_SMP_27_SHIFT)
+#define APBDMA_TRIG_REG_0_SMP_27_RANGE                  4:4
+#define APBDMA_TRIG_REG_0_SMP_27_WOFFSET                        0x0
+#define APBDMA_TRIG_REG_0_SMP_27_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_SMP_27_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMA_TRIG_REG_0_SMP_27_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_SMP_27_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_SMP_27_NOT_ACTIVE                     _MK_ENUM_CONST(0)
+#define APBDMA_TRIG_REG_0_SMP_27_ACTIVE                 _MK_ENUM_CONST(1)
+
+// Semaphore requests SW initiated DMA request 
+#define APBDMA_TRIG_REG_0_SMP_26_SHIFT                  _MK_SHIFT_CONST(3)
+#define APBDMA_TRIG_REG_0_SMP_26_FIELD                  (_MK_MASK_CONST(0x1) << APBDMA_TRIG_REG_0_SMP_26_SHIFT)
+#define APBDMA_TRIG_REG_0_SMP_26_RANGE                  3:3
+#define APBDMA_TRIG_REG_0_SMP_26_WOFFSET                        0x0
+#define APBDMA_TRIG_REG_0_SMP_26_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_SMP_26_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMA_TRIG_REG_0_SMP_26_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_SMP_26_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_SMP_26_NOT_ACTIVE                     _MK_ENUM_CONST(0)
+#define APBDMA_TRIG_REG_0_SMP_26_ACTIVE                 _MK_ENUM_CONST(1)
+
+// Semaphore requests SW initiated DMA request 
+#define APBDMA_TRIG_REG_0_SMP_25_SHIFT                  _MK_SHIFT_CONST(2)
+#define APBDMA_TRIG_REG_0_SMP_25_FIELD                  (_MK_MASK_CONST(0x1) << APBDMA_TRIG_REG_0_SMP_25_SHIFT)
+#define APBDMA_TRIG_REG_0_SMP_25_RANGE                  2:2
+#define APBDMA_TRIG_REG_0_SMP_25_WOFFSET                        0x0
+#define APBDMA_TRIG_REG_0_SMP_25_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_SMP_25_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMA_TRIG_REG_0_SMP_25_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_SMP_25_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_SMP_25_NOT_ACTIVE                     _MK_ENUM_CONST(0)
+#define APBDMA_TRIG_REG_0_SMP_25_ACTIVE                 _MK_ENUM_CONST(1)
+
+// Semaphore requests SW initiated DMA request 
+#define APBDMA_TRIG_REG_0_SMP_24_SHIFT                  _MK_SHIFT_CONST(1)
+#define APBDMA_TRIG_REG_0_SMP_24_FIELD                  (_MK_MASK_CONST(0x1) << APBDMA_TRIG_REG_0_SMP_24_SHIFT)
+#define APBDMA_TRIG_REG_0_SMP_24_RANGE                  1:1
+#define APBDMA_TRIG_REG_0_SMP_24_WOFFSET                        0x0
+#define APBDMA_TRIG_REG_0_SMP_24_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_SMP_24_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMA_TRIG_REG_0_SMP_24_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_SMP_24_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_SMP_24_NOT_ACTIVE                     _MK_ENUM_CONST(0)
+#define APBDMA_TRIG_REG_0_SMP_24_ACTIVE                 _MK_ENUM_CONST(1)
+
+
+//
+// REGISTER LIST
+//
+#define LIST_ARAPBDMA_REGS(_op_) \
+_op_(APBDMA_COMMAND_0) \
+_op_(APBDMA_STATUS_0) \
+_op_(APBDMA_REQUESTORS_TX_0) \
+_op_(APBDMA_REQUESTORS_RX_0) \
+_op_(APBDMA_CNTRL_REG_0) \
+_op_(APBDMA_IRQ_STA_CPU_0) \
+_op_(APBDMA_IRQ_STA_COP_0) \
+_op_(APBDMA_IRQ_MASK_0) \
+_op_(APBDMA_IRQ_MASK_SET_0) \
+_op_(APBDMA_IRQ_MASK_CLR_0) \
+_op_(APBDMA_TRIG_REG_0)
+
+
+//
+// ADDRESS SPACES
+//
+
+#define BASE_ADDRESS_APBDMA     0x00000000
+
+//
+// ARAPBDMA REGISTER BANKS
+//
+
+#define APBDMA0_FIRST_REG 0x0000 // APBDMA_COMMAND_0
+#define APBDMA0_LAST_REG 0x0028 // APBDMA_TRIG_REG_0
+
+#ifndef _MK_SHIFT_CONST
+  #define _MK_SHIFT_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_MASK_CONST
+  #define _MK_MASK_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_ENUM_CONST
+  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
+#endif
+#ifndef _MK_ADDR_CONST
+  #define _MK_ADDR_CONST(_constant_) _constant_
+#endif
+
+#endif // ifndef ___ARAPBDMA_H_INC_
diff --git a/arch/arm/mach-tegra/include/ap20/arapbdmachan.h b/arch/arm/mach-tegra/include/ap20/arapbdmachan.h
new file mode 100644
index 000000000000..12092fabf195
--- /dev/null
+++ b/arch/arm/mach-tegra/include/ap20/arapbdmachan.h
@@ -0,0 +1,7087 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+//
+// DO NOT EDIT - generated by simspec!
+//
+
+#ifndef ___ARAPBDMACHAN_H_INC_
+#define ___ARAPBDMACHAN_H_INC_
+
+// Register APBDMACHAN_CHANNEL_0_CSR_0  
+#define APBDMACHAN_CHANNEL_0_CSR_0                      _MK_ADDR_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_SECURE                       0x0
+#define APBDMACHAN_CHANNEL_0_CSR_0_WORD_COUNT                   0x1
+#define APBDMACHAN_CHANNEL_0_CSR_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_RESET_MASK                   _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_0_CSR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_READ_MASK                    _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_0_CSR_0_WRITE_MASK                   _MK_MASK_CONST(0xfffffffc)
+// Enables DMA channel transfer 
+#define APBDMACHAN_CHANNEL_0_CSR_0_ENB_SHIFT                    _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_0_CSR_0_ENB_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_0_CSR_0_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_0_CSR_0_ENB_RANGE                    31:31
+#define APBDMACHAN_CHANNEL_0_CSR_0_ENB_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_0_CSR_0_ENB_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_ENB_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_0_CSR_0_ENB_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_ENB_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_ENB_DISABLE                  _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_ENB_ENABLE                   _MK_ENUM_CONST(1)
+
+// Interrupts when DMA Block Transfer Completes 
+#define APBDMACHAN_CHANNEL_0_CSR_0_IE_EOC_SHIFT                 _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_0_CSR_0_IE_EOC_FIELD                 (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_0_CSR_0_IE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_0_CSR_0_IE_EOC_RANGE                 30:30
+#define APBDMACHAN_CHANNEL_0_CSR_0_IE_EOC_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_0_CSR_0_IE_EOC_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_IE_EOC_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_0_CSR_0_IE_EOC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_IE_EOC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_IE_EOC_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_IE_EOC_ENABLE                        _MK_ENUM_CONST(1)
+
+// Holds this Processor until DMA Block Transfer Completes 
+#define APBDMACHAN_CHANNEL_0_CSR_0_HOLD_SHIFT                   _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_0_CSR_0_HOLD_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_0_CSR_0_HOLD_SHIFT)
+#define APBDMACHAN_CHANNEL_0_CSR_0_HOLD_RANGE                   29:29
+#define APBDMACHAN_CHANNEL_0_CSR_0_HOLD_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_0_CSR_0_HOLD_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_HOLD_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_0_CSR_0_HOLD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_HOLD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_HOLD_DISABLE                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_HOLD_ENABLE                  _MK_ENUM_CONST(1)
+
+//DMA Transfer Direction 1 = AHB read to APB write 0 = APB read to AHB write
+#define APBDMACHAN_CHANNEL_0_CSR_0_DIR_SHIFT                    _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_0_CSR_0_DIR_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_0_CSR_0_DIR_SHIFT)
+#define APBDMACHAN_CHANNEL_0_CSR_0_DIR_RANGE                    28:28
+#define APBDMACHAN_CHANNEL_0_CSR_0_DIR_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_0_CSR_0_DIR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_DIR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_0_CSR_0_DIR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_DIR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_DIR_AHB_WRITE                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_DIR_AHB_READ                 _MK_ENUM_CONST(1)
+
+// Run Once or Run Multiple Mode (Allow Retriggering of this Channel) 1 = Run for One Block Transfer 0 = Run for Multiple Block Transfer
+#define APBDMACHAN_CHANNEL_0_CSR_0_ONCE_SHIFT                   _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_0_CSR_0_ONCE_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_0_CSR_0_ONCE_SHIFT)
+#define APBDMACHAN_CHANNEL_0_CSR_0_ONCE_RANGE                   27:27
+#define APBDMACHAN_CHANNEL_0_CSR_0_ONCE_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_0_CSR_0_ONCE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_ONCE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_0_CSR_0_ONCE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_ONCE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_ONCE_MULTIPLE_BLOCK                  _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_ONCE_SINGLE_BLOCK                    _MK_ENUM_CONST(1)
+
+// Enable on Non-Zero Value
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_SHIFT                       _MK_SHIFT_CONST(22)
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_FIELD                       (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_RANGE                       26:22
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_NA1                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_SMP24                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_SMP25                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_SMP26                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_SMP27                       _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_XRQ_A                       _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_XRQ_B                       _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_TMR1                        _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_TMR2                        _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_APB_0                       _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_APB_1                       _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_APB_2                       _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_APB_3                       _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_APB_4                       _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_APB_5                       _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_APB_6                       _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_APB_7                       _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_APB_8                       _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_APB_9                       _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_APB_10                      _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_APB_11                      _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_APB_12                      _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_APB_13                      _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_APB_14                      _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_APB_15                      _MK_ENUM_CONST(24)
+
+// Flow Control Enable (Synchronize Burst Transfers) 1 = Link to DRQ source 0 = Independent of DRQ request
+#define APBDMACHAN_CHANNEL_0_CSR_0_FLOW_SHIFT                   _MK_SHIFT_CONST(21)
+#define APBDMACHAN_CHANNEL_0_CSR_0_FLOW_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_0_CSR_0_FLOW_SHIFT)
+#define APBDMACHAN_CHANNEL_0_CSR_0_FLOW_RANGE                   21:21
+#define APBDMACHAN_CHANNEL_0_CSR_0_FLOW_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_0_CSR_0_FLOW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_FLOW_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_0_CSR_0_FLOW_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_FLOW_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_FLOW_DISABLE                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_FLOW_ENABLE                  _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_SHIFT                        _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_FIELD                        (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_RANGE                        20:16
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_CNTR_REQ                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_I2S_2                        _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_I2S_1                        _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_SPD_I                        _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_UI_I                 _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_MIPI                 _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_I2S2_2                       _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_I2S2_1                       _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_UART_A                       _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_UART_B                       _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_UART_C                       _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_SPI                  _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_AC97                 _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_ACModem                      _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_SL4B                 _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_SL2B1                        _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_SL2B2                        _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_SL2B3                        _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_SL2B4                        _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_UART_D                       _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_UART_E                       _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_I2C                  _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_I2C2                 _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_I2C3                 _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_DVC_I2C                      _MK_ENUM_CONST(24)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_OWR                  _MK_ENUM_CONST(25)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_NA26                 _MK_ENUM_CONST(26)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_NA27                 _MK_ENUM_CONST(27)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_NA28                 _MK_ENUM_CONST(28)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_NA29                 _MK_ENUM_CONST(29)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_NA30                 _MK_ENUM_CONST(30)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_NA31                 _MK_ENUM_CONST(31)
+
+// Number of 32bit word cycles
+#define APBDMACHAN_CHANNEL_0_CSR_0_WCOUNT_SHIFT                 _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_0_CSR_0_WCOUNT_FIELD                 (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_0_CSR_0_WCOUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_0_CSR_0_WCOUNT_RANGE                 15:2
+#define APBDMACHAN_CHANNEL_0_CSR_0_WCOUNT_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_0_CSR_0_WCOUNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_WCOUNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_0_CSR_0_WCOUNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_WCOUNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_0_STA_0  
+#define APBDMACHAN_CHANNEL_0_STA_0                      _MK_ADDR_CONST(0x4)
+#define APBDMACHAN_CHANNEL_0_STA_0_SECURE                       0x0
+#define APBDMACHAN_CHANNEL_0_STA_0_WORD_COUNT                   0x1
+#define APBDMACHAN_CHANNEL_0_STA_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_STA_0_RESET_MASK                   _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_0_STA_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_STA_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_STA_0_READ_MASK                    _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_0_STA_0_WRITE_MASK                   _MK_MASK_CONST(0x40000000)
+// indicates whether DMA Channel Status active or not
+#define APBDMACHAN_CHANNEL_0_STA_0_BSY_SHIFT                    _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_0_STA_0_BSY_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_0_STA_0_BSY_SHIFT)
+#define APBDMACHAN_CHANNEL_0_STA_0_BSY_RANGE                    31:31
+#define APBDMACHAN_CHANNEL_0_STA_0_BSY_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_0_STA_0_BSY_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_STA_0_BSY_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_0_STA_0_BSY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_STA_0_BSY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_STA_0_BSY_WAIT                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_0_STA_0_BSY_ACTIVE                   _MK_ENUM_CONST(1)
+
+//  Write '1' to clear the flag                                    
+#define APBDMACHAN_CHANNEL_0_STA_0_ISE_EOC_SHIFT                        _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_0_STA_0_ISE_EOC_FIELD                        (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_0_STA_0_ISE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_0_STA_0_ISE_EOC_RANGE                        30:30
+#define APBDMACHAN_CHANNEL_0_STA_0_ISE_EOC_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_0_STA_0_ISE_EOC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_STA_0_ISE_EOC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_0_STA_0_ISE_EOC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_STA_0_ISE_EOC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_STA_0_ISE_EOC_NO_INTR                      _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_0_STA_0_ISE_EOC_INTR                 _MK_ENUM_CONST(1)
+
+// Holding Status of Processor
+#define APBDMACHAN_CHANNEL_0_STA_0_HALT_SHIFT                   _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_0_STA_0_HALT_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_0_STA_0_HALT_SHIFT)
+#define APBDMACHAN_CHANNEL_0_STA_0_HALT_RANGE                   29:29
+#define APBDMACHAN_CHANNEL_0_STA_0_HALT_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_0_STA_0_HALT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_STA_0_HALT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_0_STA_0_HALT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_STA_0_HALT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_STA_0_HALT_NO_HALT                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_0_STA_0_HALT_HALT                    _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_0_STA_0_PING_PONG_STA_SHIFT                  _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_0_STA_0_PING_PONG_STA_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_0_STA_0_PING_PONG_STA_SHIFT)
+#define APBDMACHAN_CHANNEL_0_STA_0_PING_PONG_STA_RANGE                  28:28
+#define APBDMACHAN_CHANNEL_0_STA_0_PING_PONG_STA_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_0_STA_0_PING_PONG_STA_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_STA_0_PING_PONG_STA_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_0_STA_0_PING_PONG_STA_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_STA_0_PING_PONG_STA_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_STA_0_PING_PONG_STA_PING_INTR_STA                  _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_0_STA_0_PING_PONG_STA_PONG_INTR_STA                  _MK_ENUM_CONST(1)
+
+// Current 32bit word cycles Flags set /cleared by HW
+#define APBDMACHAN_CHANNEL_0_STA_0_COUNT_SHIFT                  _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_0_STA_0_COUNT_FIELD                  (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_0_STA_0_COUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_0_STA_0_COUNT_RANGE                  15:2
+#define APBDMACHAN_CHANNEL_0_STA_0_COUNT_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_0_STA_0_COUNT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_STA_0_COUNT_DEFAULT_MASK                   _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_0_STA_0_COUNT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_STA_0_COUNT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Reserved address 8 [0x8] 
+
+// Reserved address 12 [0xc] 
+
+// Register APBDMACHAN_CHANNEL_0_AHB_PTR_0  
+#define APBDMACHAN_CHANNEL_0_AHB_PTR_0                  _MK_ADDR_CONST(0x10)
+#define APBDMACHAN_CHANNEL_0_AHB_PTR_0_SECURE                   0x0
+#define APBDMACHAN_CHANNEL_0_AHB_PTR_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_0_AHB_PTR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_AHB_PTR_0_RESET_MASK                       _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_0_AHB_PTR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_AHB_PTR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_AHB_PTR_0_READ_MASK                        _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_0_AHB_PTR_0_WRITE_MASK                       _MK_MASK_CONST(0xfffffffc)
+// APB-DMA Starting Address for AHB Bus: SW writes to  modify
+#define APBDMACHAN_CHANNEL_0_AHB_PTR_0_AHB_BASE_SHIFT                   _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_0_AHB_PTR_0_AHB_BASE_FIELD                   (_MK_MASK_CONST(0x3fffffff) << APBDMACHAN_CHANNEL_0_AHB_PTR_0_AHB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_0_AHB_PTR_0_AHB_BASE_RANGE                   31:2
+#define APBDMACHAN_CHANNEL_0_AHB_PTR_0_AHB_BASE_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_0_AHB_PTR_0_AHB_BASE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_AHB_PTR_0_AHB_BASE_DEFAULT_MASK                    _MK_MASK_CONST(0x3fffffff)
+#define APBDMACHAN_CHANNEL_0_AHB_PTR_0_AHB_BASE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_AHB_PTR_0_AHB_BASE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_0_AHB_SEQ_0  
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0                  _MK_ADDR_CONST(0x14)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_SECURE                   0x0
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_RESET_VAL                        _MK_MASK_CONST(0x20000000)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_RESET_MASK                       _MK_MASK_CONST(0xff0f0000)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_READ_MASK                        _MK_MASK_CONST(0xff0f0000)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_WRITE_MASK                       _MK_MASK_CONST(0xff0f0000)
+// 0 = send interrupt to COP
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_INTR_ENB_SHIFT                   _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_INTR_ENB_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_0_AHB_SEQ_0_INTR_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_INTR_ENB_RANGE                   31:31
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_INTR_ENB_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_INTR_ENB_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_INTR_ENB_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_INTR_ENB_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_INTR_ENB_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_INTR_ENB_CPU                     _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_INTR_ENB_COP                     _MK_ENUM_CONST(0)
+
+// AHB Bus Width 0 = 8 bit Bus (RSVD) 1 = 16 bit Bus (RSVD) 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD)4 = 128 bit Bus (RSVD)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT                      _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_BUS_WIDTH_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_BUS_WIDTH_RANGE                      30:28
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_BUS_WIDTH_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT                    _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_8                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_16                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_32                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_64                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_128                      _MK_ENUM_CONST(4)
+
+// when enabled the data going  to AHB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }.
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT                      _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_DATA_SWAP_FIELD                      (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_DATA_SWAP_RANGE                      27:27
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_DATA_SWAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_DATA_SWAP_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_DATA_SWAP_ENABLE                     _MK_ENUM_CONST(1)
+
+// AHB Burst Size DMA Burst Length (encoded) 4 = 1 Word (1x32bits) 5 = 4 Words (4x32bits)else = 8 Words (8x32bits) default
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_BURST_SHIFT                  _MK_SHIFT_CONST(24)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_BURST_FIELD                  (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_BURST_SHIFT)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_BURST_RANGE                  26:24
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_BURST_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_BURST_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_BURST_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_BURST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_BURST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_BURST_DMA_BURST_1WORDS                       _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_BURST_DMA_BURST_4WORDS                       _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_BURST_DMA_BURST_8WORDS                       _MK_ENUM_CONST(6)
+
+// 2X Double Buffering Mode (For Run-Multiple Mode with No Wrap Operations) 1 = Reload Base Address for 2X blocks (reload every other time) 0 = Reload Base Address for 1X blocks  (def) (reload each time)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_DBL_BUF_SHIFT                    _MK_SHIFT_CONST(19)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_DBL_BUF_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_0_AHB_SEQ_0_DBL_BUF_SHIFT)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_DBL_BUF_RANGE                    19:19
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_DBL_BUF_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_DBL_BUF_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_DBL_BUF_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_DBL_BUF_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_DBL_BUF_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_DBL_BUF_RELOAD_FOR_1X_BLOCKS                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_DBL_BUF_RELOAD_FOR_2X_BLOCKS                     _MK_ENUM_CONST(1)
+
+// AHB Address Wrap: AHB Address wrap-around window 0=No Wrap (default) 5=Wrap on 512 word window 1=Wrap on 32 word window 6=Wrap on 1024 word window 2=Wrap on 64 word window 7=Wrap on 2048 word window 3=Wrap on 128 word window 4=Wrap on 256 word window
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_WRAP_SHIFT                       _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_WRAP_FIELD                       (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_0_AHB_SEQ_0_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_WRAP_RANGE                       18:16
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_WRAP_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_WRAP_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_WRAP_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_WRAP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_WRAP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_WRAP_NO_WRAP                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_WRAP_WRAP_0N_32WORDS                     _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_WRAP_WRAP_ON_64WORDS                     _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_WRAP_WRAP_ON_128WORDS                    _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_WRAP_WRAP_ON_256WORDS                    _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_WRAP_WRAP_ON_512WORDS                    _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_WRAP_WRAP_ON_1024WORDS                   _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_WRAP_WRAP_ON_2048WORDS                   _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_0_APB_PTR_0  
+#define APBDMACHAN_CHANNEL_0_APB_PTR_0                  _MK_ADDR_CONST(0x18)
+#define APBDMACHAN_CHANNEL_0_APB_PTR_0_SECURE                   0x0
+#define APBDMACHAN_CHANNEL_0_APB_PTR_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_0_APB_PTR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_APB_PTR_0_RESET_MASK                       _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_0_APB_PTR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_APB_PTR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_APB_PTR_0_READ_MASK                        _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_0_APB_PTR_0_WRITE_MASK                       _MK_MASK_CONST(0xfffc)
+// APB-DMA Starting address for APB Bus:APB Base address:Upper 16 bits are fixed at 0x7000:XXXX
+#define APBDMACHAN_CHANNEL_0_APB_PTR_0_APB_BASE_SHIFT                   _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_0_APB_PTR_0_APB_BASE_FIELD                   (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_0_APB_PTR_0_APB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_0_APB_PTR_0_APB_BASE_RANGE                   15:2
+#define APBDMACHAN_CHANNEL_0_APB_PTR_0_APB_BASE_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_0_APB_PTR_0_APB_BASE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_APB_PTR_0_APB_BASE_DEFAULT_MASK                    _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_0_APB_PTR_0_APB_BASE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_APB_PTR_0_APB_BASE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_0_APB_SEQ_0  
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0                  _MK_ADDR_CONST(0x1c)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_SECURE                   0x0
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_RESET_VAL                        _MK_MASK_CONST(0x20010000)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_RESET_MASK                       _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_READ_MASK                        _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_WRITE_MASK                       _MK_MASK_CONST(0x78070000)
+// 0 = 8 bit Bus 1 = 16 bit Bus 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD) 4 = 128 bit BUS (RSVD)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_BUS_WIDTH_SHIFT                      _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_BUS_WIDTH_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_BUS_WIDTH_RANGE                      30:28
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_BUS_WIDTH_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT                    _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_8                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_16                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_32                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_64                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_128                      _MK_ENUM_CONST(4)
+
+//When enabled the data going  to APB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }.
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_DATA_SWAP_SHIFT                      _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_DATA_SWAP_FIELD                      (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_DATA_SWAP_RANGE                      27:27
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_DATA_SWAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_DATA_SWAP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_DATA_SWAP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_DATA_SWAP_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_DATA_SWAP_ENABLE                     _MK_ENUM_CONST(1)
+
+//APB Address Wrap-around Window 0 = No Wrap 1 = Wrap on 1 Word Window (def) 2 = Wrap on 2 Word Window 3 = Wrap on 4 Word Window 4 = Wrap on 8 Word Window 5 = Wrap on 16 Word Window 6 = Wrap on 32 Word Window 7 = Wrap on 64 Word Window (rsvd)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_ADDR_WRAP_SHIFT                      _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_ADDR_WRAP_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_ADDR_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_ADDR_WRAP_RANGE                      18:16
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_ADDR_WRAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_ADDR_WRAP_NO_WRAP                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_ADDR_WRAP_WRAP_0N_1WORDS                     _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_2WORDS                     _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_4WORDS                     _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_8WORDS                     _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_16WORDS                    _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_32WORDS                    _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_64WORDS                    _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_1_CSR_0  
+#define APBDMACHAN_CHANNEL_1_CSR_0                      _MK_ADDR_CONST(0x20)
+#define APBDMACHAN_CHANNEL_1_CSR_0_SECURE                       0x0
+#define APBDMACHAN_CHANNEL_1_CSR_0_WORD_COUNT                   0x1
+#define APBDMACHAN_CHANNEL_1_CSR_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_RESET_MASK                   _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_1_CSR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_READ_MASK                    _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_1_CSR_0_WRITE_MASK                   _MK_MASK_CONST(0xfffffffc)
+// Enables DMA channel transfer 
+#define APBDMACHAN_CHANNEL_1_CSR_0_ENB_SHIFT                    _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_1_CSR_0_ENB_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_1_CSR_0_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_1_CSR_0_ENB_RANGE                    31:31
+#define APBDMACHAN_CHANNEL_1_CSR_0_ENB_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_1_CSR_0_ENB_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_ENB_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_1_CSR_0_ENB_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_ENB_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_ENB_DISABLE                  _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_ENB_ENABLE                   _MK_ENUM_CONST(1)
+
+// Interrupts when DMA Block Transfer Completes 
+#define APBDMACHAN_CHANNEL_1_CSR_0_IE_EOC_SHIFT                 _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_1_CSR_0_IE_EOC_FIELD                 (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_1_CSR_0_IE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_1_CSR_0_IE_EOC_RANGE                 30:30
+#define APBDMACHAN_CHANNEL_1_CSR_0_IE_EOC_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_1_CSR_0_IE_EOC_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_IE_EOC_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_1_CSR_0_IE_EOC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_IE_EOC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_IE_EOC_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_IE_EOC_ENABLE                        _MK_ENUM_CONST(1)
+
+// Holds this Processor until DMA Block Transfer Completes
+#define APBDMACHAN_CHANNEL_1_CSR_0_HOLD_SHIFT                   _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_1_CSR_0_HOLD_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_1_CSR_0_HOLD_SHIFT)
+#define APBDMACHAN_CHANNEL_1_CSR_0_HOLD_RANGE                   29:29
+#define APBDMACHAN_CHANNEL_1_CSR_0_HOLD_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_1_CSR_0_HOLD_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_HOLD_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_1_CSR_0_HOLD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_HOLD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_HOLD_DISABLE                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_HOLD_ENABLE                  _MK_ENUM_CONST(1)
+
+// DMA Transfer Direction 1 = AHB read to APB write 0 = APB read to AHB write
+#define APBDMACHAN_CHANNEL_1_CSR_0_DIR_SHIFT                    _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_1_CSR_0_DIR_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_1_CSR_0_DIR_SHIFT)
+#define APBDMACHAN_CHANNEL_1_CSR_0_DIR_RANGE                    28:28
+#define APBDMACHAN_CHANNEL_1_CSR_0_DIR_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_1_CSR_0_DIR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_DIR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_1_CSR_0_DIR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_DIR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_DIR_AHB_WRITE                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_DIR_AHB_READ                 _MK_ENUM_CONST(1)
+
+// Run Once or Run Multiple Mode (Allow Retriggering of this Channel) 1 = Run for One Block Transfer 0 = Run for Multiple Block Transfer
+#define APBDMACHAN_CHANNEL_1_CSR_0_ONCE_SHIFT                   _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_1_CSR_0_ONCE_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_1_CSR_0_ONCE_SHIFT)
+#define APBDMACHAN_CHANNEL_1_CSR_0_ONCE_RANGE                   27:27
+#define APBDMACHAN_CHANNEL_1_CSR_0_ONCE_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_1_CSR_0_ONCE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_ONCE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_1_CSR_0_ONCE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_ONCE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_ONCE_MULTIPLE_BLOCK                  _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_ONCE_SINGLE_BLOCK                    _MK_ENUM_CONST(1)
+
+// Enable on Non-Zero Value
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_SHIFT                       _MK_SHIFT_CONST(22)
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_FIELD                       (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_RANGE                       26:22
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_NA1                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_SMP24                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_SMP25                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_SMP26                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_SMP27                       _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_XRQ_A                       _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_XRQ_B                       _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_TMR1                        _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_TMR2                        _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_APB_0                       _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_APB_1                       _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_APB_2                       _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_APB_3                       _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_APB_4                       _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_APB_5                       _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_APB_6                       _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_APB_7                       _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_APB_8                       _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_APB_9                       _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_APB_10                      _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_APB_11                      _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_APB_12                      _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_APB_13                      _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_APB_14                      _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_APB_15                      _MK_ENUM_CONST(24)
+
+// Flow Control Enable (Synchronize Burst Transfers) 1 = Link to DRQ source 0 = Independent of DRQ request
+#define APBDMACHAN_CHANNEL_1_CSR_0_FLOW_SHIFT                   _MK_SHIFT_CONST(21)
+#define APBDMACHAN_CHANNEL_1_CSR_0_FLOW_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_1_CSR_0_FLOW_SHIFT)
+#define APBDMACHAN_CHANNEL_1_CSR_0_FLOW_RANGE                   21:21
+#define APBDMACHAN_CHANNEL_1_CSR_0_FLOW_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_1_CSR_0_FLOW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_FLOW_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_1_CSR_0_FLOW_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_FLOW_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_FLOW_DISABLE                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_FLOW_ENABLE                  _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_SHIFT                        _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_FIELD                        (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_RANGE                        20:16
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_CNTR_REQ                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_I2S_2                        _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_I2S_1                        _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_SPD_I                        _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_UI_I                 _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_MIPI                 _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_I2S2_2                       _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_I2S2_1                       _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_UART_A                       _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_UART_B                       _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_UART_C                       _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_SPI                  _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_AC97                 _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_ACModem                      _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_SL4B                 _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_SL2B1                        _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_SL2B2                        _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_SL2B3                        _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_SL2B4                        _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_UART_D                       _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_UART_E                       _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_I2C                  _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_I2C2                 _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_I2C3                 _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_DVC_I2C                      _MK_ENUM_CONST(24)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_OWR                  _MK_ENUM_CONST(25)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_NA26                 _MK_ENUM_CONST(26)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_NA27                 _MK_ENUM_CONST(27)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_NA28                 _MK_ENUM_CONST(28)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_NA29                 _MK_ENUM_CONST(29)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_NA30                 _MK_ENUM_CONST(30)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_NA31                 _MK_ENUM_CONST(31)
+
+// Number of 32bit word cycles
+#define APBDMACHAN_CHANNEL_1_CSR_0_WCOUNT_SHIFT                 _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_1_CSR_0_WCOUNT_FIELD                 (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_1_CSR_0_WCOUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_1_CSR_0_WCOUNT_RANGE                 15:2
+#define APBDMACHAN_CHANNEL_1_CSR_0_WCOUNT_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_1_CSR_0_WCOUNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_WCOUNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_1_CSR_0_WCOUNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_WCOUNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_1_STA_0  
+#define APBDMACHAN_CHANNEL_1_STA_0                      _MK_ADDR_CONST(0x24)
+#define APBDMACHAN_CHANNEL_1_STA_0_SECURE                       0x0
+#define APBDMACHAN_CHANNEL_1_STA_0_WORD_COUNT                   0x1
+#define APBDMACHAN_CHANNEL_1_STA_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_STA_0_RESET_MASK                   _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_1_STA_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_STA_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_STA_0_READ_MASK                    _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_1_STA_0_WRITE_MASK                   _MK_MASK_CONST(0x40000000)
+// indicates whether DMA Channel Status active or not
+#define APBDMACHAN_CHANNEL_1_STA_0_BSY_SHIFT                    _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_1_STA_0_BSY_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_1_STA_0_BSY_SHIFT)
+#define APBDMACHAN_CHANNEL_1_STA_0_BSY_RANGE                    31:31
+#define APBDMACHAN_CHANNEL_1_STA_0_BSY_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_1_STA_0_BSY_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_STA_0_BSY_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_1_STA_0_BSY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_STA_0_BSY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_STA_0_BSY_WAIT                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_1_STA_0_BSY_ACTIVE                   _MK_ENUM_CONST(1)
+
+//  Write '1' to clear the flag
+#define APBDMACHAN_CHANNEL_1_STA_0_ISE_EOC_SHIFT                        _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_1_STA_0_ISE_EOC_FIELD                        (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_1_STA_0_ISE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_1_STA_0_ISE_EOC_RANGE                        30:30
+#define APBDMACHAN_CHANNEL_1_STA_0_ISE_EOC_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_1_STA_0_ISE_EOC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_STA_0_ISE_EOC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_1_STA_0_ISE_EOC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_STA_0_ISE_EOC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_STA_0_ISE_EOC_NO_INTR                      _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_1_STA_0_ISE_EOC_INTR                 _MK_ENUM_CONST(1)
+
+// Holding Status of Processor
+#define APBDMACHAN_CHANNEL_1_STA_0_HALT_SHIFT                   _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_1_STA_0_HALT_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_1_STA_0_HALT_SHIFT)
+#define APBDMACHAN_CHANNEL_1_STA_0_HALT_RANGE                   29:29
+#define APBDMACHAN_CHANNEL_1_STA_0_HALT_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_1_STA_0_HALT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_STA_0_HALT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_1_STA_0_HALT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_STA_0_HALT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_STA_0_HALT_NO_HALT                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_1_STA_0_HALT_HALT                    _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_1_STA_0_PING_PONG_STA_SHIFT                  _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_1_STA_0_PING_PONG_STA_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_1_STA_0_PING_PONG_STA_SHIFT)
+#define APBDMACHAN_CHANNEL_1_STA_0_PING_PONG_STA_RANGE                  28:28
+#define APBDMACHAN_CHANNEL_1_STA_0_PING_PONG_STA_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_1_STA_0_PING_PONG_STA_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_STA_0_PING_PONG_STA_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_1_STA_0_PING_PONG_STA_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_STA_0_PING_PONG_STA_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_STA_0_PING_PONG_STA_PING_INTR_STA                  _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_1_STA_0_PING_PONG_STA_PONG_INTR_STA                  _MK_ENUM_CONST(1)
+
+// Current 32bit word cycles Flags set /cleared by HW
+#define APBDMACHAN_CHANNEL_1_STA_0_COUNT_SHIFT                  _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_1_STA_0_COUNT_FIELD                  (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_1_STA_0_COUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_1_STA_0_COUNT_RANGE                  15:2
+#define APBDMACHAN_CHANNEL_1_STA_0_COUNT_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_1_STA_0_COUNT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_STA_0_COUNT_DEFAULT_MASK                   _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_1_STA_0_COUNT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_STA_0_COUNT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Reserved address 40 [0x28] 
+
+// Reserved address 44 [0x2c] 
+
+// Register APBDMACHAN_CHANNEL_1_AHB_PTR_0  
+#define APBDMACHAN_CHANNEL_1_AHB_PTR_0                  _MK_ADDR_CONST(0x30)
+#define APBDMACHAN_CHANNEL_1_AHB_PTR_0_SECURE                   0x0
+#define APBDMACHAN_CHANNEL_1_AHB_PTR_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_1_AHB_PTR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_AHB_PTR_0_RESET_MASK                       _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_1_AHB_PTR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_AHB_PTR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_AHB_PTR_0_READ_MASK                        _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_1_AHB_PTR_0_WRITE_MASK                       _MK_MASK_CONST(0xfffffffc)
+// APB-DMA Starting Address for AHB Bus: SW writes to  modify
+#define APBDMACHAN_CHANNEL_1_AHB_PTR_0_AHB_BASE_SHIFT                   _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_1_AHB_PTR_0_AHB_BASE_FIELD                   (_MK_MASK_CONST(0x3fffffff) << APBDMACHAN_CHANNEL_1_AHB_PTR_0_AHB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_1_AHB_PTR_0_AHB_BASE_RANGE                   31:2
+#define APBDMACHAN_CHANNEL_1_AHB_PTR_0_AHB_BASE_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_1_AHB_PTR_0_AHB_BASE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_AHB_PTR_0_AHB_BASE_DEFAULT_MASK                    _MK_MASK_CONST(0x3fffffff)
+#define APBDMACHAN_CHANNEL_1_AHB_PTR_0_AHB_BASE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_AHB_PTR_0_AHB_BASE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_1_AHB_SEQ_0  
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0                  _MK_ADDR_CONST(0x34)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_SECURE                   0x0
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_RESET_VAL                        _MK_MASK_CONST(0x20000000)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_RESET_MASK                       _MK_MASK_CONST(0xff0f0000)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_READ_MASK                        _MK_MASK_CONST(0xff0f0000)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_WRITE_MASK                       _MK_MASK_CONST(0xff0f0000)
+// 0 = send interrupt to COP
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_INTR_ENB_SHIFT                   _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_INTR_ENB_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_1_AHB_SEQ_0_INTR_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_INTR_ENB_RANGE                   31:31
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_INTR_ENB_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_INTR_ENB_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_INTR_ENB_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_INTR_ENB_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_INTR_ENB_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_INTR_ENB_CPU                     _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_INTR_ENB_COP                     _MK_ENUM_CONST(0)
+
+// AHB Bus Width 0 = 8 bit Bus (RSVD) 1 = 16 bit Bus (RSVD) 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD)4 = 128 bit Bus (RSVD)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT                      _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_BUS_WIDTH_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_BUS_WIDTH_RANGE                      30:28
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_BUS_WIDTH_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT                    _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_8                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_16                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_32                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_64                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_128                      _MK_ENUM_CONST(4)
+
+//when enabled the data going  to AHB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT                      _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_DATA_SWAP_FIELD                      (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_DATA_SWAP_RANGE                      27:27
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_DATA_SWAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_DATA_SWAP_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_DATA_SWAP_ENABLE                     _MK_ENUM_CONST(1)
+
+// AHB Burst Size DMA Burst Length (encoded) 4 = 1 Word (1x32bits) 5 = 4 Words (4x32bits)else = 8 Words (8x32bits) default
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_BURST_SHIFT                  _MK_SHIFT_CONST(24)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_BURST_FIELD                  (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_BURST_SHIFT)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_BURST_RANGE                  26:24
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_BURST_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_BURST_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_BURST_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_BURST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_BURST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_BURST_DMA_BURST_1WORDS                       _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_BURST_DMA_BURST_4WORDS                       _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_BURST_DMA_BURST_8WORDS                       _MK_ENUM_CONST(6)
+
+// 2X Double Buffering Mode (For Run-Multiple Mode with No Wrap Operations) 1 = Reload Base Address for 2X blocks (reload every other time) 0 = Reload Base Address for 1X blocks  (def) (reload each time)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_DBL_BUF_SHIFT                    _MK_SHIFT_CONST(19)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_DBL_BUF_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_1_AHB_SEQ_0_DBL_BUF_SHIFT)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_DBL_BUF_RANGE                    19:19
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_DBL_BUF_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_DBL_BUF_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_DBL_BUF_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_DBL_BUF_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_DBL_BUF_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_DBL_BUF_RELOAD_FOR_1X_BLOCKS                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_DBL_BUF_RELOAD_FOR_2X_BLOCKS                     _MK_ENUM_CONST(1)
+
+// AHB Address Wrap: AHB Address wrap-around window 0=No Wrap (default) 5=Wrap on 512 word window 1=Wrap on 32 word window 6=Wrap on 1024 word window 2=Wrap on 64 word window 7=Wrap on 2048 word window 3=Wrap on 128 word window 4=Wrap on 256 word window
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_WRAP_SHIFT                       _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_WRAP_FIELD                       (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_1_AHB_SEQ_0_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_WRAP_RANGE                       18:16
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_WRAP_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_WRAP_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_WRAP_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_WRAP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_WRAP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_WRAP_NO_WRAP                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_WRAP_WRAP_0N_32WORDS                     _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_WRAP_WRAP_ON_64WORDS                     _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_WRAP_WRAP_ON_128WORDS                    _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_WRAP_WRAP_ON_256WORDS                    _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_WRAP_WRAP_ON_512WORDS                    _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_WRAP_WRAP_ON_1024WORDS                   _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_WRAP_WRAP_ON_2048WORDS                   _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_1_APB_PTR_0  
+#define APBDMACHAN_CHANNEL_1_APB_PTR_0                  _MK_ADDR_CONST(0x38)
+#define APBDMACHAN_CHANNEL_1_APB_PTR_0_SECURE                   0x0
+#define APBDMACHAN_CHANNEL_1_APB_PTR_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_1_APB_PTR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_APB_PTR_0_RESET_MASK                       _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_1_APB_PTR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_APB_PTR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_APB_PTR_0_READ_MASK                        _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_1_APB_PTR_0_WRITE_MASK                       _MK_MASK_CONST(0xfffc)
+// APB-DMA Starting address for APB Bus: APB Base address: Upper 16 bits are fixed at 0x7000:XXXX
+#define APBDMACHAN_CHANNEL_1_APB_PTR_0_APB_BASE_SHIFT                   _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_1_APB_PTR_0_APB_BASE_FIELD                   (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_1_APB_PTR_0_APB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_1_APB_PTR_0_APB_BASE_RANGE                   15:2
+#define APBDMACHAN_CHANNEL_1_APB_PTR_0_APB_BASE_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_1_APB_PTR_0_APB_BASE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_APB_PTR_0_APB_BASE_DEFAULT_MASK                    _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_1_APB_PTR_0_APB_BASE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_APB_PTR_0_APB_BASE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_1_APB_SEQ_0  
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0                  _MK_ADDR_CONST(0x3c)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_SECURE                   0x0
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_RESET_VAL                        _MK_MASK_CONST(0x20010000)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_RESET_MASK                       _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_READ_MASK                        _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_WRITE_MASK                       _MK_MASK_CONST(0x78070000)
+// 0 = 8 bit Bus 1 = 16 bit Bus 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD) 4 = 128 bit BUS (RSVD)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_BUS_WIDTH_SHIFT                      _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_BUS_WIDTH_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_BUS_WIDTH_RANGE                      30:28
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_BUS_WIDTH_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT                    _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_8                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_16                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_32                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_64                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_128                      _MK_ENUM_CONST(4)
+
+//when enabled the data going  to APB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_DATA_SWAP_SHIFT                      _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_DATA_SWAP_FIELD                      (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_DATA_SWAP_RANGE                      27:27
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_DATA_SWAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_DATA_SWAP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_DATA_SWAP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_DATA_SWAP_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_DATA_SWAP_ENABLE                     _MK_ENUM_CONST(1)
+
+//APB Address Wrap-around Window 0 = No Wrap 1 = Wrap on 1 Word Window (def) 2 = Wrap on 2 Word Window 3 = Wrap on 4 Word Window 4 = Wrap on 8 Word Window 5 = Wrap on 16 Word Window 6 = Wrap on 32 Word Window 7 = Wrap on 64 Word Window (rsvd)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_ADDR_WRAP_SHIFT                      _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_ADDR_WRAP_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_ADDR_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_ADDR_WRAP_RANGE                      18:16
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_ADDR_WRAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_ADDR_WRAP_NO_WRAP                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_ADDR_WRAP_WRAP_0N_1WORDS                     _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_2WORDS                     _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_4WORDS                     _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_8WORDS                     _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_16WORDS                    _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_32WORDS                    _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_64WORDS                    _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_2_CSR_0  
+#define APBDMACHAN_CHANNEL_2_CSR_0                      _MK_ADDR_CONST(0x40)
+#define APBDMACHAN_CHANNEL_2_CSR_0_SECURE                       0x0
+#define APBDMACHAN_CHANNEL_2_CSR_0_WORD_COUNT                   0x1
+#define APBDMACHAN_CHANNEL_2_CSR_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_RESET_MASK                   _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_2_CSR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_READ_MASK                    _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_2_CSR_0_WRITE_MASK                   _MK_MASK_CONST(0xfffffffc)
+// Enables DMA channel transfer 
+#define APBDMACHAN_CHANNEL_2_CSR_0_ENB_SHIFT                    _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_2_CSR_0_ENB_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_2_CSR_0_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_2_CSR_0_ENB_RANGE                    31:31
+#define APBDMACHAN_CHANNEL_2_CSR_0_ENB_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_2_CSR_0_ENB_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_ENB_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_2_CSR_0_ENB_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_ENB_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_ENB_DISABLE                  _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_ENB_ENABLE                   _MK_ENUM_CONST(1)
+
+// Interrupts when DMA Block Transfer Completes 
+#define APBDMACHAN_CHANNEL_2_CSR_0_IE_EOC_SHIFT                 _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_2_CSR_0_IE_EOC_FIELD                 (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_2_CSR_0_IE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_2_CSR_0_IE_EOC_RANGE                 30:30
+#define APBDMACHAN_CHANNEL_2_CSR_0_IE_EOC_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_2_CSR_0_IE_EOC_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_IE_EOC_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_2_CSR_0_IE_EOC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_IE_EOC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_IE_EOC_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_IE_EOC_ENABLE                        _MK_ENUM_CONST(1)
+
+// Holds this Processor until DMA Block Transfer Completes 
+#define APBDMACHAN_CHANNEL_2_CSR_0_HOLD_SHIFT                   _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_2_CSR_0_HOLD_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_2_CSR_0_HOLD_SHIFT)
+#define APBDMACHAN_CHANNEL_2_CSR_0_HOLD_RANGE                   29:29
+#define APBDMACHAN_CHANNEL_2_CSR_0_HOLD_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_2_CSR_0_HOLD_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_HOLD_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_2_CSR_0_HOLD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_HOLD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_HOLD_DISABLE                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_HOLD_ENABLE                  _MK_ENUM_CONST(1)
+
+// DMA Transfer Direction 1 = AHB read to APB write 0 = APB read to AHB write
+#define APBDMACHAN_CHANNEL_2_CSR_0_DIR_SHIFT                    _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_2_CSR_0_DIR_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_2_CSR_0_DIR_SHIFT)
+#define APBDMACHAN_CHANNEL_2_CSR_0_DIR_RANGE                    28:28
+#define APBDMACHAN_CHANNEL_2_CSR_0_DIR_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_2_CSR_0_DIR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_DIR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_2_CSR_0_DIR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_DIR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_DIR_AHB_WRITE                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_DIR_AHB_READ                 _MK_ENUM_CONST(1)
+
+// Run Once or Run Multiple Mode (Allow Retriggering of this Channel) 1 = Run for One Block Transfer 0 = Run for Multiple Block Transfer
+#define APBDMACHAN_CHANNEL_2_CSR_0_ONCE_SHIFT                   _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_2_CSR_0_ONCE_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_2_CSR_0_ONCE_SHIFT)
+#define APBDMACHAN_CHANNEL_2_CSR_0_ONCE_RANGE                   27:27
+#define APBDMACHAN_CHANNEL_2_CSR_0_ONCE_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_2_CSR_0_ONCE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_ONCE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_2_CSR_0_ONCE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_ONCE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_ONCE_MULTIPLE_BLOCK                  _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_ONCE_SINGLE_BLOCK                    _MK_ENUM_CONST(1)
+
+// Enable on Non-Zero Value
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_SHIFT                       _MK_SHIFT_CONST(22)
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_FIELD                       (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_RANGE                       26:22
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_NA1                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_SMP24                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_SMP25                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_SMP26                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_SMP27                       _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_XRQ_A                       _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_XRQ_B                       _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_TMR1                        _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_TMR2                        _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_APB_0                       _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_APB_1                       _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_APB_2                       _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_APB_3                       _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_APB_4                       _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_APB_5                       _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_APB_6                       _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_APB_7                       _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_APB_8                       _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_APB_9                       _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_APB_10                      _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_APB_11                      _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_APB_12                      _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_APB_13                      _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_APB_14                      _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_APB_15                      _MK_ENUM_CONST(24)
+
+// Flow Control Enable (Synchronize Burst Transfers) 1 = Link to DRQ source 0 = Independent of DRQ request
+#define APBDMACHAN_CHANNEL_2_CSR_0_FLOW_SHIFT                   _MK_SHIFT_CONST(21)
+#define APBDMACHAN_CHANNEL_2_CSR_0_FLOW_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_2_CSR_0_FLOW_SHIFT)
+#define APBDMACHAN_CHANNEL_2_CSR_0_FLOW_RANGE                   21:21
+#define APBDMACHAN_CHANNEL_2_CSR_0_FLOW_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_2_CSR_0_FLOW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_FLOW_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_2_CSR_0_FLOW_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_FLOW_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_FLOW_DISABLE                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_FLOW_ENABLE                  _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_SHIFT                        _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_FIELD                        (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_RANGE                        20:16
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_CNTR_REQ                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_I2S_2                        _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_I2S_1                        _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_SPD_I                        _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_UI_I                 _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_MIPI                 _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_I2S2_2                       _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_I2S2_1                       _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_UART_A                       _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_UART_B                       _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_UART_C                       _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_SPI                  _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_AC97                 _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_ACModem                      _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_SL4B                 _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_SL2B1                        _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_SL2B2                        _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_SL2B3                        _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_SL2B4                        _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_UART_D                       _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_UART_E                       _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_I2C                  _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_I2C2                 _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_I2C3                 _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_DVC_I2C                      _MK_ENUM_CONST(24)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_OWR                  _MK_ENUM_CONST(25)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_NA26                 _MK_ENUM_CONST(26)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_NA27                 _MK_ENUM_CONST(27)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_NA28                 _MK_ENUM_CONST(28)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_NA29                 _MK_ENUM_CONST(29)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_NA30                 _MK_ENUM_CONST(30)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_NA31                 _MK_ENUM_CONST(31)
+
+// Number of 32bit word cycles
+#define APBDMACHAN_CHANNEL_2_CSR_0_WCOUNT_SHIFT                 _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_2_CSR_0_WCOUNT_FIELD                 (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_2_CSR_0_WCOUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_2_CSR_0_WCOUNT_RANGE                 15:2
+#define APBDMACHAN_CHANNEL_2_CSR_0_WCOUNT_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_2_CSR_0_WCOUNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_WCOUNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_2_CSR_0_WCOUNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_WCOUNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_2_STA_0  
+#define APBDMACHAN_CHANNEL_2_STA_0                      _MK_ADDR_CONST(0x44)
+#define APBDMACHAN_CHANNEL_2_STA_0_SECURE                       0x0
+#define APBDMACHAN_CHANNEL_2_STA_0_WORD_COUNT                   0x1
+#define APBDMACHAN_CHANNEL_2_STA_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_STA_0_RESET_MASK                   _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_2_STA_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_STA_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_STA_0_READ_MASK                    _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_2_STA_0_WRITE_MASK                   _MK_MASK_CONST(0x40000000)
+// indicates whether DMA Channel Status active or not
+#define APBDMACHAN_CHANNEL_2_STA_0_BSY_SHIFT                    _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_2_STA_0_BSY_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_2_STA_0_BSY_SHIFT)
+#define APBDMACHAN_CHANNEL_2_STA_0_BSY_RANGE                    31:31
+#define APBDMACHAN_CHANNEL_2_STA_0_BSY_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_2_STA_0_BSY_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_STA_0_BSY_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_2_STA_0_BSY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_STA_0_BSY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_STA_0_BSY_WAIT                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_2_STA_0_BSY_ACTIVE                   _MK_ENUM_CONST(1)
+
+//  Write '1' to clear the flag
+#define APBDMACHAN_CHANNEL_2_STA_0_ISE_EOC_SHIFT                        _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_2_STA_0_ISE_EOC_FIELD                        (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_2_STA_0_ISE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_2_STA_0_ISE_EOC_RANGE                        30:30
+#define APBDMACHAN_CHANNEL_2_STA_0_ISE_EOC_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_2_STA_0_ISE_EOC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_STA_0_ISE_EOC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_2_STA_0_ISE_EOC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_STA_0_ISE_EOC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_STA_0_ISE_EOC_NO_INTR                      _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_2_STA_0_ISE_EOC_INTR                 _MK_ENUM_CONST(1)
+
+// Holding Status of Processor 
+#define APBDMACHAN_CHANNEL_2_STA_0_HALT_SHIFT                   _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_2_STA_0_HALT_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_2_STA_0_HALT_SHIFT)
+#define APBDMACHAN_CHANNEL_2_STA_0_HALT_RANGE                   29:29
+#define APBDMACHAN_CHANNEL_2_STA_0_HALT_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_2_STA_0_HALT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_STA_0_HALT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_2_STA_0_HALT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_STA_0_HALT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_STA_0_HALT_NO_HALT                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_2_STA_0_HALT_HALT                    _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_2_STA_0_PING_PONG_STA_SHIFT                  _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_2_STA_0_PING_PONG_STA_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_2_STA_0_PING_PONG_STA_SHIFT)
+#define APBDMACHAN_CHANNEL_2_STA_0_PING_PONG_STA_RANGE                  28:28
+#define APBDMACHAN_CHANNEL_2_STA_0_PING_PONG_STA_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_2_STA_0_PING_PONG_STA_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_STA_0_PING_PONG_STA_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_2_STA_0_PING_PONG_STA_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_STA_0_PING_PONG_STA_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_STA_0_PING_PONG_STA_PING_INTR_STA                  _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_2_STA_0_PING_PONG_STA_PONG_INTR_STA                  _MK_ENUM_CONST(1)
+
+// Current 32bit word cycles Flags set /cleared by HW
+#define APBDMACHAN_CHANNEL_2_STA_0_COUNT_SHIFT                  _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_2_STA_0_COUNT_FIELD                  (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_2_STA_0_COUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_2_STA_0_COUNT_RANGE                  15:2
+#define APBDMACHAN_CHANNEL_2_STA_0_COUNT_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_2_STA_0_COUNT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_STA_0_COUNT_DEFAULT_MASK                   _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_2_STA_0_COUNT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_STA_0_COUNT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Reserved address 72 [0x48] 
+
+// Reserved address 76 [0x4c] 
+
+// Register APBDMACHAN_CHANNEL_2_AHB_PTR_0  
+#define APBDMACHAN_CHANNEL_2_AHB_PTR_0                  _MK_ADDR_CONST(0x50)
+#define APBDMACHAN_CHANNEL_2_AHB_PTR_0_SECURE                   0x0
+#define APBDMACHAN_CHANNEL_2_AHB_PTR_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_2_AHB_PTR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_AHB_PTR_0_RESET_MASK                       _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_2_AHB_PTR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_AHB_PTR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_AHB_PTR_0_READ_MASK                        _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_2_AHB_PTR_0_WRITE_MASK                       _MK_MASK_CONST(0xfffffffc)
+// APB-DMA Starting Address for AHB Bus: SW writes to  modify
+#define APBDMACHAN_CHANNEL_2_AHB_PTR_0_AHB_BASE_SHIFT                   _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_2_AHB_PTR_0_AHB_BASE_FIELD                   (_MK_MASK_CONST(0x3fffffff) << APBDMACHAN_CHANNEL_2_AHB_PTR_0_AHB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_2_AHB_PTR_0_AHB_BASE_RANGE                   31:2
+#define APBDMACHAN_CHANNEL_2_AHB_PTR_0_AHB_BASE_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_2_AHB_PTR_0_AHB_BASE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_AHB_PTR_0_AHB_BASE_DEFAULT_MASK                    _MK_MASK_CONST(0x3fffffff)
+#define APBDMACHAN_CHANNEL_2_AHB_PTR_0_AHB_BASE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_AHB_PTR_0_AHB_BASE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_2_AHB_SEQ_0  
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0                  _MK_ADDR_CONST(0x54)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_SECURE                   0x0
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_RESET_VAL                        _MK_MASK_CONST(0x20000000)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_RESET_MASK                       _MK_MASK_CONST(0xff0f0000)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_READ_MASK                        _MK_MASK_CONST(0xff0f0000)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_WRITE_MASK                       _MK_MASK_CONST(0xff0f0000)
+// 0 = send interrupt to COP
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_INTR_ENB_SHIFT                   _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_INTR_ENB_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_2_AHB_SEQ_0_INTR_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_INTR_ENB_RANGE                   31:31
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_INTR_ENB_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_INTR_ENB_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_INTR_ENB_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_INTR_ENB_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_INTR_ENB_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_INTR_ENB_CPU                     _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_INTR_ENB_COP                     _MK_ENUM_CONST(0)
+
+// AHB Bus Width 0 = 8 bit Bus (RSVD) 1 = 16 bit Bus (RSVD) 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD)4 = 128 bit Bus (RSVD)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT                      _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_BUS_WIDTH_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_BUS_WIDTH_RANGE                      30:28
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_BUS_WIDTH_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT                    _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_8                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_16                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_32                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_64                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_128                      _MK_ENUM_CONST(4)
+
+// when enabled the data going  to AHB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT                      _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_DATA_SWAP_FIELD                      (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_DATA_SWAP_RANGE                      27:27
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_DATA_SWAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_DATA_SWAP_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_DATA_SWAP_ENABLE                     _MK_ENUM_CONST(1)
+
+// AHB Burst Size DMA Burst Length (encoded) 4 = 1 Word (1x32bits) 5 = 4 Words (4x32bits)else = 8 Words (8x32bits) default
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_BURST_SHIFT                  _MK_SHIFT_CONST(24)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_BURST_FIELD                  (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_BURST_SHIFT)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_BURST_RANGE                  26:24
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_BURST_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_BURST_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_BURST_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_BURST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_BURST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_BURST_DMA_BURST_1WORDS                       _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_BURST_DMA_BURST_4WORDS                       _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_BURST_DMA_BURST_8WORDS                       _MK_ENUM_CONST(6)
+
+// 2X Double Buffering Mode (For Run-Multiple Mode with No Wrap Operations) 1 = Reload Base Address for 2X blocks (reload every other time) 0 = Reload Base Address for 1X blocks  (def) (reload each time)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_DBL_BUF_SHIFT                    _MK_SHIFT_CONST(19)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_DBL_BUF_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_2_AHB_SEQ_0_DBL_BUF_SHIFT)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_DBL_BUF_RANGE                    19:19
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_DBL_BUF_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_DBL_BUF_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_DBL_BUF_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_DBL_BUF_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_DBL_BUF_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_DBL_BUF_RELOAD_FOR_1X_BLOCKS                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_DBL_BUF_RELOAD_FOR_2X_BLOCKS                     _MK_ENUM_CONST(1)
+
+// AHB Address Wrap: AHB Address wrap-around window 0=No Wrap (default) 5=Wrap on 512 word window 1=Wrap on 32 word window 6=Wrap on 1024 word window 2=Wrap on 64 word window 7=Wrap on 2048 word window 3=Wrap on 128 word window 4=Wrap on 256 word window
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_WRAP_SHIFT                       _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_WRAP_FIELD                       (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_2_AHB_SEQ_0_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_WRAP_RANGE                       18:16
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_WRAP_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_WRAP_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_WRAP_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_WRAP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_WRAP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_WRAP_NO_WRAP                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_WRAP_WRAP_0N_32WORDS                     _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_WRAP_WRAP_ON_64WORDS                     _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_WRAP_WRAP_ON_128WORDS                    _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_WRAP_WRAP_ON_256WORDS                    _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_WRAP_WRAP_ON_512WORDS                    _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_WRAP_WRAP_ON_1024WORDS                   _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_WRAP_WRAP_ON_2048WORDS                   _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_2_APB_PTR_0  
+#define APBDMACHAN_CHANNEL_2_APB_PTR_0                  _MK_ADDR_CONST(0x58)
+#define APBDMACHAN_CHANNEL_2_APB_PTR_0_SECURE                   0x0
+#define APBDMACHAN_CHANNEL_2_APB_PTR_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_2_APB_PTR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_APB_PTR_0_RESET_MASK                       _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_2_APB_PTR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_APB_PTR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_APB_PTR_0_READ_MASK                        _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_2_APB_PTR_0_WRITE_MASK                       _MK_MASK_CONST(0xfffc)
+// APB-DMA Starting address for APB Bus: APB Base  address: Upper 16 bits are fixed at 0x7000:XXXX
+#define APBDMACHAN_CHANNEL_2_APB_PTR_0_APB_BASE_SHIFT                   _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_2_APB_PTR_0_APB_BASE_FIELD                   (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_2_APB_PTR_0_APB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_2_APB_PTR_0_APB_BASE_RANGE                   15:2
+#define APBDMACHAN_CHANNEL_2_APB_PTR_0_APB_BASE_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_2_APB_PTR_0_APB_BASE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_APB_PTR_0_APB_BASE_DEFAULT_MASK                    _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_2_APB_PTR_0_APB_BASE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_APB_PTR_0_APB_BASE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_2_APB_SEQ_0  
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0                  _MK_ADDR_CONST(0x5c)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_SECURE                   0x0
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_RESET_VAL                        _MK_MASK_CONST(0x20010000)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_RESET_MASK                       _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_READ_MASK                        _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_WRITE_MASK                       _MK_MASK_CONST(0x78070000)
+// 0 = 8 bit Bus 1 = 16 bit Bus 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD) 4 = 128 bit BUS (RSVD)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_BUS_WIDTH_SHIFT                      _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_BUS_WIDTH_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_BUS_WIDTH_RANGE                      30:28
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_BUS_WIDTH_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT                    _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_8                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_16                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_32                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_64                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_128                      _MK_ENUM_CONST(4)
+
+// when enabled the data going  to APB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_DATA_SWAP_SHIFT                      _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_DATA_SWAP_FIELD                      (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_DATA_SWAP_RANGE                      27:27
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_DATA_SWAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_DATA_SWAP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_DATA_SWAP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_DATA_SWAP_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_DATA_SWAP_ENABLE                     _MK_ENUM_CONST(1)
+
+//APB Address Wrap-around Window 0 = No Wrap 1 = Wrap on 1 Word Window (def) 2 = Wrap on 2 Word Window 3 = Wrap on 4 Word Window 4 = Wrap on 8 Word Window 5 = Wrap on 16 Word Window 6 = Wrap on 32 Word Window 7 = Wrap on 64 Word Window (rsvd)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_ADDR_WRAP_SHIFT                      _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_ADDR_WRAP_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_ADDR_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_ADDR_WRAP_RANGE                      18:16
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_ADDR_WRAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_ADDR_WRAP_NO_WRAP                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_ADDR_WRAP_WRAP_0N_1WORDS                     _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_2WORDS                     _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_4WORDS                     _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_8WORDS                     _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_16WORDS                    _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_32WORDS                    _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_64WORDS                    _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_3_CSR_0  
+#define APBDMACHAN_CHANNEL_3_CSR_0                      _MK_ADDR_CONST(0x60)
+#define APBDMACHAN_CHANNEL_3_CSR_0_SECURE                       0x0
+#define APBDMACHAN_CHANNEL_3_CSR_0_WORD_COUNT                   0x1
+#define APBDMACHAN_CHANNEL_3_CSR_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_RESET_MASK                   _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_3_CSR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_READ_MASK                    _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_3_CSR_0_WRITE_MASK                   _MK_MASK_CONST(0xfffffffc)
+// Enables DMA channel transfer 
+#define APBDMACHAN_CHANNEL_3_CSR_0_ENB_SHIFT                    _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_3_CSR_0_ENB_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_3_CSR_0_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_3_CSR_0_ENB_RANGE                    31:31
+#define APBDMACHAN_CHANNEL_3_CSR_0_ENB_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_3_CSR_0_ENB_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_ENB_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_3_CSR_0_ENB_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_ENB_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_ENB_DISABLE                  _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_ENB_ENABLE                   _MK_ENUM_CONST(1)
+
+// Interrupts when DMA Block Transfer Completes 
+#define APBDMACHAN_CHANNEL_3_CSR_0_IE_EOC_SHIFT                 _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_3_CSR_0_IE_EOC_FIELD                 (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_3_CSR_0_IE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_3_CSR_0_IE_EOC_RANGE                 30:30
+#define APBDMACHAN_CHANNEL_3_CSR_0_IE_EOC_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_3_CSR_0_IE_EOC_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_IE_EOC_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_3_CSR_0_IE_EOC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_IE_EOC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_IE_EOC_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_IE_EOC_ENABLE                        _MK_ENUM_CONST(1)
+
+// Holds this Processor until DMA Block Transfer Completes 
+#define APBDMACHAN_CHANNEL_3_CSR_0_HOLD_SHIFT                   _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_3_CSR_0_HOLD_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_3_CSR_0_HOLD_SHIFT)
+#define APBDMACHAN_CHANNEL_3_CSR_0_HOLD_RANGE                   29:29
+#define APBDMACHAN_CHANNEL_3_CSR_0_HOLD_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_3_CSR_0_HOLD_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_HOLD_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_3_CSR_0_HOLD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_HOLD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_HOLD_DISABLE                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_HOLD_ENABLE                  _MK_ENUM_CONST(1)
+
+// DMA Transfer Direction 1 = AHB read to APB write 0 = APB read to AHB write
+#define APBDMACHAN_CHANNEL_3_CSR_0_DIR_SHIFT                    _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_3_CSR_0_DIR_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_3_CSR_0_DIR_SHIFT)
+#define APBDMACHAN_CHANNEL_3_CSR_0_DIR_RANGE                    28:28
+#define APBDMACHAN_CHANNEL_3_CSR_0_DIR_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_3_CSR_0_DIR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_DIR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_3_CSR_0_DIR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_DIR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_DIR_AHB_WRITE                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_DIR_AHB_READ                 _MK_ENUM_CONST(1)
+
+// Run Once or Run Multiple Mode (Allow Retriggering of this Channel) 1 = Run for One Block Transfer 0 = Run for Multiple Block Transfer
+#define APBDMACHAN_CHANNEL_3_CSR_0_ONCE_SHIFT                   _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_3_CSR_0_ONCE_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_3_CSR_0_ONCE_SHIFT)
+#define APBDMACHAN_CHANNEL_3_CSR_0_ONCE_RANGE                   27:27
+#define APBDMACHAN_CHANNEL_3_CSR_0_ONCE_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_3_CSR_0_ONCE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_ONCE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_3_CSR_0_ONCE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_ONCE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_ONCE_MULTIPLE_BLOCK                  _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_ONCE_SINGLE_BLOCK                    _MK_ENUM_CONST(1)
+
+// Enable on Non-Zero Value
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_SHIFT                       _MK_SHIFT_CONST(22)
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_FIELD                       (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_RANGE                       26:22
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_NA1                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_SMP24                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_SMP25                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_SMP26                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_SMP27                       _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_XRQ_A                       _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_XRQ_B                       _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_TMR1                        _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_TMR2                        _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_APB_0                       _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_APB_1                       _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_APB_2                       _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_APB_3                       _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_APB_4                       _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_APB_5                       _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_APB_6                       _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_APB_7                       _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_APB_8                       _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_APB_9                       _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_APB_10                      _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_APB_11                      _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_APB_12                      _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_APB_13                      _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_APB_14                      _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_APB_15                      _MK_ENUM_CONST(24)
+
+// Flow Control Enable (Synchronize Burst Transfers) 1 = Link to DRQ source 0 = Independent of DRQ request
+#define APBDMACHAN_CHANNEL_3_CSR_0_FLOW_SHIFT                   _MK_SHIFT_CONST(21)
+#define APBDMACHAN_CHANNEL_3_CSR_0_FLOW_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_3_CSR_0_FLOW_SHIFT)
+#define APBDMACHAN_CHANNEL_3_CSR_0_FLOW_RANGE                   21:21
+#define APBDMACHAN_CHANNEL_3_CSR_0_FLOW_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_3_CSR_0_FLOW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_FLOW_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_3_CSR_0_FLOW_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_FLOW_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_FLOW_DISABLE                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_FLOW_ENABLE                  _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_SHIFT                        _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_FIELD                        (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_RANGE                        20:16
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_CNTR_REQ                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_I2S_2                        _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_I2S_1                        _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_SPD_I                        _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_UI_I                 _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_MIPI                 _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_I2S2_2                       _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_I2S2_1                       _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_UART_A                       _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_UART_B                       _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_UART_C                       _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_SPI                  _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_AC97                 _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_ACModem                      _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_SL4B                 _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_SL2B1                        _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_SL2B2                        _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_SL2B3                        _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_SL2B4                        _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_UART_D                       _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_UART_E                       _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_I2C                  _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_I2C2                 _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_I2C3                 _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_DVC_I2C                      _MK_ENUM_CONST(24)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_OWR                  _MK_ENUM_CONST(25)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_NA26                 _MK_ENUM_CONST(26)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_NA27                 _MK_ENUM_CONST(27)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_NA28                 _MK_ENUM_CONST(28)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_NA29                 _MK_ENUM_CONST(29)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_NA30                 _MK_ENUM_CONST(30)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_NA31                 _MK_ENUM_CONST(31)
+
+// Number of 32bit word cycles
+#define APBDMACHAN_CHANNEL_3_CSR_0_WCOUNT_SHIFT                 _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_3_CSR_0_WCOUNT_FIELD                 (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_3_CSR_0_WCOUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_3_CSR_0_WCOUNT_RANGE                 15:2
+#define APBDMACHAN_CHANNEL_3_CSR_0_WCOUNT_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_3_CSR_0_WCOUNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_WCOUNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_3_CSR_0_WCOUNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_WCOUNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_3_STA_0  
+#define APBDMACHAN_CHANNEL_3_STA_0                      _MK_ADDR_CONST(0x64)
+#define APBDMACHAN_CHANNEL_3_STA_0_SECURE                       0x0
+#define APBDMACHAN_CHANNEL_3_STA_0_WORD_COUNT                   0x1
+#define APBDMACHAN_CHANNEL_3_STA_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_STA_0_RESET_MASK                   _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_3_STA_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_STA_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_STA_0_READ_MASK                    _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_3_STA_0_WRITE_MASK                   _MK_MASK_CONST(0x40000000)
+// indicates whether DMA Channel Status active
+#define APBDMACHAN_CHANNEL_3_STA_0_BSY_SHIFT                    _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_3_STA_0_BSY_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_3_STA_0_BSY_SHIFT)
+#define APBDMACHAN_CHANNEL_3_STA_0_BSY_RANGE                    31:31
+#define APBDMACHAN_CHANNEL_3_STA_0_BSY_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_3_STA_0_BSY_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_STA_0_BSY_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_3_STA_0_BSY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_STA_0_BSY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_STA_0_BSY_WAIT                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_3_STA_0_BSY_ACTIVE                   _MK_ENUM_CONST(1)
+
+//  Write '1' to clear the flag
+#define APBDMACHAN_CHANNEL_3_STA_0_ISE_EOC_SHIFT                        _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_3_STA_0_ISE_EOC_FIELD                        (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_3_STA_0_ISE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_3_STA_0_ISE_EOC_RANGE                        30:30
+#define APBDMACHAN_CHANNEL_3_STA_0_ISE_EOC_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_3_STA_0_ISE_EOC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_STA_0_ISE_EOC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_3_STA_0_ISE_EOC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_STA_0_ISE_EOC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_STA_0_ISE_EOC_NO_INTR                      _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_3_STA_0_ISE_EOC_INTR                 _MK_ENUM_CONST(1)
+
+// Holding Status of Processor 
+#define APBDMACHAN_CHANNEL_3_STA_0_HALT_SHIFT                   _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_3_STA_0_HALT_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_3_STA_0_HALT_SHIFT)
+#define APBDMACHAN_CHANNEL_3_STA_0_HALT_RANGE                   29:29
+#define APBDMACHAN_CHANNEL_3_STA_0_HALT_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_3_STA_0_HALT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_STA_0_HALT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_3_STA_0_HALT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_STA_0_HALT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_STA_0_HALT_NO_HALT                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_3_STA_0_HALT_HALT                    _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_3_STA_0_PING_PONG_STA_SHIFT                  _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_3_STA_0_PING_PONG_STA_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_3_STA_0_PING_PONG_STA_SHIFT)
+#define APBDMACHAN_CHANNEL_3_STA_0_PING_PONG_STA_RANGE                  28:28
+#define APBDMACHAN_CHANNEL_3_STA_0_PING_PONG_STA_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_3_STA_0_PING_PONG_STA_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_STA_0_PING_PONG_STA_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_3_STA_0_PING_PONG_STA_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_STA_0_PING_PONG_STA_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_STA_0_PING_PONG_STA_PING_INTR_STA                  _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_3_STA_0_PING_PONG_STA_PONG_INTR_STA                  _MK_ENUM_CONST(1)
+
+// Current 32bit word cycles Flags set /cleared by HW
+#define APBDMACHAN_CHANNEL_3_STA_0_COUNT_SHIFT                  _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_3_STA_0_COUNT_FIELD                  (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_3_STA_0_COUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_3_STA_0_COUNT_RANGE                  15:2
+#define APBDMACHAN_CHANNEL_3_STA_0_COUNT_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_3_STA_0_COUNT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_STA_0_COUNT_DEFAULT_MASK                   _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_3_STA_0_COUNT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_STA_0_COUNT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Reserved address 104 [0x68] 
+
+// Reserved address 108 [0x6c] 
+
+// Register APBDMACHAN_CHANNEL_3_AHB_PTR_0  
+#define APBDMACHAN_CHANNEL_3_AHB_PTR_0                  _MK_ADDR_CONST(0x70)
+#define APBDMACHAN_CHANNEL_3_AHB_PTR_0_SECURE                   0x0
+#define APBDMACHAN_CHANNEL_3_AHB_PTR_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_3_AHB_PTR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_AHB_PTR_0_RESET_MASK                       _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_3_AHB_PTR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_AHB_PTR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_AHB_PTR_0_READ_MASK                        _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_3_AHB_PTR_0_WRITE_MASK                       _MK_MASK_CONST(0xfffffffc)
+// APB-DMA Starting Address for AHB Bus: SW writes to  modify
+#define APBDMACHAN_CHANNEL_3_AHB_PTR_0_AHB_BASE_SHIFT                   _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_3_AHB_PTR_0_AHB_BASE_FIELD                   (_MK_MASK_CONST(0x3fffffff) << APBDMACHAN_CHANNEL_3_AHB_PTR_0_AHB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_3_AHB_PTR_0_AHB_BASE_RANGE                   31:2
+#define APBDMACHAN_CHANNEL_3_AHB_PTR_0_AHB_BASE_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_3_AHB_PTR_0_AHB_BASE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_AHB_PTR_0_AHB_BASE_DEFAULT_MASK                    _MK_MASK_CONST(0x3fffffff)
+#define APBDMACHAN_CHANNEL_3_AHB_PTR_0_AHB_BASE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_AHB_PTR_0_AHB_BASE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_3_AHB_SEQ_0  
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0                  _MK_ADDR_CONST(0x74)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_SECURE                   0x0
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_RESET_VAL                        _MK_MASK_CONST(0x20000000)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_RESET_MASK                       _MK_MASK_CONST(0xff070000)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_READ_MASK                        _MK_MASK_CONST(0xff070000)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_WRITE_MASK                       _MK_MASK_CONST(0xff070000)
+//  0 = send interrupt to COP                                            
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_INTR_ENB_SHIFT                   _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_INTR_ENB_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_3_AHB_SEQ_0_INTR_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_INTR_ENB_RANGE                   31:31
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_INTR_ENB_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_INTR_ENB_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_INTR_ENB_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_INTR_ENB_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_INTR_ENB_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_INTR_ENB_CPU                     _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_INTR_ENB_COP                     _MK_ENUM_CONST(0)
+
+// AHB Bus Width 0 = 8 bit Bus (RSVD) 1 = 16 bit Bus (RSVD) 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD)4 = 128 bit Bus (RSVD)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT                      _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_BUS_WIDTH_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_BUS_WIDTH_RANGE                      30:28
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_BUS_WIDTH_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT                    _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_8                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_16                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_32                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_64                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_128                      _MK_ENUM_CONST(4)
+
+// When enabled the data going  to AHB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT                      _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_DATA_SWAP_FIELD                      (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_DATA_SWAP_RANGE                      27:27
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_DATA_SWAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_DATA_SWAP_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_DATA_SWAP_ENABLE                     _MK_ENUM_CONST(1)
+
+// AHB Burst Size DMA Burst Length (encoded) 4 = 1 Word (1x32bits) 5 = 4 Words (4x32bits)else = 8 Words (8x32bits) default
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_BURST_SHIFT                  _MK_SHIFT_CONST(24)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_BURST_FIELD                  (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_BURST_SHIFT)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_BURST_RANGE                  26:24
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_BURST_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_BURST_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_BURST_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_BURST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_BURST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_BURST_DMA_BURST_1WORDS                       _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_BURST_DMA_BURST_4WORDS                       _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_BURST_DMA_BURST_8WORDS                       _MK_ENUM_CONST(6)
+
+// AHB Address Wrap: AHB Address wrap-around window 0=No Wrap (default) 5=Wrap on 512 word window 1=Wrap on 32 word window 6=Wrap on 1024 word window 2=Wrap on 64 word window 7=Wrap on 2048 word window 3=Wrap on 128 word window 4=Wrap on 256 word window
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_WRAP_SHIFT                       _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_WRAP_FIELD                       (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_3_AHB_SEQ_0_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_WRAP_RANGE                       18:16
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_WRAP_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_WRAP_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_WRAP_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_WRAP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_WRAP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_WRAP_NO_WRAP                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_WRAP_WRAP_0N_32WORDS                     _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_WRAP_WRAP_ON_64WORDS                     _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_WRAP_WRAP_ON_128WORDS                    _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_WRAP_WRAP_ON_256WORDS                    _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_WRAP_WRAP_ON_512WORDS                    _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_WRAP_WRAP_ON_1024WORDS                   _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_WRAP_WRAP_ON_2048WORDS                   _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_3_APB_PTR_0  
+#define APBDMACHAN_CHANNEL_3_APB_PTR_0                  _MK_ADDR_CONST(0x78)
+#define APBDMACHAN_CHANNEL_3_APB_PTR_0_SECURE                   0x0
+#define APBDMACHAN_CHANNEL_3_APB_PTR_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_3_APB_PTR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_APB_PTR_0_RESET_MASK                       _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_3_APB_PTR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_APB_PTR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_APB_PTR_0_READ_MASK                        _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_3_APB_PTR_0_WRITE_MASK                       _MK_MASK_CONST(0xfffc)
+// APB-DMA Starting address for APB Bus: APB Base  address: Upper 16 bits are fixed at 0x7000:XXXX
+#define APBDMACHAN_CHANNEL_3_APB_PTR_0_APB_BASE_SHIFT                   _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_3_APB_PTR_0_APB_BASE_FIELD                   (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_3_APB_PTR_0_APB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_3_APB_PTR_0_APB_BASE_RANGE                   15:2
+#define APBDMACHAN_CHANNEL_3_APB_PTR_0_APB_BASE_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_3_APB_PTR_0_APB_BASE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_APB_PTR_0_APB_BASE_DEFAULT_MASK                    _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_3_APB_PTR_0_APB_BASE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_APB_PTR_0_APB_BASE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_3_APB_SEQ_0  
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0                  _MK_ADDR_CONST(0x7c)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_SECURE                   0x0
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_RESET_VAL                        _MK_MASK_CONST(0x20010000)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_RESET_MASK                       _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_READ_MASK                        _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_WRITE_MASK                       _MK_MASK_CONST(0x78070000)
+// 0 = 8 bit Bus 1 = 16 bit Bus 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD) 4 = 128 bit BUS (RSVD)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_BUS_WIDTH_SHIFT                      _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_BUS_WIDTH_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_BUS_WIDTH_RANGE                      30:28
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_BUS_WIDTH_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT                    _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_8                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_16                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_32                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_64                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_128                      _MK_ENUM_CONST(4)
+
+// when enabled the data going  to APB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_DATA_SWAP_SHIFT                      _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_DATA_SWAP_FIELD                      (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_DATA_SWAP_RANGE                      27:27
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_DATA_SWAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_DATA_SWAP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_DATA_SWAP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_DATA_SWAP_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_DATA_SWAP_ENABLE                     _MK_ENUM_CONST(1)
+
+//APB Address Wrap-around Window 0 = No Wrap 1 = Wrap on 1 Word Window (def) 2 = Wrap on 2 Word Window 3 = Wrap on 4 Word Window 4 = Wrap on 8 Word Window 5 = Wrap on 16 Word Window 6 = Wrap on 32 Word Window 7 = Wrap on 64 Word Window (rsvd)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_ADDR_WRAP_SHIFT                      _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_ADDR_WRAP_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_ADDR_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_ADDR_WRAP_RANGE                      18:16
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_ADDR_WRAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_ADDR_WRAP_NO_WRAP                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_ADDR_WRAP_WRAP_0N_1WORDS                     _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_2WORDS                     _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_4WORDS                     _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_8WORDS                     _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_16WORDS                    _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_32WORDS                    _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_64WORDS                    _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_4_CSR_0  
+#define APBDMACHAN_CHANNEL_4_CSR_0                      _MK_ADDR_CONST(0x80)
+#define APBDMACHAN_CHANNEL_4_CSR_0_SECURE                       0x0
+#define APBDMACHAN_CHANNEL_4_CSR_0_WORD_COUNT                   0x1
+#define APBDMACHAN_CHANNEL_4_CSR_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_RESET_MASK                   _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_4_CSR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_READ_MASK                    _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_4_CSR_0_WRITE_MASK                   _MK_MASK_CONST(0xfffffffc)
+// Enables DMA channel transfer 
+#define APBDMACHAN_CHANNEL_4_CSR_0_ENB_SHIFT                    _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_4_CSR_0_ENB_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_4_CSR_0_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_4_CSR_0_ENB_RANGE                    31:31
+#define APBDMACHAN_CHANNEL_4_CSR_0_ENB_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_4_CSR_0_ENB_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_ENB_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_4_CSR_0_ENB_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_ENB_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_ENB_DISABLE                  _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_ENB_ENABLE                   _MK_ENUM_CONST(1)
+
+// Interrupts when DMA Block Transfer Completes 
+#define APBDMACHAN_CHANNEL_4_CSR_0_IE_EOC_SHIFT                 _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_4_CSR_0_IE_EOC_FIELD                 (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_4_CSR_0_IE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_4_CSR_0_IE_EOC_RANGE                 30:30
+#define APBDMACHAN_CHANNEL_4_CSR_0_IE_EOC_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_4_CSR_0_IE_EOC_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_IE_EOC_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_4_CSR_0_IE_EOC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_IE_EOC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_IE_EOC_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_IE_EOC_ENABLE                        _MK_ENUM_CONST(1)
+
+// Holds this Processor until DMA Block Transfer Completes 
+#define APBDMACHAN_CHANNEL_4_CSR_0_HOLD_SHIFT                   _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_4_CSR_0_HOLD_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_4_CSR_0_HOLD_SHIFT)
+#define APBDMACHAN_CHANNEL_4_CSR_0_HOLD_RANGE                   29:29
+#define APBDMACHAN_CHANNEL_4_CSR_0_HOLD_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_4_CSR_0_HOLD_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_HOLD_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_4_CSR_0_HOLD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_HOLD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_HOLD_DISABLE                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_HOLD_ENABLE                  _MK_ENUM_CONST(1)
+
+// DMA Transfer Direction 1 = AHB read to APB write 0 = APB read to AHB write
+#define APBDMACHAN_CHANNEL_4_CSR_0_DIR_SHIFT                    _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_4_CSR_0_DIR_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_4_CSR_0_DIR_SHIFT)
+#define APBDMACHAN_CHANNEL_4_CSR_0_DIR_RANGE                    28:28
+#define APBDMACHAN_CHANNEL_4_CSR_0_DIR_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_4_CSR_0_DIR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_DIR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_4_CSR_0_DIR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_DIR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_DIR_AHB_WRITE                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_DIR_AHB_READ                 _MK_ENUM_CONST(1)
+
+// Run Once or Run Multiple Mode (Allow Retriggering of this Channel) 1 = Run for One Block Transfer 0 = Run for Multiple Block Transfer
+#define APBDMACHAN_CHANNEL_4_CSR_0_ONCE_SHIFT                   _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_4_CSR_0_ONCE_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_4_CSR_0_ONCE_SHIFT)
+#define APBDMACHAN_CHANNEL_4_CSR_0_ONCE_RANGE                   27:27
+#define APBDMACHAN_CHANNEL_4_CSR_0_ONCE_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_4_CSR_0_ONCE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_ONCE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_4_CSR_0_ONCE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_ONCE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_ONCE_MULTIPLE_BLOCK                  _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_ONCE_SINGLE_BLOCK                    _MK_ENUM_CONST(1)
+
+// Enable on Non-Zero Value
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_SHIFT                       _MK_SHIFT_CONST(22)
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_FIELD                       (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_RANGE                       26:22
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_NA1                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_SMP24                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_SMP25                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_SMP26                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_SMP27                       _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_XRQ_A                       _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_XRQ_B                       _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_TMR1                        _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_TMR2                        _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_APB_0                       _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_APB_1                       _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_APB_2                       _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_APB_3                       _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_APB_4                       _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_APB_5                       _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_APB_6                       _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_APB_7                       _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_APB_8                       _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_APB_9                       _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_APB_10                      _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_APB_11                      _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_APB_12                      _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_APB_13                      _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_APB_14                      _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_APB_15                      _MK_ENUM_CONST(24)
+
+// Flow Control Enable (Synchronize Burst Transfers) 1 = Link to DRQ source 0 = Independent of DRQ request
+#define APBDMACHAN_CHANNEL_4_CSR_0_FLOW_SHIFT                   _MK_SHIFT_CONST(21)
+#define APBDMACHAN_CHANNEL_4_CSR_0_FLOW_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_4_CSR_0_FLOW_SHIFT)
+#define APBDMACHAN_CHANNEL_4_CSR_0_FLOW_RANGE                   21:21
+#define APBDMACHAN_CHANNEL_4_CSR_0_FLOW_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_4_CSR_0_FLOW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_FLOW_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_4_CSR_0_FLOW_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_FLOW_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_FLOW_DISABLE                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_FLOW_ENABLE                  _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_SHIFT                        _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_FIELD                        (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_RANGE                        20:16
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_CNTR_REQ                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_I2S_2                        _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_I2S_1                        _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_SPD_I                        _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_UI_I                 _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_MIPI                 _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_I2S2_2                       _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_I2S2_1                       _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_UART_A                       _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_UART_B                       _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_UART_C                       _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_SPI                  _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_AC97                 _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_ACModem                      _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_SL4B                 _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_SL2B1                        _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_SL2B2                        _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_SL2B3                        _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_SL2B4                        _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_UART_D                       _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_UART_E                       _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_I2C                  _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_I2C2                 _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_I2C3                 _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_DVC_I2C                      _MK_ENUM_CONST(24)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_OWR                  _MK_ENUM_CONST(25)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_NA26                 _MK_ENUM_CONST(26)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_NA27                 _MK_ENUM_CONST(27)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_NA28                 _MK_ENUM_CONST(28)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_NA29                 _MK_ENUM_CONST(29)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_NA30                 _MK_ENUM_CONST(30)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_NA31                 _MK_ENUM_CONST(31)
+
+// Number of 32bit word cycles
+#define APBDMACHAN_CHANNEL_4_CSR_0_WCOUNT_SHIFT                 _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_4_CSR_0_WCOUNT_FIELD                 (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_4_CSR_0_WCOUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_4_CSR_0_WCOUNT_RANGE                 15:2
+#define APBDMACHAN_CHANNEL_4_CSR_0_WCOUNT_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_4_CSR_0_WCOUNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_WCOUNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_4_CSR_0_WCOUNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_WCOUNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_4_STA_0  
+#define APBDMACHAN_CHANNEL_4_STA_0                      _MK_ADDR_CONST(0x84)
+#define APBDMACHAN_CHANNEL_4_STA_0_SECURE                       0x0
+#define APBDMACHAN_CHANNEL_4_STA_0_WORD_COUNT                   0x1
+#define APBDMACHAN_CHANNEL_4_STA_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_STA_0_RESET_MASK                   _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_4_STA_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_STA_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_STA_0_READ_MASK                    _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_4_STA_0_WRITE_MASK                   _MK_MASK_CONST(0x40000000)
+// indicates whether DMA Channel Status active or not
+#define APBDMACHAN_CHANNEL_4_STA_0_BSY_SHIFT                    _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_4_STA_0_BSY_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_4_STA_0_BSY_SHIFT)
+#define APBDMACHAN_CHANNEL_4_STA_0_BSY_RANGE                    31:31
+#define APBDMACHAN_CHANNEL_4_STA_0_BSY_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_4_STA_0_BSY_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_STA_0_BSY_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_4_STA_0_BSY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_STA_0_BSY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_STA_0_BSY_WAIT                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_4_STA_0_BSY_ACTIVE                   _MK_ENUM_CONST(1)
+
+//  Write '1' to clear the flag
+#define APBDMACHAN_CHANNEL_4_STA_0_ISE_EOC_SHIFT                        _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_4_STA_0_ISE_EOC_FIELD                        (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_4_STA_0_ISE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_4_STA_0_ISE_EOC_RANGE                        30:30
+#define APBDMACHAN_CHANNEL_4_STA_0_ISE_EOC_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_4_STA_0_ISE_EOC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_STA_0_ISE_EOC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_4_STA_0_ISE_EOC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_STA_0_ISE_EOC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_STA_0_ISE_EOC_NO_INTR                      _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_4_STA_0_ISE_EOC_INTR                 _MK_ENUM_CONST(1)
+
+// Holding Status of Processor 
+#define APBDMACHAN_CHANNEL_4_STA_0_HALT_SHIFT                   _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_4_STA_0_HALT_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_4_STA_0_HALT_SHIFT)
+#define APBDMACHAN_CHANNEL_4_STA_0_HALT_RANGE                   29:29
+#define APBDMACHAN_CHANNEL_4_STA_0_HALT_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_4_STA_0_HALT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_STA_0_HALT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_4_STA_0_HALT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_STA_0_HALT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_STA_0_HALT_NO_HALT                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_4_STA_0_HALT_HALT                    _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_4_STA_0_PING_PONG_STA_SHIFT                  _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_4_STA_0_PING_PONG_STA_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_4_STA_0_PING_PONG_STA_SHIFT)
+#define APBDMACHAN_CHANNEL_4_STA_0_PING_PONG_STA_RANGE                  28:28
+#define APBDMACHAN_CHANNEL_4_STA_0_PING_PONG_STA_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_4_STA_0_PING_PONG_STA_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_STA_0_PING_PONG_STA_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_4_STA_0_PING_PONG_STA_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_STA_0_PING_PONG_STA_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_STA_0_PING_PONG_STA_PING_INTR_STA                  _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_4_STA_0_PING_PONG_STA_PONG_INTR_STA                  _MK_ENUM_CONST(1)
+
+// Current 32bit word cycles Flags set /cleared by HW
+#define APBDMACHAN_CHANNEL_4_STA_0_COUNT_SHIFT                  _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_4_STA_0_COUNT_FIELD                  (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_4_STA_0_COUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_4_STA_0_COUNT_RANGE                  15:2
+#define APBDMACHAN_CHANNEL_4_STA_0_COUNT_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_4_STA_0_COUNT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_STA_0_COUNT_DEFAULT_MASK                   _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_4_STA_0_COUNT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_STA_0_COUNT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Reserved address 136 [0x88] 
+
+// Reserved address 140 [0x8c] 
+
+// Register APBDMACHAN_CHANNEL_4_AHB_PTR_0  
+#define APBDMACHAN_CHANNEL_4_AHB_PTR_0                  _MK_ADDR_CONST(0x90)
+#define APBDMACHAN_CHANNEL_4_AHB_PTR_0_SECURE                   0x0
+#define APBDMACHAN_CHANNEL_4_AHB_PTR_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_4_AHB_PTR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_AHB_PTR_0_RESET_MASK                       _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_4_AHB_PTR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_AHB_PTR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_AHB_PTR_0_READ_MASK                        _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_4_AHB_PTR_0_WRITE_MASK                       _MK_MASK_CONST(0xfffffffc)
+// APB-DMA Starting Address for AHB Bus: SW writes to  modify
+#define APBDMACHAN_CHANNEL_4_AHB_PTR_0_AHB_BASE_SHIFT                   _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_4_AHB_PTR_0_AHB_BASE_FIELD                   (_MK_MASK_CONST(0x3fffffff) << APBDMACHAN_CHANNEL_4_AHB_PTR_0_AHB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_4_AHB_PTR_0_AHB_BASE_RANGE                   31:2
+#define APBDMACHAN_CHANNEL_4_AHB_PTR_0_AHB_BASE_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_4_AHB_PTR_0_AHB_BASE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_AHB_PTR_0_AHB_BASE_DEFAULT_MASK                    _MK_MASK_CONST(0x3fffffff)
+#define APBDMACHAN_CHANNEL_4_AHB_PTR_0_AHB_BASE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_AHB_PTR_0_AHB_BASE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_4_AHB_SEQ_0  
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0                  _MK_ADDR_CONST(0x94)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_SECURE                   0x0
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_RESET_VAL                        _MK_MASK_CONST(0x20000000)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_RESET_MASK                       _MK_MASK_CONST(0xff0f0000)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_READ_MASK                        _MK_MASK_CONST(0xff0f0000)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_WRITE_MASK                       _MK_MASK_CONST(0xff0f0000)
+//  0 = send interrupt to COP
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_INTR_ENB_SHIFT                   _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_INTR_ENB_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_4_AHB_SEQ_0_INTR_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_INTR_ENB_RANGE                   31:31
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_INTR_ENB_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_INTR_ENB_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_INTR_ENB_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_INTR_ENB_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_INTR_ENB_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_INTR_ENB_CPU                     _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_INTR_ENB_COP                     _MK_ENUM_CONST(0)
+
+// AHB Bus Width 0 = 8 bit Bus (RSVD) 1 = 16 bit Bus (RSVD) 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD)4 = 128 bit Bus (RSVD)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT                      _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_BUS_WIDTH_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_BUS_WIDTH_RANGE                      30:28
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_BUS_WIDTH_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT                    _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_8                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_16                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_32                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_64                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_128                      _MK_ENUM_CONST(4)
+
+// when enabled the data going  to AHB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT                      _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_DATA_SWAP_FIELD                      (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_DATA_SWAP_RANGE                      27:27
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_DATA_SWAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_DATA_SWAP_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_DATA_SWAP_ENABLE                     _MK_ENUM_CONST(1)
+
+// AHB Burst Size DMA Burst Length (encoded) 4 = 1 Word (1x32bits) 5 = 4 Words (4x32bits)else = 8 Words (8x32bits) default
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_BURST_SHIFT                  _MK_SHIFT_CONST(24)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_BURST_FIELD                  (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_BURST_SHIFT)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_BURST_RANGE                  26:24
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_BURST_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_BURST_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_BURST_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_BURST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_BURST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_BURST_DMA_BURST_1WORDS                       _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_BURST_DMA_BURST_4WORDS                       _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_BURST_DMA_BURST_8WORDS                       _MK_ENUM_CONST(6)
+
+// 2X Double Buffering Mode (For Run-Multiple Mode with No Wrap Operations) 1 = Reload Base Address for 2X blocks (reload every other time) 0 = Reload Base Address for 1X blocks  (def) (reload each time)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_DBL_BUF_SHIFT                    _MK_SHIFT_CONST(19)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_DBL_BUF_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_4_AHB_SEQ_0_DBL_BUF_SHIFT)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_DBL_BUF_RANGE                    19:19
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_DBL_BUF_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_DBL_BUF_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_DBL_BUF_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_DBL_BUF_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_DBL_BUF_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_DBL_BUF_RELOAD_FOR_1X_BLOCKS                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_DBL_BUF_RELOAD_FOR_2X_BLOCKS                     _MK_ENUM_CONST(1)
+
+// AHB Address Wrap: AHB Address wrap-around window 0=No Wrap (default) 5=Wrap on 512 word window 1=Wrap on 32 word window 6=Wrap on 1024 word window 2=Wrap on 64 word window 7=Wrap on 2048 word window 3=Wrap on 128 word window 4=Wrap on 256 word window
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_WRAP_SHIFT                       _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_WRAP_FIELD                       (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_4_AHB_SEQ_0_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_WRAP_RANGE                       18:16
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_WRAP_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_WRAP_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_WRAP_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_WRAP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_WRAP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_WRAP_NO_WRAP                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_WRAP_WRAP_0N_32WORDS                     _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_WRAP_WRAP_ON_64WORDS                     _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_WRAP_WRAP_ON_128WORDS                    _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_WRAP_WRAP_ON_256WORDS                    _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_WRAP_WRAP_ON_512WORDS                    _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_WRAP_WRAP_ON_1024WORDS                   _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_WRAP_WRAP_ON_2048WORDS                   _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_4_APB_PTR_0  
+#define APBDMACHAN_CHANNEL_4_APB_PTR_0                  _MK_ADDR_CONST(0x98)
+#define APBDMACHAN_CHANNEL_4_APB_PTR_0_SECURE                   0x0
+#define APBDMACHAN_CHANNEL_4_APB_PTR_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_4_APB_PTR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_APB_PTR_0_RESET_MASK                       _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_4_APB_PTR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_APB_PTR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_APB_PTR_0_READ_MASK                        _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_4_APB_PTR_0_WRITE_MASK                       _MK_MASK_CONST(0xfffc)
+// APB-DMA Starting address for APB Bus: APB Base address:Upper 16 bits are fixed at 0x7000:XXXX
+#define APBDMACHAN_CHANNEL_4_APB_PTR_0_APB_BASE_SHIFT                   _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_4_APB_PTR_0_APB_BASE_FIELD                   (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_4_APB_PTR_0_APB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_4_APB_PTR_0_APB_BASE_RANGE                   15:2
+#define APBDMACHAN_CHANNEL_4_APB_PTR_0_APB_BASE_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_4_APB_PTR_0_APB_BASE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_APB_PTR_0_APB_BASE_DEFAULT_MASK                    _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_4_APB_PTR_0_APB_BASE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_APB_PTR_0_APB_BASE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_4_APB_SEQ_0  
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0                  _MK_ADDR_CONST(0x9c)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_SECURE                   0x0
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_RESET_VAL                        _MK_MASK_CONST(0x20010000)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_RESET_MASK                       _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_READ_MASK                        _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_WRITE_MASK                       _MK_MASK_CONST(0x78070000)
+// 0 = 8 bit Bus 1 = 16 bit Bus 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD) 4 = 128 bit BUS (RSVD)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_BUS_WIDTH_SHIFT                      _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_BUS_WIDTH_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_BUS_WIDTH_RANGE                      30:28
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_BUS_WIDTH_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT                    _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_8                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_16                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_32                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_64                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_128                      _MK_ENUM_CONST(4)
+
+// when enabled the data going  to APB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_DATA_SWAP_SHIFT                      _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_DATA_SWAP_FIELD                      (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_DATA_SWAP_RANGE                      27:27
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_DATA_SWAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_DATA_SWAP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_DATA_SWAP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_DATA_SWAP_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_DATA_SWAP_ENABLE                     _MK_ENUM_CONST(1)
+
+//APB Address Wrap-around Window 0 = No Wrap 1 = Wrap on 1 Word Window (def) 2 = Wrap on 2 Word Window 3 = Wrap on 4 Word Window 4 = Wrap on 8 Word Window 5 = Wrap on 16 Word Window 6 = Wrap on 32 Word Window 7 = Wrap on 64 Word Window (rsvd)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_ADDR_WRAP_SHIFT                      _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_ADDR_WRAP_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_ADDR_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_ADDR_WRAP_RANGE                      18:16
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_ADDR_WRAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_ADDR_WRAP_NO_WRAP                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_ADDR_WRAP_WRAP_0N_1WORDS                     _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_2WORDS                     _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_4WORDS                     _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_8WORDS                     _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_16WORDS                    _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_32WORDS                    _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_64WORDS                    _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_5_CSR_0  
+#define APBDMACHAN_CHANNEL_5_CSR_0                      _MK_ADDR_CONST(0xa0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_SECURE                       0x0
+#define APBDMACHAN_CHANNEL_5_CSR_0_WORD_COUNT                   0x1
+#define APBDMACHAN_CHANNEL_5_CSR_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_RESET_MASK                   _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_5_CSR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_READ_MASK                    _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_5_CSR_0_WRITE_MASK                   _MK_MASK_CONST(0xfffffffc)
+// Enables DMA channel transfer
+#define APBDMACHAN_CHANNEL_5_CSR_0_ENB_SHIFT                    _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_5_CSR_0_ENB_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_5_CSR_0_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_5_CSR_0_ENB_RANGE                    31:31
+#define APBDMACHAN_CHANNEL_5_CSR_0_ENB_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_5_CSR_0_ENB_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_ENB_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_5_CSR_0_ENB_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_ENB_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_ENB_DISABLE                  _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_ENB_ENABLE                   _MK_ENUM_CONST(1)
+
+// Interrupts when DMA Block Transfer Completes 
+#define APBDMACHAN_CHANNEL_5_CSR_0_IE_EOC_SHIFT                 _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_5_CSR_0_IE_EOC_FIELD                 (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_5_CSR_0_IE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_5_CSR_0_IE_EOC_RANGE                 30:30
+#define APBDMACHAN_CHANNEL_5_CSR_0_IE_EOC_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_5_CSR_0_IE_EOC_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_IE_EOC_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_5_CSR_0_IE_EOC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_IE_EOC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_IE_EOC_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_IE_EOC_ENABLE                        _MK_ENUM_CONST(1)
+
+// Holds this Processor until DMA Block Transfer Completes 
+#define APBDMACHAN_CHANNEL_5_CSR_0_HOLD_SHIFT                   _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_5_CSR_0_HOLD_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_5_CSR_0_HOLD_SHIFT)
+#define APBDMACHAN_CHANNEL_5_CSR_0_HOLD_RANGE                   29:29
+#define APBDMACHAN_CHANNEL_5_CSR_0_HOLD_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_5_CSR_0_HOLD_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_HOLD_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_5_CSR_0_HOLD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_HOLD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_HOLD_DISABLE                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_HOLD_ENABLE                  _MK_ENUM_CONST(1)
+
+// DMA Transfer Direction 1 = AHB read to APB write 0 = APB read to AHB write
+#define APBDMACHAN_CHANNEL_5_CSR_0_DIR_SHIFT                    _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_5_CSR_0_DIR_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_5_CSR_0_DIR_SHIFT)
+#define APBDMACHAN_CHANNEL_5_CSR_0_DIR_RANGE                    28:28
+#define APBDMACHAN_CHANNEL_5_CSR_0_DIR_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_5_CSR_0_DIR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_DIR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_5_CSR_0_DIR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_DIR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_DIR_AHB_WRITE                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_DIR_AHB_READ                 _MK_ENUM_CONST(1)
+
+// Run Once or Run Multiple Mode (Allow Retriggering of this Channel) 1 = Run for One Block Transfer 0 = Run for Multiple Block Transfer
+#define APBDMACHAN_CHANNEL_5_CSR_0_ONCE_SHIFT                   _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_5_CSR_0_ONCE_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_5_CSR_0_ONCE_SHIFT)
+#define APBDMACHAN_CHANNEL_5_CSR_0_ONCE_RANGE                   27:27
+#define APBDMACHAN_CHANNEL_5_CSR_0_ONCE_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_5_CSR_0_ONCE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_ONCE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_5_CSR_0_ONCE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_ONCE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_ONCE_MULTIPLE_BLOCK                  _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_ONCE_SINGLE_BLOCK                    _MK_ENUM_CONST(1)
+
+// Enable on Non-Zero Value
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_SHIFT                       _MK_SHIFT_CONST(22)
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_FIELD                       (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_RANGE                       26:22
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_NA1                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_SMP24                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_SMP25                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_SMP26                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_SMP27                       _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_XRQ_A                       _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_XRQ_B                       _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_TMR1                        _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_TMR2                        _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_APB_0                       _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_APB_1                       _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_APB_2                       _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_APB_3                       _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_APB_4                       _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_APB_5                       _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_APB_6                       _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_APB_7                       _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_APB_8                       _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_APB_9                       _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_APB_10                      _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_APB_11                      _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_APB_12                      _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_APB_13                      _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_APB_14                      _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_APB_15                      _MK_ENUM_CONST(24)
+
+// Flow Control Enable (Synchronize Burst Transfers) 1 = Link to DRQ source 0 = Independent of DRQ request
+#define APBDMACHAN_CHANNEL_5_CSR_0_FLOW_SHIFT                   _MK_SHIFT_CONST(21)
+#define APBDMACHAN_CHANNEL_5_CSR_0_FLOW_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_5_CSR_0_FLOW_SHIFT)
+#define APBDMACHAN_CHANNEL_5_CSR_0_FLOW_RANGE                   21:21
+#define APBDMACHAN_CHANNEL_5_CSR_0_FLOW_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_5_CSR_0_FLOW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_FLOW_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_5_CSR_0_FLOW_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_FLOW_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_FLOW_DISABLE                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_FLOW_ENABLE                  _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_SHIFT                        _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_FIELD                        (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_RANGE                        20:16
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_CNTR_REQ                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_I2S_2                        _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_I2S_1                        _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_SPD_I                        _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_UI_I                 _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_MIPI                 _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_I2S2_2                       _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_I2S2_1                       _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_UART_A                       _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_UART_B                       _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_UART_C                       _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_SPI                  _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_AC97                 _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_ACModem                      _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_SL4B                 _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_SL2B1                        _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_SL2B2                        _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_SL2B3                        _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_SL2B4                        _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_UART_D                       _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_UART_E                       _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_I2C                  _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_I2C2                 _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_I2C3                 _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_DVC_I2C                      _MK_ENUM_CONST(24)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_OWR                  _MK_ENUM_CONST(25)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_NA26                 _MK_ENUM_CONST(26)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_NA27                 _MK_ENUM_CONST(27)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_NA28                 _MK_ENUM_CONST(28)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_NA29                 _MK_ENUM_CONST(29)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_NA30                 _MK_ENUM_CONST(30)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_NA31                 _MK_ENUM_CONST(31)
+
+// Number of 32bit word cycles
+#define APBDMACHAN_CHANNEL_5_CSR_0_WCOUNT_SHIFT                 _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_5_CSR_0_WCOUNT_FIELD                 (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_5_CSR_0_WCOUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_5_CSR_0_WCOUNT_RANGE                 15:2
+#define APBDMACHAN_CHANNEL_5_CSR_0_WCOUNT_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_5_CSR_0_WCOUNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_WCOUNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_5_CSR_0_WCOUNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_WCOUNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_5_STA_0  
+#define APBDMACHAN_CHANNEL_5_STA_0                      _MK_ADDR_CONST(0xa4)
+#define APBDMACHAN_CHANNEL_5_STA_0_SECURE                       0x0
+#define APBDMACHAN_CHANNEL_5_STA_0_WORD_COUNT                   0x1
+#define APBDMACHAN_CHANNEL_5_STA_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_STA_0_RESET_MASK                   _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_5_STA_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_STA_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_STA_0_READ_MASK                    _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_5_STA_0_WRITE_MASK                   _MK_MASK_CONST(0x40000000)
+// indicate whether DMA Channel Status active or not
+#define APBDMACHAN_CHANNEL_5_STA_0_BSY_SHIFT                    _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_5_STA_0_BSY_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_5_STA_0_BSY_SHIFT)
+#define APBDMACHAN_CHANNEL_5_STA_0_BSY_RANGE                    31:31
+#define APBDMACHAN_CHANNEL_5_STA_0_BSY_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_5_STA_0_BSY_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_STA_0_BSY_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_5_STA_0_BSY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_STA_0_BSY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_STA_0_BSY_WAIT                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_5_STA_0_BSY_ACTIVE                   _MK_ENUM_CONST(1)
+
+//  Write '1' to clear the flag
+#define APBDMACHAN_CHANNEL_5_STA_0_ISE_EOC_SHIFT                        _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_5_STA_0_ISE_EOC_FIELD                        (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_5_STA_0_ISE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_5_STA_0_ISE_EOC_RANGE                        30:30
+#define APBDMACHAN_CHANNEL_5_STA_0_ISE_EOC_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_5_STA_0_ISE_EOC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_STA_0_ISE_EOC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_5_STA_0_ISE_EOC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_STA_0_ISE_EOC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_STA_0_ISE_EOC_NO_INTR                      _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_5_STA_0_ISE_EOC_INTR                 _MK_ENUM_CONST(1)
+
+// Holding Status of Processor
+#define APBDMACHAN_CHANNEL_5_STA_0_HALT_SHIFT                   _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_5_STA_0_HALT_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_5_STA_0_HALT_SHIFT)
+#define APBDMACHAN_CHANNEL_5_STA_0_HALT_RANGE                   29:29
+#define APBDMACHAN_CHANNEL_5_STA_0_HALT_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_5_STA_0_HALT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_STA_0_HALT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_5_STA_0_HALT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_STA_0_HALT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_STA_0_HALT_NO_HALT                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_5_STA_0_HALT_HALT                    _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_5_STA_0_PING_PONG_STA_SHIFT                  _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_5_STA_0_PING_PONG_STA_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_5_STA_0_PING_PONG_STA_SHIFT)
+#define APBDMACHAN_CHANNEL_5_STA_0_PING_PONG_STA_RANGE                  28:28
+#define APBDMACHAN_CHANNEL_5_STA_0_PING_PONG_STA_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_5_STA_0_PING_PONG_STA_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_STA_0_PING_PONG_STA_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_5_STA_0_PING_PONG_STA_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_STA_0_PING_PONG_STA_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_STA_0_PING_PONG_STA_PING_INTR_STA                  _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_5_STA_0_PING_PONG_STA_PONG_INTR_STA                  _MK_ENUM_CONST(1)
+
+// Current 32bit word cycles Flags set /cleared by HW
+#define APBDMACHAN_CHANNEL_5_STA_0_COUNT_SHIFT                  _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_5_STA_0_COUNT_FIELD                  (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_5_STA_0_COUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_5_STA_0_COUNT_RANGE                  15:2
+#define APBDMACHAN_CHANNEL_5_STA_0_COUNT_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_5_STA_0_COUNT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_STA_0_COUNT_DEFAULT_MASK                   _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_5_STA_0_COUNT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_STA_0_COUNT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Reserved address 168 [0xa8] 
+
+// Reserved address 172 [0xac] 
+
+// Register APBDMACHAN_CHANNEL_5_AHB_PTR_0  
+#define APBDMACHAN_CHANNEL_5_AHB_PTR_0                  _MK_ADDR_CONST(0xb0)
+#define APBDMACHAN_CHANNEL_5_AHB_PTR_0_SECURE                   0x0
+#define APBDMACHAN_CHANNEL_5_AHB_PTR_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_5_AHB_PTR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_AHB_PTR_0_RESET_MASK                       _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_5_AHB_PTR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_AHB_PTR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_AHB_PTR_0_READ_MASK                        _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_5_AHB_PTR_0_WRITE_MASK                       _MK_MASK_CONST(0xfffffffc)
+// APB-DMA Starting Address for AHB Bus: SW writes to  modify
+#define APBDMACHAN_CHANNEL_5_AHB_PTR_0_AHB_BASE_SHIFT                   _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_5_AHB_PTR_0_AHB_BASE_FIELD                   (_MK_MASK_CONST(0x3fffffff) << APBDMACHAN_CHANNEL_5_AHB_PTR_0_AHB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_5_AHB_PTR_0_AHB_BASE_RANGE                   31:2
+#define APBDMACHAN_CHANNEL_5_AHB_PTR_0_AHB_BASE_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_5_AHB_PTR_0_AHB_BASE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_AHB_PTR_0_AHB_BASE_DEFAULT_MASK                    _MK_MASK_CONST(0x3fffffff)
+#define APBDMACHAN_CHANNEL_5_AHB_PTR_0_AHB_BASE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_AHB_PTR_0_AHB_BASE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_5_AHB_SEQ_0  
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0                  _MK_ADDR_CONST(0xb4)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_SECURE                   0x0
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_RESET_VAL                        _MK_MASK_CONST(0x20000000)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_RESET_MASK                       _MK_MASK_CONST(0xff0f0000)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_READ_MASK                        _MK_MASK_CONST(0xff0f0000)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_WRITE_MASK                       _MK_MASK_CONST(0xff0f0000)
+//  0 = send interrupt to COP
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_INTR_ENB_SHIFT                   _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_INTR_ENB_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_5_AHB_SEQ_0_INTR_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_INTR_ENB_RANGE                   31:31
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_INTR_ENB_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_INTR_ENB_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_INTR_ENB_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_INTR_ENB_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_INTR_ENB_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_INTR_ENB_CPU                     _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_INTR_ENB_COP                     _MK_ENUM_CONST(0)
+
+// AHB Bus Width 0 = 8 bit Bus (RSVD) 1 = 16 bit Bus (RSVD) 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD)4 = 128 bit Bus (RSVD)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT                      _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_BUS_WIDTH_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_BUS_WIDTH_RANGE                      30:28
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_BUS_WIDTH_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT                    _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_8                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_16                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_32                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_64                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_128                      _MK_ENUM_CONST(4)
+
+// when enabled the data going  to AHB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT                      _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_DATA_SWAP_FIELD                      (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_DATA_SWAP_RANGE                      27:27
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_DATA_SWAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_DATA_SWAP_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_DATA_SWAP_ENABLE                     _MK_ENUM_CONST(1)
+
+// AHB Burst Size DMA Burst Length (encoded) 4 = 1 Word (1x32bits) 5 = 4 Words (4x32bits)else = 8 Words (8x32bits) default
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_BURST_SHIFT                  _MK_SHIFT_CONST(24)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_BURST_FIELD                  (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_BURST_SHIFT)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_BURST_RANGE                  26:24
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_BURST_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_BURST_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_BURST_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_BURST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_BURST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_BURST_DMA_BURST_1WORDS                       _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_BURST_DMA_BURST_4WORDS                       _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_BURST_DMA_BURST_8WORDS                       _MK_ENUM_CONST(6)
+
+// 2X Double Buffering Mode (For Run-Multiple Mode with No Wrap Operations) 1 = Reload Base Address for 2X blocks (reload every other time) 0 = Reload Base Address for 1X blocks  (def) (reload each time)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_DBL_BUF_SHIFT                    _MK_SHIFT_CONST(19)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_DBL_BUF_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_5_AHB_SEQ_0_DBL_BUF_SHIFT)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_DBL_BUF_RANGE                    19:19
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_DBL_BUF_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_DBL_BUF_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_DBL_BUF_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_DBL_BUF_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_DBL_BUF_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_DBL_BUF_RELOAD_FOR_1X_BLOCKS                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_DBL_BUF_RELOAD_FOR_2X_BLOCKS                     _MK_ENUM_CONST(1)
+
+// AHB Address Wrap: AHB Address wrap-around window 0=No Wrap (default) 5=Wrap on 512 word window 1=Wrap on 32 word window 6=Wrap on 1024 word window 2=Wrap on 64 word window 7=Wrap on 2048 word window 3=Wrap on 128 word window 4=Wrap on 256 word window
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_WRAP_SHIFT                       _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_WRAP_FIELD                       (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_5_AHB_SEQ_0_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_WRAP_RANGE                       18:16
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_WRAP_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_WRAP_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_WRAP_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_WRAP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_WRAP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_WRAP_NO_WRAP                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_WRAP_WRAP_0N_32WORDS                     _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_WRAP_WRAP_ON_64WORDS                     _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_WRAP_WRAP_ON_128WORDS                    _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_WRAP_WRAP_ON_256WORDS                    _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_WRAP_WRAP_ON_512WORDS                    _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_WRAP_WRAP_ON_1024WORDS                   _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_WRAP_WRAP_ON_2048WORDS                   _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_5_APB_PTR_0  
+#define APBDMACHAN_CHANNEL_5_APB_PTR_0                  _MK_ADDR_CONST(0xb8)
+#define APBDMACHAN_CHANNEL_5_APB_PTR_0_SECURE                   0x0
+#define APBDMACHAN_CHANNEL_5_APB_PTR_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_5_APB_PTR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_APB_PTR_0_RESET_MASK                       _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_5_APB_PTR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_APB_PTR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_APB_PTR_0_READ_MASK                        _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_5_APB_PTR_0_WRITE_MASK                       _MK_MASK_CONST(0xfffc)
+// APB-DMA Starting address for APB Bus: APB Base address:Upper 16 bits are fixed at 0x7000:XXXX
+#define APBDMACHAN_CHANNEL_5_APB_PTR_0_APB_BASE_SHIFT                   _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_5_APB_PTR_0_APB_BASE_FIELD                   (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_5_APB_PTR_0_APB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_5_APB_PTR_0_APB_BASE_RANGE                   15:2
+#define APBDMACHAN_CHANNEL_5_APB_PTR_0_APB_BASE_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_5_APB_PTR_0_APB_BASE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_APB_PTR_0_APB_BASE_DEFAULT_MASK                    _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_5_APB_PTR_0_APB_BASE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_APB_PTR_0_APB_BASE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_5_APB_SEQ_0  
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0                  _MK_ADDR_CONST(0xbc)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_SECURE                   0x0
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_RESET_VAL                        _MK_MASK_CONST(0x20010000)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_RESET_MASK                       _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_READ_MASK                        _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_WRITE_MASK                       _MK_MASK_CONST(0x78070000)
+// 0 = 8 bit Bus 1 = 16 bit Bus 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD) 4 = 128 bit BUS (RSVD)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_BUS_WIDTH_SHIFT                      _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_BUS_WIDTH_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_BUS_WIDTH_RANGE                      30:28
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_BUS_WIDTH_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT                    _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_8                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_16                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_32                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_64                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_128                      _MK_ENUM_CONST(4)
+
+// when enabled the data going  to APB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_DATA_SWAP_SHIFT                      _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_DATA_SWAP_FIELD                      (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_DATA_SWAP_RANGE                      27:27
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_DATA_SWAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_DATA_SWAP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_DATA_SWAP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_DATA_SWAP_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_DATA_SWAP_ENABLE                     _MK_ENUM_CONST(1)
+
+//APB Address Wrap-around Window 0 = No Wrap 1 = Wrap on 1 Word Window (def) 2 = Wrap on 2 Word Window 3 = Wrap on 4 Word Window 4 = Wrap on 8 Word Window 5 = Wrap on 16 Word Window 6 = Wrap on 32 Word Window 7 = Wrap on 64 Word Window (rsvd)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_ADDR_WRAP_SHIFT                      _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_ADDR_WRAP_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_ADDR_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_ADDR_WRAP_RANGE                      18:16
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_ADDR_WRAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_ADDR_WRAP_NO_WRAP                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_ADDR_WRAP_WRAP_0N_1WORDS                     _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_2WORDS                     _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_4WORDS                     _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_8WORDS                     _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_16WORDS                    _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_32WORDS                    _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_64WORDS                    _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_6_CSR_0  
+#define APBDMACHAN_CHANNEL_6_CSR_0                      _MK_ADDR_CONST(0xc0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_SECURE                       0x0
+#define APBDMACHAN_CHANNEL_6_CSR_0_WORD_COUNT                   0x1
+#define APBDMACHAN_CHANNEL_6_CSR_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_RESET_MASK                   _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_6_CSR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_READ_MASK                    _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_6_CSR_0_WRITE_MASK                   _MK_MASK_CONST(0xfffffffc)
+// Enables DMA channel transfer 
+#define APBDMACHAN_CHANNEL_6_CSR_0_ENB_SHIFT                    _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_6_CSR_0_ENB_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_6_CSR_0_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_6_CSR_0_ENB_RANGE                    31:31
+#define APBDMACHAN_CHANNEL_6_CSR_0_ENB_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_6_CSR_0_ENB_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_ENB_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_6_CSR_0_ENB_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_ENB_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_ENB_DISABLE                  _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_ENB_ENABLE                   _MK_ENUM_CONST(1)
+
+// Interrupts when DMA Block Transfer Completes 
+#define APBDMACHAN_CHANNEL_6_CSR_0_IE_EOC_SHIFT                 _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_6_CSR_0_IE_EOC_FIELD                 (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_6_CSR_0_IE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_6_CSR_0_IE_EOC_RANGE                 30:30
+#define APBDMACHAN_CHANNEL_6_CSR_0_IE_EOC_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_6_CSR_0_IE_EOC_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_IE_EOC_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_6_CSR_0_IE_EOC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_IE_EOC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_IE_EOC_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_IE_EOC_ENABLE                        _MK_ENUM_CONST(1)
+
+// Holds this Processor until DMA Block Transfer Completes
+#define APBDMACHAN_CHANNEL_6_CSR_0_HOLD_SHIFT                   _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_6_CSR_0_HOLD_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_6_CSR_0_HOLD_SHIFT)
+#define APBDMACHAN_CHANNEL_6_CSR_0_HOLD_RANGE                   29:29
+#define APBDMACHAN_CHANNEL_6_CSR_0_HOLD_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_6_CSR_0_HOLD_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_HOLD_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_6_CSR_0_HOLD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_HOLD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_HOLD_DISABLE                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_HOLD_ENABLE                  _MK_ENUM_CONST(1)
+
+// DMA Transfer Direction 1 = AHB read to APB write 0 = APB read to AHB write
+#define APBDMACHAN_CHANNEL_6_CSR_0_DIR_SHIFT                    _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_6_CSR_0_DIR_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_6_CSR_0_DIR_SHIFT)
+#define APBDMACHAN_CHANNEL_6_CSR_0_DIR_RANGE                    28:28
+#define APBDMACHAN_CHANNEL_6_CSR_0_DIR_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_6_CSR_0_DIR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_DIR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_6_CSR_0_DIR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_DIR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_DIR_AHB_WRITE                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_DIR_AHB_READ                 _MK_ENUM_CONST(1)
+
+// Run Once or Run Multiple Mode (Allow Retriggering of this Channel) 1 = Run for One Block Transfer 0 = Run for Multiple Block Transfer
+#define APBDMACHAN_CHANNEL_6_CSR_0_ONCE_SHIFT                   _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_6_CSR_0_ONCE_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_6_CSR_0_ONCE_SHIFT)
+#define APBDMACHAN_CHANNEL_6_CSR_0_ONCE_RANGE                   27:27
+#define APBDMACHAN_CHANNEL_6_CSR_0_ONCE_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_6_CSR_0_ONCE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_ONCE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_6_CSR_0_ONCE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_ONCE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_ONCE_MULTIPLE_BLOCK                  _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_ONCE_SINGLE_BLOCK                    _MK_ENUM_CONST(1)
+
+// Enable on Non-Zero Value
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_SHIFT                       _MK_SHIFT_CONST(22)
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_FIELD                       (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_RANGE                       26:22
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_NA1                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_SMP24                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_SMP25                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_SMP26                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_SMP27                       _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_XRQ_A                       _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_XRQ_B                       _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_TMR1                        _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_TMR2                        _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_APB_0                       _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_APB_1                       _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_APB_2                       _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_APB_3                       _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_APB_4                       _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_APB_5                       _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_APB_6                       _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_APB_7                       _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_APB_8                       _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_APB_9                       _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_APB_10                      _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_APB_11                      _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_APB_12                      _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_APB_13                      _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_APB_14                      _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_APB_15                      _MK_ENUM_CONST(24)
+
+// Flow Control Enable (Synchronize Burst Transfers) 1 = Link to DRQ source 0 = Independent of DRQ request
+#define APBDMACHAN_CHANNEL_6_CSR_0_FLOW_SHIFT                   _MK_SHIFT_CONST(21)
+#define APBDMACHAN_CHANNEL_6_CSR_0_FLOW_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_6_CSR_0_FLOW_SHIFT)
+#define APBDMACHAN_CHANNEL_6_CSR_0_FLOW_RANGE                   21:21
+#define APBDMACHAN_CHANNEL_6_CSR_0_FLOW_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_6_CSR_0_FLOW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_FLOW_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_6_CSR_0_FLOW_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_FLOW_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_FLOW_DISABLE                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_FLOW_ENABLE                  _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_SHIFT                        _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_FIELD                        (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_RANGE                        20:16
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_CNTR_REQ                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_I2S_2                        _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_I2S_1                        _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_SPD_I                        _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_UI_I                 _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_MIPI                 _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_I2S2_2                       _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_I2S2_1                       _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_UART_A                       _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_UART_B                       _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_UART_C                       _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_SPI                  _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_AC97                 _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_ACModem                      _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_SL4B                 _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_SL2B1                        _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_SL2B2                        _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_SL2B3                        _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_SL2B4                        _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_UART_D                       _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_UART_E                       _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_I2C                  _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_I2C2                 _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_I2C3                 _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_DVC_I2C                      _MK_ENUM_CONST(24)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_OWR                  _MK_ENUM_CONST(25)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_NA26                 _MK_ENUM_CONST(26)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_NA27                 _MK_ENUM_CONST(27)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_NA28                 _MK_ENUM_CONST(28)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_NA29                 _MK_ENUM_CONST(29)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_NA30                 _MK_ENUM_CONST(30)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_NA31                 _MK_ENUM_CONST(31)
+
+// Number of 32bit word cycles
+#define APBDMACHAN_CHANNEL_6_CSR_0_WCOUNT_SHIFT                 _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_6_CSR_0_WCOUNT_FIELD                 (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_6_CSR_0_WCOUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_6_CSR_0_WCOUNT_RANGE                 15:2
+#define APBDMACHAN_CHANNEL_6_CSR_0_WCOUNT_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_6_CSR_0_WCOUNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_WCOUNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_6_CSR_0_WCOUNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_WCOUNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_6_STA_0  
+#define APBDMACHAN_CHANNEL_6_STA_0                      _MK_ADDR_CONST(0xc4)
+#define APBDMACHAN_CHANNEL_6_STA_0_SECURE                       0x0
+#define APBDMACHAN_CHANNEL_6_STA_0_WORD_COUNT                   0x1
+#define APBDMACHAN_CHANNEL_6_STA_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_STA_0_RESET_MASK                   _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_6_STA_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_STA_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_STA_0_READ_MASK                    _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_6_STA_0_WRITE_MASK                   _MK_MASK_CONST(0x40000000)
+// indicate whether DMA Channel Status active or not
+#define APBDMACHAN_CHANNEL_6_STA_0_BSY_SHIFT                    _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_6_STA_0_BSY_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_6_STA_0_BSY_SHIFT)
+#define APBDMACHAN_CHANNEL_6_STA_0_BSY_RANGE                    31:31
+#define APBDMACHAN_CHANNEL_6_STA_0_BSY_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_6_STA_0_BSY_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_STA_0_BSY_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_6_STA_0_BSY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_STA_0_BSY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_STA_0_BSY_WAIT                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_6_STA_0_BSY_ACTIVE                   _MK_ENUM_CONST(1)
+
+//  Write '1' to clear the flag
+#define APBDMACHAN_CHANNEL_6_STA_0_ISE_EOC_SHIFT                        _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_6_STA_0_ISE_EOC_FIELD                        (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_6_STA_0_ISE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_6_STA_0_ISE_EOC_RANGE                        30:30
+#define APBDMACHAN_CHANNEL_6_STA_0_ISE_EOC_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_6_STA_0_ISE_EOC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_STA_0_ISE_EOC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_6_STA_0_ISE_EOC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_STA_0_ISE_EOC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_STA_0_ISE_EOC_NO_INTR                      _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_6_STA_0_ISE_EOC_INTR                 _MK_ENUM_CONST(1)
+
+// Holding Status of Processor 
+#define APBDMACHAN_CHANNEL_6_STA_0_HALT_SHIFT                   _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_6_STA_0_HALT_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_6_STA_0_HALT_SHIFT)
+#define APBDMACHAN_CHANNEL_6_STA_0_HALT_RANGE                   29:29
+#define APBDMACHAN_CHANNEL_6_STA_0_HALT_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_6_STA_0_HALT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_STA_0_HALT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_6_STA_0_HALT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_STA_0_HALT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_STA_0_HALT_NO_HALT                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_6_STA_0_HALT_HALT                    _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_6_STA_0_PING_PONG_STA_SHIFT                  _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_6_STA_0_PING_PONG_STA_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_6_STA_0_PING_PONG_STA_SHIFT)
+#define APBDMACHAN_CHANNEL_6_STA_0_PING_PONG_STA_RANGE                  28:28
+#define APBDMACHAN_CHANNEL_6_STA_0_PING_PONG_STA_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_6_STA_0_PING_PONG_STA_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_STA_0_PING_PONG_STA_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_6_STA_0_PING_PONG_STA_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_STA_0_PING_PONG_STA_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_STA_0_PING_PONG_STA_PING_INTR_STA                  _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_6_STA_0_PING_PONG_STA_PONG_INTR_STA                  _MK_ENUM_CONST(1)
+
+// Current 32bit word cycles Flags set /cleared by HW
+#define APBDMACHAN_CHANNEL_6_STA_0_COUNT_SHIFT                  _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_6_STA_0_COUNT_FIELD                  (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_6_STA_0_COUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_6_STA_0_COUNT_RANGE                  15:2
+#define APBDMACHAN_CHANNEL_6_STA_0_COUNT_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_6_STA_0_COUNT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_STA_0_COUNT_DEFAULT_MASK                   _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_6_STA_0_COUNT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_STA_0_COUNT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Reserved address 200 [0xc8] 
+
+// Reserved address 204 [0xcc] 
+
+// Register APBDMACHAN_CHANNEL_6_AHB_PTR_0  
+#define APBDMACHAN_CHANNEL_6_AHB_PTR_0                  _MK_ADDR_CONST(0xd0)
+#define APBDMACHAN_CHANNEL_6_AHB_PTR_0_SECURE                   0x0
+#define APBDMACHAN_CHANNEL_6_AHB_PTR_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_6_AHB_PTR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_AHB_PTR_0_RESET_MASK                       _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_6_AHB_PTR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_AHB_PTR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_AHB_PTR_0_READ_MASK                        _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_6_AHB_PTR_0_WRITE_MASK                       _MK_MASK_CONST(0xfffffffc)
+// APB-DMA Starting Address for AHB Bus: SW writes to  modify
+#define APBDMACHAN_CHANNEL_6_AHB_PTR_0_AHB_BASE_SHIFT                   _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_6_AHB_PTR_0_AHB_BASE_FIELD                   (_MK_MASK_CONST(0x3fffffff) << APBDMACHAN_CHANNEL_6_AHB_PTR_0_AHB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_6_AHB_PTR_0_AHB_BASE_RANGE                   31:2
+#define APBDMACHAN_CHANNEL_6_AHB_PTR_0_AHB_BASE_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_6_AHB_PTR_0_AHB_BASE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_AHB_PTR_0_AHB_BASE_DEFAULT_MASK                    _MK_MASK_CONST(0x3fffffff)
+#define APBDMACHAN_CHANNEL_6_AHB_PTR_0_AHB_BASE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_AHB_PTR_0_AHB_BASE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_6_AHB_SEQ_0  
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0                  _MK_ADDR_CONST(0xd4)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_SECURE                   0x0
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_RESET_VAL                        _MK_MASK_CONST(0x20000000)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_RESET_MASK                       _MK_MASK_CONST(0xff0f0000)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_READ_MASK                        _MK_MASK_CONST(0xff0f0000)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_WRITE_MASK                       _MK_MASK_CONST(0xff0f0000)
+//  0 = send interrupt to COP
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_INTR_ENB_SHIFT                   _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_INTR_ENB_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_6_AHB_SEQ_0_INTR_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_INTR_ENB_RANGE                   31:31
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_INTR_ENB_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_INTR_ENB_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_INTR_ENB_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_INTR_ENB_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_INTR_ENB_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_INTR_ENB_CPU                     _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_INTR_ENB_COP                     _MK_ENUM_CONST(0)
+
+// AHB Bus Width 0 = 8 bit Bus (RSVD) 1 = 16 bit Bus (RSVD) 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD)4 = 128 bit Bus (RSVD)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT                      _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_BUS_WIDTH_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_BUS_WIDTH_RANGE                      30:28
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_BUS_WIDTH_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT                    _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_8                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_16                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_32                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_64                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_128                      _MK_ENUM_CONST(4)
+
+// when enabled the data going  to AHB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT                      _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_DATA_SWAP_FIELD                      (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_DATA_SWAP_RANGE                      27:27
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_DATA_SWAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_DATA_SWAP_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_DATA_SWAP_ENABLE                     _MK_ENUM_CONST(1)
+
+// AHB Burst Size DMA Burst Length (encoded) 4 = 1 Word (1x32bits) 5 = 4 Words (4x32bits)else = 8 Words (8x32bits) default
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_BURST_SHIFT                  _MK_SHIFT_CONST(24)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_BURST_FIELD                  (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_BURST_SHIFT)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_BURST_RANGE                  26:24
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_BURST_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_BURST_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_BURST_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_BURST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_BURST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_BURST_DMA_BURST_1WORDS                       _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_BURST_DMA_BURST_4WORDS                       _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_BURST_DMA_BURST_8WORDS                       _MK_ENUM_CONST(6)
+
+// 2X Double Buffering Mode (For Run-Multiple Mode with No Wrap Operations) 1 = Reload Base Address for 2X blocks (reload every other time) 0 = Reload Base Address for 1X blocks  (def) (reload each time)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_DBL_BUF_SHIFT                    _MK_SHIFT_CONST(19)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_DBL_BUF_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_6_AHB_SEQ_0_DBL_BUF_SHIFT)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_DBL_BUF_RANGE                    19:19
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_DBL_BUF_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_DBL_BUF_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_DBL_BUF_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_DBL_BUF_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_DBL_BUF_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_DBL_BUF_RELOAD_FOR_1X_BLOCKS                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_DBL_BUF_RELOAD_FOR_2X_BLOCKS                     _MK_ENUM_CONST(1)
+
+// AHB Address Wrap: AHB Address wrap-around window 0=No Wrap (default) 5=Wrap on 512 word window 1=Wrap on 32 word window 6=Wrap on 1024 word window 2=Wrap on 64 word window 7=Wrap on 2048 word window 3=Wrap on 128 word window 4=Wrap on 256 word window
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_WRAP_SHIFT                       _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_WRAP_FIELD                       (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_6_AHB_SEQ_0_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_WRAP_RANGE                       18:16
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_WRAP_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_WRAP_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_WRAP_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_WRAP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_WRAP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_WRAP_NO_WRAP                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_WRAP_WRAP_0N_32WORDS                     _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_WRAP_WRAP_ON_64WORDS                     _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_WRAP_WRAP_ON_128WORDS                    _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_WRAP_WRAP_ON_256WORDS                    _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_WRAP_WRAP_ON_512WORDS                    _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_WRAP_WRAP_ON_1024WORDS                   _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_WRAP_WRAP_ON_2048WORDS                   _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_6_APB_PTR_0  
+#define APBDMACHAN_CHANNEL_6_APB_PTR_0                  _MK_ADDR_CONST(0xd8)
+#define APBDMACHAN_CHANNEL_6_APB_PTR_0_SECURE                   0x0
+#define APBDMACHAN_CHANNEL_6_APB_PTR_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_6_APB_PTR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_APB_PTR_0_RESET_MASK                       _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_6_APB_PTR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_APB_PTR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_APB_PTR_0_READ_MASK                        _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_6_APB_PTR_0_WRITE_MASK                       _MK_MASK_CONST(0xfffc)
+// APB-DMA Starting address for APB Bus: APB Base address:Upper 16 bits are fixed at 0x7000:XXXX
+#define APBDMACHAN_CHANNEL_6_APB_PTR_0_APB_BASE_SHIFT                   _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_6_APB_PTR_0_APB_BASE_FIELD                   (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_6_APB_PTR_0_APB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_6_APB_PTR_0_APB_BASE_RANGE                   15:2
+#define APBDMACHAN_CHANNEL_6_APB_PTR_0_APB_BASE_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_6_APB_PTR_0_APB_BASE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_APB_PTR_0_APB_BASE_DEFAULT_MASK                    _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_6_APB_PTR_0_APB_BASE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_APB_PTR_0_APB_BASE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_6_APB_SEQ_0  
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0                  _MK_ADDR_CONST(0xdc)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_SECURE                   0x0
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_RESET_VAL                        _MK_MASK_CONST(0x20010000)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_RESET_MASK                       _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_READ_MASK                        _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_WRITE_MASK                       _MK_MASK_CONST(0x78070000)
+// 0 = 8 bit Bus 1 = 16 bit Bus 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD) 4 = 128 bit BUS (RSVD)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_BUS_WIDTH_SHIFT                      _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_BUS_WIDTH_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_BUS_WIDTH_RANGE                      30:28
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_BUS_WIDTH_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT                    _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_8                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_16                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_32                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_64                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_128                      _MK_ENUM_CONST(4)
+
+// when enabled the data going  to APB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_DATA_SWAP_SHIFT                      _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_DATA_SWAP_FIELD                      (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_DATA_SWAP_RANGE                      27:27
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_DATA_SWAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_DATA_SWAP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_DATA_SWAP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_DATA_SWAP_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_DATA_SWAP_ENABLE                     _MK_ENUM_CONST(1)
+
+//APB Address Wrap-around Window 0 = No Wrap 1 = Wrap on 1 Word Window (def) 2 = Wrap on 2 Word Window 3 = Wrap on 4 Word Window 4 = Wrap on 8 Word Window 5 = Wrap on 16 Word Window 6 = Wrap on 32 Word Window 7 = Wrap on 64 Word Window (rsvd)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_ADDR_WRAP_SHIFT                      _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_ADDR_WRAP_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_ADDR_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_ADDR_WRAP_RANGE                      18:16
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_ADDR_WRAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_ADDR_WRAP_NO_WRAP                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_ADDR_WRAP_WRAP_0N_1WORDS                     _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_2WORDS                     _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_4WORDS                     _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_8WORDS                     _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_16WORDS                    _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_32WORDS                    _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_64WORDS                    _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_7_CSR_0  
+#define APBDMACHAN_CHANNEL_7_CSR_0                      _MK_ADDR_CONST(0xe0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_SECURE                       0x0
+#define APBDMACHAN_CHANNEL_7_CSR_0_WORD_COUNT                   0x1
+#define APBDMACHAN_CHANNEL_7_CSR_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_RESET_MASK                   _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_7_CSR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_READ_MASK                    _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_7_CSR_0_WRITE_MASK                   _MK_MASK_CONST(0xfffffffc)
+// Enables DMA channel transfer 
+#define APBDMACHAN_CHANNEL_7_CSR_0_ENB_SHIFT                    _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_7_CSR_0_ENB_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_7_CSR_0_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_7_CSR_0_ENB_RANGE                    31:31
+#define APBDMACHAN_CHANNEL_7_CSR_0_ENB_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_7_CSR_0_ENB_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_ENB_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_7_CSR_0_ENB_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_ENB_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_ENB_DISABLE                  _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_ENB_ENABLE                   _MK_ENUM_CONST(1)
+
+// Interrupts when DMA Block Transfer Completes 
+#define APBDMACHAN_CHANNEL_7_CSR_0_IE_EOC_SHIFT                 _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_7_CSR_0_IE_EOC_FIELD                 (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_7_CSR_0_IE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_7_CSR_0_IE_EOC_RANGE                 30:30
+#define APBDMACHAN_CHANNEL_7_CSR_0_IE_EOC_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_7_CSR_0_IE_EOC_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_IE_EOC_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_7_CSR_0_IE_EOC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_IE_EOC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_IE_EOC_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_IE_EOC_ENABLE                        _MK_ENUM_CONST(1)
+
+// Holds this Processor until DMA Block Transfer Completes
+#define APBDMACHAN_CHANNEL_7_CSR_0_HOLD_SHIFT                   _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_7_CSR_0_HOLD_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_7_CSR_0_HOLD_SHIFT)
+#define APBDMACHAN_CHANNEL_7_CSR_0_HOLD_RANGE                   29:29
+#define APBDMACHAN_CHANNEL_7_CSR_0_HOLD_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_7_CSR_0_HOLD_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_HOLD_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_7_CSR_0_HOLD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_HOLD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_HOLD_DISABLE                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_HOLD_ENABLE                  _MK_ENUM_CONST(1)
+
+// DMA Transfer Direction 1 = AHB read to APB write 0 = APB read to AHB write
+#define APBDMACHAN_CHANNEL_7_CSR_0_DIR_SHIFT                    _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_7_CSR_0_DIR_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_7_CSR_0_DIR_SHIFT)
+#define APBDMACHAN_CHANNEL_7_CSR_0_DIR_RANGE                    28:28
+#define APBDMACHAN_CHANNEL_7_CSR_0_DIR_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_7_CSR_0_DIR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_DIR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_7_CSR_0_DIR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_DIR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_DIR_AHB_WRITE                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_DIR_AHB_READ                 _MK_ENUM_CONST(1)
+
+// Run Once or Run Multiple Mode (Allow Retriggering of this Channel) 1 = Run for One Block Transfer 0 = Run for Multiple Block Transfer
+#define APBDMACHAN_CHANNEL_7_CSR_0_ONCE_SHIFT                   _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_7_CSR_0_ONCE_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_7_CSR_0_ONCE_SHIFT)
+#define APBDMACHAN_CHANNEL_7_CSR_0_ONCE_RANGE                   27:27
+#define APBDMACHAN_CHANNEL_7_CSR_0_ONCE_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_7_CSR_0_ONCE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_ONCE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_7_CSR_0_ONCE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_ONCE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_ONCE_MULTIPLE_BLOCK                  _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_ONCE_SINGLE_BLOCK                    _MK_ENUM_CONST(1)
+
+// Enable on Non-Zero Value
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_SHIFT                       _MK_SHIFT_CONST(22)
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_FIELD                       (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_RANGE                       26:22
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_NA1                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_SMP24                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_SMP25                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_SMP26                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_SMP27                       _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_XRQ_A                       _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_XRQ_B                       _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_TMR1                        _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_TMR2                        _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_APB_0                       _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_APB_1                       _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_APB_2                       _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_APB_3                       _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_APB_4                       _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_APB_5                       _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_APB_6                       _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_APB_7                       _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_APB_8                       _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_APB_9                       _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_APB_10                      _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_APB_11                      _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_APB_12                      _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_APB_13                      _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_APB_14                      _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_APB_15                      _MK_ENUM_CONST(24)
+
+// Flow Control Enable (Synchronize Burst Transfers) 1 = Link to DRQ source 0 = Independent of DRQ request
+#define APBDMACHAN_CHANNEL_7_CSR_0_FLOW_SHIFT                   _MK_SHIFT_CONST(21)
+#define APBDMACHAN_CHANNEL_7_CSR_0_FLOW_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_7_CSR_0_FLOW_SHIFT)
+#define APBDMACHAN_CHANNEL_7_CSR_0_FLOW_RANGE                   21:21
+#define APBDMACHAN_CHANNEL_7_CSR_0_FLOW_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_7_CSR_0_FLOW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_FLOW_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_7_CSR_0_FLOW_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_FLOW_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_FLOW_DISABLE                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_FLOW_ENABLE                  _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_SHIFT                        _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_FIELD                        (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_RANGE                        20:16
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_CNTR_REQ                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_I2S_2                        _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_I2S_1                        _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_SPD_I                        _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_UI_I                 _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_MIPI                 _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_I2S2_2                       _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_I2S2_1                       _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_UART_A                       _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_UART_B                       _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_UART_C                       _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_SPI                  _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_AC97                 _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_ACModem                      _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_SL4B                 _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_SL2B1                        _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_SL2B2                        _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_SL2B3                        _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_SL2B4                        _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_UART_D                       _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_UART_E                       _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_I2C                  _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_I2C2                 _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_I2C3                 _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_DVC_I2C                      _MK_ENUM_CONST(24)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_OWR                  _MK_ENUM_CONST(25)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_NA26                 _MK_ENUM_CONST(26)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_NA27                 _MK_ENUM_CONST(27)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_NA28                 _MK_ENUM_CONST(28)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_NA29                 _MK_ENUM_CONST(29)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_NA30                 _MK_ENUM_CONST(30)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_NA31                 _MK_ENUM_CONST(31)
+
+// Number of 32bit word cycles
+#define APBDMACHAN_CHANNEL_7_CSR_0_WCOUNT_SHIFT                 _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_7_CSR_0_WCOUNT_FIELD                 (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_7_CSR_0_WCOUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_7_CSR_0_WCOUNT_RANGE                 15:2
+#define APBDMACHAN_CHANNEL_7_CSR_0_WCOUNT_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_7_CSR_0_WCOUNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_WCOUNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_7_CSR_0_WCOUNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_WCOUNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_7_STA_0  
+#define APBDMACHAN_CHANNEL_7_STA_0                      _MK_ADDR_CONST(0xe4)
+#define APBDMACHAN_CHANNEL_7_STA_0_SECURE                       0x0
+#define APBDMACHAN_CHANNEL_7_STA_0_WORD_COUNT                   0x1
+#define APBDMACHAN_CHANNEL_7_STA_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_STA_0_RESET_MASK                   _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_7_STA_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_STA_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_STA_0_READ_MASK                    _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_7_STA_0_WRITE_MASK                   _MK_MASK_CONST(0x40000000)
+// indicate whether DMA Channel Status Active or not 
+#define APBDMACHAN_CHANNEL_7_STA_0_BSY_SHIFT                    _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_7_STA_0_BSY_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_7_STA_0_BSY_SHIFT)
+#define APBDMACHAN_CHANNEL_7_STA_0_BSY_RANGE                    31:31
+#define APBDMACHAN_CHANNEL_7_STA_0_BSY_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_7_STA_0_BSY_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_STA_0_BSY_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_7_STA_0_BSY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_STA_0_BSY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_STA_0_BSY_WAIT                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_7_STA_0_BSY_ACTIVE                   _MK_ENUM_CONST(1)
+
+//  Write '1' to clear the flag
+#define APBDMACHAN_CHANNEL_7_STA_0_ISE_EOC_SHIFT                        _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_7_STA_0_ISE_EOC_FIELD                        (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_7_STA_0_ISE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_7_STA_0_ISE_EOC_RANGE                        30:30
+#define APBDMACHAN_CHANNEL_7_STA_0_ISE_EOC_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_7_STA_0_ISE_EOC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_STA_0_ISE_EOC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_7_STA_0_ISE_EOC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_STA_0_ISE_EOC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_STA_0_ISE_EOC_NO_INTR                      _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_7_STA_0_ISE_EOC_INTR                 _MK_ENUM_CONST(1)
+
+// Holding Status of Processor 
+#define APBDMACHAN_CHANNEL_7_STA_0_HALT_SHIFT                   _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_7_STA_0_HALT_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_7_STA_0_HALT_SHIFT)
+#define APBDMACHAN_CHANNEL_7_STA_0_HALT_RANGE                   29:29
+#define APBDMACHAN_CHANNEL_7_STA_0_HALT_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_7_STA_0_HALT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_STA_0_HALT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_7_STA_0_HALT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_STA_0_HALT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_STA_0_HALT_NO_HALT                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_7_STA_0_HALT_HALT                    _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_7_STA_0_PING_PONG_STA_SHIFT                  _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_7_STA_0_PING_PONG_STA_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_7_STA_0_PING_PONG_STA_SHIFT)
+#define APBDMACHAN_CHANNEL_7_STA_0_PING_PONG_STA_RANGE                  28:28
+#define APBDMACHAN_CHANNEL_7_STA_0_PING_PONG_STA_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_7_STA_0_PING_PONG_STA_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_STA_0_PING_PONG_STA_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_7_STA_0_PING_PONG_STA_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_STA_0_PING_PONG_STA_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_STA_0_PING_PONG_STA_PING_INTR_STA                  _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_7_STA_0_PING_PONG_STA_PONG_INTR_STA                  _MK_ENUM_CONST(1)
+
+// Current 32bit word cycles Flags set /cleared by HW
+#define APBDMACHAN_CHANNEL_7_STA_0_COUNT_SHIFT                  _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_7_STA_0_COUNT_FIELD                  (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_7_STA_0_COUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_7_STA_0_COUNT_RANGE                  15:2
+#define APBDMACHAN_CHANNEL_7_STA_0_COUNT_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_7_STA_0_COUNT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_STA_0_COUNT_DEFAULT_MASK                   _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_7_STA_0_COUNT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_STA_0_COUNT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Reserved address 232 [0xe8] 
+
+// Reserved address 236 [0xec] 
+
+// Register APBDMACHAN_CHANNEL_7_AHB_PTR_0  
+#define APBDMACHAN_CHANNEL_7_AHB_PTR_0                  _MK_ADDR_CONST(0xf0)
+#define APBDMACHAN_CHANNEL_7_AHB_PTR_0_SECURE                   0x0
+#define APBDMACHAN_CHANNEL_7_AHB_PTR_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_7_AHB_PTR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_AHB_PTR_0_RESET_MASK                       _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_7_AHB_PTR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_AHB_PTR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_AHB_PTR_0_READ_MASK                        _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_7_AHB_PTR_0_WRITE_MASK                       _MK_MASK_CONST(0xfffffffc)
+// APB-DMA Starting Address for AHB Bus: SW writes to  modify
+#define APBDMACHAN_CHANNEL_7_AHB_PTR_0_AHB_BASE_SHIFT                   _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_7_AHB_PTR_0_AHB_BASE_FIELD                   (_MK_MASK_CONST(0x3fffffff) << APBDMACHAN_CHANNEL_7_AHB_PTR_0_AHB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_7_AHB_PTR_0_AHB_BASE_RANGE                   31:2
+#define APBDMACHAN_CHANNEL_7_AHB_PTR_0_AHB_BASE_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_7_AHB_PTR_0_AHB_BASE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_AHB_PTR_0_AHB_BASE_DEFAULT_MASK                    _MK_MASK_CONST(0x3fffffff)
+#define APBDMACHAN_CHANNEL_7_AHB_PTR_0_AHB_BASE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_AHB_PTR_0_AHB_BASE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_7_AHB_SEQ_0  
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0                  _MK_ADDR_CONST(0xf4)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_SECURE                   0x0
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_RESET_VAL                        _MK_MASK_CONST(0x20000000)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_RESET_MASK                       _MK_MASK_CONST(0xff0f0000)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_READ_MASK                        _MK_MASK_CONST(0xff0f0000)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_WRITE_MASK                       _MK_MASK_CONST(0xff0f0000)
+//  0 = send interrupt to COP
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_INTR_ENB_SHIFT                   _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_INTR_ENB_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_7_AHB_SEQ_0_INTR_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_INTR_ENB_RANGE                   31:31
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_INTR_ENB_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_INTR_ENB_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_INTR_ENB_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_INTR_ENB_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_INTR_ENB_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_INTR_ENB_CPU                     _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_INTR_ENB_COP                     _MK_ENUM_CONST(0)
+
+// AHB Bus Width 0 = 8 bit Bus (RSVD) 1 = 16 bit Bus (RSVD) 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD)4 = 128 bit Bus (RSVD)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT                      _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_BUS_WIDTH_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_BUS_WIDTH_RANGE                      30:28
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_BUS_WIDTH_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT                    _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_8                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_16                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_32                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_64                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_128                      _MK_ENUM_CONST(4)
+
+// when enabled the data going  to AHB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT                      _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_DATA_SWAP_FIELD                      (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_DATA_SWAP_RANGE                      27:27
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_DATA_SWAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_DATA_SWAP_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_DATA_SWAP_ENABLE                     _MK_ENUM_CONST(1)
+
+// AHB Burst Size DMA Burst Length (encoded) 4 = 1 Word (1x32bits) 5 = 4 Words (4x32bits)else = 8 Words (8x32bits) default
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_BURST_SHIFT                  _MK_SHIFT_CONST(24)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_BURST_FIELD                  (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_BURST_SHIFT)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_BURST_RANGE                  26:24
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_BURST_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_BURST_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_BURST_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_BURST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_BURST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_BURST_DMA_BURST_1WORDS                       _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_BURST_DMA_BURST_4WORDS                       _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_BURST_DMA_BURST_8WORDS                       _MK_ENUM_CONST(6)
+
+// 2X Double Buffering Mode (For Run-Multiple Mode with No Wrap Operations) 1 = Reload Base Address for 2X blocks (reload every other time) 0 = Reload Base Address for 1X blocks  (def) (reload each time)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_DBL_BUF_SHIFT                    _MK_SHIFT_CONST(19)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_DBL_BUF_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_7_AHB_SEQ_0_DBL_BUF_SHIFT)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_DBL_BUF_RANGE                    19:19
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_DBL_BUF_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_DBL_BUF_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_DBL_BUF_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_DBL_BUF_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_DBL_BUF_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_DBL_BUF_RELOAD_FOR_1X_BLOCKS                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_DBL_BUF_RELOAD_FOR_2X_BLOCKS                     _MK_ENUM_CONST(1)
+
+// AHB Address Wrap: AHB Address wrap-around window 0=No Wrap (default) 5=Wrap on 512 word window 1=Wrap on 32 word window 6=Wrap on 1024 word window 2=Wrap on 64 word window 7=Wrap on 2048 word window 3=Wrap on 128 word window 4=Wrap on 256 word window
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_WRAP_SHIFT                       _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_WRAP_FIELD                       (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_7_AHB_SEQ_0_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_WRAP_RANGE                       18:16
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_WRAP_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_WRAP_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_WRAP_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_WRAP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_WRAP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_WRAP_NO_WRAP                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_WRAP_WRAP_0N_32WORDS                     _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_WRAP_WRAP_ON_64WORDS                     _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_WRAP_WRAP_ON_128WORDS                    _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_WRAP_WRAP_ON_256WORDS                    _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_WRAP_WRAP_ON_512WORDS                    _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_WRAP_WRAP_ON_1024WORDS                   _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_WRAP_WRAP_ON_2048WORDS                   _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_7_APB_PTR_0  
+#define APBDMACHAN_CHANNEL_7_APB_PTR_0                  _MK_ADDR_CONST(0xf8)
+#define APBDMACHAN_CHANNEL_7_APB_PTR_0_SECURE                   0x0
+#define APBDMACHAN_CHANNEL_7_APB_PTR_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_7_APB_PTR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_APB_PTR_0_RESET_MASK                       _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_7_APB_PTR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_APB_PTR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_APB_PTR_0_READ_MASK                        _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_7_APB_PTR_0_WRITE_MASK                       _MK_MASK_CONST(0xfffc)
+// APB-DMA Starting address for APB Bus: APB Base address:Upper 16 bits are fixed at 0x7000:XXXX
+#define APBDMACHAN_CHANNEL_7_APB_PTR_0_APB_BASE_SHIFT                   _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_7_APB_PTR_0_APB_BASE_FIELD                   (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_7_APB_PTR_0_APB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_7_APB_PTR_0_APB_BASE_RANGE                   15:2
+#define APBDMACHAN_CHANNEL_7_APB_PTR_0_APB_BASE_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_7_APB_PTR_0_APB_BASE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_APB_PTR_0_APB_BASE_DEFAULT_MASK                    _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_7_APB_PTR_0_APB_BASE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_APB_PTR_0_APB_BASE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_7_APB_SEQ_0  
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0                  _MK_ADDR_CONST(0xfc)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_SECURE                   0x0
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_RESET_VAL                        _MK_MASK_CONST(0x20010000)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_RESET_MASK                       _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_READ_MASK                        _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_WRITE_MASK                       _MK_MASK_CONST(0x78070000)
+// 0 = 8 bit Bus 1 = 16 bit Bus 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD) 4 = 128 bit BUS (RSVD)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_BUS_WIDTH_SHIFT                      _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_BUS_WIDTH_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_BUS_WIDTH_RANGE                      30:28
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_BUS_WIDTH_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT                    _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_8                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_16                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_32                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_64                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_128                      _MK_ENUM_CONST(4)
+
+// when enabled the data going  to APB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }.
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_DATA_SWAP_SHIFT                      _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_DATA_SWAP_FIELD                      (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_DATA_SWAP_RANGE                      27:27
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_DATA_SWAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_DATA_SWAP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_DATA_SWAP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_DATA_SWAP_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_DATA_SWAP_ENABLE                     _MK_ENUM_CONST(1)
+
+//APB Address Wrap-around Window 0 = No Wrap 1 = Wrap on 1 Word Window (def) 2 = Wrap on 2 Word Window 3 = Wrap on 4 Word Window 4 = Wrap on 8 Word Window 5 = Wrap on 16 Word Window 6 = Wrap on 32 Word Window 7 = Wrap on 64 Word Window (rsvd)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_ADDR_WRAP_SHIFT                      _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_ADDR_WRAP_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_ADDR_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_ADDR_WRAP_RANGE                      18:16
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_ADDR_WRAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_ADDR_WRAP_NO_WRAP                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_ADDR_WRAP_WRAP_0N_1WORDS                     _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_2WORDS                     _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_4WORDS                     _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_8WORDS                     _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_16WORDS                    _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_32WORDS                    _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_64WORDS                    _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_8_CSR_0  
+#define APBDMACHAN_CHANNEL_8_CSR_0                      _MK_ADDR_CONST(0x100)
+#define APBDMACHAN_CHANNEL_8_CSR_0_SECURE                       0x0
+#define APBDMACHAN_CHANNEL_8_CSR_0_WORD_COUNT                   0x1
+#define APBDMACHAN_CHANNEL_8_CSR_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_RESET_MASK                   _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_8_CSR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_READ_MASK                    _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_8_CSR_0_WRITE_MASK                   _MK_MASK_CONST(0xfffffffc)
+// Enables DMA channel transfer 
+#define APBDMACHAN_CHANNEL_8_CSR_0_ENB_SHIFT                    _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_8_CSR_0_ENB_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_8_CSR_0_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_8_CSR_0_ENB_RANGE                    31:31
+#define APBDMACHAN_CHANNEL_8_CSR_0_ENB_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_8_CSR_0_ENB_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_ENB_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_8_CSR_0_ENB_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_ENB_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_ENB_DISABLE                  _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_ENB_ENABLE                   _MK_ENUM_CONST(1)
+
+// Interrupts when DMA Block Transfer Completes 
+#define APBDMACHAN_CHANNEL_8_CSR_0_IE_EOC_SHIFT                 _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_8_CSR_0_IE_EOC_FIELD                 (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_8_CSR_0_IE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_8_CSR_0_IE_EOC_RANGE                 30:30
+#define APBDMACHAN_CHANNEL_8_CSR_0_IE_EOC_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_8_CSR_0_IE_EOC_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_IE_EOC_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_8_CSR_0_IE_EOC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_IE_EOC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_IE_EOC_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_IE_EOC_ENABLE                        _MK_ENUM_CONST(1)
+
+// Holds this Processor until DMA Block Transfer Completes
+#define APBDMACHAN_CHANNEL_8_CSR_0_HOLD_SHIFT                   _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_8_CSR_0_HOLD_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_8_CSR_0_HOLD_SHIFT)
+#define APBDMACHAN_CHANNEL_8_CSR_0_HOLD_RANGE                   29:29
+#define APBDMACHAN_CHANNEL_8_CSR_0_HOLD_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_8_CSR_0_HOLD_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_HOLD_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_8_CSR_0_HOLD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_HOLD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_HOLD_DISABLE                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_HOLD_ENABLE                  _MK_ENUM_CONST(1)
+
+// DMA Transfer Direction 1 = AHB read to APB write 0 = APB read to AHB write
+#define APBDMACHAN_CHANNEL_8_CSR_0_DIR_SHIFT                    _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_8_CSR_0_DIR_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_8_CSR_0_DIR_SHIFT)
+#define APBDMACHAN_CHANNEL_8_CSR_0_DIR_RANGE                    28:28
+#define APBDMACHAN_CHANNEL_8_CSR_0_DIR_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_8_CSR_0_DIR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_DIR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_8_CSR_0_DIR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_DIR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_DIR_AHB_WRITE                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_DIR_AHB_READ                 _MK_ENUM_CONST(1)
+
+// Run Once or Run Multiple Mode (Allow Retriggering of this Channel) 1 = Run for One Block Transfer 0 = Run for Multiple Block Transfer
+#define APBDMACHAN_CHANNEL_8_CSR_0_ONCE_SHIFT                   _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_8_CSR_0_ONCE_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_8_CSR_0_ONCE_SHIFT)
+#define APBDMACHAN_CHANNEL_8_CSR_0_ONCE_RANGE                   27:27
+#define APBDMACHAN_CHANNEL_8_CSR_0_ONCE_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_8_CSR_0_ONCE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_ONCE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_8_CSR_0_ONCE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_ONCE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_ONCE_MULTIPLE_BLOCK                  _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_ONCE_SINGLE_BLOCK                    _MK_ENUM_CONST(1)
+
+// Enable on Non-Zero Value
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_SHIFT                       _MK_SHIFT_CONST(22)
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_FIELD                       (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_RANGE                       26:22
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_NA1                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_SMP24                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_SMP25                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_SMP26                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_SMP27                       _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_XRQ_A                       _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_XRQ_B                       _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_TMR1                        _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_TMR2                        _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_APB_0                       _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_APB_1                       _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_APB_2                       _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_APB_3                       _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_APB_4                       _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_APB_5                       _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_APB_6                       _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_APB_7                       _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_APB_8                       _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_APB_9                       _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_APB_10                      _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_APB_11                      _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_APB_12                      _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_APB_13                      _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_APB_14                      _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_APB_15                      _MK_ENUM_CONST(24)
+
+// Flow Control Enable (Synchronize Burst Transfers) 1 = Link to DRQ source 0 = Independent of DRQ request
+#define APBDMACHAN_CHANNEL_8_CSR_0_FLOW_SHIFT                   _MK_SHIFT_CONST(21)
+#define APBDMACHAN_CHANNEL_8_CSR_0_FLOW_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_8_CSR_0_FLOW_SHIFT)
+#define APBDMACHAN_CHANNEL_8_CSR_0_FLOW_RANGE                   21:21
+#define APBDMACHAN_CHANNEL_8_CSR_0_FLOW_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_8_CSR_0_FLOW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_FLOW_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_8_CSR_0_FLOW_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_FLOW_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_FLOW_DISABLE                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_FLOW_ENABLE                  _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_SHIFT                        _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_FIELD                        (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_RANGE                        20:16
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_CNTR_REQ                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_I2S_2                        _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_I2S_1                        _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_SPD_I                        _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_UI_I                 _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_MIPI                 _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_I2S2_2                       _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_I2S2_1                       _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_UART_A                       _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_UART_B                       _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_UART_C                       _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_SPI                  _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_AC97                 _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_ACModem                      _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_SL4B                 _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_SL2B1                        _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_SL2B2                        _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_SL2B3                        _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_SL2B4                        _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_UART_D                       _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_UART_E                       _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_I2C                  _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_I2C2                 _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_I2C3                 _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_DVC_I2C                      _MK_ENUM_CONST(24)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_OWR                  _MK_ENUM_CONST(25)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_NA26                 _MK_ENUM_CONST(26)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_NA27                 _MK_ENUM_CONST(27)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_NA28                 _MK_ENUM_CONST(28)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_NA29                 _MK_ENUM_CONST(29)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_NA30                 _MK_ENUM_CONST(30)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_NA31                 _MK_ENUM_CONST(31)
+
+// Number of 32bit word cycles
+#define APBDMACHAN_CHANNEL_8_CSR_0_WCOUNT_SHIFT                 _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_8_CSR_0_WCOUNT_FIELD                 (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_8_CSR_0_WCOUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_8_CSR_0_WCOUNT_RANGE                 15:2
+#define APBDMACHAN_CHANNEL_8_CSR_0_WCOUNT_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_8_CSR_0_WCOUNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_WCOUNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_8_CSR_0_WCOUNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_WCOUNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_8_STA_0  
+#define APBDMACHAN_CHANNEL_8_STA_0                      _MK_ADDR_CONST(0x104)
+#define APBDMACHAN_CHANNEL_8_STA_0_SECURE                       0x0
+#define APBDMACHAN_CHANNEL_8_STA_0_WORD_COUNT                   0x1
+#define APBDMACHAN_CHANNEL_8_STA_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_STA_0_RESET_MASK                   _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_8_STA_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_STA_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_STA_0_READ_MASK                    _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_8_STA_0_WRITE_MASK                   _MK_MASK_CONST(0x40000000)
+// indicate DMA Channel Status activate or not
+#define APBDMACHAN_CHANNEL_8_STA_0_BSY_SHIFT                    _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_8_STA_0_BSY_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_8_STA_0_BSY_SHIFT)
+#define APBDMACHAN_CHANNEL_8_STA_0_BSY_RANGE                    31:31
+#define APBDMACHAN_CHANNEL_8_STA_0_BSY_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_8_STA_0_BSY_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_STA_0_BSY_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_8_STA_0_BSY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_STA_0_BSY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_STA_0_BSY_WAIT                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_8_STA_0_BSY_ACTIVE                   _MK_ENUM_CONST(1)
+
+//  Write '1' to clear the flag
+#define APBDMACHAN_CHANNEL_8_STA_0_ISE_EOC_SHIFT                        _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_8_STA_0_ISE_EOC_FIELD                        (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_8_STA_0_ISE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_8_STA_0_ISE_EOC_RANGE                        30:30
+#define APBDMACHAN_CHANNEL_8_STA_0_ISE_EOC_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_8_STA_0_ISE_EOC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_STA_0_ISE_EOC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_8_STA_0_ISE_EOC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_STA_0_ISE_EOC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_STA_0_ISE_EOC_NO_INTR                      _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_8_STA_0_ISE_EOC_INTR                 _MK_ENUM_CONST(1)
+
+// Holding Status of Processor 
+#define APBDMACHAN_CHANNEL_8_STA_0_HALT_SHIFT                   _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_8_STA_0_HALT_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_8_STA_0_HALT_SHIFT)
+#define APBDMACHAN_CHANNEL_8_STA_0_HALT_RANGE                   29:29
+#define APBDMACHAN_CHANNEL_8_STA_0_HALT_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_8_STA_0_HALT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_STA_0_HALT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_8_STA_0_HALT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_STA_0_HALT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_STA_0_HALT_NO_HALT                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_8_STA_0_HALT_HALT                    _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_8_STA_0_PING_PONG_STA_SHIFT                  _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_8_STA_0_PING_PONG_STA_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_8_STA_0_PING_PONG_STA_SHIFT)
+#define APBDMACHAN_CHANNEL_8_STA_0_PING_PONG_STA_RANGE                  28:28
+#define APBDMACHAN_CHANNEL_8_STA_0_PING_PONG_STA_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_8_STA_0_PING_PONG_STA_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_STA_0_PING_PONG_STA_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_8_STA_0_PING_PONG_STA_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_STA_0_PING_PONG_STA_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_STA_0_PING_PONG_STA_PING_INTR_STA                  _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_8_STA_0_PING_PONG_STA_PONG_INTR_STA                  _MK_ENUM_CONST(1)
+
+// Current 32bit word cycles Flags set /cleared by HW
+#define APBDMACHAN_CHANNEL_8_STA_0_COUNT_SHIFT                  _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_8_STA_0_COUNT_FIELD                  (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_8_STA_0_COUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_8_STA_0_COUNT_RANGE                  15:2
+#define APBDMACHAN_CHANNEL_8_STA_0_COUNT_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_8_STA_0_COUNT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_STA_0_COUNT_DEFAULT_MASK                   _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_8_STA_0_COUNT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_STA_0_COUNT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Reserved address 264 [0x108] 
+
+// Reserved address 268 [0x10c] 
+
+// Register APBDMACHAN_CHANNEL_8_AHB_PTR_0  
+#define APBDMACHAN_CHANNEL_8_AHB_PTR_0                  _MK_ADDR_CONST(0x110)
+#define APBDMACHAN_CHANNEL_8_AHB_PTR_0_SECURE                   0x0
+#define APBDMACHAN_CHANNEL_8_AHB_PTR_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_8_AHB_PTR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_AHB_PTR_0_RESET_MASK                       _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_8_AHB_PTR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_AHB_PTR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_AHB_PTR_0_READ_MASK                        _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_8_AHB_PTR_0_WRITE_MASK                       _MK_MASK_CONST(0xfffffffc)
+// APB-DMA Starting Address for AHB Bus: SW writes to  modify
+#define APBDMACHAN_CHANNEL_8_AHB_PTR_0_AHB_BASE_SHIFT                   _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_8_AHB_PTR_0_AHB_BASE_FIELD                   (_MK_MASK_CONST(0x3fffffff) << APBDMACHAN_CHANNEL_8_AHB_PTR_0_AHB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_8_AHB_PTR_0_AHB_BASE_RANGE                   31:2
+#define APBDMACHAN_CHANNEL_8_AHB_PTR_0_AHB_BASE_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_8_AHB_PTR_0_AHB_BASE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_AHB_PTR_0_AHB_BASE_DEFAULT_MASK                    _MK_MASK_CONST(0x3fffffff)
+#define APBDMACHAN_CHANNEL_8_AHB_PTR_0_AHB_BASE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_AHB_PTR_0_AHB_BASE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_8_AHB_SEQ_0  
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0                  _MK_ADDR_CONST(0x114)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_SECURE                   0x0
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_RESET_VAL                        _MK_MASK_CONST(0x20000000)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_RESET_MASK                       _MK_MASK_CONST(0xff0f0000)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_READ_MASK                        _MK_MASK_CONST(0xff0f0000)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_WRITE_MASK                       _MK_MASK_CONST(0xff0f0000)
+//  0 = send interrupt to COP
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_INTR_ENB_SHIFT                   _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_INTR_ENB_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_8_AHB_SEQ_0_INTR_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_INTR_ENB_RANGE                   31:31
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_INTR_ENB_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_INTR_ENB_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_INTR_ENB_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_INTR_ENB_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_INTR_ENB_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_INTR_ENB_CPU                     _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_INTR_ENB_COP                     _MK_ENUM_CONST(0)
+
+// AHB Bus Width 0 = 8 bit Bus (RSVD) 1 = 16 bit Bus (RSVD) 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD)4 = 128 bit Bus (RSVD)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT                      _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_BUS_WIDTH_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_BUS_WIDTH_RANGE                      30:28
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_BUS_WIDTH_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT                    _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_8                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_16                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_32                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_64                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_128                      _MK_ENUM_CONST(4)
+
+// When enabled the data going  to AHB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }.
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT                      _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_DATA_SWAP_FIELD                      (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_DATA_SWAP_RANGE                      27:27
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_DATA_SWAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_DATA_SWAP_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_DATA_SWAP_ENABLE                     _MK_ENUM_CONST(1)
+
+// AHB Burst Size DMA Burst Length (encoded) 4 = 1 Word (1x32bits) 5 = 4 Words (4x32bits)else = 8 Words (8x32bits) default
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_BURST_SHIFT                  _MK_SHIFT_CONST(24)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_BURST_FIELD                  (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_BURST_SHIFT)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_BURST_RANGE                  26:24
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_BURST_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_BURST_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_BURST_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_BURST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_BURST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_BURST_DMA_BURST_1WORDS                       _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_BURST_DMA_BURST_4WORDS                       _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_BURST_DMA_BURST_8WORDS                       _MK_ENUM_CONST(6)
+
+// 2X Double Buffering Mode (For Run-Multiple Mode with No Wrap Operations) 1 = Reload Base Address for 2X blocks (reload every other time) 0 = Reload Base Address for 1X blocks  (def) (reload each time)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_DBL_BUF_SHIFT                    _MK_SHIFT_CONST(19)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_DBL_BUF_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_8_AHB_SEQ_0_DBL_BUF_SHIFT)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_DBL_BUF_RANGE                    19:19
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_DBL_BUF_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_DBL_BUF_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_DBL_BUF_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_DBL_BUF_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_DBL_BUF_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_DBL_BUF_RELOAD_FOR_1X_BLOCKS                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_DBL_BUF_RELOAD_FOR_2X_BLOCKS                     _MK_ENUM_CONST(1)
+
+// AHB Address Wrap: AHB Address wrap-around window 0=No Wrap (default) 5=Wrap on 512 word window 1=Wrap on 32 word window 6=Wrap on 1024 word window 2=Wrap on 64 word window 7=Wrap on 2048 word window 3=Wrap on 128 word window 4=Wrap on 256 word window
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_WRAP_SHIFT                       _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_WRAP_FIELD                       (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_8_AHB_SEQ_0_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_WRAP_RANGE                       18:16
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_WRAP_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_WRAP_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_WRAP_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_WRAP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_WRAP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_WRAP_NO_WRAP                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_WRAP_WRAP_0N_32WORDS                     _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_WRAP_WRAP_ON_64WORDS                     _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_WRAP_WRAP_ON_128WORDS                    _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_WRAP_WRAP_ON_256WORDS                    _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_WRAP_WRAP_ON_512WORDS                    _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_WRAP_WRAP_ON_1024WORDS                   _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_WRAP_WRAP_ON_2048WORDS                   _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_8_APB_PTR_0  
+#define APBDMACHAN_CHANNEL_8_APB_PTR_0                  _MK_ADDR_CONST(0x118)
+#define APBDMACHAN_CHANNEL_8_APB_PTR_0_SECURE                   0x0
+#define APBDMACHAN_CHANNEL_8_APB_PTR_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_8_APB_PTR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_APB_PTR_0_RESET_MASK                       _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_8_APB_PTR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_APB_PTR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_APB_PTR_0_READ_MASK                        _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_8_APB_PTR_0_WRITE_MASK                       _MK_MASK_CONST(0xfffc)
+// APB-DMA Starting address for APB Bus: APB Base address:Upper 16 bits are fixed at 0x7000:XXXX
+#define APBDMACHAN_CHANNEL_8_APB_PTR_0_APB_BASE_SHIFT                   _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_8_APB_PTR_0_APB_BASE_FIELD                   (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_8_APB_PTR_0_APB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_8_APB_PTR_0_APB_BASE_RANGE                   15:2
+#define APBDMACHAN_CHANNEL_8_APB_PTR_0_APB_BASE_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_8_APB_PTR_0_APB_BASE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_APB_PTR_0_APB_BASE_DEFAULT_MASK                    _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_8_APB_PTR_0_APB_BASE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_APB_PTR_0_APB_BASE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_8_APB_SEQ_0  
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0                  _MK_ADDR_CONST(0x11c)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_SECURE                   0x0
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_RESET_VAL                        _MK_MASK_CONST(0x20010000)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_RESET_MASK                       _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_READ_MASK                        _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_WRITE_MASK                       _MK_MASK_CONST(0x78070000)
+// 0 = 8 bit Bus 1 = 16 bit Bus 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD) 4 = 128 bit BUS (RSVD)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_BUS_WIDTH_SHIFT                      _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_BUS_WIDTH_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_BUS_WIDTH_RANGE                      30:28
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_BUS_WIDTH_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT                    _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_8                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_16                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_32                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_64                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_128                      _MK_ENUM_CONST(4)
+
+// when enabled the data going  to APB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }.
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_DATA_SWAP_SHIFT                      _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_DATA_SWAP_FIELD                      (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_DATA_SWAP_RANGE                      27:27
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_DATA_SWAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_DATA_SWAP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_DATA_SWAP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_DATA_SWAP_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_DATA_SWAP_ENABLE                     _MK_ENUM_CONST(1)
+
+//APB Address Wrap-around Window 0 = No Wrap 1 = Wrap on 1 Word Window (def) 2 = Wrap on 2 Word Window 3 = Wrap on 4 Word Window 4 = Wrap on 8 Word Window 5 = Wrap on 16 Word Window 6 = Wrap on 32 Word Window 7 = Wrap on 64 Word Window (rsvd)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_ADDR_WRAP_SHIFT                      _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_ADDR_WRAP_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_ADDR_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_ADDR_WRAP_RANGE                      18:16
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_ADDR_WRAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_ADDR_WRAP_NO_WRAP                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_ADDR_WRAP_WRAP_0N_1WORDS                     _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_2WORDS                     _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_4WORDS                     _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_8WORDS                     _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_16WORDS                    _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_32WORDS                    _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_64WORDS                    _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_9_CSR_0  
+#define APBDMACHAN_CHANNEL_9_CSR_0                      _MK_ADDR_CONST(0x120)
+#define APBDMACHAN_CHANNEL_9_CSR_0_SECURE                       0x0
+#define APBDMACHAN_CHANNEL_9_CSR_0_WORD_COUNT                   0x1
+#define APBDMACHAN_CHANNEL_9_CSR_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_RESET_MASK                   _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_9_CSR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_READ_MASK                    _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_9_CSR_0_WRITE_MASK                   _MK_MASK_CONST(0xfffffffc)
+// Enables DMA channel transfer 
+#define APBDMACHAN_CHANNEL_9_CSR_0_ENB_SHIFT                    _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_9_CSR_0_ENB_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_9_CSR_0_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_9_CSR_0_ENB_RANGE                    31:31
+#define APBDMACHAN_CHANNEL_9_CSR_0_ENB_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_9_CSR_0_ENB_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_ENB_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_9_CSR_0_ENB_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_ENB_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_ENB_DISABLE                  _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_ENB_ENABLE                   _MK_ENUM_CONST(1)
+
+// Interrupts when DMA Block Transfer Completes 
+#define APBDMACHAN_CHANNEL_9_CSR_0_IE_EOC_SHIFT                 _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_9_CSR_0_IE_EOC_FIELD                 (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_9_CSR_0_IE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_9_CSR_0_IE_EOC_RANGE                 30:30
+#define APBDMACHAN_CHANNEL_9_CSR_0_IE_EOC_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_9_CSR_0_IE_EOC_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_IE_EOC_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_9_CSR_0_IE_EOC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_IE_EOC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_IE_EOC_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_IE_EOC_ENABLE                        _MK_ENUM_CONST(1)
+
+// Holds this Processor until DMA Block Transfer Completes 
+#define APBDMACHAN_CHANNEL_9_CSR_0_HOLD_SHIFT                   _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_9_CSR_0_HOLD_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_9_CSR_0_HOLD_SHIFT)
+#define APBDMACHAN_CHANNEL_9_CSR_0_HOLD_RANGE                   29:29
+#define APBDMACHAN_CHANNEL_9_CSR_0_HOLD_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_9_CSR_0_HOLD_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_HOLD_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_9_CSR_0_HOLD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_HOLD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_HOLD_DISABLE                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_HOLD_ENABLE                  _MK_ENUM_CONST(1)
+
+// DMA Transfer Direction 1 = AHB read to APB write 0 = APB read to AHB write
+#define APBDMACHAN_CHANNEL_9_CSR_0_DIR_SHIFT                    _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_9_CSR_0_DIR_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_9_CSR_0_DIR_SHIFT)
+#define APBDMACHAN_CHANNEL_9_CSR_0_DIR_RANGE                    28:28
+#define APBDMACHAN_CHANNEL_9_CSR_0_DIR_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_9_CSR_0_DIR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_DIR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_9_CSR_0_DIR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_DIR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_DIR_AHB_WRITE                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_DIR_AHB_READ                 _MK_ENUM_CONST(1)
+
+// Run Once or Run Multiple Mode (Allow Retriggering of this Channel) 1 = Run for One Block Transfer 0 = Run for Multiple Block Transfer
+#define APBDMACHAN_CHANNEL_9_CSR_0_ONCE_SHIFT                   _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_9_CSR_0_ONCE_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_9_CSR_0_ONCE_SHIFT)
+#define APBDMACHAN_CHANNEL_9_CSR_0_ONCE_RANGE                   27:27
+#define APBDMACHAN_CHANNEL_9_CSR_0_ONCE_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_9_CSR_0_ONCE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_ONCE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_9_CSR_0_ONCE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_ONCE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_ONCE_MULTIPLE_BLOCK                  _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_ONCE_SINGLE_BLOCK                    _MK_ENUM_CONST(1)
+
+// Enable on Non-Zero Value
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_SHIFT                       _MK_SHIFT_CONST(22)
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_FIELD                       (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_RANGE                       26:22
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_NA1                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_SMP24                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_SMP25                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_SMP26                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_SMP27                       _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_XRQ_A                       _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_XRQ_B                       _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_TMR1                        _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_TMR2                        _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_APB_0                       _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_APB_1                       _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_APB_2                       _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_APB_3                       _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_APB_4                       _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_APB_5                       _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_APB_6                       _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_APB_7                       _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_APB_8                       _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_APB_9                       _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_APB_10                      _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_APB_11                      _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_APB_12                      _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_APB_13                      _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_APB_14                      _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_APB_15                      _MK_ENUM_CONST(24)
+
+// Flow Control Enable (Synchronize Burst Transfers) 1 = Link to DRQ source 0 = Independent of DRQ request
+#define APBDMACHAN_CHANNEL_9_CSR_0_FLOW_SHIFT                   _MK_SHIFT_CONST(21)
+#define APBDMACHAN_CHANNEL_9_CSR_0_FLOW_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_9_CSR_0_FLOW_SHIFT)
+#define APBDMACHAN_CHANNEL_9_CSR_0_FLOW_RANGE                   21:21
+#define APBDMACHAN_CHANNEL_9_CSR_0_FLOW_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_9_CSR_0_FLOW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_FLOW_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_9_CSR_0_FLOW_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_FLOW_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_FLOW_DISABLE                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_FLOW_ENABLE                  _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_SHIFT                        _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_FIELD                        (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_RANGE                        20:16
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_CNTR_REQ                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_I2S_2                        _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_I2S_1                        _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_SPD_I                        _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_UI_I                 _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_MIPI                 _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_I2S2_2                       _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_I2S2_1                       _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_UART_A                       _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_UART_B                       _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_UART_C                       _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_SPI                  _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_AC97                 _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_ACModem                      _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_SL4B                 _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_SL2B1                        _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_SL2B2                        _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_SL2B3                        _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_SL2B4                        _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_UART_D                       _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_UART_E                       _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_I2C                  _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_I2C2                 _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_I2C3                 _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_DVC_I2C                      _MK_ENUM_CONST(24)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_OWR                  _MK_ENUM_CONST(25)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_NA26                 _MK_ENUM_CONST(26)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_NA27                 _MK_ENUM_CONST(27)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_NA28                 _MK_ENUM_CONST(28)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_NA29                 _MK_ENUM_CONST(29)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_NA30                 _MK_ENUM_CONST(30)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_NA31                 _MK_ENUM_CONST(31)
+
+// Number of 32bit word cycles
+#define APBDMACHAN_CHANNEL_9_CSR_0_WCOUNT_SHIFT                 _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_9_CSR_0_WCOUNT_FIELD                 (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_9_CSR_0_WCOUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_9_CSR_0_WCOUNT_RANGE                 15:2
+#define APBDMACHAN_CHANNEL_9_CSR_0_WCOUNT_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_9_CSR_0_WCOUNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_WCOUNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_9_CSR_0_WCOUNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_WCOUNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_9_STA_0  
+#define APBDMACHAN_CHANNEL_9_STA_0                      _MK_ADDR_CONST(0x124)
+#define APBDMACHAN_CHANNEL_9_STA_0_SECURE                       0x0
+#define APBDMACHAN_CHANNEL_9_STA_0_WORD_COUNT                   0x1
+#define APBDMACHAN_CHANNEL_9_STA_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_STA_0_RESET_MASK                   _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_9_STA_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_STA_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_STA_0_READ_MASK                    _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_9_STA_0_WRITE_MASK                   _MK_MASK_CONST(0x40000000)
+// indicate DMA Channel Status activate or not
+#define APBDMACHAN_CHANNEL_9_STA_0_BSY_SHIFT                    _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_9_STA_0_BSY_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_9_STA_0_BSY_SHIFT)
+#define APBDMACHAN_CHANNEL_9_STA_0_BSY_RANGE                    31:31
+#define APBDMACHAN_CHANNEL_9_STA_0_BSY_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_9_STA_0_BSY_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_STA_0_BSY_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_9_STA_0_BSY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_STA_0_BSY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_STA_0_BSY_WAIT                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_9_STA_0_BSY_ACTIVE                   _MK_ENUM_CONST(1)
+
+//  Write '1' to clear the flag
+#define APBDMACHAN_CHANNEL_9_STA_0_ISE_EOC_SHIFT                        _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_9_STA_0_ISE_EOC_FIELD                        (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_9_STA_0_ISE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_9_STA_0_ISE_EOC_RANGE                        30:30
+#define APBDMACHAN_CHANNEL_9_STA_0_ISE_EOC_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_9_STA_0_ISE_EOC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_STA_0_ISE_EOC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_9_STA_0_ISE_EOC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_STA_0_ISE_EOC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_STA_0_ISE_EOC_NO_INTR                      _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_9_STA_0_ISE_EOC_INTR                 _MK_ENUM_CONST(1)
+
+// Holding Status of Processor 
+#define APBDMACHAN_CHANNEL_9_STA_0_HALT_SHIFT                   _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_9_STA_0_HALT_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_9_STA_0_HALT_SHIFT)
+#define APBDMACHAN_CHANNEL_9_STA_0_HALT_RANGE                   29:29
+#define APBDMACHAN_CHANNEL_9_STA_0_HALT_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_9_STA_0_HALT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_STA_0_HALT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_9_STA_0_HALT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_STA_0_HALT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_STA_0_HALT_NO_HALT                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_9_STA_0_HALT_HALT                    _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_9_STA_0_PING_PONG_STA_SHIFT                  _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_9_STA_0_PING_PONG_STA_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_9_STA_0_PING_PONG_STA_SHIFT)
+#define APBDMACHAN_CHANNEL_9_STA_0_PING_PONG_STA_RANGE                  28:28
+#define APBDMACHAN_CHANNEL_9_STA_0_PING_PONG_STA_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_9_STA_0_PING_PONG_STA_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_STA_0_PING_PONG_STA_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_9_STA_0_PING_PONG_STA_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_STA_0_PING_PONG_STA_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_STA_0_PING_PONG_STA_PING_INTR_STA                  _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_9_STA_0_PING_PONG_STA_PONG_INTR_STA                  _MK_ENUM_CONST(1)
+
+// Current 32bit word cycles Flags set /cleared by HW
+#define APBDMACHAN_CHANNEL_9_STA_0_COUNT_SHIFT                  _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_9_STA_0_COUNT_FIELD                  (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_9_STA_0_COUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_9_STA_0_COUNT_RANGE                  15:2
+#define APBDMACHAN_CHANNEL_9_STA_0_COUNT_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_9_STA_0_COUNT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_STA_0_COUNT_DEFAULT_MASK                   _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_9_STA_0_COUNT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_STA_0_COUNT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Reserved address 296 [0x128] 
+
+// Reserved address 300 [0x12c] 
+
+// Register APBDMACHAN_CHANNEL_9_AHB_PTR_0  
+#define APBDMACHAN_CHANNEL_9_AHB_PTR_0                  _MK_ADDR_CONST(0x130)
+#define APBDMACHAN_CHANNEL_9_AHB_PTR_0_SECURE                   0x0
+#define APBDMACHAN_CHANNEL_9_AHB_PTR_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_9_AHB_PTR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_AHB_PTR_0_RESET_MASK                       _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_9_AHB_PTR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_AHB_PTR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_AHB_PTR_0_READ_MASK                        _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_9_AHB_PTR_0_WRITE_MASK                       _MK_MASK_CONST(0xfffffffc)
+// APB-DMA Starting Address for AHB Bus: SW writes to  modify
+#define APBDMACHAN_CHANNEL_9_AHB_PTR_0_AHB_BASE_SHIFT                   _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_9_AHB_PTR_0_AHB_BASE_FIELD                   (_MK_MASK_CONST(0x3fffffff) << APBDMACHAN_CHANNEL_9_AHB_PTR_0_AHB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_9_AHB_PTR_0_AHB_BASE_RANGE                   31:2
+#define APBDMACHAN_CHANNEL_9_AHB_PTR_0_AHB_BASE_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_9_AHB_PTR_0_AHB_BASE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_AHB_PTR_0_AHB_BASE_DEFAULT_MASK                    _MK_MASK_CONST(0x3fffffff)
+#define APBDMACHAN_CHANNEL_9_AHB_PTR_0_AHB_BASE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_AHB_PTR_0_AHB_BASE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_9_AHB_SEQ_0  
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0                  _MK_ADDR_CONST(0x134)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_SECURE                   0x0
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_RESET_VAL                        _MK_MASK_CONST(0x20000000)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_RESET_MASK                       _MK_MASK_CONST(0xff0f0000)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_READ_MASK                        _MK_MASK_CONST(0xff0f0000)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_WRITE_MASK                       _MK_MASK_CONST(0xff0f0000)
+//  0 = send interrupt to COP
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_INTR_ENB_SHIFT                   _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_INTR_ENB_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_9_AHB_SEQ_0_INTR_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_INTR_ENB_RANGE                   31:31
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_INTR_ENB_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_INTR_ENB_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_INTR_ENB_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_INTR_ENB_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_INTR_ENB_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_INTR_ENB_CPU                     _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_INTR_ENB_COP                     _MK_ENUM_CONST(0)
+
+// AHB Bus Width 0 = 8 bit Bus (RSVD) 1 = 16 bit Bus (RSVD) 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD)4 = 128 bit Bus (RSVD)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT                      _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_BUS_WIDTH_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_BUS_WIDTH_RANGE                      30:28
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_BUS_WIDTH_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT                    _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_8                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_16                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_32                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_64                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_128                      _MK_ENUM_CONST(4)
+
+//When enabled the data going to AHB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT                      _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_DATA_SWAP_FIELD                      (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_DATA_SWAP_RANGE                      27:27
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_DATA_SWAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_DATA_SWAP_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_DATA_SWAP_ENABLE                     _MK_ENUM_CONST(1)
+
+// AHB Burst Size DMA Burst Length (encoded) 4 = 1 Word (1x32bits) 5 = 4 Words (4x32bits)else = 8 Words (8x32bits) default
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_BURST_SHIFT                  _MK_SHIFT_CONST(24)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_BURST_FIELD                  (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_BURST_SHIFT)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_BURST_RANGE                  26:24
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_BURST_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_BURST_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_BURST_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_BURST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_BURST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_BURST_DMA_BURST_1WORDS                       _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_BURST_DMA_BURST_4WORDS                       _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_BURST_DMA_BURST_8WORDS                       _MK_ENUM_CONST(6)
+
+// 2X Double Buffering Mode (For Run-Multiple Mode with No Wrap Operations) 1 = Reload Base Address for 2X blocks (reload every other time) 0 = Reload Base Address for 1X blocks  (def) (reload each time)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_DBL_BUF_SHIFT                    _MK_SHIFT_CONST(19)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_DBL_BUF_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_9_AHB_SEQ_0_DBL_BUF_SHIFT)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_DBL_BUF_RANGE                    19:19
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_DBL_BUF_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_DBL_BUF_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_DBL_BUF_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_DBL_BUF_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_DBL_BUF_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_DBL_BUF_RELOAD_FOR_1X_BLOCKS                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_DBL_BUF_RELOAD_FOR_2X_BLOCKS                     _MK_ENUM_CONST(1)
+
+// AHB Address Wrap: AHB Address wrap-around window 0=No Wrap (default) 5=Wrap on 512 word window 1=Wrap on 32 word window 6=Wrap on 1024 word window 2=Wrap on 64 word window 7=Wrap on 2048 word window 3=Wrap on 128 word window 4=Wrap on 256 word window
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_WRAP_SHIFT                       _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_WRAP_FIELD                       (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_9_AHB_SEQ_0_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_WRAP_RANGE                       18:16
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_WRAP_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_WRAP_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_WRAP_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_WRAP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_WRAP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_WRAP_NO_WRAP                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_WRAP_WRAP_0N_32WORDS                     _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_WRAP_WRAP_ON_64WORDS                     _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_WRAP_WRAP_ON_128WORDS                    _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_WRAP_WRAP_ON_256WORDS                    _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_WRAP_WRAP_ON_512WORDS                    _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_WRAP_WRAP_ON_1024WORDS                   _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_WRAP_WRAP_ON_2048WORDS                   _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_9_APB_PTR_0  
+#define APBDMACHAN_CHANNEL_9_APB_PTR_0                  _MK_ADDR_CONST(0x138)
+#define APBDMACHAN_CHANNEL_9_APB_PTR_0_SECURE                   0x0
+#define APBDMACHAN_CHANNEL_9_APB_PTR_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_9_APB_PTR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_APB_PTR_0_RESET_MASK                       _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_9_APB_PTR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_APB_PTR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_APB_PTR_0_READ_MASK                        _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_9_APB_PTR_0_WRITE_MASK                       _MK_MASK_CONST(0xfffc)
+//APB-DMA Starting address for APB Bus: APB Base address: Upper 16 bits are fixed at 0x7000:XXXX
+#define APBDMACHAN_CHANNEL_9_APB_PTR_0_APB_BASE_SHIFT                   _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_9_APB_PTR_0_APB_BASE_FIELD                   (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_9_APB_PTR_0_APB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_9_APB_PTR_0_APB_BASE_RANGE                   15:2
+#define APBDMACHAN_CHANNEL_9_APB_PTR_0_APB_BASE_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_9_APB_PTR_0_APB_BASE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_APB_PTR_0_APB_BASE_DEFAULT_MASK                    _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_9_APB_PTR_0_APB_BASE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_APB_PTR_0_APB_BASE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_9_APB_SEQ_0  
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0                  _MK_ADDR_CONST(0x13c)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_SECURE                   0x0
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_RESET_VAL                        _MK_MASK_CONST(0x20010000)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_RESET_MASK                       _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_READ_MASK                        _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_WRITE_MASK                       _MK_MASK_CONST(0x78070000)
+// 0 = 8 bit Bus 1 = 16 bit Bus 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD) 4 = 128 bit BUS (RSVD)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_BUS_WIDTH_SHIFT                      _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_BUS_WIDTH_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_BUS_WIDTH_RANGE                      30:28
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_BUS_WIDTH_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT                    _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_8                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_16                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_32                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_64                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_128                      _MK_ENUM_CONST(4)
+
+// When enabled the data going  to APB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_DATA_SWAP_SHIFT                      _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_DATA_SWAP_FIELD                      (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_DATA_SWAP_RANGE                      27:27
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_DATA_SWAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_DATA_SWAP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_DATA_SWAP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_DATA_SWAP_DISBALE                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_DATA_SWAP_ENABLE                     _MK_ENUM_CONST(1)
+
+//APB Address Wrap-around Window 0 = No Wrap 1 = Wrap on 1 Word Window (def) 2 = Wrap on 2 Word Window 3 = Wrap on 4 Word Window 4 = Wrap on 8 Word Window 5 = Wrap on 16 Word Window 6 = Wrap on 32 Word Window 7 = Wrap on 64 Word Window (rsvd)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_ADDR_WRAP_SHIFT                      _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_ADDR_WRAP_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_ADDR_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_ADDR_WRAP_RANGE                      18:16
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_ADDR_WRAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_ADDR_WRAP_NO_WRAP                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_ADDR_WRAP_WRAP_0N_1WORDS                     _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_2WORDS                     _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_4WORDS                     _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_8WORDS                     _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_16WORDS                    _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_32WORDS                    _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_64WORDS                    _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_10_CSR_0  
+#define APBDMACHAN_CHANNEL_10_CSR_0                     _MK_ADDR_CONST(0x140)
+#define APBDMACHAN_CHANNEL_10_CSR_0_SECURE                      0x0
+#define APBDMACHAN_CHANNEL_10_CSR_0_WORD_COUNT                  0x1
+#define APBDMACHAN_CHANNEL_10_CSR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_RESET_MASK                  _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_10_CSR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_READ_MASK                   _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_10_CSR_0_WRITE_MASK                  _MK_MASK_CONST(0xfffffffc)
+// Enables DMA channel transfer 
+#define APBDMACHAN_CHANNEL_10_CSR_0_ENB_SHIFT                   _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_10_CSR_0_ENB_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_10_CSR_0_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_10_CSR_0_ENB_RANGE                   31:31
+#define APBDMACHAN_CHANNEL_10_CSR_0_ENB_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_10_CSR_0_ENB_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_ENB_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_10_CSR_0_ENB_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_ENB_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_ENB_DISABLE                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_ENB_ENABLE                  _MK_ENUM_CONST(1)
+
+// Interrupts when DMA Block Transfer Completes
+#define APBDMACHAN_CHANNEL_10_CSR_0_IE_EOC_SHIFT                        _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_10_CSR_0_IE_EOC_FIELD                        (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_10_CSR_0_IE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_10_CSR_0_IE_EOC_RANGE                        30:30
+#define APBDMACHAN_CHANNEL_10_CSR_0_IE_EOC_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_10_CSR_0_IE_EOC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_IE_EOC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_10_CSR_0_IE_EOC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_IE_EOC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_IE_EOC_DISABLE                      _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_IE_EOC_ENABLE                       _MK_ENUM_CONST(1)
+
+// Holds this Processor until DMA Block Transfer Completes
+#define APBDMACHAN_CHANNEL_10_CSR_0_HOLD_SHIFT                  _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_10_CSR_0_HOLD_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_10_CSR_0_HOLD_SHIFT)
+#define APBDMACHAN_CHANNEL_10_CSR_0_HOLD_RANGE                  29:29
+#define APBDMACHAN_CHANNEL_10_CSR_0_HOLD_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_10_CSR_0_HOLD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_HOLD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_10_CSR_0_HOLD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_HOLD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_HOLD_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_HOLD_ENABLE                 _MK_ENUM_CONST(1)
+
+// DMA Transfer Direction 1 = AHB read to APB write 0 = APB read to AHB write
+#define APBDMACHAN_CHANNEL_10_CSR_0_DIR_SHIFT                   _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_10_CSR_0_DIR_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_10_CSR_0_DIR_SHIFT)
+#define APBDMACHAN_CHANNEL_10_CSR_0_DIR_RANGE                   28:28
+#define APBDMACHAN_CHANNEL_10_CSR_0_DIR_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_10_CSR_0_DIR_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_DIR_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_10_CSR_0_DIR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_DIR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_DIR_AHB_WRITE                       _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_DIR_AHB_READ                        _MK_ENUM_CONST(1)
+
+// Run Once or Run Multiple Mode (Allow Retriggering of this Channel) 1 = Run for One Block Transfer 0 = Run for Multiple Block Transfer
+#define APBDMACHAN_CHANNEL_10_CSR_0_ONCE_SHIFT                  _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_10_CSR_0_ONCE_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_10_CSR_0_ONCE_SHIFT)
+#define APBDMACHAN_CHANNEL_10_CSR_0_ONCE_RANGE                  27:27
+#define APBDMACHAN_CHANNEL_10_CSR_0_ONCE_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_10_CSR_0_ONCE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_ONCE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_10_CSR_0_ONCE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_ONCE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_ONCE_MULTIPLE_BLOCK                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_ONCE_SINGLE_BLOCK                   _MK_ENUM_CONST(1)
+
+// Enable on Non-Zero Value
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_SHIFT                      _MK_SHIFT_CONST(22)
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_FIELD                      (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_RANGE                      26:22
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_NA1                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_SMP24                      _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_SMP25                      _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_SMP26                      _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_SMP27                      _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_XRQ_A                      _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_XRQ_B                      _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_TMR1                       _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_TMR2                       _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_APB_0                      _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_APB_1                      _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_APB_2                      _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_APB_3                      _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_APB_4                      _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_APB_5                      _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_APB_6                      _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_APB_7                      _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_APB_8                      _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_APB_9                      _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_APB_10                     _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_APB_11                     _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_APB_12                     _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_APB_13                     _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_APB_14                     _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_APB_15                     _MK_ENUM_CONST(24)
+
+// Flow Control Enable (Synchronize Burst Transfers) 1 = Link to DRQ source 0 = Independent of DRQ request
+#define APBDMACHAN_CHANNEL_10_CSR_0_FLOW_SHIFT                  _MK_SHIFT_CONST(21)
+#define APBDMACHAN_CHANNEL_10_CSR_0_FLOW_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_10_CSR_0_FLOW_SHIFT)
+#define APBDMACHAN_CHANNEL_10_CSR_0_FLOW_RANGE                  21:21
+#define APBDMACHAN_CHANNEL_10_CSR_0_FLOW_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_10_CSR_0_FLOW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_FLOW_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_10_CSR_0_FLOW_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_FLOW_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_FLOW_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_FLOW_ENABLE                 _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_SHIFT                       _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_FIELD                       (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_RANGE                       20:16
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_CNTR_REQ                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_I2S_2                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_I2S_1                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_SPD_I                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_UI_I                        _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_MIPI                        _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_I2S2_2                      _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_I2S2_1                      _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_UART_A                      _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_UART_B                      _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_UART_C                      _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_SPI                 _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_AC97                        _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_ACModem                     _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_SL4B                        _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_SL2B1                       _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_SL2B2                       _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_SL2B3                       _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_SL2B4                       _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_UART_D                      _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_UART_E                      _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_I2C                 _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_I2C2                        _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_I2C3                        _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_DVC_I2C                     _MK_ENUM_CONST(24)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_OWR                 _MK_ENUM_CONST(25)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_NA26                        _MK_ENUM_CONST(26)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_NA27                        _MK_ENUM_CONST(27)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_NA28                        _MK_ENUM_CONST(28)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_NA29                        _MK_ENUM_CONST(29)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_NA30                        _MK_ENUM_CONST(30)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_NA31                        _MK_ENUM_CONST(31)
+
+// Number of 32bit word cycles
+#define APBDMACHAN_CHANNEL_10_CSR_0_WCOUNT_SHIFT                        _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_10_CSR_0_WCOUNT_FIELD                        (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_10_CSR_0_WCOUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_10_CSR_0_WCOUNT_RANGE                        15:2
+#define APBDMACHAN_CHANNEL_10_CSR_0_WCOUNT_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_10_CSR_0_WCOUNT_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_WCOUNT_DEFAULT_MASK                 _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_10_CSR_0_WCOUNT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_WCOUNT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_10_STA_0  
+#define APBDMACHAN_CHANNEL_10_STA_0                     _MK_ADDR_CONST(0x144)
+#define APBDMACHAN_CHANNEL_10_STA_0_SECURE                      0x0
+#define APBDMACHAN_CHANNEL_10_STA_0_WORD_COUNT                  0x1
+#define APBDMACHAN_CHANNEL_10_STA_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_STA_0_RESET_MASK                  _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_10_STA_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_STA_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_STA_0_READ_MASK                   _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_10_STA_0_WRITE_MASK                  _MK_MASK_CONST(0x40000000)
+// indicate DMA Channel Status activated or not 
+#define APBDMACHAN_CHANNEL_10_STA_0_BSY_SHIFT                   _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_10_STA_0_BSY_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_10_STA_0_BSY_SHIFT)
+#define APBDMACHAN_CHANNEL_10_STA_0_BSY_RANGE                   31:31
+#define APBDMACHAN_CHANNEL_10_STA_0_BSY_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_10_STA_0_BSY_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_STA_0_BSY_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_10_STA_0_BSY_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_STA_0_BSY_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_STA_0_BSY_WAIT                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_10_STA_0_BSY_ACTIVE                  _MK_ENUM_CONST(1)
+
+// Write '1' to clear the flag
+#define APBDMACHAN_CHANNEL_10_STA_0_ISE_EOC_SHIFT                       _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_10_STA_0_ISE_EOC_FIELD                       (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_10_STA_0_ISE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_10_STA_0_ISE_EOC_RANGE                       30:30
+#define APBDMACHAN_CHANNEL_10_STA_0_ISE_EOC_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_10_STA_0_ISE_EOC_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_STA_0_ISE_EOC_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_10_STA_0_ISE_EOC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_STA_0_ISE_EOC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_STA_0_ISE_EOC_NO_INTR                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_10_STA_0_ISE_EOC_INTR                        _MK_ENUM_CONST(1)
+
+// Holding Status of Processor 
+#define APBDMACHAN_CHANNEL_10_STA_0_HALT_SHIFT                  _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_10_STA_0_HALT_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_10_STA_0_HALT_SHIFT)
+#define APBDMACHAN_CHANNEL_10_STA_0_HALT_RANGE                  29:29
+#define APBDMACHAN_CHANNEL_10_STA_0_HALT_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_10_STA_0_HALT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_STA_0_HALT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_10_STA_0_HALT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_STA_0_HALT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_STA_0_HALT_NO_HALT                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_10_STA_0_HALT_HALT                   _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_10_STA_0_PING_PONG_STA_SHIFT                 _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_10_STA_0_PING_PONG_STA_FIELD                 (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_10_STA_0_PING_PONG_STA_SHIFT)
+#define APBDMACHAN_CHANNEL_10_STA_0_PING_PONG_STA_RANGE                 28:28
+#define APBDMACHAN_CHANNEL_10_STA_0_PING_PONG_STA_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_10_STA_0_PING_PONG_STA_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_STA_0_PING_PONG_STA_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_10_STA_0_PING_PONG_STA_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_STA_0_PING_PONG_STA_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_STA_0_PING_PONG_STA_PING_INTR_STA                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_10_STA_0_PING_PONG_STA_PONG_INTR_STA                 _MK_ENUM_CONST(1)
+
+// Current 32bit word cycles Flags set /cleared by HW
+#define APBDMACHAN_CHANNEL_10_STA_0_COUNT_SHIFT                 _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_10_STA_0_COUNT_FIELD                 (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_10_STA_0_COUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_10_STA_0_COUNT_RANGE                 15:2
+#define APBDMACHAN_CHANNEL_10_STA_0_COUNT_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_10_STA_0_COUNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_STA_0_COUNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_10_STA_0_COUNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_STA_0_COUNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Reserved address 328 [0x148] 
+
+// Reserved address 332 [0x14c] 
+
+// Register APBDMACHAN_CHANNEL_10_AHB_PTR_0  
+#define APBDMACHAN_CHANNEL_10_AHB_PTR_0                 _MK_ADDR_CONST(0x150)
+#define APBDMACHAN_CHANNEL_10_AHB_PTR_0_SECURE                  0x0
+#define APBDMACHAN_CHANNEL_10_AHB_PTR_0_WORD_COUNT                      0x1
+#define APBDMACHAN_CHANNEL_10_AHB_PTR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_AHB_PTR_0_RESET_MASK                      _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_10_AHB_PTR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_AHB_PTR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_AHB_PTR_0_READ_MASK                       _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_10_AHB_PTR_0_WRITE_MASK                      _MK_MASK_CONST(0xfffffffc)
+// APB-DMA Starting Address for AHB Bus: SW writes to  modify
+#define APBDMACHAN_CHANNEL_10_AHB_PTR_0_AHB_BASE_SHIFT                  _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_10_AHB_PTR_0_AHB_BASE_FIELD                  (_MK_MASK_CONST(0x3fffffff) << APBDMACHAN_CHANNEL_10_AHB_PTR_0_AHB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_10_AHB_PTR_0_AHB_BASE_RANGE                  31:2
+#define APBDMACHAN_CHANNEL_10_AHB_PTR_0_AHB_BASE_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_10_AHB_PTR_0_AHB_BASE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_AHB_PTR_0_AHB_BASE_DEFAULT_MASK                   _MK_MASK_CONST(0x3fffffff)
+#define APBDMACHAN_CHANNEL_10_AHB_PTR_0_AHB_BASE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_AHB_PTR_0_AHB_BASE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_10_AHB_SEQ_0  
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0                 _MK_ADDR_CONST(0x154)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_SECURE                  0x0
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_WORD_COUNT                      0x1
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_RESET_VAL                       _MK_MASK_CONST(0x20000000)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_RESET_MASK                      _MK_MASK_CONST(0xff0f0000)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_READ_MASK                       _MK_MASK_CONST(0xff0f0000)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_WRITE_MASK                      _MK_MASK_CONST(0xff0f0000)
+//  0 = send interrupt to COP
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_INTR_ENB_SHIFT                  _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_INTR_ENB_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_10_AHB_SEQ_0_INTR_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_INTR_ENB_RANGE                  31:31
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_INTR_ENB_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_INTR_ENB_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_INTR_ENB_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_INTR_ENB_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_INTR_ENB_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_INTR_ENB_CPU                    _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_INTR_ENB_COP                    _MK_ENUM_CONST(0)
+
+// AHB Bus Width 0 = 8 bit Bus (RSVD) 1 = 16 bit Bus (RSVD) 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD)4 = 128 bit Bus (RSVD)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT                     _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_BUS_WIDTH_FIELD                     (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_BUS_WIDTH_RANGE                     30:28
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_BUS_WIDTH_WOFFSET                   0x0
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT                   _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_8                       _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_16                      _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_32                      _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_64                      _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_128                     _MK_ENUM_CONST(4)
+
+// when enabled the data going  to AHB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT                     _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_DATA_SWAP_FIELD                     (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_DATA_SWAP_RANGE                     27:27
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_DATA_SWAP_WOFFSET                   0x0
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_DATA_SWAP_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_DATA_SWAP_ENABLE                    _MK_ENUM_CONST(1)
+
+// AHB Burst Size DMA Burst Length (encoded) 4 = 1 Word (1x32bits) 5 = 4 Words (4x32bits)else = 8 Words (8x32bits) default
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_BURST_SHIFT                 _MK_SHIFT_CONST(24)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_BURST_FIELD                 (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_BURST_SHIFT)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_BURST_RANGE                 26:24
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_BURST_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_BURST_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_BURST_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_BURST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_BURST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_BURST_DMA_BURST_1WORDS                      _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_BURST_DMA_BURST_4WORDS                      _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_BURST_DMA_BURST_8WORDS                      _MK_ENUM_CONST(6)
+
+// 2X Double Buffering Mode (For Run-Multiple Mode with No Wrap Operations) 1 = Reload Base Address for 2X blocks (reload every other time) 0 = Reload Base Address for 1X blocks  (def) (reload each time)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_DBL_BUF_SHIFT                   _MK_SHIFT_CONST(19)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_DBL_BUF_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_10_AHB_SEQ_0_DBL_BUF_SHIFT)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_DBL_BUF_RANGE                   19:19
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_DBL_BUF_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_DBL_BUF_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_DBL_BUF_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_DBL_BUF_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_DBL_BUF_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_DBL_BUF_RELOAD_FOR_1X_BLOCKS                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_DBL_BUF_RELOAD_FOR_2X_BLOCKS                    _MK_ENUM_CONST(1)
+
+// AHB Address Wrap: AHB Address wrap-around window 0=No Wrap (default) 5=Wrap on 512 word window 1=Wrap on 32 word window 6=Wrap on 1024 word window 2=Wrap on 64 word window 7=Wrap on 2048 word window 3=Wrap on 128 word window 4=Wrap on 256 word window
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_WRAP_SHIFT                      _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_WRAP_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_10_AHB_SEQ_0_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_WRAP_RANGE                      18:16
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_WRAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_WRAP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_WRAP_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_WRAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_WRAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_WRAP_NO_WRAP                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_WRAP_WRAP_0N_32WORDS                    _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_WRAP_WRAP_ON_64WORDS                    _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_WRAP_WRAP_ON_128WORDS                   _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_WRAP_WRAP_ON_256WORDS                   _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_WRAP_WRAP_ON_512WORDS                   _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_WRAP_WRAP_ON_1024WORDS                  _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_WRAP_WRAP_ON_2048WORDS                  _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_10_APB_PTR_0  
+#define APBDMACHAN_CHANNEL_10_APB_PTR_0                 _MK_ADDR_CONST(0x158)
+#define APBDMACHAN_CHANNEL_10_APB_PTR_0_SECURE                  0x0
+#define APBDMACHAN_CHANNEL_10_APB_PTR_0_WORD_COUNT                      0x1
+#define APBDMACHAN_CHANNEL_10_APB_PTR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_APB_PTR_0_RESET_MASK                      _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_10_APB_PTR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_APB_PTR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_APB_PTR_0_READ_MASK                       _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_10_APB_PTR_0_WRITE_MASK                      _MK_MASK_CONST(0xfffc)
+// APB-DMA Starting address for APB Bus: APB Base  address: Upper 16 bits are fixed at 0x7000:XXXX
+#define APBDMACHAN_CHANNEL_10_APB_PTR_0_APB_BASE_SHIFT                  _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_10_APB_PTR_0_APB_BASE_FIELD                  (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_10_APB_PTR_0_APB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_10_APB_PTR_0_APB_BASE_RANGE                  15:2
+#define APBDMACHAN_CHANNEL_10_APB_PTR_0_APB_BASE_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_10_APB_PTR_0_APB_BASE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_APB_PTR_0_APB_BASE_DEFAULT_MASK                   _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_10_APB_PTR_0_APB_BASE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_APB_PTR_0_APB_BASE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_10_APB_SEQ_0  
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0                 _MK_ADDR_CONST(0x15c)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_SECURE                  0x0
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_WORD_COUNT                      0x1
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_RESET_VAL                       _MK_MASK_CONST(0x20010000)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_RESET_MASK                      _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_READ_MASK                       _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_WRITE_MASK                      _MK_MASK_CONST(0x78070000)
+// 0 = 8 bit Bus 1 = 16 bit Bus 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD) 4 = 128 bit BUS (RSVD)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_BUS_WIDTH_SHIFT                     _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_BUS_WIDTH_FIELD                     (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_BUS_WIDTH_RANGE                     30:28
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_BUS_WIDTH_WOFFSET                   0x0
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT                   _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_8                       _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_16                      _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_32                      _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_64                      _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_128                     _MK_ENUM_CONST(4)
+
+// when enabled the data going  to APB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_DATA_SWAP_SHIFT                     _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_DATA_SWAP_FIELD                     (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_DATA_SWAP_RANGE                     27:27
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_DATA_SWAP_WOFFSET                   0x0
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_DATA_SWAP_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_DATA_SWAP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_DATA_SWAP_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_DATA_SWAP_ENABLE                    _MK_ENUM_CONST(1)
+
+//APB Address Wrap-around Window 0 = No Wrap 1 = Wrap on 1 Word Window (def) 2 = Wrap on 2 Word Window 3 = Wrap on 4 Word Window 4 = Wrap on 8 Word Window 5 = Wrap on 16 Word Window 6 = Wrap on 32 Word Window 7 = Wrap on 64 Word Window (rsvd)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_ADDR_WRAP_SHIFT                     _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_ADDR_WRAP_FIELD                     (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_ADDR_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_ADDR_WRAP_RANGE                     18:16
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_ADDR_WRAP_WOFFSET                   0x0
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_ADDR_WRAP_NO_WRAP                   _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_ADDR_WRAP_WRAP_0N_1WORDS                    _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_2WORDS                    _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_4WORDS                    _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_8WORDS                    _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_16WORDS                   _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_32WORDS                   _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_64WORDS                   _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_11_CSR_0  
+#define APBDMACHAN_CHANNEL_11_CSR_0                     _MK_ADDR_CONST(0x160)
+#define APBDMACHAN_CHANNEL_11_CSR_0_SECURE                      0x0
+#define APBDMACHAN_CHANNEL_11_CSR_0_WORD_COUNT                  0x1
+#define APBDMACHAN_CHANNEL_11_CSR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_RESET_MASK                  _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_11_CSR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_READ_MASK                   _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_11_CSR_0_WRITE_MASK                  _MK_MASK_CONST(0xfffffffc)
+// Enables DMA channel transfer 
+#define APBDMACHAN_CHANNEL_11_CSR_0_ENB_SHIFT                   _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_11_CSR_0_ENB_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_11_CSR_0_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_11_CSR_0_ENB_RANGE                   31:31
+#define APBDMACHAN_CHANNEL_11_CSR_0_ENB_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_11_CSR_0_ENB_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_ENB_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_11_CSR_0_ENB_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_ENB_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_ENB_DISABLE                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_ENB_ENABLE                  _MK_ENUM_CONST(1)
+
+// Interrupts when DMA Block Transfer Completes
+#define APBDMACHAN_CHANNEL_11_CSR_0_IE_EOC_SHIFT                        _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_11_CSR_0_IE_EOC_FIELD                        (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_11_CSR_0_IE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_11_CSR_0_IE_EOC_RANGE                        30:30
+#define APBDMACHAN_CHANNEL_11_CSR_0_IE_EOC_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_11_CSR_0_IE_EOC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_IE_EOC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_11_CSR_0_IE_EOC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_IE_EOC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_IE_EOC_DISABLE                      _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_IE_EOC_ENABLE                       _MK_ENUM_CONST(1)
+
+// Holds this Processor until DMA Block Transfer Completes
+#define APBDMACHAN_CHANNEL_11_CSR_0_HOLD_SHIFT                  _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_11_CSR_0_HOLD_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_11_CSR_0_HOLD_SHIFT)
+#define APBDMACHAN_CHANNEL_11_CSR_0_HOLD_RANGE                  29:29
+#define APBDMACHAN_CHANNEL_11_CSR_0_HOLD_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_11_CSR_0_HOLD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_HOLD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_11_CSR_0_HOLD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_HOLD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_HOLD_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_HOLD_ENABLE                 _MK_ENUM_CONST(1)
+
+// DMA Transfer Direction 1 = AHB read to APB write 0 = APB read to AHB write
+#define APBDMACHAN_CHANNEL_11_CSR_0_DIR_SHIFT                   _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_11_CSR_0_DIR_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_11_CSR_0_DIR_SHIFT)
+#define APBDMACHAN_CHANNEL_11_CSR_0_DIR_RANGE                   28:28
+#define APBDMACHAN_CHANNEL_11_CSR_0_DIR_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_11_CSR_0_DIR_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_DIR_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_11_CSR_0_DIR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_DIR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_DIR_AHB_WRITE                       _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_DIR_AHB_READ                        _MK_ENUM_CONST(1)
+
+// Run Once or Run Multiple Mode (Allow Retriggering of this Channel) 1 = Run for One Block Transfer 0 = Run for Multiple Block Transfer
+#define APBDMACHAN_CHANNEL_11_CSR_0_ONCE_SHIFT                  _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_11_CSR_0_ONCE_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_11_CSR_0_ONCE_SHIFT)
+#define APBDMACHAN_CHANNEL_11_CSR_0_ONCE_RANGE                  27:27
+#define APBDMACHAN_CHANNEL_11_CSR_0_ONCE_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_11_CSR_0_ONCE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_ONCE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_11_CSR_0_ONCE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_ONCE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_ONCE_MULTIPLE_BLOCK                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_ONCE_SINGLE_BLOCK                   _MK_ENUM_CONST(1)
+
+// Enable on Non-Zero Value
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_SHIFT                      _MK_SHIFT_CONST(22)
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_FIELD                      (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_RANGE                      26:22
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_NA1                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_SMP24                      _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_SMP25                      _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_SMP26                      _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_SMP27                      _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_XRQ_A                      _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_XRQ_B                      _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_TMR1                       _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_TMR2                       _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_APB_0                      _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_APB_1                      _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_APB_2                      _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_APB_3                      _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_APB_4                      _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_APB_5                      _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_APB_6                      _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_APB_7                      _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_APB_8                      _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_APB_9                      _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_APB_10                     _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_APB_11                     _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_APB_12                     _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_APB_13                     _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_APB_14                     _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_APB_15                     _MK_ENUM_CONST(24)
+
+// Flow Control Enable (Synchronize Burst Transfers) 1 = Link to DRQ source 0 = Independent of DRQ request
+#define APBDMACHAN_CHANNEL_11_CSR_0_FLOW_SHIFT                  _MK_SHIFT_CONST(21)
+#define APBDMACHAN_CHANNEL_11_CSR_0_FLOW_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_11_CSR_0_FLOW_SHIFT)
+#define APBDMACHAN_CHANNEL_11_CSR_0_FLOW_RANGE                  21:21
+#define APBDMACHAN_CHANNEL_11_CSR_0_FLOW_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_11_CSR_0_FLOW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_FLOW_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_11_CSR_0_FLOW_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_FLOW_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_FLOW_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_FLOW_ENABLE                 _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_SHIFT                       _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_FIELD                       (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_RANGE                       20:16
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_CNTR_REQ                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_I2S_2                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_I2S_1                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_SPD_I                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_UI_I                        _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_MIPI                        _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_I2S2_2                      _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_I2S2_1                      _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_UART_A                      _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_UART_B                      _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_UART_C                      _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_SPI                 _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_AC97                        _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_ACModem                     _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_SL4B                        _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_SL2B1                       _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_SL2B2                       _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_SL2B3                       _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_SL2B4                       _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_UART_D                      _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_UART_E                      _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_I2C                 _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_I2C2                        _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_I2C3                        _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_DVC_I2C                     _MK_ENUM_CONST(24)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_OWR                 _MK_ENUM_CONST(25)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_NA26                        _MK_ENUM_CONST(26)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_NA27                        _MK_ENUM_CONST(27)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_NA28                        _MK_ENUM_CONST(28)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_NA29                        _MK_ENUM_CONST(29)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_NA30                        _MK_ENUM_CONST(30)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_NA31                        _MK_ENUM_CONST(31)
+
+// Number of 32bit word cycles
+#define APBDMACHAN_CHANNEL_11_CSR_0_WCOUNT_SHIFT                        _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_11_CSR_0_WCOUNT_FIELD                        (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_11_CSR_0_WCOUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_11_CSR_0_WCOUNT_RANGE                        15:2
+#define APBDMACHAN_CHANNEL_11_CSR_0_WCOUNT_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_11_CSR_0_WCOUNT_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_WCOUNT_DEFAULT_MASK                 _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_11_CSR_0_WCOUNT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_WCOUNT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_11_STA_0  
+#define APBDMACHAN_CHANNEL_11_STA_0                     _MK_ADDR_CONST(0x164)
+#define APBDMACHAN_CHANNEL_11_STA_0_SECURE                      0x0
+#define APBDMACHAN_CHANNEL_11_STA_0_WORD_COUNT                  0x1
+#define APBDMACHAN_CHANNEL_11_STA_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_STA_0_RESET_MASK                  _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_11_STA_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_STA_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_STA_0_READ_MASK                   _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_11_STA_0_WRITE_MASK                  _MK_MASK_CONST(0x40000000)
+// indicate DMA Channel Status activated or waiting
+#define APBDMACHAN_CHANNEL_11_STA_0_BSY_SHIFT                   _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_11_STA_0_BSY_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_11_STA_0_BSY_SHIFT)
+#define APBDMACHAN_CHANNEL_11_STA_0_BSY_RANGE                   31:31
+#define APBDMACHAN_CHANNEL_11_STA_0_BSY_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_11_STA_0_BSY_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_STA_0_BSY_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_11_STA_0_BSY_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_STA_0_BSY_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_STA_0_BSY_WAIT                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_11_STA_0_BSY_ACTIVE                  _MK_ENUM_CONST(1)
+
+//  Write '1' to clear the flag
+#define APBDMACHAN_CHANNEL_11_STA_0_ISE_EOC_SHIFT                       _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_11_STA_0_ISE_EOC_FIELD                       (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_11_STA_0_ISE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_11_STA_0_ISE_EOC_RANGE                       30:30
+#define APBDMACHAN_CHANNEL_11_STA_0_ISE_EOC_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_11_STA_0_ISE_EOC_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_STA_0_ISE_EOC_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_11_STA_0_ISE_EOC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_STA_0_ISE_EOC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_STA_0_ISE_EOC_NO_INTR                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_11_STA_0_ISE_EOC_INTR                        _MK_ENUM_CONST(1)
+
+// Holding Status of Processor 
+#define APBDMACHAN_CHANNEL_11_STA_0_HALT_SHIFT                  _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_11_STA_0_HALT_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_11_STA_0_HALT_SHIFT)
+#define APBDMACHAN_CHANNEL_11_STA_0_HALT_RANGE                  29:29
+#define APBDMACHAN_CHANNEL_11_STA_0_HALT_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_11_STA_0_HALT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_STA_0_HALT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_11_STA_0_HALT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_STA_0_HALT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_STA_0_HALT_NO_HALT                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_11_STA_0_HALT_HALT                   _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_11_STA_0_PING_PONG_STA_SHIFT                 _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_11_STA_0_PING_PONG_STA_FIELD                 (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_11_STA_0_PING_PONG_STA_SHIFT)
+#define APBDMACHAN_CHANNEL_11_STA_0_PING_PONG_STA_RANGE                 28:28
+#define APBDMACHAN_CHANNEL_11_STA_0_PING_PONG_STA_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_11_STA_0_PING_PONG_STA_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_STA_0_PING_PONG_STA_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_11_STA_0_PING_PONG_STA_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_STA_0_PING_PONG_STA_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_STA_0_PING_PONG_STA_PING_INTR_STA                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_11_STA_0_PING_PONG_STA_PONG_INTR_STA                 _MK_ENUM_CONST(1)
+
+// Current 32bit word cycles Flags set /cleared by HW
+#define APBDMACHAN_CHANNEL_11_STA_0_COUNT_SHIFT                 _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_11_STA_0_COUNT_FIELD                 (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_11_STA_0_COUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_11_STA_0_COUNT_RANGE                 15:2
+#define APBDMACHAN_CHANNEL_11_STA_0_COUNT_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_11_STA_0_COUNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_STA_0_COUNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_11_STA_0_COUNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_STA_0_COUNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Reserved address 360 [0x168] 
+
+// Reserved address 364 [0x16c] 
+
+// Register APBDMACHAN_CHANNEL_11_AHB_PTR_0  
+#define APBDMACHAN_CHANNEL_11_AHB_PTR_0                 _MK_ADDR_CONST(0x170)
+#define APBDMACHAN_CHANNEL_11_AHB_PTR_0_SECURE                  0x0
+#define APBDMACHAN_CHANNEL_11_AHB_PTR_0_WORD_COUNT                      0x1
+#define APBDMACHAN_CHANNEL_11_AHB_PTR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_AHB_PTR_0_RESET_MASK                      _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_11_AHB_PTR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_AHB_PTR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_AHB_PTR_0_READ_MASK                       _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_11_AHB_PTR_0_WRITE_MASK                      _MK_MASK_CONST(0xfffffffc)
+// APB-DMA Starting Address for AHB Bus: SW writes to  modify
+#define APBDMACHAN_CHANNEL_11_AHB_PTR_0_AHB_BASE_SHIFT                  _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_11_AHB_PTR_0_AHB_BASE_FIELD                  (_MK_MASK_CONST(0x3fffffff) << APBDMACHAN_CHANNEL_11_AHB_PTR_0_AHB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_11_AHB_PTR_0_AHB_BASE_RANGE                  31:2
+#define APBDMACHAN_CHANNEL_11_AHB_PTR_0_AHB_BASE_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_11_AHB_PTR_0_AHB_BASE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_AHB_PTR_0_AHB_BASE_DEFAULT_MASK                   _MK_MASK_CONST(0x3fffffff)
+#define APBDMACHAN_CHANNEL_11_AHB_PTR_0_AHB_BASE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_AHB_PTR_0_AHB_BASE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_11_AHB_SEQ_0  
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0                 _MK_ADDR_CONST(0x174)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_SECURE                  0x0
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_WORD_COUNT                      0x1
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_RESET_VAL                       _MK_MASK_CONST(0x20000000)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_RESET_MASK                      _MK_MASK_CONST(0xff070000)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_READ_MASK                       _MK_MASK_CONST(0xff070000)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_WRITE_MASK                      _MK_MASK_CONST(0xff070000)
+//  0 = send interrupt to COP
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_INTR_ENB_SHIFT                  _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_INTR_ENB_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_11_AHB_SEQ_0_INTR_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_INTR_ENB_RANGE                  31:31
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_INTR_ENB_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_INTR_ENB_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_INTR_ENB_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_INTR_ENB_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_INTR_ENB_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_INTR_ENB_CPU                    _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_INTR_ENB_COP                    _MK_ENUM_CONST(0)
+
+// AHB Bus Width 0 = 8 bit Bus (RSVD) 1 = 16 bit Bus (RSVD) 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD)4 = 128 bit Bus (RSVD)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT                     _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_BUS_WIDTH_FIELD                     (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_BUS_WIDTH_RANGE                     30:28
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_BUS_WIDTH_WOFFSET                   0x0
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT                   _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_8                       _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_16                      _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_32                      _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_64                      _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_128                     _MK_ENUM_CONST(4)
+
+// when enabled the data going  to AHB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT                     _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_DATA_SWAP_FIELD                     (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_DATA_SWAP_RANGE                     27:27
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_DATA_SWAP_WOFFSET                   0x0
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_DATA_SWAP_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_DATA_SWAP_ENABLE                    _MK_ENUM_CONST(1)
+
+// AHB Burst Size DMA Burst Length (encoded) 4 = 1 Word (1x32bits) 5 = 4 Words (4x32bits)else = 8 Words (8x32bits) default
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_BURST_SHIFT                 _MK_SHIFT_CONST(24)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_BURST_FIELD                 (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_BURST_SHIFT)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_BURST_RANGE                 26:24
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_BURST_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_BURST_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_BURST_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_BURST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_BURST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_BURST_DMA_BURST_1WORDS                      _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_BURST_DMA_BURST_4WORDS                      _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_BURST_DMA_BURST_8WORDS                      _MK_ENUM_CONST(6)
+
+// AHB Address Wrap: AHB Address wrap-around window 0=No Wrap (default) 5=Wrap on 512 word window 1=Wrap on 32 word window 6=Wrap on 1024 word window 2=Wrap on 64 word window 7=Wrap on 2048 word window 3=Wrap on 128 word window 4=Wrap on 256 word window
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_WRAP_SHIFT                      _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_WRAP_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_11_AHB_SEQ_0_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_WRAP_RANGE                      18:16
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_WRAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_WRAP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_WRAP_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_WRAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_WRAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_WRAP_NO_WRAP                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_WRAP_WRAP_0N_32WORDS                    _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_WRAP_WRAP_ON_64WORDS                    _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_WRAP_WRAP_ON_128WORDS                   _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_WRAP_WRAP_ON_256WORDS                   _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_WRAP_WRAP_ON_512WORDS                   _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_WRAP_WRAP_ON_1024WORDS                  _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_WRAP_WRAP_ON_2048WORDS                  _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_11_APB_PTR_0  
+#define APBDMACHAN_CHANNEL_11_APB_PTR_0                 _MK_ADDR_CONST(0x178)
+#define APBDMACHAN_CHANNEL_11_APB_PTR_0_SECURE                  0x0
+#define APBDMACHAN_CHANNEL_11_APB_PTR_0_WORD_COUNT                      0x1
+#define APBDMACHAN_CHANNEL_11_APB_PTR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_APB_PTR_0_RESET_MASK                      _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_11_APB_PTR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_APB_PTR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_APB_PTR_0_READ_MASK                       _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_11_APB_PTR_0_WRITE_MASK                      _MK_MASK_CONST(0xfffc)
+// APB-DMA Starting address for APB Bus: APB Base  address: Upper 16 bits are fixed at 0x7000:XXXX
+#define APBDMACHAN_CHANNEL_11_APB_PTR_0_APB_BASE_SHIFT                  _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_11_APB_PTR_0_APB_BASE_FIELD                  (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_11_APB_PTR_0_APB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_11_APB_PTR_0_APB_BASE_RANGE                  15:2
+#define APBDMACHAN_CHANNEL_11_APB_PTR_0_APB_BASE_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_11_APB_PTR_0_APB_BASE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_APB_PTR_0_APB_BASE_DEFAULT_MASK                   _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_11_APB_PTR_0_APB_BASE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_APB_PTR_0_APB_BASE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_11_APB_SEQ_0  
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0                 _MK_ADDR_CONST(0x17c)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_SECURE                  0x0
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_WORD_COUNT                      0x1
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_RESET_VAL                       _MK_MASK_CONST(0x20010000)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_RESET_MASK                      _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_READ_MASK                       _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_WRITE_MASK                      _MK_MASK_CONST(0x78070000)
+// 0 = 8 bit Bus 1 = 16 bit Bus 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD) 4 = 128 bit BUS (RSVD)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_BUS_WIDTH_SHIFT                     _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_BUS_WIDTH_FIELD                     (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_BUS_WIDTH_RANGE                     30:28
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_BUS_WIDTH_WOFFSET                   0x0
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT                   _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_8                       _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_16                      _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_32                      _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_64                      _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_128                     _MK_ENUM_CONST(4)
+
+// When enabled the data going  to APB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_DATA_SWAP_SHIFT                     _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_DATA_SWAP_FIELD                     (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_DATA_SWAP_RANGE                     27:27
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_DATA_SWAP_WOFFSET                   0x0
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_DATA_SWAP_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_DATA_SWAP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_DATA_SWAP_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_DATA_SWAP_ENABLE                    _MK_ENUM_CONST(1)
+
+//APB Address Wrap-around Window 0 = No Wrap 1 = Wrap on 1 Word Window (def) 2 = Wrap on 2 Word Window 3 = Wrap on 4 Word Window 4 = Wrap on 8 Word Window 5 = Wrap on 16 Word Window 6 = Wrap on 32 Word Window 7 = Wrap on 64 Word Window (rsvd)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_ADDR_WRAP_SHIFT                     _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_ADDR_WRAP_FIELD                     (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_ADDR_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_ADDR_WRAP_RANGE                     18:16
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_ADDR_WRAP_WOFFSET                   0x0
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_ADDR_WRAP_NO_WRAP                   _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_ADDR_WRAP_WRAP_0N_1WORDS                    _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_2WORDS                    _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_4WORDS                    _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_8WORDS                    _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_16WORDS                   _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_32WORDS                   _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_64WORDS                   _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_12_CSR_0  
+#define APBDMACHAN_CHANNEL_12_CSR_0                     _MK_ADDR_CONST(0x180)
+#define APBDMACHAN_CHANNEL_12_CSR_0_SECURE                      0x0
+#define APBDMACHAN_CHANNEL_12_CSR_0_WORD_COUNT                  0x1
+#define APBDMACHAN_CHANNEL_12_CSR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_RESET_MASK                  _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_12_CSR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_READ_MASK                   _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_12_CSR_0_WRITE_MASK                  _MK_MASK_CONST(0xfffffffc)
+// Enables DMA channel transfer 
+#define APBDMACHAN_CHANNEL_12_CSR_0_ENB_SHIFT                   _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_12_CSR_0_ENB_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_12_CSR_0_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_12_CSR_0_ENB_RANGE                   31:31
+#define APBDMACHAN_CHANNEL_12_CSR_0_ENB_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_12_CSR_0_ENB_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_ENB_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_12_CSR_0_ENB_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_ENB_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_ENB_DISABLE                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_ENB_ENABLE                  _MK_ENUM_CONST(1)
+
+// Interrupts when DMA Block Transfer Completes 
+#define APBDMACHAN_CHANNEL_12_CSR_0_IE_EOC_SHIFT                        _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_12_CSR_0_IE_EOC_FIELD                        (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_12_CSR_0_IE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_12_CSR_0_IE_EOC_RANGE                        30:30
+#define APBDMACHAN_CHANNEL_12_CSR_0_IE_EOC_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_12_CSR_0_IE_EOC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_IE_EOC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_12_CSR_0_IE_EOC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_IE_EOC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_IE_EOC_DISABLE                      _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_IE_EOC_ENABLE                       _MK_ENUM_CONST(1)
+
+// Holds this Processor until DMA Block Transfer Completes
+#define APBDMACHAN_CHANNEL_12_CSR_0_HOLD_SHIFT                  _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_12_CSR_0_HOLD_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_12_CSR_0_HOLD_SHIFT)
+#define APBDMACHAN_CHANNEL_12_CSR_0_HOLD_RANGE                  29:29
+#define APBDMACHAN_CHANNEL_12_CSR_0_HOLD_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_12_CSR_0_HOLD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_HOLD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_12_CSR_0_HOLD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_HOLD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_HOLD_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_HOLD_ENABLE                 _MK_ENUM_CONST(1)
+
+// DMA Transfer Direction 1 = AHB read to APB write 0 = APB read to AHB write
+#define APBDMACHAN_CHANNEL_12_CSR_0_DIR_SHIFT                   _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_12_CSR_0_DIR_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_12_CSR_0_DIR_SHIFT)
+#define APBDMACHAN_CHANNEL_12_CSR_0_DIR_RANGE                   28:28
+#define APBDMACHAN_CHANNEL_12_CSR_0_DIR_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_12_CSR_0_DIR_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_DIR_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_12_CSR_0_DIR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_DIR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_DIR_AHB_WRITE                       _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_DIR_AHB_READ                        _MK_ENUM_CONST(1)
+
+// Run Once or Run Multiple Mode (Allow Retriggering of this Channel) 1 = Run for One Block Transfer 0 = Run for Multiple Block Transfer
+#define APBDMACHAN_CHANNEL_12_CSR_0_ONCE_SHIFT                  _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_12_CSR_0_ONCE_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_12_CSR_0_ONCE_SHIFT)
+#define APBDMACHAN_CHANNEL_12_CSR_0_ONCE_RANGE                  27:27
+#define APBDMACHAN_CHANNEL_12_CSR_0_ONCE_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_12_CSR_0_ONCE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_ONCE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_12_CSR_0_ONCE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_ONCE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_ONCE_MULTIPLE_BLOCK                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_ONCE_SINGLE_BLOCK                   _MK_ENUM_CONST(1)
+
+// Enable on Non-Zero Value
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_SHIFT                      _MK_SHIFT_CONST(22)
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_FIELD                      (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_RANGE                      26:22
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_NA1                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_SMP24                      _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_SMP25                      _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_SMP26                      _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_SMP27                      _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_XRQ_A                      _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_XRQ_B                      _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_TMR1                       _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_TMR2                       _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_APB_0                      _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_APB_1                      _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_APB_2                      _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_APB_3                      _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_APB_4                      _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_APB_5                      _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_APB_6                      _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_APB_7                      _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_APB_8                      _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_APB_9                      _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_APB_10                     _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_APB_11                     _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_APB_12                     _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_APB_13                     _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_APB_14                     _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_APB_15                     _MK_ENUM_CONST(24)
+
+// Flow Control Enable (Synchronize Burst Transfers) 1 = Link to DRQ source 0 = Independent of DRQ request
+#define APBDMACHAN_CHANNEL_12_CSR_0_FLOW_SHIFT                  _MK_SHIFT_CONST(21)
+#define APBDMACHAN_CHANNEL_12_CSR_0_FLOW_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_12_CSR_0_FLOW_SHIFT)
+#define APBDMACHAN_CHANNEL_12_CSR_0_FLOW_RANGE                  21:21
+#define APBDMACHAN_CHANNEL_12_CSR_0_FLOW_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_12_CSR_0_FLOW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_FLOW_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_12_CSR_0_FLOW_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_FLOW_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_FLOW_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_FLOW_ENABLE                 _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_SHIFT                       _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_FIELD                       (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_RANGE                       20:16
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_CNTR_REQ                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_I2S_2                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_I2S_1                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_SPD_I                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_UI_I                        _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_MIPI                        _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_I2S2_2                      _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_I2S2_1                      _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_UART_A                      _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_UART_B                      _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_UART_C                      _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_SPI                 _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_AC97                        _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_ACModem                     _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_SL4B                        _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_SL2B1                       _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_SL2B2                       _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_SL2B3                       _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_SL2B4                       _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_UART_D                      _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_UART_E                      _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_I2C                 _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_I2C2                        _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_I2C3                        _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_DVC_I2C                     _MK_ENUM_CONST(24)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_OWR                 _MK_ENUM_CONST(25)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_NA26                        _MK_ENUM_CONST(26)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_NA27                        _MK_ENUM_CONST(27)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_NA28                        _MK_ENUM_CONST(28)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_NA29                        _MK_ENUM_CONST(29)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_NA30                        _MK_ENUM_CONST(30)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_NA31                        _MK_ENUM_CONST(31)
+
+// Number of 32bit word cycles
+#define APBDMACHAN_CHANNEL_12_CSR_0_WCOUNT_SHIFT                        _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_12_CSR_0_WCOUNT_FIELD                        (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_12_CSR_0_WCOUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_12_CSR_0_WCOUNT_RANGE                        15:2
+#define APBDMACHAN_CHANNEL_12_CSR_0_WCOUNT_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_12_CSR_0_WCOUNT_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_WCOUNT_DEFAULT_MASK                 _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_12_CSR_0_WCOUNT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_WCOUNT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_12_STA_0  
+#define APBDMACHAN_CHANNEL_12_STA_0                     _MK_ADDR_CONST(0x184)
+#define APBDMACHAN_CHANNEL_12_STA_0_SECURE                      0x0
+#define APBDMACHAN_CHANNEL_12_STA_0_WORD_COUNT                  0x1
+#define APBDMACHAN_CHANNEL_12_STA_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_STA_0_RESET_MASK                  _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_12_STA_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_STA_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_STA_0_READ_MASK                   _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_12_STA_0_WRITE_MASK                  _MK_MASK_CONST(0x40000000)
+// indicate DMA Channel Status activated or not
+#define APBDMACHAN_CHANNEL_12_STA_0_BSY_SHIFT                   _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_12_STA_0_BSY_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_12_STA_0_BSY_SHIFT)
+#define APBDMACHAN_CHANNEL_12_STA_0_BSY_RANGE                   31:31
+#define APBDMACHAN_CHANNEL_12_STA_0_BSY_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_12_STA_0_BSY_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_STA_0_BSY_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_12_STA_0_BSY_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_STA_0_BSY_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_STA_0_BSY_WAIT                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_12_STA_0_BSY_ACTIVE                  _MK_ENUM_CONST(1)
+
+//  Write '1' to clear the flag
+#define APBDMACHAN_CHANNEL_12_STA_0_ISE_EOC_SHIFT                       _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_12_STA_0_ISE_EOC_FIELD                       (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_12_STA_0_ISE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_12_STA_0_ISE_EOC_RANGE                       30:30
+#define APBDMACHAN_CHANNEL_12_STA_0_ISE_EOC_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_12_STA_0_ISE_EOC_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_STA_0_ISE_EOC_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_12_STA_0_ISE_EOC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_STA_0_ISE_EOC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_STA_0_ISE_EOC_NO_INTR                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_12_STA_0_ISE_EOC_INTR                        _MK_ENUM_CONST(1)
+
+// Holding Status of Processor
+#define APBDMACHAN_CHANNEL_12_STA_0_HALT_SHIFT                  _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_12_STA_0_HALT_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_12_STA_0_HALT_SHIFT)
+#define APBDMACHAN_CHANNEL_12_STA_0_HALT_RANGE                  29:29
+#define APBDMACHAN_CHANNEL_12_STA_0_HALT_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_12_STA_0_HALT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_STA_0_HALT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_12_STA_0_HALT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_STA_0_HALT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_STA_0_HALT_NO_HALT                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_12_STA_0_HALT_HALT                   _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_12_STA_0_PING_PONG_STA_SHIFT                 _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_12_STA_0_PING_PONG_STA_FIELD                 (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_12_STA_0_PING_PONG_STA_SHIFT)
+#define APBDMACHAN_CHANNEL_12_STA_0_PING_PONG_STA_RANGE                 28:28
+#define APBDMACHAN_CHANNEL_12_STA_0_PING_PONG_STA_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_12_STA_0_PING_PONG_STA_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_STA_0_PING_PONG_STA_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_12_STA_0_PING_PONG_STA_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_STA_0_PING_PONG_STA_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_STA_0_PING_PONG_STA_PING_INTR_STA                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_12_STA_0_PING_PONG_STA_PONG_INTR_STA                 _MK_ENUM_CONST(1)
+
+// Current 32bit word cycles Flags set /cleared by HW
+#define APBDMACHAN_CHANNEL_12_STA_0_COUNT_SHIFT                 _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_12_STA_0_COUNT_FIELD                 (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_12_STA_0_COUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_12_STA_0_COUNT_RANGE                 15:2
+#define APBDMACHAN_CHANNEL_12_STA_0_COUNT_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_12_STA_0_COUNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_STA_0_COUNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_12_STA_0_COUNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_STA_0_COUNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Reserved address 392 [0x188] 
+
+// Reserved address 396 [0x18c] 
+
+// Register APBDMACHAN_CHANNEL_12_AHB_PTR_0  
+#define APBDMACHAN_CHANNEL_12_AHB_PTR_0                 _MK_ADDR_CONST(0x190)
+#define APBDMACHAN_CHANNEL_12_AHB_PTR_0_SECURE                  0x0
+#define APBDMACHAN_CHANNEL_12_AHB_PTR_0_WORD_COUNT                      0x1
+#define APBDMACHAN_CHANNEL_12_AHB_PTR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_AHB_PTR_0_RESET_MASK                      _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_12_AHB_PTR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_AHB_PTR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_AHB_PTR_0_READ_MASK                       _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_12_AHB_PTR_0_WRITE_MASK                      _MK_MASK_CONST(0xfffffffc)
+// APB-DMA Starting Address for AHB Bus: SW writes to  modify
+#define APBDMACHAN_CHANNEL_12_AHB_PTR_0_AHB_BASE_SHIFT                  _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_12_AHB_PTR_0_AHB_BASE_FIELD                  (_MK_MASK_CONST(0x3fffffff) << APBDMACHAN_CHANNEL_12_AHB_PTR_0_AHB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_12_AHB_PTR_0_AHB_BASE_RANGE                  31:2
+#define APBDMACHAN_CHANNEL_12_AHB_PTR_0_AHB_BASE_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_12_AHB_PTR_0_AHB_BASE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_AHB_PTR_0_AHB_BASE_DEFAULT_MASK                   _MK_MASK_CONST(0x3fffffff)
+#define APBDMACHAN_CHANNEL_12_AHB_PTR_0_AHB_BASE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_AHB_PTR_0_AHB_BASE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_12_AHB_SEQ_0  
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0                 _MK_ADDR_CONST(0x194)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_SECURE                  0x0
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_WORD_COUNT                      0x1
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_RESET_VAL                       _MK_MASK_CONST(0x20000000)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_RESET_MASK                      _MK_MASK_CONST(0xff0f0000)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_READ_MASK                       _MK_MASK_CONST(0xff0f0000)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_WRITE_MASK                      _MK_MASK_CONST(0xff0f0000)
+//  0 = send interrupt to COP
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_INTR_ENB_SHIFT                  _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_INTR_ENB_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_12_AHB_SEQ_0_INTR_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_INTR_ENB_RANGE                  31:31
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_INTR_ENB_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_INTR_ENB_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_INTR_ENB_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_INTR_ENB_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_INTR_ENB_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_INTR_ENB_CPU                    _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_INTR_ENB_COP                    _MK_ENUM_CONST(0)
+
+// AHB Bus Width 0 = 8 bit Bus (RSVD) 1 = 16 bit Bus (RSVD) 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD)4 = 128 bit Bus (RSVD)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT                     _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_BUS_WIDTH_FIELD                     (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_BUS_WIDTH_RANGE                     30:28
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_BUS_WIDTH_WOFFSET                   0x0
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT                   _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_8                       _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_16                      _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_32                      _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_64                      _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_128                     _MK_ENUM_CONST(4)
+
+// When enabled the data going  to AHB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT                     _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_DATA_SWAP_FIELD                     (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_DATA_SWAP_RANGE                     27:27
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_DATA_SWAP_WOFFSET                   0x0
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_DATA_SWAP_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_DATA_SWAP_ENABLE                    _MK_ENUM_CONST(1)
+
+// AHB Burst Size DMA Burst Length (encoded) 4 = 1 Word (1x32bits) 5 = 4 Words (4x32bits)else = 8 Words (8x32bits) default
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_BURST_SHIFT                 _MK_SHIFT_CONST(24)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_BURST_FIELD                 (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_BURST_SHIFT)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_BURST_RANGE                 26:24
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_BURST_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_BURST_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_BURST_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_BURST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_BURST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_BURST_DMA_BURST_1WORDS                      _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_BURST_DMA_BURST_4WORDS                      _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_BURST_DMA_BURST_8WORDS                      _MK_ENUM_CONST(6)
+
+// 2X Double Buffering Mode (For Run-Multiple Mode with No Wrap Operations) 1 = Reload Base Address for 2X blocks (reload every other time) 0 = Reload Base Address for 1X blocks  (def) (reload each time)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_DBL_BUF_SHIFT                   _MK_SHIFT_CONST(19)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_DBL_BUF_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_12_AHB_SEQ_0_DBL_BUF_SHIFT)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_DBL_BUF_RANGE                   19:19
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_DBL_BUF_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_DBL_BUF_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_DBL_BUF_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_DBL_BUF_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_DBL_BUF_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_DBL_BUF_RELOAD_FOR_1X_BLOCKS                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_DBL_BUF_RELOAD_FOR_2X_BLOCKS                    _MK_ENUM_CONST(1)
+
+// AHB Address Wrap: AHB Address wrap-around window 0=No Wrap (default) 5=Wrap on 512 word window 1=Wrap on 32 word window 6=Wrap on 1024 word window 2=Wrap on 64 word window 7=Wrap on 2048 word window 3=Wrap on 128 word window 4=Wrap on 256 word window
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_WRAP_SHIFT                      _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_WRAP_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_12_AHB_SEQ_0_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_WRAP_RANGE                      18:16
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_WRAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_WRAP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_WRAP_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_WRAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_WRAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_WRAP_NO_WRAP                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_WRAP_WRAP_0N_32WORDS                    _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_WRAP_WRAP_ON_64WORDS                    _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_WRAP_WRAP_ON_128WORDS                   _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_WRAP_WRAP_ON_256WORDS                   _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_WRAP_WRAP_ON_512WORDS                   _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_WRAP_WRAP_ON_1024WORDS                  _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_WRAP_WRAP_ON_2048WORDS                  _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_12_APB_PTR_0  
+#define APBDMACHAN_CHANNEL_12_APB_PTR_0                 _MK_ADDR_CONST(0x198)
+#define APBDMACHAN_CHANNEL_12_APB_PTR_0_SECURE                  0x0
+#define APBDMACHAN_CHANNEL_12_APB_PTR_0_WORD_COUNT                      0x1
+#define APBDMACHAN_CHANNEL_12_APB_PTR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_APB_PTR_0_RESET_MASK                      _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_12_APB_PTR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_APB_PTR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_APB_PTR_0_READ_MASK                       _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_12_APB_PTR_0_WRITE_MASK                      _MK_MASK_CONST(0xfffc)
+// APB-DMA Starting address for APB Bus: APB Base address:Upper 16 bits are fixed at 0x7000:XXXX
+#define APBDMACHAN_CHANNEL_12_APB_PTR_0_APB_BASE_SHIFT                  _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_12_APB_PTR_0_APB_BASE_FIELD                  (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_12_APB_PTR_0_APB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_12_APB_PTR_0_APB_BASE_RANGE                  15:2
+#define APBDMACHAN_CHANNEL_12_APB_PTR_0_APB_BASE_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_12_APB_PTR_0_APB_BASE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_APB_PTR_0_APB_BASE_DEFAULT_MASK                   _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_12_APB_PTR_0_APB_BASE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_APB_PTR_0_APB_BASE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_12_APB_SEQ_0  
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0                 _MK_ADDR_CONST(0x19c)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_SECURE                  0x0
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_WORD_COUNT                      0x1
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_RESET_VAL                       _MK_MASK_CONST(0x20010000)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_RESET_MASK                      _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_READ_MASK                       _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_WRITE_MASK                      _MK_MASK_CONST(0x78070000)
+// 0 = 8 bit Bus 1 = 16 bit Bus 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD) 4 = 128 bit BUS (RSVD)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_BUS_WIDTH_SHIFT                     _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_BUS_WIDTH_FIELD                     (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_BUS_WIDTH_RANGE                     30:28
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_BUS_WIDTH_WOFFSET                   0x0
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT                   _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_8                       _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_16                      _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_32                      _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_64                      _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_128                     _MK_ENUM_CONST(4)
+
+// When enabled the data going  to APB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_DATA_SWAP_SHIFT                     _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_DATA_SWAP_FIELD                     (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_DATA_SWAP_RANGE                     27:27
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_DATA_SWAP_WOFFSET                   0x0
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_DATA_SWAP_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_DATA_SWAP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_DATA_SWAP_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_DATA_SWAP_ENABLE                    _MK_ENUM_CONST(1)
+
+//APB Address Wrap-around Window 0 = No Wrap 1 = Wrap on 1 Word Window (def) 2 = Wrap on 2 Word Window 3 = Wrap on 4 Word Window 4 = Wrap on 8 Word Window 5 = Wrap on 16 Word Window 6 = Wrap on 32 Word Window 7 = Wrap on 64 Word Window (rsvd)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_ADDR_WRAP_SHIFT                     _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_ADDR_WRAP_FIELD                     (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_ADDR_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_ADDR_WRAP_RANGE                     18:16
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_ADDR_WRAP_WOFFSET                   0x0
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_ADDR_WRAP_NO_WRAP                   _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_ADDR_WRAP_WRAP_0N_1WORDS                    _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_2WORDS                    _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_4WORDS                    _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_8WORDS                    _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_16WORDS                   _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_32WORDS                   _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_64WORDS                   _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_13_CSR_0  
+#define APBDMACHAN_CHANNEL_13_CSR_0                     _MK_ADDR_CONST(0x1a0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_SECURE                      0x0
+#define APBDMACHAN_CHANNEL_13_CSR_0_WORD_COUNT                  0x1
+#define APBDMACHAN_CHANNEL_13_CSR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_RESET_MASK                  _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_13_CSR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_READ_MASK                   _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_13_CSR_0_WRITE_MASK                  _MK_MASK_CONST(0xfffffffc)
+// Enables DMA channel transfer 
+#define APBDMACHAN_CHANNEL_13_CSR_0_ENB_SHIFT                   _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_13_CSR_0_ENB_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_13_CSR_0_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_13_CSR_0_ENB_RANGE                   31:31
+#define APBDMACHAN_CHANNEL_13_CSR_0_ENB_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_13_CSR_0_ENB_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_ENB_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_13_CSR_0_ENB_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_ENB_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_ENB_DISABLE                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_ENB_ENABLE                  _MK_ENUM_CONST(1)
+
+// Interrupts when DMA Block Transfer Completes 
+#define APBDMACHAN_CHANNEL_13_CSR_0_IE_EOC_SHIFT                        _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_13_CSR_0_IE_EOC_FIELD                        (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_13_CSR_0_IE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_13_CSR_0_IE_EOC_RANGE                        30:30
+#define APBDMACHAN_CHANNEL_13_CSR_0_IE_EOC_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_13_CSR_0_IE_EOC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_IE_EOC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_13_CSR_0_IE_EOC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_IE_EOC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_IE_EOC_DISABLE                      _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_IE_EOC_ENABLE                       _MK_ENUM_CONST(1)
+
+// Holds this Processor until DMA Block Transfer Completes 
+#define APBDMACHAN_CHANNEL_13_CSR_0_HOLD_SHIFT                  _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_13_CSR_0_HOLD_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_13_CSR_0_HOLD_SHIFT)
+#define APBDMACHAN_CHANNEL_13_CSR_0_HOLD_RANGE                  29:29
+#define APBDMACHAN_CHANNEL_13_CSR_0_HOLD_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_13_CSR_0_HOLD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_HOLD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_13_CSR_0_HOLD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_HOLD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_HOLD_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_HOLD_ENABLE                 _MK_ENUM_CONST(1)
+
+// DMA Transfer Direction 1 = AHB read to APB write 0 = APB read to AHB write
+#define APBDMACHAN_CHANNEL_13_CSR_0_DIR_SHIFT                   _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_13_CSR_0_DIR_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_13_CSR_0_DIR_SHIFT)
+#define APBDMACHAN_CHANNEL_13_CSR_0_DIR_RANGE                   28:28
+#define APBDMACHAN_CHANNEL_13_CSR_0_DIR_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_13_CSR_0_DIR_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_DIR_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_13_CSR_0_DIR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_DIR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_DIR_AHB_WRITE                       _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_DIR_AHB_READ                        _MK_ENUM_CONST(1)
+
+// Run Once or Run Multiple Mode (Allow Retriggering of this Channel) 1 = Run for One Block Transfer 0 = Run for Multiple Block Transfer
+#define APBDMACHAN_CHANNEL_13_CSR_0_ONCE_SHIFT                  _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_13_CSR_0_ONCE_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_13_CSR_0_ONCE_SHIFT)
+#define APBDMACHAN_CHANNEL_13_CSR_0_ONCE_RANGE                  27:27
+#define APBDMACHAN_CHANNEL_13_CSR_0_ONCE_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_13_CSR_0_ONCE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_ONCE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_13_CSR_0_ONCE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_ONCE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_ONCE_MULTIPLE_BLOCK                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_ONCE_SINGLE_BLOCK                   _MK_ENUM_CONST(1)
+
+// Enable on Non-Zero Value
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_SHIFT                      _MK_SHIFT_CONST(22)
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_FIELD                      (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_RANGE                      26:22
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_NA1                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_SMP24                      _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_SMP25                      _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_SMP26                      _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_SMP27                      _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_XRQ_A                      _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_XRQ_B                      _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_TMR1                       _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_TMR2                       _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_APB_0                      _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_APB_1                      _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_APB_2                      _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_APB_3                      _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_APB_4                      _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_APB_5                      _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_APB_6                      _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_APB_7                      _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_APB_8                      _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_APB_9                      _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_APB_10                     _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_APB_11                     _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_APB_12                     _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_APB_13                     _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_APB_14                     _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_APB_15                     _MK_ENUM_CONST(24)
+
+// Flow Control Enable (Synchronize Burst Transfers) 1 = Link to DRQ source 0 = Independent of DRQ request
+#define APBDMACHAN_CHANNEL_13_CSR_0_FLOW_SHIFT                  _MK_SHIFT_CONST(21)
+#define APBDMACHAN_CHANNEL_13_CSR_0_FLOW_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_13_CSR_0_FLOW_SHIFT)
+#define APBDMACHAN_CHANNEL_13_CSR_0_FLOW_RANGE                  21:21
+#define APBDMACHAN_CHANNEL_13_CSR_0_FLOW_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_13_CSR_0_FLOW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_FLOW_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_13_CSR_0_FLOW_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_FLOW_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_FLOW_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_FLOW_ENABLE                 _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_SHIFT                       _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_FIELD                       (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_RANGE                       20:16
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_CNTR_REQ                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_I2S_2                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_I2S_1                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_SPD_I                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_UI_I                        _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_MIPI                        _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_I2S2_2                      _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_I2S2_1                      _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_UART_A                      _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_UART_B                      _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_UART_C                      _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_SPI                 _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_AC97                        _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_ACModem                     _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_SL4B                        _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_SL2B1                       _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_SL2B2                       _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_SL2B3                       _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_SL2B4                       _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_UART_D                      _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_UART_E                      _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_I2C                 _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_I2C2                        _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_I2C3                        _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_DVC_I2C                     _MK_ENUM_CONST(24)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_OWR                 _MK_ENUM_CONST(25)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_NA26                        _MK_ENUM_CONST(26)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_NA27                        _MK_ENUM_CONST(27)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_NA28                        _MK_ENUM_CONST(28)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_NA29                        _MK_ENUM_CONST(29)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_NA30                        _MK_ENUM_CONST(30)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_NA31                        _MK_ENUM_CONST(31)
+
+// Number of 32bit word cycles
+#define APBDMACHAN_CHANNEL_13_CSR_0_WCOUNT_SHIFT                        _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_13_CSR_0_WCOUNT_FIELD                        (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_13_CSR_0_WCOUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_13_CSR_0_WCOUNT_RANGE                        15:2
+#define APBDMACHAN_CHANNEL_13_CSR_0_WCOUNT_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_13_CSR_0_WCOUNT_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_WCOUNT_DEFAULT_MASK                 _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_13_CSR_0_WCOUNT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_WCOUNT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_13_STA_0  
+#define APBDMACHAN_CHANNEL_13_STA_0                     _MK_ADDR_CONST(0x1a4)
+#define APBDMACHAN_CHANNEL_13_STA_0_SECURE                      0x0
+#define APBDMACHAN_CHANNEL_13_STA_0_WORD_COUNT                  0x1
+#define APBDMACHAN_CHANNEL_13_STA_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_STA_0_RESET_MASK                  _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_13_STA_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_STA_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_STA_0_READ_MASK                   _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_13_STA_0_WRITE_MASK                  _MK_MASK_CONST(0x40000000)
+// indicate DMA Channel Status activated or not 
+#define APBDMACHAN_CHANNEL_13_STA_0_BSY_SHIFT                   _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_13_STA_0_BSY_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_13_STA_0_BSY_SHIFT)
+#define APBDMACHAN_CHANNEL_13_STA_0_BSY_RANGE                   31:31
+#define APBDMACHAN_CHANNEL_13_STA_0_BSY_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_13_STA_0_BSY_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_STA_0_BSY_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_13_STA_0_BSY_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_STA_0_BSY_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_STA_0_BSY_WAIT                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_13_STA_0_BSY_ACTIVE                  _MK_ENUM_CONST(1)
+
+//  Write '1' to clear the flag
+#define APBDMACHAN_CHANNEL_13_STA_0_ISE_EOC_SHIFT                       _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_13_STA_0_ISE_EOC_FIELD                       (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_13_STA_0_ISE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_13_STA_0_ISE_EOC_RANGE                       30:30
+#define APBDMACHAN_CHANNEL_13_STA_0_ISE_EOC_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_13_STA_0_ISE_EOC_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_STA_0_ISE_EOC_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_13_STA_0_ISE_EOC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_STA_0_ISE_EOC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_STA_0_ISE_EOC_NO_INTR                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_13_STA_0_ISE_EOC_INTR                        _MK_ENUM_CONST(1)
+
+// Holding Status of Processor
+#define APBDMACHAN_CHANNEL_13_STA_0_HALT_SHIFT                  _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_13_STA_0_HALT_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_13_STA_0_HALT_SHIFT)
+#define APBDMACHAN_CHANNEL_13_STA_0_HALT_RANGE                  29:29
+#define APBDMACHAN_CHANNEL_13_STA_0_HALT_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_13_STA_0_HALT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_STA_0_HALT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_13_STA_0_HALT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_STA_0_HALT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_STA_0_HALT_NO_HALT                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_13_STA_0_HALT_HALT                   _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_13_STA_0_PING_PONG_STA_SHIFT                 _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_13_STA_0_PING_PONG_STA_FIELD                 (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_13_STA_0_PING_PONG_STA_SHIFT)
+#define APBDMACHAN_CHANNEL_13_STA_0_PING_PONG_STA_RANGE                 28:28
+#define APBDMACHAN_CHANNEL_13_STA_0_PING_PONG_STA_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_13_STA_0_PING_PONG_STA_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_STA_0_PING_PONG_STA_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_13_STA_0_PING_PONG_STA_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_STA_0_PING_PONG_STA_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_STA_0_PING_PONG_STA_PING_INTR_STA                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_13_STA_0_PING_PONG_STA_PONG_INTR_STA                 _MK_ENUM_CONST(1)
+
+// Current 32bit word cycles Flags set /cleared by HW
+#define APBDMACHAN_CHANNEL_13_STA_0_COUNT_SHIFT                 _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_13_STA_0_COUNT_FIELD                 (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_13_STA_0_COUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_13_STA_0_COUNT_RANGE                 15:2
+#define APBDMACHAN_CHANNEL_13_STA_0_COUNT_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_13_STA_0_COUNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_STA_0_COUNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_13_STA_0_COUNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_STA_0_COUNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Reserved address 424 [0x1a8] 
+
+// Reserved address 428 [0x1ac] 
+
+// Register APBDMACHAN_CHANNEL_13_AHB_PTR_0  
+#define APBDMACHAN_CHANNEL_13_AHB_PTR_0                 _MK_ADDR_CONST(0x1b0)
+#define APBDMACHAN_CHANNEL_13_AHB_PTR_0_SECURE                  0x0
+#define APBDMACHAN_CHANNEL_13_AHB_PTR_0_WORD_COUNT                      0x1
+#define APBDMACHAN_CHANNEL_13_AHB_PTR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_AHB_PTR_0_RESET_MASK                      _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_13_AHB_PTR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_AHB_PTR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_AHB_PTR_0_READ_MASK                       _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_13_AHB_PTR_0_WRITE_MASK                      _MK_MASK_CONST(0xfffffffc)
+// APB-DMA Starting Address for AHB Bus: SW writes to  modify
+#define APBDMACHAN_CHANNEL_13_AHB_PTR_0_AHB_BASE_SHIFT                  _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_13_AHB_PTR_0_AHB_BASE_FIELD                  (_MK_MASK_CONST(0x3fffffff) << APBDMACHAN_CHANNEL_13_AHB_PTR_0_AHB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_13_AHB_PTR_0_AHB_BASE_RANGE                  31:2
+#define APBDMACHAN_CHANNEL_13_AHB_PTR_0_AHB_BASE_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_13_AHB_PTR_0_AHB_BASE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_AHB_PTR_0_AHB_BASE_DEFAULT_MASK                   _MK_MASK_CONST(0x3fffffff)
+#define APBDMACHAN_CHANNEL_13_AHB_PTR_0_AHB_BASE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_AHB_PTR_0_AHB_BASE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_13_AHB_SEQ_0  
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0                 _MK_ADDR_CONST(0x1b4)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_SECURE                  0x0
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_WORD_COUNT                      0x1
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_RESET_VAL                       _MK_MASK_CONST(0x20000000)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_RESET_MASK                      _MK_MASK_CONST(0xff0f0000)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_READ_MASK                       _MK_MASK_CONST(0xff0f0000)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_WRITE_MASK                      _MK_MASK_CONST(0xff0f0000)
+//  0 = send interrupt to COP
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_INTR_ENB_SHIFT                  _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_INTR_ENB_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_13_AHB_SEQ_0_INTR_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_INTR_ENB_RANGE                  31:31
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_INTR_ENB_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_INTR_ENB_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_INTR_ENB_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_INTR_ENB_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_INTR_ENB_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_INTR_ENB_CPU                    _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_INTR_ENB_COP                    _MK_ENUM_CONST(0)
+
+// AHB Bus Width 0 = 8 bit Bus (RSVD) 1 = 16 bit Bus (RSVD) 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD)4 = 128 bit Bus (RSVD)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT                     _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_BUS_WIDTH_FIELD                     (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_BUS_WIDTH_RANGE                     30:28
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_BUS_WIDTH_WOFFSET                   0x0
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT                   _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_8                       _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_16                      _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_32                      _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_64                      _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_128                     _MK_ENUM_CONST(4)
+
+// When enabled the data going  to AHB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT                     _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_DATA_SWAP_FIELD                     (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_DATA_SWAP_RANGE                     27:27
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_DATA_SWAP_WOFFSET                   0x0
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_DATA_SWAP_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_DATA_SWAP_ENABLE                    _MK_ENUM_CONST(1)
+
+// AHB Burst Size DMA Burst Length (encoded) 4 = 1 Word (1x32bits) 5 = 4 Words (4x32bits)else = 8 Words (8x32bits) default
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_BURST_SHIFT                 _MK_SHIFT_CONST(24)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_BURST_FIELD                 (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_BURST_SHIFT)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_BURST_RANGE                 26:24
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_BURST_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_BURST_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_BURST_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_BURST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_BURST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_BURST_DMA_BURST_1WORDS                      _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_BURST_DMA_BURST_4WORDS                      _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_BURST_DMA_BURST_8WORDS                      _MK_ENUM_CONST(6)
+
+// 2X Double Buffering Mode (For Run-Multiple Mode with No Wrap Operations) 1 = Reload Base Address for 2X blocks (reload every other time) 0 = Reload Base Address for 1X blocks  (def) (reload each time)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_DBL_BUF_SHIFT                   _MK_SHIFT_CONST(19)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_DBL_BUF_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_13_AHB_SEQ_0_DBL_BUF_SHIFT)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_DBL_BUF_RANGE                   19:19
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_DBL_BUF_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_DBL_BUF_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_DBL_BUF_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_DBL_BUF_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_DBL_BUF_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_DBL_BUF_RELOAD_FOR_1X_BLOCKS                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_DBL_BUF_RELOAD_FOR_2X_BLOCKS                    _MK_ENUM_CONST(1)
+
+// AHB Address Wrap: AHB Address wrap-around window 0=No Wrap (default) 5=Wrap on 512 word window 1=Wrap on 32 word window 6=Wrap on 1024 word window 2=Wrap on 64 word window 7=Wrap on 2048 word window 3=Wrap on 128 word window 4=Wrap on 256 word window
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_WRAP_SHIFT                      _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_WRAP_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_13_AHB_SEQ_0_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_WRAP_RANGE                      18:16
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_WRAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_WRAP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_WRAP_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_WRAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_WRAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_WRAP_NO_WRAP                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_WRAP_WRAP_0N_32WORDS                    _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_WRAP_WRAP_ON_64WORDS                    _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_WRAP_WRAP_ON_128WORDS                   _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_WRAP_WRAP_ON_256WORDS                   _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_WRAP_WRAP_ON_512WORDS                   _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_WRAP_WRAP_ON_1024WORDS                  _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_WRAP_WRAP_ON_2048WORDS                  _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_13_APB_PTR_0  
+#define APBDMACHAN_CHANNEL_13_APB_PTR_0                 _MK_ADDR_CONST(0x1b8)
+#define APBDMACHAN_CHANNEL_13_APB_PTR_0_SECURE                  0x0
+#define APBDMACHAN_CHANNEL_13_APB_PTR_0_WORD_COUNT                      0x1
+#define APBDMACHAN_CHANNEL_13_APB_PTR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_APB_PTR_0_RESET_MASK                      _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_13_APB_PTR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_APB_PTR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_APB_PTR_0_READ_MASK                       _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_13_APB_PTR_0_WRITE_MASK                      _MK_MASK_CONST(0xfffc)
+// APB-DMA Starting address for APB Bus: APB Base address:Upper 16 bits are fixed at 0x7000:XXXX
+#define APBDMACHAN_CHANNEL_13_APB_PTR_0_APB_BASE_SHIFT                  _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_13_APB_PTR_0_APB_BASE_FIELD                  (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_13_APB_PTR_0_APB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_13_APB_PTR_0_APB_BASE_RANGE                  15:2
+#define APBDMACHAN_CHANNEL_13_APB_PTR_0_APB_BASE_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_13_APB_PTR_0_APB_BASE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_APB_PTR_0_APB_BASE_DEFAULT_MASK                   _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_13_APB_PTR_0_APB_BASE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_APB_PTR_0_APB_BASE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_13_APB_SEQ_0  
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0                 _MK_ADDR_CONST(0x1bc)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_SECURE                  0x0
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_WORD_COUNT                      0x1
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_RESET_VAL                       _MK_MASK_CONST(0x20010000)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_RESET_MASK                      _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_READ_MASK                       _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_WRITE_MASK                      _MK_MASK_CONST(0x78070000)
+// 0 = 8 bit Bus 1 = 16 bit Bus 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD) 4 = 128 bit BUS (RSVD)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_BUS_WIDTH_SHIFT                     _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_BUS_WIDTH_FIELD                     (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_BUS_WIDTH_RANGE                     30:28
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_BUS_WIDTH_WOFFSET                   0x0
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT                   _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_8                       _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_16                      _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_32                      _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_64                      _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_128                     _MK_ENUM_CONST(4)
+
+// When enabled the data going  to APB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_DATA_SWAP_SHIFT                     _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_DATA_SWAP_FIELD                     (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_DATA_SWAP_RANGE                     27:27
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_DATA_SWAP_WOFFSET                   0x0
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_DATA_SWAP_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_DATA_SWAP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_DATA_SWAP_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_DATA_SWAP_ENABLE                    _MK_ENUM_CONST(1)
+
+//APB Address Wrap-around Window 0 = No Wrap 1 = Wrap on 1 Word Window (def) 2 = Wrap on 2 Word Window 3 = Wrap on 4 Word Window 4 = Wrap on 8 Word Window 5 = Wrap on 16 Word Window 6 = Wrap on 32 Word Window 7 = Wrap on 64 Word Window (rsvd)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_ADDR_WRAP_SHIFT                     _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_ADDR_WRAP_FIELD                     (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_ADDR_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_ADDR_WRAP_RANGE                     18:16
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_ADDR_WRAP_WOFFSET                   0x0
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_ADDR_WRAP_NO_WRAP                   _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_ADDR_WRAP_WRAP_0N_1WORDS                    _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_2WORDS                    _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_4WORDS                    _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_8WORDS                    _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_16WORDS                   _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_32WORDS                   _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_64WORDS                   _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_14_CSR_0  
+#define APBDMACHAN_CHANNEL_14_CSR_0                     _MK_ADDR_CONST(0x1c0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_SECURE                      0x0
+#define APBDMACHAN_CHANNEL_14_CSR_0_WORD_COUNT                  0x1
+#define APBDMACHAN_CHANNEL_14_CSR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_RESET_MASK                  _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_14_CSR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_READ_MASK                   _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_14_CSR_0_WRITE_MASK                  _MK_MASK_CONST(0xfffffffc)
+// Enables DMA channel transfer 
+#define APBDMACHAN_CHANNEL_14_CSR_0_ENB_SHIFT                   _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_14_CSR_0_ENB_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_14_CSR_0_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_14_CSR_0_ENB_RANGE                   31:31
+#define APBDMACHAN_CHANNEL_14_CSR_0_ENB_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_14_CSR_0_ENB_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_ENB_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_14_CSR_0_ENB_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_ENB_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_ENB_DISABLE                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_ENB_ENABLE                  _MK_ENUM_CONST(1)
+
+// Interrupts when DMA Block Transfer Completes 
+#define APBDMACHAN_CHANNEL_14_CSR_0_IE_EOC_SHIFT                        _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_14_CSR_0_IE_EOC_FIELD                        (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_14_CSR_0_IE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_14_CSR_0_IE_EOC_RANGE                        30:30
+#define APBDMACHAN_CHANNEL_14_CSR_0_IE_EOC_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_14_CSR_0_IE_EOC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_IE_EOC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_14_CSR_0_IE_EOC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_IE_EOC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_IE_EOC_DISABLE                      _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_IE_EOC_ENABLE                       _MK_ENUM_CONST(1)
+
+// Holds this Processor until DMA Block Transfer Completes 
+#define APBDMACHAN_CHANNEL_14_CSR_0_HOLD_SHIFT                  _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_14_CSR_0_HOLD_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_14_CSR_0_HOLD_SHIFT)
+#define APBDMACHAN_CHANNEL_14_CSR_0_HOLD_RANGE                  29:29
+#define APBDMACHAN_CHANNEL_14_CSR_0_HOLD_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_14_CSR_0_HOLD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_HOLD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_14_CSR_0_HOLD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_HOLD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_HOLD_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_HOLD_ENABLE                 _MK_ENUM_CONST(1)
+
+// DMA Transfer Direction 1 = AHB read to APB write 0 = APB read to AHB write
+#define APBDMACHAN_CHANNEL_14_CSR_0_DIR_SHIFT                   _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_14_CSR_0_DIR_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_14_CSR_0_DIR_SHIFT)
+#define APBDMACHAN_CHANNEL_14_CSR_0_DIR_RANGE                   28:28
+#define APBDMACHAN_CHANNEL_14_CSR_0_DIR_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_14_CSR_0_DIR_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_DIR_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_14_CSR_0_DIR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_DIR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_DIR_AHB_WRITE                       _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_DIR_AHB_READ                        _MK_ENUM_CONST(1)
+
+// Run Once or Run Multiple Mode (Allow Retriggering of this Channel) 1 = Run for One Block Transfer 0 = Run for Multiple Block Transfer
+#define APBDMACHAN_CHANNEL_14_CSR_0_ONCE_SHIFT                  _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_14_CSR_0_ONCE_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_14_CSR_0_ONCE_SHIFT)
+#define APBDMACHAN_CHANNEL_14_CSR_0_ONCE_RANGE                  27:27
+#define APBDMACHAN_CHANNEL_14_CSR_0_ONCE_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_14_CSR_0_ONCE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_ONCE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_14_CSR_0_ONCE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_ONCE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_ONCE_MULTIPLE_BLOCK                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_ONCE_SINGLE_BLOCK                   _MK_ENUM_CONST(1)
+
+// Enable on Non-Zero Value
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_SHIFT                      _MK_SHIFT_CONST(22)
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_FIELD                      (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_RANGE                      26:22
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_NA1                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_SMP24                      _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_SMP25                      _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_SMP26                      _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_SMP27                      _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_XRQ_A                      _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_XRQ_B                      _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_TMR1                       _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_TMR2                       _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_APB_0                      _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_APB_1                      _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_APB_2                      _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_APB_3                      _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_APB_4                      _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_APB_5                      _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_APB_6                      _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_APB_7                      _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_APB_8                      _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_APB_9                      _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_APB_10                     _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_APB_11                     _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_APB_12                     _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_APB_13                     _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_APB_14                     _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_APB_15                     _MK_ENUM_CONST(24)
+
+// Flow Control Enable (Synchronize Burst Transfers) 1 = Link to DRQ source 0 = Independent of DRQ request
+#define APBDMACHAN_CHANNEL_14_CSR_0_FLOW_SHIFT                  _MK_SHIFT_CONST(21)
+#define APBDMACHAN_CHANNEL_14_CSR_0_FLOW_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_14_CSR_0_FLOW_SHIFT)
+#define APBDMACHAN_CHANNEL_14_CSR_0_FLOW_RANGE                  21:21
+#define APBDMACHAN_CHANNEL_14_CSR_0_FLOW_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_14_CSR_0_FLOW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_FLOW_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_14_CSR_0_FLOW_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_FLOW_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_FLOW_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_FLOW_ENABLE                 _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_SHIFT                       _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_FIELD                       (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_RANGE                       20:16
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_CNTR_REQ                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_I2S_2                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_I2S_1                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_SPD_I                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_UI_I                        _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_MIPI                        _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_I2S2_2                      _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_I2S2_1                      _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_UART_A                      _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_UART_B                      _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_UART_C                      _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_SPI                 _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_AC97                        _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_ACModem                     _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_SL4B                        _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_SL2B1                       _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_SL2B2                       _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_SL2B3                       _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_SL2B4                       _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_UART_D                      _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_UART_E                      _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_I2C                 _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_I2C2                        _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_I2C3                        _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_DVC_I2C                     _MK_ENUM_CONST(24)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_OWR                 _MK_ENUM_CONST(25)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_NA26                        _MK_ENUM_CONST(26)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_NA27                        _MK_ENUM_CONST(27)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_NA28                        _MK_ENUM_CONST(28)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_NA29                        _MK_ENUM_CONST(29)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_NA30                        _MK_ENUM_CONST(30)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_NA31                        _MK_ENUM_CONST(31)
+
+// Number of 32bit word cycles
+#define APBDMACHAN_CHANNEL_14_CSR_0_WCOUNT_SHIFT                        _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_14_CSR_0_WCOUNT_FIELD                        (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_14_CSR_0_WCOUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_14_CSR_0_WCOUNT_RANGE                        15:2
+#define APBDMACHAN_CHANNEL_14_CSR_0_WCOUNT_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_14_CSR_0_WCOUNT_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_WCOUNT_DEFAULT_MASK                 _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_14_CSR_0_WCOUNT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_WCOUNT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_14_STA_0  
+#define APBDMACHAN_CHANNEL_14_STA_0                     _MK_ADDR_CONST(0x1c4)
+#define APBDMACHAN_CHANNEL_14_STA_0_SECURE                      0x0
+#define APBDMACHAN_CHANNEL_14_STA_0_WORD_COUNT                  0x1
+#define APBDMACHAN_CHANNEL_14_STA_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_STA_0_RESET_MASK                  _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_14_STA_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_STA_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_STA_0_READ_MASK                   _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_14_STA_0_WRITE_MASK                  _MK_MASK_CONST(0x40000000)
+// indicate DMA Channel Status activated or not 
+#define APBDMACHAN_CHANNEL_14_STA_0_BSY_SHIFT                   _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_14_STA_0_BSY_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_14_STA_0_BSY_SHIFT)
+#define APBDMACHAN_CHANNEL_14_STA_0_BSY_RANGE                   31:31
+#define APBDMACHAN_CHANNEL_14_STA_0_BSY_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_14_STA_0_BSY_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_STA_0_BSY_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_14_STA_0_BSY_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_STA_0_BSY_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_STA_0_BSY_WAIT                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_14_STA_0_BSY_ACTIVE                  _MK_ENUM_CONST(1)
+
+//  Write '1' to clear the flag
+#define APBDMACHAN_CHANNEL_14_STA_0_ISE_EOC_SHIFT                       _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_14_STA_0_ISE_EOC_FIELD                       (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_14_STA_0_ISE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_14_STA_0_ISE_EOC_RANGE                       30:30
+#define APBDMACHAN_CHANNEL_14_STA_0_ISE_EOC_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_14_STA_0_ISE_EOC_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_STA_0_ISE_EOC_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_14_STA_0_ISE_EOC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_STA_0_ISE_EOC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_STA_0_ISE_EOC_NO_INTR                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_14_STA_0_ISE_EOC_INTR                        _MK_ENUM_CONST(1)
+
+// Holding Status of Processor 
+#define APBDMACHAN_CHANNEL_14_STA_0_HALT_SHIFT                  _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_14_STA_0_HALT_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_14_STA_0_HALT_SHIFT)
+#define APBDMACHAN_CHANNEL_14_STA_0_HALT_RANGE                  29:29
+#define APBDMACHAN_CHANNEL_14_STA_0_HALT_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_14_STA_0_HALT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_STA_0_HALT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_14_STA_0_HALT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_STA_0_HALT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_STA_0_HALT_NO_HALT                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_14_STA_0_HALT_HALT                   _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_14_STA_0_PING_PONG_STA_SHIFT                 _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_14_STA_0_PING_PONG_STA_FIELD                 (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_14_STA_0_PING_PONG_STA_SHIFT)
+#define APBDMACHAN_CHANNEL_14_STA_0_PING_PONG_STA_RANGE                 28:28
+#define APBDMACHAN_CHANNEL_14_STA_0_PING_PONG_STA_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_14_STA_0_PING_PONG_STA_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_STA_0_PING_PONG_STA_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_14_STA_0_PING_PONG_STA_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_STA_0_PING_PONG_STA_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_STA_0_PING_PONG_STA_PING_INTR_STA                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_14_STA_0_PING_PONG_STA_PONG_INTR_STA                 _MK_ENUM_CONST(1)
+
+// Current 32bit word cycles Flags set /cleared by HW
+#define APBDMACHAN_CHANNEL_14_STA_0_COUNT_SHIFT                 _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_14_STA_0_COUNT_FIELD                 (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_14_STA_0_COUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_14_STA_0_COUNT_RANGE                 15:2
+#define APBDMACHAN_CHANNEL_14_STA_0_COUNT_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_14_STA_0_COUNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_STA_0_COUNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_14_STA_0_COUNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_STA_0_COUNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Reserved address 456 [0x1c8] 
+
+// Reserved address 460 [0x1cc] 
+
+// Register APBDMACHAN_CHANNEL_14_AHB_PTR_0  
+#define APBDMACHAN_CHANNEL_14_AHB_PTR_0                 _MK_ADDR_CONST(0x1d0)
+#define APBDMACHAN_CHANNEL_14_AHB_PTR_0_SECURE                  0x0
+#define APBDMACHAN_CHANNEL_14_AHB_PTR_0_WORD_COUNT                      0x1
+#define APBDMACHAN_CHANNEL_14_AHB_PTR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_AHB_PTR_0_RESET_MASK                      _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_14_AHB_PTR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_AHB_PTR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_AHB_PTR_0_READ_MASK                       _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_14_AHB_PTR_0_WRITE_MASK                      _MK_MASK_CONST(0xfffffffc)
+// APB-DMA Starting Address for AHB Bus: SW writes to  modify
+#define APBDMACHAN_CHANNEL_14_AHB_PTR_0_AHB_BASE_SHIFT                  _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_14_AHB_PTR_0_AHB_BASE_FIELD                  (_MK_MASK_CONST(0x3fffffff) << APBDMACHAN_CHANNEL_14_AHB_PTR_0_AHB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_14_AHB_PTR_0_AHB_BASE_RANGE                  31:2
+#define APBDMACHAN_CHANNEL_14_AHB_PTR_0_AHB_BASE_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_14_AHB_PTR_0_AHB_BASE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_AHB_PTR_0_AHB_BASE_DEFAULT_MASK                   _MK_MASK_CONST(0x3fffffff)
+#define APBDMACHAN_CHANNEL_14_AHB_PTR_0_AHB_BASE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_AHB_PTR_0_AHB_BASE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_14_AHB_SEQ_0  
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0                 _MK_ADDR_CONST(0x1d4)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_SECURE                  0x0
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_WORD_COUNT                      0x1
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_RESET_VAL                       _MK_MASK_CONST(0x20000000)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_RESET_MASK                      _MK_MASK_CONST(0xff0f0000)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_READ_MASK                       _MK_MASK_CONST(0xff0f0000)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_WRITE_MASK                      _MK_MASK_CONST(0xff0f0000)
+//  0 = send interrupt to COP
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_INTR_ENB_SHIFT                  _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_INTR_ENB_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_14_AHB_SEQ_0_INTR_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_INTR_ENB_RANGE                  31:31
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_INTR_ENB_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_INTR_ENB_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_INTR_ENB_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_INTR_ENB_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_INTR_ENB_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_INTR_ENB_CPU                    _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_INTR_ENB_COP                    _MK_ENUM_CONST(0)
+
+// AHB Bus Width 0 = 8 bit Bus (RSVD) 1 = 16 bit Bus (RSVD) 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD)4 = 128 bit Bus (RSVD)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT                     _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_BUS_WIDTH_FIELD                     (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_BUS_WIDTH_RANGE                     30:28
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_BUS_WIDTH_WOFFSET                   0x0
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT                   _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_8                       _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_16                      _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_32                      _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_64                      _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_128                     _MK_ENUM_CONST(4)
+
+// When enabled the data going  to AHB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT                     _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_DATA_SWAP_FIELD                     (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_DATA_SWAP_RANGE                     27:27
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_DATA_SWAP_WOFFSET                   0x0
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_DATA_SWAP_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_DATA_SWAP_ENABLE                    _MK_ENUM_CONST(1)
+
+// AHB Burst Size DMA Burst Length (encoded) 4 = 1 Word (1x32bits) 5 = 4 Words (4x32bits)else = 8 Words (8x32bits) default
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_BURST_SHIFT                 _MK_SHIFT_CONST(24)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_BURST_FIELD                 (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_BURST_SHIFT)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_BURST_RANGE                 26:24
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_BURST_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_BURST_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_BURST_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_BURST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_BURST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_BURST_DMA_BURST_1WORDS                      _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_BURST_DMA_BURST_4WORDS                      _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_BURST_DMA_BURST_8WORDS                      _MK_ENUM_CONST(6)
+
+// 2X Double Buffering Mode (For Run-Multiple Mode with No Wrap Operations) 1 = Reload Base Address for 2X blocks (reload every other time) 0 = Reload Base Address for 1X blocks  (def) (reload each time)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_DBL_BUF_SHIFT                   _MK_SHIFT_CONST(19)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_DBL_BUF_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_14_AHB_SEQ_0_DBL_BUF_SHIFT)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_DBL_BUF_RANGE                   19:19
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_DBL_BUF_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_DBL_BUF_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_DBL_BUF_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_DBL_BUF_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_DBL_BUF_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_DBL_BUF_RELOAD_FOR_1X_BLOCKS                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_DBL_BUF_RELOAD_FOR_2X_BLOCKS                    _MK_ENUM_CONST(1)
+
+// AHB Address Wrap: AHB Address wrap-around window 0=No Wrap (default) 5=Wrap on 512 word window 1=Wrap on 32 word window 6=Wrap on 1024 word window 2=Wrap on 64 word window 7=Wrap on 2048 word window 3=Wrap on 128 word window 4=Wrap on 256 word window
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_WRAP_SHIFT                      _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_WRAP_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_14_AHB_SEQ_0_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_WRAP_RANGE                      18:16
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_WRAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_WRAP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_WRAP_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_WRAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_WRAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_WRAP_NO_WRAP                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_WRAP_WRAP_0N_32WORDS                    _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_WRAP_WRAP_ON_64WORDS                    _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_WRAP_WRAP_ON_128WORDS                   _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_WRAP_WRAP_ON_256WORDS                   _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_WRAP_WRAP_ON_512WORDS                   _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_WRAP_WRAP_ON_1024WORDS                  _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_WRAP_WRAP_ON_2048WORDS                  _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_14_APB_PTR_0  
+#define APBDMACHAN_CHANNEL_14_APB_PTR_0                 _MK_ADDR_CONST(0x1d8)
+#define APBDMACHAN_CHANNEL_14_APB_PTR_0_SECURE                  0x0
+#define APBDMACHAN_CHANNEL_14_APB_PTR_0_WORD_COUNT                      0x1
+#define APBDMACHAN_CHANNEL_14_APB_PTR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_APB_PTR_0_RESET_MASK                      _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_14_APB_PTR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_APB_PTR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_APB_PTR_0_READ_MASK                       _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_14_APB_PTR_0_WRITE_MASK                      _MK_MASK_CONST(0xfffc)
+// APB-DMA Starting address for APB Bus: APB Base address:Upper 16 bits are fixed at 0x7000:XXXX
+#define APBDMACHAN_CHANNEL_14_APB_PTR_0_APB_BASE_SHIFT                  _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_14_APB_PTR_0_APB_BASE_FIELD                  (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_14_APB_PTR_0_APB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_14_APB_PTR_0_APB_BASE_RANGE                  15:2
+#define APBDMACHAN_CHANNEL_14_APB_PTR_0_APB_BASE_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_14_APB_PTR_0_APB_BASE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_APB_PTR_0_APB_BASE_DEFAULT_MASK                   _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_14_APB_PTR_0_APB_BASE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_APB_PTR_0_APB_BASE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_14_APB_SEQ_0  
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0                 _MK_ADDR_CONST(0x1dc)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_SECURE                  0x0
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_WORD_COUNT                      0x1
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_RESET_VAL                       _MK_MASK_CONST(0x20010000)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_RESET_MASK                      _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_READ_MASK                       _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_WRITE_MASK                      _MK_MASK_CONST(0x78070000)
+// 0 = 8 bit Bus 1 = 16 bit Bus 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD) 4 = 128 bit BUS (RSVD)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_BUS_WIDTH_SHIFT                     _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_BUS_WIDTH_FIELD                     (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_BUS_WIDTH_RANGE                     30:28
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_BUS_WIDTH_WOFFSET                   0x0
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT                   _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_8                       _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_16                      _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_32                      _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_64                      _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_128                     _MK_ENUM_CONST(4)
+
+// When enabled the data going  to APB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_DATA_SWAP_SHIFT                     _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_DATA_SWAP_FIELD                     (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_DATA_SWAP_RANGE                     27:27
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_DATA_SWAP_WOFFSET                   0x0
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_DATA_SWAP_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_DATA_SWAP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_DATA_SWAP_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_DATA_SWAP_ENABLE                    _MK_ENUM_CONST(1)
+
+//APB Address Wrap-around Window 0 = No Wrap 1 = Wrap on 1 Word Window (def) 2 = Wrap on 2 Word Window 3 = Wrap on 4 Word Window 4 = Wrap on 8 Word Window 5 = Wrap on 16 Word Window 6 = Wrap on 32 Word Window 7 = Wrap on 64 Word Window (rsvd)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_ADDR_WRAP_SHIFT                     _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_ADDR_WRAP_FIELD                     (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_ADDR_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_ADDR_WRAP_RANGE                     18:16
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_ADDR_WRAP_WOFFSET                   0x0
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_ADDR_WRAP_NO_WRAP                   _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_ADDR_WRAP_WRAP_0N_1WORDS                    _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_2WORDS                    _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_4WORDS                    _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_8WORDS                    _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_16WORDS                   _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_32WORDS                   _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_64WORDS                   _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_15_CSR_0  
+#define APBDMACHAN_CHANNEL_15_CSR_0                     _MK_ADDR_CONST(0x1e0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_SECURE                      0x0
+#define APBDMACHAN_CHANNEL_15_CSR_0_WORD_COUNT                  0x1
+#define APBDMACHAN_CHANNEL_15_CSR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_RESET_MASK                  _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_15_CSR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_READ_MASK                   _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_15_CSR_0_WRITE_MASK                  _MK_MASK_CONST(0xfffffffc)
+// Enables DMA channel transfer 
+#define APBDMACHAN_CHANNEL_15_CSR_0_ENB_SHIFT                   _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_15_CSR_0_ENB_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_15_CSR_0_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_15_CSR_0_ENB_RANGE                   31:31
+#define APBDMACHAN_CHANNEL_15_CSR_0_ENB_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_15_CSR_0_ENB_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_ENB_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_15_CSR_0_ENB_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_ENB_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_ENB_DISABLE                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_ENB_ENABLE                  _MK_ENUM_CONST(1)
+
+// Interrupts when DMA Block Transfer Completes 
+#define APBDMACHAN_CHANNEL_15_CSR_0_IE_EOC_SHIFT                        _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_15_CSR_0_IE_EOC_FIELD                        (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_15_CSR_0_IE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_15_CSR_0_IE_EOC_RANGE                        30:30
+#define APBDMACHAN_CHANNEL_15_CSR_0_IE_EOC_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_15_CSR_0_IE_EOC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_IE_EOC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_15_CSR_0_IE_EOC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_IE_EOC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_IE_EOC_DISABLE                      _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_IE_EOC_ENABLE                       _MK_ENUM_CONST(1)
+
+// Holds this Processor until DMA Block Transfer Completes 
+#define APBDMACHAN_CHANNEL_15_CSR_0_HOLD_SHIFT                  _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_15_CSR_0_HOLD_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_15_CSR_0_HOLD_SHIFT)
+#define APBDMACHAN_CHANNEL_15_CSR_0_HOLD_RANGE                  29:29
+#define APBDMACHAN_CHANNEL_15_CSR_0_HOLD_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_15_CSR_0_HOLD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_HOLD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_15_CSR_0_HOLD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_HOLD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_HOLD_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_HOLD_ENABLE                 _MK_ENUM_CONST(1)
+
+// DMA Transfer Direction 1 = AHB read to APB write 0 = APB read to AHB write
+#define APBDMACHAN_CHANNEL_15_CSR_0_DIR_SHIFT                   _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_15_CSR_0_DIR_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_15_CSR_0_DIR_SHIFT)
+#define APBDMACHAN_CHANNEL_15_CSR_0_DIR_RANGE                   28:28
+#define APBDMACHAN_CHANNEL_15_CSR_0_DIR_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_15_CSR_0_DIR_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_DIR_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_15_CSR_0_DIR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_DIR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_DIR_AHB_WRITE                       _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_DIR_AHB_READ                        _MK_ENUM_CONST(1)
+
+// Run Once or Run Multiple Mode (Allow Retriggering of this Channel) 1 = Run for One Block Transfer 0 = Run for Multiple Block Transfer
+#define APBDMACHAN_CHANNEL_15_CSR_0_ONCE_SHIFT                  _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_15_CSR_0_ONCE_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_15_CSR_0_ONCE_SHIFT)
+#define APBDMACHAN_CHANNEL_15_CSR_0_ONCE_RANGE                  27:27
+#define APBDMACHAN_CHANNEL_15_CSR_0_ONCE_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_15_CSR_0_ONCE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_ONCE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_15_CSR_0_ONCE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_ONCE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_ONCE_MULTIPLE_BLOCK                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_ONCE_SINGLE_BLOCK                   _MK_ENUM_CONST(1)
+
+// Enable on Non-Zero Value
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_SHIFT                      _MK_SHIFT_CONST(22)
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_FIELD                      (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_RANGE                      26:22
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_NA1                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_SMP24                      _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_SMP25                      _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_SMP26                      _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_SMP27                      _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_XRQ_A                      _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_XRQ_B                      _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_TMR1                       _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_TMR2                       _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_APB_0                      _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_APB_1                      _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_APB_2                      _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_APB_3                      _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_APB_4                      _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_APB_5                      _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_APB_6                      _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_APB_7                      _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_APB_8                      _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_APB_9                      _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_APB_10                     _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_APB_11                     _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_APB_12                     _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_APB_13                     _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_APB_14                     _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_APB_15                     _MK_ENUM_CONST(24)
+
+// Flow Control Enable (Synchronize Burst Transfers) 1 = Link to DRQ source 0 = Independent of DRQ request
+#define APBDMACHAN_CHANNEL_15_CSR_0_FLOW_SHIFT                  _MK_SHIFT_CONST(21)
+#define APBDMACHAN_CHANNEL_15_CSR_0_FLOW_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_15_CSR_0_FLOW_SHIFT)
+#define APBDMACHAN_CHANNEL_15_CSR_0_FLOW_RANGE                  21:21
+#define APBDMACHAN_CHANNEL_15_CSR_0_FLOW_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_15_CSR_0_FLOW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_FLOW_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_15_CSR_0_FLOW_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_FLOW_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_FLOW_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_FLOW_ENABLE                 _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_SHIFT                       _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_FIELD                       (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_RANGE                       20:16
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_CNTR_REQ                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_I2S_2                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_I2S_1                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_SPD_I                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_UI_I                        _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_MIPI                        _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_I2S2_2                      _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_I2S2_1                      _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_UART_A                      _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_UART_B                      _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_UART_C                      _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_SPI                 _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_AC97                        _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_ACModem                     _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_SL4B                        _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_SL2B1                       _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_SL2B2                       _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_SL2B3                       _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_SL2B4                       _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_UART_D                      _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_UART_E                      _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_I2C                 _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_I2C2                        _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_I2C3                        _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_DVC_I2C                     _MK_ENUM_CONST(24)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_OWR                 _MK_ENUM_CONST(25)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_NA26                        _MK_ENUM_CONST(26)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_NA27                        _MK_ENUM_CONST(27)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_NA28                        _MK_ENUM_CONST(28)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_NA29                        _MK_ENUM_CONST(29)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_NA30                        _MK_ENUM_CONST(30)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_NA31                        _MK_ENUM_CONST(31)
+
+// Number of 32bit word cycles
+#define APBDMACHAN_CHANNEL_15_CSR_0_WCOUNT_SHIFT                        _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_15_CSR_0_WCOUNT_FIELD                        (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_15_CSR_0_WCOUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_15_CSR_0_WCOUNT_RANGE                        15:2
+#define APBDMACHAN_CHANNEL_15_CSR_0_WCOUNT_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_15_CSR_0_WCOUNT_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_WCOUNT_DEFAULT_MASK                 _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_15_CSR_0_WCOUNT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_WCOUNT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_15_STA_0  
+#define APBDMACHAN_CHANNEL_15_STA_0                     _MK_ADDR_CONST(0x1e4)
+#define APBDMACHAN_CHANNEL_15_STA_0_SECURE                      0x0
+#define APBDMACHAN_CHANNEL_15_STA_0_WORD_COUNT                  0x1
+#define APBDMACHAN_CHANNEL_15_STA_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_STA_0_RESET_MASK                  _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_15_STA_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_STA_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_STA_0_READ_MASK                   _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_15_STA_0_WRITE_MASK                  _MK_MASK_CONST(0x40000000)
+// indicate DMA Channel Status activated or not 
+#define APBDMACHAN_CHANNEL_15_STA_0_BSY_SHIFT                   _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_15_STA_0_BSY_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_15_STA_0_BSY_SHIFT)
+#define APBDMACHAN_CHANNEL_15_STA_0_BSY_RANGE                   31:31
+#define APBDMACHAN_CHANNEL_15_STA_0_BSY_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_15_STA_0_BSY_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_STA_0_BSY_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_15_STA_0_BSY_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_STA_0_BSY_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_STA_0_BSY_WAIT                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_15_STA_0_BSY_ACTIVE                  _MK_ENUM_CONST(1)
+
+//  Write '1' to clear the flag
+#define APBDMACHAN_CHANNEL_15_STA_0_ISE_EOC_SHIFT                       _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_15_STA_0_ISE_EOC_FIELD                       (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_15_STA_0_ISE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_15_STA_0_ISE_EOC_RANGE                       30:30
+#define APBDMACHAN_CHANNEL_15_STA_0_ISE_EOC_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_15_STA_0_ISE_EOC_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_STA_0_ISE_EOC_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_15_STA_0_ISE_EOC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_STA_0_ISE_EOC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_STA_0_ISE_EOC_NO_INTR                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_15_STA_0_ISE_EOC_INTR                        _MK_ENUM_CONST(1)
+
+// Holding Status of Processor 
+#define APBDMACHAN_CHANNEL_15_STA_0_HALT_SHIFT                  _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_15_STA_0_HALT_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_15_STA_0_HALT_SHIFT)
+#define APBDMACHAN_CHANNEL_15_STA_0_HALT_RANGE                  29:29
+#define APBDMACHAN_CHANNEL_15_STA_0_HALT_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_15_STA_0_HALT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_STA_0_HALT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_15_STA_0_HALT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_STA_0_HALT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_STA_0_HALT_NO_HALT                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_15_STA_0_HALT_HALT                   _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_15_STA_0_PING_PONG_STA_SHIFT                 _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_15_STA_0_PING_PONG_STA_FIELD                 (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_15_STA_0_PING_PONG_STA_SHIFT)
+#define APBDMACHAN_CHANNEL_15_STA_0_PING_PONG_STA_RANGE                 28:28
+#define APBDMACHAN_CHANNEL_15_STA_0_PING_PONG_STA_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_15_STA_0_PING_PONG_STA_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_STA_0_PING_PONG_STA_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_15_STA_0_PING_PONG_STA_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_STA_0_PING_PONG_STA_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_STA_0_PING_PONG_STA_PING_INTR_STA                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_15_STA_0_PING_PONG_STA_PONG_INTR_STA                 _MK_ENUM_CONST(1)
+
+// Current 32bit word cycles Flags set /cleared by HW
+#define APBDMACHAN_CHANNEL_15_STA_0_COUNT_SHIFT                 _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_15_STA_0_COUNT_FIELD                 (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_15_STA_0_COUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_15_STA_0_COUNT_RANGE                 15:2
+#define APBDMACHAN_CHANNEL_15_STA_0_COUNT_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_15_STA_0_COUNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_STA_0_COUNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_15_STA_0_COUNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_STA_0_COUNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Reserved address 488 [0x1e8] 
+
+// Reserved address 492 [0x1ec] 
+
+// Register APBDMACHAN_CHANNEL_15_AHB_PTR_0  
+#define APBDMACHAN_CHANNEL_15_AHB_PTR_0                 _MK_ADDR_CONST(0x1f0)
+#define APBDMACHAN_CHANNEL_15_AHB_PTR_0_SECURE                  0x0
+#define APBDMACHAN_CHANNEL_15_AHB_PTR_0_WORD_COUNT                      0x1
+#define APBDMACHAN_CHANNEL_15_AHB_PTR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_AHB_PTR_0_RESET_MASK                      _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_15_AHB_PTR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_AHB_PTR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_AHB_PTR_0_READ_MASK                       _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_15_AHB_PTR_0_WRITE_MASK                      _MK_MASK_CONST(0xfffffffc)
+// APB-DMA Starting Address for AHB Bus: SW writes to  modify
+#define APBDMACHAN_CHANNEL_15_AHB_PTR_0_AHB_BASE_SHIFT                  _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_15_AHB_PTR_0_AHB_BASE_FIELD                  (_MK_MASK_CONST(0x3fffffff) << APBDMACHAN_CHANNEL_15_AHB_PTR_0_AHB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_15_AHB_PTR_0_AHB_BASE_RANGE                  31:2
+#define APBDMACHAN_CHANNEL_15_AHB_PTR_0_AHB_BASE_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_15_AHB_PTR_0_AHB_BASE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_AHB_PTR_0_AHB_BASE_DEFAULT_MASK                   _MK_MASK_CONST(0x3fffffff)
+#define APBDMACHAN_CHANNEL_15_AHB_PTR_0_AHB_BASE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_AHB_PTR_0_AHB_BASE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_15_AHB_SEQ_0  
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0                 _MK_ADDR_CONST(0x1f4)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_SECURE                  0x0
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_WORD_COUNT                      0x1
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_RESET_VAL                       _MK_MASK_CONST(0x20000000)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_RESET_MASK                      _MK_MASK_CONST(0xff0f0000)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_READ_MASK                       _MK_MASK_CONST(0xff0f0000)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_WRITE_MASK                      _MK_MASK_CONST(0xff0f0000)
+//  0 = send interrupt to COP
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_INTR_ENB_SHIFT                  _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_INTR_ENB_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_15_AHB_SEQ_0_INTR_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_INTR_ENB_RANGE                  31:31
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_INTR_ENB_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_INTR_ENB_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_INTR_ENB_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_INTR_ENB_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_INTR_ENB_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_INTR_ENB_CPU                    _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_INTR_ENB_COP                    _MK_ENUM_CONST(0)
+
+// AHB Bus Width 0 = 8 bit Bus (RSVD) 1 = 16 bit Bus (RSVD) 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD)4 = 128 bit Bus (RSVD)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT                     _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_BUS_WIDTH_FIELD                     (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_BUS_WIDTH_RANGE                     30:28
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_BUS_WIDTH_WOFFSET                   0x0
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT                   _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_8                       _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_16                      _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_32                      _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_64                      _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_128                     _MK_ENUM_CONST(4)
+
+// When enabled the data going  to AHB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT                     _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_DATA_SWAP_FIELD                     (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_DATA_SWAP_RANGE                     27:27
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_DATA_SWAP_WOFFSET                   0x0
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_DATA_SWAP_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_DATA_SWAP_ENABLE                    _MK_ENUM_CONST(1)
+
+// AHB Burst Size DMA Burst Length (encoded) 4 = 1 Word (1x32bits) 5 = 4 Words (4x32bits)else = 8 Words (8x32bits) default
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_BURST_SHIFT                 _MK_SHIFT_CONST(24)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_BURST_FIELD                 (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_BURST_SHIFT)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_BURST_RANGE                 26:24
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_BURST_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_BURST_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_BURST_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_BURST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_BURST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_BURST_DMA_BURST_1WORDS                      _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_BURST_DMA_BURST_4WORDS                      _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_BURST_DMA_BURST_8WORDS                      _MK_ENUM_CONST(6)
+
+// 2X Double Buffering Mode (For Run-Multiple Mode with No Wrap Operations) 1 = Reload Base Address for 2X blocks (reload every other time) 0 = Reload Base Address for 1X blocks  (def) (reload each time)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_DBL_BUF_SHIFT                   _MK_SHIFT_CONST(19)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_DBL_BUF_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_15_AHB_SEQ_0_DBL_BUF_SHIFT)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_DBL_BUF_RANGE                   19:19
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_DBL_BUF_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_DBL_BUF_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_DBL_BUF_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_DBL_BUF_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_DBL_BUF_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_DBL_BUF_RELOAD_FOR_1X_BLOCKS                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_DBL_BUF_RELOAD_FOR_2X_BLOCKS                    _MK_ENUM_CONST(1)
+
+// AHB Address Wrap: AHB Address wrap-around window 0=No Wrap (default) 5=Wrap on 512 word window 1=Wrap on 32 word window 6=Wrap on 1024 word window 2=Wrap on 64 word window 7=Wrap on 2048 word window 3=Wrap on 128 word window 4=Wrap on 256 word window
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_WRAP_SHIFT                      _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_WRAP_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_15_AHB_SEQ_0_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_WRAP_RANGE                      18:16
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_WRAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_WRAP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_WRAP_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_WRAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_WRAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_WRAP_NO_WRAP                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_WRAP_WRAP_0N_32WORDS                    _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_WRAP_WRAP_ON_64WORDS                    _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_WRAP_WRAP_ON_128WORDS                   _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_WRAP_WRAP_ON_256WORDS                   _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_WRAP_WRAP_ON_512WORDS                   _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_WRAP_WRAP_ON_1024WORDS                  _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_WRAP_WRAP_ON_2048WORDS                  _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_15_APB_PTR_0  
+#define APBDMACHAN_CHANNEL_15_APB_PTR_0                 _MK_ADDR_CONST(0x1f8)
+#define APBDMACHAN_CHANNEL_15_APB_PTR_0_SECURE                  0x0
+#define APBDMACHAN_CHANNEL_15_APB_PTR_0_WORD_COUNT                      0x1
+#define APBDMACHAN_CHANNEL_15_APB_PTR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_APB_PTR_0_RESET_MASK                      _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_15_APB_PTR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_APB_PTR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_APB_PTR_0_READ_MASK                       _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_15_APB_PTR_0_WRITE_MASK                      _MK_MASK_CONST(0xfffc)
+// APB-DMA Starting address for APB Bus: APB Base address:Upper 16 bits are fixed at 0x7000:XXXX
+#define APBDMACHAN_CHANNEL_15_APB_PTR_0_APB_BASE_SHIFT                  _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_15_APB_PTR_0_APB_BASE_FIELD                  (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_15_APB_PTR_0_APB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_15_APB_PTR_0_APB_BASE_RANGE                  15:2
+#define APBDMACHAN_CHANNEL_15_APB_PTR_0_APB_BASE_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_15_APB_PTR_0_APB_BASE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_APB_PTR_0_APB_BASE_DEFAULT_MASK                   _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_15_APB_PTR_0_APB_BASE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_APB_PTR_0_APB_BASE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_15_APB_SEQ_0  
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0                 _MK_ADDR_CONST(0x1fc)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_SECURE                  0x0
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_WORD_COUNT                      0x1
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_RESET_VAL                       _MK_MASK_CONST(0x20010000)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_RESET_MASK                      _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_READ_MASK                       _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_WRITE_MASK                      _MK_MASK_CONST(0x78070000)
+// 0 = 8 bit Bus 1 = 16 bit Bus 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD) 4 = 128 bit BUS (RSVD)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_BUS_WIDTH_SHIFT                     _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_BUS_WIDTH_FIELD                     (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_BUS_WIDTH_RANGE                     30:28
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_BUS_WIDTH_WOFFSET                   0x0
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT                   _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_8                       _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_16                      _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_32                      _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_64                      _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_128                     _MK_ENUM_CONST(4)
+
+// When enabled the data going  to APB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }.
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_DATA_SWAP_SHIFT                     _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_DATA_SWAP_FIELD                     (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_DATA_SWAP_RANGE                     27:27
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_DATA_SWAP_WOFFSET                   0x0
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_DATA_SWAP_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_DATA_SWAP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_DATA_SWAP_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_DATA_SWAP_ENABLE                    _MK_ENUM_CONST(1)
+
+//APB Address Wrap-around Window 0 = No Wrap 1 = Wrap on 1 Word Window (def) 2 = Wrap on 2 Word Window 3 = Wrap on 4 Word Window 4 = Wrap on 8 Word Window 5 = Wrap on 16 Word Window 6 = Wrap on 32 Word Window 7 = Wrap on 64 Word Window (rsvd)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_ADDR_WRAP_SHIFT                     _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_ADDR_WRAP_FIELD                     (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_ADDR_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_ADDR_WRAP_RANGE                     18:16
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_ADDR_WRAP_WOFFSET                   0x0
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_ADDR_WRAP_NO_WRAP                   _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_ADDR_WRAP_WRAP_0N_1WORDS                    _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_2WORDS                    _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_4WORDS                    _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_8WORDS                    _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_16WORDS                   _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_32WORDS                   _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_64WORDS                   _MK_ENUM_CONST(7)
+
+
+//
+// REGISTER LIST
+//
+#define LIST_ARAPBDMACHAN_REGS(_op_) \
+_op_(APBDMACHAN_CHANNEL_0_CSR_0) \
+_op_(APBDMACHAN_CHANNEL_0_STA_0) \
+_op_(APBDMACHAN_CHANNEL_0_AHB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_0_AHB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_0_APB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_0_APB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_1_CSR_0) \
+_op_(APBDMACHAN_CHANNEL_1_STA_0) \
+_op_(APBDMACHAN_CHANNEL_1_AHB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_1_AHB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_1_APB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_1_APB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_2_CSR_0) \
+_op_(APBDMACHAN_CHANNEL_2_STA_0) \
+_op_(APBDMACHAN_CHANNEL_2_AHB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_2_AHB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_2_APB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_2_APB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_3_CSR_0) \
+_op_(APBDMACHAN_CHANNEL_3_STA_0) \
+_op_(APBDMACHAN_CHANNEL_3_AHB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_3_AHB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_3_APB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_3_APB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_4_CSR_0) \
+_op_(APBDMACHAN_CHANNEL_4_STA_0) \
+_op_(APBDMACHAN_CHANNEL_4_AHB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_4_AHB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_4_APB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_4_APB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_5_CSR_0) \
+_op_(APBDMACHAN_CHANNEL_5_STA_0) \
+_op_(APBDMACHAN_CHANNEL_5_AHB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_5_AHB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_5_APB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_5_APB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_6_CSR_0) \
+_op_(APBDMACHAN_CHANNEL_6_STA_0) \
+_op_(APBDMACHAN_CHANNEL_6_AHB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_6_AHB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_6_APB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_6_APB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_7_CSR_0) \
+_op_(APBDMACHAN_CHANNEL_7_STA_0) \
+_op_(APBDMACHAN_CHANNEL_7_AHB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_7_AHB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_7_APB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_7_APB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_8_CSR_0) \
+_op_(APBDMACHAN_CHANNEL_8_STA_0) \
+_op_(APBDMACHAN_CHANNEL_8_AHB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_8_AHB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_8_APB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_8_APB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_9_CSR_0) \
+_op_(APBDMACHAN_CHANNEL_9_STA_0) \
+_op_(APBDMACHAN_CHANNEL_9_AHB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_9_AHB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_9_APB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_9_APB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_10_CSR_0) \
+_op_(APBDMACHAN_CHANNEL_10_STA_0) \
+_op_(APBDMACHAN_CHANNEL_10_AHB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_10_AHB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_10_APB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_10_APB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_11_CSR_0) \
+_op_(APBDMACHAN_CHANNEL_11_STA_0) \
+_op_(APBDMACHAN_CHANNEL_11_AHB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_11_AHB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_11_APB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_11_APB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_12_CSR_0) \
+_op_(APBDMACHAN_CHANNEL_12_STA_0) \
+_op_(APBDMACHAN_CHANNEL_12_AHB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_12_AHB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_12_APB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_12_APB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_13_CSR_0) \
+_op_(APBDMACHAN_CHANNEL_13_STA_0) \
+_op_(APBDMACHAN_CHANNEL_13_AHB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_13_AHB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_13_APB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_13_APB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_14_CSR_0) \
+_op_(APBDMACHAN_CHANNEL_14_STA_0) \
+_op_(APBDMACHAN_CHANNEL_14_AHB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_14_AHB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_14_APB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_14_APB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_15_CSR_0) \
+_op_(APBDMACHAN_CHANNEL_15_STA_0) \
+_op_(APBDMACHAN_CHANNEL_15_AHB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_15_AHB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_15_APB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_15_APB_SEQ_0)
+
+
+//
+// ADDRESS SPACES
+//
+
+#define BASE_ADDRESS_APBDMACHAN 0x00000000
+
+//
+// ARAPBDMACHAN REGISTER BANKS
+//
+
+#define APBDMACHAN0_FIRST_REG 0x0000 // APBDMACHAN_CHANNEL_0_CSR_0
+#define APBDMACHAN0_LAST_REG 0x0004 // APBDMACHAN_CHANNEL_0_STA_0
+#define APBDMACHAN1_FIRST_REG 0x0010 // APBDMACHAN_CHANNEL_0_AHB_PTR_0
+#define APBDMACHAN1_LAST_REG 0x0024 // APBDMACHAN_CHANNEL_1_STA_0
+#define APBDMACHAN2_FIRST_REG 0x0030 // APBDMACHAN_CHANNEL_1_AHB_PTR_0
+#define APBDMACHAN2_LAST_REG 0x0044 // APBDMACHAN_CHANNEL_2_STA_0
+#define APBDMACHAN3_FIRST_REG 0x0050 // APBDMACHAN_CHANNEL_2_AHB_PTR_0
+#define APBDMACHAN3_LAST_REG 0x0064 // APBDMACHAN_CHANNEL_3_STA_0
+#define APBDMACHAN4_FIRST_REG 0x0070 // APBDMACHAN_CHANNEL_3_AHB_PTR_0
+#define APBDMACHAN4_LAST_REG 0x0084 // APBDMACHAN_CHANNEL_4_STA_0
+#define APBDMACHAN5_FIRST_REG 0x0090 // APBDMACHAN_CHANNEL_4_AHB_PTR_0
+#define APBDMACHAN5_LAST_REG 0x00a4 // APBDMACHAN_CHANNEL_5_STA_0
+#define APBDMACHAN6_FIRST_REG 0x00b0 // APBDMACHAN_CHANNEL_5_AHB_PTR_0
+#define APBDMACHAN6_LAST_REG 0x00c4 // APBDMACHAN_CHANNEL_6_STA_0
+#define APBDMACHAN7_FIRST_REG 0x00d0 // APBDMACHAN_CHANNEL_6_AHB_PTR_0
+#define APBDMACHAN7_LAST_REG 0x00e4 // APBDMACHAN_CHANNEL_7_STA_0
+#define APBDMACHAN8_FIRST_REG 0x00f0 // APBDMACHAN_CHANNEL_7_AHB_PTR_0
+#define APBDMACHAN8_LAST_REG 0x0104 // APBDMACHAN_CHANNEL_8_STA_0
+#define APBDMACHAN9_FIRST_REG 0x0110 // APBDMACHAN_CHANNEL_8_AHB_PTR_0
+#define APBDMACHAN9_LAST_REG 0x0124 // APBDMACHAN_CHANNEL_9_STA_0
+#define APBDMACHAN10_FIRST_REG 0x0130 // APBDMACHAN_CHANNEL_9_AHB_PTR_0
+#define APBDMACHAN10_LAST_REG 0x0144 // APBDMACHAN_CHANNEL_10_STA_0
+#define APBDMACHAN11_FIRST_REG 0x0150 // APBDMACHAN_CHANNEL_10_AHB_PTR_0
+#define APBDMACHAN11_LAST_REG 0x0164 // APBDMACHAN_CHANNEL_11_STA_0
+#define APBDMACHAN12_FIRST_REG 0x0170 // APBDMACHAN_CHANNEL_11_AHB_PTR_0
+#define APBDMACHAN12_LAST_REG 0x0184 // APBDMACHAN_CHANNEL_12_STA_0
+#define APBDMACHAN13_FIRST_REG 0x0190 // APBDMACHAN_CHANNEL_12_AHB_PTR_0
+#define APBDMACHAN13_LAST_REG 0x01a4 // APBDMACHAN_CHANNEL_13_STA_0
+#define APBDMACHAN14_FIRST_REG 0x01b0 // APBDMACHAN_CHANNEL_13_AHB_PTR_0
+#define APBDMACHAN14_LAST_REG 0x01c4 // APBDMACHAN_CHANNEL_14_STA_0
+#define APBDMACHAN15_FIRST_REG 0x01d0 // APBDMACHAN_CHANNEL_14_AHB_PTR_0
+#define APBDMACHAN15_LAST_REG 0x01e4 // APBDMACHAN_CHANNEL_15_STA_0
+#define APBDMACHAN16_FIRST_REG 0x01f0 // APBDMACHAN_CHANNEL_15_AHB_PTR_0
+#define APBDMACHAN16_LAST_REG 0x01fc // APBDMACHAN_CHANNEL_15_APB_SEQ_0
+
+#ifndef _MK_SHIFT_CONST
+  #define _MK_SHIFT_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_MASK_CONST
+  #define _MK_MASK_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_ENUM_CONST
+  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
+#endif
+#ifndef _MK_ADDR_CONST
+  #define _MK_ADDR_CONST(_constant_) _constant_
+#endif
+
+#endif // ifndef ___ARAPBDMACHAN_H_INC_
diff --git a/arch/arm/mach-tegra/include/ap20/arapbpm.h b/arch/arm/mach-tegra/include/ap20/arapbpm.h
new file mode 100644
index 000000000000..6725a85fe701
--- /dev/null
+++ b/arch/arm/mach-tegra/include/ap20/arapbpm.h
@@ -0,0 +1,3602 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+//
+// DO NOT EDIT - generated by simspec!
+//
+
+#ifndef ___ARAPBPM_H_INC_
+#define ___ARAPBPM_H_INC_
+
+// Register APBDEV_PMC_CNTRL_0  
+#define APBDEV_PMC_CNTRL_0                      _MK_ADDR_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_SECURE                       0x0
+#define APBDEV_PMC_CNTRL_0_WORD_COUNT                   0x1
+#define APBDEV_PMC_CNTRL_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_RESET_MASK                   _MK_MASK_CONST(0x7ffff)
+#define APBDEV_PMC_CNTRL_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_READ_MASK                    _MK_MASK_CONST(0x7ffff)
+#define APBDEV_PMC_CNTRL_0_WRITE_MASK                   _MK_MASK_CONST(0x7ffff)
+// Disable 32KHz clock to KBC 
+#define APBDEV_PMC_CNTRL_0_KBC_CLK_DIS_SHIFT                    _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_CNTRL_0_KBC_CLK_DIS_FIELD                    (_MK_MASK_CONST(0x1) << APBDEV_PMC_CNTRL_0_KBC_CLK_DIS_SHIFT)
+#define APBDEV_PMC_CNTRL_0_KBC_CLK_DIS_RANGE                    0:0
+#define APBDEV_PMC_CNTRL_0_KBC_CLK_DIS_WOFFSET                  0x0
+#define APBDEV_PMC_CNTRL_0_KBC_CLK_DIS_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_KBC_CLK_DIS_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_CNTRL_0_KBC_CLK_DIS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_KBC_CLK_DIS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_KBC_CLK_DIS_DISABLE                  _MK_ENUM_CONST(0)
+#define APBDEV_PMC_CNTRL_0_KBC_CLK_DIS_ENABLE                   _MK_ENUM_CONST(1)
+
+// Disable  32KHz clock to RTC                          
+#define APBDEV_PMC_CNTRL_0_RTC_CLK_DIS_SHIFT                    _MK_SHIFT_CONST(1)
+#define APBDEV_PMC_CNTRL_0_RTC_CLK_DIS_FIELD                    (_MK_MASK_CONST(0x1) << APBDEV_PMC_CNTRL_0_RTC_CLK_DIS_SHIFT)
+#define APBDEV_PMC_CNTRL_0_RTC_CLK_DIS_RANGE                    1:1
+#define APBDEV_PMC_CNTRL_0_RTC_CLK_DIS_WOFFSET                  0x0
+#define APBDEV_PMC_CNTRL_0_RTC_CLK_DIS_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_RTC_CLK_DIS_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_CNTRL_0_RTC_CLK_DIS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_RTC_CLK_DIS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_RTC_CLK_DIS_DISABLE                  _MK_ENUM_CONST(0)
+#define APBDEV_PMC_CNTRL_0_RTC_CLK_DIS_ENABLE                   _MK_ENUM_CONST(1)
+
+// Software reset to RTC
+#define APBDEV_PMC_CNTRL_0_RTC_RST_SHIFT                        _MK_SHIFT_CONST(2)
+#define APBDEV_PMC_CNTRL_0_RTC_RST_FIELD                        (_MK_MASK_CONST(0x1) << APBDEV_PMC_CNTRL_0_RTC_RST_SHIFT)
+#define APBDEV_PMC_CNTRL_0_RTC_RST_RANGE                        2:2
+#define APBDEV_PMC_CNTRL_0_RTC_RST_WOFFSET                      0x0
+#define APBDEV_PMC_CNTRL_0_RTC_RST_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_RTC_RST_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_CNTRL_0_RTC_RST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_RTC_RST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_RTC_RST_DISABLE                      _MK_ENUM_CONST(0)
+#define APBDEV_PMC_CNTRL_0_RTC_RST_ENABLE                       _MK_ENUM_CONST(1)
+
+// Software reset to KBC  
+#define APBDEV_PMC_CNTRL_0_KBC_RST_SHIFT                        _MK_SHIFT_CONST(3)
+#define APBDEV_PMC_CNTRL_0_KBC_RST_FIELD                        (_MK_MASK_CONST(0x1) << APBDEV_PMC_CNTRL_0_KBC_RST_SHIFT)
+#define APBDEV_PMC_CNTRL_0_KBC_RST_RANGE                        3:3
+#define APBDEV_PMC_CNTRL_0_KBC_RST_WOFFSET                      0x0
+#define APBDEV_PMC_CNTRL_0_KBC_RST_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_KBC_RST_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_CNTRL_0_KBC_RST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_KBC_RST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_KBC_RST_DISABLE                      _MK_ENUM_CONST(0)
+#define APBDEV_PMC_CNTRL_0_KBC_RST_ENABLE                       _MK_ENUM_CONST(1)
+
+// Reset to CAR - generates 2 clock cycle  pulse. 
+#define APBDEV_PMC_CNTRL_0_MAIN_RST_SHIFT                       _MK_SHIFT_CONST(4)
+#define APBDEV_PMC_CNTRL_0_MAIN_RST_FIELD                       (_MK_MASK_CONST(0x1) << APBDEV_PMC_CNTRL_0_MAIN_RST_SHIFT)
+#define APBDEV_PMC_CNTRL_0_MAIN_RST_RANGE                       4:4
+#define APBDEV_PMC_CNTRL_0_MAIN_RST_WOFFSET                     0x0
+#define APBDEV_PMC_CNTRL_0_MAIN_RST_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_MAIN_RST_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_CNTRL_0_MAIN_RST_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_MAIN_RST_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_MAIN_RST_DISABLE                     _MK_ENUM_CONST(0)
+#define APBDEV_PMC_CNTRL_0_MAIN_RST_ENABLE                      _MK_ENUM_CONST(1)
+
+// Enables latching wakeup events - stops latching   on transition from 1 to 0(sequence - set to 1,set to 0) 
+#define APBDEV_PMC_CNTRL_0_LATCHWAKE_EN_SHIFT                   _MK_SHIFT_CONST(5)
+#define APBDEV_PMC_CNTRL_0_LATCHWAKE_EN_FIELD                   (_MK_MASK_CONST(0x1) << APBDEV_PMC_CNTRL_0_LATCHWAKE_EN_SHIFT)
+#define APBDEV_PMC_CNTRL_0_LATCHWAKE_EN_RANGE                   5:5
+#define APBDEV_PMC_CNTRL_0_LATCHWAKE_EN_WOFFSET                 0x0
+#define APBDEV_PMC_CNTRL_0_LATCHWAKE_EN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_LATCHWAKE_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_CNTRL_0_LATCHWAKE_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_LATCHWAKE_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_LATCHWAKE_EN_DISABLE                 _MK_ENUM_CONST(0)
+#define APBDEV_PMC_CNTRL_0_LATCHWAKE_EN_ENABLE                  _MK_ENUM_CONST(1)
+
+// Disable  detecting glitch on wakeup event- in default operation glitches are ignored on wakeup lines. if this bit is set to 1, glitch (event shorter than half 32khz clock, will be causing wakeup from lp0
+#define APBDEV_PMC_CNTRL_0_GLITCHDET_DIS_SHIFT                  _MK_SHIFT_CONST(6)
+#define APBDEV_PMC_CNTRL_0_GLITCHDET_DIS_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_PMC_CNTRL_0_GLITCHDET_DIS_SHIFT)
+#define APBDEV_PMC_CNTRL_0_GLITCHDET_DIS_RANGE                  6:6
+#define APBDEV_PMC_CNTRL_0_GLITCHDET_DIS_WOFFSET                        0x0
+#define APBDEV_PMC_CNTRL_0_GLITCHDET_DIS_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_GLITCHDET_DIS_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_CNTRL_0_GLITCHDET_DIS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_GLITCHDET_DIS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_GLITCHDET_DIS_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDEV_PMC_CNTRL_0_GLITCHDET_DIS_ENABLE                 _MK_ENUM_CONST(1)
+
+// Enables blinking counter and blink output -works only if BLINK field in DPD_PADS_ORIDE is set to 1
+#define APBDEV_PMC_CNTRL_0_BLINK_EN_SHIFT                       _MK_SHIFT_CONST(7)
+#define APBDEV_PMC_CNTRL_0_BLINK_EN_FIELD                       (_MK_MASK_CONST(0x1) << APBDEV_PMC_CNTRL_0_BLINK_EN_SHIFT)
+#define APBDEV_PMC_CNTRL_0_BLINK_EN_RANGE                       7:7
+#define APBDEV_PMC_CNTRL_0_BLINK_EN_WOFFSET                     0x0
+#define APBDEV_PMC_CNTRL_0_BLINK_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_BLINK_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_CNTRL_0_BLINK_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_BLINK_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_BLINK_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APBDEV_PMC_CNTRL_0_BLINK_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// Inverts power request polarity
+#define APBDEV_PMC_CNTRL_0_PWRREQ_POLARITY_SHIFT                        _MK_SHIFT_CONST(8)
+#define APBDEV_PMC_CNTRL_0_PWRREQ_POLARITY_FIELD                        (_MK_MASK_CONST(0x1) << APBDEV_PMC_CNTRL_0_PWRREQ_POLARITY_SHIFT)
+#define APBDEV_PMC_CNTRL_0_PWRREQ_POLARITY_RANGE                        8:8
+#define APBDEV_PMC_CNTRL_0_PWRREQ_POLARITY_WOFFSET                      0x0
+#define APBDEV_PMC_CNTRL_0_PWRREQ_POLARITY_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_PWRREQ_POLARITY_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_CNTRL_0_PWRREQ_POLARITY_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_PWRREQ_POLARITY_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_PWRREQ_POLARITY_NORMAL                       _MK_ENUM_CONST(0)
+#define APBDEV_PMC_CNTRL_0_PWRREQ_POLARITY_INVERT                       _MK_ENUM_CONST(1)
+
+// Power request output enable. resets to tristate
+#define APBDEV_PMC_CNTRL_0_PWRREQ_OE_SHIFT                      _MK_SHIFT_CONST(9)
+#define APBDEV_PMC_CNTRL_0_PWRREQ_OE_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_PMC_CNTRL_0_PWRREQ_OE_SHIFT)
+#define APBDEV_PMC_CNTRL_0_PWRREQ_OE_RANGE                      9:9
+#define APBDEV_PMC_CNTRL_0_PWRREQ_OE_WOFFSET                    0x0
+#define APBDEV_PMC_CNTRL_0_PWRREQ_OE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_PWRREQ_OE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_CNTRL_0_PWRREQ_OE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_PWRREQ_OE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_PWRREQ_OE_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_CNTRL_0_PWRREQ_OE_ENABLE                     _MK_ENUM_CONST(1)
+
+// Inverts system clock enable polarity 
+#define APBDEV_PMC_CNTRL_0_SYSCLK_POLARITY_SHIFT                        _MK_SHIFT_CONST(10)
+#define APBDEV_PMC_CNTRL_0_SYSCLK_POLARITY_FIELD                        (_MK_MASK_CONST(0x1) << APBDEV_PMC_CNTRL_0_SYSCLK_POLARITY_SHIFT)
+#define APBDEV_PMC_CNTRL_0_SYSCLK_POLARITY_RANGE                        10:10
+#define APBDEV_PMC_CNTRL_0_SYSCLK_POLARITY_WOFFSET                      0x0
+#define APBDEV_PMC_CNTRL_0_SYSCLK_POLARITY_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_SYSCLK_POLARITY_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_CNTRL_0_SYSCLK_POLARITY_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_SYSCLK_POLARITY_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_SYSCLK_POLARITY_NORMAL                       _MK_ENUM_CONST(0)
+#define APBDEV_PMC_CNTRL_0_SYSCLK_POLARITY_INVERT                       _MK_ENUM_CONST(1)
+
+// Enables output of system enable clock - works only if SYS_CLK field in DPD_PADS_ORIDE is set to 1. resets to tristate
+#define APBDEV_PMC_CNTRL_0_SYSCLK_OE_SHIFT                      _MK_SHIFT_CONST(11)
+#define APBDEV_PMC_CNTRL_0_SYSCLK_OE_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_PMC_CNTRL_0_SYSCLK_OE_SHIFT)
+#define APBDEV_PMC_CNTRL_0_SYSCLK_OE_RANGE                      11:11
+#define APBDEV_PMC_CNTRL_0_SYSCLK_OE_WOFFSET                    0x0
+#define APBDEV_PMC_CNTRL_0_SYSCLK_OE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_SYSCLK_OE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_CNTRL_0_SYSCLK_OE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_SYSCLK_OE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_SYSCLK_OE_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_CNTRL_0_SYSCLK_OE_ENABLE                     _MK_ENUM_CONST(1)
+
+// Disable  power gating - global override, will override function of PWRGATE_TOGGLE register. all partitions will stay enabled. 
+#define APBDEV_PMC_CNTRL_0_PWRGATE_DIS_SHIFT                    _MK_SHIFT_CONST(12)
+#define APBDEV_PMC_CNTRL_0_PWRGATE_DIS_FIELD                    (_MK_MASK_CONST(0x1) << APBDEV_PMC_CNTRL_0_PWRGATE_DIS_SHIFT)
+#define APBDEV_PMC_CNTRL_0_PWRGATE_DIS_RANGE                    12:12
+#define APBDEV_PMC_CNTRL_0_PWRGATE_DIS_WOFFSET                  0x0
+#define APBDEV_PMC_CNTRL_0_PWRGATE_DIS_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_PWRGATE_DIS_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_CNTRL_0_PWRGATE_DIS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_PWRGATE_DIS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_PWRGATE_DIS_DISABLE                  _MK_ENUM_CONST(0)
+#define APBDEV_PMC_CNTRL_0_PWRGATE_DIS_ENABLE                   _MK_ENUM_CONST(1)
+
+// AO intitlized  purely sftw diagnostic and interpretation
+#define APBDEV_PMC_CNTRL_0_AOINIT_SHIFT                 _MK_SHIFT_CONST(13)
+#define APBDEV_PMC_CNTRL_0_AOINIT_FIELD                 (_MK_MASK_CONST(0x1) << APBDEV_PMC_CNTRL_0_AOINIT_SHIFT)
+#define APBDEV_PMC_CNTRL_0_AOINIT_RANGE                 13:13
+#define APBDEV_PMC_CNTRL_0_AOINIT_WOFFSET                       0x0
+#define APBDEV_PMC_CNTRL_0_AOINIT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_AOINIT_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_CNTRL_0_AOINIT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_AOINIT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_AOINIT_NOTDONE                       _MK_ENUM_CONST(0)
+#define APBDEV_PMC_CNTRL_0_AOINIT_DONE                  _MK_ENUM_CONST(1)
+
+// when set causes side effect of entering lp0 after powering down cpu
+#define APBDEV_PMC_CNTRL_0_SIDE_EFFECT_LP0_SHIFT                        _MK_SHIFT_CONST(14)
+#define APBDEV_PMC_CNTRL_0_SIDE_EFFECT_LP0_FIELD                        (_MK_MASK_CONST(0x1) << APBDEV_PMC_CNTRL_0_SIDE_EFFECT_LP0_SHIFT)
+#define APBDEV_PMC_CNTRL_0_SIDE_EFFECT_LP0_RANGE                        14:14
+#define APBDEV_PMC_CNTRL_0_SIDE_EFFECT_LP0_WOFFSET                      0x0
+#define APBDEV_PMC_CNTRL_0_SIDE_EFFECT_LP0_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_SIDE_EFFECT_LP0_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_CNTRL_0_SIDE_EFFECT_LP0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_SIDE_EFFECT_LP0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_SIDE_EFFECT_LP0_DISABLE                      _MK_ENUM_CONST(0)
+#define APBDEV_PMC_CNTRL_0_SIDE_EFFECT_LP0_ENABLE                       _MK_ENUM_CONST(1)
+
+// Inverts power request polarity
+#define APBDEV_PMC_CNTRL_0_CPUPWRREQ_POLARITY_SHIFT                     _MK_SHIFT_CONST(15)
+#define APBDEV_PMC_CNTRL_0_CPUPWRREQ_POLARITY_FIELD                     (_MK_MASK_CONST(0x1) << APBDEV_PMC_CNTRL_0_CPUPWRREQ_POLARITY_SHIFT)
+#define APBDEV_PMC_CNTRL_0_CPUPWRREQ_POLARITY_RANGE                     15:15
+#define APBDEV_PMC_CNTRL_0_CPUPWRREQ_POLARITY_WOFFSET                   0x0
+#define APBDEV_PMC_CNTRL_0_CPUPWRREQ_POLARITY_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_CPUPWRREQ_POLARITY_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_CNTRL_0_CPUPWRREQ_POLARITY_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_CPUPWRREQ_POLARITY_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_CPUPWRREQ_POLARITY_NORMAL                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_CNTRL_0_CPUPWRREQ_POLARITY_INVERT                    _MK_ENUM_CONST(1)
+
+// Power request output enable. resets to tristate
+#define APBDEV_PMC_CNTRL_0_CPUPWRREQ_OE_SHIFT                   _MK_SHIFT_CONST(16)
+#define APBDEV_PMC_CNTRL_0_CPUPWRREQ_OE_FIELD                   (_MK_MASK_CONST(0x1) << APBDEV_PMC_CNTRL_0_CPUPWRREQ_OE_SHIFT)
+#define APBDEV_PMC_CNTRL_0_CPUPWRREQ_OE_RANGE                   16:16
+#define APBDEV_PMC_CNTRL_0_CPUPWRREQ_OE_WOFFSET                 0x0
+#define APBDEV_PMC_CNTRL_0_CPUPWRREQ_OE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_CPUPWRREQ_OE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_CNTRL_0_CPUPWRREQ_OE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_CPUPWRREQ_OE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_CPUPWRREQ_OE_DISABLE                 _MK_ENUM_CONST(0)
+#define APBDEV_PMC_CNTRL_0_CPUPWRREQ_OE_ENABLE                  _MK_ENUM_CONST(1)
+
+// Inverts INTR polarity
+#define APBDEV_PMC_CNTRL_0_INTR_POLARITY_SHIFT                  _MK_SHIFT_CONST(17)
+#define APBDEV_PMC_CNTRL_0_INTR_POLARITY_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_PMC_CNTRL_0_INTR_POLARITY_SHIFT)
+#define APBDEV_PMC_CNTRL_0_INTR_POLARITY_RANGE                  17:17
+#define APBDEV_PMC_CNTRL_0_INTR_POLARITY_WOFFSET                        0x0
+#define APBDEV_PMC_CNTRL_0_INTR_POLARITY_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_INTR_POLARITY_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_CNTRL_0_INTR_POLARITY_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_INTR_POLARITY_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_INTR_POLARITY_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDEV_PMC_CNTRL_0_INTR_POLARITY_ENABLE                 _MK_ENUM_CONST(1)
+
+// Fuse override
+#define APBDEV_PMC_CNTRL_0_FUSE_OVERRIDE_SHIFT                  _MK_SHIFT_CONST(18)
+#define APBDEV_PMC_CNTRL_0_FUSE_OVERRIDE_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_PMC_CNTRL_0_FUSE_OVERRIDE_SHIFT)
+#define APBDEV_PMC_CNTRL_0_FUSE_OVERRIDE_RANGE                  18:18
+#define APBDEV_PMC_CNTRL_0_FUSE_OVERRIDE_WOFFSET                        0x0
+#define APBDEV_PMC_CNTRL_0_FUSE_OVERRIDE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_FUSE_OVERRIDE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_CNTRL_0_FUSE_OVERRIDE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_FUSE_OVERRIDE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_FUSE_OVERRIDE_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDEV_PMC_CNTRL_0_FUSE_OVERRIDE_ENABLE                 _MK_ENUM_CONST(1)
+
+
+// Register APBDEV_PMC_SEC_DISABLE_0  
+#define APBDEV_PMC_SEC_DISABLE_0                        _MK_ADDR_CONST(0x4)
+#define APBDEV_PMC_SEC_DISABLE_0_SECURE                         0x0
+#define APBDEV_PMC_SEC_DISABLE_0_WORD_COUNT                     0x1
+#define APBDEV_PMC_SEC_DISABLE_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SEC_DISABLE_0_RESET_MASK                     _MK_MASK_CONST(0xf)
+#define APBDEV_PMC_SEC_DISABLE_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SEC_DISABLE_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SEC_DISABLE_0_READ_MASK                      _MK_MASK_CONST(0xf)
+#define APBDEV_PMC_SEC_DISABLE_0_WRITE_MASK                     _MK_MASK_CONST(0xf)
+// disable write to secure registers
+#define APBDEV_PMC_SEC_DISABLE_0_WRITE_SHIFT                    _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SEC_DISABLE_0_WRITE_FIELD                    (_MK_MASK_CONST(0x1) << APBDEV_PMC_SEC_DISABLE_0_WRITE_SHIFT)
+#define APBDEV_PMC_SEC_DISABLE_0_WRITE_RANGE                    0:0
+#define APBDEV_PMC_SEC_DISABLE_0_WRITE_WOFFSET                  0x0
+#define APBDEV_PMC_SEC_DISABLE_0_WRITE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SEC_DISABLE_0_WRITE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_SEC_DISABLE_0_WRITE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SEC_DISABLE_0_WRITE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SEC_DISABLE_0_WRITE_OFF                      _MK_ENUM_CONST(0)
+#define APBDEV_PMC_SEC_DISABLE_0_WRITE_ON                       _MK_ENUM_CONST(1)
+
+// disable read  from  secure registers
+#define APBDEV_PMC_SEC_DISABLE_0_READ_SHIFT                     _MK_SHIFT_CONST(1)
+#define APBDEV_PMC_SEC_DISABLE_0_READ_FIELD                     (_MK_MASK_CONST(0x1) << APBDEV_PMC_SEC_DISABLE_0_READ_SHIFT)
+#define APBDEV_PMC_SEC_DISABLE_0_READ_RANGE                     1:1
+#define APBDEV_PMC_SEC_DISABLE_0_READ_WOFFSET                   0x0
+#define APBDEV_PMC_SEC_DISABLE_0_READ_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SEC_DISABLE_0_READ_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_SEC_DISABLE_0_READ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SEC_DISABLE_0_READ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SEC_DISABLE_0_READ_OFF                       _MK_ENUM_CONST(0)
+#define APBDEV_PMC_SEC_DISABLE_0_READ_ON                        _MK_ENUM_CONST(1)
+
+// disable write to bondout secure registers
+#define APBDEV_PMC_SEC_DISABLE_0_BWRITE_SHIFT                   _MK_SHIFT_CONST(2)
+#define APBDEV_PMC_SEC_DISABLE_0_BWRITE_FIELD                   (_MK_MASK_CONST(0x1) << APBDEV_PMC_SEC_DISABLE_0_BWRITE_SHIFT)
+#define APBDEV_PMC_SEC_DISABLE_0_BWRITE_RANGE                   2:2
+#define APBDEV_PMC_SEC_DISABLE_0_BWRITE_WOFFSET                 0x0
+#define APBDEV_PMC_SEC_DISABLE_0_BWRITE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SEC_DISABLE_0_BWRITE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_SEC_DISABLE_0_BWRITE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SEC_DISABLE_0_BWRITE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SEC_DISABLE_0_BWRITE_OFF                     _MK_ENUM_CONST(0)
+#define APBDEV_PMC_SEC_DISABLE_0_BWRITE_ON                      _MK_ENUM_CONST(1)
+
+// disable read  from bondout secure registers
+#define APBDEV_PMC_SEC_DISABLE_0_BREAD_SHIFT                    _MK_SHIFT_CONST(3)
+#define APBDEV_PMC_SEC_DISABLE_0_BREAD_FIELD                    (_MK_MASK_CONST(0x1) << APBDEV_PMC_SEC_DISABLE_0_BREAD_SHIFT)
+#define APBDEV_PMC_SEC_DISABLE_0_BREAD_RANGE                    3:3
+#define APBDEV_PMC_SEC_DISABLE_0_BREAD_WOFFSET                  0x0
+#define APBDEV_PMC_SEC_DISABLE_0_BREAD_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SEC_DISABLE_0_BREAD_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_SEC_DISABLE_0_BREAD_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SEC_DISABLE_0_BREAD_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SEC_DISABLE_0_BREAD_OFF                      _MK_ENUM_CONST(0)
+#define APBDEV_PMC_SEC_DISABLE_0_BREAD_ON                       _MK_ENUM_CONST(1)
+
+
+// Register APBDEV_PMC_PMC_SWRST_0  
+#define APBDEV_PMC_PMC_SWRST_0                  _MK_ADDR_CONST(0x8)
+#define APBDEV_PMC_PMC_SWRST_0_SECURE                   0x0
+#define APBDEV_PMC_PMC_SWRST_0_WORD_COUNT                       0x1
+#define APBDEV_PMC_PMC_SWRST_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PMC_SWRST_0_RESET_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PMC_SWRST_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PMC_SWRST_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PMC_SWRST_0_READ_MASK                        _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PMC_SWRST_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
+//software reset to pmc only
+#define APBDEV_PMC_PMC_SWRST_0_RST_SHIFT                        _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_PMC_SWRST_0_RST_FIELD                        (_MK_MASK_CONST(0x1) << APBDEV_PMC_PMC_SWRST_0_RST_SHIFT)
+#define APBDEV_PMC_PMC_SWRST_0_RST_RANGE                        0:0
+#define APBDEV_PMC_PMC_SWRST_0_RST_WOFFSET                      0x0
+#define APBDEV_PMC_PMC_SWRST_0_RST_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PMC_SWRST_0_RST_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PMC_SWRST_0_RST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PMC_SWRST_0_RST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PMC_SWRST_0_RST_DISABLE                      _MK_ENUM_CONST(0)
+#define APBDEV_PMC_PMC_SWRST_0_RST_ENABLE                       _MK_ENUM_CONST(1)
+
+
+// Register APBDEV_PMC_WAKE_MASK_0  
+#define APBDEV_PMC_WAKE_MASK_0                  _MK_ADDR_CONST(0xc)
+#define APBDEV_PMC_WAKE_MASK_0_SECURE                   0x0
+#define APBDEV_PMC_WAKE_MASK_0_WORD_COUNT                       0x1
+#define APBDEV_PMC_WAKE_MASK_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_MASK_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_WAKE_MASK_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_MASK_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_MASK_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_WAKE_MASK_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+// pin  0-15  wake enable      
+#define APBDEV_PMC_WAKE_MASK_0_EVENT_SHIFT                      _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_WAKE_MASK_0_EVENT_FIELD                      (_MK_MASK_CONST(0xffff) << APBDEV_PMC_WAKE_MASK_0_EVENT_SHIFT)
+#define APBDEV_PMC_WAKE_MASK_0_EVENT_RANGE                      15:0
+#define APBDEV_PMC_WAKE_MASK_0_EVENT_WOFFSET                    0x0
+#define APBDEV_PMC_WAKE_MASK_0_EVENT_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_MASK_0_EVENT_DEFAULT_MASK                       _MK_MASK_CONST(0xffff)
+#define APBDEV_PMC_WAKE_MASK_0_EVENT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_MASK_0_EVENT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_MASK_0_EVENT_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_WAKE_MASK_0_EVENT_ENABLE                     _MK_ENUM_CONST(1)
+
+// RTC  wake enable                
+#define APBDEV_PMC_WAKE_MASK_0_RTC_SHIFT                        _MK_SHIFT_CONST(16)
+#define APBDEV_PMC_WAKE_MASK_0_RTC_FIELD                        (_MK_MASK_CONST(0x1) << APBDEV_PMC_WAKE_MASK_0_RTC_SHIFT)
+#define APBDEV_PMC_WAKE_MASK_0_RTC_RANGE                        16:16
+#define APBDEV_PMC_WAKE_MASK_0_RTC_WOFFSET                      0x0
+#define APBDEV_PMC_WAKE_MASK_0_RTC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_MASK_0_RTC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_WAKE_MASK_0_RTC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_MASK_0_RTC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_MASK_0_RTC_DISABLE                      _MK_ENUM_CONST(0)
+#define APBDEV_PMC_WAKE_MASK_0_RTC_ENABLE                       _MK_ENUM_CONST(1)
+
+// KBC  wake  enable                
+#define APBDEV_PMC_WAKE_MASK_0_KBC_SHIFT                        _MK_SHIFT_CONST(17)
+#define APBDEV_PMC_WAKE_MASK_0_KBC_FIELD                        (_MK_MASK_CONST(0x1) << APBDEV_PMC_WAKE_MASK_0_KBC_SHIFT)
+#define APBDEV_PMC_WAKE_MASK_0_KBC_RANGE                        17:17
+#define APBDEV_PMC_WAKE_MASK_0_KBC_WOFFSET                      0x0
+#define APBDEV_PMC_WAKE_MASK_0_KBC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_MASK_0_KBC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_WAKE_MASK_0_KBC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_MASK_0_KBC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_MASK_0_KBC_DISABLE                      _MK_ENUM_CONST(0)
+#define APBDEV_PMC_WAKE_MASK_0_KBC_ENABLE                       _MK_ENUM_CONST(1)
+
+// PWR_INT wake enable               
+#define APBDEV_PMC_WAKE_MASK_0_PWR_INT_SHIFT                    _MK_SHIFT_CONST(18)
+#define APBDEV_PMC_WAKE_MASK_0_PWR_INT_FIELD                    (_MK_MASK_CONST(0x1) << APBDEV_PMC_WAKE_MASK_0_PWR_INT_SHIFT)
+#define APBDEV_PMC_WAKE_MASK_0_PWR_INT_RANGE                    18:18
+#define APBDEV_PMC_WAKE_MASK_0_PWR_INT_WOFFSET                  0x0
+#define APBDEV_PMC_WAKE_MASK_0_PWR_INT_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_MASK_0_PWR_INT_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_WAKE_MASK_0_PWR_INT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_MASK_0_PWR_INT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_MASK_0_PWR_INT_DISABLE                  _MK_ENUM_CONST(0)
+#define APBDEV_PMC_WAKE_MASK_0_PWR_INT_ENABLE                   _MK_ENUM_CONST(1)
+
+#define APBDEV_PMC_WAKE_MASK_0_USB_EVENT_SHIFT                  _MK_SHIFT_CONST(19)
+#define APBDEV_PMC_WAKE_MASK_0_USB_EVENT_FIELD                  (_MK_MASK_CONST(0xf) << APBDEV_PMC_WAKE_MASK_0_USB_EVENT_SHIFT)
+#define APBDEV_PMC_WAKE_MASK_0_USB_EVENT_RANGE                  22:19
+#define APBDEV_PMC_WAKE_MASK_0_USB_EVENT_WOFFSET                        0x0
+#define APBDEV_PMC_WAKE_MASK_0_USB_EVENT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_MASK_0_USB_EVENT_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
+#define APBDEV_PMC_WAKE_MASK_0_USB_EVENT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_MASK_0_USB_EVENT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_MASK_0_USB_EVENT_ACTIVE_LOW                     _MK_ENUM_CONST(0)
+#define APBDEV_PMC_WAKE_MASK_0_USB_EVENT_ACTIVE_HIGH                    _MK_ENUM_CONST(1)
+
+#define APBDEV_PMC_WAKE_MASK_0_EVENT_RES_SHIFT                  _MK_SHIFT_CONST(23)
+#define APBDEV_PMC_WAKE_MASK_0_EVENT_RES_FIELD                  (_MK_MASK_CONST(0xff) << APBDEV_PMC_WAKE_MASK_0_EVENT_RES_SHIFT)
+#define APBDEV_PMC_WAKE_MASK_0_EVENT_RES_RANGE                  30:23
+#define APBDEV_PMC_WAKE_MASK_0_EVENT_RES_WOFFSET                        0x0
+#define APBDEV_PMC_WAKE_MASK_0_EVENT_RES_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_MASK_0_EVENT_RES_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
+#define APBDEV_PMC_WAKE_MASK_0_EVENT_RES_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_MASK_0_EVENT_RES_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_MASK_0_EVENT_RES_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDEV_PMC_WAKE_MASK_0_EVENT_RES_ENABLE                 _MK_ENUM_CONST(1)
+
+// external reset wake enable
+#define APBDEV_PMC_WAKE_MASK_0_RESET_N_SHIFT                    _MK_SHIFT_CONST(31)
+#define APBDEV_PMC_WAKE_MASK_0_RESET_N_FIELD                    (_MK_MASK_CONST(0x1) << APBDEV_PMC_WAKE_MASK_0_RESET_N_SHIFT)
+#define APBDEV_PMC_WAKE_MASK_0_RESET_N_RANGE                    31:31
+#define APBDEV_PMC_WAKE_MASK_0_RESET_N_WOFFSET                  0x0
+#define APBDEV_PMC_WAKE_MASK_0_RESET_N_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_MASK_0_RESET_N_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_WAKE_MASK_0_RESET_N_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_MASK_0_RESET_N_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_MASK_0_RESET_N_DISABLE                  _MK_ENUM_CONST(0)
+#define APBDEV_PMC_WAKE_MASK_0_RESET_N_ENABLE                   _MK_ENUM_CONST(1)
+
+
+// Register APBDEV_PMC_WAKE_LVL_0  
+#define APBDEV_PMC_WAKE_LVL_0                   _MK_ADDR_CONST(0x10)
+#define APBDEV_PMC_WAKE_LVL_0_SECURE                    0x0
+#define APBDEV_PMC_WAKE_LVL_0_WORD_COUNT                        0x1
+#define APBDEV_PMC_WAKE_LVL_0_RESET_VAL                         _MK_MASK_CONST(0x7f9fffff)
+#define APBDEV_PMC_WAKE_LVL_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_WAKE_LVL_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_LVL_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_LVL_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_WAKE_LVL_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
+// pin 0-15 wake  level       
+#define APBDEV_PMC_WAKE_LVL_0_EVENT_SHIFT                       _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_WAKE_LVL_0_EVENT_FIELD                       (_MK_MASK_CONST(0xffff) << APBDEV_PMC_WAKE_LVL_0_EVENT_SHIFT)
+#define APBDEV_PMC_WAKE_LVL_0_EVENT_RANGE                       15:0
+#define APBDEV_PMC_WAKE_LVL_0_EVENT_WOFFSET                     0x0
+#define APBDEV_PMC_WAKE_LVL_0_EVENT_DEFAULT                     _MK_MASK_CONST(0xffff)
+#define APBDEV_PMC_WAKE_LVL_0_EVENT_DEFAULT_MASK                        _MK_MASK_CONST(0xffff)
+#define APBDEV_PMC_WAKE_LVL_0_EVENT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_LVL_0_EVENT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_LVL_0_EVENT_ACTIVE_LOW                  _MK_ENUM_CONST(0)
+#define APBDEV_PMC_WAKE_LVL_0_EVENT_ACTIVE_HIGH                 _MK_ENUM_CONST(1)
+
+// RTC  wake  level               
+#define APBDEV_PMC_WAKE_LVL_0_RTC_SHIFT                 _MK_SHIFT_CONST(16)
+#define APBDEV_PMC_WAKE_LVL_0_RTC_FIELD                 (_MK_MASK_CONST(0x1) << APBDEV_PMC_WAKE_LVL_0_RTC_SHIFT)
+#define APBDEV_PMC_WAKE_LVL_0_RTC_RANGE                 16:16
+#define APBDEV_PMC_WAKE_LVL_0_RTC_WOFFSET                       0x0
+#define APBDEV_PMC_WAKE_LVL_0_RTC_DEFAULT                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_WAKE_LVL_0_RTC_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_WAKE_LVL_0_RTC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_LVL_0_RTC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_LVL_0_RTC_ACTIVE_LOW                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_WAKE_LVL_0_RTC_ACTIVE_HIGH                   _MK_ENUM_CONST(1)
+
+// KBC  wake level                
+#define APBDEV_PMC_WAKE_LVL_0_KBC_SHIFT                 _MK_SHIFT_CONST(17)
+#define APBDEV_PMC_WAKE_LVL_0_KBC_FIELD                 (_MK_MASK_CONST(0x1) << APBDEV_PMC_WAKE_LVL_0_KBC_SHIFT)
+#define APBDEV_PMC_WAKE_LVL_0_KBC_RANGE                 17:17
+#define APBDEV_PMC_WAKE_LVL_0_KBC_WOFFSET                       0x0
+#define APBDEV_PMC_WAKE_LVL_0_KBC_DEFAULT                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_WAKE_LVL_0_KBC_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_WAKE_LVL_0_KBC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_LVL_0_KBC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_LVL_0_KBC_ACTIVE_LOW                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_WAKE_LVL_0_KBC_ACTIVE_HIGH                   _MK_ENUM_CONST(1)
+
+// power interrupt - now pernamently tied to  bit 18            
+#define APBDEV_PMC_WAKE_LVL_0_PWR_INT_SHIFT                     _MK_SHIFT_CONST(18)
+#define APBDEV_PMC_WAKE_LVL_0_PWR_INT_FIELD                     (_MK_MASK_CONST(0x1) << APBDEV_PMC_WAKE_LVL_0_PWR_INT_SHIFT)
+#define APBDEV_PMC_WAKE_LVL_0_PWR_INT_RANGE                     18:18
+#define APBDEV_PMC_WAKE_LVL_0_PWR_INT_WOFFSET                   0x0
+#define APBDEV_PMC_WAKE_LVL_0_PWR_INT_DEFAULT                   _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_WAKE_LVL_0_PWR_INT_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_WAKE_LVL_0_PWR_INT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_LVL_0_PWR_INT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_LVL_0_PWR_INT_ACTIVE_LOW                        _MK_ENUM_CONST(0)
+#define APBDEV_PMC_WAKE_LVL_0_PWR_INT_ACTIVE_HIGH                       _MK_ENUM_CONST(1)
+
+#define APBDEV_PMC_WAKE_LVL_0_USB_EVENT_SHIFT                   _MK_SHIFT_CONST(19)
+#define APBDEV_PMC_WAKE_LVL_0_USB_EVENT_FIELD                   (_MK_MASK_CONST(0xf) << APBDEV_PMC_WAKE_LVL_0_USB_EVENT_SHIFT)
+#define APBDEV_PMC_WAKE_LVL_0_USB_EVENT_RANGE                   22:19
+#define APBDEV_PMC_WAKE_LVL_0_USB_EVENT_WOFFSET                 0x0
+#define APBDEV_PMC_WAKE_LVL_0_USB_EVENT_DEFAULT                 _MK_MASK_CONST(0x3)
+#define APBDEV_PMC_WAKE_LVL_0_USB_EVENT_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define APBDEV_PMC_WAKE_LVL_0_USB_EVENT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_LVL_0_USB_EVENT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_LVL_0_USB_EVENT_ACTIVE_LOW                      _MK_ENUM_CONST(0)
+#define APBDEV_PMC_WAKE_LVL_0_USB_EVENT_ACTIVE_HIGH                     _MK_ENUM_CONST(1)
+
+#define APBDEV_PMC_WAKE_LVL_0_EVENT_RES_SHIFT                   _MK_SHIFT_CONST(23)
+#define APBDEV_PMC_WAKE_LVL_0_EVENT_RES_FIELD                   (_MK_MASK_CONST(0xff) << APBDEV_PMC_WAKE_LVL_0_EVENT_RES_SHIFT)
+#define APBDEV_PMC_WAKE_LVL_0_EVENT_RES_RANGE                   30:23
+#define APBDEV_PMC_WAKE_LVL_0_EVENT_RES_WOFFSET                 0x0
+#define APBDEV_PMC_WAKE_LVL_0_EVENT_RES_DEFAULT                 _MK_MASK_CONST(0xff)
+#define APBDEV_PMC_WAKE_LVL_0_EVENT_RES_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define APBDEV_PMC_WAKE_LVL_0_EVENT_RES_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_LVL_0_EVENT_RES_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_LVL_0_EVENT_RES_ACTIVE_LOW                      _MK_ENUM_CONST(0)
+#define APBDEV_PMC_WAKE_LVL_0_EVENT_RES_ACTIVE_HIGH                     _MK_ENUM_CONST(1)
+
+// external reset wake level (low active!)              
+#define APBDEV_PMC_WAKE_LVL_0_RESET_N_SHIFT                     _MK_SHIFT_CONST(31)
+#define APBDEV_PMC_WAKE_LVL_0_RESET_N_FIELD                     (_MK_MASK_CONST(0x1) << APBDEV_PMC_WAKE_LVL_0_RESET_N_SHIFT)
+#define APBDEV_PMC_WAKE_LVL_0_RESET_N_RANGE                     31:31
+#define APBDEV_PMC_WAKE_LVL_0_RESET_N_WOFFSET                   0x0
+#define APBDEV_PMC_WAKE_LVL_0_RESET_N_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_LVL_0_RESET_N_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_WAKE_LVL_0_RESET_N_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_LVL_0_RESET_N_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_LVL_0_RESET_N_ACTIVE_LOW                        _MK_ENUM_CONST(0)
+#define APBDEV_PMC_WAKE_LVL_0_RESET_N_ACTIVE_HIGH                       _MK_ENUM_CONST(1)
+
+
+// Register APBDEV_PMC_WAKE_STATUS_0  
+#define APBDEV_PMC_WAKE_STATUS_0                        _MK_ADDR_CONST(0x14)
+#define APBDEV_PMC_WAKE_STATUS_0_SECURE                         0x0
+#define APBDEV_PMC_WAKE_STATUS_0_WORD_COUNT                     0x1
+#define APBDEV_PMC_WAKE_STATUS_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_STATUS_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_WAKE_STATUS_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_STATUS_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_STATUS_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_WAKE_STATUS_0_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
+// pin 0-15 wake    
+#define APBDEV_PMC_WAKE_STATUS_0_EVENT_SHIFT                    _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_WAKE_STATUS_0_EVENT_FIELD                    (_MK_MASK_CONST(0xffff) << APBDEV_PMC_WAKE_STATUS_0_EVENT_SHIFT)
+#define APBDEV_PMC_WAKE_STATUS_0_EVENT_RANGE                    15:0
+#define APBDEV_PMC_WAKE_STATUS_0_EVENT_WOFFSET                  0x0
+#define APBDEV_PMC_WAKE_STATUS_0_EVENT_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_STATUS_0_EVENT_DEFAULT_MASK                     _MK_MASK_CONST(0xffff)
+#define APBDEV_PMC_WAKE_STATUS_0_EVENT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_STATUS_0_EVENT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_STATUS_0_EVENT_NOT_SET                  _MK_ENUM_CONST(0)
+#define APBDEV_PMC_WAKE_STATUS_0_EVENT_SET                      _MK_ENUM_CONST(1)
+
+// RTC wake                
+#define APBDEV_PMC_WAKE_STATUS_0_RTC_SHIFT                      _MK_SHIFT_CONST(16)
+#define APBDEV_PMC_WAKE_STATUS_0_RTC_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_PMC_WAKE_STATUS_0_RTC_SHIFT)
+#define APBDEV_PMC_WAKE_STATUS_0_RTC_RANGE                      16:16
+#define APBDEV_PMC_WAKE_STATUS_0_RTC_WOFFSET                    0x0
+#define APBDEV_PMC_WAKE_STATUS_0_RTC_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_STATUS_0_RTC_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_WAKE_STATUS_0_RTC_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_STATUS_0_RTC_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_STATUS_0_RTC_NOT_SET                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_WAKE_STATUS_0_RTC_SET                        _MK_ENUM_CONST(1)
+
+// KBC wake              
+#define APBDEV_PMC_WAKE_STATUS_0_KBC_SHIFT                      _MK_SHIFT_CONST(17)
+#define APBDEV_PMC_WAKE_STATUS_0_KBC_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_PMC_WAKE_STATUS_0_KBC_SHIFT)
+#define APBDEV_PMC_WAKE_STATUS_0_KBC_RANGE                      17:17
+#define APBDEV_PMC_WAKE_STATUS_0_KBC_WOFFSET                    0x0
+#define APBDEV_PMC_WAKE_STATUS_0_KBC_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_STATUS_0_KBC_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_WAKE_STATUS_0_KBC_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_STATUS_0_KBC_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_STATUS_0_KBC_NOT_SET                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_WAKE_STATUS_0_KBC_SET                        _MK_ENUM_CONST(1)
+
+// power interrupt            
+#define APBDEV_PMC_WAKE_STATUS_0_PWR_INT_SHIFT                  _MK_SHIFT_CONST(18)
+#define APBDEV_PMC_WAKE_STATUS_0_PWR_INT_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_PMC_WAKE_STATUS_0_PWR_INT_SHIFT)
+#define APBDEV_PMC_WAKE_STATUS_0_PWR_INT_RANGE                  18:18
+#define APBDEV_PMC_WAKE_STATUS_0_PWR_INT_WOFFSET                        0x0
+#define APBDEV_PMC_WAKE_STATUS_0_PWR_INT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_STATUS_0_PWR_INT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_WAKE_STATUS_0_PWR_INT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_STATUS_0_PWR_INT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_STATUS_0_PWR_INT_NOT_SET                        _MK_ENUM_CONST(0)
+#define APBDEV_PMC_WAKE_STATUS_0_PWR_INT_SET                    _MK_ENUM_CONST(1)
+
+// USB wake events
+#define APBDEV_PMC_WAKE_STATUS_0_USB_EVENT_SHIFT                        _MK_SHIFT_CONST(19)
+#define APBDEV_PMC_WAKE_STATUS_0_USB_EVENT_FIELD                        (_MK_MASK_CONST(0xf) << APBDEV_PMC_WAKE_STATUS_0_USB_EVENT_SHIFT)
+#define APBDEV_PMC_WAKE_STATUS_0_USB_EVENT_RANGE                        22:19
+#define APBDEV_PMC_WAKE_STATUS_0_USB_EVENT_WOFFSET                      0x0
+#define APBDEV_PMC_WAKE_STATUS_0_USB_EVENT_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_STATUS_0_USB_EVENT_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define APBDEV_PMC_WAKE_STATUS_0_USB_EVENT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_STATUS_0_USB_EVENT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_STATUS_0_USB_EVENT_NOT_SET                      _MK_ENUM_CONST(0)
+#define APBDEV_PMC_WAKE_STATUS_0_USB_EVENT_SET                  _MK_ENUM_CONST(1)
+
+#define APBDEV_PMC_WAKE_STATUS_0_EVENT_RES_SHIFT                        _MK_SHIFT_CONST(23)
+#define APBDEV_PMC_WAKE_STATUS_0_EVENT_RES_FIELD                        (_MK_MASK_CONST(0xff) << APBDEV_PMC_WAKE_STATUS_0_EVENT_RES_SHIFT)
+#define APBDEV_PMC_WAKE_STATUS_0_EVENT_RES_RANGE                        30:23
+#define APBDEV_PMC_WAKE_STATUS_0_EVENT_RES_WOFFSET                      0x0
+#define APBDEV_PMC_WAKE_STATUS_0_EVENT_RES_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_STATUS_0_EVENT_RES_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
+#define APBDEV_PMC_WAKE_STATUS_0_EVENT_RES_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_STATUS_0_EVENT_RES_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_STATUS_0_EVENT_RES_NOT_SET                      _MK_ENUM_CONST(0)
+#define APBDEV_PMC_WAKE_STATUS_0_EVENT_RES_SET                  _MK_ENUM_CONST(1)
+
+// external reset            
+#define APBDEV_PMC_WAKE_STATUS_0_RESET_N_SHIFT                  _MK_SHIFT_CONST(31)
+#define APBDEV_PMC_WAKE_STATUS_0_RESET_N_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_PMC_WAKE_STATUS_0_RESET_N_SHIFT)
+#define APBDEV_PMC_WAKE_STATUS_0_RESET_N_RANGE                  31:31
+#define APBDEV_PMC_WAKE_STATUS_0_RESET_N_WOFFSET                        0x0
+#define APBDEV_PMC_WAKE_STATUS_0_RESET_N_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_STATUS_0_RESET_N_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_WAKE_STATUS_0_RESET_N_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_STATUS_0_RESET_N_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_STATUS_0_RESET_N_NOT_SET                        _MK_ENUM_CONST(0)
+#define APBDEV_PMC_WAKE_STATUS_0_RESET_N_SET                    _MK_ENUM_CONST(1)
+
+
+// Register APBDEV_PMC_SW_WAKE_STATUS_0  
+#define APBDEV_PMC_SW_WAKE_STATUS_0                     _MK_ADDR_CONST(0x18)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_SECURE                      0x0
+#define APBDEV_PMC_SW_WAKE_STATUS_0_WORD_COUNT                  0x1
+#define APBDEV_PMC_SW_WAKE_STATUS_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+// pin 0-15 wake    
+#define APBDEV_PMC_SW_WAKE_STATUS_0_EVENT_SHIFT                 _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_EVENT_FIELD                 (_MK_MASK_CONST(0xffff) << APBDEV_PMC_SW_WAKE_STATUS_0_EVENT_SHIFT)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_EVENT_RANGE                 15:0
+#define APBDEV_PMC_SW_WAKE_STATUS_0_EVENT_WOFFSET                       0x0
+#define APBDEV_PMC_SW_WAKE_STATUS_0_EVENT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_EVENT_DEFAULT_MASK                  _MK_MASK_CONST(0xffff)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_EVENT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_EVENT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_EVENT_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_EVENT_ENABLE                        _MK_ENUM_CONST(1)
+
+// RTC wake                
+#define APBDEV_PMC_SW_WAKE_STATUS_0_RTC_SHIFT                   _MK_SHIFT_CONST(16)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_RTC_FIELD                   (_MK_MASK_CONST(0x1) << APBDEV_PMC_SW_WAKE_STATUS_0_RTC_SHIFT)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_RTC_RANGE                   16:16
+#define APBDEV_PMC_SW_WAKE_STATUS_0_RTC_WOFFSET                 0x0
+#define APBDEV_PMC_SW_WAKE_STATUS_0_RTC_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_RTC_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_RTC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_RTC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_RTC_DISABLE                 _MK_ENUM_CONST(0)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_RTC_ENABLE                  _MK_ENUM_CONST(1)
+
+// KBC wake              
+#define APBDEV_PMC_SW_WAKE_STATUS_0_KBC_SHIFT                   _MK_SHIFT_CONST(17)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_KBC_FIELD                   (_MK_MASK_CONST(0x1) << APBDEV_PMC_SW_WAKE_STATUS_0_KBC_SHIFT)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_KBC_RANGE                   17:17
+#define APBDEV_PMC_SW_WAKE_STATUS_0_KBC_WOFFSET                 0x0
+#define APBDEV_PMC_SW_WAKE_STATUS_0_KBC_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_KBC_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_KBC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_KBC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_KBC_DISABLE                 _MK_ENUM_CONST(0)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_KBC_ENABLE                  _MK_ENUM_CONST(1)
+
+// power interrupt            
+#define APBDEV_PMC_SW_WAKE_STATUS_0_PWR_INT_SHIFT                       _MK_SHIFT_CONST(18)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_PWR_INT_FIELD                       (_MK_MASK_CONST(0x1) << APBDEV_PMC_SW_WAKE_STATUS_0_PWR_INT_SHIFT)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_PWR_INT_RANGE                       18:18
+#define APBDEV_PMC_SW_WAKE_STATUS_0_PWR_INT_WOFFSET                     0x0
+#define APBDEV_PMC_SW_WAKE_STATUS_0_PWR_INT_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_PWR_INT_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_PWR_INT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_PWR_INT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_PWR_INT_NOT_SET                     _MK_ENUM_CONST(0)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_PWR_INT_SET                 _MK_ENUM_CONST(1)
+
+// USB wake events
+#define APBDEV_PMC_SW_WAKE_STATUS_0_USB_EVENT_SHIFT                     _MK_SHIFT_CONST(19)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_USB_EVENT_FIELD                     (_MK_MASK_CONST(0xf) << APBDEV_PMC_SW_WAKE_STATUS_0_USB_EVENT_SHIFT)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_USB_EVENT_RANGE                     22:19
+#define APBDEV_PMC_SW_WAKE_STATUS_0_USB_EVENT_WOFFSET                   0x0
+#define APBDEV_PMC_SW_WAKE_STATUS_0_USB_EVENT_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_USB_EVENT_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_USB_EVENT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_USB_EVENT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_USB_EVENT_NOT_SET                   _MK_ENUM_CONST(0)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_USB_EVENT_SET                       _MK_ENUM_CONST(1)
+
+#define APBDEV_PMC_SW_WAKE_STATUS_0_EVENT_RES_SHIFT                     _MK_SHIFT_CONST(23)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_EVENT_RES_FIELD                     (_MK_MASK_CONST(0xff) << APBDEV_PMC_SW_WAKE_STATUS_0_EVENT_RES_SHIFT)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_EVENT_RES_RANGE                     30:23
+#define APBDEV_PMC_SW_WAKE_STATUS_0_EVENT_RES_WOFFSET                   0x0
+#define APBDEV_PMC_SW_WAKE_STATUS_0_EVENT_RES_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_EVENT_RES_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_EVENT_RES_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_EVENT_RES_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_EVENT_RES_NOT_SET                   _MK_ENUM_CONST(0)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_EVENT_RES_SET                       _MK_ENUM_CONST(1)
+
+// external reset            
+#define APBDEV_PMC_SW_WAKE_STATUS_0_RESET_N_SHIFT                       _MK_SHIFT_CONST(31)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_RESET_N_FIELD                       (_MK_MASK_CONST(0x1) << APBDEV_PMC_SW_WAKE_STATUS_0_RESET_N_SHIFT)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_RESET_N_RANGE                       31:31
+#define APBDEV_PMC_SW_WAKE_STATUS_0_RESET_N_WOFFSET                     0x0
+#define APBDEV_PMC_SW_WAKE_STATUS_0_RESET_N_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_RESET_N_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_RESET_N_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_RESET_N_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_RESET_N_NOT_SET                     _MK_ENUM_CONST(0)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_RESET_N_SET                 _MK_ENUM_CONST(1)
+
+
+// Register APBDEV_PMC_DPD_PADS_ORIDE_0  
+#define APBDEV_PMC_DPD_PADS_ORIDE_0                     _MK_ADDR_CONST(0x1c)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_SECURE                      0x0
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_WORD_COUNT                  0x1
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_RESET_VAL                   _MK_MASK_CONST(0x200000)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_RESET_MASK                  _MK_MASK_CONST(0x3ffffff)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_READ_MASK                   _MK_MASK_CONST(0x3ffffff)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_WRITE_MASK                  _MK_MASK_CONST(0x3ffffff)
+//override dpd idle state with column 0 output
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL0_SHIFT                      _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL0_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL0_SHIFT)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL0_RANGE                      0:0
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL0_WOFFSET                    0x0
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL0_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL0_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL0_ENABLE                     _MK_ENUM_CONST(1)
+
+//override dpd idle state with column 1 output
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL1_SHIFT                      _MK_SHIFT_CONST(1)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL1_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL1_SHIFT)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL1_RANGE                      1:1
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL1_WOFFSET                    0x0
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL1_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL1_ENABLE                     _MK_ENUM_CONST(1)
+
+//override dpd idle state with column 2 output
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL2_SHIFT                      _MK_SHIFT_CONST(2)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL2_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL2_SHIFT)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL2_RANGE                      2:2
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL2_WOFFSET                    0x0
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL2_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL2_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL2_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL2_ENABLE                     _MK_ENUM_CONST(1)
+
+//override dpd idle state with column 3 output
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL3_SHIFT                      _MK_SHIFT_CONST(3)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL3_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL3_SHIFT)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL3_RANGE                      3:3
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL3_WOFFSET                    0x0
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL3_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL3_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL3_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL3_ENABLE                     _MK_ENUM_CONST(1)
+
+//override dpd idle state with column 4 output
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL4_SHIFT                      _MK_SHIFT_CONST(4)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL4_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL4_SHIFT)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL4_RANGE                      4:4
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL4_WOFFSET                    0x0
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL4_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL4_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL4_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL4_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL4_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL4_ENABLE                     _MK_ENUM_CONST(1)
+
+//override dpd idle state with column 5 output
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL5_SHIFT                      _MK_SHIFT_CONST(5)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL5_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL5_SHIFT)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL5_RANGE                      5:5
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL5_WOFFSET                    0x0
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL5_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL5_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL5_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL5_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL5_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL5_ENABLE                     _MK_ENUM_CONST(1)
+
+//override dpd idle state with column 6 output
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL6_SHIFT                      _MK_SHIFT_CONST(6)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL6_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL6_SHIFT)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL6_RANGE                      6:6
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL6_WOFFSET                    0x0
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL6_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL6_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL6_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL6_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL6_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL6_ENABLE                     _MK_ENUM_CONST(1)
+
+//override dpd idle state with column 7 output
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL7_SHIFT                      _MK_SHIFT_CONST(7)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL7_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL7_SHIFT)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL7_RANGE                      7:7
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL7_WOFFSET                    0x0
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL7_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL7_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL7_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL7_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL7_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL7_ENABLE                     _MK_ENUM_CONST(1)
+
+//override dpd idle state with column 8 output
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL8_SHIFT                      _MK_SHIFT_CONST(8)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL8_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL8_SHIFT)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL8_RANGE                      8:8
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL8_WOFFSET                    0x0
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL8_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL8_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL8_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL8_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL8_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL8_ENABLE                     _MK_ENUM_CONST(1)
+
+//override dpd idle state with column 9 output
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL9_SHIFT                      _MK_SHIFT_CONST(9)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL9_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL9_SHIFT)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL9_RANGE                      9:9
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL9_WOFFSET                    0x0
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL9_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL9_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL9_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL9_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL9_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL9_ENABLE                     _MK_ENUM_CONST(1)
+
+//override dpd idle state with column 10 output
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL10_SHIFT                     _MK_SHIFT_CONST(10)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL10_FIELD                     (_MK_MASK_CONST(0x1) << APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL10_SHIFT)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL10_RANGE                     10:10
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL10_WOFFSET                   0x0
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL10_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL10_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL10_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL10_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL10_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL10_ENABLE                    _MK_ENUM_CONST(1)
+
+//override dpd idle state with column 11 output
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL11_SHIFT                     _MK_SHIFT_CONST(11)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL11_FIELD                     (_MK_MASK_CONST(0x1) << APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL11_SHIFT)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL11_RANGE                     11:11
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL11_WOFFSET                   0x0
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL11_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL11_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL11_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL11_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL11_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL11_ENABLE                    _MK_ENUM_CONST(1)
+
+//override dpd idle state with column 12 output
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL12_SHIFT                     _MK_SHIFT_CONST(12)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL12_FIELD                     (_MK_MASK_CONST(0x1) << APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL12_SHIFT)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL12_RANGE                     12:12
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL12_WOFFSET                   0x0
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL12_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL12_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL12_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL12_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL12_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL12_ENABLE                    _MK_ENUM_CONST(1)
+
+//override dpd idle state with row 0  output
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW0_SHIFT                      _MK_SHIFT_CONST(13)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW0_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW0_SHIFT)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW0_RANGE                      13:13
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW0_WOFFSET                    0x0
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW0_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW0_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW0_ENABLE                     _MK_ENUM_CONST(1)
+
+//override dpd idle state with row 1  output
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW1_SHIFT                      _MK_SHIFT_CONST(14)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW1_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW1_SHIFT)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW1_RANGE                      14:14
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW1_WOFFSET                    0x0
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW1_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW1_ENABLE                     _MK_ENUM_CONST(1)
+
+//override dpd idle state with row 2  output
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW2_SHIFT                      _MK_SHIFT_CONST(15)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW2_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW2_SHIFT)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW2_RANGE                      15:15
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW2_WOFFSET                    0x0
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW2_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW2_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW2_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW2_ENABLE                     _MK_ENUM_CONST(1)
+
+//override dpd idle state with row 3  output
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW3_SHIFT                      _MK_SHIFT_CONST(16)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW3_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW3_SHIFT)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW3_RANGE                      16:16
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW3_WOFFSET                    0x0
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW3_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW3_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW3_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW3_ENABLE                     _MK_ENUM_CONST(1)
+
+//override dpd idle state with row 4  output
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW4_SHIFT                      _MK_SHIFT_CONST(17)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW4_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW4_SHIFT)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW4_RANGE                      17:17
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW4_WOFFSET                    0x0
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW4_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW4_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW4_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW4_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW4_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW4_ENABLE                     _MK_ENUM_CONST(1)
+
+//override dpd idle state with row 5  output
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW5_SHIFT                      _MK_SHIFT_CONST(18)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW5_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW5_SHIFT)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW5_RANGE                      18:18
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW5_WOFFSET                    0x0
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW5_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW5_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW5_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW5_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW5_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW5_ENABLE                     _MK_ENUM_CONST(1)
+
+//override dpd idle state with row 6  output
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW6_SHIFT                      _MK_SHIFT_CONST(19)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW6_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW6_SHIFT)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW6_RANGE                      19:19
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW6_WOFFSET                    0x0
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW6_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW6_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW6_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW6_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW6_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW6_ENABLE                     _MK_ENUM_CONST(1)
+
+//override dpd idle state with blink ouptut
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_BLINK_SHIFT                 _MK_SHIFT_CONST(20)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_BLINK_FIELD                 (_MK_MASK_CONST(0x1) << APBDEV_PMC_DPD_PADS_ORIDE_0_BLINK_SHIFT)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_BLINK_RANGE                 20:20
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_BLINK_WOFFSET                       0x0
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_BLINK_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_BLINK_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_BLINK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_BLINK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_BLINK_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_BLINK_ENABLE                        _MK_ENUM_CONST(1)
+
+//override dpd idle state with column with sys_clk_request output
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_SYS_CLK_SHIFT                       _MK_SHIFT_CONST(21)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_SYS_CLK_FIELD                       (_MK_MASK_CONST(0x1) << APBDEV_PMC_DPD_PADS_ORIDE_0_SYS_CLK_SHIFT)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_SYS_CLK_RANGE                       21:21
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_SYS_CLK_WOFFSET                     0x0
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_SYS_CLK_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_SYS_CLK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_SYS_CLK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_SYS_CLK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_SYS_CLK_DISABLE                     _MK_ENUM_CONST(0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_SYS_CLK_ENABLE                      _MK_ENUM_CONST(1)
+
+//override dpd idle state with row 7  output
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW7_SHIFT                      _MK_SHIFT_CONST(22)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW7_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW7_SHIFT)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW7_RANGE                      22:22
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW7_WOFFSET                    0x0
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW7_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW7_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW7_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW7_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW7_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW7_ENABLE                     _MK_ENUM_CONST(1)
+
+//override dpd idle state with row 8  output
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW8_SHIFT                      _MK_SHIFT_CONST(23)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW8_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW8_SHIFT)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW8_RANGE                      23:23
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW8_WOFFSET                    0x0
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW8_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW8_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW8_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW8_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW8_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW8_ENABLE                     _MK_ENUM_CONST(1)
+
+//override dpd idle state with row 9  output
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW9_SHIFT                      _MK_SHIFT_CONST(24)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW9_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW9_SHIFT)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW9_RANGE                      24:24
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW9_WOFFSET                    0x0
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW9_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW9_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW9_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW9_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW9_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW9_ENABLE                     _MK_ENUM_CONST(1)
+
+//override dpd idle state with row 10  output
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW10_SHIFT                     _MK_SHIFT_CONST(25)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW10_FIELD                     (_MK_MASK_CONST(0x1) << APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW10_SHIFT)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW10_RANGE                     25:25
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW10_WOFFSET                   0x0
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW10_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW10_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW10_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW10_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW10_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW10_ENABLE                    _MK_ENUM_CONST(1)
+
+
+// Register APBDEV_PMC_DPD_SAMPLE_0  
+#define APBDEV_PMC_DPD_SAMPLE_0                 _MK_ADDR_CONST(0x20)
+#define APBDEV_PMC_DPD_SAMPLE_0_SECURE                  0x0
+#define APBDEV_PMC_DPD_SAMPLE_0_WORD_COUNT                      0x1
+#define APBDEV_PMC_DPD_SAMPLE_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_SAMPLE_0_RESET_MASK                      _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_SAMPLE_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_SAMPLE_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_SAMPLE_0_READ_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_SAMPLE_0_WRITE_MASK                      _MK_MASK_CONST(0x1)
+// will set sampling of pads value
+#define APBDEV_PMC_DPD_SAMPLE_0_ON_SHIFT                        _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_DPD_SAMPLE_0_ON_FIELD                        (_MK_MASK_CONST(0x1) << APBDEV_PMC_DPD_SAMPLE_0_ON_SHIFT)
+#define APBDEV_PMC_DPD_SAMPLE_0_ON_RANGE                        0:0
+#define APBDEV_PMC_DPD_SAMPLE_0_ON_WOFFSET                      0x0
+#define APBDEV_PMC_DPD_SAMPLE_0_ON_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_SAMPLE_0_ON_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_SAMPLE_0_ON_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_SAMPLE_0_ON_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_SAMPLE_0_ON_DISABLE                      _MK_ENUM_CONST(0)
+#define APBDEV_PMC_DPD_SAMPLE_0_ON_ENABLE                       _MK_ENUM_CONST(1)
+
+
+// Register APBDEV_PMC_DPD_ENABLE_0  
+#define APBDEV_PMC_DPD_ENABLE_0                 _MK_ADDR_CONST(0x24)
+#define APBDEV_PMC_DPD_ENABLE_0_SECURE                  0x0
+#define APBDEV_PMC_DPD_ENABLE_0_WORD_COUNT                      0x1
+#define APBDEV_PMC_DPD_ENABLE_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_ENABLE_0_RESET_MASK                      _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_ENABLE_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_ENABLE_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_ENABLE_0_READ_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_ENABLE_0_WRITE_MASK                      _MK_MASK_CONST(0x1)
+// will set sampling of pads value
+#define APBDEV_PMC_DPD_ENABLE_0_ON_SHIFT                        _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_DPD_ENABLE_0_ON_FIELD                        (_MK_MASK_CONST(0x1) << APBDEV_PMC_DPD_ENABLE_0_ON_SHIFT)
+#define APBDEV_PMC_DPD_ENABLE_0_ON_RANGE                        0:0
+#define APBDEV_PMC_DPD_ENABLE_0_ON_WOFFSET                      0x0
+#define APBDEV_PMC_DPD_ENABLE_0_ON_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_ENABLE_0_ON_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_ENABLE_0_ON_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_ENABLE_0_ON_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_ENABLE_0_ON_DISABLE                      _MK_ENUM_CONST(0)
+#define APBDEV_PMC_DPD_ENABLE_0_ON_ENABLE                       _MK_ENUM_CONST(1)
+
+
+// Register APBDEV_PMC_PWRGATE_TIMER_OFF_0  
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0                  _MK_ADDR_CONST(0x28)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_SECURE                   0x0
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_WORD_COUNT                       0x1
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RESET_VAL                        _MK_MASK_CONST(0xeca97531)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+// timer value for rail 0
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL0_SHIFT                      _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL0_FIELD                      (_MK_MASK_CONST(0xf) << APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL0_SHIFT)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL0_RANGE                      3:0
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL0_WOFFSET                    0x0
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL0_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL0_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// timer value for rail 1
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL1_SHIFT                      _MK_SHIFT_CONST(4)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL1_FIELD                      (_MK_MASK_CONST(0xf) << APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL1_SHIFT)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL1_RANGE                      7:4
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL1_WOFFSET                    0x0
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL1_DEFAULT                    _MK_MASK_CONST(0x3)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL1_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// timer value for rail 2
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL2_SHIFT                      _MK_SHIFT_CONST(8)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL2_FIELD                      (_MK_MASK_CONST(0xf) << APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL2_SHIFT)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL2_RANGE                      11:8
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL2_WOFFSET                    0x0
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL2_DEFAULT                    _MK_MASK_CONST(0x5)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL2_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// timer value for rail 3
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL3_SHIFT                      _MK_SHIFT_CONST(12)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL3_FIELD                      (_MK_MASK_CONST(0xf) << APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL3_SHIFT)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL3_RANGE                      15:12
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL3_WOFFSET                    0x0
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL3_DEFAULT                    _MK_MASK_CONST(0x7)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL3_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// timer value for rail 4
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL4_SHIFT                      _MK_SHIFT_CONST(16)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL4_FIELD                      (_MK_MASK_CONST(0xf) << APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL4_SHIFT)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL4_RANGE                      19:16
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL4_WOFFSET                    0x0
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL4_DEFAULT                    _MK_MASK_CONST(0x9)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL4_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL4_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL4_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// timer value for rail 5
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL5_SHIFT                      _MK_SHIFT_CONST(20)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL5_FIELD                      (_MK_MASK_CONST(0xf) << APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL5_SHIFT)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL5_RANGE                      23:20
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL5_WOFFSET                    0x0
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL5_DEFAULT                    _MK_MASK_CONST(0xa)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL5_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL5_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL5_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// timer value for rail 6
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL6_SHIFT                      _MK_SHIFT_CONST(24)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL6_FIELD                      (_MK_MASK_CONST(0xf) << APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL6_SHIFT)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL6_RANGE                      27:24
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL6_WOFFSET                    0x0
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL6_DEFAULT                    _MK_MASK_CONST(0xc)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL6_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL6_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL6_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// timer value for rail 7
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL7_SHIFT                      _MK_SHIFT_CONST(28)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL7_FIELD                      (_MK_MASK_CONST(0xf) << APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL7_SHIFT)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL7_RANGE                      31:28
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL7_WOFFSET                    0x0
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL7_DEFAULT                    _MK_MASK_CONST(0xe)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL7_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL7_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL7_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_PWRGATE_TIMER_ON_0  
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0                   _MK_ADDR_CONST(0x2c)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_SECURE                    0x0
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_WORD_COUNT                        0x1
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RESET_VAL                         _MK_MASK_CONST(0xeca97531)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
+// timer value for rail 0
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL0_SHIFT                       _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL0_FIELD                       (_MK_MASK_CONST(0xf) << APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL0_SHIFT)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL0_RANGE                       3:0
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL0_WOFFSET                     0x0
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL0_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL0_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// timer value for rail 1
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL1_SHIFT                       _MK_SHIFT_CONST(4)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL1_FIELD                       (_MK_MASK_CONST(0xf) << APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL1_SHIFT)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL1_RANGE                       7:4
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL1_WOFFSET                     0x0
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL1_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL1_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// timer value for rail 2
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL2_SHIFT                       _MK_SHIFT_CONST(8)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL2_FIELD                       (_MK_MASK_CONST(0xf) << APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL2_SHIFT)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL2_RANGE                       11:8
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL2_WOFFSET                     0x0
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL2_DEFAULT                     _MK_MASK_CONST(0x5)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL2_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// timer value for rail 3
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL3_SHIFT                       _MK_SHIFT_CONST(12)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL3_FIELD                       (_MK_MASK_CONST(0xf) << APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL3_SHIFT)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL3_RANGE                       15:12
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL3_WOFFSET                     0x0
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL3_DEFAULT                     _MK_MASK_CONST(0x7)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL3_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// timer value for rail 4
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL4_SHIFT                       _MK_SHIFT_CONST(16)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL4_FIELD                       (_MK_MASK_CONST(0xf) << APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL4_SHIFT)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL4_RANGE                       19:16
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL4_WOFFSET                     0x0
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL4_DEFAULT                     _MK_MASK_CONST(0x9)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL4_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// timer value for rail 5
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL5_SHIFT                       _MK_SHIFT_CONST(20)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL5_FIELD                       (_MK_MASK_CONST(0xf) << APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL5_SHIFT)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL5_RANGE                       23:20
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL5_WOFFSET                     0x0
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL5_DEFAULT                     _MK_MASK_CONST(0xa)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL5_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// timer value for rail 6
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL6_SHIFT                       _MK_SHIFT_CONST(24)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL6_FIELD                       (_MK_MASK_CONST(0xf) << APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL6_SHIFT)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL6_RANGE                       27:24
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL6_WOFFSET                     0x0
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL6_DEFAULT                     _MK_MASK_CONST(0xc)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL6_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// timer value for rail 7
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL7_SHIFT                       _MK_SHIFT_CONST(28)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL7_FIELD                       (_MK_MASK_CONST(0xf) << APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL7_SHIFT)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL7_RANGE                       31:28
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL7_WOFFSET                     0x0
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL7_DEFAULT                     _MK_MASK_CONST(0xe)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL7_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_PWRGATE_TOGGLE_0  
+#define APBDEV_PMC_PWRGATE_TOGGLE_0                     _MK_ADDR_CONST(0x30)
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_SECURE                      0x0
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_WORD_COUNT                  0x1
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_RESET_MASK                  _MK_MASK_CONST(0x107)
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_READ_MASK                   _MK_MASK_CONST(0x107)
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_WRITE_MASK                  _MK_MASK_CONST(0x107)
+//id of partition to be toggled 
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_PARTID_SHIFT                        _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_PARTID_FIELD                        (_MK_MASK_CONST(0x7) << APBDEV_PMC_PWRGATE_TOGGLE_0_PARTID_SHIFT)
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_PARTID_RANGE                        2:0
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_PARTID_WOFFSET                      0x0
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_PARTID_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_PARTID_DEFAULT_MASK                 _MK_MASK_CONST(0x7)
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_PARTID_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_PARTID_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_PARTID_CP                   _MK_ENUM_CONST(0)
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_PARTID_TD                   _MK_ENUM_CONST(1)
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_PARTID_VE                   _MK_ENUM_CONST(2)
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_PARTID_VDE                  _MK_ENUM_CONST(4)
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_PARTID_PCX                  _MK_ENUM_CONST(3)
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_PARTID_L2C                  _MK_ENUM_CONST(5)
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_PARTID_MPE                  _MK_ENUM_CONST(6)
+
+//start power down/up
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_START_SHIFT                 _MK_SHIFT_CONST(8)
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_START_FIELD                 (_MK_MASK_CONST(0x1) << APBDEV_PMC_PWRGATE_TOGGLE_0_START_SHIFT)
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_START_RANGE                 8:8
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_START_WOFFSET                       0x0
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_START_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_START_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_START_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_START_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_START_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_START_ENABLE                        _MK_ENUM_CONST(1)
+
+
+// Register APBDEV_PMC_REMOVE_CLAMPING_CMD_0  
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0                        _MK_ADDR_CONST(0x34)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_SECURE                         0x0
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_WORD_COUNT                     0x1
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_RESET_MASK                     _MK_MASK_CONST(0x7f)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_READ_MASK                      _MK_MASK_CONST(0x7f)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_WRITE_MASK                     _MK_MASK_CONST(0x7f)
+//remove clamping to CPU
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_CPU_SHIFT                      _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_CPU_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_PMC_REMOVE_CLAMPING_CMD_0_CPU_SHIFT)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_CPU_RANGE                      0:0
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_CPU_WOFFSET                    0x0
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_CPU_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_CPU_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_CPU_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_CPU_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_CPU_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_CPU_ENABLE                     _MK_ENUM_CONST(1)
+
+//remove clamping to TD
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_TD_SHIFT                       _MK_SHIFT_CONST(1)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_TD_FIELD                       (_MK_MASK_CONST(0x1) << APBDEV_PMC_REMOVE_CLAMPING_CMD_0_TD_SHIFT)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_TD_RANGE                       1:1
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_TD_WOFFSET                     0x0
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_TD_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_TD_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_TD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_TD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_TD_DISABLE                     _MK_ENUM_CONST(0)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_TD_ENABLE                      _MK_ENUM_CONST(1)
+
+//remove clamping to VE
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_VE_SHIFT                       _MK_SHIFT_CONST(2)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_VE_FIELD                       (_MK_MASK_CONST(0x1) << APBDEV_PMC_REMOVE_CLAMPING_CMD_0_VE_SHIFT)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_VE_RANGE                       2:2
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_VE_WOFFSET                     0x0
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_VE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_VE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_VE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_VE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_VE_DISABLE                     _MK_ENUM_CONST(0)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_VE_ENABLE                      _MK_ENUM_CONST(1)
+
+//remove clamping to VDE
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_VDE_SHIFT                      _MK_SHIFT_CONST(3)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_VDE_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_PMC_REMOVE_CLAMPING_CMD_0_VDE_SHIFT)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_VDE_RANGE                      3:3
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_VDE_WOFFSET                    0x0
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_VDE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_VDE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_VDE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_VDE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_VDE_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_VDE_ENABLE                     _MK_ENUM_CONST(1)
+
+//remove clamping to PCX
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_PCX_SHIFT                      _MK_SHIFT_CONST(4)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_PCX_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_PMC_REMOVE_CLAMPING_CMD_0_PCX_SHIFT)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_PCX_RANGE                      4:4
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_PCX_WOFFSET                    0x0
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_PCX_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_PCX_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_PCX_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_PCX_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_PCX_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_PCX_ENABLE                     _MK_ENUM_CONST(1)
+
+//remove clamping to L2_CACHE
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_L2C_SHIFT                      _MK_SHIFT_CONST(5)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_L2C_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_PMC_REMOVE_CLAMPING_CMD_0_L2C_SHIFT)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_L2C_RANGE                      5:5
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_L2C_WOFFSET                    0x0
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_L2C_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_L2C_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_L2C_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_L2C_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_L2C_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_L2C_ENABLE                     _MK_ENUM_CONST(1)
+
+//remove clamping to MPE_CACHE
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_MPE_SHIFT                      _MK_SHIFT_CONST(6)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_MPE_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_PMC_REMOVE_CLAMPING_CMD_0_MPE_SHIFT)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_MPE_RANGE                      6:6
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_MPE_WOFFSET                    0x0
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_MPE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_MPE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_MPE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_MPE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_MPE_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_MPE_ENABLE                     _MK_ENUM_CONST(1)
+
+
+// Register APBDEV_PMC_PWRGATE_STATUS_0  
+#define APBDEV_PMC_PWRGATE_STATUS_0                     _MK_ADDR_CONST(0x38)
+#define APBDEV_PMC_PWRGATE_STATUS_0_SECURE                      0x0
+#define APBDEV_PMC_PWRGATE_STATUS_0_WORD_COUNT                  0x1
+#define APBDEV_PMC_PWRGATE_STATUS_0_RESET_VAL                   _MK_MASK_CONST(0x7f)
+#define APBDEV_PMC_PWRGATE_STATUS_0_RESET_MASK                  _MK_MASK_CONST(0x7f)
+#define APBDEV_PMC_PWRGATE_STATUS_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_STATUS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_STATUS_0_READ_MASK                   _MK_MASK_CONST(0x7f)
+#define APBDEV_PMC_PWRGATE_STATUS_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+//status of CPU partition
+#define APBDEV_PMC_PWRGATE_STATUS_0_CPU_SHIFT                   _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_PWRGATE_STATUS_0_CPU_FIELD                   (_MK_MASK_CONST(0x1) << APBDEV_PMC_PWRGATE_STATUS_0_CPU_SHIFT)
+#define APBDEV_PMC_PWRGATE_STATUS_0_CPU_RANGE                   0:0
+#define APBDEV_PMC_PWRGATE_STATUS_0_CPU_WOFFSET                 0x0
+#define APBDEV_PMC_PWRGATE_STATUS_0_CPU_DEFAULT                 _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWRGATE_STATUS_0_CPU_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWRGATE_STATUS_0_CPU_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_STATUS_0_CPU_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_STATUS_0_CPU_OFF                     _MK_ENUM_CONST(0)
+#define APBDEV_PMC_PWRGATE_STATUS_0_CPU_ON                      _MK_ENUM_CONST(1)
+
+//status of TD  Partition
+#define APBDEV_PMC_PWRGATE_STATUS_0_TD_SHIFT                    _MK_SHIFT_CONST(1)
+#define APBDEV_PMC_PWRGATE_STATUS_0_TD_FIELD                    (_MK_MASK_CONST(0x1) << APBDEV_PMC_PWRGATE_STATUS_0_TD_SHIFT)
+#define APBDEV_PMC_PWRGATE_STATUS_0_TD_RANGE                    1:1
+#define APBDEV_PMC_PWRGATE_STATUS_0_TD_WOFFSET                  0x0
+#define APBDEV_PMC_PWRGATE_STATUS_0_TD_DEFAULT                  _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWRGATE_STATUS_0_TD_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWRGATE_STATUS_0_TD_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_STATUS_0_TD_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_STATUS_0_TD_OFF                      _MK_ENUM_CONST(0)
+#define APBDEV_PMC_PWRGATE_STATUS_0_TD_ON                       _MK_ENUM_CONST(1)
+
+//status of VE  partition
+#define APBDEV_PMC_PWRGATE_STATUS_0_VE_SHIFT                    _MK_SHIFT_CONST(2)
+#define APBDEV_PMC_PWRGATE_STATUS_0_VE_FIELD                    (_MK_MASK_CONST(0x1) << APBDEV_PMC_PWRGATE_STATUS_0_VE_SHIFT)
+#define APBDEV_PMC_PWRGATE_STATUS_0_VE_RANGE                    2:2
+#define APBDEV_PMC_PWRGATE_STATUS_0_VE_WOFFSET                  0x0
+#define APBDEV_PMC_PWRGATE_STATUS_0_VE_DEFAULT                  _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWRGATE_STATUS_0_VE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWRGATE_STATUS_0_VE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_STATUS_0_VE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_STATUS_0_VE_OFF                      _MK_ENUM_CONST(0)
+#define APBDEV_PMC_PWRGATE_STATUS_0_VE_ON                       _MK_ENUM_CONST(1)
+
+//status of VDE  partition
+#define APBDEV_PMC_PWRGATE_STATUS_0_VDE_SHIFT                   _MK_SHIFT_CONST(4)
+#define APBDEV_PMC_PWRGATE_STATUS_0_VDE_FIELD                   (_MK_MASK_CONST(0x1) << APBDEV_PMC_PWRGATE_STATUS_0_VDE_SHIFT)
+#define APBDEV_PMC_PWRGATE_STATUS_0_VDE_RANGE                   4:4
+#define APBDEV_PMC_PWRGATE_STATUS_0_VDE_WOFFSET                 0x0
+#define APBDEV_PMC_PWRGATE_STATUS_0_VDE_DEFAULT                 _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWRGATE_STATUS_0_VDE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWRGATE_STATUS_0_VDE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_STATUS_0_VDE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_STATUS_0_VDE_OFF                     _MK_ENUM_CONST(0)
+#define APBDEV_PMC_PWRGATE_STATUS_0_VDE_ON                      _MK_ENUM_CONST(1)
+
+//status of PCX  partition
+#define APBDEV_PMC_PWRGATE_STATUS_0_PCX_SHIFT                   _MK_SHIFT_CONST(3)
+#define APBDEV_PMC_PWRGATE_STATUS_0_PCX_FIELD                   (_MK_MASK_CONST(0x1) << APBDEV_PMC_PWRGATE_STATUS_0_PCX_SHIFT)
+#define APBDEV_PMC_PWRGATE_STATUS_0_PCX_RANGE                   3:3
+#define APBDEV_PMC_PWRGATE_STATUS_0_PCX_WOFFSET                 0x0
+#define APBDEV_PMC_PWRGATE_STATUS_0_PCX_DEFAULT                 _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWRGATE_STATUS_0_PCX_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWRGATE_STATUS_0_PCX_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_STATUS_0_PCX_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_STATUS_0_PCX_OFF                     _MK_ENUM_CONST(0)
+#define APBDEV_PMC_PWRGATE_STATUS_0_PCX_ON                      _MK_ENUM_CONST(1)
+
+//status of L2C  partition
+#define APBDEV_PMC_PWRGATE_STATUS_0_L2C_SHIFT                   _MK_SHIFT_CONST(5)
+#define APBDEV_PMC_PWRGATE_STATUS_0_L2C_FIELD                   (_MK_MASK_CONST(0x1) << APBDEV_PMC_PWRGATE_STATUS_0_L2C_SHIFT)
+#define APBDEV_PMC_PWRGATE_STATUS_0_L2C_RANGE                   5:5
+#define APBDEV_PMC_PWRGATE_STATUS_0_L2C_WOFFSET                 0x0
+#define APBDEV_PMC_PWRGATE_STATUS_0_L2C_DEFAULT                 _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWRGATE_STATUS_0_L2C_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWRGATE_STATUS_0_L2C_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_STATUS_0_L2C_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_STATUS_0_L2C_OFF                     _MK_ENUM_CONST(0)
+#define APBDEV_PMC_PWRGATE_STATUS_0_L2C_ON                      _MK_ENUM_CONST(1)
+
+//status of MPE  partition
+#define APBDEV_PMC_PWRGATE_STATUS_0_MPE_SHIFT                   _MK_SHIFT_CONST(6)
+#define APBDEV_PMC_PWRGATE_STATUS_0_MPE_FIELD                   (_MK_MASK_CONST(0x1) << APBDEV_PMC_PWRGATE_STATUS_0_MPE_SHIFT)
+#define APBDEV_PMC_PWRGATE_STATUS_0_MPE_RANGE                   6:6
+#define APBDEV_PMC_PWRGATE_STATUS_0_MPE_WOFFSET                 0x0
+#define APBDEV_PMC_PWRGATE_STATUS_0_MPE_DEFAULT                 _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWRGATE_STATUS_0_MPE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWRGATE_STATUS_0_MPE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_STATUS_0_MPE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_STATUS_0_MPE_OFF                     _MK_ENUM_CONST(0)
+#define APBDEV_PMC_PWRGATE_STATUS_0_MPE_ON                      _MK_ENUM_CONST(1)
+
+
+// Register APBDEV_PMC_PWRGOOD_TIMER_0  
+#define APBDEV_PMC_PWRGOOD_TIMER_0                      _MK_ADDR_CONST(0x3c)
+#define APBDEV_PMC_PWRGOOD_TIMER_0_SECURE                       0x0
+#define APBDEV_PMC_PWRGOOD_TIMER_0_WORD_COUNT                   0x1
+#define APBDEV_PMC_PWRGOOD_TIMER_0_RESET_VAL                    _MK_MASK_CONST(0x7f)
+#define APBDEV_PMC_PWRGOOD_TIMER_0_RESET_MASK                   _MK_MASK_CONST(0xffff)
+#define APBDEV_PMC_PWRGOOD_TIMER_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGOOD_TIMER_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGOOD_TIMER_0_READ_MASK                    _MK_MASK_CONST(0xffff)
+#define APBDEV_PMC_PWRGOOD_TIMER_0_WRITE_MASK                   _MK_MASK_CONST(0xffff)
+// pmu timer * 32
+#define APBDEV_PMC_PWRGOOD_TIMER_0_PMU_TIM_SHIFT                        _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_PWRGOOD_TIMER_0_PMU_TIM_FIELD                        (_MK_MASK_CONST(0xff) << APBDEV_PMC_PWRGOOD_TIMER_0_PMU_TIM_SHIFT)
+#define APBDEV_PMC_PWRGOOD_TIMER_0_PMU_TIM_RANGE                        7:0
+#define APBDEV_PMC_PWRGOOD_TIMER_0_PMU_TIM_WOFFSET                      0x0
+#define APBDEV_PMC_PWRGOOD_TIMER_0_PMU_TIM_DEFAULT                      _MK_MASK_CONST(0x7f)
+#define APBDEV_PMC_PWRGOOD_TIMER_0_PMU_TIM_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
+#define APBDEV_PMC_PWRGOOD_TIMER_0_PMU_TIM_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGOOD_TIMER_0_PMU_TIM_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// xtal timer * 32
+#define APBDEV_PMC_PWRGOOD_TIMER_0_DATA_SHIFT                   _MK_SHIFT_CONST(8)
+#define APBDEV_PMC_PWRGOOD_TIMER_0_DATA_FIELD                   (_MK_MASK_CONST(0xff) << APBDEV_PMC_PWRGOOD_TIMER_0_DATA_SHIFT)
+#define APBDEV_PMC_PWRGOOD_TIMER_0_DATA_RANGE                   15:8
+#define APBDEV_PMC_PWRGOOD_TIMER_0_DATA_WOFFSET                 0x0
+#define APBDEV_PMC_PWRGOOD_TIMER_0_DATA_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGOOD_TIMER_0_DATA_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define APBDEV_PMC_PWRGOOD_TIMER_0_DATA_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGOOD_TIMER_0_DATA_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_BLINK_TIMER_0  
+#define APBDEV_PMC_BLINK_TIMER_0                        _MK_ADDR_CONST(0x40)
+#define APBDEV_PMC_BLINK_TIMER_0_SECURE                         0x0
+#define APBDEV_PMC_BLINK_TIMER_0_WORD_COUNT                     0x1
+#define APBDEV_PMC_BLINK_TIMER_0_RESET_VAL                      _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_BLINK_TIMER_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_BLINK_TIMER_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_BLINK_TIMER_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_BLINK_TIMER_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_BLINK_TIMER_0_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
+// time on 
+#define APBDEV_PMC_BLINK_TIMER_0_DATA_ON_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_BLINK_TIMER_0_DATA_ON_FIELD                  (_MK_MASK_CONST(0x7fff) << APBDEV_PMC_BLINK_TIMER_0_DATA_ON_SHIFT)
+#define APBDEV_PMC_BLINK_TIMER_0_DATA_ON_RANGE                  14:0
+#define APBDEV_PMC_BLINK_TIMER_0_DATA_ON_WOFFSET                        0x0
+#define APBDEV_PMC_BLINK_TIMER_0_DATA_ON_DEFAULT                        _MK_MASK_CONST(0xffff)
+#define APBDEV_PMC_BLINK_TIMER_0_DATA_ON_DEFAULT_MASK                   _MK_MASK_CONST(0x7fff)
+#define APBDEV_PMC_BLINK_TIMER_0_DATA_ON_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_BLINK_TIMER_0_DATA_ON_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// if 0 32khz clock 
+#define APBDEV_PMC_BLINK_TIMER_0_FORCE_BLINK_SHIFT                      _MK_SHIFT_CONST(15)
+#define APBDEV_PMC_BLINK_TIMER_0_FORCE_BLINK_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_PMC_BLINK_TIMER_0_FORCE_BLINK_SHIFT)
+#define APBDEV_PMC_BLINK_TIMER_0_FORCE_BLINK_RANGE                      15:15
+#define APBDEV_PMC_BLINK_TIMER_0_FORCE_BLINK_WOFFSET                    0x0
+#define APBDEV_PMC_BLINK_TIMER_0_FORCE_BLINK_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_BLINK_TIMER_0_FORCE_BLINK_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_BLINK_TIMER_0_FORCE_BLINK_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_BLINK_TIMER_0_FORCE_BLINK_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// time off         
+#define APBDEV_PMC_BLINK_TIMER_0_DATA_OFF_SHIFT                 _MK_SHIFT_CONST(16)
+#define APBDEV_PMC_BLINK_TIMER_0_DATA_OFF_FIELD                 (_MK_MASK_CONST(0xffff) << APBDEV_PMC_BLINK_TIMER_0_DATA_OFF_SHIFT)
+#define APBDEV_PMC_BLINK_TIMER_0_DATA_OFF_RANGE                 31:16
+#define APBDEV_PMC_BLINK_TIMER_0_DATA_OFF_WOFFSET                       0x0
+#define APBDEV_PMC_BLINK_TIMER_0_DATA_OFF_DEFAULT                       _MK_MASK_CONST(0xffff)
+#define APBDEV_PMC_BLINK_TIMER_0_DATA_OFF_DEFAULT_MASK                  _MK_MASK_CONST(0xffff)
+#define APBDEV_PMC_BLINK_TIMER_0_DATA_OFF_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_BLINK_TIMER_0_DATA_OFF_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_NO_IOPOWER_0  
+#define APBDEV_PMC_NO_IOPOWER_0                 _MK_ADDR_CONST(0x44)
+#define APBDEV_PMC_NO_IOPOWER_0_SECURE                  0x0
+#define APBDEV_PMC_NO_IOPOWER_0_WORD_COUNT                      0x1
+#define APBDEV_PMC_NO_IOPOWER_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_RESET_MASK                      _MK_MASK_CONST(0x3ff)
+#define APBDEV_PMC_NO_IOPOWER_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_READ_MASK                       _MK_MASK_CONST(0x3ff)
+#define APBDEV_PMC_NO_IOPOWER_0_WRITE_MASK                      _MK_MASK_CONST(0x3ff)
+//rail ao IOs   
+#define APBDEV_PMC_NO_IOPOWER_0_SYS_SHIFT                       _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_NO_IOPOWER_0_SYS_FIELD                       (_MK_MASK_CONST(0x1) << APBDEV_PMC_NO_IOPOWER_0_SYS_SHIFT)
+#define APBDEV_PMC_NO_IOPOWER_0_SYS_RANGE                       0:0
+#define APBDEV_PMC_NO_IOPOWER_0_SYS_WOFFSET                     0x0
+#define APBDEV_PMC_NO_IOPOWER_0_SYS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_SYS_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_NO_IOPOWER_0_SYS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_SYS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_SYS_DISABLE                     _MK_ENUM_CONST(0)
+#define APBDEV_PMC_NO_IOPOWER_0_SYS_ENABLE                      _MK_ENUM_CONST(1)
+
+//rail at3 IOs 
+#define APBDEV_PMC_NO_IOPOWER_0_NAND_SHIFT                      _MK_SHIFT_CONST(1)
+#define APBDEV_PMC_NO_IOPOWER_0_NAND_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_PMC_NO_IOPOWER_0_NAND_SHIFT)
+#define APBDEV_PMC_NO_IOPOWER_0_NAND_RANGE                      1:1
+#define APBDEV_PMC_NO_IOPOWER_0_NAND_WOFFSET                    0x0
+#define APBDEV_PMC_NO_IOPOWER_0_NAND_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_NAND_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_NO_IOPOWER_0_NAND_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_NAND_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_NAND_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_NO_IOPOWER_0_NAND_ENABLE                     _MK_ENUM_CONST(1)
+
+//rail dbg IOs   
+#define APBDEV_PMC_NO_IOPOWER_0_UART_SHIFT                      _MK_SHIFT_CONST(2)
+#define APBDEV_PMC_NO_IOPOWER_0_UART_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_PMC_NO_IOPOWER_0_UART_SHIFT)
+#define APBDEV_PMC_NO_IOPOWER_0_UART_RANGE                      2:2
+#define APBDEV_PMC_NO_IOPOWER_0_UART_WOFFSET                    0x0
+#define APBDEV_PMC_NO_IOPOWER_0_UART_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_UART_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_NO_IOPOWER_0_UART_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_UART_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_UART_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_NO_IOPOWER_0_UART_ENABLE                     _MK_ENUM_CONST(1)
+
+//rail dlcd IOs   
+#define APBDEV_PMC_NO_IOPOWER_0_BB_SHIFT                        _MK_SHIFT_CONST(3)
+#define APBDEV_PMC_NO_IOPOWER_0_BB_FIELD                        (_MK_MASK_CONST(0x1) << APBDEV_PMC_NO_IOPOWER_0_BB_SHIFT)
+#define APBDEV_PMC_NO_IOPOWER_0_BB_RANGE                        3:3
+#define APBDEV_PMC_NO_IOPOWER_0_BB_WOFFSET                      0x0
+#define APBDEV_PMC_NO_IOPOWER_0_BB_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_BB_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_NO_IOPOWER_0_BB_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_BB_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_BB_DISABLE                      _MK_ENUM_CONST(0)
+#define APBDEV_PMC_NO_IOPOWER_0_BB_ENABLE                       _MK_ENUM_CONST(1)
+
+//rail dvi IOs   
+#define APBDEV_PMC_NO_IOPOWER_0_VI_SHIFT                        _MK_SHIFT_CONST(4)
+#define APBDEV_PMC_NO_IOPOWER_0_VI_FIELD                        (_MK_MASK_CONST(0x1) << APBDEV_PMC_NO_IOPOWER_0_VI_SHIFT)
+#define APBDEV_PMC_NO_IOPOWER_0_VI_RANGE                        4:4
+#define APBDEV_PMC_NO_IOPOWER_0_VI_WOFFSET                      0x0
+#define APBDEV_PMC_NO_IOPOWER_0_VI_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_VI_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_NO_IOPOWER_0_VI_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_VI_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_VI_DISABLE                      _MK_ENUM_CONST(0)
+#define APBDEV_PMC_NO_IOPOWER_0_VI_ENABLE                       _MK_ENUM_CONST(1)
+
+//rail i2s IOs   
+#define APBDEV_PMC_NO_IOPOWER_0_AUDIO_SHIFT                     _MK_SHIFT_CONST(5)
+#define APBDEV_PMC_NO_IOPOWER_0_AUDIO_FIELD                     (_MK_MASK_CONST(0x1) << APBDEV_PMC_NO_IOPOWER_0_AUDIO_SHIFT)
+#define APBDEV_PMC_NO_IOPOWER_0_AUDIO_RANGE                     5:5
+#define APBDEV_PMC_NO_IOPOWER_0_AUDIO_WOFFSET                   0x0
+#define APBDEV_PMC_NO_IOPOWER_0_AUDIO_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_AUDIO_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_NO_IOPOWER_0_AUDIO_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_AUDIO_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_AUDIO_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDEV_PMC_NO_IOPOWER_0_AUDIO_ENABLE                    _MK_ENUM_CONST(1)
+
+//rail lcd IOs   
+#define APBDEV_PMC_NO_IOPOWER_0_LCD_SHIFT                       _MK_SHIFT_CONST(6)
+#define APBDEV_PMC_NO_IOPOWER_0_LCD_FIELD                       (_MK_MASK_CONST(0x1) << APBDEV_PMC_NO_IOPOWER_0_LCD_SHIFT)
+#define APBDEV_PMC_NO_IOPOWER_0_LCD_RANGE                       6:6
+#define APBDEV_PMC_NO_IOPOWER_0_LCD_WOFFSET                     0x0
+#define APBDEV_PMC_NO_IOPOWER_0_LCD_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_LCD_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_NO_IOPOWER_0_LCD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_LCD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_LCD_DISABLE                     _MK_ENUM_CONST(0)
+#define APBDEV_PMC_NO_IOPOWER_0_LCD_ENABLE                      _MK_ENUM_CONST(1)
+
+//rail mem IOs   
+#define APBDEV_PMC_NO_IOPOWER_0_MEM_SHIFT                       _MK_SHIFT_CONST(7)
+#define APBDEV_PMC_NO_IOPOWER_0_MEM_FIELD                       (_MK_MASK_CONST(0x1) << APBDEV_PMC_NO_IOPOWER_0_MEM_SHIFT)
+#define APBDEV_PMC_NO_IOPOWER_0_MEM_RANGE                       7:7
+#define APBDEV_PMC_NO_IOPOWER_0_MEM_WOFFSET                     0x0
+#define APBDEV_PMC_NO_IOPOWER_0_MEM_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_MEM_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_NO_IOPOWER_0_MEM_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_MEM_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_MEM_DISABLE                     _MK_ENUM_CONST(0)
+#define APBDEV_PMC_NO_IOPOWER_0_MEM_ENABLE                      _MK_ENUM_CONST(1)
+
+//rail sd IOs   
+#define APBDEV_PMC_NO_IOPOWER_0_SD_SHIFT                        _MK_SHIFT_CONST(8)
+#define APBDEV_PMC_NO_IOPOWER_0_SD_FIELD                        (_MK_MASK_CONST(0x1) << APBDEV_PMC_NO_IOPOWER_0_SD_SHIFT)
+#define APBDEV_PMC_NO_IOPOWER_0_SD_RANGE                        8:8
+#define APBDEV_PMC_NO_IOPOWER_0_SD_WOFFSET                      0x0
+#define APBDEV_PMC_NO_IOPOWER_0_SD_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_SD_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_NO_IOPOWER_0_SD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_SD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_SD_DISABLE                      _MK_ENUM_CONST(0)
+#define APBDEV_PMC_NO_IOPOWER_0_SD_ENABLE                       _MK_ENUM_CONST(1)
+
+//rail mipi IOs   
+#define APBDEV_PMC_NO_IOPOWER_0_MIPI_SHIFT                      _MK_SHIFT_CONST(9)
+#define APBDEV_PMC_NO_IOPOWER_0_MIPI_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_PMC_NO_IOPOWER_0_MIPI_SHIFT)
+#define APBDEV_PMC_NO_IOPOWER_0_MIPI_RANGE                      9:9
+#define APBDEV_PMC_NO_IOPOWER_0_MIPI_WOFFSET                    0x0
+#define APBDEV_PMC_NO_IOPOWER_0_MIPI_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_MIPI_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_NO_IOPOWER_0_MIPI_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_MIPI_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_MIPI_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_NO_IOPOWER_0_MIPI_ENABLE                     _MK_ENUM_CONST(1)
+
+
+// Register APBDEV_PMC_PWR_DET_0  
+#define APBDEV_PMC_PWR_DET_0                    _MK_ADDR_CONST(0x48)
+#define APBDEV_PMC_PWR_DET_0_SECURE                     0x0
+#define APBDEV_PMC_PWR_DET_0_WORD_COUNT                         0x1
+#define APBDEV_PMC_PWR_DET_0_RESET_VAL                  _MK_MASK_CONST(0x1ff)
+#define APBDEV_PMC_PWR_DET_0_RESET_MASK                         _MK_MASK_CONST(0x1ff)
+#define APBDEV_PMC_PWR_DET_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_0_READ_MASK                  _MK_MASK_CONST(0x1ff)
+#define APBDEV_PMC_PWR_DET_0_WRITE_MASK                         _MK_MASK_CONST(0x1ff)
+//rail ao IOs   
+#define APBDEV_PMC_PWR_DET_0_SYS_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_PWR_DET_0_SYS_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_PMC_PWR_DET_0_SYS_SHIFT)
+#define APBDEV_PMC_PWR_DET_0_SYS_RANGE                  0:0
+#define APBDEV_PMC_PWR_DET_0_SYS_WOFFSET                        0x0
+#define APBDEV_PMC_PWR_DET_0_SYS_DEFAULT                        _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_0_SYS_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_0_SYS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_0_SYS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_0_SYS_ENABLE                 _MK_ENUM_CONST(0)
+#define APBDEV_PMC_PWR_DET_0_SYS_DISABLE                        _MK_ENUM_CONST(1)
+
+//rail at3 IOs 
+#define APBDEV_PMC_PWR_DET_0_NAND_SHIFT                 _MK_SHIFT_CONST(1)
+#define APBDEV_PMC_PWR_DET_0_NAND_FIELD                 (_MK_MASK_CONST(0x1) << APBDEV_PMC_PWR_DET_0_NAND_SHIFT)
+#define APBDEV_PMC_PWR_DET_0_NAND_RANGE                 1:1
+#define APBDEV_PMC_PWR_DET_0_NAND_WOFFSET                       0x0
+#define APBDEV_PMC_PWR_DET_0_NAND_DEFAULT                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_0_NAND_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_0_NAND_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_0_NAND_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_0_NAND_ENABLE                        _MK_ENUM_CONST(0)
+#define APBDEV_PMC_PWR_DET_0_NAND_DISABLE                       _MK_ENUM_CONST(1)
+
+//rail dbg IOs   
+#define APBDEV_PMC_PWR_DET_0_UART_SHIFT                 _MK_SHIFT_CONST(2)
+#define APBDEV_PMC_PWR_DET_0_UART_FIELD                 (_MK_MASK_CONST(0x1) << APBDEV_PMC_PWR_DET_0_UART_SHIFT)
+#define APBDEV_PMC_PWR_DET_0_UART_RANGE                 2:2
+#define APBDEV_PMC_PWR_DET_0_UART_WOFFSET                       0x0
+#define APBDEV_PMC_PWR_DET_0_UART_DEFAULT                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_0_UART_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_0_UART_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_0_UART_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_0_UART_ENABLE                        _MK_ENUM_CONST(0)
+#define APBDEV_PMC_PWR_DET_0_UART_DISABLE                       _MK_ENUM_CONST(1)
+
+//rail dlcd IOs   
+#define APBDEV_PMC_PWR_DET_0_BB_SHIFT                   _MK_SHIFT_CONST(3)
+#define APBDEV_PMC_PWR_DET_0_BB_FIELD                   (_MK_MASK_CONST(0x1) << APBDEV_PMC_PWR_DET_0_BB_SHIFT)
+#define APBDEV_PMC_PWR_DET_0_BB_RANGE                   3:3
+#define APBDEV_PMC_PWR_DET_0_BB_WOFFSET                 0x0
+#define APBDEV_PMC_PWR_DET_0_BB_DEFAULT                 _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_0_BB_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_0_BB_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_0_BB_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_0_BB_ENABLE                  _MK_ENUM_CONST(0)
+#define APBDEV_PMC_PWR_DET_0_BB_DISABLE                 _MK_ENUM_CONST(1)
+
+//rail dvi IOs   
+#define APBDEV_PMC_PWR_DET_0_VI_SHIFT                   _MK_SHIFT_CONST(4)
+#define APBDEV_PMC_PWR_DET_0_VI_FIELD                   (_MK_MASK_CONST(0x1) << APBDEV_PMC_PWR_DET_0_VI_SHIFT)
+#define APBDEV_PMC_PWR_DET_0_VI_RANGE                   4:4
+#define APBDEV_PMC_PWR_DET_0_VI_WOFFSET                 0x0
+#define APBDEV_PMC_PWR_DET_0_VI_DEFAULT                 _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_0_VI_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_0_VI_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_0_VI_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_0_VI_ENABLE                  _MK_ENUM_CONST(0)
+#define APBDEV_PMC_PWR_DET_0_VI_DISABLE                 _MK_ENUM_CONST(1)
+
+//rail i2s IOs   
+#define APBDEV_PMC_PWR_DET_0_AUDIO_SHIFT                        _MK_SHIFT_CONST(5)
+#define APBDEV_PMC_PWR_DET_0_AUDIO_FIELD                        (_MK_MASK_CONST(0x1) << APBDEV_PMC_PWR_DET_0_AUDIO_SHIFT)
+#define APBDEV_PMC_PWR_DET_0_AUDIO_RANGE                        5:5
+#define APBDEV_PMC_PWR_DET_0_AUDIO_WOFFSET                      0x0
+#define APBDEV_PMC_PWR_DET_0_AUDIO_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_0_AUDIO_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_0_AUDIO_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_0_AUDIO_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_0_AUDIO_ENABLE                       _MK_ENUM_CONST(0)
+#define APBDEV_PMC_PWR_DET_0_AUDIO_DISABLE                      _MK_ENUM_CONST(1)
+
+//rail lcd IOs   
+#define APBDEV_PMC_PWR_DET_0_LCD_SHIFT                  _MK_SHIFT_CONST(6)
+#define APBDEV_PMC_PWR_DET_0_LCD_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_PMC_PWR_DET_0_LCD_SHIFT)
+#define APBDEV_PMC_PWR_DET_0_LCD_RANGE                  6:6
+#define APBDEV_PMC_PWR_DET_0_LCD_WOFFSET                        0x0
+#define APBDEV_PMC_PWR_DET_0_LCD_DEFAULT                        _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_0_LCD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_0_LCD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_0_LCD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_0_LCD_ENABLE                 _MK_ENUM_CONST(0)
+#define APBDEV_PMC_PWR_DET_0_LCD_DISABLE                        _MK_ENUM_CONST(1)
+
+//rail mem IOs   
+#define APBDEV_PMC_PWR_DET_0_MEM_SHIFT                  _MK_SHIFT_CONST(7)
+#define APBDEV_PMC_PWR_DET_0_MEM_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_PMC_PWR_DET_0_MEM_SHIFT)
+#define APBDEV_PMC_PWR_DET_0_MEM_RANGE                  7:7
+#define APBDEV_PMC_PWR_DET_0_MEM_WOFFSET                        0x0
+#define APBDEV_PMC_PWR_DET_0_MEM_DEFAULT                        _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_0_MEM_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_0_MEM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_0_MEM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_0_MEM_ENABLE                 _MK_ENUM_CONST(0)
+#define APBDEV_PMC_PWR_DET_0_MEM_DISABLE                        _MK_ENUM_CONST(1)
+
+//rail sd IOs   
+#define APBDEV_PMC_PWR_DET_0_SD_SHIFT                   _MK_SHIFT_CONST(8)
+#define APBDEV_PMC_PWR_DET_0_SD_FIELD                   (_MK_MASK_CONST(0x1) << APBDEV_PMC_PWR_DET_0_SD_SHIFT)
+#define APBDEV_PMC_PWR_DET_0_SD_RANGE                   8:8
+#define APBDEV_PMC_PWR_DET_0_SD_WOFFSET                 0x0
+#define APBDEV_PMC_PWR_DET_0_SD_DEFAULT                 _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_0_SD_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_0_SD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_0_SD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_0_SD_ENABLE                  _MK_ENUM_CONST(0)
+#define APBDEV_PMC_PWR_DET_0_SD_DISABLE                 _MK_ENUM_CONST(1)
+
+
+// Register APBDEV_PMC_PWR_DET_LATCH_0  
+#define APBDEV_PMC_PWR_DET_LATCH_0                      _MK_ADDR_CONST(0x4c)
+#define APBDEV_PMC_PWR_DET_LATCH_0_SECURE                       0x0
+#define APBDEV_PMC_PWR_DET_LATCH_0_WORD_COUNT                   0x1
+#define APBDEV_PMC_PWR_DET_LATCH_0_RESET_VAL                    _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_LATCH_0_RESET_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_LATCH_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_LATCH_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_LATCH_0_READ_MASK                    _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_LATCH_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
+//power detect latch, latches value as long set to 1  
+#define APBDEV_PMC_PWR_DET_LATCH_0_LATCH_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_PWR_DET_LATCH_0_LATCH_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_PMC_PWR_DET_LATCH_0_LATCH_SHIFT)
+#define APBDEV_PMC_PWR_DET_LATCH_0_LATCH_RANGE                  0:0
+#define APBDEV_PMC_PWR_DET_LATCH_0_LATCH_WOFFSET                        0x0
+#define APBDEV_PMC_PWR_DET_LATCH_0_LATCH_DEFAULT                        _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_LATCH_0_LATCH_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_LATCH_0_LATCH_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_LATCH_0_LATCH_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_LATCH_0_LATCH_ENABLE                 _MK_ENUM_CONST(0)
+#define APBDEV_PMC_PWR_DET_LATCH_0_LATCH_DISABLE                        _MK_ENUM_CONST(1)
+
+
+// Register APBDEV_PMC_SCRATCH0_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH0_0                   _MK_ADDR_CONST(0x50)
+#define APBDEV_PMC_SCRATCH0_0_SECURE                    0x0
+#define APBDEV_PMC_SCRATCH0_0_WORD_COUNT                        0x1
+#define APBDEV_PMC_SCRATCH0_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH0_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH0_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH0_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH0_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH0_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH0_0_SCRATCH0_SHIFT                    _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH0_0_SCRATCH0_FIELD                    (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH0_0_SCRATCH0_SHIFT)
+#define APBDEV_PMC_SCRATCH0_0_SCRATCH0_RANGE                    31:0
+#define APBDEV_PMC_SCRATCH0_0_SCRATCH0_WOFFSET                  0x0
+#define APBDEV_PMC_SCRATCH0_0_SCRATCH0_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH0_0_SCRATCH0_DEFAULT_MASK                     _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH0_0_SCRATCH0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH0_0_SCRATCH0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH1_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH1_0                   _MK_ADDR_CONST(0x54)
+#define APBDEV_PMC_SCRATCH1_0_SECURE                    0x0
+#define APBDEV_PMC_SCRATCH1_0_WORD_COUNT                        0x1
+#define APBDEV_PMC_SCRATCH1_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH1_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH1_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH1_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH1_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH1_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH1_0_SCRATCH1_SHIFT                    _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH1_0_SCRATCH1_FIELD                    (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH1_0_SCRATCH1_SHIFT)
+#define APBDEV_PMC_SCRATCH1_0_SCRATCH1_RANGE                    31:0
+#define APBDEV_PMC_SCRATCH1_0_SCRATCH1_WOFFSET                  0x0
+#define APBDEV_PMC_SCRATCH1_0_SCRATCH1_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH1_0_SCRATCH1_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH1_0_SCRATCH1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH1_0_SCRATCH1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH2_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH2_0                   _MK_ADDR_CONST(0x58)
+#define APBDEV_PMC_SCRATCH2_0_SECURE                    0x0
+#define APBDEV_PMC_SCRATCH2_0_WORD_COUNT                        0x1
+#define APBDEV_PMC_SCRATCH2_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH2_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH2_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH2_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH2_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH2_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH2_0_SCRATCH2_SHIFT                    _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH2_0_SCRATCH2_FIELD                    (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH2_0_SCRATCH2_SHIFT)
+#define APBDEV_PMC_SCRATCH2_0_SCRATCH2_RANGE                    31:0
+#define APBDEV_PMC_SCRATCH2_0_SCRATCH2_WOFFSET                  0x0
+#define APBDEV_PMC_SCRATCH2_0_SCRATCH2_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH2_0_SCRATCH2_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH2_0_SCRATCH2_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH2_0_SCRATCH2_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH3_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH3_0                   _MK_ADDR_CONST(0x5c)
+#define APBDEV_PMC_SCRATCH3_0_SECURE                    0x0
+#define APBDEV_PMC_SCRATCH3_0_WORD_COUNT                        0x1
+#define APBDEV_PMC_SCRATCH3_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH3_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH3_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH3_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH3_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH3_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH3_0_SCRATCH3_SHIFT                    _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH3_0_SCRATCH3_FIELD                    (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH3_0_SCRATCH3_SHIFT)
+#define APBDEV_PMC_SCRATCH3_0_SCRATCH3_RANGE                    31:0
+#define APBDEV_PMC_SCRATCH3_0_SCRATCH3_WOFFSET                  0x0
+#define APBDEV_PMC_SCRATCH3_0_SCRATCH3_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH3_0_SCRATCH3_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH3_0_SCRATCH3_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH3_0_SCRATCH3_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH4_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH4_0                   _MK_ADDR_CONST(0x60)
+#define APBDEV_PMC_SCRATCH4_0_SECURE                    0x0
+#define APBDEV_PMC_SCRATCH4_0_WORD_COUNT                        0x1
+#define APBDEV_PMC_SCRATCH4_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH4_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH4_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH4_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH4_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH4_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH4_0_SCRATCH4_SHIFT                    _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH4_0_SCRATCH4_FIELD                    (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH4_0_SCRATCH4_SHIFT)
+#define APBDEV_PMC_SCRATCH4_0_SCRATCH4_RANGE                    31:0
+#define APBDEV_PMC_SCRATCH4_0_SCRATCH4_WOFFSET                  0x0
+#define APBDEV_PMC_SCRATCH4_0_SCRATCH4_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH4_0_SCRATCH4_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH4_0_SCRATCH4_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH4_0_SCRATCH4_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH5_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH5_0                   _MK_ADDR_CONST(0x64)
+#define APBDEV_PMC_SCRATCH5_0_SECURE                    0x0
+#define APBDEV_PMC_SCRATCH5_0_WORD_COUNT                        0x1
+#define APBDEV_PMC_SCRATCH5_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH5_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH5_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH5_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH5_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH5_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH5_0_SCRATCH5_SHIFT                    _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH5_0_SCRATCH5_FIELD                    (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH5_0_SCRATCH5_SHIFT)
+#define APBDEV_PMC_SCRATCH5_0_SCRATCH5_RANGE                    31:0
+#define APBDEV_PMC_SCRATCH5_0_SCRATCH5_WOFFSET                  0x0
+#define APBDEV_PMC_SCRATCH5_0_SCRATCH5_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH5_0_SCRATCH5_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH5_0_SCRATCH5_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH5_0_SCRATCH5_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH6_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH6_0                   _MK_ADDR_CONST(0x68)
+#define APBDEV_PMC_SCRATCH6_0_SECURE                    0x0
+#define APBDEV_PMC_SCRATCH6_0_WORD_COUNT                        0x1
+#define APBDEV_PMC_SCRATCH6_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH6_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH6_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH6_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH6_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH6_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH6_0_SCRATCH6_SHIFT                    _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH6_0_SCRATCH6_FIELD                    (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH6_0_SCRATCH6_SHIFT)
+#define APBDEV_PMC_SCRATCH6_0_SCRATCH6_RANGE                    31:0
+#define APBDEV_PMC_SCRATCH6_0_SCRATCH6_WOFFSET                  0x0
+#define APBDEV_PMC_SCRATCH6_0_SCRATCH6_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH6_0_SCRATCH6_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH6_0_SCRATCH6_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH6_0_SCRATCH6_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH7_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH7_0                   _MK_ADDR_CONST(0x6c)
+#define APBDEV_PMC_SCRATCH7_0_SECURE                    0x0
+#define APBDEV_PMC_SCRATCH7_0_WORD_COUNT                        0x1
+#define APBDEV_PMC_SCRATCH7_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH7_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH7_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH7_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH7_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH7_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH7_0_SCRATCH7_SHIFT                    _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH7_0_SCRATCH7_FIELD                    (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH7_0_SCRATCH7_SHIFT)
+#define APBDEV_PMC_SCRATCH7_0_SCRATCH7_RANGE                    31:0
+#define APBDEV_PMC_SCRATCH7_0_SCRATCH7_WOFFSET                  0x0
+#define APBDEV_PMC_SCRATCH7_0_SCRATCH7_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH7_0_SCRATCH7_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH7_0_SCRATCH7_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH7_0_SCRATCH7_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH8_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH8_0                   _MK_ADDR_CONST(0x70)
+#define APBDEV_PMC_SCRATCH8_0_SECURE                    0x0
+#define APBDEV_PMC_SCRATCH8_0_WORD_COUNT                        0x1
+#define APBDEV_PMC_SCRATCH8_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH8_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH8_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH8_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH8_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH8_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH8_0_SCRATCH8_SHIFT                    _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH8_0_SCRATCH8_FIELD                    (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH8_0_SCRATCH8_SHIFT)
+#define APBDEV_PMC_SCRATCH8_0_SCRATCH8_RANGE                    31:0
+#define APBDEV_PMC_SCRATCH8_0_SCRATCH8_WOFFSET                  0x0
+#define APBDEV_PMC_SCRATCH8_0_SCRATCH8_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH8_0_SCRATCH8_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH8_0_SCRATCH8_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH8_0_SCRATCH8_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH9_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH9_0                   _MK_ADDR_CONST(0x74)
+#define APBDEV_PMC_SCRATCH9_0_SECURE                    0x0
+#define APBDEV_PMC_SCRATCH9_0_WORD_COUNT                        0x1
+#define APBDEV_PMC_SCRATCH9_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH9_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH9_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH9_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH9_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH9_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH9_0_SCRATCH9_SHIFT                    _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH9_0_SCRATCH9_FIELD                    (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH9_0_SCRATCH9_SHIFT)
+#define APBDEV_PMC_SCRATCH9_0_SCRATCH9_RANGE                    31:0
+#define APBDEV_PMC_SCRATCH9_0_SCRATCH9_WOFFSET                  0x0
+#define APBDEV_PMC_SCRATCH9_0_SCRATCH9_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH9_0_SCRATCH9_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH9_0_SCRATCH9_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH9_0_SCRATCH9_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH10_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH10_0                  _MK_ADDR_CONST(0x78)
+#define APBDEV_PMC_SCRATCH10_0_SECURE                   0x0
+#define APBDEV_PMC_SCRATCH10_0_WORD_COUNT                       0x1
+#define APBDEV_PMC_SCRATCH10_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH10_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH10_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH10_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH10_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH10_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH10_0_SCRATCH10_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH10_0_SCRATCH10_FIELD                  (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH10_0_SCRATCH10_SHIFT)
+#define APBDEV_PMC_SCRATCH10_0_SCRATCH10_RANGE                  31:0
+#define APBDEV_PMC_SCRATCH10_0_SCRATCH10_WOFFSET                        0x0
+#define APBDEV_PMC_SCRATCH10_0_SCRATCH10_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH10_0_SCRATCH10_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH10_0_SCRATCH10_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH10_0_SCRATCH10_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH11_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH11_0                  _MK_ADDR_CONST(0x7c)
+#define APBDEV_PMC_SCRATCH11_0_SECURE                   0x0
+#define APBDEV_PMC_SCRATCH11_0_WORD_COUNT                       0x1
+#define APBDEV_PMC_SCRATCH11_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH11_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH11_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH11_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH11_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH11_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH11_0_SCRATCH11_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH11_0_SCRATCH11_FIELD                  (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH11_0_SCRATCH11_SHIFT)
+#define APBDEV_PMC_SCRATCH11_0_SCRATCH11_RANGE                  31:0
+#define APBDEV_PMC_SCRATCH11_0_SCRATCH11_WOFFSET                        0x0
+#define APBDEV_PMC_SCRATCH11_0_SCRATCH11_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH11_0_SCRATCH11_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH11_0_SCRATCH11_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH11_0_SCRATCH11_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH12_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH12_0                  _MK_ADDR_CONST(0x80)
+#define APBDEV_PMC_SCRATCH12_0_SECURE                   0x0
+#define APBDEV_PMC_SCRATCH12_0_WORD_COUNT                       0x1
+#define APBDEV_PMC_SCRATCH12_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH12_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH12_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH12_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH12_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH12_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH12_0_SCRATCH12_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH12_0_SCRATCH12_FIELD                  (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH12_0_SCRATCH12_SHIFT)
+#define APBDEV_PMC_SCRATCH12_0_SCRATCH12_RANGE                  31:0
+#define APBDEV_PMC_SCRATCH12_0_SCRATCH12_WOFFSET                        0x0
+#define APBDEV_PMC_SCRATCH12_0_SCRATCH12_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH12_0_SCRATCH12_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH12_0_SCRATCH12_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH12_0_SCRATCH12_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH13_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH13_0                  _MK_ADDR_CONST(0x84)
+#define APBDEV_PMC_SCRATCH13_0_SECURE                   0x0
+#define APBDEV_PMC_SCRATCH13_0_WORD_COUNT                       0x1
+#define APBDEV_PMC_SCRATCH13_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH13_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH13_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH13_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH13_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH13_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH13_0_SCRATCH13_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH13_0_SCRATCH13_FIELD                  (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH13_0_SCRATCH13_SHIFT)
+#define APBDEV_PMC_SCRATCH13_0_SCRATCH13_RANGE                  31:0
+#define APBDEV_PMC_SCRATCH13_0_SCRATCH13_WOFFSET                        0x0
+#define APBDEV_PMC_SCRATCH13_0_SCRATCH13_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH13_0_SCRATCH13_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH13_0_SCRATCH13_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH13_0_SCRATCH13_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH14_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH14_0                  _MK_ADDR_CONST(0x88)
+#define APBDEV_PMC_SCRATCH14_0_SECURE                   0x0
+#define APBDEV_PMC_SCRATCH14_0_WORD_COUNT                       0x1
+#define APBDEV_PMC_SCRATCH14_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH14_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH14_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH14_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH14_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH14_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH14_0_SCRATCH14_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH14_0_SCRATCH14_FIELD                  (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH14_0_SCRATCH14_SHIFT)
+#define APBDEV_PMC_SCRATCH14_0_SCRATCH14_RANGE                  31:0
+#define APBDEV_PMC_SCRATCH14_0_SCRATCH14_WOFFSET                        0x0
+#define APBDEV_PMC_SCRATCH14_0_SCRATCH14_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH14_0_SCRATCH14_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH14_0_SCRATCH14_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH14_0_SCRATCH14_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH15_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH15_0                  _MK_ADDR_CONST(0x8c)
+#define APBDEV_PMC_SCRATCH15_0_SECURE                   0x0
+#define APBDEV_PMC_SCRATCH15_0_WORD_COUNT                       0x1
+#define APBDEV_PMC_SCRATCH15_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH15_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH15_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH15_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH15_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH15_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH15_0_SCRATCH15_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH15_0_SCRATCH15_FIELD                  (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH15_0_SCRATCH15_SHIFT)
+#define APBDEV_PMC_SCRATCH15_0_SCRATCH15_RANGE                  31:0
+#define APBDEV_PMC_SCRATCH15_0_SCRATCH15_WOFFSET                        0x0
+#define APBDEV_PMC_SCRATCH15_0_SCRATCH15_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH15_0_SCRATCH15_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH15_0_SCRATCH15_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH15_0_SCRATCH15_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH16_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH16_0                  _MK_ADDR_CONST(0x90)
+#define APBDEV_PMC_SCRATCH16_0_SECURE                   0x0
+#define APBDEV_PMC_SCRATCH16_0_WORD_COUNT                       0x1
+#define APBDEV_PMC_SCRATCH16_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH16_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH16_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH16_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH16_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH16_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH16_0_SCRATCH16_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH16_0_SCRATCH16_FIELD                  (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH16_0_SCRATCH16_SHIFT)
+#define APBDEV_PMC_SCRATCH16_0_SCRATCH16_RANGE                  31:0
+#define APBDEV_PMC_SCRATCH16_0_SCRATCH16_WOFFSET                        0x0
+#define APBDEV_PMC_SCRATCH16_0_SCRATCH16_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH16_0_SCRATCH16_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH16_0_SCRATCH16_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH16_0_SCRATCH16_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH17_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH17_0                  _MK_ADDR_CONST(0x94)
+#define APBDEV_PMC_SCRATCH17_0_SECURE                   0x0
+#define APBDEV_PMC_SCRATCH17_0_WORD_COUNT                       0x1
+#define APBDEV_PMC_SCRATCH17_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH17_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH17_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH17_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH17_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH17_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH17_0_SCRATCH17_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH17_0_SCRATCH17_FIELD                  (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH17_0_SCRATCH17_SHIFT)
+#define APBDEV_PMC_SCRATCH17_0_SCRATCH17_RANGE                  31:0
+#define APBDEV_PMC_SCRATCH17_0_SCRATCH17_WOFFSET                        0x0
+#define APBDEV_PMC_SCRATCH17_0_SCRATCH17_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH17_0_SCRATCH17_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH17_0_SCRATCH17_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH17_0_SCRATCH17_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH18_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH18_0                  _MK_ADDR_CONST(0x98)
+#define APBDEV_PMC_SCRATCH18_0_SECURE                   0x0
+#define APBDEV_PMC_SCRATCH18_0_WORD_COUNT                       0x1
+#define APBDEV_PMC_SCRATCH18_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH18_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH18_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH18_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH18_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH18_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH18_0_SCRATCH18_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH18_0_SCRATCH18_FIELD                  (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH18_0_SCRATCH18_SHIFT)
+#define APBDEV_PMC_SCRATCH18_0_SCRATCH18_RANGE                  31:0
+#define APBDEV_PMC_SCRATCH18_0_SCRATCH18_WOFFSET                        0x0
+#define APBDEV_PMC_SCRATCH18_0_SCRATCH18_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH18_0_SCRATCH18_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH18_0_SCRATCH18_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH18_0_SCRATCH18_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH19_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH19_0                  _MK_ADDR_CONST(0x9c)
+#define APBDEV_PMC_SCRATCH19_0_SECURE                   0x0
+#define APBDEV_PMC_SCRATCH19_0_WORD_COUNT                       0x1
+#define APBDEV_PMC_SCRATCH19_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH19_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH19_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH19_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH19_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH19_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH19_0_SCRATCH19_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH19_0_SCRATCH19_FIELD                  (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH19_0_SCRATCH19_SHIFT)
+#define APBDEV_PMC_SCRATCH19_0_SCRATCH19_RANGE                  31:0
+#define APBDEV_PMC_SCRATCH19_0_SCRATCH19_WOFFSET                        0x0
+#define APBDEV_PMC_SCRATCH19_0_SCRATCH19_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH19_0_SCRATCH19_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH19_0_SCRATCH19_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH19_0_SCRATCH19_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH20_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH20_0                  _MK_ADDR_CONST(0xa0)
+#define APBDEV_PMC_SCRATCH20_0_SECURE                   0x0
+#define APBDEV_PMC_SCRATCH20_0_WORD_COUNT                       0x1
+#define APBDEV_PMC_SCRATCH20_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH20_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH20_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH20_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH20_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH20_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH20_0_SCRATCH20_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH20_0_SCRATCH20_FIELD                  (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH20_0_SCRATCH20_SHIFT)
+#define APBDEV_PMC_SCRATCH20_0_SCRATCH20_RANGE                  31:0
+#define APBDEV_PMC_SCRATCH20_0_SCRATCH20_WOFFSET                        0x0
+#define APBDEV_PMC_SCRATCH20_0_SCRATCH20_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH20_0_SCRATCH20_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH20_0_SCRATCH20_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH20_0_SCRATCH20_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH21_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH21_0                  _MK_ADDR_CONST(0xa4)
+#define APBDEV_PMC_SCRATCH21_0_SECURE                   0x0
+#define APBDEV_PMC_SCRATCH21_0_WORD_COUNT                       0x1
+#define APBDEV_PMC_SCRATCH21_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH21_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH21_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH21_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH21_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH21_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH21_0_SCRATCH21_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH21_0_SCRATCH21_FIELD                  (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH21_0_SCRATCH21_SHIFT)
+#define APBDEV_PMC_SCRATCH21_0_SCRATCH21_RANGE                  31:0
+#define APBDEV_PMC_SCRATCH21_0_SCRATCH21_WOFFSET                        0x0
+#define APBDEV_PMC_SCRATCH21_0_SCRATCH21_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH21_0_SCRATCH21_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH21_0_SCRATCH21_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH21_0_SCRATCH21_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH22_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH22_0                  _MK_ADDR_CONST(0xa8)
+#define APBDEV_PMC_SCRATCH22_0_SECURE                   0x0
+#define APBDEV_PMC_SCRATCH22_0_WORD_COUNT                       0x1
+#define APBDEV_PMC_SCRATCH22_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH22_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH22_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH22_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH22_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH22_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH22_0_SCRATCH22_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH22_0_SCRATCH22_FIELD                  (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH22_0_SCRATCH22_SHIFT)
+#define APBDEV_PMC_SCRATCH22_0_SCRATCH22_RANGE                  31:0
+#define APBDEV_PMC_SCRATCH22_0_SCRATCH22_WOFFSET                        0x0
+#define APBDEV_PMC_SCRATCH22_0_SCRATCH22_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH22_0_SCRATCH22_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH22_0_SCRATCH22_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH22_0_SCRATCH22_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH23_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH23_0                  _MK_ADDR_CONST(0xac)
+#define APBDEV_PMC_SCRATCH23_0_SECURE                   0x0
+#define APBDEV_PMC_SCRATCH23_0_WORD_COUNT                       0x1
+#define APBDEV_PMC_SCRATCH23_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH23_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH23_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH23_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH23_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH23_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH23_0_SCRATCH23_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH23_0_SCRATCH23_FIELD                  (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH23_0_SCRATCH23_SHIFT)
+#define APBDEV_PMC_SCRATCH23_0_SCRATCH23_RANGE                  31:0
+#define APBDEV_PMC_SCRATCH23_0_SCRATCH23_WOFFSET                        0x0
+#define APBDEV_PMC_SCRATCH23_0_SCRATCH23_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH23_0_SCRATCH23_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH23_0_SCRATCH23_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH23_0_SCRATCH23_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SECURE_SCRATCH0_0  // Secure scratch register
+#define APBDEV_PMC_SECURE_SCRATCH0_0                    _MK_ADDR_CONST(0xb0)
+#define APBDEV_PMC_SECURE_SCRATCH0_0_SECURE                     0x0
+#define APBDEV_PMC_SECURE_SCRATCH0_0_WORD_COUNT                         0x1
+#define APBDEV_PMC_SECURE_SCRATCH0_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH0_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH0_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH0_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH0_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SECURE_SCRATCH0_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SECURE_SCRATCH0_0_SECURE_SCRATCH0_SHIFT                      _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SECURE_SCRATCH0_0_SECURE_SCRATCH0_FIELD                      (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SECURE_SCRATCH0_0_SECURE_SCRATCH0_SHIFT)
+#define APBDEV_PMC_SECURE_SCRATCH0_0_SECURE_SCRATCH0_RANGE                      31:0
+#define APBDEV_PMC_SECURE_SCRATCH0_0_SECURE_SCRATCH0_WOFFSET                    0x0
+#define APBDEV_PMC_SECURE_SCRATCH0_0_SECURE_SCRATCH0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH0_0_SECURE_SCRATCH0_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH0_0_SECURE_SCRATCH0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH0_0_SECURE_SCRATCH0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SECURE_SCRATCH1_0  // Secure scratch register
+#define APBDEV_PMC_SECURE_SCRATCH1_0                    _MK_ADDR_CONST(0xb4)
+#define APBDEV_PMC_SECURE_SCRATCH1_0_SECURE                     0x0
+#define APBDEV_PMC_SECURE_SCRATCH1_0_WORD_COUNT                         0x1
+#define APBDEV_PMC_SECURE_SCRATCH1_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH1_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH1_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SECURE_SCRATCH1_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SECURE_SCRATCH1_0_SECURE_SCRATCH1_SHIFT                      _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SECURE_SCRATCH1_0_SECURE_SCRATCH1_FIELD                      (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SECURE_SCRATCH1_0_SECURE_SCRATCH1_SHIFT)
+#define APBDEV_PMC_SECURE_SCRATCH1_0_SECURE_SCRATCH1_RANGE                      31:0
+#define APBDEV_PMC_SECURE_SCRATCH1_0_SECURE_SCRATCH1_WOFFSET                    0x0
+#define APBDEV_PMC_SECURE_SCRATCH1_0_SECURE_SCRATCH1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH1_0_SECURE_SCRATCH1_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH1_0_SECURE_SCRATCH1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH1_0_SECURE_SCRATCH1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SECURE_SCRATCH2_0  // Secure scratch register
+#define APBDEV_PMC_SECURE_SCRATCH2_0                    _MK_ADDR_CONST(0xb8)
+#define APBDEV_PMC_SECURE_SCRATCH2_0_SECURE                     0x0
+#define APBDEV_PMC_SECURE_SCRATCH2_0_WORD_COUNT                         0x1
+#define APBDEV_PMC_SECURE_SCRATCH2_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH2_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH2_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH2_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH2_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SECURE_SCRATCH2_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SECURE_SCRATCH2_0_SECURE_SCRATCH2_SHIFT                      _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SECURE_SCRATCH2_0_SECURE_SCRATCH2_FIELD                      (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SECURE_SCRATCH2_0_SECURE_SCRATCH2_SHIFT)
+#define APBDEV_PMC_SECURE_SCRATCH2_0_SECURE_SCRATCH2_RANGE                      31:0
+#define APBDEV_PMC_SECURE_SCRATCH2_0_SECURE_SCRATCH2_WOFFSET                    0x0
+#define APBDEV_PMC_SECURE_SCRATCH2_0_SECURE_SCRATCH2_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH2_0_SECURE_SCRATCH2_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH2_0_SECURE_SCRATCH2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH2_0_SECURE_SCRATCH2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SECURE_SCRATCH3_0  // Secure scratch register
+#define APBDEV_PMC_SECURE_SCRATCH3_0                    _MK_ADDR_CONST(0xbc)
+#define APBDEV_PMC_SECURE_SCRATCH3_0_SECURE                     0x0
+#define APBDEV_PMC_SECURE_SCRATCH3_0_WORD_COUNT                         0x1
+#define APBDEV_PMC_SECURE_SCRATCH3_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH3_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH3_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH3_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH3_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SECURE_SCRATCH3_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SECURE_SCRATCH3_0_SECURE_SCRATCH3_SHIFT                      _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SECURE_SCRATCH3_0_SECURE_SCRATCH3_FIELD                      (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SECURE_SCRATCH3_0_SECURE_SCRATCH3_SHIFT)
+#define APBDEV_PMC_SECURE_SCRATCH3_0_SECURE_SCRATCH3_RANGE                      31:0
+#define APBDEV_PMC_SECURE_SCRATCH3_0_SECURE_SCRATCH3_WOFFSET                    0x0
+#define APBDEV_PMC_SECURE_SCRATCH3_0_SECURE_SCRATCH3_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH3_0_SECURE_SCRATCH3_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH3_0_SECURE_SCRATCH3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH3_0_SECURE_SCRATCH3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SECURE_SCRATCH4_0  // Secure scratch register
+#define APBDEV_PMC_SECURE_SCRATCH4_0                    _MK_ADDR_CONST(0xc0)
+#define APBDEV_PMC_SECURE_SCRATCH4_0_SECURE                     0x0
+#define APBDEV_PMC_SECURE_SCRATCH4_0_WORD_COUNT                         0x1
+#define APBDEV_PMC_SECURE_SCRATCH4_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH4_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH4_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH4_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH4_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SECURE_SCRATCH4_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SECURE_SCRATCH4_0_SECURE_SCRATCH4_SHIFT                      _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SECURE_SCRATCH4_0_SECURE_SCRATCH4_FIELD                      (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SECURE_SCRATCH4_0_SECURE_SCRATCH4_SHIFT)
+#define APBDEV_PMC_SECURE_SCRATCH4_0_SECURE_SCRATCH4_RANGE                      31:0
+#define APBDEV_PMC_SECURE_SCRATCH4_0_SECURE_SCRATCH4_WOFFSET                    0x0
+#define APBDEV_PMC_SECURE_SCRATCH4_0_SECURE_SCRATCH4_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH4_0_SECURE_SCRATCH4_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH4_0_SECURE_SCRATCH4_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH4_0_SECURE_SCRATCH4_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SECURE_SCRATCH5_0  // Secure scratch register
+#define APBDEV_PMC_SECURE_SCRATCH5_0                    _MK_ADDR_CONST(0xc4)
+#define APBDEV_PMC_SECURE_SCRATCH5_0_SECURE                     0x0
+#define APBDEV_PMC_SECURE_SCRATCH5_0_WORD_COUNT                         0x1
+#define APBDEV_PMC_SECURE_SCRATCH5_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH5_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH5_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH5_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH5_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SECURE_SCRATCH5_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SECURE_SCRATCH5_0_SECURE_SCRATCH5_SHIFT                      _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SECURE_SCRATCH5_0_SECURE_SCRATCH5_FIELD                      (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SECURE_SCRATCH5_0_SECURE_SCRATCH5_SHIFT)
+#define APBDEV_PMC_SECURE_SCRATCH5_0_SECURE_SCRATCH5_RANGE                      31:0
+#define APBDEV_PMC_SECURE_SCRATCH5_0_SECURE_SCRATCH5_WOFFSET                    0x0
+#define APBDEV_PMC_SECURE_SCRATCH5_0_SECURE_SCRATCH5_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH5_0_SECURE_SCRATCH5_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH5_0_SECURE_SCRATCH5_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH5_0_SECURE_SCRATCH5_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_CPUPWRGOOD_TIMER_0  
+#define APBDEV_PMC_CPUPWRGOOD_TIMER_0                   _MK_ADDR_CONST(0xc8)
+#define APBDEV_PMC_CPUPWRGOOD_TIMER_0_SECURE                    0x0
+#define APBDEV_PMC_CPUPWRGOOD_TIMER_0_WORD_COUNT                        0x1
+#define APBDEV_PMC_CPUPWRGOOD_TIMER_0_RESET_VAL                         _MK_MASK_CONST(0xffff)
+#define APBDEV_PMC_CPUPWRGOOD_TIMER_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_CPUPWRGOOD_TIMER_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CPUPWRGOOD_TIMER_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CPUPWRGOOD_TIMER_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_CPUPWRGOOD_TIMER_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
+// timer data
+#define APBDEV_PMC_CPUPWRGOOD_TIMER_0_DATA_SHIFT                        _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_CPUPWRGOOD_TIMER_0_DATA_FIELD                        (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_CPUPWRGOOD_TIMER_0_DATA_SHIFT)
+#define APBDEV_PMC_CPUPWRGOOD_TIMER_0_DATA_RANGE                        31:0
+#define APBDEV_PMC_CPUPWRGOOD_TIMER_0_DATA_WOFFSET                      0x0
+#define APBDEV_PMC_CPUPWRGOOD_TIMER_0_DATA_DEFAULT                      _MK_MASK_CONST(0xffff)
+#define APBDEV_PMC_CPUPWRGOOD_TIMER_0_DATA_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_CPUPWRGOOD_TIMER_0_DATA_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CPUPWRGOOD_TIMER_0_DATA_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_CPUPWROFF_TIMER_0  
+#define APBDEV_PMC_CPUPWROFF_TIMER_0                    _MK_ADDR_CONST(0xcc)
+#define APBDEV_PMC_CPUPWROFF_TIMER_0_SECURE                     0x0
+#define APBDEV_PMC_CPUPWROFF_TIMER_0_WORD_COUNT                         0x1
+#define APBDEV_PMC_CPUPWROFF_TIMER_0_RESET_VAL                  _MK_MASK_CONST(0xffff)
+#define APBDEV_PMC_CPUPWROFF_TIMER_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_CPUPWROFF_TIMER_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CPUPWROFF_TIMER_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CPUPWROFF_TIMER_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_CPUPWROFF_TIMER_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+// timer data
+#define APBDEV_PMC_CPUPWROFF_TIMER_0_DATA_SHIFT                 _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_CPUPWROFF_TIMER_0_DATA_FIELD                 (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_CPUPWROFF_TIMER_0_DATA_SHIFT)
+#define APBDEV_PMC_CPUPWROFF_TIMER_0_DATA_RANGE                 31:0
+#define APBDEV_PMC_CPUPWROFF_TIMER_0_DATA_WOFFSET                       0x0
+#define APBDEV_PMC_CPUPWROFF_TIMER_0_DATA_DEFAULT                       _MK_MASK_CONST(0xffff)
+#define APBDEV_PMC_CPUPWROFF_TIMER_0_DATA_DEFAULT_MASK                  _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_CPUPWROFF_TIMER_0_DATA_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CPUPWROFF_TIMER_0_DATA_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_PG_MASK_0  
+#define APBDEV_PMC_PG_MASK_0                    _MK_ADDR_CONST(0xd0)
+#define APBDEV_PMC_PG_MASK_0_SECURE                     0x0
+#define APBDEV_PMC_PG_MASK_0_WORD_COUNT                         0x1
+#define APBDEV_PMC_PG_MASK_0_RESET_VAL                  _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_PG_MASK_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_PG_MASK_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PG_MASK_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PG_MASK_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_PG_MASK_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+// Mask TD rail
+#define APBDEV_PMC_PG_MASK_0_TD_SHIFT                   _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_PG_MASK_0_TD_FIELD                   (_MK_MASK_CONST(0xff) << APBDEV_PMC_PG_MASK_0_TD_SHIFT)
+#define APBDEV_PMC_PG_MASK_0_TD_RANGE                   7:0
+#define APBDEV_PMC_PG_MASK_0_TD_WOFFSET                 0x0
+#define APBDEV_PMC_PG_MASK_0_TD_DEFAULT                 _MK_MASK_CONST(0xff)
+#define APBDEV_PMC_PG_MASK_0_TD_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define APBDEV_PMC_PG_MASK_0_TD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PG_MASK_0_TD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Mask VE rail
+#define APBDEV_PMC_PG_MASK_0_VE_SHIFT                   _MK_SHIFT_CONST(8)
+#define APBDEV_PMC_PG_MASK_0_VE_FIELD                   (_MK_MASK_CONST(0xff) << APBDEV_PMC_PG_MASK_0_VE_SHIFT)
+#define APBDEV_PMC_PG_MASK_0_VE_RANGE                   15:8
+#define APBDEV_PMC_PG_MASK_0_VE_WOFFSET                 0x0
+#define APBDEV_PMC_PG_MASK_0_VE_DEFAULT                 _MK_MASK_CONST(0xff)
+#define APBDEV_PMC_PG_MASK_0_VE_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define APBDEV_PMC_PG_MASK_0_VE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PG_MASK_0_VE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Mask VDE rail
+#define APBDEV_PMC_PG_MASK_0_VD_SHIFT                   _MK_SHIFT_CONST(16)
+#define APBDEV_PMC_PG_MASK_0_VD_FIELD                   (_MK_MASK_CONST(0xff) << APBDEV_PMC_PG_MASK_0_VD_SHIFT)
+#define APBDEV_PMC_PG_MASK_0_VD_RANGE                   23:16
+#define APBDEV_PMC_PG_MASK_0_VD_WOFFSET                 0x0
+#define APBDEV_PMC_PG_MASK_0_VD_DEFAULT                 _MK_MASK_CONST(0xff)
+#define APBDEV_PMC_PG_MASK_0_VD_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define APBDEV_PMC_PG_MASK_0_VD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PG_MASK_0_VD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Mask PCX rail
+#define APBDEV_PMC_PG_MASK_0_PX_SHIFT                   _MK_SHIFT_CONST(24)
+#define APBDEV_PMC_PG_MASK_0_PX_FIELD                   (_MK_MASK_CONST(0xff) << APBDEV_PMC_PG_MASK_0_PX_SHIFT)
+#define APBDEV_PMC_PG_MASK_0_PX_RANGE                   31:24
+#define APBDEV_PMC_PG_MASK_0_PX_WOFFSET                 0x0
+#define APBDEV_PMC_PG_MASK_0_PX_DEFAULT                 _MK_MASK_CONST(0xff)
+#define APBDEV_PMC_PG_MASK_0_PX_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define APBDEV_PMC_PG_MASK_0_PX_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PG_MASK_0_PX_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_PG_MASK_1_0  
+#define APBDEV_PMC_PG_MASK_1_0                  _MK_ADDR_CONST(0xd4)
+#define APBDEV_PMC_PG_MASK_1_0_SECURE                   0x0
+#define APBDEV_PMC_PG_MASK_1_0_WORD_COUNT                       0x1
+#define APBDEV_PMC_PG_MASK_1_0_RESET_VAL                        _MK_MASK_CONST(0xff01)
+#define APBDEV_PMC_PG_MASK_1_0_RESET_MASK                       _MK_MASK_CONST(0xff01)
+#define APBDEV_PMC_PG_MASK_1_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PG_MASK_1_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PG_MASK_1_0_READ_MASK                        _MK_MASK_CONST(0xff01)
+#define APBDEV_PMC_PG_MASK_1_0_WRITE_MASK                       _MK_MASK_CONST(0xff01)
+// MASK L2C rail
+#define APBDEV_PMC_PG_MASK_1_0_L2C_SHIFT                        _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_PG_MASK_1_0_L2C_FIELD                        (_MK_MASK_CONST(0x1) << APBDEV_PMC_PG_MASK_1_0_L2C_SHIFT)
+#define APBDEV_PMC_PG_MASK_1_0_L2C_RANGE                        0:0
+#define APBDEV_PMC_PG_MASK_1_0_L2C_WOFFSET                      0x0
+#define APBDEV_PMC_PG_MASK_1_0_L2C_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PG_MASK_1_0_L2C_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PG_MASK_1_0_L2C_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PG_MASK_1_0_L2C_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// MASK MPE rail
+#define APBDEV_PMC_PG_MASK_1_0_MPE_SHIFT                        _MK_SHIFT_CONST(8)
+#define APBDEV_PMC_PG_MASK_1_0_MPE_FIELD                        (_MK_MASK_CONST(0xff) << APBDEV_PMC_PG_MASK_1_0_MPE_SHIFT)
+#define APBDEV_PMC_PG_MASK_1_0_MPE_RANGE                        15:8
+#define APBDEV_PMC_PG_MASK_1_0_MPE_WOFFSET                      0x0
+#define APBDEV_PMC_PG_MASK_1_0_MPE_DEFAULT                      _MK_MASK_CONST(0xff)
+#define APBDEV_PMC_PG_MASK_1_0_MPE_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
+#define APBDEV_PMC_PG_MASK_1_0_MPE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PG_MASK_1_0_MPE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_AUTO_WAKE_LVL_0  
+#define APBDEV_PMC_AUTO_WAKE_LVL_0                      _MK_ADDR_CONST(0xd8)
+#define APBDEV_PMC_AUTO_WAKE_LVL_0_SECURE                       0x0
+#define APBDEV_PMC_AUTO_WAKE_LVL_0_WORD_COUNT                   0x1
+#define APBDEV_PMC_AUTO_WAKE_LVL_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_AUTO_WAKE_LVL_0_RESET_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_AUTO_WAKE_LVL_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_AUTO_WAKE_LVL_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_AUTO_WAKE_LVL_0_READ_MASK                    _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_AUTO_WAKE_LVL_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
+//Causes PMC to sample the wake pads
+#define APBDEV_PMC_AUTO_WAKE_LVL_0_SMPL_SHIFT                   _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_AUTO_WAKE_LVL_0_SMPL_FIELD                   (_MK_MASK_CONST(0x1) << APBDEV_PMC_AUTO_WAKE_LVL_0_SMPL_SHIFT)
+#define APBDEV_PMC_AUTO_WAKE_LVL_0_SMPL_RANGE                   0:0
+#define APBDEV_PMC_AUTO_WAKE_LVL_0_SMPL_WOFFSET                 0x0
+#define APBDEV_PMC_AUTO_WAKE_LVL_0_SMPL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_AUTO_WAKE_LVL_0_SMPL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_AUTO_WAKE_LVL_0_SMPL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_AUTO_WAKE_LVL_0_SMPL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_AUTO_WAKE_LVL_0_SMPL_DISABLE                 _MK_ENUM_CONST(0)
+#define APBDEV_PMC_AUTO_WAKE_LVL_0_SMPL_ENABLE                  _MK_ENUM_CONST(1)
+
+
+// Register APBDEV_PMC_AUTO_WAKE_LVL_MASK_0  
+#define APBDEV_PMC_AUTO_WAKE_LVL_MASK_0                 _MK_ADDR_CONST(0xdc)
+#define APBDEV_PMC_AUTO_WAKE_LVL_MASK_0_SECURE                  0x0
+#define APBDEV_PMC_AUTO_WAKE_LVL_MASK_0_WORD_COUNT                      0x1
+#define APBDEV_PMC_AUTO_WAKE_LVL_MASK_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_AUTO_WAKE_LVL_MASK_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_AUTO_WAKE_LVL_MASK_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_AUTO_WAKE_LVL_MASK_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_AUTO_WAKE_LVL_MASK_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_AUTO_WAKE_LVL_MASK_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_AUTO_WAKE_LVL_MASK_0_VALUE_SHIFT                     _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_AUTO_WAKE_LVL_MASK_0_VALUE_FIELD                     (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_AUTO_WAKE_LVL_MASK_0_VALUE_SHIFT)
+#define APBDEV_PMC_AUTO_WAKE_LVL_MASK_0_VALUE_RANGE                     31:0
+#define APBDEV_PMC_AUTO_WAKE_LVL_MASK_0_VALUE_WOFFSET                   0x0
+#define APBDEV_PMC_AUTO_WAKE_LVL_MASK_0_VALUE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_AUTO_WAKE_LVL_MASK_0_VALUE_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_AUTO_WAKE_LVL_MASK_0_VALUE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_AUTO_WAKE_LVL_MASK_0_VALUE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_WAKE_DELAY_0  
+#define APBDEV_PMC_WAKE_DELAY_0                 _MK_ADDR_CONST(0xe0)
+#define APBDEV_PMC_WAKE_DELAY_0_SECURE                  0x0
+#define APBDEV_PMC_WAKE_DELAY_0_WORD_COUNT                      0x1
+#define APBDEV_PMC_WAKE_DELAY_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_DELAY_0_RESET_MASK                      _MK_MASK_CONST(0xffff)
+#define APBDEV_PMC_WAKE_DELAY_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_DELAY_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_DELAY_0_READ_MASK                       _MK_MASK_CONST(0xffff)
+#define APBDEV_PMC_WAKE_DELAY_0_WRITE_MASK                      _MK_MASK_CONST(0xffff)
+#define APBDEV_PMC_WAKE_DELAY_0_VALUE_SHIFT                     _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_WAKE_DELAY_0_VALUE_FIELD                     (_MK_MASK_CONST(0xffff) << APBDEV_PMC_WAKE_DELAY_0_VALUE_SHIFT)
+#define APBDEV_PMC_WAKE_DELAY_0_VALUE_RANGE                     15:0
+#define APBDEV_PMC_WAKE_DELAY_0_VALUE_WOFFSET                   0x0
+#define APBDEV_PMC_WAKE_DELAY_0_VALUE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_DELAY_0_VALUE_DEFAULT_MASK                      _MK_MASK_CONST(0xffff)
+#define APBDEV_PMC_WAKE_DELAY_0_VALUE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_DELAY_0_VALUE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_PWR_DET_VAL_0  
+#define APBDEV_PMC_PWR_DET_VAL_0                        _MK_ADDR_CONST(0xe4)
+#define APBDEV_PMC_PWR_DET_VAL_0_SECURE                         0x0
+#define APBDEV_PMC_PWR_DET_VAL_0_WORD_COUNT                     0x1
+#define APBDEV_PMC_PWR_DET_VAL_0_RESET_VAL                      _MK_MASK_CONST(0x1ff)
+#define APBDEV_PMC_PWR_DET_VAL_0_RESET_MASK                     _MK_MASK_CONST(0x1ff)
+#define APBDEV_PMC_PWR_DET_VAL_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_VAL_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_VAL_0_READ_MASK                      _MK_MASK_CONST(0x1ff)
+#define APBDEV_PMC_PWR_DET_VAL_0_WRITE_MASK                     _MK_MASK_CONST(0x1ff)
+//rail ao IOs   
+#define APBDEV_PMC_PWR_DET_VAL_0_SYS_SHIFT                      _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_PWR_DET_VAL_0_SYS_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_PMC_PWR_DET_VAL_0_SYS_SHIFT)
+#define APBDEV_PMC_PWR_DET_VAL_0_SYS_RANGE                      0:0
+#define APBDEV_PMC_PWR_DET_VAL_0_SYS_WOFFSET                    0x0
+#define APBDEV_PMC_PWR_DET_VAL_0_SYS_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_VAL_0_SYS_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_VAL_0_SYS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_VAL_0_SYS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_VAL_0_SYS_ENABLE                     _MK_ENUM_CONST(0)
+#define APBDEV_PMC_PWR_DET_VAL_0_SYS_DISABLE                    _MK_ENUM_CONST(1)
+
+//rail at3 IOs 
+#define APBDEV_PMC_PWR_DET_VAL_0_NAND_SHIFT                     _MK_SHIFT_CONST(1)
+#define APBDEV_PMC_PWR_DET_VAL_0_NAND_FIELD                     (_MK_MASK_CONST(0x1) << APBDEV_PMC_PWR_DET_VAL_0_NAND_SHIFT)
+#define APBDEV_PMC_PWR_DET_VAL_0_NAND_RANGE                     1:1
+#define APBDEV_PMC_PWR_DET_VAL_0_NAND_WOFFSET                   0x0
+#define APBDEV_PMC_PWR_DET_VAL_0_NAND_DEFAULT                   _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_VAL_0_NAND_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_VAL_0_NAND_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_VAL_0_NAND_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_VAL_0_NAND_ENABLE                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_PWR_DET_VAL_0_NAND_DISABLE                   _MK_ENUM_CONST(1)
+
+//rail dbg IOs   
+#define APBDEV_PMC_PWR_DET_VAL_0_UART_SHIFT                     _MK_SHIFT_CONST(2)
+#define APBDEV_PMC_PWR_DET_VAL_0_UART_FIELD                     (_MK_MASK_CONST(0x1) << APBDEV_PMC_PWR_DET_VAL_0_UART_SHIFT)
+#define APBDEV_PMC_PWR_DET_VAL_0_UART_RANGE                     2:2
+#define APBDEV_PMC_PWR_DET_VAL_0_UART_WOFFSET                   0x0
+#define APBDEV_PMC_PWR_DET_VAL_0_UART_DEFAULT                   _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_VAL_0_UART_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_VAL_0_UART_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_VAL_0_UART_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_VAL_0_UART_ENABLE                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_PWR_DET_VAL_0_UART_DISABLE                   _MK_ENUM_CONST(1)
+
+//rail dlcd IOs   
+#define APBDEV_PMC_PWR_DET_VAL_0_BB_SHIFT                       _MK_SHIFT_CONST(3)
+#define APBDEV_PMC_PWR_DET_VAL_0_BB_FIELD                       (_MK_MASK_CONST(0x1) << APBDEV_PMC_PWR_DET_VAL_0_BB_SHIFT)
+#define APBDEV_PMC_PWR_DET_VAL_0_BB_RANGE                       3:3
+#define APBDEV_PMC_PWR_DET_VAL_0_BB_WOFFSET                     0x0
+#define APBDEV_PMC_PWR_DET_VAL_0_BB_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_VAL_0_BB_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_VAL_0_BB_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_VAL_0_BB_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_VAL_0_BB_ENABLE                      _MK_ENUM_CONST(0)
+#define APBDEV_PMC_PWR_DET_VAL_0_BB_DISABLE                     _MK_ENUM_CONST(1)
+
+//rail dvi IOs   
+#define APBDEV_PMC_PWR_DET_VAL_0_VI_SHIFT                       _MK_SHIFT_CONST(4)
+#define APBDEV_PMC_PWR_DET_VAL_0_VI_FIELD                       (_MK_MASK_CONST(0x1) << APBDEV_PMC_PWR_DET_VAL_0_VI_SHIFT)
+#define APBDEV_PMC_PWR_DET_VAL_0_VI_RANGE                       4:4
+#define APBDEV_PMC_PWR_DET_VAL_0_VI_WOFFSET                     0x0
+#define APBDEV_PMC_PWR_DET_VAL_0_VI_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_VAL_0_VI_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_VAL_0_VI_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_VAL_0_VI_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_VAL_0_VI_ENABLE                      _MK_ENUM_CONST(0)
+#define APBDEV_PMC_PWR_DET_VAL_0_VI_DISABLE                     _MK_ENUM_CONST(1)
+
+//rail i2s IOs   
+#define APBDEV_PMC_PWR_DET_VAL_0_AUDIO_SHIFT                    _MK_SHIFT_CONST(5)
+#define APBDEV_PMC_PWR_DET_VAL_0_AUDIO_FIELD                    (_MK_MASK_CONST(0x1) << APBDEV_PMC_PWR_DET_VAL_0_AUDIO_SHIFT)
+#define APBDEV_PMC_PWR_DET_VAL_0_AUDIO_RANGE                    5:5
+#define APBDEV_PMC_PWR_DET_VAL_0_AUDIO_WOFFSET                  0x0
+#define APBDEV_PMC_PWR_DET_VAL_0_AUDIO_DEFAULT                  _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_VAL_0_AUDIO_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_VAL_0_AUDIO_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_VAL_0_AUDIO_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_VAL_0_AUDIO_ENABLE                   _MK_ENUM_CONST(0)
+#define APBDEV_PMC_PWR_DET_VAL_0_AUDIO_DISABLE                  _MK_ENUM_CONST(1)
+
+//rail lcd IOs   
+#define APBDEV_PMC_PWR_DET_VAL_0_LCD_SHIFT                      _MK_SHIFT_CONST(6)
+#define APBDEV_PMC_PWR_DET_VAL_0_LCD_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_PMC_PWR_DET_VAL_0_LCD_SHIFT)
+#define APBDEV_PMC_PWR_DET_VAL_0_LCD_RANGE                      6:6
+#define APBDEV_PMC_PWR_DET_VAL_0_LCD_WOFFSET                    0x0
+#define APBDEV_PMC_PWR_DET_VAL_0_LCD_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_VAL_0_LCD_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_VAL_0_LCD_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_VAL_0_LCD_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_VAL_0_LCD_ENABLE                     _MK_ENUM_CONST(0)
+#define APBDEV_PMC_PWR_DET_VAL_0_LCD_DISABLE                    _MK_ENUM_CONST(1)
+
+//rail mem IOs   
+#define APBDEV_PMC_PWR_DET_VAL_0_MEM_SHIFT                      _MK_SHIFT_CONST(7)
+#define APBDEV_PMC_PWR_DET_VAL_0_MEM_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_PMC_PWR_DET_VAL_0_MEM_SHIFT)
+#define APBDEV_PMC_PWR_DET_VAL_0_MEM_RANGE                      7:7
+#define APBDEV_PMC_PWR_DET_VAL_0_MEM_WOFFSET                    0x0
+#define APBDEV_PMC_PWR_DET_VAL_0_MEM_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_VAL_0_MEM_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_VAL_0_MEM_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_VAL_0_MEM_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_VAL_0_MEM_ENABLE                     _MK_ENUM_CONST(0)
+#define APBDEV_PMC_PWR_DET_VAL_0_MEM_DISABLE                    _MK_ENUM_CONST(1)
+
+//rail sd IOs   
+#define APBDEV_PMC_PWR_DET_VAL_0_SD_SHIFT                       _MK_SHIFT_CONST(8)
+#define APBDEV_PMC_PWR_DET_VAL_0_SD_FIELD                       (_MK_MASK_CONST(0x1) << APBDEV_PMC_PWR_DET_VAL_0_SD_SHIFT)
+#define APBDEV_PMC_PWR_DET_VAL_0_SD_RANGE                       8:8
+#define APBDEV_PMC_PWR_DET_VAL_0_SD_WOFFSET                     0x0
+#define APBDEV_PMC_PWR_DET_VAL_0_SD_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_VAL_0_SD_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_VAL_0_SD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_VAL_0_SD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_VAL_0_SD_ENABLE                      _MK_ENUM_CONST(0)
+#define APBDEV_PMC_PWR_DET_VAL_0_SD_DISABLE                     _MK_ENUM_CONST(1)
+
+
+// Register APBDEV_PMC_DDR_PWR_0  
+#define APBDEV_PMC_DDR_PWR_0                    _MK_ADDR_CONST(0xe8)
+#define APBDEV_PMC_DDR_PWR_0_SECURE                     0x0
+#define APBDEV_PMC_DDR_PWR_0_WORD_COUNT                         0x1
+#define APBDEV_PMC_DDR_PWR_0_RESET_VAL                  _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DDR_PWR_0_RESET_MASK                         _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DDR_PWR_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DDR_PWR_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DDR_PWR_0_READ_MASK                  _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DDR_PWR_0_WRITE_MASK                         _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DDR_PWR_0_VAL_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_DDR_PWR_0_VAL_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_PMC_DDR_PWR_0_VAL_SHIFT)
+#define APBDEV_PMC_DDR_PWR_0_VAL_RANGE                  0:0
+#define APBDEV_PMC_DDR_PWR_0_VAL_WOFFSET                        0x0
+#define APBDEV_PMC_DDR_PWR_0_VAL_DEFAULT                        _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DDR_PWR_0_VAL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DDR_PWR_0_VAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DDR_PWR_0_VAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DDR_PWR_0_VAL_E_12V                  _MK_ENUM_CONST(0)
+#define APBDEV_PMC_DDR_PWR_0_VAL_E_18V                  _MK_ENUM_CONST(1)
+
+
+// Register APBDEV_PMC_USB_DEBOUNCE_DEL_0  
+#define APBDEV_PMC_USB_DEBOUNCE_DEL_0                   _MK_ADDR_CONST(0xec)
+#define APBDEV_PMC_USB_DEBOUNCE_DEL_0_SECURE                    0x0
+#define APBDEV_PMC_USB_DEBOUNCE_DEL_0_WORD_COUNT                        0x1
+#define APBDEV_PMC_USB_DEBOUNCE_DEL_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_USB_DEBOUNCE_DEL_0_RESET_MASK                        _MK_MASK_CONST(0xffff)
+#define APBDEV_PMC_USB_DEBOUNCE_DEL_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_USB_DEBOUNCE_DEL_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_USB_DEBOUNCE_DEL_0_READ_MASK                         _MK_MASK_CONST(0xffff)
+#define APBDEV_PMC_USB_DEBOUNCE_DEL_0_WRITE_MASK                        _MK_MASK_CONST(0xffff)
+#define APBDEV_PMC_USB_DEBOUNCE_DEL_0_VAL_SHIFT                 _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_USB_DEBOUNCE_DEL_0_VAL_FIELD                 (_MK_MASK_CONST(0xffff) << APBDEV_PMC_USB_DEBOUNCE_DEL_0_VAL_SHIFT)
+#define APBDEV_PMC_USB_DEBOUNCE_DEL_0_VAL_RANGE                 15:0
+#define APBDEV_PMC_USB_DEBOUNCE_DEL_0_VAL_WOFFSET                       0x0
+#define APBDEV_PMC_USB_DEBOUNCE_DEL_0_VAL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_USB_DEBOUNCE_DEL_0_VAL_DEFAULT_MASK                  _MK_MASK_CONST(0xffff)
+#define APBDEV_PMC_USB_DEBOUNCE_DEL_0_VAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_USB_DEBOUNCE_DEL_0_VAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_USB_AO_0  
+#define APBDEV_PMC_USB_AO_0                     _MK_ADDR_CONST(0xf0)
+#define APBDEV_PMC_USB_AO_0_SECURE                      0x0
+#define APBDEV_PMC_USB_AO_0_WORD_COUNT                  0x1
+#define APBDEV_PMC_USB_AO_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_USB_AO_0_RESET_MASK                  _MK_MASK_CONST(0xf)
+#define APBDEV_PMC_USB_AO_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_USB_AO_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_USB_AO_0_READ_MASK                   _MK_MASK_CONST(0xf)
+#define APBDEV_PMC_USB_AO_0_WRITE_MASK                  _MK_MASK_CONST(0xf)
+#define APBDEV_PMC_USB_AO_0_UB_ID_PD_SHIFT                      _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_USB_AO_0_UB_ID_PD_FIELD                      (_MK_MASK_CONST(0x3) << APBDEV_PMC_USB_AO_0_UB_ID_PD_SHIFT)
+#define APBDEV_PMC_USB_AO_0_UB_ID_PD_RANGE                      1:0
+#define APBDEV_PMC_USB_AO_0_UB_ID_PD_WOFFSET                    0x0
+#define APBDEV_PMC_USB_AO_0_UB_ID_PD_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_USB_AO_0_UB_ID_PD_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APBDEV_PMC_USB_AO_0_UB_ID_PD_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_USB_AO_0_UB_ID_PD_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APBDEV_PMC_USB_AO_0_VBUS_WAKEUP_PD_SHIFT                        _MK_SHIFT_CONST(2)
+#define APBDEV_PMC_USB_AO_0_VBUS_WAKEUP_PD_FIELD                        (_MK_MASK_CONST(0x3) << APBDEV_PMC_USB_AO_0_VBUS_WAKEUP_PD_SHIFT)
+#define APBDEV_PMC_USB_AO_0_VBUS_WAKEUP_PD_RANGE                        3:2
+#define APBDEV_PMC_USB_AO_0_VBUS_WAKEUP_PD_WOFFSET                      0x0
+#define APBDEV_PMC_USB_AO_0_VBUS_WAKEUP_PD_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_USB_AO_0_VBUS_WAKEUP_PD_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define APBDEV_PMC_USB_AO_0_VBUS_WAKEUP_PD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_USB_AO_0_VBUS_WAKEUP_PD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_CRYPTO_OP_0  
+#define APBDEV_PMC_CRYPTO_OP_0                  _MK_ADDR_CONST(0xf4)
+#define APBDEV_PMC_CRYPTO_OP_0_SECURE                   0x0
+#define APBDEV_PMC_CRYPTO_OP_0_WORD_COUNT                       0x1
+#define APBDEV_PMC_CRYPTO_OP_0_RESET_VAL                        _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_CRYPTO_OP_0_RESET_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_CRYPTO_OP_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CRYPTO_OP_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CRYPTO_OP_0_READ_MASK                        _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_CRYPTO_OP_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
+//Disabled by default
+#define APBDEV_PMC_CRYPTO_OP_0_VAL_SHIFT                        _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_CRYPTO_OP_0_VAL_FIELD                        (_MK_MASK_CONST(0x1) << APBDEV_PMC_CRYPTO_OP_0_VAL_SHIFT)
+#define APBDEV_PMC_CRYPTO_OP_0_VAL_RANGE                        0:0
+#define APBDEV_PMC_CRYPTO_OP_0_VAL_WOFFSET                      0x0
+#define APBDEV_PMC_CRYPTO_OP_0_VAL_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_CRYPTO_OP_0_VAL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_CRYPTO_OP_0_VAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CRYPTO_OP_0_VAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CRYPTO_OP_0_VAL_ENABLE                       _MK_ENUM_CONST(0)
+#define APBDEV_PMC_CRYPTO_OP_0_VAL_DISABLE                      _MK_ENUM_CONST(1)
+
+
+// Register APBDEV_PMC_PLLP_WB0_OVERRIDE_0  
+#define APBDEV_PMC_PLLP_WB0_OVERRIDE_0                  _MK_ADDR_CONST(0xf8)
+#define APBDEV_PMC_PLLP_WB0_OVERRIDE_0_SECURE                   0x0
+#define APBDEV_PMC_PLLP_WB0_OVERRIDE_0_WORD_COUNT                       0x1
+#define APBDEV_PMC_PLLP_WB0_OVERRIDE_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PLLP_WB0_OVERRIDE_0_RESET_MASK                       _MK_MASK_CONST(0xf)
+#define APBDEV_PMC_PLLP_WB0_OVERRIDE_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PLLP_WB0_OVERRIDE_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PLLP_WB0_OVERRIDE_0_READ_MASK                        _MK_MASK_CONST(0xf)
+#define APBDEV_PMC_PLLP_WB0_OVERRIDE_0_WRITE_MASK                       _MK_MASK_CONST(0xf)
+#define APBDEV_PMC_PLLP_WB0_OVERRIDE_0_VAL_SHIFT                        _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_PLLP_WB0_OVERRIDE_0_VAL_FIELD                        (_MK_MASK_CONST(0xf) << APBDEV_PMC_PLLP_WB0_OVERRIDE_0_VAL_SHIFT)
+#define APBDEV_PMC_PLLP_WB0_OVERRIDE_0_VAL_RANGE                        3:0
+#define APBDEV_PMC_PLLP_WB0_OVERRIDE_0_VAL_WOFFSET                      0x0
+#define APBDEV_PMC_PLLP_WB0_OVERRIDE_0_VAL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PLLP_WB0_OVERRIDE_0_VAL_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define APBDEV_PMC_PLLP_WB0_OVERRIDE_0_VAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PLLP_WB0_OVERRIDE_0_VAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// 1 = override CAR PLLP setting, 0 = no override.
+#define APBDEV_PMC_PLLP_WB0_OVERRIDE_0_OVERRIDE_ENABLE_SHIFT                    _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_PLLP_WB0_OVERRIDE_0_OVERRIDE_ENABLE_FIELD                    (_MK_MASK_CONST(0x1) << APBDEV_PMC_PLLP_WB0_OVERRIDE_0_OVERRIDE_ENABLE_SHIFT)
+#define APBDEV_PMC_PLLP_WB0_OVERRIDE_0_OVERRIDE_ENABLE_RANGE                    0:0
+#define APBDEV_PMC_PLLP_WB0_OVERRIDE_0_OVERRIDE_ENABLE_WOFFSET                  0x0
+#define APBDEV_PMC_PLLP_WB0_OVERRIDE_0_OVERRIDE_ENABLE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PLLP_WB0_OVERRIDE_0_OVERRIDE_ENABLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PLLP_WB0_OVERRIDE_0_OVERRIDE_ENABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PLLP_WB0_OVERRIDE_0_OVERRIDE_ENABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// 1 = enable PLLP, 0 = disable PLLP.
+#define APBDEV_PMC_PLLP_WB0_OVERRIDE_0_PLLP_ENABLE_SHIFT                        _MK_SHIFT_CONST(1)
+#define APBDEV_PMC_PLLP_WB0_OVERRIDE_0_PLLP_ENABLE_FIELD                        (_MK_MASK_CONST(0x1) << APBDEV_PMC_PLLP_WB0_OVERRIDE_0_PLLP_ENABLE_SHIFT)
+#define APBDEV_PMC_PLLP_WB0_OVERRIDE_0_PLLP_ENABLE_RANGE                        1:1
+#define APBDEV_PMC_PLLP_WB0_OVERRIDE_0_PLLP_ENABLE_WOFFSET                      0x0
+#define APBDEV_PMC_PLLP_WB0_OVERRIDE_0_PLLP_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PLLP_WB0_OVERRIDE_0_PLLP_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PLLP_WB0_OVERRIDE_0_PLLP_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PLLP_WB0_OVERRIDE_0_PLLP_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// 00 = 13MHz, 01 = 19.2MHz, 10 = 12MHz, 11 = 26MHz.
+#define APBDEV_PMC_PLLP_WB0_OVERRIDE_0_OSC_FREQ_SHIFT                   _MK_SHIFT_CONST(2)
+#define APBDEV_PMC_PLLP_WB0_OVERRIDE_0_OSC_FREQ_FIELD                   (_MK_MASK_CONST(0x3) << APBDEV_PMC_PLLP_WB0_OVERRIDE_0_OSC_FREQ_SHIFT)
+#define APBDEV_PMC_PLLP_WB0_OVERRIDE_0_OSC_FREQ_RANGE                   3:2
+#define APBDEV_PMC_PLLP_WB0_OVERRIDE_0_OSC_FREQ_WOFFSET                 0x0
+#define APBDEV_PMC_PLLP_WB0_OVERRIDE_0_OSC_FREQ_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PLLP_WB0_OVERRIDE_0_OSC_FREQ_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APBDEV_PMC_PLLP_WB0_OVERRIDE_0_OSC_FREQ_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PLLP_WB0_OVERRIDE_0_OSC_FREQ_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH24_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH24_0                  _MK_ADDR_CONST(0xfc)
+#define APBDEV_PMC_SCRATCH24_0_SECURE                   0x0
+#define APBDEV_PMC_SCRATCH24_0_WORD_COUNT                       0x1
+#define APBDEV_PMC_SCRATCH24_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH24_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH24_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH24_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH24_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH24_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH24_0_SCRATCH24_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH24_0_SCRATCH24_FIELD                  (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH24_0_SCRATCH24_SHIFT)
+#define APBDEV_PMC_SCRATCH24_0_SCRATCH24_RANGE                  31:0
+#define APBDEV_PMC_SCRATCH24_0_SCRATCH24_WOFFSET                        0x0
+#define APBDEV_PMC_SCRATCH24_0_SCRATCH24_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH24_0_SCRATCH24_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH24_0_SCRATCH24_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH24_0_SCRATCH24_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH25_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH25_0                  _MK_ADDR_CONST(0x100)
+#define APBDEV_PMC_SCRATCH25_0_SECURE                   0x0
+#define APBDEV_PMC_SCRATCH25_0_WORD_COUNT                       0x1
+#define APBDEV_PMC_SCRATCH25_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH25_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH25_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH25_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH25_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH25_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH25_0_SCRATCH25_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH25_0_SCRATCH25_FIELD                  (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH25_0_SCRATCH25_SHIFT)
+#define APBDEV_PMC_SCRATCH25_0_SCRATCH25_RANGE                  31:0
+#define APBDEV_PMC_SCRATCH25_0_SCRATCH25_WOFFSET                        0x0
+#define APBDEV_PMC_SCRATCH25_0_SCRATCH25_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH25_0_SCRATCH25_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH25_0_SCRATCH25_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH25_0_SCRATCH25_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH26_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH26_0                  _MK_ADDR_CONST(0x104)
+#define APBDEV_PMC_SCRATCH26_0_SECURE                   0x0
+#define APBDEV_PMC_SCRATCH26_0_WORD_COUNT                       0x1
+#define APBDEV_PMC_SCRATCH26_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH26_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH26_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH26_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH26_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH26_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH26_0_SCRATCH26_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH26_0_SCRATCH26_FIELD                  (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH26_0_SCRATCH26_SHIFT)
+#define APBDEV_PMC_SCRATCH26_0_SCRATCH26_RANGE                  31:0
+#define APBDEV_PMC_SCRATCH26_0_SCRATCH26_WOFFSET                        0x0
+#define APBDEV_PMC_SCRATCH26_0_SCRATCH26_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH26_0_SCRATCH26_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH26_0_SCRATCH26_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH26_0_SCRATCH26_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH27_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH27_0                  _MK_ADDR_CONST(0x108)
+#define APBDEV_PMC_SCRATCH27_0_SECURE                   0x0
+#define APBDEV_PMC_SCRATCH27_0_WORD_COUNT                       0x1
+#define APBDEV_PMC_SCRATCH27_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH27_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH27_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH27_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH27_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH27_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH27_0_SCRATCH27_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH27_0_SCRATCH27_FIELD                  (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH27_0_SCRATCH27_SHIFT)
+#define APBDEV_PMC_SCRATCH27_0_SCRATCH27_RANGE                  31:0
+#define APBDEV_PMC_SCRATCH27_0_SCRATCH27_WOFFSET                        0x0
+#define APBDEV_PMC_SCRATCH27_0_SCRATCH27_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH27_0_SCRATCH27_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH27_0_SCRATCH27_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH27_0_SCRATCH27_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH28_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH28_0                  _MK_ADDR_CONST(0x10c)
+#define APBDEV_PMC_SCRATCH28_0_SECURE                   0x0
+#define APBDEV_PMC_SCRATCH28_0_WORD_COUNT                       0x1
+#define APBDEV_PMC_SCRATCH28_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH28_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH28_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH28_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH28_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH28_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH28_0_SCRATCH28_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH28_0_SCRATCH28_FIELD                  (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH28_0_SCRATCH28_SHIFT)
+#define APBDEV_PMC_SCRATCH28_0_SCRATCH28_RANGE                  31:0
+#define APBDEV_PMC_SCRATCH28_0_SCRATCH28_WOFFSET                        0x0
+#define APBDEV_PMC_SCRATCH28_0_SCRATCH28_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH28_0_SCRATCH28_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH28_0_SCRATCH28_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH28_0_SCRATCH28_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH29_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH29_0                  _MK_ADDR_CONST(0x110)
+#define APBDEV_PMC_SCRATCH29_0_SECURE                   0x0
+#define APBDEV_PMC_SCRATCH29_0_WORD_COUNT                       0x1
+#define APBDEV_PMC_SCRATCH29_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH29_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH29_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH29_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH29_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH29_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH29_0_SCRATCH29_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH29_0_SCRATCH29_FIELD                  (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH29_0_SCRATCH29_SHIFT)
+#define APBDEV_PMC_SCRATCH29_0_SCRATCH29_RANGE                  31:0
+#define APBDEV_PMC_SCRATCH29_0_SCRATCH29_WOFFSET                        0x0
+#define APBDEV_PMC_SCRATCH29_0_SCRATCH29_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH29_0_SCRATCH29_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH29_0_SCRATCH29_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH29_0_SCRATCH29_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH30_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH30_0                  _MK_ADDR_CONST(0x114)
+#define APBDEV_PMC_SCRATCH30_0_SECURE                   0x0
+#define APBDEV_PMC_SCRATCH30_0_WORD_COUNT                       0x1
+#define APBDEV_PMC_SCRATCH30_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH30_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH30_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH30_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH30_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH30_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH30_0_SCRATCH30_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH30_0_SCRATCH30_FIELD                  (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH30_0_SCRATCH30_SHIFT)
+#define APBDEV_PMC_SCRATCH30_0_SCRATCH30_RANGE                  31:0
+#define APBDEV_PMC_SCRATCH30_0_SCRATCH30_WOFFSET                        0x0
+#define APBDEV_PMC_SCRATCH30_0_SCRATCH30_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH30_0_SCRATCH30_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH30_0_SCRATCH30_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH30_0_SCRATCH30_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH31_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH31_0                  _MK_ADDR_CONST(0x118)
+#define APBDEV_PMC_SCRATCH31_0_SECURE                   0x0
+#define APBDEV_PMC_SCRATCH31_0_WORD_COUNT                       0x1
+#define APBDEV_PMC_SCRATCH31_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH31_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH31_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH31_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH31_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH31_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH31_0_SCRATCH31_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH31_0_SCRATCH31_FIELD                  (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH31_0_SCRATCH31_SHIFT)
+#define APBDEV_PMC_SCRATCH31_0_SCRATCH31_RANGE                  31:0
+#define APBDEV_PMC_SCRATCH31_0_SCRATCH31_WOFFSET                        0x0
+#define APBDEV_PMC_SCRATCH31_0_SCRATCH31_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH31_0_SCRATCH31_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH31_0_SCRATCH31_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH31_0_SCRATCH31_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH32_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH32_0                  _MK_ADDR_CONST(0x11c)
+#define APBDEV_PMC_SCRATCH32_0_SECURE                   0x0
+#define APBDEV_PMC_SCRATCH32_0_WORD_COUNT                       0x1
+#define APBDEV_PMC_SCRATCH32_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH32_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH32_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH32_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH32_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH32_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH32_0_SCRATCH32_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH32_0_SCRATCH32_FIELD                  (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH32_0_SCRATCH32_SHIFT)
+#define APBDEV_PMC_SCRATCH32_0_SCRATCH32_RANGE                  31:0
+#define APBDEV_PMC_SCRATCH32_0_SCRATCH32_WOFFSET                        0x0
+#define APBDEV_PMC_SCRATCH32_0_SCRATCH32_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH32_0_SCRATCH32_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH32_0_SCRATCH32_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH32_0_SCRATCH32_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH33_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH33_0                  _MK_ADDR_CONST(0x120)
+#define APBDEV_PMC_SCRATCH33_0_SECURE                   0x0
+#define APBDEV_PMC_SCRATCH33_0_WORD_COUNT                       0x1
+#define APBDEV_PMC_SCRATCH33_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH33_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH33_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH33_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH33_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH33_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH33_0_SCRATCH33_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH33_0_SCRATCH33_FIELD                  (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH33_0_SCRATCH33_SHIFT)
+#define APBDEV_PMC_SCRATCH33_0_SCRATCH33_RANGE                  31:0
+#define APBDEV_PMC_SCRATCH33_0_SCRATCH33_WOFFSET                        0x0
+#define APBDEV_PMC_SCRATCH33_0_SCRATCH33_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH33_0_SCRATCH33_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH33_0_SCRATCH33_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH33_0_SCRATCH33_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH34_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH34_0                  _MK_ADDR_CONST(0x124)
+#define APBDEV_PMC_SCRATCH34_0_SECURE                   0x0
+#define APBDEV_PMC_SCRATCH34_0_WORD_COUNT                       0x1
+#define APBDEV_PMC_SCRATCH34_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH34_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH34_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH34_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH34_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH34_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH34_0_SCRATCH34_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH34_0_SCRATCH34_FIELD                  (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH34_0_SCRATCH34_SHIFT)
+#define APBDEV_PMC_SCRATCH34_0_SCRATCH34_RANGE                  31:0
+#define APBDEV_PMC_SCRATCH34_0_SCRATCH34_WOFFSET                        0x0
+#define APBDEV_PMC_SCRATCH34_0_SCRATCH34_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH34_0_SCRATCH34_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH34_0_SCRATCH34_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH34_0_SCRATCH34_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH35_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH35_0                  _MK_ADDR_CONST(0x128)
+#define APBDEV_PMC_SCRATCH35_0_SECURE                   0x0
+#define APBDEV_PMC_SCRATCH35_0_WORD_COUNT                       0x1
+#define APBDEV_PMC_SCRATCH35_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH35_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH35_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH35_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH35_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH35_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH35_0_SCRATCH35_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH35_0_SCRATCH35_FIELD                  (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH35_0_SCRATCH35_SHIFT)
+#define APBDEV_PMC_SCRATCH35_0_SCRATCH35_RANGE                  31:0
+#define APBDEV_PMC_SCRATCH35_0_SCRATCH35_WOFFSET                        0x0
+#define APBDEV_PMC_SCRATCH35_0_SCRATCH35_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH35_0_SCRATCH35_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH35_0_SCRATCH35_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH35_0_SCRATCH35_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH36_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH36_0                  _MK_ADDR_CONST(0x12c)
+#define APBDEV_PMC_SCRATCH36_0_SECURE                   0x0
+#define APBDEV_PMC_SCRATCH36_0_WORD_COUNT                       0x1
+#define APBDEV_PMC_SCRATCH36_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH36_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH36_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH36_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH36_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH36_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH36_0_SCRATCH36_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH36_0_SCRATCH36_FIELD                  (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH36_0_SCRATCH36_SHIFT)
+#define APBDEV_PMC_SCRATCH36_0_SCRATCH36_RANGE                  31:0
+#define APBDEV_PMC_SCRATCH36_0_SCRATCH36_WOFFSET                        0x0
+#define APBDEV_PMC_SCRATCH36_0_SCRATCH36_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH36_0_SCRATCH36_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH36_0_SCRATCH36_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH36_0_SCRATCH36_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH37_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH37_0                  _MK_ADDR_CONST(0x130)
+#define APBDEV_PMC_SCRATCH37_0_SECURE                   0x0
+#define APBDEV_PMC_SCRATCH37_0_WORD_COUNT                       0x1
+#define APBDEV_PMC_SCRATCH37_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH37_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH37_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH37_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH37_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH37_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH37_0_SCRATCH37_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH37_0_SCRATCH37_FIELD                  (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH37_0_SCRATCH37_SHIFT)
+#define APBDEV_PMC_SCRATCH37_0_SCRATCH37_RANGE                  31:0
+#define APBDEV_PMC_SCRATCH37_0_SCRATCH37_WOFFSET                        0x0
+#define APBDEV_PMC_SCRATCH37_0_SCRATCH37_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH37_0_SCRATCH37_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH37_0_SCRATCH37_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH37_0_SCRATCH37_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH38_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH38_0                  _MK_ADDR_CONST(0x134)
+#define APBDEV_PMC_SCRATCH38_0_SECURE                   0x0
+#define APBDEV_PMC_SCRATCH38_0_WORD_COUNT                       0x1
+#define APBDEV_PMC_SCRATCH38_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH38_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH38_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH38_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH38_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH38_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH38_0_SCRATCH38_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH38_0_SCRATCH38_FIELD                  (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH38_0_SCRATCH38_SHIFT)
+#define APBDEV_PMC_SCRATCH38_0_SCRATCH38_RANGE                  31:0
+#define APBDEV_PMC_SCRATCH38_0_SCRATCH38_WOFFSET                        0x0
+#define APBDEV_PMC_SCRATCH38_0_SCRATCH38_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH38_0_SCRATCH38_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH38_0_SCRATCH38_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH38_0_SCRATCH38_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH39_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH39_0                  _MK_ADDR_CONST(0x138)
+#define APBDEV_PMC_SCRATCH39_0_SECURE                   0x0
+#define APBDEV_PMC_SCRATCH39_0_WORD_COUNT                       0x1
+#define APBDEV_PMC_SCRATCH39_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH39_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH39_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH39_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH39_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH39_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH39_0_SCRATCH39_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH39_0_SCRATCH39_FIELD                  (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH39_0_SCRATCH39_SHIFT)
+#define APBDEV_PMC_SCRATCH39_0_SCRATCH39_RANGE                  31:0
+#define APBDEV_PMC_SCRATCH39_0_SCRATCH39_WOFFSET                        0x0
+#define APBDEV_PMC_SCRATCH39_0_SCRATCH39_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH39_0_SCRATCH39_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH39_0_SCRATCH39_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH39_0_SCRATCH39_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH40_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH40_0                  _MK_ADDR_CONST(0x13c)
+#define APBDEV_PMC_SCRATCH40_0_SECURE                   0x0
+#define APBDEV_PMC_SCRATCH40_0_WORD_COUNT                       0x1
+#define APBDEV_PMC_SCRATCH40_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH40_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH40_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH40_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH40_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH40_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH40_0_SCRATCH40_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH40_0_SCRATCH40_FIELD                  (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH40_0_SCRATCH40_SHIFT)
+#define APBDEV_PMC_SCRATCH40_0_SCRATCH40_RANGE                  31:0
+#define APBDEV_PMC_SCRATCH40_0_SCRATCH40_WOFFSET                        0x0
+#define APBDEV_PMC_SCRATCH40_0_SCRATCH40_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH40_0_SCRATCH40_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH40_0_SCRATCH40_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH40_0_SCRATCH40_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH41_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH41_0                  _MK_ADDR_CONST(0x140)
+#define APBDEV_PMC_SCRATCH41_0_SECURE                   0x0
+#define APBDEV_PMC_SCRATCH41_0_WORD_COUNT                       0x1
+#define APBDEV_PMC_SCRATCH41_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH41_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH41_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH41_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH41_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH41_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH41_0_SCRATCH41_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH41_0_SCRATCH41_FIELD                  (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH41_0_SCRATCH41_SHIFT)
+#define APBDEV_PMC_SCRATCH41_0_SCRATCH41_RANGE                  31:0
+#define APBDEV_PMC_SCRATCH41_0_SCRATCH41_WOFFSET                        0x0
+#define APBDEV_PMC_SCRATCH41_0_SCRATCH41_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH41_0_SCRATCH41_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH41_0_SCRATCH41_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH41_0_SCRATCH41_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH42_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH42_0                  _MK_ADDR_CONST(0x144)
+#define APBDEV_PMC_SCRATCH42_0_SECURE                   0x0
+#define APBDEV_PMC_SCRATCH42_0_WORD_COUNT                       0x1
+#define APBDEV_PMC_SCRATCH42_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH42_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH42_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH42_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH42_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH42_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH42_0_SCRATCH42_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH42_0_SCRATCH42_FIELD                  (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH42_0_SCRATCH42_SHIFT)
+#define APBDEV_PMC_SCRATCH42_0_SCRATCH42_RANGE                  31:0
+#define APBDEV_PMC_SCRATCH42_0_SCRATCH42_WOFFSET                        0x0
+#define APBDEV_PMC_SCRATCH42_0_SCRATCH42_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH42_0_SCRATCH42_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH42_0_SCRATCH42_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH42_0_SCRATCH42_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_BONDOUT_MIRROR0_0  // Secure scratch register
+#define APBDEV_PMC_BONDOUT_MIRROR0_0                    _MK_ADDR_CONST(0x148)
+#define APBDEV_PMC_BONDOUT_MIRROR0_0_SECURE                     0x0
+#define APBDEV_PMC_BONDOUT_MIRROR0_0_WORD_COUNT                         0x1
+#define APBDEV_PMC_BONDOUT_MIRROR0_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_BONDOUT_MIRROR0_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_BONDOUT_MIRROR0_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_BONDOUT_MIRROR0_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_BONDOUT_MIRROR0_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_BONDOUT_MIRROR0_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_BONDOUT_MIRROR0_0_BONDOUT_MIRROR0_SHIFT                      _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_BONDOUT_MIRROR0_0_BONDOUT_MIRROR0_FIELD                      (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_BONDOUT_MIRROR0_0_BONDOUT_MIRROR0_SHIFT)
+#define APBDEV_PMC_BONDOUT_MIRROR0_0_BONDOUT_MIRROR0_RANGE                      31:0
+#define APBDEV_PMC_BONDOUT_MIRROR0_0_BONDOUT_MIRROR0_WOFFSET                    0x0
+#define APBDEV_PMC_BONDOUT_MIRROR0_0_BONDOUT_MIRROR0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_BONDOUT_MIRROR0_0_BONDOUT_MIRROR0_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_BONDOUT_MIRROR0_0_BONDOUT_MIRROR0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_BONDOUT_MIRROR0_0_BONDOUT_MIRROR0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_BONDOUT_MIRROR1_0  // Secure scratch register
+#define APBDEV_PMC_BONDOUT_MIRROR1_0                    _MK_ADDR_CONST(0x14c)
+#define APBDEV_PMC_BONDOUT_MIRROR1_0_SECURE                     0x0
+#define APBDEV_PMC_BONDOUT_MIRROR1_0_WORD_COUNT                         0x1
+#define APBDEV_PMC_BONDOUT_MIRROR1_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_BONDOUT_MIRROR1_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_BONDOUT_MIRROR1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_BONDOUT_MIRROR1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_BONDOUT_MIRROR1_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_BONDOUT_MIRROR1_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_BONDOUT_MIRROR1_0_BONDOUT_MIRROR1_SHIFT                      _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_BONDOUT_MIRROR1_0_BONDOUT_MIRROR1_FIELD                      (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_BONDOUT_MIRROR1_0_BONDOUT_MIRROR1_SHIFT)
+#define APBDEV_PMC_BONDOUT_MIRROR1_0_BONDOUT_MIRROR1_RANGE                      31:0
+#define APBDEV_PMC_BONDOUT_MIRROR1_0_BONDOUT_MIRROR1_WOFFSET                    0x0
+#define APBDEV_PMC_BONDOUT_MIRROR1_0_BONDOUT_MIRROR1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_BONDOUT_MIRROR1_0_BONDOUT_MIRROR1_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_BONDOUT_MIRROR1_0_BONDOUT_MIRROR1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_BONDOUT_MIRROR1_0_BONDOUT_MIRROR1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_BONDOUT_MIRROR2_0  // Secure scratch register
+#define APBDEV_PMC_BONDOUT_MIRROR2_0                    _MK_ADDR_CONST(0x150)
+#define APBDEV_PMC_BONDOUT_MIRROR2_0_SECURE                     0x0
+#define APBDEV_PMC_BONDOUT_MIRROR2_0_WORD_COUNT                         0x1
+#define APBDEV_PMC_BONDOUT_MIRROR2_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_BONDOUT_MIRROR2_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_BONDOUT_MIRROR2_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_BONDOUT_MIRROR2_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_BONDOUT_MIRROR2_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_BONDOUT_MIRROR2_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_BONDOUT_MIRROR2_0_BONDOUT_MIRROR2_SHIFT                      _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_BONDOUT_MIRROR2_0_BONDOUT_MIRROR2_FIELD                      (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_BONDOUT_MIRROR2_0_BONDOUT_MIRROR2_SHIFT)
+#define APBDEV_PMC_BONDOUT_MIRROR2_0_BONDOUT_MIRROR2_RANGE                      31:0
+#define APBDEV_PMC_BONDOUT_MIRROR2_0_BONDOUT_MIRROR2_WOFFSET                    0x0
+#define APBDEV_PMC_BONDOUT_MIRROR2_0_BONDOUT_MIRROR2_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_BONDOUT_MIRROR2_0_BONDOUT_MIRROR2_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_BONDOUT_MIRROR2_0_BONDOUT_MIRROR2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_BONDOUT_MIRROR2_0_BONDOUT_MIRROR2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SYS_33V_EN_0  
+#define APBDEV_PMC_SYS_33V_EN_0                 _MK_ADDR_CONST(0x154)
+#define APBDEV_PMC_SYS_33V_EN_0_SECURE                  0x0
+#define APBDEV_PMC_SYS_33V_EN_0_WORD_COUNT                      0x1
+#define APBDEV_PMC_SYS_33V_EN_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SYS_33V_EN_0_RESET_MASK                      _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_SYS_33V_EN_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SYS_33V_EN_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SYS_33V_EN_0_READ_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_SYS_33V_EN_0_WRITE_MASK                      _MK_MASK_CONST(0x1)
+// 1 - 3.3v, 0 - 1.8v
+#define APBDEV_PMC_SYS_33V_EN_0_val_SHIFT                       _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SYS_33V_EN_0_val_FIELD                       (_MK_MASK_CONST(0x1) << APBDEV_PMC_SYS_33V_EN_0_val_SHIFT)
+#define APBDEV_PMC_SYS_33V_EN_0_val_RANGE                       0:0
+#define APBDEV_PMC_SYS_33V_EN_0_val_WOFFSET                     0x0
+#define APBDEV_PMC_SYS_33V_EN_0_val_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SYS_33V_EN_0_val_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_SYS_33V_EN_0_val_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SYS_33V_EN_0_val_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_BONDOUT_MIRROR_ACCESS_0  
+#define APBDEV_PMC_BONDOUT_MIRROR_ACCESS_0                      _MK_ADDR_CONST(0x158)
+#define APBDEV_PMC_BONDOUT_MIRROR_ACCESS_0_SECURE                       0x0
+#define APBDEV_PMC_BONDOUT_MIRROR_ACCESS_0_WORD_COUNT                   0x1
+#define APBDEV_PMC_BONDOUT_MIRROR_ACCESS_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_BONDOUT_MIRROR_ACCESS_0_RESET_MASK                   _MK_MASK_CONST(0x3)
+#define APBDEV_PMC_BONDOUT_MIRROR_ACCESS_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_BONDOUT_MIRROR_ACCESS_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_BONDOUT_MIRROR_ACCESS_0_READ_MASK                    _MK_MASK_CONST(0x3)
+#define APBDEV_PMC_BONDOUT_MIRROR_ACCESS_0_WRITE_MASK                   _MK_MASK_CONST(0x3)
+// disable write to bondout secure registers
+#define APBDEV_PMC_BONDOUT_MIRROR_ACCESS_0_BWRITE_SHIFT                 _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_BONDOUT_MIRROR_ACCESS_0_BWRITE_FIELD                 (_MK_MASK_CONST(0x1) << APBDEV_PMC_BONDOUT_MIRROR_ACCESS_0_BWRITE_SHIFT)
+#define APBDEV_PMC_BONDOUT_MIRROR_ACCESS_0_BWRITE_RANGE                 0:0
+#define APBDEV_PMC_BONDOUT_MIRROR_ACCESS_0_BWRITE_WOFFSET                       0x0
+#define APBDEV_PMC_BONDOUT_MIRROR_ACCESS_0_BWRITE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_BONDOUT_MIRROR_ACCESS_0_BWRITE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_BONDOUT_MIRROR_ACCESS_0_BWRITE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_BONDOUT_MIRROR_ACCESS_0_BWRITE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_BONDOUT_MIRROR_ACCESS_0_BWRITE_OFF                   _MK_ENUM_CONST(0)
+#define APBDEV_PMC_BONDOUT_MIRROR_ACCESS_0_BWRITE_ON                    _MK_ENUM_CONST(1)
+
+// disable read  from bondout secure registers
+#define APBDEV_PMC_BONDOUT_MIRROR_ACCESS_0_BREAD_SHIFT                  _MK_SHIFT_CONST(1)
+#define APBDEV_PMC_BONDOUT_MIRROR_ACCESS_0_BREAD_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_PMC_BONDOUT_MIRROR_ACCESS_0_BREAD_SHIFT)
+#define APBDEV_PMC_BONDOUT_MIRROR_ACCESS_0_BREAD_RANGE                  1:1
+#define APBDEV_PMC_BONDOUT_MIRROR_ACCESS_0_BREAD_WOFFSET                        0x0
+#define APBDEV_PMC_BONDOUT_MIRROR_ACCESS_0_BREAD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_BONDOUT_MIRROR_ACCESS_0_BREAD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_BONDOUT_MIRROR_ACCESS_0_BREAD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_BONDOUT_MIRROR_ACCESS_0_BREAD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_BONDOUT_MIRROR_ACCESS_0_BREAD_OFF                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_BONDOUT_MIRROR_ACCESS_0_BREAD_ON                     _MK_ENUM_CONST(1)
+
+
+// Register APBDEV_PMC_GATE_0  
+#define APBDEV_PMC_GATE_0                       _MK_ADDR_CONST(0x15c)
+#define APBDEV_PMC_GATE_0_SECURE                        0x0
+#define APBDEV_PMC_GATE_0_WORD_COUNT                    0x1
+#define APBDEV_PMC_GATE_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_GATE_0_RESET_MASK                    _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_GATE_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_GATE_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_GATE_0_READ_MASK                     _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_GATE_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_GATE_0_GATE_WAKE_SHIFT                       _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_GATE_0_GATE_WAKE_FIELD                       (_MK_MASK_CONST(0x1) << APBDEV_PMC_GATE_0_GATE_WAKE_SHIFT)
+#define APBDEV_PMC_GATE_0_GATE_WAKE_RANGE                       0:0
+#define APBDEV_PMC_GATE_0_GATE_WAKE_WOFFSET                     0x0
+#define APBDEV_PMC_GATE_0_GATE_WAKE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_GATE_0_GATE_WAKE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_GATE_0_GATE_WAKE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_GATE_0_GATE_WAKE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_GATE_0_GATE_WAKE_OFF                 _MK_ENUM_CONST(0)
+#define APBDEV_PMC_GATE_0_GATE_WAKE_ON                  _MK_ENUM_CONST(1)
+
+#define APBDEV_PMC_GATE_0_GATE_DBNS_SHIFT                       _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_GATE_0_GATE_DBNS_FIELD                       (_MK_MASK_CONST(0x1) << APBDEV_PMC_GATE_0_GATE_DBNS_SHIFT)
+#define APBDEV_PMC_GATE_0_GATE_DBNS_RANGE                       0:0
+#define APBDEV_PMC_GATE_0_GATE_DBNS_WOFFSET                     0x0
+#define APBDEV_PMC_GATE_0_GATE_DBNS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_GATE_0_GATE_DBNS_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_GATE_0_GATE_DBNS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_GATE_0_GATE_DBNS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_GATE_0_GATE_DBNS_OFF                 _MK_ENUM_CONST(0)
+#define APBDEV_PMC_GATE_0_GATE_DBNS_ON                  _MK_ENUM_CONST(1)
+
+
+//
+// REGISTER LIST
+//
+#define LIST_ARAPBPM_REGS(_op_) \
+_op_(APBDEV_PMC_CNTRL_0) \
+_op_(APBDEV_PMC_SEC_DISABLE_0) \
+_op_(APBDEV_PMC_PMC_SWRST_0) \
+_op_(APBDEV_PMC_WAKE_MASK_0) \
+_op_(APBDEV_PMC_WAKE_LVL_0) \
+_op_(APBDEV_PMC_WAKE_STATUS_0) \
+_op_(APBDEV_PMC_SW_WAKE_STATUS_0) \
+_op_(APBDEV_PMC_DPD_PADS_ORIDE_0) \
+_op_(APBDEV_PMC_DPD_SAMPLE_0) \
+_op_(APBDEV_PMC_DPD_ENABLE_0) \
+_op_(APBDEV_PMC_PWRGATE_TIMER_OFF_0) \
+_op_(APBDEV_PMC_PWRGATE_TIMER_ON_0) \
+_op_(APBDEV_PMC_PWRGATE_TOGGLE_0) \
+_op_(APBDEV_PMC_REMOVE_CLAMPING_CMD_0) \
+_op_(APBDEV_PMC_PWRGATE_STATUS_0) \
+_op_(APBDEV_PMC_PWRGOOD_TIMER_0) \
+_op_(APBDEV_PMC_BLINK_TIMER_0) \
+_op_(APBDEV_PMC_NO_IOPOWER_0) \
+_op_(APBDEV_PMC_PWR_DET_0) \
+_op_(APBDEV_PMC_PWR_DET_LATCH_0) \
+_op_(APBDEV_PMC_SCRATCH0_0) \
+_op_(APBDEV_PMC_SCRATCH1_0) \
+_op_(APBDEV_PMC_SCRATCH2_0) \
+_op_(APBDEV_PMC_SCRATCH3_0) \
+_op_(APBDEV_PMC_SCRATCH4_0) \
+_op_(APBDEV_PMC_SCRATCH5_0) \
+_op_(APBDEV_PMC_SCRATCH6_0) \
+_op_(APBDEV_PMC_SCRATCH7_0) \
+_op_(APBDEV_PMC_SCRATCH8_0) \
+_op_(APBDEV_PMC_SCRATCH9_0) \
+_op_(APBDEV_PMC_SCRATCH10_0) \
+_op_(APBDEV_PMC_SCRATCH11_0) \
+_op_(APBDEV_PMC_SCRATCH12_0) \
+_op_(APBDEV_PMC_SCRATCH13_0) \
+_op_(APBDEV_PMC_SCRATCH14_0) \
+_op_(APBDEV_PMC_SCRATCH15_0) \
+_op_(APBDEV_PMC_SCRATCH16_0) \
+_op_(APBDEV_PMC_SCRATCH17_0) \
+_op_(APBDEV_PMC_SCRATCH18_0) \
+_op_(APBDEV_PMC_SCRATCH19_0) \
+_op_(APBDEV_PMC_SCRATCH20_0) \
+_op_(APBDEV_PMC_SCRATCH21_0) \
+_op_(APBDEV_PMC_SCRATCH22_0) \
+_op_(APBDEV_PMC_SCRATCH23_0) \
+_op_(APBDEV_PMC_SECURE_SCRATCH0_0) \
+_op_(APBDEV_PMC_SECURE_SCRATCH1_0) \
+_op_(APBDEV_PMC_SECURE_SCRATCH2_0) \
+_op_(APBDEV_PMC_SECURE_SCRATCH3_0) \
+_op_(APBDEV_PMC_SECURE_SCRATCH4_0) \
+_op_(APBDEV_PMC_SECURE_SCRATCH5_0) \
+_op_(APBDEV_PMC_CPUPWRGOOD_TIMER_0) \
+_op_(APBDEV_PMC_CPUPWROFF_TIMER_0) \
+_op_(APBDEV_PMC_PG_MASK_0) \
+_op_(APBDEV_PMC_PG_MASK_1_0) \
+_op_(APBDEV_PMC_AUTO_WAKE_LVL_0) \
+_op_(APBDEV_PMC_AUTO_WAKE_LVL_MASK_0) \
+_op_(APBDEV_PMC_WAKE_DELAY_0) \
+_op_(APBDEV_PMC_PWR_DET_VAL_0) \
+_op_(APBDEV_PMC_DDR_PWR_0) \
+_op_(APBDEV_PMC_USB_DEBOUNCE_DEL_0) \
+_op_(APBDEV_PMC_USB_AO_0) \
+_op_(APBDEV_PMC_CRYPTO_OP_0) \
+_op_(APBDEV_PMC_PLLP_WB0_OVERRIDE_0) \
+_op_(APBDEV_PMC_SCRATCH24_0) \
+_op_(APBDEV_PMC_SCRATCH25_0) \
+_op_(APBDEV_PMC_SCRATCH26_0) \
+_op_(APBDEV_PMC_SCRATCH27_0) \
+_op_(APBDEV_PMC_SCRATCH28_0) \
+_op_(APBDEV_PMC_SCRATCH29_0) \
+_op_(APBDEV_PMC_SCRATCH30_0) \
+_op_(APBDEV_PMC_SCRATCH31_0) \
+_op_(APBDEV_PMC_SCRATCH32_0) \
+_op_(APBDEV_PMC_SCRATCH33_0) \
+_op_(APBDEV_PMC_SCRATCH34_0) \
+_op_(APBDEV_PMC_SCRATCH35_0) \
+_op_(APBDEV_PMC_SCRATCH36_0) \
+_op_(APBDEV_PMC_SCRATCH37_0) \
+_op_(APBDEV_PMC_SCRATCH38_0) \
+_op_(APBDEV_PMC_SCRATCH39_0) \
+_op_(APBDEV_PMC_SCRATCH40_0) \
+_op_(APBDEV_PMC_SCRATCH41_0) \
+_op_(APBDEV_PMC_SCRATCH42_0) \
+_op_(APBDEV_PMC_BONDOUT_MIRROR0_0) \
+_op_(APBDEV_PMC_BONDOUT_MIRROR1_0) \
+_op_(APBDEV_PMC_BONDOUT_MIRROR2_0) \
+_op_(APBDEV_PMC_SYS_33V_EN_0) \
+_op_(APBDEV_PMC_BONDOUT_MIRROR_ACCESS_0) \
+_op_(APBDEV_PMC_GATE_0)
+
+
+//
+// ADDRESS SPACES
+//
+
+#define BASE_ADDRESS_APBDEV_PMC 0x00000000
+
+//
+// ARAPBPM REGISTER BANKS
+//
+
+#define APBDEV_PMC0_FIRST_REG 0x0000 // APBDEV_PMC_CNTRL_0
+#define APBDEV_PMC0_LAST_REG 0x015c // APBDEV_PMC_GATE_0
+
+#ifndef _MK_SHIFT_CONST
+  #define _MK_SHIFT_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_MASK_CONST
+  #define _MK_MASK_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_ENUM_CONST
+  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
+#endif
+#ifndef _MK_ADDR_CONST
+  #define _MK_ADDR_CONST(_constant_) _constant_
+#endif
+
+#endif // ifndef ___ARAPBPM_H_INC_
diff --git a/arch/arm/mach-tegra/include/ap20/arclk_rst.h b/arch/arm/mach-tegra/include/ap20/arclk_rst.h
new file mode 100644
index 000000000000..fbcc898df117
--- /dev/null
+++ b/arch/arm/mach-tegra/include/ap20/arclk_rst.h
@@ -0,0 +1,12976 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+//
+// DO NOT EDIT - generated by simspec!
+//
+
+#ifndef ___ARCLK_RST_H_INC_
+#define ___ARCLK_RST_H_INC_
+
+// Register CLK_RST_CONTROLLER_RST_SOURCE_0  
+#define CLK_RST_CONTROLLER_RST_SOURCE_0                 _MK_ADDR_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_SECURE                  0x0
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WORD_COUNT                      0x1
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_RESET_MASK                      _MK_MASK_CONST(0x3f37)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_READ_MASK                       _MK_MASK_CONST(0x3f37)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WRITE_MASK                      _MK_MASK_CONST(0x37)
+// System reset by SW (RO)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_SWR_SYS_RST_STA_SHIFT                   _MK_SHIFT_CONST(13)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_SWR_SYS_RST_STA_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_SOURCE_0_SWR_SYS_RST_STA_SHIFT)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_SWR_SYS_RST_STA_RANGE                   13:13
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_SWR_SYS_RST_STA_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_SWR_SYS_RST_STA_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_SWR_SYS_RST_STA_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_SWR_SYS_RST_STA_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_SWR_SYS_RST_STA_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// System reset by watch dog timer (RO)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SYS_RST_STA_SHIFT                   _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SYS_RST_STA_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SYS_RST_STA_SHIFT)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SYS_RST_STA_RANGE                   12:12
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SYS_RST_STA_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SYS_RST_STA_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SYS_RST_STA_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SYS_RST_STA_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SYS_RST_STA_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// COP reset by SW (RO)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_SWR_COP_RST_STA_SHIFT                   _MK_SHIFT_CONST(11)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_SWR_COP_RST_STA_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_SOURCE_0_SWR_COP_RST_STA_SHIFT)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_SWR_COP_RST_STA_RANGE                   11:11
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_SWR_COP_RST_STA_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_SWR_COP_RST_STA_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_SWR_COP_RST_STA_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_SWR_COP_RST_STA_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_SWR_COP_RST_STA_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// COP reset by watch dog timer (RO)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_COP_RST_STA_SHIFT                   _MK_SHIFT_CONST(10)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_COP_RST_STA_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_COP_RST_STA_SHIFT)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_COP_RST_STA_RANGE                   10:10
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_COP_RST_STA_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_COP_RST_STA_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_COP_RST_STA_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_COP_RST_STA_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_COP_RST_STA_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// CPU reset by SW (RO)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_SWR_CPU_RST_STA_SHIFT                   _MK_SHIFT_CONST(9)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_SWR_CPU_RST_STA_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_SOURCE_0_SWR_CPU_RST_STA_SHIFT)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_SWR_CPU_RST_STA_RANGE                   9:9
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_SWR_CPU_RST_STA_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_SWR_CPU_RST_STA_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_SWR_CPU_RST_STA_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_SWR_CPU_RST_STA_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_SWR_CPU_RST_STA_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// CPU reset by watch dog timer (RO)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_CPU_RST_STA_SHIFT                   _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_CPU_RST_STA_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_CPU_RST_STA_SHIFT)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_CPU_RST_STA_RANGE                   8:8
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_CPU_RST_STA_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_CPU_RST_STA_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_CPU_RST_STA_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_CPU_RST_STA_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_CPU_RST_STA_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Enable Watch Dog Timer (Dead Man Timer)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_EN_SHIFT                    _MK_SHIFT_CONST(5)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_EN_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_EN_SHIFT)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_EN_RANGE                    5:5
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_EN_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_EN_INIT_ENUM                        DISABLE
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_EN_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_EN_ENABLE                   _MK_ENUM_CONST(1)
+
+// Watch Dog Timer Select
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SEL_SHIFT                   _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SEL_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SEL_SHIFT)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SEL_RANGE                   4:4
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SEL_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SEL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SEL_INIT_ENUM                       TIMER1
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SEL_TIMER1                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SEL_TIMER2                  _MK_ENUM_CONST(1)
+
+// Enable Watch Dog Timer reset for system.
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SYS_RST_EN_SHIFT                    _MK_SHIFT_CONST(2)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SYS_RST_EN_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SYS_RST_EN_SHIFT)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SYS_RST_EN_RANGE                    2:2
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SYS_RST_EN_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SYS_RST_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SYS_RST_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SYS_RST_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SYS_RST_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SYS_RST_EN_INIT_ENUM                        DISABLE
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SYS_RST_EN_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SYS_RST_EN_ENABLE                   _MK_ENUM_CONST(1)
+
+// Enable Watch Dog Timer reset for COP
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_COP_RST_EN_SHIFT                    _MK_SHIFT_CONST(1)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_COP_RST_EN_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_COP_RST_EN_SHIFT)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_COP_RST_EN_RANGE                    1:1
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_COP_RST_EN_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_COP_RST_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_COP_RST_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_COP_RST_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_COP_RST_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_COP_RST_EN_INIT_ENUM                        DISABLE
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_COP_RST_EN_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_COP_RST_EN_ENABLE                   _MK_ENUM_CONST(1)
+
+// Enable Watch Dog Timer reset for CPU
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_CPU_RST_EN_SHIFT                    _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_CPU_RST_EN_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_CPU_RST_EN_SHIFT)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_CPU_RST_EN_RANGE                    0:0
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_CPU_RST_EN_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_CPU_RST_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_CPU_RST_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_CPU_RST_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_CPU_RST_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_CPU_RST_EN_INIT_ENUM                        DISABLE
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_CPU_RST_EN_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_CPU_RST_EN_ENABLE                   _MK_ENUM_CONST(1)
+
+
+// Register CLK_RST_CONTROLLER_RST_DEVICES_L_0  
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0                      _MK_ADDR_CONST(0x4)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SECURE                       0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_WORD_COUNT                   0x1
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_RESET_VAL                    _MK_MASK_CONST(0x3ffffec9)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_RESET_MASK                   _MK_MASK_CONST(0xbfffffff)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_READ_MASK                    _MK_MASK_CONST(0xbfffffff)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_WRITE_MASK                   _MK_MASK_CONST(0xbfffffff)
+// Reset COP cache controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CACHE2_RST_SHIFT                 _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CACHE2_RST_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CACHE2_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CACHE2_RST_RANGE                 31:31
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CACHE2_RST_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CACHE2_RST_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CACHE2_RST_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CACHE2_RST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CACHE2_RST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CACHE2_RST_INIT_ENUM                     DISABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CACHE2_RST_DISABLE                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CACHE2_RST_ENABLE                        _MK_ENUM_CONST(1)
+
+// Reset vector co-processor.
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_VCP_RST_SHIFT                    _MK_SHIFT_CONST(29)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_VCP_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_VCP_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_VCP_RST_RANGE                    29:29
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_VCP_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_VCP_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_VCP_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_VCP_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_VCP_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_VCP_RST_INIT_ENUM                        ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_VCP_RST_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_VCP_RST_ENABLE                   _MK_ENUM_CONST(1)
+
+// Reset HOST1X.
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_HOST1X_RST_SHIFT                 _MK_SHIFT_CONST(28)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_HOST1X_RST_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_HOST1X_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_HOST1X_RST_RANGE                 28:28
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_HOST1X_RST_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_HOST1X_RST_DEFAULT                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_HOST1X_RST_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_HOST1X_RST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_HOST1X_RST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_HOST1X_RST_INIT_ENUM                     ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_HOST1X_RST_DISABLE                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_HOST1X_RST_ENABLE                        _MK_ENUM_CONST(1)
+
+// Reset DISP1 controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_DISP1_RST_SHIFT                  _MK_SHIFT_CONST(27)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_DISP1_RST_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_DISP1_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_DISP1_RST_RANGE                  27:27
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_DISP1_RST_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_DISP1_RST_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_DISP1_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_DISP1_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_DISP1_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_DISP1_RST_INIT_ENUM                      ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_DISP1_RST_DISABLE                        _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_DISP1_RST_ENABLE                 _MK_ENUM_CONST(1)
+
+// Reset DISP2 controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_DISP2_RST_SHIFT                  _MK_SHIFT_CONST(26)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_DISP2_RST_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_DISP2_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_DISP2_RST_RANGE                  26:26
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_DISP2_RST_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_DISP2_RST_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_DISP2_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_DISP2_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_DISP2_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_DISP2_RST_INIT_ENUM                      ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_DISP2_RST_DISABLE                        _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_DISP2_RST_ENABLE                 _MK_ENUM_CONST(1)
+
+// Reset IDE controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_IDE_RST_SHIFT                    _MK_SHIFT_CONST(25)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_IDE_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_IDE_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_IDE_RST_RANGE                    25:25
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_IDE_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_IDE_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_IDE_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_IDE_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_IDE_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_IDE_RST_INIT_ENUM                        ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_IDE_RST_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_IDE_RST_ENABLE                   _MK_ENUM_CONST(1)
+
+// Reset 3D controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_3D_RST_SHIFT                     _MK_SHIFT_CONST(24)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_3D_RST_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_3D_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_3D_RST_RANGE                     24:24
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_3D_RST_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_3D_RST_DEFAULT                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_3D_RST_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_3D_RST_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_3D_RST_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_3D_RST_INIT_ENUM                 ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_3D_RST_DISABLE                   _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_3D_RST_ENABLE                    _MK_ENUM_CONST(1)
+
+// Reset ISP controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_ISP_RST_SHIFT                    _MK_SHIFT_CONST(23)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_ISP_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_ISP_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_ISP_RST_RANGE                    23:23
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_ISP_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_ISP_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_ISP_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_ISP_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_ISP_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_ISP_RST_INIT_ENUM                        ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_ISP_RST_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_ISP_RST_ENABLE                   _MK_ENUM_CONST(1)
+
+// Reset USB controller
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_USBD_RST_SHIFT                   _MK_SHIFT_CONST(22)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_USBD_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_USBD_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_USBD_RST_RANGE                   22:22
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_USBD_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_USBD_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_USBD_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_USBD_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_USBD_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_USBD_RST_INIT_ENUM                       ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_USBD_RST_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_USBD_RST_ENABLE                  _MK_ENUM_CONST(1)
+
+// Reset 2D graphics engine controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_2D_RST_SHIFT                     _MK_SHIFT_CONST(21)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_2D_RST_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_2D_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_2D_RST_RANGE                     21:21
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_2D_RST_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_2D_RST_DEFAULT                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_2D_RST_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_2D_RST_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_2D_RST_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_2D_RST_INIT_ENUM                 ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_2D_RST_DISABLE                   _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_2D_RST_ENABLE                    _MK_ENUM_CONST(1)
+
+// Reset VI controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_VI_RST_SHIFT                     _MK_SHIFT_CONST(20)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_VI_RST_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_VI_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_VI_RST_RANGE                     20:20
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_VI_RST_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_VI_RST_DEFAULT                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_VI_RST_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_VI_RST_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_VI_RST_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_VI_RST_INIT_ENUM                 ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_VI_RST_DISABLE                   _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_VI_RST_ENABLE                    _MK_ENUM_CONST(1)
+
+// Reset EPP controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_EPP_RST_SHIFT                    _MK_SHIFT_CONST(19)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_EPP_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_EPP_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_EPP_RST_RANGE                    19:19
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_EPP_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_EPP_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_EPP_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_EPP_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_EPP_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_EPP_RST_INIT_ENUM                        ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_EPP_RST_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_EPP_RST_ENABLE                   _MK_ENUM_CONST(1)
+
+// Reset I2S 2 Controller
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2S2_RST_SHIFT                   _MK_SHIFT_CONST(18)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2S2_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2S2_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2S2_RST_RANGE                   18:18
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2S2_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2S2_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2S2_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2S2_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2S2_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2S2_RST_INIT_ENUM                       ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2S2_RST_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2S2_RST_ENABLE                  _MK_ENUM_CONST(1)
+
+// Reset Pulse Width Modulator
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_PWM_RST_SHIFT                    _MK_SHIFT_CONST(17)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_PWM_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_PWM_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_PWM_RST_RANGE                    17:17
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_PWM_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_PWM_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_PWM_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_PWM_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_PWM_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_PWM_RST_INIT_ENUM                        ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_PWM_RST_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_PWM_RST_ENABLE                   _MK_ENUM_CONST(1)
+
+// Reset Three Wire Controller
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TWC_RST_SHIFT                    _MK_SHIFT_CONST(16)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TWC_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TWC_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TWC_RST_RANGE                    16:16
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TWC_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TWC_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TWC_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TWC_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TWC_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TWC_RST_INIT_ENUM                        ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TWC_RST_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TWC_RST_ENABLE                   _MK_ENUM_CONST(1)
+
+// Reset SDMMC4 controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SDMMC4_RST_SHIFT                 _MK_SHIFT_CONST(15)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SDMMC4_RST_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SDMMC4_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SDMMC4_RST_RANGE                 15:15
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SDMMC4_RST_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SDMMC4_RST_DEFAULT                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SDMMC4_RST_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SDMMC4_RST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SDMMC4_RST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SDMMC4_RST_INIT_ENUM                     ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SDMMC4_RST_DISABLE                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SDMMC4_RST_ENABLE                        _MK_ENUM_CONST(1)
+
+// Reset SDMMC1 controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SDMMC1_RST_SHIFT                 _MK_SHIFT_CONST(14)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SDMMC1_RST_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SDMMC1_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SDMMC1_RST_RANGE                 14:14
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SDMMC1_RST_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SDMMC1_RST_DEFAULT                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SDMMC1_RST_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SDMMC1_RST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SDMMC1_RST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SDMMC1_RST_INIT_ENUM                     ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SDMMC1_RST_DISABLE                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SDMMC1_RST_ENABLE                        _MK_ENUM_CONST(1)
+
+// Reset NAND flash controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_NDFLASH_RST_SHIFT                        _MK_SHIFT_CONST(13)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_NDFLASH_RST_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_NDFLASH_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_NDFLASH_RST_RANGE                        13:13
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_NDFLASH_RST_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_NDFLASH_RST_DEFAULT                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_NDFLASH_RST_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_NDFLASH_RST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_NDFLASH_RST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_NDFLASH_RST_INIT_ENUM                    ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_NDFLASH_RST_DISABLE                      _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_NDFLASH_RST_ENABLE                       _MK_ENUM_CONST(1)
+
+// Reset I2C1 Controller
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2C1_RST_SHIFT                   _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2C1_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2C1_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2C1_RST_RANGE                   12:12
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2C1_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2C1_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2C1_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2C1_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2C1_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2C1_RST_INIT_ENUM                       ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2C1_RST_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2C1_RST_ENABLE                  _MK_ENUM_CONST(1)
+
+// Reset I2S 1 Controller
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2S1_RST_SHIFT                   _MK_SHIFT_CONST(11)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2S1_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2S1_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2S1_RST_RANGE                   11:11
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2S1_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2S1_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2S1_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2S1_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2S1_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2S1_RST_INIT_ENUM                       ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2S1_RST_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2S1_RST_ENABLE                  _MK_ENUM_CONST(1)
+
+// Reset SPDIF Controller
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SPDIF_RST_SHIFT                  _MK_SHIFT_CONST(10)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SPDIF_RST_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SPDIF_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SPDIF_RST_RANGE                  10:10
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SPDIF_RST_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SPDIF_RST_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SPDIF_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SPDIF_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SPDIF_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SPDIF_RST_INIT_ENUM                      ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SPDIF_RST_DISABLE                        _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SPDIF_RST_ENABLE                 _MK_ENUM_CONST(1)
+
+// Reset SDMMC2 Controller
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SDMMC2_RST_SHIFT                 _MK_SHIFT_CONST(9)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SDMMC2_RST_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SDMMC2_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SDMMC2_RST_RANGE                 9:9
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SDMMC2_RST_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SDMMC2_RST_DEFAULT                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SDMMC2_RST_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SDMMC2_RST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SDMMC2_RST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SDMMC2_RST_INIT_ENUM                     ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SDMMC2_RST_DISABLE                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SDMMC2_RST_ENABLE                        _MK_ENUM_CONST(1)
+
+// Reset GPIO Controller
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_GPIO_RST_SHIFT                   _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_GPIO_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_GPIO_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_GPIO_RST_RANGE                   8:8
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_GPIO_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_GPIO_RST_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_GPIO_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_GPIO_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_GPIO_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_GPIO_RST_INIT_ENUM                       DISABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_GPIO_RST_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_GPIO_RST_ENABLE                  _MK_ENUM_CONST(1)
+
+// Reset UARTB/VFIR Controller
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_UARTB_RST_SHIFT                  _MK_SHIFT_CONST(7)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_UARTB_RST_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_UARTB_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_UARTB_RST_RANGE                  7:7
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_UARTB_RST_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_UARTB_RST_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_UARTB_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_UARTB_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_UARTB_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_UARTB_RST_INIT_ENUM                      ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_UARTB_RST_DISABLE                        _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_UARTB_RST_ENABLE                 _MK_ENUM_CONST(1)
+
+// Reset UARTA Controller 
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_UARTA_RST_SHIFT                  _MK_SHIFT_CONST(6)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_UARTA_RST_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_UARTA_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_UARTA_RST_RANGE                  6:6
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_UARTA_RST_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_UARTA_RST_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_UARTA_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_UARTA_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_UARTA_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_UARTA_RST_INIT_ENUM                      ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_UARTA_RST_DISABLE                        _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_UARTA_RST_ENABLE                 _MK_ENUM_CONST(1)
+
+// Reset Timer Controller
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TMR_RST_SHIFT                    _MK_SHIFT_CONST(5)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TMR_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TMR_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TMR_RST_RANGE                    5:5
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TMR_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TMR_RST_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TMR_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TMR_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TMR_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TMR_RST_INIT_ENUM                        DISABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TMR_RST_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TMR_RST_ENABLE                   _MK_ENUM_CONST(1)
+
+// Reset RTC Controller
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_RTC_RST_SHIFT                    _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_RTC_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_RTC_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_RTC_RST_RANGE                    4:4
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_RTC_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_RTC_RST_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_RTC_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_RTC_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_RTC_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_RTC_RST_INIT_ENUM                        DISABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_RTC_RST_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_RTC_RST_ENABLE                   _MK_ENUM_CONST(1)
+
+// Reset AC97 Controller
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_AC97_RST_SHIFT                   _MK_SHIFT_CONST(3)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_AC97_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_AC97_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_AC97_RST_RANGE                   3:3
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_AC97_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_AC97_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_AC97_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_AC97_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_AC97_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_AC97_RST_INIT_ENUM                       ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_AC97_RST_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_AC97_RST_ENABLE                  _MK_ENUM_CONST(1)
+
+// Write 1 to pulse System Reset Signal. HW clears  this bit
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TRIG_SYS_RST_SHIFT                       _MK_SHIFT_CONST(2)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TRIG_SYS_RST_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TRIG_SYS_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TRIG_SYS_RST_RANGE                       2:2
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TRIG_SYS_RST_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TRIG_SYS_RST_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TRIG_SYS_RST_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TRIG_SYS_RST_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TRIG_SYS_RST_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TRIG_SYS_RST_INIT_ENUM                   DISABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TRIG_SYS_RST_DISABLE                     _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TRIG_SYS_RST_ENABLE                      _MK_ENUM_CONST(1)
+
+// Write 1 to force COP Reset Signal. SW needs to  clear this bit when done.
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_COP_RST_SHIFT                    _MK_SHIFT_CONST(1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_COP_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_COP_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_COP_RST_RANGE                    1:1
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_COP_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_COP_RST_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_COP_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_COP_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_COP_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_COP_RST_INIT_ENUM                        DISABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_COP_RST_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_COP_RST_ENABLE                   _MK_ENUM_CONST(1)
+
+// Write 1 to force CPU Reset Signal. SW needs to  clear this bit when done.
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CPU_RST_SHIFT                    _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CPU_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CPU_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CPU_RST_RANGE                    0:0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CPU_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CPU_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CPU_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CPU_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CPU_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CPU_RST_INIT_ENUM                        ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CPU_RST_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CPU_RST_ENABLE                   _MK_ENUM_CONST(1)
+
+
+// Register CLK_RST_CONTROLLER_RST_DEVICES_H_0  
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0                      _MK_ADDR_CONST(0x8)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SECURE                       0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_WORD_COUNT                   0x1
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_RESET_VAL                    _MK_MASK_CONST(0xfefffb77)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_RESET_MASK                   _MK_MASK_CONST(0xfefffff7)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_READ_MASK                    _MK_MASK_CONST(0xfefffff7)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_WRITE_MASK                   _MK_MASK_CONST(0xfefffff7)
+// Reset BSEV controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_BSEV_RST_SHIFT                   _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_BSEV_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_BSEV_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_BSEV_RST_RANGE                   31:31
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_BSEV_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_BSEV_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_BSEV_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_BSEV_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_BSEV_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_BSEV_RST_INIT_ENUM                       ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_BSEV_RST_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_BSEV_RST_ENABLE                  _MK_ENUM_CONST(1)
+
+// Reset BSEA controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_BSEA_RST_SHIFT                   _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_BSEA_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_BSEA_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_BSEA_RST_RANGE                   30:30
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_BSEA_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_BSEA_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_BSEA_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_BSEA_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_BSEA_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_BSEA_RST_INIT_ENUM                       ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_BSEA_RST_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_BSEA_RST_ENABLE                  _MK_ENUM_CONST(1)
+
+// Reset VDE & BSEV controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_VDE_RST_SHIFT                    _MK_SHIFT_CONST(29)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_VDE_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_VDE_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_VDE_RST_RANGE                    29:29
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_VDE_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_VDE_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_VDE_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_VDE_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_VDE_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_VDE_RST_INIT_ENUM                        ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_VDE_RST_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_VDE_RST_ENABLE                   _MK_ENUM_CONST(1)
+
+// Reset MPE controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MPE_RST_SHIFT                    _MK_SHIFT_CONST(28)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MPE_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MPE_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MPE_RST_RANGE                    28:28
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MPE_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MPE_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MPE_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MPE_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MPE_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MPE_RST_INIT_ENUM                        ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MPE_RST_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MPE_RST_ENABLE                   _MK_ENUM_CONST(1)
+
+// Reset USB3 controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_USB3_RST_SHIFT                   _MK_SHIFT_CONST(27)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_USB3_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_USB3_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_USB3_RST_RANGE                   27:27
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_USB3_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_USB3_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_USB3_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_USB3_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_USB3_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_USB3_RST_INIT_ENUM                       ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_USB3_RST_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_USB3_RST_ENABLE                  _MK_ENUM_CONST(1)
+
+// Reset USB2 controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_USB2_RST_SHIFT                   _MK_SHIFT_CONST(26)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_USB2_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_USB2_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_USB2_RST_RANGE                   26:26
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_USB2_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_USB2_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_USB2_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_USB2_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_USB2_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_USB2_RST_INIT_ENUM                       ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_USB2_RST_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_USB2_RST_ENABLE                  _MK_ENUM_CONST(1)
+
+// Reset EMC controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_EMC_RST_SHIFT                    _MK_SHIFT_CONST(25)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_EMC_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_EMC_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_EMC_RST_RANGE                    25:25
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_EMC_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_EMC_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_EMC_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_EMC_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_EMC_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_EMC_RST_INIT_ENUM                        ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_EMC_RST_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_EMC_RST_ENABLE                   _MK_ENUM_CONST(1)
+
+// Reset UART C Controller
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_UARTC_RST_SHIFT                  _MK_SHIFT_CONST(23)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_UARTC_RST_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_UARTC_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_UARTC_RST_RANGE                  23:23
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_UARTC_RST_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_UARTC_RST_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_UARTC_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_UARTC_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_UARTC_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_UARTC_RST_INIT_ENUM                      ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_UARTC_RST_DISABLE                        _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_UARTC_RST_ENABLE                 _MK_ENUM_CONST(1)
+
+// Reset I2C 2 controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_I2C2_RST_SHIFT                   _MK_SHIFT_CONST(22)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_I2C2_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_I2C2_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_I2C2_RST_RANGE                   22:22
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_I2C2_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_I2C2_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_I2C2_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_I2C2_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_I2C2_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_I2C2_RST_INIT_ENUM                       ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_I2C2_RST_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_I2C2_RST_ENABLE                  _MK_ENUM_CONST(1)
+
+// Reset TVDAC controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_TVDAC_RST_SHIFT                  _MK_SHIFT_CONST(21)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_TVDAC_RST_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_TVDAC_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_TVDAC_RST_RANGE                  21:21
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_TVDAC_RST_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_TVDAC_RST_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_TVDAC_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_TVDAC_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_TVDAC_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_TVDAC_RST_INIT_ENUM                      ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_TVDAC_RST_DISABLE                        _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_TVDAC_RST_ENABLE                 _MK_ENUM_CONST(1)
+
+// Reset CSI controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_CSI_RST_SHIFT                    _MK_SHIFT_CONST(20)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_CSI_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_CSI_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_CSI_RST_RANGE                    20:20
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_CSI_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_CSI_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_CSI_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_CSI_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_CSI_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_CSI_RST_INIT_ENUM                        ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_CSI_RST_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_CSI_RST_ENABLE                   _MK_ENUM_CONST(1)
+
+// Reset HDMI
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_HDMI_RST_SHIFT                   _MK_SHIFT_CONST(19)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_HDMI_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_HDMI_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_HDMI_RST_RANGE                   19:19
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_HDMI_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_HDMI_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_HDMI_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_HDMI_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_HDMI_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_HDMI_RST_INIT_ENUM                       ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_HDMI_RST_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_HDMI_RST_ENABLE                  _MK_ENUM_CONST(1)
+
+// Reset MIPI base-band controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MIPI_RST_SHIFT                   _MK_SHIFT_CONST(18)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MIPI_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MIPI_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MIPI_RST_RANGE                   18:18
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MIPI_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MIPI_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MIPI_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MIPI_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MIPI_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MIPI_RST_INIT_ENUM                       ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MIPI_RST_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MIPI_RST_ENABLE                  _MK_ENUM_CONST(1)
+
+// Reset TVO/CVE controller
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_TVO_RST_SHIFT                    _MK_SHIFT_CONST(17)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_TVO_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_TVO_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_TVO_RST_RANGE                    17:17
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_TVO_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_TVO_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_TVO_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_TVO_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_TVO_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_TVO_RST_INIT_ENUM                        ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_TVO_RST_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_TVO_RST_ENABLE                   _MK_ENUM_CONST(1)
+
+// Reset DSI controller
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_DSI_RST_SHIFT                    _MK_SHIFT_CONST(16)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_DSI_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_DSI_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_DSI_RST_RANGE                    16:16
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_DSI_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_DSI_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_DSI_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_DSI_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_DSI_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_DSI_RST_INIT_ENUM                        ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_DSI_RST_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_DSI_RST_ENABLE                   _MK_ENUM_CONST(1)
+
+// Reset DVC-I2C Controller
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_DVC_I2C_RST_SHIFT                        _MK_SHIFT_CONST(15)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_DVC_I2C_RST_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_DVC_I2C_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_DVC_I2C_RST_RANGE                        15:15
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_DVC_I2C_RST_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_DVC_I2C_RST_DEFAULT                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_DVC_I2C_RST_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_DVC_I2C_RST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_DVC_I2C_RST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_DVC_I2C_RST_INIT_ENUM                    ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_DVC_I2C_RST_DISABLE                      _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_DVC_I2C_RST_ENABLE                       _MK_ENUM_CONST(1)
+
+// Reset SBC 3 Controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC3_RST_SHIFT                   _MK_SHIFT_CONST(14)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC3_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC3_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC3_RST_RANGE                   14:14
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC3_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC3_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC3_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC3_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC3_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC3_RST_INIT_ENUM                       ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC3_RST_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC3_RST_ENABLE                  _MK_ENUM_CONST(1)
+
+// Reset XIO controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_XIO_RST_SHIFT                    _MK_SHIFT_CONST(13)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_XIO_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_XIO_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_XIO_RST_RANGE                    13:13
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_XIO_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_XIO_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_XIO_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_XIO_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_XIO_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_XIO_RST_INIT_ENUM                        ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_XIO_RST_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_XIO_RST_ENABLE                   _MK_ENUM_CONST(1)
+
+// Reset SBC 2 Controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC2_RST_SHIFT                   _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC2_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC2_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC2_RST_RANGE                   12:12
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC2_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC2_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC2_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC2_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC2_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC2_RST_INIT_ENUM                       ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC2_RST_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC2_RST_ENABLE                  _MK_ENUM_CONST(1)
+
+// Reset SPI 1 Controller
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SPI1_RST_SHIFT                   _MK_SHIFT_CONST(11)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SPI1_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SPI1_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SPI1_RST_RANGE                   11:11
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SPI1_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SPI1_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SPI1_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SPI1_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SPI1_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SPI1_RST_INIT_ENUM                       ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SPI1_RST_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SPI1_RST_ENABLE                  _MK_ENUM_CONST(1)
+
+// Reset NOR Flash Controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_NOR_RST_SHIFT                    _MK_SHIFT_CONST(10)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_NOR_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_NOR_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_NOR_RST_RANGE                    10:10
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_NOR_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_NOR_RST_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_NOR_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_NOR_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_NOR_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_NOR_RST_INIT_ENUM                        DISABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_NOR_RST_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_NOR_RST_ENABLE                   _MK_ENUM_CONST(1)
+
+// Reset NOR Flash Controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SNOR_RST_SHIFT                   _MK_SHIFT_CONST(10)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SNOR_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SNOR_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SNOR_RST_RANGE                   10:10
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SNOR_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SNOR_RST_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SNOR_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SNOR_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SNOR_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SNOR_RST_INIT_ENUM                       DISABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SNOR_RST_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SNOR_RST_ENABLE                  _MK_ENUM_CONST(1)
+
+// Reset SBC 1 Controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC1_RST_SHIFT                   _MK_SHIFT_CONST(9)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC1_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC1_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC1_RST_RANGE                   9:9
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC1_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC1_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC1_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC1_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC1_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC1_RST_INIT_ENUM                       ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC1_RST_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC1_RST_ENABLE                  _MK_ENUM_CONST(1)
+
+// Reset KFuse controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_KFUSE_RST_SHIFT                  _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_KFUSE_RST_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_KFUSE_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_KFUSE_RST_RANGE                  8:8
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_KFUSE_RST_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_KFUSE_RST_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_KFUSE_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_KFUSE_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_KFUSE_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_KFUSE_RST_INIT_ENUM                      ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_KFUSE_RST_DISABLE                        _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_KFUSE_RST_ENABLE                 _MK_ENUM_CONST(1)
+
+// Reset Fuse controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_FUSE_RST_SHIFT                   _MK_SHIFT_CONST(7)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_FUSE_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_FUSE_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_FUSE_RST_RANGE                   7:7
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_FUSE_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_FUSE_RST_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_FUSE_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_FUSE_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_FUSE_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_FUSE_RST_INIT_ENUM                       DISABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_FUSE_RST_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_FUSE_RST_ENABLE                  _MK_ENUM_CONST(1)
+
+// Reset PMC controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_PMC_RST_SHIFT                    _MK_SHIFT_CONST(6)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_PMC_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_PMC_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_PMC_RST_RANGE                    6:6
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_PMC_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_PMC_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_PMC_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_PMC_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_PMC_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_PMC_RST_INIT_ENUM                        ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_PMC_RST_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_PMC_RST_ENABLE                   _MK_ENUM_CONST(1)
+
+// Reset statistic monitor
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_STAT_MON_RST_SHIFT                       _MK_SHIFT_CONST(5)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_STAT_MON_RST_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_STAT_MON_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_STAT_MON_RST_RANGE                       5:5
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_STAT_MON_RST_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_STAT_MON_RST_DEFAULT                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_STAT_MON_RST_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_STAT_MON_RST_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_STAT_MON_RST_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_STAT_MON_RST_INIT_ENUM                   ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_STAT_MON_RST_DISABLE                     _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_STAT_MON_RST_ENABLE                      _MK_ENUM_CONST(1)
+
+// Reset Keyboard controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_KBC_RST_SHIFT                    _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_KBC_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_KBC_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_KBC_RST_RANGE                    4:4
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_KBC_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_KBC_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_KBC_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_KBC_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_KBC_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_KBC_RST_INIT_ENUM                        ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_KBC_RST_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_KBC_RST_ENABLE                   _MK_ENUM_CONST(1)
+
+// Reset APB-DMA.
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_APBDMA_RST_SHIFT                 _MK_SHIFT_CONST(2)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_APBDMA_RST_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_APBDMA_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_APBDMA_RST_RANGE                 2:2
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_APBDMA_RST_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_APBDMA_RST_DEFAULT                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_APBDMA_RST_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_APBDMA_RST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_APBDMA_RST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_APBDMA_RST_INIT_ENUM                     ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_APBDMA_RST_DISABLE                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_APBDMA_RST_ENABLE                        _MK_ENUM_CONST(1)
+
+// Reset AHB-DMA.
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_AHBDMA_RST_SHIFT                 _MK_SHIFT_CONST(1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_AHBDMA_RST_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_AHBDMA_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_AHBDMA_RST_RANGE                 1:1
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_AHBDMA_RST_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_AHBDMA_RST_DEFAULT                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_AHBDMA_RST_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_AHBDMA_RST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_AHBDMA_RST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_AHBDMA_RST_INIT_ENUM                     ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_AHBDMA_RST_DISABLE                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_AHBDMA_RST_ENABLE                        _MK_ENUM_CONST(1)
+
+// Reset MC.
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MEM_RST_SHIFT                    _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MEM_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MEM_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MEM_RST_RANGE                    0:0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MEM_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MEM_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MEM_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MEM_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MEM_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MEM_RST_INIT_ENUM                        ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MEM_RST_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MEM_RST_ENABLE                   _MK_ENUM_CONST(1)
+
+
+// Register CLK_RST_CONTROLLER_RST_DEVICES_U_0  
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0                      _MK_ADDR_CONST(0xc)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SECURE                       0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_WORD_COUNT                   0x1
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_RESET_VAL                    _MK_MASK_CONST(0x15ff)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_RESET_MASK                   _MK_MASK_CONST(0x1fff)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_READ_MASK                    _MK_MASK_CONST(0x1fff)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_WRITE_MASK                   _MK_MASK_CONST(0x1fff)
+// Reset LA logic.
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_LA_RST_SHIFT                     _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_LA_RST_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_LA_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_LA_RST_RANGE                     12:12
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_LA_RST_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_LA_RST_DEFAULT                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_LA_RST_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_LA_RST_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_LA_RST_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_LA_RST_INIT_ENUM                 ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_LA_RST_DISABLE                   _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_LA_RST_ENABLE                    _MK_ENUM_CONST(1)
+
+// Reset AVPUCQ logic.
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_AVPUCQ_RST_SHIFT                 _MK_SHIFT_CONST(11)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_AVPUCQ_RST_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_AVPUCQ_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_AVPUCQ_RST_RANGE                 11:11
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_AVPUCQ_RST_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_AVPUCQ_RST_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_AVPUCQ_RST_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_AVPUCQ_RST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_AVPUCQ_RST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_AVPUCQ_RST_INIT_ENUM                     DISABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_AVPUCQ_RST_DISABLE                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_AVPUCQ_RST_ENABLE                        _MK_ENUM_CONST(1)
+
+// Reset PCIEXCLK logic.
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_PCIEXCLK_RST_SHIFT                       _MK_SHIFT_CONST(10)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_PCIEXCLK_RST_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_PCIEXCLK_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_PCIEXCLK_RST_RANGE                       10:10
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_PCIEXCLK_RST_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_PCIEXCLK_RST_DEFAULT                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_PCIEXCLK_RST_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_PCIEXCLK_RST_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_PCIEXCLK_RST_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_PCIEXCLK_RST_INIT_ENUM                   ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_PCIEXCLK_RST_DISABLE                     _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_PCIEXCLK_RST_ENABLE                      _MK_ENUM_CONST(1)
+
+// Reset Coresight controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_CSITE_RST_SHIFT                  _MK_SHIFT_CONST(9)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_CSITE_RST_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_CSITE_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_CSITE_RST_RANGE                  9:9
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_CSITE_RST_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_CSITE_RST_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_CSITE_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_CSITE_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_CSITE_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_CSITE_RST_INIT_ENUM                      DISABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_CSITE_RST_DISABLE                        _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_CSITE_RST_ENABLE                 _MK_ENUM_CONST(1)
+
+// Reset AFI controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_AFI_RST_SHIFT                    _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_AFI_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_AFI_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_AFI_RST_RANGE                    8:8
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_AFI_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_AFI_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_AFI_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_AFI_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_AFI_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_AFI_RST_INIT_ENUM                        ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_AFI_RST_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_AFI_RST_ENABLE                   _MK_ENUM_CONST(1)
+
+// Reset OWR controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_OWR_RST_SHIFT                    _MK_SHIFT_CONST(7)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_OWR_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_OWR_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_OWR_RST_RANGE                    7:7
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_OWR_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_OWR_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_OWR_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_OWR_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_OWR_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_OWR_RST_INIT_ENUM                        ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_OWR_RST_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_OWR_RST_ENABLE                   _MK_ENUM_CONST(1)
+
+// Reset PCIE controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_PCIE_RST_SHIFT                   _MK_SHIFT_CONST(6)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_PCIE_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_PCIE_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_PCIE_RST_RANGE                   6:6
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_PCIE_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_PCIE_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_PCIE_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_PCIE_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_PCIE_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_PCIE_RST_INIT_ENUM                       ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_PCIE_RST_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_PCIE_RST_ENABLE                  _MK_ENUM_CONST(1)
+
+// Reset SDMMC3 controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_SDMMC3_RST_SHIFT                 _MK_SHIFT_CONST(5)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_SDMMC3_RST_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_SDMMC3_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_SDMMC3_RST_RANGE                 5:5
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_SDMMC3_RST_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_SDMMC3_RST_DEFAULT                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_SDMMC3_RST_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_SDMMC3_RST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_SDMMC3_RST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_SDMMC3_RST_INIT_ENUM                     ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_SDMMC3_RST_DISABLE                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_SDMMC3_RST_ENABLE                        _MK_ENUM_CONST(1)
+
+// Reset SBC4 controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_SBC4_RST_SHIFT                   _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_SBC4_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_SBC4_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_SBC4_RST_RANGE                   4:4
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_SBC4_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_SBC4_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_SBC4_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_SBC4_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_SBC4_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_SBC4_RST_INIT_ENUM                       ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_SBC4_RST_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_SBC4_RST_ENABLE                  _MK_ENUM_CONST(1)
+
+// Reset I2C3 controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_I2C3_RST_SHIFT                   _MK_SHIFT_CONST(3)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_I2C3_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_I2C3_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_I2C3_RST_RANGE                   3:3
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_I2C3_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_I2C3_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_I2C3_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_I2C3_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_I2C3_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_I2C3_RST_INIT_ENUM                       ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_I2C3_RST_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_I2C3_RST_ENABLE                  _MK_ENUM_CONST(1)
+
+// Reset UARTE controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_UARTE_RST_SHIFT                  _MK_SHIFT_CONST(2)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_UARTE_RST_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_UARTE_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_UARTE_RST_RANGE                  2:2
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_UARTE_RST_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_UARTE_RST_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_UARTE_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_UARTE_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_UARTE_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_UARTE_RST_INIT_ENUM                      ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_UARTE_RST_DISABLE                        _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_UARTE_RST_ENABLE                 _MK_ENUM_CONST(1)
+
+// Reset UARTD controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_UARTD_RST_SHIFT                  _MK_SHIFT_CONST(1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_UARTD_RST_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_UARTD_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_UARTD_RST_RANGE                  1:1
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_UARTD_RST_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_UARTD_RST_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_UARTD_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_UARTD_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_UARTD_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_UARTD_RST_INIT_ENUM                      ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_UARTD_RST_DISABLE                        _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_UARTD_RST_ENABLE                 _MK_ENUM_CONST(1)
+
+// Reset SPEEDO controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_SPEEDO_RST_SHIFT                 _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_SPEEDO_RST_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_SPEEDO_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_SPEEDO_RST_RANGE                 0:0
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_SPEEDO_RST_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_SPEEDO_RST_DEFAULT                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_SPEEDO_RST_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_SPEEDO_RST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_SPEEDO_RST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_SPEEDO_RST_INIT_ENUM                     ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_SPEEDO_RST_DISABLE                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_SPEEDO_RST_ENABLE                        _MK_ENUM_CONST(1)
+
+
+// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0  
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0                      _MK_ADDR_CONST(0x10)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_SECURE                       0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_WORD_COUNT                   0x1
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_RESET_VAL                    _MK_MASK_CONST(0x80000130)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_RESET_MASK                   _MK_MASK_CONST(0xbffffff9)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_READ_MASK                    _MK_MASK_CONST(0xbffffff9)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_WRITE_MASK                   _MK_MASK_CONST(0xbffffff9)
+// Enable clock to COP cache controller.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CACHE2_SHIFT                 _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CACHE2_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CACHE2_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CACHE2_RANGE                 31:31
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CACHE2_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CACHE2_DEFAULT                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CACHE2_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CACHE2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CACHE2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CACHE2_INIT_ENUM                     ENABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CACHE2_DISABLE                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CACHE2_ENABLE                        _MK_ENUM_CONST(1)
+
+// Enable clock to vector co-processor.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_VCP_SHIFT                    _MK_SHIFT_CONST(29)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_VCP_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_VCP_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_VCP_RANGE                    29:29
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_VCP_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_VCP_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_VCP_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_VCP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_VCP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_VCP_INIT_ENUM                        DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_VCP_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_VCP_ENABLE                   _MK_ENUM_CONST(1)
+
+// Enable clock to HOST1X.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_HOST1X_SHIFT                 _MK_SHIFT_CONST(28)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_HOST1X_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_HOST1X_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_HOST1X_RANGE                 28:28
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_HOST1X_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_HOST1X_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_HOST1X_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_HOST1X_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_HOST1X_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_HOST1X_INIT_ENUM                     DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_HOST1X_DISABLE                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_HOST1X_ENABLE                        _MK_ENUM_CONST(1)
+
+// Enable clock to DISP1 controller.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_DISP1_SHIFT                  _MK_SHIFT_CONST(27)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_DISP1_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_DISP1_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_DISP1_RANGE                  27:27
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_DISP1_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_DISP1_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_DISP1_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_DISP1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_DISP1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_DISP1_INIT_ENUM                      DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_DISP1_DISABLE                        _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_DISP1_ENABLE                 _MK_ENUM_CONST(1)
+
+// Enable clock to DISP2 controller.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_DISP2_SHIFT                  _MK_SHIFT_CONST(26)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_DISP2_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_DISP2_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_DISP2_RANGE                  26:26
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_DISP2_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_DISP2_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_DISP2_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_DISP2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_DISP2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_DISP2_INIT_ENUM                      DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_DISP2_DISABLE                        _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_DISP2_ENABLE                 _MK_ENUM_CONST(1)
+
+// Enable clock to IDE controller
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_IDE_SHIFT                    _MK_SHIFT_CONST(25)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_IDE_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_IDE_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_IDE_RANGE                    25:25
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_IDE_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_IDE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_IDE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_IDE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_IDE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_IDE_INIT_ENUM                        DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_IDE_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_IDE_ENABLE                   _MK_ENUM_CONST(1)
+
+// Enable clock to 3D controller.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_3D_SHIFT                     _MK_SHIFT_CONST(24)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_3D_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_3D_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_3D_RANGE                     24:24
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_3D_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_3D_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_3D_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_3D_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_3D_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_3D_INIT_ENUM                 DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_3D_DISABLE                   _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_3D_ENABLE                    _MK_ENUM_CONST(1)
+
+// Enable clock to ISP controller.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_ISP_SHIFT                    _MK_SHIFT_CONST(23)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_ISP_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_ISP_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_ISP_RANGE                    23:23
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_ISP_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_ISP_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_ISP_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_ISP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_ISP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_ISP_INIT_ENUM                        DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_ISP_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_ISP_ENABLE                   _MK_ENUM_CONST(1)
+
+// Enable clock to USB controller
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_USBD_SHIFT                   _MK_SHIFT_CONST(22)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_USBD_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_USBD_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_USBD_RANGE                   22:22
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_USBD_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_USBD_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_USBD_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_USBD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_USBD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_USBD_INIT_ENUM                       DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_USBD_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_USBD_ENABLE                  _MK_ENUM_CONST(1)
+
+// Enable clock to 2D graphics engine.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_2D_SHIFT                     _MK_SHIFT_CONST(21)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_2D_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_2D_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_2D_RANGE                     21:21
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_2D_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_2D_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_2D_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_2D_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_2D_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_2D_INIT_ENUM                 DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_2D_DISABLE                   _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_2D_ENABLE                    _MK_ENUM_CONST(1)
+
+// Enable clock to VI controller.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_VI_SHIFT                     _MK_SHIFT_CONST(20)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_VI_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_VI_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_VI_RANGE                     20:20
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_VI_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_VI_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_VI_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_VI_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_VI_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_VI_INIT_ENUM                 DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_VI_DISABLE                   _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_VI_ENABLE                    _MK_ENUM_CONST(1)
+
+// Enable clock to EPP controller.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_EPP_SHIFT                    _MK_SHIFT_CONST(19)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_EPP_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_EPP_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_EPP_RANGE                    19:19
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_EPP_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_EPP_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_EPP_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_EPP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_EPP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_EPP_INIT_ENUM                        DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_EPP_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_EPP_ENABLE                   _MK_ENUM_CONST(1)
+
+// Enable clock to I2S 2 controller
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2S2_SHIFT                   _MK_SHIFT_CONST(18)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2S2_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2S2_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2S2_RANGE                   18:18
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2S2_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2S2_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2S2_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2S2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2S2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2S2_INIT_ENUM                       DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2S2_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2S2_ENABLE                  _MK_ENUM_CONST(1)
+
+// Enable clock to PWM (Pulse Width Modulator)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_PWM_SHIFT                    _MK_SHIFT_CONST(17)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_PWM_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_PWM_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_PWM_RANGE                    17:17
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_PWM_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_PWM_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_PWM_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_PWM_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_PWM_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_PWM_INIT_ENUM                        DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_PWM_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_PWM_ENABLE                   _MK_ENUM_CONST(1)
+
+// Enable clock to 3-Wire Interface Controller
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_TWC_SHIFT                    _MK_SHIFT_CONST(16)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_TWC_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_TWC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_TWC_RANGE                    16:16
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_TWC_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_TWC_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_TWC_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_TWC_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_TWC_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_TWC_INIT_ENUM                        DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_TWC_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_TWC_ENABLE                   _MK_ENUM_CONST(1)
+
+// Enable clock to SDMMC4 controller.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDMMC4_SHIFT                 _MK_SHIFT_CONST(15)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDMMC4_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDMMC4_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDMMC4_RANGE                 15:15
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDMMC4_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDMMC4_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDMMC4_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDMMC4_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDMMC4_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDMMC4_INIT_ENUM                     DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDMMC4_DISABLE                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDMMC4_ENABLE                        _MK_ENUM_CONST(1)
+
+// Enable clock to SDMMC1 controller.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDMMC1_SHIFT                 _MK_SHIFT_CONST(14)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDMMC1_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDMMC1_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDMMC1_RANGE                 14:14
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDMMC1_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDMMC1_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDMMC1_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDMMC1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDMMC1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDMMC1_INIT_ENUM                     DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDMMC1_DISABLE                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDMMC1_ENABLE                        _MK_ENUM_CONST(1)
+
+// Enable clock to NAND flash controller.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_NDFLASH_SHIFT                        _MK_SHIFT_CONST(13)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_NDFLASH_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_NDFLASH_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_NDFLASH_RANGE                        13:13
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_NDFLASH_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_NDFLASH_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_NDFLASH_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_NDFLASH_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_NDFLASH_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_NDFLASH_INIT_ENUM                    DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_NDFLASH_DISABLE                      _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_NDFLASH_ENABLE                       _MK_ENUM_CONST(1)
+
+// Enable clock to I2C1 Controller
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2C1_SHIFT                   _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2C1_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2C1_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2C1_RANGE                   12:12
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2C1_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2C1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2C1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2C1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2C1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2C1_INIT_ENUM                       DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2C1_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2C1_ENABLE                  _MK_ENUM_CONST(1)
+
+// Enable clock to I2S1 Controller
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2S1_SHIFT                   _MK_SHIFT_CONST(11)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2S1_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2S1_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2S1_RANGE                   11:11
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2S1_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2S1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2S1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2S1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2S1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2S1_INIT_ENUM                       DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2S1_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2S1_ENABLE                  _MK_ENUM_CONST(1)
+
+// Enable clock to SPDIF Controller
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SPDIF_SHIFT                  _MK_SHIFT_CONST(10)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SPDIF_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SPDIF_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SPDIF_RANGE                  10:10
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SPDIF_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SPDIF_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SPDIF_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SPDIF_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SPDIF_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SPDIF_INIT_ENUM                      DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SPDIF_DISABLE                        _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SPDIF_ENABLE                 _MK_ENUM_CONST(1)
+
+// Enable clock to SDMMC2 controller.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDMMC2_SHIFT                 _MK_SHIFT_CONST(9)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDMMC2_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDMMC2_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDMMC2_RANGE                 9:9
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDMMC2_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDMMC2_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDMMC2_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDMMC2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDMMC2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDMMC2_INIT_ENUM                     DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDMMC2_DISABLE                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDMMC2_ENABLE                        _MK_ENUM_CONST(1)
+
+// Enable clock to GPIO Controller
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_GPIO_SHIFT                   _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_GPIO_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_GPIO_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_GPIO_RANGE                   8:8
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_GPIO_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_GPIO_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_GPIO_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_GPIO_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_GPIO_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_GPIO_INIT_ENUM                       ENABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_GPIO_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_GPIO_ENABLE                  _MK_ENUM_CONST(1)
+
+// Enable clock to UARTB/VFIR Controller
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_UARTB_SHIFT                  _MK_SHIFT_CONST(7)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_UARTB_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_UARTB_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_UARTB_RANGE                  7:7
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_UARTB_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_UARTB_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_UARTB_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_UARTB_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_UARTB_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_UARTB_INIT_ENUM                      DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_UARTB_DISABLE                        _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_UARTB_ENABLE                 _MK_ENUM_CONST(1)
+
+// Enable clock to UARTA Controller
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_UARTA_SHIFT                  _MK_SHIFT_CONST(6)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_UARTA_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_UARTA_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_UARTA_RANGE                  6:6
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_UARTA_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_UARTA_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_UARTA_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_UARTA_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_UARTA_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_UARTA_INIT_ENUM                      DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_UARTA_DISABLE                        _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_UARTA_ENABLE                 _MK_ENUM_CONST(1)
+
+// Enable clock to Timer Controller
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_TMR_SHIFT                    _MK_SHIFT_CONST(5)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_TMR_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_TMR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_TMR_RANGE                    5:5
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_TMR_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_TMR_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_TMR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_TMR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_TMR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_TMR_INIT_ENUM                        ENABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_TMR_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_TMR_ENABLE                   _MK_ENUM_CONST(1)
+
+// Enable clock to RTC Controller
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_RTC_SHIFT                    _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_RTC_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_RTC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_RTC_RANGE                    4:4
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_RTC_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_RTC_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_RTC_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_RTC_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_RTC_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_RTC_INIT_ENUM                        ENABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_RTC_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_RTC_ENABLE                   _MK_ENUM_CONST(1)
+
+// Enable clock to AC97 Controller
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_AC97_SHIFT                   _MK_SHIFT_CONST(3)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_AC97_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_AC97_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_AC97_RANGE                   3:3
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_AC97_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_AC97_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_AC97_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_AC97_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_AC97_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_AC97_INIT_ENUM                       DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_AC97_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_AC97_ENABLE                  _MK_ENUM_CONST(1)
+
+// Enable clock to CPU.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CPU_SHIFT                    _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CPU_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CPU_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CPU_RANGE                    0:0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CPU_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CPU_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CPU_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CPU_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CPU_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CPU_INIT_ENUM                        DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CPU_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CPU_ENABLE                   _MK_ENUM_CONST(1)
+
+
+// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0  
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0                      _MK_ADDR_CONST(0x14)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_SECURE                       0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_WORD_COUNT                   0x1
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_RESET_VAL                    _MK_MASK_CONST(0x480)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_RESET_MASK                   _MK_MASK_CONST(0xfefffff7)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_READ_MASK                    _MK_MASK_CONST(0xfefffff7)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_WRITE_MASK                   _MK_MASK_CONST(0xfefffff7)
+// Enable clock to BSEV Controller.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_BSEV_SHIFT                   _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_BSEV_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_BSEV_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_BSEV_RANGE                   31:31
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_BSEV_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_BSEV_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_BSEV_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_BSEV_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_BSEV_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_BSEV_INIT_ENUM                       DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_BSEV_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_BSEV_ENABLE                  _MK_ENUM_CONST(1)
+
+// Enable clock to BSEA Controller
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_BSEA_SHIFT                   _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_BSEA_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_BSEA_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_BSEA_RANGE                   30:30
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_BSEA_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_BSEA_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_BSEA_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_BSEA_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_BSEA_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_BSEA_INIT_ENUM                       DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_BSEA_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_BSEA_ENABLE                  _MK_ENUM_CONST(1)
+
+// Enable clock to VDE Controller
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_VDE_SHIFT                    _MK_SHIFT_CONST(29)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_VDE_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_VDE_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_VDE_RANGE                    29:29
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_VDE_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_VDE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_VDE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_VDE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_VDE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_VDE_INIT_ENUM                        DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_VDE_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_VDE_ENABLE                   _MK_ENUM_CONST(1)
+
+// Enable clock to MPE controller.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MPE_SHIFT                    _MK_SHIFT_CONST(28)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MPE_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MPE_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MPE_RANGE                    28:28
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MPE_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MPE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MPE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MPE_INIT_ENUM                        DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MPE_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MPE_ENABLE                   _MK_ENUM_CONST(1)
+
+// Enable clock to USB3 controller.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_USB3_SHIFT                   _MK_SHIFT_CONST(27)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_USB3_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_USB3_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_USB3_RANGE                   27:27
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_USB3_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_USB3_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_USB3_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_USB3_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_USB3_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_USB3_INIT_ENUM                       DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_USB3_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_USB3_ENABLE                  _MK_ENUM_CONST(1)
+
+// Enable clock to USB2 controller.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_USB2_SHIFT                   _MK_SHIFT_CONST(26)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_USB2_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_USB2_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_USB2_RANGE                   26:26
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_USB2_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_USB2_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_USB2_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_USB2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_USB2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_USB2_INIT_ENUM                       DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_USB2_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_USB2_ENABLE                  _MK_ENUM_CONST(1)
+
+// Enable clock to EMC controller.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_EMC_SHIFT                    _MK_SHIFT_CONST(25)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_EMC_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_EMC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_EMC_RANGE                    25:25
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_EMC_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_EMC_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_EMC_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_EMC_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_EMC_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_EMC_INIT_ENUM                        DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_EMC_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_EMC_ENABLE                   _MK_ENUM_CONST(1)
+
+// Enable clock to UART-C Controller
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_UARTC_SHIFT                  _MK_SHIFT_CONST(23)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_UARTC_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_UARTC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_UARTC_RANGE                  23:23
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_UARTC_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_UARTC_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_UARTC_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_UARTC_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_UARTC_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_UARTC_INIT_ENUM                      DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_UARTC_DISABLE                        _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_UARTC_ENABLE                 _MK_ENUM_CONST(1)
+
+// Enable clock to I2C2 controller.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_I2C2_SHIFT                   _MK_SHIFT_CONST(22)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_I2C2_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_I2C2_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_I2C2_RANGE                   22:22
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_I2C2_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_I2C2_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_I2C2_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_I2C2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_I2C2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_I2C2_INIT_ENUM                       DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_I2C2_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_I2C2_ENABLE                  _MK_ENUM_CONST(1)
+
+// Enable clock to TVDAC controller.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_TVDAC_SHIFT                  _MK_SHIFT_CONST(21)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_TVDAC_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_TVDAC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_TVDAC_RANGE                  21:21
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_TVDAC_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_TVDAC_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_TVDAC_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_TVDAC_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_TVDAC_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_TVDAC_INIT_ENUM                      DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_TVDAC_DISABLE                        _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_TVDAC_ENABLE                 _MK_ENUM_CONST(1)
+
+// Enable clock to CSI controller
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_CSI_SHIFT                    _MK_SHIFT_CONST(20)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_CSI_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_CSI_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_CSI_RANGE                    20:20
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_CSI_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_CSI_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_CSI_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_CSI_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_CSI_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_CSI_INIT_ENUM                        DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_CSI_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_CSI_ENABLE                   _MK_ENUM_CONST(1)
+
+// Enable clock to HDMI
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_HDMI_SHIFT                   _MK_SHIFT_CONST(19)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_HDMI_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_HDMI_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_HDMI_RANGE                   19:19
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_HDMI_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_HDMI_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_HDMI_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_HDMI_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_HDMI_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_HDMI_INIT_ENUM                       DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_HDMI_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_HDMI_ENABLE                  _MK_ENUM_CONST(1)
+
+// Enable clock to MIPI base-band controller
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MIPI_SHIFT                   _MK_SHIFT_CONST(18)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MIPI_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MIPI_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MIPI_RANGE                   18:18
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MIPI_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MIPI_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MIPI_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MIPI_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MIPI_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MIPI_INIT_ENUM                       DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MIPI_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MIPI_ENABLE                  _MK_ENUM_CONST(1)
+
+// Enable clock to TVO/CVE controller
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_TVO_SHIFT                    _MK_SHIFT_CONST(17)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_TVO_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_TVO_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_TVO_RANGE                    17:17
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_TVO_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_TVO_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_TVO_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_TVO_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_TVO_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_TVO_INIT_ENUM                        DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_TVO_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_TVO_ENABLE                   _MK_ENUM_CONST(1)
+
+// Enable clock to DSI controller
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_DSI_SHIFT                    _MK_SHIFT_CONST(16)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_DSI_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_DSI_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_DSI_RANGE                    16:16
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_DSI_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_DSI_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_DSI_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_DSI_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_DSI_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_DSI_INIT_ENUM                        DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_DSI_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_DSI_ENABLE                   _MK_ENUM_CONST(1)
+
+// Enable clock to DVC-I2C Controller
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_DVC_I2C_SHIFT                        _MK_SHIFT_CONST(15)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_DVC_I2C_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_DVC_I2C_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_DVC_I2C_RANGE                        15:15
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_DVC_I2C_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_DVC_I2C_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_DVC_I2C_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_DVC_I2C_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_DVC_I2C_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_DVC_I2C_INIT_ENUM                    DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_DVC_I2C_DISABLE                      _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_DVC_I2C_ENABLE                       _MK_ENUM_CONST(1)
+
+// Enable clock to SBC 3 Controller.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC3_SHIFT                   _MK_SHIFT_CONST(14)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC3_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC3_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC3_RANGE                   14:14
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC3_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC3_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC3_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC3_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC3_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC3_INIT_ENUM                       DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC3_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC3_ENABLE                  _MK_ENUM_CONST(1)
+
+// Enable clock to XIO Controller.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_XIO_SHIFT                    _MK_SHIFT_CONST(13)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_XIO_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_XIO_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_XIO_RANGE                    13:13
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_XIO_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_XIO_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_XIO_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_XIO_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_XIO_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_XIO_INIT_ENUM                        DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_XIO_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_XIO_ENABLE                   _MK_ENUM_CONST(1)
+
+// Enable clock to SBC 2 Controller.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC2_SHIFT                   _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC2_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC2_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC2_RANGE                   12:12
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC2_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC2_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC2_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC2_INIT_ENUM                       DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC2_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC2_ENABLE                  _MK_ENUM_CONST(1)
+
+// Enable clock to SPI 1 Controller
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SPI1_SHIFT                   _MK_SHIFT_CONST(11)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SPI1_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SPI1_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SPI1_RANGE                   11:11
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SPI1_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SPI1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SPI1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SPI1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SPI1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SPI1_INIT_ENUM                       DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SPI1_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SPI1_ENABLE                  _MK_ENUM_CONST(1)
+
+// Enable clock to NOR Flash Controller.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_NOR_SHIFT                    _MK_SHIFT_CONST(10)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_NOR_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_NOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_NOR_RANGE                    10:10
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_NOR_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_NOR_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_NOR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_NOR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_NOR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_NOR_INIT_ENUM                        ENABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_NOR_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_NOR_ENABLE                   _MK_ENUM_CONST(1)
+
+// Enable clock to NOR Flash Controller.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SNOR_SHIFT                   _MK_SHIFT_CONST(10)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SNOR_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SNOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SNOR_RANGE                   10:10
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SNOR_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SNOR_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SNOR_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SNOR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SNOR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SNOR_INIT_ENUM                       ENABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SNOR_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SNOR_ENABLE                  _MK_ENUM_CONST(1)
+
+// Enable clock to SBC 1 Controller.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC1_SHIFT                   _MK_SHIFT_CONST(9)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC1_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC1_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC1_RANGE                   9:9
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC1_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC1_INIT_ENUM                       DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC1_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC1_ENABLE                  _MK_ENUM_CONST(1)
+
+// Enable clock to KFUSE controller.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_KFUSE_SHIFT                  _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_KFUSE_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_KFUSE_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_KFUSE_RANGE                  8:8
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_KFUSE_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_KFUSE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_KFUSE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_KFUSE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_KFUSE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_KFUSE_INIT_ENUM                      DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_KFUSE_DISABLE                        _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_KFUSE_ENABLE                 _MK_ENUM_CONST(1)
+
+// Enable clock to FUSE controller.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_FUSE_SHIFT                   _MK_SHIFT_CONST(7)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_FUSE_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_FUSE_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_FUSE_RANGE                   7:7
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_FUSE_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_FUSE_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_FUSE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_FUSE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_FUSE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_FUSE_INIT_ENUM                       ENABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_FUSE_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_FUSE_ENABLE                  _MK_ENUM_CONST(1)
+
+// Enable clock to PMC controller.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_PMC_SHIFT                    _MK_SHIFT_CONST(6)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_PMC_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_PMC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_PMC_RANGE                    6:6
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_PMC_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_PMC_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_PMC_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_PMC_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_PMC_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_PMC_INIT_ENUM                        DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_PMC_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_PMC_ENABLE                   _MK_ENUM_CONST(1)
+
+// Enable clock to statistic monitor.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_STAT_MON_SHIFT                       _MK_SHIFT_CONST(5)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_STAT_MON_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_STAT_MON_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_STAT_MON_RANGE                       5:5
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_STAT_MON_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_STAT_MON_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_STAT_MON_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_STAT_MON_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_STAT_MON_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_STAT_MON_INIT_ENUM                   DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_STAT_MON_DISABLE                     _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_STAT_MON_ENABLE                      _MK_ENUM_CONST(1)
+
+// Enable clock to keyboard controller.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_KBC_SHIFT                    _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_KBC_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_KBC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_KBC_RANGE                    4:4
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_KBC_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_KBC_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_KBC_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_KBC_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_KBC_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_KBC_INIT_ENUM                        DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_KBC_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_KBC_ENABLE                   _MK_ENUM_CONST(1)
+
+// Enable clock to APB-DMA.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_APBDMA_SHIFT                 _MK_SHIFT_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_APBDMA_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_APBDMA_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_APBDMA_RANGE                 2:2
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_APBDMA_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_APBDMA_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_APBDMA_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_APBDMA_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_APBDMA_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_APBDMA_INIT_ENUM                     DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_APBDMA_DISABLE                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_APBDMA_ENABLE                        _MK_ENUM_CONST(1)
+
+// Enable clock to AHB-DMA.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_AHBDMA_SHIFT                 _MK_SHIFT_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_AHBDMA_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_AHBDMA_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_AHBDMA_RANGE                 1:1
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_AHBDMA_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_AHBDMA_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_AHBDMA_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_AHBDMA_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_AHBDMA_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_AHBDMA_INIT_ENUM                     DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_AHBDMA_DISABLE                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_AHBDMA_ENABLE                        _MK_ENUM_CONST(1)
+
+// Enable clock to MC/EMC.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MEM_SHIFT                    _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MEM_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MEM_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MEM_RANGE                    0:0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MEM_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MEM_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MEM_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MEM_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MEM_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MEM_INIT_ENUM                        DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MEM_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MEM_ENABLE                   _MK_ENUM_CONST(1)
+
+
+// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0  
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0                      _MK_ADDR_CONST(0x18)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_SECURE                       0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_WORD_COUNT                   0x1
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_RESET_VAL                    _MK_MASK_CONST(0x7f00a00)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_RESET_MASK                   _MK_MASK_CONST(0x77f01bff)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_READ_MASK                    _MK_MASK_CONST(0x77f01bff)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_WRITE_MASK                   _MK_MASK_CONST(0x77f01bff)
+// Enable clock to DEV1 pad.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_DEV1_OUT_SHIFT                       _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_DEV1_OUT_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_DEV1_OUT_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_DEV1_OUT_RANGE                       30:30
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_DEV1_OUT_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_DEV1_OUT_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_DEV1_OUT_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_DEV1_OUT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_DEV1_OUT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_DEV1_OUT_INIT_ENUM                   DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_DEV1_OUT_DISABLE                     _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_DEV1_OUT_ENABLE                      _MK_ENUM_CONST(1)
+
+// Enable clock to DEV2 pad.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_DEV2_OUT_SHIFT                       _MK_SHIFT_CONST(29)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_DEV2_OUT_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_DEV2_OUT_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_DEV2_OUT_RANGE                       29:29
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_DEV2_OUT_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_DEV2_OUT_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_DEV2_OUT_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_DEV2_OUT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_DEV2_OUT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_DEV2_OUT_INIT_ENUM                   DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_DEV2_OUT_DISABLE                     _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_DEV2_OUT_ENABLE                      _MK_ENUM_CONST(1)
+
+// Enable clock to SUS pad.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_SUS_OUT_SHIFT                        _MK_SHIFT_CONST(28)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_SUS_OUT_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_SUS_OUT_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_SUS_OUT_RANGE                        28:28
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_SUS_OUT_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_SUS_OUT_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_SUS_OUT_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_SUS_OUT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_SUS_OUT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_SUS_OUT_INIT_ENUM                    DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_SUS_OUT_DISABLE                      _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_SUS_OUT_ENABLE                       _MK_ENUM_CONST(1)
+
+// Enable CLK_M clk doubler.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_M_DOUBLER_ENB_SHIFT                      _MK_SHIFT_CONST(26)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_M_DOUBLER_ENB_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_M_DOUBLER_ENB_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_M_DOUBLER_ENB_RANGE                      26:26
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_M_DOUBLER_ENB_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_M_DOUBLER_ENB_DEFAULT                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_M_DOUBLER_ENB_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_M_DOUBLER_ENB_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_M_DOUBLER_ENB_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_M_DOUBLER_ENB_INIT_ENUM                  ENABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_M_DOUBLER_ENB_DISABLE                    _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_M_DOUBLER_ENB_ENABLE                     _MK_ENUM_CONST(1)
+
+// Enable audio sync clk doubler.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_SYNC_CLK_DOUBLER_ENB_SHIFT                   _MK_SHIFT_CONST(25)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_SYNC_CLK_DOUBLER_ENB_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_SYNC_CLK_DOUBLER_ENB_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_SYNC_CLK_DOUBLER_ENB_RANGE                   25:25
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_SYNC_CLK_DOUBLER_ENB_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_SYNC_CLK_DOUBLER_ENB_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_SYNC_CLK_DOUBLER_ENB_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_SYNC_CLK_DOUBLER_ENB_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_SYNC_CLK_DOUBLER_ENB_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_SYNC_CLK_DOUBLER_ENB_INIT_ENUM                       ENABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_SYNC_CLK_DOUBLER_ENB_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_SYNC_CLK_DOUBLER_ENB_ENABLE                  _MK_ENUM_CONST(1)
+
+// Enable COP cache ram clk.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_CRAM2_SHIFT                  _MK_SHIFT_CONST(24)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_CRAM2_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_CRAM2_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_CRAM2_RANGE                  24:24
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_CRAM2_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_CRAM2_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_CRAM2_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_CRAM2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_CRAM2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_CRAM2_INIT_ENUM                      ENABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_CRAM2_DISABLE                        _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_CRAM2_ENABLE                 _MK_ENUM_CONST(1)
+
+// Enable IRAMD clk.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_IRAMD_SHIFT                  _MK_SHIFT_CONST(23)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_IRAMD_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_IRAMD_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_IRAMD_RANGE                  23:23
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_IRAMD_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_IRAMD_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_IRAMD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_IRAMD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_IRAMD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_IRAMD_INIT_ENUM                      ENABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_IRAMD_DISABLE                        _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_IRAMD_ENABLE                 _MK_ENUM_CONST(1)
+
+// Enable IRAMC clk.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_IRAMC_SHIFT                  _MK_SHIFT_CONST(22)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_IRAMC_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_IRAMC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_IRAMC_RANGE                  22:22
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_IRAMC_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_IRAMC_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_IRAMC_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_IRAMC_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_IRAMC_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_IRAMC_INIT_ENUM                      ENABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_IRAMC_DISABLE                        _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_IRAMC_ENABLE                 _MK_ENUM_CONST(1)
+
+// Enable IRAMB clk.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_IRAMB_SHIFT                  _MK_SHIFT_CONST(21)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_IRAMB_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_IRAMB_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_IRAMB_RANGE                  21:21
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_IRAMB_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_IRAMB_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_IRAMB_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_IRAMB_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_IRAMB_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_IRAMB_INIT_ENUM                      ENABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_IRAMB_DISABLE                        _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_IRAMB_ENABLE                 _MK_ENUM_CONST(1)
+
+// Enable IRAMB clk.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_IRAMA_SHIFT                  _MK_SHIFT_CONST(20)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_IRAMA_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_IRAMA_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_IRAMA_RANGE                  20:20
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_IRAMA_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_IRAMA_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_IRAMA_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_IRAMA_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_IRAMA_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_IRAMA_INIT_ENUM                      ENABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_IRAMA_DISABLE                        _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_IRAMA_ENABLE                 _MK_ENUM_CONST(1)
+
+// Enable clock to LA.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_LA_SHIFT                     _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_LA_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_LA_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_LA_RANGE                     12:12
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_LA_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_LA_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_LA_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_LA_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_LA_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_LA_INIT_ENUM                 DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_LA_DISABLE                   _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_LA_ENABLE                    _MK_ENUM_CONST(1)
+
+// Enable clock to AVPUCQ.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_AVPUCQ_SHIFT                 _MK_SHIFT_CONST(11)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_AVPUCQ_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_AVPUCQ_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_AVPUCQ_RANGE                 11:11
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_AVPUCQ_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_AVPUCQ_DEFAULT                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_AVPUCQ_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_AVPUCQ_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_AVPUCQ_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_AVPUCQ_INIT_ENUM                     ENABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_AVPUCQ_DISABLE                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_AVPUCQ_ENABLE                        _MK_ENUM_CONST(1)
+
+// Enable clock to Coresight.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_CSITE_SHIFT                  _MK_SHIFT_CONST(9)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_CSITE_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_CSITE_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_CSITE_RANGE                  9:9
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_CSITE_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_CSITE_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_CSITE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_CSITE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_CSITE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_CSITE_INIT_ENUM                      ENABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_CSITE_DISABLE                        _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_CSITE_ENABLE                 _MK_ENUM_CONST(1)
+
+// Enable clock to AFI.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_AFI_SHIFT                    _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_AFI_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_AFI_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_AFI_RANGE                    8:8
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_AFI_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_AFI_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_AFI_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_AFI_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_AFI_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_AFI_INIT_ENUM                        DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_AFI_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_AFI_ENABLE                   _MK_ENUM_CONST(1)
+
+// Enable clock to OWR.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_OWR_SHIFT                    _MK_SHIFT_CONST(7)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_OWR_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_OWR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_OWR_RANGE                    7:7
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_OWR_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_OWR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_OWR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_OWR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_OWR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_OWR_INIT_ENUM                        DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_OWR_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_OWR_ENABLE                   _MK_ENUM_CONST(1)
+
+// Enable clock to PCIE.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_PCIE_SHIFT                   _MK_SHIFT_CONST(6)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_PCIE_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_PCIE_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_PCIE_RANGE                   6:6
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_PCIE_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_PCIE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_PCIE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_PCIE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_PCIE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_PCIE_INIT_ENUM                       DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_PCIE_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_PCIE_ENABLE                  _MK_ENUM_CONST(1)
+
+// Enable clock to SDMMC3.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_SDMMC3_SHIFT                 _MK_SHIFT_CONST(5)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_SDMMC3_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_SDMMC3_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_SDMMC3_RANGE                 5:5
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_SDMMC3_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_SDMMC3_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_SDMMC3_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_SDMMC3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_SDMMC3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_SDMMC3_INIT_ENUM                     DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_SDMMC3_DISABLE                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_SDMMC3_ENABLE                        _MK_ENUM_CONST(1)
+
+// Enable clock to SBC4.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_SBC4_SHIFT                   _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_SBC4_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_SBC4_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_SBC4_RANGE                   4:4
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_SBC4_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_SBC4_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_SBC4_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_SBC4_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_SBC4_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_SBC4_INIT_ENUM                       DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_SBC4_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_SBC4_ENABLE                  _MK_ENUM_CONST(1)
+
+// Enable clock to I2C3.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_I2C3_SHIFT                   _MK_SHIFT_CONST(3)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_I2C3_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_I2C3_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_I2C3_RANGE                   3:3
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_I2C3_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_I2C3_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_I2C3_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_I2C3_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_I2C3_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_I2C3_INIT_ENUM                       DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_I2C3_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_I2C3_ENABLE                  _MK_ENUM_CONST(1)
+
+// Enable clock to UARTE.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_UARTE_SHIFT                  _MK_SHIFT_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_UARTE_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_UARTE_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_UARTE_RANGE                  2:2
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_UARTE_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_UARTE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_UARTE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_UARTE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_UARTE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_UARTE_INIT_ENUM                      DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_UARTE_DISABLE                        _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_UARTE_ENABLE                 _MK_ENUM_CONST(1)
+
+// Enable clock to UARTD.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_UARTD_SHIFT                  _MK_SHIFT_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_UARTD_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_UARTD_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_UARTD_RANGE                  1:1
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_UARTD_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_UARTD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_UARTD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_UARTD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_UARTD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_UARTD_INIT_ENUM                      DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_UARTD_DISABLE                        _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_UARTD_ENABLE                 _MK_ENUM_CONST(1)
+
+// Enable clock to SPEEDO.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_SPEEDO_SHIFT                 _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_SPEEDO_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_SPEEDO_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_SPEEDO_RANGE                 0:0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_SPEEDO_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_SPEEDO_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_SPEEDO_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_SPEEDO_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_SPEEDO_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_SPEEDO_INIT_ENUM                     DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_SPEEDO_DISABLE                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_SPEEDO_ENABLE                        _MK_ENUM_CONST(1)
+
+
+// Reserved address 28 [0x1c] 
+
+// Register CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0  
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0                  _MK_ADDR_CONST(0x20)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_SECURE                   0x0
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_WORD_COUNT                       0x1
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_RESET_VAL                        _MK_MASK_CONST(0x10000000)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_RESET_MASK                       _MK_MASK_CONST(0xff00ffff)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_READ_MASK                        _MK_MASK_CONST(0xff00ffff)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_WRITE_MASK                       _MK_MASK_CONST(0xff00ffff)
+// 0000=32KHz Clock source; 
+// 0001=IDLE Clock Source;
+// 001X=Run clock source; 
+// 01XX=IRQ Clock Source;
+// 1XXX=FIQ Clock Source
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_STATE_SHIFT                  _MK_SHIFT_CONST(28)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_STATE_FIELD                  (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_STATE_SHIFT)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_STATE_RANGE                  31:28
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_STATE_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_STATE_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_STATE_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_STATE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_STATE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_STATE_STDBY                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_STATE_IDLE                   _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_STATE_RUN                    _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_STATE_IRQ                    _MK_ENUM_CONST(4)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_STATE_FIQ                    _MK_ENUM_CONST(8)
+
+//  0 = NOP ; 1=Burst on COP FIQ
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_COP_AUTO_CWAKEUP_FROM_FIQ_SHIFT                  _MK_SHIFT_CONST(27)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_COP_AUTO_CWAKEUP_FROM_FIQ_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_COP_AUTO_CWAKEUP_FROM_FIQ_SHIFT)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_COP_AUTO_CWAKEUP_FROM_FIQ_RANGE                  27:27
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_COP_AUTO_CWAKEUP_FROM_FIQ_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_COP_AUTO_CWAKEUP_FROM_FIQ_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_COP_AUTO_CWAKEUP_FROM_FIQ_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_COP_AUTO_CWAKEUP_FROM_FIQ_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_COP_AUTO_CWAKEUP_FROM_FIQ_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  0 = NOP ; 1=Burst on CPU FIQ
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_AUTO_CWAKEUP_FROM_FIQ_SHIFT                  _MK_SHIFT_CONST(26)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_AUTO_CWAKEUP_FROM_FIQ_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_AUTO_CWAKEUP_FROM_FIQ_SHIFT)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_AUTO_CWAKEUP_FROM_FIQ_RANGE                  26:26
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_AUTO_CWAKEUP_FROM_FIQ_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_AUTO_CWAKEUP_FROM_FIQ_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_AUTO_CWAKEUP_FROM_FIQ_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_AUTO_CWAKEUP_FROM_FIQ_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_AUTO_CWAKEUP_FROM_FIQ_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  0 = NOP ; 1=Burst on COP IRQ
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_COP_AUTO_CWAKEUP_FROM_IRQ_SHIFT                  _MK_SHIFT_CONST(25)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_COP_AUTO_CWAKEUP_FROM_IRQ_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_COP_AUTO_CWAKEUP_FROM_IRQ_SHIFT)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_COP_AUTO_CWAKEUP_FROM_IRQ_RANGE                  25:25
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_COP_AUTO_CWAKEUP_FROM_IRQ_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_COP_AUTO_CWAKEUP_FROM_IRQ_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_COP_AUTO_CWAKEUP_FROM_IRQ_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_COP_AUTO_CWAKEUP_FROM_IRQ_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_COP_AUTO_CWAKEUP_FROM_IRQ_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  0 = NOP ; 1=Burst on CPU IRQ
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_AUTO_CWAKEUP_FROM_IRQ_SHIFT                  _MK_SHIFT_CONST(24)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_AUTO_CWAKEUP_FROM_IRQ_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_AUTO_CWAKEUP_FROM_IRQ_SHIFT)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_AUTO_CWAKEUP_FROM_IRQ_RANGE                  24:24
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_AUTO_CWAKEUP_FROM_IRQ_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_AUTO_CWAKEUP_FROM_IRQ_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_AUTO_CWAKEUP_FROM_IRQ_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_AUTO_CWAKEUP_FROM_IRQ_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_AUTO_CWAKEUP_FROM_IRQ_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  0000 = clk_m,
+//  0001 = pllC_out0,
+//  0010 = clk_s,
+//  0011 = pllM_out0,
+//  0100 = pllP_out0,
+//  0101 = pllP_out4,
+//  0110 = pllP_out3,
+//  0111 = clk_d,
+//  1xxx = PLLX_out0,
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_FIQ_SOURCE_SHIFT                 _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_FIQ_SOURCE_FIELD                 (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_FIQ_SOURCE_SHIFT)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_FIQ_SOURCE_RANGE                 15:12
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_FIQ_SOURCE_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_FIQ_SOURCE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_FIQ_SOURCE_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_FIQ_SOURCE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_FIQ_SOURCE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_FIQ_SOURCE_CLKM                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_FIQ_SOURCE_PLLC_OUT0                     _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_FIQ_SOURCE_CLKS                  _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_FIQ_SOURCE_PLLM_OUT0                     _MK_ENUM_CONST(3)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_FIQ_SOURCE_PLLP_OUT0                     _MK_ENUM_CONST(4)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_FIQ_SOURCE_PLLP_OUT4                     _MK_ENUM_CONST(5)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_FIQ_SOURCE_PLLP_OUT3                     _MK_ENUM_CONST(6)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_FIQ_SOURCE_CLKD                  _MK_ENUM_CONST(7)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_FIQ_SOURCE_PLLX_OUT0                     _MK_ENUM_CONST(8)
+
+//  Same definitions as CWAKEUP_FIQ_SOURCE
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IRQ_SOURCE_SHIFT                 _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IRQ_SOURCE_FIELD                 (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IRQ_SOURCE_SHIFT)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IRQ_SOURCE_RANGE                 11:8
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IRQ_SOURCE_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IRQ_SOURCE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IRQ_SOURCE_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IRQ_SOURCE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IRQ_SOURCE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IRQ_SOURCE_CLKM                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IRQ_SOURCE_PLLC_OUT0                     _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IRQ_SOURCE_CLKS                  _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IRQ_SOURCE_PLLM_OUT0                     _MK_ENUM_CONST(3)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IRQ_SOURCE_PLLP_OUT0                     _MK_ENUM_CONST(4)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IRQ_SOURCE_PLLP_OUT4                     _MK_ENUM_CONST(5)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IRQ_SOURCE_PLLP_OUT3                     _MK_ENUM_CONST(6)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IRQ_SOURCE_CLKD                  _MK_ENUM_CONST(7)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IRQ_SOURCE_PLLX_OUT0                     _MK_ENUM_CONST(8)
+
+//  Same definitions as CWAKEUP_FIQ_SOURCE
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_RUN_SOURCE_SHIFT                 _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_RUN_SOURCE_FIELD                 (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_RUN_SOURCE_SHIFT)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_RUN_SOURCE_RANGE                 7:4
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_RUN_SOURCE_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_RUN_SOURCE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_RUN_SOURCE_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_RUN_SOURCE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_RUN_SOURCE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_RUN_SOURCE_CLKM                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_RUN_SOURCE_PLLC_OUT0                     _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_RUN_SOURCE_CLKS                  _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_RUN_SOURCE_PLLM_OUT0                     _MK_ENUM_CONST(3)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_RUN_SOURCE_PLLP_OUT0                     _MK_ENUM_CONST(4)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_RUN_SOURCE_PLLP_OUT4                     _MK_ENUM_CONST(5)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_RUN_SOURCE_PLLP_OUT3                     _MK_ENUM_CONST(6)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_RUN_SOURCE_CLKD                  _MK_ENUM_CONST(7)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_RUN_SOURCE_PLLX_OUT0                     _MK_ENUM_CONST(8)
+
+//  Same definitions as CWAKEUP_FIQ
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IDLE_SOURCE_SHIFT                        _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IDLE_SOURCE_FIELD                        (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IDLE_SOURCE_SHIFT)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IDLE_SOURCE_RANGE                        3:0
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IDLE_SOURCE_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IDLE_SOURCE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IDLE_SOURCE_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IDLE_SOURCE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IDLE_SOURCE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IDLE_SOURCE_CLKM                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IDLE_SOURCE_PLLC_OUT0                    _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IDLE_SOURCE_CLKS                 _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IDLE_SOURCE_PLLM_OUT0                    _MK_ENUM_CONST(3)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IDLE_SOURCE_PLLP_OUT0                    _MK_ENUM_CONST(4)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IDLE_SOURCE_PLLP_OUT4                    _MK_ENUM_CONST(5)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IDLE_SOURCE_PLLP_OUT3                    _MK_ENUM_CONST(6)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IDLE_SOURCE_CLKD                 _MK_ENUM_CONST(7)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IDLE_SOURCE_PLLX_OUT0                    _MK_ENUM_CONST(8)
+
+
+// Register CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0  
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0                 _MK_ADDR_CONST(0x24)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SECURE                  0x0
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_WORD_COUNT                      0x1
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_RESET_MASK                      _MK_MASK_CONST(0x8f00ffff)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_READ_MASK                       _MK_MASK_CONST(0x8f00ffff)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_WRITE_MASK                      _MK_MASK_CONST(0x8f00ffff)
+//  0 = disable divider.
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_ENB_SHIFT                    _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_ENB_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_ENB_SHIFT)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_ENB_RANGE                    31:31
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_ENB_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_ENB_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_ENB_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_ENB_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_ENB_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_ENB_INIT_ENUM                        DISABLE
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_ENB_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_ENB_ENABLE                   _MK_ENUM_CONST(1)
+
+//  0 = enable FIQ, disable FIQ.
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_COP_FIQ_SHIFT                       _MK_SHIFT_CONST(27)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_COP_FIQ_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_COP_FIQ_SHIFT)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_COP_FIQ_RANGE                       27:27
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_COP_FIQ_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_COP_FIQ_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_COP_FIQ_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_COP_FIQ_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_COP_FIQ_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+//  0 = enable FIQ, disable FIQ.
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_CPU_FIQ_SHIFT                       _MK_SHIFT_CONST(26)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_CPU_FIQ_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_CPU_FIQ_SHIFT)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_CPU_FIQ_RANGE                       26:26
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_CPU_FIQ_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_CPU_FIQ_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_CPU_FIQ_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_CPU_FIQ_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_CPU_FIQ_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+//  0 = enable IRQ, disable IRQ.
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_COP_IRQ_SHIFT                       _MK_SHIFT_CONST(25)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_COP_IRQ_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_COP_IRQ_SHIFT)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_COP_IRQ_RANGE                       25:25
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_COP_IRQ_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_COP_IRQ_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_COP_IRQ_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_COP_IRQ_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_COP_IRQ_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+//  0 = enable IRQ, disable IRQ.
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_CPU_IRQ_SHIFT                       _MK_SHIFT_CONST(24)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_CPU_IRQ_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_CPU_IRQ_SHIFT)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_CPU_IRQ_RANGE                       24:24
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_CPU_IRQ_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_CPU_IRQ_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_CPU_IRQ_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_CPU_IRQ_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_CPU_IRQ_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Actual value = n + 1.
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIVIDEND_SHIFT                       _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIVIDEND_FIELD                       (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIVIDEND_SHIFT)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIVIDEND_RANGE                       15:8
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIVIDEND_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIVIDEND_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIVIDEND_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIVIDEND_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIVIDEND_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Actual value = n + 1.
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIVISOR_SHIFT                        _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIVISOR_FIELD                        (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIVISOR_RANGE                        7:0
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIVISOR_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIVISOR_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIVISOR_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIVISOR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIVISOR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0  
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0                  _MK_ADDR_CONST(0x28)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SECURE                   0x0
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_WORD_COUNT                       0x1
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_RESET_VAL                        _MK_MASK_CONST(0x10000000)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_RESET_MASK                       _MK_MASK_CONST(0xff007777)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_READ_MASK                        _MK_MASK_CONST(0xff007777)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_WRITE_MASK                       _MK_MASK_CONST(0xff007777)
+// 0000=32KHz Clock source; 
+// 0001=IDLE Clock Source;
+// 001X=Run clock source; 
+// 01XX=IRQ Clock Source;
+// 1XXX=FIQ Clock Source
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SYS_STATE_SHIFT                  _MK_SHIFT_CONST(28)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SYS_STATE_FIELD                  (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SYS_STATE_SHIFT)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SYS_STATE_RANGE                  31:28
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SYS_STATE_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SYS_STATE_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SYS_STATE_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SYS_STATE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SYS_STATE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SYS_STATE_STDBY                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SYS_STATE_IDLE                   _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SYS_STATE_RUN                    _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SYS_STATE_IRQ                    _MK_ENUM_CONST(4)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SYS_STATE_FIQ                    _MK_ENUM_CONST(8)
+
+//  0 = NOP ; 1=Burst on COP FIQ
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_COP_AUTO_SWAKEUP_FROM_FIQ_SHIFT                  _MK_SHIFT_CONST(27)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_COP_AUTO_SWAKEUP_FROM_FIQ_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_COP_AUTO_SWAKEUP_FROM_FIQ_SHIFT)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_COP_AUTO_SWAKEUP_FROM_FIQ_RANGE                  27:27
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_COP_AUTO_SWAKEUP_FROM_FIQ_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_COP_AUTO_SWAKEUP_FROM_FIQ_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_COP_AUTO_SWAKEUP_FROM_FIQ_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_COP_AUTO_SWAKEUP_FROM_FIQ_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_COP_AUTO_SWAKEUP_FROM_FIQ_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  0 = NOP ; 1=Burst on CPU FIQ
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_CPU_AUTO_SWAKEUP_FROM_FIQ_SHIFT                  _MK_SHIFT_CONST(26)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_CPU_AUTO_SWAKEUP_FROM_FIQ_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_CPU_AUTO_SWAKEUP_FROM_FIQ_SHIFT)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_CPU_AUTO_SWAKEUP_FROM_FIQ_RANGE                  26:26
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_CPU_AUTO_SWAKEUP_FROM_FIQ_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_CPU_AUTO_SWAKEUP_FROM_FIQ_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_CPU_AUTO_SWAKEUP_FROM_FIQ_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_CPU_AUTO_SWAKEUP_FROM_FIQ_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_CPU_AUTO_SWAKEUP_FROM_FIQ_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  0 = NOP ; 1=Burst on COP IRQ
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_COP_AUTO_SWAKEUP_FROM_IRQ_SHIFT                  _MK_SHIFT_CONST(25)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_COP_AUTO_SWAKEUP_FROM_IRQ_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_COP_AUTO_SWAKEUP_FROM_IRQ_SHIFT)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_COP_AUTO_SWAKEUP_FROM_IRQ_RANGE                  25:25
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_COP_AUTO_SWAKEUP_FROM_IRQ_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_COP_AUTO_SWAKEUP_FROM_IRQ_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_COP_AUTO_SWAKEUP_FROM_IRQ_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_COP_AUTO_SWAKEUP_FROM_IRQ_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_COP_AUTO_SWAKEUP_FROM_IRQ_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  0 = NOP ; 1=Burst on CPU IRQ
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_CPU_AUTO_SWAKEUP_FROM_IRQ_SHIFT                  _MK_SHIFT_CONST(24)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_CPU_AUTO_SWAKEUP_FROM_IRQ_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_CPU_AUTO_SWAKEUP_FROM_IRQ_SHIFT)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_CPU_AUTO_SWAKEUP_FROM_IRQ_RANGE                  24:24
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_CPU_AUTO_SWAKEUP_FROM_IRQ_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_CPU_AUTO_SWAKEUP_FROM_IRQ_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_CPU_AUTO_SWAKEUP_FROM_IRQ_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_CPU_AUTO_SWAKEUP_FROM_IRQ_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_CPU_AUTO_SWAKEUP_FROM_IRQ_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  000 = clk_m,
+//  001 = pllC_out1,
+//  010 = pllP_out4,
+//  011 = pllP_out3,
+//  100 = pllP_out2,
+//  101 = clk_d,
+//  110 = clk_s,
+//  111 = pllM_out1,
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_FIQ_SOURCE_SHIFT                 _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_FIQ_SOURCE_FIELD                 (_MK_MASK_CONST(0x7) << CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_FIQ_SOURCE_SHIFT)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_FIQ_SOURCE_RANGE                 14:12
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_FIQ_SOURCE_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_FIQ_SOURCE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_FIQ_SOURCE_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_FIQ_SOURCE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_FIQ_SOURCE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_FIQ_SOURCE_CLKM                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_FIQ_SOURCE_PLLC_OUT1                     _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_FIQ_SOURCE_PLLP_OUT4                     _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_FIQ_SOURCE_PLLP_OUT3                     _MK_ENUM_CONST(3)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_FIQ_SOURCE_PLLP_OUT2                     _MK_ENUM_CONST(4)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_FIQ_SOURCE_CLKD                  _MK_ENUM_CONST(5)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_FIQ_SOURCE_CLKS                  _MK_ENUM_CONST(6)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_FIQ_SOURCE_PLLM_OUT1                     _MK_ENUM_CONST(7)
+
+//  Same definitions as SWAKEUP_FIQ_SOURCE
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IRQ_SOURCE_SHIFT                 _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IRQ_SOURCE_FIELD                 (_MK_MASK_CONST(0x7) << CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IRQ_SOURCE_SHIFT)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IRQ_SOURCE_RANGE                 10:8
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IRQ_SOURCE_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IRQ_SOURCE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IRQ_SOURCE_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IRQ_SOURCE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IRQ_SOURCE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IRQ_SOURCE_CLKM                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IRQ_SOURCE_PLLC_OUT1                     _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IRQ_SOURCE_PLLP_OUT4                     _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IRQ_SOURCE_PLLP_OUT3                     _MK_ENUM_CONST(3)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IRQ_SOURCE_PLLP_OUT2                     _MK_ENUM_CONST(4)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IRQ_SOURCE_CLKD                  _MK_ENUM_CONST(5)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IRQ_SOURCE_CLKS                  _MK_ENUM_CONST(6)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IRQ_SOURCE_PLLM_OUT1                     _MK_ENUM_CONST(7)
+
+//  Same definitions as SWAKEUP_FIQ_SOURCE
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_RUN_SOURCE_SHIFT                 _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_RUN_SOURCE_FIELD                 (_MK_MASK_CONST(0x7) << CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_RUN_SOURCE_SHIFT)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_RUN_SOURCE_RANGE                 6:4
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_RUN_SOURCE_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_RUN_SOURCE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_RUN_SOURCE_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_RUN_SOURCE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_RUN_SOURCE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_RUN_SOURCE_CLKM                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_RUN_SOURCE_PLLC_OUT1                     _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_RUN_SOURCE_PLLP_OUT4                     _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_RUN_SOURCE_PLLP_OUT3                     _MK_ENUM_CONST(3)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_RUN_SOURCE_PLLP_OUT2                     _MK_ENUM_CONST(4)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_RUN_SOURCE_CLKD                  _MK_ENUM_CONST(5)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_RUN_SOURCE_CLKS                  _MK_ENUM_CONST(6)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_RUN_SOURCE_PLLM_OUT1                     _MK_ENUM_CONST(7)
+
+//  Same definitions as SWAKEUP_FIQ_SOURCE
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IDLE_SOURCE_SHIFT                        _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IDLE_SOURCE_FIELD                        (_MK_MASK_CONST(0x7) << CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IDLE_SOURCE_SHIFT)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IDLE_SOURCE_RANGE                        2:0
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IDLE_SOURCE_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IDLE_SOURCE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IDLE_SOURCE_DEFAULT_MASK                 _MK_MASK_CONST(0x7)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IDLE_SOURCE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IDLE_SOURCE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IDLE_SOURCE_CLKM                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IDLE_SOURCE_PLLC_OUT1                    _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IDLE_SOURCE_PLLP_OUT4                    _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IDLE_SOURCE_PLLP_OUT3                    _MK_ENUM_CONST(3)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IDLE_SOURCE_PLLP_OUT2                    _MK_ENUM_CONST(4)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IDLE_SOURCE_CLKD                 _MK_ENUM_CONST(5)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IDLE_SOURCE_CLKS                 _MK_ENUM_CONST(6)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IDLE_SOURCE_PLLM_OUT1                    _MK_ENUM_CONST(7)
+
+
+// Register CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0  
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0                 _MK_ADDR_CONST(0x2c)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SECURE                  0x0
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_WORD_COUNT                      0x1
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_RESET_MASK                      _MK_MASK_CONST(0x8f00ffff)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_READ_MASK                       _MK_MASK_CONST(0x8f00ffff)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_WRITE_MASK                      _MK_MASK_CONST(0x8f00ffff)
+//  0 = disable divider.
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_ENB_SHIFT                    _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_ENB_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_ENB_SHIFT)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_ENB_RANGE                    31:31
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_ENB_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_ENB_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_ENB_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_ENB_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_ENB_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_ENB_INIT_ENUM                        DISABLE
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_ENB_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_ENB_ENABLE                   _MK_ENUM_CONST(1)
+
+//  0 = enable FIQ, disable FIQ.
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_COP_FIQ_SHIFT                       _MK_SHIFT_CONST(27)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_COP_FIQ_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_COP_FIQ_SHIFT)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_COP_FIQ_RANGE                       27:27
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_COP_FIQ_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_COP_FIQ_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_COP_FIQ_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_COP_FIQ_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_COP_FIQ_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+//  0 = enable FIQ, disable FIQ.
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_CPU_FIQ_SHIFT                       _MK_SHIFT_CONST(26)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_CPU_FIQ_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_CPU_FIQ_SHIFT)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_CPU_FIQ_RANGE                       26:26
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_CPU_FIQ_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_CPU_FIQ_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_CPU_FIQ_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_CPU_FIQ_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_CPU_FIQ_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+//  0 = enable IRQ, disable IRQ.
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_COP_IRQ_SHIFT                       _MK_SHIFT_CONST(25)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_COP_IRQ_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_COP_IRQ_SHIFT)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_COP_IRQ_RANGE                       25:25
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_COP_IRQ_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_COP_IRQ_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_COP_IRQ_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_COP_IRQ_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_COP_IRQ_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+//  0 = enable IRQ, disable IRQ.
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_CPU_IRQ_SHIFT                       _MK_SHIFT_CONST(24)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_CPU_IRQ_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_CPU_IRQ_SHIFT)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_CPU_IRQ_RANGE                       24:24
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_CPU_IRQ_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_CPU_IRQ_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_CPU_IRQ_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_CPU_IRQ_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_CPU_IRQ_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Actual value = n + 1.
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIVIDEND_SHIFT                       _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIVIDEND_FIELD                       (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIVIDEND_SHIFT)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIVIDEND_RANGE                       15:8
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIVIDEND_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIVIDEND_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIVIDEND_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIVIDEND_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIVIDEND_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Actual value = n + 1.
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIVISOR_SHIFT                        _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIVISOR_FIELD                        (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIVISOR_RANGE                        7:0
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIVISOR_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIVISOR_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIVISOR_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIVISOR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIVISOR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0  
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0                    _MK_ADDR_CONST(0x30)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_SECURE                     0x0
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_WORD_COUNT                         0x1
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_RESET_MASK                         _MK_MASK_CONST(0xbb)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_READ_MASK                  _MK_MASK_CONST(0xbb)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_WRITE_MASK                         _MK_MASK_CONST(0xbb)
+//  0=enable HCLK, 1=disable HCLK.
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_HCLK_DIS_SHIFT                     _MK_SHIFT_CONST(7)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_HCLK_DIS_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_HCLK_DIS_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_HCLK_DIS_RANGE                     7:7
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_HCLK_DIS_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_HCLK_DIS_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_HCLK_DIS_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_HCLK_DIS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_HCLK_DIS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+//  1/(n+1) of SCLK.
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_AHB_RATE_SHIFT                     _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_AHB_RATE_FIELD                     (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_AHB_RATE_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_AHB_RATE_RANGE                     5:4
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_AHB_RATE_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_AHB_RATE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_AHB_RATE_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_AHB_RATE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_AHB_RATE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+//  0=enable PCLK, 1=disable PCLK.
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_PCLK_DIS_SHIFT                     _MK_SHIFT_CONST(3)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_PCLK_DIS_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_PCLK_DIS_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_PCLK_DIS_RANGE                     3:3
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_PCLK_DIS_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_PCLK_DIS_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_PCLK_DIS_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_PCLK_DIS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_PCLK_DIS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+//  1/(n+1) of HCLK.
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_APB_RATE_SHIFT                     _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_APB_RATE_FIELD                     (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_APB_RATE_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_APB_RATE_RANGE                     1:0
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_APB_RATE_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_APB_RATE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_APB_RATE_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_APB_RATE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_APB_RATE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_PROG_DLY_CLK_0  
+#define CLK_RST_CONTROLLER_PROG_DLY_CLK_0                       _MK_ADDR_CONST(0x34)
+#define CLK_RST_CONTROLLER_PROG_DLY_CLK_0_SECURE                        0x0
+#define CLK_RST_CONTROLLER_PROG_DLY_CLK_0_WORD_COUNT                    0x1
+#define CLK_RST_CONTROLLER_PROG_DLY_CLK_0_RESET_VAL                     _MK_MASK_CONST(0x7700)
+#define CLK_RST_CONTROLLER_PROG_DLY_CLK_0_RESET_MASK                    _MK_MASK_CONST(0xff00)
+#define CLK_RST_CONTROLLER_PROG_DLY_CLK_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PROG_DLY_CLK_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PROG_DLY_CLK_0_READ_MASK                     _MK_MASK_CONST(0xff00)
+#define CLK_RST_CONTROLLER_PROG_DLY_CLK_0_WRITE_MASK                    _MK_MASK_CONST(0xff00)
+// 16 Taps of selectable delay for CLK_M clk doubler
+#define CLK_RST_CONTROLLER_PROG_DLY_CLK_0_CLK_D_DELCLK_SEL_SHIFT                        _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_PROG_DLY_CLK_0_CLK_D_DELCLK_SEL_FIELD                        (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_PROG_DLY_CLK_0_CLK_D_DELCLK_SEL_SHIFT)
+#define CLK_RST_CONTROLLER_PROG_DLY_CLK_0_CLK_D_DELCLK_SEL_RANGE                        15:12
+#define CLK_RST_CONTROLLER_PROG_DLY_CLK_0_CLK_D_DELCLK_SEL_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_PROG_DLY_CLK_0_CLK_D_DELCLK_SEL_DEFAULT                      _MK_MASK_CONST(0x7)
+#define CLK_RST_CONTROLLER_PROG_DLY_CLK_0_CLK_D_DELCLK_SEL_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_PROG_DLY_CLK_0_CLK_D_DELCLK_SEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PROG_DLY_CLK_0_CLK_D_DELCLK_SEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// 16 Taps of selectable delay for SYNC_CLK clk doubler
+#define CLK_RST_CONTROLLER_PROG_DLY_CLK_0_SYNC_CLK_DELCLK_SEL_SHIFT                     _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_PROG_DLY_CLK_0_SYNC_CLK_DELCLK_SEL_FIELD                     (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_PROG_DLY_CLK_0_SYNC_CLK_DELCLK_SEL_SHIFT)
+#define CLK_RST_CONTROLLER_PROG_DLY_CLK_0_SYNC_CLK_DELCLK_SEL_RANGE                     11:8
+#define CLK_RST_CONTROLLER_PROG_DLY_CLK_0_SYNC_CLK_DELCLK_SEL_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_PROG_DLY_CLK_0_SYNC_CLK_DELCLK_SEL_DEFAULT                   _MK_MASK_CONST(0x7)
+#define CLK_RST_CONTROLLER_PROG_DLY_CLK_0_SYNC_CLK_DELCLK_SEL_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_PROG_DLY_CLK_0_SYNC_CLK_DELCLK_SEL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PROG_DLY_CLK_0_SYNC_CLK_DELCLK_SEL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_RATE_0  
+#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_RATE_0                        _MK_ADDR_CONST(0x38)
+#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_RATE_0_SECURE                         0x0
+#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_RATE_0_WORD_COUNT                     0x1
+#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_RATE_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_RATE_0_RESET_MASK                     _MK_MASK_CONST(0x1f)
+#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_RATE_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_RATE_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_RATE_0_READ_MASK                      _MK_MASK_CONST(0x1f)
+#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_RATE_0_WRITE_MASK                     _MK_MASK_CONST(0x1f)
+//  0 = Enable AUDIO SYNC CLK
+#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_RATE_0_SYNC_CLK_DIS_SHIFT                     _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_RATE_0_SYNC_CLK_DIS_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_RATE_0_SYNC_CLK_DIS_SHIFT)
+#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_RATE_0_SYNC_CLK_DIS_RANGE                     4:4
+#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_RATE_0_SYNC_CLK_DIS_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_RATE_0_SYNC_CLK_DIS_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_RATE_0_SYNC_CLK_DIS_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_RATE_0_SYNC_CLK_DIS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_RATE_0_SYNC_CLK_DIS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// 0000 = SPDIFIN recovered bit clock.
+// 0001 = I2S1 bit clock.
+// 0010 = I2S2 bit clock.
+// 0011 = AC97 bit clock.
+// 0100 = pllA_out0.
+// 0101 = external audio clock (dap_mclk2).
+// 0110 = external audio clock (dap_mclk1).
+// 0111 = external vimclk (vimclk).
+// 1xxx = reserved
+#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_RATE_0_SYNC_CLK_RATE_SHIFT                    _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_RATE_0_SYNC_CLK_RATE_FIELD                    (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_RATE_0_SYNC_CLK_RATE_SHIFT)
+#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_RATE_0_SYNC_CLK_RATE_RANGE                    3:0
+#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_RATE_0_SYNC_CLK_RATE_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_RATE_0_SYNC_CLK_RATE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_RATE_0_SYNC_CLK_RATE_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_RATE_0_SYNC_CLK_RATE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_RATE_0_SYNC_CLK_RATE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_RATE_0_SYNC_CLK_RATE_SPDIFIN                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_RATE_0_SYNC_CLK_RATE_I2S1                     _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_RATE_0_SYNC_CLK_RATE_I2S2                     _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_RATE_0_SYNC_CLK_RATE_AC97                     _MK_ENUM_CONST(3)
+#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_RATE_0_SYNC_CLK_RATE_PLLA_OUT0                        _MK_ENUM_CONST(4)
+#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_RATE_0_SYNC_CLK_RATE_EXT_AUDIO_CLK2                   _MK_ENUM_CONST(5)
+#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_RATE_0_SYNC_CLK_RATE_EXT_AUDIO_CLK1                   _MK_ENUM_CONST(6)
+#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_RATE_0_SYNC_CLK_RATE_EXT_VIMCLK                       _MK_ENUM_CONST(7)
+
+
+// Reserved address 60 [0x3c] 
+
+// Register CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0  
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0                        _MK_ADDR_CONST(0x40)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_SECURE                         0x0
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_WORD_COUNT                     0x1
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_RESET_MASK                     _MK_MASK_CONST(0xff007777)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_READ_MASK                      _MK_MASK_CONST(0xff007777)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_WRITE_MASK                     _MK_MASK_CONST(0xff007777)
+// 0000=no skip.
+// 0001=skip base on IDLE Clock skip rate;
+// 001X=skip base on Run clock skip rate; 
+// 01XX=skip base on IRQ Clock skip rate;
+// 1XXX=skip base on FIQ Clock skip rate
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_STATE_SHIFT                       _MK_SHIFT_CONST(28)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_STATE_FIELD                       (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_STATE_SHIFT)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_STATE_RANGE                       31:28
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_STATE_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_STATE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_STATE_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_STATE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_STATE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+//  0 = NOP ; 1=Burst on COP FIQ
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_COP_FIQ_SHIFT                    _MK_SHIFT_CONST(27)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_COP_FIQ_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_COP_FIQ_SHIFT)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_COP_FIQ_RANGE                    27:27
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_COP_FIQ_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_COP_FIQ_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_COP_FIQ_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_COP_FIQ_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_COP_FIQ_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+//  0 = NOP ; 1=Burst on CPU FIQ
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_CPU_FIQ_SHIFT                    _MK_SHIFT_CONST(26)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_CPU_FIQ_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_CPU_FIQ_SHIFT)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_CPU_FIQ_RANGE                    26:26
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_CPU_FIQ_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_CPU_FIQ_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_CPU_FIQ_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_CPU_FIQ_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_CPU_FIQ_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+//  0 = NOP ; 1=Burst on COP IRQ
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_COP_IRQ_SHIFT                    _MK_SHIFT_CONST(25)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_COP_IRQ_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_COP_IRQ_SHIFT)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_COP_IRQ_RANGE                    25:25
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_COP_IRQ_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_COP_IRQ_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_COP_IRQ_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_COP_IRQ_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_COP_IRQ_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+//  0 = NOP ; 1=Burst on CPU IRQ
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_CPU_IRQ_SHIFT                    _MK_SHIFT_CONST(24)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_CPU_IRQ_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_CPU_IRQ_SHIFT)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_CPU_IRQ_RANGE                    24:24
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_CPU_IRQ_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_CPU_IRQ_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_CPU_IRQ_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_CPU_IRQ_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_CPU_IRQ_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+//  skip n/16 clock.
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_FIQ_SHIFT                    _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_FIQ_FIELD                    (_MK_MASK_CONST(0x7) << CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_FIQ_SHIFT)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_FIQ_RANGE                    14:12
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_FIQ_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_FIQ_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_FIQ_DEFAULT_MASK                     _MK_MASK_CONST(0x7)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_FIQ_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_FIQ_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+//  Same definitions as COP_CLK_SKIP_RATE_FIQ
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_IRQ_SHIFT                    _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_IRQ_FIELD                    (_MK_MASK_CONST(0x7) << CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_IRQ_SHIFT)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_IRQ_RANGE                    10:8
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_IRQ_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_IRQ_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_IRQ_DEFAULT_MASK                     _MK_MASK_CONST(0x7)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_IRQ_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_IRQ_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+//  Same definitions as COP_CLK_SKIP_RATE_FIQ
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_RUN_SHIFT                    _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_RUN_FIELD                    (_MK_MASK_CONST(0x7) << CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_RUN_SHIFT)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_RUN_RANGE                    6:4
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_RUN_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_RUN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_RUN_DEFAULT_MASK                     _MK_MASK_CONST(0x7)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_RUN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_RUN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+//  Same definitions as COP_CLK_SKIP_RATE_FIQ
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_IDLE_SHIFT                   _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_IDLE_FIELD                   (_MK_MASK_CONST(0x7) << CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_IDLE_SHIFT)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_IDLE_RANGE                   2:0
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_IDLE_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_IDLE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_IDLE_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_IDLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_IDLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_MASK_ARM_0  
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0                       _MK_ADDR_CONST(0x44)
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_SECURE                        0x0
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_WORD_COUNT                    0x1
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_RESET_MASK                    _MK_MASK_CONST(0x80030003)
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_READ_MASK                     _MK_MASK_CONST(0x80030003)
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_WRITE_MASK                    _MK_MASK_CONST(0x30003)
+//  1 = ARM11 AXI pipe is flushed.
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_AXI_FLUSH_DONE_SHIFT                  _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_AXI_FLUSH_DONE_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_MASK_ARM_0_AXI_FLUSH_DONE_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_AXI_FLUSH_DONE_RANGE                  31:31
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_AXI_FLUSH_DONE_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_AXI_FLUSH_DONE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_AXI_FLUSH_DONE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_AXI_FLUSH_DONE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_AXI_FLUSH_DONE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  1 = reset CPU0 when flow control assert halt.
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_RST_CPU0_WHEN_HALT_SHIFT                      _MK_SHIFT_CONST(17)
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_RST_CPU0_WHEN_HALT_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_MASK_ARM_0_RST_CPU0_WHEN_HALT_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_RST_CPU0_WHEN_HALT_RANGE                      17:17
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_RST_CPU0_WHEN_HALT_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_RST_CPU0_WHEN_HALT_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_RST_CPU0_WHEN_HALT_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_RST_CPU0_WHEN_HALT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_RST_CPU0_WHEN_HALT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+//  1 = HW will stop clock to CPU when halt, 0 = no clock stop.
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_CLK_MASK_CPU_HALT_SHIFT                       _MK_SHIFT_CONST(16)
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_CLK_MASK_CPU_HALT_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_MASK_ARM_0_CLK_MASK_CPU_HALT_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_CLK_MASK_CPU_HALT_RANGE                       16:16
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_CLK_MASK_CPU_HALT_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_CLK_MASK_CPU_HALT_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_CLK_MASK_CPU_HALT_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_CLK_MASK_CPU_HALT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_CLK_MASK_CPU_HALT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+//  00 = no clock masking.
+//  01 = u2_nwait_r.
+//  10 = u2_nwait_r.
+//  11 = no clock masking.
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_CLK_MASK_COP_SHIFT                    _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_CLK_MASK_COP_FIELD                    (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_MASK_ARM_0_CLK_MASK_COP_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_CLK_MASK_COP_RANGE                    1:0
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_CLK_MASK_COP_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_CLK_MASK_COP_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_CLK_MASK_COP_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_CLK_MASK_COP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_CLK_MASK_COP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_MISC_CLK_ENB_0  
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0                       _MK_ADDR_CONST(0x48)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_SECURE                        0x0
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_WORD_COUNT                    0x1
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_RESET_MASK                    _MK_MASK_CONST(0x10f00000)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_READ_MASK                     _MK_MASK_CONST(0x10f00000)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_WRITE_MASK                    _MK_MASK_CONST(0x10f00000)
+// 1 = VISIBLE, 0 = NOT VISIBLE.
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CFG_ALL_VISIBLE_SHIFT                 _MK_SHIFT_CONST(28)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CFG_ALL_VISIBLE_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CFG_ALL_VISIBLE_SHIFT)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CFG_ALL_VISIBLE_RANGE                 28:28
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CFG_ALL_VISIBLE_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CFG_ALL_VISIBLE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CFG_ALL_VISIBLE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CFG_ALL_VISIBLE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CFG_ALL_VISIBLE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// 00 = osc, 01 = osc/2, 10 = osc/4, 11 = osc/8.
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_DEV1_OSC_DIV_SEL_SHIFT                        _MK_SHIFT_CONST(22)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_DEV1_OSC_DIV_SEL_FIELD                        (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_MISC_CLK_ENB_0_DEV1_OSC_DIV_SEL_SHIFT)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_DEV1_OSC_DIV_SEL_RANGE                        23:22
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_DEV1_OSC_DIV_SEL_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_DEV1_OSC_DIV_SEL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_DEV1_OSC_DIV_SEL_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_DEV1_OSC_DIV_SEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_DEV1_OSC_DIV_SEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// 00 = osc, 01 = osc/2, 10 = osc/4, 11 = osc/8.
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_DEV2_OSC_DIV_SEL_SHIFT                        _MK_SHIFT_CONST(20)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_DEV2_OSC_DIV_SEL_FIELD                        (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_MISC_CLK_ENB_0_DEV2_OSC_DIV_SEL_SHIFT)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_DEV2_OSC_DIV_SEL_RANGE                        21:20
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_DEV2_OSC_DIV_SEL_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_DEV2_OSC_DIV_SEL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_DEV2_OSC_DIV_SEL_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_DEV2_OSC_DIV_SEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_DEV2_OSC_DIV_SEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0  
+#define CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0                      _MK_ADDR_CONST(0x4c)
+#define CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0_SECURE                       0x0
+#define CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0_WORD_COUNT                   0x1
+#define CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0_RESET_VAL                    _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0_RESET_MASK                   _MK_MASK_CONST(0x303)
+#define CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0_READ_MASK                    _MK_MASK_CONST(0x303)
+#define CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0_WRITE_MASK                   _MK_MASK_CONST(0x303)
+// Clock divider ratio for the cpu bridge devices
+// connected to CPU/L2-cache.
+//   00 = div-by-1.
+//   01 = div-by-2.
+//   10 = div-by-3.
+//   11 = div-by-4.
+#define CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0_CPU_BRIDGE_CLKDIV_SHIFT                      _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0_CPU_BRIDGE_CLKDIV_FIELD                      (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0_CPU_BRIDGE_CLKDIV_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0_CPU_BRIDGE_CLKDIV_RANGE                      1:0
+#define CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0_CPU_BRIDGE_CLKDIV_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0_CPU_BRIDGE_CLKDIV_DEFAULT                    _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0_CPU_BRIDGE_CLKDIV_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0_CPU_BRIDGE_CLKDIV_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0_CPU_BRIDGE_CLKDIV_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// 1 = CPU0 clock stop, 0 = CPU0 clock run.
+#define CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0_CPU0_CLK_STP_SHIFT                   _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0_CPU0_CLK_STP_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0_CPU0_CLK_STP_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0_CPU0_CLK_STP_RANGE                   8:8
+#define CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0_CPU0_CLK_STP_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0_CPU0_CLK_STP_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0_CPU0_CLK_STP_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0_CPU0_CLK_STP_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0_CPU0_CLK_STP_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// 1 = CPU1 clock stop, 0 = CPU1 clock run.
+#define CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0_CPU1_CLK_STP_SHIFT                   _MK_SHIFT_CONST(9)
+#define CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0_CPU1_CLK_STP_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0_CPU1_CLK_STP_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0_CPU1_CLK_STP_RANGE                   9:9
+#define CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0_CPU1_CLK_STP_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0_CPU1_CLK_STP_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0_CPU1_CLK_STP_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0_CPU1_CLK_STP_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0_CPU1_CLK_STP_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_OSC_CTRL_0  
+#define CLK_RST_CONTROLLER_OSC_CTRL_0                   _MK_ADDR_CONST(0x50)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_SECURE                    0x0
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_WORD_COUNT                        0x1
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_RESET_VAL                         _MK_MASK_CONST(0x3f1)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_RESET_MASK                        _MK_MASK_CONST(0xfff1f3f3)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_READ_MASK                         _MK_MASK_CONST(0xfff1f3f3)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_WRITE_MASK                        _MK_MASK_CONST(0xfff1f3f3)
+// 00 = 13MHz, 01 = 19.2MHz, 10 = 12MHz, 11 = 26MHz.
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSC_FREQ_SHIFT                    _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSC_FREQ_FIELD                    (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_OSC_CTRL_0_OSC_FREQ_SHIFT)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSC_FREQ_RANGE                    31:30
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSC_FREQ_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSC_FREQ_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSC_FREQ_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSC_FREQ_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSC_FREQ_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// PLL reference clock divide.  00 = /1, 01 = /2, 10 = /4, 11 = reserve.
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_PLL_REF_DIV_SHIFT                 _MK_SHIFT_CONST(28)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_PLL_REF_DIV_FIELD                 (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_OSC_CTRL_0_PLL_REF_DIV_SHIFT)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_PLL_REF_DIV_RANGE                 29:28
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_PLL_REF_DIV_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_PLL_REF_DIV_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_PLL_REF_DIV_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_PLL_REF_DIV_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_PLL_REF_DIV_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Crystal oscillator spare register control.
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSCFI_SPARE_SHIFT                 _MK_SHIFT_CONST(20)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSCFI_SPARE_FIELD                 (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_OSC_CTRL_0_OSCFI_SPARE_SHIFT)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSCFI_SPARE_RANGE                 27:20
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSCFI_SPARE_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSCFI_SPARE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSCFI_SPARE_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSCFI_SPARE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSCFI_SPARE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Crystal oscillator duty cycle control.
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XODS_SHIFT                        _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XODS_FIELD                        (_MK_MASK_CONST(0x1f) << CLK_RST_CONTROLLER_OSC_CTRL_0_XODS_SHIFT)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XODS_RANGE                        16:12
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XODS_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XODS_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XODS_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XODS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XODS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Crystal oscillator drive strength control.
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOFS_SHIFT                        _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOFS_FIELD                        (_MK_MASK_CONST(0x3f) << CLK_RST_CONTROLLER_OSC_CTRL_0_XOFS_SHIFT)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOFS_RANGE                        9:4
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOFS_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOFS_DEFAULT                      _MK_MASK_CONST(0x3f)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOFS_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOFS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOFS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Crystal oscillator bypass enable (1 = enable bypass).
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOBP_SHIFT                        _MK_SHIFT_CONST(1)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOBP_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_OSC_CTRL_0_XOBP_SHIFT)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOBP_RANGE                        1:1
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOBP_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOBP_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOBP_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOBP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOBP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Crystal oscillator enable (1 = enable).
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOE_SHIFT                 _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOE_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_OSC_CTRL_0_XOE_SHIFT)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOE_RANGE                 0:0
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOE_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOE_DEFAULT                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_PLL_LFSR_0  
+#define CLK_RST_CONTROLLER_PLL_LFSR_0                   _MK_ADDR_CONST(0x54)
+#define CLK_RST_CONTROLLER_PLL_LFSR_0_SECURE                    0x0
+#define CLK_RST_CONTROLLER_PLL_LFSR_0_WORD_COUNT                        0x1
+#define CLK_RST_CONTROLLER_PLL_LFSR_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLL_LFSR_0_RESET_MASK                        _MK_MASK_CONST(0xffff)
+#define CLK_RST_CONTROLLER_PLL_LFSR_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLL_LFSR_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLL_LFSR_0_READ_MASK                         _MK_MASK_CONST(0xffff)
+#define CLK_RST_CONTROLLER_PLL_LFSR_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+// Random number generated from PLL linear feedback shift register.
+#define CLK_RST_CONTROLLER_PLL_LFSR_0_RND_SHIFT                 _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_PLL_LFSR_0_RND_FIELD                 (_MK_MASK_CONST(0xffff) << CLK_RST_CONTROLLER_PLL_LFSR_0_RND_SHIFT)
+#define CLK_RST_CONTROLLER_PLL_LFSR_0_RND_RANGE                 15:0
+#define CLK_RST_CONTROLLER_PLL_LFSR_0_RND_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_PLL_LFSR_0_RND_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLL_LFSR_0_RND_DEFAULT_MASK                  _MK_MASK_CONST(0xffff)
+#define CLK_RST_CONTROLLER_PLL_LFSR_0_RND_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLL_LFSR_0_RND_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_OSC_FREQ_DET_0  
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0                       _MK_ADDR_CONST(0x58)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_SECURE                        0x0
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_WORD_COUNT                    0x1
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_RESET_MASK                    _MK_MASK_CONST(0x8000000f)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_READ_MASK                     _MK_MASK_CONST(0x8000000f)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_WRITE_MASK                    _MK_MASK_CONST(0x8000000f)
+// 0 = default, 1 = enable osc frequency detect. 
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_OSC_FREQ_DET_TRIG_SHIFT                       _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_OSC_FREQ_DET_TRIG_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_OSC_FREQ_DET_0_OSC_FREQ_DET_TRIG_SHIFT)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_OSC_FREQ_DET_TRIG_RANGE                       31:31
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_OSC_FREQ_DET_TRIG_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_OSC_FREQ_DET_TRIG_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_OSC_FREQ_DET_TRIG_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_OSC_FREQ_DET_TRIG_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_OSC_FREQ_DET_TRIG_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_OSC_FREQ_DET_TRIG_INIT_ENUM                   DISABLE
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_OSC_FREQ_DET_TRIG_DISABLE                     _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_OSC_FREQ_DET_TRIG_ENABLE                      _MK_ENUM_CONST(1)
+
+// Indicate the # of 32KHz clock period as window in n+1 scheme.
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_REF_CLK_WIN_CFG_SHIFT                 _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_REF_CLK_WIN_CFG_FIELD                 (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_OSC_FREQ_DET_0_REF_CLK_WIN_CFG_SHIFT)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_REF_CLK_WIN_CFG_RANGE                 3:0
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_REF_CLK_WIN_CFG_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_REF_CLK_WIN_CFG_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_REF_CLK_WIN_CFG_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_REF_CLK_WIN_CFG_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_REF_CLK_WIN_CFG_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0  
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0                        _MK_ADDR_CONST(0x5c)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_SECURE                         0x0
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_WORD_COUNT                     0x1
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_RESET_MASK                     _MK_MASK_CONST(0x8000ffff)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_READ_MASK                      _MK_MASK_CONST(0x8000ffff)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
+// 0 = not busy, 1 = busy.
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_OSC_FREQ_DET_BUSY_SHIFT                        _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_OSC_FREQ_DET_BUSY_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_OSC_FREQ_DET_BUSY_SHIFT)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_OSC_FREQ_DET_BUSY_RANGE                        31:31
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_OSC_FREQ_DET_BUSY_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_OSC_FREQ_DET_BUSY_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_OSC_FREQ_DET_BUSY_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_OSC_FREQ_DET_BUSY_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_OSC_FREQ_DET_BUSY_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// indicate the number of osc count within the 32KHz clock reference window.
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_OSC_FREQ_DET_CNT_SHIFT                 _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_OSC_FREQ_DET_CNT_FIELD                 (_MK_MASK_CONST(0xffff) << CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_OSC_FREQ_DET_CNT_SHIFT)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_OSC_FREQ_DET_CNT_RANGE                 15:0
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_OSC_FREQ_DET_CNT_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_OSC_FREQ_DET_CNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_OSC_FREQ_DET_CNT_DEFAULT_MASK                  _MK_MASK_CONST(0xffff)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_OSC_FREQ_DET_CNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_OSC_FREQ_DET_CNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0  
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0                   _MK_ADDR_CONST(0x60)
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_SECURE                    0x0
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_WORD_COUNT                        0x1
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_RESET_MASK                        _MK_MASK_CONST(0x3ff)
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_READ_MASK                         _MK_MASK_CONST(0x3ff)
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_WRITE_MASK                        _MK_MASK_CONST(0x3ff)
+// PTO counter reset.
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_CNT_RST_SHIFT                 _MK_SHIFT_CONST(9)
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_CNT_RST_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_CNT_RST_SHIFT)
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_CNT_RST_RANGE                 9:9
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_CNT_RST_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_CNT_RST_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_CNT_RST_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_CNT_RST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_CNT_RST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// enable PTO counter.
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_CNT_EN_SHIFT                  _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_CNT_EN_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_CNT_EN_SHIFT)
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_CNT_EN_RANGE                  8:8
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_CNT_EN_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_CNT_EN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_CNT_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_CNT_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_CNT_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// PLL PTO source select.
+// 0000 = PLLX PTO div-2.
+// 0001 = PLLC PTO div-2.
+// 0010 = PLLM PTO div-2.
+// 0011 = PLLP PTO div-2.
+// 0100 = PLLA PTO div-2.
+// 0101 = PLLU PTO div-2.
+// 0110 = PLLD PTO div-2.
+// 0111 = PLLE PTO div-2.
+// 1000 = PLLS PTO div-2.
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_SRC_SEL_SHIFT                 _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_SRC_SEL_FIELD                 (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_SRC_SEL_SHIFT)
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_SRC_SEL_RANGE                 7:4
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_SRC_SEL_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_SRC_SEL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_SRC_SEL_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_SRC_SEL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_SRC_SEL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Indicate the # of 32KHz clock period as window in n+1 scheme.
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_REF_CLK_WIN_CFG_SHIFT                 _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_REF_CLK_WIN_CFG_FIELD                 (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_REF_CLK_WIN_CFG_SHIFT)
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_REF_CLK_WIN_CFG_RANGE                 3:0
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_REF_CLK_WIN_CFG_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_REF_CLK_WIN_CFG_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_REF_CLK_WIN_CFG_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_REF_CLK_WIN_CFG_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_REF_CLK_WIN_CFG_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0  
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0                 _MK_ADDR_CONST(0x64)
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0_SECURE                  0x0
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0_WORD_COUNT                      0x1
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0_RESET_MASK                      _MK_MASK_CONST(0x8000ffff)
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0_READ_MASK                       _MK_MASK_CONST(0x8000ffff)
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
+// 0 = not busy, 1 = busy.
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0_PTO_CLK_CNT_BUSY_SHIFT                  _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0_PTO_CLK_CNT_BUSY_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0_PTO_CLK_CNT_BUSY_SHIFT)
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0_PTO_CLK_CNT_BUSY_RANGE                  31:31
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0_PTO_CLK_CNT_BUSY_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0_PTO_CLK_CNT_BUSY_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0_PTO_CLK_CNT_BUSY_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0_PTO_CLK_CNT_BUSY_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0_PTO_CLK_CNT_BUSY_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// indicate the number of PTO clock count within the 32KHz clock reference window.
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0_PTO_CLK_CNT_SHIFT                       _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0_PTO_CLK_CNT_FIELD                       (_MK_MASK_CONST(0xffff) << CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0_PTO_CLK_CNT_SHIFT)
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0_PTO_CLK_CNT_RANGE                       15:0
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0_PTO_CLK_CNT_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0_PTO_CLK_CNT_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0_PTO_CLK_CNT_DEFAULT_MASK                        _MK_MASK_CONST(0xffff)
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0_PTO_CLK_CNT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0_PTO_CLK_CNT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_PLLE_SS_CNTL_0  
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0                       _MK_ADDR_CONST(0x68)
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_SECURE                        0x0
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_WORD_COUNT                    0x1
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_RESET_VAL                     _MK_MASK_CONST(0x5e00)
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
+// interpolator bias current. 
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_INTEGOFFSET_SHIFT                        _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_INTEGOFFSET_FIELD                        (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_INTEGOFFSET_SHIFT)
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_INTEGOFFSET_RANGE                        31:30
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_INTEGOFFSET_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_INTEGOFFSET_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_INTEGOFFSET_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_INTEGOFFSET_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_INTEGOFFSET_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Triangle generator increment interval control.
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCINCINTRV_SHIFT                        _MK_SHIFT_CONST(24)
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCINCINTRV_FIELD                        (_MK_MASK_CONST(0x3f) << CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCINCINTRV_SHIFT)
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCINCINTRV_RANGE                        29:24
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCINCINTRV_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCINCINTRV_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCINCINTRV_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCINCINTRV_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCINCINTRV_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Triangle generator increment control.
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCINC_SHIFT                     _MK_SHIFT_CONST(16)
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCINC_FIELD                     (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCINC_SHIFT)
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCINC_RANGE                     23:16
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCINC_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCINC_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCINC_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCINC_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCINC_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// 0 gives down spread, 1 gives up-spread.
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCINVERT_SHIFT                  _MK_SHIFT_CONST(15)
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCINVERT_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCINVERT_SHIFT)
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCINVERT_RANGE                  15:15
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCINVERT_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCINVERT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCINVERT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCINVERT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCINVERT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// 0 gives control to SSCINVERT, 1 enables center spread.
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCCENTER_SHIFT                  _MK_SHIFT_CONST(14)
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCCENTER_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCCENTER_SHIFT)
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCCENTER_RANGE                  14:14
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCCENTER_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCCENTER_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCCENTER_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCCENTER_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCCENTER_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Bypass from pulse density modulator. Normally set to zero.
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCPDMBYP_SHIFT                  _MK_SHIFT_CONST(13)
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCPDMBYP_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCPDMBYP_SHIFT)
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCPDMBYP_RANGE                  13:13
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCPDMBYP_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCPDMBYP_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCPDMBYP_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCPDMBYP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCPDMBYP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// 0 enables spreading, 1 disables spreading.
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCBYP_SHIFT                     _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCBYP_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCBYP_SHIFT)
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCBYP_RANGE                     12:12
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCBYP_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCBYP_DEFAULT                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCBYP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCBYP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCBYP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Interpolator reset. 0=normal operation  1=resets SS machine.
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_INTERP_RESET_SHIFT                       _MK_SHIFT_CONST(11)
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_INTERP_RESET_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_INTERP_RESET_SHIFT)
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_INTERP_RESET_RANGE                       11:11
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_INTERP_RESET_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_INTERP_RESET_DEFAULT                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_INTERP_RESET_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_INTERP_RESET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_INTERP_RESET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// When set feedback clock bypasses interpolator. Default value is zero.
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_BYPASS_SS_SHIFT                  _MK_SHIFT_CONST(10)
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_BYPASS_SS_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_BYPASS_SS_SHIFT)
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_BYPASS_SS_RANGE                  10:10
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_BYPASS_SS_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_BYPASS_SS_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_BYPASS_SS_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_BYPASS_SS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_BYPASS_SS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Enables reference current for external devices like PLL_DIFFCLKBUF_CML.
+// Overrides IDDQ and ENABLE for bandgap.
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_EN_IREF_SHIFT                    _MK_SHIFT_CONST(9)
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_EN_IREF_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_EN_IREF_SHIFT)
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_EN_IREF_RANGE                    9:9
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_EN_IREF_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_EN_IREF_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_EN_IREF_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_EN_IREF_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_EN_IREF_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Spread limit control.
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCMAX_SHIFT                     _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCMAX_FIELD                     (_MK_MASK_CONST(0x1ff) << CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCMAX_SHIFT)
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCMAX_RANGE                     8:0
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCMAX_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCMAX_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCMAX_DEFAULT_MASK                      _MK_MASK_CONST(0x1ff)
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCMAX_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCMAX_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Reserved address 108 [0x6c] 
+
+// Register CLK_RST_CONTROLLER_BOND_OUT_L_0  
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0                 _MK_ADDR_CONST(0x70)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_SECURE                  0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_WORD_COUNT                      0x1
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_RESET_MASK                      _MK_MASK_CONST(0xbffffff9)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_READ_MASK                       _MK_MASK_CONST(0xbffffff9)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_WRITE_MASK                      _MK_MASK_CONST(0xbffffff9)
+// Bond out COP cache controller.
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_CACHE2_SHIFT                   _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_CACHE2_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_CACHE2_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_CACHE2_RANGE                   31:31
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_CACHE2_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_CACHE2_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_CACHE2_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_CACHE2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_CACHE2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Bond out vector co-processor.
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_VCP_SHIFT                      _MK_SHIFT_CONST(29)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_VCP_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_VCP_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_VCP_RANGE                      29:29
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_VCP_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_VCP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_VCP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_VCP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_VCP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Bond out HOST1X.
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_HOST1X_SHIFT                   _MK_SHIFT_CONST(28)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_HOST1X_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_HOST1X_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_HOST1X_RANGE                   28:28
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_HOST1X_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_HOST1X_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_HOST1X_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_HOST1X_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_HOST1X_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Bond out DISP1 controller.
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_DISP1_SHIFT                    _MK_SHIFT_CONST(27)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_DISP1_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_DISP1_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_DISP1_RANGE                    27:27
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_DISP1_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_DISP1_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_DISP1_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_DISP1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_DISP1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Bond out DISP2 controller.
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_DISP2_SHIFT                    _MK_SHIFT_CONST(26)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_DISP2_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_DISP2_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_DISP2_RANGE                    26:26
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_DISP2_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_DISP2_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_DISP2_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_DISP2_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_DISP2_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Bond out IDE controller
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_IDE_SHIFT                      _MK_SHIFT_CONST(25)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_IDE_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_IDE_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_IDE_RANGE                      25:25
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_IDE_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_IDE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_IDE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_IDE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_IDE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Bond out 3D controller.
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_3D_SHIFT                       _MK_SHIFT_CONST(24)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_3D_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_3D_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_3D_RANGE                       24:24
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_3D_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_3D_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_3D_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_3D_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_3D_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Bond out ISP controller.
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_ISP_SHIFT                      _MK_SHIFT_CONST(23)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_ISP_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_ISP_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_ISP_RANGE                      23:23
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_ISP_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_ISP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_ISP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_ISP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_ISP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Bond out USB controller
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_USBD_SHIFT                     _MK_SHIFT_CONST(22)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_USBD_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_USBD_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_USBD_RANGE                     22:22
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_USBD_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_USBD_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_USBD_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_USBD_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_USBD_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Bond out 2D graphics engine.
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_2D_SHIFT                       _MK_SHIFT_CONST(21)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_2D_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_2D_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_2D_RANGE                       21:21
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_2D_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_2D_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_2D_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_2D_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_2D_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Bond out VI controller.
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_VI_SHIFT                       _MK_SHIFT_CONST(20)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_VI_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_VI_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_VI_RANGE                       20:20
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_VI_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_VI_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_VI_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_VI_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_VI_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Bond out EPP controller.
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_EPP_SHIFT                      _MK_SHIFT_CONST(19)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_EPP_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_EPP_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_EPP_RANGE                      19:19
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_EPP_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_EPP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_EPP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_EPP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_EPP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Bond out I2S 2 controller
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_I2S2_SHIFT                     _MK_SHIFT_CONST(18)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_I2S2_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_I2S2_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_I2S2_RANGE                     18:18
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_I2S2_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_I2S2_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_I2S2_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_I2S2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_I2S2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Bond out PWM (Pulse Width Modulator)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_PWM_SHIFT                      _MK_SHIFT_CONST(17)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_PWM_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_PWM_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_PWM_RANGE                      17:17
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_PWM_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_PWM_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_PWM_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_PWM_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_PWM_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Bond out 3-Wire Interface Controller
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_TWC_SHIFT                      _MK_SHIFT_CONST(16)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_TWC_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_TWC_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_TWC_RANGE                      16:16
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_TWC_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_TWC_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_TWC_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_TWC_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_TWC_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Bond out SDMMC4 controller.
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SDMMC4_SHIFT                   _MK_SHIFT_CONST(15)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SDMMC4_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SDMMC4_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SDMMC4_RANGE                   15:15
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SDMMC4_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SDMMC4_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SDMMC4_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SDMMC4_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SDMMC4_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Bond out SDMMC1 controller.
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SDMMC1_SHIFT                   _MK_SHIFT_CONST(14)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SDMMC1_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SDMMC1_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SDMMC1_RANGE                   14:14
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SDMMC1_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SDMMC1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SDMMC1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SDMMC1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SDMMC1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Bond out NAND flash controller.
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_NDFLASH_SHIFT                  _MK_SHIFT_CONST(13)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_NDFLASH_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_NDFLASH_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_NDFLASH_RANGE                  13:13
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_NDFLASH_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_NDFLASH_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_NDFLASH_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_NDFLASH_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_NDFLASH_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Bond out I2C1 Controller
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_I2C1_SHIFT                     _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_I2C1_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_I2C1_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_I2C1_RANGE                     12:12
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_I2C1_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_I2C1_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_I2C1_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_I2C1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_I2C1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Bond out I2S1 Controller
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_I2S1_SHIFT                     _MK_SHIFT_CONST(11)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_I2S1_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_I2S1_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_I2S1_RANGE                     11:11
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_I2S1_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_I2S1_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_I2S1_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_I2S1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_I2S1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Bond out SPDIF Controller
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SPDIF_SHIFT                    _MK_SHIFT_CONST(10)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SPDIF_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SPDIF_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SPDIF_RANGE                    10:10
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SPDIF_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SPDIF_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SPDIF_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SPDIF_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SPDIF_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Bond out SDMMC2 controller.
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SDMMC2_SHIFT                   _MK_SHIFT_CONST(9)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SDMMC2_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SDMMC2_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SDMMC2_RANGE                   9:9
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SDMMC2_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SDMMC2_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SDMMC2_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SDMMC2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SDMMC2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Bond out GPIO Controller
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_GPIO_SHIFT                     _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_GPIO_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_GPIO_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_GPIO_RANGE                     8:8
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_GPIO_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_GPIO_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_GPIO_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_GPIO_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_GPIO_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Bond out UARTB/VFIR Controller
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_UARTB_SHIFT                    _MK_SHIFT_CONST(7)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_UARTB_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_UARTB_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_UARTB_RANGE                    7:7
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_UARTB_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_UARTB_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_UARTB_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_UARTB_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_UARTB_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Bond out UARTA Controller
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_UARTA_SHIFT                    _MK_SHIFT_CONST(6)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_UARTA_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_UARTA_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_UARTA_RANGE                    6:6
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_UARTA_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_UARTA_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_UARTA_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_UARTA_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_UARTA_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Bond out Timer Controller
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_TMR_SHIFT                      _MK_SHIFT_CONST(5)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_TMR_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_TMR_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_TMR_RANGE                      5:5
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_TMR_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_TMR_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_TMR_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_TMR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_TMR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Bond out RTC Controller
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_RTC_SHIFT                      _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_RTC_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_RTC_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_RTC_RANGE                      4:4
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_RTC_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_RTC_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_RTC_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_RTC_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_RTC_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Bond out AC97 Controller
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_AC97_SHIFT                     _MK_SHIFT_CONST(3)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_AC97_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_AC97_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_AC97_RANGE                     3:3
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_AC97_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_AC97_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_AC97_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_AC97_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_AC97_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Bond out CPU.
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_CPU_SHIFT                      _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_CPU_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_CPU_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_CPU_RANGE                      0:0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_CPU_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_CPU_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_CPU_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_CPU_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_CPU_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_BOND_OUT_H_0  
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0                 _MK_ADDR_CONST(0x74)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_SECURE                  0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_WORD_COUNT                      0x1
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_RESET_MASK                      _MK_MASK_CONST(0xfefffff7)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_READ_MASK                       _MK_MASK_CONST(0xfefffff7)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_WRITE_MASK                      _MK_MASK_CONST(0xfefffff7)
+// Bond out BSEV Controller.
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_BSEV_SHIFT                     _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_BSEV_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_BSEV_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_BSEV_RANGE                     31:31
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_BSEV_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_BSEV_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_BSEV_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_BSEV_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_BSEV_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Bond out BSEA Controller
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_BSEA_SHIFT                     _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_BSEA_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_BSEA_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_BSEA_RANGE                     30:30
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_BSEA_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_BSEA_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_BSEA_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_BSEA_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_BSEA_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Bond out VDE Controller
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_VDE_SHIFT                      _MK_SHIFT_CONST(29)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_VDE_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_VDE_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_VDE_RANGE                      29:29
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_VDE_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_VDE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_VDE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_VDE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_VDE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Bond out MPE controller.
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_MPE_SHIFT                      _MK_SHIFT_CONST(28)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_MPE_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_MPE_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_MPE_RANGE                      28:28
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_MPE_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_MPE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_MPE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_MPE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_MPE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Bond out USB3 controller.
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_USB3_SHIFT                     _MK_SHIFT_CONST(27)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_USB3_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_USB3_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_USB3_RANGE                     27:27
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_USB3_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_USB3_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_USB3_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_USB3_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_USB3_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Bond out USB2 controller.
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_USB2_SHIFT                     _MK_SHIFT_CONST(26)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_USB2_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_USB2_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_USB2_RANGE                     26:26
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_USB2_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_USB2_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_USB2_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_USB2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_USB2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Bond out EMC controller.
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_EMC_SHIFT                      _MK_SHIFT_CONST(25)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_EMC_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_EMC_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_EMC_RANGE                      25:25
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_EMC_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_EMC_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_EMC_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_EMC_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_EMC_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Bond out UART-C Controller
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_UARTC_SHIFT                    _MK_SHIFT_CONST(23)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_UARTC_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_UARTC_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_UARTC_RANGE                    23:23
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_UARTC_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_UARTC_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_UARTC_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_UARTC_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_UARTC_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Bond out I2C2 controller.
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_I2C2_SHIFT                     _MK_SHIFT_CONST(22)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_I2C2_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_I2C2_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_I2C2_RANGE                     22:22
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_I2C2_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_I2C2_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_I2C2_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_I2C2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_I2C2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Bond out TVDAC controller.
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_TVDAC_SHIFT                    _MK_SHIFT_CONST(21)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_TVDAC_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_TVDAC_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_TVDAC_RANGE                    21:21
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_TVDAC_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_TVDAC_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_TVDAC_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_TVDAC_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_TVDAC_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Bond out CSI controller
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_CSI_SHIFT                      _MK_SHIFT_CONST(20)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_CSI_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_CSI_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_CSI_RANGE                      20:20
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_CSI_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_CSI_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_CSI_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_CSI_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_CSI_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Bond out HDMI
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_HDMI_SHIFT                     _MK_SHIFT_CONST(19)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_HDMI_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_HDMI_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_HDMI_RANGE                     19:19
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_HDMI_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_HDMI_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_HDMI_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_HDMI_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_HDMI_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Bond out MIPI base-band controller
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_MIPI_SHIFT                     _MK_SHIFT_CONST(18)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_MIPI_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_MIPI_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_MIPI_RANGE                     18:18
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_MIPI_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_MIPI_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_MIPI_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_MIPI_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_MIPI_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Bond out TVO/CVE controller
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_TVO_SHIFT                      _MK_SHIFT_CONST(17)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_TVO_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_TVO_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_TVO_RANGE                      17:17
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_TVO_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_TVO_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_TVO_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_TVO_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_TVO_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Bond out DSI controller
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_DSI_SHIFT                      _MK_SHIFT_CONST(16)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_DSI_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_DSI_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_DSI_RANGE                      16:16
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_DSI_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_DSI_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_DSI_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_DSI_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_DSI_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Bond out DVC-I2C Controller
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_DVC_I2C_SHIFT                  _MK_SHIFT_CONST(15)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_DVC_I2C_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_DVC_I2C_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_DVC_I2C_RANGE                  15:15
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_DVC_I2C_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_DVC_I2C_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_DVC_I2C_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_DVC_I2C_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_DVC_I2C_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Bond out SBC 3 Controller.
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SBC3_SHIFT                     _MK_SHIFT_CONST(14)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SBC3_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SBC3_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SBC3_RANGE                     14:14
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SBC3_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SBC3_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SBC3_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SBC3_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SBC3_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Bond out XIO Controller.
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_XIO_SHIFT                      _MK_SHIFT_CONST(13)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_XIO_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_XIO_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_XIO_RANGE                      13:13
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_XIO_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_XIO_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_XIO_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_XIO_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_XIO_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Bond out SBC 2 Controller.
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SBC2_SHIFT                     _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SBC2_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SBC2_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SBC2_RANGE                     12:12
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SBC2_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SBC2_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SBC2_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SBC2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SBC2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Bond out SPI 1 Controller
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SPI1_SHIFT                     _MK_SHIFT_CONST(11)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SPI1_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SPI1_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SPI1_RANGE                     11:11
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SPI1_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SPI1_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SPI1_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SPI1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SPI1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Bond out NOR Flash Controller.
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_NOR_SHIFT                      _MK_SHIFT_CONST(10)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_NOR_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_NOR_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_NOR_RANGE                      10:10
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_NOR_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_NOR_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_NOR_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_NOR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_NOR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Bond out NOR Flash Controller.
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SNOR_SHIFT                     _MK_SHIFT_CONST(10)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SNOR_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SNOR_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SNOR_RANGE                     10:10
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SNOR_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SNOR_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SNOR_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SNOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SNOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Bond out SBC 1 Controller.
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SBC1_SHIFT                     _MK_SHIFT_CONST(9)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SBC1_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SBC1_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SBC1_RANGE                     9:9
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SBC1_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SBC1_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SBC1_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SBC1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SBC1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Bond out KFUSE controller.
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_KFUSE_SHIFT                    _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_KFUSE_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_KFUSE_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_KFUSE_RANGE                    8:8
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_KFUSE_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_KFUSE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_KFUSE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_KFUSE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_KFUSE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Bond out FUSE controller.
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_FUSE_SHIFT                     _MK_SHIFT_CONST(7)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_FUSE_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_FUSE_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_FUSE_RANGE                     7:7
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_FUSE_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_FUSE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_FUSE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_FUSE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_FUSE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Bond out PMC controller.
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_PMC_SHIFT                      _MK_SHIFT_CONST(6)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_PMC_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_PMC_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_PMC_RANGE                      6:6
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_PMC_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_PMC_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_PMC_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_PMC_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_PMC_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Bond out statistic monitor.
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_STAT_MON_SHIFT                 _MK_SHIFT_CONST(5)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_STAT_MON_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_STAT_MON_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_STAT_MON_RANGE                 5:5
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_STAT_MON_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_STAT_MON_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_STAT_MON_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_STAT_MON_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_STAT_MON_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Bond out keyboard controller.
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_KBC_SHIFT                      _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_KBC_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_KBC_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_KBC_RANGE                      4:4
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_KBC_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_KBC_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_KBC_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_KBC_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_KBC_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Bond out APB-DMA.
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_APBDMA_SHIFT                   _MK_SHIFT_CONST(2)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_APBDMA_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_APBDMA_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_APBDMA_RANGE                   2:2
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_APBDMA_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_APBDMA_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_APBDMA_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_APBDMA_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_APBDMA_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Bond out AHB-DMA.
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_AHBDMA_SHIFT                   _MK_SHIFT_CONST(1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_AHBDMA_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_AHBDMA_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_AHBDMA_RANGE                   1:1
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_AHBDMA_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_AHBDMA_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_AHBDMA_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_AHBDMA_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_AHBDMA_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Bond out MC/EMC.
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_MEM_SHIFT                      _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_MEM_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_MEM_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_MEM_RANGE                      0:0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_MEM_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_MEM_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_MEM_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_MEM_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_MEM_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_BOND_OUT_U_0  
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0                 _MK_ADDR_CONST(0x78)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_SECURE                  0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_WORD_COUNT                      0x1
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_RESET_MASK                      _MK_MASK_CONST(0x77f01bff)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_READ_MASK                       _MK_MASK_CONST(0x77f01bff)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_WRITE_MASK                      _MK_MASK_CONST(0x77f01bff)
+// Bond out DEV1_OUT.
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_DEV1_OUT_SHIFT                 _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_DEV1_OUT_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_DEV1_OUT_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_DEV1_OUT_RANGE                 30:30
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_DEV1_OUT_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_DEV1_OUT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_DEV1_OUT_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_DEV1_OUT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_DEV1_OUT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Bond out DEV2_OUT.
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_DEV2_OUT_SHIFT                 _MK_SHIFT_CONST(29)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_DEV2_OUT_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_DEV2_OUT_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_DEV2_OUT_RANGE                 29:29
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_DEV2_OUT_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_DEV2_OUT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_DEV2_OUT_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_DEV2_OUT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_DEV2_OUT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Bond out SUS_OUT.
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_SUS_OUT_SHIFT                  _MK_SHIFT_CONST(28)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_SUS_OUT_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_SUS_OUT_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_SUS_OUT_RANGE                  28:28
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_SUS_OUT_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_SUS_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_SUS_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_SUS_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_SUS_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Bond out CLK_M_DOUBLER.
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_CLK_M_DOUBLER_SHIFT                    _MK_SHIFT_CONST(26)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_CLK_M_DOUBLER_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_CLK_M_DOUBLER_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_CLK_M_DOUBLER_RANGE                    26:26
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_CLK_M_DOUBLER_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_CLK_M_DOUBLER_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_CLK_M_DOUBLER_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_CLK_M_DOUBLER_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_CLK_M_DOUBLER_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Bond out SYNC_CLK_DOUBLER.
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_SYNC_CLK_DOUBLER_SHIFT                 _MK_SHIFT_CONST(25)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_SYNC_CLK_DOUBLER_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_SYNC_CLK_DOUBLER_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_SYNC_CLK_DOUBLER_RANGE                 25:25
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_SYNC_CLK_DOUBLER_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_SYNC_CLK_DOUBLER_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_SYNC_CLK_DOUBLER_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_SYNC_CLK_DOUBLER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_SYNC_CLK_DOUBLER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Bond out CRAM2.
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_CRAM2_SHIFT                    _MK_SHIFT_CONST(24)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_CRAM2_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_CRAM2_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_CRAM2_RANGE                    24:24
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_CRAM2_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_CRAM2_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_CRAM2_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_CRAM2_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_CRAM2_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Bond out IRAMD.
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_IRAMD_SHIFT                    _MK_SHIFT_CONST(23)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_IRAMD_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_IRAMD_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_IRAMD_RANGE                    23:23
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_IRAMD_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_IRAMD_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_IRAMD_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_IRAMD_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_IRAMD_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Bond out IRAMC.
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_IRAMC_SHIFT                    _MK_SHIFT_CONST(22)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_IRAMC_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_IRAMC_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_IRAMC_RANGE                    22:22
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_IRAMC_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_IRAMC_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_IRAMC_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_IRAMC_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_IRAMC_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Bond out IRAMB.
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_IRAMB_SHIFT                    _MK_SHIFT_CONST(21)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_IRAMB_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_IRAMB_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_IRAMB_RANGE                    21:21
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_IRAMB_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_IRAMB_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_IRAMB_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_IRAMB_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_IRAMB_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Bond out IRAMA.
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_IRAMA_SHIFT                    _MK_SHIFT_CONST(20)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_IRAMA_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_IRAMA_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_IRAMA_RANGE                    20:20
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_IRAMA_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_IRAMA_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_IRAMA_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_IRAMA_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_IRAMA_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Bond out LA.
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_LA_SHIFT                       _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_LA_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_LA_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_LA_RANGE                       12:12
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_LA_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_LA_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_LA_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_LA_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_LA_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Bond out AVPUCQ.
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_AVPUCQ_SHIFT                   _MK_SHIFT_CONST(11)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_AVPUCQ_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_AVPUCQ_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_AVPUCQ_RANGE                   11:11
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_AVPUCQ_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_AVPUCQ_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_AVPUCQ_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_AVPUCQ_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_AVPUCQ_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Bond out CSITE.
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_CSITE_SHIFT                    _MK_SHIFT_CONST(9)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_CSITE_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_CSITE_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_CSITE_RANGE                    9:9
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_CSITE_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_CSITE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_CSITE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_CSITE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_CSITE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Bond out AFI.
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_AFI_SHIFT                      _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_AFI_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_AFI_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_AFI_RANGE                      8:8
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_AFI_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_AFI_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_AFI_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_AFI_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_AFI_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Bond out OWR.
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_OWR_SHIFT                      _MK_SHIFT_CONST(7)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_OWR_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_OWR_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_OWR_RANGE                      7:7
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_OWR_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_OWR_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_OWR_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_OWR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_OWR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Bond out PCIE.
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_PCIE_SHIFT                     _MK_SHIFT_CONST(6)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_PCIE_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_PCIE_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_PCIE_RANGE                     6:6
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_PCIE_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_PCIE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_PCIE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_PCIE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_PCIE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Bond out SDMMC3.
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_SDMMC3_SHIFT                   _MK_SHIFT_CONST(5)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_SDMMC3_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_SDMMC3_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_SDMMC3_RANGE                   5:5
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_SDMMC3_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_SDMMC3_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_SDMMC3_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_SDMMC3_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_SDMMC3_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Bond out SBC4.
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_SBC4_SHIFT                     _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_SBC4_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_SBC4_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_SBC4_RANGE                     4:4
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_SBC4_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_SBC4_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_SBC4_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_SBC4_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_SBC4_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Bond out I2C3.
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_I2C3_SHIFT                     _MK_SHIFT_CONST(3)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_I2C3_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_I2C3_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_I2C3_RANGE                     3:3
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_I2C3_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_I2C3_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_I2C3_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_I2C3_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_I2C3_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Bond out UARTE.
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_UARTE_SHIFT                    _MK_SHIFT_CONST(2)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_UARTE_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_UARTE_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_UARTE_RANGE                    2:2
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_UARTE_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_UARTE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_UARTE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_UARTE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_UARTE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Bond out UARTD.
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_UARTD_SHIFT                    _MK_SHIFT_CONST(1)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_UARTD_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_UARTD_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_UARTD_RANGE                    1:1
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_UARTD_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_UARTD_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_UARTD_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_UARTD_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_UARTD_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Bond out SPEEDO.
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_SPEEDO_SHIFT                   _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_SPEEDO_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_SPEEDO_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_SPEEDO_RANGE                   0:0
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_SPEEDO_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_SPEEDO_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_SPEEDO_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_SPEEDO_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_SPEEDO_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Reserved address 124 [0x7c] 
+
+// Register CLK_RST_CONTROLLER_PLLC_BASE_0  
+#define CLK_RST_CONTROLLER_PLLC_BASE_0                  _MK_ADDR_CONST(0x80)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_SECURE                   0x0
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_WORD_COUNT                       0x1
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_RESET_VAL                        _MK_MASK_CONST(0x10c)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_RESET_MASK                       _MK_MASK_CONST(0xe873ff1f)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_READ_MASK                        _MK_MASK_CONST(0xe873ff1f)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_WRITE_MASK                       _MK_MASK_CONST(0xe073ff1f)
+//  0 = no bypass, 1 = bypass.
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_BYPASS_SHIFT                        _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_BYPASS_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_BYPASS_SHIFT)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_BYPASS_RANGE                        31:31
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_BYPASS_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_BYPASS_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_BYPASS_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_BYPASS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_BYPASS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_BYPASS_INIT_ENUM                    DISABLE
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_BYPASS_DISABLE                      _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_BYPASS_ENABLE                       _MK_ENUM_CONST(1)
+
+//  0 = disable, 1 = enable.
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_ENABLE_SHIFT                        _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_ENABLE_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_ENABLE_SHIFT)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_ENABLE_RANGE                        30:30
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_ENABLE_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_ENABLE_INIT_ENUM                    DISABLE
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_ENABLE_DISABLE                      _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_ENABLE_ENABLE                       _MK_ENUM_CONST(1)
+
+//  0 = enable reference clk, 1 = disable reference clk.
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_REF_DIS_SHIFT                       _MK_SHIFT_CONST(29)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_REF_DIS_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_REF_DIS_SHIFT)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_REF_DIS_RANGE                       29:29
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_REF_DIS_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_REF_DIS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_REF_DIS_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_REF_DIS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_REF_DIS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_REF_DIS_INIT_ENUM                   REF_ENABLE
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_REF_DIS_REF_ENABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_REF_DIS_REF_DISABLE                 _MK_ENUM_CONST(1)
+
+//  0 = not lock, 1 = lock.
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_LOCK_SHIFT                  _MK_SHIFT_CONST(27)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_LOCK_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_LOCK_SHIFT)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_LOCK_RANGE                  27:27
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_LOCK_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_LOCK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_LOCK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_LOCK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_LOCK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  0 = post divider (2^n).
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVP_SHIFT                  _MK_SHIFT_CONST(20)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVP_FIELD                  (_MK_MASK_CONST(0x7) << CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVP_SHIFT)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVP_RANGE                  22:20
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVP_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVP_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVP_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  PLL feedback divider.
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVN_SHIFT                  _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVN_FIELD                  (_MK_MASK_CONST(0x3ff) << CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVN_SHIFT)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVN_RANGE                  17:8
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVN_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVN_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVN_DEFAULT_MASK                   _MK_MASK_CONST(0x3ff)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  PLL input divider.
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVM_SHIFT                  _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVM_FIELD                  (_MK_MASK_CONST(0x1f) << CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVM_SHIFT)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVM_RANGE                  4:0
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVM_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVM_DEFAULT                        _MK_MASK_CONST(0xc)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVM_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_PLLC_OUT_0  
+#define CLK_RST_CONTROLLER_PLLC_OUT_0                   _MK_ADDR_CONST(0x84)
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_SECURE                    0x0
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_WORD_COUNT                        0x1
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_RESET_VAL                         _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_RESET_MASK                        _MK_MASK_CONST(0xff03)
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_READ_MASK                         _MK_MASK_CONST(0xff03)
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_WRITE_MASK                        _MK_MASK_CONST(0xff03)
+//  PLLC_OUT1 divider from base PLLC (lsb denote 0.5x).
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_RATIO_SHIFT                     _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_RATIO_FIELD                     (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_RATIO_SHIFT)
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_RATIO_RANGE                     15:8
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_RATIO_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_RATIO_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_RATIO_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_RATIO_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_RATIO_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+//  PLLC_OUT1 divider clk enable.  0 = disable, 1 = enable.
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_CLKEN_SHIFT                     _MK_SHIFT_CONST(1)
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_CLKEN_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_CLKEN_SHIFT)
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_CLKEN_RANGE                     1:1
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_CLKEN_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_CLKEN_DEFAULT                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_CLKEN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_CLKEN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_CLKEN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_CLKEN_INIT_ENUM                 ENABLE
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_CLKEN_DISABLE                   _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_CLKEN_ENABLE                    _MK_ENUM_CONST(1)
+
+//  PLLC_OUT1 divider reset.  0 = reset, 1 = not reset.
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_RSTN_SHIFT                      _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_RSTN_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_RSTN_SHIFT)
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_RSTN_RANGE                      0:0
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_RSTN_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_RSTN_DEFAULT                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_RSTN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_RSTN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_RSTN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_RSTN_INIT_ENUM                  RESET_DISABLE
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_RSTN_RESET_ENABLE                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_RSTN_RESET_DISABLE                      _MK_ENUM_CONST(1)
+
+
+// Reserved address 136 [0x88] 
+
+// Register CLK_RST_CONTROLLER_PLLC_MISC_0  
+#define CLK_RST_CONTROLLER_PLLC_MISC_0                  _MK_ADDR_CONST(0x8c)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_SECURE                   0x0
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_WORD_COUNT                       0x1
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_RESET_VAL                        _MK_MASK_CONST(0x100)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_RESET_MASK                       _MK_MASK_CONST(0xc0d7ffff)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_READ_MASK                        _MK_MASK_CONST(0xc0d7ffff)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_WRITE_MASK                       _MK_MASK_CONST(0xc0d7ffff)
+//  1 = invert PLLC_OUT1 clock.
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_OUT1_INV_CLK_SHIFT                  _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_OUT1_INV_CLK_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_OUT1_INV_CLK_SHIFT)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_OUT1_INV_CLK_RANGE                  31:31
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_OUT1_INV_CLK_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_OUT1_INV_CLK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_OUT1_INV_CLK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_OUT1_INV_CLK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_OUT1_INV_CLK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  1 = bypass PLLC_OUT1 divider.
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_OUT1_DIV_BYP_SHIFT                  _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_OUT1_DIV_BYP_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_OUT1_DIV_BYP_SHIFT)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_OUT1_DIV_BYP_RANGE                  30:30
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_OUT1_DIV_BYP_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_OUT1_DIV_BYP_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_OUT1_DIV_BYP_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_OUT1_DIV_BYP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_OUT1_DIV_BYP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  Base PLLC test output select.
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_PTS_SHIFT                   _MK_SHIFT_CONST(22)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_PTS_FIELD                   (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_PTS_SHIFT)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_PTS_RANGE                   23:22
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_PTS_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_PTS_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_PTS_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_PTS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_PTS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+//  Base PLLC DCCON control.
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_DCCON_SHIFT                 _MK_SHIFT_CONST(20)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_DCCON_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_DCCON_SHIFT)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_DCCON_RANGE                 20:20
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_DCCON_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_DCCON_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_DCCON_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_DCCON_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_DCCON_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//  1 = enable, 0 = disable. 
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_LOCK_ENABLE_SHIFT                   _MK_SHIFT_CONST(18)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_LOCK_ENABLE_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_LOCK_ENABLE_SHIFT)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_LOCK_ENABLE_RANGE                   18:18
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_LOCK_ENABLE_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_LOCK_ENABLE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_LOCK_ENABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_LOCK_ENABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_LOCK_ENABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_LOCK_ENABLE_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_LOCK_ENABLE_ENABLE                  _MK_ENUM_CONST(1)
+
+//  lock select.
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_LOCK_SEL_SHIFT                      _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_LOCK_SEL_FIELD                      (_MK_MASK_CONST(0x3f) << CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_LOCK_SEL_SHIFT)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_LOCK_SEL_RANGE                      17:12
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_LOCK_SEL_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_LOCK_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_LOCK_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3f)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_LOCK_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_LOCK_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+//  Base PLLC charge pump setup control.
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_CPCON_SHIFT                 _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_CPCON_FIELD                 (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_CPCON_SHIFT)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_CPCON_RANGE                 11:8
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_CPCON_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_CPCON_DEFAULT                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_CPCON_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_CPCON_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_CPCON_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//  Base PLLC loop filter setup control.
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_LFCON_SHIFT                 _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_LFCON_FIELD                 (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_LFCON_SHIFT)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_LFCON_RANGE                 7:4
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_LFCON_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_LFCON_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_LFCON_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_LFCON_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_LFCON_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//  Base PLLC VCO range setup control.
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_VCOCON_SHIFT                        _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_VCOCON_FIELD                        (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_VCOCON_SHIFT)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_VCOCON_RANGE                        3:0
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_VCOCON_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_VCOCON_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_VCOCON_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_VCOCON_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_VCOCON_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_PLLM_BASE_0  
+#define CLK_RST_CONTROLLER_PLLM_BASE_0                  _MK_ADDR_CONST(0x90)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_SECURE                   0x0
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_WORD_COUNT                       0x1
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_RESET_VAL                        _MK_MASK_CONST(0x10c)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_RESET_MASK                       _MK_MASK_CONST(0xe873ff1f)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_READ_MASK                        _MK_MASK_CONST(0xe873ff1f)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_WRITE_MASK                       _MK_MASK_CONST(0xe073ff1f)
+//  0 = no bypass, 1 = bypass.
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_BYPASS_SHIFT                        _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_BYPASS_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_BYPASS_SHIFT)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_BYPASS_RANGE                        31:31
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_BYPASS_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_BYPASS_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_BYPASS_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_BYPASS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_BYPASS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_BYPASS_INIT_ENUM                    DISABLE
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_BYPASS_DISABLE                      _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_BYPASS_ENABLE                       _MK_ENUM_CONST(1)
+
+//  0 = disable, 1 = enable.
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_ENABLE_SHIFT                        _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_ENABLE_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_ENABLE_SHIFT)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_ENABLE_RANGE                        30:30
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_ENABLE_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_ENABLE_INIT_ENUM                    DISABLE
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_ENABLE_DISABLE                      _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_ENABLE_ENABLE                       _MK_ENUM_CONST(1)
+
+//  0 = enable reference clk, 1 = disable reference clk.
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_REF_DIS_SHIFT                       _MK_SHIFT_CONST(29)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_REF_DIS_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_REF_DIS_SHIFT)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_REF_DIS_RANGE                       29:29
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_REF_DIS_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_REF_DIS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_REF_DIS_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_REF_DIS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_REF_DIS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_REF_DIS_INIT_ENUM                   REF_ENABLE
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_REF_DIS_REF_ENABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_REF_DIS_REF_DISABLE                 _MK_ENUM_CONST(1)
+
+//  0 = not lock, 1 = lock.
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_LOCK_SHIFT                  _MK_SHIFT_CONST(27)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_LOCK_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_LOCK_SHIFT)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_LOCK_RANGE                  27:27
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_LOCK_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_LOCK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_LOCK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_LOCK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_LOCK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  0 = post divider (2^n).
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVP_SHIFT                  _MK_SHIFT_CONST(20)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVP_FIELD                  (_MK_MASK_CONST(0x7) << CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVP_SHIFT)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVP_RANGE                  22:20
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVP_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVP_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVP_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  PLL feedback divider.
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVN_SHIFT                  _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVN_FIELD                  (_MK_MASK_CONST(0x3ff) << CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVN_SHIFT)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVN_RANGE                  17:8
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVN_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVN_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVN_DEFAULT_MASK                   _MK_MASK_CONST(0x3ff)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  PLL input divider.
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVM_SHIFT                  _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVM_FIELD                  (_MK_MASK_CONST(0x1f) << CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVM_SHIFT)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVM_RANGE                  4:0
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVM_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVM_DEFAULT                        _MK_MASK_CONST(0xc)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVM_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_PLLM_OUT_0  
+#define CLK_RST_CONTROLLER_PLLM_OUT_0                   _MK_ADDR_CONST(0x94)
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_SECURE                    0x0
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_WORD_COUNT                        0x1
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_RESET_VAL                         _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_RESET_MASK                        _MK_MASK_CONST(0xff03)
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_READ_MASK                         _MK_MASK_CONST(0xff03)
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_WRITE_MASK                        _MK_MASK_CONST(0xff03)
+//  PLLM_OUT1 divider from base PLLM (lsb denote 0.5x).
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_RATIO_SHIFT                     _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_RATIO_FIELD                     (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_RATIO_SHIFT)
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_RATIO_RANGE                     15:8
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_RATIO_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_RATIO_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_RATIO_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_RATIO_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_RATIO_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+//  PLLM_OUT1 divider clk enable.  0 = disable, 1 = enable.
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_CLKEN_SHIFT                     _MK_SHIFT_CONST(1)
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_CLKEN_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_CLKEN_SHIFT)
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_CLKEN_RANGE                     1:1
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_CLKEN_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_CLKEN_DEFAULT                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_CLKEN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_CLKEN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_CLKEN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_CLKEN_INIT_ENUM                 ENABLE
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_CLKEN_DISABLE                   _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_CLKEN_ENABLE                    _MK_ENUM_CONST(1)
+
+//  PLLM_OUT1 divider reset.  0 = reset, 1 = not reset.
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_RSTN_SHIFT                      _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_RSTN_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_RSTN_SHIFT)
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_RSTN_RANGE                      0:0
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_RSTN_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_RSTN_DEFAULT                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_RSTN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_RSTN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_RSTN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_RSTN_INIT_ENUM                  RESET_DISABLE
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_RSTN_RESET_ENABLE                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_RSTN_RESET_DISABLE                      _MK_ENUM_CONST(1)
+
+
+// Reserved address 152 [0x98] 
+
+// Register CLK_RST_CONTROLLER_PLLM_MISC_0  
+#define CLK_RST_CONTROLLER_PLLM_MISC_0                  _MK_ADDR_CONST(0x9c)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_SECURE                   0x0
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_WORD_COUNT                       0x1
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_RESET_VAL                        _MK_MASK_CONST(0x100)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_RESET_MASK                       _MK_MASK_CONST(0xcfd7ffff)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_READ_MASK                        _MK_MASK_CONST(0xcfd7ffff)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_WRITE_MASK                       _MK_MASK_CONST(0xcfd7ffff)
+//  1 = invert PLLM_OUT1 clock.
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_OUT1_INV_CLK_SHIFT                  _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_OUT1_INV_CLK_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_OUT1_INV_CLK_SHIFT)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_OUT1_INV_CLK_RANGE                  31:31
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_OUT1_INV_CLK_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_OUT1_INV_CLK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_OUT1_INV_CLK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_OUT1_INV_CLK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_OUT1_INV_CLK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  1 = bypass PLLM_OUT1 divider.
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_OUT1_DIV_BYP_SHIFT                  _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_OUT1_DIV_BYP_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_OUT1_DIV_BYP_SHIFT)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_OUT1_DIV_BYP_RANGE                  30:30
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_OUT1_DIV_BYP_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_OUT1_DIV_BYP_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_OUT1_DIV_BYP_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_OUT1_DIV_BYP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_OUT1_DIV_BYP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  Base PLLM setup.
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_SETUP_SHIFT                 _MK_SHIFT_CONST(24)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_SETUP_FIELD                 (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_SETUP_SHIFT)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_SETUP_RANGE                 27:24
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_SETUP_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_SETUP_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_SETUP_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_SETUP_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_SETUP_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//  Base PLLM test output select.
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_PTS_SHIFT                   _MK_SHIFT_CONST(22)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_PTS_FIELD                   (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_PTS_SHIFT)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_PTS_RANGE                   23:22
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_PTS_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_PTS_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_PTS_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_PTS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_PTS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+//  Base PLLM DCCON control.
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_DCCON_SHIFT                 _MK_SHIFT_CONST(20)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_DCCON_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_DCCON_SHIFT)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_DCCON_RANGE                 20:20
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_DCCON_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_DCCON_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_DCCON_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_DCCON_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_DCCON_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//  1 = enable, 0 = disable. 
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_LOCK_ENABLE_SHIFT                   _MK_SHIFT_CONST(18)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_LOCK_ENABLE_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_LOCK_ENABLE_SHIFT)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_LOCK_ENABLE_RANGE                   18:18
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_LOCK_ENABLE_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_LOCK_ENABLE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_LOCK_ENABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_LOCK_ENABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_LOCK_ENABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_LOCK_ENABLE_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_LOCK_ENABLE_ENABLE                  _MK_ENUM_CONST(1)
+
+//  lock select.
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_LOCK_SEL_SHIFT                      _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_LOCK_SEL_FIELD                      (_MK_MASK_CONST(0x3f) << CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_LOCK_SEL_SHIFT)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_LOCK_SEL_RANGE                      17:12
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_LOCK_SEL_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_LOCK_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_LOCK_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3f)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_LOCK_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_LOCK_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+//  Base PLLM charge pump setup control.
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_CPCON_SHIFT                 _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_CPCON_FIELD                 (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_CPCON_SHIFT)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_CPCON_RANGE                 11:8
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_CPCON_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_CPCON_DEFAULT                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_CPCON_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_CPCON_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_CPCON_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//  Base PLLM loop filter setup control.
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_LFCON_SHIFT                 _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_LFCON_FIELD                 (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_LFCON_SHIFT)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_LFCON_RANGE                 7:4
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_LFCON_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_LFCON_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_LFCON_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_LFCON_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_LFCON_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//  Base PLLM VCO range setup control.
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_VCOCON_SHIFT                        _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_VCOCON_FIELD                        (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_VCOCON_SHIFT)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_VCOCON_RANGE                        3:0
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_VCOCON_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_VCOCON_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_VCOCON_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_VCOCON_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_VCOCON_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_PLLP_BASE_0  
+#define CLK_RST_CONTROLLER_PLLP_BASE_0                  _MK_ADDR_CONST(0xa0)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_SECURE                   0x0
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_WORD_COUNT                       0x1
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_RESET_VAL                        _MK_MASK_CONST(0x10c)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_RESET_MASK                       _MK_MASK_CONST(0xf873ff1f)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_READ_MASK                        _MK_MASK_CONST(0xf873ff1f)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_WRITE_MASK                       _MK_MASK_CONST(0xf073ff1f)
+//  0 = no bypass, 1 = bypass.
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BYPASS_SHIFT                        _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BYPASS_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BYPASS_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BYPASS_RANGE                        31:31
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BYPASS_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BYPASS_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BYPASS_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BYPASS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BYPASS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BYPASS_INIT_ENUM                    DISABLE
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BYPASS_DISABLE                      _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BYPASS_ENABLE                       _MK_ENUM_CONST(1)
+
+//  0 = disable, 1 = enable.
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_ENABLE_SHIFT                        _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_ENABLE_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_ENABLE_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_ENABLE_RANGE                        30:30
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_ENABLE_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_ENABLE_INIT_ENUM                    DISABLE
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_ENABLE_DISABLE                      _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_ENABLE_ENABLE                       _MK_ENUM_CONST(1)
+
+//  0 = enable reference clk, 1 = disable reference clk.
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_REF_DIS_SHIFT                       _MK_SHIFT_CONST(29)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_REF_DIS_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_REF_DIS_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_REF_DIS_RANGE                       29:29
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_REF_DIS_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_REF_DIS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_REF_DIS_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_REF_DIS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_REF_DIS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_REF_DIS_INIT_ENUM                   REF_ENABLE
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_REF_DIS_REF_ENABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_REF_DIS_REF_DISABLE                 _MK_ENUM_CONST(1)
+
+//  0 = disallow base override , 1 = allow base override.
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BASE_OVRRIDE_SHIFT                  _MK_SHIFT_CONST(28)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BASE_OVRRIDE_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BASE_OVRRIDE_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BASE_OVRRIDE_RANGE                  28:28
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BASE_OVRRIDE_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BASE_OVRRIDE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BASE_OVRRIDE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BASE_OVRRIDE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BASE_OVRRIDE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BASE_OVRRIDE_INIT_ENUM                      DISABLE
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BASE_OVRRIDE_DISABLE                        _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BASE_OVRRIDE_ENABLE                 _MK_ENUM_CONST(1)
+
+//  0 = not lock, 1 = lock.
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_LOCK_SHIFT                  _MK_SHIFT_CONST(27)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_LOCK_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_LOCK_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_LOCK_RANGE                  27:27
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_LOCK_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_LOCK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_LOCK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_LOCK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_LOCK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  0 = post divider (2^n).
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVP_SHIFT                  _MK_SHIFT_CONST(20)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVP_FIELD                  (_MK_MASK_CONST(0x7) << CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVP_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVP_RANGE                  22:20
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVP_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVP_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVP_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  PLL feedback divider.
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVN_SHIFT                  _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVN_FIELD                  (_MK_MASK_CONST(0x3ff) << CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVN_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVN_RANGE                  17:8
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVN_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVN_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVN_DEFAULT_MASK                   _MK_MASK_CONST(0x3ff)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  PLL input divider.
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVM_SHIFT                  _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVM_FIELD                  (_MK_MASK_CONST(0x1f) << CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVM_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVM_RANGE                  4:0
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVM_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVM_DEFAULT                        _MK_MASK_CONST(0xc)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVM_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_PLLP_OUTA_0  
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0                  _MK_ADDR_CONST(0xa4)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_SECURE                   0x0
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_WORD_COUNT                       0x1
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_RESET_VAL                        _MK_MASK_CONST(0x30003)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_RESET_MASK                       _MK_MASK_CONST(0xff07ff07)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_READ_MASK                        _MK_MASK_CONST(0xff07ff07)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_WRITE_MASK                       _MK_MASK_CONST(0xff07ff07)
+//  PLLP_OUT2 divider from base PLLP (lsb denote 0.5x).
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_RATIO_SHIFT                    _MK_SHIFT_CONST(24)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_RATIO_FIELD                    (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_RATIO_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_RATIO_RANGE                    31:24
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_RATIO_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_RATIO_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_RATIO_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_RATIO_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_RATIO_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+//  0 = disallow PLLP_OUT2 ratio override, 1 = enable override.
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_OVRRIDE_SHIFT                  _MK_SHIFT_CONST(18)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_OVRRIDE_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_OVRRIDE_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_OVRRIDE_RANGE                  18:18
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_OVRRIDE_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_OVRRIDE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_OVRRIDE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_OVRRIDE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_OVRRIDE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_OVRRIDE_INIT_ENUM                      DISABLE
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_OVRRIDE_DISABLE                        _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_OVRRIDE_ENABLE                 _MK_ENUM_CONST(1)
+
+//  PLLP_OUT2 divider clk enable.  0 = disable, 1 = enable.
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_CLKEN_SHIFT                    _MK_SHIFT_CONST(17)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_CLKEN_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_CLKEN_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_CLKEN_RANGE                    17:17
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_CLKEN_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_CLKEN_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_CLKEN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_CLKEN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_CLKEN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_CLKEN_INIT_ENUM                        ENABLE
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_CLKEN_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_CLKEN_ENABLE                   _MK_ENUM_CONST(1)
+
+//  PLLP_OUT2 divider reset.  0 = reset, 1 = not reset.
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_RSTN_SHIFT                     _MK_SHIFT_CONST(16)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_RSTN_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_RSTN_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_RSTN_RANGE                     16:16
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_RSTN_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_RSTN_DEFAULT                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_RSTN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_RSTN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_RSTN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_RSTN_INIT_ENUM                 RESET_DISABLE
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_RSTN_RESET_ENABLE                      _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_RSTN_RESET_DISABLE                     _MK_ENUM_CONST(1)
+
+//  PLLP_OUT1 divider from base PLLP (lsb denote 0.5x).
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_RATIO_SHIFT                    _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_RATIO_FIELD                    (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_RATIO_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_RATIO_RANGE                    15:8
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_RATIO_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_RATIO_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_RATIO_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_RATIO_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_RATIO_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+//  0 = disallow PLLP_OUT1 ratio override, 1 = enable override.
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_OVRRIDE_SHIFT                  _MK_SHIFT_CONST(2)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_OVRRIDE_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_OVRRIDE_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_OVRRIDE_RANGE                  2:2
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_OVRRIDE_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_OVRRIDE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_OVRRIDE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_OVRRIDE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_OVRRIDE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_OVRRIDE_INIT_ENUM                      DISABLE
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_OVRRIDE_DISABLE                        _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_OVRRIDE_ENABLE                 _MK_ENUM_CONST(1)
+
+//  PLLP_OUT1 divider clk enable.  0 = disable, 1 = enable.
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_CLKEN_SHIFT                    _MK_SHIFT_CONST(1)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_CLKEN_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_CLKEN_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_CLKEN_RANGE                    1:1
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_CLKEN_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_CLKEN_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_CLKEN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_CLKEN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_CLKEN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_CLKEN_INIT_ENUM                        ENABLE
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_CLKEN_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_CLKEN_ENABLE                   _MK_ENUM_CONST(1)
+
+//  PLLP_OUT1 divider reset.  0 = reset, 1 = not reset.
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_RSTN_SHIFT                     _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_RSTN_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_RSTN_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_RSTN_RANGE                     0:0
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_RSTN_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_RSTN_DEFAULT                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_RSTN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_RSTN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_RSTN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_RSTN_INIT_ENUM                 RESET_DISABLE
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_RSTN_RESET_ENABLE                      _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_RSTN_RESET_DISABLE                     _MK_ENUM_CONST(1)
+
+
+// Register CLK_RST_CONTROLLER_PLLP_OUTB_0  
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0                  _MK_ADDR_CONST(0xa8)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_SECURE                   0x0
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_WORD_COUNT                       0x1
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_RESET_VAL                        _MK_MASK_CONST(0x30003)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_RESET_MASK                       _MK_MASK_CONST(0xff07ff07)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_READ_MASK                        _MK_MASK_CONST(0xff07ff07)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_WRITE_MASK                       _MK_MASK_CONST(0xff07ff07)
+//  PLLP_OUT4 divider from base PLLP (lsb denote 0.5x).
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_RATIO_SHIFT                    _MK_SHIFT_CONST(24)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_RATIO_FIELD                    (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_RATIO_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_RATIO_RANGE                    31:24
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_RATIO_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_RATIO_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_RATIO_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_RATIO_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_RATIO_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+//  0 = disallow PLLP_OUT4 ratio override, 1 = enable override.
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_OVRRIDE_SHIFT                  _MK_SHIFT_CONST(18)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_OVRRIDE_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_OVRRIDE_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_OVRRIDE_RANGE                  18:18
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_OVRRIDE_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_OVRRIDE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_OVRRIDE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_OVRRIDE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_OVRRIDE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_OVRRIDE_INIT_ENUM                      DISABLE
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_OVRRIDE_DISABLE                        _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_OVRRIDE_ENABLE                 _MK_ENUM_CONST(1)
+
+//  PLLP_OUT4 divider clk enable.  0 = disable, 1 = enable.
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_CLKEN_SHIFT                    _MK_SHIFT_CONST(17)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_CLKEN_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_CLKEN_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_CLKEN_RANGE                    17:17
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_CLKEN_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_CLKEN_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_CLKEN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_CLKEN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_CLKEN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_CLKEN_INIT_ENUM                        ENABLE
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_CLKEN_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_CLKEN_ENABLE                   _MK_ENUM_CONST(1)
+
+//  PLLP_OUT4 divider reset.  0 = reset, 1 = not reset.
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_RSTN_SHIFT                     _MK_SHIFT_CONST(16)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_RSTN_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_RSTN_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_RSTN_RANGE                     16:16
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_RSTN_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_RSTN_DEFAULT                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_RSTN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_RSTN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_RSTN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_RSTN_INIT_ENUM                 RESET_DISABLE
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_RSTN_RESET_ENABLE                      _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_RSTN_RESET_DISABLE                     _MK_ENUM_CONST(1)
+
+//  PLLP_OUT3 divider from base PLLP (lsb denote 0.5x).
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_RATIO_SHIFT                    _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_RATIO_FIELD                    (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_RATIO_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_RATIO_RANGE                    15:8
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_RATIO_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_RATIO_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_RATIO_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_RATIO_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_RATIO_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+//  0 = disallow PLLP_OUT3 ratio override, 1 = enable override.
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_OVRRIDE_SHIFT                  _MK_SHIFT_CONST(2)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_OVRRIDE_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_OVRRIDE_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_OVRRIDE_RANGE                  2:2
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_OVRRIDE_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_OVRRIDE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_OVRRIDE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_OVRRIDE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_OVRRIDE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_OVRRIDE_INIT_ENUM                      DISABLE
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_OVRRIDE_DISABLE                        _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_OVRRIDE_ENABLE                 _MK_ENUM_CONST(1)
+
+//  PLLP_OUT3 divider clk enable.  0 = disable, 1 = enable.
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_CLKEN_SHIFT                    _MK_SHIFT_CONST(1)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_CLKEN_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_CLKEN_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_CLKEN_RANGE                    1:1
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_CLKEN_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_CLKEN_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_CLKEN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_CLKEN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_CLKEN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_CLKEN_INIT_ENUM                        ENABLE
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_CLKEN_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_CLKEN_ENABLE                   _MK_ENUM_CONST(1)
+
+//  PLLP_OUT3 divider reset.  0 = reset, 1 = not reset.
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_RSTN_SHIFT                     _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_RSTN_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_RSTN_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_RSTN_RANGE                     0:0
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_RSTN_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_RSTN_DEFAULT                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_RSTN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_RSTN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_RSTN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_RSTN_INIT_ENUM                 RESET_DISABLE
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_RSTN_RESET_ENABLE                      _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_RSTN_RESET_DISABLE                     _MK_ENUM_CONST(1)
+
+
+// Register CLK_RST_CONTROLLER_PLLP_MISC_0  
+#define CLK_RST_CONTROLLER_PLLP_MISC_0                  _MK_ADDR_CONST(0xac)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_SECURE                   0x0
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_WORD_COUNT                       0x1
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_RESET_VAL                        _MK_MASK_CONST(0x100)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_RESET_MASK                       _MK_MASK_CONST(0xffd7ffff)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_READ_MASK                        _MK_MASK_CONST(0xffd7ffff)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_WRITE_MASK                       _MK_MASK_CONST(0xffd7ffff)
+//  1 = invert PLLP_OUT4 clock.
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT4_INV_CLK_SHIFT                  _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT4_INV_CLK_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT4_INV_CLK_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT4_INV_CLK_RANGE                  31:31
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT4_INV_CLK_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT4_INV_CLK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT4_INV_CLK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT4_INV_CLK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT4_INV_CLK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  1 = invert PLLP_OUT3 clock.
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT3_INV_CLK_SHIFT                  _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT3_INV_CLK_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT3_INV_CLK_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT3_INV_CLK_RANGE                  30:30
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT3_INV_CLK_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT3_INV_CLK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT3_INV_CLK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT3_INV_CLK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT3_INV_CLK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  1 = invert PLLP_OUT2 clock.
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT2_INV_CLK_SHIFT                  _MK_SHIFT_CONST(29)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT2_INV_CLK_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT2_INV_CLK_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT2_INV_CLK_RANGE                  29:29
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT2_INV_CLK_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT2_INV_CLK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT2_INV_CLK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT2_INV_CLK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT2_INV_CLK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  1 = invert PLLP_OUT1 clock.
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT1_INV_CLK_SHIFT                  _MK_SHIFT_CONST(28)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT1_INV_CLK_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT1_INV_CLK_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT1_INV_CLK_RANGE                  28:28
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT1_INV_CLK_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT1_INV_CLK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT1_INV_CLK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT1_INV_CLK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT1_INV_CLK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  1 = bypass PLLP_OUT4 divider.
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT4_DIV_BYP_SHIFT                  _MK_SHIFT_CONST(27)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT4_DIV_BYP_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT4_DIV_BYP_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT4_DIV_BYP_RANGE                  27:27
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT4_DIV_BYP_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT4_DIV_BYP_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT4_DIV_BYP_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT4_DIV_BYP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT4_DIV_BYP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  1 = bypass PLLP_OUT3 divider.
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT3_DIV_BYP_SHIFT                  _MK_SHIFT_CONST(26)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT3_DIV_BYP_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT3_DIV_BYP_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT3_DIV_BYP_RANGE                  26:26
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT3_DIV_BYP_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT3_DIV_BYP_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT3_DIV_BYP_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT3_DIV_BYP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT3_DIV_BYP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  1 = bypass PLLP_OUT2 divider.
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT2_DIV_BYP_SHIFT                  _MK_SHIFT_CONST(25)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT2_DIV_BYP_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT2_DIV_BYP_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT2_DIV_BYP_RANGE                  25:25
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT2_DIV_BYP_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT2_DIV_BYP_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT2_DIV_BYP_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT2_DIV_BYP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT2_DIV_BYP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  1 = bypass PLLP_OUT1 divider.
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT1_DIV_BYP_SHIFT                  _MK_SHIFT_CONST(24)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT1_DIV_BYP_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT1_DIV_BYP_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT1_DIV_BYP_RANGE                  24:24
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT1_DIV_BYP_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT1_DIV_BYP_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT1_DIV_BYP_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT1_DIV_BYP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT1_DIV_BYP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  Base PLLP test output select.
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_PTS_SHIFT                   _MK_SHIFT_CONST(22)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_PTS_FIELD                   (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_PTS_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_PTS_RANGE                   23:22
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_PTS_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_PTS_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_PTS_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_PTS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_PTS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+//  Base PLLP DCCON control.
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_DCCON_SHIFT                 _MK_SHIFT_CONST(20)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_DCCON_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_DCCON_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_DCCON_RANGE                 20:20
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_DCCON_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_DCCON_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_DCCON_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_DCCON_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_DCCON_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//  1 = enable, 0 = disable. 
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LOCK_ENABLE_SHIFT                   _MK_SHIFT_CONST(18)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LOCK_ENABLE_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LOCK_ENABLE_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LOCK_ENABLE_RANGE                   18:18
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LOCK_ENABLE_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LOCK_ENABLE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LOCK_ENABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LOCK_ENABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LOCK_ENABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LOCK_ENABLE_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LOCK_ENABLE_ENABLE                  _MK_ENUM_CONST(1)
+
+//  lock select.
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LOCK_SEL_SHIFT                      _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LOCK_SEL_FIELD                      (_MK_MASK_CONST(0x3f) << CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LOCK_SEL_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LOCK_SEL_RANGE                      17:12
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LOCK_SEL_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LOCK_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LOCK_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3f)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LOCK_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LOCK_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+//  Base PLLP charge pump setup control.
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_CPCON_SHIFT                 _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_CPCON_FIELD                 (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_CPCON_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_CPCON_RANGE                 11:8
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_CPCON_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_CPCON_DEFAULT                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_CPCON_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_CPCON_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_CPCON_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//  Base PLLP loop filter setup control.
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LFCON_SHIFT                 _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LFCON_FIELD                 (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LFCON_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LFCON_RANGE                 7:4
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LFCON_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LFCON_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LFCON_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LFCON_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LFCON_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//  Base PLLP VCO range setup control.
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_VCOCON_SHIFT                        _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_VCOCON_FIELD                        (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_VCOCON_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_VCOCON_RANGE                        3:0
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_VCOCON_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_VCOCON_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_VCOCON_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_VCOCON_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_VCOCON_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_PLLA_BASE_0  
+#define CLK_RST_CONTROLLER_PLLA_BASE_0                  _MK_ADDR_CONST(0xb0)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_SECURE                   0x0
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_WORD_COUNT                       0x1
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_RESET_VAL                        _MK_MASK_CONST(0x10c)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_RESET_MASK                       _MK_MASK_CONST(0xe873ff1f)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_READ_MASK                        _MK_MASK_CONST(0xe873ff1f)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_WRITE_MASK                       _MK_MASK_CONST(0xe073ff1f)
+//  0 = no bypass, 1 = bypass.
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_BYPASS_SHIFT                        _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_BYPASS_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_BYPASS_SHIFT)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_BYPASS_RANGE                        31:31
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_BYPASS_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_BYPASS_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_BYPASS_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_BYPASS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_BYPASS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_BYPASS_INIT_ENUM                    DISABLE
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_BYPASS_DISABLE                      _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_BYPASS_ENABLE                       _MK_ENUM_CONST(1)
+
+//  0 = disable, 1 = enable.
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_ENABLE_SHIFT                        _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_ENABLE_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_ENABLE_SHIFT)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_ENABLE_RANGE                        30:30
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_ENABLE_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_ENABLE_INIT_ENUM                    DISABLE
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_ENABLE_DISABLE                      _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_ENABLE_ENABLE                       _MK_ENUM_CONST(1)
+
+//  0 = enable reference clk, 1 = disable reference clk.
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_REF_DIS_SHIFT                       _MK_SHIFT_CONST(29)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_REF_DIS_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_REF_DIS_SHIFT)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_REF_DIS_RANGE                       29:29
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_REF_DIS_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_REF_DIS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_REF_DIS_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_REF_DIS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_REF_DIS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_REF_DIS_INIT_ENUM                   REF_ENABLE
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_REF_DIS_REF_ENABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_REF_DIS_REF_DISABLE                 _MK_ENUM_CONST(1)
+
+//  0 = not lock, 1 = lock.
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_LOCK_SHIFT                  _MK_SHIFT_CONST(27)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_LOCK_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_LOCK_SHIFT)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_LOCK_RANGE                  27:27
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_LOCK_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_LOCK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_LOCK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_LOCK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_LOCK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  0 = post divider (2^n).
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVP_SHIFT                  _MK_SHIFT_CONST(20)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVP_FIELD                  (_MK_MASK_CONST(0x7) << CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVP_SHIFT)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVP_RANGE                  22:20
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVP_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVP_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVP_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  PLL feedback divider.
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVN_SHIFT                  _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVN_FIELD                  (_MK_MASK_CONST(0x3ff) << CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVN_SHIFT)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVN_RANGE                  17:8
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVN_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVN_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVN_DEFAULT_MASK                   _MK_MASK_CONST(0x3ff)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  PLL input divider.
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVM_SHIFT                  _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVM_FIELD                  (_MK_MASK_CONST(0x1f) << CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVM_SHIFT)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVM_RANGE                  4:0
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVM_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVM_DEFAULT                        _MK_MASK_CONST(0xc)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVM_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_PLLA_OUT_0  
+#define CLK_RST_CONTROLLER_PLLA_OUT_0                   _MK_ADDR_CONST(0xb4)
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_SECURE                    0x0
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_WORD_COUNT                        0x1
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_RESET_VAL                         _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_RESET_MASK                        _MK_MASK_CONST(0xff03)
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_READ_MASK                         _MK_MASK_CONST(0xff03)
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_WRITE_MASK                        _MK_MASK_CONST(0xff03)
+//  PLLA_OUT0 divider from base PLLA (lsb denote 0.5x).
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RATIO_SHIFT                     _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RATIO_FIELD                     (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RATIO_SHIFT)
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RATIO_RANGE                     15:8
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RATIO_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RATIO_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RATIO_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RATIO_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RATIO_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RATIO_DISABLE                   _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RATIO_ENABLE                    _MK_ENUM_CONST(1)
+
+//  PLLA_OUT0 divider clk enable.  0 = disable, 1 = enable.
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_CLKEN_SHIFT                     _MK_SHIFT_CONST(1)
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_CLKEN_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_CLKEN_SHIFT)
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_CLKEN_RANGE                     1:1
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_CLKEN_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_CLKEN_DEFAULT                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_CLKEN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_CLKEN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_CLKEN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_CLKEN_INIT_ENUM                 ENABLE
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_CLKEN_DISABLE                   _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_CLKEN_ENABLE                    _MK_ENUM_CONST(1)
+
+//  PLLA_OUT0 divider reset.  0 = reset, 1 = not reset.
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RSTN_SHIFT                      _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RSTN_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RSTN_SHIFT)
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RSTN_RANGE                      0:0
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RSTN_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RSTN_DEFAULT                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RSTN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RSTN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RSTN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RSTN_INIT_ENUM                  RESET_DISABLE
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RSTN_RESET_ENABLE                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RSTN_RESET_DISABLE                      _MK_ENUM_CONST(1)
+
+
+// Reserved address 184 [0xb8] 
+
+// Register CLK_RST_CONTROLLER_PLLA_MISC_0  
+#define CLK_RST_CONTROLLER_PLLA_MISC_0                  _MK_ADDR_CONST(0xbc)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_SECURE                   0x0
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_WORD_COUNT                       0x1
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_RESET_VAL                        _MK_MASK_CONST(0x100)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_RESET_MASK                       _MK_MASK_CONST(0xc0d7ffff)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_READ_MASK                        _MK_MASK_CONST(0xc0d7ffff)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_WRITE_MASK                       _MK_MASK_CONST(0xc0d7ffff)
+//  1 = invert PLLA_OUT0 clock.
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_OUT0_INV_CLK_SHIFT                  _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_OUT0_INV_CLK_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_OUT0_INV_CLK_SHIFT)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_OUT0_INV_CLK_RANGE                  31:31
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_OUT0_INV_CLK_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_OUT0_INV_CLK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_OUT0_INV_CLK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_OUT0_INV_CLK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_OUT0_INV_CLK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  1 = bypass PLLA_OUT0 divider.
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_OUT0_DIV_BYP_SHIFT                  _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_OUT0_DIV_BYP_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_OUT0_DIV_BYP_SHIFT)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_OUT0_DIV_BYP_RANGE                  30:30
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_OUT0_DIV_BYP_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_OUT0_DIV_BYP_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_OUT0_DIV_BYP_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_OUT0_DIV_BYP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_OUT0_DIV_BYP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  Base PLLA test output select.
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_PTS_SHIFT                   _MK_SHIFT_CONST(22)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_PTS_FIELD                   (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_PTS_SHIFT)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_PTS_RANGE                   23:22
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_PTS_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_PTS_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_PTS_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_PTS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_PTS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+//  Base PLLA DCCON control.
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_DCCON_SHIFT                 _MK_SHIFT_CONST(20)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_DCCON_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_DCCON_SHIFT)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_DCCON_RANGE                 20:20
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_DCCON_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_DCCON_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_DCCON_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_DCCON_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_DCCON_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//  1 = enable, 0 = disable. 
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_LOCK_ENABLE_SHIFT                   _MK_SHIFT_CONST(18)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_LOCK_ENABLE_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_LOCK_ENABLE_SHIFT)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_LOCK_ENABLE_RANGE                   18:18
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_LOCK_ENABLE_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_LOCK_ENABLE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_LOCK_ENABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_LOCK_ENABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_LOCK_ENABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_LOCK_ENABLE_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_LOCK_ENABLE_ENABLE                  _MK_ENUM_CONST(1)
+
+//  lock select.
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_LOCK_SEL_SHIFT                      _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_LOCK_SEL_FIELD                      (_MK_MASK_CONST(0x3f) << CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_LOCK_SEL_SHIFT)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_LOCK_SEL_RANGE                      17:12
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_LOCK_SEL_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_LOCK_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_LOCK_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3f)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_LOCK_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_LOCK_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+//  Base PLLA charge pump setup control.
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_CPCON_SHIFT                 _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_CPCON_FIELD                 (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_CPCON_SHIFT)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_CPCON_RANGE                 11:8
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_CPCON_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_CPCON_DEFAULT                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_CPCON_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_CPCON_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_CPCON_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//  Base PLLA loop filter setup control.
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_LFCON_SHIFT                 _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_LFCON_FIELD                 (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_LFCON_SHIFT)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_LFCON_RANGE                 7:4
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_LFCON_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_LFCON_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_LFCON_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_LFCON_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_LFCON_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//  Base PLLA VCO range setup control.
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_VCOCON_SHIFT                        _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_VCOCON_FIELD                        (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_VCOCON_SHIFT)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_VCOCON_RANGE                        3:0
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_VCOCON_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_VCOCON_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_VCOCON_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_VCOCON_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_VCOCON_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_PLLU_BASE_0  
+#define CLK_RST_CONTROLLER_PLLU_BASE_0                  _MK_ADDR_CONST(0xc0)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_SECURE                   0x0
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_WORD_COUNT                       0x1
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_RESET_VAL                        _MK_MASK_CONST(0x10c)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_RESET_MASK                       _MK_MASK_CONST(0xe9f3ff1f)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_READ_MASK                        _MK_MASK_CONST(0xe9f3ff1f)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_WRITE_MASK                       _MK_MASK_CONST(0xe1f3ff1f)
+//  0 = no bypass, 1 = bypass.
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_BYPASS_SHIFT                        _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_BYPASS_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_BYPASS_SHIFT)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_BYPASS_RANGE                        31:31
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_BYPASS_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_BYPASS_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_BYPASS_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_BYPASS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_BYPASS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_BYPASS_INIT_ENUM                    DISABLE
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_BYPASS_DISABLE                      _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_BYPASS_ENABLE                       _MK_ENUM_CONST(1)
+
+//  0 = disable, 1 = enable.  This bit is use only when PLLU_OVERRIDE bit is set.
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_ENABLE_SHIFT                        _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_ENABLE_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_ENABLE_SHIFT)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_ENABLE_RANGE                        30:30
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_ENABLE_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_ENABLE_INIT_ENUM                    DISABLE
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_ENABLE_DISABLE                      _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_ENABLE_ENABLE                       _MK_ENUM_CONST(1)
+
+//  0 = enable reference clk, 1 = disable reference clk.
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_REF_DIS_SHIFT                       _MK_SHIFT_CONST(29)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_REF_DIS_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_REF_DIS_SHIFT)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_REF_DIS_RANGE                       29:29
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_REF_DIS_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_REF_DIS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_REF_DIS_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_REF_DIS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_REF_DIS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_REF_DIS_INIT_ENUM                   REF_ENABLE
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_REF_DIS_REF_ENABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_REF_DIS_REF_DISABLE                 _MK_ENUM_CONST(1)
+
+//  0 = not lock, 1 = lock.
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_LOCK_SHIFT                  _MK_SHIFT_CONST(27)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_LOCK_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_LOCK_SHIFT)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_LOCK_RANGE                  27:27
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_LOCK_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_LOCK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_LOCK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_LOCK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_LOCK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// 0 = FO_[ICUSB,HSIC,USB] controlled by USB controllers, 1 = controlled by PLLU_CLKENABLEs.
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_OVERRIDE_SHIFT                      _MK_SHIFT_CONST(24)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_OVERRIDE_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_OVERRIDE_SHIFT)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_OVERRIDE_RANGE                      24:24
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_OVERRIDE_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_OVERRIDE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_OVERRIDE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_OVERRIDE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_OVERRIDE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+//  FO_ICUSB output enable.  This bit is use only when PLLU_OVERRIDE bit is set.
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_CLKENABLE_ICUSB_SHIFT                       _MK_SHIFT_CONST(23)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_CLKENABLE_ICUSB_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_CLKENABLE_ICUSB_SHIFT)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_CLKENABLE_ICUSB_RANGE                       23:23
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_CLKENABLE_ICUSB_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_CLKENABLE_ICUSB_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_CLKENABLE_ICUSB_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_CLKENABLE_ICUSB_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_CLKENABLE_ICUSB_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+//  FO_HSIC output enable.  This bit is use only when PLLU_OVERRIDE bit is set.
+//  Otherwise, USB controllers will control this automatically.  
+//  0 = disable, 1 = enable.
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_CLKENABLE_HSIC_SHIFT                        _MK_SHIFT_CONST(22)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_CLKENABLE_HSIC_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_CLKENABLE_HSIC_SHIFT)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_CLKENABLE_HSIC_RANGE                        22:22
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_CLKENABLE_HSIC_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_CLKENABLE_HSIC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_CLKENABLE_HSIC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_CLKENABLE_HSIC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_CLKENABLE_HSIC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+//  FO_USB output enable.  This bit is use only when PLLU_OVERRIDE bit is set.
+//  Otherwise, USB controllers will control this automatically.  
+//  0 = disable, 1 = enable.
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_CLKENABLE_USB_SHIFT                 _MK_SHIFT_CONST(21)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_CLKENABLE_USB_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_CLKENABLE_USB_SHIFT)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_CLKENABLE_USB_RANGE                 21:21
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_CLKENABLE_USB_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_CLKENABLE_USB_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_CLKENABLE_USB_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_CLKENABLE_USB_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_CLKENABLE_USB_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//  0 = post-div of 2, 1 = post-div of 1.
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_VCO_FREQ_SHIFT                      _MK_SHIFT_CONST(20)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_VCO_FREQ_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_VCO_FREQ_SHIFT)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_VCO_FREQ_RANGE                      20:20
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_VCO_FREQ_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_VCO_FREQ_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_VCO_FREQ_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_VCO_FREQ_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_VCO_FREQ_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+//  PLL feedback divider.
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_DIVN_SHIFT                  _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_DIVN_FIELD                  (_MK_MASK_CONST(0x3ff) << CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_DIVN_SHIFT)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_DIVN_RANGE                  17:8
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_DIVN_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_DIVN_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_DIVN_DEFAULT_MASK                   _MK_MASK_CONST(0x3ff)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_DIVN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_DIVN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  PLL input divider.
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_DIVM_SHIFT                  _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_DIVM_FIELD                  (_MK_MASK_CONST(0x1f) << CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_DIVM_SHIFT)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_DIVM_RANGE                  4:0
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_DIVM_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_DIVM_DEFAULT                        _MK_MASK_CONST(0xc)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_DIVM_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_DIVM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_DIVM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Reserved address 196 [0xc4] 
+
+// Reserved address 200 [0xc8] 
+
+// Register CLK_RST_CONTROLLER_PLLU_MISC_0  
+#define CLK_RST_CONTROLLER_PLLU_MISC_0                  _MK_ADDR_CONST(0xcc)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_SECURE                   0x0
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_WORD_COUNT                       0x1
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_RESET_VAL                        _MK_MASK_CONST(0x100)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_RESET_MASK                       _MK_MASK_CONST(0x3843ffff)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_READ_MASK                        _MK_MASK_CONST(0x3843ffff)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_WRITE_MASK                       _MK_MASK_CONST(0x3843ffff)
+//  Base PLLU test output select.
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_PTS_SHIFT                   _MK_SHIFT_CONST(27)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_PTS_FIELD                   (_MK_MASK_CONST(0x7) << CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_PTS_SHIFT)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_PTS_RANGE                   29:27
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_PTS_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_PTS_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_PTS_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_PTS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_PTS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+//  1 = enable, 0 = disable. 
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LOCK_ENABLE_SHIFT                   _MK_SHIFT_CONST(22)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LOCK_ENABLE_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LOCK_ENABLE_SHIFT)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LOCK_ENABLE_RANGE                   22:22
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LOCK_ENABLE_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LOCK_ENABLE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LOCK_ENABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LOCK_ENABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LOCK_ENABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LOCK_ENABLE_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LOCK_ENABLE_ENABLE                  _MK_ENUM_CONST(1)
+
+//  lock select.
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LOCK_SEL_SHIFT                      _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LOCK_SEL_FIELD                      (_MK_MASK_CONST(0x3f) << CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LOCK_SEL_SHIFT)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LOCK_SEL_RANGE                      17:12
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LOCK_SEL_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LOCK_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LOCK_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3f)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LOCK_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LOCK_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+//  Base PLLU charge pump setup control.
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_CPCON_SHIFT                 _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_CPCON_FIELD                 (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_CPCON_SHIFT)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_CPCON_RANGE                 11:8
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_CPCON_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_CPCON_DEFAULT                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_CPCON_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_CPCON_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_CPCON_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//  Base PLLU loop filter setup control.
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LFCON_SHIFT                 _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LFCON_FIELD                 (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LFCON_SHIFT)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LFCON_RANGE                 7:4
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LFCON_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LFCON_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LFCON_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LFCON_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LFCON_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//  Base PLLU VCO range setup control.
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_VCOCON_SHIFT                        _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_VCOCON_FIELD                        (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_VCOCON_SHIFT)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_VCOCON_RANGE                        3:0
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_VCOCON_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_VCOCON_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_VCOCON_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_VCOCON_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_VCOCON_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_PLLD_BASE_0  
+#define CLK_RST_CONTROLLER_PLLD_BASE_0                  _MK_ADDR_CONST(0xd0)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_SECURE                   0x0
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_WORD_COUNT                       0x1
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_RESET_VAL                        _MK_MASK_CONST(0x10c)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_RESET_MASK                       _MK_MASK_CONST(0xe873ff1f)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_READ_MASK                        _MK_MASK_CONST(0xe873ff1f)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_WRITE_MASK                       _MK_MASK_CONST(0xe073ff1f)
+//  0 = no bypass, 1 = bypass.
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_BYPASS_SHIFT                        _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_BYPASS_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_BYPASS_SHIFT)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_BYPASS_RANGE                        31:31
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_BYPASS_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_BYPASS_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_BYPASS_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_BYPASS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_BYPASS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_BYPASS_INIT_ENUM                    DISABLE
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_BYPASS_DISABLE                      _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_BYPASS_ENABLE                       _MK_ENUM_CONST(1)
+
+//  0 = disable, 1 = enable.
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_ENABLE_SHIFT                        _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_ENABLE_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_ENABLE_SHIFT)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_ENABLE_RANGE                        30:30
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_ENABLE_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_ENABLE_INIT_ENUM                    DISABLE
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_ENABLE_DISABLE                      _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_ENABLE_ENABLE                       _MK_ENUM_CONST(1)
+
+//  0 = enable reference clk, 1 = disable reference clk.
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_REF_DIS_SHIFT                       _MK_SHIFT_CONST(29)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_REF_DIS_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_REF_DIS_SHIFT)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_REF_DIS_RANGE                       29:29
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_REF_DIS_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_REF_DIS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_REF_DIS_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_REF_DIS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_REF_DIS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_REF_DIS_INIT_ENUM                   REF_ENABLE
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_REF_DIS_REF_ENABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_REF_DIS_REF_DISABLE                 _MK_ENUM_CONST(1)
+
+//  0 = not lock, 1 = lock.
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_LOCK_SHIFT                  _MK_SHIFT_CONST(27)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_LOCK_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_LOCK_SHIFT)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_LOCK_RANGE                  27:27
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_LOCK_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_LOCK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_LOCK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_LOCK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_LOCK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  0 = post divider (2^n).
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVP_SHIFT                  _MK_SHIFT_CONST(20)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVP_FIELD                  (_MK_MASK_CONST(0x7) << CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVP_SHIFT)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVP_RANGE                  22:20
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVP_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVP_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVP_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  PLL feedback divider.
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVN_SHIFT                  _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVN_FIELD                  (_MK_MASK_CONST(0x3ff) << CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVN_SHIFT)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVN_RANGE                  17:8
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVN_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVN_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVN_DEFAULT_MASK                   _MK_MASK_CONST(0x3ff)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  PLL input divider.
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVM_SHIFT                  _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVM_FIELD                  (_MK_MASK_CONST(0x1f) << CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVM_SHIFT)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVM_RANGE                  4:0
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVM_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVM_DEFAULT                        _MK_MASK_CONST(0xc)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVM_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Reserved address 212 [0xd4] 
+
+// Reserved address 216 [0xd8] 
+
+// Register CLK_RST_CONTROLLER_PLLD_MISC_0  
+#define CLK_RST_CONTROLLER_PLLD_MISC_0                  _MK_ADDR_CONST(0xdc)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_SECURE                   0x0
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_WORD_COUNT                       0x1
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_RESET_VAL                        _MK_MASK_CONST(0x100)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+//  1 = 5-125MHz, 0 = 40-1000MHz.
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_FO_MODE_SHIFT                       _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_FO_MODE_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_FO_MODE_SHIFT)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_FO_MODE_RANGE                       31:31
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_FO_MODE_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_FO_MODE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_FO_MODE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_FO_MODE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_FO_MODE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+//  0 = disable, 1 = normal operation.
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_CLKENABLE_SHIFT                     _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_CLKENABLE_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_CLKENABLE_SHIFT)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_CLKENABLE_RANGE                     30:30
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_CLKENABLE_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_CLKENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_CLKENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_CLKENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_CLKENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+//  Base PLLD test output select.
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_PTS_SHIFT                   _MK_SHIFT_CONST(27)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_PTS_FIELD                   (_MK_MASK_CONST(0x7) << CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_PTS_SHIFT)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_PTS_RANGE                   29:27
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_PTS_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_PTS_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_PTS_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_PTS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_PTS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+//  load pulse position adjust.
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOADADJ_SHIFT                       _MK_SHIFT_CONST(24)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOADADJ_FIELD                       (_MK_MASK_CONST(0x7) << CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOADADJ_SHIFT)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOADADJ_RANGE                       26:24
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOADADJ_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOADADJ_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOADADJ_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOADADJ_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOADADJ_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+//  0 = normal operation, 1 = reset.
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_DIV_RST_SHIFT                       _MK_SHIFT_CONST(23)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_DIV_RST_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_DIV_RST_SHIFT)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_DIV_RST_RANGE                       23:23
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_DIV_RST_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_DIV_RST_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_DIV_RST_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_DIV_RST_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_DIV_RST_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+//  1 = enable, 0 = disable. 
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOCK_ENABLE_SHIFT                   _MK_SHIFT_CONST(22)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOCK_ENABLE_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOCK_ENABLE_SHIFT)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOCK_ENABLE_RANGE                   22:22
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOCK_ENABLE_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOCK_ENABLE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOCK_ENABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOCK_ENABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOCK_ENABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOCK_ENABLE_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOCK_ENABLE_ENABLE                  _MK_ENUM_CONST(1)
+
+//  lock select.
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOCK_SEL_SHIFT                      _MK_SHIFT_CONST(16)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOCK_SEL_FIELD                      (_MK_MASK_CONST(0x3f) << CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOCK_SEL_SHIFT)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOCK_SEL_RANGE                      21:16
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOCK_SEL_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOCK_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOCK_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3f)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOCK_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOCK_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+//  Base PLLD DCCON control.
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_DCCON_SHIFT                 _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_DCCON_FIELD                 (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_DCCON_SHIFT)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_DCCON_RANGE                 15:12
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_DCCON_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_DCCON_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_DCCON_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_DCCON_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_DCCON_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//  Base PLLD charge pump setup control.
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_CPCON_SHIFT                 _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_CPCON_FIELD                 (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_CPCON_SHIFT)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_CPCON_RANGE                 11:8
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_CPCON_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_CPCON_DEFAULT                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_CPCON_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_CPCON_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_CPCON_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//  Base PLLD loop filter setup control.
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LFCON_SHIFT                 _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LFCON_FIELD                 (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LFCON_SHIFT)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LFCON_RANGE                 7:4
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LFCON_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LFCON_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LFCON_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LFCON_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LFCON_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//  Base PLLD VCO range setup control.
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_VCOCON_SHIFT                        _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_VCOCON_FIELD                        (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_VCOCON_SHIFT)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_VCOCON_RANGE                        3:0
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_VCOCON_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_VCOCON_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_VCOCON_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_VCOCON_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_VCOCON_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_PLLX_BASE_0  
+#define CLK_RST_CONTROLLER_PLLX_BASE_0                  _MK_ADDR_CONST(0xe0)
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_SECURE                   0x0
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_WORD_COUNT                       0x1
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_RESET_VAL                        _MK_MASK_CONST(0x10c)
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_RESET_MASK                       _MK_MASK_CONST(0xe873ff1f)
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_READ_MASK                        _MK_MASK_CONST(0xe873ff1f)
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_WRITE_MASK                       _MK_MASK_CONST(0xe073ff1f)
+//  0 = no bypass, 1 = bypass.
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_BYPASS_SHIFT                        _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_BYPASS_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_BYPASS_SHIFT)
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_BYPASS_RANGE                        31:31
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_BYPASS_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_BYPASS_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_BYPASS_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_BYPASS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_BYPASS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_BYPASS_INIT_ENUM                    DISABLE
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_BYPASS_DISABLE                      _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_BYPASS_ENABLE                       _MK_ENUM_CONST(1)
+
+//  0 = disable, 1 = enable.
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_ENABLE_SHIFT                        _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_ENABLE_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_ENABLE_SHIFT)
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_ENABLE_RANGE                        30:30
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_ENABLE_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_ENABLE_INIT_ENUM                    DISABLE
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_ENABLE_DISABLE                      _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_ENABLE_ENABLE                       _MK_ENUM_CONST(1)
+
+//  0 = enable reference clk, 1 = disable reference clk.
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_REF_DIS_SHIFT                       _MK_SHIFT_CONST(29)
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_REF_DIS_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_REF_DIS_SHIFT)
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_REF_DIS_RANGE                       29:29
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_REF_DIS_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_REF_DIS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_REF_DIS_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_REF_DIS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_REF_DIS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_REF_DIS_INIT_ENUM                   REF_ENABLE
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_REF_DIS_REF_ENABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_REF_DIS_REF_DISABLE                 _MK_ENUM_CONST(1)
+
+//  0 = not lock, 1 = lock.
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_LOCK_SHIFT                  _MK_SHIFT_CONST(27)
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_LOCK_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_LOCK_SHIFT)
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_LOCK_RANGE                  27:27
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_LOCK_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_LOCK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_LOCK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_LOCK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_LOCK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  0 = post divider (2^n).
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_DIVP_SHIFT                  _MK_SHIFT_CONST(20)
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_DIVP_FIELD                  (_MK_MASK_CONST(0x7) << CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_DIVP_SHIFT)
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_DIVP_RANGE                  22:20
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_DIVP_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_DIVP_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_DIVP_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_DIVP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_DIVP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  PLL feedback divider.
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_DIVN_SHIFT                  _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_DIVN_FIELD                  (_MK_MASK_CONST(0x3ff) << CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_DIVN_SHIFT)
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_DIVN_RANGE                  17:8
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_DIVN_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_DIVN_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_DIVN_DEFAULT_MASK                   _MK_MASK_CONST(0x3ff)
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_DIVN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_DIVN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  PLL input divider.
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_DIVM_SHIFT                  _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_DIVM_FIELD                  (_MK_MASK_CONST(0x1f) << CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_DIVM_SHIFT)
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_DIVM_RANGE                  4:0
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_DIVM_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_DIVM_DEFAULT                        _MK_MASK_CONST(0xc)
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_DIVM_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_DIVM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_DIVM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_PLLX_MISC_0  
+#define CLK_RST_CONTROLLER_PLLX_MISC_0                  _MK_ADDR_CONST(0xe4)
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_SECURE                   0x0
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_WORD_COUNT                       0x1
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_RESET_VAL                        _MK_MASK_CONST(0x100100)
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_RESET_MASK                       _MK_MASK_CONST(0xfd7ffff)
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_READ_MASK                        _MK_MASK_CONST(0xfd7ffff)
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_WRITE_MASK                       _MK_MASK_CONST(0xfd7ffff)
+//  Base PLLX setup.
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_SETUP_SHIFT                 _MK_SHIFT_CONST(24)
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_SETUP_FIELD                 (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_SETUP_SHIFT)
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_SETUP_RANGE                 27:24
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_SETUP_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_SETUP_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_SETUP_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_SETUP_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_SETUP_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//  Base PLLX test output select.
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_PTS_SHIFT                   _MK_SHIFT_CONST(22)
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_PTS_FIELD                   (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_PTS_SHIFT)
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_PTS_RANGE                   23:22
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_PTS_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_PTS_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_PTS_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_PTS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_PTS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+//  Base PLLX DCCON control.
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_DCCON_SHIFT                 _MK_SHIFT_CONST(20)
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_DCCON_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_DCCON_SHIFT)
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_DCCON_RANGE                 20:20
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_DCCON_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_DCCON_DEFAULT                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_DCCON_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_DCCON_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_DCCON_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//  1 = enable, 0 = disable. 
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_LOCK_ENABLE_SHIFT                   _MK_SHIFT_CONST(18)
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_LOCK_ENABLE_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_LOCK_ENABLE_SHIFT)
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_LOCK_ENABLE_RANGE                   18:18
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_LOCK_ENABLE_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_LOCK_ENABLE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_LOCK_ENABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_LOCK_ENABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_LOCK_ENABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_LOCK_ENABLE_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_LOCK_ENABLE_ENABLE                  _MK_ENUM_CONST(1)
+
+//  lock select.
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_LOCK_SEL_SHIFT                      _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_LOCK_SEL_FIELD                      (_MK_MASK_CONST(0x3f) << CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_LOCK_SEL_SHIFT)
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_LOCK_SEL_RANGE                      17:12
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_LOCK_SEL_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_LOCK_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_LOCK_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3f)
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_LOCK_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_LOCK_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+//  Base PLLX charge pump setup control.
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_CPCON_SHIFT                 _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_CPCON_FIELD                 (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_CPCON_SHIFT)
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_CPCON_RANGE                 11:8
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_CPCON_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_CPCON_DEFAULT                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_CPCON_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_CPCON_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_CPCON_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//  Base PLLX loop filter setup control.
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_LFCON_SHIFT                 _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_LFCON_FIELD                 (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_LFCON_SHIFT)
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_LFCON_RANGE                 7:4
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_LFCON_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_LFCON_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_LFCON_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_LFCON_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_LFCON_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//  Base PLLX VCO range setup control.
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_VCOCON_SHIFT                        _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_VCOCON_FIELD                        (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_VCOCON_SHIFT)
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_VCOCON_RANGE                        3:0
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_VCOCON_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_VCOCON_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_VCOCON_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_VCOCON_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_VCOCON_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_PLLE_BASE_0  
+#define CLK_RST_CONTROLLER_PLLE_BASE_0                  _MK_ADDR_CONST(0xe8)
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_SECURE                   0x0
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_WORD_COUNT                       0x1
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_RESET_VAL                        _MK_MASK_CONST(0xd18c801)
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+//  Enable CML pdivider. 0 = disable, 1 = enable.
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_ENABLE_CML_SHIFT                    _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_ENABLE_CML_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_ENABLE_CML_SHIFT)
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_ENABLE_CML_RANGE                    31:31
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_ENABLE_CML_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_ENABLE_CML_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_ENABLE_CML_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_ENABLE_CML_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_ENABLE_CML_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_ENABLE_CML_INIT_ENUM                        DISABLE
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_ENABLE_CML_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_ENABLE_CML_ENABLE                   _MK_ENUM_CONST(1)
+
+//  PLL enable. 0 = disable, 1 = enable.
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_ENABLE_SHIFT                        _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_ENABLE_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_ENABLE_SHIFT)
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_ENABLE_RANGE                        30:30
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_ENABLE_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_ENABLE_INIT_ENUM                    DISABLE
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_ENABLE_DISABLE                      _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_ENABLE_ENABLE                       _MK_ENUM_CONST(1)
+
+//  Forces PLL_LOCK to 1.
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_LOCK_OVERRIDE_SHIFT                 _MK_SHIFT_CONST(29)
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_LOCK_OVERRIDE_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_LOCK_OVERRIDE_SHIFT)
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_LOCK_OVERRIDE_RANGE                 29:29
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_LOCK_OVERRIDE_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_LOCK_OVERRIDE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_LOCK_OVERRIDE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_LOCK_OVERRIDE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_LOCK_OVERRIDE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//  0 gives vcoclk/4, 1 gives vcoclk/2 clock to the interpolator logic. Normally set to zero.
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_FDIV4B_SHIFT                        _MK_SHIFT_CONST(28)
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_FDIV4B_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_FDIV4B_SHIFT)
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_FDIV4B_RANGE                        28:28
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_FDIV4B_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_FDIV4B_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_FDIV4B_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_FDIV4B_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_FDIV4B_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+//  divider control for CLOCKOUT_CML/CLOCKOUTB_CML.
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_PLDIV_CML_SHIFT                     _MK_SHIFT_CONST(24)
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_PLDIV_CML_FIELD                     (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_PLDIV_CML_SHIFT)
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_PLDIV_CML_RANGE                     27:24
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_PLDIV_CML_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_PLDIV_CML_DEFAULT                   _MK_MASK_CONST(0xd)
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_PLDIV_CML_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_PLDIV_CML_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_PLDIV_CML_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+//  Base PLLE setup[19:18].
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_EXT_SETUP_19_18_SHIFT                       _MK_SHIFT_CONST(22)
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_EXT_SETUP_19_18_FIELD                       (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_EXT_SETUP_19_18_SHIFT)
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_EXT_SETUP_19_18_RANGE                       23:22
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_EXT_SETUP_19_18_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_EXT_SETUP_19_18_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_EXT_SETUP_19_18_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_EXT_SETUP_19_18_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_EXT_SETUP_19_18_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+//  post divider for CLOCKOUT and SYNC_CLOCKOUT.
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_PLDIV_SHIFT                 _MK_SHIFT_CONST(16)
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_PLDIV_FIELD                 (_MK_MASK_CONST(0x3f) << CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_PLDIV_SHIFT)
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_PLDIV_RANGE                 21:16
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_PLDIV_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_PLDIV_DEFAULT                       _MK_MASK_CONST(0x18)
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_PLDIV_DEFAULT_MASK                  _MK_MASK_CONST(0x3f)
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_PLDIV_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_PLDIV_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//  feedback divider.
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_NDIV_SHIFT                  _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_NDIV_FIELD                  (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_NDIV_SHIFT)
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_NDIV_RANGE                  15:8
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_NDIV_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_NDIV_DEFAULT                        _MK_MASK_CONST(0xc8)
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_NDIV_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_NDIV_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_NDIV_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  input divider.
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_MDIV_SHIFT                  _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_MDIV_FIELD                  (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_MDIV_SHIFT)
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_MDIV_RANGE                  7:0
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_MDIV_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_MDIV_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_MDIV_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_MDIV_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_MDIV_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_PLLE_MISC_0  
+#define CLK_RST_CONTROLLER_PLLE_MISC_0                  _MK_ADDR_CONST(0xec)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_SECURE                   0x0
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_WORD_COUNT                       0x1
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_WRITE_MASK                       _MK_MASK_CONST(0xffff07ff)
+//  Base PLLE setup[15:0].
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_SETUP_SHIFT                 _MK_SHIFT_CONST(16)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_SETUP_FIELD                 (_MK_MASK_CONST(0xffff) << CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_SETUP_SHIFT)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_SETUP_RANGE                 31:16
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_SETUP_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_SETUP_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_SETUP_DEFAULT_MASK                  _MK_MASK_CONST(0xffff)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_SETUP_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_SETUP_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//  When read, this is PLL_READY status: 1 = PLL finish training, 0 = PLL not finish training.
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_PLL_READY_SHIFT                     _MK_SHIFT_CONST(15)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_PLL_READY_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_PLL_READY_SHIFT)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_PLL_READY_RANGE                     15:15
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_PLL_READY_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_PLL_READY_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_PLL_READY_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_PLL_READY_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_PLL_READY_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+//  Process monitor debug output.
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_MON_TESTOUT_SHIFT                   _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_MON_TESTOUT_FIELD                   (_MK_MASK_CONST(0x7) << CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_MON_TESTOUT_SHIFT)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_MON_TESTOUT_RANGE                   14:12
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_MON_TESTOUT_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_MON_TESTOUT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_MON_TESTOUT_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_MON_TESTOUT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_MON_TESTOUT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+//  0 = not lock, 1 = lock.
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_LOCK_SHIFT                  _MK_SHIFT_CONST(11)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_LOCK_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_LOCK_SHIFT)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_LOCK_RANGE                  11:11
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_LOCK_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_LOCK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_LOCK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_LOCK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_LOCK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  0 = enable reference clk, 1 = disable reference clk.
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_REF_DIS_SHIFT                       _MK_SHIFT_CONST(10)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_REF_DIS_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_REF_DIS_SHIFT)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_REF_DIS_RANGE                       10:10
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_REF_DIS_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_REF_DIS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_REF_DIS_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_REF_DIS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_REF_DIS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_REF_DIS_INIT_ENUM                   REF_ENABLE
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_REF_DIS_REF_ENABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_REF_DIS_REF_DISABLE                 _MK_ENUM_CONST(1)
+
+//  1 = enable, 0 = disable. 
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_LOCK_ENABLE_SHIFT                   _MK_SHIFT_CONST(9)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_LOCK_ENABLE_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_LOCK_ENABLE_SHIFT)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_LOCK_ENABLE_RANGE                   9:9
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_LOCK_ENABLE_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_LOCK_ENABLE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_LOCK_ENABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_LOCK_ENABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_LOCK_ENABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_LOCK_ENABLE_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_LOCK_ENABLE_ENABLE                  _MK_ENUM_CONST(1)
+
+//  Bypass PLL (similar to PTO control of other PLL).
+//  0 = PTO always 0 if PLLE_ENABLE=0 (SYN_CLOCKOUT=0), 
+//  0 = PTO = PLLE CLOCKIN if PLLE_ENABLE=1,
+//  1 = PTO = PLLE FO (SYN_CLOCKOUT=VCOCLOCK/PLDIV).
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_PTS_SHIFT                   _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_PTS_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_PTS_SHIFT)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_PTS_RANGE                   8:8
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_PTS_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_PTS_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_PTS_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_PTS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_PTS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+//  Base PLLE charge pump gain control.
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_KCP_SHIFT                   _MK_SHIFT_CONST(6)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_KCP_FIELD                   (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_KCP_SHIFT)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_KCP_RANGE                   7:6
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_KCP_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_KCP_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_KCP_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_KCP_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_KCP_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+//  Base PLLE loop filter resistor control.
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_LFRES_SHIFT                 _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_LFRES_FIELD                 (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_LFRES_SHIFT)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_LFRES_RANGE                 5:4
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_LFRES_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_LFRES_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_LFRES_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_LFRES_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_LFRES_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//  Base PLLE setup[17:16].
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_EXT_SETUP_17_16_SHIFT                       _MK_SHIFT_CONST(2)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_EXT_SETUP_17_16_FIELD                       (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_EXT_SETUP_17_16_SHIFT)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_EXT_SETUP_17_16_RANGE                       3:2
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_EXT_SETUP_17_16_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_EXT_SETUP_17_16_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_EXT_SETUP_17_16_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_EXT_SETUP_17_16_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_EXT_SETUP_17_16_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+//  Base PLLE sync mode (leave it at 0).
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_SYNC_MODE_SHIFT                     _MK_SHIFT_CONST(1)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_SYNC_MODE_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_SYNC_MODE_SHIFT)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_SYNC_MODE_RANGE                     1:1
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_SYNC_MODE_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_SYNC_MODE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_SYNC_MODE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_SYNC_MODE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_SYNC_MODE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+//  Base PLLE VCO gain.
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_KVCO_SHIFT                  _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_KVCO_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_KVCO_SHIFT)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_KVCO_RANGE                  0:0
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_KVCO_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_KVCO_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_KVCO_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_KVCO_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_KVCO_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_PLLS_BASE_0  
+#define CLK_RST_CONTROLLER_PLLS_BASE_0                  _MK_ADDR_CONST(0xf0)
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_SECURE                   0x0
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_WORD_COUNT                       0x1
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_RESET_VAL                        _MK_MASK_CONST(0x101)
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_RESET_MASK                       _MK_MASK_CONST(0xe873ff0f)
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_READ_MASK                        _MK_MASK_CONST(0xe873ff0f)
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_WRITE_MASK                       _MK_MASK_CONST(0xe073ff0f)
+//  0 = no bypass, 1 = bypass.
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_BYPASS_SHIFT                        _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_BYPASS_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_BYPASS_SHIFT)
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_BYPASS_RANGE                        31:31
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_BYPASS_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_BYPASS_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_BYPASS_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_BYPASS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_BYPASS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_BYPASS_INIT_ENUM                    DISABLE
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_BYPASS_DISABLE                      _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_BYPASS_ENABLE                       _MK_ENUM_CONST(1)
+
+//  0 = disable, 1 = enable.
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_ENABLE_SHIFT                        _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_ENABLE_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_ENABLE_SHIFT)
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_ENABLE_RANGE                        30:30
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_ENABLE_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_ENABLE_INIT_ENUM                    DISABLE
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_ENABLE_DISABLE                      _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_ENABLE_ENABLE                       _MK_ENUM_CONST(1)
+
+//  0 = enable reference clk, 1 = disable reference clk.
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_REF_DIS_SHIFT                       _MK_SHIFT_CONST(29)
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_REF_DIS_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_REF_DIS_SHIFT)
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_REF_DIS_RANGE                       29:29
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_REF_DIS_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_REF_DIS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_REF_DIS_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_REF_DIS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_REF_DIS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_REF_DIS_INIT_ENUM                   REF_ENABLE
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_REF_DIS_REF_ENABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_REF_DIS_REF_DISABLE                 _MK_ENUM_CONST(1)
+
+//  0 = not lock, 1 = lock.
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_LOCK_SHIFT                  _MK_SHIFT_CONST(27)
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_LOCK_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_LOCK_SHIFT)
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_LOCK_RANGE                  27:27
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_LOCK_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_LOCK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_LOCK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_LOCK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_LOCK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  0 = post divider (2^n).
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_DIVP_SHIFT                  _MK_SHIFT_CONST(20)
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_DIVP_FIELD                  (_MK_MASK_CONST(0x7) << CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_DIVP_SHIFT)
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_DIVP_RANGE                  22:20
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_DIVP_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_DIVP_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_DIVP_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_DIVP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_DIVP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  PLL feedback divider.
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_DIVN_SHIFT                  _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_DIVN_FIELD                  (_MK_MASK_CONST(0x3ff) << CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_DIVN_SHIFT)
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_DIVN_RANGE                  17:8
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_DIVN_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_DIVN_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_DIVN_DEFAULT_MASK                   _MK_MASK_CONST(0x3ff)
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_DIVN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_DIVN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  PLL input divider.
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_DIVM_SHIFT                  _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_DIVM_FIELD                  (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_DIVM_SHIFT)
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_DIVM_RANGE                  3:0
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_DIVM_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_DIVM_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_DIVM_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_DIVM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_DIVM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_PLLS_MISC_0  
+#define CLK_RST_CONTROLLER_PLLS_MISC_0                  _MK_ADDR_CONST(0xf4)
+#define CLK_RST_CONTROLLER_PLLS_MISC_0_SECURE                   0x0
+#define CLK_RST_CONTROLLER_PLLS_MISC_0_WORD_COUNT                       0x1
+#define CLK_RST_CONTROLLER_PLLS_MISC_0_RESET_VAL                        _MK_MASK_CONST(0x100)
+#define CLK_RST_CONTROLLER_PLLS_MISC_0_RESET_MASK                       _MK_MASK_CONST(0xc7ffff)
+#define CLK_RST_CONTROLLER_PLLS_MISC_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLS_MISC_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLS_MISC_0_READ_MASK                        _MK_MASK_CONST(0xc7ffff)
+#define CLK_RST_CONTROLLER_PLLS_MISC_0_WRITE_MASK                       _MK_MASK_CONST(0xc7ffff)
+//  Base PLLS test output select.
+#define CLK_RST_CONTROLLER_PLLS_MISC_0_PLLS_PTS_SHIFT                   _MK_SHIFT_CONST(22)
+#define CLK_RST_CONTROLLER_PLLS_MISC_0_PLLS_PTS_FIELD                   (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_PLLS_MISC_0_PLLS_PTS_SHIFT)
+#define CLK_RST_CONTROLLER_PLLS_MISC_0_PLLS_PTS_RANGE                   23:22
+#define CLK_RST_CONTROLLER_PLLS_MISC_0_PLLS_PTS_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_PLLS_MISC_0_PLLS_PTS_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLS_MISC_0_PLLS_PTS_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_PLLS_MISC_0_PLLS_PTS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLS_MISC_0_PLLS_PTS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+//  1 = enable, 0 = disable. 
+#define CLK_RST_CONTROLLER_PLLS_MISC_0_PLLS_LOCK_ENABLE_SHIFT                   _MK_SHIFT_CONST(18)
+#define CLK_RST_CONTROLLER_PLLS_MISC_0_PLLS_LOCK_ENABLE_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLS_MISC_0_PLLS_LOCK_ENABLE_SHIFT)
+#define CLK_RST_CONTROLLER_PLLS_MISC_0_PLLS_LOCK_ENABLE_RANGE                   18:18
+#define CLK_RST_CONTROLLER_PLLS_MISC_0_PLLS_LOCK_ENABLE_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_PLLS_MISC_0_PLLS_LOCK_ENABLE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLS_MISC_0_PLLS_LOCK_ENABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLS_MISC_0_PLLS_LOCK_ENABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLS_MISC_0_PLLS_LOCK_ENABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLS_MISC_0_PLLS_LOCK_ENABLE_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLS_MISC_0_PLLS_LOCK_ENABLE_ENABLE                  _MK_ENUM_CONST(1)
+
+//  lock select.
+#define CLK_RST_CONTROLLER_PLLS_MISC_0_PLLS_LOCK_SEL_SHIFT                      _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_PLLS_MISC_0_PLLS_LOCK_SEL_FIELD                      (_MK_MASK_CONST(0x3f) << CLK_RST_CONTROLLER_PLLS_MISC_0_PLLS_LOCK_SEL_SHIFT)
+#define CLK_RST_CONTROLLER_PLLS_MISC_0_PLLS_LOCK_SEL_RANGE                      17:12
+#define CLK_RST_CONTROLLER_PLLS_MISC_0_PLLS_LOCK_SEL_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_PLLS_MISC_0_PLLS_LOCK_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLS_MISC_0_PLLS_LOCK_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3f)
+#define CLK_RST_CONTROLLER_PLLS_MISC_0_PLLS_LOCK_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLS_MISC_0_PLLS_LOCK_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+//  Base PLLS charge pump setup control.
+#define CLK_RST_CONTROLLER_PLLS_MISC_0_PLLS_CPCON_SHIFT                 _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_PLLS_MISC_0_PLLS_CPCON_FIELD                 (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_PLLS_MISC_0_PLLS_CPCON_SHIFT)
+#define CLK_RST_CONTROLLER_PLLS_MISC_0_PLLS_CPCON_RANGE                 11:8
+#define CLK_RST_CONTROLLER_PLLS_MISC_0_PLLS_CPCON_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_PLLS_MISC_0_PLLS_CPCON_DEFAULT                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLS_MISC_0_PLLS_CPCON_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_PLLS_MISC_0_PLLS_CPCON_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLS_MISC_0_PLLS_CPCON_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//  Base PLLS loop filter setup control.
+#define CLK_RST_CONTROLLER_PLLS_MISC_0_PLLS_LFCON_SHIFT                 _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_PLLS_MISC_0_PLLS_LFCON_FIELD                 (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_PLLS_MISC_0_PLLS_LFCON_SHIFT)
+#define CLK_RST_CONTROLLER_PLLS_MISC_0_PLLS_LFCON_RANGE                 7:4
+#define CLK_RST_CONTROLLER_PLLS_MISC_0_PLLS_LFCON_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_PLLS_MISC_0_PLLS_LFCON_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLS_MISC_0_PLLS_LFCON_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_PLLS_MISC_0_PLLS_LFCON_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLS_MISC_0_PLLS_LFCON_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//  Base PLLS VCO range setup control.
+#define CLK_RST_CONTROLLER_PLLS_MISC_0_PLLS_VCOCON_SHIFT                        _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_PLLS_MISC_0_PLLS_VCOCON_FIELD                        (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_PLLS_MISC_0_PLLS_VCOCON_SHIFT)
+#define CLK_RST_CONTROLLER_PLLS_MISC_0_PLLS_VCOCON_RANGE                        3:0
+#define CLK_RST_CONTROLLER_PLLS_MISC_0_PLLS_VCOCON_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_PLLS_MISC_0_PLLS_VCOCON_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLS_MISC_0_PLLS_VCOCON_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_PLLS_MISC_0_PLLS_VCOCON_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLS_MISC_0_PLLS_VCOCON_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0  
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0                 _MK_ADDR_CONST(0xf8)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_SECURE                  0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_WORD_COUNT                      0x1
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_RESET_MASK                      _MK_MASK_CONST(0xfffffffe)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_READ_MASK                       _MK_MASK_CONST(0xfffffffe)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_WRITE_MASK                      _MK_MASK_CONST(0xfffffffe)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_TVDAC_CLK_OVR_ON_SHIFT                  _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_TVDAC_CLK_OVR_ON_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_TVDAC_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_TVDAC_CLK_OVR_ON_RANGE                  31:31
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_TVDAC_CLK_OVR_ON_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_TVDAC_CLK_OVR_ON_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_TVDAC_CLK_OVR_ON_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_TVDAC_CLK_OVR_ON_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_TVDAC_CLK_OVR_ON_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_PPCS_CLK_OVR_ON_SHIFT                   _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_PPCS_CLK_OVR_ON_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_PPCS_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_PPCS_CLK_OVR_ON_RANGE                   30:30
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_PPCS_CLK_OVR_ON_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_PPCS_CLK_OVR_ON_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_PPCS_CLK_OVR_ON_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_PPCS_CLK_OVR_ON_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_PPCS_CLK_OVR_ON_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_BSEA_CLK_OVR_ON_SHIFT                   _MK_SHIFT_CONST(29)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_BSEA_CLK_OVR_ON_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_BSEA_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_BSEA_CLK_OVR_ON_RANGE                   29:29
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_BSEA_CLK_OVR_ON_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_BSEA_CLK_OVR_ON_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_BSEA_CLK_OVR_ON_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_BSEA_CLK_OVR_ON_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_BSEA_CLK_OVR_ON_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_BSEV_CLK_OVR_ON_SHIFT                   _MK_SHIFT_CONST(28)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_BSEV_CLK_OVR_ON_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_BSEV_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_BSEV_CLK_OVR_ON_RANGE                   28:28
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_BSEV_CLK_OVR_ON_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_BSEV_CLK_OVR_ON_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_BSEV_CLK_OVR_ON_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_BSEV_CLK_OVR_ON_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_BSEV_CLK_OVR_ON_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_VDE_CLK_OVR_ON_SHIFT                    _MK_SHIFT_CONST(27)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_VDE_CLK_OVR_ON_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_VDE_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_VDE_CLK_OVR_ON_RANGE                    27:27
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_VDE_CLK_OVR_ON_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_VDE_CLK_OVR_ON_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_VDE_CLK_OVR_ON_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_VDE_CLK_OVR_ON_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_VDE_CLK_OVR_ON_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_VPECLK_OVR_ON_SHIFT                        _MK_SHIFT_CONST(26)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_VPECLK_OVR_ON_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_VPECLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_VPECLK_OVR_ON_RANGE                        26:26
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_VPECLK_OVR_ON_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_VPECLK_OVR_ON_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_VPECLK_OVR_ON_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_VPECLK_OVR_ON_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_VPECLK_OVR_ON_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_TEXCLK_OVR_ON_SHIFT                        _MK_SHIFT_CONST(25)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_TEXCLK_OVR_ON_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_TEXCLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_TEXCLK_OVR_ON_RANGE                        25:25
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_TEXCLK_OVR_ON_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_TEXCLK_OVR_ON_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_TEXCLK_OVR_ON_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_TEXCLK_OVR_ON_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_TEXCLK_OVR_ON_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_SETUPCLK_OVR_ON_SHIFT                      _MK_SHIFT_CONST(24)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_SETUPCLK_OVR_ON_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_SETUPCLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_SETUPCLK_OVR_ON_RANGE                      24:24
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_SETUPCLK_OVR_ON_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_SETUPCLK_OVR_ON_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_SETUPCLK_OVR_ON_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_SETUPCLK_OVR_ON_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_SETUPCLK_OVR_ON_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_QRASTCLK_OVR_ON_SHIFT                      _MK_SHIFT_CONST(23)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_QRASTCLK_OVR_ON_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_QRASTCLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_QRASTCLK_OVR_ON_RANGE                      23:23
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_QRASTCLK_OVR_ON_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_QRASTCLK_OVR_ON_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_QRASTCLK_OVR_ON_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_QRASTCLK_OVR_ON_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_QRASTCLK_OVR_ON_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_PSEQCLK_OVR_ON_SHIFT                       _MK_SHIFT_CONST(22)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_PSEQCLK_OVR_ON_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_PSEQCLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_PSEQCLK_OVR_ON_RANGE                       22:22
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_PSEQCLK_OVR_ON_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_PSEQCLK_OVR_ON_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_PSEQCLK_OVR_ON_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_PSEQCLK_OVR_ON_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_PSEQCLK_OVR_ON_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_IDXCLK_OVR_ON_SHIFT                        _MK_SHIFT_CONST(21)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_IDXCLK_OVR_ON_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_IDXCLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_IDXCLK_OVR_ON_RANGE                        21:21
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_IDXCLK_OVR_ON_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_IDXCLK_OVR_ON_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_IDXCLK_OVR_ON_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_IDXCLK_OVR_ON_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_IDXCLK_OVR_ON_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_FDCCLK_OVR_ON_SHIFT                        _MK_SHIFT_CONST(20)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_FDCCLK_OVR_ON_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_FDCCLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_FDCCLK_OVR_ON_RANGE                        20:20
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_FDCCLK_OVR_ON_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_FDCCLK_OVR_ON_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_FDCCLK_OVR_ON_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_FDCCLK_OVR_ON_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_FDCCLK_OVR_ON_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_DWRCLK_OVR_ON_SHIFT                        _MK_SHIFT_CONST(19)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_DWRCLK_OVR_ON_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_DWRCLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_DWRCLK_OVR_ON_RANGE                        19:19
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_DWRCLK_OVR_ON_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_DWRCLK_OVR_ON_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_DWRCLK_OVR_ON_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_DWRCLK_OVR_ON_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_DWRCLK_OVR_ON_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_CLIPCLK_OVR_ON_SHIFT                       _MK_SHIFT_CONST(18)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_CLIPCLK_OVR_ON_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_CLIPCLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_CLIPCLK_OVR_ON_RANGE                       18:18
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_CLIPCLK_OVR_ON_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_CLIPCLK_OVR_ON_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_CLIPCLK_OVR_ON_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_CLIPCLK_OVR_ON_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_CLIPCLK_OVR_ON_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_ATRASTCLK_OVR_ON_SHIFT                     _MK_SHIFT_CONST(17)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_ATRASTCLK_OVR_ON_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_ATRASTCLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_ATRASTCLK_OVR_ON_RANGE                     17:17
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_ATRASTCLK_OVR_ON_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_ATRASTCLK_OVR_ON_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_ATRASTCLK_OVR_ON_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_ATRASTCLK_OVR_ON_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_ATRASTCLK_OVR_ON_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_ALUCLK_OVR_ON_SHIFT                        _MK_SHIFT_CONST(16)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_ALUCLK_OVR_ON_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_ALUCLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_ALUCLK_OVR_ON_RANGE                        16:16
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_ALUCLK_OVR_ON_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_ALUCLK_OVR_ON_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_ALUCLK_OVR_ON_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_ALUCLK_OVR_ON_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_ALUCLK_OVR_ON_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_VI_CLK_OVR_ON_SHIFT                     _MK_SHIFT_CONST(15)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_VI_CLK_OVR_ON_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_VI_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_VI_CLK_OVR_ON_RANGE                     15:15
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_VI_CLK_OVR_ON_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_VI_CLK_OVR_ON_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_VI_CLK_OVR_ON_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_VI_CLK_OVR_ON_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_VI_CLK_OVR_ON_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_MPE_CLK_OVR_ON_SHIFT                    _MK_SHIFT_CONST(14)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_MPE_CLK_OVR_ON_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_MPE_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_MPE_CLK_OVR_ON_RANGE                    14:14
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_MPE_CLK_OVR_ON_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_MPE_CLK_OVR_ON_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_MPE_CLK_OVR_ON_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_MPE_CLK_OVR_ON_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_MPE_CLK_OVR_ON_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_MPCORE_CLK_OVR_ON_SHIFT                 _MK_SHIFT_CONST(13)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_MPCORE_CLK_OVR_ON_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_MPCORE_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_MPCORE_CLK_OVR_ON_RANGE                 13:13
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_MPCORE_CLK_OVR_ON_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_MPCORE_CLK_OVR_ON_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_MPCORE_CLK_OVR_ON_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_MPCORE_CLK_OVR_ON_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_MPCORE_CLK_OVR_ON_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_MC_CLK_OVR_ON_SHIFT                     _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_MC_CLK_OVR_ON_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_MC_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_MC_CLK_OVR_ON_RANGE                     12:12
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_MC_CLK_OVR_ON_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_MC_CLK_OVR_ON_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_MC_CLK_OVR_ON_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_MC_CLK_OVR_ON_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_MC_CLK_OVR_ON_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_KBC_CLK_OVR_ON_SHIFT                    _MK_SHIFT_CONST(11)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_KBC_CLK_OVR_ON_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_KBC_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_KBC_CLK_OVR_ON_RANGE                    11:11
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_KBC_CLK_OVR_ON_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_KBC_CLK_OVR_ON_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_KBC_CLK_OVR_ON_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_KBC_CLK_OVR_ON_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_KBC_CLK_OVR_ON_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_RIF_CLK_OVR_ON_SHIFT                 _MK_SHIFT_CONST(10)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_RIF_CLK_OVR_ON_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_RIF_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_RIF_CLK_OVR_ON_RANGE                 10:10
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_RIF_CLK_OVR_ON_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_RIF_CLK_OVR_ON_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_RIF_CLK_OVR_ON_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_RIF_CLK_OVR_ON_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_RIF_CLK_OVR_ON_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_RDMA_CLK_OVR_ON_SHIFT                        _MK_SHIFT_CONST(9)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_RDMA_CLK_OVR_ON_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_RDMA_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_RDMA_CLK_OVR_ON_RANGE                        9:9
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_RDMA_CLK_OVR_ON_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_RDMA_CLK_OVR_ON_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_RDMA_CLK_OVR_ON_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_RDMA_CLK_OVR_ON_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_RDMA_CLK_OVR_ON_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_INTFC_OVR_ON_SHIFT                   _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_INTFC_OVR_ON_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_INTFC_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_INTFC_OVR_ON_RANGE                   8:8
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_INTFC_OVR_ON_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_INTFC_OVR_ON_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_INTFC_OVR_ON_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_INTFC_OVR_ON_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_INTFC_OVR_ON_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_CLK_OVR_ON_SHIFT                     _MK_SHIFT_CONST(7)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_CLK_OVR_ON_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_CLK_OVR_ON_RANGE                     7:7
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_CLK_OVR_ON_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_CLK_OVR_ON_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_CLK_OVR_ON_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_CLK_OVR_ON_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_CLK_OVR_ON_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_CDMA_CLK_OVR_ON_SHIFT                        _MK_SHIFT_CONST(6)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_CDMA_CLK_OVR_ON_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_CDMA_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_CDMA_CLK_OVR_ON_RANGE                        6:6
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_CDMA_CLK_OVR_ON_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_CDMA_CLK_OVR_ON_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_CDMA_CLK_OVR_ON_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_CDMA_CLK_OVR_ON_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_CDMA_CLK_OVR_ON_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR2D_CLK_OVR_ON_SHIFT                   _MK_SHIFT_CONST(5)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR2D_CLK_OVR_ON_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR2D_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR2D_CLK_OVR_ON_RANGE                   5:5
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR2D_CLK_OVR_ON_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR2D_CLK_OVR_ON_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR2D_CLK_OVR_ON_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR2D_CLK_OVR_ON_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR2D_CLK_OVR_ON_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_EPP_CLK_OVR_ON_SHIFT                    _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_EPP_CLK_OVR_ON_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_EPP_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_EPP_CLK_OVR_ON_RANGE                    4:4
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_EPP_CLK_OVR_ON_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_EPP_CLK_OVR_ON_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_EPP_CLK_OVR_ON_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_EPP_CLK_OVR_ON_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_EPP_CLK_OVR_ON_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_EMC_CLK_OVR_ON_SHIFT                    _MK_SHIFT_CONST(3)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_EMC_CLK_OVR_ON_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_EMC_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_EMC_CLK_OVR_ON_RANGE                    3:3
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_EMC_CLK_OVR_ON_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_EMC_CLK_OVR_ON_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_EMC_CLK_OVR_ON_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_EMC_CLK_OVR_ON_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_EMC_CLK_OVR_ON_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_DCB_CLK_OVR_ON_SHIFT                    _MK_SHIFT_CONST(2)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_DCB_CLK_OVR_ON_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_DCB_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_DCB_CLK_OVR_ON_RANGE                    2:2
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_DCB_CLK_OVR_ON_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_DCB_CLK_OVR_ON_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_DCB_CLK_OVR_ON_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_DCB_CLK_OVR_ON_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_DCB_CLK_OVR_ON_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_DC_CLK_OVR_ON_SHIFT                     _MK_SHIFT_CONST(1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_DC_CLK_OVR_ON_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_DC_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_DC_CLK_OVR_ON_RANGE                     1:1
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_DC_CLK_OVR_ON_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_DC_CLK_OVR_ON_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_DC_CLK_OVR_ON_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_DC_CLK_OVR_ON_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_DC_CLK_OVR_ON_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0  
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0                 _MK_ADDR_CONST(0xfc)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_SECURE                  0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_WORD_COUNT                      0x1
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_RESET_MASK                      _MK_MASK_CONST(0x3fff)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_READ_MASK                       _MK_MASK_CONST(0x3fff)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_WRITE_MASK                      _MK_MASK_CONST(0x3fff)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_USB1_CLK_OVR_ON_SHIFT                   _MK_SHIFT_CONST(13)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_USB1_CLK_OVR_ON_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_USB1_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_USB1_CLK_OVR_ON_RANGE                   13:13
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_USB1_CLK_OVR_ON_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_USB1_CLK_OVR_ON_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_USB1_CLK_OVR_ON_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_USB1_CLK_OVR_ON_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_USB1_CLK_OVR_ON_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_USB3_CLK_OVR_ON_SHIFT                   _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_USB3_CLK_OVR_ON_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_USB3_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_USB3_CLK_OVR_ON_RANGE                   12:12
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_USB3_CLK_OVR_ON_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_USB3_CLK_OVR_ON_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_USB3_CLK_OVR_ON_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_USB3_CLK_OVR_ON_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_USB3_CLK_OVR_ON_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_AVPC_CLK_OVR_ON_SHIFT                   _MK_SHIFT_CONST(11)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_AVPC_CLK_OVR_ON_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_AVPC_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_AVPC_CLK_OVR_ON_RANGE                   11:11
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_AVPC_CLK_OVR_ON_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_AVPC_CLK_OVR_ON_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_AVPC_CLK_OVR_ON_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_AVPC_CLK_OVR_ON_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_AVPC_CLK_OVR_ON_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_USB2_CLK_OVR_ON_SHIFT                   _MK_SHIFT_CONST(10)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_USB2_CLK_OVR_ON_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_USB2_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_USB2_CLK_OVR_ON_RANGE                   10:10
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_USB2_CLK_OVR_ON_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_USB2_CLK_OVR_ON_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_USB2_CLK_OVR_ON_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_USB2_CLK_OVR_ON_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_USB2_CLK_OVR_ON_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MPEC_CLK_OVR_ON_SHIFT                       _MK_SHIFT_CONST(9)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MPEC_CLK_OVR_ON_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MPEC_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MPEC_CLK_OVR_ON_RANGE                       9:9
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MPEC_CLK_OVR_ON_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MPEC_CLK_OVR_ON_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MPEC_CLK_OVR_ON_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MPEC_CLK_OVR_ON_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MPEC_CLK_OVR_ON_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MPEB_CLK_OVR_ON_SHIFT                       _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MPEB_CLK_OVR_ON_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MPEB_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MPEB_CLK_OVR_ON_RANGE                       8:8
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MPEB_CLK_OVR_ON_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MPEB_CLK_OVR_ON_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MPEB_CLK_OVR_ON_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MPEB_CLK_OVR_ON_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MPEB_CLK_OVR_ON_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_REGS_CLK_OVR_ON_SHIFT                       _MK_SHIFT_CONST(7)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_REGS_CLK_OVR_ON_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_REGS_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_REGS_CLK_OVR_ON_RANGE                       7:7
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_REGS_CLK_OVR_ON_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_REGS_CLK_OVR_ON_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_REGS_CLK_OVR_ON_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_REGS_CLK_OVR_ON_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_REGS_CLK_OVR_ON_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MPEA_CLK_OVR_ON_SHIFT                       _MK_SHIFT_CONST(6)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MPEA_CLK_OVR_ON_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MPEA_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MPEA_CLK_OVR_ON_RANGE                       6:6
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MPEA_CLK_OVR_ON_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MPEA_CLK_OVR_ON_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MPEA_CLK_OVR_ON_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MPEA_CLK_OVR_ON_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MPEA_CLK_OVR_ON_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_PMEM_CLK_OVR_ON_SHIFT                       _MK_SHIFT_CONST(5)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_PMEM_CLK_OVR_ON_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_PMEM_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_PMEM_CLK_OVR_ON_RANGE                       5:5
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_PMEM_CLK_OVR_ON_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_PMEM_CLK_OVR_ON_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_PMEM_CLK_OVR_ON_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_PMEM_CLK_OVR_ON_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_PMEM_CLK_OVR_ON_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_IB_CLK_OVR_ON_SHIFT                 _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_IB_CLK_OVR_ON_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_IB_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_IB_CLK_OVR_ON_RANGE                 4:4
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_IB_CLK_OVR_ON_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_IB_CLK_OVR_ON_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_IB_CLK_OVR_ON_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_IB_CLK_OVR_ON_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_IB_CLK_OVR_ON_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MEMRD_CLK_OVR_ON_SHIFT                      _MK_SHIFT_CONST(3)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MEMRD_CLK_OVR_ON_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MEMRD_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MEMRD_CLK_OVR_ON_RANGE                      3:3
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MEMRD_CLK_OVR_ON_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MEMRD_CLK_OVR_ON_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MEMRD_CLK_OVR_ON_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MEMRD_CLK_OVR_ON_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MEMRD_CLK_OVR_ON_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_RC_CLK_OVR_ON_SHIFT                 _MK_SHIFT_CONST(2)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_RC_CLK_OVR_ON_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_RC_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_RC_CLK_OVR_ON_RANGE                 2:2
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_RC_CLK_OVR_ON_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_RC_CLK_OVR_ON_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_RC_CLK_OVR_ON_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_RC_CLK_OVR_ON_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_RC_CLK_OVR_ON_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_CSI_CLK_OVR_ON_SHIFT                    _MK_SHIFT_CONST(1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_CSI_CLK_OVR_ON_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_CSI_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_CSI_CLK_OVR_ON_RANGE                    1:1
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_CSI_CLK_OVR_ON_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_CSI_CLK_OVR_ON_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_CSI_CLK_OVR_ON_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_CSI_CLK_OVR_ON_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_CSI_CLK_OVR_ON_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_RTC_CLK_OVR_ON_SHIFT                    _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_RTC_CLK_OVR_ON_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_RTC_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_RTC_CLK_OVR_ON_RANGE                    0:0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_RTC_CLK_OVR_ON_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_RTC_CLK_OVR_ON_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_RTC_CLK_OVR_ON_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_RTC_CLK_OVR_ON_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_RTC_CLK_OVR_ON_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0                    _MK_ADDR_CONST(0x100)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_SECURE                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_WORD_COUNT                         0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_RESET_VAL                  _MK_MASK_CONST(0xd0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_RESET_MASK                         _MK_MASK_CONST(0xd00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_READ_MASK                  _MK_MASK_CONST(0xd00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_WRITE_MASK                         _MK_MASK_CONST(0xd00000ff)
+//  00 = pllA_out0
+//  01 = audio SYNC_CLK x 2
+//  10 = pllP_out0
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_SRC_SHIFT                 _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_SRC_FIELD                 (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_SRC_RANGE                 31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_SRC_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_SRC_DEFAULT                       _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_SRC_INIT_ENUM                     CLK_M
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_SRC_PLLA_OUT0                     _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_SRC_SYNC_CLK_X2                   _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_SRC_PLLP_OUT0                     _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_SRC_CLK_M                 _MK_ENUM_CONST(3)
+
+// 1 = enable I2S1 master clock, disable I2S1 master clock.
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_MASTER_CLKEN_SHIFT                    _MK_SHIFT_CONST(28)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_MASTER_CLKEN_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_MASTER_CLKEN_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_MASTER_CLKEN_RANGE                    28:28
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_MASTER_CLKEN_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_MASTER_CLKEN_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_MASTER_CLKEN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_MASTER_CLKEN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_MASTER_CLKEN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+//  N  = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_DIVISOR_SHIFT                     _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_DIVISOR_FIELD                     (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_DIVISOR_RANGE                     7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_DIVISOR_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_DIVISOR_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_DIVISOR_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_DIVISOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_DIVISOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0                    _MK_ADDR_CONST(0x104)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_SECURE                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_WORD_COUNT                         0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_RESET_VAL                  _MK_MASK_CONST(0xd0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_RESET_MASK                         _MK_MASK_CONST(0xd00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_READ_MASK                  _MK_MASK_CONST(0xd00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_WRITE_MASK                         _MK_MASK_CONST(0xd00000ff)
+//  00 = pllA_out0
+//  01 = audio SYNC_CLK x 2
+//  10 = pllP_out0
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_SRC_SHIFT                 _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_SRC_FIELD                 (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_SRC_RANGE                 31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_SRC_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_SRC_DEFAULT                       _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_SRC_INIT_ENUM                     CLK_M
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_SRC_PLLA_OUT0                     _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_SRC_SYNC_CLK_X2                   _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_SRC_PLLP_OUT0                     _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_SRC_CLK_M                 _MK_ENUM_CONST(3)
+
+// 1 = enable I2S2 master clock, disable I2S2 master clock.
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_MASTER_CLKEN_SHIFT                    _MK_SHIFT_CONST(28)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_MASTER_CLKEN_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_MASTER_CLKEN_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_MASTER_CLKEN_RANGE                    28:28
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_MASTER_CLKEN_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_MASTER_CLKEN_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_MASTER_CLKEN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_MASTER_CLKEN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_MASTER_CLKEN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+//  N  = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_DIVISOR_SHIFT                     _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_DIVISOR_FIELD                     (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_DIVISOR_RANGE                     7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_DIVISOR_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_DIVISOR_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_DIVISOR_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_DIVISOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_DIVISOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0                       _MK_ADDR_CONST(0x108)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_SECURE                        0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_WORD_COUNT                    0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_RESET_VAL                     _MK_MASK_CONST(0xc0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_RESET_MASK                    _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_READ_MASK                     _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_WRITE_MASK                    _MK_MASK_CONST(0xc00000ff)
+//  00 = pllA_out0
+//  01 = audio SYNC_CLK x 2
+//  10 = pllP_out0
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_SPDIFOUT_CLK_SRC_SHIFT                        _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_SPDIFOUT_CLK_SRC_FIELD                        (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_SPDIFOUT_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_SPDIFOUT_CLK_SRC_RANGE                        31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_SPDIFOUT_CLK_SRC_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_SPDIFOUT_CLK_SRC_DEFAULT                      _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_SPDIFOUT_CLK_SRC_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_SPDIFOUT_CLK_SRC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_SPDIFOUT_CLK_SRC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_SPDIFOUT_CLK_SRC_INIT_ENUM                    CLK_M
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_SPDIFOUT_CLK_SRC_PLLA_OUT0                    _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_SPDIFOUT_CLK_SRC_SYNC_CLK_X2                  _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_SPDIFOUT_CLK_SRC_PLLP_OUT0                    _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_SPDIFOUT_CLK_SRC_CLK_M                        _MK_ENUM_CONST(3)
+
+//  N  = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_SPDIFOUT_CLK_DIVISOR_SHIFT                    _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_SPDIFOUT_CLK_DIVISOR_FIELD                    (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_SPDIFOUT_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_SPDIFOUT_CLK_DIVISOR_RANGE                    7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_SPDIFOUT_CLK_DIVISOR_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_SPDIFOUT_CLK_DIVISOR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_SPDIFOUT_CLK_DIVISOR_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_SPDIFOUT_CLK_DIVISOR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_SPDIFOUT_CLK_DIVISOR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0                        _MK_ADDR_CONST(0x10c)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_SECURE                         0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_WORD_COUNT                     0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_RESET_MASK                     _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_READ_MASK                      _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_WRITE_MASK                     _MK_MASK_CONST(0xc00000ff)
+//  00 = pllP_out0
+//  01 = pllC_out0
+//  10 = pllM_out0
+//  11 = 1'b0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_SPDIFIN_CLK_SRC_SHIFT                  _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_SPDIFIN_CLK_SRC_FIELD                  (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_SPDIFIN_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_SPDIFIN_CLK_SRC_RANGE                  31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_SPDIFIN_CLK_SRC_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_SPDIFIN_CLK_SRC_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_SPDIFIN_CLK_SRC_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_SPDIFIN_CLK_SRC_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_SPDIFIN_CLK_SRC_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_SPDIFIN_CLK_SRC_INIT_ENUM                      PLLP_OUT0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_SPDIFIN_CLK_SRC_PLLP_OUT0                      _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_SPDIFIN_CLK_SRC_PLLC_OUT0                      _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_SPDIFIN_CLK_SRC_PLLM_OUT0                      _MK_ENUM_CONST(2)
+
+//  N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_SPDIFIN_CLK_DIVISOR_SHIFT                      _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_SPDIFIN_CLK_DIVISOR_FIELD                      (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_SPDIFIN_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_SPDIFIN_CLK_DIVISOR_RANGE                      7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_SPDIFIN_CLK_DIVISOR_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_SPDIFIN_CLK_DIVISOR_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_SPDIFIN_CLK_DIVISOR_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_SPDIFIN_CLK_DIVISOR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_SPDIFIN_CLK_DIVISOR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0                     _MK_ADDR_CONST(0x110)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_SECURE                      0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_WORD_COUNT                  0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_RESET_VAL                   _MK_MASK_CONST(0x30000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_RESET_MASK                  _MK_MASK_CONST(0x700000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_READ_MASK                   _MK_MASK_CONST(0x700000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_WRITE_MASK                  _MK_MASK_CONST(0x700000ff)
+//  000 = pllP_out0
+//  001 = pllC_out0
+//  010 = audio SYNC_CLK x 2
+//  011 = clk_m
+//  100 = clk_s
+#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_PWM_CLK_SRC_SHIFT                   _MK_SHIFT_CONST(28)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_PWM_CLK_SRC_FIELD                   (_MK_MASK_CONST(0x7) << CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_PWM_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_PWM_CLK_SRC_RANGE                   30:28
+#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_PWM_CLK_SRC_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_PWM_CLK_SRC_DEFAULT                 _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_PWM_CLK_SRC_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_PWM_CLK_SRC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_PWM_CLK_SRC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_PWM_CLK_SRC_INIT_ENUM                       CLK_M
+#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_PWM_CLK_SRC_PLLP_OUT0                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_PWM_CLK_SRC_PLLC_OUT0                       _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_PWM_CLK_SRC_SYNC_CLK_X2                     _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_PWM_CLK_SRC_CLK_M                   _MK_ENUM_CONST(3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_PWM_CLK_SRC_CLK_S                   _MK_ENUM_CONST(4)
+
+//  N  = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_PWM_CLK_DIVISOR_SHIFT                       _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_PWM_CLK_DIVISOR_FIELD                       (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_PWM_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_PWM_CLK_DIVISOR_RANGE                       7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_PWM_CLK_DIVISOR_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_PWM_CLK_DIVISOR_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_PWM_CLK_DIVISOR_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_PWM_CLK_DIVISOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_PWM_CLK_DIVISOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0                    _MK_ADDR_CONST(0x114)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SECURE                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_WORD_COUNT                         0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_RESET_VAL                  _MK_MASK_CONST(0xc0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_RESET_MASK                         _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_READ_MASK                  _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_WRITE_MASK                         _MK_MASK_CONST(0xc00000ff)
+//  00 = pllP_out0
+//  01 = pllC_out0
+//  10 = pllM_out0
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_SRC_SHIFT                 _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_SRC_FIELD                 (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_SRC_RANGE                 31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_SRC_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_SRC_DEFAULT                       _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_SRC_INIT_ENUM                     CLK_M
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_SRC_PLLP_OUT0                     _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_SRC_PLLC_OUT0                     _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_SRC_PLLM_OUT0                     _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_SRC_CLK_M                 _MK_ENUM_CONST(3)
+
+//  N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_DIVISOR_SHIFT                     _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_DIVISOR_FIELD                     (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_DIVISOR_RANGE                     7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_DIVISOR_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_DIVISOR_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_DIVISOR_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_DIVISOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_DIVISOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0                    _MK_ADDR_CONST(0x118)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0_SECURE                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0_WORD_COUNT                         0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0_RESET_VAL                  _MK_MASK_CONST(0xc0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0_RESET_MASK                         _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0_READ_MASK                  _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0_WRITE_MASK                         _MK_MASK_CONST(0xc00000ff)
+//  00 = pllP_out0
+//  01 = pllC_out0
+//  10 = pllM_out0
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0_SBC2_CLK_SRC_SHIFT                 _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0_SBC2_CLK_SRC_FIELD                 (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0_SBC2_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0_SBC2_CLK_SRC_RANGE                 31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0_SBC2_CLK_SRC_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0_SBC2_CLK_SRC_DEFAULT                       _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0_SBC2_CLK_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0_SBC2_CLK_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0_SBC2_CLK_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0_SBC2_CLK_SRC_INIT_ENUM                     CLK_M
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0_SBC2_CLK_SRC_PLLP_OUT0                     _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0_SBC2_CLK_SRC_PLLC_OUT0                     _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0_SBC2_CLK_SRC_PLLM_OUT0                     _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0_SBC2_CLK_SRC_CLK_M                 _MK_ENUM_CONST(3)
+
+//  N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0_SBC2_CLK_DIVISOR_SHIFT                     _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0_SBC2_CLK_DIVISOR_FIELD                     (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0_SBC2_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0_SBC2_CLK_DIVISOR_RANGE                     7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0_SBC2_CLK_DIVISOR_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0_SBC2_CLK_DIVISOR_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0_SBC2_CLK_DIVISOR_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0_SBC2_CLK_DIVISOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0_SBC2_CLK_DIVISOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0                    _MK_ADDR_CONST(0x11c)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0_SECURE                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0_WORD_COUNT                         0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0_RESET_VAL                  _MK_MASK_CONST(0xc0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0_RESET_MASK                         _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0_READ_MASK                  _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0_WRITE_MASK                         _MK_MASK_CONST(0xc00000ff)
+//  00 = pllP_out0
+//  01 = pllC_out0
+//  10 = pllM_out0
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0_SBC3_CLK_SRC_SHIFT                 _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0_SBC3_CLK_SRC_FIELD                 (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0_SBC3_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0_SBC3_CLK_SRC_RANGE                 31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0_SBC3_CLK_SRC_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0_SBC3_CLK_SRC_DEFAULT                       _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0_SBC3_CLK_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0_SBC3_CLK_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0_SBC3_CLK_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0_SBC3_CLK_SRC_INIT_ENUM                     CLK_M
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0_SBC3_CLK_SRC_PLLP_OUT0                     _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0_SBC3_CLK_SRC_PLLC_OUT0                     _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0_SBC3_CLK_SRC_PLLM_OUT0                     _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0_SBC3_CLK_SRC_CLK_M                 _MK_ENUM_CONST(3)
+
+//  N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0_SBC3_CLK_DIVISOR_SHIFT                     _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0_SBC3_CLK_DIVISOR_FIELD                     (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0_SBC3_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0_SBC3_CLK_DIVISOR_RANGE                     7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0_SBC3_CLK_DIVISOR_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0_SBC3_CLK_DIVISOR_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0_SBC3_CLK_DIVISOR_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0_SBC3_CLK_DIVISOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0_SBC3_CLK_DIVISOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0                     _MK_ADDR_CONST(0x120)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0_SECURE                      0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0_WORD_COUNT                  0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0_RESET_VAL                   _MK_MASK_CONST(0xc0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0_RESET_MASK                  _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0_READ_MASK                   _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0_WRITE_MASK                  _MK_MASK_CONST(0xc00000ff)
+//  00 = pllP_out0
+//  01 = pllC_out0
+//  10 = pllM_out0
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0_XIO_CLK_SRC_SHIFT                   _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0_XIO_CLK_SRC_FIELD                   (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0_XIO_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0_XIO_CLK_SRC_RANGE                   31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0_XIO_CLK_SRC_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0_XIO_CLK_SRC_DEFAULT                 _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0_XIO_CLK_SRC_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0_XIO_CLK_SRC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0_XIO_CLK_SRC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0_XIO_CLK_SRC_INIT_ENUM                       CLK_M
+#define CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0_XIO_CLK_SRC_PLLP_OUT0                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0_XIO_CLK_SRC_PLLC_OUT0                       _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0_XIO_CLK_SRC_PLLM_OUT0                       _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0_XIO_CLK_SRC_CLK_M                   _MK_ENUM_CONST(3)
+
+//  N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0_XIO_CLK_DIVISOR_SHIFT                       _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0_XIO_CLK_DIVISOR_FIELD                       (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0_XIO_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0_XIO_CLK_DIVISOR_RANGE                       7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0_XIO_CLK_DIVISOR_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0_XIO_CLK_DIVISOR_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0_XIO_CLK_DIVISOR_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0_XIO_CLK_DIVISOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0_XIO_CLK_DIVISOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0                    _MK_ADDR_CONST(0x124)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_SECURE                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_WORD_COUNT                         0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_RESET_VAL                  _MK_MASK_CONST(0xc0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_RESET_MASK                         _MK_MASK_CONST(0xc000ffff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_READ_MASK                  _MK_MASK_CONST(0xc000ffff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_WRITE_MASK                         _MK_MASK_CONST(0xc000ffff)
+//  00 = pllP_out0
+//  01 = pllC_out0
+//  10 = pllM_out0
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_SRC_SHIFT                 _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_SRC_FIELD                 (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_SRC_RANGE                 31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_SRC_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_SRC_DEFAULT                       _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_SRC_INIT_ENUM                     CLK_M
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_SRC_PLLP_OUT0                     _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_SRC_PLLC_OUT0                     _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_SRC_PLLM_OUT0                     _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_SRC_CLK_M                 _MK_ENUM_CONST(3)
+
+//  N = Divide by (n+1) (lsb denote 1.0x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_DIVISOR_SHIFT                     _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_DIVISOR_FIELD                     (_MK_MASK_CONST(0xffff) << CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_DIVISOR_RANGE                     15:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_DIVISOR_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_DIVISOR_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_DIVISOR_DEFAULT_MASK                      _MK_MASK_CONST(0xffff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_DIVISOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_DIVISOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0                 _MK_ADDR_CONST(0x128)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_SECURE                  0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_WORD_COUNT                      0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_RESET_VAL                       _MK_MASK_CONST(0xc0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_RESET_MASK                      _MK_MASK_CONST(0xc000ffff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_READ_MASK                       _MK_MASK_CONST(0xc000ffff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_WRITE_MASK                      _MK_MASK_CONST(0xc000ffff)
+//  00 = pllP_out0
+//  01 = pllC_out0
+//  10 = pllM_out0
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_DVC_I2C_CLK_SRC_SHIFT                   _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_DVC_I2C_CLK_SRC_FIELD                   (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_DVC_I2C_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_DVC_I2C_CLK_SRC_RANGE                   31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_DVC_I2C_CLK_SRC_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_DVC_I2C_CLK_SRC_DEFAULT                 _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_DVC_I2C_CLK_SRC_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_DVC_I2C_CLK_SRC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_DVC_I2C_CLK_SRC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_DVC_I2C_CLK_SRC_INIT_ENUM                       CLK_M
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_DVC_I2C_CLK_SRC_PLLP_OUT0                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_DVC_I2C_CLK_SRC_PLLC_OUT0                       _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_DVC_I2C_CLK_SRC_PLLM_OUT0                       _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_DVC_I2C_CLK_SRC_CLK_M                   _MK_ENUM_CONST(3)
+
+//  N = Divide by (n+1) (lsb denote 1.0x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_DVC_I2C_CLK_DIVISOR_SHIFT                       _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_DVC_I2C_CLK_DIVISOR_FIELD                       (_MK_MASK_CONST(0xffff) << CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_DVC_I2C_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_DVC_I2C_CLK_DIVISOR_RANGE                       15:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_DVC_I2C_CLK_DIVISOR_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_DVC_I2C_CLK_DIVISOR_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_DVC_I2C_CLK_DIVISOR_DEFAULT_MASK                        _MK_MASK_CONST(0xffff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_DVC_I2C_CLK_DIVISOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_DVC_I2C_CLK_DIVISOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0                     _MK_ADDR_CONST(0x12c)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0_SECURE                      0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0_WORD_COUNT                  0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0_RESET_VAL                   _MK_MASK_CONST(0xc0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0_RESET_MASK                  _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0_READ_MASK                   _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0_WRITE_MASK                  _MK_MASK_CONST(0xc00000ff)
+//  00 = pllP_out0
+//  01 = pllC_out0
+//  10 = pllM_out0
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0_TWC_CLK_SRC_SHIFT                   _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0_TWC_CLK_SRC_FIELD                   (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0_TWC_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0_TWC_CLK_SRC_RANGE                   31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0_TWC_CLK_SRC_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0_TWC_CLK_SRC_DEFAULT                 _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0_TWC_CLK_SRC_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0_TWC_CLK_SRC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0_TWC_CLK_SRC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0_TWC_CLK_SRC_INIT_ENUM                       CLK_M
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0_TWC_CLK_SRC_PLLP_OUT0                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0_TWC_CLK_SRC_PLLC_OUT0                       _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0_TWC_CLK_SRC_PLLM_OUT0                       _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0_TWC_CLK_SRC_CLK_M                   _MK_ENUM_CONST(3)
+
+//  N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0_TWC_CLK_DIVISOR_SHIFT                       _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0_TWC_CLK_DIVISOR_FIELD                       (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0_TWC_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0_TWC_CLK_DIVISOR_RANGE                       7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0_TWC_CLK_DIVISOR_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0_TWC_CLK_DIVISOR_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0_TWC_CLK_DIVISOR_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0_TWC_CLK_DIVISOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0_TWC_CLK_DIVISOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Reserved address 304 [0x130] 
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0                    _MK_ADDR_CONST(0x134)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0_SECURE                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0_WORD_COUNT                         0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0_RESET_VAL                  _MK_MASK_CONST(0xc0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0_RESET_MASK                         _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0_READ_MASK                  _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0_WRITE_MASK                         _MK_MASK_CONST(0xc00000ff)
+//  00 = pllP_out0
+//  01 = pllC_out0
+//  10 = pllM_out0
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0_SBC1_CLK_SRC_SHIFT                 _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0_SBC1_CLK_SRC_FIELD                 (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0_SBC1_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0_SBC1_CLK_SRC_RANGE                 31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0_SBC1_CLK_SRC_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0_SBC1_CLK_SRC_DEFAULT                       _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0_SBC1_CLK_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0_SBC1_CLK_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0_SBC1_CLK_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0_SBC1_CLK_SRC_INIT_ENUM                     CLK_M
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0_SBC1_CLK_SRC_PLLP_OUT0                     _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0_SBC1_CLK_SRC_PLLC_OUT0                     _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0_SBC1_CLK_SRC_PLLM_OUT0                     _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0_SBC1_CLK_SRC_CLK_M                 _MK_ENUM_CONST(3)
+
+//  N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0_SBC1_CLK_DIVISOR_SHIFT                     _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0_SBC1_CLK_DIVISOR_FIELD                     (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0_SBC1_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0_SBC1_CLK_DIVISOR_RANGE                     7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0_SBC1_CLK_DIVISOR_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0_SBC1_CLK_DIVISOR_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0_SBC1_CLK_DIVISOR_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0_SBC1_CLK_DIVISOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0_SBC1_CLK_DIVISOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_DISP1_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP1_0                   _MK_ADDR_CONST(0x138)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP1_0_SECURE                    0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP1_0_WORD_COUNT                        0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP1_0_RESET_VAL                         _MK_MASK_CONST(0xc0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP1_0_RESET_MASK                        _MK_MASK_CONST(0xc0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP1_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP1_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP1_0_READ_MASK                         _MK_MASK_CONST(0xc0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP1_0_WRITE_MASK                        _MK_MASK_CONST(0xc0000000)
+//  00 = pllP_out0
+//  01 = pllD_out0
+//  10 = pllC_out0
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP1_0_DISP1_CLK_SRC_SHIFT                       _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP1_0_DISP1_CLK_SRC_FIELD                       (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_DISP1_0_DISP1_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP1_0_DISP1_CLK_SRC_RANGE                       31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP1_0_DISP1_CLK_SRC_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP1_0_DISP1_CLK_SRC_DEFAULT                     _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP1_0_DISP1_CLK_SRC_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP1_0_DISP1_CLK_SRC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP1_0_DISP1_CLK_SRC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP1_0_DISP1_CLK_SRC_INIT_ENUM                   CLK_M
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP1_0_DISP1_CLK_SRC_PLLP_OUT0                   _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP1_0_DISP1_CLK_SRC_PLLD_OUT0                   _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP1_0_DISP1_CLK_SRC_PLLC_OUT0                   _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP1_0_DISP1_CLK_SRC_CLK_M                       _MK_ENUM_CONST(3)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_DISP2_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP2_0                   _MK_ADDR_CONST(0x13c)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP2_0_SECURE                    0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP2_0_WORD_COUNT                        0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP2_0_RESET_VAL                         _MK_MASK_CONST(0xc0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP2_0_RESET_MASK                        _MK_MASK_CONST(0xc0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP2_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP2_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP2_0_READ_MASK                         _MK_MASK_CONST(0xc0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP2_0_WRITE_MASK                        _MK_MASK_CONST(0xc0000000)
+//  00 = pllP_out0
+//  01 = pllD_out0
+//  10 = pllC_out0
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP2_0_DISP2_CLK_SRC_SHIFT                       _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP2_0_DISP2_CLK_SRC_FIELD                       (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_DISP2_0_DISP2_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP2_0_DISP2_CLK_SRC_RANGE                       31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP2_0_DISP2_CLK_SRC_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP2_0_DISP2_CLK_SRC_DEFAULT                     _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP2_0_DISP2_CLK_SRC_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP2_0_DISP2_CLK_SRC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP2_0_DISP2_CLK_SRC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP2_0_DISP2_CLK_SRC_INIT_ENUM                   CLK_M
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP2_0_DISP2_CLK_SRC_PLLP_OUT0                   _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP2_0_DISP2_CLK_SRC_PLLD_OUT0                   _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP2_0_DISP2_CLK_SRC_PLLC_OUT0                   _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP2_0_DISP2_CLK_SRC_CLK_M                       _MK_ENUM_CONST(3)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0                     _MK_ADDR_CONST(0x140)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_SECURE                      0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_WORD_COUNT                  0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_RESET_VAL                   _MK_MASK_CONST(0xc0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_RESET_MASK                  _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_READ_MASK                   _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_WRITE_MASK                  _MK_MASK_CONST(0xc00000ff)
+//  00 = pllP_out0
+//  01 = pllD_out0
+//  10 = pllC_out0
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_CVE_CLK_SRC_SHIFT                   _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_CVE_CLK_SRC_FIELD                   (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_CVE_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_CVE_CLK_SRC_RANGE                   31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_CVE_CLK_SRC_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_CVE_CLK_SRC_DEFAULT                 _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_CVE_CLK_SRC_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_CVE_CLK_SRC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_CVE_CLK_SRC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_CVE_CLK_SRC_INIT_ENUM                       CLK_M
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_CVE_CLK_SRC_PLLP_OUT0                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_CVE_CLK_SRC_PLLD_OUT0                       _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_CVE_CLK_SRC_PLLC_OUT0                       _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_CVE_CLK_SRC_CLK_M                   _MK_ENUM_CONST(3)
+
+//  N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_CVE_CLK_DIVISOR_SHIFT                       _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_CVE_CLK_DIVISOR_FIELD                       (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_CVE_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_CVE_CLK_DIVISOR_RANGE                       7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_CVE_CLK_DIVISOR_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_CVE_CLK_DIVISOR_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_CVE_CLK_DIVISOR_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_CVE_CLK_DIVISOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_CVE_CLK_DIVISOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0                     _MK_ADDR_CONST(0x144)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0_SECURE                      0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0_WORD_COUNT                  0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0_RESET_VAL                   _MK_MASK_CONST(0xc0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0_RESET_MASK                  _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0_READ_MASK                   _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0_WRITE_MASK                  _MK_MASK_CONST(0xc00000ff)
+//  00 = pllP_out0
+//  01 = pllC_out0
+//  10 = pllM_out0
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0_IDE_CLK_SRC_SHIFT                   _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0_IDE_CLK_SRC_FIELD                   (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0_IDE_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0_IDE_CLK_SRC_RANGE                   31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0_IDE_CLK_SRC_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0_IDE_CLK_SRC_DEFAULT                 _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0_IDE_CLK_SRC_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0_IDE_CLK_SRC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0_IDE_CLK_SRC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0_IDE_CLK_SRC_INIT_ENUM                       CLK_M
+#define CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0_IDE_CLK_SRC_PLLP_OUT0                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0_IDE_CLK_SRC_PLLC_OUT0                       _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0_IDE_CLK_SRC_PLLM_OUT0                       _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0_IDE_CLK_SRC_CLK_M                   _MK_ENUM_CONST(3)
+
+//  N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0_IDE_CLK_DIVISOR_SHIFT                       _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0_IDE_CLK_DIVISOR_FIELD                       (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0_IDE_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0_IDE_CLK_DIVISOR_RANGE                       7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0_IDE_CLK_DIVISOR_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0_IDE_CLK_DIVISOR_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0_IDE_CLK_DIVISOR_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0_IDE_CLK_DIVISOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0_IDE_CLK_DIVISOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_VI_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0                      _MK_ADDR_CONST(0x148)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_SECURE                       0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_WORD_COUNT                   0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_RESET_MASK                   _MK_MASK_CONST(0xc30000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_READ_MASK                    _MK_MASK_CONST(0xc30000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_WRITE_MASK                   _MK_MASK_CONST(0xc30000ff)
+//  00 = pllM_out0
+//  01 = pllC_out0
+//  10 = pllP_out0
+//  11 = pllA_out0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SRC_SHIFT                     _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SRC_FIELD                     (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SRC_RANGE                     31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SRC_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SRC_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SRC_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SRC_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SRC_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SRC_INIT_ENUM                 PLLM_OUT0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SRC_PLLM_OUT0                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SRC_PLLC_OUT0                 _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SRC_PLLP_OUT0                 _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SRC_PLLA_OUT0                 _MK_ENUM_CONST(3)
+
+// 0 = pd2vi_clk, 1 = vi_sensor_clk.
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_PD2VI_CLK_SEL_SHIFT                  _MK_SHIFT_CONST(25)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_PD2VI_CLK_SEL_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_PD2VI_CLK_SEL_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_PD2VI_CLK_SEL_RANGE                  25:25
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_PD2VI_CLK_SEL_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_PD2VI_CLK_SEL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_PD2VI_CLK_SEL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_PD2VI_CLK_SEL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_PD2VI_CLK_SEL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// 0 = select internal clock, 1 = select external clock (pd2vi_clk).
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SEL_SHIFT                     _MK_SHIFT_CONST(24)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SEL_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SEL_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SEL_RANGE                     24:24
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SEL_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SEL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SEL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SEL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SEL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SEL_INIT_ENUM                 INTERNAL
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SEL_INTERNAL                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SEL_EXTERNAL                  _MK_ENUM_CONST(1)
+
+//  N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_DIVISOR_SHIFT                 _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_DIVISOR_FIELD                 (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_DIVISOR_RANGE                 7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_DIVISOR_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_DIVISOR_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_DIVISOR_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_DIVISOR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_DIVISOR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Reserved address 332 [0x14c] 
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0                  _MK_ADDR_CONST(0x150)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SECURE                   0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_WORD_COUNT                       0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_RESET_VAL                        _MK_MASK_CONST(0xc0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_RESET_MASK                       _MK_MASK_CONST(0xc08f00ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_READ_MASK                        _MK_MASK_CONST(0xc08f00ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_WRITE_MASK                       _MK_MASK_CONST(0xc08f00ff)
+//  00 = pllP_out0
+//  01 = pllC_out0
+//  10 = pllM_out0
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_CLK_SRC_SHIFT                     _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_CLK_SRC_FIELD                     (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_CLK_SRC_RANGE                     31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_CLK_SRC_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_CLK_SRC_DEFAULT                   _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_CLK_SRC_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_CLK_SRC_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_CLK_SRC_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_CLK_SRC_INIT_ENUM                 CLK_M
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_CLK_SRC_PLLP_OUT0                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_CLK_SRC_PLLC_OUT0                 _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_CLK_SRC_PLLM_OUT0                 _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_CLK_SRC_CLK_M                     _MK_ENUM_CONST(3)
+
+// 1 = use internal feedback clock.
+// 0 = use external feedback clock.
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_INT_FB_SEL_SHIFT                  _MK_SHIFT_CONST(23)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_INT_FB_SEL_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_INT_FB_SEL_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_INT_FB_SEL_RANGE                  23:23
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_INT_FB_SEL_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_INT_FB_SEL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_INT_FB_SEL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_INT_FB_SEL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_INT_FB_SEL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// 16-tap of internal feedback clock delay.
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_INT_FB_DLY_SHIFT                  _MK_SHIFT_CONST(16)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_INT_FB_DLY_FIELD                  (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_INT_FB_DLY_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_INT_FB_DLY_RANGE                  19:16
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_INT_FB_DLY_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_INT_FB_DLY_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_INT_FB_DLY_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_INT_FB_DLY_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_INT_FB_DLY_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_CLK_DIVISOR_SHIFT                 _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_CLK_DIVISOR_FIELD                 (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_CLK_DIVISOR_RANGE                 7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_CLK_DIVISOR_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_CLK_DIVISOR_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_CLK_DIVISOR_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_CLK_DIVISOR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_CLK_DIVISOR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0                  _MK_ADDR_CONST(0x154)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_SECURE                   0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_WORD_COUNT                       0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_RESET_VAL                        _MK_MASK_CONST(0xc0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_RESET_MASK                       _MK_MASK_CONST(0xc08f00ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_READ_MASK                        _MK_MASK_CONST(0xc08f00ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_WRITE_MASK                       _MK_MASK_CONST(0xc08f00ff)
+//  00 = pllP_out0
+//  01 = pllC_out0
+//  10 = pllM_out0
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_SDMMC2_CLK_SRC_SHIFT                     _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_SDMMC2_CLK_SRC_FIELD                     (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_SDMMC2_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_SDMMC2_CLK_SRC_RANGE                     31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_SDMMC2_CLK_SRC_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_SDMMC2_CLK_SRC_DEFAULT                   _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_SDMMC2_CLK_SRC_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_SDMMC2_CLK_SRC_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_SDMMC2_CLK_SRC_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_SDMMC2_CLK_SRC_INIT_ENUM                 CLK_M
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_SDMMC2_CLK_SRC_PLLP_OUT0                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_SDMMC2_CLK_SRC_PLLC_OUT0                 _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_SDMMC2_CLK_SRC_PLLM_OUT0                 _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_SDMMC2_CLK_SRC_CLK_M                     _MK_ENUM_CONST(3)
+
+// 1 = use internal feedback clock.
+// 0 = use external feedback clock.
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_SDMMC2_INT_FB_SEL_SHIFT                  _MK_SHIFT_CONST(23)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_SDMMC2_INT_FB_SEL_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_SDMMC2_INT_FB_SEL_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_SDMMC2_INT_FB_SEL_RANGE                  23:23
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_SDMMC2_INT_FB_SEL_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_SDMMC2_INT_FB_SEL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_SDMMC2_INT_FB_SEL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_SDMMC2_INT_FB_SEL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_SDMMC2_INT_FB_SEL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// 16-tap of internal feedback clock delay.
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_SDMMC2_INT_FB_DLY_SHIFT                  _MK_SHIFT_CONST(16)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_SDMMC2_INT_FB_DLY_FIELD                  (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_SDMMC2_INT_FB_DLY_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_SDMMC2_INT_FB_DLY_RANGE                  19:16
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_SDMMC2_INT_FB_DLY_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_SDMMC2_INT_FB_DLY_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_SDMMC2_INT_FB_DLY_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_SDMMC2_INT_FB_DLY_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_SDMMC2_INT_FB_DLY_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_SDMMC2_CLK_DIVISOR_SHIFT                 _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_SDMMC2_CLK_DIVISOR_FIELD                 (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_SDMMC2_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_SDMMC2_CLK_DIVISOR_RANGE                 7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_SDMMC2_CLK_DIVISOR_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_SDMMC2_CLK_DIVISOR_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_SDMMC2_CLK_DIVISOR_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_SDMMC2_CLK_DIVISOR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_SDMMC2_CLK_DIVISOR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0                     _MK_ADDR_CONST(0x158)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_SECURE                      0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_WORD_COUNT                  0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_RESET_MASK                  _MK_MASK_CONST(0xc000ffff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_READ_MASK                   _MK_MASK_CONST(0xc000ffff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_WRITE_MASK                  _MK_MASK_CONST(0xc000ffff)
+//  00 = pllM_out0
+//  01 = pllC_out0
+//  10 = pllP_out0
+//  11 = pllA_out0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_G3D_CLK_SRC_SHIFT                   _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_G3D_CLK_SRC_FIELD                   (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_G3D_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_G3D_CLK_SRC_RANGE                   31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_G3D_CLK_SRC_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_G3D_CLK_SRC_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_G3D_CLK_SRC_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_G3D_CLK_SRC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_G3D_CLK_SRC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_G3D_CLK_SRC_INIT_ENUM                       PLLM_OUT0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_G3D_CLK_SRC_PLLM_OUT0                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_G3D_CLK_SRC_PLLC_OUT0                       _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_G3D_CLK_SRC_PLLP_OUT0                       _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_G3D_CLK_SRC_PLLA_OUT0                       _MK_ENUM_CONST(3)
+
+//  N = Divide by (n+1) (lsb denote 0.5x)
+//  if all 0's, this idle divisor field will not be use.
+//  for non-zero values, when host1x is idle, this field will be use
+//  instead of G3D_CLK_DIVISOR.
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_G3D_IDLE_DIVISOR_SHIFT                      _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_G3D_IDLE_DIVISOR_FIELD                      (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_G3D_IDLE_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_G3D_IDLE_DIVISOR_RANGE                      15:8
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_G3D_IDLE_DIVISOR_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_G3D_IDLE_DIVISOR_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_G3D_IDLE_DIVISOR_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_G3D_IDLE_DIVISOR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_G3D_IDLE_DIVISOR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+//  N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_G3D_CLK_DIVISOR_SHIFT                       _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_G3D_CLK_DIVISOR_FIELD                       (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_G3D_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_G3D_CLK_DIVISOR_RANGE                       7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_G3D_CLK_DIVISOR_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_G3D_CLK_DIVISOR_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_G3D_CLK_DIVISOR_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_G3D_CLK_DIVISOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_G3D_CLK_DIVISOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0                     _MK_ADDR_CONST(0x15c)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_SECURE                      0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_WORD_COUNT                  0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_RESET_MASK                  _MK_MASK_CONST(0xc000ffff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_READ_MASK                   _MK_MASK_CONST(0xc000ffff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_WRITE_MASK                  _MK_MASK_CONST(0xc000ffff)
+//  00 = pllM_out0
+//  01 = pllC_out0
+//  10 = pllP_out0
+//  11 = pllA_out0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_G2D_CLK_SRC_SHIFT                   _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_G2D_CLK_SRC_FIELD                   (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_G2D_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_G2D_CLK_SRC_RANGE                   31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_G2D_CLK_SRC_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_G2D_CLK_SRC_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_G2D_CLK_SRC_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_G2D_CLK_SRC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_G2D_CLK_SRC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_G2D_CLK_SRC_INIT_ENUM                       PLLM_OUT0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_G2D_CLK_SRC_PLLM_OUT0                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_G2D_CLK_SRC_PLLC_OUT0                       _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_G2D_CLK_SRC_PLLP_OUT0                       _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_G2D_CLK_SRC_PLLA_OUT0                       _MK_ENUM_CONST(3)
+
+//  N = Divide by (n+1) (lsb denote 0.5x)
+//  if all 0's, this idle divisor field will not be use.
+//  for non-zero values, when host1x is idle, this field will be use
+//  instead of G2D_CLK_DIVISOR.
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_G2D_IDLE_DIVISOR_SHIFT                      _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_G2D_IDLE_DIVISOR_FIELD                      (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_G2D_IDLE_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_G2D_IDLE_DIVISOR_RANGE                      15:8
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_G2D_IDLE_DIVISOR_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_G2D_IDLE_DIVISOR_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_G2D_IDLE_DIVISOR_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_G2D_IDLE_DIVISOR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_G2D_IDLE_DIVISOR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+//  N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_G2D_CLK_DIVISOR_SHIFT                       _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_G2D_CLK_DIVISOR_FIELD                       (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_G2D_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_G2D_CLK_DIVISOR_RANGE                       7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_G2D_CLK_DIVISOR_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_G2D_CLK_DIVISOR_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_G2D_CLK_DIVISOR_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_G2D_CLK_DIVISOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_G2D_CLK_DIVISOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0                 _MK_ADDR_CONST(0x160)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_SECURE                  0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_WORD_COUNT                      0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_RESET_VAL                       _MK_MASK_CONST(0xc0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_RESET_MASK                      _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_READ_MASK                       _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_WRITE_MASK                      _MK_MASK_CONST(0xc00000ff)
+// 00 = pllP_out0
+// 01 = pllC_out0
+// 10 = pllM_out0
+// 11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_NDFLASH_CLK_SRC_SHIFT                   _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_NDFLASH_CLK_SRC_FIELD                   (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_NDFLASH_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_NDFLASH_CLK_SRC_RANGE                   31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_NDFLASH_CLK_SRC_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_NDFLASH_CLK_SRC_DEFAULT                 _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_NDFLASH_CLK_SRC_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_NDFLASH_CLK_SRC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_NDFLASH_CLK_SRC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_NDFLASH_CLK_SRC_INIT_ENUM                       CLK_M
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_NDFLASH_CLK_SRC_PLLP_OUT0                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_NDFLASH_CLK_SRC_PLLC_OUT0                       _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_NDFLASH_CLK_SRC_PLLM_OUT0                       _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_NDFLASH_CLK_SRC_CLK_M                   _MK_ENUM_CONST(3)
+
+// N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_NDFLASH_CLK_DIVISOR_SHIFT                       _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_NDFLASH_CLK_DIVISOR_FIELD                       (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_NDFLASH_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_NDFLASH_CLK_DIVISOR_RANGE                       7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_NDFLASH_CLK_DIVISOR_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_NDFLASH_CLK_DIVISOR_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_NDFLASH_CLK_DIVISOR_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_NDFLASH_CLK_DIVISOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_NDFLASH_CLK_DIVISOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0                  _MK_ADDR_CONST(0x164)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SECURE                   0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_WORD_COUNT                       0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_RESET_VAL                        _MK_MASK_CONST(0xc0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_RESET_MASK                       _MK_MASK_CONST(0xc08f00ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_READ_MASK                        _MK_MASK_CONST(0xc08f00ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_WRITE_MASK                       _MK_MASK_CONST(0xc08f00ff)
+// 00 = pllP_out0
+// 01 = pllC_out0
+// 10 = pllM_out0
+// 11 = CLK_M
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_CLK_SRC_SHIFT                     _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_CLK_SRC_FIELD                     (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_CLK_SRC_RANGE                     31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_CLK_SRC_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_CLK_SRC_DEFAULT                   _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_CLK_SRC_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_CLK_SRC_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_CLK_SRC_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_CLK_SRC_INIT_ENUM                 CLK_M
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_CLK_SRC_PLLP_OUT0                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_CLK_SRC_PLLC_OUT0                 _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_CLK_SRC_PLLM_OUT0                 _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_CLK_SRC_CLK_M                     _MK_ENUM_CONST(3)
+
+// 1 = use internal feedback clock.
+// 0 = use external feedback clock.
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_INT_FB_SEL_SHIFT                  _MK_SHIFT_CONST(23)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_INT_FB_SEL_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_INT_FB_SEL_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_INT_FB_SEL_RANGE                  23:23
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_INT_FB_SEL_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_INT_FB_SEL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_INT_FB_SEL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_INT_FB_SEL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_INT_FB_SEL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// 16-tap of internal feedback clock delay.
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_INT_FB_DLY_SHIFT                  _MK_SHIFT_CONST(16)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_INT_FB_DLY_FIELD                  (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_INT_FB_DLY_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_INT_FB_DLY_RANGE                  19:16
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_INT_FB_DLY_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_INT_FB_DLY_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_INT_FB_DLY_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_INT_FB_DLY_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_INT_FB_DLY_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_CLK_DIVISOR_SHIFT                 _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_CLK_DIVISOR_FIELD                 (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_CLK_DIVISOR_RANGE                 7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_CLK_DIVISOR_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_CLK_DIVISOR_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_CLK_DIVISOR_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_CLK_DIVISOR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_CLK_DIVISOR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0                    _MK_ADDR_CONST(0x168)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_SECURE                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_WORD_COUNT                         0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_RESET_VAL                  _MK_MASK_CONST(0xc0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_RESET_MASK                         _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_READ_MASK                  _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_WRITE_MASK                         _MK_MASK_CONST(0xc00000ff)
+// 00 = pllP_out0
+// 01 = pllC_out0
+// 10 = pllM_out0
+// 11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_VFIR_CLK_SRC_SHIFT                 _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_VFIR_CLK_SRC_FIELD                 (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_VFIR_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_VFIR_CLK_SRC_RANGE                 31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_VFIR_CLK_SRC_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_VFIR_CLK_SRC_DEFAULT                       _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_VFIR_CLK_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_VFIR_CLK_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_VFIR_CLK_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_VFIR_CLK_SRC_INIT_ENUM                     CLK_M
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_VFIR_CLK_SRC_PLLP_OUT0                     _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_VFIR_CLK_SRC_PLLC_OUT0                     _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_VFIR_CLK_SRC_PLLM_OUT0                     _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_VFIR_CLK_SRC_CLK_M                 _MK_ENUM_CONST(3)
+
+// N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_VFIR_CLK_DIVISOR_SHIFT                     _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_VFIR_CLK_DIVISOR_FIELD                     (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_VFIR_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_VFIR_CLK_DIVISOR_RANGE                     7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_VFIR_CLK_DIVISOR_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_VFIR_CLK_DIVISOR_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_VFIR_CLK_DIVISOR_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_VFIR_CLK_DIVISOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_VFIR_CLK_DIVISOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0                     _MK_ADDR_CONST(0x16c)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0_SECURE                      0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0_WORD_COUNT                  0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0_RESET_MASK                  _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0_READ_MASK                   _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0_WRITE_MASK                  _MK_MASK_CONST(0xc00000ff)
+//  00 = pllM_out0
+//  01 = pllC_out0
+//  10 = pllP_out0
+//  11 = pllA_out0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0_EPP_CLK_SRC_SHIFT                   _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0_EPP_CLK_SRC_FIELD                   (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0_EPP_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0_EPP_CLK_SRC_RANGE                   31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0_EPP_CLK_SRC_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0_EPP_CLK_SRC_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0_EPP_CLK_SRC_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0_EPP_CLK_SRC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0_EPP_CLK_SRC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0_EPP_CLK_SRC_INIT_ENUM                       PLLM_OUT0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0_EPP_CLK_SRC_PLLM_OUT0                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0_EPP_CLK_SRC_PLLC_OUT0                       _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0_EPP_CLK_SRC_PLLP_OUT0                       _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0_EPP_CLK_SRC_PLLA_OUT0                       _MK_ENUM_CONST(3)
+
+//  N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0_EPP_CLK_DIVISOR_SHIFT                       _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0_EPP_CLK_DIVISOR_FIELD                       (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0_EPP_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0_EPP_CLK_DIVISOR_RANGE                       7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0_EPP_CLK_DIVISOR_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0_EPP_CLK_DIVISOR_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0_EPP_CLK_DIVISOR_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0_EPP_CLK_DIVISOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0_EPP_CLK_DIVISOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0                     _MK_ADDR_CONST(0x170)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0_SECURE                      0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0_WORD_COUNT                  0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0_RESET_MASK                  _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0_READ_MASK                   _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0_WRITE_MASK                  _MK_MASK_CONST(0xc00000ff)
+//  00 = pllM_out0
+//  01 = pllC_out0
+//  10 = pllP_out0
+//  11 = pllA_out0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0_MPE_CLK_SRC_SHIFT                   _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0_MPE_CLK_SRC_FIELD                   (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0_MPE_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0_MPE_CLK_SRC_RANGE                   31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0_MPE_CLK_SRC_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0_MPE_CLK_SRC_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0_MPE_CLK_SRC_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0_MPE_CLK_SRC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0_MPE_CLK_SRC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0_MPE_CLK_SRC_INIT_ENUM                       PLLM_out0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0_MPE_CLK_SRC_PLLM_OUT0                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0_MPE_CLK_SRC_PLLC_OUT0                       _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0_MPE_CLK_SRC_PLLP_OUT0                       _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0_MPE_CLK_SRC_PLLA_OUT0                       _MK_ENUM_CONST(3)
+
+//  N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0_MPE_CLK_DIVISOR_SHIFT                       _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0_MPE_CLK_DIVISOR_FIELD                       (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0_MPE_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0_MPE_CLK_DIVISOR_RANGE                       7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0_MPE_CLK_DIVISOR_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0_MPE_CLK_DIVISOR_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0_MPE_CLK_DIVISOR_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0_MPE_CLK_DIVISOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0_MPE_CLK_DIVISOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0                    _MK_ADDR_CONST(0x174)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0_SECURE                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0_WORD_COUNT                         0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0_RESET_VAL                  _MK_MASK_CONST(0xc0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0_RESET_MASK                         _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0_READ_MASK                  _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0_WRITE_MASK                         _MK_MASK_CONST(0xc00000ff)
+//  00 = pllP_out0
+//  01 = pllC_out0
+//  10 = pllM_out0
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0_MIPI_CLK_SRC_SHIFT                 _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0_MIPI_CLK_SRC_FIELD                 (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0_MIPI_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0_MIPI_CLK_SRC_RANGE                 31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0_MIPI_CLK_SRC_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0_MIPI_CLK_SRC_DEFAULT                       _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0_MIPI_CLK_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0_MIPI_CLK_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0_MIPI_CLK_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0_MIPI_CLK_SRC_INIT_ENUM                     CLK_M
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0_MIPI_CLK_SRC_PLLP_OUT0                     _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0_MIPI_CLK_SRC_PLLC_OUT0                     _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0_MIPI_CLK_SRC_PLLM_OUT0                     _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0_MIPI_CLK_SRC_CLK_M                 _MK_ENUM_CONST(3)
+
+//  N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0_MIPI_CLK_DIVISOR_SHIFT                     _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0_MIPI_CLK_DIVISOR_FIELD                     (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0_MIPI_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0_MIPI_CLK_DIVISOR_RANGE                     7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0_MIPI_CLK_DIVISOR_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0_MIPI_CLK_DIVISOR_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0_MIPI_CLK_DIVISOR_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0_MIPI_CLK_DIVISOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0_MIPI_CLK_DIVISOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0                   _MK_ADDR_CONST(0x178)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_SECURE                    0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_WORD_COUNT                        0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_RESET_VAL                         _MK_MASK_CONST(0xc0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_RESET_MASK                        _MK_MASK_CONST(0xc0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_READ_MASK                         _MK_MASK_CONST(0xc0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_WRITE_MASK                        _MK_MASK_CONST(0xc0000000)
+//  00 = pllP_out0
+//  01 = pllC_out0
+//  10 = pllM_out0
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_SRC_SHIFT                       _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_SRC_FIELD                       (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_SRC_RANGE                       31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_SRC_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_SRC_DEFAULT                     _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_SRC_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_SRC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_SRC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_SRC_INIT_ENUM                   CLK_M
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_SRC_PLLP_OUT0                   _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_SRC_PLLC_OUT0                   _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_SRC_PLLM_OUT0                   _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_SRC_CLK_M                       _MK_ENUM_CONST(3)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0                   _MK_ADDR_CONST(0x17c)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_SECURE                    0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_WORD_COUNT                        0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_RESET_VAL                         _MK_MASK_CONST(0xc0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_RESET_MASK                        _MK_MASK_CONST(0xc0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_READ_MASK                         _MK_MASK_CONST(0xc0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_WRITE_MASK                        _MK_MASK_CONST(0xc0000000)
+//  00 = pllP_out0
+//  01 = pllC_out0
+//  10 = pllM_out0
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_CLK_SRC_SHIFT                       _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_CLK_SRC_FIELD                       (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_CLK_SRC_RANGE                       31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_CLK_SRC_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_CLK_SRC_DEFAULT                     _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_CLK_SRC_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_CLK_SRC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_CLK_SRC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_CLK_SRC_INIT_ENUM                   CLK_M
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_CLK_SRC_PLLP_OUT0                   _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_CLK_SRC_PLLC_OUT0                   _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_CLK_SRC_PLLM_OUT0                   _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_CLK_SRC_CLK_M                       _MK_ENUM_CONST(3)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0                  _MK_ADDR_CONST(0x180)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_SECURE                   0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_WORD_COUNT                       0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_RESET_MASK                       _MK_MASK_CONST(0xc000ffff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_READ_MASK                        _MK_MASK_CONST(0xc000ffff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_WRITE_MASK                       _MK_MASK_CONST(0xc000ffff)
+//  00 = pllM_out0
+//  01 = pllC_out0
+//  10 = pllP_out0
+//  11 = pllA_out0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_SRC_SHIFT                     _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_SRC_FIELD                     (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_SRC_RANGE                     31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_SRC_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_SRC_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_SRC_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_SRC_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_SRC_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_SRC_INIT_ENUM                 PLLM_OUT0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_SRC_PLLM_OUT0                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_SRC_PLLC_OUT0                 _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_SRC_PLLP_OUT0                 _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_SRC_PLLA_OUT0                 _MK_ENUM_CONST(3)
+
+//  N = Divide by (n+1) (lsb denote 0.5x)
+//  if all 0's, this idle divisor field will not be use.
+//  for non-zero values, when host1x is idle, this field will be use
+//  instead of HOST1X_CLK_DIVISOR.
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_IDLE_DIVISOR_SHIFT                        _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_IDLE_DIVISOR_FIELD                        (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_IDLE_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_IDLE_DIVISOR_RANGE                        15:8
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_IDLE_DIVISOR_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_IDLE_DIVISOR_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_IDLE_DIVISOR_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_IDLE_DIVISOR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_IDLE_DIVISOR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+//  N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_DIVISOR_SHIFT                 _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_DIVISOR_FIELD                 (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_DIVISOR_RANGE                 7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_DIVISOR_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_DIVISOR_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_DIVISOR_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_DIVISOR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_DIVISOR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Reserved address 388 [0x184] 
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0                     _MK_ADDR_CONST(0x188)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_SECURE                      0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_WORD_COUNT                  0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_RESET_VAL                   _MK_MASK_CONST(0xc0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_RESET_MASK                  _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_READ_MASK                   _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_WRITE_MASK                  _MK_MASK_CONST(0xc00000ff)
+//  00 = pllP_out0
+//  01 = pllD_out0
+//  10 = pllC_out0
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_TVO_CLK_SRC_SHIFT                   _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_TVO_CLK_SRC_FIELD                   (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_TVO_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_TVO_CLK_SRC_RANGE                   31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_TVO_CLK_SRC_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_TVO_CLK_SRC_DEFAULT                 _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_TVO_CLK_SRC_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_TVO_CLK_SRC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_TVO_CLK_SRC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_TVO_CLK_SRC_INIT_ENUM                       CLK_M
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_TVO_CLK_SRC_PLLP_OUT0                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_TVO_CLK_SRC_PLLD_OUT0                       _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_TVO_CLK_SRC_PLLC_OUT0                       _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_TVO_CLK_SRC_CLK_M                   _MK_ENUM_CONST(3)
+
+//  N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_TVO_CLK_DIVISOR_SHIFT                       _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_TVO_CLK_DIVISOR_FIELD                       (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_TVO_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_TVO_CLK_DIVISOR_RANGE                       7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_TVO_CLK_DIVISOR_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_TVO_CLK_DIVISOR_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_TVO_CLK_DIVISOR_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_TVO_CLK_DIVISOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_TVO_CLK_DIVISOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0                    _MK_ADDR_CONST(0x18c)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0_SECURE                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0_WORD_COUNT                         0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0_RESET_VAL                  _MK_MASK_CONST(0xc0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0_RESET_MASK                         _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0_READ_MASK                  _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0_WRITE_MASK                         _MK_MASK_CONST(0xc00000ff)
+//  00 = pllP_out0
+//  01 = pllD_out0
+//  10 = pllC_out0
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0_HDMI_CLK_SRC_SHIFT                 _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0_HDMI_CLK_SRC_FIELD                 (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0_HDMI_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0_HDMI_CLK_SRC_RANGE                 31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0_HDMI_CLK_SRC_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0_HDMI_CLK_SRC_DEFAULT                       _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0_HDMI_CLK_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0_HDMI_CLK_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0_HDMI_CLK_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0_HDMI_CLK_SRC_INIT_ENUM                     CLK_M
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0_HDMI_CLK_SRC_PLLP_OUT0                     _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0_HDMI_CLK_SRC_PLLD_OUT0                     _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0_HDMI_CLK_SRC_PLLC_OUT0                     _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0_HDMI_CLK_SRC_CLK_M                 _MK_ENUM_CONST(3)
+
+//  N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0_HDMI_CLK_DIVISOR_SHIFT                     _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0_HDMI_CLK_DIVISOR_FIELD                     (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0_HDMI_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0_HDMI_CLK_DIVISOR_RANGE                     7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0_HDMI_CLK_DIVISOR_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0_HDMI_CLK_DIVISOR_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0_HDMI_CLK_DIVISOR_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0_HDMI_CLK_DIVISOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0_HDMI_CLK_DIVISOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Reserved address 400 [0x190] 
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0                   _MK_ADDR_CONST(0x194)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_SECURE                    0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_WORD_COUNT                        0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_RESET_VAL                         _MK_MASK_CONST(0xc0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_RESET_MASK                        _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_READ_MASK                         _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_WRITE_MASK                        _MK_MASK_CONST(0xc00000ff)
+//  00 = pllP_out0
+//  01 = pllD_out0
+//  10 = pllC_out0
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_TVDAC_CLK_SRC_SHIFT                       _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_TVDAC_CLK_SRC_FIELD                       (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_TVDAC_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_TVDAC_CLK_SRC_RANGE                       31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_TVDAC_CLK_SRC_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_TVDAC_CLK_SRC_DEFAULT                     _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_TVDAC_CLK_SRC_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_TVDAC_CLK_SRC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_TVDAC_CLK_SRC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_TVDAC_CLK_SRC_INIT_ENUM                   CLK_M
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_TVDAC_CLK_SRC_PLLP_OUT0                   _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_TVDAC_CLK_SRC_PLLD_OUT0                   _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_TVDAC_CLK_SRC_PLLC_OUT0                   _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_TVDAC_CLK_SRC_CLK_M                       _MK_ENUM_CONST(3)
+
+//  N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_TVDAC_CLK_DIVISOR_SHIFT                   _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_TVDAC_CLK_DIVISOR_FIELD                   (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_TVDAC_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_TVDAC_CLK_DIVISOR_RANGE                   7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_TVDAC_CLK_DIVISOR_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_TVDAC_CLK_DIVISOR_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_TVDAC_CLK_DIVISOR_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_TVDAC_CLK_DIVISOR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_TVDAC_CLK_DIVISOR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0                    _MK_ADDR_CONST(0x198)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_SECURE                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_WORD_COUNT                         0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_RESET_VAL                  _MK_MASK_CONST(0xc0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_RESET_MASK                         _MK_MASK_CONST(0xc000ffff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_READ_MASK                  _MK_MASK_CONST(0xc000ffff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_WRITE_MASK                         _MK_MASK_CONST(0xc000ffff)
+//  00 = pllP_out0
+//  01 = pllC_out0
+//  10 = pllM_out0
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_SRC_SHIFT                 _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_SRC_FIELD                 (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_SRC_RANGE                 31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_SRC_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_SRC_DEFAULT                       _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_SRC_INIT_ENUM                     CLK_M
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_SRC_PLLP_OUT0                     _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_SRC_PLLC_OUT0                     _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_SRC_PLLM_OUT0                     _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_SRC_CLK_M                 _MK_ENUM_CONST(3)
+
+//  N = Divide by (n+1) (lsb denote 1.0x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_DIVISOR_SHIFT                     _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_DIVISOR_FIELD                     (_MK_MASK_CONST(0xffff) << CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_DIVISOR_RANGE                     15:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_DIVISOR_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_DIVISOR_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_DIVISOR_DEFAULT_MASK                      _MK_MASK_CONST(0xffff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_DIVISOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_DIVISOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0                     _MK_ADDR_CONST(0x19c)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_SECURE                      0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_WORD_COUNT                  0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_RESET_VAL                   _MK_MASK_CONST(0xc0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_RESET_MASK                  _MK_MASK_CONST(0xe30000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_READ_MASK                   _MK_MASK_CONST(0xe30000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_WRITE_MASK                  _MK_MASK_CONST(0xe30000ff)
+// 00 = pllM_out0
+// 01 = pllC_out0
+// 10 = pllP_out0
+// 11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_SRC_SHIFT                        _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_SRC_FIELD                        (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_SRC_RANGE                        31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_SRC_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_SRC_DEFAULT                      _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_SRC_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_SRC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_SRC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_SRC_INIT_ENUM                    CLK_M
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_SRC_PLLM_OUT0                    _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_SRC_PLLC_OUT0                    _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_SRC_PLLP_OUT0                    _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_SRC_CLK_M                        _MK_ENUM_CONST(3)
+
+// 1 = use un-divided PllM_out0 as clock source.
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_USE_PLLM_UD_SHIFT                   _MK_SHIFT_CONST(29)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_USE_PLLM_UD_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_USE_PLLM_UD_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_USE_PLLM_UD_RANGE                   29:29
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_USE_PLLM_UD_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_USE_PLLM_UD_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_USE_PLLM_UD_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_USE_PLLM_UD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_USE_PLLM_UD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+//  1 = enable EMC 2X clock.
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_ENB_SHIFT                        _MK_SHIFT_CONST(25)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_ENB_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_ENB_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_ENB_RANGE                        25:25
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_ENB_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_ENB_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_ENB_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_ENB_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_ENB_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_ENB_INIT_ENUM                    DISABLE
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_ENB_DISABLE                      _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_ENB_ENABLE                       _MK_ENUM_CONST(1)
+
+//  1 = enable EMC 1X clock.
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_1X_CLK_ENB_SHIFT                        _MK_SHIFT_CONST(24)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_1X_CLK_ENB_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_1X_CLK_ENB_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_1X_CLK_ENB_RANGE                        24:24
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_1X_CLK_ENB_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_1X_CLK_ENB_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_1X_CLK_ENB_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_1X_CLK_ENB_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_1X_CLK_ENB_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_1X_CLK_ENB_INIT_ENUM                    DISABLE
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_1X_CLK_ENB_DISABLE                      _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_1X_CLK_ENB_ENABLE                       _MK_ENUM_CONST(1)
+
+//  N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_DIVISOR_SHIFT                    _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_DIVISOR_FIELD                    (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_DIVISOR_RANGE                    7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_DIVISOR_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_DIVISOR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_DIVISOR_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_DIVISOR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_DIVISOR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0                   _MK_ADDR_CONST(0x1a0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_SECURE                    0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_WORD_COUNT                        0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_RESET_VAL                         _MK_MASK_CONST(0xc0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_RESET_MASK                        _MK_MASK_CONST(0xc0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_READ_MASK                         _MK_MASK_CONST(0xc0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_WRITE_MASK                        _MK_MASK_CONST(0xc0000000)
+//  00 = pllP_out0
+//  01 = pllC_out0
+//  10 = pllM_out0
+//  11 = CLK_M
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_SRC_SHIFT                       _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_SRC_FIELD                       (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_SRC_RANGE                       31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_SRC_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_SRC_DEFAULT                     _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_SRC_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_SRC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_SRC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_SRC_INIT_ENUM                   CLK_M
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_SRC_PLLP_OUT0                   _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_SRC_PLLC_OUT0                   _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_SRC_PLLM_OUT0                   _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_SRC_CLK_M                       _MK_ENUM_CONST(3)
+
+
+// Reserved address 420 [0x1a4] 
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0                       _MK_ADDR_CONST(0x1a8)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_SECURE                        0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_WORD_COUNT                    0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_RESET_MASK                    _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_READ_MASK                     _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_WRITE_MASK                    _MK_MASK_CONST(0xc00000ff)
+//  00 = pllM_out0
+//  01 = pllC_out0
+//  10 = pllP_out0
+//  11 = pllA_out0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_VI_SENSOR_CLK_SRC_SHIFT                       _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_VI_SENSOR_CLK_SRC_FIELD                       (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_VI_SENSOR_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_VI_SENSOR_CLK_SRC_RANGE                       31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_VI_SENSOR_CLK_SRC_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_VI_SENSOR_CLK_SRC_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_VI_SENSOR_CLK_SRC_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_VI_SENSOR_CLK_SRC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_VI_SENSOR_CLK_SRC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_VI_SENSOR_CLK_SRC_INIT_ENUM                   PLLM_OUT0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_VI_SENSOR_CLK_SRC_PLLM_OUT0                   _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_VI_SENSOR_CLK_SRC_PLLC_OUT0                   _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_VI_SENSOR_CLK_SRC_PLLP_OUT0                   _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_VI_SENSOR_CLK_SRC_PLLA_OUT0                   _MK_ENUM_CONST(3)
+
+//  N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_VI_SENSOR_CLK_DIVISOR_SHIFT                   _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_VI_SENSOR_CLK_DIVISOR_FIELD                   (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_VI_SENSOR_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_VI_SENSOR_CLK_DIVISOR_RANGE                   7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_VI_SENSOR_CLK_DIVISOR_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_VI_SENSOR_CLK_DIVISOR_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_VI_SENSOR_CLK_DIVISOR_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_VI_SENSOR_CLK_DIVISOR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_VI_SENSOR_CLK_DIVISOR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Reserved address 428 [0x1ac] 
+
+// Reserved address 432 [0x1b0] 
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_SBC4_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC4_0                    _MK_ADDR_CONST(0x1b4)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC4_0_SECURE                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC4_0_WORD_COUNT                         0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC4_0_RESET_VAL                  _MK_MASK_CONST(0xc0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC4_0_RESET_MASK                         _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC4_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC4_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC4_0_READ_MASK                  _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC4_0_WRITE_MASK                         _MK_MASK_CONST(0xc00000ff)
+//  00 = pllP_out0
+//  01 = pllC_out0
+//  10 = pllM_out0
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC4_0_SBC4_CLK_SRC_SHIFT                 _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC4_0_SBC4_CLK_SRC_FIELD                 (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_SBC4_0_SBC4_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC4_0_SBC4_CLK_SRC_RANGE                 31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC4_0_SBC4_CLK_SRC_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC4_0_SBC4_CLK_SRC_DEFAULT                       _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC4_0_SBC4_CLK_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC4_0_SBC4_CLK_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC4_0_SBC4_CLK_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC4_0_SBC4_CLK_SRC_INIT_ENUM                     CLK_M
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC4_0_SBC4_CLK_SRC_PLLP_OUT0                     _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC4_0_SBC4_CLK_SRC_PLLC_OUT0                     _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC4_0_SBC4_CLK_SRC_PLLM_OUT0                     _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC4_0_SBC4_CLK_SRC_CLK_M                 _MK_ENUM_CONST(3)
+
+//  N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC4_0_SBC4_CLK_DIVISOR_SHIFT                     _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC4_0_SBC4_CLK_DIVISOR_FIELD                     (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_SBC4_0_SBC4_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC4_0_SBC4_CLK_DIVISOR_RANGE                     7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC4_0_SBC4_CLK_DIVISOR_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC4_0_SBC4_CLK_DIVISOR_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC4_0_SBC4_CLK_DIVISOR_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC4_0_SBC4_CLK_DIVISOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC4_0_SBC4_CLK_DIVISOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0                    _MK_ADDR_CONST(0x1b8)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_SECURE                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_WORD_COUNT                         0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_RESET_VAL                  _MK_MASK_CONST(0xc0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_RESET_MASK                         _MK_MASK_CONST(0xc000ffff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_READ_MASK                  _MK_MASK_CONST(0xc000ffff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_WRITE_MASK                         _MK_MASK_CONST(0xc000ffff)
+//  00 = pllP_out0
+//  01 = pllC_out0
+//  10 = pllM_out0
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_I2C3_CLK_SRC_SHIFT                 _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_I2C3_CLK_SRC_FIELD                 (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_I2C3_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_I2C3_CLK_SRC_RANGE                 31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_I2C3_CLK_SRC_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_I2C3_CLK_SRC_DEFAULT                       _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_I2C3_CLK_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_I2C3_CLK_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_I2C3_CLK_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_I2C3_CLK_SRC_INIT_ENUM                     CLK_M
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_I2C3_CLK_SRC_PLLP_OUT0                     _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_I2C3_CLK_SRC_PLLC_OUT0                     _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_I2C3_CLK_SRC_PLLM_OUT0                     _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_I2C3_CLK_SRC_CLK_M                 _MK_ENUM_CONST(3)
+
+//  N = Divide by (n+1) (lsb denote 1.0x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_I2C3_CLK_DIVISOR_SHIFT                     _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_I2C3_CLK_DIVISOR_FIELD                     (_MK_MASK_CONST(0xffff) << CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_I2C3_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_I2C3_CLK_DIVISOR_RANGE                     15:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_I2C3_CLK_DIVISOR_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_I2C3_CLK_DIVISOR_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_I2C3_CLK_DIVISOR_DEFAULT_MASK                      _MK_MASK_CONST(0xffff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_I2C3_CLK_DIVISOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_I2C3_CLK_DIVISOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0                  _MK_ADDR_CONST(0x1bc)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SECURE                   0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_WORD_COUNT                       0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_RESET_VAL                        _MK_MASK_CONST(0xc0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_RESET_MASK                       _MK_MASK_CONST(0xc08f00ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_READ_MASK                        _MK_MASK_CONST(0xc08f00ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_WRITE_MASK                       _MK_MASK_CONST(0xc08f00ff)
+//  00 = pllP_out0
+//  01 = pllC_out0
+//  10 = pllM_out0
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_CLK_SRC_SHIFT                     _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_CLK_SRC_FIELD                     (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_CLK_SRC_RANGE                     31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_CLK_SRC_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_CLK_SRC_DEFAULT                   _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_CLK_SRC_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_CLK_SRC_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_CLK_SRC_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_CLK_SRC_INIT_ENUM                 CLK_M
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_CLK_SRC_PLLP_OUT0                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_CLK_SRC_PLLC_OUT0                 _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_CLK_SRC_PLLM_OUT0                 _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_CLK_SRC_CLK_M                     _MK_ENUM_CONST(3)
+
+// 1 = use internal feedback clock.
+// 0 = use external feedback clock.
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_INT_FB_SEL_SHIFT                  _MK_SHIFT_CONST(23)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_INT_FB_SEL_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_INT_FB_SEL_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_INT_FB_SEL_RANGE                  23:23
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_INT_FB_SEL_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_INT_FB_SEL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_INT_FB_SEL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_INT_FB_SEL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_INT_FB_SEL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// 16-tap of internal feedback clock delay.
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_INT_FB_DLY_SHIFT                  _MK_SHIFT_CONST(16)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_INT_FB_DLY_FIELD                  (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_INT_FB_DLY_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_INT_FB_DLY_RANGE                  19:16
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_INT_FB_DLY_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_INT_FB_DLY_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_INT_FB_DLY_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_INT_FB_DLY_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_INT_FB_DLY_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_CLK_DIVISOR_SHIFT                 _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_CLK_DIVISOR_FIELD                 (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_CLK_DIVISOR_RANGE                 7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_CLK_DIVISOR_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_CLK_DIVISOR_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_CLK_DIVISOR_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_CLK_DIVISOR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_CLK_DIVISOR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0                   _MK_ADDR_CONST(0x1c0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_SECURE                    0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_WORD_COUNT                        0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_RESET_VAL                         _MK_MASK_CONST(0xc0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_RESET_MASK                        _MK_MASK_CONST(0xc0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_READ_MASK                         _MK_MASK_CONST(0xc0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_WRITE_MASK                        _MK_MASK_CONST(0xc0000000)
+//  00 = pllP_out0
+//  01 = pllC_out0
+//  10 = pllM_out0
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_CLK_SRC_SHIFT                       _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_CLK_SRC_FIELD                       (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_CLK_SRC_RANGE                       31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_CLK_SRC_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_CLK_SRC_DEFAULT                     _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_CLK_SRC_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_CLK_SRC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_CLK_SRC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_CLK_SRC_INIT_ENUM                   CLK_M
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_CLK_SRC_PLLP_OUT0                   _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_CLK_SRC_PLLC_OUT0                   _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_CLK_SRC_PLLM_OUT0                   _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_CLK_SRC_CLK_M                       _MK_ENUM_CONST(3)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0                   _MK_ADDR_CONST(0x1c4)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_SECURE                    0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_WORD_COUNT                        0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_RESET_VAL                         _MK_MASK_CONST(0xc0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_RESET_MASK                        _MK_MASK_CONST(0xc0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_READ_MASK                         _MK_MASK_CONST(0xc0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_WRITE_MASK                        _MK_MASK_CONST(0xc0000000)
+//  00 = pllP_out0
+//  01 = pllC_out0
+//  10 = pllM_out0
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_UARTE_CLK_SRC_SHIFT                       _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_UARTE_CLK_SRC_FIELD                       (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_UARTE_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_UARTE_CLK_SRC_RANGE                       31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_UARTE_CLK_SRC_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_UARTE_CLK_SRC_DEFAULT                     _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_UARTE_CLK_SRC_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_UARTE_CLK_SRC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_UARTE_CLK_SRC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_UARTE_CLK_SRC_INIT_ENUM                   CLK_M
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_UARTE_CLK_SRC_PLLP_OUT0                   _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_UARTE_CLK_SRC_PLLC_OUT0                   _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_UARTE_CLK_SRC_PLLM_OUT0                   _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_UARTE_CLK_SRC_CLK_M                       _MK_ENUM_CONST(3)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_VDE_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VDE_0                     _MK_ADDR_CONST(0x1c8)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VDE_0_SECURE                      0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VDE_0_WORD_COUNT                  0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VDE_0_RESET_VAL                   _MK_MASK_CONST(0xc0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VDE_0_RESET_MASK                  _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VDE_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VDE_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VDE_0_READ_MASK                   _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VDE_0_WRITE_MASK                  _MK_MASK_CONST(0xc00000ff)
+//  00 = pllP_out0
+//  01 = pllC_out0
+//  10 = pllM_out0
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VDE_0_VDE_CLK_SRC_SHIFT                   _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VDE_0_VDE_CLK_SRC_FIELD                   (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_VDE_0_VDE_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VDE_0_VDE_CLK_SRC_RANGE                   31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VDE_0_VDE_CLK_SRC_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VDE_0_VDE_CLK_SRC_DEFAULT                 _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VDE_0_VDE_CLK_SRC_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VDE_0_VDE_CLK_SRC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VDE_0_VDE_CLK_SRC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VDE_0_VDE_CLK_SRC_INIT_ENUM                       CLK_M
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VDE_0_VDE_CLK_SRC_PLLP_OUT0                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VDE_0_VDE_CLK_SRC_PLLC_OUT0                       _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VDE_0_VDE_CLK_SRC_PLLM_OUT0                       _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VDE_0_VDE_CLK_SRC_CLK_M                   _MK_ENUM_CONST(3)
+
+//  N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VDE_0_VDE_CLK_DIVISOR_SHIFT                       _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VDE_0_VDE_CLK_DIVISOR_FIELD                       (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_VDE_0_VDE_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VDE_0_VDE_CLK_DIVISOR_RANGE                       7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VDE_0_VDE_CLK_DIVISOR_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VDE_0_VDE_CLK_DIVISOR_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VDE_0_VDE_CLK_DIVISOR_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VDE_0_VDE_CLK_DIVISOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VDE_0_VDE_CLK_DIVISOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_OWR_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_OWR_0                     _MK_ADDR_CONST(0x1cc)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_OWR_0_SECURE                      0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_OWR_0_WORD_COUNT                  0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_OWR_0_RESET_VAL                   _MK_MASK_CONST(0xc0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_OWR_0_RESET_MASK                  _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_OWR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_OWR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_OWR_0_READ_MASK                   _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_OWR_0_WRITE_MASK                  _MK_MASK_CONST(0xc00000ff)
+//  00 = pllP_out0
+//  01 = pllC_out0
+//  10 = pllM_out0
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_OWR_0_OWR_CLK_SRC_SHIFT                   _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_OWR_0_OWR_CLK_SRC_FIELD                   (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_OWR_0_OWR_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_OWR_0_OWR_CLK_SRC_RANGE                   31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_OWR_0_OWR_CLK_SRC_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_OWR_0_OWR_CLK_SRC_DEFAULT                 _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_OWR_0_OWR_CLK_SRC_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_OWR_0_OWR_CLK_SRC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_OWR_0_OWR_CLK_SRC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_OWR_0_OWR_CLK_SRC_INIT_ENUM                       CLK_M
+#define CLK_RST_CONTROLLER_CLK_SOURCE_OWR_0_OWR_CLK_SRC_PLLP_OUT0                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_OWR_0_OWR_CLK_SRC_PLLC_OUT0                       _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_OWR_0_OWR_CLK_SRC_PLLM_OUT0                       _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_OWR_0_OWR_CLK_SRC_CLK_M                   _MK_ENUM_CONST(3)
+
+//  N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_OWR_0_OWR_CLK_DIVISOR_SHIFT                       _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_OWR_0_OWR_CLK_DIVISOR_FIELD                       (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_OWR_0_OWR_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_OWR_0_OWR_CLK_DIVISOR_RANGE                       7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_OWR_0_OWR_CLK_DIVISOR_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_OWR_0_OWR_CLK_DIVISOR_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_OWR_0_OWR_CLK_DIVISOR_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_OWR_0_OWR_CLK_DIVISOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_OWR_0_OWR_CLK_DIVISOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_NOR_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NOR_0                     _MK_ADDR_CONST(0x1d0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NOR_0_SECURE                      0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NOR_0_WORD_COUNT                  0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NOR_0_RESET_VAL                   _MK_MASK_CONST(0xc0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NOR_0_RESET_MASK                  _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NOR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NOR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NOR_0_READ_MASK                   _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NOR_0_WRITE_MASK                  _MK_MASK_CONST(0xc00000ff)
+//  00 = pllP_out0
+//  01 = pllC_out0
+//  10 = pllM_out0
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NOR_0_NOR_CLK_SRC_SHIFT                   _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NOR_0_NOR_CLK_SRC_FIELD                   (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_NOR_0_NOR_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NOR_0_NOR_CLK_SRC_RANGE                   31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NOR_0_NOR_CLK_SRC_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NOR_0_NOR_CLK_SRC_DEFAULT                 _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NOR_0_NOR_CLK_SRC_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NOR_0_NOR_CLK_SRC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NOR_0_NOR_CLK_SRC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NOR_0_NOR_CLK_SRC_INIT_ENUM                       CLK_M
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NOR_0_NOR_CLK_SRC_PLLP_OUT0                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NOR_0_NOR_CLK_SRC_PLLC_OUT0                       _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NOR_0_NOR_CLK_SRC_PLLM_OUT0                       _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NOR_0_NOR_CLK_SRC_CLK_M                   _MK_ENUM_CONST(3)
+
+//  N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NOR_0_NOR_CLK_DIVISOR_SHIFT                       _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NOR_0_NOR_CLK_DIVISOR_FIELD                       (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_NOR_0_NOR_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NOR_0_NOR_CLK_DIVISOR_RANGE                       7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NOR_0_NOR_CLK_DIVISOR_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NOR_0_NOR_CLK_DIVISOR_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NOR_0_NOR_CLK_DIVISOR_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NOR_0_NOR_CLK_DIVISOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NOR_0_NOR_CLK_DIVISOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+//  00 = pllP_out0
+//  01 = pllC_out0
+//  10 = pllM_out0
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NOR_0_SNOR_CLK_SRC_SHIFT                  _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NOR_0_SNOR_CLK_SRC_FIELD                  (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_NOR_0_SNOR_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NOR_0_SNOR_CLK_SRC_RANGE                  31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NOR_0_SNOR_CLK_SRC_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NOR_0_SNOR_CLK_SRC_DEFAULT                        _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NOR_0_SNOR_CLK_SRC_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NOR_0_SNOR_CLK_SRC_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NOR_0_SNOR_CLK_SRC_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NOR_0_SNOR_CLK_SRC_INIT_ENUM                      CLK_M
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NOR_0_SNOR_CLK_SRC_PLLP_OUT0                      _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NOR_0_SNOR_CLK_SRC_PLLC_OUT0                      _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NOR_0_SNOR_CLK_SRC_PLLM_OUT0                      _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NOR_0_SNOR_CLK_SRC_CLK_M                  _MK_ENUM_CONST(3)
+
+//  N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NOR_0_SNOR_CLK_DIVISOR_SHIFT                      _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NOR_0_SNOR_CLK_DIVISOR_FIELD                      (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_NOR_0_SNOR_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NOR_0_SNOR_CLK_DIVISOR_RANGE                      7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NOR_0_SNOR_CLK_DIVISOR_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NOR_0_SNOR_CLK_DIVISOR_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NOR_0_SNOR_CLK_DIVISOR_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NOR_0_SNOR_CLK_DIVISOR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NOR_0_SNOR_CLK_DIVISOR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0                   _MK_ADDR_CONST(0x1d4)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_SECURE                    0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_WORD_COUNT                        0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_RESET_VAL                         _MK_MASK_CONST(0xc0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_RESET_MASK                        _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_READ_MASK                         _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_WRITE_MASK                        _MK_MASK_CONST(0xc00000ff)
+//  00 = pllP_out0
+//  01 = pllC_out0
+//  10 = pllM_out0
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_CSITE_CLK_SRC_SHIFT                       _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_CSITE_CLK_SRC_FIELD                       (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_CSITE_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_CSITE_CLK_SRC_RANGE                       31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_CSITE_CLK_SRC_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_CSITE_CLK_SRC_DEFAULT                     _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_CSITE_CLK_SRC_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_CSITE_CLK_SRC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_CSITE_CLK_SRC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_CSITE_CLK_SRC_INIT_ENUM                   CLK_M
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_CSITE_CLK_SRC_PLLP_OUT0                   _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_CSITE_CLK_SRC_PLLC_OUT0                   _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_CSITE_CLK_SRC_PLLM_OUT0                   _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_CSITE_CLK_SRC_CLK_M                       _MK_ENUM_CONST(3)
+
+//  N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_CSITE_CLK_DIVISOR_SHIFT                   _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_CSITE_CLK_DIVISOR_FIELD                   (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_CSITE_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_CSITE_CLK_DIVISOR_RANGE                   7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_CSITE_CLK_DIVISOR_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_CSITE_CLK_DIVISOR_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_CSITE_CLK_DIVISOR_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_CSITE_CLK_DIVISOR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_CSITE_CLK_DIVISOR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Reserved address 472 [0x1d8] 
+
+// Reserved address 476 [0x1dc] 
+
+// Reserved address 480 [0x1e0] 
+
+// Reserved address 484 [0x1e4] 
+
+// Reserved address 488 [0x1e8] 
+
+// Reserved address 492 [0x1ec] 
+
+// Reserved address 496 [0x1f0] 
+
+// Reserved address 500 [0x1f4] 
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_LA_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0                      _MK_ADDR_CONST(0x1f8)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_SECURE                       0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_WORD_COUNT                   0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_RESET_VAL                    _MK_MASK_CONST(0xc0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_RESET_MASK                   _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_READ_MASK                    _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_WRITE_MASK                   _MK_MASK_CONST(0xc00000ff)
+//  00 = pllP_out0
+//  01 = pllC_out0
+//  10 = pllM_out0
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_LA_CLK_SRC_SHIFT                     _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_LA_CLK_SRC_FIELD                     (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_LA_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_LA_CLK_SRC_RANGE                     31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_LA_CLK_SRC_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_LA_CLK_SRC_DEFAULT                   _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_LA_CLK_SRC_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_LA_CLK_SRC_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_LA_CLK_SRC_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_LA_CLK_SRC_INIT_ENUM                 CLK_M
+#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_LA_CLK_SRC_PLLP_OUT0                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_LA_CLK_SRC_PLLC_OUT0                 _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_LA_CLK_SRC_PLLM_OUT0                 _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_LA_CLK_SRC_CLK_M                     _MK_ENUM_CONST(3)
+
+//  N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_LA_CLK_DIVISOR_SHIFT                 _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_LA_CLK_DIVISOR_FIELD                 (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_LA_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_LA_CLK_DIVISOR_RANGE                 7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_LA_CLK_DIVISOR_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_LA_CLK_DIVISOR_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_LA_CLK_DIVISOR_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_LA_CLK_DIVISOR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_LA_CLK_DIVISOR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_OSC_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_OSC_0                     _MK_ADDR_CONST(0x1fc)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_OSC_0_SECURE                      0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_OSC_0_WORD_COUNT                  0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_OSC_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_OSC_0_RESET_MASK                  _MK_MASK_CONST(0x10000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_OSC_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_OSC_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_OSC_0_READ_MASK                   _MK_MASK_CONST(0x10000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_OSC_0_WRITE_MASK                  _MK_MASK_CONST(0x10000000)
+//  0 = external oscillator
+//  1 = internal PLL_S
+#define CLK_RST_CONTROLLER_CLK_SOURCE_OSC_0_OSC_CLK_SRC_SHIFT                   _MK_SHIFT_CONST(28)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_OSC_0_OSC_CLK_SRC_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_SOURCE_OSC_0_OSC_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_OSC_0_OSC_CLK_SRC_RANGE                   28:28
+#define CLK_RST_CONTROLLER_CLK_SOURCE_OSC_0_OSC_CLK_SRC_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_OSC_0_OSC_CLK_SRC_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_OSC_0_OSC_CLK_SRC_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_OSC_0_OSC_CLK_SRC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_OSC_0_OSC_CLK_SRC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_OSC_0_OSC_CLK_SRC_INIT_ENUM                       EXT_OSC
+#define CLK_RST_CONTROLLER_CLK_SOURCE_OSC_0_OSC_CLK_SRC_EXT_OSC                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_OSC_0_OSC_CLK_SRC_INT_PLLS_OUT                    _MK_ENUM_CONST(1)
+
+
+// Register CLK_RST_CONTROLLER_LOCK_BOND_OUT_0  
+#define CLK_RST_CONTROLLER_LOCK_BOND_OUT_0                      _MK_ADDR_CONST(0x200)
+#define CLK_RST_CONTROLLER_LOCK_BOND_OUT_0_SECURE                       0x0
+#define CLK_RST_CONTROLLER_LOCK_BOND_OUT_0_WORD_COUNT                   0x1
+#define CLK_RST_CONTROLLER_LOCK_BOND_OUT_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LOCK_BOND_OUT_0_RESET_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LOCK_BOND_OUT_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LOCK_BOND_OUT_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LOCK_BOND_OUT_0_READ_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LOCK_BOND_OUT_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
+// 1 = lock all BOND_OUT_[L,H,U] registers.
+#define CLK_RST_CONTROLLER_LOCK_BOND_OUT_0_LOCK_BOND_OUT_REG_SHIFT                      _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_LOCK_BOND_OUT_0_LOCK_BOND_OUT_REG_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LOCK_BOND_OUT_0_LOCK_BOND_OUT_REG_SHIFT)
+#define CLK_RST_CONTROLLER_LOCK_BOND_OUT_0_LOCK_BOND_OUT_REG_RANGE                      0:0
+#define CLK_RST_CONTROLLER_LOCK_BOND_OUT_0_LOCK_BOND_OUT_REG_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_LOCK_BOND_OUT_0_LOCK_BOND_OUT_REG_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LOCK_BOND_OUT_0_LOCK_BOND_OUT_REG_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LOCK_BOND_OUT_0_LOCK_BOND_OUT_REG_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LOCK_BOND_OUT_0_LOCK_BOND_OUT_REG_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Reserved address 516 [0x204] 
+
+// Reserved address 520 [0x208] 
+
+// Reserved address 524 [0x20c] 
+
+// Reserved address 528 [0x210] 
+
+// Reserved address 532 [0x214] 
+
+// Reserved address 536 [0x218] 
+
+// Reserved address 540 [0x21c] 
+
+// Reserved address 544 [0x220] 
+
+// Reserved address 548 [0x224] 
+
+// Reserved address 552 [0x228] 
+
+// Reserved address 556 [0x22c] 
+
+// Reserved address 560 [0x230] 
+
+// Reserved address 564 [0x234] 
+
+// Reserved address 568 [0x238] 
+
+// Reserved address 572 [0x23c] 
+
+// Reserved address 576 [0x240] 
+
+// Reserved address 580 [0x244] 
+
+// Reserved address 584 [0x248] 
+
+// Reserved address 588 [0x24c] 
+
+// Reserved address 592 [0x250] 
+
+// Reserved address 596 [0x254] 
+
+// Reserved address 600 [0x258] 
+
+// Reserved address 604 [0x25c] 
+
+// Reserved address 608 [0x260] 
+
+// Reserved address 612 [0x264] 
+
+// Reserved address 616 [0x268] 
+
+// Reserved address 620 [0x26c] 
+
+// Reserved address 624 [0x270] 
+
+// Reserved address 628 [0x274] 
+
+// Reserved address 632 [0x278] 
+
+// Reserved address 636 [0x27c] 
+
+// Reserved address 640 [0x280] 
+
+// Reserved address 644 [0x284] 
+
+// Reserved address 648 [0x288] 
+
+// Reserved address 652 [0x28c] 
+
+// Reserved address 656 [0x290] 
+
+// Reserved address 660 [0x294] 
+
+// Reserved address 664 [0x298] 
+
+// Reserved address 668 [0x29c] 
+
+// Reserved address 672 [0x2a0] 
+
+// Reserved address 676 [0x2a4] 
+
+// Reserved address 680 [0x2a8] 
+
+// Reserved address 684 [0x2ac] 
+
+// Reserved address 688 [0x2b0] 
+
+// Reserved address 692 [0x2b4] 
+
+// Reserved address 696 [0x2b8] 
+
+// Reserved address 700 [0x2bc] 
+
+// Reserved address 704 [0x2c0] 
+
+// Reserved address 708 [0x2c4] 
+
+// Reserved address 712 [0x2c8] 
+
+// Reserved address 716 [0x2cc] 
+
+// Reserved address 720 [0x2d0] 
+
+// Reserved address 724 [0x2d4] 
+
+// Reserved address 728 [0x2d8] 
+
+// Reserved address 732 [0x2dc] 
+
+// Reserved address 736 [0x2e0] 
+
+// Reserved address 740 [0x2e4] 
+
+// Reserved address 744 [0x2e8] 
+
+// Reserved address 748 [0x2ec] 
+
+// Reserved address 752 [0x2f0] 
+
+// Reserved address 756 [0x2f4] 
+
+// Reserved address 760 [0x2f8] 
+
+// Reserved address 764 [0x2fc] 
+
+// Register CLK_RST_CONTROLLER_RST_DEV_L_SET_0  
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0                      _MK_ADDR_CONST(0x300)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SECURE                       0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_WORD_COUNT                   0x1
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_RESET_VAL                    _MK_MASK_CONST(0x3ffffec9)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_RESET_MASK                   _MK_MASK_CONST(0xbfffffff)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_READ_MASK                    _MK_MASK_CONST(0xbfffffff)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_WRITE_MASK                   _MK_MASK_CONST(0xbfffffff)
+// set reset COP cache controller.
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_CACHE2_RST_SHIFT                 _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_CACHE2_RST_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_CACHE2_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_CACHE2_RST_RANGE                 31:31
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_CACHE2_RST_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_CACHE2_RST_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_CACHE2_RST_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_CACHE2_RST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_CACHE2_RST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// set reset vector co-processor.
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_VCP_RST_SHIFT                    _MK_SHIFT_CONST(29)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_VCP_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_VCP_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_VCP_RST_RANGE                    29:29
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_VCP_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_VCP_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_VCP_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_VCP_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_VCP_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// set reset HOST1X.
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_HOST1X_RST_SHIFT                 _MK_SHIFT_CONST(28)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_HOST1X_RST_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_HOST1X_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_HOST1X_RST_RANGE                 28:28
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_HOST1X_RST_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_HOST1X_RST_DEFAULT                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_HOST1X_RST_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_HOST1X_RST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_HOST1X_RST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// set reset DISP1 controller.
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_DISP1_RST_SHIFT                  _MK_SHIFT_CONST(27)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_DISP1_RST_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_DISP1_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_DISP1_RST_RANGE                  27:27
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_DISP1_RST_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_DISP1_RST_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_DISP1_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_DISP1_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_DISP1_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// set reset DISP2 controller.
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_DISP2_RST_SHIFT                  _MK_SHIFT_CONST(26)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_DISP2_RST_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_DISP2_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_DISP2_RST_RANGE                  26:26
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_DISP2_RST_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_DISP2_RST_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_DISP2_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_DISP2_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_DISP2_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// set reset IDE controller.
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_IDE_RST_SHIFT                    _MK_SHIFT_CONST(25)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_IDE_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_IDE_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_IDE_RST_RANGE                    25:25
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_IDE_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_IDE_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_IDE_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_IDE_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_IDE_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// set reset 3D controller.
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_3D_RST_SHIFT                     _MK_SHIFT_CONST(24)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_3D_RST_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_3D_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_3D_RST_RANGE                     24:24
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_3D_RST_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_3D_RST_DEFAULT                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_3D_RST_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_3D_RST_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_3D_RST_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// set reset ISP controller.
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_ISP_RST_SHIFT                    _MK_SHIFT_CONST(23)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_ISP_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_ISP_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_ISP_RST_RANGE                    23:23
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_ISP_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_ISP_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_ISP_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_ISP_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_ISP_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// set reset USB controller
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_USBD_RST_SHIFT                   _MK_SHIFT_CONST(22)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_USBD_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_USBD_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_USBD_RST_RANGE                   22:22
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_USBD_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_USBD_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_USBD_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_USBD_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_USBD_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// set reset 2D graphics engine controller.
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_2D_RST_SHIFT                     _MK_SHIFT_CONST(21)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_2D_RST_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_2D_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_2D_RST_RANGE                     21:21
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_2D_RST_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_2D_RST_DEFAULT                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_2D_RST_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_2D_RST_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_2D_RST_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// set reset VI controller.
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_VI_RST_SHIFT                     _MK_SHIFT_CONST(20)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_VI_RST_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_VI_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_VI_RST_RANGE                     20:20
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_VI_RST_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_VI_RST_DEFAULT                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_VI_RST_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_VI_RST_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_VI_RST_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// set reset EPP controller.
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_EPP_RST_SHIFT                    _MK_SHIFT_CONST(19)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_EPP_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_EPP_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_EPP_RST_RANGE                    19:19
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_EPP_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_EPP_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_EPP_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_EPP_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_EPP_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// set reset I2S 2 Controller
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_I2S2_RST_SHIFT                   _MK_SHIFT_CONST(18)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_I2S2_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_I2S2_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_I2S2_RST_RANGE                   18:18
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_I2S2_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_I2S2_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_I2S2_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_I2S2_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_I2S2_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// set reset Pulse Width Modulator
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_PWM_RST_SHIFT                    _MK_SHIFT_CONST(17)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_PWM_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_PWM_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_PWM_RST_RANGE                    17:17
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_PWM_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_PWM_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_PWM_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_PWM_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_PWM_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// set reset Three Wire Controller
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_TWC_RST_SHIFT                    _MK_SHIFT_CONST(16)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_TWC_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_TWC_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_TWC_RST_RANGE                    16:16
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_TWC_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_TWC_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_TWC_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_TWC_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_TWC_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// set reset SDMMC4 controller.
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_SDMMC4_RST_SHIFT                 _MK_SHIFT_CONST(15)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_SDMMC4_RST_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_SDMMC4_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_SDMMC4_RST_RANGE                 15:15
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_SDMMC4_RST_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_SDMMC4_RST_DEFAULT                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_SDMMC4_RST_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_SDMMC4_RST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_SDMMC4_RST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// set reset SDMMC1 controller.
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_SDMMC1_RST_SHIFT                 _MK_SHIFT_CONST(14)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_SDMMC1_RST_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_SDMMC1_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_SDMMC1_RST_RANGE                 14:14
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_SDMMC1_RST_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_SDMMC1_RST_DEFAULT                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_SDMMC1_RST_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_SDMMC1_RST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_SDMMC1_RST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// set reset NAND flash controller.
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_NDFLASH_RST_SHIFT                        _MK_SHIFT_CONST(13)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_NDFLASH_RST_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_NDFLASH_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_NDFLASH_RST_RANGE                        13:13
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_NDFLASH_RST_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_NDFLASH_RST_DEFAULT                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_NDFLASH_RST_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_NDFLASH_RST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_NDFLASH_RST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// set reset I2C1 Controller
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_I2C1_RST_SHIFT                   _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_I2C1_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_I2C1_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_I2C1_RST_RANGE                   12:12
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_I2C1_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_I2C1_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_I2C1_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_I2C1_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_I2C1_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// set reset I2S 1 Controller
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_I2S1_RST_SHIFT                   _MK_SHIFT_CONST(11)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_I2S1_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_I2S1_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_I2S1_RST_RANGE                   11:11
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_I2S1_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_I2S1_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_I2S1_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_I2S1_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_I2S1_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// set reset SPDIF Controller
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_SPDIF_RST_SHIFT                  _MK_SHIFT_CONST(10)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_SPDIF_RST_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_SPDIF_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_SPDIF_RST_RANGE                  10:10
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_SPDIF_RST_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_SPDIF_RST_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_SPDIF_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_SPDIF_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_SPDIF_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// set reset SDMMC2 Controller
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_SDMMC2_RST_SHIFT                 _MK_SHIFT_CONST(9)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_SDMMC2_RST_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_SDMMC2_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_SDMMC2_RST_RANGE                 9:9
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_SDMMC2_RST_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_SDMMC2_RST_DEFAULT                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_SDMMC2_RST_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_SDMMC2_RST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_SDMMC2_RST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// set reset GPIO Controller
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_GPIO_RST_SHIFT                   _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_GPIO_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_GPIO_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_GPIO_RST_RANGE                   8:8
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_GPIO_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_GPIO_RST_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_GPIO_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_GPIO_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_GPIO_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// set reset UARTB/VFIR Controller
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_UARTB_RST_SHIFT                  _MK_SHIFT_CONST(7)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_UARTB_RST_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_UARTB_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_UARTB_RST_RANGE                  7:7
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_UARTB_RST_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_UARTB_RST_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_UARTB_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_UARTB_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_UARTB_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// set reset UARTA Controller 
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_UARTA_RST_SHIFT                  _MK_SHIFT_CONST(6)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_UARTA_RST_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_UARTA_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_UARTA_RST_RANGE                  6:6
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_UARTA_RST_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_UARTA_RST_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_UARTA_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_UARTA_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_UARTA_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// set reset Timer Controller
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_TMR_RST_SHIFT                    _MK_SHIFT_CONST(5)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_TMR_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_TMR_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_TMR_RST_RANGE                    5:5
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_TMR_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_TMR_RST_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_TMR_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_TMR_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_TMR_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// set reset RTC Controller
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_RTC_RST_SHIFT                    _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_RTC_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_RTC_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_RTC_RST_RANGE                    4:4
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_RTC_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_RTC_RST_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_RTC_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_RTC_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_RTC_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// set reset AC97 Controller
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_AC97_RST_SHIFT                   _MK_SHIFT_CONST(3)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_AC97_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_AC97_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_AC97_RST_RANGE                   3:3
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_AC97_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_AC97_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_AC97_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_AC97_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_AC97_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Write 1 to pulse System Reset Signal.
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_TRIG_SYS_RST_SHIFT                       _MK_SHIFT_CONST(2)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_TRIG_SYS_RST_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_TRIG_SYS_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_TRIG_SYS_RST_RANGE                       2:2
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_TRIG_SYS_RST_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_TRIG_SYS_RST_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_TRIG_SYS_RST_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_TRIG_SYS_RST_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_TRIG_SYS_RST_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// set reset COP.
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_COP_RST_SHIFT                    _MK_SHIFT_CONST(1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_COP_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_COP_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_COP_RST_RANGE                    1:1
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_COP_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_COP_RST_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_COP_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_COP_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_COP_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// set reset CPU.
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_CPU_RST_SHIFT                    _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_CPU_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_CPU_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_CPU_RST_RANGE                    0:0
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_CPU_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_CPU_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_CPU_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_CPU_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_CPU_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_RST_DEV_L_CLR_0  
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0                      _MK_ADDR_CONST(0x304)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_SECURE                       0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_WORD_COUNT                   0x1
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_RESET_VAL                    _MK_MASK_CONST(0x3ffffec9)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_RESET_MASK                   _MK_MASK_CONST(0xbffffffb)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_READ_MASK                    _MK_MASK_CONST(0xbffffffb)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_WRITE_MASK                   _MK_MASK_CONST(0xbffffffb)
+// clear reset COP cache controller.
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_CACHE2_RST_SHIFT                 _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_CACHE2_RST_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_CACHE2_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_CACHE2_RST_RANGE                 31:31
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_CACHE2_RST_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_CACHE2_RST_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_CACHE2_RST_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_CACHE2_RST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_CACHE2_RST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// clear reset vector co-processor.
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_VCP_RST_SHIFT                    _MK_SHIFT_CONST(29)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_VCP_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_VCP_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_VCP_RST_RANGE                    29:29
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_VCP_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_VCP_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_VCP_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_VCP_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_VCP_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// clear reset HOST1X.
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_HOST1X_RST_SHIFT                 _MK_SHIFT_CONST(28)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_HOST1X_RST_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_HOST1X_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_HOST1X_RST_RANGE                 28:28
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_HOST1X_RST_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_HOST1X_RST_DEFAULT                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_HOST1X_RST_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_HOST1X_RST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_HOST1X_RST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// clear reset DISP1 controller.
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_DISP1_RST_SHIFT                  _MK_SHIFT_CONST(27)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_DISP1_RST_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_DISP1_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_DISP1_RST_RANGE                  27:27
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_DISP1_RST_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_DISP1_RST_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_DISP1_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_DISP1_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_DISP1_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// clear reset DISP2 controller.
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_DISP2_RST_SHIFT                  _MK_SHIFT_CONST(26)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_DISP2_RST_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_DISP2_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_DISP2_RST_RANGE                  26:26
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_DISP2_RST_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_DISP2_RST_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_DISP2_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_DISP2_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_DISP2_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// clear reset IDE controller.
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_IDE_RST_SHIFT                    _MK_SHIFT_CONST(25)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_IDE_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_IDE_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_IDE_RST_RANGE                    25:25
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_IDE_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_IDE_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_IDE_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_IDE_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_IDE_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// clear reset 3D controlelr.
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_3D_RST_SHIFT                     _MK_SHIFT_CONST(24)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_3D_RST_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_3D_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_3D_RST_RANGE                     24:24
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_3D_RST_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_3D_RST_DEFAULT                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_3D_RST_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_3D_RST_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_3D_RST_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// clear reset ISP controller.
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_ISP_RST_SHIFT                    _MK_SHIFT_CONST(23)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_ISP_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_ISP_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_ISP_RST_RANGE                    23:23
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_ISP_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_ISP_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_ISP_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_ISP_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_ISP_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// clear reset USB controller
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_USBD_RST_SHIFT                   _MK_SHIFT_CONST(22)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_USBD_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_USBD_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_USBD_RST_RANGE                   22:22
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_USBD_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_USBD_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_USBD_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_USBD_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_USBD_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// clear reset 2D graphics engine controller.
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_2D_RST_SHIFT                     _MK_SHIFT_CONST(21)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_2D_RST_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_2D_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_2D_RST_RANGE                     21:21
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_2D_RST_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_2D_RST_DEFAULT                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_2D_RST_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_2D_RST_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_2D_RST_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// clear reset VI controller.
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_VI_RST_SHIFT                     _MK_SHIFT_CONST(20)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_VI_RST_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_VI_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_VI_RST_RANGE                     20:20
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_VI_RST_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_VI_RST_DEFAULT                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_VI_RST_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_VI_RST_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_VI_RST_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// clear reset EPP controller.
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_EPP_RST_SHIFT                    _MK_SHIFT_CONST(19)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_EPP_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_EPP_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_EPP_RST_RANGE                    19:19
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_EPP_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_EPP_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_EPP_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_EPP_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_EPP_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// clear reset I2S 2 Controller
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_I2S2_RST_SHIFT                   _MK_SHIFT_CONST(18)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_I2S2_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_I2S2_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_I2S2_RST_RANGE                   18:18
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_I2S2_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_I2S2_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_I2S2_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_I2S2_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_I2S2_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// clear reset Pulse Width Modulator
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_PWM_RST_SHIFT                    _MK_SHIFT_CONST(17)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_PWM_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_PWM_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_PWM_RST_RANGE                    17:17
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_PWM_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_PWM_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_PWM_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_PWM_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_PWM_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// clear reset Three Wire Controller
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_TWC_RST_SHIFT                    _MK_SHIFT_CONST(16)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_TWC_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_TWC_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_TWC_RST_RANGE                    16:16
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_TWC_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_TWC_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_TWC_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_TWC_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_TWC_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// clear reset SDMMC4 controller.
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_SDMMC4_RST_SHIFT                 _MK_SHIFT_CONST(15)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_SDMMC4_RST_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_SDMMC4_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_SDMMC4_RST_RANGE                 15:15
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_SDMMC4_RST_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_SDMMC4_RST_DEFAULT                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_SDMMC4_RST_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_SDMMC4_RST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_SDMMC4_RST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// clear reset SDMMC1 controller.
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_SDMMC1_RST_SHIFT                 _MK_SHIFT_CONST(14)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_SDMMC1_RST_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_SDMMC1_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_SDMMC1_RST_RANGE                 14:14
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_SDMMC1_RST_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_SDMMC1_RST_DEFAULT                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_SDMMC1_RST_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_SDMMC1_RST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_SDMMC1_RST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// clear reset NAND flash controller.
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_NDFLASH_RST_SHIFT                        _MK_SHIFT_CONST(13)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_NDFLASH_RST_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_NDFLASH_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_NDFLASH_RST_RANGE                        13:13
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_NDFLASH_RST_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_NDFLASH_RST_DEFAULT                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_NDFLASH_RST_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_NDFLASH_RST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_NDFLASH_RST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// clear reset I2C1 Controller
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_I2C1_RST_SHIFT                   _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_I2C1_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_I2C1_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_I2C1_RST_RANGE                   12:12
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_I2C1_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_I2C1_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_I2C1_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_I2C1_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_I2C1_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// clear reset I2S 1 Controller
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_I2S1_RST_SHIFT                   _MK_SHIFT_CONST(11)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_I2S1_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_I2S1_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_I2S1_RST_RANGE                   11:11
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_I2S1_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_I2S1_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_I2S1_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_I2S1_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_I2S1_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// clear reset SPDIF Controller
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_SPDIF_RST_SHIFT                  _MK_SHIFT_CONST(10)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_SPDIF_RST_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_SPDIF_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_SPDIF_RST_RANGE                  10:10
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_SPDIF_RST_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_SPDIF_RST_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_SPDIF_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_SPDIF_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_SPDIF_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// clear reset SDMMC2 Controller
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_SDMMC2_RST_SHIFT                 _MK_SHIFT_CONST(9)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_SDMMC2_RST_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_SDMMC2_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_SDMMC2_RST_RANGE                 9:9
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_SDMMC2_RST_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_SDMMC2_RST_DEFAULT                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_SDMMC2_RST_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_SDMMC2_RST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_SDMMC2_RST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// clear reset GPIO Controller
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_GPIO_RST_SHIFT                   _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_GPIO_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_GPIO_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_GPIO_RST_RANGE                   8:8
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_GPIO_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_GPIO_RST_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_GPIO_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_GPIO_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_GPIO_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// clear reset UARTB/VFIR Controller
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_UARTB_RST_SHIFT                  _MK_SHIFT_CONST(7)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_UARTB_RST_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_UARTB_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_UARTB_RST_RANGE                  7:7
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_UARTB_RST_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_UARTB_RST_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_UARTB_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_UARTB_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_UARTB_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// clear reset UARTA Controller 
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_UARTA_RST_SHIFT                  _MK_SHIFT_CONST(6)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_UARTA_RST_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_UARTA_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_UARTA_RST_RANGE                  6:6
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_UARTA_RST_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_UARTA_RST_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_UARTA_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_UARTA_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_UARTA_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// clear reset Timer Controller
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_TMR_RST_SHIFT                    _MK_SHIFT_CONST(5)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_TMR_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_TMR_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_TMR_RST_RANGE                    5:5
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_TMR_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_TMR_RST_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_TMR_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_TMR_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_TMR_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// clear reset RTC Controller
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_RTC_RST_SHIFT                    _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_RTC_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_RTC_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_RTC_RST_RANGE                    4:4
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_RTC_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_RTC_RST_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_RTC_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_RTC_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_RTC_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// clear reset AC97 Controller
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_AC97_RST_SHIFT                   _MK_SHIFT_CONST(3)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_AC97_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_AC97_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_AC97_RST_RANGE                   3:3
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_AC97_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_AC97_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_AC97_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_AC97_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_AC97_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// clear reset COP.
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_COP_RST_SHIFT                    _MK_SHIFT_CONST(1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_COP_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_COP_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_COP_RST_RANGE                    1:1
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_COP_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_COP_RST_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_COP_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_COP_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_COP_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// clear reset CPU.
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_CPU_RST_SHIFT                    _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_CPU_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_CPU_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_CPU_RST_RANGE                    0:0
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_CPU_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_CPU_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_CPU_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_CPU_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_CPU_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_RST_DEV_H_SET_0  
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0                      _MK_ADDR_CONST(0x308)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SECURE                       0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_WORD_COUNT                   0x1
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_RESET_VAL                    _MK_MASK_CONST(0xfefffb77)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_RESET_MASK                   _MK_MASK_CONST(0xfefffff7)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_READ_MASK                    _MK_MASK_CONST(0xfefffff7)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_WRITE_MASK                   _MK_MASK_CONST(0xfefffff7)
+// set reset BSEV controller.
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_BSEV_RST_SHIFT                   _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_BSEV_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_BSEV_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_BSEV_RST_RANGE                   31:31
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_BSEV_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_BSEV_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_BSEV_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_BSEV_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_BSEV_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// set reset BSEA controller.
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_BSEA_RST_SHIFT                   _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_BSEA_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_BSEA_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_BSEA_RST_RANGE                   30:30
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_BSEA_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_BSEA_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_BSEA_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_BSEA_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_BSEA_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// set reset VDE controller.
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_VDE_RST_SHIFT                    _MK_SHIFT_CONST(29)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_VDE_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_VDE_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_VDE_RST_RANGE                    29:29
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_VDE_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_VDE_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_VDE_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_VDE_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_VDE_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// set reset MPE controller.
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_MPE_RST_SHIFT                    _MK_SHIFT_CONST(28)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_MPE_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_MPE_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_MPE_RST_RANGE                    28:28
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_MPE_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_MPE_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_MPE_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_MPE_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_MPE_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// set reset USB3 controller.
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_USB3_RST_SHIFT                   _MK_SHIFT_CONST(27)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_USB3_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_USB3_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_USB3_RST_RANGE                   27:27
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_USB3_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_USB3_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_USB3_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_USB3_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_USB3_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// set reset USB2 controller.
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_USB2_RST_SHIFT                   _MK_SHIFT_CONST(26)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_USB2_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_USB2_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_USB2_RST_RANGE                   26:26
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_USB2_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_USB2_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_USB2_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_USB2_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_USB2_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// set reset EMC controller.
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_EMC_RST_SHIFT                    _MK_SHIFT_CONST(25)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_EMC_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_EMC_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_EMC_RST_RANGE                    25:25
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_EMC_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_EMC_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_EMC_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_EMC_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_EMC_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// set reset UART C Controller
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_UARTC_RST_SHIFT                  _MK_SHIFT_CONST(23)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_UARTC_RST_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_UARTC_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_UARTC_RST_RANGE                  23:23
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_UARTC_RST_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_UARTC_RST_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_UARTC_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_UARTC_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_UARTC_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// set reset I2C 2 controller.
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_I2C2_RST_SHIFT                   _MK_SHIFT_CONST(22)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_I2C2_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_I2C2_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_I2C2_RST_RANGE                   22:22
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_I2C2_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_I2C2_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_I2C2_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_I2C2_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_I2C2_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// set reset TVDAC controller.
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_TVDAC_RST_SHIFT                  _MK_SHIFT_CONST(21)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_TVDAC_RST_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_TVDAC_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_TVDAC_RST_RANGE                  21:21
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_TVDAC_RST_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_TVDAC_RST_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_TVDAC_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_TVDAC_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_TVDAC_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// set reset CSI controller.
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_CSI_RST_SHIFT                    _MK_SHIFT_CONST(20)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_CSI_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_CSI_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_CSI_RST_RANGE                    20:20
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_CSI_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_CSI_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_CSI_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_CSI_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_CSI_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// set reset HDMI
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_HDMI_RST_SHIFT                   _MK_SHIFT_CONST(19)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_HDMI_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_HDMI_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_HDMI_RST_RANGE                   19:19
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_HDMI_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_HDMI_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_HDMI_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_HDMI_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_HDMI_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// set reset MIPI base-band controller.
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_MIPI_RST_SHIFT                   _MK_SHIFT_CONST(18)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_MIPI_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_MIPI_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_MIPI_RST_RANGE                   18:18
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_MIPI_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_MIPI_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_MIPI_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_MIPI_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_MIPI_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// set reset TVO/CVE controller
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_TVO_RST_SHIFT                    _MK_SHIFT_CONST(17)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_TVO_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_TVO_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_TVO_RST_RANGE                    17:17
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_TVO_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_TVO_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_TVO_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_TVO_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_TVO_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// set reset DSI controller
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_DSI_RST_SHIFT                    _MK_SHIFT_CONST(16)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_DSI_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_DSI_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_DSI_RST_RANGE                    16:16
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_DSI_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_DSI_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_DSI_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_DSI_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_DSI_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// set reset DVC-I2C Controller
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_DVC_I2C_RST_SHIFT                        _MK_SHIFT_CONST(15)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_DVC_I2C_RST_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_DVC_I2C_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_DVC_I2C_RST_RANGE                        15:15
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_DVC_I2C_RST_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_DVC_I2C_RST_DEFAULT                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_DVC_I2C_RST_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_DVC_I2C_RST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_DVC_I2C_RST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// set reset SBC 3 Controller.
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_SBC3_RST_SHIFT                   _MK_SHIFT_CONST(14)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_SBC3_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_SBC3_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_SBC3_RST_RANGE                   14:14
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_SBC3_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_SBC3_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_SBC3_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_SBC3_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_SBC3_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// set reset XIO controller.
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_XIO_RST_SHIFT                    _MK_SHIFT_CONST(13)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_XIO_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_XIO_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_XIO_RST_RANGE                    13:13
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_XIO_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_XIO_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_XIO_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_XIO_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_XIO_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// set reset SBC 2 Controller.
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_SBC2_RST_SHIFT                   _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_SBC2_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_SBC2_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_SBC2_RST_RANGE                   12:12
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_SBC2_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_SBC2_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_SBC2_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_SBC2_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_SBC2_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// set reset SPI 1 Controller
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_SPI1_RST_SHIFT                   _MK_SHIFT_CONST(11)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_SPI1_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_SPI1_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_SPI1_RST_RANGE                   11:11
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_SPI1_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_SPI1_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_SPI1_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_SPI1_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_SPI1_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// set reset NOR Flash Controller.
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_NOR_RST_SHIFT                    _MK_SHIFT_CONST(10)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_NOR_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_NOR_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_NOR_RST_RANGE                    10:10
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_NOR_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_NOR_RST_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_NOR_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_NOR_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_NOR_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// set reset NOR Flash Controller.
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_SNOR_RST_SHIFT                   _MK_SHIFT_CONST(10)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_SNOR_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_SNOR_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_SNOR_RST_RANGE                   10:10
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_SNOR_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_SNOR_RST_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_SNOR_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_SNOR_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_SNOR_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// set reset SBC 1 Controller.
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_SBC1_RST_SHIFT                   _MK_SHIFT_CONST(9)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_SBC1_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_SBC1_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_SBC1_RST_RANGE                   9:9
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_SBC1_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_SBC1_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_SBC1_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_SBC1_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_SBC1_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// set reset KFuse controller.
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_KFUSE_RST_SHIFT                  _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_KFUSE_RST_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_KFUSE_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_KFUSE_RST_RANGE                  8:8
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_KFUSE_RST_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_KFUSE_RST_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_KFUSE_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_KFUSE_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_KFUSE_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// set reset Fuse controller.
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_FUSE_RST_SHIFT                   _MK_SHIFT_CONST(7)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_FUSE_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_FUSE_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_FUSE_RST_RANGE                   7:7
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_FUSE_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_FUSE_RST_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_FUSE_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_FUSE_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_FUSE_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// set reset PMC controller.
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_PMC_RST_SHIFT                    _MK_SHIFT_CONST(6)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_PMC_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_PMC_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_PMC_RST_RANGE                    6:6
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_PMC_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_PMC_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_PMC_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_PMC_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_PMC_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// set reset statistic monitor
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_STAT_MON_RST_SHIFT                       _MK_SHIFT_CONST(5)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_STAT_MON_RST_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_STAT_MON_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_STAT_MON_RST_RANGE                       5:5
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_STAT_MON_RST_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_STAT_MON_RST_DEFAULT                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_STAT_MON_RST_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_STAT_MON_RST_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_STAT_MON_RST_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// set reset Keyboard controller.
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_KBC_RST_SHIFT                    _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_KBC_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_KBC_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_KBC_RST_RANGE                    4:4
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_KBC_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_KBC_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_KBC_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_KBC_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_KBC_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// set reset APB-DMA.
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_APBDMA_RST_SHIFT                 _MK_SHIFT_CONST(2)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_APBDMA_RST_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_APBDMA_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_APBDMA_RST_RANGE                 2:2
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_APBDMA_RST_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_APBDMA_RST_DEFAULT                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_APBDMA_RST_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_APBDMA_RST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_APBDMA_RST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// set reset AHB-DMA.
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_AHBDMA_RST_SHIFT                 _MK_SHIFT_CONST(1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_AHBDMA_RST_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_AHBDMA_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_AHBDMA_RST_RANGE                 1:1
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_AHBDMA_RST_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_AHBDMA_RST_DEFAULT                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_AHBDMA_RST_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_AHBDMA_RST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_AHBDMA_RST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// set reset MC.
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_MEM_RST_SHIFT                    _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_MEM_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_MEM_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_MEM_RST_RANGE                    0:0
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_MEM_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_MEM_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_MEM_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_MEM_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_MEM_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_RST_DEV_H_CLR_0  
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0                      _MK_ADDR_CONST(0x30c)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_SECURE                       0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_WORD_COUNT                   0x1
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_RESET_VAL                    _MK_MASK_CONST(0xfefffb77)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_RESET_MASK                   _MK_MASK_CONST(0xfefffff7)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_READ_MASK                    _MK_MASK_CONST(0xfefffff7)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_WRITE_MASK                   _MK_MASK_CONST(0xfefffff7)
+// clear reset BSEV controller.
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_BSEV_RST_SHIFT                   _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_BSEV_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_BSEV_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_BSEV_RST_RANGE                   31:31
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_BSEV_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_BSEV_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_BSEV_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_BSEV_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_BSEV_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// clear reset BSEA controller.
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_BSEA_RST_SHIFT                   _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_BSEA_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_BSEA_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_BSEA_RST_RANGE                   30:30
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_BSEA_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_BSEA_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_BSEA_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_BSEA_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_BSEA_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// clear reset VDE controller.
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_VDE_RST_SHIFT                    _MK_SHIFT_CONST(29)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_VDE_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_VDE_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_VDE_RST_RANGE                    29:29
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_VDE_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_VDE_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_VDE_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_VDE_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_VDE_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// clear reset MPE controller.
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_MPE_RST_SHIFT                    _MK_SHIFT_CONST(28)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_MPE_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_MPE_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_MPE_RST_RANGE                    28:28
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_MPE_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_MPE_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_MPE_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_MPE_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_MPE_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// clear reset USB3 controller.
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_USB3_RST_SHIFT                   _MK_SHIFT_CONST(27)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_USB3_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_USB3_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_USB3_RST_RANGE                   27:27
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_USB3_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_USB3_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_USB3_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_USB3_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_USB3_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// clear reset USB2 controller.
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_USB2_RST_SHIFT                   _MK_SHIFT_CONST(26)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_USB2_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_USB2_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_USB2_RST_RANGE                   26:26
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_USB2_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_USB2_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_USB2_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_USB2_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_USB2_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// clear reset EMC controller.
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_EMC_RST_SHIFT                    _MK_SHIFT_CONST(25)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_EMC_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_EMC_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_EMC_RST_RANGE                    25:25
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_EMC_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_EMC_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_EMC_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_EMC_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_EMC_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// clear reset UART C Controller
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_UARTC_RST_SHIFT                  _MK_SHIFT_CONST(23)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_UARTC_RST_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_UARTC_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_UARTC_RST_RANGE                  23:23
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_UARTC_RST_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_UARTC_RST_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_UARTC_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_UARTC_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_UARTC_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// clear reset I2C 2 controller.
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_I2C2_RST_SHIFT                   _MK_SHIFT_CONST(22)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_I2C2_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_I2C2_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_I2C2_RST_RANGE                   22:22
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_I2C2_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_I2C2_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_I2C2_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_I2C2_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_I2C2_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// clear reset TVDAC controller.
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_TVDAC_RST_SHIFT                  _MK_SHIFT_CONST(21)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_TVDAC_RST_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_TVDAC_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_TVDAC_RST_RANGE                  21:21
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_TVDAC_RST_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_TVDAC_RST_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_TVDAC_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_TVDAC_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_TVDAC_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// clear reset CSI controller.
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_CSI_RST_SHIFT                    _MK_SHIFT_CONST(20)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_CSI_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_CSI_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_CSI_RST_RANGE                    20:20
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_CSI_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_CSI_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_CSI_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_CSI_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_CSI_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// clear reset HDMI
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_HDMI_RST_SHIFT                   _MK_SHIFT_CONST(19)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_HDMI_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_HDMI_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_HDMI_RST_RANGE                   19:19
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_HDMI_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_HDMI_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_HDMI_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_HDMI_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_HDMI_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// clear reset MIPI base-band controller.
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_MIPI_RST_SHIFT                   _MK_SHIFT_CONST(18)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_MIPI_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_MIPI_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_MIPI_RST_RANGE                   18:18
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_MIPI_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_MIPI_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_MIPI_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_MIPI_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_MIPI_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// clear reset TVO/CVE controller
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_TVO_RST_SHIFT                    _MK_SHIFT_CONST(17)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_TVO_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_TVO_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_TVO_RST_RANGE                    17:17
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_TVO_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_TVO_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_TVO_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_TVO_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_TVO_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// clear reset DSI controller
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_DSI_RST_SHIFT                    _MK_SHIFT_CONST(16)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_DSI_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_DSI_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_DSI_RST_RANGE                    16:16
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_DSI_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_DSI_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_DSI_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_DSI_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_DSI_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// clear reset DVC-I2C Controller
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_DVC_I2C_RST_SHIFT                        _MK_SHIFT_CONST(15)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_DVC_I2C_RST_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_DVC_I2C_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_DVC_I2C_RST_RANGE                        15:15
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_DVC_I2C_RST_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_DVC_I2C_RST_DEFAULT                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_DVC_I2C_RST_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_DVC_I2C_RST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_DVC_I2C_RST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// clear reset SBC 3 Controller.
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_SBC3_RST_SHIFT                   _MK_SHIFT_CONST(14)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_SBC3_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_SBC3_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_SBC3_RST_RANGE                   14:14
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_SBC3_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_SBC3_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_SBC3_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_SBC3_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_SBC3_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// clear reset XIO controller.
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_XIO_RST_SHIFT                    _MK_SHIFT_CONST(13)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_XIO_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_XIO_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_XIO_RST_RANGE                    13:13
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_XIO_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_XIO_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_XIO_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_XIO_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_XIO_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// clear reset SBC 2 Controller.
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_SBC2_RST_SHIFT                   _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_SBC2_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_SBC2_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_SBC2_RST_RANGE                   12:12
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_SBC2_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_SBC2_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_SBC2_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_SBC2_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_SBC2_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// clear reset SPI 1 Controller
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_SPI1_RST_SHIFT                   _MK_SHIFT_CONST(11)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_SPI1_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_SPI1_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_SPI1_RST_RANGE                   11:11
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_SPI1_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_SPI1_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_SPI1_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_SPI1_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_SPI1_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// clear reset NOR Flash Controller.
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_NOR_RST_SHIFT                    _MK_SHIFT_CONST(10)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_NOR_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_NOR_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_NOR_RST_RANGE                    10:10
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_NOR_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_NOR_RST_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_NOR_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_NOR_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_NOR_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// clear reset NOR Flash Controller.
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_SNOR_RST_SHIFT                   _MK_SHIFT_CONST(10)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_SNOR_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_SNOR_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_SNOR_RST_RANGE                   10:10
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_SNOR_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_SNOR_RST_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_SNOR_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_SNOR_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_SNOR_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// clear reset SBC 1 Controller.
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_SBC1_RST_SHIFT                   _MK_SHIFT_CONST(9)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_SBC1_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_SBC1_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_SBC1_RST_RANGE                   9:9
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_SBC1_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_SBC1_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_SBC1_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_SBC1_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_SBC1_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// clear reset KFuse controller.
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_KFUSE_RST_SHIFT                  _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_KFUSE_RST_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_KFUSE_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_KFUSE_RST_RANGE                  8:8
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_KFUSE_RST_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_KFUSE_RST_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_KFUSE_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_KFUSE_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_KFUSE_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// clear reset Fuse controller.
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_FUSE_RST_SHIFT                   _MK_SHIFT_CONST(7)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_FUSE_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_FUSE_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_FUSE_RST_RANGE                   7:7
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_FUSE_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_FUSE_RST_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_FUSE_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_FUSE_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_FUSE_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// clear reset PMC controller.
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_PMC_RST_SHIFT                    _MK_SHIFT_CONST(6)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_PMC_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_PMC_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_PMC_RST_RANGE                    6:6
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_PMC_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_PMC_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_PMC_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_PMC_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_PMC_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// clear reset statistic monitor
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_STAT_MON_RST_SHIFT                       _MK_SHIFT_CONST(5)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_STAT_MON_RST_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_STAT_MON_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_STAT_MON_RST_RANGE                       5:5
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_STAT_MON_RST_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_STAT_MON_RST_DEFAULT                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_STAT_MON_RST_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_STAT_MON_RST_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_STAT_MON_RST_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// clear reset Keyboard controller.
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_KBC_RST_SHIFT                    _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_KBC_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_KBC_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_KBC_RST_RANGE                    4:4
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_KBC_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_KBC_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_KBC_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_KBC_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_KBC_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// clear reset APB-DMA.
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_APBDMA_RST_SHIFT                 _MK_SHIFT_CONST(2)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_APBDMA_RST_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_APBDMA_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_APBDMA_RST_RANGE                 2:2
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_APBDMA_RST_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_APBDMA_RST_DEFAULT                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_APBDMA_RST_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_APBDMA_RST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_APBDMA_RST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// clear reset AHB-DMA.
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_AHBDMA_RST_SHIFT                 _MK_SHIFT_CONST(1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_AHBDMA_RST_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_AHBDMA_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_AHBDMA_RST_RANGE                 1:1
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_AHBDMA_RST_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_AHBDMA_RST_DEFAULT                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_AHBDMA_RST_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_AHBDMA_RST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_AHBDMA_RST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// clear reset MC.
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_MEM_RST_SHIFT                    _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_MEM_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_MEM_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_MEM_RST_RANGE                    0:0
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_MEM_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_MEM_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_MEM_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_MEM_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_MEM_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_RST_DEV_U_SET_0  
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0                      _MK_ADDR_CONST(0x310)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SECURE                       0x0
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_WORD_COUNT                   0x1
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_RESET_VAL                    _MK_MASK_CONST(0x15ff)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_RESET_MASK                   _MK_MASK_CONST(0x1fff)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_READ_MASK                    _MK_MASK_CONST(0x1fff)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_WRITE_MASK                   _MK_MASK_CONST(0x1fff)
+// set reset LA logic.
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_LA_RST_SHIFT                     _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_LA_RST_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_LA_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_LA_RST_RANGE                     12:12
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_LA_RST_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_LA_RST_DEFAULT                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_LA_RST_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_LA_RST_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_LA_RST_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// set reset AVPUCQ logic.
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_AVPUCQ_RST_SHIFT                 _MK_SHIFT_CONST(11)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_AVPUCQ_RST_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_AVPUCQ_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_AVPUCQ_RST_RANGE                 11:11
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_AVPUCQ_RST_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_AVPUCQ_RST_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_AVPUCQ_RST_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_AVPUCQ_RST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_AVPUCQ_RST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// set reset PCIEXCLK logic.
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_PCIEXCLK_RST_SHIFT                       _MK_SHIFT_CONST(10)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_PCIEXCLK_RST_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_PCIEXCLK_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_PCIEXCLK_RST_RANGE                       10:10
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_PCIEXCLK_RST_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_PCIEXCLK_RST_DEFAULT                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_PCIEXCLK_RST_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_PCIEXCLK_RST_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_PCIEXCLK_RST_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// set reset CSITE controller.
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_CSITE_RST_SHIFT                  _MK_SHIFT_CONST(9)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_CSITE_RST_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_CSITE_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_CSITE_RST_RANGE                  9:9
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_CSITE_RST_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_CSITE_RST_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_CSITE_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_CSITE_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_CSITE_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// set reset AFI controller.
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_AFI_RST_SHIFT                    _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_AFI_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_AFI_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_AFI_RST_RANGE                    8:8
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_AFI_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_AFI_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_AFI_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_AFI_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_AFI_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// set reset OWR controller.
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_OWR_RST_SHIFT                    _MK_SHIFT_CONST(7)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_OWR_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_OWR_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_OWR_RST_RANGE                    7:7
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_OWR_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_OWR_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_OWR_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_OWR_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_OWR_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// set reset PCIE controller.
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_PCIE_RST_SHIFT                   _MK_SHIFT_CONST(6)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_PCIE_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_PCIE_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_PCIE_RST_RANGE                   6:6
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_PCIE_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_PCIE_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_PCIE_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_PCIE_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_PCIE_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// set reset SDMMC3 controller.
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_SDMMC3_RST_SHIFT                 _MK_SHIFT_CONST(5)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_SDMMC3_RST_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_SDMMC3_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_SDMMC3_RST_RANGE                 5:5
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_SDMMC3_RST_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_SDMMC3_RST_DEFAULT                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_SDMMC3_RST_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_SDMMC3_RST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_SDMMC3_RST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// set reset SBC4 controller.
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_SBC4_RST_SHIFT                   _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_SBC4_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_SBC4_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_SBC4_RST_RANGE                   4:4
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_SBC4_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_SBC4_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_SBC4_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_SBC4_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_SBC4_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// set reset I2C3 controller.
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_I2C3_RST_SHIFT                   _MK_SHIFT_CONST(3)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_I2C3_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_I2C3_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_I2C3_RST_RANGE                   3:3
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_I2C3_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_I2C3_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_I2C3_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_I2C3_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_I2C3_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// set reset UARTE controller.
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_UARTE_RST_SHIFT                  _MK_SHIFT_CONST(2)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_UARTE_RST_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_UARTE_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_UARTE_RST_RANGE                  2:2
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_UARTE_RST_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_UARTE_RST_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_UARTE_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_UARTE_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_UARTE_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// set reset UARTD controller.
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_UARTD_RST_SHIFT                  _MK_SHIFT_CONST(1)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_UARTD_RST_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_UARTD_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_UARTD_RST_RANGE                  1:1
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_UARTD_RST_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_UARTD_RST_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_UARTD_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_UARTD_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_UARTD_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// set reset SPEEDO controller.
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_SPEEDO_RST_SHIFT                 _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_SPEEDO_RST_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_SPEEDO_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_SPEEDO_RST_RANGE                 0:0
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_SPEEDO_RST_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_SPEEDO_RST_DEFAULT                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_SPEEDO_RST_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_SPEEDO_RST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_SPEEDO_RST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_RST_DEV_U_CLR_0  
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0                      _MK_ADDR_CONST(0x314)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_SECURE                       0x0
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_WORD_COUNT                   0x1
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_RESET_VAL                    _MK_MASK_CONST(0x15ff)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_RESET_MASK                   _MK_MASK_CONST(0x1fff)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_READ_MASK                    _MK_MASK_CONST(0x1fff)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_WRITE_MASK                   _MK_MASK_CONST(0x1fff)
+// clear reset LA logic.
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_LA_RST_SHIFT                     _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_LA_RST_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_LA_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_LA_RST_RANGE                     12:12
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_LA_RST_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_LA_RST_DEFAULT                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_LA_RST_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_LA_RST_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_LA_RST_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// clear reset AVPUCQ logic.
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_AVPUCQ_RST_SHIFT                 _MK_SHIFT_CONST(11)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_AVPUCQ_RST_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_AVPUCQ_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_AVPUCQ_RST_RANGE                 11:11
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_AVPUCQ_RST_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_AVPUCQ_RST_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_AVPUCQ_RST_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_AVPUCQ_RST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_AVPUCQ_RST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// clear reset PCIEXCLK logic.
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_PCIEXCLK_RST_SHIFT                       _MK_SHIFT_CONST(10)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_PCIEXCLK_RST_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_PCIEXCLK_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_PCIEXCLK_RST_RANGE                       10:10
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_PCIEXCLK_RST_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_PCIEXCLK_RST_DEFAULT                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_PCIEXCLK_RST_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_PCIEXCLK_RST_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_PCIEXCLK_RST_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// clear reset CSITE controller.
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_CSITE_RST_SHIFT                  _MK_SHIFT_CONST(9)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_CSITE_RST_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_CSITE_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_CSITE_RST_RANGE                  9:9
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_CSITE_RST_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_CSITE_RST_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_CSITE_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_CSITE_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_CSITE_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// clear reset AFI controller.
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_AFI_RST_SHIFT                    _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_AFI_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_AFI_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_AFI_RST_RANGE                    8:8
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_AFI_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_AFI_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_AFI_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_AFI_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_AFI_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// clear reset OWR controller.
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_OWR_RST_SHIFT                    _MK_SHIFT_CONST(7)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_OWR_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_OWR_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_OWR_RST_RANGE                    7:7
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_OWR_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_OWR_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_OWR_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_OWR_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_OWR_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// clear reset PCIE controller.
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_PCIE_RST_SHIFT                   _MK_SHIFT_CONST(6)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_PCIE_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_PCIE_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_PCIE_RST_RANGE                   6:6
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_PCIE_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_PCIE_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_PCIE_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_PCIE_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_PCIE_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// clear reset SDMMC3 controller.
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_SDMMC3_RST_SHIFT                 _MK_SHIFT_CONST(5)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_SDMMC3_RST_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_SDMMC3_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_SDMMC3_RST_RANGE                 5:5
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_SDMMC3_RST_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_SDMMC3_RST_DEFAULT                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_SDMMC3_RST_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_SDMMC3_RST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_SDMMC3_RST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// clear reset SBC4 controller.
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_SBC4_RST_SHIFT                   _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_SBC4_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_SBC4_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_SBC4_RST_RANGE                   4:4
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_SBC4_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_SBC4_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_SBC4_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_SBC4_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_SBC4_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// clear reset I2C3 controller.
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_I2C3_RST_SHIFT                   _MK_SHIFT_CONST(3)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_I2C3_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_I2C3_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_I2C3_RST_RANGE                   3:3
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_I2C3_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_I2C3_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_I2C3_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_I2C3_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_I2C3_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// clear reset UARTE controller.
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_UARTE_RST_SHIFT                  _MK_SHIFT_CONST(2)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_UARTE_RST_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_UARTE_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_UARTE_RST_RANGE                  2:2
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_UARTE_RST_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_UARTE_RST_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_UARTE_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_UARTE_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_UARTE_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// clear reset UARTD controller.
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_UARTD_RST_SHIFT                  _MK_SHIFT_CONST(1)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_UARTD_RST_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_UARTD_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_UARTD_RST_RANGE                  1:1
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_UARTD_RST_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_UARTD_RST_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_UARTD_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_UARTD_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_UARTD_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// clear reset SPEEDO controller.
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_SPEEDO_RST_SHIFT                 _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_SPEEDO_RST_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_SPEEDO_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_SPEEDO_RST_RANGE                 0:0
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_SPEEDO_RST_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_SPEEDO_RST_DEFAULT                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_SPEEDO_RST_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_SPEEDO_RST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_SPEEDO_RST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Reserved address 792 [0x318] 
+
+// Reserved address 796 [0x31c] 
+
+// Register CLK_RST_CONTROLLER_CLK_ENB_L_SET_0  
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0                      _MK_ADDR_CONST(0x320)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SECURE                       0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_WORD_COUNT                   0x1
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_RESET_VAL                    _MK_MASK_CONST(0x80000130)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_RESET_MASK                   _MK_MASK_CONST(0xbffffff9)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_READ_MASK                    _MK_MASK_CONST(0xbffffff9)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_WRITE_MASK                   _MK_MASK_CONST(0xbffffff9)
+// set enable clock to COP cache controller.
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_CACHE2_SHIFT                     _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_CACHE2_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_CACHE2_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_CACHE2_RANGE                     31:31
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_CACHE2_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_CACHE2_DEFAULT                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_CACHE2_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_CACHE2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_CACHE2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// set enable clock to vector co-processor.
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_VCP_SHIFT                        _MK_SHIFT_CONST(29)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_VCP_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_VCP_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_VCP_RANGE                        29:29
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_VCP_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_VCP_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_VCP_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_VCP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_VCP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// set enable clock to HOST1X.
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_HOST1X_SHIFT                     _MK_SHIFT_CONST(28)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_HOST1X_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_HOST1X_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_HOST1X_RANGE                     28:28
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_HOST1X_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_HOST1X_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_HOST1X_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_HOST1X_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_HOST1X_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// set enable clock to DISP1 controller.
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_DISP1_SHIFT                      _MK_SHIFT_CONST(27)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_DISP1_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_DISP1_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_DISP1_RANGE                      27:27
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_DISP1_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_DISP1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_DISP1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_DISP1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_DISP1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// set enable clock to DISP2 controller.
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_DISP2_SHIFT                      _MK_SHIFT_CONST(26)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_DISP2_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_DISP2_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_DISP2_RANGE                      26:26
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_DISP2_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_DISP2_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_DISP2_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_DISP2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_DISP2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// set enable clock to IDE controller
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_IDE_SHIFT                        _MK_SHIFT_CONST(25)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_IDE_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_IDE_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_IDE_RANGE                        25:25
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_IDE_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_IDE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_IDE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_IDE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_IDE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// set enable clock to 3D controller.
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_3D_SHIFT                 _MK_SHIFT_CONST(24)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_3D_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_3D_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_3D_RANGE                 24:24
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_3D_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_3D_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_3D_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_3D_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_3D_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// set enable clock to ISP controller.
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_ISP_SHIFT                        _MK_SHIFT_CONST(23)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_ISP_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_ISP_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_ISP_RANGE                        23:23
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_ISP_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_ISP_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_ISP_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_ISP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_ISP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// set enable clock to USB controller
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_USBD_SHIFT                       _MK_SHIFT_CONST(22)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_USBD_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_USBD_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_USBD_RANGE                       22:22
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_USBD_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_USBD_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_USBD_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_USBD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_USBD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// set enable clock to 2D graphics engine.
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_2D_SHIFT                 _MK_SHIFT_CONST(21)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_2D_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_2D_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_2D_RANGE                 21:21
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_2D_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_2D_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_2D_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_2D_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_2D_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// set enable clock to VI controller.
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_VI_SHIFT                 _MK_SHIFT_CONST(20)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_VI_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_VI_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_VI_RANGE                 20:20
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_VI_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_VI_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_VI_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_VI_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_VI_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// set enable clock to EPP controller.
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_EPP_SHIFT                        _MK_SHIFT_CONST(19)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_EPP_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_EPP_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_EPP_RANGE                        19:19
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_EPP_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_EPP_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_EPP_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_EPP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_EPP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// set enable clock to I2S 2 controller
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_I2S2_SHIFT                       _MK_SHIFT_CONST(18)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_I2S2_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_I2S2_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_I2S2_RANGE                       18:18
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_I2S2_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_I2S2_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_I2S2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_I2S2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_I2S2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// set enable clock to PWM (Pulse Width Modulator)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_PWM_SHIFT                        _MK_SHIFT_CONST(17)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_PWM_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_PWM_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_PWM_RANGE                        17:17
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_PWM_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_PWM_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_PWM_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_PWM_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_PWM_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// set enable clock to 3-Wire Interface Controller
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_TWC_SHIFT                        _MK_SHIFT_CONST(16)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_TWC_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_TWC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_TWC_RANGE                        16:16
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_TWC_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_TWC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_TWC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_TWC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_TWC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// set enable clock to SDMMC4 controller.
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_SDMMC4_SHIFT                     _MK_SHIFT_CONST(15)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_SDMMC4_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_SDMMC4_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_SDMMC4_RANGE                     15:15
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_SDMMC4_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_SDMMC4_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_SDMMC4_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_SDMMC4_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_SDMMC4_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// set enable clock to SDMMC1 controller.
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_SDMMC1_SHIFT                     _MK_SHIFT_CONST(14)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_SDMMC1_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_SDMMC1_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_SDMMC1_RANGE                     14:14
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_SDMMC1_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_SDMMC1_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_SDMMC1_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_SDMMC1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_SDMMC1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// set enable clock to NAND flash controller.
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_NDFLASH_SHIFT                    _MK_SHIFT_CONST(13)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_NDFLASH_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_NDFLASH_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_NDFLASH_RANGE                    13:13
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_NDFLASH_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_NDFLASH_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_NDFLASH_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_NDFLASH_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_NDFLASH_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// set enable clock to I2C1 Controller
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_I2C1_SHIFT                       _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_I2C1_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_I2C1_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_I2C1_RANGE                       12:12
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_I2C1_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_I2C1_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_I2C1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_I2C1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_I2C1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// set enable clock to I2S1 Controller
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_I2S1_SHIFT                       _MK_SHIFT_CONST(11)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_I2S1_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_I2S1_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_I2S1_RANGE                       11:11
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_I2S1_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_I2S1_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_I2S1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_I2S1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_I2S1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// set enable clock to SPDIF Controller
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_SPDIF_SHIFT                      _MK_SHIFT_CONST(10)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_SPDIF_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_SPDIF_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_SPDIF_RANGE                      10:10
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_SPDIF_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_SPDIF_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_SPDIF_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_SPDIF_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_SPDIF_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// set enable clock to SDMMC2 controller.
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_SDMMC2_SHIFT                     _MK_SHIFT_CONST(9)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_SDMMC2_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_SDMMC2_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_SDMMC2_RANGE                     9:9
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_SDMMC2_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_SDMMC2_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_SDMMC2_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_SDMMC2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_SDMMC2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// set enable clock to GPIO Controller
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_GPIO_SHIFT                       _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_GPIO_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_GPIO_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_GPIO_RANGE                       8:8
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_GPIO_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_GPIO_DEFAULT                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_GPIO_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_GPIO_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_GPIO_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// set enable clock to UARTB/VFIR Controller
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_UARTB_SHIFT                      _MK_SHIFT_CONST(7)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_UARTB_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_UARTB_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_UARTB_RANGE                      7:7
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_UARTB_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_UARTB_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_UARTB_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_UARTB_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_UARTB_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// set enable clock to UARTA Controller
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_UARTA_SHIFT                      _MK_SHIFT_CONST(6)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_UARTA_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_UARTA_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_UARTA_RANGE                      6:6
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_UARTA_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_UARTA_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_UARTA_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_UARTA_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_UARTA_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// set enable clock to Timer Controller
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_TMR_SHIFT                        _MK_SHIFT_CONST(5)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_TMR_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_TMR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_TMR_RANGE                        5:5
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_TMR_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_TMR_DEFAULT                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_TMR_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_TMR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_TMR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// set enable clock to RTC Controller
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_RTC_SHIFT                        _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_RTC_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_RTC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_RTC_RANGE                        4:4
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_RTC_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_RTC_DEFAULT                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_RTC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_RTC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_RTC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// set enable clock to AC97 Controller
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_AC97_SHIFT                       _MK_SHIFT_CONST(3)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_AC97_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_AC97_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_AC97_RANGE                       3:3
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_AC97_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_AC97_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_AC97_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_AC97_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_AC97_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// set enable clock to CPU.
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_CPU_SHIFT                        _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_CPU_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_CPU_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_CPU_RANGE                        0:0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_CPU_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_CPU_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_CPU_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_CPU_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_CPU_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0  
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0                      _MK_ADDR_CONST(0x324)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_SECURE                       0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_WORD_COUNT                   0x1
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_RESET_VAL                    _MK_MASK_CONST(0x80000130)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_RESET_MASK                   _MK_MASK_CONST(0xbffffff9)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_READ_MASK                    _MK_MASK_CONST(0xbffffff9)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_WRITE_MASK                   _MK_MASK_CONST(0xbffffff9)
+// clear enable clock to COP cache controller.
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_CACHE2_SHIFT                     _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_CACHE2_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_CACHE2_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_CACHE2_RANGE                     31:31
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_CACHE2_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_CACHE2_DEFAULT                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_CACHE2_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_CACHE2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_CACHE2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// clear enable clock to vector co-processor.
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_VCP_SHIFT                        _MK_SHIFT_CONST(29)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_VCP_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_VCP_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_VCP_RANGE                        29:29
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_VCP_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_VCP_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_VCP_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_VCP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_VCP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// clear enable clock to HOST1X.
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_HOST1X_SHIFT                     _MK_SHIFT_CONST(28)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_HOST1X_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_HOST1X_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_HOST1X_RANGE                     28:28
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_HOST1X_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_HOST1X_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_HOST1X_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_HOST1X_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_HOST1X_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// clear enable clock to DISP1 controller.
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_DISP1_SHIFT                      _MK_SHIFT_CONST(27)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_DISP1_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_DISP1_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_DISP1_RANGE                      27:27
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_DISP1_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_DISP1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_DISP1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_DISP1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_DISP1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// clear enable clock to DISP2 controller.
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_DISP2_SHIFT                      _MK_SHIFT_CONST(26)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_DISP2_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_DISP2_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_DISP2_RANGE                      26:26
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_DISP2_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_DISP2_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_DISP2_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_DISP2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_DISP2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// clear enable clock to IDE controller
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_IDE_SHIFT                        _MK_SHIFT_CONST(25)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_IDE_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_IDE_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_IDE_RANGE                        25:25
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_IDE_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_IDE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_IDE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_IDE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_IDE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// clear enable clock to 3D controller.
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_3D_SHIFT                 _MK_SHIFT_CONST(24)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_3D_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_3D_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_3D_RANGE                 24:24
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_3D_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_3D_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_3D_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_3D_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_3D_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// clear enable clock to ISP controller.
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_ISP_SHIFT                        _MK_SHIFT_CONST(23)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_ISP_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_ISP_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_ISP_RANGE                        23:23
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_ISP_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_ISP_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_ISP_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_ISP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_ISP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// clear enable clock to USB controller
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_USBD_SHIFT                       _MK_SHIFT_CONST(22)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_USBD_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_USBD_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_USBD_RANGE                       22:22
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_USBD_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_USBD_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_USBD_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_USBD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_USBD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// clear enable clock to 2D graphics engine.
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_2D_SHIFT                 _MK_SHIFT_CONST(21)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_2D_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_2D_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_2D_RANGE                 21:21
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_2D_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_2D_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_2D_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_2D_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_2D_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// clear enable clock to VI controller.
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_VI_SHIFT                 _MK_SHIFT_CONST(20)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_VI_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_VI_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_VI_RANGE                 20:20
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_VI_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_VI_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_VI_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_VI_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_VI_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// clear enable clock to EPP controller.
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_EPP_SHIFT                        _MK_SHIFT_CONST(19)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_EPP_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_EPP_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_EPP_RANGE                        19:19
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_EPP_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_EPP_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_EPP_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_EPP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_EPP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// clear enable clock to I2S 2 controller
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_I2S2_SHIFT                       _MK_SHIFT_CONST(18)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_I2S2_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_I2S2_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_I2S2_RANGE                       18:18
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_I2S2_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_I2S2_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_I2S2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_I2S2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_I2S2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// clear enable clock to PWM (Pulse Width Modulator)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_PWM_SHIFT                        _MK_SHIFT_CONST(17)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_PWM_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_PWM_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_PWM_RANGE                        17:17
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_PWM_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_PWM_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_PWM_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_PWM_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_PWM_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// clear enable clock to 3-Wire Interface Controller
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_TWC_SHIFT                        _MK_SHIFT_CONST(16)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_TWC_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_TWC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_TWC_RANGE                        16:16
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_TWC_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_TWC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_TWC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_TWC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_TWC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// clear enable clock to SDMMC4 controller.
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_SDMMC4_SHIFT                     _MK_SHIFT_CONST(15)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_SDMMC4_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_SDMMC4_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_SDMMC4_RANGE                     15:15
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_SDMMC4_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_SDMMC4_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_SDMMC4_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_SDMMC4_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_SDMMC4_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// clear enable clock to SDMMC1 controller.
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_SDMMC1_SHIFT                     _MK_SHIFT_CONST(14)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_SDMMC1_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_SDMMC1_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_SDMMC1_RANGE                     14:14
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_SDMMC1_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_SDMMC1_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_SDMMC1_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_SDMMC1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_SDMMC1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// clear enable clock to NAND flash controller.
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_NDFLASH_SHIFT                    _MK_SHIFT_CONST(13)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_NDFLASH_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_NDFLASH_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_NDFLASH_RANGE                    13:13
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_NDFLASH_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_NDFLASH_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_NDFLASH_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_NDFLASH_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_NDFLASH_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// clear enable clock to I2C1 Controller
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_I2C1_SHIFT                       _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_I2C1_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_I2C1_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_I2C1_RANGE                       12:12
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_I2C1_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_I2C1_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_I2C1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_I2C1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_I2C1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// clear enable clock to I2S1 Controller
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_I2S1_SHIFT                       _MK_SHIFT_CONST(11)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_I2S1_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_I2S1_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_I2S1_RANGE                       11:11
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_I2S1_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_I2S1_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_I2S1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_I2S1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_I2S1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// clear enable clock to SPDIF Controller
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_SPDIF_SHIFT                      _MK_SHIFT_CONST(10)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_SPDIF_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_SPDIF_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_SPDIF_RANGE                      10:10
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_SPDIF_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_SPDIF_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_SPDIF_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_SPDIF_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_SPDIF_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// clear enable clock to SDMMC2 controller.
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_SDMMC2_SHIFT                     _MK_SHIFT_CONST(9)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_SDMMC2_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_SDMMC2_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_SDMMC2_RANGE                     9:9
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_SDMMC2_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_SDMMC2_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_SDMMC2_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_SDMMC2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_SDMMC2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// clear enable clock to GPIO Controller
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_GPIO_SHIFT                       _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_GPIO_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_GPIO_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_GPIO_RANGE                       8:8
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_GPIO_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_GPIO_DEFAULT                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_GPIO_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_GPIO_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_GPIO_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// clear enable clock to UARTB/VFIR Controller
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_UARTB_SHIFT                      _MK_SHIFT_CONST(7)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_UARTB_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_UARTB_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_UARTB_RANGE                      7:7
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_UARTB_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_UARTB_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_UARTB_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_UARTB_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_UARTB_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// clear enable clock to UARTA Controller
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_UARTA_SHIFT                      _MK_SHIFT_CONST(6)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_UARTA_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_UARTA_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_UARTA_RANGE                      6:6
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_UARTA_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_UARTA_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_UARTA_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_UARTA_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_UARTA_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// clear enable clock to Timer Controller
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_TMR_SHIFT                        _MK_SHIFT_CONST(5)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_TMR_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_TMR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_TMR_RANGE                        5:5
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_TMR_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_TMR_DEFAULT                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_TMR_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_TMR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_TMR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// clear enable clock to RTC Controller
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_RTC_SHIFT                        _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_RTC_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_RTC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_RTC_RANGE                        4:4
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_RTC_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_RTC_DEFAULT                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_RTC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_RTC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_RTC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// clear enable clock to AC97 Controller
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_AC97_SHIFT                       _MK_SHIFT_CONST(3)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_AC97_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_AC97_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_AC97_RANGE                       3:3
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_AC97_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_AC97_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_AC97_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_AC97_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_AC97_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// clear enable clock to CPU.
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_CPU_SHIFT                        _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_CPU_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_CPU_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_CPU_RANGE                        0:0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_CPU_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_CPU_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_CPU_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_CPU_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_CPU_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_ENB_H_SET_0  
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0                      _MK_ADDR_CONST(0x328)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SECURE                       0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_WORD_COUNT                   0x1
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_RESET_VAL                    _MK_MASK_CONST(0x400)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_RESET_MASK                   _MK_MASK_CONST(0xfefffff7)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_READ_MASK                    _MK_MASK_CONST(0xfefffff7)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_WRITE_MASK                   _MK_MASK_CONST(0xfefffff7)
+// set enable clock to BSEV Controller.
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_BSEV_SHIFT                       _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_BSEV_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_BSEV_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_BSEV_RANGE                       31:31
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_BSEV_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_BSEV_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_BSEV_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_BSEV_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_BSEV_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// set enable clock to BSEA Controller
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_BSEA_SHIFT                       _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_BSEA_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_BSEA_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_BSEA_RANGE                       30:30
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_BSEA_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_BSEA_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_BSEA_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_BSEA_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_BSEA_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// set enable clock to VDE Controller
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_VDE_SHIFT                        _MK_SHIFT_CONST(29)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_VDE_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_VDE_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_VDE_RANGE                        29:29
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_VDE_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_VDE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_VDE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_VDE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_VDE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// set enable clock to MPE controller.
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_MPE_SHIFT                        _MK_SHIFT_CONST(28)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_MPE_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_MPE_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_MPE_RANGE                        28:28
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_MPE_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_MPE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_MPE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_MPE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_MPE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// set enable clock to USB3 controller.
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_USB3_SHIFT                       _MK_SHIFT_CONST(27)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_USB3_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_USB3_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_USB3_RANGE                       27:27
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_USB3_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_USB3_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_USB3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_USB3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_USB3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// set enable clock to USB2 controller.
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_USB2_SHIFT                       _MK_SHIFT_CONST(26)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_USB2_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_USB2_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_USB2_RANGE                       26:26
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_USB2_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_USB2_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_USB2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_USB2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_USB2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// set enable clock to EMC controller.
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_EMC_SHIFT                        _MK_SHIFT_CONST(25)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_EMC_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_EMC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_EMC_RANGE                        25:25
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_EMC_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_EMC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_EMC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_EMC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_EMC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// set enable clock to UART-C Controller
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_UARTC_SHIFT                      _MK_SHIFT_CONST(23)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_UARTC_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_UARTC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_UARTC_RANGE                      23:23
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_UARTC_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_UARTC_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_UARTC_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_UARTC_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_UARTC_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// set enable clock to I2C2 controller.
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_I2C2_SHIFT                       _MK_SHIFT_CONST(22)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_I2C2_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_I2C2_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_I2C2_RANGE                       22:22
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_I2C2_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_I2C2_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_I2C2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_I2C2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_I2C2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// set enable clock to TVDAC controller.
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_TVDAC_SHIFT                      _MK_SHIFT_CONST(21)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_TVDAC_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_TVDAC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_TVDAC_RANGE                      21:21
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_TVDAC_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_TVDAC_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_TVDAC_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_TVDAC_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_TVDAC_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// set enable clock to CSI controller
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_CSI_SHIFT                        _MK_SHIFT_CONST(20)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_CSI_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_CSI_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_CSI_RANGE                        20:20
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_CSI_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_CSI_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_CSI_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_CSI_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_CSI_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// set enable clock to HDMI
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_HDMI_SHIFT                       _MK_SHIFT_CONST(19)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_HDMI_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_HDMI_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_HDMI_RANGE                       19:19
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_HDMI_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_HDMI_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_HDMI_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_HDMI_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_HDMI_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// set enable clock to MIPI base-band controller
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_MIPI_SHIFT                       _MK_SHIFT_CONST(18)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_MIPI_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_MIPI_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_MIPI_RANGE                       18:18
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_MIPI_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_MIPI_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_MIPI_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_MIPI_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_MIPI_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// set enable clock to TVO/CVE controller
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_TVO_SHIFT                        _MK_SHIFT_CONST(17)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_TVO_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_TVO_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_TVO_RANGE                        17:17
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_TVO_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_TVO_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_TVO_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_TVO_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_TVO_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// set enable clock to DSI controller
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_DSI_SHIFT                        _MK_SHIFT_CONST(16)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_DSI_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_DSI_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_DSI_RANGE                        16:16
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_DSI_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_DSI_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_DSI_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_DSI_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_DSI_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// set enable clock to DVC-I2C Controller
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_DVC_I2C_SHIFT                    _MK_SHIFT_CONST(15)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_DVC_I2C_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_DVC_I2C_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_DVC_I2C_RANGE                    15:15
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_DVC_I2C_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_DVC_I2C_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_DVC_I2C_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_DVC_I2C_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_DVC_I2C_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// set enable clock to SBC 3 Controller.
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_SBC3_SHIFT                       _MK_SHIFT_CONST(14)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_SBC3_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_SBC3_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_SBC3_RANGE                       14:14
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_SBC3_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_SBC3_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_SBC3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_SBC3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_SBC3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// set enable clock to XIO Controller.
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_XIO_SHIFT                        _MK_SHIFT_CONST(13)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_XIO_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_XIO_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_XIO_RANGE                        13:13
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_XIO_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_XIO_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_XIO_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_XIO_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_XIO_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// set enable clock to SBC 2 Controller.
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_SBC2_SHIFT                       _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_SBC2_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_SBC2_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_SBC2_RANGE                       12:12
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_SBC2_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_SBC2_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_SBC2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_SBC2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_SBC2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// set enable clock to SPI 1 Controller
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_SPI1_SHIFT                       _MK_SHIFT_CONST(11)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_SPI1_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_SPI1_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_SPI1_RANGE                       11:11
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_SPI1_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_SPI1_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_SPI1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_SPI1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_SPI1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// set enable clock to NOR Flash Controller.
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_NOR_SHIFT                        _MK_SHIFT_CONST(10)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_NOR_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_NOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_NOR_RANGE                        10:10
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_NOR_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_NOR_DEFAULT                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_NOR_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_NOR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_NOR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// set enable clock to NOR Flash Controller.
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_SNOR_SHIFT                       _MK_SHIFT_CONST(10)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_SNOR_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_SNOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_SNOR_RANGE                       10:10
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_SNOR_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_SNOR_DEFAULT                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_SNOR_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_SNOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_SNOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// set enable clock to SBC 1 Controller.
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_SBC1_SHIFT                       _MK_SHIFT_CONST(9)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_SBC1_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_SBC1_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_SBC1_RANGE                       9:9
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_SBC1_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_SBC1_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_SBC1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_SBC1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_SBC1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// set enable clock to KFUSE controller.
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_KFUSE_SHIFT                      _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_KFUSE_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_KFUSE_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_KFUSE_RANGE                      8:8
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_KFUSE_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_KFUSE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_KFUSE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_KFUSE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_KFUSE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// set enable clock to FUSE controller.
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_FUSE_SHIFT                       _MK_SHIFT_CONST(7)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_FUSE_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_FUSE_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_FUSE_RANGE                       7:7
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_FUSE_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_FUSE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_FUSE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_FUSE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_FUSE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// set enable clock to PMC controller.
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_PMC_SHIFT                        _MK_SHIFT_CONST(6)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_PMC_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_PMC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_PMC_RANGE                        6:6
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_PMC_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_PMC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_PMC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_PMC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_PMC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// set enable clock to statistic monitor.
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_STAT_MON_SHIFT                   _MK_SHIFT_CONST(5)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_STAT_MON_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_STAT_MON_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_STAT_MON_RANGE                   5:5
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_STAT_MON_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_STAT_MON_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_STAT_MON_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_STAT_MON_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_STAT_MON_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// set enable clock to keyboard controller.
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_KBC_SHIFT                        _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_KBC_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_KBC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_KBC_RANGE                        4:4
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_KBC_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_KBC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_KBC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_KBC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_KBC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// set enable clock to APB-DMA.
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_APBDMA_SHIFT                     _MK_SHIFT_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_APBDMA_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_APBDMA_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_APBDMA_RANGE                     2:2
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_APBDMA_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_APBDMA_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_APBDMA_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_APBDMA_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_APBDMA_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// set enable clock to AHB-DMA.
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_AHBDMA_SHIFT                     _MK_SHIFT_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_AHBDMA_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_AHBDMA_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_AHBDMA_RANGE                     1:1
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_AHBDMA_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_AHBDMA_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_AHBDMA_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_AHBDMA_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_AHBDMA_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// set enable clock to MC/EMC.
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_MEM_SHIFT                        _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_MEM_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_MEM_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_MEM_RANGE                        0:0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_MEM_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_MEM_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_MEM_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_MEM_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_MEM_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0  
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0                      _MK_ADDR_CONST(0x32c)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_SECURE                       0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_WORD_COUNT                   0x1
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_RESET_VAL                    _MK_MASK_CONST(0x400)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_RESET_MASK                   _MK_MASK_CONST(0xfefffff7)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_READ_MASK                    _MK_MASK_CONST(0xfefffff7)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_WRITE_MASK                   _MK_MASK_CONST(0xfefffff7)
+// clear enable clock to BSEV Controller.
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_BSEV_SHIFT                       _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_BSEV_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_BSEV_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_BSEV_RANGE                       31:31
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_BSEV_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_BSEV_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_BSEV_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_BSEV_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_BSEV_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// clear enable clock to BSEA Controller
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_BSEA_SHIFT                       _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_BSEA_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_BSEA_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_BSEA_RANGE                       30:30
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_BSEA_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_BSEA_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_BSEA_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_BSEA_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_BSEA_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// clear enable clock to VDE Controller
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_VDE_SHIFT                        _MK_SHIFT_CONST(29)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_VDE_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_VDE_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_VDE_RANGE                        29:29
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_VDE_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_VDE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_VDE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_VDE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_VDE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// clear enable clock to MPE controller.
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_MPE_SHIFT                        _MK_SHIFT_CONST(28)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_MPE_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_MPE_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_MPE_RANGE                        28:28
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_MPE_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_MPE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_MPE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_MPE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_MPE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// clear enable clock to USB3 controller.
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_USB3_SHIFT                       _MK_SHIFT_CONST(27)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_USB3_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_USB3_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_USB3_RANGE                       27:27
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_USB3_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_USB3_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_USB3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_USB3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_USB3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// clear enable clock to USB2 controller.
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_USB2_SHIFT                       _MK_SHIFT_CONST(26)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_USB2_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_USB2_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_USB2_RANGE                       26:26
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_USB2_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_USB2_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_USB2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_USB2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_USB2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// clear enable clock to EMC controller.
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_EMC_SHIFT                        _MK_SHIFT_CONST(25)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_EMC_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_EMC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_EMC_RANGE                        25:25
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_EMC_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_EMC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_EMC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_EMC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_EMC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// clear enable clock to UART-C Controller
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_UARTC_SHIFT                      _MK_SHIFT_CONST(23)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_UARTC_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_UARTC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_UARTC_RANGE                      23:23
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_UARTC_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_UARTC_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_UARTC_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_UARTC_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_UARTC_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// clear enable clock to I2C2 controller.
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_I2C2_SHIFT                       _MK_SHIFT_CONST(22)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_I2C2_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_I2C2_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_I2C2_RANGE                       22:22
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_I2C2_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_I2C2_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_I2C2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_I2C2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_I2C2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// clear enable clock to TVDAC controller.
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_TVDAC_SHIFT                      _MK_SHIFT_CONST(21)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_TVDAC_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_TVDAC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_TVDAC_RANGE                      21:21
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_TVDAC_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_TVDAC_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_TVDAC_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_TVDAC_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_TVDAC_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// clear enable clock to CSI controller
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_CSI_SHIFT                        _MK_SHIFT_CONST(20)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_CSI_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_CSI_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_CSI_RANGE                        20:20
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_CSI_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_CSI_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_CSI_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_CSI_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_CSI_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// clear enable clock to HDMI
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_HDMI_SHIFT                       _MK_SHIFT_CONST(19)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_HDMI_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_HDMI_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_HDMI_RANGE                       19:19
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_HDMI_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_HDMI_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_HDMI_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_HDMI_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_HDMI_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// clear enable clock to MIPI base-band controller
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_MIPI_SHIFT                       _MK_SHIFT_CONST(18)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_MIPI_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_MIPI_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_MIPI_RANGE                       18:18
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_MIPI_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_MIPI_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_MIPI_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_MIPI_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_MIPI_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// clear enable clock to TVO/CVE controller
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_TVO_SHIFT                        _MK_SHIFT_CONST(17)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_TVO_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_TVO_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_TVO_RANGE                        17:17
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_TVO_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_TVO_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_TVO_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_TVO_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_TVO_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// clear enable clock to DSI controller
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_DSI_SHIFT                        _MK_SHIFT_CONST(16)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_DSI_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_DSI_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_DSI_RANGE                        16:16
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_DSI_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_DSI_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_DSI_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_DSI_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_DSI_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// clear enable clock to DVC-I2C Controller
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_DVC_I2C_SHIFT                    _MK_SHIFT_CONST(15)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_DVC_I2C_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_DVC_I2C_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_DVC_I2C_RANGE                    15:15
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_DVC_I2C_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_DVC_I2C_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_DVC_I2C_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_DVC_I2C_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_DVC_I2C_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// clear enable clock to SBC 3 Controller.
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_SBC3_SHIFT                       _MK_SHIFT_CONST(14)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_SBC3_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_SBC3_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_SBC3_RANGE                       14:14
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_SBC3_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_SBC3_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_SBC3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_SBC3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_SBC3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// clear enable clock to XIO Controller.
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_XIO_SHIFT                        _MK_SHIFT_CONST(13)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_XIO_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_XIO_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_XIO_RANGE                        13:13
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_XIO_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_XIO_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_XIO_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_XIO_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_XIO_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// clear enable clock to SBC 2 Controller.
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_SBC2_SHIFT                       _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_SBC2_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_SBC2_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_SBC2_RANGE                       12:12
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_SBC2_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_SBC2_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_SBC2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_SBC2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_SBC2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// clear enable clock to SPI 1 Controller
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_SPI1_SHIFT                       _MK_SHIFT_CONST(11)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_SPI1_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_SPI1_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_SPI1_RANGE                       11:11
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_SPI1_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_SPI1_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_SPI1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_SPI1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_SPI1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// clear enable clock to NOR Flash Controller.
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_NOR_SHIFT                        _MK_SHIFT_CONST(10)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_NOR_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_NOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_NOR_RANGE                        10:10
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_NOR_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_NOR_DEFAULT                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_NOR_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_NOR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_NOR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// clear enable clock to NOR Flash Controller.
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_SNOR_SHIFT                       _MK_SHIFT_CONST(10)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_SNOR_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_SNOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_SNOR_RANGE                       10:10
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_SNOR_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_SNOR_DEFAULT                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_SNOR_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_SNOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_SNOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// clear enable clock to SBC 1 Controller.
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_SBC1_SHIFT                       _MK_SHIFT_CONST(9)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_SBC1_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_SBC1_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_SBC1_RANGE                       9:9
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_SBC1_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_SBC1_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_SBC1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_SBC1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_SBC1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// clear enable clock to KFUSE controller.
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_KFUSE_SHIFT                      _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_KFUSE_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_KFUSE_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_KFUSE_RANGE                      8:8
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_KFUSE_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_KFUSE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_KFUSE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_KFUSE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_KFUSE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// clear enable clock to FUSE controller.
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_FUSE_SHIFT                       _MK_SHIFT_CONST(7)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_FUSE_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_FUSE_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_FUSE_RANGE                       7:7
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_FUSE_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_FUSE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_FUSE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_FUSE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_FUSE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// clear enable clock to PMC controller.
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_PMC_SHIFT                        _MK_SHIFT_CONST(6)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_PMC_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_PMC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_PMC_RANGE                        6:6
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_PMC_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_PMC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_PMC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_PMC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_PMC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// clear enable clock to statistic monitor.
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_STAT_MON_SHIFT                   _MK_SHIFT_CONST(5)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_STAT_MON_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_STAT_MON_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_STAT_MON_RANGE                   5:5
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_STAT_MON_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_STAT_MON_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_STAT_MON_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_STAT_MON_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_STAT_MON_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// clear enable clock to keyboard controller.
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_KBC_SHIFT                        _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_KBC_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_KBC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_KBC_RANGE                        4:4
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_KBC_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_KBC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_KBC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_KBC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_KBC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// clear enable clock to APB-DMA.
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_APBDMA_SHIFT                     _MK_SHIFT_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_APBDMA_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_APBDMA_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_APBDMA_RANGE                     2:2
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_APBDMA_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_APBDMA_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_APBDMA_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_APBDMA_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_APBDMA_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// clear enable clock to AHB-DMA.
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_AHBDMA_SHIFT                     _MK_SHIFT_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_AHBDMA_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_AHBDMA_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_AHBDMA_RANGE                     1:1
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_AHBDMA_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_AHBDMA_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_AHBDMA_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_AHBDMA_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_AHBDMA_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// clear enable clock to MC/EMC.
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_MEM_SHIFT                        _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_MEM_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_MEM_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_MEM_RANGE                        0:0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_MEM_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_MEM_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_MEM_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_MEM_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_MEM_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_ENB_U_SET_0  
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0                      _MK_ADDR_CONST(0x330)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SECURE                       0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_WORD_COUNT                   0x1
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_RESET_VAL                    _MK_MASK_CONST(0x7f00a00)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_RESET_MASK                   _MK_MASK_CONST(0x77f01bff)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_READ_MASK                    _MK_MASK_CONST(0x77f01bff)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_WRITE_MASK                   _MK_MASK_CONST(0x77f01bff)
+// set enable clock to DEV1 pad.
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_DEV1_OUT_SHIFT                   _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_DEV1_OUT_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_DEV1_OUT_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_DEV1_OUT_RANGE                   30:30
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_DEV1_OUT_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_DEV1_OUT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_DEV1_OUT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_DEV1_OUT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_DEV1_OUT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// set enable clock to DEV2 pad.
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_DEV2_OUT_SHIFT                   _MK_SHIFT_CONST(29)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_DEV2_OUT_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_DEV2_OUT_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_DEV2_OUT_RANGE                   29:29
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_DEV2_OUT_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_DEV2_OUT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_DEV2_OUT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_DEV2_OUT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_DEV2_OUT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// set enable clock to SUS pad.
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_SUS_OUT_SHIFT                    _MK_SHIFT_CONST(28)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_SUS_OUT_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_SUS_OUT_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_SUS_OUT_RANGE                    28:28
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_SUS_OUT_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_SUS_OUT_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_SUS_OUT_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_SUS_OUT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_SUS_OUT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// set enable CLK_M clk doubler.
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_M_DOUBLER_ENB_SHIFT                  _MK_SHIFT_CONST(26)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_M_DOUBLER_ENB_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_M_DOUBLER_ENB_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_M_DOUBLER_ENB_RANGE                  26:26
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_M_DOUBLER_ENB_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_M_DOUBLER_ENB_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_M_DOUBLER_ENB_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_M_DOUBLER_ENB_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_M_DOUBLER_ENB_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// set enable audio sync clk doubler.
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_SYNC_CLK_DOUBLER_ENB_SHIFT                       _MK_SHIFT_CONST(25)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_SYNC_CLK_DOUBLER_ENB_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_SYNC_CLK_DOUBLER_ENB_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_SYNC_CLK_DOUBLER_ENB_RANGE                       25:25
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_SYNC_CLK_DOUBLER_ENB_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_SYNC_CLK_DOUBLER_ENB_DEFAULT                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_SYNC_CLK_DOUBLER_ENB_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_SYNC_CLK_DOUBLER_ENB_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_SYNC_CLK_DOUBLER_ENB_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// set enable COP cache ram clk.
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_CRAM2_SHIFT                      _MK_SHIFT_CONST(24)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_CRAM2_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_CRAM2_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_CRAM2_RANGE                      24:24
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_CRAM2_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_CRAM2_DEFAULT                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_CRAM2_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_CRAM2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_CRAM2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// set enable IRAMD clk.
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_IRAMD_SHIFT                      _MK_SHIFT_CONST(23)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_IRAMD_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_IRAMD_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_IRAMD_RANGE                      23:23
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_IRAMD_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_IRAMD_DEFAULT                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_IRAMD_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_IRAMD_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_IRAMD_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// set enable IRAMC clk.
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_IRAMC_SHIFT                      _MK_SHIFT_CONST(22)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_IRAMC_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_IRAMC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_IRAMC_RANGE                      22:22
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_IRAMC_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_IRAMC_DEFAULT                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_IRAMC_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_IRAMC_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_IRAMC_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// set enable IRAMB clk.
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_IRAMB_SHIFT                      _MK_SHIFT_CONST(21)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_IRAMB_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_IRAMB_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_IRAMB_RANGE                      21:21
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_IRAMB_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_IRAMB_DEFAULT                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_IRAMB_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_IRAMB_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_IRAMB_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// set enable IRAMB clk.
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_IRAMA_SHIFT                      _MK_SHIFT_CONST(20)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_IRAMA_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_IRAMA_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_IRAMA_RANGE                      20:20
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_IRAMA_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_IRAMA_DEFAULT                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_IRAMA_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_IRAMA_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_IRAMA_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// set enable clock to LA.
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_LA_SHIFT                 _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_LA_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_LA_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_LA_RANGE                 12:12
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_LA_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_LA_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_LA_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_LA_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_LA_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// set enable clock to AVPUCQ.
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_AVPUCQ_SHIFT                     _MK_SHIFT_CONST(11)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_AVPUCQ_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_AVPUCQ_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_AVPUCQ_RANGE                     11:11
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_AVPUCQ_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_AVPUCQ_DEFAULT                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_AVPUCQ_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_AVPUCQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_AVPUCQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// set enable clock to CSITE.
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_CSITE_SHIFT                      _MK_SHIFT_CONST(9)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_CSITE_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_CSITE_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_CSITE_RANGE                      9:9
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_CSITE_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_CSITE_DEFAULT                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_CSITE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_CSITE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_CSITE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// set enable clock to AFI.
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_AFI_SHIFT                        _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_AFI_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_AFI_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_AFI_RANGE                        8:8
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_AFI_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_AFI_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_AFI_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_AFI_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_AFI_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// set enable clock to OWR.
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_OWR_SHIFT                        _MK_SHIFT_CONST(7)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_OWR_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_OWR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_OWR_RANGE                        7:7
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_OWR_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_OWR_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_OWR_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_OWR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_OWR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// set enable clock to PCIE.
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_PCIE_SHIFT                       _MK_SHIFT_CONST(6)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_PCIE_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_PCIE_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_PCIE_RANGE                       6:6
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_PCIE_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_PCIE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_PCIE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_PCIE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_PCIE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// set enable clock to SDMMC3.
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_SDMMC3_SHIFT                     _MK_SHIFT_CONST(5)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_SDMMC3_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_SDMMC3_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_SDMMC3_RANGE                     5:5
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_SDMMC3_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_SDMMC3_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_SDMMC3_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_SDMMC3_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_SDMMC3_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// set enable clock to SBC4.
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_SBC4_SHIFT                       _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_SBC4_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_SBC4_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_SBC4_RANGE                       4:4
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_SBC4_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_SBC4_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_SBC4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_SBC4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_SBC4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// set enable clock to I2C3.
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_I2C3_SHIFT                       _MK_SHIFT_CONST(3)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_I2C3_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_I2C3_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_I2C3_RANGE                       3:3
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_I2C3_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_I2C3_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_I2C3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_I2C3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_I2C3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// set enable clock to UARTE.
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_UARTE_SHIFT                      _MK_SHIFT_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_UARTE_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_UARTE_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_UARTE_RANGE                      2:2
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_UARTE_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_UARTE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_UARTE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_UARTE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_UARTE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// set enable clock to UARTD.
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_UARTD_SHIFT                      _MK_SHIFT_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_UARTD_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_UARTD_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_UARTD_RANGE                      1:1
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_UARTD_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_UARTD_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_UARTD_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_UARTD_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_UARTD_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// set enable clock to SPEEDO.
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_SPEEDO_SHIFT                     _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_SPEEDO_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_SPEEDO_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_SPEEDO_RANGE                     0:0
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_SPEEDO_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_SPEEDO_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_SPEEDO_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_SPEEDO_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_SPEEDO_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0  
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0                      _MK_ADDR_CONST(0x334)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_SECURE                       0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_WORD_COUNT                   0x1
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_RESET_VAL                    _MK_MASK_CONST(0x7f00a00)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_RESET_MASK                   _MK_MASK_CONST(0x77f01bff)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_READ_MASK                    _MK_MASK_CONST(0x77f01bff)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_WRITE_MASK                   _MK_MASK_CONST(0x77f01bff)
+// clear enable clock to DEV1 pad.
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_DEV1_OUT_SHIFT                   _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_DEV1_OUT_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_DEV1_OUT_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_DEV1_OUT_RANGE                   30:30
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_DEV1_OUT_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_DEV1_OUT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_DEV1_OUT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_DEV1_OUT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_DEV1_OUT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// clear enable clock to DEV2 pad.
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_DEV2_OUT_SHIFT                   _MK_SHIFT_CONST(29)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_DEV2_OUT_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_DEV2_OUT_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_DEV2_OUT_RANGE                   29:29
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_DEV2_OUT_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_DEV2_OUT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_DEV2_OUT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_DEV2_OUT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_DEV2_OUT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// clear enable clock to SUS pad.
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_SUS_OUT_SHIFT                    _MK_SHIFT_CONST(28)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_SUS_OUT_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_SUS_OUT_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_SUS_OUT_RANGE                    28:28
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_SUS_OUT_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_SUS_OUT_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_SUS_OUT_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_SUS_OUT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_SUS_OUT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// clear enable CLK_M clk doubler.
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_M_DOUBLER_ENB_SHIFT                  _MK_SHIFT_CONST(26)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_M_DOUBLER_ENB_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_M_DOUBLER_ENB_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_M_DOUBLER_ENB_RANGE                  26:26
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_M_DOUBLER_ENB_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_M_DOUBLER_ENB_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_M_DOUBLER_ENB_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_M_DOUBLER_ENB_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_M_DOUBLER_ENB_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// clear enable audio sync clk doubler.
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_SYNC_CLK_DOUBLER_ENB_SHIFT                       _MK_SHIFT_CONST(25)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_SYNC_CLK_DOUBLER_ENB_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_SYNC_CLK_DOUBLER_ENB_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_SYNC_CLK_DOUBLER_ENB_RANGE                       25:25
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_SYNC_CLK_DOUBLER_ENB_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_SYNC_CLK_DOUBLER_ENB_DEFAULT                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_SYNC_CLK_DOUBLER_ENB_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_SYNC_CLK_DOUBLER_ENB_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_SYNC_CLK_DOUBLER_ENB_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// clear enable COP cache ram clk.
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_CRAM2_SHIFT                      _MK_SHIFT_CONST(24)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_CRAM2_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_CRAM2_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_CRAM2_RANGE                      24:24
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_CRAM2_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_CRAM2_DEFAULT                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_CRAM2_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_CRAM2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_CRAM2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// clear enable IRAMD clk.
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_IRAMD_SHIFT                      _MK_SHIFT_CONST(23)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_IRAMD_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_IRAMD_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_IRAMD_RANGE                      23:23
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_IRAMD_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_IRAMD_DEFAULT                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_IRAMD_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_IRAMD_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_IRAMD_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// clear enable IRAMC clk.
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_IRAMC_SHIFT                      _MK_SHIFT_CONST(22)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_IRAMC_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_IRAMC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_IRAMC_RANGE                      22:22
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_IRAMC_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_IRAMC_DEFAULT                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_IRAMC_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_IRAMC_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_IRAMC_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// clear enable IRAMB clk.
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_IRAMB_SHIFT                      _MK_SHIFT_CONST(21)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_IRAMB_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_IRAMB_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_IRAMB_RANGE                      21:21
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_IRAMB_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_IRAMB_DEFAULT                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_IRAMB_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_IRAMB_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_IRAMB_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// clear enable IRAMB clk.
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_IRAMA_SHIFT                      _MK_SHIFT_CONST(20)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_IRAMA_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_IRAMA_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_IRAMA_RANGE                      20:20
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_IRAMA_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_IRAMA_DEFAULT                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_IRAMA_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_IRAMA_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_IRAMA_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// clear enable clock to LA.
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_LA_SHIFT                 _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_LA_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_LA_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_LA_RANGE                 12:12
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_LA_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_LA_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_LA_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_LA_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_LA_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// clear enable clock to AVPUCQ.
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_AVPUCQ_SHIFT                     _MK_SHIFT_CONST(11)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_AVPUCQ_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_AVPUCQ_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_AVPUCQ_RANGE                     11:11
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_AVPUCQ_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_AVPUCQ_DEFAULT                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_AVPUCQ_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_AVPUCQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_AVPUCQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// clear enable clock to CSITE.
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_CSITE_SHIFT                      _MK_SHIFT_CONST(9)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_CSITE_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_CSITE_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_CSITE_RANGE                      9:9
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_CSITE_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_CSITE_DEFAULT                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_CSITE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_CSITE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_CSITE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// clear enable clock to AFI.
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_AFI_SHIFT                        _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_AFI_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_AFI_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_AFI_RANGE                        8:8
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_AFI_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_AFI_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_AFI_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_AFI_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_AFI_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// clear enable clock to OWR.
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_OWR_SHIFT                        _MK_SHIFT_CONST(7)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_OWR_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_OWR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_OWR_RANGE                        7:7
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_OWR_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_OWR_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_OWR_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_OWR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_OWR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// clear enable clock to PCIE.
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_PCIE_SHIFT                       _MK_SHIFT_CONST(6)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_PCIE_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_PCIE_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_PCIE_RANGE                       6:6
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_PCIE_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_PCIE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_PCIE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_PCIE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_PCIE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// clear enable clock to SDMMC3.
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_SDMMC3_SHIFT                     _MK_SHIFT_CONST(5)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_SDMMC3_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_SDMMC3_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_SDMMC3_RANGE                     5:5
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_SDMMC3_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_SDMMC3_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_SDMMC3_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_SDMMC3_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_SDMMC3_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// clear enable clock to SBC4.
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_SBC4_SHIFT                       _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_SBC4_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_SBC4_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_SBC4_RANGE                       4:4
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_SBC4_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_SBC4_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_SBC4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_SBC4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_SBC4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// clear enable clock to I2C3.
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_I2C3_SHIFT                       _MK_SHIFT_CONST(3)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_I2C3_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_I2C3_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_I2C3_RANGE                       3:3
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_I2C3_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_I2C3_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_I2C3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_I2C3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_I2C3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// clear enable clock to UARTE.
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_UARTE_SHIFT                      _MK_SHIFT_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_UARTE_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_UARTE_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_UARTE_RANGE                      2:2
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_UARTE_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_UARTE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_UARTE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_UARTE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_UARTE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// clear enable clock to UARTD.
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_UARTD_SHIFT                      _MK_SHIFT_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_UARTD_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_UARTD_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_UARTD_RANGE                      1:1
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_UARTD_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_UARTD_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_UARTD_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_UARTD_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_UARTD_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// clear enable clock to SPEEDO.
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_SPEEDO_SHIFT                     _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_SPEEDO_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_SPEEDO_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_SPEEDO_RANGE                     0:0
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_SPEEDO_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_SPEEDO_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_SPEEDO_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_SPEEDO_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_SPEEDO_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Reserved address 824 [0x338] 
+
+// Reserved address 828 [0x33c] 
+
+// Register CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0  
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0                  _MK_ADDR_CONST(0x340)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SECURE                   0x0
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_WORD_COUNT                       0x1
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_RESET_VAL                        _MK_MASK_CONST(0x2222)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_RESET_MASK                       _MK_MASK_CONST(0x70003333)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_READ_MASK                        _MK_MASK_CONST(0x70003333)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_WRITE_MASK                       _MK_MASK_CONST(0x70003333)
+// 1 = assert nPRESETDBG to the coresight.
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_PRESETDBG_SHIFT                      _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_PRESETDBG_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_PRESETDBG_SHIFT)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_PRESETDBG_RANGE                      30:30
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_PRESETDBG_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_PRESETDBG_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_PRESETDBG_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_PRESETDBG_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_PRESETDBG_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// 1 = assert nSCURESET to the SCU.
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_SCURESET_SHIFT                       _MK_SHIFT_CONST(29)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_SCURESET_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_SCURESET_SHIFT)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_SCURESET_RANGE                       29:29
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_SCURESET_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_SCURESET_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_SCURESET_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_SCURESET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_SCURESET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// 1 = assert nPERIPHRESET to the CPU.
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_PERIPHRESET_SHIFT                    _MK_SHIFT_CONST(28)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_PERIPHRESET_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_PERIPHRESET_SHIFT)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_PERIPHRESET_RANGE                    28:28
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_PERIPHRESET_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_PERIPHRESET_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_PERIPHRESET_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_PERIPHRESET_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_PERIPHRESET_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// 1 = assert nDBGRESET to CPU1.
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_DBGRESET1_SHIFT                      _MK_SHIFT_CONST(13)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_DBGRESET1_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_DBGRESET1_SHIFT)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_DBGRESET1_RANGE                      13:13
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_DBGRESET1_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_DBGRESET1_DEFAULT                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_DBGRESET1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_DBGRESET1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_DBGRESET1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// 1 = assert nDBGRESET to CPU0.
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_DBGRESET0_SHIFT                      _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_DBGRESET0_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_DBGRESET0_SHIFT)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_DBGRESET0_RANGE                      12:12
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_DBGRESET0_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_DBGRESET0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_DBGRESET0_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_DBGRESET0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_DBGRESET0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// 1 = assert nWDRESET to CPU1.
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_WDRESET1_SHIFT                       _MK_SHIFT_CONST(9)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_WDRESET1_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_WDRESET1_SHIFT)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_WDRESET1_RANGE                       9:9
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_WDRESET1_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_WDRESET1_DEFAULT                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_WDRESET1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_WDRESET1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_WDRESET1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// 1 = assert nWDRESET to CPU0.
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_WDRESET0_SHIFT                       _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_WDRESET0_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_WDRESET0_SHIFT)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_WDRESET0_RANGE                       8:8
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_WDRESET0_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_WDRESET0_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_WDRESET0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_WDRESET0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_WDRESET0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// 1 = assert nDERESET to CPU1.
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_DERESET1_SHIFT                       _MK_SHIFT_CONST(5)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_DERESET1_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_DERESET1_SHIFT)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_DERESET1_RANGE                       5:5
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_DERESET1_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_DERESET1_DEFAULT                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_DERESET1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_DERESET1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_DERESET1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// 1 = assert nDERESET to CPU0.
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_DERESET0_SHIFT                       _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_DERESET0_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_DERESET0_SHIFT)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_DERESET0_RANGE                       4:4
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_DERESET0_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_DERESET0_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_DERESET0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_DERESET0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_DERESET0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// 1 = assert nCPURESET to CPU1.
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_CPURESET1_SHIFT                      _MK_SHIFT_CONST(1)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_CPURESET1_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_CPURESET1_SHIFT)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_CPURESET1_RANGE                      1:1
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_CPURESET1_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_CPURESET1_DEFAULT                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_CPURESET1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_CPURESET1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_CPURESET1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// 1 = assert nCPURESET to CPU0.
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_CPURESET0_SHIFT                      _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_CPURESET0_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_CPURESET0_SHIFT)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_CPURESET0_RANGE                      0:0
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_CPURESET0_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_CPURESET0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_CPURESET0_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_CPURESET0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_CPURESET0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0  
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0                  _MK_ADDR_CONST(0x344)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_SECURE                   0x0
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_WORD_COUNT                       0x1
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_RESET_VAL                        _MK_MASK_CONST(0x2222)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_RESET_MASK                       _MK_MASK_CONST(0x70003333)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_READ_MASK                        _MK_MASK_CONST(0x70003333)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_WRITE_MASK                       _MK_MASK_CONST(0x70003333)
+// 1 = deasesrt nPRESETDBG to the coresight.
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_PRESETDBG_SHIFT                      _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_PRESETDBG_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_PRESETDBG_SHIFT)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_PRESETDBG_RANGE                      30:30
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_PRESETDBG_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_PRESETDBG_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_PRESETDBG_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_PRESETDBG_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_PRESETDBG_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// 1 = deasesrt nSCURESET to the SCU.
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_SCURESET_SHIFT                       _MK_SHIFT_CONST(29)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_SCURESET_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_SCURESET_SHIFT)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_SCURESET_RANGE                       29:29
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_SCURESET_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_SCURESET_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_SCURESET_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_SCURESET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_SCURESET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// 1 = deasesrt nPERIPHRESET to the CPU's interrupt/timer.
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_PERIPHRESET_SHIFT                    _MK_SHIFT_CONST(28)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_PERIPHRESET_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_PERIPHRESET_SHIFT)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_PERIPHRESET_RANGE                    28:28
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_PERIPHRESET_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_PERIPHRESET_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_PERIPHRESET_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_PERIPHRESET_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_PERIPHRESET_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// 1 = deasesrt nDBGRESET to CPU1.
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_DBGRESET1_SHIFT                      _MK_SHIFT_CONST(13)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_DBGRESET1_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_DBGRESET1_SHIFT)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_DBGRESET1_RANGE                      13:13
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_DBGRESET1_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_DBGRESET1_DEFAULT                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_DBGRESET1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_DBGRESET1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_DBGRESET1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// 1 = deasesrt nDBGRESET to CPU0.
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_DBGRESET0_SHIFT                      _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_DBGRESET0_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_DBGRESET0_SHIFT)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_DBGRESET0_RANGE                      12:12
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_DBGRESET0_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_DBGRESET0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_DBGRESET0_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_DBGRESET0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_DBGRESET0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// 1 = deasesrt nWDRESET to CPU1.
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_WDRESET1_SHIFT                       _MK_SHIFT_CONST(9)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_WDRESET1_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_WDRESET1_SHIFT)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_WDRESET1_RANGE                       9:9
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_WDRESET1_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_WDRESET1_DEFAULT                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_WDRESET1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_WDRESET1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_WDRESET1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// 1 = deasesrt nWDRESET to CPU0.
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_WDRESET0_SHIFT                       _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_WDRESET0_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_WDRESET0_SHIFT)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_WDRESET0_RANGE                       8:8
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_WDRESET0_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_WDRESET0_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_WDRESET0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_WDRESET0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_WDRESET0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// 1 = deasesrt nDERESET to CPU1.
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_DERESET1_SHIFT                       _MK_SHIFT_CONST(5)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_DERESET1_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_DERESET1_SHIFT)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_DERESET1_RANGE                       5:5
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_DERESET1_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_DERESET1_DEFAULT                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_DERESET1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_DERESET1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_DERESET1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// 1 = deasesrt nDERESET to CPU0.
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_DERESET0_SHIFT                       _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_DERESET0_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_DERESET0_SHIFT)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_DERESET0_RANGE                       4:4
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_DERESET0_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_DERESET0_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_DERESET0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_DERESET0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_DERESET0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// 1 = deasesrt nCPURESET to CPU1.
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_CPURESET1_SHIFT                      _MK_SHIFT_CONST(1)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_CPURESET1_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_CPURESET1_SHIFT)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_CPURESET1_RANGE                      1:1
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_CPURESET1_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_CPURESET1_DEFAULT                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_CPURESET1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_CPURESET1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_CPURESET1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// 1 = deasesrt nCPURESET to CPU0.
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_CPURESET0_SHIFT                      _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_CPURESET0_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_CPURESET0_SHIFT)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_CPURESET0_RANGE                      0:0
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_CPURESET0_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_CPURESET0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_CPURESET0_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_CPURESET0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_CPURESET0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Reserved address 840 [0x348] 
+
+// Reserved address 844 [0x34c] 
+
+//
+// REGISTER LIST
+//
+#define LIST_ARCLK_RST_REGS(_op_) \
+_op_(CLK_RST_CONTROLLER_RST_SOURCE_0) \
+_op_(CLK_RST_CONTROLLER_RST_DEVICES_L_0) \
+_op_(CLK_RST_CONTROLLER_RST_DEVICES_H_0) \
+_op_(CLK_RST_CONTROLLER_RST_DEVICES_U_0) \
+_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0) \
+_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0) \
+_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0) \
+_op_(CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0) \
+_op_(CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0) \
+_op_(CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0) \
+_op_(CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0) \
+_op_(CLK_RST_CONTROLLER_PROG_DLY_CLK_0) \
+_op_(CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_RATE_0) \
+_op_(CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0) \
+_op_(CLK_RST_CONTROLLER_CLK_MASK_ARM_0) \
+_op_(CLK_RST_CONTROLLER_MISC_CLK_ENB_0) \
+_op_(CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0) \
+_op_(CLK_RST_CONTROLLER_OSC_CTRL_0) \
+_op_(CLK_RST_CONTROLLER_PLL_LFSR_0) \
+_op_(CLK_RST_CONTROLLER_OSC_FREQ_DET_0) \
+_op_(CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0) \
+_op_(CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0) \
+_op_(CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0) \
+_op_(CLK_RST_CONTROLLER_PLLE_SS_CNTL_0) \
+_op_(CLK_RST_CONTROLLER_BOND_OUT_L_0) \
+_op_(CLK_RST_CONTROLLER_BOND_OUT_H_0) \
+_op_(CLK_RST_CONTROLLER_BOND_OUT_U_0) \
+_op_(CLK_RST_CONTROLLER_PLLC_BASE_0) \
+_op_(CLK_RST_CONTROLLER_PLLC_OUT_0) \
+_op_(CLK_RST_CONTROLLER_PLLC_MISC_0) \
+_op_(CLK_RST_CONTROLLER_PLLM_BASE_0) \
+_op_(CLK_RST_CONTROLLER_PLLM_OUT_0) \
+_op_(CLK_RST_CONTROLLER_PLLM_MISC_0) \
+_op_(CLK_RST_CONTROLLER_PLLP_BASE_0) \
+_op_(CLK_RST_CONTROLLER_PLLP_OUTA_0) \
+_op_(CLK_RST_CONTROLLER_PLLP_OUTB_0) \
+_op_(CLK_RST_CONTROLLER_PLLP_MISC_0) \
+_op_(CLK_RST_CONTROLLER_PLLA_BASE_0) \
+_op_(CLK_RST_CONTROLLER_PLLA_OUT_0) \
+_op_(CLK_RST_CONTROLLER_PLLA_MISC_0) \
+_op_(CLK_RST_CONTROLLER_PLLU_BASE_0) \
+_op_(CLK_RST_CONTROLLER_PLLU_MISC_0) \
+_op_(CLK_RST_CONTROLLER_PLLD_BASE_0) \
+_op_(CLK_RST_CONTROLLER_PLLD_MISC_0) \
+_op_(CLK_RST_CONTROLLER_PLLX_BASE_0) \
+_op_(CLK_RST_CONTROLLER_PLLX_MISC_0) \
+_op_(CLK_RST_CONTROLLER_PLLE_BASE_0) \
+_op_(CLK_RST_CONTROLLER_PLLE_MISC_0) \
+_op_(CLK_RST_CONTROLLER_PLLS_BASE_0) \
+_op_(CLK_RST_CONTROLLER_PLLS_MISC_0) \
+_op_(CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0) \
+_op_(CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_DISP1_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_DISP2_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_VI_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_SBC4_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_VDE_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_OWR_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_NOR_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_LA_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_OSC_0) \
+_op_(CLK_RST_CONTROLLER_LOCK_BOND_OUT_0) \
+_op_(CLK_RST_CONTROLLER_RST_DEV_L_SET_0) \
+_op_(CLK_RST_CONTROLLER_RST_DEV_L_CLR_0) \
+_op_(CLK_RST_CONTROLLER_RST_DEV_H_SET_0) \
+_op_(CLK_RST_CONTROLLER_RST_DEV_H_CLR_0) \
+_op_(CLK_RST_CONTROLLER_RST_DEV_U_SET_0) \
+_op_(CLK_RST_CONTROLLER_RST_DEV_U_CLR_0) \
+_op_(CLK_RST_CONTROLLER_CLK_ENB_L_SET_0) \
+_op_(CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0) \
+_op_(CLK_RST_CONTROLLER_CLK_ENB_H_SET_0) \
+_op_(CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0) \
+_op_(CLK_RST_CONTROLLER_CLK_ENB_U_SET_0) \
+_op_(CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0) \
+_op_(CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0) \
+_op_(CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0)
+
+
+//
+// ADDRESS SPACES
+//
+
+#define BASE_ADDRESS_CLK_RST_CONTROLLER 0x00000000
+
+//
+// ARCLK_RST REGISTER BANKS
+//
+
+#define CLK_RST_CONTROLLER0_FIRST_REG 0x0000 // CLK_RST_CONTROLLER_RST_SOURCE_0
+#define CLK_RST_CONTROLLER0_LAST_REG 0x0018 // CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0
+#define CLK_RST_CONTROLLER1_FIRST_REG 0x0020 // CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0
+#define CLK_RST_CONTROLLER1_LAST_REG 0x0038 // CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_RATE_0
+#define CLK_RST_CONTROLLER2_FIRST_REG 0x0040 // CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0
+#define CLK_RST_CONTROLLER2_LAST_REG 0x0068 // CLK_RST_CONTROLLER_PLLE_SS_CNTL_0
+#define CLK_RST_CONTROLLER3_FIRST_REG 0x0070 // CLK_RST_CONTROLLER_BOND_OUT_L_0
+#define CLK_RST_CONTROLLER3_LAST_REG 0x0078 // CLK_RST_CONTROLLER_BOND_OUT_U_0
+#define CLK_RST_CONTROLLER4_FIRST_REG 0x0080 // CLK_RST_CONTROLLER_PLLC_BASE_0
+#define CLK_RST_CONTROLLER4_LAST_REG 0x0084 // CLK_RST_CONTROLLER_PLLC_OUT_0
+#define CLK_RST_CONTROLLER5_FIRST_REG 0x008c // CLK_RST_CONTROLLER_PLLC_MISC_0
+#define CLK_RST_CONTROLLER5_LAST_REG 0x0094 // CLK_RST_CONTROLLER_PLLM_OUT_0
+#define CLK_RST_CONTROLLER6_FIRST_REG 0x009c // CLK_RST_CONTROLLER_PLLM_MISC_0
+#define CLK_RST_CONTROLLER6_LAST_REG 0x00b4 // CLK_RST_CONTROLLER_PLLA_OUT_0
+#define CLK_RST_CONTROLLER7_FIRST_REG 0x00bc // CLK_RST_CONTROLLER_PLLA_MISC_0
+#define CLK_RST_CONTROLLER7_LAST_REG 0x00c0 // CLK_RST_CONTROLLER_PLLU_BASE_0
+#define CLK_RST_CONTROLLER8_FIRST_REG 0x00cc // CLK_RST_CONTROLLER_PLLU_MISC_0
+#define CLK_RST_CONTROLLER8_LAST_REG 0x00d0 // CLK_RST_CONTROLLER_PLLD_BASE_0
+#define CLK_RST_CONTROLLER9_FIRST_REG 0x00dc // CLK_RST_CONTROLLER_PLLD_MISC_0
+#define CLK_RST_CONTROLLER9_LAST_REG 0x012c // CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0
+#define CLK_RST_CONTROLLER10_FIRST_REG 0x0134 // CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0
+#define CLK_RST_CONTROLLER10_LAST_REG 0x0148 // CLK_RST_CONTROLLER_CLK_SOURCE_VI_0
+#define CLK_RST_CONTROLLER11_FIRST_REG 0x0150 // CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0
+#define CLK_RST_CONTROLLER11_LAST_REG 0x0180 // CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0
+#define CLK_RST_CONTROLLER12_FIRST_REG 0x0188 // CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0
+#define CLK_RST_CONTROLLER12_LAST_REG 0x018c // CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0
+#define CLK_RST_CONTROLLER13_FIRST_REG 0x0194 // CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0
+#define CLK_RST_CONTROLLER13_LAST_REG 0x01a0 // CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0
+#define CLK_RST_CONTROLLER14_FIRST_REG 0x01a8 // CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0
+#define CLK_RST_CONTROLLER14_LAST_REG 0x01a8 // CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0
+#define CLK_RST_CONTROLLER15_FIRST_REG 0x01b4 // CLK_RST_CONTROLLER_CLK_SOURCE_SBC4_0
+#define CLK_RST_CONTROLLER15_LAST_REG 0x01d4 // CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0
+#define CLK_RST_CONTROLLER16_FIRST_REG 0x01f8 // CLK_RST_CONTROLLER_CLK_SOURCE_LA_0
+#define CLK_RST_CONTROLLER16_LAST_REG 0x0200 // CLK_RST_CONTROLLER_LOCK_BOND_OUT_0
+#define CLK_RST_CONTROLLER17_FIRST_REG 0x0300 // CLK_RST_CONTROLLER_RST_DEV_L_SET_0
+#define CLK_RST_CONTROLLER17_LAST_REG 0x0314 // CLK_RST_CONTROLLER_RST_DEV_U_CLR_0
+#define CLK_RST_CONTROLLER18_FIRST_REG 0x0320 // CLK_RST_CONTROLLER_CLK_ENB_L_SET_0
+#define CLK_RST_CONTROLLER18_LAST_REG 0x0334 // CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0
+#define CLK_RST_CONTROLLER19_FIRST_REG 0x0340 // CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0
+#define CLK_RST_CONTROLLER19_LAST_REG 0x0344 // CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0
+
+#ifndef _MK_SHIFT_CONST
+  #define _MK_SHIFT_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_MASK_CONST
+  #define _MK_MASK_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_ENUM_CONST
+  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
+#endif
+#ifndef _MK_ADDR_CONST
+  #define _MK_ADDR_CONST(_constant_) _constant_
+#endif
+
+#endif // ifndef ___ARCLK_RST_H_INC_
diff --git a/arch/arm/mach-tegra/include/ap20/ardvc.h b/arch/arm/mach-tegra/include/ap20/ardvc.h
new file mode 100644
index 000000000000..6d9d5486d725
--- /dev/null
+++ b/arch/arm/mach-tegra/include/ap20/ardvc.h
@@ -0,0 +1,5536 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+//
+// DO NOT EDIT - generated by simspec!
+//
+
+#ifndef ___ARDVC_H_INC_
+#define ___ARDVC_H_INC_
+
+// Register DVC_CTRL_REG1_0  
+#define DVC_CTRL_REG1_0                 _MK_ADDR_CONST(0x0)
+#define DVC_CTRL_REG1_0_SECURE                  0x0
+#define DVC_CTRL_REG1_0_WORD_COUNT                      0x1
+#define DVC_CTRL_REG1_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define DVC_CTRL_REG1_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define DVC_CTRL_REG1_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define DVC_CTRL_REG1_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define DVC_CTRL_REG1_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define DVC_CTRL_REG1_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+//Number of ref_clks to wait for PMU voltage change  request to take effect
+#define DVC_CTRL_REG1_0_PMU_WAIT_CNT_SHIFT                      _MK_SHIFT_CONST(11)
+#define DVC_CTRL_REG1_0_PMU_WAIT_CNT_FIELD                      (_MK_MASK_CONST(0x1fffff) << DVC_CTRL_REG1_0_PMU_WAIT_CNT_SHIFT)
+#define DVC_CTRL_REG1_0_PMU_WAIT_CNT_RANGE                      31:11
+#define DVC_CTRL_REG1_0_PMU_WAIT_CNT_WOFFSET                    0x0
+#define DVC_CTRL_REG1_0_PMU_WAIT_CNT_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_CTRL_REG1_0_PMU_WAIT_CNT_DEFAULT_MASK                       _MK_MASK_CONST(0x1fffff)
+#define DVC_CTRL_REG1_0_PMU_WAIT_CNT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define DVC_CTRL_REG1_0_PMU_WAIT_CNT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+//Enable Interrupt  0: disable (default), 1:Enable
+#define DVC_CTRL_REG1_0_INTR_EN_SHIFT                   _MK_SHIFT_CONST(10)
+#define DVC_CTRL_REG1_0_INTR_EN_FIELD                   (_MK_MASK_CONST(0x1) << DVC_CTRL_REG1_0_INTR_EN_SHIFT)
+#define DVC_CTRL_REG1_0_INTR_EN_RANGE                   10:10
+#define DVC_CTRL_REG1_0_INTR_EN_WOFFSET                 0x0
+#define DVC_CTRL_REG1_0_INTR_EN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define DVC_CTRL_REG1_0_INTR_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define DVC_CTRL_REG1_0_INTR_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define DVC_CTRL_REG1_0_INTR_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define DVC_CTRL_REG1_0_INTR_EN_DISABLE                 _MK_ENUM_CONST(0)
+#define DVC_CTRL_REG1_0_INTR_EN_ENABLE                  _MK_ENUM_CONST(1)
+
+// 0:not present , 1:present
+#define DVC_CTRL_REG1_0_EXT_PMU_SHIFT                   _MK_SHIFT_CONST(9)
+#define DVC_CTRL_REG1_0_EXT_PMU_FIELD                   (_MK_MASK_CONST(0x1) << DVC_CTRL_REG1_0_EXT_PMU_SHIFT)
+#define DVC_CTRL_REG1_0_EXT_PMU_RANGE                   9:9
+#define DVC_CTRL_REG1_0_EXT_PMU_WOFFSET                 0x0
+#define DVC_CTRL_REG1_0_EXT_PMU_DEFAULT                 _MK_MASK_CONST(0x0)
+#define DVC_CTRL_REG1_0_EXT_PMU_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define DVC_CTRL_REG1_0_EXT_PMU_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define DVC_CTRL_REG1_0_EXT_PMU_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define DVC_CTRL_REG1_0_EXT_PMU_NOT_PRESENT                     _MK_ENUM_CONST(0)
+#define DVC_CTRL_REG1_0_EXT_PMU_PRESENT                 _MK_ENUM_CONST(1)
+
+// Number of iterations to adjust the voltage
+#define DVC_CTRL_REG1_0_NUM_ITER_SHIFT                  _MK_SHIFT_CONST(2)
+#define DVC_CTRL_REG1_0_NUM_ITER_FIELD                  (_MK_MASK_CONST(0x7f) << DVC_CTRL_REG1_0_NUM_ITER_SHIFT)
+#define DVC_CTRL_REG1_0_NUM_ITER_RANGE                  8:2
+#define DVC_CTRL_REG1_0_NUM_ITER_WOFFSET                        0x0
+#define DVC_CTRL_REG1_0_NUM_ITER_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_CTRL_REG1_0_NUM_ITER_DEFAULT_MASK                   _MK_MASK_CONST(0x7f)
+#define DVC_CTRL_REG1_0_NUM_ITER_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_CTRL_REG1_0_NUM_ITER_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// 0: disable(default) , 1: Fixed Voltage adjust  mode , 2: Continuous mode
+#define DVC_CTRL_REG1_0_MODE_SHIFT                      _MK_SHIFT_CONST(0)
+#define DVC_CTRL_REG1_0_MODE_FIELD                      (_MK_MASK_CONST(0x3) << DVC_CTRL_REG1_0_MODE_SHIFT)
+#define DVC_CTRL_REG1_0_MODE_RANGE                      1:0
+#define DVC_CTRL_REG1_0_MODE_WOFFSET                    0x0
+#define DVC_CTRL_REG1_0_MODE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_CTRL_REG1_0_MODE_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define DVC_CTRL_REG1_0_MODE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define DVC_CTRL_REG1_0_MODE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define DVC_CTRL_REG1_0_MODE_DISABLE                    _MK_ENUM_CONST(0)
+#define DVC_CTRL_REG1_0_MODE_FIX_MODE                   _MK_ENUM_CONST(1)
+#define DVC_CTRL_REG1_0_MODE_CONT_MODE                  _MK_ENUM_CONST(2)
+
+
+// Register DVC_CTRL_REG2_0  
+#define DVC_CTRL_REG2_0                 _MK_ADDR_CONST(0x4)
+#define DVC_CTRL_REG2_0_SECURE                  0x0
+#define DVC_CTRL_REG2_0_WORD_COUNT                      0x1
+#define DVC_CTRL_REG2_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define DVC_CTRL_REG2_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define DVC_CTRL_REG2_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define DVC_CTRL_REG2_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define DVC_CTRL_REG2_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define DVC_CTRL_REG2_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Wakeup timer, in terms of number of ref clocks, for voltage adjustment process.
+#define DVC_CTRL_REG2_0_TIMER_CNT_SHIFT                 _MK_SHIFT_CONST(9)
+#define DVC_CTRL_REG2_0_TIMER_CNT_FIELD                 (_MK_MASK_CONST(0x7fffff) << DVC_CTRL_REG2_0_TIMER_CNT_SHIFT)
+#define DVC_CTRL_REG2_0_TIMER_CNT_RANGE                 31:9
+#define DVC_CTRL_REG2_0_TIMER_CNT_WOFFSET                       0x0
+#define DVC_CTRL_REG2_0_TIMER_CNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_CTRL_REG2_0_TIMER_CNT_DEFAULT_MASK                  _MK_MASK_CONST(0x7fffff)
+#define DVC_CTRL_REG2_0_TIMER_CNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_CTRL_REG2_0_TIMER_CNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// The period in terms of number of ref clks, during  which perf counter is incremented.
+#define DVC_CTRL_REG2_0_ROSC_SA_CNT_SHIFT                       _MK_SHIFT_CONST(2)
+#define DVC_CTRL_REG2_0_ROSC_SA_CNT_FIELD                       (_MK_MASK_CONST(0x7f) << DVC_CTRL_REG2_0_ROSC_SA_CNT_SHIFT)
+#define DVC_CTRL_REG2_0_ROSC_SA_CNT_RANGE                       8:2
+#define DVC_CTRL_REG2_0_ROSC_SA_CNT_WOFFSET                     0x0
+#define DVC_CTRL_REG2_0_ROSC_SA_CNT_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_CTRL_REG2_0_ROSC_SA_CNT_DEFAULT_MASK                        _MK_MASK_CONST(0x7f)
+#define DVC_CTRL_REG2_0_ROSC_SA_CNT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define DVC_CTRL_REG2_0_ROSC_SA_CNT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Number of ref clocks to wait for the ring oscillator  settle.
+#define DVC_CTRL_REG2_0_ROSC_START_DEL_SHIFT                    _MK_SHIFT_CONST(0)
+#define DVC_CTRL_REG2_0_ROSC_START_DEL_FIELD                    (_MK_MASK_CONST(0x3) << DVC_CTRL_REG2_0_ROSC_START_DEL_SHIFT)
+#define DVC_CTRL_REG2_0_ROSC_START_DEL_RANGE                    1:0
+#define DVC_CTRL_REG2_0_ROSC_START_DEL_WOFFSET                  0x0
+#define DVC_CTRL_REG2_0_ROSC_START_DEL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define DVC_CTRL_REG2_0_ROSC_START_DEL_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define DVC_CTRL_REG2_0_ROSC_START_DEL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_CTRL_REG2_0_ROSC_START_DEL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register DVC_CTRL_REG3_0  
+#define DVC_CTRL_REG3_0                 _MK_ADDR_CONST(0x8)
+#define DVC_CTRL_REG3_0_SECURE                  0x0
+#define DVC_CTRL_REG3_0_WORD_COUNT                      0x1
+#define DVC_CTRL_REG3_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define DVC_CTRL_REG3_0_RESET_MASK                      _MK_MASK_CONST(0xf7ffc3ff)
+#define DVC_CTRL_REG3_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define DVC_CTRL_REG3_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define DVC_CTRL_REG3_0_READ_MASK                       _MK_MASK_CONST(0xf7ffc3ff)
+#define DVC_CTRL_REG3_0_WRITE_MASK                      _MK_MASK_CONST(0xf7ffc3ff)
+// Status bit which s/w should write to let DVC know that PMU has been programmed. DVC will then clear this bit.
+#define DVC_CTRL_REG3_0_SW_PROG_PMU_DONE_SHIFT                  _MK_SHIFT_CONST(31)
+#define DVC_CTRL_REG3_0_SW_PROG_PMU_DONE_FIELD                  (_MK_MASK_CONST(0x1) << DVC_CTRL_REG3_0_SW_PROG_PMU_DONE_SHIFT)
+#define DVC_CTRL_REG3_0_SW_PROG_PMU_DONE_RANGE                  31:31
+#define DVC_CTRL_REG3_0_SW_PROG_PMU_DONE_WOFFSET                        0x0
+#define DVC_CTRL_REG3_0_SW_PROG_PMU_DONE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_CTRL_REG3_0_SW_PROG_PMU_DONE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define DVC_CTRL_REG3_0_SW_PROG_PMU_DONE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_CTRL_REG3_0_SW_PROG_PMU_DONE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Enable I2C intr which is triggered after I2C transfer is done.
+#define DVC_CTRL_REG3_0_I2C_DONE_INTR_EN_SHIFT                  _MK_SHIFT_CONST(30)
+#define DVC_CTRL_REG3_0_I2C_DONE_INTR_EN_FIELD                  (_MK_MASK_CONST(0x1) << DVC_CTRL_REG3_0_I2C_DONE_INTR_EN_SHIFT)
+#define DVC_CTRL_REG3_0_I2C_DONE_INTR_EN_RANGE                  30:30
+#define DVC_CTRL_REG3_0_I2C_DONE_INTR_EN_WOFFSET                        0x0
+#define DVC_CTRL_REG3_0_I2C_DONE_INTR_EN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_CTRL_REG3_0_I2C_DONE_INTR_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define DVC_CTRL_REG3_0_I2C_DONE_INTR_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_CTRL_REG3_0_I2C_DONE_INTR_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define DVC_CTRL_REG3_0_I2C_DONE_INTR_EN_DISABLE                        _MK_ENUM_CONST(0)
+#define DVC_CTRL_REG3_0_I2C_DONE_INTR_EN_ENABLE                 _MK_ENUM_CONST(1)
+
+// PMU voltage program ready intr enable
+#define DVC_CTRL_REG3_0_PMU_VOLT_READY_INTR_EN_SHIFT                    _MK_SHIFT_CONST(29)
+#define DVC_CTRL_REG3_0_PMU_VOLT_READY_INTR_EN_FIELD                    (_MK_MASK_CONST(0x1) << DVC_CTRL_REG3_0_PMU_VOLT_READY_INTR_EN_SHIFT)
+#define DVC_CTRL_REG3_0_PMU_VOLT_READY_INTR_EN_RANGE                    29:29
+#define DVC_CTRL_REG3_0_PMU_VOLT_READY_INTR_EN_WOFFSET                  0x0
+#define DVC_CTRL_REG3_0_PMU_VOLT_READY_INTR_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define DVC_CTRL_REG3_0_PMU_VOLT_READY_INTR_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define DVC_CTRL_REG3_0_PMU_VOLT_READY_INTR_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_CTRL_REG3_0_PMU_VOLT_READY_INTR_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define DVC_CTRL_REG3_0_PMU_VOLT_READY_INTR_EN_DISABLE                  _MK_ENUM_CONST(0)
+#define DVC_CTRL_REG3_0_PMU_VOLT_READY_INTR_EN_ENABLE                   _MK_ENUM_CONST(1)
+
+// Enable for target performance adjustment done interrupt.
+#define DVC_CTRL_REG3_0_TGT_PERF_DONE_INTR_EN_SHIFT                     _MK_SHIFT_CONST(28)
+#define DVC_CTRL_REG3_0_TGT_PERF_DONE_INTR_EN_FIELD                     (_MK_MASK_CONST(0x1) << DVC_CTRL_REG3_0_TGT_PERF_DONE_INTR_EN_SHIFT)
+#define DVC_CTRL_REG3_0_TGT_PERF_DONE_INTR_EN_RANGE                     28:28
+#define DVC_CTRL_REG3_0_TGT_PERF_DONE_INTR_EN_WOFFSET                   0x0
+#define DVC_CTRL_REG3_0_TGT_PERF_DONE_INTR_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define DVC_CTRL_REG3_0_TGT_PERF_DONE_INTR_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define DVC_CTRL_REG3_0_TGT_PERF_DONE_INTR_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_CTRL_REG3_0_TGT_PERF_DONE_INTR_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define DVC_CTRL_REG3_0_TGT_PERF_DONE_INTR_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define DVC_CTRL_REG3_0_TGT_PERF_DONE_INTR_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// Select either hardware or software to program the PMU via I2C.
+#define DVC_CTRL_REG3_0_I2C_HW_SW_PROG_SHIFT                    _MK_SHIFT_CONST(26)
+#define DVC_CTRL_REG3_0_I2C_HW_SW_PROG_FIELD                    (_MK_MASK_CONST(0x1) << DVC_CTRL_REG3_0_I2C_HW_SW_PROG_SHIFT)
+#define DVC_CTRL_REG3_0_I2C_HW_SW_PROG_RANGE                    26:26
+#define DVC_CTRL_REG3_0_I2C_HW_SW_PROG_WOFFSET                  0x0
+#define DVC_CTRL_REG3_0_I2C_HW_SW_PROG_DEFAULT                  _MK_MASK_CONST(0x0)
+#define DVC_CTRL_REG3_0_I2C_HW_SW_PROG_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define DVC_CTRL_REG3_0_I2C_HW_SW_PROG_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_CTRL_REG3_0_I2C_HW_SW_PROG_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define DVC_CTRL_REG3_0_I2C_HW_SW_PROG_HW                       _MK_ENUM_CONST(0)
+#define DVC_CTRL_REG3_0_I2C_HW_SW_PROG_SW                       _MK_ENUM_CONST(1)
+
+// Enable Wakeup timer.
+#define DVC_CTRL_REG3_0_TIMER_EN_SHIFT                  _MK_SHIFT_CONST(25)
+#define DVC_CTRL_REG3_0_TIMER_EN_FIELD                  (_MK_MASK_CONST(0x1) << DVC_CTRL_REG3_0_TIMER_EN_SHIFT)
+#define DVC_CTRL_REG3_0_TIMER_EN_RANGE                  25:25
+#define DVC_CTRL_REG3_0_TIMER_EN_WOFFSET                        0x0
+#define DVC_CTRL_REG3_0_TIMER_EN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_CTRL_REG3_0_TIMER_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define DVC_CTRL_REG3_0_TIMER_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_CTRL_REG3_0_TIMER_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define DVC_CTRL_REG3_0_TIMER_EN_DISABLE                        _MK_ENUM_CONST(0)
+#define DVC_CTRL_REG3_0_TIMER_EN_ENABLE                 _MK_ENUM_CONST(1)
+
+// Number of decrement requests, after an increment  request, to wait for, before voltage change is applied.
+#define DVC_CTRL_REG3_0_HYST_CNTR_SHIFT                 _MK_SHIFT_CONST(22)
+#define DVC_CTRL_REG3_0_HYST_CNTR_FIELD                 (_MK_MASK_CONST(0x7) << DVC_CTRL_REG3_0_HYST_CNTR_SHIFT)
+#define DVC_CTRL_REG3_0_HYST_CNTR_RANGE                 24:22
+#define DVC_CTRL_REG3_0_HYST_CNTR_WOFFSET                       0x0
+#define DVC_CTRL_REG3_0_HYST_CNTR_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_CTRL_REG3_0_HYST_CNTR_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
+#define DVC_CTRL_REG3_0_HYST_CNTR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_CTRL_REG3_0_HYST_CNTR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Self clearing bit that if set causes one  performance monitor sample to be taken 
+#define DVC_CTRL_REG3_0_TRIG_PM_SA_SHIFT                        _MK_SHIFT_CONST(21)
+#define DVC_CTRL_REG3_0_TRIG_PM_SA_FIELD                        (_MK_MASK_CONST(0x1) << DVC_CTRL_REG3_0_TRIG_PM_SA_SHIFT)
+#define DVC_CTRL_REG3_0_TRIG_PM_SA_RANGE                        21:21
+#define DVC_CTRL_REG3_0_TRIG_PM_SA_WOFFSET                      0x0
+#define DVC_CTRL_REG3_0_TRIG_PM_SA_DEFAULT                      _MK_MASK_CONST(0x0)
+#define DVC_CTRL_REG3_0_TRIG_PM_SA_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define DVC_CTRL_REG3_0_TRIG_PM_SA_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define DVC_CTRL_REG3_0_TRIG_PM_SA_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Select 1 of 32 path of ring oscillator adder
+#define DVC_CTRL_REG3_0_MUX_SEL_SHIFT                   _MK_SHIFT_CONST(16)
+#define DVC_CTRL_REG3_0_MUX_SEL_FIELD                   (_MK_MASK_CONST(0x1f) << DVC_CTRL_REG3_0_MUX_SEL_SHIFT)
+#define DVC_CTRL_REG3_0_MUX_SEL_RANGE                   20:16
+#define DVC_CTRL_REG3_0_MUX_SEL_WOFFSET                 0x0
+#define DVC_CTRL_REG3_0_MUX_SEL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define DVC_CTRL_REG3_0_MUX_SEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1f)
+#define DVC_CTRL_REG3_0_MUX_SEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define DVC_CTRL_REG3_0_MUX_SEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// 0:not long path , 1:select long path for clk
+#define DVC_CTRL_REG3_0_LONG_PATH_EN_SHIFT                      _MK_SHIFT_CONST(15)
+#define DVC_CTRL_REG3_0_LONG_PATH_EN_FIELD                      (_MK_MASK_CONST(0x1) << DVC_CTRL_REG3_0_LONG_PATH_EN_SHIFT)
+#define DVC_CTRL_REG3_0_LONG_PATH_EN_RANGE                      15:15
+#define DVC_CTRL_REG3_0_LONG_PATH_EN_WOFFSET                    0x0
+#define DVC_CTRL_REG3_0_LONG_PATH_EN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_CTRL_REG3_0_LONG_PATH_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define DVC_CTRL_REG3_0_LONG_PATH_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define DVC_CTRL_REG3_0_LONG_PATH_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define DVC_CTRL_REG3_0_LONG_PATH_EN_DISABLE                    _MK_ENUM_CONST(0)
+#define DVC_CTRL_REG3_0_LONG_PATH_EN_ENABLE                     _MK_ENUM_CONST(1)
+
+// Select between adder ring oscillator (0) and speedo ring oscillator (1).
+#define DVC_CTRL_REG3_0_RING_OSC_SEL_SHIFT                      _MK_SHIFT_CONST(14)
+#define DVC_CTRL_REG3_0_RING_OSC_SEL_FIELD                      (_MK_MASK_CONST(0x1) << DVC_CTRL_REG3_0_RING_OSC_SEL_SHIFT)
+#define DVC_CTRL_REG3_0_RING_OSC_SEL_RANGE                      14:14
+#define DVC_CTRL_REG3_0_RING_OSC_SEL_WOFFSET                    0x0
+#define DVC_CTRL_REG3_0_RING_OSC_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_CTRL_REG3_0_RING_OSC_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define DVC_CTRL_REG3_0_RING_OSC_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define DVC_CTRL_REG3_0_RING_OSC_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define DVC_CTRL_REG3_0_RING_OSC_SEL_OLD                        _MK_ENUM_CONST(0)
+#define DVC_CTRL_REG3_0_RING_OSC_SEL_NEW                        _MK_ENUM_CONST(1)
+
+// (actual perf-target perf)>threshold, voltage  tuning is done if enabled
+#define DVC_CTRL_REG3_0_VA_TH_H_SHIFT                   _MK_SHIFT_CONST(0)
+#define DVC_CTRL_REG3_0_VA_TH_H_FIELD                   (_MK_MASK_CONST(0x3ff) << DVC_CTRL_REG3_0_VA_TH_H_SHIFT)
+#define DVC_CTRL_REG3_0_VA_TH_H_RANGE                   9:0
+#define DVC_CTRL_REG3_0_VA_TH_H_WOFFSET                 0x0
+#define DVC_CTRL_REG3_0_VA_TH_H_DEFAULT                 _MK_MASK_CONST(0x0)
+#define DVC_CTRL_REG3_0_VA_TH_H_DEFAULT_MASK                    _MK_MASK_CONST(0x3ff)
+#define DVC_CTRL_REG3_0_VA_TH_H_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define DVC_CTRL_REG3_0_VA_TH_H_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register DVC_STATUS_REG_0  
+#define DVC_STATUS_REG_0                        _MK_ADDR_CONST(0xc)
+#define DVC_STATUS_REG_0_SECURE                         0x0
+#define DVC_STATUS_REG_0_WORD_COUNT                     0x1
+#define DVC_STATUS_REG_0_RESET_VAL                      _MK_MASK_CONST(0x60000)
+#define DVC_STATUS_REG_0_RESET_MASK                     _MK_MASK_CONST(0x7fffffff)
+#define DVC_STATUS_REG_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define DVC_STATUS_REG_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define DVC_STATUS_REG_0_READ_MASK                      _MK_MASK_CONST(0x7fffffff)
+#define DVC_STATUS_REG_0_WRITE_MASK                     _MK_MASK_CONST(0x7fffffff)
+// Interrupt to indicate I2C transfer is done
+#define DVC_STATUS_REG_0_I2C_DONE_INTR_SHIFT                    _MK_SHIFT_CONST(30)
+#define DVC_STATUS_REG_0_I2C_DONE_INTR_FIELD                    (_MK_MASK_CONST(0x1) << DVC_STATUS_REG_0_I2C_DONE_INTR_SHIFT)
+#define DVC_STATUS_REG_0_I2C_DONE_INTR_RANGE                    30:30
+#define DVC_STATUS_REG_0_I2C_DONE_INTR_WOFFSET                  0x0
+#define DVC_STATUS_REG_0_I2C_DONE_INTR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define DVC_STATUS_REG_0_I2C_DONE_INTR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define DVC_STATUS_REG_0_I2C_DONE_INTR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_STATUS_REG_0_I2C_DONE_INTR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Interrupt indicating that voltage adjustment value is ready and can be programmed to PMU via I2C by software.
+#define DVC_STATUS_REG_0_PMU_VOLT_READY_INTR_SHIFT                      _MK_SHIFT_CONST(29)
+#define DVC_STATUS_REG_0_PMU_VOLT_READY_INTR_FIELD                      (_MK_MASK_CONST(0x1) << DVC_STATUS_REG_0_PMU_VOLT_READY_INTR_SHIFT)
+#define DVC_STATUS_REG_0_PMU_VOLT_READY_INTR_RANGE                      29:29
+#define DVC_STATUS_REG_0_PMU_VOLT_READY_INTR_WOFFSET                    0x0
+#define DVC_STATUS_REG_0_PMU_VOLT_READY_INTR_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_STATUS_REG_0_PMU_VOLT_READY_INTR_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define DVC_STATUS_REG_0_PMU_VOLT_READY_INTR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define DVC_STATUS_REG_0_PMU_VOLT_READY_INTR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Interrupt to firmware to indicate voltage change has been completed.
+#define DVC_STATUS_REG_0_TGT_PERF_DONE_INTR_SHIFT                       _MK_SHIFT_CONST(28)
+#define DVC_STATUS_REG_0_TGT_PERF_DONE_INTR_FIELD                       (_MK_MASK_CONST(0x1) << DVC_STATUS_REG_0_TGT_PERF_DONE_INTR_SHIFT)
+#define DVC_STATUS_REG_0_TGT_PERF_DONE_INTR_RANGE                       28:28
+#define DVC_STATUS_REG_0_TGT_PERF_DONE_INTR_WOFFSET                     0x0
+#define DVC_STATUS_REG_0_TGT_PERF_DONE_INTR_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_STATUS_REG_0_TGT_PERF_DONE_INTR_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define DVC_STATUS_REG_0_TGT_PERF_DONE_INTR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define DVC_STATUS_REG_0_TGT_PERF_DONE_INTR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// DVC/PMU is busy adjusting voltage.
+#define DVC_STATUS_REG_0_BUSY_SHIFT                     _MK_SHIFT_CONST(27)
+#define DVC_STATUS_REG_0_BUSY_FIELD                     (_MK_MASK_CONST(0x1) << DVC_STATUS_REG_0_BUSY_SHIFT)
+#define DVC_STATUS_REG_0_BUSY_RANGE                     27:27
+#define DVC_STATUS_REG_0_BUSY_WOFFSET                   0x0
+#define DVC_STATUS_REG_0_BUSY_DEFAULT                   _MK_MASK_CONST(0x0)
+#define DVC_STATUS_REG_0_BUSY_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define DVC_STATUS_REG_0_BUSY_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_STATUS_REG_0_BUSY_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Carry output from the adder of the new ring oscillator
+#define DVC_STATUS_REG_0_CARRY_OUT_SHIFT                        _MK_SHIFT_CONST(26)
+#define DVC_STATUS_REG_0_CARRY_OUT_FIELD                        (_MK_MASK_CONST(0x1) << DVC_STATUS_REG_0_CARRY_OUT_SHIFT)
+#define DVC_STATUS_REG_0_CARRY_OUT_RANGE                        26:26
+#define DVC_STATUS_REG_0_CARRY_OUT_WOFFSET                      0x0
+#define DVC_STATUS_REG_0_CARRY_OUT_DEFAULT                      _MK_MASK_CONST(0x0)
+#define DVC_STATUS_REG_0_CARRY_OUT_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define DVC_STATUS_REG_0_CARRY_OUT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define DVC_STATUS_REG_0_CARRY_OUT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// I2C Status bits 
+#define DVC_STATUS_REG_0_I2C_STATUS_SHIFT                       _MK_SHIFT_CONST(22)
+#define DVC_STATUS_REG_0_I2C_STATUS_FIELD                       (_MK_MASK_CONST(0xf) << DVC_STATUS_REG_0_I2C_STATUS_SHIFT)
+#define DVC_STATUS_REG_0_I2C_STATUS_RANGE                       25:22
+#define DVC_STATUS_REG_0_I2C_STATUS_WOFFSET                     0x0
+#define DVC_STATUS_REG_0_I2C_STATUS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_STATUS_REG_0_I2C_STATUS_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define DVC_STATUS_REG_0_I2C_STATUS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define DVC_STATUS_REG_0_I2C_STATUS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Indicates error for I2C master in data transfer
+#define DVC_STATUS_REG_0_I2C_ERROR_SHIFT                        _MK_SHIFT_CONST(21)
+#define DVC_STATUS_REG_0_I2C_ERROR_FIELD                        (_MK_MASK_CONST(0x1) << DVC_STATUS_REG_0_I2C_ERROR_SHIFT)
+#define DVC_STATUS_REG_0_I2C_ERROR_RANGE                        21:21
+#define DVC_STATUS_REG_0_I2C_ERROR_WOFFSET                      0x0
+#define DVC_STATUS_REG_0_I2C_ERROR_DEFAULT                      _MK_MASK_CONST(0x0)
+#define DVC_STATUS_REG_0_I2C_ERROR_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define DVC_STATUS_REG_0_I2C_ERROR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define DVC_STATUS_REG_0_I2C_ERROR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Measured performance count less than target performance count condition detected.
+#define DVC_STATUS_REG_0_TGT_PM_UNDERRUN_SHIFT                  _MK_SHIFT_CONST(20)
+#define DVC_STATUS_REG_0_TGT_PM_UNDERRUN_FIELD                  (_MK_MASK_CONST(0x1) << DVC_STATUS_REG_0_TGT_PM_UNDERRUN_SHIFT)
+#define DVC_STATUS_REG_0_TGT_PM_UNDERRUN_RANGE                  20:20
+#define DVC_STATUS_REG_0_TGT_PM_UNDERRUN_WOFFSET                        0x0
+#define DVC_STATUS_REG_0_TGT_PM_UNDERRUN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_STATUS_REG_0_TGT_PM_UNDERRUN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define DVC_STATUS_REG_0_TGT_PM_UNDERRUN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_STATUS_REG_0_TGT_PM_UNDERRUN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Voltage adjustment exceeds the limit
+#define DVC_STATUS_REG_0_VADJ_ERR_SHIFT                 _MK_SHIFT_CONST(19)
+#define DVC_STATUS_REG_0_VADJ_ERR_FIELD                 (_MK_MASK_CONST(0x1) << DVC_STATUS_REG_0_VADJ_ERR_SHIFT)
+#define DVC_STATUS_REG_0_VADJ_ERR_RANGE                 19:19
+#define DVC_STATUS_REG_0_VADJ_ERR_WOFFSET                       0x0
+#define DVC_STATUS_REG_0_VADJ_ERR_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_STATUS_REG_0_VADJ_ERR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define DVC_STATUS_REG_0_VADJ_ERR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_STATUS_REG_0_VADJ_ERR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Value of the voltage that has been applied.
+#define DVC_STATUS_REG_0_CURR_VOLT_SHIFT                        _MK_SHIFT_CONST(14)
+#define DVC_STATUS_REG_0_CURR_VOLT_FIELD                        (_MK_MASK_CONST(0x1f) << DVC_STATUS_REG_0_CURR_VOLT_SHIFT)
+#define DVC_STATUS_REG_0_CURR_VOLT_RANGE                        18:14
+#define DVC_STATUS_REG_0_CURR_VOLT_WOFFSET                      0x0
+#define DVC_STATUS_REG_0_CURR_VOLT_DEFAULT                      _MK_MASK_CONST(0x18)
+#define DVC_STATUS_REG_0_CURR_VOLT_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define DVC_STATUS_REG_0_CURR_VOLT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define DVC_STATUS_REG_0_CURR_VOLT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Performance monitor sample value for the last sample
+#define DVC_STATUS_REG_0_PMON_VALUE_SHIFT                       _MK_SHIFT_CONST(0)
+#define DVC_STATUS_REG_0_PMON_VALUE_FIELD                       (_MK_MASK_CONST(0x3fff) << DVC_STATUS_REG_0_PMON_VALUE_SHIFT)
+#define DVC_STATUS_REG_0_PMON_VALUE_RANGE                       13:0
+#define DVC_STATUS_REG_0_PMON_VALUE_WOFFSET                     0x0
+#define DVC_STATUS_REG_0_PMON_VALUE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_STATUS_REG_0_PMON_VALUE_DEFAULT_MASK                        _MK_MASK_CONST(0x3fff)
+#define DVC_STATUS_REG_0_PMON_VALUE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define DVC_STATUS_REG_0_PMON_VALUE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register DVC_I2C_CTRL_REG_0  
+#define DVC_I2C_CTRL_REG_0                      _MK_ADDR_CONST(0x10)
+#define DVC_I2C_CTRL_REG_0_SECURE                       0x0
+#define DVC_I2C_CTRL_REG_0_WORD_COUNT                   0x1
+#define DVC_I2C_CTRL_REG_0_RESET_VAL                    _MK_MASK_CONST(0x14514000)
+#define DVC_I2C_CTRL_REG_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define DVC_I2C_CTRL_REG_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define DVC_I2C_CTRL_REG_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define DVC_I2C_CTRL_REG_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
+#define DVC_I2C_CTRL_REG_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
+// 1 or 2 or 3 Commands for writing to PMU-I2C slave.
+// 000=>  1 cmd vsel1 only to core
+// 001=>  2 cmd's vsel1 & vsel2 to the core & AO
+// 010=>  3 cmd's vsel1 & vsel2 & vsel3 to the core, AO and CPU
+// 011=> NA
+// 100 => 2 cmd's vsel1 to the core, vsel2 is S/W controlled
+// 101 & 110 = > NA
+// 111 => 3 cmd's vsel1 to the core , vsel2 & vsel3 are S/W controlled
+#define DVC_I2C_CTRL_REG_0_MULTI_CMD_SHIFT                      _MK_SHIFT_CONST(29)
+#define DVC_I2C_CTRL_REG_0_MULTI_CMD_FIELD                      (_MK_MASK_CONST(0x7) << DVC_I2C_CTRL_REG_0_MULTI_CMD_SHIFT)
+#define DVC_I2C_CTRL_REG_0_MULTI_CMD_RANGE                      31:29
+#define DVC_I2C_CTRL_REG_0_MULTI_CMD_WOFFSET                    0x0
+#define DVC_I2C_CTRL_REG_0_MULTI_CMD_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_I2C_CTRL_REG_0_MULTI_CMD_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define DVC_I2C_CTRL_REG_0_MULTI_CMD_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define DVC_I2C_CTRL_REG_0_MULTI_CMD_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Size of vsel3 to match with PMU
+#define DVC_I2C_CTRL_REG_0_SIZE3_SHIFT                  _MK_SHIFT_CONST(26)
+#define DVC_I2C_CTRL_REG_0_SIZE3_FIELD                  (_MK_MASK_CONST(0x7) << DVC_I2C_CTRL_REG_0_SIZE3_SHIFT)
+#define DVC_I2C_CTRL_REG_0_SIZE3_RANGE                  28:26
+#define DVC_I2C_CTRL_REG_0_SIZE3_WOFFSET                        0x0
+#define DVC_I2C_CTRL_REG_0_SIZE3_DEFAULT                        _MK_MASK_CONST(0x5)
+#define DVC_I2C_CTRL_REG_0_SIZE3_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
+#define DVC_I2C_CTRL_REG_0_SIZE3_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_I2C_CTRL_REG_0_SIZE3_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Shift vsel3 to match with PMU
+#define DVC_I2C_CTRL_REG_0_SHIFT3_SHIFT                 _MK_SHIFT_CONST(23)
+#define DVC_I2C_CTRL_REG_0_SHIFT3_FIELD                 (_MK_MASK_CONST(0x7) << DVC_I2C_CTRL_REG_0_SHIFT3_SHIFT)
+#define DVC_I2C_CTRL_REG_0_SHIFT3_RANGE                 25:23
+#define DVC_I2C_CTRL_REG_0_SHIFT3_WOFFSET                       0x0
+#define DVC_I2C_CTRL_REG_0_SHIFT3_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_I2C_CTRL_REG_0_SHIFT3_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
+#define DVC_I2C_CTRL_REG_0_SHIFT3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_I2C_CTRL_REG_0_SHIFT3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Size of vsel2 to match with PMU
+#define DVC_I2C_CTRL_REG_0_SIZE2_SHIFT                  _MK_SHIFT_CONST(20)
+#define DVC_I2C_CTRL_REG_0_SIZE2_FIELD                  (_MK_MASK_CONST(0x7) << DVC_I2C_CTRL_REG_0_SIZE2_SHIFT)
+#define DVC_I2C_CTRL_REG_0_SIZE2_RANGE                  22:20
+#define DVC_I2C_CTRL_REG_0_SIZE2_WOFFSET                        0x0
+#define DVC_I2C_CTRL_REG_0_SIZE2_DEFAULT                        _MK_MASK_CONST(0x5)
+#define DVC_I2C_CTRL_REG_0_SIZE2_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
+#define DVC_I2C_CTRL_REG_0_SIZE2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_I2C_CTRL_REG_0_SIZE2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Shift vsel2 to match with PMU
+#define DVC_I2C_CTRL_REG_0_SHIFT2_SHIFT                 _MK_SHIFT_CONST(17)
+#define DVC_I2C_CTRL_REG_0_SHIFT2_FIELD                 (_MK_MASK_CONST(0x7) << DVC_I2C_CTRL_REG_0_SHIFT2_SHIFT)
+#define DVC_I2C_CTRL_REG_0_SHIFT2_RANGE                 19:17
+#define DVC_I2C_CTRL_REG_0_SHIFT2_WOFFSET                       0x0
+#define DVC_I2C_CTRL_REG_0_SHIFT2_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_I2C_CTRL_REG_0_SHIFT2_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
+#define DVC_I2C_CTRL_REG_0_SHIFT2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_I2C_CTRL_REG_0_SHIFT2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Size of vsel to match with PMU
+#define DVC_I2C_CTRL_REG_0_SIZE1_SHIFT                  _MK_SHIFT_CONST(14)
+#define DVC_I2C_CTRL_REG_0_SIZE1_FIELD                  (_MK_MASK_CONST(0x7) << DVC_I2C_CTRL_REG_0_SIZE1_SHIFT)
+#define DVC_I2C_CTRL_REG_0_SIZE1_RANGE                  16:14
+#define DVC_I2C_CTRL_REG_0_SIZE1_WOFFSET                        0x0
+#define DVC_I2C_CTRL_REG_0_SIZE1_DEFAULT                        _MK_MASK_CONST(0x5)
+#define DVC_I2C_CTRL_REG_0_SIZE1_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
+#define DVC_I2C_CTRL_REG_0_SIZE1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_I2C_CTRL_REG_0_SIZE1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Shift vsel to match with PMU
+#define DVC_I2C_CTRL_REG_0_SHIFT1_SHIFT                 _MK_SHIFT_CONST(11)
+#define DVC_I2C_CTRL_REG_0_SHIFT1_FIELD                 (_MK_MASK_CONST(0x7) << DVC_I2C_CTRL_REG_0_SHIFT1_SHIFT)
+#define DVC_I2C_CTRL_REG_0_SHIFT1_RANGE                 13:11
+#define DVC_I2C_CTRL_REG_0_SHIFT1_WOFFSET                       0x0
+#define DVC_I2C_CTRL_REG_0_SHIFT1_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_I2C_CTRL_REG_0_SHIFT1_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
+#define DVC_I2C_CTRL_REG_0_SHIFT1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_I2C_CTRL_REG_0_SHIFT1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// 7 bit or 10 bit addressing
+#define DVC_I2C_CTRL_REG_0_ADDR_7BIT_10BIT_SHIFT                        _MK_SHIFT_CONST(10)
+#define DVC_I2C_CTRL_REG_0_ADDR_7BIT_10BIT_FIELD                        (_MK_MASK_CONST(0x1) << DVC_I2C_CTRL_REG_0_ADDR_7BIT_10BIT_SHIFT)
+#define DVC_I2C_CTRL_REG_0_ADDR_7BIT_10BIT_RANGE                        10:10
+#define DVC_I2C_CTRL_REG_0_ADDR_7BIT_10BIT_WOFFSET                      0x0
+#define DVC_I2C_CTRL_REG_0_ADDR_7BIT_10BIT_DEFAULT                      _MK_MASK_CONST(0x0)
+#define DVC_I2C_CTRL_REG_0_ADDR_7BIT_10BIT_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define DVC_I2C_CTRL_REG_0_ADDR_7BIT_10BIT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define DVC_I2C_CTRL_REG_0_ADDR_7BIT_10BIT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// External slave ID Address
+#define DVC_I2C_CTRL_REG_0_SLAVE_ID_SHIFT                       _MK_SHIFT_CONST(0)
+#define DVC_I2C_CTRL_REG_0_SLAVE_ID_FIELD                       (_MK_MASK_CONST(0x3ff) << DVC_I2C_CTRL_REG_0_SLAVE_ID_SHIFT)
+#define DVC_I2C_CTRL_REG_0_SLAVE_ID_RANGE                       9:0
+#define DVC_I2C_CTRL_REG_0_SLAVE_ID_WOFFSET                     0x0
+#define DVC_I2C_CTRL_REG_0_SLAVE_ID_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_I2C_CTRL_REG_0_SLAVE_ID_DEFAULT_MASK                        _MK_MASK_CONST(0x3ff)
+#define DVC_I2C_CTRL_REG_0_SLAVE_ID_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define DVC_I2C_CTRL_REG_0_SLAVE_ID_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register DVC_I2C_ADDR_DATA_REG_0  
+#define DVC_I2C_ADDR_DATA_REG_0                 _MK_ADDR_CONST(0x14)
+#define DVC_I2C_ADDR_DATA_REG_0_SECURE                  0x0
+#define DVC_I2C_ADDR_DATA_REG_0_WORD_COUNT                      0x1
+#define DVC_I2C_ADDR_DATA_REG_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define DVC_I2C_ADDR_DATA_REG_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define DVC_I2C_ADDR_DATA_REG_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define DVC_I2C_ADDR_DATA_REG_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define DVC_I2C_ADDR_DATA_REG_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define DVC_I2C_ADDR_DATA_REG_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Optional second data
+#define DVC_I2C_ADDR_DATA_REG_0_DATA2_SHIFT                     _MK_SHIFT_CONST(24)
+#define DVC_I2C_ADDR_DATA_REG_0_DATA2_FIELD                     (_MK_MASK_CONST(0xff) << DVC_I2C_ADDR_DATA_REG_0_DATA2_SHIFT)
+#define DVC_I2C_ADDR_DATA_REG_0_DATA2_RANGE                     31:24
+#define DVC_I2C_ADDR_DATA_REG_0_DATA2_WOFFSET                   0x0
+#define DVC_I2C_ADDR_DATA_REG_0_DATA2_DEFAULT                   _MK_MASK_CONST(0x0)
+#define DVC_I2C_ADDR_DATA_REG_0_DATA2_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define DVC_I2C_ADDR_DATA_REG_0_DATA2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_I2C_ADDR_DATA_REG_0_DATA2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Optional second addr
+#define DVC_I2C_ADDR_DATA_REG_0_ADDR2_SHIFT                     _MK_SHIFT_CONST(16)
+#define DVC_I2C_ADDR_DATA_REG_0_ADDR2_FIELD                     (_MK_MASK_CONST(0xff) << DVC_I2C_ADDR_DATA_REG_0_ADDR2_SHIFT)
+#define DVC_I2C_ADDR_DATA_REG_0_ADDR2_RANGE                     23:16
+#define DVC_I2C_ADDR_DATA_REG_0_ADDR2_WOFFSET                   0x0
+#define DVC_I2C_ADDR_DATA_REG_0_ADDR2_DEFAULT                   _MK_MASK_CONST(0x0)
+#define DVC_I2C_ADDR_DATA_REG_0_ADDR2_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define DVC_I2C_ADDR_DATA_REG_0_ADDR2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_I2C_ADDR_DATA_REG_0_ADDR2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Default data
+#define DVC_I2C_ADDR_DATA_REG_0_DATA1_SHIFT                     _MK_SHIFT_CONST(8)
+#define DVC_I2C_ADDR_DATA_REG_0_DATA1_FIELD                     (_MK_MASK_CONST(0xff) << DVC_I2C_ADDR_DATA_REG_0_DATA1_SHIFT)
+#define DVC_I2C_ADDR_DATA_REG_0_DATA1_RANGE                     15:8
+#define DVC_I2C_ADDR_DATA_REG_0_DATA1_WOFFSET                   0x0
+#define DVC_I2C_ADDR_DATA_REG_0_DATA1_DEFAULT                   _MK_MASK_CONST(0x0)
+#define DVC_I2C_ADDR_DATA_REG_0_DATA1_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define DVC_I2C_ADDR_DATA_REG_0_DATA1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_I2C_ADDR_DATA_REG_0_DATA1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Addr for voltage sel
+#define DVC_I2C_ADDR_DATA_REG_0_ADDR1_SHIFT                     _MK_SHIFT_CONST(0)
+#define DVC_I2C_ADDR_DATA_REG_0_ADDR1_FIELD                     (_MK_MASK_CONST(0xff) << DVC_I2C_ADDR_DATA_REG_0_ADDR1_SHIFT)
+#define DVC_I2C_ADDR_DATA_REG_0_ADDR1_RANGE                     7:0
+#define DVC_I2C_ADDR_DATA_REG_0_ADDR1_WOFFSET                   0x0
+#define DVC_I2C_ADDR_DATA_REG_0_ADDR1_DEFAULT                   _MK_MASK_CONST(0x0)
+#define DVC_I2C_ADDR_DATA_REG_0_ADDR1_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define DVC_I2C_ADDR_DATA_REG_0_ADDR1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_I2C_ADDR_DATA_REG_0_ADDR1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register DVC_RING_OSC_ADDER_IN1_0  
+#define DVC_RING_OSC_ADDER_IN1_0                        _MK_ADDR_CONST(0x18)
+#define DVC_RING_OSC_ADDER_IN1_0_SECURE                         0x0
+#define DVC_RING_OSC_ADDER_IN1_0_WORD_COUNT                     0x1
+#define DVC_RING_OSC_ADDER_IN1_0_RESET_VAL                      _MK_MASK_CONST(0xffffffff)
+#define DVC_RING_OSC_ADDER_IN1_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
+#define DVC_RING_OSC_ADDER_IN1_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define DVC_RING_OSC_ADDER_IN1_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define DVC_RING_OSC_ADDER_IN1_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define DVC_RING_OSC_ADDER_IN1_0_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
+// Ring osc adder input1
+#define DVC_RING_OSC_ADDER_IN1_0_ADDER_IN1_SHIFT                        _MK_SHIFT_CONST(0)
+#define DVC_RING_OSC_ADDER_IN1_0_ADDER_IN1_FIELD                        (_MK_MASK_CONST(0xffffffff) << DVC_RING_OSC_ADDER_IN1_0_ADDER_IN1_SHIFT)
+#define DVC_RING_OSC_ADDER_IN1_0_ADDER_IN1_RANGE                        31:0
+#define DVC_RING_OSC_ADDER_IN1_0_ADDER_IN1_WOFFSET                      0x0
+#define DVC_RING_OSC_ADDER_IN1_0_ADDER_IN1_DEFAULT                      _MK_MASK_CONST(0xffffffff)
+#define DVC_RING_OSC_ADDER_IN1_0_ADDER_IN1_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
+#define DVC_RING_OSC_ADDER_IN1_0_ADDER_IN1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define DVC_RING_OSC_ADDER_IN1_0_ADDER_IN1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define DVC_RING_OSC_ADDER_IN1_0_ADDER_IN1_INIT_ENUM                    -1
+
+
+// Register DVC_RING_OSC_ADDER_IN2_0  
+#define DVC_RING_OSC_ADDER_IN2_0                        _MK_ADDR_CONST(0x1c)
+#define DVC_RING_OSC_ADDER_IN2_0_SECURE                         0x0
+#define DVC_RING_OSC_ADDER_IN2_0_WORD_COUNT                     0x1
+#define DVC_RING_OSC_ADDER_IN2_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_RING_OSC_ADDER_IN2_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
+#define DVC_RING_OSC_ADDER_IN2_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define DVC_RING_OSC_ADDER_IN2_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define DVC_RING_OSC_ADDER_IN2_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define DVC_RING_OSC_ADDER_IN2_0_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
+// Ring osc adder input2
+#define DVC_RING_OSC_ADDER_IN2_0_ADDER_IN2_SHIFT                        _MK_SHIFT_CONST(0)
+#define DVC_RING_OSC_ADDER_IN2_0_ADDER_IN2_FIELD                        (_MK_MASK_CONST(0xffffffff) << DVC_RING_OSC_ADDER_IN2_0_ADDER_IN2_SHIFT)
+#define DVC_RING_OSC_ADDER_IN2_0_ADDER_IN2_RANGE                        31:0
+#define DVC_RING_OSC_ADDER_IN2_0_ADDER_IN2_WOFFSET                      0x0
+#define DVC_RING_OSC_ADDER_IN2_0_ADDER_IN2_DEFAULT                      _MK_MASK_CONST(0x0)
+#define DVC_RING_OSC_ADDER_IN2_0_ADDER_IN2_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
+#define DVC_RING_OSC_ADDER_IN2_0_ADDER_IN2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define DVC_RING_OSC_ADDER_IN2_0_ADDER_IN2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register DVC_REQ_REGISTER_0  
+#define DVC_REQ_REGISTER_0                      _MK_ADDR_CONST(0x20)
+#define DVC_REQ_REGISTER_0_SECURE                       0x0
+#define DVC_REQ_REGISTER_0_WORD_COUNT                   0x1
+#define DVC_REQ_REGISTER_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define DVC_REQ_REGISTER_0_RESET_MASK                   _MK_MASK_CONST(0x7f)
+#define DVC_REQ_REGISTER_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define DVC_REQ_REGISTER_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define DVC_REQ_REGISTER_0_READ_MASK                    _MK_MASK_CONST(0x7f)
+#define DVC_REQ_REGISTER_0_WRITE_MASK                   _MK_MASK_CONST(0x7f)
+// Self clearing bit , which firmware can use to trigger DVC voltage change
+#define DVC_REQ_REGISTER_0_REQ_VLD_SHIFT                        _MK_SHIFT_CONST(6)
+#define DVC_REQ_REGISTER_0_REQ_VLD_FIELD                        (_MK_MASK_CONST(0x1) << DVC_REQ_REGISTER_0_REQ_VLD_SHIFT)
+#define DVC_REQ_REGISTER_0_REQ_VLD_RANGE                        6:6
+#define DVC_REQ_REGISTER_0_REQ_VLD_WOFFSET                      0x0
+#define DVC_REQ_REGISTER_0_REQ_VLD_DEFAULT                      _MK_MASK_CONST(0x0)
+#define DVC_REQ_REGISTER_0_REQ_VLD_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define DVC_REQ_REGISTER_0_REQ_VLD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define DVC_REQ_REGISTER_0_REQ_VLD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define DVC_REQ_REGISTER_0_REQ_VLD_INVALID                      _MK_ENUM_CONST(0)
+#define DVC_REQ_REGISTER_0_REQ_VLD_VALID                        _MK_ENUM_CONST(1)
+
+// firmware target performance
+#define DVC_REQ_REGISTER_0_NORM_FREQ_SHIFT                      _MK_SHIFT_CONST(0)
+#define DVC_REQ_REGISTER_0_NORM_FREQ_FIELD                      (_MK_MASK_CONST(0x3f) << DVC_REQ_REGISTER_0_NORM_FREQ_SHIFT)
+#define DVC_REQ_REGISTER_0_NORM_FREQ_RANGE                      5:0
+#define DVC_REQ_REGISTER_0_NORM_FREQ_WOFFSET                    0x0
+#define DVC_REQ_REGISTER_0_NORM_FREQ_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_REQ_REGISTER_0_NORM_FREQ_DEFAULT_MASK                       _MK_MASK_CONST(0x3f)
+#define DVC_REQ_REGISTER_0_NORM_FREQ_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define DVC_REQ_REGISTER_0_NORM_FREQ_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register DVC_I2C_ADDR_DATA_REG_3_0  
+#define DVC_I2C_ADDR_DATA_REG_3_0                       _MK_ADDR_CONST(0x24)
+#define DVC_I2C_ADDR_DATA_REG_3_0_SECURE                        0x0
+#define DVC_I2C_ADDR_DATA_REG_3_0_WORD_COUNT                    0x1
+#define DVC_I2C_ADDR_DATA_REG_3_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define DVC_I2C_ADDR_DATA_REG_3_0_RESET_MASK                    _MK_MASK_CONST(0xffff)
+#define DVC_I2C_ADDR_DATA_REG_3_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define DVC_I2C_ADDR_DATA_REG_3_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define DVC_I2C_ADDR_DATA_REG_3_0_READ_MASK                     _MK_MASK_CONST(0xffff)
+#define DVC_I2C_ADDR_DATA_REG_3_0_WRITE_MASK                    _MK_MASK_CONST(0xffff)
+//Default Data
+#define DVC_I2C_ADDR_DATA_REG_3_0_DATA3_SHIFT                   _MK_SHIFT_CONST(8)
+#define DVC_I2C_ADDR_DATA_REG_3_0_DATA3_FIELD                   (_MK_MASK_CONST(0xff) << DVC_I2C_ADDR_DATA_REG_3_0_DATA3_SHIFT)
+#define DVC_I2C_ADDR_DATA_REG_3_0_DATA3_RANGE                   15:8
+#define DVC_I2C_ADDR_DATA_REG_3_0_DATA3_WOFFSET                 0x0
+#define DVC_I2C_ADDR_DATA_REG_3_0_DATA3_DEFAULT                 _MK_MASK_CONST(0x0)
+#define DVC_I2C_ADDR_DATA_REG_3_0_DATA3_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define DVC_I2C_ADDR_DATA_REG_3_0_DATA3_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define DVC_I2C_ADDR_DATA_REG_3_0_DATA3_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+//Addr For Volatge sel 3
+#define DVC_I2C_ADDR_DATA_REG_3_0_ADDR3_SHIFT                   _MK_SHIFT_CONST(0)
+#define DVC_I2C_ADDR_DATA_REG_3_0_ADDR3_FIELD                   (_MK_MASK_CONST(0xff) << DVC_I2C_ADDR_DATA_REG_3_0_ADDR3_SHIFT)
+#define DVC_I2C_ADDR_DATA_REG_3_0_ADDR3_RANGE                   7:0
+#define DVC_I2C_ADDR_DATA_REG_3_0_ADDR3_WOFFSET                 0x0
+#define DVC_I2C_ADDR_DATA_REG_3_0_ADDR3_DEFAULT                 _MK_MASK_CONST(0x0)
+#define DVC_I2C_ADDR_DATA_REG_3_0_ADDR3_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define DVC_I2C_ADDR_DATA_REG_3_0_ADDR3_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define DVC_I2C_ADDR_DATA_REG_3_0_ADDR3_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Reserved address 40 [0x28] 
+
+// Reserved address 44 [0x2c] 
+
+// Reserved address 48 [0x30] 
+
+// Reserved address 52 [0x34] 
+
+// Reserved address 56 [0x38] 
+
+// Reserved address 60 [0x3c] 
+
+// Register DVC_I2C_CNFG_0  
+#define DVC_I2C_CNFG_0                  _MK_ADDR_CONST(0x40)
+#define DVC_I2C_CNFG_0_SECURE                   0x0
+#define DVC_I2C_CNFG_0_WORD_COUNT                       0x1
+#define DVC_I2C_CNFG_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define DVC_I2C_CNFG_0_RESET_MASK                       _MK_MASK_CONST(0x7fff)
+#define DVC_I2C_CNFG_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_I2C_CNFG_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define DVC_I2C_CNFG_0_READ_MASK                        _MK_MASK_CONST(0x7fff)
+#define DVC_I2C_CNFG_0_WRITE_MASK                       _MK_MASK_CONST(0x7fff)
+// Debounce period for sda and scl lines
+// 0 = No debounce
+// 1 = 2T
+// 2  = 4T
+// 3 =  6T etc
+// where T is the period of the fix PLL 
+//clk source coming to i2c.
+//Maximum debounce period programmable is 
+//14T.A debounce period of >50ns is desirable
+#define DVC_I2C_CNFG_0_DEBOUNCE_CNT_SHIFT                       _MK_SHIFT_CONST(12)
+#define DVC_I2C_CNFG_0_DEBOUNCE_CNT_FIELD                       (_MK_MASK_CONST(0x7) << DVC_I2C_CNFG_0_DEBOUNCE_CNT_SHIFT)
+#define DVC_I2C_CNFG_0_DEBOUNCE_CNT_RANGE                       14:12
+#define DVC_I2C_CNFG_0_DEBOUNCE_CNT_WOFFSET                     0x0
+#define DVC_I2C_CNFG_0_DEBOUNCE_CNT_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_I2C_CNFG_0_DEBOUNCE_CNT_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
+#define DVC_I2C_CNFG_0_DEBOUNCE_CNT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define DVC_I2C_CNFG_0_DEBOUNCE_CNT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Write 1 to enable new master fsm
+// 0 = old fsm
+#define DVC_I2C_CNFG_0_NEW_MASTER_FSM_SHIFT                     _MK_SHIFT_CONST(11)
+#define DVC_I2C_CNFG_0_NEW_MASTER_FSM_FIELD                     (_MK_MASK_CONST(0x1) << DVC_I2C_CNFG_0_NEW_MASTER_FSM_SHIFT)
+#define DVC_I2C_CNFG_0_NEW_MASTER_FSM_RANGE                     11:11
+#define DVC_I2C_CNFG_0_NEW_MASTER_FSM_WOFFSET                   0x0
+#define DVC_I2C_CNFG_0_NEW_MASTER_FSM_DEFAULT                   _MK_MASK_CONST(0x0)
+#define DVC_I2C_CNFG_0_NEW_MASTER_FSM_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define DVC_I2C_CNFG_0_NEW_MASTER_FSM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_I2C_CNFG_0_NEW_MASTER_FSM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define DVC_I2C_CNFG_0_NEW_MASTER_FSM_DISABLE                   _MK_ENUM_CONST(0)
+#define DVC_I2C_CNFG_0_NEW_MASTER_FSM_ENABLE                    _MK_ENUM_CONST(1)
+
+// Write 1 to initiate transfer in packet mode.
+#define DVC_I2C_CNFG_0_PACKET_MODE_EN_SHIFT                     _MK_SHIFT_CONST(10)
+#define DVC_I2C_CNFG_0_PACKET_MODE_EN_FIELD                     (_MK_MASK_CONST(0x1) << DVC_I2C_CNFG_0_PACKET_MODE_EN_SHIFT)
+#define DVC_I2C_CNFG_0_PACKET_MODE_EN_RANGE                     10:10
+#define DVC_I2C_CNFG_0_PACKET_MODE_EN_WOFFSET                   0x0
+#define DVC_I2C_CNFG_0_PACKET_MODE_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define DVC_I2C_CNFG_0_PACKET_MODE_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define DVC_I2C_CNFG_0_PACKET_MODE_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_I2C_CNFG_0_PACKET_MODE_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define DVC_I2C_CNFG_0_PACKET_MODE_EN_NOP                       _MK_ENUM_CONST(0)
+#define DVC_I2C_CNFG_0_PACKET_MODE_EN_GO                        _MK_ENUM_CONST(1)
+
+// Writing a 1 causes the master to initiate the
+// transaction in normal mode. Values of other  bits are not
+// affected when this bit is 1,Cleared by 
+// hardware.  Other bits of the register are
+// masked for writes when this bit is programmed
+// to one.hence,firware should first configure
+// all other registrs and  bits [8:0] of 
+// I2C_CNFG register before the bit
+// I2C_CNFG[9] is programmed to Zero.
+#define DVC_I2C_CNFG_0_SEND_SHIFT                       _MK_SHIFT_CONST(9)
+#define DVC_I2C_CNFG_0_SEND_FIELD                       (_MK_MASK_CONST(0x1) << DVC_I2C_CNFG_0_SEND_SHIFT)
+#define DVC_I2C_CNFG_0_SEND_RANGE                       9:9
+#define DVC_I2C_CNFG_0_SEND_WOFFSET                     0x0
+#define DVC_I2C_CNFG_0_SEND_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_I2C_CNFG_0_SEND_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define DVC_I2C_CNFG_0_SEND_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define DVC_I2C_CNFG_0_SEND_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_I2C_CNFG_0_SEND_NOP                 _MK_ENUM_CONST(0)
+#define DVC_I2C_CNFG_0_SEND_GO                  _MK_ENUM_CONST(1)
+
+// Enable mode to handle devices that do not generate ACK. 
+// 1 - dont look for an ack at the end of the Enable
+#define DVC_I2C_CNFG_0_NOACK_SHIFT                      _MK_SHIFT_CONST(8)
+#define DVC_I2C_CNFG_0_NOACK_FIELD                      (_MK_MASK_CONST(0x1) << DVC_I2C_CNFG_0_NOACK_SHIFT)
+#define DVC_I2C_CNFG_0_NOACK_RANGE                      8:8
+#define DVC_I2C_CNFG_0_NOACK_WOFFSET                    0x0
+#define DVC_I2C_CNFG_0_NOACK_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_I2C_CNFG_0_NOACK_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define DVC_I2C_CNFG_0_NOACK_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define DVC_I2C_CNFG_0_NOACK_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define DVC_I2C_CNFG_0_NOACK_DISABLE                    _MK_ENUM_CONST(0)
+#define DVC_I2C_CNFG_0_NOACK_ENABLE                     _MK_ENUM_CONST(1)
+
+// Read/Write Command for Slave 2:
+// 1 -  Read Transaction; 0 -  write Transaction.
+// For a 7-bit slave address,this bit must match
+// with the LSB of address byte for slave 2.
+// Valid only when  bit-4 of this register is 
+// set
+#define DVC_I2C_CNFG_0_CMD2_SHIFT                       _MK_SHIFT_CONST(7)
+#define DVC_I2C_CNFG_0_CMD2_FIELD                       (_MK_MASK_CONST(0x1) << DVC_I2C_CNFG_0_CMD2_SHIFT)
+#define DVC_I2C_CNFG_0_CMD2_RANGE                       7:7
+#define DVC_I2C_CNFG_0_CMD2_WOFFSET                     0x0
+#define DVC_I2C_CNFG_0_CMD2_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_I2C_CNFG_0_CMD2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define DVC_I2C_CNFG_0_CMD2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define DVC_I2C_CNFG_0_CMD2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_I2C_CNFG_0_CMD2_DISABLE                     _MK_ENUM_CONST(0)
+#define DVC_I2C_CNFG_0_CMD2_ENABLE                      _MK_ENUM_CONST(1)
+
+// Read/Write Command for Slave 1: 
+// 1 - Read Transaction; 0 -  write Transaction.
+// Command for Slave 1: For a 7-bit slave address
+// this bit must match with the LSB of address 
+// byte for slave1.
+#define DVC_I2C_CNFG_0_CMD1_SHIFT                       _MK_SHIFT_CONST(6)
+#define DVC_I2C_CNFG_0_CMD1_FIELD                       (_MK_MASK_CONST(0x1) << DVC_I2C_CNFG_0_CMD1_SHIFT)
+#define DVC_I2C_CNFG_0_CMD1_RANGE                       6:6
+#define DVC_I2C_CNFG_0_CMD1_WOFFSET                     0x0
+#define DVC_I2C_CNFG_0_CMD1_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_I2C_CNFG_0_CMD1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define DVC_I2C_CNFG_0_CMD1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define DVC_I2C_CNFG_0_CMD1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_I2C_CNFG_0_CMD1_DISABLE                     _MK_ENUM_CONST(0)
+#define DVC_I2C_CNFG_0_CMD1_ENABLE                      _MK_ENUM_CONST(1)
+
+//  1 = Yes, a Start byte needs to be  sent.
+#define DVC_I2C_CNFG_0_START_SHIFT                      _MK_SHIFT_CONST(5)
+#define DVC_I2C_CNFG_0_START_FIELD                      (_MK_MASK_CONST(0x1) << DVC_I2C_CNFG_0_START_SHIFT)
+#define DVC_I2C_CNFG_0_START_RANGE                      5:5
+#define DVC_I2C_CNFG_0_START_WOFFSET                    0x0
+#define DVC_I2C_CNFG_0_START_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_I2C_CNFG_0_START_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define DVC_I2C_CNFG_0_START_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define DVC_I2C_CNFG_0_START_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define DVC_I2C_CNFG_0_START_DISABLE                    _MK_ENUM_CONST(0)
+#define DVC_I2C_CNFG_0_START_ENABLE                     _MK_ENUM_CONST(1)
+
+//  1 - Enables a two slave transaction ;
+//  0 = No command for Slave 2 present.
+#define DVC_I2C_CNFG_0_SLV2_SHIFT                       _MK_SHIFT_CONST(4)
+#define DVC_I2C_CNFG_0_SLV2_FIELD                       (_MK_MASK_CONST(0x1) << DVC_I2C_CNFG_0_SLV2_SHIFT)
+#define DVC_I2C_CNFG_0_SLV2_RANGE                       4:4
+#define DVC_I2C_CNFG_0_SLV2_WOFFSET                     0x0
+#define DVC_I2C_CNFG_0_SLV2_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_I2C_CNFG_0_SLV2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define DVC_I2C_CNFG_0_SLV2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define DVC_I2C_CNFG_0_SLV2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_I2C_CNFG_0_SLV2_DISABLE                     _MK_ENUM_CONST(0)
+#define DVC_I2C_CNFG_0_SLV2_ENABLE                      _MK_ENUM_CONST(1)
+
+// The Number of bytes to be transmitted per
+// transaction 000= 1byte ... 111 = 8bytes;
+// In a two slave transaction number of bytes
+// should be programmed less than 011.
+#define DVC_I2C_CNFG_0_LENGTH_SHIFT                     _MK_SHIFT_CONST(1)
+#define DVC_I2C_CNFG_0_LENGTH_FIELD                     (_MK_MASK_CONST(0x7) << DVC_I2C_CNFG_0_LENGTH_SHIFT)
+#define DVC_I2C_CNFG_0_LENGTH_RANGE                     3:1
+#define DVC_I2C_CNFG_0_LENGTH_WOFFSET                   0x0
+#define DVC_I2C_CNFG_0_LENGTH_DEFAULT                   _MK_MASK_CONST(0x0)
+#define DVC_I2C_CNFG_0_LENGTH_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define DVC_I2C_CNFG_0_LENGTH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_I2C_CNFG_0_LENGTH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Address mode defines whether a 7-bit or a 
+// 10-bit slave address is programmed. 1 = 10-bit
+// device address 0  = 7-bit device address  
+#define DVC_I2C_CNFG_0_A_MOD_SHIFT                      _MK_SHIFT_CONST(0)
+#define DVC_I2C_CNFG_0_A_MOD_FIELD                      (_MK_MASK_CONST(0x1) << DVC_I2C_CNFG_0_A_MOD_SHIFT)
+#define DVC_I2C_CNFG_0_A_MOD_RANGE                      0:0
+#define DVC_I2C_CNFG_0_A_MOD_WOFFSET                    0x0
+#define DVC_I2C_CNFG_0_A_MOD_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_I2C_CNFG_0_A_MOD_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define DVC_I2C_CNFG_0_A_MOD_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define DVC_I2C_CNFG_0_A_MOD_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define DVC_I2C_CNFG_0_A_MOD_SEVEN_BIT_DEVICE_ADDRESS                   _MK_ENUM_CONST(0)
+#define DVC_I2C_CNFG_0_A_MOD_TEN_BIT_DEVICE_ADDRESS                     _MK_ENUM_CONST(1)
+
+
+// Register DVC_I2C_CMD_ADDR0_0  
+#define DVC_I2C_CMD_ADDR0_0                     _MK_ADDR_CONST(0x44)
+#define DVC_I2C_CMD_ADDR0_0_SECURE                      0x0
+#define DVC_I2C_CMD_ADDR0_0_WORD_COUNT                  0x1
+#define DVC_I2C_CMD_ADDR0_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_I2C_CMD_ADDR0_0_RESET_MASK                  _MK_MASK_CONST(0x3ff)
+#define DVC_I2C_CMD_ADDR0_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_I2C_CMD_ADDR0_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_I2C_CMD_ADDR0_0_READ_MASK                   _MK_MASK_CONST(0x3ff)
+#define DVC_I2C_CMD_ADDR0_0_WRITE_MASK                  _MK_MASK_CONST(0x3ff)
+// In case of 7-Bit mode address is written in the 
+// I2C_CMD_ADDR0[7:1] and I2C_CMD_ADDR0[0] indicates the
+// read/write transaction.I2C_CMD_ADDR0[0] bit must match 
+// with the I2C_CNFG[6].
+// In case of 10-Bit mode addess is written in 
+// I2C_CMD_ADDR0[9:0] and I2C_CNFG[6]  indicates the 
+// read/write transaction. 
+#define DVC_I2C_CMD_ADDR0_0_ADDR0_SHIFT                 _MK_SHIFT_CONST(0)
+#define DVC_I2C_CMD_ADDR0_0_ADDR0_FIELD                 (_MK_MASK_CONST(0x3ff) << DVC_I2C_CMD_ADDR0_0_ADDR0_SHIFT)
+#define DVC_I2C_CMD_ADDR0_0_ADDR0_RANGE                 9:0
+#define DVC_I2C_CMD_ADDR0_0_ADDR0_WOFFSET                       0x0
+#define DVC_I2C_CMD_ADDR0_0_ADDR0_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_I2C_CMD_ADDR0_0_ADDR0_DEFAULT_MASK                  _MK_MASK_CONST(0x3ff)
+#define DVC_I2C_CMD_ADDR0_0_ADDR0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_I2C_CMD_ADDR0_0_ADDR0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register DVC_I2C_CMD_ADDR1_0  
+#define DVC_I2C_CMD_ADDR1_0                     _MK_ADDR_CONST(0x48)
+#define DVC_I2C_CMD_ADDR1_0_SECURE                      0x0
+#define DVC_I2C_CMD_ADDR1_0_WORD_COUNT                  0x1
+#define DVC_I2C_CMD_ADDR1_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_I2C_CMD_ADDR1_0_RESET_MASK                  _MK_MASK_CONST(0x3ff)
+#define DVC_I2C_CMD_ADDR1_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_I2C_CMD_ADDR1_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_I2C_CMD_ADDR1_0_READ_MASK                   _MK_MASK_CONST(0x3ff)
+#define DVC_I2C_CMD_ADDR1_0_WRITE_MASK                  _MK_MASK_CONST(0x3ff)
+// In case of 7-Bit mode address is written in the 
+// I2C_CMD_ADDR0[7:1] and I2C_CMD_ADDR0[0] indicates the 
+// read/write transaction.I2C_CMD_ADDR0[0] bit must match
+// with the I2C_CNFG[7].        
+// In case of 10-Bit mode addess is written in 
+// I2C_CMD_ADDR0[9:0] and I2C_CNFG[7] indicates the 
+// read/write transaction. 
+#define DVC_I2C_CMD_ADDR1_0_ADDR1_SHIFT                 _MK_SHIFT_CONST(0)
+#define DVC_I2C_CMD_ADDR1_0_ADDR1_FIELD                 (_MK_MASK_CONST(0x3ff) << DVC_I2C_CMD_ADDR1_0_ADDR1_SHIFT)
+#define DVC_I2C_CMD_ADDR1_0_ADDR1_RANGE                 9:0
+#define DVC_I2C_CMD_ADDR1_0_ADDR1_WOFFSET                       0x0
+#define DVC_I2C_CMD_ADDR1_0_ADDR1_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_I2C_CMD_ADDR1_0_ADDR1_DEFAULT_MASK                  _MK_MASK_CONST(0x3ff)
+#define DVC_I2C_CMD_ADDR1_0_ADDR1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_I2C_CMD_ADDR1_0_ADDR1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register DVC_I2C_CMD_DATA1_0  
+#define DVC_I2C_CMD_DATA1_0                     _MK_ADDR_CONST(0x4c)
+#define DVC_I2C_CMD_DATA1_0_SECURE                      0x0
+#define DVC_I2C_CMD_DATA1_0_WORD_COUNT                  0x1
+#define DVC_I2C_CMD_DATA1_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_I2C_CMD_DATA1_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define DVC_I2C_CMD_DATA1_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_I2C_CMD_DATA1_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_I2C_CMD_DATA1_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define DVC_I2C_CMD_DATA1_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+// Fourth data byte to be sent/received
+#define DVC_I2C_CMD_DATA1_0_DATA4_SHIFT                 _MK_SHIFT_CONST(24)
+#define DVC_I2C_CMD_DATA1_0_DATA4_FIELD                 (_MK_MASK_CONST(0xff) << DVC_I2C_CMD_DATA1_0_DATA4_SHIFT)
+#define DVC_I2C_CMD_DATA1_0_DATA4_RANGE                 31:24
+#define DVC_I2C_CMD_DATA1_0_DATA4_WOFFSET                       0x0
+#define DVC_I2C_CMD_DATA1_0_DATA4_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_I2C_CMD_DATA1_0_DATA4_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define DVC_I2C_CMD_DATA1_0_DATA4_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_I2C_CMD_DATA1_0_DATA4_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Third data byte to be sent/received
+#define DVC_I2C_CMD_DATA1_0_DATA3_SHIFT                 _MK_SHIFT_CONST(16)
+#define DVC_I2C_CMD_DATA1_0_DATA3_FIELD                 (_MK_MASK_CONST(0xff) << DVC_I2C_CMD_DATA1_0_DATA3_SHIFT)
+#define DVC_I2C_CMD_DATA1_0_DATA3_RANGE                 23:16
+#define DVC_I2C_CMD_DATA1_0_DATA3_WOFFSET                       0x0
+#define DVC_I2C_CMD_DATA1_0_DATA3_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_I2C_CMD_DATA1_0_DATA3_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define DVC_I2C_CMD_DATA1_0_DATA3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_I2C_CMD_DATA1_0_DATA3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Second data byte to be sent/received
+#define DVC_I2C_CMD_DATA1_0_DATA2_SHIFT                 _MK_SHIFT_CONST(8)
+#define DVC_I2C_CMD_DATA1_0_DATA2_FIELD                 (_MK_MASK_CONST(0xff) << DVC_I2C_CMD_DATA1_0_DATA2_SHIFT)
+#define DVC_I2C_CMD_DATA1_0_DATA2_RANGE                 15:8
+#define DVC_I2C_CMD_DATA1_0_DATA2_WOFFSET                       0x0
+#define DVC_I2C_CMD_DATA1_0_DATA2_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_I2C_CMD_DATA1_0_DATA2_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define DVC_I2C_CMD_DATA1_0_DATA2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_I2C_CMD_DATA1_0_DATA2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// This register contains the first data byte to be  sent/received.
+#define DVC_I2C_CMD_DATA1_0_DATA1_SHIFT                 _MK_SHIFT_CONST(0)
+#define DVC_I2C_CMD_DATA1_0_DATA1_FIELD                 (_MK_MASK_CONST(0xff) << DVC_I2C_CMD_DATA1_0_DATA1_SHIFT)
+#define DVC_I2C_CMD_DATA1_0_DATA1_RANGE                 7:0
+#define DVC_I2C_CMD_DATA1_0_DATA1_WOFFSET                       0x0
+#define DVC_I2C_CMD_DATA1_0_DATA1_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_I2C_CMD_DATA1_0_DATA1_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define DVC_I2C_CMD_DATA1_0_DATA1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_I2C_CMD_DATA1_0_DATA1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register DVC_I2C_CMD_DATA2_0  
+#define DVC_I2C_CMD_DATA2_0                     _MK_ADDR_CONST(0x50)
+#define DVC_I2C_CMD_DATA2_0_SECURE                      0x0
+#define DVC_I2C_CMD_DATA2_0_WORD_COUNT                  0x1
+#define DVC_I2C_CMD_DATA2_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_I2C_CMD_DATA2_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define DVC_I2C_CMD_DATA2_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_I2C_CMD_DATA2_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_I2C_CMD_DATA2_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define DVC_I2C_CMD_DATA2_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+// Eighth data byte to be sent/received
+#define DVC_I2C_CMD_DATA2_0_DATA8_SHIFT                 _MK_SHIFT_CONST(24)
+#define DVC_I2C_CMD_DATA2_0_DATA8_FIELD                 (_MK_MASK_CONST(0xff) << DVC_I2C_CMD_DATA2_0_DATA8_SHIFT)
+#define DVC_I2C_CMD_DATA2_0_DATA8_RANGE                 31:24
+#define DVC_I2C_CMD_DATA2_0_DATA8_WOFFSET                       0x0
+#define DVC_I2C_CMD_DATA2_0_DATA8_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_I2C_CMD_DATA2_0_DATA8_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define DVC_I2C_CMD_DATA2_0_DATA8_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_I2C_CMD_DATA2_0_DATA8_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Seventh data byte to be sent/received
+#define DVC_I2C_CMD_DATA2_0_DATA7_SHIFT                 _MK_SHIFT_CONST(16)
+#define DVC_I2C_CMD_DATA2_0_DATA7_FIELD                 (_MK_MASK_CONST(0xff) << DVC_I2C_CMD_DATA2_0_DATA7_SHIFT)
+#define DVC_I2C_CMD_DATA2_0_DATA7_RANGE                 23:16
+#define DVC_I2C_CMD_DATA2_0_DATA7_WOFFSET                       0x0
+#define DVC_I2C_CMD_DATA2_0_DATA7_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_I2C_CMD_DATA2_0_DATA7_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define DVC_I2C_CMD_DATA2_0_DATA7_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_I2C_CMD_DATA2_0_DATA7_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Sixth data byte to be sent/received
+#define DVC_I2C_CMD_DATA2_0_DATA6_SHIFT                 _MK_SHIFT_CONST(8)
+#define DVC_I2C_CMD_DATA2_0_DATA6_FIELD                 (_MK_MASK_CONST(0xff) << DVC_I2C_CMD_DATA2_0_DATA6_SHIFT)
+#define DVC_I2C_CMD_DATA2_0_DATA6_RANGE                 15:8
+#define DVC_I2C_CMD_DATA2_0_DATA6_WOFFSET                       0x0
+#define DVC_I2C_CMD_DATA2_0_DATA6_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_I2C_CMD_DATA2_0_DATA6_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define DVC_I2C_CMD_DATA2_0_DATA6_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_I2C_CMD_DATA2_0_DATA6_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// This register contains the Fifth data byte to be  sent/received.
+#define DVC_I2C_CMD_DATA2_0_DATA5_SHIFT                 _MK_SHIFT_CONST(0)
+#define DVC_I2C_CMD_DATA2_0_DATA5_FIELD                 (_MK_MASK_CONST(0xff) << DVC_I2C_CMD_DATA2_0_DATA5_SHIFT)
+#define DVC_I2C_CMD_DATA2_0_DATA5_RANGE                 7:0
+#define DVC_I2C_CMD_DATA2_0_DATA5_WOFFSET                       0x0
+#define DVC_I2C_CMD_DATA2_0_DATA5_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_I2C_CMD_DATA2_0_DATA5_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define DVC_I2C_CMD_DATA2_0_DATA5_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_I2C_CMD_DATA2_0_DATA5_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Reserved address 84 [0x54] 
+
+// Reserved address 88 [0x58] 
+
+// Register DVC_I2C_STATUS_0  
+#define DVC_I2C_STATUS_0                        _MK_ADDR_CONST(0x5c)
+#define DVC_I2C_STATUS_0_SECURE                         0x0
+#define DVC_I2C_STATUS_0_WORD_COUNT                     0x1
+#define DVC_I2C_STATUS_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_I2C_STATUS_0_RESET_MASK                     _MK_MASK_CONST(0x1ff)
+#define DVC_I2C_STATUS_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define DVC_I2C_STATUS_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define DVC_I2C_STATUS_0_READ_MASK                      _MK_MASK_CONST(0x1ff)
+#define DVC_I2C_STATUS_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
+//  1 = Busy.
+#define DVC_I2C_STATUS_0_BUSY_SHIFT                     _MK_SHIFT_CONST(8)
+#define DVC_I2C_STATUS_0_BUSY_FIELD                     (_MK_MASK_CONST(0x1) << DVC_I2C_STATUS_0_BUSY_SHIFT)
+#define DVC_I2C_STATUS_0_BUSY_RANGE                     8:8
+#define DVC_I2C_STATUS_0_BUSY_WOFFSET                   0x0
+#define DVC_I2C_STATUS_0_BUSY_DEFAULT                   _MK_MASK_CONST(0x0)
+#define DVC_I2C_STATUS_0_BUSY_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define DVC_I2C_STATUS_0_BUSY_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_I2C_STATUS_0_BUSY_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define DVC_I2C_STATUS_0_BUSY_NOT_BUSY                  _MK_ENUM_CONST(0)
+#define DVC_I2C_STATUS_0_BUSY_BUSY                      _MK_ENUM_CONST(1)
+
+// Transaction for Slave2 for x byte failed. x is 'h0 to 'ha.
+// all others invalid 
+#define DVC_I2C_STATUS_0_CMD2_STAT_SHIFT                        _MK_SHIFT_CONST(4)
+#define DVC_I2C_STATUS_0_CMD2_STAT_FIELD                        (_MK_MASK_CONST(0xf) << DVC_I2C_STATUS_0_CMD2_STAT_SHIFT)
+#define DVC_I2C_STATUS_0_CMD2_STAT_RANGE                        7:4
+#define DVC_I2C_STATUS_0_CMD2_STAT_WOFFSET                      0x0
+#define DVC_I2C_STATUS_0_CMD2_STAT_DEFAULT                      _MK_MASK_CONST(0x0)
+#define DVC_I2C_STATUS_0_CMD2_STAT_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define DVC_I2C_STATUS_0_CMD2_STAT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define DVC_I2C_STATUS_0_CMD2_STAT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define DVC_I2C_STATUS_0_CMD2_STAT_SL2_XFER_SUCCESSFUL                  _MK_ENUM_CONST(0)
+#define DVC_I2C_STATUS_0_CMD2_STAT_SL2_NOACK_FOR_BYTE1                  _MK_ENUM_CONST(1)
+#define DVC_I2C_STATUS_0_CMD2_STAT_SL2_NOACK_FOR_BYTE2                  _MK_ENUM_CONST(2)
+#define DVC_I2C_STATUS_0_CMD2_STAT_SL2_NOACK_FOR_BYTE3                  _MK_ENUM_CONST(3)
+#define DVC_I2C_STATUS_0_CMD2_STAT_SL2_NOACK_FOR_BYTE4                  _MK_ENUM_CONST(4)
+#define DVC_I2C_STATUS_0_CMD2_STAT_SL2_NOACK_FOR_BYTE5                  _MK_ENUM_CONST(5)
+#define DVC_I2C_STATUS_0_CMD2_STAT_SL2_NOACK_FOR_BYTE6                  _MK_ENUM_CONST(6)
+#define DVC_I2C_STATUS_0_CMD2_STAT_SL2_NOACK_FOR_BYTE7                  _MK_ENUM_CONST(7)
+#define DVC_I2C_STATUS_0_CMD2_STAT_SL2_NOACK_FOR_BYTE8                  _MK_ENUM_CONST(8)
+#define DVC_I2C_STATUS_0_CMD2_STAT_SL2_NOACK_FOR_BYTE9                  _MK_ENUM_CONST(9)
+#define DVC_I2C_STATUS_0_CMD2_STAT_SL2_NOACK_FOR_BYTE10                 _MK_ENUM_CONST(10)
+
+// Transaction for Slave1 for x byte failed. x is 'h0 to 'ha.
+// all others invalid
+#define DVC_I2C_STATUS_0_CMD1_STAT_SHIFT                        _MK_SHIFT_CONST(0)
+#define DVC_I2C_STATUS_0_CMD1_STAT_FIELD                        (_MK_MASK_CONST(0xf) << DVC_I2C_STATUS_0_CMD1_STAT_SHIFT)
+#define DVC_I2C_STATUS_0_CMD1_STAT_RANGE                        3:0
+#define DVC_I2C_STATUS_0_CMD1_STAT_WOFFSET                      0x0
+#define DVC_I2C_STATUS_0_CMD1_STAT_DEFAULT                      _MK_MASK_CONST(0x0)
+#define DVC_I2C_STATUS_0_CMD1_STAT_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define DVC_I2C_STATUS_0_CMD1_STAT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define DVC_I2C_STATUS_0_CMD1_STAT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define DVC_I2C_STATUS_0_CMD1_STAT_SL1_XFER_SUCCESSFUL                  _MK_ENUM_CONST(0)
+#define DVC_I2C_STATUS_0_CMD1_STAT_SL1_NOACK_FOR_BYTE1                  _MK_ENUM_CONST(1)
+#define DVC_I2C_STATUS_0_CMD1_STAT_SL1_NOACK_FOR_BYTE2                  _MK_ENUM_CONST(2)
+#define DVC_I2C_STATUS_0_CMD1_STAT_SL1_NOACK_FOR_BYTE3                  _MK_ENUM_CONST(3)
+#define DVC_I2C_STATUS_0_CMD1_STAT_SL1_NOACK_FOR_BYTE4                  _MK_ENUM_CONST(4)
+#define DVC_I2C_STATUS_0_CMD1_STAT_SL1_NOACK_FOR_BYTE5                  _MK_ENUM_CONST(5)
+#define DVC_I2C_STATUS_0_CMD1_STAT_SL1_NOACK_FOR_BYTE6                  _MK_ENUM_CONST(6)
+#define DVC_I2C_STATUS_0_CMD1_STAT_SL1_NOACK_FOR_BYTE7                  _MK_ENUM_CONST(7)
+#define DVC_I2C_STATUS_0_CMD1_STAT_SL1_NOACK_FOR_BYTE8                  _MK_ENUM_CONST(8)
+#define DVC_I2C_STATUS_0_CMD1_STAT_SL1_NOACK_FOR_BYTE9                  _MK_ENUM_CONST(9)
+#define DVC_I2C_STATUS_0_CMD1_STAT_SL1_NOACK_FOR_BYTE10                 _MK_ENUM_CONST(10)
+
+
+// Packet I2C_IO_PACKET_HEADER_0
+#define I2C_IO_PACKET_HEADER_0_SIZE 32
+
+#define I2C_IO_PACKET_HEADER_0_RESERVED0_3_SHIFT                        _MK_SHIFT_CONST(30)
+#define I2C_IO_PACKET_HEADER_0_RESERVED0_3_FIELD                        (_MK_MASK_CONST(0x3) << I2C_IO_PACKET_HEADER_0_RESERVED0_3_SHIFT)
+#define I2C_IO_PACKET_HEADER_0_RESERVED0_3_RANGE                        _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(30)
+#define I2C_IO_PACKET_HEADER_0_RESERVED0_3_ROW                  0
+
+#define I2C_IO_PACKET_HEADER_0_HDRSZ_SHIFT                      _MK_SHIFT_CONST(28)
+#define I2C_IO_PACKET_HEADER_0_HDRSZ_FIELD                      (_MK_MASK_CONST(0x3) << I2C_IO_PACKET_HEADER_0_HDRSZ_SHIFT)
+#define I2C_IO_PACKET_HEADER_0_HDRSZ_RANGE                      _MK_SHIFT_CONST(29):_MK_SHIFT_CONST(28)
+#define I2C_IO_PACKET_HEADER_0_HDRSZ_ROW                        0
+#define I2C_IO_PACKET_HEADER_0_HDRSZ_ONE                        _MK_ENUM_CONST(0)
+#define I2C_IO_PACKET_HEADER_0_HDRSZ_TWO                        _MK_ENUM_CONST(1)
+#define I2C_IO_PACKET_HEADER_0_HDRSZ_THREE                      _MK_ENUM_CONST(2)
+#define I2C_IO_PACKET_HEADER_0_HDRSZ_FOUR                       _MK_ENUM_CONST(3)
+
+#define I2C_IO_PACKET_HEADER_0_RESERVED0_2_SHIFT                        _MK_SHIFT_CONST(24)
+#define I2C_IO_PACKET_HEADER_0_RESERVED0_2_FIELD                        (_MK_MASK_CONST(0xf) << I2C_IO_PACKET_HEADER_0_RESERVED0_2_SHIFT)
+#define I2C_IO_PACKET_HEADER_0_RESERVED0_2_RANGE                        _MK_SHIFT_CONST(27):_MK_SHIFT_CONST(24)
+#define I2C_IO_PACKET_HEADER_0_RESERVED0_2_ROW                  0
+
+#define I2C_IO_PACKET_HEADER_0_PKTID_SHIFT                      _MK_SHIFT_CONST(16)
+#define I2C_IO_PACKET_HEADER_0_PKTID_FIELD                      (_MK_MASK_CONST(0xff) << I2C_IO_PACKET_HEADER_0_PKTID_SHIFT)
+#define I2C_IO_PACKET_HEADER_0_PKTID_RANGE                      _MK_SHIFT_CONST(23):_MK_SHIFT_CONST(16)
+#define I2C_IO_PACKET_HEADER_0_PKTID_ROW                        0
+
+#define I2C_IO_PACKET_HEADER_0_CONTROLLER_ID_SHIFT                      _MK_SHIFT_CONST(12)
+#define I2C_IO_PACKET_HEADER_0_CONTROLLER_ID_FIELD                      (_MK_MASK_CONST(0xf) << I2C_IO_PACKET_HEADER_0_CONTROLLER_ID_SHIFT)
+#define I2C_IO_PACKET_HEADER_0_CONTROLLER_ID_RANGE                      _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(12)
+#define I2C_IO_PACKET_HEADER_0_CONTROLLER_ID_ROW                        0
+#define I2C_IO_PACKET_HEADER_0_CONTROLLER_ID_I2C1                       _MK_ENUM_CONST(0)
+#define I2C_IO_PACKET_HEADER_0_CONTROLLER_ID_I2C2                       _MK_ENUM_CONST(1)
+#define I2C_IO_PACKET_HEADER_0_CONTROLLER_ID_I2C3                       _MK_ENUM_CONST(2)
+#define I2C_IO_PACKET_HEADER_0_CONTROLLER_ID_DVC_I2C                    _MK_ENUM_CONST(3)
+
+#define I2C_IO_PACKET_HEADER_0_RESERVED0_1_SHIFT                        _MK_SHIFT_CONST(8)
+#define I2C_IO_PACKET_HEADER_0_RESERVED0_1_FIELD                        (_MK_MASK_CONST(0xf) << I2C_IO_PACKET_HEADER_0_RESERVED0_1_SHIFT)
+#define I2C_IO_PACKET_HEADER_0_RESERVED0_1_RANGE                        _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(8)
+#define I2C_IO_PACKET_HEADER_0_RESERVED0_1_ROW                  0
+
+#define I2C_IO_PACKET_HEADER_0_PROTOCOL_SHIFT                   _MK_SHIFT_CONST(4)
+#define I2C_IO_PACKET_HEADER_0_PROTOCOL_FIELD                   (_MK_MASK_CONST(0xf) << I2C_IO_PACKET_HEADER_0_PROTOCOL_SHIFT)
+#define I2C_IO_PACKET_HEADER_0_PROTOCOL_RANGE                   _MK_SHIFT_CONST(7):_MK_SHIFT_CONST(4)
+#define I2C_IO_PACKET_HEADER_0_PROTOCOL_ROW                     0
+#define I2C_IO_PACKET_HEADER_0_PROTOCOL_RESERVED                        _MK_ENUM_CONST(0)
+#define I2C_IO_PACKET_HEADER_0_PROTOCOL_I2C                     _MK_ENUM_CONST(1)
+
+#define I2C_IO_PACKET_HEADER_0_RESERVED0_0_SHIFT                        _MK_SHIFT_CONST(3)
+#define I2C_IO_PACKET_HEADER_0_RESERVED0_0_FIELD                        (_MK_MASK_CONST(0x1) << I2C_IO_PACKET_HEADER_0_RESERVED0_0_SHIFT)
+#define I2C_IO_PACKET_HEADER_0_RESERVED0_0_RANGE                        _MK_SHIFT_CONST(3):_MK_SHIFT_CONST(3)
+#define I2C_IO_PACKET_HEADER_0_RESERVED0_0_ROW                  0
+
+#define I2C_IO_PACKET_HEADER_0_PKTTYPE_SHIFT                    _MK_SHIFT_CONST(0)
+#define I2C_IO_PACKET_HEADER_0_PKTTYPE_FIELD                    (_MK_MASK_CONST(0x7) << I2C_IO_PACKET_HEADER_0_PKTTYPE_SHIFT)
+#define I2C_IO_PACKET_HEADER_0_PKTTYPE_RANGE                    _MK_SHIFT_CONST(2):_MK_SHIFT_CONST(0)
+#define I2C_IO_PACKET_HEADER_0_PKTTYPE_ROW                      0
+
+#define I2C_IO_PACKET_HEADER_0_RESERVED1_0_SHIFT                        _MK_SHIFT_CONST(12)
+#define I2C_IO_PACKET_HEADER_0_RESERVED1_0_FIELD                        (_MK_MASK_CONST(0xfffff) << I2C_IO_PACKET_HEADER_0_RESERVED1_0_SHIFT)
+#define I2C_IO_PACKET_HEADER_0_RESERVED1_0_RANGE                        _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(12)
+#define I2C_IO_PACKET_HEADER_0_RESERVED1_0_ROW                  1
+
+#define I2C_IO_PACKET_HEADER_0_PAYLOADSIZE_SHIFT                        _MK_SHIFT_CONST(0)
+#define I2C_IO_PACKET_HEADER_0_PAYLOADSIZE_FIELD                        (_MK_MASK_CONST(0xfff) << I2C_IO_PACKET_HEADER_0_PAYLOADSIZE_SHIFT)
+#define I2C_IO_PACKET_HEADER_0_PAYLOADSIZE_RANGE                        _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(0)
+#define I2C_IO_PACKET_HEADER_0_PAYLOADSIZE_ROW                  1
+
+#define I2C_IO_PACKET_HEADER_0_RESERVED2_0_SHIFT                        _MK_SHIFT_CONST(23)
+#define I2C_IO_PACKET_HEADER_0_RESERVED2_0_FIELD                        (_MK_MASK_CONST(0x1ff) << I2C_IO_PACKET_HEADER_0_RESERVED2_0_SHIFT)
+#define I2C_IO_PACKET_HEADER_0_RESERVED2_0_RANGE                        _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(23)
+#define I2C_IO_PACKET_HEADER_0_RESERVED2_0_ROW                  2
+
+#define I2C_IO_PACKET_HEADER_0_HS_MODE_SHIFT                    _MK_SHIFT_CONST(22)
+#define I2C_IO_PACKET_HEADER_0_HS_MODE_FIELD                    (_MK_MASK_CONST(0x1) << I2C_IO_PACKET_HEADER_0_HS_MODE_SHIFT)
+#define I2C_IO_PACKET_HEADER_0_HS_MODE_RANGE                    _MK_SHIFT_CONST(22):_MK_SHIFT_CONST(22)
+#define I2C_IO_PACKET_HEADER_0_HS_MODE_ROW                      2
+#define I2C_IO_PACKET_HEADER_0_HS_MODE_DISABLE                  _MK_ENUM_CONST(0)
+#define I2C_IO_PACKET_HEADER_0_HS_MODE_ENABLE                   _MK_ENUM_CONST(1)
+
+#define I2C_IO_PACKET_HEADER_0_CONTUNE_ON_NACK_SHIFT                    _MK_SHIFT_CONST(21)
+#define I2C_IO_PACKET_HEADER_0_CONTUNE_ON_NACK_FIELD                    (_MK_MASK_CONST(0x1) << I2C_IO_PACKET_HEADER_0_CONTUNE_ON_NACK_SHIFT)
+#define I2C_IO_PACKET_HEADER_0_CONTUNE_ON_NACK_RANGE                    _MK_SHIFT_CONST(21):_MK_SHIFT_CONST(21)
+#define I2C_IO_PACKET_HEADER_0_CONTUNE_ON_NACK_ROW                      2
+#define I2C_IO_PACKET_HEADER_0_CONTUNE_ON_NACK_DISABLE                  _MK_ENUM_CONST(0)
+#define I2C_IO_PACKET_HEADER_0_CONTUNE_ON_NACK_ENABLE                   _MK_ENUM_CONST(1)
+
+#define I2C_IO_PACKET_HEADER_0_SEND_START_BYTE_SHIFT                    _MK_SHIFT_CONST(20)
+#define I2C_IO_PACKET_HEADER_0_SEND_START_BYTE_FIELD                    (_MK_MASK_CONST(0x1) << I2C_IO_PACKET_HEADER_0_SEND_START_BYTE_SHIFT)
+#define I2C_IO_PACKET_HEADER_0_SEND_START_BYTE_RANGE                    _MK_SHIFT_CONST(20):_MK_SHIFT_CONST(20)
+#define I2C_IO_PACKET_HEADER_0_SEND_START_BYTE_ROW                      2
+#define I2C_IO_PACKET_HEADER_0_SEND_START_BYTE_DISABLE                  _MK_ENUM_CONST(0)
+#define I2C_IO_PACKET_HEADER_0_SEND_START_BYTE_ENABLE                   _MK_ENUM_CONST(1)
+
+#define I2C_IO_PACKET_HEADER_0_READ_SHIFT                       _MK_SHIFT_CONST(19)
+#define I2C_IO_PACKET_HEADER_0_READ_FIELD                       (_MK_MASK_CONST(0x1) << I2C_IO_PACKET_HEADER_0_READ_SHIFT)
+#define I2C_IO_PACKET_HEADER_0_READ_RANGE                       _MK_SHIFT_CONST(19):_MK_SHIFT_CONST(19)
+#define I2C_IO_PACKET_HEADER_0_READ_ROW                 2
+#define I2C_IO_PACKET_HEADER_0_READ_WRITE                       _MK_ENUM_CONST(0)
+#define I2C_IO_PACKET_HEADER_0_READ_READ                        _MK_ENUM_CONST(1)
+
+#define I2C_IO_PACKET_HEADER_0_ADDR_MODE_SHIFT                  _MK_SHIFT_CONST(18)
+#define I2C_IO_PACKET_HEADER_0_ADDR_MODE_FIELD                  (_MK_MASK_CONST(0x1) << I2C_IO_PACKET_HEADER_0_ADDR_MODE_SHIFT)
+#define I2C_IO_PACKET_HEADER_0_ADDR_MODE_RANGE                  _MK_SHIFT_CONST(18):_MK_SHIFT_CONST(18)
+#define I2C_IO_PACKET_HEADER_0_ADDR_MODE_ROW                    2
+#define I2C_IO_PACKET_HEADER_0_ADDR_MODE_SEVEN_BIT                      _MK_ENUM_CONST(0)
+#define I2C_IO_PACKET_HEADER_0_ADDR_MODE_TEN_BIT                        _MK_ENUM_CONST(1)
+
+#define I2C_IO_PACKET_HEADER_0_IE_SHIFT                 _MK_SHIFT_CONST(17)
+#define I2C_IO_PACKET_HEADER_0_IE_FIELD                 (_MK_MASK_CONST(0x1) << I2C_IO_PACKET_HEADER_0_IE_SHIFT)
+#define I2C_IO_PACKET_HEADER_0_IE_RANGE                 _MK_SHIFT_CONST(17):_MK_SHIFT_CONST(17)
+#define I2C_IO_PACKET_HEADER_0_IE_ROW                   2
+#define I2C_IO_PACKET_HEADER_0_IE_DISABLE                       _MK_ENUM_CONST(0)
+#define I2C_IO_PACKET_HEADER_0_IE_ENABLE                        _MK_ENUM_CONST(1)
+
+#define I2C_IO_PACKET_HEADER_0_REPEAT_START_SHIFT                       _MK_SHIFT_CONST(16)
+#define I2C_IO_PACKET_HEADER_0_REPEAT_START_FIELD                       (_MK_MASK_CONST(0x1) << I2C_IO_PACKET_HEADER_0_REPEAT_START_SHIFT)
+#define I2C_IO_PACKET_HEADER_0_REPEAT_START_RANGE                       _MK_SHIFT_CONST(16):_MK_SHIFT_CONST(16)
+#define I2C_IO_PACKET_HEADER_0_REPEAT_START_ROW                 2
+#define I2C_IO_PACKET_HEADER_0_REPEAT_START_STOP                        _MK_ENUM_CONST(0)
+#define I2C_IO_PACKET_HEADER_0_REPEAT_START_REPEAT_START                        _MK_ENUM_CONST(1)
+
+#define I2C_IO_PACKET_HEADER_0_RESERVED2_1_SHIFT                        _MK_SHIFT_CONST(15)
+#define I2C_IO_PACKET_HEADER_0_RESERVED2_1_FIELD                        (_MK_MASK_CONST(0x1) << I2C_IO_PACKET_HEADER_0_RESERVED2_1_SHIFT)
+#define I2C_IO_PACKET_HEADER_0_RESERVED2_1_RANGE                        _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(15)
+#define I2C_IO_PACKET_HEADER_0_RESERVED2_1_ROW                  2
+
+#define I2C_IO_PACKET_HEADER_0_HS_MASTER_ADDR_SHIFT                     _MK_SHIFT_CONST(12)
+#define I2C_IO_PACKET_HEADER_0_HS_MASTER_ADDR_FIELD                     (_MK_MASK_CONST(0x7) << I2C_IO_PACKET_HEADER_0_HS_MASTER_ADDR_SHIFT)
+#define I2C_IO_PACKET_HEADER_0_HS_MASTER_ADDR_RANGE                     _MK_SHIFT_CONST(14):_MK_SHIFT_CONST(12)
+#define I2C_IO_PACKET_HEADER_0_HS_MASTER_ADDR_ROW                       2
+
+#define I2C_IO_PACKET_HEADER_0_RESERVED2_2_SHIFT                        _MK_SHIFT_CONST(10)
+#define I2C_IO_PACKET_HEADER_0_RESERVED2_2_FIELD                        (_MK_MASK_CONST(0x3) << I2C_IO_PACKET_HEADER_0_RESERVED2_2_SHIFT)
+#define I2C_IO_PACKET_HEADER_0_RESERVED2_2_RANGE                        _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(10)
+#define I2C_IO_PACKET_HEADER_0_RESERVED2_2_ROW                  2
+
+#define I2C_IO_PACKET_HEADER_0_SLAVE_ADDR_SHIFT                 _MK_SHIFT_CONST(0)
+#define I2C_IO_PACKET_HEADER_0_SLAVE_ADDR_FIELD                 (_MK_MASK_CONST(0x3ff) << I2C_IO_PACKET_HEADER_0_SLAVE_ADDR_SHIFT)
+#define I2C_IO_PACKET_HEADER_0_SLAVE_ADDR_RANGE                 _MK_SHIFT_CONST(9):_MK_SHIFT_CONST(0)
+#define I2C_IO_PACKET_HEADER_0_SLAVE_ADDR_ROW                   2
+
+
+// Register DVC_I2C_TX_PACKET_FIFO_0  
+#define DVC_I2C_TX_PACKET_FIFO_0                        _MK_ADDR_CONST(0x60)
+#define DVC_I2C_TX_PACKET_FIFO_0_SECURE                         0x0
+#define DVC_I2C_TX_PACKET_FIFO_0_WORD_COUNT                     0x1
+#define DVC_I2C_TX_PACKET_FIFO_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_I2C_TX_PACKET_FIFO_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
+#define DVC_I2C_TX_PACKET_FIFO_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define DVC_I2C_TX_PACKET_FIFO_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define DVC_I2C_TX_PACKET_FIFO_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define DVC_I2C_TX_PACKET_FIFO_0_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
+//SW writes packets into this register  
+//A packet may contain generic
+#define DVC_I2C_TX_PACKET_FIFO_0_TX_PACKET_SHIFT                        _MK_SHIFT_CONST(0)
+#define DVC_I2C_TX_PACKET_FIFO_0_TX_PACKET_FIELD                        (_MK_MASK_CONST(0xffffffff) << DVC_I2C_TX_PACKET_FIFO_0_TX_PACKET_SHIFT)
+#define DVC_I2C_TX_PACKET_FIFO_0_TX_PACKET_RANGE                        31:0
+#define DVC_I2C_TX_PACKET_FIFO_0_TX_PACKET_WOFFSET                      0x0
+#define DVC_I2C_TX_PACKET_FIFO_0_TX_PACKET_DEFAULT                      _MK_MASK_CONST(0x0)
+#define DVC_I2C_TX_PACKET_FIFO_0_TX_PACKET_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
+#define DVC_I2C_TX_PACKET_FIFO_0_TX_PACKET_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define DVC_I2C_TX_PACKET_FIFO_0_TX_PACKET_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register DVC_I2C_RX_FIFO_0  
+#define DVC_I2C_RX_FIFO_0                       _MK_ADDR_CONST(0x64)
+#define DVC_I2C_RX_FIFO_0_SECURE                        0x0
+#define DVC_I2C_RX_FIFO_0_WORD_COUNT                    0x1
+#define DVC_I2C_RX_FIFO_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define DVC_I2C_RX_FIFO_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
+#define DVC_I2C_RX_FIFO_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define DVC_I2C_RX_FIFO_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define DVC_I2C_RX_FIFO_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define DVC_I2C_RX_FIFO_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+//SW Reads data from this register,causes pop  
+#define DVC_I2C_RX_FIFO_0_RD_DATA_SHIFT                 _MK_SHIFT_CONST(0)
+#define DVC_I2C_RX_FIFO_0_RD_DATA_FIELD                 (_MK_MASK_CONST(0xffffffff) << DVC_I2C_RX_FIFO_0_RD_DATA_SHIFT)
+#define DVC_I2C_RX_FIFO_0_RD_DATA_RANGE                 31:0
+#define DVC_I2C_RX_FIFO_0_RD_DATA_WOFFSET                       0x0
+#define DVC_I2C_RX_FIFO_0_RD_DATA_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_I2C_RX_FIFO_0_RD_DATA_DEFAULT_MASK                  _MK_MASK_CONST(0xffffffff)
+#define DVC_I2C_RX_FIFO_0_RD_DATA_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_I2C_RX_FIFO_0_RD_DATA_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register DVC_PACKET_TRANSFER_STATUS_0  
+#define DVC_PACKET_TRANSFER_STATUS_0                    _MK_ADDR_CONST(0x68)
+#define DVC_PACKET_TRANSFER_STATUS_0_SECURE                     0x0
+#define DVC_PACKET_TRANSFER_STATUS_0_WORD_COUNT                         0x1
+#define DVC_PACKET_TRANSFER_STATUS_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define DVC_PACKET_TRANSFER_STATUS_0_RESET_MASK                         _MK_MASK_CONST(0x1ffffff)
+#define DVC_PACKET_TRANSFER_STATUS_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define DVC_PACKET_TRANSFER_STATUS_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define DVC_PACKET_TRANSFER_STATUS_0_READ_MASK                  _MK_MASK_CONST(0x1ffffff)
+#define DVC_PACKET_TRANSFER_STATUS_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
+//The packet transfer for which last packet is set has been
+//completed       
+#define DVC_PACKET_TRANSFER_STATUS_0_TRANSFER_COMPLETE_SHIFT                    _MK_SHIFT_CONST(24)
+#define DVC_PACKET_TRANSFER_STATUS_0_TRANSFER_COMPLETE_FIELD                    (_MK_MASK_CONST(0x1) << DVC_PACKET_TRANSFER_STATUS_0_TRANSFER_COMPLETE_SHIFT)
+#define DVC_PACKET_TRANSFER_STATUS_0_TRANSFER_COMPLETE_RANGE                    24:24
+#define DVC_PACKET_TRANSFER_STATUS_0_TRANSFER_COMPLETE_WOFFSET                  0x0
+#define DVC_PACKET_TRANSFER_STATUS_0_TRANSFER_COMPLETE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define DVC_PACKET_TRANSFER_STATUS_0_TRANSFER_COMPLETE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define DVC_PACKET_TRANSFER_STATUS_0_TRANSFER_COMPLETE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_PACKET_TRANSFER_STATUS_0_TRANSFER_COMPLETE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define DVC_PACKET_TRANSFER_STATUS_0_TRANSFER_COMPLETE_UNSET                    _MK_ENUM_CONST(0)
+#define DVC_PACKET_TRANSFER_STATUS_0_TRANSFER_COMPLETE_SET                      _MK_ENUM_CONST(1)
+
+//The current packet id for which the transaction is 
+//happening on the bus
+#define DVC_PACKET_TRANSFER_STATUS_0_TRANSFER_PKT_ID_SHIFT                      _MK_SHIFT_CONST(16)
+#define DVC_PACKET_TRANSFER_STATUS_0_TRANSFER_PKT_ID_FIELD                      (_MK_MASK_CONST(0xff) << DVC_PACKET_TRANSFER_STATUS_0_TRANSFER_PKT_ID_SHIFT)
+#define DVC_PACKET_TRANSFER_STATUS_0_TRANSFER_PKT_ID_RANGE                      23:16
+#define DVC_PACKET_TRANSFER_STATUS_0_TRANSFER_PKT_ID_WOFFSET                    0x0
+#define DVC_PACKET_TRANSFER_STATUS_0_TRANSFER_PKT_ID_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_PACKET_TRANSFER_STATUS_0_TRANSFER_PKT_ID_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
+#define DVC_PACKET_TRANSFER_STATUS_0_TRANSFER_PKT_ID_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define DVC_PACKET_TRANSFER_STATUS_0_TRANSFER_PKT_ID_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+//The number of bytes transferred in the current packet 
+#define DVC_PACKET_TRANSFER_STATUS_0_TRANSFER_BYTENUM_SHIFT                     _MK_SHIFT_CONST(4)
+#define DVC_PACKET_TRANSFER_STATUS_0_TRANSFER_BYTENUM_FIELD                     (_MK_MASK_CONST(0xfff) << DVC_PACKET_TRANSFER_STATUS_0_TRANSFER_BYTENUM_SHIFT)
+#define DVC_PACKET_TRANSFER_STATUS_0_TRANSFER_BYTENUM_RANGE                     15:4
+#define DVC_PACKET_TRANSFER_STATUS_0_TRANSFER_BYTENUM_WOFFSET                   0x0
+#define DVC_PACKET_TRANSFER_STATUS_0_TRANSFER_BYTENUM_DEFAULT                   _MK_MASK_CONST(0x0)
+#define DVC_PACKET_TRANSFER_STATUS_0_TRANSFER_BYTENUM_DEFAULT_MASK                      _MK_MASK_CONST(0xfff)
+#define DVC_PACKET_TRANSFER_STATUS_0_TRANSFER_BYTENUM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_PACKET_TRANSFER_STATUS_0_TRANSFER_BYTENUM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+//No ack recieved for the addr byte
+#define DVC_PACKET_TRANSFER_STATUS_0_NOACK_FOR_ADDR_SHIFT                       _MK_SHIFT_CONST(3)
+#define DVC_PACKET_TRANSFER_STATUS_0_NOACK_FOR_ADDR_FIELD                       (_MK_MASK_CONST(0x1) << DVC_PACKET_TRANSFER_STATUS_0_NOACK_FOR_ADDR_SHIFT)
+#define DVC_PACKET_TRANSFER_STATUS_0_NOACK_FOR_ADDR_RANGE                       3:3
+#define DVC_PACKET_TRANSFER_STATUS_0_NOACK_FOR_ADDR_WOFFSET                     0x0
+#define DVC_PACKET_TRANSFER_STATUS_0_NOACK_FOR_ADDR_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_PACKET_TRANSFER_STATUS_0_NOACK_FOR_ADDR_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define DVC_PACKET_TRANSFER_STATUS_0_NOACK_FOR_ADDR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define DVC_PACKET_TRANSFER_STATUS_0_NOACK_FOR_ADDR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_PACKET_TRANSFER_STATUS_0_NOACK_FOR_ADDR_UNSET                       _MK_ENUM_CONST(0)
+#define DVC_PACKET_TRANSFER_STATUS_0_NOACK_FOR_ADDR_SET                 _MK_ENUM_CONST(1)
+
+//No ack recieved for the data byte
+#define DVC_PACKET_TRANSFER_STATUS_0_NOACK_FOR_DATA_SHIFT                       _MK_SHIFT_CONST(2)
+#define DVC_PACKET_TRANSFER_STATUS_0_NOACK_FOR_DATA_FIELD                       (_MK_MASK_CONST(0x1) << DVC_PACKET_TRANSFER_STATUS_0_NOACK_FOR_DATA_SHIFT)
+#define DVC_PACKET_TRANSFER_STATUS_0_NOACK_FOR_DATA_RANGE                       2:2
+#define DVC_PACKET_TRANSFER_STATUS_0_NOACK_FOR_DATA_WOFFSET                     0x0
+#define DVC_PACKET_TRANSFER_STATUS_0_NOACK_FOR_DATA_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_PACKET_TRANSFER_STATUS_0_NOACK_FOR_DATA_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define DVC_PACKET_TRANSFER_STATUS_0_NOACK_FOR_DATA_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define DVC_PACKET_TRANSFER_STATUS_0_NOACK_FOR_DATA_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_PACKET_TRANSFER_STATUS_0_NOACK_FOR_DATA_UNSET                       _MK_ENUM_CONST(0)
+#define DVC_PACKET_TRANSFER_STATUS_0_NOACK_FOR_DATA_SET                 _MK_ENUM_CONST(1)
+
+//Arbitration lost for the current byte
+#define DVC_PACKET_TRANSFER_STATUS_0_ARB_LOST_SHIFT                     _MK_SHIFT_CONST(1)
+#define DVC_PACKET_TRANSFER_STATUS_0_ARB_LOST_FIELD                     (_MK_MASK_CONST(0x1) << DVC_PACKET_TRANSFER_STATUS_0_ARB_LOST_SHIFT)
+#define DVC_PACKET_TRANSFER_STATUS_0_ARB_LOST_RANGE                     1:1
+#define DVC_PACKET_TRANSFER_STATUS_0_ARB_LOST_WOFFSET                   0x0
+#define DVC_PACKET_TRANSFER_STATUS_0_ARB_LOST_DEFAULT                   _MK_MASK_CONST(0x0)
+#define DVC_PACKET_TRANSFER_STATUS_0_ARB_LOST_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define DVC_PACKET_TRANSFER_STATUS_0_ARB_LOST_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_PACKET_TRANSFER_STATUS_0_ARB_LOST_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define DVC_PACKET_TRANSFER_STATUS_0_ARB_LOST_UNSET                     _MK_ENUM_CONST(0)
+#define DVC_PACKET_TRANSFER_STATUS_0_ARB_LOST_SET                       _MK_ENUM_CONST(1)
+
+//1 = Controller is busy
+#define DVC_PACKET_TRANSFER_STATUS_0_CONTROLLER_BUSY_SHIFT                      _MK_SHIFT_CONST(0)
+#define DVC_PACKET_TRANSFER_STATUS_0_CONTROLLER_BUSY_FIELD                      (_MK_MASK_CONST(0x1) << DVC_PACKET_TRANSFER_STATUS_0_CONTROLLER_BUSY_SHIFT)
+#define DVC_PACKET_TRANSFER_STATUS_0_CONTROLLER_BUSY_RANGE                      0:0
+#define DVC_PACKET_TRANSFER_STATUS_0_CONTROLLER_BUSY_WOFFSET                    0x0
+#define DVC_PACKET_TRANSFER_STATUS_0_CONTROLLER_BUSY_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_PACKET_TRANSFER_STATUS_0_CONTROLLER_BUSY_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define DVC_PACKET_TRANSFER_STATUS_0_CONTROLLER_BUSY_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define DVC_PACKET_TRANSFER_STATUS_0_CONTROLLER_BUSY_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define DVC_PACKET_TRANSFER_STATUS_0_CONTROLLER_BUSY_UNSET                      _MK_ENUM_CONST(0)
+#define DVC_PACKET_TRANSFER_STATUS_0_CONTROLLER_BUSY_SET                        _MK_ENUM_CONST(1)
+
+
+// Register DVC_FIFO_CONTROL_0  
+#define DVC_FIFO_CONTROL_0                      _MK_ADDR_CONST(0x6c)
+#define DVC_FIFO_CONTROL_0_SECURE                       0x0
+#define DVC_FIFO_CONTROL_0_WORD_COUNT                   0x1
+#define DVC_FIFO_CONTROL_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define DVC_FIFO_CONTROL_0_RESET_MASK                   _MK_MASK_CONST(0xff)
+#define DVC_FIFO_CONTROL_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define DVC_FIFO_CONTROL_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define DVC_FIFO_CONTROL_0_READ_MASK                    _MK_MASK_CONST(0xff)
+#define DVC_FIFO_CONTROL_0_WRITE_MASK                   _MK_MASK_CONST(0xff)
+//Transmit fifo trigger level 
+//000 = 1 word,  Dma trigger is asserted when 
+//at least one word empty in the fifo 
+//010 = 2 word,  Dma trigger is asserted when 
+//at least 2 words empty in the fifo 
+#define DVC_FIFO_CONTROL_0_TX_FIFO_TRIG_SHIFT                   _MK_SHIFT_CONST(5)
+#define DVC_FIFO_CONTROL_0_TX_FIFO_TRIG_FIELD                   (_MK_MASK_CONST(0x7) << DVC_FIFO_CONTROL_0_TX_FIFO_TRIG_SHIFT)
+#define DVC_FIFO_CONTROL_0_TX_FIFO_TRIG_RANGE                   7:5
+#define DVC_FIFO_CONTROL_0_TX_FIFO_TRIG_WOFFSET                 0x0
+#define DVC_FIFO_CONTROL_0_TX_FIFO_TRIG_DEFAULT                 _MK_MASK_CONST(0x0)
+#define DVC_FIFO_CONTROL_0_TX_FIFO_TRIG_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
+#define DVC_FIFO_CONTROL_0_TX_FIFO_TRIG_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define DVC_FIFO_CONTROL_0_TX_FIFO_TRIG_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+//Receive fifo trigger level 
+//000 = 1 word  Dma trigger is asserted when 
+//at least one word full in the fifo 
+//010 = 2 word  Dma trigger is asserted when 
+//at least 2 word full in the fifo 
+#define DVC_FIFO_CONTROL_0_RX_FIFO_TRIG_SHIFT                   _MK_SHIFT_CONST(2)
+#define DVC_FIFO_CONTROL_0_RX_FIFO_TRIG_FIELD                   (_MK_MASK_CONST(0x7) << DVC_FIFO_CONTROL_0_RX_FIFO_TRIG_SHIFT)
+#define DVC_FIFO_CONTROL_0_RX_FIFO_TRIG_RANGE                   4:2
+#define DVC_FIFO_CONTROL_0_RX_FIFO_TRIG_WOFFSET                 0x0
+#define DVC_FIFO_CONTROL_0_RX_FIFO_TRIG_DEFAULT                 _MK_MASK_CONST(0x0)
+#define DVC_FIFO_CONTROL_0_RX_FIFO_TRIG_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
+#define DVC_FIFO_CONTROL_0_RX_FIFO_TRIG_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define DVC_FIFO_CONTROL_0_RX_FIFO_TRIG_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+//1= flush the tx fifo,cleared after fifo is flushed
+#define DVC_FIFO_CONTROL_0_TX_FIFO_FLUSH_SHIFT                  _MK_SHIFT_CONST(1)
+#define DVC_FIFO_CONTROL_0_TX_FIFO_FLUSH_FIELD                  (_MK_MASK_CONST(0x1) << DVC_FIFO_CONTROL_0_TX_FIFO_FLUSH_SHIFT)
+#define DVC_FIFO_CONTROL_0_TX_FIFO_FLUSH_RANGE                  1:1
+#define DVC_FIFO_CONTROL_0_TX_FIFO_FLUSH_WOFFSET                        0x0
+#define DVC_FIFO_CONTROL_0_TX_FIFO_FLUSH_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_FIFO_CONTROL_0_TX_FIFO_FLUSH_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define DVC_FIFO_CONTROL_0_TX_FIFO_FLUSH_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_FIFO_CONTROL_0_TX_FIFO_FLUSH_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define DVC_FIFO_CONTROL_0_TX_FIFO_FLUSH_UNSET                  _MK_ENUM_CONST(0)
+#define DVC_FIFO_CONTROL_0_TX_FIFO_FLUSH_SET                    _MK_ENUM_CONST(1)
+
+//1= flush the rx fifo,cleared after fifo is flushed 
+#define DVC_FIFO_CONTROL_0_RX_FIFO_FLUSH_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_FIFO_CONTROL_0_RX_FIFO_FLUSH_FIELD                  (_MK_MASK_CONST(0x1) << DVC_FIFO_CONTROL_0_RX_FIFO_FLUSH_SHIFT)
+#define DVC_FIFO_CONTROL_0_RX_FIFO_FLUSH_RANGE                  0:0
+#define DVC_FIFO_CONTROL_0_RX_FIFO_FLUSH_WOFFSET                        0x0
+#define DVC_FIFO_CONTROL_0_RX_FIFO_FLUSH_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_FIFO_CONTROL_0_RX_FIFO_FLUSH_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define DVC_FIFO_CONTROL_0_RX_FIFO_FLUSH_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_FIFO_CONTROL_0_RX_FIFO_FLUSH_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define DVC_FIFO_CONTROL_0_RX_FIFO_FLUSH_UNSET                  _MK_ENUM_CONST(0)
+#define DVC_FIFO_CONTROL_0_RX_FIFO_FLUSH_SET                    _MK_ENUM_CONST(1)
+
+
+// Register DVC_FIFO_STATUS_0  
+#define DVC_FIFO_STATUS_0                       _MK_ADDR_CONST(0x70)
+#define DVC_FIFO_STATUS_0_SECURE                        0x0
+#define DVC_FIFO_STATUS_0_WORD_COUNT                    0x1
+#define DVC_FIFO_STATUS_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define DVC_FIFO_STATUS_0_RESET_MASK                    _MK_MASK_CONST(0xff)
+#define DVC_FIFO_STATUS_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define DVC_FIFO_STATUS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define DVC_FIFO_STATUS_0_READ_MASK                     _MK_MASK_CONST(0xff)
+#define DVC_FIFO_STATUS_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+//The number of slots that can be written to the tx fifo
+//0000 = tx_fifo full
+//0001 = 1 slot empty 
+//0010 = 2 slots empty 
+#define DVC_FIFO_STATUS_0_TX_FIFO_EMPTY_CNT_SHIFT                       _MK_SHIFT_CONST(4)
+#define DVC_FIFO_STATUS_0_TX_FIFO_EMPTY_CNT_FIELD                       (_MK_MASK_CONST(0xf) << DVC_FIFO_STATUS_0_TX_FIFO_EMPTY_CNT_SHIFT)
+#define DVC_FIFO_STATUS_0_TX_FIFO_EMPTY_CNT_RANGE                       7:4
+#define DVC_FIFO_STATUS_0_TX_FIFO_EMPTY_CNT_WOFFSET                     0x0
+#define DVC_FIFO_STATUS_0_TX_FIFO_EMPTY_CNT_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_FIFO_STATUS_0_TX_FIFO_EMPTY_CNT_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define DVC_FIFO_STATUS_0_TX_FIFO_EMPTY_CNT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define DVC_FIFO_STATUS_0_TX_FIFO_EMPTY_CNT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+//The number of slots to be read from  the rx fifo
+//0000 = rx_fifo empty
+//0001 = 1 slot  full
+//0010 = 2 slots  full
+#define DVC_FIFO_STATUS_0_RX_FIFO_FULL_CNT_SHIFT                        _MK_SHIFT_CONST(0)
+#define DVC_FIFO_STATUS_0_RX_FIFO_FULL_CNT_FIELD                        (_MK_MASK_CONST(0xf) << DVC_FIFO_STATUS_0_RX_FIFO_FULL_CNT_SHIFT)
+#define DVC_FIFO_STATUS_0_RX_FIFO_FULL_CNT_RANGE                        3:0
+#define DVC_FIFO_STATUS_0_RX_FIFO_FULL_CNT_WOFFSET                      0x0
+#define DVC_FIFO_STATUS_0_RX_FIFO_FULL_CNT_DEFAULT                      _MK_MASK_CONST(0x0)
+#define DVC_FIFO_STATUS_0_RX_FIFO_FULL_CNT_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define DVC_FIFO_STATUS_0_RX_FIFO_FULL_CNT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define DVC_FIFO_STATUS_0_RX_FIFO_FULL_CNT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register DVC_INTERRUPT_MASK_REGISTER_0  
+#define DVC_INTERRUPT_MASK_REGISTER_0                   _MK_ADDR_CONST(0x74)
+#define DVC_INTERRUPT_MASK_REGISTER_0_SECURE                    0x0
+#define DVC_INTERRUPT_MASK_REGISTER_0_WORD_COUNT                        0x1
+#define DVC_INTERRUPT_MASK_REGISTER_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define DVC_INTERRUPT_MASK_REGISTER_0_RESET_MASK                        _MK_MASK_CONST(0x7f)
+#define DVC_INTERRUPT_MASK_REGISTER_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define DVC_INTERRUPT_MASK_REGISTER_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define DVC_INTERRUPT_MASK_REGISTER_0_READ_MASK                         _MK_MASK_CONST(0x7f)
+#define DVC_INTERRUPT_MASK_REGISTER_0_WRITE_MASK                        _MK_MASK_CONST(0x7f)
+#define DVC_INTERRUPT_MASK_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_INT_EN_SHIFT                    _MK_SHIFT_CONST(6)
+#define DVC_INTERRUPT_MASK_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_INT_EN_FIELD                    (_MK_MASK_CONST(0x1) << DVC_INTERRUPT_MASK_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_INT_EN_SHIFT)
+#define DVC_INTERRUPT_MASK_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_INT_EN_RANGE                    6:6
+#define DVC_INTERRUPT_MASK_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_INT_EN_WOFFSET                  0x0
+#define DVC_INTERRUPT_MASK_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_INT_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define DVC_INTERRUPT_MASK_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_INT_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define DVC_INTERRUPT_MASK_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_INT_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_INTERRUPT_MASK_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_INT_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define DVC_INTERRUPT_MASK_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_INT_EN_DISABLE                  _MK_ENUM_CONST(0)
+#define DVC_INTERRUPT_MASK_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_INT_EN_ENABLE                   _MK_ENUM_CONST(1)
+
+#define DVC_INTERRUPT_MASK_REGISTER_0_TFIFO_OVF_INT_EN_SHIFT                    _MK_SHIFT_CONST(5)
+#define DVC_INTERRUPT_MASK_REGISTER_0_TFIFO_OVF_INT_EN_FIELD                    (_MK_MASK_CONST(0x1) << DVC_INTERRUPT_MASK_REGISTER_0_TFIFO_OVF_INT_EN_SHIFT)
+#define DVC_INTERRUPT_MASK_REGISTER_0_TFIFO_OVF_INT_EN_RANGE                    5:5
+#define DVC_INTERRUPT_MASK_REGISTER_0_TFIFO_OVF_INT_EN_WOFFSET                  0x0
+#define DVC_INTERRUPT_MASK_REGISTER_0_TFIFO_OVF_INT_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define DVC_INTERRUPT_MASK_REGISTER_0_TFIFO_OVF_INT_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define DVC_INTERRUPT_MASK_REGISTER_0_TFIFO_OVF_INT_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_INTERRUPT_MASK_REGISTER_0_TFIFO_OVF_INT_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define DVC_INTERRUPT_MASK_REGISTER_0_TFIFO_OVF_INT_EN_DISABLE                  _MK_ENUM_CONST(0)
+#define DVC_INTERRUPT_MASK_REGISTER_0_TFIFO_OVF_INT_EN_ENABLE                   _MK_ENUM_CONST(1)
+
+#define DVC_INTERRUPT_MASK_REGISTER_0_RFIFO_UNF_INT_EN_SHIFT                    _MK_SHIFT_CONST(4)
+#define DVC_INTERRUPT_MASK_REGISTER_0_RFIFO_UNF_INT_EN_FIELD                    (_MK_MASK_CONST(0x1) << DVC_INTERRUPT_MASK_REGISTER_0_RFIFO_UNF_INT_EN_SHIFT)
+#define DVC_INTERRUPT_MASK_REGISTER_0_RFIFO_UNF_INT_EN_RANGE                    4:4
+#define DVC_INTERRUPT_MASK_REGISTER_0_RFIFO_UNF_INT_EN_WOFFSET                  0x0
+#define DVC_INTERRUPT_MASK_REGISTER_0_RFIFO_UNF_INT_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define DVC_INTERRUPT_MASK_REGISTER_0_RFIFO_UNF_INT_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define DVC_INTERRUPT_MASK_REGISTER_0_RFIFO_UNF_INT_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_INTERRUPT_MASK_REGISTER_0_RFIFO_UNF_INT_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define DVC_INTERRUPT_MASK_REGISTER_0_RFIFO_UNF_INT_EN_DISABLE                  _MK_ENUM_CONST(0)
+#define DVC_INTERRUPT_MASK_REGISTER_0_RFIFO_UNF_INT_EN_ENABLE                   _MK_ENUM_CONST(1)
+
+#define DVC_INTERRUPT_MASK_REGISTER_0_NOACK_INT_EN_SHIFT                        _MK_SHIFT_CONST(3)
+#define DVC_INTERRUPT_MASK_REGISTER_0_NOACK_INT_EN_FIELD                        (_MK_MASK_CONST(0x1) << DVC_INTERRUPT_MASK_REGISTER_0_NOACK_INT_EN_SHIFT)
+#define DVC_INTERRUPT_MASK_REGISTER_0_NOACK_INT_EN_RANGE                        3:3
+#define DVC_INTERRUPT_MASK_REGISTER_0_NOACK_INT_EN_WOFFSET                      0x0
+#define DVC_INTERRUPT_MASK_REGISTER_0_NOACK_INT_EN_DEFAULT                      _MK_MASK_CONST(0x0)
+#define DVC_INTERRUPT_MASK_REGISTER_0_NOACK_INT_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define DVC_INTERRUPT_MASK_REGISTER_0_NOACK_INT_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define DVC_INTERRUPT_MASK_REGISTER_0_NOACK_INT_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define DVC_INTERRUPT_MASK_REGISTER_0_NOACK_INT_EN_DISABLE                      _MK_ENUM_CONST(0)
+#define DVC_INTERRUPT_MASK_REGISTER_0_NOACK_INT_EN_ENABLE                       _MK_ENUM_CONST(1)
+
+#define DVC_INTERRUPT_MASK_REGISTER_0_ARB_LOST_INT_EN_SHIFT                     _MK_SHIFT_CONST(2)
+#define DVC_INTERRUPT_MASK_REGISTER_0_ARB_LOST_INT_EN_FIELD                     (_MK_MASK_CONST(0x1) << DVC_INTERRUPT_MASK_REGISTER_0_ARB_LOST_INT_EN_SHIFT)
+#define DVC_INTERRUPT_MASK_REGISTER_0_ARB_LOST_INT_EN_RANGE                     2:2
+#define DVC_INTERRUPT_MASK_REGISTER_0_ARB_LOST_INT_EN_WOFFSET                   0x0
+#define DVC_INTERRUPT_MASK_REGISTER_0_ARB_LOST_INT_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define DVC_INTERRUPT_MASK_REGISTER_0_ARB_LOST_INT_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define DVC_INTERRUPT_MASK_REGISTER_0_ARB_LOST_INT_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_INTERRUPT_MASK_REGISTER_0_ARB_LOST_INT_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define DVC_INTERRUPT_MASK_REGISTER_0_ARB_LOST_INT_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define DVC_INTERRUPT_MASK_REGISTER_0_ARB_LOST_INT_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+#define DVC_INTERRUPT_MASK_REGISTER_0_TFIFO_DATA_REQ_INT_EN_SHIFT                       _MK_SHIFT_CONST(1)
+#define DVC_INTERRUPT_MASK_REGISTER_0_TFIFO_DATA_REQ_INT_EN_FIELD                       (_MK_MASK_CONST(0x1) << DVC_INTERRUPT_MASK_REGISTER_0_TFIFO_DATA_REQ_INT_EN_SHIFT)
+#define DVC_INTERRUPT_MASK_REGISTER_0_TFIFO_DATA_REQ_INT_EN_RANGE                       1:1
+#define DVC_INTERRUPT_MASK_REGISTER_0_TFIFO_DATA_REQ_INT_EN_WOFFSET                     0x0
+#define DVC_INTERRUPT_MASK_REGISTER_0_TFIFO_DATA_REQ_INT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_INTERRUPT_MASK_REGISTER_0_TFIFO_DATA_REQ_INT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define DVC_INTERRUPT_MASK_REGISTER_0_TFIFO_DATA_REQ_INT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define DVC_INTERRUPT_MASK_REGISTER_0_TFIFO_DATA_REQ_INT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_INTERRUPT_MASK_REGISTER_0_TFIFO_DATA_REQ_INT_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define DVC_INTERRUPT_MASK_REGISTER_0_TFIFO_DATA_REQ_INT_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+#define DVC_INTERRUPT_MASK_REGISTER_0_RFIFO_DATA_REQ_INT_EN_SHIFT                       _MK_SHIFT_CONST(0)
+#define DVC_INTERRUPT_MASK_REGISTER_0_RFIFO_DATA_REQ_INT_EN_FIELD                       (_MK_MASK_CONST(0x1) << DVC_INTERRUPT_MASK_REGISTER_0_RFIFO_DATA_REQ_INT_EN_SHIFT)
+#define DVC_INTERRUPT_MASK_REGISTER_0_RFIFO_DATA_REQ_INT_EN_RANGE                       0:0
+#define DVC_INTERRUPT_MASK_REGISTER_0_RFIFO_DATA_REQ_INT_EN_WOFFSET                     0x0
+#define DVC_INTERRUPT_MASK_REGISTER_0_RFIFO_DATA_REQ_INT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_INTERRUPT_MASK_REGISTER_0_RFIFO_DATA_REQ_INT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define DVC_INTERRUPT_MASK_REGISTER_0_RFIFO_DATA_REQ_INT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define DVC_INTERRUPT_MASK_REGISTER_0_RFIFO_DATA_REQ_INT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_INTERRUPT_MASK_REGISTER_0_RFIFO_DATA_REQ_INT_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define DVC_INTERRUPT_MASK_REGISTER_0_RFIFO_DATA_REQ_INT_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+
+// Register DVC_INTERRUPT_STATUS_REGISTER_0  //This register indicates the status bit for which the interrupt is set.If set,Write 1 to clear it
+//However TFIFO_DATA_REQ,RFIFO_DATA_REQ fields depend on the fifo trigger levels and cannot be cleared.
+#define DVC_INTERRUPT_STATUS_REGISTER_0                 _MK_ADDR_CONST(0x78)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_SECURE                  0x0
+#define DVC_INTERRUPT_STATUS_REGISTER_0_WORD_COUNT                      0x1
+#define DVC_INTERRUPT_STATUS_REGISTER_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_RESET_MASK                      _MK_MASK_CONST(0xff)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_READ_MASK                       _MK_MASK_CONST(0xff)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_WRITE_MASK                      _MK_MASK_CONST(0xff)
+//A packet has been transferred succesfully.
+//TRANSFER_PKT_ID filed can be used to know the 
+//current byte under transfer.This bit can be
+//masked by the IE field in the i2c specific header
+#define DVC_INTERRUPT_STATUS_REGISTER_0_PACKET_XFER_COMPLETE_SHIFT                      _MK_SHIFT_CONST(7)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_PACKET_XFER_COMPLETE_FIELD                      (_MK_MASK_CONST(0x1) << DVC_INTERRUPT_STATUS_REGISTER_0_PACKET_XFER_COMPLETE_SHIFT)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_PACKET_XFER_COMPLETE_RANGE                      7:7
+#define DVC_INTERRUPT_STATUS_REGISTER_0_PACKET_XFER_COMPLETE_WOFFSET                    0x0
+#define DVC_INTERRUPT_STATUS_REGISTER_0_PACKET_XFER_COMPLETE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_PACKET_XFER_COMPLETE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_PACKET_XFER_COMPLETE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_PACKET_XFER_COMPLETE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_PACKET_XFER_COMPLETE_UNSET                      _MK_ENUM_CONST(0)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_PACKET_XFER_COMPLETE_SET                        _MK_ENUM_CONST(1)
+
+//All the packets transferred succesfully
+#define DVC_INTERRUPT_STATUS_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_SHIFT                 _MK_SHIFT_CONST(6)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_FIELD                 (_MK_MASK_CONST(0x1) << DVC_INTERRUPT_STATUS_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_SHIFT)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_RANGE                 6:6
+#define DVC_INTERRUPT_STATUS_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_WOFFSET                       0x0
+#define DVC_INTERRUPT_STATUS_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_UNSET                 _MK_ENUM_CONST(0)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_SET                   _MK_ENUM_CONST(1)
+
+//Tx fifo overflow
+#define DVC_INTERRUPT_STATUS_REGISTER_0_TFIFO_OVF_SHIFT                 _MK_SHIFT_CONST(5)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_TFIFO_OVF_FIELD                 (_MK_MASK_CONST(0x1) << DVC_INTERRUPT_STATUS_REGISTER_0_TFIFO_OVF_SHIFT)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_TFIFO_OVF_RANGE                 5:5
+#define DVC_INTERRUPT_STATUS_REGISTER_0_TFIFO_OVF_WOFFSET                       0x0
+#define DVC_INTERRUPT_STATUS_REGISTER_0_TFIFO_OVF_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_TFIFO_OVF_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_TFIFO_OVF_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_TFIFO_OVF_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_TFIFO_OVF_UNSET                 _MK_ENUM_CONST(0)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_TFIFO_OVF_SET                   _MK_ENUM_CONST(1)
+
+//rx fifo underflow
+#define DVC_INTERRUPT_STATUS_REGISTER_0_RFIFO_UNF_SHIFT                 _MK_SHIFT_CONST(4)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_RFIFO_UNF_FIELD                 (_MK_MASK_CONST(0x1) << DVC_INTERRUPT_STATUS_REGISTER_0_RFIFO_UNF_SHIFT)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_RFIFO_UNF_RANGE                 4:4
+#define DVC_INTERRUPT_STATUS_REGISTER_0_RFIFO_UNF_WOFFSET                       0x0
+#define DVC_INTERRUPT_STATUS_REGISTER_0_RFIFO_UNF_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_RFIFO_UNF_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_RFIFO_UNF_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_RFIFO_UNF_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_RFIFO_UNF_UNSET                 _MK_ENUM_CONST(0)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_RFIFO_UNF_SET                   _MK_ENUM_CONST(1)
+
+//No ACK from slave
+#define DVC_INTERRUPT_STATUS_REGISTER_0_NOACK_SHIFT                     _MK_SHIFT_CONST(3)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_NOACK_FIELD                     (_MK_MASK_CONST(0x1) << DVC_INTERRUPT_STATUS_REGISTER_0_NOACK_SHIFT)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_NOACK_RANGE                     3:3
+#define DVC_INTERRUPT_STATUS_REGISTER_0_NOACK_WOFFSET                   0x0
+#define DVC_INTERRUPT_STATUS_REGISTER_0_NOACK_DEFAULT                   _MK_MASK_CONST(0x0)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_NOACK_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_NOACK_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_NOACK_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_NOACK_UNSET                     _MK_ENUM_CONST(0)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_NOACK_SET                       _MK_ENUM_CONST(1)
+
+//Arbitration lost
+#define DVC_INTERRUPT_STATUS_REGISTER_0_ARB_LOST_SHIFT                  _MK_SHIFT_CONST(2)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_ARB_LOST_FIELD                  (_MK_MASK_CONST(0x1) << DVC_INTERRUPT_STATUS_REGISTER_0_ARB_LOST_SHIFT)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_ARB_LOST_RANGE                  2:2
+#define DVC_INTERRUPT_STATUS_REGISTER_0_ARB_LOST_WOFFSET                        0x0
+#define DVC_INTERRUPT_STATUS_REGISTER_0_ARB_LOST_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_ARB_LOST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_ARB_LOST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_ARB_LOST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_ARB_LOST_UNSET                  _MK_ENUM_CONST(0)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_ARB_LOST_SET                    _MK_ENUM_CONST(1)
+
+//Tx fifo data req
+#define DVC_INTERRUPT_STATUS_REGISTER_0_TFIFO_DATA_REQ_SHIFT                    _MK_SHIFT_CONST(1)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_TFIFO_DATA_REQ_FIELD                    (_MK_MASK_CONST(0x1) << DVC_INTERRUPT_STATUS_REGISTER_0_TFIFO_DATA_REQ_SHIFT)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_TFIFO_DATA_REQ_RANGE                    1:1
+#define DVC_INTERRUPT_STATUS_REGISTER_0_TFIFO_DATA_REQ_WOFFSET                  0x0
+#define DVC_INTERRUPT_STATUS_REGISTER_0_TFIFO_DATA_REQ_DEFAULT                  _MK_MASK_CONST(0x0)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_TFIFO_DATA_REQ_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_TFIFO_DATA_REQ_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_TFIFO_DATA_REQ_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_TFIFO_DATA_REQ_UNSET                    _MK_ENUM_CONST(0)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_TFIFO_DATA_REQ_SET                      _MK_ENUM_CONST(1)
+
+//rx fifo data req
+#define DVC_INTERRUPT_STATUS_REGISTER_0_RFIFO_DATA_REQ_SHIFT                    _MK_SHIFT_CONST(0)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_RFIFO_DATA_REQ_FIELD                    (_MK_MASK_CONST(0x1) << DVC_INTERRUPT_STATUS_REGISTER_0_RFIFO_DATA_REQ_SHIFT)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_RFIFO_DATA_REQ_RANGE                    0:0
+#define DVC_INTERRUPT_STATUS_REGISTER_0_RFIFO_DATA_REQ_WOFFSET                  0x0
+#define DVC_INTERRUPT_STATUS_REGISTER_0_RFIFO_DATA_REQ_DEFAULT                  _MK_MASK_CONST(0x0)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_RFIFO_DATA_REQ_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_RFIFO_DATA_REQ_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_RFIFO_DATA_REQ_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_RFIFO_DATA_REQ_UNSET                    _MK_ENUM_CONST(0)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_RFIFO_DATA_REQ_SET                      _MK_ENUM_CONST(1)
+
+
+// Register DVC_I2C_CLK_DIVISOR_REGISTER_0  
+#define DVC_I2C_CLK_DIVISOR_REGISTER_0                  _MK_ADDR_CONST(0x7c)
+#define DVC_I2C_CLK_DIVISOR_REGISTER_0_SECURE                   0x0
+#define DVC_I2C_CLK_DIVISOR_REGISTER_0_WORD_COUNT                       0x1
+#define DVC_I2C_CLK_DIVISOR_REGISTER_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define DVC_I2C_CLK_DIVISOR_REGISTER_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
+#define DVC_I2C_CLK_DIVISOR_REGISTER_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_I2C_CLK_DIVISOR_REGISTER_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define DVC_I2C_CLK_DIVISOR_REGISTER_0_READ_MASK                        _MK_MASK_CONST(0xffff)
+#define DVC_I2C_CLK_DIVISOR_REGISTER_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
+//N= divide by n+1
+#define DVC_I2C_CLK_DIVISOR_REGISTER_0_I2C_CLK_DIVISOR_HSMODE_SHIFT                     _MK_SHIFT_CONST(0)
+#define DVC_I2C_CLK_DIVISOR_REGISTER_0_I2C_CLK_DIVISOR_HSMODE_FIELD                     (_MK_MASK_CONST(0xffff) << DVC_I2C_CLK_DIVISOR_REGISTER_0_I2C_CLK_DIVISOR_HSMODE_SHIFT)
+#define DVC_I2C_CLK_DIVISOR_REGISTER_0_I2C_CLK_DIVISOR_HSMODE_RANGE                     15:0
+#define DVC_I2C_CLK_DIVISOR_REGISTER_0_I2C_CLK_DIVISOR_HSMODE_WOFFSET                   0x0
+#define DVC_I2C_CLK_DIVISOR_REGISTER_0_I2C_CLK_DIVISOR_HSMODE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define DVC_I2C_CLK_DIVISOR_REGISTER_0_I2C_CLK_DIVISOR_HSMODE_DEFAULT_MASK                      _MK_MASK_CONST(0xffff)
+#define DVC_I2C_CLK_DIVISOR_REGISTER_0_I2C_CLK_DIVISOR_HSMODE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_I2C_CLK_DIVISOR_REGISTER_0_I2C_CLK_DIVISOR_HSMODE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VSEL_MAP_LUT_0  
+#define DVC_VSEL_MAP_LUT_0                      _MK_ADDR_CONST(0x80)
+#define DVC_VSEL_MAP_LUT_0_SECURE                       0x0
+#define DVC_VSEL_MAP_LUT_0_WORD_COUNT                   0x1
+#define DVC_VSEL_MAP_LUT_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_0_RESET_MASK                   _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_0_READ_MASK                    _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_0_WRITE_MASK                   _MK_MASK_CONST(0x3ff)
+//VSEL3 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_0_VSEL3_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VSEL_MAP_LUT_0_VSEL3_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_0_VSEL3_SHIFT)
+#define DVC_VSEL_MAP_LUT_0_VSEL3_RANGE                  9:5
+#define DVC_VSEL_MAP_LUT_0_VSEL3_WOFFSET                        0x0
+#define DVC_VSEL_MAP_LUT_0_VSEL3_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_0_VSEL3_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_0_VSEL3_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_0_VSEL3_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//VSEL2 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_0_VSEL2_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VSEL_MAP_LUT_0_VSEL2_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_0_VSEL2_SHIFT)
+#define DVC_VSEL_MAP_LUT_0_VSEL2_RANGE                  4:0
+#define DVC_VSEL_MAP_LUT_0_VSEL2_WOFFSET                        0x0
+#define DVC_VSEL_MAP_LUT_0_VSEL2_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_0_VSEL2_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_0_VSEL2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_0_VSEL2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VSEL_MAP_LUT  
+#define DVC_VSEL_MAP_LUT                        _MK_ADDR_CONST(0x80)
+#define DVC_VSEL_MAP_LUT_SECURE                         0x0
+#define DVC_VSEL_MAP_LUT_WORD_COUNT                     0x1
+#define DVC_VSEL_MAP_LUT_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_RESET_MASK                     _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_READ_MASK                      _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_WRITE_MASK                     _MK_MASK_CONST(0x3ff)
+//VSEL3 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_VSEL3_SHIFT                    _MK_SHIFT_CONST(5)
+#define DVC_VSEL_MAP_LUT_VSEL3_FIELD                    (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_VSEL3_SHIFT)
+#define DVC_VSEL_MAP_LUT_VSEL3_RANGE                    9:5
+#define DVC_VSEL_MAP_LUT_VSEL3_WOFFSET                  0x0
+#define DVC_VSEL_MAP_LUT_VSEL3_DEFAULT                  _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_VSEL3_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_VSEL3_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_VSEL3_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+//VSEL2 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_VSEL2_SHIFT                    _MK_SHIFT_CONST(0)
+#define DVC_VSEL_MAP_LUT_VSEL2_FIELD                    (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_VSEL2_SHIFT)
+#define DVC_VSEL_MAP_LUT_VSEL2_RANGE                    4:0
+#define DVC_VSEL_MAP_LUT_VSEL2_WOFFSET                  0x0
+#define DVC_VSEL_MAP_LUT_VSEL2_DEFAULT                  _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_VSEL2_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_VSEL2_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_VSEL2_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VSEL_MAP_LUT_1  
+#define DVC_VSEL_MAP_LUT_1                      _MK_ADDR_CONST(0x84)
+#define DVC_VSEL_MAP_LUT_1_SECURE                       0x0
+#define DVC_VSEL_MAP_LUT_1_WORD_COUNT                   0x1
+#define DVC_VSEL_MAP_LUT_1_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_1_RESET_MASK                   _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_1_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_1_READ_MASK                    _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_1_WRITE_MASK                   _MK_MASK_CONST(0x3ff)
+//VSEL3 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_1_VSEL3_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VSEL_MAP_LUT_1_VSEL3_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_1_VSEL3_SHIFT)
+#define DVC_VSEL_MAP_LUT_1_VSEL3_RANGE                  9:5
+#define DVC_VSEL_MAP_LUT_1_VSEL3_WOFFSET                        0x0
+#define DVC_VSEL_MAP_LUT_1_VSEL3_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_1_VSEL3_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_1_VSEL3_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_1_VSEL3_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//VSEL2 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_1_VSEL2_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VSEL_MAP_LUT_1_VSEL2_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_1_VSEL2_SHIFT)
+#define DVC_VSEL_MAP_LUT_1_VSEL2_RANGE                  4:0
+#define DVC_VSEL_MAP_LUT_1_VSEL2_WOFFSET                        0x0
+#define DVC_VSEL_MAP_LUT_1_VSEL2_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_1_VSEL2_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_1_VSEL2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_1_VSEL2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VSEL_MAP_LUT_2  
+#define DVC_VSEL_MAP_LUT_2                      _MK_ADDR_CONST(0x88)
+#define DVC_VSEL_MAP_LUT_2_SECURE                       0x0
+#define DVC_VSEL_MAP_LUT_2_WORD_COUNT                   0x1
+#define DVC_VSEL_MAP_LUT_2_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_2_RESET_MASK                   _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_2_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_2_READ_MASK                    _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_2_WRITE_MASK                   _MK_MASK_CONST(0x3ff)
+//VSEL3 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_2_VSEL3_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VSEL_MAP_LUT_2_VSEL3_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_2_VSEL3_SHIFT)
+#define DVC_VSEL_MAP_LUT_2_VSEL3_RANGE                  9:5
+#define DVC_VSEL_MAP_LUT_2_VSEL3_WOFFSET                        0x0
+#define DVC_VSEL_MAP_LUT_2_VSEL3_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_2_VSEL3_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_2_VSEL3_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_2_VSEL3_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//VSEL2 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_2_VSEL2_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VSEL_MAP_LUT_2_VSEL2_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_2_VSEL2_SHIFT)
+#define DVC_VSEL_MAP_LUT_2_VSEL2_RANGE                  4:0
+#define DVC_VSEL_MAP_LUT_2_VSEL2_WOFFSET                        0x0
+#define DVC_VSEL_MAP_LUT_2_VSEL2_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_2_VSEL2_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_2_VSEL2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_2_VSEL2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VSEL_MAP_LUT_3  
+#define DVC_VSEL_MAP_LUT_3                      _MK_ADDR_CONST(0x8c)
+#define DVC_VSEL_MAP_LUT_3_SECURE                       0x0
+#define DVC_VSEL_MAP_LUT_3_WORD_COUNT                   0x1
+#define DVC_VSEL_MAP_LUT_3_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_3_RESET_MASK                   _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_3_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_3_READ_MASK                    _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_3_WRITE_MASK                   _MK_MASK_CONST(0x3ff)
+//VSEL3 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_3_VSEL3_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VSEL_MAP_LUT_3_VSEL3_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_3_VSEL3_SHIFT)
+#define DVC_VSEL_MAP_LUT_3_VSEL3_RANGE                  9:5
+#define DVC_VSEL_MAP_LUT_3_VSEL3_WOFFSET                        0x0
+#define DVC_VSEL_MAP_LUT_3_VSEL3_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_3_VSEL3_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_3_VSEL3_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_3_VSEL3_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//VSEL2 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_3_VSEL2_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VSEL_MAP_LUT_3_VSEL2_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_3_VSEL2_SHIFT)
+#define DVC_VSEL_MAP_LUT_3_VSEL2_RANGE                  4:0
+#define DVC_VSEL_MAP_LUT_3_VSEL2_WOFFSET                        0x0
+#define DVC_VSEL_MAP_LUT_3_VSEL2_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_3_VSEL2_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_3_VSEL2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_3_VSEL2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VSEL_MAP_LUT_4  
+#define DVC_VSEL_MAP_LUT_4                      _MK_ADDR_CONST(0x90)
+#define DVC_VSEL_MAP_LUT_4_SECURE                       0x0
+#define DVC_VSEL_MAP_LUT_4_WORD_COUNT                   0x1
+#define DVC_VSEL_MAP_LUT_4_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_4_RESET_MASK                   _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_4_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_4_READ_MASK                    _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_4_WRITE_MASK                   _MK_MASK_CONST(0x3ff)
+//VSEL3 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_4_VSEL3_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VSEL_MAP_LUT_4_VSEL3_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_4_VSEL3_SHIFT)
+#define DVC_VSEL_MAP_LUT_4_VSEL3_RANGE                  9:5
+#define DVC_VSEL_MAP_LUT_4_VSEL3_WOFFSET                        0x0
+#define DVC_VSEL_MAP_LUT_4_VSEL3_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_4_VSEL3_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_4_VSEL3_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_4_VSEL3_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//VSEL2 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_4_VSEL2_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VSEL_MAP_LUT_4_VSEL2_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_4_VSEL2_SHIFT)
+#define DVC_VSEL_MAP_LUT_4_VSEL2_RANGE                  4:0
+#define DVC_VSEL_MAP_LUT_4_VSEL2_WOFFSET                        0x0
+#define DVC_VSEL_MAP_LUT_4_VSEL2_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_4_VSEL2_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_4_VSEL2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_4_VSEL2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VSEL_MAP_LUT_5  
+#define DVC_VSEL_MAP_LUT_5                      _MK_ADDR_CONST(0x94)
+#define DVC_VSEL_MAP_LUT_5_SECURE                       0x0
+#define DVC_VSEL_MAP_LUT_5_WORD_COUNT                   0x1
+#define DVC_VSEL_MAP_LUT_5_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_5_RESET_MASK                   _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_5_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_5_READ_MASK                    _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_5_WRITE_MASK                   _MK_MASK_CONST(0x3ff)
+//VSEL3 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_5_VSEL3_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VSEL_MAP_LUT_5_VSEL3_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_5_VSEL3_SHIFT)
+#define DVC_VSEL_MAP_LUT_5_VSEL3_RANGE                  9:5
+#define DVC_VSEL_MAP_LUT_5_VSEL3_WOFFSET                        0x0
+#define DVC_VSEL_MAP_LUT_5_VSEL3_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_5_VSEL3_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_5_VSEL3_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_5_VSEL3_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//VSEL2 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_5_VSEL2_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VSEL_MAP_LUT_5_VSEL2_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_5_VSEL2_SHIFT)
+#define DVC_VSEL_MAP_LUT_5_VSEL2_RANGE                  4:0
+#define DVC_VSEL_MAP_LUT_5_VSEL2_WOFFSET                        0x0
+#define DVC_VSEL_MAP_LUT_5_VSEL2_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_5_VSEL2_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_5_VSEL2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_5_VSEL2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VSEL_MAP_LUT_6  
+#define DVC_VSEL_MAP_LUT_6                      _MK_ADDR_CONST(0x98)
+#define DVC_VSEL_MAP_LUT_6_SECURE                       0x0
+#define DVC_VSEL_MAP_LUT_6_WORD_COUNT                   0x1
+#define DVC_VSEL_MAP_LUT_6_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_6_RESET_MASK                   _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_6_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_6_READ_MASK                    _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_6_WRITE_MASK                   _MK_MASK_CONST(0x3ff)
+//VSEL3 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_6_VSEL3_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VSEL_MAP_LUT_6_VSEL3_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_6_VSEL3_SHIFT)
+#define DVC_VSEL_MAP_LUT_6_VSEL3_RANGE                  9:5
+#define DVC_VSEL_MAP_LUT_6_VSEL3_WOFFSET                        0x0
+#define DVC_VSEL_MAP_LUT_6_VSEL3_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_6_VSEL3_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_6_VSEL3_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_6_VSEL3_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//VSEL2 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_6_VSEL2_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VSEL_MAP_LUT_6_VSEL2_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_6_VSEL2_SHIFT)
+#define DVC_VSEL_MAP_LUT_6_VSEL2_RANGE                  4:0
+#define DVC_VSEL_MAP_LUT_6_VSEL2_WOFFSET                        0x0
+#define DVC_VSEL_MAP_LUT_6_VSEL2_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_6_VSEL2_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_6_VSEL2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_6_VSEL2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VSEL_MAP_LUT_7  
+#define DVC_VSEL_MAP_LUT_7                      _MK_ADDR_CONST(0x9c)
+#define DVC_VSEL_MAP_LUT_7_SECURE                       0x0
+#define DVC_VSEL_MAP_LUT_7_WORD_COUNT                   0x1
+#define DVC_VSEL_MAP_LUT_7_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_7_RESET_MASK                   _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_7_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_7_READ_MASK                    _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_7_WRITE_MASK                   _MK_MASK_CONST(0x3ff)
+//VSEL3 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_7_VSEL3_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VSEL_MAP_LUT_7_VSEL3_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_7_VSEL3_SHIFT)
+#define DVC_VSEL_MAP_LUT_7_VSEL3_RANGE                  9:5
+#define DVC_VSEL_MAP_LUT_7_VSEL3_WOFFSET                        0x0
+#define DVC_VSEL_MAP_LUT_7_VSEL3_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_7_VSEL3_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_7_VSEL3_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_7_VSEL3_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//VSEL2 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_7_VSEL2_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VSEL_MAP_LUT_7_VSEL2_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_7_VSEL2_SHIFT)
+#define DVC_VSEL_MAP_LUT_7_VSEL2_RANGE                  4:0
+#define DVC_VSEL_MAP_LUT_7_VSEL2_WOFFSET                        0x0
+#define DVC_VSEL_MAP_LUT_7_VSEL2_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_7_VSEL2_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_7_VSEL2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_7_VSEL2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VSEL_MAP_LUT_8  
+#define DVC_VSEL_MAP_LUT_8                      _MK_ADDR_CONST(0xa0)
+#define DVC_VSEL_MAP_LUT_8_SECURE                       0x0
+#define DVC_VSEL_MAP_LUT_8_WORD_COUNT                   0x1
+#define DVC_VSEL_MAP_LUT_8_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_8_RESET_MASK                   _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_8_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_8_READ_MASK                    _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_8_WRITE_MASK                   _MK_MASK_CONST(0x3ff)
+//VSEL3 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_8_VSEL3_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VSEL_MAP_LUT_8_VSEL3_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_8_VSEL3_SHIFT)
+#define DVC_VSEL_MAP_LUT_8_VSEL3_RANGE                  9:5
+#define DVC_VSEL_MAP_LUT_8_VSEL3_WOFFSET                        0x0
+#define DVC_VSEL_MAP_LUT_8_VSEL3_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_8_VSEL3_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_8_VSEL3_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_8_VSEL3_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//VSEL2 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_8_VSEL2_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VSEL_MAP_LUT_8_VSEL2_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_8_VSEL2_SHIFT)
+#define DVC_VSEL_MAP_LUT_8_VSEL2_RANGE                  4:0
+#define DVC_VSEL_MAP_LUT_8_VSEL2_WOFFSET                        0x0
+#define DVC_VSEL_MAP_LUT_8_VSEL2_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_8_VSEL2_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_8_VSEL2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_8_VSEL2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VSEL_MAP_LUT_9  
+#define DVC_VSEL_MAP_LUT_9                      _MK_ADDR_CONST(0xa4)
+#define DVC_VSEL_MAP_LUT_9_SECURE                       0x0
+#define DVC_VSEL_MAP_LUT_9_WORD_COUNT                   0x1
+#define DVC_VSEL_MAP_LUT_9_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_9_RESET_MASK                   _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_9_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_9_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_9_READ_MASK                    _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_9_WRITE_MASK                   _MK_MASK_CONST(0x3ff)
+//VSEL3 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_9_VSEL3_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VSEL_MAP_LUT_9_VSEL3_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_9_VSEL3_SHIFT)
+#define DVC_VSEL_MAP_LUT_9_VSEL3_RANGE                  9:5
+#define DVC_VSEL_MAP_LUT_9_VSEL3_WOFFSET                        0x0
+#define DVC_VSEL_MAP_LUT_9_VSEL3_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_9_VSEL3_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_9_VSEL3_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_9_VSEL3_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//VSEL2 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_9_VSEL2_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VSEL_MAP_LUT_9_VSEL2_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_9_VSEL2_SHIFT)
+#define DVC_VSEL_MAP_LUT_9_VSEL2_RANGE                  4:0
+#define DVC_VSEL_MAP_LUT_9_VSEL2_WOFFSET                        0x0
+#define DVC_VSEL_MAP_LUT_9_VSEL2_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_9_VSEL2_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_9_VSEL2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_9_VSEL2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VSEL_MAP_LUT_10  
+#define DVC_VSEL_MAP_LUT_10                     _MK_ADDR_CONST(0xa8)
+#define DVC_VSEL_MAP_LUT_10_SECURE                      0x0
+#define DVC_VSEL_MAP_LUT_10_WORD_COUNT                  0x1
+#define DVC_VSEL_MAP_LUT_10_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_10_RESET_MASK                  _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_10_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_10_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_10_READ_MASK                   _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_10_WRITE_MASK                  _MK_MASK_CONST(0x3ff)
+//VSEL3 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_10_VSEL3_SHIFT                 _MK_SHIFT_CONST(5)
+#define DVC_VSEL_MAP_LUT_10_VSEL3_FIELD                 (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_10_VSEL3_SHIFT)
+#define DVC_VSEL_MAP_LUT_10_VSEL3_RANGE                 9:5
+#define DVC_VSEL_MAP_LUT_10_VSEL3_WOFFSET                       0x0
+#define DVC_VSEL_MAP_LUT_10_VSEL3_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_10_VSEL3_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_10_VSEL3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_10_VSEL3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//VSEL2 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_10_VSEL2_SHIFT                 _MK_SHIFT_CONST(0)
+#define DVC_VSEL_MAP_LUT_10_VSEL2_FIELD                 (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_10_VSEL2_SHIFT)
+#define DVC_VSEL_MAP_LUT_10_VSEL2_RANGE                 4:0
+#define DVC_VSEL_MAP_LUT_10_VSEL2_WOFFSET                       0x0
+#define DVC_VSEL_MAP_LUT_10_VSEL2_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_10_VSEL2_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_10_VSEL2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_10_VSEL2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VSEL_MAP_LUT_11  
+#define DVC_VSEL_MAP_LUT_11                     _MK_ADDR_CONST(0xac)
+#define DVC_VSEL_MAP_LUT_11_SECURE                      0x0
+#define DVC_VSEL_MAP_LUT_11_WORD_COUNT                  0x1
+#define DVC_VSEL_MAP_LUT_11_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_11_RESET_MASK                  _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_11_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_11_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_11_READ_MASK                   _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_11_WRITE_MASK                  _MK_MASK_CONST(0x3ff)
+//VSEL3 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_11_VSEL3_SHIFT                 _MK_SHIFT_CONST(5)
+#define DVC_VSEL_MAP_LUT_11_VSEL3_FIELD                 (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_11_VSEL3_SHIFT)
+#define DVC_VSEL_MAP_LUT_11_VSEL3_RANGE                 9:5
+#define DVC_VSEL_MAP_LUT_11_VSEL3_WOFFSET                       0x0
+#define DVC_VSEL_MAP_LUT_11_VSEL3_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_11_VSEL3_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_11_VSEL3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_11_VSEL3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//VSEL2 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_11_VSEL2_SHIFT                 _MK_SHIFT_CONST(0)
+#define DVC_VSEL_MAP_LUT_11_VSEL2_FIELD                 (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_11_VSEL2_SHIFT)
+#define DVC_VSEL_MAP_LUT_11_VSEL2_RANGE                 4:0
+#define DVC_VSEL_MAP_LUT_11_VSEL2_WOFFSET                       0x0
+#define DVC_VSEL_MAP_LUT_11_VSEL2_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_11_VSEL2_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_11_VSEL2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_11_VSEL2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VSEL_MAP_LUT_12  
+#define DVC_VSEL_MAP_LUT_12                     _MK_ADDR_CONST(0xb0)
+#define DVC_VSEL_MAP_LUT_12_SECURE                      0x0
+#define DVC_VSEL_MAP_LUT_12_WORD_COUNT                  0x1
+#define DVC_VSEL_MAP_LUT_12_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_12_RESET_MASK                  _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_12_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_12_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_12_READ_MASK                   _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_12_WRITE_MASK                  _MK_MASK_CONST(0x3ff)
+//VSEL3 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_12_VSEL3_SHIFT                 _MK_SHIFT_CONST(5)
+#define DVC_VSEL_MAP_LUT_12_VSEL3_FIELD                 (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_12_VSEL3_SHIFT)
+#define DVC_VSEL_MAP_LUT_12_VSEL3_RANGE                 9:5
+#define DVC_VSEL_MAP_LUT_12_VSEL3_WOFFSET                       0x0
+#define DVC_VSEL_MAP_LUT_12_VSEL3_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_12_VSEL3_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_12_VSEL3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_12_VSEL3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//VSEL2 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_12_VSEL2_SHIFT                 _MK_SHIFT_CONST(0)
+#define DVC_VSEL_MAP_LUT_12_VSEL2_FIELD                 (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_12_VSEL2_SHIFT)
+#define DVC_VSEL_MAP_LUT_12_VSEL2_RANGE                 4:0
+#define DVC_VSEL_MAP_LUT_12_VSEL2_WOFFSET                       0x0
+#define DVC_VSEL_MAP_LUT_12_VSEL2_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_12_VSEL2_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_12_VSEL2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_12_VSEL2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VSEL_MAP_LUT_13  
+#define DVC_VSEL_MAP_LUT_13                     _MK_ADDR_CONST(0xb4)
+#define DVC_VSEL_MAP_LUT_13_SECURE                      0x0
+#define DVC_VSEL_MAP_LUT_13_WORD_COUNT                  0x1
+#define DVC_VSEL_MAP_LUT_13_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_13_RESET_MASK                  _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_13_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_13_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_13_READ_MASK                   _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_13_WRITE_MASK                  _MK_MASK_CONST(0x3ff)
+//VSEL3 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_13_VSEL3_SHIFT                 _MK_SHIFT_CONST(5)
+#define DVC_VSEL_MAP_LUT_13_VSEL3_FIELD                 (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_13_VSEL3_SHIFT)
+#define DVC_VSEL_MAP_LUT_13_VSEL3_RANGE                 9:5
+#define DVC_VSEL_MAP_LUT_13_VSEL3_WOFFSET                       0x0
+#define DVC_VSEL_MAP_LUT_13_VSEL3_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_13_VSEL3_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_13_VSEL3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_13_VSEL3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//VSEL2 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_13_VSEL2_SHIFT                 _MK_SHIFT_CONST(0)
+#define DVC_VSEL_MAP_LUT_13_VSEL2_FIELD                 (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_13_VSEL2_SHIFT)
+#define DVC_VSEL_MAP_LUT_13_VSEL2_RANGE                 4:0
+#define DVC_VSEL_MAP_LUT_13_VSEL2_WOFFSET                       0x0
+#define DVC_VSEL_MAP_LUT_13_VSEL2_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_13_VSEL2_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_13_VSEL2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_13_VSEL2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VSEL_MAP_LUT_14  
+#define DVC_VSEL_MAP_LUT_14                     _MK_ADDR_CONST(0xb8)
+#define DVC_VSEL_MAP_LUT_14_SECURE                      0x0
+#define DVC_VSEL_MAP_LUT_14_WORD_COUNT                  0x1
+#define DVC_VSEL_MAP_LUT_14_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_14_RESET_MASK                  _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_14_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_14_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_14_READ_MASK                   _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_14_WRITE_MASK                  _MK_MASK_CONST(0x3ff)
+//VSEL3 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_14_VSEL3_SHIFT                 _MK_SHIFT_CONST(5)
+#define DVC_VSEL_MAP_LUT_14_VSEL3_FIELD                 (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_14_VSEL3_SHIFT)
+#define DVC_VSEL_MAP_LUT_14_VSEL3_RANGE                 9:5
+#define DVC_VSEL_MAP_LUT_14_VSEL3_WOFFSET                       0x0
+#define DVC_VSEL_MAP_LUT_14_VSEL3_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_14_VSEL3_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_14_VSEL3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_14_VSEL3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//VSEL2 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_14_VSEL2_SHIFT                 _MK_SHIFT_CONST(0)
+#define DVC_VSEL_MAP_LUT_14_VSEL2_FIELD                 (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_14_VSEL2_SHIFT)
+#define DVC_VSEL_MAP_LUT_14_VSEL2_RANGE                 4:0
+#define DVC_VSEL_MAP_LUT_14_VSEL2_WOFFSET                       0x0
+#define DVC_VSEL_MAP_LUT_14_VSEL2_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_14_VSEL2_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_14_VSEL2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_14_VSEL2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VSEL_MAP_LUT_15  
+#define DVC_VSEL_MAP_LUT_15                     _MK_ADDR_CONST(0xbc)
+#define DVC_VSEL_MAP_LUT_15_SECURE                      0x0
+#define DVC_VSEL_MAP_LUT_15_WORD_COUNT                  0x1
+#define DVC_VSEL_MAP_LUT_15_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_15_RESET_MASK                  _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_15_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_15_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_15_READ_MASK                   _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_15_WRITE_MASK                  _MK_MASK_CONST(0x3ff)
+//VSEL3 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_15_VSEL3_SHIFT                 _MK_SHIFT_CONST(5)
+#define DVC_VSEL_MAP_LUT_15_VSEL3_FIELD                 (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_15_VSEL3_SHIFT)
+#define DVC_VSEL_MAP_LUT_15_VSEL3_RANGE                 9:5
+#define DVC_VSEL_MAP_LUT_15_VSEL3_WOFFSET                       0x0
+#define DVC_VSEL_MAP_LUT_15_VSEL3_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_15_VSEL3_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_15_VSEL3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_15_VSEL3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//VSEL2 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_15_VSEL2_SHIFT                 _MK_SHIFT_CONST(0)
+#define DVC_VSEL_MAP_LUT_15_VSEL2_FIELD                 (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_15_VSEL2_SHIFT)
+#define DVC_VSEL_MAP_LUT_15_VSEL2_RANGE                 4:0
+#define DVC_VSEL_MAP_LUT_15_VSEL2_WOFFSET                       0x0
+#define DVC_VSEL_MAP_LUT_15_VSEL2_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_15_VSEL2_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_15_VSEL2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_15_VSEL2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VSEL_MAP_LUT_16  
+#define DVC_VSEL_MAP_LUT_16                     _MK_ADDR_CONST(0xc0)
+#define DVC_VSEL_MAP_LUT_16_SECURE                      0x0
+#define DVC_VSEL_MAP_LUT_16_WORD_COUNT                  0x1
+#define DVC_VSEL_MAP_LUT_16_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_16_RESET_MASK                  _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_16_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_16_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_16_READ_MASK                   _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_16_WRITE_MASK                  _MK_MASK_CONST(0x3ff)
+//VSEL3 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_16_VSEL3_SHIFT                 _MK_SHIFT_CONST(5)
+#define DVC_VSEL_MAP_LUT_16_VSEL3_FIELD                 (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_16_VSEL3_SHIFT)
+#define DVC_VSEL_MAP_LUT_16_VSEL3_RANGE                 9:5
+#define DVC_VSEL_MAP_LUT_16_VSEL3_WOFFSET                       0x0
+#define DVC_VSEL_MAP_LUT_16_VSEL3_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_16_VSEL3_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_16_VSEL3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_16_VSEL3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//VSEL2 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_16_VSEL2_SHIFT                 _MK_SHIFT_CONST(0)
+#define DVC_VSEL_MAP_LUT_16_VSEL2_FIELD                 (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_16_VSEL2_SHIFT)
+#define DVC_VSEL_MAP_LUT_16_VSEL2_RANGE                 4:0
+#define DVC_VSEL_MAP_LUT_16_VSEL2_WOFFSET                       0x0
+#define DVC_VSEL_MAP_LUT_16_VSEL2_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_16_VSEL2_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_16_VSEL2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_16_VSEL2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VSEL_MAP_LUT_17  
+#define DVC_VSEL_MAP_LUT_17                     _MK_ADDR_CONST(0xc4)
+#define DVC_VSEL_MAP_LUT_17_SECURE                      0x0
+#define DVC_VSEL_MAP_LUT_17_WORD_COUNT                  0x1
+#define DVC_VSEL_MAP_LUT_17_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_17_RESET_MASK                  _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_17_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_17_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_17_READ_MASK                   _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_17_WRITE_MASK                  _MK_MASK_CONST(0x3ff)
+//VSEL3 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_17_VSEL3_SHIFT                 _MK_SHIFT_CONST(5)
+#define DVC_VSEL_MAP_LUT_17_VSEL3_FIELD                 (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_17_VSEL3_SHIFT)
+#define DVC_VSEL_MAP_LUT_17_VSEL3_RANGE                 9:5
+#define DVC_VSEL_MAP_LUT_17_VSEL3_WOFFSET                       0x0
+#define DVC_VSEL_MAP_LUT_17_VSEL3_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_17_VSEL3_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_17_VSEL3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_17_VSEL3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//VSEL2 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_17_VSEL2_SHIFT                 _MK_SHIFT_CONST(0)
+#define DVC_VSEL_MAP_LUT_17_VSEL2_FIELD                 (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_17_VSEL2_SHIFT)
+#define DVC_VSEL_MAP_LUT_17_VSEL2_RANGE                 4:0
+#define DVC_VSEL_MAP_LUT_17_VSEL2_WOFFSET                       0x0
+#define DVC_VSEL_MAP_LUT_17_VSEL2_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_17_VSEL2_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_17_VSEL2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_17_VSEL2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VSEL_MAP_LUT_18  
+#define DVC_VSEL_MAP_LUT_18                     _MK_ADDR_CONST(0xc8)
+#define DVC_VSEL_MAP_LUT_18_SECURE                      0x0
+#define DVC_VSEL_MAP_LUT_18_WORD_COUNT                  0x1
+#define DVC_VSEL_MAP_LUT_18_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_18_RESET_MASK                  _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_18_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_18_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_18_READ_MASK                   _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_18_WRITE_MASK                  _MK_MASK_CONST(0x3ff)
+//VSEL3 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_18_VSEL3_SHIFT                 _MK_SHIFT_CONST(5)
+#define DVC_VSEL_MAP_LUT_18_VSEL3_FIELD                 (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_18_VSEL3_SHIFT)
+#define DVC_VSEL_MAP_LUT_18_VSEL3_RANGE                 9:5
+#define DVC_VSEL_MAP_LUT_18_VSEL3_WOFFSET                       0x0
+#define DVC_VSEL_MAP_LUT_18_VSEL3_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_18_VSEL3_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_18_VSEL3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_18_VSEL3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//VSEL2 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_18_VSEL2_SHIFT                 _MK_SHIFT_CONST(0)
+#define DVC_VSEL_MAP_LUT_18_VSEL2_FIELD                 (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_18_VSEL2_SHIFT)
+#define DVC_VSEL_MAP_LUT_18_VSEL2_RANGE                 4:0
+#define DVC_VSEL_MAP_LUT_18_VSEL2_WOFFSET                       0x0
+#define DVC_VSEL_MAP_LUT_18_VSEL2_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_18_VSEL2_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_18_VSEL2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_18_VSEL2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VSEL_MAP_LUT_19  
+#define DVC_VSEL_MAP_LUT_19                     _MK_ADDR_CONST(0xcc)
+#define DVC_VSEL_MAP_LUT_19_SECURE                      0x0
+#define DVC_VSEL_MAP_LUT_19_WORD_COUNT                  0x1
+#define DVC_VSEL_MAP_LUT_19_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_19_RESET_MASK                  _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_19_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_19_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_19_READ_MASK                   _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_19_WRITE_MASK                  _MK_MASK_CONST(0x3ff)
+//VSEL3 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_19_VSEL3_SHIFT                 _MK_SHIFT_CONST(5)
+#define DVC_VSEL_MAP_LUT_19_VSEL3_FIELD                 (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_19_VSEL3_SHIFT)
+#define DVC_VSEL_MAP_LUT_19_VSEL3_RANGE                 9:5
+#define DVC_VSEL_MAP_LUT_19_VSEL3_WOFFSET                       0x0
+#define DVC_VSEL_MAP_LUT_19_VSEL3_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_19_VSEL3_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_19_VSEL3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_19_VSEL3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//VSEL2 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_19_VSEL2_SHIFT                 _MK_SHIFT_CONST(0)
+#define DVC_VSEL_MAP_LUT_19_VSEL2_FIELD                 (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_19_VSEL2_SHIFT)
+#define DVC_VSEL_MAP_LUT_19_VSEL2_RANGE                 4:0
+#define DVC_VSEL_MAP_LUT_19_VSEL2_WOFFSET                       0x0
+#define DVC_VSEL_MAP_LUT_19_VSEL2_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_19_VSEL2_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_19_VSEL2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_19_VSEL2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VSEL_MAP_LUT_20  
+#define DVC_VSEL_MAP_LUT_20                     _MK_ADDR_CONST(0xd0)
+#define DVC_VSEL_MAP_LUT_20_SECURE                      0x0
+#define DVC_VSEL_MAP_LUT_20_WORD_COUNT                  0x1
+#define DVC_VSEL_MAP_LUT_20_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_20_RESET_MASK                  _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_20_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_20_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_20_READ_MASK                   _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_20_WRITE_MASK                  _MK_MASK_CONST(0x3ff)
+//VSEL3 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_20_VSEL3_SHIFT                 _MK_SHIFT_CONST(5)
+#define DVC_VSEL_MAP_LUT_20_VSEL3_FIELD                 (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_20_VSEL3_SHIFT)
+#define DVC_VSEL_MAP_LUT_20_VSEL3_RANGE                 9:5
+#define DVC_VSEL_MAP_LUT_20_VSEL3_WOFFSET                       0x0
+#define DVC_VSEL_MAP_LUT_20_VSEL3_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_20_VSEL3_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_20_VSEL3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_20_VSEL3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//VSEL2 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_20_VSEL2_SHIFT                 _MK_SHIFT_CONST(0)
+#define DVC_VSEL_MAP_LUT_20_VSEL2_FIELD                 (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_20_VSEL2_SHIFT)
+#define DVC_VSEL_MAP_LUT_20_VSEL2_RANGE                 4:0
+#define DVC_VSEL_MAP_LUT_20_VSEL2_WOFFSET                       0x0
+#define DVC_VSEL_MAP_LUT_20_VSEL2_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_20_VSEL2_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_20_VSEL2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_20_VSEL2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VSEL_MAP_LUT_21  
+#define DVC_VSEL_MAP_LUT_21                     _MK_ADDR_CONST(0xd4)
+#define DVC_VSEL_MAP_LUT_21_SECURE                      0x0
+#define DVC_VSEL_MAP_LUT_21_WORD_COUNT                  0x1
+#define DVC_VSEL_MAP_LUT_21_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_21_RESET_MASK                  _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_21_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_21_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_21_READ_MASK                   _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_21_WRITE_MASK                  _MK_MASK_CONST(0x3ff)
+//VSEL3 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_21_VSEL3_SHIFT                 _MK_SHIFT_CONST(5)
+#define DVC_VSEL_MAP_LUT_21_VSEL3_FIELD                 (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_21_VSEL3_SHIFT)
+#define DVC_VSEL_MAP_LUT_21_VSEL3_RANGE                 9:5
+#define DVC_VSEL_MAP_LUT_21_VSEL3_WOFFSET                       0x0
+#define DVC_VSEL_MAP_LUT_21_VSEL3_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_21_VSEL3_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_21_VSEL3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_21_VSEL3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//VSEL2 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_21_VSEL2_SHIFT                 _MK_SHIFT_CONST(0)
+#define DVC_VSEL_MAP_LUT_21_VSEL2_FIELD                 (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_21_VSEL2_SHIFT)
+#define DVC_VSEL_MAP_LUT_21_VSEL2_RANGE                 4:0
+#define DVC_VSEL_MAP_LUT_21_VSEL2_WOFFSET                       0x0
+#define DVC_VSEL_MAP_LUT_21_VSEL2_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_21_VSEL2_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_21_VSEL2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_21_VSEL2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VSEL_MAP_LUT_22  
+#define DVC_VSEL_MAP_LUT_22                     _MK_ADDR_CONST(0xd8)
+#define DVC_VSEL_MAP_LUT_22_SECURE                      0x0
+#define DVC_VSEL_MAP_LUT_22_WORD_COUNT                  0x1
+#define DVC_VSEL_MAP_LUT_22_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_22_RESET_MASK                  _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_22_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_22_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_22_READ_MASK                   _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_22_WRITE_MASK                  _MK_MASK_CONST(0x3ff)
+//VSEL3 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_22_VSEL3_SHIFT                 _MK_SHIFT_CONST(5)
+#define DVC_VSEL_MAP_LUT_22_VSEL3_FIELD                 (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_22_VSEL3_SHIFT)
+#define DVC_VSEL_MAP_LUT_22_VSEL3_RANGE                 9:5
+#define DVC_VSEL_MAP_LUT_22_VSEL3_WOFFSET                       0x0
+#define DVC_VSEL_MAP_LUT_22_VSEL3_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_22_VSEL3_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_22_VSEL3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_22_VSEL3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//VSEL2 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_22_VSEL2_SHIFT                 _MK_SHIFT_CONST(0)
+#define DVC_VSEL_MAP_LUT_22_VSEL2_FIELD                 (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_22_VSEL2_SHIFT)
+#define DVC_VSEL_MAP_LUT_22_VSEL2_RANGE                 4:0
+#define DVC_VSEL_MAP_LUT_22_VSEL2_WOFFSET                       0x0
+#define DVC_VSEL_MAP_LUT_22_VSEL2_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_22_VSEL2_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_22_VSEL2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_22_VSEL2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VSEL_MAP_LUT_23  
+#define DVC_VSEL_MAP_LUT_23                     _MK_ADDR_CONST(0xdc)
+#define DVC_VSEL_MAP_LUT_23_SECURE                      0x0
+#define DVC_VSEL_MAP_LUT_23_WORD_COUNT                  0x1
+#define DVC_VSEL_MAP_LUT_23_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_23_RESET_MASK                  _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_23_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_23_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_23_READ_MASK                   _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_23_WRITE_MASK                  _MK_MASK_CONST(0x3ff)
+//VSEL3 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_23_VSEL3_SHIFT                 _MK_SHIFT_CONST(5)
+#define DVC_VSEL_MAP_LUT_23_VSEL3_FIELD                 (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_23_VSEL3_SHIFT)
+#define DVC_VSEL_MAP_LUT_23_VSEL3_RANGE                 9:5
+#define DVC_VSEL_MAP_LUT_23_VSEL3_WOFFSET                       0x0
+#define DVC_VSEL_MAP_LUT_23_VSEL3_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_23_VSEL3_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_23_VSEL3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_23_VSEL3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//VSEL2 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_23_VSEL2_SHIFT                 _MK_SHIFT_CONST(0)
+#define DVC_VSEL_MAP_LUT_23_VSEL2_FIELD                 (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_23_VSEL2_SHIFT)
+#define DVC_VSEL_MAP_LUT_23_VSEL2_RANGE                 4:0
+#define DVC_VSEL_MAP_LUT_23_VSEL2_WOFFSET                       0x0
+#define DVC_VSEL_MAP_LUT_23_VSEL2_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_23_VSEL2_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_23_VSEL2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_23_VSEL2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VSEL_MAP_LUT_24  
+#define DVC_VSEL_MAP_LUT_24                     _MK_ADDR_CONST(0xe0)
+#define DVC_VSEL_MAP_LUT_24_SECURE                      0x0
+#define DVC_VSEL_MAP_LUT_24_WORD_COUNT                  0x1
+#define DVC_VSEL_MAP_LUT_24_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_24_RESET_MASK                  _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_24_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_24_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_24_READ_MASK                   _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_24_WRITE_MASK                  _MK_MASK_CONST(0x3ff)
+//VSEL3 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_24_VSEL3_SHIFT                 _MK_SHIFT_CONST(5)
+#define DVC_VSEL_MAP_LUT_24_VSEL3_FIELD                 (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_24_VSEL3_SHIFT)
+#define DVC_VSEL_MAP_LUT_24_VSEL3_RANGE                 9:5
+#define DVC_VSEL_MAP_LUT_24_VSEL3_WOFFSET                       0x0
+#define DVC_VSEL_MAP_LUT_24_VSEL3_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_24_VSEL3_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_24_VSEL3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_24_VSEL3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//VSEL2 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_24_VSEL2_SHIFT                 _MK_SHIFT_CONST(0)
+#define DVC_VSEL_MAP_LUT_24_VSEL2_FIELD                 (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_24_VSEL2_SHIFT)
+#define DVC_VSEL_MAP_LUT_24_VSEL2_RANGE                 4:0
+#define DVC_VSEL_MAP_LUT_24_VSEL2_WOFFSET                       0x0
+#define DVC_VSEL_MAP_LUT_24_VSEL2_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_24_VSEL2_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_24_VSEL2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_24_VSEL2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VSEL_MAP_LUT_25  
+#define DVC_VSEL_MAP_LUT_25                     _MK_ADDR_CONST(0xe4)
+#define DVC_VSEL_MAP_LUT_25_SECURE                      0x0
+#define DVC_VSEL_MAP_LUT_25_WORD_COUNT                  0x1
+#define DVC_VSEL_MAP_LUT_25_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_25_RESET_MASK                  _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_25_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_25_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_25_READ_MASK                   _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_25_WRITE_MASK                  _MK_MASK_CONST(0x3ff)
+//VSEL3 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_25_VSEL3_SHIFT                 _MK_SHIFT_CONST(5)
+#define DVC_VSEL_MAP_LUT_25_VSEL3_FIELD                 (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_25_VSEL3_SHIFT)
+#define DVC_VSEL_MAP_LUT_25_VSEL3_RANGE                 9:5
+#define DVC_VSEL_MAP_LUT_25_VSEL3_WOFFSET                       0x0
+#define DVC_VSEL_MAP_LUT_25_VSEL3_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_25_VSEL3_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_25_VSEL3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_25_VSEL3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//VSEL2 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_25_VSEL2_SHIFT                 _MK_SHIFT_CONST(0)
+#define DVC_VSEL_MAP_LUT_25_VSEL2_FIELD                 (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_25_VSEL2_SHIFT)
+#define DVC_VSEL_MAP_LUT_25_VSEL2_RANGE                 4:0
+#define DVC_VSEL_MAP_LUT_25_VSEL2_WOFFSET                       0x0
+#define DVC_VSEL_MAP_LUT_25_VSEL2_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_25_VSEL2_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_25_VSEL2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_25_VSEL2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VSEL_MAP_LUT_26  
+#define DVC_VSEL_MAP_LUT_26                     _MK_ADDR_CONST(0xe8)
+#define DVC_VSEL_MAP_LUT_26_SECURE                      0x0
+#define DVC_VSEL_MAP_LUT_26_WORD_COUNT                  0x1
+#define DVC_VSEL_MAP_LUT_26_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_26_RESET_MASK                  _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_26_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_26_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_26_READ_MASK                   _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_26_WRITE_MASK                  _MK_MASK_CONST(0x3ff)
+//VSEL3 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_26_VSEL3_SHIFT                 _MK_SHIFT_CONST(5)
+#define DVC_VSEL_MAP_LUT_26_VSEL3_FIELD                 (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_26_VSEL3_SHIFT)
+#define DVC_VSEL_MAP_LUT_26_VSEL3_RANGE                 9:5
+#define DVC_VSEL_MAP_LUT_26_VSEL3_WOFFSET                       0x0
+#define DVC_VSEL_MAP_LUT_26_VSEL3_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_26_VSEL3_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_26_VSEL3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_26_VSEL3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//VSEL2 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_26_VSEL2_SHIFT                 _MK_SHIFT_CONST(0)
+#define DVC_VSEL_MAP_LUT_26_VSEL2_FIELD                 (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_26_VSEL2_SHIFT)
+#define DVC_VSEL_MAP_LUT_26_VSEL2_RANGE                 4:0
+#define DVC_VSEL_MAP_LUT_26_VSEL2_WOFFSET                       0x0
+#define DVC_VSEL_MAP_LUT_26_VSEL2_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_26_VSEL2_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_26_VSEL2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_26_VSEL2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VSEL_MAP_LUT_27  
+#define DVC_VSEL_MAP_LUT_27                     _MK_ADDR_CONST(0xec)
+#define DVC_VSEL_MAP_LUT_27_SECURE                      0x0
+#define DVC_VSEL_MAP_LUT_27_WORD_COUNT                  0x1
+#define DVC_VSEL_MAP_LUT_27_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_27_RESET_MASK                  _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_27_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_27_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_27_READ_MASK                   _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_27_WRITE_MASK                  _MK_MASK_CONST(0x3ff)
+//VSEL3 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_27_VSEL3_SHIFT                 _MK_SHIFT_CONST(5)
+#define DVC_VSEL_MAP_LUT_27_VSEL3_FIELD                 (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_27_VSEL3_SHIFT)
+#define DVC_VSEL_MAP_LUT_27_VSEL3_RANGE                 9:5
+#define DVC_VSEL_MAP_LUT_27_VSEL3_WOFFSET                       0x0
+#define DVC_VSEL_MAP_LUT_27_VSEL3_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_27_VSEL3_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_27_VSEL3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_27_VSEL3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//VSEL2 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_27_VSEL2_SHIFT                 _MK_SHIFT_CONST(0)
+#define DVC_VSEL_MAP_LUT_27_VSEL2_FIELD                 (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_27_VSEL2_SHIFT)
+#define DVC_VSEL_MAP_LUT_27_VSEL2_RANGE                 4:0
+#define DVC_VSEL_MAP_LUT_27_VSEL2_WOFFSET                       0x0
+#define DVC_VSEL_MAP_LUT_27_VSEL2_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_27_VSEL2_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_27_VSEL2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_27_VSEL2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VSEL_MAP_LUT_28  
+#define DVC_VSEL_MAP_LUT_28                     _MK_ADDR_CONST(0xf0)
+#define DVC_VSEL_MAP_LUT_28_SECURE                      0x0
+#define DVC_VSEL_MAP_LUT_28_WORD_COUNT                  0x1
+#define DVC_VSEL_MAP_LUT_28_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_28_RESET_MASK                  _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_28_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_28_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_28_READ_MASK                   _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_28_WRITE_MASK                  _MK_MASK_CONST(0x3ff)
+//VSEL3 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_28_VSEL3_SHIFT                 _MK_SHIFT_CONST(5)
+#define DVC_VSEL_MAP_LUT_28_VSEL3_FIELD                 (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_28_VSEL3_SHIFT)
+#define DVC_VSEL_MAP_LUT_28_VSEL3_RANGE                 9:5
+#define DVC_VSEL_MAP_LUT_28_VSEL3_WOFFSET                       0x0
+#define DVC_VSEL_MAP_LUT_28_VSEL3_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_28_VSEL3_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_28_VSEL3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_28_VSEL3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//VSEL2 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_28_VSEL2_SHIFT                 _MK_SHIFT_CONST(0)
+#define DVC_VSEL_MAP_LUT_28_VSEL2_FIELD                 (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_28_VSEL2_SHIFT)
+#define DVC_VSEL_MAP_LUT_28_VSEL2_RANGE                 4:0
+#define DVC_VSEL_MAP_LUT_28_VSEL2_WOFFSET                       0x0
+#define DVC_VSEL_MAP_LUT_28_VSEL2_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_28_VSEL2_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_28_VSEL2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_28_VSEL2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VSEL_MAP_LUT_29  
+#define DVC_VSEL_MAP_LUT_29                     _MK_ADDR_CONST(0xf4)
+#define DVC_VSEL_MAP_LUT_29_SECURE                      0x0
+#define DVC_VSEL_MAP_LUT_29_WORD_COUNT                  0x1
+#define DVC_VSEL_MAP_LUT_29_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_29_RESET_MASK                  _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_29_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_29_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_29_READ_MASK                   _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_29_WRITE_MASK                  _MK_MASK_CONST(0x3ff)
+//VSEL3 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_29_VSEL3_SHIFT                 _MK_SHIFT_CONST(5)
+#define DVC_VSEL_MAP_LUT_29_VSEL3_FIELD                 (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_29_VSEL3_SHIFT)
+#define DVC_VSEL_MAP_LUT_29_VSEL3_RANGE                 9:5
+#define DVC_VSEL_MAP_LUT_29_VSEL3_WOFFSET                       0x0
+#define DVC_VSEL_MAP_LUT_29_VSEL3_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_29_VSEL3_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_29_VSEL3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_29_VSEL3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//VSEL2 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_29_VSEL2_SHIFT                 _MK_SHIFT_CONST(0)
+#define DVC_VSEL_MAP_LUT_29_VSEL2_FIELD                 (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_29_VSEL2_SHIFT)
+#define DVC_VSEL_MAP_LUT_29_VSEL2_RANGE                 4:0
+#define DVC_VSEL_MAP_LUT_29_VSEL2_WOFFSET                       0x0
+#define DVC_VSEL_MAP_LUT_29_VSEL2_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_29_VSEL2_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_29_VSEL2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_29_VSEL2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VSEL_MAP_LUT_30  
+#define DVC_VSEL_MAP_LUT_30                     _MK_ADDR_CONST(0xf8)
+#define DVC_VSEL_MAP_LUT_30_SECURE                      0x0
+#define DVC_VSEL_MAP_LUT_30_WORD_COUNT                  0x1
+#define DVC_VSEL_MAP_LUT_30_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_30_RESET_MASK                  _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_30_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_30_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_30_READ_MASK                   _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_30_WRITE_MASK                  _MK_MASK_CONST(0x3ff)
+//VSEL3 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_30_VSEL3_SHIFT                 _MK_SHIFT_CONST(5)
+#define DVC_VSEL_MAP_LUT_30_VSEL3_FIELD                 (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_30_VSEL3_SHIFT)
+#define DVC_VSEL_MAP_LUT_30_VSEL3_RANGE                 9:5
+#define DVC_VSEL_MAP_LUT_30_VSEL3_WOFFSET                       0x0
+#define DVC_VSEL_MAP_LUT_30_VSEL3_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_30_VSEL3_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_30_VSEL3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_30_VSEL3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//VSEL2 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_30_VSEL2_SHIFT                 _MK_SHIFT_CONST(0)
+#define DVC_VSEL_MAP_LUT_30_VSEL2_FIELD                 (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_30_VSEL2_SHIFT)
+#define DVC_VSEL_MAP_LUT_30_VSEL2_RANGE                 4:0
+#define DVC_VSEL_MAP_LUT_30_VSEL2_WOFFSET                       0x0
+#define DVC_VSEL_MAP_LUT_30_VSEL2_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_30_VSEL2_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_30_VSEL2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_30_VSEL2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VSEL_MAP_LUT_31  
+#define DVC_VSEL_MAP_LUT_31                     _MK_ADDR_CONST(0xfc)
+#define DVC_VSEL_MAP_LUT_31_SECURE                      0x0
+#define DVC_VSEL_MAP_LUT_31_WORD_COUNT                  0x1
+#define DVC_VSEL_MAP_LUT_31_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_31_RESET_MASK                  _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_31_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_31_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_31_READ_MASK                   _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_31_WRITE_MASK                  _MK_MASK_CONST(0x3ff)
+//VSEL3 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_31_VSEL3_SHIFT                 _MK_SHIFT_CONST(5)
+#define DVC_VSEL_MAP_LUT_31_VSEL3_FIELD                 (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_31_VSEL3_SHIFT)
+#define DVC_VSEL_MAP_LUT_31_VSEL3_RANGE                 9:5
+#define DVC_VSEL_MAP_LUT_31_VSEL3_WOFFSET                       0x0
+#define DVC_VSEL_MAP_LUT_31_VSEL3_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_31_VSEL3_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_31_VSEL3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_31_VSEL3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//VSEL2 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_31_VSEL2_SHIFT                 _MK_SHIFT_CONST(0)
+#define DVC_VSEL_MAP_LUT_31_VSEL2_FIELD                 (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_31_VSEL2_SHIFT)
+#define DVC_VSEL_MAP_LUT_31_VSEL2_RANGE                 4:0
+#define DVC_VSEL_MAP_LUT_31_VSEL2_WOFFSET                       0x0
+#define DVC_VSEL_MAP_LUT_31_VSEL2_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_31_VSEL2_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_31_VSEL2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_31_VSEL2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_0  
+#define DVC_VLUT_0                      _MK_ADDR_CONST(0x100)
+#define DVC_VLUT_0_SECURE                       0x0
+#define DVC_VLUT_0_WORD_COUNT                   0x1
+#define DVC_VLUT_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_0_RESET_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_0_READ_MASK                    _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_0_WRITE_MASK                   _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_0_PMCNT_SHIFT                  _MK_SHIFT_CONST(10)
+#define DVC_VLUT_0_PMCNT_FIELD                  (_MK_MASK_CONST(0x3fff) << DVC_VLUT_0_PMCNT_SHIFT)
+#define DVC_VLUT_0_PMCNT_RANGE                  23:10
+#define DVC_VLUT_0_PMCNT_WOFFSET                        0x0
+#define DVC_VLUT_0_PMCNT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_0_PMCNT_DEFAULT_MASK                   _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_0_PMCNT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_0_PMCNT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_0_VMIN_SHIFT                   _MK_SHIFT_CONST(5)
+#define DVC_VLUT_0_VMIN_FIELD                   (_MK_MASK_CONST(0x1f) << DVC_VLUT_0_VMIN_SHIFT)
+#define DVC_VLUT_0_VMIN_RANGE                   9:5
+#define DVC_VLUT_0_VMIN_WOFFSET                 0x0
+#define DVC_VLUT_0_VMIN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define DVC_VLUT_0_VMIN_DEFAULT_MASK                    _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_0_VMIN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_0_VMIN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_0_VMAX_SHIFT                   _MK_SHIFT_CONST(0)
+#define DVC_VLUT_0_VMAX_FIELD                   (_MK_MASK_CONST(0x1f) << DVC_VLUT_0_VMAX_SHIFT)
+#define DVC_VLUT_0_VMAX_RANGE                   4:0
+#define DVC_VLUT_0_VMAX_WOFFSET                 0x0
+#define DVC_VLUT_0_VMAX_DEFAULT                 _MK_MASK_CONST(0x0)
+#define DVC_VLUT_0_VMAX_DEFAULT_MASK                    _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_0_VMAX_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_0_VMAX_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT  
+#define DVC_VLUT                        _MK_ADDR_CONST(0x100)
+#define DVC_VLUT_SECURE                         0x0
+#define DVC_VLUT_WORD_COUNT                     0x1
+#define DVC_VLUT_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_RESET_MASK                     _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define DVC_VLUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_READ_MASK                      _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_WRITE_MASK                     _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_PMCNT_SHIFT                    _MK_SHIFT_CONST(10)
+#define DVC_VLUT_PMCNT_FIELD                    (_MK_MASK_CONST(0x3fff) << DVC_VLUT_PMCNT_SHIFT)
+#define DVC_VLUT_PMCNT_RANGE                    23:10
+#define DVC_VLUT_PMCNT_WOFFSET                  0x0
+#define DVC_VLUT_PMCNT_DEFAULT                  _MK_MASK_CONST(0x0)
+#define DVC_VLUT_PMCNT_DEFAULT_MASK                     _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_PMCNT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_PMCNT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_VMIN_SHIFT                     _MK_SHIFT_CONST(5)
+#define DVC_VLUT_VMIN_FIELD                     (_MK_MASK_CONST(0x1f) << DVC_VLUT_VMIN_SHIFT)
+#define DVC_VLUT_VMIN_RANGE                     9:5
+#define DVC_VLUT_VMIN_WOFFSET                   0x0
+#define DVC_VLUT_VMIN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define DVC_VLUT_VMIN_DEFAULT_MASK                      _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_VMIN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_VMIN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_VMAX_SHIFT                     _MK_SHIFT_CONST(0)
+#define DVC_VLUT_VMAX_FIELD                     (_MK_MASK_CONST(0x1f) << DVC_VLUT_VMAX_SHIFT)
+#define DVC_VLUT_VMAX_RANGE                     4:0
+#define DVC_VLUT_VMAX_WOFFSET                   0x0
+#define DVC_VLUT_VMAX_DEFAULT                   _MK_MASK_CONST(0x0)
+#define DVC_VLUT_VMAX_DEFAULT_MASK                      _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_VMAX_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_VMAX_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_1  
+#define DVC_VLUT_1                      _MK_ADDR_CONST(0x104)
+#define DVC_VLUT_1_SECURE                       0x0
+#define DVC_VLUT_1_WORD_COUNT                   0x1
+#define DVC_VLUT_1_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_1_RESET_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_1_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_1_READ_MASK                    _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_1_WRITE_MASK                   _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_1_PMCNT_SHIFT                  _MK_SHIFT_CONST(10)
+#define DVC_VLUT_1_PMCNT_FIELD                  (_MK_MASK_CONST(0x3fff) << DVC_VLUT_1_PMCNT_SHIFT)
+#define DVC_VLUT_1_PMCNT_RANGE                  23:10
+#define DVC_VLUT_1_PMCNT_WOFFSET                        0x0
+#define DVC_VLUT_1_PMCNT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_1_PMCNT_DEFAULT_MASK                   _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_1_PMCNT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_1_PMCNT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_1_VMIN_SHIFT                   _MK_SHIFT_CONST(5)
+#define DVC_VLUT_1_VMIN_FIELD                   (_MK_MASK_CONST(0x1f) << DVC_VLUT_1_VMIN_SHIFT)
+#define DVC_VLUT_1_VMIN_RANGE                   9:5
+#define DVC_VLUT_1_VMIN_WOFFSET                 0x0
+#define DVC_VLUT_1_VMIN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define DVC_VLUT_1_VMIN_DEFAULT_MASK                    _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_1_VMIN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_1_VMIN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_1_VMAX_SHIFT                   _MK_SHIFT_CONST(0)
+#define DVC_VLUT_1_VMAX_FIELD                   (_MK_MASK_CONST(0x1f) << DVC_VLUT_1_VMAX_SHIFT)
+#define DVC_VLUT_1_VMAX_RANGE                   4:0
+#define DVC_VLUT_1_VMAX_WOFFSET                 0x0
+#define DVC_VLUT_1_VMAX_DEFAULT                 _MK_MASK_CONST(0x0)
+#define DVC_VLUT_1_VMAX_DEFAULT_MASK                    _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_1_VMAX_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_1_VMAX_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_2  
+#define DVC_VLUT_2                      _MK_ADDR_CONST(0x108)
+#define DVC_VLUT_2_SECURE                       0x0
+#define DVC_VLUT_2_WORD_COUNT                   0x1
+#define DVC_VLUT_2_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_2_RESET_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_2_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_2_READ_MASK                    _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_2_WRITE_MASK                   _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_2_PMCNT_SHIFT                  _MK_SHIFT_CONST(10)
+#define DVC_VLUT_2_PMCNT_FIELD                  (_MK_MASK_CONST(0x3fff) << DVC_VLUT_2_PMCNT_SHIFT)
+#define DVC_VLUT_2_PMCNT_RANGE                  23:10
+#define DVC_VLUT_2_PMCNT_WOFFSET                        0x0
+#define DVC_VLUT_2_PMCNT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_2_PMCNT_DEFAULT_MASK                   _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_2_PMCNT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_2_PMCNT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_2_VMIN_SHIFT                   _MK_SHIFT_CONST(5)
+#define DVC_VLUT_2_VMIN_FIELD                   (_MK_MASK_CONST(0x1f) << DVC_VLUT_2_VMIN_SHIFT)
+#define DVC_VLUT_2_VMIN_RANGE                   9:5
+#define DVC_VLUT_2_VMIN_WOFFSET                 0x0
+#define DVC_VLUT_2_VMIN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define DVC_VLUT_2_VMIN_DEFAULT_MASK                    _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_2_VMIN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_2_VMIN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_2_VMAX_SHIFT                   _MK_SHIFT_CONST(0)
+#define DVC_VLUT_2_VMAX_FIELD                   (_MK_MASK_CONST(0x1f) << DVC_VLUT_2_VMAX_SHIFT)
+#define DVC_VLUT_2_VMAX_RANGE                   4:0
+#define DVC_VLUT_2_VMAX_WOFFSET                 0x0
+#define DVC_VLUT_2_VMAX_DEFAULT                 _MK_MASK_CONST(0x0)
+#define DVC_VLUT_2_VMAX_DEFAULT_MASK                    _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_2_VMAX_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_2_VMAX_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_3  
+#define DVC_VLUT_3                      _MK_ADDR_CONST(0x10c)
+#define DVC_VLUT_3_SECURE                       0x0
+#define DVC_VLUT_3_WORD_COUNT                   0x1
+#define DVC_VLUT_3_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_3_RESET_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_3_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_3_READ_MASK                    _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_3_WRITE_MASK                   _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_3_PMCNT_SHIFT                  _MK_SHIFT_CONST(10)
+#define DVC_VLUT_3_PMCNT_FIELD                  (_MK_MASK_CONST(0x3fff) << DVC_VLUT_3_PMCNT_SHIFT)
+#define DVC_VLUT_3_PMCNT_RANGE                  23:10
+#define DVC_VLUT_3_PMCNT_WOFFSET                        0x0
+#define DVC_VLUT_3_PMCNT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_3_PMCNT_DEFAULT_MASK                   _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_3_PMCNT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_3_PMCNT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_3_VMIN_SHIFT                   _MK_SHIFT_CONST(5)
+#define DVC_VLUT_3_VMIN_FIELD                   (_MK_MASK_CONST(0x1f) << DVC_VLUT_3_VMIN_SHIFT)
+#define DVC_VLUT_3_VMIN_RANGE                   9:5
+#define DVC_VLUT_3_VMIN_WOFFSET                 0x0
+#define DVC_VLUT_3_VMIN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define DVC_VLUT_3_VMIN_DEFAULT_MASK                    _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_3_VMIN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_3_VMIN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_3_VMAX_SHIFT                   _MK_SHIFT_CONST(0)
+#define DVC_VLUT_3_VMAX_FIELD                   (_MK_MASK_CONST(0x1f) << DVC_VLUT_3_VMAX_SHIFT)
+#define DVC_VLUT_3_VMAX_RANGE                   4:0
+#define DVC_VLUT_3_VMAX_WOFFSET                 0x0
+#define DVC_VLUT_3_VMAX_DEFAULT                 _MK_MASK_CONST(0x0)
+#define DVC_VLUT_3_VMAX_DEFAULT_MASK                    _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_3_VMAX_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_3_VMAX_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_4  
+#define DVC_VLUT_4                      _MK_ADDR_CONST(0x110)
+#define DVC_VLUT_4_SECURE                       0x0
+#define DVC_VLUT_4_WORD_COUNT                   0x1
+#define DVC_VLUT_4_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_4_RESET_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_4_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_4_READ_MASK                    _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_4_WRITE_MASK                   _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_4_PMCNT_SHIFT                  _MK_SHIFT_CONST(10)
+#define DVC_VLUT_4_PMCNT_FIELD                  (_MK_MASK_CONST(0x3fff) << DVC_VLUT_4_PMCNT_SHIFT)
+#define DVC_VLUT_4_PMCNT_RANGE                  23:10
+#define DVC_VLUT_4_PMCNT_WOFFSET                        0x0
+#define DVC_VLUT_4_PMCNT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_4_PMCNT_DEFAULT_MASK                   _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_4_PMCNT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_4_PMCNT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_4_VMIN_SHIFT                   _MK_SHIFT_CONST(5)
+#define DVC_VLUT_4_VMIN_FIELD                   (_MK_MASK_CONST(0x1f) << DVC_VLUT_4_VMIN_SHIFT)
+#define DVC_VLUT_4_VMIN_RANGE                   9:5
+#define DVC_VLUT_4_VMIN_WOFFSET                 0x0
+#define DVC_VLUT_4_VMIN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define DVC_VLUT_4_VMIN_DEFAULT_MASK                    _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_4_VMIN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_4_VMIN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_4_VMAX_SHIFT                   _MK_SHIFT_CONST(0)
+#define DVC_VLUT_4_VMAX_FIELD                   (_MK_MASK_CONST(0x1f) << DVC_VLUT_4_VMAX_SHIFT)
+#define DVC_VLUT_4_VMAX_RANGE                   4:0
+#define DVC_VLUT_4_VMAX_WOFFSET                 0x0
+#define DVC_VLUT_4_VMAX_DEFAULT                 _MK_MASK_CONST(0x0)
+#define DVC_VLUT_4_VMAX_DEFAULT_MASK                    _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_4_VMAX_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_4_VMAX_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_5  
+#define DVC_VLUT_5                      _MK_ADDR_CONST(0x114)
+#define DVC_VLUT_5_SECURE                       0x0
+#define DVC_VLUT_5_WORD_COUNT                   0x1
+#define DVC_VLUT_5_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_5_RESET_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_5_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_5_READ_MASK                    _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_5_WRITE_MASK                   _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_5_PMCNT_SHIFT                  _MK_SHIFT_CONST(10)
+#define DVC_VLUT_5_PMCNT_FIELD                  (_MK_MASK_CONST(0x3fff) << DVC_VLUT_5_PMCNT_SHIFT)
+#define DVC_VLUT_5_PMCNT_RANGE                  23:10
+#define DVC_VLUT_5_PMCNT_WOFFSET                        0x0
+#define DVC_VLUT_5_PMCNT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_5_PMCNT_DEFAULT_MASK                   _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_5_PMCNT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_5_PMCNT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_5_VMIN_SHIFT                   _MK_SHIFT_CONST(5)
+#define DVC_VLUT_5_VMIN_FIELD                   (_MK_MASK_CONST(0x1f) << DVC_VLUT_5_VMIN_SHIFT)
+#define DVC_VLUT_5_VMIN_RANGE                   9:5
+#define DVC_VLUT_5_VMIN_WOFFSET                 0x0
+#define DVC_VLUT_5_VMIN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define DVC_VLUT_5_VMIN_DEFAULT_MASK                    _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_5_VMIN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_5_VMIN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_5_VMAX_SHIFT                   _MK_SHIFT_CONST(0)
+#define DVC_VLUT_5_VMAX_FIELD                   (_MK_MASK_CONST(0x1f) << DVC_VLUT_5_VMAX_SHIFT)
+#define DVC_VLUT_5_VMAX_RANGE                   4:0
+#define DVC_VLUT_5_VMAX_WOFFSET                 0x0
+#define DVC_VLUT_5_VMAX_DEFAULT                 _MK_MASK_CONST(0x0)
+#define DVC_VLUT_5_VMAX_DEFAULT_MASK                    _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_5_VMAX_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_5_VMAX_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_6  
+#define DVC_VLUT_6                      _MK_ADDR_CONST(0x118)
+#define DVC_VLUT_6_SECURE                       0x0
+#define DVC_VLUT_6_WORD_COUNT                   0x1
+#define DVC_VLUT_6_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_6_RESET_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_6_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_6_READ_MASK                    _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_6_WRITE_MASK                   _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_6_PMCNT_SHIFT                  _MK_SHIFT_CONST(10)
+#define DVC_VLUT_6_PMCNT_FIELD                  (_MK_MASK_CONST(0x3fff) << DVC_VLUT_6_PMCNT_SHIFT)
+#define DVC_VLUT_6_PMCNT_RANGE                  23:10
+#define DVC_VLUT_6_PMCNT_WOFFSET                        0x0
+#define DVC_VLUT_6_PMCNT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_6_PMCNT_DEFAULT_MASK                   _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_6_PMCNT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_6_PMCNT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_6_VMIN_SHIFT                   _MK_SHIFT_CONST(5)
+#define DVC_VLUT_6_VMIN_FIELD                   (_MK_MASK_CONST(0x1f) << DVC_VLUT_6_VMIN_SHIFT)
+#define DVC_VLUT_6_VMIN_RANGE                   9:5
+#define DVC_VLUT_6_VMIN_WOFFSET                 0x0
+#define DVC_VLUT_6_VMIN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define DVC_VLUT_6_VMIN_DEFAULT_MASK                    _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_6_VMIN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_6_VMIN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_6_VMAX_SHIFT                   _MK_SHIFT_CONST(0)
+#define DVC_VLUT_6_VMAX_FIELD                   (_MK_MASK_CONST(0x1f) << DVC_VLUT_6_VMAX_SHIFT)
+#define DVC_VLUT_6_VMAX_RANGE                   4:0
+#define DVC_VLUT_6_VMAX_WOFFSET                 0x0
+#define DVC_VLUT_6_VMAX_DEFAULT                 _MK_MASK_CONST(0x0)
+#define DVC_VLUT_6_VMAX_DEFAULT_MASK                    _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_6_VMAX_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_6_VMAX_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_7  
+#define DVC_VLUT_7                      _MK_ADDR_CONST(0x11c)
+#define DVC_VLUT_7_SECURE                       0x0
+#define DVC_VLUT_7_WORD_COUNT                   0x1
+#define DVC_VLUT_7_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_7_RESET_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_7_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_7_READ_MASK                    _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_7_WRITE_MASK                   _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_7_PMCNT_SHIFT                  _MK_SHIFT_CONST(10)
+#define DVC_VLUT_7_PMCNT_FIELD                  (_MK_MASK_CONST(0x3fff) << DVC_VLUT_7_PMCNT_SHIFT)
+#define DVC_VLUT_7_PMCNT_RANGE                  23:10
+#define DVC_VLUT_7_PMCNT_WOFFSET                        0x0
+#define DVC_VLUT_7_PMCNT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_7_PMCNT_DEFAULT_MASK                   _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_7_PMCNT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_7_PMCNT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_7_VMIN_SHIFT                   _MK_SHIFT_CONST(5)
+#define DVC_VLUT_7_VMIN_FIELD                   (_MK_MASK_CONST(0x1f) << DVC_VLUT_7_VMIN_SHIFT)
+#define DVC_VLUT_7_VMIN_RANGE                   9:5
+#define DVC_VLUT_7_VMIN_WOFFSET                 0x0
+#define DVC_VLUT_7_VMIN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define DVC_VLUT_7_VMIN_DEFAULT_MASK                    _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_7_VMIN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_7_VMIN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_7_VMAX_SHIFT                   _MK_SHIFT_CONST(0)
+#define DVC_VLUT_7_VMAX_FIELD                   (_MK_MASK_CONST(0x1f) << DVC_VLUT_7_VMAX_SHIFT)
+#define DVC_VLUT_7_VMAX_RANGE                   4:0
+#define DVC_VLUT_7_VMAX_WOFFSET                 0x0
+#define DVC_VLUT_7_VMAX_DEFAULT                 _MK_MASK_CONST(0x0)
+#define DVC_VLUT_7_VMAX_DEFAULT_MASK                    _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_7_VMAX_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_7_VMAX_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_8  
+#define DVC_VLUT_8                      _MK_ADDR_CONST(0x120)
+#define DVC_VLUT_8_SECURE                       0x0
+#define DVC_VLUT_8_WORD_COUNT                   0x1
+#define DVC_VLUT_8_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_8_RESET_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_8_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_8_READ_MASK                    _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_8_WRITE_MASK                   _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_8_PMCNT_SHIFT                  _MK_SHIFT_CONST(10)
+#define DVC_VLUT_8_PMCNT_FIELD                  (_MK_MASK_CONST(0x3fff) << DVC_VLUT_8_PMCNT_SHIFT)
+#define DVC_VLUT_8_PMCNT_RANGE                  23:10
+#define DVC_VLUT_8_PMCNT_WOFFSET                        0x0
+#define DVC_VLUT_8_PMCNT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_8_PMCNT_DEFAULT_MASK                   _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_8_PMCNT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_8_PMCNT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_8_VMIN_SHIFT                   _MK_SHIFT_CONST(5)
+#define DVC_VLUT_8_VMIN_FIELD                   (_MK_MASK_CONST(0x1f) << DVC_VLUT_8_VMIN_SHIFT)
+#define DVC_VLUT_8_VMIN_RANGE                   9:5
+#define DVC_VLUT_8_VMIN_WOFFSET                 0x0
+#define DVC_VLUT_8_VMIN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define DVC_VLUT_8_VMIN_DEFAULT_MASK                    _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_8_VMIN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_8_VMIN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_8_VMAX_SHIFT                   _MK_SHIFT_CONST(0)
+#define DVC_VLUT_8_VMAX_FIELD                   (_MK_MASK_CONST(0x1f) << DVC_VLUT_8_VMAX_SHIFT)
+#define DVC_VLUT_8_VMAX_RANGE                   4:0
+#define DVC_VLUT_8_VMAX_WOFFSET                 0x0
+#define DVC_VLUT_8_VMAX_DEFAULT                 _MK_MASK_CONST(0x0)
+#define DVC_VLUT_8_VMAX_DEFAULT_MASK                    _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_8_VMAX_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_8_VMAX_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_9  
+#define DVC_VLUT_9                      _MK_ADDR_CONST(0x124)
+#define DVC_VLUT_9_SECURE                       0x0
+#define DVC_VLUT_9_WORD_COUNT                   0x1
+#define DVC_VLUT_9_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_9_RESET_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_9_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_9_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_9_READ_MASK                    _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_9_WRITE_MASK                   _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_9_PMCNT_SHIFT                  _MK_SHIFT_CONST(10)
+#define DVC_VLUT_9_PMCNT_FIELD                  (_MK_MASK_CONST(0x3fff) << DVC_VLUT_9_PMCNT_SHIFT)
+#define DVC_VLUT_9_PMCNT_RANGE                  23:10
+#define DVC_VLUT_9_PMCNT_WOFFSET                        0x0
+#define DVC_VLUT_9_PMCNT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_9_PMCNT_DEFAULT_MASK                   _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_9_PMCNT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_9_PMCNT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_9_VMIN_SHIFT                   _MK_SHIFT_CONST(5)
+#define DVC_VLUT_9_VMIN_FIELD                   (_MK_MASK_CONST(0x1f) << DVC_VLUT_9_VMIN_SHIFT)
+#define DVC_VLUT_9_VMIN_RANGE                   9:5
+#define DVC_VLUT_9_VMIN_WOFFSET                 0x0
+#define DVC_VLUT_9_VMIN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define DVC_VLUT_9_VMIN_DEFAULT_MASK                    _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_9_VMIN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_9_VMIN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_9_VMAX_SHIFT                   _MK_SHIFT_CONST(0)
+#define DVC_VLUT_9_VMAX_FIELD                   (_MK_MASK_CONST(0x1f) << DVC_VLUT_9_VMAX_SHIFT)
+#define DVC_VLUT_9_VMAX_RANGE                   4:0
+#define DVC_VLUT_9_VMAX_WOFFSET                 0x0
+#define DVC_VLUT_9_VMAX_DEFAULT                 _MK_MASK_CONST(0x0)
+#define DVC_VLUT_9_VMAX_DEFAULT_MASK                    _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_9_VMAX_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_9_VMAX_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_10  
+#define DVC_VLUT_10                     _MK_ADDR_CONST(0x128)
+#define DVC_VLUT_10_SECURE                      0x0
+#define DVC_VLUT_10_WORD_COUNT                  0x1
+#define DVC_VLUT_10_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VLUT_10_RESET_MASK                  _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_10_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_10_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_10_READ_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_10_WRITE_MASK                  _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_10_PMCNT_SHIFT                 _MK_SHIFT_CONST(10)
+#define DVC_VLUT_10_PMCNT_FIELD                 (_MK_MASK_CONST(0x3fff) << DVC_VLUT_10_PMCNT_SHIFT)
+#define DVC_VLUT_10_PMCNT_RANGE                 23:10
+#define DVC_VLUT_10_PMCNT_WOFFSET                       0x0
+#define DVC_VLUT_10_PMCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_10_PMCNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_10_PMCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_10_PMCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_10_VMIN_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VLUT_10_VMIN_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_10_VMIN_SHIFT)
+#define DVC_VLUT_10_VMIN_RANGE                  9:5
+#define DVC_VLUT_10_VMIN_WOFFSET                        0x0
+#define DVC_VLUT_10_VMIN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_10_VMIN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_10_VMIN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_10_VMIN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_10_VMAX_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VLUT_10_VMAX_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_10_VMAX_SHIFT)
+#define DVC_VLUT_10_VMAX_RANGE                  4:0
+#define DVC_VLUT_10_VMAX_WOFFSET                        0x0
+#define DVC_VLUT_10_VMAX_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_10_VMAX_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_10_VMAX_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_10_VMAX_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_11  
+#define DVC_VLUT_11                     _MK_ADDR_CONST(0x12c)
+#define DVC_VLUT_11_SECURE                      0x0
+#define DVC_VLUT_11_WORD_COUNT                  0x1
+#define DVC_VLUT_11_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VLUT_11_RESET_MASK                  _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_11_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_11_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_11_READ_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_11_WRITE_MASK                  _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_11_PMCNT_SHIFT                 _MK_SHIFT_CONST(10)
+#define DVC_VLUT_11_PMCNT_FIELD                 (_MK_MASK_CONST(0x3fff) << DVC_VLUT_11_PMCNT_SHIFT)
+#define DVC_VLUT_11_PMCNT_RANGE                 23:10
+#define DVC_VLUT_11_PMCNT_WOFFSET                       0x0
+#define DVC_VLUT_11_PMCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_11_PMCNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_11_PMCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_11_PMCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_11_VMIN_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VLUT_11_VMIN_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_11_VMIN_SHIFT)
+#define DVC_VLUT_11_VMIN_RANGE                  9:5
+#define DVC_VLUT_11_VMIN_WOFFSET                        0x0
+#define DVC_VLUT_11_VMIN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_11_VMIN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_11_VMIN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_11_VMIN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_11_VMAX_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VLUT_11_VMAX_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_11_VMAX_SHIFT)
+#define DVC_VLUT_11_VMAX_RANGE                  4:0
+#define DVC_VLUT_11_VMAX_WOFFSET                        0x0
+#define DVC_VLUT_11_VMAX_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_11_VMAX_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_11_VMAX_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_11_VMAX_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_12  
+#define DVC_VLUT_12                     _MK_ADDR_CONST(0x130)
+#define DVC_VLUT_12_SECURE                      0x0
+#define DVC_VLUT_12_WORD_COUNT                  0x1
+#define DVC_VLUT_12_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VLUT_12_RESET_MASK                  _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_12_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_12_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_12_READ_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_12_WRITE_MASK                  _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_12_PMCNT_SHIFT                 _MK_SHIFT_CONST(10)
+#define DVC_VLUT_12_PMCNT_FIELD                 (_MK_MASK_CONST(0x3fff) << DVC_VLUT_12_PMCNT_SHIFT)
+#define DVC_VLUT_12_PMCNT_RANGE                 23:10
+#define DVC_VLUT_12_PMCNT_WOFFSET                       0x0
+#define DVC_VLUT_12_PMCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_12_PMCNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_12_PMCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_12_PMCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_12_VMIN_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VLUT_12_VMIN_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_12_VMIN_SHIFT)
+#define DVC_VLUT_12_VMIN_RANGE                  9:5
+#define DVC_VLUT_12_VMIN_WOFFSET                        0x0
+#define DVC_VLUT_12_VMIN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_12_VMIN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_12_VMIN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_12_VMIN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_12_VMAX_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VLUT_12_VMAX_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_12_VMAX_SHIFT)
+#define DVC_VLUT_12_VMAX_RANGE                  4:0
+#define DVC_VLUT_12_VMAX_WOFFSET                        0x0
+#define DVC_VLUT_12_VMAX_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_12_VMAX_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_12_VMAX_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_12_VMAX_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_13  
+#define DVC_VLUT_13                     _MK_ADDR_CONST(0x134)
+#define DVC_VLUT_13_SECURE                      0x0
+#define DVC_VLUT_13_WORD_COUNT                  0x1
+#define DVC_VLUT_13_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VLUT_13_RESET_MASK                  _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_13_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_13_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_13_READ_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_13_WRITE_MASK                  _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_13_PMCNT_SHIFT                 _MK_SHIFT_CONST(10)
+#define DVC_VLUT_13_PMCNT_FIELD                 (_MK_MASK_CONST(0x3fff) << DVC_VLUT_13_PMCNT_SHIFT)
+#define DVC_VLUT_13_PMCNT_RANGE                 23:10
+#define DVC_VLUT_13_PMCNT_WOFFSET                       0x0
+#define DVC_VLUT_13_PMCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_13_PMCNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_13_PMCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_13_PMCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_13_VMIN_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VLUT_13_VMIN_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_13_VMIN_SHIFT)
+#define DVC_VLUT_13_VMIN_RANGE                  9:5
+#define DVC_VLUT_13_VMIN_WOFFSET                        0x0
+#define DVC_VLUT_13_VMIN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_13_VMIN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_13_VMIN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_13_VMIN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_13_VMAX_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VLUT_13_VMAX_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_13_VMAX_SHIFT)
+#define DVC_VLUT_13_VMAX_RANGE                  4:0
+#define DVC_VLUT_13_VMAX_WOFFSET                        0x0
+#define DVC_VLUT_13_VMAX_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_13_VMAX_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_13_VMAX_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_13_VMAX_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_14  
+#define DVC_VLUT_14                     _MK_ADDR_CONST(0x138)
+#define DVC_VLUT_14_SECURE                      0x0
+#define DVC_VLUT_14_WORD_COUNT                  0x1
+#define DVC_VLUT_14_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VLUT_14_RESET_MASK                  _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_14_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_14_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_14_READ_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_14_WRITE_MASK                  _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_14_PMCNT_SHIFT                 _MK_SHIFT_CONST(10)
+#define DVC_VLUT_14_PMCNT_FIELD                 (_MK_MASK_CONST(0x3fff) << DVC_VLUT_14_PMCNT_SHIFT)
+#define DVC_VLUT_14_PMCNT_RANGE                 23:10
+#define DVC_VLUT_14_PMCNT_WOFFSET                       0x0
+#define DVC_VLUT_14_PMCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_14_PMCNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_14_PMCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_14_PMCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_14_VMIN_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VLUT_14_VMIN_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_14_VMIN_SHIFT)
+#define DVC_VLUT_14_VMIN_RANGE                  9:5
+#define DVC_VLUT_14_VMIN_WOFFSET                        0x0
+#define DVC_VLUT_14_VMIN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_14_VMIN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_14_VMIN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_14_VMIN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_14_VMAX_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VLUT_14_VMAX_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_14_VMAX_SHIFT)
+#define DVC_VLUT_14_VMAX_RANGE                  4:0
+#define DVC_VLUT_14_VMAX_WOFFSET                        0x0
+#define DVC_VLUT_14_VMAX_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_14_VMAX_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_14_VMAX_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_14_VMAX_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_15  
+#define DVC_VLUT_15                     _MK_ADDR_CONST(0x13c)
+#define DVC_VLUT_15_SECURE                      0x0
+#define DVC_VLUT_15_WORD_COUNT                  0x1
+#define DVC_VLUT_15_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VLUT_15_RESET_MASK                  _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_15_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_15_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_15_READ_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_15_WRITE_MASK                  _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_15_PMCNT_SHIFT                 _MK_SHIFT_CONST(10)
+#define DVC_VLUT_15_PMCNT_FIELD                 (_MK_MASK_CONST(0x3fff) << DVC_VLUT_15_PMCNT_SHIFT)
+#define DVC_VLUT_15_PMCNT_RANGE                 23:10
+#define DVC_VLUT_15_PMCNT_WOFFSET                       0x0
+#define DVC_VLUT_15_PMCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_15_PMCNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_15_PMCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_15_PMCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_15_VMIN_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VLUT_15_VMIN_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_15_VMIN_SHIFT)
+#define DVC_VLUT_15_VMIN_RANGE                  9:5
+#define DVC_VLUT_15_VMIN_WOFFSET                        0x0
+#define DVC_VLUT_15_VMIN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_15_VMIN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_15_VMIN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_15_VMIN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_15_VMAX_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VLUT_15_VMAX_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_15_VMAX_SHIFT)
+#define DVC_VLUT_15_VMAX_RANGE                  4:0
+#define DVC_VLUT_15_VMAX_WOFFSET                        0x0
+#define DVC_VLUT_15_VMAX_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_15_VMAX_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_15_VMAX_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_15_VMAX_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_16  
+#define DVC_VLUT_16                     _MK_ADDR_CONST(0x140)
+#define DVC_VLUT_16_SECURE                      0x0
+#define DVC_VLUT_16_WORD_COUNT                  0x1
+#define DVC_VLUT_16_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VLUT_16_RESET_MASK                  _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_16_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_16_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_16_READ_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_16_WRITE_MASK                  _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_16_PMCNT_SHIFT                 _MK_SHIFT_CONST(10)
+#define DVC_VLUT_16_PMCNT_FIELD                 (_MK_MASK_CONST(0x3fff) << DVC_VLUT_16_PMCNT_SHIFT)
+#define DVC_VLUT_16_PMCNT_RANGE                 23:10
+#define DVC_VLUT_16_PMCNT_WOFFSET                       0x0
+#define DVC_VLUT_16_PMCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_16_PMCNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_16_PMCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_16_PMCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_16_VMIN_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VLUT_16_VMIN_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_16_VMIN_SHIFT)
+#define DVC_VLUT_16_VMIN_RANGE                  9:5
+#define DVC_VLUT_16_VMIN_WOFFSET                        0x0
+#define DVC_VLUT_16_VMIN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_16_VMIN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_16_VMIN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_16_VMIN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_16_VMAX_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VLUT_16_VMAX_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_16_VMAX_SHIFT)
+#define DVC_VLUT_16_VMAX_RANGE                  4:0
+#define DVC_VLUT_16_VMAX_WOFFSET                        0x0
+#define DVC_VLUT_16_VMAX_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_16_VMAX_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_16_VMAX_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_16_VMAX_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_17  
+#define DVC_VLUT_17                     _MK_ADDR_CONST(0x144)
+#define DVC_VLUT_17_SECURE                      0x0
+#define DVC_VLUT_17_WORD_COUNT                  0x1
+#define DVC_VLUT_17_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VLUT_17_RESET_MASK                  _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_17_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_17_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_17_READ_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_17_WRITE_MASK                  _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_17_PMCNT_SHIFT                 _MK_SHIFT_CONST(10)
+#define DVC_VLUT_17_PMCNT_FIELD                 (_MK_MASK_CONST(0x3fff) << DVC_VLUT_17_PMCNT_SHIFT)
+#define DVC_VLUT_17_PMCNT_RANGE                 23:10
+#define DVC_VLUT_17_PMCNT_WOFFSET                       0x0
+#define DVC_VLUT_17_PMCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_17_PMCNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_17_PMCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_17_PMCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_17_VMIN_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VLUT_17_VMIN_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_17_VMIN_SHIFT)
+#define DVC_VLUT_17_VMIN_RANGE                  9:5
+#define DVC_VLUT_17_VMIN_WOFFSET                        0x0
+#define DVC_VLUT_17_VMIN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_17_VMIN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_17_VMIN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_17_VMIN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_17_VMAX_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VLUT_17_VMAX_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_17_VMAX_SHIFT)
+#define DVC_VLUT_17_VMAX_RANGE                  4:0
+#define DVC_VLUT_17_VMAX_WOFFSET                        0x0
+#define DVC_VLUT_17_VMAX_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_17_VMAX_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_17_VMAX_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_17_VMAX_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_18  
+#define DVC_VLUT_18                     _MK_ADDR_CONST(0x148)
+#define DVC_VLUT_18_SECURE                      0x0
+#define DVC_VLUT_18_WORD_COUNT                  0x1
+#define DVC_VLUT_18_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VLUT_18_RESET_MASK                  _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_18_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_18_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_18_READ_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_18_WRITE_MASK                  _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_18_PMCNT_SHIFT                 _MK_SHIFT_CONST(10)
+#define DVC_VLUT_18_PMCNT_FIELD                 (_MK_MASK_CONST(0x3fff) << DVC_VLUT_18_PMCNT_SHIFT)
+#define DVC_VLUT_18_PMCNT_RANGE                 23:10
+#define DVC_VLUT_18_PMCNT_WOFFSET                       0x0
+#define DVC_VLUT_18_PMCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_18_PMCNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_18_PMCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_18_PMCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_18_VMIN_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VLUT_18_VMIN_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_18_VMIN_SHIFT)
+#define DVC_VLUT_18_VMIN_RANGE                  9:5
+#define DVC_VLUT_18_VMIN_WOFFSET                        0x0
+#define DVC_VLUT_18_VMIN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_18_VMIN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_18_VMIN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_18_VMIN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_18_VMAX_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VLUT_18_VMAX_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_18_VMAX_SHIFT)
+#define DVC_VLUT_18_VMAX_RANGE                  4:0
+#define DVC_VLUT_18_VMAX_WOFFSET                        0x0
+#define DVC_VLUT_18_VMAX_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_18_VMAX_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_18_VMAX_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_18_VMAX_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_19  
+#define DVC_VLUT_19                     _MK_ADDR_CONST(0x14c)
+#define DVC_VLUT_19_SECURE                      0x0
+#define DVC_VLUT_19_WORD_COUNT                  0x1
+#define DVC_VLUT_19_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VLUT_19_RESET_MASK                  _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_19_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_19_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_19_READ_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_19_WRITE_MASK                  _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_19_PMCNT_SHIFT                 _MK_SHIFT_CONST(10)
+#define DVC_VLUT_19_PMCNT_FIELD                 (_MK_MASK_CONST(0x3fff) << DVC_VLUT_19_PMCNT_SHIFT)
+#define DVC_VLUT_19_PMCNT_RANGE                 23:10
+#define DVC_VLUT_19_PMCNT_WOFFSET                       0x0
+#define DVC_VLUT_19_PMCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_19_PMCNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_19_PMCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_19_PMCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_19_VMIN_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VLUT_19_VMIN_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_19_VMIN_SHIFT)
+#define DVC_VLUT_19_VMIN_RANGE                  9:5
+#define DVC_VLUT_19_VMIN_WOFFSET                        0x0
+#define DVC_VLUT_19_VMIN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_19_VMIN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_19_VMIN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_19_VMIN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_19_VMAX_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VLUT_19_VMAX_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_19_VMAX_SHIFT)
+#define DVC_VLUT_19_VMAX_RANGE                  4:0
+#define DVC_VLUT_19_VMAX_WOFFSET                        0x0
+#define DVC_VLUT_19_VMAX_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_19_VMAX_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_19_VMAX_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_19_VMAX_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_20  
+#define DVC_VLUT_20                     _MK_ADDR_CONST(0x150)
+#define DVC_VLUT_20_SECURE                      0x0
+#define DVC_VLUT_20_WORD_COUNT                  0x1
+#define DVC_VLUT_20_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VLUT_20_RESET_MASK                  _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_20_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_20_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_20_READ_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_20_WRITE_MASK                  _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_20_PMCNT_SHIFT                 _MK_SHIFT_CONST(10)
+#define DVC_VLUT_20_PMCNT_FIELD                 (_MK_MASK_CONST(0x3fff) << DVC_VLUT_20_PMCNT_SHIFT)
+#define DVC_VLUT_20_PMCNT_RANGE                 23:10
+#define DVC_VLUT_20_PMCNT_WOFFSET                       0x0
+#define DVC_VLUT_20_PMCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_20_PMCNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_20_PMCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_20_PMCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_20_VMIN_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VLUT_20_VMIN_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_20_VMIN_SHIFT)
+#define DVC_VLUT_20_VMIN_RANGE                  9:5
+#define DVC_VLUT_20_VMIN_WOFFSET                        0x0
+#define DVC_VLUT_20_VMIN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_20_VMIN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_20_VMIN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_20_VMIN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_20_VMAX_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VLUT_20_VMAX_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_20_VMAX_SHIFT)
+#define DVC_VLUT_20_VMAX_RANGE                  4:0
+#define DVC_VLUT_20_VMAX_WOFFSET                        0x0
+#define DVC_VLUT_20_VMAX_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_20_VMAX_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_20_VMAX_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_20_VMAX_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_21  
+#define DVC_VLUT_21                     _MK_ADDR_CONST(0x154)
+#define DVC_VLUT_21_SECURE                      0x0
+#define DVC_VLUT_21_WORD_COUNT                  0x1
+#define DVC_VLUT_21_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VLUT_21_RESET_MASK                  _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_21_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_21_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_21_READ_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_21_WRITE_MASK                  _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_21_PMCNT_SHIFT                 _MK_SHIFT_CONST(10)
+#define DVC_VLUT_21_PMCNT_FIELD                 (_MK_MASK_CONST(0x3fff) << DVC_VLUT_21_PMCNT_SHIFT)
+#define DVC_VLUT_21_PMCNT_RANGE                 23:10
+#define DVC_VLUT_21_PMCNT_WOFFSET                       0x0
+#define DVC_VLUT_21_PMCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_21_PMCNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_21_PMCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_21_PMCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_21_VMIN_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VLUT_21_VMIN_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_21_VMIN_SHIFT)
+#define DVC_VLUT_21_VMIN_RANGE                  9:5
+#define DVC_VLUT_21_VMIN_WOFFSET                        0x0
+#define DVC_VLUT_21_VMIN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_21_VMIN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_21_VMIN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_21_VMIN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_21_VMAX_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VLUT_21_VMAX_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_21_VMAX_SHIFT)
+#define DVC_VLUT_21_VMAX_RANGE                  4:0
+#define DVC_VLUT_21_VMAX_WOFFSET                        0x0
+#define DVC_VLUT_21_VMAX_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_21_VMAX_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_21_VMAX_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_21_VMAX_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_22  
+#define DVC_VLUT_22                     _MK_ADDR_CONST(0x158)
+#define DVC_VLUT_22_SECURE                      0x0
+#define DVC_VLUT_22_WORD_COUNT                  0x1
+#define DVC_VLUT_22_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VLUT_22_RESET_MASK                  _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_22_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_22_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_22_READ_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_22_WRITE_MASK                  _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_22_PMCNT_SHIFT                 _MK_SHIFT_CONST(10)
+#define DVC_VLUT_22_PMCNT_FIELD                 (_MK_MASK_CONST(0x3fff) << DVC_VLUT_22_PMCNT_SHIFT)
+#define DVC_VLUT_22_PMCNT_RANGE                 23:10
+#define DVC_VLUT_22_PMCNT_WOFFSET                       0x0
+#define DVC_VLUT_22_PMCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_22_PMCNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_22_PMCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_22_PMCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_22_VMIN_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VLUT_22_VMIN_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_22_VMIN_SHIFT)
+#define DVC_VLUT_22_VMIN_RANGE                  9:5
+#define DVC_VLUT_22_VMIN_WOFFSET                        0x0
+#define DVC_VLUT_22_VMIN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_22_VMIN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_22_VMIN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_22_VMIN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_22_VMAX_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VLUT_22_VMAX_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_22_VMAX_SHIFT)
+#define DVC_VLUT_22_VMAX_RANGE                  4:0
+#define DVC_VLUT_22_VMAX_WOFFSET                        0x0
+#define DVC_VLUT_22_VMAX_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_22_VMAX_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_22_VMAX_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_22_VMAX_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_23  
+#define DVC_VLUT_23                     _MK_ADDR_CONST(0x15c)
+#define DVC_VLUT_23_SECURE                      0x0
+#define DVC_VLUT_23_WORD_COUNT                  0x1
+#define DVC_VLUT_23_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VLUT_23_RESET_MASK                  _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_23_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_23_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_23_READ_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_23_WRITE_MASK                  _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_23_PMCNT_SHIFT                 _MK_SHIFT_CONST(10)
+#define DVC_VLUT_23_PMCNT_FIELD                 (_MK_MASK_CONST(0x3fff) << DVC_VLUT_23_PMCNT_SHIFT)
+#define DVC_VLUT_23_PMCNT_RANGE                 23:10
+#define DVC_VLUT_23_PMCNT_WOFFSET                       0x0
+#define DVC_VLUT_23_PMCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_23_PMCNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_23_PMCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_23_PMCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_23_VMIN_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VLUT_23_VMIN_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_23_VMIN_SHIFT)
+#define DVC_VLUT_23_VMIN_RANGE                  9:5
+#define DVC_VLUT_23_VMIN_WOFFSET                        0x0
+#define DVC_VLUT_23_VMIN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_23_VMIN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_23_VMIN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_23_VMIN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_23_VMAX_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VLUT_23_VMAX_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_23_VMAX_SHIFT)
+#define DVC_VLUT_23_VMAX_RANGE                  4:0
+#define DVC_VLUT_23_VMAX_WOFFSET                        0x0
+#define DVC_VLUT_23_VMAX_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_23_VMAX_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_23_VMAX_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_23_VMAX_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_24  
+#define DVC_VLUT_24                     _MK_ADDR_CONST(0x160)
+#define DVC_VLUT_24_SECURE                      0x0
+#define DVC_VLUT_24_WORD_COUNT                  0x1
+#define DVC_VLUT_24_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VLUT_24_RESET_MASK                  _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_24_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_24_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_24_READ_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_24_WRITE_MASK                  _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_24_PMCNT_SHIFT                 _MK_SHIFT_CONST(10)
+#define DVC_VLUT_24_PMCNT_FIELD                 (_MK_MASK_CONST(0x3fff) << DVC_VLUT_24_PMCNT_SHIFT)
+#define DVC_VLUT_24_PMCNT_RANGE                 23:10
+#define DVC_VLUT_24_PMCNT_WOFFSET                       0x0
+#define DVC_VLUT_24_PMCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_24_PMCNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_24_PMCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_24_PMCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_24_VMIN_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VLUT_24_VMIN_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_24_VMIN_SHIFT)
+#define DVC_VLUT_24_VMIN_RANGE                  9:5
+#define DVC_VLUT_24_VMIN_WOFFSET                        0x0
+#define DVC_VLUT_24_VMIN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_24_VMIN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_24_VMIN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_24_VMIN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_24_VMAX_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VLUT_24_VMAX_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_24_VMAX_SHIFT)
+#define DVC_VLUT_24_VMAX_RANGE                  4:0
+#define DVC_VLUT_24_VMAX_WOFFSET                        0x0
+#define DVC_VLUT_24_VMAX_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_24_VMAX_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_24_VMAX_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_24_VMAX_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_25  
+#define DVC_VLUT_25                     _MK_ADDR_CONST(0x164)
+#define DVC_VLUT_25_SECURE                      0x0
+#define DVC_VLUT_25_WORD_COUNT                  0x1
+#define DVC_VLUT_25_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VLUT_25_RESET_MASK                  _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_25_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_25_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_25_READ_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_25_WRITE_MASK                  _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_25_PMCNT_SHIFT                 _MK_SHIFT_CONST(10)
+#define DVC_VLUT_25_PMCNT_FIELD                 (_MK_MASK_CONST(0x3fff) << DVC_VLUT_25_PMCNT_SHIFT)
+#define DVC_VLUT_25_PMCNT_RANGE                 23:10
+#define DVC_VLUT_25_PMCNT_WOFFSET                       0x0
+#define DVC_VLUT_25_PMCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_25_PMCNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_25_PMCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_25_PMCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_25_VMIN_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VLUT_25_VMIN_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_25_VMIN_SHIFT)
+#define DVC_VLUT_25_VMIN_RANGE                  9:5
+#define DVC_VLUT_25_VMIN_WOFFSET                        0x0
+#define DVC_VLUT_25_VMIN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_25_VMIN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_25_VMIN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_25_VMIN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_25_VMAX_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VLUT_25_VMAX_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_25_VMAX_SHIFT)
+#define DVC_VLUT_25_VMAX_RANGE                  4:0
+#define DVC_VLUT_25_VMAX_WOFFSET                        0x0
+#define DVC_VLUT_25_VMAX_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_25_VMAX_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_25_VMAX_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_25_VMAX_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_26  
+#define DVC_VLUT_26                     _MK_ADDR_CONST(0x168)
+#define DVC_VLUT_26_SECURE                      0x0
+#define DVC_VLUT_26_WORD_COUNT                  0x1
+#define DVC_VLUT_26_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VLUT_26_RESET_MASK                  _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_26_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_26_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_26_READ_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_26_WRITE_MASK                  _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_26_PMCNT_SHIFT                 _MK_SHIFT_CONST(10)
+#define DVC_VLUT_26_PMCNT_FIELD                 (_MK_MASK_CONST(0x3fff) << DVC_VLUT_26_PMCNT_SHIFT)
+#define DVC_VLUT_26_PMCNT_RANGE                 23:10
+#define DVC_VLUT_26_PMCNT_WOFFSET                       0x0
+#define DVC_VLUT_26_PMCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_26_PMCNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_26_PMCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_26_PMCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_26_VMIN_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VLUT_26_VMIN_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_26_VMIN_SHIFT)
+#define DVC_VLUT_26_VMIN_RANGE                  9:5
+#define DVC_VLUT_26_VMIN_WOFFSET                        0x0
+#define DVC_VLUT_26_VMIN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_26_VMIN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_26_VMIN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_26_VMIN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_26_VMAX_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VLUT_26_VMAX_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_26_VMAX_SHIFT)
+#define DVC_VLUT_26_VMAX_RANGE                  4:0
+#define DVC_VLUT_26_VMAX_WOFFSET                        0x0
+#define DVC_VLUT_26_VMAX_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_26_VMAX_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_26_VMAX_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_26_VMAX_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_27  
+#define DVC_VLUT_27                     _MK_ADDR_CONST(0x16c)
+#define DVC_VLUT_27_SECURE                      0x0
+#define DVC_VLUT_27_WORD_COUNT                  0x1
+#define DVC_VLUT_27_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VLUT_27_RESET_MASK                  _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_27_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_27_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_27_READ_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_27_WRITE_MASK                  _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_27_PMCNT_SHIFT                 _MK_SHIFT_CONST(10)
+#define DVC_VLUT_27_PMCNT_FIELD                 (_MK_MASK_CONST(0x3fff) << DVC_VLUT_27_PMCNT_SHIFT)
+#define DVC_VLUT_27_PMCNT_RANGE                 23:10
+#define DVC_VLUT_27_PMCNT_WOFFSET                       0x0
+#define DVC_VLUT_27_PMCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_27_PMCNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_27_PMCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_27_PMCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_27_VMIN_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VLUT_27_VMIN_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_27_VMIN_SHIFT)
+#define DVC_VLUT_27_VMIN_RANGE                  9:5
+#define DVC_VLUT_27_VMIN_WOFFSET                        0x0
+#define DVC_VLUT_27_VMIN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_27_VMIN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_27_VMIN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_27_VMIN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_27_VMAX_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VLUT_27_VMAX_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_27_VMAX_SHIFT)
+#define DVC_VLUT_27_VMAX_RANGE                  4:0
+#define DVC_VLUT_27_VMAX_WOFFSET                        0x0
+#define DVC_VLUT_27_VMAX_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_27_VMAX_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_27_VMAX_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_27_VMAX_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_28  
+#define DVC_VLUT_28                     _MK_ADDR_CONST(0x170)
+#define DVC_VLUT_28_SECURE                      0x0
+#define DVC_VLUT_28_WORD_COUNT                  0x1
+#define DVC_VLUT_28_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VLUT_28_RESET_MASK                  _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_28_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_28_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_28_READ_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_28_WRITE_MASK                  _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_28_PMCNT_SHIFT                 _MK_SHIFT_CONST(10)
+#define DVC_VLUT_28_PMCNT_FIELD                 (_MK_MASK_CONST(0x3fff) << DVC_VLUT_28_PMCNT_SHIFT)
+#define DVC_VLUT_28_PMCNT_RANGE                 23:10
+#define DVC_VLUT_28_PMCNT_WOFFSET                       0x0
+#define DVC_VLUT_28_PMCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_28_PMCNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_28_PMCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_28_PMCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_28_VMIN_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VLUT_28_VMIN_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_28_VMIN_SHIFT)
+#define DVC_VLUT_28_VMIN_RANGE                  9:5
+#define DVC_VLUT_28_VMIN_WOFFSET                        0x0
+#define DVC_VLUT_28_VMIN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_28_VMIN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_28_VMIN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_28_VMIN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_28_VMAX_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VLUT_28_VMAX_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_28_VMAX_SHIFT)
+#define DVC_VLUT_28_VMAX_RANGE                  4:0
+#define DVC_VLUT_28_VMAX_WOFFSET                        0x0
+#define DVC_VLUT_28_VMAX_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_28_VMAX_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_28_VMAX_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_28_VMAX_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_29  
+#define DVC_VLUT_29                     _MK_ADDR_CONST(0x174)
+#define DVC_VLUT_29_SECURE                      0x0
+#define DVC_VLUT_29_WORD_COUNT                  0x1
+#define DVC_VLUT_29_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VLUT_29_RESET_MASK                  _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_29_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_29_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_29_READ_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_29_WRITE_MASK                  _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_29_PMCNT_SHIFT                 _MK_SHIFT_CONST(10)
+#define DVC_VLUT_29_PMCNT_FIELD                 (_MK_MASK_CONST(0x3fff) << DVC_VLUT_29_PMCNT_SHIFT)
+#define DVC_VLUT_29_PMCNT_RANGE                 23:10
+#define DVC_VLUT_29_PMCNT_WOFFSET                       0x0
+#define DVC_VLUT_29_PMCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_29_PMCNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_29_PMCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_29_PMCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_29_VMIN_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VLUT_29_VMIN_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_29_VMIN_SHIFT)
+#define DVC_VLUT_29_VMIN_RANGE                  9:5
+#define DVC_VLUT_29_VMIN_WOFFSET                        0x0
+#define DVC_VLUT_29_VMIN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_29_VMIN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_29_VMIN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_29_VMIN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_29_VMAX_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VLUT_29_VMAX_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_29_VMAX_SHIFT)
+#define DVC_VLUT_29_VMAX_RANGE                  4:0
+#define DVC_VLUT_29_VMAX_WOFFSET                        0x0
+#define DVC_VLUT_29_VMAX_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_29_VMAX_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_29_VMAX_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_29_VMAX_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_30  
+#define DVC_VLUT_30                     _MK_ADDR_CONST(0x178)
+#define DVC_VLUT_30_SECURE                      0x0
+#define DVC_VLUT_30_WORD_COUNT                  0x1
+#define DVC_VLUT_30_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VLUT_30_RESET_MASK                  _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_30_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_30_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_30_READ_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_30_WRITE_MASK                  _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_30_PMCNT_SHIFT                 _MK_SHIFT_CONST(10)
+#define DVC_VLUT_30_PMCNT_FIELD                 (_MK_MASK_CONST(0x3fff) << DVC_VLUT_30_PMCNT_SHIFT)
+#define DVC_VLUT_30_PMCNT_RANGE                 23:10
+#define DVC_VLUT_30_PMCNT_WOFFSET                       0x0
+#define DVC_VLUT_30_PMCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_30_PMCNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_30_PMCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_30_PMCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_30_VMIN_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VLUT_30_VMIN_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_30_VMIN_SHIFT)
+#define DVC_VLUT_30_VMIN_RANGE                  9:5
+#define DVC_VLUT_30_VMIN_WOFFSET                        0x0
+#define DVC_VLUT_30_VMIN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_30_VMIN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_30_VMIN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_30_VMIN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_30_VMAX_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VLUT_30_VMAX_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_30_VMAX_SHIFT)
+#define DVC_VLUT_30_VMAX_RANGE                  4:0
+#define DVC_VLUT_30_VMAX_WOFFSET                        0x0
+#define DVC_VLUT_30_VMAX_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_30_VMAX_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_30_VMAX_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_30_VMAX_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_31  
+#define DVC_VLUT_31                     _MK_ADDR_CONST(0x17c)
+#define DVC_VLUT_31_SECURE                      0x0
+#define DVC_VLUT_31_WORD_COUNT                  0x1
+#define DVC_VLUT_31_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VLUT_31_RESET_MASK                  _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_31_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_31_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_31_READ_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_31_WRITE_MASK                  _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_31_PMCNT_SHIFT                 _MK_SHIFT_CONST(10)
+#define DVC_VLUT_31_PMCNT_FIELD                 (_MK_MASK_CONST(0x3fff) << DVC_VLUT_31_PMCNT_SHIFT)
+#define DVC_VLUT_31_PMCNT_RANGE                 23:10
+#define DVC_VLUT_31_PMCNT_WOFFSET                       0x0
+#define DVC_VLUT_31_PMCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_31_PMCNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_31_PMCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_31_PMCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_31_VMIN_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VLUT_31_VMIN_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_31_VMIN_SHIFT)
+#define DVC_VLUT_31_VMIN_RANGE                  9:5
+#define DVC_VLUT_31_VMIN_WOFFSET                        0x0
+#define DVC_VLUT_31_VMIN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_31_VMIN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_31_VMIN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_31_VMIN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_31_VMAX_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VLUT_31_VMAX_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_31_VMAX_SHIFT)
+#define DVC_VLUT_31_VMAX_RANGE                  4:0
+#define DVC_VLUT_31_VMAX_WOFFSET                        0x0
+#define DVC_VLUT_31_VMAX_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_31_VMAX_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_31_VMAX_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_31_VMAX_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_32  
+#define DVC_VLUT_32                     _MK_ADDR_CONST(0x180)
+#define DVC_VLUT_32_SECURE                      0x0
+#define DVC_VLUT_32_WORD_COUNT                  0x1
+#define DVC_VLUT_32_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VLUT_32_RESET_MASK                  _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_32_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_32_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_32_READ_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_32_WRITE_MASK                  _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_32_PMCNT_SHIFT                 _MK_SHIFT_CONST(10)
+#define DVC_VLUT_32_PMCNT_FIELD                 (_MK_MASK_CONST(0x3fff) << DVC_VLUT_32_PMCNT_SHIFT)
+#define DVC_VLUT_32_PMCNT_RANGE                 23:10
+#define DVC_VLUT_32_PMCNT_WOFFSET                       0x0
+#define DVC_VLUT_32_PMCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_32_PMCNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_32_PMCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_32_PMCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_32_VMIN_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VLUT_32_VMIN_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_32_VMIN_SHIFT)
+#define DVC_VLUT_32_VMIN_RANGE                  9:5
+#define DVC_VLUT_32_VMIN_WOFFSET                        0x0
+#define DVC_VLUT_32_VMIN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_32_VMIN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_32_VMIN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_32_VMIN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_32_VMAX_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VLUT_32_VMAX_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_32_VMAX_SHIFT)
+#define DVC_VLUT_32_VMAX_RANGE                  4:0
+#define DVC_VLUT_32_VMAX_WOFFSET                        0x0
+#define DVC_VLUT_32_VMAX_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_32_VMAX_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_32_VMAX_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_32_VMAX_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_33  
+#define DVC_VLUT_33                     _MK_ADDR_CONST(0x184)
+#define DVC_VLUT_33_SECURE                      0x0
+#define DVC_VLUT_33_WORD_COUNT                  0x1
+#define DVC_VLUT_33_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VLUT_33_RESET_MASK                  _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_33_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_33_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_33_READ_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_33_WRITE_MASK                  _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_33_PMCNT_SHIFT                 _MK_SHIFT_CONST(10)
+#define DVC_VLUT_33_PMCNT_FIELD                 (_MK_MASK_CONST(0x3fff) << DVC_VLUT_33_PMCNT_SHIFT)
+#define DVC_VLUT_33_PMCNT_RANGE                 23:10
+#define DVC_VLUT_33_PMCNT_WOFFSET                       0x0
+#define DVC_VLUT_33_PMCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_33_PMCNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_33_PMCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_33_PMCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_33_VMIN_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VLUT_33_VMIN_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_33_VMIN_SHIFT)
+#define DVC_VLUT_33_VMIN_RANGE                  9:5
+#define DVC_VLUT_33_VMIN_WOFFSET                        0x0
+#define DVC_VLUT_33_VMIN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_33_VMIN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_33_VMIN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_33_VMIN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_33_VMAX_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VLUT_33_VMAX_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_33_VMAX_SHIFT)
+#define DVC_VLUT_33_VMAX_RANGE                  4:0
+#define DVC_VLUT_33_VMAX_WOFFSET                        0x0
+#define DVC_VLUT_33_VMAX_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_33_VMAX_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_33_VMAX_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_33_VMAX_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_34  
+#define DVC_VLUT_34                     _MK_ADDR_CONST(0x188)
+#define DVC_VLUT_34_SECURE                      0x0
+#define DVC_VLUT_34_WORD_COUNT                  0x1
+#define DVC_VLUT_34_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VLUT_34_RESET_MASK                  _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_34_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_34_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_34_READ_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_34_WRITE_MASK                  _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_34_PMCNT_SHIFT                 _MK_SHIFT_CONST(10)
+#define DVC_VLUT_34_PMCNT_FIELD                 (_MK_MASK_CONST(0x3fff) << DVC_VLUT_34_PMCNT_SHIFT)
+#define DVC_VLUT_34_PMCNT_RANGE                 23:10
+#define DVC_VLUT_34_PMCNT_WOFFSET                       0x0
+#define DVC_VLUT_34_PMCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_34_PMCNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_34_PMCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_34_PMCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_34_VMIN_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VLUT_34_VMIN_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_34_VMIN_SHIFT)
+#define DVC_VLUT_34_VMIN_RANGE                  9:5
+#define DVC_VLUT_34_VMIN_WOFFSET                        0x0
+#define DVC_VLUT_34_VMIN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_34_VMIN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_34_VMIN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_34_VMIN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_34_VMAX_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VLUT_34_VMAX_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_34_VMAX_SHIFT)
+#define DVC_VLUT_34_VMAX_RANGE                  4:0
+#define DVC_VLUT_34_VMAX_WOFFSET                        0x0
+#define DVC_VLUT_34_VMAX_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_34_VMAX_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_34_VMAX_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_34_VMAX_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_35  
+#define DVC_VLUT_35                     _MK_ADDR_CONST(0x18c)
+#define DVC_VLUT_35_SECURE                      0x0
+#define DVC_VLUT_35_WORD_COUNT                  0x1
+#define DVC_VLUT_35_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VLUT_35_RESET_MASK                  _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_35_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_35_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_35_READ_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_35_WRITE_MASK                  _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_35_PMCNT_SHIFT                 _MK_SHIFT_CONST(10)
+#define DVC_VLUT_35_PMCNT_FIELD                 (_MK_MASK_CONST(0x3fff) << DVC_VLUT_35_PMCNT_SHIFT)
+#define DVC_VLUT_35_PMCNT_RANGE                 23:10
+#define DVC_VLUT_35_PMCNT_WOFFSET                       0x0
+#define DVC_VLUT_35_PMCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_35_PMCNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_35_PMCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_35_PMCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_35_VMIN_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VLUT_35_VMIN_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_35_VMIN_SHIFT)
+#define DVC_VLUT_35_VMIN_RANGE                  9:5
+#define DVC_VLUT_35_VMIN_WOFFSET                        0x0
+#define DVC_VLUT_35_VMIN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_35_VMIN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_35_VMIN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_35_VMIN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_35_VMAX_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VLUT_35_VMAX_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_35_VMAX_SHIFT)
+#define DVC_VLUT_35_VMAX_RANGE                  4:0
+#define DVC_VLUT_35_VMAX_WOFFSET                        0x0
+#define DVC_VLUT_35_VMAX_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_35_VMAX_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_35_VMAX_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_35_VMAX_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_36  
+#define DVC_VLUT_36                     _MK_ADDR_CONST(0x190)
+#define DVC_VLUT_36_SECURE                      0x0
+#define DVC_VLUT_36_WORD_COUNT                  0x1
+#define DVC_VLUT_36_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VLUT_36_RESET_MASK                  _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_36_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_36_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_36_READ_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_36_WRITE_MASK                  _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_36_PMCNT_SHIFT                 _MK_SHIFT_CONST(10)
+#define DVC_VLUT_36_PMCNT_FIELD                 (_MK_MASK_CONST(0x3fff) << DVC_VLUT_36_PMCNT_SHIFT)
+#define DVC_VLUT_36_PMCNT_RANGE                 23:10
+#define DVC_VLUT_36_PMCNT_WOFFSET                       0x0
+#define DVC_VLUT_36_PMCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_36_PMCNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_36_PMCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_36_PMCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_36_VMIN_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VLUT_36_VMIN_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_36_VMIN_SHIFT)
+#define DVC_VLUT_36_VMIN_RANGE                  9:5
+#define DVC_VLUT_36_VMIN_WOFFSET                        0x0
+#define DVC_VLUT_36_VMIN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_36_VMIN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_36_VMIN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_36_VMIN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_36_VMAX_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VLUT_36_VMAX_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_36_VMAX_SHIFT)
+#define DVC_VLUT_36_VMAX_RANGE                  4:0
+#define DVC_VLUT_36_VMAX_WOFFSET                        0x0
+#define DVC_VLUT_36_VMAX_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_36_VMAX_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_36_VMAX_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_36_VMAX_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_37  
+#define DVC_VLUT_37                     _MK_ADDR_CONST(0x194)
+#define DVC_VLUT_37_SECURE                      0x0
+#define DVC_VLUT_37_WORD_COUNT                  0x1
+#define DVC_VLUT_37_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VLUT_37_RESET_MASK                  _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_37_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_37_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_37_READ_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_37_WRITE_MASK                  _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_37_PMCNT_SHIFT                 _MK_SHIFT_CONST(10)
+#define DVC_VLUT_37_PMCNT_FIELD                 (_MK_MASK_CONST(0x3fff) << DVC_VLUT_37_PMCNT_SHIFT)
+#define DVC_VLUT_37_PMCNT_RANGE                 23:10
+#define DVC_VLUT_37_PMCNT_WOFFSET                       0x0
+#define DVC_VLUT_37_PMCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_37_PMCNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_37_PMCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_37_PMCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_37_VMIN_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VLUT_37_VMIN_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_37_VMIN_SHIFT)
+#define DVC_VLUT_37_VMIN_RANGE                  9:5
+#define DVC_VLUT_37_VMIN_WOFFSET                        0x0
+#define DVC_VLUT_37_VMIN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_37_VMIN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_37_VMIN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_37_VMIN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_37_VMAX_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VLUT_37_VMAX_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_37_VMAX_SHIFT)
+#define DVC_VLUT_37_VMAX_RANGE                  4:0
+#define DVC_VLUT_37_VMAX_WOFFSET                        0x0
+#define DVC_VLUT_37_VMAX_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_37_VMAX_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_37_VMAX_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_37_VMAX_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_38  
+#define DVC_VLUT_38                     _MK_ADDR_CONST(0x198)
+#define DVC_VLUT_38_SECURE                      0x0
+#define DVC_VLUT_38_WORD_COUNT                  0x1
+#define DVC_VLUT_38_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VLUT_38_RESET_MASK                  _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_38_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_38_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_38_READ_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_38_WRITE_MASK                  _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_38_PMCNT_SHIFT                 _MK_SHIFT_CONST(10)
+#define DVC_VLUT_38_PMCNT_FIELD                 (_MK_MASK_CONST(0x3fff) << DVC_VLUT_38_PMCNT_SHIFT)
+#define DVC_VLUT_38_PMCNT_RANGE                 23:10
+#define DVC_VLUT_38_PMCNT_WOFFSET                       0x0
+#define DVC_VLUT_38_PMCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_38_PMCNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_38_PMCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_38_PMCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_38_VMIN_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VLUT_38_VMIN_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_38_VMIN_SHIFT)
+#define DVC_VLUT_38_VMIN_RANGE                  9:5
+#define DVC_VLUT_38_VMIN_WOFFSET                        0x0
+#define DVC_VLUT_38_VMIN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_38_VMIN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_38_VMIN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_38_VMIN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_38_VMAX_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VLUT_38_VMAX_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_38_VMAX_SHIFT)
+#define DVC_VLUT_38_VMAX_RANGE                  4:0
+#define DVC_VLUT_38_VMAX_WOFFSET                        0x0
+#define DVC_VLUT_38_VMAX_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_38_VMAX_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_38_VMAX_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_38_VMAX_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_39  
+#define DVC_VLUT_39                     _MK_ADDR_CONST(0x19c)
+#define DVC_VLUT_39_SECURE                      0x0
+#define DVC_VLUT_39_WORD_COUNT                  0x1
+#define DVC_VLUT_39_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VLUT_39_RESET_MASK                  _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_39_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_39_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_39_READ_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_39_WRITE_MASK                  _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_39_PMCNT_SHIFT                 _MK_SHIFT_CONST(10)
+#define DVC_VLUT_39_PMCNT_FIELD                 (_MK_MASK_CONST(0x3fff) << DVC_VLUT_39_PMCNT_SHIFT)
+#define DVC_VLUT_39_PMCNT_RANGE                 23:10
+#define DVC_VLUT_39_PMCNT_WOFFSET                       0x0
+#define DVC_VLUT_39_PMCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_39_PMCNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_39_PMCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_39_PMCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_39_VMIN_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VLUT_39_VMIN_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_39_VMIN_SHIFT)
+#define DVC_VLUT_39_VMIN_RANGE                  9:5
+#define DVC_VLUT_39_VMIN_WOFFSET                        0x0
+#define DVC_VLUT_39_VMIN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_39_VMIN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_39_VMIN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_39_VMIN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_39_VMAX_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VLUT_39_VMAX_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_39_VMAX_SHIFT)
+#define DVC_VLUT_39_VMAX_RANGE                  4:0
+#define DVC_VLUT_39_VMAX_WOFFSET                        0x0
+#define DVC_VLUT_39_VMAX_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_39_VMAX_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_39_VMAX_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_39_VMAX_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_40  
+#define DVC_VLUT_40                     _MK_ADDR_CONST(0x1a0)
+#define DVC_VLUT_40_SECURE                      0x0
+#define DVC_VLUT_40_WORD_COUNT                  0x1
+#define DVC_VLUT_40_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VLUT_40_RESET_MASK                  _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_40_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_40_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_40_READ_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_40_WRITE_MASK                  _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_40_PMCNT_SHIFT                 _MK_SHIFT_CONST(10)
+#define DVC_VLUT_40_PMCNT_FIELD                 (_MK_MASK_CONST(0x3fff) << DVC_VLUT_40_PMCNT_SHIFT)
+#define DVC_VLUT_40_PMCNT_RANGE                 23:10
+#define DVC_VLUT_40_PMCNT_WOFFSET                       0x0
+#define DVC_VLUT_40_PMCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_40_PMCNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_40_PMCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_40_PMCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_40_VMIN_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VLUT_40_VMIN_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_40_VMIN_SHIFT)
+#define DVC_VLUT_40_VMIN_RANGE                  9:5
+#define DVC_VLUT_40_VMIN_WOFFSET                        0x0
+#define DVC_VLUT_40_VMIN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_40_VMIN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_40_VMIN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_40_VMIN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_40_VMAX_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VLUT_40_VMAX_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_40_VMAX_SHIFT)
+#define DVC_VLUT_40_VMAX_RANGE                  4:0
+#define DVC_VLUT_40_VMAX_WOFFSET                        0x0
+#define DVC_VLUT_40_VMAX_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_40_VMAX_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_40_VMAX_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_40_VMAX_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_41  
+#define DVC_VLUT_41                     _MK_ADDR_CONST(0x1a4)
+#define DVC_VLUT_41_SECURE                      0x0
+#define DVC_VLUT_41_WORD_COUNT                  0x1
+#define DVC_VLUT_41_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VLUT_41_RESET_MASK                  _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_41_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_41_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_41_READ_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_41_WRITE_MASK                  _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_41_PMCNT_SHIFT                 _MK_SHIFT_CONST(10)
+#define DVC_VLUT_41_PMCNT_FIELD                 (_MK_MASK_CONST(0x3fff) << DVC_VLUT_41_PMCNT_SHIFT)
+#define DVC_VLUT_41_PMCNT_RANGE                 23:10
+#define DVC_VLUT_41_PMCNT_WOFFSET                       0x0
+#define DVC_VLUT_41_PMCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_41_PMCNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_41_PMCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_41_PMCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_41_VMIN_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VLUT_41_VMIN_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_41_VMIN_SHIFT)
+#define DVC_VLUT_41_VMIN_RANGE                  9:5
+#define DVC_VLUT_41_VMIN_WOFFSET                        0x0
+#define DVC_VLUT_41_VMIN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_41_VMIN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_41_VMIN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_41_VMIN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_41_VMAX_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VLUT_41_VMAX_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_41_VMAX_SHIFT)
+#define DVC_VLUT_41_VMAX_RANGE                  4:0
+#define DVC_VLUT_41_VMAX_WOFFSET                        0x0
+#define DVC_VLUT_41_VMAX_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_41_VMAX_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_41_VMAX_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_41_VMAX_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_42  
+#define DVC_VLUT_42                     _MK_ADDR_CONST(0x1a8)
+#define DVC_VLUT_42_SECURE                      0x0
+#define DVC_VLUT_42_WORD_COUNT                  0x1
+#define DVC_VLUT_42_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VLUT_42_RESET_MASK                  _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_42_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_42_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_42_READ_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_42_WRITE_MASK                  _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_42_PMCNT_SHIFT                 _MK_SHIFT_CONST(10)
+#define DVC_VLUT_42_PMCNT_FIELD                 (_MK_MASK_CONST(0x3fff) << DVC_VLUT_42_PMCNT_SHIFT)
+#define DVC_VLUT_42_PMCNT_RANGE                 23:10
+#define DVC_VLUT_42_PMCNT_WOFFSET                       0x0
+#define DVC_VLUT_42_PMCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_42_PMCNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_42_PMCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_42_PMCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_42_VMIN_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VLUT_42_VMIN_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_42_VMIN_SHIFT)
+#define DVC_VLUT_42_VMIN_RANGE                  9:5
+#define DVC_VLUT_42_VMIN_WOFFSET                        0x0
+#define DVC_VLUT_42_VMIN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_42_VMIN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_42_VMIN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_42_VMIN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_42_VMAX_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VLUT_42_VMAX_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_42_VMAX_SHIFT)
+#define DVC_VLUT_42_VMAX_RANGE                  4:0
+#define DVC_VLUT_42_VMAX_WOFFSET                        0x0
+#define DVC_VLUT_42_VMAX_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_42_VMAX_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_42_VMAX_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_42_VMAX_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_43  
+#define DVC_VLUT_43                     _MK_ADDR_CONST(0x1ac)
+#define DVC_VLUT_43_SECURE                      0x0
+#define DVC_VLUT_43_WORD_COUNT                  0x1
+#define DVC_VLUT_43_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VLUT_43_RESET_MASK                  _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_43_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_43_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_43_READ_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_43_WRITE_MASK                  _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_43_PMCNT_SHIFT                 _MK_SHIFT_CONST(10)
+#define DVC_VLUT_43_PMCNT_FIELD                 (_MK_MASK_CONST(0x3fff) << DVC_VLUT_43_PMCNT_SHIFT)
+#define DVC_VLUT_43_PMCNT_RANGE                 23:10
+#define DVC_VLUT_43_PMCNT_WOFFSET                       0x0
+#define DVC_VLUT_43_PMCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_43_PMCNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_43_PMCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_43_PMCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_43_VMIN_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VLUT_43_VMIN_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_43_VMIN_SHIFT)
+#define DVC_VLUT_43_VMIN_RANGE                  9:5
+#define DVC_VLUT_43_VMIN_WOFFSET                        0x0
+#define DVC_VLUT_43_VMIN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_43_VMIN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_43_VMIN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_43_VMIN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_43_VMAX_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VLUT_43_VMAX_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_43_VMAX_SHIFT)
+#define DVC_VLUT_43_VMAX_RANGE                  4:0
+#define DVC_VLUT_43_VMAX_WOFFSET                        0x0
+#define DVC_VLUT_43_VMAX_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_43_VMAX_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_43_VMAX_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_43_VMAX_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_44  
+#define DVC_VLUT_44                     _MK_ADDR_CONST(0x1b0)
+#define DVC_VLUT_44_SECURE                      0x0
+#define DVC_VLUT_44_WORD_COUNT                  0x1
+#define DVC_VLUT_44_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VLUT_44_RESET_MASK                  _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_44_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_44_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_44_READ_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_44_WRITE_MASK                  _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_44_PMCNT_SHIFT                 _MK_SHIFT_CONST(10)
+#define DVC_VLUT_44_PMCNT_FIELD                 (_MK_MASK_CONST(0x3fff) << DVC_VLUT_44_PMCNT_SHIFT)
+#define DVC_VLUT_44_PMCNT_RANGE                 23:10
+#define DVC_VLUT_44_PMCNT_WOFFSET                       0x0
+#define DVC_VLUT_44_PMCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_44_PMCNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_44_PMCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_44_PMCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_44_VMIN_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VLUT_44_VMIN_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_44_VMIN_SHIFT)
+#define DVC_VLUT_44_VMIN_RANGE                  9:5
+#define DVC_VLUT_44_VMIN_WOFFSET                        0x0
+#define DVC_VLUT_44_VMIN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_44_VMIN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_44_VMIN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_44_VMIN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_44_VMAX_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VLUT_44_VMAX_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_44_VMAX_SHIFT)
+#define DVC_VLUT_44_VMAX_RANGE                  4:0
+#define DVC_VLUT_44_VMAX_WOFFSET                        0x0
+#define DVC_VLUT_44_VMAX_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_44_VMAX_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_44_VMAX_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_44_VMAX_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_45  
+#define DVC_VLUT_45                     _MK_ADDR_CONST(0x1b4)
+#define DVC_VLUT_45_SECURE                      0x0
+#define DVC_VLUT_45_WORD_COUNT                  0x1
+#define DVC_VLUT_45_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VLUT_45_RESET_MASK                  _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_45_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_45_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_45_READ_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_45_WRITE_MASK                  _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_45_PMCNT_SHIFT                 _MK_SHIFT_CONST(10)
+#define DVC_VLUT_45_PMCNT_FIELD                 (_MK_MASK_CONST(0x3fff) << DVC_VLUT_45_PMCNT_SHIFT)
+#define DVC_VLUT_45_PMCNT_RANGE                 23:10
+#define DVC_VLUT_45_PMCNT_WOFFSET                       0x0
+#define DVC_VLUT_45_PMCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_45_PMCNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_45_PMCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_45_PMCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_45_VMIN_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VLUT_45_VMIN_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_45_VMIN_SHIFT)
+#define DVC_VLUT_45_VMIN_RANGE                  9:5
+#define DVC_VLUT_45_VMIN_WOFFSET                        0x0
+#define DVC_VLUT_45_VMIN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_45_VMIN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_45_VMIN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_45_VMIN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_45_VMAX_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VLUT_45_VMAX_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_45_VMAX_SHIFT)
+#define DVC_VLUT_45_VMAX_RANGE                  4:0
+#define DVC_VLUT_45_VMAX_WOFFSET                        0x0
+#define DVC_VLUT_45_VMAX_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_45_VMAX_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_45_VMAX_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_45_VMAX_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_46  
+#define DVC_VLUT_46                     _MK_ADDR_CONST(0x1b8)
+#define DVC_VLUT_46_SECURE                      0x0
+#define DVC_VLUT_46_WORD_COUNT                  0x1
+#define DVC_VLUT_46_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VLUT_46_RESET_MASK                  _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_46_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_46_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_46_READ_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_46_WRITE_MASK                  _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_46_PMCNT_SHIFT                 _MK_SHIFT_CONST(10)
+#define DVC_VLUT_46_PMCNT_FIELD                 (_MK_MASK_CONST(0x3fff) << DVC_VLUT_46_PMCNT_SHIFT)
+#define DVC_VLUT_46_PMCNT_RANGE                 23:10
+#define DVC_VLUT_46_PMCNT_WOFFSET                       0x0
+#define DVC_VLUT_46_PMCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_46_PMCNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_46_PMCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_46_PMCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_46_VMIN_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VLUT_46_VMIN_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_46_VMIN_SHIFT)
+#define DVC_VLUT_46_VMIN_RANGE                  9:5
+#define DVC_VLUT_46_VMIN_WOFFSET                        0x0
+#define DVC_VLUT_46_VMIN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_46_VMIN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_46_VMIN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_46_VMIN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_46_VMAX_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VLUT_46_VMAX_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_46_VMAX_SHIFT)
+#define DVC_VLUT_46_VMAX_RANGE                  4:0
+#define DVC_VLUT_46_VMAX_WOFFSET                        0x0
+#define DVC_VLUT_46_VMAX_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_46_VMAX_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_46_VMAX_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_46_VMAX_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_47  
+#define DVC_VLUT_47                     _MK_ADDR_CONST(0x1bc)
+#define DVC_VLUT_47_SECURE                      0x0
+#define DVC_VLUT_47_WORD_COUNT                  0x1
+#define DVC_VLUT_47_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VLUT_47_RESET_MASK                  _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_47_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_47_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_47_READ_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_47_WRITE_MASK                  _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_47_PMCNT_SHIFT                 _MK_SHIFT_CONST(10)
+#define DVC_VLUT_47_PMCNT_FIELD                 (_MK_MASK_CONST(0x3fff) << DVC_VLUT_47_PMCNT_SHIFT)
+#define DVC_VLUT_47_PMCNT_RANGE                 23:10
+#define DVC_VLUT_47_PMCNT_WOFFSET                       0x0
+#define DVC_VLUT_47_PMCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_47_PMCNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_47_PMCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_47_PMCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_47_VMIN_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VLUT_47_VMIN_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_47_VMIN_SHIFT)
+#define DVC_VLUT_47_VMIN_RANGE                  9:5
+#define DVC_VLUT_47_VMIN_WOFFSET                        0x0
+#define DVC_VLUT_47_VMIN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_47_VMIN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_47_VMIN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_47_VMIN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_47_VMAX_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VLUT_47_VMAX_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_47_VMAX_SHIFT)
+#define DVC_VLUT_47_VMAX_RANGE                  4:0
+#define DVC_VLUT_47_VMAX_WOFFSET                        0x0
+#define DVC_VLUT_47_VMAX_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_47_VMAX_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_47_VMAX_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_47_VMAX_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_48  
+#define DVC_VLUT_48                     _MK_ADDR_CONST(0x1c0)
+#define DVC_VLUT_48_SECURE                      0x0
+#define DVC_VLUT_48_WORD_COUNT                  0x1
+#define DVC_VLUT_48_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VLUT_48_RESET_MASK                  _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_48_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_48_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_48_READ_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_48_WRITE_MASK                  _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_48_PMCNT_SHIFT                 _MK_SHIFT_CONST(10)
+#define DVC_VLUT_48_PMCNT_FIELD                 (_MK_MASK_CONST(0x3fff) << DVC_VLUT_48_PMCNT_SHIFT)
+#define DVC_VLUT_48_PMCNT_RANGE                 23:10
+#define DVC_VLUT_48_PMCNT_WOFFSET                       0x0
+#define DVC_VLUT_48_PMCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_48_PMCNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_48_PMCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_48_PMCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_48_VMIN_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VLUT_48_VMIN_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_48_VMIN_SHIFT)
+#define DVC_VLUT_48_VMIN_RANGE                  9:5
+#define DVC_VLUT_48_VMIN_WOFFSET                        0x0
+#define DVC_VLUT_48_VMIN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_48_VMIN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_48_VMIN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_48_VMIN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_48_VMAX_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VLUT_48_VMAX_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_48_VMAX_SHIFT)
+#define DVC_VLUT_48_VMAX_RANGE                  4:0
+#define DVC_VLUT_48_VMAX_WOFFSET                        0x0
+#define DVC_VLUT_48_VMAX_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_48_VMAX_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_48_VMAX_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_48_VMAX_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_49  
+#define DVC_VLUT_49                     _MK_ADDR_CONST(0x1c4)
+#define DVC_VLUT_49_SECURE                      0x0
+#define DVC_VLUT_49_WORD_COUNT                  0x1
+#define DVC_VLUT_49_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VLUT_49_RESET_MASK                  _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_49_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_49_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_49_READ_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_49_WRITE_MASK                  _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_49_PMCNT_SHIFT                 _MK_SHIFT_CONST(10)
+#define DVC_VLUT_49_PMCNT_FIELD                 (_MK_MASK_CONST(0x3fff) << DVC_VLUT_49_PMCNT_SHIFT)
+#define DVC_VLUT_49_PMCNT_RANGE                 23:10
+#define DVC_VLUT_49_PMCNT_WOFFSET                       0x0
+#define DVC_VLUT_49_PMCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_49_PMCNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_49_PMCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_49_PMCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_49_VMIN_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VLUT_49_VMIN_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_49_VMIN_SHIFT)
+#define DVC_VLUT_49_VMIN_RANGE                  9:5
+#define DVC_VLUT_49_VMIN_WOFFSET                        0x0
+#define DVC_VLUT_49_VMIN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_49_VMIN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_49_VMIN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_49_VMIN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_49_VMAX_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VLUT_49_VMAX_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_49_VMAX_SHIFT)
+#define DVC_VLUT_49_VMAX_RANGE                  4:0
+#define DVC_VLUT_49_VMAX_WOFFSET                        0x0
+#define DVC_VLUT_49_VMAX_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_49_VMAX_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_49_VMAX_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_49_VMAX_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_50  
+#define DVC_VLUT_50                     _MK_ADDR_CONST(0x1c8)
+#define DVC_VLUT_50_SECURE                      0x0
+#define DVC_VLUT_50_WORD_COUNT                  0x1
+#define DVC_VLUT_50_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VLUT_50_RESET_MASK                  _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_50_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_50_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_50_READ_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_50_WRITE_MASK                  _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_50_PMCNT_SHIFT                 _MK_SHIFT_CONST(10)
+#define DVC_VLUT_50_PMCNT_FIELD                 (_MK_MASK_CONST(0x3fff) << DVC_VLUT_50_PMCNT_SHIFT)
+#define DVC_VLUT_50_PMCNT_RANGE                 23:10
+#define DVC_VLUT_50_PMCNT_WOFFSET                       0x0
+#define DVC_VLUT_50_PMCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_50_PMCNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_50_PMCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_50_PMCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_50_VMIN_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VLUT_50_VMIN_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_50_VMIN_SHIFT)
+#define DVC_VLUT_50_VMIN_RANGE                  9:5
+#define DVC_VLUT_50_VMIN_WOFFSET                        0x0
+#define DVC_VLUT_50_VMIN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_50_VMIN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_50_VMIN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_50_VMIN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_50_VMAX_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VLUT_50_VMAX_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_50_VMAX_SHIFT)
+#define DVC_VLUT_50_VMAX_RANGE                  4:0
+#define DVC_VLUT_50_VMAX_WOFFSET                        0x0
+#define DVC_VLUT_50_VMAX_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_50_VMAX_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_50_VMAX_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_50_VMAX_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_51  
+#define DVC_VLUT_51                     _MK_ADDR_CONST(0x1cc)
+#define DVC_VLUT_51_SECURE                      0x0
+#define DVC_VLUT_51_WORD_COUNT                  0x1
+#define DVC_VLUT_51_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VLUT_51_RESET_MASK                  _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_51_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_51_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_51_READ_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_51_WRITE_MASK                  _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_51_PMCNT_SHIFT                 _MK_SHIFT_CONST(10)
+#define DVC_VLUT_51_PMCNT_FIELD                 (_MK_MASK_CONST(0x3fff) << DVC_VLUT_51_PMCNT_SHIFT)
+#define DVC_VLUT_51_PMCNT_RANGE                 23:10
+#define DVC_VLUT_51_PMCNT_WOFFSET                       0x0
+#define DVC_VLUT_51_PMCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_51_PMCNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_51_PMCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_51_PMCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_51_VMIN_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VLUT_51_VMIN_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_51_VMIN_SHIFT)
+#define DVC_VLUT_51_VMIN_RANGE                  9:5
+#define DVC_VLUT_51_VMIN_WOFFSET                        0x0
+#define DVC_VLUT_51_VMIN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_51_VMIN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_51_VMIN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_51_VMIN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_51_VMAX_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VLUT_51_VMAX_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_51_VMAX_SHIFT)
+#define DVC_VLUT_51_VMAX_RANGE                  4:0
+#define DVC_VLUT_51_VMAX_WOFFSET                        0x0
+#define DVC_VLUT_51_VMAX_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_51_VMAX_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_51_VMAX_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_51_VMAX_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_52  
+#define DVC_VLUT_52                     _MK_ADDR_CONST(0x1d0)
+#define DVC_VLUT_52_SECURE                      0x0
+#define DVC_VLUT_52_WORD_COUNT                  0x1
+#define DVC_VLUT_52_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VLUT_52_RESET_MASK                  _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_52_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_52_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_52_READ_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_52_WRITE_MASK                  _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_52_PMCNT_SHIFT                 _MK_SHIFT_CONST(10)
+#define DVC_VLUT_52_PMCNT_FIELD                 (_MK_MASK_CONST(0x3fff) << DVC_VLUT_52_PMCNT_SHIFT)
+#define DVC_VLUT_52_PMCNT_RANGE                 23:10
+#define DVC_VLUT_52_PMCNT_WOFFSET                       0x0
+#define DVC_VLUT_52_PMCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_52_PMCNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_52_PMCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_52_PMCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_52_VMIN_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VLUT_52_VMIN_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_52_VMIN_SHIFT)
+#define DVC_VLUT_52_VMIN_RANGE                  9:5
+#define DVC_VLUT_52_VMIN_WOFFSET                        0x0
+#define DVC_VLUT_52_VMIN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_52_VMIN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_52_VMIN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_52_VMIN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_52_VMAX_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VLUT_52_VMAX_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_52_VMAX_SHIFT)
+#define DVC_VLUT_52_VMAX_RANGE                  4:0
+#define DVC_VLUT_52_VMAX_WOFFSET                        0x0
+#define DVC_VLUT_52_VMAX_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_52_VMAX_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_52_VMAX_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_52_VMAX_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_53  
+#define DVC_VLUT_53                     _MK_ADDR_CONST(0x1d4)
+#define DVC_VLUT_53_SECURE                      0x0
+#define DVC_VLUT_53_WORD_COUNT                  0x1
+#define DVC_VLUT_53_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VLUT_53_RESET_MASK                  _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_53_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_53_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_53_READ_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_53_WRITE_MASK                  _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_53_PMCNT_SHIFT                 _MK_SHIFT_CONST(10)
+#define DVC_VLUT_53_PMCNT_FIELD                 (_MK_MASK_CONST(0x3fff) << DVC_VLUT_53_PMCNT_SHIFT)
+#define DVC_VLUT_53_PMCNT_RANGE                 23:10
+#define DVC_VLUT_53_PMCNT_WOFFSET                       0x0
+#define DVC_VLUT_53_PMCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_53_PMCNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_53_PMCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_53_PMCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_53_VMIN_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VLUT_53_VMIN_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_53_VMIN_SHIFT)
+#define DVC_VLUT_53_VMIN_RANGE                  9:5
+#define DVC_VLUT_53_VMIN_WOFFSET                        0x0
+#define DVC_VLUT_53_VMIN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_53_VMIN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_53_VMIN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_53_VMIN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_53_VMAX_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VLUT_53_VMAX_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_53_VMAX_SHIFT)
+#define DVC_VLUT_53_VMAX_RANGE                  4:0
+#define DVC_VLUT_53_VMAX_WOFFSET                        0x0
+#define DVC_VLUT_53_VMAX_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_53_VMAX_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_53_VMAX_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_53_VMAX_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_54  
+#define DVC_VLUT_54                     _MK_ADDR_CONST(0x1d8)
+#define DVC_VLUT_54_SECURE                      0x0
+#define DVC_VLUT_54_WORD_COUNT                  0x1
+#define DVC_VLUT_54_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VLUT_54_RESET_MASK                  _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_54_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_54_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_54_READ_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_54_WRITE_MASK                  _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_54_PMCNT_SHIFT                 _MK_SHIFT_CONST(10)
+#define DVC_VLUT_54_PMCNT_FIELD                 (_MK_MASK_CONST(0x3fff) << DVC_VLUT_54_PMCNT_SHIFT)
+#define DVC_VLUT_54_PMCNT_RANGE                 23:10
+#define DVC_VLUT_54_PMCNT_WOFFSET                       0x0
+#define DVC_VLUT_54_PMCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_54_PMCNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_54_PMCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_54_PMCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_54_VMIN_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VLUT_54_VMIN_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_54_VMIN_SHIFT)
+#define DVC_VLUT_54_VMIN_RANGE                  9:5
+#define DVC_VLUT_54_VMIN_WOFFSET                        0x0
+#define DVC_VLUT_54_VMIN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_54_VMIN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_54_VMIN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_54_VMIN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_54_VMAX_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VLUT_54_VMAX_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_54_VMAX_SHIFT)
+#define DVC_VLUT_54_VMAX_RANGE                  4:0
+#define DVC_VLUT_54_VMAX_WOFFSET                        0x0
+#define DVC_VLUT_54_VMAX_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_54_VMAX_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_54_VMAX_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_54_VMAX_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_55  
+#define DVC_VLUT_55                     _MK_ADDR_CONST(0x1dc)
+#define DVC_VLUT_55_SECURE                      0x0
+#define DVC_VLUT_55_WORD_COUNT                  0x1
+#define DVC_VLUT_55_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VLUT_55_RESET_MASK                  _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_55_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_55_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_55_READ_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_55_WRITE_MASK                  _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_55_PMCNT_SHIFT                 _MK_SHIFT_CONST(10)
+#define DVC_VLUT_55_PMCNT_FIELD                 (_MK_MASK_CONST(0x3fff) << DVC_VLUT_55_PMCNT_SHIFT)
+#define DVC_VLUT_55_PMCNT_RANGE                 23:10
+#define DVC_VLUT_55_PMCNT_WOFFSET                       0x0
+#define DVC_VLUT_55_PMCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_55_PMCNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_55_PMCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_55_PMCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_55_VMIN_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VLUT_55_VMIN_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_55_VMIN_SHIFT)
+#define DVC_VLUT_55_VMIN_RANGE                  9:5
+#define DVC_VLUT_55_VMIN_WOFFSET                        0x0
+#define DVC_VLUT_55_VMIN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_55_VMIN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_55_VMIN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_55_VMIN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_55_VMAX_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VLUT_55_VMAX_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_55_VMAX_SHIFT)
+#define DVC_VLUT_55_VMAX_RANGE                  4:0
+#define DVC_VLUT_55_VMAX_WOFFSET                        0x0
+#define DVC_VLUT_55_VMAX_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_55_VMAX_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_55_VMAX_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_55_VMAX_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_56  
+#define DVC_VLUT_56                     _MK_ADDR_CONST(0x1e0)
+#define DVC_VLUT_56_SECURE                      0x0
+#define DVC_VLUT_56_WORD_COUNT                  0x1
+#define DVC_VLUT_56_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VLUT_56_RESET_MASK                  _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_56_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_56_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_56_READ_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_56_WRITE_MASK                  _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_56_PMCNT_SHIFT                 _MK_SHIFT_CONST(10)
+#define DVC_VLUT_56_PMCNT_FIELD                 (_MK_MASK_CONST(0x3fff) << DVC_VLUT_56_PMCNT_SHIFT)
+#define DVC_VLUT_56_PMCNT_RANGE                 23:10
+#define DVC_VLUT_56_PMCNT_WOFFSET                       0x0
+#define DVC_VLUT_56_PMCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_56_PMCNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_56_PMCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_56_PMCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_56_VMIN_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VLUT_56_VMIN_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_56_VMIN_SHIFT)
+#define DVC_VLUT_56_VMIN_RANGE                  9:5
+#define DVC_VLUT_56_VMIN_WOFFSET                        0x0
+#define DVC_VLUT_56_VMIN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_56_VMIN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_56_VMIN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_56_VMIN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_56_VMAX_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VLUT_56_VMAX_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_56_VMAX_SHIFT)
+#define DVC_VLUT_56_VMAX_RANGE                  4:0
+#define DVC_VLUT_56_VMAX_WOFFSET                        0x0
+#define DVC_VLUT_56_VMAX_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_56_VMAX_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_56_VMAX_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_56_VMAX_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_57  
+#define DVC_VLUT_57                     _MK_ADDR_CONST(0x1e4)
+#define DVC_VLUT_57_SECURE                      0x0
+#define DVC_VLUT_57_WORD_COUNT                  0x1
+#define DVC_VLUT_57_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VLUT_57_RESET_MASK                  _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_57_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_57_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_57_READ_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_57_WRITE_MASK                  _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_57_PMCNT_SHIFT                 _MK_SHIFT_CONST(10)
+#define DVC_VLUT_57_PMCNT_FIELD                 (_MK_MASK_CONST(0x3fff) << DVC_VLUT_57_PMCNT_SHIFT)
+#define DVC_VLUT_57_PMCNT_RANGE                 23:10
+#define DVC_VLUT_57_PMCNT_WOFFSET                       0x0
+#define DVC_VLUT_57_PMCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_57_PMCNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_57_PMCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_57_PMCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_57_VMIN_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VLUT_57_VMIN_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_57_VMIN_SHIFT)
+#define DVC_VLUT_57_VMIN_RANGE                  9:5
+#define DVC_VLUT_57_VMIN_WOFFSET                        0x0
+#define DVC_VLUT_57_VMIN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_57_VMIN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_57_VMIN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_57_VMIN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_57_VMAX_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VLUT_57_VMAX_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_57_VMAX_SHIFT)
+#define DVC_VLUT_57_VMAX_RANGE                  4:0
+#define DVC_VLUT_57_VMAX_WOFFSET                        0x0
+#define DVC_VLUT_57_VMAX_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_57_VMAX_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_57_VMAX_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_57_VMAX_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_58  
+#define DVC_VLUT_58                     _MK_ADDR_CONST(0x1e8)
+#define DVC_VLUT_58_SECURE                      0x0
+#define DVC_VLUT_58_WORD_COUNT                  0x1
+#define DVC_VLUT_58_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VLUT_58_RESET_MASK                  _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_58_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_58_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_58_READ_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_58_WRITE_MASK                  _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_58_PMCNT_SHIFT                 _MK_SHIFT_CONST(10)
+#define DVC_VLUT_58_PMCNT_FIELD                 (_MK_MASK_CONST(0x3fff) << DVC_VLUT_58_PMCNT_SHIFT)
+#define DVC_VLUT_58_PMCNT_RANGE                 23:10
+#define DVC_VLUT_58_PMCNT_WOFFSET                       0x0
+#define DVC_VLUT_58_PMCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_58_PMCNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_58_PMCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_58_PMCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_58_VMIN_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VLUT_58_VMIN_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_58_VMIN_SHIFT)
+#define DVC_VLUT_58_VMIN_RANGE                  9:5
+#define DVC_VLUT_58_VMIN_WOFFSET                        0x0
+#define DVC_VLUT_58_VMIN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_58_VMIN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_58_VMIN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_58_VMIN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_58_VMAX_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VLUT_58_VMAX_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_58_VMAX_SHIFT)
+#define DVC_VLUT_58_VMAX_RANGE                  4:0
+#define DVC_VLUT_58_VMAX_WOFFSET                        0x0
+#define DVC_VLUT_58_VMAX_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_58_VMAX_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_58_VMAX_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_58_VMAX_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_59  
+#define DVC_VLUT_59                     _MK_ADDR_CONST(0x1ec)
+#define DVC_VLUT_59_SECURE                      0x0
+#define DVC_VLUT_59_WORD_COUNT                  0x1
+#define DVC_VLUT_59_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VLUT_59_RESET_MASK                  _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_59_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_59_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_59_READ_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_59_WRITE_MASK                  _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_59_PMCNT_SHIFT                 _MK_SHIFT_CONST(10)
+#define DVC_VLUT_59_PMCNT_FIELD                 (_MK_MASK_CONST(0x3fff) << DVC_VLUT_59_PMCNT_SHIFT)
+#define DVC_VLUT_59_PMCNT_RANGE                 23:10
+#define DVC_VLUT_59_PMCNT_WOFFSET                       0x0
+#define DVC_VLUT_59_PMCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_59_PMCNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_59_PMCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_59_PMCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_59_VMIN_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VLUT_59_VMIN_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_59_VMIN_SHIFT)
+#define DVC_VLUT_59_VMIN_RANGE                  9:5
+#define DVC_VLUT_59_VMIN_WOFFSET                        0x0
+#define DVC_VLUT_59_VMIN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_59_VMIN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_59_VMIN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_59_VMIN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_59_VMAX_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VLUT_59_VMAX_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_59_VMAX_SHIFT)
+#define DVC_VLUT_59_VMAX_RANGE                  4:0
+#define DVC_VLUT_59_VMAX_WOFFSET                        0x0
+#define DVC_VLUT_59_VMAX_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_59_VMAX_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_59_VMAX_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_59_VMAX_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_60  
+#define DVC_VLUT_60                     _MK_ADDR_CONST(0x1f0)
+#define DVC_VLUT_60_SECURE                      0x0
+#define DVC_VLUT_60_WORD_COUNT                  0x1
+#define DVC_VLUT_60_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VLUT_60_RESET_MASK                  _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_60_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_60_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_60_READ_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_60_WRITE_MASK                  _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_60_PMCNT_SHIFT                 _MK_SHIFT_CONST(10)
+#define DVC_VLUT_60_PMCNT_FIELD                 (_MK_MASK_CONST(0x3fff) << DVC_VLUT_60_PMCNT_SHIFT)
+#define DVC_VLUT_60_PMCNT_RANGE                 23:10
+#define DVC_VLUT_60_PMCNT_WOFFSET                       0x0
+#define DVC_VLUT_60_PMCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_60_PMCNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_60_PMCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_60_PMCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_60_VMIN_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VLUT_60_VMIN_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_60_VMIN_SHIFT)
+#define DVC_VLUT_60_VMIN_RANGE                  9:5
+#define DVC_VLUT_60_VMIN_WOFFSET                        0x0
+#define DVC_VLUT_60_VMIN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_60_VMIN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_60_VMIN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_60_VMIN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_60_VMAX_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VLUT_60_VMAX_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_60_VMAX_SHIFT)
+#define DVC_VLUT_60_VMAX_RANGE                  4:0
+#define DVC_VLUT_60_VMAX_WOFFSET                        0x0
+#define DVC_VLUT_60_VMAX_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_60_VMAX_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_60_VMAX_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_60_VMAX_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_61  
+#define DVC_VLUT_61                     _MK_ADDR_CONST(0x1f4)
+#define DVC_VLUT_61_SECURE                      0x0
+#define DVC_VLUT_61_WORD_COUNT                  0x1
+#define DVC_VLUT_61_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VLUT_61_RESET_MASK                  _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_61_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_61_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_61_READ_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_61_WRITE_MASK                  _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_61_PMCNT_SHIFT                 _MK_SHIFT_CONST(10)
+#define DVC_VLUT_61_PMCNT_FIELD                 (_MK_MASK_CONST(0x3fff) << DVC_VLUT_61_PMCNT_SHIFT)
+#define DVC_VLUT_61_PMCNT_RANGE                 23:10
+#define DVC_VLUT_61_PMCNT_WOFFSET                       0x0
+#define DVC_VLUT_61_PMCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_61_PMCNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_61_PMCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_61_PMCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_61_VMIN_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VLUT_61_VMIN_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_61_VMIN_SHIFT)
+#define DVC_VLUT_61_VMIN_RANGE                  9:5
+#define DVC_VLUT_61_VMIN_WOFFSET                        0x0
+#define DVC_VLUT_61_VMIN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_61_VMIN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_61_VMIN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_61_VMIN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_61_VMAX_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VLUT_61_VMAX_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_61_VMAX_SHIFT)
+#define DVC_VLUT_61_VMAX_RANGE                  4:0
+#define DVC_VLUT_61_VMAX_WOFFSET                        0x0
+#define DVC_VLUT_61_VMAX_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_61_VMAX_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_61_VMAX_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_61_VMAX_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_62  
+#define DVC_VLUT_62                     _MK_ADDR_CONST(0x1f8)
+#define DVC_VLUT_62_SECURE                      0x0
+#define DVC_VLUT_62_WORD_COUNT                  0x1
+#define DVC_VLUT_62_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VLUT_62_RESET_MASK                  _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_62_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_62_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_62_READ_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_62_WRITE_MASK                  _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_62_PMCNT_SHIFT                 _MK_SHIFT_CONST(10)
+#define DVC_VLUT_62_PMCNT_FIELD                 (_MK_MASK_CONST(0x3fff) << DVC_VLUT_62_PMCNT_SHIFT)
+#define DVC_VLUT_62_PMCNT_RANGE                 23:10
+#define DVC_VLUT_62_PMCNT_WOFFSET                       0x0
+#define DVC_VLUT_62_PMCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_62_PMCNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_62_PMCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_62_PMCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_62_VMIN_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VLUT_62_VMIN_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_62_VMIN_SHIFT)
+#define DVC_VLUT_62_VMIN_RANGE                  9:5
+#define DVC_VLUT_62_VMIN_WOFFSET                        0x0
+#define DVC_VLUT_62_VMIN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_62_VMIN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_62_VMIN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_62_VMIN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_62_VMAX_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VLUT_62_VMAX_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_62_VMAX_SHIFT)
+#define DVC_VLUT_62_VMAX_RANGE                  4:0
+#define DVC_VLUT_62_VMAX_WOFFSET                        0x0
+#define DVC_VLUT_62_VMAX_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_62_VMAX_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_62_VMAX_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_62_VMAX_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_63  
+#define DVC_VLUT_63                     _MK_ADDR_CONST(0x1fc)
+#define DVC_VLUT_63_SECURE                      0x0
+#define DVC_VLUT_63_WORD_COUNT                  0x1
+#define DVC_VLUT_63_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VLUT_63_RESET_MASK                  _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_63_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_63_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_63_READ_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_63_WRITE_MASK                  _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_63_PMCNT_SHIFT                 _MK_SHIFT_CONST(10)
+#define DVC_VLUT_63_PMCNT_FIELD                 (_MK_MASK_CONST(0x3fff) << DVC_VLUT_63_PMCNT_SHIFT)
+#define DVC_VLUT_63_PMCNT_RANGE                 23:10
+#define DVC_VLUT_63_PMCNT_WOFFSET                       0x0
+#define DVC_VLUT_63_PMCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_63_PMCNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_63_PMCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_63_PMCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_63_VMIN_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VLUT_63_VMIN_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_63_VMIN_SHIFT)
+#define DVC_VLUT_63_VMIN_RANGE                  9:5
+#define DVC_VLUT_63_VMIN_WOFFSET                        0x0
+#define DVC_VLUT_63_VMIN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_63_VMIN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_63_VMIN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_63_VMIN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_63_VMAX_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VLUT_63_VMAX_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_63_VMAX_SHIFT)
+#define DVC_VLUT_63_VMAX_RANGE                  4:0
+#define DVC_VLUT_63_VMAX_WOFFSET                        0x0
+#define DVC_VLUT_63_VMAX_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_63_VMAX_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_63_VMAX_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_63_VMAX_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+//
+// REGISTER LIST
+//
+#define LIST_ARDVC_REGS(_op_) \
+_op_(DVC_CTRL_REG1_0) \
+_op_(DVC_CTRL_REG2_0) \
+_op_(DVC_CTRL_REG3_0) \
+_op_(DVC_STATUS_REG_0) \
+_op_(DVC_I2C_CTRL_REG_0) \
+_op_(DVC_I2C_ADDR_DATA_REG_0) \
+_op_(DVC_RING_OSC_ADDER_IN1_0) \
+_op_(DVC_RING_OSC_ADDER_IN2_0) \
+_op_(DVC_REQ_REGISTER_0) \
+_op_(DVC_I2C_ADDR_DATA_REG_3_0) \
+_op_(DVC_I2C_CNFG_0) \
+_op_(DVC_I2C_CMD_ADDR0_0) \
+_op_(DVC_I2C_CMD_ADDR1_0) \
+_op_(DVC_I2C_CMD_DATA1_0) \
+_op_(DVC_I2C_CMD_DATA2_0) \
+_op_(DVC_I2C_STATUS_0) \
+_op_(DVC_I2C_TX_PACKET_FIFO_0) \
+_op_(DVC_I2C_RX_FIFO_0) \
+_op_(DVC_PACKET_TRANSFER_STATUS_0) \
+_op_(DVC_FIFO_CONTROL_0) \
+_op_(DVC_FIFO_STATUS_0) \
+_op_(DVC_INTERRUPT_MASK_REGISTER_0) \
+_op_(DVC_INTERRUPT_STATUS_REGISTER_0) \
+_op_(DVC_I2C_CLK_DIVISOR_REGISTER_0) \
+_op_(DVC_VSEL_MAP_LUT_0) \
+_op_(DVC_VSEL_MAP_LUT) \
+_op_(DVC_VSEL_MAP_LUT_1) \
+_op_(DVC_VSEL_MAP_LUT_2) \
+_op_(DVC_VSEL_MAP_LUT_3) \
+_op_(DVC_VSEL_MAP_LUT_4) \
+_op_(DVC_VSEL_MAP_LUT_5) \
+_op_(DVC_VSEL_MAP_LUT_6) \
+_op_(DVC_VSEL_MAP_LUT_7) \
+_op_(DVC_VSEL_MAP_LUT_8) \
+_op_(DVC_VSEL_MAP_LUT_9) \
+_op_(DVC_VSEL_MAP_LUT_10) \
+_op_(DVC_VSEL_MAP_LUT_11) \
+_op_(DVC_VSEL_MAP_LUT_12) \
+_op_(DVC_VSEL_MAP_LUT_13) \
+_op_(DVC_VSEL_MAP_LUT_14) \
+_op_(DVC_VSEL_MAP_LUT_15) \
+_op_(DVC_VSEL_MAP_LUT_16) \
+_op_(DVC_VSEL_MAP_LUT_17) \
+_op_(DVC_VSEL_MAP_LUT_18) \
+_op_(DVC_VSEL_MAP_LUT_19) \
+_op_(DVC_VSEL_MAP_LUT_20) \
+_op_(DVC_VSEL_MAP_LUT_21) \
+_op_(DVC_VSEL_MAP_LUT_22) \
+_op_(DVC_VSEL_MAP_LUT_23) \
+_op_(DVC_VSEL_MAP_LUT_24) \
+_op_(DVC_VSEL_MAP_LUT_25) \
+_op_(DVC_VSEL_MAP_LUT_26) \
+_op_(DVC_VSEL_MAP_LUT_27) \
+_op_(DVC_VSEL_MAP_LUT_28) \
+_op_(DVC_VSEL_MAP_LUT_29) \
+_op_(DVC_VSEL_MAP_LUT_30) \
+_op_(DVC_VSEL_MAP_LUT_31) \
+_op_(DVC_VLUT_0) \
+_op_(DVC_VLUT) \
+_op_(DVC_VLUT_1) \
+_op_(DVC_VLUT_2) \
+_op_(DVC_VLUT_3) \
+_op_(DVC_VLUT_4) \
+_op_(DVC_VLUT_5) \
+_op_(DVC_VLUT_6) \
+_op_(DVC_VLUT_7) \
+_op_(DVC_VLUT_8) \
+_op_(DVC_VLUT_9) \
+_op_(DVC_VLUT_10) \
+_op_(DVC_VLUT_11) \
+_op_(DVC_VLUT_12) \
+_op_(DVC_VLUT_13) \
+_op_(DVC_VLUT_14) \
+_op_(DVC_VLUT_15) \
+_op_(DVC_VLUT_16) \
+_op_(DVC_VLUT_17) \
+_op_(DVC_VLUT_18) \
+_op_(DVC_VLUT_19) \
+_op_(DVC_VLUT_20) \
+_op_(DVC_VLUT_21) \
+_op_(DVC_VLUT_22) \
+_op_(DVC_VLUT_23) \
+_op_(DVC_VLUT_24) \
+_op_(DVC_VLUT_25) \
+_op_(DVC_VLUT_26) \
+_op_(DVC_VLUT_27) \
+_op_(DVC_VLUT_28) \
+_op_(DVC_VLUT_29) \
+_op_(DVC_VLUT_30) \
+_op_(DVC_VLUT_31) \
+_op_(DVC_VLUT_32) \
+_op_(DVC_VLUT_33) \
+_op_(DVC_VLUT_34) \
+_op_(DVC_VLUT_35) \
+_op_(DVC_VLUT_36) \
+_op_(DVC_VLUT_37) \
+_op_(DVC_VLUT_38) \
+_op_(DVC_VLUT_39) \
+_op_(DVC_VLUT_40) \
+_op_(DVC_VLUT_41) \
+_op_(DVC_VLUT_42) \
+_op_(DVC_VLUT_43) \
+_op_(DVC_VLUT_44) \
+_op_(DVC_VLUT_45) \
+_op_(DVC_VLUT_46) \
+_op_(DVC_VLUT_47) \
+_op_(DVC_VLUT_48) \
+_op_(DVC_VLUT_49) \
+_op_(DVC_VLUT_50) \
+_op_(DVC_VLUT_51) \
+_op_(DVC_VLUT_52) \
+_op_(DVC_VLUT_53) \
+_op_(DVC_VLUT_54) \
+_op_(DVC_VLUT_55) \
+_op_(DVC_VLUT_56) \
+_op_(DVC_VLUT_57) \
+_op_(DVC_VLUT_58) \
+_op_(DVC_VLUT_59) \
+_op_(DVC_VLUT_60) \
+_op_(DVC_VLUT_61) \
+_op_(DVC_VLUT_62) \
+_op_(DVC_VLUT_63)
+
+
+//
+// ADDRESS SPACES
+//
+
+#define BASE_ADDRESS_DVC        0x00000000
+
+//
+// ARDVC REGISTER BANKS
+//
+
+#define DVC0_FIRST_REG 0x0000 // DVC_CTRL_REG1_0
+#define DVC0_LAST_REG 0x0024 // DVC_I2C_ADDR_DATA_REG_3_0
+#define DVC1_FIRST_REG 0x0040 // DVC_I2C_CNFG_0
+#define DVC1_LAST_REG 0x0050 // DVC_I2C_CMD_DATA2_0
+#define DVC2_FIRST_REG 0x005c // DVC_I2C_STATUS_0
+#define DVC2_LAST_REG 0x01fc // DVC_VLUT_63
+
+#ifndef _MK_SHIFT_CONST
+  #define _MK_SHIFT_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_MASK_CONST
+  #define _MK_MASK_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_ENUM_CONST
+  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
+#endif
+#ifndef _MK_ADDR_CONST
+  #define _MK_ADDR_CONST(_constant_) _constant_
+#endif
+
+#endif // ifndef ___ARDVC_H_INC_
diff --git a/arch/arm/mach-tegra/include/ap20/aremc.h b/arch/arm/mach-tegra/include/ap20/aremc.h
new file mode 100644
index 000000000000..cc6d52b2e045
--- /dev/null
+++ b/arch/arm/mach-tegra/include/ap20/aremc.h
@@ -0,0 +1,7271 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+//
+// DO NOT EDIT - generated by simspec!
+//
+
+#ifndef ___AREMC_H_INC_
+#define ___AREMC_H_INC_
+#define EMC_FBIO_DATA_MAX       31
+#define EMC_FBIO_DATA_WIDTH     32
+#define EMC_FBIO_DOE_MAX        3
+#define EMC_FBIO_DOE_WIDTH      4
+#define MAX_EMC_TIMING_WDV      15
+
+// Register EMC_INTSTATUS_0  // Interrupt Status Register.
+#define EMC_INTSTATUS_0                 _MK_ADDR_CONST(0x0)
+#define EMC_INTSTATUS_0_SECURE                  0x0
+#define EMC_INTSTATUS_0_WORD_COUNT                      0x1
+#define EMC_INTSTATUS_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define EMC_INTSTATUS_0_RESET_MASK                      _MK_MASK_CONST(0x38)
+#define EMC_INTSTATUS_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EMC_INTSTATUS_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_INTSTATUS_0_READ_MASK                       _MK_MASK_CONST(0x38)
+#define EMC_INTSTATUS_0_WRITE_MASK                      _MK_MASK_CONST(0x38)
+// Refresh request overflow timeout.
+#define EMC_INTSTATUS_0_REFRESH_OVERFLOW_INT_SHIFT                      _MK_SHIFT_CONST(3)
+#define EMC_INTSTATUS_0_REFRESH_OVERFLOW_INT_FIELD                      (_MK_MASK_CONST(0x1) << EMC_INTSTATUS_0_REFRESH_OVERFLOW_INT_SHIFT)
+#define EMC_INTSTATUS_0_REFRESH_OVERFLOW_INT_RANGE                      3:3
+#define EMC_INTSTATUS_0_REFRESH_OVERFLOW_INT_WOFFSET                    0x0
+#define EMC_INTSTATUS_0_REFRESH_OVERFLOW_INT_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_INTSTATUS_0_REFRESH_OVERFLOW_INT_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define EMC_INTSTATUS_0_REFRESH_OVERFLOW_INT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_INTSTATUS_0_REFRESH_OVERFLOW_INT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_INTSTATUS_0_REFRESH_OVERFLOW_INT_INIT_ENUM                  CLEAR
+#define EMC_INTSTATUS_0_REFRESH_OVERFLOW_INT_CLEAR                      _MK_ENUM_CONST(0)
+#define EMC_INTSTATUS_0_REFRESH_OVERFLOW_INT_SET                        _MK_ENUM_CONST(1)
+
+// CAR/EMC clock-change handshake complete.
+#define EMC_INTSTATUS_0_CLKCHANGE_COMPLETE_INT_SHIFT                    _MK_SHIFT_CONST(4)
+#define EMC_INTSTATUS_0_CLKCHANGE_COMPLETE_INT_FIELD                    (_MK_MASK_CONST(0x1) << EMC_INTSTATUS_0_CLKCHANGE_COMPLETE_INT_SHIFT)
+#define EMC_INTSTATUS_0_CLKCHANGE_COMPLETE_INT_RANGE                    4:4
+#define EMC_INTSTATUS_0_CLKCHANGE_COMPLETE_INT_WOFFSET                  0x0
+#define EMC_INTSTATUS_0_CLKCHANGE_COMPLETE_INT_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_INTSTATUS_0_CLKCHANGE_COMPLETE_INT_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define EMC_INTSTATUS_0_CLKCHANGE_COMPLETE_INT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_INTSTATUS_0_CLKCHANGE_COMPLETE_INT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_INTSTATUS_0_CLKCHANGE_COMPLETE_INT_INIT_ENUM                        CLEAR
+#define EMC_INTSTATUS_0_CLKCHANGE_COMPLETE_INT_CLEAR                    _MK_ENUM_CONST(0)
+#define EMC_INTSTATUS_0_CLKCHANGE_COMPLETE_INT_SET                      _MK_ENUM_CONST(1)
+
+// LPDDR2 MRR data is available to be read.
+#define EMC_INTSTATUS_0_MRR_DIVLD_INT_SHIFT                     _MK_SHIFT_CONST(5)
+#define EMC_INTSTATUS_0_MRR_DIVLD_INT_FIELD                     (_MK_MASK_CONST(0x1) << EMC_INTSTATUS_0_MRR_DIVLD_INT_SHIFT)
+#define EMC_INTSTATUS_0_MRR_DIVLD_INT_RANGE                     5:5
+#define EMC_INTSTATUS_0_MRR_DIVLD_INT_WOFFSET                   0x0
+#define EMC_INTSTATUS_0_MRR_DIVLD_INT_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_INTSTATUS_0_MRR_DIVLD_INT_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define EMC_INTSTATUS_0_MRR_DIVLD_INT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_INTSTATUS_0_MRR_DIVLD_INT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_INTSTATUS_0_MRR_DIVLD_INT_INIT_ENUM                 CLEAR
+#define EMC_INTSTATUS_0_MRR_DIVLD_INT_CLEAR                     _MK_ENUM_CONST(0)
+#define EMC_INTSTATUS_0_MRR_DIVLD_INT_SET                       _MK_ENUM_CONST(1)
+
+
+// Register EMC_INTMASK_0  // Interrupt Mask Register. 
+#define EMC_INTMASK_0                   _MK_ADDR_CONST(0x4)
+#define EMC_INTMASK_0_SECURE                    0x0
+#define EMC_INTMASK_0_WORD_COUNT                        0x1
+#define EMC_INTMASK_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define EMC_INTMASK_0_RESET_MASK                        _MK_MASK_CONST(0x38)
+#define EMC_INTMASK_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define EMC_INTMASK_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_INTMASK_0_READ_MASK                         _MK_MASK_CONST(0x38)
+#define EMC_INTMASK_0_WRITE_MASK                        _MK_MASK_CONST(0x38)
+// Mask for refresh request overflow timeout.
+#define EMC_INTMASK_0_REFRESH_OVERFLOW_INTMASK_SHIFT                    _MK_SHIFT_CONST(3)
+#define EMC_INTMASK_0_REFRESH_OVERFLOW_INTMASK_FIELD                    (_MK_MASK_CONST(0x1) << EMC_INTMASK_0_REFRESH_OVERFLOW_INTMASK_SHIFT)
+#define EMC_INTMASK_0_REFRESH_OVERFLOW_INTMASK_RANGE                    3:3
+#define EMC_INTMASK_0_REFRESH_OVERFLOW_INTMASK_WOFFSET                  0x0
+#define EMC_INTMASK_0_REFRESH_OVERFLOW_INTMASK_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_INTMASK_0_REFRESH_OVERFLOW_INTMASK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define EMC_INTMASK_0_REFRESH_OVERFLOW_INTMASK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_INTMASK_0_REFRESH_OVERFLOW_INTMASK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_INTMASK_0_REFRESH_OVERFLOW_INTMASK_INIT_ENUM                        MASKED
+#define EMC_INTMASK_0_REFRESH_OVERFLOW_INTMASK_MASKED                   _MK_ENUM_CONST(0)
+#define EMC_INTMASK_0_REFRESH_OVERFLOW_INTMASK_UNMASKED                 _MK_ENUM_CONST(1)
+
+// Mask for CAR/EMC clock-change handshake complete.
+#define EMC_INTMASK_0_CLKCHANGE_COMPLETE_INTMASK_SHIFT                  _MK_SHIFT_CONST(4)
+#define EMC_INTMASK_0_CLKCHANGE_COMPLETE_INTMASK_FIELD                  (_MK_MASK_CONST(0x1) << EMC_INTMASK_0_CLKCHANGE_COMPLETE_INTMASK_SHIFT)
+#define EMC_INTMASK_0_CLKCHANGE_COMPLETE_INTMASK_RANGE                  4:4
+#define EMC_INTMASK_0_CLKCHANGE_COMPLETE_INTMASK_WOFFSET                        0x0
+#define EMC_INTMASK_0_CLKCHANGE_COMPLETE_INTMASK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_INTMASK_0_CLKCHANGE_COMPLETE_INTMASK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define EMC_INTMASK_0_CLKCHANGE_COMPLETE_INTMASK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_INTMASK_0_CLKCHANGE_COMPLETE_INTMASK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_INTMASK_0_CLKCHANGE_COMPLETE_INTMASK_INIT_ENUM                      MASKED
+#define EMC_INTMASK_0_CLKCHANGE_COMPLETE_INTMASK_MASKED                 _MK_ENUM_CONST(0)
+#define EMC_INTMASK_0_CLKCHANGE_COMPLETE_INTMASK_UNMASKED                       _MK_ENUM_CONST(1)
+
+// Mask for MRR data available.
+#define EMC_INTMASK_0_MRR_DIVLD_INTMASK_SHIFT                   _MK_SHIFT_CONST(5)
+#define EMC_INTMASK_0_MRR_DIVLD_INTMASK_FIELD                   (_MK_MASK_CONST(0x1) << EMC_INTMASK_0_MRR_DIVLD_INTMASK_SHIFT)
+#define EMC_INTMASK_0_MRR_DIVLD_INTMASK_RANGE                   5:5
+#define EMC_INTMASK_0_MRR_DIVLD_INTMASK_WOFFSET                 0x0
+#define EMC_INTMASK_0_MRR_DIVLD_INTMASK_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_INTMASK_0_MRR_DIVLD_INTMASK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define EMC_INTMASK_0_MRR_DIVLD_INTMASK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_INTMASK_0_MRR_DIVLD_INTMASK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define EMC_INTMASK_0_MRR_DIVLD_INTMASK_INIT_ENUM                       MASKED
+#define EMC_INTMASK_0_MRR_DIVLD_INTMASK_MASKED                  _MK_ENUM_CONST(0)
+#define EMC_INTMASK_0_MRR_DIVLD_INTMASK_UNMASKED                        _MK_ENUM_CONST(1)
+
+
+// Register EMC_DBG_0  // Debug Register
+#define EMC_DBG_0                       _MK_ADDR_CONST(0x8)
+#define EMC_DBG_0_SECURE                        0x0
+#define EMC_DBG_0_WORD_COUNT                    0x1
+#define EMC_DBG_0_RESET_VAL                     _MK_MASK_CONST(0x1000400)
+#define EMC_DBG_0_RESET_MASK                    _MK_MASK_CONST(0x1000637)
+#define EMC_DBG_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define EMC_DBG_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_DBG_0_READ_MASK                     _MK_MASK_CONST(0x1000637)
+#define EMC_DBG_0_WRITE_MASK                    _MK_MASK_CONST(0x1000637)
+// controls whether reads to the configuration registers are done from the assembly or active state.
+#define EMC_DBG_0_READ_MUX_SHIFT                        _MK_SHIFT_CONST(0)
+#define EMC_DBG_0_READ_MUX_FIELD                        (_MK_MASK_CONST(0x1) << EMC_DBG_0_READ_MUX_SHIFT)
+#define EMC_DBG_0_READ_MUX_RANGE                        0:0
+#define EMC_DBG_0_READ_MUX_WOFFSET                      0x0
+#define EMC_DBG_0_READ_MUX_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_DBG_0_READ_MUX_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define EMC_DBG_0_READ_MUX_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_DBG_0_READ_MUX_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_DBG_0_READ_MUX_INIT_ENUM                    ACTIVE
+#define EMC_DBG_0_READ_MUX_ACTIVE                       _MK_ENUM_CONST(0)
+#define EMC_DBG_0_READ_MUX_ASSEMBLY                     _MK_ENUM_CONST(1)
+
+// controls whether writes to the configuration registers are done from the assembly or active state.
+#define EMC_DBG_0_WRITE_MUX_SHIFT                       _MK_SHIFT_CONST(1)
+#define EMC_DBG_0_WRITE_MUX_FIELD                       (_MK_MASK_CONST(0x1) << EMC_DBG_0_WRITE_MUX_SHIFT)
+#define EMC_DBG_0_WRITE_MUX_RANGE                       1:1
+#define EMC_DBG_0_WRITE_MUX_WOFFSET                     0x0
+#define EMC_DBG_0_WRITE_MUX_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_DBG_0_WRITE_MUX_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define EMC_DBG_0_WRITE_MUX_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_DBG_0_WRITE_MUX_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EMC_DBG_0_WRITE_MUX_INIT_ENUM                   ASSEMBLY
+#define EMC_DBG_0_WRITE_MUX_ASSEMBLY                    _MK_ENUM_CONST(0)
+#define EMC_DBG_0_WRITE_MUX_ACTIVE                      _MK_ENUM_CONST(1)
+
+// causes the active state to get updated with the assembly state immediately upon writing the TIMING_CONTROL register.
+#define EMC_DBG_0_FORCE_UPDATE_SHIFT                    _MK_SHIFT_CONST(2)
+#define EMC_DBG_0_FORCE_UPDATE_FIELD                    (_MK_MASK_CONST(0x1) << EMC_DBG_0_FORCE_UPDATE_SHIFT)
+#define EMC_DBG_0_FORCE_UPDATE_RANGE                    2:2
+#define EMC_DBG_0_FORCE_UPDATE_WOFFSET                  0x0
+#define EMC_DBG_0_FORCE_UPDATE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_DBG_0_FORCE_UPDATE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define EMC_DBG_0_FORCE_UPDATE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_DBG_0_FORCE_UPDATE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_DBG_0_FORCE_UPDATE_INIT_ENUM                        DISABLED
+#define EMC_DBG_0_FORCE_UPDATE_DISABLED                 _MK_ENUM_CONST(0)
+#define EMC_DBG_0_FORCE_UPDATE_ENABLED                  _MK_ENUM_CONST(1)
+
+// should be set to MRS_256 when a non-mobile DRAM is used because they require a 200 cycle
+// delay between the DLL reset and any read commands.
+#define EMC_DBG_0_MRS_WAIT_SHIFT                        _MK_SHIFT_CONST(4)
+#define EMC_DBG_0_MRS_WAIT_FIELD                        (_MK_MASK_CONST(0x1) << EMC_DBG_0_MRS_WAIT_SHIFT)
+#define EMC_DBG_0_MRS_WAIT_RANGE                        4:4
+#define EMC_DBG_0_MRS_WAIT_WOFFSET                      0x0
+#define EMC_DBG_0_MRS_WAIT_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_DBG_0_MRS_WAIT_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define EMC_DBG_0_MRS_WAIT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_DBG_0_MRS_WAIT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_DBG_0_MRS_WAIT_INIT_ENUM                    MRS_2
+#define EMC_DBG_0_MRS_WAIT_MRS_2                        _MK_ENUM_CONST(0)
+#define EMC_DBG_0_MRS_WAIT_MRS_256                      _MK_ENUM_CONST(1)
+
+// specifies whether or not to periodic reset the FBIO read-data fifo during normal operation.
+// The periodic resets can be used for graceful recovery from an intermittent failure condition;
+// only the initial reset is absolutely required.
+#define EMC_DBG_0_PERIODIC_QRST_SHIFT                   _MK_SHIFT_CONST(5)
+#define EMC_DBG_0_PERIODIC_QRST_FIELD                   (_MK_MASK_CONST(0x1) << EMC_DBG_0_PERIODIC_QRST_SHIFT)
+#define EMC_DBG_0_PERIODIC_QRST_RANGE                   5:5
+#define EMC_DBG_0_PERIODIC_QRST_WOFFSET                 0x0
+#define EMC_DBG_0_PERIODIC_QRST_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_DBG_0_PERIODIC_QRST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define EMC_DBG_0_PERIODIC_QRST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_DBG_0_PERIODIC_QRST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define EMC_DBG_0_PERIODIC_QRST_INIT_ENUM                       DISABLED
+#define EMC_DBG_0_PERIODIC_QRST_DISABLED                        _MK_ENUM_CONST(0)
+#define EMC_DBG_0_PERIODIC_QRST_ENABLED                 _MK_ENUM_CONST(1)
+
+// controls whether the dqm signals during reads are managed for power (not relevant for DDR).
+// If set to MANAGED, EMC only turns them on when necessary.  If set to ALWAYS_ON, the dqm signals are
+// enabled during non-write operation.
+#define EMC_DBG_0_READ_DQM_CTRL_SHIFT                   _MK_SHIFT_CONST(9)
+#define EMC_DBG_0_READ_DQM_CTRL_FIELD                   (_MK_MASK_CONST(0x1) << EMC_DBG_0_READ_DQM_CTRL_SHIFT)
+#define EMC_DBG_0_READ_DQM_CTRL_RANGE                   9:9
+#define EMC_DBG_0_READ_DQM_CTRL_WOFFSET                 0x0
+#define EMC_DBG_0_READ_DQM_CTRL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_DBG_0_READ_DQM_CTRL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define EMC_DBG_0_READ_DQM_CTRL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_DBG_0_READ_DQM_CTRL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define EMC_DBG_0_READ_DQM_CTRL_INIT_ENUM                       MANAGED
+#define EMC_DBG_0_READ_DQM_CTRL_MANAGED                 _MK_ENUM_CONST(0)
+#define EMC_DBG_0_READ_DQM_CTRL_ALWAYS_ON                       _MK_ENUM_CONST(1)
+
+// determines whether the busy signal from the auto-precharge cancellation (APC) fifo
+// is allowed to stall requests to the EMC.
+#define EMC_DBG_0_AP_REQ_BUSY_CTRL_SHIFT                        _MK_SHIFT_CONST(10)
+#define EMC_DBG_0_AP_REQ_BUSY_CTRL_FIELD                        (_MK_MASK_CONST(0x1) << EMC_DBG_0_AP_REQ_BUSY_CTRL_SHIFT)
+#define EMC_DBG_0_AP_REQ_BUSY_CTRL_RANGE                        10:10
+#define EMC_DBG_0_AP_REQ_BUSY_CTRL_WOFFSET                      0x0
+#define EMC_DBG_0_AP_REQ_BUSY_CTRL_DEFAULT                      _MK_MASK_CONST(0x1)
+#define EMC_DBG_0_AP_REQ_BUSY_CTRL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define EMC_DBG_0_AP_REQ_BUSY_CTRL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_DBG_0_AP_REQ_BUSY_CTRL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_DBG_0_AP_REQ_BUSY_CTRL_INIT_ENUM                    ENABLED
+#define EMC_DBG_0_AP_REQ_BUSY_CTRL_DISABLED                     _MK_ENUM_CONST(0)
+#define EMC_DBG_0_AP_REQ_BUSY_CTRL_ENABLED                      _MK_ENUM_CONST(1)
+
+// determines the priority of cfg accesses to the DRAM.  Setting this register to ENABLED
+// gives DRAM config cycles (refresh, mrs, emrs, etc.) higher priority over real time requestors.
+// The DISABLED setting gives the real time requestors higher priority than DRAM config cycles.
+// Do not program to DISABLED unless for debugging.
+#define EMC_DBG_0_CFG_PRIORITY_SHIFT                    _MK_SHIFT_CONST(24)
+#define EMC_DBG_0_CFG_PRIORITY_FIELD                    (_MK_MASK_CONST(0x1) << EMC_DBG_0_CFG_PRIORITY_SHIFT)
+#define EMC_DBG_0_CFG_PRIORITY_RANGE                    24:24
+#define EMC_DBG_0_CFG_PRIORITY_WOFFSET                  0x0
+#define EMC_DBG_0_CFG_PRIORITY_DEFAULT                  _MK_MASK_CONST(0x1)
+#define EMC_DBG_0_CFG_PRIORITY_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define EMC_DBG_0_CFG_PRIORITY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_DBG_0_CFG_PRIORITY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_DBG_0_CFG_PRIORITY_INIT_ENUM                        ENABLED
+#define EMC_DBG_0_CFG_PRIORITY_DISABLED                 _MK_ENUM_CONST(0)
+#define EMC_DBG_0_CFG_PRIORITY_ENABLED                  _MK_ENUM_CONST(1)
+
+
+// Register EMC_CFG_0  // Configuration Register
+#define EMC_CFG_0                       _MK_ADDR_CONST(0xc)
+#define EMC_CFG_0_SECURE                        0x0
+#define EMC_CFG_0_WORD_COUNT                    0x1
+#define EMC_CFG_0_RESET_VAL                     _MK_MASK_CONST(0x300ff00)
+#define EMC_CFG_0_RESET_MASK                    _MK_MASK_CONST(0xe301ff01)
+#define EMC_CFG_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define EMC_CFG_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_CFG_0_READ_MASK                     _MK_MASK_CONST(0xe301ff01)
+#define EMC_CFG_0_WRITE_MASK                    _MK_MASK_CONST(0xe301ff01)
+// preemptively closes all of the banks after the EMC has been idle for PRE_IDLE_CYCLES cycles and
+// there are banks open. PRE_IDLE_EN can be enabled if violating tRAS max is an issue.
+#define EMC_CFG_0_PRE_IDLE_EN_SHIFT                     _MK_SHIFT_CONST(0)
+#define EMC_CFG_0_PRE_IDLE_EN_FIELD                     (_MK_MASK_CONST(0x1) << EMC_CFG_0_PRE_IDLE_EN_SHIFT)
+#define EMC_CFG_0_PRE_IDLE_EN_RANGE                     0:0
+#define EMC_CFG_0_PRE_IDLE_EN_WOFFSET                   0x0
+#define EMC_CFG_0_PRE_IDLE_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_CFG_0_PRE_IDLE_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define EMC_CFG_0_PRE_IDLE_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_CFG_0_PRE_IDLE_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_CFG_0_PRE_IDLE_EN_INIT_ENUM                 DISABLED
+#define EMC_CFG_0_PRE_IDLE_EN_DISABLED                  _MK_ENUM_CONST(0)
+#define EMC_CFG_0_PRE_IDLE_EN_ENABLED                   _MK_ENUM_CONST(1)
+
+// cycles after which an idle bank may be closed. Note that 0 is an illegal setting for PRE_IDLE_CYCLES.
+#define EMC_CFG_0_PRE_IDLE_CYCLES_SHIFT                 _MK_SHIFT_CONST(8)
+#define EMC_CFG_0_PRE_IDLE_CYCLES_FIELD                 (_MK_MASK_CONST(0xff) << EMC_CFG_0_PRE_IDLE_CYCLES_SHIFT)
+#define EMC_CFG_0_PRE_IDLE_CYCLES_RANGE                 15:8
+#define EMC_CFG_0_PRE_IDLE_CYCLES_WOFFSET                       0x0
+#define EMC_CFG_0_PRE_IDLE_CYCLES_DEFAULT                       _MK_MASK_CONST(0xff)
+#define EMC_CFG_0_PRE_IDLE_CYCLES_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define EMC_CFG_0_PRE_IDLE_CYCLES_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_CFG_0_PRE_IDLE_CYCLES_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// used to try to clear the auto-precharge bit on the previous request if the next request
+// is on the same page.  The previous request has to be in reach for this to happen.
+#define EMC_CFG_0_CLEAR_AP_PREV_SPREQ_SHIFT                     _MK_SHIFT_CONST(16)
+#define EMC_CFG_0_CLEAR_AP_PREV_SPREQ_FIELD                     (_MK_MASK_CONST(0x1) << EMC_CFG_0_CLEAR_AP_PREV_SPREQ_SHIFT)
+#define EMC_CFG_0_CLEAR_AP_PREV_SPREQ_RANGE                     16:16
+#define EMC_CFG_0_CLEAR_AP_PREV_SPREQ_WOFFSET                   0x0
+#define EMC_CFG_0_CLEAR_AP_PREV_SPREQ_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_CFG_0_CLEAR_AP_PREV_SPREQ_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define EMC_CFG_0_CLEAR_AP_PREV_SPREQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_CFG_0_CLEAR_AP_PREV_SPREQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_CFG_0_CLEAR_AP_PREV_SPREQ_INIT_ENUM                 DISABLED
+#define EMC_CFG_0_CLEAR_AP_PREV_SPREQ_DISABLED                  _MK_ENUM_CONST(0)
+#define EMC_CFG_0_CLEAR_AP_PREV_SPREQ_ENABLED                   _MK_ENUM_CONST(1)
+
+// enable auto-precharge in the EMC for reads. This bits, when set to DISABLE, will override the settings in the MC
+// register. Otherwise, they permit clients to make auto-precharge requests as specified by the Memory Controller.
+#define EMC_CFG_0_AUTO_PRE_RD_SHIFT                     _MK_SHIFT_CONST(24)
+#define EMC_CFG_0_AUTO_PRE_RD_FIELD                     (_MK_MASK_CONST(0x1) << EMC_CFG_0_AUTO_PRE_RD_SHIFT)
+#define EMC_CFG_0_AUTO_PRE_RD_RANGE                     24:24
+#define EMC_CFG_0_AUTO_PRE_RD_WOFFSET                   0x0
+#define EMC_CFG_0_AUTO_PRE_RD_DEFAULT                   _MK_MASK_CONST(0x1)
+#define EMC_CFG_0_AUTO_PRE_RD_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define EMC_CFG_0_AUTO_PRE_RD_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_CFG_0_AUTO_PRE_RD_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_CFG_0_AUTO_PRE_RD_INIT_ENUM                 ENABLED
+#define EMC_CFG_0_AUTO_PRE_RD_DISABLED                  _MK_ENUM_CONST(0)
+#define EMC_CFG_0_AUTO_PRE_RD_ENABLED                   _MK_ENUM_CONST(1)
+
+// enable auto-precharge in the EMC for writes. This bits, when set to DISABLE, will override the settings in the MC
+// register. Otherwise, they permit clients to make auto-precharge requests as specified by the Memory Controller.
+#define EMC_CFG_0_AUTO_PRE_WR_SHIFT                     _MK_SHIFT_CONST(25)
+#define EMC_CFG_0_AUTO_PRE_WR_FIELD                     (_MK_MASK_CONST(0x1) << EMC_CFG_0_AUTO_PRE_WR_SHIFT)
+#define EMC_CFG_0_AUTO_PRE_WR_RANGE                     25:25
+#define EMC_CFG_0_AUTO_PRE_WR_WOFFSET                   0x0
+#define EMC_CFG_0_AUTO_PRE_WR_DEFAULT                   _MK_MASK_CONST(0x1)
+#define EMC_CFG_0_AUTO_PRE_WR_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define EMC_CFG_0_AUTO_PRE_WR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_CFG_0_AUTO_PRE_WR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_CFG_0_AUTO_PRE_WR_INIT_ENUM                 ENABLED
+#define EMC_CFG_0_AUTO_PRE_WR_DISABLED                  _MK_ENUM_CONST(0)
+#define EMC_CFG_0_AUTO_PRE_WR_ENABLED                   _MK_ENUM_CONST(1)
+
+// allows the DRAM controller to perform opportunistic active powerdown control using the CKE
+// pin on the DRAM. The behavior of the powerdown control logic is controlled by the PDEX2* and *2PDEN
+// registers. The value of DRAM_ACPD should only be changed when CKE is low, e.g., during software-controlled
+// self-refresh or before DRAM initialization.
+// If enabling ACPD, you should ALWAYS enable DRAM_CLKSTOP_PDSR_ONLY.
+// Not doing so will result in sub-optimal power-down & clockstop performance.  The powerdown conditions are
+// met within a couple of cycles after the clock has stopped, so the clock must be restarted & minimum clock
+// timings met before powerdown can be issued and clock restopped.
+#define EMC_CFG_0_DRAM_ACPD_SHIFT                       _MK_SHIFT_CONST(29)
+#define EMC_CFG_0_DRAM_ACPD_FIELD                       (_MK_MASK_CONST(0x1) << EMC_CFG_0_DRAM_ACPD_SHIFT)
+#define EMC_CFG_0_DRAM_ACPD_RANGE                       29:29
+#define EMC_CFG_0_DRAM_ACPD_WOFFSET                     0x0
+#define EMC_CFG_0_DRAM_ACPD_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_CFG_0_DRAM_ACPD_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define EMC_CFG_0_DRAM_ACPD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_CFG_0_DRAM_ACPD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EMC_CFG_0_DRAM_ACPD_INIT_ENUM                   NO_POWERDOWN
+#define EMC_CFG_0_DRAM_ACPD_NO_POWERDOWN                        _MK_ENUM_CONST(0)
+#define EMC_CFG_0_DRAM_ACPD_ACTIVE_POWERDOWN                    _MK_ENUM_CONST(1)
+
+// clockstop (if enabled) only allowed to happen if CKE=0 (for all CKE bits associated w/ clock)
+#define EMC_CFG_0_DRAM_CLKSTOP_PDSR_ONLY_SHIFT                  _MK_SHIFT_CONST(30)
+#define EMC_CFG_0_DRAM_CLKSTOP_PDSR_ONLY_FIELD                  (_MK_MASK_CONST(0x1) << EMC_CFG_0_DRAM_CLKSTOP_PDSR_ONLY_SHIFT)
+#define EMC_CFG_0_DRAM_CLKSTOP_PDSR_ONLY_RANGE                  30:30
+#define EMC_CFG_0_DRAM_CLKSTOP_PDSR_ONLY_WOFFSET                        0x0
+#define EMC_CFG_0_DRAM_CLKSTOP_PDSR_ONLY_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_CFG_0_DRAM_CLKSTOP_PDSR_ONLY_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define EMC_CFG_0_DRAM_CLKSTOP_PDSR_ONLY_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_CFG_0_DRAM_CLKSTOP_PDSR_ONLY_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_CFG_0_DRAM_CLKSTOP_PDSR_ONLY_INIT_ENUM                      DISABLED
+#define EMC_CFG_0_DRAM_CLKSTOP_PDSR_ONLY_DISABLED                       _MK_ENUM_CONST(0)
+#define EMC_CFG_0_DRAM_CLKSTOP_PDSR_ONLY_ENABLED                        _MK_ENUM_CONST(1)
+
+// allows the DRAM controller to turn off the clock to the DRAM when it is safe to do so
+// (no operations are ongoing, and tRFC, tMRS, tRP, etc. have all been satisfied).
+#define EMC_CFG_0_DRAM_CLKSTOP_SHIFT                    _MK_SHIFT_CONST(31)
+#define EMC_CFG_0_DRAM_CLKSTOP_FIELD                    (_MK_MASK_CONST(0x1) << EMC_CFG_0_DRAM_CLKSTOP_SHIFT)
+#define EMC_CFG_0_DRAM_CLKSTOP_RANGE                    31:31
+#define EMC_CFG_0_DRAM_CLKSTOP_WOFFSET                  0x0
+#define EMC_CFG_0_DRAM_CLKSTOP_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_CFG_0_DRAM_CLKSTOP_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define EMC_CFG_0_DRAM_CLKSTOP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_CFG_0_DRAM_CLKSTOP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_CFG_0_DRAM_CLKSTOP_INIT_ENUM                        DISABLED
+#define EMC_CFG_0_DRAM_CLKSTOP_DISABLED                 _MK_ENUM_CONST(0)
+#define EMC_CFG_0_DRAM_CLKSTOP_ENABLED                  _MK_ENUM_CONST(1)
+
+
+// Register EMC_ADR_CFG_0  // External memory address config Register
+#define EMC_ADR_CFG_0                   _MK_ADDR_CONST(0x10)
+#define EMC_ADR_CFG_0_SECURE                    0x0
+#define EMC_ADR_CFG_0_WORD_COUNT                        0x1
+#define EMC_ADR_CFG_0_RESET_VAL                         _MK_MASK_CONST(0x40202)
+#define EMC_ADR_CFG_0_RESET_MASK                        _MK_MASK_CONST(0x30f0307)
+#define EMC_ADR_CFG_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define EMC_ADR_CFG_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_ADR_CFG_0_READ_MASK                         _MK_MASK_CONST(0x30f0307)
+#define EMC_ADR_CFG_0_WRITE_MASK                        _MK_MASK_CONST(0x30f0307)
+// width of column address of the attached SDRAM device.
+#define EMC_ADR_CFG_0_EMEM_COLWIDTH_SHIFT                       _MK_SHIFT_CONST(0)
+#define EMC_ADR_CFG_0_EMEM_COLWIDTH_FIELD                       (_MK_MASK_CONST(0x7) << EMC_ADR_CFG_0_EMEM_COLWIDTH_SHIFT)
+#define EMC_ADR_CFG_0_EMEM_COLWIDTH_RANGE                       2:0
+#define EMC_ADR_CFG_0_EMEM_COLWIDTH_WOFFSET                     0x0
+#define EMC_ADR_CFG_0_EMEM_COLWIDTH_DEFAULT                     _MK_MASK_CONST(0x2)
+#define EMC_ADR_CFG_0_EMEM_COLWIDTH_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
+#define EMC_ADR_CFG_0_EMEM_COLWIDTH_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_ADR_CFG_0_EMEM_COLWIDTH_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EMC_ADR_CFG_0_EMEM_COLWIDTH_INIT_ENUM                   W9
+#define EMC_ADR_CFG_0_EMEM_COLWIDTH_W7                  _MK_ENUM_CONST(0)
+#define EMC_ADR_CFG_0_EMEM_COLWIDTH_W8                  _MK_ENUM_CONST(1)
+#define EMC_ADR_CFG_0_EMEM_COLWIDTH_W9                  _MK_ENUM_CONST(2)
+#define EMC_ADR_CFG_0_EMEM_COLWIDTH_W10                 _MK_ENUM_CONST(3)
+#define EMC_ADR_CFG_0_EMEM_COLWIDTH_W11                 _MK_ENUM_CONST(4)
+
+// width of bank address of the attached SDRAM device.
+#define EMC_ADR_CFG_0_EMEM_BANKWIDTH_SHIFT                      _MK_SHIFT_CONST(8)
+#define EMC_ADR_CFG_0_EMEM_BANKWIDTH_FIELD                      (_MK_MASK_CONST(0x3) << EMC_ADR_CFG_0_EMEM_BANKWIDTH_SHIFT)
+#define EMC_ADR_CFG_0_EMEM_BANKWIDTH_RANGE                      9:8
+#define EMC_ADR_CFG_0_EMEM_BANKWIDTH_WOFFSET                    0x0
+#define EMC_ADR_CFG_0_EMEM_BANKWIDTH_DEFAULT                    _MK_MASK_CONST(0x2)
+#define EMC_ADR_CFG_0_EMEM_BANKWIDTH_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define EMC_ADR_CFG_0_EMEM_BANKWIDTH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_ADR_CFG_0_EMEM_BANKWIDTH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_ADR_CFG_0_EMEM_BANKWIDTH_INIT_ENUM                  W2
+#define EMC_ADR_CFG_0_EMEM_BANKWIDTH_W1                 _MK_ENUM_CONST(1)
+#define EMC_ADR_CFG_0_EMEM_BANKWIDTH_W2                 _MK_ENUM_CONST(2)
+#define EMC_ADR_CFG_0_EMEM_BANKWIDTH_W3                 _MK_ENUM_CONST(3)
+
+// size of the attached SDRAM device used to generate width of row address.
+#define EMC_ADR_CFG_0_EMEM_DEVSIZE_SHIFT                        _MK_SHIFT_CONST(16)
+#define EMC_ADR_CFG_0_EMEM_DEVSIZE_FIELD                        (_MK_MASK_CONST(0xf) << EMC_ADR_CFG_0_EMEM_DEVSIZE_SHIFT)
+#define EMC_ADR_CFG_0_EMEM_DEVSIZE_RANGE                        19:16
+#define EMC_ADR_CFG_0_EMEM_DEVSIZE_WOFFSET                      0x0
+#define EMC_ADR_CFG_0_EMEM_DEVSIZE_DEFAULT                      _MK_MASK_CONST(0x4)
+#define EMC_ADR_CFG_0_EMEM_DEVSIZE_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define EMC_ADR_CFG_0_EMEM_DEVSIZE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_ADR_CFG_0_EMEM_DEVSIZE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_ADR_CFG_0_EMEM_DEVSIZE_INIT_ENUM                    D64MB
+#define EMC_ADR_CFG_0_EMEM_DEVSIZE_D4MB                 _MK_ENUM_CONST(0)
+#define EMC_ADR_CFG_0_EMEM_DEVSIZE_D8MB                 _MK_ENUM_CONST(1)
+#define EMC_ADR_CFG_0_EMEM_DEVSIZE_D16MB                        _MK_ENUM_CONST(2)
+#define EMC_ADR_CFG_0_EMEM_DEVSIZE_D32MB                        _MK_ENUM_CONST(3)
+#define EMC_ADR_CFG_0_EMEM_DEVSIZE_D64MB                        _MK_ENUM_CONST(4)
+#define EMC_ADR_CFG_0_EMEM_DEVSIZE_D128MB                       _MK_ENUM_CONST(5)
+#define EMC_ADR_CFG_0_EMEM_DEVSIZE_D256MB                       _MK_ENUM_CONST(6)
+#define EMC_ADR_CFG_0_EMEM_DEVSIZE_D512MB                       _MK_ENUM_CONST(7)
+#define EMC_ADR_CFG_0_EMEM_DEVSIZE_D1024MB                      _MK_ENUM_CONST(8)
+#define EMC_ADR_CFG_0_EMEM_DEVSIZE_D1GB                 _MK_ENUM_CONST(8)
+
+// the number of attached devices.
+// If more than one device is attached, the DEVSIZE, COLWIDTH, and BANKWIDTH configurations for the second device
+// will be defined by the fields in ADR_CFG_1, while the fields in ADR_CFG will only apply to the first device.
+#define EMC_ADR_CFG_0_EMEM_NUMDEV_SHIFT                 _MK_SHIFT_CONST(24)
+#define EMC_ADR_CFG_0_EMEM_NUMDEV_FIELD                 (_MK_MASK_CONST(0x3) << EMC_ADR_CFG_0_EMEM_NUMDEV_SHIFT)
+#define EMC_ADR_CFG_0_EMEM_NUMDEV_RANGE                 25:24
+#define EMC_ADR_CFG_0_EMEM_NUMDEV_WOFFSET                       0x0
+#define EMC_ADR_CFG_0_EMEM_NUMDEV_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_ADR_CFG_0_EMEM_NUMDEV_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define EMC_ADR_CFG_0_EMEM_NUMDEV_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_ADR_CFG_0_EMEM_NUMDEV_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_ADR_CFG_0_EMEM_NUMDEV_INIT_ENUM                     N1
+#define EMC_ADR_CFG_0_EMEM_NUMDEV_N1                    _MK_ENUM_CONST(0)
+#define EMC_ADR_CFG_0_EMEM_NUMDEV_N2                    _MK_ENUM_CONST(1)
+
+
+// Register EMC_ADR_CFG_1_0  // External memory address config Register, Device[1]
+#define EMC_ADR_CFG_1_0                 _MK_ADDR_CONST(0x14)
+#define EMC_ADR_CFG_1_0_SECURE                  0x0
+#define EMC_ADR_CFG_1_0_WORD_COUNT                      0x1
+#define EMC_ADR_CFG_1_0_RESET_VAL                       _MK_MASK_CONST(0x40202)
+#define EMC_ADR_CFG_1_0_RESET_MASK                      _MK_MASK_CONST(0xf0307)
+#define EMC_ADR_CFG_1_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EMC_ADR_CFG_1_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_ADR_CFG_1_0_READ_MASK                       _MK_MASK_CONST(0xf0307)
+#define EMC_ADR_CFG_1_0_WRITE_MASK                      _MK_MASK_CONST(0xf0307)
+// width of column address of the attached SDRAM device.
+#define EMC_ADR_CFG_1_0_EMEM1_COLWIDTH_SHIFT                    _MK_SHIFT_CONST(0)
+#define EMC_ADR_CFG_1_0_EMEM1_COLWIDTH_FIELD                    (_MK_MASK_CONST(0x7) << EMC_ADR_CFG_1_0_EMEM1_COLWIDTH_SHIFT)
+#define EMC_ADR_CFG_1_0_EMEM1_COLWIDTH_RANGE                    2:0
+#define EMC_ADR_CFG_1_0_EMEM1_COLWIDTH_WOFFSET                  0x0
+#define EMC_ADR_CFG_1_0_EMEM1_COLWIDTH_DEFAULT                  _MK_MASK_CONST(0x2)
+#define EMC_ADR_CFG_1_0_EMEM1_COLWIDTH_DEFAULT_MASK                     _MK_MASK_CONST(0x7)
+#define EMC_ADR_CFG_1_0_EMEM1_COLWIDTH_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_ADR_CFG_1_0_EMEM1_COLWIDTH_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_ADR_CFG_1_0_EMEM1_COLWIDTH_INIT_ENUM                        W9
+#define EMC_ADR_CFG_1_0_EMEM1_COLWIDTH_W7                       _MK_ENUM_CONST(0)
+#define EMC_ADR_CFG_1_0_EMEM1_COLWIDTH_W8                       _MK_ENUM_CONST(1)
+#define EMC_ADR_CFG_1_0_EMEM1_COLWIDTH_W9                       _MK_ENUM_CONST(2)
+#define EMC_ADR_CFG_1_0_EMEM1_COLWIDTH_W10                      _MK_ENUM_CONST(3)
+#define EMC_ADR_CFG_1_0_EMEM1_COLWIDTH_W11                      _MK_ENUM_CONST(4)
+
+// width of bank address of the attached SDRAM device.
+#define EMC_ADR_CFG_1_0_EMEM1_BANKWIDTH_SHIFT                   _MK_SHIFT_CONST(8)
+#define EMC_ADR_CFG_1_0_EMEM1_BANKWIDTH_FIELD                   (_MK_MASK_CONST(0x3) << EMC_ADR_CFG_1_0_EMEM1_BANKWIDTH_SHIFT)
+#define EMC_ADR_CFG_1_0_EMEM1_BANKWIDTH_RANGE                   9:8
+#define EMC_ADR_CFG_1_0_EMEM1_BANKWIDTH_WOFFSET                 0x0
+#define EMC_ADR_CFG_1_0_EMEM1_BANKWIDTH_DEFAULT                 _MK_MASK_CONST(0x2)
+#define EMC_ADR_CFG_1_0_EMEM1_BANKWIDTH_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define EMC_ADR_CFG_1_0_EMEM1_BANKWIDTH_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_ADR_CFG_1_0_EMEM1_BANKWIDTH_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define EMC_ADR_CFG_1_0_EMEM1_BANKWIDTH_INIT_ENUM                       W2
+#define EMC_ADR_CFG_1_0_EMEM1_BANKWIDTH_W1                      _MK_ENUM_CONST(1)
+#define EMC_ADR_CFG_1_0_EMEM1_BANKWIDTH_W2                      _MK_ENUM_CONST(2)
+#define EMC_ADR_CFG_1_0_EMEM1_BANKWIDTH_W3                      _MK_ENUM_CONST(3)
+
+// size of the attached SDRAM device used to generate width of row address.
+#define EMC_ADR_CFG_1_0_EMEM1_DEVSIZE_SHIFT                     _MK_SHIFT_CONST(16)
+#define EMC_ADR_CFG_1_0_EMEM1_DEVSIZE_FIELD                     (_MK_MASK_CONST(0xf) << EMC_ADR_CFG_1_0_EMEM1_DEVSIZE_SHIFT)
+#define EMC_ADR_CFG_1_0_EMEM1_DEVSIZE_RANGE                     19:16
+#define EMC_ADR_CFG_1_0_EMEM1_DEVSIZE_WOFFSET                   0x0
+#define EMC_ADR_CFG_1_0_EMEM1_DEVSIZE_DEFAULT                   _MK_MASK_CONST(0x4)
+#define EMC_ADR_CFG_1_0_EMEM1_DEVSIZE_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define EMC_ADR_CFG_1_0_EMEM1_DEVSIZE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_ADR_CFG_1_0_EMEM1_DEVSIZE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_ADR_CFG_1_0_EMEM1_DEVSIZE_INIT_ENUM                 D64MB
+#define EMC_ADR_CFG_1_0_EMEM1_DEVSIZE_D4MB                      _MK_ENUM_CONST(0)
+#define EMC_ADR_CFG_1_0_EMEM1_DEVSIZE_D8MB                      _MK_ENUM_CONST(1)
+#define EMC_ADR_CFG_1_0_EMEM1_DEVSIZE_D16MB                     _MK_ENUM_CONST(2)
+#define EMC_ADR_CFG_1_0_EMEM1_DEVSIZE_D32MB                     _MK_ENUM_CONST(3)
+#define EMC_ADR_CFG_1_0_EMEM1_DEVSIZE_D64MB                     _MK_ENUM_CONST(4)
+#define EMC_ADR_CFG_1_0_EMEM1_DEVSIZE_D128MB                    _MK_ENUM_CONST(5)
+#define EMC_ADR_CFG_1_0_EMEM1_DEVSIZE_D256MB                    _MK_ENUM_CONST(6)
+#define EMC_ADR_CFG_1_0_EMEM1_DEVSIZE_D512MB                    _MK_ENUM_CONST(7)
+#define EMC_ADR_CFG_1_0_EMEM1_DEVSIZE_D1024MB                   _MK_ENUM_CONST(8)
+#define EMC_ADR_CFG_1_0_EMEM1_DEVSIZE_D1GB                      _MK_ENUM_CONST(8)
+
+
+// Reserved address 24 [0x18] 
+
+// Reserved address 28 [0x1c] 
+
+// Register EMC_REFCTRL_0  // Refresh Control Register
+#define EMC_REFCTRL_0                   _MK_ADDR_CONST(0x20)
+#define EMC_REFCTRL_0_SECURE                    0x0
+#define EMC_REFCTRL_0_WORD_COUNT                        0x1
+#define EMC_REFCTRL_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define EMC_REFCTRL_0_RESET_MASK                        _MK_MASK_CONST(0x80000003)
+#define EMC_REFCTRL_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define EMC_REFCTRL_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_REFCTRL_0_READ_MASK                         _MK_MASK_CONST(0x80000003)
+#define EMC_REFCTRL_0_WRITE_MASK                        _MK_MASK_CONST(0x80000003)
+// disables refresh to individual attached device (1 bit per dram chip-select).
+#define EMC_REFCTRL_0_DEVICE_REFRESH_DISABLE_SHIFT                      _MK_SHIFT_CONST(0)
+#define EMC_REFCTRL_0_DEVICE_REFRESH_DISABLE_FIELD                      (_MK_MASK_CONST(0x3) << EMC_REFCTRL_0_DEVICE_REFRESH_DISABLE_SHIFT)
+#define EMC_REFCTRL_0_DEVICE_REFRESH_DISABLE_RANGE                      1:0
+#define EMC_REFCTRL_0_DEVICE_REFRESH_DISABLE_WOFFSET                    0x0
+#define EMC_REFCTRL_0_DEVICE_REFRESH_DISABLE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_REFCTRL_0_DEVICE_REFRESH_DISABLE_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define EMC_REFCTRL_0_DEVICE_REFRESH_DISABLE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_REFCTRL_0_DEVICE_REFRESH_DISABLE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// enable refresh controller. 
+#define EMC_REFCTRL_0_REF_VALID_SHIFT                   _MK_SHIFT_CONST(31)
+#define EMC_REFCTRL_0_REF_VALID_FIELD                   (_MK_MASK_CONST(0x1) << EMC_REFCTRL_0_REF_VALID_SHIFT)
+#define EMC_REFCTRL_0_REF_VALID_RANGE                   31:31
+#define EMC_REFCTRL_0_REF_VALID_WOFFSET                 0x0
+#define EMC_REFCTRL_0_REF_VALID_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_REFCTRL_0_REF_VALID_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define EMC_REFCTRL_0_REF_VALID_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_REFCTRL_0_REF_VALID_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define EMC_REFCTRL_0_REF_VALID_INIT_ENUM                       DISABLED
+#define EMC_REFCTRL_0_REF_VALID_DISABLED                        _MK_ENUM_CONST(0)
+#define EMC_REFCTRL_0_REF_VALID_ENABLED                 _MK_ENUM_CONST(1)
+
+
+// Register EMC_PIN_0  // Controls state of selected DRAM pins
+#define EMC_PIN_0                       _MK_ADDR_CONST(0x24)
+#define EMC_PIN_0_SECURE                        0x0
+#define EMC_PIN_0_WORD_COUNT                    0x1
+#define EMC_PIN_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define EMC_PIN_0_RESET_MASK                    _MK_MASK_CONST(0x11)
+#define EMC_PIN_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define EMC_PIN_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_PIN_0_READ_MASK                     _MK_MASK_CONST(0x11)
+#define EMC_PIN_0_WRITE_MASK                    _MK_MASK_CONST(0x11)
+// selects the level of the CKE pin.
+// This can be used to place the DRAM in power down state.  PIN_CKE value is applied all CKE pins.
+#define EMC_PIN_0_PIN_CKE_SHIFT                 _MK_SHIFT_CONST(0)
+#define EMC_PIN_0_PIN_CKE_FIELD                 (_MK_MASK_CONST(0x1) << EMC_PIN_0_PIN_CKE_SHIFT)
+#define EMC_PIN_0_PIN_CKE_RANGE                 0:0
+#define EMC_PIN_0_PIN_CKE_WOFFSET                       0x0
+#define EMC_PIN_0_PIN_CKE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_PIN_0_PIN_CKE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define EMC_PIN_0_PIN_CKE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_PIN_0_PIN_CKE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_PIN_0_PIN_CKE_INIT_ENUM                     POWERDOWN
+#define EMC_PIN_0_PIN_CKE_POWERDOWN                     _MK_ENUM_CONST(0)
+#define EMC_PIN_0_PIN_CKE_NORMAL                        _MK_ENUM_CONST(1)
+
+// is used to always mask DRAM writes.
+// This pin should only be used for initialization.  Certain DRAM vendors (e.g., Samsung),
+// require the DQM to be high during initialization.  The register value should be set to NORMAL
+// after the initialization sequence.
+#define EMC_PIN_0_PIN_DQM_SHIFT                 _MK_SHIFT_CONST(4)
+#define EMC_PIN_0_PIN_DQM_FIELD                 (_MK_MASK_CONST(0x1) << EMC_PIN_0_PIN_DQM_SHIFT)
+#define EMC_PIN_0_PIN_DQM_RANGE                 4:4
+#define EMC_PIN_0_PIN_DQM_WOFFSET                       0x0
+#define EMC_PIN_0_PIN_DQM_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_PIN_0_PIN_DQM_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define EMC_PIN_0_PIN_DQM_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_PIN_0_PIN_DQM_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_PIN_0_PIN_DQM_INIT_ENUM                     NORMAL
+#define EMC_PIN_0_PIN_DQM_NORMAL                        _MK_ENUM_CONST(0)
+#define EMC_PIN_0_PIN_DQM_INACTIVE                      _MK_ENUM_CONST(1)
+
+
+// Register EMC_TIMING_CONTROL_0  // Triggers an update of the timing-related registers
+#define EMC_TIMING_CONTROL_0                    _MK_ADDR_CONST(0x28)
+#define EMC_TIMING_CONTROL_0_SECURE                     0x0
+#define EMC_TIMING_CONTROL_0_WORD_COUNT                         0x1
+#define EMC_TIMING_CONTROL_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define EMC_TIMING_CONTROL_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_TIMING_CONTROL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define EMC_TIMING_CONTROL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_TIMING_CONTROL_0_READ_MASK                  _MK_MASK_CONST(0x1)
+#define EMC_TIMING_CONTROL_0_WRITE_MASK                         _MK_MASK_CONST(0x1)
+#define EMC_TIMING_CONTROL_0_TIMING_UPDATE_SHIFT                        _MK_SHIFT_CONST(0)
+#define EMC_TIMING_CONTROL_0_TIMING_UPDATE_FIELD                        (_MK_MASK_CONST(0x1) << EMC_TIMING_CONTROL_0_TIMING_UPDATE_SHIFT)
+#define EMC_TIMING_CONTROL_0_TIMING_UPDATE_RANGE                        0:0
+#define EMC_TIMING_CONTROL_0_TIMING_UPDATE_WOFFSET                      0x0
+#define EMC_TIMING_CONTROL_0_TIMING_UPDATE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_TIMING_CONTROL_0_TIMING_UPDATE_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define EMC_TIMING_CONTROL_0_TIMING_UPDATE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_TIMING_CONTROL_0_TIMING_UPDATE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register EMC_RC_0  // DRAM timing parameter
+#define EMC_RC_0                        _MK_ADDR_CONST(0x2c)
+#define EMC_RC_0_SECURE                         0x0
+#define EMC_RC_0_WORD_COUNT                     0x1
+#define EMC_RC_0_RESET_VAL                      _MK_MASK_CONST(0x3f)
+#define EMC_RC_0_RESET_MASK                     _MK_MASK_CONST(0x3f)
+#define EMC_RC_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define EMC_RC_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_RC_0_READ_MASK                      _MK_MASK_CONST(0x3f)
+#define EMC_RC_0_WRITE_MASK                     _MK_MASK_CONST(0x3f)
+// specifies the row cycle time.
+// This is the minimum number of cycles between activate commands to the same bank.
+#define EMC_RC_0_RC_SHIFT                       _MK_SHIFT_CONST(0)
+#define EMC_RC_0_RC_FIELD                       (_MK_MASK_CONST(0x3f) << EMC_RC_0_RC_SHIFT)
+#define EMC_RC_0_RC_RANGE                       5:0
+#define EMC_RC_0_RC_WOFFSET                     0x0
+#define EMC_RC_0_RC_DEFAULT                     _MK_MASK_CONST(0x3f)
+#define EMC_RC_0_RC_DEFAULT_MASK                        _MK_MASK_CONST(0x3f)
+#define EMC_RC_0_RC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_RC_0_RC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register EMC_RFC_0  // DRAM timing parameter
+#define EMC_RFC_0                       _MK_ADDR_CONST(0x30)
+#define EMC_RFC_0_SECURE                        0x0
+#define EMC_RFC_0_WORD_COUNT                    0x1
+#define EMC_RFC_0_RESET_VAL                     _MK_MASK_CONST(0x3f)
+#define EMC_RFC_0_RESET_MASK                    _MK_MASK_CONST(0x1ff)
+#define EMC_RFC_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define EMC_RFC_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_RFC_0_READ_MASK                     _MK_MASK_CONST(0x1ff)
+#define EMC_RFC_0_WRITE_MASK                    _MK_MASK_CONST(0x1ff)
+// specifies the auto refresh cycle time.
+// This is the minimum number of cycles between an auto refresh command and a subsequent auto refresh
+// or activate command.
+#define EMC_RFC_0_RFC_SHIFT                     _MK_SHIFT_CONST(0)
+#define EMC_RFC_0_RFC_FIELD                     (_MK_MASK_CONST(0x1ff) << EMC_RFC_0_RFC_SHIFT)
+#define EMC_RFC_0_RFC_RANGE                     8:0
+#define EMC_RFC_0_RFC_WOFFSET                   0x0
+#define EMC_RFC_0_RFC_DEFAULT                   _MK_MASK_CONST(0x3f)
+#define EMC_RFC_0_RFC_DEFAULT_MASK                      _MK_MASK_CONST(0x1ff)
+#define EMC_RFC_0_RFC_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_RFC_0_RFC_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EMC_RAS_0  // DRAM timing parameter
+#define EMC_RAS_0                       _MK_ADDR_CONST(0x34)
+#define EMC_RAS_0_SECURE                        0x0
+#define EMC_RAS_0_WORD_COUNT                    0x1
+#define EMC_RAS_0_RESET_VAL                     _MK_MASK_CONST(0x3f)
+#define EMC_RAS_0_RESET_MASK                    _MK_MASK_CONST(0x3f)
+#define EMC_RAS_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define EMC_RAS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_RAS_0_READ_MASK                     _MK_MASK_CONST(0x3f)
+#define EMC_RAS_0_WRITE_MASK                    _MK_MASK_CONST(0x3f)
+// specifies the row active time. 
+// This is the minimum number of cycles between an activate command and a precharge command to the same bank.
+#define EMC_RAS_0_RAS_SHIFT                     _MK_SHIFT_CONST(0)
+#define EMC_RAS_0_RAS_FIELD                     (_MK_MASK_CONST(0x3f) << EMC_RAS_0_RAS_SHIFT)
+#define EMC_RAS_0_RAS_RANGE                     5:0
+#define EMC_RAS_0_RAS_WOFFSET                   0x0
+#define EMC_RAS_0_RAS_DEFAULT                   _MK_MASK_CONST(0x3f)
+#define EMC_RAS_0_RAS_DEFAULT_MASK                      _MK_MASK_CONST(0x3f)
+#define EMC_RAS_0_RAS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_RAS_0_RAS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EMC_RP_0  // DRAM timing parameter
+#define EMC_RP_0                        _MK_ADDR_CONST(0x38)
+#define EMC_RP_0_SECURE                         0x0
+#define EMC_RP_0_WORD_COUNT                     0x1
+#define EMC_RP_0_RESET_VAL                      _MK_MASK_CONST(0x3f)
+#define EMC_RP_0_RESET_MASK                     _MK_MASK_CONST(0x3f)
+#define EMC_RP_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define EMC_RP_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_RP_0_READ_MASK                      _MK_MASK_CONST(0x3f)
+#define EMC_RP_0_WRITE_MASK                     _MK_MASK_CONST(0x3f)
+// specifies the row precharge time.
+// This is the minimum number of cycles between a precharge command and an activate command to the same bank.
+#define EMC_RP_0_RP_SHIFT                       _MK_SHIFT_CONST(0)
+#define EMC_RP_0_RP_FIELD                       (_MK_MASK_CONST(0x3f) << EMC_RP_0_RP_SHIFT)
+#define EMC_RP_0_RP_RANGE                       5:0
+#define EMC_RP_0_RP_WOFFSET                     0x0
+#define EMC_RP_0_RP_DEFAULT                     _MK_MASK_CONST(0x3f)
+#define EMC_RP_0_RP_DEFAULT_MASK                        _MK_MASK_CONST(0x3f)
+#define EMC_RP_0_RP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_RP_0_RP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register EMC_R2W_0  // DRAM timing parameter
+#define EMC_R2W_0                       _MK_ADDR_CONST(0x3c)
+#define EMC_R2W_0_SECURE                        0x0
+#define EMC_R2W_0_WORD_COUNT                    0x1
+#define EMC_R2W_0_RESET_VAL                     _MK_MASK_CONST(0x1f)
+#define EMC_R2W_0_RESET_MASK                    _MK_MASK_CONST(0x1f)
+#define EMC_R2W_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define EMC_R2W_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_R2W_0_READ_MASK                     _MK_MASK_CONST(0x1f)
+#define EMC_R2W_0_WRITE_MASK                    _MK_MASK_CONST(0x1f)
+// specifies the minimum number of cycles from any read command to any write command,
+// irrespective of bank.  This parameter guarantees the read->write turn-around time on the bus.
+// Set to ((CL+1)-WL + R2W_bus_turnaround_clks). If ODT is enabled,  set to ((CL+1)-WL + R2W_bus_turnaround_clks + 1)).
+// Largest programming value is 29
+#define EMC_R2W_0_R2W_SHIFT                     _MK_SHIFT_CONST(0)
+#define EMC_R2W_0_R2W_FIELD                     (_MK_MASK_CONST(0x1f) << EMC_R2W_0_R2W_SHIFT)
+#define EMC_R2W_0_R2W_RANGE                     4:0
+#define EMC_R2W_0_R2W_WOFFSET                   0x0
+#define EMC_R2W_0_R2W_DEFAULT                   _MK_MASK_CONST(0x1f)
+#define EMC_R2W_0_R2W_DEFAULT_MASK                      _MK_MASK_CONST(0x1f)
+#define EMC_R2W_0_R2W_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_R2W_0_R2W_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EMC_W2R_0  // DRAM timing parameter
+#define EMC_W2R_0                       _MK_ADDR_CONST(0x40)
+#define EMC_W2R_0_SECURE                        0x0
+#define EMC_W2R_0_WORD_COUNT                    0x1
+#define EMC_W2R_0_RESET_VAL                     _MK_MASK_CONST(0x1f)
+#define EMC_W2R_0_RESET_MASK                    _MK_MASK_CONST(0x1f)
+#define EMC_W2R_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define EMC_W2R_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_W2R_0_READ_MASK                     _MK_MASK_CONST(0x1f)
+#define EMC_W2R_0_WRITE_MASK                    _MK_MASK_CONST(0x1f)
+// specifies the minimum number of cycles from a write command to a read command,
+// irrespective of bank. Set to ((WL+1) + tWTR).
+// Largest programming value is 29
+#define EMC_W2R_0_W2R_SHIFT                     _MK_SHIFT_CONST(0)
+#define EMC_W2R_0_W2R_FIELD                     (_MK_MASK_CONST(0x1f) << EMC_W2R_0_W2R_SHIFT)
+#define EMC_W2R_0_W2R_RANGE                     4:0
+#define EMC_W2R_0_W2R_WOFFSET                   0x0
+#define EMC_W2R_0_W2R_DEFAULT                   _MK_MASK_CONST(0x1f)
+#define EMC_W2R_0_W2R_DEFAULT_MASK                      _MK_MASK_CONST(0x1f)
+#define EMC_W2R_0_W2R_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_W2R_0_W2R_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EMC_R2P_0  // DRAM timing parameter
+#define EMC_R2P_0                       _MK_ADDR_CONST(0x44)
+#define EMC_R2P_0_SECURE                        0x0
+#define EMC_R2P_0_WORD_COUNT                    0x1
+#define EMC_R2P_0_RESET_VAL                     _MK_MASK_CONST(0x1f)
+#define EMC_R2P_0_RESET_MASK                    _MK_MASK_CONST(0x1f)
+#define EMC_R2P_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define EMC_R2P_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_R2P_0_READ_MASK                     _MK_MASK_CONST(0x1f)
+#define EMC_R2P_0_WRITE_MASK                    _MK_MASK_CONST(0x1f)
+// specifies the minimum number of cycles from a read command to
+// a precharge command for the same bank.  Set to 1 clock.
+#define EMC_R2P_0_R2P_SHIFT                     _MK_SHIFT_CONST(0)
+#define EMC_R2P_0_R2P_FIELD                     (_MK_MASK_CONST(0x1f) << EMC_R2P_0_R2P_SHIFT)
+#define EMC_R2P_0_R2P_RANGE                     4:0
+#define EMC_R2P_0_R2P_WOFFSET                   0x0
+#define EMC_R2P_0_R2P_DEFAULT                   _MK_MASK_CONST(0x1f)
+#define EMC_R2P_0_R2P_DEFAULT_MASK                      _MK_MASK_CONST(0x1f)
+#define EMC_R2P_0_R2P_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_R2P_0_R2P_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EMC_W2P_0  // DRAM timing parameter
+#define EMC_W2P_0                       _MK_ADDR_CONST(0x48)
+#define EMC_W2P_0_SECURE                        0x0
+#define EMC_W2P_0_WORD_COUNT                    0x1
+#define EMC_W2P_0_RESET_VAL                     _MK_MASK_CONST(0x1f)
+#define EMC_W2P_0_RESET_MASK                    _MK_MASK_CONST(0x1f)
+#define EMC_W2P_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define EMC_W2P_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_W2P_0_READ_MASK                     _MK_MASK_CONST(0x1f)
+#define EMC_W2P_0_WRITE_MASK                    _MK_MASK_CONST(0x1f)
+// specifies the minimum number of cycles from a write command to
+// a precharge command for the same bank. Set to ((WL+1) + tWR).
+#define EMC_W2P_0_W2P_SHIFT                     _MK_SHIFT_CONST(0)
+#define EMC_W2P_0_W2P_FIELD                     (_MK_MASK_CONST(0x1f) << EMC_W2P_0_W2P_SHIFT)
+#define EMC_W2P_0_W2P_RANGE                     4:0
+#define EMC_W2P_0_W2P_WOFFSET                   0x0
+#define EMC_W2P_0_W2P_DEFAULT                   _MK_MASK_CONST(0x1f)
+#define EMC_W2P_0_W2P_DEFAULT_MASK                      _MK_MASK_CONST(0x1f)
+#define EMC_W2P_0_W2P_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_W2P_0_W2P_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EMC_RD_RCD_0  // DRAM timing parameter
+#define EMC_RD_RCD_0                    _MK_ADDR_CONST(0x4c)
+#define EMC_RD_RCD_0_SECURE                     0x0
+#define EMC_RD_RCD_0_WORD_COUNT                         0x1
+#define EMC_RD_RCD_0_RESET_VAL                  _MK_MASK_CONST(0x1f)
+#define EMC_RD_RCD_0_RESET_MASK                         _MK_MASK_CONST(0x3f)
+#define EMC_RD_RCD_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define EMC_RD_RCD_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_RD_RCD_0_READ_MASK                  _MK_MASK_CONST(0x3f)
+#define EMC_RD_RCD_0_WRITE_MASK                         _MK_MASK_CONST(0x3f)
+// specifies the ras to cas delay.
+// RD_RCD is the minimum number of cycles between an activate command and a read command to the same bank.
+#define EMC_RD_RCD_0_RD_RCD_SHIFT                       _MK_SHIFT_CONST(0)
+#define EMC_RD_RCD_0_RD_RCD_FIELD                       (_MK_MASK_CONST(0x3f) << EMC_RD_RCD_0_RD_RCD_SHIFT)
+#define EMC_RD_RCD_0_RD_RCD_RANGE                       5:0
+#define EMC_RD_RCD_0_RD_RCD_WOFFSET                     0x0
+#define EMC_RD_RCD_0_RD_RCD_DEFAULT                     _MK_MASK_CONST(0x1f)
+#define EMC_RD_RCD_0_RD_RCD_DEFAULT_MASK                        _MK_MASK_CONST(0x3f)
+#define EMC_RD_RCD_0_RD_RCD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_RD_RCD_0_RD_RCD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register EMC_WR_RCD_0  // DRAM timing parameter
+#define EMC_WR_RCD_0                    _MK_ADDR_CONST(0x50)
+#define EMC_WR_RCD_0_SECURE                     0x0
+#define EMC_WR_RCD_0_WORD_COUNT                         0x1
+#define EMC_WR_RCD_0_RESET_VAL                  _MK_MASK_CONST(0x1f)
+#define EMC_WR_RCD_0_RESET_MASK                         _MK_MASK_CONST(0x3f)
+#define EMC_WR_RCD_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define EMC_WR_RCD_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_WR_RCD_0_READ_MASK                  _MK_MASK_CONST(0x3f)
+#define EMC_WR_RCD_0_WRITE_MASK                         _MK_MASK_CONST(0x3f)
+// minimum number of cycles between an activate command and a
+// write command to the same bank.
+#define EMC_WR_RCD_0_WR_RCD_SHIFT                       _MK_SHIFT_CONST(0)
+#define EMC_WR_RCD_0_WR_RCD_FIELD                       (_MK_MASK_CONST(0x3f) << EMC_WR_RCD_0_WR_RCD_SHIFT)
+#define EMC_WR_RCD_0_WR_RCD_RANGE                       5:0
+#define EMC_WR_RCD_0_WR_RCD_WOFFSET                     0x0
+#define EMC_WR_RCD_0_WR_RCD_DEFAULT                     _MK_MASK_CONST(0x1f)
+#define EMC_WR_RCD_0_WR_RCD_DEFAULT_MASK                        _MK_MASK_CONST(0x3f)
+#define EMC_WR_RCD_0_WR_RCD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_WR_RCD_0_WR_RCD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register EMC_RRD_0  // DRAM timing parameter
+#define EMC_RRD_0                       _MK_ADDR_CONST(0x54)
+#define EMC_RRD_0_SECURE                        0x0
+#define EMC_RRD_0_WORD_COUNT                    0x1
+#define EMC_RRD_0_RESET_VAL                     _MK_MASK_CONST(0xf)
+#define EMC_RRD_0_RESET_MASK                    _MK_MASK_CONST(0xf)
+#define EMC_RRD_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define EMC_RRD_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_RRD_0_READ_MASK                     _MK_MASK_CONST(0xf)
+#define EMC_RRD_0_WRITE_MASK                    _MK_MASK_CONST(0xf)
+// specifies the Bank X Act to Bank Y Act command delay.
+#define EMC_RRD_0_RRD_SHIFT                     _MK_SHIFT_CONST(0)
+#define EMC_RRD_0_RRD_FIELD                     (_MK_MASK_CONST(0xf) << EMC_RRD_0_RRD_SHIFT)
+#define EMC_RRD_0_RRD_RANGE                     3:0
+#define EMC_RRD_0_RRD_WOFFSET                   0x0
+#define EMC_RRD_0_RRD_DEFAULT                   _MK_MASK_CONST(0xf)
+#define EMC_RRD_0_RRD_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define EMC_RRD_0_RRD_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_RRD_0_RRD_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EMC_REXT_0  // DRAM timing parameter
+#define EMC_REXT_0                      _MK_ADDR_CONST(0x58)
+#define EMC_REXT_0_SECURE                       0x0
+#define EMC_REXT_0_WORD_COUNT                   0x1
+#define EMC_REXT_0_RESET_VAL                    _MK_MASK_CONST(0x1)
+#define EMC_REXT_0_RESET_MASK                   _MK_MASK_CONST(0xf)
+#define EMC_REXT_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define EMC_REXT_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_REXT_0_READ_MASK                    _MK_MASK_CONST(0xf)
+#define EMC_REXT_0_WRITE_MASK                   _MK_MASK_CONST(0xf)
+// specifies the read to read delay for reads when 
+// multiple physical devices are present.
+#define EMC_REXT_0_REXT_SHIFT                   _MK_SHIFT_CONST(0)
+#define EMC_REXT_0_REXT_FIELD                   (_MK_MASK_CONST(0xf) << EMC_REXT_0_REXT_SHIFT)
+#define EMC_REXT_0_REXT_RANGE                   3:0
+#define EMC_REXT_0_REXT_WOFFSET                 0x0
+#define EMC_REXT_0_REXT_DEFAULT                 _MK_MASK_CONST(0x1)
+#define EMC_REXT_0_REXT_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define EMC_REXT_0_REXT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_REXT_0_REXT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register EMC_WDV_0  // DRAM timing parameter
+#define EMC_WDV_0                       _MK_ADDR_CONST(0x5c)
+#define EMC_WDV_0_SECURE                        0x0
+#define EMC_WDV_0_WORD_COUNT                    0x1
+#define EMC_WDV_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define EMC_WDV_0_RESET_MASK                    _MK_MASK_CONST(0xf)
+#define EMC_WDV_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define EMC_WDV_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_WDV_0_READ_MASK                     _MK_MASK_CONST(0xf)
+#define EMC_WDV_0_WRITE_MASK                    _MK_MASK_CONST(0xf)
+// the number of cycles to post (delay) write data from being asserted
+// to the rams. Set to 0 for DDR1 operation. For DDR1, the delay obtained is the programmed value + 1.
+#define EMC_WDV_0_WDV_SHIFT                     _MK_SHIFT_CONST(0)
+#define EMC_WDV_0_WDV_FIELD                     (_MK_MASK_CONST(0xf) << EMC_WDV_0_WDV_SHIFT)
+#define EMC_WDV_0_WDV_RANGE                     3:0
+#define EMC_WDV_0_WDV_WOFFSET                   0x0
+#define EMC_WDV_0_WDV_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_WDV_0_WDV_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define EMC_WDV_0_WDV_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_WDV_0_WDV_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_WDV_0_WDV_MAX                       _MK_ENUM_CONST(15)
+
+
+// Register EMC_QUSE_0  // DRAM timing parameter
+#define EMC_QUSE_0                      _MK_ADDR_CONST(0x60)
+#define EMC_QUSE_0_SECURE                       0x0
+#define EMC_QUSE_0_WORD_COUNT                   0x1
+#define EMC_QUSE_0_RESET_VAL                    _MK_MASK_CONST(0x2)
+#define EMC_QUSE_0_RESET_MASK                   _MK_MASK_CONST(0xf)
+#define EMC_QUSE_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define EMC_QUSE_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_QUSE_0_READ_MASK                    _MK_MASK_CONST(0xf)
+#define EMC_QUSE_0_WRITE_MASK                   _MK_MASK_CONST(0xf)
+// tells the chip when to look for read return data.
+#define EMC_QUSE_0_QUSE_SHIFT                   _MK_SHIFT_CONST(0)
+#define EMC_QUSE_0_QUSE_FIELD                   (_MK_MASK_CONST(0xf) << EMC_QUSE_0_QUSE_SHIFT)
+#define EMC_QUSE_0_QUSE_RANGE                   3:0
+#define EMC_QUSE_0_QUSE_WOFFSET                 0x0
+#define EMC_QUSE_0_QUSE_DEFAULT                 _MK_MASK_CONST(0x2)
+#define EMC_QUSE_0_QUSE_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define EMC_QUSE_0_QUSE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_QUSE_0_QUSE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register EMC_QRST_0  // DRAM timing parameter
+#define EMC_QRST_0                      _MK_ADDR_CONST(0x64)
+#define EMC_QRST_0_SECURE                       0x0
+#define EMC_QRST_0_WORD_COUNT                   0x1
+#define EMC_QRST_0_RESET_VAL                    _MK_MASK_CONST(0x1)
+#define EMC_QRST_0_RESET_MASK                   _MK_MASK_CONST(0xf)
+#define EMC_QRST_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define EMC_QRST_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_QRST_0_READ_MASK                    _MK_MASK_CONST(0xf)
+#define EMC_QRST_0_WRITE_MASK                   _MK_MASK_CONST(0xf)
+// time from expiration of QSAFE until reset is issued
+#define EMC_QRST_0_QRST_SHIFT                   _MK_SHIFT_CONST(0)
+#define EMC_QRST_0_QRST_FIELD                   (_MK_MASK_CONST(0xf) << EMC_QRST_0_QRST_SHIFT)
+#define EMC_QRST_0_QRST_RANGE                   3:0
+#define EMC_QRST_0_QRST_WOFFSET                 0x0
+#define EMC_QRST_0_QRST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define EMC_QRST_0_QRST_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define EMC_QRST_0_QRST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_QRST_0_QRST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register EMC_QSAFE_0  // DRAM timing parameter
+#define EMC_QSAFE_0                     _MK_ADDR_CONST(0x68)
+#define EMC_QSAFE_0_SECURE                      0x0
+#define EMC_QSAFE_0_WORD_COUNT                  0x1
+#define EMC_QSAFE_0_RESET_VAL                   _MK_MASK_CONST(0x7)
+#define EMC_QSAFE_0_RESET_MASK                  _MK_MASK_CONST(0xf)
+#define EMC_QSAFE_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define EMC_QSAFE_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EMC_QSAFE_0_READ_MASK                   _MK_MASK_CONST(0xf)
+#define EMC_QSAFE_0_WRITE_MASK                  _MK_MASK_CONST(0xf)
+// time from a read command to when it is safe to issue a QRST (delayed by the QRST parameter).
+#define EMC_QSAFE_0_QSAFE_SHIFT                 _MK_SHIFT_CONST(0)
+#define EMC_QSAFE_0_QSAFE_FIELD                 (_MK_MASK_CONST(0xf) << EMC_QSAFE_0_QSAFE_SHIFT)
+#define EMC_QSAFE_0_QSAFE_RANGE                 3:0
+#define EMC_QSAFE_0_QSAFE_WOFFSET                       0x0
+#define EMC_QSAFE_0_QSAFE_DEFAULT                       _MK_MASK_CONST(0x7)
+#define EMC_QSAFE_0_QSAFE_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define EMC_QSAFE_0_QSAFE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_QSAFE_0_QSAFE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EMC_RDV_0  // DRAM timing parameter
+#define EMC_RDV_0                       _MK_ADDR_CONST(0x6c)
+#define EMC_RDV_0_SECURE                        0x0
+#define EMC_RDV_0_WORD_COUNT                    0x1
+#define EMC_RDV_0_RESET_VAL                     _MK_MASK_CONST(0x8)
+#define EMC_RDV_0_RESET_MASK                    _MK_MASK_CONST(0x1f)
+#define EMC_RDV_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define EMC_RDV_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_RDV_0_READ_MASK                     _MK_MASK_CONST(0x1f)
+#define EMC_RDV_0_WRITE_MASK                    _MK_MASK_CONST(0x1f)
+// time from read command to latching the read data from the pad macros.
+#define EMC_RDV_0_RDV_SHIFT                     _MK_SHIFT_CONST(0)
+#define EMC_RDV_0_RDV_FIELD                     (_MK_MASK_CONST(0x1f) << EMC_RDV_0_RDV_SHIFT)
+#define EMC_RDV_0_RDV_RANGE                     4:0
+#define EMC_RDV_0_RDV_WOFFSET                   0x0
+#define EMC_RDV_0_RDV_DEFAULT                   _MK_MASK_CONST(0x8)
+#define EMC_RDV_0_RDV_DEFAULT_MASK                      _MK_MASK_CONST(0x1f)
+#define EMC_RDV_0_RDV_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_RDV_0_RDV_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_RDV_0_RDV_MAX                       _MK_ENUM_CONST(15)
+
+
+// Register EMC_REFRESH_0  // DRAM timing parameter
+#define EMC_REFRESH_0                   _MK_ADDR_CONST(0x70)
+#define EMC_REFRESH_0_SECURE                    0x0
+#define EMC_REFRESH_0_WORD_COUNT                        0x1
+#define EMC_REFRESH_0_RESET_VAL                         _MK_MASK_CONST(0x1f)
+#define EMC_REFRESH_0_RESET_MASK                        _MK_MASK_CONST(0x1f)
+#define EMC_REFRESH_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define EMC_REFRESH_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_REFRESH_0_READ_MASK                         _MK_MASK_CONST(0xffff)
+#define EMC_REFRESH_0_WRITE_MASK                        _MK_MASK_CONST(0xffff)
+#define EMC_REFRESH_0_REFRESH_LO_SHIFT                  _MK_SHIFT_CONST(0)
+#define EMC_REFRESH_0_REFRESH_LO_FIELD                  (_MK_MASK_CONST(0x1f) << EMC_REFRESH_0_REFRESH_LO_SHIFT)
+#define EMC_REFRESH_0_REFRESH_LO_RANGE                  4:0
+#define EMC_REFRESH_0_REFRESH_LO_WOFFSET                        0x0
+#define EMC_REFRESH_0_REFRESH_LO_DEFAULT                        _MK_MASK_CONST(0x1f)
+#define EMC_REFRESH_0_REFRESH_LO_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define EMC_REFRESH_0_REFRESH_LO_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_REFRESH_0_REFRESH_LO_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_REFRESH_0_REFRESH_LO_INIT_ENUM                      MAX
+#define EMC_REFRESH_0_REFRESH_LO_MAX                    _MK_ENUM_CONST(31)
+
+// specifies the interval between refresh requests.
+#define EMC_REFRESH_0_REFRESH_SHIFT                     _MK_SHIFT_CONST(5)
+#define EMC_REFRESH_0_REFRESH_FIELD                     (_MK_MASK_CONST(0x7ff) << EMC_REFRESH_0_REFRESH_SHIFT)
+#define EMC_REFRESH_0_REFRESH_RANGE                     15:5
+#define EMC_REFRESH_0_REFRESH_WOFFSET                   0x0
+#define EMC_REFRESH_0_REFRESH_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_REFRESH_0_REFRESH_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_REFRESH_0_REFRESH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_REFRESH_0_REFRESH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EMC_BURST_REFRESH_NUM_0  // DRAM timing parameter
+#define EMC_BURST_REFRESH_NUM_0                 _MK_ADDR_CONST(0x74)
+#define EMC_BURST_REFRESH_NUM_0_SECURE                  0x0
+#define EMC_BURST_REFRESH_NUM_0_WORD_COUNT                      0x1
+#define EMC_BURST_REFRESH_NUM_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define EMC_BURST_REFRESH_NUM_0_RESET_MASK                      _MK_MASK_CONST(0xf)
+#define EMC_BURST_REFRESH_NUM_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EMC_BURST_REFRESH_NUM_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_BURST_REFRESH_NUM_0_READ_MASK                       _MK_MASK_CONST(0xf)
+#define EMC_BURST_REFRESH_NUM_0_WRITE_MASK                      _MK_MASK_CONST(0xf)
+// specify the refresh burst count.
+#define EMC_BURST_REFRESH_NUM_0_BURST_REFRESH_NUM_SHIFT                 _MK_SHIFT_CONST(0)
+#define EMC_BURST_REFRESH_NUM_0_BURST_REFRESH_NUM_FIELD                 (_MK_MASK_CONST(0xf) << EMC_BURST_REFRESH_NUM_0_BURST_REFRESH_NUM_SHIFT)
+#define EMC_BURST_REFRESH_NUM_0_BURST_REFRESH_NUM_RANGE                 3:0
+#define EMC_BURST_REFRESH_NUM_0_BURST_REFRESH_NUM_WOFFSET                       0x0
+#define EMC_BURST_REFRESH_NUM_0_BURST_REFRESH_NUM_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_BURST_REFRESH_NUM_0_BURST_REFRESH_NUM_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define EMC_BURST_REFRESH_NUM_0_BURST_REFRESH_NUM_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_BURST_REFRESH_NUM_0_BURST_REFRESH_NUM_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_BURST_REFRESH_NUM_0_BURST_REFRESH_NUM_INIT_ENUM                     BR1
+#define EMC_BURST_REFRESH_NUM_0_BURST_REFRESH_NUM_BR1                   _MK_ENUM_CONST(0)
+#define EMC_BURST_REFRESH_NUM_0_BURST_REFRESH_NUM_BR2                   _MK_ENUM_CONST(1)
+#define EMC_BURST_REFRESH_NUM_0_BURST_REFRESH_NUM_BR4                   _MK_ENUM_CONST(2)
+#define EMC_BURST_REFRESH_NUM_0_BURST_REFRESH_NUM_BR8                   _MK_ENUM_CONST(3)
+#define EMC_BURST_REFRESH_NUM_0_BURST_REFRESH_NUM_BR16                  _MK_ENUM_CONST(4)
+#define EMC_BURST_REFRESH_NUM_0_BURST_REFRESH_NUM_BR32                  _MK_ENUM_CONST(5)
+#define EMC_BURST_REFRESH_NUM_0_BURST_REFRESH_NUM_BR64                  _MK_ENUM_CONST(6)
+#define EMC_BURST_REFRESH_NUM_0_BURST_REFRESH_NUM_BR128                 _MK_ENUM_CONST(7)
+#define EMC_BURST_REFRESH_NUM_0_BURST_REFRESH_NUM_BR256                 _MK_ENUM_CONST(8)
+#define EMC_BURST_REFRESH_NUM_0_BURST_REFRESH_NUM_BR512                 _MK_ENUM_CONST(9)
+#define EMC_BURST_REFRESH_NUM_0_BURST_REFRESH_NUM_MAX                   _MK_ENUM_CONST(9)
+
+
+// Register EMC_PDEX2WR_0  // DRAM timing parameter
+#define EMC_PDEX2WR_0                   _MK_ADDR_CONST(0x78)
+#define EMC_PDEX2WR_0_SECURE                    0x0
+#define EMC_PDEX2WR_0_WORD_COUNT                        0x1
+#define EMC_PDEX2WR_0_RESET_VAL                         _MK_MASK_CONST(0xe)
+#define EMC_PDEX2WR_0_RESET_MASK                        _MK_MASK_CONST(0xf)
+#define EMC_PDEX2WR_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define EMC_PDEX2WR_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_PDEX2WR_0_READ_MASK                         _MK_MASK_CONST(0xf)
+#define EMC_PDEX2WR_0_WRITE_MASK                        _MK_MASK_CONST(0xf)
+// specify the timing delay from exit of powerdown mode to a write command.
+// Largest allowed value is 14
+#define EMC_PDEX2WR_0_PDEX2WR_SHIFT                     _MK_SHIFT_CONST(0)
+#define EMC_PDEX2WR_0_PDEX2WR_FIELD                     (_MK_MASK_CONST(0xf) << EMC_PDEX2WR_0_PDEX2WR_SHIFT)
+#define EMC_PDEX2WR_0_PDEX2WR_RANGE                     3:0
+#define EMC_PDEX2WR_0_PDEX2WR_WOFFSET                   0x0
+#define EMC_PDEX2WR_0_PDEX2WR_DEFAULT                   _MK_MASK_CONST(0xe)
+#define EMC_PDEX2WR_0_PDEX2WR_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define EMC_PDEX2WR_0_PDEX2WR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_PDEX2WR_0_PDEX2WR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EMC_PDEX2RD_0  // DRAM timing parameter
+#define EMC_PDEX2RD_0                   _MK_ADDR_CONST(0x7c)
+#define EMC_PDEX2RD_0_SECURE                    0x0
+#define EMC_PDEX2RD_0_WORD_COUNT                        0x1
+#define EMC_PDEX2RD_0_RESET_VAL                         _MK_MASK_CONST(0xe)
+#define EMC_PDEX2RD_0_RESET_MASK                        _MK_MASK_CONST(0xf)
+#define EMC_PDEX2RD_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define EMC_PDEX2RD_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_PDEX2RD_0_READ_MASK                         _MK_MASK_CONST(0xf)
+#define EMC_PDEX2RD_0_WRITE_MASK                        _MK_MASK_CONST(0xf)
+// specify the timing delay from exit of powerdown mode to a read command.
+// Largest allowed value is 14
+#define EMC_PDEX2RD_0_PDEX2RD_SHIFT                     _MK_SHIFT_CONST(0)
+#define EMC_PDEX2RD_0_PDEX2RD_FIELD                     (_MK_MASK_CONST(0xf) << EMC_PDEX2RD_0_PDEX2RD_SHIFT)
+#define EMC_PDEX2RD_0_PDEX2RD_RANGE                     3:0
+#define EMC_PDEX2RD_0_PDEX2RD_WOFFSET                   0x0
+#define EMC_PDEX2RD_0_PDEX2RD_DEFAULT                   _MK_MASK_CONST(0xe)
+#define EMC_PDEX2RD_0_PDEX2RD_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define EMC_PDEX2RD_0_PDEX2RD_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_PDEX2RD_0_PDEX2RD_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EMC_PCHG2PDEN_0  // DRAM timing parameter
+#define EMC_PCHG2PDEN_0                 _MK_ADDR_CONST(0x80)
+#define EMC_PCHG2PDEN_0_SECURE                  0x0
+#define EMC_PCHG2PDEN_0_WORD_COUNT                      0x1
+#define EMC_PCHG2PDEN_0_RESET_VAL                       _MK_MASK_CONST(0xf)
+#define EMC_PCHG2PDEN_0_RESET_MASK                      _MK_MASK_CONST(0x1f)
+#define EMC_PCHG2PDEN_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EMC_PCHG2PDEN_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_PCHG2PDEN_0_READ_MASK                       _MK_MASK_CONST(0x1f)
+#define EMC_PCHG2PDEN_0_WRITE_MASK                      _MK_MASK_CONST(0x1f)
+//  specify the timing delay from a precharge command to powerdown entry.
+#define EMC_PCHG2PDEN_0_PCHG2PDEN_SHIFT                 _MK_SHIFT_CONST(0)
+#define EMC_PCHG2PDEN_0_PCHG2PDEN_FIELD                 (_MK_MASK_CONST(0x1f) << EMC_PCHG2PDEN_0_PCHG2PDEN_SHIFT)
+#define EMC_PCHG2PDEN_0_PCHG2PDEN_RANGE                 4:0
+#define EMC_PCHG2PDEN_0_PCHG2PDEN_WOFFSET                       0x0
+#define EMC_PCHG2PDEN_0_PCHG2PDEN_DEFAULT                       _MK_MASK_CONST(0xf)
+#define EMC_PCHG2PDEN_0_PCHG2PDEN_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define EMC_PCHG2PDEN_0_PCHG2PDEN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_PCHG2PDEN_0_PCHG2PDEN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EMC_ACT2PDEN_0  // DRAM timing parameter
+#define EMC_ACT2PDEN_0                  _MK_ADDR_CONST(0x84)
+#define EMC_ACT2PDEN_0_SECURE                   0x0
+#define EMC_ACT2PDEN_0_WORD_COUNT                       0x1
+#define EMC_ACT2PDEN_0_RESET_VAL                        _MK_MASK_CONST(0xf)
+#define EMC_ACT2PDEN_0_RESET_MASK                       _MK_MASK_CONST(0x1f)
+#define EMC_ACT2PDEN_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define EMC_ACT2PDEN_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_ACT2PDEN_0_READ_MASK                        _MK_MASK_CONST(0x1f)
+#define EMC_ACT2PDEN_0_WRITE_MASK                       _MK_MASK_CONST(0x1f)
+// specify the timing delay from an activate, mrs or emrs command to powerdown entry.
+#define EMC_ACT2PDEN_0_ACT2PDEN_SHIFT                   _MK_SHIFT_CONST(0)
+#define EMC_ACT2PDEN_0_ACT2PDEN_FIELD                   (_MK_MASK_CONST(0x1f) << EMC_ACT2PDEN_0_ACT2PDEN_SHIFT)
+#define EMC_ACT2PDEN_0_ACT2PDEN_RANGE                   4:0
+#define EMC_ACT2PDEN_0_ACT2PDEN_WOFFSET                 0x0
+#define EMC_ACT2PDEN_0_ACT2PDEN_DEFAULT                 _MK_MASK_CONST(0xf)
+#define EMC_ACT2PDEN_0_ACT2PDEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1f)
+#define EMC_ACT2PDEN_0_ACT2PDEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_ACT2PDEN_0_ACT2PDEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register EMC_AR2PDEN_0  // DRAM timing parameter
+#define EMC_AR2PDEN_0                   _MK_ADDR_CONST(0x88)
+#define EMC_AR2PDEN_0_SECURE                    0x0
+#define EMC_AR2PDEN_0_WORD_COUNT                        0x1
+#define EMC_AR2PDEN_0_RESET_VAL                         _MK_MASK_CONST(0x1f)
+#define EMC_AR2PDEN_0_RESET_MASK                        _MK_MASK_CONST(0x1f)
+#define EMC_AR2PDEN_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define EMC_AR2PDEN_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_AR2PDEN_0_READ_MASK                         _MK_MASK_CONST(0x1f)
+#define EMC_AR2PDEN_0_WRITE_MASK                        _MK_MASK_CONST(0x1f)
+// specify the timing delay from an autorefresh command to powerdown entry.
+#define EMC_AR2PDEN_0_AR2PDEN_SHIFT                     _MK_SHIFT_CONST(0)
+#define EMC_AR2PDEN_0_AR2PDEN_FIELD                     (_MK_MASK_CONST(0x1f) << EMC_AR2PDEN_0_AR2PDEN_SHIFT)
+#define EMC_AR2PDEN_0_AR2PDEN_RANGE                     4:0
+#define EMC_AR2PDEN_0_AR2PDEN_WOFFSET                   0x0
+#define EMC_AR2PDEN_0_AR2PDEN_DEFAULT                   _MK_MASK_CONST(0x1f)
+#define EMC_AR2PDEN_0_AR2PDEN_DEFAULT_MASK                      _MK_MASK_CONST(0x1f)
+#define EMC_AR2PDEN_0_AR2PDEN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_AR2PDEN_0_AR2PDEN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EMC_RW2PDEN_0  // DRAM timing parameter
+#define EMC_RW2PDEN_0                   _MK_ADDR_CONST(0x8c)
+#define EMC_RW2PDEN_0_SECURE                    0x0
+#define EMC_RW2PDEN_0_WORD_COUNT                        0x1
+#define EMC_RW2PDEN_0_RESET_VAL                         _MK_MASK_CONST(0xf)
+#define EMC_RW2PDEN_0_RESET_MASK                        _MK_MASK_CONST(0x3f)
+#define EMC_RW2PDEN_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define EMC_RW2PDEN_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_RW2PDEN_0_READ_MASK                         _MK_MASK_CONST(0x3f)
+#define EMC_RW2PDEN_0_WRITE_MASK                        _MK_MASK_CONST(0x3f)
+// specify the timing delay from a read/write command to powerdown entry.
+//  Auto-precharge timing must be taken into account when programming this field (affects lpddr & lpddr2/ddr2 differently).
+#define EMC_RW2PDEN_0_RW2PDEN_SHIFT                     _MK_SHIFT_CONST(0)
+#define EMC_RW2PDEN_0_RW2PDEN_FIELD                     (_MK_MASK_CONST(0x3f) << EMC_RW2PDEN_0_RW2PDEN_SHIFT)
+#define EMC_RW2PDEN_0_RW2PDEN_RANGE                     5:0
+#define EMC_RW2PDEN_0_RW2PDEN_WOFFSET                   0x0
+#define EMC_RW2PDEN_0_RW2PDEN_DEFAULT                   _MK_MASK_CONST(0xf)
+#define EMC_RW2PDEN_0_RW2PDEN_DEFAULT_MASK                      _MK_MASK_CONST(0x3f)
+#define EMC_RW2PDEN_0_RW2PDEN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_RW2PDEN_0_RW2PDEN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EMC_TXSR_0  // DRAM timing parameter
+#define EMC_TXSR_0                      _MK_ADDR_CONST(0x90)
+#define EMC_TXSR_0_SECURE                       0x0
+#define EMC_TXSR_0_WORD_COUNT                   0x1
+#define EMC_TXSR_0_RESET_VAL                    _MK_MASK_CONST(0x7ff)
+#define EMC_TXSR_0_RESET_MASK                   _MK_MASK_CONST(0xfff)
+#define EMC_TXSR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define EMC_TXSR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_TXSR_0_READ_MASK                    _MK_MASK_CONST(0xfff)
+#define EMC_TXSR_0_WRITE_MASK                   _MK_MASK_CONST(0xfff)
+// cycles between self-refresh exit & first DRAM command
+// Largest allowed value is 0xffe
+#define EMC_TXSR_0_TXSR_SHIFT                   _MK_SHIFT_CONST(0)
+#define EMC_TXSR_0_TXSR_FIELD                   (_MK_MASK_CONST(0xfff) << EMC_TXSR_0_TXSR_SHIFT)
+#define EMC_TXSR_0_TXSR_RANGE                   11:0
+#define EMC_TXSR_0_TXSR_WOFFSET                 0x0
+#define EMC_TXSR_0_TXSR_DEFAULT                 _MK_MASK_CONST(0x7ff)
+#define EMC_TXSR_0_TXSR_DEFAULT_MASK                    _MK_MASK_CONST(0xfff)
+#define EMC_TXSR_0_TXSR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_TXSR_0_TXSR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register EMC_TCKE_0  // DRAM timing parameter
+#define EMC_TCKE_0                      _MK_ADDR_CONST(0x94)
+#define EMC_TCKE_0_SECURE                       0x0
+#define EMC_TCKE_0_WORD_COUNT                   0x1
+#define EMC_TCKE_0_RESET_VAL                    _MK_MASK_CONST(0xe)
+#define EMC_TCKE_0_RESET_MASK                   _MK_MASK_CONST(0xf)
+#define EMC_TCKE_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define EMC_TCKE_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_TCKE_0_READ_MASK                    _MK_MASK_CONST(0xf)
+#define EMC_TCKE_0_WRITE_MASK                   _MK_MASK_CONST(0xf)
+// specify minimum CKE pulse width.
+#define EMC_TCKE_0_TCKE_SHIFT                   _MK_SHIFT_CONST(0)
+#define EMC_TCKE_0_TCKE_FIELD                   (_MK_MASK_CONST(0xf) << EMC_TCKE_0_TCKE_SHIFT)
+#define EMC_TCKE_0_TCKE_RANGE                   3:0
+#define EMC_TCKE_0_TCKE_WOFFSET                 0x0
+#define EMC_TCKE_0_TCKE_DEFAULT                 _MK_MASK_CONST(0xe)
+#define EMC_TCKE_0_TCKE_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define EMC_TCKE_0_TCKE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_TCKE_0_TCKE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register EMC_TFAW_0  // DRAM timing parameter
+#define EMC_TFAW_0                      _MK_ADDR_CONST(0x98)
+#define EMC_TFAW_0_SECURE                       0x0
+#define EMC_TFAW_0_WORD_COUNT                   0x1
+#define EMC_TFAW_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define EMC_TFAW_0_RESET_MASK                   _MK_MASK_CONST(0x3f)
+#define EMC_TFAW_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define EMC_TFAW_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_TFAW_0_READ_MASK                    _MK_MASK_CONST(0x3f)
+#define EMC_TFAW_0_WRITE_MASK                   _MK_MASK_CONST(0x3f)
+// specify the width of the FAW (four-activate window) for 8-bank devices.
+// Set to 0 to disable this timing check. Only 4 activates may occur withing the rolling window. 
+#define EMC_TFAW_0_TFAW_SHIFT                   _MK_SHIFT_CONST(0)
+#define EMC_TFAW_0_TFAW_FIELD                   (_MK_MASK_CONST(0x3f) << EMC_TFAW_0_TFAW_SHIFT)
+#define EMC_TFAW_0_TFAW_RANGE                   5:0
+#define EMC_TFAW_0_TFAW_WOFFSET                 0x0
+#define EMC_TFAW_0_TFAW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_TFAW_0_TFAW_DEFAULT_MASK                    _MK_MASK_CONST(0x3f)
+#define EMC_TFAW_0_TFAW_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_TFAW_0_TFAW_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register EMC_TRPAB_0  // DRAM timing parameter
+#define EMC_TRPAB_0                     _MK_ADDR_CONST(0x9c)
+#define EMC_TRPAB_0_SECURE                      0x0
+#define EMC_TRPAB_0_WORD_COUNT                  0x1
+#define EMC_TRPAB_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define EMC_TRPAB_0_RESET_MASK                  _MK_MASK_CONST(0x3f)
+#define EMC_TRPAB_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define EMC_TRPAB_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EMC_TRPAB_0_READ_MASK                   _MK_MASK_CONST(0x3f)
+#define EMC_TRPAB_0_WRITE_MASK                  _MK_MASK_CONST(0x3f)
+// specify precharge-all tRP allowance for 8-bank devices.
+// Setting this field to 0 will cause EMC to use TRP.TRP for precharge-all.
+#define EMC_TRPAB_0_TRPAB_SHIFT                 _MK_SHIFT_CONST(0)
+#define EMC_TRPAB_0_TRPAB_FIELD                 (_MK_MASK_CONST(0x3f) << EMC_TRPAB_0_TRPAB_SHIFT)
+#define EMC_TRPAB_0_TRPAB_RANGE                 5:0
+#define EMC_TRPAB_0_TRPAB_WOFFSET                       0x0
+#define EMC_TRPAB_0_TRPAB_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_TRPAB_0_TRPAB_DEFAULT_MASK                  _MK_MASK_CONST(0x3f)
+#define EMC_TRPAB_0_TRPAB_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_TRPAB_0_TRPAB_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EMC_TCLKSTABLE_0  // DRAM timing parameter
+#define EMC_TCLKSTABLE_0                        _MK_ADDR_CONST(0xa0)
+#define EMC_TCLKSTABLE_0_SECURE                         0x0
+#define EMC_TCLKSTABLE_0_WORD_COUNT                     0x1
+#define EMC_TCLKSTABLE_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define EMC_TCLKSTABLE_0_RESET_MASK                     _MK_MASK_CONST(0xf)
+#define EMC_TCLKSTABLE_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define EMC_TCLKSTABLE_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_TCLKSTABLE_0_READ_MASK                      _MK_MASK_CONST(0xf)
+#define EMC_TCLKSTABLE_0_WRITE_MASK                     _MK_MASK_CONST(0xf)
+// specify minimum number of cycles of a stable clock period
+// prior to exiting powerdown or self-refresh modes.
+#define EMC_TCLKSTABLE_0_TCLKSTABLE_SHIFT                       _MK_SHIFT_CONST(0)
+#define EMC_TCLKSTABLE_0_TCLKSTABLE_FIELD                       (_MK_MASK_CONST(0xf) << EMC_TCLKSTABLE_0_TCLKSTABLE_SHIFT)
+#define EMC_TCLKSTABLE_0_TCLKSTABLE_RANGE                       3:0
+#define EMC_TCLKSTABLE_0_TCLKSTABLE_WOFFSET                     0x0
+#define EMC_TCLKSTABLE_0_TCLKSTABLE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_TCLKSTABLE_0_TCLKSTABLE_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define EMC_TCLKSTABLE_0_TCLKSTABLE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_TCLKSTABLE_0_TCLKSTABLE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register EMC_TCLKSTOP_0  // DRAM timing parameter
+#define EMC_TCLKSTOP_0                  _MK_ADDR_CONST(0xa4)
+#define EMC_TCLKSTOP_0_SECURE                   0x0
+#define EMC_TCLKSTOP_0_WORD_COUNT                       0x1
+#define EMC_TCLKSTOP_0_RESET_VAL                        _MK_MASK_CONST(0x2)
+#define EMC_TCLKSTOP_0_RESET_MASK                       _MK_MASK_CONST(0xf)
+#define EMC_TCLKSTOP_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define EMC_TCLKSTOP_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_TCLKSTOP_0_READ_MASK                        _MK_MASK_CONST(0xf)
+#define EMC_TCLKSTOP_0_WRITE_MASK                       _MK_MASK_CONST(0xf)
+// delay from last command to stopping the external clock to DRAM devices.
+#define EMC_TCLKSTOP_0_TCLKSTOP_SHIFT                   _MK_SHIFT_CONST(0)
+#define EMC_TCLKSTOP_0_TCLKSTOP_FIELD                   (_MK_MASK_CONST(0xf) << EMC_TCLKSTOP_0_TCLKSTOP_SHIFT)
+#define EMC_TCLKSTOP_0_TCLKSTOP_RANGE                   3:0
+#define EMC_TCLKSTOP_0_TCLKSTOP_WOFFSET                 0x0
+#define EMC_TCLKSTOP_0_TCLKSTOP_DEFAULT                 _MK_MASK_CONST(0x2)
+#define EMC_TCLKSTOP_0_TCLKSTOP_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define EMC_TCLKSTOP_0_TCLKSTOP_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_TCLKSTOP_0_TCLKSTOP_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register EMC_TREFBW_0  // DRAM timing parameter
+#define EMC_TREFBW_0                    _MK_ADDR_CONST(0xa8)
+#define EMC_TREFBW_0_SECURE                     0x0
+#define EMC_TREFBW_0_WORD_COUNT                         0x1
+#define EMC_TREFBW_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define EMC_TREFBW_0_RESET_MASK                         _MK_MASK_CONST(0x3fff)
+#define EMC_TREFBW_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define EMC_TREFBW_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_TREFBW_0_READ_MASK                  _MK_MASK_CONST(0x3fff)
+#define EMC_TREFBW_0_WRITE_MASK                         _MK_MASK_CONST(0x3fff)
+// specify the width of the burst-refresh window.
+// If set to a non-zero value, only 8 refreshes will occur in this rolling window.
+// Set to 0 to disable this timing check. 
+#define EMC_TREFBW_0_TREFBW_SHIFT                       _MK_SHIFT_CONST(0)
+#define EMC_TREFBW_0_TREFBW_FIELD                       (_MK_MASK_CONST(0x3fff) << EMC_TREFBW_0_TREFBW_SHIFT)
+#define EMC_TREFBW_0_TREFBW_RANGE                       13:0
+#define EMC_TREFBW_0_TREFBW_WOFFSET                     0x0
+#define EMC_TREFBW_0_TREFBW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_TREFBW_0_TREFBW_DEFAULT_MASK                        _MK_MASK_CONST(0x3fff)
+#define EMC_TREFBW_0_TREFBW_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_TREFBW_0_TREFBW_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register EMC_QUSE_EXTRA_0  
+#define EMC_QUSE_EXTRA_0                        _MK_ADDR_CONST(0xac)
+#define EMC_QUSE_EXTRA_0_SECURE                         0x0
+#define EMC_QUSE_EXTRA_0_WORD_COUNT                     0x1
+#define EMC_QUSE_EXTRA_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define EMC_QUSE_EXTRA_0_RESET_MASK                     _MK_MASK_CONST(0xf)
+#define EMC_QUSE_EXTRA_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define EMC_QUSE_EXTRA_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_QUSE_EXTRA_0_READ_MASK                      _MK_MASK_CONST(0xf)
+#define EMC_QUSE_EXTRA_0_WRITE_MASK                     _MK_MASK_CONST(0xf)
+#define EMC_QUSE_EXTRA_0_QUSE_EXTRA_SHIFT                       _MK_SHIFT_CONST(0)
+#define EMC_QUSE_EXTRA_0_QUSE_EXTRA_FIELD                       (_MK_MASK_CONST(0xf) << EMC_QUSE_EXTRA_0_QUSE_EXTRA_SHIFT)
+#define EMC_QUSE_EXTRA_0_QUSE_EXTRA_RANGE                       3:0
+#define EMC_QUSE_EXTRA_0_QUSE_EXTRA_WOFFSET                     0x0
+#define EMC_QUSE_EXTRA_0_QUSE_EXTRA_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_QUSE_EXTRA_0_QUSE_EXTRA_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define EMC_QUSE_EXTRA_0_QUSE_EXTRA_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_QUSE_EXTRA_0_QUSE_EXTRA_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register EMC_ODT_WRITE_0  
+#define EMC_ODT_WRITE_0                 _MK_ADDR_CONST(0xb0)
+#define EMC_ODT_WRITE_0_SECURE                  0x0
+#define EMC_ODT_WRITE_0_WORD_COUNT                      0x1
+#define EMC_ODT_WRITE_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define EMC_ODT_WRITE_0_RESET_MASK                      _MK_MASK_CONST(0xc0000007)
+#define EMC_ODT_WRITE_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EMC_ODT_WRITE_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_ODT_WRITE_0_READ_MASK                       _MK_MASK_CONST(0xc0000007)
+#define EMC_ODT_WRITE_0_WRITE_MASK                      _MK_MASK_CONST(0xc0000007)
+// Set this field = ABS ( WL - ceiling(tAOND) - 2 ).
+// The valid programming range is 0 <= ODT_WR_DELAY <= 2 if ODT_B4_WRITE=0, 0 <= ODT_WR_DELAY <= 1 if ODT_B4_WRITE=1
+#define EMC_ODT_WRITE_0_ODT_WR_DELAY_SHIFT                      _MK_SHIFT_CONST(0)
+#define EMC_ODT_WRITE_0_ODT_WR_DELAY_FIELD                      (_MK_MASK_CONST(0x7) << EMC_ODT_WRITE_0_ODT_WR_DELAY_SHIFT)
+#define EMC_ODT_WRITE_0_ODT_WR_DELAY_RANGE                      2:0
+#define EMC_ODT_WRITE_0_ODT_WR_DELAY_WOFFSET                    0x0
+#define EMC_ODT_WRITE_0_ODT_WR_DELAY_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_ODT_WRITE_0_ODT_WR_DELAY_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define EMC_ODT_WRITE_0_ODT_WR_DELAY_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_ODT_WRITE_0_ODT_WR_DELAY_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// If this field == 1, ODT is turned on ODT_WR_DELAY cycles prior to dram WRITE command.
+// If this field == 0, ODT is turned on ODT_WR_DELAY cycles after dram WRITE command.
+// Set ODT_B4_WRITE to 1 if ( WL - ceiling(tAOND) - 2 ) < 0.
+#define EMC_ODT_WRITE_0_ODT_B4_WRITE_SHIFT                      _MK_SHIFT_CONST(30)
+#define EMC_ODT_WRITE_0_ODT_B4_WRITE_FIELD                      (_MK_MASK_CONST(0x1) << EMC_ODT_WRITE_0_ODT_B4_WRITE_SHIFT)
+#define EMC_ODT_WRITE_0_ODT_B4_WRITE_RANGE                      30:30
+#define EMC_ODT_WRITE_0_ODT_B4_WRITE_WOFFSET                    0x0
+#define EMC_ODT_WRITE_0_ODT_B4_WRITE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_ODT_WRITE_0_ODT_B4_WRITE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define EMC_ODT_WRITE_0_ODT_B4_WRITE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_ODT_WRITE_0_ODT_B4_WRITE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// enables ODT to be turned on prior to issuing write to DRAM.
+// If ENABLE_ODT_DURING_WRITE = 1 and DISABLE_ODT_DURING_READ = 0, ODT will always be enabled after 1st write.
+#define EMC_ODT_WRITE_0_ENABLE_ODT_DURING_WRITE_SHIFT                   _MK_SHIFT_CONST(31)
+#define EMC_ODT_WRITE_0_ENABLE_ODT_DURING_WRITE_FIELD                   (_MK_MASK_CONST(0x1) << EMC_ODT_WRITE_0_ENABLE_ODT_DURING_WRITE_SHIFT)
+#define EMC_ODT_WRITE_0_ENABLE_ODT_DURING_WRITE_RANGE                   31:31
+#define EMC_ODT_WRITE_0_ENABLE_ODT_DURING_WRITE_WOFFSET                 0x0
+#define EMC_ODT_WRITE_0_ENABLE_ODT_DURING_WRITE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_ODT_WRITE_0_ENABLE_ODT_DURING_WRITE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define EMC_ODT_WRITE_0_ENABLE_ODT_DURING_WRITE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_ODT_WRITE_0_ENABLE_ODT_DURING_WRITE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register EMC_ODT_READ_0  
+#define EMC_ODT_READ_0                  _MK_ADDR_CONST(0xb4)
+#define EMC_ODT_READ_0_SECURE                   0x0
+#define EMC_ODT_READ_0_WORD_COUNT                       0x1
+#define EMC_ODT_READ_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define EMC_ODT_READ_0_RESET_MASK                       _MK_MASK_CONST(0xc0000007)
+#define EMC_ODT_READ_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define EMC_ODT_READ_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_ODT_READ_0_READ_MASK                        _MK_MASK_CONST(0xc0000007)
+#define EMC_ODT_READ_0_WRITE_MASK                       _MK_MASK_CONST(0xc0000007)
+// Set this field = ABS ( RL - ceiling(tAOFD) - 2 ).
+// The valid programming range is 0 <= ODT_RD_DELAY <= 2 if ODT_B4_READ=0, 0 <= ODT_RD_DELAY <= 1 if ODT_B4_READ=1
+#define EMC_ODT_READ_0_ODT_RD_DELAY_SHIFT                       _MK_SHIFT_CONST(0)
+#define EMC_ODT_READ_0_ODT_RD_DELAY_FIELD                       (_MK_MASK_CONST(0x7) << EMC_ODT_READ_0_ODT_RD_DELAY_SHIFT)
+#define EMC_ODT_READ_0_ODT_RD_DELAY_RANGE                       2:0
+#define EMC_ODT_READ_0_ODT_RD_DELAY_WOFFSET                     0x0
+#define EMC_ODT_READ_0_ODT_RD_DELAY_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_ODT_READ_0_ODT_RD_DELAY_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
+#define EMC_ODT_READ_0_ODT_RD_DELAY_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_ODT_READ_0_ODT_RD_DELAY_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// If this field == 1, ODT is turned off ODT_RD_DELAY cycles prior to dram READ command.
+// If this field == 0, ODT is turned off ODT_RD_DELAY cycles after dram READ command.
+// Set ODT_B4_READ to 1 if ( RL - ceiling(tAOFD) - 2 ) < 0.
+#define EMC_ODT_READ_0_ODT_B4_READ_SHIFT                        _MK_SHIFT_CONST(30)
+#define EMC_ODT_READ_0_ODT_B4_READ_FIELD                        (_MK_MASK_CONST(0x1) << EMC_ODT_READ_0_ODT_B4_READ_SHIFT)
+#define EMC_ODT_READ_0_ODT_B4_READ_RANGE                        30:30
+#define EMC_ODT_READ_0_ODT_B4_READ_WOFFSET                      0x0
+#define EMC_ODT_READ_0_ODT_B4_READ_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_ODT_READ_0_ODT_B4_READ_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define EMC_ODT_READ_0_ODT_B4_READ_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_ODT_READ_0_ODT_B4_READ_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// enables ODT to be turned off prior to issuing read to DRAM.
+// If this field == 0, ODT state will not be changed for reads. 
+// If this field == 1, Turn off ODT prior to READ command
+//   (has no effect if ODT ENABLE_ODT_DURING_WRITE == 0, as ODT will always be disabled). 
+#define EMC_ODT_READ_0_DISABLE_ODT_DURING_READ_SHIFT                    _MK_SHIFT_CONST(31)
+#define EMC_ODT_READ_0_DISABLE_ODT_DURING_READ_FIELD                    (_MK_MASK_CONST(0x1) << EMC_ODT_READ_0_DISABLE_ODT_DURING_READ_SHIFT)
+#define EMC_ODT_READ_0_DISABLE_ODT_DURING_READ_RANGE                    31:31
+#define EMC_ODT_READ_0_DISABLE_ODT_DURING_READ_WOFFSET                  0x0
+#define EMC_ODT_READ_0_DISABLE_ODT_DURING_READ_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_ODT_READ_0_DISABLE_ODT_DURING_READ_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define EMC_ODT_READ_0_DISABLE_ODT_DURING_READ_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_ODT_READ_0_DISABLE_ODT_DURING_READ_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Reserved address 184 [0xb8] 
+
+// Reserved address 188 [0xbc] 
+
+// Reserved address 192 [0xc0] 
+
+// Reserved address 196 [0xc4] 
+
+// Reserved address 200 [0xc8] 
+
+// Register EMC_MRS_0  // Command trigger: MRS
+#define EMC_MRS_0                       _MK_ADDR_CONST(0xcc)
+#define EMC_MRS_0_SECURE                        0x0
+#define EMC_MRS_0_WORD_COUNT                    0x1
+#define EMC_MRS_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define EMC_MRS_0_RESET_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_MRS_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define EMC_MRS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_MRS_0_READ_MASK                     _MK_MASK_CONST(0xc0303fff)
+#define EMC_MRS_0_WRITE_MASK                    _MK_MASK_CONST(0xc0303fff)
+// mode-register data to be written. 
+#define EMC_MRS_0_MRS_ADR_SHIFT                 _MK_SHIFT_CONST(0)
+#define EMC_MRS_0_MRS_ADR_FIELD                 (_MK_MASK_CONST(0x3fff) << EMC_MRS_0_MRS_ADR_SHIFT)
+#define EMC_MRS_0_MRS_ADR_RANGE                 13:0
+#define EMC_MRS_0_MRS_ADR_WOFFSET                       0x0
+#define EMC_MRS_0_MRS_ADR_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_MRS_0_MRS_ADR_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_MRS_0_MRS_ADR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_MRS_0_MRS_ADR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Set to 0x0 for MRS.
+#define EMC_MRS_0_MRS_BA_SHIFT                  _MK_SHIFT_CONST(20)
+#define EMC_MRS_0_MRS_BA_FIELD                  (_MK_MASK_CONST(0x3) << EMC_MRS_0_MRS_BA_SHIFT)
+#define EMC_MRS_0_MRS_BA_RANGE                  21:20
+#define EMC_MRS_0_MRS_BA_WOFFSET                        0x0
+#define EMC_MRS_0_MRS_BA_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_MRS_0_MRS_BA_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_MRS_0_MRS_BA_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_MRS_0_MRS_BA_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// active low chip-select, 0x0 applies command to both devices, 0x2 to for only dev0, 0x1 for only dev1.
+#define EMC_MRS_0_MRS_DEV_SELECTN_SHIFT                 _MK_SHIFT_CONST(30)
+#define EMC_MRS_0_MRS_DEV_SELECTN_FIELD                 (_MK_MASK_CONST(0x3) << EMC_MRS_0_MRS_DEV_SELECTN_SHIFT)
+#define EMC_MRS_0_MRS_DEV_SELECTN_RANGE                 31:30
+#define EMC_MRS_0_MRS_DEV_SELECTN_WOFFSET                       0x0
+#define EMC_MRS_0_MRS_DEV_SELECTN_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_MRS_0_MRS_DEV_SELECTN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_MRS_0_MRS_DEV_SELECTN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_MRS_0_MRS_DEV_SELECTN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EMC_EMRS_0  // Command trigger: EMRS
+#define EMC_EMRS_0                      _MK_ADDR_CONST(0xd0)
+#define EMC_EMRS_0_SECURE                       0x0
+#define EMC_EMRS_0_WORD_COUNT                   0x1
+#define EMC_EMRS_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define EMC_EMRS_0_RESET_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_EMRS_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define EMC_EMRS_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_EMRS_0_READ_MASK                    _MK_MASK_CONST(0xc0303fff)
+#define EMC_EMRS_0_WRITE_MASK                   _MK_MASK_CONST(0xc0303fff)
+// mode-register data to be written. 
+#define EMC_EMRS_0_EMRS_ADR_SHIFT                       _MK_SHIFT_CONST(0)
+#define EMC_EMRS_0_EMRS_ADR_FIELD                       (_MK_MASK_CONST(0x3fff) << EMC_EMRS_0_EMRS_ADR_SHIFT)
+#define EMC_EMRS_0_EMRS_ADR_RANGE                       13:0
+#define EMC_EMRS_0_EMRS_ADR_WOFFSET                     0x0
+#define EMC_EMRS_0_EMRS_ADR_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_EMRS_0_EMRS_ADR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_EMRS_0_EMRS_ADR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_EMRS_0_EMRS_ADR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Set to 0x1 for EMRS (and where applicable, 0x2 for EMRS2, and 0x3 for EMRS3).
+#define EMC_EMRS_0_EMRS_BA_SHIFT                        _MK_SHIFT_CONST(20)
+#define EMC_EMRS_0_EMRS_BA_FIELD                        (_MK_MASK_CONST(0x3) << EMC_EMRS_0_EMRS_BA_SHIFT)
+#define EMC_EMRS_0_EMRS_BA_RANGE                        21:20
+#define EMC_EMRS_0_EMRS_BA_WOFFSET                      0x0
+#define EMC_EMRS_0_EMRS_BA_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_EMRS_0_EMRS_BA_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define EMC_EMRS_0_EMRS_BA_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_EMRS_0_EMRS_BA_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// active low chip-select, 0x0 applies command to both devices, 0x2 to for only dev0, 0x1 for only dev1.
+#define EMC_EMRS_0_EMRS_DEV_SELECTN_SHIFT                       _MK_SHIFT_CONST(30)
+#define EMC_EMRS_0_EMRS_DEV_SELECTN_FIELD                       (_MK_MASK_CONST(0x3) << EMC_EMRS_0_EMRS_DEV_SELECTN_SHIFT)
+#define EMC_EMRS_0_EMRS_DEV_SELECTN_RANGE                       31:30
+#define EMC_EMRS_0_EMRS_DEV_SELECTN_WOFFSET                     0x0
+#define EMC_EMRS_0_EMRS_DEV_SELECTN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_EMRS_0_EMRS_DEV_SELECTN_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_EMRS_0_EMRS_DEV_SELECTN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_EMRS_0_EMRS_DEV_SELECTN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register EMC_REF_0  // Command trigger: Refresh
+#define EMC_REF_0                       _MK_ADDR_CONST(0xd4)
+#define EMC_REF_0_SECURE                        0x0
+#define EMC_REF_0_WORD_COUNT                    0x1
+#define EMC_REF_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define EMC_REF_0_RESET_MASK                    _MK_MASK_CONST(0xff01)
+#define EMC_REF_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define EMC_REF_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_REF_0_READ_MASK                     _MK_MASK_CONST(0xff01)
+#define EMC_REF_0_WRITE_MASK                    _MK_MASK_CONST(0xff01)
+// causes the hardware to perform a REFRESH to all DRAM banks.
+#define EMC_REF_0_REF_CMD_SHIFT                 _MK_SHIFT_CONST(0)
+#define EMC_REF_0_REF_CMD_FIELD                 (_MK_MASK_CONST(0x1) << EMC_REF_0_REF_CMD_SHIFT)
+#define EMC_REF_0_REF_CMD_RANGE                 0:0
+#define EMC_REF_0_REF_CMD_WOFFSET                       0x0
+#define EMC_REF_0_REF_CMD_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_REF_0_REF_CMD_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define EMC_REF_0_REF_CMD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_REF_0_REF_CMD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// perform (REF_NUM + 1) refresh cycles.
+#define EMC_REF_0_REF_NUM_SHIFT                 _MK_SHIFT_CONST(8)
+#define EMC_REF_0_REF_NUM_FIELD                 (_MK_MASK_CONST(0xff) << EMC_REF_0_REF_NUM_SHIFT)
+#define EMC_REF_0_REF_NUM_RANGE                 15:8
+#define EMC_REF_0_REF_NUM_WOFFSET                       0x0
+#define EMC_REF_0_REF_NUM_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_REF_0_REF_NUM_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define EMC_REF_0_REF_NUM_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_REF_0_REF_NUM_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EMC_PRE_0  // Command trigger: Precharge-All
+#define EMC_PRE_0                       _MK_ADDR_CONST(0xd8)
+#define EMC_PRE_0_SECURE                        0x0
+#define EMC_PRE_0_WORD_COUNT                    0x1
+#define EMC_PRE_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define EMC_PRE_0_RESET_MASK                    _MK_MASK_CONST(0x1)
+#define EMC_PRE_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define EMC_PRE_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_PRE_0_READ_MASK                     _MK_MASK_CONST(0xc0000001)
+#define EMC_PRE_0_WRITE_MASK                    _MK_MASK_CONST(0xc0000001)
+// causes the hardware to perform a PRECHARGE to all DRAM banks.
+#define EMC_PRE_0_PRE_CMD_SHIFT                 _MK_SHIFT_CONST(0)
+#define EMC_PRE_0_PRE_CMD_FIELD                 (_MK_MASK_CONST(0x1) << EMC_PRE_0_PRE_CMD_SHIFT)
+#define EMC_PRE_0_PRE_CMD_RANGE                 0:0
+#define EMC_PRE_0_PRE_CMD_WOFFSET                       0x0
+#define EMC_PRE_0_PRE_CMD_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_PRE_0_PRE_CMD_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define EMC_PRE_0_PRE_CMD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_PRE_0_PRE_CMD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// active low chip-select, 0x0 applies command to both devices, 0x2 to for only dev0, 0x1 for only dev1.
+#define EMC_PRE_0_PRE_DEV_SELECTN_SHIFT                 _MK_SHIFT_CONST(30)
+#define EMC_PRE_0_PRE_DEV_SELECTN_FIELD                 (_MK_MASK_CONST(0x3) << EMC_PRE_0_PRE_DEV_SELECTN_SHIFT)
+#define EMC_PRE_0_PRE_DEV_SELECTN_RANGE                 31:30
+#define EMC_PRE_0_PRE_DEV_SELECTN_WOFFSET                       0x0
+#define EMC_PRE_0_PRE_DEV_SELECTN_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_PRE_0_PRE_DEV_SELECTN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_PRE_0_PRE_DEV_SELECTN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_PRE_0_PRE_DEV_SELECTN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EMC_NOP_0  // Command trigger: NOP
+#define EMC_NOP_0                       _MK_ADDR_CONST(0xdc)
+#define EMC_NOP_0_SECURE                        0x0
+#define EMC_NOP_0_WORD_COUNT                    0x1
+#define EMC_NOP_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define EMC_NOP_0_RESET_MASK                    _MK_MASK_CONST(0x1)
+#define EMC_NOP_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define EMC_NOP_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_NOP_0_READ_MASK                     _MK_MASK_CONST(0x1)
+#define EMC_NOP_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
+// causes the hardware to perform a NOP to all DRAM banks.
+#define EMC_NOP_0_NOP_CMD_SHIFT                 _MK_SHIFT_CONST(0)
+#define EMC_NOP_0_NOP_CMD_FIELD                 (_MK_MASK_CONST(0x1) << EMC_NOP_0_NOP_CMD_SHIFT)
+#define EMC_NOP_0_NOP_CMD_RANGE                 0:0
+#define EMC_NOP_0_NOP_CMD_WOFFSET                       0x0
+#define EMC_NOP_0_NOP_CMD_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_NOP_0_NOP_CMD_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define EMC_NOP_0_NOP_CMD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_NOP_0_NOP_CMD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EMC_SELF_REF_0  // Command trigger: SELF REFRESH
+#define EMC_SELF_REF_0                  _MK_ADDR_CONST(0xe0)
+#define EMC_SELF_REF_0_SECURE                   0x0
+#define EMC_SELF_REF_0_WORD_COUNT                       0x1
+#define EMC_SELF_REF_0_RESET_VAL                        _MK_MASK_CONST(0xc0000000)
+#define EMC_SELF_REF_0_RESET_MASK                       _MK_MASK_CONST(0xc0000001)
+#define EMC_SELF_REF_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define EMC_SELF_REF_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_SELF_REF_0_READ_MASK                        _MK_MASK_CONST(0xc0000001)
+#define EMC_SELF_REF_0_WRITE_MASK                       _MK_MASK_CONST(0xc0000001)
+// causes the hardware to issue a SELF_REFRESH command. While CMD:ENABLED, the CKE pin is held deasserted. The CMD:ENABLED state will override the PIN:CKE setting.
+// The DRAM will ignore all accesses until CMD:DISABLED.
+#define EMC_SELF_REF_0_SELF_REF_CMD_SHIFT                       _MK_SHIFT_CONST(0)
+#define EMC_SELF_REF_0_SELF_REF_CMD_FIELD                       (_MK_MASK_CONST(0x1) << EMC_SELF_REF_0_SELF_REF_CMD_SHIFT)
+#define EMC_SELF_REF_0_SELF_REF_CMD_RANGE                       0:0
+#define EMC_SELF_REF_0_SELF_REF_CMD_WOFFSET                     0x0
+#define EMC_SELF_REF_0_SELF_REF_CMD_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_SELF_REF_0_SELF_REF_CMD_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define EMC_SELF_REF_0_SELF_REF_CMD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_SELF_REF_0_SELF_REF_CMD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EMC_SELF_REF_0_SELF_REF_CMD_INIT_ENUM                   DISABLED
+#define EMC_SELF_REF_0_SELF_REF_CMD_DISABLED                    _MK_ENUM_CONST(0)
+#define EMC_SELF_REF_0_SELF_REF_CMD_ENABLED                     _MK_ENUM_CONST(1)
+
+// active low chip-select, 0x0 applies command to both devices, 0x2 to for only dev0, 0x1 for only dev1, 0x3 for neither device.
+#define EMC_SELF_REF_0_SREF_DEV_SELECTN_SHIFT                   _MK_SHIFT_CONST(30)
+#define EMC_SELF_REF_0_SREF_DEV_SELECTN_FIELD                   (_MK_MASK_CONST(0x3) << EMC_SELF_REF_0_SREF_DEV_SELECTN_SHIFT)
+#define EMC_SELF_REF_0_SREF_DEV_SELECTN_RANGE                   31:30
+#define EMC_SELF_REF_0_SREF_DEV_SELECTN_WOFFSET                 0x0
+#define EMC_SELF_REF_0_SREF_DEV_SELECTN_DEFAULT                 _MK_MASK_CONST(0x3)
+#define EMC_SELF_REF_0_SREF_DEV_SELECTN_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define EMC_SELF_REF_0_SREF_DEV_SELECTN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_SELF_REF_0_SREF_DEV_SELECTN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register EMC_DPD_0  // Command trigger: Deep Power Down
+#define EMC_DPD_0                       _MK_ADDR_CONST(0xe4)
+#define EMC_DPD_0_SECURE                        0x0
+#define EMC_DPD_0_WORD_COUNT                    0x1
+#define EMC_DPD_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define EMC_DPD_0_RESET_MASK                    _MK_MASK_CONST(0x1)
+#define EMC_DPD_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define EMC_DPD_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_DPD_0_READ_MASK                     _MK_MASK_CONST(0xc0000001)
+#define EMC_DPD_0_WRITE_MASK                    _MK_MASK_CONST(0xc0000001)
+// causes the hardware to issue the deep power down command (Burst Terminate w/ cke low). While in DPD mode, the DRAM will not maintain data integrity.
+// While CMD:ENABLED, the CKE pin is held deasserted. The CMD:ENABLED state will override the PIN:CKE setting.
+// The DRAM will ignore all accesses until CMD:DISABLED.
+#define EMC_DPD_0_DPD_CMD_SHIFT                 _MK_SHIFT_CONST(0)
+#define EMC_DPD_0_DPD_CMD_FIELD                 (_MK_MASK_CONST(0x1) << EMC_DPD_0_DPD_CMD_SHIFT)
+#define EMC_DPD_0_DPD_CMD_RANGE                 0:0
+#define EMC_DPD_0_DPD_CMD_WOFFSET                       0x0
+#define EMC_DPD_0_DPD_CMD_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_DPD_0_DPD_CMD_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define EMC_DPD_0_DPD_CMD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_DPD_0_DPD_CMD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_DPD_0_DPD_CMD_INIT_ENUM                     DISABLED
+#define EMC_DPD_0_DPD_CMD_DISABLED                      _MK_ENUM_CONST(0)
+#define EMC_DPD_0_DPD_CMD_ENABLED                       _MK_ENUM_CONST(1)
+
+// active low chip-select, 0x0 applies command to both devices, 0x2 to for only dev0, 0x1 for only dev1.
+#define EMC_DPD_0_DPD_DEV_SELECTN_SHIFT                 _MK_SHIFT_CONST(30)
+#define EMC_DPD_0_DPD_DEV_SELECTN_FIELD                 (_MK_MASK_CONST(0x3) << EMC_DPD_0_DPD_DEV_SELECTN_SHIFT)
+#define EMC_DPD_0_DPD_DEV_SELECTN_RANGE                 31:30
+#define EMC_DPD_0_DPD_DEV_SELECTN_WOFFSET                       0x0
+#define EMC_DPD_0_DPD_DEV_SELECTN_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_DPD_0_DPD_DEV_SELECTN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_DPD_0_DPD_DEV_SELECTN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_DPD_0_DPD_DEV_SELECTN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EMC_MRW_0  // Command trigger: MRW
+#define EMC_MRW_0                       _MK_ADDR_CONST(0xe8)
+#define EMC_MRW_0_SECURE                        0x0
+#define EMC_MRW_0_WORD_COUNT                    0x1
+#define EMC_MRW_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define EMC_MRW_0_RESET_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_MRW_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define EMC_MRW_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_MRW_0_READ_MASK                     _MK_MASK_CONST(0x0)
+#define EMC_MRW_0_WRITE_MASK                    _MK_MASK_CONST(0xc0ff00ff)
+// data to be written
+#define EMC_MRW_0_MRW_OP_SHIFT                  _MK_SHIFT_CONST(0)
+#define EMC_MRW_0_MRW_OP_FIELD                  (_MK_MASK_CONST(0xff) << EMC_MRW_0_MRW_OP_SHIFT)
+#define EMC_MRW_0_MRW_OP_RANGE                  7:0
+#define EMC_MRW_0_MRW_OP_WOFFSET                        0x0
+#define EMC_MRW_0_MRW_OP_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_MRW_0_MRW_OP_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_MRW_0_MRW_OP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_MRW_0_MRW_OP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// register address
+#define EMC_MRW_0_MRW_MA_SHIFT                  _MK_SHIFT_CONST(16)
+#define EMC_MRW_0_MRW_MA_FIELD                  (_MK_MASK_CONST(0xff) << EMC_MRW_0_MRW_MA_SHIFT)
+#define EMC_MRW_0_MRW_MA_RANGE                  23:16
+#define EMC_MRW_0_MRW_MA_WOFFSET                        0x0
+#define EMC_MRW_0_MRW_MA_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_MRW_0_MRW_MA_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_MRW_0_MRW_MA_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_MRW_0_MRW_MA_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// active-low chip-select,  0x0 applies command to both devices, 0x2 to for only dev0, 0x1 for dev1.
+#define EMC_MRW_0_MRW_DEV_SELECTN_SHIFT                 _MK_SHIFT_CONST(30)
+#define EMC_MRW_0_MRW_DEV_SELECTN_FIELD                 (_MK_MASK_CONST(0x3) << EMC_MRW_0_MRW_DEV_SELECTN_SHIFT)
+#define EMC_MRW_0_MRW_DEV_SELECTN_RANGE                 31:30
+#define EMC_MRW_0_MRW_DEV_SELECTN_WOFFSET                       0x0
+#define EMC_MRW_0_MRW_DEV_SELECTN_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_MRW_0_MRW_DEV_SELECTN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_MRW_0_MRW_DEV_SELECTN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_MRW_0_MRW_DEV_SELECTN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EMC_MRR_0  // Command trigger: MRR
+#define EMC_MRR_0                       _MK_ADDR_CONST(0xec)
+#define EMC_MRR_0_SECURE                        0x0
+#define EMC_MRR_0_WORD_COUNT                    0x1
+#define EMC_MRR_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define EMC_MRR_0_RESET_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_MRR_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define EMC_MRR_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_MRR_0_READ_MASK                     _MK_MASK_CONST(0xffff)
+#define EMC_MRR_0_WRITE_MASK                    _MK_MASK_CONST(0xc0ff0000)
+// data returned
+#define EMC_MRR_0_MRR_DATA_SHIFT                        _MK_SHIFT_CONST(0)
+#define EMC_MRR_0_MRR_DATA_FIELD                        (_MK_MASK_CONST(0xffff) << EMC_MRR_0_MRR_DATA_SHIFT)
+#define EMC_MRR_0_MRR_DATA_RANGE                        15:0
+#define EMC_MRR_0_MRR_DATA_WOFFSET                      0x0
+#define EMC_MRR_0_MRR_DATA_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_MRR_0_MRR_DATA_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define EMC_MRR_0_MRR_DATA_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_MRR_0_MRR_DATA_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// register address
+#define EMC_MRR_0_MRR_MA_SHIFT                  _MK_SHIFT_CONST(16)
+#define EMC_MRR_0_MRR_MA_FIELD                  (_MK_MASK_CONST(0xff) << EMC_MRR_0_MRR_MA_SHIFT)
+#define EMC_MRR_0_MRR_MA_RANGE                  23:16
+#define EMC_MRR_0_MRR_MA_WOFFSET                        0x0
+#define EMC_MRR_0_MRR_MA_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_MRR_0_MRR_MA_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_MRR_0_MRR_MA_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_MRR_0_MRR_MA_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// active-low chip-select, choose which device to send the command to. (enum for safety).
+#define EMC_MRR_0_MRR_DEV_SELECTN_SHIFT                 _MK_SHIFT_CONST(30)
+#define EMC_MRR_0_MRR_DEV_SELECTN_FIELD                 (_MK_MASK_CONST(0x3) << EMC_MRR_0_MRR_DEV_SELECTN_SHIFT)
+#define EMC_MRR_0_MRR_DEV_SELECTN_RANGE                 31:30
+#define EMC_MRR_0_MRR_DEV_SELECTN_WOFFSET                       0x0
+#define EMC_MRR_0_MRR_DEV_SELECTN_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_MRR_0_MRR_DEV_SELECTN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_MRR_0_MRR_DEV_SELECTN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_MRR_0_MRR_DEV_SELECTN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_MRR_0_MRR_DEV_SELECTN_ILLEGAL                       _MK_ENUM_CONST(0)
+#define EMC_MRR_0_MRR_DEV_SELECTN_DEV1                  _MK_ENUM_CONST(1)
+#define EMC_MRR_0_MRR_DEV_SELECTN_DEV0                  _MK_ENUM_CONST(2)
+#define EMC_MRR_0_MRR_DEV_SELECTN_RESERVED                      _MK_ENUM_CONST(3)
+
+
+// Register EMC_CMDQ_0  // Command Queue Depth register
+#define EMC_CMDQ_0                      _MK_ADDR_CONST(0xf0)
+#define EMC_CMDQ_0_SECURE                       0x0
+#define EMC_CMDQ_0_WORD_COUNT                   0x1
+#define EMC_CMDQ_0_RESET_VAL                    _MK_MASK_CONST(0x10004408)
+#define EMC_CMDQ_0_RESET_MASK                   _MK_MASK_CONST(0x1f00771f)
+#define EMC_CMDQ_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define EMC_CMDQ_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_CMDQ_0_READ_MASK                    _MK_MASK_CONST(0x1f00771f)
+#define EMC_CMDQ_0_WRITE_MASK                   _MK_MASK_CONST(0x1f00771f)
+#define EMC_CMDQ_0_RW_DEPTH_SHIFT                       _MK_SHIFT_CONST(0)
+#define EMC_CMDQ_0_RW_DEPTH_FIELD                       (_MK_MASK_CONST(0x1f) << EMC_CMDQ_0_RW_DEPTH_SHIFT)
+#define EMC_CMDQ_0_RW_DEPTH_RANGE                       4:0
+#define EMC_CMDQ_0_RW_DEPTH_WOFFSET                     0x0
+#define EMC_CMDQ_0_RW_DEPTH_DEFAULT                     _MK_MASK_CONST(0x8)
+#define EMC_CMDQ_0_RW_DEPTH_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define EMC_CMDQ_0_RW_DEPTH_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_CMDQ_0_RW_DEPTH_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define EMC_CMDQ_0_ACT_DEPTH_SHIFT                      _MK_SHIFT_CONST(8)
+#define EMC_CMDQ_0_ACT_DEPTH_FIELD                      (_MK_MASK_CONST(0x7) << EMC_CMDQ_0_ACT_DEPTH_SHIFT)
+#define EMC_CMDQ_0_ACT_DEPTH_RANGE                      10:8
+#define EMC_CMDQ_0_ACT_DEPTH_WOFFSET                    0x0
+#define EMC_CMDQ_0_ACT_DEPTH_DEFAULT                    _MK_MASK_CONST(0x4)
+#define EMC_CMDQ_0_ACT_DEPTH_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define EMC_CMDQ_0_ACT_DEPTH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_CMDQ_0_ACT_DEPTH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define EMC_CMDQ_0_PRE_DEPTH_SHIFT                      _MK_SHIFT_CONST(12)
+#define EMC_CMDQ_0_PRE_DEPTH_FIELD                      (_MK_MASK_CONST(0x7) << EMC_CMDQ_0_PRE_DEPTH_SHIFT)
+#define EMC_CMDQ_0_PRE_DEPTH_RANGE                      14:12
+#define EMC_CMDQ_0_PRE_DEPTH_WOFFSET                    0x0
+#define EMC_CMDQ_0_PRE_DEPTH_DEFAULT                    _MK_MASK_CONST(0x4)
+#define EMC_CMDQ_0_PRE_DEPTH_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define EMC_CMDQ_0_PRE_DEPTH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_CMDQ_0_PRE_DEPTH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define EMC_CMDQ_0_RW_WD_DEPTH_SHIFT                    _MK_SHIFT_CONST(24)
+#define EMC_CMDQ_0_RW_WD_DEPTH_FIELD                    (_MK_MASK_CONST(0x1f) << EMC_CMDQ_0_RW_WD_DEPTH_SHIFT)
+#define EMC_CMDQ_0_RW_WD_DEPTH_RANGE                    28:24
+#define EMC_CMDQ_0_RW_WD_DEPTH_WOFFSET                  0x0
+#define EMC_CMDQ_0_RW_WD_DEPTH_DEFAULT                  _MK_MASK_CONST(0x10)
+#define EMC_CMDQ_0_RW_WD_DEPTH_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define EMC_CMDQ_0_RW_WD_DEPTH_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_CMDQ_0_RW_WD_DEPTH_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register EMC_FBIO_CFG1_0  // FBIO configuration register
+#define EMC_FBIO_CFG1_0                 _MK_ADDR_CONST(0xf4)
+#define EMC_FBIO_CFG1_0_SECURE                  0x0
+#define EMC_FBIO_CFG1_0_WORD_COUNT                      0x1
+#define EMC_FBIO_CFG1_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define EMC_FBIO_CFG1_0_RESET_MASK                      _MK_MASK_CONST(0x10000)
+#define EMC_FBIO_CFG1_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EMC_FBIO_CFG1_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_FBIO_CFG1_0_READ_MASK                       _MK_MASK_CONST(0x10000)
+#define EMC_FBIO_CFG1_0_WRITE_MASK                      _MK_MASK_CONST(0x10000)
+// determines whether the output enable is the same width as data (DEN_EARLY=0) or 1/2 bit time wider on either end (DEN_EARLY=1).
+#define EMC_FBIO_CFG1_0_CFG_DEN_EARLY_SHIFT                     _MK_SHIFT_CONST(16)
+#define EMC_FBIO_CFG1_0_CFG_DEN_EARLY_FIELD                     (_MK_MASK_CONST(0x1) << EMC_FBIO_CFG1_0_CFG_DEN_EARLY_SHIFT)
+#define EMC_FBIO_CFG1_0_CFG_DEN_EARLY_RANGE                     16:16
+#define EMC_FBIO_CFG1_0_CFG_DEN_EARLY_WOFFSET                   0x0
+#define EMC_FBIO_CFG1_0_CFG_DEN_EARLY_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_FBIO_CFG1_0_CFG_DEN_EARLY_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define EMC_FBIO_CFG1_0_CFG_DEN_EARLY_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_FBIO_CFG1_0_CFG_DEN_EARLY_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_FBIO_CFG1_0_CFG_DEN_EARLY_INIT_ENUM                 DISABLE
+#define EMC_FBIO_CFG1_0_CFG_DEN_EARLY_DISABLE                   _MK_ENUM_CONST(0)
+#define EMC_FBIO_CFG1_0_CFG_DEN_EARLY_ENABLE                    _MK_ENUM_CONST(1)
+
+
+// Register EMC_FBIO_DQSIB_DLY_0  // FBIO configuration register
+#define EMC_FBIO_DQSIB_DLY_0                    _MK_ADDR_CONST(0xf8)
+#define EMC_FBIO_DQSIB_DLY_0_SECURE                     0x0
+#define EMC_FBIO_DQSIB_DLY_0_WORD_COUNT                         0x1
+#define EMC_FBIO_DQSIB_DLY_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define EMC_FBIO_DQSIB_DLY_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_FBIO_DQSIB_DLY_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define EMC_FBIO_DQSIB_DLY_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_FBIO_DQSIB_DLY_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EMC_FBIO_DQSIB_DLY_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_0_SHIFT                 _MK_SHIFT_CONST(0)
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_0_FIELD                 (_MK_MASK_CONST(0xff) << EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_0_SHIFT)
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_0_RANGE                 7:0
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_0_WOFFSET                       0x0
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_0_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_0_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_1_SHIFT                 _MK_SHIFT_CONST(8)
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_1_FIELD                 (_MK_MASK_CONST(0xff) << EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_1_SHIFT)
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_1_RANGE                 15:8
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_1_WOFFSET                       0x0
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_1_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_1_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_2_SHIFT                 _MK_SHIFT_CONST(16)
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_2_FIELD                 (_MK_MASK_CONST(0xff) << EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_2_SHIFT)
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_2_RANGE                 23:16
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_2_WOFFSET                       0x0
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_2_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_2_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_3_SHIFT                 _MK_SHIFT_CONST(24)
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_3_FIELD                 (_MK_MASK_CONST(0xff) << EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_3_SHIFT)
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_3_RANGE                 31:24
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_3_WOFFSET                       0x0
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_3_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_3_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EMC_FBIO_DQSIB_DLY_MSB_0  // FBIO configuration register
+#define EMC_FBIO_DQSIB_DLY_MSB_0                        _MK_ADDR_CONST(0xfc)
+#define EMC_FBIO_DQSIB_DLY_MSB_0_SECURE                         0x0
+#define EMC_FBIO_DQSIB_DLY_MSB_0_WORD_COUNT                     0x1
+#define EMC_FBIO_DQSIB_DLY_MSB_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define EMC_FBIO_DQSIB_DLY_MSB_0_RESET_MASK                     _MK_MASK_CONST(0x3030303)
+#define EMC_FBIO_DQSIB_DLY_MSB_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define EMC_FBIO_DQSIB_DLY_MSB_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_FBIO_DQSIB_DLY_MSB_0_READ_MASK                      _MK_MASK_CONST(0x3030303)
+#define EMC_FBIO_DQSIB_DLY_MSB_0_WRITE_MASK                     _MK_MASK_CONST(0x3030303)
+#define EMC_FBIO_DQSIB_DLY_MSB_0_CFG_DQSIB_DLY_MSB_BYTE_0_SHIFT                 _MK_SHIFT_CONST(0)
+#define EMC_FBIO_DQSIB_DLY_MSB_0_CFG_DQSIB_DLY_MSB_BYTE_0_FIELD                 (_MK_MASK_CONST(0x3) << EMC_FBIO_DQSIB_DLY_MSB_0_CFG_DQSIB_DLY_MSB_BYTE_0_SHIFT)
+#define EMC_FBIO_DQSIB_DLY_MSB_0_CFG_DQSIB_DLY_MSB_BYTE_0_RANGE                 1:0
+#define EMC_FBIO_DQSIB_DLY_MSB_0_CFG_DQSIB_DLY_MSB_BYTE_0_WOFFSET                       0x0
+#define EMC_FBIO_DQSIB_DLY_MSB_0_CFG_DQSIB_DLY_MSB_BYTE_0_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_FBIO_DQSIB_DLY_MSB_0_CFG_DQSIB_DLY_MSB_BYTE_0_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define EMC_FBIO_DQSIB_DLY_MSB_0_CFG_DQSIB_DLY_MSB_BYTE_0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_FBIO_DQSIB_DLY_MSB_0_CFG_DQSIB_DLY_MSB_BYTE_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define EMC_FBIO_DQSIB_DLY_MSB_0_CFG_DQSIB_DLY_MSB_BYTE_1_SHIFT                 _MK_SHIFT_CONST(8)
+#define EMC_FBIO_DQSIB_DLY_MSB_0_CFG_DQSIB_DLY_MSB_BYTE_1_FIELD                 (_MK_MASK_CONST(0x3) << EMC_FBIO_DQSIB_DLY_MSB_0_CFG_DQSIB_DLY_MSB_BYTE_1_SHIFT)
+#define EMC_FBIO_DQSIB_DLY_MSB_0_CFG_DQSIB_DLY_MSB_BYTE_1_RANGE                 9:8
+#define EMC_FBIO_DQSIB_DLY_MSB_0_CFG_DQSIB_DLY_MSB_BYTE_1_WOFFSET                       0x0
+#define EMC_FBIO_DQSIB_DLY_MSB_0_CFG_DQSIB_DLY_MSB_BYTE_1_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_FBIO_DQSIB_DLY_MSB_0_CFG_DQSIB_DLY_MSB_BYTE_1_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define EMC_FBIO_DQSIB_DLY_MSB_0_CFG_DQSIB_DLY_MSB_BYTE_1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_FBIO_DQSIB_DLY_MSB_0_CFG_DQSIB_DLY_MSB_BYTE_1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define EMC_FBIO_DQSIB_DLY_MSB_0_CFG_DQSIB_DLY_MSB_BYTE_2_SHIFT                 _MK_SHIFT_CONST(16)
+#define EMC_FBIO_DQSIB_DLY_MSB_0_CFG_DQSIB_DLY_MSB_BYTE_2_FIELD                 (_MK_MASK_CONST(0x3) << EMC_FBIO_DQSIB_DLY_MSB_0_CFG_DQSIB_DLY_MSB_BYTE_2_SHIFT)
+#define EMC_FBIO_DQSIB_DLY_MSB_0_CFG_DQSIB_DLY_MSB_BYTE_2_RANGE                 17:16
+#define EMC_FBIO_DQSIB_DLY_MSB_0_CFG_DQSIB_DLY_MSB_BYTE_2_WOFFSET                       0x0
+#define EMC_FBIO_DQSIB_DLY_MSB_0_CFG_DQSIB_DLY_MSB_BYTE_2_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_FBIO_DQSIB_DLY_MSB_0_CFG_DQSIB_DLY_MSB_BYTE_2_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define EMC_FBIO_DQSIB_DLY_MSB_0_CFG_DQSIB_DLY_MSB_BYTE_2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_FBIO_DQSIB_DLY_MSB_0_CFG_DQSIB_DLY_MSB_BYTE_2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define EMC_FBIO_DQSIB_DLY_MSB_0_CFG_DQSIB_DLY_MSB_BYTE_3_SHIFT                 _MK_SHIFT_CONST(24)
+#define EMC_FBIO_DQSIB_DLY_MSB_0_CFG_DQSIB_DLY_MSB_BYTE_3_FIELD                 (_MK_MASK_CONST(0x3) << EMC_FBIO_DQSIB_DLY_MSB_0_CFG_DQSIB_DLY_MSB_BYTE_3_SHIFT)
+#define EMC_FBIO_DQSIB_DLY_MSB_0_CFG_DQSIB_DLY_MSB_BYTE_3_RANGE                 25:24
+#define EMC_FBIO_DQSIB_DLY_MSB_0_CFG_DQSIB_DLY_MSB_BYTE_3_WOFFSET                       0x0
+#define EMC_FBIO_DQSIB_DLY_MSB_0_CFG_DQSIB_DLY_MSB_BYTE_3_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_FBIO_DQSIB_DLY_MSB_0_CFG_DQSIB_DLY_MSB_BYTE_3_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define EMC_FBIO_DQSIB_DLY_MSB_0_CFG_DQSIB_DLY_MSB_BYTE_3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_FBIO_DQSIB_DLY_MSB_0_CFG_DQSIB_DLY_MSB_BYTE_3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EMC_FBIO_SPARE_0  // FBIO spare register
+#define EMC_FBIO_SPARE_0                        _MK_ADDR_CONST(0x100)
+#define EMC_FBIO_SPARE_0_SECURE                         0x0
+#define EMC_FBIO_SPARE_0_WORD_COUNT                     0x1
+#define EMC_FBIO_SPARE_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define EMC_FBIO_SPARE_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
+#define EMC_FBIO_SPARE_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define EMC_FBIO_SPARE_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_FBIO_SPARE_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EMC_FBIO_SPARE_0_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
+#define EMC_FBIO_SPARE_0_CFG_FBIO_SPARE_SHIFT                   _MK_SHIFT_CONST(0)
+#define EMC_FBIO_SPARE_0_CFG_FBIO_SPARE_FIELD                   (_MK_MASK_CONST(0xffffffff) << EMC_FBIO_SPARE_0_CFG_FBIO_SPARE_SHIFT)
+#define EMC_FBIO_SPARE_0_CFG_FBIO_SPARE_RANGE                   31:0
+#define EMC_FBIO_SPARE_0_CFG_FBIO_SPARE_WOFFSET                 0x0
+#define EMC_FBIO_SPARE_0_CFG_FBIO_SPARE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_FBIO_SPARE_0_CFG_FBIO_SPARE_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
+#define EMC_FBIO_SPARE_0_CFG_FBIO_SPARE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_FBIO_SPARE_0_CFG_FBIO_SPARE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register EMC_FBIO_CFG5_0  // FBIO configuration Register 
+#define EMC_FBIO_CFG5_0                 _MK_ADDR_CONST(0x104)
+#define EMC_FBIO_CFG5_0_SECURE                  0x0
+#define EMC_FBIO_CFG5_0_WORD_COUNT                      0x1
+#define EMC_FBIO_CFG5_0_RESET_VAL                       _MK_MASK_CONST(0x1)
+#define EMC_FBIO_CFG5_0_RESET_MASK                      _MK_MASK_CONST(0x793)
+#define EMC_FBIO_CFG5_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EMC_FBIO_CFG5_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_FBIO_CFG5_0_READ_MASK                       _MK_MASK_CONST(0x793)
+#define EMC_FBIO_CFG5_0_WRITE_MASK                      _MK_MASK_CONST(0x793)
+// specifies which DRAM protocol to use for the attached device(s).
+#define EMC_FBIO_CFG5_0_DRAM_TYPE_SHIFT                 _MK_SHIFT_CONST(0)
+#define EMC_FBIO_CFG5_0_DRAM_TYPE_FIELD                 (_MK_MASK_CONST(0x3) << EMC_FBIO_CFG5_0_DRAM_TYPE_SHIFT)
+#define EMC_FBIO_CFG5_0_DRAM_TYPE_RANGE                 1:0
+#define EMC_FBIO_CFG5_0_DRAM_TYPE_WOFFSET                       0x0
+#define EMC_FBIO_CFG5_0_DRAM_TYPE_DEFAULT                       _MK_MASK_CONST(0x1)
+#define EMC_FBIO_CFG5_0_DRAM_TYPE_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define EMC_FBIO_CFG5_0_DRAM_TYPE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_FBIO_CFG5_0_DRAM_TYPE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_FBIO_CFG5_0_DRAM_TYPE_INIT_ENUM                     DDR1
+#define EMC_FBIO_CFG5_0_DRAM_TYPE_RESERVED                      _MK_ENUM_CONST(0)
+#define EMC_FBIO_CFG5_0_DRAM_TYPE_DDR1                  _MK_ENUM_CONST(1)
+#define EMC_FBIO_CFG5_0_DRAM_TYPE_LPDDR2                        _MK_ENUM_CONST(2)
+#define EMC_FBIO_CFG5_0_DRAM_TYPE_DDR2                  _MK_ENUM_CONST(3)
+
+//  specifies whether the DRAM data-bus is 16-bits or 32-bits wide.
+#define EMC_FBIO_CFG5_0_DRAM_WIDTH_SHIFT                        _MK_SHIFT_CONST(4)
+#define EMC_FBIO_CFG5_0_DRAM_WIDTH_FIELD                        (_MK_MASK_CONST(0x1) << EMC_FBIO_CFG5_0_DRAM_WIDTH_SHIFT)
+#define EMC_FBIO_CFG5_0_DRAM_WIDTH_RANGE                        4:4
+#define EMC_FBIO_CFG5_0_DRAM_WIDTH_WOFFSET                      0x0
+#define EMC_FBIO_CFG5_0_DRAM_WIDTH_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_FBIO_CFG5_0_DRAM_WIDTH_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define EMC_FBIO_CFG5_0_DRAM_WIDTH_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_FBIO_CFG5_0_DRAM_WIDTH_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_FBIO_CFG5_0_DRAM_WIDTH_INIT_ENUM                    X32
+#define EMC_FBIO_CFG5_0_DRAM_WIDTH_X32                  _MK_ENUM_CONST(0)
+#define EMC_FBIO_CFG5_0_DRAM_WIDTH_X16                  _MK_ENUM_CONST(1)
+
+// enables differential signalling on dqs strobes (lpddr2/ddr2 options)
+#define EMC_FBIO_CFG5_0_DIFFERENTIAL_DQS_SHIFT                  _MK_SHIFT_CONST(7)
+#define EMC_FBIO_CFG5_0_DIFFERENTIAL_DQS_FIELD                  (_MK_MASK_CONST(0x1) << EMC_FBIO_CFG5_0_DIFFERENTIAL_DQS_SHIFT)
+#define EMC_FBIO_CFG5_0_DIFFERENTIAL_DQS_RANGE                  7:7
+#define EMC_FBIO_CFG5_0_DIFFERENTIAL_DQS_WOFFSET                        0x0
+#define EMC_FBIO_CFG5_0_DIFFERENTIAL_DQS_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_FBIO_CFG5_0_DIFFERENTIAL_DQS_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define EMC_FBIO_CFG5_0_DIFFERENTIAL_DQS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_FBIO_CFG5_0_DIFFERENTIAL_DQS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_FBIO_CFG5_0_DIFFERENTIAL_DQS_INIT_ENUM                      DISABLED
+#define EMC_FBIO_CFG5_0_DIFFERENTIAL_DQS_DISABLED                       _MK_ENUM_CONST(0)
+#define EMC_FBIO_CFG5_0_DIFFERENTIAL_DQS_ENABLED                        _MK_ENUM_CONST(1)
+
+// enables CTT_TERMINATION mode in pads (ddr2 support)
+#define EMC_FBIO_CFG5_0_CTT_TERMINATION_SHIFT                   _MK_SHIFT_CONST(8)
+#define EMC_FBIO_CFG5_0_CTT_TERMINATION_FIELD                   (_MK_MASK_CONST(0x1) << EMC_FBIO_CFG5_0_CTT_TERMINATION_SHIFT)
+#define EMC_FBIO_CFG5_0_CTT_TERMINATION_RANGE                   8:8
+#define EMC_FBIO_CFG5_0_CTT_TERMINATION_WOFFSET                 0x0
+#define EMC_FBIO_CFG5_0_CTT_TERMINATION_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_FBIO_CFG5_0_CTT_TERMINATION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define EMC_FBIO_CFG5_0_CTT_TERMINATION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_FBIO_CFG5_0_CTT_TERMINATION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define EMC_FBIO_CFG5_0_CTT_TERMINATION_INIT_ENUM                       DISABLED
+#define EMC_FBIO_CFG5_0_CTT_TERMINATION_DISABLED                        _MK_ENUM_CONST(0)
+#define EMC_FBIO_CFG5_0_CTT_TERMINATION_ENABLED                 _MK_ENUM_CONST(1)
+
+// enables pulldowns on dqs lines (and pullups on DQS_N if DIFFERENTIAL_DQS).
+#define EMC_FBIO_CFG5_0_DQS_PULLD_SHIFT                 _MK_SHIFT_CONST(9)
+#define EMC_FBIO_CFG5_0_DQS_PULLD_FIELD                 (_MK_MASK_CONST(0x1) << EMC_FBIO_CFG5_0_DQS_PULLD_SHIFT)
+#define EMC_FBIO_CFG5_0_DQS_PULLD_RANGE                 9:9
+#define EMC_FBIO_CFG5_0_DQS_PULLD_WOFFSET                       0x0
+#define EMC_FBIO_CFG5_0_DQS_PULLD_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_FBIO_CFG5_0_DQS_PULLD_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define EMC_FBIO_CFG5_0_DQS_PULLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_FBIO_CFG5_0_DQS_PULLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_FBIO_CFG5_0_DQS_PULLD_INIT_ENUM                     DISABLED
+#define EMC_FBIO_CFG5_0_DQS_PULLD_DISABLED                      _MK_ENUM_CONST(0)
+#define EMC_FBIO_CFG5_0_DQS_PULLD_ENABLED                       _MK_ENUM_CONST(1)
+
+// disables reads/writes to a device until the precharge command has been issued by the dram internally.
+#define EMC_FBIO_CFG5_0_DISABLE_CONCURRENT_AUTOPRE_SHIFT                        _MK_SHIFT_CONST(10)
+#define EMC_FBIO_CFG5_0_DISABLE_CONCURRENT_AUTOPRE_FIELD                        (_MK_MASK_CONST(0x1) << EMC_FBIO_CFG5_0_DISABLE_CONCURRENT_AUTOPRE_SHIFT)
+#define EMC_FBIO_CFG5_0_DISABLE_CONCURRENT_AUTOPRE_RANGE                        10:10
+#define EMC_FBIO_CFG5_0_DISABLE_CONCURRENT_AUTOPRE_WOFFSET                      0x0
+#define EMC_FBIO_CFG5_0_DISABLE_CONCURRENT_AUTOPRE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_FBIO_CFG5_0_DISABLE_CONCURRENT_AUTOPRE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define EMC_FBIO_CFG5_0_DISABLE_CONCURRENT_AUTOPRE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_FBIO_CFG5_0_DISABLE_CONCURRENT_AUTOPRE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_FBIO_CFG5_0_DISABLE_CONCURRENT_AUTOPRE_INIT_ENUM                    DISABLED
+#define EMC_FBIO_CFG5_0_DISABLE_CONCURRENT_AUTOPRE_DISABLED                     _MK_ENUM_CONST(0)
+#define EMC_FBIO_CFG5_0_DISABLE_CONCURRENT_AUTOPRE_ENABLED                      _MK_ENUM_CONST(1)
+
+
+// Register EMC_FBIO_WRPTR_EQ_2_0  // FBIO wrptr register
+#define EMC_FBIO_WRPTR_EQ_2_0                   _MK_ADDR_CONST(0x108)
+#define EMC_FBIO_WRPTR_EQ_2_0_SECURE                    0x0
+#define EMC_FBIO_WRPTR_EQ_2_0_WORD_COUNT                        0x1
+#define EMC_FBIO_WRPTR_EQ_2_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define EMC_FBIO_WRPTR_EQ_2_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_FBIO_WRPTR_EQ_2_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define EMC_FBIO_WRPTR_EQ_2_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_FBIO_WRPTR_EQ_2_0_READ_MASK                         _MK_MASK_CONST(0xf)
+#define EMC_FBIO_WRPTR_EQ_2_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_FBIO_WRPTR_EQ_2_0_FB_WRPTR_EQ_2_SHIFT                       _MK_SHIFT_CONST(0)
+#define EMC_FBIO_WRPTR_EQ_2_0_FB_WRPTR_EQ_2_FIELD                       (_MK_MASK_CONST(0xf) << EMC_FBIO_WRPTR_EQ_2_0_FB_WRPTR_EQ_2_SHIFT)
+#define EMC_FBIO_WRPTR_EQ_2_0_FB_WRPTR_EQ_2_RANGE                       3:0
+#define EMC_FBIO_WRPTR_EQ_2_0_FB_WRPTR_EQ_2_WOFFSET                     0x0
+#define EMC_FBIO_WRPTR_EQ_2_0_FB_WRPTR_EQ_2_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_FBIO_WRPTR_EQ_2_0_FB_WRPTR_EQ_2_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_FBIO_WRPTR_EQ_2_0_FB_WRPTR_EQ_2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_FBIO_WRPTR_EQ_2_0_FB_WRPTR_EQ_2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register EMC_FBIO_QUSE_DLY_0  // FBIO configuration register
+#define EMC_FBIO_QUSE_DLY_0                     _MK_ADDR_CONST(0x10c)
+#define EMC_FBIO_QUSE_DLY_0_SECURE                      0x0
+#define EMC_FBIO_QUSE_DLY_0_WORD_COUNT                  0x1
+#define EMC_FBIO_QUSE_DLY_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define EMC_FBIO_QUSE_DLY_0_RESET_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_FBIO_QUSE_DLY_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define EMC_FBIO_QUSE_DLY_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EMC_FBIO_QUSE_DLY_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define EMC_FBIO_QUSE_DLY_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_0_SHIFT                   _MK_SHIFT_CONST(0)
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_0_FIELD                   (_MK_MASK_CONST(0xff) << EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_0_SHIFT)
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_0_RANGE                   7:0
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_0_WOFFSET                 0x0
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_0_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_1_SHIFT                   _MK_SHIFT_CONST(8)
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_1_FIELD                   (_MK_MASK_CONST(0xff) << EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_1_SHIFT)
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_1_RANGE                   15:8
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_1_WOFFSET                 0x0
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_1_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_2_SHIFT                   _MK_SHIFT_CONST(16)
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_2_FIELD                   (_MK_MASK_CONST(0xff) << EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_2_SHIFT)
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_2_RANGE                   23:16
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_2_WOFFSET                 0x0
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_2_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_2_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_3_SHIFT                   _MK_SHIFT_CONST(24)
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_3_FIELD                   (_MK_MASK_CONST(0xff) << EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_3_SHIFT)
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_3_RANGE                   31:24
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_3_WOFFSET                 0x0
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_3_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_3_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_3_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_3_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register EMC_FBIO_QUSE_DLY_MSB_0  // FBIO configuration register
+#define EMC_FBIO_QUSE_DLY_MSB_0                 _MK_ADDR_CONST(0x110)
+#define EMC_FBIO_QUSE_DLY_MSB_0_SECURE                  0x0
+#define EMC_FBIO_QUSE_DLY_MSB_0_WORD_COUNT                      0x1
+#define EMC_FBIO_QUSE_DLY_MSB_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define EMC_FBIO_QUSE_DLY_MSB_0_RESET_MASK                      _MK_MASK_CONST(0x3030303)
+#define EMC_FBIO_QUSE_DLY_MSB_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EMC_FBIO_QUSE_DLY_MSB_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_FBIO_QUSE_DLY_MSB_0_READ_MASK                       _MK_MASK_CONST(0x3030303)
+#define EMC_FBIO_QUSE_DLY_MSB_0_WRITE_MASK                      _MK_MASK_CONST(0x3030303)
+#define EMC_FBIO_QUSE_DLY_MSB_0_CFG_QUSE_DLY_MSB_BYTE_0_SHIFT                   _MK_SHIFT_CONST(0)
+#define EMC_FBIO_QUSE_DLY_MSB_0_CFG_QUSE_DLY_MSB_BYTE_0_FIELD                   (_MK_MASK_CONST(0x3) << EMC_FBIO_QUSE_DLY_MSB_0_CFG_QUSE_DLY_MSB_BYTE_0_SHIFT)
+#define EMC_FBIO_QUSE_DLY_MSB_0_CFG_QUSE_DLY_MSB_BYTE_0_RANGE                   1:0
+#define EMC_FBIO_QUSE_DLY_MSB_0_CFG_QUSE_DLY_MSB_BYTE_0_WOFFSET                 0x0
+#define EMC_FBIO_QUSE_DLY_MSB_0_CFG_QUSE_DLY_MSB_BYTE_0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_FBIO_QUSE_DLY_MSB_0_CFG_QUSE_DLY_MSB_BYTE_0_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define EMC_FBIO_QUSE_DLY_MSB_0_CFG_QUSE_DLY_MSB_BYTE_0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_FBIO_QUSE_DLY_MSB_0_CFG_QUSE_DLY_MSB_BYTE_0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define EMC_FBIO_QUSE_DLY_MSB_0_CFG_QUSE_DLY_MSB_BYTE_1_SHIFT                   _MK_SHIFT_CONST(8)
+#define EMC_FBIO_QUSE_DLY_MSB_0_CFG_QUSE_DLY_MSB_BYTE_1_FIELD                   (_MK_MASK_CONST(0x3) << EMC_FBIO_QUSE_DLY_MSB_0_CFG_QUSE_DLY_MSB_BYTE_1_SHIFT)
+#define EMC_FBIO_QUSE_DLY_MSB_0_CFG_QUSE_DLY_MSB_BYTE_1_RANGE                   9:8
+#define EMC_FBIO_QUSE_DLY_MSB_0_CFG_QUSE_DLY_MSB_BYTE_1_WOFFSET                 0x0
+#define EMC_FBIO_QUSE_DLY_MSB_0_CFG_QUSE_DLY_MSB_BYTE_1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_FBIO_QUSE_DLY_MSB_0_CFG_QUSE_DLY_MSB_BYTE_1_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define EMC_FBIO_QUSE_DLY_MSB_0_CFG_QUSE_DLY_MSB_BYTE_1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_FBIO_QUSE_DLY_MSB_0_CFG_QUSE_DLY_MSB_BYTE_1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define EMC_FBIO_QUSE_DLY_MSB_0_CFG_QUSE_DLY_MSB_BYTE_2_SHIFT                   _MK_SHIFT_CONST(16)
+#define EMC_FBIO_QUSE_DLY_MSB_0_CFG_QUSE_DLY_MSB_BYTE_2_FIELD                   (_MK_MASK_CONST(0x3) << EMC_FBIO_QUSE_DLY_MSB_0_CFG_QUSE_DLY_MSB_BYTE_2_SHIFT)
+#define EMC_FBIO_QUSE_DLY_MSB_0_CFG_QUSE_DLY_MSB_BYTE_2_RANGE                   17:16
+#define EMC_FBIO_QUSE_DLY_MSB_0_CFG_QUSE_DLY_MSB_BYTE_2_WOFFSET                 0x0
+#define EMC_FBIO_QUSE_DLY_MSB_0_CFG_QUSE_DLY_MSB_BYTE_2_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_FBIO_QUSE_DLY_MSB_0_CFG_QUSE_DLY_MSB_BYTE_2_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define EMC_FBIO_QUSE_DLY_MSB_0_CFG_QUSE_DLY_MSB_BYTE_2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_FBIO_QUSE_DLY_MSB_0_CFG_QUSE_DLY_MSB_BYTE_2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define EMC_FBIO_QUSE_DLY_MSB_0_CFG_QUSE_DLY_MSB_BYTE_3_SHIFT                   _MK_SHIFT_CONST(24)
+#define EMC_FBIO_QUSE_DLY_MSB_0_CFG_QUSE_DLY_MSB_BYTE_3_FIELD                   (_MK_MASK_CONST(0x3) << EMC_FBIO_QUSE_DLY_MSB_0_CFG_QUSE_DLY_MSB_BYTE_3_SHIFT)
+#define EMC_FBIO_QUSE_DLY_MSB_0_CFG_QUSE_DLY_MSB_BYTE_3_RANGE                   25:24
+#define EMC_FBIO_QUSE_DLY_MSB_0_CFG_QUSE_DLY_MSB_BYTE_3_WOFFSET                 0x0
+#define EMC_FBIO_QUSE_DLY_MSB_0_CFG_QUSE_DLY_MSB_BYTE_3_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_FBIO_QUSE_DLY_MSB_0_CFG_QUSE_DLY_MSB_BYTE_3_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define EMC_FBIO_QUSE_DLY_MSB_0_CFG_QUSE_DLY_MSB_BYTE_3_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_FBIO_QUSE_DLY_MSB_0_CFG_QUSE_DLY_MSB_BYTE_3_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register EMC_FBIO_CFG6_0  // FBIO configuration register   
+#define EMC_FBIO_CFG6_0                 _MK_ADDR_CONST(0x114)
+#define EMC_FBIO_CFG6_0_SECURE                  0x0
+#define EMC_FBIO_CFG6_0_WORD_COUNT                      0x1
+#define EMC_FBIO_CFG6_0_RESET_VAL                       _MK_MASK_CONST(0x2)
+#define EMC_FBIO_CFG6_0_RESET_MASK                      _MK_MASK_CONST(0x7)
+#define EMC_FBIO_CFG6_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EMC_FBIO_CFG6_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_FBIO_CFG6_0_READ_MASK                       _MK_MASK_CONST(0x7)
+#define EMC_FBIO_CFG6_0_WRITE_MASK                      _MK_MASK_CONST(0x7)
+#define EMC_FBIO_CFG6_0_CFG_QUSE_LATE_SHIFT                     _MK_SHIFT_CONST(0)
+#define EMC_FBIO_CFG6_0_CFG_QUSE_LATE_FIELD                     (_MK_MASK_CONST(0x7) << EMC_FBIO_CFG6_0_CFG_QUSE_LATE_SHIFT)
+#define EMC_FBIO_CFG6_0_CFG_QUSE_LATE_RANGE                     2:0
+#define EMC_FBIO_CFG6_0_CFG_QUSE_LATE_WOFFSET                   0x0
+#define EMC_FBIO_CFG6_0_CFG_QUSE_LATE_DEFAULT                   _MK_MASK_CONST(0x2)
+#define EMC_FBIO_CFG6_0_CFG_QUSE_LATE_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define EMC_FBIO_CFG6_0_CFG_QUSE_LATE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_FBIO_CFG6_0_CFG_QUSE_LATE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Reserved address 280 [0x118] 
+
+// Reserved address 284 [0x11c] 
+
+// Register EMC_DQS_TRIMMER_RD0_0  
+#define EMC_DQS_TRIMMER_RD0_0                   _MK_ADDR_CONST(0x120)
+#define EMC_DQS_TRIMMER_RD0_0_SECURE                    0x0
+#define EMC_DQS_TRIMMER_RD0_0_WORD_COUNT                        0x1
+#define EMC_DQS_TRIMMER_RD0_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD0_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD0_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD0_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD0_0_READ_MASK                         _MK_MASK_CONST(0x3ff03ff)
+#define EMC_DQS_TRIMMER_RD0_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD0_0_QUSE_CURRENT_TRIM_VAL_BYTE_0_SHIFT                        _MK_SHIFT_CONST(0)
+#define EMC_DQS_TRIMMER_RD0_0_QUSE_CURRENT_TRIM_VAL_BYTE_0_FIELD                        (_MK_MASK_CONST(0x3ff) << EMC_DQS_TRIMMER_RD0_0_QUSE_CURRENT_TRIM_VAL_BYTE_0_SHIFT)
+#define EMC_DQS_TRIMMER_RD0_0_QUSE_CURRENT_TRIM_VAL_BYTE_0_RANGE                        9:0
+#define EMC_DQS_TRIMMER_RD0_0_QUSE_CURRENT_TRIM_VAL_BYTE_0_WOFFSET                      0x0
+#define EMC_DQS_TRIMMER_RD0_0_QUSE_CURRENT_TRIM_VAL_BYTE_0_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD0_0_QUSE_CURRENT_TRIM_VAL_BYTE_0_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD0_0_QUSE_CURRENT_TRIM_VAL_BYTE_0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD0_0_QUSE_CURRENT_TRIM_VAL_BYTE_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define EMC_DQS_TRIMMER_RD0_0_DQS_CURRENT_TRIM_VAL_BYTE_0_SHIFT                 _MK_SHIFT_CONST(16)
+#define EMC_DQS_TRIMMER_RD0_0_DQS_CURRENT_TRIM_VAL_BYTE_0_FIELD                 (_MK_MASK_CONST(0x3ff) << EMC_DQS_TRIMMER_RD0_0_DQS_CURRENT_TRIM_VAL_BYTE_0_SHIFT)
+#define EMC_DQS_TRIMMER_RD0_0_DQS_CURRENT_TRIM_VAL_BYTE_0_RANGE                 25:16
+#define EMC_DQS_TRIMMER_RD0_0_DQS_CURRENT_TRIM_VAL_BYTE_0_WOFFSET                       0x0
+#define EMC_DQS_TRIMMER_RD0_0_DQS_CURRENT_TRIM_VAL_BYTE_0_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD0_0_DQS_CURRENT_TRIM_VAL_BYTE_0_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD0_0_DQS_CURRENT_TRIM_VAL_BYTE_0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD0_0_DQS_CURRENT_TRIM_VAL_BYTE_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EMC_DQS_TRIMMER_RD1_0  
+#define EMC_DQS_TRIMMER_RD1_0                   _MK_ADDR_CONST(0x124)
+#define EMC_DQS_TRIMMER_RD1_0_SECURE                    0x0
+#define EMC_DQS_TRIMMER_RD1_0_WORD_COUNT                        0x1
+#define EMC_DQS_TRIMMER_RD1_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD1_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD1_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD1_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD1_0_READ_MASK                         _MK_MASK_CONST(0x3ff03ff)
+#define EMC_DQS_TRIMMER_RD1_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD1_0_QUSE_CURRENT_TRIM_VAL_BYTE_1_SHIFT                        _MK_SHIFT_CONST(0)
+#define EMC_DQS_TRIMMER_RD1_0_QUSE_CURRENT_TRIM_VAL_BYTE_1_FIELD                        (_MK_MASK_CONST(0x3ff) << EMC_DQS_TRIMMER_RD1_0_QUSE_CURRENT_TRIM_VAL_BYTE_1_SHIFT)
+#define EMC_DQS_TRIMMER_RD1_0_QUSE_CURRENT_TRIM_VAL_BYTE_1_RANGE                        9:0
+#define EMC_DQS_TRIMMER_RD1_0_QUSE_CURRENT_TRIM_VAL_BYTE_1_WOFFSET                      0x0
+#define EMC_DQS_TRIMMER_RD1_0_QUSE_CURRENT_TRIM_VAL_BYTE_1_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD1_0_QUSE_CURRENT_TRIM_VAL_BYTE_1_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD1_0_QUSE_CURRENT_TRIM_VAL_BYTE_1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD1_0_QUSE_CURRENT_TRIM_VAL_BYTE_1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define EMC_DQS_TRIMMER_RD1_0_DQS_CURRENT_TRIM_VAL_BYTE_1_SHIFT                 _MK_SHIFT_CONST(16)
+#define EMC_DQS_TRIMMER_RD1_0_DQS_CURRENT_TRIM_VAL_BYTE_1_FIELD                 (_MK_MASK_CONST(0x3ff) << EMC_DQS_TRIMMER_RD1_0_DQS_CURRENT_TRIM_VAL_BYTE_1_SHIFT)
+#define EMC_DQS_TRIMMER_RD1_0_DQS_CURRENT_TRIM_VAL_BYTE_1_RANGE                 25:16
+#define EMC_DQS_TRIMMER_RD1_0_DQS_CURRENT_TRIM_VAL_BYTE_1_WOFFSET                       0x0
+#define EMC_DQS_TRIMMER_RD1_0_DQS_CURRENT_TRIM_VAL_BYTE_1_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD1_0_DQS_CURRENT_TRIM_VAL_BYTE_1_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD1_0_DQS_CURRENT_TRIM_VAL_BYTE_1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD1_0_DQS_CURRENT_TRIM_VAL_BYTE_1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EMC_DQS_TRIMMER_RD2_0  
+#define EMC_DQS_TRIMMER_RD2_0                   _MK_ADDR_CONST(0x128)
+#define EMC_DQS_TRIMMER_RD2_0_SECURE                    0x0
+#define EMC_DQS_TRIMMER_RD2_0_WORD_COUNT                        0x1
+#define EMC_DQS_TRIMMER_RD2_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD2_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD2_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD2_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD2_0_READ_MASK                         _MK_MASK_CONST(0x3ff03ff)
+#define EMC_DQS_TRIMMER_RD2_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD2_0_QUSE_CURRENT_TRIM_VAL_BYTE_2_SHIFT                        _MK_SHIFT_CONST(0)
+#define EMC_DQS_TRIMMER_RD2_0_QUSE_CURRENT_TRIM_VAL_BYTE_2_FIELD                        (_MK_MASK_CONST(0x3ff) << EMC_DQS_TRIMMER_RD2_0_QUSE_CURRENT_TRIM_VAL_BYTE_2_SHIFT)
+#define EMC_DQS_TRIMMER_RD2_0_QUSE_CURRENT_TRIM_VAL_BYTE_2_RANGE                        9:0
+#define EMC_DQS_TRIMMER_RD2_0_QUSE_CURRENT_TRIM_VAL_BYTE_2_WOFFSET                      0x0
+#define EMC_DQS_TRIMMER_RD2_0_QUSE_CURRENT_TRIM_VAL_BYTE_2_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD2_0_QUSE_CURRENT_TRIM_VAL_BYTE_2_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD2_0_QUSE_CURRENT_TRIM_VAL_BYTE_2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD2_0_QUSE_CURRENT_TRIM_VAL_BYTE_2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define EMC_DQS_TRIMMER_RD2_0_DQS_CURRENT_TRIM_VAL_BYTE_2_SHIFT                 _MK_SHIFT_CONST(16)
+#define EMC_DQS_TRIMMER_RD2_0_DQS_CURRENT_TRIM_VAL_BYTE_2_FIELD                 (_MK_MASK_CONST(0x3ff) << EMC_DQS_TRIMMER_RD2_0_DQS_CURRENT_TRIM_VAL_BYTE_2_SHIFT)
+#define EMC_DQS_TRIMMER_RD2_0_DQS_CURRENT_TRIM_VAL_BYTE_2_RANGE                 25:16
+#define EMC_DQS_TRIMMER_RD2_0_DQS_CURRENT_TRIM_VAL_BYTE_2_WOFFSET                       0x0
+#define EMC_DQS_TRIMMER_RD2_0_DQS_CURRENT_TRIM_VAL_BYTE_2_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD2_0_DQS_CURRENT_TRIM_VAL_BYTE_2_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD2_0_DQS_CURRENT_TRIM_VAL_BYTE_2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD2_0_DQS_CURRENT_TRIM_VAL_BYTE_2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EMC_DQS_TRIMMER_RD3_0  
+#define EMC_DQS_TRIMMER_RD3_0                   _MK_ADDR_CONST(0x12c)
+#define EMC_DQS_TRIMMER_RD3_0_SECURE                    0x0
+#define EMC_DQS_TRIMMER_RD3_0_WORD_COUNT                        0x1
+#define EMC_DQS_TRIMMER_RD3_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD3_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD3_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD3_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD3_0_READ_MASK                         _MK_MASK_CONST(0x3ff03ff)
+#define EMC_DQS_TRIMMER_RD3_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD3_0_QUSE_CURRENT_TRIM_VAL_BYTE_3_SHIFT                        _MK_SHIFT_CONST(0)
+#define EMC_DQS_TRIMMER_RD3_0_QUSE_CURRENT_TRIM_VAL_BYTE_3_FIELD                        (_MK_MASK_CONST(0x3ff) << EMC_DQS_TRIMMER_RD3_0_QUSE_CURRENT_TRIM_VAL_BYTE_3_SHIFT)
+#define EMC_DQS_TRIMMER_RD3_0_QUSE_CURRENT_TRIM_VAL_BYTE_3_RANGE                        9:0
+#define EMC_DQS_TRIMMER_RD3_0_QUSE_CURRENT_TRIM_VAL_BYTE_3_WOFFSET                      0x0
+#define EMC_DQS_TRIMMER_RD3_0_QUSE_CURRENT_TRIM_VAL_BYTE_3_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD3_0_QUSE_CURRENT_TRIM_VAL_BYTE_3_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD3_0_QUSE_CURRENT_TRIM_VAL_BYTE_3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD3_0_QUSE_CURRENT_TRIM_VAL_BYTE_3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define EMC_DQS_TRIMMER_RD3_0_DQS_CURRENT_TRIM_VAL_BYTE_3_SHIFT                 _MK_SHIFT_CONST(16)
+#define EMC_DQS_TRIMMER_RD3_0_DQS_CURRENT_TRIM_VAL_BYTE_3_FIELD                 (_MK_MASK_CONST(0x3ff) << EMC_DQS_TRIMMER_RD3_0_DQS_CURRENT_TRIM_VAL_BYTE_3_SHIFT)
+#define EMC_DQS_TRIMMER_RD3_0_DQS_CURRENT_TRIM_VAL_BYTE_3_RANGE                 25:16
+#define EMC_DQS_TRIMMER_RD3_0_DQS_CURRENT_TRIM_VAL_BYTE_3_WOFFSET                       0x0
+#define EMC_DQS_TRIMMER_RD3_0_DQS_CURRENT_TRIM_VAL_BYTE_3_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD3_0_DQS_CURRENT_TRIM_VAL_BYTE_3_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD3_0_DQS_CURRENT_TRIM_VAL_BYTE_3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD3_0_DQS_CURRENT_TRIM_VAL_BYTE_3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Reserved address 304 [0x130] 
+
+// Reserved address 308 [0x134] 
+
+// Reserved address 312 [0x138] 
+
+// Reserved address 316 [0x13c] 
+
+// Register EMC_CLKEN_OVERRIDE_0  
+#define EMC_CLKEN_OVERRIDE_0                    _MK_ADDR_CONST(0x140)
+#define EMC_CLKEN_OVERRIDE_0_SECURE                     0x0
+#define EMC_CLKEN_OVERRIDE_0_WORD_COUNT                         0x1
+#define EMC_CLKEN_OVERRIDE_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define EMC_CLKEN_OVERRIDE_0_RESET_MASK                         _MK_MASK_CONST(0x7f)
+#define EMC_CLKEN_OVERRIDE_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define EMC_CLKEN_OVERRIDE_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_CLKEN_OVERRIDE_0_READ_MASK                  _MK_MASK_CONST(0x7f)
+#define EMC_CLKEN_OVERRIDE_0_WRITE_MASK                         _MK_MASK_CONST(0x7f)
+#define EMC_CLKEN_OVERRIDE_0_ARB_CLKEN_OVR_SHIFT                        _MK_SHIFT_CONST(0)
+#define EMC_CLKEN_OVERRIDE_0_ARB_CLKEN_OVR_FIELD                        (_MK_MASK_CONST(0x1) << EMC_CLKEN_OVERRIDE_0_ARB_CLKEN_OVR_SHIFT)
+#define EMC_CLKEN_OVERRIDE_0_ARB_CLKEN_OVR_RANGE                        0:0
+#define EMC_CLKEN_OVERRIDE_0_ARB_CLKEN_OVR_WOFFSET                      0x0
+#define EMC_CLKEN_OVERRIDE_0_ARB_CLKEN_OVR_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_CLKEN_OVERRIDE_0_ARB_CLKEN_OVR_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define EMC_CLKEN_OVERRIDE_0_ARB_CLKEN_OVR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_CLKEN_OVERRIDE_0_ARB_CLKEN_OVR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_CLKEN_OVERRIDE_0_ARB_CLKEN_OVR_INIT_ENUM                    CLK_GATED
+#define EMC_CLKEN_OVERRIDE_0_ARB_CLKEN_OVR_CLK_GATED                    _MK_ENUM_CONST(0)
+#define EMC_CLKEN_OVERRIDE_0_ARB_CLKEN_OVR_CLK_ALWAYS_ON                        _MK_ENUM_CONST(1)
+#define EMC_CLKEN_OVERRIDE_0_ARB_CLKEN_OVR_DISABLE                      _MK_ENUM_CONST(0)
+#define EMC_CLKEN_OVERRIDE_0_ARB_CLKEN_OVR_ENABLE                       _MK_ENUM_CONST(1)
+#define EMC_CLKEN_OVERRIDE_0_ARB_CLKEN_OVR_DISABLED                     _MK_ENUM_CONST(0)
+#define EMC_CLKEN_OVERRIDE_0_ARB_CLKEN_OVR_ENABLED                      _MK_ENUM_CONST(1)
+
+#define EMC_CLKEN_OVERRIDE_0_CMDQ_CLKEN_OVR_SHIFT                       _MK_SHIFT_CONST(1)
+#define EMC_CLKEN_OVERRIDE_0_CMDQ_CLKEN_OVR_FIELD                       (_MK_MASK_CONST(0x1) << EMC_CLKEN_OVERRIDE_0_CMDQ_CLKEN_OVR_SHIFT)
+#define EMC_CLKEN_OVERRIDE_0_CMDQ_CLKEN_OVR_RANGE                       1:1
+#define EMC_CLKEN_OVERRIDE_0_CMDQ_CLKEN_OVR_WOFFSET                     0x0
+#define EMC_CLKEN_OVERRIDE_0_CMDQ_CLKEN_OVR_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_CLKEN_OVERRIDE_0_CMDQ_CLKEN_OVR_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define EMC_CLKEN_OVERRIDE_0_CMDQ_CLKEN_OVR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_CLKEN_OVERRIDE_0_CMDQ_CLKEN_OVR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EMC_CLKEN_OVERRIDE_0_CMDQ_CLKEN_OVR_INIT_ENUM                   CLK_GATED
+#define EMC_CLKEN_OVERRIDE_0_CMDQ_CLKEN_OVR_CLK_GATED                   _MK_ENUM_CONST(0)
+#define EMC_CLKEN_OVERRIDE_0_CMDQ_CLKEN_OVR_CLK_ALWAYS_ON                       _MK_ENUM_CONST(1)
+#define EMC_CLKEN_OVERRIDE_0_CMDQ_CLKEN_OVR_DISABLE                     _MK_ENUM_CONST(0)
+#define EMC_CLKEN_OVERRIDE_0_CMDQ_CLKEN_OVR_ENABLE                      _MK_ENUM_CONST(1)
+#define EMC_CLKEN_OVERRIDE_0_CMDQ_CLKEN_OVR_DISABLED                    _MK_ENUM_CONST(0)
+#define EMC_CLKEN_OVERRIDE_0_CMDQ_CLKEN_OVR_ENABLED                     _MK_ENUM_CONST(1)
+
+#define EMC_CLKEN_OVERRIDE_0_DRAMC_CLKEN_OVR_SHIFT                      _MK_SHIFT_CONST(2)
+#define EMC_CLKEN_OVERRIDE_0_DRAMC_CLKEN_OVR_FIELD                      (_MK_MASK_CONST(0x1) << EMC_CLKEN_OVERRIDE_0_DRAMC_CLKEN_OVR_SHIFT)
+#define EMC_CLKEN_OVERRIDE_0_DRAMC_CLKEN_OVR_RANGE                      2:2
+#define EMC_CLKEN_OVERRIDE_0_DRAMC_CLKEN_OVR_WOFFSET                    0x0
+#define EMC_CLKEN_OVERRIDE_0_DRAMC_CLKEN_OVR_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_CLKEN_OVERRIDE_0_DRAMC_CLKEN_OVR_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define EMC_CLKEN_OVERRIDE_0_DRAMC_CLKEN_OVR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_CLKEN_OVERRIDE_0_DRAMC_CLKEN_OVR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_CLKEN_OVERRIDE_0_DRAMC_CLKEN_OVR_INIT_ENUM                  CLK_GATED
+#define EMC_CLKEN_OVERRIDE_0_DRAMC_CLKEN_OVR_CLK_GATED                  _MK_ENUM_CONST(0)
+#define EMC_CLKEN_OVERRIDE_0_DRAMC_CLKEN_OVR_CLK_ALWAYS_ON                      _MK_ENUM_CONST(1)
+#define EMC_CLKEN_OVERRIDE_0_DRAMC_CLKEN_OVR_DISABLE                    _MK_ENUM_CONST(0)
+#define EMC_CLKEN_OVERRIDE_0_DRAMC_CLKEN_OVR_ENABLE                     _MK_ENUM_CONST(1)
+#define EMC_CLKEN_OVERRIDE_0_DRAMC_CLKEN_OVR_DISABLED                   _MK_ENUM_CONST(0)
+#define EMC_CLKEN_OVERRIDE_0_DRAMC_CLKEN_OVR_ENABLED                    _MK_ENUM_CONST(1)
+
+#define EMC_CLKEN_OVERRIDE_0_RR_CLKEN_OVR_SHIFT                 _MK_SHIFT_CONST(3)
+#define EMC_CLKEN_OVERRIDE_0_RR_CLKEN_OVR_FIELD                 (_MK_MASK_CONST(0x1) << EMC_CLKEN_OVERRIDE_0_RR_CLKEN_OVR_SHIFT)
+#define EMC_CLKEN_OVERRIDE_0_RR_CLKEN_OVR_RANGE                 3:3
+#define EMC_CLKEN_OVERRIDE_0_RR_CLKEN_OVR_WOFFSET                       0x0
+#define EMC_CLKEN_OVERRIDE_0_RR_CLKEN_OVR_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_CLKEN_OVERRIDE_0_RR_CLKEN_OVR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define EMC_CLKEN_OVERRIDE_0_RR_CLKEN_OVR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_CLKEN_OVERRIDE_0_RR_CLKEN_OVR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_CLKEN_OVERRIDE_0_RR_CLKEN_OVR_INIT_ENUM                     CLK_GATED
+#define EMC_CLKEN_OVERRIDE_0_RR_CLKEN_OVR_CLK_GATED                     _MK_ENUM_CONST(0)
+#define EMC_CLKEN_OVERRIDE_0_RR_CLKEN_OVR_CLK_ALWAYS_ON                 _MK_ENUM_CONST(1)
+#define EMC_CLKEN_OVERRIDE_0_RR_CLKEN_OVR_DISABLE                       _MK_ENUM_CONST(0)
+#define EMC_CLKEN_OVERRIDE_0_RR_CLKEN_OVR_ENABLE                        _MK_ENUM_CONST(1)
+#define EMC_CLKEN_OVERRIDE_0_RR_CLKEN_OVR_DISABLED                      _MK_ENUM_CONST(0)
+#define EMC_CLKEN_OVERRIDE_0_RR_CLKEN_OVR_ENABLED                       _MK_ENUM_CONST(1)
+
+#define EMC_CLKEN_OVERRIDE_0_LL_CLKEN_OVR_SHIFT                 _MK_SHIFT_CONST(4)
+#define EMC_CLKEN_OVERRIDE_0_LL_CLKEN_OVR_FIELD                 (_MK_MASK_CONST(0x1) << EMC_CLKEN_OVERRIDE_0_LL_CLKEN_OVR_SHIFT)
+#define EMC_CLKEN_OVERRIDE_0_LL_CLKEN_OVR_RANGE                 4:4
+#define EMC_CLKEN_OVERRIDE_0_LL_CLKEN_OVR_WOFFSET                       0x0
+#define EMC_CLKEN_OVERRIDE_0_LL_CLKEN_OVR_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_CLKEN_OVERRIDE_0_LL_CLKEN_OVR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define EMC_CLKEN_OVERRIDE_0_LL_CLKEN_OVR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_CLKEN_OVERRIDE_0_LL_CLKEN_OVR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_CLKEN_OVERRIDE_0_LL_CLKEN_OVR_INIT_ENUM                     CLK_GATED
+#define EMC_CLKEN_OVERRIDE_0_LL_CLKEN_OVR_CLK_GATED                     _MK_ENUM_CONST(0)
+#define EMC_CLKEN_OVERRIDE_0_LL_CLKEN_OVR_CLK_ALWAYS_ON                 _MK_ENUM_CONST(1)
+#define EMC_CLKEN_OVERRIDE_0_LL_CLKEN_OVR_DISABLE                       _MK_ENUM_CONST(0)
+#define EMC_CLKEN_OVERRIDE_0_LL_CLKEN_OVR_ENABLE                        _MK_ENUM_CONST(1)
+#define EMC_CLKEN_OVERRIDE_0_LL_CLKEN_OVR_DISABLED                      _MK_ENUM_CONST(0)
+#define EMC_CLKEN_OVERRIDE_0_LL_CLKEN_OVR_ENABLED                       _MK_ENUM_CONST(1)
+
+#define EMC_CLKEN_OVERRIDE_0_LLSTATS_CLKEN_OVR_SHIFT                    _MK_SHIFT_CONST(5)
+#define EMC_CLKEN_OVERRIDE_0_LLSTATS_CLKEN_OVR_FIELD                    (_MK_MASK_CONST(0x1) << EMC_CLKEN_OVERRIDE_0_LLSTATS_CLKEN_OVR_SHIFT)
+#define EMC_CLKEN_OVERRIDE_0_LLSTATS_CLKEN_OVR_RANGE                    5:5
+#define EMC_CLKEN_OVERRIDE_0_LLSTATS_CLKEN_OVR_WOFFSET                  0x0
+#define EMC_CLKEN_OVERRIDE_0_LLSTATS_CLKEN_OVR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_CLKEN_OVERRIDE_0_LLSTATS_CLKEN_OVR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define EMC_CLKEN_OVERRIDE_0_LLSTATS_CLKEN_OVR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_CLKEN_OVERRIDE_0_LLSTATS_CLKEN_OVR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_CLKEN_OVERRIDE_0_LLSTATS_CLKEN_OVR_INIT_ENUM                        CLK_GATED
+#define EMC_CLKEN_OVERRIDE_0_LLSTATS_CLKEN_OVR_CLK_GATED                        _MK_ENUM_CONST(0)
+#define EMC_CLKEN_OVERRIDE_0_LLSTATS_CLKEN_OVR_CLK_ALWAYS_ON                    _MK_ENUM_CONST(1)
+#define EMC_CLKEN_OVERRIDE_0_LLSTATS_CLKEN_OVR_DISABLE                  _MK_ENUM_CONST(0)
+#define EMC_CLKEN_OVERRIDE_0_LLSTATS_CLKEN_OVR_ENABLE                   _MK_ENUM_CONST(1)
+#define EMC_CLKEN_OVERRIDE_0_LLSTATS_CLKEN_OVR_DISABLED                 _MK_ENUM_CONST(0)
+#define EMC_CLKEN_OVERRIDE_0_LLSTATS_CLKEN_OVR_ENABLED                  _MK_ENUM_CONST(1)
+
+#define EMC_CLKEN_OVERRIDE_0_STATS_CLKEN_OVR_SHIFT                      _MK_SHIFT_CONST(6)
+#define EMC_CLKEN_OVERRIDE_0_STATS_CLKEN_OVR_FIELD                      (_MK_MASK_CONST(0x1) << EMC_CLKEN_OVERRIDE_0_STATS_CLKEN_OVR_SHIFT)
+#define EMC_CLKEN_OVERRIDE_0_STATS_CLKEN_OVR_RANGE                      6:6
+#define EMC_CLKEN_OVERRIDE_0_STATS_CLKEN_OVR_WOFFSET                    0x0
+#define EMC_CLKEN_OVERRIDE_0_STATS_CLKEN_OVR_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_CLKEN_OVERRIDE_0_STATS_CLKEN_OVR_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define EMC_CLKEN_OVERRIDE_0_STATS_CLKEN_OVR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_CLKEN_OVERRIDE_0_STATS_CLKEN_OVR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_CLKEN_OVERRIDE_0_STATS_CLKEN_OVR_INIT_ENUM                  CLK_GATED
+#define EMC_CLKEN_OVERRIDE_0_STATS_CLKEN_OVR_CLK_GATED                  _MK_ENUM_CONST(0)
+#define EMC_CLKEN_OVERRIDE_0_STATS_CLKEN_OVR_CLK_ALWAYS_ON                      _MK_ENUM_CONST(1)
+#define EMC_CLKEN_OVERRIDE_0_STATS_CLKEN_OVR_DISABLE                    _MK_ENUM_CONST(0)
+#define EMC_CLKEN_OVERRIDE_0_STATS_CLKEN_OVR_ENABLE                     _MK_ENUM_CONST(1)
+#define EMC_CLKEN_OVERRIDE_0_STATS_CLKEN_OVR_DISABLED                   _MK_ENUM_CONST(0)
+#define EMC_CLKEN_OVERRIDE_0_STATS_CLKEN_OVR_ENABLED                    _MK_ENUM_CONST(1)
+
+#define NV_MC_EMEM_DFIFO_DEPTH  4
+#define NV_MC_IMEM_DFIFO_DEPTH  5
+#define NV_MC_EMEM_APFIFO_DEPTH 5
+#define NV_MC_ARB_EMEM_REGLEVEL 3
+#define NV_MC_EMEM_REQ_ID_WIDEREQ       8
+#define NV_MC_EMEM_RDI_ID_WIDERDI       8
+#define NV_MC_EMEM_REQ_ID_ILLEGALACC    7
+#define NV_MC_EMEM_RDI_ID_ILLEGALACC    7
+#define NV_MC_EMEM_REQ_ID_LLRAWDECR     6
+#define NV_MC_EMEM_RDI_ID_LLRAWDECR     6
+#define NV_MC_EMEM_REQ_ID_APCIGNORE     5
+#define NV_MC_EMEM_RDI_ID_APCIGNORE     5
+
+// Packet MC2EMC
+#define MC2EMC_SIZE 186
+
+#define MC2EMC_WDO_SHIFT                        _MK_SHIFT_CONST(0)
+#define MC2EMC_WDO_FIELD                        (_MK_MASK_CONST(0xffffffff) << MC2EMC_WDO_SHIFT)
+#define MC2EMC_WDO_RANGE                        _MK_SHIFT_CONST(127):_MK_SHIFT_CONST(0)
+#define MC2EMC_WDO_ROW                  0
+
+#define MC2EMC_WDO_0_SHIFT                      _MK_SHIFT_CONST(0)
+#define MC2EMC_WDO_0_FIELD                      (_MK_MASK_CONST(0xffffffff) << MC2EMC_WDO_0_SHIFT)
+#define MC2EMC_WDO_0_RANGE                      _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define MC2EMC_WDO_0_ROW                        0
+
+#define MC2EMC_WDO_1_SHIFT                      _MK_SHIFT_CONST(32)
+#define MC2EMC_WDO_1_FIELD                      (_MK_MASK_CONST(0xffffffff) << MC2EMC_WDO_1_SHIFT)
+#define MC2EMC_WDO_1_RANGE                      _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(32)
+#define MC2EMC_WDO_1_ROW                        0
+
+#define MC2EMC_WDO_2_SHIFT                      _MK_SHIFT_CONST(64)
+#define MC2EMC_WDO_2_FIELD                      (_MK_MASK_CONST(0xffffffff) << MC2EMC_WDO_2_SHIFT)
+#define MC2EMC_WDO_2_RANGE                      _MK_SHIFT_CONST(95):_MK_SHIFT_CONST(64)
+#define MC2EMC_WDO_2_ROW                        0
+
+#define MC2EMC_WDO_3_SHIFT                      _MK_SHIFT_CONST(96)
+#define MC2EMC_WDO_3_FIELD                      (_MK_MASK_CONST(0xffffffff) << MC2EMC_WDO_3_SHIFT)
+#define MC2EMC_WDO_3_RANGE                      _MK_SHIFT_CONST(127):_MK_SHIFT_CONST(96)
+#define MC2EMC_WDO_3_ROW                        0
+
+#define MC2EMC_BE_SHIFT                 _MK_SHIFT_CONST(128)
+#define MC2EMC_BE_FIELD                 (_MK_MASK_CONST(0xffff) << MC2EMC_BE_SHIFT)
+#define MC2EMC_BE_RANGE                 _MK_SHIFT_CONST(143):_MK_SHIFT_CONST(128)
+#define MC2EMC_BE_ROW                   0
+
+#define MC2EMC_ADR_SHIFT                        _MK_SHIFT_CONST(144)
+#define MC2EMC_ADR_FIELD                        (_MK_MASK_CONST(0x3ffffff) << MC2EMC_ADR_SHIFT)
+#define MC2EMC_ADR_RANGE                        _MK_SHIFT_CONST(169):_MK_SHIFT_CONST(144)
+#define MC2EMC_ADR_ROW                  0
+
+#define MC2EMC_REQ_ID_SHIFT                     _MK_SHIFT_CONST(170)
+#define MC2EMC_REQ_ID_FIELD                     (_MK_MASK_CONST(0x1ff) << MC2EMC_REQ_ID_SHIFT)
+#define MC2EMC_REQ_ID_RANGE                     _MK_SHIFT_CONST(178):_MK_SHIFT_CONST(170)
+#define MC2EMC_REQ_ID_ROW                       0
+
+#define MC2EMC_AP_SHIFT                 _MK_SHIFT_CONST(179)
+#define MC2EMC_AP_FIELD                 (_MK_MASK_CONST(0x1) << MC2EMC_AP_SHIFT)
+#define MC2EMC_AP_RANGE                 _MK_SHIFT_CONST(179):_MK_SHIFT_CONST(179)
+#define MC2EMC_AP_ROW                   0
+
+#define MC2EMC_WE_SHIFT                 _MK_SHIFT_CONST(180)
+#define MC2EMC_WE_FIELD                 (_MK_MASK_CONST(0x1) << MC2EMC_WE_SHIFT)
+#define MC2EMC_WE_RANGE                 _MK_SHIFT_CONST(180):_MK_SHIFT_CONST(180)
+#define MC2EMC_WE_ROW                   0
+
+#define MC2EMC_TAG_SHIFT                        _MK_SHIFT_CONST(181)
+#define MC2EMC_TAG_FIELD                        (_MK_MASK_CONST(0x1f) << MC2EMC_TAG_SHIFT)
+#define MC2EMC_TAG_RANGE                        _MK_SHIFT_CONST(185):_MK_SHIFT_CONST(181)
+#define MC2EMC_TAG_ROW                  0
+
+
+// Packet MC2EMC_APC
+#define MC2EMC_APC_SIZE 3
+
+#define MC2EMC_APC_CLR_SHIFT                    _MK_SHIFT_CONST(0)
+#define MC2EMC_APC_CLR_FIELD                    (_MK_MASK_CONST(0x1) << MC2EMC_APC_CLR_SHIFT)
+#define MC2EMC_APC_CLR_RANGE                    _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define MC2EMC_APC_CLR_ROW                      0
+
+#define MC2EMC_APC_BANK_SHIFT                   _MK_SHIFT_CONST(1)
+#define MC2EMC_APC_BANK_FIELD                   (_MK_MASK_CONST(0x3) << MC2EMC_APC_BANK_SHIFT)
+#define MC2EMC_APC_BANK_RANGE                   _MK_SHIFT_CONST(2):_MK_SHIFT_CONST(1)
+#define MC2EMC_APC_BANK_ROW                     0
+
+
+// Packet EMC2MC
+#define EMC2MC_SIZE 137
+
+#define EMC2MC_RDI_SHIFT                        _MK_SHIFT_CONST(0)
+#define EMC2MC_RDI_FIELD                        (_MK_MASK_CONST(0xffffffff) << EMC2MC_RDI_SHIFT)
+#define EMC2MC_RDI_RANGE                        _MK_SHIFT_CONST(127):_MK_SHIFT_CONST(0)
+#define EMC2MC_RDI_ROW                  0
+
+#define EMC2MC_RDI_0_SHIFT                      _MK_SHIFT_CONST(0)
+#define EMC2MC_RDI_0_FIELD                      (_MK_MASK_CONST(0xffffffff) << EMC2MC_RDI_0_SHIFT)
+#define EMC2MC_RDI_0_RANGE                      _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define EMC2MC_RDI_0_ROW                        0
+
+#define EMC2MC_RDI_1_SHIFT                      _MK_SHIFT_CONST(32)
+#define EMC2MC_RDI_1_FIELD                      (_MK_MASK_CONST(0xffffffff) << EMC2MC_RDI_1_SHIFT)
+#define EMC2MC_RDI_1_RANGE                      _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(32)
+#define EMC2MC_RDI_1_ROW                        0
+
+#define EMC2MC_RDI_2_SHIFT                      _MK_SHIFT_CONST(64)
+#define EMC2MC_RDI_2_FIELD                      (_MK_MASK_CONST(0xffffffff) << EMC2MC_RDI_2_SHIFT)
+#define EMC2MC_RDI_2_RANGE                      _MK_SHIFT_CONST(95):_MK_SHIFT_CONST(64)
+#define EMC2MC_RDI_2_ROW                        0
+
+#define EMC2MC_RDI_3_SHIFT                      _MK_SHIFT_CONST(96)
+#define EMC2MC_RDI_3_FIELD                      (_MK_MASK_CONST(0xffffffff) << EMC2MC_RDI_3_SHIFT)
+#define EMC2MC_RDI_3_RANGE                      _MK_SHIFT_CONST(127):_MK_SHIFT_CONST(96)
+#define EMC2MC_RDI_3_ROW                        0
+
+#define EMC2MC_RDI_ID_SHIFT                     _MK_SHIFT_CONST(128)
+#define EMC2MC_RDI_ID_FIELD                     (_MK_MASK_CONST(0x1ff) << EMC2MC_RDI_ID_SHIFT)
+#define EMC2MC_RDI_ID_RANGE                     _MK_SHIFT_CONST(136):_MK_SHIFT_CONST(128)
+#define EMC2MC_RDI_ID_ROW                       0
+
+
+// Packet MC2EMC_LL
+#define MC2EMC_LL_SIZE 33
+
+#define MC2EMC_LL_ADR_SHIFT                     _MK_SHIFT_CONST(0)
+#define MC2EMC_LL_ADR_FIELD                     (_MK_MASK_CONST(0x7ffffff) << MC2EMC_LL_ADR_SHIFT)
+#define MC2EMC_LL_ADR_RANGE                     _MK_SHIFT_CONST(26):_MK_SHIFT_CONST(0)
+#define MC2EMC_LL_ADR_ROW                       0
+
+#define MC2EMC_LL_TAG_SHIFT                     _MK_SHIFT_CONST(27)
+#define MC2EMC_LL_TAG_FIELD                     (_MK_MASK_CONST(0x1f) << MC2EMC_LL_TAG_SHIFT)
+#define MC2EMC_LL_TAG_RANGE                     _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(27)
+#define MC2EMC_LL_TAG_ROW                       0
+
+#define MC2EMC_LL_DOUBLEREQ_SHIFT                       _MK_SHIFT_CONST(32)
+#define MC2EMC_LL_DOUBLEREQ_FIELD                       (_MK_MASK_CONST(0x1) << MC2EMC_LL_DOUBLEREQ_SHIFT)
+#define MC2EMC_LL_DOUBLEREQ_RANGE                       _MK_SHIFT_CONST(32):_MK_SHIFT_CONST(32)
+#define MC2EMC_LL_DOUBLEREQ_ROW                 0
+
+
+// Packet EMC2MC_LL
+#define EMC2MC_LL_SIZE 64
+
+#define EMC2MC_LL_RDI_SHIFT                     _MK_SHIFT_CONST(0)
+#define EMC2MC_LL_RDI_FIELD                     (_MK_MASK_CONST(0xffffffff) << EMC2MC_LL_RDI_SHIFT)
+#define EMC2MC_LL_RDI_RANGE                     _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(0)
+#define EMC2MC_LL_RDI_ROW                       0
+
+
+// Packet MC2EMC_LL_CRITINFO
+#define MC2EMC_LL_CRITINFO_SIZE 11
+
+#define MC2EMC_LL_CRITINFO_HP_SHIFT                     _MK_SHIFT_CONST(0)
+#define MC2EMC_LL_CRITINFO_HP_FIELD                     (_MK_MASK_CONST(0x1f) << MC2EMC_LL_CRITINFO_HP_SHIFT)
+#define MC2EMC_LL_CRITINFO_HP_RANGE                     _MK_SHIFT_CONST(4):_MK_SHIFT_CONST(0)
+#define MC2EMC_LL_CRITINFO_HP_ROW                       0
+
+#define MC2EMC_LL_CRITINFO_TIMEOUT_SHIFT                        _MK_SHIFT_CONST(5)
+#define MC2EMC_LL_CRITINFO_TIMEOUT_FIELD                        (_MK_MASK_CONST(0x3f) << MC2EMC_LL_CRITINFO_TIMEOUT_SHIFT)
+#define MC2EMC_LL_CRITINFO_TIMEOUT_RANGE                        _MK_SHIFT_CONST(10):_MK_SHIFT_CONST(5)
+#define MC2EMC_LL_CRITINFO_TIMEOUT_ROW                  0
+
+
+// Packet MC2EMC_LL_ARBINFO
+#define MC2EMC_LL_ARBINFO_SIZE 2
+
+#define MC2EMC_LL_ARBINFO_BANK_SHIFT                    _MK_SHIFT_CONST(0)
+#define MC2EMC_LL_ARBINFO_BANK_FIELD                    (_MK_MASK_CONST(0x3) << MC2EMC_LL_ARBINFO_BANK_SHIFT)
+#define MC2EMC_LL_ARBINFO_BANK_RANGE                    _MK_SHIFT_CONST(1):_MK_SHIFT_CONST(0)
+#define MC2EMC_LL_ARBINFO_BANK_ROW                      0
+
+
+// Packet CMC2MC_AXI_A
+#define CMC2MC_AXI_A_SIZE 63
+
+#define CMC2MC_AXI_A_AADDR_SHIFT                        _MK_SHIFT_CONST(0)
+#define CMC2MC_AXI_A_AADDR_FIELD                        (_MK_MASK_CONST(0xffffffff) << CMC2MC_AXI_A_AADDR_SHIFT)
+#define CMC2MC_AXI_A_AADDR_RANGE                        _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CMC2MC_AXI_A_AADDR_ROW                  0
+
+#define CMC2MC_AXI_A_AID_SHIFT                  _MK_SHIFT_CONST(32)
+#define CMC2MC_AXI_A_AID_FIELD                  (_MK_MASK_CONST(0x1fff) << CMC2MC_AXI_A_AID_SHIFT)
+#define CMC2MC_AXI_A_AID_RANGE                  _MK_SHIFT_CONST(44):_MK_SHIFT_CONST(32)
+#define CMC2MC_AXI_A_AID_ROW                    0
+
+#define CMC2MC_AXI_A_ALEN_SHIFT                 _MK_SHIFT_CONST(45)
+#define CMC2MC_AXI_A_ALEN_FIELD                 (_MK_MASK_CONST(0xf) << CMC2MC_AXI_A_ALEN_SHIFT)
+#define CMC2MC_AXI_A_ALEN_RANGE                 _MK_SHIFT_CONST(48):_MK_SHIFT_CONST(45)
+#define CMC2MC_AXI_A_ALEN_ROW                   0
+#define CMC2MC_AXI_A_ALEN_ONEDATA                       _MK_ENUM_CONST(0)
+#define CMC2MC_AXI_A_ALEN_TWODATA                       _MK_ENUM_CONST(1)
+#define CMC2MC_AXI_A_ALEN_THREEDATA                     _MK_ENUM_CONST(2)
+#define CMC2MC_AXI_A_ALEN_FOURDATA                      _MK_ENUM_CONST(3)
+#define CMC2MC_AXI_A_ALEN_FIVEDATA                      _MK_ENUM_CONST(4)
+#define CMC2MC_AXI_A_ALEN_SIXDATA                       _MK_ENUM_CONST(5)
+#define CMC2MC_AXI_A_ALEN_SEVENDATA                     _MK_ENUM_CONST(6)
+#define CMC2MC_AXI_A_ALEN_EIGHTDATA                     _MK_ENUM_CONST(7)
+#define CMC2MC_AXI_A_ALEN_NINEDATA                      _MK_ENUM_CONST(8)
+#define CMC2MC_AXI_A_ALEN_TENDATA                       _MK_ENUM_CONST(9)
+#define CMC2MC_AXI_A_ALEN_ELEVENDATA                    _MK_ENUM_CONST(10)
+#define CMC2MC_AXI_A_ALEN_TWELVEDATA                    _MK_ENUM_CONST(11)
+#define CMC2MC_AXI_A_ALEN_THIRTEENDATA                  _MK_ENUM_CONST(12)
+#define CMC2MC_AXI_A_ALEN_FOURTEENDATA                  _MK_ENUM_CONST(13)
+#define CMC2MC_AXI_A_ALEN_FIFTHTEENDATA                 _MK_ENUM_CONST(14)
+#define CMC2MC_AXI_A_ALEN_SIXTEENDATA                   _MK_ENUM_CONST(15)
+
+#define CMC2MC_AXI_A_ASIZE_SHIFT                        _MK_SHIFT_CONST(49)
+#define CMC2MC_AXI_A_ASIZE_FIELD                        (_MK_MASK_CONST(0x7) << CMC2MC_AXI_A_ASIZE_SHIFT)
+#define CMC2MC_AXI_A_ASIZE_RANGE                        _MK_SHIFT_CONST(51):_MK_SHIFT_CONST(49)
+#define CMC2MC_AXI_A_ASIZE_ROW                  0
+#define CMC2MC_AXI_A_ASIZE_ONEBYTE                      _MK_ENUM_CONST(0)
+#define CMC2MC_AXI_A_ASIZE_TWOBYTES                     _MK_ENUM_CONST(1)
+#define CMC2MC_AXI_A_ASIZE_FOURBYTES                    _MK_ENUM_CONST(2)
+#define CMC2MC_AXI_A_ASIZE_EIGHTBYTES                   _MK_ENUM_CONST(3)
+#define CMC2MC_AXI_A_ASIZE_SIXTEENBYTES                 _MK_ENUM_CONST(4)
+#define CMC2MC_AXI_A_ASIZE_THIRTYTWOBYTES                       _MK_ENUM_CONST(5)
+#define CMC2MC_AXI_A_ASIZE_SIXTYFOURBYTES                       _MK_ENUM_CONST(6)
+#define CMC2MC_AXI_A_ASIZE_ONEHUNDREDTWENTYEIGHTBYTES                   _MK_ENUM_CONST(7)
+
+#define CMC2MC_AXI_A_ABURST_SHIFT                       _MK_SHIFT_CONST(52)
+#define CMC2MC_AXI_A_ABURST_FIELD                       (_MK_MASK_CONST(0x3) << CMC2MC_AXI_A_ABURST_SHIFT)
+#define CMC2MC_AXI_A_ABURST_RANGE                       _MK_SHIFT_CONST(53):_MK_SHIFT_CONST(52)
+#define CMC2MC_AXI_A_ABURST_ROW                 0
+#define CMC2MC_AXI_A_ABURST_FIXED                       _MK_ENUM_CONST(0)
+#define CMC2MC_AXI_A_ABURST_INCR                        _MK_ENUM_CONST(1)
+#define CMC2MC_AXI_A_ABURST_WRAP                        _MK_ENUM_CONST(2)
+#define CMC2MC_AXI_A_ABURST_RSVD                        _MK_ENUM_CONST(3)
+
+#define CMC2MC_AXI_A_ALOCK_SHIFT                        _MK_SHIFT_CONST(54)
+#define CMC2MC_AXI_A_ALOCK_FIELD                        (_MK_MASK_CONST(0x3) << CMC2MC_AXI_A_ALOCK_SHIFT)
+#define CMC2MC_AXI_A_ALOCK_RANGE                        _MK_SHIFT_CONST(55):_MK_SHIFT_CONST(54)
+#define CMC2MC_AXI_A_ALOCK_ROW                  0
+#define CMC2MC_AXI_A_ALOCK_NORMAL                       _MK_ENUM_CONST(0)
+#define CMC2MC_AXI_A_ALOCK_EXCLUSIVE                    _MK_ENUM_CONST(1)
+#define CMC2MC_AXI_A_ALOCK_LOCKED                       _MK_ENUM_CONST(2)
+#define CMC2MC_AXI_A_ALOCK_RSVD                 _MK_ENUM_CONST(3)
+
+#define CMC2MC_AXI_A_ACACHE_SHIFT                       _MK_SHIFT_CONST(56)
+#define CMC2MC_AXI_A_ACACHE_FIELD                       (_MK_MASK_CONST(0xf) << CMC2MC_AXI_A_ACACHE_SHIFT)
+#define CMC2MC_AXI_A_ACACHE_RANGE                       _MK_SHIFT_CONST(59):_MK_SHIFT_CONST(56)
+#define CMC2MC_AXI_A_ACACHE_ROW                 0
+#define CMC2MC_AXI_A_ACACHE_NONCACHEABLE_NONBUFFERABLE                  _MK_ENUM_CONST(0)
+#define CMC2MC_AXI_A_ACACHE_BUFFERABLE                  _MK_ENUM_CONST(1)
+#define CMC2MC_AXI_A_ACACHE_CACHEABLE_DONOTALLOCATE                     _MK_ENUM_CONST(2)
+#define CMC2MC_AXI_A_ACACHE_CACHEABLE_BUFFERABLE_DONOTALLOCATE                  _MK_ENUM_CONST(3)
+#define CMC2MC_AXI_A_ACACHE_CACHEABLEWRITETHROUGH_ALLOCATEONREAD                        _MK_ENUM_CONST(6)
+#define CMC2MC_AXI_A_ACACHE_CACHEABLEWRITEBACK_ALLOCATEONREAD                   _MK_ENUM_CONST(7)
+#define CMC2MC_AXI_A_ACACHE_CACHEABLEWRITETHROUGH_ALLOCATEONWRITE                       _MK_ENUM_CONST(10)
+#define CMC2MC_AXI_A_ACACHE_CACHEABLEWRITEBACK_ALLOCATEONWRITE                  _MK_ENUM_CONST(11)
+#define CMC2MC_AXI_A_ACACHE_CACHEABLEWRITETHROUGH_ALLOCATEONREADWRITE                   _MK_ENUM_CONST(14)
+#define CMC2MC_AXI_A_ACACHE_CACHEABLEWRITEBACK_ALLOCATEONREADWRITE                      _MK_ENUM_CONST(15)
+
+#define CMC2MC_AXI_A_APROT_SHIFT                        _MK_SHIFT_CONST(60)
+#define CMC2MC_AXI_A_APROT_FIELD                        (_MK_MASK_CONST(0x7) << CMC2MC_AXI_A_APROT_SHIFT)
+#define CMC2MC_AXI_A_APROT_RANGE                        _MK_SHIFT_CONST(62):_MK_SHIFT_CONST(60)
+#define CMC2MC_AXI_A_APROT_ROW                  0
+#define CMC2MC_AXI_A_APROT_DATA_SECURE_NORMAL                   _MK_ENUM_CONST(0)
+#define CMC2MC_AXI_A_APROT_DATA_SECURE_PRIVILEGED                       _MK_ENUM_CONST(1)
+#define CMC2MC_AXI_A_APROT_DATA_NONSECURE_NORMAL                        _MK_ENUM_CONST(2)
+#define CMC2MC_AXI_A_APROT_DATA_NONSECURE_PRIVILEGED                    _MK_ENUM_CONST(3)
+#define CMC2MC_AXI_A_APROT_INST_SECURE_NORMAL                   _MK_ENUM_CONST(4)
+#define CMC2MC_AXI_A_APROT_INST_SECURE_PRIVILEGED                       _MK_ENUM_CONST(5)
+#define CMC2MC_AXI_A_APROT_INST_NONSECURE_NORMAL                        _MK_ENUM_CONST(6)
+#define CMC2MC_AXI_A_APROT_INST_NONSECURE_PRIVILEGED                    _MK_ENUM_CONST(7)
+
+
+// Packet CMC2MC_AXI_W
+#define CMC2MC_AXI_W_SIZE 86
+
+#define CMC2MC_AXI_W_WDATA_SHIFT                        _MK_SHIFT_CONST(0)
+#define CMC2MC_AXI_W_WDATA_FIELD                        (_MK_MASK_CONST(0xffffffff) << CMC2MC_AXI_W_WDATA_SHIFT)
+#define CMC2MC_AXI_W_WDATA_RANGE                        _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(0)
+#define CMC2MC_AXI_W_WDATA_ROW                  0
+
+#define CMC2MC_AXI_W_WID_SHIFT                  _MK_SHIFT_CONST(64)
+#define CMC2MC_AXI_W_WID_FIELD                  (_MK_MASK_CONST(0x1fff) << CMC2MC_AXI_W_WID_SHIFT)
+#define CMC2MC_AXI_W_WID_RANGE                  _MK_SHIFT_CONST(76):_MK_SHIFT_CONST(64)
+#define CMC2MC_AXI_W_WID_ROW                    0
+
+#define CMC2MC_AXI_W_WSTRB_SHIFT                        _MK_SHIFT_CONST(77)
+#define CMC2MC_AXI_W_WSTRB_FIELD                        (_MK_MASK_CONST(0xff) << CMC2MC_AXI_W_WSTRB_SHIFT)
+#define CMC2MC_AXI_W_WSTRB_RANGE                        _MK_SHIFT_CONST(84):_MK_SHIFT_CONST(77)
+#define CMC2MC_AXI_W_WSTRB_ROW                  0
+
+#define CMC2MC_AXI_W_WLAST_SHIFT                        _MK_SHIFT_CONST(85)
+#define CMC2MC_AXI_W_WLAST_FIELD                        (_MK_MASK_CONST(0x1) << CMC2MC_AXI_W_WLAST_SHIFT)
+#define CMC2MC_AXI_W_WLAST_RANGE                        _MK_SHIFT_CONST(85):_MK_SHIFT_CONST(85)
+#define CMC2MC_AXI_W_WLAST_ROW                  0
+#define CMC2MC_AXI_W_WLAST_DISABLED                     _MK_ENUM_CONST(0)
+#define CMC2MC_AXI_W_WLAST_ENABLED                      _MK_ENUM_CONST(1)
+
+
+// Packet CMC2MC_AXI_B
+#define CMC2MC_AXI_B_SIZE 15
+
+#define CMC2MC_AXI_B_BID_SHIFT                  _MK_SHIFT_CONST(0)
+#define CMC2MC_AXI_B_BID_FIELD                  (_MK_MASK_CONST(0x1fff) << CMC2MC_AXI_B_BID_SHIFT)
+#define CMC2MC_AXI_B_BID_RANGE                  _MK_SHIFT_CONST(12):_MK_SHIFT_CONST(0)
+#define CMC2MC_AXI_B_BID_ROW                    0
+
+#define CMC2MC_AXI_B_BRESP_SHIFT                        _MK_SHIFT_CONST(13)
+#define CMC2MC_AXI_B_BRESP_FIELD                        (_MK_MASK_CONST(0x3) << CMC2MC_AXI_B_BRESP_SHIFT)
+#define CMC2MC_AXI_B_BRESP_RANGE                        _MK_SHIFT_CONST(14):_MK_SHIFT_CONST(13)
+#define CMC2MC_AXI_B_BRESP_ROW                  0
+#define CMC2MC_AXI_B_BRESP_OKAY                 _MK_ENUM_CONST(0)
+#define CMC2MC_AXI_B_BRESP_EXOKAY                       _MK_ENUM_CONST(1)
+#define CMC2MC_AXI_B_BRESP_SLVERR                       _MK_ENUM_CONST(2)
+#define CMC2MC_AXI_B_BRESP_DECERR                       _MK_ENUM_CONST(3)
+
+
+// Packet CMC2MC_AXI_R
+#define CMC2MC_AXI_R_SIZE 80
+
+#define CMC2MC_AXI_R_RDATA_SHIFT                        _MK_SHIFT_CONST(0)
+#define CMC2MC_AXI_R_RDATA_FIELD                        (_MK_MASK_CONST(0xffffffff) << CMC2MC_AXI_R_RDATA_SHIFT)
+#define CMC2MC_AXI_R_RDATA_RANGE                        _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(0)
+#define CMC2MC_AXI_R_RDATA_ROW                  0
+
+#define CMC2MC_AXI_R_RID_SHIFT                  _MK_SHIFT_CONST(64)
+#define CMC2MC_AXI_R_RID_FIELD                  (_MK_MASK_CONST(0x1fff) << CMC2MC_AXI_R_RID_SHIFT)
+#define CMC2MC_AXI_R_RID_RANGE                  _MK_SHIFT_CONST(76):_MK_SHIFT_CONST(64)
+#define CMC2MC_AXI_R_RID_ROW                    0
+
+#define CMC2MC_AXI_R_RRESP_SHIFT                        _MK_SHIFT_CONST(77)
+#define CMC2MC_AXI_R_RRESP_FIELD                        (_MK_MASK_CONST(0x3) << CMC2MC_AXI_R_RRESP_SHIFT)
+#define CMC2MC_AXI_R_RRESP_RANGE                        _MK_SHIFT_CONST(78):_MK_SHIFT_CONST(77)
+#define CMC2MC_AXI_R_RRESP_ROW                  0
+#define CMC2MC_AXI_R_RRESP_OKAY                 _MK_ENUM_CONST(0)
+#define CMC2MC_AXI_R_RRESP_EXOKAY                       _MK_ENUM_CONST(1)
+#define CMC2MC_AXI_R_RRESP_SLVERR                       _MK_ENUM_CONST(2)
+#define CMC2MC_AXI_R_RRESP_DECERR                       _MK_ENUM_CONST(3)
+
+#define CMC2MC_AXI_R_RLAST_SHIFT                        _MK_SHIFT_CONST(79)
+#define CMC2MC_AXI_R_RLAST_FIELD                        (_MK_MASK_CONST(0x1) << CMC2MC_AXI_R_RLAST_SHIFT)
+#define CMC2MC_AXI_R_RLAST_RANGE                        _MK_SHIFT_CONST(79):_MK_SHIFT_CONST(79)
+#define CMC2MC_AXI_R_RLAST_ROW                  0
+#define CMC2MC_AXI_R_RLAST_DISABLED                     _MK_ENUM_CONST(0)
+#define CMC2MC_AXI_R_RLAST_ENABLED                      _MK_ENUM_CONST(1)
+
+
+// Packet MSELECT2MC_AXI_A
+#define MSELECT2MC_AXI_A_SIZE 63
+
+#define MSELECT2MC_AXI_A_AADDR_SHIFT                    _MK_SHIFT_CONST(0)
+#define MSELECT2MC_AXI_A_AADDR_FIELD                    (_MK_MASK_CONST(0xffffffff) << MSELECT2MC_AXI_A_AADDR_SHIFT)
+#define MSELECT2MC_AXI_A_AADDR_RANGE                    _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define MSELECT2MC_AXI_A_AADDR_ROW                      0
+
+#define MSELECT2MC_AXI_A_AID_SHIFT                      _MK_SHIFT_CONST(32)
+#define MSELECT2MC_AXI_A_AID_FIELD                      (_MK_MASK_CONST(0x1fff) << MSELECT2MC_AXI_A_AID_SHIFT)
+#define MSELECT2MC_AXI_A_AID_RANGE                      _MK_SHIFT_CONST(44):_MK_SHIFT_CONST(32)
+#define MSELECT2MC_AXI_A_AID_ROW                        0
+
+#define MSELECT2MC_AXI_A_ALEN_SHIFT                     _MK_SHIFT_CONST(45)
+#define MSELECT2MC_AXI_A_ALEN_FIELD                     (_MK_MASK_CONST(0xf) << MSELECT2MC_AXI_A_ALEN_SHIFT)
+#define MSELECT2MC_AXI_A_ALEN_RANGE                     _MK_SHIFT_CONST(48):_MK_SHIFT_CONST(45)
+#define MSELECT2MC_AXI_A_ALEN_ROW                       0
+#define MSELECT2MC_AXI_A_ALEN_ONEDATA                   _MK_ENUM_CONST(0)
+#define MSELECT2MC_AXI_A_ALEN_TWODATA                   _MK_ENUM_CONST(1)
+#define MSELECT2MC_AXI_A_ALEN_THREEDATA                 _MK_ENUM_CONST(2)
+#define MSELECT2MC_AXI_A_ALEN_FOURDATA                  _MK_ENUM_CONST(3)
+#define MSELECT2MC_AXI_A_ALEN_FIVEDATA                  _MK_ENUM_CONST(4)
+#define MSELECT2MC_AXI_A_ALEN_SIXDATA                   _MK_ENUM_CONST(5)
+#define MSELECT2MC_AXI_A_ALEN_SEVENDATA                 _MK_ENUM_CONST(6)
+#define MSELECT2MC_AXI_A_ALEN_EIGHTDATA                 _MK_ENUM_CONST(7)
+#define MSELECT2MC_AXI_A_ALEN_NINEDATA                  _MK_ENUM_CONST(8)
+#define MSELECT2MC_AXI_A_ALEN_TENDATA                   _MK_ENUM_CONST(9)
+#define MSELECT2MC_AXI_A_ALEN_ELEVENDATA                        _MK_ENUM_CONST(10)
+#define MSELECT2MC_AXI_A_ALEN_TWELVEDATA                        _MK_ENUM_CONST(11)
+#define MSELECT2MC_AXI_A_ALEN_THIRTEENDATA                      _MK_ENUM_CONST(12)
+#define MSELECT2MC_AXI_A_ALEN_FOURTEENDATA                      _MK_ENUM_CONST(13)
+#define MSELECT2MC_AXI_A_ALEN_FIFTHTEENDATA                     _MK_ENUM_CONST(14)
+#define MSELECT2MC_AXI_A_ALEN_SIXTEENDATA                       _MK_ENUM_CONST(15)
+
+#define MSELECT2MC_AXI_A_ASIZE_SHIFT                    _MK_SHIFT_CONST(49)
+#define MSELECT2MC_AXI_A_ASIZE_FIELD                    (_MK_MASK_CONST(0x7) << MSELECT2MC_AXI_A_ASIZE_SHIFT)
+#define MSELECT2MC_AXI_A_ASIZE_RANGE                    _MK_SHIFT_CONST(51):_MK_SHIFT_CONST(49)
+#define MSELECT2MC_AXI_A_ASIZE_ROW                      0
+#define MSELECT2MC_AXI_A_ASIZE_ONEBYTE                  _MK_ENUM_CONST(0)
+#define MSELECT2MC_AXI_A_ASIZE_TWOBYTES                 _MK_ENUM_CONST(1)
+#define MSELECT2MC_AXI_A_ASIZE_FOURBYTES                        _MK_ENUM_CONST(2)
+#define MSELECT2MC_AXI_A_ASIZE_EIGHTBYTES                       _MK_ENUM_CONST(3)
+#define MSELECT2MC_AXI_A_ASIZE_SIXTEENBYTES                     _MK_ENUM_CONST(4)
+#define MSELECT2MC_AXI_A_ASIZE_THIRTYTWOBYTES                   _MK_ENUM_CONST(5)
+#define MSELECT2MC_AXI_A_ASIZE_SIXTYFOURBYTES                   _MK_ENUM_CONST(6)
+#define MSELECT2MC_AXI_A_ASIZE_ONEHUNDREDTWENTYEIGHTBYTES                       _MK_ENUM_CONST(7)
+
+#define MSELECT2MC_AXI_A_ABURST_SHIFT                   _MK_SHIFT_CONST(52)
+#define MSELECT2MC_AXI_A_ABURST_FIELD                   (_MK_MASK_CONST(0x3) << MSELECT2MC_AXI_A_ABURST_SHIFT)
+#define MSELECT2MC_AXI_A_ABURST_RANGE                   _MK_SHIFT_CONST(53):_MK_SHIFT_CONST(52)
+#define MSELECT2MC_AXI_A_ABURST_ROW                     0
+#define MSELECT2MC_AXI_A_ABURST_FIXED                   _MK_ENUM_CONST(0)
+#define MSELECT2MC_AXI_A_ABURST_INCR                    _MK_ENUM_CONST(1)
+#define MSELECT2MC_AXI_A_ABURST_WRAP                    _MK_ENUM_CONST(2)
+#define MSELECT2MC_AXI_A_ABURST_RSVD                    _MK_ENUM_CONST(3)
+
+#define MSELECT2MC_AXI_A_ALOCK_SHIFT                    _MK_SHIFT_CONST(54)
+#define MSELECT2MC_AXI_A_ALOCK_FIELD                    (_MK_MASK_CONST(0x3) << MSELECT2MC_AXI_A_ALOCK_SHIFT)
+#define MSELECT2MC_AXI_A_ALOCK_RANGE                    _MK_SHIFT_CONST(55):_MK_SHIFT_CONST(54)
+#define MSELECT2MC_AXI_A_ALOCK_ROW                      0
+#define MSELECT2MC_AXI_A_ALOCK_NORMAL                   _MK_ENUM_CONST(0)
+#define MSELECT2MC_AXI_A_ALOCK_EXCLUSIVE                        _MK_ENUM_CONST(1)
+#define MSELECT2MC_AXI_A_ALOCK_LOCKED                   _MK_ENUM_CONST(2)
+#define MSELECT2MC_AXI_A_ALOCK_RSVD                     _MK_ENUM_CONST(3)
+
+#define MSELECT2MC_AXI_A_ACACHE_SHIFT                   _MK_SHIFT_CONST(56)
+#define MSELECT2MC_AXI_A_ACACHE_FIELD                   (_MK_MASK_CONST(0xf) << MSELECT2MC_AXI_A_ACACHE_SHIFT)
+#define MSELECT2MC_AXI_A_ACACHE_RANGE                   _MK_SHIFT_CONST(59):_MK_SHIFT_CONST(56)
+#define MSELECT2MC_AXI_A_ACACHE_ROW                     0
+#define MSELECT2MC_AXI_A_ACACHE_NONCACHEABLE_NONBUFFERABLE                      _MK_ENUM_CONST(0)
+#define MSELECT2MC_AXI_A_ACACHE_BUFFERABLE                      _MK_ENUM_CONST(1)
+#define MSELECT2MC_AXI_A_ACACHE_CACHEABLE_DONOTALLOCATE                 _MK_ENUM_CONST(2)
+#define MSELECT2MC_AXI_A_ACACHE_CACHEABLE_BUFFERABLE_DONOTALLOCATE                      _MK_ENUM_CONST(3)
+#define MSELECT2MC_AXI_A_ACACHE_CACHEABLEWRITETHROUGH_ALLOCATEONREAD                    _MK_ENUM_CONST(6)
+#define MSELECT2MC_AXI_A_ACACHE_CACHEABLEWRITEBACK_ALLOCATEONREAD                       _MK_ENUM_CONST(7)
+#define MSELECT2MC_AXI_A_ACACHE_CACHEABLEWRITETHROUGH_ALLOCATEONWRITE                   _MK_ENUM_CONST(10)
+#define MSELECT2MC_AXI_A_ACACHE_CACHEABLEWRITEBACK_ALLOCATEONWRITE                      _MK_ENUM_CONST(11)
+#define MSELECT2MC_AXI_A_ACACHE_CACHEABLEWRITETHROUGH_ALLOCATEONREADWRITE                       _MK_ENUM_CONST(14)
+#define MSELECT2MC_AXI_A_ACACHE_CACHEABLEWRITEBACK_ALLOCATEONREADWRITE                  _MK_ENUM_CONST(15)
+
+#define MSELECT2MC_AXI_A_APROT_SHIFT                    _MK_SHIFT_CONST(60)
+#define MSELECT2MC_AXI_A_APROT_FIELD                    (_MK_MASK_CONST(0x7) << MSELECT2MC_AXI_A_APROT_SHIFT)
+#define MSELECT2MC_AXI_A_APROT_RANGE                    _MK_SHIFT_CONST(62):_MK_SHIFT_CONST(60)
+#define MSELECT2MC_AXI_A_APROT_ROW                      0
+#define MSELECT2MC_AXI_A_APROT_DATA_SECURE_NORMAL                       _MK_ENUM_CONST(0)
+#define MSELECT2MC_AXI_A_APROT_DATA_SECURE_PRIVILEGED                   _MK_ENUM_CONST(1)
+#define MSELECT2MC_AXI_A_APROT_DATA_NONSECURE_NORMAL                    _MK_ENUM_CONST(2)
+#define MSELECT2MC_AXI_A_APROT_DATA_NONSECURE_PRIVILEGED                        _MK_ENUM_CONST(3)
+#define MSELECT2MC_AXI_A_APROT_INST_SECURE_NORMAL                       _MK_ENUM_CONST(4)
+#define MSELECT2MC_AXI_A_APROT_INST_SECURE_PRIVILEGED                   _MK_ENUM_CONST(5)
+#define MSELECT2MC_AXI_A_APROT_INST_NONSECURE_NORMAL                    _MK_ENUM_CONST(6)
+#define MSELECT2MC_AXI_A_APROT_INST_NONSECURE_PRIVILEGED                        _MK_ENUM_CONST(7)
+
+
+// Packet MSELECT2MC_AXI_W
+#define MSELECT2MC_AXI_W_SIZE 86
+
+#define MSELECT2MC_AXI_W_WDATA_SHIFT                    _MK_SHIFT_CONST(0)
+#define MSELECT2MC_AXI_W_WDATA_FIELD                    (_MK_MASK_CONST(0xffffffff) << MSELECT2MC_AXI_W_WDATA_SHIFT)
+#define MSELECT2MC_AXI_W_WDATA_RANGE                    _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(0)
+#define MSELECT2MC_AXI_W_WDATA_ROW                      0
+
+#define MSELECT2MC_AXI_W_WID_SHIFT                      _MK_SHIFT_CONST(64)
+#define MSELECT2MC_AXI_W_WID_FIELD                      (_MK_MASK_CONST(0x1fff) << MSELECT2MC_AXI_W_WID_SHIFT)
+#define MSELECT2MC_AXI_W_WID_RANGE                      _MK_SHIFT_CONST(76):_MK_SHIFT_CONST(64)
+#define MSELECT2MC_AXI_W_WID_ROW                        0
+
+#define MSELECT2MC_AXI_W_WSTRB_SHIFT                    _MK_SHIFT_CONST(77)
+#define MSELECT2MC_AXI_W_WSTRB_FIELD                    (_MK_MASK_CONST(0xff) << MSELECT2MC_AXI_W_WSTRB_SHIFT)
+#define MSELECT2MC_AXI_W_WSTRB_RANGE                    _MK_SHIFT_CONST(84):_MK_SHIFT_CONST(77)
+#define MSELECT2MC_AXI_W_WSTRB_ROW                      0
+
+#define MSELECT2MC_AXI_W_WLAST_SHIFT                    _MK_SHIFT_CONST(85)
+#define MSELECT2MC_AXI_W_WLAST_FIELD                    (_MK_MASK_CONST(0x1) << MSELECT2MC_AXI_W_WLAST_SHIFT)
+#define MSELECT2MC_AXI_W_WLAST_RANGE                    _MK_SHIFT_CONST(85):_MK_SHIFT_CONST(85)
+#define MSELECT2MC_AXI_W_WLAST_ROW                      0
+#define MSELECT2MC_AXI_W_WLAST_DISABLED                 _MK_ENUM_CONST(0)
+#define MSELECT2MC_AXI_W_WLAST_ENABLED                  _MK_ENUM_CONST(1)
+
+
+// Packet MSELECT2MC_AXI_B
+#define MSELECT2MC_AXI_B_SIZE 15
+
+#define MSELECT2MC_AXI_B_BID_SHIFT                      _MK_SHIFT_CONST(0)
+#define MSELECT2MC_AXI_B_BID_FIELD                      (_MK_MASK_CONST(0x1fff) << MSELECT2MC_AXI_B_BID_SHIFT)
+#define MSELECT2MC_AXI_B_BID_RANGE                      _MK_SHIFT_CONST(12):_MK_SHIFT_CONST(0)
+#define MSELECT2MC_AXI_B_BID_ROW                        0
+
+#define MSELECT2MC_AXI_B_BRESP_SHIFT                    _MK_SHIFT_CONST(13)
+#define MSELECT2MC_AXI_B_BRESP_FIELD                    (_MK_MASK_CONST(0x3) << MSELECT2MC_AXI_B_BRESP_SHIFT)
+#define MSELECT2MC_AXI_B_BRESP_RANGE                    _MK_SHIFT_CONST(14):_MK_SHIFT_CONST(13)
+#define MSELECT2MC_AXI_B_BRESP_ROW                      0
+#define MSELECT2MC_AXI_B_BRESP_OKAY                     _MK_ENUM_CONST(0)
+#define MSELECT2MC_AXI_B_BRESP_EXOKAY                   _MK_ENUM_CONST(1)
+#define MSELECT2MC_AXI_B_BRESP_SLVERR                   _MK_ENUM_CONST(2)
+#define MSELECT2MC_AXI_B_BRESP_DECERR                   _MK_ENUM_CONST(3)
+
+
+// Packet MSELECT2MC_AXI_R
+#define MSELECT2MC_AXI_R_SIZE 80
+
+#define MSELECT2MC_AXI_R_RDATA_SHIFT                    _MK_SHIFT_CONST(0)
+#define MSELECT2MC_AXI_R_RDATA_FIELD                    (_MK_MASK_CONST(0xffffffff) << MSELECT2MC_AXI_R_RDATA_SHIFT)
+#define MSELECT2MC_AXI_R_RDATA_RANGE                    _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(0)
+#define MSELECT2MC_AXI_R_RDATA_ROW                      0
+
+#define MSELECT2MC_AXI_R_RID_SHIFT                      _MK_SHIFT_CONST(64)
+#define MSELECT2MC_AXI_R_RID_FIELD                      (_MK_MASK_CONST(0x1fff) << MSELECT2MC_AXI_R_RID_SHIFT)
+#define MSELECT2MC_AXI_R_RID_RANGE                      _MK_SHIFT_CONST(76):_MK_SHIFT_CONST(64)
+#define MSELECT2MC_AXI_R_RID_ROW                        0
+
+#define MSELECT2MC_AXI_R_RRESP_SHIFT                    _MK_SHIFT_CONST(77)
+#define MSELECT2MC_AXI_R_RRESP_FIELD                    (_MK_MASK_CONST(0x3) << MSELECT2MC_AXI_R_RRESP_SHIFT)
+#define MSELECT2MC_AXI_R_RRESP_RANGE                    _MK_SHIFT_CONST(78):_MK_SHIFT_CONST(77)
+#define MSELECT2MC_AXI_R_RRESP_ROW                      0
+#define MSELECT2MC_AXI_R_RRESP_OKAY                     _MK_ENUM_CONST(0)
+#define MSELECT2MC_AXI_R_RRESP_EXOKAY                   _MK_ENUM_CONST(1)
+#define MSELECT2MC_AXI_R_RRESP_SLVERR                   _MK_ENUM_CONST(2)
+#define MSELECT2MC_AXI_R_RRESP_DECERR                   _MK_ENUM_CONST(3)
+
+#define MSELECT2MC_AXI_R_RLAST_SHIFT                    _MK_SHIFT_CONST(79)
+#define MSELECT2MC_AXI_R_RLAST_FIELD                    (_MK_MASK_CONST(0x1) << MSELECT2MC_AXI_R_RLAST_SHIFT)
+#define MSELECT2MC_AXI_R_RLAST_RANGE                    _MK_SHIFT_CONST(79):_MK_SHIFT_CONST(79)
+#define MSELECT2MC_AXI_R_RLAST_ROW                      0
+#define MSELECT2MC_AXI_R_RLAST_DISABLED                 _MK_ENUM_CONST(0)
+#define MSELECT2MC_AXI_R_RLAST_ENABLED                  _MK_ENUM_CONST(1)
+
+
+// Packet AXI2MC_AXI_A
+#define AXI2MC_AXI_A_SIZE 63
+
+#define AXI2MC_AXI_A_AADDR_SHIFT                        _MK_SHIFT_CONST(0)
+#define AXI2MC_AXI_A_AADDR_FIELD                        (_MK_MASK_CONST(0xffffffff) << AXI2MC_AXI_A_AADDR_SHIFT)
+#define AXI2MC_AXI_A_AADDR_RANGE                        _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define AXI2MC_AXI_A_AADDR_ROW                  0
+
+#define AXI2MC_AXI_A_AID_SHIFT                  _MK_SHIFT_CONST(32)
+#define AXI2MC_AXI_A_AID_FIELD                  (_MK_MASK_CONST(0x1fff) << AXI2MC_AXI_A_AID_SHIFT)
+#define AXI2MC_AXI_A_AID_RANGE                  _MK_SHIFT_CONST(44):_MK_SHIFT_CONST(32)
+#define AXI2MC_AXI_A_AID_ROW                    0
+
+#define AXI2MC_AXI_A_ALEN_SHIFT                 _MK_SHIFT_CONST(45)
+#define AXI2MC_AXI_A_ALEN_FIELD                 (_MK_MASK_CONST(0xf) << AXI2MC_AXI_A_ALEN_SHIFT)
+#define AXI2MC_AXI_A_ALEN_RANGE                 _MK_SHIFT_CONST(48):_MK_SHIFT_CONST(45)
+#define AXI2MC_AXI_A_ALEN_ROW                   0
+#define AXI2MC_AXI_A_ALEN_ONEDATA                       _MK_ENUM_CONST(0)
+#define AXI2MC_AXI_A_ALEN_TWODATA                       _MK_ENUM_CONST(1)
+#define AXI2MC_AXI_A_ALEN_THREEDATA                     _MK_ENUM_CONST(2)
+#define AXI2MC_AXI_A_ALEN_FOURDATA                      _MK_ENUM_CONST(3)
+#define AXI2MC_AXI_A_ALEN_FIVEDATA                      _MK_ENUM_CONST(4)
+#define AXI2MC_AXI_A_ALEN_SIXDATA                       _MK_ENUM_CONST(5)
+#define AXI2MC_AXI_A_ALEN_SEVENDATA                     _MK_ENUM_CONST(6)
+#define AXI2MC_AXI_A_ALEN_EIGHTDATA                     _MK_ENUM_CONST(7)
+#define AXI2MC_AXI_A_ALEN_NINEDATA                      _MK_ENUM_CONST(8)
+#define AXI2MC_AXI_A_ALEN_TENDATA                       _MK_ENUM_CONST(9)
+#define AXI2MC_AXI_A_ALEN_ELEVENDATA                    _MK_ENUM_CONST(10)
+#define AXI2MC_AXI_A_ALEN_TWELVEDATA                    _MK_ENUM_CONST(11)
+#define AXI2MC_AXI_A_ALEN_THIRTEENDATA                  _MK_ENUM_CONST(12)
+#define AXI2MC_AXI_A_ALEN_FOURTEENDATA                  _MK_ENUM_CONST(13)
+#define AXI2MC_AXI_A_ALEN_FIFTHTEENDATA                 _MK_ENUM_CONST(14)
+#define AXI2MC_AXI_A_ALEN_SIXTEENDATA                   _MK_ENUM_CONST(15)
+
+#define AXI2MC_AXI_A_ASIZE_SHIFT                        _MK_SHIFT_CONST(49)
+#define AXI2MC_AXI_A_ASIZE_FIELD                        (_MK_MASK_CONST(0x7) << AXI2MC_AXI_A_ASIZE_SHIFT)
+#define AXI2MC_AXI_A_ASIZE_RANGE                        _MK_SHIFT_CONST(51):_MK_SHIFT_CONST(49)
+#define AXI2MC_AXI_A_ASIZE_ROW                  0
+#define AXI2MC_AXI_A_ASIZE_ONEBYTE                      _MK_ENUM_CONST(0)
+#define AXI2MC_AXI_A_ASIZE_TWOBYTES                     _MK_ENUM_CONST(1)
+#define AXI2MC_AXI_A_ASIZE_FOURBYTES                    _MK_ENUM_CONST(2)
+#define AXI2MC_AXI_A_ASIZE_EIGHTBYTES                   _MK_ENUM_CONST(3)
+#define AXI2MC_AXI_A_ASIZE_SIXTEENBYTES                 _MK_ENUM_CONST(4)
+#define AXI2MC_AXI_A_ASIZE_THIRTYTWOBYTES                       _MK_ENUM_CONST(5)
+#define AXI2MC_AXI_A_ASIZE_SIXTYFOURBYTES                       _MK_ENUM_CONST(6)
+#define AXI2MC_AXI_A_ASIZE_ONEHUNDREDTWENTYEIGHTBYTES                   _MK_ENUM_CONST(7)
+
+#define AXI2MC_AXI_A_ABURST_SHIFT                       _MK_SHIFT_CONST(52)
+#define AXI2MC_AXI_A_ABURST_FIELD                       (_MK_MASK_CONST(0x3) << AXI2MC_AXI_A_ABURST_SHIFT)
+#define AXI2MC_AXI_A_ABURST_RANGE                       _MK_SHIFT_CONST(53):_MK_SHIFT_CONST(52)
+#define AXI2MC_AXI_A_ABURST_ROW                 0
+#define AXI2MC_AXI_A_ABURST_FIXED                       _MK_ENUM_CONST(0)
+#define AXI2MC_AXI_A_ABURST_INCR                        _MK_ENUM_CONST(1)
+#define AXI2MC_AXI_A_ABURST_WRAP                        _MK_ENUM_CONST(2)
+#define AXI2MC_AXI_A_ABURST_RSVD                        _MK_ENUM_CONST(3)
+
+#define AXI2MC_AXI_A_ALOCK_SHIFT                        _MK_SHIFT_CONST(54)
+#define AXI2MC_AXI_A_ALOCK_FIELD                        (_MK_MASK_CONST(0x3) << AXI2MC_AXI_A_ALOCK_SHIFT)
+#define AXI2MC_AXI_A_ALOCK_RANGE                        _MK_SHIFT_CONST(55):_MK_SHIFT_CONST(54)
+#define AXI2MC_AXI_A_ALOCK_ROW                  0
+#define AXI2MC_AXI_A_ALOCK_NORMAL                       _MK_ENUM_CONST(0)
+#define AXI2MC_AXI_A_ALOCK_EXCLUSIVE                    _MK_ENUM_CONST(1)
+#define AXI2MC_AXI_A_ALOCK_LOCKED                       _MK_ENUM_CONST(2)
+#define AXI2MC_AXI_A_ALOCK_RSVD                 _MK_ENUM_CONST(3)
+
+#define AXI2MC_AXI_A_ACACHE_SHIFT                       _MK_SHIFT_CONST(56)
+#define AXI2MC_AXI_A_ACACHE_FIELD                       (_MK_MASK_CONST(0xf) << AXI2MC_AXI_A_ACACHE_SHIFT)
+#define AXI2MC_AXI_A_ACACHE_RANGE                       _MK_SHIFT_CONST(59):_MK_SHIFT_CONST(56)
+#define AXI2MC_AXI_A_ACACHE_ROW                 0
+#define AXI2MC_AXI_A_ACACHE_NONCACHEABLE_NONBUFFERABLE                  _MK_ENUM_CONST(0)
+#define AXI2MC_AXI_A_ACACHE_BUFFERABLE                  _MK_ENUM_CONST(1)
+#define AXI2MC_AXI_A_ACACHE_CACHEABLE_DONOTALLOCATE                     _MK_ENUM_CONST(2)
+#define AXI2MC_AXI_A_ACACHE_CACHEABLE_BUFFERABLE_DONOTALLOCATE                  _MK_ENUM_CONST(3)
+#define AXI2MC_AXI_A_ACACHE_CACHEABLEWRITETHROUGH_ALLOCATEONREAD                        _MK_ENUM_CONST(6)
+#define AXI2MC_AXI_A_ACACHE_CACHEABLEWRITEBACK_ALLOCATEONREAD                   _MK_ENUM_CONST(7)
+#define AXI2MC_AXI_A_ACACHE_CACHEABLEWRITETHROUGH_ALLOCATEONWRITE                       _MK_ENUM_CONST(10)
+#define AXI2MC_AXI_A_ACACHE_CACHEABLEWRITEBACK_ALLOCATEONWRITE                  _MK_ENUM_CONST(11)
+#define AXI2MC_AXI_A_ACACHE_CACHEABLEWRITETHROUGH_ALLOCATEONREADWRITE                   _MK_ENUM_CONST(14)
+#define AXI2MC_AXI_A_ACACHE_CACHEABLEWRITEBACK_ALLOCATEONREADWRITE                      _MK_ENUM_CONST(15)
+
+#define AXI2MC_AXI_A_APROT_SHIFT                        _MK_SHIFT_CONST(60)
+#define AXI2MC_AXI_A_APROT_FIELD                        (_MK_MASK_CONST(0x7) << AXI2MC_AXI_A_APROT_SHIFT)
+#define AXI2MC_AXI_A_APROT_RANGE                        _MK_SHIFT_CONST(62):_MK_SHIFT_CONST(60)
+#define AXI2MC_AXI_A_APROT_ROW                  0
+#define AXI2MC_AXI_A_APROT_DATA_SECURE_NORMAL                   _MK_ENUM_CONST(0)
+#define AXI2MC_AXI_A_APROT_DATA_SECURE_PRIVILEGED                       _MK_ENUM_CONST(1)
+#define AXI2MC_AXI_A_APROT_DATA_NONSECURE_NORMAL                        _MK_ENUM_CONST(2)
+#define AXI2MC_AXI_A_APROT_DATA_NONSECURE_PRIVILEGED                    _MK_ENUM_CONST(3)
+#define AXI2MC_AXI_A_APROT_INST_SECURE_NORMAL                   _MK_ENUM_CONST(4)
+#define AXI2MC_AXI_A_APROT_INST_SECURE_PRIVILEGED                       _MK_ENUM_CONST(5)
+#define AXI2MC_AXI_A_APROT_INST_NONSECURE_NORMAL                        _MK_ENUM_CONST(6)
+#define AXI2MC_AXI_A_APROT_INST_NONSECURE_PRIVILEGED                    _MK_ENUM_CONST(7)
+
+
+// Packet AXI2MC_AXI_W
+#define AXI2MC_AXI_W_SIZE 302
+
+#define AXI2MC_AXI_W_WDATA_SHIFT                        _MK_SHIFT_CONST(0)
+#define AXI2MC_AXI_W_WDATA_FIELD                        (_MK_MASK_CONST(0xffffffff) << AXI2MC_AXI_W_WDATA_SHIFT)
+#define AXI2MC_AXI_W_WDATA_RANGE                        _MK_SHIFT_CONST(255):_MK_SHIFT_CONST(0)
+#define AXI2MC_AXI_W_WDATA_ROW                  0
+
+#define AXI2MC_AXI_W_WID_SHIFT                  _MK_SHIFT_CONST(256)
+#define AXI2MC_AXI_W_WID_FIELD                  (_MK_MASK_CONST(0x1fff) << AXI2MC_AXI_W_WID_SHIFT)
+#define AXI2MC_AXI_W_WID_RANGE                  _MK_SHIFT_CONST(268):_MK_SHIFT_CONST(256)
+#define AXI2MC_AXI_W_WID_ROW                    0
+
+#define AXI2MC_AXI_W_WSTRB_SHIFT                        _MK_SHIFT_CONST(269)
+#define AXI2MC_AXI_W_WSTRB_FIELD                        (_MK_MASK_CONST(0xffffffff) << AXI2MC_AXI_W_WSTRB_SHIFT)
+#define AXI2MC_AXI_W_WSTRB_RANGE                        _MK_SHIFT_CONST(300):_MK_SHIFT_CONST(269)
+#define AXI2MC_AXI_W_WSTRB_ROW                  0
+
+#define AXI2MC_AXI_W_WLAST_SHIFT                        _MK_SHIFT_CONST(301)
+#define AXI2MC_AXI_W_WLAST_FIELD                        (_MK_MASK_CONST(0x1) << AXI2MC_AXI_W_WLAST_SHIFT)
+#define AXI2MC_AXI_W_WLAST_RANGE                        _MK_SHIFT_CONST(301):_MK_SHIFT_CONST(301)
+#define AXI2MC_AXI_W_WLAST_ROW                  0
+#define AXI2MC_AXI_W_WLAST_DISABLED                     _MK_ENUM_CONST(0)
+#define AXI2MC_AXI_W_WLAST_ENABLED                      _MK_ENUM_CONST(1)
+
+
+// Packet AXI2MC_AXI_B
+#define AXI2MC_AXI_B_SIZE 15
+
+#define AXI2MC_AXI_B_BID_SHIFT                  _MK_SHIFT_CONST(0)
+#define AXI2MC_AXI_B_BID_FIELD                  (_MK_MASK_CONST(0x1fff) << AXI2MC_AXI_B_BID_SHIFT)
+#define AXI2MC_AXI_B_BID_RANGE                  _MK_SHIFT_CONST(12):_MK_SHIFT_CONST(0)
+#define AXI2MC_AXI_B_BID_ROW                    0
+
+#define AXI2MC_AXI_B_BRESP_SHIFT                        _MK_SHIFT_CONST(13)
+#define AXI2MC_AXI_B_BRESP_FIELD                        (_MK_MASK_CONST(0x3) << AXI2MC_AXI_B_BRESP_SHIFT)
+#define AXI2MC_AXI_B_BRESP_RANGE                        _MK_SHIFT_CONST(14):_MK_SHIFT_CONST(13)
+#define AXI2MC_AXI_B_BRESP_ROW                  0
+#define AXI2MC_AXI_B_BRESP_OKAY                 _MK_ENUM_CONST(0)
+#define AXI2MC_AXI_B_BRESP_EXOKAY                       _MK_ENUM_CONST(1)
+#define AXI2MC_AXI_B_BRESP_SLVERR                       _MK_ENUM_CONST(2)
+#define AXI2MC_AXI_B_BRESP_DECERR                       _MK_ENUM_CONST(3)
+
+
+// Packet AXI2MC_AXI_R
+#define AXI2MC_AXI_R_SIZE 272
+
+#define AXI2MC_AXI_R_RDATA_SHIFT                        _MK_SHIFT_CONST(0)
+#define AXI2MC_AXI_R_RDATA_FIELD                        (_MK_MASK_CONST(0xffffffff) << AXI2MC_AXI_R_RDATA_SHIFT)
+#define AXI2MC_AXI_R_RDATA_RANGE                        _MK_SHIFT_CONST(255):_MK_SHIFT_CONST(0)
+#define AXI2MC_AXI_R_RDATA_ROW                  0
+
+#define AXI2MC_AXI_R_RID_SHIFT                  _MK_SHIFT_CONST(256)
+#define AXI2MC_AXI_R_RID_FIELD                  (_MK_MASK_CONST(0x1fff) << AXI2MC_AXI_R_RID_SHIFT)
+#define AXI2MC_AXI_R_RID_RANGE                  _MK_SHIFT_CONST(268):_MK_SHIFT_CONST(256)
+#define AXI2MC_AXI_R_RID_ROW                    0
+
+#define AXI2MC_AXI_R_RRESP_SHIFT                        _MK_SHIFT_CONST(269)
+#define AXI2MC_AXI_R_RRESP_FIELD                        (_MK_MASK_CONST(0x3) << AXI2MC_AXI_R_RRESP_SHIFT)
+#define AXI2MC_AXI_R_RRESP_RANGE                        _MK_SHIFT_CONST(270):_MK_SHIFT_CONST(269)
+#define AXI2MC_AXI_R_RRESP_ROW                  0
+#define AXI2MC_AXI_R_RRESP_OKAY                 _MK_ENUM_CONST(0)
+#define AXI2MC_AXI_R_RRESP_EXOKAY                       _MK_ENUM_CONST(1)
+#define AXI2MC_AXI_R_RRESP_SLVERR                       _MK_ENUM_CONST(2)
+#define AXI2MC_AXI_R_RRESP_DECERR                       _MK_ENUM_CONST(3)
+
+#define AXI2MC_AXI_R_RLAST_SHIFT                        _MK_SHIFT_CONST(271)
+#define AXI2MC_AXI_R_RLAST_FIELD                        (_MK_MASK_CONST(0x1) << AXI2MC_AXI_R_RLAST_SHIFT)
+#define AXI2MC_AXI_R_RLAST_RANGE                        _MK_SHIFT_CONST(271):_MK_SHIFT_CONST(271)
+#define AXI2MC_AXI_R_RLAST_ROW                  0
+#define AXI2MC_AXI_R_RLAST_DISABLED                     _MK_ENUM_CONST(0)
+#define AXI2MC_AXI_R_RLAST_ENABLED                      _MK_ENUM_CONST(1)
+
+
+// Packet MC_AXI_RWREQ
+#define MC_AXI_RWREQ_SIZE 112
+
+#define MC_AXI_RWREQ_AADDR_SHIFT                        _MK_SHIFT_CONST(0)
+#define MC_AXI_RWREQ_AADDR_FIELD                        (_MK_MASK_CONST(0xffffffff) << MC_AXI_RWREQ_AADDR_SHIFT)
+#define MC_AXI_RWREQ_AADDR_RANGE                        _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define MC_AXI_RWREQ_AADDR_ROW                  0
+
+#define MC_AXI_RWREQ_AID_SHIFT                  _MK_SHIFT_CONST(32)
+#define MC_AXI_RWREQ_AID_FIELD                  (_MK_MASK_CONST(0x1fff) << MC_AXI_RWREQ_AID_SHIFT)
+#define MC_AXI_RWREQ_AID_RANGE                  _MK_SHIFT_CONST(44):_MK_SHIFT_CONST(32)
+#define MC_AXI_RWREQ_AID_ROW                    0
+
+#define MC_AXI_RWREQ_ALEN_SHIFT                 _MK_SHIFT_CONST(45)
+#define MC_AXI_RWREQ_ALEN_FIELD                 (_MK_MASK_CONST(0xf) << MC_AXI_RWREQ_ALEN_SHIFT)
+#define MC_AXI_RWREQ_ALEN_RANGE                 _MK_SHIFT_CONST(48):_MK_SHIFT_CONST(45)
+#define MC_AXI_RWREQ_ALEN_ROW                   0
+
+#define MC_AXI_RWREQ_ASIZE_SHIFT                        _MK_SHIFT_CONST(49)
+#define MC_AXI_RWREQ_ASIZE_FIELD                        (_MK_MASK_CONST(0x7) << MC_AXI_RWREQ_ASIZE_SHIFT)
+#define MC_AXI_RWREQ_ASIZE_RANGE                        _MK_SHIFT_CONST(51):_MK_SHIFT_CONST(49)
+#define MC_AXI_RWREQ_ASIZE_ROW                  2
+
+#define MC_AXI_RWREQ_ABURST_SHIFT                       _MK_SHIFT_CONST(52)
+#define MC_AXI_RWREQ_ABURST_FIELD                       (_MK_MASK_CONST(0x3) << MC_AXI_RWREQ_ABURST_SHIFT)
+#define MC_AXI_RWREQ_ABURST_RANGE                       _MK_SHIFT_CONST(53):_MK_SHIFT_CONST(52)
+#define MC_AXI_RWREQ_ABURST_ROW                 0
+#define MC_AXI_RWREQ_ABURST_FIXED                       _MK_ENUM_CONST(0)
+#define MC_AXI_RWREQ_ABURST_INCR                        _MK_ENUM_CONST(1)
+#define MC_AXI_RWREQ_ABURST_WRAP                        _MK_ENUM_CONST(2)
+#define MC_AXI_RWREQ_ABURST_RSVD                        _MK_ENUM_CONST(3)
+
+#define MC_AXI_RWREQ_ALOCK_SHIFT                        _MK_SHIFT_CONST(54)
+#define MC_AXI_RWREQ_ALOCK_FIELD                        (_MK_MASK_CONST(0x3) << MC_AXI_RWREQ_ALOCK_SHIFT)
+#define MC_AXI_RWREQ_ALOCK_RANGE                        _MK_SHIFT_CONST(55):_MK_SHIFT_CONST(54)
+#define MC_AXI_RWREQ_ALOCK_ROW                  0
+
+#define MC_AXI_RWREQ_ACACHE_SHIFT                       _MK_SHIFT_CONST(56)
+#define MC_AXI_RWREQ_ACACHE_FIELD                       (_MK_MASK_CONST(0xf) << MC_AXI_RWREQ_ACACHE_SHIFT)
+#define MC_AXI_RWREQ_ACACHE_RANGE                       _MK_SHIFT_CONST(59):_MK_SHIFT_CONST(56)
+#define MC_AXI_RWREQ_ACACHE_ROW                 0
+
+#define MC_AXI_RWREQ_APROT_SHIFT                        _MK_SHIFT_CONST(60)
+#define MC_AXI_RWREQ_APROT_FIELD                        (_MK_MASK_CONST(0x7) << MC_AXI_RWREQ_APROT_SHIFT)
+#define MC_AXI_RWREQ_APROT_RANGE                        _MK_SHIFT_CONST(62):_MK_SHIFT_CONST(60)
+#define MC_AXI_RWREQ_APROT_ROW                  0
+
+#define MC_AXI_RWREQ_ASB_SHIFT                  _MK_SHIFT_CONST(63)
+#define MC_AXI_RWREQ_ASB_FIELD                  (_MK_MASK_CONST(0x3) << MC_AXI_RWREQ_ASB_SHIFT)
+#define MC_AXI_RWREQ_ASB_RANGE                  _MK_SHIFT_CONST(64):_MK_SHIFT_CONST(63)
+#define MC_AXI_RWREQ_ASB_ROW                    0
+
+#define MC_AXI_RWREQ_ARW_SHIFT                  _MK_SHIFT_CONST(65)
+#define MC_AXI_RWREQ_ARW_FIELD                  (_MK_MASK_CONST(0x1) << MC_AXI_RWREQ_ARW_SHIFT)
+#define MC_AXI_RWREQ_ARW_RANGE                  _MK_SHIFT_CONST(65):_MK_SHIFT_CONST(65)
+#define MC_AXI_RWREQ_ARW_ROW                    0
+
+#define MC_AXI_RWREQ_ACT_AADDR_SHIFT                    _MK_SHIFT_CONST(66)
+#define MC_AXI_RWREQ_ACT_AADDR_FIELD                    (_MK_MASK_CONST(0xffffffff) << MC_AXI_RWREQ_ACT_AADDR_SHIFT)
+#define MC_AXI_RWREQ_ACT_AADDR_RANGE                    _MK_SHIFT_CONST(97):_MK_SHIFT_CONST(66)
+#define MC_AXI_RWREQ_ACT_AADDR_ROW                      0
+
+#define MC_AXI_RWREQ_ACT_ALEN_SHIFT                     _MK_SHIFT_CONST(98)
+#define MC_AXI_RWREQ_ACT_ALEN_FIELD                     (_MK_MASK_CONST(0xf) << MC_AXI_RWREQ_ACT_ALEN_SHIFT)
+#define MC_AXI_RWREQ_ACT_ALEN_RANGE                     _MK_SHIFT_CONST(101):_MK_SHIFT_CONST(98)
+#define MC_AXI_RWREQ_ACT_ALEN_ROW                       0
+
+#define MC_AXI_RWREQ_ACT_ASIZE_SHIFT                    _MK_SHIFT_CONST(102)
+#define MC_AXI_RWREQ_ACT_ASIZE_FIELD                    (_MK_MASK_CONST(0x7) << MC_AXI_RWREQ_ACT_ASIZE_SHIFT)
+#define MC_AXI_RWREQ_ACT_ASIZE_RANGE                    _MK_SHIFT_CONST(104):_MK_SHIFT_CONST(102)
+#define MC_AXI_RWREQ_ACT_ASIZE_ROW                      0
+
+#define MC_AXI_RWREQ_DOUBLEREQ_SHIFT                    _MK_SHIFT_CONST(105)
+#define MC_AXI_RWREQ_DOUBLEREQ_FIELD                    (_MK_MASK_CONST(0x1) << MC_AXI_RWREQ_DOUBLEREQ_SHIFT)
+#define MC_AXI_RWREQ_DOUBLEREQ_RANGE                    _MK_SHIFT_CONST(105):_MK_SHIFT_CONST(105)
+#define MC_AXI_RWREQ_DOUBLEREQ_ROW                      0
+
+#define MC_AXI_RWREQ_ILLEGALACC_SHIFT                   _MK_SHIFT_CONST(106)
+#define MC_AXI_RWREQ_ILLEGALACC_FIELD                   (_MK_MASK_CONST(0x1) << MC_AXI_RWREQ_ILLEGALACC_SHIFT)
+#define MC_AXI_RWREQ_ILLEGALACC_RANGE                   _MK_SHIFT_CONST(106):_MK_SHIFT_CONST(106)
+#define MC_AXI_RWREQ_ILLEGALACC_ROW                     0
+
+#define MC_AXI_RWREQ_TAG_SHIFT                  _MK_SHIFT_CONST(107)
+#define MC_AXI_RWREQ_TAG_FIELD                  (_MK_MASK_CONST(0x1f) << MC_AXI_RWREQ_TAG_SHIFT)
+#define MC_AXI_RWREQ_TAG_RANGE                  _MK_SHIFT_CONST(111):_MK_SHIFT_CONST(107)
+#define MC_AXI_RWREQ_TAG_ROW                    0
+
+
+// Packet CSR_C2MC_RESET
+#define CSR_C2MC_RESET_SIZE 1
+
+#define CSR_C2MC_RESET_RSTN_SHIFT                       _MK_SHIFT_CONST(0)
+#define CSR_C2MC_RESET_RSTN_FIELD                       (_MK_MASK_CONST(0x1) << CSR_C2MC_RESET_RSTN_SHIFT)
+#define CSR_C2MC_RESET_RSTN_RANGE                       _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CSR_C2MC_RESET_RSTN_ROW                 0
+
+
+// Packet CSR_C2MC_REQ
+#define CSR_C2MC_REQ_SIZE 32
+
+#define CSR_C2MC_REQ_ADR_SHIFT                  _MK_SHIFT_CONST(0)
+#define CSR_C2MC_REQ_ADR_FIELD                  (_MK_MASK_CONST(0xffffffff) << CSR_C2MC_REQ_ADR_SHIFT)
+#define CSR_C2MC_REQ_ADR_RANGE                  _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CSR_C2MC_REQ_ADR_ROW                    0
+
+
+// Packet CSR_C2MC_SIZE
+#define CSR_C2MC_SIZE_SIZE 1
+
+#define CSR_C2MC_SIZE_SIZE_SHIFT                        _MK_SHIFT_CONST(0)
+#define CSR_C2MC_SIZE_SIZE_FIELD                        (_MK_MASK_CONST(0x1) << CSR_C2MC_SIZE_SIZE_SHIFT)
+#define CSR_C2MC_SIZE_SIZE_RANGE                        _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CSR_C2MC_SIZE_SIZE_ROW                  0
+
+
+// Packet CSR_C2MC_SECURE
+#define CSR_C2MC_SECURE_SIZE 1
+
+#define CSR_C2MC_SECURE_SECURE_SHIFT                    _MK_SHIFT_CONST(0)
+#define CSR_C2MC_SECURE_SECURE_FIELD                    (_MK_MASK_CONST(0x1) << CSR_C2MC_SECURE_SECURE_SHIFT)
+#define CSR_C2MC_SECURE_SECURE_RANGE                    _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CSR_C2MC_SECURE_SECURE_ROW                      0
+
+
+// Packet CSR_C2MC_TAG
+#define CSR_C2MC_TAG_SIZE 5
+
+#define CSR_C2MC_TAG_TAG_SHIFT                  _MK_SHIFT_CONST(0)
+#define CSR_C2MC_TAG_TAG_FIELD                  (_MK_MASK_CONST(0x1f) << CSR_C2MC_TAG_TAG_SHIFT)
+#define CSR_C2MC_TAG_TAG_RANGE                  _MK_SHIFT_CONST(4):_MK_SHIFT_CONST(0)
+#define CSR_C2MC_TAG_TAG_ROW                    0
+
+
+// Packet CSR_C2MC_BP_REQ
+#define CSR_C2MC_BP_REQ_SIZE 48
+
+#define CSR_C2MC_BP_REQ_BASEADR_SHIFT                   _MK_SHIFT_CONST(0)
+#define CSR_C2MC_BP_REQ_BASEADR_FIELD                   (_MK_MASK_CONST(0xffffffff) << CSR_C2MC_BP_REQ_BASEADR_SHIFT)
+#define CSR_C2MC_BP_REQ_BASEADR_RANGE                   _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CSR_C2MC_BP_REQ_BASEADR_ROW                     0
+
+#define CSR_C2MC_BP_REQ_PITCH_SHIFT                     _MK_SHIFT_CONST(32)
+#define CSR_C2MC_BP_REQ_PITCH_FIELD                     (_MK_MASK_CONST(0xffff) << CSR_C2MC_BP_REQ_PITCH_SHIFT)
+#define CSR_C2MC_BP_REQ_PITCH_RANGE                     _MK_SHIFT_CONST(47):_MK_SHIFT_CONST(32)
+#define CSR_C2MC_BP_REQ_PITCH_ROW                       0
+
+
+// Packet CSR_C2MC_ADRXY
+#define CSR_C2MC_ADRXY_SIZE 30
+
+#define CSR_C2MC_ADRXY_OFFX_SHIFT                       _MK_SHIFT_CONST(0)
+#define CSR_C2MC_ADRXY_OFFX_FIELD                       (_MK_MASK_CONST(0xffff) << CSR_C2MC_ADRXY_OFFX_SHIFT)
+#define CSR_C2MC_ADRXY_OFFX_RANGE                       _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(0)
+#define CSR_C2MC_ADRXY_OFFX_ROW                 0
+
+#define CSR_C2MC_ADRXY_OFFY_SHIFT                       _MK_SHIFT_CONST(16)
+#define CSR_C2MC_ADRXY_OFFY_FIELD                       (_MK_MASK_CONST(0x3fff) << CSR_C2MC_ADRXY_OFFY_SHIFT)
+#define CSR_C2MC_ADRXY_OFFY_RANGE                       _MK_SHIFT_CONST(29):_MK_SHIFT_CONST(16)
+#define CSR_C2MC_ADRXY_OFFY_ROW                 0
+
+
+// Packet CSR_C2MC_TILE
+#define CSR_C2MC_TILE_SIZE 33
+
+#define CSR_C2MC_TILE_LINADR_SHIFT                      _MK_SHIFT_CONST(0)
+#define CSR_C2MC_TILE_LINADR_FIELD                      (_MK_MASK_CONST(0xffffffff) << CSR_C2MC_TILE_LINADR_SHIFT)
+#define CSR_C2MC_TILE_LINADR_RANGE                      _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CSR_C2MC_TILE_LINADR_ROW                        0
+
+#define CSR_C2MC_TILE_TMODE_SHIFT                       _MK_SHIFT_CONST(32)
+#define CSR_C2MC_TILE_TMODE_FIELD                       (_MK_MASK_CONST(0x1) << CSR_C2MC_TILE_TMODE_SHIFT)
+#define CSR_C2MC_TILE_TMODE_RANGE                       _MK_SHIFT_CONST(32):_MK_SHIFT_CONST(32)
+#define CSR_C2MC_TILE_TMODE_ROW                 0
+#define CSR_C2MC_TILE_TMODE_LINEAR                      _MK_ENUM_CONST(0)
+#define CSR_C2MC_TILE_TMODE_TILED                       _MK_ENUM_CONST(1)
+
+
+// Packet CSR_C2MC_RDI
+#define CSR_C2MC_RDI_SIZE 256
+
+#define CSR_C2MC_RDI_RDI_SHIFT                  _MK_SHIFT_CONST(0)
+#define CSR_C2MC_RDI_RDI_FIELD                  (_MK_MASK_CONST(0xffffffff) << CSR_C2MC_RDI_RDI_SHIFT)
+#define CSR_C2MC_RDI_RDI_RANGE                  _MK_SHIFT_CONST(255):_MK_SHIFT_CONST(0)
+#define CSR_C2MC_RDI_RDI_ROW                    0
+
+
+// Packet CSR_C2MC_HP
+#define CSR_C2MC_HP_SIZE 38
+
+// high-priority threshold
+#define CSR_C2MC_HP_HPTH_SHIFT                  _MK_SHIFT_CONST(0)
+#define CSR_C2MC_HP_HPTH_FIELD                  (_MK_MASK_CONST(0xffffffff) << CSR_C2MC_HP_HPTH_SHIFT)
+#define CSR_C2MC_HP_HPTH_RANGE                  _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CSR_C2MC_HP_HPTH_ROW                    0
+
+// high-priority timer
+#define CSR_C2MC_HP_HPTM_SHIFT                  _MK_SHIFT_CONST(32)
+#define CSR_C2MC_HP_HPTM_FIELD                  (_MK_MASK_CONST(0x3f) << CSR_C2MC_HP_HPTM_SHIFT)
+#define CSR_C2MC_HP_HPTM_RANGE                  _MK_SHIFT_CONST(37):_MK_SHIFT_CONST(32)
+#define CSR_C2MC_HP_HPTM_ROW                    0
+
+
+// Packet CSR_C2MC_HYST
+#define CSR_C2MC_HYST_SIZE 32
+
+#define CSR_C2MC_HYST_HYST_REQ_TM_SHIFT                 _MK_SHIFT_CONST(0)
+#define CSR_C2MC_HYST_HYST_REQ_TM_FIELD                 (_MK_MASK_CONST(0xff) << CSR_C2MC_HYST_HYST_REQ_TM_SHIFT)
+#define CSR_C2MC_HYST_HYST_REQ_TM_RANGE                 _MK_SHIFT_CONST(7):_MK_SHIFT_CONST(0)
+#define CSR_C2MC_HYST_HYST_REQ_TM_ROW                   0
+
+#define CSR_C2MC_HYST_DHYST_TM_SHIFT                    _MK_SHIFT_CONST(8)
+#define CSR_C2MC_HYST_DHYST_TM_FIELD                    (_MK_MASK_CONST(0xff) << CSR_C2MC_HYST_DHYST_TM_SHIFT)
+#define CSR_C2MC_HYST_DHYST_TM_RANGE                    _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(8)
+#define CSR_C2MC_HYST_DHYST_TM_ROW                      0
+
+#define CSR_C2MC_HYST_DHYST_TH_SHIFT                    _MK_SHIFT_CONST(16)
+#define CSR_C2MC_HYST_DHYST_TH_FIELD                    (_MK_MASK_CONST(0xff) << CSR_C2MC_HYST_DHYST_TH_SHIFT)
+#define CSR_C2MC_HYST_DHYST_TH_RANGE                    _MK_SHIFT_CONST(23):_MK_SHIFT_CONST(16)
+#define CSR_C2MC_HYST_DHYST_TH_ROW                      0
+
+#define CSR_C2MC_HYST_HYST_TM_SHIFT                     _MK_SHIFT_CONST(24)
+#define CSR_C2MC_HYST_HYST_TM_FIELD                     (_MK_MASK_CONST(0xf) << CSR_C2MC_HYST_HYST_TM_SHIFT)
+#define CSR_C2MC_HYST_HYST_TM_RANGE                     _MK_SHIFT_CONST(27):_MK_SHIFT_CONST(24)
+#define CSR_C2MC_HYST_HYST_TM_ROW                       0
+
+#define CSR_C2MC_HYST_HYST_REQ_TH_SHIFT                 _MK_SHIFT_CONST(28)
+#define CSR_C2MC_HYST_HYST_REQ_TH_FIELD                 (_MK_MASK_CONST(0x7) << CSR_C2MC_HYST_HYST_REQ_TH_SHIFT)
+#define CSR_C2MC_HYST_HYST_REQ_TH_RANGE                 _MK_SHIFT_CONST(30):_MK_SHIFT_CONST(28)
+#define CSR_C2MC_HYST_HYST_REQ_TH_ROW                   0
+
+#define CSR_C2MC_HYST_HYST_EN_SHIFT                     _MK_SHIFT_CONST(31)
+#define CSR_C2MC_HYST_HYST_EN_FIELD                     (_MK_MASK_CONST(0x1) << CSR_C2MC_HYST_HYST_EN_SHIFT)
+#define CSR_C2MC_HYST_HYST_EN_RANGE                     _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(31)
+#define CSR_C2MC_HYST_HYST_EN_ROW                       0
+
+
+// Packet CSW_C2MC_RESET
+#define CSW_C2MC_RESET_SIZE 1
+
+#define CSW_C2MC_RESET_RSTN_SHIFT                       _MK_SHIFT_CONST(0)
+#define CSW_C2MC_RESET_RSTN_FIELD                       (_MK_MASK_CONST(0x1) << CSW_C2MC_RESET_RSTN_SHIFT)
+#define CSW_C2MC_RESET_RSTN_RANGE                       _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CSW_C2MC_RESET_RSTN_ROW                 0
+
+
+// Packet CSW_C2MC_REQ
+#define CSW_C2MC_REQ_SIZE 321
+
+#define CSW_C2MC_REQ_ADR_SHIFT                  _MK_SHIFT_CONST(0)
+#define CSW_C2MC_REQ_ADR_FIELD                  (_MK_MASK_CONST(0xffffffff) << CSW_C2MC_REQ_ADR_SHIFT)
+#define CSW_C2MC_REQ_ADR_RANGE                  _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CSW_C2MC_REQ_ADR_ROW                    0
+
+#define CSW_C2MC_REQ_BE_SHIFT                   _MK_SHIFT_CONST(32)
+#define CSW_C2MC_REQ_BE_FIELD                   (_MK_MASK_CONST(0xffffffff) << CSW_C2MC_REQ_BE_SHIFT)
+#define CSW_C2MC_REQ_BE_RANGE                   _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(32)
+#define CSW_C2MC_REQ_BE_ROW                     0
+
+#define CSW_C2MC_REQ_WDO_SHIFT                  _MK_SHIFT_CONST(64)
+#define CSW_C2MC_REQ_WDO_FIELD                  (_MK_MASK_CONST(0xffffffff) << CSW_C2MC_REQ_WDO_SHIFT)
+#define CSW_C2MC_REQ_WDO_RANGE                  _MK_SHIFT_CONST(319):_MK_SHIFT_CONST(64)
+#define CSW_C2MC_REQ_WDO_ROW                    0
+
+#define CSW_C2MC_REQ_TAG_SHIFT                  _MK_SHIFT_CONST(320)
+#define CSW_C2MC_REQ_TAG_FIELD                  (_MK_MASK_CONST(0x1) << CSW_C2MC_REQ_TAG_SHIFT)
+#define CSW_C2MC_REQ_TAG_RANGE                  _MK_SHIFT_CONST(320):_MK_SHIFT_CONST(320)
+#define CSW_C2MC_REQ_TAG_ROW                    0
+
+
+// Packet CSW_C2MC_SECURE
+#define CSW_C2MC_SECURE_SIZE 1
+
+#define CSW_C2MC_SECURE_SECURE_SHIFT                    _MK_SHIFT_CONST(0)
+#define CSW_C2MC_SECURE_SECURE_FIELD                    (_MK_MASK_CONST(0x1) << CSW_C2MC_SECURE_SECURE_SHIFT)
+#define CSW_C2MC_SECURE_SECURE_RANGE                    _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CSW_C2MC_SECURE_SECURE_ROW                      0
+
+
+// Packet CSW_C2MC_BP_REQ
+#define CSW_C2MC_BP_REQ_SIZE 337
+
+#define CSW_C2MC_BP_REQ_BASEADR_SHIFT                   _MK_SHIFT_CONST(0)
+#define CSW_C2MC_BP_REQ_BASEADR_FIELD                   (_MK_MASK_CONST(0xffffffff) << CSW_C2MC_BP_REQ_BASEADR_SHIFT)
+#define CSW_C2MC_BP_REQ_BASEADR_RANGE                   _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CSW_C2MC_BP_REQ_BASEADR_ROW                     0
+
+#define CSW_C2MC_BP_REQ_PITCH_SHIFT                     _MK_SHIFT_CONST(32)
+#define CSW_C2MC_BP_REQ_PITCH_FIELD                     (_MK_MASK_CONST(0xffff) << CSW_C2MC_BP_REQ_PITCH_SHIFT)
+#define CSW_C2MC_BP_REQ_PITCH_RANGE                     _MK_SHIFT_CONST(47):_MK_SHIFT_CONST(32)
+#define CSW_C2MC_BP_REQ_PITCH_ROW                       0
+
+#define CSW_C2MC_BP_REQ_BE_SHIFT                        _MK_SHIFT_CONST(48)
+#define CSW_C2MC_BP_REQ_BE_FIELD                        (_MK_MASK_CONST(0xffffffff) << CSW_C2MC_BP_REQ_BE_SHIFT)
+#define CSW_C2MC_BP_REQ_BE_RANGE                        _MK_SHIFT_CONST(79):_MK_SHIFT_CONST(48)
+#define CSW_C2MC_BP_REQ_BE_ROW                  0
+
+#define CSW_C2MC_BP_REQ_WDO_SHIFT                       _MK_SHIFT_CONST(80)
+#define CSW_C2MC_BP_REQ_WDO_FIELD                       (_MK_MASK_CONST(0xffffffff) << CSW_C2MC_BP_REQ_WDO_SHIFT)
+#define CSW_C2MC_BP_REQ_WDO_RANGE                       _MK_SHIFT_CONST(335):_MK_SHIFT_CONST(80)
+#define CSW_C2MC_BP_REQ_WDO_ROW                 0
+
+#define CSW_C2MC_BP_REQ_TAG_SHIFT                       _MK_SHIFT_CONST(336)
+#define CSW_C2MC_BP_REQ_TAG_FIELD                       (_MK_MASK_CONST(0x1) << CSW_C2MC_BP_REQ_TAG_SHIFT)
+#define CSW_C2MC_BP_REQ_TAG_RANGE                       _MK_SHIFT_CONST(336):_MK_SHIFT_CONST(336)
+#define CSW_C2MC_BP_REQ_TAG_ROW                 0
+
+
+// Packet CSW_C2MC_ADRXY
+#define CSW_C2MC_ADRXY_SIZE 30
+
+#define CSW_C2MC_ADRXY_OFFX_SHIFT                       _MK_SHIFT_CONST(0)
+#define CSW_C2MC_ADRXY_OFFX_FIELD                       (_MK_MASK_CONST(0xffff) << CSW_C2MC_ADRXY_OFFX_SHIFT)
+#define CSW_C2MC_ADRXY_OFFX_RANGE                       _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(0)
+#define CSW_C2MC_ADRXY_OFFX_ROW                 0
+
+#define CSW_C2MC_ADRXY_OFFY_SHIFT                       _MK_SHIFT_CONST(16)
+#define CSW_C2MC_ADRXY_OFFY_FIELD                       (_MK_MASK_CONST(0x3fff) << CSW_C2MC_ADRXY_OFFY_SHIFT)
+#define CSW_C2MC_ADRXY_OFFY_RANGE                       _MK_SHIFT_CONST(29):_MK_SHIFT_CONST(16)
+#define CSW_C2MC_ADRXY_OFFY_ROW                 0
+
+
+// Packet CSW_C2MC_TILE
+#define CSW_C2MC_TILE_SIZE 33
+
+#define CSW_C2MC_TILE_LINADR_SHIFT                      _MK_SHIFT_CONST(0)
+#define CSW_C2MC_TILE_LINADR_FIELD                      (_MK_MASK_CONST(0xffffffff) << CSW_C2MC_TILE_LINADR_SHIFT)
+#define CSW_C2MC_TILE_LINADR_RANGE                      _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CSW_C2MC_TILE_LINADR_ROW                        0
+
+#define CSW_C2MC_TILE_TMODE_SHIFT                       _MK_SHIFT_CONST(32)
+#define CSW_C2MC_TILE_TMODE_FIELD                       (_MK_MASK_CONST(0x1) << CSW_C2MC_TILE_TMODE_SHIFT)
+#define CSW_C2MC_TILE_TMODE_RANGE                       _MK_SHIFT_CONST(32):_MK_SHIFT_CONST(32)
+#define CSW_C2MC_TILE_TMODE_ROW                 0
+#define CSW_C2MC_TILE_TMODE_LINEAR                      _MK_ENUM_CONST(0)
+#define CSW_C2MC_TILE_TMODE_TILED                       _MK_ENUM_CONST(1)
+
+
+// Packet CSW_C2MC_XDI
+#define CSW_C2MC_XDI_SIZE 32
+
+// sometimes fake data
+#define CSW_C2MC_XDI_XDI_SHIFT                  _MK_SHIFT_CONST(0)
+#define CSW_C2MC_XDI_XDI_FIELD                  (_MK_MASK_CONST(0xffffffff) << CSW_C2MC_XDI_XDI_SHIFT)
+#define CSW_C2MC_XDI_XDI_RANGE                  _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CSW_C2MC_XDI_XDI_ROW                    0
+
+
+// Packet CSW_C2MC_HP
+#define CSW_C2MC_HP_SIZE 32
+
+// high-priority threshold
+#define CSW_C2MC_HP_HPTH_SHIFT                  _MK_SHIFT_CONST(0)
+#define CSW_C2MC_HP_HPTH_FIELD                  (_MK_MASK_CONST(0xffffffff) << CSW_C2MC_HP_HPTH_SHIFT)
+#define CSW_C2MC_HP_HPTH_RANGE                  _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CSW_C2MC_HP_HPTH_ROW                    0
+
+
+// Packet CSW_C2MC_WCOAL
+#define CSW_C2MC_WCOAL_SIZE 32
+
+// write-coalescing time-out
+#define CSW_C2MC_WCOAL_WCOALTM_SHIFT                    _MK_SHIFT_CONST(0)
+#define CSW_C2MC_WCOAL_WCOALTM_FIELD                    (_MK_MASK_CONST(0xffffffff) << CSW_C2MC_WCOAL_WCOALTM_SHIFT)
+#define CSW_C2MC_WCOAL_WCOALTM_RANGE                    _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CSW_C2MC_WCOAL_WCOALTM_ROW                      0
+
+
+// Packet CSW_C2MC_HYST
+#define CSW_C2MC_HYST_SIZE 32
+
+// hysteresis control register
+#define CSW_C2MC_HYST_HYST_SHIFT                        _MK_SHIFT_CONST(0)
+#define CSW_C2MC_HYST_HYST_FIELD                        (_MK_MASK_CONST(0xffffffff) << CSW_C2MC_HYST_HYST_SHIFT)
+#define CSW_C2MC_HYST_HYST_RANGE                        _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CSW_C2MC_HYST_HYST_ROW                  0
+
+
+// Packet CBR_C2MC_RESET
+#define CBR_C2MC_RESET_SIZE 1
+
+#define CBR_C2MC_RESET_RSTN_SHIFT                       _MK_SHIFT_CONST(0)
+#define CBR_C2MC_RESET_RSTN_FIELD                       (_MK_MASK_CONST(0x1) << CBR_C2MC_RESET_RSTN_SHIFT)
+#define CBR_C2MC_RESET_RSTN_RANGE                       _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CBR_C2MC_RESET_RSTN_ROW                 0
+
+
+// Packet CBR_C2MC_REQP
+#define CBR_C2MC_REQP_SIZE 263
+
+#define CBR_C2MC_REQP_ADR_SHIFT                 _MK_SHIFT_CONST(0)
+#define CBR_C2MC_REQP_ADR_FIELD                 (_MK_MASK_CONST(0xffffffff) << CBR_C2MC_REQP_ADR_SHIFT)
+#define CBR_C2MC_REQP_ADR_RANGE                 _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CBR_C2MC_REQP_ADR_ROW                   0
+
+#define CBR_C2MC_REQP_ADRU_SHIFT                        _MK_SHIFT_CONST(32)
+#define CBR_C2MC_REQP_ADRU_FIELD                        (_MK_MASK_CONST(0xffffffff) << CBR_C2MC_REQP_ADRU_SHIFT)
+#define CBR_C2MC_REQP_ADRU_RANGE                        _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(32)
+#define CBR_C2MC_REQP_ADRU_ROW                  0
+
+#define CBR_C2MC_REQP_ADRV_SHIFT                        _MK_SHIFT_CONST(64)
+#define CBR_C2MC_REQP_ADRV_FIELD                        (_MK_MASK_CONST(0xffffffff) << CBR_C2MC_REQP_ADRV_SHIFT)
+#define CBR_C2MC_REQP_ADRV_RANGE                        _MK_SHIFT_CONST(95):_MK_SHIFT_CONST(64)
+#define CBR_C2MC_REQP_ADRV_ROW                  0
+
+#define CBR_C2MC_REQP_LS_SHIFT                  _MK_SHIFT_CONST(96)
+#define CBR_C2MC_REQP_LS_FIELD                  (_MK_MASK_CONST(0xffffffff) << CBR_C2MC_REQP_LS_SHIFT)
+#define CBR_C2MC_REQP_LS_RANGE                  _MK_SHIFT_CONST(127):_MK_SHIFT_CONST(96)
+#define CBR_C2MC_REQP_LS_ROW                    0
+
+#define CBR_C2MC_REQP_LSUV_SHIFT                        _MK_SHIFT_CONST(128)
+#define CBR_C2MC_REQP_LSUV_FIELD                        (_MK_MASK_CONST(0xffffffff) << CBR_C2MC_REQP_LSUV_SHIFT)
+#define CBR_C2MC_REQP_LSUV_RANGE                        _MK_SHIFT_CONST(159):_MK_SHIFT_CONST(128)
+#define CBR_C2MC_REQP_LSUV_ROW                  0
+
+#define CBR_C2MC_REQP_HS_SHIFT                  _MK_SHIFT_CONST(160)
+#define CBR_C2MC_REQP_HS_FIELD                  (_MK_MASK_CONST(0xffffffff) << CBR_C2MC_REQP_HS_SHIFT)
+#define CBR_C2MC_REQP_HS_RANGE                  _MK_SHIFT_CONST(191):_MK_SHIFT_CONST(160)
+#define CBR_C2MC_REQP_HS_ROW                    0
+
+#define CBR_C2MC_REQP_VS_SHIFT                  _MK_SHIFT_CONST(192)
+#define CBR_C2MC_REQP_VS_FIELD                  (_MK_MASK_CONST(0xffffffff) << CBR_C2MC_REQP_VS_SHIFT)
+#define CBR_C2MC_REQP_VS_RANGE                  _MK_SHIFT_CONST(223):_MK_SHIFT_CONST(192)
+#define CBR_C2MC_REQP_VS_ROW                    0
+
+#define CBR_C2MC_REQP_DL_SHIFT                  _MK_SHIFT_CONST(224)
+#define CBR_C2MC_REQP_DL_FIELD                  (_MK_MASK_CONST(0xffffffff) << CBR_C2MC_REQP_DL_SHIFT)
+#define CBR_C2MC_REQP_DL_RANGE                  _MK_SHIFT_CONST(255):_MK_SHIFT_CONST(224)
+#define CBR_C2MC_REQP_DL_ROW                    0
+
+#define CBR_C2MC_REQP_HD_SHIFT                  _MK_SHIFT_CONST(256)
+#define CBR_C2MC_REQP_HD_FIELD                  (_MK_MASK_CONST(0x1) << CBR_C2MC_REQP_HD_SHIFT)
+#define CBR_C2MC_REQP_HD_RANGE                  _MK_SHIFT_CONST(256):_MK_SHIFT_CONST(256)
+#define CBR_C2MC_REQP_HD_ROW                    0
+
+#define CBR_C2MC_REQP_VD_SHIFT                  _MK_SHIFT_CONST(257)
+#define CBR_C2MC_REQP_VD_FIELD                  (_MK_MASK_CONST(0x1) << CBR_C2MC_REQP_VD_SHIFT)
+#define CBR_C2MC_REQP_VD_RANGE                  _MK_SHIFT_CONST(257):_MK_SHIFT_CONST(257)
+#define CBR_C2MC_REQP_VD_ROW                    0
+
+#define CBR_C2MC_REQP_VX2_SHIFT                 _MK_SHIFT_CONST(258)
+#define CBR_C2MC_REQP_VX2_FIELD                 (_MK_MASK_CONST(0x1) << CBR_C2MC_REQP_VX2_SHIFT)
+#define CBR_C2MC_REQP_VX2_RANGE                 _MK_SHIFT_CONST(258):_MK_SHIFT_CONST(258)
+#define CBR_C2MC_REQP_VX2_ROW                   0
+
+#define CBR_C2MC_REQP_LP_SHIFT                  _MK_SHIFT_CONST(259)
+#define CBR_C2MC_REQP_LP_FIELD                  (_MK_MASK_CONST(0x1) << CBR_C2MC_REQP_LP_SHIFT)
+#define CBR_C2MC_REQP_LP_RANGE                  _MK_SHIFT_CONST(259):_MK_SHIFT_CONST(259)
+#define CBR_C2MC_REQP_LP_ROW                    0
+
+#define CBR_C2MC_REQP_YUV_SHIFT                 _MK_SHIFT_CONST(260)
+#define CBR_C2MC_REQP_YUV_FIELD                 (_MK_MASK_CONST(0x7) << CBR_C2MC_REQP_YUV_SHIFT)
+#define CBR_C2MC_REQP_YUV_RANGE                 _MK_SHIFT_CONST(262):_MK_SHIFT_CONST(260)
+#define CBR_C2MC_REQP_YUV_ROW                   0
+
+
+// Packet CBR_C2MC_SECURE
+#define CBR_C2MC_SECURE_SIZE 1
+
+#define CBR_C2MC_SECURE_SECURE_SHIFT                    _MK_SHIFT_CONST(0)
+#define CBR_C2MC_SECURE_SECURE_FIELD                    (_MK_MASK_CONST(0x1) << CBR_C2MC_SECURE_SECURE_SHIFT)
+#define CBR_C2MC_SECURE_SECURE_RANGE                    _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CBR_C2MC_SECURE_SECURE_ROW                      0
+
+
+// Packet CBR_C2MC_ADRXY
+#define CBR_C2MC_ADRXY_SIZE 44
+
+#define CBR_C2MC_ADRXY_OFFX_SHIFT                       _MK_SHIFT_CONST(0)
+#define CBR_C2MC_ADRXY_OFFX_FIELD                       (_MK_MASK_CONST(0xffff) << CBR_C2MC_ADRXY_OFFX_SHIFT)
+#define CBR_C2MC_ADRXY_OFFX_RANGE                       _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(0)
+#define CBR_C2MC_ADRXY_OFFX_ROW                 0
+
+#define CBR_C2MC_ADRXY_OFFY_SHIFT                       _MK_SHIFT_CONST(16)
+#define CBR_C2MC_ADRXY_OFFY_FIELD                       (_MK_MASK_CONST(0x3fff) << CBR_C2MC_ADRXY_OFFY_SHIFT)
+#define CBR_C2MC_ADRXY_OFFY_RANGE                       _MK_SHIFT_CONST(29):_MK_SHIFT_CONST(16)
+#define CBR_C2MC_ADRXY_OFFY_ROW                 0
+
+#define CBR_C2MC_ADRXY_OFFYUV_SHIFT                     _MK_SHIFT_CONST(30)
+#define CBR_C2MC_ADRXY_OFFYUV_FIELD                     (_MK_MASK_CONST(0x3fff) << CBR_C2MC_ADRXY_OFFYUV_SHIFT)
+#define CBR_C2MC_ADRXY_OFFYUV_RANGE                     _MK_SHIFT_CONST(43):_MK_SHIFT_CONST(30)
+#define CBR_C2MC_ADRXY_OFFYUV_ROW                       0
+
+
+// Packet CBR_C2MC_TILE
+#define CBR_C2MC_TILE_SIZE 98
+
+#define CBR_C2MC_TILE_LINADR_SHIFT                      _MK_SHIFT_CONST(0)
+#define CBR_C2MC_TILE_LINADR_FIELD                      (_MK_MASK_CONST(0xffffffff) << CBR_C2MC_TILE_LINADR_SHIFT)
+#define CBR_C2MC_TILE_LINADR_RANGE                      _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CBR_C2MC_TILE_LINADR_ROW                        0
+
+#define CBR_C2MC_TILE_LINADRU_SHIFT                     _MK_SHIFT_CONST(32)
+#define CBR_C2MC_TILE_LINADRU_FIELD                     (_MK_MASK_CONST(0xffffffff) << CBR_C2MC_TILE_LINADRU_SHIFT)
+#define CBR_C2MC_TILE_LINADRU_RANGE                     _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(32)
+#define CBR_C2MC_TILE_LINADRU_ROW                       0
+
+#define CBR_C2MC_TILE_LINADRV_SHIFT                     _MK_SHIFT_CONST(64)
+#define CBR_C2MC_TILE_LINADRV_FIELD                     (_MK_MASK_CONST(0xffffffff) << CBR_C2MC_TILE_LINADRV_SHIFT)
+#define CBR_C2MC_TILE_LINADRV_RANGE                     _MK_SHIFT_CONST(95):_MK_SHIFT_CONST(64)
+#define CBR_C2MC_TILE_LINADRV_ROW                       0
+
+#define CBR_C2MC_TILE_TMODE_SHIFT                       _MK_SHIFT_CONST(96)
+#define CBR_C2MC_TILE_TMODE_FIELD                       (_MK_MASK_CONST(0x1) << CBR_C2MC_TILE_TMODE_SHIFT)
+#define CBR_C2MC_TILE_TMODE_RANGE                       _MK_SHIFT_CONST(96):_MK_SHIFT_CONST(96)
+#define CBR_C2MC_TILE_TMODE_ROW                 0
+#define CBR_C2MC_TILE_TMODE_LINEAR                      _MK_ENUM_CONST(0)
+#define CBR_C2MC_TILE_TMODE_TILED                       _MK_ENUM_CONST(1)
+
+#define CBR_C2MC_TILE_TMODEUV_SHIFT                     _MK_SHIFT_CONST(97)
+#define CBR_C2MC_TILE_TMODEUV_FIELD                     (_MK_MASK_CONST(0x1) << CBR_C2MC_TILE_TMODEUV_SHIFT)
+#define CBR_C2MC_TILE_TMODEUV_RANGE                     _MK_SHIFT_CONST(97):_MK_SHIFT_CONST(97)
+#define CBR_C2MC_TILE_TMODEUV_ROW                       0
+#define CBR_C2MC_TILE_TMODEUV_LINEAR                    _MK_ENUM_CONST(0)
+#define CBR_C2MC_TILE_TMODEUV_TILED                     _MK_ENUM_CONST(1)
+
+
+// Packet CBR_C2MC_RDYP
+#define CBR_C2MC_RDYP_SIZE 1
+
+// fake data
+#define CBR_C2MC_RDYP_RDYP_SHIFT                        _MK_SHIFT_CONST(0)
+#define CBR_C2MC_RDYP_RDYP_FIELD                        (_MK_MASK_CONST(0x1) << CBR_C2MC_RDYP_RDYP_SHIFT)
+#define CBR_C2MC_RDYP_RDYP_RANGE                        _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CBR_C2MC_RDYP_RDYP_ROW                  0
+
+
+// Packet CBR_C2MC_OUTSTD
+#define CBR_C2MC_OUTSTD_SIZE 1
+
+#define CBR_C2MC_OUTSTD_OUTSTD_SHIFT                    _MK_SHIFT_CONST(0)
+#define CBR_C2MC_OUTSTD_OUTSTD_FIELD                    (_MK_MASK_CONST(0x1) << CBR_C2MC_OUTSTD_OUTSTD_SHIFT)
+#define CBR_C2MC_OUTSTD_OUTSTD_RANGE                    _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CBR_C2MC_OUTSTD_OUTSTD_ROW                      0
+
+
+// Packet CBR_C2MC_STOP
+#define CBR_C2MC_STOP_SIZE 1
+
+#define CBR_C2MC_STOP_STOP_SHIFT                        _MK_SHIFT_CONST(0)
+#define CBR_C2MC_STOP_STOP_FIELD                        (_MK_MASK_CONST(0x1) << CBR_C2MC_STOP_STOP_SHIFT)
+#define CBR_C2MC_STOP_STOP_RANGE                        _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CBR_C2MC_STOP_STOP_ROW                  0
+
+
+// Packet CBR_C2MC_RDI
+#define CBR_C2MC_RDI_SIZE 262
+
+#define CBR_C2MC_RDI_RDI_SHIFT                  _MK_SHIFT_CONST(0)
+#define CBR_C2MC_RDI_RDI_FIELD                  (_MK_MASK_CONST(0xffffffff) << CBR_C2MC_RDI_RDI_SHIFT)
+#define CBR_C2MC_RDI_RDI_RANGE                  _MK_SHIFT_CONST(255):_MK_SHIFT_CONST(0)
+#define CBR_C2MC_RDI_RDI_ROW                    0
+
+#define CBR_C2MC_RDI_RDILST_SHIFT                       _MK_SHIFT_CONST(256)
+#define CBR_C2MC_RDI_RDILST_FIELD                       (_MK_MASK_CONST(0x1) << CBR_C2MC_RDI_RDILST_SHIFT)
+#define CBR_C2MC_RDI_RDILST_RANGE                       _MK_SHIFT_CONST(256):_MK_SHIFT_CONST(256)
+#define CBR_C2MC_RDI_RDILST_ROW                 0
+
+#define CBR_C2MC_RDI_RDINB_SHIFT                        _MK_SHIFT_CONST(257)
+#define CBR_C2MC_RDI_RDINB_FIELD                        (_MK_MASK_CONST(0x1f) << CBR_C2MC_RDI_RDINB_SHIFT)
+#define CBR_C2MC_RDI_RDINB_RANGE                        _MK_SHIFT_CONST(261):_MK_SHIFT_CONST(257)
+#define CBR_C2MC_RDI_RDINB_ROW                  0
+
+
+// Packet CBR_C2MC_DOREQ
+#define CBR_C2MC_DOREQ_SIZE 64
+
+#define CBR_C2MC_DOREQ_ADR_SHIFT                        _MK_SHIFT_CONST(0)
+#define CBR_C2MC_DOREQ_ADR_FIELD                        (_MK_MASK_CONST(0xffffffff) << CBR_C2MC_DOREQ_ADR_SHIFT)
+#define CBR_C2MC_DOREQ_ADR_RANGE                        _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CBR_C2MC_DOREQ_ADR_ROW                  0
+
+#define CBR_C2MC_DOREQ_LS_SHIFT                 _MK_SHIFT_CONST(32)
+#define CBR_C2MC_DOREQ_LS_FIELD                 (_MK_MASK_CONST(0xffffffff) << CBR_C2MC_DOREQ_LS_SHIFT)
+#define CBR_C2MC_DOREQ_LS_RANGE                 _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(32)
+#define CBR_C2MC_DOREQ_LS_ROW                   0
+
+
+// Packet CBR_C2MC_HP
+#define CBR_C2MC_HP_SIZE 71
+
+// high-priority threshold
+#define CBR_C2MC_HP_HPTH_SHIFT                  _MK_SHIFT_CONST(0)
+#define CBR_C2MC_HP_HPTH_FIELD                  (_MK_MASK_CONST(0xffffffff) << CBR_C2MC_HP_HPTH_SHIFT)
+#define CBR_C2MC_HP_HPTH_RANGE                  _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CBR_C2MC_HP_HPTH_ROW                    0
+
+// high-priority timer
+#define CBR_C2MC_HP_HPTM_SHIFT                  _MK_SHIFT_CONST(32)
+#define CBR_C2MC_HP_HPTM_FIELD                  (_MK_MASK_CONST(0x3f) << CBR_C2MC_HP_HPTM_SHIFT)
+#define CBR_C2MC_HP_HPTM_RANGE                  _MK_SHIFT_CONST(37):_MK_SHIFT_CONST(32)
+#define CBR_C2MC_HP_HPTM_ROW                    0
+
+// suppression - start of frame
+#define CBR_C2MC_HP_HPSOF_SHIFT                 _MK_SHIFT_CONST(38)
+#define CBR_C2MC_HP_HPSOF_FIELD                 (_MK_MASK_CONST(0x1) << CBR_C2MC_HP_HPSOF_SHIFT)
+#define CBR_C2MC_HP_HPSOF_RANGE                 _MK_SHIFT_CONST(38):_MK_SHIFT_CONST(38)
+#define CBR_C2MC_HP_HPSOF_ROW                   0
+
+// suppression - cycles per word
+#define CBR_C2MC_HP_HPCPW_SHIFT                 _MK_SHIFT_CONST(39)
+#define CBR_C2MC_HP_HPCPW_FIELD                 (_MK_MASK_CONST(0xffff) << CBR_C2MC_HP_HPCPW_SHIFT)
+#define CBR_C2MC_HP_HPCPW_RANGE                 _MK_SHIFT_CONST(54):_MK_SHIFT_CONST(39)
+#define CBR_C2MC_HP_HPCPW_ROW                   0
+
+// suppression - words per line
+#define CBR_C2MC_HP_HPCBNPW_SHIFT                       _MK_SHIFT_CONST(55)
+#define CBR_C2MC_HP_HPCBNPW_FIELD                       (_MK_MASK_CONST(0xffff) << CBR_C2MC_HP_HPCBNPW_SHIFT)
+#define CBR_C2MC_HP_HPCBNPW_RANGE                       _MK_SHIFT_CONST(70):_MK_SHIFT_CONST(55)
+#define CBR_C2MC_HP_HPCBNPW_ROW                 0
+
+
+// Packet CBR_C2MC_HYST
+#define CBR_C2MC_HYST_SIZE 32
+
+#define CBR_C2MC_HYST_HYST_REQ_TM_SHIFT                 _MK_SHIFT_CONST(0)
+#define CBR_C2MC_HYST_HYST_REQ_TM_FIELD                 (_MK_MASK_CONST(0xff) << CBR_C2MC_HYST_HYST_REQ_TM_SHIFT)
+#define CBR_C2MC_HYST_HYST_REQ_TM_RANGE                 _MK_SHIFT_CONST(7):_MK_SHIFT_CONST(0)
+#define CBR_C2MC_HYST_HYST_REQ_TM_ROW                   0
+
+#define CBR_C2MC_HYST_DHYST_TM_SHIFT                    _MK_SHIFT_CONST(8)
+#define CBR_C2MC_HYST_DHYST_TM_FIELD                    (_MK_MASK_CONST(0xff) << CBR_C2MC_HYST_DHYST_TM_SHIFT)
+#define CBR_C2MC_HYST_DHYST_TM_RANGE                    _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(8)
+#define CBR_C2MC_HYST_DHYST_TM_ROW                      0
+
+#define CBR_C2MC_HYST_DHYST_TH_SHIFT                    _MK_SHIFT_CONST(16)
+#define CBR_C2MC_HYST_DHYST_TH_FIELD                    (_MK_MASK_CONST(0xff) << CBR_C2MC_HYST_DHYST_TH_SHIFT)
+#define CBR_C2MC_HYST_DHYST_TH_RANGE                    _MK_SHIFT_CONST(23):_MK_SHIFT_CONST(16)
+#define CBR_C2MC_HYST_DHYST_TH_ROW                      0
+
+#define CBR_C2MC_HYST_HYST_TM_SHIFT                     _MK_SHIFT_CONST(24)
+#define CBR_C2MC_HYST_HYST_TM_FIELD                     (_MK_MASK_CONST(0xf) << CBR_C2MC_HYST_HYST_TM_SHIFT)
+#define CBR_C2MC_HYST_HYST_TM_RANGE                     _MK_SHIFT_CONST(27):_MK_SHIFT_CONST(24)
+#define CBR_C2MC_HYST_HYST_TM_ROW                       0
+
+#define CBR_C2MC_HYST_HYST_REQ_TH_SHIFT                 _MK_SHIFT_CONST(28)
+#define CBR_C2MC_HYST_HYST_REQ_TH_FIELD                 (_MK_MASK_CONST(0x7) << CBR_C2MC_HYST_HYST_REQ_TH_SHIFT)
+#define CBR_C2MC_HYST_HYST_REQ_TH_RANGE                 _MK_SHIFT_CONST(30):_MK_SHIFT_CONST(28)
+#define CBR_C2MC_HYST_HYST_REQ_TH_ROW                   0
+
+#define CBR_C2MC_HYST_HYST_EN_SHIFT                     _MK_SHIFT_CONST(31)
+#define CBR_C2MC_HYST_HYST_EN_FIELD                     (_MK_MASK_CONST(0x1) << CBR_C2MC_HYST_HYST_EN_SHIFT)
+#define CBR_C2MC_HYST_HYST_EN_RANGE                     _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(31)
+#define CBR_C2MC_HYST_HYST_EN_ROW                       0
+
+
+// Packet CBW_C2MC_RESET
+#define CBW_C2MC_RESET_SIZE 1
+
+#define CBW_C2MC_RESET_RSTN_SHIFT                       _MK_SHIFT_CONST(0)
+#define CBW_C2MC_RESET_RSTN_FIELD                       (_MK_MASK_CONST(0x1) << CBW_C2MC_RESET_RSTN_SHIFT)
+#define CBW_C2MC_RESET_RSTN_RANGE                       _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CBW_C2MC_RESET_RSTN_ROW                 0
+
+
+// Packet CBW_C2MC_REQP
+#define CBW_C2MC_REQP_SIZE 134
+
+#define CBW_C2MC_REQP_ADR_SHIFT                 _MK_SHIFT_CONST(0)
+#define CBW_C2MC_REQP_ADR_FIELD                 (_MK_MASK_CONST(0xffffffff) << CBW_C2MC_REQP_ADR_SHIFT)
+#define CBW_C2MC_REQP_ADR_RANGE                 _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CBW_C2MC_REQP_ADR_ROW                   0
+
+#define CBW_C2MC_REQP_LS_SHIFT                  _MK_SHIFT_CONST(32)
+#define CBW_C2MC_REQP_LS_FIELD                  (_MK_MASK_CONST(0xffffffff) << CBW_C2MC_REQP_LS_SHIFT)
+#define CBW_C2MC_REQP_LS_RANGE                  _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(32)
+#define CBW_C2MC_REQP_LS_ROW                    0
+
+#define CBW_C2MC_REQP_HS_SHIFT                  _MK_SHIFT_CONST(64)
+#define CBW_C2MC_REQP_HS_FIELD                  (_MK_MASK_CONST(0xffffffff) << CBW_C2MC_REQP_HS_SHIFT)
+#define CBW_C2MC_REQP_HS_RANGE                  _MK_SHIFT_CONST(95):_MK_SHIFT_CONST(64)
+#define CBW_C2MC_REQP_HS_ROW                    0
+
+#define CBW_C2MC_REQP_VS_SHIFT                  _MK_SHIFT_CONST(96)
+#define CBW_C2MC_REQP_VS_FIELD                  (_MK_MASK_CONST(0xffffffff) << CBW_C2MC_REQP_VS_SHIFT)
+#define CBW_C2MC_REQP_VS_RANGE                  _MK_SHIFT_CONST(127):_MK_SHIFT_CONST(96)
+#define CBW_C2MC_REQP_VS_ROW                    0
+
+#define CBW_C2MC_REQP_HD_SHIFT                  _MK_SHIFT_CONST(128)
+#define CBW_C2MC_REQP_HD_FIELD                  (_MK_MASK_CONST(0x1) << CBW_C2MC_REQP_HD_SHIFT)
+#define CBW_C2MC_REQP_HD_RANGE                  _MK_SHIFT_CONST(128):_MK_SHIFT_CONST(128)
+#define CBW_C2MC_REQP_HD_ROW                    0
+
+#define CBW_C2MC_REQP_VD_SHIFT                  _MK_SHIFT_CONST(129)
+#define CBW_C2MC_REQP_VD_FIELD                  (_MK_MASK_CONST(0x1) << CBW_C2MC_REQP_VD_SHIFT)
+#define CBW_C2MC_REQP_VD_RANGE                  _MK_SHIFT_CONST(129):_MK_SHIFT_CONST(129)
+#define CBW_C2MC_REQP_VD_ROW                    0
+
+#define CBW_C2MC_REQP_BPP_SHIFT                 _MK_SHIFT_CONST(130)
+#define CBW_C2MC_REQP_BPP_FIELD                 (_MK_MASK_CONST(0x3) << CBW_C2MC_REQP_BPP_SHIFT)
+#define CBW_C2MC_REQP_BPP_RANGE                 _MK_SHIFT_CONST(131):_MK_SHIFT_CONST(130)
+#define CBW_C2MC_REQP_BPP_ROW                   0
+
+#define CBW_C2MC_REQP_XY_SHIFT                  _MK_SHIFT_CONST(132)
+#define CBW_C2MC_REQP_XY_FIELD                  (_MK_MASK_CONST(0x1) << CBW_C2MC_REQP_XY_SHIFT)
+#define CBW_C2MC_REQP_XY_RANGE                  _MK_SHIFT_CONST(132):_MK_SHIFT_CONST(132)
+#define CBW_C2MC_REQP_XY_ROW                    0
+
+#define CBW_C2MC_REQP_PK_SHIFT                  _MK_SHIFT_CONST(133)
+#define CBW_C2MC_REQP_PK_FIELD                  (_MK_MASK_CONST(0x1) << CBW_C2MC_REQP_PK_SHIFT)
+#define CBW_C2MC_REQP_PK_RANGE                  _MK_SHIFT_CONST(133):_MK_SHIFT_CONST(133)
+#define CBW_C2MC_REQP_PK_ROW                    0
+
+
+// Packet CBW_C2MC_SECURE
+#define CBW_C2MC_SECURE_SIZE 1
+
+#define CBW_C2MC_SECURE_SECURE_SHIFT                    _MK_SHIFT_CONST(0)
+#define CBW_C2MC_SECURE_SECURE_FIELD                    (_MK_MASK_CONST(0x1) << CBW_C2MC_SECURE_SECURE_SHIFT)
+#define CBW_C2MC_SECURE_SECURE_RANGE                    _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CBW_C2MC_SECURE_SECURE_ROW                      0
+
+
+// Packet CBW_C2MC_ADRXY
+#define CBW_C2MC_ADRXY_SIZE 30
+
+#define CBW_C2MC_ADRXY_OFFX_SHIFT                       _MK_SHIFT_CONST(0)
+#define CBW_C2MC_ADRXY_OFFX_FIELD                       (_MK_MASK_CONST(0xffff) << CBW_C2MC_ADRXY_OFFX_SHIFT)
+#define CBW_C2MC_ADRXY_OFFX_RANGE                       _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(0)
+#define CBW_C2MC_ADRXY_OFFX_ROW                 0
+
+#define CBW_C2MC_ADRXY_OFFY_SHIFT                       _MK_SHIFT_CONST(16)
+#define CBW_C2MC_ADRXY_OFFY_FIELD                       (_MK_MASK_CONST(0x3fff) << CBW_C2MC_ADRXY_OFFY_SHIFT)
+#define CBW_C2MC_ADRXY_OFFY_RANGE                       _MK_SHIFT_CONST(29):_MK_SHIFT_CONST(16)
+#define CBW_C2MC_ADRXY_OFFY_ROW                 0
+
+
+// Packet CBW_C2MC_TILE
+#define CBW_C2MC_TILE_SIZE 33
+
+#define CBW_C2MC_TILE_LINADR_SHIFT                      _MK_SHIFT_CONST(0)
+#define CBW_C2MC_TILE_LINADR_FIELD                      (_MK_MASK_CONST(0xffffffff) << CBW_C2MC_TILE_LINADR_SHIFT)
+#define CBW_C2MC_TILE_LINADR_RANGE                      _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CBW_C2MC_TILE_LINADR_ROW                        0
+
+#define CBW_C2MC_TILE_TMODE_SHIFT                       _MK_SHIFT_CONST(32)
+#define CBW_C2MC_TILE_TMODE_FIELD                       (_MK_MASK_CONST(0x1) << CBW_C2MC_TILE_TMODE_SHIFT)
+#define CBW_C2MC_TILE_TMODE_RANGE                       _MK_SHIFT_CONST(32):_MK_SHIFT_CONST(32)
+#define CBW_C2MC_TILE_TMODE_ROW                 0
+#define CBW_C2MC_TILE_TMODE_LINEAR                      _MK_ENUM_CONST(0)
+#define CBW_C2MC_TILE_TMODE_TILED                       _MK_ENUM_CONST(1)
+
+
+// Packet CBW_C2MC_RDYP
+#define CBW_C2MC_RDYP_SIZE 1
+
+// fake data
+#define CBW_C2MC_RDYP_RDYP_SHIFT                        _MK_SHIFT_CONST(0)
+#define CBW_C2MC_RDYP_RDYP_FIELD                        (_MK_MASK_CONST(0x1) << CBW_C2MC_RDYP_RDYP_SHIFT)
+#define CBW_C2MC_RDYP_RDYP_RANGE                        _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CBW_C2MC_RDYP_RDYP_ROW                  0
+
+
+// Packet CBW_C2MC_STOP
+#define CBW_C2MC_STOP_SIZE 1
+
+#define CBW_C2MC_STOP_STOP_SHIFT                        _MK_SHIFT_CONST(0)
+#define CBW_C2MC_STOP_STOP_FIELD                        (_MK_MASK_CONST(0x1) << CBW_C2MC_STOP_STOP_SHIFT)
+#define CBW_C2MC_STOP_STOP_RANGE                        _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CBW_C2MC_STOP_STOP_ROW                  0
+
+
+// Packet CBW_C2MC_XDI
+#define CBW_C2MC_XDI_SIZE 1
+
+// fake data
+#define CBW_C2MC_XDI_XDI_SHIFT                  _MK_SHIFT_CONST(0)
+#define CBW_C2MC_XDI_XDI_FIELD                  (_MK_MASK_CONST(0x1) << CBW_C2MC_XDI_XDI_SHIFT)
+#define CBW_C2MC_XDI_XDI_RANGE                  _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CBW_C2MC_XDI_XDI_ROW                    0
+
+
+// Packet CBW_C2MC_DOREQ
+#define CBW_C2MC_DOREQ_SIZE 321
+
+#define CBW_C2MC_DOREQ_ADR_SHIFT                        _MK_SHIFT_CONST(0)
+#define CBW_C2MC_DOREQ_ADR_FIELD                        (_MK_MASK_CONST(0xffffffff) << CBW_C2MC_DOREQ_ADR_SHIFT)
+#define CBW_C2MC_DOREQ_ADR_RANGE                        _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CBW_C2MC_DOREQ_ADR_ROW                  0
+
+#define CBW_C2MC_DOREQ_BE_SHIFT                 _MK_SHIFT_CONST(32)
+#define CBW_C2MC_DOREQ_BE_FIELD                 (_MK_MASK_CONST(0xffffffff) << CBW_C2MC_DOREQ_BE_SHIFT)
+#define CBW_C2MC_DOREQ_BE_RANGE                 _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(32)
+#define CBW_C2MC_DOREQ_BE_ROW                   0
+
+#define CBW_C2MC_DOREQ_WDO_SHIFT                        _MK_SHIFT_CONST(64)
+#define CBW_C2MC_DOREQ_WDO_FIELD                        (_MK_MASK_CONST(0xffffffff) << CBW_C2MC_DOREQ_WDO_SHIFT)
+#define CBW_C2MC_DOREQ_WDO_RANGE                        _MK_SHIFT_CONST(319):_MK_SHIFT_CONST(64)
+#define CBW_C2MC_DOREQ_WDO_ROW                  0
+
+#define CBW_C2MC_DOREQ_TAG_SHIFT                        _MK_SHIFT_CONST(320)
+#define CBW_C2MC_DOREQ_TAG_FIELD                        (_MK_MASK_CONST(0x1) << CBW_C2MC_DOREQ_TAG_SHIFT)
+#define CBW_C2MC_DOREQ_TAG_RANGE                        _MK_SHIFT_CONST(320):_MK_SHIFT_CONST(320)
+#define CBW_C2MC_DOREQ_TAG_ROW                  0
+
+
+// Packet CBW_C2MC_HP
+#define CBW_C2MC_HP_SIZE 32
+
+// high-priority threshold
+#define CBW_C2MC_HP_HPTH_SHIFT                  _MK_SHIFT_CONST(0)
+#define CBW_C2MC_HP_HPTH_FIELD                  (_MK_MASK_CONST(0xffffffff) << CBW_C2MC_HP_HPTH_SHIFT)
+#define CBW_C2MC_HP_HPTH_RANGE                  _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CBW_C2MC_HP_HPTH_ROW                    0
+
+
+// Packet CBW_C2MC_WCOAL
+#define CBW_C2MC_WCOAL_SIZE 32
+
+// write-coalescing time-out
+#define CBW_C2MC_WCOAL_WCOALTM_SHIFT                    _MK_SHIFT_CONST(0)
+#define CBW_C2MC_WCOAL_WCOALTM_FIELD                    (_MK_MASK_CONST(0xffffffff) << CBW_C2MC_WCOAL_WCOALTM_SHIFT)
+#define CBW_C2MC_WCOAL_WCOALTM_RANGE                    _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CBW_C2MC_WCOAL_WCOALTM_ROW                      0
+
+
+// Packet CBW_C2MC_HYST
+#define CBW_C2MC_HYST_SIZE 32
+
+#define CBW_C2MC_HYST_HYST_REQ_TM_SHIFT                 _MK_SHIFT_CONST(0)
+#define CBW_C2MC_HYST_HYST_REQ_TM_FIELD                 (_MK_MASK_CONST(0xfff) << CBW_C2MC_HYST_HYST_REQ_TM_SHIFT)
+#define CBW_C2MC_HYST_HYST_REQ_TM_RANGE                 _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(0)
+#define CBW_C2MC_HYST_HYST_REQ_TM_ROW                   0
+
+#define CBW_C2MC_HYST_HYST_REQ_TH_SHIFT                 _MK_SHIFT_CONST(28)
+#define CBW_C2MC_HYST_HYST_REQ_TH_FIELD                 (_MK_MASK_CONST(0x7) << CBW_C2MC_HYST_HYST_REQ_TH_SHIFT)
+#define CBW_C2MC_HYST_HYST_REQ_TH_RANGE                 _MK_SHIFT_CONST(30):_MK_SHIFT_CONST(28)
+#define CBW_C2MC_HYST_HYST_REQ_TH_ROW                   0
+
+#define CBW_C2MC_HYST_HYST_EN_SHIFT                     _MK_SHIFT_CONST(31)
+#define CBW_C2MC_HYST_HYST_EN_FIELD                     (_MK_MASK_CONST(0x1) << CBW_C2MC_HYST_HYST_EN_SHIFT)
+#define CBW_C2MC_HYST_HYST_EN_RANGE                     _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(31)
+#define CBW_C2MC_HYST_HYST_EN_ROW                       0
+
+
+// Packet CCR_C2MC_RESET
+#define CCR_C2MC_RESET_SIZE 1
+
+#define CCR_C2MC_RESET_RSTN_SHIFT                       _MK_SHIFT_CONST(0)
+#define CCR_C2MC_RESET_RSTN_FIELD                       (_MK_MASK_CONST(0x1) << CCR_C2MC_RESET_RSTN_SHIFT)
+#define CCR_C2MC_RESET_RSTN_RANGE                       _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CCR_C2MC_RESET_RSTN_ROW                 0
+
+
+// Packet CCR_C2MC_REQ
+#define CCR_C2MC_REQ_SIZE 101
+
+#define CCR_C2MC_REQ_ADR_SHIFT                  _MK_SHIFT_CONST(0)
+#define CCR_C2MC_REQ_ADR_FIELD                  (_MK_MASK_CONST(0xffffffff) << CCR_C2MC_REQ_ADR_SHIFT)
+#define CCR_C2MC_REQ_ADR_RANGE                  _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CCR_C2MC_REQ_ADR_ROW                    0
+
+#define CCR_C2MC_REQ_LS_SHIFT                   _MK_SHIFT_CONST(32)
+#define CCR_C2MC_REQ_LS_FIELD                   (_MK_MASK_CONST(0xffffffff) << CCR_C2MC_REQ_LS_SHIFT)
+#define CCR_C2MC_REQ_LS_RANGE                   _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(32)
+#define CCR_C2MC_REQ_LS_ROW                     0
+
+// HI is apparently a reserved keyword
+#define CCR_C2MC_REQ_HINC_SHIFT                 _MK_SHIFT_CONST(64)
+#define CCR_C2MC_REQ_HINC_FIELD                 (_MK_MASK_CONST(0xffffffff) << CCR_C2MC_REQ_HINC_SHIFT)
+#define CCR_C2MC_REQ_HINC_RANGE                 _MK_SHIFT_CONST(95):_MK_SHIFT_CONST(64)
+#define CCR_C2MC_REQ_HINC_ROW                   0
+
+#define CCR_C2MC_REQ_ACMD_SHIFT                 _MK_SHIFT_CONST(96)
+#define CCR_C2MC_REQ_ACMD_FIELD                 (_MK_MASK_CONST(0x3) << CCR_C2MC_REQ_ACMD_SHIFT)
+#define CCR_C2MC_REQ_ACMD_RANGE                 _MK_SHIFT_CONST(97):_MK_SHIFT_CONST(96)
+#define CCR_C2MC_REQ_ACMD_ROW                   0
+
+#define CCR_C2MC_REQ_LN_SHIFT                   _MK_SHIFT_CONST(98)
+#define CCR_C2MC_REQ_LN_FIELD                   (_MK_MASK_CONST(0x1) << CCR_C2MC_REQ_LN_SHIFT)
+#define CCR_C2MC_REQ_LN_RANGE                   _MK_SHIFT_CONST(98):_MK_SHIFT_CONST(98)
+#define CCR_C2MC_REQ_LN_ROW                     0
+
+#define CCR_C2MC_REQ_HD_SHIFT                   _MK_SHIFT_CONST(99)
+#define CCR_C2MC_REQ_HD_FIELD                   (_MK_MASK_CONST(0x1) << CCR_C2MC_REQ_HD_SHIFT)
+#define CCR_C2MC_REQ_HD_RANGE                   _MK_SHIFT_CONST(99):_MK_SHIFT_CONST(99)
+#define CCR_C2MC_REQ_HD_ROW                     0
+
+#define CCR_C2MC_REQ_VD_SHIFT                   _MK_SHIFT_CONST(100)
+#define CCR_C2MC_REQ_VD_FIELD                   (_MK_MASK_CONST(0x1) << CCR_C2MC_REQ_VD_SHIFT)
+#define CCR_C2MC_REQ_VD_RANGE                   _MK_SHIFT_CONST(100):_MK_SHIFT_CONST(100)
+#define CCR_C2MC_REQ_VD_ROW                     0
+
+
+// Packet CCR_C2MC_SECURE
+#define CCR_C2MC_SECURE_SIZE 1
+
+#define CCR_C2MC_SECURE_SECURE_SHIFT                    _MK_SHIFT_CONST(0)
+#define CCR_C2MC_SECURE_SECURE_FIELD                    (_MK_MASK_CONST(0x1) << CCR_C2MC_SECURE_SECURE_SHIFT)
+#define CCR_C2MC_SECURE_SECURE_RANGE                    _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CCR_C2MC_SECURE_SECURE_ROW                      0
+
+
+// Packet CCR_C2MC_RDI
+#define CCR_C2MC_RDI_SIZE 256
+
+#define CCR_C2MC_RDI_RDI_SHIFT                  _MK_SHIFT_CONST(0)
+#define CCR_C2MC_RDI_RDI_FIELD                  (_MK_MASK_CONST(0xffffffff) << CCR_C2MC_RDI_RDI_SHIFT)
+#define CCR_C2MC_RDI_RDI_RANGE                  _MK_SHIFT_CONST(255):_MK_SHIFT_CONST(0)
+#define CCR_C2MC_RDI_RDI_ROW                    0
+
+
+// Packet CCR_C2MC_HP
+#define CCR_C2MC_HP_SIZE 38
+
+// high-priority threshold
+#define CCR_C2MC_HP_HPTH_SHIFT                  _MK_SHIFT_CONST(0)
+#define CCR_C2MC_HP_HPTH_FIELD                  (_MK_MASK_CONST(0xffffffff) << CCR_C2MC_HP_HPTH_SHIFT)
+#define CCR_C2MC_HP_HPTH_RANGE                  _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CCR_C2MC_HP_HPTH_ROW                    0
+
+// high-priority timer
+#define CCR_C2MC_HP_HPTM_SHIFT                  _MK_SHIFT_CONST(32)
+#define CCR_C2MC_HP_HPTM_FIELD                  (_MK_MASK_CONST(0x3f) << CCR_C2MC_HP_HPTM_SHIFT)
+#define CCR_C2MC_HP_HPTM_RANGE                  _MK_SHIFT_CONST(37):_MK_SHIFT_CONST(32)
+#define CCR_C2MC_HP_HPTM_ROW                    0
+
+
+// Packet CCR_C2MC_HYST
+#define CCR_C2MC_HYST_SIZE 32
+
+// hysteresis control register
+#define CCR_C2MC_HYST_HYST_SHIFT                        _MK_SHIFT_CONST(0)
+#define CCR_C2MC_HYST_HYST_FIELD                        (_MK_MASK_CONST(0xffffffff) << CCR_C2MC_HYST_HYST_SHIFT)
+#define CCR_C2MC_HYST_HYST_RANGE                        _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CCR_C2MC_HYST_HYST_ROW                  0
+
+
+// Packet CCW_C2MC_RESET
+#define CCW_C2MC_RESET_SIZE 1
+
+#define CCW_C2MC_RESET_RSTN_SHIFT                       _MK_SHIFT_CONST(0)
+#define CCW_C2MC_RESET_RSTN_FIELD                       (_MK_MASK_CONST(0x1) << CCW_C2MC_RESET_RSTN_SHIFT)
+#define CCW_C2MC_RESET_RSTN_RANGE                       _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CCW_C2MC_RESET_RSTN_ROW                 0
+
+
+// Packet CCW_C2MC_REQ
+#define CCW_C2MC_REQ_SIZE 417
+
+#define CCW_C2MC_REQ_ADR_SHIFT                  _MK_SHIFT_CONST(0)
+#define CCW_C2MC_REQ_ADR_FIELD                  (_MK_MASK_CONST(0xffffffff) << CCW_C2MC_REQ_ADR_SHIFT)
+#define CCW_C2MC_REQ_ADR_RANGE                  _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CCW_C2MC_REQ_ADR_ROW                    0
+
+#define CCW_C2MC_REQ_LS_SHIFT                   _MK_SHIFT_CONST(32)
+#define CCW_C2MC_REQ_LS_FIELD                   (_MK_MASK_CONST(0xffffffff) << CCW_C2MC_REQ_LS_SHIFT)
+#define CCW_C2MC_REQ_LS_RANGE                   _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(32)
+#define CCW_C2MC_REQ_LS_ROW                     0
+
+// HI is apparently a reserved keyword
+#define CCW_C2MC_REQ_HINC_SHIFT                 _MK_SHIFT_CONST(64)
+#define CCW_C2MC_REQ_HINC_FIELD                 (_MK_MASK_CONST(0xffffffff) << CCW_C2MC_REQ_HINC_SHIFT)
+#define CCW_C2MC_REQ_HINC_RANGE                 _MK_SHIFT_CONST(95):_MK_SHIFT_CONST(64)
+#define CCW_C2MC_REQ_HINC_ROW                   0
+
+#define CCW_C2MC_REQ_ACMD_SHIFT                 _MK_SHIFT_CONST(96)
+#define CCW_C2MC_REQ_ACMD_FIELD                 (_MK_MASK_CONST(0x3) << CCW_C2MC_REQ_ACMD_SHIFT)
+#define CCW_C2MC_REQ_ACMD_RANGE                 _MK_SHIFT_CONST(97):_MK_SHIFT_CONST(96)
+#define CCW_C2MC_REQ_ACMD_ROW                   0
+
+#define CCW_C2MC_REQ_LN_SHIFT                   _MK_SHIFT_CONST(98)
+#define CCW_C2MC_REQ_LN_FIELD                   (_MK_MASK_CONST(0x1) << CCW_C2MC_REQ_LN_SHIFT)
+#define CCW_C2MC_REQ_LN_RANGE                   _MK_SHIFT_CONST(98):_MK_SHIFT_CONST(98)
+#define CCW_C2MC_REQ_LN_ROW                     0
+
+#define CCW_C2MC_REQ_HD_SHIFT                   _MK_SHIFT_CONST(99)
+#define CCW_C2MC_REQ_HD_FIELD                   (_MK_MASK_CONST(0x1) << CCW_C2MC_REQ_HD_SHIFT)
+#define CCW_C2MC_REQ_HD_RANGE                   _MK_SHIFT_CONST(99):_MK_SHIFT_CONST(99)
+#define CCW_C2MC_REQ_HD_ROW                     0
+
+#define CCW_C2MC_REQ_VD_SHIFT                   _MK_SHIFT_CONST(100)
+#define CCW_C2MC_REQ_VD_FIELD                   (_MK_MASK_CONST(0x1) << CCW_C2MC_REQ_VD_SHIFT)
+#define CCW_C2MC_REQ_VD_RANGE                   _MK_SHIFT_CONST(100):_MK_SHIFT_CONST(100)
+#define CCW_C2MC_REQ_VD_ROW                     0
+
+#define CCW_C2MC_REQ_BPP_SHIFT                  _MK_SHIFT_CONST(101)
+#define CCW_C2MC_REQ_BPP_FIELD                  (_MK_MASK_CONST(0x3) << CCW_C2MC_REQ_BPP_SHIFT)
+#define CCW_C2MC_REQ_BPP_RANGE                  _MK_SHIFT_CONST(102):_MK_SHIFT_CONST(101)
+#define CCW_C2MC_REQ_BPP_ROW                    0
+
+#define CCW_C2MC_REQ_XY_SHIFT                   _MK_SHIFT_CONST(103)
+#define CCW_C2MC_REQ_XY_FIELD                   (_MK_MASK_CONST(0x1) << CCW_C2MC_REQ_XY_SHIFT)
+#define CCW_C2MC_REQ_XY_RANGE                   _MK_SHIFT_CONST(103):_MK_SHIFT_CONST(103)
+#define CCW_C2MC_REQ_XY_ROW                     0
+
+#define CCW_C2MC_REQ_BE_SHIFT                   _MK_SHIFT_CONST(128)
+#define CCW_C2MC_REQ_BE_FIELD                   (_MK_MASK_CONST(0xffffffff) << CCW_C2MC_REQ_BE_SHIFT)
+#define CCW_C2MC_REQ_BE_RANGE                   _MK_SHIFT_CONST(159):_MK_SHIFT_CONST(128)
+#define CCW_C2MC_REQ_BE_ROW                     0
+
+#define CCW_C2MC_REQ_WDO_SHIFT                  _MK_SHIFT_CONST(160)
+#define CCW_C2MC_REQ_WDO_FIELD                  (_MK_MASK_CONST(0xffffffff) << CCW_C2MC_REQ_WDO_SHIFT)
+#define CCW_C2MC_REQ_WDO_RANGE                  _MK_SHIFT_CONST(415):_MK_SHIFT_CONST(160)
+#define CCW_C2MC_REQ_WDO_ROW                    0
+
+#define CCW_C2MC_REQ_TAG_SHIFT                  _MK_SHIFT_CONST(416)
+#define CCW_C2MC_REQ_TAG_FIELD                  (_MK_MASK_CONST(0x1) << CCW_C2MC_REQ_TAG_SHIFT)
+#define CCW_C2MC_REQ_TAG_RANGE                  _MK_SHIFT_CONST(416):_MK_SHIFT_CONST(416)
+#define CCW_C2MC_REQ_TAG_ROW                    0
+
+
+// Packet CCW_C2MC_SECURE
+#define CCW_C2MC_SECURE_SIZE 1
+
+#define CCW_C2MC_SECURE_SECURE_SHIFT                    _MK_SHIFT_CONST(0)
+#define CCW_C2MC_SECURE_SECURE_FIELD                    (_MK_MASK_CONST(0x1) << CCW_C2MC_SECURE_SECURE_SHIFT)
+#define CCW_C2MC_SECURE_SECURE_RANGE                    _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CCW_C2MC_SECURE_SECURE_ROW                      0
+
+
+// Packet CCW_C2MC_ADRXY
+#define CCW_C2MC_ADRXY_SIZE 30
+
+#define CCW_C2MC_ADRXY_OFFX_SHIFT                       _MK_SHIFT_CONST(0)
+#define CCW_C2MC_ADRXY_OFFX_FIELD                       (_MK_MASK_CONST(0xffff) << CCW_C2MC_ADRXY_OFFX_SHIFT)
+#define CCW_C2MC_ADRXY_OFFX_RANGE                       _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(0)
+#define CCW_C2MC_ADRXY_OFFX_ROW                 0
+
+#define CCW_C2MC_ADRXY_OFFY_SHIFT                       _MK_SHIFT_CONST(16)
+#define CCW_C2MC_ADRXY_OFFY_FIELD                       (_MK_MASK_CONST(0x3fff) << CCW_C2MC_ADRXY_OFFY_SHIFT)
+#define CCW_C2MC_ADRXY_OFFY_RANGE                       _MK_SHIFT_CONST(29):_MK_SHIFT_CONST(16)
+#define CCW_C2MC_ADRXY_OFFY_ROW                 0
+
+
+// Packet CCW_C2MC_TILE
+#define CCW_C2MC_TILE_SIZE 33
+
+#define CCW_C2MC_TILE_LINADR_SHIFT                      _MK_SHIFT_CONST(0)
+#define CCW_C2MC_TILE_LINADR_FIELD                      (_MK_MASK_CONST(0xffffffff) << CCW_C2MC_TILE_LINADR_SHIFT)
+#define CCW_C2MC_TILE_LINADR_RANGE                      _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CCW_C2MC_TILE_LINADR_ROW                        0
+
+#define CCW_C2MC_TILE_TMODE_SHIFT                       _MK_SHIFT_CONST(32)
+#define CCW_C2MC_TILE_TMODE_FIELD                       (_MK_MASK_CONST(0x1) << CCW_C2MC_TILE_TMODE_SHIFT)
+#define CCW_C2MC_TILE_TMODE_RANGE                       _MK_SHIFT_CONST(32):_MK_SHIFT_CONST(32)
+#define CCW_C2MC_TILE_TMODE_ROW                 0
+#define CCW_C2MC_TILE_TMODE_LINEAR                      _MK_ENUM_CONST(0)
+#define CCW_C2MC_TILE_TMODE_TILED                       _MK_ENUM_CONST(1)
+
+
+// Packet CCW_C2MC_XDI
+#define CCW_C2MC_XDI_SIZE 1
+
+// fake data
+#define CCW_C2MC_XDI_XDI_SHIFT                  _MK_SHIFT_CONST(0)
+#define CCW_C2MC_XDI_XDI_FIELD                  (_MK_MASK_CONST(0x1) << CCW_C2MC_XDI_XDI_SHIFT)
+#define CCW_C2MC_XDI_XDI_RANGE                  _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CCW_C2MC_XDI_XDI_ROW                    0
+
+
+// Packet CCW_C2MC_HP
+#define CCW_C2MC_HP_SIZE 32
+
+// high-priority threshold
+#define CCW_C2MC_HP_HPTH_SHIFT                  _MK_SHIFT_CONST(0)
+#define CCW_C2MC_HP_HPTH_FIELD                  (_MK_MASK_CONST(0xffffffff) << CCW_C2MC_HP_HPTH_SHIFT)
+#define CCW_C2MC_HP_HPTH_RANGE                  _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CCW_C2MC_HP_HPTH_ROW                    0
+
+
+// Packet CCW_C2MC_WCOAL
+#define CCW_C2MC_WCOAL_SIZE 32
+
+// write-coalescing time-out
+#define CCW_C2MC_WCOAL_WCOALTM_SHIFT                    _MK_SHIFT_CONST(0)
+#define CCW_C2MC_WCOAL_WCOALTM_FIELD                    (_MK_MASK_CONST(0xffffffff) << CCW_C2MC_WCOAL_WCOALTM_SHIFT)
+#define CCW_C2MC_WCOAL_WCOALTM_RANGE                    _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CCW_C2MC_WCOAL_WCOALTM_ROW                      0
+
+
+// Packet CCW_C2MC_HYST
+#define CCW_C2MC_HYST_SIZE 32
+
+#define CCW_C2MC_HYST_HYST_REQ_TM_SHIFT                 _MK_SHIFT_CONST(0)
+#define CCW_C2MC_HYST_HYST_REQ_TM_FIELD                 (_MK_MASK_CONST(0xfff) << CCW_C2MC_HYST_HYST_REQ_TM_SHIFT)
+#define CCW_C2MC_HYST_HYST_REQ_TM_RANGE                 _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(0)
+#define CCW_C2MC_HYST_HYST_REQ_TM_ROW                   0
+
+#define CCW_C2MC_HYST_HYST_REQ_TH_SHIFT                 _MK_SHIFT_CONST(28)
+#define CCW_C2MC_HYST_HYST_REQ_TH_FIELD                 (_MK_MASK_CONST(0x7) << CCW_C2MC_HYST_HYST_REQ_TH_SHIFT)
+#define CCW_C2MC_HYST_HYST_REQ_TH_RANGE                 _MK_SHIFT_CONST(30):_MK_SHIFT_CONST(28)
+#define CCW_C2MC_HYST_HYST_REQ_TH_ROW                   0
+
+#define CCW_C2MC_HYST_HYST_EN_SHIFT                     _MK_SHIFT_CONST(31)
+#define CCW_C2MC_HYST_HYST_EN_FIELD                     (_MK_MASK_CONST(0x1) << CCW_C2MC_HYST_HYST_EN_SHIFT)
+#define CCW_C2MC_HYST_HYST_EN_RANGE                     _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(31)
+#define CCW_C2MC_HYST_HYST_EN_ROW                       0
+
+
+// Packet SC_MCCIF_ASYNC
+#define SC_MCCIF_ASYNC_SIZE 4
+
+#define SC_MCCIF_ASYNC_RDCL_RDFAST_SHIFT                        _MK_SHIFT_CONST(0)
+#define SC_MCCIF_ASYNC_RDCL_RDFAST_FIELD                        (_MK_MASK_CONST(0x1) << SC_MCCIF_ASYNC_RDCL_RDFAST_SHIFT)
+#define SC_MCCIF_ASYNC_RDCL_RDFAST_RANGE                        _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define SC_MCCIF_ASYNC_RDCL_RDFAST_ROW                  0
+
+#define SC_MCCIF_ASYNC_RDMC_RDFAST_SHIFT                        _MK_SHIFT_CONST(1)
+#define SC_MCCIF_ASYNC_RDMC_RDFAST_FIELD                        (_MK_MASK_CONST(0x1) << SC_MCCIF_ASYNC_RDMC_RDFAST_SHIFT)
+#define SC_MCCIF_ASYNC_RDMC_RDFAST_RANGE                        _MK_SHIFT_CONST(1):_MK_SHIFT_CONST(1)
+#define SC_MCCIF_ASYNC_RDMC_RDFAST_ROW                  0
+
+#define SC_MCCIF_ASYNC_WRCL_MCLE2X_SHIFT                        _MK_SHIFT_CONST(2)
+#define SC_MCCIF_ASYNC_WRCL_MCLE2X_FIELD                        (_MK_MASK_CONST(0x1) << SC_MCCIF_ASYNC_WRCL_MCLE2X_SHIFT)
+#define SC_MCCIF_ASYNC_WRCL_MCLE2X_RANGE                        _MK_SHIFT_CONST(2):_MK_SHIFT_CONST(2)
+#define SC_MCCIF_ASYNC_WRCL_MCLE2X_ROW                  0
+
+#define SC_MCCIF_ASYNC_WRMC_CLLE2X_SHIFT                        _MK_SHIFT_CONST(3)
+#define SC_MCCIF_ASYNC_WRMC_CLLE2X_FIELD                        (_MK_MASK_CONST(0x1) << SC_MCCIF_ASYNC_WRMC_CLLE2X_SHIFT)
+#define SC_MCCIF_ASYNC_WRMC_CLLE2X_RANGE                        _MK_SHIFT_CONST(3):_MK_SHIFT_CONST(3)
+#define SC_MCCIF_ASYNC_WRMC_CLLE2X_ROW                  0
+
+
+// Register EMC_LL_ARB_CONFIG_0  // LOW-LATENCY arbiter configuration
+#define EMC_LL_ARB_CONFIG_0                     _MK_ADDR_CONST(0x144)
+#define EMC_LL_ARB_CONFIG_0_SECURE                      0x0
+#define EMC_LL_ARB_CONFIG_0_WORD_COUNT                  0x1
+#define EMC_LL_ARB_CONFIG_0_RESET_VAL                   _MK_MASK_CONST(0x2003)
+#define EMC_LL_ARB_CONFIG_0_RESET_MASK                  _MK_MASK_CONST(0x3f00f10f)
+#define EMC_LL_ARB_CONFIG_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define EMC_LL_ARB_CONFIG_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EMC_LL_ARB_CONFIG_0_READ_MASK                   _MK_MASK_CONST(0x3f00f10f)
+#define EMC_LL_ARB_CONFIG_0_WRITE_MASK                  _MK_MASK_CONST(0x3f00f10f)
+#define EMC_LL_ARB_CONFIG_0_DIE_OFF_EXP_SHIFT                   _MK_SHIFT_CONST(0)
+#define EMC_LL_ARB_CONFIG_0_DIE_OFF_EXP_FIELD                   (_MK_MASK_CONST(0xf) << EMC_LL_ARB_CONFIG_0_DIE_OFF_EXP_SHIFT)
+#define EMC_LL_ARB_CONFIG_0_DIE_OFF_EXP_RANGE                   3:0
+#define EMC_LL_ARB_CONFIG_0_DIE_OFF_EXP_WOFFSET                 0x0
+#define EMC_LL_ARB_CONFIG_0_DIE_OFF_EXP_DEFAULT                 _MK_MASK_CONST(0x3)
+#define EMC_LL_ARB_CONFIG_0_DIE_OFF_EXP_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define EMC_LL_ARB_CONFIG_0_DIE_OFF_EXP_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_LL_ARB_CONFIG_0_DIE_OFF_EXP_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define EMC_LL_ARB_CONFIG_0_ALLOW_IDLE_INSERT_SHIFT                     _MK_SHIFT_CONST(8)
+#define EMC_LL_ARB_CONFIG_0_ALLOW_IDLE_INSERT_FIELD                     (_MK_MASK_CONST(0x1) << EMC_LL_ARB_CONFIG_0_ALLOW_IDLE_INSERT_SHIFT)
+#define EMC_LL_ARB_CONFIG_0_ALLOW_IDLE_INSERT_RANGE                     8:8
+#define EMC_LL_ARB_CONFIG_0_ALLOW_IDLE_INSERT_WOFFSET                   0x0
+#define EMC_LL_ARB_CONFIG_0_ALLOW_IDLE_INSERT_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_LL_ARB_CONFIG_0_ALLOW_IDLE_INSERT_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define EMC_LL_ARB_CONFIG_0_ALLOW_IDLE_INSERT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_LL_ARB_CONFIG_0_ALLOW_IDLE_INSERT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_LL_ARB_CONFIG_0_ALLOW_IDLE_INSERT_INIT_ENUM                 DISABLED
+#define EMC_LL_ARB_CONFIG_0_ALLOW_IDLE_INSERT_DISABLED                  _MK_ENUM_CONST(0)
+#define EMC_LL_ARB_CONFIG_0_ALLOW_IDLE_INSERT_ENABLED                   _MK_ENUM_CONST(1)
+
+#define EMC_LL_ARB_CONFIG_0_MAX_LL_GREED_SHIFT                  _MK_SHIFT_CONST(12)
+#define EMC_LL_ARB_CONFIG_0_MAX_LL_GREED_FIELD                  (_MK_MASK_CONST(0xf) << EMC_LL_ARB_CONFIG_0_MAX_LL_GREED_SHIFT)
+#define EMC_LL_ARB_CONFIG_0_MAX_LL_GREED_RANGE                  15:12
+#define EMC_LL_ARB_CONFIG_0_MAX_LL_GREED_WOFFSET                        0x0
+#define EMC_LL_ARB_CONFIG_0_MAX_LL_GREED_DEFAULT                        _MK_MASK_CONST(0x2)
+#define EMC_LL_ARB_CONFIG_0_MAX_LL_GREED_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
+#define EMC_LL_ARB_CONFIG_0_MAX_LL_GREED_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_LL_ARB_CONFIG_0_MAX_LL_GREED_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// set to one to get AP15 behavior
+#define EMC_LL_ARB_CONFIG_0_LL_GREED_DIFF_BANK_DISABLE_SHIFT                    _MK_SHIFT_CONST(24)
+#define EMC_LL_ARB_CONFIG_0_LL_GREED_DIFF_BANK_DISABLE_FIELD                    (_MK_MASK_CONST(0x1) << EMC_LL_ARB_CONFIG_0_LL_GREED_DIFF_BANK_DISABLE_SHIFT)
+#define EMC_LL_ARB_CONFIG_0_LL_GREED_DIFF_BANK_DISABLE_RANGE                    24:24
+#define EMC_LL_ARB_CONFIG_0_LL_GREED_DIFF_BANK_DISABLE_WOFFSET                  0x0
+#define EMC_LL_ARB_CONFIG_0_LL_GREED_DIFF_BANK_DISABLE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_LL_ARB_CONFIG_0_LL_GREED_DIFF_BANK_DISABLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define EMC_LL_ARB_CONFIG_0_LL_GREED_DIFF_BANK_DISABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_LL_ARB_CONFIG_0_LL_GREED_DIFF_BANK_DISABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// set to one to get AP15 behavior
+#define EMC_LL_ARB_CONFIG_0_LL_GREED_DIFF_BANK_AFTER_DISABLE_SHIFT                      _MK_SHIFT_CONST(25)
+#define EMC_LL_ARB_CONFIG_0_LL_GREED_DIFF_BANK_AFTER_DISABLE_FIELD                      (_MK_MASK_CONST(0x1) << EMC_LL_ARB_CONFIG_0_LL_GREED_DIFF_BANK_AFTER_DISABLE_SHIFT)
+#define EMC_LL_ARB_CONFIG_0_LL_GREED_DIFF_BANK_AFTER_DISABLE_RANGE                      25:25
+#define EMC_LL_ARB_CONFIG_0_LL_GREED_DIFF_BANK_AFTER_DISABLE_WOFFSET                    0x0
+#define EMC_LL_ARB_CONFIG_0_LL_GREED_DIFF_BANK_AFTER_DISABLE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_LL_ARB_CONFIG_0_LL_GREED_DIFF_BANK_AFTER_DISABLE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define EMC_LL_ARB_CONFIG_0_LL_GREED_DIFF_BANK_AFTER_DISABLE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_LL_ARB_CONFIG_0_LL_GREED_DIFF_BANK_AFTER_DISABLE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// set to one to get AP15 behavior
+#define EMC_LL_ARB_CONFIG_0_LL_FORCE_INSERT_WR_DISABLE_SHIFT                    _MK_SHIFT_CONST(26)
+#define EMC_LL_ARB_CONFIG_0_LL_FORCE_INSERT_WR_DISABLE_FIELD                    (_MK_MASK_CONST(0x1) << EMC_LL_ARB_CONFIG_0_LL_FORCE_INSERT_WR_DISABLE_SHIFT)
+#define EMC_LL_ARB_CONFIG_0_LL_FORCE_INSERT_WR_DISABLE_RANGE                    26:26
+#define EMC_LL_ARB_CONFIG_0_LL_FORCE_INSERT_WR_DISABLE_WOFFSET                  0x0
+#define EMC_LL_ARB_CONFIG_0_LL_FORCE_INSERT_WR_DISABLE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_LL_ARB_CONFIG_0_LL_FORCE_INSERT_WR_DISABLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define EMC_LL_ARB_CONFIG_0_LL_FORCE_INSERT_WR_DISABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_LL_ARB_CONFIG_0_LL_FORCE_INSERT_WR_DISABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// set to one to get AP15 behavior
+#define EMC_LL_ARB_CONFIG_0_LL_INSERT_DIFF_BANK_BEFORE_DISABLE_SHIFT                    _MK_SHIFT_CONST(27)
+#define EMC_LL_ARB_CONFIG_0_LL_INSERT_DIFF_BANK_BEFORE_DISABLE_FIELD                    (_MK_MASK_CONST(0x1) << EMC_LL_ARB_CONFIG_0_LL_INSERT_DIFF_BANK_BEFORE_DISABLE_SHIFT)
+#define EMC_LL_ARB_CONFIG_0_LL_INSERT_DIFF_BANK_BEFORE_DISABLE_RANGE                    27:27
+#define EMC_LL_ARB_CONFIG_0_LL_INSERT_DIFF_BANK_BEFORE_DISABLE_WOFFSET                  0x0
+#define EMC_LL_ARB_CONFIG_0_LL_INSERT_DIFF_BANK_BEFORE_DISABLE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_LL_ARB_CONFIG_0_LL_INSERT_DIFF_BANK_BEFORE_DISABLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define EMC_LL_ARB_CONFIG_0_LL_INSERT_DIFF_BANK_BEFORE_DISABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_LL_ARB_CONFIG_0_LL_INSERT_DIFF_BANK_BEFORE_DISABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// set to one to get AP15 behavior
+#define EMC_LL_ARB_CONFIG_0_LL_INSERT_DIFF_BANK_AFTER_TOGGLE_SHIFT                      _MK_SHIFT_CONST(28)
+#define EMC_LL_ARB_CONFIG_0_LL_INSERT_DIFF_BANK_AFTER_TOGGLE_FIELD                      (_MK_MASK_CONST(0x1) << EMC_LL_ARB_CONFIG_0_LL_INSERT_DIFF_BANK_AFTER_TOGGLE_SHIFT)
+#define EMC_LL_ARB_CONFIG_0_LL_INSERT_DIFF_BANK_AFTER_TOGGLE_RANGE                      28:28
+#define EMC_LL_ARB_CONFIG_0_LL_INSERT_DIFF_BANK_AFTER_TOGGLE_WOFFSET                    0x0
+#define EMC_LL_ARB_CONFIG_0_LL_INSERT_DIFF_BANK_AFTER_TOGGLE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_LL_ARB_CONFIG_0_LL_INSERT_DIFF_BANK_AFTER_TOGGLE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define EMC_LL_ARB_CONFIG_0_LL_INSERT_DIFF_BANK_AFTER_TOGGLE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_LL_ARB_CONFIG_0_LL_INSERT_DIFF_BANK_AFTER_TOGGLE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// set to zero to get AP15 behavior
+#define EMC_LL_ARB_CONFIG_0_LL_INSERT_DIFF_BANK_AFTER_REMOVE_SHIFT                      _MK_SHIFT_CONST(29)
+#define EMC_LL_ARB_CONFIG_0_LL_INSERT_DIFF_BANK_AFTER_REMOVE_FIELD                      (_MK_MASK_CONST(0x1) << EMC_LL_ARB_CONFIG_0_LL_INSERT_DIFF_BANK_AFTER_REMOVE_SHIFT)
+#define EMC_LL_ARB_CONFIG_0_LL_INSERT_DIFF_BANK_AFTER_REMOVE_RANGE                      29:29
+#define EMC_LL_ARB_CONFIG_0_LL_INSERT_DIFF_BANK_AFTER_REMOVE_WOFFSET                    0x0
+#define EMC_LL_ARB_CONFIG_0_LL_INSERT_DIFF_BANK_AFTER_REMOVE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_LL_ARB_CONFIG_0_LL_INSERT_DIFF_BANK_AFTER_REMOVE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define EMC_LL_ARB_CONFIG_0_LL_INSERT_DIFF_BANK_AFTER_REMOVE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_LL_ARB_CONFIG_0_LL_INSERT_DIFF_BANK_AFTER_REMOVE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register EMC_T_MIN_CRITICAL_HP_0  // LOW-LATENCY arbiter configuration
+#define EMC_T_MIN_CRITICAL_HP_0                 _MK_ADDR_CONST(0x148)
+#define EMC_T_MIN_CRITICAL_HP_0_SECURE                  0x0
+#define EMC_T_MIN_CRITICAL_HP_0_WORD_COUNT                      0x1
+#define EMC_T_MIN_CRITICAL_HP_0_RESET_VAL                       _MK_MASK_CONST(0xa080600)
+#define EMC_T_MIN_CRITICAL_HP_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EMC_T_MIN_CRITICAL_HP_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EMC_T_MIN_CRITICAL_HP_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_T_MIN_CRITICAL_HP_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EMC_T_MIN_CRITICAL_HP_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_0_SHIFT                   _MK_SHIFT_CONST(0)
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_0_FIELD                   (_MK_MASK_CONST(0xff) << EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_0_SHIFT)
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_0_RANGE                   7:0
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_0_WOFFSET                 0x0
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_0_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_1_SHIFT                   _MK_SHIFT_CONST(8)
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_1_FIELD                   (_MK_MASK_CONST(0xff) << EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_1_SHIFT)
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_1_RANGE                   15:8
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_1_WOFFSET                 0x0
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_1_DEFAULT                 _MK_MASK_CONST(0x6)
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_1_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_2_SHIFT                   _MK_SHIFT_CONST(16)
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_2_FIELD                   (_MK_MASK_CONST(0xff) << EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_2_SHIFT)
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_2_RANGE                   23:16
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_2_WOFFSET                 0x0
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_2_DEFAULT                 _MK_MASK_CONST(0x8)
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_2_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_3_SHIFT                   _MK_SHIFT_CONST(24)
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_3_FIELD                   (_MK_MASK_CONST(0xff) << EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_3_SHIFT)
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_3_RANGE                   31:24
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_3_WOFFSET                 0x0
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_3_DEFAULT                 _MK_MASK_CONST(0xa)
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_3_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_3_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_3_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register EMC_T_MIN_CRITICAL_TIMEOUT_0  // LOW-LATENCY arbiter configuration
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0                    _MK_ADDR_CONST(0x14c)
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_SECURE                     0x0
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_WORD_COUNT                         0x1
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_RESET_VAL                  _MK_MASK_CONST(0xa080600)
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_0_SHIFT                 _MK_SHIFT_CONST(0)
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_0_FIELD                 (_MK_MASK_CONST(0xff) << EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_0_SHIFT)
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_0_RANGE                 7:0
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_0_WOFFSET                       0x0
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_0_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_0_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_1_SHIFT                 _MK_SHIFT_CONST(8)
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_1_FIELD                 (_MK_MASK_CONST(0xff) << EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_1_SHIFT)
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_1_RANGE                 15:8
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_1_WOFFSET                       0x0
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_1_DEFAULT                       _MK_MASK_CONST(0x6)
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_1_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_2_SHIFT                 _MK_SHIFT_CONST(16)
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_2_FIELD                 (_MK_MASK_CONST(0xff) << EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_2_SHIFT)
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_2_RANGE                 23:16
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_2_WOFFSET                       0x0
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_2_DEFAULT                       _MK_MASK_CONST(0x8)
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_2_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_3_SHIFT                 _MK_SHIFT_CONST(24)
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_3_FIELD                 (_MK_MASK_CONST(0xff) << EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_3_SHIFT)
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_3_RANGE                 31:24
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_3_WOFFSET                       0x0
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_3_DEFAULT                       _MK_MASK_CONST(0xa)
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_3_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EMC_T_MIN_LOAD_0  // LOW-LATENCY arbiter configuration
+#define EMC_T_MIN_LOAD_0                        _MK_ADDR_CONST(0x150)
+#define EMC_T_MIN_LOAD_0_SECURE                         0x0
+#define EMC_T_MIN_LOAD_0_WORD_COUNT                     0x1
+#define EMC_T_MIN_LOAD_0_RESET_VAL                      _MK_MASK_CONST(0x8040200)
+#define EMC_T_MIN_LOAD_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
+#define EMC_T_MIN_LOAD_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define EMC_T_MIN_LOAD_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_T_MIN_LOAD_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EMC_T_MIN_LOAD_0_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_0_SHIFT                     _MK_SHIFT_CONST(0)
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_0_FIELD                     (_MK_MASK_CONST(0xff) << EMC_T_MIN_LOAD_0_T_MIN_LOAD_0_SHIFT)
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_0_RANGE                     7:0
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_0_WOFFSET                   0x0
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_0_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_0_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_1_SHIFT                     _MK_SHIFT_CONST(8)
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_1_FIELD                     (_MK_MASK_CONST(0xff) << EMC_T_MIN_LOAD_0_T_MIN_LOAD_1_SHIFT)
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_1_RANGE                     15:8
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_1_WOFFSET                   0x0
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_1_DEFAULT                   _MK_MASK_CONST(0x2)
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_1_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_2_SHIFT                     _MK_SHIFT_CONST(16)
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_2_FIELD                     (_MK_MASK_CONST(0xff) << EMC_T_MIN_LOAD_0_T_MIN_LOAD_2_SHIFT)
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_2_RANGE                     23:16
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_2_WOFFSET                   0x0
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_2_DEFAULT                   _MK_MASK_CONST(0x4)
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_2_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_3_SHIFT                     _MK_SHIFT_CONST(24)
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_3_FIELD                     (_MK_MASK_CONST(0xff) << EMC_T_MIN_LOAD_0_T_MIN_LOAD_3_SHIFT)
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_3_RANGE                     31:24
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_3_WOFFSET                   0x0
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_3_DEFAULT                   _MK_MASK_CONST(0x8)
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_3_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_3_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_3_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EMC_T_MAX_CRITICAL_HP_0  // LOW-LATENCY arbiter configuration
+#define EMC_T_MAX_CRITICAL_HP_0                 _MK_ADDR_CONST(0x154)
+#define EMC_T_MAX_CRITICAL_HP_0_SECURE                  0x0
+#define EMC_T_MAX_CRITICAL_HP_0_WORD_COUNT                      0x1
+#define EMC_T_MAX_CRITICAL_HP_0_RESET_VAL                       _MK_MASK_CONST(0xb0a0901)
+#define EMC_T_MAX_CRITICAL_HP_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EMC_T_MAX_CRITICAL_HP_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EMC_T_MAX_CRITICAL_HP_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_T_MAX_CRITICAL_HP_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EMC_T_MAX_CRITICAL_HP_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_0_SHIFT                   _MK_SHIFT_CONST(0)
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_0_FIELD                   (_MK_MASK_CONST(0xff) << EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_0_SHIFT)
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_0_RANGE                   7:0
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_0_WOFFSET                 0x0
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_0_DEFAULT                 _MK_MASK_CONST(0x1)
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_0_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_1_SHIFT                   _MK_SHIFT_CONST(8)
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_1_FIELD                   (_MK_MASK_CONST(0xff) << EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_1_SHIFT)
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_1_RANGE                   15:8
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_1_WOFFSET                 0x0
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_1_DEFAULT                 _MK_MASK_CONST(0x9)
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_1_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_2_SHIFT                   _MK_SHIFT_CONST(16)
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_2_FIELD                   (_MK_MASK_CONST(0xff) << EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_2_SHIFT)
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_2_RANGE                   23:16
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_2_WOFFSET                 0x0
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_2_DEFAULT                 _MK_MASK_CONST(0xa)
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_2_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_3_SHIFT                   _MK_SHIFT_CONST(24)
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_3_FIELD                   (_MK_MASK_CONST(0xff) << EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_3_SHIFT)
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_3_RANGE                   31:24
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_3_WOFFSET                 0x0
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_3_DEFAULT                 _MK_MASK_CONST(0xb)
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_3_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_3_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_3_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register EMC_T_MAX_CRITICAL_TIMEOUT_0  // LOW-LATENCY arbiter configuration
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0                    _MK_ADDR_CONST(0x158)
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_SECURE                     0x0
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_WORD_COUNT                         0x1
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_RESET_VAL                  _MK_MASK_CONST(0xb0a0901)
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_0_SHIFT                 _MK_SHIFT_CONST(0)
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_0_FIELD                 (_MK_MASK_CONST(0xff) << EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_0_SHIFT)
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_0_RANGE                 7:0
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_0_WOFFSET                       0x0
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_0_DEFAULT                       _MK_MASK_CONST(0x1)
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_0_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_1_SHIFT                 _MK_SHIFT_CONST(8)
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_1_FIELD                 (_MK_MASK_CONST(0xff) << EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_1_SHIFT)
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_1_RANGE                 15:8
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_1_WOFFSET                       0x0
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_1_DEFAULT                       _MK_MASK_CONST(0x9)
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_1_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_2_SHIFT                 _MK_SHIFT_CONST(16)
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_2_FIELD                 (_MK_MASK_CONST(0xff) << EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_2_SHIFT)
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_2_RANGE                 23:16
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_2_WOFFSET                       0x0
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_2_DEFAULT                       _MK_MASK_CONST(0xa)
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_2_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_3_SHIFT                 _MK_SHIFT_CONST(24)
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_3_FIELD                 (_MK_MASK_CONST(0xff) << EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_3_SHIFT)
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_3_RANGE                 31:24
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_3_WOFFSET                       0x0
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_3_DEFAULT                       _MK_MASK_CONST(0xb)
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_3_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EMC_T_MAX_LOAD_0  // LOW-LATENCY arbiter configuration
+#define EMC_T_MAX_LOAD_0                        _MK_ADDR_CONST(0x15c)
+#define EMC_T_MAX_LOAD_0_SECURE                         0x0
+#define EMC_T_MAX_LOAD_0_WORD_COUNT                     0x1
+#define EMC_T_MAX_LOAD_0_RESET_VAL                      _MK_MASK_CONST(0x20100804)
+#define EMC_T_MAX_LOAD_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
+#define EMC_T_MAX_LOAD_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define EMC_T_MAX_LOAD_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_T_MAX_LOAD_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EMC_T_MAX_LOAD_0_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_0_SHIFT                     _MK_SHIFT_CONST(0)
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_0_FIELD                     (_MK_MASK_CONST(0xff) << EMC_T_MAX_LOAD_0_T_MAX_LOAD_0_SHIFT)
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_0_RANGE                     7:0
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_0_WOFFSET                   0x0
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_0_DEFAULT                   _MK_MASK_CONST(0x4)
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_0_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_1_SHIFT                     _MK_SHIFT_CONST(8)
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_1_FIELD                     (_MK_MASK_CONST(0xff) << EMC_T_MAX_LOAD_0_T_MAX_LOAD_1_SHIFT)
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_1_RANGE                     15:8
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_1_WOFFSET                   0x0
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_1_DEFAULT                   _MK_MASK_CONST(0x8)
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_1_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_2_SHIFT                     _MK_SHIFT_CONST(16)
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_2_FIELD                     (_MK_MASK_CONST(0xff) << EMC_T_MAX_LOAD_0_T_MAX_LOAD_2_SHIFT)
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_2_RANGE                     23:16
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_2_WOFFSET                   0x0
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_2_DEFAULT                   _MK_MASK_CONST(0x10)
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_2_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_3_SHIFT                     _MK_SHIFT_CONST(24)
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_3_FIELD                     (_MK_MASK_CONST(0xff) << EMC_T_MAX_LOAD_0_T_MAX_LOAD_3_SHIFT)
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_3_RANGE                     31:24
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_3_WOFFSET                   0x0
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_3_DEFAULT                   _MK_MASK_CONST(0x20)
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_3_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_3_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_3_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EMC_STAT_CONTROL_0  
+#define EMC_STAT_CONTROL_0                      _MK_ADDR_CONST(0x160)
+#define EMC_STAT_CONTROL_0_SECURE                       0x0
+#define EMC_STAT_CONTROL_0_WORD_COUNT                   0x1
+#define EMC_STAT_CONTROL_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_CONTROL_0_RESET_MASK                   _MK_MASK_CONST(0x30307)
+#define EMC_STAT_CONTROL_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_CONTROL_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_CONTROL_0_READ_MASK                    _MK_MASK_CONST(0x30307)
+#define EMC_STAT_CONTROL_0_WRITE_MASK                   _MK_MASK_CONST(0x30307)
+#define EMC_STAT_CONTROL_0_LLMC_GATHER_SHIFT                    _MK_SHIFT_CONST(0)
+#define EMC_STAT_CONTROL_0_LLMC_GATHER_FIELD                    (_MK_MASK_CONST(0x7) << EMC_STAT_CONTROL_0_LLMC_GATHER_SHIFT)
+#define EMC_STAT_CONTROL_0_LLMC_GATHER_RANGE                    2:0
+#define EMC_STAT_CONTROL_0_LLMC_GATHER_WOFFSET                  0x0
+#define EMC_STAT_CONTROL_0_LLMC_GATHER_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_CONTROL_0_LLMC_GATHER_DEFAULT_MASK                     _MK_MASK_CONST(0x7)
+#define EMC_STAT_CONTROL_0_LLMC_GATHER_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_CONTROL_0_LLMC_GATHER_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_CONTROL_0_LLMC_GATHER_INIT_ENUM                        RST
+#define EMC_STAT_CONTROL_0_LLMC_GATHER_RST                      _MK_ENUM_CONST(0)
+#define EMC_STAT_CONTROL_0_LLMC_GATHER_CLEAR                    _MK_ENUM_CONST(1)
+#define EMC_STAT_CONTROL_0_LLMC_GATHER_DISABLE                  _MK_ENUM_CONST(2)
+#define EMC_STAT_CONTROL_0_LLMC_GATHER_ENABLE                   _MK_ENUM_CONST(3)
+#define EMC_STAT_CONTROL_0_LLMC_GATHER_SLAVE_TO_MC                      _MK_ENUM_CONST(4)
+
+#define EMC_STAT_CONTROL_0_PWR_GATHER_SHIFT                     _MK_SHIFT_CONST(8)
+#define EMC_STAT_CONTROL_0_PWR_GATHER_FIELD                     (_MK_MASK_CONST(0x3) << EMC_STAT_CONTROL_0_PWR_GATHER_SHIFT)
+#define EMC_STAT_CONTROL_0_PWR_GATHER_RANGE                     9:8
+#define EMC_STAT_CONTROL_0_PWR_GATHER_WOFFSET                   0x0
+#define EMC_STAT_CONTROL_0_PWR_GATHER_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_STAT_CONTROL_0_PWR_GATHER_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define EMC_STAT_CONTROL_0_PWR_GATHER_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_STAT_CONTROL_0_PWR_GATHER_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_STAT_CONTROL_0_PWR_GATHER_INIT_ENUM                 RST
+#define EMC_STAT_CONTROL_0_PWR_GATHER_RST                       _MK_ENUM_CONST(0)
+#define EMC_STAT_CONTROL_0_PWR_GATHER_CLEAR                     _MK_ENUM_CONST(1)
+#define EMC_STAT_CONTROL_0_PWR_GATHER_DISABLE                   _MK_ENUM_CONST(2)
+#define EMC_STAT_CONTROL_0_PWR_GATHER_ENABLE                    _MK_ENUM_CONST(3)
+
+#define EMC_STAT_CONTROL_0_DRAM_GATHER_SHIFT                    _MK_SHIFT_CONST(16)
+#define EMC_STAT_CONTROL_0_DRAM_GATHER_FIELD                    (_MK_MASK_CONST(0x3) << EMC_STAT_CONTROL_0_DRAM_GATHER_SHIFT)
+#define EMC_STAT_CONTROL_0_DRAM_GATHER_RANGE                    17:16
+#define EMC_STAT_CONTROL_0_DRAM_GATHER_WOFFSET                  0x0
+#define EMC_STAT_CONTROL_0_DRAM_GATHER_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_CONTROL_0_DRAM_GATHER_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define EMC_STAT_CONTROL_0_DRAM_GATHER_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_CONTROL_0_DRAM_GATHER_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_CONTROL_0_DRAM_GATHER_INIT_ENUM                        RST
+#define EMC_STAT_CONTROL_0_DRAM_GATHER_RST                      _MK_ENUM_CONST(0)
+#define EMC_STAT_CONTROL_0_DRAM_GATHER_CLEAR                    _MK_ENUM_CONST(1)
+#define EMC_STAT_CONTROL_0_DRAM_GATHER_DISABLE                  _MK_ENUM_CONST(2)
+#define EMC_STAT_CONTROL_0_DRAM_GATHER_ENABLE                   _MK_ENUM_CONST(3)
+
+
+// Register EMC_STAT_STATUS_0  
+#define EMC_STAT_STATUS_0                       _MK_ADDR_CONST(0x164)
+#define EMC_STAT_STATUS_0_SECURE                        0x0
+#define EMC_STAT_STATUS_0_WORD_COUNT                    0x1
+#define EMC_STAT_STATUS_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_STATUS_0_RESET_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_STATUS_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define EMC_STAT_STATUS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_STATUS_0_READ_MASK                     _MK_MASK_CONST(0x10101)
+#define EMC_STAT_STATUS_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_STATUS_0_LLMC_LIMIT_SHIFT                      _MK_SHIFT_CONST(0)
+#define EMC_STAT_STATUS_0_LLMC_LIMIT_FIELD                      (_MK_MASK_CONST(0x1) << EMC_STAT_STATUS_0_LLMC_LIMIT_SHIFT)
+#define EMC_STAT_STATUS_0_LLMC_LIMIT_RANGE                      0:0
+#define EMC_STAT_STATUS_0_LLMC_LIMIT_WOFFSET                    0x0
+#define EMC_STAT_STATUS_0_LLMC_LIMIT_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_STATUS_0_LLMC_LIMIT_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_STATUS_0_LLMC_LIMIT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_STAT_STATUS_0_LLMC_LIMIT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define EMC_STAT_STATUS_0_PWR_LIMIT_SHIFT                       _MK_SHIFT_CONST(8)
+#define EMC_STAT_STATUS_0_PWR_LIMIT_FIELD                       (_MK_MASK_CONST(0x1) << EMC_STAT_STATUS_0_PWR_LIMIT_SHIFT)
+#define EMC_STAT_STATUS_0_PWR_LIMIT_RANGE                       8:8
+#define EMC_STAT_STATUS_0_PWR_LIMIT_WOFFSET                     0x0
+#define EMC_STAT_STATUS_0_PWR_LIMIT_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_STATUS_0_PWR_LIMIT_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_STAT_STATUS_0_PWR_LIMIT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_STATUS_0_PWR_LIMIT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define EMC_STAT_STATUS_0_DRAM_LIMIT_SHIFT                      _MK_SHIFT_CONST(16)
+#define EMC_STAT_STATUS_0_DRAM_LIMIT_FIELD                      (_MK_MASK_CONST(0x1) << EMC_STAT_STATUS_0_DRAM_LIMIT_SHIFT)
+#define EMC_STAT_STATUS_0_DRAM_LIMIT_RANGE                      16:16
+#define EMC_STAT_STATUS_0_DRAM_LIMIT_WOFFSET                    0x0
+#define EMC_STAT_STATUS_0_DRAM_LIMIT_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_STATUS_0_DRAM_LIMIT_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_STATUS_0_DRAM_LIMIT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_STAT_STATUS_0_DRAM_LIMIT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register EMC_STAT_LLMC_ADDR_LOW_0  
+#define EMC_STAT_LLMC_ADDR_LOW_0                        _MK_ADDR_CONST(0x168)
+#define EMC_STAT_LLMC_ADDR_LOW_0_SECURE                         0x0
+#define EMC_STAT_LLMC_ADDR_LOW_0_WORD_COUNT                     0x1
+#define EMC_STAT_LLMC_ADDR_LOW_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_ADDR_LOW_0_RESET_MASK                     _MK_MASK_CONST(0x3ffffff0)
+#define EMC_STAT_LLMC_ADDR_LOW_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_ADDR_LOW_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_ADDR_LOW_0_READ_MASK                      _MK_MASK_CONST(0x3ffffff0)
+#define EMC_STAT_LLMC_ADDR_LOW_0_WRITE_MASK                     _MK_MASK_CONST(0x3ffffff0)
+#define EMC_STAT_LLMC_ADDR_LOW_0_LLMC_ADDR_LOW_SHIFT                    _MK_SHIFT_CONST(4)
+#define EMC_STAT_LLMC_ADDR_LOW_0_LLMC_ADDR_LOW_FIELD                    (_MK_MASK_CONST(0x3ffffff) << EMC_STAT_LLMC_ADDR_LOW_0_LLMC_ADDR_LOW_SHIFT)
+#define EMC_STAT_LLMC_ADDR_LOW_0_LLMC_ADDR_LOW_RANGE                    29:4
+#define EMC_STAT_LLMC_ADDR_LOW_0_LLMC_ADDR_LOW_WOFFSET                  0x0
+#define EMC_STAT_LLMC_ADDR_LOW_0_LLMC_ADDR_LOW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_ADDR_LOW_0_LLMC_ADDR_LOW_DEFAULT_MASK                     _MK_MASK_CONST(0x3ffffff)
+#define EMC_STAT_LLMC_ADDR_LOW_0_LLMC_ADDR_LOW_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_ADDR_LOW_0_LLMC_ADDR_LOW_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register EMC_STAT_LLMC_ADDR_HIGH_0  
+#define EMC_STAT_LLMC_ADDR_HIGH_0                       _MK_ADDR_CONST(0x16c)
+#define EMC_STAT_LLMC_ADDR_HIGH_0_SECURE                        0x0
+#define EMC_STAT_LLMC_ADDR_HIGH_0_WORD_COUNT                    0x1
+#define EMC_STAT_LLMC_ADDR_HIGH_0_RESET_VAL                     _MK_MASK_CONST(0x3ffffff0)
+#define EMC_STAT_LLMC_ADDR_HIGH_0_RESET_MASK                    _MK_MASK_CONST(0x3ffffff0)
+#define EMC_STAT_LLMC_ADDR_HIGH_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_ADDR_HIGH_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_ADDR_HIGH_0_READ_MASK                     _MK_MASK_CONST(0x3ffffff0)
+#define EMC_STAT_LLMC_ADDR_HIGH_0_WRITE_MASK                    _MK_MASK_CONST(0x3ffffff0)
+#define EMC_STAT_LLMC_ADDR_HIGH_0_LLMC_ADDR_HIGH_SHIFT                  _MK_SHIFT_CONST(4)
+#define EMC_STAT_LLMC_ADDR_HIGH_0_LLMC_ADDR_HIGH_FIELD                  (_MK_MASK_CONST(0x3ffffff) << EMC_STAT_LLMC_ADDR_HIGH_0_LLMC_ADDR_HIGH_SHIFT)
+#define EMC_STAT_LLMC_ADDR_HIGH_0_LLMC_ADDR_HIGH_RANGE                  29:4
+#define EMC_STAT_LLMC_ADDR_HIGH_0_LLMC_ADDR_HIGH_WOFFSET                        0x0
+#define EMC_STAT_LLMC_ADDR_HIGH_0_LLMC_ADDR_HIGH_DEFAULT                        _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_LLMC_ADDR_HIGH_0_LLMC_ADDR_HIGH_DEFAULT_MASK                   _MK_MASK_CONST(0x3ffffff)
+#define EMC_STAT_LLMC_ADDR_HIGH_0_LLMC_ADDR_HIGH_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_ADDR_HIGH_0_LLMC_ADDR_HIGH_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_ADDR_HIGH_0_LLMC_ADDR_HIGH_INIT_ENUM                      -1
+
+
+// Register EMC_STAT_LLMC_CLOCK_LIMIT_0  
+#define EMC_STAT_LLMC_CLOCK_LIMIT_0                     _MK_ADDR_CONST(0x170)
+#define EMC_STAT_LLMC_CLOCK_LIMIT_0_SECURE                      0x0
+#define EMC_STAT_LLMC_CLOCK_LIMIT_0_WORD_COUNT                  0x1
+#define EMC_STAT_LLMC_CLOCK_LIMIT_0_RESET_VAL                   _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_LLMC_CLOCK_LIMIT_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_LLMC_CLOCK_LIMIT_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_CLOCK_LIMIT_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_CLOCK_LIMIT_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_LLMC_CLOCK_LIMIT_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_LLMC_CLOCK_LIMIT_0_LLMC_CLOCK_LIMIT_SHIFT                      _MK_SHIFT_CONST(0)
+#define EMC_STAT_LLMC_CLOCK_LIMIT_0_LLMC_CLOCK_LIMIT_FIELD                      (_MK_MASK_CONST(0xffffffff) << EMC_STAT_LLMC_CLOCK_LIMIT_0_LLMC_CLOCK_LIMIT_SHIFT)
+#define EMC_STAT_LLMC_CLOCK_LIMIT_0_LLMC_CLOCK_LIMIT_RANGE                      31:0
+#define EMC_STAT_LLMC_CLOCK_LIMIT_0_LLMC_CLOCK_LIMIT_WOFFSET                    0x0
+#define EMC_STAT_LLMC_CLOCK_LIMIT_0_LLMC_CLOCK_LIMIT_DEFAULT                    _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_LLMC_CLOCK_LIMIT_0_LLMC_CLOCK_LIMIT_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_LLMC_CLOCK_LIMIT_0_LLMC_CLOCK_LIMIT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_CLOCK_LIMIT_0_LLMC_CLOCK_LIMIT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_CLOCK_LIMIT_0_LLMC_CLOCK_LIMIT_INIT_ENUM                  -1
+
+
+// Register EMC_STAT_LLMC_CLOCKS_0  
+#define EMC_STAT_LLMC_CLOCKS_0                  _MK_ADDR_CONST(0x174)
+#define EMC_STAT_LLMC_CLOCKS_0_SECURE                   0x0
+#define EMC_STAT_LLMC_CLOCKS_0_WORD_COUNT                       0x1
+#define EMC_STAT_LLMC_CLOCKS_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_CLOCKS_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_CLOCKS_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_CLOCKS_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_CLOCKS_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_LLMC_CLOCKS_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_CLOCKS_0_LLMC_CLOCKS_SHIFT                        _MK_SHIFT_CONST(0)
+#define EMC_STAT_LLMC_CLOCKS_0_LLMC_CLOCKS_FIELD                        (_MK_MASK_CONST(0xffffffff) << EMC_STAT_LLMC_CLOCKS_0_LLMC_CLOCKS_SHIFT)
+#define EMC_STAT_LLMC_CLOCKS_0_LLMC_CLOCKS_RANGE                        31:0
+#define EMC_STAT_LLMC_CLOCKS_0_LLMC_CLOCKS_WOFFSET                      0x0
+#define EMC_STAT_LLMC_CLOCKS_0_LLMC_CLOCKS_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_CLOCKS_0_LLMC_CLOCKS_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_CLOCKS_0_LLMC_CLOCKS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_CLOCKS_0_LLMC_CLOCKS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Packet AREMC_STAT_CONTROL
+#define AREMC_STAT_CONTROL_SIZE 28
+
+#define AREMC_STAT_CONTROL_MODE_SHIFT                   _MK_SHIFT_CONST(0)
+#define AREMC_STAT_CONTROL_MODE_FIELD                   (_MK_MASK_CONST(0x3) << AREMC_STAT_CONTROL_MODE_SHIFT)
+#define AREMC_STAT_CONTROL_MODE_RANGE                   _MK_SHIFT_CONST(1):_MK_SHIFT_CONST(0)
+#define AREMC_STAT_CONTROL_MODE_ROW                     0
+#define AREMC_STAT_CONTROL_MODE_BANDWIDTH                       _MK_ENUM_CONST(0)
+#define AREMC_STAT_CONTROL_MODE_LATENCY_AVG                     _MK_ENUM_CONST(1)
+#define AREMC_STAT_CONTROL_MODE_LATENCY_HISTO                   _MK_ENUM_CONST(2)
+
+#define AREMC_STAT_CONTROL_SKIP_SHIFT                   _MK_SHIFT_CONST(4)
+#define AREMC_STAT_CONTROL_SKIP_FIELD                   (_MK_MASK_CONST(0x7) << AREMC_STAT_CONTROL_SKIP_SHIFT)
+#define AREMC_STAT_CONTROL_SKIP_RANGE                   _MK_SHIFT_CONST(6):_MK_SHIFT_CONST(4)
+#define AREMC_STAT_CONTROL_SKIP_ROW                     0
+
+#define AREMC_STAT_CONTROL_CLIENT_TYPE_SHIFT                    _MK_SHIFT_CONST(8)
+#define AREMC_STAT_CONTROL_CLIENT_TYPE_FIELD                    (_MK_MASK_CONST(0x1) << AREMC_STAT_CONTROL_CLIENT_TYPE_SHIFT)
+#define AREMC_STAT_CONTROL_CLIENT_TYPE_RANGE                    _MK_SHIFT_CONST(8):_MK_SHIFT_CONST(8)
+#define AREMC_STAT_CONTROL_CLIENT_TYPE_ROW                      0
+#define AREMC_STAT_CONTROL_CLIENT_TYPE_MPCORER                  _MK_ENUM_CONST(0)
+
+#define AREMC_STAT_CONTROL_EVENT_SHIFT                  _MK_SHIFT_CONST(16)
+#define AREMC_STAT_CONTROL_EVENT_FIELD                  (_MK_MASK_CONST(0x1) << AREMC_STAT_CONTROL_EVENT_SHIFT)
+#define AREMC_STAT_CONTROL_EVENT_RANGE                  _MK_SHIFT_CONST(16):_MK_SHIFT_CONST(16)
+#define AREMC_STAT_CONTROL_EVENT_ROW                    0
+#define AREMC_STAT_CONTROL_EVENT_QUALIFIED                      _MK_ENUM_CONST(0)
+
+#define AREMC_STAT_CONTROL_FILTER_CLIENT_SHIFT                  _MK_SHIFT_CONST(26)
+#define AREMC_STAT_CONTROL_FILTER_CLIENT_FIELD                  (_MK_MASK_CONST(0x1) << AREMC_STAT_CONTROL_FILTER_CLIENT_SHIFT)
+#define AREMC_STAT_CONTROL_FILTER_CLIENT_RANGE                  _MK_SHIFT_CONST(26):_MK_SHIFT_CONST(26)
+#define AREMC_STAT_CONTROL_FILTER_CLIENT_ROW                    0
+#define AREMC_STAT_CONTROL_FILTER_CLIENT_DISABLE                        _MK_ENUM_CONST(0)
+#define AREMC_STAT_CONTROL_FILTER_CLIENT_ENABLE                 _MK_ENUM_CONST(1)
+
+#define AREMC_STAT_CONTROL_FILTER_ADDR_SHIFT                    _MK_SHIFT_CONST(27)
+#define AREMC_STAT_CONTROL_FILTER_ADDR_FIELD                    (_MK_MASK_CONST(0x1) << AREMC_STAT_CONTROL_FILTER_ADDR_SHIFT)
+#define AREMC_STAT_CONTROL_FILTER_ADDR_RANGE                    _MK_SHIFT_CONST(27):_MK_SHIFT_CONST(27)
+#define AREMC_STAT_CONTROL_FILTER_ADDR_ROW                      0
+#define AREMC_STAT_CONTROL_FILTER_ADDR_DISABLE                  _MK_ENUM_CONST(0)
+#define AREMC_STAT_CONTROL_FILTER_ADDR_ENABLE                   _MK_ENUM_CONST(1)
+
+
+// Register EMC_STAT_LLMC_CONTROL_0_0  
+#define EMC_STAT_LLMC_CONTROL_0_0                       _MK_ADDR_CONST(0x178)
+#define EMC_STAT_LLMC_CONTROL_0_0_SECURE                        0x0
+#define EMC_STAT_LLMC_CONTROL_0_0_WORD_COUNT                    0x1
+#define EMC_STAT_LLMC_CONTROL_0_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_CONTROL_0_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_LLMC_CONTROL_0_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_CONTROL_0_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_CONTROL_0_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_LLMC_CONTROL_0_0_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_LLMC_CONTROL_0_0_LLMC_CONTROL_0_SHIFT                  _MK_SHIFT_CONST(0)
+#define EMC_STAT_LLMC_CONTROL_0_0_LLMC_CONTROL_0_FIELD                  (_MK_MASK_CONST(0xffffffff) << EMC_STAT_LLMC_CONTROL_0_0_LLMC_CONTROL_0_SHIFT)
+#define EMC_STAT_LLMC_CONTROL_0_0_LLMC_CONTROL_0_RANGE                  31:0
+#define EMC_STAT_LLMC_CONTROL_0_0_LLMC_CONTROL_0_WOFFSET                        0x0
+#define EMC_STAT_LLMC_CONTROL_0_0_LLMC_CONTROL_0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_CONTROL_0_0_LLMC_CONTROL_0_DEFAULT_MASK                   _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_LLMC_CONTROL_0_0_LLMC_CONTROL_0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_CONTROL_0_0_LLMC_CONTROL_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Reserved address 380 [0x17c] 
+
+// Packet AREMC_STAT_HIST_LIMIT
+#define AREMC_STAT_HIST_LIMIT_SIZE 32
+
+#define AREMC_STAT_HIST_LIMIT_LOW_SHIFT                 _MK_SHIFT_CONST(0)
+#define AREMC_STAT_HIST_LIMIT_LOW_FIELD                 (_MK_MASK_CONST(0xffff) << AREMC_STAT_HIST_LIMIT_LOW_SHIFT)
+#define AREMC_STAT_HIST_LIMIT_LOW_RANGE                 _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(0)
+#define AREMC_STAT_HIST_LIMIT_LOW_ROW                   0
+
+#define AREMC_STAT_HIST_LIMIT_HIGH_SHIFT                        _MK_SHIFT_CONST(16)
+#define AREMC_STAT_HIST_LIMIT_HIGH_FIELD                        (_MK_MASK_CONST(0xffff) << AREMC_STAT_HIST_LIMIT_HIGH_SHIFT)
+#define AREMC_STAT_HIST_LIMIT_HIGH_RANGE                        _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(16)
+#define AREMC_STAT_HIST_LIMIT_HIGH_ROW                  0
+
+
+// Register EMC_STAT_LLMC_HIST_LIMIT_0_0  
+#define EMC_STAT_LLMC_HIST_LIMIT_0_0                    _MK_ADDR_CONST(0x180)
+#define EMC_STAT_LLMC_HIST_LIMIT_0_0_SECURE                     0x0
+#define EMC_STAT_LLMC_HIST_LIMIT_0_0_WORD_COUNT                         0x1
+#define EMC_STAT_LLMC_HIST_LIMIT_0_0_RESET_VAL                  _MK_MASK_CONST(0xffff0000)
+#define EMC_STAT_LLMC_HIST_LIMIT_0_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_LLMC_HIST_LIMIT_0_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_HIST_LIMIT_0_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_HIST_LIMIT_0_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_LLMC_HIST_LIMIT_0_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_LLMC_HIST_LIMIT_0_0_LLMC_HIST_LIMIT_0_SHIFT                    _MK_SHIFT_CONST(0)
+#define EMC_STAT_LLMC_HIST_LIMIT_0_0_LLMC_HIST_LIMIT_0_FIELD                    (_MK_MASK_CONST(0xffffffff) << EMC_STAT_LLMC_HIST_LIMIT_0_0_LLMC_HIST_LIMIT_0_SHIFT)
+#define EMC_STAT_LLMC_HIST_LIMIT_0_0_LLMC_HIST_LIMIT_0_RANGE                    31:0
+#define EMC_STAT_LLMC_HIST_LIMIT_0_0_LLMC_HIST_LIMIT_0_WOFFSET                  0x0
+#define EMC_STAT_LLMC_HIST_LIMIT_0_0_LLMC_HIST_LIMIT_0_DEFAULT                  _MK_MASK_CONST(0xffff0000)
+#define EMC_STAT_LLMC_HIST_LIMIT_0_0_LLMC_HIST_LIMIT_0_DEFAULT_MASK                     _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_LLMC_HIST_LIMIT_0_0_LLMC_HIST_LIMIT_0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_HIST_LIMIT_0_0_LLMC_HIST_LIMIT_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_HIST_LIMIT_0_0_LLMC_HIST_LIMIT_0_INIT_ENUM                        -65536
+
+
+// Reserved address 388 [0x184] 
+
+// Register EMC_STAT_LLMC_COUNT_0_0  
+#define EMC_STAT_LLMC_COUNT_0_0                 _MK_ADDR_CONST(0x188)
+#define EMC_STAT_LLMC_COUNT_0_0_SECURE                  0x0
+#define EMC_STAT_LLMC_COUNT_0_0_WORD_COUNT                      0x1
+#define EMC_STAT_LLMC_COUNT_0_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_COUNT_0_0_RESET_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_COUNT_0_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_COUNT_0_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_COUNT_0_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_LLMC_COUNT_0_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_COUNT_0_0_LLMC_COUNT_0_SHIFT                      _MK_SHIFT_CONST(0)
+#define EMC_STAT_LLMC_COUNT_0_0_LLMC_COUNT_0_FIELD                      (_MK_MASK_CONST(0xffffffff) << EMC_STAT_LLMC_COUNT_0_0_LLMC_COUNT_0_SHIFT)
+#define EMC_STAT_LLMC_COUNT_0_0_LLMC_COUNT_0_RANGE                      31:0
+#define EMC_STAT_LLMC_COUNT_0_0_LLMC_COUNT_0_WOFFSET                    0x0
+#define EMC_STAT_LLMC_COUNT_0_0_LLMC_COUNT_0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_COUNT_0_0_LLMC_COUNT_0_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_COUNT_0_0_LLMC_COUNT_0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_COUNT_0_0_LLMC_COUNT_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Reserved address 396 [0x18c] 
+
+// Register EMC_STAT_LLMC_HIST_0_0  
+#define EMC_STAT_LLMC_HIST_0_0                  _MK_ADDR_CONST(0x190)
+#define EMC_STAT_LLMC_HIST_0_0_SECURE                   0x0
+#define EMC_STAT_LLMC_HIST_0_0_WORD_COUNT                       0x1
+#define EMC_STAT_LLMC_HIST_0_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_HIST_0_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_HIST_0_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_HIST_0_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_HIST_0_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_LLMC_HIST_0_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_HIST_0_0_LLMC_HIST_0_SHIFT                        _MK_SHIFT_CONST(0)
+#define EMC_STAT_LLMC_HIST_0_0_LLMC_HIST_0_FIELD                        (_MK_MASK_CONST(0xffffffff) << EMC_STAT_LLMC_HIST_0_0_LLMC_HIST_0_SHIFT)
+#define EMC_STAT_LLMC_HIST_0_0_LLMC_HIST_0_RANGE                        31:0
+#define EMC_STAT_LLMC_HIST_0_0_LLMC_HIST_0_WOFFSET                      0x0
+#define EMC_STAT_LLMC_HIST_0_0_LLMC_HIST_0_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_HIST_0_0_LLMC_HIST_0_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_HIST_0_0_LLMC_HIST_0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_HIST_0_0_LLMC_HIST_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Reserved address 404 [0x194] 
+
+// Register EMC_STAT_PWR_CLOCK_LIMIT_0  
+#define EMC_STAT_PWR_CLOCK_LIMIT_0                      _MK_ADDR_CONST(0x198)
+#define EMC_STAT_PWR_CLOCK_LIMIT_0_SECURE                       0x0
+#define EMC_STAT_PWR_CLOCK_LIMIT_0_WORD_COUNT                   0x1
+#define EMC_STAT_PWR_CLOCK_LIMIT_0_RESET_VAL                    _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_PWR_CLOCK_LIMIT_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_PWR_CLOCK_LIMIT_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_PWR_CLOCK_LIMIT_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_PWR_CLOCK_LIMIT_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_PWR_CLOCK_LIMIT_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_PWR_CLOCK_LIMIT_0_PWR_CLOCK_LIMIT_SHIFT                        _MK_SHIFT_CONST(0)
+#define EMC_STAT_PWR_CLOCK_LIMIT_0_PWR_CLOCK_LIMIT_FIELD                        (_MK_MASK_CONST(0xffffffff) << EMC_STAT_PWR_CLOCK_LIMIT_0_PWR_CLOCK_LIMIT_SHIFT)
+#define EMC_STAT_PWR_CLOCK_LIMIT_0_PWR_CLOCK_LIMIT_RANGE                        31:0
+#define EMC_STAT_PWR_CLOCK_LIMIT_0_PWR_CLOCK_LIMIT_WOFFSET                      0x0
+#define EMC_STAT_PWR_CLOCK_LIMIT_0_PWR_CLOCK_LIMIT_DEFAULT                      _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_PWR_CLOCK_LIMIT_0_PWR_CLOCK_LIMIT_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_PWR_CLOCK_LIMIT_0_PWR_CLOCK_LIMIT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_STAT_PWR_CLOCK_LIMIT_0_PWR_CLOCK_LIMIT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_PWR_CLOCK_LIMIT_0_PWR_CLOCK_LIMIT_INIT_ENUM                    -1
+
+
+// Register EMC_STAT_PWR_CLOCKS_0  
+#define EMC_STAT_PWR_CLOCKS_0                   _MK_ADDR_CONST(0x19c)
+#define EMC_STAT_PWR_CLOCKS_0_SECURE                    0x0
+#define EMC_STAT_PWR_CLOCKS_0_WORD_COUNT                        0x1
+#define EMC_STAT_PWR_CLOCKS_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define EMC_STAT_PWR_CLOCKS_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_STAT_PWR_CLOCKS_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_PWR_CLOCKS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_STAT_PWR_CLOCKS_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_PWR_CLOCKS_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_STAT_PWR_CLOCKS_0_PWR_CLOCKS_SHIFT                  _MK_SHIFT_CONST(0)
+#define EMC_STAT_PWR_CLOCKS_0_PWR_CLOCKS_FIELD                  (_MK_MASK_CONST(0xffffffff) << EMC_STAT_PWR_CLOCKS_0_PWR_CLOCKS_SHIFT)
+#define EMC_STAT_PWR_CLOCKS_0_PWR_CLOCKS_RANGE                  31:0
+#define EMC_STAT_PWR_CLOCKS_0_PWR_CLOCKS_WOFFSET                        0x0
+#define EMC_STAT_PWR_CLOCKS_0_PWR_CLOCKS_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_STAT_PWR_CLOCKS_0_PWR_CLOCKS_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_STAT_PWR_CLOCKS_0_PWR_CLOCKS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_PWR_CLOCKS_0_PWR_CLOCKS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register EMC_STAT_PWR_COUNT_0  
+#define EMC_STAT_PWR_COUNT_0                    _MK_ADDR_CONST(0x1a0)
+#define EMC_STAT_PWR_COUNT_0_SECURE                     0x0
+#define EMC_STAT_PWR_COUNT_0_WORD_COUNT                         0x1
+#define EMC_STAT_PWR_COUNT_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_PWR_COUNT_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_STAT_PWR_COUNT_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_PWR_COUNT_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_PWR_COUNT_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_PWR_COUNT_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_STAT_PWR_COUNT_0_PWR_COUNT_SHIFT                    _MK_SHIFT_CONST(0)
+#define EMC_STAT_PWR_COUNT_0_PWR_COUNT_FIELD                    (_MK_MASK_CONST(0xffffffff) << EMC_STAT_PWR_COUNT_0_PWR_COUNT_SHIFT)
+#define EMC_STAT_PWR_COUNT_0_PWR_COUNT_RANGE                    31:0
+#define EMC_STAT_PWR_COUNT_0_PWR_COUNT_WOFFSET                  0x0
+#define EMC_STAT_PWR_COUNT_0_PWR_COUNT_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_PWR_COUNT_0_PWR_COUNT_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_PWR_COUNT_0_PWR_COUNT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_PWR_COUNT_0_PWR_COUNT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register EMC_STAT_DRAM_CLOCK_LIMIT_LO_0  
+#define EMC_STAT_DRAM_CLOCK_LIMIT_LO_0                  _MK_ADDR_CONST(0x1a4)
+#define EMC_STAT_DRAM_CLOCK_LIMIT_LO_0_SECURE                   0x0
+#define EMC_STAT_DRAM_CLOCK_LIMIT_LO_0_WORD_COUNT                       0x1
+#define EMC_STAT_DRAM_CLOCK_LIMIT_LO_0_RESET_VAL                        _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_DRAM_CLOCK_LIMIT_LO_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_DRAM_CLOCK_LIMIT_LO_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_CLOCK_LIMIT_LO_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_CLOCK_LIMIT_LO_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_DRAM_CLOCK_LIMIT_LO_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_DRAM_CLOCK_LIMIT_LO_0_DRAM_CLOCK_LIMIT_LO_SHIFT                        _MK_SHIFT_CONST(0)
+#define EMC_STAT_DRAM_CLOCK_LIMIT_LO_0_DRAM_CLOCK_LIMIT_LO_FIELD                        (_MK_MASK_CONST(0xffffffff) << EMC_STAT_DRAM_CLOCK_LIMIT_LO_0_DRAM_CLOCK_LIMIT_LO_SHIFT)
+#define EMC_STAT_DRAM_CLOCK_LIMIT_LO_0_DRAM_CLOCK_LIMIT_LO_RANGE                        31:0
+#define EMC_STAT_DRAM_CLOCK_LIMIT_LO_0_DRAM_CLOCK_LIMIT_LO_WOFFSET                      0x0
+#define EMC_STAT_DRAM_CLOCK_LIMIT_LO_0_DRAM_CLOCK_LIMIT_LO_DEFAULT                      _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_DRAM_CLOCK_LIMIT_LO_0_DRAM_CLOCK_LIMIT_LO_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_DRAM_CLOCK_LIMIT_LO_0_DRAM_CLOCK_LIMIT_LO_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_CLOCK_LIMIT_LO_0_DRAM_CLOCK_LIMIT_LO_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_CLOCK_LIMIT_LO_0_DRAM_CLOCK_LIMIT_LO_INIT_ENUM                    -1
+
+
+// Register EMC_STAT_DRAM_CLOCK_LIMIT_HI_0  
+#define EMC_STAT_DRAM_CLOCK_LIMIT_HI_0                  _MK_ADDR_CONST(0x1a8)
+#define EMC_STAT_DRAM_CLOCK_LIMIT_HI_0_SECURE                   0x0
+#define EMC_STAT_DRAM_CLOCK_LIMIT_HI_0_WORD_COUNT                       0x1
+#define EMC_STAT_DRAM_CLOCK_LIMIT_HI_0_RESET_VAL                        _MK_MASK_CONST(0xff)
+#define EMC_STAT_DRAM_CLOCK_LIMIT_HI_0_RESET_MASK                       _MK_MASK_CONST(0xff)
+#define EMC_STAT_DRAM_CLOCK_LIMIT_HI_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_CLOCK_LIMIT_HI_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_CLOCK_LIMIT_HI_0_READ_MASK                        _MK_MASK_CONST(0xff)
+#define EMC_STAT_DRAM_CLOCK_LIMIT_HI_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
+#define EMC_STAT_DRAM_CLOCK_LIMIT_HI_0_DRAM_CLOCK_LIMIT_HI_SHIFT                        _MK_SHIFT_CONST(0)
+#define EMC_STAT_DRAM_CLOCK_LIMIT_HI_0_DRAM_CLOCK_LIMIT_HI_FIELD                        (_MK_MASK_CONST(0xff) << EMC_STAT_DRAM_CLOCK_LIMIT_HI_0_DRAM_CLOCK_LIMIT_HI_SHIFT)
+#define EMC_STAT_DRAM_CLOCK_LIMIT_HI_0_DRAM_CLOCK_LIMIT_HI_RANGE                        7:0
+#define EMC_STAT_DRAM_CLOCK_LIMIT_HI_0_DRAM_CLOCK_LIMIT_HI_WOFFSET                      0x0
+#define EMC_STAT_DRAM_CLOCK_LIMIT_HI_0_DRAM_CLOCK_LIMIT_HI_DEFAULT                      _MK_MASK_CONST(0xff)
+#define EMC_STAT_DRAM_CLOCK_LIMIT_HI_0_DRAM_CLOCK_LIMIT_HI_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
+#define EMC_STAT_DRAM_CLOCK_LIMIT_HI_0_DRAM_CLOCK_LIMIT_HI_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_CLOCK_LIMIT_HI_0_DRAM_CLOCK_LIMIT_HI_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register EMC_STAT_DRAM_CLOCKS_LO_0  
+#define EMC_STAT_DRAM_CLOCKS_LO_0                       _MK_ADDR_CONST(0x1ac)
+#define EMC_STAT_DRAM_CLOCKS_LO_0_SECURE                        0x0
+#define EMC_STAT_DRAM_CLOCKS_LO_0_WORD_COUNT                    0x1
+#define EMC_STAT_DRAM_CLOCKS_LO_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_CLOCKS_LO_0_RESET_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_CLOCKS_LO_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_CLOCKS_LO_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_CLOCKS_LO_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_DRAM_CLOCKS_LO_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_CLOCKS_LO_0_DRAM_CLOCKS_LO_SHIFT                  _MK_SHIFT_CONST(0)
+#define EMC_STAT_DRAM_CLOCKS_LO_0_DRAM_CLOCKS_LO_FIELD                  (_MK_MASK_CONST(0xffffffff) << EMC_STAT_DRAM_CLOCKS_LO_0_DRAM_CLOCKS_LO_SHIFT)
+#define EMC_STAT_DRAM_CLOCKS_LO_0_DRAM_CLOCKS_LO_RANGE                  31:0
+#define EMC_STAT_DRAM_CLOCKS_LO_0_DRAM_CLOCKS_LO_WOFFSET                        0x0
+#define EMC_STAT_DRAM_CLOCKS_LO_0_DRAM_CLOCKS_LO_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_CLOCKS_LO_0_DRAM_CLOCKS_LO_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_CLOCKS_LO_0_DRAM_CLOCKS_LO_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_CLOCKS_LO_0_DRAM_CLOCKS_LO_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register EMC_STAT_DRAM_CLOCKS_HI_0  
+#define EMC_STAT_DRAM_CLOCKS_HI_0                       _MK_ADDR_CONST(0x1b0)
+#define EMC_STAT_DRAM_CLOCKS_HI_0_SECURE                        0x0
+#define EMC_STAT_DRAM_CLOCKS_HI_0_WORD_COUNT                    0x1
+#define EMC_STAT_DRAM_CLOCKS_HI_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_CLOCKS_HI_0_RESET_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_CLOCKS_HI_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_CLOCKS_HI_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_CLOCKS_HI_0_READ_MASK                     _MK_MASK_CONST(0xff)
+#define EMC_STAT_DRAM_CLOCKS_HI_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_CLOCKS_HI_0_DRAM_CLOCKS_HI_SHIFT                  _MK_SHIFT_CONST(0)
+#define EMC_STAT_DRAM_CLOCKS_HI_0_DRAM_CLOCKS_HI_FIELD                  (_MK_MASK_CONST(0xff) << EMC_STAT_DRAM_CLOCKS_HI_0_DRAM_CLOCKS_HI_SHIFT)
+#define EMC_STAT_DRAM_CLOCKS_HI_0_DRAM_CLOCKS_HI_RANGE                  7:0
+#define EMC_STAT_DRAM_CLOCKS_HI_0_DRAM_CLOCKS_HI_WOFFSET                        0x0
+#define EMC_STAT_DRAM_CLOCKS_HI_0_DRAM_CLOCKS_HI_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_CLOCKS_HI_0_DRAM_CLOCKS_HI_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_CLOCKS_HI_0_DRAM_CLOCKS_HI_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_CLOCKS_HI_0_DRAM_CLOCKS_HI_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register EMC_STAT_DRAM_DEV0_ACTIVATE_CNT_LO_0  
+#define EMC_STAT_DRAM_DEV0_ACTIVATE_CNT_LO_0                    _MK_ADDR_CONST(0x1b4)
+#define EMC_STAT_DRAM_DEV0_ACTIVATE_CNT_LO_0_SECURE                     0x0
+#define EMC_STAT_DRAM_DEV0_ACTIVATE_CNT_LO_0_WORD_COUNT                         0x1
+#define EMC_STAT_DRAM_DEV0_ACTIVATE_CNT_LO_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_ACTIVATE_CNT_LO_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_ACTIVATE_CNT_LO_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_ACTIVATE_CNT_LO_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_ACTIVATE_CNT_LO_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_DRAM_DEV0_ACTIVATE_CNT_LO_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_ACTIVATE_CNT_LO_0_DEV0_ACTIVATE_CNT_LO_SHIFT                 _MK_SHIFT_CONST(0)
+#define EMC_STAT_DRAM_DEV0_ACTIVATE_CNT_LO_0_DEV0_ACTIVATE_CNT_LO_FIELD                 (_MK_MASK_CONST(0xffffffff) << EMC_STAT_DRAM_DEV0_ACTIVATE_CNT_LO_0_DEV0_ACTIVATE_CNT_LO_SHIFT)
+#define EMC_STAT_DRAM_DEV0_ACTIVATE_CNT_LO_0_DEV0_ACTIVATE_CNT_LO_RANGE                 31:0
+#define EMC_STAT_DRAM_DEV0_ACTIVATE_CNT_LO_0_DEV0_ACTIVATE_CNT_LO_WOFFSET                       0x0
+#define EMC_STAT_DRAM_DEV0_ACTIVATE_CNT_LO_0_DEV0_ACTIVATE_CNT_LO_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_ACTIVATE_CNT_LO_0_DEV0_ACTIVATE_CNT_LO_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_ACTIVATE_CNT_LO_0_DEV0_ACTIVATE_CNT_LO_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_ACTIVATE_CNT_LO_0_DEV0_ACTIVATE_CNT_LO_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EMC_STAT_DRAM_DEV0_ACTIVATE_CNT_HI_0  
+#define EMC_STAT_DRAM_DEV0_ACTIVATE_CNT_HI_0                    _MK_ADDR_CONST(0x1b8)
+#define EMC_STAT_DRAM_DEV0_ACTIVATE_CNT_HI_0_SECURE                     0x0
+#define EMC_STAT_DRAM_DEV0_ACTIVATE_CNT_HI_0_WORD_COUNT                         0x1
+#define EMC_STAT_DRAM_DEV0_ACTIVATE_CNT_HI_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_ACTIVATE_CNT_HI_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_ACTIVATE_CNT_HI_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_ACTIVATE_CNT_HI_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_ACTIVATE_CNT_HI_0_READ_MASK                  _MK_MASK_CONST(0xff)
+#define EMC_STAT_DRAM_DEV0_ACTIVATE_CNT_HI_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_ACTIVATE_CNT_HI_0_DEV0_ACTIVATE_CNT_HI_SHIFT                 _MK_SHIFT_CONST(0)
+#define EMC_STAT_DRAM_DEV0_ACTIVATE_CNT_HI_0_DEV0_ACTIVATE_CNT_HI_FIELD                 (_MK_MASK_CONST(0xff) << EMC_STAT_DRAM_DEV0_ACTIVATE_CNT_HI_0_DEV0_ACTIVATE_CNT_HI_SHIFT)
+#define EMC_STAT_DRAM_DEV0_ACTIVATE_CNT_HI_0_DEV0_ACTIVATE_CNT_HI_RANGE                 7:0
+#define EMC_STAT_DRAM_DEV0_ACTIVATE_CNT_HI_0_DEV0_ACTIVATE_CNT_HI_WOFFSET                       0x0
+#define EMC_STAT_DRAM_DEV0_ACTIVATE_CNT_HI_0_DEV0_ACTIVATE_CNT_HI_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_ACTIVATE_CNT_HI_0_DEV0_ACTIVATE_CNT_HI_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_ACTIVATE_CNT_HI_0_DEV0_ACTIVATE_CNT_HI_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_ACTIVATE_CNT_HI_0_DEV0_ACTIVATE_CNT_HI_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EMC_STAT_DRAM_DEV0_READ_CNT_LO_0  
+#define EMC_STAT_DRAM_DEV0_READ_CNT_LO_0                        _MK_ADDR_CONST(0x1bc)
+#define EMC_STAT_DRAM_DEV0_READ_CNT_LO_0_SECURE                         0x0
+#define EMC_STAT_DRAM_DEV0_READ_CNT_LO_0_WORD_COUNT                     0x1
+#define EMC_STAT_DRAM_DEV0_READ_CNT_LO_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_READ_CNT_LO_0_RESET_MASK                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_READ_CNT_LO_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_READ_CNT_LO_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_READ_CNT_LO_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_DRAM_DEV0_READ_CNT_LO_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_READ_CNT_LO_0_DEV0_READ_CNT_LO_SHIFT                 _MK_SHIFT_CONST(0)
+#define EMC_STAT_DRAM_DEV0_READ_CNT_LO_0_DEV0_READ_CNT_LO_FIELD                 (_MK_MASK_CONST(0xffffffff) << EMC_STAT_DRAM_DEV0_READ_CNT_LO_0_DEV0_READ_CNT_LO_SHIFT)
+#define EMC_STAT_DRAM_DEV0_READ_CNT_LO_0_DEV0_READ_CNT_LO_RANGE                 31:0
+#define EMC_STAT_DRAM_DEV0_READ_CNT_LO_0_DEV0_READ_CNT_LO_WOFFSET                       0x0
+#define EMC_STAT_DRAM_DEV0_READ_CNT_LO_0_DEV0_READ_CNT_LO_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_READ_CNT_LO_0_DEV0_READ_CNT_LO_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_READ_CNT_LO_0_DEV0_READ_CNT_LO_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_READ_CNT_LO_0_DEV0_READ_CNT_LO_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EMC_STAT_DRAM_DEV0_READ_CNT_HI_0  
+#define EMC_STAT_DRAM_DEV0_READ_CNT_HI_0                        _MK_ADDR_CONST(0x1c0)
+#define EMC_STAT_DRAM_DEV0_READ_CNT_HI_0_SECURE                         0x0
+#define EMC_STAT_DRAM_DEV0_READ_CNT_HI_0_WORD_COUNT                     0x1
+#define EMC_STAT_DRAM_DEV0_READ_CNT_HI_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_READ_CNT_HI_0_RESET_MASK                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_READ_CNT_HI_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_READ_CNT_HI_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_READ_CNT_HI_0_READ_MASK                      _MK_MASK_CONST(0xff)
+#define EMC_STAT_DRAM_DEV0_READ_CNT_HI_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_READ_CNT_HI_0_DEV0_READ_CNT_HI_SHIFT                 _MK_SHIFT_CONST(0)
+#define EMC_STAT_DRAM_DEV0_READ_CNT_HI_0_DEV0_READ_CNT_HI_FIELD                 (_MK_MASK_CONST(0xff) << EMC_STAT_DRAM_DEV0_READ_CNT_HI_0_DEV0_READ_CNT_HI_SHIFT)
+#define EMC_STAT_DRAM_DEV0_READ_CNT_HI_0_DEV0_READ_CNT_HI_RANGE                 7:0
+#define EMC_STAT_DRAM_DEV0_READ_CNT_HI_0_DEV0_READ_CNT_HI_WOFFSET                       0x0
+#define EMC_STAT_DRAM_DEV0_READ_CNT_HI_0_DEV0_READ_CNT_HI_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_READ_CNT_HI_0_DEV0_READ_CNT_HI_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_READ_CNT_HI_0_DEV0_READ_CNT_HI_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_READ_CNT_HI_0_DEV0_READ_CNT_HI_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EMC_STAT_DRAM_DEV0_WRITE_CNT_LO_0  
+#define EMC_STAT_DRAM_DEV0_WRITE_CNT_LO_0                       _MK_ADDR_CONST(0x1c4)
+#define EMC_STAT_DRAM_DEV0_WRITE_CNT_LO_0_SECURE                        0x0
+#define EMC_STAT_DRAM_DEV0_WRITE_CNT_LO_0_WORD_COUNT                    0x1
+#define EMC_STAT_DRAM_DEV0_WRITE_CNT_LO_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_WRITE_CNT_LO_0_RESET_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_WRITE_CNT_LO_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_WRITE_CNT_LO_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_WRITE_CNT_LO_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_DRAM_DEV0_WRITE_CNT_LO_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_WRITE_CNT_LO_0_DEV0_WRITE_CNT_LO_SHIFT                       _MK_SHIFT_CONST(0)
+#define EMC_STAT_DRAM_DEV0_WRITE_CNT_LO_0_DEV0_WRITE_CNT_LO_FIELD                       (_MK_MASK_CONST(0xffffffff) << EMC_STAT_DRAM_DEV0_WRITE_CNT_LO_0_DEV0_WRITE_CNT_LO_SHIFT)
+#define EMC_STAT_DRAM_DEV0_WRITE_CNT_LO_0_DEV0_WRITE_CNT_LO_RANGE                       31:0
+#define EMC_STAT_DRAM_DEV0_WRITE_CNT_LO_0_DEV0_WRITE_CNT_LO_WOFFSET                     0x0
+#define EMC_STAT_DRAM_DEV0_WRITE_CNT_LO_0_DEV0_WRITE_CNT_LO_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_WRITE_CNT_LO_0_DEV0_WRITE_CNT_LO_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_WRITE_CNT_LO_0_DEV0_WRITE_CNT_LO_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_WRITE_CNT_LO_0_DEV0_WRITE_CNT_LO_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register EMC_STAT_DRAM_DEV0_WRITE_CNT_HI_0  
+#define EMC_STAT_DRAM_DEV0_WRITE_CNT_HI_0                       _MK_ADDR_CONST(0x1c8)
+#define EMC_STAT_DRAM_DEV0_WRITE_CNT_HI_0_SECURE                        0x0
+#define EMC_STAT_DRAM_DEV0_WRITE_CNT_HI_0_WORD_COUNT                    0x1
+#define EMC_STAT_DRAM_DEV0_WRITE_CNT_HI_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_WRITE_CNT_HI_0_RESET_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_WRITE_CNT_HI_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_WRITE_CNT_HI_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_WRITE_CNT_HI_0_READ_MASK                     _MK_MASK_CONST(0xff)
+#define EMC_STAT_DRAM_DEV0_WRITE_CNT_HI_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_WRITE_CNT_HI_0_DEV0_WRITE_CNT_HI_SHIFT                       _MK_SHIFT_CONST(0)
+#define EMC_STAT_DRAM_DEV0_WRITE_CNT_HI_0_DEV0_WRITE_CNT_HI_FIELD                       (_MK_MASK_CONST(0xff) << EMC_STAT_DRAM_DEV0_WRITE_CNT_HI_0_DEV0_WRITE_CNT_HI_SHIFT)
+#define EMC_STAT_DRAM_DEV0_WRITE_CNT_HI_0_DEV0_WRITE_CNT_HI_RANGE                       7:0
+#define EMC_STAT_DRAM_DEV0_WRITE_CNT_HI_0_DEV0_WRITE_CNT_HI_WOFFSET                     0x0
+#define EMC_STAT_DRAM_DEV0_WRITE_CNT_HI_0_DEV0_WRITE_CNT_HI_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_WRITE_CNT_HI_0_DEV0_WRITE_CNT_HI_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_WRITE_CNT_HI_0_DEV0_WRITE_CNT_HI_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_WRITE_CNT_HI_0_DEV0_WRITE_CNT_HI_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register EMC_STAT_DRAM_DEV0_REF_CNT_LO_0  
+#define EMC_STAT_DRAM_DEV0_REF_CNT_LO_0                 _MK_ADDR_CONST(0x1cc)
+#define EMC_STAT_DRAM_DEV0_REF_CNT_LO_0_SECURE                  0x0
+#define EMC_STAT_DRAM_DEV0_REF_CNT_LO_0_WORD_COUNT                      0x1
+#define EMC_STAT_DRAM_DEV0_REF_CNT_LO_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_REF_CNT_LO_0_RESET_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_REF_CNT_LO_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_REF_CNT_LO_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_REF_CNT_LO_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_DRAM_DEV0_REF_CNT_LO_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_REF_CNT_LO_0_DEV0_REF_CNT_LO_SHIFT                   _MK_SHIFT_CONST(0)
+#define EMC_STAT_DRAM_DEV0_REF_CNT_LO_0_DEV0_REF_CNT_LO_FIELD                   (_MK_MASK_CONST(0xffffffff) << EMC_STAT_DRAM_DEV0_REF_CNT_LO_0_DEV0_REF_CNT_LO_SHIFT)
+#define EMC_STAT_DRAM_DEV0_REF_CNT_LO_0_DEV0_REF_CNT_LO_RANGE                   31:0
+#define EMC_STAT_DRAM_DEV0_REF_CNT_LO_0_DEV0_REF_CNT_LO_WOFFSET                 0x0
+#define EMC_STAT_DRAM_DEV0_REF_CNT_LO_0_DEV0_REF_CNT_LO_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_REF_CNT_LO_0_DEV0_REF_CNT_LO_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_REF_CNT_LO_0_DEV0_REF_CNT_LO_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_REF_CNT_LO_0_DEV0_REF_CNT_LO_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register EMC_STAT_DRAM_DEV0_REF_CNT_HI_0  
+#define EMC_STAT_DRAM_DEV0_REF_CNT_HI_0                 _MK_ADDR_CONST(0x1d0)
+#define EMC_STAT_DRAM_DEV0_REF_CNT_HI_0_SECURE                  0x0
+#define EMC_STAT_DRAM_DEV0_REF_CNT_HI_0_WORD_COUNT                      0x1
+#define EMC_STAT_DRAM_DEV0_REF_CNT_HI_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_REF_CNT_HI_0_RESET_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_REF_CNT_HI_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_REF_CNT_HI_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_REF_CNT_HI_0_READ_MASK                       _MK_MASK_CONST(0xff)
+#define EMC_STAT_DRAM_DEV0_REF_CNT_HI_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_REF_CNT_HI_0_DEV0_REF_CNT_HI_SHIFT                   _MK_SHIFT_CONST(0)
+#define EMC_STAT_DRAM_DEV0_REF_CNT_HI_0_DEV0_REF_CNT_HI_FIELD                   (_MK_MASK_CONST(0xff) << EMC_STAT_DRAM_DEV0_REF_CNT_HI_0_DEV0_REF_CNT_HI_SHIFT)
+#define EMC_STAT_DRAM_DEV0_REF_CNT_HI_0_DEV0_REF_CNT_HI_RANGE                   7:0
+#define EMC_STAT_DRAM_DEV0_REF_CNT_HI_0_DEV0_REF_CNT_HI_WOFFSET                 0x0
+#define EMC_STAT_DRAM_DEV0_REF_CNT_HI_0_DEV0_REF_CNT_HI_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_REF_CNT_HI_0_DEV0_REF_CNT_HI_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_REF_CNT_HI_0_DEV0_REF_CNT_HI_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_REF_CNT_HI_0_DEV0_REF_CNT_HI_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ1_LO_0  
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ1_LO_0                       _MK_ADDR_CONST(0x1d4)
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ1_LO_0_SECURE                        0x0
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ1_LO_0_WORD_COUNT                    0x1
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ1_LO_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ1_LO_0_RESET_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ1_LO_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ1_LO_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ1_LO_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ1_LO_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ1_LO_0_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ1_LO_SHIFT                       _MK_SHIFT_CONST(0)
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ1_LO_0_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ1_LO_FIELD                       (_MK_MASK_CONST(0xffffffff) << EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ1_LO_0_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ1_LO_SHIFT)
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ1_LO_0_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ1_LO_RANGE                       31:0
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ1_LO_0_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ1_LO_WOFFSET                     0x0
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ1_LO_0_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ1_LO_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ1_LO_0_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ1_LO_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ1_LO_0_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ1_LO_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ1_LO_0_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ1_LO_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ1_HI_0  
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ1_HI_0                       _MK_ADDR_CONST(0x1d8)
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ1_HI_0_SECURE                        0x0
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ1_HI_0_WORD_COUNT                    0x1
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ1_HI_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ1_HI_0_RESET_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ1_HI_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ1_HI_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ1_HI_0_READ_MASK                     _MK_MASK_CONST(0xff)
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ1_HI_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ1_HI_0_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ1_HI_SHIFT                       _MK_SHIFT_CONST(0)
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ1_HI_0_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ1_HI_FIELD                       (_MK_MASK_CONST(0xff) << EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ1_HI_0_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ1_HI_SHIFT)
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ1_HI_0_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ1_HI_RANGE                       7:0
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ1_HI_0_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ1_HI_WOFFSET                     0x0
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ1_HI_0_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ1_HI_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ1_HI_0_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ1_HI_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ1_HI_0_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ1_HI_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ1_HI_0_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ1_HI_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ0_LO_0  
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ0_LO_0                       _MK_ADDR_CONST(0x1dc)
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ0_LO_0_SECURE                        0x0
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ0_LO_0_WORD_COUNT                    0x1
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ0_LO_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ0_LO_0_RESET_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ0_LO_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ0_LO_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ0_LO_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ0_LO_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ0_LO_0_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ0_LO_SHIFT                       _MK_SHIFT_CONST(0)
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ0_LO_0_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ0_LO_FIELD                       (_MK_MASK_CONST(0xffffffff) << EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ0_LO_0_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ0_LO_SHIFT)
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ0_LO_0_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ0_LO_RANGE                       31:0
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ0_LO_0_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ0_LO_WOFFSET                     0x0
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ0_LO_0_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ0_LO_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ0_LO_0_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ0_LO_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ0_LO_0_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ0_LO_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ0_LO_0_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ0_LO_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ0_HI_0  
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ0_HI_0                       _MK_ADDR_CONST(0x1e0)
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ0_HI_0_SECURE                        0x0
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ0_HI_0_WORD_COUNT                    0x1
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ0_HI_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ0_HI_0_RESET_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ0_HI_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ0_HI_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ0_HI_0_READ_MASK                     _MK_MASK_CONST(0xff)
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ0_HI_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ0_HI_0_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ0_HI_SHIFT                       _MK_SHIFT_CONST(0)
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ0_HI_0_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ0_HI_FIELD                       (_MK_MASK_CONST(0xff) << EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ0_HI_0_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ0_HI_SHIFT)
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ0_HI_0_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ0_HI_RANGE                       7:0
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ0_HI_0_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ0_HI_WOFFSET                     0x0
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ0_HI_0_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ0_HI_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ0_HI_0_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ0_HI_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ0_HI_0_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ0_HI_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ0_HI_0_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ0_HI_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register EMC_STAT_DRAM_DEV0_CKE_EQ1_CLKS_LO_0  
+#define EMC_STAT_DRAM_DEV0_CKE_EQ1_CLKS_LO_0                    _MK_ADDR_CONST(0x1e4)
+#define EMC_STAT_DRAM_DEV0_CKE_EQ1_CLKS_LO_0_SECURE                     0x0
+#define EMC_STAT_DRAM_DEV0_CKE_EQ1_CLKS_LO_0_WORD_COUNT                         0x1
+#define EMC_STAT_DRAM_DEV0_CKE_EQ1_CLKS_LO_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_CKE_EQ1_CLKS_LO_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_CKE_EQ1_CLKS_LO_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_CKE_EQ1_CLKS_LO_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_CKE_EQ1_CLKS_LO_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_DRAM_DEV0_CKE_EQ1_CLKS_LO_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_CKE_EQ1_CLKS_LO_0_DEV0_CKE_EQ1_CLKS_LO_SHIFT                 _MK_SHIFT_CONST(0)
+#define EMC_STAT_DRAM_DEV0_CKE_EQ1_CLKS_LO_0_DEV0_CKE_EQ1_CLKS_LO_FIELD                 (_MK_MASK_CONST(0xffffffff) << EMC_STAT_DRAM_DEV0_CKE_EQ1_CLKS_LO_0_DEV0_CKE_EQ1_CLKS_LO_SHIFT)
+#define EMC_STAT_DRAM_DEV0_CKE_EQ1_CLKS_LO_0_DEV0_CKE_EQ1_CLKS_LO_RANGE                 31:0
+#define EMC_STAT_DRAM_DEV0_CKE_EQ1_CLKS_LO_0_DEV0_CKE_EQ1_CLKS_LO_WOFFSET                       0x0
+#define EMC_STAT_DRAM_DEV0_CKE_EQ1_CLKS_LO_0_DEV0_CKE_EQ1_CLKS_LO_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_CKE_EQ1_CLKS_LO_0_DEV0_CKE_EQ1_CLKS_LO_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_CKE_EQ1_CLKS_LO_0_DEV0_CKE_EQ1_CLKS_LO_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_CKE_EQ1_CLKS_LO_0_DEV0_CKE_EQ1_CLKS_LO_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EMC_STAT_DRAM_DEV0_CKE_EQ1_CLKS_HI_0  
+#define EMC_STAT_DRAM_DEV0_CKE_EQ1_CLKS_HI_0                    _MK_ADDR_CONST(0x1e8)
+#define EMC_STAT_DRAM_DEV0_CKE_EQ1_CLKS_HI_0_SECURE                     0x0
+#define EMC_STAT_DRAM_DEV0_CKE_EQ1_CLKS_HI_0_WORD_COUNT                         0x1
+#define EMC_STAT_DRAM_DEV0_CKE_EQ1_CLKS_HI_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_CKE_EQ1_CLKS_HI_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_CKE_EQ1_CLKS_HI_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_CKE_EQ1_CLKS_HI_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_CKE_EQ1_CLKS_HI_0_READ_MASK                  _MK_MASK_CONST(0xff)
+#define EMC_STAT_DRAM_DEV0_CKE_EQ1_CLKS_HI_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_CKE_EQ1_CLKS_HI_0_DEV0_CKE_EQ1_CLKS_HI_SHIFT                 _MK_SHIFT_CONST(0)
+#define EMC_STAT_DRAM_DEV0_CKE_EQ1_CLKS_HI_0_DEV0_CKE_EQ1_CLKS_HI_FIELD                 (_MK_MASK_CONST(0xff) << EMC_STAT_DRAM_DEV0_CKE_EQ1_CLKS_HI_0_DEV0_CKE_EQ1_CLKS_HI_SHIFT)
+#define EMC_STAT_DRAM_DEV0_CKE_EQ1_CLKS_HI_0_DEV0_CKE_EQ1_CLKS_HI_RANGE                 7:0
+#define EMC_STAT_DRAM_DEV0_CKE_EQ1_CLKS_HI_0_DEV0_CKE_EQ1_CLKS_HI_WOFFSET                       0x0
+#define EMC_STAT_DRAM_DEV0_CKE_EQ1_CLKS_HI_0_DEV0_CKE_EQ1_CLKS_HI_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_CKE_EQ1_CLKS_HI_0_DEV0_CKE_EQ1_CLKS_HI_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_CKE_EQ1_CLKS_HI_0_DEV0_CKE_EQ1_CLKS_HI_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_CKE_EQ1_CLKS_HI_0_DEV0_CKE_EQ1_CLKS_HI_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ1_LO_0  
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ1_LO_0                 _MK_ADDR_CONST(0x1ec)
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ1_LO_0_SECURE                  0x0
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ1_LO_0_WORD_COUNT                      0x1
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ1_LO_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ1_LO_0_RESET_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ1_LO_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ1_LO_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ1_LO_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ1_LO_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ1_LO_0_DEV0_EXTCLKS_CKE_EQ1_LO_SHIFT                   _MK_SHIFT_CONST(0)
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ1_LO_0_DEV0_EXTCLKS_CKE_EQ1_LO_FIELD                   (_MK_MASK_CONST(0xffffffff) << EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ1_LO_0_DEV0_EXTCLKS_CKE_EQ1_LO_SHIFT)
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ1_LO_0_DEV0_EXTCLKS_CKE_EQ1_LO_RANGE                   31:0
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ1_LO_0_DEV0_EXTCLKS_CKE_EQ1_LO_WOFFSET                 0x0
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ1_LO_0_DEV0_EXTCLKS_CKE_EQ1_LO_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ1_LO_0_DEV0_EXTCLKS_CKE_EQ1_LO_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ1_LO_0_DEV0_EXTCLKS_CKE_EQ1_LO_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ1_LO_0_DEV0_EXTCLKS_CKE_EQ1_LO_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ1_HI_0  
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ1_HI_0                 _MK_ADDR_CONST(0x1f0)
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ1_HI_0_SECURE                  0x0
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ1_HI_0_WORD_COUNT                      0x1
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ1_HI_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ1_HI_0_RESET_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ1_HI_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ1_HI_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ1_HI_0_READ_MASK                       _MK_MASK_CONST(0xff)
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ1_HI_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ1_HI_0_DEV0_EXTCLKS_CKE_EQ1_HI_SHIFT                   _MK_SHIFT_CONST(0)
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ1_HI_0_DEV0_EXTCLKS_CKE_EQ1_HI_FIELD                   (_MK_MASK_CONST(0xff) << EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ1_HI_0_DEV0_EXTCLKS_CKE_EQ1_HI_SHIFT)
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ1_HI_0_DEV0_EXTCLKS_CKE_EQ1_HI_RANGE                   7:0
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ1_HI_0_DEV0_EXTCLKS_CKE_EQ1_HI_WOFFSET                 0x0
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ1_HI_0_DEV0_EXTCLKS_CKE_EQ1_HI_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ1_HI_0_DEV0_EXTCLKS_CKE_EQ1_HI_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ1_HI_0_DEV0_EXTCLKS_CKE_EQ1_HI_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ1_HI_0_DEV0_EXTCLKS_CKE_EQ1_HI_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ0_LO_0  
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ0_LO_0                 _MK_ADDR_CONST(0x1f4)
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ0_LO_0_SECURE                  0x0
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ0_LO_0_WORD_COUNT                      0x1
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ0_LO_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ0_LO_0_RESET_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ0_LO_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ0_LO_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ0_LO_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ0_LO_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ0_LO_0_DEV0_EXTCLKS_CKE_EQ0_LO_SHIFT                   _MK_SHIFT_CONST(0)
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ0_LO_0_DEV0_EXTCLKS_CKE_EQ0_LO_FIELD                   (_MK_MASK_CONST(0xffffffff) << EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ0_LO_0_DEV0_EXTCLKS_CKE_EQ0_LO_SHIFT)
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ0_LO_0_DEV0_EXTCLKS_CKE_EQ0_LO_RANGE                   31:0
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ0_LO_0_DEV0_EXTCLKS_CKE_EQ0_LO_WOFFSET                 0x0
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ0_LO_0_DEV0_EXTCLKS_CKE_EQ0_LO_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ0_LO_0_DEV0_EXTCLKS_CKE_EQ0_LO_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ0_LO_0_DEV0_EXTCLKS_CKE_EQ0_LO_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ0_LO_0_DEV0_EXTCLKS_CKE_EQ0_LO_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ0_HI_0  
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ0_HI_0                 _MK_ADDR_CONST(0x1f8)
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ0_HI_0_SECURE                  0x0
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ0_HI_0_WORD_COUNT                      0x1
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ0_HI_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ0_HI_0_RESET_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ0_HI_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ0_HI_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ0_HI_0_READ_MASK                       _MK_MASK_CONST(0xff)
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ0_HI_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ0_HI_0_DEV0_EXTCLKS_CKE_EQ0_HI_SHIFT                   _MK_SHIFT_CONST(0)
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ0_HI_0_DEV0_EXTCLKS_CKE_EQ0_HI_FIELD                   (_MK_MASK_CONST(0xff) << EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ0_HI_0_DEV0_EXTCLKS_CKE_EQ0_HI_SHIFT)
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ0_HI_0_DEV0_EXTCLKS_CKE_EQ0_HI_RANGE                   7:0
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ0_HI_0_DEV0_EXTCLKS_CKE_EQ0_HI_WOFFSET                 0x0
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ0_HI_0_DEV0_EXTCLKS_CKE_EQ0_HI_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ0_HI_0_DEV0_EXTCLKS_CKE_EQ0_HI_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ0_HI_0_DEV0_EXTCLKS_CKE_EQ0_HI_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ0_HI_0_DEV0_EXTCLKS_CKE_EQ0_HI_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register EMC_STAT_DRAM_DEV1_ACTIVATE_CNT_LO_0  
+#define EMC_STAT_DRAM_DEV1_ACTIVATE_CNT_LO_0                    _MK_ADDR_CONST(0x1fc)
+#define EMC_STAT_DRAM_DEV1_ACTIVATE_CNT_LO_0_SECURE                     0x0
+#define EMC_STAT_DRAM_DEV1_ACTIVATE_CNT_LO_0_WORD_COUNT                         0x1
+#define EMC_STAT_DRAM_DEV1_ACTIVATE_CNT_LO_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_ACTIVATE_CNT_LO_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_ACTIVATE_CNT_LO_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_ACTIVATE_CNT_LO_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_ACTIVATE_CNT_LO_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_DRAM_DEV1_ACTIVATE_CNT_LO_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_ACTIVATE_CNT_LO_0_DEV1_ACTIVATE_CNT_LO_SHIFT                 _MK_SHIFT_CONST(0)
+#define EMC_STAT_DRAM_DEV1_ACTIVATE_CNT_LO_0_DEV1_ACTIVATE_CNT_LO_FIELD                 (_MK_MASK_CONST(0xffffffff) << EMC_STAT_DRAM_DEV1_ACTIVATE_CNT_LO_0_DEV1_ACTIVATE_CNT_LO_SHIFT)
+#define EMC_STAT_DRAM_DEV1_ACTIVATE_CNT_LO_0_DEV1_ACTIVATE_CNT_LO_RANGE                 31:0
+#define EMC_STAT_DRAM_DEV1_ACTIVATE_CNT_LO_0_DEV1_ACTIVATE_CNT_LO_WOFFSET                       0x0
+#define EMC_STAT_DRAM_DEV1_ACTIVATE_CNT_LO_0_DEV1_ACTIVATE_CNT_LO_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_ACTIVATE_CNT_LO_0_DEV1_ACTIVATE_CNT_LO_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_ACTIVATE_CNT_LO_0_DEV1_ACTIVATE_CNT_LO_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_ACTIVATE_CNT_LO_0_DEV1_ACTIVATE_CNT_LO_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EMC_STAT_DRAM_DEV1_ACTIVATE_CNT_HI_0  
+#define EMC_STAT_DRAM_DEV1_ACTIVATE_CNT_HI_0                    _MK_ADDR_CONST(0x200)
+#define EMC_STAT_DRAM_DEV1_ACTIVATE_CNT_HI_0_SECURE                     0x0
+#define EMC_STAT_DRAM_DEV1_ACTIVATE_CNT_HI_0_WORD_COUNT                         0x1
+#define EMC_STAT_DRAM_DEV1_ACTIVATE_CNT_HI_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_ACTIVATE_CNT_HI_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_ACTIVATE_CNT_HI_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_ACTIVATE_CNT_HI_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_ACTIVATE_CNT_HI_0_READ_MASK                  _MK_MASK_CONST(0xff)
+#define EMC_STAT_DRAM_DEV1_ACTIVATE_CNT_HI_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_ACTIVATE_CNT_HI_0_DEV1_ACTIVATE_CNT_HI_SHIFT                 _MK_SHIFT_CONST(0)
+#define EMC_STAT_DRAM_DEV1_ACTIVATE_CNT_HI_0_DEV1_ACTIVATE_CNT_HI_FIELD                 (_MK_MASK_CONST(0xff) << EMC_STAT_DRAM_DEV1_ACTIVATE_CNT_HI_0_DEV1_ACTIVATE_CNT_HI_SHIFT)
+#define EMC_STAT_DRAM_DEV1_ACTIVATE_CNT_HI_0_DEV1_ACTIVATE_CNT_HI_RANGE                 7:0
+#define EMC_STAT_DRAM_DEV1_ACTIVATE_CNT_HI_0_DEV1_ACTIVATE_CNT_HI_WOFFSET                       0x0
+#define EMC_STAT_DRAM_DEV1_ACTIVATE_CNT_HI_0_DEV1_ACTIVATE_CNT_HI_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_ACTIVATE_CNT_HI_0_DEV1_ACTIVATE_CNT_HI_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_ACTIVATE_CNT_HI_0_DEV1_ACTIVATE_CNT_HI_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_ACTIVATE_CNT_HI_0_DEV1_ACTIVATE_CNT_HI_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EMC_STAT_DRAM_DEV1_READ_CNT_LO_0  
+#define EMC_STAT_DRAM_DEV1_READ_CNT_LO_0                        _MK_ADDR_CONST(0x204)
+#define EMC_STAT_DRAM_DEV1_READ_CNT_LO_0_SECURE                         0x0
+#define EMC_STAT_DRAM_DEV1_READ_CNT_LO_0_WORD_COUNT                     0x1
+#define EMC_STAT_DRAM_DEV1_READ_CNT_LO_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_READ_CNT_LO_0_RESET_MASK                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_READ_CNT_LO_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_READ_CNT_LO_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_READ_CNT_LO_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_DRAM_DEV1_READ_CNT_LO_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_READ_CNT_LO_0_DEV1_READ_CNT_LO_SHIFT                 _MK_SHIFT_CONST(0)
+#define EMC_STAT_DRAM_DEV1_READ_CNT_LO_0_DEV1_READ_CNT_LO_FIELD                 (_MK_MASK_CONST(0xffffffff) << EMC_STAT_DRAM_DEV1_READ_CNT_LO_0_DEV1_READ_CNT_LO_SHIFT)
+#define EMC_STAT_DRAM_DEV1_READ_CNT_LO_0_DEV1_READ_CNT_LO_RANGE                 31:0
+#define EMC_STAT_DRAM_DEV1_READ_CNT_LO_0_DEV1_READ_CNT_LO_WOFFSET                       0x0
+#define EMC_STAT_DRAM_DEV1_READ_CNT_LO_0_DEV1_READ_CNT_LO_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_READ_CNT_LO_0_DEV1_READ_CNT_LO_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_READ_CNT_LO_0_DEV1_READ_CNT_LO_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_READ_CNT_LO_0_DEV1_READ_CNT_LO_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EMC_STAT_DRAM_DEV1_READ_CNT_HI_0  
+#define EMC_STAT_DRAM_DEV1_READ_CNT_HI_0                        _MK_ADDR_CONST(0x208)
+#define EMC_STAT_DRAM_DEV1_READ_CNT_HI_0_SECURE                         0x0
+#define EMC_STAT_DRAM_DEV1_READ_CNT_HI_0_WORD_COUNT                     0x1
+#define EMC_STAT_DRAM_DEV1_READ_CNT_HI_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_READ_CNT_HI_0_RESET_MASK                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_READ_CNT_HI_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_READ_CNT_HI_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_READ_CNT_HI_0_READ_MASK                      _MK_MASK_CONST(0xff)
+#define EMC_STAT_DRAM_DEV1_READ_CNT_HI_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_READ_CNT_HI_0_DEV1_READ_CNT_HI_SHIFT                 _MK_SHIFT_CONST(0)
+#define EMC_STAT_DRAM_DEV1_READ_CNT_HI_0_DEV1_READ_CNT_HI_FIELD                 (_MK_MASK_CONST(0xff) << EMC_STAT_DRAM_DEV1_READ_CNT_HI_0_DEV1_READ_CNT_HI_SHIFT)
+#define EMC_STAT_DRAM_DEV1_READ_CNT_HI_0_DEV1_READ_CNT_HI_RANGE                 7:0
+#define EMC_STAT_DRAM_DEV1_READ_CNT_HI_0_DEV1_READ_CNT_HI_WOFFSET                       0x0
+#define EMC_STAT_DRAM_DEV1_READ_CNT_HI_0_DEV1_READ_CNT_HI_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_READ_CNT_HI_0_DEV1_READ_CNT_HI_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_READ_CNT_HI_0_DEV1_READ_CNT_HI_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_READ_CNT_HI_0_DEV1_READ_CNT_HI_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EMC_STAT_DRAM_DEV1_WRITE_CNT_LO_0  
+#define EMC_STAT_DRAM_DEV1_WRITE_CNT_LO_0                       _MK_ADDR_CONST(0x20c)
+#define EMC_STAT_DRAM_DEV1_WRITE_CNT_LO_0_SECURE                        0x0
+#define EMC_STAT_DRAM_DEV1_WRITE_CNT_LO_0_WORD_COUNT                    0x1
+#define EMC_STAT_DRAM_DEV1_WRITE_CNT_LO_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_WRITE_CNT_LO_0_RESET_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_WRITE_CNT_LO_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_WRITE_CNT_LO_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_WRITE_CNT_LO_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_DRAM_DEV1_WRITE_CNT_LO_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_WRITE_CNT_LO_0_DEV1_WRITE_CNT_LO_SHIFT                       _MK_SHIFT_CONST(0)
+#define EMC_STAT_DRAM_DEV1_WRITE_CNT_LO_0_DEV1_WRITE_CNT_LO_FIELD                       (_MK_MASK_CONST(0xffffffff) << EMC_STAT_DRAM_DEV1_WRITE_CNT_LO_0_DEV1_WRITE_CNT_LO_SHIFT)
+#define EMC_STAT_DRAM_DEV1_WRITE_CNT_LO_0_DEV1_WRITE_CNT_LO_RANGE                       31:0
+#define EMC_STAT_DRAM_DEV1_WRITE_CNT_LO_0_DEV1_WRITE_CNT_LO_WOFFSET                     0x0
+#define EMC_STAT_DRAM_DEV1_WRITE_CNT_LO_0_DEV1_WRITE_CNT_LO_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_WRITE_CNT_LO_0_DEV1_WRITE_CNT_LO_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_WRITE_CNT_LO_0_DEV1_WRITE_CNT_LO_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_WRITE_CNT_LO_0_DEV1_WRITE_CNT_LO_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register EMC_STAT_DRAM_DEV1_WRITE_CNT_HI_0  
+#define EMC_STAT_DRAM_DEV1_WRITE_CNT_HI_0                       _MK_ADDR_CONST(0x210)
+#define EMC_STAT_DRAM_DEV1_WRITE_CNT_HI_0_SECURE                        0x0
+#define EMC_STAT_DRAM_DEV1_WRITE_CNT_HI_0_WORD_COUNT                    0x1
+#define EMC_STAT_DRAM_DEV1_WRITE_CNT_HI_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_WRITE_CNT_HI_0_RESET_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_WRITE_CNT_HI_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_WRITE_CNT_HI_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_WRITE_CNT_HI_0_READ_MASK                     _MK_MASK_CONST(0xff)
+#define EMC_STAT_DRAM_DEV1_WRITE_CNT_HI_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_WRITE_CNT_HI_0_DEV1_WRITE_CNT_HI_SHIFT                       _MK_SHIFT_CONST(0)
+#define EMC_STAT_DRAM_DEV1_WRITE_CNT_HI_0_DEV1_WRITE_CNT_HI_FIELD                       (_MK_MASK_CONST(0xff) << EMC_STAT_DRAM_DEV1_WRITE_CNT_HI_0_DEV1_WRITE_CNT_HI_SHIFT)
+#define EMC_STAT_DRAM_DEV1_WRITE_CNT_HI_0_DEV1_WRITE_CNT_HI_RANGE                       7:0
+#define EMC_STAT_DRAM_DEV1_WRITE_CNT_HI_0_DEV1_WRITE_CNT_HI_WOFFSET                     0x0
+#define EMC_STAT_DRAM_DEV1_WRITE_CNT_HI_0_DEV1_WRITE_CNT_HI_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_WRITE_CNT_HI_0_DEV1_WRITE_CNT_HI_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_WRITE_CNT_HI_0_DEV1_WRITE_CNT_HI_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_WRITE_CNT_HI_0_DEV1_WRITE_CNT_HI_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register EMC_STAT_DRAM_DEV1_REF_CNT_LO_0  
+#define EMC_STAT_DRAM_DEV1_REF_CNT_LO_0                 _MK_ADDR_CONST(0x214)
+#define EMC_STAT_DRAM_DEV1_REF_CNT_LO_0_SECURE                  0x0
+#define EMC_STAT_DRAM_DEV1_REF_CNT_LO_0_WORD_COUNT                      0x1
+#define EMC_STAT_DRAM_DEV1_REF_CNT_LO_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_REF_CNT_LO_0_RESET_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_REF_CNT_LO_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_REF_CNT_LO_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_REF_CNT_LO_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_DRAM_DEV1_REF_CNT_LO_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_REF_CNT_LO_0_DEV1_REF_CNT_LO_SHIFT                   _MK_SHIFT_CONST(0)
+#define EMC_STAT_DRAM_DEV1_REF_CNT_LO_0_DEV1_REF_CNT_LO_FIELD                   (_MK_MASK_CONST(0xffffffff) << EMC_STAT_DRAM_DEV1_REF_CNT_LO_0_DEV1_REF_CNT_LO_SHIFT)
+#define EMC_STAT_DRAM_DEV1_REF_CNT_LO_0_DEV1_REF_CNT_LO_RANGE                   31:0
+#define EMC_STAT_DRAM_DEV1_REF_CNT_LO_0_DEV1_REF_CNT_LO_WOFFSET                 0x0
+#define EMC_STAT_DRAM_DEV1_REF_CNT_LO_0_DEV1_REF_CNT_LO_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_REF_CNT_LO_0_DEV1_REF_CNT_LO_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_REF_CNT_LO_0_DEV1_REF_CNT_LO_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_REF_CNT_LO_0_DEV1_REF_CNT_LO_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register EMC_STAT_DRAM_DEV1_REF_CNT_HI_0  
+#define EMC_STAT_DRAM_DEV1_REF_CNT_HI_0                 _MK_ADDR_CONST(0x218)
+#define EMC_STAT_DRAM_DEV1_REF_CNT_HI_0_SECURE                  0x0
+#define EMC_STAT_DRAM_DEV1_REF_CNT_HI_0_WORD_COUNT                      0x1
+#define EMC_STAT_DRAM_DEV1_REF_CNT_HI_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_REF_CNT_HI_0_RESET_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_REF_CNT_HI_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_REF_CNT_HI_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_REF_CNT_HI_0_READ_MASK                       _MK_MASK_CONST(0xff)
+#define EMC_STAT_DRAM_DEV1_REF_CNT_HI_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_REF_CNT_HI_0_DEV1_REF_CNT_HI_SHIFT                   _MK_SHIFT_CONST(0)
+#define EMC_STAT_DRAM_DEV1_REF_CNT_HI_0_DEV1_REF_CNT_HI_FIELD                   (_MK_MASK_CONST(0xff) << EMC_STAT_DRAM_DEV1_REF_CNT_HI_0_DEV1_REF_CNT_HI_SHIFT)
+#define EMC_STAT_DRAM_DEV1_REF_CNT_HI_0_DEV1_REF_CNT_HI_RANGE                   7:0
+#define EMC_STAT_DRAM_DEV1_REF_CNT_HI_0_DEV1_REF_CNT_HI_WOFFSET                 0x0
+#define EMC_STAT_DRAM_DEV1_REF_CNT_HI_0_DEV1_REF_CNT_HI_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_REF_CNT_HI_0_DEV1_REF_CNT_HI_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_REF_CNT_HI_0_DEV1_REF_CNT_HI_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_REF_CNT_HI_0_DEV1_REF_CNT_HI_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ1_LO_0  
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ1_LO_0                       _MK_ADDR_CONST(0x21c)
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ1_LO_0_SECURE                        0x0
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ1_LO_0_WORD_COUNT                    0x1
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ1_LO_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ1_LO_0_RESET_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ1_LO_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ1_LO_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ1_LO_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ1_LO_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ1_LO_0_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ1_LO_SHIFT                       _MK_SHIFT_CONST(0)
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ1_LO_0_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ1_LO_FIELD                       (_MK_MASK_CONST(0xffffffff) << EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ1_LO_0_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ1_LO_SHIFT)
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ1_LO_0_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ1_LO_RANGE                       31:0
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ1_LO_0_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ1_LO_WOFFSET                     0x0
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ1_LO_0_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ1_LO_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ1_LO_0_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ1_LO_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ1_LO_0_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ1_LO_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ1_LO_0_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ1_LO_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ1_HI_0  
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ1_HI_0                       _MK_ADDR_CONST(0x220)
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ1_HI_0_SECURE                        0x0
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ1_HI_0_WORD_COUNT                    0x1
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ1_HI_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ1_HI_0_RESET_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ1_HI_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ1_HI_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ1_HI_0_READ_MASK                     _MK_MASK_CONST(0xff)
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ1_HI_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ1_HI_0_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ1_HI_SHIFT                       _MK_SHIFT_CONST(0)
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ1_HI_0_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ1_HI_FIELD                       (_MK_MASK_CONST(0xff) << EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ1_HI_0_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ1_HI_SHIFT)
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ1_HI_0_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ1_HI_RANGE                       7:0
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ1_HI_0_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ1_HI_WOFFSET                     0x0
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ1_HI_0_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ1_HI_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ1_HI_0_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ1_HI_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ1_HI_0_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ1_HI_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ1_HI_0_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ1_HI_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ0_LO_0  
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ0_LO_0                       _MK_ADDR_CONST(0x224)
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ0_LO_0_SECURE                        0x0
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ0_LO_0_WORD_COUNT                    0x1
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ0_LO_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ0_LO_0_RESET_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ0_LO_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ0_LO_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ0_LO_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ0_LO_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ0_LO_0_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ0_LO_SHIFT                       _MK_SHIFT_CONST(0)
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ0_LO_0_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ0_LO_FIELD                       (_MK_MASK_CONST(0xffffffff) << EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ0_LO_0_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ0_LO_SHIFT)
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ0_LO_0_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ0_LO_RANGE                       31:0
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ0_LO_0_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ0_LO_WOFFSET                     0x0
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ0_LO_0_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ0_LO_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ0_LO_0_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ0_LO_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ0_LO_0_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ0_LO_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ0_LO_0_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ0_LO_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ0_HI_0  
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ0_HI_0                       _MK_ADDR_CONST(0x228)
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ0_HI_0_SECURE                        0x0
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ0_HI_0_WORD_COUNT                    0x1
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ0_HI_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ0_HI_0_RESET_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ0_HI_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ0_HI_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ0_HI_0_READ_MASK                     _MK_MASK_CONST(0xff)
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ0_HI_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ0_HI_0_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ0_HI_SHIFT                       _MK_SHIFT_CONST(0)
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ0_HI_0_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ0_HI_FIELD                       (_MK_MASK_CONST(0xff) << EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ0_HI_0_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ0_HI_SHIFT)
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ0_HI_0_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ0_HI_RANGE                       7:0
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ0_HI_0_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ0_HI_WOFFSET                     0x0
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ0_HI_0_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ0_HI_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ0_HI_0_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ0_HI_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ0_HI_0_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ0_HI_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ0_HI_0_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ0_HI_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register EMC_STAT_DRAM_DEV1_CKE_EQ1_CLKS_LO_0  
+#define EMC_STAT_DRAM_DEV1_CKE_EQ1_CLKS_LO_0                    _MK_ADDR_CONST(0x22c)
+#define EMC_STAT_DRAM_DEV1_CKE_EQ1_CLKS_LO_0_SECURE                     0x0
+#define EMC_STAT_DRAM_DEV1_CKE_EQ1_CLKS_LO_0_WORD_COUNT                         0x1
+#define EMC_STAT_DRAM_DEV1_CKE_EQ1_CLKS_LO_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_CKE_EQ1_CLKS_LO_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_CKE_EQ1_CLKS_LO_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_CKE_EQ1_CLKS_LO_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_CKE_EQ1_CLKS_LO_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_DRAM_DEV1_CKE_EQ1_CLKS_LO_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_CKE_EQ1_CLKS_LO_0_DEV1_CKE_EQ1_CLKS_LO_SHIFT                 _MK_SHIFT_CONST(0)
+#define EMC_STAT_DRAM_DEV1_CKE_EQ1_CLKS_LO_0_DEV1_CKE_EQ1_CLKS_LO_FIELD                 (_MK_MASK_CONST(0xffffffff) << EMC_STAT_DRAM_DEV1_CKE_EQ1_CLKS_LO_0_DEV1_CKE_EQ1_CLKS_LO_SHIFT)
+#define EMC_STAT_DRAM_DEV1_CKE_EQ1_CLKS_LO_0_DEV1_CKE_EQ1_CLKS_LO_RANGE                 31:0
+#define EMC_STAT_DRAM_DEV1_CKE_EQ1_CLKS_LO_0_DEV1_CKE_EQ1_CLKS_LO_WOFFSET                       0x0
+#define EMC_STAT_DRAM_DEV1_CKE_EQ1_CLKS_LO_0_DEV1_CKE_EQ1_CLKS_LO_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_CKE_EQ1_CLKS_LO_0_DEV1_CKE_EQ1_CLKS_LO_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_CKE_EQ1_CLKS_LO_0_DEV1_CKE_EQ1_CLKS_LO_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_CKE_EQ1_CLKS_LO_0_DEV1_CKE_EQ1_CLKS_LO_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EMC_STAT_DRAM_DEV1_CKE_EQ1_CLKS_HI_0  
+#define EMC_STAT_DRAM_DEV1_CKE_EQ1_CLKS_HI_0                    _MK_ADDR_CONST(0x230)
+#define EMC_STAT_DRAM_DEV1_CKE_EQ1_CLKS_HI_0_SECURE                     0x0
+#define EMC_STAT_DRAM_DEV1_CKE_EQ1_CLKS_HI_0_WORD_COUNT                         0x1
+#define EMC_STAT_DRAM_DEV1_CKE_EQ1_CLKS_HI_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_CKE_EQ1_CLKS_HI_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_CKE_EQ1_CLKS_HI_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_CKE_EQ1_CLKS_HI_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_CKE_EQ1_CLKS_HI_0_READ_MASK                  _MK_MASK_CONST(0xff)
+#define EMC_STAT_DRAM_DEV1_CKE_EQ1_CLKS_HI_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_CKE_EQ1_CLKS_HI_0_DEV1_CKE_EQ1_CLKS_HI_SHIFT                 _MK_SHIFT_CONST(0)
+#define EMC_STAT_DRAM_DEV1_CKE_EQ1_CLKS_HI_0_DEV1_CKE_EQ1_CLKS_HI_FIELD                 (_MK_MASK_CONST(0xff) << EMC_STAT_DRAM_DEV1_CKE_EQ1_CLKS_HI_0_DEV1_CKE_EQ1_CLKS_HI_SHIFT)
+#define EMC_STAT_DRAM_DEV1_CKE_EQ1_CLKS_HI_0_DEV1_CKE_EQ1_CLKS_HI_RANGE                 7:0
+#define EMC_STAT_DRAM_DEV1_CKE_EQ1_CLKS_HI_0_DEV1_CKE_EQ1_CLKS_HI_WOFFSET                       0x0
+#define EMC_STAT_DRAM_DEV1_CKE_EQ1_CLKS_HI_0_DEV1_CKE_EQ1_CLKS_HI_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_CKE_EQ1_CLKS_HI_0_DEV1_CKE_EQ1_CLKS_HI_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_CKE_EQ1_CLKS_HI_0_DEV1_CKE_EQ1_CLKS_HI_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_CKE_EQ1_CLKS_HI_0_DEV1_CKE_EQ1_CLKS_HI_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ1_LO_0  
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ1_LO_0                 _MK_ADDR_CONST(0x234)
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ1_LO_0_SECURE                  0x0
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ1_LO_0_WORD_COUNT                      0x1
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ1_LO_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ1_LO_0_RESET_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ1_LO_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ1_LO_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ1_LO_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ1_LO_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ1_LO_0_DEV1_EXTCLKS_CKE_EQ1_LO_SHIFT                   _MK_SHIFT_CONST(0)
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ1_LO_0_DEV1_EXTCLKS_CKE_EQ1_LO_FIELD                   (_MK_MASK_CONST(0xffffffff) << EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ1_LO_0_DEV1_EXTCLKS_CKE_EQ1_LO_SHIFT)
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ1_LO_0_DEV1_EXTCLKS_CKE_EQ1_LO_RANGE                   31:0
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ1_LO_0_DEV1_EXTCLKS_CKE_EQ1_LO_WOFFSET                 0x0
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ1_LO_0_DEV1_EXTCLKS_CKE_EQ1_LO_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ1_LO_0_DEV1_EXTCLKS_CKE_EQ1_LO_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ1_LO_0_DEV1_EXTCLKS_CKE_EQ1_LO_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ1_LO_0_DEV1_EXTCLKS_CKE_EQ1_LO_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ1_HI_0  
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ1_HI_0                 _MK_ADDR_CONST(0x238)
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ1_HI_0_SECURE                  0x0
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ1_HI_0_WORD_COUNT                      0x1
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ1_HI_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ1_HI_0_RESET_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ1_HI_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ1_HI_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ1_HI_0_READ_MASK                       _MK_MASK_CONST(0xff)
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ1_HI_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ1_HI_0_DEV1_EXTCLKS_CKE_EQ1_HI_SHIFT                   _MK_SHIFT_CONST(0)
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ1_HI_0_DEV1_EXTCLKS_CKE_EQ1_HI_FIELD                   (_MK_MASK_CONST(0xff) << EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ1_HI_0_DEV1_EXTCLKS_CKE_EQ1_HI_SHIFT)
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ1_HI_0_DEV1_EXTCLKS_CKE_EQ1_HI_RANGE                   7:0
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ1_HI_0_DEV1_EXTCLKS_CKE_EQ1_HI_WOFFSET                 0x0
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ1_HI_0_DEV1_EXTCLKS_CKE_EQ1_HI_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ1_HI_0_DEV1_EXTCLKS_CKE_EQ1_HI_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ1_HI_0_DEV1_EXTCLKS_CKE_EQ1_HI_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ1_HI_0_DEV1_EXTCLKS_CKE_EQ1_HI_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ0_LO_0  
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ0_LO_0                 _MK_ADDR_CONST(0x23c)
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ0_LO_0_SECURE                  0x0
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ0_LO_0_WORD_COUNT                      0x1
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ0_LO_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ0_LO_0_RESET_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ0_LO_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ0_LO_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ0_LO_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ0_LO_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ0_LO_0_DEV1_EXTCLKS_CKE_EQ0_LO_SHIFT                   _MK_SHIFT_CONST(0)
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ0_LO_0_DEV1_EXTCLKS_CKE_EQ0_LO_FIELD                   (_MK_MASK_CONST(0xffffffff) << EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ0_LO_0_DEV1_EXTCLKS_CKE_EQ0_LO_SHIFT)
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ0_LO_0_DEV1_EXTCLKS_CKE_EQ0_LO_RANGE                   31:0
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ0_LO_0_DEV1_EXTCLKS_CKE_EQ0_LO_WOFFSET                 0x0
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ0_LO_0_DEV1_EXTCLKS_CKE_EQ0_LO_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ0_LO_0_DEV1_EXTCLKS_CKE_EQ0_LO_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ0_LO_0_DEV1_EXTCLKS_CKE_EQ0_LO_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ0_LO_0_DEV1_EXTCLKS_CKE_EQ0_LO_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ0_HI_0  
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ0_HI_0                 _MK_ADDR_CONST(0x240)
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ0_HI_0_SECURE                  0x0
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ0_HI_0_WORD_COUNT                      0x1
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ0_HI_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ0_HI_0_RESET_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ0_HI_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ0_HI_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ0_HI_0_READ_MASK                       _MK_MASK_CONST(0xff)
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ0_HI_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ0_HI_0_DEV1_EXTCLKS_CKE_EQ0_HI_SHIFT                   _MK_SHIFT_CONST(0)
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ0_HI_0_DEV1_EXTCLKS_CKE_EQ0_HI_FIELD                   (_MK_MASK_CONST(0xff) << EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ0_HI_0_DEV1_EXTCLKS_CKE_EQ0_HI_SHIFT)
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ0_HI_0_DEV1_EXTCLKS_CKE_EQ0_HI_RANGE                   7:0
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ0_HI_0_DEV1_EXTCLKS_CKE_EQ0_HI_WOFFSET                 0x0
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ0_HI_0_DEV1_EXTCLKS_CKE_EQ0_HI_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ0_HI_0_DEV1_EXTCLKS_CKE_EQ0_HI_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ0_HI_0_DEV1_EXTCLKS_CKE_EQ0_HI_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ0_HI_0_DEV1_EXTCLKS_CKE_EQ0_HI_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ1_LO_0  
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ1_LO_0                 _MK_ADDR_CONST(0x244)
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ1_LO_0_SECURE                  0x0
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ1_LO_0_WORD_COUNT                      0x1
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ1_LO_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ1_LO_0_RESET_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ1_LO_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ1_LO_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ1_LO_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ1_LO_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ1_LO_0_DEV0_NO_BANKS_ACTIVE_CKE_EQ1_LO_SHIFT                   _MK_SHIFT_CONST(0)
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ1_LO_0_DEV0_NO_BANKS_ACTIVE_CKE_EQ1_LO_FIELD                   (_MK_MASK_CONST(0xffffffff) << EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ1_LO_0_DEV0_NO_BANKS_ACTIVE_CKE_EQ1_LO_SHIFT)
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ1_LO_0_DEV0_NO_BANKS_ACTIVE_CKE_EQ1_LO_RANGE                   31:0
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ1_LO_0_DEV0_NO_BANKS_ACTIVE_CKE_EQ1_LO_WOFFSET                 0x0
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ1_LO_0_DEV0_NO_BANKS_ACTIVE_CKE_EQ1_LO_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ1_LO_0_DEV0_NO_BANKS_ACTIVE_CKE_EQ1_LO_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ1_LO_0_DEV0_NO_BANKS_ACTIVE_CKE_EQ1_LO_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ1_LO_0_DEV0_NO_BANKS_ACTIVE_CKE_EQ1_LO_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ1_HI_0  
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ1_HI_0                 _MK_ADDR_CONST(0x248)
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ1_HI_0_SECURE                  0x0
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ1_HI_0_WORD_COUNT                      0x1
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ1_HI_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ1_HI_0_RESET_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ1_HI_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ1_HI_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ1_HI_0_READ_MASK                       _MK_MASK_CONST(0xff)
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ1_HI_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ1_HI_0_DEV0_NO_BANKS_ACTIVE_CKE_EQ1_HI_SHIFT                   _MK_SHIFT_CONST(0)
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ1_HI_0_DEV0_NO_BANKS_ACTIVE_CKE_EQ1_HI_FIELD                   (_MK_MASK_CONST(0xff) << EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ1_HI_0_DEV0_NO_BANKS_ACTIVE_CKE_EQ1_HI_SHIFT)
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ1_HI_0_DEV0_NO_BANKS_ACTIVE_CKE_EQ1_HI_RANGE                   7:0
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ1_HI_0_DEV0_NO_BANKS_ACTIVE_CKE_EQ1_HI_WOFFSET                 0x0
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ1_HI_0_DEV0_NO_BANKS_ACTIVE_CKE_EQ1_HI_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ1_HI_0_DEV0_NO_BANKS_ACTIVE_CKE_EQ1_HI_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ1_HI_0_DEV0_NO_BANKS_ACTIVE_CKE_EQ1_HI_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ1_HI_0_DEV0_NO_BANKS_ACTIVE_CKE_EQ1_HI_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ0_LO_0  
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ0_LO_0                 _MK_ADDR_CONST(0x24c)
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ0_LO_0_SECURE                  0x0
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ0_LO_0_WORD_COUNT                      0x1
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ0_LO_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ0_LO_0_RESET_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ0_LO_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ0_LO_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ0_LO_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ0_LO_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ0_LO_0_DEV0_NO_BANKS_ACTIVE_CKE_EQ0_LO_SHIFT                   _MK_SHIFT_CONST(0)
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ0_LO_0_DEV0_NO_BANKS_ACTIVE_CKE_EQ0_LO_FIELD                   (_MK_MASK_CONST(0xffffffff) << EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ0_LO_0_DEV0_NO_BANKS_ACTIVE_CKE_EQ0_LO_SHIFT)
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ0_LO_0_DEV0_NO_BANKS_ACTIVE_CKE_EQ0_LO_RANGE                   31:0
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ0_LO_0_DEV0_NO_BANKS_ACTIVE_CKE_EQ0_LO_WOFFSET                 0x0
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ0_LO_0_DEV0_NO_BANKS_ACTIVE_CKE_EQ0_LO_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ0_LO_0_DEV0_NO_BANKS_ACTIVE_CKE_EQ0_LO_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ0_LO_0_DEV0_NO_BANKS_ACTIVE_CKE_EQ0_LO_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ0_LO_0_DEV0_NO_BANKS_ACTIVE_CKE_EQ0_LO_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ0_HI_0  
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ0_HI_0                 _MK_ADDR_CONST(0x250)
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ0_HI_0_SECURE                  0x0
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ0_HI_0_WORD_COUNT                      0x1
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ0_HI_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ0_HI_0_RESET_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ0_HI_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ0_HI_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ0_HI_0_READ_MASK                       _MK_MASK_CONST(0xff)
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ0_HI_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ0_HI_0_DEV0_NO_BANKS_ACTIVE_CKE_EQ0_HI_SHIFT                   _MK_SHIFT_CONST(0)
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ0_HI_0_DEV0_NO_BANKS_ACTIVE_CKE_EQ0_HI_FIELD                   (_MK_MASK_CONST(0xff) << EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ0_HI_0_DEV0_NO_BANKS_ACTIVE_CKE_EQ0_HI_SHIFT)
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ0_HI_0_DEV0_NO_BANKS_ACTIVE_CKE_EQ0_HI_RANGE                   7:0
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ0_HI_0_DEV0_NO_BANKS_ACTIVE_CKE_EQ0_HI_WOFFSET                 0x0
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ0_HI_0_DEV0_NO_BANKS_ACTIVE_CKE_EQ0_HI_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ0_HI_0_DEV0_NO_BANKS_ACTIVE_CKE_EQ0_HI_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ0_HI_0_DEV0_NO_BANKS_ACTIVE_CKE_EQ0_HI_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ0_HI_0_DEV0_NO_BANKS_ACTIVE_CKE_EQ0_HI_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ1_LO_0  
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ1_LO_0                 _MK_ADDR_CONST(0x254)
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ1_LO_0_SECURE                  0x0
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ1_LO_0_WORD_COUNT                      0x1
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ1_LO_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ1_LO_0_RESET_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ1_LO_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ1_LO_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ1_LO_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ1_LO_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ1_LO_0_DEV1_NO_BANKS_ACTIVE_CKE_EQ1_LO_SHIFT                   _MK_SHIFT_CONST(0)
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ1_LO_0_DEV1_NO_BANKS_ACTIVE_CKE_EQ1_LO_FIELD                   (_MK_MASK_CONST(0xffffffff) << EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ1_LO_0_DEV1_NO_BANKS_ACTIVE_CKE_EQ1_LO_SHIFT)
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ1_LO_0_DEV1_NO_BANKS_ACTIVE_CKE_EQ1_LO_RANGE                   31:0
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ1_LO_0_DEV1_NO_BANKS_ACTIVE_CKE_EQ1_LO_WOFFSET                 0x0
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ1_LO_0_DEV1_NO_BANKS_ACTIVE_CKE_EQ1_LO_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ1_LO_0_DEV1_NO_BANKS_ACTIVE_CKE_EQ1_LO_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ1_LO_0_DEV1_NO_BANKS_ACTIVE_CKE_EQ1_LO_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ1_LO_0_DEV1_NO_BANKS_ACTIVE_CKE_EQ1_LO_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ1_HI_0  
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ1_HI_0                 _MK_ADDR_CONST(0x258)
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ1_HI_0_SECURE                  0x0
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ1_HI_0_WORD_COUNT                      0x1
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ1_HI_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ1_HI_0_RESET_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ1_HI_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ1_HI_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ1_HI_0_READ_MASK                       _MK_MASK_CONST(0xff)
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ1_HI_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ1_HI_0_DEV1_NO_BANKS_ACTIVE_CKE_EQ1_HI_SHIFT                   _MK_SHIFT_CONST(0)
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ1_HI_0_DEV1_NO_BANKS_ACTIVE_CKE_EQ1_HI_FIELD                   (_MK_MASK_CONST(0xff) << EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ1_HI_0_DEV1_NO_BANKS_ACTIVE_CKE_EQ1_HI_SHIFT)
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ1_HI_0_DEV1_NO_BANKS_ACTIVE_CKE_EQ1_HI_RANGE                   7:0
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ1_HI_0_DEV1_NO_BANKS_ACTIVE_CKE_EQ1_HI_WOFFSET                 0x0
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ1_HI_0_DEV1_NO_BANKS_ACTIVE_CKE_EQ1_HI_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ1_HI_0_DEV1_NO_BANKS_ACTIVE_CKE_EQ1_HI_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ1_HI_0_DEV1_NO_BANKS_ACTIVE_CKE_EQ1_HI_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ1_HI_0_DEV1_NO_BANKS_ACTIVE_CKE_EQ1_HI_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ0_LO_0  
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ0_LO_0                 _MK_ADDR_CONST(0x25c)
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ0_LO_0_SECURE                  0x0
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ0_LO_0_WORD_COUNT                      0x1
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ0_LO_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ0_LO_0_RESET_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ0_LO_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ0_LO_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ0_LO_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ0_LO_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ0_LO_0_DEV1_NO_BANKS_ACTIVE_CKE_EQ0_LO_SHIFT                   _MK_SHIFT_CONST(0)
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ0_LO_0_DEV1_NO_BANKS_ACTIVE_CKE_EQ0_LO_FIELD                   (_MK_MASK_CONST(0xffffffff) << EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ0_LO_0_DEV1_NO_BANKS_ACTIVE_CKE_EQ0_LO_SHIFT)
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ0_LO_0_DEV1_NO_BANKS_ACTIVE_CKE_EQ0_LO_RANGE                   31:0
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ0_LO_0_DEV1_NO_BANKS_ACTIVE_CKE_EQ0_LO_WOFFSET                 0x0
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ0_LO_0_DEV1_NO_BANKS_ACTIVE_CKE_EQ0_LO_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ0_LO_0_DEV1_NO_BANKS_ACTIVE_CKE_EQ0_LO_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ0_LO_0_DEV1_NO_BANKS_ACTIVE_CKE_EQ0_LO_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ0_LO_0_DEV1_NO_BANKS_ACTIVE_CKE_EQ0_LO_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ0_HI_0  
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ0_HI_0                 _MK_ADDR_CONST(0x260)
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ0_HI_0_SECURE                  0x0
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ0_HI_0_WORD_COUNT                      0x1
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ0_HI_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ0_HI_0_RESET_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ0_HI_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ0_HI_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ0_HI_0_READ_MASK                       _MK_MASK_CONST(0xff)
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ0_HI_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ0_HI_0_DEV1_NO_BANKS_ACTIVE_CKE_EQ0_HI_SHIFT                   _MK_SHIFT_CONST(0)
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ0_HI_0_DEV1_NO_BANKS_ACTIVE_CKE_EQ0_HI_FIELD                   (_MK_MASK_CONST(0xff) << EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ0_HI_0_DEV1_NO_BANKS_ACTIVE_CKE_EQ0_HI_SHIFT)
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ0_HI_0_DEV1_NO_BANKS_ACTIVE_CKE_EQ0_HI_RANGE                   7:0
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ0_HI_0_DEV1_NO_BANKS_ACTIVE_CKE_EQ0_HI_WOFFSET                 0x0
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ0_HI_0_DEV1_NO_BANKS_ACTIVE_CKE_EQ0_HI_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ0_HI_0_DEV1_NO_BANKS_ACTIVE_CKE_EQ0_HI_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ0_HI_0_DEV1_NO_BANKS_ACTIVE_CKE_EQ0_HI_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ0_HI_0_DEV1_NO_BANKS_ACTIVE_CKE_EQ0_HI_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Reserved address 612 [0x264] 
+
+// Reserved address 616 [0x268] 
+
+// Reserved address 620 [0x26c] 
+
+// Reserved address 624 [0x270] 
+
+// Reserved address 628 [0x274] 
+
+// Reserved address 632 [0x278] 
+
+// Reserved address 636 [0x27c] 
+
+// Reserved address 640 [0x280] 
+
+// Reserved address 644 [0x284] 
+
+// Reserved address 648 [0x288] 
+
+// Reserved address 652 [0x28c] 
+
+// Reserved address 656 [0x290] 
+
+// Reserved address 660 [0x294] 
+
+// Reserved address 664 [0x298] 
+
+// Reserved address 668 [0x29c] 
+
+// Reserved address 672 [0x2a0] 
+
+// Register EMC_AUTO_CAL_CONFIG_0  // Auto-calibration settings for EMC pads
+#define EMC_AUTO_CAL_CONFIG_0                   _MK_ADDR_CONST(0x2a4)
+#define EMC_AUTO_CAL_CONFIG_0_SECURE                    0x0
+#define EMC_AUTO_CAL_CONFIG_0_WORD_COUNT                        0x1
+#define EMC_AUTO_CAL_CONFIG_0_RESET_VAL                         _MK_MASK_CONST(0xa60000)
+#define EMC_AUTO_CAL_CONFIG_0_RESET_MASK                        _MK_MASK_CONST(0xf3ff1f1f)
+#define EMC_AUTO_CAL_CONFIG_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_CONFIG_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_CONFIG_0_READ_MASK                         _MK_MASK_CONST(0xf3ff1f1f)
+#define EMC_AUTO_CAL_CONFIG_0_WRITE_MASK                        _MK_MASK_CONST(0x73ff1f1f)
+// 2's complement offset for pull-up value
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_PU_OFFSET_SHIFT                  _MK_SHIFT_CONST(0)
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_PU_OFFSET_FIELD                  (_MK_MASK_CONST(0x1f) << EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_PU_OFFSET_SHIFT)
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_PU_OFFSET_RANGE                  4:0
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_PU_OFFSET_WOFFSET                        0x0
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_PU_OFFSET_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_PU_OFFSET_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_PU_OFFSET_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_PU_OFFSET_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// 2's complement offset for pull-down value
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_PD_OFFSET_SHIFT                  _MK_SHIFT_CONST(8)
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_PD_OFFSET_FIELD                  (_MK_MASK_CONST(0x1f) << EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_PD_OFFSET_SHIFT)
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_PD_OFFSET_RANGE                  12:8
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_PD_OFFSET_WOFFSET                        0x0
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_PD_OFFSET_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_PD_OFFSET_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_PD_OFFSET_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_PD_OFFSET_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Auto Cal calibration step interval (in emc clocks)
+// - the default is set for 1.0us calibration step at 166MHz
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_STEP_SHIFT                       _MK_SHIFT_CONST(16)
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_STEP_FIELD                       (_MK_MASK_CONST(0x3ff) << EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_STEP_SHIFT)
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_STEP_RANGE                       25:16
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_STEP_WOFFSET                     0x0
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_STEP_DEFAULT                     _MK_MASK_CONST(0xa6)
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_STEP_DEFAULT_MASK                        _MK_MASK_CONST(0x3ff)
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_STEP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_STEP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// 0 (Normal operation) pad DRVDN/UP_SLWR/F tied to AUTO_CAL output
+//                      DRDVDN/UP_SLWR/F[3:0] = AUTO_CAL_PULLDOWN/UP[4:1]
+// 1 (override) use CFG2TMC_*_DRVDN/UP_SLWR/F pins to control pad slew inputs
+#define EMC_AUTO_CAL_CONFIG_0_AUTOCAL_SLW_OVERRIDE_SHIFT                        _MK_SHIFT_CONST(28)
+#define EMC_AUTO_CAL_CONFIG_0_AUTOCAL_SLW_OVERRIDE_FIELD                        (_MK_MASK_CONST(0x1) << EMC_AUTO_CAL_CONFIG_0_AUTOCAL_SLW_OVERRIDE_SHIFT)
+#define EMC_AUTO_CAL_CONFIG_0_AUTOCAL_SLW_OVERRIDE_RANGE                        28:28
+#define EMC_AUTO_CAL_CONFIG_0_AUTOCAL_SLW_OVERRIDE_WOFFSET                      0x0
+#define EMC_AUTO_CAL_CONFIG_0_AUTOCAL_SLW_OVERRIDE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_CONFIG_0_AUTOCAL_SLW_OVERRIDE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define EMC_AUTO_CAL_CONFIG_0_AUTOCAL_SLW_OVERRIDE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_CONFIG_0_AUTOCAL_SLW_OVERRIDE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// 1 (normal operation): use EMC generated pullup/dn (override or autocal) 0 (disabled): use cfg2tmc_xm2* register settings for pullup/dn
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_ENABLE_SHIFT                     _MK_SHIFT_CONST(29)
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_ENABLE_FIELD                     (_MK_MASK_CONST(0x1) << EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_ENABLE_SHIFT)
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_ENABLE_RANGE                     29:29
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_ENABLE_WOFFSET                   0x0
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_ENABLE_INIT_ENUM                 DISABLED
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_ENABLE_DISABLED                  _MK_ENUM_CONST(0)
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_ENABLE_ENABLED                   _MK_ENUM_CONST(1)
+
+// 0 (normal operation): use AUTO_CAL_PU/PD_OFFSET as an offset 
+//                       to the calibration tate machine setting
+// 1 (override)        : use AUTO_CAL_PU/PD_OFFSET register 
+//                       values directly
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_OVERRIDE_SHIFT                   _MK_SHIFT_CONST(30)
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_OVERRIDE_FIELD                   (_MK_MASK_CONST(0x1) << EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_OVERRIDE_SHIFT)
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_OVERRIDE_RANGE                   30:30
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_OVERRIDE_WOFFSET                 0x0
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_OVERRIDE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_OVERRIDE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_OVERRIDE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_OVERRIDE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Writing a one to this bit starts the calibration state
+// machine.  This bit must be set even if the override is
+// set in order to latch in the override value.
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_START_SHIFT                      _MK_SHIFT_CONST(31)
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_START_FIELD                      (_MK_MASK_CONST(0x1) << EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_START_SHIFT)
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_START_RANGE                      31:31
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_START_WOFFSET                    0x0
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_START_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_START_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_START_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_START_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register EMC_AUTO_CAL_INTERVAL_0  // EMC pad calibration interval
+#define EMC_AUTO_CAL_INTERVAL_0                 _MK_ADDR_CONST(0x2a8)
+#define EMC_AUTO_CAL_INTERVAL_0_SECURE                  0x0
+#define EMC_AUTO_CAL_INTERVAL_0_WORD_COUNT                      0x1
+#define EMC_AUTO_CAL_INTERVAL_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_INTERVAL_0_RESET_MASK                      _MK_MASK_CONST(0xfffffff)
+#define EMC_AUTO_CAL_INTERVAL_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_INTERVAL_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_INTERVAL_0_READ_MASK                       _MK_MASK_CONST(0xfffffff)
+#define EMC_AUTO_CAL_INTERVAL_0_WRITE_MASK                      _MK_MASK_CONST(0xfffffff)
+// 0: do calibration once
+// Otherwise, auto-calibration occurs at intervals equivalent
+// to the programmed number of cycles.
+#define EMC_AUTO_CAL_INTERVAL_0_AUTO_CAL_INTERVAL_SHIFT                 _MK_SHIFT_CONST(0)
+#define EMC_AUTO_CAL_INTERVAL_0_AUTO_CAL_INTERVAL_FIELD                 (_MK_MASK_CONST(0xfffffff) << EMC_AUTO_CAL_INTERVAL_0_AUTO_CAL_INTERVAL_SHIFT)
+#define EMC_AUTO_CAL_INTERVAL_0_AUTO_CAL_INTERVAL_RANGE                 27:0
+#define EMC_AUTO_CAL_INTERVAL_0_AUTO_CAL_INTERVAL_WOFFSET                       0x0
+#define EMC_AUTO_CAL_INTERVAL_0_AUTO_CAL_INTERVAL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_INTERVAL_0_AUTO_CAL_INTERVAL_DEFAULT_MASK                  _MK_MASK_CONST(0xfffffff)
+#define EMC_AUTO_CAL_INTERVAL_0_AUTO_CAL_INTERVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_INTERVAL_0_AUTO_CAL_INTERVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EMC_AUTO_CAL_STATUS_0  // EMC pad calibration status
+#define EMC_AUTO_CAL_STATUS_0                   _MK_ADDR_CONST(0x2ac)
+#define EMC_AUTO_CAL_STATUS_0_SECURE                    0x0
+#define EMC_AUTO_CAL_STATUS_0_WORD_COUNT                        0x1
+#define EMC_AUTO_CAL_STATUS_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_STATUS_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_STATUS_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_STATUS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_STATUS_0_READ_MASK                         _MK_MASK_CONST(0x9f1f1f1f)
+#define EMC_AUTO_CAL_STATUS_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+// Pullup code generated by auto-calibration
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLUP_SHIFT                     _MK_SHIFT_CONST(0)
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLUP_FIELD                     (_MK_MASK_CONST(0x1f) << EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLUP_SHIFT)
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLUP_RANGE                     4:0
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLUP_WOFFSET                   0x0
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLUP_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLUP_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLUP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLUP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Pulldown code generated by auto-calibration
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLDOWN_SHIFT                   _MK_SHIFT_CONST(8)
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLDOWN_FIELD                   (_MK_MASK_CONST(0x1f) << EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLDOWN_SHIFT)
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLDOWN_RANGE                   12:8
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLDOWN_WOFFSET                 0x0
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLDOWN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLDOWN_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLDOWN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLDOWN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Pullup code sent to pads
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLUP_ADJ_SHIFT                 _MK_SHIFT_CONST(16)
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLUP_ADJ_FIELD                 (_MK_MASK_CONST(0x1f) << EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLUP_ADJ_SHIFT)
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLUP_ADJ_RANGE                 20:16
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLUP_ADJ_WOFFSET                       0x0
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLUP_ADJ_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLUP_ADJ_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLUP_ADJ_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLUP_ADJ_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Pulldown code sent to pads
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLDOWN_ADJ_SHIFT                       _MK_SHIFT_CONST(24)
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLDOWN_ADJ_FIELD                       (_MK_MASK_CONST(0x1f) << EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLDOWN_ADJ_SHIFT)
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLDOWN_ADJ_RANGE                       28:24
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLDOWN_ADJ_WOFFSET                     0x0
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLDOWN_ADJ_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLDOWN_ADJ_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLDOWN_ADJ_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLDOWN_ADJ_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// One when auto calibrate is active
+// - valid only after auto calibrate sequence has 
+// completed (EMC_CAL_ACTIVE == 0)
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_ACTIVE_SHIFT                     _MK_SHIFT_CONST(31)
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_ACTIVE_FIELD                     (_MK_MASK_CONST(0x1) << EMC_AUTO_CAL_STATUS_0_AUTO_CAL_ACTIVE_SHIFT)
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_ACTIVE_RANGE                     31:31
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_ACTIVE_WOFFSET                   0x0
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_ACTIVE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_ACTIVE_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_ACTIVE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_ACTIVE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EMC_REQ_CTRL_0  // Request status/control
+#define EMC_REQ_CTRL_0                  _MK_ADDR_CONST(0x2b0)
+#define EMC_REQ_CTRL_0_SECURE                   0x0
+#define EMC_REQ_CTRL_0_WORD_COUNT                       0x1
+#define EMC_REQ_CTRL_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define EMC_REQ_CTRL_0_RESET_MASK                       _MK_MASK_CONST(0x3)
+#define EMC_REQ_CTRL_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define EMC_REQ_CTRL_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_REQ_CTRL_0_READ_MASK                        _MK_MASK_CONST(0x3)
+#define EMC_REQ_CTRL_0_WRITE_MASK                       _MK_MASK_CONST(0x3)
+// Stall incoming read transactions (1st non-LL read will stall all transactions)
+#define EMC_REQ_CTRL_0_STALL_ALL_READS_SHIFT                    _MK_SHIFT_CONST(0)
+#define EMC_REQ_CTRL_0_STALL_ALL_READS_FIELD                    (_MK_MASK_CONST(0x1) << EMC_REQ_CTRL_0_STALL_ALL_READS_SHIFT)
+#define EMC_REQ_CTRL_0_STALL_ALL_READS_RANGE                    0:0
+#define EMC_REQ_CTRL_0_STALL_ALL_READS_WOFFSET                  0x0
+#define EMC_REQ_CTRL_0_STALL_ALL_READS_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_REQ_CTRL_0_STALL_ALL_READS_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define EMC_REQ_CTRL_0_STALL_ALL_READS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_REQ_CTRL_0_STALL_ALL_READS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Stall incoming write transactions
+#define EMC_REQ_CTRL_0_STALL_ALL_WRITES_SHIFT                   _MK_SHIFT_CONST(1)
+#define EMC_REQ_CTRL_0_STALL_ALL_WRITES_FIELD                   (_MK_MASK_CONST(0x1) << EMC_REQ_CTRL_0_STALL_ALL_WRITES_SHIFT)
+#define EMC_REQ_CTRL_0_STALL_ALL_WRITES_RANGE                   1:1
+#define EMC_REQ_CTRL_0_STALL_ALL_WRITES_WOFFSET                 0x0
+#define EMC_REQ_CTRL_0_STALL_ALL_WRITES_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_REQ_CTRL_0_STALL_ALL_WRITES_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define EMC_REQ_CTRL_0_STALL_ALL_WRITES_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_REQ_CTRL_0_STALL_ALL_WRITES_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register EMC_EMC_STATUS_0  // EMC state-machine status
+#define EMC_EMC_STATUS_0                        _MK_ADDR_CONST(0x2b4)
+#define EMC_EMC_STATUS_0_SECURE                         0x0
+#define EMC_EMC_STATUS_0_WORD_COUNT                     0x1
+#define EMC_EMC_STATUS_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define EMC_EMC_STATUS_0_RESET_MASK                     _MK_MASK_CONST(0x0)
+#define EMC_EMC_STATUS_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define EMC_EMC_STATUS_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_EMC_STATUS_0_READ_MASK                      _MK_MASK_CONST(0x1f3337)
+#define EMC_EMC_STATUS_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
+// Request fifo is empty
+#define EMC_EMC_STATUS_0_EMC_REQ_FIFO_EMPTY_SHIFT                       _MK_SHIFT_CONST(0)
+#define EMC_EMC_STATUS_0_EMC_REQ_FIFO_EMPTY_FIELD                       (_MK_MASK_CONST(0x1) << EMC_EMC_STATUS_0_EMC_REQ_FIFO_EMPTY_SHIFT)
+#define EMC_EMC_STATUS_0_EMC_REQ_FIFO_EMPTY_RANGE                       0:0
+#define EMC_EMC_STATUS_0_EMC_REQ_FIFO_EMPTY_WOFFSET                     0x0
+#define EMC_EMC_STATUS_0_EMC_REQ_FIFO_EMPTY_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_EMC_STATUS_0_EMC_REQ_FIFO_EMPTY_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_EMC_STATUS_0_EMC_REQ_FIFO_EMPTY_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_EMC_STATUS_0_EMC_REQ_FIFO_EMPTY_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// LL Request fifo is empty
+#define EMC_EMC_STATUS_0_EMC_LL_REQ_FIFO_EMPTY_SHIFT                    _MK_SHIFT_CONST(1)
+#define EMC_EMC_STATUS_0_EMC_LL_REQ_FIFO_EMPTY_FIELD                    (_MK_MASK_CONST(0x1) << EMC_EMC_STATUS_0_EMC_LL_REQ_FIFO_EMPTY_SHIFT)
+#define EMC_EMC_STATUS_0_EMC_LL_REQ_FIFO_EMPTY_RANGE                    1:1
+#define EMC_EMC_STATUS_0_EMC_LL_REQ_FIFO_EMPTY_WOFFSET                  0x0
+#define EMC_EMC_STATUS_0_EMC_LL_REQ_FIFO_EMPTY_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_EMC_STATUS_0_EMC_LL_REQ_FIFO_EMPTY_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EMC_EMC_STATUS_0_EMC_LL_REQ_FIFO_EMPTY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_EMC_STATUS_0_EMC_LL_REQ_FIFO_EMPTY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// All non-stalled requests have completed 
+#define EMC_EMC_STATUS_0_NO_OUTSTANDING_TRANSACTIONS_SHIFT                      _MK_SHIFT_CONST(2)
+#define EMC_EMC_STATUS_0_NO_OUTSTANDING_TRANSACTIONS_FIELD                      (_MK_MASK_CONST(0x1) << EMC_EMC_STATUS_0_NO_OUTSTANDING_TRANSACTIONS_SHIFT)
+#define EMC_EMC_STATUS_0_NO_OUTSTANDING_TRANSACTIONS_RANGE                      2:2
+#define EMC_EMC_STATUS_0_NO_OUTSTANDING_TRANSACTIONS_WOFFSET                    0x0
+#define EMC_EMC_STATUS_0_NO_OUTSTANDING_TRANSACTIONS_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_EMC_STATUS_0_NO_OUTSTANDING_TRANSACTIONS_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_EMC_STATUS_0_NO_OUTSTANDING_TRANSACTIONS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_EMC_STATUS_0_NO_OUTSTANDING_TRANSACTIONS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// dev[n] has entered powerdown state (incoming req's will awaken if not stalled)
+#define EMC_EMC_STATUS_0_DRAM_IN_POWERDOWN_SHIFT                        _MK_SHIFT_CONST(4)
+#define EMC_EMC_STATUS_0_DRAM_IN_POWERDOWN_FIELD                        (_MK_MASK_CONST(0x3) << EMC_EMC_STATUS_0_DRAM_IN_POWERDOWN_SHIFT)
+#define EMC_EMC_STATUS_0_DRAM_IN_POWERDOWN_RANGE                        5:4
+#define EMC_EMC_STATUS_0_DRAM_IN_POWERDOWN_WOFFSET                      0x0
+#define EMC_EMC_STATUS_0_DRAM_IN_POWERDOWN_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_EMC_STATUS_0_DRAM_IN_POWERDOWN_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define EMC_EMC_STATUS_0_DRAM_IN_POWERDOWN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_EMC_STATUS_0_DRAM_IN_POWERDOWN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// dev[n] has been put into self-refresh (will remain until SR exit cmd).
+#define EMC_EMC_STATUS_0_DRAM_IN_SELF_REFRESH_SHIFT                     _MK_SHIFT_CONST(8)
+#define EMC_EMC_STATUS_0_DRAM_IN_SELF_REFRESH_FIELD                     (_MK_MASK_CONST(0x3) << EMC_EMC_STATUS_0_DRAM_IN_SELF_REFRESH_SHIFT)
+#define EMC_EMC_STATUS_0_DRAM_IN_SELF_REFRESH_RANGE                     9:8
+#define EMC_EMC_STATUS_0_DRAM_IN_SELF_REFRESH_WOFFSET                   0x0
+#define EMC_EMC_STATUS_0_DRAM_IN_SELF_REFRESH_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_EMC_STATUS_0_DRAM_IN_SELF_REFRESH_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_EMC_STATUS_0_DRAM_IN_SELF_REFRESH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_EMC_STATUS_0_DRAM_IN_SELF_REFRESH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// dev[n] has been put into deep powerdown state
+#define EMC_EMC_STATUS_0_DRAM_IN_DPD_SHIFT                      _MK_SHIFT_CONST(12)
+#define EMC_EMC_STATUS_0_DRAM_IN_DPD_FIELD                      (_MK_MASK_CONST(0x3) << EMC_EMC_STATUS_0_DRAM_IN_DPD_SHIFT)
+#define EMC_EMC_STATUS_0_DRAM_IN_DPD_RANGE                      13:12
+#define EMC_EMC_STATUS_0_DRAM_IN_DPD_WOFFSET                    0x0
+#define EMC_EMC_STATUS_0_DRAM_IN_DPD_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_EMC_STATUS_0_DRAM_IN_DPD_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_EMC_STATUS_0_DRAM_IN_DPD_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_EMC_STATUS_0_DRAM_IN_DPD_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// mrr fifospace available
+#define EMC_EMC_STATUS_0_MRR_FIFO_SPACE_SHIFT                   _MK_SHIFT_CONST(16)
+#define EMC_EMC_STATUS_0_MRR_FIFO_SPACE_FIELD                   (_MK_MASK_CONST(0xf) << EMC_EMC_STATUS_0_MRR_FIFO_SPACE_SHIFT)
+#define EMC_EMC_STATUS_0_MRR_FIFO_SPACE_RANGE                   19:16
+#define EMC_EMC_STATUS_0_MRR_FIFO_SPACE_WOFFSET                 0x0
+#define EMC_EMC_STATUS_0_MRR_FIFO_SPACE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_EMC_STATUS_0_MRR_FIFO_SPACE_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_EMC_STATUS_0_MRR_FIFO_SPACE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_EMC_STATUS_0_MRR_FIFO_SPACE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// mrr data available for reading
+#define EMC_EMC_STATUS_0_MRR_DIVLD_SHIFT                        _MK_SHIFT_CONST(20)
+#define EMC_EMC_STATUS_0_MRR_DIVLD_FIELD                        (_MK_MASK_CONST(0x1) << EMC_EMC_STATUS_0_MRR_DIVLD_SHIFT)
+#define EMC_EMC_STATUS_0_MRR_DIVLD_RANGE                        20:20
+#define EMC_EMC_STATUS_0_MRR_DIVLD_WOFFSET                      0x0
+#define EMC_EMC_STATUS_0_MRR_DIVLD_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_EMC_STATUS_0_MRR_DIVLD_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define EMC_EMC_STATUS_0_MRR_DIVLD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_EMC_STATUS_0_MRR_DIVLD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register EMC_CFG_2_0  // EMC Configuration
+#define EMC_CFG_2_0                     _MK_ADDR_CONST(0x2b8)
+#define EMC_CFG_2_0_SECURE                      0x0
+#define EMC_CFG_2_0_WORD_COUNT                  0x1
+#define EMC_CFG_2_0_RESET_VAL                   _MK_MASK_CONST(0x3)
+#define EMC_CFG_2_0_RESET_MASK                  _MK_MASK_CONST(0x80330707)
+#define EMC_CFG_2_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define EMC_CFG_2_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EMC_CFG_2_0_READ_MASK                   _MK_MASK_CONST(0x80330707)
+#define EMC_CFG_2_0_WRITE_MASK                  _MK_MASK_CONST(0x80330707)
+// allows EMC and CAR to handshake on PLL divider/source changes.
+#define EMC_CFG_2_0_CLKCHANGE_REQ_ENABLE_SHIFT                  _MK_SHIFT_CONST(0)
+#define EMC_CFG_2_0_CLKCHANGE_REQ_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << EMC_CFG_2_0_CLKCHANGE_REQ_ENABLE_SHIFT)
+#define EMC_CFG_2_0_CLKCHANGE_REQ_ENABLE_RANGE                  0:0
+#define EMC_CFG_2_0_CLKCHANGE_REQ_ENABLE_WOFFSET                        0x0
+#define EMC_CFG_2_0_CLKCHANGE_REQ_ENABLE_DEFAULT                        _MK_MASK_CONST(0x1)
+#define EMC_CFG_2_0_CLKCHANGE_REQ_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define EMC_CFG_2_0_CLKCHANGE_REQ_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_CFG_2_0_CLKCHANGE_REQ_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_CFG_2_0_CLKCHANGE_REQ_ENABLE_INIT_ENUM                      ENABLED
+#define EMC_CFG_2_0_CLKCHANGE_REQ_ENABLE_DISABLED                       _MK_ENUM_CONST(0)
+#define EMC_CFG_2_0_CLKCHANGE_REQ_ENABLE_ENABLED                        _MK_ENUM_CONST(1)
+
+// Forces dram into power-down during CLKCHANGE.
+#define EMC_CFG_2_0_CLKCHANGE_PD_ENABLE_SHIFT                   _MK_SHIFT_CONST(1)
+#define EMC_CFG_2_0_CLKCHANGE_PD_ENABLE_FIELD                   (_MK_MASK_CONST(0x1) << EMC_CFG_2_0_CLKCHANGE_PD_ENABLE_SHIFT)
+#define EMC_CFG_2_0_CLKCHANGE_PD_ENABLE_RANGE                   1:1
+#define EMC_CFG_2_0_CLKCHANGE_PD_ENABLE_WOFFSET                 0x0
+#define EMC_CFG_2_0_CLKCHANGE_PD_ENABLE_DEFAULT                 _MK_MASK_CONST(0x1)
+#define EMC_CFG_2_0_CLKCHANGE_PD_ENABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define EMC_CFG_2_0_CLKCHANGE_PD_ENABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_CFG_2_0_CLKCHANGE_PD_ENABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define EMC_CFG_2_0_CLKCHANGE_PD_ENABLE_INIT_ENUM                       ENABLED
+#define EMC_CFG_2_0_CLKCHANGE_PD_ENABLE_DISABLED                        _MK_ENUM_CONST(0)
+#define EMC_CFG_2_0_CLKCHANGE_PD_ENABLE_ENABLED                 _MK_ENUM_CONST(1)
+
+// Forces dram into self-refresh during CLKCHANGE.   Takes precedent over CLKCHANGE_PD_ENABLE if both are set.
+#define EMC_CFG_2_0_CLKCHANGE_SR_ENABLE_SHIFT                   _MK_SHIFT_CONST(2)
+#define EMC_CFG_2_0_CLKCHANGE_SR_ENABLE_FIELD                   (_MK_MASK_CONST(0x1) << EMC_CFG_2_0_CLKCHANGE_SR_ENABLE_SHIFT)
+#define EMC_CFG_2_0_CLKCHANGE_SR_ENABLE_RANGE                   2:2
+#define EMC_CFG_2_0_CLKCHANGE_SR_ENABLE_WOFFSET                 0x0
+#define EMC_CFG_2_0_CLKCHANGE_SR_ENABLE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_CFG_2_0_CLKCHANGE_SR_ENABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define EMC_CFG_2_0_CLKCHANGE_SR_ENABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_CFG_2_0_CLKCHANGE_SR_ENABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define EMC_CFG_2_0_CLKCHANGE_SR_ENABLE_INIT_ENUM                       DISABLED
+#define EMC_CFG_2_0_CLKCHANGE_SR_ENABLE_DISABLED                        _MK_ENUM_CONST(0)
+#define EMC_CFG_2_0_CLKCHANGE_SR_ENABLE_ENABLED                 _MK_ENUM_CONST(1)
+
+// Remaps address/command pins for LPDDR_POP ball-out otherwise    uses standard LPDDR2 pin configuration.
+#define EMC_CFG_2_0_PIN_CONFIG_SHIFT                    _MK_SHIFT_CONST(8)
+#define EMC_CFG_2_0_PIN_CONFIG_FIELD                    (_MK_MASK_CONST(0x3) << EMC_CFG_2_0_PIN_CONFIG_SHIFT)
+#define EMC_CFG_2_0_PIN_CONFIG_RANGE                    9:8
+#define EMC_CFG_2_0_PIN_CONFIG_WOFFSET                  0x0
+#define EMC_CFG_2_0_PIN_CONFIG_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_CFG_2_0_PIN_CONFIG_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define EMC_CFG_2_0_PIN_CONFIG_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_CFG_2_0_PIN_CONFIG_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_CFG_2_0_PIN_CONFIG_INIT_ENUM                        LPDDR2
+#define EMC_CFG_2_0_PIN_CONFIG_LPDDR2                   _MK_ENUM_CONST(0)
+#define EMC_CFG_2_0_PIN_CONFIG_LPDDR_POP                        _MK_ENUM_CONST(1)
+#define EMC_CFG_2_0_PIN_CONFIG_RESERVED                 _MK_ENUM_CONST(2)
+
+// Used to select source for DRAM clock.  If enabled, xm2_addr_mclk pins   instead of xm2_mclk.  the former is located adjacent to addr pins used
+//   in lpddr2 (for lower clk to addr skew).  If disabled, xm2_addr_mclk will
+//   be disabled & xm2_mclk will output DRAM clock (required for LPDDR_POP).
+#define EMC_CFG_2_0_USE_ADDR_CLK_SHIFT                  _MK_SHIFT_CONST(10)
+#define EMC_CFG_2_0_USE_ADDR_CLK_FIELD                  (_MK_MASK_CONST(0x1) << EMC_CFG_2_0_USE_ADDR_CLK_SHIFT)
+#define EMC_CFG_2_0_USE_ADDR_CLK_RANGE                  10:10
+#define EMC_CFG_2_0_USE_ADDR_CLK_WOFFSET                        0x0
+#define EMC_CFG_2_0_USE_ADDR_CLK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_CFG_2_0_USE_ADDR_CLK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define EMC_CFG_2_0_USE_ADDR_CLK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_CFG_2_0_USE_ADDR_CLK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_CFG_2_0_USE_ADDR_CLK_INIT_ENUM                      DISABLED
+#define EMC_CFG_2_0_USE_ADDR_CLK_DISABLED                       _MK_ENUM_CONST(0)
+#define EMC_CFG_2_0_USE_ADDR_CLK_ENABLED                        _MK_ENUM_CONST(1)
+
+// Indicates which AP bytelane is connected to DRAM byte 0 (over which MRR data is returned).
+#define EMC_CFG_2_0_MRR_BYTESEL_SHIFT                   _MK_SHIFT_CONST(16)
+#define EMC_CFG_2_0_MRR_BYTESEL_FIELD                   (_MK_MASK_CONST(0x3) << EMC_CFG_2_0_MRR_BYTESEL_SHIFT)
+#define EMC_CFG_2_0_MRR_BYTESEL_RANGE                   17:16
+#define EMC_CFG_2_0_MRR_BYTESEL_WOFFSET                 0x0
+#define EMC_CFG_2_0_MRR_BYTESEL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_CFG_2_0_MRR_BYTESEL_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define EMC_CFG_2_0_MRR_BYTESEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_CFG_2_0_MRR_BYTESEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// If using 2 X16 DRAM on a single CS to form 32-bit wide data,
+//   indicates which bytelane 2nd DRAM's byte 0 is connected to.
+#define EMC_CFG_2_0_MRR_BYTESEL_X16_SHIFT                       _MK_SHIFT_CONST(20)
+#define EMC_CFG_2_0_MRR_BYTESEL_X16_FIELD                       (_MK_MASK_CONST(0x3) << EMC_CFG_2_0_MRR_BYTESEL_X16_SHIFT)
+#define EMC_CFG_2_0_MRR_BYTESEL_X16_RANGE                       21:20
+#define EMC_CFG_2_0_MRR_BYTESEL_X16_WOFFSET                     0x0
+#define EMC_CFG_2_0_MRR_BYTESEL_X16_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_CFG_2_0_MRR_BYTESEL_X16_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define EMC_CFG_2_0_MRR_BYTESEL_X16_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_CFG_2_0_MRR_BYTESEL_X16_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// CYA bit, gives priority to activates over precharges,  determining which    (precharge/activate) is processed first if both are pending and unblocked.
+#define EMC_CFG_2_0_DRAMC_PRE_B4_ACT_SHIFT                      _MK_SHIFT_CONST(31)
+#define EMC_CFG_2_0_DRAMC_PRE_B4_ACT_FIELD                      (_MK_MASK_CONST(0x1) << EMC_CFG_2_0_DRAMC_PRE_B4_ACT_SHIFT)
+#define EMC_CFG_2_0_DRAMC_PRE_B4_ACT_RANGE                      31:31
+#define EMC_CFG_2_0_DRAMC_PRE_B4_ACT_WOFFSET                    0x0
+#define EMC_CFG_2_0_DRAMC_PRE_B4_ACT_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_CFG_2_0_DRAMC_PRE_B4_ACT_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define EMC_CFG_2_0_DRAMC_PRE_B4_ACT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_CFG_2_0_DRAMC_PRE_B4_ACT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_CFG_2_0_DRAMC_PRE_B4_ACT_INIT_ENUM                  DISABLED
+#define EMC_CFG_2_0_DRAMC_PRE_B4_ACT_DISABLED                   _MK_ENUM_CONST(0)
+#define EMC_CFG_2_0_DRAMC_PRE_B4_ACT_ENABLED                    _MK_ENUM_CONST(1)
+
+
+// Register EMC_CFG_DIG_DLL_0  // Configure Digital DLL
+#define EMC_CFG_DIG_DLL_0                       _MK_ADDR_CONST(0x2bc)
+#define EMC_CFG_DIG_DLL_0_SECURE                        0x0
+#define EMC_CFG_DIG_DLL_0_WORD_COUNT                    0x1
+#define EMC_CFG_DIG_DLL_0_RESET_VAL                     _MK_MASK_CONST(0x57)
+#define EMC_CFG_DIG_DLL_0_RESET_MASK                    _MK_MASK_CONST(0x7bff0fff)
+#define EMC_CFG_DIG_DLL_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define EMC_CFG_DIG_DLL_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_CFG_DIG_DLL_0_READ_MASK                     _MK_MASK_CONST(0xfbff0fff)
+#define EMC_CFG_DIG_DLL_0_WRITE_MASK                    _MK_MASK_CONST(0x3bff0fff)
+// Enable digital DLL's.
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_EN_SHIFT                      _MK_SHIFT_CONST(0)
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_EN_FIELD                      (_MK_MASK_CONST(0x1) << EMC_CFG_DIG_DLL_0_CFG_DLL_EN_SHIFT)
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_EN_RANGE                      0:0
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_EN_WOFFSET                    0x0
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_EN_DEFAULT                    _MK_MASK_CONST(0x1)
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_EN_INIT_ENUM                  ENABLED
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_EN_DISABLED                   _MK_ENUM_CONST(0)
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_EN_ENABLED                    _MK_ENUM_CONST(1)
+
+// Enable DL trimmer cells (embedded in pads).
+#define EMC_CFG_DIG_DLL_0_CFG_DLI_TRIMMER_EN_SHIFT                      _MK_SHIFT_CONST(1)
+#define EMC_CFG_DIG_DLL_0_CFG_DLI_TRIMMER_EN_FIELD                      (_MK_MASK_CONST(0x1) << EMC_CFG_DIG_DLL_0_CFG_DLI_TRIMMER_EN_SHIFT)
+#define EMC_CFG_DIG_DLL_0_CFG_DLI_TRIMMER_EN_RANGE                      1:1
+#define EMC_CFG_DIG_DLL_0_CFG_DLI_TRIMMER_EN_WOFFSET                    0x0
+#define EMC_CFG_DIG_DLL_0_CFG_DLI_TRIMMER_EN_DEFAULT                    _MK_MASK_CONST(0x1)
+#define EMC_CFG_DIG_DLL_0_CFG_DLI_TRIMMER_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define EMC_CFG_DIG_DLL_0_CFG_DLI_TRIMMER_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_CFG_DIG_DLL_0_CFG_DLI_TRIMMER_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_CFG_DIG_DLL_0_CFG_DLI_TRIMMER_EN_INIT_ENUM                  ENABLED
+#define EMC_CFG_DIG_DLL_0_CFG_DLI_TRIMMER_EN_DISABLED                   _MK_ENUM_CONST(0)
+#define EMC_CFG_DIG_DLL_0_CFG_DLI_TRIMMER_EN_ENABLED                    _MK_ENUM_CONST(1)
+
+// Override DLL's DLI output w/ OVERRIDE_VAL (still uses mult/offset).
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_OVERRIDE_EN_SHIFT                     _MK_SHIFT_CONST(2)
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_OVERRIDE_EN_FIELD                     (_MK_MASK_CONST(0x1) << EMC_CFG_DIG_DLL_0_CFG_DLL_OVERRIDE_EN_SHIFT)
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_OVERRIDE_EN_RANGE                     2:2
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_OVERRIDE_EN_WOFFSET                   0x0
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_OVERRIDE_EN_DEFAULT                   _MK_MASK_CONST(0x1)
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_OVERRIDE_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_OVERRIDE_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_OVERRIDE_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_OVERRIDE_EN_INIT_ENUM                 ENABLED
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_OVERRIDE_EN_DISABLED                  _MK_ENUM_CONST(0)
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_OVERRIDE_EN_ENABLED                   _MK_ENUM_CONST(1)
+
+// Turn off upper DLL & use lower dll output to drive all trimmers.
+#define EMC_CFG_DIG_DLL_0_CFG_USE_SINGLE_DLL_SHIFT                      _MK_SHIFT_CONST(3)
+#define EMC_CFG_DIG_DLL_0_CFG_USE_SINGLE_DLL_FIELD                      (_MK_MASK_CONST(0x1) << EMC_CFG_DIG_DLL_0_CFG_USE_SINGLE_DLL_SHIFT)
+#define EMC_CFG_DIG_DLL_0_CFG_USE_SINGLE_DLL_RANGE                      3:3
+#define EMC_CFG_DIG_DLL_0_CFG_USE_SINGLE_DLL_WOFFSET                    0x0
+#define EMC_CFG_DIG_DLL_0_CFG_USE_SINGLE_DLL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_CFG_DIG_DLL_0_CFG_USE_SINGLE_DLL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define EMC_CFG_DIG_DLL_0_CFG_USE_SINGLE_DLL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_CFG_DIG_DLL_0_CFG_USE_SINGLE_DLL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_CFG_DIG_DLL_0_CFG_USE_SINGLE_DLL_INIT_ENUM                  DISABLED
+#define EMC_CFG_DIG_DLL_0_CFG_USE_SINGLE_DLL_DISABLED                   _MK_ENUM_CONST(0)
+#define EMC_CFG_DIG_DLL_0_CFG_USE_SINGLE_DLL_ENABLED                    _MK_ENUM_CONST(1)
+
+// Set trimmer values directly for each byte via    FBIO_QUSE_DLY/FBIO_DQS_DLY & FBIO_QUSE_DLY_MSB/FBIO_DQS_DLY_MSB.
+#define EMC_CFG_DIG_DLL_0_CFG_PERBYTE_TRIMMER_OVERRIDE_SHIFT                    _MK_SHIFT_CONST(4)
+#define EMC_CFG_DIG_DLL_0_CFG_PERBYTE_TRIMMER_OVERRIDE_FIELD                    (_MK_MASK_CONST(0x1) << EMC_CFG_DIG_DLL_0_CFG_PERBYTE_TRIMMER_OVERRIDE_SHIFT)
+#define EMC_CFG_DIG_DLL_0_CFG_PERBYTE_TRIMMER_OVERRIDE_RANGE                    4:4
+#define EMC_CFG_DIG_DLL_0_CFG_PERBYTE_TRIMMER_OVERRIDE_WOFFSET                  0x0
+#define EMC_CFG_DIG_DLL_0_CFG_PERBYTE_TRIMMER_OVERRIDE_DEFAULT                  _MK_MASK_CONST(0x1)
+#define EMC_CFG_DIG_DLL_0_CFG_PERBYTE_TRIMMER_OVERRIDE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define EMC_CFG_DIG_DLL_0_CFG_PERBYTE_TRIMMER_OVERRIDE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_CFG_DIG_DLL_0_CFG_PERBYTE_TRIMMER_OVERRIDE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_CFG_DIG_DLL_0_CFG_PERBYTE_TRIMMER_OVERRIDE_INIT_ENUM                        ENABLED
+#define EMC_CFG_DIG_DLL_0_CFG_PERBYTE_TRIMMER_OVERRIDE_DISABLED                 _MK_ENUM_CONST(0)
+#define EMC_CFG_DIG_DLL_0_CFG_PERBYTE_TRIMMER_OVERRIDE_ENABLED                  _MK_ENUM_CONST(1)
+
+// Enable DLL for use w/ lowspeed EMCCLK operation (<200MHz).
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_LOWSPEED_SHIFT                        _MK_SHIFT_CONST(5)
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_LOWSPEED_FIELD                        (_MK_MASK_CONST(0x1) << EMC_CFG_DIG_DLL_0_CFG_DLL_LOWSPEED_SHIFT)
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_LOWSPEED_RANGE                        5:5
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_LOWSPEED_WOFFSET                      0x0
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_LOWSPEED_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_LOWSPEED_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_LOWSPEED_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_LOWSPEED_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Controls how frequently DLL runs, as follows
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_MODE_SHIFT                    _MK_SHIFT_CONST(6)
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_MODE_FIELD                    (_MK_MASK_CONST(0x3) << EMC_CFG_DIG_DLL_0_CFG_DLL_MODE_SHIFT)
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_MODE_RANGE                    7:6
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_MODE_WOFFSET                  0x0
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_MODE_DEFAULT                  _MK_MASK_CONST(0x1)
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_MODE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_MODE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_MODE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_MODE_INIT_ENUM                        RUN_TIL_LOCK
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_MODE_RUN_CONTINUOUS                   _MK_ENUM_CONST(0)    // // DLL will run continuously (only disabled during reads).  This option will consume the most power.
+
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_MODE_RUN_TIL_LOCK                     _MK_ENUM_CONST(1)    // // after DLL_RESET is set, DLL will run until it has locked, then be disabled
+
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_MODE_RUN_PERIODIC                     _MK_ENUM_CONST(2)    // // DLL will be re-enabled w/ each refresh to make sure LOCK is maintained
+
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_MODE_RESERVED                 _MK_ENUM_CONST(3)
+
+// DLL Loop filter control (2^(udset+3)).
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_UDSET_SHIFT                   _MK_SHIFT_CONST(8)
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_UDSET_FIELD                   (_MK_MASK_CONST(0xf) << EMC_CFG_DIG_DLL_0_CFG_DLL_UDSET_SHIFT)
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_UDSET_RANGE                   11:8
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_UDSET_WOFFSET                 0x0
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_UDSET_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_UDSET_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_UDSET_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_UDSET_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Value to use in place of DLI output if CFG_DLL_OVERRIDE_EN is set.
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_OVERRIDE_VAL_SHIFT                    _MK_SHIFT_CONST(16)
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_OVERRIDE_VAL_FIELD                    (_MK_MASK_CONST(0x3ff) << EMC_CFG_DIG_DLL_0_CFG_DLL_OVERRIDE_VAL_SHIFT)
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_OVERRIDE_VAL_RANGE                    25:16
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_OVERRIDE_VAL_WOFFSET                  0x0
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_OVERRIDE_VAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_OVERRIDE_VAL_DEFAULT_MASK                     _MK_MASK_CONST(0x3ff)
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_OVERRIDE_VAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_OVERRIDE_VAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// CYA bit -- disable override of DLL logic when DLL_ALM is set
+//     (otherwise overrides DLI to 0x3FF).
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_ALARM_DISABLE_SHIFT                   _MK_SHIFT_CONST(27)
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_ALARM_DISABLE_FIELD                   (_MK_MASK_CONST(0x1) << EMC_CFG_DIG_DLL_0_CFG_DLL_ALARM_DISABLE_SHIFT)
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_ALARM_DISABLE_RANGE                   27:27
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_ALARM_DISABLE_WOFFSET                 0x0
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_ALARM_DISABLE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_ALARM_DISABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_ALARM_DISABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_ALARM_DISABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// CYA in case DLL has problems locking. DLL will be treated as locked 
+//     after LIMIT emcclk cycles. Counter is reset w/ DLL_RESET (from above) 
+//     or w/ each periodic update (if using RUN_PERIODIC).  Settings are:
+//       00:  LIMIT = 2^12
+//       01:  LIMIT = 2^15
+//       10:  LIMIT = 2^16
+//       11:  LIMIT = 2^16 + 2^17
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_LOCK_LIMIT_SHIFT                      _MK_SHIFT_CONST(28)
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_LOCK_LIMIT_FIELD                      (_MK_MASK_CONST(0x3) << EMC_CFG_DIG_DLL_0_CFG_DLL_LOCK_LIMIT_SHIFT)
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_LOCK_LIMIT_RANGE                      29:28
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_LOCK_LIMIT_WOFFSET                    0x0
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_LOCK_LIMIT_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_LOCK_LIMIT_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_LOCK_LIMIT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_LOCK_LIMIT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Writing 1 to this register will send reset pulse to DLL's on next shadow
+//     update.  Must reset DLL's when changing clock frequency by factor >= 2
+#define EMC_CFG_DIG_DLL_0_DLL_RESET_SHIFT                       _MK_SHIFT_CONST(30)
+#define EMC_CFG_DIG_DLL_0_DLL_RESET_FIELD                       (_MK_MASK_CONST(0x1) << EMC_CFG_DIG_DLL_0_DLL_RESET_SHIFT)
+#define EMC_CFG_DIG_DLL_0_DLL_RESET_RANGE                       30:30
+#define EMC_CFG_DIG_DLL_0_DLL_RESET_WOFFSET                     0x0
+#define EMC_CFG_DIG_DLL_0_DLL_RESET_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_CFG_DIG_DLL_0_DLL_RESET_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define EMC_CFG_DIG_DLL_0_DLL_RESET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_CFG_DIG_DLL_0_DLL_RESET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Writing 1 to this register causes override_val to be used in place of
+// DLL output until DLL_LOCK is obtained.  Takes effect on next shadow update.
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_USE_OVERRIDE_UNTIL_LOCK_SHIFT                 _MK_SHIFT_CONST(31)
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_USE_OVERRIDE_UNTIL_LOCK_FIELD                 (_MK_MASK_CONST(0x1) << EMC_CFG_DIG_DLL_0_CFG_DLL_USE_OVERRIDE_UNTIL_LOCK_SHIFT)
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_USE_OVERRIDE_UNTIL_LOCK_RANGE                 31:31
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_USE_OVERRIDE_UNTIL_LOCK_WOFFSET                       0x0
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_USE_OVERRIDE_UNTIL_LOCK_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_USE_OVERRIDE_UNTIL_LOCK_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_USE_OVERRIDE_UNTIL_LOCK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_USE_OVERRIDE_UNTIL_LOCK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EMC_DLL_XFORM_DQS_0  // Configure Digital DLL
+#define EMC_DLL_XFORM_DQS_0                     _MK_ADDR_CONST(0x2c0)
+#define EMC_DLL_XFORM_DQS_0_SECURE                      0x0
+#define EMC_DLL_XFORM_DQS_0_WORD_COUNT                  0x1
+#define EMC_DLL_XFORM_DQS_0_RESET_VAL                   _MK_MASK_CONST(0x10)
+#define EMC_DLL_XFORM_DQS_0_RESET_MASK                  _MK_MASK_CONST(0x7fff1f)
+#define EMC_DLL_XFORM_DQS_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define EMC_DLL_XFORM_DQS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EMC_DLL_XFORM_DQS_0_READ_MASK                   _MK_MASK_CONST(0x7fff1f)
+#define EMC_DLL_XFORM_DQS_0_WRITE_MASK                  _MK_MASK_CONST(0x7fff1f)
+#define EMC_DLL_XFORM_DQS_0_XFORM_DQS_MULT_SHIFT                        _MK_SHIFT_CONST(0)
+#define EMC_DLL_XFORM_DQS_0_XFORM_DQS_MULT_FIELD                        (_MK_MASK_CONST(0x1f) << EMC_DLL_XFORM_DQS_0_XFORM_DQS_MULT_SHIFT)
+#define EMC_DLL_XFORM_DQS_0_XFORM_DQS_MULT_RANGE                        4:0
+#define EMC_DLL_XFORM_DQS_0_XFORM_DQS_MULT_WOFFSET                      0x0
+#define EMC_DLL_XFORM_DQS_0_XFORM_DQS_MULT_DEFAULT                      _MK_MASK_CONST(0x10)
+#define EMC_DLL_XFORM_DQS_0_XFORM_DQS_MULT_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define EMC_DLL_XFORM_DQS_0_XFORM_DQS_MULT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_DLL_XFORM_DQS_0_XFORM_DQS_MULT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define EMC_DLL_XFORM_DQS_0_XFORM_DQS_OFFS_SHIFT                        _MK_SHIFT_CONST(8)
+#define EMC_DLL_XFORM_DQS_0_XFORM_DQS_OFFS_FIELD                        (_MK_MASK_CONST(0x7fff) << EMC_DLL_XFORM_DQS_0_XFORM_DQS_OFFS_SHIFT)
+#define EMC_DLL_XFORM_DQS_0_XFORM_DQS_OFFS_RANGE                        22:8
+#define EMC_DLL_XFORM_DQS_0_XFORM_DQS_OFFS_WOFFSET                      0x0
+#define EMC_DLL_XFORM_DQS_0_XFORM_DQS_OFFS_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_DLL_XFORM_DQS_0_XFORM_DQS_OFFS_DEFAULT_MASK                 _MK_MASK_CONST(0x7fff)
+#define EMC_DLL_XFORM_DQS_0_XFORM_DQS_OFFS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_DLL_XFORM_DQS_0_XFORM_DQS_OFFS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register EMC_DLL_XFORM_QUSE_0  // Configure Digital DLL
+#define EMC_DLL_XFORM_QUSE_0                    _MK_ADDR_CONST(0x2c4)
+#define EMC_DLL_XFORM_QUSE_0_SECURE                     0x0
+#define EMC_DLL_XFORM_QUSE_0_WORD_COUNT                         0x1
+#define EMC_DLL_XFORM_QUSE_0_RESET_VAL                  _MK_MASK_CONST(0x8)
+#define EMC_DLL_XFORM_QUSE_0_RESET_MASK                         _MK_MASK_CONST(0x7fff1f)
+#define EMC_DLL_XFORM_QUSE_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define EMC_DLL_XFORM_QUSE_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_DLL_XFORM_QUSE_0_READ_MASK                  _MK_MASK_CONST(0x7fff1f)
+#define EMC_DLL_XFORM_QUSE_0_WRITE_MASK                         _MK_MASK_CONST(0x7fff1f)
+#define EMC_DLL_XFORM_QUSE_0_XFORM_QUSE_MULT_SHIFT                      _MK_SHIFT_CONST(0)
+#define EMC_DLL_XFORM_QUSE_0_XFORM_QUSE_MULT_FIELD                      (_MK_MASK_CONST(0x1f) << EMC_DLL_XFORM_QUSE_0_XFORM_QUSE_MULT_SHIFT)
+#define EMC_DLL_XFORM_QUSE_0_XFORM_QUSE_MULT_RANGE                      4:0
+#define EMC_DLL_XFORM_QUSE_0_XFORM_QUSE_MULT_WOFFSET                    0x0
+#define EMC_DLL_XFORM_QUSE_0_XFORM_QUSE_MULT_DEFAULT                    _MK_MASK_CONST(0x8)
+#define EMC_DLL_XFORM_QUSE_0_XFORM_QUSE_MULT_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define EMC_DLL_XFORM_QUSE_0_XFORM_QUSE_MULT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_DLL_XFORM_QUSE_0_XFORM_QUSE_MULT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define EMC_DLL_XFORM_QUSE_0_XFORM_QUSE_OFFS_SHIFT                      _MK_SHIFT_CONST(8)
+#define EMC_DLL_XFORM_QUSE_0_XFORM_QUSE_OFFS_FIELD                      (_MK_MASK_CONST(0x7fff) << EMC_DLL_XFORM_QUSE_0_XFORM_QUSE_OFFS_SHIFT)
+#define EMC_DLL_XFORM_QUSE_0_XFORM_QUSE_OFFS_RANGE                      22:8
+#define EMC_DLL_XFORM_QUSE_0_XFORM_QUSE_OFFS_WOFFSET                    0x0
+#define EMC_DLL_XFORM_QUSE_0_XFORM_QUSE_OFFS_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_DLL_XFORM_QUSE_0_XFORM_QUSE_OFFS_DEFAULT_MASK                       _MK_MASK_CONST(0x7fff)
+#define EMC_DLL_XFORM_QUSE_0_XFORM_QUSE_OFFS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_DLL_XFORM_QUSE_0_XFORM_QUSE_OFFS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register EMC_DIG_DLL_UPPER_STATUS_0  // Digital DLL Status
+#define EMC_DIG_DLL_UPPER_STATUS_0                      _MK_ADDR_CONST(0x2c8)
+#define EMC_DIG_DLL_UPPER_STATUS_0_SECURE                       0x0
+#define EMC_DIG_DLL_UPPER_STATUS_0_WORD_COUNT                   0x1
+#define EMC_DIG_DLL_UPPER_STATUS_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define EMC_DIG_DLL_UPPER_STATUS_0_RESET_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_DIG_DLL_UPPER_STATUS_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define EMC_DIG_DLL_UPPER_STATUS_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_DIG_DLL_UPPER_STATUS_0_READ_MASK                    _MK_MASK_CONST(0xe3ff)
+#define EMC_DIG_DLL_UPPER_STATUS_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_DIG_DLL_UPPER_STATUS_0_DLL_UPPER_OUT_SHIFT                  _MK_SHIFT_CONST(0)
+#define EMC_DIG_DLL_UPPER_STATUS_0_DLL_UPPER_OUT_FIELD                  (_MK_MASK_CONST(0x3ff) << EMC_DIG_DLL_UPPER_STATUS_0_DLL_UPPER_OUT_SHIFT)
+#define EMC_DIG_DLL_UPPER_STATUS_0_DLL_UPPER_OUT_RANGE                  9:0
+#define EMC_DIG_DLL_UPPER_STATUS_0_DLL_UPPER_OUT_WOFFSET                        0x0
+#define EMC_DIG_DLL_UPPER_STATUS_0_DLL_UPPER_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_DIG_DLL_UPPER_STATUS_0_DLL_UPPER_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_DIG_DLL_UPPER_STATUS_0_DLL_UPPER_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_DIG_DLL_UPPER_STATUS_0_DLL_UPPER_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define EMC_DIG_DLL_UPPER_STATUS_0_DLL_UPPER_LOCK_TIMEOUT_SHIFT                 _MK_SHIFT_CONST(13)
+#define EMC_DIG_DLL_UPPER_STATUS_0_DLL_UPPER_LOCK_TIMEOUT_FIELD                 (_MK_MASK_CONST(0x1) << EMC_DIG_DLL_UPPER_STATUS_0_DLL_UPPER_LOCK_TIMEOUT_SHIFT)
+#define EMC_DIG_DLL_UPPER_STATUS_0_DLL_UPPER_LOCK_TIMEOUT_RANGE                 13:13
+#define EMC_DIG_DLL_UPPER_STATUS_0_DLL_UPPER_LOCK_TIMEOUT_WOFFSET                       0x0
+#define EMC_DIG_DLL_UPPER_STATUS_0_DLL_UPPER_LOCK_TIMEOUT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_DIG_DLL_UPPER_STATUS_0_DLL_UPPER_LOCK_TIMEOUT_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_DIG_DLL_UPPER_STATUS_0_DLL_UPPER_LOCK_TIMEOUT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_DIG_DLL_UPPER_STATUS_0_DLL_UPPER_LOCK_TIMEOUT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define EMC_DIG_DLL_UPPER_STATUS_0_DLL_UPPER_ALARM_SHIFT                        _MK_SHIFT_CONST(14)
+#define EMC_DIG_DLL_UPPER_STATUS_0_DLL_UPPER_ALARM_FIELD                        (_MK_MASK_CONST(0x1) << EMC_DIG_DLL_UPPER_STATUS_0_DLL_UPPER_ALARM_SHIFT)
+#define EMC_DIG_DLL_UPPER_STATUS_0_DLL_UPPER_ALARM_RANGE                        14:14
+#define EMC_DIG_DLL_UPPER_STATUS_0_DLL_UPPER_ALARM_WOFFSET                      0x0
+#define EMC_DIG_DLL_UPPER_STATUS_0_DLL_UPPER_ALARM_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_DIG_DLL_UPPER_STATUS_0_DLL_UPPER_ALARM_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define EMC_DIG_DLL_UPPER_STATUS_0_DLL_UPPER_ALARM_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_DIG_DLL_UPPER_STATUS_0_DLL_UPPER_ALARM_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define EMC_DIG_DLL_UPPER_STATUS_0_DLL_UPPER_LOCK_SHIFT                 _MK_SHIFT_CONST(15)
+#define EMC_DIG_DLL_UPPER_STATUS_0_DLL_UPPER_LOCK_FIELD                 (_MK_MASK_CONST(0x1) << EMC_DIG_DLL_UPPER_STATUS_0_DLL_UPPER_LOCK_SHIFT)
+#define EMC_DIG_DLL_UPPER_STATUS_0_DLL_UPPER_LOCK_RANGE                 15:15
+#define EMC_DIG_DLL_UPPER_STATUS_0_DLL_UPPER_LOCK_WOFFSET                       0x0
+#define EMC_DIG_DLL_UPPER_STATUS_0_DLL_UPPER_LOCK_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_DIG_DLL_UPPER_STATUS_0_DLL_UPPER_LOCK_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_DIG_DLL_UPPER_STATUS_0_DLL_UPPER_LOCK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_DIG_DLL_UPPER_STATUS_0_DLL_UPPER_LOCK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EMC_DIG_DLL_LOWER_STATUS_0  // Digital DLL Status
+#define EMC_DIG_DLL_LOWER_STATUS_0                      _MK_ADDR_CONST(0x2cc)
+#define EMC_DIG_DLL_LOWER_STATUS_0_SECURE                       0x0
+#define EMC_DIG_DLL_LOWER_STATUS_0_WORD_COUNT                   0x1
+#define EMC_DIG_DLL_LOWER_STATUS_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define EMC_DIG_DLL_LOWER_STATUS_0_RESET_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_DIG_DLL_LOWER_STATUS_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define EMC_DIG_DLL_LOWER_STATUS_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_DIG_DLL_LOWER_STATUS_0_READ_MASK                    _MK_MASK_CONST(0xe3ff)
+#define EMC_DIG_DLL_LOWER_STATUS_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_DIG_DLL_LOWER_STATUS_0_DLL_LOWER_OUT_SHIFT                  _MK_SHIFT_CONST(0)
+#define EMC_DIG_DLL_LOWER_STATUS_0_DLL_LOWER_OUT_FIELD                  (_MK_MASK_CONST(0x3ff) << EMC_DIG_DLL_LOWER_STATUS_0_DLL_LOWER_OUT_SHIFT)
+#define EMC_DIG_DLL_LOWER_STATUS_0_DLL_LOWER_OUT_RANGE                  9:0
+#define EMC_DIG_DLL_LOWER_STATUS_0_DLL_LOWER_OUT_WOFFSET                        0x0
+#define EMC_DIG_DLL_LOWER_STATUS_0_DLL_LOWER_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_DIG_DLL_LOWER_STATUS_0_DLL_LOWER_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_DIG_DLL_LOWER_STATUS_0_DLL_LOWER_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_DIG_DLL_LOWER_STATUS_0_DLL_LOWER_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define EMC_DIG_DLL_LOWER_STATUS_0_DLL_LOWER_LOCK_TIMEOUT_SHIFT                 _MK_SHIFT_CONST(13)
+#define EMC_DIG_DLL_LOWER_STATUS_0_DLL_LOWER_LOCK_TIMEOUT_FIELD                 (_MK_MASK_CONST(0x1) << EMC_DIG_DLL_LOWER_STATUS_0_DLL_LOWER_LOCK_TIMEOUT_SHIFT)
+#define EMC_DIG_DLL_LOWER_STATUS_0_DLL_LOWER_LOCK_TIMEOUT_RANGE                 13:13
+#define EMC_DIG_DLL_LOWER_STATUS_0_DLL_LOWER_LOCK_TIMEOUT_WOFFSET                       0x0
+#define EMC_DIG_DLL_LOWER_STATUS_0_DLL_LOWER_LOCK_TIMEOUT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_DIG_DLL_LOWER_STATUS_0_DLL_LOWER_LOCK_TIMEOUT_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_DIG_DLL_LOWER_STATUS_0_DLL_LOWER_LOCK_TIMEOUT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_DIG_DLL_LOWER_STATUS_0_DLL_LOWER_LOCK_TIMEOUT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define EMC_DIG_DLL_LOWER_STATUS_0_DLL_LOWER_ALARM_SHIFT                        _MK_SHIFT_CONST(14)
+#define EMC_DIG_DLL_LOWER_STATUS_0_DLL_LOWER_ALARM_FIELD                        (_MK_MASK_CONST(0x1) << EMC_DIG_DLL_LOWER_STATUS_0_DLL_LOWER_ALARM_SHIFT)
+#define EMC_DIG_DLL_LOWER_STATUS_0_DLL_LOWER_ALARM_RANGE                        14:14
+#define EMC_DIG_DLL_LOWER_STATUS_0_DLL_LOWER_ALARM_WOFFSET                      0x0
+#define EMC_DIG_DLL_LOWER_STATUS_0_DLL_LOWER_ALARM_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_DIG_DLL_LOWER_STATUS_0_DLL_LOWER_ALARM_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define EMC_DIG_DLL_LOWER_STATUS_0_DLL_LOWER_ALARM_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_DIG_DLL_LOWER_STATUS_0_DLL_LOWER_ALARM_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define EMC_DIG_DLL_LOWER_STATUS_0_DLL_LOWER_LOCK_SHIFT                 _MK_SHIFT_CONST(15)
+#define EMC_DIG_DLL_LOWER_STATUS_0_DLL_LOWER_LOCK_FIELD                 (_MK_MASK_CONST(0x1) << EMC_DIG_DLL_LOWER_STATUS_0_DLL_LOWER_LOCK_SHIFT)
+#define EMC_DIG_DLL_LOWER_STATUS_0_DLL_LOWER_LOCK_RANGE                 15:15
+#define EMC_DIG_DLL_LOWER_STATUS_0_DLL_LOWER_LOCK_WOFFSET                       0x0
+#define EMC_DIG_DLL_LOWER_STATUS_0_DLL_LOWER_LOCK_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_DIG_DLL_LOWER_STATUS_0_DLL_LOWER_LOCK_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_DIG_DLL_LOWER_STATUS_0_DLL_LOWER_LOCK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_DIG_DLL_LOWER_STATUS_0_DLL_LOWER_LOCK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EMC_CFG_CLKTRIM_0_0  // Configures m4clk trimmers
+#define EMC_CFG_CLKTRIM_0_0                     _MK_ADDR_CONST(0x2d0)
+#define EMC_CFG_CLKTRIM_0_0_SECURE                      0x0
+#define EMC_CFG_CLKTRIM_0_0_WORD_COUNT                  0x1
+#define EMC_CFG_CLKTRIM_0_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define EMC_CFG_CLKTRIM_0_0_RESET_MASK                  _MK_MASK_CONST(0x3fffffff)
+#define EMC_CFG_CLKTRIM_0_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define EMC_CFG_CLKTRIM_0_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EMC_CFG_CLKTRIM_0_0_READ_MASK                   _MK_MASK_CONST(0x3fffffff)
+#define EMC_CFG_CLKTRIM_0_0_WRITE_MASK                  _MK_MASK_CONST(0x3fffffff)
+#define EMC_CFG_CLKTRIM_0_0_CFG_DATA0_CLKTRIM_SHIFT                     _MK_SHIFT_CONST(0)
+#define EMC_CFG_CLKTRIM_0_0_CFG_DATA0_CLKTRIM_FIELD                     (_MK_MASK_CONST(0x3f) << EMC_CFG_CLKTRIM_0_0_CFG_DATA0_CLKTRIM_SHIFT)
+#define EMC_CFG_CLKTRIM_0_0_CFG_DATA0_CLKTRIM_RANGE                     5:0
+#define EMC_CFG_CLKTRIM_0_0_CFG_DATA0_CLKTRIM_WOFFSET                   0x0
+#define EMC_CFG_CLKTRIM_0_0_CFG_DATA0_CLKTRIM_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_CFG_CLKTRIM_0_0_CFG_DATA0_CLKTRIM_DEFAULT_MASK                      _MK_MASK_CONST(0x3f)
+#define EMC_CFG_CLKTRIM_0_0_CFG_DATA0_CLKTRIM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_CFG_CLKTRIM_0_0_CFG_DATA0_CLKTRIM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_CFG_CLKTRIM_0_0_CFG_DATA0_CLKTRIM_MAX                       _MK_ENUM_CONST(47)
+
+#define EMC_CFG_CLKTRIM_0_0_CFG_DATA1_CLKTRIM_SHIFT                     _MK_SHIFT_CONST(6)
+#define EMC_CFG_CLKTRIM_0_0_CFG_DATA1_CLKTRIM_FIELD                     (_MK_MASK_CONST(0x3f) << EMC_CFG_CLKTRIM_0_0_CFG_DATA1_CLKTRIM_SHIFT)
+#define EMC_CFG_CLKTRIM_0_0_CFG_DATA1_CLKTRIM_RANGE                     11:6
+#define EMC_CFG_CLKTRIM_0_0_CFG_DATA1_CLKTRIM_WOFFSET                   0x0
+#define EMC_CFG_CLKTRIM_0_0_CFG_DATA1_CLKTRIM_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_CFG_CLKTRIM_0_0_CFG_DATA1_CLKTRIM_DEFAULT_MASK                      _MK_MASK_CONST(0x3f)
+#define EMC_CFG_CLKTRIM_0_0_CFG_DATA1_CLKTRIM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_CFG_CLKTRIM_0_0_CFG_DATA1_CLKTRIM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_CFG_CLKTRIM_0_0_CFG_DATA1_CLKTRIM_MAX                       _MK_ENUM_CONST(47)
+
+#define EMC_CFG_CLKTRIM_0_0_CFG_DATA2_CLKTRIM_SHIFT                     _MK_SHIFT_CONST(12)
+#define EMC_CFG_CLKTRIM_0_0_CFG_DATA2_CLKTRIM_FIELD                     (_MK_MASK_CONST(0x3f) << EMC_CFG_CLKTRIM_0_0_CFG_DATA2_CLKTRIM_SHIFT)
+#define EMC_CFG_CLKTRIM_0_0_CFG_DATA2_CLKTRIM_RANGE                     17:12
+#define EMC_CFG_CLKTRIM_0_0_CFG_DATA2_CLKTRIM_WOFFSET                   0x0
+#define EMC_CFG_CLKTRIM_0_0_CFG_DATA2_CLKTRIM_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_CFG_CLKTRIM_0_0_CFG_DATA2_CLKTRIM_DEFAULT_MASK                      _MK_MASK_CONST(0x3f)
+#define EMC_CFG_CLKTRIM_0_0_CFG_DATA2_CLKTRIM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_CFG_CLKTRIM_0_0_CFG_DATA2_CLKTRIM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_CFG_CLKTRIM_0_0_CFG_DATA2_CLKTRIM_MAX                       _MK_ENUM_CONST(47)
+
+#define EMC_CFG_CLKTRIM_0_0_CFG_DATA3_CLKTRIM_SHIFT                     _MK_SHIFT_CONST(18)
+#define EMC_CFG_CLKTRIM_0_0_CFG_DATA3_CLKTRIM_FIELD                     (_MK_MASK_CONST(0x3f) << EMC_CFG_CLKTRIM_0_0_CFG_DATA3_CLKTRIM_SHIFT)
+#define EMC_CFG_CLKTRIM_0_0_CFG_DATA3_CLKTRIM_RANGE                     23:18
+#define EMC_CFG_CLKTRIM_0_0_CFG_DATA3_CLKTRIM_WOFFSET                   0x0
+#define EMC_CFG_CLKTRIM_0_0_CFG_DATA3_CLKTRIM_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_CFG_CLKTRIM_0_0_CFG_DATA3_CLKTRIM_DEFAULT_MASK                      _MK_MASK_CONST(0x3f)
+#define EMC_CFG_CLKTRIM_0_0_CFG_DATA3_CLKTRIM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_CFG_CLKTRIM_0_0_CFG_DATA3_CLKTRIM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_CFG_CLKTRIM_0_0_CFG_DATA3_CLKTRIM_MAX                       _MK_ENUM_CONST(47)
+
+#define EMC_CFG_CLKTRIM_0_0_CFG_MCLK_ADDR_CLKTRIM_SHIFT                 _MK_SHIFT_CONST(24)
+#define EMC_CFG_CLKTRIM_0_0_CFG_MCLK_ADDR_CLKTRIM_FIELD                 (_MK_MASK_CONST(0x3f) << EMC_CFG_CLKTRIM_0_0_CFG_MCLK_ADDR_CLKTRIM_SHIFT)
+#define EMC_CFG_CLKTRIM_0_0_CFG_MCLK_ADDR_CLKTRIM_RANGE                 29:24
+#define EMC_CFG_CLKTRIM_0_0_CFG_MCLK_ADDR_CLKTRIM_WOFFSET                       0x0
+#define EMC_CFG_CLKTRIM_0_0_CFG_MCLK_ADDR_CLKTRIM_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_CFG_CLKTRIM_0_0_CFG_MCLK_ADDR_CLKTRIM_DEFAULT_MASK                  _MK_MASK_CONST(0x3f)
+#define EMC_CFG_CLKTRIM_0_0_CFG_MCLK_ADDR_CLKTRIM_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_CFG_CLKTRIM_0_0_CFG_MCLK_ADDR_CLKTRIM_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_CFG_CLKTRIM_0_0_CFG_MCLK_ADDR_CLKTRIM_MAX                   _MK_ENUM_CONST(47)
+
+
+// Register EMC_CFG_CLKTRIM_1_0  // Configures m4clk trimmers
+#define EMC_CFG_CLKTRIM_1_0                     _MK_ADDR_CONST(0x2d4)
+#define EMC_CFG_CLKTRIM_1_0_SECURE                      0x0
+#define EMC_CFG_CLKTRIM_1_0_WORD_COUNT                  0x1
+#define EMC_CFG_CLKTRIM_1_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define EMC_CFG_CLKTRIM_1_0_RESET_MASK                  _MK_MASK_CONST(0x3fffffff)
+#define EMC_CFG_CLKTRIM_1_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define EMC_CFG_CLKTRIM_1_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EMC_CFG_CLKTRIM_1_0_READ_MASK                   _MK_MASK_CONST(0x3fffffff)
+#define EMC_CFG_CLKTRIM_1_0_WRITE_MASK                  _MK_MASK_CONST(0x3fffffff)
+#define EMC_CFG_CLKTRIM_1_0_CFG_DQS0_CLKTRIM_SHIFT                      _MK_SHIFT_CONST(0)
+#define EMC_CFG_CLKTRIM_1_0_CFG_DQS0_CLKTRIM_FIELD                      (_MK_MASK_CONST(0x3f) << EMC_CFG_CLKTRIM_1_0_CFG_DQS0_CLKTRIM_SHIFT)
+#define EMC_CFG_CLKTRIM_1_0_CFG_DQS0_CLKTRIM_RANGE                      5:0
+#define EMC_CFG_CLKTRIM_1_0_CFG_DQS0_CLKTRIM_WOFFSET                    0x0
+#define EMC_CFG_CLKTRIM_1_0_CFG_DQS0_CLKTRIM_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_CFG_CLKTRIM_1_0_CFG_DQS0_CLKTRIM_DEFAULT_MASK                       _MK_MASK_CONST(0x3f)
+#define EMC_CFG_CLKTRIM_1_0_CFG_DQS0_CLKTRIM_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_CFG_CLKTRIM_1_0_CFG_DQS0_CLKTRIM_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_CFG_CLKTRIM_1_0_CFG_DQS0_CLKTRIM_MAX                        _MK_ENUM_CONST(47)
+
+#define EMC_CFG_CLKTRIM_1_0_CFG_DQS1_CLKTRIM_SHIFT                      _MK_SHIFT_CONST(6)
+#define EMC_CFG_CLKTRIM_1_0_CFG_DQS1_CLKTRIM_FIELD                      (_MK_MASK_CONST(0x3f) << EMC_CFG_CLKTRIM_1_0_CFG_DQS1_CLKTRIM_SHIFT)
+#define EMC_CFG_CLKTRIM_1_0_CFG_DQS1_CLKTRIM_RANGE                      11:6
+#define EMC_CFG_CLKTRIM_1_0_CFG_DQS1_CLKTRIM_WOFFSET                    0x0
+#define EMC_CFG_CLKTRIM_1_0_CFG_DQS1_CLKTRIM_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_CFG_CLKTRIM_1_0_CFG_DQS1_CLKTRIM_DEFAULT_MASK                       _MK_MASK_CONST(0x3f)
+#define EMC_CFG_CLKTRIM_1_0_CFG_DQS1_CLKTRIM_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_CFG_CLKTRIM_1_0_CFG_DQS1_CLKTRIM_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_CFG_CLKTRIM_1_0_CFG_DQS1_CLKTRIM_MAX                        _MK_ENUM_CONST(47)
+
+#define EMC_CFG_CLKTRIM_1_0_CFG_DQS2_CLKTRIM_SHIFT                      _MK_SHIFT_CONST(12)
+#define EMC_CFG_CLKTRIM_1_0_CFG_DQS2_CLKTRIM_FIELD                      (_MK_MASK_CONST(0x3f) << EMC_CFG_CLKTRIM_1_0_CFG_DQS2_CLKTRIM_SHIFT)
+#define EMC_CFG_CLKTRIM_1_0_CFG_DQS2_CLKTRIM_RANGE                      17:12
+#define EMC_CFG_CLKTRIM_1_0_CFG_DQS2_CLKTRIM_WOFFSET                    0x0
+#define EMC_CFG_CLKTRIM_1_0_CFG_DQS2_CLKTRIM_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_CFG_CLKTRIM_1_0_CFG_DQS2_CLKTRIM_DEFAULT_MASK                       _MK_MASK_CONST(0x3f)
+#define EMC_CFG_CLKTRIM_1_0_CFG_DQS2_CLKTRIM_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_CFG_CLKTRIM_1_0_CFG_DQS2_CLKTRIM_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_CFG_CLKTRIM_1_0_CFG_DQS2_CLKTRIM_MAX                        _MK_ENUM_CONST(47)
+
+#define EMC_CFG_CLKTRIM_1_0_CFG_DQS3_CLKTRIM_SHIFT                      _MK_SHIFT_CONST(18)
+#define EMC_CFG_CLKTRIM_1_0_CFG_DQS3_CLKTRIM_FIELD                      (_MK_MASK_CONST(0x3f) << EMC_CFG_CLKTRIM_1_0_CFG_DQS3_CLKTRIM_SHIFT)
+#define EMC_CFG_CLKTRIM_1_0_CFG_DQS3_CLKTRIM_RANGE                      23:18
+#define EMC_CFG_CLKTRIM_1_0_CFG_DQS3_CLKTRIM_WOFFSET                    0x0
+#define EMC_CFG_CLKTRIM_1_0_CFG_DQS3_CLKTRIM_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_CFG_CLKTRIM_1_0_CFG_DQS3_CLKTRIM_DEFAULT_MASK                       _MK_MASK_CONST(0x3f)
+#define EMC_CFG_CLKTRIM_1_0_CFG_DQS3_CLKTRIM_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_CFG_CLKTRIM_1_0_CFG_DQS3_CLKTRIM_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_CFG_CLKTRIM_1_0_CFG_DQS3_CLKTRIM_MAX                        _MK_ENUM_CONST(47)
+
+#define EMC_CFG_CLKTRIM_1_0_CFG_MCLK_CLKTRIM_SHIFT                      _MK_SHIFT_CONST(24)
+#define EMC_CFG_CLKTRIM_1_0_CFG_MCLK_CLKTRIM_FIELD                      (_MK_MASK_CONST(0x3f) << EMC_CFG_CLKTRIM_1_0_CFG_MCLK_CLKTRIM_SHIFT)
+#define EMC_CFG_CLKTRIM_1_0_CFG_MCLK_CLKTRIM_RANGE                      29:24
+#define EMC_CFG_CLKTRIM_1_0_CFG_MCLK_CLKTRIM_WOFFSET                    0x0
+#define EMC_CFG_CLKTRIM_1_0_CFG_MCLK_CLKTRIM_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_CFG_CLKTRIM_1_0_CFG_MCLK_CLKTRIM_DEFAULT_MASK                       _MK_MASK_CONST(0x3f)
+#define EMC_CFG_CLKTRIM_1_0_CFG_MCLK_CLKTRIM_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_CFG_CLKTRIM_1_0_CFG_MCLK_CLKTRIM_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_CFG_CLKTRIM_1_0_CFG_MCLK_CLKTRIM_MAX                        _MK_ENUM_CONST(47)
+
+
+// Register EMC_CFG_CLKTRIM_2_0  // Configures m4clk trimmers
+#define EMC_CFG_CLKTRIM_2_0                     _MK_ADDR_CONST(0x2d8)
+#define EMC_CFG_CLKTRIM_2_0_SECURE                      0x0
+#define EMC_CFG_CLKTRIM_2_0_WORD_COUNT                  0x1
+#define EMC_CFG_CLKTRIM_2_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define EMC_CFG_CLKTRIM_2_0_RESET_MASK                  _MK_MASK_CONST(0x3fffffff)
+#define EMC_CFG_CLKTRIM_2_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define EMC_CFG_CLKTRIM_2_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EMC_CFG_CLKTRIM_2_0_READ_MASK                   _MK_MASK_CONST(0x3fffffff)
+#define EMC_CFG_CLKTRIM_2_0_WRITE_MASK                  _MK_MASK_CONST(0x3fffffff)
+#define EMC_CFG_CLKTRIM_2_0_CFG_DQ0_CLKTRIM_SHIFT                       _MK_SHIFT_CONST(0)
+#define EMC_CFG_CLKTRIM_2_0_CFG_DQ0_CLKTRIM_FIELD                       (_MK_MASK_CONST(0x3f) << EMC_CFG_CLKTRIM_2_0_CFG_DQ0_CLKTRIM_SHIFT)
+#define EMC_CFG_CLKTRIM_2_0_CFG_DQ0_CLKTRIM_RANGE                       5:0
+#define EMC_CFG_CLKTRIM_2_0_CFG_DQ0_CLKTRIM_WOFFSET                     0x0
+#define EMC_CFG_CLKTRIM_2_0_CFG_DQ0_CLKTRIM_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_CFG_CLKTRIM_2_0_CFG_DQ0_CLKTRIM_DEFAULT_MASK                        _MK_MASK_CONST(0x3f)
+#define EMC_CFG_CLKTRIM_2_0_CFG_DQ0_CLKTRIM_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_CFG_CLKTRIM_2_0_CFG_DQ0_CLKTRIM_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EMC_CFG_CLKTRIM_2_0_CFG_DQ0_CLKTRIM_MAX                 _MK_ENUM_CONST(47)
+
+#define EMC_CFG_CLKTRIM_2_0_CFG_DQ1_CLKTRIM_SHIFT                       _MK_SHIFT_CONST(6)
+#define EMC_CFG_CLKTRIM_2_0_CFG_DQ1_CLKTRIM_FIELD                       (_MK_MASK_CONST(0x3f) << EMC_CFG_CLKTRIM_2_0_CFG_DQ1_CLKTRIM_SHIFT)
+#define EMC_CFG_CLKTRIM_2_0_CFG_DQ1_CLKTRIM_RANGE                       11:6
+#define EMC_CFG_CLKTRIM_2_0_CFG_DQ1_CLKTRIM_WOFFSET                     0x0
+#define EMC_CFG_CLKTRIM_2_0_CFG_DQ1_CLKTRIM_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_CFG_CLKTRIM_2_0_CFG_DQ1_CLKTRIM_DEFAULT_MASK                        _MK_MASK_CONST(0x3f)
+#define EMC_CFG_CLKTRIM_2_0_CFG_DQ1_CLKTRIM_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_CFG_CLKTRIM_2_0_CFG_DQ1_CLKTRIM_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EMC_CFG_CLKTRIM_2_0_CFG_DQ1_CLKTRIM_MAX                 _MK_ENUM_CONST(47)
+
+#define EMC_CFG_CLKTRIM_2_0_CFG_DQ2_CLKTRIM_SHIFT                       _MK_SHIFT_CONST(12)
+#define EMC_CFG_CLKTRIM_2_0_CFG_DQ2_CLKTRIM_FIELD                       (_MK_MASK_CONST(0x3f) << EMC_CFG_CLKTRIM_2_0_CFG_DQ2_CLKTRIM_SHIFT)
+#define EMC_CFG_CLKTRIM_2_0_CFG_DQ2_CLKTRIM_RANGE                       17:12
+#define EMC_CFG_CLKTRIM_2_0_CFG_DQ2_CLKTRIM_WOFFSET                     0x0
+#define EMC_CFG_CLKTRIM_2_0_CFG_DQ2_CLKTRIM_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_CFG_CLKTRIM_2_0_CFG_DQ2_CLKTRIM_DEFAULT_MASK                        _MK_MASK_CONST(0x3f)
+#define EMC_CFG_CLKTRIM_2_0_CFG_DQ2_CLKTRIM_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_CFG_CLKTRIM_2_0_CFG_DQ2_CLKTRIM_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EMC_CFG_CLKTRIM_2_0_CFG_DQ2_CLKTRIM_MAX                 _MK_ENUM_CONST(47)
+
+#define EMC_CFG_CLKTRIM_2_0_CFG_DQ3_CLKTRIM_SHIFT                       _MK_SHIFT_CONST(18)
+#define EMC_CFG_CLKTRIM_2_0_CFG_DQ3_CLKTRIM_FIELD                       (_MK_MASK_CONST(0x3f) << EMC_CFG_CLKTRIM_2_0_CFG_DQ3_CLKTRIM_SHIFT)
+#define EMC_CFG_CLKTRIM_2_0_CFG_DQ3_CLKTRIM_RANGE                       23:18
+#define EMC_CFG_CLKTRIM_2_0_CFG_DQ3_CLKTRIM_WOFFSET                     0x0
+#define EMC_CFG_CLKTRIM_2_0_CFG_DQ3_CLKTRIM_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_CFG_CLKTRIM_2_0_CFG_DQ3_CLKTRIM_DEFAULT_MASK                        _MK_MASK_CONST(0x3f)
+#define EMC_CFG_CLKTRIM_2_0_CFG_DQ3_CLKTRIM_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_CFG_CLKTRIM_2_0_CFG_DQ3_CLKTRIM_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EMC_CFG_CLKTRIM_2_0_CFG_DQ3_CLKTRIM_MAX                 _MK_ENUM_CONST(47)
+
+#define EMC_CFG_CLKTRIM_2_0_CFG_CMD_CLKTRIM_SHIFT                       _MK_SHIFT_CONST(24)
+#define EMC_CFG_CLKTRIM_2_0_CFG_CMD_CLKTRIM_FIELD                       (_MK_MASK_CONST(0x3f) << EMC_CFG_CLKTRIM_2_0_CFG_CMD_CLKTRIM_SHIFT)
+#define EMC_CFG_CLKTRIM_2_0_CFG_CMD_CLKTRIM_RANGE                       29:24
+#define EMC_CFG_CLKTRIM_2_0_CFG_CMD_CLKTRIM_WOFFSET                     0x0
+#define EMC_CFG_CLKTRIM_2_0_CFG_CMD_CLKTRIM_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_CFG_CLKTRIM_2_0_CFG_CMD_CLKTRIM_DEFAULT_MASK                        _MK_MASK_CONST(0x3f)
+#define EMC_CFG_CLKTRIM_2_0_CFG_CMD_CLKTRIM_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_CFG_CLKTRIM_2_0_CFG_CMD_CLKTRIM_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EMC_CFG_CLKTRIM_2_0_CFG_CMD_CLKTRIM_MAX                 _MK_ENUM_CONST(47)
+
+
+// Register EMC_CTT_TERM_CTRL_0  // Configure CTT termination output drive strength
+#define EMC_CTT_TERM_CTRL_0                     _MK_ADDR_CONST(0x2dc)
+#define EMC_CTT_TERM_CTRL_0_SECURE                      0x0
+#define EMC_CTT_TERM_CTRL_0_WORD_COUNT                  0x1
+#define EMC_CTT_TERM_CTRL_0_RESET_VAL                   _MK_MASK_CONST(0x802)
+#define EMC_CTT_TERM_CTRL_0_RESET_MASK                  _MK_MASK_CONST(0x80001f07)
+#define EMC_CTT_TERM_CTRL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define EMC_CTT_TERM_CTRL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EMC_CTT_TERM_CTRL_0_READ_MASK                   _MK_MASK_CONST(0x9f0f9f07)
+#define EMC_CTT_TERM_CTRL_0_WRITE_MASK                  _MK_MASK_CONST(0x80001f07)
+// 
+#define EMC_CTT_TERM_CTRL_0_TERM_SLOPE_SHIFT                    _MK_SHIFT_CONST(0)
+#define EMC_CTT_TERM_CTRL_0_TERM_SLOPE_FIELD                    (_MK_MASK_CONST(0x7) << EMC_CTT_TERM_CTRL_0_TERM_SLOPE_SHIFT)
+#define EMC_CTT_TERM_CTRL_0_TERM_SLOPE_RANGE                    2:0
+#define EMC_CTT_TERM_CTRL_0_TERM_SLOPE_WOFFSET                  0x0
+#define EMC_CTT_TERM_CTRL_0_TERM_SLOPE_DEFAULT                  _MK_MASK_CONST(0x2)
+#define EMC_CTT_TERM_CTRL_0_TERM_SLOPE_DEFAULT_MASK                     _MK_MASK_CONST(0x7)
+#define EMC_CTT_TERM_CTRL_0_TERM_SLOPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_CTT_TERM_CTRL_0_TERM_SLOPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+//
+#define EMC_CTT_TERM_CTRL_0_TERM_OFFSET_SHIFT                   _MK_SHIFT_CONST(8)
+#define EMC_CTT_TERM_CTRL_0_TERM_OFFSET_FIELD                   (_MK_MASK_CONST(0x1f) << EMC_CTT_TERM_CTRL_0_TERM_OFFSET_SHIFT)
+#define EMC_CTT_TERM_CTRL_0_TERM_OFFSET_RANGE                   12:8
+#define EMC_CTT_TERM_CTRL_0_TERM_OFFSET_WOFFSET                 0x0
+#define EMC_CTT_TERM_CTRL_0_TERM_OFFSET_DEFAULT                 _MK_MASK_CONST(0x8)
+#define EMC_CTT_TERM_CTRL_0_TERM_OFFSET_DEFAULT_MASK                    _MK_MASK_CONST(0x1f)
+#define EMC_CTT_TERM_CTRL_0_TERM_OFFSET_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_CTT_TERM_CTRL_0_TERM_OFFSET_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define EMC_CTT_TERM_CTRL_0_TERM_DRVDN_SHIFT                    _MK_SHIFT_CONST(15)
+#define EMC_CTT_TERM_CTRL_0_TERM_DRVDN_FIELD                    (_MK_MASK_CONST(0x1f) << EMC_CTT_TERM_CTRL_0_TERM_DRVDN_SHIFT)
+#define EMC_CTT_TERM_CTRL_0_TERM_DRVDN_RANGE                    19:15
+#define EMC_CTT_TERM_CTRL_0_TERM_DRVDN_WOFFSET                  0x0
+#define EMC_CTT_TERM_CTRL_0_TERM_DRVDN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_CTT_TERM_CTRL_0_TERM_DRVDN_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EMC_CTT_TERM_CTRL_0_TERM_DRVDN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_CTT_TERM_CTRL_0_TERM_DRVDN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define EMC_CTT_TERM_CTRL_0_TERM_DRVUP_SHIFT                    _MK_SHIFT_CONST(24)
+#define EMC_CTT_TERM_CTRL_0_TERM_DRVUP_FIELD                    (_MK_MASK_CONST(0x1f) << EMC_CTT_TERM_CTRL_0_TERM_DRVUP_SHIFT)
+#define EMC_CTT_TERM_CTRL_0_TERM_DRVUP_RANGE                    28:24
+#define EMC_CTT_TERM_CTRL_0_TERM_DRVUP_WOFFSET                  0x0
+#define EMC_CTT_TERM_CTRL_0_TERM_DRVUP_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_CTT_TERM_CTRL_0_TERM_DRVUP_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EMC_CTT_TERM_CTRL_0_TERM_DRVUP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_CTT_TERM_CTRL_0_TERM_DRVUP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// 
+#define EMC_CTT_TERM_CTRL_0_TERM_OVERRIDE_SHIFT                 _MK_SHIFT_CONST(31)
+#define EMC_CTT_TERM_CTRL_0_TERM_OVERRIDE_FIELD                 (_MK_MASK_CONST(0x1) << EMC_CTT_TERM_CTRL_0_TERM_OVERRIDE_SHIFT)
+#define EMC_CTT_TERM_CTRL_0_TERM_OVERRIDE_RANGE                 31:31
+#define EMC_CTT_TERM_CTRL_0_TERM_OVERRIDE_WOFFSET                       0x0
+#define EMC_CTT_TERM_CTRL_0_TERM_OVERRIDE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_CTT_TERM_CTRL_0_TERM_OVERRIDE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define EMC_CTT_TERM_CTRL_0_TERM_OVERRIDE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_CTT_TERM_CTRL_0_TERM_OVERRIDE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_CTT_TERM_CTRL_0_TERM_OVERRIDE_INIT_ENUM                     DISABLED
+#define EMC_CTT_TERM_CTRL_0_TERM_OVERRIDE_DISABLED                      _MK_ENUM_CONST(0)
+#define EMC_CTT_TERM_CTRL_0_TERM_OVERRIDE_ENABLED                       _MK_ENUM_CONST(1)
+
+
+// Register EMC_ZCAL_REF_CNT_0  // Configure ZQ Calibration
+#define EMC_ZCAL_REF_CNT_0                      _MK_ADDR_CONST(0x2e0)
+#define EMC_ZCAL_REF_CNT_0_SECURE                       0x0
+#define EMC_ZCAL_REF_CNT_0_WORD_COUNT                   0x1
+#define EMC_ZCAL_REF_CNT_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define EMC_ZCAL_REF_CNT_0_RESET_MASK                   _MK_MASK_CONST(0xffffff)
+#define EMC_ZCAL_REF_CNT_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define EMC_ZCAL_REF_CNT_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_ZCAL_REF_CNT_0_READ_MASK                    _MK_MASK_CONST(0xffffff)
+#define EMC_ZCAL_REF_CNT_0_WRITE_MASK                   _MK_MASK_CONST(0xffffff)
+// Number of refreshes to wait between issuance of ZCAL_MRW_CMD.  If 0, ZCAL is disabled and internal counter will be reset.
+#define EMC_ZCAL_REF_CNT_0_ZCAL_REF_INTERVAL_SHIFT                      _MK_SHIFT_CONST(0)
+#define EMC_ZCAL_REF_CNT_0_ZCAL_REF_INTERVAL_FIELD                      (_MK_MASK_CONST(0xffffff) << EMC_ZCAL_REF_CNT_0_ZCAL_REF_INTERVAL_SHIFT)
+#define EMC_ZCAL_REF_CNT_0_ZCAL_REF_INTERVAL_RANGE                      23:0
+#define EMC_ZCAL_REF_CNT_0_ZCAL_REF_INTERVAL_WOFFSET                    0x0
+#define EMC_ZCAL_REF_CNT_0_ZCAL_REF_INTERVAL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_ZCAL_REF_CNT_0_ZCAL_REF_INTERVAL_DEFAULT_MASK                       _MK_MASK_CONST(0xffffff)
+#define EMC_ZCAL_REF_CNT_0_ZCAL_REF_INTERVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_ZCAL_REF_CNT_0_ZCAL_REF_INTERVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register EMC_ZCAL_WAIT_CNT_0  // Configure ZQ Calibration
+#define EMC_ZCAL_WAIT_CNT_0                     _MK_ADDR_CONST(0x2e4)
+#define EMC_ZCAL_WAIT_CNT_0_SECURE                      0x0
+#define EMC_ZCAL_WAIT_CNT_0_WORD_COUNT                  0x1
+#define EMC_ZCAL_WAIT_CNT_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define EMC_ZCAL_WAIT_CNT_0_RESET_MASK                  _MK_MASK_CONST(0xff)
+#define EMC_ZCAL_WAIT_CNT_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define EMC_ZCAL_WAIT_CNT_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EMC_ZCAL_WAIT_CNT_0_READ_MASK                   _MK_MASK_CONST(0xff)
+#define EMC_ZCAL_WAIT_CNT_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
+// Number of emc clocks to wait before issuing any commands after sending ZCAL_MRW_CMD.
+#define EMC_ZCAL_WAIT_CNT_0_ZCAL_WAIT_CNT_SHIFT                 _MK_SHIFT_CONST(0)
+#define EMC_ZCAL_WAIT_CNT_0_ZCAL_WAIT_CNT_FIELD                 (_MK_MASK_CONST(0xff) << EMC_ZCAL_WAIT_CNT_0_ZCAL_WAIT_CNT_SHIFT)
+#define EMC_ZCAL_WAIT_CNT_0_ZCAL_WAIT_CNT_RANGE                 7:0
+#define EMC_ZCAL_WAIT_CNT_0_ZCAL_WAIT_CNT_WOFFSET                       0x0
+#define EMC_ZCAL_WAIT_CNT_0_ZCAL_WAIT_CNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_ZCAL_WAIT_CNT_0_ZCAL_WAIT_CNT_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define EMC_ZCAL_WAIT_CNT_0_ZCAL_WAIT_CNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_ZCAL_WAIT_CNT_0_ZCAL_WAIT_CNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EMC_ZCAL_MRW_CMD_0  // Configure ZQ Calibration
+#define EMC_ZCAL_MRW_CMD_0                      _MK_ADDR_CONST(0x2e8)
+#define EMC_ZCAL_MRW_CMD_0_SECURE                       0x0
+#define EMC_ZCAL_MRW_CMD_0_WORD_COUNT                   0x1
+#define EMC_ZCAL_MRW_CMD_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define EMC_ZCAL_MRW_CMD_0_RESET_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_ZCAL_MRW_CMD_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define EMC_ZCAL_MRW_CMD_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_ZCAL_MRW_CMD_0_READ_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_ZCAL_MRW_CMD_0_WRITE_MASK                   _MK_MASK_CONST(0xc0ff00ff)
+// MRW OP field to be sent after ZCAL_REF_CNT
+#define EMC_ZCAL_MRW_CMD_0_ZQ_MRW_OP_SHIFT                      _MK_SHIFT_CONST(0)
+#define EMC_ZCAL_MRW_CMD_0_ZQ_MRW_OP_FIELD                      (_MK_MASK_CONST(0xff) << EMC_ZCAL_MRW_CMD_0_ZQ_MRW_OP_SHIFT)
+#define EMC_ZCAL_MRW_CMD_0_ZQ_MRW_OP_RANGE                      7:0
+#define EMC_ZCAL_MRW_CMD_0_ZQ_MRW_OP_WOFFSET                    0x0
+#define EMC_ZCAL_MRW_CMD_0_ZQ_MRW_OP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_ZCAL_MRW_CMD_0_ZQ_MRW_OP_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_ZCAL_MRW_CMD_0_ZQ_MRW_OP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_ZCAL_MRW_CMD_0_ZQ_MRW_OP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// MRW MA field to be sent after ZCAL_REF_CNT
+#define EMC_ZCAL_MRW_CMD_0_ZQ_MRW_MA_SHIFT                      _MK_SHIFT_CONST(16)
+#define EMC_ZCAL_MRW_CMD_0_ZQ_MRW_MA_FIELD                      (_MK_MASK_CONST(0xff) << EMC_ZCAL_MRW_CMD_0_ZQ_MRW_MA_SHIFT)
+#define EMC_ZCAL_MRW_CMD_0_ZQ_MRW_MA_RANGE                      23:16
+#define EMC_ZCAL_MRW_CMD_0_ZQ_MRW_MA_WOFFSET                    0x0
+#define EMC_ZCAL_MRW_CMD_0_ZQ_MRW_MA_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_ZCAL_MRW_CMD_0_ZQ_MRW_MA_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_ZCAL_MRW_CMD_0_ZQ_MRW_MA_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_ZCAL_MRW_CMD_0_ZQ_MRW_MA_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// active-low chip-select, 0x0 applies command to both devices (will happen 1 at a time), 0x2 to for only dev0, 0x1 for dev1.
+#define EMC_ZCAL_MRW_CMD_0_ZQ_MRW_DEV_SELECTN_SHIFT                     _MK_SHIFT_CONST(30)
+#define EMC_ZCAL_MRW_CMD_0_ZQ_MRW_DEV_SELECTN_FIELD                     (_MK_MASK_CONST(0x3) << EMC_ZCAL_MRW_CMD_0_ZQ_MRW_DEV_SELECTN_SHIFT)
+#define EMC_ZCAL_MRW_CMD_0_ZQ_MRW_DEV_SELECTN_RANGE                     31:30
+#define EMC_ZCAL_MRW_CMD_0_ZQ_MRW_DEV_SELECTN_WOFFSET                   0x0
+#define EMC_ZCAL_MRW_CMD_0_ZQ_MRW_DEV_SELECTN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_ZCAL_MRW_CMD_0_ZQ_MRW_DEV_SELECTN_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_ZCAL_MRW_CMD_0_ZQ_MRW_DEV_SELECTN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_ZCAL_MRW_CMD_0_ZQ_MRW_DEV_SELECTN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+//
+// REGISTER LIST
+//
+#define LIST_AREMC_REGS(_op_) \
+_op_(EMC_INTSTATUS_0) \
+_op_(EMC_INTMASK_0) \
+_op_(EMC_DBG_0) \
+_op_(EMC_CFG_0) \
+_op_(EMC_ADR_CFG_0) \
+_op_(EMC_ADR_CFG_1_0) \
+_op_(EMC_REFCTRL_0) \
+_op_(EMC_PIN_0) \
+_op_(EMC_TIMING_CONTROL_0) \
+_op_(EMC_RC_0) \
+_op_(EMC_RFC_0) \
+_op_(EMC_RAS_0) \
+_op_(EMC_RP_0) \
+_op_(EMC_R2W_0) \
+_op_(EMC_W2R_0) \
+_op_(EMC_R2P_0) \
+_op_(EMC_W2P_0) \
+_op_(EMC_RD_RCD_0) \
+_op_(EMC_WR_RCD_0) \
+_op_(EMC_RRD_0) \
+_op_(EMC_REXT_0) \
+_op_(EMC_WDV_0) \
+_op_(EMC_QUSE_0) \
+_op_(EMC_QRST_0) \
+_op_(EMC_QSAFE_0) \
+_op_(EMC_RDV_0) \
+_op_(EMC_REFRESH_0) \
+_op_(EMC_BURST_REFRESH_NUM_0) \
+_op_(EMC_PDEX2WR_0) \
+_op_(EMC_PDEX2RD_0) \
+_op_(EMC_PCHG2PDEN_0) \
+_op_(EMC_ACT2PDEN_0) \
+_op_(EMC_AR2PDEN_0) \
+_op_(EMC_RW2PDEN_0) \
+_op_(EMC_TXSR_0) \
+_op_(EMC_TCKE_0) \
+_op_(EMC_TFAW_0) \
+_op_(EMC_TRPAB_0) \
+_op_(EMC_TCLKSTABLE_0) \
+_op_(EMC_TCLKSTOP_0) \
+_op_(EMC_TREFBW_0) \
+_op_(EMC_QUSE_EXTRA_0) \
+_op_(EMC_ODT_WRITE_0) \
+_op_(EMC_ODT_READ_0) \
+_op_(EMC_MRS_0) \
+_op_(EMC_EMRS_0) \
+_op_(EMC_REF_0) \
+_op_(EMC_PRE_0) \
+_op_(EMC_NOP_0) \
+_op_(EMC_SELF_REF_0) \
+_op_(EMC_DPD_0) \
+_op_(EMC_MRW_0) \
+_op_(EMC_MRR_0) \
+_op_(EMC_CMDQ_0) \
+_op_(EMC_FBIO_CFG1_0) \
+_op_(EMC_FBIO_DQSIB_DLY_0) \
+_op_(EMC_FBIO_DQSIB_DLY_MSB_0) \
+_op_(EMC_FBIO_SPARE_0) \
+_op_(EMC_FBIO_CFG5_0) \
+_op_(EMC_FBIO_WRPTR_EQ_2_0) \
+_op_(EMC_FBIO_QUSE_DLY_0) \
+_op_(EMC_FBIO_QUSE_DLY_MSB_0) \
+_op_(EMC_FBIO_CFG6_0) \
+_op_(EMC_DQS_TRIMMER_RD0_0) \
+_op_(EMC_DQS_TRIMMER_RD1_0) \
+_op_(EMC_DQS_TRIMMER_RD2_0) \
+_op_(EMC_DQS_TRIMMER_RD3_0) \
+_op_(EMC_CLKEN_OVERRIDE_0) \
+_op_(EMC_LL_ARB_CONFIG_0) \
+_op_(EMC_T_MIN_CRITICAL_HP_0) \
+_op_(EMC_T_MIN_CRITICAL_TIMEOUT_0) \
+_op_(EMC_T_MIN_LOAD_0) \
+_op_(EMC_T_MAX_CRITICAL_HP_0) \
+_op_(EMC_T_MAX_CRITICAL_TIMEOUT_0) \
+_op_(EMC_T_MAX_LOAD_0) \
+_op_(EMC_STAT_CONTROL_0) \
+_op_(EMC_STAT_STATUS_0) \
+_op_(EMC_STAT_LLMC_ADDR_LOW_0) \
+_op_(EMC_STAT_LLMC_ADDR_HIGH_0) \
+_op_(EMC_STAT_LLMC_CLOCK_LIMIT_0) \
+_op_(EMC_STAT_LLMC_CLOCKS_0) \
+_op_(EMC_STAT_LLMC_CONTROL_0_0) \
+_op_(EMC_STAT_LLMC_HIST_LIMIT_0_0) \
+_op_(EMC_STAT_LLMC_COUNT_0_0) \
+_op_(EMC_STAT_LLMC_HIST_0_0) \
+_op_(EMC_STAT_PWR_CLOCK_LIMIT_0) \
+_op_(EMC_STAT_PWR_CLOCKS_0) \
+_op_(EMC_STAT_PWR_COUNT_0) \
+_op_(EMC_STAT_DRAM_CLOCK_LIMIT_LO_0) \
+_op_(EMC_STAT_DRAM_CLOCK_LIMIT_HI_0) \
+_op_(EMC_STAT_DRAM_CLOCKS_LO_0) \
+_op_(EMC_STAT_DRAM_CLOCKS_HI_0) \
+_op_(EMC_STAT_DRAM_DEV0_ACTIVATE_CNT_LO_0) \
+_op_(EMC_STAT_DRAM_DEV0_ACTIVATE_CNT_HI_0) \
+_op_(EMC_STAT_DRAM_DEV0_READ_CNT_LO_0) \
+_op_(EMC_STAT_DRAM_DEV0_READ_CNT_HI_0) \
+_op_(EMC_STAT_DRAM_DEV0_WRITE_CNT_LO_0) \
+_op_(EMC_STAT_DRAM_DEV0_WRITE_CNT_HI_0) \
+_op_(EMC_STAT_DRAM_DEV0_REF_CNT_LO_0) \
+_op_(EMC_STAT_DRAM_DEV0_REF_CNT_HI_0) \
+_op_(EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ1_LO_0) \
+_op_(EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ1_HI_0) \
+_op_(EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ0_LO_0) \
+_op_(EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ0_HI_0) \
+_op_(EMC_STAT_DRAM_DEV0_CKE_EQ1_CLKS_LO_0) \
+_op_(EMC_STAT_DRAM_DEV0_CKE_EQ1_CLKS_HI_0) \
+_op_(EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ1_LO_0) \
+_op_(EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ1_HI_0) \
+_op_(EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ0_LO_0) \
+_op_(EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ0_HI_0) \
+_op_(EMC_STAT_DRAM_DEV1_ACTIVATE_CNT_LO_0) \
+_op_(EMC_STAT_DRAM_DEV1_ACTIVATE_CNT_HI_0) \
+_op_(EMC_STAT_DRAM_DEV1_READ_CNT_LO_0) \
+_op_(EMC_STAT_DRAM_DEV1_READ_CNT_HI_0) \
+_op_(EMC_STAT_DRAM_DEV1_WRITE_CNT_LO_0) \
+_op_(EMC_STAT_DRAM_DEV1_WRITE_CNT_HI_0) \
+_op_(EMC_STAT_DRAM_DEV1_REF_CNT_LO_0) \
+_op_(EMC_STAT_DRAM_DEV1_REF_CNT_HI_0) \
+_op_(EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ1_LO_0) \
+_op_(EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ1_HI_0) \
+_op_(EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ0_LO_0) \
+_op_(EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ0_HI_0) \
+_op_(EMC_STAT_DRAM_DEV1_CKE_EQ1_CLKS_LO_0) \
+_op_(EMC_STAT_DRAM_DEV1_CKE_EQ1_CLKS_HI_0) \
+_op_(EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ1_LO_0) \
+_op_(EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ1_HI_0) \
+_op_(EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ0_LO_0) \
+_op_(EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ0_HI_0) \
+_op_(EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ1_LO_0) \
+_op_(EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ1_HI_0) \
+_op_(EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ0_LO_0) \
+_op_(EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ0_HI_0) \
+_op_(EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ1_LO_0) \
+_op_(EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ1_HI_0) \
+_op_(EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ0_LO_0) \
+_op_(EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ0_HI_0) \
+_op_(EMC_AUTO_CAL_CONFIG_0) \
+_op_(EMC_AUTO_CAL_INTERVAL_0) \
+_op_(EMC_AUTO_CAL_STATUS_0) \
+_op_(EMC_REQ_CTRL_0) \
+_op_(EMC_EMC_STATUS_0) \
+_op_(EMC_CFG_2_0) \
+_op_(EMC_CFG_DIG_DLL_0) \
+_op_(EMC_DLL_XFORM_DQS_0) \
+_op_(EMC_DLL_XFORM_QUSE_0) \
+_op_(EMC_DIG_DLL_UPPER_STATUS_0) \
+_op_(EMC_DIG_DLL_LOWER_STATUS_0) \
+_op_(EMC_CFG_CLKTRIM_0_0) \
+_op_(EMC_CFG_CLKTRIM_1_0) \
+_op_(EMC_CFG_CLKTRIM_2_0) \
+_op_(EMC_CTT_TERM_CTRL_0) \
+_op_(EMC_ZCAL_REF_CNT_0) \
+_op_(EMC_ZCAL_WAIT_CNT_0) \
+_op_(EMC_ZCAL_MRW_CMD_0)
+
+
+//
+// ADDRESS SPACES
+//
+
+#define BASE_ADDRESS_EMC        0x00000000
+
+//
+// AREMC REGISTER BANKS
+//
+
+#define EMC0_FIRST_REG 0x0000 // EMC_INTSTATUS_0
+#define EMC0_LAST_REG 0x0014 // EMC_ADR_CFG_1_0
+#define EMC1_FIRST_REG 0x0020 // EMC_REFCTRL_0
+#define EMC1_LAST_REG 0x00b4 // EMC_ODT_READ_0
+#define EMC2_FIRST_REG 0x00cc // EMC_MRS_0
+#define EMC2_LAST_REG 0x0114 // EMC_FBIO_CFG6_0
+#define EMC3_FIRST_REG 0x0120 // EMC_DQS_TRIMMER_RD0_0
+#define EMC3_LAST_REG 0x012c // EMC_DQS_TRIMMER_RD3_0
+#define EMC4_FIRST_REG 0x0140 // EMC_CLKEN_OVERRIDE_0
+#define EMC4_LAST_REG 0x0178 // EMC_STAT_LLMC_CONTROL_0_0
+#define EMC5_FIRST_REG 0x0180 // EMC_STAT_LLMC_HIST_LIMIT_0_0
+#define EMC5_LAST_REG 0x0180 // EMC_STAT_LLMC_HIST_LIMIT_0_0
+#define EMC6_FIRST_REG 0x0188 // EMC_STAT_LLMC_COUNT_0_0
+#define EMC6_LAST_REG 0x0188 // EMC_STAT_LLMC_COUNT_0_0
+#define EMC7_FIRST_REG 0x0190 // EMC_STAT_LLMC_HIST_0_0
+#define EMC7_LAST_REG 0x0190 // EMC_STAT_LLMC_HIST_0_0
+#define EMC8_FIRST_REG 0x0198 // EMC_STAT_PWR_CLOCK_LIMIT_0
+#define EMC8_LAST_REG 0x0260 // EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ0_HI_0
+#define EMC9_FIRST_REG 0x02a4 // EMC_AUTO_CAL_CONFIG_0
+#define EMC9_LAST_REG 0x02e8 // EMC_ZCAL_MRW_CMD_0
+
+#ifndef _MK_SHIFT_CONST
+  #define _MK_SHIFT_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_MASK_CONST
+  #define _MK_MASK_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_ENUM_CONST
+  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
+#endif
+#ifndef _MK_ADDR_CONST
+  #define _MK_ADDR_CONST(_constant_) _constant_
+#endif
+
+#endif // ifndef ___AREMC_H_INC_
diff --git a/arch/arm/mach-tegra/include/ap20/arfuse.h b/arch/arm/mach-tegra/include/ap20/arfuse.h
new file mode 100644
index 000000000000..51f4a4a0f080
--- /dev/null
+++ b/arch/arm/mach-tegra/include/ap20/arfuse.h
@@ -0,0 +1,2899 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+//
+// DO NOT EDIT - generated by simspec!
+//
+
+#ifndef ___ARFUSE_H_INC_
+#define ___ARFUSE_H_INC_
+
+// Register FUSE_FUSECTRL_0  
+#define FUSE_FUSECTRL_0                 _MK_ADDR_CONST(0x0)
+#define FUSE_FUSECTRL_0_SECURE                  0x0
+#define FUSE_FUSECTRL_0_WORD_COUNT                      0x1
+#define FUSE_FUSECTRL_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSECTRL_0_RESET_MASK                      _MK_MASK_CONST(0x3)
+#define FUSE_FUSECTRL_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSECTRL_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define FUSE_FUSECTRL_0_READ_MASK                       _MK_MASK_CONST(0xc00f0000)
+#define FUSE_FUSECTRL_0_WRITE_MASK                      _MK_MASK_CONST(0x3)
+#define FUSE_FUSECTRL_0_FUSECTRL_CMD_SHIFT                      _MK_SHIFT_CONST(0)
+#define FUSE_FUSECTRL_0_FUSECTRL_CMD_FIELD                      (_MK_MASK_CONST(0x3) << FUSE_FUSECTRL_0_FUSECTRL_CMD_SHIFT)
+#define FUSE_FUSECTRL_0_FUSECTRL_CMD_RANGE                      1:0
+#define FUSE_FUSECTRL_0_FUSECTRL_CMD_WOFFSET                    0x0
+#define FUSE_FUSECTRL_0_FUSECTRL_CMD_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSECTRL_0_FUSECTRL_CMD_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define FUSE_FUSECTRL_0_FUSECTRL_CMD_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSECTRL_0_FUSECTRL_CMD_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSECTRL_0_FUSECTRL_CMD_INIT_ENUM                  IDLE
+#define FUSE_FUSECTRL_0_FUSECTRL_CMD_IDLE                       _MK_ENUM_CONST(0)
+#define FUSE_FUSECTRL_0_FUSECTRL_CMD_READ                       _MK_ENUM_CONST(1)
+#define FUSE_FUSECTRL_0_FUSECTRL_CMD_WRITE                      _MK_ENUM_CONST(2)
+#define FUSE_FUSECTRL_0_FUSECTRL_CMD_SENSE_CTRL                 _MK_ENUM_CONST(3)
+
+#define FUSE_FUSECTRL_0_FUSECTRL_STATE_SHIFT                    _MK_SHIFT_CONST(16)
+#define FUSE_FUSECTRL_0_FUSECTRL_STATE_FIELD                    (_MK_MASK_CONST(0xf) << FUSE_FUSECTRL_0_FUSECTRL_STATE_SHIFT)
+#define FUSE_FUSECTRL_0_FUSECTRL_STATE_RANGE                    19:16
+#define FUSE_FUSECTRL_0_FUSECTRL_STATE_WOFFSET                  0x0
+#define FUSE_FUSECTRL_0_FUSECTRL_STATE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSECTRL_0_FUSECTRL_STATE_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSECTRL_0_FUSECTRL_STATE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSECTRL_0_FUSECTRL_STATE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSECTRL_0_FUSECTRL_STATE_STATE_RESET                      _MK_ENUM_CONST(0)
+#define FUSE_FUSECTRL_0_FUSECTRL_STATE_STATE_POST_RESET                 _MK_ENUM_CONST(1)
+#define FUSE_FUSECTRL_0_FUSECTRL_STATE_STATE_LOAD_ROW0                  _MK_ENUM_CONST(2)
+#define FUSE_FUSECTRL_0_FUSECTRL_STATE_STATE_LOAD_ROW1                  _MK_ENUM_CONST(3)
+#define FUSE_FUSECTRL_0_FUSECTRL_STATE_STATE_IDLE                       _MK_ENUM_CONST(4)
+#define FUSE_FUSECTRL_0_FUSECTRL_STATE_STATE_READ_SETUP                 _MK_ENUM_CONST(5)
+#define FUSE_FUSECTRL_0_FUSECTRL_STATE_STATE_READ_STROBE                        _MK_ENUM_CONST(6)
+#define FUSE_FUSECTRL_0_FUSECTRL_STATE_STATE_SAMPLE_FUSES                       _MK_ENUM_CONST(7)
+#define FUSE_FUSECTRL_0_FUSECTRL_STATE_STATE_READ_HOLD                  _MK_ENUM_CONST(8)
+#define FUSE_FUSECTRL_0_FUSECTRL_STATE_STATE_WRITE_SETUP                        _MK_ENUM_CONST(9)
+#define FUSE_FUSECTRL_0_FUSECTRL_STATE_STATE_WRITE_ADDR_SETUP                   _MK_ENUM_CONST(10)
+#define FUSE_FUSECTRL_0_FUSECTRL_STATE_STATE_WRITE_PROGRAM                      _MK_ENUM_CONST(11)
+#define FUSE_FUSECTRL_0_FUSECTRL_STATE_STATE_WRITE_ADDR_HOLD                    _MK_ENUM_CONST(12)
+
+#define FUSE_FUSECTRL_0_FUSECTRL_FUSE_SENSE_DONE_SHIFT                  _MK_SHIFT_CONST(30)
+#define FUSE_FUSECTRL_0_FUSECTRL_FUSE_SENSE_DONE_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_FUSECTRL_0_FUSECTRL_FUSE_SENSE_DONE_SHIFT)
+#define FUSE_FUSECTRL_0_FUSECTRL_FUSE_SENSE_DONE_RANGE                  30:30
+#define FUSE_FUSECTRL_0_FUSECTRL_FUSE_SENSE_DONE_WOFFSET                        0x0
+#define FUSE_FUSECTRL_0_FUSECTRL_FUSE_SENSE_DONE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSECTRL_0_FUSECTRL_FUSE_SENSE_DONE_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSECTRL_0_FUSECTRL_FUSE_SENSE_DONE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSECTRL_0_FUSECTRL_FUSE_SENSE_DONE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSECTRL_0_FUSECTRL_RAMREPAIR_SHIFT_DONE_SHIFT                     _MK_SHIFT_CONST(31)
+#define FUSE_FUSECTRL_0_FUSECTRL_RAMREPAIR_SHIFT_DONE_FIELD                     (_MK_MASK_CONST(0x1) << FUSE_FUSECTRL_0_FUSECTRL_RAMREPAIR_SHIFT_DONE_SHIFT)
+#define FUSE_FUSECTRL_0_FUSECTRL_RAMREPAIR_SHIFT_DONE_RANGE                     31:31
+#define FUSE_FUSECTRL_0_FUSECTRL_RAMREPAIR_SHIFT_DONE_WOFFSET                   0x0
+#define FUSE_FUSECTRL_0_FUSECTRL_RAMREPAIR_SHIFT_DONE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSECTRL_0_FUSECTRL_RAMREPAIR_SHIFT_DONE_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSECTRL_0_FUSECTRL_RAMREPAIR_SHIFT_DONE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSECTRL_0_FUSECTRL_RAMREPAIR_SHIFT_DONE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_FUSEADDR_0  
+#define FUSE_FUSEADDR_0                 _MK_ADDR_CONST(0x4)
+#define FUSE_FUSEADDR_0_SECURE                  0x0
+#define FUSE_FUSEADDR_0_WORD_COUNT                      0x1
+#define FUSE_FUSEADDR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEADDR_0_RESET_MASK                      _MK_MASK_CONST(0xff)
+#define FUSE_FUSEADDR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEADDR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define FUSE_FUSEADDR_0_READ_MASK                       _MK_MASK_CONST(0xff)
+#define FUSE_FUSEADDR_0_WRITE_MASK                      _MK_MASK_CONST(0xff)
+#define FUSE_FUSEADDR_0_FUSEADDR_VLDFLD_SHIFT                   _MK_SHIFT_CONST(0)
+#define FUSE_FUSEADDR_0_FUSEADDR_VLDFLD_FIELD                   (_MK_MASK_CONST(0xff) << FUSE_FUSEADDR_0_FUSEADDR_VLDFLD_SHIFT)
+#define FUSE_FUSEADDR_0_FUSEADDR_VLDFLD_RANGE                   7:0
+#define FUSE_FUSEADDR_0_FUSEADDR_VLDFLD_WOFFSET                 0x0
+#define FUSE_FUSEADDR_0_FUSEADDR_VLDFLD_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEADDR_0_FUSEADDR_VLDFLD_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define FUSE_FUSEADDR_0_FUSEADDR_VLDFLD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEADDR_0_FUSEADDR_VLDFLD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_FUSERDATA_0  
+#define FUSE_FUSERDATA_0                        _MK_ADDR_CONST(0x8)
+#define FUSE_FUSERDATA_0_SECURE                         0x0
+#define FUSE_FUSERDATA_0_WORD_COUNT                     0x1
+#define FUSE_FUSERDATA_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSERDATA_0_RESET_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSERDATA_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define FUSE_FUSERDATA_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSERDATA_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSERDATA_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSERDATA_0_FUSERDATA_DATA_SHIFT                   _MK_SHIFT_CONST(0)
+#define FUSE_FUSERDATA_0_FUSERDATA_DATA_FIELD                   (_MK_MASK_CONST(0xffffffff) << FUSE_FUSERDATA_0_FUSERDATA_DATA_SHIFT)
+#define FUSE_FUSERDATA_0_FUSERDATA_DATA_RANGE                   31:0
+#define FUSE_FUSERDATA_0_FUSERDATA_DATA_WOFFSET                 0x0
+#define FUSE_FUSERDATA_0_FUSERDATA_DATA_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSERDATA_0_FUSERDATA_DATA_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSERDATA_0_FUSERDATA_DATA_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSERDATA_0_FUSERDATA_DATA_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_FUSEWDATA_0  
+#define FUSE_FUSEWDATA_0                        _MK_ADDR_CONST(0xc)
+#define FUSE_FUSEWDATA_0_SECURE                         0x0
+#define FUSE_FUSEWDATA_0_WORD_COUNT                     0x1
+#define FUSE_FUSEWDATA_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWDATA_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWDATA_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWDATA_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWDATA_0_READ_MASK                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWDATA_0_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWDATA_0_FUSEWDATA_DATA_SHIFT                   _MK_SHIFT_CONST(0)
+#define FUSE_FUSEWDATA_0_FUSEWDATA_DATA_FIELD                   (_MK_MASK_CONST(0xffffffff) << FUSE_FUSEWDATA_0_FUSEWDATA_DATA_SHIFT)
+#define FUSE_FUSEWDATA_0_FUSEWDATA_DATA_RANGE                   31:0
+#define FUSE_FUSEWDATA_0_FUSEWDATA_DATA_WOFFSET                 0x0
+#define FUSE_FUSEWDATA_0_FUSEWDATA_DATA_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWDATA_0_FUSEWDATA_DATA_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWDATA_0_FUSEWDATA_DATA_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWDATA_0_FUSEWDATA_DATA_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_FUSETIME_RD1_0  
+#define FUSE_FUSETIME_RD1_0                     _MK_ADDR_CONST(0x10)
+#define FUSE_FUSETIME_RD1_0_SECURE                      0x0
+#define FUSE_FUSETIME_RD1_0_WORD_COUNT                  0x1
+#define FUSE_FUSETIME_RD1_0_RESET_VAL                   _MK_MASK_CONST(0x10201)
+#define FUSE_FUSETIME_RD1_0_RESET_MASK                  _MK_MASK_CONST(0xffffff)
+#define FUSE_FUSETIME_RD1_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSETIME_RD1_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSETIME_RD1_0_READ_MASK                   _MK_MASK_CONST(0xffffff)
+#define FUSE_FUSETIME_RD1_0_WRITE_MASK                  _MK_MASK_CONST(0xffffff)
+#define FUSE_FUSETIME_RD1_0_FUSETIME_RD1_TSUR_MAX_SHIFT                 _MK_SHIFT_CONST(0)
+#define FUSE_FUSETIME_RD1_0_FUSETIME_RD1_TSUR_MAX_FIELD                 (_MK_MASK_CONST(0xff) << FUSE_FUSETIME_RD1_0_FUSETIME_RD1_TSUR_MAX_SHIFT)
+#define FUSE_FUSETIME_RD1_0_FUSETIME_RD1_TSUR_MAX_RANGE                 7:0
+#define FUSE_FUSETIME_RD1_0_FUSETIME_RD1_TSUR_MAX_WOFFSET                       0x0
+#define FUSE_FUSETIME_RD1_0_FUSETIME_RD1_TSUR_MAX_DEFAULT                       _MK_MASK_CONST(0x1)
+#define FUSE_FUSETIME_RD1_0_FUSETIME_RD1_TSUR_MAX_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define FUSE_FUSETIME_RD1_0_FUSETIME_RD1_TSUR_MAX_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSETIME_RD1_0_FUSETIME_RD1_TSUR_MAX_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSETIME_RD1_0_FUSETIME_RD1_TSUR_FUSEOUT_SHIFT                     _MK_SHIFT_CONST(8)
+#define FUSE_FUSETIME_RD1_0_FUSETIME_RD1_TSUR_FUSEOUT_FIELD                     (_MK_MASK_CONST(0xff) << FUSE_FUSETIME_RD1_0_FUSETIME_RD1_TSUR_FUSEOUT_SHIFT)
+#define FUSE_FUSETIME_RD1_0_FUSETIME_RD1_TSUR_FUSEOUT_RANGE                     15:8
+#define FUSE_FUSETIME_RD1_0_FUSETIME_RD1_TSUR_FUSEOUT_WOFFSET                   0x0
+#define FUSE_FUSETIME_RD1_0_FUSETIME_RD1_TSUR_FUSEOUT_DEFAULT                   _MK_MASK_CONST(0x2)
+#define FUSE_FUSETIME_RD1_0_FUSETIME_RD1_TSUR_FUSEOUT_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define FUSE_FUSETIME_RD1_0_FUSETIME_RD1_TSUR_FUSEOUT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSETIME_RD1_0_FUSETIME_RD1_TSUR_FUSEOUT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSETIME_RD1_0_FUSETIME_RD1_THR_MAX_SHIFT                  _MK_SHIFT_CONST(16)
+#define FUSE_FUSETIME_RD1_0_FUSETIME_RD1_THR_MAX_FIELD                  (_MK_MASK_CONST(0xff) << FUSE_FUSETIME_RD1_0_FUSETIME_RD1_THR_MAX_SHIFT)
+#define FUSE_FUSETIME_RD1_0_FUSETIME_RD1_THR_MAX_RANGE                  23:16
+#define FUSE_FUSETIME_RD1_0_FUSETIME_RD1_THR_MAX_WOFFSET                        0x0
+#define FUSE_FUSETIME_RD1_0_FUSETIME_RD1_THR_MAX_DEFAULT                        _MK_MASK_CONST(0x1)
+#define FUSE_FUSETIME_RD1_0_FUSETIME_RD1_THR_MAX_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
+#define FUSE_FUSETIME_RD1_0_FUSETIME_RD1_THR_MAX_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSETIME_RD1_0_FUSETIME_RD1_THR_MAX_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_FUSETIME_RD2_0  
+#define FUSE_FUSETIME_RD2_0                     _MK_ADDR_CONST(0x14)
+#define FUSE_FUSETIME_RD2_0_SECURE                      0x0
+#define FUSE_FUSETIME_RD2_0_WORD_COUNT                  0x1
+#define FUSE_FUSETIME_RD2_0_RESET_VAL                   _MK_MASK_CONST(0x3)
+#define FUSE_FUSETIME_RD2_0_RESET_MASK                  _MK_MASK_CONST(0xffff)
+#define FUSE_FUSETIME_RD2_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSETIME_RD2_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSETIME_RD2_0_READ_MASK                   _MK_MASK_CONST(0xffff)
+#define FUSE_FUSETIME_RD2_0_WRITE_MASK                  _MK_MASK_CONST(0xffff)
+#define FUSE_FUSETIME_RD2_0_FUSETIME_RD2_TWIDTH_RD_SHIFT                        _MK_SHIFT_CONST(0)
+#define FUSE_FUSETIME_RD2_0_FUSETIME_RD2_TWIDTH_RD_FIELD                        (_MK_MASK_CONST(0xffff) << FUSE_FUSETIME_RD2_0_FUSETIME_RD2_TWIDTH_RD_SHIFT)
+#define FUSE_FUSETIME_RD2_0_FUSETIME_RD2_TWIDTH_RD_RANGE                        15:0
+#define FUSE_FUSETIME_RD2_0_FUSETIME_RD2_TWIDTH_RD_WOFFSET                      0x0
+#define FUSE_FUSETIME_RD2_0_FUSETIME_RD2_TWIDTH_RD_DEFAULT                      _MK_MASK_CONST(0x3)
+#define FUSE_FUSETIME_RD2_0_FUSETIME_RD2_TWIDTH_RD_DEFAULT_MASK                 _MK_MASK_CONST(0xffff)
+#define FUSE_FUSETIME_RD2_0_FUSETIME_RD2_TWIDTH_RD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSETIME_RD2_0_FUSETIME_RD2_TWIDTH_RD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_FUSETIME_PGM1_0  
+#define FUSE_FUSETIME_PGM1_0                    _MK_ADDR_CONST(0x18)
+#define FUSE_FUSETIME_PGM1_0_SECURE                     0x0
+#define FUSE_FUSETIME_PGM1_0_WORD_COUNT                         0x1
+#define FUSE_FUSETIME_PGM1_0_RESET_VAL                  _MK_MASK_CONST(0x101a0)
+#define FUSE_FUSETIME_PGM1_0_RESET_MASK                         _MK_MASK_CONST(0xffffff)
+#define FUSE_FUSETIME_PGM1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSETIME_PGM1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSETIME_PGM1_0_READ_MASK                  _MK_MASK_CONST(0xffffff)
+#define FUSE_FUSETIME_PGM1_0_WRITE_MASK                         _MK_MASK_CONST(0xffffff)
+#define FUSE_FUSETIME_PGM1_0_FUSETIME_PGM1_TSUP_MAX_SHIFT                       _MK_SHIFT_CONST(0)
+#define FUSE_FUSETIME_PGM1_0_FUSETIME_PGM1_TSUP_MAX_FIELD                       (_MK_MASK_CONST(0xff) << FUSE_FUSETIME_PGM1_0_FUSETIME_PGM1_TSUP_MAX_SHIFT)
+#define FUSE_FUSETIME_PGM1_0_FUSETIME_PGM1_TSUP_MAX_RANGE                       7:0
+#define FUSE_FUSETIME_PGM1_0_FUSETIME_PGM1_TSUP_MAX_WOFFSET                     0x0
+#define FUSE_FUSETIME_PGM1_0_FUSETIME_PGM1_TSUP_MAX_DEFAULT                     _MK_MASK_CONST(0xa0)
+#define FUSE_FUSETIME_PGM1_0_FUSETIME_PGM1_TSUP_MAX_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define FUSE_FUSETIME_PGM1_0_FUSETIME_PGM1_TSUP_MAX_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSETIME_PGM1_0_FUSETIME_PGM1_TSUP_MAX_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSETIME_PGM1_0_FUSETIME_PGM1_TSUP_ADDR_SHIFT                      _MK_SHIFT_CONST(8)
+#define FUSE_FUSETIME_PGM1_0_FUSETIME_PGM1_TSUP_ADDR_FIELD                      (_MK_MASK_CONST(0xff) << FUSE_FUSETIME_PGM1_0_FUSETIME_PGM1_TSUP_ADDR_SHIFT)
+#define FUSE_FUSETIME_PGM1_0_FUSETIME_PGM1_TSUP_ADDR_RANGE                      15:8
+#define FUSE_FUSETIME_PGM1_0_FUSETIME_PGM1_TSUP_ADDR_WOFFSET                    0x0
+#define FUSE_FUSETIME_PGM1_0_FUSETIME_PGM1_TSUP_ADDR_DEFAULT                    _MK_MASK_CONST(0x1)
+#define FUSE_FUSETIME_PGM1_0_FUSETIME_PGM1_TSUP_ADDR_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
+#define FUSE_FUSETIME_PGM1_0_FUSETIME_PGM1_TSUP_ADDR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSETIME_PGM1_0_FUSETIME_PGM1_TSUP_ADDR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSETIME_PGM1_0_FUSETIME_PGM1_THP_ADDR_SHIFT                       _MK_SHIFT_CONST(16)
+#define FUSE_FUSETIME_PGM1_0_FUSETIME_PGM1_THP_ADDR_FIELD                       (_MK_MASK_CONST(0xff) << FUSE_FUSETIME_PGM1_0_FUSETIME_PGM1_THP_ADDR_SHIFT)
+#define FUSE_FUSETIME_PGM1_0_FUSETIME_PGM1_THP_ADDR_RANGE                       23:16
+#define FUSE_FUSETIME_PGM1_0_FUSETIME_PGM1_THP_ADDR_WOFFSET                     0x0
+#define FUSE_FUSETIME_PGM1_0_FUSETIME_PGM1_THP_ADDR_DEFAULT                     _MK_MASK_CONST(0x1)
+#define FUSE_FUSETIME_PGM1_0_FUSETIME_PGM1_THP_ADDR_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define FUSE_FUSETIME_PGM1_0_FUSETIME_PGM1_THP_ADDR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSETIME_PGM1_0_FUSETIME_PGM1_THP_ADDR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_FUSETIME_PGM2_0  
+#define FUSE_FUSETIME_PGM2_0                    _MK_ADDR_CONST(0x1c)
+#define FUSE_FUSETIME_PGM2_0_SECURE                     0x0
+#define FUSE_FUSETIME_PGM2_0_WORD_COUNT                         0x1
+#define FUSE_FUSETIME_PGM2_0_RESET_VAL                  _MK_MASK_CONST(0x104)
+#define FUSE_FUSETIME_PGM2_0_RESET_MASK                         _MK_MASK_CONST(0xffff)
+#define FUSE_FUSETIME_PGM2_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSETIME_PGM2_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSETIME_PGM2_0_READ_MASK                  _MK_MASK_CONST(0xffff)
+#define FUSE_FUSETIME_PGM2_0_WRITE_MASK                         _MK_MASK_CONST(0xffff)
+#define FUSE_FUSETIME_PGM2_0_FUSETIME_PGM2_TWIDTH_PGM_SHIFT                     _MK_SHIFT_CONST(0)
+#define FUSE_FUSETIME_PGM2_0_FUSETIME_PGM2_TWIDTH_PGM_FIELD                     (_MK_MASK_CONST(0xffff) << FUSE_FUSETIME_PGM2_0_FUSETIME_PGM2_TWIDTH_PGM_SHIFT)
+#define FUSE_FUSETIME_PGM2_0_FUSETIME_PGM2_TWIDTH_PGM_RANGE                     15:0
+#define FUSE_FUSETIME_PGM2_0_FUSETIME_PGM2_TWIDTH_PGM_WOFFSET                   0x0
+#define FUSE_FUSETIME_PGM2_0_FUSETIME_PGM2_TWIDTH_PGM_DEFAULT                   _MK_MASK_CONST(0x104)
+#define FUSE_FUSETIME_PGM2_0_FUSETIME_PGM2_TWIDTH_PGM_DEFAULT_MASK                      _MK_MASK_CONST(0xffff)
+#define FUSE_FUSETIME_PGM2_0_FUSETIME_PGM2_TWIDTH_PGM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSETIME_PGM2_0_FUSETIME_PGM2_TWIDTH_PGM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_PRIV2INTFC_START_0  
+#define FUSE_PRIV2INTFC_START_0                 _MK_ADDR_CONST(0x20)
+#define FUSE_PRIV2INTFC_START_0_SECURE                  0x0
+#define FUSE_PRIV2INTFC_START_0_WORD_COUNT                      0x1
+#define FUSE_PRIV2INTFC_START_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define FUSE_PRIV2INTFC_START_0_RESET_MASK                      _MK_MASK_CONST(0x3)
+#define FUSE_PRIV2INTFC_START_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define FUSE_PRIV2INTFC_START_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define FUSE_PRIV2INTFC_START_0_READ_MASK                       _MK_MASK_CONST(0x0)
+#define FUSE_PRIV2INTFC_START_0_WRITE_MASK                      _MK_MASK_CONST(0x3)
+#define FUSE_PRIV2INTFC_START_0_PRIV2INTFC_START_DATA_SHIFT                     _MK_SHIFT_CONST(0)
+#define FUSE_PRIV2INTFC_START_0_PRIV2INTFC_START_DATA_FIELD                     (_MK_MASK_CONST(0x1) << FUSE_PRIV2INTFC_START_0_PRIV2INTFC_START_DATA_SHIFT)
+#define FUSE_PRIV2INTFC_START_0_PRIV2INTFC_START_DATA_RANGE                     0:0
+#define FUSE_PRIV2INTFC_START_0_PRIV2INTFC_START_DATA_WOFFSET                   0x0
+#define FUSE_PRIV2INTFC_START_0_PRIV2INTFC_START_DATA_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_PRIV2INTFC_START_0_PRIV2INTFC_START_DATA_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FUSE_PRIV2INTFC_START_0_PRIV2INTFC_START_DATA_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_PRIV2INTFC_START_0_PRIV2INTFC_START_DATA_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FUSE_PRIV2INTFC_START_0_PRIV2INTFC_SKIP_RAMREPAIR_SHIFT                 _MK_SHIFT_CONST(1)
+#define FUSE_PRIV2INTFC_START_0_PRIV2INTFC_SKIP_RAMREPAIR_FIELD                 (_MK_MASK_CONST(0x1) << FUSE_PRIV2INTFC_START_0_PRIV2INTFC_SKIP_RAMREPAIR_SHIFT)
+#define FUSE_PRIV2INTFC_START_0_PRIV2INTFC_SKIP_RAMREPAIR_RANGE                 1:1
+#define FUSE_PRIV2INTFC_START_0_PRIV2INTFC_SKIP_RAMREPAIR_WOFFSET                       0x0
+#define FUSE_PRIV2INTFC_START_0_PRIV2INTFC_SKIP_RAMREPAIR_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_PRIV2INTFC_START_0_PRIV2INTFC_SKIP_RAMREPAIR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_PRIV2INTFC_START_0_PRIV2INTFC_SKIP_RAMREPAIR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_PRIV2INTFC_START_0_PRIV2INTFC_SKIP_RAMREPAIR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_FUSEBYPASS_0  
+#define FUSE_FUSEBYPASS_0                       _MK_ADDR_CONST(0x24)
+#define FUSE_FUSEBYPASS_0_SECURE                        0x0
+#define FUSE_FUSEBYPASS_0_WORD_COUNT                    0x1
+#define FUSE_FUSEBYPASS_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEBYPASS_0_RESET_MASK                    _MK_MASK_CONST(0x1)
+#define FUSE_FUSEBYPASS_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEBYPASS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEBYPASS_0_READ_MASK                     _MK_MASK_CONST(0x1)
+#define FUSE_FUSEBYPASS_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
+#define FUSE_FUSEBYPASS_0_FUSEBYPASS_VAL_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_FUSEBYPASS_0_FUSEBYPASS_VAL_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_FUSEBYPASS_0_FUSEBYPASS_VAL_SHIFT)
+#define FUSE_FUSEBYPASS_0_FUSEBYPASS_VAL_RANGE                  0:0
+#define FUSE_FUSEBYPASS_0_FUSEBYPASS_VAL_WOFFSET                        0x0
+#define FUSE_FUSEBYPASS_0_FUSEBYPASS_VAL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEBYPASS_0_FUSEBYPASS_VAL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_FUSEBYPASS_0_FUSEBYPASS_VAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEBYPASS_0_FUSEBYPASS_VAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEBYPASS_0_FUSEBYPASS_VAL_INIT_ENUM                      DISABLED
+#define FUSE_FUSEBYPASS_0_FUSEBYPASS_VAL_DISABLED                       _MK_ENUM_CONST(0)
+#define FUSE_FUSEBYPASS_0_FUSEBYPASS_VAL_ENABLED                        _MK_ENUM_CONST(1)
+#define FUSE_FUSEBYPASS_0_FUSEBYPASS_VAL_DISABLE                        _MK_ENUM_CONST(0)
+#define FUSE_FUSEBYPASS_0_FUSEBYPASS_VAL_ENABLE                 _MK_ENUM_CONST(1)
+
+
+// Register FUSE_PRIVATEKEYDISABLE_0  
+#define FUSE_PRIVATEKEYDISABLE_0                        _MK_ADDR_CONST(0x28)
+#define FUSE_PRIVATEKEYDISABLE_0_SECURE                         0x0
+#define FUSE_PRIVATEKEYDISABLE_0_WORD_COUNT                     0x1
+#define FUSE_PRIVATEKEYDISABLE_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATEKEYDISABLE_0_RESET_MASK                     _MK_MASK_CONST(0x1)
+#define FUSE_PRIVATEKEYDISABLE_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATEKEYDISABLE_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATEKEYDISABLE_0_READ_MASK                      _MK_MASK_CONST(0x1)
+#define FUSE_PRIVATEKEYDISABLE_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
+#define FUSE_PRIVATEKEYDISABLE_0_PRIVATEKEYDISABLE_VAL_SHIFT                    _MK_SHIFT_CONST(0)
+#define FUSE_PRIVATEKEYDISABLE_0_PRIVATEKEYDISABLE_VAL_FIELD                    (_MK_MASK_CONST(0x1) << FUSE_PRIVATEKEYDISABLE_0_PRIVATEKEYDISABLE_VAL_SHIFT)
+#define FUSE_PRIVATEKEYDISABLE_0_PRIVATEKEYDISABLE_VAL_RANGE                    0:0
+#define FUSE_PRIVATEKEYDISABLE_0_PRIVATEKEYDISABLE_VAL_WOFFSET                  0x0
+#define FUSE_PRIVATEKEYDISABLE_0_PRIVATEKEYDISABLE_VAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATEKEYDISABLE_0_PRIVATEKEYDISABLE_VAL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FUSE_PRIVATEKEYDISABLE_0_PRIVATEKEYDISABLE_VAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATEKEYDISABLE_0_PRIVATEKEYDISABLE_VAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATEKEYDISABLE_0_PRIVATEKEYDISABLE_VAL_INIT_ENUM                        KEY_VISIBLE
+#define FUSE_PRIVATEKEYDISABLE_0_PRIVATEKEYDISABLE_VAL_KEY_VISIBLE                      _MK_ENUM_CONST(0)
+#define FUSE_PRIVATEKEYDISABLE_0_PRIVATEKEYDISABLE_VAL_KEY_INVISIBLE                    _MK_ENUM_CONST(1)
+
+
+// Register FUSE_DISABLEREGPROGRAM_0  
+#define FUSE_DISABLEREGPROGRAM_0                        _MK_ADDR_CONST(0x2c)
+#define FUSE_DISABLEREGPROGRAM_0_SECURE                         0x0
+#define FUSE_DISABLEREGPROGRAM_0_WORD_COUNT                     0x1
+#define FUSE_DISABLEREGPROGRAM_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_DISABLEREGPROGRAM_0_RESET_MASK                     _MK_MASK_CONST(0x1)
+#define FUSE_DISABLEREGPROGRAM_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define FUSE_DISABLEREGPROGRAM_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define FUSE_DISABLEREGPROGRAM_0_READ_MASK                      _MK_MASK_CONST(0x1)
+#define FUSE_DISABLEREGPROGRAM_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
+#define FUSE_DISABLEREGPROGRAM_0_DISABLEREGPROGRAM_VAL_SHIFT                    _MK_SHIFT_CONST(0)
+#define FUSE_DISABLEREGPROGRAM_0_DISABLEREGPROGRAM_VAL_FIELD                    (_MK_MASK_CONST(0x1) << FUSE_DISABLEREGPROGRAM_0_DISABLEREGPROGRAM_VAL_SHIFT)
+#define FUSE_DISABLEREGPROGRAM_0_DISABLEREGPROGRAM_VAL_RANGE                    0:0
+#define FUSE_DISABLEREGPROGRAM_0_DISABLEREGPROGRAM_VAL_WOFFSET                  0x0
+#define FUSE_DISABLEREGPROGRAM_0_DISABLEREGPROGRAM_VAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_DISABLEREGPROGRAM_0_DISABLEREGPROGRAM_VAL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FUSE_DISABLEREGPROGRAM_0_DISABLEREGPROGRAM_VAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_DISABLEREGPROGRAM_0_DISABLEREGPROGRAM_VAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_DISABLEREGPROGRAM_0_DISABLEREGPROGRAM_VAL_INIT_ENUM                        DISABLED
+#define FUSE_DISABLEREGPROGRAM_0_DISABLEREGPROGRAM_VAL_DISABLED                 _MK_ENUM_CONST(0)
+#define FUSE_DISABLEREGPROGRAM_0_DISABLEREGPROGRAM_VAL_ENABLED                  _MK_ENUM_CONST(1)
+#define FUSE_DISABLEREGPROGRAM_0_DISABLEREGPROGRAM_VAL_DISABLE                  _MK_ENUM_CONST(0)
+#define FUSE_DISABLEREGPROGRAM_0_DISABLEREGPROGRAM_VAL_ENABLE                   _MK_ENUM_CONST(1)
+
+
+// Register FUSE_WRITE_ACCESS_SW_0  
+#define FUSE_WRITE_ACCESS_SW_0                  _MK_ADDR_CONST(0x30)
+#define FUSE_WRITE_ACCESS_SW_0_SECURE                   0x0
+#define FUSE_WRITE_ACCESS_SW_0_WORD_COUNT                       0x1
+#define FUSE_WRITE_ACCESS_SW_0_RESET_VAL                        _MK_MASK_CONST(0x1)
+#define FUSE_WRITE_ACCESS_SW_0_RESET_MASK                       _MK_MASK_CONST(0x1)
+#define FUSE_WRITE_ACCESS_SW_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_WRITE_ACCESS_SW_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_WRITE_ACCESS_SW_0_READ_MASK                        _MK_MASK_CONST(0x10001)
+#define FUSE_WRITE_ACCESS_SW_0_WRITE_MASK                       _MK_MASK_CONST(0x10001)
+#define FUSE_WRITE_ACCESS_SW_0_WRITE_ACCESS_SW_CTRL_SHIFT                       _MK_SHIFT_CONST(0)
+#define FUSE_WRITE_ACCESS_SW_0_WRITE_ACCESS_SW_CTRL_FIELD                       (_MK_MASK_CONST(0x1) << FUSE_WRITE_ACCESS_SW_0_WRITE_ACCESS_SW_CTRL_SHIFT)
+#define FUSE_WRITE_ACCESS_SW_0_WRITE_ACCESS_SW_CTRL_RANGE                       0:0
+#define FUSE_WRITE_ACCESS_SW_0_WRITE_ACCESS_SW_CTRL_WOFFSET                     0x0
+#define FUSE_WRITE_ACCESS_SW_0_WRITE_ACCESS_SW_CTRL_DEFAULT                     _MK_MASK_CONST(0x1)
+#define FUSE_WRITE_ACCESS_SW_0_WRITE_ACCESS_SW_CTRL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FUSE_WRITE_ACCESS_SW_0_WRITE_ACCESS_SW_CTRL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_WRITE_ACCESS_SW_0_WRITE_ACCESS_SW_CTRL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_WRITE_ACCESS_SW_0_WRITE_ACCESS_SW_CTRL_INIT_ENUM                   READONLY
+#define FUSE_WRITE_ACCESS_SW_0_WRITE_ACCESS_SW_CTRL_READWRITE                   _MK_ENUM_CONST(0)
+#define FUSE_WRITE_ACCESS_SW_0_WRITE_ACCESS_SW_CTRL_READONLY                    _MK_ENUM_CONST(1)
+
+#define FUSE_WRITE_ACCESS_SW_0_WRITE_ACCESS_SW_STATUS_SHIFT                     _MK_SHIFT_CONST(16)
+#define FUSE_WRITE_ACCESS_SW_0_WRITE_ACCESS_SW_STATUS_FIELD                     (_MK_MASK_CONST(0x1) << FUSE_WRITE_ACCESS_SW_0_WRITE_ACCESS_SW_STATUS_SHIFT)
+#define FUSE_WRITE_ACCESS_SW_0_WRITE_ACCESS_SW_STATUS_RANGE                     16:16
+#define FUSE_WRITE_ACCESS_SW_0_WRITE_ACCESS_SW_STATUS_WOFFSET                   0x0
+#define FUSE_WRITE_ACCESS_SW_0_WRITE_ACCESS_SW_STATUS_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_WRITE_ACCESS_SW_0_WRITE_ACCESS_SW_STATUS_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define FUSE_WRITE_ACCESS_SW_0_WRITE_ACCESS_SW_STATUS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_WRITE_ACCESS_SW_0_WRITE_ACCESS_SW_STATUS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define FUSE_WRITE_ACCESS_SW_0_WRITE_ACCESS_SW_STATUS_NOWRITE                   _MK_ENUM_CONST(0)
+#define FUSE_WRITE_ACCESS_SW_0_WRITE_ACCESS_SW_STATUS_WRITE                     _MK_ENUM_CONST(1)
+
+
+// Register FUSE_PWR_GOOD_SW_0  
+#define FUSE_PWR_GOOD_SW_0                      _MK_ADDR_CONST(0x34)
+#define FUSE_PWR_GOOD_SW_0_SECURE                       0x0
+#define FUSE_PWR_GOOD_SW_0_WORD_COUNT                   0x1
+#define FUSE_PWR_GOOD_SW_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define FUSE_PWR_GOOD_SW_0_RESET_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_PWR_GOOD_SW_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define FUSE_PWR_GOOD_SW_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define FUSE_PWR_GOOD_SW_0_READ_MASK                    _MK_MASK_CONST(0x1)
+#define FUSE_PWR_GOOD_SW_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_PWR_GOOD_SW_0_PWR_GOOD_SW_VAL_SHIFT                        _MK_SHIFT_CONST(0)
+#define FUSE_PWR_GOOD_SW_0_PWR_GOOD_SW_VAL_FIELD                        (_MK_MASK_CONST(0x1) << FUSE_PWR_GOOD_SW_0_PWR_GOOD_SW_VAL_SHIFT)
+#define FUSE_PWR_GOOD_SW_0_PWR_GOOD_SW_VAL_RANGE                        0:0
+#define FUSE_PWR_GOOD_SW_0_PWR_GOOD_SW_VAL_WOFFSET                      0x0
+#define FUSE_PWR_GOOD_SW_0_PWR_GOOD_SW_VAL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_PWR_GOOD_SW_0_PWR_GOOD_SW_VAL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define FUSE_PWR_GOOD_SW_0_PWR_GOOD_SW_VAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_PWR_GOOD_SW_0_PWR_GOOD_SW_VAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define FUSE_PWR_GOOD_SW_0_PWR_GOOD_SW_VAL_INIT_ENUM                    PWR_GOOD_NOT_OK
+#define FUSE_PWR_GOOD_SW_0_PWR_GOOD_SW_VAL_PWR_GOOD_NOT_OK                      _MK_ENUM_CONST(0)
+#define FUSE_PWR_GOOD_SW_0_PWR_GOOD_SW_VAL_PWR_GOOD_OK                  _MK_ENUM_CONST(1)
+
+
+// Reserved address 56 [0x38] 
+
+// Reserved address 60 [0x3c] 
+
+// Reserved address 64 [0x40] 
+
+// Reserved address 68 [0x44] 
+
+// Register FUSE_REG_REF_CTRL_0  
+#define FUSE_REG_REF_CTRL_0                     _MK_ADDR_CONST(0x48)
+#define FUSE_REG_REF_CTRL_0_SECURE                      0x0
+#define FUSE_REG_REF_CTRL_0_WORD_COUNT                  0x1
+#define FUSE_REG_REF_CTRL_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_REG_REF_CTRL_0_RESET_MASK                  _MK_MASK_CONST(0x3)
+#define FUSE_REG_REF_CTRL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_REG_REF_CTRL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_REG_REF_CTRL_0_READ_MASK                   _MK_MASK_CONST(0x3)
+#define FUSE_REG_REF_CTRL_0_WRITE_MASK                  _MK_MASK_CONST(0x3)
+#define FUSE_REG_REF_CTRL_0_REG_REF_CTRL_DATA_SHIFT                     _MK_SHIFT_CONST(0)
+#define FUSE_REG_REF_CTRL_0_REG_REF_CTRL_DATA_FIELD                     (_MK_MASK_CONST(0x3) << FUSE_REG_REF_CTRL_0_REG_REF_CTRL_DATA_SHIFT)
+#define FUSE_REG_REF_CTRL_0_REG_REF_CTRL_DATA_RANGE                     1:0
+#define FUSE_REG_REF_CTRL_0_REG_REF_CTRL_DATA_WOFFSET                   0x0
+#define FUSE_REG_REF_CTRL_0_REG_REF_CTRL_DATA_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_REG_REF_CTRL_0_REG_REF_CTRL_DATA_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define FUSE_REG_REF_CTRL_0_REG_REF_CTRL_DATA_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_REG_REF_CTRL_0_REG_REF_CTRL_DATA_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_REG_BIAS_CTRL_0  
+#define FUSE_REG_BIAS_CTRL_0                    _MK_ADDR_CONST(0x4c)
+#define FUSE_REG_BIAS_CTRL_0_SECURE                     0x0
+#define FUSE_REG_BIAS_CTRL_0_WORD_COUNT                         0x1
+#define FUSE_REG_BIAS_CTRL_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define FUSE_REG_BIAS_CTRL_0_RESET_MASK                         _MK_MASK_CONST(0x3)
+#define FUSE_REG_BIAS_CTRL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define FUSE_REG_BIAS_CTRL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define FUSE_REG_BIAS_CTRL_0_READ_MASK                  _MK_MASK_CONST(0x3)
+#define FUSE_REG_BIAS_CTRL_0_WRITE_MASK                         _MK_MASK_CONST(0x3)
+#define FUSE_REG_BIAS_CTRL_0_REG_BIAS_CTRL_DATA_SHIFT                   _MK_SHIFT_CONST(0)
+#define FUSE_REG_BIAS_CTRL_0_REG_BIAS_CTRL_DATA_FIELD                   (_MK_MASK_CONST(0x3) << FUSE_REG_BIAS_CTRL_0_REG_BIAS_CTRL_DATA_SHIFT)
+#define FUSE_REG_BIAS_CTRL_0_REG_BIAS_CTRL_DATA_RANGE                   1:0
+#define FUSE_REG_BIAS_CTRL_0_REG_BIAS_CTRL_DATA_WOFFSET                 0x0
+#define FUSE_REG_BIAS_CTRL_0_REG_BIAS_CTRL_DATA_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_REG_BIAS_CTRL_0_REG_BIAS_CTRL_DATA_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define FUSE_REG_BIAS_CTRL_0_REG_BIAS_CTRL_DATA_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_REG_BIAS_CTRL_0_REG_BIAS_CTRL_DATA_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_PRIVATE_KEY0_NONZERO_0  
+#define FUSE_PRIVATE_KEY0_NONZERO_0                     _MK_ADDR_CONST(0x50)
+#define FUSE_PRIVATE_KEY0_NONZERO_0_SECURE                      0x0
+#define FUSE_PRIVATE_KEY0_NONZERO_0_WORD_COUNT                  0x1
+#define FUSE_PRIVATE_KEY0_NONZERO_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY0_NONZERO_0_RESET_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY0_NONZERO_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY0_NONZERO_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY0_NONZERO_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_PRIVATE_KEY0_NONZERO_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY0_NONZERO_0_PRIVATE_KEY0_NONZERO_DATA_SHIFT                     _MK_SHIFT_CONST(0)
+#define FUSE_PRIVATE_KEY0_NONZERO_0_PRIVATE_KEY0_NONZERO_DATA_FIELD                     (_MK_MASK_CONST(0x1) << FUSE_PRIVATE_KEY0_NONZERO_0_PRIVATE_KEY0_NONZERO_DATA_SHIFT)
+#define FUSE_PRIVATE_KEY0_NONZERO_0_PRIVATE_KEY0_NONZERO_DATA_RANGE                     0:0
+#define FUSE_PRIVATE_KEY0_NONZERO_0_PRIVATE_KEY0_NONZERO_DATA_WOFFSET                   0x0
+#define FUSE_PRIVATE_KEY0_NONZERO_0_PRIVATE_KEY0_NONZERO_DATA_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY0_NONZERO_0_PRIVATE_KEY0_NONZERO_DATA_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY0_NONZERO_0_PRIVATE_KEY0_NONZERO_DATA_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY0_NONZERO_0_PRIVATE_KEY0_NONZERO_DATA_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_PRIVATE_KEY1_NONZERO_0  
+#define FUSE_PRIVATE_KEY1_NONZERO_0                     _MK_ADDR_CONST(0x54)
+#define FUSE_PRIVATE_KEY1_NONZERO_0_SECURE                      0x0
+#define FUSE_PRIVATE_KEY1_NONZERO_0_WORD_COUNT                  0x1
+#define FUSE_PRIVATE_KEY1_NONZERO_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY1_NONZERO_0_RESET_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY1_NONZERO_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY1_NONZERO_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY1_NONZERO_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_PRIVATE_KEY1_NONZERO_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY1_NONZERO_0_PRIVATE_KEY1_NONZERO_DATA_SHIFT                     _MK_SHIFT_CONST(0)
+#define FUSE_PRIVATE_KEY1_NONZERO_0_PRIVATE_KEY1_NONZERO_DATA_FIELD                     (_MK_MASK_CONST(0x1) << FUSE_PRIVATE_KEY1_NONZERO_0_PRIVATE_KEY1_NONZERO_DATA_SHIFT)
+#define FUSE_PRIVATE_KEY1_NONZERO_0_PRIVATE_KEY1_NONZERO_DATA_RANGE                     0:0
+#define FUSE_PRIVATE_KEY1_NONZERO_0_PRIVATE_KEY1_NONZERO_DATA_WOFFSET                   0x0
+#define FUSE_PRIVATE_KEY1_NONZERO_0_PRIVATE_KEY1_NONZERO_DATA_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY1_NONZERO_0_PRIVATE_KEY1_NONZERO_DATA_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY1_NONZERO_0_PRIVATE_KEY1_NONZERO_DATA_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY1_NONZERO_0_PRIVATE_KEY1_NONZERO_DATA_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_PRIVATE_KEY2_NONZERO_0  
+#define FUSE_PRIVATE_KEY2_NONZERO_0                     _MK_ADDR_CONST(0x58)
+#define FUSE_PRIVATE_KEY2_NONZERO_0_SECURE                      0x0
+#define FUSE_PRIVATE_KEY2_NONZERO_0_WORD_COUNT                  0x1
+#define FUSE_PRIVATE_KEY2_NONZERO_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY2_NONZERO_0_RESET_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY2_NONZERO_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY2_NONZERO_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY2_NONZERO_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_PRIVATE_KEY2_NONZERO_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY2_NONZERO_0_PRIVATE_KEY2_NONZERO_DATA_SHIFT                     _MK_SHIFT_CONST(0)
+#define FUSE_PRIVATE_KEY2_NONZERO_0_PRIVATE_KEY2_NONZERO_DATA_FIELD                     (_MK_MASK_CONST(0x1) << FUSE_PRIVATE_KEY2_NONZERO_0_PRIVATE_KEY2_NONZERO_DATA_SHIFT)
+#define FUSE_PRIVATE_KEY2_NONZERO_0_PRIVATE_KEY2_NONZERO_DATA_RANGE                     0:0
+#define FUSE_PRIVATE_KEY2_NONZERO_0_PRIVATE_KEY2_NONZERO_DATA_WOFFSET                   0x0
+#define FUSE_PRIVATE_KEY2_NONZERO_0_PRIVATE_KEY2_NONZERO_DATA_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY2_NONZERO_0_PRIVATE_KEY2_NONZERO_DATA_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY2_NONZERO_0_PRIVATE_KEY2_NONZERO_DATA_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY2_NONZERO_0_PRIVATE_KEY2_NONZERO_DATA_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_PRIVATE_KEY3_NONZERO_0  
+#define FUSE_PRIVATE_KEY3_NONZERO_0                     _MK_ADDR_CONST(0x5c)
+#define FUSE_PRIVATE_KEY3_NONZERO_0_SECURE                      0x0
+#define FUSE_PRIVATE_KEY3_NONZERO_0_WORD_COUNT                  0x1
+#define FUSE_PRIVATE_KEY3_NONZERO_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY3_NONZERO_0_RESET_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY3_NONZERO_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY3_NONZERO_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY3_NONZERO_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_PRIVATE_KEY3_NONZERO_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY3_NONZERO_0_PRIVATE_KEY3_NONZERO_DATA_SHIFT                     _MK_SHIFT_CONST(0)
+#define FUSE_PRIVATE_KEY3_NONZERO_0_PRIVATE_KEY3_NONZERO_DATA_FIELD                     (_MK_MASK_CONST(0x1) << FUSE_PRIVATE_KEY3_NONZERO_0_PRIVATE_KEY3_NONZERO_DATA_SHIFT)
+#define FUSE_PRIVATE_KEY3_NONZERO_0_PRIVATE_KEY3_NONZERO_DATA_RANGE                     0:0
+#define FUSE_PRIVATE_KEY3_NONZERO_0_PRIVATE_KEY3_NONZERO_DATA_WOFFSET                   0x0
+#define FUSE_PRIVATE_KEY3_NONZERO_0_PRIVATE_KEY3_NONZERO_DATA_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY3_NONZERO_0_PRIVATE_KEY3_NONZERO_DATA_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY3_NONZERO_0_PRIVATE_KEY3_NONZERO_DATA_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY3_NONZERO_0_PRIVATE_KEY3_NONZERO_DATA_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_PRIVATE_KEY4_NONZERO_0  
+#define FUSE_PRIVATE_KEY4_NONZERO_0                     _MK_ADDR_CONST(0x60)
+#define FUSE_PRIVATE_KEY4_NONZERO_0_SECURE                      0x0
+#define FUSE_PRIVATE_KEY4_NONZERO_0_WORD_COUNT                  0x1
+#define FUSE_PRIVATE_KEY4_NONZERO_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY4_NONZERO_0_RESET_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY4_NONZERO_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY4_NONZERO_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY4_NONZERO_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_PRIVATE_KEY4_NONZERO_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY4_NONZERO_0_PRIVATE_KEY4_NONZERO_DATA_SHIFT                     _MK_SHIFT_CONST(0)
+#define FUSE_PRIVATE_KEY4_NONZERO_0_PRIVATE_KEY4_NONZERO_DATA_FIELD                     (_MK_MASK_CONST(0x1) << FUSE_PRIVATE_KEY4_NONZERO_0_PRIVATE_KEY4_NONZERO_DATA_SHIFT)
+#define FUSE_PRIVATE_KEY4_NONZERO_0_PRIVATE_KEY4_NONZERO_DATA_RANGE                     0:0
+#define FUSE_PRIVATE_KEY4_NONZERO_0_PRIVATE_KEY4_NONZERO_DATA_WOFFSET                   0x0
+#define FUSE_PRIVATE_KEY4_NONZERO_0_PRIVATE_KEY4_NONZERO_DATA_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY4_NONZERO_0_PRIVATE_KEY4_NONZERO_DATA_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY4_NONZERO_0_PRIVATE_KEY4_NONZERO_DATA_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY4_NONZERO_0_PRIVATE_KEY4_NONZERO_DATA_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Reserved address 100 [0x64] 
+
+// Reserved address 104 [0x68] 
+
+// Reserved address 108 [0x6c] 
+
+// Reserved address 112 [0x70] 
+
+// Reserved address 116 [0x74] 
+
+// Reserved address 120 [0x78] 
+
+// Reserved address 124 [0x7c] 
+
+// Reserved address 128 [0x80] 
+
+// Reserved address 132 [0x84] 
+
+// Reserved address 136 [0x88] 
+
+// Reserved address 140 [0x8c] 
+
+// Reserved address 144 [0x90] 
+
+// Reserved address 148 [0x94] 
+
+// Reserved address 152 [0x98] 
+
+// Reserved address 156 [0x9c] 
+
+// Reserved address 160 [0xa0] 
+
+// Reserved address 164 [0xa4] 
+
+// Reserved address 168 [0xa8] 
+
+// Reserved address 172 [0xac] 
+
+// Reserved address 176 [0xb0] 
+
+// Reserved address 180 [0xb4] 
+
+// Reserved address 184 [0xb8] 
+
+// Reserved address 188 [0xbc] 
+
+// Reserved address 192 [0xc0] 
+
+// Reserved address 196 [0xc4] 
+
+// Reserved address 200 [0xc8] 
+
+// Reserved address 204 [0xcc] 
+
+// Reserved address 208 [0xd0] 
+
+// Reserved address 212 [0xd4] 
+
+// Reserved address 216 [0xd8] 
+
+// Reserved address 220 [0xdc] 
+
+// Reserved address 224 [0xe0] 
+
+// Reserved address 228 [0xe4] 
+
+// Reserved address 232 [0xe8] 
+
+// Reserved address 236 [0xec] 
+
+// Reserved address 240 [0xf0] 
+
+// Reserved address 244 [0xf4] 
+
+// Reserved address 248 [0xf8] 
+
+// Reserved address 252 [0xfc] 
+
+// Register FUSE_PRODUCTION_MODE_0  
+#define FUSE_PRODUCTION_MODE_0                  _MK_ADDR_CONST(0x100)
+#define FUSE_PRODUCTION_MODE_0_SECURE                   0x0
+#define FUSE_PRODUCTION_MODE_0_WORD_COUNT                       0x1
+#define FUSE_PRODUCTION_MODE_0_RESET_VAL                        _MK_MASK_CONST(0x1)
+#define FUSE_PRODUCTION_MODE_0_RESET_MASK                       _MK_MASK_CONST(0x1)
+#define FUSE_PRODUCTION_MODE_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_PRODUCTION_MODE_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_PRODUCTION_MODE_0_READ_MASK                        _MK_MASK_CONST(0x1)
+#define FUSE_PRODUCTION_MODE_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
+#define FUSE_PRODUCTION_MODE_0_PRODUCTION_MODE_SHIFT                    _MK_SHIFT_CONST(0)
+#define FUSE_PRODUCTION_MODE_0_PRODUCTION_MODE_FIELD                    (_MK_MASK_CONST(0x1) << FUSE_PRODUCTION_MODE_0_PRODUCTION_MODE_SHIFT)
+#define FUSE_PRODUCTION_MODE_0_PRODUCTION_MODE_RANGE                    0:0
+#define FUSE_PRODUCTION_MODE_0_PRODUCTION_MODE_WOFFSET                  0x0
+#define FUSE_PRODUCTION_MODE_0_PRODUCTION_MODE_DEFAULT                  _MK_MASK_CONST(0x1)
+#define FUSE_PRODUCTION_MODE_0_PRODUCTION_MODE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FUSE_PRODUCTION_MODE_0_PRODUCTION_MODE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_PRODUCTION_MODE_0_PRODUCTION_MODE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_JTAG_SECUREID_VALID_0  
+#define FUSE_JTAG_SECUREID_VALID_0                      _MK_ADDR_CONST(0x104)
+#define FUSE_JTAG_SECUREID_VALID_0_SECURE                       0x0
+#define FUSE_JTAG_SECUREID_VALID_0_WORD_COUNT                   0x1
+#define FUSE_JTAG_SECUREID_VALID_0_RESET_VAL                    _MK_MASK_CONST(0x1)
+#define FUSE_JTAG_SECUREID_VALID_0_RESET_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_JTAG_SECUREID_VALID_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define FUSE_JTAG_SECUREID_VALID_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define FUSE_JTAG_SECUREID_VALID_0_READ_MASK                    _MK_MASK_CONST(0x1)
+#define FUSE_JTAG_SECUREID_VALID_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_JTAG_SECUREID_VALID_0_JTAG_SECUREID_VALID_SHIFT                    _MK_SHIFT_CONST(0)
+#define FUSE_JTAG_SECUREID_VALID_0_JTAG_SECUREID_VALID_FIELD                    (_MK_MASK_CONST(0x1) << FUSE_JTAG_SECUREID_VALID_0_JTAG_SECUREID_VALID_SHIFT)
+#define FUSE_JTAG_SECUREID_VALID_0_JTAG_SECUREID_VALID_RANGE                    0:0
+#define FUSE_JTAG_SECUREID_VALID_0_JTAG_SECUREID_VALID_WOFFSET                  0x0
+#define FUSE_JTAG_SECUREID_VALID_0_JTAG_SECUREID_VALID_DEFAULT                  _MK_MASK_CONST(0x1)
+#define FUSE_JTAG_SECUREID_VALID_0_JTAG_SECUREID_VALID_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FUSE_JTAG_SECUREID_VALID_0_JTAG_SECUREID_VALID_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_JTAG_SECUREID_VALID_0_JTAG_SECUREID_VALID_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_JTAG_SECUREID_0_0  
+#define FUSE_JTAG_SECUREID_0_0                  _MK_ADDR_CONST(0x108)
+#define FUSE_JTAG_SECUREID_0_0_SECURE                   0x0
+#define FUSE_JTAG_SECUREID_0_0_WORD_COUNT                       0x1
+#define FUSE_JTAG_SECUREID_0_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define FUSE_JTAG_SECUREID_0_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
+#define FUSE_JTAG_SECUREID_0_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_JTAG_SECUREID_0_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_JTAG_SECUREID_0_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define FUSE_JTAG_SECUREID_0_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+#define FUSE_JTAG_SECUREID_0_0_JTAG_SECUREID_0_SHIFT                    _MK_SHIFT_CONST(0)
+#define FUSE_JTAG_SECUREID_0_0_JTAG_SECUREID_0_FIELD                    (_MK_MASK_CONST(0xffffffff) << FUSE_JTAG_SECUREID_0_0_JTAG_SECUREID_0_SHIFT)
+#define FUSE_JTAG_SECUREID_0_0_JTAG_SECUREID_0_RANGE                    31:0
+#define FUSE_JTAG_SECUREID_0_0_JTAG_SECUREID_0_WOFFSET                  0x0
+#define FUSE_JTAG_SECUREID_0_0_JTAG_SECUREID_0_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_JTAG_SECUREID_0_0_JTAG_SECUREID_0_DEFAULT_MASK                     _MK_MASK_CONST(0xffffffff)
+#define FUSE_JTAG_SECUREID_0_0_JTAG_SECUREID_0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_JTAG_SECUREID_0_0_JTAG_SECUREID_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_JTAG_SECUREID_1_0  
+#define FUSE_JTAG_SECUREID_1_0                  _MK_ADDR_CONST(0x10c)
+#define FUSE_JTAG_SECUREID_1_0_SECURE                   0x0
+#define FUSE_JTAG_SECUREID_1_0_WORD_COUNT                       0x1
+#define FUSE_JTAG_SECUREID_1_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define FUSE_JTAG_SECUREID_1_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
+#define FUSE_JTAG_SECUREID_1_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_JTAG_SECUREID_1_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_JTAG_SECUREID_1_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define FUSE_JTAG_SECUREID_1_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+#define FUSE_JTAG_SECUREID_1_0_JTAG_SECUREID_1_SHIFT                    _MK_SHIFT_CONST(0)
+#define FUSE_JTAG_SECUREID_1_0_JTAG_SECUREID_1_FIELD                    (_MK_MASK_CONST(0xffffffff) << FUSE_JTAG_SECUREID_1_0_JTAG_SECUREID_1_SHIFT)
+#define FUSE_JTAG_SECUREID_1_0_JTAG_SECUREID_1_RANGE                    31:0
+#define FUSE_JTAG_SECUREID_1_0_JTAG_SECUREID_1_WOFFSET                  0x0
+#define FUSE_JTAG_SECUREID_1_0_JTAG_SECUREID_1_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_JTAG_SECUREID_1_0_JTAG_SECUREID_1_DEFAULT_MASK                     _MK_MASK_CONST(0xffffffff)
+#define FUSE_JTAG_SECUREID_1_0_JTAG_SECUREID_1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_JTAG_SECUREID_1_0_JTAG_SECUREID_1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SKU_INFO_0  
+#define FUSE_SKU_INFO_0                 _MK_ADDR_CONST(0x110)
+#define FUSE_SKU_INFO_0_SECURE                  0x0
+#define FUSE_SKU_INFO_0_WORD_COUNT                      0x1
+#define FUSE_SKU_INFO_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define FUSE_SKU_INFO_0_RESET_MASK                      _MK_MASK_CONST(0xff)
+#define FUSE_SKU_INFO_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define FUSE_SKU_INFO_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define FUSE_SKU_INFO_0_READ_MASK                       _MK_MASK_CONST(0xff)
+#define FUSE_SKU_INFO_0_WRITE_MASK                      _MK_MASK_CONST(0xff)
+#define FUSE_SKU_INFO_0_SKU_INFO_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_SKU_INFO_0_SKU_INFO_FIELD                  (_MK_MASK_CONST(0xff) << FUSE_SKU_INFO_0_SKU_INFO_SHIFT)
+#define FUSE_SKU_INFO_0_SKU_INFO_RANGE                  7:0
+#define FUSE_SKU_INFO_0_SKU_INFO_WOFFSET                        0x0
+#define FUSE_SKU_INFO_0_SKU_INFO_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_SKU_INFO_0_SKU_INFO_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
+#define FUSE_SKU_INFO_0_SKU_INFO_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_SKU_INFO_0_SKU_INFO_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_PROCESS_CALIB_0  
+#define FUSE_PROCESS_CALIB_0                    _MK_ADDR_CONST(0x114)
+#define FUSE_PROCESS_CALIB_0_SECURE                     0x0
+#define FUSE_PROCESS_CALIB_0_WORD_COUNT                         0x1
+#define FUSE_PROCESS_CALIB_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define FUSE_PROCESS_CALIB_0_RESET_MASK                         _MK_MASK_CONST(0x3)
+#define FUSE_PROCESS_CALIB_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define FUSE_PROCESS_CALIB_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define FUSE_PROCESS_CALIB_0_READ_MASK                  _MK_MASK_CONST(0x3)
+#define FUSE_PROCESS_CALIB_0_WRITE_MASK                         _MK_MASK_CONST(0x3)
+#define FUSE_PROCESS_CALIB_0_PROCESS_CALIB_SHIFT                        _MK_SHIFT_CONST(0)
+#define FUSE_PROCESS_CALIB_0_PROCESS_CALIB_FIELD                        (_MK_MASK_CONST(0x3) << FUSE_PROCESS_CALIB_0_PROCESS_CALIB_SHIFT)
+#define FUSE_PROCESS_CALIB_0_PROCESS_CALIB_RANGE                        1:0
+#define FUSE_PROCESS_CALIB_0_PROCESS_CALIB_WOFFSET                      0x0
+#define FUSE_PROCESS_CALIB_0_PROCESS_CALIB_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_PROCESS_CALIB_0_PROCESS_CALIB_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define FUSE_PROCESS_CALIB_0_PROCESS_CALIB_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_PROCESS_CALIB_0_PROCESS_CALIB_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_IO_CALIB_0  
+#define FUSE_IO_CALIB_0                 _MK_ADDR_CONST(0x118)
+#define FUSE_IO_CALIB_0_SECURE                  0x0
+#define FUSE_IO_CALIB_0_WORD_COUNT                      0x1
+#define FUSE_IO_CALIB_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define FUSE_IO_CALIB_0_RESET_MASK                      _MK_MASK_CONST(0x3ff)
+#define FUSE_IO_CALIB_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define FUSE_IO_CALIB_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define FUSE_IO_CALIB_0_READ_MASK                       _MK_MASK_CONST(0x3ff)
+#define FUSE_IO_CALIB_0_WRITE_MASK                      _MK_MASK_CONST(0x3ff)
+#define FUSE_IO_CALIB_0_IO_CALIB_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_IO_CALIB_0_IO_CALIB_FIELD                  (_MK_MASK_CONST(0x3ff) << FUSE_IO_CALIB_0_IO_CALIB_SHIFT)
+#define FUSE_IO_CALIB_0_IO_CALIB_RANGE                  9:0
+#define FUSE_IO_CALIB_0_IO_CALIB_WOFFSET                        0x0
+#define FUSE_IO_CALIB_0_IO_CALIB_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_IO_CALIB_0_IO_CALIB_DEFAULT_MASK                   _MK_MASK_CONST(0x3ff)
+#define FUSE_IO_CALIB_0_IO_CALIB_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_IO_CALIB_0_IO_CALIB_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_DAC_CRT_CALIB_0  
+#define FUSE_DAC_CRT_CALIB_0                    _MK_ADDR_CONST(0x11c)
+#define FUSE_DAC_CRT_CALIB_0_SECURE                     0x0
+#define FUSE_DAC_CRT_CALIB_0_WORD_COUNT                         0x1
+#define FUSE_DAC_CRT_CALIB_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define FUSE_DAC_CRT_CALIB_0_RESET_MASK                         _MK_MASK_CONST(0xff)
+#define FUSE_DAC_CRT_CALIB_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define FUSE_DAC_CRT_CALIB_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define FUSE_DAC_CRT_CALIB_0_READ_MASK                  _MK_MASK_CONST(0xff)
+#define FUSE_DAC_CRT_CALIB_0_WRITE_MASK                         _MK_MASK_CONST(0xff)
+#define FUSE_DAC_CRT_CALIB_0_DAC_CRT_CALIB_SHIFT                        _MK_SHIFT_CONST(0)
+#define FUSE_DAC_CRT_CALIB_0_DAC_CRT_CALIB_FIELD                        (_MK_MASK_CONST(0xff) << FUSE_DAC_CRT_CALIB_0_DAC_CRT_CALIB_SHIFT)
+#define FUSE_DAC_CRT_CALIB_0_DAC_CRT_CALIB_RANGE                        7:0
+#define FUSE_DAC_CRT_CALIB_0_DAC_CRT_CALIB_WOFFSET                      0x0
+#define FUSE_DAC_CRT_CALIB_0_DAC_CRT_CALIB_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_DAC_CRT_CALIB_0_DAC_CRT_CALIB_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
+#define FUSE_DAC_CRT_CALIB_0_DAC_CRT_CALIB_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_DAC_CRT_CALIB_0_DAC_CRT_CALIB_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_DAC_HDTV_CALIB_0  
+#define FUSE_DAC_HDTV_CALIB_0                   _MK_ADDR_CONST(0x120)
+#define FUSE_DAC_HDTV_CALIB_0_SECURE                    0x0
+#define FUSE_DAC_HDTV_CALIB_0_WORD_COUNT                        0x1
+#define FUSE_DAC_HDTV_CALIB_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define FUSE_DAC_HDTV_CALIB_0_RESET_MASK                        _MK_MASK_CONST(0xff)
+#define FUSE_DAC_HDTV_CALIB_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define FUSE_DAC_HDTV_CALIB_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define FUSE_DAC_HDTV_CALIB_0_READ_MASK                         _MK_MASK_CONST(0xff)
+#define FUSE_DAC_HDTV_CALIB_0_WRITE_MASK                        _MK_MASK_CONST(0xff)
+#define FUSE_DAC_HDTV_CALIB_0_DAC_HDTV_CALIB_SHIFT                      _MK_SHIFT_CONST(0)
+#define FUSE_DAC_HDTV_CALIB_0_DAC_HDTV_CALIB_FIELD                      (_MK_MASK_CONST(0xff) << FUSE_DAC_HDTV_CALIB_0_DAC_HDTV_CALIB_SHIFT)
+#define FUSE_DAC_HDTV_CALIB_0_DAC_HDTV_CALIB_RANGE                      7:0
+#define FUSE_DAC_HDTV_CALIB_0_DAC_HDTV_CALIB_WOFFSET                    0x0
+#define FUSE_DAC_HDTV_CALIB_0_DAC_HDTV_CALIB_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_DAC_HDTV_CALIB_0_DAC_HDTV_CALIB_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
+#define FUSE_DAC_HDTV_CALIB_0_DAC_HDTV_CALIB_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_DAC_HDTV_CALIB_0_DAC_HDTV_CALIB_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_DAC_SDTV_CALIB_0  
+#define FUSE_DAC_SDTV_CALIB_0                   _MK_ADDR_CONST(0x124)
+#define FUSE_DAC_SDTV_CALIB_0_SECURE                    0x0
+#define FUSE_DAC_SDTV_CALIB_0_WORD_COUNT                        0x1
+#define FUSE_DAC_SDTV_CALIB_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define FUSE_DAC_SDTV_CALIB_0_RESET_MASK                        _MK_MASK_CONST(0xff)
+#define FUSE_DAC_SDTV_CALIB_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define FUSE_DAC_SDTV_CALIB_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define FUSE_DAC_SDTV_CALIB_0_READ_MASK                         _MK_MASK_CONST(0xff)
+#define FUSE_DAC_SDTV_CALIB_0_WRITE_MASK                        _MK_MASK_CONST(0xff)
+#define FUSE_DAC_SDTV_CALIB_0_DAC_SDTV_CALIB_SHIFT                      _MK_SHIFT_CONST(0)
+#define FUSE_DAC_SDTV_CALIB_0_DAC_SDTV_CALIB_FIELD                      (_MK_MASK_CONST(0xff) << FUSE_DAC_SDTV_CALIB_0_DAC_SDTV_CALIB_SHIFT)
+#define FUSE_DAC_SDTV_CALIB_0_DAC_SDTV_CALIB_RANGE                      7:0
+#define FUSE_DAC_SDTV_CALIB_0_DAC_SDTV_CALIB_WOFFSET                    0x0
+#define FUSE_DAC_SDTV_CALIB_0_DAC_SDTV_CALIB_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_DAC_SDTV_CALIB_0_DAC_SDTV_CALIB_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
+#define FUSE_DAC_SDTV_CALIB_0_DAC_SDTV_CALIB_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_DAC_SDTV_CALIB_0_DAC_SDTV_CALIB_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Reserved address 296 [0x128] 
+
+// Reserved address 300 [0x12c] 
+
+// Reserved address 304 [0x130] 
+
+// Reserved address 308 [0x134] 
+
+// Reserved address 312 [0x138] 
+
+// Reserved address 316 [0x13c] 
+
+// Reserved address 320 [0x140] 
+
+// Reserved address 324 [0x144] 
+
+// Register FUSE_FA_0  
+#define FUSE_FA_0                       _MK_ADDR_CONST(0x148)
+#define FUSE_FA_0_SECURE                        0x0
+#define FUSE_FA_0_WORD_COUNT                    0x1
+#define FUSE_FA_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define FUSE_FA_0_RESET_MASK                    _MK_MASK_CONST(0x1)
+#define FUSE_FA_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define FUSE_FA_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define FUSE_FA_0_READ_MASK                     _MK_MASK_CONST(0x1)
+#define FUSE_FA_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
+#define FUSE_FA_0_FA_SHIFT                      _MK_SHIFT_CONST(0)
+#define FUSE_FA_0_FA_FIELD                      (_MK_MASK_CONST(0x1) << FUSE_FA_0_FA_SHIFT)
+#define FUSE_FA_0_FA_RANGE                      0:0
+#define FUSE_FA_0_FA_WOFFSET                    0x0
+#define FUSE_FA_0_FA_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FA_0_FA_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FUSE_FA_0_FA_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FA_0_FA_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_RESERVED_PRODUCTION_0  
+#define FUSE_RESERVED_PRODUCTION_0                      _MK_ADDR_CONST(0x14c)
+#define FUSE_RESERVED_PRODUCTION_0_SECURE                       0x0
+#define FUSE_RESERVED_PRODUCTION_0_WORD_COUNT                   0x1
+#define FUSE_RESERVED_PRODUCTION_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_PRODUCTION_0_RESET_MASK                   _MK_MASK_CONST(0xf)
+#define FUSE_RESERVED_PRODUCTION_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_PRODUCTION_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_PRODUCTION_0_READ_MASK                    _MK_MASK_CONST(0xf)
+#define FUSE_RESERVED_PRODUCTION_0_WRITE_MASK                   _MK_MASK_CONST(0xf)
+#define FUSE_RESERVED_PRODUCTION_0_RESERVED_PRODUCTION_SHIFT                    _MK_SHIFT_CONST(0)
+#define FUSE_RESERVED_PRODUCTION_0_RESERVED_PRODUCTION_FIELD                    (_MK_MASK_CONST(0xf) << FUSE_RESERVED_PRODUCTION_0_RESERVED_PRODUCTION_SHIFT)
+#define FUSE_RESERVED_PRODUCTION_0_RESERVED_PRODUCTION_RANGE                    3:0
+#define FUSE_RESERVED_PRODUCTION_0_RESERVED_PRODUCTION_WOFFSET                  0x0
+#define FUSE_RESERVED_PRODUCTION_0_RESERVED_PRODUCTION_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_PRODUCTION_0_RESERVED_PRODUCTION_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
+#define FUSE_RESERVED_PRODUCTION_0_RESERVED_PRODUCTION_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_PRODUCTION_0_RESERVED_PRODUCTION_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_HDMI_LANE0_CALIB_0  
+#define FUSE_HDMI_LANE0_CALIB_0                 _MK_ADDR_CONST(0x150)
+#define FUSE_HDMI_LANE0_CALIB_0_SECURE                  0x0
+#define FUSE_HDMI_LANE0_CALIB_0_WORD_COUNT                      0x1
+#define FUSE_HDMI_LANE0_CALIB_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define FUSE_HDMI_LANE0_CALIB_0_RESET_MASK                      _MK_MASK_CONST(0x3f)
+#define FUSE_HDMI_LANE0_CALIB_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define FUSE_HDMI_LANE0_CALIB_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define FUSE_HDMI_LANE0_CALIB_0_READ_MASK                       _MK_MASK_CONST(0x3f)
+#define FUSE_HDMI_LANE0_CALIB_0_WRITE_MASK                      _MK_MASK_CONST(0x3f)
+#define FUSE_HDMI_LANE0_CALIB_0_HDMI_LANE0_CALIB_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_HDMI_LANE0_CALIB_0_HDMI_LANE0_CALIB_FIELD                  (_MK_MASK_CONST(0x3f) << FUSE_HDMI_LANE0_CALIB_0_HDMI_LANE0_CALIB_SHIFT)
+#define FUSE_HDMI_LANE0_CALIB_0_HDMI_LANE0_CALIB_RANGE                  5:0
+#define FUSE_HDMI_LANE0_CALIB_0_HDMI_LANE0_CALIB_WOFFSET                        0x0
+#define FUSE_HDMI_LANE0_CALIB_0_HDMI_LANE0_CALIB_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_HDMI_LANE0_CALIB_0_HDMI_LANE0_CALIB_DEFAULT_MASK                   _MK_MASK_CONST(0x3f)
+#define FUSE_HDMI_LANE0_CALIB_0_HDMI_LANE0_CALIB_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_HDMI_LANE0_CALIB_0_HDMI_LANE0_CALIB_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_HDMI_LANE1_CALIB_0  
+#define FUSE_HDMI_LANE1_CALIB_0                 _MK_ADDR_CONST(0x154)
+#define FUSE_HDMI_LANE1_CALIB_0_SECURE                  0x0
+#define FUSE_HDMI_LANE1_CALIB_0_WORD_COUNT                      0x1
+#define FUSE_HDMI_LANE1_CALIB_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define FUSE_HDMI_LANE1_CALIB_0_RESET_MASK                      _MK_MASK_CONST(0x3f)
+#define FUSE_HDMI_LANE1_CALIB_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define FUSE_HDMI_LANE1_CALIB_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define FUSE_HDMI_LANE1_CALIB_0_READ_MASK                       _MK_MASK_CONST(0x3f)
+#define FUSE_HDMI_LANE1_CALIB_0_WRITE_MASK                      _MK_MASK_CONST(0x3f)
+#define FUSE_HDMI_LANE1_CALIB_0_HDMI_LANE1_CALIB_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_HDMI_LANE1_CALIB_0_HDMI_LANE1_CALIB_FIELD                  (_MK_MASK_CONST(0x3f) << FUSE_HDMI_LANE1_CALIB_0_HDMI_LANE1_CALIB_SHIFT)
+#define FUSE_HDMI_LANE1_CALIB_0_HDMI_LANE1_CALIB_RANGE                  5:0
+#define FUSE_HDMI_LANE1_CALIB_0_HDMI_LANE1_CALIB_WOFFSET                        0x0
+#define FUSE_HDMI_LANE1_CALIB_0_HDMI_LANE1_CALIB_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_HDMI_LANE1_CALIB_0_HDMI_LANE1_CALIB_DEFAULT_MASK                   _MK_MASK_CONST(0x3f)
+#define FUSE_HDMI_LANE1_CALIB_0_HDMI_LANE1_CALIB_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_HDMI_LANE1_CALIB_0_HDMI_LANE1_CALIB_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_HDMI_LANE2_CALIB_0  
+#define FUSE_HDMI_LANE2_CALIB_0                 _MK_ADDR_CONST(0x158)
+#define FUSE_HDMI_LANE2_CALIB_0_SECURE                  0x0
+#define FUSE_HDMI_LANE2_CALIB_0_WORD_COUNT                      0x1
+#define FUSE_HDMI_LANE2_CALIB_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define FUSE_HDMI_LANE2_CALIB_0_RESET_MASK                      _MK_MASK_CONST(0x3f)
+#define FUSE_HDMI_LANE2_CALIB_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define FUSE_HDMI_LANE2_CALIB_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define FUSE_HDMI_LANE2_CALIB_0_READ_MASK                       _MK_MASK_CONST(0x3f)
+#define FUSE_HDMI_LANE2_CALIB_0_WRITE_MASK                      _MK_MASK_CONST(0x3f)
+#define FUSE_HDMI_LANE2_CALIB_0_HDMI_LANE2_CALIB_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_HDMI_LANE2_CALIB_0_HDMI_LANE2_CALIB_FIELD                  (_MK_MASK_CONST(0x3f) << FUSE_HDMI_LANE2_CALIB_0_HDMI_LANE2_CALIB_SHIFT)
+#define FUSE_HDMI_LANE2_CALIB_0_HDMI_LANE2_CALIB_RANGE                  5:0
+#define FUSE_HDMI_LANE2_CALIB_0_HDMI_LANE2_CALIB_WOFFSET                        0x0
+#define FUSE_HDMI_LANE2_CALIB_0_HDMI_LANE2_CALIB_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_HDMI_LANE2_CALIB_0_HDMI_LANE2_CALIB_DEFAULT_MASK                   _MK_MASK_CONST(0x3f)
+#define FUSE_HDMI_LANE2_CALIB_0_HDMI_LANE2_CALIB_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_HDMI_LANE2_CALIB_0_HDMI_LANE2_CALIB_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_HDMI_LANE3_CALIB_0  
+#define FUSE_HDMI_LANE3_CALIB_0                 _MK_ADDR_CONST(0x15c)
+#define FUSE_HDMI_LANE3_CALIB_0_SECURE                  0x0
+#define FUSE_HDMI_LANE3_CALIB_0_WORD_COUNT                      0x1
+#define FUSE_HDMI_LANE3_CALIB_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define FUSE_HDMI_LANE3_CALIB_0_RESET_MASK                      _MK_MASK_CONST(0x3f)
+#define FUSE_HDMI_LANE3_CALIB_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define FUSE_HDMI_LANE3_CALIB_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define FUSE_HDMI_LANE3_CALIB_0_READ_MASK                       _MK_MASK_CONST(0x3f)
+#define FUSE_HDMI_LANE3_CALIB_0_WRITE_MASK                      _MK_MASK_CONST(0x3f)
+#define FUSE_HDMI_LANE3_CALIB_0_HDMI_LANE3_CALIB_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_HDMI_LANE3_CALIB_0_HDMI_LANE3_CALIB_FIELD                  (_MK_MASK_CONST(0x3f) << FUSE_HDMI_LANE3_CALIB_0_HDMI_LANE3_CALIB_SHIFT)
+#define FUSE_HDMI_LANE3_CALIB_0_HDMI_LANE3_CALIB_RANGE                  5:0
+#define FUSE_HDMI_LANE3_CALIB_0_HDMI_LANE3_CALIB_WOFFSET                        0x0
+#define FUSE_HDMI_LANE3_CALIB_0_HDMI_LANE3_CALIB_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_HDMI_LANE3_CALIB_0_HDMI_LANE3_CALIB_DEFAULT_MASK                   _MK_MASK_CONST(0x3f)
+#define FUSE_HDMI_LANE3_CALIB_0_HDMI_LANE3_CALIB_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_HDMI_LANE3_CALIB_0_HDMI_LANE3_CALIB_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Reserved address 352 [0x160] 
+
+// Reserved address 356 [0x164] 
+
+// Reserved address 360 [0x168] 
+
+// Reserved address 364 [0x16c] 
+
+// Reserved address 368 [0x170] 
+
+// Reserved address 372 [0x174] 
+
+// Reserved address 376 [0x178] 
+
+// Reserved address 380 [0x17c] 
+
+// Reserved address 384 [0x180] 
+
+// Reserved address 388 [0x184] 
+
+// Reserved address 392 [0x188] 
+
+// Reserved address 396 [0x18c] 
+
+// Reserved address 400 [0x190] 
+
+// Reserved address 404 [0x194] 
+
+// Reserved address 408 [0x198] 
+
+// Reserved address 412 [0x19c] 
+
+// Register FUSE_SECURITY_MODE_0  
+#define FUSE_SECURITY_MODE_0                    _MK_ADDR_CONST(0x1a0)
+#define FUSE_SECURITY_MODE_0_SECURE                     0x0
+#define FUSE_SECURITY_MODE_0_WORD_COUNT                         0x1
+#define FUSE_SECURITY_MODE_0_RESET_VAL                  _MK_MASK_CONST(0x1)
+#define FUSE_SECURITY_MODE_0_RESET_MASK                         _MK_MASK_CONST(0x1)
+#define FUSE_SECURITY_MODE_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define FUSE_SECURITY_MODE_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define FUSE_SECURITY_MODE_0_READ_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_SECURITY_MODE_0_WRITE_MASK                         _MK_MASK_CONST(0x1)
+#define FUSE_SECURITY_MODE_0_SECURITY_MODE_SHIFT                        _MK_SHIFT_CONST(0)
+#define FUSE_SECURITY_MODE_0_SECURITY_MODE_FIELD                        (_MK_MASK_CONST(0x1) << FUSE_SECURITY_MODE_0_SECURITY_MODE_SHIFT)
+#define FUSE_SECURITY_MODE_0_SECURITY_MODE_RANGE                        0:0
+#define FUSE_SECURITY_MODE_0_SECURITY_MODE_WOFFSET                      0x0
+#define FUSE_SECURITY_MODE_0_SECURITY_MODE_DEFAULT                      _MK_MASK_CONST(0x1)
+#define FUSE_SECURITY_MODE_0_SECURITY_MODE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define FUSE_SECURITY_MODE_0_SECURITY_MODE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_SECURITY_MODE_0_SECURITY_MODE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_PRIVATE_KEY0_0  
+#define FUSE_PRIVATE_KEY0_0                     _MK_ADDR_CONST(0x1a4)
+#define FUSE_PRIVATE_KEY0_0_SECURE                      0x0
+#define FUSE_PRIVATE_KEY0_0_WORD_COUNT                  0x1
+#define FUSE_PRIVATE_KEY0_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY0_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define FUSE_PRIVATE_KEY0_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY0_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY0_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FUSE_PRIVATE_KEY0_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+#define FUSE_PRIVATE_KEY0_0_PRIVATE_KEY0_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_PRIVATE_KEY0_0_PRIVATE_KEY0_FIELD                  (_MK_MASK_CONST(0xffffffff) << FUSE_PRIVATE_KEY0_0_PRIVATE_KEY0_SHIFT)
+#define FUSE_PRIVATE_KEY0_0_PRIVATE_KEY0_RANGE                  31:0
+#define FUSE_PRIVATE_KEY0_0_PRIVATE_KEY0_WOFFSET                        0x0
+#define FUSE_PRIVATE_KEY0_0_PRIVATE_KEY0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY0_0_PRIVATE_KEY0_DEFAULT_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FUSE_PRIVATE_KEY0_0_PRIVATE_KEY0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY0_0_PRIVATE_KEY0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_PRIVATE_KEY1_0  
+#define FUSE_PRIVATE_KEY1_0                     _MK_ADDR_CONST(0x1a8)
+#define FUSE_PRIVATE_KEY1_0_SECURE                      0x0
+#define FUSE_PRIVATE_KEY1_0_WORD_COUNT                  0x1
+#define FUSE_PRIVATE_KEY1_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY1_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define FUSE_PRIVATE_KEY1_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY1_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY1_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FUSE_PRIVATE_KEY1_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+#define FUSE_PRIVATE_KEY1_0_PRIVATE_KEY1_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_PRIVATE_KEY1_0_PRIVATE_KEY1_FIELD                  (_MK_MASK_CONST(0xffffffff) << FUSE_PRIVATE_KEY1_0_PRIVATE_KEY1_SHIFT)
+#define FUSE_PRIVATE_KEY1_0_PRIVATE_KEY1_RANGE                  31:0
+#define FUSE_PRIVATE_KEY1_0_PRIVATE_KEY1_WOFFSET                        0x0
+#define FUSE_PRIVATE_KEY1_0_PRIVATE_KEY1_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY1_0_PRIVATE_KEY1_DEFAULT_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FUSE_PRIVATE_KEY1_0_PRIVATE_KEY1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY1_0_PRIVATE_KEY1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_PRIVATE_KEY2_0  
+#define FUSE_PRIVATE_KEY2_0                     _MK_ADDR_CONST(0x1ac)
+#define FUSE_PRIVATE_KEY2_0_SECURE                      0x0
+#define FUSE_PRIVATE_KEY2_0_WORD_COUNT                  0x1
+#define FUSE_PRIVATE_KEY2_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY2_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define FUSE_PRIVATE_KEY2_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY2_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY2_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FUSE_PRIVATE_KEY2_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+#define FUSE_PRIVATE_KEY2_0_PRIVATE_KEY2_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_PRIVATE_KEY2_0_PRIVATE_KEY2_FIELD                  (_MK_MASK_CONST(0xffffffff) << FUSE_PRIVATE_KEY2_0_PRIVATE_KEY2_SHIFT)
+#define FUSE_PRIVATE_KEY2_0_PRIVATE_KEY2_RANGE                  31:0
+#define FUSE_PRIVATE_KEY2_0_PRIVATE_KEY2_WOFFSET                        0x0
+#define FUSE_PRIVATE_KEY2_0_PRIVATE_KEY2_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY2_0_PRIVATE_KEY2_DEFAULT_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FUSE_PRIVATE_KEY2_0_PRIVATE_KEY2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY2_0_PRIVATE_KEY2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_PRIVATE_KEY3_0  
+#define FUSE_PRIVATE_KEY3_0                     _MK_ADDR_CONST(0x1b0)
+#define FUSE_PRIVATE_KEY3_0_SECURE                      0x0
+#define FUSE_PRIVATE_KEY3_0_WORD_COUNT                  0x1
+#define FUSE_PRIVATE_KEY3_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY3_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define FUSE_PRIVATE_KEY3_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY3_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY3_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FUSE_PRIVATE_KEY3_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+#define FUSE_PRIVATE_KEY3_0_PRIVATE_KEY3_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_PRIVATE_KEY3_0_PRIVATE_KEY3_FIELD                  (_MK_MASK_CONST(0xffffffff) << FUSE_PRIVATE_KEY3_0_PRIVATE_KEY3_SHIFT)
+#define FUSE_PRIVATE_KEY3_0_PRIVATE_KEY3_RANGE                  31:0
+#define FUSE_PRIVATE_KEY3_0_PRIVATE_KEY3_WOFFSET                        0x0
+#define FUSE_PRIVATE_KEY3_0_PRIVATE_KEY3_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY3_0_PRIVATE_KEY3_DEFAULT_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FUSE_PRIVATE_KEY3_0_PRIVATE_KEY3_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY3_0_PRIVATE_KEY3_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_PRIVATE_KEY4_0  
+#define FUSE_PRIVATE_KEY4_0                     _MK_ADDR_CONST(0x1b4)
+#define FUSE_PRIVATE_KEY4_0_SECURE                      0x0
+#define FUSE_PRIVATE_KEY4_0_WORD_COUNT                  0x1
+#define FUSE_PRIVATE_KEY4_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY4_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define FUSE_PRIVATE_KEY4_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY4_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY4_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FUSE_PRIVATE_KEY4_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+#define FUSE_PRIVATE_KEY4_0_PRIVATE_KEY4_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_PRIVATE_KEY4_0_PRIVATE_KEY4_FIELD                  (_MK_MASK_CONST(0xffffffff) << FUSE_PRIVATE_KEY4_0_PRIVATE_KEY4_SHIFT)
+#define FUSE_PRIVATE_KEY4_0_PRIVATE_KEY4_RANGE                  31:0
+#define FUSE_PRIVATE_KEY4_0_PRIVATE_KEY4_WOFFSET                        0x0
+#define FUSE_PRIVATE_KEY4_0_PRIVATE_KEY4_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY4_0_PRIVATE_KEY4_DEFAULT_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FUSE_PRIVATE_KEY4_0_PRIVATE_KEY4_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY4_0_PRIVATE_KEY4_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_ARM_DEBUG_DIS_0  
+#define FUSE_ARM_DEBUG_DIS_0                    _MK_ADDR_CONST(0x1b8)
+#define FUSE_ARM_DEBUG_DIS_0_SECURE                     0x0
+#define FUSE_ARM_DEBUG_DIS_0_WORD_COUNT                         0x1
+#define FUSE_ARM_DEBUG_DIS_0_RESET_VAL                  _MK_MASK_CONST(0x1)
+#define FUSE_ARM_DEBUG_DIS_0_RESET_MASK                         _MK_MASK_CONST(0x1)
+#define FUSE_ARM_DEBUG_DIS_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define FUSE_ARM_DEBUG_DIS_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define FUSE_ARM_DEBUG_DIS_0_READ_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_ARM_DEBUG_DIS_0_WRITE_MASK                         _MK_MASK_CONST(0x1)
+#define FUSE_ARM_DEBUG_DIS_0_ARM_DEBUG_DIS_SHIFT                        _MK_SHIFT_CONST(0)
+#define FUSE_ARM_DEBUG_DIS_0_ARM_DEBUG_DIS_FIELD                        (_MK_MASK_CONST(0x1) << FUSE_ARM_DEBUG_DIS_0_ARM_DEBUG_DIS_SHIFT)
+#define FUSE_ARM_DEBUG_DIS_0_ARM_DEBUG_DIS_RANGE                        0:0
+#define FUSE_ARM_DEBUG_DIS_0_ARM_DEBUG_DIS_WOFFSET                      0x0
+#define FUSE_ARM_DEBUG_DIS_0_ARM_DEBUG_DIS_DEFAULT                      _MK_MASK_CONST(0x1)
+#define FUSE_ARM_DEBUG_DIS_0_ARM_DEBUG_DIS_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define FUSE_ARM_DEBUG_DIS_0_ARM_DEBUG_DIS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_ARM_DEBUG_DIS_0_ARM_DEBUG_DIS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_BOOT_DEVICE_INFO_0  
+#define FUSE_BOOT_DEVICE_INFO_0                 _MK_ADDR_CONST(0x1bc)
+#define FUSE_BOOT_DEVICE_INFO_0_SECURE                  0x0
+#define FUSE_BOOT_DEVICE_INFO_0_WORD_COUNT                      0x1
+#define FUSE_BOOT_DEVICE_INFO_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define FUSE_BOOT_DEVICE_INFO_0_RESET_MASK                      _MK_MASK_CONST(0xffff)
+#define FUSE_BOOT_DEVICE_INFO_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define FUSE_BOOT_DEVICE_INFO_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define FUSE_BOOT_DEVICE_INFO_0_READ_MASK                       _MK_MASK_CONST(0xffff)
+#define FUSE_BOOT_DEVICE_INFO_0_WRITE_MASK                      _MK_MASK_CONST(0xffff)
+#define FUSE_BOOT_DEVICE_INFO_0_BOOT_DEVICE_INFO_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_BOOT_DEVICE_INFO_0_BOOT_DEVICE_INFO_FIELD                  (_MK_MASK_CONST(0xffff) << FUSE_BOOT_DEVICE_INFO_0_BOOT_DEVICE_INFO_SHIFT)
+#define FUSE_BOOT_DEVICE_INFO_0_BOOT_DEVICE_INFO_RANGE                  15:0
+#define FUSE_BOOT_DEVICE_INFO_0_BOOT_DEVICE_INFO_WOFFSET                        0x0
+#define FUSE_BOOT_DEVICE_INFO_0_BOOT_DEVICE_INFO_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_BOOT_DEVICE_INFO_0_BOOT_DEVICE_INFO_DEFAULT_MASK                   _MK_MASK_CONST(0xffff)
+#define FUSE_BOOT_DEVICE_INFO_0_BOOT_DEVICE_INFO_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_BOOT_DEVICE_INFO_0_BOOT_DEVICE_INFO_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_RESERVED_SW_0  
+#define FUSE_RESERVED_SW_0                      _MK_ADDR_CONST(0x1c0)
+#define FUSE_RESERVED_SW_0_SECURE                       0x0
+#define FUSE_RESERVED_SW_0_WORD_COUNT                   0x1
+#define FUSE_RESERVED_SW_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_SW_0_RESET_MASK                   _MK_MASK_CONST(0xff)
+#define FUSE_RESERVED_SW_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_SW_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_SW_0_READ_MASK                    _MK_MASK_CONST(0xff)
+#define FUSE_RESERVED_SW_0_WRITE_MASK                   _MK_MASK_CONST(0xff)
+#define FUSE_RESERVED_SW_0_RESERVED_SW_SHIFT                    _MK_SHIFT_CONST(0)
+#define FUSE_RESERVED_SW_0_RESERVED_SW_FIELD                    (_MK_MASK_CONST(0xff) << FUSE_RESERVED_SW_0_RESERVED_SW_SHIFT)
+#define FUSE_RESERVED_SW_0_RESERVED_SW_RANGE                    7:0
+#define FUSE_RESERVED_SW_0_RESERVED_SW_WOFFSET                  0x0
+#define FUSE_RESERVED_SW_0_RESERVED_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_SW_0_RESERVED_SW_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
+#define FUSE_RESERVED_SW_0_RESERVED_SW_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_SW_0_RESERVED_SW_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_ARM_DEBUG_CONTROL_0  
+#define FUSE_ARM_DEBUG_CONTROL_0                        _MK_ADDR_CONST(0x1c4)
+#define FUSE_ARM_DEBUG_CONTROL_0_SECURE                         0x0
+#define FUSE_ARM_DEBUG_CONTROL_0_WORD_COUNT                     0x1
+#define FUSE_ARM_DEBUG_CONTROL_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_ARM_DEBUG_CONTROL_0_RESET_MASK                     _MK_MASK_CONST(0xf)
+#define FUSE_ARM_DEBUG_CONTROL_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define FUSE_ARM_DEBUG_CONTROL_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define FUSE_ARM_DEBUG_CONTROL_0_READ_MASK                      _MK_MASK_CONST(0xf)
+#define FUSE_ARM_DEBUG_CONTROL_0_WRITE_MASK                     _MK_MASK_CONST(0xf)
+#define FUSE_ARM_DEBUG_CONTROL_0_ARM_DEBUG_CONTROL_SHIFT                        _MK_SHIFT_CONST(0)
+#define FUSE_ARM_DEBUG_CONTROL_0_ARM_DEBUG_CONTROL_FIELD                        (_MK_MASK_CONST(0xf) << FUSE_ARM_DEBUG_CONTROL_0_ARM_DEBUG_CONTROL_SHIFT)
+#define FUSE_ARM_DEBUG_CONTROL_0_ARM_DEBUG_CONTROL_RANGE                        3:0
+#define FUSE_ARM_DEBUG_CONTROL_0_ARM_DEBUG_CONTROL_WOFFSET                      0x0
+#define FUSE_ARM_DEBUG_CONTROL_0_ARM_DEBUG_CONTROL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_ARM_DEBUG_CONTROL_0_ARM_DEBUG_CONTROL_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define FUSE_ARM_DEBUG_CONTROL_0_ARM_DEBUG_CONTROL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_ARM_DEBUG_CONTROL_0_ARM_DEBUG_CONTROL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_RESERVED_ODM0_0  
+#define FUSE_RESERVED_ODM0_0                    _MK_ADDR_CONST(0x1c8)
+#define FUSE_RESERVED_ODM0_0_SECURE                     0x0
+#define FUSE_RESERVED_ODM0_0_WORD_COUNT                         0x1
+#define FUSE_RESERVED_ODM0_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_ODM0_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
+#define FUSE_RESERVED_ODM0_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_ODM0_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_ODM0_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define FUSE_RESERVED_ODM0_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+#define FUSE_RESERVED_ODM0_0_RESERVED_ODM0_SHIFT                        _MK_SHIFT_CONST(0)
+#define FUSE_RESERVED_ODM0_0_RESERVED_ODM0_FIELD                        (_MK_MASK_CONST(0xffffffff) << FUSE_RESERVED_ODM0_0_RESERVED_ODM0_SHIFT)
+#define FUSE_RESERVED_ODM0_0_RESERVED_ODM0_RANGE                        31:0
+#define FUSE_RESERVED_ODM0_0_RESERVED_ODM0_WOFFSET                      0x0
+#define FUSE_RESERVED_ODM0_0_RESERVED_ODM0_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_ODM0_0_RESERVED_ODM0_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
+#define FUSE_RESERVED_ODM0_0_RESERVED_ODM0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_ODM0_0_RESERVED_ODM0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_RESERVED_ODM1_0  
+#define FUSE_RESERVED_ODM1_0                    _MK_ADDR_CONST(0x1cc)
+#define FUSE_RESERVED_ODM1_0_SECURE                     0x0
+#define FUSE_RESERVED_ODM1_0_WORD_COUNT                         0x1
+#define FUSE_RESERVED_ODM1_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_ODM1_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
+#define FUSE_RESERVED_ODM1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_ODM1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_ODM1_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define FUSE_RESERVED_ODM1_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+#define FUSE_RESERVED_ODM1_0_RESERVED_ODM1_SHIFT                        _MK_SHIFT_CONST(0)
+#define FUSE_RESERVED_ODM1_0_RESERVED_ODM1_FIELD                        (_MK_MASK_CONST(0xffffffff) << FUSE_RESERVED_ODM1_0_RESERVED_ODM1_SHIFT)
+#define FUSE_RESERVED_ODM1_0_RESERVED_ODM1_RANGE                        31:0
+#define FUSE_RESERVED_ODM1_0_RESERVED_ODM1_WOFFSET                      0x0
+#define FUSE_RESERVED_ODM1_0_RESERVED_ODM1_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_ODM1_0_RESERVED_ODM1_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
+#define FUSE_RESERVED_ODM1_0_RESERVED_ODM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_ODM1_0_RESERVED_ODM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_RESERVED_ODM2_0  
+#define FUSE_RESERVED_ODM2_0                    _MK_ADDR_CONST(0x1d0)
+#define FUSE_RESERVED_ODM2_0_SECURE                     0x0
+#define FUSE_RESERVED_ODM2_0_WORD_COUNT                         0x1
+#define FUSE_RESERVED_ODM2_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_ODM2_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
+#define FUSE_RESERVED_ODM2_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_ODM2_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_ODM2_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define FUSE_RESERVED_ODM2_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+#define FUSE_RESERVED_ODM2_0_RESERVED_ODM2_SHIFT                        _MK_SHIFT_CONST(0)
+#define FUSE_RESERVED_ODM2_0_RESERVED_ODM2_FIELD                        (_MK_MASK_CONST(0xffffffff) << FUSE_RESERVED_ODM2_0_RESERVED_ODM2_SHIFT)
+#define FUSE_RESERVED_ODM2_0_RESERVED_ODM2_RANGE                        31:0
+#define FUSE_RESERVED_ODM2_0_RESERVED_ODM2_WOFFSET                      0x0
+#define FUSE_RESERVED_ODM2_0_RESERVED_ODM2_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_ODM2_0_RESERVED_ODM2_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
+#define FUSE_RESERVED_ODM2_0_RESERVED_ODM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_ODM2_0_RESERVED_ODM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_RESERVED_ODM3_0  
+#define FUSE_RESERVED_ODM3_0                    _MK_ADDR_CONST(0x1d4)
+#define FUSE_RESERVED_ODM3_0_SECURE                     0x0
+#define FUSE_RESERVED_ODM3_0_WORD_COUNT                         0x1
+#define FUSE_RESERVED_ODM3_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_ODM3_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
+#define FUSE_RESERVED_ODM3_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_ODM3_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_ODM3_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define FUSE_RESERVED_ODM3_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+#define FUSE_RESERVED_ODM3_0_RESERVED_ODM3_SHIFT                        _MK_SHIFT_CONST(0)
+#define FUSE_RESERVED_ODM3_0_RESERVED_ODM3_FIELD                        (_MK_MASK_CONST(0xffffffff) << FUSE_RESERVED_ODM3_0_RESERVED_ODM3_SHIFT)
+#define FUSE_RESERVED_ODM3_0_RESERVED_ODM3_RANGE                        31:0
+#define FUSE_RESERVED_ODM3_0_RESERVED_ODM3_WOFFSET                      0x0
+#define FUSE_RESERVED_ODM3_0_RESERVED_ODM3_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_ODM3_0_RESERVED_ODM3_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
+#define FUSE_RESERVED_ODM3_0_RESERVED_ODM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_ODM3_0_RESERVED_ODM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_RESERVED_ODM4_0  
+#define FUSE_RESERVED_ODM4_0                    _MK_ADDR_CONST(0x1d8)
+#define FUSE_RESERVED_ODM4_0_SECURE                     0x0
+#define FUSE_RESERVED_ODM4_0_WORD_COUNT                         0x1
+#define FUSE_RESERVED_ODM4_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_ODM4_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
+#define FUSE_RESERVED_ODM4_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_ODM4_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_ODM4_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define FUSE_RESERVED_ODM4_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+#define FUSE_RESERVED_ODM4_0_RESERVED_ODM4_SHIFT                        _MK_SHIFT_CONST(0)
+#define FUSE_RESERVED_ODM4_0_RESERVED_ODM4_FIELD                        (_MK_MASK_CONST(0xffffffff) << FUSE_RESERVED_ODM4_0_RESERVED_ODM4_SHIFT)
+#define FUSE_RESERVED_ODM4_0_RESERVED_ODM4_RANGE                        31:0
+#define FUSE_RESERVED_ODM4_0_RESERVED_ODM4_WOFFSET                      0x0
+#define FUSE_RESERVED_ODM4_0_RESERVED_ODM4_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_ODM4_0_RESERVED_ODM4_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
+#define FUSE_RESERVED_ODM4_0_RESERVED_ODM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_ODM4_0_RESERVED_ODM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_RESERVED_ODM5_0  
+#define FUSE_RESERVED_ODM5_0                    _MK_ADDR_CONST(0x1dc)
+#define FUSE_RESERVED_ODM5_0_SECURE                     0x0
+#define FUSE_RESERVED_ODM5_0_WORD_COUNT                         0x1
+#define FUSE_RESERVED_ODM5_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_ODM5_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
+#define FUSE_RESERVED_ODM5_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_ODM5_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_ODM5_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define FUSE_RESERVED_ODM5_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+#define FUSE_RESERVED_ODM5_0_RESERVED_ODM5_SHIFT                        _MK_SHIFT_CONST(0)
+#define FUSE_RESERVED_ODM5_0_RESERVED_ODM5_FIELD                        (_MK_MASK_CONST(0xffffffff) << FUSE_RESERVED_ODM5_0_RESERVED_ODM5_SHIFT)
+#define FUSE_RESERVED_ODM5_0_RESERVED_ODM5_RANGE                        31:0
+#define FUSE_RESERVED_ODM5_0_RESERVED_ODM5_WOFFSET                      0x0
+#define FUSE_RESERVED_ODM5_0_RESERVED_ODM5_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_ODM5_0_RESERVED_ODM5_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
+#define FUSE_RESERVED_ODM5_0_RESERVED_ODM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_ODM5_0_RESERVED_ODM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_RESERVED_ODM6_0  
+#define FUSE_RESERVED_ODM6_0                    _MK_ADDR_CONST(0x1e0)
+#define FUSE_RESERVED_ODM6_0_SECURE                     0x0
+#define FUSE_RESERVED_ODM6_0_WORD_COUNT                         0x1
+#define FUSE_RESERVED_ODM6_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_ODM6_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
+#define FUSE_RESERVED_ODM6_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_ODM6_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_ODM6_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define FUSE_RESERVED_ODM6_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+#define FUSE_RESERVED_ODM6_0_RESERVED_ODM6_SHIFT                        _MK_SHIFT_CONST(0)
+#define FUSE_RESERVED_ODM6_0_RESERVED_ODM6_FIELD                        (_MK_MASK_CONST(0xffffffff) << FUSE_RESERVED_ODM6_0_RESERVED_ODM6_SHIFT)
+#define FUSE_RESERVED_ODM6_0_RESERVED_ODM6_RANGE                        31:0
+#define FUSE_RESERVED_ODM6_0_RESERVED_ODM6_WOFFSET                      0x0
+#define FUSE_RESERVED_ODM6_0_RESERVED_ODM6_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_ODM6_0_RESERVED_ODM6_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
+#define FUSE_RESERVED_ODM6_0_RESERVED_ODM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_ODM6_0_RESERVED_ODM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_RESERVED_ODM7_0  
+#define FUSE_RESERVED_ODM7_0                    _MK_ADDR_CONST(0x1e4)
+#define FUSE_RESERVED_ODM7_0_SECURE                     0x0
+#define FUSE_RESERVED_ODM7_0_WORD_COUNT                         0x1
+#define FUSE_RESERVED_ODM7_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_ODM7_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
+#define FUSE_RESERVED_ODM7_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_ODM7_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_ODM7_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define FUSE_RESERVED_ODM7_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+#define FUSE_RESERVED_ODM7_0_RESERVED_ODM7_SHIFT                        _MK_SHIFT_CONST(0)
+#define FUSE_RESERVED_ODM7_0_RESERVED_ODM7_FIELD                        (_MK_MASK_CONST(0xffffffff) << FUSE_RESERVED_ODM7_0_RESERVED_ODM7_SHIFT)
+#define FUSE_RESERVED_ODM7_0_RESERVED_ODM7_RANGE                        31:0
+#define FUSE_RESERVED_ODM7_0_RESERVED_ODM7_WOFFSET                      0x0
+#define FUSE_RESERVED_ODM7_0_RESERVED_ODM7_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_ODM7_0_RESERVED_ODM7_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
+#define FUSE_RESERVED_ODM7_0_RESERVED_ODM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_ODM7_0_RESERVED_ODM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_OBS_DIS_0  
+#define FUSE_OBS_DIS_0                  _MK_ADDR_CONST(0x1e8)
+#define FUSE_OBS_DIS_0_SECURE                   0x0
+#define FUSE_OBS_DIS_0_WORD_COUNT                       0x1
+#define FUSE_OBS_DIS_0_RESET_VAL                        _MK_MASK_CONST(0x1)
+#define FUSE_OBS_DIS_0_RESET_MASK                       _MK_MASK_CONST(0x1)
+#define FUSE_OBS_DIS_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_OBS_DIS_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_OBS_DIS_0_READ_MASK                        _MK_MASK_CONST(0x1)
+#define FUSE_OBS_DIS_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
+#define FUSE_OBS_DIS_0_OBS_DIS_SHIFT                    _MK_SHIFT_CONST(0)
+#define FUSE_OBS_DIS_0_OBS_DIS_FIELD                    (_MK_MASK_CONST(0x1) << FUSE_OBS_DIS_0_OBS_DIS_SHIFT)
+#define FUSE_OBS_DIS_0_OBS_DIS_RANGE                    0:0
+#define FUSE_OBS_DIS_0_OBS_DIS_WOFFSET                  0x0
+#define FUSE_OBS_DIS_0_OBS_DIS_DEFAULT                  _MK_MASK_CONST(0x1)
+#define FUSE_OBS_DIS_0_OBS_DIS_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FUSE_OBS_DIS_0_OBS_DIS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_OBS_DIS_0_OBS_DIS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_NOR_INFO_0  
+#define FUSE_NOR_INFO_0                 _MK_ADDR_CONST(0x1ec)
+#define FUSE_NOR_INFO_0_SECURE                  0x0
+#define FUSE_NOR_INFO_0_WORD_COUNT                      0x1
+#define FUSE_NOR_INFO_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define FUSE_NOR_INFO_0_RESET_MASK                      _MK_MASK_CONST(0x3)
+#define FUSE_NOR_INFO_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define FUSE_NOR_INFO_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define FUSE_NOR_INFO_0_READ_MASK                       _MK_MASK_CONST(0x3)
+#define FUSE_NOR_INFO_0_WRITE_MASK                      _MK_MASK_CONST(0x3)
+#define FUSE_NOR_INFO_0_NOR_INFO_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_NOR_INFO_0_NOR_INFO_FIELD                  (_MK_MASK_CONST(0x3) << FUSE_NOR_INFO_0_NOR_INFO_SHIFT)
+#define FUSE_NOR_INFO_0_NOR_INFO_RANGE                  1:0
+#define FUSE_NOR_INFO_0_NOR_INFO_WOFFSET                        0x0
+#define FUSE_NOR_INFO_0_NOR_INFO_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_NOR_INFO_0_NOR_INFO_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define FUSE_NOR_INFO_0_NOR_INFO_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_NOR_INFO_0_NOR_INFO_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_USB_CALIB_0  
+#define FUSE_USB_CALIB_0                        _MK_ADDR_CONST(0x1f0)
+#define FUSE_USB_CALIB_0_SECURE                         0x0
+#define FUSE_USB_CALIB_0_WORD_COUNT                     0x1
+#define FUSE_USB_CALIB_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_USB_CALIB_0_RESET_MASK                     _MK_MASK_CONST(0x7f)
+#define FUSE_USB_CALIB_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define FUSE_USB_CALIB_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define FUSE_USB_CALIB_0_READ_MASK                      _MK_MASK_CONST(0x7f)
+#define FUSE_USB_CALIB_0_WRITE_MASK                     _MK_MASK_CONST(0x7f)
+#define FUSE_USB_CALIB_0_USB_CALIB_SHIFT                        _MK_SHIFT_CONST(0)
+#define FUSE_USB_CALIB_0_USB_CALIB_FIELD                        (_MK_MASK_CONST(0x7f) << FUSE_USB_CALIB_0_USB_CALIB_SHIFT)
+#define FUSE_USB_CALIB_0_USB_CALIB_RANGE                        6:0
+#define FUSE_USB_CALIB_0_USB_CALIB_WOFFSET                      0x0
+#define FUSE_USB_CALIB_0_USB_CALIB_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_USB_CALIB_0_USB_CALIB_DEFAULT_MASK                 _MK_MASK_CONST(0x7f)
+#define FUSE_USB_CALIB_0_USB_CALIB_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_USB_CALIB_0_USB_CALIB_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Reserved address 500 [0x1f4] 
+
+// Register FUSE_KFUSE_PRIVKEY_CTRL_0  
+#define FUSE_KFUSE_PRIVKEY_CTRL_0                       _MK_ADDR_CONST(0x1f8)
+#define FUSE_KFUSE_PRIVKEY_CTRL_0_SECURE                        0x0
+#define FUSE_KFUSE_PRIVKEY_CTRL_0_WORD_COUNT                    0x1
+#define FUSE_KFUSE_PRIVKEY_CTRL_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define FUSE_KFUSE_PRIVKEY_CTRL_0_RESET_MASK                    _MK_MASK_CONST(0x3)
+#define FUSE_KFUSE_PRIVKEY_CTRL_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define FUSE_KFUSE_PRIVKEY_CTRL_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define FUSE_KFUSE_PRIVKEY_CTRL_0_READ_MASK                     _MK_MASK_CONST(0x3)
+#define FUSE_KFUSE_PRIVKEY_CTRL_0_WRITE_MASK                    _MK_MASK_CONST(0x3)
+#define FUSE_KFUSE_PRIVKEY_CTRL_0_KFUSE_PRIVKEY_CTRL_SHIFT                      _MK_SHIFT_CONST(0)
+#define FUSE_KFUSE_PRIVKEY_CTRL_0_KFUSE_PRIVKEY_CTRL_FIELD                      (_MK_MASK_CONST(0x3) << FUSE_KFUSE_PRIVKEY_CTRL_0_KFUSE_PRIVKEY_CTRL_SHIFT)
+#define FUSE_KFUSE_PRIVKEY_CTRL_0_KFUSE_PRIVKEY_CTRL_RANGE                      1:0
+#define FUSE_KFUSE_PRIVKEY_CTRL_0_KFUSE_PRIVKEY_CTRL_WOFFSET                    0x0
+#define FUSE_KFUSE_PRIVKEY_CTRL_0_KFUSE_PRIVKEY_CTRL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_KFUSE_PRIVKEY_CTRL_0_KFUSE_PRIVKEY_CTRL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define FUSE_KFUSE_PRIVKEY_CTRL_0_KFUSE_PRIVKEY_CTRL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_KFUSE_PRIVKEY_CTRL_0_KFUSE_PRIVKEY_CTRL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_PACKAGE_INFO_0  
+#define FUSE_PACKAGE_INFO_0                     _MK_ADDR_CONST(0x1fc)
+#define FUSE_PACKAGE_INFO_0_SECURE                      0x0
+#define FUSE_PACKAGE_INFO_0_WORD_COUNT                  0x1
+#define FUSE_PACKAGE_INFO_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_PACKAGE_INFO_0_RESET_MASK                  _MK_MASK_CONST(0x3)
+#define FUSE_PACKAGE_INFO_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_PACKAGE_INFO_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_PACKAGE_INFO_0_READ_MASK                   _MK_MASK_CONST(0x3)
+#define FUSE_PACKAGE_INFO_0_WRITE_MASK                  _MK_MASK_CONST(0x3)
+#define FUSE_PACKAGE_INFO_0_PACKAGE_INFO_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_PACKAGE_INFO_0_PACKAGE_INFO_FIELD                  (_MK_MASK_CONST(0x3) << FUSE_PACKAGE_INFO_0_PACKAGE_INFO_SHIFT)
+#define FUSE_PACKAGE_INFO_0_PACKAGE_INFO_RANGE                  1:0
+#define FUSE_PACKAGE_INFO_0_PACKAGE_INFO_WOFFSET                        0x0
+#define FUSE_PACKAGE_INFO_0_PACKAGE_INFO_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_PACKAGE_INFO_0_PACKAGE_INFO_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define FUSE_PACKAGE_INFO_0_PACKAGE_INFO_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_PACKAGE_INFO_0_PACKAGE_INFO_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_0_0  
+#define FUSE_SPARE_BIT_0_0                      _MK_ADDR_CONST(0x200)
+#define FUSE_SPARE_BIT_0_0_SECURE                       0x0
+#define FUSE_SPARE_BIT_0_0_WORD_COUNT                   0x1
+#define FUSE_SPARE_BIT_0_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_0_0_RESET_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_0_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_0_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_0_0_READ_MASK                    _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_0_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_0_0_SPARE_BIT_0_SHIFT                    _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_0_0_SPARE_BIT_0_FIELD                    (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_0_0_SPARE_BIT_0_SHIFT)
+#define FUSE_SPARE_BIT_0_0_SPARE_BIT_0_RANGE                    0:0
+#define FUSE_SPARE_BIT_0_0_SPARE_BIT_0_WOFFSET                  0x0
+#define FUSE_SPARE_BIT_0_0_SPARE_BIT_0_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_0_0_SPARE_BIT_0_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_0_0_SPARE_BIT_0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_0_0_SPARE_BIT_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_1_0  
+#define FUSE_SPARE_BIT_1_0                      _MK_ADDR_CONST(0x204)
+#define FUSE_SPARE_BIT_1_0_SECURE                       0x0
+#define FUSE_SPARE_BIT_1_0_WORD_COUNT                   0x1
+#define FUSE_SPARE_BIT_1_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_1_0_RESET_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_1_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_1_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_1_0_READ_MASK                    _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_1_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_1_0_SPARE_BIT_1_SHIFT                    _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_1_0_SPARE_BIT_1_FIELD                    (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_1_0_SPARE_BIT_1_SHIFT)
+#define FUSE_SPARE_BIT_1_0_SPARE_BIT_1_RANGE                    0:0
+#define FUSE_SPARE_BIT_1_0_SPARE_BIT_1_WOFFSET                  0x0
+#define FUSE_SPARE_BIT_1_0_SPARE_BIT_1_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_1_0_SPARE_BIT_1_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_1_0_SPARE_BIT_1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_1_0_SPARE_BIT_1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_2_0  
+#define FUSE_SPARE_BIT_2_0                      _MK_ADDR_CONST(0x208)
+#define FUSE_SPARE_BIT_2_0_SECURE                       0x0
+#define FUSE_SPARE_BIT_2_0_WORD_COUNT                   0x1
+#define FUSE_SPARE_BIT_2_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_2_0_RESET_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_2_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_2_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_2_0_READ_MASK                    _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_2_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_2_0_SPARE_BIT_2_SHIFT                    _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_2_0_SPARE_BIT_2_FIELD                    (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_2_0_SPARE_BIT_2_SHIFT)
+#define FUSE_SPARE_BIT_2_0_SPARE_BIT_2_RANGE                    0:0
+#define FUSE_SPARE_BIT_2_0_SPARE_BIT_2_WOFFSET                  0x0
+#define FUSE_SPARE_BIT_2_0_SPARE_BIT_2_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_2_0_SPARE_BIT_2_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_2_0_SPARE_BIT_2_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_2_0_SPARE_BIT_2_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_3_0  
+#define FUSE_SPARE_BIT_3_0                      _MK_ADDR_CONST(0x20c)
+#define FUSE_SPARE_BIT_3_0_SECURE                       0x0
+#define FUSE_SPARE_BIT_3_0_WORD_COUNT                   0x1
+#define FUSE_SPARE_BIT_3_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_3_0_RESET_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_3_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_3_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_3_0_READ_MASK                    _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_3_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_3_0_SPARE_BIT_3_SHIFT                    _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_3_0_SPARE_BIT_3_FIELD                    (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_3_0_SPARE_BIT_3_SHIFT)
+#define FUSE_SPARE_BIT_3_0_SPARE_BIT_3_RANGE                    0:0
+#define FUSE_SPARE_BIT_3_0_SPARE_BIT_3_WOFFSET                  0x0
+#define FUSE_SPARE_BIT_3_0_SPARE_BIT_3_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_3_0_SPARE_BIT_3_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_3_0_SPARE_BIT_3_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_3_0_SPARE_BIT_3_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_4_0  
+#define FUSE_SPARE_BIT_4_0                      _MK_ADDR_CONST(0x210)
+#define FUSE_SPARE_BIT_4_0_SECURE                       0x0
+#define FUSE_SPARE_BIT_4_0_WORD_COUNT                   0x1
+#define FUSE_SPARE_BIT_4_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_4_0_RESET_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_4_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_4_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_4_0_READ_MASK                    _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_4_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_4_0_SPARE_BIT_4_SHIFT                    _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_4_0_SPARE_BIT_4_FIELD                    (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_4_0_SPARE_BIT_4_SHIFT)
+#define FUSE_SPARE_BIT_4_0_SPARE_BIT_4_RANGE                    0:0
+#define FUSE_SPARE_BIT_4_0_SPARE_BIT_4_WOFFSET                  0x0
+#define FUSE_SPARE_BIT_4_0_SPARE_BIT_4_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_4_0_SPARE_BIT_4_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_4_0_SPARE_BIT_4_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_4_0_SPARE_BIT_4_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_5_0  
+#define FUSE_SPARE_BIT_5_0                      _MK_ADDR_CONST(0x214)
+#define FUSE_SPARE_BIT_5_0_SECURE                       0x0
+#define FUSE_SPARE_BIT_5_0_WORD_COUNT                   0x1
+#define FUSE_SPARE_BIT_5_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_5_0_RESET_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_5_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_5_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_5_0_READ_MASK                    _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_5_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_5_0_SPARE_BIT_5_SHIFT                    _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_5_0_SPARE_BIT_5_FIELD                    (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_5_0_SPARE_BIT_5_SHIFT)
+#define FUSE_SPARE_BIT_5_0_SPARE_BIT_5_RANGE                    0:0
+#define FUSE_SPARE_BIT_5_0_SPARE_BIT_5_WOFFSET                  0x0
+#define FUSE_SPARE_BIT_5_0_SPARE_BIT_5_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_5_0_SPARE_BIT_5_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_5_0_SPARE_BIT_5_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_5_0_SPARE_BIT_5_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_6_0  
+#define FUSE_SPARE_BIT_6_0                      _MK_ADDR_CONST(0x218)
+#define FUSE_SPARE_BIT_6_0_SECURE                       0x0
+#define FUSE_SPARE_BIT_6_0_WORD_COUNT                   0x1
+#define FUSE_SPARE_BIT_6_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_6_0_RESET_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_6_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_6_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_6_0_READ_MASK                    _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_6_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_6_0_SPARE_BIT_6_SHIFT                    _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_6_0_SPARE_BIT_6_FIELD                    (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_6_0_SPARE_BIT_6_SHIFT)
+#define FUSE_SPARE_BIT_6_0_SPARE_BIT_6_RANGE                    0:0
+#define FUSE_SPARE_BIT_6_0_SPARE_BIT_6_WOFFSET                  0x0
+#define FUSE_SPARE_BIT_6_0_SPARE_BIT_6_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_6_0_SPARE_BIT_6_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_6_0_SPARE_BIT_6_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_6_0_SPARE_BIT_6_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_7_0  
+#define FUSE_SPARE_BIT_7_0                      _MK_ADDR_CONST(0x21c)
+#define FUSE_SPARE_BIT_7_0_SECURE                       0x0
+#define FUSE_SPARE_BIT_7_0_WORD_COUNT                   0x1
+#define FUSE_SPARE_BIT_7_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_7_0_RESET_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_7_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_7_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_7_0_READ_MASK                    _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_7_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_7_0_SPARE_BIT_7_SHIFT                    _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_7_0_SPARE_BIT_7_FIELD                    (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_7_0_SPARE_BIT_7_SHIFT)
+#define FUSE_SPARE_BIT_7_0_SPARE_BIT_7_RANGE                    0:0
+#define FUSE_SPARE_BIT_7_0_SPARE_BIT_7_WOFFSET                  0x0
+#define FUSE_SPARE_BIT_7_0_SPARE_BIT_7_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_7_0_SPARE_BIT_7_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_7_0_SPARE_BIT_7_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_7_0_SPARE_BIT_7_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_8_0  
+#define FUSE_SPARE_BIT_8_0                      _MK_ADDR_CONST(0x220)
+#define FUSE_SPARE_BIT_8_0_SECURE                       0x0
+#define FUSE_SPARE_BIT_8_0_WORD_COUNT                   0x1
+#define FUSE_SPARE_BIT_8_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_8_0_RESET_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_8_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_8_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_8_0_READ_MASK                    _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_8_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_8_0_SPARE_BIT_8_SHIFT                    _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_8_0_SPARE_BIT_8_FIELD                    (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_8_0_SPARE_BIT_8_SHIFT)
+#define FUSE_SPARE_BIT_8_0_SPARE_BIT_8_RANGE                    0:0
+#define FUSE_SPARE_BIT_8_0_SPARE_BIT_8_WOFFSET                  0x0
+#define FUSE_SPARE_BIT_8_0_SPARE_BIT_8_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_8_0_SPARE_BIT_8_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_8_0_SPARE_BIT_8_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_8_0_SPARE_BIT_8_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_9_0  
+#define FUSE_SPARE_BIT_9_0                      _MK_ADDR_CONST(0x224)
+#define FUSE_SPARE_BIT_9_0_SECURE                       0x0
+#define FUSE_SPARE_BIT_9_0_WORD_COUNT                   0x1
+#define FUSE_SPARE_BIT_9_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_9_0_RESET_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_9_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_9_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_9_0_READ_MASK                    _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_9_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_9_0_SPARE_BIT_9_SHIFT                    _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_9_0_SPARE_BIT_9_FIELD                    (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_9_0_SPARE_BIT_9_SHIFT)
+#define FUSE_SPARE_BIT_9_0_SPARE_BIT_9_RANGE                    0:0
+#define FUSE_SPARE_BIT_9_0_SPARE_BIT_9_WOFFSET                  0x0
+#define FUSE_SPARE_BIT_9_0_SPARE_BIT_9_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_9_0_SPARE_BIT_9_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_9_0_SPARE_BIT_9_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_9_0_SPARE_BIT_9_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_10_0  
+#define FUSE_SPARE_BIT_10_0                     _MK_ADDR_CONST(0x228)
+#define FUSE_SPARE_BIT_10_0_SECURE                      0x0
+#define FUSE_SPARE_BIT_10_0_WORD_COUNT                  0x1
+#define FUSE_SPARE_BIT_10_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_10_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_10_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_10_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_10_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_10_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_10_0_SPARE_BIT_10_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_10_0_SPARE_BIT_10_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_10_0_SPARE_BIT_10_SHIFT)
+#define FUSE_SPARE_BIT_10_0_SPARE_BIT_10_RANGE                  0:0
+#define FUSE_SPARE_BIT_10_0_SPARE_BIT_10_WOFFSET                        0x0
+#define FUSE_SPARE_BIT_10_0_SPARE_BIT_10_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_10_0_SPARE_BIT_10_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_10_0_SPARE_BIT_10_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_10_0_SPARE_BIT_10_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_11_0  
+#define FUSE_SPARE_BIT_11_0                     _MK_ADDR_CONST(0x22c)
+#define FUSE_SPARE_BIT_11_0_SECURE                      0x0
+#define FUSE_SPARE_BIT_11_0_WORD_COUNT                  0x1
+#define FUSE_SPARE_BIT_11_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_11_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_11_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_11_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_11_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_11_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_11_0_SPARE_BIT_11_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_11_0_SPARE_BIT_11_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_11_0_SPARE_BIT_11_SHIFT)
+#define FUSE_SPARE_BIT_11_0_SPARE_BIT_11_RANGE                  0:0
+#define FUSE_SPARE_BIT_11_0_SPARE_BIT_11_WOFFSET                        0x0
+#define FUSE_SPARE_BIT_11_0_SPARE_BIT_11_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_11_0_SPARE_BIT_11_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_11_0_SPARE_BIT_11_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_11_0_SPARE_BIT_11_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_12_0  
+#define FUSE_SPARE_BIT_12_0                     _MK_ADDR_CONST(0x230)
+#define FUSE_SPARE_BIT_12_0_SECURE                      0x0
+#define FUSE_SPARE_BIT_12_0_WORD_COUNT                  0x1
+#define FUSE_SPARE_BIT_12_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_12_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_12_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_12_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_12_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_12_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_12_0_SPARE_BIT_12_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_12_0_SPARE_BIT_12_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_12_0_SPARE_BIT_12_SHIFT)
+#define FUSE_SPARE_BIT_12_0_SPARE_BIT_12_RANGE                  0:0
+#define FUSE_SPARE_BIT_12_0_SPARE_BIT_12_WOFFSET                        0x0
+#define FUSE_SPARE_BIT_12_0_SPARE_BIT_12_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_12_0_SPARE_BIT_12_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_12_0_SPARE_BIT_12_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_12_0_SPARE_BIT_12_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_13_0  
+#define FUSE_SPARE_BIT_13_0                     _MK_ADDR_CONST(0x234)
+#define FUSE_SPARE_BIT_13_0_SECURE                      0x0
+#define FUSE_SPARE_BIT_13_0_WORD_COUNT                  0x1
+#define FUSE_SPARE_BIT_13_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_13_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_13_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_13_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_13_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_13_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_13_0_SPARE_BIT_13_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_13_0_SPARE_BIT_13_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_13_0_SPARE_BIT_13_SHIFT)
+#define FUSE_SPARE_BIT_13_0_SPARE_BIT_13_RANGE                  0:0
+#define FUSE_SPARE_BIT_13_0_SPARE_BIT_13_WOFFSET                        0x0
+#define FUSE_SPARE_BIT_13_0_SPARE_BIT_13_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_13_0_SPARE_BIT_13_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_13_0_SPARE_BIT_13_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_13_0_SPARE_BIT_13_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_14_0  
+#define FUSE_SPARE_BIT_14_0                     _MK_ADDR_CONST(0x238)
+#define FUSE_SPARE_BIT_14_0_SECURE                      0x0
+#define FUSE_SPARE_BIT_14_0_WORD_COUNT                  0x1
+#define FUSE_SPARE_BIT_14_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_14_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_14_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_14_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_14_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_14_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_14_0_SPARE_BIT_14_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_14_0_SPARE_BIT_14_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_14_0_SPARE_BIT_14_SHIFT)
+#define FUSE_SPARE_BIT_14_0_SPARE_BIT_14_RANGE                  0:0
+#define FUSE_SPARE_BIT_14_0_SPARE_BIT_14_WOFFSET                        0x0
+#define FUSE_SPARE_BIT_14_0_SPARE_BIT_14_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_14_0_SPARE_BIT_14_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_14_0_SPARE_BIT_14_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_14_0_SPARE_BIT_14_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_15_0  
+#define FUSE_SPARE_BIT_15_0                     _MK_ADDR_CONST(0x23c)
+#define FUSE_SPARE_BIT_15_0_SECURE                      0x0
+#define FUSE_SPARE_BIT_15_0_WORD_COUNT                  0x1
+#define FUSE_SPARE_BIT_15_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_15_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_15_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_15_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_15_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_15_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_15_0_SPARE_BIT_15_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_15_0_SPARE_BIT_15_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_15_0_SPARE_BIT_15_SHIFT)
+#define FUSE_SPARE_BIT_15_0_SPARE_BIT_15_RANGE                  0:0
+#define FUSE_SPARE_BIT_15_0_SPARE_BIT_15_WOFFSET                        0x0
+#define FUSE_SPARE_BIT_15_0_SPARE_BIT_15_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_15_0_SPARE_BIT_15_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_15_0_SPARE_BIT_15_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_15_0_SPARE_BIT_15_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_16_0  
+#define FUSE_SPARE_BIT_16_0                     _MK_ADDR_CONST(0x240)
+#define FUSE_SPARE_BIT_16_0_SECURE                      0x0
+#define FUSE_SPARE_BIT_16_0_WORD_COUNT                  0x1
+#define FUSE_SPARE_BIT_16_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_16_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_16_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_16_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_16_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_16_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_16_0_SPARE_BIT_16_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_16_0_SPARE_BIT_16_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_16_0_SPARE_BIT_16_SHIFT)
+#define FUSE_SPARE_BIT_16_0_SPARE_BIT_16_RANGE                  0:0
+#define FUSE_SPARE_BIT_16_0_SPARE_BIT_16_WOFFSET                        0x0
+#define FUSE_SPARE_BIT_16_0_SPARE_BIT_16_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_16_0_SPARE_BIT_16_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_16_0_SPARE_BIT_16_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_16_0_SPARE_BIT_16_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_17_0  
+#define FUSE_SPARE_BIT_17_0                     _MK_ADDR_CONST(0x244)
+#define FUSE_SPARE_BIT_17_0_SECURE                      0x0
+#define FUSE_SPARE_BIT_17_0_WORD_COUNT                  0x1
+#define FUSE_SPARE_BIT_17_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_17_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_17_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_17_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_17_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_17_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_17_0_SPARE_BIT_17_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_17_0_SPARE_BIT_17_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_17_0_SPARE_BIT_17_SHIFT)
+#define FUSE_SPARE_BIT_17_0_SPARE_BIT_17_RANGE                  0:0
+#define FUSE_SPARE_BIT_17_0_SPARE_BIT_17_WOFFSET                        0x0
+#define FUSE_SPARE_BIT_17_0_SPARE_BIT_17_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_17_0_SPARE_BIT_17_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_17_0_SPARE_BIT_17_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_17_0_SPARE_BIT_17_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_18_0  
+#define FUSE_SPARE_BIT_18_0                     _MK_ADDR_CONST(0x248)
+#define FUSE_SPARE_BIT_18_0_SECURE                      0x0
+#define FUSE_SPARE_BIT_18_0_WORD_COUNT                  0x1
+#define FUSE_SPARE_BIT_18_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_18_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_18_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_18_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_18_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_18_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_18_0_SPARE_BIT_18_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_18_0_SPARE_BIT_18_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_18_0_SPARE_BIT_18_SHIFT)
+#define FUSE_SPARE_BIT_18_0_SPARE_BIT_18_RANGE                  0:0
+#define FUSE_SPARE_BIT_18_0_SPARE_BIT_18_WOFFSET                        0x0
+#define FUSE_SPARE_BIT_18_0_SPARE_BIT_18_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_18_0_SPARE_BIT_18_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_18_0_SPARE_BIT_18_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_18_0_SPARE_BIT_18_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_19_0  
+#define FUSE_SPARE_BIT_19_0                     _MK_ADDR_CONST(0x24c)
+#define FUSE_SPARE_BIT_19_0_SECURE                      0x0
+#define FUSE_SPARE_BIT_19_0_WORD_COUNT                  0x1
+#define FUSE_SPARE_BIT_19_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_19_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_19_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_19_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_19_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_19_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_19_0_SPARE_BIT_19_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_19_0_SPARE_BIT_19_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_19_0_SPARE_BIT_19_SHIFT)
+#define FUSE_SPARE_BIT_19_0_SPARE_BIT_19_RANGE                  0:0
+#define FUSE_SPARE_BIT_19_0_SPARE_BIT_19_WOFFSET                        0x0
+#define FUSE_SPARE_BIT_19_0_SPARE_BIT_19_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_19_0_SPARE_BIT_19_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_19_0_SPARE_BIT_19_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_19_0_SPARE_BIT_19_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_20_0  
+#define FUSE_SPARE_BIT_20_0                     _MK_ADDR_CONST(0x250)
+#define FUSE_SPARE_BIT_20_0_SECURE                      0x0
+#define FUSE_SPARE_BIT_20_0_WORD_COUNT                  0x1
+#define FUSE_SPARE_BIT_20_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_20_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_20_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_20_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_20_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_20_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_20_0_SPARE_BIT_20_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_20_0_SPARE_BIT_20_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_20_0_SPARE_BIT_20_SHIFT)
+#define FUSE_SPARE_BIT_20_0_SPARE_BIT_20_RANGE                  0:0
+#define FUSE_SPARE_BIT_20_0_SPARE_BIT_20_WOFFSET                        0x0
+#define FUSE_SPARE_BIT_20_0_SPARE_BIT_20_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_20_0_SPARE_BIT_20_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_20_0_SPARE_BIT_20_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_20_0_SPARE_BIT_20_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_21_0  
+#define FUSE_SPARE_BIT_21_0                     _MK_ADDR_CONST(0x254)
+#define FUSE_SPARE_BIT_21_0_SECURE                      0x0
+#define FUSE_SPARE_BIT_21_0_WORD_COUNT                  0x1
+#define FUSE_SPARE_BIT_21_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_21_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_21_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_21_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_21_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_21_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_21_0_SPARE_BIT_21_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_21_0_SPARE_BIT_21_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_21_0_SPARE_BIT_21_SHIFT)
+#define FUSE_SPARE_BIT_21_0_SPARE_BIT_21_RANGE                  0:0
+#define FUSE_SPARE_BIT_21_0_SPARE_BIT_21_WOFFSET                        0x0
+#define FUSE_SPARE_BIT_21_0_SPARE_BIT_21_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_21_0_SPARE_BIT_21_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_21_0_SPARE_BIT_21_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_21_0_SPARE_BIT_21_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_22_0  
+#define FUSE_SPARE_BIT_22_0                     _MK_ADDR_CONST(0x258)
+#define FUSE_SPARE_BIT_22_0_SECURE                      0x0
+#define FUSE_SPARE_BIT_22_0_WORD_COUNT                  0x1
+#define FUSE_SPARE_BIT_22_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_22_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_22_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_22_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_22_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_22_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_22_0_SPARE_BIT_22_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_22_0_SPARE_BIT_22_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_22_0_SPARE_BIT_22_SHIFT)
+#define FUSE_SPARE_BIT_22_0_SPARE_BIT_22_RANGE                  0:0
+#define FUSE_SPARE_BIT_22_0_SPARE_BIT_22_WOFFSET                        0x0
+#define FUSE_SPARE_BIT_22_0_SPARE_BIT_22_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_22_0_SPARE_BIT_22_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_22_0_SPARE_BIT_22_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_22_0_SPARE_BIT_22_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_23_0  
+#define FUSE_SPARE_BIT_23_0                     _MK_ADDR_CONST(0x25c)
+#define FUSE_SPARE_BIT_23_0_SECURE                      0x0
+#define FUSE_SPARE_BIT_23_0_WORD_COUNT                  0x1
+#define FUSE_SPARE_BIT_23_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_23_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_23_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_23_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_23_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_23_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_23_0_SPARE_BIT_23_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_23_0_SPARE_BIT_23_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_23_0_SPARE_BIT_23_SHIFT)
+#define FUSE_SPARE_BIT_23_0_SPARE_BIT_23_RANGE                  0:0
+#define FUSE_SPARE_BIT_23_0_SPARE_BIT_23_WOFFSET                        0x0
+#define FUSE_SPARE_BIT_23_0_SPARE_BIT_23_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_23_0_SPARE_BIT_23_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_23_0_SPARE_BIT_23_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_23_0_SPARE_BIT_23_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_24_0  
+#define FUSE_SPARE_BIT_24_0                     _MK_ADDR_CONST(0x260)
+#define FUSE_SPARE_BIT_24_0_SECURE                      0x0
+#define FUSE_SPARE_BIT_24_0_WORD_COUNT                  0x1
+#define FUSE_SPARE_BIT_24_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_24_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_24_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_24_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_24_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_24_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_24_0_SPARE_BIT_24_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_24_0_SPARE_BIT_24_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_24_0_SPARE_BIT_24_SHIFT)
+#define FUSE_SPARE_BIT_24_0_SPARE_BIT_24_RANGE                  0:0
+#define FUSE_SPARE_BIT_24_0_SPARE_BIT_24_WOFFSET                        0x0
+#define FUSE_SPARE_BIT_24_0_SPARE_BIT_24_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_24_0_SPARE_BIT_24_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_24_0_SPARE_BIT_24_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_24_0_SPARE_BIT_24_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_25_0  
+#define FUSE_SPARE_BIT_25_0                     _MK_ADDR_CONST(0x264)
+#define FUSE_SPARE_BIT_25_0_SECURE                      0x0
+#define FUSE_SPARE_BIT_25_0_WORD_COUNT                  0x1
+#define FUSE_SPARE_BIT_25_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_25_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_25_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_25_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_25_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_25_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_25_0_SPARE_BIT_25_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_25_0_SPARE_BIT_25_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_25_0_SPARE_BIT_25_SHIFT)
+#define FUSE_SPARE_BIT_25_0_SPARE_BIT_25_RANGE                  0:0
+#define FUSE_SPARE_BIT_25_0_SPARE_BIT_25_WOFFSET                        0x0
+#define FUSE_SPARE_BIT_25_0_SPARE_BIT_25_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_25_0_SPARE_BIT_25_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_25_0_SPARE_BIT_25_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_25_0_SPARE_BIT_25_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_26_0  
+#define FUSE_SPARE_BIT_26_0                     _MK_ADDR_CONST(0x268)
+#define FUSE_SPARE_BIT_26_0_SECURE                      0x0
+#define FUSE_SPARE_BIT_26_0_WORD_COUNT                  0x1
+#define FUSE_SPARE_BIT_26_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_26_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_26_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_26_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_26_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_26_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_26_0_SPARE_BIT_26_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_26_0_SPARE_BIT_26_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_26_0_SPARE_BIT_26_SHIFT)
+#define FUSE_SPARE_BIT_26_0_SPARE_BIT_26_RANGE                  0:0
+#define FUSE_SPARE_BIT_26_0_SPARE_BIT_26_WOFFSET                        0x0
+#define FUSE_SPARE_BIT_26_0_SPARE_BIT_26_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_26_0_SPARE_BIT_26_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_26_0_SPARE_BIT_26_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_26_0_SPARE_BIT_26_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_27_0  
+#define FUSE_SPARE_BIT_27_0                     _MK_ADDR_CONST(0x26c)
+#define FUSE_SPARE_BIT_27_0_SECURE                      0x0
+#define FUSE_SPARE_BIT_27_0_WORD_COUNT                  0x1
+#define FUSE_SPARE_BIT_27_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_27_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_27_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_27_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_27_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_27_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_27_0_SPARE_BIT_27_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_27_0_SPARE_BIT_27_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_27_0_SPARE_BIT_27_SHIFT)
+#define FUSE_SPARE_BIT_27_0_SPARE_BIT_27_RANGE                  0:0
+#define FUSE_SPARE_BIT_27_0_SPARE_BIT_27_WOFFSET                        0x0
+#define FUSE_SPARE_BIT_27_0_SPARE_BIT_27_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_27_0_SPARE_BIT_27_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_27_0_SPARE_BIT_27_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_27_0_SPARE_BIT_27_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_28_0  
+#define FUSE_SPARE_BIT_28_0                     _MK_ADDR_CONST(0x270)
+#define FUSE_SPARE_BIT_28_0_SECURE                      0x0
+#define FUSE_SPARE_BIT_28_0_WORD_COUNT                  0x1
+#define FUSE_SPARE_BIT_28_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_28_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_28_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_28_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_28_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_28_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_28_0_SPARE_BIT_28_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_28_0_SPARE_BIT_28_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_28_0_SPARE_BIT_28_SHIFT)
+#define FUSE_SPARE_BIT_28_0_SPARE_BIT_28_RANGE                  0:0
+#define FUSE_SPARE_BIT_28_0_SPARE_BIT_28_WOFFSET                        0x0
+#define FUSE_SPARE_BIT_28_0_SPARE_BIT_28_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_28_0_SPARE_BIT_28_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_28_0_SPARE_BIT_28_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_28_0_SPARE_BIT_28_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_29_0  
+#define FUSE_SPARE_BIT_29_0                     _MK_ADDR_CONST(0x274)
+#define FUSE_SPARE_BIT_29_0_SECURE                      0x0
+#define FUSE_SPARE_BIT_29_0_WORD_COUNT                  0x1
+#define FUSE_SPARE_BIT_29_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_29_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_29_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_29_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_29_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_29_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_29_0_SPARE_BIT_29_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_29_0_SPARE_BIT_29_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_29_0_SPARE_BIT_29_SHIFT)
+#define FUSE_SPARE_BIT_29_0_SPARE_BIT_29_RANGE                  0:0
+#define FUSE_SPARE_BIT_29_0_SPARE_BIT_29_WOFFSET                        0x0
+#define FUSE_SPARE_BIT_29_0_SPARE_BIT_29_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_29_0_SPARE_BIT_29_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_29_0_SPARE_BIT_29_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_29_0_SPARE_BIT_29_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_30_0  
+#define FUSE_SPARE_BIT_30_0                     _MK_ADDR_CONST(0x278)
+#define FUSE_SPARE_BIT_30_0_SECURE                      0x0
+#define FUSE_SPARE_BIT_30_0_WORD_COUNT                  0x1
+#define FUSE_SPARE_BIT_30_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_30_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_30_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_30_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_30_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_30_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_30_0_SPARE_BIT_30_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_30_0_SPARE_BIT_30_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_30_0_SPARE_BIT_30_SHIFT)
+#define FUSE_SPARE_BIT_30_0_SPARE_BIT_30_RANGE                  0:0
+#define FUSE_SPARE_BIT_30_0_SPARE_BIT_30_WOFFSET                        0x0
+#define FUSE_SPARE_BIT_30_0_SPARE_BIT_30_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_30_0_SPARE_BIT_30_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_30_0_SPARE_BIT_30_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_30_0_SPARE_BIT_30_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_31_0  
+#define FUSE_SPARE_BIT_31_0                     _MK_ADDR_CONST(0x27c)
+#define FUSE_SPARE_BIT_31_0_SECURE                      0x0
+#define FUSE_SPARE_BIT_31_0_WORD_COUNT                  0x1
+#define FUSE_SPARE_BIT_31_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_31_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_31_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_31_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_31_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_31_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_31_0_SPARE_BIT_31_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_31_0_SPARE_BIT_31_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_31_0_SPARE_BIT_31_SHIFT)
+#define FUSE_SPARE_BIT_31_0_SPARE_BIT_31_RANGE                  0:0
+#define FUSE_SPARE_BIT_31_0_SPARE_BIT_31_WOFFSET                        0x0
+#define FUSE_SPARE_BIT_31_0_SPARE_BIT_31_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_31_0_SPARE_BIT_31_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_31_0_SPARE_BIT_31_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_31_0_SPARE_BIT_31_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_32_0  
+#define FUSE_SPARE_BIT_32_0                     _MK_ADDR_CONST(0x280)
+#define FUSE_SPARE_BIT_32_0_SECURE                      0x0
+#define FUSE_SPARE_BIT_32_0_WORD_COUNT                  0x1
+#define FUSE_SPARE_BIT_32_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_32_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_32_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_32_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_32_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_32_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_32_0_SPARE_BIT_32_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_32_0_SPARE_BIT_32_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_32_0_SPARE_BIT_32_SHIFT)
+#define FUSE_SPARE_BIT_32_0_SPARE_BIT_32_RANGE                  0:0
+#define FUSE_SPARE_BIT_32_0_SPARE_BIT_32_WOFFSET                        0x0
+#define FUSE_SPARE_BIT_32_0_SPARE_BIT_32_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_32_0_SPARE_BIT_32_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_32_0_SPARE_BIT_32_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_32_0_SPARE_BIT_32_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_33_0  
+#define FUSE_SPARE_BIT_33_0                     _MK_ADDR_CONST(0x284)
+#define FUSE_SPARE_BIT_33_0_SECURE                      0x0
+#define FUSE_SPARE_BIT_33_0_WORD_COUNT                  0x1
+#define FUSE_SPARE_BIT_33_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_33_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_33_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_33_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_33_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_33_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_33_0_SPARE_BIT_33_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_33_0_SPARE_BIT_33_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_33_0_SPARE_BIT_33_SHIFT)
+#define FUSE_SPARE_BIT_33_0_SPARE_BIT_33_RANGE                  0:0
+#define FUSE_SPARE_BIT_33_0_SPARE_BIT_33_WOFFSET                        0x0
+#define FUSE_SPARE_BIT_33_0_SPARE_BIT_33_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_33_0_SPARE_BIT_33_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_33_0_SPARE_BIT_33_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_33_0_SPARE_BIT_33_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_34_0  
+#define FUSE_SPARE_BIT_34_0                     _MK_ADDR_CONST(0x288)
+#define FUSE_SPARE_BIT_34_0_SECURE                      0x0
+#define FUSE_SPARE_BIT_34_0_WORD_COUNT                  0x1
+#define FUSE_SPARE_BIT_34_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_34_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_34_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_34_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_34_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_34_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_34_0_SPARE_BIT_34_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_34_0_SPARE_BIT_34_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_34_0_SPARE_BIT_34_SHIFT)
+#define FUSE_SPARE_BIT_34_0_SPARE_BIT_34_RANGE                  0:0
+#define FUSE_SPARE_BIT_34_0_SPARE_BIT_34_WOFFSET                        0x0
+#define FUSE_SPARE_BIT_34_0_SPARE_BIT_34_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_34_0_SPARE_BIT_34_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_34_0_SPARE_BIT_34_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_34_0_SPARE_BIT_34_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_35_0  
+#define FUSE_SPARE_BIT_35_0                     _MK_ADDR_CONST(0x28c)
+#define FUSE_SPARE_BIT_35_0_SECURE                      0x0
+#define FUSE_SPARE_BIT_35_0_WORD_COUNT                  0x1
+#define FUSE_SPARE_BIT_35_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_35_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_35_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_35_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_35_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_35_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_35_0_SPARE_BIT_35_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_35_0_SPARE_BIT_35_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_35_0_SPARE_BIT_35_SHIFT)
+#define FUSE_SPARE_BIT_35_0_SPARE_BIT_35_RANGE                  0:0
+#define FUSE_SPARE_BIT_35_0_SPARE_BIT_35_WOFFSET                        0x0
+#define FUSE_SPARE_BIT_35_0_SPARE_BIT_35_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_35_0_SPARE_BIT_35_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_35_0_SPARE_BIT_35_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_35_0_SPARE_BIT_35_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_36_0  
+#define FUSE_SPARE_BIT_36_0                     _MK_ADDR_CONST(0x290)
+#define FUSE_SPARE_BIT_36_0_SECURE                      0x0
+#define FUSE_SPARE_BIT_36_0_WORD_COUNT                  0x1
+#define FUSE_SPARE_BIT_36_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_36_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_36_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_36_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_36_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_36_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_36_0_SPARE_BIT_36_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_36_0_SPARE_BIT_36_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_36_0_SPARE_BIT_36_SHIFT)
+#define FUSE_SPARE_BIT_36_0_SPARE_BIT_36_RANGE                  0:0
+#define FUSE_SPARE_BIT_36_0_SPARE_BIT_36_WOFFSET                        0x0
+#define FUSE_SPARE_BIT_36_0_SPARE_BIT_36_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_36_0_SPARE_BIT_36_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_36_0_SPARE_BIT_36_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_36_0_SPARE_BIT_36_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_37_0  
+#define FUSE_SPARE_BIT_37_0                     _MK_ADDR_CONST(0x294)
+#define FUSE_SPARE_BIT_37_0_SECURE                      0x0
+#define FUSE_SPARE_BIT_37_0_WORD_COUNT                  0x1
+#define FUSE_SPARE_BIT_37_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_37_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_37_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_37_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_37_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_37_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_37_0_SPARE_BIT_37_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_37_0_SPARE_BIT_37_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_37_0_SPARE_BIT_37_SHIFT)
+#define FUSE_SPARE_BIT_37_0_SPARE_BIT_37_RANGE                  0:0
+#define FUSE_SPARE_BIT_37_0_SPARE_BIT_37_WOFFSET                        0x0
+#define FUSE_SPARE_BIT_37_0_SPARE_BIT_37_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_37_0_SPARE_BIT_37_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_37_0_SPARE_BIT_37_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_37_0_SPARE_BIT_37_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_38_0  
+#define FUSE_SPARE_BIT_38_0                     _MK_ADDR_CONST(0x298)
+#define FUSE_SPARE_BIT_38_0_SECURE                      0x0
+#define FUSE_SPARE_BIT_38_0_WORD_COUNT                  0x1
+#define FUSE_SPARE_BIT_38_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_38_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_38_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_38_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_38_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_38_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_38_0_SPARE_BIT_38_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_38_0_SPARE_BIT_38_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_38_0_SPARE_BIT_38_SHIFT)
+#define FUSE_SPARE_BIT_38_0_SPARE_BIT_38_RANGE                  0:0
+#define FUSE_SPARE_BIT_38_0_SPARE_BIT_38_WOFFSET                        0x0
+#define FUSE_SPARE_BIT_38_0_SPARE_BIT_38_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_38_0_SPARE_BIT_38_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_38_0_SPARE_BIT_38_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_38_0_SPARE_BIT_38_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_39_0  
+#define FUSE_SPARE_BIT_39_0                     _MK_ADDR_CONST(0x29c)
+#define FUSE_SPARE_BIT_39_0_SECURE                      0x0
+#define FUSE_SPARE_BIT_39_0_WORD_COUNT                  0x1
+#define FUSE_SPARE_BIT_39_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_39_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_39_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_39_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_39_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_39_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_39_0_SPARE_BIT_39_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_39_0_SPARE_BIT_39_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_39_0_SPARE_BIT_39_SHIFT)
+#define FUSE_SPARE_BIT_39_0_SPARE_BIT_39_RANGE                  0:0
+#define FUSE_SPARE_BIT_39_0_SPARE_BIT_39_WOFFSET                        0x0
+#define FUSE_SPARE_BIT_39_0_SPARE_BIT_39_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_39_0_SPARE_BIT_39_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_39_0_SPARE_BIT_39_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_39_0_SPARE_BIT_39_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_40_0  
+#define FUSE_SPARE_BIT_40_0                     _MK_ADDR_CONST(0x2a0)
+#define FUSE_SPARE_BIT_40_0_SECURE                      0x0
+#define FUSE_SPARE_BIT_40_0_WORD_COUNT                  0x1
+#define FUSE_SPARE_BIT_40_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_40_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_40_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_40_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_40_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_40_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_40_0_SPARE_BIT_40_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_40_0_SPARE_BIT_40_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_40_0_SPARE_BIT_40_SHIFT)
+#define FUSE_SPARE_BIT_40_0_SPARE_BIT_40_RANGE                  0:0
+#define FUSE_SPARE_BIT_40_0_SPARE_BIT_40_WOFFSET                        0x0
+#define FUSE_SPARE_BIT_40_0_SPARE_BIT_40_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_40_0_SPARE_BIT_40_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_40_0_SPARE_BIT_40_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_40_0_SPARE_BIT_40_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_41_0  
+#define FUSE_SPARE_BIT_41_0                     _MK_ADDR_CONST(0x2a4)
+#define FUSE_SPARE_BIT_41_0_SECURE                      0x0
+#define FUSE_SPARE_BIT_41_0_WORD_COUNT                  0x1
+#define FUSE_SPARE_BIT_41_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_41_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_41_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_41_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_41_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_41_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_41_0_SPARE_BIT_41_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_41_0_SPARE_BIT_41_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_41_0_SPARE_BIT_41_SHIFT)
+#define FUSE_SPARE_BIT_41_0_SPARE_BIT_41_RANGE                  0:0
+#define FUSE_SPARE_BIT_41_0_SPARE_BIT_41_WOFFSET                        0x0
+#define FUSE_SPARE_BIT_41_0_SPARE_BIT_41_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_41_0_SPARE_BIT_41_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_41_0_SPARE_BIT_41_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_41_0_SPARE_BIT_41_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_42_0  
+#define FUSE_SPARE_BIT_42_0                     _MK_ADDR_CONST(0x2a8)
+#define FUSE_SPARE_BIT_42_0_SECURE                      0x0
+#define FUSE_SPARE_BIT_42_0_WORD_COUNT                  0x1
+#define FUSE_SPARE_BIT_42_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_42_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_42_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_42_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_42_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_42_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_42_0_SPARE_BIT_42_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_42_0_SPARE_BIT_42_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_42_0_SPARE_BIT_42_SHIFT)
+#define FUSE_SPARE_BIT_42_0_SPARE_BIT_42_RANGE                  0:0
+#define FUSE_SPARE_BIT_42_0_SPARE_BIT_42_WOFFSET                        0x0
+#define FUSE_SPARE_BIT_42_0_SPARE_BIT_42_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_42_0_SPARE_BIT_42_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_42_0_SPARE_BIT_42_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_42_0_SPARE_BIT_42_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_43_0  
+#define FUSE_SPARE_BIT_43_0                     _MK_ADDR_CONST(0x2ac)
+#define FUSE_SPARE_BIT_43_0_SECURE                      0x0
+#define FUSE_SPARE_BIT_43_0_WORD_COUNT                  0x1
+#define FUSE_SPARE_BIT_43_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_43_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_43_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_43_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_43_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_43_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_43_0_SPARE_BIT_43_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_43_0_SPARE_BIT_43_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_43_0_SPARE_BIT_43_SHIFT)
+#define FUSE_SPARE_BIT_43_0_SPARE_BIT_43_RANGE                  0:0
+#define FUSE_SPARE_BIT_43_0_SPARE_BIT_43_WOFFSET                        0x0
+#define FUSE_SPARE_BIT_43_0_SPARE_BIT_43_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_43_0_SPARE_BIT_43_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_43_0_SPARE_BIT_43_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_43_0_SPARE_BIT_43_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_44_0  
+#define FUSE_SPARE_BIT_44_0                     _MK_ADDR_CONST(0x2b0)
+#define FUSE_SPARE_BIT_44_0_SECURE                      0x0
+#define FUSE_SPARE_BIT_44_0_WORD_COUNT                  0x1
+#define FUSE_SPARE_BIT_44_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_44_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_44_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_44_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_44_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_44_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_44_0_SPARE_BIT_44_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_44_0_SPARE_BIT_44_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_44_0_SPARE_BIT_44_SHIFT)
+#define FUSE_SPARE_BIT_44_0_SPARE_BIT_44_RANGE                  0:0
+#define FUSE_SPARE_BIT_44_0_SPARE_BIT_44_WOFFSET                        0x0
+#define FUSE_SPARE_BIT_44_0_SPARE_BIT_44_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_44_0_SPARE_BIT_44_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_44_0_SPARE_BIT_44_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_44_0_SPARE_BIT_44_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_45_0  
+#define FUSE_SPARE_BIT_45_0                     _MK_ADDR_CONST(0x2b4)
+#define FUSE_SPARE_BIT_45_0_SECURE                      0x0
+#define FUSE_SPARE_BIT_45_0_WORD_COUNT                  0x1
+#define FUSE_SPARE_BIT_45_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_45_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_45_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_45_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_45_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_45_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_45_0_SPARE_BIT_45_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_45_0_SPARE_BIT_45_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_45_0_SPARE_BIT_45_SHIFT)
+#define FUSE_SPARE_BIT_45_0_SPARE_BIT_45_RANGE                  0:0
+#define FUSE_SPARE_BIT_45_0_SPARE_BIT_45_WOFFSET                        0x0
+#define FUSE_SPARE_BIT_45_0_SPARE_BIT_45_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_45_0_SPARE_BIT_45_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_45_0_SPARE_BIT_45_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_45_0_SPARE_BIT_45_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_46_0  
+#define FUSE_SPARE_BIT_46_0                     _MK_ADDR_CONST(0x2b8)
+#define FUSE_SPARE_BIT_46_0_SECURE                      0x0
+#define FUSE_SPARE_BIT_46_0_WORD_COUNT                  0x1
+#define FUSE_SPARE_BIT_46_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_46_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_46_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_46_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_46_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_46_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_46_0_SPARE_BIT_46_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_46_0_SPARE_BIT_46_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_46_0_SPARE_BIT_46_SHIFT)
+#define FUSE_SPARE_BIT_46_0_SPARE_BIT_46_RANGE                  0:0
+#define FUSE_SPARE_BIT_46_0_SPARE_BIT_46_WOFFSET                        0x0
+#define FUSE_SPARE_BIT_46_0_SPARE_BIT_46_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_46_0_SPARE_BIT_46_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_46_0_SPARE_BIT_46_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_46_0_SPARE_BIT_46_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_47_0  
+#define FUSE_SPARE_BIT_47_0                     _MK_ADDR_CONST(0x2bc)
+#define FUSE_SPARE_BIT_47_0_SECURE                      0x0
+#define FUSE_SPARE_BIT_47_0_WORD_COUNT                  0x1
+#define FUSE_SPARE_BIT_47_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_47_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_47_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_47_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_47_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_47_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_47_0_SPARE_BIT_47_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_47_0_SPARE_BIT_47_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_47_0_SPARE_BIT_47_SHIFT)
+#define FUSE_SPARE_BIT_47_0_SPARE_BIT_47_RANGE                  0:0
+#define FUSE_SPARE_BIT_47_0_SPARE_BIT_47_WOFFSET                        0x0
+#define FUSE_SPARE_BIT_47_0_SPARE_BIT_47_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_47_0_SPARE_BIT_47_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_47_0_SPARE_BIT_47_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_47_0_SPARE_BIT_47_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_48_0  
+#define FUSE_SPARE_BIT_48_0                     _MK_ADDR_CONST(0x2c0)
+#define FUSE_SPARE_BIT_48_0_SECURE                      0x0
+#define FUSE_SPARE_BIT_48_0_WORD_COUNT                  0x1
+#define FUSE_SPARE_BIT_48_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_48_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_48_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_48_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_48_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_48_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_48_0_SPARE_BIT_48_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_48_0_SPARE_BIT_48_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_48_0_SPARE_BIT_48_SHIFT)
+#define FUSE_SPARE_BIT_48_0_SPARE_BIT_48_RANGE                  0:0
+#define FUSE_SPARE_BIT_48_0_SPARE_BIT_48_WOFFSET                        0x0
+#define FUSE_SPARE_BIT_48_0_SPARE_BIT_48_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_48_0_SPARE_BIT_48_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_48_0_SPARE_BIT_48_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_48_0_SPARE_BIT_48_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_49_0  
+#define FUSE_SPARE_BIT_49_0                     _MK_ADDR_CONST(0x2c4)
+#define FUSE_SPARE_BIT_49_0_SECURE                      0x0
+#define FUSE_SPARE_BIT_49_0_WORD_COUNT                  0x1
+#define FUSE_SPARE_BIT_49_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_49_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_49_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_49_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_49_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_49_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_49_0_SPARE_BIT_49_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_49_0_SPARE_BIT_49_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_49_0_SPARE_BIT_49_SHIFT)
+#define FUSE_SPARE_BIT_49_0_SPARE_BIT_49_RANGE                  0:0
+#define FUSE_SPARE_BIT_49_0_SPARE_BIT_49_WOFFSET                        0x0
+#define FUSE_SPARE_BIT_49_0_SPARE_BIT_49_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_49_0_SPARE_BIT_49_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_49_0_SPARE_BIT_49_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_49_0_SPARE_BIT_49_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_50_0  
+#define FUSE_SPARE_BIT_50_0                     _MK_ADDR_CONST(0x2c8)
+#define FUSE_SPARE_BIT_50_0_SECURE                      0x0
+#define FUSE_SPARE_BIT_50_0_WORD_COUNT                  0x1
+#define FUSE_SPARE_BIT_50_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_50_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_50_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_50_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_50_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_50_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_50_0_SPARE_BIT_50_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_50_0_SPARE_BIT_50_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_50_0_SPARE_BIT_50_SHIFT)
+#define FUSE_SPARE_BIT_50_0_SPARE_BIT_50_RANGE                  0:0
+#define FUSE_SPARE_BIT_50_0_SPARE_BIT_50_WOFFSET                        0x0
+#define FUSE_SPARE_BIT_50_0_SPARE_BIT_50_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_50_0_SPARE_BIT_50_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_50_0_SPARE_BIT_50_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_50_0_SPARE_BIT_50_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_51_0  
+#define FUSE_SPARE_BIT_51_0                     _MK_ADDR_CONST(0x2cc)
+#define FUSE_SPARE_BIT_51_0_SECURE                      0x0
+#define FUSE_SPARE_BIT_51_0_WORD_COUNT                  0x1
+#define FUSE_SPARE_BIT_51_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_51_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_51_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_51_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_51_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_51_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_51_0_SPARE_BIT_51_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_51_0_SPARE_BIT_51_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_51_0_SPARE_BIT_51_SHIFT)
+#define FUSE_SPARE_BIT_51_0_SPARE_BIT_51_RANGE                  0:0
+#define FUSE_SPARE_BIT_51_0_SPARE_BIT_51_WOFFSET                        0x0
+#define FUSE_SPARE_BIT_51_0_SPARE_BIT_51_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_51_0_SPARE_BIT_51_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_51_0_SPARE_BIT_51_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_51_0_SPARE_BIT_51_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_52_0  
+#define FUSE_SPARE_BIT_52_0                     _MK_ADDR_CONST(0x2d0)
+#define FUSE_SPARE_BIT_52_0_SECURE                      0x0
+#define FUSE_SPARE_BIT_52_0_WORD_COUNT                  0x1
+#define FUSE_SPARE_BIT_52_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_52_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_52_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_52_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_52_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_52_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_52_0_SPARE_BIT_52_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_52_0_SPARE_BIT_52_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_52_0_SPARE_BIT_52_SHIFT)
+#define FUSE_SPARE_BIT_52_0_SPARE_BIT_52_RANGE                  0:0
+#define FUSE_SPARE_BIT_52_0_SPARE_BIT_52_WOFFSET                        0x0
+#define FUSE_SPARE_BIT_52_0_SPARE_BIT_52_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_52_0_SPARE_BIT_52_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_52_0_SPARE_BIT_52_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_52_0_SPARE_BIT_52_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_53_0  
+#define FUSE_SPARE_BIT_53_0                     _MK_ADDR_CONST(0x2d4)
+#define FUSE_SPARE_BIT_53_0_SECURE                      0x0
+#define FUSE_SPARE_BIT_53_0_WORD_COUNT                  0x1
+#define FUSE_SPARE_BIT_53_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_53_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_53_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_53_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_53_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_53_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_53_0_SPARE_BIT_53_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_53_0_SPARE_BIT_53_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_53_0_SPARE_BIT_53_SHIFT)
+#define FUSE_SPARE_BIT_53_0_SPARE_BIT_53_RANGE                  0:0
+#define FUSE_SPARE_BIT_53_0_SPARE_BIT_53_WOFFSET                        0x0
+#define FUSE_SPARE_BIT_53_0_SPARE_BIT_53_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_53_0_SPARE_BIT_53_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_53_0_SPARE_BIT_53_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_53_0_SPARE_BIT_53_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_54_0  
+#define FUSE_SPARE_BIT_54_0                     _MK_ADDR_CONST(0x2d8)
+#define FUSE_SPARE_BIT_54_0_SECURE                      0x0
+#define FUSE_SPARE_BIT_54_0_WORD_COUNT                  0x1
+#define FUSE_SPARE_BIT_54_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_54_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_54_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_54_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_54_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_54_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_54_0_SPARE_BIT_54_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_54_0_SPARE_BIT_54_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_54_0_SPARE_BIT_54_SHIFT)
+#define FUSE_SPARE_BIT_54_0_SPARE_BIT_54_RANGE                  0:0
+#define FUSE_SPARE_BIT_54_0_SPARE_BIT_54_WOFFSET                        0x0
+#define FUSE_SPARE_BIT_54_0_SPARE_BIT_54_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_54_0_SPARE_BIT_54_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_54_0_SPARE_BIT_54_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_54_0_SPARE_BIT_54_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_55_0  
+#define FUSE_SPARE_BIT_55_0                     _MK_ADDR_CONST(0x2dc)
+#define FUSE_SPARE_BIT_55_0_SECURE                      0x0
+#define FUSE_SPARE_BIT_55_0_WORD_COUNT                  0x1
+#define FUSE_SPARE_BIT_55_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_55_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_55_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_55_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_55_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_55_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_55_0_SPARE_BIT_55_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_55_0_SPARE_BIT_55_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_55_0_SPARE_BIT_55_SHIFT)
+#define FUSE_SPARE_BIT_55_0_SPARE_BIT_55_RANGE                  0:0
+#define FUSE_SPARE_BIT_55_0_SPARE_BIT_55_WOFFSET                        0x0
+#define FUSE_SPARE_BIT_55_0_SPARE_BIT_55_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_55_0_SPARE_BIT_55_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_55_0_SPARE_BIT_55_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_55_0_SPARE_BIT_55_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_56_0  
+#define FUSE_SPARE_BIT_56_0                     _MK_ADDR_CONST(0x2e0)
+#define FUSE_SPARE_BIT_56_0_SECURE                      0x0
+#define FUSE_SPARE_BIT_56_0_WORD_COUNT                  0x1
+#define FUSE_SPARE_BIT_56_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_56_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_56_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_56_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_56_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_56_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_56_0_SPARE_BIT_56_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_56_0_SPARE_BIT_56_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_56_0_SPARE_BIT_56_SHIFT)
+#define FUSE_SPARE_BIT_56_0_SPARE_BIT_56_RANGE                  0:0
+#define FUSE_SPARE_BIT_56_0_SPARE_BIT_56_WOFFSET                        0x0
+#define FUSE_SPARE_BIT_56_0_SPARE_BIT_56_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_56_0_SPARE_BIT_56_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_56_0_SPARE_BIT_56_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_56_0_SPARE_BIT_56_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_57_0  
+#define FUSE_SPARE_BIT_57_0                     _MK_ADDR_CONST(0x2e4)
+#define FUSE_SPARE_BIT_57_0_SECURE                      0x0
+#define FUSE_SPARE_BIT_57_0_WORD_COUNT                  0x1
+#define FUSE_SPARE_BIT_57_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_57_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_57_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_57_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_57_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_57_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_57_0_SPARE_BIT_57_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_57_0_SPARE_BIT_57_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_57_0_SPARE_BIT_57_SHIFT)
+#define FUSE_SPARE_BIT_57_0_SPARE_BIT_57_RANGE                  0:0
+#define FUSE_SPARE_BIT_57_0_SPARE_BIT_57_WOFFSET                        0x0
+#define FUSE_SPARE_BIT_57_0_SPARE_BIT_57_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_57_0_SPARE_BIT_57_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_57_0_SPARE_BIT_57_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_57_0_SPARE_BIT_57_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_58_0  
+#define FUSE_SPARE_BIT_58_0                     _MK_ADDR_CONST(0x2e8)
+#define FUSE_SPARE_BIT_58_0_SECURE                      0x0
+#define FUSE_SPARE_BIT_58_0_WORD_COUNT                  0x1
+#define FUSE_SPARE_BIT_58_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_58_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_58_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_58_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_58_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_58_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_58_0_SPARE_BIT_58_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_58_0_SPARE_BIT_58_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_58_0_SPARE_BIT_58_SHIFT)
+#define FUSE_SPARE_BIT_58_0_SPARE_BIT_58_RANGE                  0:0
+#define FUSE_SPARE_BIT_58_0_SPARE_BIT_58_WOFFSET                        0x0
+#define FUSE_SPARE_BIT_58_0_SPARE_BIT_58_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_58_0_SPARE_BIT_58_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_58_0_SPARE_BIT_58_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_58_0_SPARE_BIT_58_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_59_0  
+#define FUSE_SPARE_BIT_59_0                     _MK_ADDR_CONST(0x2ec)
+#define FUSE_SPARE_BIT_59_0_SECURE                      0x0
+#define FUSE_SPARE_BIT_59_0_WORD_COUNT                  0x1
+#define FUSE_SPARE_BIT_59_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_59_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_59_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_59_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_59_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_59_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_59_0_SPARE_BIT_59_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_59_0_SPARE_BIT_59_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_59_0_SPARE_BIT_59_SHIFT)
+#define FUSE_SPARE_BIT_59_0_SPARE_BIT_59_RANGE                  0:0
+#define FUSE_SPARE_BIT_59_0_SPARE_BIT_59_WOFFSET                        0x0
+#define FUSE_SPARE_BIT_59_0_SPARE_BIT_59_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_59_0_SPARE_BIT_59_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_59_0_SPARE_BIT_59_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_59_0_SPARE_BIT_59_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_60_0  
+#define FUSE_SPARE_BIT_60_0                     _MK_ADDR_CONST(0x2f0)
+#define FUSE_SPARE_BIT_60_0_SECURE                      0x0
+#define FUSE_SPARE_BIT_60_0_WORD_COUNT                  0x1
+#define FUSE_SPARE_BIT_60_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_60_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_60_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_60_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_60_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_60_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_60_0_SPARE_BIT_60_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_60_0_SPARE_BIT_60_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_60_0_SPARE_BIT_60_SHIFT)
+#define FUSE_SPARE_BIT_60_0_SPARE_BIT_60_RANGE                  0:0
+#define FUSE_SPARE_BIT_60_0_SPARE_BIT_60_WOFFSET                        0x0
+#define FUSE_SPARE_BIT_60_0_SPARE_BIT_60_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_60_0_SPARE_BIT_60_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_60_0_SPARE_BIT_60_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_60_0_SPARE_BIT_60_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_61_0  
+#define FUSE_SPARE_BIT_61_0                     _MK_ADDR_CONST(0x2f4)
+#define FUSE_SPARE_BIT_61_0_SECURE                      0x0
+#define FUSE_SPARE_BIT_61_0_WORD_COUNT                  0x1
+#define FUSE_SPARE_BIT_61_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_61_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_61_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_61_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_61_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_61_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_61_0_SPARE_BIT_61_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_61_0_SPARE_BIT_61_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_61_0_SPARE_BIT_61_SHIFT)
+#define FUSE_SPARE_BIT_61_0_SPARE_BIT_61_RANGE                  0:0
+#define FUSE_SPARE_BIT_61_0_SPARE_BIT_61_WOFFSET                        0x0
+#define FUSE_SPARE_BIT_61_0_SPARE_BIT_61_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_61_0_SPARE_BIT_61_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_61_0_SPARE_BIT_61_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_61_0_SPARE_BIT_61_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+//
+// REGISTER LIST
+//
+#define LIST_ARFUSE_REGS(_op_) \
+_op_(FUSE_FUSECTRL_0) \
+_op_(FUSE_FUSEADDR_0) \
+_op_(FUSE_FUSERDATA_0) \
+_op_(FUSE_FUSEWDATA_0) \
+_op_(FUSE_FUSETIME_RD1_0) \
+_op_(FUSE_FUSETIME_RD2_0) \
+_op_(FUSE_FUSETIME_PGM1_0) \
+_op_(FUSE_FUSETIME_PGM2_0) \
+_op_(FUSE_PRIV2INTFC_START_0) \
+_op_(FUSE_FUSEBYPASS_0) \
+_op_(FUSE_PRIVATEKEYDISABLE_0) \
+_op_(FUSE_DISABLEREGPROGRAM_0) \
+_op_(FUSE_WRITE_ACCESS_SW_0) \
+_op_(FUSE_PWR_GOOD_SW_0) \
+_op_(FUSE_REG_REF_CTRL_0) \
+_op_(FUSE_REG_BIAS_CTRL_0) \
+_op_(FUSE_PRIVATE_KEY0_NONZERO_0) \
+_op_(FUSE_PRIVATE_KEY1_NONZERO_0) \
+_op_(FUSE_PRIVATE_KEY2_NONZERO_0) \
+_op_(FUSE_PRIVATE_KEY3_NONZERO_0) \
+_op_(FUSE_PRIVATE_KEY4_NONZERO_0) \
+_op_(FUSE_PRODUCTION_MODE_0) \
+_op_(FUSE_JTAG_SECUREID_VALID_0) \
+_op_(FUSE_JTAG_SECUREID_0_0) \
+_op_(FUSE_JTAG_SECUREID_1_0) \
+_op_(FUSE_SKU_INFO_0) \
+_op_(FUSE_PROCESS_CALIB_0) \
+_op_(FUSE_IO_CALIB_0) \
+_op_(FUSE_DAC_CRT_CALIB_0) \
+_op_(FUSE_DAC_HDTV_CALIB_0) \
+_op_(FUSE_DAC_SDTV_CALIB_0) \
+_op_(FUSE_FA_0) \
+_op_(FUSE_RESERVED_PRODUCTION_0) \
+_op_(FUSE_HDMI_LANE0_CALIB_0) \
+_op_(FUSE_HDMI_LANE1_CALIB_0) \
+_op_(FUSE_HDMI_LANE2_CALIB_0) \
+_op_(FUSE_HDMI_LANE3_CALIB_0) \
+_op_(FUSE_SECURITY_MODE_0) \
+_op_(FUSE_PRIVATE_KEY0_0) \
+_op_(FUSE_PRIVATE_KEY1_0) \
+_op_(FUSE_PRIVATE_KEY2_0) \
+_op_(FUSE_PRIVATE_KEY3_0) \
+_op_(FUSE_PRIVATE_KEY4_0) \
+_op_(FUSE_ARM_DEBUG_DIS_0) \
+_op_(FUSE_BOOT_DEVICE_INFO_0) \
+_op_(FUSE_RESERVED_SW_0) \
+_op_(FUSE_ARM_DEBUG_CONTROL_0) \
+_op_(FUSE_RESERVED_ODM0_0) \
+_op_(FUSE_RESERVED_ODM1_0) \
+_op_(FUSE_RESERVED_ODM2_0) \
+_op_(FUSE_RESERVED_ODM3_0) \
+_op_(FUSE_RESERVED_ODM4_0) \
+_op_(FUSE_RESERVED_ODM5_0) \
+_op_(FUSE_RESERVED_ODM6_0) \
+_op_(FUSE_RESERVED_ODM7_0) \
+_op_(FUSE_OBS_DIS_0) \
+_op_(FUSE_NOR_INFO_0) \
+_op_(FUSE_USB_CALIB_0) \
+_op_(FUSE_KFUSE_PRIVKEY_CTRL_0) \
+_op_(FUSE_PACKAGE_INFO_0) \
+_op_(FUSE_SPARE_BIT_0_0) \
+_op_(FUSE_SPARE_BIT_1_0) \
+_op_(FUSE_SPARE_BIT_2_0) \
+_op_(FUSE_SPARE_BIT_3_0) \
+_op_(FUSE_SPARE_BIT_4_0) \
+_op_(FUSE_SPARE_BIT_5_0) \
+_op_(FUSE_SPARE_BIT_6_0) \
+_op_(FUSE_SPARE_BIT_7_0) \
+_op_(FUSE_SPARE_BIT_8_0) \
+_op_(FUSE_SPARE_BIT_9_0) \
+_op_(FUSE_SPARE_BIT_10_0) \
+_op_(FUSE_SPARE_BIT_11_0) \
+_op_(FUSE_SPARE_BIT_12_0) \
+_op_(FUSE_SPARE_BIT_13_0) \
+_op_(FUSE_SPARE_BIT_14_0) \
+_op_(FUSE_SPARE_BIT_15_0) \
+_op_(FUSE_SPARE_BIT_16_0) \
+_op_(FUSE_SPARE_BIT_17_0) \
+_op_(FUSE_SPARE_BIT_18_0) \
+_op_(FUSE_SPARE_BIT_19_0) \
+_op_(FUSE_SPARE_BIT_20_0) \
+_op_(FUSE_SPARE_BIT_21_0) \
+_op_(FUSE_SPARE_BIT_22_0) \
+_op_(FUSE_SPARE_BIT_23_0) \
+_op_(FUSE_SPARE_BIT_24_0) \
+_op_(FUSE_SPARE_BIT_25_0) \
+_op_(FUSE_SPARE_BIT_26_0) \
+_op_(FUSE_SPARE_BIT_27_0) \
+_op_(FUSE_SPARE_BIT_28_0) \
+_op_(FUSE_SPARE_BIT_29_0) \
+_op_(FUSE_SPARE_BIT_30_0) \
+_op_(FUSE_SPARE_BIT_31_0) \
+_op_(FUSE_SPARE_BIT_32_0) \
+_op_(FUSE_SPARE_BIT_33_0) \
+_op_(FUSE_SPARE_BIT_34_0) \
+_op_(FUSE_SPARE_BIT_35_0) \
+_op_(FUSE_SPARE_BIT_36_0) \
+_op_(FUSE_SPARE_BIT_37_0) \
+_op_(FUSE_SPARE_BIT_38_0) \
+_op_(FUSE_SPARE_BIT_39_0) \
+_op_(FUSE_SPARE_BIT_40_0) \
+_op_(FUSE_SPARE_BIT_41_0) \
+_op_(FUSE_SPARE_BIT_42_0) \
+_op_(FUSE_SPARE_BIT_43_0) \
+_op_(FUSE_SPARE_BIT_44_0) \
+_op_(FUSE_SPARE_BIT_45_0) \
+_op_(FUSE_SPARE_BIT_46_0) \
+_op_(FUSE_SPARE_BIT_47_0) \
+_op_(FUSE_SPARE_BIT_48_0) \
+_op_(FUSE_SPARE_BIT_49_0) \
+_op_(FUSE_SPARE_BIT_50_0) \
+_op_(FUSE_SPARE_BIT_51_0) \
+_op_(FUSE_SPARE_BIT_52_0) \
+_op_(FUSE_SPARE_BIT_53_0) \
+_op_(FUSE_SPARE_BIT_54_0) \
+_op_(FUSE_SPARE_BIT_55_0) \
+_op_(FUSE_SPARE_BIT_56_0) \
+_op_(FUSE_SPARE_BIT_57_0) \
+_op_(FUSE_SPARE_BIT_58_0) \
+_op_(FUSE_SPARE_BIT_59_0) \
+_op_(FUSE_SPARE_BIT_60_0) \
+_op_(FUSE_SPARE_BIT_61_0)
+
+
+//
+// ADDRESS SPACES
+//
+
+#define BASE_ADDRESS_FUSE       0x00000000
+
+//
+// ARFUSE REGISTER BANKS
+//
+
+#define FUSE0_FIRST_REG 0x0000 // FUSE_FUSECTRL_0
+#define FUSE0_LAST_REG 0x0034 // FUSE_PWR_GOOD_SW_0
+#define FUSE1_FIRST_REG 0x0048 // FUSE_REG_REF_CTRL_0
+#define FUSE1_LAST_REG 0x0060 // FUSE_PRIVATE_KEY4_NONZERO_0
+#define FUSE2_FIRST_REG 0x0100 // FUSE_PRODUCTION_MODE_0
+#define FUSE2_LAST_REG 0x0124 // FUSE_DAC_SDTV_CALIB_0
+#define FUSE3_FIRST_REG 0x0148 // FUSE_FA_0
+#define FUSE3_LAST_REG 0x015c // FUSE_HDMI_LANE3_CALIB_0
+#define FUSE4_FIRST_REG 0x01a0 // FUSE_SECURITY_MODE_0
+#define FUSE4_LAST_REG 0x01f0 // FUSE_USB_CALIB_0
+#define FUSE5_FIRST_REG 0x01f8 // FUSE_KFUSE_PRIVKEY_CTRL_0
+#define FUSE5_LAST_REG 0x02f4 // FUSE_SPARE_BIT_61_0
+
+#ifndef _MK_SHIFT_CONST
+  #define _MK_SHIFT_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_MASK_CONST
+  #define _MK_MASK_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_ENUM_CONST
+  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
+#endif
+#ifndef _MK_ADDR_CONST
+  #define _MK_ADDR_CONST(_constant_) _constant_
+#endif
+
+#endif // ifndef ___ARFUSE_H_INC_
diff --git a/arch/arm/mach-tegra/include/ap20/ari2c.h b/arch/arm/mach-tegra/include/ap20/ari2c.h
new file mode 100644
index 000000000000..ffe4e11f404a
--- /dev/null
+++ b/arch/arm/mach-tegra/include/ap20/ari2c.h
@@ -0,0 +1,1393 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+//
+// DO NOT EDIT - generated by simspec!
+//
+
+#ifndef ___ARI2C_H_INC_
+#define ___ARI2C_H_INC_
+
+// Register I2C_I2C_CNFG_0  
+#define I2C_I2C_CNFG_0                  _MK_ADDR_CONST(0x0)
+#define I2C_I2C_CNFG_0_SECURE                   0x0
+#define I2C_I2C_CNFG_0_WORD_COUNT                       0x1
+#define I2C_I2C_CNFG_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_RESET_MASK                       _MK_MASK_CONST(0x7fff)
+#define I2C_I2C_CNFG_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_READ_MASK                        _MK_MASK_CONST(0x7fff)
+#define I2C_I2C_CNFG_0_WRITE_MASK                       _MK_MASK_CONST(0x7fff)
+// Debounce period for sda and scl lines
+// 0 = No debounce
+// 1 = 2T
+// 2  = 4T
+// 3 =  6T etc
+// where T is the period of the fix PLL 
+//clk source coming to i2c.
+//Maximum debounce period programmable is 
+//14T.A debounce period of >50ns is desirable
+#define I2C_I2C_CNFG_0_DEBOUNCE_CNT_SHIFT                       _MK_SHIFT_CONST(12)
+#define I2C_I2C_CNFG_0_DEBOUNCE_CNT_FIELD                       (_MK_MASK_CONST(0x7) << I2C_I2C_CNFG_0_DEBOUNCE_CNT_SHIFT)
+#define I2C_I2C_CNFG_0_DEBOUNCE_CNT_RANGE                       14:12
+#define I2C_I2C_CNFG_0_DEBOUNCE_CNT_WOFFSET                     0x0
+#define I2C_I2C_CNFG_0_DEBOUNCE_CNT_DEFAULT                     _MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_DEBOUNCE_CNT_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
+#define I2C_I2C_CNFG_0_DEBOUNCE_CNT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_DEBOUNCE_CNT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Write 1 to enable new master fsm
+// 0 = old fsm
+#define I2C_I2C_CNFG_0_NEW_MASTER_FSM_SHIFT                     _MK_SHIFT_CONST(11)
+#define I2C_I2C_CNFG_0_NEW_MASTER_FSM_FIELD                     (_MK_MASK_CONST(0x1) << I2C_I2C_CNFG_0_NEW_MASTER_FSM_SHIFT)
+#define I2C_I2C_CNFG_0_NEW_MASTER_FSM_RANGE                     11:11
+#define I2C_I2C_CNFG_0_NEW_MASTER_FSM_WOFFSET                   0x0
+#define I2C_I2C_CNFG_0_NEW_MASTER_FSM_DEFAULT                   _MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_NEW_MASTER_FSM_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define I2C_I2C_CNFG_0_NEW_MASTER_FSM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_NEW_MASTER_FSM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_NEW_MASTER_FSM_DISABLE                   _MK_ENUM_CONST(0)
+#define I2C_I2C_CNFG_0_NEW_MASTER_FSM_ENABLE                    _MK_ENUM_CONST(1)
+
+// Write 1 to initiate transfer in packet mode.
+#define I2C_I2C_CNFG_0_PACKET_MODE_EN_SHIFT                     _MK_SHIFT_CONST(10)
+#define I2C_I2C_CNFG_0_PACKET_MODE_EN_FIELD                     (_MK_MASK_CONST(0x1) << I2C_I2C_CNFG_0_PACKET_MODE_EN_SHIFT)
+#define I2C_I2C_CNFG_0_PACKET_MODE_EN_RANGE                     10:10
+#define I2C_I2C_CNFG_0_PACKET_MODE_EN_WOFFSET                   0x0
+#define I2C_I2C_CNFG_0_PACKET_MODE_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_PACKET_MODE_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define I2C_I2C_CNFG_0_PACKET_MODE_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_PACKET_MODE_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_PACKET_MODE_EN_NOP                       _MK_ENUM_CONST(0)
+#define I2C_I2C_CNFG_0_PACKET_MODE_EN_GO                        _MK_ENUM_CONST(1)
+
+// Writing a 1 causes the master to initiate the
+// transaction in normal mode. Values of other  bits are not
+// affected when this bit is 1,Cleared by 
+// hardware.  Other bits of the register are
+// masked for writes when this bit is programmed
+// to one.hence,firware should first configure
+// all other registrs and  bits [8:0] of 
+// I2C_CNFG register before the bit
+// I2C_CNFG[9] is programmed to Zero.
+#define I2C_I2C_CNFG_0_SEND_SHIFT                       _MK_SHIFT_CONST(9)
+#define I2C_I2C_CNFG_0_SEND_FIELD                       (_MK_MASK_CONST(0x1) << I2C_I2C_CNFG_0_SEND_SHIFT)
+#define I2C_I2C_CNFG_0_SEND_RANGE                       9:9
+#define I2C_I2C_CNFG_0_SEND_WOFFSET                     0x0
+#define I2C_I2C_CNFG_0_SEND_DEFAULT                     _MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_SEND_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define I2C_I2C_CNFG_0_SEND_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_SEND_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_SEND_NOP                 _MK_ENUM_CONST(0)
+#define I2C_I2C_CNFG_0_SEND_GO                  _MK_ENUM_CONST(1)
+
+// Enable mode to handle devices that do not generate ACK. 
+// 1 - dont look for an ack at the end of the Enable
+#define I2C_I2C_CNFG_0_NOACK_SHIFT                      _MK_SHIFT_CONST(8)
+#define I2C_I2C_CNFG_0_NOACK_FIELD                      (_MK_MASK_CONST(0x1) << I2C_I2C_CNFG_0_NOACK_SHIFT)
+#define I2C_I2C_CNFG_0_NOACK_RANGE                      8:8
+#define I2C_I2C_CNFG_0_NOACK_WOFFSET                    0x0
+#define I2C_I2C_CNFG_0_NOACK_DEFAULT                    _MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_NOACK_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define I2C_I2C_CNFG_0_NOACK_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_NOACK_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_NOACK_DISABLE                    _MK_ENUM_CONST(0)
+#define I2C_I2C_CNFG_0_NOACK_ENABLE                     _MK_ENUM_CONST(1)
+
+// Read/Write Command for Slave 2:
+// 1 -  Read Transaction; 0 -  write Transaction.
+// For a 7-bit slave address,this bit must match
+// with the LSB of address byte for slave 2.
+// Valid only when  bit-4 of this register is 
+// set
+#define I2C_I2C_CNFG_0_CMD2_SHIFT                       _MK_SHIFT_CONST(7)
+#define I2C_I2C_CNFG_0_CMD2_FIELD                       (_MK_MASK_CONST(0x1) << I2C_I2C_CNFG_0_CMD2_SHIFT)
+#define I2C_I2C_CNFG_0_CMD2_RANGE                       7:7
+#define I2C_I2C_CNFG_0_CMD2_WOFFSET                     0x0
+#define I2C_I2C_CNFG_0_CMD2_DEFAULT                     _MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_CMD2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define I2C_I2C_CNFG_0_CMD2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_CMD2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_CMD2_DISABLE                     _MK_ENUM_CONST(0)
+#define I2C_I2C_CNFG_0_CMD2_ENABLE                      _MK_ENUM_CONST(1)
+
+// Read/Write Command for Slave 1: 
+// 1 - Read Transaction; 0 -  write Transaction.
+// Command for Slave 1: For a 7-bit slave address
+// this bit must match with the LSB of address 
+// byte for slave1.
+#define I2C_I2C_CNFG_0_CMD1_SHIFT                       _MK_SHIFT_CONST(6)
+#define I2C_I2C_CNFG_0_CMD1_FIELD                       (_MK_MASK_CONST(0x1) << I2C_I2C_CNFG_0_CMD1_SHIFT)
+#define I2C_I2C_CNFG_0_CMD1_RANGE                       6:6
+#define I2C_I2C_CNFG_0_CMD1_WOFFSET                     0x0
+#define I2C_I2C_CNFG_0_CMD1_DEFAULT                     _MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_CMD1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define I2C_I2C_CNFG_0_CMD1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_CMD1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_CMD1_DISABLE                     _MK_ENUM_CONST(0)
+#define I2C_I2C_CNFG_0_CMD1_ENABLE                      _MK_ENUM_CONST(1)
+
+//  1 = Yes, a Start byte needs to be  sent.
+#define I2C_I2C_CNFG_0_START_SHIFT                      _MK_SHIFT_CONST(5)
+#define I2C_I2C_CNFG_0_START_FIELD                      (_MK_MASK_CONST(0x1) << I2C_I2C_CNFG_0_START_SHIFT)
+#define I2C_I2C_CNFG_0_START_RANGE                      5:5
+#define I2C_I2C_CNFG_0_START_WOFFSET                    0x0
+#define I2C_I2C_CNFG_0_START_DEFAULT                    _MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_START_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define I2C_I2C_CNFG_0_START_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_START_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_START_DISABLE                    _MK_ENUM_CONST(0)
+#define I2C_I2C_CNFG_0_START_ENABLE                     _MK_ENUM_CONST(1)
+
+//  1 - Enables a two slave transaction ;
+//  0 = No command for Slave 2 present.
+#define I2C_I2C_CNFG_0_SLV2_SHIFT                       _MK_SHIFT_CONST(4)
+#define I2C_I2C_CNFG_0_SLV2_FIELD                       (_MK_MASK_CONST(0x1) << I2C_I2C_CNFG_0_SLV2_SHIFT)
+#define I2C_I2C_CNFG_0_SLV2_RANGE                       4:4
+#define I2C_I2C_CNFG_0_SLV2_WOFFSET                     0x0
+#define I2C_I2C_CNFG_0_SLV2_DEFAULT                     _MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_SLV2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define I2C_I2C_CNFG_0_SLV2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_SLV2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_SLV2_DISABLE                     _MK_ENUM_CONST(0)
+#define I2C_I2C_CNFG_0_SLV2_ENABLE                      _MK_ENUM_CONST(1)
+
+// The Number of bytes to be transmitted per
+// transaction 000= 1byte ... 111 = 8bytes;
+// In a two slave transaction number of bytes
+// should be programmed less than 011.
+#define I2C_I2C_CNFG_0_LENGTH_SHIFT                     _MK_SHIFT_CONST(1)
+#define I2C_I2C_CNFG_0_LENGTH_FIELD                     (_MK_MASK_CONST(0x7) << I2C_I2C_CNFG_0_LENGTH_SHIFT)
+#define I2C_I2C_CNFG_0_LENGTH_RANGE                     3:1
+#define I2C_I2C_CNFG_0_LENGTH_WOFFSET                   0x0
+#define I2C_I2C_CNFG_0_LENGTH_DEFAULT                   _MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_LENGTH_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define I2C_I2C_CNFG_0_LENGTH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_LENGTH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Address mode defines whether a 7-bit or a 
+// 10-bit slave address is programmed. 1 = 10-bit
+// device address 0  = 7-bit device address  
+#define I2C_I2C_CNFG_0_A_MOD_SHIFT                      _MK_SHIFT_CONST(0)
+#define I2C_I2C_CNFG_0_A_MOD_FIELD                      (_MK_MASK_CONST(0x1) << I2C_I2C_CNFG_0_A_MOD_SHIFT)
+#define I2C_I2C_CNFG_0_A_MOD_RANGE                      0:0
+#define I2C_I2C_CNFG_0_A_MOD_WOFFSET                    0x0
+#define I2C_I2C_CNFG_0_A_MOD_DEFAULT                    _MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_A_MOD_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define I2C_I2C_CNFG_0_A_MOD_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_A_MOD_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_A_MOD_SEVEN_BIT_DEVICE_ADDRESS                   _MK_ENUM_CONST(0)
+#define I2C_I2C_CNFG_0_A_MOD_TEN_BIT_DEVICE_ADDRESS                     _MK_ENUM_CONST(1)
+
+
+// Register I2C_I2C_CMD_ADDR0_0  
+#define I2C_I2C_CMD_ADDR0_0                     _MK_ADDR_CONST(0x4)
+#define I2C_I2C_CMD_ADDR0_0_SECURE                      0x0
+#define I2C_I2C_CMD_ADDR0_0_WORD_COUNT                  0x1
+#define I2C_I2C_CMD_ADDR0_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_ADDR0_0_RESET_MASK                  _MK_MASK_CONST(0x3ff)
+#define I2C_I2C_CMD_ADDR0_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_ADDR0_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_ADDR0_0_READ_MASK                   _MK_MASK_CONST(0x3ff)
+#define I2C_I2C_CMD_ADDR0_0_WRITE_MASK                  _MK_MASK_CONST(0x3ff)
+// In case of 7-Bit mode address is written in the 
+// I2C_CMD_ADDR0[7:1] and I2C_CMD_ADDR0[0] indicates the
+// read/write transaction.I2C_CMD_ADDR0[0] bit must match 
+// with the I2C_CNFG[6].
+// In case of 10-Bit mode addess is written in 
+// I2C_CMD_ADDR0[9:0] and I2C_CNFG[6]  indicates the 
+// read/write transaction. 
+#define I2C_I2C_CMD_ADDR0_0_ADDR0_SHIFT                 _MK_SHIFT_CONST(0)
+#define I2C_I2C_CMD_ADDR0_0_ADDR0_FIELD                 (_MK_MASK_CONST(0x3ff) << I2C_I2C_CMD_ADDR0_0_ADDR0_SHIFT)
+#define I2C_I2C_CMD_ADDR0_0_ADDR0_RANGE                 9:0
+#define I2C_I2C_CMD_ADDR0_0_ADDR0_WOFFSET                       0x0
+#define I2C_I2C_CMD_ADDR0_0_ADDR0_DEFAULT                       _MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_ADDR0_0_ADDR0_DEFAULT_MASK                  _MK_MASK_CONST(0x3ff)
+#define I2C_I2C_CMD_ADDR0_0_ADDR0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_ADDR0_0_ADDR0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register I2C_I2C_CMD_ADDR1_0  
+#define I2C_I2C_CMD_ADDR1_0                     _MK_ADDR_CONST(0x8)
+#define I2C_I2C_CMD_ADDR1_0_SECURE                      0x0
+#define I2C_I2C_CMD_ADDR1_0_WORD_COUNT                  0x1
+#define I2C_I2C_CMD_ADDR1_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_ADDR1_0_RESET_MASK                  _MK_MASK_CONST(0x3ff)
+#define I2C_I2C_CMD_ADDR1_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_ADDR1_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_ADDR1_0_READ_MASK                   _MK_MASK_CONST(0x3ff)
+#define I2C_I2C_CMD_ADDR1_0_WRITE_MASK                  _MK_MASK_CONST(0x3ff)
+// In case of 7-Bit mode address is written in the 
+// I2C_CMD_ADDR0[7:1] and I2C_CMD_ADDR0[0] indicates the 
+// read/write transaction.I2C_CMD_ADDR0[0] bit must match
+// with the I2C_CNFG[7].        
+// In case of 10-Bit mode addess is written in 
+// I2C_CMD_ADDR0[9:0] and I2C_CNFG[7] indicates the 
+// read/write transaction. 
+#define I2C_I2C_CMD_ADDR1_0_ADDR1_SHIFT                 _MK_SHIFT_CONST(0)
+#define I2C_I2C_CMD_ADDR1_0_ADDR1_FIELD                 (_MK_MASK_CONST(0x3ff) << I2C_I2C_CMD_ADDR1_0_ADDR1_SHIFT)
+#define I2C_I2C_CMD_ADDR1_0_ADDR1_RANGE                 9:0
+#define I2C_I2C_CMD_ADDR1_0_ADDR1_WOFFSET                       0x0
+#define I2C_I2C_CMD_ADDR1_0_ADDR1_DEFAULT                       _MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_ADDR1_0_ADDR1_DEFAULT_MASK                  _MK_MASK_CONST(0x3ff)
+#define I2C_I2C_CMD_ADDR1_0_ADDR1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_ADDR1_0_ADDR1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register I2C_I2C_CMD_DATA1_0  
+#define I2C_I2C_CMD_DATA1_0                     _MK_ADDR_CONST(0xc)
+#define I2C_I2C_CMD_DATA1_0_SECURE                      0x0
+#define I2C_I2C_CMD_DATA1_0_WORD_COUNT                  0x1
+#define I2C_I2C_CMD_DATA1_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_DATA1_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define I2C_I2C_CMD_DATA1_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_DATA1_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_DATA1_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define I2C_I2C_CMD_DATA1_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+// Fourth data byte to be sent/received
+#define I2C_I2C_CMD_DATA1_0_DATA4_SHIFT                 _MK_SHIFT_CONST(24)
+#define I2C_I2C_CMD_DATA1_0_DATA4_FIELD                 (_MK_MASK_CONST(0xff) << I2C_I2C_CMD_DATA1_0_DATA4_SHIFT)
+#define I2C_I2C_CMD_DATA1_0_DATA4_RANGE                 31:24
+#define I2C_I2C_CMD_DATA1_0_DATA4_WOFFSET                       0x0
+#define I2C_I2C_CMD_DATA1_0_DATA4_DEFAULT                       _MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_DATA1_0_DATA4_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define I2C_I2C_CMD_DATA1_0_DATA4_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_DATA1_0_DATA4_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Third data byte to be sent/received
+#define I2C_I2C_CMD_DATA1_0_DATA3_SHIFT                 _MK_SHIFT_CONST(16)
+#define I2C_I2C_CMD_DATA1_0_DATA3_FIELD                 (_MK_MASK_CONST(0xff) << I2C_I2C_CMD_DATA1_0_DATA3_SHIFT)
+#define I2C_I2C_CMD_DATA1_0_DATA3_RANGE                 23:16
+#define I2C_I2C_CMD_DATA1_0_DATA3_WOFFSET                       0x0
+#define I2C_I2C_CMD_DATA1_0_DATA3_DEFAULT                       _MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_DATA1_0_DATA3_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define I2C_I2C_CMD_DATA1_0_DATA3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_DATA1_0_DATA3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Second data byte to be sent/received
+#define I2C_I2C_CMD_DATA1_0_DATA2_SHIFT                 _MK_SHIFT_CONST(8)
+#define I2C_I2C_CMD_DATA1_0_DATA2_FIELD                 (_MK_MASK_CONST(0xff) << I2C_I2C_CMD_DATA1_0_DATA2_SHIFT)
+#define I2C_I2C_CMD_DATA1_0_DATA2_RANGE                 15:8
+#define I2C_I2C_CMD_DATA1_0_DATA2_WOFFSET                       0x0
+#define I2C_I2C_CMD_DATA1_0_DATA2_DEFAULT                       _MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_DATA1_0_DATA2_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define I2C_I2C_CMD_DATA1_0_DATA2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_DATA1_0_DATA2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// This register contains the first data byte to be  sent/received.
+#define I2C_I2C_CMD_DATA1_0_DATA1_SHIFT                 _MK_SHIFT_CONST(0)
+#define I2C_I2C_CMD_DATA1_0_DATA1_FIELD                 (_MK_MASK_CONST(0xff) << I2C_I2C_CMD_DATA1_0_DATA1_SHIFT)
+#define I2C_I2C_CMD_DATA1_0_DATA1_RANGE                 7:0
+#define I2C_I2C_CMD_DATA1_0_DATA1_WOFFSET                       0x0
+#define I2C_I2C_CMD_DATA1_0_DATA1_DEFAULT                       _MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_DATA1_0_DATA1_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define I2C_I2C_CMD_DATA1_0_DATA1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_DATA1_0_DATA1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register I2C_I2C_CMD_DATA2_0  
+#define I2C_I2C_CMD_DATA2_0                     _MK_ADDR_CONST(0x10)
+#define I2C_I2C_CMD_DATA2_0_SECURE                      0x0
+#define I2C_I2C_CMD_DATA2_0_WORD_COUNT                  0x1
+#define I2C_I2C_CMD_DATA2_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_DATA2_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define I2C_I2C_CMD_DATA2_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_DATA2_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_DATA2_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define I2C_I2C_CMD_DATA2_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+// Eighth data byte to be sent/received
+#define I2C_I2C_CMD_DATA2_0_DATA8_SHIFT                 _MK_SHIFT_CONST(24)
+#define I2C_I2C_CMD_DATA2_0_DATA8_FIELD                 (_MK_MASK_CONST(0xff) << I2C_I2C_CMD_DATA2_0_DATA8_SHIFT)
+#define I2C_I2C_CMD_DATA2_0_DATA8_RANGE                 31:24
+#define I2C_I2C_CMD_DATA2_0_DATA8_WOFFSET                       0x0
+#define I2C_I2C_CMD_DATA2_0_DATA8_DEFAULT                       _MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_DATA2_0_DATA8_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define I2C_I2C_CMD_DATA2_0_DATA8_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_DATA2_0_DATA8_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Seventh data byte to be sent/received
+#define I2C_I2C_CMD_DATA2_0_DATA7_SHIFT                 _MK_SHIFT_CONST(16)
+#define I2C_I2C_CMD_DATA2_0_DATA7_FIELD                 (_MK_MASK_CONST(0xff) << I2C_I2C_CMD_DATA2_0_DATA7_SHIFT)
+#define I2C_I2C_CMD_DATA2_0_DATA7_RANGE                 23:16
+#define I2C_I2C_CMD_DATA2_0_DATA7_WOFFSET                       0x0
+#define I2C_I2C_CMD_DATA2_0_DATA7_DEFAULT                       _MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_DATA2_0_DATA7_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define I2C_I2C_CMD_DATA2_0_DATA7_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_DATA2_0_DATA7_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Sixth data byte to be sent/received
+#define I2C_I2C_CMD_DATA2_0_DATA6_SHIFT                 _MK_SHIFT_CONST(8)
+#define I2C_I2C_CMD_DATA2_0_DATA6_FIELD                 (_MK_MASK_CONST(0xff) << I2C_I2C_CMD_DATA2_0_DATA6_SHIFT)
+#define I2C_I2C_CMD_DATA2_0_DATA6_RANGE                 15:8
+#define I2C_I2C_CMD_DATA2_0_DATA6_WOFFSET                       0x0
+#define I2C_I2C_CMD_DATA2_0_DATA6_DEFAULT                       _MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_DATA2_0_DATA6_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define I2C_I2C_CMD_DATA2_0_DATA6_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_DATA2_0_DATA6_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// This register contains the Fifth data byte to be  sent/received.
+#define I2C_I2C_CMD_DATA2_0_DATA5_SHIFT                 _MK_SHIFT_CONST(0)
+#define I2C_I2C_CMD_DATA2_0_DATA5_FIELD                 (_MK_MASK_CONST(0xff) << I2C_I2C_CMD_DATA2_0_DATA5_SHIFT)
+#define I2C_I2C_CMD_DATA2_0_DATA5_RANGE                 7:0
+#define I2C_I2C_CMD_DATA2_0_DATA5_WOFFSET                       0x0
+#define I2C_I2C_CMD_DATA2_0_DATA5_DEFAULT                       _MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_DATA2_0_DATA5_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define I2C_I2C_CMD_DATA2_0_DATA5_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_DATA2_0_DATA5_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Reserved address 20 [0x14] 
+
+// Reserved address 24 [0x18] 
+
+// Register I2C_I2C_STATUS_0  
+#define I2C_I2C_STATUS_0                        _MK_ADDR_CONST(0x1c)
+#define I2C_I2C_STATUS_0_SECURE                         0x0
+#define I2C_I2C_STATUS_0_WORD_COUNT                     0x1
+#define I2C_I2C_STATUS_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define I2C_I2C_STATUS_0_RESET_MASK                     _MK_MASK_CONST(0x1ff)
+#define I2C_I2C_STATUS_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define I2C_I2C_STATUS_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define I2C_I2C_STATUS_0_READ_MASK                      _MK_MASK_CONST(0x1ff)
+#define I2C_I2C_STATUS_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
+//  1 = Busy.
+#define I2C_I2C_STATUS_0_BUSY_SHIFT                     _MK_SHIFT_CONST(8)
+#define I2C_I2C_STATUS_0_BUSY_FIELD                     (_MK_MASK_CONST(0x1) << I2C_I2C_STATUS_0_BUSY_SHIFT)
+#define I2C_I2C_STATUS_0_BUSY_RANGE                     8:8
+#define I2C_I2C_STATUS_0_BUSY_WOFFSET                   0x0
+#define I2C_I2C_STATUS_0_BUSY_DEFAULT                   _MK_MASK_CONST(0x0)
+#define I2C_I2C_STATUS_0_BUSY_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define I2C_I2C_STATUS_0_BUSY_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define I2C_I2C_STATUS_0_BUSY_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define I2C_I2C_STATUS_0_BUSY_NOT_BUSY                  _MK_ENUM_CONST(0)
+#define I2C_I2C_STATUS_0_BUSY_BUSY                      _MK_ENUM_CONST(1)
+
+// Transaction for Slave2 for x byte failed. x is 'h0 to 'ha.
+// all others invalid 
+#define I2C_I2C_STATUS_0_CMD2_STAT_SHIFT                        _MK_SHIFT_CONST(4)
+#define I2C_I2C_STATUS_0_CMD2_STAT_FIELD                        (_MK_MASK_CONST(0xf) << I2C_I2C_STATUS_0_CMD2_STAT_SHIFT)
+#define I2C_I2C_STATUS_0_CMD2_STAT_RANGE                        7:4
+#define I2C_I2C_STATUS_0_CMD2_STAT_WOFFSET                      0x0
+#define I2C_I2C_STATUS_0_CMD2_STAT_DEFAULT                      _MK_MASK_CONST(0x0)
+#define I2C_I2C_STATUS_0_CMD2_STAT_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define I2C_I2C_STATUS_0_CMD2_STAT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define I2C_I2C_STATUS_0_CMD2_STAT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define I2C_I2C_STATUS_0_CMD2_STAT_SL2_XFER_SUCCESSFUL                  _MK_ENUM_CONST(0)
+#define I2C_I2C_STATUS_0_CMD2_STAT_SL2_NOACK_FOR_BYTE1                  _MK_ENUM_CONST(1)
+#define I2C_I2C_STATUS_0_CMD2_STAT_SL2_NOACK_FOR_BYTE2                  _MK_ENUM_CONST(2)
+#define I2C_I2C_STATUS_0_CMD2_STAT_SL2_NOACK_FOR_BYTE3                  _MK_ENUM_CONST(3)
+#define I2C_I2C_STATUS_0_CMD2_STAT_SL2_NOACK_FOR_BYTE4                  _MK_ENUM_CONST(4)
+#define I2C_I2C_STATUS_0_CMD2_STAT_SL2_NOACK_FOR_BYTE5                  _MK_ENUM_CONST(5)
+#define I2C_I2C_STATUS_0_CMD2_STAT_SL2_NOACK_FOR_BYTE6                  _MK_ENUM_CONST(6)
+#define I2C_I2C_STATUS_0_CMD2_STAT_SL2_NOACK_FOR_BYTE7                  _MK_ENUM_CONST(7)
+#define I2C_I2C_STATUS_0_CMD2_STAT_SL2_NOACK_FOR_BYTE8                  _MK_ENUM_CONST(8)
+#define I2C_I2C_STATUS_0_CMD2_STAT_SL2_NOACK_FOR_BYTE9                  _MK_ENUM_CONST(9)
+#define I2C_I2C_STATUS_0_CMD2_STAT_SL2_NOACK_FOR_BYTE10                 _MK_ENUM_CONST(10)
+
+// Transaction for Slave1 for x byte failed. x is 'h0 to 'ha.
+// all others invalid
+#define I2C_I2C_STATUS_0_CMD1_STAT_SHIFT                        _MK_SHIFT_CONST(0)
+#define I2C_I2C_STATUS_0_CMD1_STAT_FIELD                        (_MK_MASK_CONST(0xf) << I2C_I2C_STATUS_0_CMD1_STAT_SHIFT)
+#define I2C_I2C_STATUS_0_CMD1_STAT_RANGE                        3:0
+#define I2C_I2C_STATUS_0_CMD1_STAT_WOFFSET                      0x0
+#define I2C_I2C_STATUS_0_CMD1_STAT_DEFAULT                      _MK_MASK_CONST(0x0)
+#define I2C_I2C_STATUS_0_CMD1_STAT_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define I2C_I2C_STATUS_0_CMD1_STAT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define I2C_I2C_STATUS_0_CMD1_STAT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define I2C_I2C_STATUS_0_CMD1_STAT_SL1_XFER_SUCCESSFUL                  _MK_ENUM_CONST(0)
+#define I2C_I2C_STATUS_0_CMD1_STAT_SL1_NOACK_FOR_BYTE1                  _MK_ENUM_CONST(1)
+#define I2C_I2C_STATUS_0_CMD1_STAT_SL1_NOACK_FOR_BYTE2                  _MK_ENUM_CONST(2)
+#define I2C_I2C_STATUS_0_CMD1_STAT_SL1_NOACK_FOR_BYTE3                  _MK_ENUM_CONST(3)
+#define I2C_I2C_STATUS_0_CMD1_STAT_SL1_NOACK_FOR_BYTE4                  _MK_ENUM_CONST(4)
+#define I2C_I2C_STATUS_0_CMD1_STAT_SL1_NOACK_FOR_BYTE5                  _MK_ENUM_CONST(5)
+#define I2C_I2C_STATUS_0_CMD1_STAT_SL1_NOACK_FOR_BYTE6                  _MK_ENUM_CONST(6)
+#define I2C_I2C_STATUS_0_CMD1_STAT_SL1_NOACK_FOR_BYTE7                  _MK_ENUM_CONST(7)
+#define I2C_I2C_STATUS_0_CMD1_STAT_SL1_NOACK_FOR_BYTE8                  _MK_ENUM_CONST(8)
+#define I2C_I2C_STATUS_0_CMD1_STAT_SL1_NOACK_FOR_BYTE9                  _MK_ENUM_CONST(9)
+#define I2C_I2C_STATUS_0_CMD1_STAT_SL1_NOACK_FOR_BYTE10                 _MK_ENUM_CONST(10)
+
+
+// Register I2C_I2C_SL_CNFG_0  
+#define I2C_I2C_SL_CNFG_0                       _MK_ADDR_CONST(0x20)
+#define I2C_I2C_SL_CNFG_0_SECURE                        0x0
+#define I2C_I2C_SL_CNFG_0_WORD_COUNT                    0x1
+#define I2C_I2C_SL_CNFG_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_CNFG_0_RESET_MASK                    _MK_MASK_CONST(0x7)
+#define I2C_I2C_SL_CNFG_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_CNFG_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_CNFG_0_READ_MASK                     _MK_MASK_CONST(0x7)
+#define I2C_I2C_SL_CNFG_0_WRITE_MASK                    _MK_MASK_CONST(0x7)
+// New Slave
+// 1 - use new slave
+#define I2C_I2C_SL_CNFG_0_NEWSL_SHIFT                   _MK_SHIFT_CONST(2)
+#define I2C_I2C_SL_CNFG_0_NEWSL_FIELD                   (_MK_MASK_CONST(0x1) << I2C_I2C_SL_CNFG_0_NEWSL_SHIFT)
+#define I2C_I2C_SL_CNFG_0_NEWSL_RANGE                   2:2
+#define I2C_I2C_SL_CNFG_0_NEWSL_WOFFSET                 0x0
+#define I2C_I2C_SL_CNFG_0_NEWSL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_CNFG_0_NEWSL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define I2C_I2C_SL_CNFG_0_NEWSL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_CNFG_0_NEWSL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_CNFG_0_NEWSL_DISABLE                 _MK_ENUM_CONST(0)
+#define I2C_I2C_SL_CNFG_0_NEWSL_ENABLE                  _MK_ENUM_CONST(1)
+
+// Disable Slave Ack. 
+// 1 - slave will not ack reception of address or data byte. 
+#define I2C_I2C_SL_CNFG_0_NACK_SHIFT                    _MK_SHIFT_CONST(1)
+#define I2C_I2C_SL_CNFG_0_NACK_FIELD                    (_MK_MASK_CONST(0x1) << I2C_I2C_SL_CNFG_0_NACK_SHIFT)
+#define I2C_I2C_SL_CNFG_0_NACK_RANGE                    1:1
+#define I2C_I2C_SL_CNFG_0_NACK_WOFFSET                  0x0
+#define I2C_I2C_SL_CNFG_0_NACK_DEFAULT                  _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_CNFG_0_NACK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define I2C_I2C_SL_CNFG_0_NACK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_CNFG_0_NACK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_CNFG_0_NACK_DISABLE                  _MK_ENUM_CONST(0)
+#define I2C_I2C_SL_CNFG_0_NACK_ENABLE                   _MK_ENUM_CONST(1)
+
+// Slave response to general call address (zero address) 
+// 1 - Enable.
+#define I2C_I2C_SL_CNFG_0_RESP_SHIFT                    _MK_SHIFT_CONST(0)
+#define I2C_I2C_SL_CNFG_0_RESP_FIELD                    (_MK_MASK_CONST(0x1) << I2C_I2C_SL_CNFG_0_RESP_SHIFT)
+#define I2C_I2C_SL_CNFG_0_RESP_RANGE                    0:0
+#define I2C_I2C_SL_CNFG_0_RESP_WOFFSET                  0x0
+#define I2C_I2C_SL_CNFG_0_RESP_DEFAULT                  _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_CNFG_0_RESP_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define I2C_I2C_SL_CNFG_0_RESP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_CNFG_0_RESP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_CNFG_0_RESP_DISABLE                  _MK_ENUM_CONST(0)
+#define I2C_I2C_SL_CNFG_0_RESP_ENABLE                   _MK_ENUM_CONST(1)
+
+
+// Register I2C_I2C_SL_RCVD_0  
+#define I2C_I2C_SL_RCVD_0                       _MK_ADDR_CONST(0x24)
+#define I2C_I2C_SL_RCVD_0_SECURE                        0x0
+#define I2C_I2C_SL_RCVD_0_WORD_COUNT                    0x1
+#define I2C_I2C_SL_RCVD_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_RCVD_0_RESET_MASK                    _MK_MASK_CONST(0xff)
+#define I2C_I2C_SL_RCVD_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_RCVD_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_RCVD_0_READ_MASK                     _MK_MASK_CONST(0xff)
+#define I2C_I2C_SL_RCVD_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
+//slave Received data 
+#define I2C_I2C_SL_RCVD_0_SL_DATA_SHIFT                 _MK_SHIFT_CONST(0)
+#define I2C_I2C_SL_RCVD_0_SL_DATA_FIELD                 (_MK_MASK_CONST(0xff) << I2C_I2C_SL_RCVD_0_SL_DATA_SHIFT)
+#define I2C_I2C_SL_RCVD_0_SL_DATA_RANGE                 7:0
+#define I2C_I2C_SL_RCVD_0_SL_DATA_WOFFSET                       0x0
+#define I2C_I2C_SL_RCVD_0_SL_DATA_DEFAULT                       _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_RCVD_0_SL_DATA_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define I2C_I2C_SL_RCVD_0_SL_DATA_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_RCVD_0_SL_DATA_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register I2C_I2C_SL_STATUS_0  
+#define I2C_I2C_SL_STATUS_0                     _MK_ADDR_CONST(0x28)
+#define I2C_I2C_SL_STATUS_0_SECURE                      0x0
+#define I2C_I2C_SL_STATUS_0_WORD_COUNT                  0x1
+#define I2C_I2C_SL_STATUS_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_STATUS_0_RESET_MASK                  _MK_MASK_CONST(0x7fff)
+#define I2C_I2C_SL_STATUS_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_STATUS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_STATUS_0_READ_MASK                   _MK_MASK_CONST(0x7fff)
+#define I2C_I2C_SL_STATUS_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+//  HW master addr received via general call addressing.
+//  This field is meaningful only if HW_MSTR_INT is set.
+#define I2C_I2C_SL_STATUS_0_HW_MSTR_ADR_SHIFT                   _MK_SHIFT_CONST(8)
+#define I2C_I2C_SL_STATUS_0_HW_MSTR_ADR_FIELD                   (_MK_MASK_CONST(0x7f) << I2C_I2C_SL_STATUS_0_HW_MSTR_ADR_SHIFT)
+#define I2C_I2C_SL_STATUS_0_HW_MSTR_ADR_RANGE                   14:8
+#define I2C_I2C_SL_STATUS_0_HW_MSTR_ADR_WOFFSET                 0x0
+#define I2C_I2C_SL_STATUS_0_HW_MSTR_ADR_DEFAULT                 _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_STATUS_0_HW_MSTR_ADR_DEFAULT_MASK                    _MK_MASK_CONST(0x7f)
+#define I2C_I2C_SL_STATUS_0_HW_MSTR_ADR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_STATUS_0_HW_MSTR_ADR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+//  1 = Interrupt has been generated by  slave  
+//  Hardware Master Address is received after
+//  General Call Address.
+//  1 = Received HW Master Address
+//  0 = No event.
+#define I2C_I2C_SL_STATUS_0_HW_MSTR_INT_SHIFT                   _MK_SHIFT_CONST(7)
+#define I2C_I2C_SL_STATUS_0_HW_MSTR_INT_FIELD                   (_MK_MASK_CONST(0x1) << I2C_I2C_SL_STATUS_0_HW_MSTR_INT_SHIFT)
+#define I2C_I2C_SL_STATUS_0_HW_MSTR_INT_RANGE                   7:7
+#define I2C_I2C_SL_STATUS_0_HW_MSTR_INT_WOFFSET                 0x0
+#define I2C_I2C_SL_STATUS_0_HW_MSTR_INT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_STATUS_0_HW_MSTR_INT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define I2C_I2C_SL_STATUS_0_HW_MSTR_INT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_STATUS_0_HW_MSTR_INT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+//  1 = Interrupt has been generated by  slave  
+//  By after General Call Address is 0x04.
+//  1 = Reprogram slave address.
+//  0 = No action.
+#define I2C_I2C_SL_STATUS_0_REPROG_SL_SHIFT                     _MK_SHIFT_CONST(6)
+#define I2C_I2C_SL_STATUS_0_REPROG_SL_FIELD                     (_MK_MASK_CONST(0x1) << I2C_I2C_SL_STATUS_0_REPROG_SL_SHIFT)
+#define I2C_I2C_SL_STATUS_0_REPROG_SL_RANGE                     6:6
+#define I2C_I2C_SL_STATUS_0_REPROG_SL_WOFFSET                   0x0
+#define I2C_I2C_SL_STATUS_0_REPROG_SL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_STATUS_0_REPROG_SL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define I2C_I2C_SL_STATUS_0_REPROG_SL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_STATUS_0_REPROG_SL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+//  1 = Interrupt has been generated by  slave  
+//  By after General Call Address is 0x06.
+//  1 = Reset and reprogram slave address.
+//  0 = No action.
+#define I2C_I2C_SL_STATUS_0_RST_SL_SHIFT                        _MK_SHIFT_CONST(5)
+#define I2C_I2C_SL_STATUS_0_RST_SL_FIELD                        (_MK_MASK_CONST(0x1) << I2C_I2C_SL_STATUS_0_RST_SL_SHIFT)
+#define I2C_I2C_SL_STATUS_0_RST_SL_RANGE                        5:5
+#define I2C_I2C_SL_STATUS_0_RST_SL_WOFFSET                      0x0
+#define I2C_I2C_SL_STATUS_0_RST_SL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_STATUS_0_RST_SL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define I2C_I2C_SL_STATUS_0_RST_SL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_STATUS_0_RST_SL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+//  1 = Interrupt has been generated by  slave  
+//  Transaction completed as indicated by stop/repeat start condition.
+//  1 = Transaction completed.
+//  0 = No transaction occurred  or transaction in progress.
+#define I2C_I2C_SL_STATUS_0_END_TRANS_SHIFT                     _MK_SHIFT_CONST(4)
+#define I2C_I2C_SL_STATUS_0_END_TRANS_FIELD                     (_MK_MASK_CONST(0x1) << I2C_I2C_SL_STATUS_0_END_TRANS_SHIFT)
+#define I2C_I2C_SL_STATUS_0_END_TRANS_RANGE                     4:4
+#define I2C_I2C_SL_STATUS_0_END_TRANS_WOFFSET                   0x0
+#define I2C_I2C_SL_STATUS_0_END_TRANS_DEFAULT                   _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_STATUS_0_END_TRANS_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define I2C_I2C_SL_STATUS_0_END_TRANS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_STATUS_0_END_TRANS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+//  1 = Interrupt has been generated by  slave  
+//  0 = No interrupt generated  
+#define I2C_I2C_SL_STATUS_0_SL_IRQ_SHIFT                        _MK_SHIFT_CONST(3)
+#define I2C_I2C_SL_STATUS_0_SL_IRQ_FIELD                        (_MK_MASK_CONST(0x1) << I2C_I2C_SL_STATUS_0_SL_IRQ_SHIFT)
+#define I2C_I2C_SL_STATUS_0_SL_IRQ_RANGE                        3:3
+#define I2C_I2C_SL_STATUS_0_SL_IRQ_WOFFSET                      0x0
+#define I2C_I2C_SL_STATUS_0_SL_IRQ_DEFAULT                      _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_STATUS_0_SL_IRQ_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define I2C_I2C_SL_STATUS_0_SL_IRQ_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_STATUS_0_SL_IRQ_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_STATUS_0_SL_IRQ_UNSET                        _MK_ENUM_CONST(0)
+#define I2C_I2C_SL_STATUS_0_SL_IRQ_SET                  _MK_ENUM_CONST(1)
+
+//  New Transaction Receieved status
+//  1 = Transaction occurred. 
+//  0  = No transaction occurred 
+#define I2C_I2C_SL_STATUS_0_RCVD_SHIFT                  _MK_SHIFT_CONST(2)
+#define I2C_I2C_SL_STATUS_0_RCVD_FIELD                  (_MK_MASK_CONST(0x1) << I2C_I2C_SL_STATUS_0_RCVD_SHIFT)
+#define I2C_I2C_SL_STATUS_0_RCVD_RANGE                  2:2
+#define I2C_I2C_SL_STATUS_0_RCVD_WOFFSET                        0x0
+#define I2C_I2C_SL_STATUS_0_RCVD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_STATUS_0_RCVD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define I2C_I2C_SL_STATUS_0_RCVD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_STATUS_0_RCVD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_STATUS_0_RCVD_NO_TRANSACTION_OCCURED                 _MK_ENUM_CONST(0)
+#define I2C_I2C_SL_STATUS_0_RCVD_TRANSACTION_OCCURED                    _MK_ENUM_CONST(1)
+
+//  Slave Transaction status 
+//  0 = Write
+//  1=Read
+#define I2C_I2C_SL_STATUS_0_RNW_SHIFT                   _MK_SHIFT_CONST(1)
+#define I2C_I2C_SL_STATUS_0_RNW_FIELD                   (_MK_MASK_CONST(0x1) << I2C_I2C_SL_STATUS_0_RNW_SHIFT)
+#define I2C_I2C_SL_STATUS_0_RNW_RANGE                   1:1
+#define I2C_I2C_SL_STATUS_0_RNW_WOFFSET                 0x0
+#define I2C_I2C_SL_STATUS_0_RNW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_STATUS_0_RNW_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define I2C_I2C_SL_STATUS_0_RNW_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_STATUS_0_RNW_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_STATUS_0_RNW_WRITE                   _MK_ENUM_CONST(0)
+#define I2C_I2C_SL_STATUS_0_RNW_READ                    _MK_ENUM_CONST(1)
+
+//  Zero Address Status
+//  1 = Yes, slave responded  
+//  0  = No, slave did not respond
+#define I2C_I2C_SL_STATUS_0_ZA_SHIFT                    _MK_SHIFT_CONST(0)
+#define I2C_I2C_SL_STATUS_0_ZA_FIELD                    (_MK_MASK_CONST(0x1) << I2C_I2C_SL_STATUS_0_ZA_SHIFT)
+#define I2C_I2C_SL_STATUS_0_ZA_RANGE                    0:0
+#define I2C_I2C_SL_STATUS_0_ZA_WOFFSET                  0x0
+#define I2C_I2C_SL_STATUS_0_ZA_DEFAULT                  _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_STATUS_0_ZA_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define I2C_I2C_SL_STATUS_0_ZA_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_STATUS_0_ZA_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_STATUS_0_ZA_NO_SLAVE_RESPONSE                        _MK_ENUM_CONST(0)
+#define I2C_I2C_SL_STATUS_0_ZA_SLAVE_RESPONSE                   _MK_ENUM_CONST(1)
+
+
+// Register I2C_I2C_SL_ADDR1_0  
+#define I2C_I2C_SL_ADDR1_0                      _MK_ADDR_CONST(0x2c)
+#define I2C_I2C_SL_ADDR1_0_SECURE                       0x0
+#define I2C_I2C_SL_ADDR1_0_WORD_COUNT                   0x1
+#define I2C_I2C_SL_ADDR1_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_ADDR1_0_RESET_MASK                   _MK_MASK_CONST(0xff)
+#define I2C_I2C_SL_ADDR1_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_ADDR1_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_ADDR1_0_READ_MASK                    _MK_MASK_CONST(0xff)
+#define I2C_I2C_SL_ADDR1_0_WRITE_MASK                   _MK_MASK_CONST(0xff)
+//   For a 10-bit slave address, this field is the least significant 8 bits. 
+#define I2C_I2C_SL_ADDR1_0_SL_ADDR0_SHIFT                       _MK_SHIFT_CONST(0)
+#define I2C_I2C_SL_ADDR1_0_SL_ADDR0_FIELD                       (_MK_MASK_CONST(0xff) << I2C_I2C_SL_ADDR1_0_SL_ADDR0_SHIFT)
+#define I2C_I2C_SL_ADDR1_0_SL_ADDR0_RANGE                       7:0
+#define I2C_I2C_SL_ADDR1_0_SL_ADDR0_WOFFSET                     0x0
+#define I2C_I2C_SL_ADDR1_0_SL_ADDR0_DEFAULT                     _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_ADDR1_0_SL_ADDR0_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define I2C_I2C_SL_ADDR1_0_SL_ADDR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_ADDR1_0_SL_ADDR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register I2C_I2C_SL_ADDR2_0  
+#define I2C_I2C_SL_ADDR2_0                      _MK_ADDR_CONST(0x30)
+#define I2C_I2C_SL_ADDR2_0_SECURE                       0x0
+#define I2C_I2C_SL_ADDR2_0_WORD_COUNT                   0x1
+#define I2C_I2C_SL_ADDR2_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_ADDR2_0_RESET_MASK                   _MK_MASK_CONST(0x7)
+#define I2C_I2C_SL_ADDR2_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_ADDR2_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_ADDR2_0_READ_MASK                    _MK_MASK_CONST(0x7)
+#define I2C_I2C_SL_ADDR2_0_WRITE_MASK                   _MK_MASK_CONST(0x7)
+// In 7 bit address mode these bits are dont care;
+// In 10 bit address mode they represent the 2 MSB of the address.
+#define I2C_I2C_SL_ADDR2_0_SL_ADDR_HI_SHIFT                     _MK_SHIFT_CONST(1)
+#define I2C_I2C_SL_ADDR2_0_SL_ADDR_HI_FIELD                     (_MK_MASK_CONST(0x3) << I2C_I2C_SL_ADDR2_0_SL_ADDR_HI_SHIFT)
+#define I2C_I2C_SL_ADDR2_0_SL_ADDR_HI_RANGE                     2:1
+#define I2C_I2C_SL_ADDR2_0_SL_ADDR_HI_WOFFSET                   0x0
+#define I2C_I2C_SL_ADDR2_0_SL_ADDR_HI_DEFAULT                   _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_ADDR2_0_SL_ADDR_HI_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define I2C_I2C_SL_ADDR2_0_SL_ADDR_HI_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_ADDR2_0_SL_ADDR_HI_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// 0 = 7-bit addressing.
+// 1 - 10 bit addressing.  
+#define I2C_I2C_SL_ADDR2_0_VLD_SHIFT                    _MK_SHIFT_CONST(0)
+#define I2C_I2C_SL_ADDR2_0_VLD_FIELD                    (_MK_MASK_CONST(0x1) << I2C_I2C_SL_ADDR2_0_VLD_SHIFT)
+#define I2C_I2C_SL_ADDR2_0_VLD_RANGE                    0:0
+#define I2C_I2C_SL_ADDR2_0_VLD_WOFFSET                  0x0
+#define I2C_I2C_SL_ADDR2_0_VLD_DEFAULT                  _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_ADDR2_0_VLD_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define I2C_I2C_SL_ADDR2_0_VLD_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_ADDR2_0_VLD_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_ADDR2_0_VLD_SEVEN_BIT_ADDR_MODE                      _MK_ENUM_CONST(0)
+#define I2C_I2C_SL_ADDR2_0_VLD_TEN_BIT_ADDR_MODE                        _MK_ENUM_CONST(1)
+
+
+// Reserved address 52 [0x34] 
+
+// Reserved address 56 [0x38] 
+
+// Register I2C_I2C_SL_DELAY_COUNT_0  
+#define I2C_I2C_SL_DELAY_COUNT_0                        _MK_ADDR_CONST(0x3c)
+#define I2C_I2C_SL_DELAY_COUNT_0_SECURE                         0x0
+#define I2C_I2C_SL_DELAY_COUNT_0_WORD_COUNT                     0x1
+#define I2C_I2C_SL_DELAY_COUNT_0_RESET_VAL                      _MK_MASK_CONST(0x1e)
+#define I2C_I2C_SL_DELAY_COUNT_0_RESET_MASK                     _MK_MASK_CONST(0xffff)
+#define I2C_I2C_SL_DELAY_COUNT_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_DELAY_COUNT_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_DELAY_COUNT_0_READ_MASK                      _MK_MASK_CONST(0xffff)
+#define I2C_I2C_SL_DELAY_COUNT_0_WRITE_MASK                     _MK_MASK_CONST(0xffff)
+// The value determines the timing  between an address 
+// cycle and a subsequent data cycle or two consecutive 
+// data  cycles on the bus.The I2C_SL_DELAY_COUNT is valid
+// only when internal slave is accessed.
+// I2C_SL_DELAY_COUNT has to be programmed such that 
+// TIMING = T * DLY where T is period of clock source
+// selected for I2c; and DLY is I2C_SL_DELAY_COUNT ;
+// TIMING is the desired timing, A value of >= 1250 ns is
+// advisable.
+#define I2C_I2C_SL_DELAY_COUNT_0_SL_DELAY_COUNT_SHIFT                   _MK_SHIFT_CONST(0)
+#define I2C_I2C_SL_DELAY_COUNT_0_SL_DELAY_COUNT_FIELD                   (_MK_MASK_CONST(0xffff) << I2C_I2C_SL_DELAY_COUNT_0_SL_DELAY_COUNT_SHIFT)
+#define I2C_I2C_SL_DELAY_COUNT_0_SL_DELAY_COUNT_RANGE                   15:0
+#define I2C_I2C_SL_DELAY_COUNT_0_SL_DELAY_COUNT_WOFFSET                 0x0
+#define I2C_I2C_SL_DELAY_COUNT_0_SL_DELAY_COUNT_DEFAULT                 _MK_MASK_CONST(0x1e)
+#define I2C_I2C_SL_DELAY_COUNT_0_SL_DELAY_COUNT_DEFAULT_MASK                    _MK_MASK_CONST(0xffff)
+#define I2C_I2C_SL_DELAY_COUNT_0_SL_DELAY_COUNT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_DELAY_COUNT_0_SL_DELAY_COUNT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Reserved address 64 [0x40] 
+
+// Reserved address 68 [0x44] 
+
+// Reserved address 72 [0x48] 
+
+// Reserved address 76 [0x4c] 
+
+// Packet I2C_IO_PACKET_HEADER_0
+#define I2C_IO_PACKET_HEADER_0_SIZE 32
+
+#define I2C_IO_PACKET_HEADER_0_RESERVED0_3_SHIFT                        _MK_SHIFT_CONST(30)
+#define I2C_IO_PACKET_HEADER_0_RESERVED0_3_FIELD                        (_MK_MASK_CONST(0x3) << I2C_IO_PACKET_HEADER_0_RESERVED0_3_SHIFT)
+#define I2C_IO_PACKET_HEADER_0_RESERVED0_3_RANGE                        _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(30)
+#define I2C_IO_PACKET_HEADER_0_RESERVED0_3_ROW                  0
+
+#define I2C_IO_PACKET_HEADER_0_HDRSZ_SHIFT                      _MK_SHIFT_CONST(28)
+#define I2C_IO_PACKET_HEADER_0_HDRSZ_FIELD                      (_MK_MASK_CONST(0x3) << I2C_IO_PACKET_HEADER_0_HDRSZ_SHIFT)
+#define I2C_IO_PACKET_HEADER_0_HDRSZ_RANGE                      _MK_SHIFT_CONST(29):_MK_SHIFT_CONST(28)
+#define I2C_IO_PACKET_HEADER_0_HDRSZ_ROW                        0
+#define I2C_IO_PACKET_HEADER_0_HDRSZ_ONE                        _MK_ENUM_CONST(0)
+#define I2C_IO_PACKET_HEADER_0_HDRSZ_TWO                        _MK_ENUM_CONST(1)
+#define I2C_IO_PACKET_HEADER_0_HDRSZ_THREE                      _MK_ENUM_CONST(2)
+#define I2C_IO_PACKET_HEADER_0_HDRSZ_FOUR                       _MK_ENUM_CONST(3)
+
+#define I2C_IO_PACKET_HEADER_0_RESERVED0_2_SHIFT                        _MK_SHIFT_CONST(24)
+#define I2C_IO_PACKET_HEADER_0_RESERVED0_2_FIELD                        (_MK_MASK_CONST(0xf) << I2C_IO_PACKET_HEADER_0_RESERVED0_2_SHIFT)
+#define I2C_IO_PACKET_HEADER_0_RESERVED0_2_RANGE                        _MK_SHIFT_CONST(27):_MK_SHIFT_CONST(24)
+#define I2C_IO_PACKET_HEADER_0_RESERVED0_2_ROW                  0
+
+#define I2C_IO_PACKET_HEADER_0_PKTID_SHIFT                      _MK_SHIFT_CONST(16)
+#define I2C_IO_PACKET_HEADER_0_PKTID_FIELD                      (_MK_MASK_CONST(0xff) << I2C_IO_PACKET_HEADER_0_PKTID_SHIFT)
+#define I2C_IO_PACKET_HEADER_0_PKTID_RANGE                      _MK_SHIFT_CONST(23):_MK_SHIFT_CONST(16)
+#define I2C_IO_PACKET_HEADER_0_PKTID_ROW                        0
+
+#define I2C_IO_PACKET_HEADER_0_CONTROLLER_ID_SHIFT                      _MK_SHIFT_CONST(12)
+#define I2C_IO_PACKET_HEADER_0_CONTROLLER_ID_FIELD                      (_MK_MASK_CONST(0xf) << I2C_IO_PACKET_HEADER_0_CONTROLLER_ID_SHIFT)
+#define I2C_IO_PACKET_HEADER_0_CONTROLLER_ID_RANGE                      _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(12)
+#define I2C_IO_PACKET_HEADER_0_CONTROLLER_ID_ROW                        0
+#define I2C_IO_PACKET_HEADER_0_CONTROLLER_ID_I2C1                       _MK_ENUM_CONST(0)
+#define I2C_IO_PACKET_HEADER_0_CONTROLLER_ID_I2C2                       _MK_ENUM_CONST(1)
+#define I2C_IO_PACKET_HEADER_0_CONTROLLER_ID_I2C3                       _MK_ENUM_CONST(2)
+#define I2C_IO_PACKET_HEADER_0_CONTROLLER_ID_DVC_I2C                    _MK_ENUM_CONST(3)
+
+#define I2C_IO_PACKET_HEADER_0_RESERVED0_1_SHIFT                        _MK_SHIFT_CONST(8)
+#define I2C_IO_PACKET_HEADER_0_RESERVED0_1_FIELD                        (_MK_MASK_CONST(0xf) << I2C_IO_PACKET_HEADER_0_RESERVED0_1_SHIFT)
+#define I2C_IO_PACKET_HEADER_0_RESERVED0_1_RANGE                        _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(8)
+#define I2C_IO_PACKET_HEADER_0_RESERVED0_1_ROW                  0
+
+#define I2C_IO_PACKET_HEADER_0_PROTOCOL_SHIFT                   _MK_SHIFT_CONST(4)
+#define I2C_IO_PACKET_HEADER_0_PROTOCOL_FIELD                   (_MK_MASK_CONST(0xf) << I2C_IO_PACKET_HEADER_0_PROTOCOL_SHIFT)
+#define I2C_IO_PACKET_HEADER_0_PROTOCOL_RANGE                   _MK_SHIFT_CONST(7):_MK_SHIFT_CONST(4)
+#define I2C_IO_PACKET_HEADER_0_PROTOCOL_ROW                     0
+#define I2C_IO_PACKET_HEADER_0_PROTOCOL_RESERVED                        _MK_ENUM_CONST(0)
+#define I2C_IO_PACKET_HEADER_0_PROTOCOL_I2C                     _MK_ENUM_CONST(1)
+
+#define I2C_IO_PACKET_HEADER_0_RESERVED0_0_SHIFT                        _MK_SHIFT_CONST(3)
+#define I2C_IO_PACKET_HEADER_0_RESERVED0_0_FIELD                        (_MK_MASK_CONST(0x1) << I2C_IO_PACKET_HEADER_0_RESERVED0_0_SHIFT)
+#define I2C_IO_PACKET_HEADER_0_RESERVED0_0_RANGE                        _MK_SHIFT_CONST(3):_MK_SHIFT_CONST(3)
+#define I2C_IO_PACKET_HEADER_0_RESERVED0_0_ROW                  0
+
+#define I2C_IO_PACKET_HEADER_0_PKTTYPE_SHIFT                    _MK_SHIFT_CONST(0)
+#define I2C_IO_PACKET_HEADER_0_PKTTYPE_FIELD                    (_MK_MASK_CONST(0x7) << I2C_IO_PACKET_HEADER_0_PKTTYPE_SHIFT)
+#define I2C_IO_PACKET_HEADER_0_PKTTYPE_RANGE                    _MK_SHIFT_CONST(2):_MK_SHIFT_CONST(0)
+#define I2C_IO_PACKET_HEADER_0_PKTTYPE_ROW                      0
+
+#define I2C_IO_PACKET_HEADER_0_RESERVED1_0_SHIFT                        _MK_SHIFT_CONST(12)
+#define I2C_IO_PACKET_HEADER_0_RESERVED1_0_FIELD                        (_MK_MASK_CONST(0xfffff) << I2C_IO_PACKET_HEADER_0_RESERVED1_0_SHIFT)
+#define I2C_IO_PACKET_HEADER_0_RESERVED1_0_RANGE                        _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(12)
+#define I2C_IO_PACKET_HEADER_0_RESERVED1_0_ROW                  1
+
+#define I2C_IO_PACKET_HEADER_0_PAYLOADSIZE_SHIFT                        _MK_SHIFT_CONST(0)
+#define I2C_IO_PACKET_HEADER_0_PAYLOADSIZE_FIELD                        (_MK_MASK_CONST(0xfff) << I2C_IO_PACKET_HEADER_0_PAYLOADSIZE_SHIFT)
+#define I2C_IO_PACKET_HEADER_0_PAYLOADSIZE_RANGE                        _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(0)
+#define I2C_IO_PACKET_HEADER_0_PAYLOADSIZE_ROW                  1
+
+#define I2C_IO_PACKET_HEADER_0_RESERVED2_0_SHIFT                        _MK_SHIFT_CONST(23)
+#define I2C_IO_PACKET_HEADER_0_RESERVED2_0_FIELD                        (_MK_MASK_CONST(0x1ff) << I2C_IO_PACKET_HEADER_0_RESERVED2_0_SHIFT)
+#define I2C_IO_PACKET_HEADER_0_RESERVED2_0_RANGE                        _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(23)
+#define I2C_IO_PACKET_HEADER_0_RESERVED2_0_ROW                  2
+
+#define I2C_IO_PACKET_HEADER_0_HS_MODE_SHIFT                    _MK_SHIFT_CONST(22)
+#define I2C_IO_PACKET_HEADER_0_HS_MODE_FIELD                    (_MK_MASK_CONST(0x1) << I2C_IO_PACKET_HEADER_0_HS_MODE_SHIFT)
+#define I2C_IO_PACKET_HEADER_0_HS_MODE_RANGE                    _MK_SHIFT_CONST(22):_MK_SHIFT_CONST(22)
+#define I2C_IO_PACKET_HEADER_0_HS_MODE_ROW                      2
+#define I2C_IO_PACKET_HEADER_0_HS_MODE_DISABLE                  _MK_ENUM_CONST(0)
+#define I2C_IO_PACKET_HEADER_0_HS_MODE_ENABLE                   _MK_ENUM_CONST(1)
+
+#define I2C_IO_PACKET_HEADER_0_CONTUNE_ON_NACK_SHIFT                    _MK_SHIFT_CONST(21)
+#define I2C_IO_PACKET_HEADER_0_CONTUNE_ON_NACK_FIELD                    (_MK_MASK_CONST(0x1) << I2C_IO_PACKET_HEADER_0_CONTUNE_ON_NACK_SHIFT)
+#define I2C_IO_PACKET_HEADER_0_CONTUNE_ON_NACK_RANGE                    _MK_SHIFT_CONST(21):_MK_SHIFT_CONST(21)
+#define I2C_IO_PACKET_HEADER_0_CONTUNE_ON_NACK_ROW                      2
+#define I2C_IO_PACKET_HEADER_0_CONTUNE_ON_NACK_DISABLE                  _MK_ENUM_CONST(0)
+#define I2C_IO_PACKET_HEADER_0_CONTUNE_ON_NACK_ENABLE                   _MK_ENUM_CONST(1)
+
+#define I2C_IO_PACKET_HEADER_0_SEND_START_BYTE_SHIFT                    _MK_SHIFT_CONST(20)
+#define I2C_IO_PACKET_HEADER_0_SEND_START_BYTE_FIELD                    (_MK_MASK_CONST(0x1) << I2C_IO_PACKET_HEADER_0_SEND_START_BYTE_SHIFT)
+#define I2C_IO_PACKET_HEADER_0_SEND_START_BYTE_RANGE                    _MK_SHIFT_CONST(20):_MK_SHIFT_CONST(20)
+#define I2C_IO_PACKET_HEADER_0_SEND_START_BYTE_ROW                      2
+#define I2C_IO_PACKET_HEADER_0_SEND_START_BYTE_DISABLE                  _MK_ENUM_CONST(0)
+#define I2C_IO_PACKET_HEADER_0_SEND_START_BYTE_ENABLE                   _MK_ENUM_CONST(1)
+
+#define I2C_IO_PACKET_HEADER_0_READ_SHIFT                       _MK_SHIFT_CONST(19)
+#define I2C_IO_PACKET_HEADER_0_READ_FIELD                       (_MK_MASK_CONST(0x1) << I2C_IO_PACKET_HEADER_0_READ_SHIFT)
+#define I2C_IO_PACKET_HEADER_0_READ_RANGE                       _MK_SHIFT_CONST(19):_MK_SHIFT_CONST(19)
+#define I2C_IO_PACKET_HEADER_0_READ_ROW                 2
+#define I2C_IO_PACKET_HEADER_0_READ_WRITE                       _MK_ENUM_CONST(0)
+#define I2C_IO_PACKET_HEADER_0_READ_READ                        _MK_ENUM_CONST(1)
+
+#define I2C_IO_PACKET_HEADER_0_ADDR_MODE_SHIFT                  _MK_SHIFT_CONST(18)
+#define I2C_IO_PACKET_HEADER_0_ADDR_MODE_FIELD                  (_MK_MASK_CONST(0x1) << I2C_IO_PACKET_HEADER_0_ADDR_MODE_SHIFT)
+#define I2C_IO_PACKET_HEADER_0_ADDR_MODE_RANGE                  _MK_SHIFT_CONST(18):_MK_SHIFT_CONST(18)
+#define I2C_IO_PACKET_HEADER_0_ADDR_MODE_ROW                    2
+#define I2C_IO_PACKET_HEADER_0_ADDR_MODE_SEVEN_BIT                      _MK_ENUM_CONST(0)
+#define I2C_IO_PACKET_HEADER_0_ADDR_MODE_TEN_BIT                        _MK_ENUM_CONST(1)
+
+#define I2C_IO_PACKET_HEADER_0_IE_SHIFT                 _MK_SHIFT_CONST(17)
+#define I2C_IO_PACKET_HEADER_0_IE_FIELD                 (_MK_MASK_CONST(0x1) << I2C_IO_PACKET_HEADER_0_IE_SHIFT)
+#define I2C_IO_PACKET_HEADER_0_IE_RANGE                 _MK_SHIFT_CONST(17):_MK_SHIFT_CONST(17)
+#define I2C_IO_PACKET_HEADER_0_IE_ROW                   2
+#define I2C_IO_PACKET_HEADER_0_IE_DISABLE                       _MK_ENUM_CONST(0)
+#define I2C_IO_PACKET_HEADER_0_IE_ENABLE                        _MK_ENUM_CONST(1)
+
+#define I2C_IO_PACKET_HEADER_0_REPEAT_START_SHIFT                       _MK_SHIFT_CONST(16)
+#define I2C_IO_PACKET_HEADER_0_REPEAT_START_FIELD                       (_MK_MASK_CONST(0x1) << I2C_IO_PACKET_HEADER_0_REPEAT_START_SHIFT)
+#define I2C_IO_PACKET_HEADER_0_REPEAT_START_RANGE                       _MK_SHIFT_CONST(16):_MK_SHIFT_CONST(16)
+#define I2C_IO_PACKET_HEADER_0_REPEAT_START_ROW                 2
+#define I2C_IO_PACKET_HEADER_0_REPEAT_START_STOP                        _MK_ENUM_CONST(0)
+#define I2C_IO_PACKET_HEADER_0_REPEAT_START_REPEAT_START                        _MK_ENUM_CONST(1)
+
+#define I2C_IO_PACKET_HEADER_0_RESERVED2_1_SHIFT                        _MK_SHIFT_CONST(15)
+#define I2C_IO_PACKET_HEADER_0_RESERVED2_1_FIELD                        (_MK_MASK_CONST(0x1) << I2C_IO_PACKET_HEADER_0_RESERVED2_1_SHIFT)
+#define I2C_IO_PACKET_HEADER_0_RESERVED2_1_RANGE                        _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(15)
+#define I2C_IO_PACKET_HEADER_0_RESERVED2_1_ROW                  2
+
+#define I2C_IO_PACKET_HEADER_0_HS_MASTER_ADDR_SHIFT                     _MK_SHIFT_CONST(12)
+#define I2C_IO_PACKET_HEADER_0_HS_MASTER_ADDR_FIELD                     (_MK_MASK_CONST(0x7) << I2C_IO_PACKET_HEADER_0_HS_MASTER_ADDR_SHIFT)
+#define I2C_IO_PACKET_HEADER_0_HS_MASTER_ADDR_RANGE                     _MK_SHIFT_CONST(14):_MK_SHIFT_CONST(12)
+#define I2C_IO_PACKET_HEADER_0_HS_MASTER_ADDR_ROW                       2
+
+#define I2C_IO_PACKET_HEADER_0_RESERVED2_2_SHIFT                        _MK_SHIFT_CONST(10)
+#define I2C_IO_PACKET_HEADER_0_RESERVED2_2_FIELD                        (_MK_MASK_CONST(0x3) << I2C_IO_PACKET_HEADER_0_RESERVED2_2_SHIFT)
+#define I2C_IO_PACKET_HEADER_0_RESERVED2_2_RANGE                        _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(10)
+#define I2C_IO_PACKET_HEADER_0_RESERVED2_2_ROW                  2
+
+#define I2C_IO_PACKET_HEADER_0_SLAVE_ADDR_SHIFT                 _MK_SHIFT_CONST(0)
+#define I2C_IO_PACKET_HEADER_0_SLAVE_ADDR_FIELD                 (_MK_MASK_CONST(0x3ff) << I2C_IO_PACKET_HEADER_0_SLAVE_ADDR_SHIFT)
+#define I2C_IO_PACKET_HEADER_0_SLAVE_ADDR_RANGE                 _MK_SHIFT_CONST(9):_MK_SHIFT_CONST(0)
+#define I2C_IO_PACKET_HEADER_0_SLAVE_ADDR_ROW                   2
+
+
+// Register I2C_I2C_TX_PACKET_FIFO_0  
+#define I2C_I2C_TX_PACKET_FIFO_0                        _MK_ADDR_CONST(0x50)
+#define I2C_I2C_TX_PACKET_FIFO_0_SECURE                         0x0
+#define I2C_I2C_TX_PACKET_FIFO_0_WORD_COUNT                     0x1
+#define I2C_I2C_TX_PACKET_FIFO_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define I2C_I2C_TX_PACKET_FIFO_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
+#define I2C_I2C_TX_PACKET_FIFO_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define I2C_I2C_TX_PACKET_FIFO_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define I2C_I2C_TX_PACKET_FIFO_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define I2C_I2C_TX_PACKET_FIFO_0_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
+//SW writes packets into this register  
+//A packet may contain generic
+#define I2C_I2C_TX_PACKET_FIFO_0_TX_PACKET_SHIFT                        _MK_SHIFT_CONST(0)
+#define I2C_I2C_TX_PACKET_FIFO_0_TX_PACKET_FIELD                        (_MK_MASK_CONST(0xffffffff) << I2C_I2C_TX_PACKET_FIFO_0_TX_PACKET_SHIFT)
+#define I2C_I2C_TX_PACKET_FIFO_0_TX_PACKET_RANGE                        31:0
+#define I2C_I2C_TX_PACKET_FIFO_0_TX_PACKET_WOFFSET                      0x0
+#define I2C_I2C_TX_PACKET_FIFO_0_TX_PACKET_DEFAULT                      _MK_MASK_CONST(0x0)
+#define I2C_I2C_TX_PACKET_FIFO_0_TX_PACKET_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
+#define I2C_I2C_TX_PACKET_FIFO_0_TX_PACKET_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define I2C_I2C_TX_PACKET_FIFO_0_TX_PACKET_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register I2C_I2C_RX_FIFO_0  
+#define I2C_I2C_RX_FIFO_0                       _MK_ADDR_CONST(0x54)
+#define I2C_I2C_RX_FIFO_0_SECURE                        0x0
+#define I2C_I2C_RX_FIFO_0_WORD_COUNT                    0x1
+#define I2C_I2C_RX_FIFO_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define I2C_I2C_RX_FIFO_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
+#define I2C_I2C_RX_FIFO_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define I2C_I2C_RX_FIFO_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define I2C_I2C_RX_FIFO_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define I2C_I2C_RX_FIFO_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+//SW Reads data from this register,causes pop  
+#define I2C_I2C_RX_FIFO_0_RD_DATA_SHIFT                 _MK_SHIFT_CONST(0)
+#define I2C_I2C_RX_FIFO_0_RD_DATA_FIELD                 (_MK_MASK_CONST(0xffffffff) << I2C_I2C_RX_FIFO_0_RD_DATA_SHIFT)
+#define I2C_I2C_RX_FIFO_0_RD_DATA_RANGE                 31:0
+#define I2C_I2C_RX_FIFO_0_RD_DATA_WOFFSET                       0x0
+#define I2C_I2C_RX_FIFO_0_RD_DATA_DEFAULT                       _MK_MASK_CONST(0x0)
+#define I2C_I2C_RX_FIFO_0_RD_DATA_DEFAULT_MASK                  _MK_MASK_CONST(0xffffffff)
+#define I2C_I2C_RX_FIFO_0_RD_DATA_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define I2C_I2C_RX_FIFO_0_RD_DATA_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register I2C_PACKET_TRANSFER_STATUS_0  
+#define I2C_PACKET_TRANSFER_STATUS_0                    _MK_ADDR_CONST(0x58)
+#define I2C_PACKET_TRANSFER_STATUS_0_SECURE                     0x0
+#define I2C_PACKET_TRANSFER_STATUS_0_WORD_COUNT                         0x1
+#define I2C_PACKET_TRANSFER_STATUS_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define I2C_PACKET_TRANSFER_STATUS_0_RESET_MASK                         _MK_MASK_CONST(0x1ffffff)
+#define I2C_PACKET_TRANSFER_STATUS_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define I2C_PACKET_TRANSFER_STATUS_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define I2C_PACKET_TRANSFER_STATUS_0_READ_MASK                  _MK_MASK_CONST(0x1ffffff)
+#define I2C_PACKET_TRANSFER_STATUS_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
+//The packet transfer for which last packet is set has been
+//completed       
+#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_COMPLETE_SHIFT                    _MK_SHIFT_CONST(24)
+#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_COMPLETE_FIELD                    (_MK_MASK_CONST(0x1) << I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_COMPLETE_SHIFT)
+#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_COMPLETE_RANGE                    24:24
+#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_COMPLETE_WOFFSET                  0x0
+#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_COMPLETE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_COMPLETE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_COMPLETE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_COMPLETE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_COMPLETE_UNSET                    _MK_ENUM_CONST(0)
+#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_COMPLETE_SET                      _MK_ENUM_CONST(1)
+
+//The current packet id for which the transaction is 
+//happening on the bus
+#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_PKT_ID_SHIFT                      _MK_SHIFT_CONST(16)
+#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_PKT_ID_FIELD                      (_MK_MASK_CONST(0xff) << I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_PKT_ID_SHIFT)
+#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_PKT_ID_RANGE                      23:16
+#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_PKT_ID_WOFFSET                    0x0
+#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_PKT_ID_DEFAULT                    _MK_MASK_CONST(0x0)
+#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_PKT_ID_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
+#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_PKT_ID_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_PKT_ID_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+//The number of bytes transferred in the current packet 
+#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_BYTENUM_SHIFT                     _MK_SHIFT_CONST(4)
+#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_BYTENUM_FIELD                     (_MK_MASK_CONST(0xfff) << I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_BYTENUM_SHIFT)
+#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_BYTENUM_RANGE                     15:4
+#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_BYTENUM_WOFFSET                   0x0
+#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_BYTENUM_DEFAULT                   _MK_MASK_CONST(0x0)
+#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_BYTENUM_DEFAULT_MASK                      _MK_MASK_CONST(0xfff)
+#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_BYTENUM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_BYTENUM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+//No ack recieved for the addr byte
+#define I2C_PACKET_TRANSFER_STATUS_0_NOACK_FOR_ADDR_SHIFT                       _MK_SHIFT_CONST(3)
+#define I2C_PACKET_TRANSFER_STATUS_0_NOACK_FOR_ADDR_FIELD                       (_MK_MASK_CONST(0x1) << I2C_PACKET_TRANSFER_STATUS_0_NOACK_FOR_ADDR_SHIFT)
+#define I2C_PACKET_TRANSFER_STATUS_0_NOACK_FOR_ADDR_RANGE                       3:3
+#define I2C_PACKET_TRANSFER_STATUS_0_NOACK_FOR_ADDR_WOFFSET                     0x0
+#define I2C_PACKET_TRANSFER_STATUS_0_NOACK_FOR_ADDR_DEFAULT                     _MK_MASK_CONST(0x0)
+#define I2C_PACKET_TRANSFER_STATUS_0_NOACK_FOR_ADDR_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define I2C_PACKET_TRANSFER_STATUS_0_NOACK_FOR_ADDR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define I2C_PACKET_TRANSFER_STATUS_0_NOACK_FOR_ADDR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define I2C_PACKET_TRANSFER_STATUS_0_NOACK_FOR_ADDR_UNSET                       _MK_ENUM_CONST(0)
+#define I2C_PACKET_TRANSFER_STATUS_0_NOACK_FOR_ADDR_SET                 _MK_ENUM_CONST(1)
+
+//No ack recieved for the data byte
+#define I2C_PACKET_TRANSFER_STATUS_0_NOACK_FOR_DATA_SHIFT                       _MK_SHIFT_CONST(2)
+#define I2C_PACKET_TRANSFER_STATUS_0_NOACK_FOR_DATA_FIELD                       (_MK_MASK_CONST(0x1) << I2C_PACKET_TRANSFER_STATUS_0_NOACK_FOR_DATA_SHIFT)
+#define I2C_PACKET_TRANSFER_STATUS_0_NOACK_FOR_DATA_RANGE                       2:2
+#define I2C_PACKET_TRANSFER_STATUS_0_NOACK_FOR_DATA_WOFFSET                     0x0
+#define I2C_PACKET_TRANSFER_STATUS_0_NOACK_FOR_DATA_DEFAULT                     _MK_MASK_CONST(0x0)
+#define I2C_PACKET_TRANSFER_STATUS_0_NOACK_FOR_DATA_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define I2C_PACKET_TRANSFER_STATUS_0_NOACK_FOR_DATA_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define I2C_PACKET_TRANSFER_STATUS_0_NOACK_FOR_DATA_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define I2C_PACKET_TRANSFER_STATUS_0_NOACK_FOR_DATA_UNSET                       _MK_ENUM_CONST(0)
+#define I2C_PACKET_TRANSFER_STATUS_0_NOACK_FOR_DATA_SET                 _MK_ENUM_CONST(1)
+
+//Arbitration lost for the current byte
+#define I2C_PACKET_TRANSFER_STATUS_0_ARB_LOST_SHIFT                     _MK_SHIFT_CONST(1)
+#define I2C_PACKET_TRANSFER_STATUS_0_ARB_LOST_FIELD                     (_MK_MASK_CONST(0x1) << I2C_PACKET_TRANSFER_STATUS_0_ARB_LOST_SHIFT)
+#define I2C_PACKET_TRANSFER_STATUS_0_ARB_LOST_RANGE                     1:1
+#define I2C_PACKET_TRANSFER_STATUS_0_ARB_LOST_WOFFSET                   0x0
+#define I2C_PACKET_TRANSFER_STATUS_0_ARB_LOST_DEFAULT                   _MK_MASK_CONST(0x0)
+#define I2C_PACKET_TRANSFER_STATUS_0_ARB_LOST_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define I2C_PACKET_TRANSFER_STATUS_0_ARB_LOST_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define I2C_PACKET_TRANSFER_STATUS_0_ARB_LOST_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define I2C_PACKET_TRANSFER_STATUS_0_ARB_LOST_UNSET                     _MK_ENUM_CONST(0)
+#define I2C_PACKET_TRANSFER_STATUS_0_ARB_LOST_SET                       _MK_ENUM_CONST(1)
+
+//1 = Controller is busy
+#define I2C_PACKET_TRANSFER_STATUS_0_CONTROLLER_BUSY_SHIFT                      _MK_SHIFT_CONST(0)
+#define I2C_PACKET_TRANSFER_STATUS_0_CONTROLLER_BUSY_FIELD                      (_MK_MASK_CONST(0x1) << I2C_PACKET_TRANSFER_STATUS_0_CONTROLLER_BUSY_SHIFT)
+#define I2C_PACKET_TRANSFER_STATUS_0_CONTROLLER_BUSY_RANGE                      0:0
+#define I2C_PACKET_TRANSFER_STATUS_0_CONTROLLER_BUSY_WOFFSET                    0x0
+#define I2C_PACKET_TRANSFER_STATUS_0_CONTROLLER_BUSY_DEFAULT                    _MK_MASK_CONST(0x0)
+#define I2C_PACKET_TRANSFER_STATUS_0_CONTROLLER_BUSY_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define I2C_PACKET_TRANSFER_STATUS_0_CONTROLLER_BUSY_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define I2C_PACKET_TRANSFER_STATUS_0_CONTROLLER_BUSY_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define I2C_PACKET_TRANSFER_STATUS_0_CONTROLLER_BUSY_UNSET                      _MK_ENUM_CONST(0)
+#define I2C_PACKET_TRANSFER_STATUS_0_CONTROLLER_BUSY_SET                        _MK_ENUM_CONST(1)
+
+
+// Register I2C_FIFO_CONTROL_0  
+#define I2C_FIFO_CONTROL_0                      _MK_ADDR_CONST(0x5c)
+#define I2C_FIFO_CONTROL_0_SECURE                       0x0
+#define I2C_FIFO_CONTROL_0_WORD_COUNT                   0x1
+#define I2C_FIFO_CONTROL_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define I2C_FIFO_CONTROL_0_RESET_MASK                   _MK_MASK_CONST(0xff)
+#define I2C_FIFO_CONTROL_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define I2C_FIFO_CONTROL_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define I2C_FIFO_CONTROL_0_READ_MASK                    _MK_MASK_CONST(0xff)
+#define I2C_FIFO_CONTROL_0_WRITE_MASK                   _MK_MASK_CONST(0xff)
+//Transmit fifo trigger level 
+//000 = 1 word,  Dma trigger is asserted when 
+//at least one word empty in the fifo 
+//010 = 2 word,  Dma trigger is asserted when 
+//at least 2 words empty in the fifo 
+#define I2C_FIFO_CONTROL_0_TX_FIFO_TRIG_SHIFT                   _MK_SHIFT_CONST(5)
+#define I2C_FIFO_CONTROL_0_TX_FIFO_TRIG_FIELD                   (_MK_MASK_CONST(0x7) << I2C_FIFO_CONTROL_0_TX_FIFO_TRIG_SHIFT)
+#define I2C_FIFO_CONTROL_0_TX_FIFO_TRIG_RANGE                   7:5
+#define I2C_FIFO_CONTROL_0_TX_FIFO_TRIG_WOFFSET                 0x0
+#define I2C_FIFO_CONTROL_0_TX_FIFO_TRIG_DEFAULT                 _MK_MASK_CONST(0x0)
+#define I2C_FIFO_CONTROL_0_TX_FIFO_TRIG_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
+#define I2C_FIFO_CONTROL_0_TX_FIFO_TRIG_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define I2C_FIFO_CONTROL_0_TX_FIFO_TRIG_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+//Receive fifo trigger level 
+//000 = 1 word  Dma trigger is asserted when 
+//at least one word full in the fifo 
+//010 = 2 word  Dma trigger is asserted when 
+//at least 2 word full in the fifo 
+#define I2C_FIFO_CONTROL_0_RX_FIFO_TRIG_SHIFT                   _MK_SHIFT_CONST(2)
+#define I2C_FIFO_CONTROL_0_RX_FIFO_TRIG_FIELD                   (_MK_MASK_CONST(0x7) << I2C_FIFO_CONTROL_0_RX_FIFO_TRIG_SHIFT)
+#define I2C_FIFO_CONTROL_0_RX_FIFO_TRIG_RANGE                   4:2
+#define I2C_FIFO_CONTROL_0_RX_FIFO_TRIG_WOFFSET                 0x0
+#define I2C_FIFO_CONTROL_0_RX_FIFO_TRIG_DEFAULT                 _MK_MASK_CONST(0x0)
+#define I2C_FIFO_CONTROL_0_RX_FIFO_TRIG_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
+#define I2C_FIFO_CONTROL_0_RX_FIFO_TRIG_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define I2C_FIFO_CONTROL_0_RX_FIFO_TRIG_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+//1= flush the tx fifo,cleared after fifo is flushed
+#define I2C_FIFO_CONTROL_0_TX_FIFO_FLUSH_SHIFT                  _MK_SHIFT_CONST(1)
+#define I2C_FIFO_CONTROL_0_TX_FIFO_FLUSH_FIELD                  (_MK_MASK_CONST(0x1) << I2C_FIFO_CONTROL_0_TX_FIFO_FLUSH_SHIFT)
+#define I2C_FIFO_CONTROL_0_TX_FIFO_FLUSH_RANGE                  1:1
+#define I2C_FIFO_CONTROL_0_TX_FIFO_FLUSH_WOFFSET                        0x0
+#define I2C_FIFO_CONTROL_0_TX_FIFO_FLUSH_DEFAULT                        _MK_MASK_CONST(0x0)
+#define I2C_FIFO_CONTROL_0_TX_FIFO_FLUSH_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define I2C_FIFO_CONTROL_0_TX_FIFO_FLUSH_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define I2C_FIFO_CONTROL_0_TX_FIFO_FLUSH_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define I2C_FIFO_CONTROL_0_TX_FIFO_FLUSH_UNSET                  _MK_ENUM_CONST(0)
+#define I2C_FIFO_CONTROL_0_TX_FIFO_FLUSH_SET                    _MK_ENUM_CONST(1)
+
+//1= flush the rx fifo,cleared after fifo is flushed 
+#define I2C_FIFO_CONTROL_0_RX_FIFO_FLUSH_SHIFT                  _MK_SHIFT_CONST(0)
+#define I2C_FIFO_CONTROL_0_RX_FIFO_FLUSH_FIELD                  (_MK_MASK_CONST(0x1) << I2C_FIFO_CONTROL_0_RX_FIFO_FLUSH_SHIFT)
+#define I2C_FIFO_CONTROL_0_RX_FIFO_FLUSH_RANGE                  0:0
+#define I2C_FIFO_CONTROL_0_RX_FIFO_FLUSH_WOFFSET                        0x0
+#define I2C_FIFO_CONTROL_0_RX_FIFO_FLUSH_DEFAULT                        _MK_MASK_CONST(0x0)
+#define I2C_FIFO_CONTROL_0_RX_FIFO_FLUSH_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define I2C_FIFO_CONTROL_0_RX_FIFO_FLUSH_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define I2C_FIFO_CONTROL_0_RX_FIFO_FLUSH_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define I2C_FIFO_CONTROL_0_RX_FIFO_FLUSH_UNSET                  _MK_ENUM_CONST(0)
+#define I2C_FIFO_CONTROL_0_RX_FIFO_FLUSH_SET                    _MK_ENUM_CONST(1)
+
+
+// Register I2C_FIFO_STATUS_0  
+#define I2C_FIFO_STATUS_0                       _MK_ADDR_CONST(0x60)
+#define I2C_FIFO_STATUS_0_SECURE                        0x0
+#define I2C_FIFO_STATUS_0_WORD_COUNT                    0x1
+#define I2C_FIFO_STATUS_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define I2C_FIFO_STATUS_0_RESET_MASK                    _MK_MASK_CONST(0xff)
+#define I2C_FIFO_STATUS_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define I2C_FIFO_STATUS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define I2C_FIFO_STATUS_0_READ_MASK                     _MK_MASK_CONST(0xff)
+#define I2C_FIFO_STATUS_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+//The number of slots that can be written to the tx fifo
+//0000 = tx_fifo full
+//0001 = 1 slot empty 
+//0010 = 2 slots empty 
+#define I2C_FIFO_STATUS_0_TX_FIFO_EMPTY_CNT_SHIFT                       _MK_SHIFT_CONST(4)
+#define I2C_FIFO_STATUS_0_TX_FIFO_EMPTY_CNT_FIELD                       (_MK_MASK_CONST(0xf) << I2C_FIFO_STATUS_0_TX_FIFO_EMPTY_CNT_SHIFT)
+#define I2C_FIFO_STATUS_0_TX_FIFO_EMPTY_CNT_RANGE                       7:4
+#define I2C_FIFO_STATUS_0_TX_FIFO_EMPTY_CNT_WOFFSET                     0x0
+#define I2C_FIFO_STATUS_0_TX_FIFO_EMPTY_CNT_DEFAULT                     _MK_MASK_CONST(0x0)
+#define I2C_FIFO_STATUS_0_TX_FIFO_EMPTY_CNT_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define I2C_FIFO_STATUS_0_TX_FIFO_EMPTY_CNT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define I2C_FIFO_STATUS_0_TX_FIFO_EMPTY_CNT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+//The number of slots to be read from  the rx fifo
+//0000 = rx_fifo empty
+//0001 = 1 slot  full
+//0010 = 2 slots  full
+#define I2C_FIFO_STATUS_0_RX_FIFO_FULL_CNT_SHIFT                        _MK_SHIFT_CONST(0)
+#define I2C_FIFO_STATUS_0_RX_FIFO_FULL_CNT_FIELD                        (_MK_MASK_CONST(0xf) << I2C_FIFO_STATUS_0_RX_FIFO_FULL_CNT_SHIFT)
+#define I2C_FIFO_STATUS_0_RX_FIFO_FULL_CNT_RANGE                        3:0
+#define I2C_FIFO_STATUS_0_RX_FIFO_FULL_CNT_WOFFSET                      0x0
+#define I2C_FIFO_STATUS_0_RX_FIFO_FULL_CNT_DEFAULT                      _MK_MASK_CONST(0x0)
+#define I2C_FIFO_STATUS_0_RX_FIFO_FULL_CNT_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define I2C_FIFO_STATUS_0_RX_FIFO_FULL_CNT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define I2C_FIFO_STATUS_0_RX_FIFO_FULL_CNT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register I2C_INTERRUPT_MASK_REGISTER_0  
+#define I2C_INTERRUPT_MASK_REGISTER_0                   _MK_ADDR_CONST(0x64)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SECURE                    0x0
+#define I2C_INTERRUPT_MASK_REGISTER_0_WORD_COUNT                        0x1
+#define I2C_INTERRUPT_MASK_REGISTER_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_RESET_MASK                        _MK_MASK_CONST(0x7f)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_READ_MASK                         _MK_MASK_CONST(0x7f)
+#define I2C_INTERRUPT_MASK_REGISTER_0_WRITE_MASK                        _MK_MASK_CONST(0x7f)
+#define I2C_INTERRUPT_MASK_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_INT_EN_SHIFT                    _MK_SHIFT_CONST(6)
+#define I2C_INTERRUPT_MASK_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_INT_EN_FIELD                    (_MK_MASK_CONST(0x1) << I2C_INTERRUPT_MASK_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_INT_EN_SHIFT)
+#define I2C_INTERRUPT_MASK_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_INT_EN_RANGE                    6:6
+#define I2C_INTERRUPT_MASK_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_INT_EN_WOFFSET                  0x0
+#define I2C_INTERRUPT_MASK_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_INT_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_INT_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define I2C_INTERRUPT_MASK_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_INT_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_INT_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_INT_EN_DISABLE                  _MK_ENUM_CONST(0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_INT_EN_ENABLE                   _MK_ENUM_CONST(1)
+
+#define I2C_INTERRUPT_MASK_REGISTER_0_TFIFO_OVF_INT_EN_SHIFT                    _MK_SHIFT_CONST(5)
+#define I2C_INTERRUPT_MASK_REGISTER_0_TFIFO_OVF_INT_EN_FIELD                    (_MK_MASK_CONST(0x1) << I2C_INTERRUPT_MASK_REGISTER_0_TFIFO_OVF_INT_EN_SHIFT)
+#define I2C_INTERRUPT_MASK_REGISTER_0_TFIFO_OVF_INT_EN_RANGE                    5:5
+#define I2C_INTERRUPT_MASK_REGISTER_0_TFIFO_OVF_INT_EN_WOFFSET                  0x0
+#define I2C_INTERRUPT_MASK_REGISTER_0_TFIFO_OVF_INT_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_TFIFO_OVF_INT_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define I2C_INTERRUPT_MASK_REGISTER_0_TFIFO_OVF_INT_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_TFIFO_OVF_INT_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_TFIFO_OVF_INT_EN_DISABLE                  _MK_ENUM_CONST(0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_TFIFO_OVF_INT_EN_ENABLE                   _MK_ENUM_CONST(1)
+
+#define I2C_INTERRUPT_MASK_REGISTER_0_RFIFO_UNF_INT_EN_SHIFT                    _MK_SHIFT_CONST(4)
+#define I2C_INTERRUPT_MASK_REGISTER_0_RFIFO_UNF_INT_EN_FIELD                    (_MK_MASK_CONST(0x1) << I2C_INTERRUPT_MASK_REGISTER_0_RFIFO_UNF_INT_EN_SHIFT)
+#define I2C_INTERRUPT_MASK_REGISTER_0_RFIFO_UNF_INT_EN_RANGE                    4:4
+#define I2C_INTERRUPT_MASK_REGISTER_0_RFIFO_UNF_INT_EN_WOFFSET                  0x0
+#define I2C_INTERRUPT_MASK_REGISTER_0_RFIFO_UNF_INT_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_RFIFO_UNF_INT_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define I2C_INTERRUPT_MASK_REGISTER_0_RFIFO_UNF_INT_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_RFIFO_UNF_INT_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_RFIFO_UNF_INT_EN_DISABLE                  _MK_ENUM_CONST(0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_RFIFO_UNF_INT_EN_ENABLE                   _MK_ENUM_CONST(1)
+
+#define I2C_INTERRUPT_MASK_REGISTER_0_NOACK_INT_EN_SHIFT                        _MK_SHIFT_CONST(3)
+#define I2C_INTERRUPT_MASK_REGISTER_0_NOACK_INT_EN_FIELD                        (_MK_MASK_CONST(0x1) << I2C_INTERRUPT_MASK_REGISTER_0_NOACK_INT_EN_SHIFT)
+#define I2C_INTERRUPT_MASK_REGISTER_0_NOACK_INT_EN_RANGE                        3:3
+#define I2C_INTERRUPT_MASK_REGISTER_0_NOACK_INT_EN_WOFFSET                      0x0
+#define I2C_INTERRUPT_MASK_REGISTER_0_NOACK_INT_EN_DEFAULT                      _MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_NOACK_INT_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define I2C_INTERRUPT_MASK_REGISTER_0_NOACK_INT_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_NOACK_INT_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_NOACK_INT_EN_DISABLE                      _MK_ENUM_CONST(0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_NOACK_INT_EN_ENABLE                       _MK_ENUM_CONST(1)
+
+#define I2C_INTERRUPT_MASK_REGISTER_0_ARB_LOST_INT_EN_SHIFT                     _MK_SHIFT_CONST(2)
+#define I2C_INTERRUPT_MASK_REGISTER_0_ARB_LOST_INT_EN_FIELD                     (_MK_MASK_CONST(0x1) << I2C_INTERRUPT_MASK_REGISTER_0_ARB_LOST_INT_EN_SHIFT)
+#define I2C_INTERRUPT_MASK_REGISTER_0_ARB_LOST_INT_EN_RANGE                     2:2
+#define I2C_INTERRUPT_MASK_REGISTER_0_ARB_LOST_INT_EN_WOFFSET                   0x0
+#define I2C_INTERRUPT_MASK_REGISTER_0_ARB_LOST_INT_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_ARB_LOST_INT_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define I2C_INTERRUPT_MASK_REGISTER_0_ARB_LOST_INT_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_ARB_LOST_INT_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_ARB_LOST_INT_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_ARB_LOST_INT_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+#define I2C_INTERRUPT_MASK_REGISTER_0_TFIFO_DATA_REQ_INT_EN_SHIFT                       _MK_SHIFT_CONST(1)
+#define I2C_INTERRUPT_MASK_REGISTER_0_TFIFO_DATA_REQ_INT_EN_FIELD                       (_MK_MASK_CONST(0x1) << I2C_INTERRUPT_MASK_REGISTER_0_TFIFO_DATA_REQ_INT_EN_SHIFT)
+#define I2C_INTERRUPT_MASK_REGISTER_0_TFIFO_DATA_REQ_INT_EN_RANGE                       1:1
+#define I2C_INTERRUPT_MASK_REGISTER_0_TFIFO_DATA_REQ_INT_EN_WOFFSET                     0x0
+#define I2C_INTERRUPT_MASK_REGISTER_0_TFIFO_DATA_REQ_INT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_TFIFO_DATA_REQ_INT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define I2C_INTERRUPT_MASK_REGISTER_0_TFIFO_DATA_REQ_INT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_TFIFO_DATA_REQ_INT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_TFIFO_DATA_REQ_INT_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_TFIFO_DATA_REQ_INT_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+#define I2C_INTERRUPT_MASK_REGISTER_0_RFIFO_DATA_REQ_INT_EN_SHIFT                       _MK_SHIFT_CONST(0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_RFIFO_DATA_REQ_INT_EN_FIELD                       (_MK_MASK_CONST(0x1) << I2C_INTERRUPT_MASK_REGISTER_0_RFIFO_DATA_REQ_INT_EN_SHIFT)
+#define I2C_INTERRUPT_MASK_REGISTER_0_RFIFO_DATA_REQ_INT_EN_RANGE                       0:0
+#define I2C_INTERRUPT_MASK_REGISTER_0_RFIFO_DATA_REQ_INT_EN_WOFFSET                     0x0
+#define I2C_INTERRUPT_MASK_REGISTER_0_RFIFO_DATA_REQ_INT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_RFIFO_DATA_REQ_INT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define I2C_INTERRUPT_MASK_REGISTER_0_RFIFO_DATA_REQ_INT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_RFIFO_DATA_REQ_INT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_RFIFO_DATA_REQ_INT_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_RFIFO_DATA_REQ_INT_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+
+// Register I2C_INTERRUPT_STATUS_REGISTER_0  //This register indicates the status bit for which the interrupt is set.If set,Write 1 to clear it
+//However TFIFO_DATA_REQ,RFIFO_DATA_REQ fields depend on the fifo trigger levels and cannot be cleared.
+#define I2C_INTERRUPT_STATUS_REGISTER_0                 _MK_ADDR_CONST(0x68)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SECURE                  0x0
+#define I2C_INTERRUPT_STATUS_REGISTER_0_WORD_COUNT                      0x1
+#define I2C_INTERRUPT_STATUS_REGISTER_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_RESET_MASK                      _MK_MASK_CONST(0xff)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_READ_MASK                       _MK_MASK_CONST(0xff)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_WRITE_MASK                      _MK_MASK_CONST(0xff)
+//A packet has been transferred succesfully.
+//TRANSFER_PKT_ID filed can be used to know the 
+//current byte under transfer.This bit can be
+//masked by the IE field in the i2c specific header
+#define I2C_INTERRUPT_STATUS_REGISTER_0_PACKET_XFER_COMPLETE_SHIFT                      _MK_SHIFT_CONST(7)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_PACKET_XFER_COMPLETE_FIELD                      (_MK_MASK_CONST(0x1) << I2C_INTERRUPT_STATUS_REGISTER_0_PACKET_XFER_COMPLETE_SHIFT)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_PACKET_XFER_COMPLETE_RANGE                      7:7
+#define I2C_INTERRUPT_STATUS_REGISTER_0_PACKET_XFER_COMPLETE_WOFFSET                    0x0
+#define I2C_INTERRUPT_STATUS_REGISTER_0_PACKET_XFER_COMPLETE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_PACKET_XFER_COMPLETE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_PACKET_XFER_COMPLETE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_PACKET_XFER_COMPLETE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_PACKET_XFER_COMPLETE_UNSET                      _MK_ENUM_CONST(0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_PACKET_XFER_COMPLETE_SET                        _MK_ENUM_CONST(1)
+
+//All the packets transferred succesfully
+#define I2C_INTERRUPT_STATUS_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_SHIFT                 _MK_SHIFT_CONST(6)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_FIELD                 (_MK_MASK_CONST(0x1) << I2C_INTERRUPT_STATUS_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_SHIFT)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_RANGE                 6:6
+#define I2C_INTERRUPT_STATUS_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_WOFFSET                       0x0
+#define I2C_INTERRUPT_STATUS_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_UNSET                 _MK_ENUM_CONST(0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_SET                   _MK_ENUM_CONST(1)
+
+//Tx fifo overflow
+#define I2C_INTERRUPT_STATUS_REGISTER_0_TFIFO_OVF_SHIFT                 _MK_SHIFT_CONST(5)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_TFIFO_OVF_FIELD                 (_MK_MASK_CONST(0x1) << I2C_INTERRUPT_STATUS_REGISTER_0_TFIFO_OVF_SHIFT)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_TFIFO_OVF_RANGE                 5:5
+#define I2C_INTERRUPT_STATUS_REGISTER_0_TFIFO_OVF_WOFFSET                       0x0
+#define I2C_INTERRUPT_STATUS_REGISTER_0_TFIFO_OVF_DEFAULT                       _MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_TFIFO_OVF_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_TFIFO_OVF_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_TFIFO_OVF_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_TFIFO_OVF_UNSET                 _MK_ENUM_CONST(0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_TFIFO_OVF_SET                   _MK_ENUM_CONST(1)
+
+//rx fifo underflow
+#define I2C_INTERRUPT_STATUS_REGISTER_0_RFIFO_UNF_SHIFT                 _MK_SHIFT_CONST(4)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_RFIFO_UNF_FIELD                 (_MK_MASK_CONST(0x1) << I2C_INTERRUPT_STATUS_REGISTER_0_RFIFO_UNF_SHIFT)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_RFIFO_UNF_RANGE                 4:4
+#define I2C_INTERRUPT_STATUS_REGISTER_0_RFIFO_UNF_WOFFSET                       0x0
+#define I2C_INTERRUPT_STATUS_REGISTER_0_RFIFO_UNF_DEFAULT                       _MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_RFIFO_UNF_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_RFIFO_UNF_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_RFIFO_UNF_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_RFIFO_UNF_UNSET                 _MK_ENUM_CONST(0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_RFIFO_UNF_SET                   _MK_ENUM_CONST(1)
+
+//No ACK from slave
+#define I2C_INTERRUPT_STATUS_REGISTER_0_NOACK_SHIFT                     _MK_SHIFT_CONST(3)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_NOACK_FIELD                     (_MK_MASK_CONST(0x1) << I2C_INTERRUPT_STATUS_REGISTER_0_NOACK_SHIFT)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_NOACK_RANGE                     3:3
+#define I2C_INTERRUPT_STATUS_REGISTER_0_NOACK_WOFFSET                   0x0
+#define I2C_INTERRUPT_STATUS_REGISTER_0_NOACK_DEFAULT                   _MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_NOACK_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_NOACK_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_NOACK_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_NOACK_UNSET                     _MK_ENUM_CONST(0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_NOACK_SET                       _MK_ENUM_CONST(1)
+
+//Arbitration lost
+#define I2C_INTERRUPT_STATUS_REGISTER_0_ARB_LOST_SHIFT                  _MK_SHIFT_CONST(2)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_ARB_LOST_FIELD                  (_MK_MASK_CONST(0x1) << I2C_INTERRUPT_STATUS_REGISTER_0_ARB_LOST_SHIFT)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_ARB_LOST_RANGE                  2:2
+#define I2C_INTERRUPT_STATUS_REGISTER_0_ARB_LOST_WOFFSET                        0x0
+#define I2C_INTERRUPT_STATUS_REGISTER_0_ARB_LOST_DEFAULT                        _MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_ARB_LOST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_ARB_LOST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_ARB_LOST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_ARB_LOST_UNSET                  _MK_ENUM_CONST(0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_ARB_LOST_SET                    _MK_ENUM_CONST(1)
+
+//Tx fifo data req
+#define I2C_INTERRUPT_STATUS_REGISTER_0_TFIFO_DATA_REQ_SHIFT                    _MK_SHIFT_CONST(1)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_TFIFO_DATA_REQ_FIELD                    (_MK_MASK_CONST(0x1) << I2C_INTERRUPT_STATUS_REGISTER_0_TFIFO_DATA_REQ_SHIFT)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_TFIFO_DATA_REQ_RANGE                    1:1
+#define I2C_INTERRUPT_STATUS_REGISTER_0_TFIFO_DATA_REQ_WOFFSET                  0x0
+#define I2C_INTERRUPT_STATUS_REGISTER_0_TFIFO_DATA_REQ_DEFAULT                  _MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_TFIFO_DATA_REQ_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_TFIFO_DATA_REQ_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_TFIFO_DATA_REQ_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_TFIFO_DATA_REQ_UNSET                    _MK_ENUM_CONST(0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_TFIFO_DATA_REQ_SET                      _MK_ENUM_CONST(1)
+
+//rx fifo data req
+#define I2C_INTERRUPT_STATUS_REGISTER_0_RFIFO_DATA_REQ_SHIFT                    _MK_SHIFT_CONST(0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_RFIFO_DATA_REQ_FIELD                    (_MK_MASK_CONST(0x1) << I2C_INTERRUPT_STATUS_REGISTER_0_RFIFO_DATA_REQ_SHIFT)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_RFIFO_DATA_REQ_RANGE                    0:0
+#define I2C_INTERRUPT_STATUS_REGISTER_0_RFIFO_DATA_REQ_WOFFSET                  0x0
+#define I2C_INTERRUPT_STATUS_REGISTER_0_RFIFO_DATA_REQ_DEFAULT                  _MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_RFIFO_DATA_REQ_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_RFIFO_DATA_REQ_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_RFIFO_DATA_REQ_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_RFIFO_DATA_REQ_UNSET                    _MK_ENUM_CONST(0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_RFIFO_DATA_REQ_SET                      _MK_ENUM_CONST(1)
+
+
+// Register I2C_I2C_CLK_DIVISOR_REGISTER_0  
+#define I2C_I2C_CLK_DIVISOR_REGISTER_0                  _MK_ADDR_CONST(0x6c)
+#define I2C_I2C_CLK_DIVISOR_REGISTER_0_SECURE                   0x0
+#define I2C_I2C_CLK_DIVISOR_REGISTER_0_WORD_COUNT                       0x1
+#define I2C_I2C_CLK_DIVISOR_REGISTER_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define I2C_I2C_CLK_DIVISOR_REGISTER_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
+#define I2C_I2C_CLK_DIVISOR_REGISTER_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define I2C_I2C_CLK_DIVISOR_REGISTER_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define I2C_I2C_CLK_DIVISOR_REGISTER_0_READ_MASK                        _MK_MASK_CONST(0xffff)
+#define I2C_I2C_CLK_DIVISOR_REGISTER_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
+//N= divide by n+1
+#define I2C_I2C_CLK_DIVISOR_REGISTER_0_I2C_CLK_DIVISOR_HSMODE_SHIFT                     _MK_SHIFT_CONST(0)
+#define I2C_I2C_CLK_DIVISOR_REGISTER_0_I2C_CLK_DIVISOR_HSMODE_FIELD                     (_MK_MASK_CONST(0xffff) << I2C_I2C_CLK_DIVISOR_REGISTER_0_I2C_CLK_DIVISOR_HSMODE_SHIFT)
+#define I2C_I2C_CLK_DIVISOR_REGISTER_0_I2C_CLK_DIVISOR_HSMODE_RANGE                     15:0
+#define I2C_I2C_CLK_DIVISOR_REGISTER_0_I2C_CLK_DIVISOR_HSMODE_WOFFSET                   0x0
+#define I2C_I2C_CLK_DIVISOR_REGISTER_0_I2C_CLK_DIVISOR_HSMODE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define I2C_I2C_CLK_DIVISOR_REGISTER_0_I2C_CLK_DIVISOR_HSMODE_DEFAULT_MASK                      _MK_MASK_CONST(0xffff)
+#define I2C_I2C_CLK_DIVISOR_REGISTER_0_I2C_CLK_DIVISOR_HSMODE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define I2C_I2C_CLK_DIVISOR_REGISTER_0_I2C_CLK_DIVISOR_HSMODE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+//
+// REGISTER LIST
+//
+#define LIST_ARI2C_REGS(_op_) \
+_op_(I2C_I2C_CNFG_0) \
+_op_(I2C_I2C_CMD_ADDR0_0) \
+_op_(I2C_I2C_CMD_ADDR1_0) \
+_op_(I2C_I2C_CMD_DATA1_0) \
+_op_(I2C_I2C_CMD_DATA2_0) \
+_op_(I2C_I2C_STATUS_0) \
+_op_(I2C_I2C_SL_CNFG_0) \
+_op_(I2C_I2C_SL_RCVD_0) \
+_op_(I2C_I2C_SL_STATUS_0) \
+_op_(I2C_I2C_SL_ADDR1_0) \
+_op_(I2C_I2C_SL_ADDR2_0) \
+_op_(I2C_I2C_SL_DELAY_COUNT_0) \
+_op_(I2C_I2C_TX_PACKET_FIFO_0) \
+_op_(I2C_I2C_RX_FIFO_0) \
+_op_(I2C_PACKET_TRANSFER_STATUS_0) \
+_op_(I2C_FIFO_CONTROL_0) \
+_op_(I2C_FIFO_STATUS_0) \
+_op_(I2C_INTERRUPT_MASK_REGISTER_0) \
+_op_(I2C_INTERRUPT_STATUS_REGISTER_0) \
+_op_(I2C_I2C_CLK_DIVISOR_REGISTER_0)
+
+
+//
+// ADDRESS SPACES
+//
+
+#define BASE_ADDRESS_I2C        0x00000000
+
+//
+// ARI2C REGISTER BANKS
+//
+
+#define I2C0_FIRST_REG 0x0000 // I2C_I2C_CNFG_0
+#define I2C0_LAST_REG 0x0010 // I2C_I2C_CMD_DATA2_0
+#define I2C1_FIRST_REG 0x001c // I2C_I2C_STATUS_0
+#define I2C1_LAST_REG 0x0030 // I2C_I2C_SL_ADDR2_0
+#define I2C2_FIRST_REG 0x003c // I2C_I2C_SL_DELAY_COUNT_0
+#define I2C2_LAST_REG 0x003c // I2C_I2C_SL_DELAY_COUNT_0
+#define I2C3_FIRST_REG 0x0050 // I2C_I2C_TX_PACKET_FIFO_0
+#define I2C3_LAST_REG 0x006c // I2C_I2C_CLK_DIVISOR_REGISTER_0
+
+#ifndef _MK_SHIFT_CONST
+  #define _MK_SHIFT_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_MASK_CONST
+  #define _MK_MASK_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_ENUM_CONST
+  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
+#endif
+#ifndef _MK_ADDR_CONST
+  #define _MK_ADDR_CONST(_constant_) _constant_
+#endif
+
+#endif // ifndef ___ARI2C_H_INC_
diff --git a/arch/arm/mach-tegra/include/ap20/armc.h b/arch/arm/mach-tegra/include/ap20/armc.h
new file mode 100644
index 000000000000..6db92de69f18
--- /dev/null
+++ b/arch/arm/mach-tegra/include/ap20/armc.h
@@ -0,0 +1,9705 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+//
+// DO NOT EDIT - generated by simspec!
+//
+
+#ifndef ___ARMC_H_INC_
+#define ___ARMC_H_INC_
+
+// Register MC_INTSTATUS_0  
+#define MC_INTSTATUS_0                  _MK_ADDR_CONST(0x0)
+#define MC_INTSTATUS_0_SECURE                   0x0
+#define MC_INTSTATUS_0_WORD_COUNT                       0x1
+#define MC_INTSTATUS_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define MC_INTSTATUS_0_RESET_MASK                       _MK_MASK_CONST(0x1c0)
+#define MC_INTSTATUS_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define MC_INTSTATUS_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_INTSTATUS_0_READ_MASK                        _MK_MASK_CONST(0x1c0)
+#define MC_INTSTATUS_0_WRITE_MASK                       _MK_MASK_CONST(0x1c0)
+// EMEM Address Decode Error for a non AXI client.
+#define MC_INTSTATUS_0_DECERR_EMEM_OTHERS_INT_SHIFT                     _MK_SHIFT_CONST(6)
+#define MC_INTSTATUS_0_DECERR_EMEM_OTHERS_INT_FIELD                     (_MK_MASK_CONST(0x1) << MC_INTSTATUS_0_DECERR_EMEM_OTHERS_INT_SHIFT)
+#define MC_INTSTATUS_0_DECERR_EMEM_OTHERS_INT_RANGE                     6:6
+#define MC_INTSTATUS_0_DECERR_EMEM_OTHERS_INT_WOFFSET                   0x0
+#define MC_INTSTATUS_0_DECERR_EMEM_OTHERS_INT_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_INTSTATUS_0_DECERR_EMEM_OTHERS_INT_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define MC_INTSTATUS_0_DECERR_EMEM_OTHERS_INT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_INTSTATUS_0_DECERR_EMEM_OTHERS_INT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_INTSTATUS_0_DECERR_EMEM_OTHERS_INT_INIT_ENUM                 CLEAR
+#define MC_INTSTATUS_0_DECERR_EMEM_OTHERS_INT_CLEAR                     _MK_ENUM_CONST(0)
+#define MC_INTSTATUS_0_DECERR_EMEM_OTHERS_INT_SET                       _MK_ENUM_CONST(1)
+
+// A GART access was attepted to an invalid page.
+#define MC_INTSTATUS_0_INVALID_GART_PAGE_INT_SHIFT                      _MK_SHIFT_CONST(7)
+#define MC_INTSTATUS_0_INVALID_GART_PAGE_INT_FIELD                      (_MK_MASK_CONST(0x1) << MC_INTSTATUS_0_INVALID_GART_PAGE_INT_SHIFT)
+#define MC_INTSTATUS_0_INVALID_GART_PAGE_INT_RANGE                      7:7
+#define MC_INTSTATUS_0_INVALID_GART_PAGE_INT_WOFFSET                    0x0
+#define MC_INTSTATUS_0_INVALID_GART_PAGE_INT_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_INTSTATUS_0_INVALID_GART_PAGE_INT_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_INTSTATUS_0_INVALID_GART_PAGE_INT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_INTSTATUS_0_INVALID_GART_PAGE_INT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_INTSTATUS_0_INVALID_GART_PAGE_INT_INIT_ENUM                  CLEAR
+#define MC_INTSTATUS_0_INVALID_GART_PAGE_INT_CLEAR                      _MK_ENUM_CONST(0)
+#define MC_INTSTATUS_0_INVALID_GART_PAGE_INT_SET                        _MK_ENUM_CONST(1)
+
+// A nonsecure access was attempted to a secured region.
+#define MC_INTSTATUS_0_SECURITY_VIOLATION_INT_SHIFT                     _MK_SHIFT_CONST(8)
+#define MC_INTSTATUS_0_SECURITY_VIOLATION_INT_FIELD                     (_MK_MASK_CONST(0x1) << MC_INTSTATUS_0_SECURITY_VIOLATION_INT_SHIFT)
+#define MC_INTSTATUS_0_SECURITY_VIOLATION_INT_RANGE                     8:8
+#define MC_INTSTATUS_0_SECURITY_VIOLATION_INT_WOFFSET                   0x0
+#define MC_INTSTATUS_0_SECURITY_VIOLATION_INT_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_INTSTATUS_0_SECURITY_VIOLATION_INT_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define MC_INTSTATUS_0_SECURITY_VIOLATION_INT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_INTSTATUS_0_SECURITY_VIOLATION_INT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_INTSTATUS_0_SECURITY_VIOLATION_INT_INIT_ENUM                 CLEAR
+#define MC_INTSTATUS_0_SECURITY_VIOLATION_INT_CLEAR                     _MK_ENUM_CONST(0)
+#define MC_INTSTATUS_0_SECURITY_VIOLATION_INT_SET                       _MK_ENUM_CONST(1)
+
+
+// Register MC_INTMASK_0  
+#define MC_INTMASK_0                    _MK_ADDR_CONST(0x4)
+#define MC_INTMASK_0_SECURE                     0x0
+#define MC_INTMASK_0_WORD_COUNT                         0x1
+#define MC_INTMASK_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define MC_INTMASK_0_RESET_MASK                         _MK_MASK_CONST(0x1c0)
+#define MC_INTMASK_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define MC_INTMASK_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_INTMASK_0_READ_MASK                  _MK_MASK_CONST(0x1c0)
+#define MC_INTMASK_0_WRITE_MASK                         _MK_MASK_CONST(0x1c0)
+// EMEM Address Decode Error for a non AXI client.
+#define MC_INTMASK_0_DECERR_EMEM_OTHERS_INTMASK_SHIFT                   _MK_SHIFT_CONST(6)
+#define MC_INTMASK_0_DECERR_EMEM_OTHERS_INTMASK_FIELD                   (_MK_MASK_CONST(0x1) << MC_INTMASK_0_DECERR_EMEM_OTHERS_INTMASK_SHIFT)
+#define MC_INTMASK_0_DECERR_EMEM_OTHERS_INTMASK_RANGE                   6:6
+#define MC_INTMASK_0_DECERR_EMEM_OTHERS_INTMASK_WOFFSET                 0x0
+#define MC_INTMASK_0_DECERR_EMEM_OTHERS_INTMASK_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_INTMASK_0_DECERR_EMEM_OTHERS_INTMASK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define MC_INTMASK_0_DECERR_EMEM_OTHERS_INTMASK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_INTMASK_0_DECERR_EMEM_OTHERS_INTMASK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_INTMASK_0_DECERR_EMEM_OTHERS_INTMASK_INIT_ENUM                       MASKED
+#define MC_INTMASK_0_DECERR_EMEM_OTHERS_INTMASK_MASKED                  _MK_ENUM_CONST(0)
+#define MC_INTMASK_0_DECERR_EMEM_OTHERS_INTMASK_UNMASKED                        _MK_ENUM_CONST(1)
+
+// A GART access was attepted to an invalid page.
+#define MC_INTMASK_0_INVALID_GART_PAGE_INTMASK_SHIFT                    _MK_SHIFT_CONST(7)
+#define MC_INTMASK_0_INVALID_GART_PAGE_INTMASK_FIELD                    (_MK_MASK_CONST(0x1) << MC_INTMASK_0_INVALID_GART_PAGE_INTMASK_SHIFT)
+#define MC_INTMASK_0_INVALID_GART_PAGE_INTMASK_RANGE                    7:7
+#define MC_INTMASK_0_INVALID_GART_PAGE_INTMASK_WOFFSET                  0x0
+#define MC_INTMASK_0_INVALID_GART_PAGE_INTMASK_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_INTMASK_0_INVALID_GART_PAGE_INTMASK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_INTMASK_0_INVALID_GART_PAGE_INTMASK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_INTMASK_0_INVALID_GART_PAGE_INTMASK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_INTMASK_0_INVALID_GART_PAGE_INTMASK_INIT_ENUM                        MASKED
+#define MC_INTMASK_0_INVALID_GART_PAGE_INTMASK_MASKED                   _MK_ENUM_CONST(0)
+#define MC_INTMASK_0_INVALID_GART_PAGE_INTMASK_UNMASKED                 _MK_ENUM_CONST(1)
+
+// A nonsecure access was attempted to a secured region.
+#define MC_INTMASK_0_SECURITY_VIOLATION_INTMASK_SHIFT                   _MK_SHIFT_CONST(8)
+#define MC_INTMASK_0_SECURITY_VIOLATION_INTMASK_FIELD                   (_MK_MASK_CONST(0x1) << MC_INTMASK_0_SECURITY_VIOLATION_INTMASK_SHIFT)
+#define MC_INTMASK_0_SECURITY_VIOLATION_INTMASK_RANGE                   8:8
+#define MC_INTMASK_0_SECURITY_VIOLATION_INTMASK_WOFFSET                 0x0
+#define MC_INTMASK_0_SECURITY_VIOLATION_INTMASK_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_INTMASK_0_SECURITY_VIOLATION_INTMASK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define MC_INTMASK_0_SECURITY_VIOLATION_INTMASK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_INTMASK_0_SECURITY_VIOLATION_INTMASK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_INTMASK_0_SECURITY_VIOLATION_INTMASK_INIT_ENUM                       MASKED
+#define MC_INTMASK_0_SECURITY_VIOLATION_INTMASK_MASKED                  _MK_ENUM_CONST(0)
+#define MC_INTMASK_0_SECURITY_VIOLATION_INTMASK_UNMASKED                        _MK_ENUM_CONST(1)
+
+
+// Reserved address 8 [0x8] 
+
+// Register MC_EMEM_CFG_0  
+#define MC_EMEM_CFG_0                   _MK_ADDR_CONST(0xc)
+#define MC_EMEM_CFG_0_SECURE                    0x0
+#define MC_EMEM_CFG_0_WORD_COUNT                        0x1
+#define MC_EMEM_CFG_0_RESET_VAL                         _MK_MASK_CONST(0x10000)
+#define MC_EMEM_CFG_0_RESET_MASK                        _MK_MASK_CONST(0x3fffff)
+#define MC_EMEM_CFG_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define MC_EMEM_CFG_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_EMEM_CFG_0_READ_MASK                         _MK_MASK_CONST(0x3fffff)
+#define MC_EMEM_CFG_0_WRITE_MASK                        _MK_MASK_CONST(0x3fffff)
+#define MC_EMEM_CFG_0_EMEM_SIZE_KB_SHIFT                        _MK_SHIFT_CONST(0)
+#define MC_EMEM_CFG_0_EMEM_SIZE_KB_FIELD                        (_MK_MASK_CONST(0x3fffff) << MC_EMEM_CFG_0_EMEM_SIZE_KB_SHIFT)
+#define MC_EMEM_CFG_0_EMEM_SIZE_KB_RANGE                        21:0
+#define MC_EMEM_CFG_0_EMEM_SIZE_KB_WOFFSET                      0x0
+#define MC_EMEM_CFG_0_EMEM_SIZE_KB_DEFAULT                      _MK_MASK_CONST(0x10000)
+#define MC_EMEM_CFG_0_EMEM_SIZE_KB_DEFAULT_MASK                 _MK_MASK_CONST(0x3fffff)
+#define MC_EMEM_CFG_0_EMEM_SIZE_KB_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_EMEM_CFG_0_EMEM_SIZE_KB_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register MC_EMEM_ADR_CFG_0  
+#define MC_EMEM_ADR_CFG_0                       _MK_ADDR_CONST(0x10)
+#define MC_EMEM_ADR_CFG_0_SECURE                        0x0
+#define MC_EMEM_ADR_CFG_0_WORD_COUNT                    0x1
+#define MC_EMEM_ADR_CFG_0_RESET_VAL                     _MK_MASK_CONST(0x40202)
+#define MC_EMEM_ADR_CFG_0_RESET_MASK                    _MK_MASK_CONST(0x30f0307)
+#define MC_EMEM_ADR_CFG_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define MC_EMEM_ADR_CFG_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_EMEM_ADR_CFG_0_READ_MASK                     _MK_MASK_CONST(0x30f0307)
+#define MC_EMEM_ADR_CFG_0_WRITE_MASK                    _MK_MASK_CONST(0x30f0307)
+#define MC_EMEM_ADR_CFG_0_EMEM_COLWIDTH_SHIFT                   _MK_SHIFT_CONST(0)
+#define MC_EMEM_ADR_CFG_0_EMEM_COLWIDTH_FIELD                   (_MK_MASK_CONST(0x7) << MC_EMEM_ADR_CFG_0_EMEM_COLWIDTH_SHIFT)
+#define MC_EMEM_ADR_CFG_0_EMEM_COLWIDTH_RANGE                   2:0
+#define MC_EMEM_ADR_CFG_0_EMEM_COLWIDTH_WOFFSET                 0x0
+#define MC_EMEM_ADR_CFG_0_EMEM_COLWIDTH_DEFAULT                 _MK_MASK_CONST(0x2)
+#define MC_EMEM_ADR_CFG_0_EMEM_COLWIDTH_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
+#define MC_EMEM_ADR_CFG_0_EMEM_COLWIDTH_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_EMEM_ADR_CFG_0_EMEM_COLWIDTH_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_EMEM_ADR_CFG_0_EMEM_COLWIDTH_INIT_ENUM                       W9
+#define MC_EMEM_ADR_CFG_0_EMEM_COLWIDTH_W7                      _MK_ENUM_CONST(0)
+#define MC_EMEM_ADR_CFG_0_EMEM_COLWIDTH_W8                      _MK_ENUM_CONST(1)
+#define MC_EMEM_ADR_CFG_0_EMEM_COLWIDTH_W9                      _MK_ENUM_CONST(2)
+#define MC_EMEM_ADR_CFG_0_EMEM_COLWIDTH_W10                     _MK_ENUM_CONST(3)
+#define MC_EMEM_ADR_CFG_0_EMEM_COLWIDTH_W11                     _MK_ENUM_CONST(4)
+
+#define MC_EMEM_ADR_CFG_0_EMEM_BANKWIDTH_SHIFT                  _MK_SHIFT_CONST(8)
+#define MC_EMEM_ADR_CFG_0_EMEM_BANKWIDTH_FIELD                  (_MK_MASK_CONST(0x3) << MC_EMEM_ADR_CFG_0_EMEM_BANKWIDTH_SHIFT)
+#define MC_EMEM_ADR_CFG_0_EMEM_BANKWIDTH_RANGE                  9:8
+#define MC_EMEM_ADR_CFG_0_EMEM_BANKWIDTH_WOFFSET                        0x0
+#define MC_EMEM_ADR_CFG_0_EMEM_BANKWIDTH_DEFAULT                        _MK_MASK_CONST(0x2)
+#define MC_EMEM_ADR_CFG_0_EMEM_BANKWIDTH_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define MC_EMEM_ADR_CFG_0_EMEM_BANKWIDTH_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_EMEM_ADR_CFG_0_EMEM_BANKWIDTH_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_EMEM_ADR_CFG_0_EMEM_BANKWIDTH_INIT_ENUM                      W2
+#define MC_EMEM_ADR_CFG_0_EMEM_BANKWIDTH_W1                     _MK_ENUM_CONST(1)
+#define MC_EMEM_ADR_CFG_0_EMEM_BANKWIDTH_W2                     _MK_ENUM_CONST(2)
+#define MC_EMEM_ADR_CFG_0_EMEM_BANKWIDTH_W3                     _MK_ENUM_CONST(3)
+
+#define MC_EMEM_ADR_CFG_0_EMEM_DEVSIZE_SHIFT                    _MK_SHIFT_CONST(16)
+#define MC_EMEM_ADR_CFG_0_EMEM_DEVSIZE_FIELD                    (_MK_MASK_CONST(0xf) << MC_EMEM_ADR_CFG_0_EMEM_DEVSIZE_SHIFT)
+#define MC_EMEM_ADR_CFG_0_EMEM_DEVSIZE_RANGE                    19:16
+#define MC_EMEM_ADR_CFG_0_EMEM_DEVSIZE_WOFFSET                  0x0
+#define MC_EMEM_ADR_CFG_0_EMEM_DEVSIZE_DEFAULT                  _MK_MASK_CONST(0x4)
+#define MC_EMEM_ADR_CFG_0_EMEM_DEVSIZE_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
+#define MC_EMEM_ADR_CFG_0_EMEM_DEVSIZE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_EMEM_ADR_CFG_0_EMEM_DEVSIZE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_EMEM_ADR_CFG_0_EMEM_DEVSIZE_INIT_ENUM                        D64MB
+#define MC_EMEM_ADR_CFG_0_EMEM_DEVSIZE_D4MB                     _MK_ENUM_CONST(0)
+#define MC_EMEM_ADR_CFG_0_EMEM_DEVSIZE_D8MB                     _MK_ENUM_CONST(1)
+#define MC_EMEM_ADR_CFG_0_EMEM_DEVSIZE_D16MB                    _MK_ENUM_CONST(2)
+#define MC_EMEM_ADR_CFG_0_EMEM_DEVSIZE_D32MB                    _MK_ENUM_CONST(3)
+#define MC_EMEM_ADR_CFG_0_EMEM_DEVSIZE_D64MB                    _MK_ENUM_CONST(4)
+#define MC_EMEM_ADR_CFG_0_EMEM_DEVSIZE_D128MB                   _MK_ENUM_CONST(5)
+#define MC_EMEM_ADR_CFG_0_EMEM_DEVSIZE_D256MB                   _MK_ENUM_CONST(6)
+#define MC_EMEM_ADR_CFG_0_EMEM_DEVSIZE_D512MB                   _MK_ENUM_CONST(7)
+#define MC_EMEM_ADR_CFG_0_EMEM_DEVSIZE_D1024MB                  _MK_ENUM_CONST(8)
+#define MC_EMEM_ADR_CFG_0_EMEM_DEVSIZE_D1GB                     _MK_ENUM_CONST(8)
+
+#define MC_EMEM_ADR_CFG_0_EMEM_NUMDEV_SHIFT                     _MK_SHIFT_CONST(24)
+#define MC_EMEM_ADR_CFG_0_EMEM_NUMDEV_FIELD                     (_MK_MASK_CONST(0x3) << MC_EMEM_ADR_CFG_0_EMEM_NUMDEV_SHIFT)
+#define MC_EMEM_ADR_CFG_0_EMEM_NUMDEV_RANGE                     25:24
+#define MC_EMEM_ADR_CFG_0_EMEM_NUMDEV_WOFFSET                   0x0
+#define MC_EMEM_ADR_CFG_0_EMEM_NUMDEV_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_EMEM_ADR_CFG_0_EMEM_NUMDEV_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define MC_EMEM_ADR_CFG_0_EMEM_NUMDEV_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_EMEM_ADR_CFG_0_EMEM_NUMDEV_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_EMEM_ADR_CFG_0_EMEM_NUMDEV_INIT_ENUM                 N1
+#define MC_EMEM_ADR_CFG_0_EMEM_NUMDEV_N1                        _MK_ENUM_CONST(0)
+#define MC_EMEM_ADR_CFG_0_EMEM_NUMDEV_N2                        _MK_ENUM_CONST(1)
+
+#define NV_MC_ARB_EMEM_SPMSB    5
+
+// Register MC_EMEM_ARB_CFG0_0  
+#define MC_EMEM_ARB_CFG0_0                      _MK_ADDR_CONST(0x14)
+#define MC_EMEM_ARB_CFG0_0_SECURE                       0x0
+#define MC_EMEM_ARB_CFG0_0_WORD_COUNT                   0x1
+#define MC_EMEM_ARB_CFG0_0_RESET_VAL                    _MK_MASK_CONST(0x102030)
+#define MC_EMEM_ARB_CFG0_0_RESET_MASK                   _MK_MASK_CONST(0x703fffff)
+#define MC_EMEM_ARB_CFG0_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG0_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG0_0_READ_MASK                    _MK_MASK_CONST(0x703fffff)
+#define MC_EMEM_ARB_CFG0_0_WRITE_MASK                   _MK_MASK_CONST(0x703fffff)
+#define MC_EMEM_ARB_CFG0_0_EMEM_RWCNT_TH_SHIFT                  _MK_SHIFT_CONST(0)
+#define MC_EMEM_ARB_CFG0_0_EMEM_RWCNT_TH_FIELD                  (_MK_MASK_CONST(0xff) << MC_EMEM_ARB_CFG0_0_EMEM_RWCNT_TH_SHIFT)
+#define MC_EMEM_ARB_CFG0_0_EMEM_RWCNT_TH_RANGE                  7:0
+#define MC_EMEM_ARB_CFG0_0_EMEM_RWCNT_TH_WOFFSET                        0x0
+#define MC_EMEM_ARB_CFG0_0_EMEM_RWCNT_TH_DEFAULT                        _MK_MASK_CONST(0x30)
+#define MC_EMEM_ARB_CFG0_0_EMEM_RWCNT_TH_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
+#define MC_EMEM_ARB_CFG0_0_EMEM_RWCNT_TH_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG0_0_EMEM_RWCNT_TH_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define MC_EMEM_ARB_CFG0_0_EMEM_WRCNT_TH_SHIFT                  _MK_SHIFT_CONST(8)
+#define MC_EMEM_ARB_CFG0_0_EMEM_WRCNT_TH_FIELD                  (_MK_MASK_CONST(0xff) << MC_EMEM_ARB_CFG0_0_EMEM_WRCNT_TH_SHIFT)
+#define MC_EMEM_ARB_CFG0_0_EMEM_WRCNT_TH_RANGE                  15:8
+#define MC_EMEM_ARB_CFG0_0_EMEM_WRCNT_TH_WOFFSET                        0x0
+#define MC_EMEM_ARB_CFG0_0_EMEM_WRCNT_TH_DEFAULT                        _MK_MASK_CONST(0x20)
+#define MC_EMEM_ARB_CFG0_0_EMEM_WRCNT_TH_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
+#define MC_EMEM_ARB_CFG0_0_EMEM_WRCNT_TH_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG0_0_EMEM_WRCNT_TH_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define MC_EMEM_ARB_CFG0_0_EMEM_SP_MAX_GRANT_OVERALL_SHIFT                      _MK_SHIFT_CONST(16)
+#define MC_EMEM_ARB_CFG0_0_EMEM_SP_MAX_GRANT_OVERALL_FIELD                      (_MK_MASK_CONST(0x3f) << MC_EMEM_ARB_CFG0_0_EMEM_SP_MAX_GRANT_OVERALL_SHIFT)
+#define MC_EMEM_ARB_CFG0_0_EMEM_SP_MAX_GRANT_OVERALL_RANGE                      21:16
+#define MC_EMEM_ARB_CFG0_0_EMEM_SP_MAX_GRANT_OVERALL_WOFFSET                    0x0
+#define MC_EMEM_ARB_CFG0_0_EMEM_SP_MAX_GRANT_OVERALL_DEFAULT                    _MK_MASK_CONST(0x10)
+#define MC_EMEM_ARB_CFG0_0_EMEM_SP_MAX_GRANT_OVERALL_DEFAULT_MASK                       _MK_MASK_CONST(0x3f)
+#define MC_EMEM_ARB_CFG0_0_EMEM_SP_MAX_GRANT_OVERALL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG0_0_EMEM_SP_MAX_GRANT_OVERALL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define MC_EMEM_ARB_CFG0_0_EMEM_CLEAR_SP_ON_AUTOPC_SHIFT                        _MK_SHIFT_CONST(28)
+#define MC_EMEM_ARB_CFG0_0_EMEM_CLEAR_SP_ON_AUTOPC_FIELD                        (_MK_MASK_CONST(0x1) << MC_EMEM_ARB_CFG0_0_EMEM_CLEAR_SP_ON_AUTOPC_SHIFT)
+#define MC_EMEM_ARB_CFG0_0_EMEM_CLEAR_SP_ON_AUTOPC_RANGE                        28:28
+#define MC_EMEM_ARB_CFG0_0_EMEM_CLEAR_SP_ON_AUTOPC_WOFFSET                      0x0
+#define MC_EMEM_ARB_CFG0_0_EMEM_CLEAR_SP_ON_AUTOPC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG0_0_EMEM_CLEAR_SP_ON_AUTOPC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_EMEM_ARB_CFG0_0_EMEM_CLEAR_SP_ON_AUTOPC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG0_0_EMEM_CLEAR_SP_ON_AUTOPC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG0_0_EMEM_CLEAR_SP_ON_AUTOPC_INIT_ENUM                    DISABLE
+#define MC_EMEM_ARB_CFG0_0_EMEM_CLEAR_SP_ON_AUTOPC_DISABLE                      _MK_ENUM_CONST(0)
+#define MC_EMEM_ARB_CFG0_0_EMEM_CLEAR_SP_ON_AUTOPC_ENABLE                       _MK_ENUM_CONST(1)
+#define MC_EMEM_ARB_CFG0_0_EMEM_CLEAR_SP_ON_AUTOPC_DISABLED                     _MK_ENUM_CONST(0)
+#define MC_EMEM_ARB_CFG0_0_EMEM_CLEAR_SP_ON_AUTOPC_ENABLED                      _MK_ENUM_CONST(1)
+
+#define MC_EMEM_ARB_CFG0_0_EMEM_CLEAR_AP_PREV_SPREQ_SHIFT                       _MK_SHIFT_CONST(29)
+#define MC_EMEM_ARB_CFG0_0_EMEM_CLEAR_AP_PREV_SPREQ_FIELD                       (_MK_MASK_CONST(0x1) << MC_EMEM_ARB_CFG0_0_EMEM_CLEAR_AP_PREV_SPREQ_SHIFT)
+#define MC_EMEM_ARB_CFG0_0_EMEM_CLEAR_AP_PREV_SPREQ_RANGE                       29:29
+#define MC_EMEM_ARB_CFG0_0_EMEM_CLEAR_AP_PREV_SPREQ_WOFFSET                     0x0
+#define MC_EMEM_ARB_CFG0_0_EMEM_CLEAR_AP_PREV_SPREQ_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG0_0_EMEM_CLEAR_AP_PREV_SPREQ_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_EMEM_ARB_CFG0_0_EMEM_CLEAR_AP_PREV_SPREQ_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG0_0_EMEM_CLEAR_AP_PREV_SPREQ_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG0_0_EMEM_CLEAR_AP_PREV_SPREQ_INIT_ENUM                   DISABLE
+#define MC_EMEM_ARB_CFG0_0_EMEM_CLEAR_AP_PREV_SPREQ_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_EMEM_ARB_CFG0_0_EMEM_CLEAR_AP_PREV_SPREQ_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_EMEM_ARB_CFG0_0_EMEM_CLEAR_AP_PREV_SPREQ_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_EMEM_ARB_CFG0_0_EMEM_CLEAR_AP_PREV_SPREQ_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_EMEM_ARB_CFG0_0_EMEM_NOBLOCK_BY_BANK_WHEN_HP_SHIFT                   _MK_SHIFT_CONST(30)
+#define MC_EMEM_ARB_CFG0_0_EMEM_NOBLOCK_BY_BANK_WHEN_HP_FIELD                   (_MK_MASK_CONST(0x1) << MC_EMEM_ARB_CFG0_0_EMEM_NOBLOCK_BY_BANK_WHEN_HP_SHIFT)
+#define MC_EMEM_ARB_CFG0_0_EMEM_NOBLOCK_BY_BANK_WHEN_HP_RANGE                   30:30
+#define MC_EMEM_ARB_CFG0_0_EMEM_NOBLOCK_BY_BANK_WHEN_HP_WOFFSET                 0x0
+#define MC_EMEM_ARB_CFG0_0_EMEM_NOBLOCK_BY_BANK_WHEN_HP_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG0_0_EMEM_NOBLOCK_BY_BANK_WHEN_HP_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define MC_EMEM_ARB_CFG0_0_EMEM_NOBLOCK_BY_BANK_WHEN_HP_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG0_0_EMEM_NOBLOCK_BY_BANK_WHEN_HP_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG0_0_EMEM_NOBLOCK_BY_BANK_WHEN_HP_INIT_ENUM                       DISABLE
+#define MC_EMEM_ARB_CFG0_0_EMEM_NOBLOCK_BY_BANK_WHEN_HP_DISABLE                 _MK_ENUM_CONST(0)
+#define MC_EMEM_ARB_CFG0_0_EMEM_NOBLOCK_BY_BANK_WHEN_HP_ENABLE                  _MK_ENUM_CONST(1)
+#define MC_EMEM_ARB_CFG0_0_EMEM_NOBLOCK_BY_BANK_WHEN_HP_DISABLED                        _MK_ENUM_CONST(0)
+#define MC_EMEM_ARB_CFG0_0_EMEM_NOBLOCK_BY_BANK_WHEN_HP_ENABLED                 _MK_ENUM_CONST(1)
+
+
+// Register MC_EMEM_ARB_CFG1_0  
+#define MC_EMEM_ARB_CFG1_0                      _MK_ADDR_CONST(0x18)
+#define MC_EMEM_ARB_CFG1_0_SECURE                       0x0
+#define MC_EMEM_ARB_CFG1_0_WORD_COUNT                   0x1
+#define MC_EMEM_ARB_CFG1_0_RESET_VAL                    _MK_MASK_CONST(0x1010f7df)
+#define MC_EMEM_ARB_CFG1_0_RESET_MASK                   _MK_MASK_CONST(0x3f3ff7df)
+#define MC_EMEM_ARB_CFG1_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG1_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG1_0_READ_MASK                    _MK_MASK_CONST(0x3f3ff7df)
+#define MC_EMEM_ARB_CFG1_0_WRITE_MASK                   _MK_MASK_CONST(0x3f3ff7df)
+#define MC_EMEM_ARB_CFG1_0_EMEM_RCL_MASK_SHIFT                  _MK_SHIFT_CONST(0)
+#define MC_EMEM_ARB_CFG1_0_EMEM_RCL_MASK_FIELD                  (_MK_MASK_CONST(0x1f) << MC_EMEM_ARB_CFG1_0_EMEM_RCL_MASK_SHIFT)
+#define MC_EMEM_ARB_CFG1_0_EMEM_RCL_MASK_RANGE                  4:0
+#define MC_EMEM_ARB_CFG1_0_EMEM_RCL_MASK_WOFFSET                        0x0
+#define MC_EMEM_ARB_CFG1_0_EMEM_RCL_MASK_DEFAULT                        _MK_MASK_CONST(0x1f)
+#define MC_EMEM_ARB_CFG1_0_EMEM_RCL_MASK_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define MC_EMEM_ARB_CFG1_0_EMEM_RCL_MASK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG1_0_EMEM_RCL_MASK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG1_0_EMEM_RCL_MASK_INIT_ENUM                      ALL
+#define MC_EMEM_ARB_CFG1_0_EMEM_RCL_MASK_NONE                   _MK_ENUM_CONST(0)
+#define MC_EMEM_ARB_CFG1_0_EMEM_RCL_MASK_ALL                    _MK_ENUM_CONST(31)
+
+#define MC_EMEM_ARB_CFG1_0_EMEM_WCL_MASK_SHIFT                  _MK_SHIFT_CONST(6)
+#define MC_EMEM_ARB_CFG1_0_EMEM_WCL_MASK_FIELD                  (_MK_MASK_CONST(0x1f) << MC_EMEM_ARB_CFG1_0_EMEM_WCL_MASK_SHIFT)
+#define MC_EMEM_ARB_CFG1_0_EMEM_WCL_MASK_RANGE                  10:6
+#define MC_EMEM_ARB_CFG1_0_EMEM_WCL_MASK_WOFFSET                        0x0
+#define MC_EMEM_ARB_CFG1_0_EMEM_WCL_MASK_DEFAULT                        _MK_MASK_CONST(0x1f)
+#define MC_EMEM_ARB_CFG1_0_EMEM_WCL_MASK_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define MC_EMEM_ARB_CFG1_0_EMEM_WCL_MASK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG1_0_EMEM_WCL_MASK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG1_0_EMEM_WCL_MASK_INIT_ENUM                      ALL
+#define MC_EMEM_ARB_CFG1_0_EMEM_WCL_MASK_NONE                   _MK_ENUM_CONST(0)
+#define MC_EMEM_ARB_CFG1_0_EMEM_WCL_MASK_ALL                    _MK_ENUM_CONST(31)
+
+#define MC_EMEM_ARB_CFG1_0_EMEM_NORWSWITCH_BKBLOCK_SHIFT                        _MK_SHIFT_CONST(12)
+#define MC_EMEM_ARB_CFG1_0_EMEM_NORWSWITCH_BKBLOCK_FIELD                        (_MK_MASK_CONST(0x1) << MC_EMEM_ARB_CFG1_0_EMEM_NORWSWITCH_BKBLOCK_SHIFT)
+#define MC_EMEM_ARB_CFG1_0_EMEM_NORWSWITCH_BKBLOCK_RANGE                        12:12
+#define MC_EMEM_ARB_CFG1_0_EMEM_NORWSWITCH_BKBLOCK_WOFFSET                      0x0
+#define MC_EMEM_ARB_CFG1_0_EMEM_NORWSWITCH_BKBLOCK_DEFAULT                      _MK_MASK_CONST(0x1)
+#define MC_EMEM_ARB_CFG1_0_EMEM_NORWSWITCH_BKBLOCK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_EMEM_ARB_CFG1_0_EMEM_NORWSWITCH_BKBLOCK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG1_0_EMEM_NORWSWITCH_BKBLOCK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG1_0_EMEM_NORWSWITCH_BKBLOCK_INIT_ENUM                    ENABLE
+#define MC_EMEM_ARB_CFG1_0_EMEM_NORWSWITCH_BKBLOCK_DISABLE                      _MK_ENUM_CONST(0)
+#define MC_EMEM_ARB_CFG1_0_EMEM_NORWSWITCH_BKBLOCK_ENABLE                       _MK_ENUM_CONST(1)
+#define MC_EMEM_ARB_CFG1_0_EMEM_NORWSWITCH_BKBLOCK_DISABLED                     _MK_ENUM_CONST(0)
+#define MC_EMEM_ARB_CFG1_0_EMEM_NORWSWITCH_BKBLOCK_ENABLED                      _MK_ENUM_CONST(1)
+
+#define MC_EMEM_ARB_CFG1_0_EMEM_NOWRSWITCH_BKBLOCK_SHIFT                        _MK_SHIFT_CONST(13)
+#define MC_EMEM_ARB_CFG1_0_EMEM_NOWRSWITCH_BKBLOCK_FIELD                        (_MK_MASK_CONST(0x1) << MC_EMEM_ARB_CFG1_0_EMEM_NOWRSWITCH_BKBLOCK_SHIFT)
+#define MC_EMEM_ARB_CFG1_0_EMEM_NOWRSWITCH_BKBLOCK_RANGE                        13:13
+#define MC_EMEM_ARB_CFG1_0_EMEM_NOWRSWITCH_BKBLOCK_WOFFSET                      0x0
+#define MC_EMEM_ARB_CFG1_0_EMEM_NOWRSWITCH_BKBLOCK_DEFAULT                      _MK_MASK_CONST(0x1)
+#define MC_EMEM_ARB_CFG1_0_EMEM_NOWRSWITCH_BKBLOCK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_EMEM_ARB_CFG1_0_EMEM_NOWRSWITCH_BKBLOCK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG1_0_EMEM_NOWRSWITCH_BKBLOCK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG1_0_EMEM_NOWRSWITCH_BKBLOCK_INIT_ENUM                    ENABLE
+#define MC_EMEM_ARB_CFG1_0_EMEM_NOWRSWITCH_BKBLOCK_DISABLE                      _MK_ENUM_CONST(0)
+#define MC_EMEM_ARB_CFG1_0_EMEM_NOWRSWITCH_BKBLOCK_ENABLE                       _MK_ENUM_CONST(1)
+#define MC_EMEM_ARB_CFG1_0_EMEM_NOWRSWITCH_BKBLOCK_DISABLED                     _MK_ENUM_CONST(0)
+#define MC_EMEM_ARB_CFG1_0_EMEM_NOWRSWITCH_BKBLOCK_ENABLED                      _MK_ENUM_CONST(1)
+
+#define MC_EMEM_ARB_CFG1_0_EMEM_RWSWITCH_RWINEXPIRED_SHIFT                      _MK_SHIFT_CONST(14)
+#define MC_EMEM_ARB_CFG1_0_EMEM_RWSWITCH_RWINEXPIRED_FIELD                      (_MK_MASK_CONST(0x1) << MC_EMEM_ARB_CFG1_0_EMEM_RWSWITCH_RWINEXPIRED_SHIFT)
+#define MC_EMEM_ARB_CFG1_0_EMEM_RWSWITCH_RWINEXPIRED_RANGE                      14:14
+#define MC_EMEM_ARB_CFG1_0_EMEM_RWSWITCH_RWINEXPIRED_WOFFSET                    0x0
+#define MC_EMEM_ARB_CFG1_0_EMEM_RWSWITCH_RWINEXPIRED_DEFAULT                    _MK_MASK_CONST(0x1)
+#define MC_EMEM_ARB_CFG1_0_EMEM_RWSWITCH_RWINEXPIRED_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_EMEM_ARB_CFG1_0_EMEM_RWSWITCH_RWINEXPIRED_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG1_0_EMEM_RWSWITCH_RWINEXPIRED_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG1_0_EMEM_RWSWITCH_RWINEXPIRED_INIT_ENUM                  ENABLE
+#define MC_EMEM_ARB_CFG1_0_EMEM_RWSWITCH_RWINEXPIRED_DISABLE                    _MK_ENUM_CONST(0)
+#define MC_EMEM_ARB_CFG1_0_EMEM_RWSWITCH_RWINEXPIRED_ENABLE                     _MK_ENUM_CONST(1)
+#define MC_EMEM_ARB_CFG1_0_EMEM_RWSWITCH_RWINEXPIRED_DISABLED                   _MK_ENUM_CONST(0)
+#define MC_EMEM_ARB_CFG1_0_EMEM_RWSWITCH_RWINEXPIRED_ENABLED                    _MK_ENUM_CONST(1)
+
+#define MC_EMEM_ARB_CFG1_0_EMEM_WRSWITCH_WWINEXPIRED_SHIFT                      _MK_SHIFT_CONST(15)
+#define MC_EMEM_ARB_CFG1_0_EMEM_WRSWITCH_WWINEXPIRED_FIELD                      (_MK_MASK_CONST(0x1) << MC_EMEM_ARB_CFG1_0_EMEM_WRSWITCH_WWINEXPIRED_SHIFT)
+#define MC_EMEM_ARB_CFG1_0_EMEM_WRSWITCH_WWINEXPIRED_RANGE                      15:15
+#define MC_EMEM_ARB_CFG1_0_EMEM_WRSWITCH_WWINEXPIRED_WOFFSET                    0x0
+#define MC_EMEM_ARB_CFG1_0_EMEM_WRSWITCH_WWINEXPIRED_DEFAULT                    _MK_MASK_CONST(0x1)
+#define MC_EMEM_ARB_CFG1_0_EMEM_WRSWITCH_WWINEXPIRED_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_EMEM_ARB_CFG1_0_EMEM_WRSWITCH_WWINEXPIRED_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG1_0_EMEM_WRSWITCH_WWINEXPIRED_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG1_0_EMEM_WRSWITCH_WWINEXPIRED_INIT_ENUM                  ENABLE
+#define MC_EMEM_ARB_CFG1_0_EMEM_WRSWITCH_WWINEXPIRED_DISABLE                    _MK_ENUM_CONST(0)
+#define MC_EMEM_ARB_CFG1_0_EMEM_WRSWITCH_WWINEXPIRED_ENABLE                     _MK_ENUM_CONST(1)
+#define MC_EMEM_ARB_CFG1_0_EMEM_WRSWITCH_WWINEXPIRED_DISABLED                   _MK_ENUM_CONST(0)
+#define MC_EMEM_ARB_CFG1_0_EMEM_WRSWITCH_WWINEXPIRED_ENABLED                    _MK_ENUM_CONST(1)
+
+#define MC_EMEM_ARB_CFG1_0_EMEM_SP_MAX_GRANT_SHIFT                      _MK_SHIFT_CONST(16)
+#define MC_EMEM_ARB_CFG1_0_EMEM_SP_MAX_GRANT_FIELD                      (_MK_MASK_CONST(0x3f) << MC_EMEM_ARB_CFG1_0_EMEM_SP_MAX_GRANT_SHIFT)
+#define MC_EMEM_ARB_CFG1_0_EMEM_SP_MAX_GRANT_RANGE                      21:16
+#define MC_EMEM_ARB_CFG1_0_EMEM_SP_MAX_GRANT_WOFFSET                    0x0
+#define MC_EMEM_ARB_CFG1_0_EMEM_SP_MAX_GRANT_DEFAULT                    _MK_MASK_CONST(0x10)
+#define MC_EMEM_ARB_CFG1_0_EMEM_SP_MAX_GRANT_DEFAULT_MASK                       _MK_MASK_CONST(0x3f)
+#define MC_EMEM_ARB_CFG1_0_EMEM_SP_MAX_GRANT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG1_0_EMEM_SP_MAX_GRANT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define MC_EMEM_ARB_CFG1_0_EMEM_SP_MAX_GRANT_RW_SHIFT                   _MK_SHIFT_CONST(24)
+#define MC_EMEM_ARB_CFG1_0_EMEM_SP_MAX_GRANT_RW_FIELD                   (_MK_MASK_CONST(0x3f) << MC_EMEM_ARB_CFG1_0_EMEM_SP_MAX_GRANT_RW_SHIFT)
+#define MC_EMEM_ARB_CFG1_0_EMEM_SP_MAX_GRANT_RW_RANGE                   29:24
+#define MC_EMEM_ARB_CFG1_0_EMEM_SP_MAX_GRANT_RW_WOFFSET                 0x0
+#define MC_EMEM_ARB_CFG1_0_EMEM_SP_MAX_GRANT_RW_DEFAULT                 _MK_MASK_CONST(0x10)
+#define MC_EMEM_ARB_CFG1_0_EMEM_SP_MAX_GRANT_RW_DEFAULT_MASK                    _MK_MASK_CONST(0x3f)
+#define MC_EMEM_ARB_CFG1_0_EMEM_SP_MAX_GRANT_RW_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG1_0_EMEM_SP_MAX_GRANT_RW_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register MC_EMEM_ARB_CFG2_0  
+#define MC_EMEM_ARB_CFG2_0                      _MK_ADDR_CONST(0x1c)
+#define MC_EMEM_ARB_CFG2_0_SECURE                       0x0
+#define MC_EMEM_ARB_CFG2_0_WORD_COUNT                   0x1
+#define MC_EMEM_ARB_CFG2_0_RESET_VAL                    _MK_MASK_CONST(0xc080c08)
+#define MC_EMEM_ARB_CFG2_0_RESET_MASK                   _MK_MASK_CONST(0x3f3f3f3f)
+#define MC_EMEM_ARB_CFG2_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG2_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG2_0_READ_MASK                    _MK_MASK_CONST(0x3f3f3f3f)
+#define MC_EMEM_ARB_CFG2_0_WRITE_MASK                   _MK_MASK_CONST(0x3f3f3f3f)
+#define MC_EMEM_ARB_CFG2_0_EMEM_BANKCNT_RD_TH_SHIFT                     _MK_SHIFT_CONST(0)
+#define MC_EMEM_ARB_CFG2_0_EMEM_BANKCNT_RD_TH_FIELD                     (_MK_MASK_CONST(0x3f) << MC_EMEM_ARB_CFG2_0_EMEM_BANKCNT_RD_TH_SHIFT)
+#define MC_EMEM_ARB_CFG2_0_EMEM_BANKCNT_RD_TH_RANGE                     5:0
+#define MC_EMEM_ARB_CFG2_0_EMEM_BANKCNT_RD_TH_WOFFSET                   0x0
+#define MC_EMEM_ARB_CFG2_0_EMEM_BANKCNT_RD_TH_DEFAULT                   _MK_MASK_CONST(0x8)
+#define MC_EMEM_ARB_CFG2_0_EMEM_BANKCNT_RD_TH_DEFAULT_MASK                      _MK_MASK_CONST(0x3f)
+#define MC_EMEM_ARB_CFG2_0_EMEM_BANKCNT_RD_TH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG2_0_EMEM_BANKCNT_RD_TH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define MC_EMEM_ARB_CFG2_0_EMEM_BANKCNT_NSP_RD_TH_SHIFT                 _MK_SHIFT_CONST(8)
+#define MC_EMEM_ARB_CFG2_0_EMEM_BANKCNT_NSP_RD_TH_FIELD                 (_MK_MASK_CONST(0x3f) << MC_EMEM_ARB_CFG2_0_EMEM_BANKCNT_NSP_RD_TH_SHIFT)
+#define MC_EMEM_ARB_CFG2_0_EMEM_BANKCNT_NSP_RD_TH_RANGE                 13:8
+#define MC_EMEM_ARB_CFG2_0_EMEM_BANKCNT_NSP_RD_TH_WOFFSET                       0x0
+#define MC_EMEM_ARB_CFG2_0_EMEM_BANKCNT_NSP_RD_TH_DEFAULT                       _MK_MASK_CONST(0xc)
+#define MC_EMEM_ARB_CFG2_0_EMEM_BANKCNT_NSP_RD_TH_DEFAULT_MASK                  _MK_MASK_CONST(0x3f)
+#define MC_EMEM_ARB_CFG2_0_EMEM_BANKCNT_NSP_RD_TH_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG2_0_EMEM_BANKCNT_NSP_RD_TH_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define MC_EMEM_ARB_CFG2_0_EMEM_BANKCNT_WR_TH_SHIFT                     _MK_SHIFT_CONST(16)
+#define MC_EMEM_ARB_CFG2_0_EMEM_BANKCNT_WR_TH_FIELD                     (_MK_MASK_CONST(0x3f) << MC_EMEM_ARB_CFG2_0_EMEM_BANKCNT_WR_TH_SHIFT)
+#define MC_EMEM_ARB_CFG2_0_EMEM_BANKCNT_WR_TH_RANGE                     21:16
+#define MC_EMEM_ARB_CFG2_0_EMEM_BANKCNT_WR_TH_WOFFSET                   0x0
+#define MC_EMEM_ARB_CFG2_0_EMEM_BANKCNT_WR_TH_DEFAULT                   _MK_MASK_CONST(0x8)
+#define MC_EMEM_ARB_CFG2_0_EMEM_BANKCNT_WR_TH_DEFAULT_MASK                      _MK_MASK_CONST(0x3f)
+#define MC_EMEM_ARB_CFG2_0_EMEM_BANKCNT_WR_TH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG2_0_EMEM_BANKCNT_WR_TH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define MC_EMEM_ARB_CFG2_0_EMEM_BANKCNT_NSP_WR_TH_SHIFT                 _MK_SHIFT_CONST(24)
+#define MC_EMEM_ARB_CFG2_0_EMEM_BANKCNT_NSP_WR_TH_FIELD                 (_MK_MASK_CONST(0x3f) << MC_EMEM_ARB_CFG2_0_EMEM_BANKCNT_NSP_WR_TH_SHIFT)
+#define MC_EMEM_ARB_CFG2_0_EMEM_BANKCNT_NSP_WR_TH_RANGE                 29:24
+#define MC_EMEM_ARB_CFG2_0_EMEM_BANKCNT_NSP_WR_TH_WOFFSET                       0x0
+#define MC_EMEM_ARB_CFG2_0_EMEM_BANKCNT_NSP_WR_TH_DEFAULT                       _MK_MASK_CONST(0xc)
+#define MC_EMEM_ARB_CFG2_0_EMEM_BANKCNT_NSP_WR_TH_DEFAULT_MASK                  _MK_MASK_CONST(0x3f)
+#define MC_EMEM_ARB_CFG2_0_EMEM_BANKCNT_NSP_WR_TH_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG2_0_EMEM_BANKCNT_NSP_WR_TH_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Reserved address 32 [0x20] 
+
+// Register MC_GART_CONFIG_0  
+#define MC_GART_CONFIG_0                        _MK_ADDR_CONST(0x24)
+#define MC_GART_CONFIG_0_SECURE                         0x0
+#define MC_GART_CONFIG_0_WORD_COUNT                     0x1
+#define MC_GART_CONFIG_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define MC_GART_CONFIG_0_RESET_MASK                     _MK_MASK_CONST(0x1)
+#define MC_GART_CONFIG_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define MC_GART_CONFIG_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_GART_CONFIG_0_READ_MASK                      _MK_MASK_CONST(0x1)
+#define MC_GART_CONFIG_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
+#define MC_GART_CONFIG_0_GART_ENABLE_SHIFT                      _MK_SHIFT_CONST(0)
+#define MC_GART_CONFIG_0_GART_ENABLE_FIELD                      (_MK_MASK_CONST(0x1) << MC_GART_CONFIG_0_GART_ENABLE_SHIFT)
+#define MC_GART_CONFIG_0_GART_ENABLE_RANGE                      0:0
+#define MC_GART_CONFIG_0_GART_ENABLE_WOFFSET                    0x0
+#define MC_GART_CONFIG_0_GART_ENABLE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_GART_CONFIG_0_GART_ENABLE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_GART_CONFIG_0_GART_ENABLE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_GART_CONFIG_0_GART_ENABLE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_GART_CONFIG_0_GART_ENABLE_INIT_ENUM                  DISABLE
+#define MC_GART_CONFIG_0_GART_ENABLE_DISABLE                    _MK_ENUM_CONST(0)
+#define MC_GART_CONFIG_0_GART_ENABLE_ENABLE                     _MK_ENUM_CONST(1)
+
+
+// Register MC_GART_ENTRY_ADDR_0  
+#define MC_GART_ENTRY_ADDR_0                    _MK_ADDR_CONST(0x28)
+#define MC_GART_ENTRY_ADDR_0_SECURE                     0x0
+#define MC_GART_ENTRY_ADDR_0_WORD_COUNT                         0x1
+#define MC_GART_ENTRY_ADDR_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define MC_GART_ENTRY_ADDR_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define MC_GART_ENTRY_ADDR_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define MC_GART_ENTRY_ADDR_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_GART_ENTRY_ADDR_0_READ_MASK                  _MK_MASK_CONST(0x1fff000)
+#define MC_GART_ENTRY_ADDR_0_WRITE_MASK                         _MK_MASK_CONST(0x1fff000)
+#define MC_GART_ENTRY_ADDR_0_GART_ENTRY_ADDR_TABLE_ADDR_SHIFT                   _MK_SHIFT_CONST(12)
+#define MC_GART_ENTRY_ADDR_0_GART_ENTRY_ADDR_TABLE_ADDR_FIELD                   (_MK_MASK_CONST(0x1fff) << MC_GART_ENTRY_ADDR_0_GART_ENTRY_ADDR_TABLE_ADDR_SHIFT)
+#define MC_GART_ENTRY_ADDR_0_GART_ENTRY_ADDR_TABLE_ADDR_RANGE                   24:12
+#define MC_GART_ENTRY_ADDR_0_GART_ENTRY_ADDR_TABLE_ADDR_WOFFSET                 0x0
+#define MC_GART_ENTRY_ADDR_0_GART_ENTRY_ADDR_TABLE_ADDR_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_GART_ENTRY_ADDR_0_GART_ENTRY_ADDR_TABLE_ADDR_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_GART_ENTRY_ADDR_0_GART_ENTRY_ADDR_TABLE_ADDR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_GART_ENTRY_ADDR_0_GART_ENTRY_ADDR_TABLE_ADDR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register MC_GART_ENTRY_DATA_0  
+#define MC_GART_ENTRY_DATA_0                    _MK_ADDR_CONST(0x2c)
+#define MC_GART_ENTRY_DATA_0_SECURE                     0x0
+#define MC_GART_ENTRY_DATA_0_WORD_COUNT                         0x1
+#define MC_GART_ENTRY_DATA_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define MC_GART_ENTRY_DATA_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define MC_GART_ENTRY_DATA_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define MC_GART_ENTRY_DATA_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_GART_ENTRY_DATA_0_READ_MASK                  _MK_MASK_CONST(0xfffff000)
+#define MC_GART_ENTRY_DATA_0_WRITE_MASK                         _MK_MASK_CONST(0xfffff000)
+#define MC_GART_ENTRY_DATA_0_GART_ENTRY_DATA_PHYS_ADDR_VALID_SHIFT                      _MK_SHIFT_CONST(31)
+#define MC_GART_ENTRY_DATA_0_GART_ENTRY_DATA_PHYS_ADDR_VALID_FIELD                      (_MK_MASK_CONST(0x1) << MC_GART_ENTRY_DATA_0_GART_ENTRY_DATA_PHYS_ADDR_VALID_SHIFT)
+#define MC_GART_ENTRY_DATA_0_GART_ENTRY_DATA_PHYS_ADDR_VALID_RANGE                      31:31
+#define MC_GART_ENTRY_DATA_0_GART_ENTRY_DATA_PHYS_ADDR_VALID_WOFFSET                    0x0
+#define MC_GART_ENTRY_DATA_0_GART_ENTRY_DATA_PHYS_ADDR_VALID_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_GART_ENTRY_DATA_0_GART_ENTRY_DATA_PHYS_ADDR_VALID_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_GART_ENTRY_DATA_0_GART_ENTRY_DATA_PHYS_ADDR_VALID_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_GART_ENTRY_DATA_0_GART_ENTRY_DATA_PHYS_ADDR_VALID_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define MC_GART_ENTRY_DATA_0_GART_ENTRY_DATA_PHYS_ADDR_SHIFT                    _MK_SHIFT_CONST(12)
+#define MC_GART_ENTRY_DATA_0_GART_ENTRY_DATA_PHYS_ADDR_FIELD                    (_MK_MASK_CONST(0x7ffff) << MC_GART_ENTRY_DATA_0_GART_ENTRY_DATA_PHYS_ADDR_SHIFT)
+#define MC_GART_ENTRY_DATA_0_GART_ENTRY_DATA_PHYS_ADDR_RANGE                    30:12
+#define MC_GART_ENTRY_DATA_0_GART_ENTRY_DATA_PHYS_ADDR_WOFFSET                  0x0
+#define MC_GART_ENTRY_DATA_0_GART_ENTRY_DATA_PHYS_ADDR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_GART_ENTRY_DATA_0_GART_ENTRY_DATA_PHYS_ADDR_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_GART_ENTRY_DATA_0_GART_ENTRY_DATA_PHYS_ADDR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_GART_ENTRY_DATA_0_GART_ENTRY_DATA_PHYS_ADDR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register MC_GART_ERROR_REQ_0  
+#define MC_GART_ERROR_REQ_0                     _MK_ADDR_CONST(0x30)
+#define MC_GART_ERROR_REQ_0_SECURE                      0x0
+#define MC_GART_ERROR_REQ_0_WORD_COUNT                  0x1
+#define MC_GART_ERROR_REQ_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define MC_GART_ERROR_REQ_0_RESET_MASK                  _MK_MASK_CONST(0x0)
+#define MC_GART_ERROR_REQ_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define MC_GART_ERROR_REQ_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_GART_ERROR_REQ_0_READ_MASK                   _MK_MASK_CONST(0x7f)
+#define MC_GART_ERROR_REQ_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define MC_GART_ERROR_REQ_0_GART_ERROR_DIRECTION_SHIFT                  _MK_SHIFT_CONST(0)
+#define MC_GART_ERROR_REQ_0_GART_ERROR_DIRECTION_FIELD                  (_MK_MASK_CONST(0x1) << MC_GART_ERROR_REQ_0_GART_ERROR_DIRECTION_SHIFT)
+#define MC_GART_ERROR_REQ_0_GART_ERROR_DIRECTION_RANGE                  0:0
+#define MC_GART_ERROR_REQ_0_GART_ERROR_DIRECTION_WOFFSET                        0x0
+#define MC_GART_ERROR_REQ_0_GART_ERROR_DIRECTION_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_GART_ERROR_REQ_0_GART_ERROR_DIRECTION_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_GART_ERROR_REQ_0_GART_ERROR_DIRECTION_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_GART_ERROR_REQ_0_GART_ERROR_DIRECTION_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_GART_ERROR_REQ_0_GART_ERROR_DIRECTION_READ                   _MK_ENUM_CONST(0)
+#define MC_GART_ERROR_REQ_0_GART_ERROR_DIRECTION_WRITE                  _MK_ENUM_CONST(1)
+
+#define MC_GART_ERROR_REQ_0_GART_ERROR_CLIENT_ID_SHIFT                  _MK_SHIFT_CONST(1)
+#define MC_GART_ERROR_REQ_0_GART_ERROR_CLIENT_ID_FIELD                  (_MK_MASK_CONST(0x3f) << MC_GART_ERROR_REQ_0_GART_ERROR_CLIENT_ID_SHIFT)
+#define MC_GART_ERROR_REQ_0_GART_ERROR_CLIENT_ID_RANGE                  6:1
+#define MC_GART_ERROR_REQ_0_GART_ERROR_CLIENT_ID_WOFFSET                        0x0
+#define MC_GART_ERROR_REQ_0_GART_ERROR_CLIENT_ID_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_GART_ERROR_REQ_0_GART_ERROR_CLIENT_ID_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_GART_ERROR_REQ_0_GART_ERROR_CLIENT_ID_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_GART_ERROR_REQ_0_GART_ERROR_CLIENT_ID_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register MC_GART_ERROR_ADDR_0  
+#define MC_GART_ERROR_ADDR_0                    _MK_ADDR_CONST(0x34)
+#define MC_GART_ERROR_ADDR_0_SECURE                     0x0
+#define MC_GART_ERROR_ADDR_0_WORD_COUNT                         0x1
+#define MC_GART_ERROR_ADDR_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define MC_GART_ERROR_ADDR_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define MC_GART_ERROR_ADDR_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define MC_GART_ERROR_ADDR_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_GART_ERROR_ADDR_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define MC_GART_ERROR_ADDR_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
+#define MC_GART_ERROR_ADDR_0_GART_ERROR_ADDRESS_SHIFT                   _MK_SHIFT_CONST(0)
+#define MC_GART_ERROR_ADDR_0_GART_ERROR_ADDRESS_FIELD                   (_MK_MASK_CONST(0xffffffff) << MC_GART_ERROR_ADDR_0_GART_ERROR_ADDRESS_SHIFT)
+#define MC_GART_ERROR_ADDR_0_GART_ERROR_ADDRESS_RANGE                   31:0
+#define MC_GART_ERROR_ADDR_0_GART_ERROR_ADDRESS_WOFFSET                 0x0
+#define MC_GART_ERROR_ADDR_0_GART_ERROR_ADDRESS_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_GART_ERROR_ADDR_0_GART_ERROR_ADDRESS_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_GART_ERROR_ADDR_0_GART_ERROR_ADDRESS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_GART_ERROR_ADDR_0_GART_ERROR_ADDRESS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Reserved address 56 [0x38] 
+
+// Register MC_TIMEOUT_CTRL_0  
+#define MC_TIMEOUT_CTRL_0                       _MK_ADDR_CONST(0x3c)
+#define MC_TIMEOUT_CTRL_0_SECURE                        0x0
+#define MC_TIMEOUT_CTRL_0_WORD_COUNT                    0x1
+#define MC_TIMEOUT_CTRL_0_RESET_VAL                     _MK_MASK_CONST(0x28)
+#define MC_TIMEOUT_CTRL_0_RESET_MASK                    _MK_MASK_CONST(0x78)
+#define MC_TIMEOUT_CTRL_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_CTRL_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_CTRL_0_READ_MASK                     _MK_MASK_CONST(0x78)
+#define MC_TIMEOUT_CTRL_0_WRITE_MASK                    _MK_MASK_CONST(0x78)
+#define MC_TIMEOUT_CTRL_0_EMEM_TM_SFACTOR_SHIFT                 _MK_SHIFT_CONST(3)
+#define MC_TIMEOUT_CTRL_0_EMEM_TM_SFACTOR_FIELD                 (_MK_MASK_CONST(0x7) << MC_TIMEOUT_CTRL_0_EMEM_TM_SFACTOR_SHIFT)
+#define MC_TIMEOUT_CTRL_0_EMEM_TM_SFACTOR_RANGE                 5:3
+#define MC_TIMEOUT_CTRL_0_EMEM_TM_SFACTOR_WOFFSET                       0x0
+#define MC_TIMEOUT_CTRL_0_EMEM_TM_SFACTOR_DEFAULT                       _MK_MASK_CONST(0x5)
+#define MC_TIMEOUT_CTRL_0_EMEM_TM_SFACTOR_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
+#define MC_TIMEOUT_CTRL_0_EMEM_TM_SFACTOR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_CTRL_0_EMEM_TM_SFACTOR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_CTRL_0_TMCREDITS_SHIFT                       _MK_SHIFT_CONST(6)
+#define MC_TIMEOUT_CTRL_0_TMCREDITS_FIELD                       (_MK_MASK_CONST(0x1) << MC_TIMEOUT_CTRL_0_TMCREDITS_SHIFT)
+#define MC_TIMEOUT_CTRL_0_TMCREDITS_RANGE                       6:6
+#define MC_TIMEOUT_CTRL_0_TMCREDITS_WOFFSET                     0x0
+#define MC_TIMEOUT_CTRL_0_TMCREDITS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_CTRL_0_TMCREDITS_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_TIMEOUT_CTRL_0_TMCREDITS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_CTRL_0_TMCREDITS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_CTRL_0_TMCREDITS_INIT_ENUM                   FROM_CIF_FIFO
+#define MC_TIMEOUT_CTRL_0_TMCREDITS_FROM_CIF_FIFO                       _MK_ENUM_CONST(0)
+#define MC_TIMEOUT_CTRL_0_TMCREDITS_ONE                 _MK_ENUM_CONST(1)
+
+
+// Reserved address 64 [0x40] 
+
+// Reserved address 68 [0x44] 
+
+// Reserved address 72 [0x48] 
+
+// Reserved address 76 [0x4c] 
+
+// Reserved address 80 [0x50] 
+
+// Reserved address 84 [0x54] 
+
+// Register MC_DECERR_EMEM_OTHERS_STATUS_0  
+#define MC_DECERR_EMEM_OTHERS_STATUS_0                  _MK_ADDR_CONST(0x58)
+#define MC_DECERR_EMEM_OTHERS_STATUS_0_SECURE                   0x0
+#define MC_DECERR_EMEM_OTHERS_STATUS_0_WORD_COUNT                       0x1
+#define MC_DECERR_EMEM_OTHERS_STATUS_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define MC_DECERR_EMEM_OTHERS_STATUS_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define MC_DECERR_EMEM_OTHERS_STATUS_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define MC_DECERR_EMEM_OTHERS_STATUS_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_DECERR_EMEM_OTHERS_STATUS_0_READ_MASK                        _MK_MASK_CONST(0x8000003f)
+#define MC_DECERR_EMEM_OTHERS_STATUS_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
+#define MC_DECERR_EMEM_OTHERS_STATUS_0_DECERR_EMEM_OTHERS_ID_SHIFT                      _MK_SHIFT_CONST(0)
+#define MC_DECERR_EMEM_OTHERS_STATUS_0_DECERR_EMEM_OTHERS_ID_FIELD                      (_MK_MASK_CONST(0x3f) << MC_DECERR_EMEM_OTHERS_STATUS_0_DECERR_EMEM_OTHERS_ID_SHIFT)
+#define MC_DECERR_EMEM_OTHERS_STATUS_0_DECERR_EMEM_OTHERS_ID_RANGE                      5:0
+#define MC_DECERR_EMEM_OTHERS_STATUS_0_DECERR_EMEM_OTHERS_ID_WOFFSET                    0x0
+#define MC_DECERR_EMEM_OTHERS_STATUS_0_DECERR_EMEM_OTHERS_ID_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_DECERR_EMEM_OTHERS_STATUS_0_DECERR_EMEM_OTHERS_ID_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_DECERR_EMEM_OTHERS_STATUS_0_DECERR_EMEM_OTHERS_ID_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_DECERR_EMEM_OTHERS_STATUS_0_DECERR_EMEM_OTHERS_ID_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define MC_DECERR_EMEM_OTHERS_STATUS_0_DECERR_EMEM_OTHERS_RW_SHIFT                      _MK_SHIFT_CONST(31)
+#define MC_DECERR_EMEM_OTHERS_STATUS_0_DECERR_EMEM_OTHERS_RW_FIELD                      (_MK_MASK_CONST(0x1) << MC_DECERR_EMEM_OTHERS_STATUS_0_DECERR_EMEM_OTHERS_RW_SHIFT)
+#define MC_DECERR_EMEM_OTHERS_STATUS_0_DECERR_EMEM_OTHERS_RW_RANGE                      31:31
+#define MC_DECERR_EMEM_OTHERS_STATUS_0_DECERR_EMEM_OTHERS_RW_WOFFSET                    0x0
+#define MC_DECERR_EMEM_OTHERS_STATUS_0_DECERR_EMEM_OTHERS_RW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_DECERR_EMEM_OTHERS_STATUS_0_DECERR_EMEM_OTHERS_RW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_DECERR_EMEM_OTHERS_STATUS_0_DECERR_EMEM_OTHERS_RW_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_DECERR_EMEM_OTHERS_STATUS_0_DECERR_EMEM_OTHERS_RW_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_DECERR_EMEM_OTHERS_STATUS_0_DECERR_EMEM_OTHERS_RW_READ                       _MK_ENUM_CONST(0)
+#define MC_DECERR_EMEM_OTHERS_STATUS_0_DECERR_EMEM_OTHERS_RW_WRITE                      _MK_ENUM_CONST(1)
+
+
+// Register MC_DECERR_EMEM_OTHERS_ADR_0  
+#define MC_DECERR_EMEM_OTHERS_ADR_0                     _MK_ADDR_CONST(0x5c)
+#define MC_DECERR_EMEM_OTHERS_ADR_0_SECURE                      0x0
+#define MC_DECERR_EMEM_OTHERS_ADR_0_WORD_COUNT                  0x1
+#define MC_DECERR_EMEM_OTHERS_ADR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define MC_DECERR_EMEM_OTHERS_ADR_0_RESET_MASK                  _MK_MASK_CONST(0x0)
+#define MC_DECERR_EMEM_OTHERS_ADR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define MC_DECERR_EMEM_OTHERS_ADR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_DECERR_EMEM_OTHERS_ADR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define MC_DECERR_EMEM_OTHERS_ADR_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define MC_DECERR_EMEM_OTHERS_ADR_0_DECERR_EMEM_OTHERS_ADR_SHIFT                        _MK_SHIFT_CONST(0)
+#define MC_DECERR_EMEM_OTHERS_ADR_0_DECERR_EMEM_OTHERS_ADR_FIELD                        (_MK_MASK_CONST(0xffffffff) << MC_DECERR_EMEM_OTHERS_ADR_0_DECERR_EMEM_OTHERS_ADR_SHIFT)
+#define MC_DECERR_EMEM_OTHERS_ADR_0_DECERR_EMEM_OTHERS_ADR_RANGE                        31:0
+#define MC_DECERR_EMEM_OTHERS_ADR_0_DECERR_EMEM_OTHERS_ADR_WOFFSET                      0x0
+#define MC_DECERR_EMEM_OTHERS_ADR_0_DECERR_EMEM_OTHERS_ADR_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_DECERR_EMEM_OTHERS_ADR_0_DECERR_EMEM_OTHERS_ADR_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_DECERR_EMEM_OTHERS_ADR_0_DECERR_EMEM_OTHERS_ADR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_DECERR_EMEM_OTHERS_ADR_0_DECERR_EMEM_OTHERS_ADR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Reserved address 96 [0x60] 
+
+// Reserved address 100 [0x64] 
+
+// Register MC_CLKEN_OVERRIDE_0  
+#define MC_CLKEN_OVERRIDE_0                     _MK_ADDR_CONST(0x68)
+#define MC_CLKEN_OVERRIDE_0_SECURE                      0x0
+#define MC_CLKEN_OVERRIDE_0_WORD_COUNT                  0x1
+#define MC_CLKEN_OVERRIDE_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define MC_CLKEN_OVERRIDE_0_RESET_MASK                  _MK_MASK_CONST(0x1d)
+#define MC_CLKEN_OVERRIDE_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define MC_CLKEN_OVERRIDE_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_CLKEN_OVERRIDE_0_READ_MASK                   _MK_MASK_CONST(0x1d)
+#define MC_CLKEN_OVERRIDE_0_WRITE_MASK                  _MK_MASK_CONST(0x1d)
+#define MC_CLKEN_OVERRIDE_0_CIF_CLKEN_OVR_SHIFT                 _MK_SHIFT_CONST(0)
+#define MC_CLKEN_OVERRIDE_0_CIF_CLKEN_OVR_FIELD                 (_MK_MASK_CONST(0x1) << MC_CLKEN_OVERRIDE_0_CIF_CLKEN_OVR_SHIFT)
+#define MC_CLKEN_OVERRIDE_0_CIF_CLKEN_OVR_RANGE                 0:0
+#define MC_CLKEN_OVERRIDE_0_CIF_CLKEN_OVR_WOFFSET                       0x0
+#define MC_CLKEN_OVERRIDE_0_CIF_CLKEN_OVR_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_CLKEN_OVERRIDE_0_CIF_CLKEN_OVR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_CLKEN_OVERRIDE_0_CIF_CLKEN_OVR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_CLKEN_OVERRIDE_0_CIF_CLKEN_OVR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_CLKEN_OVERRIDE_0_CIF_CLKEN_OVR_INIT_ENUM                     CLK_GATED
+#define MC_CLKEN_OVERRIDE_0_CIF_CLKEN_OVR_CLK_GATED                     _MK_ENUM_CONST(0)
+#define MC_CLKEN_OVERRIDE_0_CIF_CLKEN_OVR_CLK_ALWAYS_ON                 _MK_ENUM_CONST(1)
+#define MC_CLKEN_OVERRIDE_0_CIF_CLKEN_OVR_DISABLE                       _MK_ENUM_CONST(0)
+#define MC_CLKEN_OVERRIDE_0_CIF_CLKEN_OVR_ENABLE                        _MK_ENUM_CONST(1)
+#define MC_CLKEN_OVERRIDE_0_CIF_CLKEN_OVR_DISABLED                      _MK_ENUM_CONST(0)
+#define MC_CLKEN_OVERRIDE_0_CIF_CLKEN_OVR_ENABLED                       _MK_ENUM_CONST(1)
+
+#define MC_CLKEN_OVERRIDE_0_ESEQ_CLKEN_OVR_SHIFT                        _MK_SHIFT_CONST(2)
+#define MC_CLKEN_OVERRIDE_0_ESEQ_CLKEN_OVR_FIELD                        (_MK_MASK_CONST(0x1) << MC_CLKEN_OVERRIDE_0_ESEQ_CLKEN_OVR_SHIFT)
+#define MC_CLKEN_OVERRIDE_0_ESEQ_CLKEN_OVR_RANGE                        2:2
+#define MC_CLKEN_OVERRIDE_0_ESEQ_CLKEN_OVR_WOFFSET                      0x0
+#define MC_CLKEN_OVERRIDE_0_ESEQ_CLKEN_OVR_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_CLKEN_OVERRIDE_0_ESEQ_CLKEN_OVR_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_CLKEN_OVERRIDE_0_ESEQ_CLKEN_OVR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_CLKEN_OVERRIDE_0_ESEQ_CLKEN_OVR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_CLKEN_OVERRIDE_0_ESEQ_CLKEN_OVR_INIT_ENUM                    CLK_GATED
+#define MC_CLKEN_OVERRIDE_0_ESEQ_CLKEN_OVR_CLK_GATED                    _MK_ENUM_CONST(0)
+#define MC_CLKEN_OVERRIDE_0_ESEQ_CLKEN_OVR_CLK_ALWAYS_ON                        _MK_ENUM_CONST(1)
+#define MC_CLKEN_OVERRIDE_0_ESEQ_CLKEN_OVR_DISABLE                      _MK_ENUM_CONST(0)
+#define MC_CLKEN_OVERRIDE_0_ESEQ_CLKEN_OVR_ENABLE                       _MK_ENUM_CONST(1)
+#define MC_CLKEN_OVERRIDE_0_ESEQ_CLKEN_OVR_DISABLED                     _MK_ENUM_CONST(0)
+#define MC_CLKEN_OVERRIDE_0_ESEQ_CLKEN_OVR_ENABLED                      _MK_ENUM_CONST(1)
+
+#define MC_CLKEN_OVERRIDE_0_REGS_CLKEN_OVR_SHIFT                        _MK_SHIFT_CONST(3)
+#define MC_CLKEN_OVERRIDE_0_REGS_CLKEN_OVR_FIELD                        (_MK_MASK_CONST(0x1) << MC_CLKEN_OVERRIDE_0_REGS_CLKEN_OVR_SHIFT)
+#define MC_CLKEN_OVERRIDE_0_REGS_CLKEN_OVR_RANGE                        3:3
+#define MC_CLKEN_OVERRIDE_0_REGS_CLKEN_OVR_WOFFSET                      0x0
+#define MC_CLKEN_OVERRIDE_0_REGS_CLKEN_OVR_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_CLKEN_OVERRIDE_0_REGS_CLKEN_OVR_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_CLKEN_OVERRIDE_0_REGS_CLKEN_OVR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_CLKEN_OVERRIDE_0_REGS_CLKEN_OVR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_CLKEN_OVERRIDE_0_REGS_CLKEN_OVR_INIT_ENUM                    CLK_GATED
+#define MC_CLKEN_OVERRIDE_0_REGS_CLKEN_OVR_CLK_GATED                    _MK_ENUM_CONST(0)
+#define MC_CLKEN_OVERRIDE_0_REGS_CLKEN_OVR_CLK_ALWAYS_ON                        _MK_ENUM_CONST(1)
+#define MC_CLKEN_OVERRIDE_0_REGS_CLKEN_OVR_DISABLE                      _MK_ENUM_CONST(0)
+#define MC_CLKEN_OVERRIDE_0_REGS_CLKEN_OVR_ENABLE                       _MK_ENUM_CONST(1)
+#define MC_CLKEN_OVERRIDE_0_REGS_CLKEN_OVR_DISABLED                     _MK_ENUM_CONST(0)
+#define MC_CLKEN_OVERRIDE_0_REGS_CLKEN_OVR_ENABLED                      _MK_ENUM_CONST(1)
+
+#define MC_CLKEN_OVERRIDE_0_GART_CLKEN_OVR_SHIFT                        _MK_SHIFT_CONST(4)
+#define MC_CLKEN_OVERRIDE_0_GART_CLKEN_OVR_FIELD                        (_MK_MASK_CONST(0x1) << MC_CLKEN_OVERRIDE_0_GART_CLKEN_OVR_SHIFT)
+#define MC_CLKEN_OVERRIDE_0_GART_CLKEN_OVR_RANGE                        4:4
+#define MC_CLKEN_OVERRIDE_0_GART_CLKEN_OVR_WOFFSET                      0x0
+#define MC_CLKEN_OVERRIDE_0_GART_CLKEN_OVR_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_CLKEN_OVERRIDE_0_GART_CLKEN_OVR_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_CLKEN_OVERRIDE_0_GART_CLKEN_OVR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_CLKEN_OVERRIDE_0_GART_CLKEN_OVR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_CLKEN_OVERRIDE_0_GART_CLKEN_OVR_INIT_ENUM                    CLK_GATED
+#define MC_CLKEN_OVERRIDE_0_GART_CLKEN_OVR_CLK_GATED                    _MK_ENUM_CONST(0)
+#define MC_CLKEN_OVERRIDE_0_GART_CLKEN_OVR_CLK_ALWAYS_ON                        _MK_ENUM_CONST(1)
+#define MC_CLKEN_OVERRIDE_0_GART_CLKEN_OVR_DISABLE                      _MK_ENUM_CONST(0)
+#define MC_CLKEN_OVERRIDE_0_GART_CLKEN_OVR_ENABLE                       _MK_ENUM_CONST(1)
+#define MC_CLKEN_OVERRIDE_0_GART_CLKEN_OVR_DISABLED                     _MK_ENUM_CONST(0)
+#define MC_CLKEN_OVERRIDE_0_GART_CLKEN_OVR_ENABLED                      _MK_ENUM_CONST(1)
+
+
+// Register MC_SECURITY_CFG0_0  
+#define MC_SECURITY_CFG0_0                      _MK_ADDR_CONST(0x6c)
+#define MC_SECURITY_CFG0_0_SECURE                       0x1
+#define MC_SECURITY_CFG0_0_WORD_COUNT                   0x1
+#define MC_SECURITY_CFG0_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define MC_SECURITY_CFG0_0_RESET_MASK                   _MK_MASK_CONST(0xfff00000)
+#define MC_SECURITY_CFG0_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define MC_SECURITY_CFG0_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_SECURITY_CFG0_0_READ_MASK                    _MK_MASK_CONST(0xfff00000)
+#define MC_SECURITY_CFG0_0_WRITE_MASK                   _MK_MASK_CONST(0xfff00000)
+#define MC_SECURITY_CFG0_0_SECURITY_BOM_SHIFT                   _MK_SHIFT_CONST(20)
+#define MC_SECURITY_CFG0_0_SECURITY_BOM_FIELD                   (_MK_MASK_CONST(0xfff) << MC_SECURITY_CFG0_0_SECURITY_BOM_SHIFT)
+#define MC_SECURITY_CFG0_0_SECURITY_BOM_RANGE                   31:20
+#define MC_SECURITY_CFG0_0_SECURITY_BOM_WOFFSET                 0x0
+#define MC_SECURITY_CFG0_0_SECURITY_BOM_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_SECURITY_CFG0_0_SECURITY_BOM_DEFAULT_MASK                    _MK_MASK_CONST(0xfff)
+#define MC_SECURITY_CFG0_0_SECURITY_BOM_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_SECURITY_CFG0_0_SECURITY_BOM_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register MC_SECURITY_CFG1_0  
+#define MC_SECURITY_CFG1_0                      _MK_ADDR_CONST(0x70)
+#define MC_SECURITY_CFG1_0_SECURE                       0x1
+#define MC_SECURITY_CFG1_0_WORD_COUNT                   0x1
+#define MC_SECURITY_CFG1_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define MC_SECURITY_CFG1_0_RESET_MASK                   _MK_MASK_CONST(0xfff)
+#define MC_SECURITY_CFG1_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define MC_SECURITY_CFG1_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_SECURITY_CFG1_0_READ_MASK                    _MK_MASK_CONST(0xfff)
+#define MC_SECURITY_CFG1_0_WRITE_MASK                   _MK_MASK_CONST(0xfff)
+#define MC_SECURITY_CFG1_0_SECURITY_SIZE_MB_SHIFT                       _MK_SHIFT_CONST(0)
+#define MC_SECURITY_CFG1_0_SECURITY_SIZE_MB_FIELD                       (_MK_MASK_CONST(0xfff) << MC_SECURITY_CFG1_0_SECURITY_SIZE_MB_SHIFT)
+#define MC_SECURITY_CFG1_0_SECURITY_SIZE_MB_RANGE                       11:0
+#define MC_SECURITY_CFG1_0_SECURITY_SIZE_MB_WOFFSET                     0x0
+#define MC_SECURITY_CFG1_0_SECURITY_SIZE_MB_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_SECURITY_CFG1_0_SECURITY_SIZE_MB_DEFAULT_MASK                        _MK_MASK_CONST(0xfff)
+#define MC_SECURITY_CFG1_0_SECURITY_SIZE_MB_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_SECURITY_CFG1_0_SECURITY_SIZE_MB_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register MC_SECURITY_VIOLATION_STATUS_0  
+#define MC_SECURITY_VIOLATION_STATUS_0                  _MK_ADDR_CONST(0x74)
+#define MC_SECURITY_VIOLATION_STATUS_0_SECURE                   0x0
+#define MC_SECURITY_VIOLATION_STATUS_0_WORD_COUNT                       0x1
+#define MC_SECURITY_VIOLATION_STATUS_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define MC_SECURITY_VIOLATION_STATUS_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define MC_SECURITY_VIOLATION_STATUS_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define MC_SECURITY_VIOLATION_STATUS_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_SECURITY_VIOLATION_STATUS_0_READ_MASK                        _MK_MASK_CONST(0xc000003f)
+#define MC_SECURITY_VIOLATION_STATUS_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
+#define MC_SECURITY_VIOLATION_STATUS_0_SECURITY_VIOLATION_ID_SHIFT                      _MK_SHIFT_CONST(0)
+#define MC_SECURITY_VIOLATION_STATUS_0_SECURITY_VIOLATION_ID_FIELD                      (_MK_MASK_CONST(0x3f) << MC_SECURITY_VIOLATION_STATUS_0_SECURITY_VIOLATION_ID_SHIFT)
+#define MC_SECURITY_VIOLATION_STATUS_0_SECURITY_VIOLATION_ID_RANGE                      5:0
+#define MC_SECURITY_VIOLATION_STATUS_0_SECURITY_VIOLATION_ID_WOFFSET                    0x0
+#define MC_SECURITY_VIOLATION_STATUS_0_SECURITY_VIOLATION_ID_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_SECURITY_VIOLATION_STATUS_0_SECURITY_VIOLATION_ID_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_SECURITY_VIOLATION_STATUS_0_SECURITY_VIOLATION_ID_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_SECURITY_VIOLATION_STATUS_0_SECURITY_VIOLATION_ID_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define MC_SECURITY_VIOLATION_STATUS_0_SECURITY_VIOLATION_TYPE_SHIFT                    _MK_SHIFT_CONST(30)
+#define MC_SECURITY_VIOLATION_STATUS_0_SECURITY_VIOLATION_TYPE_FIELD                    (_MK_MASK_CONST(0x1) << MC_SECURITY_VIOLATION_STATUS_0_SECURITY_VIOLATION_TYPE_SHIFT)
+#define MC_SECURITY_VIOLATION_STATUS_0_SECURITY_VIOLATION_TYPE_RANGE                    30:30
+#define MC_SECURITY_VIOLATION_STATUS_0_SECURITY_VIOLATION_TYPE_WOFFSET                  0x0
+#define MC_SECURITY_VIOLATION_STATUS_0_SECURITY_VIOLATION_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_SECURITY_VIOLATION_STATUS_0_SECURITY_VIOLATION_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_SECURITY_VIOLATION_STATUS_0_SECURITY_VIOLATION_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_SECURITY_VIOLATION_STATUS_0_SECURITY_VIOLATION_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_SECURITY_VIOLATION_STATUS_0_SECURITY_VIOLATION_TYPE_TRUSTZONE                        _MK_ENUM_CONST(0)
+#define MC_SECURITY_VIOLATION_STATUS_0_SECURITY_VIOLATION_TYPE_CARVEOUT                 _MK_ENUM_CONST(1)
+
+#define MC_SECURITY_VIOLATION_STATUS_0_SECURITY_VIOLATION_RW_SHIFT                      _MK_SHIFT_CONST(31)
+#define MC_SECURITY_VIOLATION_STATUS_0_SECURITY_VIOLATION_RW_FIELD                      (_MK_MASK_CONST(0x1) << MC_SECURITY_VIOLATION_STATUS_0_SECURITY_VIOLATION_RW_SHIFT)
+#define MC_SECURITY_VIOLATION_STATUS_0_SECURITY_VIOLATION_RW_RANGE                      31:31
+#define MC_SECURITY_VIOLATION_STATUS_0_SECURITY_VIOLATION_RW_WOFFSET                    0x0
+#define MC_SECURITY_VIOLATION_STATUS_0_SECURITY_VIOLATION_RW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_SECURITY_VIOLATION_STATUS_0_SECURITY_VIOLATION_RW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_SECURITY_VIOLATION_STATUS_0_SECURITY_VIOLATION_RW_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_SECURITY_VIOLATION_STATUS_0_SECURITY_VIOLATION_RW_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_SECURITY_VIOLATION_STATUS_0_SECURITY_VIOLATION_RW_READ                       _MK_ENUM_CONST(0)
+#define MC_SECURITY_VIOLATION_STATUS_0_SECURITY_VIOLATION_RW_WRITE                      _MK_ENUM_CONST(1)
+
+
+// Register MC_SECURITY_VIOLATION_ADR_0  
+#define MC_SECURITY_VIOLATION_ADR_0                     _MK_ADDR_CONST(0x78)
+#define MC_SECURITY_VIOLATION_ADR_0_SECURE                      0x0
+#define MC_SECURITY_VIOLATION_ADR_0_WORD_COUNT                  0x1
+#define MC_SECURITY_VIOLATION_ADR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define MC_SECURITY_VIOLATION_ADR_0_RESET_MASK                  _MK_MASK_CONST(0x0)
+#define MC_SECURITY_VIOLATION_ADR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define MC_SECURITY_VIOLATION_ADR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_SECURITY_VIOLATION_ADR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define MC_SECURITY_VIOLATION_ADR_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define MC_SECURITY_VIOLATION_ADR_0_SECURITY_VIOLATION_ADR_SHIFT                        _MK_SHIFT_CONST(0)
+#define MC_SECURITY_VIOLATION_ADR_0_SECURITY_VIOLATION_ADR_FIELD                        (_MK_MASK_CONST(0xffffffff) << MC_SECURITY_VIOLATION_ADR_0_SECURITY_VIOLATION_ADR_SHIFT)
+#define MC_SECURITY_VIOLATION_ADR_0_SECURITY_VIOLATION_ADR_RANGE                        31:0
+#define MC_SECURITY_VIOLATION_ADR_0_SECURITY_VIOLATION_ADR_WOFFSET                      0x0
+#define MC_SECURITY_VIOLATION_ADR_0_SECURITY_VIOLATION_ADR_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_SECURITY_VIOLATION_ADR_0_SECURITY_VIOLATION_ADR_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_SECURITY_VIOLATION_ADR_0_SECURITY_VIOLATION_ADR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_SECURITY_VIOLATION_ADR_0_SECURITY_VIOLATION_ADR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register MC_SECURITY_CFG2_0  
+#define MC_SECURITY_CFG2_0                      _MK_ADDR_CONST(0x7c)
+#define MC_SECURITY_CFG2_0_SECURE                       0x1
+#define MC_SECURITY_CFG2_0_WORD_COUNT                   0x1
+#define MC_SECURITY_CFG2_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define MC_SECURITY_CFG2_0_RESET_MASK                   _MK_MASK_CONST(0xfff00000)
+#define MC_SECURITY_CFG2_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define MC_SECURITY_CFG2_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_SECURITY_CFG2_0_READ_MASK                    _MK_MASK_CONST(0xfff00000)
+#define MC_SECURITY_CFG2_0_WRITE_MASK                   _MK_MASK_CONST(0xfff00000)
+#define MC_SECURITY_CFG2_0_CARVEOUT_BOM_SHIFT                   _MK_SHIFT_CONST(20)
+#define MC_SECURITY_CFG2_0_CARVEOUT_BOM_FIELD                   (_MK_MASK_CONST(0xfff) << MC_SECURITY_CFG2_0_CARVEOUT_BOM_SHIFT)
+#define MC_SECURITY_CFG2_0_CARVEOUT_BOM_RANGE                   31:20
+#define MC_SECURITY_CFG2_0_CARVEOUT_BOM_WOFFSET                 0x0
+#define MC_SECURITY_CFG2_0_CARVEOUT_BOM_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_SECURITY_CFG2_0_CARVEOUT_BOM_DEFAULT_MASK                    _MK_MASK_CONST(0xfff)
+#define MC_SECURITY_CFG2_0_CARVEOUT_BOM_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_SECURITY_CFG2_0_CARVEOUT_BOM_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Reserved address 128 [0x80] 
+
+// Reserved address 132 [0x84] 
+
+// Reserved address 136 [0x88] 
+
+// Reserved address 140 [0x8c] 
+
+// Register MC_STAT_CONTROL_0  
+#define MC_STAT_CONTROL_0                       _MK_ADDR_CONST(0x90)
+#define MC_STAT_CONTROL_0_SECURE                        0x0
+#define MC_STAT_CONTROL_0_WORD_COUNT                    0x1
+#define MC_STAT_CONTROL_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define MC_STAT_CONTROL_0_RESET_MASK                    _MK_MASK_CONST(0x300)
+#define MC_STAT_CONTROL_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define MC_STAT_CONTROL_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_STAT_CONTROL_0_READ_MASK                     _MK_MASK_CONST(0x300)
+#define MC_STAT_CONTROL_0_WRITE_MASK                    _MK_MASK_CONST(0x300)
+#define MC_STAT_CONTROL_0_EMC_GATHER_SHIFT                      _MK_SHIFT_CONST(8)
+#define MC_STAT_CONTROL_0_EMC_GATHER_FIELD                      (_MK_MASK_CONST(0x3) << MC_STAT_CONTROL_0_EMC_GATHER_SHIFT)
+#define MC_STAT_CONTROL_0_EMC_GATHER_RANGE                      9:8
+#define MC_STAT_CONTROL_0_EMC_GATHER_WOFFSET                    0x0
+#define MC_STAT_CONTROL_0_EMC_GATHER_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_STAT_CONTROL_0_EMC_GATHER_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define MC_STAT_CONTROL_0_EMC_GATHER_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_STAT_CONTROL_0_EMC_GATHER_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_STAT_CONTROL_0_EMC_GATHER_INIT_ENUM                  RST
+#define MC_STAT_CONTROL_0_EMC_GATHER_RST                        _MK_ENUM_CONST(0)
+#define MC_STAT_CONTROL_0_EMC_GATHER_CLEAR                      _MK_ENUM_CONST(1)
+#define MC_STAT_CONTROL_0_EMC_GATHER_DISABLE                    _MK_ENUM_CONST(2)
+#define MC_STAT_CONTROL_0_EMC_GATHER_ENABLE                     _MK_ENUM_CONST(3)
+
+
+// Register MC_STAT_STATUS_0  
+#define MC_STAT_STATUS_0                        _MK_ADDR_CONST(0x94)
+#define MC_STAT_STATUS_0_SECURE                         0x0
+#define MC_STAT_STATUS_0_WORD_COUNT                     0x1
+#define MC_STAT_STATUS_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define MC_STAT_STATUS_0_RESET_MASK                     _MK_MASK_CONST(0x0)
+#define MC_STAT_STATUS_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define MC_STAT_STATUS_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_STAT_STATUS_0_READ_MASK                      _MK_MASK_CONST(0x100)
+#define MC_STAT_STATUS_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
+#define MC_STAT_STATUS_0_EMC_LIMIT_SHIFT                        _MK_SHIFT_CONST(8)
+#define MC_STAT_STATUS_0_EMC_LIMIT_FIELD                        (_MK_MASK_CONST(0x1) << MC_STAT_STATUS_0_EMC_LIMIT_SHIFT)
+#define MC_STAT_STATUS_0_EMC_LIMIT_RANGE                        8:8
+#define MC_STAT_STATUS_0_EMC_LIMIT_WOFFSET                      0x0
+#define MC_STAT_STATUS_0_EMC_LIMIT_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_STAT_STATUS_0_EMC_LIMIT_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_STAT_STATUS_0_EMC_LIMIT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_STAT_STATUS_0_EMC_LIMIT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register MC_STAT_EMC_ADDR_LOW_0  
+#define MC_STAT_EMC_ADDR_LOW_0                  _MK_ADDR_CONST(0x98)
+#define MC_STAT_EMC_ADDR_LOW_0_SECURE                   0x0
+#define MC_STAT_EMC_ADDR_LOW_0_WORD_COUNT                       0x1
+#define MC_STAT_EMC_ADDR_LOW_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_ADDR_LOW_0_RESET_MASK                       _MK_MASK_CONST(0x3ffffff0)
+#define MC_STAT_EMC_ADDR_LOW_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_ADDR_LOW_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_ADDR_LOW_0_READ_MASK                        _MK_MASK_CONST(0x3ffffff0)
+#define MC_STAT_EMC_ADDR_LOW_0_WRITE_MASK                       _MK_MASK_CONST(0x3ffffff0)
+#define MC_STAT_EMC_ADDR_LOW_0_EMC_ADDR_LOW_SHIFT                       _MK_SHIFT_CONST(4)
+#define MC_STAT_EMC_ADDR_LOW_0_EMC_ADDR_LOW_FIELD                       (_MK_MASK_CONST(0x3ffffff) << MC_STAT_EMC_ADDR_LOW_0_EMC_ADDR_LOW_SHIFT)
+#define MC_STAT_EMC_ADDR_LOW_0_EMC_ADDR_LOW_RANGE                       29:4
+#define MC_STAT_EMC_ADDR_LOW_0_EMC_ADDR_LOW_WOFFSET                     0x0
+#define MC_STAT_EMC_ADDR_LOW_0_EMC_ADDR_LOW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_ADDR_LOW_0_EMC_ADDR_LOW_DEFAULT_MASK                        _MK_MASK_CONST(0x3ffffff)
+#define MC_STAT_EMC_ADDR_LOW_0_EMC_ADDR_LOW_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_ADDR_LOW_0_EMC_ADDR_LOW_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register MC_STAT_EMC_ADDR_HIGH_0  
+#define MC_STAT_EMC_ADDR_HIGH_0                 _MK_ADDR_CONST(0x9c)
+#define MC_STAT_EMC_ADDR_HIGH_0_SECURE                  0x0
+#define MC_STAT_EMC_ADDR_HIGH_0_WORD_COUNT                      0x1
+#define MC_STAT_EMC_ADDR_HIGH_0_RESET_VAL                       _MK_MASK_CONST(0x3ffffff0)
+#define MC_STAT_EMC_ADDR_HIGH_0_RESET_MASK                      _MK_MASK_CONST(0x3ffffff0)
+#define MC_STAT_EMC_ADDR_HIGH_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_ADDR_HIGH_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_ADDR_HIGH_0_READ_MASK                       _MK_MASK_CONST(0x3ffffff0)
+#define MC_STAT_EMC_ADDR_HIGH_0_WRITE_MASK                      _MK_MASK_CONST(0x3ffffff0)
+#define MC_STAT_EMC_ADDR_HIGH_0_EMC_ADDR_HIGH_SHIFT                     _MK_SHIFT_CONST(4)
+#define MC_STAT_EMC_ADDR_HIGH_0_EMC_ADDR_HIGH_FIELD                     (_MK_MASK_CONST(0x3ffffff) << MC_STAT_EMC_ADDR_HIGH_0_EMC_ADDR_HIGH_SHIFT)
+#define MC_STAT_EMC_ADDR_HIGH_0_EMC_ADDR_HIGH_RANGE                     29:4
+#define MC_STAT_EMC_ADDR_HIGH_0_EMC_ADDR_HIGH_WOFFSET                   0x0
+#define MC_STAT_EMC_ADDR_HIGH_0_EMC_ADDR_HIGH_DEFAULT                   _MK_MASK_CONST(0xffffffff)
+#define MC_STAT_EMC_ADDR_HIGH_0_EMC_ADDR_HIGH_DEFAULT_MASK                      _MK_MASK_CONST(0x3ffffff)
+#define MC_STAT_EMC_ADDR_HIGH_0_EMC_ADDR_HIGH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_ADDR_HIGH_0_EMC_ADDR_HIGH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_ADDR_HIGH_0_EMC_ADDR_HIGH_INIT_ENUM                 -1
+
+
+// Register MC_STAT_EMC_CLOCK_LIMIT_0  
+#define MC_STAT_EMC_CLOCK_LIMIT_0                       _MK_ADDR_CONST(0xa0)
+#define MC_STAT_EMC_CLOCK_LIMIT_0_SECURE                        0x0
+#define MC_STAT_EMC_CLOCK_LIMIT_0_WORD_COUNT                    0x1
+#define MC_STAT_EMC_CLOCK_LIMIT_0_RESET_VAL                     _MK_MASK_CONST(0xffffffff)
+#define MC_STAT_EMC_CLOCK_LIMIT_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
+#define MC_STAT_EMC_CLOCK_LIMIT_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_CLOCK_LIMIT_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_CLOCK_LIMIT_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define MC_STAT_EMC_CLOCK_LIMIT_0_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
+#define MC_STAT_EMC_CLOCK_LIMIT_0_EMC_CLOCK_LIMIT_SHIFT                 _MK_SHIFT_CONST(0)
+#define MC_STAT_EMC_CLOCK_LIMIT_0_EMC_CLOCK_LIMIT_FIELD                 (_MK_MASK_CONST(0xffffffff) << MC_STAT_EMC_CLOCK_LIMIT_0_EMC_CLOCK_LIMIT_SHIFT)
+#define MC_STAT_EMC_CLOCK_LIMIT_0_EMC_CLOCK_LIMIT_RANGE                 31:0
+#define MC_STAT_EMC_CLOCK_LIMIT_0_EMC_CLOCK_LIMIT_WOFFSET                       0x0
+#define MC_STAT_EMC_CLOCK_LIMIT_0_EMC_CLOCK_LIMIT_DEFAULT                       _MK_MASK_CONST(0xffffffff)
+#define MC_STAT_EMC_CLOCK_LIMIT_0_EMC_CLOCK_LIMIT_DEFAULT_MASK                  _MK_MASK_CONST(0xffffffff)
+#define MC_STAT_EMC_CLOCK_LIMIT_0_EMC_CLOCK_LIMIT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_CLOCK_LIMIT_0_EMC_CLOCK_LIMIT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_CLOCK_LIMIT_0_EMC_CLOCK_LIMIT_INIT_ENUM                     -1
+
+
+// Register MC_STAT_EMC_CLOCKS_0  
+#define MC_STAT_EMC_CLOCKS_0                    _MK_ADDR_CONST(0xa4)
+#define MC_STAT_EMC_CLOCKS_0_SECURE                     0x0
+#define MC_STAT_EMC_CLOCKS_0_WORD_COUNT                         0x1
+#define MC_STAT_EMC_CLOCKS_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_CLOCKS_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_CLOCKS_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_CLOCKS_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_CLOCKS_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define MC_STAT_EMC_CLOCKS_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_CLOCKS_0_EMC_CLOCKS_SHIFT                   _MK_SHIFT_CONST(0)
+#define MC_STAT_EMC_CLOCKS_0_EMC_CLOCKS_FIELD                   (_MK_MASK_CONST(0xffffffff) << MC_STAT_EMC_CLOCKS_0_EMC_CLOCKS_SHIFT)
+#define MC_STAT_EMC_CLOCKS_0_EMC_CLOCKS_RANGE                   31:0
+#define MC_STAT_EMC_CLOCKS_0_EMC_CLOCKS_WOFFSET                 0x0
+#define MC_STAT_EMC_CLOCKS_0_EMC_CLOCKS_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_CLOCKS_0_EMC_CLOCKS_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_CLOCKS_0_EMC_CLOCKS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_CLOCKS_0_EMC_CLOCKS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Packet ARMC_STAT_CONTROL
+#define ARMC_STAT_CONTROL_SIZE 32
+
+#define ARMC_STAT_CONTROL_MODE_SHIFT                    _MK_SHIFT_CONST(0)
+#define ARMC_STAT_CONTROL_MODE_FIELD                    (_MK_MASK_CONST(0x3) << ARMC_STAT_CONTROL_MODE_SHIFT)
+#define ARMC_STAT_CONTROL_MODE_RANGE                    _MK_SHIFT_CONST(1):_MK_SHIFT_CONST(0)
+#define ARMC_STAT_CONTROL_MODE_ROW                      0
+#define ARMC_STAT_CONTROL_MODE_BANDWIDTH                        _MK_ENUM_CONST(0)
+#define ARMC_STAT_CONTROL_MODE_LATENCY_AVG                      _MK_ENUM_CONST(1)
+#define ARMC_STAT_CONTROL_MODE_LATENCY_HISTO                    _MK_ENUM_CONST(2)
+
+#define ARMC_STAT_CONTROL_SKIP_SHIFT                    _MK_SHIFT_CONST(4)
+#define ARMC_STAT_CONTROL_SKIP_FIELD                    (_MK_MASK_CONST(0x7) << ARMC_STAT_CONTROL_SKIP_SHIFT)
+#define ARMC_STAT_CONTROL_SKIP_RANGE                    _MK_SHIFT_CONST(6):_MK_SHIFT_CONST(4)
+#define ARMC_STAT_CONTROL_SKIP_ROW                      0
+
+#define ARMC_STAT_CONTROL_CLIENT_ID_SHIFT                       _MK_SHIFT_CONST(8)
+#define ARMC_STAT_CONTROL_CLIENT_ID_FIELD                       (_MK_MASK_CONST(0x3f) << ARMC_STAT_CONTROL_CLIENT_ID_SHIFT)
+#define ARMC_STAT_CONTROL_CLIENT_ID_RANGE                       _MK_SHIFT_CONST(13):_MK_SHIFT_CONST(8)
+#define ARMC_STAT_CONTROL_CLIENT_ID_ROW                 0
+
+#define ARMC_STAT_CONTROL_EVENT_SHIFT                   _MK_SHIFT_CONST(16)
+#define ARMC_STAT_CONTROL_EVENT_FIELD                   (_MK_MASK_CONST(0xff) << ARMC_STAT_CONTROL_EVENT_SHIFT)
+#define ARMC_STAT_CONTROL_EVENT_RANGE                   _MK_SHIFT_CONST(23):_MK_SHIFT_CONST(16)
+#define ARMC_STAT_CONTROL_EVENT_ROW                     0
+#define ARMC_STAT_CONTROL_EVENT_QUALIFIED                       _MK_ENUM_CONST(0)
+#define ARMC_STAT_CONTROL_EVENT_ANY_READ                        _MK_ENUM_CONST(1)
+#define ARMC_STAT_CONTROL_EVENT_ANY_WRITE                       _MK_ENUM_CONST(2)
+#define ARMC_STAT_CONTROL_EVENT_RD_WR_CHANGE                    _MK_ENUM_CONST(3)
+#define ARMC_STAT_CONTROL_EVENT_SUCCESSIVE                      _MK_ENUM_CONST(4)
+#define ARMC_STAT_CONTROL_EVENT_ARB_BANK_AA                     _MK_ENUM_CONST(5)
+#define ARMC_STAT_CONTROL_EVENT_ARB_BANK_BB                     _MK_ENUM_CONST(6)
+#define ARMC_STAT_CONTROL_EVENT_PAGE_MISS                       _MK_ENUM_CONST(7)
+#define ARMC_STAT_CONTROL_EVENT_AUTO_PRECHARGE                  _MK_ENUM_CONST(8)
+
+#define ARMC_STAT_CONTROL_PRI_EVENT_SHIFT                       _MK_SHIFT_CONST(24)
+#define ARMC_STAT_CONTROL_PRI_EVENT_FIELD                       (_MK_MASK_CONST(0x3) << ARMC_STAT_CONTROL_PRI_EVENT_SHIFT)
+#define ARMC_STAT_CONTROL_PRI_EVENT_RANGE                       _MK_SHIFT_CONST(25):_MK_SHIFT_CONST(24)
+#define ARMC_STAT_CONTROL_PRI_EVENT_ROW                 0
+#define ARMC_STAT_CONTROL_PRI_EVENT_HP                  _MK_ENUM_CONST(0)
+#define ARMC_STAT_CONTROL_PRI_EVENT_TM                  _MK_ENUM_CONST(1)
+#define ARMC_STAT_CONTROL_PRI_EVENT_BW                  _MK_ENUM_CONST(2)
+
+#define ARMC_STAT_CONTROL_FILTER_CLIENT_SHIFT                   _MK_SHIFT_CONST(26)
+#define ARMC_STAT_CONTROL_FILTER_CLIENT_FIELD                   (_MK_MASK_CONST(0x1) << ARMC_STAT_CONTROL_FILTER_CLIENT_SHIFT)
+#define ARMC_STAT_CONTROL_FILTER_CLIENT_RANGE                   _MK_SHIFT_CONST(26):_MK_SHIFT_CONST(26)
+#define ARMC_STAT_CONTROL_FILTER_CLIENT_ROW                     0
+#define ARMC_STAT_CONTROL_FILTER_CLIENT_DISABLE                 _MK_ENUM_CONST(0)
+#define ARMC_STAT_CONTROL_FILTER_CLIENT_ENABLE                  _MK_ENUM_CONST(1)
+
+#define ARMC_STAT_CONTROL_FILTER_ADDR_SHIFT                     _MK_SHIFT_CONST(27)
+#define ARMC_STAT_CONTROL_FILTER_ADDR_FIELD                     (_MK_MASK_CONST(0x1) << ARMC_STAT_CONTROL_FILTER_ADDR_SHIFT)
+#define ARMC_STAT_CONTROL_FILTER_ADDR_RANGE                     _MK_SHIFT_CONST(27):_MK_SHIFT_CONST(27)
+#define ARMC_STAT_CONTROL_FILTER_ADDR_ROW                       0
+#define ARMC_STAT_CONTROL_FILTER_ADDR_DISABLE                   _MK_ENUM_CONST(0)
+#define ARMC_STAT_CONTROL_FILTER_ADDR_ENABLE                    _MK_ENUM_CONST(1)
+
+#define ARMC_STAT_CONTROL_FILTER_PRI_SHIFT                      _MK_SHIFT_CONST(28)
+#define ARMC_STAT_CONTROL_FILTER_PRI_FIELD                      (_MK_MASK_CONST(0x3) << ARMC_STAT_CONTROL_FILTER_PRI_SHIFT)
+#define ARMC_STAT_CONTROL_FILTER_PRI_RANGE                      _MK_SHIFT_CONST(29):_MK_SHIFT_CONST(28)
+#define ARMC_STAT_CONTROL_FILTER_PRI_ROW                        0
+#define ARMC_STAT_CONTROL_FILTER_PRI_DISABLE                    _MK_ENUM_CONST(0)
+#define ARMC_STAT_CONTROL_FILTER_PRI_NO                 _MK_ENUM_CONST(1)
+#define ARMC_STAT_CONTROL_FILTER_PRI_YES                        _MK_ENUM_CONST(2)
+
+#define ARMC_STAT_CONTROL_FILTER_COALESCED_SHIFT                        _MK_SHIFT_CONST(30)
+#define ARMC_STAT_CONTROL_FILTER_COALESCED_FIELD                        (_MK_MASK_CONST(0x3) << ARMC_STAT_CONTROL_FILTER_COALESCED_SHIFT)
+#define ARMC_STAT_CONTROL_FILTER_COALESCED_RANGE                        _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(30)
+#define ARMC_STAT_CONTROL_FILTER_COALESCED_ROW                  0
+#define ARMC_STAT_CONTROL_FILTER_COALESCED_DISABLE                      _MK_ENUM_CONST(0)
+#define ARMC_STAT_CONTROL_FILTER_COALESCED_NO                   _MK_ENUM_CONST(1)
+#define ARMC_STAT_CONTROL_FILTER_COALESCED_YES                  _MK_ENUM_CONST(2)
+
+
+// Register MC_STAT_EMC_CONTROL_0_0  
+#define MC_STAT_EMC_CONTROL_0_0                 _MK_ADDR_CONST(0xa8)
+#define MC_STAT_EMC_CONTROL_0_0_SECURE                  0x0
+#define MC_STAT_EMC_CONTROL_0_0_WORD_COUNT                      0x1
+#define MC_STAT_EMC_CONTROL_0_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_CONTROL_0_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define MC_STAT_EMC_CONTROL_0_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_CONTROL_0_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_CONTROL_0_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define MC_STAT_EMC_CONTROL_0_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+#define MC_STAT_EMC_CONTROL_0_0_EMC_CONTROL_0_SHIFT                     _MK_SHIFT_CONST(0)
+#define MC_STAT_EMC_CONTROL_0_0_EMC_CONTROL_0_FIELD                     (_MK_MASK_CONST(0xffffffff) << MC_STAT_EMC_CONTROL_0_0_EMC_CONTROL_0_SHIFT)
+#define MC_STAT_EMC_CONTROL_0_0_EMC_CONTROL_0_RANGE                     31:0
+#define MC_STAT_EMC_CONTROL_0_0_EMC_CONTROL_0_WOFFSET                   0x0
+#define MC_STAT_EMC_CONTROL_0_0_EMC_CONTROL_0_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_CONTROL_0_0_EMC_CONTROL_0_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define MC_STAT_EMC_CONTROL_0_0_EMC_CONTROL_0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_CONTROL_0_0_EMC_CONTROL_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register MC_STAT_EMC_CONTROL_1_0  
+#define MC_STAT_EMC_CONTROL_1_0                 _MK_ADDR_CONST(0xac)
+#define MC_STAT_EMC_CONTROL_1_0_SECURE                  0x0
+#define MC_STAT_EMC_CONTROL_1_0_WORD_COUNT                      0x1
+#define MC_STAT_EMC_CONTROL_1_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_CONTROL_1_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define MC_STAT_EMC_CONTROL_1_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_CONTROL_1_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_CONTROL_1_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define MC_STAT_EMC_CONTROL_1_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+#define MC_STAT_EMC_CONTROL_1_0_EMC_CONTROL_1_SHIFT                     _MK_SHIFT_CONST(0)
+#define MC_STAT_EMC_CONTROL_1_0_EMC_CONTROL_1_FIELD                     (_MK_MASK_CONST(0xffffffff) << MC_STAT_EMC_CONTROL_1_0_EMC_CONTROL_1_SHIFT)
+#define MC_STAT_EMC_CONTROL_1_0_EMC_CONTROL_1_RANGE                     31:0
+#define MC_STAT_EMC_CONTROL_1_0_EMC_CONTROL_1_WOFFSET                   0x0
+#define MC_STAT_EMC_CONTROL_1_0_EMC_CONTROL_1_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_CONTROL_1_0_EMC_CONTROL_1_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define MC_STAT_EMC_CONTROL_1_0_EMC_CONTROL_1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_CONTROL_1_0_EMC_CONTROL_1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Packet ARMC_STAT_HIST_LIMIT
+#define ARMC_STAT_HIST_LIMIT_SIZE 32
+
+#define ARMC_STAT_HIST_LIMIT_LOW_SHIFT                  _MK_SHIFT_CONST(0)
+#define ARMC_STAT_HIST_LIMIT_LOW_FIELD                  (_MK_MASK_CONST(0xffff) << ARMC_STAT_HIST_LIMIT_LOW_SHIFT)
+#define ARMC_STAT_HIST_LIMIT_LOW_RANGE                  _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(0)
+#define ARMC_STAT_HIST_LIMIT_LOW_ROW                    0
+
+#define ARMC_STAT_HIST_LIMIT_HIGH_SHIFT                 _MK_SHIFT_CONST(16)
+#define ARMC_STAT_HIST_LIMIT_HIGH_FIELD                 (_MK_MASK_CONST(0xffff) << ARMC_STAT_HIST_LIMIT_HIGH_SHIFT)
+#define ARMC_STAT_HIST_LIMIT_HIGH_RANGE                 _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(16)
+#define ARMC_STAT_HIST_LIMIT_HIGH_ROW                   0
+
+
+// Register MC_STAT_EMC_HIST_LIMIT_0_0  
+#define MC_STAT_EMC_HIST_LIMIT_0_0                      _MK_ADDR_CONST(0xb0)
+#define MC_STAT_EMC_HIST_LIMIT_0_0_SECURE                       0x0
+#define MC_STAT_EMC_HIST_LIMIT_0_0_WORD_COUNT                   0x1
+#define MC_STAT_EMC_HIST_LIMIT_0_0_RESET_VAL                    _MK_MASK_CONST(0xffff0000)
+#define MC_STAT_EMC_HIST_LIMIT_0_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define MC_STAT_EMC_HIST_LIMIT_0_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_HIST_LIMIT_0_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_HIST_LIMIT_0_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
+#define MC_STAT_EMC_HIST_LIMIT_0_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
+#define MC_STAT_EMC_HIST_LIMIT_0_0_EMC_HIST_LIMIT_0_SHIFT                       _MK_SHIFT_CONST(0)
+#define MC_STAT_EMC_HIST_LIMIT_0_0_EMC_HIST_LIMIT_0_FIELD                       (_MK_MASK_CONST(0xffffffff) << MC_STAT_EMC_HIST_LIMIT_0_0_EMC_HIST_LIMIT_0_SHIFT)
+#define MC_STAT_EMC_HIST_LIMIT_0_0_EMC_HIST_LIMIT_0_RANGE                       31:0
+#define MC_STAT_EMC_HIST_LIMIT_0_0_EMC_HIST_LIMIT_0_WOFFSET                     0x0
+#define MC_STAT_EMC_HIST_LIMIT_0_0_EMC_HIST_LIMIT_0_DEFAULT                     _MK_MASK_CONST(0xffff0000)
+#define MC_STAT_EMC_HIST_LIMIT_0_0_EMC_HIST_LIMIT_0_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
+#define MC_STAT_EMC_HIST_LIMIT_0_0_EMC_HIST_LIMIT_0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_HIST_LIMIT_0_0_EMC_HIST_LIMIT_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_HIST_LIMIT_0_0_EMC_HIST_LIMIT_0_INIT_ENUM                   -65536
+
+
+// Register MC_STAT_EMC_HIST_LIMIT_1_0  
+#define MC_STAT_EMC_HIST_LIMIT_1_0                      _MK_ADDR_CONST(0xb4)
+#define MC_STAT_EMC_HIST_LIMIT_1_0_SECURE                       0x0
+#define MC_STAT_EMC_HIST_LIMIT_1_0_WORD_COUNT                   0x1
+#define MC_STAT_EMC_HIST_LIMIT_1_0_RESET_VAL                    _MK_MASK_CONST(0xffff0000)
+#define MC_STAT_EMC_HIST_LIMIT_1_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define MC_STAT_EMC_HIST_LIMIT_1_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_HIST_LIMIT_1_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_HIST_LIMIT_1_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
+#define MC_STAT_EMC_HIST_LIMIT_1_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
+#define MC_STAT_EMC_HIST_LIMIT_1_0_EMC_HIST_LIMIT_1_SHIFT                       _MK_SHIFT_CONST(0)
+#define MC_STAT_EMC_HIST_LIMIT_1_0_EMC_HIST_LIMIT_1_FIELD                       (_MK_MASK_CONST(0xffffffff) << MC_STAT_EMC_HIST_LIMIT_1_0_EMC_HIST_LIMIT_1_SHIFT)
+#define MC_STAT_EMC_HIST_LIMIT_1_0_EMC_HIST_LIMIT_1_RANGE                       31:0
+#define MC_STAT_EMC_HIST_LIMIT_1_0_EMC_HIST_LIMIT_1_WOFFSET                     0x0
+#define MC_STAT_EMC_HIST_LIMIT_1_0_EMC_HIST_LIMIT_1_DEFAULT                     _MK_MASK_CONST(0xffff0000)
+#define MC_STAT_EMC_HIST_LIMIT_1_0_EMC_HIST_LIMIT_1_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
+#define MC_STAT_EMC_HIST_LIMIT_1_0_EMC_HIST_LIMIT_1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_HIST_LIMIT_1_0_EMC_HIST_LIMIT_1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_HIST_LIMIT_1_0_EMC_HIST_LIMIT_1_INIT_ENUM                   -65536
+
+
+// Register MC_STAT_EMC_COUNT_0_0  
+#define MC_STAT_EMC_COUNT_0_0                   _MK_ADDR_CONST(0xb8)
+#define MC_STAT_EMC_COUNT_0_0_SECURE                    0x0
+#define MC_STAT_EMC_COUNT_0_0_WORD_COUNT                        0x1
+#define MC_STAT_EMC_COUNT_0_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_COUNT_0_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_COUNT_0_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_COUNT_0_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_COUNT_0_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define MC_STAT_EMC_COUNT_0_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_COUNT_0_0_EMC_COUNT_0_SHIFT                 _MK_SHIFT_CONST(0)
+#define MC_STAT_EMC_COUNT_0_0_EMC_COUNT_0_FIELD                 (_MK_MASK_CONST(0xffffffff) << MC_STAT_EMC_COUNT_0_0_EMC_COUNT_0_SHIFT)
+#define MC_STAT_EMC_COUNT_0_0_EMC_COUNT_0_RANGE                 31:0
+#define MC_STAT_EMC_COUNT_0_0_EMC_COUNT_0_WOFFSET                       0x0
+#define MC_STAT_EMC_COUNT_0_0_EMC_COUNT_0_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_COUNT_0_0_EMC_COUNT_0_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_COUNT_0_0_EMC_COUNT_0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_COUNT_0_0_EMC_COUNT_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register MC_STAT_EMC_COUNT_1_0  
+#define MC_STAT_EMC_COUNT_1_0                   _MK_ADDR_CONST(0xbc)
+#define MC_STAT_EMC_COUNT_1_0_SECURE                    0x0
+#define MC_STAT_EMC_COUNT_1_0_WORD_COUNT                        0x1
+#define MC_STAT_EMC_COUNT_1_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_COUNT_1_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_COUNT_1_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_COUNT_1_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_COUNT_1_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define MC_STAT_EMC_COUNT_1_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_COUNT_1_0_EMC_COUNT_1_SHIFT                 _MK_SHIFT_CONST(0)
+#define MC_STAT_EMC_COUNT_1_0_EMC_COUNT_1_FIELD                 (_MK_MASK_CONST(0xffffffff) << MC_STAT_EMC_COUNT_1_0_EMC_COUNT_1_SHIFT)
+#define MC_STAT_EMC_COUNT_1_0_EMC_COUNT_1_RANGE                 31:0
+#define MC_STAT_EMC_COUNT_1_0_EMC_COUNT_1_WOFFSET                       0x0
+#define MC_STAT_EMC_COUNT_1_0_EMC_COUNT_1_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_COUNT_1_0_EMC_COUNT_1_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_COUNT_1_0_EMC_COUNT_1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_COUNT_1_0_EMC_COUNT_1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register MC_STAT_EMC_HIST_0_0  
+#define MC_STAT_EMC_HIST_0_0                    _MK_ADDR_CONST(0xc0)
+#define MC_STAT_EMC_HIST_0_0_SECURE                     0x0
+#define MC_STAT_EMC_HIST_0_0_WORD_COUNT                         0x1
+#define MC_STAT_EMC_HIST_0_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_HIST_0_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_HIST_0_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_HIST_0_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_HIST_0_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define MC_STAT_EMC_HIST_0_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_HIST_0_0_EMC_HIST_0_SHIFT                   _MK_SHIFT_CONST(0)
+#define MC_STAT_EMC_HIST_0_0_EMC_HIST_0_FIELD                   (_MK_MASK_CONST(0xffffffff) << MC_STAT_EMC_HIST_0_0_EMC_HIST_0_SHIFT)
+#define MC_STAT_EMC_HIST_0_0_EMC_HIST_0_RANGE                   31:0
+#define MC_STAT_EMC_HIST_0_0_EMC_HIST_0_WOFFSET                 0x0
+#define MC_STAT_EMC_HIST_0_0_EMC_HIST_0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_HIST_0_0_EMC_HIST_0_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_HIST_0_0_EMC_HIST_0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_HIST_0_0_EMC_HIST_0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register MC_STAT_EMC_HIST_1_0  
+#define MC_STAT_EMC_HIST_1_0                    _MK_ADDR_CONST(0xc4)
+#define MC_STAT_EMC_HIST_1_0_SECURE                     0x0
+#define MC_STAT_EMC_HIST_1_0_WORD_COUNT                         0x1
+#define MC_STAT_EMC_HIST_1_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_HIST_1_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_HIST_1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_HIST_1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_HIST_1_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define MC_STAT_EMC_HIST_1_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_HIST_1_0_EMC_HIST_1_SHIFT                   _MK_SHIFT_CONST(0)
+#define MC_STAT_EMC_HIST_1_0_EMC_HIST_1_FIELD                   (_MK_MASK_CONST(0xffffffff) << MC_STAT_EMC_HIST_1_0_EMC_HIST_1_SHIFT)
+#define MC_STAT_EMC_HIST_1_0_EMC_HIST_1_RANGE                   31:0
+#define MC_STAT_EMC_HIST_1_0_EMC_HIST_1_WOFFSET                 0x0
+#define MC_STAT_EMC_HIST_1_0_EMC_HIST_1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_HIST_1_0_EMC_HIST_1_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_HIST_1_0_EMC_HIST_1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_HIST_1_0_EMC_HIST_1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define MC_CLIENT_CTRL_DISABLE  0
+#define MC_CLIENT_CTRL_ENABLE   1
+
+// Register MC_CLIENT_CTRL_0  
+#define MC_CLIENT_CTRL_0                        _MK_ADDR_CONST(0x100)
+#define MC_CLIENT_CTRL_0_SECURE                         0x0
+#define MC_CLIENT_CTRL_0_WORD_COUNT                     0x1
+#define MC_CLIENT_CTRL_0_RESET_VAL                      _MK_MASK_CONST(0x7fff)
+#define MC_CLIENT_CTRL_0_RESET_MASK                     _MK_MASK_CONST(0x7fff)
+#define MC_CLIENT_CTRL_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_READ_MASK                      _MK_MASK_CONST(0x7fff)
+#define MC_CLIENT_CTRL_0_WRITE_MASK                     _MK_MASK_CONST(0x7fff)
+#define MC_CLIENT_CTRL_0_AVPC_ENABLE_SHIFT                      _MK_SHIFT_CONST(0)
+#define MC_CLIENT_CTRL_0_AVPC_ENABLE_FIELD                      (_MK_MASK_CONST(0x1) << MC_CLIENT_CTRL_0_AVPC_ENABLE_SHIFT)
+#define MC_CLIENT_CTRL_0_AVPC_ENABLE_RANGE                      0:0
+#define MC_CLIENT_CTRL_0_AVPC_ENABLE_WOFFSET                    0x0
+#define MC_CLIENT_CTRL_0_AVPC_ENABLE_DEFAULT                    _MK_MASK_CONST(0x1)
+#define MC_CLIENT_CTRL_0_AVPC_ENABLE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_CLIENT_CTRL_0_AVPC_ENABLE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_AVPC_ENABLE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_AVPC_ENABLE_INIT_ENUM                  ENABLE
+#define MC_CLIENT_CTRL_0_AVPC_ENABLE_DISABLE                    _MK_ENUM_CONST(0)
+#define MC_CLIENT_CTRL_0_AVPC_ENABLE_ENABLE                     _MK_ENUM_CONST(1)
+#define MC_CLIENT_CTRL_0_AVPC_ENABLE_DISABLED                   _MK_ENUM_CONST(0)
+#define MC_CLIENT_CTRL_0_AVPC_ENABLE_ENABLED                    _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_CTRL_0_DC_ENABLE_SHIFT                        _MK_SHIFT_CONST(1)
+#define MC_CLIENT_CTRL_0_DC_ENABLE_FIELD                        (_MK_MASK_CONST(0x1) << MC_CLIENT_CTRL_0_DC_ENABLE_SHIFT)
+#define MC_CLIENT_CTRL_0_DC_ENABLE_RANGE                        1:1
+#define MC_CLIENT_CTRL_0_DC_ENABLE_WOFFSET                      0x0
+#define MC_CLIENT_CTRL_0_DC_ENABLE_DEFAULT                      _MK_MASK_CONST(0x1)
+#define MC_CLIENT_CTRL_0_DC_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_CLIENT_CTRL_0_DC_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_DC_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_DC_ENABLE_INIT_ENUM                    ENABLE
+#define MC_CLIENT_CTRL_0_DC_ENABLE_DISABLE                      _MK_ENUM_CONST(0)
+#define MC_CLIENT_CTRL_0_DC_ENABLE_ENABLE                       _MK_ENUM_CONST(1)
+#define MC_CLIENT_CTRL_0_DC_ENABLE_DISABLED                     _MK_ENUM_CONST(0)
+#define MC_CLIENT_CTRL_0_DC_ENABLE_ENABLED                      _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_CTRL_0_DCB_ENABLE_SHIFT                       _MK_SHIFT_CONST(2)
+#define MC_CLIENT_CTRL_0_DCB_ENABLE_FIELD                       (_MK_MASK_CONST(0x1) << MC_CLIENT_CTRL_0_DCB_ENABLE_SHIFT)
+#define MC_CLIENT_CTRL_0_DCB_ENABLE_RANGE                       2:2
+#define MC_CLIENT_CTRL_0_DCB_ENABLE_WOFFSET                     0x0
+#define MC_CLIENT_CTRL_0_DCB_ENABLE_DEFAULT                     _MK_MASK_CONST(0x1)
+#define MC_CLIENT_CTRL_0_DCB_ENABLE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_CLIENT_CTRL_0_DCB_ENABLE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_DCB_ENABLE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_DCB_ENABLE_INIT_ENUM                   ENABLE
+#define MC_CLIENT_CTRL_0_DCB_ENABLE_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_CLIENT_CTRL_0_DCB_ENABLE_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_CLIENT_CTRL_0_DCB_ENABLE_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_CLIENT_CTRL_0_DCB_ENABLE_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_CTRL_0_EPP_ENABLE_SHIFT                       _MK_SHIFT_CONST(3)
+#define MC_CLIENT_CTRL_0_EPP_ENABLE_FIELD                       (_MK_MASK_CONST(0x1) << MC_CLIENT_CTRL_0_EPP_ENABLE_SHIFT)
+#define MC_CLIENT_CTRL_0_EPP_ENABLE_RANGE                       3:3
+#define MC_CLIENT_CTRL_0_EPP_ENABLE_WOFFSET                     0x0
+#define MC_CLIENT_CTRL_0_EPP_ENABLE_DEFAULT                     _MK_MASK_CONST(0x1)
+#define MC_CLIENT_CTRL_0_EPP_ENABLE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_CLIENT_CTRL_0_EPP_ENABLE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_EPP_ENABLE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_EPP_ENABLE_INIT_ENUM                   ENABLE
+#define MC_CLIENT_CTRL_0_EPP_ENABLE_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_CLIENT_CTRL_0_EPP_ENABLE_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_CLIENT_CTRL_0_EPP_ENABLE_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_CLIENT_CTRL_0_EPP_ENABLE_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_CTRL_0_G2_ENABLE_SHIFT                        _MK_SHIFT_CONST(4)
+#define MC_CLIENT_CTRL_0_G2_ENABLE_FIELD                        (_MK_MASK_CONST(0x1) << MC_CLIENT_CTRL_0_G2_ENABLE_SHIFT)
+#define MC_CLIENT_CTRL_0_G2_ENABLE_RANGE                        4:4
+#define MC_CLIENT_CTRL_0_G2_ENABLE_WOFFSET                      0x0
+#define MC_CLIENT_CTRL_0_G2_ENABLE_DEFAULT                      _MK_MASK_CONST(0x1)
+#define MC_CLIENT_CTRL_0_G2_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_CLIENT_CTRL_0_G2_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_G2_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_G2_ENABLE_INIT_ENUM                    ENABLE
+#define MC_CLIENT_CTRL_0_G2_ENABLE_DISABLE                      _MK_ENUM_CONST(0)
+#define MC_CLIENT_CTRL_0_G2_ENABLE_ENABLE                       _MK_ENUM_CONST(1)
+#define MC_CLIENT_CTRL_0_G2_ENABLE_DISABLED                     _MK_ENUM_CONST(0)
+#define MC_CLIENT_CTRL_0_G2_ENABLE_ENABLED                      _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_CTRL_0_HC_ENABLE_SHIFT                        _MK_SHIFT_CONST(5)
+#define MC_CLIENT_CTRL_0_HC_ENABLE_FIELD                        (_MK_MASK_CONST(0x1) << MC_CLIENT_CTRL_0_HC_ENABLE_SHIFT)
+#define MC_CLIENT_CTRL_0_HC_ENABLE_RANGE                        5:5
+#define MC_CLIENT_CTRL_0_HC_ENABLE_WOFFSET                      0x0
+#define MC_CLIENT_CTRL_0_HC_ENABLE_DEFAULT                      _MK_MASK_CONST(0x1)
+#define MC_CLIENT_CTRL_0_HC_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_CLIENT_CTRL_0_HC_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_HC_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_HC_ENABLE_INIT_ENUM                    ENABLE
+#define MC_CLIENT_CTRL_0_HC_ENABLE_DISABLE                      _MK_ENUM_CONST(0)
+#define MC_CLIENT_CTRL_0_HC_ENABLE_ENABLE                       _MK_ENUM_CONST(1)
+#define MC_CLIENT_CTRL_0_HC_ENABLE_DISABLED                     _MK_ENUM_CONST(0)
+#define MC_CLIENT_CTRL_0_HC_ENABLE_ENABLED                      _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_CTRL_0_ISP_ENABLE_SHIFT                       _MK_SHIFT_CONST(6)
+#define MC_CLIENT_CTRL_0_ISP_ENABLE_FIELD                       (_MK_MASK_CONST(0x1) << MC_CLIENT_CTRL_0_ISP_ENABLE_SHIFT)
+#define MC_CLIENT_CTRL_0_ISP_ENABLE_RANGE                       6:6
+#define MC_CLIENT_CTRL_0_ISP_ENABLE_WOFFSET                     0x0
+#define MC_CLIENT_CTRL_0_ISP_ENABLE_DEFAULT                     _MK_MASK_CONST(0x1)
+#define MC_CLIENT_CTRL_0_ISP_ENABLE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_CLIENT_CTRL_0_ISP_ENABLE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_ISP_ENABLE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_ISP_ENABLE_INIT_ENUM                   ENABLE
+#define MC_CLIENT_CTRL_0_ISP_ENABLE_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_CLIENT_CTRL_0_ISP_ENABLE_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_CLIENT_CTRL_0_ISP_ENABLE_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_CLIENT_CTRL_0_ISP_ENABLE_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_CTRL_0_MPCORE_ENABLE_SHIFT                    _MK_SHIFT_CONST(7)
+#define MC_CLIENT_CTRL_0_MPCORE_ENABLE_FIELD                    (_MK_MASK_CONST(0x1) << MC_CLIENT_CTRL_0_MPCORE_ENABLE_SHIFT)
+#define MC_CLIENT_CTRL_0_MPCORE_ENABLE_RANGE                    7:7
+#define MC_CLIENT_CTRL_0_MPCORE_ENABLE_WOFFSET                  0x0
+#define MC_CLIENT_CTRL_0_MPCORE_ENABLE_DEFAULT                  _MK_MASK_CONST(0x1)
+#define MC_CLIENT_CTRL_0_MPCORE_ENABLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_CLIENT_CTRL_0_MPCORE_ENABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_MPCORE_ENABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_MPCORE_ENABLE_INIT_ENUM                        ENABLE
+#define MC_CLIENT_CTRL_0_MPCORE_ENABLE_DISABLE                  _MK_ENUM_CONST(0)
+#define MC_CLIENT_CTRL_0_MPCORE_ENABLE_ENABLE                   _MK_ENUM_CONST(1)
+#define MC_CLIENT_CTRL_0_MPCORE_ENABLE_DISABLED                 _MK_ENUM_CONST(0)
+#define MC_CLIENT_CTRL_0_MPCORE_ENABLE_ENABLED                  _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_CTRL_0_MPEA_ENABLE_SHIFT                      _MK_SHIFT_CONST(8)
+#define MC_CLIENT_CTRL_0_MPEA_ENABLE_FIELD                      (_MK_MASK_CONST(0x1) << MC_CLIENT_CTRL_0_MPEA_ENABLE_SHIFT)
+#define MC_CLIENT_CTRL_0_MPEA_ENABLE_RANGE                      8:8
+#define MC_CLIENT_CTRL_0_MPEA_ENABLE_WOFFSET                    0x0
+#define MC_CLIENT_CTRL_0_MPEA_ENABLE_DEFAULT                    _MK_MASK_CONST(0x1)
+#define MC_CLIENT_CTRL_0_MPEA_ENABLE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_CLIENT_CTRL_0_MPEA_ENABLE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_MPEA_ENABLE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_MPEA_ENABLE_INIT_ENUM                  ENABLE
+#define MC_CLIENT_CTRL_0_MPEA_ENABLE_DISABLE                    _MK_ENUM_CONST(0)
+#define MC_CLIENT_CTRL_0_MPEA_ENABLE_ENABLE                     _MK_ENUM_CONST(1)
+#define MC_CLIENT_CTRL_0_MPEA_ENABLE_DISABLED                   _MK_ENUM_CONST(0)
+#define MC_CLIENT_CTRL_0_MPEA_ENABLE_ENABLED                    _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_CTRL_0_MPEB_ENABLE_SHIFT                      _MK_SHIFT_CONST(9)
+#define MC_CLIENT_CTRL_0_MPEB_ENABLE_FIELD                      (_MK_MASK_CONST(0x1) << MC_CLIENT_CTRL_0_MPEB_ENABLE_SHIFT)
+#define MC_CLIENT_CTRL_0_MPEB_ENABLE_RANGE                      9:9
+#define MC_CLIENT_CTRL_0_MPEB_ENABLE_WOFFSET                    0x0
+#define MC_CLIENT_CTRL_0_MPEB_ENABLE_DEFAULT                    _MK_MASK_CONST(0x1)
+#define MC_CLIENT_CTRL_0_MPEB_ENABLE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_CLIENT_CTRL_0_MPEB_ENABLE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_MPEB_ENABLE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_MPEB_ENABLE_INIT_ENUM                  ENABLE
+#define MC_CLIENT_CTRL_0_MPEB_ENABLE_DISABLE                    _MK_ENUM_CONST(0)
+#define MC_CLIENT_CTRL_0_MPEB_ENABLE_ENABLE                     _MK_ENUM_CONST(1)
+#define MC_CLIENT_CTRL_0_MPEB_ENABLE_DISABLED                   _MK_ENUM_CONST(0)
+#define MC_CLIENT_CTRL_0_MPEB_ENABLE_ENABLED                    _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_CTRL_0_MPEC_ENABLE_SHIFT                      _MK_SHIFT_CONST(10)
+#define MC_CLIENT_CTRL_0_MPEC_ENABLE_FIELD                      (_MK_MASK_CONST(0x1) << MC_CLIENT_CTRL_0_MPEC_ENABLE_SHIFT)
+#define MC_CLIENT_CTRL_0_MPEC_ENABLE_RANGE                      10:10
+#define MC_CLIENT_CTRL_0_MPEC_ENABLE_WOFFSET                    0x0
+#define MC_CLIENT_CTRL_0_MPEC_ENABLE_DEFAULT                    _MK_MASK_CONST(0x1)
+#define MC_CLIENT_CTRL_0_MPEC_ENABLE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_CLIENT_CTRL_0_MPEC_ENABLE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_MPEC_ENABLE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_MPEC_ENABLE_INIT_ENUM                  ENABLE
+#define MC_CLIENT_CTRL_0_MPEC_ENABLE_DISABLE                    _MK_ENUM_CONST(0)
+#define MC_CLIENT_CTRL_0_MPEC_ENABLE_ENABLE                     _MK_ENUM_CONST(1)
+#define MC_CLIENT_CTRL_0_MPEC_ENABLE_DISABLED                   _MK_ENUM_CONST(0)
+#define MC_CLIENT_CTRL_0_MPEC_ENABLE_ENABLED                    _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_CTRL_0_NV_ENABLE_SHIFT                        _MK_SHIFT_CONST(11)
+#define MC_CLIENT_CTRL_0_NV_ENABLE_FIELD                        (_MK_MASK_CONST(0x1) << MC_CLIENT_CTRL_0_NV_ENABLE_SHIFT)
+#define MC_CLIENT_CTRL_0_NV_ENABLE_RANGE                        11:11
+#define MC_CLIENT_CTRL_0_NV_ENABLE_WOFFSET                      0x0
+#define MC_CLIENT_CTRL_0_NV_ENABLE_DEFAULT                      _MK_MASK_CONST(0x1)
+#define MC_CLIENT_CTRL_0_NV_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_CLIENT_CTRL_0_NV_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_NV_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_NV_ENABLE_INIT_ENUM                    ENABLE
+#define MC_CLIENT_CTRL_0_NV_ENABLE_DISABLE                      _MK_ENUM_CONST(0)
+#define MC_CLIENT_CTRL_0_NV_ENABLE_ENABLE                       _MK_ENUM_CONST(1)
+#define MC_CLIENT_CTRL_0_NV_ENABLE_DISABLED                     _MK_ENUM_CONST(0)
+#define MC_CLIENT_CTRL_0_NV_ENABLE_ENABLED                      _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_CTRL_0_PPCS_ENABLE_SHIFT                      _MK_SHIFT_CONST(12)
+#define MC_CLIENT_CTRL_0_PPCS_ENABLE_FIELD                      (_MK_MASK_CONST(0x1) << MC_CLIENT_CTRL_0_PPCS_ENABLE_SHIFT)
+#define MC_CLIENT_CTRL_0_PPCS_ENABLE_RANGE                      12:12
+#define MC_CLIENT_CTRL_0_PPCS_ENABLE_WOFFSET                    0x0
+#define MC_CLIENT_CTRL_0_PPCS_ENABLE_DEFAULT                    _MK_MASK_CONST(0x1)
+#define MC_CLIENT_CTRL_0_PPCS_ENABLE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_CLIENT_CTRL_0_PPCS_ENABLE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_PPCS_ENABLE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_PPCS_ENABLE_INIT_ENUM                  ENABLE
+#define MC_CLIENT_CTRL_0_PPCS_ENABLE_DISABLE                    _MK_ENUM_CONST(0)
+#define MC_CLIENT_CTRL_0_PPCS_ENABLE_ENABLE                     _MK_ENUM_CONST(1)
+#define MC_CLIENT_CTRL_0_PPCS_ENABLE_DISABLED                   _MK_ENUM_CONST(0)
+#define MC_CLIENT_CTRL_0_PPCS_ENABLE_ENABLED                    _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_CTRL_0_VDE_ENABLE_SHIFT                       _MK_SHIFT_CONST(13)
+#define MC_CLIENT_CTRL_0_VDE_ENABLE_FIELD                       (_MK_MASK_CONST(0x1) << MC_CLIENT_CTRL_0_VDE_ENABLE_SHIFT)
+#define MC_CLIENT_CTRL_0_VDE_ENABLE_RANGE                       13:13
+#define MC_CLIENT_CTRL_0_VDE_ENABLE_WOFFSET                     0x0
+#define MC_CLIENT_CTRL_0_VDE_ENABLE_DEFAULT                     _MK_MASK_CONST(0x1)
+#define MC_CLIENT_CTRL_0_VDE_ENABLE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_CLIENT_CTRL_0_VDE_ENABLE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_VDE_ENABLE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_VDE_ENABLE_INIT_ENUM                   ENABLE
+#define MC_CLIENT_CTRL_0_VDE_ENABLE_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_CLIENT_CTRL_0_VDE_ENABLE_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_CLIENT_CTRL_0_VDE_ENABLE_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_CLIENT_CTRL_0_VDE_ENABLE_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_CTRL_0_VI_ENABLE_SHIFT                        _MK_SHIFT_CONST(14)
+#define MC_CLIENT_CTRL_0_VI_ENABLE_FIELD                        (_MK_MASK_CONST(0x1) << MC_CLIENT_CTRL_0_VI_ENABLE_SHIFT)
+#define MC_CLIENT_CTRL_0_VI_ENABLE_RANGE                        14:14
+#define MC_CLIENT_CTRL_0_VI_ENABLE_WOFFSET                      0x0
+#define MC_CLIENT_CTRL_0_VI_ENABLE_DEFAULT                      _MK_MASK_CONST(0x1)
+#define MC_CLIENT_CTRL_0_VI_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_CLIENT_CTRL_0_VI_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_VI_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_VI_ENABLE_INIT_ENUM                    ENABLE
+#define MC_CLIENT_CTRL_0_VI_ENABLE_DISABLE                      _MK_ENUM_CONST(0)
+#define MC_CLIENT_CTRL_0_VI_ENABLE_ENABLE                       _MK_ENUM_CONST(1)
+#define MC_CLIENT_CTRL_0_VI_ENABLE_DISABLED                     _MK_ENUM_CONST(0)
+#define MC_CLIENT_CTRL_0_VI_ENABLE_ENABLED                      _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_HOTRESETN_DISABLE     1
+#define MC_CLIENT_HOTRESETN_ENABLE      0
+
+// Register MC_CLIENT_HOTRESETN_0  
+#define MC_CLIENT_HOTRESETN_0                   _MK_ADDR_CONST(0x104)
+#define MC_CLIENT_HOTRESETN_0_SECURE                    0x0
+#define MC_CLIENT_HOTRESETN_0_WORD_COUNT                        0x1
+#define MC_CLIENT_HOTRESETN_0_RESET_VAL                         _MK_MASK_CONST(0x7fff)
+#define MC_CLIENT_HOTRESETN_0_RESET_MASK                        _MK_MASK_CONST(0x7fff)
+#define MC_CLIENT_HOTRESETN_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_READ_MASK                         _MK_MASK_CONST(0x7fff)
+#define MC_CLIENT_HOTRESETN_0_WRITE_MASK                        _MK_MASK_CONST(0x7fff)
+#define MC_CLIENT_HOTRESETN_0_AVPC_HOTRESETN_SHIFT                      _MK_SHIFT_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_AVPC_HOTRESETN_FIELD                      (_MK_MASK_CONST(0x1) << MC_CLIENT_HOTRESETN_0_AVPC_HOTRESETN_SHIFT)
+#define MC_CLIENT_HOTRESETN_0_AVPC_HOTRESETN_RANGE                      0:0
+#define MC_CLIENT_HOTRESETN_0_AVPC_HOTRESETN_WOFFSET                    0x0
+#define MC_CLIENT_HOTRESETN_0_AVPC_HOTRESETN_DEFAULT                    _MK_MASK_CONST(0x1)
+#define MC_CLIENT_HOTRESETN_0_AVPC_HOTRESETN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_CLIENT_HOTRESETN_0_AVPC_HOTRESETN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_AVPC_HOTRESETN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_AVPC_HOTRESETN_INIT_ENUM                  DISABLE
+#define MC_CLIENT_HOTRESETN_0_AVPC_HOTRESETN_ENABLE                     _MK_ENUM_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_AVPC_HOTRESETN_DISABLE                    _MK_ENUM_CONST(1)
+#define MC_CLIENT_HOTRESETN_0_AVPC_HOTRESETN_ENABLED                    _MK_ENUM_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_AVPC_HOTRESETN_DISABLED                   _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_HOTRESETN_0_DC_HOTRESETN_SHIFT                        _MK_SHIFT_CONST(1)
+#define MC_CLIENT_HOTRESETN_0_DC_HOTRESETN_FIELD                        (_MK_MASK_CONST(0x1) << MC_CLIENT_HOTRESETN_0_DC_HOTRESETN_SHIFT)
+#define MC_CLIENT_HOTRESETN_0_DC_HOTRESETN_RANGE                        1:1
+#define MC_CLIENT_HOTRESETN_0_DC_HOTRESETN_WOFFSET                      0x0
+#define MC_CLIENT_HOTRESETN_0_DC_HOTRESETN_DEFAULT                      _MK_MASK_CONST(0x1)
+#define MC_CLIENT_HOTRESETN_0_DC_HOTRESETN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_CLIENT_HOTRESETN_0_DC_HOTRESETN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_DC_HOTRESETN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_DC_HOTRESETN_INIT_ENUM                    DISABLE
+#define MC_CLIENT_HOTRESETN_0_DC_HOTRESETN_ENABLE                       _MK_ENUM_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_DC_HOTRESETN_DISABLE                      _MK_ENUM_CONST(1)
+#define MC_CLIENT_HOTRESETN_0_DC_HOTRESETN_ENABLED                      _MK_ENUM_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_DC_HOTRESETN_DISABLED                     _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_HOTRESETN_0_DCB_HOTRESETN_SHIFT                       _MK_SHIFT_CONST(2)
+#define MC_CLIENT_HOTRESETN_0_DCB_HOTRESETN_FIELD                       (_MK_MASK_CONST(0x1) << MC_CLIENT_HOTRESETN_0_DCB_HOTRESETN_SHIFT)
+#define MC_CLIENT_HOTRESETN_0_DCB_HOTRESETN_RANGE                       2:2
+#define MC_CLIENT_HOTRESETN_0_DCB_HOTRESETN_WOFFSET                     0x0
+#define MC_CLIENT_HOTRESETN_0_DCB_HOTRESETN_DEFAULT                     _MK_MASK_CONST(0x1)
+#define MC_CLIENT_HOTRESETN_0_DCB_HOTRESETN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_CLIENT_HOTRESETN_0_DCB_HOTRESETN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_DCB_HOTRESETN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_DCB_HOTRESETN_INIT_ENUM                   DISABLE
+#define MC_CLIENT_HOTRESETN_0_DCB_HOTRESETN_ENABLE                      _MK_ENUM_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_DCB_HOTRESETN_DISABLE                     _MK_ENUM_CONST(1)
+#define MC_CLIENT_HOTRESETN_0_DCB_HOTRESETN_ENABLED                     _MK_ENUM_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_DCB_HOTRESETN_DISABLED                    _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_HOTRESETN_0_EPP_HOTRESETN_SHIFT                       _MK_SHIFT_CONST(3)
+#define MC_CLIENT_HOTRESETN_0_EPP_HOTRESETN_FIELD                       (_MK_MASK_CONST(0x1) << MC_CLIENT_HOTRESETN_0_EPP_HOTRESETN_SHIFT)
+#define MC_CLIENT_HOTRESETN_0_EPP_HOTRESETN_RANGE                       3:3
+#define MC_CLIENT_HOTRESETN_0_EPP_HOTRESETN_WOFFSET                     0x0
+#define MC_CLIENT_HOTRESETN_0_EPP_HOTRESETN_DEFAULT                     _MK_MASK_CONST(0x1)
+#define MC_CLIENT_HOTRESETN_0_EPP_HOTRESETN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_CLIENT_HOTRESETN_0_EPP_HOTRESETN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_EPP_HOTRESETN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_EPP_HOTRESETN_INIT_ENUM                   DISABLE
+#define MC_CLIENT_HOTRESETN_0_EPP_HOTRESETN_ENABLE                      _MK_ENUM_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_EPP_HOTRESETN_DISABLE                     _MK_ENUM_CONST(1)
+#define MC_CLIENT_HOTRESETN_0_EPP_HOTRESETN_ENABLED                     _MK_ENUM_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_EPP_HOTRESETN_DISABLED                    _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_HOTRESETN_0_G2_HOTRESETN_SHIFT                        _MK_SHIFT_CONST(4)
+#define MC_CLIENT_HOTRESETN_0_G2_HOTRESETN_FIELD                        (_MK_MASK_CONST(0x1) << MC_CLIENT_HOTRESETN_0_G2_HOTRESETN_SHIFT)
+#define MC_CLIENT_HOTRESETN_0_G2_HOTRESETN_RANGE                        4:4
+#define MC_CLIENT_HOTRESETN_0_G2_HOTRESETN_WOFFSET                      0x0
+#define MC_CLIENT_HOTRESETN_0_G2_HOTRESETN_DEFAULT                      _MK_MASK_CONST(0x1)
+#define MC_CLIENT_HOTRESETN_0_G2_HOTRESETN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_CLIENT_HOTRESETN_0_G2_HOTRESETN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_G2_HOTRESETN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_G2_HOTRESETN_INIT_ENUM                    DISABLE
+#define MC_CLIENT_HOTRESETN_0_G2_HOTRESETN_ENABLE                       _MK_ENUM_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_G2_HOTRESETN_DISABLE                      _MK_ENUM_CONST(1)
+#define MC_CLIENT_HOTRESETN_0_G2_HOTRESETN_ENABLED                      _MK_ENUM_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_G2_HOTRESETN_DISABLED                     _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_HOTRESETN_0_HC_HOTRESETN_SHIFT                        _MK_SHIFT_CONST(5)
+#define MC_CLIENT_HOTRESETN_0_HC_HOTRESETN_FIELD                        (_MK_MASK_CONST(0x1) << MC_CLIENT_HOTRESETN_0_HC_HOTRESETN_SHIFT)
+#define MC_CLIENT_HOTRESETN_0_HC_HOTRESETN_RANGE                        5:5
+#define MC_CLIENT_HOTRESETN_0_HC_HOTRESETN_WOFFSET                      0x0
+#define MC_CLIENT_HOTRESETN_0_HC_HOTRESETN_DEFAULT                      _MK_MASK_CONST(0x1)
+#define MC_CLIENT_HOTRESETN_0_HC_HOTRESETN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_CLIENT_HOTRESETN_0_HC_HOTRESETN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_HC_HOTRESETN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_HC_HOTRESETN_INIT_ENUM                    DISABLE
+#define MC_CLIENT_HOTRESETN_0_HC_HOTRESETN_ENABLE                       _MK_ENUM_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_HC_HOTRESETN_DISABLE                      _MK_ENUM_CONST(1)
+#define MC_CLIENT_HOTRESETN_0_HC_HOTRESETN_ENABLED                      _MK_ENUM_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_HC_HOTRESETN_DISABLED                     _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_HOTRESETN_0_ISP_HOTRESETN_SHIFT                       _MK_SHIFT_CONST(6)
+#define MC_CLIENT_HOTRESETN_0_ISP_HOTRESETN_FIELD                       (_MK_MASK_CONST(0x1) << MC_CLIENT_HOTRESETN_0_ISP_HOTRESETN_SHIFT)
+#define MC_CLIENT_HOTRESETN_0_ISP_HOTRESETN_RANGE                       6:6
+#define MC_CLIENT_HOTRESETN_0_ISP_HOTRESETN_WOFFSET                     0x0
+#define MC_CLIENT_HOTRESETN_0_ISP_HOTRESETN_DEFAULT                     _MK_MASK_CONST(0x1)
+#define MC_CLIENT_HOTRESETN_0_ISP_HOTRESETN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_CLIENT_HOTRESETN_0_ISP_HOTRESETN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_ISP_HOTRESETN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_ISP_HOTRESETN_INIT_ENUM                   DISABLE
+#define MC_CLIENT_HOTRESETN_0_ISP_HOTRESETN_ENABLE                      _MK_ENUM_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_ISP_HOTRESETN_DISABLE                     _MK_ENUM_CONST(1)
+#define MC_CLIENT_HOTRESETN_0_ISP_HOTRESETN_ENABLED                     _MK_ENUM_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_ISP_HOTRESETN_DISABLED                    _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_HOTRESETN_0_MPCORE_HOTRESETN_SHIFT                    _MK_SHIFT_CONST(7)
+#define MC_CLIENT_HOTRESETN_0_MPCORE_HOTRESETN_FIELD                    (_MK_MASK_CONST(0x1) << MC_CLIENT_HOTRESETN_0_MPCORE_HOTRESETN_SHIFT)
+#define MC_CLIENT_HOTRESETN_0_MPCORE_HOTRESETN_RANGE                    7:7
+#define MC_CLIENT_HOTRESETN_0_MPCORE_HOTRESETN_WOFFSET                  0x0
+#define MC_CLIENT_HOTRESETN_0_MPCORE_HOTRESETN_DEFAULT                  _MK_MASK_CONST(0x1)
+#define MC_CLIENT_HOTRESETN_0_MPCORE_HOTRESETN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_CLIENT_HOTRESETN_0_MPCORE_HOTRESETN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_MPCORE_HOTRESETN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_MPCORE_HOTRESETN_INIT_ENUM                        DISABLE
+#define MC_CLIENT_HOTRESETN_0_MPCORE_HOTRESETN_ENABLE                   _MK_ENUM_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_MPCORE_HOTRESETN_DISABLE                  _MK_ENUM_CONST(1)
+#define MC_CLIENT_HOTRESETN_0_MPCORE_HOTRESETN_ENABLED                  _MK_ENUM_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_MPCORE_HOTRESETN_DISABLED                 _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_HOTRESETN_0_MPEA_HOTRESETN_SHIFT                      _MK_SHIFT_CONST(8)
+#define MC_CLIENT_HOTRESETN_0_MPEA_HOTRESETN_FIELD                      (_MK_MASK_CONST(0x1) << MC_CLIENT_HOTRESETN_0_MPEA_HOTRESETN_SHIFT)
+#define MC_CLIENT_HOTRESETN_0_MPEA_HOTRESETN_RANGE                      8:8
+#define MC_CLIENT_HOTRESETN_0_MPEA_HOTRESETN_WOFFSET                    0x0
+#define MC_CLIENT_HOTRESETN_0_MPEA_HOTRESETN_DEFAULT                    _MK_MASK_CONST(0x1)
+#define MC_CLIENT_HOTRESETN_0_MPEA_HOTRESETN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_CLIENT_HOTRESETN_0_MPEA_HOTRESETN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_MPEA_HOTRESETN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_MPEA_HOTRESETN_INIT_ENUM                  DISABLE
+#define MC_CLIENT_HOTRESETN_0_MPEA_HOTRESETN_ENABLE                     _MK_ENUM_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_MPEA_HOTRESETN_DISABLE                    _MK_ENUM_CONST(1)
+#define MC_CLIENT_HOTRESETN_0_MPEA_HOTRESETN_ENABLED                    _MK_ENUM_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_MPEA_HOTRESETN_DISABLED                   _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_HOTRESETN_0_MPEB_HOTRESETN_SHIFT                      _MK_SHIFT_CONST(9)
+#define MC_CLIENT_HOTRESETN_0_MPEB_HOTRESETN_FIELD                      (_MK_MASK_CONST(0x1) << MC_CLIENT_HOTRESETN_0_MPEB_HOTRESETN_SHIFT)
+#define MC_CLIENT_HOTRESETN_0_MPEB_HOTRESETN_RANGE                      9:9
+#define MC_CLIENT_HOTRESETN_0_MPEB_HOTRESETN_WOFFSET                    0x0
+#define MC_CLIENT_HOTRESETN_0_MPEB_HOTRESETN_DEFAULT                    _MK_MASK_CONST(0x1)
+#define MC_CLIENT_HOTRESETN_0_MPEB_HOTRESETN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_CLIENT_HOTRESETN_0_MPEB_HOTRESETN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_MPEB_HOTRESETN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_MPEB_HOTRESETN_INIT_ENUM                  DISABLE
+#define MC_CLIENT_HOTRESETN_0_MPEB_HOTRESETN_ENABLE                     _MK_ENUM_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_MPEB_HOTRESETN_DISABLE                    _MK_ENUM_CONST(1)
+#define MC_CLIENT_HOTRESETN_0_MPEB_HOTRESETN_ENABLED                    _MK_ENUM_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_MPEB_HOTRESETN_DISABLED                   _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_HOTRESETN_0_MPEC_HOTRESETN_SHIFT                      _MK_SHIFT_CONST(10)
+#define MC_CLIENT_HOTRESETN_0_MPEC_HOTRESETN_FIELD                      (_MK_MASK_CONST(0x1) << MC_CLIENT_HOTRESETN_0_MPEC_HOTRESETN_SHIFT)
+#define MC_CLIENT_HOTRESETN_0_MPEC_HOTRESETN_RANGE                      10:10
+#define MC_CLIENT_HOTRESETN_0_MPEC_HOTRESETN_WOFFSET                    0x0
+#define MC_CLIENT_HOTRESETN_0_MPEC_HOTRESETN_DEFAULT                    _MK_MASK_CONST(0x1)
+#define MC_CLIENT_HOTRESETN_0_MPEC_HOTRESETN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_CLIENT_HOTRESETN_0_MPEC_HOTRESETN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_MPEC_HOTRESETN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_MPEC_HOTRESETN_INIT_ENUM                  DISABLE
+#define MC_CLIENT_HOTRESETN_0_MPEC_HOTRESETN_ENABLE                     _MK_ENUM_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_MPEC_HOTRESETN_DISABLE                    _MK_ENUM_CONST(1)
+#define MC_CLIENT_HOTRESETN_0_MPEC_HOTRESETN_ENABLED                    _MK_ENUM_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_MPEC_HOTRESETN_DISABLED                   _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_HOTRESETN_0_NV_HOTRESETN_SHIFT                        _MK_SHIFT_CONST(11)
+#define MC_CLIENT_HOTRESETN_0_NV_HOTRESETN_FIELD                        (_MK_MASK_CONST(0x1) << MC_CLIENT_HOTRESETN_0_NV_HOTRESETN_SHIFT)
+#define MC_CLIENT_HOTRESETN_0_NV_HOTRESETN_RANGE                        11:11
+#define MC_CLIENT_HOTRESETN_0_NV_HOTRESETN_WOFFSET                      0x0
+#define MC_CLIENT_HOTRESETN_0_NV_HOTRESETN_DEFAULT                      _MK_MASK_CONST(0x1)
+#define MC_CLIENT_HOTRESETN_0_NV_HOTRESETN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_CLIENT_HOTRESETN_0_NV_HOTRESETN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_NV_HOTRESETN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_NV_HOTRESETN_INIT_ENUM                    DISABLE
+#define MC_CLIENT_HOTRESETN_0_NV_HOTRESETN_ENABLE                       _MK_ENUM_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_NV_HOTRESETN_DISABLE                      _MK_ENUM_CONST(1)
+#define MC_CLIENT_HOTRESETN_0_NV_HOTRESETN_ENABLED                      _MK_ENUM_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_NV_HOTRESETN_DISABLED                     _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_HOTRESETN_0_PPCS_HOTRESETN_SHIFT                      _MK_SHIFT_CONST(12)
+#define MC_CLIENT_HOTRESETN_0_PPCS_HOTRESETN_FIELD                      (_MK_MASK_CONST(0x1) << MC_CLIENT_HOTRESETN_0_PPCS_HOTRESETN_SHIFT)
+#define MC_CLIENT_HOTRESETN_0_PPCS_HOTRESETN_RANGE                      12:12
+#define MC_CLIENT_HOTRESETN_0_PPCS_HOTRESETN_WOFFSET                    0x0
+#define MC_CLIENT_HOTRESETN_0_PPCS_HOTRESETN_DEFAULT                    _MK_MASK_CONST(0x1)
+#define MC_CLIENT_HOTRESETN_0_PPCS_HOTRESETN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_CLIENT_HOTRESETN_0_PPCS_HOTRESETN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_PPCS_HOTRESETN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_PPCS_HOTRESETN_INIT_ENUM                  DISABLE
+#define MC_CLIENT_HOTRESETN_0_PPCS_HOTRESETN_ENABLE                     _MK_ENUM_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_PPCS_HOTRESETN_DISABLE                    _MK_ENUM_CONST(1)
+#define MC_CLIENT_HOTRESETN_0_PPCS_HOTRESETN_ENABLED                    _MK_ENUM_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_PPCS_HOTRESETN_DISABLED                   _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_HOTRESETN_0_VDE_HOTRESETN_SHIFT                       _MK_SHIFT_CONST(13)
+#define MC_CLIENT_HOTRESETN_0_VDE_HOTRESETN_FIELD                       (_MK_MASK_CONST(0x1) << MC_CLIENT_HOTRESETN_0_VDE_HOTRESETN_SHIFT)
+#define MC_CLIENT_HOTRESETN_0_VDE_HOTRESETN_RANGE                       13:13
+#define MC_CLIENT_HOTRESETN_0_VDE_HOTRESETN_WOFFSET                     0x0
+#define MC_CLIENT_HOTRESETN_0_VDE_HOTRESETN_DEFAULT                     _MK_MASK_CONST(0x1)
+#define MC_CLIENT_HOTRESETN_0_VDE_HOTRESETN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_CLIENT_HOTRESETN_0_VDE_HOTRESETN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_VDE_HOTRESETN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_VDE_HOTRESETN_INIT_ENUM                   DISABLE
+#define MC_CLIENT_HOTRESETN_0_VDE_HOTRESETN_ENABLE                      _MK_ENUM_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_VDE_HOTRESETN_DISABLE                     _MK_ENUM_CONST(1)
+#define MC_CLIENT_HOTRESETN_0_VDE_HOTRESETN_ENABLED                     _MK_ENUM_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_VDE_HOTRESETN_DISABLED                    _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_HOTRESETN_0_VI_HOTRESETN_SHIFT                        _MK_SHIFT_CONST(14)
+#define MC_CLIENT_HOTRESETN_0_VI_HOTRESETN_FIELD                        (_MK_MASK_CONST(0x1) << MC_CLIENT_HOTRESETN_0_VI_HOTRESETN_SHIFT)
+#define MC_CLIENT_HOTRESETN_0_VI_HOTRESETN_RANGE                        14:14
+#define MC_CLIENT_HOTRESETN_0_VI_HOTRESETN_WOFFSET                      0x0
+#define MC_CLIENT_HOTRESETN_0_VI_HOTRESETN_DEFAULT                      _MK_MASK_CONST(0x1)
+#define MC_CLIENT_HOTRESETN_0_VI_HOTRESETN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_CLIENT_HOTRESETN_0_VI_HOTRESETN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_VI_HOTRESETN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_VI_HOTRESETN_INIT_ENUM                    DISABLE
+#define MC_CLIENT_HOTRESETN_0_VI_HOTRESETN_ENABLE                       _MK_ENUM_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_VI_HOTRESETN_DISABLE                      _MK_ENUM_CONST(1)
+#define MC_CLIENT_HOTRESETN_0_VI_HOTRESETN_ENABLED                      _MK_ENUM_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_VI_HOTRESETN_DISABLED                     _MK_ENUM_CONST(1)
+
+
+// Register MC_AXI_DECERR_OVR_0  
+#define MC_AXI_DECERR_OVR_0                     _MK_ADDR_CONST(0x108)
+#define MC_AXI_DECERR_OVR_0_SECURE                      0x0
+#define MC_AXI_DECERR_OVR_0_WORD_COUNT                  0x1
+#define MC_AXI_DECERR_OVR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define MC_AXI_DECERR_OVR_0_RESET_MASK                  _MK_MASK_CONST(0x3)
+#define MC_AXI_DECERR_OVR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define MC_AXI_DECERR_OVR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_AXI_DECERR_OVR_0_READ_MASK                   _MK_MASK_CONST(0x3)
+#define MC_AXI_DECERR_OVR_0_WRITE_MASK                  _MK_MASK_CONST(0x3)
+#define MC_AXI_DECERR_OVR_0_MPCORER_DECERR_OVR_SHIFT                    _MK_SHIFT_CONST(0)
+#define MC_AXI_DECERR_OVR_0_MPCORER_DECERR_OVR_FIELD                    (_MK_MASK_CONST(0x1) << MC_AXI_DECERR_OVR_0_MPCORER_DECERR_OVR_SHIFT)
+#define MC_AXI_DECERR_OVR_0_MPCORER_DECERR_OVR_RANGE                    0:0
+#define MC_AXI_DECERR_OVR_0_MPCORER_DECERR_OVR_WOFFSET                  0x0
+#define MC_AXI_DECERR_OVR_0_MPCORER_DECERR_OVR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_AXI_DECERR_OVR_0_MPCORER_DECERR_OVR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_AXI_DECERR_OVR_0_MPCORER_DECERR_OVR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_AXI_DECERR_OVR_0_MPCORER_DECERR_OVR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_AXI_DECERR_OVR_0_MPCORER_DECERR_OVR_INIT_ENUM                        DISABLE
+#define MC_AXI_DECERR_OVR_0_MPCORER_DECERR_OVR_DECERR_ALLOWED                   _MK_ENUM_CONST(0)
+#define MC_AXI_DECERR_OVR_0_MPCORER_DECERR_OVR_ALWAYS_OK                        _MK_ENUM_CONST(1)
+#define MC_AXI_DECERR_OVR_0_MPCORER_DECERR_OVR_DISABLE                  _MK_ENUM_CONST(0)
+#define MC_AXI_DECERR_OVR_0_MPCORER_DECERR_OVR_ENABLE                   _MK_ENUM_CONST(1)
+#define MC_AXI_DECERR_OVR_0_MPCORER_DECERR_OVR_DISABLED                 _MK_ENUM_CONST(0)
+#define MC_AXI_DECERR_OVR_0_MPCORER_DECERR_OVR_ENABLED                  _MK_ENUM_CONST(1)
+
+#define MC_AXI_DECERR_OVR_0_MPCOREW_DECERR_OVR_SHIFT                    _MK_SHIFT_CONST(1)
+#define MC_AXI_DECERR_OVR_0_MPCOREW_DECERR_OVR_FIELD                    (_MK_MASK_CONST(0x1) << MC_AXI_DECERR_OVR_0_MPCOREW_DECERR_OVR_SHIFT)
+#define MC_AXI_DECERR_OVR_0_MPCOREW_DECERR_OVR_RANGE                    1:1
+#define MC_AXI_DECERR_OVR_0_MPCOREW_DECERR_OVR_WOFFSET                  0x0
+#define MC_AXI_DECERR_OVR_0_MPCOREW_DECERR_OVR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_AXI_DECERR_OVR_0_MPCOREW_DECERR_OVR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_AXI_DECERR_OVR_0_MPCOREW_DECERR_OVR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_AXI_DECERR_OVR_0_MPCOREW_DECERR_OVR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_AXI_DECERR_OVR_0_MPCOREW_DECERR_OVR_INIT_ENUM                        DISABLE
+#define MC_AXI_DECERR_OVR_0_MPCOREW_DECERR_OVR_DECERR_ALLOWED                   _MK_ENUM_CONST(0)
+#define MC_AXI_DECERR_OVR_0_MPCOREW_DECERR_OVR_ALWAYS_OK                        _MK_ENUM_CONST(1)
+#define MC_AXI_DECERR_OVR_0_MPCOREW_DECERR_OVR_DISABLE                  _MK_ENUM_CONST(0)
+#define MC_AXI_DECERR_OVR_0_MPCOREW_DECERR_OVR_ENABLE                   _MK_ENUM_CONST(1)
+#define MC_AXI_DECERR_OVR_0_MPCOREW_DECERR_OVR_DISABLED                 _MK_ENUM_CONST(0)
+#define MC_AXI_DECERR_OVR_0_MPCOREW_DECERR_OVR_ENABLED                  _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_LL_CTRL_DISABLE       0
+#define MC_CLIENT_LL_CTRL_ENABLE        1
+
+// Register MC_LOWLATENCY_CONFIG_0  
+#define MC_LOWLATENCY_CONFIG_0                  _MK_ADDR_CONST(0x10c)
+#define MC_LOWLATENCY_CONFIG_0_SECURE                   0x0
+#define MC_LOWLATENCY_CONFIG_0_WORD_COUNT                       0x1
+#define MC_LOWLATENCY_CONFIG_0_RESET_VAL                        _MK_MASK_CONST(0x80000003)
+#define MC_LOWLATENCY_CONFIG_0_RESET_MASK                       _MK_MASK_CONST(0x80000003)
+#define MC_LOWLATENCY_CONFIG_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_CONFIG_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_CONFIG_0_READ_MASK                        _MK_MASK_CONST(0x80000003)
+#define MC_LOWLATENCY_CONFIG_0_WRITE_MASK                       _MK_MASK_CONST(0x80000003)
+#define MC_LOWLATENCY_CONFIG_0_MPCORER_LL_CTRL_SHIFT                    _MK_SHIFT_CONST(0)
+#define MC_LOWLATENCY_CONFIG_0_MPCORER_LL_CTRL_FIELD                    (_MK_MASK_CONST(0x1) << MC_LOWLATENCY_CONFIG_0_MPCORER_LL_CTRL_SHIFT)
+#define MC_LOWLATENCY_CONFIG_0_MPCORER_LL_CTRL_RANGE                    0:0
+#define MC_LOWLATENCY_CONFIG_0_MPCORER_LL_CTRL_WOFFSET                  0x0
+#define MC_LOWLATENCY_CONFIG_0_MPCORER_LL_CTRL_DEFAULT                  _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_CONFIG_0_MPCORER_LL_CTRL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_CONFIG_0_MPCORER_LL_CTRL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_CONFIG_0_MPCORER_LL_CTRL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_CONFIG_0_MPCORER_LL_CTRL_INIT_ENUM                        ENABLE
+#define MC_LOWLATENCY_CONFIG_0_MPCORER_LL_CTRL_DISABLE                  _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_CONFIG_0_MPCORER_LL_CTRL_ENABLE                   _MK_ENUM_CONST(1)
+#define MC_LOWLATENCY_CONFIG_0_MPCORER_LL_CTRL_DISABLED                 _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_CONFIG_0_MPCORER_LL_CTRL_ENABLED                  _MK_ENUM_CONST(1)
+
+#define MC_LOWLATENCY_CONFIG_0_MPCORER_LL_SEND_BOTH_SHIFT                       _MK_SHIFT_CONST(1)
+#define MC_LOWLATENCY_CONFIG_0_MPCORER_LL_SEND_BOTH_FIELD                       (_MK_MASK_CONST(0x1) << MC_LOWLATENCY_CONFIG_0_MPCORER_LL_SEND_BOTH_SHIFT)
+#define MC_LOWLATENCY_CONFIG_0_MPCORER_LL_SEND_BOTH_RANGE                       1:1
+#define MC_LOWLATENCY_CONFIG_0_MPCORER_LL_SEND_BOTH_WOFFSET                     0x0
+#define MC_LOWLATENCY_CONFIG_0_MPCORER_LL_SEND_BOTH_DEFAULT                     _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_CONFIG_0_MPCORER_LL_SEND_BOTH_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_CONFIG_0_MPCORER_LL_SEND_BOTH_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_CONFIG_0_MPCORER_LL_SEND_BOTH_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_CONFIG_0_MPCORER_LL_SEND_BOTH_INIT_ENUM                   ENABLE
+#define MC_LOWLATENCY_CONFIG_0_MPCORER_LL_SEND_BOTH_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_CONFIG_0_MPCORER_LL_SEND_BOTH_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_LOWLATENCY_CONFIG_0_MPCORER_LL_SEND_BOTH_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_CONFIG_0_MPCORER_LL_SEND_BOTH_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_LOWLATENCY_CONFIG_0_LL_DRAM_INTERLEAVE_SHIFT                 _MK_SHIFT_CONST(31)
+#define MC_LOWLATENCY_CONFIG_0_LL_DRAM_INTERLEAVE_FIELD                 (_MK_MASK_CONST(0x1) << MC_LOWLATENCY_CONFIG_0_LL_DRAM_INTERLEAVE_SHIFT)
+#define MC_LOWLATENCY_CONFIG_0_LL_DRAM_INTERLEAVE_RANGE                 31:31
+#define MC_LOWLATENCY_CONFIG_0_LL_DRAM_INTERLEAVE_WOFFSET                       0x0
+#define MC_LOWLATENCY_CONFIG_0_LL_DRAM_INTERLEAVE_DEFAULT                       _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_CONFIG_0_LL_DRAM_INTERLEAVE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_CONFIG_0_LL_DRAM_INTERLEAVE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_CONFIG_0_LL_DRAM_INTERLEAVE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_CONFIG_0_LL_DRAM_INTERLEAVE_INIT_ENUM                     ENABLE
+#define MC_LOWLATENCY_CONFIG_0_LL_DRAM_INTERLEAVE_DISABLE                       _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_CONFIG_0_LL_DRAM_INTERLEAVE_ENABLE                        _MK_ENUM_CONST(1)
+#define MC_LOWLATENCY_CONFIG_0_LL_DRAM_INTERLEAVE_DISABLED                      _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_CONFIG_0_LL_DRAM_INTERLEAVE_ENABLED                       _MK_ENUM_CONST(1)
+
+
+// Register MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0  
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0                     _MK_ADDR_CONST(0x110)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_SECURE                      0x0
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_WORD_COUNT                  0x1
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_RESET_VAL                   _MK_MASK_CONST(0xfffff)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_RESET_MASK                  _MK_MASK_CONST(0xfffff)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_READ_MASK                   _MK_MASK_CONST(0xfffff)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_WRITE_MASK                  _MK_MASK_CONST(0xfffff)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPU_LL_RAW_PARTICIPATE_SHIFT                       _MK_SHIFT_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPU_LL_RAW_PARTICIPATE_FIELD                       (_MK_MASK_CONST(0x1) << MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPU_LL_RAW_PARTICIPATE_SHIFT)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPU_LL_RAW_PARTICIPATE_RANGE                       0:0
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPU_LL_RAW_PARTICIPATE_WOFFSET                     0x0
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPU_LL_RAW_PARTICIPATE_DEFAULT                     _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPU_LL_RAW_PARTICIPATE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPU_LL_RAW_PARTICIPATE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPU_LL_RAW_PARTICIPATE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPU_LL_RAW_PARTICIPATE_INIT_ENUM                   ENABLE
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPU_LL_RAW_PARTICIPATE_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPU_LL_RAW_PARTICIPATE_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPU_LL_RAW_PARTICIPATE_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPU_LL_RAW_PARTICIPATE_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPV_LL_RAW_PARTICIPATE_SHIFT                       _MK_SHIFT_CONST(1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPV_LL_RAW_PARTICIPATE_FIELD                       (_MK_MASK_CONST(0x1) << MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPV_LL_RAW_PARTICIPATE_SHIFT)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPV_LL_RAW_PARTICIPATE_RANGE                       1:1
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPV_LL_RAW_PARTICIPATE_WOFFSET                     0x0
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPV_LL_RAW_PARTICIPATE_DEFAULT                     _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPV_LL_RAW_PARTICIPATE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPV_LL_RAW_PARTICIPATE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPV_LL_RAW_PARTICIPATE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPV_LL_RAW_PARTICIPATE_INIT_ENUM                   ENABLE
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPV_LL_RAW_PARTICIPATE_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPV_LL_RAW_PARTICIPATE_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPV_LL_RAW_PARTICIPATE_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPV_LL_RAW_PARTICIPATE_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPY_LL_RAW_PARTICIPATE_SHIFT                       _MK_SHIFT_CONST(2)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPY_LL_RAW_PARTICIPATE_FIELD                       (_MK_MASK_CONST(0x1) << MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPY_LL_RAW_PARTICIPATE_SHIFT)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPY_LL_RAW_PARTICIPATE_RANGE                       2:2
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPY_LL_RAW_PARTICIPATE_WOFFSET                     0x0
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPY_LL_RAW_PARTICIPATE_DEFAULT                     _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPY_LL_RAW_PARTICIPATE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPY_LL_RAW_PARTICIPATE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPY_LL_RAW_PARTICIPATE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPY_LL_RAW_PARTICIPATE_INIT_ENUM                   ENABLE
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPY_LL_RAW_PARTICIPATE_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPY_LL_RAW_PARTICIPATE_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPY_LL_RAW_PARTICIPATE_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPY_LL_RAW_PARTICIPATE_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPEUNIFBW_LL_RAW_PARTICIPATE_SHIFT                  _MK_SHIFT_CONST(3)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPEUNIFBW_LL_RAW_PARTICIPATE_FIELD                  (_MK_MASK_CONST(0x1) << MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPEUNIFBW_LL_RAW_PARTICIPATE_SHIFT)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPEUNIFBW_LL_RAW_PARTICIPATE_RANGE                  3:3
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPEUNIFBW_LL_RAW_PARTICIPATE_WOFFSET                        0x0
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPEUNIFBW_LL_RAW_PARTICIPATE_DEFAULT                        _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPEUNIFBW_LL_RAW_PARTICIPATE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPEUNIFBW_LL_RAW_PARTICIPATE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPEUNIFBW_LL_RAW_PARTICIPATE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPEUNIFBW_LL_RAW_PARTICIPATE_INIT_ENUM                      ENABLE
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPEUNIFBW_LL_RAW_PARTICIPATE_DISABLE                        _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPEUNIFBW_LL_RAW_PARTICIPATE_ENABLE                 _MK_ENUM_CONST(1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPEUNIFBW_LL_RAW_PARTICIPATE_DISABLED                       _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPEUNIFBW_LL_RAW_PARTICIPATE_ENABLED                        _MK_ENUM_CONST(1)
+
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWSB_LL_RAW_PARTICIPATE_SHIFT                      _MK_SHIFT_CONST(4)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWSB_LL_RAW_PARTICIPATE_FIELD                      (_MK_MASK_CONST(0x1) << MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWSB_LL_RAW_PARTICIPATE_SHIFT)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWSB_LL_RAW_PARTICIPATE_RANGE                      4:4
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWSB_LL_RAW_PARTICIPATE_WOFFSET                    0x0
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWSB_LL_RAW_PARTICIPATE_DEFAULT                    _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWSB_LL_RAW_PARTICIPATE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWSB_LL_RAW_PARTICIPATE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWSB_LL_RAW_PARTICIPATE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWSB_LL_RAW_PARTICIPATE_INIT_ENUM                  ENABLE
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWSB_LL_RAW_PARTICIPATE_DISABLE                    _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWSB_LL_RAW_PARTICIPATE_ENABLE                     _MK_ENUM_CONST(1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWSB_LL_RAW_PARTICIPATE_DISABLED                   _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWSB_LL_RAW_PARTICIPATE_ENABLED                    _MK_ENUM_CONST(1)
+
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWU_LL_RAW_PARTICIPATE_SHIFT                       _MK_SHIFT_CONST(5)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWU_LL_RAW_PARTICIPATE_FIELD                       (_MK_MASK_CONST(0x1) << MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWU_LL_RAW_PARTICIPATE_SHIFT)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWU_LL_RAW_PARTICIPATE_RANGE                       5:5
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWU_LL_RAW_PARTICIPATE_WOFFSET                     0x0
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWU_LL_RAW_PARTICIPATE_DEFAULT                     _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWU_LL_RAW_PARTICIPATE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWU_LL_RAW_PARTICIPATE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWU_LL_RAW_PARTICIPATE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWU_LL_RAW_PARTICIPATE_INIT_ENUM                   ENABLE
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWU_LL_RAW_PARTICIPATE_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWU_LL_RAW_PARTICIPATE_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWU_LL_RAW_PARTICIPATE_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWU_LL_RAW_PARTICIPATE_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWV_LL_RAW_PARTICIPATE_SHIFT                       _MK_SHIFT_CONST(6)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWV_LL_RAW_PARTICIPATE_FIELD                       (_MK_MASK_CONST(0x1) << MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWV_LL_RAW_PARTICIPATE_SHIFT)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWV_LL_RAW_PARTICIPATE_RANGE                       6:6
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWV_LL_RAW_PARTICIPATE_WOFFSET                     0x0
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWV_LL_RAW_PARTICIPATE_DEFAULT                     _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWV_LL_RAW_PARTICIPATE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWV_LL_RAW_PARTICIPATE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWV_LL_RAW_PARTICIPATE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWV_LL_RAW_PARTICIPATE_INIT_ENUM                   ENABLE
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWV_LL_RAW_PARTICIPATE_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWV_LL_RAW_PARTICIPATE_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWV_LL_RAW_PARTICIPATE_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWV_LL_RAW_PARTICIPATE_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWY_LL_RAW_PARTICIPATE_SHIFT                       _MK_SHIFT_CONST(7)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWY_LL_RAW_PARTICIPATE_FIELD                       (_MK_MASK_CONST(0x1) << MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWY_LL_RAW_PARTICIPATE_SHIFT)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWY_LL_RAW_PARTICIPATE_RANGE                       7:7
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWY_LL_RAW_PARTICIPATE_WOFFSET                     0x0
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWY_LL_RAW_PARTICIPATE_DEFAULT                     _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWY_LL_RAW_PARTICIPATE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWY_LL_RAW_PARTICIPATE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWY_LL_RAW_PARTICIPATE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWY_LL_RAW_PARTICIPATE_INIT_ENUM                   ENABLE
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWY_LL_RAW_PARTICIPATE_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWY_LL_RAW_PARTICIPATE_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWY_LL_RAW_PARTICIPATE_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWY_LL_RAW_PARTICIPATE_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_G2DW_LL_RAW_PARTICIPATE_SHIFT                       _MK_SHIFT_CONST(8)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_G2DW_LL_RAW_PARTICIPATE_FIELD                       (_MK_MASK_CONST(0x1) << MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_G2DW_LL_RAW_PARTICIPATE_SHIFT)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_G2DW_LL_RAW_PARTICIPATE_RANGE                       8:8
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_G2DW_LL_RAW_PARTICIPATE_WOFFSET                     0x0
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_G2DW_LL_RAW_PARTICIPATE_DEFAULT                     _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_G2DW_LL_RAW_PARTICIPATE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_G2DW_LL_RAW_PARTICIPATE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_G2DW_LL_RAW_PARTICIPATE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_G2DW_LL_RAW_PARTICIPATE_INIT_ENUM                   ENABLE
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_G2DW_LL_RAW_PARTICIPATE_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_G2DW_LL_RAW_PARTICIPATE_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_G2DW_LL_RAW_PARTICIPATE_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_G2DW_LL_RAW_PARTICIPATE_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_AVPCARM7W_LL_RAW_PARTICIPATE_SHIFT                  _MK_SHIFT_CONST(9)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_AVPCARM7W_LL_RAW_PARTICIPATE_FIELD                  (_MK_MASK_CONST(0x1) << MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_AVPCARM7W_LL_RAW_PARTICIPATE_SHIFT)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_AVPCARM7W_LL_RAW_PARTICIPATE_RANGE                  9:9
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_AVPCARM7W_LL_RAW_PARTICIPATE_WOFFSET                        0x0
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_AVPCARM7W_LL_RAW_PARTICIPATE_DEFAULT                        _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_AVPCARM7W_LL_RAW_PARTICIPATE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_AVPCARM7W_LL_RAW_PARTICIPATE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_AVPCARM7W_LL_RAW_PARTICIPATE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_AVPCARM7W_LL_RAW_PARTICIPATE_INIT_ENUM                      ENABLE
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_AVPCARM7W_LL_RAW_PARTICIPATE_DISABLE                        _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_AVPCARM7W_LL_RAW_PARTICIPATE_ENABLE                 _MK_ENUM_CONST(1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_AVPCARM7W_LL_RAW_PARTICIPATE_DISABLED                       _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_AVPCARM7W_LL_RAW_PARTICIPATE_ENABLED                        _MK_ENUM_CONST(1)
+
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_FDCDWR_LL_RAW_PARTICIPATE_SHIFT                     _MK_SHIFT_CONST(10)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_FDCDWR_LL_RAW_PARTICIPATE_FIELD                     (_MK_MASK_CONST(0x1) << MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_FDCDWR_LL_RAW_PARTICIPATE_SHIFT)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_FDCDWR_LL_RAW_PARTICIPATE_RANGE                     10:10
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_FDCDWR_LL_RAW_PARTICIPATE_WOFFSET                   0x0
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_FDCDWR_LL_RAW_PARTICIPATE_DEFAULT                   _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_FDCDWR_LL_RAW_PARTICIPATE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_FDCDWR_LL_RAW_PARTICIPATE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_FDCDWR_LL_RAW_PARTICIPATE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_FDCDWR_LL_RAW_PARTICIPATE_INIT_ENUM                 ENABLE
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_FDCDWR_LL_RAW_PARTICIPATE_DISABLE                   _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_FDCDWR_LL_RAW_PARTICIPATE_ENABLE                    _MK_ENUM_CONST(1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_FDCDWR_LL_RAW_PARTICIPATE_DISABLED                  _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_FDCDWR_LL_RAW_PARTICIPATE_ENABLED                   _MK_ENUM_CONST(1)
+
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_HOST1XW_LL_RAW_PARTICIPATE_SHIFT                    _MK_SHIFT_CONST(11)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_HOST1XW_LL_RAW_PARTICIPATE_FIELD                    (_MK_MASK_CONST(0x1) << MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_HOST1XW_LL_RAW_PARTICIPATE_SHIFT)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_HOST1XW_LL_RAW_PARTICIPATE_RANGE                    11:11
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_HOST1XW_LL_RAW_PARTICIPATE_WOFFSET                  0x0
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_HOST1XW_LL_RAW_PARTICIPATE_DEFAULT                  _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_HOST1XW_LL_RAW_PARTICIPATE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_HOST1XW_LL_RAW_PARTICIPATE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_HOST1XW_LL_RAW_PARTICIPATE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_HOST1XW_LL_RAW_PARTICIPATE_INIT_ENUM                        ENABLE
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_HOST1XW_LL_RAW_PARTICIPATE_DISABLE                  _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_HOST1XW_LL_RAW_PARTICIPATE_ENABLE                   _MK_ENUM_CONST(1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_HOST1XW_LL_RAW_PARTICIPATE_DISABLED                 _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_HOST1XW_LL_RAW_PARTICIPATE_ENABLED                  _MK_ENUM_CONST(1)
+
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_ISPW_LL_RAW_PARTICIPATE_SHIFT                       _MK_SHIFT_CONST(12)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_ISPW_LL_RAW_PARTICIPATE_FIELD                       (_MK_MASK_CONST(0x1) << MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_ISPW_LL_RAW_PARTICIPATE_SHIFT)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_ISPW_LL_RAW_PARTICIPATE_RANGE                       12:12
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_ISPW_LL_RAW_PARTICIPATE_WOFFSET                     0x0
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_ISPW_LL_RAW_PARTICIPATE_DEFAULT                     _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_ISPW_LL_RAW_PARTICIPATE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_ISPW_LL_RAW_PARTICIPATE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_ISPW_LL_RAW_PARTICIPATE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_ISPW_LL_RAW_PARTICIPATE_INIT_ENUM                   ENABLE
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_ISPW_LL_RAW_PARTICIPATE_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_ISPW_LL_RAW_PARTICIPATE_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_ISPW_LL_RAW_PARTICIPATE_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_ISPW_LL_RAW_PARTICIPATE_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPCOREW_LL_RAW_PARTICIPATE_SHIFT                    _MK_SHIFT_CONST(13)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPCOREW_LL_RAW_PARTICIPATE_FIELD                    (_MK_MASK_CONST(0x1) << MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPCOREW_LL_RAW_PARTICIPATE_SHIFT)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPCOREW_LL_RAW_PARTICIPATE_RANGE                    13:13
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPCOREW_LL_RAW_PARTICIPATE_WOFFSET                  0x0
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPCOREW_LL_RAW_PARTICIPATE_DEFAULT                  _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPCOREW_LL_RAW_PARTICIPATE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPCOREW_LL_RAW_PARTICIPATE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPCOREW_LL_RAW_PARTICIPATE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPCOREW_LL_RAW_PARTICIPATE_INIT_ENUM                        ENABLE
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPCOREW_LL_RAW_PARTICIPATE_DISABLE                  _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPCOREW_LL_RAW_PARTICIPATE_ENABLE                   _MK_ENUM_CONST(1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPCOREW_LL_RAW_PARTICIPATE_DISABLED                 _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPCOREW_LL_RAW_PARTICIPATE_ENABLED                  _MK_ENUM_CONST(1)
+
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPECSWR_LL_RAW_PARTICIPATE_SHIFT                    _MK_SHIFT_CONST(14)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPECSWR_LL_RAW_PARTICIPATE_FIELD                    (_MK_MASK_CONST(0x1) << MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPECSWR_LL_RAW_PARTICIPATE_SHIFT)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPECSWR_LL_RAW_PARTICIPATE_RANGE                    14:14
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPECSWR_LL_RAW_PARTICIPATE_WOFFSET                  0x0
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPECSWR_LL_RAW_PARTICIPATE_DEFAULT                  _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPECSWR_LL_RAW_PARTICIPATE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPECSWR_LL_RAW_PARTICIPATE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPECSWR_LL_RAW_PARTICIPATE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPECSWR_LL_RAW_PARTICIPATE_INIT_ENUM                        ENABLE
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPECSWR_LL_RAW_PARTICIPATE_DISABLE                  _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPECSWR_LL_RAW_PARTICIPATE_ENABLE                   _MK_ENUM_CONST(1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPECSWR_LL_RAW_PARTICIPATE_DISABLED                 _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPECSWR_LL_RAW_PARTICIPATE_ENABLED                  _MK_ENUM_CONST(1)
+
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSAHBDMAW_LL_RAW_PARTICIPATE_SHIFT                        _MK_SHIFT_CONST(15)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSAHBDMAW_LL_RAW_PARTICIPATE_FIELD                        (_MK_MASK_CONST(0x1) << MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSAHBDMAW_LL_RAW_PARTICIPATE_SHIFT)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSAHBDMAW_LL_RAW_PARTICIPATE_RANGE                        15:15
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSAHBDMAW_LL_RAW_PARTICIPATE_WOFFSET                      0x0
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSAHBDMAW_LL_RAW_PARTICIPATE_DEFAULT                      _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSAHBDMAW_LL_RAW_PARTICIPATE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSAHBDMAW_LL_RAW_PARTICIPATE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSAHBDMAW_LL_RAW_PARTICIPATE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSAHBDMAW_LL_RAW_PARTICIPATE_INIT_ENUM                    ENABLE
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSAHBDMAW_LL_RAW_PARTICIPATE_DISABLE                      _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSAHBDMAW_LL_RAW_PARTICIPATE_ENABLE                       _MK_ENUM_CONST(1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSAHBDMAW_LL_RAW_PARTICIPATE_DISABLED                     _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSAHBDMAW_LL_RAW_PARTICIPATE_ENABLED                      _MK_ENUM_CONST(1)
+
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSAHBSLVW_LL_RAW_PARTICIPATE_SHIFT                        _MK_SHIFT_CONST(16)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSAHBSLVW_LL_RAW_PARTICIPATE_FIELD                        (_MK_MASK_CONST(0x1) << MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSAHBSLVW_LL_RAW_PARTICIPATE_SHIFT)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSAHBSLVW_LL_RAW_PARTICIPATE_RANGE                        16:16
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSAHBSLVW_LL_RAW_PARTICIPATE_WOFFSET                      0x0
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSAHBSLVW_LL_RAW_PARTICIPATE_DEFAULT                      _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSAHBSLVW_LL_RAW_PARTICIPATE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSAHBSLVW_LL_RAW_PARTICIPATE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSAHBSLVW_LL_RAW_PARTICIPATE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSAHBSLVW_LL_RAW_PARTICIPATE_INIT_ENUM                    ENABLE
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSAHBSLVW_LL_RAW_PARTICIPATE_DISABLE                      _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSAHBSLVW_LL_RAW_PARTICIPATE_ENABLE                       _MK_ENUM_CONST(1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSAHBSLVW_LL_RAW_PARTICIPATE_DISABLED                     _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSAHBSLVW_LL_RAW_PARTICIPATE_ENABLED                      _MK_ENUM_CONST(1)
+
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEBSEVW_LL_RAW_PARTICIPATE_SHIFT                   _MK_SHIFT_CONST(17)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEBSEVW_LL_RAW_PARTICIPATE_FIELD                   (_MK_MASK_CONST(0x1) << MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEBSEVW_LL_RAW_PARTICIPATE_SHIFT)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEBSEVW_LL_RAW_PARTICIPATE_RANGE                   17:17
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEBSEVW_LL_RAW_PARTICIPATE_WOFFSET                 0x0
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEBSEVW_LL_RAW_PARTICIPATE_DEFAULT                 _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEBSEVW_LL_RAW_PARTICIPATE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEBSEVW_LL_RAW_PARTICIPATE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEBSEVW_LL_RAW_PARTICIPATE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEBSEVW_LL_RAW_PARTICIPATE_INIT_ENUM                       ENABLE
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEBSEVW_LL_RAW_PARTICIPATE_DISABLE                 _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEBSEVW_LL_RAW_PARTICIPATE_ENABLE                  _MK_ENUM_CONST(1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEBSEVW_LL_RAW_PARTICIPATE_DISABLED                        _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEBSEVW_LL_RAW_PARTICIPATE_ENABLED                 _MK_ENUM_CONST(1)
+
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEMBEW_LL_RAW_PARTICIPATE_SHIFT                    _MK_SHIFT_CONST(18)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEMBEW_LL_RAW_PARTICIPATE_FIELD                    (_MK_MASK_CONST(0x1) << MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEMBEW_LL_RAW_PARTICIPATE_SHIFT)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEMBEW_LL_RAW_PARTICIPATE_RANGE                    18:18
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEMBEW_LL_RAW_PARTICIPATE_WOFFSET                  0x0
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEMBEW_LL_RAW_PARTICIPATE_DEFAULT                  _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEMBEW_LL_RAW_PARTICIPATE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEMBEW_LL_RAW_PARTICIPATE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEMBEW_LL_RAW_PARTICIPATE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEMBEW_LL_RAW_PARTICIPATE_INIT_ENUM                        ENABLE
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEMBEW_LL_RAW_PARTICIPATE_DISABLE                  _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEMBEW_LL_RAW_PARTICIPATE_ENABLE                   _MK_ENUM_CONST(1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEMBEW_LL_RAW_PARTICIPATE_DISABLED                 _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEMBEW_LL_RAW_PARTICIPATE_ENABLED                  _MK_ENUM_CONST(1)
+
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDETPMW_LL_RAW_PARTICIPATE_SHIFT                    _MK_SHIFT_CONST(19)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDETPMW_LL_RAW_PARTICIPATE_FIELD                    (_MK_MASK_CONST(0x1) << MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDETPMW_LL_RAW_PARTICIPATE_SHIFT)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDETPMW_LL_RAW_PARTICIPATE_RANGE                    19:19
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDETPMW_LL_RAW_PARTICIPATE_WOFFSET                  0x0
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDETPMW_LL_RAW_PARTICIPATE_DEFAULT                  _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDETPMW_LL_RAW_PARTICIPATE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDETPMW_LL_RAW_PARTICIPATE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDETPMW_LL_RAW_PARTICIPATE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDETPMW_LL_RAW_PARTICIPATE_INIT_ENUM                        ENABLE
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDETPMW_LL_RAW_PARTICIPATE_DISABLE                  _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDETPMW_LL_RAW_PARTICIPATE_ENABLE                   _MK_ENUM_CONST(1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDETPMW_LL_RAW_PARTICIPATE_DISABLED                 _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDETPMW_LL_RAW_PARTICIPATE_ENABLED                  _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_BWSHARE_DISABLE       0
+#define MC_CLIENT_BWSHARE_ENABLE        1
+
+// Register MC_BWSHARE_TMVAL_0  
+#define MC_BWSHARE_TMVAL_0                      _MK_ADDR_CONST(0x114)
+#define MC_BWSHARE_TMVAL_0_SECURE                       0x0
+#define MC_BWSHARE_TMVAL_0_WORD_COUNT                   0x1
+#define MC_BWSHARE_TMVAL_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_TMVAL_0_RESET_MASK                   _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_TMVAL_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_TMVAL_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_TMVAL_0_READ_MASK                    _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_TMVAL_0_WRITE_MASK                   _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_TMVAL_0_BW_TM_SFACTOR1_SHIFT                 _MK_SHIFT_CONST(0)
+#define MC_BWSHARE_TMVAL_0_BW_TM_SFACTOR1_FIELD                 (_MK_MASK_CONST(0xf) << MC_BWSHARE_TMVAL_0_BW_TM_SFACTOR1_SHIFT)
+#define MC_BWSHARE_TMVAL_0_BW_TM_SFACTOR1_RANGE                 3:0
+#define MC_BWSHARE_TMVAL_0_BW_TM_SFACTOR1_WOFFSET                       0x0
+#define MC_BWSHARE_TMVAL_0_BW_TM_SFACTOR1_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_TMVAL_0_BW_TM_SFACTOR1_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define MC_BWSHARE_TMVAL_0_BW_TM_SFACTOR1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_TMVAL_0_BW_TM_SFACTOR1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_TMVAL_0_BW_TM_SFACTOR2_SHIFT                 _MK_SHIFT_CONST(4)
+#define MC_BWSHARE_TMVAL_0_BW_TM_SFACTOR2_FIELD                 (_MK_MASK_CONST(0xf) << MC_BWSHARE_TMVAL_0_BW_TM_SFACTOR2_SHIFT)
+#define MC_BWSHARE_TMVAL_0_BW_TM_SFACTOR2_RANGE                 7:4
+#define MC_BWSHARE_TMVAL_0_BW_TM_SFACTOR2_WOFFSET                       0x0
+#define MC_BWSHARE_TMVAL_0_BW_TM_SFACTOR2_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_TMVAL_0_BW_TM_SFACTOR2_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define MC_BWSHARE_TMVAL_0_BW_TM_SFACTOR2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_TMVAL_0_BW_TM_SFACTOR2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Reserved address 280 [0x118] 
+
+// Reserved address 284 [0x11c] 
+
+// Register MC_BWSHARE_EMEM_CTRL_0_0  
+#define MC_BWSHARE_EMEM_CTRL_0_0                        _MK_ADDR_CONST(0x120)
+#define MC_BWSHARE_EMEM_CTRL_0_0_SECURE                         0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_WORD_COUNT                     0x1
+#define MC_BWSHARE_EMEM_CTRL_0_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
+#define MC_BWSHARE_EMEM_CTRL_0_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define MC_BWSHARE_EMEM_CTRL_0_0_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0A_BW_EMEM_SHIFT                        _MK_SHIFT_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0A_BW_EMEM_FIELD                        (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0A_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0A_BW_EMEM_RANGE                        0:0
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0A_BW_EMEM_WOFFSET                      0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0A_BW_EMEM_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0A_BW_EMEM_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0A_BW_EMEM_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0A_BW_EMEM_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0A_BW_EMEM_INIT_ENUM                    DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0A_BW_EMEM_DISABLE                      _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0A_BW_EMEM_ENABLE                       _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0A_BW_EMEM_DISABLED                     _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0A_BW_EMEM_ENABLED                      _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0AB_BW_EMEM_SHIFT                       _MK_SHIFT_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0AB_BW_EMEM_FIELD                       (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0AB_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0AB_BW_EMEM_RANGE                       1:1
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0AB_BW_EMEM_WOFFSET                     0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0AB_BW_EMEM_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0AB_BW_EMEM_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0AB_BW_EMEM_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0AB_BW_EMEM_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0AB_BW_EMEM_INIT_ENUM                   DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0AB_BW_EMEM_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0AB_BW_EMEM_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0AB_BW_EMEM_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0AB_BW_EMEM_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0B_BW_EMEM_SHIFT                        _MK_SHIFT_CONST(2)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0B_BW_EMEM_FIELD                        (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0B_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0B_BW_EMEM_RANGE                        2:2
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0B_BW_EMEM_WOFFSET                      0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0B_BW_EMEM_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0B_BW_EMEM_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0B_BW_EMEM_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0B_BW_EMEM_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0B_BW_EMEM_INIT_ENUM                    DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0B_BW_EMEM_DISABLE                      _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0B_BW_EMEM_ENABLE                       _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0B_BW_EMEM_DISABLED                     _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0B_BW_EMEM_ENABLED                      _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0BB_BW_EMEM_SHIFT                       _MK_SHIFT_CONST(3)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0BB_BW_EMEM_FIELD                       (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0BB_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0BB_BW_EMEM_RANGE                       3:3
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0BB_BW_EMEM_WOFFSET                     0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0BB_BW_EMEM_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0BB_BW_EMEM_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0BB_BW_EMEM_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0BB_BW_EMEM_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0BB_BW_EMEM_INIT_ENUM                   DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0BB_BW_EMEM_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0BB_BW_EMEM_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0BB_BW_EMEM_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0BB_BW_EMEM_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0C_BW_EMEM_SHIFT                        _MK_SHIFT_CONST(4)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0C_BW_EMEM_FIELD                        (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0C_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0C_BW_EMEM_RANGE                        4:4
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0C_BW_EMEM_WOFFSET                      0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0C_BW_EMEM_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0C_BW_EMEM_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0C_BW_EMEM_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0C_BW_EMEM_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0C_BW_EMEM_INIT_ENUM                    DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0C_BW_EMEM_DISABLE                      _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0C_BW_EMEM_ENABLE                       _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0C_BW_EMEM_DISABLED                     _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0C_BW_EMEM_ENABLED                      _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0CB_BW_EMEM_SHIFT                       _MK_SHIFT_CONST(5)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0CB_BW_EMEM_FIELD                       (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0CB_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0CB_BW_EMEM_RANGE                       5:5
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0CB_BW_EMEM_WOFFSET                     0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0CB_BW_EMEM_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0CB_BW_EMEM_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0CB_BW_EMEM_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0CB_BW_EMEM_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0CB_BW_EMEM_INIT_ENUM                   DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0CB_BW_EMEM_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0CB_BW_EMEM_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0CB_BW_EMEM_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0CB_BW_EMEM_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY1B_BW_EMEM_SHIFT                        _MK_SHIFT_CONST(6)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY1B_BW_EMEM_FIELD                        (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY1B_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY1B_BW_EMEM_RANGE                        6:6
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY1B_BW_EMEM_WOFFSET                      0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY1B_BW_EMEM_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY1B_BW_EMEM_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY1B_BW_EMEM_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY1B_BW_EMEM_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY1B_BW_EMEM_INIT_ENUM                    DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY1B_BW_EMEM_DISABLE                      _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY1B_BW_EMEM_ENABLE                       _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY1B_BW_EMEM_DISABLED                     _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY1B_BW_EMEM_ENABLED                      _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY1BB_BW_EMEM_SHIFT                       _MK_SHIFT_CONST(7)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY1BB_BW_EMEM_FIELD                       (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY1BB_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY1BB_BW_EMEM_RANGE                       7:7
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY1BB_BW_EMEM_WOFFSET                     0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY1BB_BW_EMEM_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY1BB_BW_EMEM_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY1BB_BW_EMEM_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY1BB_BW_EMEM_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY1BB_BW_EMEM_INIT_ENUM                   DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY1BB_BW_EMEM_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY1BB_BW_EMEM_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY1BB_BW_EMEM_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY1BB_BW_EMEM_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_EPPUP_BW_EMEM_SHIFT                    _MK_SHIFT_CONST(8)
+#define MC_BWSHARE_EMEM_CTRL_0_0_EPPUP_BW_EMEM_FIELD                    (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_EPPUP_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_EPPUP_BW_EMEM_RANGE                    8:8
+#define MC_BWSHARE_EMEM_CTRL_0_0_EPPUP_BW_EMEM_WOFFSET                  0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_EPPUP_BW_EMEM_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_EPPUP_BW_EMEM_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_EPPUP_BW_EMEM_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_EPPUP_BW_EMEM_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_EPPUP_BW_EMEM_INIT_ENUM                        DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_EPPUP_BW_EMEM_DISABLE                  _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_EPPUP_BW_EMEM_ENABLE                   _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_EPPUP_BW_EMEM_DISABLED                 _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_EPPUP_BW_EMEM_ENABLED                  _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2PR_BW_EMEM_SHIFT                     _MK_SHIFT_CONST(9)
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2PR_BW_EMEM_FIELD                     (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_G2PR_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2PR_BW_EMEM_RANGE                     9:9
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2PR_BW_EMEM_WOFFSET                   0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2PR_BW_EMEM_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2PR_BW_EMEM_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2PR_BW_EMEM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2PR_BW_EMEM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2PR_BW_EMEM_INIT_ENUM                 DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2PR_BW_EMEM_DISABLE                   _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2PR_BW_EMEM_ENABLE                    _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2PR_BW_EMEM_DISABLED                  _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2PR_BW_EMEM_ENABLED                   _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2SR_BW_EMEM_SHIFT                     _MK_SHIFT_CONST(10)
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2SR_BW_EMEM_FIELD                     (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_G2SR_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2SR_BW_EMEM_RANGE                     10:10
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2SR_BW_EMEM_WOFFSET                   0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2SR_BW_EMEM_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2SR_BW_EMEM_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2SR_BW_EMEM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2SR_BW_EMEM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2SR_BW_EMEM_INIT_ENUM                 DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2SR_BW_EMEM_DISABLE                   _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2SR_BW_EMEM_ENABLE                    _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2SR_BW_EMEM_DISABLED                  _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2SR_BW_EMEM_ENABLED                   _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPEUNIFBR_BW_EMEM_SHIFT                        _MK_SHIFT_CONST(11)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPEUNIFBR_BW_EMEM_FIELD                        (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_MPEUNIFBR_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPEUNIFBR_BW_EMEM_RANGE                        11:11
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPEUNIFBR_BW_EMEM_WOFFSET                      0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPEUNIFBR_BW_EMEM_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPEUNIFBR_BW_EMEM_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPEUNIFBR_BW_EMEM_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPEUNIFBR_BW_EMEM_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPEUNIFBR_BW_EMEM_INIT_ENUM                    DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPEUNIFBR_BW_EMEM_DISABLE                      _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPEUNIFBR_BW_EMEM_ENABLE                       _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPEUNIFBR_BW_EMEM_DISABLED                     _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPEUNIFBR_BW_EMEM_ENABLED                      _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_VIRUV_BW_EMEM_SHIFT                    _MK_SHIFT_CONST(12)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VIRUV_BW_EMEM_FIELD                    (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_VIRUV_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VIRUV_BW_EMEM_RANGE                    12:12
+#define MC_BWSHARE_EMEM_CTRL_0_0_VIRUV_BW_EMEM_WOFFSET                  0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_VIRUV_BW_EMEM_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VIRUV_BW_EMEM_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VIRUV_BW_EMEM_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VIRUV_BW_EMEM_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VIRUV_BW_EMEM_INIT_ENUM                        DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_VIRUV_BW_EMEM_DISABLE                  _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VIRUV_BW_EMEM_ENABLE                   _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VIRUV_BW_EMEM_DISABLED                 _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VIRUV_BW_EMEM_ENABLED                  _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_AVPCARM7R_BW_EMEM_SHIFT                        _MK_SHIFT_CONST(13)
+#define MC_BWSHARE_EMEM_CTRL_0_0_AVPCARM7R_BW_EMEM_FIELD                        (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_AVPCARM7R_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_AVPCARM7R_BW_EMEM_RANGE                        13:13
+#define MC_BWSHARE_EMEM_CTRL_0_0_AVPCARM7R_BW_EMEM_WOFFSET                      0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_AVPCARM7R_BW_EMEM_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_AVPCARM7R_BW_EMEM_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_AVPCARM7R_BW_EMEM_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_AVPCARM7R_BW_EMEM_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_AVPCARM7R_BW_EMEM_INIT_ENUM                    DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_AVPCARM7R_BW_EMEM_DISABLE                      _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_AVPCARM7R_BW_EMEM_ENABLE                       _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_AVPCARM7R_BW_EMEM_DISABLED                     _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_AVPCARM7R_BW_EMEM_ENABLED                      _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAYHC_BW_EMEM_SHIFT                        _MK_SHIFT_CONST(14)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAYHC_BW_EMEM_FIELD                        (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_DISPLAYHC_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAYHC_BW_EMEM_RANGE                        14:14
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAYHC_BW_EMEM_WOFFSET                      0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAYHC_BW_EMEM_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAYHC_BW_EMEM_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAYHC_BW_EMEM_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAYHC_BW_EMEM_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAYHC_BW_EMEM_INIT_ENUM                    DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAYHC_BW_EMEM_DISABLE                      _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAYHC_BW_EMEM_ENABLE                       _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAYHC_BW_EMEM_DISABLED                     _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAYHC_BW_EMEM_ENABLED                      _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAYHCB_BW_EMEM_SHIFT                       _MK_SHIFT_CONST(15)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAYHCB_BW_EMEM_FIELD                       (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_DISPLAYHCB_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAYHCB_BW_EMEM_RANGE                       15:15
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAYHCB_BW_EMEM_WOFFSET                     0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAYHCB_BW_EMEM_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAYHCB_BW_EMEM_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAYHCB_BW_EMEM_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAYHCB_BW_EMEM_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAYHCB_BW_EMEM_INIT_ENUM                   DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAYHCB_BW_EMEM_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAYHCB_BW_EMEM_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAYHCB_BW_EMEM_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAYHCB_BW_EMEM_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_FDCDRD_BW_EMEM_SHIFT                   _MK_SHIFT_CONST(16)
+#define MC_BWSHARE_EMEM_CTRL_0_0_FDCDRD_BW_EMEM_FIELD                   (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_FDCDRD_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_FDCDRD_BW_EMEM_RANGE                   16:16
+#define MC_BWSHARE_EMEM_CTRL_0_0_FDCDRD_BW_EMEM_WOFFSET                 0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_FDCDRD_BW_EMEM_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_FDCDRD_BW_EMEM_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_FDCDRD_BW_EMEM_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_FDCDRD_BW_EMEM_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_FDCDRD_BW_EMEM_INIT_ENUM                       DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_FDCDRD_BW_EMEM_DISABLE                 _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_FDCDRD_BW_EMEM_ENABLE                  _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_FDCDRD_BW_EMEM_DISABLED                        _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_FDCDRD_BW_EMEM_ENABLED                 _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2DR_BW_EMEM_SHIFT                     _MK_SHIFT_CONST(17)
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2DR_BW_EMEM_FIELD                     (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_G2DR_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2DR_BW_EMEM_RANGE                     17:17
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2DR_BW_EMEM_WOFFSET                   0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2DR_BW_EMEM_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2DR_BW_EMEM_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2DR_BW_EMEM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2DR_BW_EMEM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2DR_BW_EMEM_INIT_ENUM                 DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2DR_BW_EMEM_DISABLE                   _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2DR_BW_EMEM_ENABLE                    _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2DR_BW_EMEM_DISABLED                  _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2DR_BW_EMEM_ENABLED                   _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_HOST1XDMAR_BW_EMEM_SHIFT                       _MK_SHIFT_CONST(18)
+#define MC_BWSHARE_EMEM_CTRL_0_0_HOST1XDMAR_BW_EMEM_FIELD                       (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_HOST1XDMAR_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_HOST1XDMAR_BW_EMEM_RANGE                       18:18
+#define MC_BWSHARE_EMEM_CTRL_0_0_HOST1XDMAR_BW_EMEM_WOFFSET                     0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_HOST1XDMAR_BW_EMEM_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_HOST1XDMAR_BW_EMEM_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_HOST1XDMAR_BW_EMEM_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_HOST1XDMAR_BW_EMEM_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_HOST1XDMAR_BW_EMEM_INIT_ENUM                   DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_HOST1XDMAR_BW_EMEM_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_HOST1XDMAR_BW_EMEM_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_HOST1XDMAR_BW_EMEM_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_HOST1XDMAR_BW_EMEM_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_HOST1XR_BW_EMEM_SHIFT                  _MK_SHIFT_CONST(19)
+#define MC_BWSHARE_EMEM_CTRL_0_0_HOST1XR_BW_EMEM_FIELD                  (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_HOST1XR_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_HOST1XR_BW_EMEM_RANGE                  19:19
+#define MC_BWSHARE_EMEM_CTRL_0_0_HOST1XR_BW_EMEM_WOFFSET                        0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_HOST1XR_BW_EMEM_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_HOST1XR_BW_EMEM_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_HOST1XR_BW_EMEM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_HOST1XR_BW_EMEM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_HOST1XR_BW_EMEM_INIT_ENUM                      DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_HOST1XR_BW_EMEM_DISABLE                        _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_HOST1XR_BW_EMEM_ENABLE                 _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_HOST1XR_BW_EMEM_DISABLED                       _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_HOST1XR_BW_EMEM_ENABLED                        _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_IDXSRD_BW_EMEM_SHIFT                   _MK_SHIFT_CONST(20)
+#define MC_BWSHARE_EMEM_CTRL_0_0_IDXSRD_BW_EMEM_FIELD                   (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_IDXSRD_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_IDXSRD_BW_EMEM_RANGE                   20:20
+#define MC_BWSHARE_EMEM_CTRL_0_0_IDXSRD_BW_EMEM_WOFFSET                 0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_IDXSRD_BW_EMEM_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_IDXSRD_BW_EMEM_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_IDXSRD_BW_EMEM_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_IDXSRD_BW_EMEM_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_IDXSRD_BW_EMEM_INIT_ENUM                       DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_IDXSRD_BW_EMEM_DISABLE                 _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_IDXSRD_BW_EMEM_ENABLE                  _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_IDXSRD_BW_EMEM_DISABLED                        _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_IDXSRD_BW_EMEM_ENABLED                 _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPCORER_BW_EMEM_SHIFT                  _MK_SHIFT_CONST(21)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPCORER_BW_EMEM_FIELD                  (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_MPCORER_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPCORER_BW_EMEM_RANGE                  21:21
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPCORER_BW_EMEM_WOFFSET                        0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPCORER_BW_EMEM_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPCORER_BW_EMEM_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPCORER_BW_EMEM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPCORER_BW_EMEM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPCORER_BW_EMEM_INIT_ENUM                      DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPCORER_BW_EMEM_DISABLE                        _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPCORER_BW_EMEM_ENABLE                 _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPCORER_BW_EMEM_DISABLED                       _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPCORER_BW_EMEM_ENABLED                        _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPE_IPRED_BW_EMEM_SHIFT                        _MK_SHIFT_CONST(22)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPE_IPRED_BW_EMEM_FIELD                        (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_MPE_IPRED_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPE_IPRED_BW_EMEM_RANGE                        22:22
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPE_IPRED_BW_EMEM_WOFFSET                      0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPE_IPRED_BW_EMEM_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPE_IPRED_BW_EMEM_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPE_IPRED_BW_EMEM_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPE_IPRED_BW_EMEM_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPE_IPRED_BW_EMEM_INIT_ENUM                    DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPE_IPRED_BW_EMEM_DISABLE                      _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPE_IPRED_BW_EMEM_ENABLE                       _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPE_IPRED_BW_EMEM_DISABLED                     _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPE_IPRED_BW_EMEM_ENABLED                      _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPEAMEMRD_BW_EMEM_SHIFT                        _MK_SHIFT_CONST(23)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPEAMEMRD_BW_EMEM_FIELD                        (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_MPEAMEMRD_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPEAMEMRD_BW_EMEM_RANGE                        23:23
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPEAMEMRD_BW_EMEM_WOFFSET                      0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPEAMEMRD_BW_EMEM_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPEAMEMRD_BW_EMEM_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPEAMEMRD_BW_EMEM_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPEAMEMRD_BW_EMEM_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPEAMEMRD_BW_EMEM_INIT_ENUM                    DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPEAMEMRD_BW_EMEM_DISABLE                      _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPEAMEMRD_BW_EMEM_ENABLE                       _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPEAMEMRD_BW_EMEM_DISABLED                     _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPEAMEMRD_BW_EMEM_ENABLED                      _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPECSRD_BW_EMEM_SHIFT                  _MK_SHIFT_CONST(24)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPECSRD_BW_EMEM_FIELD                  (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_MPECSRD_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPECSRD_BW_EMEM_RANGE                  24:24
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPECSRD_BW_EMEM_WOFFSET                        0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPECSRD_BW_EMEM_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPECSRD_BW_EMEM_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPECSRD_BW_EMEM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPECSRD_BW_EMEM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPECSRD_BW_EMEM_INIT_ENUM                      DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPECSRD_BW_EMEM_DISABLE                        _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPECSRD_BW_EMEM_ENABLE                 _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPECSRD_BW_EMEM_DISABLED                       _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPECSRD_BW_EMEM_ENABLED                        _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSAHBDMAR_BW_EMEM_SHIFT                      _MK_SHIFT_CONST(25)
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSAHBDMAR_BW_EMEM_FIELD                      (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_PPCSAHBDMAR_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSAHBDMAR_BW_EMEM_RANGE                      25:25
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSAHBDMAR_BW_EMEM_WOFFSET                    0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSAHBDMAR_BW_EMEM_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSAHBDMAR_BW_EMEM_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSAHBDMAR_BW_EMEM_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSAHBDMAR_BW_EMEM_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSAHBDMAR_BW_EMEM_INIT_ENUM                  DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSAHBDMAR_BW_EMEM_DISABLE                    _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSAHBDMAR_BW_EMEM_ENABLE                     _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSAHBDMAR_BW_EMEM_DISABLED                   _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSAHBDMAR_BW_EMEM_ENABLED                    _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSAHBSLVR_BW_EMEM_SHIFT                      _MK_SHIFT_CONST(26)
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSAHBSLVR_BW_EMEM_FIELD                      (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_PPCSAHBSLVR_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSAHBSLVR_BW_EMEM_RANGE                      26:26
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSAHBSLVR_BW_EMEM_WOFFSET                    0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSAHBSLVR_BW_EMEM_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSAHBSLVR_BW_EMEM_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSAHBSLVR_BW_EMEM_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSAHBSLVR_BW_EMEM_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSAHBSLVR_BW_EMEM_INIT_ENUM                  DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSAHBSLVR_BW_EMEM_DISABLE                    _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSAHBSLVR_BW_EMEM_ENABLE                     _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSAHBSLVR_BW_EMEM_DISABLED                   _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSAHBSLVR_BW_EMEM_ENABLED                    _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_TEXSRD_BW_EMEM_SHIFT                   _MK_SHIFT_CONST(27)
+#define MC_BWSHARE_EMEM_CTRL_0_0_TEXSRD_BW_EMEM_FIELD                   (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_TEXSRD_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_TEXSRD_BW_EMEM_RANGE                   27:27
+#define MC_BWSHARE_EMEM_CTRL_0_0_TEXSRD_BW_EMEM_WOFFSET                 0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_TEXSRD_BW_EMEM_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_TEXSRD_BW_EMEM_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_TEXSRD_BW_EMEM_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_TEXSRD_BW_EMEM_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_TEXSRD_BW_EMEM_INIT_ENUM                       DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_TEXSRD_BW_EMEM_DISABLE                 _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_TEXSRD_BW_EMEM_ENABLE                  _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_TEXSRD_BW_EMEM_DISABLED                        _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_TEXSRD_BW_EMEM_ENABLED                 _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEBSEVR_BW_EMEM_SHIFT                 _MK_SHIFT_CONST(28)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEBSEVR_BW_EMEM_FIELD                 (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_VDEBSEVR_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEBSEVR_BW_EMEM_RANGE                 28:28
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEBSEVR_BW_EMEM_WOFFSET                       0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEBSEVR_BW_EMEM_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEBSEVR_BW_EMEM_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEBSEVR_BW_EMEM_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEBSEVR_BW_EMEM_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEBSEVR_BW_EMEM_INIT_ENUM                     DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEBSEVR_BW_EMEM_DISABLE                       _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEBSEVR_BW_EMEM_ENABLE                        _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEBSEVR_BW_EMEM_DISABLED                      _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEBSEVR_BW_EMEM_ENABLED                       _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEMBER_BW_EMEM_SHIFT                  _MK_SHIFT_CONST(29)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEMBER_BW_EMEM_FIELD                  (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_VDEMBER_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEMBER_BW_EMEM_RANGE                  29:29
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEMBER_BW_EMEM_WOFFSET                        0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEMBER_BW_EMEM_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEMBER_BW_EMEM_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEMBER_BW_EMEM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEMBER_BW_EMEM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEMBER_BW_EMEM_INIT_ENUM                      DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEMBER_BW_EMEM_DISABLE                        _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEMBER_BW_EMEM_ENABLE                 _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEMBER_BW_EMEM_DISABLED                       _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEMBER_BW_EMEM_ENABLED                        _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEMCER_BW_EMEM_SHIFT                  _MK_SHIFT_CONST(30)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEMCER_BW_EMEM_FIELD                  (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_VDEMCER_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEMCER_BW_EMEM_RANGE                  30:30
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEMCER_BW_EMEM_WOFFSET                        0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEMCER_BW_EMEM_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEMCER_BW_EMEM_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEMCER_BW_EMEM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEMCER_BW_EMEM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEMCER_BW_EMEM_INIT_ENUM                      DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEMCER_BW_EMEM_DISABLE                        _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEMCER_BW_EMEM_ENABLE                 _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEMCER_BW_EMEM_DISABLED                       _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEMCER_BW_EMEM_ENABLED                        _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDETPER_BW_EMEM_SHIFT                  _MK_SHIFT_CONST(31)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDETPER_BW_EMEM_FIELD                  (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_VDETPER_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDETPER_BW_EMEM_RANGE                  31:31
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDETPER_BW_EMEM_WOFFSET                        0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDETPER_BW_EMEM_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDETPER_BW_EMEM_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDETPER_BW_EMEM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDETPER_BW_EMEM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDETPER_BW_EMEM_INIT_ENUM                      DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDETPER_BW_EMEM_DISABLE                        _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDETPER_BW_EMEM_ENABLE                 _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDETPER_BW_EMEM_DISABLED                       _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDETPER_BW_EMEM_ENABLED                        _MK_ENUM_CONST(1)
+
+
+// Register MC_BWSHARE_EMEM_CTRL_1_0  
+#define MC_BWSHARE_EMEM_CTRL_1_0                        _MK_ADDR_CONST(0x124)
+#define MC_BWSHARE_EMEM_CTRL_1_0_SECURE                         0x0
+#define MC_BWSHARE_EMEM_CTRL_1_0_WORD_COUNT                     0x1
+#define MC_BWSHARE_EMEM_CTRL_1_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_RESET_MASK                     _MK_MASK_CONST(0xfffff)
+#define MC_BWSHARE_EMEM_CTRL_1_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_READ_MASK                      _MK_MASK_CONST(0xfffff)
+#define MC_BWSHARE_EMEM_CTRL_1_0_WRITE_MASK                     _MK_MASK_CONST(0xfffff)
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPU_BW_EMEM_SHIFT                     _MK_SHIFT_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPU_BW_EMEM_FIELD                     (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_1_0_EPPU_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPU_BW_EMEM_RANGE                     0:0
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPU_BW_EMEM_WOFFSET                   0x0
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPU_BW_EMEM_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPU_BW_EMEM_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPU_BW_EMEM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPU_BW_EMEM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPU_BW_EMEM_INIT_ENUM                 DISABLE
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPU_BW_EMEM_DISABLE                   _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPU_BW_EMEM_ENABLE                    _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPU_BW_EMEM_DISABLED                  _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPU_BW_EMEM_ENABLED                   _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPV_BW_EMEM_SHIFT                     _MK_SHIFT_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPV_BW_EMEM_FIELD                     (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_1_0_EPPV_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPV_BW_EMEM_RANGE                     1:1
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPV_BW_EMEM_WOFFSET                   0x0
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPV_BW_EMEM_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPV_BW_EMEM_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPV_BW_EMEM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPV_BW_EMEM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPV_BW_EMEM_INIT_ENUM                 DISABLE
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPV_BW_EMEM_DISABLE                   _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPV_BW_EMEM_ENABLE                    _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPV_BW_EMEM_DISABLED                  _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPV_BW_EMEM_ENABLED                   _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPY_BW_EMEM_SHIFT                     _MK_SHIFT_CONST(2)
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPY_BW_EMEM_FIELD                     (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_1_0_EPPY_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPY_BW_EMEM_RANGE                     2:2
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPY_BW_EMEM_WOFFSET                   0x0
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPY_BW_EMEM_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPY_BW_EMEM_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPY_BW_EMEM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPY_BW_EMEM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPY_BW_EMEM_INIT_ENUM                 DISABLE
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPY_BW_EMEM_DISABLE                   _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPY_BW_EMEM_ENABLE                    _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPY_BW_EMEM_DISABLED                  _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPY_BW_EMEM_ENABLED                   _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPEUNIFBW_BW_EMEM_SHIFT                        _MK_SHIFT_CONST(3)
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPEUNIFBW_BW_EMEM_FIELD                        (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_1_0_MPEUNIFBW_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPEUNIFBW_BW_EMEM_RANGE                        3:3
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPEUNIFBW_BW_EMEM_WOFFSET                      0x0
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPEUNIFBW_BW_EMEM_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPEUNIFBW_BW_EMEM_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPEUNIFBW_BW_EMEM_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPEUNIFBW_BW_EMEM_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPEUNIFBW_BW_EMEM_INIT_ENUM                    DISABLE
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPEUNIFBW_BW_EMEM_DISABLE                      _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPEUNIFBW_BW_EMEM_ENABLE                       _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPEUNIFBW_BW_EMEM_DISABLED                     _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPEUNIFBW_BW_EMEM_ENABLED                      _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWSB_BW_EMEM_SHIFT                    _MK_SHIFT_CONST(4)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWSB_BW_EMEM_FIELD                    (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_1_0_VIWSB_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWSB_BW_EMEM_RANGE                    4:4
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWSB_BW_EMEM_WOFFSET                  0x0
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWSB_BW_EMEM_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWSB_BW_EMEM_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWSB_BW_EMEM_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWSB_BW_EMEM_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWSB_BW_EMEM_INIT_ENUM                        DISABLE
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWSB_BW_EMEM_DISABLE                  _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWSB_BW_EMEM_ENABLE                   _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWSB_BW_EMEM_DISABLED                 _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWSB_BW_EMEM_ENABLED                  _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWU_BW_EMEM_SHIFT                     _MK_SHIFT_CONST(5)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWU_BW_EMEM_FIELD                     (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_1_0_VIWU_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWU_BW_EMEM_RANGE                     5:5
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWU_BW_EMEM_WOFFSET                   0x0
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWU_BW_EMEM_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWU_BW_EMEM_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWU_BW_EMEM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWU_BW_EMEM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWU_BW_EMEM_INIT_ENUM                 DISABLE
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWU_BW_EMEM_DISABLE                   _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWU_BW_EMEM_ENABLE                    _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWU_BW_EMEM_DISABLED                  _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWU_BW_EMEM_ENABLED                   _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWV_BW_EMEM_SHIFT                     _MK_SHIFT_CONST(6)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWV_BW_EMEM_FIELD                     (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_1_0_VIWV_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWV_BW_EMEM_RANGE                     6:6
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWV_BW_EMEM_WOFFSET                   0x0
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWV_BW_EMEM_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWV_BW_EMEM_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWV_BW_EMEM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWV_BW_EMEM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWV_BW_EMEM_INIT_ENUM                 DISABLE
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWV_BW_EMEM_DISABLE                   _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWV_BW_EMEM_ENABLE                    _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWV_BW_EMEM_DISABLED                  _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWV_BW_EMEM_ENABLED                   _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWY_BW_EMEM_SHIFT                     _MK_SHIFT_CONST(7)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWY_BW_EMEM_FIELD                     (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_1_0_VIWY_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWY_BW_EMEM_RANGE                     7:7
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWY_BW_EMEM_WOFFSET                   0x0
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWY_BW_EMEM_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWY_BW_EMEM_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWY_BW_EMEM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWY_BW_EMEM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWY_BW_EMEM_INIT_ENUM                 DISABLE
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWY_BW_EMEM_DISABLE                   _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWY_BW_EMEM_ENABLE                    _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWY_BW_EMEM_DISABLED                  _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWY_BW_EMEM_ENABLED                   _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_1_0_G2DW_BW_EMEM_SHIFT                     _MK_SHIFT_CONST(8)
+#define MC_BWSHARE_EMEM_CTRL_1_0_G2DW_BW_EMEM_FIELD                     (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_1_0_G2DW_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_1_0_G2DW_BW_EMEM_RANGE                     8:8
+#define MC_BWSHARE_EMEM_CTRL_1_0_G2DW_BW_EMEM_WOFFSET                   0x0
+#define MC_BWSHARE_EMEM_CTRL_1_0_G2DW_BW_EMEM_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_G2DW_BW_EMEM_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_G2DW_BW_EMEM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_G2DW_BW_EMEM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_G2DW_BW_EMEM_INIT_ENUM                 DISABLE
+#define MC_BWSHARE_EMEM_CTRL_1_0_G2DW_BW_EMEM_DISABLE                   _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_G2DW_BW_EMEM_ENABLE                    _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_G2DW_BW_EMEM_DISABLED                  _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_G2DW_BW_EMEM_ENABLED                   _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_1_0_AVPCARM7W_BW_EMEM_SHIFT                        _MK_SHIFT_CONST(9)
+#define MC_BWSHARE_EMEM_CTRL_1_0_AVPCARM7W_BW_EMEM_FIELD                        (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_1_0_AVPCARM7W_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_1_0_AVPCARM7W_BW_EMEM_RANGE                        9:9
+#define MC_BWSHARE_EMEM_CTRL_1_0_AVPCARM7W_BW_EMEM_WOFFSET                      0x0
+#define MC_BWSHARE_EMEM_CTRL_1_0_AVPCARM7W_BW_EMEM_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_AVPCARM7W_BW_EMEM_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_AVPCARM7W_BW_EMEM_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_AVPCARM7W_BW_EMEM_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_AVPCARM7W_BW_EMEM_INIT_ENUM                    DISABLE
+#define MC_BWSHARE_EMEM_CTRL_1_0_AVPCARM7W_BW_EMEM_DISABLE                      _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_AVPCARM7W_BW_EMEM_ENABLE                       _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_AVPCARM7W_BW_EMEM_DISABLED                     _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_AVPCARM7W_BW_EMEM_ENABLED                      _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_1_0_FDCDWR_BW_EMEM_SHIFT                   _MK_SHIFT_CONST(10)
+#define MC_BWSHARE_EMEM_CTRL_1_0_FDCDWR_BW_EMEM_FIELD                   (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_1_0_FDCDWR_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_1_0_FDCDWR_BW_EMEM_RANGE                   10:10
+#define MC_BWSHARE_EMEM_CTRL_1_0_FDCDWR_BW_EMEM_WOFFSET                 0x0
+#define MC_BWSHARE_EMEM_CTRL_1_0_FDCDWR_BW_EMEM_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_FDCDWR_BW_EMEM_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_FDCDWR_BW_EMEM_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_FDCDWR_BW_EMEM_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_FDCDWR_BW_EMEM_INIT_ENUM                       DISABLE
+#define MC_BWSHARE_EMEM_CTRL_1_0_FDCDWR_BW_EMEM_DISABLE                 _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_FDCDWR_BW_EMEM_ENABLE                  _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_FDCDWR_BW_EMEM_DISABLED                        _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_FDCDWR_BW_EMEM_ENABLED                 _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_1_0_HOST1XW_BW_EMEM_SHIFT                  _MK_SHIFT_CONST(11)
+#define MC_BWSHARE_EMEM_CTRL_1_0_HOST1XW_BW_EMEM_FIELD                  (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_1_0_HOST1XW_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_1_0_HOST1XW_BW_EMEM_RANGE                  11:11
+#define MC_BWSHARE_EMEM_CTRL_1_0_HOST1XW_BW_EMEM_WOFFSET                        0x0
+#define MC_BWSHARE_EMEM_CTRL_1_0_HOST1XW_BW_EMEM_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_HOST1XW_BW_EMEM_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_HOST1XW_BW_EMEM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_HOST1XW_BW_EMEM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_HOST1XW_BW_EMEM_INIT_ENUM                      DISABLE
+#define MC_BWSHARE_EMEM_CTRL_1_0_HOST1XW_BW_EMEM_DISABLE                        _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_HOST1XW_BW_EMEM_ENABLE                 _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_HOST1XW_BW_EMEM_DISABLED                       _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_HOST1XW_BW_EMEM_ENABLED                        _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_1_0_ISPW_BW_EMEM_SHIFT                     _MK_SHIFT_CONST(12)
+#define MC_BWSHARE_EMEM_CTRL_1_0_ISPW_BW_EMEM_FIELD                     (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_1_0_ISPW_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_1_0_ISPW_BW_EMEM_RANGE                     12:12
+#define MC_BWSHARE_EMEM_CTRL_1_0_ISPW_BW_EMEM_WOFFSET                   0x0
+#define MC_BWSHARE_EMEM_CTRL_1_0_ISPW_BW_EMEM_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_ISPW_BW_EMEM_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_ISPW_BW_EMEM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_ISPW_BW_EMEM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_ISPW_BW_EMEM_INIT_ENUM                 DISABLE
+#define MC_BWSHARE_EMEM_CTRL_1_0_ISPW_BW_EMEM_DISABLE                   _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_ISPW_BW_EMEM_ENABLE                    _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_ISPW_BW_EMEM_DISABLED                  _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_ISPW_BW_EMEM_ENABLED                   _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPCOREW_BW_EMEM_SHIFT                  _MK_SHIFT_CONST(13)
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPCOREW_BW_EMEM_FIELD                  (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_1_0_MPCOREW_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPCOREW_BW_EMEM_RANGE                  13:13
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPCOREW_BW_EMEM_WOFFSET                        0x0
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPCOREW_BW_EMEM_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPCOREW_BW_EMEM_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPCOREW_BW_EMEM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPCOREW_BW_EMEM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPCOREW_BW_EMEM_INIT_ENUM                      DISABLE
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPCOREW_BW_EMEM_DISABLE                        _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPCOREW_BW_EMEM_ENABLE                 _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPCOREW_BW_EMEM_DISABLED                       _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPCOREW_BW_EMEM_ENABLED                        _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPECSWR_BW_EMEM_SHIFT                  _MK_SHIFT_CONST(14)
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPECSWR_BW_EMEM_FIELD                  (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_1_0_MPECSWR_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPECSWR_BW_EMEM_RANGE                  14:14
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPECSWR_BW_EMEM_WOFFSET                        0x0
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPECSWR_BW_EMEM_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPECSWR_BW_EMEM_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPECSWR_BW_EMEM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPECSWR_BW_EMEM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPECSWR_BW_EMEM_INIT_ENUM                      DISABLE
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPECSWR_BW_EMEM_DISABLE                        _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPECSWR_BW_EMEM_ENABLE                 _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPECSWR_BW_EMEM_DISABLED                       _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPECSWR_BW_EMEM_ENABLED                        _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSAHBDMAW_BW_EMEM_SHIFT                      _MK_SHIFT_CONST(15)
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSAHBDMAW_BW_EMEM_FIELD                      (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_1_0_PPCSAHBDMAW_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSAHBDMAW_BW_EMEM_RANGE                      15:15
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSAHBDMAW_BW_EMEM_WOFFSET                    0x0
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSAHBDMAW_BW_EMEM_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSAHBDMAW_BW_EMEM_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSAHBDMAW_BW_EMEM_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSAHBDMAW_BW_EMEM_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSAHBDMAW_BW_EMEM_INIT_ENUM                  DISABLE
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSAHBDMAW_BW_EMEM_DISABLE                    _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSAHBDMAW_BW_EMEM_ENABLE                     _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSAHBDMAW_BW_EMEM_DISABLED                   _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSAHBDMAW_BW_EMEM_ENABLED                    _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSAHBSLVW_BW_EMEM_SHIFT                      _MK_SHIFT_CONST(16)
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSAHBSLVW_BW_EMEM_FIELD                      (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_1_0_PPCSAHBSLVW_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSAHBSLVW_BW_EMEM_RANGE                      16:16
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSAHBSLVW_BW_EMEM_WOFFSET                    0x0
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSAHBSLVW_BW_EMEM_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSAHBSLVW_BW_EMEM_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSAHBSLVW_BW_EMEM_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSAHBSLVW_BW_EMEM_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSAHBSLVW_BW_EMEM_INIT_ENUM                  DISABLE
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSAHBSLVW_BW_EMEM_DISABLE                    _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSAHBSLVW_BW_EMEM_ENABLE                     _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSAHBSLVW_BW_EMEM_DISABLED                   _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSAHBSLVW_BW_EMEM_ENABLED                    _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEBSEVW_BW_EMEM_SHIFT                 _MK_SHIFT_CONST(17)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEBSEVW_BW_EMEM_FIELD                 (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_1_0_VDEBSEVW_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEBSEVW_BW_EMEM_RANGE                 17:17
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEBSEVW_BW_EMEM_WOFFSET                       0x0
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEBSEVW_BW_EMEM_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEBSEVW_BW_EMEM_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEBSEVW_BW_EMEM_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEBSEVW_BW_EMEM_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEBSEVW_BW_EMEM_INIT_ENUM                     DISABLE
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEBSEVW_BW_EMEM_DISABLE                       _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEBSEVW_BW_EMEM_ENABLE                        _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEBSEVW_BW_EMEM_DISABLED                      _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEBSEVW_BW_EMEM_ENABLED                       _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEMBEW_BW_EMEM_SHIFT                  _MK_SHIFT_CONST(18)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEMBEW_BW_EMEM_FIELD                  (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_1_0_VDEMBEW_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEMBEW_BW_EMEM_RANGE                  18:18
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEMBEW_BW_EMEM_WOFFSET                        0x0
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEMBEW_BW_EMEM_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEMBEW_BW_EMEM_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEMBEW_BW_EMEM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEMBEW_BW_EMEM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEMBEW_BW_EMEM_INIT_ENUM                      DISABLE
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEMBEW_BW_EMEM_DISABLE                        _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEMBEW_BW_EMEM_ENABLE                 _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEMBEW_BW_EMEM_DISABLED                       _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEMBEW_BW_EMEM_ENABLED                        _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDETPMW_BW_EMEM_SHIFT                  _MK_SHIFT_CONST(19)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDETPMW_BW_EMEM_FIELD                  (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_1_0_VDETPMW_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDETPMW_BW_EMEM_RANGE                  19:19
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDETPMW_BW_EMEM_WOFFSET                        0x0
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDETPMW_BW_EMEM_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDETPMW_BW_EMEM_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDETPMW_BW_EMEM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDETPMW_BW_EMEM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDETPMW_BW_EMEM_INIT_ENUM                      DISABLE
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDETPMW_BW_EMEM_DISABLE                        _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDETPMW_BW_EMEM_ENABLE                 _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDETPMW_BW_EMEM_DISABLED                       _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDETPMW_BW_EMEM_ENABLED                        _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_AP_CTRL_DISABLE       0
+#define MC_CLIENT_AP_CTRL_ENABLE        1
+
+// Register MC_AP_CTRL_0_0  
+#define MC_AP_CTRL_0_0                  _MK_ADDR_CONST(0x128)
+#define MC_AP_CTRL_0_0_SECURE                   0x0
+#define MC_AP_CTRL_0_0_WORD_COUNT                       0x1
+#define MC_AP_CTRL_0_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
+#define MC_AP_CTRL_0_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define MC_AP_CTRL_0_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+#define MC_AP_CTRL_0_0_DISPLAY0A_APVAL_SHIFT                    _MK_SHIFT_CONST(0)
+#define MC_AP_CTRL_0_0_DISPLAY0A_APVAL_FIELD                    (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_DISPLAY0A_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_DISPLAY0A_APVAL_RANGE                    0:0
+#define MC_AP_CTRL_0_0_DISPLAY0A_APVAL_WOFFSET                  0x0
+#define MC_AP_CTRL_0_0_DISPLAY0A_APVAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_DISPLAY0A_APVAL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_DISPLAY0A_APVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_DISPLAY0A_APVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_DISPLAY0A_APVAL_INIT_ENUM                        DISABLE
+#define MC_AP_CTRL_0_0_DISPLAY0A_APVAL_DISABLE                  _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_DISPLAY0A_APVAL_ENABLE                   _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_DISPLAY0A_APVAL_DISABLED                 _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_DISPLAY0A_APVAL_ENABLED                  _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_DISPLAY0AB_APVAL_SHIFT                   _MK_SHIFT_CONST(1)
+#define MC_AP_CTRL_0_0_DISPLAY0AB_APVAL_FIELD                   (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_DISPLAY0AB_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_DISPLAY0AB_APVAL_RANGE                   1:1
+#define MC_AP_CTRL_0_0_DISPLAY0AB_APVAL_WOFFSET                 0x0
+#define MC_AP_CTRL_0_0_DISPLAY0AB_APVAL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_DISPLAY0AB_APVAL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_DISPLAY0AB_APVAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_DISPLAY0AB_APVAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_DISPLAY0AB_APVAL_INIT_ENUM                       DISABLE
+#define MC_AP_CTRL_0_0_DISPLAY0AB_APVAL_DISABLE                 _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_DISPLAY0AB_APVAL_ENABLE                  _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_DISPLAY0AB_APVAL_DISABLED                        _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_DISPLAY0AB_APVAL_ENABLED                 _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_DISPLAY0B_APVAL_SHIFT                    _MK_SHIFT_CONST(2)
+#define MC_AP_CTRL_0_0_DISPLAY0B_APVAL_FIELD                    (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_DISPLAY0B_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_DISPLAY0B_APVAL_RANGE                    2:2
+#define MC_AP_CTRL_0_0_DISPLAY0B_APVAL_WOFFSET                  0x0
+#define MC_AP_CTRL_0_0_DISPLAY0B_APVAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_DISPLAY0B_APVAL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_DISPLAY0B_APVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_DISPLAY0B_APVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_DISPLAY0B_APVAL_INIT_ENUM                        DISABLE
+#define MC_AP_CTRL_0_0_DISPLAY0B_APVAL_DISABLE                  _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_DISPLAY0B_APVAL_ENABLE                   _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_DISPLAY0B_APVAL_DISABLED                 _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_DISPLAY0B_APVAL_ENABLED                  _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_DISPLAY0BB_APVAL_SHIFT                   _MK_SHIFT_CONST(3)
+#define MC_AP_CTRL_0_0_DISPLAY0BB_APVAL_FIELD                   (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_DISPLAY0BB_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_DISPLAY0BB_APVAL_RANGE                   3:3
+#define MC_AP_CTRL_0_0_DISPLAY0BB_APVAL_WOFFSET                 0x0
+#define MC_AP_CTRL_0_0_DISPLAY0BB_APVAL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_DISPLAY0BB_APVAL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_DISPLAY0BB_APVAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_DISPLAY0BB_APVAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_DISPLAY0BB_APVAL_INIT_ENUM                       DISABLE
+#define MC_AP_CTRL_0_0_DISPLAY0BB_APVAL_DISABLE                 _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_DISPLAY0BB_APVAL_ENABLE                  _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_DISPLAY0BB_APVAL_DISABLED                        _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_DISPLAY0BB_APVAL_ENABLED                 _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_DISPLAY0C_APVAL_SHIFT                    _MK_SHIFT_CONST(4)
+#define MC_AP_CTRL_0_0_DISPLAY0C_APVAL_FIELD                    (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_DISPLAY0C_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_DISPLAY0C_APVAL_RANGE                    4:4
+#define MC_AP_CTRL_0_0_DISPLAY0C_APVAL_WOFFSET                  0x0
+#define MC_AP_CTRL_0_0_DISPLAY0C_APVAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_DISPLAY0C_APVAL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_DISPLAY0C_APVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_DISPLAY0C_APVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_DISPLAY0C_APVAL_INIT_ENUM                        DISABLE
+#define MC_AP_CTRL_0_0_DISPLAY0C_APVAL_DISABLE                  _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_DISPLAY0C_APVAL_ENABLE                   _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_DISPLAY0C_APVAL_DISABLED                 _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_DISPLAY0C_APVAL_ENABLED                  _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_DISPLAY0CB_APVAL_SHIFT                   _MK_SHIFT_CONST(5)
+#define MC_AP_CTRL_0_0_DISPLAY0CB_APVAL_FIELD                   (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_DISPLAY0CB_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_DISPLAY0CB_APVAL_RANGE                   5:5
+#define MC_AP_CTRL_0_0_DISPLAY0CB_APVAL_WOFFSET                 0x0
+#define MC_AP_CTRL_0_0_DISPLAY0CB_APVAL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_DISPLAY0CB_APVAL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_DISPLAY0CB_APVAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_DISPLAY0CB_APVAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_DISPLAY0CB_APVAL_INIT_ENUM                       DISABLE
+#define MC_AP_CTRL_0_0_DISPLAY0CB_APVAL_DISABLE                 _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_DISPLAY0CB_APVAL_ENABLE                  _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_DISPLAY0CB_APVAL_DISABLED                        _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_DISPLAY0CB_APVAL_ENABLED                 _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_DISPLAY1B_APVAL_SHIFT                    _MK_SHIFT_CONST(6)
+#define MC_AP_CTRL_0_0_DISPLAY1B_APVAL_FIELD                    (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_DISPLAY1B_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_DISPLAY1B_APVAL_RANGE                    6:6
+#define MC_AP_CTRL_0_0_DISPLAY1B_APVAL_WOFFSET                  0x0
+#define MC_AP_CTRL_0_0_DISPLAY1B_APVAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_DISPLAY1B_APVAL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_DISPLAY1B_APVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_DISPLAY1B_APVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_DISPLAY1B_APVAL_INIT_ENUM                        DISABLE
+#define MC_AP_CTRL_0_0_DISPLAY1B_APVAL_DISABLE                  _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_DISPLAY1B_APVAL_ENABLE                   _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_DISPLAY1B_APVAL_DISABLED                 _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_DISPLAY1B_APVAL_ENABLED                  _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_DISPLAY1BB_APVAL_SHIFT                   _MK_SHIFT_CONST(7)
+#define MC_AP_CTRL_0_0_DISPLAY1BB_APVAL_FIELD                   (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_DISPLAY1BB_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_DISPLAY1BB_APVAL_RANGE                   7:7
+#define MC_AP_CTRL_0_0_DISPLAY1BB_APVAL_WOFFSET                 0x0
+#define MC_AP_CTRL_0_0_DISPLAY1BB_APVAL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_DISPLAY1BB_APVAL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_DISPLAY1BB_APVAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_DISPLAY1BB_APVAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_DISPLAY1BB_APVAL_INIT_ENUM                       DISABLE
+#define MC_AP_CTRL_0_0_DISPLAY1BB_APVAL_DISABLE                 _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_DISPLAY1BB_APVAL_ENABLE                  _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_DISPLAY1BB_APVAL_DISABLED                        _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_DISPLAY1BB_APVAL_ENABLED                 _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_EPPUP_APVAL_SHIFT                        _MK_SHIFT_CONST(8)
+#define MC_AP_CTRL_0_0_EPPUP_APVAL_FIELD                        (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_EPPUP_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_EPPUP_APVAL_RANGE                        8:8
+#define MC_AP_CTRL_0_0_EPPUP_APVAL_WOFFSET                      0x0
+#define MC_AP_CTRL_0_0_EPPUP_APVAL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_EPPUP_APVAL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_EPPUP_APVAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_EPPUP_APVAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_EPPUP_APVAL_INIT_ENUM                    DISABLE
+#define MC_AP_CTRL_0_0_EPPUP_APVAL_DISABLE                      _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_EPPUP_APVAL_ENABLE                       _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_EPPUP_APVAL_DISABLED                     _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_EPPUP_APVAL_ENABLED                      _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_G2PR_APVAL_SHIFT                 _MK_SHIFT_CONST(9)
+#define MC_AP_CTRL_0_0_G2PR_APVAL_FIELD                 (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_G2PR_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_G2PR_APVAL_RANGE                 9:9
+#define MC_AP_CTRL_0_0_G2PR_APVAL_WOFFSET                       0x0
+#define MC_AP_CTRL_0_0_G2PR_APVAL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_G2PR_APVAL_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_G2PR_APVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_G2PR_APVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_G2PR_APVAL_INIT_ENUM                     DISABLE
+#define MC_AP_CTRL_0_0_G2PR_APVAL_DISABLE                       _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_G2PR_APVAL_ENABLE                        _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_G2PR_APVAL_DISABLED                      _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_G2PR_APVAL_ENABLED                       _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_G2SR_APVAL_SHIFT                 _MK_SHIFT_CONST(10)
+#define MC_AP_CTRL_0_0_G2SR_APVAL_FIELD                 (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_G2SR_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_G2SR_APVAL_RANGE                 10:10
+#define MC_AP_CTRL_0_0_G2SR_APVAL_WOFFSET                       0x0
+#define MC_AP_CTRL_0_0_G2SR_APVAL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_G2SR_APVAL_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_G2SR_APVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_G2SR_APVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_G2SR_APVAL_INIT_ENUM                     DISABLE
+#define MC_AP_CTRL_0_0_G2SR_APVAL_DISABLE                       _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_G2SR_APVAL_ENABLE                        _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_G2SR_APVAL_DISABLED                      _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_G2SR_APVAL_ENABLED                       _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_MPEUNIFBR_APVAL_SHIFT                    _MK_SHIFT_CONST(11)
+#define MC_AP_CTRL_0_0_MPEUNIFBR_APVAL_FIELD                    (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_MPEUNIFBR_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_MPEUNIFBR_APVAL_RANGE                    11:11
+#define MC_AP_CTRL_0_0_MPEUNIFBR_APVAL_WOFFSET                  0x0
+#define MC_AP_CTRL_0_0_MPEUNIFBR_APVAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_MPEUNIFBR_APVAL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_MPEUNIFBR_APVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_MPEUNIFBR_APVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_MPEUNIFBR_APVAL_INIT_ENUM                        DISABLE
+#define MC_AP_CTRL_0_0_MPEUNIFBR_APVAL_DISABLE                  _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_MPEUNIFBR_APVAL_ENABLE                   _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_MPEUNIFBR_APVAL_DISABLED                 _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_MPEUNIFBR_APVAL_ENABLED                  _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_VIRUV_APVAL_SHIFT                        _MK_SHIFT_CONST(12)
+#define MC_AP_CTRL_0_0_VIRUV_APVAL_FIELD                        (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_VIRUV_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_VIRUV_APVAL_RANGE                        12:12
+#define MC_AP_CTRL_0_0_VIRUV_APVAL_WOFFSET                      0x0
+#define MC_AP_CTRL_0_0_VIRUV_APVAL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_VIRUV_APVAL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_VIRUV_APVAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_VIRUV_APVAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_VIRUV_APVAL_INIT_ENUM                    DISABLE
+#define MC_AP_CTRL_0_0_VIRUV_APVAL_DISABLE                      _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_VIRUV_APVAL_ENABLE                       _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_VIRUV_APVAL_DISABLED                     _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_VIRUV_APVAL_ENABLED                      _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_AVPCARM7R_APVAL_SHIFT                    _MK_SHIFT_CONST(13)
+#define MC_AP_CTRL_0_0_AVPCARM7R_APVAL_FIELD                    (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_AVPCARM7R_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_AVPCARM7R_APVAL_RANGE                    13:13
+#define MC_AP_CTRL_0_0_AVPCARM7R_APVAL_WOFFSET                  0x0
+#define MC_AP_CTRL_0_0_AVPCARM7R_APVAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_AVPCARM7R_APVAL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_AVPCARM7R_APVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_AVPCARM7R_APVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_AVPCARM7R_APVAL_INIT_ENUM                        DISABLE
+#define MC_AP_CTRL_0_0_AVPCARM7R_APVAL_DISABLE                  _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_AVPCARM7R_APVAL_ENABLE                   _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_AVPCARM7R_APVAL_DISABLED                 _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_AVPCARM7R_APVAL_ENABLED                  _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_DISPLAYHC_APVAL_SHIFT                    _MK_SHIFT_CONST(14)
+#define MC_AP_CTRL_0_0_DISPLAYHC_APVAL_FIELD                    (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_DISPLAYHC_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_DISPLAYHC_APVAL_RANGE                    14:14
+#define MC_AP_CTRL_0_0_DISPLAYHC_APVAL_WOFFSET                  0x0
+#define MC_AP_CTRL_0_0_DISPLAYHC_APVAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_DISPLAYHC_APVAL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_DISPLAYHC_APVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_DISPLAYHC_APVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_DISPLAYHC_APVAL_INIT_ENUM                        DISABLE
+#define MC_AP_CTRL_0_0_DISPLAYHC_APVAL_DISABLE                  _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_DISPLAYHC_APVAL_ENABLE                   _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_DISPLAYHC_APVAL_DISABLED                 _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_DISPLAYHC_APVAL_ENABLED                  _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_DISPLAYHCB_APVAL_SHIFT                   _MK_SHIFT_CONST(15)
+#define MC_AP_CTRL_0_0_DISPLAYHCB_APVAL_FIELD                   (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_DISPLAYHCB_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_DISPLAYHCB_APVAL_RANGE                   15:15
+#define MC_AP_CTRL_0_0_DISPLAYHCB_APVAL_WOFFSET                 0x0
+#define MC_AP_CTRL_0_0_DISPLAYHCB_APVAL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_DISPLAYHCB_APVAL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_DISPLAYHCB_APVAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_DISPLAYHCB_APVAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_DISPLAYHCB_APVAL_INIT_ENUM                       DISABLE
+#define MC_AP_CTRL_0_0_DISPLAYHCB_APVAL_DISABLE                 _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_DISPLAYHCB_APVAL_ENABLE                  _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_DISPLAYHCB_APVAL_DISABLED                        _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_DISPLAYHCB_APVAL_ENABLED                 _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_FDCDRD_APVAL_SHIFT                       _MK_SHIFT_CONST(16)
+#define MC_AP_CTRL_0_0_FDCDRD_APVAL_FIELD                       (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_FDCDRD_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_FDCDRD_APVAL_RANGE                       16:16
+#define MC_AP_CTRL_0_0_FDCDRD_APVAL_WOFFSET                     0x0
+#define MC_AP_CTRL_0_0_FDCDRD_APVAL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_FDCDRD_APVAL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_FDCDRD_APVAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_FDCDRD_APVAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_FDCDRD_APVAL_INIT_ENUM                   DISABLE
+#define MC_AP_CTRL_0_0_FDCDRD_APVAL_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_FDCDRD_APVAL_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_FDCDRD_APVAL_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_FDCDRD_APVAL_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_G2DR_APVAL_SHIFT                 _MK_SHIFT_CONST(17)
+#define MC_AP_CTRL_0_0_G2DR_APVAL_FIELD                 (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_G2DR_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_G2DR_APVAL_RANGE                 17:17
+#define MC_AP_CTRL_0_0_G2DR_APVAL_WOFFSET                       0x0
+#define MC_AP_CTRL_0_0_G2DR_APVAL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_G2DR_APVAL_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_G2DR_APVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_G2DR_APVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_G2DR_APVAL_INIT_ENUM                     DISABLE
+#define MC_AP_CTRL_0_0_G2DR_APVAL_DISABLE                       _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_G2DR_APVAL_ENABLE                        _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_G2DR_APVAL_DISABLED                      _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_G2DR_APVAL_ENABLED                       _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_HOST1XDMAR_APVAL_SHIFT                   _MK_SHIFT_CONST(18)
+#define MC_AP_CTRL_0_0_HOST1XDMAR_APVAL_FIELD                   (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_HOST1XDMAR_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_HOST1XDMAR_APVAL_RANGE                   18:18
+#define MC_AP_CTRL_0_0_HOST1XDMAR_APVAL_WOFFSET                 0x0
+#define MC_AP_CTRL_0_0_HOST1XDMAR_APVAL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_HOST1XDMAR_APVAL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_HOST1XDMAR_APVAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_HOST1XDMAR_APVAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_HOST1XDMAR_APVAL_INIT_ENUM                       DISABLE
+#define MC_AP_CTRL_0_0_HOST1XDMAR_APVAL_DISABLE                 _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_HOST1XDMAR_APVAL_ENABLE                  _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_HOST1XDMAR_APVAL_DISABLED                        _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_HOST1XDMAR_APVAL_ENABLED                 _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_HOST1XR_APVAL_SHIFT                      _MK_SHIFT_CONST(19)
+#define MC_AP_CTRL_0_0_HOST1XR_APVAL_FIELD                      (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_HOST1XR_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_HOST1XR_APVAL_RANGE                      19:19
+#define MC_AP_CTRL_0_0_HOST1XR_APVAL_WOFFSET                    0x0
+#define MC_AP_CTRL_0_0_HOST1XR_APVAL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_HOST1XR_APVAL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_HOST1XR_APVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_HOST1XR_APVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_HOST1XR_APVAL_INIT_ENUM                  DISABLE
+#define MC_AP_CTRL_0_0_HOST1XR_APVAL_DISABLE                    _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_HOST1XR_APVAL_ENABLE                     _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_HOST1XR_APVAL_DISABLED                   _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_HOST1XR_APVAL_ENABLED                    _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_IDXSRD_APVAL_SHIFT                       _MK_SHIFT_CONST(20)
+#define MC_AP_CTRL_0_0_IDXSRD_APVAL_FIELD                       (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_IDXSRD_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_IDXSRD_APVAL_RANGE                       20:20
+#define MC_AP_CTRL_0_0_IDXSRD_APVAL_WOFFSET                     0x0
+#define MC_AP_CTRL_0_0_IDXSRD_APVAL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_IDXSRD_APVAL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_IDXSRD_APVAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_IDXSRD_APVAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_IDXSRD_APVAL_INIT_ENUM                   DISABLE
+#define MC_AP_CTRL_0_0_IDXSRD_APVAL_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_IDXSRD_APVAL_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_IDXSRD_APVAL_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_IDXSRD_APVAL_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_MPCORER_APVAL_SHIFT                      _MK_SHIFT_CONST(21)
+#define MC_AP_CTRL_0_0_MPCORER_APVAL_FIELD                      (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_MPCORER_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_MPCORER_APVAL_RANGE                      21:21
+#define MC_AP_CTRL_0_0_MPCORER_APVAL_WOFFSET                    0x0
+#define MC_AP_CTRL_0_0_MPCORER_APVAL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_MPCORER_APVAL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_MPCORER_APVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_MPCORER_APVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_MPCORER_APVAL_INIT_ENUM                  DISABLE
+#define MC_AP_CTRL_0_0_MPCORER_APVAL_DISABLE                    _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_MPCORER_APVAL_ENABLE                     _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_MPCORER_APVAL_DISABLED                   _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_MPCORER_APVAL_ENABLED                    _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_MPE_IPRED_APVAL_SHIFT                    _MK_SHIFT_CONST(22)
+#define MC_AP_CTRL_0_0_MPE_IPRED_APVAL_FIELD                    (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_MPE_IPRED_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_MPE_IPRED_APVAL_RANGE                    22:22
+#define MC_AP_CTRL_0_0_MPE_IPRED_APVAL_WOFFSET                  0x0
+#define MC_AP_CTRL_0_0_MPE_IPRED_APVAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_MPE_IPRED_APVAL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_MPE_IPRED_APVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_MPE_IPRED_APVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_MPE_IPRED_APVAL_INIT_ENUM                        DISABLE
+#define MC_AP_CTRL_0_0_MPE_IPRED_APVAL_DISABLE                  _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_MPE_IPRED_APVAL_ENABLE                   _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_MPE_IPRED_APVAL_DISABLED                 _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_MPE_IPRED_APVAL_ENABLED                  _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_MPEAMEMRD_APVAL_SHIFT                    _MK_SHIFT_CONST(23)
+#define MC_AP_CTRL_0_0_MPEAMEMRD_APVAL_FIELD                    (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_MPEAMEMRD_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_MPEAMEMRD_APVAL_RANGE                    23:23
+#define MC_AP_CTRL_0_0_MPEAMEMRD_APVAL_WOFFSET                  0x0
+#define MC_AP_CTRL_0_0_MPEAMEMRD_APVAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_MPEAMEMRD_APVAL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_MPEAMEMRD_APVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_MPEAMEMRD_APVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_MPEAMEMRD_APVAL_INIT_ENUM                        DISABLE
+#define MC_AP_CTRL_0_0_MPEAMEMRD_APVAL_DISABLE                  _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_MPEAMEMRD_APVAL_ENABLE                   _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_MPEAMEMRD_APVAL_DISABLED                 _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_MPEAMEMRD_APVAL_ENABLED                  _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_MPECSRD_APVAL_SHIFT                      _MK_SHIFT_CONST(24)
+#define MC_AP_CTRL_0_0_MPECSRD_APVAL_FIELD                      (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_MPECSRD_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_MPECSRD_APVAL_RANGE                      24:24
+#define MC_AP_CTRL_0_0_MPECSRD_APVAL_WOFFSET                    0x0
+#define MC_AP_CTRL_0_0_MPECSRD_APVAL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_MPECSRD_APVAL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_MPECSRD_APVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_MPECSRD_APVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_MPECSRD_APVAL_INIT_ENUM                  DISABLE
+#define MC_AP_CTRL_0_0_MPECSRD_APVAL_DISABLE                    _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_MPECSRD_APVAL_ENABLE                     _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_MPECSRD_APVAL_DISABLED                   _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_MPECSRD_APVAL_ENABLED                    _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_PPCSAHBDMAR_APVAL_SHIFT                  _MK_SHIFT_CONST(25)
+#define MC_AP_CTRL_0_0_PPCSAHBDMAR_APVAL_FIELD                  (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_PPCSAHBDMAR_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_PPCSAHBDMAR_APVAL_RANGE                  25:25
+#define MC_AP_CTRL_0_0_PPCSAHBDMAR_APVAL_WOFFSET                        0x0
+#define MC_AP_CTRL_0_0_PPCSAHBDMAR_APVAL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_PPCSAHBDMAR_APVAL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_PPCSAHBDMAR_APVAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_PPCSAHBDMAR_APVAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_PPCSAHBDMAR_APVAL_INIT_ENUM                      DISABLE
+#define MC_AP_CTRL_0_0_PPCSAHBDMAR_APVAL_DISABLE                        _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_PPCSAHBDMAR_APVAL_ENABLE                 _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_PPCSAHBDMAR_APVAL_DISABLED                       _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_PPCSAHBDMAR_APVAL_ENABLED                        _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_PPCSAHBSLVR_APVAL_SHIFT                  _MK_SHIFT_CONST(26)
+#define MC_AP_CTRL_0_0_PPCSAHBSLVR_APVAL_FIELD                  (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_PPCSAHBSLVR_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_PPCSAHBSLVR_APVAL_RANGE                  26:26
+#define MC_AP_CTRL_0_0_PPCSAHBSLVR_APVAL_WOFFSET                        0x0
+#define MC_AP_CTRL_0_0_PPCSAHBSLVR_APVAL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_PPCSAHBSLVR_APVAL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_PPCSAHBSLVR_APVAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_PPCSAHBSLVR_APVAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_PPCSAHBSLVR_APVAL_INIT_ENUM                      DISABLE
+#define MC_AP_CTRL_0_0_PPCSAHBSLVR_APVAL_DISABLE                        _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_PPCSAHBSLVR_APVAL_ENABLE                 _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_PPCSAHBSLVR_APVAL_DISABLED                       _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_PPCSAHBSLVR_APVAL_ENABLED                        _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_TEXSRD_APVAL_SHIFT                       _MK_SHIFT_CONST(27)
+#define MC_AP_CTRL_0_0_TEXSRD_APVAL_FIELD                       (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_TEXSRD_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_TEXSRD_APVAL_RANGE                       27:27
+#define MC_AP_CTRL_0_0_TEXSRD_APVAL_WOFFSET                     0x0
+#define MC_AP_CTRL_0_0_TEXSRD_APVAL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_TEXSRD_APVAL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_TEXSRD_APVAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_TEXSRD_APVAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_TEXSRD_APVAL_INIT_ENUM                   DISABLE
+#define MC_AP_CTRL_0_0_TEXSRD_APVAL_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_TEXSRD_APVAL_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_TEXSRD_APVAL_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_TEXSRD_APVAL_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_VDEBSEVR_APVAL_SHIFT                     _MK_SHIFT_CONST(28)
+#define MC_AP_CTRL_0_0_VDEBSEVR_APVAL_FIELD                     (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_VDEBSEVR_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_VDEBSEVR_APVAL_RANGE                     28:28
+#define MC_AP_CTRL_0_0_VDEBSEVR_APVAL_WOFFSET                   0x0
+#define MC_AP_CTRL_0_0_VDEBSEVR_APVAL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_VDEBSEVR_APVAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_VDEBSEVR_APVAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_VDEBSEVR_APVAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_VDEBSEVR_APVAL_INIT_ENUM                 DISABLE
+#define MC_AP_CTRL_0_0_VDEBSEVR_APVAL_DISABLE                   _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_VDEBSEVR_APVAL_ENABLE                    _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_VDEBSEVR_APVAL_DISABLED                  _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_VDEBSEVR_APVAL_ENABLED                   _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_VDEMBER_APVAL_SHIFT                      _MK_SHIFT_CONST(29)
+#define MC_AP_CTRL_0_0_VDEMBER_APVAL_FIELD                      (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_VDEMBER_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_VDEMBER_APVAL_RANGE                      29:29
+#define MC_AP_CTRL_0_0_VDEMBER_APVAL_WOFFSET                    0x0
+#define MC_AP_CTRL_0_0_VDEMBER_APVAL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_VDEMBER_APVAL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_VDEMBER_APVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_VDEMBER_APVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_VDEMBER_APVAL_INIT_ENUM                  DISABLE
+#define MC_AP_CTRL_0_0_VDEMBER_APVAL_DISABLE                    _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_VDEMBER_APVAL_ENABLE                     _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_VDEMBER_APVAL_DISABLED                   _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_VDEMBER_APVAL_ENABLED                    _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_VDEMCER_APVAL_SHIFT                      _MK_SHIFT_CONST(30)
+#define MC_AP_CTRL_0_0_VDEMCER_APVAL_FIELD                      (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_VDEMCER_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_VDEMCER_APVAL_RANGE                      30:30
+#define MC_AP_CTRL_0_0_VDEMCER_APVAL_WOFFSET                    0x0
+#define MC_AP_CTRL_0_0_VDEMCER_APVAL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_VDEMCER_APVAL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_VDEMCER_APVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_VDEMCER_APVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_VDEMCER_APVAL_INIT_ENUM                  DISABLE
+#define MC_AP_CTRL_0_0_VDEMCER_APVAL_DISABLE                    _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_VDEMCER_APVAL_ENABLE                     _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_VDEMCER_APVAL_DISABLED                   _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_VDEMCER_APVAL_ENABLED                    _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_VDETPER_APVAL_SHIFT                      _MK_SHIFT_CONST(31)
+#define MC_AP_CTRL_0_0_VDETPER_APVAL_FIELD                      (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_VDETPER_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_VDETPER_APVAL_RANGE                      31:31
+#define MC_AP_CTRL_0_0_VDETPER_APVAL_WOFFSET                    0x0
+#define MC_AP_CTRL_0_0_VDETPER_APVAL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_VDETPER_APVAL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_VDETPER_APVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_VDETPER_APVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_VDETPER_APVAL_INIT_ENUM                  DISABLE
+#define MC_AP_CTRL_0_0_VDETPER_APVAL_DISABLE                    _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_VDETPER_APVAL_ENABLE                     _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_VDETPER_APVAL_DISABLED                   _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_VDETPER_APVAL_ENABLED                    _MK_ENUM_CONST(1)
+
+
+// Register MC_AP_CTRL_1_0  
+#define MC_AP_CTRL_1_0                  _MK_ADDR_CONST(0x12c)
+#define MC_AP_CTRL_1_0_SECURE                   0x0
+#define MC_AP_CTRL_1_0_WORD_COUNT                       0x1
+#define MC_AP_CTRL_1_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_RESET_MASK                       _MK_MASK_CONST(0xfffff)
+#define MC_AP_CTRL_1_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_READ_MASK                        _MK_MASK_CONST(0xfffff)
+#define MC_AP_CTRL_1_0_WRITE_MASK                       _MK_MASK_CONST(0xfffff)
+#define MC_AP_CTRL_1_0_EPPU_APVAL_SHIFT                 _MK_SHIFT_CONST(0)
+#define MC_AP_CTRL_1_0_EPPU_APVAL_FIELD                 (_MK_MASK_CONST(0x1) << MC_AP_CTRL_1_0_EPPU_APVAL_SHIFT)
+#define MC_AP_CTRL_1_0_EPPU_APVAL_RANGE                 0:0
+#define MC_AP_CTRL_1_0_EPPU_APVAL_WOFFSET                       0x0
+#define MC_AP_CTRL_1_0_EPPU_APVAL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_EPPU_APVAL_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_1_0_EPPU_APVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_EPPU_APVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_EPPU_APVAL_INIT_ENUM                     DISABLE
+#define MC_AP_CTRL_1_0_EPPU_APVAL_DISABLE                       _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_EPPU_APVAL_ENABLE                        _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_1_0_EPPU_APVAL_DISABLED                      _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_EPPU_APVAL_ENABLED                       _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_1_0_EPPV_APVAL_SHIFT                 _MK_SHIFT_CONST(1)
+#define MC_AP_CTRL_1_0_EPPV_APVAL_FIELD                 (_MK_MASK_CONST(0x1) << MC_AP_CTRL_1_0_EPPV_APVAL_SHIFT)
+#define MC_AP_CTRL_1_0_EPPV_APVAL_RANGE                 1:1
+#define MC_AP_CTRL_1_0_EPPV_APVAL_WOFFSET                       0x0
+#define MC_AP_CTRL_1_0_EPPV_APVAL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_EPPV_APVAL_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_1_0_EPPV_APVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_EPPV_APVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_EPPV_APVAL_INIT_ENUM                     DISABLE
+#define MC_AP_CTRL_1_0_EPPV_APVAL_DISABLE                       _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_EPPV_APVAL_ENABLE                        _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_1_0_EPPV_APVAL_DISABLED                      _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_EPPV_APVAL_ENABLED                       _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_1_0_EPPY_APVAL_SHIFT                 _MK_SHIFT_CONST(2)
+#define MC_AP_CTRL_1_0_EPPY_APVAL_FIELD                 (_MK_MASK_CONST(0x1) << MC_AP_CTRL_1_0_EPPY_APVAL_SHIFT)
+#define MC_AP_CTRL_1_0_EPPY_APVAL_RANGE                 2:2
+#define MC_AP_CTRL_1_0_EPPY_APVAL_WOFFSET                       0x0
+#define MC_AP_CTRL_1_0_EPPY_APVAL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_EPPY_APVAL_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_1_0_EPPY_APVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_EPPY_APVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_EPPY_APVAL_INIT_ENUM                     DISABLE
+#define MC_AP_CTRL_1_0_EPPY_APVAL_DISABLE                       _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_EPPY_APVAL_ENABLE                        _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_1_0_EPPY_APVAL_DISABLED                      _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_EPPY_APVAL_ENABLED                       _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_1_0_MPEUNIFBW_APVAL_SHIFT                    _MK_SHIFT_CONST(3)
+#define MC_AP_CTRL_1_0_MPEUNIFBW_APVAL_FIELD                    (_MK_MASK_CONST(0x1) << MC_AP_CTRL_1_0_MPEUNIFBW_APVAL_SHIFT)
+#define MC_AP_CTRL_1_0_MPEUNIFBW_APVAL_RANGE                    3:3
+#define MC_AP_CTRL_1_0_MPEUNIFBW_APVAL_WOFFSET                  0x0
+#define MC_AP_CTRL_1_0_MPEUNIFBW_APVAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_MPEUNIFBW_APVAL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_1_0_MPEUNIFBW_APVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_MPEUNIFBW_APVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_MPEUNIFBW_APVAL_INIT_ENUM                        DISABLE
+#define MC_AP_CTRL_1_0_MPEUNIFBW_APVAL_DISABLE                  _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_MPEUNIFBW_APVAL_ENABLE                   _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_1_0_MPEUNIFBW_APVAL_DISABLED                 _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_MPEUNIFBW_APVAL_ENABLED                  _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_1_0_VIWSB_APVAL_SHIFT                        _MK_SHIFT_CONST(4)
+#define MC_AP_CTRL_1_0_VIWSB_APVAL_FIELD                        (_MK_MASK_CONST(0x1) << MC_AP_CTRL_1_0_VIWSB_APVAL_SHIFT)
+#define MC_AP_CTRL_1_0_VIWSB_APVAL_RANGE                        4:4
+#define MC_AP_CTRL_1_0_VIWSB_APVAL_WOFFSET                      0x0
+#define MC_AP_CTRL_1_0_VIWSB_APVAL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_VIWSB_APVAL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_1_0_VIWSB_APVAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_VIWSB_APVAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_VIWSB_APVAL_INIT_ENUM                    DISABLE
+#define MC_AP_CTRL_1_0_VIWSB_APVAL_DISABLE                      _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_VIWSB_APVAL_ENABLE                       _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_1_0_VIWSB_APVAL_DISABLED                     _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_VIWSB_APVAL_ENABLED                      _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_1_0_VIWU_APVAL_SHIFT                 _MK_SHIFT_CONST(5)
+#define MC_AP_CTRL_1_0_VIWU_APVAL_FIELD                 (_MK_MASK_CONST(0x1) << MC_AP_CTRL_1_0_VIWU_APVAL_SHIFT)
+#define MC_AP_CTRL_1_0_VIWU_APVAL_RANGE                 5:5
+#define MC_AP_CTRL_1_0_VIWU_APVAL_WOFFSET                       0x0
+#define MC_AP_CTRL_1_0_VIWU_APVAL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_VIWU_APVAL_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_1_0_VIWU_APVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_VIWU_APVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_VIWU_APVAL_INIT_ENUM                     DISABLE
+#define MC_AP_CTRL_1_0_VIWU_APVAL_DISABLE                       _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_VIWU_APVAL_ENABLE                        _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_1_0_VIWU_APVAL_DISABLED                      _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_VIWU_APVAL_ENABLED                       _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_1_0_VIWV_APVAL_SHIFT                 _MK_SHIFT_CONST(6)
+#define MC_AP_CTRL_1_0_VIWV_APVAL_FIELD                 (_MK_MASK_CONST(0x1) << MC_AP_CTRL_1_0_VIWV_APVAL_SHIFT)
+#define MC_AP_CTRL_1_0_VIWV_APVAL_RANGE                 6:6
+#define MC_AP_CTRL_1_0_VIWV_APVAL_WOFFSET                       0x0
+#define MC_AP_CTRL_1_0_VIWV_APVAL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_VIWV_APVAL_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_1_0_VIWV_APVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_VIWV_APVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_VIWV_APVAL_INIT_ENUM                     DISABLE
+#define MC_AP_CTRL_1_0_VIWV_APVAL_DISABLE                       _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_VIWV_APVAL_ENABLE                        _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_1_0_VIWV_APVAL_DISABLED                      _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_VIWV_APVAL_ENABLED                       _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_1_0_VIWY_APVAL_SHIFT                 _MK_SHIFT_CONST(7)
+#define MC_AP_CTRL_1_0_VIWY_APVAL_FIELD                 (_MK_MASK_CONST(0x1) << MC_AP_CTRL_1_0_VIWY_APVAL_SHIFT)
+#define MC_AP_CTRL_1_0_VIWY_APVAL_RANGE                 7:7
+#define MC_AP_CTRL_1_0_VIWY_APVAL_WOFFSET                       0x0
+#define MC_AP_CTRL_1_0_VIWY_APVAL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_VIWY_APVAL_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_1_0_VIWY_APVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_VIWY_APVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_VIWY_APVAL_INIT_ENUM                     DISABLE
+#define MC_AP_CTRL_1_0_VIWY_APVAL_DISABLE                       _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_VIWY_APVAL_ENABLE                        _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_1_0_VIWY_APVAL_DISABLED                      _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_VIWY_APVAL_ENABLED                       _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_1_0_G2DW_APVAL_SHIFT                 _MK_SHIFT_CONST(8)
+#define MC_AP_CTRL_1_0_G2DW_APVAL_FIELD                 (_MK_MASK_CONST(0x1) << MC_AP_CTRL_1_0_G2DW_APVAL_SHIFT)
+#define MC_AP_CTRL_1_0_G2DW_APVAL_RANGE                 8:8
+#define MC_AP_CTRL_1_0_G2DW_APVAL_WOFFSET                       0x0
+#define MC_AP_CTRL_1_0_G2DW_APVAL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_G2DW_APVAL_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_1_0_G2DW_APVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_G2DW_APVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_G2DW_APVAL_INIT_ENUM                     DISABLE
+#define MC_AP_CTRL_1_0_G2DW_APVAL_DISABLE                       _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_G2DW_APVAL_ENABLE                        _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_1_0_G2DW_APVAL_DISABLED                      _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_G2DW_APVAL_ENABLED                       _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_1_0_AVPCARM7W_APVAL_SHIFT                    _MK_SHIFT_CONST(9)
+#define MC_AP_CTRL_1_0_AVPCARM7W_APVAL_FIELD                    (_MK_MASK_CONST(0x1) << MC_AP_CTRL_1_0_AVPCARM7W_APVAL_SHIFT)
+#define MC_AP_CTRL_1_0_AVPCARM7W_APVAL_RANGE                    9:9
+#define MC_AP_CTRL_1_0_AVPCARM7W_APVAL_WOFFSET                  0x0
+#define MC_AP_CTRL_1_0_AVPCARM7W_APVAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_AVPCARM7W_APVAL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_1_0_AVPCARM7W_APVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_AVPCARM7W_APVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_AVPCARM7W_APVAL_INIT_ENUM                        DISABLE
+#define MC_AP_CTRL_1_0_AVPCARM7W_APVAL_DISABLE                  _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_AVPCARM7W_APVAL_ENABLE                   _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_1_0_AVPCARM7W_APVAL_DISABLED                 _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_AVPCARM7W_APVAL_ENABLED                  _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_1_0_FDCDWR_APVAL_SHIFT                       _MK_SHIFT_CONST(10)
+#define MC_AP_CTRL_1_0_FDCDWR_APVAL_FIELD                       (_MK_MASK_CONST(0x1) << MC_AP_CTRL_1_0_FDCDWR_APVAL_SHIFT)
+#define MC_AP_CTRL_1_0_FDCDWR_APVAL_RANGE                       10:10
+#define MC_AP_CTRL_1_0_FDCDWR_APVAL_WOFFSET                     0x0
+#define MC_AP_CTRL_1_0_FDCDWR_APVAL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_FDCDWR_APVAL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_1_0_FDCDWR_APVAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_FDCDWR_APVAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_FDCDWR_APVAL_INIT_ENUM                   DISABLE
+#define MC_AP_CTRL_1_0_FDCDWR_APVAL_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_FDCDWR_APVAL_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_1_0_FDCDWR_APVAL_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_FDCDWR_APVAL_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_1_0_HOST1XW_APVAL_SHIFT                      _MK_SHIFT_CONST(11)
+#define MC_AP_CTRL_1_0_HOST1XW_APVAL_FIELD                      (_MK_MASK_CONST(0x1) << MC_AP_CTRL_1_0_HOST1XW_APVAL_SHIFT)
+#define MC_AP_CTRL_1_0_HOST1XW_APVAL_RANGE                      11:11
+#define MC_AP_CTRL_1_0_HOST1XW_APVAL_WOFFSET                    0x0
+#define MC_AP_CTRL_1_0_HOST1XW_APVAL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_HOST1XW_APVAL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_1_0_HOST1XW_APVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_HOST1XW_APVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_HOST1XW_APVAL_INIT_ENUM                  DISABLE
+#define MC_AP_CTRL_1_0_HOST1XW_APVAL_DISABLE                    _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_HOST1XW_APVAL_ENABLE                     _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_1_0_HOST1XW_APVAL_DISABLED                   _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_HOST1XW_APVAL_ENABLED                    _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_1_0_ISPW_APVAL_SHIFT                 _MK_SHIFT_CONST(12)
+#define MC_AP_CTRL_1_0_ISPW_APVAL_FIELD                 (_MK_MASK_CONST(0x1) << MC_AP_CTRL_1_0_ISPW_APVAL_SHIFT)
+#define MC_AP_CTRL_1_0_ISPW_APVAL_RANGE                 12:12
+#define MC_AP_CTRL_1_0_ISPW_APVAL_WOFFSET                       0x0
+#define MC_AP_CTRL_1_0_ISPW_APVAL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_ISPW_APVAL_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_1_0_ISPW_APVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_ISPW_APVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_ISPW_APVAL_INIT_ENUM                     DISABLE
+#define MC_AP_CTRL_1_0_ISPW_APVAL_DISABLE                       _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_ISPW_APVAL_ENABLE                        _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_1_0_ISPW_APVAL_DISABLED                      _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_ISPW_APVAL_ENABLED                       _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_1_0_MPCOREW_APVAL_SHIFT                      _MK_SHIFT_CONST(13)
+#define MC_AP_CTRL_1_0_MPCOREW_APVAL_FIELD                      (_MK_MASK_CONST(0x1) << MC_AP_CTRL_1_0_MPCOREW_APVAL_SHIFT)
+#define MC_AP_CTRL_1_0_MPCOREW_APVAL_RANGE                      13:13
+#define MC_AP_CTRL_1_0_MPCOREW_APVAL_WOFFSET                    0x0
+#define MC_AP_CTRL_1_0_MPCOREW_APVAL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_MPCOREW_APVAL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_1_0_MPCOREW_APVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_MPCOREW_APVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_MPCOREW_APVAL_INIT_ENUM                  DISABLE
+#define MC_AP_CTRL_1_0_MPCOREW_APVAL_DISABLE                    _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_MPCOREW_APVAL_ENABLE                     _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_1_0_MPCOREW_APVAL_DISABLED                   _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_MPCOREW_APVAL_ENABLED                    _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_1_0_MPECSWR_APVAL_SHIFT                      _MK_SHIFT_CONST(14)
+#define MC_AP_CTRL_1_0_MPECSWR_APVAL_FIELD                      (_MK_MASK_CONST(0x1) << MC_AP_CTRL_1_0_MPECSWR_APVAL_SHIFT)
+#define MC_AP_CTRL_1_0_MPECSWR_APVAL_RANGE                      14:14
+#define MC_AP_CTRL_1_0_MPECSWR_APVAL_WOFFSET                    0x0
+#define MC_AP_CTRL_1_0_MPECSWR_APVAL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_MPECSWR_APVAL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_1_0_MPECSWR_APVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_MPECSWR_APVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_MPECSWR_APVAL_INIT_ENUM                  DISABLE
+#define MC_AP_CTRL_1_0_MPECSWR_APVAL_DISABLE                    _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_MPECSWR_APVAL_ENABLE                     _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_1_0_MPECSWR_APVAL_DISABLED                   _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_MPECSWR_APVAL_ENABLED                    _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_1_0_PPCSAHBDMAW_APVAL_SHIFT                  _MK_SHIFT_CONST(15)
+#define MC_AP_CTRL_1_0_PPCSAHBDMAW_APVAL_FIELD                  (_MK_MASK_CONST(0x1) << MC_AP_CTRL_1_0_PPCSAHBDMAW_APVAL_SHIFT)
+#define MC_AP_CTRL_1_0_PPCSAHBDMAW_APVAL_RANGE                  15:15
+#define MC_AP_CTRL_1_0_PPCSAHBDMAW_APVAL_WOFFSET                        0x0
+#define MC_AP_CTRL_1_0_PPCSAHBDMAW_APVAL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_PPCSAHBDMAW_APVAL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_1_0_PPCSAHBDMAW_APVAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_PPCSAHBDMAW_APVAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_PPCSAHBDMAW_APVAL_INIT_ENUM                      DISABLE
+#define MC_AP_CTRL_1_0_PPCSAHBDMAW_APVAL_DISABLE                        _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_PPCSAHBDMAW_APVAL_ENABLE                 _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_1_0_PPCSAHBDMAW_APVAL_DISABLED                       _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_PPCSAHBDMAW_APVAL_ENABLED                        _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_1_0_PPCSAHBSLVW_APVAL_SHIFT                  _MK_SHIFT_CONST(16)
+#define MC_AP_CTRL_1_0_PPCSAHBSLVW_APVAL_FIELD                  (_MK_MASK_CONST(0x1) << MC_AP_CTRL_1_0_PPCSAHBSLVW_APVAL_SHIFT)
+#define MC_AP_CTRL_1_0_PPCSAHBSLVW_APVAL_RANGE                  16:16
+#define MC_AP_CTRL_1_0_PPCSAHBSLVW_APVAL_WOFFSET                        0x0
+#define MC_AP_CTRL_1_0_PPCSAHBSLVW_APVAL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_PPCSAHBSLVW_APVAL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_1_0_PPCSAHBSLVW_APVAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_PPCSAHBSLVW_APVAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_PPCSAHBSLVW_APVAL_INIT_ENUM                      DISABLE
+#define MC_AP_CTRL_1_0_PPCSAHBSLVW_APVAL_DISABLE                        _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_PPCSAHBSLVW_APVAL_ENABLE                 _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_1_0_PPCSAHBSLVW_APVAL_DISABLED                       _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_PPCSAHBSLVW_APVAL_ENABLED                        _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_1_0_VDEBSEVW_APVAL_SHIFT                     _MK_SHIFT_CONST(17)
+#define MC_AP_CTRL_1_0_VDEBSEVW_APVAL_FIELD                     (_MK_MASK_CONST(0x1) << MC_AP_CTRL_1_0_VDEBSEVW_APVAL_SHIFT)
+#define MC_AP_CTRL_1_0_VDEBSEVW_APVAL_RANGE                     17:17
+#define MC_AP_CTRL_1_0_VDEBSEVW_APVAL_WOFFSET                   0x0
+#define MC_AP_CTRL_1_0_VDEBSEVW_APVAL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_VDEBSEVW_APVAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_1_0_VDEBSEVW_APVAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_VDEBSEVW_APVAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_VDEBSEVW_APVAL_INIT_ENUM                 DISABLE
+#define MC_AP_CTRL_1_0_VDEBSEVW_APVAL_DISABLE                   _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_VDEBSEVW_APVAL_ENABLE                    _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_1_0_VDEBSEVW_APVAL_DISABLED                  _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_VDEBSEVW_APVAL_ENABLED                   _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_1_0_VDEMBEW_APVAL_SHIFT                      _MK_SHIFT_CONST(18)
+#define MC_AP_CTRL_1_0_VDEMBEW_APVAL_FIELD                      (_MK_MASK_CONST(0x1) << MC_AP_CTRL_1_0_VDEMBEW_APVAL_SHIFT)
+#define MC_AP_CTRL_1_0_VDEMBEW_APVAL_RANGE                      18:18
+#define MC_AP_CTRL_1_0_VDEMBEW_APVAL_WOFFSET                    0x0
+#define MC_AP_CTRL_1_0_VDEMBEW_APVAL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_VDEMBEW_APVAL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_1_0_VDEMBEW_APVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_VDEMBEW_APVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_VDEMBEW_APVAL_INIT_ENUM                  DISABLE
+#define MC_AP_CTRL_1_0_VDEMBEW_APVAL_DISABLE                    _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_VDEMBEW_APVAL_ENABLE                     _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_1_0_VDEMBEW_APVAL_DISABLED                   _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_VDEMBEW_APVAL_ENABLED                    _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_1_0_VDETPMW_APVAL_SHIFT                      _MK_SHIFT_CONST(19)
+#define MC_AP_CTRL_1_0_VDETPMW_APVAL_FIELD                      (_MK_MASK_CONST(0x1) << MC_AP_CTRL_1_0_VDETPMW_APVAL_SHIFT)
+#define MC_AP_CTRL_1_0_VDETPMW_APVAL_RANGE                      19:19
+#define MC_AP_CTRL_1_0_VDETPMW_APVAL_WOFFSET                    0x0
+#define MC_AP_CTRL_1_0_VDETPMW_APVAL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_VDETPMW_APVAL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_1_0_VDETPMW_APVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_VDETPMW_APVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_VDETPMW_APVAL_INIT_ENUM                  DISABLE
+#define MC_AP_CTRL_1_0_VDETPMW_APVAL_DISABLE                    _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_VDETPMW_APVAL_ENABLE                     _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_1_0_VDETPMW_APVAL_DISABLED                   _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_VDETPMW_APVAL_ENABLED                    _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_INACTIVE     0
+#define MC_CLIENT_ACTIVITY_MONITOR_ACTIVE       1
+
+// Reserved address 304 [0x130] 
+
+// Reserved address 308 [0x134] 
+
+// Register MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0  
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0                     _MK_ADDR_CONST(0x138)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_SECURE                      0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_WORD_COUNT                  0x1
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0A_EMEM_ACTIVITY_SHIFT                       _MK_SHIFT_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0A_EMEM_ACTIVITY_FIELD                       (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0A_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0A_EMEM_ACTIVITY_RANGE                       0:0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0A_EMEM_ACTIVITY_WOFFSET                     0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0A_EMEM_ACTIVITY_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0A_EMEM_ACTIVITY_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0A_EMEM_ACTIVITY_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0A_EMEM_ACTIVITY_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0A_EMEM_ACTIVITY_INIT_ENUM                   DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0A_EMEM_ACTIVITY_INACTIVE                    _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0A_EMEM_ACTIVITY_ACTIVE                      _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0AB_EMEM_ACTIVITY_SHIFT                      _MK_SHIFT_CONST(1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0AB_EMEM_ACTIVITY_FIELD                      (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0AB_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0AB_EMEM_ACTIVITY_RANGE                      1:1
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0AB_EMEM_ACTIVITY_WOFFSET                    0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0AB_EMEM_ACTIVITY_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0AB_EMEM_ACTIVITY_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0AB_EMEM_ACTIVITY_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0AB_EMEM_ACTIVITY_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0AB_EMEM_ACTIVITY_INIT_ENUM                  DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0AB_EMEM_ACTIVITY_INACTIVE                   _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0AB_EMEM_ACTIVITY_ACTIVE                     _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0B_EMEM_ACTIVITY_SHIFT                       _MK_SHIFT_CONST(2)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0B_EMEM_ACTIVITY_FIELD                       (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0B_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0B_EMEM_ACTIVITY_RANGE                       2:2
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0B_EMEM_ACTIVITY_WOFFSET                     0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0B_EMEM_ACTIVITY_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0B_EMEM_ACTIVITY_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0B_EMEM_ACTIVITY_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0B_EMEM_ACTIVITY_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0B_EMEM_ACTIVITY_INIT_ENUM                   DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0B_EMEM_ACTIVITY_INACTIVE                    _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0B_EMEM_ACTIVITY_ACTIVE                      _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0BB_EMEM_ACTIVITY_SHIFT                      _MK_SHIFT_CONST(3)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0BB_EMEM_ACTIVITY_FIELD                      (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0BB_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0BB_EMEM_ACTIVITY_RANGE                      3:3
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0BB_EMEM_ACTIVITY_WOFFSET                    0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0BB_EMEM_ACTIVITY_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0BB_EMEM_ACTIVITY_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0BB_EMEM_ACTIVITY_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0BB_EMEM_ACTIVITY_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0BB_EMEM_ACTIVITY_INIT_ENUM                  DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0BB_EMEM_ACTIVITY_INACTIVE                   _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0BB_EMEM_ACTIVITY_ACTIVE                     _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0C_EMEM_ACTIVITY_SHIFT                       _MK_SHIFT_CONST(4)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0C_EMEM_ACTIVITY_FIELD                       (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0C_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0C_EMEM_ACTIVITY_RANGE                       4:4
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0C_EMEM_ACTIVITY_WOFFSET                     0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0C_EMEM_ACTIVITY_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0C_EMEM_ACTIVITY_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0C_EMEM_ACTIVITY_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0C_EMEM_ACTIVITY_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0C_EMEM_ACTIVITY_INIT_ENUM                   DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0C_EMEM_ACTIVITY_INACTIVE                    _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0C_EMEM_ACTIVITY_ACTIVE                      _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0CB_EMEM_ACTIVITY_SHIFT                      _MK_SHIFT_CONST(5)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0CB_EMEM_ACTIVITY_FIELD                      (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0CB_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0CB_EMEM_ACTIVITY_RANGE                      5:5
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0CB_EMEM_ACTIVITY_WOFFSET                    0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0CB_EMEM_ACTIVITY_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0CB_EMEM_ACTIVITY_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0CB_EMEM_ACTIVITY_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0CB_EMEM_ACTIVITY_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0CB_EMEM_ACTIVITY_INIT_ENUM                  DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0CB_EMEM_ACTIVITY_INACTIVE                   _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0CB_EMEM_ACTIVITY_ACTIVE                     _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY1B_EMEM_ACTIVITY_SHIFT                       _MK_SHIFT_CONST(6)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY1B_EMEM_ACTIVITY_FIELD                       (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY1B_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY1B_EMEM_ACTIVITY_RANGE                       6:6
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY1B_EMEM_ACTIVITY_WOFFSET                     0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY1B_EMEM_ACTIVITY_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY1B_EMEM_ACTIVITY_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY1B_EMEM_ACTIVITY_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY1B_EMEM_ACTIVITY_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY1B_EMEM_ACTIVITY_INIT_ENUM                   DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY1B_EMEM_ACTIVITY_INACTIVE                    _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY1B_EMEM_ACTIVITY_ACTIVE                      _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY1BB_EMEM_ACTIVITY_SHIFT                      _MK_SHIFT_CONST(7)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY1BB_EMEM_ACTIVITY_FIELD                      (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY1BB_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY1BB_EMEM_ACTIVITY_RANGE                      7:7
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY1BB_EMEM_ACTIVITY_WOFFSET                    0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY1BB_EMEM_ACTIVITY_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY1BB_EMEM_ACTIVITY_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY1BB_EMEM_ACTIVITY_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY1BB_EMEM_ACTIVITY_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY1BB_EMEM_ACTIVITY_INIT_ENUM                  DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY1BB_EMEM_ACTIVITY_INACTIVE                   _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY1BB_EMEM_ACTIVITY_ACTIVE                     _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_EPPUP_EMEM_ACTIVITY_SHIFT                   _MK_SHIFT_CONST(8)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_EPPUP_EMEM_ACTIVITY_FIELD                   (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_EPPUP_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_EPPUP_EMEM_ACTIVITY_RANGE                   8:8
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_EPPUP_EMEM_ACTIVITY_WOFFSET                 0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_EPPUP_EMEM_ACTIVITY_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_EPPUP_EMEM_ACTIVITY_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_EPPUP_EMEM_ACTIVITY_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_EPPUP_EMEM_ACTIVITY_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_EPPUP_EMEM_ACTIVITY_INIT_ENUM                       DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_EPPUP_EMEM_ACTIVITY_INACTIVE                        _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_EPPUP_EMEM_ACTIVITY_ACTIVE                  _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2PR_EMEM_ACTIVITY_SHIFT                    _MK_SHIFT_CONST(9)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2PR_EMEM_ACTIVITY_FIELD                    (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2PR_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2PR_EMEM_ACTIVITY_RANGE                    9:9
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2PR_EMEM_ACTIVITY_WOFFSET                  0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2PR_EMEM_ACTIVITY_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2PR_EMEM_ACTIVITY_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2PR_EMEM_ACTIVITY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2PR_EMEM_ACTIVITY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2PR_EMEM_ACTIVITY_INIT_ENUM                        DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2PR_EMEM_ACTIVITY_INACTIVE                 _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2PR_EMEM_ACTIVITY_ACTIVE                   _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2SR_EMEM_ACTIVITY_SHIFT                    _MK_SHIFT_CONST(10)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2SR_EMEM_ACTIVITY_FIELD                    (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2SR_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2SR_EMEM_ACTIVITY_RANGE                    10:10
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2SR_EMEM_ACTIVITY_WOFFSET                  0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2SR_EMEM_ACTIVITY_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2SR_EMEM_ACTIVITY_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2SR_EMEM_ACTIVITY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2SR_EMEM_ACTIVITY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2SR_EMEM_ACTIVITY_INIT_ENUM                        DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2SR_EMEM_ACTIVITY_INACTIVE                 _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2SR_EMEM_ACTIVITY_ACTIVE                   _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPEUNIFBR_EMEM_ACTIVITY_SHIFT                       _MK_SHIFT_CONST(11)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPEUNIFBR_EMEM_ACTIVITY_FIELD                       (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPEUNIFBR_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPEUNIFBR_EMEM_ACTIVITY_RANGE                       11:11
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPEUNIFBR_EMEM_ACTIVITY_WOFFSET                     0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPEUNIFBR_EMEM_ACTIVITY_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPEUNIFBR_EMEM_ACTIVITY_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPEUNIFBR_EMEM_ACTIVITY_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPEUNIFBR_EMEM_ACTIVITY_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPEUNIFBR_EMEM_ACTIVITY_INIT_ENUM                   DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPEUNIFBR_EMEM_ACTIVITY_INACTIVE                    _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPEUNIFBR_EMEM_ACTIVITY_ACTIVE                      _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VIRUV_EMEM_ACTIVITY_SHIFT                   _MK_SHIFT_CONST(12)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VIRUV_EMEM_ACTIVITY_FIELD                   (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VIRUV_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VIRUV_EMEM_ACTIVITY_RANGE                   12:12
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VIRUV_EMEM_ACTIVITY_WOFFSET                 0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VIRUV_EMEM_ACTIVITY_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VIRUV_EMEM_ACTIVITY_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VIRUV_EMEM_ACTIVITY_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VIRUV_EMEM_ACTIVITY_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VIRUV_EMEM_ACTIVITY_INIT_ENUM                       DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VIRUV_EMEM_ACTIVITY_INACTIVE                        _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VIRUV_EMEM_ACTIVITY_ACTIVE                  _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_AVPCARM7R_EMEM_ACTIVITY_SHIFT                       _MK_SHIFT_CONST(13)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_AVPCARM7R_EMEM_ACTIVITY_FIELD                       (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_AVPCARM7R_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_AVPCARM7R_EMEM_ACTIVITY_RANGE                       13:13
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_AVPCARM7R_EMEM_ACTIVITY_WOFFSET                     0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_AVPCARM7R_EMEM_ACTIVITY_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_AVPCARM7R_EMEM_ACTIVITY_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_AVPCARM7R_EMEM_ACTIVITY_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_AVPCARM7R_EMEM_ACTIVITY_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_AVPCARM7R_EMEM_ACTIVITY_INIT_ENUM                   DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_AVPCARM7R_EMEM_ACTIVITY_INACTIVE                    _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_AVPCARM7R_EMEM_ACTIVITY_ACTIVE                      _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAYHC_EMEM_ACTIVITY_SHIFT                       _MK_SHIFT_CONST(14)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAYHC_EMEM_ACTIVITY_FIELD                       (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAYHC_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAYHC_EMEM_ACTIVITY_RANGE                       14:14
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAYHC_EMEM_ACTIVITY_WOFFSET                     0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAYHC_EMEM_ACTIVITY_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAYHC_EMEM_ACTIVITY_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAYHC_EMEM_ACTIVITY_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAYHC_EMEM_ACTIVITY_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAYHC_EMEM_ACTIVITY_INIT_ENUM                   DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAYHC_EMEM_ACTIVITY_INACTIVE                    _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAYHC_EMEM_ACTIVITY_ACTIVE                      _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAYHCB_EMEM_ACTIVITY_SHIFT                      _MK_SHIFT_CONST(15)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAYHCB_EMEM_ACTIVITY_FIELD                      (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAYHCB_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAYHCB_EMEM_ACTIVITY_RANGE                      15:15
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAYHCB_EMEM_ACTIVITY_WOFFSET                    0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAYHCB_EMEM_ACTIVITY_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAYHCB_EMEM_ACTIVITY_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAYHCB_EMEM_ACTIVITY_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAYHCB_EMEM_ACTIVITY_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAYHCB_EMEM_ACTIVITY_INIT_ENUM                  DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAYHCB_EMEM_ACTIVITY_INACTIVE                   _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAYHCB_EMEM_ACTIVITY_ACTIVE                     _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_FDCDRD_EMEM_ACTIVITY_SHIFT                  _MK_SHIFT_CONST(16)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_FDCDRD_EMEM_ACTIVITY_FIELD                  (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_FDCDRD_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_FDCDRD_EMEM_ACTIVITY_RANGE                  16:16
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_FDCDRD_EMEM_ACTIVITY_WOFFSET                        0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_FDCDRD_EMEM_ACTIVITY_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_FDCDRD_EMEM_ACTIVITY_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_FDCDRD_EMEM_ACTIVITY_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_FDCDRD_EMEM_ACTIVITY_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_FDCDRD_EMEM_ACTIVITY_INIT_ENUM                      DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_FDCDRD_EMEM_ACTIVITY_INACTIVE                       _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_FDCDRD_EMEM_ACTIVITY_ACTIVE                 _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2DR_EMEM_ACTIVITY_SHIFT                    _MK_SHIFT_CONST(17)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2DR_EMEM_ACTIVITY_FIELD                    (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2DR_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2DR_EMEM_ACTIVITY_RANGE                    17:17
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2DR_EMEM_ACTIVITY_WOFFSET                  0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2DR_EMEM_ACTIVITY_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2DR_EMEM_ACTIVITY_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2DR_EMEM_ACTIVITY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2DR_EMEM_ACTIVITY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2DR_EMEM_ACTIVITY_INIT_ENUM                        DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2DR_EMEM_ACTIVITY_INACTIVE                 _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2DR_EMEM_ACTIVITY_ACTIVE                   _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_HOST1XDMAR_EMEM_ACTIVITY_SHIFT                      _MK_SHIFT_CONST(18)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_HOST1XDMAR_EMEM_ACTIVITY_FIELD                      (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_HOST1XDMAR_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_HOST1XDMAR_EMEM_ACTIVITY_RANGE                      18:18
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_HOST1XDMAR_EMEM_ACTIVITY_WOFFSET                    0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_HOST1XDMAR_EMEM_ACTIVITY_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_HOST1XDMAR_EMEM_ACTIVITY_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_HOST1XDMAR_EMEM_ACTIVITY_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_HOST1XDMAR_EMEM_ACTIVITY_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_HOST1XDMAR_EMEM_ACTIVITY_INIT_ENUM                  DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_HOST1XDMAR_EMEM_ACTIVITY_INACTIVE                   _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_HOST1XDMAR_EMEM_ACTIVITY_ACTIVE                     _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_HOST1XR_EMEM_ACTIVITY_SHIFT                 _MK_SHIFT_CONST(19)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_HOST1XR_EMEM_ACTIVITY_FIELD                 (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_HOST1XR_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_HOST1XR_EMEM_ACTIVITY_RANGE                 19:19
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_HOST1XR_EMEM_ACTIVITY_WOFFSET                       0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_HOST1XR_EMEM_ACTIVITY_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_HOST1XR_EMEM_ACTIVITY_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_HOST1XR_EMEM_ACTIVITY_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_HOST1XR_EMEM_ACTIVITY_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_HOST1XR_EMEM_ACTIVITY_INIT_ENUM                     DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_HOST1XR_EMEM_ACTIVITY_INACTIVE                      _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_HOST1XR_EMEM_ACTIVITY_ACTIVE                        _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_IDXSRD_EMEM_ACTIVITY_SHIFT                  _MK_SHIFT_CONST(20)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_IDXSRD_EMEM_ACTIVITY_FIELD                  (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_IDXSRD_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_IDXSRD_EMEM_ACTIVITY_RANGE                  20:20
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_IDXSRD_EMEM_ACTIVITY_WOFFSET                        0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_IDXSRD_EMEM_ACTIVITY_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_IDXSRD_EMEM_ACTIVITY_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_IDXSRD_EMEM_ACTIVITY_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_IDXSRD_EMEM_ACTIVITY_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_IDXSRD_EMEM_ACTIVITY_INIT_ENUM                      DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_IDXSRD_EMEM_ACTIVITY_INACTIVE                       _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_IDXSRD_EMEM_ACTIVITY_ACTIVE                 _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPCORER_EMEM_ACTIVITY_SHIFT                 _MK_SHIFT_CONST(21)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPCORER_EMEM_ACTIVITY_FIELD                 (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPCORER_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPCORER_EMEM_ACTIVITY_RANGE                 21:21
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPCORER_EMEM_ACTIVITY_WOFFSET                       0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPCORER_EMEM_ACTIVITY_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPCORER_EMEM_ACTIVITY_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPCORER_EMEM_ACTIVITY_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPCORER_EMEM_ACTIVITY_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPCORER_EMEM_ACTIVITY_INIT_ENUM                     DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPCORER_EMEM_ACTIVITY_INACTIVE                      _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPCORER_EMEM_ACTIVITY_ACTIVE                        _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPE_IPRED_EMEM_ACTIVITY_SHIFT                       _MK_SHIFT_CONST(22)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPE_IPRED_EMEM_ACTIVITY_FIELD                       (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPE_IPRED_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPE_IPRED_EMEM_ACTIVITY_RANGE                       22:22
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPE_IPRED_EMEM_ACTIVITY_WOFFSET                     0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPE_IPRED_EMEM_ACTIVITY_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPE_IPRED_EMEM_ACTIVITY_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPE_IPRED_EMEM_ACTIVITY_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPE_IPRED_EMEM_ACTIVITY_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPE_IPRED_EMEM_ACTIVITY_INIT_ENUM                   DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPE_IPRED_EMEM_ACTIVITY_INACTIVE                    _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPE_IPRED_EMEM_ACTIVITY_ACTIVE                      _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPEAMEMRD_EMEM_ACTIVITY_SHIFT                       _MK_SHIFT_CONST(23)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPEAMEMRD_EMEM_ACTIVITY_FIELD                       (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPEAMEMRD_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPEAMEMRD_EMEM_ACTIVITY_RANGE                       23:23
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPEAMEMRD_EMEM_ACTIVITY_WOFFSET                     0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPEAMEMRD_EMEM_ACTIVITY_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPEAMEMRD_EMEM_ACTIVITY_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPEAMEMRD_EMEM_ACTIVITY_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPEAMEMRD_EMEM_ACTIVITY_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPEAMEMRD_EMEM_ACTIVITY_INIT_ENUM                   DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPEAMEMRD_EMEM_ACTIVITY_INACTIVE                    _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPEAMEMRD_EMEM_ACTIVITY_ACTIVE                      _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPECSRD_EMEM_ACTIVITY_SHIFT                 _MK_SHIFT_CONST(24)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPECSRD_EMEM_ACTIVITY_FIELD                 (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPECSRD_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPECSRD_EMEM_ACTIVITY_RANGE                 24:24
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPECSRD_EMEM_ACTIVITY_WOFFSET                       0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPECSRD_EMEM_ACTIVITY_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPECSRD_EMEM_ACTIVITY_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPECSRD_EMEM_ACTIVITY_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPECSRD_EMEM_ACTIVITY_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPECSRD_EMEM_ACTIVITY_INIT_ENUM                     DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPECSRD_EMEM_ACTIVITY_INACTIVE                      _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPECSRD_EMEM_ACTIVITY_ACTIVE                        _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_PPCSAHBDMAR_EMEM_ACTIVITY_SHIFT                     _MK_SHIFT_CONST(25)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_PPCSAHBDMAR_EMEM_ACTIVITY_FIELD                     (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_PPCSAHBDMAR_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_PPCSAHBDMAR_EMEM_ACTIVITY_RANGE                     25:25
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_PPCSAHBDMAR_EMEM_ACTIVITY_WOFFSET                   0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_PPCSAHBDMAR_EMEM_ACTIVITY_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_PPCSAHBDMAR_EMEM_ACTIVITY_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_PPCSAHBDMAR_EMEM_ACTIVITY_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_PPCSAHBDMAR_EMEM_ACTIVITY_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_PPCSAHBDMAR_EMEM_ACTIVITY_INIT_ENUM                 DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_PPCSAHBDMAR_EMEM_ACTIVITY_INACTIVE                  _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_PPCSAHBDMAR_EMEM_ACTIVITY_ACTIVE                    _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_PPCSAHBSLVR_EMEM_ACTIVITY_SHIFT                     _MK_SHIFT_CONST(26)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_PPCSAHBSLVR_EMEM_ACTIVITY_FIELD                     (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_PPCSAHBSLVR_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_PPCSAHBSLVR_EMEM_ACTIVITY_RANGE                     26:26
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_PPCSAHBSLVR_EMEM_ACTIVITY_WOFFSET                   0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_PPCSAHBSLVR_EMEM_ACTIVITY_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_PPCSAHBSLVR_EMEM_ACTIVITY_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_PPCSAHBSLVR_EMEM_ACTIVITY_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_PPCSAHBSLVR_EMEM_ACTIVITY_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_PPCSAHBSLVR_EMEM_ACTIVITY_INIT_ENUM                 DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_PPCSAHBSLVR_EMEM_ACTIVITY_INACTIVE                  _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_PPCSAHBSLVR_EMEM_ACTIVITY_ACTIVE                    _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_TEXSRD_EMEM_ACTIVITY_SHIFT                  _MK_SHIFT_CONST(27)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_TEXSRD_EMEM_ACTIVITY_FIELD                  (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_TEXSRD_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_TEXSRD_EMEM_ACTIVITY_RANGE                  27:27
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_TEXSRD_EMEM_ACTIVITY_WOFFSET                        0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_TEXSRD_EMEM_ACTIVITY_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_TEXSRD_EMEM_ACTIVITY_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_TEXSRD_EMEM_ACTIVITY_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_TEXSRD_EMEM_ACTIVITY_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_TEXSRD_EMEM_ACTIVITY_INIT_ENUM                      DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_TEXSRD_EMEM_ACTIVITY_INACTIVE                       _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_TEXSRD_EMEM_ACTIVITY_ACTIVE                 _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEBSEVR_EMEM_ACTIVITY_SHIFT                        _MK_SHIFT_CONST(28)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEBSEVR_EMEM_ACTIVITY_FIELD                        (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEBSEVR_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEBSEVR_EMEM_ACTIVITY_RANGE                        28:28
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEBSEVR_EMEM_ACTIVITY_WOFFSET                      0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEBSEVR_EMEM_ACTIVITY_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEBSEVR_EMEM_ACTIVITY_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEBSEVR_EMEM_ACTIVITY_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEBSEVR_EMEM_ACTIVITY_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEBSEVR_EMEM_ACTIVITY_INIT_ENUM                    DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEBSEVR_EMEM_ACTIVITY_INACTIVE                     _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEBSEVR_EMEM_ACTIVITY_ACTIVE                       _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEMBER_EMEM_ACTIVITY_SHIFT                 _MK_SHIFT_CONST(29)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEMBER_EMEM_ACTIVITY_FIELD                 (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEMBER_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEMBER_EMEM_ACTIVITY_RANGE                 29:29
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEMBER_EMEM_ACTIVITY_WOFFSET                       0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEMBER_EMEM_ACTIVITY_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEMBER_EMEM_ACTIVITY_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEMBER_EMEM_ACTIVITY_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEMBER_EMEM_ACTIVITY_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEMBER_EMEM_ACTIVITY_INIT_ENUM                     DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEMBER_EMEM_ACTIVITY_INACTIVE                      _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEMBER_EMEM_ACTIVITY_ACTIVE                        _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEMCER_EMEM_ACTIVITY_SHIFT                 _MK_SHIFT_CONST(30)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEMCER_EMEM_ACTIVITY_FIELD                 (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEMCER_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEMCER_EMEM_ACTIVITY_RANGE                 30:30
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEMCER_EMEM_ACTIVITY_WOFFSET                       0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEMCER_EMEM_ACTIVITY_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEMCER_EMEM_ACTIVITY_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEMCER_EMEM_ACTIVITY_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEMCER_EMEM_ACTIVITY_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEMCER_EMEM_ACTIVITY_INIT_ENUM                     DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEMCER_EMEM_ACTIVITY_INACTIVE                      _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEMCER_EMEM_ACTIVITY_ACTIVE                        _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDETPER_EMEM_ACTIVITY_SHIFT                 _MK_SHIFT_CONST(31)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDETPER_EMEM_ACTIVITY_FIELD                 (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDETPER_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDETPER_EMEM_ACTIVITY_RANGE                 31:31
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDETPER_EMEM_ACTIVITY_WOFFSET                       0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDETPER_EMEM_ACTIVITY_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDETPER_EMEM_ACTIVITY_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDETPER_EMEM_ACTIVITY_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDETPER_EMEM_ACTIVITY_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDETPER_EMEM_ACTIVITY_INIT_ENUM                     DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDETPER_EMEM_ACTIVITY_INACTIVE                      _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDETPER_EMEM_ACTIVITY_ACTIVE                        _MK_ENUM_CONST(1)
+
+
+// Register MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0  
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0                     _MK_ADDR_CONST(0x13c)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_SECURE                      0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_WORD_COUNT                  0x1
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_RESET_MASK                  _MK_MASK_CONST(0xfffff)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_READ_MASK                   _MK_MASK_CONST(0xfffff)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_WRITE_MASK                  _MK_MASK_CONST(0xfffff)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPU_EMEM_ACTIVITY_SHIFT                    _MK_SHIFT_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPU_EMEM_ACTIVITY_FIELD                    (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPU_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPU_EMEM_ACTIVITY_RANGE                    0:0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPU_EMEM_ACTIVITY_WOFFSET                  0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPU_EMEM_ACTIVITY_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPU_EMEM_ACTIVITY_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPU_EMEM_ACTIVITY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPU_EMEM_ACTIVITY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPU_EMEM_ACTIVITY_INIT_ENUM                        DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPU_EMEM_ACTIVITY_INACTIVE                 _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPU_EMEM_ACTIVITY_ACTIVE                   _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPV_EMEM_ACTIVITY_SHIFT                    _MK_SHIFT_CONST(1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPV_EMEM_ACTIVITY_FIELD                    (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPV_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPV_EMEM_ACTIVITY_RANGE                    1:1
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPV_EMEM_ACTIVITY_WOFFSET                  0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPV_EMEM_ACTIVITY_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPV_EMEM_ACTIVITY_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPV_EMEM_ACTIVITY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPV_EMEM_ACTIVITY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPV_EMEM_ACTIVITY_INIT_ENUM                        DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPV_EMEM_ACTIVITY_INACTIVE                 _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPV_EMEM_ACTIVITY_ACTIVE                   _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPY_EMEM_ACTIVITY_SHIFT                    _MK_SHIFT_CONST(2)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPY_EMEM_ACTIVITY_FIELD                    (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPY_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPY_EMEM_ACTIVITY_RANGE                    2:2
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPY_EMEM_ACTIVITY_WOFFSET                  0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPY_EMEM_ACTIVITY_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPY_EMEM_ACTIVITY_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPY_EMEM_ACTIVITY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPY_EMEM_ACTIVITY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPY_EMEM_ACTIVITY_INIT_ENUM                        DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPY_EMEM_ACTIVITY_INACTIVE                 _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPY_EMEM_ACTIVITY_ACTIVE                   _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPEUNIFBW_EMEM_ACTIVITY_SHIFT                       _MK_SHIFT_CONST(3)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPEUNIFBW_EMEM_ACTIVITY_FIELD                       (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPEUNIFBW_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPEUNIFBW_EMEM_ACTIVITY_RANGE                       3:3
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPEUNIFBW_EMEM_ACTIVITY_WOFFSET                     0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPEUNIFBW_EMEM_ACTIVITY_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPEUNIFBW_EMEM_ACTIVITY_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPEUNIFBW_EMEM_ACTIVITY_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPEUNIFBW_EMEM_ACTIVITY_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPEUNIFBW_EMEM_ACTIVITY_INIT_ENUM                   DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPEUNIFBW_EMEM_ACTIVITY_INACTIVE                    _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPEUNIFBW_EMEM_ACTIVITY_ACTIVE                      _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWSB_EMEM_ACTIVITY_SHIFT                   _MK_SHIFT_CONST(4)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWSB_EMEM_ACTIVITY_FIELD                   (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWSB_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWSB_EMEM_ACTIVITY_RANGE                   4:4
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWSB_EMEM_ACTIVITY_WOFFSET                 0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWSB_EMEM_ACTIVITY_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWSB_EMEM_ACTIVITY_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWSB_EMEM_ACTIVITY_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWSB_EMEM_ACTIVITY_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWSB_EMEM_ACTIVITY_INIT_ENUM                       DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWSB_EMEM_ACTIVITY_INACTIVE                        _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWSB_EMEM_ACTIVITY_ACTIVE                  _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWU_EMEM_ACTIVITY_SHIFT                    _MK_SHIFT_CONST(5)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWU_EMEM_ACTIVITY_FIELD                    (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWU_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWU_EMEM_ACTIVITY_RANGE                    5:5
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWU_EMEM_ACTIVITY_WOFFSET                  0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWU_EMEM_ACTIVITY_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWU_EMEM_ACTIVITY_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWU_EMEM_ACTIVITY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWU_EMEM_ACTIVITY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWU_EMEM_ACTIVITY_INIT_ENUM                        DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWU_EMEM_ACTIVITY_INACTIVE                 _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWU_EMEM_ACTIVITY_ACTIVE                   _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWV_EMEM_ACTIVITY_SHIFT                    _MK_SHIFT_CONST(6)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWV_EMEM_ACTIVITY_FIELD                    (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWV_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWV_EMEM_ACTIVITY_RANGE                    6:6
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWV_EMEM_ACTIVITY_WOFFSET                  0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWV_EMEM_ACTIVITY_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWV_EMEM_ACTIVITY_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWV_EMEM_ACTIVITY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWV_EMEM_ACTIVITY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWV_EMEM_ACTIVITY_INIT_ENUM                        DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWV_EMEM_ACTIVITY_INACTIVE                 _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWV_EMEM_ACTIVITY_ACTIVE                   _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWY_EMEM_ACTIVITY_SHIFT                    _MK_SHIFT_CONST(7)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWY_EMEM_ACTIVITY_FIELD                    (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWY_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWY_EMEM_ACTIVITY_RANGE                    7:7
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWY_EMEM_ACTIVITY_WOFFSET                  0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWY_EMEM_ACTIVITY_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWY_EMEM_ACTIVITY_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWY_EMEM_ACTIVITY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWY_EMEM_ACTIVITY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWY_EMEM_ACTIVITY_INIT_ENUM                        DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWY_EMEM_ACTIVITY_INACTIVE                 _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWY_EMEM_ACTIVITY_ACTIVE                   _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_G2DW_EMEM_ACTIVITY_SHIFT                    _MK_SHIFT_CONST(8)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_G2DW_EMEM_ACTIVITY_FIELD                    (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_G2DW_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_G2DW_EMEM_ACTIVITY_RANGE                    8:8
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_G2DW_EMEM_ACTIVITY_WOFFSET                  0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_G2DW_EMEM_ACTIVITY_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_G2DW_EMEM_ACTIVITY_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_G2DW_EMEM_ACTIVITY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_G2DW_EMEM_ACTIVITY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_G2DW_EMEM_ACTIVITY_INIT_ENUM                        DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_G2DW_EMEM_ACTIVITY_INACTIVE                 _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_G2DW_EMEM_ACTIVITY_ACTIVE                   _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_AVPCARM7W_EMEM_ACTIVITY_SHIFT                       _MK_SHIFT_CONST(9)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_AVPCARM7W_EMEM_ACTIVITY_FIELD                       (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_AVPCARM7W_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_AVPCARM7W_EMEM_ACTIVITY_RANGE                       9:9
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_AVPCARM7W_EMEM_ACTIVITY_WOFFSET                     0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_AVPCARM7W_EMEM_ACTIVITY_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_AVPCARM7W_EMEM_ACTIVITY_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_AVPCARM7W_EMEM_ACTIVITY_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_AVPCARM7W_EMEM_ACTIVITY_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_AVPCARM7W_EMEM_ACTIVITY_INIT_ENUM                   DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_AVPCARM7W_EMEM_ACTIVITY_INACTIVE                    _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_AVPCARM7W_EMEM_ACTIVITY_ACTIVE                      _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_FDCDWR_EMEM_ACTIVITY_SHIFT                  _MK_SHIFT_CONST(10)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_FDCDWR_EMEM_ACTIVITY_FIELD                  (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_FDCDWR_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_FDCDWR_EMEM_ACTIVITY_RANGE                  10:10
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_FDCDWR_EMEM_ACTIVITY_WOFFSET                        0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_FDCDWR_EMEM_ACTIVITY_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_FDCDWR_EMEM_ACTIVITY_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_FDCDWR_EMEM_ACTIVITY_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_FDCDWR_EMEM_ACTIVITY_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_FDCDWR_EMEM_ACTIVITY_INIT_ENUM                      DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_FDCDWR_EMEM_ACTIVITY_INACTIVE                       _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_FDCDWR_EMEM_ACTIVITY_ACTIVE                 _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_HOST1XW_EMEM_ACTIVITY_SHIFT                 _MK_SHIFT_CONST(11)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_HOST1XW_EMEM_ACTIVITY_FIELD                 (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_HOST1XW_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_HOST1XW_EMEM_ACTIVITY_RANGE                 11:11
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_HOST1XW_EMEM_ACTIVITY_WOFFSET                       0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_HOST1XW_EMEM_ACTIVITY_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_HOST1XW_EMEM_ACTIVITY_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_HOST1XW_EMEM_ACTIVITY_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_HOST1XW_EMEM_ACTIVITY_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_HOST1XW_EMEM_ACTIVITY_INIT_ENUM                     DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_HOST1XW_EMEM_ACTIVITY_INACTIVE                      _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_HOST1XW_EMEM_ACTIVITY_ACTIVE                        _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_ISPW_EMEM_ACTIVITY_SHIFT                    _MK_SHIFT_CONST(12)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_ISPW_EMEM_ACTIVITY_FIELD                    (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_ISPW_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_ISPW_EMEM_ACTIVITY_RANGE                    12:12
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_ISPW_EMEM_ACTIVITY_WOFFSET                  0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_ISPW_EMEM_ACTIVITY_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_ISPW_EMEM_ACTIVITY_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_ISPW_EMEM_ACTIVITY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_ISPW_EMEM_ACTIVITY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_ISPW_EMEM_ACTIVITY_INIT_ENUM                        DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_ISPW_EMEM_ACTIVITY_INACTIVE                 _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_ISPW_EMEM_ACTIVITY_ACTIVE                   _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPCOREW_EMEM_ACTIVITY_SHIFT                 _MK_SHIFT_CONST(13)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPCOREW_EMEM_ACTIVITY_FIELD                 (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPCOREW_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPCOREW_EMEM_ACTIVITY_RANGE                 13:13
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPCOREW_EMEM_ACTIVITY_WOFFSET                       0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPCOREW_EMEM_ACTIVITY_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPCOREW_EMEM_ACTIVITY_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPCOREW_EMEM_ACTIVITY_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPCOREW_EMEM_ACTIVITY_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPCOREW_EMEM_ACTIVITY_INIT_ENUM                     DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPCOREW_EMEM_ACTIVITY_INACTIVE                      _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPCOREW_EMEM_ACTIVITY_ACTIVE                        _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPECSWR_EMEM_ACTIVITY_SHIFT                 _MK_SHIFT_CONST(14)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPECSWR_EMEM_ACTIVITY_FIELD                 (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPECSWR_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPECSWR_EMEM_ACTIVITY_RANGE                 14:14
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPECSWR_EMEM_ACTIVITY_WOFFSET                       0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPECSWR_EMEM_ACTIVITY_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPECSWR_EMEM_ACTIVITY_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPECSWR_EMEM_ACTIVITY_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPECSWR_EMEM_ACTIVITY_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPECSWR_EMEM_ACTIVITY_INIT_ENUM                     DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPECSWR_EMEM_ACTIVITY_INACTIVE                      _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPECSWR_EMEM_ACTIVITY_ACTIVE                        _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_PPCSAHBDMAW_EMEM_ACTIVITY_SHIFT                     _MK_SHIFT_CONST(15)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_PPCSAHBDMAW_EMEM_ACTIVITY_FIELD                     (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_PPCSAHBDMAW_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_PPCSAHBDMAW_EMEM_ACTIVITY_RANGE                     15:15
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_PPCSAHBDMAW_EMEM_ACTIVITY_WOFFSET                   0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_PPCSAHBDMAW_EMEM_ACTIVITY_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_PPCSAHBDMAW_EMEM_ACTIVITY_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_PPCSAHBDMAW_EMEM_ACTIVITY_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_PPCSAHBDMAW_EMEM_ACTIVITY_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_PPCSAHBDMAW_EMEM_ACTIVITY_INIT_ENUM                 DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_PPCSAHBDMAW_EMEM_ACTIVITY_INACTIVE                  _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_PPCSAHBDMAW_EMEM_ACTIVITY_ACTIVE                    _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_PPCSAHBSLVW_EMEM_ACTIVITY_SHIFT                     _MK_SHIFT_CONST(16)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_PPCSAHBSLVW_EMEM_ACTIVITY_FIELD                     (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_PPCSAHBSLVW_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_PPCSAHBSLVW_EMEM_ACTIVITY_RANGE                     16:16
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_PPCSAHBSLVW_EMEM_ACTIVITY_WOFFSET                   0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_PPCSAHBSLVW_EMEM_ACTIVITY_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_PPCSAHBSLVW_EMEM_ACTIVITY_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_PPCSAHBSLVW_EMEM_ACTIVITY_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_PPCSAHBSLVW_EMEM_ACTIVITY_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_PPCSAHBSLVW_EMEM_ACTIVITY_INIT_ENUM                 DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_PPCSAHBSLVW_EMEM_ACTIVITY_INACTIVE                  _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_PPCSAHBSLVW_EMEM_ACTIVITY_ACTIVE                    _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEBSEVW_EMEM_ACTIVITY_SHIFT                        _MK_SHIFT_CONST(17)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEBSEVW_EMEM_ACTIVITY_FIELD                        (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEBSEVW_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEBSEVW_EMEM_ACTIVITY_RANGE                        17:17
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEBSEVW_EMEM_ACTIVITY_WOFFSET                      0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEBSEVW_EMEM_ACTIVITY_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEBSEVW_EMEM_ACTIVITY_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEBSEVW_EMEM_ACTIVITY_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEBSEVW_EMEM_ACTIVITY_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEBSEVW_EMEM_ACTIVITY_INIT_ENUM                    DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEBSEVW_EMEM_ACTIVITY_INACTIVE                     _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEBSEVW_EMEM_ACTIVITY_ACTIVE                       _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEMBEW_EMEM_ACTIVITY_SHIFT                 _MK_SHIFT_CONST(18)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEMBEW_EMEM_ACTIVITY_FIELD                 (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEMBEW_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEMBEW_EMEM_ACTIVITY_RANGE                 18:18
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEMBEW_EMEM_ACTIVITY_WOFFSET                       0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEMBEW_EMEM_ACTIVITY_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEMBEW_EMEM_ACTIVITY_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEMBEW_EMEM_ACTIVITY_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEMBEW_EMEM_ACTIVITY_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEMBEW_EMEM_ACTIVITY_INIT_ENUM                     DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEMBEW_EMEM_ACTIVITY_INACTIVE                      _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEMBEW_EMEM_ACTIVITY_ACTIVE                        _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDETPMW_EMEM_ACTIVITY_SHIFT                 _MK_SHIFT_CONST(19)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDETPMW_EMEM_ACTIVITY_FIELD                 (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDETPMW_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDETPMW_EMEM_ACTIVITY_RANGE                 19:19
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDETPMW_EMEM_ACTIVITY_WOFFSET                       0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDETPMW_EMEM_ACTIVITY_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDETPMW_EMEM_ACTIVITY_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDETPMW_EMEM_ACTIVITY_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDETPMW_EMEM_ACTIVITY_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDETPMW_EMEM_ACTIVITY_INIT_ENUM                     DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDETPMW_EMEM_ACTIVITY_INACTIVE                      _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDETPMW_EMEM_ACTIVITY_ACTIVE                        _MK_ENUM_CONST(1)
+
+
+// Register MC_AVPC_ORRC_0  
+#define MC_AVPC_ORRC_0                  _MK_ADDR_CONST(0x140)
+#define MC_AVPC_ORRC_0_SECURE                   0x0
+#define MC_AVPC_ORRC_0_WORD_COUNT                       0x1
+#define MC_AVPC_ORRC_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define MC_AVPC_ORRC_0_RESET_MASK                       _MK_MASK_CONST(0xff)
+#define MC_AVPC_ORRC_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define MC_AVPC_ORRC_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_AVPC_ORRC_0_READ_MASK                        _MK_MASK_CONST(0xff)
+#define MC_AVPC_ORRC_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
+#define MC_AVPC_ORRC_0_AVPC_OUTREQCNT_SHIFT                     _MK_SHIFT_CONST(0)
+#define MC_AVPC_ORRC_0_AVPC_OUTREQCNT_FIELD                     (_MK_MASK_CONST(0xff) << MC_AVPC_ORRC_0_AVPC_OUTREQCNT_SHIFT)
+#define MC_AVPC_ORRC_0_AVPC_OUTREQCNT_RANGE                     7:0
+#define MC_AVPC_ORRC_0_AVPC_OUTREQCNT_WOFFSET                   0x0
+#define MC_AVPC_ORRC_0_AVPC_OUTREQCNT_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_AVPC_ORRC_0_AVPC_OUTREQCNT_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define MC_AVPC_ORRC_0_AVPC_OUTREQCNT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_AVPC_ORRC_0_AVPC_OUTREQCNT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register MC_DC_ORRC_0  
+#define MC_DC_ORRC_0                    _MK_ADDR_CONST(0x144)
+#define MC_DC_ORRC_0_SECURE                     0x0
+#define MC_DC_ORRC_0_WORD_COUNT                         0x1
+#define MC_DC_ORRC_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define MC_DC_ORRC_0_RESET_MASK                         _MK_MASK_CONST(0xff)
+#define MC_DC_ORRC_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define MC_DC_ORRC_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_DC_ORRC_0_READ_MASK                  _MK_MASK_CONST(0xff)
+#define MC_DC_ORRC_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
+#define MC_DC_ORRC_0_DC_OUTREQCNT_SHIFT                 _MK_SHIFT_CONST(0)
+#define MC_DC_ORRC_0_DC_OUTREQCNT_FIELD                 (_MK_MASK_CONST(0xff) << MC_DC_ORRC_0_DC_OUTREQCNT_SHIFT)
+#define MC_DC_ORRC_0_DC_OUTREQCNT_RANGE                 7:0
+#define MC_DC_ORRC_0_DC_OUTREQCNT_WOFFSET                       0x0
+#define MC_DC_ORRC_0_DC_OUTREQCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_DC_ORRC_0_DC_OUTREQCNT_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define MC_DC_ORRC_0_DC_OUTREQCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_DC_ORRC_0_DC_OUTREQCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register MC_DCB_ORRC_0  
+#define MC_DCB_ORRC_0                   _MK_ADDR_CONST(0x148)
+#define MC_DCB_ORRC_0_SECURE                    0x0
+#define MC_DCB_ORRC_0_WORD_COUNT                        0x1
+#define MC_DCB_ORRC_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define MC_DCB_ORRC_0_RESET_MASK                        _MK_MASK_CONST(0xff)
+#define MC_DCB_ORRC_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define MC_DCB_ORRC_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_DCB_ORRC_0_READ_MASK                         _MK_MASK_CONST(0xff)
+#define MC_DCB_ORRC_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+#define MC_DCB_ORRC_0_DCB_OUTREQCNT_SHIFT                       _MK_SHIFT_CONST(0)
+#define MC_DCB_ORRC_0_DCB_OUTREQCNT_FIELD                       (_MK_MASK_CONST(0xff) << MC_DCB_ORRC_0_DCB_OUTREQCNT_SHIFT)
+#define MC_DCB_ORRC_0_DCB_OUTREQCNT_RANGE                       7:0
+#define MC_DCB_ORRC_0_DCB_OUTREQCNT_WOFFSET                     0x0
+#define MC_DCB_ORRC_0_DCB_OUTREQCNT_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_DCB_ORRC_0_DCB_OUTREQCNT_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define MC_DCB_ORRC_0_DCB_OUTREQCNT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_DCB_ORRC_0_DCB_OUTREQCNT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register MC_EPP_ORRC_0  
+#define MC_EPP_ORRC_0                   _MK_ADDR_CONST(0x14c)
+#define MC_EPP_ORRC_0_SECURE                    0x0
+#define MC_EPP_ORRC_0_WORD_COUNT                        0x1
+#define MC_EPP_ORRC_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define MC_EPP_ORRC_0_RESET_MASK                        _MK_MASK_CONST(0xff)
+#define MC_EPP_ORRC_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define MC_EPP_ORRC_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_EPP_ORRC_0_READ_MASK                         _MK_MASK_CONST(0xff)
+#define MC_EPP_ORRC_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+#define MC_EPP_ORRC_0_EPP_OUTREQCNT_SHIFT                       _MK_SHIFT_CONST(0)
+#define MC_EPP_ORRC_0_EPP_OUTREQCNT_FIELD                       (_MK_MASK_CONST(0xff) << MC_EPP_ORRC_0_EPP_OUTREQCNT_SHIFT)
+#define MC_EPP_ORRC_0_EPP_OUTREQCNT_RANGE                       7:0
+#define MC_EPP_ORRC_0_EPP_OUTREQCNT_WOFFSET                     0x0
+#define MC_EPP_ORRC_0_EPP_OUTREQCNT_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_EPP_ORRC_0_EPP_OUTREQCNT_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define MC_EPP_ORRC_0_EPP_OUTREQCNT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_EPP_ORRC_0_EPP_OUTREQCNT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register MC_G2_ORRC_0  
+#define MC_G2_ORRC_0                    _MK_ADDR_CONST(0x150)
+#define MC_G2_ORRC_0_SECURE                     0x0
+#define MC_G2_ORRC_0_WORD_COUNT                         0x1
+#define MC_G2_ORRC_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define MC_G2_ORRC_0_RESET_MASK                         _MK_MASK_CONST(0xff)
+#define MC_G2_ORRC_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define MC_G2_ORRC_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_G2_ORRC_0_READ_MASK                  _MK_MASK_CONST(0xff)
+#define MC_G2_ORRC_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
+#define MC_G2_ORRC_0_G2_OUTREQCNT_SHIFT                 _MK_SHIFT_CONST(0)
+#define MC_G2_ORRC_0_G2_OUTREQCNT_FIELD                 (_MK_MASK_CONST(0xff) << MC_G2_ORRC_0_G2_OUTREQCNT_SHIFT)
+#define MC_G2_ORRC_0_G2_OUTREQCNT_RANGE                 7:0
+#define MC_G2_ORRC_0_G2_OUTREQCNT_WOFFSET                       0x0
+#define MC_G2_ORRC_0_G2_OUTREQCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_G2_ORRC_0_G2_OUTREQCNT_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define MC_G2_ORRC_0_G2_OUTREQCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_G2_ORRC_0_G2_OUTREQCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register MC_HC_ORRC_0  
+#define MC_HC_ORRC_0                    _MK_ADDR_CONST(0x154)
+#define MC_HC_ORRC_0_SECURE                     0x0
+#define MC_HC_ORRC_0_WORD_COUNT                         0x1
+#define MC_HC_ORRC_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define MC_HC_ORRC_0_RESET_MASK                         _MK_MASK_CONST(0xff)
+#define MC_HC_ORRC_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define MC_HC_ORRC_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_HC_ORRC_0_READ_MASK                  _MK_MASK_CONST(0xff)
+#define MC_HC_ORRC_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
+#define MC_HC_ORRC_0_HC_OUTREQCNT_SHIFT                 _MK_SHIFT_CONST(0)
+#define MC_HC_ORRC_0_HC_OUTREQCNT_FIELD                 (_MK_MASK_CONST(0xff) << MC_HC_ORRC_0_HC_OUTREQCNT_SHIFT)
+#define MC_HC_ORRC_0_HC_OUTREQCNT_RANGE                 7:0
+#define MC_HC_ORRC_0_HC_OUTREQCNT_WOFFSET                       0x0
+#define MC_HC_ORRC_0_HC_OUTREQCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_HC_ORRC_0_HC_OUTREQCNT_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define MC_HC_ORRC_0_HC_OUTREQCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_HC_ORRC_0_HC_OUTREQCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register MC_ISP_ORRC_0  
+#define MC_ISP_ORRC_0                   _MK_ADDR_CONST(0x158)
+#define MC_ISP_ORRC_0_SECURE                    0x0
+#define MC_ISP_ORRC_0_WORD_COUNT                        0x1
+#define MC_ISP_ORRC_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define MC_ISP_ORRC_0_RESET_MASK                        _MK_MASK_CONST(0xff)
+#define MC_ISP_ORRC_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define MC_ISP_ORRC_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_ISP_ORRC_0_READ_MASK                         _MK_MASK_CONST(0xff)
+#define MC_ISP_ORRC_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+#define MC_ISP_ORRC_0_ISP_OUTREQCNT_SHIFT                       _MK_SHIFT_CONST(0)
+#define MC_ISP_ORRC_0_ISP_OUTREQCNT_FIELD                       (_MK_MASK_CONST(0xff) << MC_ISP_ORRC_0_ISP_OUTREQCNT_SHIFT)
+#define MC_ISP_ORRC_0_ISP_OUTREQCNT_RANGE                       7:0
+#define MC_ISP_ORRC_0_ISP_OUTREQCNT_WOFFSET                     0x0
+#define MC_ISP_ORRC_0_ISP_OUTREQCNT_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_ISP_ORRC_0_ISP_OUTREQCNT_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define MC_ISP_ORRC_0_ISP_OUTREQCNT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_ISP_ORRC_0_ISP_OUTREQCNT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register MC_MPCORE_ORRC_0  
+#define MC_MPCORE_ORRC_0                        _MK_ADDR_CONST(0x15c)
+#define MC_MPCORE_ORRC_0_SECURE                         0x0
+#define MC_MPCORE_ORRC_0_WORD_COUNT                     0x1
+#define MC_MPCORE_ORRC_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define MC_MPCORE_ORRC_0_RESET_MASK                     _MK_MASK_CONST(0xff)
+#define MC_MPCORE_ORRC_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define MC_MPCORE_ORRC_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_MPCORE_ORRC_0_READ_MASK                      _MK_MASK_CONST(0xff)
+#define MC_MPCORE_ORRC_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
+#define MC_MPCORE_ORRC_0_MPCORE_OUTREQCNT_SHIFT                 _MK_SHIFT_CONST(0)
+#define MC_MPCORE_ORRC_0_MPCORE_OUTREQCNT_FIELD                 (_MK_MASK_CONST(0xff) << MC_MPCORE_ORRC_0_MPCORE_OUTREQCNT_SHIFT)
+#define MC_MPCORE_ORRC_0_MPCORE_OUTREQCNT_RANGE                 7:0
+#define MC_MPCORE_ORRC_0_MPCORE_OUTREQCNT_WOFFSET                       0x0
+#define MC_MPCORE_ORRC_0_MPCORE_OUTREQCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_MPCORE_ORRC_0_MPCORE_OUTREQCNT_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define MC_MPCORE_ORRC_0_MPCORE_OUTREQCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_MPCORE_ORRC_0_MPCORE_OUTREQCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register MC_MPEA_ORRC_0  
+#define MC_MPEA_ORRC_0                  _MK_ADDR_CONST(0x160)
+#define MC_MPEA_ORRC_0_SECURE                   0x0
+#define MC_MPEA_ORRC_0_WORD_COUNT                       0x1
+#define MC_MPEA_ORRC_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define MC_MPEA_ORRC_0_RESET_MASK                       _MK_MASK_CONST(0xff)
+#define MC_MPEA_ORRC_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define MC_MPEA_ORRC_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_MPEA_ORRC_0_READ_MASK                        _MK_MASK_CONST(0xff)
+#define MC_MPEA_ORRC_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
+#define MC_MPEA_ORRC_0_MPEA_OUTREQCNT_SHIFT                     _MK_SHIFT_CONST(0)
+#define MC_MPEA_ORRC_0_MPEA_OUTREQCNT_FIELD                     (_MK_MASK_CONST(0xff) << MC_MPEA_ORRC_0_MPEA_OUTREQCNT_SHIFT)
+#define MC_MPEA_ORRC_0_MPEA_OUTREQCNT_RANGE                     7:0
+#define MC_MPEA_ORRC_0_MPEA_OUTREQCNT_WOFFSET                   0x0
+#define MC_MPEA_ORRC_0_MPEA_OUTREQCNT_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_MPEA_ORRC_0_MPEA_OUTREQCNT_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define MC_MPEA_ORRC_0_MPEA_OUTREQCNT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_MPEA_ORRC_0_MPEA_OUTREQCNT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register MC_MPEB_ORRC_0  
+#define MC_MPEB_ORRC_0                  _MK_ADDR_CONST(0x164)
+#define MC_MPEB_ORRC_0_SECURE                   0x0
+#define MC_MPEB_ORRC_0_WORD_COUNT                       0x1
+#define MC_MPEB_ORRC_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define MC_MPEB_ORRC_0_RESET_MASK                       _MK_MASK_CONST(0xff)
+#define MC_MPEB_ORRC_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define MC_MPEB_ORRC_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_MPEB_ORRC_0_READ_MASK                        _MK_MASK_CONST(0xff)
+#define MC_MPEB_ORRC_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
+#define MC_MPEB_ORRC_0_MPEB_OUTREQCNT_SHIFT                     _MK_SHIFT_CONST(0)
+#define MC_MPEB_ORRC_0_MPEB_OUTREQCNT_FIELD                     (_MK_MASK_CONST(0xff) << MC_MPEB_ORRC_0_MPEB_OUTREQCNT_SHIFT)
+#define MC_MPEB_ORRC_0_MPEB_OUTREQCNT_RANGE                     7:0
+#define MC_MPEB_ORRC_0_MPEB_OUTREQCNT_WOFFSET                   0x0
+#define MC_MPEB_ORRC_0_MPEB_OUTREQCNT_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_MPEB_ORRC_0_MPEB_OUTREQCNT_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define MC_MPEB_ORRC_0_MPEB_OUTREQCNT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_MPEB_ORRC_0_MPEB_OUTREQCNT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register MC_MPEC_ORRC_0  
+#define MC_MPEC_ORRC_0                  _MK_ADDR_CONST(0x168)
+#define MC_MPEC_ORRC_0_SECURE                   0x0
+#define MC_MPEC_ORRC_0_WORD_COUNT                       0x1
+#define MC_MPEC_ORRC_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define MC_MPEC_ORRC_0_RESET_MASK                       _MK_MASK_CONST(0xff)
+#define MC_MPEC_ORRC_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define MC_MPEC_ORRC_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_MPEC_ORRC_0_READ_MASK                        _MK_MASK_CONST(0xff)
+#define MC_MPEC_ORRC_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
+#define MC_MPEC_ORRC_0_MPEC_OUTREQCNT_SHIFT                     _MK_SHIFT_CONST(0)
+#define MC_MPEC_ORRC_0_MPEC_OUTREQCNT_FIELD                     (_MK_MASK_CONST(0xff) << MC_MPEC_ORRC_0_MPEC_OUTREQCNT_SHIFT)
+#define MC_MPEC_ORRC_0_MPEC_OUTREQCNT_RANGE                     7:0
+#define MC_MPEC_ORRC_0_MPEC_OUTREQCNT_WOFFSET                   0x0
+#define MC_MPEC_ORRC_0_MPEC_OUTREQCNT_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_MPEC_ORRC_0_MPEC_OUTREQCNT_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define MC_MPEC_ORRC_0_MPEC_OUTREQCNT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_MPEC_ORRC_0_MPEC_OUTREQCNT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register MC_NV_ORRC_0  
+#define MC_NV_ORRC_0                    _MK_ADDR_CONST(0x16c)
+#define MC_NV_ORRC_0_SECURE                     0x0
+#define MC_NV_ORRC_0_WORD_COUNT                         0x1
+#define MC_NV_ORRC_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define MC_NV_ORRC_0_RESET_MASK                         _MK_MASK_CONST(0xff)
+#define MC_NV_ORRC_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define MC_NV_ORRC_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_NV_ORRC_0_READ_MASK                  _MK_MASK_CONST(0xff)
+#define MC_NV_ORRC_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
+#define MC_NV_ORRC_0_NV_OUTREQCNT_SHIFT                 _MK_SHIFT_CONST(0)
+#define MC_NV_ORRC_0_NV_OUTREQCNT_FIELD                 (_MK_MASK_CONST(0xff) << MC_NV_ORRC_0_NV_OUTREQCNT_SHIFT)
+#define MC_NV_ORRC_0_NV_OUTREQCNT_RANGE                 7:0
+#define MC_NV_ORRC_0_NV_OUTREQCNT_WOFFSET                       0x0
+#define MC_NV_ORRC_0_NV_OUTREQCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_NV_ORRC_0_NV_OUTREQCNT_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define MC_NV_ORRC_0_NV_OUTREQCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_NV_ORRC_0_NV_OUTREQCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register MC_PPCS_ORRC_0  
+#define MC_PPCS_ORRC_0                  _MK_ADDR_CONST(0x170)
+#define MC_PPCS_ORRC_0_SECURE                   0x0
+#define MC_PPCS_ORRC_0_WORD_COUNT                       0x1
+#define MC_PPCS_ORRC_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define MC_PPCS_ORRC_0_RESET_MASK                       _MK_MASK_CONST(0xff)
+#define MC_PPCS_ORRC_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define MC_PPCS_ORRC_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_PPCS_ORRC_0_READ_MASK                        _MK_MASK_CONST(0xff)
+#define MC_PPCS_ORRC_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
+#define MC_PPCS_ORRC_0_PPCS_OUTREQCNT_SHIFT                     _MK_SHIFT_CONST(0)
+#define MC_PPCS_ORRC_0_PPCS_OUTREQCNT_FIELD                     (_MK_MASK_CONST(0xff) << MC_PPCS_ORRC_0_PPCS_OUTREQCNT_SHIFT)
+#define MC_PPCS_ORRC_0_PPCS_OUTREQCNT_RANGE                     7:0
+#define MC_PPCS_ORRC_0_PPCS_OUTREQCNT_WOFFSET                   0x0
+#define MC_PPCS_ORRC_0_PPCS_OUTREQCNT_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_PPCS_ORRC_0_PPCS_OUTREQCNT_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define MC_PPCS_ORRC_0_PPCS_OUTREQCNT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_PPCS_ORRC_0_PPCS_OUTREQCNT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register MC_VDE_ORRC_0  
+#define MC_VDE_ORRC_0                   _MK_ADDR_CONST(0x174)
+#define MC_VDE_ORRC_0_SECURE                    0x0
+#define MC_VDE_ORRC_0_WORD_COUNT                        0x1
+#define MC_VDE_ORRC_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define MC_VDE_ORRC_0_RESET_MASK                        _MK_MASK_CONST(0xff)
+#define MC_VDE_ORRC_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define MC_VDE_ORRC_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_VDE_ORRC_0_READ_MASK                         _MK_MASK_CONST(0xff)
+#define MC_VDE_ORRC_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+#define MC_VDE_ORRC_0_VDE_OUTREQCNT_SHIFT                       _MK_SHIFT_CONST(0)
+#define MC_VDE_ORRC_0_VDE_OUTREQCNT_FIELD                       (_MK_MASK_CONST(0xff) << MC_VDE_ORRC_0_VDE_OUTREQCNT_SHIFT)
+#define MC_VDE_ORRC_0_VDE_OUTREQCNT_RANGE                       7:0
+#define MC_VDE_ORRC_0_VDE_OUTREQCNT_WOFFSET                     0x0
+#define MC_VDE_ORRC_0_VDE_OUTREQCNT_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_VDE_ORRC_0_VDE_OUTREQCNT_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define MC_VDE_ORRC_0_VDE_OUTREQCNT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_VDE_ORRC_0_VDE_OUTREQCNT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register MC_VI_ORRC_0  
+#define MC_VI_ORRC_0                    _MK_ADDR_CONST(0x178)
+#define MC_VI_ORRC_0_SECURE                     0x0
+#define MC_VI_ORRC_0_WORD_COUNT                         0x1
+#define MC_VI_ORRC_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define MC_VI_ORRC_0_RESET_MASK                         _MK_MASK_CONST(0xff)
+#define MC_VI_ORRC_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define MC_VI_ORRC_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_VI_ORRC_0_READ_MASK                  _MK_MASK_CONST(0xff)
+#define MC_VI_ORRC_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
+#define MC_VI_ORRC_0_VI_OUTREQCNT_SHIFT                 _MK_SHIFT_CONST(0)
+#define MC_VI_ORRC_0_VI_OUTREQCNT_FIELD                 (_MK_MASK_CONST(0xff) << MC_VI_ORRC_0_VI_OUTREQCNT_SHIFT)
+#define MC_VI_ORRC_0_VI_OUTREQCNT_RANGE                 7:0
+#define MC_VI_ORRC_0_VI_OUTREQCNT_WOFFSET                       0x0
+#define MC_VI_ORRC_0_VI_OUTREQCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_VI_ORRC_0_VI_OUTREQCNT_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define MC_VI_ORRC_0_VI_OUTREQCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_VI_ORRC_0_VI_OUTREQCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register MC_FPRI_CTRL_AVPC_0  
+#define MC_FPRI_CTRL_AVPC_0                     _MK_ADDR_CONST(0x17c)
+#define MC_FPRI_CTRL_AVPC_0_SECURE                      0x0
+#define MC_FPRI_CTRL_AVPC_0_WORD_COUNT                  0x1
+#define MC_FPRI_CTRL_AVPC_0_RESET_VAL                   _MK_MASK_CONST(0x5)
+#define MC_FPRI_CTRL_AVPC_0_RESET_MASK                  _MK_MASK_CONST(0xf)
+#define MC_FPRI_CTRL_AVPC_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_AVPC_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_AVPC_0_READ_MASK                   _MK_MASK_CONST(0xf)
+#define MC_FPRI_CTRL_AVPC_0_WRITE_MASK                  _MK_MASK_CONST(0xf)
+#define MC_FPRI_CTRL_AVPC_0_AVPCARM7R_PRIVAL_SHIFT                      _MK_SHIFT_CONST(0)
+#define MC_FPRI_CTRL_AVPC_0_AVPCARM7R_PRIVAL_FIELD                      (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_AVPC_0_AVPCARM7R_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_AVPC_0_AVPCARM7R_PRIVAL_RANGE                      1:0
+#define MC_FPRI_CTRL_AVPC_0_AVPCARM7R_PRIVAL_WOFFSET                    0x0
+#define MC_FPRI_CTRL_AVPC_0_AVPCARM7R_PRIVAL_DEFAULT                    _MK_MASK_CONST(0x1)
+#define MC_FPRI_CTRL_AVPC_0_AVPCARM7R_PRIVAL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_AVPC_0_AVPCARM7R_PRIVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_AVPC_0_AVPCARM7R_PRIVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_AVPC_0_AVPCARM7R_PRIVAL_INIT_ENUM                  LOW
+#define MC_FPRI_CTRL_AVPC_0_AVPCARM7R_PRIVAL_LOWEST                     _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_AVPC_0_AVPCARM7R_PRIVAL_LOW                        _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_AVPC_0_AVPCARM7R_PRIVAL_MED                        _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_AVPC_0_AVPCARM7R_PRIVAL_HIGH                       _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_AVPC_0_AVPCARM7W_PRIVAL_SHIFT                      _MK_SHIFT_CONST(2)
+#define MC_FPRI_CTRL_AVPC_0_AVPCARM7W_PRIVAL_FIELD                      (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_AVPC_0_AVPCARM7W_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_AVPC_0_AVPCARM7W_PRIVAL_RANGE                      3:2
+#define MC_FPRI_CTRL_AVPC_0_AVPCARM7W_PRIVAL_WOFFSET                    0x0
+#define MC_FPRI_CTRL_AVPC_0_AVPCARM7W_PRIVAL_DEFAULT                    _MK_MASK_CONST(0x1)
+#define MC_FPRI_CTRL_AVPC_0_AVPCARM7W_PRIVAL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_AVPC_0_AVPCARM7W_PRIVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_AVPC_0_AVPCARM7W_PRIVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_AVPC_0_AVPCARM7W_PRIVAL_INIT_ENUM                  LOW
+#define MC_FPRI_CTRL_AVPC_0_AVPCARM7W_PRIVAL_LOWEST                     _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_AVPC_0_AVPCARM7W_PRIVAL_LOW                        _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_AVPC_0_AVPCARM7W_PRIVAL_MED                        _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_AVPC_0_AVPCARM7W_PRIVAL_HIGH                       _MK_ENUM_CONST(3)
+
+
+// Register MC_FPRI_CTRL_DC_0  
+#define MC_FPRI_CTRL_DC_0                       _MK_ADDR_CONST(0x180)
+#define MC_FPRI_CTRL_DC_0_SECURE                        0x0
+#define MC_FPRI_CTRL_DC_0_WORD_COUNT                    0x1
+#define MC_FPRI_CTRL_DC_0_RESET_VAL                     _MK_MASK_CONST(0x155)
+#define MC_FPRI_CTRL_DC_0_RESET_MASK                    _MK_MASK_CONST(0x3ff)
+#define MC_FPRI_CTRL_DC_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_DC_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_DC_0_READ_MASK                     _MK_MASK_CONST(0x3ff)
+#define MC_FPRI_CTRL_DC_0_WRITE_MASK                    _MK_MASK_CONST(0x3ff)
+#define MC_FPRI_CTRL_DC_0_DISPLAY0A_PRIVAL_SHIFT                        _MK_SHIFT_CONST(0)
+#define MC_FPRI_CTRL_DC_0_DISPLAY0A_PRIVAL_FIELD                        (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_DC_0_DISPLAY0A_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_DC_0_DISPLAY0A_PRIVAL_RANGE                        1:0
+#define MC_FPRI_CTRL_DC_0_DISPLAY0A_PRIVAL_WOFFSET                      0x0
+#define MC_FPRI_CTRL_DC_0_DISPLAY0A_PRIVAL_DEFAULT                      _MK_MASK_CONST(0x1)
+#define MC_FPRI_CTRL_DC_0_DISPLAY0A_PRIVAL_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_DC_0_DISPLAY0A_PRIVAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_DC_0_DISPLAY0A_PRIVAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_DC_0_DISPLAY0A_PRIVAL_INIT_ENUM                    LOW
+#define MC_FPRI_CTRL_DC_0_DISPLAY0A_PRIVAL_LOWEST                       _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_DC_0_DISPLAY0A_PRIVAL_LOW                  _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_DC_0_DISPLAY0A_PRIVAL_MED                  _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_DC_0_DISPLAY0A_PRIVAL_HIGH                 _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_DC_0_DISPLAY0B_PRIVAL_SHIFT                        _MK_SHIFT_CONST(2)
+#define MC_FPRI_CTRL_DC_0_DISPLAY0B_PRIVAL_FIELD                        (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_DC_0_DISPLAY0B_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_DC_0_DISPLAY0B_PRIVAL_RANGE                        3:2
+#define MC_FPRI_CTRL_DC_0_DISPLAY0B_PRIVAL_WOFFSET                      0x0
+#define MC_FPRI_CTRL_DC_0_DISPLAY0B_PRIVAL_DEFAULT                      _MK_MASK_CONST(0x1)
+#define MC_FPRI_CTRL_DC_0_DISPLAY0B_PRIVAL_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_DC_0_DISPLAY0B_PRIVAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_DC_0_DISPLAY0B_PRIVAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_DC_0_DISPLAY0B_PRIVAL_INIT_ENUM                    LOW
+#define MC_FPRI_CTRL_DC_0_DISPLAY0B_PRIVAL_LOWEST                       _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_DC_0_DISPLAY0B_PRIVAL_LOW                  _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_DC_0_DISPLAY0B_PRIVAL_MED                  _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_DC_0_DISPLAY0B_PRIVAL_HIGH                 _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_DC_0_DISPLAY0C_PRIVAL_SHIFT                        _MK_SHIFT_CONST(4)
+#define MC_FPRI_CTRL_DC_0_DISPLAY0C_PRIVAL_FIELD                        (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_DC_0_DISPLAY0C_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_DC_0_DISPLAY0C_PRIVAL_RANGE                        5:4
+#define MC_FPRI_CTRL_DC_0_DISPLAY0C_PRIVAL_WOFFSET                      0x0
+#define MC_FPRI_CTRL_DC_0_DISPLAY0C_PRIVAL_DEFAULT                      _MK_MASK_CONST(0x1)
+#define MC_FPRI_CTRL_DC_0_DISPLAY0C_PRIVAL_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_DC_0_DISPLAY0C_PRIVAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_DC_0_DISPLAY0C_PRIVAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_DC_0_DISPLAY0C_PRIVAL_INIT_ENUM                    LOW
+#define MC_FPRI_CTRL_DC_0_DISPLAY0C_PRIVAL_LOWEST                       _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_DC_0_DISPLAY0C_PRIVAL_LOW                  _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_DC_0_DISPLAY0C_PRIVAL_MED                  _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_DC_0_DISPLAY0C_PRIVAL_HIGH                 _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_DC_0_DISPLAY1B_PRIVAL_SHIFT                        _MK_SHIFT_CONST(6)
+#define MC_FPRI_CTRL_DC_0_DISPLAY1B_PRIVAL_FIELD                        (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_DC_0_DISPLAY1B_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_DC_0_DISPLAY1B_PRIVAL_RANGE                        7:6
+#define MC_FPRI_CTRL_DC_0_DISPLAY1B_PRIVAL_WOFFSET                      0x0
+#define MC_FPRI_CTRL_DC_0_DISPLAY1B_PRIVAL_DEFAULT                      _MK_MASK_CONST(0x1)
+#define MC_FPRI_CTRL_DC_0_DISPLAY1B_PRIVAL_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_DC_0_DISPLAY1B_PRIVAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_DC_0_DISPLAY1B_PRIVAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_DC_0_DISPLAY1B_PRIVAL_INIT_ENUM                    LOW
+#define MC_FPRI_CTRL_DC_0_DISPLAY1B_PRIVAL_LOWEST                       _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_DC_0_DISPLAY1B_PRIVAL_LOW                  _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_DC_0_DISPLAY1B_PRIVAL_MED                  _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_DC_0_DISPLAY1B_PRIVAL_HIGH                 _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_DC_0_DISPLAYHC_PRIVAL_SHIFT                        _MK_SHIFT_CONST(8)
+#define MC_FPRI_CTRL_DC_0_DISPLAYHC_PRIVAL_FIELD                        (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_DC_0_DISPLAYHC_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_DC_0_DISPLAYHC_PRIVAL_RANGE                        9:8
+#define MC_FPRI_CTRL_DC_0_DISPLAYHC_PRIVAL_WOFFSET                      0x0
+#define MC_FPRI_CTRL_DC_0_DISPLAYHC_PRIVAL_DEFAULT                      _MK_MASK_CONST(0x1)
+#define MC_FPRI_CTRL_DC_0_DISPLAYHC_PRIVAL_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_DC_0_DISPLAYHC_PRIVAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_DC_0_DISPLAYHC_PRIVAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_DC_0_DISPLAYHC_PRIVAL_INIT_ENUM                    LOW
+#define MC_FPRI_CTRL_DC_0_DISPLAYHC_PRIVAL_LOWEST                       _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_DC_0_DISPLAYHC_PRIVAL_LOW                  _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_DC_0_DISPLAYHC_PRIVAL_MED                  _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_DC_0_DISPLAYHC_PRIVAL_HIGH                 _MK_ENUM_CONST(3)
+
+
+// Register MC_FPRI_CTRL_DCB_0  
+#define MC_FPRI_CTRL_DCB_0                      _MK_ADDR_CONST(0x184)
+#define MC_FPRI_CTRL_DCB_0_SECURE                       0x0
+#define MC_FPRI_CTRL_DCB_0_WORD_COUNT                   0x1
+#define MC_FPRI_CTRL_DCB_0_RESET_VAL                    _MK_MASK_CONST(0x155)
+#define MC_FPRI_CTRL_DCB_0_RESET_MASK                   _MK_MASK_CONST(0x3ff)
+#define MC_FPRI_CTRL_DCB_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_DCB_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_DCB_0_READ_MASK                    _MK_MASK_CONST(0x3ff)
+#define MC_FPRI_CTRL_DCB_0_WRITE_MASK                   _MK_MASK_CONST(0x3ff)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0AB_PRIVAL_SHIFT                      _MK_SHIFT_CONST(0)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0AB_PRIVAL_FIELD                      (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_DCB_0_DISPLAY0AB_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0AB_PRIVAL_RANGE                      1:0
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0AB_PRIVAL_WOFFSET                    0x0
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0AB_PRIVAL_DEFAULT                    _MK_MASK_CONST(0x1)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0AB_PRIVAL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0AB_PRIVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0AB_PRIVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0AB_PRIVAL_INIT_ENUM                  LOW
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0AB_PRIVAL_LOWEST                     _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0AB_PRIVAL_LOW                        _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0AB_PRIVAL_MED                        _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0AB_PRIVAL_HIGH                       _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0BB_PRIVAL_SHIFT                      _MK_SHIFT_CONST(2)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0BB_PRIVAL_FIELD                      (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_DCB_0_DISPLAY0BB_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0BB_PRIVAL_RANGE                      3:2
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0BB_PRIVAL_WOFFSET                    0x0
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0BB_PRIVAL_DEFAULT                    _MK_MASK_CONST(0x1)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0BB_PRIVAL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0BB_PRIVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0BB_PRIVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0BB_PRIVAL_INIT_ENUM                  LOW
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0BB_PRIVAL_LOWEST                     _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0BB_PRIVAL_LOW                        _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0BB_PRIVAL_MED                        _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0BB_PRIVAL_HIGH                       _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0CB_PRIVAL_SHIFT                      _MK_SHIFT_CONST(4)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0CB_PRIVAL_FIELD                      (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_DCB_0_DISPLAY0CB_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0CB_PRIVAL_RANGE                      5:4
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0CB_PRIVAL_WOFFSET                    0x0
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0CB_PRIVAL_DEFAULT                    _MK_MASK_CONST(0x1)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0CB_PRIVAL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0CB_PRIVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0CB_PRIVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0CB_PRIVAL_INIT_ENUM                  LOW
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0CB_PRIVAL_LOWEST                     _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0CB_PRIVAL_LOW                        _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0CB_PRIVAL_MED                        _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0CB_PRIVAL_HIGH                       _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_DCB_0_DISPLAY1BB_PRIVAL_SHIFT                      _MK_SHIFT_CONST(6)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY1BB_PRIVAL_FIELD                      (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_DCB_0_DISPLAY1BB_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY1BB_PRIVAL_RANGE                      7:6
+#define MC_FPRI_CTRL_DCB_0_DISPLAY1BB_PRIVAL_WOFFSET                    0x0
+#define MC_FPRI_CTRL_DCB_0_DISPLAY1BB_PRIVAL_DEFAULT                    _MK_MASK_CONST(0x1)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY1BB_PRIVAL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY1BB_PRIVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY1BB_PRIVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY1BB_PRIVAL_INIT_ENUM                  LOW
+#define MC_FPRI_CTRL_DCB_0_DISPLAY1BB_PRIVAL_LOWEST                     _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY1BB_PRIVAL_LOW                        _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY1BB_PRIVAL_MED                        _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY1BB_PRIVAL_HIGH                       _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_DCB_0_DISPLAYHCB_PRIVAL_SHIFT                      _MK_SHIFT_CONST(8)
+#define MC_FPRI_CTRL_DCB_0_DISPLAYHCB_PRIVAL_FIELD                      (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_DCB_0_DISPLAYHCB_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_DCB_0_DISPLAYHCB_PRIVAL_RANGE                      9:8
+#define MC_FPRI_CTRL_DCB_0_DISPLAYHCB_PRIVAL_WOFFSET                    0x0
+#define MC_FPRI_CTRL_DCB_0_DISPLAYHCB_PRIVAL_DEFAULT                    _MK_MASK_CONST(0x1)
+#define MC_FPRI_CTRL_DCB_0_DISPLAYHCB_PRIVAL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_DCB_0_DISPLAYHCB_PRIVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_DCB_0_DISPLAYHCB_PRIVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_DCB_0_DISPLAYHCB_PRIVAL_INIT_ENUM                  LOW
+#define MC_FPRI_CTRL_DCB_0_DISPLAYHCB_PRIVAL_LOWEST                     _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_DCB_0_DISPLAYHCB_PRIVAL_LOW                        _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_DCB_0_DISPLAYHCB_PRIVAL_MED                        _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_DCB_0_DISPLAYHCB_PRIVAL_HIGH                       _MK_ENUM_CONST(3)
+
+
+// Register MC_FPRI_CTRL_EPP_0  
+#define MC_FPRI_CTRL_EPP_0                      _MK_ADDR_CONST(0x188)
+#define MC_FPRI_CTRL_EPP_0_SECURE                       0x0
+#define MC_FPRI_CTRL_EPP_0_WORD_COUNT                   0x1
+#define MC_FPRI_CTRL_EPP_0_RESET_VAL                    _MK_MASK_CONST(0x55)
+#define MC_FPRI_CTRL_EPP_0_RESET_MASK                   _MK_MASK_CONST(0xff)
+#define MC_FPRI_CTRL_EPP_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_EPP_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_EPP_0_READ_MASK                    _MK_MASK_CONST(0xff)
+#define MC_FPRI_CTRL_EPP_0_WRITE_MASK                   _MK_MASK_CONST(0xff)
+#define MC_FPRI_CTRL_EPP_0_EPPUP_PRIVAL_SHIFT                   _MK_SHIFT_CONST(0)
+#define MC_FPRI_CTRL_EPP_0_EPPUP_PRIVAL_FIELD                   (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_EPP_0_EPPUP_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_EPP_0_EPPUP_PRIVAL_RANGE                   1:0
+#define MC_FPRI_CTRL_EPP_0_EPPUP_PRIVAL_WOFFSET                 0x0
+#define MC_FPRI_CTRL_EPP_0_EPPUP_PRIVAL_DEFAULT                 _MK_MASK_CONST(0x1)
+#define MC_FPRI_CTRL_EPP_0_EPPUP_PRIVAL_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_EPP_0_EPPUP_PRIVAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_EPP_0_EPPUP_PRIVAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_EPP_0_EPPUP_PRIVAL_INIT_ENUM                       LOW
+#define MC_FPRI_CTRL_EPP_0_EPPUP_PRIVAL_LOWEST                  _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_EPP_0_EPPUP_PRIVAL_LOW                     _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_EPP_0_EPPUP_PRIVAL_MED                     _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_EPP_0_EPPUP_PRIVAL_HIGH                    _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_EPP_0_EPPU_PRIVAL_SHIFT                    _MK_SHIFT_CONST(2)
+#define MC_FPRI_CTRL_EPP_0_EPPU_PRIVAL_FIELD                    (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_EPP_0_EPPU_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_EPP_0_EPPU_PRIVAL_RANGE                    3:2
+#define MC_FPRI_CTRL_EPP_0_EPPU_PRIVAL_WOFFSET                  0x0
+#define MC_FPRI_CTRL_EPP_0_EPPU_PRIVAL_DEFAULT                  _MK_MASK_CONST(0x1)
+#define MC_FPRI_CTRL_EPP_0_EPPU_PRIVAL_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_EPP_0_EPPU_PRIVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_EPP_0_EPPU_PRIVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_EPP_0_EPPU_PRIVAL_INIT_ENUM                        LOW
+#define MC_FPRI_CTRL_EPP_0_EPPU_PRIVAL_LOWEST                   _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_EPP_0_EPPU_PRIVAL_LOW                      _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_EPP_0_EPPU_PRIVAL_MED                      _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_EPP_0_EPPU_PRIVAL_HIGH                     _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_EPP_0_EPPV_PRIVAL_SHIFT                    _MK_SHIFT_CONST(4)
+#define MC_FPRI_CTRL_EPP_0_EPPV_PRIVAL_FIELD                    (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_EPP_0_EPPV_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_EPP_0_EPPV_PRIVAL_RANGE                    5:4
+#define MC_FPRI_CTRL_EPP_0_EPPV_PRIVAL_WOFFSET                  0x0
+#define MC_FPRI_CTRL_EPP_0_EPPV_PRIVAL_DEFAULT                  _MK_MASK_CONST(0x1)
+#define MC_FPRI_CTRL_EPP_0_EPPV_PRIVAL_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_EPP_0_EPPV_PRIVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_EPP_0_EPPV_PRIVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_EPP_0_EPPV_PRIVAL_INIT_ENUM                        LOW
+#define MC_FPRI_CTRL_EPP_0_EPPV_PRIVAL_LOWEST                   _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_EPP_0_EPPV_PRIVAL_LOW                      _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_EPP_0_EPPV_PRIVAL_MED                      _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_EPP_0_EPPV_PRIVAL_HIGH                     _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_EPP_0_EPPY_PRIVAL_SHIFT                    _MK_SHIFT_CONST(6)
+#define MC_FPRI_CTRL_EPP_0_EPPY_PRIVAL_FIELD                    (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_EPP_0_EPPY_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_EPP_0_EPPY_PRIVAL_RANGE                    7:6
+#define MC_FPRI_CTRL_EPP_0_EPPY_PRIVAL_WOFFSET                  0x0
+#define MC_FPRI_CTRL_EPP_0_EPPY_PRIVAL_DEFAULT                  _MK_MASK_CONST(0x1)
+#define MC_FPRI_CTRL_EPP_0_EPPY_PRIVAL_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_EPP_0_EPPY_PRIVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_EPP_0_EPPY_PRIVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_EPP_0_EPPY_PRIVAL_INIT_ENUM                        LOW
+#define MC_FPRI_CTRL_EPP_0_EPPY_PRIVAL_LOWEST                   _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_EPP_0_EPPY_PRIVAL_LOW                      _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_EPP_0_EPPY_PRIVAL_MED                      _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_EPP_0_EPPY_PRIVAL_HIGH                     _MK_ENUM_CONST(3)
+
+
+// Register MC_FPRI_CTRL_G2_0  
+#define MC_FPRI_CTRL_G2_0                       _MK_ADDR_CONST(0x18c)
+#define MC_FPRI_CTRL_G2_0_SECURE                        0x0
+#define MC_FPRI_CTRL_G2_0_WORD_COUNT                    0x1
+#define MC_FPRI_CTRL_G2_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_G2_0_RESET_MASK                    _MK_MASK_CONST(0xff)
+#define MC_FPRI_CTRL_G2_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_G2_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_G2_0_READ_MASK                     _MK_MASK_CONST(0xff)
+#define MC_FPRI_CTRL_G2_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
+#define MC_FPRI_CTRL_G2_0_G2PR_PRIVAL_SHIFT                     _MK_SHIFT_CONST(0)
+#define MC_FPRI_CTRL_G2_0_G2PR_PRIVAL_FIELD                     (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_G2_0_G2PR_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_G2_0_G2PR_PRIVAL_RANGE                     1:0
+#define MC_FPRI_CTRL_G2_0_G2PR_PRIVAL_WOFFSET                   0x0
+#define MC_FPRI_CTRL_G2_0_G2PR_PRIVAL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_G2_0_G2PR_PRIVAL_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_G2_0_G2PR_PRIVAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_G2_0_G2PR_PRIVAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_G2_0_G2PR_PRIVAL_INIT_ENUM                 LOWEST
+#define MC_FPRI_CTRL_G2_0_G2PR_PRIVAL_LOWEST                    _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_G2_0_G2PR_PRIVAL_LOW                       _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_G2_0_G2PR_PRIVAL_MED                       _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_G2_0_G2PR_PRIVAL_HIGH                      _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_G2_0_G2SR_PRIVAL_SHIFT                     _MK_SHIFT_CONST(2)
+#define MC_FPRI_CTRL_G2_0_G2SR_PRIVAL_FIELD                     (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_G2_0_G2SR_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_G2_0_G2SR_PRIVAL_RANGE                     3:2
+#define MC_FPRI_CTRL_G2_0_G2SR_PRIVAL_WOFFSET                   0x0
+#define MC_FPRI_CTRL_G2_0_G2SR_PRIVAL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_G2_0_G2SR_PRIVAL_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_G2_0_G2SR_PRIVAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_G2_0_G2SR_PRIVAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_G2_0_G2SR_PRIVAL_INIT_ENUM                 LOWEST
+#define MC_FPRI_CTRL_G2_0_G2SR_PRIVAL_LOWEST                    _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_G2_0_G2SR_PRIVAL_LOW                       _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_G2_0_G2SR_PRIVAL_MED                       _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_G2_0_G2SR_PRIVAL_HIGH                      _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_G2_0_G2DR_PRIVAL_SHIFT                     _MK_SHIFT_CONST(4)
+#define MC_FPRI_CTRL_G2_0_G2DR_PRIVAL_FIELD                     (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_G2_0_G2DR_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_G2_0_G2DR_PRIVAL_RANGE                     5:4
+#define MC_FPRI_CTRL_G2_0_G2DR_PRIVAL_WOFFSET                   0x0
+#define MC_FPRI_CTRL_G2_0_G2DR_PRIVAL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_G2_0_G2DR_PRIVAL_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_G2_0_G2DR_PRIVAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_G2_0_G2DR_PRIVAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_G2_0_G2DR_PRIVAL_INIT_ENUM                 LOWEST
+#define MC_FPRI_CTRL_G2_0_G2DR_PRIVAL_LOWEST                    _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_G2_0_G2DR_PRIVAL_LOW                       _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_G2_0_G2DR_PRIVAL_MED                       _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_G2_0_G2DR_PRIVAL_HIGH                      _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_G2_0_G2DW_PRIVAL_SHIFT                     _MK_SHIFT_CONST(6)
+#define MC_FPRI_CTRL_G2_0_G2DW_PRIVAL_FIELD                     (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_G2_0_G2DW_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_G2_0_G2DW_PRIVAL_RANGE                     7:6
+#define MC_FPRI_CTRL_G2_0_G2DW_PRIVAL_WOFFSET                   0x0
+#define MC_FPRI_CTRL_G2_0_G2DW_PRIVAL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_G2_0_G2DW_PRIVAL_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_G2_0_G2DW_PRIVAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_G2_0_G2DW_PRIVAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_G2_0_G2DW_PRIVAL_INIT_ENUM                 LOWEST
+#define MC_FPRI_CTRL_G2_0_G2DW_PRIVAL_LOWEST                    _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_G2_0_G2DW_PRIVAL_LOW                       _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_G2_0_G2DW_PRIVAL_MED                       _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_G2_0_G2DW_PRIVAL_HIGH                      _MK_ENUM_CONST(3)
+
+
+// Register MC_FPRI_CTRL_HC_0  
+#define MC_FPRI_CTRL_HC_0                       _MK_ADDR_CONST(0x190)
+#define MC_FPRI_CTRL_HC_0_SECURE                        0x0
+#define MC_FPRI_CTRL_HC_0_WORD_COUNT                    0x1
+#define MC_FPRI_CTRL_HC_0_RESET_VAL                     _MK_MASK_CONST(0x15)
+#define MC_FPRI_CTRL_HC_0_RESET_MASK                    _MK_MASK_CONST(0x3f)
+#define MC_FPRI_CTRL_HC_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_HC_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_HC_0_READ_MASK                     _MK_MASK_CONST(0x3f)
+#define MC_FPRI_CTRL_HC_0_WRITE_MASK                    _MK_MASK_CONST(0x3f)
+#define MC_FPRI_CTRL_HC_0_HOST1XDMAR_PRIVAL_SHIFT                       _MK_SHIFT_CONST(0)
+#define MC_FPRI_CTRL_HC_0_HOST1XDMAR_PRIVAL_FIELD                       (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_HC_0_HOST1XDMAR_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_HC_0_HOST1XDMAR_PRIVAL_RANGE                       1:0
+#define MC_FPRI_CTRL_HC_0_HOST1XDMAR_PRIVAL_WOFFSET                     0x0
+#define MC_FPRI_CTRL_HC_0_HOST1XDMAR_PRIVAL_DEFAULT                     _MK_MASK_CONST(0x1)
+#define MC_FPRI_CTRL_HC_0_HOST1XDMAR_PRIVAL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_HC_0_HOST1XDMAR_PRIVAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_HC_0_HOST1XDMAR_PRIVAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_HC_0_HOST1XDMAR_PRIVAL_INIT_ENUM                   LOW
+#define MC_FPRI_CTRL_HC_0_HOST1XDMAR_PRIVAL_LOWEST                      _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_HC_0_HOST1XDMAR_PRIVAL_LOW                 _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_HC_0_HOST1XDMAR_PRIVAL_MED                 _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_HC_0_HOST1XDMAR_PRIVAL_HIGH                        _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_HC_0_HOST1XR_PRIVAL_SHIFT                  _MK_SHIFT_CONST(2)
+#define MC_FPRI_CTRL_HC_0_HOST1XR_PRIVAL_FIELD                  (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_HC_0_HOST1XR_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_HC_0_HOST1XR_PRIVAL_RANGE                  3:2
+#define MC_FPRI_CTRL_HC_0_HOST1XR_PRIVAL_WOFFSET                        0x0
+#define MC_FPRI_CTRL_HC_0_HOST1XR_PRIVAL_DEFAULT                        _MK_MASK_CONST(0x1)
+#define MC_FPRI_CTRL_HC_0_HOST1XR_PRIVAL_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_HC_0_HOST1XR_PRIVAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_HC_0_HOST1XR_PRIVAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_HC_0_HOST1XR_PRIVAL_INIT_ENUM                      LOW
+#define MC_FPRI_CTRL_HC_0_HOST1XR_PRIVAL_LOWEST                 _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_HC_0_HOST1XR_PRIVAL_LOW                    _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_HC_0_HOST1XR_PRIVAL_MED                    _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_HC_0_HOST1XR_PRIVAL_HIGH                   _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_HC_0_HOST1XW_PRIVAL_SHIFT                  _MK_SHIFT_CONST(4)
+#define MC_FPRI_CTRL_HC_0_HOST1XW_PRIVAL_FIELD                  (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_HC_0_HOST1XW_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_HC_0_HOST1XW_PRIVAL_RANGE                  5:4
+#define MC_FPRI_CTRL_HC_0_HOST1XW_PRIVAL_WOFFSET                        0x0
+#define MC_FPRI_CTRL_HC_0_HOST1XW_PRIVAL_DEFAULT                        _MK_MASK_CONST(0x1)
+#define MC_FPRI_CTRL_HC_0_HOST1XW_PRIVAL_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_HC_0_HOST1XW_PRIVAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_HC_0_HOST1XW_PRIVAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_HC_0_HOST1XW_PRIVAL_INIT_ENUM                      LOW
+#define MC_FPRI_CTRL_HC_0_HOST1XW_PRIVAL_LOWEST                 _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_HC_0_HOST1XW_PRIVAL_LOW                    _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_HC_0_HOST1XW_PRIVAL_MED                    _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_HC_0_HOST1XW_PRIVAL_HIGH                   _MK_ENUM_CONST(3)
+
+
+// Register MC_FPRI_CTRL_ISP_0  
+#define MC_FPRI_CTRL_ISP_0                      _MK_ADDR_CONST(0x194)
+#define MC_FPRI_CTRL_ISP_0_SECURE                       0x0
+#define MC_FPRI_CTRL_ISP_0_WORD_COUNT                   0x1
+#define MC_FPRI_CTRL_ISP_0_RESET_VAL                    _MK_MASK_CONST(0x1)
+#define MC_FPRI_CTRL_ISP_0_RESET_MASK                   _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_ISP_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_ISP_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_ISP_0_READ_MASK                    _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_ISP_0_WRITE_MASK                   _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_ISP_0_ISPW_PRIVAL_SHIFT                    _MK_SHIFT_CONST(0)
+#define MC_FPRI_CTRL_ISP_0_ISPW_PRIVAL_FIELD                    (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_ISP_0_ISPW_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_ISP_0_ISPW_PRIVAL_RANGE                    1:0
+#define MC_FPRI_CTRL_ISP_0_ISPW_PRIVAL_WOFFSET                  0x0
+#define MC_FPRI_CTRL_ISP_0_ISPW_PRIVAL_DEFAULT                  _MK_MASK_CONST(0x1)
+#define MC_FPRI_CTRL_ISP_0_ISPW_PRIVAL_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_ISP_0_ISPW_PRIVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_ISP_0_ISPW_PRIVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_ISP_0_ISPW_PRIVAL_INIT_ENUM                        LOW
+#define MC_FPRI_CTRL_ISP_0_ISPW_PRIVAL_LOWEST                   _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_ISP_0_ISPW_PRIVAL_LOW                      _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_ISP_0_ISPW_PRIVAL_MED                      _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_ISP_0_ISPW_PRIVAL_HIGH                     _MK_ENUM_CONST(3)
+
+
+// Register MC_FPRI_CTRL_MPCORE_0  
+#define MC_FPRI_CTRL_MPCORE_0                   _MK_ADDR_CONST(0x198)
+#define MC_FPRI_CTRL_MPCORE_0_SECURE                    0x0
+#define MC_FPRI_CTRL_MPCORE_0_WORD_COUNT                        0x1
+#define MC_FPRI_CTRL_MPCORE_0_RESET_VAL                         _MK_MASK_CONST(0x5)
+#define MC_FPRI_CTRL_MPCORE_0_RESET_MASK                        _MK_MASK_CONST(0xf)
+#define MC_FPRI_CTRL_MPCORE_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_MPCORE_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_MPCORE_0_READ_MASK                         _MK_MASK_CONST(0xf)
+#define MC_FPRI_CTRL_MPCORE_0_WRITE_MASK                        _MK_MASK_CONST(0xf)
+#define MC_FPRI_CTRL_MPCORE_0_MPCORER_PRIVAL_SHIFT                      _MK_SHIFT_CONST(0)
+#define MC_FPRI_CTRL_MPCORE_0_MPCORER_PRIVAL_FIELD                      (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_MPCORE_0_MPCORER_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_MPCORE_0_MPCORER_PRIVAL_RANGE                      1:0
+#define MC_FPRI_CTRL_MPCORE_0_MPCORER_PRIVAL_WOFFSET                    0x0
+#define MC_FPRI_CTRL_MPCORE_0_MPCORER_PRIVAL_DEFAULT                    _MK_MASK_CONST(0x1)
+#define MC_FPRI_CTRL_MPCORE_0_MPCORER_PRIVAL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_MPCORE_0_MPCORER_PRIVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_MPCORE_0_MPCORER_PRIVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_MPCORE_0_MPCORER_PRIVAL_INIT_ENUM                  LOW
+#define MC_FPRI_CTRL_MPCORE_0_MPCORER_PRIVAL_LOWEST                     _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_MPCORE_0_MPCORER_PRIVAL_LOW                        _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_MPCORE_0_MPCORER_PRIVAL_MED                        _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_MPCORE_0_MPCORER_PRIVAL_HIGH                       _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_MPCORE_0_MPCOREW_PRIVAL_SHIFT                      _MK_SHIFT_CONST(2)
+#define MC_FPRI_CTRL_MPCORE_0_MPCOREW_PRIVAL_FIELD                      (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_MPCORE_0_MPCOREW_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_MPCORE_0_MPCOREW_PRIVAL_RANGE                      3:2
+#define MC_FPRI_CTRL_MPCORE_0_MPCOREW_PRIVAL_WOFFSET                    0x0
+#define MC_FPRI_CTRL_MPCORE_0_MPCOREW_PRIVAL_DEFAULT                    _MK_MASK_CONST(0x1)
+#define MC_FPRI_CTRL_MPCORE_0_MPCOREW_PRIVAL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_MPCORE_0_MPCOREW_PRIVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_MPCORE_0_MPCOREW_PRIVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_MPCORE_0_MPCOREW_PRIVAL_INIT_ENUM                  LOW
+#define MC_FPRI_CTRL_MPCORE_0_MPCOREW_PRIVAL_LOWEST                     _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_MPCORE_0_MPCOREW_PRIVAL_LOW                        _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_MPCORE_0_MPCOREW_PRIVAL_MED                        _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_MPCORE_0_MPCOREW_PRIVAL_HIGH                       _MK_ENUM_CONST(3)
+
+
+// Register MC_FPRI_CTRL_MPEA_0  
+#define MC_FPRI_CTRL_MPEA_0                     _MK_ADDR_CONST(0x19c)
+#define MC_FPRI_CTRL_MPEA_0_SECURE                      0x0
+#define MC_FPRI_CTRL_MPEA_0_WORD_COUNT                  0x1
+#define MC_FPRI_CTRL_MPEA_0_RESET_VAL                   _MK_MASK_CONST(0x1)
+#define MC_FPRI_CTRL_MPEA_0_RESET_MASK                  _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_MPEA_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_MPEA_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_MPEA_0_READ_MASK                   _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_MPEA_0_WRITE_MASK                  _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_MPEA_0_MPEAMEMRD_PRIVAL_SHIFT                      _MK_SHIFT_CONST(0)
+#define MC_FPRI_CTRL_MPEA_0_MPEAMEMRD_PRIVAL_FIELD                      (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_MPEA_0_MPEAMEMRD_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_MPEA_0_MPEAMEMRD_PRIVAL_RANGE                      1:0
+#define MC_FPRI_CTRL_MPEA_0_MPEAMEMRD_PRIVAL_WOFFSET                    0x0
+#define MC_FPRI_CTRL_MPEA_0_MPEAMEMRD_PRIVAL_DEFAULT                    _MK_MASK_CONST(0x1)
+#define MC_FPRI_CTRL_MPEA_0_MPEAMEMRD_PRIVAL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_MPEA_0_MPEAMEMRD_PRIVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_MPEA_0_MPEAMEMRD_PRIVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_MPEA_0_MPEAMEMRD_PRIVAL_INIT_ENUM                  LOW
+#define MC_FPRI_CTRL_MPEA_0_MPEAMEMRD_PRIVAL_LOWEST                     _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_MPEA_0_MPEAMEMRD_PRIVAL_LOW                        _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_MPEA_0_MPEAMEMRD_PRIVAL_MED                        _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_MPEA_0_MPEAMEMRD_PRIVAL_HIGH                       _MK_ENUM_CONST(3)
+
+
+// Register MC_FPRI_CTRL_MPEB_0  
+#define MC_FPRI_CTRL_MPEB_0                     _MK_ADDR_CONST(0x1a0)
+#define MC_FPRI_CTRL_MPEB_0_SECURE                      0x0
+#define MC_FPRI_CTRL_MPEB_0_WORD_COUNT                  0x1
+#define MC_FPRI_CTRL_MPEB_0_RESET_VAL                   _MK_MASK_CONST(0x15)
+#define MC_FPRI_CTRL_MPEB_0_RESET_MASK                  _MK_MASK_CONST(0x3f)
+#define MC_FPRI_CTRL_MPEB_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_MPEB_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_MPEB_0_READ_MASK                   _MK_MASK_CONST(0x3f)
+#define MC_FPRI_CTRL_MPEB_0_WRITE_MASK                  _MK_MASK_CONST(0x3f)
+#define MC_FPRI_CTRL_MPEB_0_MPEUNIFBR_PRIVAL_SHIFT                      _MK_SHIFT_CONST(0)
+#define MC_FPRI_CTRL_MPEB_0_MPEUNIFBR_PRIVAL_FIELD                      (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_MPEB_0_MPEUNIFBR_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_MPEB_0_MPEUNIFBR_PRIVAL_RANGE                      1:0
+#define MC_FPRI_CTRL_MPEB_0_MPEUNIFBR_PRIVAL_WOFFSET                    0x0
+#define MC_FPRI_CTRL_MPEB_0_MPEUNIFBR_PRIVAL_DEFAULT                    _MK_MASK_CONST(0x1)
+#define MC_FPRI_CTRL_MPEB_0_MPEUNIFBR_PRIVAL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_MPEB_0_MPEUNIFBR_PRIVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_MPEB_0_MPEUNIFBR_PRIVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_MPEB_0_MPEUNIFBR_PRIVAL_INIT_ENUM                  LOW
+#define MC_FPRI_CTRL_MPEB_0_MPEUNIFBR_PRIVAL_LOWEST                     _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_MPEB_0_MPEUNIFBR_PRIVAL_LOW                        _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_MPEB_0_MPEUNIFBR_PRIVAL_MED                        _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_MPEB_0_MPEUNIFBR_PRIVAL_HIGH                       _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_MPEB_0_MPE_IPRED_PRIVAL_SHIFT                      _MK_SHIFT_CONST(2)
+#define MC_FPRI_CTRL_MPEB_0_MPE_IPRED_PRIVAL_FIELD                      (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_MPEB_0_MPE_IPRED_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_MPEB_0_MPE_IPRED_PRIVAL_RANGE                      3:2
+#define MC_FPRI_CTRL_MPEB_0_MPE_IPRED_PRIVAL_WOFFSET                    0x0
+#define MC_FPRI_CTRL_MPEB_0_MPE_IPRED_PRIVAL_DEFAULT                    _MK_MASK_CONST(0x1)
+#define MC_FPRI_CTRL_MPEB_0_MPE_IPRED_PRIVAL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_MPEB_0_MPE_IPRED_PRIVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_MPEB_0_MPE_IPRED_PRIVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_MPEB_0_MPE_IPRED_PRIVAL_INIT_ENUM                  LOW
+#define MC_FPRI_CTRL_MPEB_0_MPE_IPRED_PRIVAL_LOWEST                     _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_MPEB_0_MPE_IPRED_PRIVAL_LOW                        _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_MPEB_0_MPE_IPRED_PRIVAL_MED                        _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_MPEB_0_MPE_IPRED_PRIVAL_HIGH                       _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_MPEB_0_MPEUNIFBW_PRIVAL_SHIFT                      _MK_SHIFT_CONST(4)
+#define MC_FPRI_CTRL_MPEB_0_MPEUNIFBW_PRIVAL_FIELD                      (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_MPEB_0_MPEUNIFBW_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_MPEB_0_MPEUNIFBW_PRIVAL_RANGE                      5:4
+#define MC_FPRI_CTRL_MPEB_0_MPEUNIFBW_PRIVAL_WOFFSET                    0x0
+#define MC_FPRI_CTRL_MPEB_0_MPEUNIFBW_PRIVAL_DEFAULT                    _MK_MASK_CONST(0x1)
+#define MC_FPRI_CTRL_MPEB_0_MPEUNIFBW_PRIVAL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_MPEB_0_MPEUNIFBW_PRIVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_MPEB_0_MPEUNIFBW_PRIVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_MPEB_0_MPEUNIFBW_PRIVAL_INIT_ENUM                  LOW
+#define MC_FPRI_CTRL_MPEB_0_MPEUNIFBW_PRIVAL_LOWEST                     _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_MPEB_0_MPEUNIFBW_PRIVAL_LOW                        _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_MPEB_0_MPEUNIFBW_PRIVAL_MED                        _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_MPEB_0_MPEUNIFBW_PRIVAL_HIGH                       _MK_ENUM_CONST(3)
+
+
+// Register MC_FPRI_CTRL_MPEC_0  
+#define MC_FPRI_CTRL_MPEC_0                     _MK_ADDR_CONST(0x1a4)
+#define MC_FPRI_CTRL_MPEC_0_SECURE                      0x0
+#define MC_FPRI_CTRL_MPEC_0_WORD_COUNT                  0x1
+#define MC_FPRI_CTRL_MPEC_0_RESET_VAL                   _MK_MASK_CONST(0x5)
+#define MC_FPRI_CTRL_MPEC_0_RESET_MASK                  _MK_MASK_CONST(0xf)
+#define MC_FPRI_CTRL_MPEC_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_MPEC_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_MPEC_0_READ_MASK                   _MK_MASK_CONST(0xf)
+#define MC_FPRI_CTRL_MPEC_0_WRITE_MASK                  _MK_MASK_CONST(0xf)
+#define MC_FPRI_CTRL_MPEC_0_MPECSRD_PRIVAL_SHIFT                        _MK_SHIFT_CONST(0)
+#define MC_FPRI_CTRL_MPEC_0_MPECSRD_PRIVAL_FIELD                        (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_MPEC_0_MPECSRD_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_MPEC_0_MPECSRD_PRIVAL_RANGE                        1:0
+#define MC_FPRI_CTRL_MPEC_0_MPECSRD_PRIVAL_WOFFSET                      0x0
+#define MC_FPRI_CTRL_MPEC_0_MPECSRD_PRIVAL_DEFAULT                      _MK_MASK_CONST(0x1)
+#define MC_FPRI_CTRL_MPEC_0_MPECSRD_PRIVAL_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_MPEC_0_MPECSRD_PRIVAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_MPEC_0_MPECSRD_PRIVAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_MPEC_0_MPECSRD_PRIVAL_INIT_ENUM                    LOW
+#define MC_FPRI_CTRL_MPEC_0_MPECSRD_PRIVAL_LOWEST                       _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_MPEC_0_MPECSRD_PRIVAL_LOW                  _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_MPEC_0_MPECSRD_PRIVAL_MED                  _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_MPEC_0_MPECSRD_PRIVAL_HIGH                 _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_MPEC_0_MPECSWR_PRIVAL_SHIFT                        _MK_SHIFT_CONST(2)
+#define MC_FPRI_CTRL_MPEC_0_MPECSWR_PRIVAL_FIELD                        (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_MPEC_0_MPECSWR_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_MPEC_0_MPECSWR_PRIVAL_RANGE                        3:2
+#define MC_FPRI_CTRL_MPEC_0_MPECSWR_PRIVAL_WOFFSET                      0x0
+#define MC_FPRI_CTRL_MPEC_0_MPECSWR_PRIVAL_DEFAULT                      _MK_MASK_CONST(0x1)
+#define MC_FPRI_CTRL_MPEC_0_MPECSWR_PRIVAL_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_MPEC_0_MPECSWR_PRIVAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_MPEC_0_MPECSWR_PRIVAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_MPEC_0_MPECSWR_PRIVAL_INIT_ENUM                    LOW
+#define MC_FPRI_CTRL_MPEC_0_MPECSWR_PRIVAL_LOWEST                       _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_MPEC_0_MPECSWR_PRIVAL_LOW                  _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_MPEC_0_MPECSWR_PRIVAL_MED                  _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_MPEC_0_MPECSWR_PRIVAL_HIGH                 _MK_ENUM_CONST(3)
+
+
+// Register MC_FPRI_CTRL_NV_0  
+#define MC_FPRI_CTRL_NV_0                       _MK_ADDR_CONST(0x1a8)
+#define MC_FPRI_CTRL_NV_0_SECURE                        0x0
+#define MC_FPRI_CTRL_NV_0_WORD_COUNT                    0x1
+#define MC_FPRI_CTRL_NV_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_NV_0_RESET_MASK                    _MK_MASK_CONST(0xff)
+#define MC_FPRI_CTRL_NV_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_NV_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_NV_0_READ_MASK                     _MK_MASK_CONST(0xff)
+#define MC_FPRI_CTRL_NV_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
+#define MC_FPRI_CTRL_NV_0_FDCDRD_PRIVAL_SHIFT                   _MK_SHIFT_CONST(0)
+#define MC_FPRI_CTRL_NV_0_FDCDRD_PRIVAL_FIELD                   (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_NV_0_FDCDRD_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_NV_0_FDCDRD_PRIVAL_RANGE                   1:0
+#define MC_FPRI_CTRL_NV_0_FDCDRD_PRIVAL_WOFFSET                 0x0
+#define MC_FPRI_CTRL_NV_0_FDCDRD_PRIVAL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_NV_0_FDCDRD_PRIVAL_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_NV_0_FDCDRD_PRIVAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_NV_0_FDCDRD_PRIVAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_NV_0_FDCDRD_PRIVAL_INIT_ENUM                       LOWEST
+#define MC_FPRI_CTRL_NV_0_FDCDRD_PRIVAL_LOWEST                  _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_NV_0_FDCDRD_PRIVAL_LOW                     _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_NV_0_FDCDRD_PRIVAL_MED                     _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_NV_0_FDCDRD_PRIVAL_HIGH                    _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_NV_0_IDXSRD_PRIVAL_SHIFT                   _MK_SHIFT_CONST(2)
+#define MC_FPRI_CTRL_NV_0_IDXSRD_PRIVAL_FIELD                   (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_NV_0_IDXSRD_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_NV_0_IDXSRD_PRIVAL_RANGE                   3:2
+#define MC_FPRI_CTRL_NV_0_IDXSRD_PRIVAL_WOFFSET                 0x0
+#define MC_FPRI_CTRL_NV_0_IDXSRD_PRIVAL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_NV_0_IDXSRD_PRIVAL_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_NV_0_IDXSRD_PRIVAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_NV_0_IDXSRD_PRIVAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_NV_0_IDXSRD_PRIVAL_INIT_ENUM                       LOWEST
+#define MC_FPRI_CTRL_NV_0_IDXSRD_PRIVAL_LOWEST                  _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_NV_0_IDXSRD_PRIVAL_LOW                     _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_NV_0_IDXSRD_PRIVAL_MED                     _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_NV_0_IDXSRD_PRIVAL_HIGH                    _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_NV_0_TEXSRD_PRIVAL_SHIFT                   _MK_SHIFT_CONST(4)
+#define MC_FPRI_CTRL_NV_0_TEXSRD_PRIVAL_FIELD                   (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_NV_0_TEXSRD_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_NV_0_TEXSRD_PRIVAL_RANGE                   5:4
+#define MC_FPRI_CTRL_NV_0_TEXSRD_PRIVAL_WOFFSET                 0x0
+#define MC_FPRI_CTRL_NV_0_TEXSRD_PRIVAL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_NV_0_TEXSRD_PRIVAL_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_NV_0_TEXSRD_PRIVAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_NV_0_TEXSRD_PRIVAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_NV_0_TEXSRD_PRIVAL_INIT_ENUM                       LOWEST
+#define MC_FPRI_CTRL_NV_0_TEXSRD_PRIVAL_LOWEST                  _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_NV_0_TEXSRD_PRIVAL_LOW                     _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_NV_0_TEXSRD_PRIVAL_MED                     _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_NV_0_TEXSRD_PRIVAL_HIGH                    _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_NV_0_FDCDWR_PRIVAL_SHIFT                   _MK_SHIFT_CONST(6)
+#define MC_FPRI_CTRL_NV_0_FDCDWR_PRIVAL_FIELD                   (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_NV_0_FDCDWR_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_NV_0_FDCDWR_PRIVAL_RANGE                   7:6
+#define MC_FPRI_CTRL_NV_0_FDCDWR_PRIVAL_WOFFSET                 0x0
+#define MC_FPRI_CTRL_NV_0_FDCDWR_PRIVAL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_NV_0_FDCDWR_PRIVAL_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_NV_0_FDCDWR_PRIVAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_NV_0_FDCDWR_PRIVAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_NV_0_FDCDWR_PRIVAL_INIT_ENUM                       LOWEST
+#define MC_FPRI_CTRL_NV_0_FDCDWR_PRIVAL_LOWEST                  _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_NV_0_FDCDWR_PRIVAL_LOW                     _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_NV_0_FDCDWR_PRIVAL_MED                     _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_NV_0_FDCDWR_PRIVAL_HIGH                    _MK_ENUM_CONST(3)
+
+
+// Register MC_FPRI_CTRL_PPCS_0  
+#define MC_FPRI_CTRL_PPCS_0                     _MK_ADDR_CONST(0x1ac)
+#define MC_FPRI_CTRL_PPCS_0_SECURE                      0x0
+#define MC_FPRI_CTRL_PPCS_0_WORD_COUNT                  0x1
+#define MC_FPRI_CTRL_PPCS_0_RESET_VAL                   _MK_MASK_CONST(0x55)
+#define MC_FPRI_CTRL_PPCS_0_RESET_MASK                  _MK_MASK_CONST(0xff)
+#define MC_FPRI_CTRL_PPCS_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_PPCS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_PPCS_0_READ_MASK                   _MK_MASK_CONST(0xff)
+#define MC_FPRI_CTRL_PPCS_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBDMAR_PRIVAL_SHIFT                    _MK_SHIFT_CONST(0)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBDMAR_PRIVAL_FIELD                    (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_PPCS_0_PPCSAHBDMAR_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBDMAR_PRIVAL_RANGE                    1:0
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBDMAR_PRIVAL_WOFFSET                  0x0
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBDMAR_PRIVAL_DEFAULT                  _MK_MASK_CONST(0x1)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBDMAR_PRIVAL_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBDMAR_PRIVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBDMAR_PRIVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBDMAR_PRIVAL_INIT_ENUM                        LOW
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBDMAR_PRIVAL_LOWEST                   _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBDMAR_PRIVAL_LOW                      _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBDMAR_PRIVAL_MED                      _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBDMAR_PRIVAL_HIGH                     _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBSLVR_PRIVAL_SHIFT                    _MK_SHIFT_CONST(2)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBSLVR_PRIVAL_FIELD                    (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_PPCS_0_PPCSAHBSLVR_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBSLVR_PRIVAL_RANGE                    3:2
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBSLVR_PRIVAL_WOFFSET                  0x0
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBSLVR_PRIVAL_DEFAULT                  _MK_MASK_CONST(0x1)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBSLVR_PRIVAL_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBSLVR_PRIVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBSLVR_PRIVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBSLVR_PRIVAL_INIT_ENUM                        LOW
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBSLVR_PRIVAL_LOWEST                   _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBSLVR_PRIVAL_LOW                      _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBSLVR_PRIVAL_MED                      _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBSLVR_PRIVAL_HIGH                     _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBDMAW_PRIVAL_SHIFT                    _MK_SHIFT_CONST(4)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBDMAW_PRIVAL_FIELD                    (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_PPCS_0_PPCSAHBDMAW_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBDMAW_PRIVAL_RANGE                    5:4
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBDMAW_PRIVAL_WOFFSET                  0x0
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBDMAW_PRIVAL_DEFAULT                  _MK_MASK_CONST(0x1)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBDMAW_PRIVAL_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBDMAW_PRIVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBDMAW_PRIVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBDMAW_PRIVAL_INIT_ENUM                        LOW
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBDMAW_PRIVAL_LOWEST                   _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBDMAW_PRIVAL_LOW                      _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBDMAW_PRIVAL_MED                      _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBDMAW_PRIVAL_HIGH                     _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBSLVW_PRIVAL_SHIFT                    _MK_SHIFT_CONST(6)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBSLVW_PRIVAL_FIELD                    (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_PPCS_0_PPCSAHBSLVW_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBSLVW_PRIVAL_RANGE                    7:6
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBSLVW_PRIVAL_WOFFSET                  0x0
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBSLVW_PRIVAL_DEFAULT                  _MK_MASK_CONST(0x1)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBSLVW_PRIVAL_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBSLVW_PRIVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBSLVW_PRIVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBSLVW_PRIVAL_INIT_ENUM                        LOW
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBSLVW_PRIVAL_LOWEST                   _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBSLVW_PRIVAL_LOW                      _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBSLVW_PRIVAL_MED                      _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBSLVW_PRIVAL_HIGH                     _MK_ENUM_CONST(3)
+
+
+// Register MC_FPRI_CTRL_VDE_0  
+#define MC_FPRI_CTRL_VDE_0                      _MK_ADDR_CONST(0x1b0)
+#define MC_FPRI_CTRL_VDE_0_SECURE                       0x0
+#define MC_FPRI_CTRL_VDE_0_WORD_COUNT                   0x1
+#define MC_FPRI_CTRL_VDE_0_RESET_VAL                    _MK_MASK_CONST(0x1555)
+#define MC_FPRI_CTRL_VDE_0_RESET_MASK                   _MK_MASK_CONST(0x3fff)
+#define MC_FPRI_CTRL_VDE_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VDE_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VDE_0_READ_MASK                    _MK_MASK_CONST(0x3fff)
+#define MC_FPRI_CTRL_VDE_0_WRITE_MASK                   _MK_MASK_CONST(0x3fff)
+#define MC_FPRI_CTRL_VDE_0_VDEBSEVR_PRIVAL_SHIFT                        _MK_SHIFT_CONST(0)
+#define MC_FPRI_CTRL_VDE_0_VDEBSEVR_PRIVAL_FIELD                        (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_VDE_0_VDEBSEVR_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_VDE_0_VDEBSEVR_PRIVAL_RANGE                        1:0
+#define MC_FPRI_CTRL_VDE_0_VDEBSEVR_PRIVAL_WOFFSET                      0x0
+#define MC_FPRI_CTRL_VDE_0_VDEBSEVR_PRIVAL_DEFAULT                      _MK_MASK_CONST(0x1)
+#define MC_FPRI_CTRL_VDE_0_VDEBSEVR_PRIVAL_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_VDE_0_VDEBSEVR_PRIVAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VDE_0_VDEBSEVR_PRIVAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VDE_0_VDEBSEVR_PRIVAL_INIT_ENUM                    LOW
+#define MC_FPRI_CTRL_VDE_0_VDEBSEVR_PRIVAL_LOWEST                       _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_VDE_0_VDEBSEVR_PRIVAL_LOW                  _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_VDE_0_VDEBSEVR_PRIVAL_MED                  _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_VDE_0_VDEBSEVR_PRIVAL_HIGH                 _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_VDE_0_VDEMBER_PRIVAL_SHIFT                 _MK_SHIFT_CONST(2)
+#define MC_FPRI_CTRL_VDE_0_VDEMBER_PRIVAL_FIELD                 (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_VDE_0_VDEMBER_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_VDE_0_VDEMBER_PRIVAL_RANGE                 3:2
+#define MC_FPRI_CTRL_VDE_0_VDEMBER_PRIVAL_WOFFSET                       0x0
+#define MC_FPRI_CTRL_VDE_0_VDEMBER_PRIVAL_DEFAULT                       _MK_MASK_CONST(0x1)
+#define MC_FPRI_CTRL_VDE_0_VDEMBER_PRIVAL_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_VDE_0_VDEMBER_PRIVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VDE_0_VDEMBER_PRIVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VDE_0_VDEMBER_PRIVAL_INIT_ENUM                     LOW
+#define MC_FPRI_CTRL_VDE_0_VDEMBER_PRIVAL_LOWEST                        _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_VDE_0_VDEMBER_PRIVAL_LOW                   _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_VDE_0_VDEMBER_PRIVAL_MED                   _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_VDE_0_VDEMBER_PRIVAL_HIGH                  _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_VDE_0_VDEMCER_PRIVAL_SHIFT                 _MK_SHIFT_CONST(4)
+#define MC_FPRI_CTRL_VDE_0_VDEMCER_PRIVAL_FIELD                 (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_VDE_0_VDEMCER_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_VDE_0_VDEMCER_PRIVAL_RANGE                 5:4
+#define MC_FPRI_CTRL_VDE_0_VDEMCER_PRIVAL_WOFFSET                       0x0
+#define MC_FPRI_CTRL_VDE_0_VDEMCER_PRIVAL_DEFAULT                       _MK_MASK_CONST(0x1)
+#define MC_FPRI_CTRL_VDE_0_VDEMCER_PRIVAL_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_VDE_0_VDEMCER_PRIVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VDE_0_VDEMCER_PRIVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VDE_0_VDEMCER_PRIVAL_INIT_ENUM                     LOW
+#define MC_FPRI_CTRL_VDE_0_VDEMCER_PRIVAL_LOWEST                        _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_VDE_0_VDEMCER_PRIVAL_LOW                   _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_VDE_0_VDEMCER_PRIVAL_MED                   _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_VDE_0_VDEMCER_PRIVAL_HIGH                  _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_VDE_0_VDETPER_PRIVAL_SHIFT                 _MK_SHIFT_CONST(6)
+#define MC_FPRI_CTRL_VDE_0_VDETPER_PRIVAL_FIELD                 (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_VDE_0_VDETPER_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_VDE_0_VDETPER_PRIVAL_RANGE                 7:6
+#define MC_FPRI_CTRL_VDE_0_VDETPER_PRIVAL_WOFFSET                       0x0
+#define MC_FPRI_CTRL_VDE_0_VDETPER_PRIVAL_DEFAULT                       _MK_MASK_CONST(0x1)
+#define MC_FPRI_CTRL_VDE_0_VDETPER_PRIVAL_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_VDE_0_VDETPER_PRIVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VDE_0_VDETPER_PRIVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VDE_0_VDETPER_PRIVAL_INIT_ENUM                     LOW
+#define MC_FPRI_CTRL_VDE_0_VDETPER_PRIVAL_LOWEST                        _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_VDE_0_VDETPER_PRIVAL_LOW                   _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_VDE_0_VDETPER_PRIVAL_MED                   _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_VDE_0_VDETPER_PRIVAL_HIGH                  _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_VDE_0_VDEBSEVW_PRIVAL_SHIFT                        _MK_SHIFT_CONST(8)
+#define MC_FPRI_CTRL_VDE_0_VDEBSEVW_PRIVAL_FIELD                        (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_VDE_0_VDEBSEVW_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_VDE_0_VDEBSEVW_PRIVAL_RANGE                        9:8
+#define MC_FPRI_CTRL_VDE_0_VDEBSEVW_PRIVAL_WOFFSET                      0x0
+#define MC_FPRI_CTRL_VDE_0_VDEBSEVW_PRIVAL_DEFAULT                      _MK_MASK_CONST(0x1)
+#define MC_FPRI_CTRL_VDE_0_VDEBSEVW_PRIVAL_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_VDE_0_VDEBSEVW_PRIVAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VDE_0_VDEBSEVW_PRIVAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VDE_0_VDEBSEVW_PRIVAL_INIT_ENUM                    LOW
+#define MC_FPRI_CTRL_VDE_0_VDEBSEVW_PRIVAL_LOWEST                       _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_VDE_0_VDEBSEVW_PRIVAL_LOW                  _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_VDE_0_VDEBSEVW_PRIVAL_MED                  _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_VDE_0_VDEBSEVW_PRIVAL_HIGH                 _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_VDE_0_VDEMBEW_PRIVAL_SHIFT                 _MK_SHIFT_CONST(10)
+#define MC_FPRI_CTRL_VDE_0_VDEMBEW_PRIVAL_FIELD                 (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_VDE_0_VDEMBEW_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_VDE_0_VDEMBEW_PRIVAL_RANGE                 11:10
+#define MC_FPRI_CTRL_VDE_0_VDEMBEW_PRIVAL_WOFFSET                       0x0
+#define MC_FPRI_CTRL_VDE_0_VDEMBEW_PRIVAL_DEFAULT                       _MK_MASK_CONST(0x1)
+#define MC_FPRI_CTRL_VDE_0_VDEMBEW_PRIVAL_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_VDE_0_VDEMBEW_PRIVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VDE_0_VDEMBEW_PRIVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VDE_0_VDEMBEW_PRIVAL_INIT_ENUM                     LOW
+#define MC_FPRI_CTRL_VDE_0_VDEMBEW_PRIVAL_LOWEST                        _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_VDE_0_VDEMBEW_PRIVAL_LOW                   _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_VDE_0_VDEMBEW_PRIVAL_MED                   _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_VDE_0_VDEMBEW_PRIVAL_HIGH                  _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_VDE_0_VDETPMW_PRIVAL_SHIFT                 _MK_SHIFT_CONST(12)
+#define MC_FPRI_CTRL_VDE_0_VDETPMW_PRIVAL_FIELD                 (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_VDE_0_VDETPMW_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_VDE_0_VDETPMW_PRIVAL_RANGE                 13:12
+#define MC_FPRI_CTRL_VDE_0_VDETPMW_PRIVAL_WOFFSET                       0x0
+#define MC_FPRI_CTRL_VDE_0_VDETPMW_PRIVAL_DEFAULT                       _MK_MASK_CONST(0x1)
+#define MC_FPRI_CTRL_VDE_0_VDETPMW_PRIVAL_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_VDE_0_VDETPMW_PRIVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VDE_0_VDETPMW_PRIVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VDE_0_VDETPMW_PRIVAL_INIT_ENUM                     LOW
+#define MC_FPRI_CTRL_VDE_0_VDETPMW_PRIVAL_LOWEST                        _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_VDE_0_VDETPMW_PRIVAL_LOW                   _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_VDE_0_VDETPMW_PRIVAL_MED                   _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_VDE_0_VDETPMW_PRIVAL_HIGH                  _MK_ENUM_CONST(3)
+
+
+// Register MC_FPRI_CTRL_VI_0  
+#define MC_FPRI_CTRL_VI_0                       _MK_ADDR_CONST(0x1b4)
+#define MC_FPRI_CTRL_VI_0_SECURE                        0x0
+#define MC_FPRI_CTRL_VI_0_WORD_COUNT                    0x1
+#define MC_FPRI_CTRL_VI_0_RESET_VAL                     _MK_MASK_CONST(0x155)
+#define MC_FPRI_CTRL_VI_0_RESET_MASK                    _MK_MASK_CONST(0x3ff)
+#define MC_FPRI_CTRL_VI_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VI_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VI_0_READ_MASK                     _MK_MASK_CONST(0x3ff)
+#define MC_FPRI_CTRL_VI_0_WRITE_MASK                    _MK_MASK_CONST(0x3ff)
+#define MC_FPRI_CTRL_VI_0_VIRUV_PRIVAL_SHIFT                    _MK_SHIFT_CONST(0)
+#define MC_FPRI_CTRL_VI_0_VIRUV_PRIVAL_FIELD                    (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_VI_0_VIRUV_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_VI_0_VIRUV_PRIVAL_RANGE                    1:0
+#define MC_FPRI_CTRL_VI_0_VIRUV_PRIVAL_WOFFSET                  0x0
+#define MC_FPRI_CTRL_VI_0_VIRUV_PRIVAL_DEFAULT                  _MK_MASK_CONST(0x1)
+#define MC_FPRI_CTRL_VI_0_VIRUV_PRIVAL_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_VI_0_VIRUV_PRIVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VI_0_VIRUV_PRIVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VI_0_VIRUV_PRIVAL_INIT_ENUM                        LOW
+#define MC_FPRI_CTRL_VI_0_VIRUV_PRIVAL_LOWEST                   _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_VI_0_VIRUV_PRIVAL_LOW                      _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_VI_0_VIRUV_PRIVAL_MED                      _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_VI_0_VIRUV_PRIVAL_HIGH                     _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_VI_0_VIWSB_PRIVAL_SHIFT                    _MK_SHIFT_CONST(2)
+#define MC_FPRI_CTRL_VI_0_VIWSB_PRIVAL_FIELD                    (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_VI_0_VIWSB_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_VI_0_VIWSB_PRIVAL_RANGE                    3:2
+#define MC_FPRI_CTRL_VI_0_VIWSB_PRIVAL_WOFFSET                  0x0
+#define MC_FPRI_CTRL_VI_0_VIWSB_PRIVAL_DEFAULT                  _MK_MASK_CONST(0x1)
+#define MC_FPRI_CTRL_VI_0_VIWSB_PRIVAL_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_VI_0_VIWSB_PRIVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VI_0_VIWSB_PRIVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VI_0_VIWSB_PRIVAL_INIT_ENUM                        LOW
+#define MC_FPRI_CTRL_VI_0_VIWSB_PRIVAL_LOWEST                   _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_VI_0_VIWSB_PRIVAL_LOW                      _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_VI_0_VIWSB_PRIVAL_MED                      _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_VI_0_VIWSB_PRIVAL_HIGH                     _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_VI_0_VIWU_PRIVAL_SHIFT                     _MK_SHIFT_CONST(4)
+#define MC_FPRI_CTRL_VI_0_VIWU_PRIVAL_FIELD                     (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_VI_0_VIWU_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_VI_0_VIWU_PRIVAL_RANGE                     5:4
+#define MC_FPRI_CTRL_VI_0_VIWU_PRIVAL_WOFFSET                   0x0
+#define MC_FPRI_CTRL_VI_0_VIWU_PRIVAL_DEFAULT                   _MK_MASK_CONST(0x1)
+#define MC_FPRI_CTRL_VI_0_VIWU_PRIVAL_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_VI_0_VIWU_PRIVAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VI_0_VIWU_PRIVAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VI_0_VIWU_PRIVAL_INIT_ENUM                 LOW
+#define MC_FPRI_CTRL_VI_0_VIWU_PRIVAL_LOWEST                    _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_VI_0_VIWU_PRIVAL_LOW                       _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_VI_0_VIWU_PRIVAL_MED                       _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_VI_0_VIWU_PRIVAL_HIGH                      _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_VI_0_VIWV_PRIVAL_SHIFT                     _MK_SHIFT_CONST(6)
+#define MC_FPRI_CTRL_VI_0_VIWV_PRIVAL_FIELD                     (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_VI_0_VIWV_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_VI_0_VIWV_PRIVAL_RANGE                     7:6
+#define MC_FPRI_CTRL_VI_0_VIWV_PRIVAL_WOFFSET                   0x0
+#define MC_FPRI_CTRL_VI_0_VIWV_PRIVAL_DEFAULT                   _MK_MASK_CONST(0x1)
+#define MC_FPRI_CTRL_VI_0_VIWV_PRIVAL_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_VI_0_VIWV_PRIVAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VI_0_VIWV_PRIVAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VI_0_VIWV_PRIVAL_INIT_ENUM                 LOW
+#define MC_FPRI_CTRL_VI_0_VIWV_PRIVAL_LOWEST                    _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_VI_0_VIWV_PRIVAL_LOW                       _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_VI_0_VIWV_PRIVAL_MED                       _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_VI_0_VIWV_PRIVAL_HIGH                      _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_VI_0_VIWY_PRIVAL_SHIFT                     _MK_SHIFT_CONST(8)
+#define MC_FPRI_CTRL_VI_0_VIWY_PRIVAL_FIELD                     (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_VI_0_VIWY_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_VI_0_VIWY_PRIVAL_RANGE                     9:8
+#define MC_FPRI_CTRL_VI_0_VIWY_PRIVAL_WOFFSET                   0x0
+#define MC_FPRI_CTRL_VI_0_VIWY_PRIVAL_DEFAULT                   _MK_MASK_CONST(0x1)
+#define MC_FPRI_CTRL_VI_0_VIWY_PRIVAL_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_VI_0_VIWY_PRIVAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VI_0_VIWY_PRIVAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VI_0_VIWY_PRIVAL_INIT_ENUM                 LOW
+#define MC_FPRI_CTRL_VI_0_VIWY_PRIVAL_LOWEST                    _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_VI_0_VIWY_PRIVAL_LOW                       _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_VI_0_VIWY_PRIVAL_MED                       _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_VI_0_VIWY_PRIVAL_HIGH                      _MK_ENUM_CONST(3)
+
+
+// Register MC_TIMEOUT_AVPC_0  
+#define MC_TIMEOUT_AVPC_0                       _MK_ADDR_CONST(0x1b8)
+#define MC_TIMEOUT_AVPC_0_SECURE                        0x0
+#define MC_TIMEOUT_AVPC_0_WORD_COUNT                    0x1
+#define MC_TIMEOUT_AVPC_0_RESET_VAL                     _MK_MASK_CONST(0x88)
+#define MC_TIMEOUT_AVPC_0_RESET_MASK                    _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_AVPC_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_AVPC_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_AVPC_0_READ_MASK                     _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_AVPC_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_AVPC_0_AVPCARM7R_TMVAL_SHIFT                 _MK_SHIFT_CONST(0)
+#define MC_TIMEOUT_AVPC_0_AVPCARM7R_TMVAL_FIELD                 (_MK_MASK_CONST(0xf) << MC_TIMEOUT_AVPC_0_AVPCARM7R_TMVAL_SHIFT)
+#define MC_TIMEOUT_AVPC_0_AVPCARM7R_TMVAL_RANGE                 3:0
+#define MC_TIMEOUT_AVPC_0_AVPCARM7R_TMVAL_WOFFSET                       0x0
+#define MC_TIMEOUT_AVPC_0_AVPCARM7R_TMVAL_DEFAULT                       _MK_MASK_CONST(0x8)
+#define MC_TIMEOUT_AVPC_0_AVPCARM7R_TMVAL_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_AVPC_0_AVPCARM7R_TMVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_AVPC_0_AVPCARM7R_TMVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_AVPC_0_AVPCARM7W_TMVAL_SHIFT                 _MK_SHIFT_CONST(4)
+#define MC_TIMEOUT_AVPC_0_AVPCARM7W_TMVAL_FIELD                 (_MK_MASK_CONST(0xf) << MC_TIMEOUT_AVPC_0_AVPCARM7W_TMVAL_SHIFT)
+#define MC_TIMEOUT_AVPC_0_AVPCARM7W_TMVAL_RANGE                 7:4
+#define MC_TIMEOUT_AVPC_0_AVPCARM7W_TMVAL_WOFFSET                       0x0
+#define MC_TIMEOUT_AVPC_0_AVPCARM7W_TMVAL_DEFAULT                       _MK_MASK_CONST(0x8)
+#define MC_TIMEOUT_AVPC_0_AVPCARM7W_TMVAL_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_AVPC_0_AVPCARM7W_TMVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_AVPC_0_AVPCARM7W_TMVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register MC_TIMEOUT_DC_0  
+#define MC_TIMEOUT_DC_0                 _MK_ADDR_CONST(0x1bc)
+#define MC_TIMEOUT_DC_0_SECURE                  0x0
+#define MC_TIMEOUT_DC_0_WORD_COUNT                      0x1
+#define MC_TIMEOUT_DC_0_RESET_VAL                       _MK_MASK_CONST(0x88888)
+#define MC_TIMEOUT_DC_0_RESET_MASK                      _MK_MASK_CONST(0xfffff)
+#define MC_TIMEOUT_DC_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_DC_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_DC_0_READ_MASK                       _MK_MASK_CONST(0xfffff)
+#define MC_TIMEOUT_DC_0_WRITE_MASK                      _MK_MASK_CONST(0xfffff)
+#define MC_TIMEOUT_DC_0_DISPLAY0A_TMVAL_SHIFT                   _MK_SHIFT_CONST(0)
+#define MC_TIMEOUT_DC_0_DISPLAY0A_TMVAL_FIELD                   (_MK_MASK_CONST(0xf) << MC_TIMEOUT_DC_0_DISPLAY0A_TMVAL_SHIFT)
+#define MC_TIMEOUT_DC_0_DISPLAY0A_TMVAL_RANGE                   3:0
+#define MC_TIMEOUT_DC_0_DISPLAY0A_TMVAL_WOFFSET                 0x0
+#define MC_TIMEOUT_DC_0_DISPLAY0A_TMVAL_DEFAULT                 _MK_MASK_CONST(0x8)
+#define MC_TIMEOUT_DC_0_DISPLAY0A_TMVAL_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_DC_0_DISPLAY0A_TMVAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_DC_0_DISPLAY0A_TMVAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_DC_0_DISPLAY0B_TMVAL_SHIFT                   _MK_SHIFT_CONST(4)
+#define MC_TIMEOUT_DC_0_DISPLAY0B_TMVAL_FIELD                   (_MK_MASK_CONST(0xf) << MC_TIMEOUT_DC_0_DISPLAY0B_TMVAL_SHIFT)
+#define MC_TIMEOUT_DC_0_DISPLAY0B_TMVAL_RANGE                   7:4
+#define MC_TIMEOUT_DC_0_DISPLAY0B_TMVAL_WOFFSET                 0x0
+#define MC_TIMEOUT_DC_0_DISPLAY0B_TMVAL_DEFAULT                 _MK_MASK_CONST(0x8)
+#define MC_TIMEOUT_DC_0_DISPLAY0B_TMVAL_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_DC_0_DISPLAY0B_TMVAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_DC_0_DISPLAY0B_TMVAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_DC_0_DISPLAY0C_TMVAL_SHIFT                   _MK_SHIFT_CONST(8)
+#define MC_TIMEOUT_DC_0_DISPLAY0C_TMVAL_FIELD                   (_MK_MASK_CONST(0xf) << MC_TIMEOUT_DC_0_DISPLAY0C_TMVAL_SHIFT)
+#define MC_TIMEOUT_DC_0_DISPLAY0C_TMVAL_RANGE                   11:8
+#define MC_TIMEOUT_DC_0_DISPLAY0C_TMVAL_WOFFSET                 0x0
+#define MC_TIMEOUT_DC_0_DISPLAY0C_TMVAL_DEFAULT                 _MK_MASK_CONST(0x8)
+#define MC_TIMEOUT_DC_0_DISPLAY0C_TMVAL_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_DC_0_DISPLAY0C_TMVAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_DC_0_DISPLAY0C_TMVAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_DC_0_DISPLAY1B_TMVAL_SHIFT                   _MK_SHIFT_CONST(12)
+#define MC_TIMEOUT_DC_0_DISPLAY1B_TMVAL_FIELD                   (_MK_MASK_CONST(0xf) << MC_TIMEOUT_DC_0_DISPLAY1B_TMVAL_SHIFT)
+#define MC_TIMEOUT_DC_0_DISPLAY1B_TMVAL_RANGE                   15:12
+#define MC_TIMEOUT_DC_0_DISPLAY1B_TMVAL_WOFFSET                 0x0
+#define MC_TIMEOUT_DC_0_DISPLAY1B_TMVAL_DEFAULT                 _MK_MASK_CONST(0x8)
+#define MC_TIMEOUT_DC_0_DISPLAY1B_TMVAL_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_DC_0_DISPLAY1B_TMVAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_DC_0_DISPLAY1B_TMVAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_DC_0_DISPLAYHC_TMVAL_SHIFT                   _MK_SHIFT_CONST(16)
+#define MC_TIMEOUT_DC_0_DISPLAYHC_TMVAL_FIELD                   (_MK_MASK_CONST(0xf) << MC_TIMEOUT_DC_0_DISPLAYHC_TMVAL_SHIFT)
+#define MC_TIMEOUT_DC_0_DISPLAYHC_TMVAL_RANGE                   19:16
+#define MC_TIMEOUT_DC_0_DISPLAYHC_TMVAL_WOFFSET                 0x0
+#define MC_TIMEOUT_DC_0_DISPLAYHC_TMVAL_DEFAULT                 _MK_MASK_CONST(0x8)
+#define MC_TIMEOUT_DC_0_DISPLAYHC_TMVAL_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_DC_0_DISPLAYHC_TMVAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_DC_0_DISPLAYHC_TMVAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register MC_TIMEOUT_DCB_0  
+#define MC_TIMEOUT_DCB_0                        _MK_ADDR_CONST(0x1c0)
+#define MC_TIMEOUT_DCB_0_SECURE                         0x0
+#define MC_TIMEOUT_DCB_0_WORD_COUNT                     0x1
+#define MC_TIMEOUT_DCB_0_RESET_VAL                      _MK_MASK_CONST(0x88888)
+#define MC_TIMEOUT_DCB_0_RESET_MASK                     _MK_MASK_CONST(0xfffff)
+#define MC_TIMEOUT_DCB_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_DCB_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_DCB_0_READ_MASK                      _MK_MASK_CONST(0xfffff)
+#define MC_TIMEOUT_DCB_0_WRITE_MASK                     _MK_MASK_CONST(0xfffff)
+#define MC_TIMEOUT_DCB_0_DISPLAY0AB_TMVAL_SHIFT                 _MK_SHIFT_CONST(0)
+#define MC_TIMEOUT_DCB_0_DISPLAY0AB_TMVAL_FIELD                 (_MK_MASK_CONST(0xf) << MC_TIMEOUT_DCB_0_DISPLAY0AB_TMVAL_SHIFT)
+#define MC_TIMEOUT_DCB_0_DISPLAY0AB_TMVAL_RANGE                 3:0
+#define MC_TIMEOUT_DCB_0_DISPLAY0AB_TMVAL_WOFFSET                       0x0
+#define MC_TIMEOUT_DCB_0_DISPLAY0AB_TMVAL_DEFAULT                       _MK_MASK_CONST(0x8)
+#define MC_TIMEOUT_DCB_0_DISPLAY0AB_TMVAL_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_DCB_0_DISPLAY0AB_TMVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_DCB_0_DISPLAY0AB_TMVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_DCB_0_DISPLAY0BB_TMVAL_SHIFT                 _MK_SHIFT_CONST(4)
+#define MC_TIMEOUT_DCB_0_DISPLAY0BB_TMVAL_FIELD                 (_MK_MASK_CONST(0xf) << MC_TIMEOUT_DCB_0_DISPLAY0BB_TMVAL_SHIFT)
+#define MC_TIMEOUT_DCB_0_DISPLAY0BB_TMVAL_RANGE                 7:4
+#define MC_TIMEOUT_DCB_0_DISPLAY0BB_TMVAL_WOFFSET                       0x0
+#define MC_TIMEOUT_DCB_0_DISPLAY0BB_TMVAL_DEFAULT                       _MK_MASK_CONST(0x8)
+#define MC_TIMEOUT_DCB_0_DISPLAY0BB_TMVAL_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_DCB_0_DISPLAY0BB_TMVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_DCB_0_DISPLAY0BB_TMVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_DCB_0_DISPLAY0CB_TMVAL_SHIFT                 _MK_SHIFT_CONST(8)
+#define MC_TIMEOUT_DCB_0_DISPLAY0CB_TMVAL_FIELD                 (_MK_MASK_CONST(0xf) << MC_TIMEOUT_DCB_0_DISPLAY0CB_TMVAL_SHIFT)
+#define MC_TIMEOUT_DCB_0_DISPLAY0CB_TMVAL_RANGE                 11:8
+#define MC_TIMEOUT_DCB_0_DISPLAY0CB_TMVAL_WOFFSET                       0x0
+#define MC_TIMEOUT_DCB_0_DISPLAY0CB_TMVAL_DEFAULT                       _MK_MASK_CONST(0x8)
+#define MC_TIMEOUT_DCB_0_DISPLAY0CB_TMVAL_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_DCB_0_DISPLAY0CB_TMVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_DCB_0_DISPLAY0CB_TMVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_DCB_0_DISPLAY1BB_TMVAL_SHIFT                 _MK_SHIFT_CONST(12)
+#define MC_TIMEOUT_DCB_0_DISPLAY1BB_TMVAL_FIELD                 (_MK_MASK_CONST(0xf) << MC_TIMEOUT_DCB_0_DISPLAY1BB_TMVAL_SHIFT)
+#define MC_TIMEOUT_DCB_0_DISPLAY1BB_TMVAL_RANGE                 15:12
+#define MC_TIMEOUT_DCB_0_DISPLAY1BB_TMVAL_WOFFSET                       0x0
+#define MC_TIMEOUT_DCB_0_DISPLAY1BB_TMVAL_DEFAULT                       _MK_MASK_CONST(0x8)
+#define MC_TIMEOUT_DCB_0_DISPLAY1BB_TMVAL_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_DCB_0_DISPLAY1BB_TMVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_DCB_0_DISPLAY1BB_TMVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_DCB_0_DISPLAYHCB_TMVAL_SHIFT                 _MK_SHIFT_CONST(16)
+#define MC_TIMEOUT_DCB_0_DISPLAYHCB_TMVAL_FIELD                 (_MK_MASK_CONST(0xf) << MC_TIMEOUT_DCB_0_DISPLAYHCB_TMVAL_SHIFT)
+#define MC_TIMEOUT_DCB_0_DISPLAYHCB_TMVAL_RANGE                 19:16
+#define MC_TIMEOUT_DCB_0_DISPLAYHCB_TMVAL_WOFFSET                       0x0
+#define MC_TIMEOUT_DCB_0_DISPLAYHCB_TMVAL_DEFAULT                       _MK_MASK_CONST(0x8)
+#define MC_TIMEOUT_DCB_0_DISPLAYHCB_TMVAL_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_DCB_0_DISPLAYHCB_TMVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_DCB_0_DISPLAYHCB_TMVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register MC_TIMEOUT_EPP_0  
+#define MC_TIMEOUT_EPP_0                        _MK_ADDR_CONST(0x1c4)
+#define MC_TIMEOUT_EPP_0_SECURE                         0x0
+#define MC_TIMEOUT_EPP_0_WORD_COUNT                     0x1
+#define MC_TIMEOUT_EPP_0_RESET_VAL                      _MK_MASK_CONST(0x8888)
+#define MC_TIMEOUT_EPP_0_RESET_MASK                     _MK_MASK_CONST(0xffff)
+#define MC_TIMEOUT_EPP_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_EPP_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_EPP_0_READ_MASK                      _MK_MASK_CONST(0xffff)
+#define MC_TIMEOUT_EPP_0_WRITE_MASK                     _MK_MASK_CONST(0xffff)
+#define MC_TIMEOUT_EPP_0_EPPUP_TMVAL_SHIFT                      _MK_SHIFT_CONST(0)
+#define MC_TIMEOUT_EPP_0_EPPUP_TMVAL_FIELD                      (_MK_MASK_CONST(0xf) << MC_TIMEOUT_EPP_0_EPPUP_TMVAL_SHIFT)
+#define MC_TIMEOUT_EPP_0_EPPUP_TMVAL_RANGE                      3:0
+#define MC_TIMEOUT_EPP_0_EPPUP_TMVAL_WOFFSET                    0x0
+#define MC_TIMEOUT_EPP_0_EPPUP_TMVAL_DEFAULT                    _MK_MASK_CONST(0x8)
+#define MC_TIMEOUT_EPP_0_EPPUP_TMVAL_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_EPP_0_EPPUP_TMVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_EPP_0_EPPUP_TMVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_EPP_0_EPPU_TMVAL_SHIFT                       _MK_SHIFT_CONST(4)
+#define MC_TIMEOUT_EPP_0_EPPU_TMVAL_FIELD                       (_MK_MASK_CONST(0xf) << MC_TIMEOUT_EPP_0_EPPU_TMVAL_SHIFT)
+#define MC_TIMEOUT_EPP_0_EPPU_TMVAL_RANGE                       7:4
+#define MC_TIMEOUT_EPP_0_EPPU_TMVAL_WOFFSET                     0x0
+#define MC_TIMEOUT_EPP_0_EPPU_TMVAL_DEFAULT                     _MK_MASK_CONST(0x8)
+#define MC_TIMEOUT_EPP_0_EPPU_TMVAL_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_EPP_0_EPPU_TMVAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_EPP_0_EPPU_TMVAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_EPP_0_EPPV_TMVAL_SHIFT                       _MK_SHIFT_CONST(8)
+#define MC_TIMEOUT_EPP_0_EPPV_TMVAL_FIELD                       (_MK_MASK_CONST(0xf) << MC_TIMEOUT_EPP_0_EPPV_TMVAL_SHIFT)
+#define MC_TIMEOUT_EPP_0_EPPV_TMVAL_RANGE                       11:8
+#define MC_TIMEOUT_EPP_0_EPPV_TMVAL_WOFFSET                     0x0
+#define MC_TIMEOUT_EPP_0_EPPV_TMVAL_DEFAULT                     _MK_MASK_CONST(0x8)
+#define MC_TIMEOUT_EPP_0_EPPV_TMVAL_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_EPP_0_EPPV_TMVAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_EPP_0_EPPV_TMVAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_EPP_0_EPPY_TMVAL_SHIFT                       _MK_SHIFT_CONST(12)
+#define MC_TIMEOUT_EPP_0_EPPY_TMVAL_FIELD                       (_MK_MASK_CONST(0xf) << MC_TIMEOUT_EPP_0_EPPY_TMVAL_SHIFT)
+#define MC_TIMEOUT_EPP_0_EPPY_TMVAL_RANGE                       15:12
+#define MC_TIMEOUT_EPP_0_EPPY_TMVAL_WOFFSET                     0x0
+#define MC_TIMEOUT_EPP_0_EPPY_TMVAL_DEFAULT                     _MK_MASK_CONST(0x8)
+#define MC_TIMEOUT_EPP_0_EPPY_TMVAL_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_EPP_0_EPPY_TMVAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_EPP_0_EPPY_TMVAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register MC_TIMEOUT_G2_0  
+#define MC_TIMEOUT_G2_0                 _MK_ADDR_CONST(0x1c8)
+#define MC_TIMEOUT_G2_0_SECURE                  0x0
+#define MC_TIMEOUT_G2_0_WORD_COUNT                      0x1
+#define MC_TIMEOUT_G2_0_RESET_VAL                       _MK_MASK_CONST(0x8888)
+#define MC_TIMEOUT_G2_0_RESET_MASK                      _MK_MASK_CONST(0xffff)
+#define MC_TIMEOUT_G2_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_G2_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_G2_0_READ_MASK                       _MK_MASK_CONST(0xffff)
+#define MC_TIMEOUT_G2_0_WRITE_MASK                      _MK_MASK_CONST(0xffff)
+#define MC_TIMEOUT_G2_0_G2PR_TMVAL_SHIFT                        _MK_SHIFT_CONST(0)
+#define MC_TIMEOUT_G2_0_G2PR_TMVAL_FIELD                        (_MK_MASK_CONST(0xf) << MC_TIMEOUT_G2_0_G2PR_TMVAL_SHIFT)
+#define MC_TIMEOUT_G2_0_G2PR_TMVAL_RANGE                        3:0
+#define MC_TIMEOUT_G2_0_G2PR_TMVAL_WOFFSET                      0x0
+#define MC_TIMEOUT_G2_0_G2PR_TMVAL_DEFAULT                      _MK_MASK_CONST(0x8)
+#define MC_TIMEOUT_G2_0_G2PR_TMVAL_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_G2_0_G2PR_TMVAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_G2_0_G2PR_TMVAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_G2_0_G2SR_TMVAL_SHIFT                        _MK_SHIFT_CONST(4)
+#define MC_TIMEOUT_G2_0_G2SR_TMVAL_FIELD                        (_MK_MASK_CONST(0xf) << MC_TIMEOUT_G2_0_G2SR_TMVAL_SHIFT)
+#define MC_TIMEOUT_G2_0_G2SR_TMVAL_RANGE                        7:4
+#define MC_TIMEOUT_G2_0_G2SR_TMVAL_WOFFSET                      0x0
+#define MC_TIMEOUT_G2_0_G2SR_TMVAL_DEFAULT                      _MK_MASK_CONST(0x8)
+#define MC_TIMEOUT_G2_0_G2SR_TMVAL_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_G2_0_G2SR_TMVAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_G2_0_G2SR_TMVAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_G2_0_G2DR_TMVAL_SHIFT                        _MK_SHIFT_CONST(8)
+#define MC_TIMEOUT_G2_0_G2DR_TMVAL_FIELD                        (_MK_MASK_CONST(0xf) << MC_TIMEOUT_G2_0_G2DR_TMVAL_SHIFT)
+#define MC_TIMEOUT_G2_0_G2DR_TMVAL_RANGE                        11:8
+#define MC_TIMEOUT_G2_0_G2DR_TMVAL_WOFFSET                      0x0
+#define MC_TIMEOUT_G2_0_G2DR_TMVAL_DEFAULT                      _MK_MASK_CONST(0x8)
+#define MC_TIMEOUT_G2_0_G2DR_TMVAL_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_G2_0_G2DR_TMVAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_G2_0_G2DR_TMVAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_G2_0_G2DW_TMVAL_SHIFT                        _MK_SHIFT_CONST(12)
+#define MC_TIMEOUT_G2_0_G2DW_TMVAL_FIELD                        (_MK_MASK_CONST(0xf) << MC_TIMEOUT_G2_0_G2DW_TMVAL_SHIFT)
+#define MC_TIMEOUT_G2_0_G2DW_TMVAL_RANGE                        15:12
+#define MC_TIMEOUT_G2_0_G2DW_TMVAL_WOFFSET                      0x0
+#define MC_TIMEOUT_G2_0_G2DW_TMVAL_DEFAULT                      _MK_MASK_CONST(0x8)
+#define MC_TIMEOUT_G2_0_G2DW_TMVAL_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_G2_0_G2DW_TMVAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_G2_0_G2DW_TMVAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register MC_TIMEOUT_HC_0  
+#define MC_TIMEOUT_HC_0                 _MK_ADDR_CONST(0x1cc)
+#define MC_TIMEOUT_HC_0_SECURE                  0x0
+#define MC_TIMEOUT_HC_0_WORD_COUNT                      0x1
+#define MC_TIMEOUT_HC_0_RESET_VAL                       _MK_MASK_CONST(0x888)
+#define MC_TIMEOUT_HC_0_RESET_MASK                      _MK_MASK_CONST(0xfff)
+#define MC_TIMEOUT_HC_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_HC_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_HC_0_READ_MASK                       _MK_MASK_CONST(0xfff)
+#define MC_TIMEOUT_HC_0_WRITE_MASK                      _MK_MASK_CONST(0xfff)
+#define MC_TIMEOUT_HC_0_HOST1XDMAR_TMVAL_SHIFT                  _MK_SHIFT_CONST(0)
+#define MC_TIMEOUT_HC_0_HOST1XDMAR_TMVAL_FIELD                  (_MK_MASK_CONST(0xf) << MC_TIMEOUT_HC_0_HOST1XDMAR_TMVAL_SHIFT)
+#define MC_TIMEOUT_HC_0_HOST1XDMAR_TMVAL_RANGE                  3:0
+#define MC_TIMEOUT_HC_0_HOST1XDMAR_TMVAL_WOFFSET                        0x0
+#define MC_TIMEOUT_HC_0_HOST1XDMAR_TMVAL_DEFAULT                        _MK_MASK_CONST(0x8)
+#define MC_TIMEOUT_HC_0_HOST1XDMAR_TMVAL_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_HC_0_HOST1XDMAR_TMVAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_HC_0_HOST1XDMAR_TMVAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_HC_0_HOST1XR_TMVAL_SHIFT                     _MK_SHIFT_CONST(4)
+#define MC_TIMEOUT_HC_0_HOST1XR_TMVAL_FIELD                     (_MK_MASK_CONST(0xf) << MC_TIMEOUT_HC_0_HOST1XR_TMVAL_SHIFT)
+#define MC_TIMEOUT_HC_0_HOST1XR_TMVAL_RANGE                     7:4
+#define MC_TIMEOUT_HC_0_HOST1XR_TMVAL_WOFFSET                   0x0
+#define MC_TIMEOUT_HC_0_HOST1XR_TMVAL_DEFAULT                   _MK_MASK_CONST(0x8)
+#define MC_TIMEOUT_HC_0_HOST1XR_TMVAL_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_HC_0_HOST1XR_TMVAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_HC_0_HOST1XR_TMVAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_HC_0_HOST1XW_TMVAL_SHIFT                     _MK_SHIFT_CONST(8)
+#define MC_TIMEOUT_HC_0_HOST1XW_TMVAL_FIELD                     (_MK_MASK_CONST(0xf) << MC_TIMEOUT_HC_0_HOST1XW_TMVAL_SHIFT)
+#define MC_TIMEOUT_HC_0_HOST1XW_TMVAL_RANGE                     11:8
+#define MC_TIMEOUT_HC_0_HOST1XW_TMVAL_WOFFSET                   0x0
+#define MC_TIMEOUT_HC_0_HOST1XW_TMVAL_DEFAULT                   _MK_MASK_CONST(0x8)
+#define MC_TIMEOUT_HC_0_HOST1XW_TMVAL_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_HC_0_HOST1XW_TMVAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_HC_0_HOST1XW_TMVAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register MC_TIMEOUT_ISP_0  
+#define MC_TIMEOUT_ISP_0                        _MK_ADDR_CONST(0x1d0)
+#define MC_TIMEOUT_ISP_0_SECURE                         0x0
+#define MC_TIMEOUT_ISP_0_WORD_COUNT                     0x1
+#define MC_TIMEOUT_ISP_0_RESET_VAL                      _MK_MASK_CONST(0x8)
+#define MC_TIMEOUT_ISP_0_RESET_MASK                     _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_ISP_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_ISP_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_ISP_0_READ_MASK                      _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_ISP_0_WRITE_MASK                     _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_ISP_0_ISPW_TMVAL_SHIFT                       _MK_SHIFT_CONST(0)
+#define MC_TIMEOUT_ISP_0_ISPW_TMVAL_FIELD                       (_MK_MASK_CONST(0xf) << MC_TIMEOUT_ISP_0_ISPW_TMVAL_SHIFT)
+#define MC_TIMEOUT_ISP_0_ISPW_TMVAL_RANGE                       3:0
+#define MC_TIMEOUT_ISP_0_ISPW_TMVAL_WOFFSET                     0x0
+#define MC_TIMEOUT_ISP_0_ISPW_TMVAL_DEFAULT                     _MK_MASK_CONST(0x8)
+#define MC_TIMEOUT_ISP_0_ISPW_TMVAL_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_ISP_0_ISPW_TMVAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_ISP_0_ISPW_TMVAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register MC_TIMEOUT_MPCORE_0  
+#define MC_TIMEOUT_MPCORE_0                     _MK_ADDR_CONST(0x1d4)
+#define MC_TIMEOUT_MPCORE_0_SECURE                      0x0
+#define MC_TIMEOUT_MPCORE_0_WORD_COUNT                  0x1
+#define MC_TIMEOUT_MPCORE_0_RESET_VAL                   _MK_MASK_CONST(0x88)
+#define MC_TIMEOUT_MPCORE_0_RESET_MASK                  _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_MPCORE_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_MPCORE_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_MPCORE_0_READ_MASK                   _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_MPCORE_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_MPCORE_0_MPCORER_TMVAL_SHIFT                 _MK_SHIFT_CONST(0)
+#define MC_TIMEOUT_MPCORE_0_MPCORER_TMVAL_FIELD                 (_MK_MASK_CONST(0xf) << MC_TIMEOUT_MPCORE_0_MPCORER_TMVAL_SHIFT)
+#define MC_TIMEOUT_MPCORE_0_MPCORER_TMVAL_RANGE                 3:0
+#define MC_TIMEOUT_MPCORE_0_MPCORER_TMVAL_WOFFSET                       0x0
+#define MC_TIMEOUT_MPCORE_0_MPCORER_TMVAL_DEFAULT                       _MK_MASK_CONST(0x8)
+#define MC_TIMEOUT_MPCORE_0_MPCORER_TMVAL_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_MPCORE_0_MPCORER_TMVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_MPCORE_0_MPCORER_TMVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_MPCORE_0_MPCOREW_TMVAL_SHIFT                 _MK_SHIFT_CONST(4)
+#define MC_TIMEOUT_MPCORE_0_MPCOREW_TMVAL_FIELD                 (_MK_MASK_CONST(0xf) << MC_TIMEOUT_MPCORE_0_MPCOREW_TMVAL_SHIFT)
+#define MC_TIMEOUT_MPCORE_0_MPCOREW_TMVAL_RANGE                 7:4
+#define MC_TIMEOUT_MPCORE_0_MPCOREW_TMVAL_WOFFSET                       0x0
+#define MC_TIMEOUT_MPCORE_0_MPCOREW_TMVAL_DEFAULT                       _MK_MASK_CONST(0x8)
+#define MC_TIMEOUT_MPCORE_0_MPCOREW_TMVAL_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_MPCORE_0_MPCOREW_TMVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_MPCORE_0_MPCOREW_TMVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register MC_TIMEOUT_MPEA_0  
+#define MC_TIMEOUT_MPEA_0                       _MK_ADDR_CONST(0x1d8)
+#define MC_TIMEOUT_MPEA_0_SECURE                        0x0
+#define MC_TIMEOUT_MPEA_0_WORD_COUNT                    0x1
+#define MC_TIMEOUT_MPEA_0_RESET_VAL                     _MK_MASK_CONST(0x8)
+#define MC_TIMEOUT_MPEA_0_RESET_MASK                    _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_MPEA_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_MPEA_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_MPEA_0_READ_MASK                     _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_MPEA_0_WRITE_MASK                    _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_MPEA_0_MPEAMEMRD_TMVAL_SHIFT                 _MK_SHIFT_CONST(0)
+#define MC_TIMEOUT_MPEA_0_MPEAMEMRD_TMVAL_FIELD                 (_MK_MASK_CONST(0xf) << MC_TIMEOUT_MPEA_0_MPEAMEMRD_TMVAL_SHIFT)
+#define MC_TIMEOUT_MPEA_0_MPEAMEMRD_TMVAL_RANGE                 3:0
+#define MC_TIMEOUT_MPEA_0_MPEAMEMRD_TMVAL_WOFFSET                       0x0
+#define MC_TIMEOUT_MPEA_0_MPEAMEMRD_TMVAL_DEFAULT                       _MK_MASK_CONST(0x8)
+#define MC_TIMEOUT_MPEA_0_MPEAMEMRD_TMVAL_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_MPEA_0_MPEAMEMRD_TMVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_MPEA_0_MPEAMEMRD_TMVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register MC_TIMEOUT_MPEB_0  
+#define MC_TIMEOUT_MPEB_0                       _MK_ADDR_CONST(0x1dc)
+#define MC_TIMEOUT_MPEB_0_SECURE                        0x0
+#define MC_TIMEOUT_MPEB_0_WORD_COUNT                    0x1
+#define MC_TIMEOUT_MPEB_0_RESET_VAL                     _MK_MASK_CONST(0x888)
+#define MC_TIMEOUT_MPEB_0_RESET_MASK                    _MK_MASK_CONST(0xfff)
+#define MC_TIMEOUT_MPEB_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_MPEB_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_MPEB_0_READ_MASK                     _MK_MASK_CONST(0xfff)
+#define MC_TIMEOUT_MPEB_0_WRITE_MASK                    _MK_MASK_CONST(0xfff)
+#define MC_TIMEOUT_MPEB_0_MPEUNIFBR_TMVAL_SHIFT                 _MK_SHIFT_CONST(0)
+#define MC_TIMEOUT_MPEB_0_MPEUNIFBR_TMVAL_FIELD                 (_MK_MASK_CONST(0xf) << MC_TIMEOUT_MPEB_0_MPEUNIFBR_TMVAL_SHIFT)
+#define MC_TIMEOUT_MPEB_0_MPEUNIFBR_TMVAL_RANGE                 3:0
+#define MC_TIMEOUT_MPEB_0_MPEUNIFBR_TMVAL_WOFFSET                       0x0
+#define MC_TIMEOUT_MPEB_0_MPEUNIFBR_TMVAL_DEFAULT                       _MK_MASK_CONST(0x8)
+#define MC_TIMEOUT_MPEB_0_MPEUNIFBR_TMVAL_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_MPEB_0_MPEUNIFBR_TMVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_MPEB_0_MPEUNIFBR_TMVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_MPEB_0_MPE_IPRED_TMVAL_SHIFT                 _MK_SHIFT_CONST(4)
+#define MC_TIMEOUT_MPEB_0_MPE_IPRED_TMVAL_FIELD                 (_MK_MASK_CONST(0xf) << MC_TIMEOUT_MPEB_0_MPE_IPRED_TMVAL_SHIFT)
+#define MC_TIMEOUT_MPEB_0_MPE_IPRED_TMVAL_RANGE                 7:4
+#define MC_TIMEOUT_MPEB_0_MPE_IPRED_TMVAL_WOFFSET                       0x0
+#define MC_TIMEOUT_MPEB_0_MPE_IPRED_TMVAL_DEFAULT                       _MK_MASK_CONST(0x8)
+#define MC_TIMEOUT_MPEB_0_MPE_IPRED_TMVAL_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_MPEB_0_MPE_IPRED_TMVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_MPEB_0_MPE_IPRED_TMVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_MPEB_0_MPEUNIFBW_TMVAL_SHIFT                 _MK_SHIFT_CONST(8)
+#define MC_TIMEOUT_MPEB_0_MPEUNIFBW_TMVAL_FIELD                 (_MK_MASK_CONST(0xf) << MC_TIMEOUT_MPEB_0_MPEUNIFBW_TMVAL_SHIFT)
+#define MC_TIMEOUT_MPEB_0_MPEUNIFBW_TMVAL_RANGE                 11:8
+#define MC_TIMEOUT_MPEB_0_MPEUNIFBW_TMVAL_WOFFSET                       0x0
+#define MC_TIMEOUT_MPEB_0_MPEUNIFBW_TMVAL_DEFAULT                       _MK_MASK_CONST(0x8)
+#define MC_TIMEOUT_MPEB_0_MPEUNIFBW_TMVAL_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_MPEB_0_MPEUNIFBW_TMVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_MPEB_0_MPEUNIFBW_TMVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register MC_TIMEOUT_MPEC_0  
+#define MC_TIMEOUT_MPEC_0                       _MK_ADDR_CONST(0x1e0)
+#define MC_TIMEOUT_MPEC_0_SECURE                        0x0
+#define MC_TIMEOUT_MPEC_0_WORD_COUNT                    0x1
+#define MC_TIMEOUT_MPEC_0_RESET_VAL                     _MK_MASK_CONST(0x88)
+#define MC_TIMEOUT_MPEC_0_RESET_MASK                    _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_MPEC_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_MPEC_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_MPEC_0_READ_MASK                     _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_MPEC_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_MPEC_0_MPECSRD_TMVAL_SHIFT                   _MK_SHIFT_CONST(0)
+#define MC_TIMEOUT_MPEC_0_MPECSRD_TMVAL_FIELD                   (_MK_MASK_CONST(0xf) << MC_TIMEOUT_MPEC_0_MPECSRD_TMVAL_SHIFT)
+#define MC_TIMEOUT_MPEC_0_MPECSRD_TMVAL_RANGE                   3:0
+#define MC_TIMEOUT_MPEC_0_MPECSRD_TMVAL_WOFFSET                 0x0
+#define MC_TIMEOUT_MPEC_0_MPECSRD_TMVAL_DEFAULT                 _MK_MASK_CONST(0x8)
+#define MC_TIMEOUT_MPEC_0_MPECSRD_TMVAL_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_MPEC_0_MPECSRD_TMVAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_MPEC_0_MPECSRD_TMVAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_MPEC_0_MPECSWR_TMVAL_SHIFT                   _MK_SHIFT_CONST(4)
+#define MC_TIMEOUT_MPEC_0_MPECSWR_TMVAL_FIELD                   (_MK_MASK_CONST(0xf) << MC_TIMEOUT_MPEC_0_MPECSWR_TMVAL_SHIFT)
+#define MC_TIMEOUT_MPEC_0_MPECSWR_TMVAL_RANGE                   7:4
+#define MC_TIMEOUT_MPEC_0_MPECSWR_TMVAL_WOFFSET                 0x0
+#define MC_TIMEOUT_MPEC_0_MPECSWR_TMVAL_DEFAULT                 _MK_MASK_CONST(0x8)
+#define MC_TIMEOUT_MPEC_0_MPECSWR_TMVAL_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_MPEC_0_MPECSWR_TMVAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_MPEC_0_MPECSWR_TMVAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register MC_TIMEOUT_NV_0  
+#define MC_TIMEOUT_NV_0                 _MK_ADDR_CONST(0x1e4)
+#define MC_TIMEOUT_NV_0_SECURE                  0x0
+#define MC_TIMEOUT_NV_0_WORD_COUNT                      0x1
+#define MC_TIMEOUT_NV_0_RESET_VAL                       _MK_MASK_CONST(0x8888)
+#define MC_TIMEOUT_NV_0_RESET_MASK                      _MK_MASK_CONST(0xffff)
+#define MC_TIMEOUT_NV_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_NV_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_NV_0_READ_MASK                       _MK_MASK_CONST(0xffff)
+#define MC_TIMEOUT_NV_0_WRITE_MASK                      _MK_MASK_CONST(0xffff)
+#define MC_TIMEOUT_NV_0_FDCDRD_TMVAL_SHIFT                      _MK_SHIFT_CONST(0)
+#define MC_TIMEOUT_NV_0_FDCDRD_TMVAL_FIELD                      (_MK_MASK_CONST(0xf) << MC_TIMEOUT_NV_0_FDCDRD_TMVAL_SHIFT)
+#define MC_TIMEOUT_NV_0_FDCDRD_TMVAL_RANGE                      3:0
+#define MC_TIMEOUT_NV_0_FDCDRD_TMVAL_WOFFSET                    0x0
+#define MC_TIMEOUT_NV_0_FDCDRD_TMVAL_DEFAULT                    _MK_MASK_CONST(0x8)
+#define MC_TIMEOUT_NV_0_FDCDRD_TMVAL_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_NV_0_FDCDRD_TMVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_NV_0_FDCDRD_TMVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_NV_0_IDXSRD_TMVAL_SHIFT                      _MK_SHIFT_CONST(4)
+#define MC_TIMEOUT_NV_0_IDXSRD_TMVAL_FIELD                      (_MK_MASK_CONST(0xf) << MC_TIMEOUT_NV_0_IDXSRD_TMVAL_SHIFT)
+#define MC_TIMEOUT_NV_0_IDXSRD_TMVAL_RANGE                      7:4
+#define MC_TIMEOUT_NV_0_IDXSRD_TMVAL_WOFFSET                    0x0
+#define MC_TIMEOUT_NV_0_IDXSRD_TMVAL_DEFAULT                    _MK_MASK_CONST(0x8)
+#define MC_TIMEOUT_NV_0_IDXSRD_TMVAL_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_NV_0_IDXSRD_TMVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_NV_0_IDXSRD_TMVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_NV_0_TEXSRD_TMVAL_SHIFT                      _MK_SHIFT_CONST(8)
+#define MC_TIMEOUT_NV_0_TEXSRD_TMVAL_FIELD                      (_MK_MASK_CONST(0xf) << MC_TIMEOUT_NV_0_TEXSRD_TMVAL_SHIFT)
+#define MC_TIMEOUT_NV_0_TEXSRD_TMVAL_RANGE                      11:8
+#define MC_TIMEOUT_NV_0_TEXSRD_TMVAL_WOFFSET                    0x0
+#define MC_TIMEOUT_NV_0_TEXSRD_TMVAL_DEFAULT                    _MK_MASK_CONST(0x8)
+#define MC_TIMEOUT_NV_0_TEXSRD_TMVAL_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_NV_0_TEXSRD_TMVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_NV_0_TEXSRD_TMVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_NV_0_FDCDWR_TMVAL_SHIFT                      _MK_SHIFT_CONST(12)
+#define MC_TIMEOUT_NV_0_FDCDWR_TMVAL_FIELD                      (_MK_MASK_CONST(0xf) << MC_TIMEOUT_NV_0_FDCDWR_TMVAL_SHIFT)
+#define MC_TIMEOUT_NV_0_FDCDWR_TMVAL_RANGE                      15:12
+#define MC_TIMEOUT_NV_0_FDCDWR_TMVAL_WOFFSET                    0x0
+#define MC_TIMEOUT_NV_0_FDCDWR_TMVAL_DEFAULT                    _MK_MASK_CONST(0x8)
+#define MC_TIMEOUT_NV_0_FDCDWR_TMVAL_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_NV_0_FDCDWR_TMVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_NV_0_FDCDWR_TMVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register MC_TIMEOUT_PPCS_0  
+#define MC_TIMEOUT_PPCS_0                       _MK_ADDR_CONST(0x1e8)
+#define MC_TIMEOUT_PPCS_0_SECURE                        0x0
+#define MC_TIMEOUT_PPCS_0_WORD_COUNT                    0x1
+#define MC_TIMEOUT_PPCS_0_RESET_VAL                     _MK_MASK_CONST(0x8888)
+#define MC_TIMEOUT_PPCS_0_RESET_MASK                    _MK_MASK_CONST(0xffff)
+#define MC_TIMEOUT_PPCS_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_PPCS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_PPCS_0_READ_MASK                     _MK_MASK_CONST(0xffff)
+#define MC_TIMEOUT_PPCS_0_WRITE_MASK                    _MK_MASK_CONST(0xffff)
+#define MC_TIMEOUT_PPCS_0_PPCSAHBDMAR_TMVAL_SHIFT                       _MK_SHIFT_CONST(0)
+#define MC_TIMEOUT_PPCS_0_PPCSAHBDMAR_TMVAL_FIELD                       (_MK_MASK_CONST(0xf) << MC_TIMEOUT_PPCS_0_PPCSAHBDMAR_TMVAL_SHIFT)
+#define MC_TIMEOUT_PPCS_0_PPCSAHBDMAR_TMVAL_RANGE                       3:0
+#define MC_TIMEOUT_PPCS_0_PPCSAHBDMAR_TMVAL_WOFFSET                     0x0
+#define MC_TIMEOUT_PPCS_0_PPCSAHBDMAR_TMVAL_DEFAULT                     _MK_MASK_CONST(0x8)
+#define MC_TIMEOUT_PPCS_0_PPCSAHBDMAR_TMVAL_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_PPCS_0_PPCSAHBDMAR_TMVAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_PPCS_0_PPCSAHBDMAR_TMVAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_PPCS_0_PPCSAHBSLVR_TMVAL_SHIFT                       _MK_SHIFT_CONST(4)
+#define MC_TIMEOUT_PPCS_0_PPCSAHBSLVR_TMVAL_FIELD                       (_MK_MASK_CONST(0xf) << MC_TIMEOUT_PPCS_0_PPCSAHBSLVR_TMVAL_SHIFT)
+#define MC_TIMEOUT_PPCS_0_PPCSAHBSLVR_TMVAL_RANGE                       7:4
+#define MC_TIMEOUT_PPCS_0_PPCSAHBSLVR_TMVAL_WOFFSET                     0x0
+#define MC_TIMEOUT_PPCS_0_PPCSAHBSLVR_TMVAL_DEFAULT                     _MK_MASK_CONST(0x8)
+#define MC_TIMEOUT_PPCS_0_PPCSAHBSLVR_TMVAL_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_PPCS_0_PPCSAHBSLVR_TMVAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_PPCS_0_PPCSAHBSLVR_TMVAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_PPCS_0_PPCSAHBDMAW_TMVAL_SHIFT                       _MK_SHIFT_CONST(8)
+#define MC_TIMEOUT_PPCS_0_PPCSAHBDMAW_TMVAL_FIELD                       (_MK_MASK_CONST(0xf) << MC_TIMEOUT_PPCS_0_PPCSAHBDMAW_TMVAL_SHIFT)
+#define MC_TIMEOUT_PPCS_0_PPCSAHBDMAW_TMVAL_RANGE                       11:8
+#define MC_TIMEOUT_PPCS_0_PPCSAHBDMAW_TMVAL_WOFFSET                     0x0
+#define MC_TIMEOUT_PPCS_0_PPCSAHBDMAW_TMVAL_DEFAULT                     _MK_MASK_CONST(0x8)
+#define MC_TIMEOUT_PPCS_0_PPCSAHBDMAW_TMVAL_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_PPCS_0_PPCSAHBDMAW_TMVAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_PPCS_0_PPCSAHBDMAW_TMVAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_PPCS_0_PPCSAHBSLVW_TMVAL_SHIFT                       _MK_SHIFT_CONST(12)
+#define MC_TIMEOUT_PPCS_0_PPCSAHBSLVW_TMVAL_FIELD                       (_MK_MASK_CONST(0xf) << MC_TIMEOUT_PPCS_0_PPCSAHBSLVW_TMVAL_SHIFT)
+#define MC_TIMEOUT_PPCS_0_PPCSAHBSLVW_TMVAL_RANGE                       15:12
+#define MC_TIMEOUT_PPCS_0_PPCSAHBSLVW_TMVAL_WOFFSET                     0x0
+#define MC_TIMEOUT_PPCS_0_PPCSAHBSLVW_TMVAL_DEFAULT                     _MK_MASK_CONST(0x8)
+#define MC_TIMEOUT_PPCS_0_PPCSAHBSLVW_TMVAL_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_PPCS_0_PPCSAHBSLVW_TMVAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_PPCS_0_PPCSAHBSLVW_TMVAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register MC_TIMEOUT_VDE_0  
+#define MC_TIMEOUT_VDE_0                        _MK_ADDR_CONST(0x1ec)
+#define MC_TIMEOUT_VDE_0_SECURE                         0x0
+#define MC_TIMEOUT_VDE_0_WORD_COUNT                     0x1
+#define MC_TIMEOUT_VDE_0_RESET_VAL                      _MK_MASK_CONST(0x4444444)
+#define MC_TIMEOUT_VDE_0_RESET_MASK                     _MK_MASK_CONST(0xfffffff)
+#define MC_TIMEOUT_VDE_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_VDE_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_VDE_0_READ_MASK                      _MK_MASK_CONST(0xfffffff)
+#define MC_TIMEOUT_VDE_0_WRITE_MASK                     _MK_MASK_CONST(0xfffffff)
+#define MC_TIMEOUT_VDE_0_VDEBSEVR_TMVAL_SHIFT                   _MK_SHIFT_CONST(0)
+#define MC_TIMEOUT_VDE_0_VDEBSEVR_TMVAL_FIELD                   (_MK_MASK_CONST(0xf) << MC_TIMEOUT_VDE_0_VDEBSEVR_TMVAL_SHIFT)
+#define MC_TIMEOUT_VDE_0_VDEBSEVR_TMVAL_RANGE                   3:0
+#define MC_TIMEOUT_VDE_0_VDEBSEVR_TMVAL_WOFFSET                 0x0
+#define MC_TIMEOUT_VDE_0_VDEBSEVR_TMVAL_DEFAULT                 _MK_MASK_CONST(0x4)
+#define MC_TIMEOUT_VDE_0_VDEBSEVR_TMVAL_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_VDE_0_VDEBSEVR_TMVAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_VDE_0_VDEBSEVR_TMVAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_VDE_0_VDEMBER_TMVAL_SHIFT                    _MK_SHIFT_CONST(4)
+#define MC_TIMEOUT_VDE_0_VDEMBER_TMVAL_FIELD                    (_MK_MASK_CONST(0xf) << MC_TIMEOUT_VDE_0_VDEMBER_TMVAL_SHIFT)
+#define MC_TIMEOUT_VDE_0_VDEMBER_TMVAL_RANGE                    7:4
+#define MC_TIMEOUT_VDE_0_VDEMBER_TMVAL_WOFFSET                  0x0
+#define MC_TIMEOUT_VDE_0_VDEMBER_TMVAL_DEFAULT                  _MK_MASK_CONST(0x4)
+#define MC_TIMEOUT_VDE_0_VDEMBER_TMVAL_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_VDE_0_VDEMBER_TMVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_VDE_0_VDEMBER_TMVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_VDE_0_VDEMCER_TMVAL_SHIFT                    _MK_SHIFT_CONST(8)
+#define MC_TIMEOUT_VDE_0_VDEMCER_TMVAL_FIELD                    (_MK_MASK_CONST(0xf) << MC_TIMEOUT_VDE_0_VDEMCER_TMVAL_SHIFT)
+#define MC_TIMEOUT_VDE_0_VDEMCER_TMVAL_RANGE                    11:8
+#define MC_TIMEOUT_VDE_0_VDEMCER_TMVAL_WOFFSET                  0x0
+#define MC_TIMEOUT_VDE_0_VDEMCER_TMVAL_DEFAULT                  _MK_MASK_CONST(0x4)
+#define MC_TIMEOUT_VDE_0_VDEMCER_TMVAL_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_VDE_0_VDEMCER_TMVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_VDE_0_VDEMCER_TMVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_VDE_0_VDETPER_TMVAL_SHIFT                    _MK_SHIFT_CONST(12)
+#define MC_TIMEOUT_VDE_0_VDETPER_TMVAL_FIELD                    (_MK_MASK_CONST(0xf) << MC_TIMEOUT_VDE_0_VDETPER_TMVAL_SHIFT)
+#define MC_TIMEOUT_VDE_0_VDETPER_TMVAL_RANGE                    15:12
+#define MC_TIMEOUT_VDE_0_VDETPER_TMVAL_WOFFSET                  0x0
+#define MC_TIMEOUT_VDE_0_VDETPER_TMVAL_DEFAULT                  _MK_MASK_CONST(0x4)
+#define MC_TIMEOUT_VDE_0_VDETPER_TMVAL_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_VDE_0_VDETPER_TMVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_VDE_0_VDETPER_TMVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_VDE_0_VDEBSEVW_TMVAL_SHIFT                   _MK_SHIFT_CONST(16)
+#define MC_TIMEOUT_VDE_0_VDEBSEVW_TMVAL_FIELD                   (_MK_MASK_CONST(0xf) << MC_TIMEOUT_VDE_0_VDEBSEVW_TMVAL_SHIFT)
+#define MC_TIMEOUT_VDE_0_VDEBSEVW_TMVAL_RANGE                   19:16
+#define MC_TIMEOUT_VDE_0_VDEBSEVW_TMVAL_WOFFSET                 0x0
+#define MC_TIMEOUT_VDE_0_VDEBSEVW_TMVAL_DEFAULT                 _MK_MASK_CONST(0x4)
+#define MC_TIMEOUT_VDE_0_VDEBSEVW_TMVAL_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_VDE_0_VDEBSEVW_TMVAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_VDE_0_VDEBSEVW_TMVAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_VDE_0_VDEMBEW_TMVAL_SHIFT                    _MK_SHIFT_CONST(20)
+#define MC_TIMEOUT_VDE_0_VDEMBEW_TMVAL_FIELD                    (_MK_MASK_CONST(0xf) << MC_TIMEOUT_VDE_0_VDEMBEW_TMVAL_SHIFT)
+#define MC_TIMEOUT_VDE_0_VDEMBEW_TMVAL_RANGE                    23:20
+#define MC_TIMEOUT_VDE_0_VDEMBEW_TMVAL_WOFFSET                  0x0
+#define MC_TIMEOUT_VDE_0_VDEMBEW_TMVAL_DEFAULT                  _MK_MASK_CONST(0x4)
+#define MC_TIMEOUT_VDE_0_VDEMBEW_TMVAL_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_VDE_0_VDEMBEW_TMVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_VDE_0_VDEMBEW_TMVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_VDE_0_VDETPMW_TMVAL_SHIFT                    _MK_SHIFT_CONST(24)
+#define MC_TIMEOUT_VDE_0_VDETPMW_TMVAL_FIELD                    (_MK_MASK_CONST(0xf) << MC_TIMEOUT_VDE_0_VDETPMW_TMVAL_SHIFT)
+#define MC_TIMEOUT_VDE_0_VDETPMW_TMVAL_RANGE                    27:24
+#define MC_TIMEOUT_VDE_0_VDETPMW_TMVAL_WOFFSET                  0x0
+#define MC_TIMEOUT_VDE_0_VDETPMW_TMVAL_DEFAULT                  _MK_MASK_CONST(0x4)
+#define MC_TIMEOUT_VDE_0_VDETPMW_TMVAL_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_VDE_0_VDETPMW_TMVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_VDE_0_VDETPMW_TMVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register MC_TIMEOUT_VI_0  
+#define MC_TIMEOUT_VI_0                 _MK_ADDR_CONST(0x1f0)
+#define MC_TIMEOUT_VI_0_SECURE                  0x0
+#define MC_TIMEOUT_VI_0_WORD_COUNT                      0x1
+#define MC_TIMEOUT_VI_0_RESET_VAL                       _MK_MASK_CONST(0x88888)
+#define MC_TIMEOUT_VI_0_RESET_MASK                      _MK_MASK_CONST(0xfffff)
+#define MC_TIMEOUT_VI_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_VI_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_VI_0_READ_MASK                       _MK_MASK_CONST(0xfffff)
+#define MC_TIMEOUT_VI_0_WRITE_MASK                      _MK_MASK_CONST(0xfffff)
+#define MC_TIMEOUT_VI_0_VIRUV_TMVAL_SHIFT                       _MK_SHIFT_CONST(0)
+#define MC_TIMEOUT_VI_0_VIRUV_TMVAL_FIELD                       (_MK_MASK_CONST(0xf) << MC_TIMEOUT_VI_0_VIRUV_TMVAL_SHIFT)
+#define MC_TIMEOUT_VI_0_VIRUV_TMVAL_RANGE                       3:0
+#define MC_TIMEOUT_VI_0_VIRUV_TMVAL_WOFFSET                     0x0
+#define MC_TIMEOUT_VI_0_VIRUV_TMVAL_DEFAULT                     _MK_MASK_CONST(0x8)
+#define MC_TIMEOUT_VI_0_VIRUV_TMVAL_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_VI_0_VIRUV_TMVAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_VI_0_VIRUV_TMVAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_VI_0_VIWSB_TMVAL_SHIFT                       _MK_SHIFT_CONST(4)
+#define MC_TIMEOUT_VI_0_VIWSB_TMVAL_FIELD                       (_MK_MASK_CONST(0xf) << MC_TIMEOUT_VI_0_VIWSB_TMVAL_SHIFT)
+#define MC_TIMEOUT_VI_0_VIWSB_TMVAL_RANGE                       7:4
+#define MC_TIMEOUT_VI_0_VIWSB_TMVAL_WOFFSET                     0x0
+#define MC_TIMEOUT_VI_0_VIWSB_TMVAL_DEFAULT                     _MK_MASK_CONST(0x8)
+#define MC_TIMEOUT_VI_0_VIWSB_TMVAL_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_VI_0_VIWSB_TMVAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_VI_0_VIWSB_TMVAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_VI_0_VIWU_TMVAL_SHIFT                        _MK_SHIFT_CONST(8)
+#define MC_TIMEOUT_VI_0_VIWU_TMVAL_FIELD                        (_MK_MASK_CONST(0xf) << MC_TIMEOUT_VI_0_VIWU_TMVAL_SHIFT)
+#define MC_TIMEOUT_VI_0_VIWU_TMVAL_RANGE                        11:8
+#define MC_TIMEOUT_VI_0_VIWU_TMVAL_WOFFSET                      0x0
+#define MC_TIMEOUT_VI_0_VIWU_TMVAL_DEFAULT                      _MK_MASK_CONST(0x8)
+#define MC_TIMEOUT_VI_0_VIWU_TMVAL_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_VI_0_VIWU_TMVAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_VI_0_VIWU_TMVAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_VI_0_VIWV_TMVAL_SHIFT                        _MK_SHIFT_CONST(12)
+#define MC_TIMEOUT_VI_0_VIWV_TMVAL_FIELD                        (_MK_MASK_CONST(0xf) << MC_TIMEOUT_VI_0_VIWV_TMVAL_SHIFT)
+#define MC_TIMEOUT_VI_0_VIWV_TMVAL_RANGE                        15:12
+#define MC_TIMEOUT_VI_0_VIWV_TMVAL_WOFFSET                      0x0
+#define MC_TIMEOUT_VI_0_VIWV_TMVAL_DEFAULT                      _MK_MASK_CONST(0x8)
+#define MC_TIMEOUT_VI_0_VIWV_TMVAL_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_VI_0_VIWV_TMVAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_VI_0_VIWV_TMVAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_VI_0_VIWY_TMVAL_SHIFT                        _MK_SHIFT_CONST(16)
+#define MC_TIMEOUT_VI_0_VIWY_TMVAL_FIELD                        (_MK_MASK_CONST(0xf) << MC_TIMEOUT_VI_0_VIWY_TMVAL_SHIFT)
+#define MC_TIMEOUT_VI_0_VIWY_TMVAL_RANGE                        19:16
+#define MC_TIMEOUT_VI_0_VIWY_TMVAL_WOFFSET                      0x0
+#define MC_TIMEOUT_VI_0_VIWY_TMVAL_DEFAULT                      _MK_MASK_CONST(0x8)
+#define MC_TIMEOUT_VI_0_VIWY_TMVAL_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_VI_0_VIWY_TMVAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_VI_0_VIWY_TMVAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register MC_TIMEOUT_RCOAL_AVPC_0  
+#define MC_TIMEOUT_RCOAL_AVPC_0                 _MK_ADDR_CONST(0x1f4)
+#define MC_TIMEOUT_RCOAL_AVPC_0_SECURE                  0x0
+#define MC_TIMEOUT_RCOAL_AVPC_0_WORD_COUNT                      0x1
+#define MC_TIMEOUT_RCOAL_AVPC_0_RESET_VAL                       _MK_MASK_CONST(0x4)
+#define MC_TIMEOUT_RCOAL_AVPC_0_RESET_MASK                      _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_RCOAL_AVPC_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_AVPC_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_AVPC_0_READ_MASK                       _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_RCOAL_AVPC_0_WRITE_MASK                      _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_RCOAL_AVPC_0_AVPCARM7R_RCOAL_TMVAL_SHIFT                     _MK_SHIFT_CONST(0)
+#define MC_TIMEOUT_RCOAL_AVPC_0_AVPCARM7R_RCOAL_TMVAL_FIELD                     (_MK_MASK_CONST(0xff) << MC_TIMEOUT_RCOAL_AVPC_0_AVPCARM7R_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_AVPC_0_AVPCARM7R_RCOAL_TMVAL_RANGE                     7:0
+#define MC_TIMEOUT_RCOAL_AVPC_0_AVPCARM7R_RCOAL_TMVAL_WOFFSET                   0x0
+#define MC_TIMEOUT_RCOAL_AVPC_0_AVPCARM7R_RCOAL_TMVAL_DEFAULT                   _MK_MASK_CONST(0x4)
+#define MC_TIMEOUT_RCOAL_AVPC_0_AVPCARM7R_RCOAL_TMVAL_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_RCOAL_AVPC_0_AVPCARM7R_RCOAL_TMVAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_AVPC_0_AVPCARM7R_RCOAL_TMVAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register MC_TIMEOUT_RCOAL_DC_0  
+#define MC_TIMEOUT_RCOAL_DC_0                   _MK_ADDR_CONST(0x1f8)
+#define MC_TIMEOUT_RCOAL_DC_0_SECURE                    0x0
+#define MC_TIMEOUT_RCOAL_DC_0_WORD_COUNT                        0x1
+#define MC_TIMEOUT_RCOAL_DC_0_RESET_VAL                         _MK_MASK_CONST(0x4040404)
+#define MC_TIMEOUT_RCOAL_DC_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
+#define MC_TIMEOUT_RCOAL_DC_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_DC_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_DC_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define MC_TIMEOUT_RCOAL_DC_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY0A_RCOAL_TMVAL_SHIFT                       _MK_SHIFT_CONST(0)
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY0A_RCOAL_TMVAL_FIELD                       (_MK_MASK_CONST(0xff) << MC_TIMEOUT_RCOAL_DC_0_DISPLAY0A_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY0A_RCOAL_TMVAL_RANGE                       7:0
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY0A_RCOAL_TMVAL_WOFFSET                     0x0
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY0A_RCOAL_TMVAL_DEFAULT                     _MK_MASK_CONST(0x4)
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY0A_RCOAL_TMVAL_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY0A_RCOAL_TMVAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY0A_RCOAL_TMVAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY0B_RCOAL_TMVAL_SHIFT                       _MK_SHIFT_CONST(8)
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY0B_RCOAL_TMVAL_FIELD                       (_MK_MASK_CONST(0xff) << MC_TIMEOUT_RCOAL_DC_0_DISPLAY0B_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY0B_RCOAL_TMVAL_RANGE                       15:8
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY0B_RCOAL_TMVAL_WOFFSET                     0x0
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY0B_RCOAL_TMVAL_DEFAULT                     _MK_MASK_CONST(0x4)
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY0B_RCOAL_TMVAL_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY0B_RCOAL_TMVAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY0B_RCOAL_TMVAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY0C_RCOAL_TMVAL_SHIFT                       _MK_SHIFT_CONST(16)
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY0C_RCOAL_TMVAL_FIELD                       (_MK_MASK_CONST(0xff) << MC_TIMEOUT_RCOAL_DC_0_DISPLAY0C_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY0C_RCOAL_TMVAL_RANGE                       23:16
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY0C_RCOAL_TMVAL_WOFFSET                     0x0
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY0C_RCOAL_TMVAL_DEFAULT                     _MK_MASK_CONST(0x4)
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY0C_RCOAL_TMVAL_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY0C_RCOAL_TMVAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY0C_RCOAL_TMVAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY1B_RCOAL_TMVAL_SHIFT                       _MK_SHIFT_CONST(24)
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY1B_RCOAL_TMVAL_FIELD                       (_MK_MASK_CONST(0xff) << MC_TIMEOUT_RCOAL_DC_0_DISPLAY1B_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY1B_RCOAL_TMVAL_RANGE                       31:24
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY1B_RCOAL_TMVAL_WOFFSET                     0x0
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY1B_RCOAL_TMVAL_DEFAULT                     _MK_MASK_CONST(0x4)
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY1B_RCOAL_TMVAL_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY1B_RCOAL_TMVAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY1B_RCOAL_TMVAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register MC_TIMEOUT1_RCOAL_DC_0  
+#define MC_TIMEOUT1_RCOAL_DC_0                  _MK_ADDR_CONST(0x1fc)
+#define MC_TIMEOUT1_RCOAL_DC_0_SECURE                   0x0
+#define MC_TIMEOUT1_RCOAL_DC_0_WORD_COUNT                       0x1
+#define MC_TIMEOUT1_RCOAL_DC_0_RESET_VAL                        _MK_MASK_CONST(0x4)
+#define MC_TIMEOUT1_RCOAL_DC_0_RESET_MASK                       _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT1_RCOAL_DC_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT1_RCOAL_DC_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT1_RCOAL_DC_0_READ_MASK                        _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT1_RCOAL_DC_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT1_RCOAL_DC_0_DISPLAYHC_RCOAL_TMVAL_SHIFT                      _MK_SHIFT_CONST(0)
+#define MC_TIMEOUT1_RCOAL_DC_0_DISPLAYHC_RCOAL_TMVAL_FIELD                      (_MK_MASK_CONST(0xff) << MC_TIMEOUT1_RCOAL_DC_0_DISPLAYHC_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT1_RCOAL_DC_0_DISPLAYHC_RCOAL_TMVAL_RANGE                      7:0
+#define MC_TIMEOUT1_RCOAL_DC_0_DISPLAYHC_RCOAL_TMVAL_WOFFSET                    0x0
+#define MC_TIMEOUT1_RCOAL_DC_0_DISPLAYHC_RCOAL_TMVAL_DEFAULT                    _MK_MASK_CONST(0x4)
+#define MC_TIMEOUT1_RCOAL_DC_0_DISPLAYHC_RCOAL_TMVAL_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT1_RCOAL_DC_0_DISPLAYHC_RCOAL_TMVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT1_RCOAL_DC_0_DISPLAYHC_RCOAL_TMVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register MC_TIMEOUT_RCOAL_DCB_0  
+#define MC_TIMEOUT_RCOAL_DCB_0                  _MK_ADDR_CONST(0x200)
+#define MC_TIMEOUT_RCOAL_DCB_0_SECURE                   0x0
+#define MC_TIMEOUT_RCOAL_DCB_0_WORD_COUNT                       0x1
+#define MC_TIMEOUT_RCOAL_DCB_0_RESET_VAL                        _MK_MASK_CONST(0x4040404)
+#define MC_TIMEOUT_RCOAL_DCB_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
+#define MC_TIMEOUT_RCOAL_DCB_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_DCB_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_DCB_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define MC_TIMEOUT_RCOAL_DCB_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY0AB_RCOAL_TMVAL_SHIFT                     _MK_SHIFT_CONST(0)
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY0AB_RCOAL_TMVAL_FIELD                     (_MK_MASK_CONST(0xff) << MC_TIMEOUT_RCOAL_DCB_0_DISPLAY0AB_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY0AB_RCOAL_TMVAL_RANGE                     7:0
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY0AB_RCOAL_TMVAL_WOFFSET                   0x0
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY0AB_RCOAL_TMVAL_DEFAULT                   _MK_MASK_CONST(0x4)
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY0AB_RCOAL_TMVAL_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY0AB_RCOAL_TMVAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY0AB_RCOAL_TMVAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY0BB_RCOAL_TMVAL_SHIFT                     _MK_SHIFT_CONST(8)
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY0BB_RCOAL_TMVAL_FIELD                     (_MK_MASK_CONST(0xff) << MC_TIMEOUT_RCOAL_DCB_0_DISPLAY0BB_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY0BB_RCOAL_TMVAL_RANGE                     15:8
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY0BB_RCOAL_TMVAL_WOFFSET                   0x0
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY0BB_RCOAL_TMVAL_DEFAULT                   _MK_MASK_CONST(0x4)
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY0BB_RCOAL_TMVAL_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY0BB_RCOAL_TMVAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY0BB_RCOAL_TMVAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY0CB_RCOAL_TMVAL_SHIFT                     _MK_SHIFT_CONST(16)
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY0CB_RCOAL_TMVAL_FIELD                     (_MK_MASK_CONST(0xff) << MC_TIMEOUT_RCOAL_DCB_0_DISPLAY0CB_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY0CB_RCOAL_TMVAL_RANGE                     23:16
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY0CB_RCOAL_TMVAL_WOFFSET                   0x0
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY0CB_RCOAL_TMVAL_DEFAULT                   _MK_MASK_CONST(0x4)
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY0CB_RCOAL_TMVAL_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY0CB_RCOAL_TMVAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY0CB_RCOAL_TMVAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY1BB_RCOAL_TMVAL_SHIFT                     _MK_SHIFT_CONST(24)
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY1BB_RCOAL_TMVAL_FIELD                     (_MK_MASK_CONST(0xff) << MC_TIMEOUT_RCOAL_DCB_0_DISPLAY1BB_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY1BB_RCOAL_TMVAL_RANGE                     31:24
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY1BB_RCOAL_TMVAL_WOFFSET                   0x0
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY1BB_RCOAL_TMVAL_DEFAULT                   _MK_MASK_CONST(0x4)
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY1BB_RCOAL_TMVAL_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY1BB_RCOAL_TMVAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY1BB_RCOAL_TMVAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register MC_TIMEOUT1_RCOAL_DCB_0  
+#define MC_TIMEOUT1_RCOAL_DCB_0                 _MK_ADDR_CONST(0x204)
+#define MC_TIMEOUT1_RCOAL_DCB_0_SECURE                  0x0
+#define MC_TIMEOUT1_RCOAL_DCB_0_WORD_COUNT                      0x1
+#define MC_TIMEOUT1_RCOAL_DCB_0_RESET_VAL                       _MK_MASK_CONST(0x4)
+#define MC_TIMEOUT1_RCOAL_DCB_0_RESET_MASK                      _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT1_RCOAL_DCB_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT1_RCOAL_DCB_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT1_RCOAL_DCB_0_READ_MASK                       _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT1_RCOAL_DCB_0_WRITE_MASK                      _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT1_RCOAL_DCB_0_DISPLAYHCB_RCOAL_TMVAL_SHIFT                    _MK_SHIFT_CONST(0)
+#define MC_TIMEOUT1_RCOAL_DCB_0_DISPLAYHCB_RCOAL_TMVAL_FIELD                    (_MK_MASK_CONST(0xff) << MC_TIMEOUT1_RCOAL_DCB_0_DISPLAYHCB_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT1_RCOAL_DCB_0_DISPLAYHCB_RCOAL_TMVAL_RANGE                    7:0
+#define MC_TIMEOUT1_RCOAL_DCB_0_DISPLAYHCB_RCOAL_TMVAL_WOFFSET                  0x0
+#define MC_TIMEOUT1_RCOAL_DCB_0_DISPLAYHCB_RCOAL_TMVAL_DEFAULT                  _MK_MASK_CONST(0x4)
+#define MC_TIMEOUT1_RCOAL_DCB_0_DISPLAYHCB_RCOAL_TMVAL_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT1_RCOAL_DCB_0_DISPLAYHCB_RCOAL_TMVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT1_RCOAL_DCB_0_DISPLAYHCB_RCOAL_TMVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register MC_TIMEOUT_RCOAL_EPP_0  
+#define MC_TIMEOUT_RCOAL_EPP_0                  _MK_ADDR_CONST(0x208)
+#define MC_TIMEOUT_RCOAL_EPP_0_SECURE                   0x0
+#define MC_TIMEOUT_RCOAL_EPP_0_WORD_COUNT                       0x1
+#define MC_TIMEOUT_RCOAL_EPP_0_RESET_VAL                        _MK_MASK_CONST(0x4)
+#define MC_TIMEOUT_RCOAL_EPP_0_RESET_MASK                       _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_RCOAL_EPP_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_EPP_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_EPP_0_READ_MASK                        _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_RCOAL_EPP_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_RCOAL_EPP_0_EPPUP_RCOAL_TMVAL_SHIFT                  _MK_SHIFT_CONST(0)
+#define MC_TIMEOUT_RCOAL_EPP_0_EPPUP_RCOAL_TMVAL_FIELD                  (_MK_MASK_CONST(0xff) << MC_TIMEOUT_RCOAL_EPP_0_EPPUP_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_EPP_0_EPPUP_RCOAL_TMVAL_RANGE                  7:0
+#define MC_TIMEOUT_RCOAL_EPP_0_EPPUP_RCOAL_TMVAL_WOFFSET                        0x0
+#define MC_TIMEOUT_RCOAL_EPP_0_EPPUP_RCOAL_TMVAL_DEFAULT                        _MK_MASK_CONST(0x4)
+#define MC_TIMEOUT_RCOAL_EPP_0_EPPUP_RCOAL_TMVAL_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_RCOAL_EPP_0_EPPUP_RCOAL_TMVAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_EPP_0_EPPUP_RCOAL_TMVAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register MC_TIMEOUT_RCOAL_G2_0  
+#define MC_TIMEOUT_RCOAL_G2_0                   _MK_ADDR_CONST(0x20c)
+#define MC_TIMEOUT_RCOAL_G2_0_SECURE                    0x0
+#define MC_TIMEOUT_RCOAL_G2_0_WORD_COUNT                        0x1
+#define MC_TIMEOUT_RCOAL_G2_0_RESET_VAL                         _MK_MASK_CONST(0x40404)
+#define MC_TIMEOUT_RCOAL_G2_0_RESET_MASK                        _MK_MASK_CONST(0xffffff)
+#define MC_TIMEOUT_RCOAL_G2_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_G2_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_G2_0_READ_MASK                         _MK_MASK_CONST(0xffffff)
+#define MC_TIMEOUT_RCOAL_G2_0_WRITE_MASK                        _MK_MASK_CONST(0xffffff)
+#define MC_TIMEOUT_RCOAL_G2_0_G2PR_RCOAL_TMVAL_SHIFT                    _MK_SHIFT_CONST(0)
+#define MC_TIMEOUT_RCOAL_G2_0_G2PR_RCOAL_TMVAL_FIELD                    (_MK_MASK_CONST(0xff) << MC_TIMEOUT_RCOAL_G2_0_G2PR_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_G2_0_G2PR_RCOAL_TMVAL_RANGE                    7:0
+#define MC_TIMEOUT_RCOAL_G2_0_G2PR_RCOAL_TMVAL_WOFFSET                  0x0
+#define MC_TIMEOUT_RCOAL_G2_0_G2PR_RCOAL_TMVAL_DEFAULT                  _MK_MASK_CONST(0x4)
+#define MC_TIMEOUT_RCOAL_G2_0_G2PR_RCOAL_TMVAL_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_RCOAL_G2_0_G2PR_RCOAL_TMVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_G2_0_G2PR_RCOAL_TMVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_RCOAL_G2_0_G2SR_RCOAL_TMVAL_SHIFT                    _MK_SHIFT_CONST(8)
+#define MC_TIMEOUT_RCOAL_G2_0_G2SR_RCOAL_TMVAL_FIELD                    (_MK_MASK_CONST(0xff) << MC_TIMEOUT_RCOAL_G2_0_G2SR_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_G2_0_G2SR_RCOAL_TMVAL_RANGE                    15:8
+#define MC_TIMEOUT_RCOAL_G2_0_G2SR_RCOAL_TMVAL_WOFFSET                  0x0
+#define MC_TIMEOUT_RCOAL_G2_0_G2SR_RCOAL_TMVAL_DEFAULT                  _MK_MASK_CONST(0x4)
+#define MC_TIMEOUT_RCOAL_G2_0_G2SR_RCOAL_TMVAL_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_RCOAL_G2_0_G2SR_RCOAL_TMVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_G2_0_G2SR_RCOAL_TMVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_RCOAL_G2_0_G2DR_RCOAL_TMVAL_SHIFT                    _MK_SHIFT_CONST(16)
+#define MC_TIMEOUT_RCOAL_G2_0_G2DR_RCOAL_TMVAL_FIELD                    (_MK_MASK_CONST(0xff) << MC_TIMEOUT_RCOAL_G2_0_G2DR_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_G2_0_G2DR_RCOAL_TMVAL_RANGE                    23:16
+#define MC_TIMEOUT_RCOAL_G2_0_G2DR_RCOAL_TMVAL_WOFFSET                  0x0
+#define MC_TIMEOUT_RCOAL_G2_0_G2DR_RCOAL_TMVAL_DEFAULT                  _MK_MASK_CONST(0x4)
+#define MC_TIMEOUT_RCOAL_G2_0_G2DR_RCOAL_TMVAL_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_RCOAL_G2_0_G2DR_RCOAL_TMVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_G2_0_G2DR_RCOAL_TMVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register MC_TIMEOUT_RCOAL_HC_0  
+#define MC_TIMEOUT_RCOAL_HC_0                   _MK_ADDR_CONST(0x210)
+#define MC_TIMEOUT_RCOAL_HC_0_SECURE                    0x0
+#define MC_TIMEOUT_RCOAL_HC_0_WORD_COUNT                        0x1
+#define MC_TIMEOUT_RCOAL_HC_0_RESET_VAL                         _MK_MASK_CONST(0x404)
+#define MC_TIMEOUT_RCOAL_HC_0_RESET_MASK                        _MK_MASK_CONST(0xffff)
+#define MC_TIMEOUT_RCOAL_HC_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_HC_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_HC_0_READ_MASK                         _MK_MASK_CONST(0xffff)
+#define MC_TIMEOUT_RCOAL_HC_0_WRITE_MASK                        _MK_MASK_CONST(0xffff)
+#define MC_TIMEOUT_RCOAL_HC_0_HOST1XDMAR_RCOAL_TMVAL_SHIFT                      _MK_SHIFT_CONST(0)
+#define MC_TIMEOUT_RCOAL_HC_0_HOST1XDMAR_RCOAL_TMVAL_FIELD                      (_MK_MASK_CONST(0xff) << MC_TIMEOUT_RCOAL_HC_0_HOST1XDMAR_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_HC_0_HOST1XDMAR_RCOAL_TMVAL_RANGE                      7:0
+#define MC_TIMEOUT_RCOAL_HC_0_HOST1XDMAR_RCOAL_TMVAL_WOFFSET                    0x0
+#define MC_TIMEOUT_RCOAL_HC_0_HOST1XDMAR_RCOAL_TMVAL_DEFAULT                    _MK_MASK_CONST(0x4)
+#define MC_TIMEOUT_RCOAL_HC_0_HOST1XDMAR_RCOAL_TMVAL_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_RCOAL_HC_0_HOST1XDMAR_RCOAL_TMVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_HC_0_HOST1XDMAR_RCOAL_TMVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_RCOAL_HC_0_HOST1XR_RCOAL_TMVAL_SHIFT                 _MK_SHIFT_CONST(8)
+#define MC_TIMEOUT_RCOAL_HC_0_HOST1XR_RCOAL_TMVAL_FIELD                 (_MK_MASK_CONST(0xff) << MC_TIMEOUT_RCOAL_HC_0_HOST1XR_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_HC_0_HOST1XR_RCOAL_TMVAL_RANGE                 15:8
+#define MC_TIMEOUT_RCOAL_HC_0_HOST1XR_RCOAL_TMVAL_WOFFSET                       0x0
+#define MC_TIMEOUT_RCOAL_HC_0_HOST1XR_RCOAL_TMVAL_DEFAULT                       _MK_MASK_CONST(0x4)
+#define MC_TIMEOUT_RCOAL_HC_0_HOST1XR_RCOAL_TMVAL_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_RCOAL_HC_0_HOST1XR_RCOAL_TMVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_HC_0_HOST1XR_RCOAL_TMVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register MC_TIMEOUT_RCOAL_MPCORE_0  
+#define MC_TIMEOUT_RCOAL_MPCORE_0                       _MK_ADDR_CONST(0x214)
+#define MC_TIMEOUT_RCOAL_MPCORE_0_SECURE                        0x0
+#define MC_TIMEOUT_RCOAL_MPCORE_0_WORD_COUNT                    0x1
+#define MC_TIMEOUT_RCOAL_MPCORE_0_RESET_VAL                     _MK_MASK_CONST(0x4)
+#define MC_TIMEOUT_RCOAL_MPCORE_0_RESET_MASK                    _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_RCOAL_MPCORE_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_MPCORE_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_MPCORE_0_READ_MASK                     _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_RCOAL_MPCORE_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_RCOAL_MPCORE_0_MPCORER_RCOAL_TMVAL_SHIFT                     _MK_SHIFT_CONST(0)
+#define MC_TIMEOUT_RCOAL_MPCORE_0_MPCORER_RCOAL_TMVAL_FIELD                     (_MK_MASK_CONST(0xff) << MC_TIMEOUT_RCOAL_MPCORE_0_MPCORER_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_MPCORE_0_MPCORER_RCOAL_TMVAL_RANGE                     7:0
+#define MC_TIMEOUT_RCOAL_MPCORE_0_MPCORER_RCOAL_TMVAL_WOFFSET                   0x0
+#define MC_TIMEOUT_RCOAL_MPCORE_0_MPCORER_RCOAL_TMVAL_DEFAULT                   _MK_MASK_CONST(0x4)
+#define MC_TIMEOUT_RCOAL_MPCORE_0_MPCORER_RCOAL_TMVAL_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_RCOAL_MPCORE_0_MPCORER_RCOAL_TMVAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_MPCORE_0_MPCORER_RCOAL_TMVAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register MC_TIMEOUT_RCOAL_MPEA_0  
+#define MC_TIMEOUT_RCOAL_MPEA_0                 _MK_ADDR_CONST(0x218)
+#define MC_TIMEOUT_RCOAL_MPEA_0_SECURE                  0x0
+#define MC_TIMEOUT_RCOAL_MPEA_0_WORD_COUNT                      0x1
+#define MC_TIMEOUT_RCOAL_MPEA_0_RESET_VAL                       _MK_MASK_CONST(0x4)
+#define MC_TIMEOUT_RCOAL_MPEA_0_RESET_MASK                      _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_RCOAL_MPEA_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_MPEA_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_MPEA_0_READ_MASK                       _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_RCOAL_MPEA_0_WRITE_MASK                      _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_RCOAL_MPEA_0_MPEAMEMRD_RCOAL_TMVAL_SHIFT                     _MK_SHIFT_CONST(0)
+#define MC_TIMEOUT_RCOAL_MPEA_0_MPEAMEMRD_RCOAL_TMVAL_FIELD                     (_MK_MASK_CONST(0xff) << MC_TIMEOUT_RCOAL_MPEA_0_MPEAMEMRD_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_MPEA_0_MPEAMEMRD_RCOAL_TMVAL_RANGE                     7:0
+#define MC_TIMEOUT_RCOAL_MPEA_0_MPEAMEMRD_RCOAL_TMVAL_WOFFSET                   0x0
+#define MC_TIMEOUT_RCOAL_MPEA_0_MPEAMEMRD_RCOAL_TMVAL_DEFAULT                   _MK_MASK_CONST(0x4)
+#define MC_TIMEOUT_RCOAL_MPEA_0_MPEAMEMRD_RCOAL_TMVAL_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_RCOAL_MPEA_0_MPEAMEMRD_RCOAL_TMVAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_MPEA_0_MPEAMEMRD_RCOAL_TMVAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register MC_TIMEOUT_RCOAL_MPEB_0  
+#define MC_TIMEOUT_RCOAL_MPEB_0                 _MK_ADDR_CONST(0x21c)
+#define MC_TIMEOUT_RCOAL_MPEB_0_SECURE                  0x0
+#define MC_TIMEOUT_RCOAL_MPEB_0_WORD_COUNT                      0x1
+#define MC_TIMEOUT_RCOAL_MPEB_0_RESET_VAL                       _MK_MASK_CONST(0x404)
+#define MC_TIMEOUT_RCOAL_MPEB_0_RESET_MASK                      _MK_MASK_CONST(0xffff)
+#define MC_TIMEOUT_RCOAL_MPEB_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_MPEB_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_MPEB_0_READ_MASK                       _MK_MASK_CONST(0xffff)
+#define MC_TIMEOUT_RCOAL_MPEB_0_WRITE_MASK                      _MK_MASK_CONST(0xffff)
+#define MC_TIMEOUT_RCOAL_MPEB_0_MPEUNIFBR_RCOAL_TMVAL_SHIFT                     _MK_SHIFT_CONST(0)
+#define MC_TIMEOUT_RCOAL_MPEB_0_MPEUNIFBR_RCOAL_TMVAL_FIELD                     (_MK_MASK_CONST(0xff) << MC_TIMEOUT_RCOAL_MPEB_0_MPEUNIFBR_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_MPEB_0_MPEUNIFBR_RCOAL_TMVAL_RANGE                     7:0
+#define MC_TIMEOUT_RCOAL_MPEB_0_MPEUNIFBR_RCOAL_TMVAL_WOFFSET                   0x0
+#define MC_TIMEOUT_RCOAL_MPEB_0_MPEUNIFBR_RCOAL_TMVAL_DEFAULT                   _MK_MASK_CONST(0x4)
+#define MC_TIMEOUT_RCOAL_MPEB_0_MPEUNIFBR_RCOAL_TMVAL_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_RCOAL_MPEB_0_MPEUNIFBR_RCOAL_TMVAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_MPEB_0_MPEUNIFBR_RCOAL_TMVAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_RCOAL_MPEB_0_MPE_IPRED_RCOAL_TMVAL_SHIFT                     _MK_SHIFT_CONST(8)
+#define MC_TIMEOUT_RCOAL_MPEB_0_MPE_IPRED_RCOAL_TMVAL_FIELD                     (_MK_MASK_CONST(0xff) << MC_TIMEOUT_RCOAL_MPEB_0_MPE_IPRED_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_MPEB_0_MPE_IPRED_RCOAL_TMVAL_RANGE                     15:8
+#define MC_TIMEOUT_RCOAL_MPEB_0_MPE_IPRED_RCOAL_TMVAL_WOFFSET                   0x0
+#define MC_TIMEOUT_RCOAL_MPEB_0_MPE_IPRED_RCOAL_TMVAL_DEFAULT                   _MK_MASK_CONST(0x4)
+#define MC_TIMEOUT_RCOAL_MPEB_0_MPE_IPRED_RCOAL_TMVAL_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_RCOAL_MPEB_0_MPE_IPRED_RCOAL_TMVAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_MPEB_0_MPE_IPRED_RCOAL_TMVAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register MC_TIMEOUT_RCOAL_MPEC_0  
+#define MC_TIMEOUT_RCOAL_MPEC_0                 _MK_ADDR_CONST(0x220)
+#define MC_TIMEOUT_RCOAL_MPEC_0_SECURE                  0x0
+#define MC_TIMEOUT_RCOAL_MPEC_0_WORD_COUNT                      0x1
+#define MC_TIMEOUT_RCOAL_MPEC_0_RESET_VAL                       _MK_MASK_CONST(0x4)
+#define MC_TIMEOUT_RCOAL_MPEC_0_RESET_MASK                      _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_RCOAL_MPEC_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_MPEC_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_MPEC_0_READ_MASK                       _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_RCOAL_MPEC_0_WRITE_MASK                      _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_RCOAL_MPEC_0_MPECSRD_RCOAL_TMVAL_SHIFT                       _MK_SHIFT_CONST(0)
+#define MC_TIMEOUT_RCOAL_MPEC_0_MPECSRD_RCOAL_TMVAL_FIELD                       (_MK_MASK_CONST(0xff) << MC_TIMEOUT_RCOAL_MPEC_0_MPECSRD_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_MPEC_0_MPECSRD_RCOAL_TMVAL_RANGE                       7:0
+#define MC_TIMEOUT_RCOAL_MPEC_0_MPECSRD_RCOAL_TMVAL_WOFFSET                     0x0
+#define MC_TIMEOUT_RCOAL_MPEC_0_MPECSRD_RCOAL_TMVAL_DEFAULT                     _MK_MASK_CONST(0x4)
+#define MC_TIMEOUT_RCOAL_MPEC_0_MPECSRD_RCOAL_TMVAL_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_RCOAL_MPEC_0_MPECSRD_RCOAL_TMVAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_MPEC_0_MPECSRD_RCOAL_TMVAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register MC_TIMEOUT_RCOAL_NV_0  
+#define MC_TIMEOUT_RCOAL_NV_0                   _MK_ADDR_CONST(0x224)
+#define MC_TIMEOUT_RCOAL_NV_0_SECURE                    0x0
+#define MC_TIMEOUT_RCOAL_NV_0_WORD_COUNT                        0x1
+#define MC_TIMEOUT_RCOAL_NV_0_RESET_VAL                         _MK_MASK_CONST(0x404)
+#define MC_TIMEOUT_RCOAL_NV_0_RESET_MASK                        _MK_MASK_CONST(0xffff)
+#define MC_TIMEOUT_RCOAL_NV_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_NV_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_NV_0_READ_MASK                         _MK_MASK_CONST(0xffff)
+#define MC_TIMEOUT_RCOAL_NV_0_WRITE_MASK                        _MK_MASK_CONST(0xffff)
+#define MC_TIMEOUT_RCOAL_NV_0_IDXSRD_RCOAL_TMVAL_SHIFT                  _MK_SHIFT_CONST(0)
+#define MC_TIMEOUT_RCOAL_NV_0_IDXSRD_RCOAL_TMVAL_FIELD                  (_MK_MASK_CONST(0xff) << MC_TIMEOUT_RCOAL_NV_0_IDXSRD_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_NV_0_IDXSRD_RCOAL_TMVAL_RANGE                  7:0
+#define MC_TIMEOUT_RCOAL_NV_0_IDXSRD_RCOAL_TMVAL_WOFFSET                        0x0
+#define MC_TIMEOUT_RCOAL_NV_0_IDXSRD_RCOAL_TMVAL_DEFAULT                        _MK_MASK_CONST(0x4)
+#define MC_TIMEOUT_RCOAL_NV_0_IDXSRD_RCOAL_TMVAL_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_RCOAL_NV_0_IDXSRD_RCOAL_TMVAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_NV_0_IDXSRD_RCOAL_TMVAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_RCOAL_NV_0_TEXSRD_RCOAL_TMVAL_SHIFT                  _MK_SHIFT_CONST(8)
+#define MC_TIMEOUT_RCOAL_NV_0_TEXSRD_RCOAL_TMVAL_FIELD                  (_MK_MASK_CONST(0xff) << MC_TIMEOUT_RCOAL_NV_0_TEXSRD_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_NV_0_TEXSRD_RCOAL_TMVAL_RANGE                  15:8
+#define MC_TIMEOUT_RCOAL_NV_0_TEXSRD_RCOAL_TMVAL_WOFFSET                        0x0
+#define MC_TIMEOUT_RCOAL_NV_0_TEXSRD_RCOAL_TMVAL_DEFAULT                        _MK_MASK_CONST(0x4)
+#define MC_TIMEOUT_RCOAL_NV_0_TEXSRD_RCOAL_TMVAL_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_RCOAL_NV_0_TEXSRD_RCOAL_TMVAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_NV_0_TEXSRD_RCOAL_TMVAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register MC_TIMEOUT_RCOAL_PPCS_0  
+#define MC_TIMEOUT_RCOAL_PPCS_0                 _MK_ADDR_CONST(0x228)
+#define MC_TIMEOUT_RCOAL_PPCS_0_SECURE                  0x0
+#define MC_TIMEOUT_RCOAL_PPCS_0_WORD_COUNT                      0x1
+#define MC_TIMEOUT_RCOAL_PPCS_0_RESET_VAL                       _MK_MASK_CONST(0x404)
+#define MC_TIMEOUT_RCOAL_PPCS_0_RESET_MASK                      _MK_MASK_CONST(0xffff)
+#define MC_TIMEOUT_RCOAL_PPCS_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_PPCS_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_PPCS_0_READ_MASK                       _MK_MASK_CONST(0xffff)
+#define MC_TIMEOUT_RCOAL_PPCS_0_WRITE_MASK                      _MK_MASK_CONST(0xffff)
+#define MC_TIMEOUT_RCOAL_PPCS_0_PPCSAHBDMAR_RCOAL_TMVAL_SHIFT                   _MK_SHIFT_CONST(0)
+#define MC_TIMEOUT_RCOAL_PPCS_0_PPCSAHBDMAR_RCOAL_TMVAL_FIELD                   (_MK_MASK_CONST(0xff) << MC_TIMEOUT_RCOAL_PPCS_0_PPCSAHBDMAR_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_PPCS_0_PPCSAHBDMAR_RCOAL_TMVAL_RANGE                   7:0
+#define MC_TIMEOUT_RCOAL_PPCS_0_PPCSAHBDMAR_RCOAL_TMVAL_WOFFSET                 0x0
+#define MC_TIMEOUT_RCOAL_PPCS_0_PPCSAHBDMAR_RCOAL_TMVAL_DEFAULT                 _MK_MASK_CONST(0x4)
+#define MC_TIMEOUT_RCOAL_PPCS_0_PPCSAHBDMAR_RCOAL_TMVAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_RCOAL_PPCS_0_PPCSAHBDMAR_RCOAL_TMVAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_PPCS_0_PPCSAHBDMAR_RCOAL_TMVAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_RCOAL_PPCS_0_PPCSAHBSLVR_RCOAL_TMVAL_SHIFT                   _MK_SHIFT_CONST(8)
+#define MC_TIMEOUT_RCOAL_PPCS_0_PPCSAHBSLVR_RCOAL_TMVAL_FIELD                   (_MK_MASK_CONST(0xff) << MC_TIMEOUT_RCOAL_PPCS_0_PPCSAHBSLVR_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_PPCS_0_PPCSAHBSLVR_RCOAL_TMVAL_RANGE                   15:8
+#define MC_TIMEOUT_RCOAL_PPCS_0_PPCSAHBSLVR_RCOAL_TMVAL_WOFFSET                 0x0
+#define MC_TIMEOUT_RCOAL_PPCS_0_PPCSAHBSLVR_RCOAL_TMVAL_DEFAULT                 _MK_MASK_CONST(0x4)
+#define MC_TIMEOUT_RCOAL_PPCS_0_PPCSAHBSLVR_RCOAL_TMVAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_RCOAL_PPCS_0_PPCSAHBSLVR_RCOAL_TMVAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_PPCS_0_PPCSAHBSLVR_RCOAL_TMVAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register MC_TIMEOUT_RCOAL_VDE_0  
+#define MC_TIMEOUT_RCOAL_VDE_0                  _MK_ADDR_CONST(0x22c)
+#define MC_TIMEOUT_RCOAL_VDE_0_SECURE                   0x0
+#define MC_TIMEOUT_RCOAL_VDE_0_WORD_COUNT                       0x1
+#define MC_TIMEOUT_RCOAL_VDE_0_RESET_VAL                        _MK_MASK_CONST(0x4040404)
+#define MC_TIMEOUT_RCOAL_VDE_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
+#define MC_TIMEOUT_RCOAL_VDE_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_VDE_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_VDE_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define MC_TIMEOUT_RCOAL_VDE_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+#define MC_TIMEOUT_RCOAL_VDE_0_VDEBSEVR_RCOAL_TMVAL_SHIFT                       _MK_SHIFT_CONST(0)
+#define MC_TIMEOUT_RCOAL_VDE_0_VDEBSEVR_RCOAL_TMVAL_FIELD                       (_MK_MASK_CONST(0xff) << MC_TIMEOUT_RCOAL_VDE_0_VDEBSEVR_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_VDE_0_VDEBSEVR_RCOAL_TMVAL_RANGE                       7:0
+#define MC_TIMEOUT_RCOAL_VDE_0_VDEBSEVR_RCOAL_TMVAL_WOFFSET                     0x0
+#define MC_TIMEOUT_RCOAL_VDE_0_VDEBSEVR_RCOAL_TMVAL_DEFAULT                     _MK_MASK_CONST(0x4)
+#define MC_TIMEOUT_RCOAL_VDE_0_VDEBSEVR_RCOAL_TMVAL_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_RCOAL_VDE_0_VDEBSEVR_RCOAL_TMVAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_VDE_0_VDEBSEVR_RCOAL_TMVAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_RCOAL_VDE_0_VDEMBER_RCOAL_TMVAL_SHIFT                        _MK_SHIFT_CONST(8)
+#define MC_TIMEOUT_RCOAL_VDE_0_VDEMBER_RCOAL_TMVAL_FIELD                        (_MK_MASK_CONST(0xff) << MC_TIMEOUT_RCOAL_VDE_0_VDEMBER_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_VDE_0_VDEMBER_RCOAL_TMVAL_RANGE                        15:8
+#define MC_TIMEOUT_RCOAL_VDE_0_VDEMBER_RCOAL_TMVAL_WOFFSET                      0x0
+#define MC_TIMEOUT_RCOAL_VDE_0_VDEMBER_RCOAL_TMVAL_DEFAULT                      _MK_MASK_CONST(0x4)
+#define MC_TIMEOUT_RCOAL_VDE_0_VDEMBER_RCOAL_TMVAL_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_RCOAL_VDE_0_VDEMBER_RCOAL_TMVAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_VDE_0_VDEMBER_RCOAL_TMVAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_RCOAL_VDE_0_VDEMCER_RCOAL_TMVAL_SHIFT                        _MK_SHIFT_CONST(16)
+#define MC_TIMEOUT_RCOAL_VDE_0_VDEMCER_RCOAL_TMVAL_FIELD                        (_MK_MASK_CONST(0xff) << MC_TIMEOUT_RCOAL_VDE_0_VDEMCER_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_VDE_0_VDEMCER_RCOAL_TMVAL_RANGE                        23:16
+#define MC_TIMEOUT_RCOAL_VDE_0_VDEMCER_RCOAL_TMVAL_WOFFSET                      0x0
+#define MC_TIMEOUT_RCOAL_VDE_0_VDEMCER_RCOAL_TMVAL_DEFAULT                      _MK_MASK_CONST(0x4)
+#define MC_TIMEOUT_RCOAL_VDE_0_VDEMCER_RCOAL_TMVAL_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_RCOAL_VDE_0_VDEMCER_RCOAL_TMVAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_VDE_0_VDEMCER_RCOAL_TMVAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_RCOAL_VDE_0_VDETPER_RCOAL_TMVAL_SHIFT                        _MK_SHIFT_CONST(24)
+#define MC_TIMEOUT_RCOAL_VDE_0_VDETPER_RCOAL_TMVAL_FIELD                        (_MK_MASK_CONST(0xff) << MC_TIMEOUT_RCOAL_VDE_0_VDETPER_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_VDE_0_VDETPER_RCOAL_TMVAL_RANGE                        31:24
+#define MC_TIMEOUT_RCOAL_VDE_0_VDETPER_RCOAL_TMVAL_WOFFSET                      0x0
+#define MC_TIMEOUT_RCOAL_VDE_0_VDETPER_RCOAL_TMVAL_DEFAULT                      _MK_MASK_CONST(0x4)
+#define MC_TIMEOUT_RCOAL_VDE_0_VDETPER_RCOAL_TMVAL_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_RCOAL_VDE_0_VDETPER_RCOAL_TMVAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_VDE_0_VDETPER_RCOAL_TMVAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register MC_TIMEOUT_RCOAL_VI_0  
+#define MC_TIMEOUT_RCOAL_VI_0                   _MK_ADDR_CONST(0x230)
+#define MC_TIMEOUT_RCOAL_VI_0_SECURE                    0x0
+#define MC_TIMEOUT_RCOAL_VI_0_WORD_COUNT                        0x1
+#define MC_TIMEOUT_RCOAL_VI_0_RESET_VAL                         _MK_MASK_CONST(0x4)
+#define MC_TIMEOUT_RCOAL_VI_0_RESET_MASK                        _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_RCOAL_VI_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_VI_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_VI_0_READ_MASK                         _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_RCOAL_VI_0_WRITE_MASK                        _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_RCOAL_VI_0_VIRUV_RCOAL_TMVAL_SHIFT                   _MK_SHIFT_CONST(0)
+#define MC_TIMEOUT_RCOAL_VI_0_VIRUV_RCOAL_TMVAL_FIELD                   (_MK_MASK_CONST(0xff) << MC_TIMEOUT_RCOAL_VI_0_VIRUV_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_VI_0_VIRUV_RCOAL_TMVAL_RANGE                   7:0
+#define MC_TIMEOUT_RCOAL_VI_0_VIRUV_RCOAL_TMVAL_WOFFSET                 0x0
+#define MC_TIMEOUT_RCOAL_VI_0_VIRUV_RCOAL_TMVAL_DEFAULT                 _MK_MASK_CONST(0x4)
+#define MC_TIMEOUT_RCOAL_VI_0_VIRUV_RCOAL_TMVAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_RCOAL_VI_0_VIRUV_RCOAL_TMVAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_VI_0_VIRUV_RCOAL_TMVAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define MC_CLIENT_RCOAL_AUTODISABLE_DISABLE     0
+#define MC_CLIENT_RCOAL_AUTODISABLE_ENABLE      1
+
+// Register MC_RCOAL_AUTODISABLE_0_0  
+#define MC_RCOAL_AUTODISABLE_0_0                        _MK_ADDR_CONST(0x234)
+#define MC_RCOAL_AUTODISABLE_0_0_SECURE                         0x0
+#define MC_RCOAL_AUTODISABLE_0_0_WORD_COUNT                     0x1
+#define MC_RCOAL_AUTODISABLE_0_0_RESET_VAL                      _MK_MASK_CONST(0x1fff)
+#define MC_RCOAL_AUTODISABLE_0_0_RESET_MASK                     _MK_MASK_CONST(0x1fff)
+#define MC_RCOAL_AUTODISABLE_0_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define MC_RCOAL_AUTODISABLE_0_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_RCOAL_AUTODISABLE_0_0_READ_MASK                      _MK_MASK_CONST(0x1fff)
+#define MC_RCOAL_AUTODISABLE_0_0_WRITE_MASK                     _MK_MASK_CONST(0x1fff)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0A_RCOAL_AUTODISABLE_EN_SHIFT                   _MK_SHIFT_CONST(0)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0A_RCOAL_AUTODISABLE_EN_FIELD                   (_MK_MASK_CONST(0x1) << MC_RCOAL_AUTODISABLE_0_0_DISPLAY0A_RCOAL_AUTODISABLE_EN_SHIFT)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0A_RCOAL_AUTODISABLE_EN_RANGE                   0:0
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0A_RCOAL_AUTODISABLE_EN_WOFFSET                 0x0
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0A_RCOAL_AUTODISABLE_EN_DEFAULT                 _MK_MASK_CONST(0x1)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0A_RCOAL_AUTODISABLE_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0A_RCOAL_AUTODISABLE_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0A_RCOAL_AUTODISABLE_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0A_RCOAL_AUTODISABLE_EN_INIT_ENUM                       ENABLE
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0A_RCOAL_AUTODISABLE_EN_DISABLE                 _MK_ENUM_CONST(0)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0A_RCOAL_AUTODISABLE_EN_ENABLE                  _MK_ENUM_CONST(1)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0A_RCOAL_AUTODISABLE_EN_DISABLED                        _MK_ENUM_CONST(0)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0A_RCOAL_AUTODISABLE_EN_ENABLED                 _MK_ENUM_CONST(1)
+
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0AB_RCOAL_AUTODISABLE_EN_SHIFT                  _MK_SHIFT_CONST(1)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0AB_RCOAL_AUTODISABLE_EN_FIELD                  (_MK_MASK_CONST(0x1) << MC_RCOAL_AUTODISABLE_0_0_DISPLAY0AB_RCOAL_AUTODISABLE_EN_SHIFT)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0AB_RCOAL_AUTODISABLE_EN_RANGE                  1:1
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0AB_RCOAL_AUTODISABLE_EN_WOFFSET                        0x0
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0AB_RCOAL_AUTODISABLE_EN_DEFAULT                        _MK_MASK_CONST(0x1)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0AB_RCOAL_AUTODISABLE_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0AB_RCOAL_AUTODISABLE_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0AB_RCOAL_AUTODISABLE_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0AB_RCOAL_AUTODISABLE_EN_INIT_ENUM                      ENABLE
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0AB_RCOAL_AUTODISABLE_EN_DISABLE                        _MK_ENUM_CONST(0)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0AB_RCOAL_AUTODISABLE_EN_ENABLE                 _MK_ENUM_CONST(1)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0AB_RCOAL_AUTODISABLE_EN_DISABLED                       _MK_ENUM_CONST(0)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0AB_RCOAL_AUTODISABLE_EN_ENABLED                        _MK_ENUM_CONST(1)
+
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0B_RCOAL_AUTODISABLE_EN_SHIFT                   _MK_SHIFT_CONST(2)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0B_RCOAL_AUTODISABLE_EN_FIELD                   (_MK_MASK_CONST(0x1) << MC_RCOAL_AUTODISABLE_0_0_DISPLAY0B_RCOAL_AUTODISABLE_EN_SHIFT)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0B_RCOAL_AUTODISABLE_EN_RANGE                   2:2
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0B_RCOAL_AUTODISABLE_EN_WOFFSET                 0x0
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0B_RCOAL_AUTODISABLE_EN_DEFAULT                 _MK_MASK_CONST(0x1)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0B_RCOAL_AUTODISABLE_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0B_RCOAL_AUTODISABLE_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0B_RCOAL_AUTODISABLE_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0B_RCOAL_AUTODISABLE_EN_INIT_ENUM                       ENABLE
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0B_RCOAL_AUTODISABLE_EN_DISABLE                 _MK_ENUM_CONST(0)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0B_RCOAL_AUTODISABLE_EN_ENABLE                  _MK_ENUM_CONST(1)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0B_RCOAL_AUTODISABLE_EN_DISABLED                        _MK_ENUM_CONST(0)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0B_RCOAL_AUTODISABLE_EN_ENABLED                 _MK_ENUM_CONST(1)
+
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0BB_RCOAL_AUTODISABLE_EN_SHIFT                  _MK_SHIFT_CONST(3)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0BB_RCOAL_AUTODISABLE_EN_FIELD                  (_MK_MASK_CONST(0x1) << MC_RCOAL_AUTODISABLE_0_0_DISPLAY0BB_RCOAL_AUTODISABLE_EN_SHIFT)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0BB_RCOAL_AUTODISABLE_EN_RANGE                  3:3
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0BB_RCOAL_AUTODISABLE_EN_WOFFSET                        0x0
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0BB_RCOAL_AUTODISABLE_EN_DEFAULT                        _MK_MASK_CONST(0x1)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0BB_RCOAL_AUTODISABLE_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0BB_RCOAL_AUTODISABLE_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0BB_RCOAL_AUTODISABLE_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0BB_RCOAL_AUTODISABLE_EN_INIT_ENUM                      ENABLE
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0BB_RCOAL_AUTODISABLE_EN_DISABLE                        _MK_ENUM_CONST(0)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0BB_RCOAL_AUTODISABLE_EN_ENABLE                 _MK_ENUM_CONST(1)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0BB_RCOAL_AUTODISABLE_EN_DISABLED                       _MK_ENUM_CONST(0)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0BB_RCOAL_AUTODISABLE_EN_ENABLED                        _MK_ENUM_CONST(1)
+
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0C_RCOAL_AUTODISABLE_EN_SHIFT                   _MK_SHIFT_CONST(4)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0C_RCOAL_AUTODISABLE_EN_FIELD                   (_MK_MASK_CONST(0x1) << MC_RCOAL_AUTODISABLE_0_0_DISPLAY0C_RCOAL_AUTODISABLE_EN_SHIFT)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0C_RCOAL_AUTODISABLE_EN_RANGE                   4:4
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0C_RCOAL_AUTODISABLE_EN_WOFFSET                 0x0
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0C_RCOAL_AUTODISABLE_EN_DEFAULT                 _MK_MASK_CONST(0x1)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0C_RCOAL_AUTODISABLE_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0C_RCOAL_AUTODISABLE_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0C_RCOAL_AUTODISABLE_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0C_RCOAL_AUTODISABLE_EN_INIT_ENUM                       ENABLE
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0C_RCOAL_AUTODISABLE_EN_DISABLE                 _MK_ENUM_CONST(0)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0C_RCOAL_AUTODISABLE_EN_ENABLE                  _MK_ENUM_CONST(1)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0C_RCOAL_AUTODISABLE_EN_DISABLED                        _MK_ENUM_CONST(0)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0C_RCOAL_AUTODISABLE_EN_ENABLED                 _MK_ENUM_CONST(1)
+
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0CB_RCOAL_AUTODISABLE_EN_SHIFT                  _MK_SHIFT_CONST(5)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0CB_RCOAL_AUTODISABLE_EN_FIELD                  (_MK_MASK_CONST(0x1) << MC_RCOAL_AUTODISABLE_0_0_DISPLAY0CB_RCOAL_AUTODISABLE_EN_SHIFT)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0CB_RCOAL_AUTODISABLE_EN_RANGE                  5:5
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0CB_RCOAL_AUTODISABLE_EN_WOFFSET                        0x0
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0CB_RCOAL_AUTODISABLE_EN_DEFAULT                        _MK_MASK_CONST(0x1)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0CB_RCOAL_AUTODISABLE_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0CB_RCOAL_AUTODISABLE_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0CB_RCOAL_AUTODISABLE_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0CB_RCOAL_AUTODISABLE_EN_INIT_ENUM                      ENABLE
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0CB_RCOAL_AUTODISABLE_EN_DISABLE                        _MK_ENUM_CONST(0)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0CB_RCOAL_AUTODISABLE_EN_ENABLE                 _MK_ENUM_CONST(1)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0CB_RCOAL_AUTODISABLE_EN_DISABLED                       _MK_ENUM_CONST(0)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0CB_RCOAL_AUTODISABLE_EN_ENABLED                        _MK_ENUM_CONST(1)
+
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY1B_RCOAL_AUTODISABLE_EN_SHIFT                   _MK_SHIFT_CONST(6)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY1B_RCOAL_AUTODISABLE_EN_FIELD                   (_MK_MASK_CONST(0x1) << MC_RCOAL_AUTODISABLE_0_0_DISPLAY1B_RCOAL_AUTODISABLE_EN_SHIFT)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY1B_RCOAL_AUTODISABLE_EN_RANGE                   6:6
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY1B_RCOAL_AUTODISABLE_EN_WOFFSET                 0x0
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY1B_RCOAL_AUTODISABLE_EN_DEFAULT                 _MK_MASK_CONST(0x1)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY1B_RCOAL_AUTODISABLE_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY1B_RCOAL_AUTODISABLE_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY1B_RCOAL_AUTODISABLE_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY1B_RCOAL_AUTODISABLE_EN_INIT_ENUM                       ENABLE
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY1B_RCOAL_AUTODISABLE_EN_DISABLE                 _MK_ENUM_CONST(0)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY1B_RCOAL_AUTODISABLE_EN_ENABLE                  _MK_ENUM_CONST(1)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY1B_RCOAL_AUTODISABLE_EN_DISABLED                        _MK_ENUM_CONST(0)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY1B_RCOAL_AUTODISABLE_EN_ENABLED                 _MK_ENUM_CONST(1)
+
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY1BB_RCOAL_AUTODISABLE_EN_SHIFT                  _MK_SHIFT_CONST(7)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY1BB_RCOAL_AUTODISABLE_EN_FIELD                  (_MK_MASK_CONST(0x1) << MC_RCOAL_AUTODISABLE_0_0_DISPLAY1BB_RCOAL_AUTODISABLE_EN_SHIFT)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY1BB_RCOAL_AUTODISABLE_EN_RANGE                  7:7
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY1BB_RCOAL_AUTODISABLE_EN_WOFFSET                        0x0
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY1BB_RCOAL_AUTODISABLE_EN_DEFAULT                        _MK_MASK_CONST(0x1)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY1BB_RCOAL_AUTODISABLE_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY1BB_RCOAL_AUTODISABLE_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY1BB_RCOAL_AUTODISABLE_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY1BB_RCOAL_AUTODISABLE_EN_INIT_ENUM                      ENABLE
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY1BB_RCOAL_AUTODISABLE_EN_DISABLE                        _MK_ENUM_CONST(0)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY1BB_RCOAL_AUTODISABLE_EN_ENABLE                 _MK_ENUM_CONST(1)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY1BB_RCOAL_AUTODISABLE_EN_DISABLED                       _MK_ENUM_CONST(0)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY1BB_RCOAL_AUTODISABLE_EN_ENABLED                        _MK_ENUM_CONST(1)
+
+#define MC_RCOAL_AUTODISABLE_0_0_EPPUP_RCOAL_AUTODISABLE_EN_SHIFT                       _MK_SHIFT_CONST(8)
+#define MC_RCOAL_AUTODISABLE_0_0_EPPUP_RCOAL_AUTODISABLE_EN_FIELD                       (_MK_MASK_CONST(0x1) << MC_RCOAL_AUTODISABLE_0_0_EPPUP_RCOAL_AUTODISABLE_EN_SHIFT)
+#define MC_RCOAL_AUTODISABLE_0_0_EPPUP_RCOAL_AUTODISABLE_EN_RANGE                       8:8
+#define MC_RCOAL_AUTODISABLE_0_0_EPPUP_RCOAL_AUTODISABLE_EN_WOFFSET                     0x0
+#define MC_RCOAL_AUTODISABLE_0_0_EPPUP_RCOAL_AUTODISABLE_EN_DEFAULT                     _MK_MASK_CONST(0x1)
+#define MC_RCOAL_AUTODISABLE_0_0_EPPUP_RCOAL_AUTODISABLE_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_RCOAL_AUTODISABLE_0_0_EPPUP_RCOAL_AUTODISABLE_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_RCOAL_AUTODISABLE_0_0_EPPUP_RCOAL_AUTODISABLE_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_RCOAL_AUTODISABLE_0_0_EPPUP_RCOAL_AUTODISABLE_EN_INIT_ENUM                   ENABLE
+#define MC_RCOAL_AUTODISABLE_0_0_EPPUP_RCOAL_AUTODISABLE_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_RCOAL_AUTODISABLE_0_0_EPPUP_RCOAL_AUTODISABLE_EN_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_RCOAL_AUTODISABLE_0_0_EPPUP_RCOAL_AUTODISABLE_EN_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_RCOAL_AUTODISABLE_0_0_EPPUP_RCOAL_AUTODISABLE_EN_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_RCOAL_AUTODISABLE_0_0_G2PR_RCOAL_AUTODISABLE_EN_SHIFT                        _MK_SHIFT_CONST(9)
+#define MC_RCOAL_AUTODISABLE_0_0_G2PR_RCOAL_AUTODISABLE_EN_FIELD                        (_MK_MASK_CONST(0x1) << MC_RCOAL_AUTODISABLE_0_0_G2PR_RCOAL_AUTODISABLE_EN_SHIFT)
+#define MC_RCOAL_AUTODISABLE_0_0_G2PR_RCOAL_AUTODISABLE_EN_RANGE                        9:9
+#define MC_RCOAL_AUTODISABLE_0_0_G2PR_RCOAL_AUTODISABLE_EN_WOFFSET                      0x0
+#define MC_RCOAL_AUTODISABLE_0_0_G2PR_RCOAL_AUTODISABLE_EN_DEFAULT                      _MK_MASK_CONST(0x1)
+#define MC_RCOAL_AUTODISABLE_0_0_G2PR_RCOAL_AUTODISABLE_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_RCOAL_AUTODISABLE_0_0_G2PR_RCOAL_AUTODISABLE_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_RCOAL_AUTODISABLE_0_0_G2PR_RCOAL_AUTODISABLE_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_RCOAL_AUTODISABLE_0_0_G2PR_RCOAL_AUTODISABLE_EN_INIT_ENUM                    ENABLE
+#define MC_RCOAL_AUTODISABLE_0_0_G2PR_RCOAL_AUTODISABLE_EN_DISABLE                      _MK_ENUM_CONST(0)
+#define MC_RCOAL_AUTODISABLE_0_0_G2PR_RCOAL_AUTODISABLE_EN_ENABLE                       _MK_ENUM_CONST(1)
+#define MC_RCOAL_AUTODISABLE_0_0_G2PR_RCOAL_AUTODISABLE_EN_DISABLED                     _MK_ENUM_CONST(0)
+#define MC_RCOAL_AUTODISABLE_0_0_G2PR_RCOAL_AUTODISABLE_EN_ENABLED                      _MK_ENUM_CONST(1)
+
+#define MC_RCOAL_AUTODISABLE_0_0_G2SR_RCOAL_AUTODISABLE_EN_SHIFT                        _MK_SHIFT_CONST(10)
+#define MC_RCOAL_AUTODISABLE_0_0_G2SR_RCOAL_AUTODISABLE_EN_FIELD                        (_MK_MASK_CONST(0x1) << MC_RCOAL_AUTODISABLE_0_0_G2SR_RCOAL_AUTODISABLE_EN_SHIFT)
+#define MC_RCOAL_AUTODISABLE_0_0_G2SR_RCOAL_AUTODISABLE_EN_RANGE                        10:10
+#define MC_RCOAL_AUTODISABLE_0_0_G2SR_RCOAL_AUTODISABLE_EN_WOFFSET                      0x0
+#define MC_RCOAL_AUTODISABLE_0_0_G2SR_RCOAL_AUTODISABLE_EN_DEFAULT                      _MK_MASK_CONST(0x1)
+#define MC_RCOAL_AUTODISABLE_0_0_G2SR_RCOAL_AUTODISABLE_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_RCOAL_AUTODISABLE_0_0_G2SR_RCOAL_AUTODISABLE_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_RCOAL_AUTODISABLE_0_0_G2SR_RCOAL_AUTODISABLE_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_RCOAL_AUTODISABLE_0_0_G2SR_RCOAL_AUTODISABLE_EN_INIT_ENUM                    ENABLE
+#define MC_RCOAL_AUTODISABLE_0_0_G2SR_RCOAL_AUTODISABLE_EN_DISABLE                      _MK_ENUM_CONST(0)
+#define MC_RCOAL_AUTODISABLE_0_0_G2SR_RCOAL_AUTODISABLE_EN_ENABLE                       _MK_ENUM_CONST(1)
+#define MC_RCOAL_AUTODISABLE_0_0_G2SR_RCOAL_AUTODISABLE_EN_DISABLED                     _MK_ENUM_CONST(0)
+#define MC_RCOAL_AUTODISABLE_0_0_G2SR_RCOAL_AUTODISABLE_EN_ENABLED                      _MK_ENUM_CONST(1)
+
+#define MC_RCOAL_AUTODISABLE_0_0_MPEUNIFBR_RCOAL_AUTODISABLE_EN_SHIFT                   _MK_SHIFT_CONST(11)
+#define MC_RCOAL_AUTODISABLE_0_0_MPEUNIFBR_RCOAL_AUTODISABLE_EN_FIELD                   (_MK_MASK_CONST(0x1) << MC_RCOAL_AUTODISABLE_0_0_MPEUNIFBR_RCOAL_AUTODISABLE_EN_SHIFT)
+#define MC_RCOAL_AUTODISABLE_0_0_MPEUNIFBR_RCOAL_AUTODISABLE_EN_RANGE                   11:11
+#define MC_RCOAL_AUTODISABLE_0_0_MPEUNIFBR_RCOAL_AUTODISABLE_EN_WOFFSET                 0x0
+#define MC_RCOAL_AUTODISABLE_0_0_MPEUNIFBR_RCOAL_AUTODISABLE_EN_DEFAULT                 _MK_MASK_CONST(0x1)
+#define MC_RCOAL_AUTODISABLE_0_0_MPEUNIFBR_RCOAL_AUTODISABLE_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define MC_RCOAL_AUTODISABLE_0_0_MPEUNIFBR_RCOAL_AUTODISABLE_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_RCOAL_AUTODISABLE_0_0_MPEUNIFBR_RCOAL_AUTODISABLE_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_RCOAL_AUTODISABLE_0_0_MPEUNIFBR_RCOAL_AUTODISABLE_EN_INIT_ENUM                       ENABLE
+#define MC_RCOAL_AUTODISABLE_0_0_MPEUNIFBR_RCOAL_AUTODISABLE_EN_DISABLE                 _MK_ENUM_CONST(0)
+#define MC_RCOAL_AUTODISABLE_0_0_MPEUNIFBR_RCOAL_AUTODISABLE_EN_ENABLE                  _MK_ENUM_CONST(1)
+#define MC_RCOAL_AUTODISABLE_0_0_MPEUNIFBR_RCOAL_AUTODISABLE_EN_DISABLED                        _MK_ENUM_CONST(0)
+#define MC_RCOAL_AUTODISABLE_0_0_MPEUNIFBR_RCOAL_AUTODISABLE_EN_ENABLED                 _MK_ENUM_CONST(1)
+
+#define MC_RCOAL_AUTODISABLE_0_0_VIRUV_RCOAL_AUTODISABLE_EN_SHIFT                       _MK_SHIFT_CONST(12)
+#define MC_RCOAL_AUTODISABLE_0_0_VIRUV_RCOAL_AUTODISABLE_EN_FIELD                       (_MK_MASK_CONST(0x1) << MC_RCOAL_AUTODISABLE_0_0_VIRUV_RCOAL_AUTODISABLE_EN_SHIFT)
+#define MC_RCOAL_AUTODISABLE_0_0_VIRUV_RCOAL_AUTODISABLE_EN_RANGE                       12:12
+#define MC_RCOAL_AUTODISABLE_0_0_VIRUV_RCOAL_AUTODISABLE_EN_WOFFSET                     0x0
+#define MC_RCOAL_AUTODISABLE_0_0_VIRUV_RCOAL_AUTODISABLE_EN_DEFAULT                     _MK_MASK_CONST(0x1)
+#define MC_RCOAL_AUTODISABLE_0_0_VIRUV_RCOAL_AUTODISABLE_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_RCOAL_AUTODISABLE_0_0_VIRUV_RCOAL_AUTODISABLE_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_RCOAL_AUTODISABLE_0_0_VIRUV_RCOAL_AUTODISABLE_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_RCOAL_AUTODISABLE_0_0_VIRUV_RCOAL_AUTODISABLE_EN_INIT_ENUM                   ENABLE
+#define MC_RCOAL_AUTODISABLE_0_0_VIRUV_RCOAL_AUTODISABLE_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_RCOAL_AUTODISABLE_0_0_VIRUV_RCOAL_AUTODISABLE_EN_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_RCOAL_AUTODISABLE_0_0_VIRUV_RCOAL_AUTODISABLE_EN_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_RCOAL_AUTODISABLE_0_0_VIRUV_RCOAL_AUTODISABLE_EN_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_INCVAL_SIZE  11
+#define MC_BWSHARE_HIGHTH_SIZE  8
+#define MC_BWSHARE_MAXTH_SIZE   8
+#define MC_BWSHARE_ALWAYSINC_DISABLE    0
+#define MC_BWSHARE_ALWAYSINC_ENABLE     1
+#define MC_BWSHARE_TMSFACTORSEL_1       0
+#define MC_BWSHARE_TMSFACTORSEL_2       1
+
+// Register MC_BWSHARE_AVPC_0  
+#define MC_BWSHARE_AVPC_0                       _MK_ADDR_CONST(0x238)
+#define MC_BWSHARE_AVPC_0_SECURE                        0x0
+#define MC_BWSHARE_AVPC_0_WORD_COUNT                    0x1
+#define MC_BWSHARE_AVPC_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_AVPC_0_RESET_MASK                    _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_AVPC_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_AVPC_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_AVPC_0_READ_MASK                     _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_AVPC_0_WRITE_MASK                    _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_AVPC_0_AVPC_BW_INCVAL_SHIFT                  _MK_SHIFT_CONST(0)
+#define MC_BWSHARE_AVPC_0_AVPC_BW_INCVAL_FIELD                  (_MK_MASK_CONST(0x7ff) << MC_BWSHARE_AVPC_0_AVPC_BW_INCVAL_SHIFT)
+#define MC_BWSHARE_AVPC_0_AVPC_BW_INCVAL_RANGE                  10:0
+#define MC_BWSHARE_AVPC_0_AVPC_BW_INCVAL_WOFFSET                        0x0
+#define MC_BWSHARE_AVPC_0_AVPC_BW_INCVAL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_AVPC_0_AVPC_BW_INCVAL_DEFAULT_MASK                   _MK_MASK_CONST(0x7ff)
+#define MC_BWSHARE_AVPC_0_AVPC_BW_INCVAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_AVPC_0_AVPC_BW_INCVAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_AVPC_0_AVPC_BW_HIGHTH_SHIFT                  _MK_SHIFT_CONST(11)
+#define MC_BWSHARE_AVPC_0_AVPC_BW_HIGHTH_FIELD                  (_MK_MASK_CONST(0xff) << MC_BWSHARE_AVPC_0_AVPC_BW_HIGHTH_SHIFT)
+#define MC_BWSHARE_AVPC_0_AVPC_BW_HIGHTH_RANGE                  18:11
+#define MC_BWSHARE_AVPC_0_AVPC_BW_HIGHTH_WOFFSET                        0x0
+#define MC_BWSHARE_AVPC_0_AVPC_BW_HIGHTH_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_AVPC_0_AVPC_BW_HIGHTH_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_AVPC_0_AVPC_BW_HIGHTH_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_AVPC_0_AVPC_BW_HIGHTH_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_AVPC_0_AVPC_BW_MAXTH_SHIFT                   _MK_SHIFT_CONST(19)
+#define MC_BWSHARE_AVPC_0_AVPC_BW_MAXTH_FIELD                   (_MK_MASK_CONST(0xff) << MC_BWSHARE_AVPC_0_AVPC_BW_MAXTH_SHIFT)
+#define MC_BWSHARE_AVPC_0_AVPC_BW_MAXTH_RANGE                   26:19
+#define MC_BWSHARE_AVPC_0_AVPC_BW_MAXTH_WOFFSET                 0x0
+#define MC_BWSHARE_AVPC_0_AVPC_BW_MAXTH_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_AVPC_0_AVPC_BW_MAXTH_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_AVPC_0_AVPC_BW_MAXTH_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_AVPC_0_AVPC_BW_MAXTH_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_AVPC_0_AVPC_BW_ALWAYSINC_SHIFT                       _MK_SHIFT_CONST(27)
+#define MC_BWSHARE_AVPC_0_AVPC_BW_ALWAYSINC_FIELD                       (_MK_MASK_CONST(0x1) << MC_BWSHARE_AVPC_0_AVPC_BW_ALWAYSINC_SHIFT)
+#define MC_BWSHARE_AVPC_0_AVPC_BW_ALWAYSINC_RANGE                       27:27
+#define MC_BWSHARE_AVPC_0_AVPC_BW_ALWAYSINC_WOFFSET                     0x0
+#define MC_BWSHARE_AVPC_0_AVPC_BW_ALWAYSINC_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_AVPC_0_AVPC_BW_ALWAYSINC_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_AVPC_0_AVPC_BW_ALWAYSINC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_AVPC_0_AVPC_BW_ALWAYSINC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_AVPC_0_AVPC_BW_ALWAYSINC_INIT_ENUM                   DISABLE
+#define MC_BWSHARE_AVPC_0_AVPC_BW_ALWAYSINC_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_BWSHARE_AVPC_0_AVPC_BW_ALWAYSINC_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_BWSHARE_AVPC_0_AVPC_BW_ALWAYSINC_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_BWSHARE_AVPC_0_AVPC_BW_ALWAYSINC_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_AVPC_0_AVPC_BW_TMSFACTORSEL_SHIFT                    _MK_SHIFT_CONST(28)
+#define MC_BWSHARE_AVPC_0_AVPC_BW_TMSFACTORSEL_FIELD                    (_MK_MASK_CONST(0x1) << MC_BWSHARE_AVPC_0_AVPC_BW_TMSFACTORSEL_SHIFT)
+#define MC_BWSHARE_AVPC_0_AVPC_BW_TMSFACTORSEL_RANGE                    28:28
+#define MC_BWSHARE_AVPC_0_AVPC_BW_TMSFACTORSEL_WOFFSET                  0x0
+#define MC_BWSHARE_AVPC_0_AVPC_BW_TMSFACTORSEL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_AVPC_0_AVPC_BW_TMSFACTORSEL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_AVPC_0_AVPC_BW_TMSFACTORSEL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_AVPC_0_AVPC_BW_TMSFACTORSEL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_AVPC_0_AVPC_BW_TMSFACTORSEL_INIT_ENUM                        TM_SFACTOR1
+#define MC_BWSHARE_AVPC_0_AVPC_BW_TMSFACTORSEL_TM_SFACTOR1                      _MK_ENUM_CONST(0)
+#define MC_BWSHARE_AVPC_0_AVPC_BW_TMSFACTORSEL_TM_SFACTOR2                      _MK_ENUM_CONST(1)
+
+
+// Register MC_BWSHARE_DC_0  
+#define MC_BWSHARE_DC_0                 _MK_ADDR_CONST(0x23c)
+#define MC_BWSHARE_DC_0_SECURE                  0x0
+#define MC_BWSHARE_DC_0_WORD_COUNT                      0x1
+#define MC_BWSHARE_DC_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_DC_0_RESET_MASK                      _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_DC_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_DC_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_DC_0_READ_MASK                       _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_DC_0_WRITE_MASK                      _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_DC_0_DC_BW_INCVAL_SHIFT                      _MK_SHIFT_CONST(0)
+#define MC_BWSHARE_DC_0_DC_BW_INCVAL_FIELD                      (_MK_MASK_CONST(0x7ff) << MC_BWSHARE_DC_0_DC_BW_INCVAL_SHIFT)
+#define MC_BWSHARE_DC_0_DC_BW_INCVAL_RANGE                      10:0
+#define MC_BWSHARE_DC_0_DC_BW_INCVAL_WOFFSET                    0x0
+#define MC_BWSHARE_DC_0_DC_BW_INCVAL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_DC_0_DC_BW_INCVAL_DEFAULT_MASK                       _MK_MASK_CONST(0x7ff)
+#define MC_BWSHARE_DC_0_DC_BW_INCVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_DC_0_DC_BW_INCVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_DC_0_DC_BW_HIGHTH_SHIFT                      _MK_SHIFT_CONST(11)
+#define MC_BWSHARE_DC_0_DC_BW_HIGHTH_FIELD                      (_MK_MASK_CONST(0xff) << MC_BWSHARE_DC_0_DC_BW_HIGHTH_SHIFT)
+#define MC_BWSHARE_DC_0_DC_BW_HIGHTH_RANGE                      18:11
+#define MC_BWSHARE_DC_0_DC_BW_HIGHTH_WOFFSET                    0x0
+#define MC_BWSHARE_DC_0_DC_BW_HIGHTH_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_DC_0_DC_BW_HIGHTH_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_DC_0_DC_BW_HIGHTH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_DC_0_DC_BW_HIGHTH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_DC_0_DC_BW_MAXTH_SHIFT                       _MK_SHIFT_CONST(19)
+#define MC_BWSHARE_DC_0_DC_BW_MAXTH_FIELD                       (_MK_MASK_CONST(0xff) << MC_BWSHARE_DC_0_DC_BW_MAXTH_SHIFT)
+#define MC_BWSHARE_DC_0_DC_BW_MAXTH_RANGE                       26:19
+#define MC_BWSHARE_DC_0_DC_BW_MAXTH_WOFFSET                     0x0
+#define MC_BWSHARE_DC_0_DC_BW_MAXTH_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_DC_0_DC_BW_MAXTH_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_DC_0_DC_BW_MAXTH_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_DC_0_DC_BW_MAXTH_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_DC_0_DC_BW_ALWAYSINC_SHIFT                   _MK_SHIFT_CONST(27)
+#define MC_BWSHARE_DC_0_DC_BW_ALWAYSINC_FIELD                   (_MK_MASK_CONST(0x1) << MC_BWSHARE_DC_0_DC_BW_ALWAYSINC_SHIFT)
+#define MC_BWSHARE_DC_0_DC_BW_ALWAYSINC_RANGE                   27:27
+#define MC_BWSHARE_DC_0_DC_BW_ALWAYSINC_WOFFSET                 0x0
+#define MC_BWSHARE_DC_0_DC_BW_ALWAYSINC_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_DC_0_DC_BW_ALWAYSINC_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_DC_0_DC_BW_ALWAYSINC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_DC_0_DC_BW_ALWAYSINC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_DC_0_DC_BW_ALWAYSINC_INIT_ENUM                       DISABLE
+#define MC_BWSHARE_DC_0_DC_BW_ALWAYSINC_DISABLE                 _MK_ENUM_CONST(0)
+#define MC_BWSHARE_DC_0_DC_BW_ALWAYSINC_ENABLE                  _MK_ENUM_CONST(1)
+#define MC_BWSHARE_DC_0_DC_BW_ALWAYSINC_DISABLED                        _MK_ENUM_CONST(0)
+#define MC_BWSHARE_DC_0_DC_BW_ALWAYSINC_ENABLED                 _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_DC_0_DC_BW_TMSFACTORSEL_SHIFT                        _MK_SHIFT_CONST(28)
+#define MC_BWSHARE_DC_0_DC_BW_TMSFACTORSEL_FIELD                        (_MK_MASK_CONST(0x1) << MC_BWSHARE_DC_0_DC_BW_TMSFACTORSEL_SHIFT)
+#define MC_BWSHARE_DC_0_DC_BW_TMSFACTORSEL_RANGE                        28:28
+#define MC_BWSHARE_DC_0_DC_BW_TMSFACTORSEL_WOFFSET                      0x0
+#define MC_BWSHARE_DC_0_DC_BW_TMSFACTORSEL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_DC_0_DC_BW_TMSFACTORSEL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_DC_0_DC_BW_TMSFACTORSEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_DC_0_DC_BW_TMSFACTORSEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_DC_0_DC_BW_TMSFACTORSEL_INIT_ENUM                    TM_SFACTOR1
+#define MC_BWSHARE_DC_0_DC_BW_TMSFACTORSEL_TM_SFACTOR1                  _MK_ENUM_CONST(0)
+#define MC_BWSHARE_DC_0_DC_BW_TMSFACTORSEL_TM_SFACTOR2                  _MK_ENUM_CONST(1)
+
+
+// Register MC_BWSHARE_DCB_0  
+#define MC_BWSHARE_DCB_0                        _MK_ADDR_CONST(0x240)
+#define MC_BWSHARE_DCB_0_SECURE                         0x0
+#define MC_BWSHARE_DCB_0_WORD_COUNT                     0x1
+#define MC_BWSHARE_DCB_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_DCB_0_RESET_MASK                     _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_DCB_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_DCB_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_DCB_0_READ_MASK                      _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_DCB_0_WRITE_MASK                     _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_DCB_0_DCB_BW_INCVAL_SHIFT                    _MK_SHIFT_CONST(0)
+#define MC_BWSHARE_DCB_0_DCB_BW_INCVAL_FIELD                    (_MK_MASK_CONST(0x7ff) << MC_BWSHARE_DCB_0_DCB_BW_INCVAL_SHIFT)
+#define MC_BWSHARE_DCB_0_DCB_BW_INCVAL_RANGE                    10:0
+#define MC_BWSHARE_DCB_0_DCB_BW_INCVAL_WOFFSET                  0x0
+#define MC_BWSHARE_DCB_0_DCB_BW_INCVAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_DCB_0_DCB_BW_INCVAL_DEFAULT_MASK                     _MK_MASK_CONST(0x7ff)
+#define MC_BWSHARE_DCB_0_DCB_BW_INCVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_DCB_0_DCB_BW_INCVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_DCB_0_DCB_BW_HIGHTH_SHIFT                    _MK_SHIFT_CONST(11)
+#define MC_BWSHARE_DCB_0_DCB_BW_HIGHTH_FIELD                    (_MK_MASK_CONST(0xff) << MC_BWSHARE_DCB_0_DCB_BW_HIGHTH_SHIFT)
+#define MC_BWSHARE_DCB_0_DCB_BW_HIGHTH_RANGE                    18:11
+#define MC_BWSHARE_DCB_0_DCB_BW_HIGHTH_WOFFSET                  0x0
+#define MC_BWSHARE_DCB_0_DCB_BW_HIGHTH_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_DCB_0_DCB_BW_HIGHTH_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_DCB_0_DCB_BW_HIGHTH_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_DCB_0_DCB_BW_HIGHTH_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_DCB_0_DCB_BW_MAXTH_SHIFT                     _MK_SHIFT_CONST(19)
+#define MC_BWSHARE_DCB_0_DCB_BW_MAXTH_FIELD                     (_MK_MASK_CONST(0xff) << MC_BWSHARE_DCB_0_DCB_BW_MAXTH_SHIFT)
+#define MC_BWSHARE_DCB_0_DCB_BW_MAXTH_RANGE                     26:19
+#define MC_BWSHARE_DCB_0_DCB_BW_MAXTH_WOFFSET                   0x0
+#define MC_BWSHARE_DCB_0_DCB_BW_MAXTH_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_DCB_0_DCB_BW_MAXTH_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_DCB_0_DCB_BW_MAXTH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_DCB_0_DCB_BW_MAXTH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_DCB_0_DCB_BW_ALWAYSINC_SHIFT                 _MK_SHIFT_CONST(27)
+#define MC_BWSHARE_DCB_0_DCB_BW_ALWAYSINC_FIELD                 (_MK_MASK_CONST(0x1) << MC_BWSHARE_DCB_0_DCB_BW_ALWAYSINC_SHIFT)
+#define MC_BWSHARE_DCB_0_DCB_BW_ALWAYSINC_RANGE                 27:27
+#define MC_BWSHARE_DCB_0_DCB_BW_ALWAYSINC_WOFFSET                       0x0
+#define MC_BWSHARE_DCB_0_DCB_BW_ALWAYSINC_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_DCB_0_DCB_BW_ALWAYSINC_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_DCB_0_DCB_BW_ALWAYSINC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_DCB_0_DCB_BW_ALWAYSINC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_DCB_0_DCB_BW_ALWAYSINC_INIT_ENUM                     DISABLE
+#define MC_BWSHARE_DCB_0_DCB_BW_ALWAYSINC_DISABLE                       _MK_ENUM_CONST(0)
+#define MC_BWSHARE_DCB_0_DCB_BW_ALWAYSINC_ENABLE                        _MK_ENUM_CONST(1)
+#define MC_BWSHARE_DCB_0_DCB_BW_ALWAYSINC_DISABLED                      _MK_ENUM_CONST(0)
+#define MC_BWSHARE_DCB_0_DCB_BW_ALWAYSINC_ENABLED                       _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_DCB_0_DCB_BW_TMSFACTORSEL_SHIFT                      _MK_SHIFT_CONST(28)
+#define MC_BWSHARE_DCB_0_DCB_BW_TMSFACTORSEL_FIELD                      (_MK_MASK_CONST(0x1) << MC_BWSHARE_DCB_0_DCB_BW_TMSFACTORSEL_SHIFT)
+#define MC_BWSHARE_DCB_0_DCB_BW_TMSFACTORSEL_RANGE                      28:28
+#define MC_BWSHARE_DCB_0_DCB_BW_TMSFACTORSEL_WOFFSET                    0x0
+#define MC_BWSHARE_DCB_0_DCB_BW_TMSFACTORSEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_DCB_0_DCB_BW_TMSFACTORSEL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_DCB_0_DCB_BW_TMSFACTORSEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_DCB_0_DCB_BW_TMSFACTORSEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_DCB_0_DCB_BW_TMSFACTORSEL_INIT_ENUM                  TM_SFACTOR1
+#define MC_BWSHARE_DCB_0_DCB_BW_TMSFACTORSEL_TM_SFACTOR1                        _MK_ENUM_CONST(0)
+#define MC_BWSHARE_DCB_0_DCB_BW_TMSFACTORSEL_TM_SFACTOR2                        _MK_ENUM_CONST(1)
+
+
+// Register MC_BWSHARE_EPP_0  
+#define MC_BWSHARE_EPP_0                        _MK_ADDR_CONST(0x244)
+#define MC_BWSHARE_EPP_0_SECURE                         0x0
+#define MC_BWSHARE_EPP_0_WORD_COUNT                     0x1
+#define MC_BWSHARE_EPP_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EPP_0_RESET_MASK                     _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_EPP_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EPP_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EPP_0_READ_MASK                      _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_EPP_0_WRITE_MASK                     _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_EPP_0_EPP_BW_INCVAL_SHIFT                    _MK_SHIFT_CONST(0)
+#define MC_BWSHARE_EPP_0_EPP_BW_INCVAL_FIELD                    (_MK_MASK_CONST(0x7ff) << MC_BWSHARE_EPP_0_EPP_BW_INCVAL_SHIFT)
+#define MC_BWSHARE_EPP_0_EPP_BW_INCVAL_RANGE                    10:0
+#define MC_BWSHARE_EPP_0_EPP_BW_INCVAL_WOFFSET                  0x0
+#define MC_BWSHARE_EPP_0_EPP_BW_INCVAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EPP_0_EPP_BW_INCVAL_DEFAULT_MASK                     _MK_MASK_CONST(0x7ff)
+#define MC_BWSHARE_EPP_0_EPP_BW_INCVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EPP_0_EPP_BW_INCVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_EPP_0_EPP_BW_HIGHTH_SHIFT                    _MK_SHIFT_CONST(11)
+#define MC_BWSHARE_EPP_0_EPP_BW_HIGHTH_FIELD                    (_MK_MASK_CONST(0xff) << MC_BWSHARE_EPP_0_EPP_BW_HIGHTH_SHIFT)
+#define MC_BWSHARE_EPP_0_EPP_BW_HIGHTH_RANGE                    18:11
+#define MC_BWSHARE_EPP_0_EPP_BW_HIGHTH_WOFFSET                  0x0
+#define MC_BWSHARE_EPP_0_EPP_BW_HIGHTH_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EPP_0_EPP_BW_HIGHTH_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_EPP_0_EPP_BW_HIGHTH_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EPP_0_EPP_BW_HIGHTH_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_EPP_0_EPP_BW_MAXTH_SHIFT                     _MK_SHIFT_CONST(19)
+#define MC_BWSHARE_EPP_0_EPP_BW_MAXTH_FIELD                     (_MK_MASK_CONST(0xff) << MC_BWSHARE_EPP_0_EPP_BW_MAXTH_SHIFT)
+#define MC_BWSHARE_EPP_0_EPP_BW_MAXTH_RANGE                     26:19
+#define MC_BWSHARE_EPP_0_EPP_BW_MAXTH_WOFFSET                   0x0
+#define MC_BWSHARE_EPP_0_EPP_BW_MAXTH_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EPP_0_EPP_BW_MAXTH_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_EPP_0_EPP_BW_MAXTH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EPP_0_EPP_BW_MAXTH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_EPP_0_EPP_BW_ALWAYSINC_SHIFT                 _MK_SHIFT_CONST(27)
+#define MC_BWSHARE_EPP_0_EPP_BW_ALWAYSINC_FIELD                 (_MK_MASK_CONST(0x1) << MC_BWSHARE_EPP_0_EPP_BW_ALWAYSINC_SHIFT)
+#define MC_BWSHARE_EPP_0_EPP_BW_ALWAYSINC_RANGE                 27:27
+#define MC_BWSHARE_EPP_0_EPP_BW_ALWAYSINC_WOFFSET                       0x0
+#define MC_BWSHARE_EPP_0_EPP_BW_ALWAYSINC_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EPP_0_EPP_BW_ALWAYSINC_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EPP_0_EPP_BW_ALWAYSINC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EPP_0_EPP_BW_ALWAYSINC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EPP_0_EPP_BW_ALWAYSINC_INIT_ENUM                     DISABLE
+#define MC_BWSHARE_EPP_0_EPP_BW_ALWAYSINC_DISABLE                       _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EPP_0_EPP_BW_ALWAYSINC_ENABLE                        _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EPP_0_EPP_BW_ALWAYSINC_DISABLED                      _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EPP_0_EPP_BW_ALWAYSINC_ENABLED                       _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EPP_0_EPP_BW_TMSFACTORSEL_SHIFT                      _MK_SHIFT_CONST(28)
+#define MC_BWSHARE_EPP_0_EPP_BW_TMSFACTORSEL_FIELD                      (_MK_MASK_CONST(0x1) << MC_BWSHARE_EPP_0_EPP_BW_TMSFACTORSEL_SHIFT)
+#define MC_BWSHARE_EPP_0_EPP_BW_TMSFACTORSEL_RANGE                      28:28
+#define MC_BWSHARE_EPP_0_EPP_BW_TMSFACTORSEL_WOFFSET                    0x0
+#define MC_BWSHARE_EPP_0_EPP_BW_TMSFACTORSEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EPP_0_EPP_BW_TMSFACTORSEL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EPP_0_EPP_BW_TMSFACTORSEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EPP_0_EPP_BW_TMSFACTORSEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EPP_0_EPP_BW_TMSFACTORSEL_INIT_ENUM                  TM_SFACTOR1
+#define MC_BWSHARE_EPP_0_EPP_BW_TMSFACTORSEL_TM_SFACTOR1                        _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EPP_0_EPP_BW_TMSFACTORSEL_TM_SFACTOR2                        _MK_ENUM_CONST(1)
+
+
+// Register MC_BWSHARE_G2_0  
+#define MC_BWSHARE_G2_0                 _MK_ADDR_CONST(0x248)
+#define MC_BWSHARE_G2_0_SECURE                  0x0
+#define MC_BWSHARE_G2_0_WORD_COUNT                      0x1
+#define MC_BWSHARE_G2_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_G2_0_RESET_MASK                      _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_G2_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_G2_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_G2_0_READ_MASK                       _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_G2_0_WRITE_MASK                      _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_G2_0_G2_BW_INCVAL_SHIFT                      _MK_SHIFT_CONST(0)
+#define MC_BWSHARE_G2_0_G2_BW_INCVAL_FIELD                      (_MK_MASK_CONST(0x7ff) << MC_BWSHARE_G2_0_G2_BW_INCVAL_SHIFT)
+#define MC_BWSHARE_G2_0_G2_BW_INCVAL_RANGE                      10:0
+#define MC_BWSHARE_G2_0_G2_BW_INCVAL_WOFFSET                    0x0
+#define MC_BWSHARE_G2_0_G2_BW_INCVAL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_G2_0_G2_BW_INCVAL_DEFAULT_MASK                       _MK_MASK_CONST(0x7ff)
+#define MC_BWSHARE_G2_0_G2_BW_INCVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_G2_0_G2_BW_INCVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_G2_0_G2_BW_HIGHTH_SHIFT                      _MK_SHIFT_CONST(11)
+#define MC_BWSHARE_G2_0_G2_BW_HIGHTH_FIELD                      (_MK_MASK_CONST(0xff) << MC_BWSHARE_G2_0_G2_BW_HIGHTH_SHIFT)
+#define MC_BWSHARE_G2_0_G2_BW_HIGHTH_RANGE                      18:11
+#define MC_BWSHARE_G2_0_G2_BW_HIGHTH_WOFFSET                    0x0
+#define MC_BWSHARE_G2_0_G2_BW_HIGHTH_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_G2_0_G2_BW_HIGHTH_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_G2_0_G2_BW_HIGHTH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_G2_0_G2_BW_HIGHTH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_G2_0_G2_BW_MAXTH_SHIFT                       _MK_SHIFT_CONST(19)
+#define MC_BWSHARE_G2_0_G2_BW_MAXTH_FIELD                       (_MK_MASK_CONST(0xff) << MC_BWSHARE_G2_0_G2_BW_MAXTH_SHIFT)
+#define MC_BWSHARE_G2_0_G2_BW_MAXTH_RANGE                       26:19
+#define MC_BWSHARE_G2_0_G2_BW_MAXTH_WOFFSET                     0x0
+#define MC_BWSHARE_G2_0_G2_BW_MAXTH_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_G2_0_G2_BW_MAXTH_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_G2_0_G2_BW_MAXTH_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_G2_0_G2_BW_MAXTH_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_G2_0_G2_BW_ALWAYSINC_SHIFT                   _MK_SHIFT_CONST(27)
+#define MC_BWSHARE_G2_0_G2_BW_ALWAYSINC_FIELD                   (_MK_MASK_CONST(0x1) << MC_BWSHARE_G2_0_G2_BW_ALWAYSINC_SHIFT)
+#define MC_BWSHARE_G2_0_G2_BW_ALWAYSINC_RANGE                   27:27
+#define MC_BWSHARE_G2_0_G2_BW_ALWAYSINC_WOFFSET                 0x0
+#define MC_BWSHARE_G2_0_G2_BW_ALWAYSINC_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_G2_0_G2_BW_ALWAYSINC_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_G2_0_G2_BW_ALWAYSINC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_G2_0_G2_BW_ALWAYSINC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_G2_0_G2_BW_ALWAYSINC_INIT_ENUM                       DISABLE
+#define MC_BWSHARE_G2_0_G2_BW_ALWAYSINC_DISABLE                 _MK_ENUM_CONST(0)
+#define MC_BWSHARE_G2_0_G2_BW_ALWAYSINC_ENABLE                  _MK_ENUM_CONST(1)
+#define MC_BWSHARE_G2_0_G2_BW_ALWAYSINC_DISABLED                        _MK_ENUM_CONST(0)
+#define MC_BWSHARE_G2_0_G2_BW_ALWAYSINC_ENABLED                 _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_G2_0_G2_BW_TMSFACTORSEL_SHIFT                        _MK_SHIFT_CONST(28)
+#define MC_BWSHARE_G2_0_G2_BW_TMSFACTORSEL_FIELD                        (_MK_MASK_CONST(0x1) << MC_BWSHARE_G2_0_G2_BW_TMSFACTORSEL_SHIFT)
+#define MC_BWSHARE_G2_0_G2_BW_TMSFACTORSEL_RANGE                        28:28
+#define MC_BWSHARE_G2_0_G2_BW_TMSFACTORSEL_WOFFSET                      0x0
+#define MC_BWSHARE_G2_0_G2_BW_TMSFACTORSEL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_G2_0_G2_BW_TMSFACTORSEL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_G2_0_G2_BW_TMSFACTORSEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_G2_0_G2_BW_TMSFACTORSEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_G2_0_G2_BW_TMSFACTORSEL_INIT_ENUM                    TM_SFACTOR1
+#define MC_BWSHARE_G2_0_G2_BW_TMSFACTORSEL_TM_SFACTOR1                  _MK_ENUM_CONST(0)
+#define MC_BWSHARE_G2_0_G2_BW_TMSFACTORSEL_TM_SFACTOR2                  _MK_ENUM_CONST(1)
+
+
+// Register MC_BWSHARE_HC_0  
+#define MC_BWSHARE_HC_0                 _MK_ADDR_CONST(0x24c)
+#define MC_BWSHARE_HC_0_SECURE                  0x0
+#define MC_BWSHARE_HC_0_WORD_COUNT                      0x1
+#define MC_BWSHARE_HC_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_HC_0_RESET_MASK                      _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_HC_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_HC_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_HC_0_READ_MASK                       _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_HC_0_WRITE_MASK                      _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_HC_0_HC_BW_INCVAL_SHIFT                      _MK_SHIFT_CONST(0)
+#define MC_BWSHARE_HC_0_HC_BW_INCVAL_FIELD                      (_MK_MASK_CONST(0x7ff) << MC_BWSHARE_HC_0_HC_BW_INCVAL_SHIFT)
+#define MC_BWSHARE_HC_0_HC_BW_INCVAL_RANGE                      10:0
+#define MC_BWSHARE_HC_0_HC_BW_INCVAL_WOFFSET                    0x0
+#define MC_BWSHARE_HC_0_HC_BW_INCVAL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_HC_0_HC_BW_INCVAL_DEFAULT_MASK                       _MK_MASK_CONST(0x7ff)
+#define MC_BWSHARE_HC_0_HC_BW_INCVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_HC_0_HC_BW_INCVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_HC_0_HC_BW_HIGHTH_SHIFT                      _MK_SHIFT_CONST(11)
+#define MC_BWSHARE_HC_0_HC_BW_HIGHTH_FIELD                      (_MK_MASK_CONST(0xff) << MC_BWSHARE_HC_0_HC_BW_HIGHTH_SHIFT)
+#define MC_BWSHARE_HC_0_HC_BW_HIGHTH_RANGE                      18:11
+#define MC_BWSHARE_HC_0_HC_BW_HIGHTH_WOFFSET                    0x0
+#define MC_BWSHARE_HC_0_HC_BW_HIGHTH_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_HC_0_HC_BW_HIGHTH_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_HC_0_HC_BW_HIGHTH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_HC_0_HC_BW_HIGHTH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_HC_0_HC_BW_MAXTH_SHIFT                       _MK_SHIFT_CONST(19)
+#define MC_BWSHARE_HC_0_HC_BW_MAXTH_FIELD                       (_MK_MASK_CONST(0xff) << MC_BWSHARE_HC_0_HC_BW_MAXTH_SHIFT)
+#define MC_BWSHARE_HC_0_HC_BW_MAXTH_RANGE                       26:19
+#define MC_BWSHARE_HC_0_HC_BW_MAXTH_WOFFSET                     0x0
+#define MC_BWSHARE_HC_0_HC_BW_MAXTH_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_HC_0_HC_BW_MAXTH_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_HC_0_HC_BW_MAXTH_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_HC_0_HC_BW_MAXTH_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_HC_0_HC_BW_ALWAYSINC_SHIFT                   _MK_SHIFT_CONST(27)
+#define MC_BWSHARE_HC_0_HC_BW_ALWAYSINC_FIELD                   (_MK_MASK_CONST(0x1) << MC_BWSHARE_HC_0_HC_BW_ALWAYSINC_SHIFT)
+#define MC_BWSHARE_HC_0_HC_BW_ALWAYSINC_RANGE                   27:27
+#define MC_BWSHARE_HC_0_HC_BW_ALWAYSINC_WOFFSET                 0x0
+#define MC_BWSHARE_HC_0_HC_BW_ALWAYSINC_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_HC_0_HC_BW_ALWAYSINC_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_HC_0_HC_BW_ALWAYSINC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_HC_0_HC_BW_ALWAYSINC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_HC_0_HC_BW_ALWAYSINC_INIT_ENUM                       DISABLE
+#define MC_BWSHARE_HC_0_HC_BW_ALWAYSINC_DISABLE                 _MK_ENUM_CONST(0)
+#define MC_BWSHARE_HC_0_HC_BW_ALWAYSINC_ENABLE                  _MK_ENUM_CONST(1)
+#define MC_BWSHARE_HC_0_HC_BW_ALWAYSINC_DISABLED                        _MK_ENUM_CONST(0)
+#define MC_BWSHARE_HC_0_HC_BW_ALWAYSINC_ENABLED                 _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_HC_0_HC_BW_TMSFACTORSEL_SHIFT                        _MK_SHIFT_CONST(28)
+#define MC_BWSHARE_HC_0_HC_BW_TMSFACTORSEL_FIELD                        (_MK_MASK_CONST(0x1) << MC_BWSHARE_HC_0_HC_BW_TMSFACTORSEL_SHIFT)
+#define MC_BWSHARE_HC_0_HC_BW_TMSFACTORSEL_RANGE                        28:28
+#define MC_BWSHARE_HC_0_HC_BW_TMSFACTORSEL_WOFFSET                      0x0
+#define MC_BWSHARE_HC_0_HC_BW_TMSFACTORSEL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_HC_0_HC_BW_TMSFACTORSEL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_HC_0_HC_BW_TMSFACTORSEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_HC_0_HC_BW_TMSFACTORSEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_HC_0_HC_BW_TMSFACTORSEL_INIT_ENUM                    TM_SFACTOR1
+#define MC_BWSHARE_HC_0_HC_BW_TMSFACTORSEL_TM_SFACTOR1                  _MK_ENUM_CONST(0)
+#define MC_BWSHARE_HC_0_HC_BW_TMSFACTORSEL_TM_SFACTOR2                  _MK_ENUM_CONST(1)
+
+
+// Register MC_BWSHARE_ISP_0  
+#define MC_BWSHARE_ISP_0                        _MK_ADDR_CONST(0x250)
+#define MC_BWSHARE_ISP_0_SECURE                         0x0
+#define MC_BWSHARE_ISP_0_WORD_COUNT                     0x1
+#define MC_BWSHARE_ISP_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_ISP_0_RESET_MASK                     _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_ISP_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_ISP_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_ISP_0_READ_MASK                      _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_ISP_0_WRITE_MASK                     _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_ISP_0_ISP_BW_INCVAL_SHIFT                    _MK_SHIFT_CONST(0)
+#define MC_BWSHARE_ISP_0_ISP_BW_INCVAL_FIELD                    (_MK_MASK_CONST(0x7ff) << MC_BWSHARE_ISP_0_ISP_BW_INCVAL_SHIFT)
+#define MC_BWSHARE_ISP_0_ISP_BW_INCVAL_RANGE                    10:0
+#define MC_BWSHARE_ISP_0_ISP_BW_INCVAL_WOFFSET                  0x0
+#define MC_BWSHARE_ISP_0_ISP_BW_INCVAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_ISP_0_ISP_BW_INCVAL_DEFAULT_MASK                     _MK_MASK_CONST(0x7ff)
+#define MC_BWSHARE_ISP_0_ISP_BW_INCVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_ISP_0_ISP_BW_INCVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_ISP_0_ISP_BW_HIGHTH_SHIFT                    _MK_SHIFT_CONST(11)
+#define MC_BWSHARE_ISP_0_ISP_BW_HIGHTH_FIELD                    (_MK_MASK_CONST(0xff) << MC_BWSHARE_ISP_0_ISP_BW_HIGHTH_SHIFT)
+#define MC_BWSHARE_ISP_0_ISP_BW_HIGHTH_RANGE                    18:11
+#define MC_BWSHARE_ISP_0_ISP_BW_HIGHTH_WOFFSET                  0x0
+#define MC_BWSHARE_ISP_0_ISP_BW_HIGHTH_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_ISP_0_ISP_BW_HIGHTH_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_ISP_0_ISP_BW_HIGHTH_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_ISP_0_ISP_BW_HIGHTH_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_ISP_0_ISP_BW_MAXTH_SHIFT                     _MK_SHIFT_CONST(19)
+#define MC_BWSHARE_ISP_0_ISP_BW_MAXTH_FIELD                     (_MK_MASK_CONST(0xff) << MC_BWSHARE_ISP_0_ISP_BW_MAXTH_SHIFT)
+#define MC_BWSHARE_ISP_0_ISP_BW_MAXTH_RANGE                     26:19
+#define MC_BWSHARE_ISP_0_ISP_BW_MAXTH_WOFFSET                   0x0
+#define MC_BWSHARE_ISP_0_ISP_BW_MAXTH_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_ISP_0_ISP_BW_MAXTH_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_ISP_0_ISP_BW_MAXTH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_ISP_0_ISP_BW_MAXTH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_ISP_0_ISP_BW_ALWAYSINC_SHIFT                 _MK_SHIFT_CONST(27)
+#define MC_BWSHARE_ISP_0_ISP_BW_ALWAYSINC_FIELD                 (_MK_MASK_CONST(0x1) << MC_BWSHARE_ISP_0_ISP_BW_ALWAYSINC_SHIFT)
+#define MC_BWSHARE_ISP_0_ISP_BW_ALWAYSINC_RANGE                 27:27
+#define MC_BWSHARE_ISP_0_ISP_BW_ALWAYSINC_WOFFSET                       0x0
+#define MC_BWSHARE_ISP_0_ISP_BW_ALWAYSINC_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_ISP_0_ISP_BW_ALWAYSINC_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_ISP_0_ISP_BW_ALWAYSINC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_ISP_0_ISP_BW_ALWAYSINC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_ISP_0_ISP_BW_ALWAYSINC_INIT_ENUM                     DISABLE
+#define MC_BWSHARE_ISP_0_ISP_BW_ALWAYSINC_DISABLE                       _MK_ENUM_CONST(0)
+#define MC_BWSHARE_ISP_0_ISP_BW_ALWAYSINC_ENABLE                        _MK_ENUM_CONST(1)
+#define MC_BWSHARE_ISP_0_ISP_BW_ALWAYSINC_DISABLED                      _MK_ENUM_CONST(0)
+#define MC_BWSHARE_ISP_0_ISP_BW_ALWAYSINC_ENABLED                       _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_ISP_0_ISP_BW_TMSFACTORSEL_SHIFT                      _MK_SHIFT_CONST(28)
+#define MC_BWSHARE_ISP_0_ISP_BW_TMSFACTORSEL_FIELD                      (_MK_MASK_CONST(0x1) << MC_BWSHARE_ISP_0_ISP_BW_TMSFACTORSEL_SHIFT)
+#define MC_BWSHARE_ISP_0_ISP_BW_TMSFACTORSEL_RANGE                      28:28
+#define MC_BWSHARE_ISP_0_ISP_BW_TMSFACTORSEL_WOFFSET                    0x0
+#define MC_BWSHARE_ISP_0_ISP_BW_TMSFACTORSEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_ISP_0_ISP_BW_TMSFACTORSEL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_ISP_0_ISP_BW_TMSFACTORSEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_ISP_0_ISP_BW_TMSFACTORSEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_ISP_0_ISP_BW_TMSFACTORSEL_INIT_ENUM                  TM_SFACTOR1
+#define MC_BWSHARE_ISP_0_ISP_BW_TMSFACTORSEL_TM_SFACTOR1                        _MK_ENUM_CONST(0)
+#define MC_BWSHARE_ISP_0_ISP_BW_TMSFACTORSEL_TM_SFACTOR2                        _MK_ENUM_CONST(1)
+
+
+// Register MC_BWSHARE_MPCORE_0  
+#define MC_BWSHARE_MPCORE_0                     _MK_ADDR_CONST(0x254)
+#define MC_BWSHARE_MPCORE_0_SECURE                      0x0
+#define MC_BWSHARE_MPCORE_0_WORD_COUNT                  0x1
+#define MC_BWSHARE_MPCORE_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPCORE_0_RESET_MASK                  _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_MPCORE_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPCORE_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPCORE_0_READ_MASK                   _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_MPCORE_0_WRITE_MASK                  _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_INCVAL_SHIFT                      _MK_SHIFT_CONST(0)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_INCVAL_FIELD                      (_MK_MASK_CONST(0x7ff) << MC_BWSHARE_MPCORE_0_MPCORE_BW_INCVAL_SHIFT)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_INCVAL_RANGE                      10:0
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_INCVAL_WOFFSET                    0x0
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_INCVAL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_INCVAL_DEFAULT_MASK                       _MK_MASK_CONST(0x7ff)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_INCVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_INCVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_HIGHTH_SHIFT                      _MK_SHIFT_CONST(11)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_HIGHTH_FIELD                      (_MK_MASK_CONST(0xff) << MC_BWSHARE_MPCORE_0_MPCORE_BW_HIGHTH_SHIFT)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_HIGHTH_RANGE                      18:11
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_HIGHTH_WOFFSET                    0x0
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_HIGHTH_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_HIGHTH_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_HIGHTH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_HIGHTH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_MAXTH_SHIFT                       _MK_SHIFT_CONST(19)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_MAXTH_FIELD                       (_MK_MASK_CONST(0xff) << MC_BWSHARE_MPCORE_0_MPCORE_BW_MAXTH_SHIFT)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_MAXTH_RANGE                       26:19
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_MAXTH_WOFFSET                     0x0
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_MAXTH_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_MAXTH_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_MAXTH_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_MAXTH_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_ALWAYSINC_SHIFT                   _MK_SHIFT_CONST(27)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_ALWAYSINC_FIELD                   (_MK_MASK_CONST(0x1) << MC_BWSHARE_MPCORE_0_MPCORE_BW_ALWAYSINC_SHIFT)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_ALWAYSINC_RANGE                   27:27
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_ALWAYSINC_WOFFSET                 0x0
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_ALWAYSINC_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_ALWAYSINC_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_ALWAYSINC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_ALWAYSINC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_ALWAYSINC_INIT_ENUM                       DISABLE
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_ALWAYSINC_DISABLE                 _MK_ENUM_CONST(0)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_ALWAYSINC_ENABLE                  _MK_ENUM_CONST(1)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_ALWAYSINC_DISABLED                        _MK_ENUM_CONST(0)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_ALWAYSINC_ENABLED                 _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_TMSFACTORSEL_SHIFT                        _MK_SHIFT_CONST(28)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_TMSFACTORSEL_FIELD                        (_MK_MASK_CONST(0x1) << MC_BWSHARE_MPCORE_0_MPCORE_BW_TMSFACTORSEL_SHIFT)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_TMSFACTORSEL_RANGE                        28:28
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_TMSFACTORSEL_WOFFSET                      0x0
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_TMSFACTORSEL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_TMSFACTORSEL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_TMSFACTORSEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_TMSFACTORSEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_TMSFACTORSEL_INIT_ENUM                    TM_SFACTOR1
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_TMSFACTORSEL_TM_SFACTOR1                  _MK_ENUM_CONST(0)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_TMSFACTORSEL_TM_SFACTOR2                  _MK_ENUM_CONST(1)
+
+
+// Register MC_BWSHARE_MPEA_0  
+#define MC_BWSHARE_MPEA_0                       _MK_ADDR_CONST(0x258)
+#define MC_BWSHARE_MPEA_0_SECURE                        0x0
+#define MC_BWSHARE_MPEA_0_WORD_COUNT                    0x1
+#define MC_BWSHARE_MPEA_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEA_0_RESET_MASK                    _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_MPEA_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEA_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEA_0_READ_MASK                     _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_MPEA_0_WRITE_MASK                    _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_INCVAL_SHIFT                  _MK_SHIFT_CONST(0)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_INCVAL_FIELD                  (_MK_MASK_CONST(0x7ff) << MC_BWSHARE_MPEA_0_MPEA_BW_INCVAL_SHIFT)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_INCVAL_RANGE                  10:0
+#define MC_BWSHARE_MPEA_0_MPEA_BW_INCVAL_WOFFSET                        0x0
+#define MC_BWSHARE_MPEA_0_MPEA_BW_INCVAL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_INCVAL_DEFAULT_MASK                   _MK_MASK_CONST(0x7ff)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_INCVAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_INCVAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_MPEA_0_MPEA_BW_HIGHTH_SHIFT                  _MK_SHIFT_CONST(11)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_HIGHTH_FIELD                  (_MK_MASK_CONST(0xff) << MC_BWSHARE_MPEA_0_MPEA_BW_HIGHTH_SHIFT)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_HIGHTH_RANGE                  18:11
+#define MC_BWSHARE_MPEA_0_MPEA_BW_HIGHTH_WOFFSET                        0x0
+#define MC_BWSHARE_MPEA_0_MPEA_BW_HIGHTH_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_HIGHTH_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_HIGHTH_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_HIGHTH_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_MPEA_0_MPEA_BW_MAXTH_SHIFT                   _MK_SHIFT_CONST(19)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_MAXTH_FIELD                   (_MK_MASK_CONST(0xff) << MC_BWSHARE_MPEA_0_MPEA_BW_MAXTH_SHIFT)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_MAXTH_RANGE                   26:19
+#define MC_BWSHARE_MPEA_0_MPEA_BW_MAXTH_WOFFSET                 0x0
+#define MC_BWSHARE_MPEA_0_MPEA_BW_MAXTH_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_MAXTH_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_MAXTH_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_MAXTH_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_MPEA_0_MPEA_BW_ALWAYSINC_SHIFT                       _MK_SHIFT_CONST(27)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_ALWAYSINC_FIELD                       (_MK_MASK_CONST(0x1) << MC_BWSHARE_MPEA_0_MPEA_BW_ALWAYSINC_SHIFT)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_ALWAYSINC_RANGE                       27:27
+#define MC_BWSHARE_MPEA_0_MPEA_BW_ALWAYSINC_WOFFSET                     0x0
+#define MC_BWSHARE_MPEA_0_MPEA_BW_ALWAYSINC_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_ALWAYSINC_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_ALWAYSINC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_ALWAYSINC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_ALWAYSINC_INIT_ENUM                   DISABLE
+#define MC_BWSHARE_MPEA_0_MPEA_BW_ALWAYSINC_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_ALWAYSINC_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_ALWAYSINC_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_ALWAYSINC_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_MPEA_0_MPEA_BW_TMSFACTORSEL_SHIFT                    _MK_SHIFT_CONST(28)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_TMSFACTORSEL_FIELD                    (_MK_MASK_CONST(0x1) << MC_BWSHARE_MPEA_0_MPEA_BW_TMSFACTORSEL_SHIFT)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_TMSFACTORSEL_RANGE                    28:28
+#define MC_BWSHARE_MPEA_0_MPEA_BW_TMSFACTORSEL_WOFFSET                  0x0
+#define MC_BWSHARE_MPEA_0_MPEA_BW_TMSFACTORSEL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_TMSFACTORSEL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_TMSFACTORSEL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_TMSFACTORSEL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_TMSFACTORSEL_INIT_ENUM                        TM_SFACTOR1
+#define MC_BWSHARE_MPEA_0_MPEA_BW_TMSFACTORSEL_TM_SFACTOR1                      _MK_ENUM_CONST(0)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_TMSFACTORSEL_TM_SFACTOR2                      _MK_ENUM_CONST(1)
+
+
+// Register MC_BWSHARE_MPEB_0  
+#define MC_BWSHARE_MPEB_0                       _MK_ADDR_CONST(0x25c)
+#define MC_BWSHARE_MPEB_0_SECURE                        0x0
+#define MC_BWSHARE_MPEB_0_WORD_COUNT                    0x1
+#define MC_BWSHARE_MPEB_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEB_0_RESET_MASK                    _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_MPEB_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEB_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEB_0_READ_MASK                     _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_MPEB_0_WRITE_MASK                    _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_INCVAL_SHIFT                  _MK_SHIFT_CONST(0)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_INCVAL_FIELD                  (_MK_MASK_CONST(0x7ff) << MC_BWSHARE_MPEB_0_MPEB_BW_INCVAL_SHIFT)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_INCVAL_RANGE                  10:0
+#define MC_BWSHARE_MPEB_0_MPEB_BW_INCVAL_WOFFSET                        0x0
+#define MC_BWSHARE_MPEB_0_MPEB_BW_INCVAL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_INCVAL_DEFAULT_MASK                   _MK_MASK_CONST(0x7ff)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_INCVAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_INCVAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_MPEB_0_MPEB_BW_HIGHTH_SHIFT                  _MK_SHIFT_CONST(11)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_HIGHTH_FIELD                  (_MK_MASK_CONST(0xff) << MC_BWSHARE_MPEB_0_MPEB_BW_HIGHTH_SHIFT)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_HIGHTH_RANGE                  18:11
+#define MC_BWSHARE_MPEB_0_MPEB_BW_HIGHTH_WOFFSET                        0x0
+#define MC_BWSHARE_MPEB_0_MPEB_BW_HIGHTH_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_HIGHTH_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_HIGHTH_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_HIGHTH_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_MPEB_0_MPEB_BW_MAXTH_SHIFT                   _MK_SHIFT_CONST(19)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_MAXTH_FIELD                   (_MK_MASK_CONST(0xff) << MC_BWSHARE_MPEB_0_MPEB_BW_MAXTH_SHIFT)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_MAXTH_RANGE                   26:19
+#define MC_BWSHARE_MPEB_0_MPEB_BW_MAXTH_WOFFSET                 0x0
+#define MC_BWSHARE_MPEB_0_MPEB_BW_MAXTH_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_MAXTH_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_MAXTH_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_MAXTH_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_MPEB_0_MPEB_BW_ALWAYSINC_SHIFT                       _MK_SHIFT_CONST(27)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_ALWAYSINC_FIELD                       (_MK_MASK_CONST(0x1) << MC_BWSHARE_MPEB_0_MPEB_BW_ALWAYSINC_SHIFT)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_ALWAYSINC_RANGE                       27:27
+#define MC_BWSHARE_MPEB_0_MPEB_BW_ALWAYSINC_WOFFSET                     0x0
+#define MC_BWSHARE_MPEB_0_MPEB_BW_ALWAYSINC_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_ALWAYSINC_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_ALWAYSINC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_ALWAYSINC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_ALWAYSINC_INIT_ENUM                   DISABLE
+#define MC_BWSHARE_MPEB_0_MPEB_BW_ALWAYSINC_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_ALWAYSINC_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_ALWAYSINC_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_ALWAYSINC_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_MPEB_0_MPEB_BW_TMSFACTORSEL_SHIFT                    _MK_SHIFT_CONST(28)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_TMSFACTORSEL_FIELD                    (_MK_MASK_CONST(0x1) << MC_BWSHARE_MPEB_0_MPEB_BW_TMSFACTORSEL_SHIFT)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_TMSFACTORSEL_RANGE                    28:28
+#define MC_BWSHARE_MPEB_0_MPEB_BW_TMSFACTORSEL_WOFFSET                  0x0
+#define MC_BWSHARE_MPEB_0_MPEB_BW_TMSFACTORSEL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_TMSFACTORSEL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_TMSFACTORSEL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_TMSFACTORSEL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_TMSFACTORSEL_INIT_ENUM                        TM_SFACTOR1
+#define MC_BWSHARE_MPEB_0_MPEB_BW_TMSFACTORSEL_TM_SFACTOR1                      _MK_ENUM_CONST(0)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_TMSFACTORSEL_TM_SFACTOR2                      _MK_ENUM_CONST(1)
+
+
+// Register MC_BWSHARE_MPEC_0  
+#define MC_BWSHARE_MPEC_0                       _MK_ADDR_CONST(0x260)
+#define MC_BWSHARE_MPEC_0_SECURE                        0x0
+#define MC_BWSHARE_MPEC_0_WORD_COUNT                    0x1
+#define MC_BWSHARE_MPEC_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEC_0_RESET_MASK                    _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_MPEC_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEC_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEC_0_READ_MASK                     _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_MPEC_0_WRITE_MASK                    _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_INCVAL_SHIFT                  _MK_SHIFT_CONST(0)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_INCVAL_FIELD                  (_MK_MASK_CONST(0x7ff) << MC_BWSHARE_MPEC_0_MPEC_BW_INCVAL_SHIFT)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_INCVAL_RANGE                  10:0
+#define MC_BWSHARE_MPEC_0_MPEC_BW_INCVAL_WOFFSET                        0x0
+#define MC_BWSHARE_MPEC_0_MPEC_BW_INCVAL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_INCVAL_DEFAULT_MASK                   _MK_MASK_CONST(0x7ff)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_INCVAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_INCVAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_MPEC_0_MPEC_BW_HIGHTH_SHIFT                  _MK_SHIFT_CONST(11)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_HIGHTH_FIELD                  (_MK_MASK_CONST(0xff) << MC_BWSHARE_MPEC_0_MPEC_BW_HIGHTH_SHIFT)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_HIGHTH_RANGE                  18:11
+#define MC_BWSHARE_MPEC_0_MPEC_BW_HIGHTH_WOFFSET                        0x0
+#define MC_BWSHARE_MPEC_0_MPEC_BW_HIGHTH_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_HIGHTH_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_HIGHTH_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_HIGHTH_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_MPEC_0_MPEC_BW_MAXTH_SHIFT                   _MK_SHIFT_CONST(19)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_MAXTH_FIELD                   (_MK_MASK_CONST(0xff) << MC_BWSHARE_MPEC_0_MPEC_BW_MAXTH_SHIFT)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_MAXTH_RANGE                   26:19
+#define MC_BWSHARE_MPEC_0_MPEC_BW_MAXTH_WOFFSET                 0x0
+#define MC_BWSHARE_MPEC_0_MPEC_BW_MAXTH_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_MAXTH_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_MAXTH_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_MAXTH_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_MPEC_0_MPEC_BW_ALWAYSINC_SHIFT                       _MK_SHIFT_CONST(27)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_ALWAYSINC_FIELD                       (_MK_MASK_CONST(0x1) << MC_BWSHARE_MPEC_0_MPEC_BW_ALWAYSINC_SHIFT)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_ALWAYSINC_RANGE                       27:27
+#define MC_BWSHARE_MPEC_0_MPEC_BW_ALWAYSINC_WOFFSET                     0x0
+#define MC_BWSHARE_MPEC_0_MPEC_BW_ALWAYSINC_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_ALWAYSINC_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_ALWAYSINC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_ALWAYSINC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_ALWAYSINC_INIT_ENUM                   DISABLE
+#define MC_BWSHARE_MPEC_0_MPEC_BW_ALWAYSINC_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_ALWAYSINC_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_ALWAYSINC_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_ALWAYSINC_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_MPEC_0_MPEC_BW_TMSFACTORSEL_SHIFT                    _MK_SHIFT_CONST(28)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_TMSFACTORSEL_FIELD                    (_MK_MASK_CONST(0x1) << MC_BWSHARE_MPEC_0_MPEC_BW_TMSFACTORSEL_SHIFT)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_TMSFACTORSEL_RANGE                    28:28
+#define MC_BWSHARE_MPEC_0_MPEC_BW_TMSFACTORSEL_WOFFSET                  0x0
+#define MC_BWSHARE_MPEC_0_MPEC_BW_TMSFACTORSEL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_TMSFACTORSEL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_TMSFACTORSEL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_TMSFACTORSEL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_TMSFACTORSEL_INIT_ENUM                        TM_SFACTOR1
+#define MC_BWSHARE_MPEC_0_MPEC_BW_TMSFACTORSEL_TM_SFACTOR1                      _MK_ENUM_CONST(0)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_TMSFACTORSEL_TM_SFACTOR2                      _MK_ENUM_CONST(1)
+
+
+// Register MC_BWSHARE_NV_0  
+#define MC_BWSHARE_NV_0                 _MK_ADDR_CONST(0x264)
+#define MC_BWSHARE_NV_0_SECURE                  0x0
+#define MC_BWSHARE_NV_0_WORD_COUNT                      0x1
+#define MC_BWSHARE_NV_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_NV_0_RESET_MASK                      _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_NV_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_NV_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_NV_0_READ_MASK                       _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_NV_0_WRITE_MASK                      _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_NV_0_NV_BW_INCVAL_SHIFT                      _MK_SHIFT_CONST(0)
+#define MC_BWSHARE_NV_0_NV_BW_INCVAL_FIELD                      (_MK_MASK_CONST(0x7ff) << MC_BWSHARE_NV_0_NV_BW_INCVAL_SHIFT)
+#define MC_BWSHARE_NV_0_NV_BW_INCVAL_RANGE                      10:0
+#define MC_BWSHARE_NV_0_NV_BW_INCVAL_WOFFSET                    0x0
+#define MC_BWSHARE_NV_0_NV_BW_INCVAL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_NV_0_NV_BW_INCVAL_DEFAULT_MASK                       _MK_MASK_CONST(0x7ff)
+#define MC_BWSHARE_NV_0_NV_BW_INCVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_NV_0_NV_BW_INCVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_NV_0_NV_BW_HIGHTH_SHIFT                      _MK_SHIFT_CONST(11)
+#define MC_BWSHARE_NV_0_NV_BW_HIGHTH_FIELD                      (_MK_MASK_CONST(0xff) << MC_BWSHARE_NV_0_NV_BW_HIGHTH_SHIFT)
+#define MC_BWSHARE_NV_0_NV_BW_HIGHTH_RANGE                      18:11
+#define MC_BWSHARE_NV_0_NV_BW_HIGHTH_WOFFSET                    0x0
+#define MC_BWSHARE_NV_0_NV_BW_HIGHTH_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_NV_0_NV_BW_HIGHTH_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_NV_0_NV_BW_HIGHTH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_NV_0_NV_BW_HIGHTH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_NV_0_NV_BW_MAXTH_SHIFT                       _MK_SHIFT_CONST(19)
+#define MC_BWSHARE_NV_0_NV_BW_MAXTH_FIELD                       (_MK_MASK_CONST(0xff) << MC_BWSHARE_NV_0_NV_BW_MAXTH_SHIFT)
+#define MC_BWSHARE_NV_0_NV_BW_MAXTH_RANGE                       26:19
+#define MC_BWSHARE_NV_0_NV_BW_MAXTH_WOFFSET                     0x0
+#define MC_BWSHARE_NV_0_NV_BW_MAXTH_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_NV_0_NV_BW_MAXTH_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_NV_0_NV_BW_MAXTH_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_NV_0_NV_BW_MAXTH_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_NV_0_NV_BW_ALWAYSINC_SHIFT                   _MK_SHIFT_CONST(27)
+#define MC_BWSHARE_NV_0_NV_BW_ALWAYSINC_FIELD                   (_MK_MASK_CONST(0x1) << MC_BWSHARE_NV_0_NV_BW_ALWAYSINC_SHIFT)
+#define MC_BWSHARE_NV_0_NV_BW_ALWAYSINC_RANGE                   27:27
+#define MC_BWSHARE_NV_0_NV_BW_ALWAYSINC_WOFFSET                 0x0
+#define MC_BWSHARE_NV_0_NV_BW_ALWAYSINC_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_NV_0_NV_BW_ALWAYSINC_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_NV_0_NV_BW_ALWAYSINC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_NV_0_NV_BW_ALWAYSINC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_NV_0_NV_BW_ALWAYSINC_INIT_ENUM                       DISABLE
+#define MC_BWSHARE_NV_0_NV_BW_ALWAYSINC_DISABLE                 _MK_ENUM_CONST(0)
+#define MC_BWSHARE_NV_0_NV_BW_ALWAYSINC_ENABLE                  _MK_ENUM_CONST(1)
+#define MC_BWSHARE_NV_0_NV_BW_ALWAYSINC_DISABLED                        _MK_ENUM_CONST(0)
+#define MC_BWSHARE_NV_0_NV_BW_ALWAYSINC_ENABLED                 _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_NV_0_NV_BW_TMSFACTORSEL_SHIFT                        _MK_SHIFT_CONST(28)
+#define MC_BWSHARE_NV_0_NV_BW_TMSFACTORSEL_FIELD                        (_MK_MASK_CONST(0x1) << MC_BWSHARE_NV_0_NV_BW_TMSFACTORSEL_SHIFT)
+#define MC_BWSHARE_NV_0_NV_BW_TMSFACTORSEL_RANGE                        28:28
+#define MC_BWSHARE_NV_0_NV_BW_TMSFACTORSEL_WOFFSET                      0x0
+#define MC_BWSHARE_NV_0_NV_BW_TMSFACTORSEL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_NV_0_NV_BW_TMSFACTORSEL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_NV_0_NV_BW_TMSFACTORSEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_NV_0_NV_BW_TMSFACTORSEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_NV_0_NV_BW_TMSFACTORSEL_INIT_ENUM                    TM_SFACTOR1
+#define MC_BWSHARE_NV_0_NV_BW_TMSFACTORSEL_TM_SFACTOR1                  _MK_ENUM_CONST(0)
+#define MC_BWSHARE_NV_0_NV_BW_TMSFACTORSEL_TM_SFACTOR2                  _MK_ENUM_CONST(1)
+
+
+// Register MC_BWSHARE_PPCS_0  
+#define MC_BWSHARE_PPCS_0                       _MK_ADDR_CONST(0x268)
+#define MC_BWSHARE_PPCS_0_SECURE                        0x0
+#define MC_BWSHARE_PPCS_0_WORD_COUNT                    0x1
+#define MC_BWSHARE_PPCS_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_PPCS_0_RESET_MASK                    _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_PPCS_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_PPCS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_PPCS_0_READ_MASK                     _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_PPCS_0_WRITE_MASK                    _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_INCVAL_SHIFT                  _MK_SHIFT_CONST(0)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_INCVAL_FIELD                  (_MK_MASK_CONST(0x7ff) << MC_BWSHARE_PPCS_0_PPCS_BW_INCVAL_SHIFT)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_INCVAL_RANGE                  10:0
+#define MC_BWSHARE_PPCS_0_PPCS_BW_INCVAL_WOFFSET                        0x0
+#define MC_BWSHARE_PPCS_0_PPCS_BW_INCVAL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_INCVAL_DEFAULT_MASK                   _MK_MASK_CONST(0x7ff)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_INCVAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_INCVAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_PPCS_0_PPCS_BW_HIGHTH_SHIFT                  _MK_SHIFT_CONST(11)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_HIGHTH_FIELD                  (_MK_MASK_CONST(0xff) << MC_BWSHARE_PPCS_0_PPCS_BW_HIGHTH_SHIFT)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_HIGHTH_RANGE                  18:11
+#define MC_BWSHARE_PPCS_0_PPCS_BW_HIGHTH_WOFFSET                        0x0
+#define MC_BWSHARE_PPCS_0_PPCS_BW_HIGHTH_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_HIGHTH_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_HIGHTH_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_HIGHTH_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_PPCS_0_PPCS_BW_MAXTH_SHIFT                   _MK_SHIFT_CONST(19)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_MAXTH_FIELD                   (_MK_MASK_CONST(0xff) << MC_BWSHARE_PPCS_0_PPCS_BW_MAXTH_SHIFT)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_MAXTH_RANGE                   26:19
+#define MC_BWSHARE_PPCS_0_PPCS_BW_MAXTH_WOFFSET                 0x0
+#define MC_BWSHARE_PPCS_0_PPCS_BW_MAXTH_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_MAXTH_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_MAXTH_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_MAXTH_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_PPCS_0_PPCS_BW_ALWAYSINC_SHIFT                       _MK_SHIFT_CONST(27)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_ALWAYSINC_FIELD                       (_MK_MASK_CONST(0x1) << MC_BWSHARE_PPCS_0_PPCS_BW_ALWAYSINC_SHIFT)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_ALWAYSINC_RANGE                       27:27
+#define MC_BWSHARE_PPCS_0_PPCS_BW_ALWAYSINC_WOFFSET                     0x0
+#define MC_BWSHARE_PPCS_0_PPCS_BW_ALWAYSINC_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_ALWAYSINC_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_ALWAYSINC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_ALWAYSINC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_ALWAYSINC_INIT_ENUM                   DISABLE
+#define MC_BWSHARE_PPCS_0_PPCS_BW_ALWAYSINC_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_ALWAYSINC_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_ALWAYSINC_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_ALWAYSINC_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_PPCS_0_PPCS_BW_TMSFACTORSEL_SHIFT                    _MK_SHIFT_CONST(28)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_TMSFACTORSEL_FIELD                    (_MK_MASK_CONST(0x1) << MC_BWSHARE_PPCS_0_PPCS_BW_TMSFACTORSEL_SHIFT)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_TMSFACTORSEL_RANGE                    28:28
+#define MC_BWSHARE_PPCS_0_PPCS_BW_TMSFACTORSEL_WOFFSET                  0x0
+#define MC_BWSHARE_PPCS_0_PPCS_BW_TMSFACTORSEL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_TMSFACTORSEL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_TMSFACTORSEL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_TMSFACTORSEL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_TMSFACTORSEL_INIT_ENUM                        TM_SFACTOR1
+#define MC_BWSHARE_PPCS_0_PPCS_BW_TMSFACTORSEL_TM_SFACTOR1                      _MK_ENUM_CONST(0)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_TMSFACTORSEL_TM_SFACTOR2                      _MK_ENUM_CONST(1)
+
+
+// Register MC_BWSHARE_VDE_0  
+#define MC_BWSHARE_VDE_0                        _MK_ADDR_CONST(0x26c)
+#define MC_BWSHARE_VDE_0_SECURE                         0x0
+#define MC_BWSHARE_VDE_0_WORD_COUNT                     0x1
+#define MC_BWSHARE_VDE_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_VDE_0_RESET_MASK                     _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_VDE_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_VDE_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_VDE_0_READ_MASK                      _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_VDE_0_WRITE_MASK                     _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_VDE_0_VDE_BW_INCVAL_SHIFT                    _MK_SHIFT_CONST(0)
+#define MC_BWSHARE_VDE_0_VDE_BW_INCVAL_FIELD                    (_MK_MASK_CONST(0x7ff) << MC_BWSHARE_VDE_0_VDE_BW_INCVAL_SHIFT)
+#define MC_BWSHARE_VDE_0_VDE_BW_INCVAL_RANGE                    10:0
+#define MC_BWSHARE_VDE_0_VDE_BW_INCVAL_WOFFSET                  0x0
+#define MC_BWSHARE_VDE_0_VDE_BW_INCVAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_VDE_0_VDE_BW_INCVAL_DEFAULT_MASK                     _MK_MASK_CONST(0x7ff)
+#define MC_BWSHARE_VDE_0_VDE_BW_INCVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_VDE_0_VDE_BW_INCVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_VDE_0_VDE_BW_HIGHTH_SHIFT                    _MK_SHIFT_CONST(11)
+#define MC_BWSHARE_VDE_0_VDE_BW_HIGHTH_FIELD                    (_MK_MASK_CONST(0xff) << MC_BWSHARE_VDE_0_VDE_BW_HIGHTH_SHIFT)
+#define MC_BWSHARE_VDE_0_VDE_BW_HIGHTH_RANGE                    18:11
+#define MC_BWSHARE_VDE_0_VDE_BW_HIGHTH_WOFFSET                  0x0
+#define MC_BWSHARE_VDE_0_VDE_BW_HIGHTH_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_VDE_0_VDE_BW_HIGHTH_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_VDE_0_VDE_BW_HIGHTH_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_VDE_0_VDE_BW_HIGHTH_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_VDE_0_VDE_BW_MAXTH_SHIFT                     _MK_SHIFT_CONST(19)
+#define MC_BWSHARE_VDE_0_VDE_BW_MAXTH_FIELD                     (_MK_MASK_CONST(0xff) << MC_BWSHARE_VDE_0_VDE_BW_MAXTH_SHIFT)
+#define MC_BWSHARE_VDE_0_VDE_BW_MAXTH_RANGE                     26:19
+#define MC_BWSHARE_VDE_0_VDE_BW_MAXTH_WOFFSET                   0x0
+#define MC_BWSHARE_VDE_0_VDE_BW_MAXTH_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_VDE_0_VDE_BW_MAXTH_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_VDE_0_VDE_BW_MAXTH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_VDE_0_VDE_BW_MAXTH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_VDE_0_VDE_BW_ALWAYSINC_SHIFT                 _MK_SHIFT_CONST(27)
+#define MC_BWSHARE_VDE_0_VDE_BW_ALWAYSINC_FIELD                 (_MK_MASK_CONST(0x1) << MC_BWSHARE_VDE_0_VDE_BW_ALWAYSINC_SHIFT)
+#define MC_BWSHARE_VDE_0_VDE_BW_ALWAYSINC_RANGE                 27:27
+#define MC_BWSHARE_VDE_0_VDE_BW_ALWAYSINC_WOFFSET                       0x0
+#define MC_BWSHARE_VDE_0_VDE_BW_ALWAYSINC_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_VDE_0_VDE_BW_ALWAYSINC_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_VDE_0_VDE_BW_ALWAYSINC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_VDE_0_VDE_BW_ALWAYSINC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_VDE_0_VDE_BW_ALWAYSINC_INIT_ENUM                     DISABLE
+#define MC_BWSHARE_VDE_0_VDE_BW_ALWAYSINC_DISABLE                       _MK_ENUM_CONST(0)
+#define MC_BWSHARE_VDE_0_VDE_BW_ALWAYSINC_ENABLE                        _MK_ENUM_CONST(1)
+#define MC_BWSHARE_VDE_0_VDE_BW_ALWAYSINC_DISABLED                      _MK_ENUM_CONST(0)
+#define MC_BWSHARE_VDE_0_VDE_BW_ALWAYSINC_ENABLED                       _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_VDE_0_VDE_BW_TMSFACTORSEL_SHIFT                      _MK_SHIFT_CONST(28)
+#define MC_BWSHARE_VDE_0_VDE_BW_TMSFACTORSEL_FIELD                      (_MK_MASK_CONST(0x1) << MC_BWSHARE_VDE_0_VDE_BW_TMSFACTORSEL_SHIFT)
+#define MC_BWSHARE_VDE_0_VDE_BW_TMSFACTORSEL_RANGE                      28:28
+#define MC_BWSHARE_VDE_0_VDE_BW_TMSFACTORSEL_WOFFSET                    0x0
+#define MC_BWSHARE_VDE_0_VDE_BW_TMSFACTORSEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_VDE_0_VDE_BW_TMSFACTORSEL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_VDE_0_VDE_BW_TMSFACTORSEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_VDE_0_VDE_BW_TMSFACTORSEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_VDE_0_VDE_BW_TMSFACTORSEL_INIT_ENUM                  TM_SFACTOR1
+#define MC_BWSHARE_VDE_0_VDE_BW_TMSFACTORSEL_TM_SFACTOR1                        _MK_ENUM_CONST(0)
+#define MC_BWSHARE_VDE_0_VDE_BW_TMSFACTORSEL_TM_SFACTOR2                        _MK_ENUM_CONST(1)
+
+
+// Register MC_BWSHARE_VI_0  
+#define MC_BWSHARE_VI_0                 _MK_ADDR_CONST(0x270)
+#define MC_BWSHARE_VI_0_SECURE                  0x0
+#define MC_BWSHARE_VI_0_WORD_COUNT                      0x1
+#define MC_BWSHARE_VI_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_VI_0_RESET_MASK                      _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_VI_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_VI_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_VI_0_READ_MASK                       _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_VI_0_WRITE_MASK                      _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_VI_0_VI_BW_INCVAL_SHIFT                      _MK_SHIFT_CONST(0)
+#define MC_BWSHARE_VI_0_VI_BW_INCVAL_FIELD                      (_MK_MASK_CONST(0x7ff) << MC_BWSHARE_VI_0_VI_BW_INCVAL_SHIFT)
+#define MC_BWSHARE_VI_0_VI_BW_INCVAL_RANGE                      10:0
+#define MC_BWSHARE_VI_0_VI_BW_INCVAL_WOFFSET                    0x0
+#define MC_BWSHARE_VI_0_VI_BW_INCVAL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_VI_0_VI_BW_INCVAL_DEFAULT_MASK                       _MK_MASK_CONST(0x7ff)
+#define MC_BWSHARE_VI_0_VI_BW_INCVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_VI_0_VI_BW_INCVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_VI_0_VI_BW_HIGHTH_SHIFT                      _MK_SHIFT_CONST(11)
+#define MC_BWSHARE_VI_0_VI_BW_HIGHTH_FIELD                      (_MK_MASK_CONST(0xff) << MC_BWSHARE_VI_0_VI_BW_HIGHTH_SHIFT)
+#define MC_BWSHARE_VI_0_VI_BW_HIGHTH_RANGE                      18:11
+#define MC_BWSHARE_VI_0_VI_BW_HIGHTH_WOFFSET                    0x0
+#define MC_BWSHARE_VI_0_VI_BW_HIGHTH_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_VI_0_VI_BW_HIGHTH_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_VI_0_VI_BW_HIGHTH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_VI_0_VI_BW_HIGHTH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_VI_0_VI_BW_MAXTH_SHIFT                       _MK_SHIFT_CONST(19)
+#define MC_BWSHARE_VI_0_VI_BW_MAXTH_FIELD                       (_MK_MASK_CONST(0xff) << MC_BWSHARE_VI_0_VI_BW_MAXTH_SHIFT)
+#define MC_BWSHARE_VI_0_VI_BW_MAXTH_RANGE                       26:19
+#define MC_BWSHARE_VI_0_VI_BW_MAXTH_WOFFSET                     0x0
+#define MC_BWSHARE_VI_0_VI_BW_MAXTH_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_VI_0_VI_BW_MAXTH_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_VI_0_VI_BW_MAXTH_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_VI_0_VI_BW_MAXTH_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_VI_0_VI_BW_ALWAYSINC_SHIFT                   _MK_SHIFT_CONST(27)
+#define MC_BWSHARE_VI_0_VI_BW_ALWAYSINC_FIELD                   (_MK_MASK_CONST(0x1) << MC_BWSHARE_VI_0_VI_BW_ALWAYSINC_SHIFT)
+#define MC_BWSHARE_VI_0_VI_BW_ALWAYSINC_RANGE                   27:27
+#define MC_BWSHARE_VI_0_VI_BW_ALWAYSINC_WOFFSET                 0x0
+#define MC_BWSHARE_VI_0_VI_BW_ALWAYSINC_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_VI_0_VI_BW_ALWAYSINC_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_VI_0_VI_BW_ALWAYSINC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_VI_0_VI_BW_ALWAYSINC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_VI_0_VI_BW_ALWAYSINC_INIT_ENUM                       DISABLE
+#define MC_BWSHARE_VI_0_VI_BW_ALWAYSINC_DISABLE                 _MK_ENUM_CONST(0)
+#define MC_BWSHARE_VI_0_VI_BW_ALWAYSINC_ENABLE                  _MK_ENUM_CONST(1)
+#define MC_BWSHARE_VI_0_VI_BW_ALWAYSINC_DISABLED                        _MK_ENUM_CONST(0)
+#define MC_BWSHARE_VI_0_VI_BW_ALWAYSINC_ENABLED                 _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_VI_0_VI_BW_TMSFACTORSEL_SHIFT                        _MK_SHIFT_CONST(28)
+#define MC_BWSHARE_VI_0_VI_BW_TMSFACTORSEL_FIELD                        (_MK_MASK_CONST(0x1) << MC_BWSHARE_VI_0_VI_BW_TMSFACTORSEL_SHIFT)
+#define MC_BWSHARE_VI_0_VI_BW_TMSFACTORSEL_RANGE                        28:28
+#define MC_BWSHARE_VI_0_VI_BW_TMSFACTORSEL_WOFFSET                      0x0
+#define MC_BWSHARE_VI_0_VI_BW_TMSFACTORSEL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_VI_0_VI_BW_TMSFACTORSEL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_VI_0_VI_BW_TMSFACTORSEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_VI_0_VI_BW_TMSFACTORSEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_VI_0_VI_BW_TMSFACTORSEL_INIT_ENUM                    TM_SFACTOR1
+#define MC_BWSHARE_VI_0_VI_BW_TMSFACTORSEL_TM_SFACTOR1                  _MK_ENUM_CONST(0)
+#define MC_BWSHARE_VI_0_VI_BW_TMSFACTORSEL_TM_SFACTOR2                  _MK_ENUM_CONST(1)
+
+#define NV_MC_EMEM_DFIFO_DEPTH  4
+#define NV_MC_IMEM_DFIFO_DEPTH  5
+#define NV_MC_EMEM_APFIFO_DEPTH 5
+#define NV_MC_ARB_EMEM_REGLEVEL 3
+#define NV_MC_EMEM_REQ_ID_WIDEREQ       8
+#define NV_MC_EMEM_RDI_ID_WIDERDI       8
+#define NV_MC_EMEM_REQ_ID_ILLEGALACC    7
+#define NV_MC_EMEM_RDI_ID_ILLEGALACC    7
+#define NV_MC_EMEM_REQ_ID_LLRAWDECR     6
+#define NV_MC_EMEM_RDI_ID_LLRAWDECR     6
+#define NV_MC_EMEM_REQ_ID_APCIGNORE     5
+#define NV_MC_EMEM_RDI_ID_APCIGNORE     5
+
+// Packet MC2EMC
+#define MC2EMC_SIZE 186
+
+#define MC2EMC_WDO_SHIFT                        _MK_SHIFT_CONST(0)
+#define MC2EMC_WDO_FIELD                        (_MK_MASK_CONST(0xffffffff) << MC2EMC_WDO_SHIFT)
+#define MC2EMC_WDO_RANGE                        _MK_SHIFT_CONST(127):_MK_SHIFT_CONST(0)
+#define MC2EMC_WDO_ROW                  0
+
+#define MC2EMC_WDO_0_SHIFT                      _MK_SHIFT_CONST(0)
+#define MC2EMC_WDO_0_FIELD                      (_MK_MASK_CONST(0xffffffff) << MC2EMC_WDO_0_SHIFT)
+#define MC2EMC_WDO_0_RANGE                      _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define MC2EMC_WDO_0_ROW                        0
+
+#define MC2EMC_WDO_1_SHIFT                      _MK_SHIFT_CONST(32)
+#define MC2EMC_WDO_1_FIELD                      (_MK_MASK_CONST(0xffffffff) << MC2EMC_WDO_1_SHIFT)
+#define MC2EMC_WDO_1_RANGE                      _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(32)
+#define MC2EMC_WDO_1_ROW                        0
+
+#define MC2EMC_WDO_2_SHIFT                      _MK_SHIFT_CONST(64)
+#define MC2EMC_WDO_2_FIELD                      (_MK_MASK_CONST(0xffffffff) << MC2EMC_WDO_2_SHIFT)
+#define MC2EMC_WDO_2_RANGE                      _MK_SHIFT_CONST(95):_MK_SHIFT_CONST(64)
+#define MC2EMC_WDO_2_ROW                        0
+
+#define MC2EMC_WDO_3_SHIFT                      _MK_SHIFT_CONST(96)
+#define MC2EMC_WDO_3_FIELD                      (_MK_MASK_CONST(0xffffffff) << MC2EMC_WDO_3_SHIFT)
+#define MC2EMC_WDO_3_RANGE                      _MK_SHIFT_CONST(127):_MK_SHIFT_CONST(96)
+#define MC2EMC_WDO_3_ROW                        0
+
+#define MC2EMC_BE_SHIFT                 _MK_SHIFT_CONST(128)
+#define MC2EMC_BE_FIELD                 (_MK_MASK_CONST(0xffff) << MC2EMC_BE_SHIFT)
+#define MC2EMC_BE_RANGE                 _MK_SHIFT_CONST(143):_MK_SHIFT_CONST(128)
+#define MC2EMC_BE_ROW                   0
+
+#define MC2EMC_ADR_SHIFT                        _MK_SHIFT_CONST(144)
+#define MC2EMC_ADR_FIELD                        (_MK_MASK_CONST(0x3ffffff) << MC2EMC_ADR_SHIFT)
+#define MC2EMC_ADR_RANGE                        _MK_SHIFT_CONST(169):_MK_SHIFT_CONST(144)
+#define MC2EMC_ADR_ROW                  0
+
+#define MC2EMC_REQ_ID_SHIFT                     _MK_SHIFT_CONST(170)
+#define MC2EMC_REQ_ID_FIELD                     (_MK_MASK_CONST(0x1ff) << MC2EMC_REQ_ID_SHIFT)
+#define MC2EMC_REQ_ID_RANGE                     _MK_SHIFT_CONST(178):_MK_SHIFT_CONST(170)
+#define MC2EMC_REQ_ID_ROW                       0
+
+#define MC2EMC_AP_SHIFT                 _MK_SHIFT_CONST(179)
+#define MC2EMC_AP_FIELD                 (_MK_MASK_CONST(0x1) << MC2EMC_AP_SHIFT)
+#define MC2EMC_AP_RANGE                 _MK_SHIFT_CONST(179):_MK_SHIFT_CONST(179)
+#define MC2EMC_AP_ROW                   0
+
+#define MC2EMC_WE_SHIFT                 _MK_SHIFT_CONST(180)
+#define MC2EMC_WE_FIELD                 (_MK_MASK_CONST(0x1) << MC2EMC_WE_SHIFT)
+#define MC2EMC_WE_RANGE                 _MK_SHIFT_CONST(180):_MK_SHIFT_CONST(180)
+#define MC2EMC_WE_ROW                   0
+
+#define MC2EMC_TAG_SHIFT                        _MK_SHIFT_CONST(181)
+#define MC2EMC_TAG_FIELD                        (_MK_MASK_CONST(0x1f) << MC2EMC_TAG_SHIFT)
+#define MC2EMC_TAG_RANGE                        _MK_SHIFT_CONST(185):_MK_SHIFT_CONST(181)
+#define MC2EMC_TAG_ROW                  0
+
+
+// Packet MC2EMC_APC
+#define MC2EMC_APC_SIZE 3
+
+#define MC2EMC_APC_CLR_SHIFT                    _MK_SHIFT_CONST(0)
+#define MC2EMC_APC_CLR_FIELD                    (_MK_MASK_CONST(0x1) << MC2EMC_APC_CLR_SHIFT)
+#define MC2EMC_APC_CLR_RANGE                    _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define MC2EMC_APC_CLR_ROW                      0
+
+#define MC2EMC_APC_BANK_SHIFT                   _MK_SHIFT_CONST(1)
+#define MC2EMC_APC_BANK_FIELD                   (_MK_MASK_CONST(0x3) << MC2EMC_APC_BANK_SHIFT)
+#define MC2EMC_APC_BANK_RANGE                   _MK_SHIFT_CONST(2):_MK_SHIFT_CONST(1)
+#define MC2EMC_APC_BANK_ROW                     0
+
+
+// Packet EMC2MC
+#define EMC2MC_SIZE 137
+
+#define EMC2MC_RDI_SHIFT                        _MK_SHIFT_CONST(0)
+#define EMC2MC_RDI_FIELD                        (_MK_MASK_CONST(0xffffffff) << EMC2MC_RDI_SHIFT)
+#define EMC2MC_RDI_RANGE                        _MK_SHIFT_CONST(127):_MK_SHIFT_CONST(0)
+#define EMC2MC_RDI_ROW                  0
+
+#define EMC2MC_RDI_0_SHIFT                      _MK_SHIFT_CONST(0)
+#define EMC2MC_RDI_0_FIELD                      (_MK_MASK_CONST(0xffffffff) << EMC2MC_RDI_0_SHIFT)
+#define EMC2MC_RDI_0_RANGE                      _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define EMC2MC_RDI_0_ROW                        0
+
+#define EMC2MC_RDI_1_SHIFT                      _MK_SHIFT_CONST(32)
+#define EMC2MC_RDI_1_FIELD                      (_MK_MASK_CONST(0xffffffff) << EMC2MC_RDI_1_SHIFT)
+#define EMC2MC_RDI_1_RANGE                      _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(32)
+#define EMC2MC_RDI_1_ROW                        0
+
+#define EMC2MC_RDI_2_SHIFT                      _MK_SHIFT_CONST(64)
+#define EMC2MC_RDI_2_FIELD                      (_MK_MASK_CONST(0xffffffff) << EMC2MC_RDI_2_SHIFT)
+#define EMC2MC_RDI_2_RANGE                      _MK_SHIFT_CONST(95):_MK_SHIFT_CONST(64)
+#define EMC2MC_RDI_2_ROW                        0
+
+#define EMC2MC_RDI_3_SHIFT                      _MK_SHIFT_CONST(96)
+#define EMC2MC_RDI_3_FIELD                      (_MK_MASK_CONST(0xffffffff) << EMC2MC_RDI_3_SHIFT)
+#define EMC2MC_RDI_3_RANGE                      _MK_SHIFT_CONST(127):_MK_SHIFT_CONST(96)
+#define EMC2MC_RDI_3_ROW                        0
+
+#define EMC2MC_RDI_ID_SHIFT                     _MK_SHIFT_CONST(128)
+#define EMC2MC_RDI_ID_FIELD                     (_MK_MASK_CONST(0x1ff) << EMC2MC_RDI_ID_SHIFT)
+#define EMC2MC_RDI_ID_RANGE                     _MK_SHIFT_CONST(136):_MK_SHIFT_CONST(128)
+#define EMC2MC_RDI_ID_ROW                       0
+
+
+// Packet MC2EMC_LL
+#define MC2EMC_LL_SIZE 33
+
+#define MC2EMC_LL_ADR_SHIFT                     _MK_SHIFT_CONST(0)
+#define MC2EMC_LL_ADR_FIELD                     (_MK_MASK_CONST(0x7ffffff) << MC2EMC_LL_ADR_SHIFT)
+#define MC2EMC_LL_ADR_RANGE                     _MK_SHIFT_CONST(26):_MK_SHIFT_CONST(0)
+#define MC2EMC_LL_ADR_ROW                       0
+
+#define MC2EMC_LL_TAG_SHIFT                     _MK_SHIFT_CONST(27)
+#define MC2EMC_LL_TAG_FIELD                     (_MK_MASK_CONST(0x1f) << MC2EMC_LL_TAG_SHIFT)
+#define MC2EMC_LL_TAG_RANGE                     _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(27)
+#define MC2EMC_LL_TAG_ROW                       0
+
+#define MC2EMC_LL_DOUBLEREQ_SHIFT                       _MK_SHIFT_CONST(32)
+#define MC2EMC_LL_DOUBLEREQ_FIELD                       (_MK_MASK_CONST(0x1) << MC2EMC_LL_DOUBLEREQ_SHIFT)
+#define MC2EMC_LL_DOUBLEREQ_RANGE                       _MK_SHIFT_CONST(32):_MK_SHIFT_CONST(32)
+#define MC2EMC_LL_DOUBLEREQ_ROW                 0
+
+
+// Packet EMC2MC_LL
+#define EMC2MC_LL_SIZE 64
+
+#define EMC2MC_LL_RDI_SHIFT                     _MK_SHIFT_CONST(0)
+#define EMC2MC_LL_RDI_FIELD                     (_MK_MASK_CONST(0xffffffff) << EMC2MC_LL_RDI_SHIFT)
+#define EMC2MC_LL_RDI_RANGE                     _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(0)
+#define EMC2MC_LL_RDI_ROW                       0
+
+
+// Packet MC2EMC_LL_CRITINFO
+#define MC2EMC_LL_CRITINFO_SIZE 11
+
+#define MC2EMC_LL_CRITINFO_HP_SHIFT                     _MK_SHIFT_CONST(0)
+#define MC2EMC_LL_CRITINFO_HP_FIELD                     (_MK_MASK_CONST(0x1f) << MC2EMC_LL_CRITINFO_HP_SHIFT)
+#define MC2EMC_LL_CRITINFO_HP_RANGE                     _MK_SHIFT_CONST(4):_MK_SHIFT_CONST(0)
+#define MC2EMC_LL_CRITINFO_HP_ROW                       0
+
+#define MC2EMC_LL_CRITINFO_TIMEOUT_SHIFT                        _MK_SHIFT_CONST(5)
+#define MC2EMC_LL_CRITINFO_TIMEOUT_FIELD                        (_MK_MASK_CONST(0x3f) << MC2EMC_LL_CRITINFO_TIMEOUT_SHIFT)
+#define MC2EMC_LL_CRITINFO_TIMEOUT_RANGE                        _MK_SHIFT_CONST(10):_MK_SHIFT_CONST(5)
+#define MC2EMC_LL_CRITINFO_TIMEOUT_ROW                  0
+
+
+// Packet MC2EMC_LL_ARBINFO
+#define MC2EMC_LL_ARBINFO_SIZE 2
+
+#define MC2EMC_LL_ARBINFO_BANK_SHIFT                    _MK_SHIFT_CONST(0)
+#define MC2EMC_LL_ARBINFO_BANK_FIELD                    (_MK_MASK_CONST(0x3) << MC2EMC_LL_ARBINFO_BANK_SHIFT)
+#define MC2EMC_LL_ARBINFO_BANK_RANGE                    _MK_SHIFT_CONST(1):_MK_SHIFT_CONST(0)
+#define MC2EMC_LL_ARBINFO_BANK_ROW                      0
+
+
+// Packet CMC2MC_AXI_A
+#define CMC2MC_AXI_A_SIZE 63
+
+#define CMC2MC_AXI_A_AADDR_SHIFT                        _MK_SHIFT_CONST(0)
+#define CMC2MC_AXI_A_AADDR_FIELD                        (_MK_MASK_CONST(0xffffffff) << CMC2MC_AXI_A_AADDR_SHIFT)
+#define CMC2MC_AXI_A_AADDR_RANGE                        _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CMC2MC_AXI_A_AADDR_ROW                  0
+
+#define CMC2MC_AXI_A_AID_SHIFT                  _MK_SHIFT_CONST(32)
+#define CMC2MC_AXI_A_AID_FIELD                  (_MK_MASK_CONST(0x1fff) << CMC2MC_AXI_A_AID_SHIFT)
+#define CMC2MC_AXI_A_AID_RANGE                  _MK_SHIFT_CONST(44):_MK_SHIFT_CONST(32)
+#define CMC2MC_AXI_A_AID_ROW                    0
+
+#define CMC2MC_AXI_A_ALEN_SHIFT                 _MK_SHIFT_CONST(45)
+#define CMC2MC_AXI_A_ALEN_FIELD                 (_MK_MASK_CONST(0xf) << CMC2MC_AXI_A_ALEN_SHIFT)
+#define CMC2MC_AXI_A_ALEN_RANGE                 _MK_SHIFT_CONST(48):_MK_SHIFT_CONST(45)
+#define CMC2MC_AXI_A_ALEN_ROW                   0
+#define CMC2MC_AXI_A_ALEN_ONEDATA                       _MK_ENUM_CONST(0)
+#define CMC2MC_AXI_A_ALEN_TWODATA                       _MK_ENUM_CONST(1)
+#define CMC2MC_AXI_A_ALEN_THREEDATA                     _MK_ENUM_CONST(2)
+#define CMC2MC_AXI_A_ALEN_FOURDATA                      _MK_ENUM_CONST(3)
+#define CMC2MC_AXI_A_ALEN_FIVEDATA                      _MK_ENUM_CONST(4)
+#define CMC2MC_AXI_A_ALEN_SIXDATA                       _MK_ENUM_CONST(5)
+#define CMC2MC_AXI_A_ALEN_SEVENDATA                     _MK_ENUM_CONST(6)
+#define CMC2MC_AXI_A_ALEN_EIGHTDATA                     _MK_ENUM_CONST(7)
+#define CMC2MC_AXI_A_ALEN_NINEDATA                      _MK_ENUM_CONST(8)
+#define CMC2MC_AXI_A_ALEN_TENDATA                       _MK_ENUM_CONST(9)
+#define CMC2MC_AXI_A_ALEN_ELEVENDATA                    _MK_ENUM_CONST(10)
+#define CMC2MC_AXI_A_ALEN_TWELVEDATA                    _MK_ENUM_CONST(11)
+#define CMC2MC_AXI_A_ALEN_THIRTEENDATA                  _MK_ENUM_CONST(12)
+#define CMC2MC_AXI_A_ALEN_FOURTEENDATA                  _MK_ENUM_CONST(13)
+#define CMC2MC_AXI_A_ALEN_FIFTHTEENDATA                 _MK_ENUM_CONST(14)
+#define CMC2MC_AXI_A_ALEN_SIXTEENDATA                   _MK_ENUM_CONST(15)
+
+#define CMC2MC_AXI_A_ASIZE_SHIFT                        _MK_SHIFT_CONST(49)
+#define CMC2MC_AXI_A_ASIZE_FIELD                        (_MK_MASK_CONST(0x7) << CMC2MC_AXI_A_ASIZE_SHIFT)
+#define CMC2MC_AXI_A_ASIZE_RANGE                        _MK_SHIFT_CONST(51):_MK_SHIFT_CONST(49)
+#define CMC2MC_AXI_A_ASIZE_ROW                  0
+#define CMC2MC_AXI_A_ASIZE_ONEBYTE                      _MK_ENUM_CONST(0)
+#define CMC2MC_AXI_A_ASIZE_TWOBYTES                     _MK_ENUM_CONST(1)
+#define CMC2MC_AXI_A_ASIZE_FOURBYTES                    _MK_ENUM_CONST(2)
+#define CMC2MC_AXI_A_ASIZE_EIGHTBYTES                   _MK_ENUM_CONST(3)
+#define CMC2MC_AXI_A_ASIZE_SIXTEENBYTES                 _MK_ENUM_CONST(4)
+#define CMC2MC_AXI_A_ASIZE_THIRTYTWOBYTES                       _MK_ENUM_CONST(5)
+#define CMC2MC_AXI_A_ASIZE_SIXTYFOURBYTES                       _MK_ENUM_CONST(6)
+#define CMC2MC_AXI_A_ASIZE_ONEHUNDREDTWENTYEIGHTBYTES                   _MK_ENUM_CONST(7)
+
+#define CMC2MC_AXI_A_ABURST_SHIFT                       _MK_SHIFT_CONST(52)
+#define CMC2MC_AXI_A_ABURST_FIELD                       (_MK_MASK_CONST(0x3) << CMC2MC_AXI_A_ABURST_SHIFT)
+#define CMC2MC_AXI_A_ABURST_RANGE                       _MK_SHIFT_CONST(53):_MK_SHIFT_CONST(52)
+#define CMC2MC_AXI_A_ABURST_ROW                 0
+#define CMC2MC_AXI_A_ABURST_FIXED                       _MK_ENUM_CONST(0)
+#define CMC2MC_AXI_A_ABURST_INCR                        _MK_ENUM_CONST(1)
+#define CMC2MC_AXI_A_ABURST_WRAP                        _MK_ENUM_CONST(2)
+#define CMC2MC_AXI_A_ABURST_RSVD                        _MK_ENUM_CONST(3)
+
+#define CMC2MC_AXI_A_ALOCK_SHIFT                        _MK_SHIFT_CONST(54)
+#define CMC2MC_AXI_A_ALOCK_FIELD                        (_MK_MASK_CONST(0x3) << CMC2MC_AXI_A_ALOCK_SHIFT)
+#define CMC2MC_AXI_A_ALOCK_RANGE                        _MK_SHIFT_CONST(55):_MK_SHIFT_CONST(54)
+#define CMC2MC_AXI_A_ALOCK_ROW                  0
+#define CMC2MC_AXI_A_ALOCK_NORMAL                       _MK_ENUM_CONST(0)
+#define CMC2MC_AXI_A_ALOCK_EXCLUSIVE                    _MK_ENUM_CONST(1)
+#define CMC2MC_AXI_A_ALOCK_LOCKED                       _MK_ENUM_CONST(2)
+#define CMC2MC_AXI_A_ALOCK_RSVD                 _MK_ENUM_CONST(3)
+
+#define CMC2MC_AXI_A_ACACHE_SHIFT                       _MK_SHIFT_CONST(56)
+#define CMC2MC_AXI_A_ACACHE_FIELD                       (_MK_MASK_CONST(0xf) << CMC2MC_AXI_A_ACACHE_SHIFT)
+#define CMC2MC_AXI_A_ACACHE_RANGE                       _MK_SHIFT_CONST(59):_MK_SHIFT_CONST(56)
+#define CMC2MC_AXI_A_ACACHE_ROW                 0
+#define CMC2MC_AXI_A_ACACHE_NONCACHEABLE_NONBUFFERABLE                  _MK_ENUM_CONST(0)
+#define CMC2MC_AXI_A_ACACHE_BUFFERABLE                  _MK_ENUM_CONST(1)
+#define CMC2MC_AXI_A_ACACHE_CACHEABLE_DONOTALLOCATE                     _MK_ENUM_CONST(2)
+#define CMC2MC_AXI_A_ACACHE_CACHEABLE_BUFFERABLE_DONOTALLOCATE                  _MK_ENUM_CONST(3)
+#define CMC2MC_AXI_A_ACACHE_CACHEABLEWRITETHROUGH_ALLOCATEONREAD                        _MK_ENUM_CONST(6)
+#define CMC2MC_AXI_A_ACACHE_CACHEABLEWRITEBACK_ALLOCATEONREAD                   _MK_ENUM_CONST(7)
+#define CMC2MC_AXI_A_ACACHE_CACHEABLEWRITETHROUGH_ALLOCATEONWRITE                       _MK_ENUM_CONST(10)
+#define CMC2MC_AXI_A_ACACHE_CACHEABLEWRITEBACK_ALLOCATEONWRITE                  _MK_ENUM_CONST(11)
+#define CMC2MC_AXI_A_ACACHE_CACHEABLEWRITETHROUGH_ALLOCATEONREADWRITE                   _MK_ENUM_CONST(14)
+#define CMC2MC_AXI_A_ACACHE_CACHEABLEWRITEBACK_ALLOCATEONREADWRITE                      _MK_ENUM_CONST(15)
+
+#define CMC2MC_AXI_A_APROT_SHIFT                        _MK_SHIFT_CONST(60)
+#define CMC2MC_AXI_A_APROT_FIELD                        (_MK_MASK_CONST(0x7) << CMC2MC_AXI_A_APROT_SHIFT)
+#define CMC2MC_AXI_A_APROT_RANGE                        _MK_SHIFT_CONST(62):_MK_SHIFT_CONST(60)
+#define CMC2MC_AXI_A_APROT_ROW                  0
+#define CMC2MC_AXI_A_APROT_DATA_SECURE_NORMAL                   _MK_ENUM_CONST(0)
+#define CMC2MC_AXI_A_APROT_DATA_SECURE_PRIVILEGED                       _MK_ENUM_CONST(1)
+#define CMC2MC_AXI_A_APROT_DATA_NONSECURE_NORMAL                        _MK_ENUM_CONST(2)
+#define CMC2MC_AXI_A_APROT_DATA_NONSECURE_PRIVILEGED                    _MK_ENUM_CONST(3)
+#define CMC2MC_AXI_A_APROT_INST_SECURE_NORMAL                   _MK_ENUM_CONST(4)
+#define CMC2MC_AXI_A_APROT_INST_SECURE_PRIVILEGED                       _MK_ENUM_CONST(5)
+#define CMC2MC_AXI_A_APROT_INST_NONSECURE_NORMAL                        _MK_ENUM_CONST(6)
+#define CMC2MC_AXI_A_APROT_INST_NONSECURE_PRIVILEGED                    _MK_ENUM_CONST(7)
+
+
+// Packet CMC2MC_AXI_W
+#define CMC2MC_AXI_W_SIZE 86
+
+#define CMC2MC_AXI_W_WDATA_SHIFT                        _MK_SHIFT_CONST(0)
+#define CMC2MC_AXI_W_WDATA_FIELD                        (_MK_MASK_CONST(0xffffffff) << CMC2MC_AXI_W_WDATA_SHIFT)
+#define CMC2MC_AXI_W_WDATA_RANGE                        _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(0)
+#define CMC2MC_AXI_W_WDATA_ROW                  0
+
+#define CMC2MC_AXI_W_WID_SHIFT                  _MK_SHIFT_CONST(64)
+#define CMC2MC_AXI_W_WID_FIELD                  (_MK_MASK_CONST(0x1fff) << CMC2MC_AXI_W_WID_SHIFT)
+#define CMC2MC_AXI_W_WID_RANGE                  _MK_SHIFT_CONST(76):_MK_SHIFT_CONST(64)
+#define CMC2MC_AXI_W_WID_ROW                    0
+
+#define CMC2MC_AXI_W_WSTRB_SHIFT                        _MK_SHIFT_CONST(77)
+#define CMC2MC_AXI_W_WSTRB_FIELD                        (_MK_MASK_CONST(0xff) << CMC2MC_AXI_W_WSTRB_SHIFT)
+#define CMC2MC_AXI_W_WSTRB_RANGE                        _MK_SHIFT_CONST(84):_MK_SHIFT_CONST(77)
+#define CMC2MC_AXI_W_WSTRB_ROW                  0
+
+#define CMC2MC_AXI_W_WLAST_SHIFT                        _MK_SHIFT_CONST(85)
+#define CMC2MC_AXI_W_WLAST_FIELD                        (_MK_MASK_CONST(0x1) << CMC2MC_AXI_W_WLAST_SHIFT)
+#define CMC2MC_AXI_W_WLAST_RANGE                        _MK_SHIFT_CONST(85):_MK_SHIFT_CONST(85)
+#define CMC2MC_AXI_W_WLAST_ROW                  0
+#define CMC2MC_AXI_W_WLAST_DISABLED                     _MK_ENUM_CONST(0)
+#define CMC2MC_AXI_W_WLAST_ENABLED                      _MK_ENUM_CONST(1)
+
+
+// Packet CMC2MC_AXI_B
+#define CMC2MC_AXI_B_SIZE 15
+
+#define CMC2MC_AXI_B_BID_SHIFT                  _MK_SHIFT_CONST(0)
+#define CMC2MC_AXI_B_BID_FIELD                  (_MK_MASK_CONST(0x1fff) << CMC2MC_AXI_B_BID_SHIFT)
+#define CMC2MC_AXI_B_BID_RANGE                  _MK_SHIFT_CONST(12):_MK_SHIFT_CONST(0)
+#define CMC2MC_AXI_B_BID_ROW                    0
+
+#define CMC2MC_AXI_B_BRESP_SHIFT                        _MK_SHIFT_CONST(13)
+#define CMC2MC_AXI_B_BRESP_FIELD                        (_MK_MASK_CONST(0x3) << CMC2MC_AXI_B_BRESP_SHIFT)
+#define CMC2MC_AXI_B_BRESP_RANGE                        _MK_SHIFT_CONST(14):_MK_SHIFT_CONST(13)
+#define CMC2MC_AXI_B_BRESP_ROW                  0
+#define CMC2MC_AXI_B_BRESP_OKAY                 _MK_ENUM_CONST(0)
+#define CMC2MC_AXI_B_BRESP_EXOKAY                       _MK_ENUM_CONST(1)
+#define CMC2MC_AXI_B_BRESP_SLVERR                       _MK_ENUM_CONST(2)
+#define CMC2MC_AXI_B_BRESP_DECERR                       _MK_ENUM_CONST(3)
+
+
+// Packet CMC2MC_AXI_R
+#define CMC2MC_AXI_R_SIZE 80
+
+#define CMC2MC_AXI_R_RDATA_SHIFT                        _MK_SHIFT_CONST(0)
+#define CMC2MC_AXI_R_RDATA_FIELD                        (_MK_MASK_CONST(0xffffffff) << CMC2MC_AXI_R_RDATA_SHIFT)
+#define CMC2MC_AXI_R_RDATA_RANGE                        _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(0)
+#define CMC2MC_AXI_R_RDATA_ROW                  0
+
+#define CMC2MC_AXI_R_RID_SHIFT                  _MK_SHIFT_CONST(64)
+#define CMC2MC_AXI_R_RID_FIELD                  (_MK_MASK_CONST(0x1fff) << CMC2MC_AXI_R_RID_SHIFT)
+#define CMC2MC_AXI_R_RID_RANGE                  _MK_SHIFT_CONST(76):_MK_SHIFT_CONST(64)
+#define CMC2MC_AXI_R_RID_ROW                    0
+
+#define CMC2MC_AXI_R_RRESP_SHIFT                        _MK_SHIFT_CONST(77)
+#define CMC2MC_AXI_R_RRESP_FIELD                        (_MK_MASK_CONST(0x3) << CMC2MC_AXI_R_RRESP_SHIFT)
+#define CMC2MC_AXI_R_RRESP_RANGE                        _MK_SHIFT_CONST(78):_MK_SHIFT_CONST(77)
+#define CMC2MC_AXI_R_RRESP_ROW                  0
+#define CMC2MC_AXI_R_RRESP_OKAY                 _MK_ENUM_CONST(0)
+#define CMC2MC_AXI_R_RRESP_EXOKAY                       _MK_ENUM_CONST(1)
+#define CMC2MC_AXI_R_RRESP_SLVERR                       _MK_ENUM_CONST(2)
+#define CMC2MC_AXI_R_RRESP_DECERR                       _MK_ENUM_CONST(3)
+
+#define CMC2MC_AXI_R_RLAST_SHIFT                        _MK_SHIFT_CONST(79)
+#define CMC2MC_AXI_R_RLAST_FIELD                        (_MK_MASK_CONST(0x1) << CMC2MC_AXI_R_RLAST_SHIFT)
+#define CMC2MC_AXI_R_RLAST_RANGE                        _MK_SHIFT_CONST(79):_MK_SHIFT_CONST(79)
+#define CMC2MC_AXI_R_RLAST_ROW                  0
+#define CMC2MC_AXI_R_RLAST_DISABLED                     _MK_ENUM_CONST(0)
+#define CMC2MC_AXI_R_RLAST_ENABLED                      _MK_ENUM_CONST(1)
+
+
+// Packet MSELECT2MC_AXI_A
+#define MSELECT2MC_AXI_A_SIZE 63
+
+#define MSELECT2MC_AXI_A_AADDR_SHIFT                    _MK_SHIFT_CONST(0)
+#define MSELECT2MC_AXI_A_AADDR_FIELD                    (_MK_MASK_CONST(0xffffffff) << MSELECT2MC_AXI_A_AADDR_SHIFT)
+#define MSELECT2MC_AXI_A_AADDR_RANGE                    _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define MSELECT2MC_AXI_A_AADDR_ROW                      0
+
+#define MSELECT2MC_AXI_A_AID_SHIFT                      _MK_SHIFT_CONST(32)
+#define MSELECT2MC_AXI_A_AID_FIELD                      (_MK_MASK_CONST(0x1fff) << MSELECT2MC_AXI_A_AID_SHIFT)
+#define MSELECT2MC_AXI_A_AID_RANGE                      _MK_SHIFT_CONST(44):_MK_SHIFT_CONST(32)
+#define MSELECT2MC_AXI_A_AID_ROW                        0
+
+#define MSELECT2MC_AXI_A_ALEN_SHIFT                     _MK_SHIFT_CONST(45)
+#define MSELECT2MC_AXI_A_ALEN_FIELD                     (_MK_MASK_CONST(0xf) << MSELECT2MC_AXI_A_ALEN_SHIFT)
+#define MSELECT2MC_AXI_A_ALEN_RANGE                     _MK_SHIFT_CONST(48):_MK_SHIFT_CONST(45)
+#define MSELECT2MC_AXI_A_ALEN_ROW                       0
+#define MSELECT2MC_AXI_A_ALEN_ONEDATA                   _MK_ENUM_CONST(0)
+#define MSELECT2MC_AXI_A_ALEN_TWODATA                   _MK_ENUM_CONST(1)
+#define MSELECT2MC_AXI_A_ALEN_THREEDATA                 _MK_ENUM_CONST(2)
+#define MSELECT2MC_AXI_A_ALEN_FOURDATA                  _MK_ENUM_CONST(3)
+#define MSELECT2MC_AXI_A_ALEN_FIVEDATA                  _MK_ENUM_CONST(4)
+#define MSELECT2MC_AXI_A_ALEN_SIXDATA                   _MK_ENUM_CONST(5)
+#define MSELECT2MC_AXI_A_ALEN_SEVENDATA                 _MK_ENUM_CONST(6)
+#define MSELECT2MC_AXI_A_ALEN_EIGHTDATA                 _MK_ENUM_CONST(7)
+#define MSELECT2MC_AXI_A_ALEN_NINEDATA                  _MK_ENUM_CONST(8)
+#define MSELECT2MC_AXI_A_ALEN_TENDATA                   _MK_ENUM_CONST(9)
+#define MSELECT2MC_AXI_A_ALEN_ELEVENDATA                        _MK_ENUM_CONST(10)
+#define MSELECT2MC_AXI_A_ALEN_TWELVEDATA                        _MK_ENUM_CONST(11)
+#define MSELECT2MC_AXI_A_ALEN_THIRTEENDATA                      _MK_ENUM_CONST(12)
+#define MSELECT2MC_AXI_A_ALEN_FOURTEENDATA                      _MK_ENUM_CONST(13)
+#define MSELECT2MC_AXI_A_ALEN_FIFTHTEENDATA                     _MK_ENUM_CONST(14)
+#define MSELECT2MC_AXI_A_ALEN_SIXTEENDATA                       _MK_ENUM_CONST(15)
+
+#define MSELECT2MC_AXI_A_ASIZE_SHIFT                    _MK_SHIFT_CONST(49)
+#define MSELECT2MC_AXI_A_ASIZE_FIELD                    (_MK_MASK_CONST(0x7) << MSELECT2MC_AXI_A_ASIZE_SHIFT)
+#define MSELECT2MC_AXI_A_ASIZE_RANGE                    _MK_SHIFT_CONST(51):_MK_SHIFT_CONST(49)
+#define MSELECT2MC_AXI_A_ASIZE_ROW                      0
+#define MSELECT2MC_AXI_A_ASIZE_ONEBYTE                  _MK_ENUM_CONST(0)
+#define MSELECT2MC_AXI_A_ASIZE_TWOBYTES                 _MK_ENUM_CONST(1)
+#define MSELECT2MC_AXI_A_ASIZE_FOURBYTES                        _MK_ENUM_CONST(2)
+#define MSELECT2MC_AXI_A_ASIZE_EIGHTBYTES                       _MK_ENUM_CONST(3)
+#define MSELECT2MC_AXI_A_ASIZE_SIXTEENBYTES                     _MK_ENUM_CONST(4)
+#define MSELECT2MC_AXI_A_ASIZE_THIRTYTWOBYTES                   _MK_ENUM_CONST(5)
+#define MSELECT2MC_AXI_A_ASIZE_SIXTYFOURBYTES                   _MK_ENUM_CONST(6)
+#define MSELECT2MC_AXI_A_ASIZE_ONEHUNDREDTWENTYEIGHTBYTES                       _MK_ENUM_CONST(7)
+
+#define MSELECT2MC_AXI_A_ABURST_SHIFT                   _MK_SHIFT_CONST(52)
+#define MSELECT2MC_AXI_A_ABURST_FIELD                   (_MK_MASK_CONST(0x3) << MSELECT2MC_AXI_A_ABURST_SHIFT)
+#define MSELECT2MC_AXI_A_ABURST_RANGE                   _MK_SHIFT_CONST(53):_MK_SHIFT_CONST(52)
+#define MSELECT2MC_AXI_A_ABURST_ROW                     0
+#define MSELECT2MC_AXI_A_ABURST_FIXED                   _MK_ENUM_CONST(0)
+#define MSELECT2MC_AXI_A_ABURST_INCR                    _MK_ENUM_CONST(1)
+#define MSELECT2MC_AXI_A_ABURST_WRAP                    _MK_ENUM_CONST(2)
+#define MSELECT2MC_AXI_A_ABURST_RSVD                    _MK_ENUM_CONST(3)
+
+#define MSELECT2MC_AXI_A_ALOCK_SHIFT                    _MK_SHIFT_CONST(54)
+#define MSELECT2MC_AXI_A_ALOCK_FIELD                    (_MK_MASK_CONST(0x3) << MSELECT2MC_AXI_A_ALOCK_SHIFT)
+#define MSELECT2MC_AXI_A_ALOCK_RANGE                    _MK_SHIFT_CONST(55):_MK_SHIFT_CONST(54)
+#define MSELECT2MC_AXI_A_ALOCK_ROW                      0
+#define MSELECT2MC_AXI_A_ALOCK_NORMAL                   _MK_ENUM_CONST(0)
+#define MSELECT2MC_AXI_A_ALOCK_EXCLUSIVE                        _MK_ENUM_CONST(1)
+#define MSELECT2MC_AXI_A_ALOCK_LOCKED                   _MK_ENUM_CONST(2)
+#define MSELECT2MC_AXI_A_ALOCK_RSVD                     _MK_ENUM_CONST(3)
+
+#define MSELECT2MC_AXI_A_ACACHE_SHIFT                   _MK_SHIFT_CONST(56)
+#define MSELECT2MC_AXI_A_ACACHE_FIELD                   (_MK_MASK_CONST(0xf) << MSELECT2MC_AXI_A_ACACHE_SHIFT)
+#define MSELECT2MC_AXI_A_ACACHE_RANGE                   _MK_SHIFT_CONST(59):_MK_SHIFT_CONST(56)
+#define MSELECT2MC_AXI_A_ACACHE_ROW                     0
+#define MSELECT2MC_AXI_A_ACACHE_NONCACHEABLE_NONBUFFERABLE                      _MK_ENUM_CONST(0)
+#define MSELECT2MC_AXI_A_ACACHE_BUFFERABLE                      _MK_ENUM_CONST(1)
+#define MSELECT2MC_AXI_A_ACACHE_CACHEABLE_DONOTALLOCATE                 _MK_ENUM_CONST(2)
+#define MSELECT2MC_AXI_A_ACACHE_CACHEABLE_BUFFERABLE_DONOTALLOCATE                      _MK_ENUM_CONST(3)
+#define MSELECT2MC_AXI_A_ACACHE_CACHEABLEWRITETHROUGH_ALLOCATEONREAD                    _MK_ENUM_CONST(6)
+#define MSELECT2MC_AXI_A_ACACHE_CACHEABLEWRITEBACK_ALLOCATEONREAD                       _MK_ENUM_CONST(7)
+#define MSELECT2MC_AXI_A_ACACHE_CACHEABLEWRITETHROUGH_ALLOCATEONWRITE                   _MK_ENUM_CONST(10)
+#define MSELECT2MC_AXI_A_ACACHE_CACHEABLEWRITEBACK_ALLOCATEONWRITE                      _MK_ENUM_CONST(11)
+#define MSELECT2MC_AXI_A_ACACHE_CACHEABLEWRITETHROUGH_ALLOCATEONREADWRITE                       _MK_ENUM_CONST(14)
+#define MSELECT2MC_AXI_A_ACACHE_CACHEABLEWRITEBACK_ALLOCATEONREADWRITE                  _MK_ENUM_CONST(15)
+
+#define MSELECT2MC_AXI_A_APROT_SHIFT                    _MK_SHIFT_CONST(60)
+#define MSELECT2MC_AXI_A_APROT_FIELD                    (_MK_MASK_CONST(0x7) << MSELECT2MC_AXI_A_APROT_SHIFT)
+#define MSELECT2MC_AXI_A_APROT_RANGE                    _MK_SHIFT_CONST(62):_MK_SHIFT_CONST(60)
+#define MSELECT2MC_AXI_A_APROT_ROW                      0
+#define MSELECT2MC_AXI_A_APROT_DATA_SECURE_NORMAL                       _MK_ENUM_CONST(0)
+#define MSELECT2MC_AXI_A_APROT_DATA_SECURE_PRIVILEGED                   _MK_ENUM_CONST(1)
+#define MSELECT2MC_AXI_A_APROT_DATA_NONSECURE_NORMAL                    _MK_ENUM_CONST(2)
+#define MSELECT2MC_AXI_A_APROT_DATA_NONSECURE_PRIVILEGED                        _MK_ENUM_CONST(3)
+#define MSELECT2MC_AXI_A_APROT_INST_SECURE_NORMAL                       _MK_ENUM_CONST(4)
+#define MSELECT2MC_AXI_A_APROT_INST_SECURE_PRIVILEGED                   _MK_ENUM_CONST(5)
+#define MSELECT2MC_AXI_A_APROT_INST_NONSECURE_NORMAL                    _MK_ENUM_CONST(6)
+#define MSELECT2MC_AXI_A_APROT_INST_NONSECURE_PRIVILEGED                        _MK_ENUM_CONST(7)
+
+
+// Packet MSELECT2MC_AXI_W
+#define MSELECT2MC_AXI_W_SIZE 86
+
+#define MSELECT2MC_AXI_W_WDATA_SHIFT                    _MK_SHIFT_CONST(0)
+#define MSELECT2MC_AXI_W_WDATA_FIELD                    (_MK_MASK_CONST(0xffffffff) << MSELECT2MC_AXI_W_WDATA_SHIFT)
+#define MSELECT2MC_AXI_W_WDATA_RANGE                    _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(0)
+#define MSELECT2MC_AXI_W_WDATA_ROW                      0
+
+#define MSELECT2MC_AXI_W_WID_SHIFT                      _MK_SHIFT_CONST(64)
+#define MSELECT2MC_AXI_W_WID_FIELD                      (_MK_MASK_CONST(0x1fff) << MSELECT2MC_AXI_W_WID_SHIFT)
+#define MSELECT2MC_AXI_W_WID_RANGE                      _MK_SHIFT_CONST(76):_MK_SHIFT_CONST(64)
+#define MSELECT2MC_AXI_W_WID_ROW                        0
+
+#define MSELECT2MC_AXI_W_WSTRB_SHIFT                    _MK_SHIFT_CONST(77)
+#define MSELECT2MC_AXI_W_WSTRB_FIELD                    (_MK_MASK_CONST(0xff) << MSELECT2MC_AXI_W_WSTRB_SHIFT)
+#define MSELECT2MC_AXI_W_WSTRB_RANGE                    _MK_SHIFT_CONST(84):_MK_SHIFT_CONST(77)
+#define MSELECT2MC_AXI_W_WSTRB_ROW                      0
+
+#define MSELECT2MC_AXI_W_WLAST_SHIFT                    _MK_SHIFT_CONST(85)
+#define MSELECT2MC_AXI_W_WLAST_FIELD                    (_MK_MASK_CONST(0x1) << MSELECT2MC_AXI_W_WLAST_SHIFT)
+#define MSELECT2MC_AXI_W_WLAST_RANGE                    _MK_SHIFT_CONST(85):_MK_SHIFT_CONST(85)
+#define MSELECT2MC_AXI_W_WLAST_ROW                      0
+#define MSELECT2MC_AXI_W_WLAST_DISABLED                 _MK_ENUM_CONST(0)
+#define MSELECT2MC_AXI_W_WLAST_ENABLED                  _MK_ENUM_CONST(1)
+
+
+// Packet MSELECT2MC_AXI_B
+#define MSELECT2MC_AXI_B_SIZE 15
+
+#define MSELECT2MC_AXI_B_BID_SHIFT                      _MK_SHIFT_CONST(0)
+#define MSELECT2MC_AXI_B_BID_FIELD                      (_MK_MASK_CONST(0x1fff) << MSELECT2MC_AXI_B_BID_SHIFT)
+#define MSELECT2MC_AXI_B_BID_RANGE                      _MK_SHIFT_CONST(12):_MK_SHIFT_CONST(0)
+#define MSELECT2MC_AXI_B_BID_ROW                        0
+
+#define MSELECT2MC_AXI_B_BRESP_SHIFT                    _MK_SHIFT_CONST(13)
+#define MSELECT2MC_AXI_B_BRESP_FIELD                    (_MK_MASK_CONST(0x3) << MSELECT2MC_AXI_B_BRESP_SHIFT)
+#define MSELECT2MC_AXI_B_BRESP_RANGE                    _MK_SHIFT_CONST(14):_MK_SHIFT_CONST(13)
+#define MSELECT2MC_AXI_B_BRESP_ROW                      0
+#define MSELECT2MC_AXI_B_BRESP_OKAY                     _MK_ENUM_CONST(0)
+#define MSELECT2MC_AXI_B_BRESP_EXOKAY                   _MK_ENUM_CONST(1)
+#define MSELECT2MC_AXI_B_BRESP_SLVERR                   _MK_ENUM_CONST(2)
+#define MSELECT2MC_AXI_B_BRESP_DECERR                   _MK_ENUM_CONST(3)
+
+
+// Packet MSELECT2MC_AXI_R
+#define MSELECT2MC_AXI_R_SIZE 80
+
+#define MSELECT2MC_AXI_R_RDATA_SHIFT                    _MK_SHIFT_CONST(0)
+#define MSELECT2MC_AXI_R_RDATA_FIELD                    (_MK_MASK_CONST(0xffffffff) << MSELECT2MC_AXI_R_RDATA_SHIFT)
+#define MSELECT2MC_AXI_R_RDATA_RANGE                    _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(0)
+#define MSELECT2MC_AXI_R_RDATA_ROW                      0
+
+#define MSELECT2MC_AXI_R_RID_SHIFT                      _MK_SHIFT_CONST(64)
+#define MSELECT2MC_AXI_R_RID_FIELD                      (_MK_MASK_CONST(0x1fff) << MSELECT2MC_AXI_R_RID_SHIFT)
+#define MSELECT2MC_AXI_R_RID_RANGE                      _MK_SHIFT_CONST(76):_MK_SHIFT_CONST(64)
+#define MSELECT2MC_AXI_R_RID_ROW                        0
+
+#define MSELECT2MC_AXI_R_RRESP_SHIFT                    _MK_SHIFT_CONST(77)
+#define MSELECT2MC_AXI_R_RRESP_FIELD                    (_MK_MASK_CONST(0x3) << MSELECT2MC_AXI_R_RRESP_SHIFT)
+#define MSELECT2MC_AXI_R_RRESP_RANGE                    _MK_SHIFT_CONST(78):_MK_SHIFT_CONST(77)
+#define MSELECT2MC_AXI_R_RRESP_ROW                      0
+#define MSELECT2MC_AXI_R_RRESP_OKAY                     _MK_ENUM_CONST(0)
+#define MSELECT2MC_AXI_R_RRESP_EXOKAY                   _MK_ENUM_CONST(1)
+#define MSELECT2MC_AXI_R_RRESP_SLVERR                   _MK_ENUM_CONST(2)
+#define MSELECT2MC_AXI_R_RRESP_DECERR                   _MK_ENUM_CONST(3)
+
+#define MSELECT2MC_AXI_R_RLAST_SHIFT                    _MK_SHIFT_CONST(79)
+#define MSELECT2MC_AXI_R_RLAST_FIELD                    (_MK_MASK_CONST(0x1) << MSELECT2MC_AXI_R_RLAST_SHIFT)
+#define MSELECT2MC_AXI_R_RLAST_RANGE                    _MK_SHIFT_CONST(79):_MK_SHIFT_CONST(79)
+#define MSELECT2MC_AXI_R_RLAST_ROW                      0
+#define MSELECT2MC_AXI_R_RLAST_DISABLED                 _MK_ENUM_CONST(0)
+#define MSELECT2MC_AXI_R_RLAST_ENABLED                  _MK_ENUM_CONST(1)
+
+
+// Packet AXI2MC_AXI_A
+#define AXI2MC_AXI_A_SIZE 63
+
+#define AXI2MC_AXI_A_AADDR_SHIFT                        _MK_SHIFT_CONST(0)
+#define AXI2MC_AXI_A_AADDR_FIELD                        (_MK_MASK_CONST(0xffffffff) << AXI2MC_AXI_A_AADDR_SHIFT)
+#define AXI2MC_AXI_A_AADDR_RANGE                        _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define AXI2MC_AXI_A_AADDR_ROW                  0
+
+#define AXI2MC_AXI_A_AID_SHIFT                  _MK_SHIFT_CONST(32)
+#define AXI2MC_AXI_A_AID_FIELD                  (_MK_MASK_CONST(0x1fff) << AXI2MC_AXI_A_AID_SHIFT)
+#define AXI2MC_AXI_A_AID_RANGE                  _MK_SHIFT_CONST(44):_MK_SHIFT_CONST(32)
+#define AXI2MC_AXI_A_AID_ROW                    0
+
+#define AXI2MC_AXI_A_ALEN_SHIFT                 _MK_SHIFT_CONST(45)
+#define AXI2MC_AXI_A_ALEN_FIELD                 (_MK_MASK_CONST(0xf) << AXI2MC_AXI_A_ALEN_SHIFT)
+#define AXI2MC_AXI_A_ALEN_RANGE                 _MK_SHIFT_CONST(48):_MK_SHIFT_CONST(45)
+#define AXI2MC_AXI_A_ALEN_ROW                   0
+#define AXI2MC_AXI_A_ALEN_ONEDATA                       _MK_ENUM_CONST(0)
+#define AXI2MC_AXI_A_ALEN_TWODATA                       _MK_ENUM_CONST(1)
+#define AXI2MC_AXI_A_ALEN_THREEDATA                     _MK_ENUM_CONST(2)
+#define AXI2MC_AXI_A_ALEN_FOURDATA                      _MK_ENUM_CONST(3)
+#define AXI2MC_AXI_A_ALEN_FIVEDATA                      _MK_ENUM_CONST(4)
+#define AXI2MC_AXI_A_ALEN_SIXDATA                       _MK_ENUM_CONST(5)
+#define AXI2MC_AXI_A_ALEN_SEVENDATA                     _MK_ENUM_CONST(6)
+#define AXI2MC_AXI_A_ALEN_EIGHTDATA                     _MK_ENUM_CONST(7)
+#define AXI2MC_AXI_A_ALEN_NINEDATA                      _MK_ENUM_CONST(8)
+#define AXI2MC_AXI_A_ALEN_TENDATA                       _MK_ENUM_CONST(9)
+#define AXI2MC_AXI_A_ALEN_ELEVENDATA                    _MK_ENUM_CONST(10)
+#define AXI2MC_AXI_A_ALEN_TWELVEDATA                    _MK_ENUM_CONST(11)
+#define AXI2MC_AXI_A_ALEN_THIRTEENDATA                  _MK_ENUM_CONST(12)
+#define AXI2MC_AXI_A_ALEN_FOURTEENDATA                  _MK_ENUM_CONST(13)
+#define AXI2MC_AXI_A_ALEN_FIFTHTEENDATA                 _MK_ENUM_CONST(14)
+#define AXI2MC_AXI_A_ALEN_SIXTEENDATA                   _MK_ENUM_CONST(15)
+
+#define AXI2MC_AXI_A_ASIZE_SHIFT                        _MK_SHIFT_CONST(49)
+#define AXI2MC_AXI_A_ASIZE_FIELD                        (_MK_MASK_CONST(0x7) << AXI2MC_AXI_A_ASIZE_SHIFT)
+#define AXI2MC_AXI_A_ASIZE_RANGE                        _MK_SHIFT_CONST(51):_MK_SHIFT_CONST(49)
+#define AXI2MC_AXI_A_ASIZE_ROW                  0
+#define AXI2MC_AXI_A_ASIZE_ONEBYTE                      _MK_ENUM_CONST(0)
+#define AXI2MC_AXI_A_ASIZE_TWOBYTES                     _MK_ENUM_CONST(1)
+#define AXI2MC_AXI_A_ASIZE_FOURBYTES                    _MK_ENUM_CONST(2)
+#define AXI2MC_AXI_A_ASIZE_EIGHTBYTES                   _MK_ENUM_CONST(3)
+#define AXI2MC_AXI_A_ASIZE_SIXTEENBYTES                 _MK_ENUM_CONST(4)
+#define AXI2MC_AXI_A_ASIZE_THIRTYTWOBYTES                       _MK_ENUM_CONST(5)
+#define AXI2MC_AXI_A_ASIZE_SIXTYFOURBYTES                       _MK_ENUM_CONST(6)
+#define AXI2MC_AXI_A_ASIZE_ONEHUNDREDTWENTYEIGHTBYTES                   _MK_ENUM_CONST(7)
+
+#define AXI2MC_AXI_A_ABURST_SHIFT                       _MK_SHIFT_CONST(52)
+#define AXI2MC_AXI_A_ABURST_FIELD                       (_MK_MASK_CONST(0x3) << AXI2MC_AXI_A_ABURST_SHIFT)
+#define AXI2MC_AXI_A_ABURST_RANGE                       _MK_SHIFT_CONST(53):_MK_SHIFT_CONST(52)
+#define AXI2MC_AXI_A_ABURST_ROW                 0
+#define AXI2MC_AXI_A_ABURST_FIXED                       _MK_ENUM_CONST(0)
+#define AXI2MC_AXI_A_ABURST_INCR                        _MK_ENUM_CONST(1)
+#define AXI2MC_AXI_A_ABURST_WRAP                        _MK_ENUM_CONST(2)
+#define AXI2MC_AXI_A_ABURST_RSVD                        _MK_ENUM_CONST(3)
+
+#define AXI2MC_AXI_A_ALOCK_SHIFT                        _MK_SHIFT_CONST(54)
+#define AXI2MC_AXI_A_ALOCK_FIELD                        (_MK_MASK_CONST(0x3) << AXI2MC_AXI_A_ALOCK_SHIFT)
+#define AXI2MC_AXI_A_ALOCK_RANGE                        _MK_SHIFT_CONST(55):_MK_SHIFT_CONST(54)
+#define AXI2MC_AXI_A_ALOCK_ROW                  0
+#define AXI2MC_AXI_A_ALOCK_NORMAL                       _MK_ENUM_CONST(0)
+#define AXI2MC_AXI_A_ALOCK_EXCLUSIVE                    _MK_ENUM_CONST(1)
+#define AXI2MC_AXI_A_ALOCK_LOCKED                       _MK_ENUM_CONST(2)
+#define AXI2MC_AXI_A_ALOCK_RSVD                 _MK_ENUM_CONST(3)
+
+#define AXI2MC_AXI_A_ACACHE_SHIFT                       _MK_SHIFT_CONST(56)
+#define AXI2MC_AXI_A_ACACHE_FIELD                       (_MK_MASK_CONST(0xf) << AXI2MC_AXI_A_ACACHE_SHIFT)
+#define AXI2MC_AXI_A_ACACHE_RANGE                       _MK_SHIFT_CONST(59):_MK_SHIFT_CONST(56)
+#define AXI2MC_AXI_A_ACACHE_ROW                 0
+#define AXI2MC_AXI_A_ACACHE_NONCACHEABLE_NONBUFFERABLE                  _MK_ENUM_CONST(0)
+#define AXI2MC_AXI_A_ACACHE_BUFFERABLE                  _MK_ENUM_CONST(1)
+#define AXI2MC_AXI_A_ACACHE_CACHEABLE_DONOTALLOCATE                     _MK_ENUM_CONST(2)
+#define AXI2MC_AXI_A_ACACHE_CACHEABLE_BUFFERABLE_DONOTALLOCATE                  _MK_ENUM_CONST(3)
+#define AXI2MC_AXI_A_ACACHE_CACHEABLEWRITETHROUGH_ALLOCATEONREAD                        _MK_ENUM_CONST(6)
+#define AXI2MC_AXI_A_ACACHE_CACHEABLEWRITEBACK_ALLOCATEONREAD                   _MK_ENUM_CONST(7)
+#define AXI2MC_AXI_A_ACACHE_CACHEABLEWRITETHROUGH_ALLOCATEONWRITE                       _MK_ENUM_CONST(10)
+#define AXI2MC_AXI_A_ACACHE_CACHEABLEWRITEBACK_ALLOCATEONWRITE                  _MK_ENUM_CONST(11)
+#define AXI2MC_AXI_A_ACACHE_CACHEABLEWRITETHROUGH_ALLOCATEONREADWRITE                   _MK_ENUM_CONST(14)
+#define AXI2MC_AXI_A_ACACHE_CACHEABLEWRITEBACK_ALLOCATEONREADWRITE                      _MK_ENUM_CONST(15)
+
+#define AXI2MC_AXI_A_APROT_SHIFT                        _MK_SHIFT_CONST(60)
+#define AXI2MC_AXI_A_APROT_FIELD                        (_MK_MASK_CONST(0x7) << AXI2MC_AXI_A_APROT_SHIFT)
+#define AXI2MC_AXI_A_APROT_RANGE                        _MK_SHIFT_CONST(62):_MK_SHIFT_CONST(60)
+#define AXI2MC_AXI_A_APROT_ROW                  0
+#define AXI2MC_AXI_A_APROT_DATA_SECURE_NORMAL                   _MK_ENUM_CONST(0)
+#define AXI2MC_AXI_A_APROT_DATA_SECURE_PRIVILEGED                       _MK_ENUM_CONST(1)
+#define AXI2MC_AXI_A_APROT_DATA_NONSECURE_NORMAL                        _MK_ENUM_CONST(2)
+#define AXI2MC_AXI_A_APROT_DATA_NONSECURE_PRIVILEGED                    _MK_ENUM_CONST(3)
+#define AXI2MC_AXI_A_APROT_INST_SECURE_NORMAL                   _MK_ENUM_CONST(4)
+#define AXI2MC_AXI_A_APROT_INST_SECURE_PRIVILEGED                       _MK_ENUM_CONST(5)
+#define AXI2MC_AXI_A_APROT_INST_NONSECURE_NORMAL                        _MK_ENUM_CONST(6)
+#define AXI2MC_AXI_A_APROT_INST_NONSECURE_PRIVILEGED                    _MK_ENUM_CONST(7)
+
+
+// Packet AXI2MC_AXI_W
+#define AXI2MC_AXI_W_SIZE 302
+
+#define AXI2MC_AXI_W_WDATA_SHIFT                        _MK_SHIFT_CONST(0)
+#define AXI2MC_AXI_W_WDATA_FIELD                        (_MK_MASK_CONST(0xffffffff) << AXI2MC_AXI_W_WDATA_SHIFT)
+#define AXI2MC_AXI_W_WDATA_RANGE                        _MK_SHIFT_CONST(255):_MK_SHIFT_CONST(0)
+#define AXI2MC_AXI_W_WDATA_ROW                  0
+
+#define AXI2MC_AXI_W_WID_SHIFT                  _MK_SHIFT_CONST(256)
+#define AXI2MC_AXI_W_WID_FIELD                  (_MK_MASK_CONST(0x1fff) << AXI2MC_AXI_W_WID_SHIFT)
+#define AXI2MC_AXI_W_WID_RANGE                  _MK_SHIFT_CONST(268):_MK_SHIFT_CONST(256)
+#define AXI2MC_AXI_W_WID_ROW                    0
+
+#define AXI2MC_AXI_W_WSTRB_SHIFT                        _MK_SHIFT_CONST(269)
+#define AXI2MC_AXI_W_WSTRB_FIELD                        (_MK_MASK_CONST(0xffffffff) << AXI2MC_AXI_W_WSTRB_SHIFT)
+#define AXI2MC_AXI_W_WSTRB_RANGE                        _MK_SHIFT_CONST(300):_MK_SHIFT_CONST(269)
+#define AXI2MC_AXI_W_WSTRB_ROW                  0
+
+#define AXI2MC_AXI_W_WLAST_SHIFT                        _MK_SHIFT_CONST(301)
+#define AXI2MC_AXI_W_WLAST_FIELD                        (_MK_MASK_CONST(0x1) << AXI2MC_AXI_W_WLAST_SHIFT)
+#define AXI2MC_AXI_W_WLAST_RANGE                        _MK_SHIFT_CONST(301):_MK_SHIFT_CONST(301)
+#define AXI2MC_AXI_W_WLAST_ROW                  0
+#define AXI2MC_AXI_W_WLAST_DISABLED                     _MK_ENUM_CONST(0)
+#define AXI2MC_AXI_W_WLAST_ENABLED                      _MK_ENUM_CONST(1)
+
+
+// Packet AXI2MC_AXI_B
+#define AXI2MC_AXI_B_SIZE 15
+
+#define AXI2MC_AXI_B_BID_SHIFT                  _MK_SHIFT_CONST(0)
+#define AXI2MC_AXI_B_BID_FIELD                  (_MK_MASK_CONST(0x1fff) << AXI2MC_AXI_B_BID_SHIFT)
+#define AXI2MC_AXI_B_BID_RANGE                  _MK_SHIFT_CONST(12):_MK_SHIFT_CONST(0)
+#define AXI2MC_AXI_B_BID_ROW                    0
+
+#define AXI2MC_AXI_B_BRESP_SHIFT                        _MK_SHIFT_CONST(13)
+#define AXI2MC_AXI_B_BRESP_FIELD                        (_MK_MASK_CONST(0x3) << AXI2MC_AXI_B_BRESP_SHIFT)
+#define AXI2MC_AXI_B_BRESP_RANGE                        _MK_SHIFT_CONST(14):_MK_SHIFT_CONST(13)
+#define AXI2MC_AXI_B_BRESP_ROW                  0
+#define AXI2MC_AXI_B_BRESP_OKAY                 _MK_ENUM_CONST(0)
+#define AXI2MC_AXI_B_BRESP_EXOKAY                       _MK_ENUM_CONST(1)
+#define AXI2MC_AXI_B_BRESP_SLVERR                       _MK_ENUM_CONST(2)
+#define AXI2MC_AXI_B_BRESP_DECERR                       _MK_ENUM_CONST(3)
+
+
+// Packet AXI2MC_AXI_R
+#define AXI2MC_AXI_R_SIZE 272
+
+#define AXI2MC_AXI_R_RDATA_SHIFT                        _MK_SHIFT_CONST(0)
+#define AXI2MC_AXI_R_RDATA_FIELD                        (_MK_MASK_CONST(0xffffffff) << AXI2MC_AXI_R_RDATA_SHIFT)
+#define AXI2MC_AXI_R_RDATA_RANGE                        _MK_SHIFT_CONST(255):_MK_SHIFT_CONST(0)
+#define AXI2MC_AXI_R_RDATA_ROW                  0
+
+#define AXI2MC_AXI_R_RID_SHIFT                  _MK_SHIFT_CONST(256)
+#define AXI2MC_AXI_R_RID_FIELD                  (_MK_MASK_CONST(0x1fff) << AXI2MC_AXI_R_RID_SHIFT)
+#define AXI2MC_AXI_R_RID_RANGE                  _MK_SHIFT_CONST(268):_MK_SHIFT_CONST(256)
+#define AXI2MC_AXI_R_RID_ROW                    0
+
+#define AXI2MC_AXI_R_RRESP_SHIFT                        _MK_SHIFT_CONST(269)
+#define AXI2MC_AXI_R_RRESP_FIELD                        (_MK_MASK_CONST(0x3) << AXI2MC_AXI_R_RRESP_SHIFT)
+#define AXI2MC_AXI_R_RRESP_RANGE                        _MK_SHIFT_CONST(270):_MK_SHIFT_CONST(269)
+#define AXI2MC_AXI_R_RRESP_ROW                  0
+#define AXI2MC_AXI_R_RRESP_OKAY                 _MK_ENUM_CONST(0)
+#define AXI2MC_AXI_R_RRESP_EXOKAY                       _MK_ENUM_CONST(1)
+#define AXI2MC_AXI_R_RRESP_SLVERR                       _MK_ENUM_CONST(2)
+#define AXI2MC_AXI_R_RRESP_DECERR                       _MK_ENUM_CONST(3)
+
+#define AXI2MC_AXI_R_RLAST_SHIFT                        _MK_SHIFT_CONST(271)
+#define AXI2MC_AXI_R_RLAST_FIELD                        (_MK_MASK_CONST(0x1) << AXI2MC_AXI_R_RLAST_SHIFT)
+#define AXI2MC_AXI_R_RLAST_RANGE                        _MK_SHIFT_CONST(271):_MK_SHIFT_CONST(271)
+#define AXI2MC_AXI_R_RLAST_ROW                  0
+#define AXI2MC_AXI_R_RLAST_DISABLED                     _MK_ENUM_CONST(0)
+#define AXI2MC_AXI_R_RLAST_ENABLED                      _MK_ENUM_CONST(1)
+
+
+// Packet MC_AXI_RWREQ
+#define MC_AXI_RWREQ_SIZE 112
+
+#define MC_AXI_RWREQ_AADDR_SHIFT                        _MK_SHIFT_CONST(0)
+#define MC_AXI_RWREQ_AADDR_FIELD                        (_MK_MASK_CONST(0xffffffff) << MC_AXI_RWREQ_AADDR_SHIFT)
+#define MC_AXI_RWREQ_AADDR_RANGE                        _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define MC_AXI_RWREQ_AADDR_ROW                  0
+
+#define MC_AXI_RWREQ_AID_SHIFT                  _MK_SHIFT_CONST(32)
+#define MC_AXI_RWREQ_AID_FIELD                  (_MK_MASK_CONST(0x1fff) << MC_AXI_RWREQ_AID_SHIFT)
+#define MC_AXI_RWREQ_AID_RANGE                  _MK_SHIFT_CONST(44):_MK_SHIFT_CONST(32)
+#define MC_AXI_RWREQ_AID_ROW                    0
+
+#define MC_AXI_RWREQ_ALEN_SHIFT                 _MK_SHIFT_CONST(45)
+#define MC_AXI_RWREQ_ALEN_FIELD                 (_MK_MASK_CONST(0xf) << MC_AXI_RWREQ_ALEN_SHIFT)
+#define MC_AXI_RWREQ_ALEN_RANGE                 _MK_SHIFT_CONST(48):_MK_SHIFT_CONST(45)
+#define MC_AXI_RWREQ_ALEN_ROW                   0
+
+#define MC_AXI_RWREQ_ASIZE_SHIFT                        _MK_SHIFT_CONST(49)
+#define MC_AXI_RWREQ_ASIZE_FIELD                        (_MK_MASK_CONST(0x7) << MC_AXI_RWREQ_ASIZE_SHIFT)
+#define MC_AXI_RWREQ_ASIZE_RANGE                        _MK_SHIFT_CONST(51):_MK_SHIFT_CONST(49)
+#define MC_AXI_RWREQ_ASIZE_ROW                  2
+
+#define MC_AXI_RWREQ_ABURST_SHIFT                       _MK_SHIFT_CONST(52)
+#define MC_AXI_RWREQ_ABURST_FIELD                       (_MK_MASK_CONST(0x3) << MC_AXI_RWREQ_ABURST_SHIFT)
+#define MC_AXI_RWREQ_ABURST_RANGE                       _MK_SHIFT_CONST(53):_MK_SHIFT_CONST(52)
+#define MC_AXI_RWREQ_ABURST_ROW                 0
+#define MC_AXI_RWREQ_ABURST_FIXED                       _MK_ENUM_CONST(0)
+#define MC_AXI_RWREQ_ABURST_INCR                        _MK_ENUM_CONST(1)
+#define MC_AXI_RWREQ_ABURST_WRAP                        _MK_ENUM_CONST(2)
+#define MC_AXI_RWREQ_ABURST_RSVD                        _MK_ENUM_CONST(3)
+
+#define MC_AXI_RWREQ_ALOCK_SHIFT                        _MK_SHIFT_CONST(54)
+#define MC_AXI_RWREQ_ALOCK_FIELD                        (_MK_MASK_CONST(0x3) << MC_AXI_RWREQ_ALOCK_SHIFT)
+#define MC_AXI_RWREQ_ALOCK_RANGE                        _MK_SHIFT_CONST(55):_MK_SHIFT_CONST(54)
+#define MC_AXI_RWREQ_ALOCK_ROW                  0
+
+#define MC_AXI_RWREQ_ACACHE_SHIFT                       _MK_SHIFT_CONST(56)
+#define MC_AXI_RWREQ_ACACHE_FIELD                       (_MK_MASK_CONST(0xf) << MC_AXI_RWREQ_ACACHE_SHIFT)
+#define MC_AXI_RWREQ_ACACHE_RANGE                       _MK_SHIFT_CONST(59):_MK_SHIFT_CONST(56)
+#define MC_AXI_RWREQ_ACACHE_ROW                 0
+
+#define MC_AXI_RWREQ_APROT_SHIFT                        _MK_SHIFT_CONST(60)
+#define MC_AXI_RWREQ_APROT_FIELD                        (_MK_MASK_CONST(0x7) << MC_AXI_RWREQ_APROT_SHIFT)
+#define MC_AXI_RWREQ_APROT_RANGE                        _MK_SHIFT_CONST(62):_MK_SHIFT_CONST(60)
+#define MC_AXI_RWREQ_APROT_ROW                  0
+
+#define MC_AXI_RWREQ_ASB_SHIFT                  _MK_SHIFT_CONST(63)
+#define MC_AXI_RWREQ_ASB_FIELD                  (_MK_MASK_CONST(0x3) << MC_AXI_RWREQ_ASB_SHIFT)
+#define MC_AXI_RWREQ_ASB_RANGE                  _MK_SHIFT_CONST(64):_MK_SHIFT_CONST(63)
+#define MC_AXI_RWREQ_ASB_ROW                    0
+
+#define MC_AXI_RWREQ_ARW_SHIFT                  _MK_SHIFT_CONST(65)
+#define MC_AXI_RWREQ_ARW_FIELD                  (_MK_MASK_CONST(0x1) << MC_AXI_RWREQ_ARW_SHIFT)
+#define MC_AXI_RWREQ_ARW_RANGE                  _MK_SHIFT_CONST(65):_MK_SHIFT_CONST(65)
+#define MC_AXI_RWREQ_ARW_ROW                    0
+
+#define MC_AXI_RWREQ_ACT_AADDR_SHIFT                    _MK_SHIFT_CONST(66)
+#define MC_AXI_RWREQ_ACT_AADDR_FIELD                    (_MK_MASK_CONST(0xffffffff) << MC_AXI_RWREQ_ACT_AADDR_SHIFT)
+#define MC_AXI_RWREQ_ACT_AADDR_RANGE                    _MK_SHIFT_CONST(97):_MK_SHIFT_CONST(66)
+#define MC_AXI_RWREQ_ACT_AADDR_ROW                      0
+
+#define MC_AXI_RWREQ_ACT_ALEN_SHIFT                     _MK_SHIFT_CONST(98)
+#define MC_AXI_RWREQ_ACT_ALEN_FIELD                     (_MK_MASK_CONST(0xf) << MC_AXI_RWREQ_ACT_ALEN_SHIFT)
+#define MC_AXI_RWREQ_ACT_ALEN_RANGE                     _MK_SHIFT_CONST(101):_MK_SHIFT_CONST(98)
+#define MC_AXI_RWREQ_ACT_ALEN_ROW                       0
+
+#define MC_AXI_RWREQ_ACT_ASIZE_SHIFT                    _MK_SHIFT_CONST(102)
+#define MC_AXI_RWREQ_ACT_ASIZE_FIELD                    (_MK_MASK_CONST(0x7) << MC_AXI_RWREQ_ACT_ASIZE_SHIFT)
+#define MC_AXI_RWREQ_ACT_ASIZE_RANGE                    _MK_SHIFT_CONST(104):_MK_SHIFT_CONST(102)
+#define MC_AXI_RWREQ_ACT_ASIZE_ROW                      0
+
+#define MC_AXI_RWREQ_DOUBLEREQ_SHIFT                    _MK_SHIFT_CONST(105)
+#define MC_AXI_RWREQ_DOUBLEREQ_FIELD                    (_MK_MASK_CONST(0x1) << MC_AXI_RWREQ_DOUBLEREQ_SHIFT)
+#define MC_AXI_RWREQ_DOUBLEREQ_RANGE                    _MK_SHIFT_CONST(105):_MK_SHIFT_CONST(105)
+#define MC_AXI_RWREQ_DOUBLEREQ_ROW                      0
+
+#define MC_AXI_RWREQ_ILLEGALACC_SHIFT                   _MK_SHIFT_CONST(106)
+#define MC_AXI_RWREQ_ILLEGALACC_FIELD                   (_MK_MASK_CONST(0x1) << MC_AXI_RWREQ_ILLEGALACC_SHIFT)
+#define MC_AXI_RWREQ_ILLEGALACC_RANGE                   _MK_SHIFT_CONST(106):_MK_SHIFT_CONST(106)
+#define MC_AXI_RWREQ_ILLEGALACC_ROW                     0
+
+#define MC_AXI_RWREQ_TAG_SHIFT                  _MK_SHIFT_CONST(107)
+#define MC_AXI_RWREQ_TAG_FIELD                  (_MK_MASK_CONST(0x1f) << MC_AXI_RWREQ_TAG_SHIFT)
+#define MC_AXI_RWREQ_TAG_RANGE                  _MK_SHIFT_CONST(111):_MK_SHIFT_CONST(107)
+#define MC_AXI_RWREQ_TAG_ROW                    0
+
+
+// Packet CSR_C2MC_RESET
+#define CSR_C2MC_RESET_SIZE 1
+
+#define CSR_C2MC_RESET_RSTN_SHIFT                       _MK_SHIFT_CONST(0)
+#define CSR_C2MC_RESET_RSTN_FIELD                       (_MK_MASK_CONST(0x1) << CSR_C2MC_RESET_RSTN_SHIFT)
+#define CSR_C2MC_RESET_RSTN_RANGE                       _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CSR_C2MC_RESET_RSTN_ROW                 0
+
+
+// Packet CSR_C2MC_REQ
+#define CSR_C2MC_REQ_SIZE 32
+
+#define CSR_C2MC_REQ_ADR_SHIFT                  _MK_SHIFT_CONST(0)
+#define CSR_C2MC_REQ_ADR_FIELD                  (_MK_MASK_CONST(0xffffffff) << CSR_C2MC_REQ_ADR_SHIFT)
+#define CSR_C2MC_REQ_ADR_RANGE                  _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CSR_C2MC_REQ_ADR_ROW                    0
+
+
+// Packet CSR_C2MC_SIZE
+#define CSR_C2MC_SIZE_SIZE 1
+
+#define CSR_C2MC_SIZE_SIZE_SHIFT                        _MK_SHIFT_CONST(0)
+#define CSR_C2MC_SIZE_SIZE_FIELD                        (_MK_MASK_CONST(0x1) << CSR_C2MC_SIZE_SIZE_SHIFT)
+#define CSR_C2MC_SIZE_SIZE_RANGE                        _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CSR_C2MC_SIZE_SIZE_ROW                  0
+
+
+// Packet CSR_C2MC_SECURE
+#define CSR_C2MC_SECURE_SIZE 1
+
+#define CSR_C2MC_SECURE_SECURE_SHIFT                    _MK_SHIFT_CONST(0)
+#define CSR_C2MC_SECURE_SECURE_FIELD                    (_MK_MASK_CONST(0x1) << CSR_C2MC_SECURE_SECURE_SHIFT)
+#define CSR_C2MC_SECURE_SECURE_RANGE                    _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CSR_C2MC_SECURE_SECURE_ROW                      0
+
+
+// Packet CSR_C2MC_TAG
+#define CSR_C2MC_TAG_SIZE 5
+
+#define CSR_C2MC_TAG_TAG_SHIFT                  _MK_SHIFT_CONST(0)
+#define CSR_C2MC_TAG_TAG_FIELD                  (_MK_MASK_CONST(0x1f) << CSR_C2MC_TAG_TAG_SHIFT)
+#define CSR_C2MC_TAG_TAG_RANGE                  _MK_SHIFT_CONST(4):_MK_SHIFT_CONST(0)
+#define CSR_C2MC_TAG_TAG_ROW                    0
+
+
+// Packet CSR_C2MC_BP_REQ
+#define CSR_C2MC_BP_REQ_SIZE 48
+
+#define CSR_C2MC_BP_REQ_BASEADR_SHIFT                   _MK_SHIFT_CONST(0)
+#define CSR_C2MC_BP_REQ_BASEADR_FIELD                   (_MK_MASK_CONST(0xffffffff) << CSR_C2MC_BP_REQ_BASEADR_SHIFT)
+#define CSR_C2MC_BP_REQ_BASEADR_RANGE                   _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CSR_C2MC_BP_REQ_BASEADR_ROW                     0
+
+#define CSR_C2MC_BP_REQ_PITCH_SHIFT                     _MK_SHIFT_CONST(32)
+#define CSR_C2MC_BP_REQ_PITCH_FIELD                     (_MK_MASK_CONST(0xffff) << CSR_C2MC_BP_REQ_PITCH_SHIFT)
+#define CSR_C2MC_BP_REQ_PITCH_RANGE                     _MK_SHIFT_CONST(47):_MK_SHIFT_CONST(32)
+#define CSR_C2MC_BP_REQ_PITCH_ROW                       0
+
+
+// Packet CSR_C2MC_ADRXY
+#define CSR_C2MC_ADRXY_SIZE 30
+
+#define CSR_C2MC_ADRXY_OFFX_SHIFT                       _MK_SHIFT_CONST(0)
+#define CSR_C2MC_ADRXY_OFFX_FIELD                       (_MK_MASK_CONST(0xffff) << CSR_C2MC_ADRXY_OFFX_SHIFT)
+#define CSR_C2MC_ADRXY_OFFX_RANGE                       _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(0)
+#define CSR_C2MC_ADRXY_OFFX_ROW                 0
+
+#define CSR_C2MC_ADRXY_OFFY_SHIFT                       _MK_SHIFT_CONST(16)
+#define CSR_C2MC_ADRXY_OFFY_FIELD                       (_MK_MASK_CONST(0x3fff) << CSR_C2MC_ADRXY_OFFY_SHIFT)
+#define CSR_C2MC_ADRXY_OFFY_RANGE                       _MK_SHIFT_CONST(29):_MK_SHIFT_CONST(16)
+#define CSR_C2MC_ADRXY_OFFY_ROW                 0
+
+
+// Packet CSR_C2MC_TILE
+#define CSR_C2MC_TILE_SIZE 33
+
+#define CSR_C2MC_TILE_LINADR_SHIFT                      _MK_SHIFT_CONST(0)
+#define CSR_C2MC_TILE_LINADR_FIELD                      (_MK_MASK_CONST(0xffffffff) << CSR_C2MC_TILE_LINADR_SHIFT)
+#define CSR_C2MC_TILE_LINADR_RANGE                      _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CSR_C2MC_TILE_LINADR_ROW                        0
+
+#define CSR_C2MC_TILE_TMODE_SHIFT                       _MK_SHIFT_CONST(32)
+#define CSR_C2MC_TILE_TMODE_FIELD                       (_MK_MASK_CONST(0x1) << CSR_C2MC_TILE_TMODE_SHIFT)
+#define CSR_C2MC_TILE_TMODE_RANGE                       _MK_SHIFT_CONST(32):_MK_SHIFT_CONST(32)
+#define CSR_C2MC_TILE_TMODE_ROW                 0
+#define CSR_C2MC_TILE_TMODE_LINEAR                      _MK_ENUM_CONST(0)
+#define CSR_C2MC_TILE_TMODE_TILED                       _MK_ENUM_CONST(1)
+
+
+// Packet CSR_C2MC_RDI
+#define CSR_C2MC_RDI_SIZE 256
+
+#define CSR_C2MC_RDI_RDI_SHIFT                  _MK_SHIFT_CONST(0)
+#define CSR_C2MC_RDI_RDI_FIELD                  (_MK_MASK_CONST(0xffffffff) << CSR_C2MC_RDI_RDI_SHIFT)
+#define CSR_C2MC_RDI_RDI_RANGE                  _MK_SHIFT_CONST(255):_MK_SHIFT_CONST(0)
+#define CSR_C2MC_RDI_RDI_ROW                    0
+
+
+// Packet CSR_C2MC_HP
+#define CSR_C2MC_HP_SIZE 38
+
+// high-priority threshold
+#define CSR_C2MC_HP_HPTH_SHIFT                  _MK_SHIFT_CONST(0)
+#define CSR_C2MC_HP_HPTH_FIELD                  (_MK_MASK_CONST(0xffffffff) << CSR_C2MC_HP_HPTH_SHIFT)
+#define CSR_C2MC_HP_HPTH_RANGE                  _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CSR_C2MC_HP_HPTH_ROW                    0
+
+// high-priority timer
+#define CSR_C2MC_HP_HPTM_SHIFT                  _MK_SHIFT_CONST(32)
+#define CSR_C2MC_HP_HPTM_FIELD                  (_MK_MASK_CONST(0x3f) << CSR_C2MC_HP_HPTM_SHIFT)
+#define CSR_C2MC_HP_HPTM_RANGE                  _MK_SHIFT_CONST(37):_MK_SHIFT_CONST(32)
+#define CSR_C2MC_HP_HPTM_ROW                    0
+
+
+// Packet CSR_C2MC_HYST
+#define CSR_C2MC_HYST_SIZE 32
+
+#define CSR_C2MC_HYST_HYST_REQ_TM_SHIFT                 _MK_SHIFT_CONST(0)
+#define CSR_C2MC_HYST_HYST_REQ_TM_FIELD                 (_MK_MASK_CONST(0xff) << CSR_C2MC_HYST_HYST_REQ_TM_SHIFT)
+#define CSR_C2MC_HYST_HYST_REQ_TM_RANGE                 _MK_SHIFT_CONST(7):_MK_SHIFT_CONST(0)
+#define CSR_C2MC_HYST_HYST_REQ_TM_ROW                   0
+
+#define CSR_C2MC_HYST_DHYST_TM_SHIFT                    _MK_SHIFT_CONST(8)
+#define CSR_C2MC_HYST_DHYST_TM_FIELD                    (_MK_MASK_CONST(0xff) << CSR_C2MC_HYST_DHYST_TM_SHIFT)
+#define CSR_C2MC_HYST_DHYST_TM_RANGE                    _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(8)
+#define CSR_C2MC_HYST_DHYST_TM_ROW                      0
+
+#define CSR_C2MC_HYST_DHYST_TH_SHIFT                    _MK_SHIFT_CONST(16)
+#define CSR_C2MC_HYST_DHYST_TH_FIELD                    (_MK_MASK_CONST(0xff) << CSR_C2MC_HYST_DHYST_TH_SHIFT)
+#define CSR_C2MC_HYST_DHYST_TH_RANGE                    _MK_SHIFT_CONST(23):_MK_SHIFT_CONST(16)
+#define CSR_C2MC_HYST_DHYST_TH_ROW                      0
+
+#define CSR_C2MC_HYST_HYST_TM_SHIFT                     _MK_SHIFT_CONST(24)
+#define CSR_C2MC_HYST_HYST_TM_FIELD                     (_MK_MASK_CONST(0xf) << CSR_C2MC_HYST_HYST_TM_SHIFT)
+#define CSR_C2MC_HYST_HYST_TM_RANGE                     _MK_SHIFT_CONST(27):_MK_SHIFT_CONST(24)
+#define CSR_C2MC_HYST_HYST_TM_ROW                       0
+
+#define CSR_C2MC_HYST_HYST_REQ_TH_SHIFT                 _MK_SHIFT_CONST(28)
+#define CSR_C2MC_HYST_HYST_REQ_TH_FIELD                 (_MK_MASK_CONST(0x7) << CSR_C2MC_HYST_HYST_REQ_TH_SHIFT)
+#define CSR_C2MC_HYST_HYST_REQ_TH_RANGE                 _MK_SHIFT_CONST(30):_MK_SHIFT_CONST(28)
+#define CSR_C2MC_HYST_HYST_REQ_TH_ROW                   0
+
+#define CSR_C2MC_HYST_HYST_EN_SHIFT                     _MK_SHIFT_CONST(31)
+#define CSR_C2MC_HYST_HYST_EN_FIELD                     (_MK_MASK_CONST(0x1) << CSR_C2MC_HYST_HYST_EN_SHIFT)
+#define CSR_C2MC_HYST_HYST_EN_RANGE                     _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(31)
+#define CSR_C2MC_HYST_HYST_EN_ROW                       0
+
+
+// Packet CSW_C2MC_RESET
+#define CSW_C2MC_RESET_SIZE 1
+
+#define CSW_C2MC_RESET_RSTN_SHIFT                       _MK_SHIFT_CONST(0)
+#define CSW_C2MC_RESET_RSTN_FIELD                       (_MK_MASK_CONST(0x1) << CSW_C2MC_RESET_RSTN_SHIFT)
+#define CSW_C2MC_RESET_RSTN_RANGE                       _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CSW_C2MC_RESET_RSTN_ROW                 0
+
+
+// Packet CSW_C2MC_REQ
+#define CSW_C2MC_REQ_SIZE 321
+
+#define CSW_C2MC_REQ_ADR_SHIFT                  _MK_SHIFT_CONST(0)
+#define CSW_C2MC_REQ_ADR_FIELD                  (_MK_MASK_CONST(0xffffffff) << CSW_C2MC_REQ_ADR_SHIFT)
+#define CSW_C2MC_REQ_ADR_RANGE                  _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CSW_C2MC_REQ_ADR_ROW                    0
+
+#define CSW_C2MC_REQ_BE_SHIFT                   _MK_SHIFT_CONST(32)
+#define CSW_C2MC_REQ_BE_FIELD                   (_MK_MASK_CONST(0xffffffff) << CSW_C2MC_REQ_BE_SHIFT)
+#define CSW_C2MC_REQ_BE_RANGE                   _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(32)
+#define CSW_C2MC_REQ_BE_ROW                     0
+
+#define CSW_C2MC_REQ_WDO_SHIFT                  _MK_SHIFT_CONST(64)
+#define CSW_C2MC_REQ_WDO_FIELD                  (_MK_MASK_CONST(0xffffffff) << CSW_C2MC_REQ_WDO_SHIFT)
+#define CSW_C2MC_REQ_WDO_RANGE                  _MK_SHIFT_CONST(319):_MK_SHIFT_CONST(64)
+#define CSW_C2MC_REQ_WDO_ROW                    0
+
+#define CSW_C2MC_REQ_TAG_SHIFT                  _MK_SHIFT_CONST(320)
+#define CSW_C2MC_REQ_TAG_FIELD                  (_MK_MASK_CONST(0x1) << CSW_C2MC_REQ_TAG_SHIFT)
+#define CSW_C2MC_REQ_TAG_RANGE                  _MK_SHIFT_CONST(320):_MK_SHIFT_CONST(320)
+#define CSW_C2MC_REQ_TAG_ROW                    0
+
+
+// Packet CSW_C2MC_SECURE
+#define CSW_C2MC_SECURE_SIZE 1
+
+#define CSW_C2MC_SECURE_SECURE_SHIFT                    _MK_SHIFT_CONST(0)
+#define CSW_C2MC_SECURE_SECURE_FIELD                    (_MK_MASK_CONST(0x1) << CSW_C2MC_SECURE_SECURE_SHIFT)
+#define CSW_C2MC_SECURE_SECURE_RANGE                    _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CSW_C2MC_SECURE_SECURE_ROW                      0
+
+
+// Packet CSW_C2MC_BP_REQ
+#define CSW_C2MC_BP_REQ_SIZE 337
+
+#define CSW_C2MC_BP_REQ_BASEADR_SHIFT                   _MK_SHIFT_CONST(0)
+#define CSW_C2MC_BP_REQ_BASEADR_FIELD                   (_MK_MASK_CONST(0xffffffff) << CSW_C2MC_BP_REQ_BASEADR_SHIFT)
+#define CSW_C2MC_BP_REQ_BASEADR_RANGE                   _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CSW_C2MC_BP_REQ_BASEADR_ROW                     0
+
+#define CSW_C2MC_BP_REQ_PITCH_SHIFT                     _MK_SHIFT_CONST(32)
+#define CSW_C2MC_BP_REQ_PITCH_FIELD                     (_MK_MASK_CONST(0xffff) << CSW_C2MC_BP_REQ_PITCH_SHIFT)
+#define CSW_C2MC_BP_REQ_PITCH_RANGE                     _MK_SHIFT_CONST(47):_MK_SHIFT_CONST(32)
+#define CSW_C2MC_BP_REQ_PITCH_ROW                       0
+
+#define CSW_C2MC_BP_REQ_BE_SHIFT                        _MK_SHIFT_CONST(48)
+#define CSW_C2MC_BP_REQ_BE_FIELD                        (_MK_MASK_CONST(0xffffffff) << CSW_C2MC_BP_REQ_BE_SHIFT)
+#define CSW_C2MC_BP_REQ_BE_RANGE                        _MK_SHIFT_CONST(79):_MK_SHIFT_CONST(48)
+#define CSW_C2MC_BP_REQ_BE_ROW                  0
+
+#define CSW_C2MC_BP_REQ_WDO_SHIFT                       _MK_SHIFT_CONST(80)
+#define CSW_C2MC_BP_REQ_WDO_FIELD                       (_MK_MASK_CONST(0xffffffff) << CSW_C2MC_BP_REQ_WDO_SHIFT)
+#define CSW_C2MC_BP_REQ_WDO_RANGE                       _MK_SHIFT_CONST(335):_MK_SHIFT_CONST(80)
+#define CSW_C2MC_BP_REQ_WDO_ROW                 0
+
+#define CSW_C2MC_BP_REQ_TAG_SHIFT                       _MK_SHIFT_CONST(336)
+#define CSW_C2MC_BP_REQ_TAG_FIELD                       (_MK_MASK_CONST(0x1) << CSW_C2MC_BP_REQ_TAG_SHIFT)
+#define CSW_C2MC_BP_REQ_TAG_RANGE                       _MK_SHIFT_CONST(336):_MK_SHIFT_CONST(336)
+#define CSW_C2MC_BP_REQ_TAG_ROW                 0
+
+
+// Packet CSW_C2MC_ADRXY
+#define CSW_C2MC_ADRXY_SIZE 30
+
+#define CSW_C2MC_ADRXY_OFFX_SHIFT                       _MK_SHIFT_CONST(0)
+#define CSW_C2MC_ADRXY_OFFX_FIELD                       (_MK_MASK_CONST(0xffff) << CSW_C2MC_ADRXY_OFFX_SHIFT)
+#define CSW_C2MC_ADRXY_OFFX_RANGE                       _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(0)
+#define CSW_C2MC_ADRXY_OFFX_ROW                 0
+
+#define CSW_C2MC_ADRXY_OFFY_SHIFT                       _MK_SHIFT_CONST(16)
+#define CSW_C2MC_ADRXY_OFFY_FIELD                       (_MK_MASK_CONST(0x3fff) << CSW_C2MC_ADRXY_OFFY_SHIFT)
+#define CSW_C2MC_ADRXY_OFFY_RANGE                       _MK_SHIFT_CONST(29):_MK_SHIFT_CONST(16)
+#define CSW_C2MC_ADRXY_OFFY_ROW                 0
+
+
+// Packet CSW_C2MC_TILE
+#define CSW_C2MC_TILE_SIZE 33
+
+#define CSW_C2MC_TILE_LINADR_SHIFT                      _MK_SHIFT_CONST(0)
+#define CSW_C2MC_TILE_LINADR_FIELD                      (_MK_MASK_CONST(0xffffffff) << CSW_C2MC_TILE_LINADR_SHIFT)
+#define CSW_C2MC_TILE_LINADR_RANGE                      _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CSW_C2MC_TILE_LINADR_ROW                        0
+
+#define CSW_C2MC_TILE_TMODE_SHIFT                       _MK_SHIFT_CONST(32)
+#define CSW_C2MC_TILE_TMODE_FIELD                       (_MK_MASK_CONST(0x1) << CSW_C2MC_TILE_TMODE_SHIFT)
+#define CSW_C2MC_TILE_TMODE_RANGE                       _MK_SHIFT_CONST(32):_MK_SHIFT_CONST(32)
+#define CSW_C2MC_TILE_TMODE_ROW                 0
+#define CSW_C2MC_TILE_TMODE_LINEAR                      _MK_ENUM_CONST(0)
+#define CSW_C2MC_TILE_TMODE_TILED                       _MK_ENUM_CONST(1)
+
+
+// Packet CSW_C2MC_XDI
+#define CSW_C2MC_XDI_SIZE 32
+
+// sometimes fake data
+#define CSW_C2MC_XDI_XDI_SHIFT                  _MK_SHIFT_CONST(0)
+#define CSW_C2MC_XDI_XDI_FIELD                  (_MK_MASK_CONST(0xffffffff) << CSW_C2MC_XDI_XDI_SHIFT)
+#define CSW_C2MC_XDI_XDI_RANGE                  _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CSW_C2MC_XDI_XDI_ROW                    0
+
+
+// Packet CSW_C2MC_HP
+#define CSW_C2MC_HP_SIZE 32
+
+// high-priority threshold
+#define CSW_C2MC_HP_HPTH_SHIFT                  _MK_SHIFT_CONST(0)
+#define CSW_C2MC_HP_HPTH_FIELD                  (_MK_MASK_CONST(0xffffffff) << CSW_C2MC_HP_HPTH_SHIFT)
+#define CSW_C2MC_HP_HPTH_RANGE                  _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CSW_C2MC_HP_HPTH_ROW                    0
+
+
+// Packet CSW_C2MC_WCOAL
+#define CSW_C2MC_WCOAL_SIZE 32
+
+// write-coalescing time-out
+#define CSW_C2MC_WCOAL_WCOALTM_SHIFT                    _MK_SHIFT_CONST(0)
+#define CSW_C2MC_WCOAL_WCOALTM_FIELD                    (_MK_MASK_CONST(0xffffffff) << CSW_C2MC_WCOAL_WCOALTM_SHIFT)
+#define CSW_C2MC_WCOAL_WCOALTM_RANGE                    _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CSW_C2MC_WCOAL_WCOALTM_ROW                      0
+
+
+// Packet CSW_C2MC_HYST
+#define CSW_C2MC_HYST_SIZE 32
+
+// hysteresis control register
+#define CSW_C2MC_HYST_HYST_SHIFT                        _MK_SHIFT_CONST(0)
+#define CSW_C2MC_HYST_HYST_FIELD                        (_MK_MASK_CONST(0xffffffff) << CSW_C2MC_HYST_HYST_SHIFT)
+#define CSW_C2MC_HYST_HYST_RANGE                        _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CSW_C2MC_HYST_HYST_ROW                  0
+
+
+// Packet CBR_C2MC_RESET
+#define CBR_C2MC_RESET_SIZE 1
+
+#define CBR_C2MC_RESET_RSTN_SHIFT                       _MK_SHIFT_CONST(0)
+#define CBR_C2MC_RESET_RSTN_FIELD                       (_MK_MASK_CONST(0x1) << CBR_C2MC_RESET_RSTN_SHIFT)
+#define CBR_C2MC_RESET_RSTN_RANGE                       _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CBR_C2MC_RESET_RSTN_ROW                 0
+
+
+// Packet CBR_C2MC_REQP
+#define CBR_C2MC_REQP_SIZE 263
+
+#define CBR_C2MC_REQP_ADR_SHIFT                 _MK_SHIFT_CONST(0)
+#define CBR_C2MC_REQP_ADR_FIELD                 (_MK_MASK_CONST(0xffffffff) << CBR_C2MC_REQP_ADR_SHIFT)
+#define CBR_C2MC_REQP_ADR_RANGE                 _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CBR_C2MC_REQP_ADR_ROW                   0
+
+#define CBR_C2MC_REQP_ADRU_SHIFT                        _MK_SHIFT_CONST(32)
+#define CBR_C2MC_REQP_ADRU_FIELD                        (_MK_MASK_CONST(0xffffffff) << CBR_C2MC_REQP_ADRU_SHIFT)
+#define CBR_C2MC_REQP_ADRU_RANGE                        _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(32)
+#define CBR_C2MC_REQP_ADRU_ROW                  0
+
+#define CBR_C2MC_REQP_ADRV_SHIFT                        _MK_SHIFT_CONST(64)
+#define CBR_C2MC_REQP_ADRV_FIELD                        (_MK_MASK_CONST(0xffffffff) << CBR_C2MC_REQP_ADRV_SHIFT)
+#define CBR_C2MC_REQP_ADRV_RANGE                        _MK_SHIFT_CONST(95):_MK_SHIFT_CONST(64)
+#define CBR_C2MC_REQP_ADRV_ROW                  0
+
+#define CBR_C2MC_REQP_LS_SHIFT                  _MK_SHIFT_CONST(96)
+#define CBR_C2MC_REQP_LS_FIELD                  (_MK_MASK_CONST(0xffffffff) << CBR_C2MC_REQP_LS_SHIFT)
+#define CBR_C2MC_REQP_LS_RANGE                  _MK_SHIFT_CONST(127):_MK_SHIFT_CONST(96)
+#define CBR_C2MC_REQP_LS_ROW                    0
+
+#define CBR_C2MC_REQP_LSUV_SHIFT                        _MK_SHIFT_CONST(128)
+#define CBR_C2MC_REQP_LSUV_FIELD                        (_MK_MASK_CONST(0xffffffff) << CBR_C2MC_REQP_LSUV_SHIFT)
+#define CBR_C2MC_REQP_LSUV_RANGE                        _MK_SHIFT_CONST(159):_MK_SHIFT_CONST(128)
+#define CBR_C2MC_REQP_LSUV_ROW                  0
+
+#define CBR_C2MC_REQP_HS_SHIFT                  _MK_SHIFT_CONST(160)
+#define CBR_C2MC_REQP_HS_FIELD                  (_MK_MASK_CONST(0xffffffff) << CBR_C2MC_REQP_HS_SHIFT)
+#define CBR_C2MC_REQP_HS_RANGE                  _MK_SHIFT_CONST(191):_MK_SHIFT_CONST(160)
+#define CBR_C2MC_REQP_HS_ROW                    0
+
+#define CBR_C2MC_REQP_VS_SHIFT                  _MK_SHIFT_CONST(192)
+#define CBR_C2MC_REQP_VS_FIELD                  (_MK_MASK_CONST(0xffffffff) << CBR_C2MC_REQP_VS_SHIFT)
+#define CBR_C2MC_REQP_VS_RANGE                  _MK_SHIFT_CONST(223):_MK_SHIFT_CONST(192)
+#define CBR_C2MC_REQP_VS_ROW                    0
+
+#define CBR_C2MC_REQP_DL_SHIFT                  _MK_SHIFT_CONST(224)
+#define CBR_C2MC_REQP_DL_FIELD                  (_MK_MASK_CONST(0xffffffff) << CBR_C2MC_REQP_DL_SHIFT)
+#define CBR_C2MC_REQP_DL_RANGE                  _MK_SHIFT_CONST(255):_MK_SHIFT_CONST(224)
+#define CBR_C2MC_REQP_DL_ROW                    0
+
+#define CBR_C2MC_REQP_HD_SHIFT                  _MK_SHIFT_CONST(256)
+#define CBR_C2MC_REQP_HD_FIELD                  (_MK_MASK_CONST(0x1) << CBR_C2MC_REQP_HD_SHIFT)
+#define CBR_C2MC_REQP_HD_RANGE                  _MK_SHIFT_CONST(256):_MK_SHIFT_CONST(256)
+#define CBR_C2MC_REQP_HD_ROW                    0
+
+#define CBR_C2MC_REQP_VD_SHIFT                  _MK_SHIFT_CONST(257)
+#define CBR_C2MC_REQP_VD_FIELD                  (_MK_MASK_CONST(0x1) << CBR_C2MC_REQP_VD_SHIFT)
+#define CBR_C2MC_REQP_VD_RANGE                  _MK_SHIFT_CONST(257):_MK_SHIFT_CONST(257)
+#define CBR_C2MC_REQP_VD_ROW                    0
+
+#define CBR_C2MC_REQP_VX2_SHIFT                 _MK_SHIFT_CONST(258)
+#define CBR_C2MC_REQP_VX2_FIELD                 (_MK_MASK_CONST(0x1) << CBR_C2MC_REQP_VX2_SHIFT)
+#define CBR_C2MC_REQP_VX2_RANGE                 _MK_SHIFT_CONST(258):_MK_SHIFT_CONST(258)
+#define CBR_C2MC_REQP_VX2_ROW                   0
+
+#define CBR_C2MC_REQP_LP_SHIFT                  _MK_SHIFT_CONST(259)
+#define CBR_C2MC_REQP_LP_FIELD                  (_MK_MASK_CONST(0x1) << CBR_C2MC_REQP_LP_SHIFT)
+#define CBR_C2MC_REQP_LP_RANGE                  _MK_SHIFT_CONST(259):_MK_SHIFT_CONST(259)
+#define CBR_C2MC_REQP_LP_ROW                    0
+
+#define CBR_C2MC_REQP_YUV_SHIFT                 _MK_SHIFT_CONST(260)
+#define CBR_C2MC_REQP_YUV_FIELD                 (_MK_MASK_CONST(0x7) << CBR_C2MC_REQP_YUV_SHIFT)
+#define CBR_C2MC_REQP_YUV_RANGE                 _MK_SHIFT_CONST(262):_MK_SHIFT_CONST(260)
+#define CBR_C2MC_REQP_YUV_ROW                   0
+
+
+// Packet CBR_C2MC_SECURE
+#define CBR_C2MC_SECURE_SIZE 1
+
+#define CBR_C2MC_SECURE_SECURE_SHIFT                    _MK_SHIFT_CONST(0)
+#define CBR_C2MC_SECURE_SECURE_FIELD                    (_MK_MASK_CONST(0x1) << CBR_C2MC_SECURE_SECURE_SHIFT)
+#define CBR_C2MC_SECURE_SECURE_RANGE                    _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CBR_C2MC_SECURE_SECURE_ROW                      0
+
+
+// Packet CBR_C2MC_ADRXY
+#define CBR_C2MC_ADRXY_SIZE 44
+
+#define CBR_C2MC_ADRXY_OFFX_SHIFT                       _MK_SHIFT_CONST(0)
+#define CBR_C2MC_ADRXY_OFFX_FIELD                       (_MK_MASK_CONST(0xffff) << CBR_C2MC_ADRXY_OFFX_SHIFT)
+#define CBR_C2MC_ADRXY_OFFX_RANGE                       _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(0)
+#define CBR_C2MC_ADRXY_OFFX_ROW                 0
+
+#define CBR_C2MC_ADRXY_OFFY_SHIFT                       _MK_SHIFT_CONST(16)
+#define CBR_C2MC_ADRXY_OFFY_FIELD                       (_MK_MASK_CONST(0x3fff) << CBR_C2MC_ADRXY_OFFY_SHIFT)
+#define CBR_C2MC_ADRXY_OFFY_RANGE                       _MK_SHIFT_CONST(29):_MK_SHIFT_CONST(16)
+#define CBR_C2MC_ADRXY_OFFY_ROW                 0
+
+#define CBR_C2MC_ADRXY_OFFYUV_SHIFT                     _MK_SHIFT_CONST(30)
+#define CBR_C2MC_ADRXY_OFFYUV_FIELD                     (_MK_MASK_CONST(0x3fff) << CBR_C2MC_ADRXY_OFFYUV_SHIFT)
+#define CBR_C2MC_ADRXY_OFFYUV_RANGE                     _MK_SHIFT_CONST(43):_MK_SHIFT_CONST(30)
+#define CBR_C2MC_ADRXY_OFFYUV_ROW                       0
+
+
+// Packet CBR_C2MC_TILE
+#define CBR_C2MC_TILE_SIZE 98
+
+#define CBR_C2MC_TILE_LINADR_SHIFT                      _MK_SHIFT_CONST(0)
+#define CBR_C2MC_TILE_LINADR_FIELD                      (_MK_MASK_CONST(0xffffffff) << CBR_C2MC_TILE_LINADR_SHIFT)
+#define CBR_C2MC_TILE_LINADR_RANGE                      _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CBR_C2MC_TILE_LINADR_ROW                        0
+
+#define CBR_C2MC_TILE_LINADRU_SHIFT                     _MK_SHIFT_CONST(32)
+#define CBR_C2MC_TILE_LINADRU_FIELD                     (_MK_MASK_CONST(0xffffffff) << CBR_C2MC_TILE_LINADRU_SHIFT)
+#define CBR_C2MC_TILE_LINADRU_RANGE                     _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(32)
+#define CBR_C2MC_TILE_LINADRU_ROW                       0
+
+#define CBR_C2MC_TILE_LINADRV_SHIFT                     _MK_SHIFT_CONST(64)
+#define CBR_C2MC_TILE_LINADRV_FIELD                     (_MK_MASK_CONST(0xffffffff) << CBR_C2MC_TILE_LINADRV_SHIFT)
+#define CBR_C2MC_TILE_LINADRV_RANGE                     _MK_SHIFT_CONST(95):_MK_SHIFT_CONST(64)
+#define CBR_C2MC_TILE_LINADRV_ROW                       0
+
+#define CBR_C2MC_TILE_TMODE_SHIFT                       _MK_SHIFT_CONST(96)
+#define CBR_C2MC_TILE_TMODE_FIELD                       (_MK_MASK_CONST(0x1) << CBR_C2MC_TILE_TMODE_SHIFT)
+#define CBR_C2MC_TILE_TMODE_RANGE                       _MK_SHIFT_CONST(96):_MK_SHIFT_CONST(96)
+#define CBR_C2MC_TILE_TMODE_ROW                 0
+#define CBR_C2MC_TILE_TMODE_LINEAR                      _MK_ENUM_CONST(0)
+#define CBR_C2MC_TILE_TMODE_TILED                       _MK_ENUM_CONST(1)
+
+#define CBR_C2MC_TILE_TMODEUV_SHIFT                     _MK_SHIFT_CONST(97)
+#define CBR_C2MC_TILE_TMODEUV_FIELD                     (_MK_MASK_CONST(0x1) << CBR_C2MC_TILE_TMODEUV_SHIFT)
+#define CBR_C2MC_TILE_TMODEUV_RANGE                     _MK_SHIFT_CONST(97):_MK_SHIFT_CONST(97)
+#define CBR_C2MC_TILE_TMODEUV_ROW                       0
+#define CBR_C2MC_TILE_TMODEUV_LINEAR                    _MK_ENUM_CONST(0)
+#define CBR_C2MC_TILE_TMODEUV_TILED                     _MK_ENUM_CONST(1)
+
+
+// Packet CBR_C2MC_RDYP
+#define CBR_C2MC_RDYP_SIZE 1
+
+// fake data
+#define CBR_C2MC_RDYP_RDYP_SHIFT                        _MK_SHIFT_CONST(0)
+#define CBR_C2MC_RDYP_RDYP_FIELD                        (_MK_MASK_CONST(0x1) << CBR_C2MC_RDYP_RDYP_SHIFT)
+#define CBR_C2MC_RDYP_RDYP_RANGE                        _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CBR_C2MC_RDYP_RDYP_ROW                  0
+
+
+// Packet CBR_C2MC_OUTSTD
+#define CBR_C2MC_OUTSTD_SIZE 1
+
+#define CBR_C2MC_OUTSTD_OUTSTD_SHIFT                    _MK_SHIFT_CONST(0)
+#define CBR_C2MC_OUTSTD_OUTSTD_FIELD                    (_MK_MASK_CONST(0x1) << CBR_C2MC_OUTSTD_OUTSTD_SHIFT)
+#define CBR_C2MC_OUTSTD_OUTSTD_RANGE                    _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CBR_C2MC_OUTSTD_OUTSTD_ROW                      0
+
+
+// Packet CBR_C2MC_STOP
+#define CBR_C2MC_STOP_SIZE 1
+
+#define CBR_C2MC_STOP_STOP_SHIFT                        _MK_SHIFT_CONST(0)
+#define CBR_C2MC_STOP_STOP_FIELD                        (_MK_MASK_CONST(0x1) << CBR_C2MC_STOP_STOP_SHIFT)
+#define CBR_C2MC_STOP_STOP_RANGE                        _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CBR_C2MC_STOP_STOP_ROW                  0
+
+
+// Packet CBR_C2MC_RDI
+#define CBR_C2MC_RDI_SIZE 262
+
+#define CBR_C2MC_RDI_RDI_SHIFT                  _MK_SHIFT_CONST(0)
+#define CBR_C2MC_RDI_RDI_FIELD                  (_MK_MASK_CONST(0xffffffff) << CBR_C2MC_RDI_RDI_SHIFT)
+#define CBR_C2MC_RDI_RDI_RANGE                  _MK_SHIFT_CONST(255):_MK_SHIFT_CONST(0)
+#define CBR_C2MC_RDI_RDI_ROW                    0
+
+#define CBR_C2MC_RDI_RDILST_SHIFT                       _MK_SHIFT_CONST(256)
+#define CBR_C2MC_RDI_RDILST_FIELD                       (_MK_MASK_CONST(0x1) << CBR_C2MC_RDI_RDILST_SHIFT)
+#define CBR_C2MC_RDI_RDILST_RANGE                       _MK_SHIFT_CONST(256):_MK_SHIFT_CONST(256)
+#define CBR_C2MC_RDI_RDILST_ROW                 0
+
+#define CBR_C2MC_RDI_RDINB_SHIFT                        _MK_SHIFT_CONST(257)
+#define CBR_C2MC_RDI_RDINB_FIELD                        (_MK_MASK_CONST(0x1f) << CBR_C2MC_RDI_RDINB_SHIFT)
+#define CBR_C2MC_RDI_RDINB_RANGE                        _MK_SHIFT_CONST(261):_MK_SHIFT_CONST(257)
+#define CBR_C2MC_RDI_RDINB_ROW                  0
+
+
+// Packet CBR_C2MC_DOREQ
+#define CBR_C2MC_DOREQ_SIZE 64
+
+#define CBR_C2MC_DOREQ_ADR_SHIFT                        _MK_SHIFT_CONST(0)
+#define CBR_C2MC_DOREQ_ADR_FIELD                        (_MK_MASK_CONST(0xffffffff) << CBR_C2MC_DOREQ_ADR_SHIFT)
+#define CBR_C2MC_DOREQ_ADR_RANGE                        _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CBR_C2MC_DOREQ_ADR_ROW                  0
+
+#define CBR_C2MC_DOREQ_LS_SHIFT                 _MK_SHIFT_CONST(32)
+#define CBR_C2MC_DOREQ_LS_FIELD                 (_MK_MASK_CONST(0xffffffff) << CBR_C2MC_DOREQ_LS_SHIFT)
+#define CBR_C2MC_DOREQ_LS_RANGE                 _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(32)
+#define CBR_C2MC_DOREQ_LS_ROW                   0
+
+
+// Packet CBR_C2MC_HP
+#define CBR_C2MC_HP_SIZE 71
+
+// high-priority threshold
+#define CBR_C2MC_HP_HPTH_SHIFT                  _MK_SHIFT_CONST(0)
+#define CBR_C2MC_HP_HPTH_FIELD                  (_MK_MASK_CONST(0xffffffff) << CBR_C2MC_HP_HPTH_SHIFT)
+#define CBR_C2MC_HP_HPTH_RANGE                  _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CBR_C2MC_HP_HPTH_ROW                    0
+
+// high-priority timer
+#define CBR_C2MC_HP_HPTM_SHIFT                  _MK_SHIFT_CONST(32)
+#define CBR_C2MC_HP_HPTM_FIELD                  (_MK_MASK_CONST(0x3f) << CBR_C2MC_HP_HPTM_SHIFT)
+#define CBR_C2MC_HP_HPTM_RANGE                  _MK_SHIFT_CONST(37):_MK_SHIFT_CONST(32)
+#define CBR_C2MC_HP_HPTM_ROW                    0
+
+// suppression - start of frame
+#define CBR_C2MC_HP_HPSOF_SHIFT                 _MK_SHIFT_CONST(38)
+#define CBR_C2MC_HP_HPSOF_FIELD                 (_MK_MASK_CONST(0x1) << CBR_C2MC_HP_HPSOF_SHIFT)
+#define CBR_C2MC_HP_HPSOF_RANGE                 _MK_SHIFT_CONST(38):_MK_SHIFT_CONST(38)
+#define CBR_C2MC_HP_HPSOF_ROW                   0
+
+// suppression - cycles per word
+#define CBR_C2MC_HP_HPCPW_SHIFT                 _MK_SHIFT_CONST(39)
+#define CBR_C2MC_HP_HPCPW_FIELD                 (_MK_MASK_CONST(0xffff) << CBR_C2MC_HP_HPCPW_SHIFT)
+#define CBR_C2MC_HP_HPCPW_RANGE                 _MK_SHIFT_CONST(54):_MK_SHIFT_CONST(39)
+#define CBR_C2MC_HP_HPCPW_ROW                   0
+
+// suppression - words per line
+#define CBR_C2MC_HP_HPCBNPW_SHIFT                       _MK_SHIFT_CONST(55)
+#define CBR_C2MC_HP_HPCBNPW_FIELD                       (_MK_MASK_CONST(0xffff) << CBR_C2MC_HP_HPCBNPW_SHIFT)
+#define CBR_C2MC_HP_HPCBNPW_RANGE                       _MK_SHIFT_CONST(70):_MK_SHIFT_CONST(55)
+#define CBR_C2MC_HP_HPCBNPW_ROW                 0
+
+
+// Packet CBR_C2MC_HYST
+#define CBR_C2MC_HYST_SIZE 32
+
+#define CBR_C2MC_HYST_HYST_REQ_TM_SHIFT                 _MK_SHIFT_CONST(0)
+#define CBR_C2MC_HYST_HYST_REQ_TM_FIELD                 (_MK_MASK_CONST(0xff) << CBR_C2MC_HYST_HYST_REQ_TM_SHIFT)
+#define CBR_C2MC_HYST_HYST_REQ_TM_RANGE                 _MK_SHIFT_CONST(7):_MK_SHIFT_CONST(0)
+#define CBR_C2MC_HYST_HYST_REQ_TM_ROW                   0
+
+#define CBR_C2MC_HYST_DHYST_TM_SHIFT                    _MK_SHIFT_CONST(8)
+#define CBR_C2MC_HYST_DHYST_TM_FIELD                    (_MK_MASK_CONST(0xff) << CBR_C2MC_HYST_DHYST_TM_SHIFT)
+#define CBR_C2MC_HYST_DHYST_TM_RANGE                    _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(8)
+#define CBR_C2MC_HYST_DHYST_TM_ROW                      0
+
+#define CBR_C2MC_HYST_DHYST_TH_SHIFT                    _MK_SHIFT_CONST(16)
+#define CBR_C2MC_HYST_DHYST_TH_FIELD                    (_MK_MASK_CONST(0xff) << CBR_C2MC_HYST_DHYST_TH_SHIFT)
+#define CBR_C2MC_HYST_DHYST_TH_RANGE                    _MK_SHIFT_CONST(23):_MK_SHIFT_CONST(16)
+#define CBR_C2MC_HYST_DHYST_TH_ROW                      0
+
+#define CBR_C2MC_HYST_HYST_TM_SHIFT                     _MK_SHIFT_CONST(24)
+#define CBR_C2MC_HYST_HYST_TM_FIELD                     (_MK_MASK_CONST(0xf) << CBR_C2MC_HYST_HYST_TM_SHIFT)
+#define CBR_C2MC_HYST_HYST_TM_RANGE                     _MK_SHIFT_CONST(27):_MK_SHIFT_CONST(24)
+#define CBR_C2MC_HYST_HYST_TM_ROW                       0
+
+#define CBR_C2MC_HYST_HYST_REQ_TH_SHIFT                 _MK_SHIFT_CONST(28)
+#define CBR_C2MC_HYST_HYST_REQ_TH_FIELD                 (_MK_MASK_CONST(0x7) << CBR_C2MC_HYST_HYST_REQ_TH_SHIFT)
+#define CBR_C2MC_HYST_HYST_REQ_TH_RANGE                 _MK_SHIFT_CONST(30):_MK_SHIFT_CONST(28)
+#define CBR_C2MC_HYST_HYST_REQ_TH_ROW                   0
+
+#define CBR_C2MC_HYST_HYST_EN_SHIFT                     _MK_SHIFT_CONST(31)
+#define CBR_C2MC_HYST_HYST_EN_FIELD                     (_MK_MASK_CONST(0x1) << CBR_C2MC_HYST_HYST_EN_SHIFT)
+#define CBR_C2MC_HYST_HYST_EN_RANGE                     _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(31)
+#define CBR_C2MC_HYST_HYST_EN_ROW                       0
+
+
+// Packet CBW_C2MC_RESET
+#define CBW_C2MC_RESET_SIZE 1
+
+#define CBW_C2MC_RESET_RSTN_SHIFT                       _MK_SHIFT_CONST(0)
+#define CBW_C2MC_RESET_RSTN_FIELD                       (_MK_MASK_CONST(0x1) << CBW_C2MC_RESET_RSTN_SHIFT)
+#define CBW_C2MC_RESET_RSTN_RANGE                       _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CBW_C2MC_RESET_RSTN_ROW                 0
+
+
+// Packet CBW_C2MC_REQP
+#define CBW_C2MC_REQP_SIZE 134
+
+#define CBW_C2MC_REQP_ADR_SHIFT                 _MK_SHIFT_CONST(0)
+#define CBW_C2MC_REQP_ADR_FIELD                 (_MK_MASK_CONST(0xffffffff) << CBW_C2MC_REQP_ADR_SHIFT)
+#define CBW_C2MC_REQP_ADR_RANGE                 _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CBW_C2MC_REQP_ADR_ROW                   0
+
+#define CBW_C2MC_REQP_LS_SHIFT                  _MK_SHIFT_CONST(32)
+#define CBW_C2MC_REQP_LS_FIELD                  (_MK_MASK_CONST(0xffffffff) << CBW_C2MC_REQP_LS_SHIFT)
+#define CBW_C2MC_REQP_LS_RANGE                  _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(32)
+#define CBW_C2MC_REQP_LS_ROW                    0
+
+#define CBW_C2MC_REQP_HS_SHIFT                  _MK_SHIFT_CONST(64)
+#define CBW_C2MC_REQP_HS_FIELD                  (_MK_MASK_CONST(0xffffffff) << CBW_C2MC_REQP_HS_SHIFT)
+#define CBW_C2MC_REQP_HS_RANGE                  _MK_SHIFT_CONST(95):_MK_SHIFT_CONST(64)
+#define CBW_C2MC_REQP_HS_ROW                    0
+
+#define CBW_C2MC_REQP_VS_SHIFT                  _MK_SHIFT_CONST(96)
+#define CBW_C2MC_REQP_VS_FIELD                  (_MK_MASK_CONST(0xffffffff) << CBW_C2MC_REQP_VS_SHIFT)
+#define CBW_C2MC_REQP_VS_RANGE                  _MK_SHIFT_CONST(127):_MK_SHIFT_CONST(96)
+#define CBW_C2MC_REQP_VS_ROW                    0
+
+#define CBW_C2MC_REQP_HD_SHIFT                  _MK_SHIFT_CONST(128)
+#define CBW_C2MC_REQP_HD_FIELD                  (_MK_MASK_CONST(0x1) << CBW_C2MC_REQP_HD_SHIFT)
+#define CBW_C2MC_REQP_HD_RANGE                  _MK_SHIFT_CONST(128):_MK_SHIFT_CONST(128)
+#define CBW_C2MC_REQP_HD_ROW                    0
+
+#define CBW_C2MC_REQP_VD_SHIFT                  _MK_SHIFT_CONST(129)
+#define CBW_C2MC_REQP_VD_FIELD                  (_MK_MASK_CONST(0x1) << CBW_C2MC_REQP_VD_SHIFT)
+#define CBW_C2MC_REQP_VD_RANGE                  _MK_SHIFT_CONST(129):_MK_SHIFT_CONST(129)
+#define CBW_C2MC_REQP_VD_ROW                    0
+
+#define CBW_C2MC_REQP_BPP_SHIFT                 _MK_SHIFT_CONST(130)
+#define CBW_C2MC_REQP_BPP_FIELD                 (_MK_MASK_CONST(0x3) << CBW_C2MC_REQP_BPP_SHIFT)
+#define CBW_C2MC_REQP_BPP_RANGE                 _MK_SHIFT_CONST(131):_MK_SHIFT_CONST(130)
+#define CBW_C2MC_REQP_BPP_ROW                   0
+
+#define CBW_C2MC_REQP_XY_SHIFT                  _MK_SHIFT_CONST(132)
+#define CBW_C2MC_REQP_XY_FIELD                  (_MK_MASK_CONST(0x1) << CBW_C2MC_REQP_XY_SHIFT)
+#define CBW_C2MC_REQP_XY_RANGE                  _MK_SHIFT_CONST(132):_MK_SHIFT_CONST(132)
+#define CBW_C2MC_REQP_XY_ROW                    0
+
+#define CBW_C2MC_REQP_PK_SHIFT                  _MK_SHIFT_CONST(133)
+#define CBW_C2MC_REQP_PK_FIELD                  (_MK_MASK_CONST(0x1) << CBW_C2MC_REQP_PK_SHIFT)
+#define CBW_C2MC_REQP_PK_RANGE                  _MK_SHIFT_CONST(133):_MK_SHIFT_CONST(133)
+#define CBW_C2MC_REQP_PK_ROW                    0
+
+
+// Packet CBW_C2MC_SECURE
+#define CBW_C2MC_SECURE_SIZE 1
+
+#define CBW_C2MC_SECURE_SECURE_SHIFT                    _MK_SHIFT_CONST(0)
+#define CBW_C2MC_SECURE_SECURE_FIELD                    (_MK_MASK_CONST(0x1) << CBW_C2MC_SECURE_SECURE_SHIFT)
+#define CBW_C2MC_SECURE_SECURE_RANGE                    _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CBW_C2MC_SECURE_SECURE_ROW                      0
+
+
+// Packet CBW_C2MC_ADRXY
+#define CBW_C2MC_ADRXY_SIZE 30
+
+#define CBW_C2MC_ADRXY_OFFX_SHIFT                       _MK_SHIFT_CONST(0)
+#define CBW_C2MC_ADRXY_OFFX_FIELD                       (_MK_MASK_CONST(0xffff) << CBW_C2MC_ADRXY_OFFX_SHIFT)
+#define CBW_C2MC_ADRXY_OFFX_RANGE                       _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(0)
+#define CBW_C2MC_ADRXY_OFFX_ROW                 0
+
+#define CBW_C2MC_ADRXY_OFFY_SHIFT                       _MK_SHIFT_CONST(16)
+#define CBW_C2MC_ADRXY_OFFY_FIELD                       (_MK_MASK_CONST(0x3fff) << CBW_C2MC_ADRXY_OFFY_SHIFT)
+#define CBW_C2MC_ADRXY_OFFY_RANGE                       _MK_SHIFT_CONST(29):_MK_SHIFT_CONST(16)
+#define CBW_C2MC_ADRXY_OFFY_ROW                 0
+
+
+// Packet CBW_C2MC_TILE
+#define CBW_C2MC_TILE_SIZE 33
+
+#define CBW_C2MC_TILE_LINADR_SHIFT                      _MK_SHIFT_CONST(0)
+#define CBW_C2MC_TILE_LINADR_FIELD                      (_MK_MASK_CONST(0xffffffff) << CBW_C2MC_TILE_LINADR_SHIFT)
+#define CBW_C2MC_TILE_LINADR_RANGE                      _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CBW_C2MC_TILE_LINADR_ROW                        0
+
+#define CBW_C2MC_TILE_TMODE_SHIFT                       _MK_SHIFT_CONST(32)
+#define CBW_C2MC_TILE_TMODE_FIELD                       (_MK_MASK_CONST(0x1) << CBW_C2MC_TILE_TMODE_SHIFT)
+#define CBW_C2MC_TILE_TMODE_RANGE                       _MK_SHIFT_CONST(32):_MK_SHIFT_CONST(32)
+#define CBW_C2MC_TILE_TMODE_ROW                 0
+#define CBW_C2MC_TILE_TMODE_LINEAR                      _MK_ENUM_CONST(0)
+#define CBW_C2MC_TILE_TMODE_TILED                       _MK_ENUM_CONST(1)
+
+
+// Packet CBW_C2MC_RDYP
+#define CBW_C2MC_RDYP_SIZE 1
+
+// fake data
+#define CBW_C2MC_RDYP_RDYP_SHIFT                        _MK_SHIFT_CONST(0)
+#define CBW_C2MC_RDYP_RDYP_FIELD                        (_MK_MASK_CONST(0x1) << CBW_C2MC_RDYP_RDYP_SHIFT)
+#define CBW_C2MC_RDYP_RDYP_RANGE                        _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CBW_C2MC_RDYP_RDYP_ROW                  0
+
+
+// Packet CBW_C2MC_STOP
+#define CBW_C2MC_STOP_SIZE 1
+
+#define CBW_C2MC_STOP_STOP_SHIFT                        _MK_SHIFT_CONST(0)
+#define CBW_C2MC_STOP_STOP_FIELD                        (_MK_MASK_CONST(0x1) << CBW_C2MC_STOP_STOP_SHIFT)
+#define CBW_C2MC_STOP_STOP_RANGE                        _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CBW_C2MC_STOP_STOP_ROW                  0
+
+
+// Packet CBW_C2MC_XDI
+#define CBW_C2MC_XDI_SIZE 1
+
+// fake data
+#define CBW_C2MC_XDI_XDI_SHIFT                  _MK_SHIFT_CONST(0)
+#define CBW_C2MC_XDI_XDI_FIELD                  (_MK_MASK_CONST(0x1) << CBW_C2MC_XDI_XDI_SHIFT)
+#define CBW_C2MC_XDI_XDI_RANGE                  _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CBW_C2MC_XDI_XDI_ROW                    0
+
+
+// Packet CBW_C2MC_DOREQ
+#define CBW_C2MC_DOREQ_SIZE 321
+
+#define CBW_C2MC_DOREQ_ADR_SHIFT                        _MK_SHIFT_CONST(0)
+#define CBW_C2MC_DOREQ_ADR_FIELD                        (_MK_MASK_CONST(0xffffffff) << CBW_C2MC_DOREQ_ADR_SHIFT)
+#define CBW_C2MC_DOREQ_ADR_RANGE                        _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CBW_C2MC_DOREQ_ADR_ROW                  0
+
+#define CBW_C2MC_DOREQ_BE_SHIFT                 _MK_SHIFT_CONST(32)
+#define CBW_C2MC_DOREQ_BE_FIELD                 (_MK_MASK_CONST(0xffffffff) << CBW_C2MC_DOREQ_BE_SHIFT)
+#define CBW_C2MC_DOREQ_BE_RANGE                 _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(32)
+#define CBW_C2MC_DOREQ_BE_ROW                   0
+
+#define CBW_C2MC_DOREQ_WDO_SHIFT                        _MK_SHIFT_CONST(64)
+#define CBW_C2MC_DOREQ_WDO_FIELD                        (_MK_MASK_CONST(0xffffffff) << CBW_C2MC_DOREQ_WDO_SHIFT)
+#define CBW_C2MC_DOREQ_WDO_RANGE                        _MK_SHIFT_CONST(319):_MK_SHIFT_CONST(64)
+#define CBW_C2MC_DOREQ_WDO_ROW                  0
+
+#define CBW_C2MC_DOREQ_TAG_SHIFT                        _MK_SHIFT_CONST(320)
+#define CBW_C2MC_DOREQ_TAG_FIELD                        (_MK_MASK_CONST(0x1) << CBW_C2MC_DOREQ_TAG_SHIFT)
+#define CBW_C2MC_DOREQ_TAG_RANGE                        _MK_SHIFT_CONST(320):_MK_SHIFT_CONST(320)
+#define CBW_C2MC_DOREQ_TAG_ROW                  0
+
+
+// Packet CBW_C2MC_HP
+#define CBW_C2MC_HP_SIZE 32
+
+// high-priority threshold
+#define CBW_C2MC_HP_HPTH_SHIFT                  _MK_SHIFT_CONST(0)
+#define CBW_C2MC_HP_HPTH_FIELD                  (_MK_MASK_CONST(0xffffffff) << CBW_C2MC_HP_HPTH_SHIFT)
+#define CBW_C2MC_HP_HPTH_RANGE                  _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CBW_C2MC_HP_HPTH_ROW                    0
+
+
+// Packet CBW_C2MC_WCOAL
+#define CBW_C2MC_WCOAL_SIZE 32
+
+// write-coalescing time-out
+#define CBW_C2MC_WCOAL_WCOALTM_SHIFT                    _MK_SHIFT_CONST(0)
+#define CBW_C2MC_WCOAL_WCOALTM_FIELD                    (_MK_MASK_CONST(0xffffffff) << CBW_C2MC_WCOAL_WCOALTM_SHIFT)
+#define CBW_C2MC_WCOAL_WCOALTM_RANGE                    _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CBW_C2MC_WCOAL_WCOALTM_ROW                      0
+
+
+// Packet CBW_C2MC_HYST
+#define CBW_C2MC_HYST_SIZE 32
+
+#define CBW_C2MC_HYST_HYST_REQ_TM_SHIFT                 _MK_SHIFT_CONST(0)
+#define CBW_C2MC_HYST_HYST_REQ_TM_FIELD                 (_MK_MASK_CONST(0xfff) << CBW_C2MC_HYST_HYST_REQ_TM_SHIFT)
+#define CBW_C2MC_HYST_HYST_REQ_TM_RANGE                 _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(0)
+#define CBW_C2MC_HYST_HYST_REQ_TM_ROW                   0
+
+#define CBW_C2MC_HYST_HYST_REQ_TH_SHIFT                 _MK_SHIFT_CONST(28)
+#define CBW_C2MC_HYST_HYST_REQ_TH_FIELD                 (_MK_MASK_CONST(0x7) << CBW_C2MC_HYST_HYST_REQ_TH_SHIFT)
+#define CBW_C2MC_HYST_HYST_REQ_TH_RANGE                 _MK_SHIFT_CONST(30):_MK_SHIFT_CONST(28)
+#define CBW_C2MC_HYST_HYST_REQ_TH_ROW                   0
+
+#define CBW_C2MC_HYST_HYST_EN_SHIFT                     _MK_SHIFT_CONST(31)
+#define CBW_C2MC_HYST_HYST_EN_FIELD                     (_MK_MASK_CONST(0x1) << CBW_C2MC_HYST_HYST_EN_SHIFT)
+#define CBW_C2MC_HYST_HYST_EN_RANGE                     _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(31)
+#define CBW_C2MC_HYST_HYST_EN_ROW                       0
+
+
+// Packet CCR_C2MC_RESET
+#define CCR_C2MC_RESET_SIZE 1
+
+#define CCR_C2MC_RESET_RSTN_SHIFT                       _MK_SHIFT_CONST(0)
+#define CCR_C2MC_RESET_RSTN_FIELD                       (_MK_MASK_CONST(0x1) << CCR_C2MC_RESET_RSTN_SHIFT)
+#define CCR_C2MC_RESET_RSTN_RANGE                       _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CCR_C2MC_RESET_RSTN_ROW                 0
+
+
+// Packet CCR_C2MC_REQ
+#define CCR_C2MC_REQ_SIZE 101
+
+#define CCR_C2MC_REQ_ADR_SHIFT                  _MK_SHIFT_CONST(0)
+#define CCR_C2MC_REQ_ADR_FIELD                  (_MK_MASK_CONST(0xffffffff) << CCR_C2MC_REQ_ADR_SHIFT)
+#define CCR_C2MC_REQ_ADR_RANGE                  _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CCR_C2MC_REQ_ADR_ROW                    0
+
+#define CCR_C2MC_REQ_LS_SHIFT                   _MK_SHIFT_CONST(32)
+#define CCR_C2MC_REQ_LS_FIELD                   (_MK_MASK_CONST(0xffffffff) << CCR_C2MC_REQ_LS_SHIFT)
+#define CCR_C2MC_REQ_LS_RANGE                   _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(32)
+#define CCR_C2MC_REQ_LS_ROW                     0
+
+// HI is apparently a reserved keyword
+#define CCR_C2MC_REQ_HINC_SHIFT                 _MK_SHIFT_CONST(64)
+#define CCR_C2MC_REQ_HINC_FIELD                 (_MK_MASK_CONST(0xffffffff) << CCR_C2MC_REQ_HINC_SHIFT)
+#define CCR_C2MC_REQ_HINC_RANGE                 _MK_SHIFT_CONST(95):_MK_SHIFT_CONST(64)
+#define CCR_C2MC_REQ_HINC_ROW                   0
+
+#define CCR_C2MC_REQ_ACMD_SHIFT                 _MK_SHIFT_CONST(96)
+#define CCR_C2MC_REQ_ACMD_FIELD                 (_MK_MASK_CONST(0x3) << CCR_C2MC_REQ_ACMD_SHIFT)
+#define CCR_C2MC_REQ_ACMD_RANGE                 _MK_SHIFT_CONST(97):_MK_SHIFT_CONST(96)
+#define CCR_C2MC_REQ_ACMD_ROW                   0
+
+#define CCR_C2MC_REQ_LN_SHIFT                   _MK_SHIFT_CONST(98)
+#define CCR_C2MC_REQ_LN_FIELD                   (_MK_MASK_CONST(0x1) << CCR_C2MC_REQ_LN_SHIFT)
+#define CCR_C2MC_REQ_LN_RANGE                   _MK_SHIFT_CONST(98):_MK_SHIFT_CONST(98)
+#define CCR_C2MC_REQ_LN_ROW                     0
+
+#define CCR_C2MC_REQ_HD_SHIFT                   _MK_SHIFT_CONST(99)
+#define CCR_C2MC_REQ_HD_FIELD                   (_MK_MASK_CONST(0x1) << CCR_C2MC_REQ_HD_SHIFT)
+#define CCR_C2MC_REQ_HD_RANGE                   _MK_SHIFT_CONST(99):_MK_SHIFT_CONST(99)
+#define CCR_C2MC_REQ_HD_ROW                     0
+
+#define CCR_C2MC_REQ_VD_SHIFT                   _MK_SHIFT_CONST(100)
+#define CCR_C2MC_REQ_VD_FIELD                   (_MK_MASK_CONST(0x1) << CCR_C2MC_REQ_VD_SHIFT)
+#define CCR_C2MC_REQ_VD_RANGE                   _MK_SHIFT_CONST(100):_MK_SHIFT_CONST(100)
+#define CCR_C2MC_REQ_VD_ROW                     0
+
+
+// Packet CCR_C2MC_SECURE
+#define CCR_C2MC_SECURE_SIZE 1
+
+#define CCR_C2MC_SECURE_SECURE_SHIFT                    _MK_SHIFT_CONST(0)
+#define CCR_C2MC_SECURE_SECURE_FIELD                    (_MK_MASK_CONST(0x1) << CCR_C2MC_SECURE_SECURE_SHIFT)
+#define CCR_C2MC_SECURE_SECURE_RANGE                    _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CCR_C2MC_SECURE_SECURE_ROW                      0
+
+
+// Packet CCR_C2MC_RDI
+#define CCR_C2MC_RDI_SIZE 256
+
+#define CCR_C2MC_RDI_RDI_SHIFT                  _MK_SHIFT_CONST(0)
+#define CCR_C2MC_RDI_RDI_FIELD                  (_MK_MASK_CONST(0xffffffff) << CCR_C2MC_RDI_RDI_SHIFT)
+#define CCR_C2MC_RDI_RDI_RANGE                  _MK_SHIFT_CONST(255):_MK_SHIFT_CONST(0)
+#define CCR_C2MC_RDI_RDI_ROW                    0
+
+
+// Packet CCR_C2MC_HP
+#define CCR_C2MC_HP_SIZE 38
+
+// high-priority threshold
+#define CCR_C2MC_HP_HPTH_SHIFT                  _MK_SHIFT_CONST(0)
+#define CCR_C2MC_HP_HPTH_FIELD                  (_MK_MASK_CONST(0xffffffff) << CCR_C2MC_HP_HPTH_SHIFT)
+#define CCR_C2MC_HP_HPTH_RANGE                  _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CCR_C2MC_HP_HPTH_ROW                    0
+
+// high-priority timer
+#define CCR_C2MC_HP_HPTM_SHIFT                  _MK_SHIFT_CONST(32)
+#define CCR_C2MC_HP_HPTM_FIELD                  (_MK_MASK_CONST(0x3f) << CCR_C2MC_HP_HPTM_SHIFT)
+#define CCR_C2MC_HP_HPTM_RANGE                  _MK_SHIFT_CONST(37):_MK_SHIFT_CONST(32)
+#define CCR_C2MC_HP_HPTM_ROW                    0
+
+
+// Packet CCR_C2MC_HYST
+#define CCR_C2MC_HYST_SIZE 32
+
+// hysteresis control register
+#define CCR_C2MC_HYST_HYST_SHIFT                        _MK_SHIFT_CONST(0)
+#define CCR_C2MC_HYST_HYST_FIELD                        (_MK_MASK_CONST(0xffffffff) << CCR_C2MC_HYST_HYST_SHIFT)
+#define CCR_C2MC_HYST_HYST_RANGE                        _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CCR_C2MC_HYST_HYST_ROW                  0
+
+
+// Packet CCW_C2MC_RESET
+#define CCW_C2MC_RESET_SIZE 1
+
+#define CCW_C2MC_RESET_RSTN_SHIFT                       _MK_SHIFT_CONST(0)
+#define CCW_C2MC_RESET_RSTN_FIELD                       (_MK_MASK_CONST(0x1) << CCW_C2MC_RESET_RSTN_SHIFT)
+#define CCW_C2MC_RESET_RSTN_RANGE                       _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CCW_C2MC_RESET_RSTN_ROW                 0
+
+
+// Packet CCW_C2MC_REQ
+#define CCW_C2MC_REQ_SIZE 417
+
+#define CCW_C2MC_REQ_ADR_SHIFT                  _MK_SHIFT_CONST(0)
+#define CCW_C2MC_REQ_ADR_FIELD                  (_MK_MASK_CONST(0xffffffff) << CCW_C2MC_REQ_ADR_SHIFT)
+#define CCW_C2MC_REQ_ADR_RANGE                  _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CCW_C2MC_REQ_ADR_ROW                    0
+
+#define CCW_C2MC_REQ_LS_SHIFT                   _MK_SHIFT_CONST(32)
+#define CCW_C2MC_REQ_LS_FIELD                   (_MK_MASK_CONST(0xffffffff) << CCW_C2MC_REQ_LS_SHIFT)
+#define CCW_C2MC_REQ_LS_RANGE                   _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(32)
+#define CCW_C2MC_REQ_LS_ROW                     0
+
+// HI is apparently a reserved keyword
+#define CCW_C2MC_REQ_HINC_SHIFT                 _MK_SHIFT_CONST(64)
+#define CCW_C2MC_REQ_HINC_FIELD                 (_MK_MASK_CONST(0xffffffff) << CCW_C2MC_REQ_HINC_SHIFT)
+#define CCW_C2MC_REQ_HINC_RANGE                 _MK_SHIFT_CONST(95):_MK_SHIFT_CONST(64)
+#define CCW_C2MC_REQ_HINC_ROW                   0
+
+#define CCW_C2MC_REQ_ACMD_SHIFT                 _MK_SHIFT_CONST(96)
+#define CCW_C2MC_REQ_ACMD_FIELD                 (_MK_MASK_CONST(0x3) << CCW_C2MC_REQ_ACMD_SHIFT)
+#define CCW_C2MC_REQ_ACMD_RANGE                 _MK_SHIFT_CONST(97):_MK_SHIFT_CONST(96)
+#define CCW_C2MC_REQ_ACMD_ROW                   0
+
+#define CCW_C2MC_REQ_LN_SHIFT                   _MK_SHIFT_CONST(98)
+#define CCW_C2MC_REQ_LN_FIELD                   (_MK_MASK_CONST(0x1) << CCW_C2MC_REQ_LN_SHIFT)
+#define CCW_C2MC_REQ_LN_RANGE                   _MK_SHIFT_CONST(98):_MK_SHIFT_CONST(98)
+#define CCW_C2MC_REQ_LN_ROW                     0
+
+#define CCW_C2MC_REQ_HD_SHIFT                   _MK_SHIFT_CONST(99)
+#define CCW_C2MC_REQ_HD_FIELD                   (_MK_MASK_CONST(0x1) << CCW_C2MC_REQ_HD_SHIFT)
+#define CCW_C2MC_REQ_HD_RANGE                   _MK_SHIFT_CONST(99):_MK_SHIFT_CONST(99)
+#define CCW_C2MC_REQ_HD_ROW                     0
+
+#define CCW_C2MC_REQ_VD_SHIFT                   _MK_SHIFT_CONST(100)
+#define CCW_C2MC_REQ_VD_FIELD                   (_MK_MASK_CONST(0x1) << CCW_C2MC_REQ_VD_SHIFT)
+#define CCW_C2MC_REQ_VD_RANGE                   _MK_SHIFT_CONST(100):_MK_SHIFT_CONST(100)
+#define CCW_C2MC_REQ_VD_ROW                     0
+
+#define CCW_C2MC_REQ_BPP_SHIFT                  _MK_SHIFT_CONST(101)
+#define CCW_C2MC_REQ_BPP_FIELD                  (_MK_MASK_CONST(0x3) << CCW_C2MC_REQ_BPP_SHIFT)
+#define CCW_C2MC_REQ_BPP_RANGE                  _MK_SHIFT_CONST(102):_MK_SHIFT_CONST(101)
+#define CCW_C2MC_REQ_BPP_ROW                    0
+
+#define CCW_C2MC_REQ_XY_SHIFT                   _MK_SHIFT_CONST(103)
+#define CCW_C2MC_REQ_XY_FIELD                   (_MK_MASK_CONST(0x1) << CCW_C2MC_REQ_XY_SHIFT)
+#define CCW_C2MC_REQ_XY_RANGE                   _MK_SHIFT_CONST(103):_MK_SHIFT_CONST(103)
+#define CCW_C2MC_REQ_XY_ROW                     0
+
+#define CCW_C2MC_REQ_BE_SHIFT                   _MK_SHIFT_CONST(128)
+#define CCW_C2MC_REQ_BE_FIELD                   (_MK_MASK_CONST(0xffffffff) << CCW_C2MC_REQ_BE_SHIFT)
+#define CCW_C2MC_REQ_BE_RANGE                   _MK_SHIFT_CONST(159):_MK_SHIFT_CONST(128)
+#define CCW_C2MC_REQ_BE_ROW                     0
+
+#define CCW_C2MC_REQ_WDO_SHIFT                  _MK_SHIFT_CONST(160)
+#define CCW_C2MC_REQ_WDO_FIELD                  (_MK_MASK_CONST(0xffffffff) << CCW_C2MC_REQ_WDO_SHIFT)
+#define CCW_C2MC_REQ_WDO_RANGE                  _MK_SHIFT_CONST(415):_MK_SHIFT_CONST(160)
+#define CCW_C2MC_REQ_WDO_ROW                    0
+
+#define CCW_C2MC_REQ_TAG_SHIFT                  _MK_SHIFT_CONST(416)
+#define CCW_C2MC_REQ_TAG_FIELD                  (_MK_MASK_CONST(0x1) << CCW_C2MC_REQ_TAG_SHIFT)
+#define CCW_C2MC_REQ_TAG_RANGE                  _MK_SHIFT_CONST(416):_MK_SHIFT_CONST(416)
+#define CCW_C2MC_REQ_TAG_ROW                    0
+
+
+// Packet CCW_C2MC_SECURE
+#define CCW_C2MC_SECURE_SIZE 1
+
+#define CCW_C2MC_SECURE_SECURE_SHIFT                    _MK_SHIFT_CONST(0)
+#define CCW_C2MC_SECURE_SECURE_FIELD                    (_MK_MASK_CONST(0x1) << CCW_C2MC_SECURE_SECURE_SHIFT)
+#define CCW_C2MC_SECURE_SECURE_RANGE                    _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CCW_C2MC_SECURE_SECURE_ROW                      0
+
+
+// Packet CCW_C2MC_ADRXY
+#define CCW_C2MC_ADRXY_SIZE 30
+
+#define CCW_C2MC_ADRXY_OFFX_SHIFT                       _MK_SHIFT_CONST(0)
+#define CCW_C2MC_ADRXY_OFFX_FIELD                       (_MK_MASK_CONST(0xffff) << CCW_C2MC_ADRXY_OFFX_SHIFT)
+#define CCW_C2MC_ADRXY_OFFX_RANGE                       _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(0)
+#define CCW_C2MC_ADRXY_OFFX_ROW                 0
+
+#define CCW_C2MC_ADRXY_OFFY_SHIFT                       _MK_SHIFT_CONST(16)
+#define CCW_C2MC_ADRXY_OFFY_FIELD                       (_MK_MASK_CONST(0x3fff) << CCW_C2MC_ADRXY_OFFY_SHIFT)
+#define CCW_C2MC_ADRXY_OFFY_RANGE                       _MK_SHIFT_CONST(29):_MK_SHIFT_CONST(16)
+#define CCW_C2MC_ADRXY_OFFY_ROW                 0
+
+
+// Packet CCW_C2MC_TILE
+#define CCW_C2MC_TILE_SIZE 33
+
+#define CCW_C2MC_TILE_LINADR_SHIFT                      _MK_SHIFT_CONST(0)
+#define CCW_C2MC_TILE_LINADR_FIELD                      (_MK_MASK_CONST(0xffffffff) << CCW_C2MC_TILE_LINADR_SHIFT)
+#define CCW_C2MC_TILE_LINADR_RANGE                      _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CCW_C2MC_TILE_LINADR_ROW                        0
+
+#define CCW_C2MC_TILE_TMODE_SHIFT                       _MK_SHIFT_CONST(32)
+#define CCW_C2MC_TILE_TMODE_FIELD                       (_MK_MASK_CONST(0x1) << CCW_C2MC_TILE_TMODE_SHIFT)
+#define CCW_C2MC_TILE_TMODE_RANGE                       _MK_SHIFT_CONST(32):_MK_SHIFT_CONST(32)
+#define CCW_C2MC_TILE_TMODE_ROW                 0
+#define CCW_C2MC_TILE_TMODE_LINEAR                      _MK_ENUM_CONST(0)
+#define CCW_C2MC_TILE_TMODE_TILED                       _MK_ENUM_CONST(1)
+
+
+// Packet CCW_C2MC_XDI
+#define CCW_C2MC_XDI_SIZE 1
+
+// fake data
+#define CCW_C2MC_XDI_XDI_SHIFT                  _MK_SHIFT_CONST(0)
+#define CCW_C2MC_XDI_XDI_FIELD                  (_MK_MASK_CONST(0x1) << CCW_C2MC_XDI_XDI_SHIFT)
+#define CCW_C2MC_XDI_XDI_RANGE                  _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CCW_C2MC_XDI_XDI_ROW                    0
+
+
+// Packet CCW_C2MC_HP
+#define CCW_C2MC_HP_SIZE 32
+
+// high-priority threshold
+#define CCW_C2MC_HP_HPTH_SHIFT                  _MK_SHIFT_CONST(0)
+#define CCW_C2MC_HP_HPTH_FIELD                  (_MK_MASK_CONST(0xffffffff) << CCW_C2MC_HP_HPTH_SHIFT)
+#define CCW_C2MC_HP_HPTH_RANGE                  _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CCW_C2MC_HP_HPTH_ROW                    0
+
+
+// Packet CCW_C2MC_WCOAL
+#define CCW_C2MC_WCOAL_SIZE 32
+
+// write-coalescing time-out
+#define CCW_C2MC_WCOAL_WCOALTM_SHIFT                    _MK_SHIFT_CONST(0)
+#define CCW_C2MC_WCOAL_WCOALTM_FIELD                    (_MK_MASK_CONST(0xffffffff) << CCW_C2MC_WCOAL_WCOALTM_SHIFT)
+#define CCW_C2MC_WCOAL_WCOALTM_RANGE                    _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CCW_C2MC_WCOAL_WCOALTM_ROW                      0
+
+
+// Packet CCW_C2MC_HYST
+#define CCW_C2MC_HYST_SIZE 32
+
+#define CCW_C2MC_HYST_HYST_REQ_TM_SHIFT                 _MK_SHIFT_CONST(0)
+#define CCW_C2MC_HYST_HYST_REQ_TM_FIELD                 (_MK_MASK_CONST(0xfff) << CCW_C2MC_HYST_HYST_REQ_TM_SHIFT)
+#define CCW_C2MC_HYST_HYST_REQ_TM_RANGE                 _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(0)
+#define CCW_C2MC_HYST_HYST_REQ_TM_ROW                   0
+
+#define CCW_C2MC_HYST_HYST_REQ_TH_SHIFT                 _MK_SHIFT_CONST(28)
+#define CCW_C2MC_HYST_HYST_REQ_TH_FIELD                 (_MK_MASK_CONST(0x7) << CCW_C2MC_HYST_HYST_REQ_TH_SHIFT)
+#define CCW_C2MC_HYST_HYST_REQ_TH_RANGE                 _MK_SHIFT_CONST(30):_MK_SHIFT_CONST(28)
+#define CCW_C2MC_HYST_HYST_REQ_TH_ROW                   0
+
+#define CCW_C2MC_HYST_HYST_EN_SHIFT                     _MK_SHIFT_CONST(31)
+#define CCW_C2MC_HYST_HYST_EN_FIELD                     (_MK_MASK_CONST(0x1) << CCW_C2MC_HYST_HYST_EN_SHIFT)
+#define CCW_C2MC_HYST_HYST_EN_RANGE                     _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(31)
+#define CCW_C2MC_HYST_HYST_EN_ROW                       0
+
+
+// Packet SC_MCCIF_ASYNC
+#define SC_MCCIF_ASYNC_SIZE 4
+
+#define SC_MCCIF_ASYNC_RDCL_RDFAST_SHIFT                        _MK_SHIFT_CONST(0)
+#define SC_MCCIF_ASYNC_RDCL_RDFAST_FIELD                        (_MK_MASK_CONST(0x1) << SC_MCCIF_ASYNC_RDCL_RDFAST_SHIFT)
+#define SC_MCCIF_ASYNC_RDCL_RDFAST_RANGE                        _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define SC_MCCIF_ASYNC_RDCL_RDFAST_ROW                  0
+
+#define SC_MCCIF_ASYNC_RDMC_RDFAST_SHIFT                        _MK_SHIFT_CONST(1)
+#define SC_MCCIF_ASYNC_RDMC_RDFAST_FIELD                        (_MK_MASK_CONST(0x1) << SC_MCCIF_ASYNC_RDMC_RDFAST_SHIFT)
+#define SC_MCCIF_ASYNC_RDMC_RDFAST_RANGE                        _MK_SHIFT_CONST(1):_MK_SHIFT_CONST(1)
+#define SC_MCCIF_ASYNC_RDMC_RDFAST_ROW                  0
+
+#define SC_MCCIF_ASYNC_WRCL_MCLE2X_SHIFT                        _MK_SHIFT_CONST(2)
+#define SC_MCCIF_ASYNC_WRCL_MCLE2X_FIELD                        (_MK_MASK_CONST(0x1) << SC_MCCIF_ASYNC_WRCL_MCLE2X_SHIFT)
+#define SC_MCCIF_ASYNC_WRCL_MCLE2X_RANGE                        _MK_SHIFT_CONST(2):_MK_SHIFT_CONST(2)
+#define SC_MCCIF_ASYNC_WRCL_MCLE2X_ROW                  0
+
+#define SC_MCCIF_ASYNC_WRMC_CLLE2X_SHIFT                        _MK_SHIFT_CONST(3)
+#define SC_MCCIF_ASYNC_WRMC_CLLE2X_FIELD                        (_MK_MASK_CONST(0x1) << SC_MCCIF_ASYNC_WRMC_CLLE2X_SHIFT)
+#define SC_MCCIF_ASYNC_WRMC_CLLE2X_RANGE                        _MK_SHIFT_CONST(3):_MK_SHIFT_CONST(3)
+#define SC_MCCIF_ASYNC_WRMC_CLLE2X_ROW                  0
+
+
+//
+// REGISTER LIST
+//
+#define LIST_ARMC_REGS(_op_) \
+_op_(MC_INTSTATUS_0) \
+_op_(MC_INTMASK_0) \
+_op_(MC_EMEM_CFG_0) \
+_op_(MC_EMEM_ADR_CFG_0) \
+_op_(MC_EMEM_ARB_CFG0_0) \
+_op_(MC_EMEM_ARB_CFG1_0) \
+_op_(MC_EMEM_ARB_CFG2_0) \
+_op_(MC_GART_CONFIG_0) \
+_op_(MC_GART_ENTRY_ADDR_0) \
+_op_(MC_GART_ENTRY_DATA_0) \
+_op_(MC_GART_ERROR_REQ_0) \
+_op_(MC_GART_ERROR_ADDR_0) \
+_op_(MC_TIMEOUT_CTRL_0) \
+_op_(MC_DECERR_EMEM_OTHERS_STATUS_0) \
+_op_(MC_DECERR_EMEM_OTHERS_ADR_0) \
+_op_(MC_CLKEN_OVERRIDE_0) \
+_op_(MC_SECURITY_CFG0_0) \
+_op_(MC_SECURITY_CFG1_0) \
+_op_(MC_SECURITY_VIOLATION_STATUS_0) \
+_op_(MC_SECURITY_VIOLATION_ADR_0) \
+_op_(MC_SECURITY_CFG2_0) \
+_op_(MC_STAT_CONTROL_0) \
+_op_(MC_STAT_STATUS_0) \
+_op_(MC_STAT_EMC_ADDR_LOW_0) \
+_op_(MC_STAT_EMC_ADDR_HIGH_0) \
+_op_(MC_STAT_EMC_CLOCK_LIMIT_0) \
+_op_(MC_STAT_EMC_CLOCKS_0) \
+_op_(MC_STAT_EMC_CONTROL_0_0) \
+_op_(MC_STAT_EMC_CONTROL_1_0) \
+_op_(MC_STAT_EMC_HIST_LIMIT_0_0) \
+_op_(MC_STAT_EMC_HIST_LIMIT_1_0) \
+_op_(MC_STAT_EMC_COUNT_0_0) \
+_op_(MC_STAT_EMC_COUNT_1_0) \
+_op_(MC_STAT_EMC_HIST_0_0) \
+_op_(MC_STAT_EMC_HIST_1_0) \
+_op_(MC_CLIENT_CTRL_0) \
+_op_(MC_CLIENT_HOTRESETN_0) \
+_op_(MC_AXI_DECERR_OVR_0) \
+_op_(MC_LOWLATENCY_CONFIG_0) \
+_op_(MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0) \
+_op_(MC_BWSHARE_TMVAL_0) \
+_op_(MC_BWSHARE_EMEM_CTRL_0_0) \
+_op_(MC_BWSHARE_EMEM_CTRL_1_0) \
+_op_(MC_AP_CTRL_0_0) \
+_op_(MC_AP_CTRL_1_0) \
+_op_(MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0) \
+_op_(MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0) \
+_op_(MC_AVPC_ORRC_0) \
+_op_(MC_DC_ORRC_0) \
+_op_(MC_DCB_ORRC_0) \
+_op_(MC_EPP_ORRC_0) \
+_op_(MC_G2_ORRC_0) \
+_op_(MC_HC_ORRC_0) \
+_op_(MC_ISP_ORRC_0) \
+_op_(MC_MPCORE_ORRC_0) \
+_op_(MC_MPEA_ORRC_0) \
+_op_(MC_MPEB_ORRC_0) \
+_op_(MC_MPEC_ORRC_0) \
+_op_(MC_NV_ORRC_0) \
+_op_(MC_PPCS_ORRC_0) \
+_op_(MC_VDE_ORRC_0) \
+_op_(MC_VI_ORRC_0) \
+_op_(MC_FPRI_CTRL_AVPC_0) \
+_op_(MC_FPRI_CTRL_DC_0) \
+_op_(MC_FPRI_CTRL_DCB_0) \
+_op_(MC_FPRI_CTRL_EPP_0) \
+_op_(MC_FPRI_CTRL_G2_0) \
+_op_(MC_FPRI_CTRL_HC_0) \
+_op_(MC_FPRI_CTRL_ISP_0) \
+_op_(MC_FPRI_CTRL_MPCORE_0) \
+_op_(MC_FPRI_CTRL_MPEA_0) \
+_op_(MC_FPRI_CTRL_MPEB_0) \
+_op_(MC_FPRI_CTRL_MPEC_0) \
+_op_(MC_FPRI_CTRL_NV_0) \
+_op_(MC_FPRI_CTRL_PPCS_0) \
+_op_(MC_FPRI_CTRL_VDE_0) \
+_op_(MC_FPRI_CTRL_VI_0) \
+_op_(MC_TIMEOUT_AVPC_0) \
+_op_(MC_TIMEOUT_DC_0) \
+_op_(MC_TIMEOUT_DCB_0) \
+_op_(MC_TIMEOUT_EPP_0) \
+_op_(MC_TIMEOUT_G2_0) \
+_op_(MC_TIMEOUT_HC_0) \
+_op_(MC_TIMEOUT_ISP_0) \
+_op_(MC_TIMEOUT_MPCORE_0) \
+_op_(MC_TIMEOUT_MPEA_0) \
+_op_(MC_TIMEOUT_MPEB_0) \
+_op_(MC_TIMEOUT_MPEC_0) \
+_op_(MC_TIMEOUT_NV_0) \
+_op_(MC_TIMEOUT_PPCS_0) \
+_op_(MC_TIMEOUT_VDE_0) \
+_op_(MC_TIMEOUT_VI_0) \
+_op_(MC_TIMEOUT_RCOAL_AVPC_0) \
+_op_(MC_TIMEOUT_RCOAL_DC_0) \
+_op_(MC_TIMEOUT1_RCOAL_DC_0) \
+_op_(MC_TIMEOUT_RCOAL_DCB_0) \
+_op_(MC_TIMEOUT1_RCOAL_DCB_0) \
+_op_(MC_TIMEOUT_RCOAL_EPP_0) \
+_op_(MC_TIMEOUT_RCOAL_G2_0) \
+_op_(MC_TIMEOUT_RCOAL_HC_0) \
+_op_(MC_TIMEOUT_RCOAL_MPCORE_0) \
+_op_(MC_TIMEOUT_RCOAL_MPEA_0) \
+_op_(MC_TIMEOUT_RCOAL_MPEB_0) \
+_op_(MC_TIMEOUT_RCOAL_MPEC_0) \
+_op_(MC_TIMEOUT_RCOAL_NV_0) \
+_op_(MC_TIMEOUT_RCOAL_PPCS_0) \
+_op_(MC_TIMEOUT_RCOAL_VDE_0) \
+_op_(MC_TIMEOUT_RCOAL_VI_0) \
+_op_(MC_RCOAL_AUTODISABLE_0_0) \
+_op_(MC_BWSHARE_AVPC_0) \
+_op_(MC_BWSHARE_DC_0) \
+_op_(MC_BWSHARE_DCB_0) \
+_op_(MC_BWSHARE_EPP_0) \
+_op_(MC_BWSHARE_G2_0) \
+_op_(MC_BWSHARE_HC_0) \
+_op_(MC_BWSHARE_ISP_0) \
+_op_(MC_BWSHARE_MPCORE_0) \
+_op_(MC_BWSHARE_MPEA_0) \
+_op_(MC_BWSHARE_MPEB_0) \
+_op_(MC_BWSHARE_MPEC_0) \
+_op_(MC_BWSHARE_NV_0) \
+_op_(MC_BWSHARE_PPCS_0) \
+_op_(MC_BWSHARE_VDE_0) \
+_op_(MC_BWSHARE_VI_0)
+
+
+//
+// ADDRESS SPACES
+//
+
+#define BASE_ADDRESS_MC 0x00000000
+
+//
+// ARMC REGISTER BANKS
+//
+
+#define MC0_FIRST_REG 0x0000 // MC_INTSTATUS_0
+#define MC0_LAST_REG 0x0004 // MC_INTMASK_0
+#define MC1_FIRST_REG 0x000c // MC_EMEM_CFG_0
+#define MC1_LAST_REG 0x001c // MC_EMEM_ARB_CFG2_0
+#define MC2_FIRST_REG 0x0024 // MC_GART_CONFIG_0
+#define MC2_LAST_REG 0x0034 // MC_GART_ERROR_ADDR_0
+#define MC3_FIRST_REG 0x003c // MC_TIMEOUT_CTRL_0
+#define MC3_LAST_REG 0x003c // MC_TIMEOUT_CTRL_0
+#define MC4_FIRST_REG 0x0058 // MC_DECERR_EMEM_OTHERS_STATUS_0
+#define MC4_LAST_REG 0x005c // MC_DECERR_EMEM_OTHERS_ADR_0
+#define MC5_FIRST_REG 0x0068 // MC_CLKEN_OVERRIDE_0
+#define MC5_LAST_REG 0x007c // MC_SECURITY_CFG2_0
+#define MC6_FIRST_REG 0x0090 // MC_STAT_CONTROL_0
+#define MC6_LAST_REG 0x00c4 // MC_STAT_EMC_HIST_1_0
+#define MC7_FIRST_REG 0x0100 // MC_CLIENT_CTRL_0
+#define MC7_LAST_REG 0x0114 // MC_BWSHARE_TMVAL_0
+#define MC8_FIRST_REG 0x0120 // MC_BWSHARE_EMEM_CTRL_0_0
+#define MC8_LAST_REG 0x012c // MC_AP_CTRL_1_0
+#define MC9_FIRST_REG 0x0138 // MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0
+#define MC9_LAST_REG 0x0270 // MC_BWSHARE_VI_0
+
+#ifndef _MK_SHIFT_CONST
+  #define _MK_SHIFT_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_MASK_CONST
+  #define _MK_MASK_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_ENUM_CONST
+  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
+#endif
+#ifndef _MK_ADDR_CONST
+  #define _MK_ADDR_CONST(_constant_) _constant_
+#endif
+
+#endif // ifndef ___ARMC_H_INC_
diff --git a/arch/arm/mach-tegra/include/ap20/arowr.h b/arch/arm/mach-tegra/include/ap20/arowr.h
new file mode 100644
index 000000000000..5cec2977a406
--- /dev/null
+++ b/arch/arm/mach-tegra/include/ap20/arowr.h
@@ -0,0 +1,1675 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+//
+// DO NOT EDIT - generated by simspec!
+//
+
+#ifndef ___AROWR_H_INC_
+#define ___AROWR_H_INC_
+#define OWR_TX_FIFO_DEPTH       32
+#define OWR_RX_FIFO_DEPTH       32
+
+// Register OWR_CONTROL_0  
+#define OWR_CONTROL_0                   _MK_ADDR_CONST(0x0)
+#define OWR_CONTROL_0_SECURE                    0x0
+#define OWR_CONTROL_0_WORD_COUNT                        0x1
+#define OWR_CONTROL_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define OWR_CONTROL_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
+#define OWR_CONTROL_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define OWR_CONTROL_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define OWR_CONTROL_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define OWR_CONTROL_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
+//Generate Reset Presence Pulse 
+//write only bit 
+//read to this register will return 0
+//bit should be programed after all the registers are programed
+#define OWR_CONTROL_0_GO_SHIFT                  _MK_SHIFT_CONST(0)
+#define OWR_CONTROL_0_GO_FIELD                  (_MK_MASK_CONST(0x1) << OWR_CONTROL_0_GO_SHIFT)
+#define OWR_CONTROL_0_GO_RANGE                  0:0
+#define OWR_CONTROL_0_GO_WOFFSET                        0x0
+#define OWR_CONTROL_0_GO_DEFAULT                        _MK_MASK_CONST(0x0)
+#define OWR_CONTROL_0_GO_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define OWR_CONTROL_0_GO_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define OWR_CONTROL_0_GO_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define OWR_CONTROL_0_GO_NO_PRESENCE_PULSE                      _MK_ENUM_CONST(0)
+#define OWR_CONTROL_0_GO_START_PRESENCE_PULSE                   _MK_ENUM_CONST(1)
+
+// when set, dq is driven to low by master before the slave does 
+// clearing this bit disables the ppm    
+#define OWR_CONTROL_0_PRESENCE_PULSE_MASKING_SHIFT                      _MK_SHIFT_CONST(1)
+#define OWR_CONTROL_0_PRESENCE_PULSE_MASKING_FIELD                      (_MK_MASK_CONST(0x1) << OWR_CONTROL_0_PRESENCE_PULSE_MASKING_SHIFT)
+#define OWR_CONTROL_0_PRESENCE_PULSE_MASKING_RANGE                      1:1
+#define OWR_CONTROL_0_PRESENCE_PULSE_MASKING_WOFFSET                    0x0
+#define OWR_CONTROL_0_PRESENCE_PULSE_MASKING_DEFAULT                    _MK_MASK_CONST(0x0)
+#define OWR_CONTROL_0_PRESENCE_PULSE_MASKING_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define OWR_CONTROL_0_PRESENCE_PULSE_MASKING_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define OWR_CONTROL_0_PRESENCE_PULSE_MASKING_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define OWR_CONTROL_0_PRESENCE_PULSE_MASKING_NO_PPM                     _MK_ENUM_CONST(0)
+#define OWR_CONTROL_0_PRESENCE_PULSE_MASKING_START_PPM                  _MK_ENUM_CONST(1)
+
+// if set to 1 data transfer is done bit by bit
+// if set to 0 data transfer is done through byte
+#define OWR_CONTROL_0_DATA_TRANSFER_MODE_SHIFT                  _MK_SHIFT_CONST(2)
+#define OWR_CONTROL_0_DATA_TRANSFER_MODE_FIELD                  (_MK_MASK_CONST(0x1) << OWR_CONTROL_0_DATA_TRANSFER_MODE_SHIFT)
+#define OWR_CONTROL_0_DATA_TRANSFER_MODE_RANGE                  2:2
+#define OWR_CONTROL_0_DATA_TRANSFER_MODE_WOFFSET                        0x0
+#define OWR_CONTROL_0_DATA_TRANSFER_MODE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define OWR_CONTROL_0_DATA_TRANSFER_MODE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define OWR_CONTROL_0_DATA_TRANSFER_MODE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define OWR_CONTROL_0_DATA_TRANSFER_MODE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define OWR_CONTROL_0_DATA_TRANSFER_MODE_BYTE_TRANSFER_MODE                     _MK_ENUM_CONST(0)
+#define OWR_CONTROL_0_DATA_TRANSFER_MODE_BIT_TRANSFER_MODE                      _MK_ENUM_CONST(1)
+
+// if set to 1 16bit crc is executed
+// if set to 0 8bit crc is executed
+#define OWR_CONTROL_0_CRC_16BIT_EN_SHIFT                        _MK_SHIFT_CONST(3)
+#define OWR_CONTROL_0_CRC_16BIT_EN_FIELD                        (_MK_MASK_CONST(0x1) << OWR_CONTROL_0_CRC_16BIT_EN_SHIFT)
+#define OWR_CONTROL_0_CRC_16BIT_EN_RANGE                        3:3
+#define OWR_CONTROL_0_CRC_16BIT_EN_WOFFSET                      0x0
+#define OWR_CONTROL_0_CRC_16BIT_EN_DEFAULT                      _MK_MASK_CONST(0x0)
+#define OWR_CONTROL_0_CRC_16BIT_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define OWR_CONTROL_0_CRC_16BIT_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define OWR_CONTROL_0_CRC_16BIT_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define OWR_CONTROL_0_CRC_16BIT_EN_CRC_8BIT_EN                  _MK_ENUM_CONST(0)
+#define OWR_CONTROL_0_CRC_16BIT_EN_CRC_16BIT_EN                 _MK_ENUM_CONST(1)
+
+// Transmit fifo attention level
+// 000 = 1 word, fifo req is asserted when least one word empty in the fifo
+// 001 = 2 word, fifo req is asserted when least 2 words empty in the fifo
+// etc.......
+#define OWR_CONTROL_0_TX_FIFO_ATTEN_LEVEL_SHIFT                 _MK_SHIFT_CONST(4)
+#define OWR_CONTROL_0_TX_FIFO_ATTEN_LEVEL_FIELD                 (_MK_MASK_CONST(0x1f) << OWR_CONTROL_0_TX_FIFO_ATTEN_LEVEL_SHIFT)
+#define OWR_CONTROL_0_TX_FIFO_ATTEN_LEVEL_RANGE                 8:4
+#define OWR_CONTROL_0_TX_FIFO_ATTEN_LEVEL_WOFFSET                       0x0
+#define OWR_CONTROL_0_TX_FIFO_ATTEN_LEVEL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define OWR_CONTROL_0_TX_FIFO_ATTEN_LEVEL_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define OWR_CONTROL_0_TX_FIFO_ATTEN_LEVEL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define OWR_CONTROL_0_TX_FIFO_ATTEN_LEVEL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Receive  fifo attention level
+// 000 = 1 word, fifo req is asserted when least one word full in the fifo
+// 001 = 2 word, fifo req is asserted when least 2 words full in the fifo
+// etc.....
+#define OWR_CONTROL_0_RX_FIFO_ATTEN_LEVEL_SHIFT                 _MK_SHIFT_CONST(9)
+#define OWR_CONTROL_0_RX_FIFO_ATTEN_LEVEL_FIELD                 (_MK_MASK_CONST(0x1f) << OWR_CONTROL_0_RX_FIFO_ATTEN_LEVEL_SHIFT)
+#define OWR_CONTROL_0_RX_FIFO_ATTEN_LEVEL_RANGE                 13:9
+#define OWR_CONTROL_0_RX_FIFO_ATTEN_LEVEL_WOFFSET                       0x0
+#define OWR_CONTROL_0_RX_FIFO_ATTEN_LEVEL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define OWR_CONTROL_0_RX_FIFO_ATTEN_LEVEL_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define OWR_CONTROL_0_RX_FIFO_ATTEN_LEVEL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define OWR_CONTROL_0_RX_FIFO_ATTEN_LEVEL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//This bit is set to 1, if crc is required 
+//for read memory cmd at end of memory
+#define OWR_CONTROL_0_RD_MEM_CRC_REQ_SHIFT                      _MK_SHIFT_CONST(14)
+#define OWR_CONTROL_0_RD_MEM_CRC_REQ_FIELD                      (_MK_MASK_CONST(0x1) << OWR_CONTROL_0_RD_MEM_CRC_REQ_SHIFT)
+#define OWR_CONTROL_0_RD_MEM_CRC_REQ_RANGE                      14:14
+#define OWR_CONTROL_0_RD_MEM_CRC_REQ_WOFFSET                    0x0
+#define OWR_CONTROL_0_RD_MEM_CRC_REQ_DEFAULT                    _MK_MASK_CONST(0x0)
+#define OWR_CONTROL_0_RD_MEM_CRC_REQ_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define OWR_CONTROL_0_RD_MEM_CRC_REQ_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define OWR_CONTROL_0_RD_MEM_CRC_REQ_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define OWR_CONTROL_0_RD_MEM_CRC_REQ_NO_CRC_READ                        _MK_ENUM_CONST(0)
+#define OWR_CONTROL_0_RD_MEM_CRC_REQ_CRC_READ                   _MK_ENUM_CONST(1)
+
+//presence pulse sample clk, master samples the data_in 
+//which should be less than or equal to (tpdl - 6) clks   
+// 6 clks are used for dglitch, 
+// if Deglitch bypassed 3 clks should be enough
+#define OWR_CONTROL_0_PRESENCE_SAMPLE_CLK_SHIFT                 _MK_SHIFT_CONST(15)
+#define OWR_CONTROL_0_PRESENCE_SAMPLE_CLK_FIELD                 (_MK_MASK_CONST(0xff) << OWR_CONTROL_0_PRESENCE_SAMPLE_CLK_SHIFT)
+#define OWR_CONTROL_0_PRESENCE_SAMPLE_CLK_RANGE                 22:15
+#define OWR_CONTROL_0_PRESENCE_SAMPLE_CLK_WOFFSET                       0x0
+#define OWR_CONTROL_0_PRESENCE_SAMPLE_CLK_DEFAULT                       _MK_MASK_CONST(0x0)
+#define OWR_CONTROL_0_PRESENCE_SAMPLE_CLK_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define OWR_CONTROL_0_PRESENCE_SAMPLE_CLK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define OWR_CONTROL_0_PRESENCE_SAMPLE_CLK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//read data sample window, master samples the data_in
+//which should be less than or equal to (tlow1 - 6) clks   
+// 6 clks are used for Deglitch, 
+// if Deglitch bypassed 3 clks should be enough
+#define OWR_CONTROL_0_RD_DATA_SAMPLE_CLK_SHIFT                  _MK_SHIFT_CONST(23)
+#define OWR_CONTROL_0_RD_DATA_SAMPLE_CLK_FIELD                  (_MK_MASK_CONST(0xf) << OWR_CONTROL_0_RD_DATA_SAMPLE_CLK_SHIFT)
+#define OWR_CONTROL_0_RD_DATA_SAMPLE_CLK_RANGE                  26:23
+#define OWR_CONTROL_0_RD_DATA_SAMPLE_CLK_WOFFSET                        0x0
+#define OWR_CONTROL_0_RD_DATA_SAMPLE_CLK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define OWR_CONTROL_0_RD_DATA_SAMPLE_CLK_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
+#define OWR_CONTROL_0_RD_DATA_SAMPLE_CLK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define OWR_CONTROL_0_RD_DATA_SAMPLE_CLK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// This bit is used to bypass the deglitch logic,
+// If 1, just takes the sync output
+// If 0, looks for any glitch in the sample window for at least 1us,
+// Deglitch requires a minimum of 6 clks(2 for sync, 2 for deglitch,
+// if glitch, checks for 2 more clks, still glitch exists, err interrupt is
+// asserted and data transfer should start from first)  
+#define OWR_CONTROL_0_BY_PASS_DGLITCH_SHIFT                     _MK_SHIFT_CONST(27)
+#define OWR_CONTROL_0_BY_PASS_DGLITCH_FIELD                     (_MK_MASK_CONST(0x1) << OWR_CONTROL_0_BY_PASS_DGLITCH_SHIFT)
+#define OWR_CONTROL_0_BY_PASS_DGLITCH_RANGE                     27:27
+#define OWR_CONTROL_0_BY_PASS_DGLITCH_WOFFSET                   0x0
+#define OWR_CONTROL_0_BY_PASS_DGLITCH_DEFAULT                   _MK_MASK_CONST(0x0)
+#define OWR_CONTROL_0_BY_PASS_DGLITCH_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define OWR_CONTROL_0_BY_PASS_DGLITCH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define OWR_CONTROL_0_BY_PASS_DGLITCH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define OWR_CONTROL_0_BY_PASS_DGLITCH_START_DGLITCH                     _MK_ENUM_CONST(0)
+#define OWR_CONTROL_0_BY_PASS_DGLITCH_NO_DGLITCH                        _MK_ENUM_CONST(1)
+
+// this bit is set to 1, if transfer needs to continue on crc err
+// else on err transfer stops, 
+// and again transfer should start on setting rpp reset(go bit)
+#define OWR_CONTROL_0_BY_PASS_CRC_ERR_SHIFT                     _MK_SHIFT_CONST(28)
+#define OWR_CONTROL_0_BY_PASS_CRC_ERR_FIELD                     (_MK_MASK_CONST(0x1) << OWR_CONTROL_0_BY_PASS_CRC_ERR_SHIFT)
+#define OWR_CONTROL_0_BY_PASS_CRC_ERR_RANGE                     28:28
+#define OWR_CONTROL_0_BY_PASS_CRC_ERR_WOFFSET                   0x0
+#define OWR_CONTROL_0_BY_PASS_CRC_ERR_DEFAULT                   _MK_MASK_CONST(0x0)
+#define OWR_CONTROL_0_BY_PASS_CRC_ERR_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define OWR_CONTROL_0_BY_PASS_CRC_ERR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define OWR_CONTROL_0_BY_PASS_CRC_ERR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define OWR_CONTROL_0_BY_PASS_CRC_ERR_STOP_TRANSFER_ON_CRC_ERR                  _MK_ENUM_CONST(0)
+#define OWR_CONTROL_0_BY_PASS_CRC_ERR_CONTINUE_TRANSFER_ON_CRC_ERR                      _MK_ENUM_CONST(1)
+
+// if 0 no transfer is done
+// if 1 write one time slot is executed
+//This bit is a write only 
+//read to this register will return 0
+#define OWR_CONTROL_0_WR1_BIT_SHIFT                     _MK_SHIFT_CONST(29)
+#define OWR_CONTROL_0_WR1_BIT_FIELD                     (_MK_MASK_CONST(0x1) << OWR_CONTROL_0_WR1_BIT_SHIFT)
+#define OWR_CONTROL_0_WR1_BIT_RANGE                     29:29
+#define OWR_CONTROL_0_WR1_BIT_WOFFSET                   0x0
+#define OWR_CONTROL_0_WR1_BIT_DEFAULT                   _MK_MASK_CONST(0x0)
+#define OWR_CONTROL_0_WR1_BIT_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define OWR_CONTROL_0_WR1_BIT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define OWR_CONTROL_0_WR1_BIT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define OWR_CONTROL_0_WR1_BIT_NO_TRANSFER                       _MK_ENUM_CONST(0)
+#define OWR_CONTROL_0_WR1_BIT_TRANSFER_ONE                      _MK_ENUM_CONST(1)
+
+// if 0 no transfer is done
+// if 1 write zero time slot is executed
+//write only bit
+//read to this register will return 0
+#define OWR_CONTROL_0_WR0_BIT_SHIFT                     _MK_SHIFT_CONST(30)
+#define OWR_CONTROL_0_WR0_BIT_FIELD                     (_MK_MASK_CONST(0x1) << OWR_CONTROL_0_WR0_BIT_SHIFT)
+#define OWR_CONTROL_0_WR0_BIT_RANGE                     30:30
+#define OWR_CONTROL_0_WR0_BIT_WOFFSET                   0x0
+#define OWR_CONTROL_0_WR0_BIT_DEFAULT                   _MK_MASK_CONST(0x0)
+#define OWR_CONTROL_0_WR0_BIT_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define OWR_CONTROL_0_WR0_BIT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define OWR_CONTROL_0_WR0_BIT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define OWR_CONTROL_0_WR0_BIT_NO_TRANSFER                       _MK_ENUM_CONST(0)
+#define OWR_CONTROL_0_WR0_BIT_TRANSFER_ZERO                     _MK_ENUM_CONST(1)
+
+// if 0 no transfer is done
+// if 1 read time slot is executed
+//write only bit 
+//read to this register will return 0
+#define OWR_CONTROL_0_RD_BIT_SHIFT                      _MK_SHIFT_CONST(31)
+#define OWR_CONTROL_0_RD_BIT_FIELD                      (_MK_MASK_CONST(0x1) << OWR_CONTROL_0_RD_BIT_SHIFT)
+#define OWR_CONTROL_0_RD_BIT_RANGE                      31:31
+#define OWR_CONTROL_0_RD_BIT_WOFFSET                    0x0
+#define OWR_CONTROL_0_RD_BIT_DEFAULT                    _MK_MASK_CONST(0x0)
+#define OWR_CONTROL_0_RD_BIT_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define OWR_CONTROL_0_RD_BIT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define OWR_CONTROL_0_RD_BIT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define OWR_CONTROL_0_RD_BIT_NO_TRANSFER                        _MK_ENUM_CONST(0)
+#define OWR_CONTROL_0_RD_BIT_TRANSFER_READ_SLOT                 _MK_ENUM_CONST(1)
+
+
+// Register OWR_COMMAND_0  
+#define OWR_COMMAND_0                   _MK_ADDR_CONST(0x4)
+#define OWR_COMMAND_0_SECURE                    0x0
+#define OWR_COMMAND_0_WORD_COUNT                        0x1
+#define OWR_COMMAND_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define OWR_COMMAND_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
+#define OWR_COMMAND_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define OWR_COMMAND_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define OWR_COMMAND_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define OWR_COMMAND_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
+//1-wire ROM commands 
+#define OWR_COMMAND_0_ROM_CMD_SHIFT                     _MK_SHIFT_CONST(0)
+#define OWR_COMMAND_0_ROM_CMD_FIELD                     (_MK_MASK_CONST(0xff) << OWR_COMMAND_0_ROM_CMD_SHIFT)
+#define OWR_COMMAND_0_ROM_CMD_RANGE                     7:0
+#define OWR_COMMAND_0_ROM_CMD_WOFFSET                   0x0
+#define OWR_COMMAND_0_ROM_CMD_DEFAULT                   _MK_MASK_CONST(0x0)
+#define OWR_COMMAND_0_ROM_CMD_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define OWR_COMMAND_0_ROM_CMD_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define OWR_COMMAND_0_ROM_CMD_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+//1-wire MEM commands 
+#define OWR_COMMAND_0_MEM_CMD_SHIFT                     _MK_SHIFT_CONST(8)
+#define OWR_COMMAND_0_MEM_CMD_FIELD                     (_MK_MASK_CONST(0xff) << OWR_COMMAND_0_MEM_CMD_SHIFT)
+#define OWR_COMMAND_0_MEM_CMD_RANGE                     15:8
+#define OWR_COMMAND_0_MEM_CMD_WOFFSET                   0x0
+#define OWR_COMMAND_0_MEM_CMD_DEFAULT                   _MK_MASK_CONST(0x0)
+#define OWR_COMMAND_0_MEM_CMD_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define OWR_COMMAND_0_MEM_CMD_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define OWR_COMMAND_0_MEM_CMD_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+//Eprom Starting Address[15:0] to write/read data into Eprom
+#define OWR_COMMAND_0_MEM_ADDR_SHIFT                    _MK_SHIFT_CONST(16)
+#define OWR_COMMAND_0_MEM_ADDR_FIELD                    (_MK_MASK_CONST(0xffff) << OWR_COMMAND_0_MEM_ADDR_SHIFT)
+#define OWR_COMMAND_0_MEM_ADDR_RANGE                    31:16
+#define OWR_COMMAND_0_MEM_ADDR_WOFFSET                  0x0
+#define OWR_COMMAND_0_MEM_ADDR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define OWR_COMMAND_0_MEM_ADDR_DEFAULT_MASK                     _MK_MASK_CONST(0xffff)
+#define OWR_COMMAND_0_MEM_ADDR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define OWR_COMMAND_0_MEM_ADDR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register OWR_EPROM_0  
+#define OWR_EPROM_0                     _MK_ADDR_CONST(0x8)
+#define OWR_EPROM_0_SECURE                      0x0
+#define OWR_EPROM_0_WORD_COUNT                  0x1
+#define OWR_EPROM_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define OWR_EPROM_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define OWR_EPROM_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define OWR_EPROM_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define OWR_EPROM_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define OWR_EPROM_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+// Num of Eprom memory bytes to transfer, 
+// Mem_Addr - Eprom end address
+#define OWR_EPROM_0_MEMORY_BYTES_TRANSFER_SHIFT                 _MK_SHIFT_CONST(0)
+#define OWR_EPROM_0_MEMORY_BYTES_TRANSFER_FIELD                 (_MK_MASK_CONST(0xffff) << OWR_EPROM_0_MEMORY_BYTES_TRANSFER_SHIFT)
+#define OWR_EPROM_0_MEMORY_BYTES_TRANSFER_RANGE                 15:0
+#define OWR_EPROM_0_MEMORY_BYTES_TRANSFER_WOFFSET                       0x0
+#define OWR_EPROM_0_MEMORY_BYTES_TRANSFER_DEFAULT                       _MK_MASK_CONST(0x0)
+#define OWR_EPROM_0_MEMORY_BYTES_TRANSFER_DEFAULT_MASK                  _MK_MASK_CONST(0xffff)
+#define OWR_EPROM_0_MEMORY_BYTES_TRANSFER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define OWR_EPROM_0_MEMORY_BYTES_TRANSFER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Num of Eprom Status bytes to transfer, 
+// Mem_Addr - Status bytes end address
+#define OWR_EPROM_0_STATUS_BYTES_TRANSFER_SHIFT                 _MK_SHIFT_CONST(16)
+#define OWR_EPROM_0_STATUS_BYTES_TRANSFER_FIELD                 (_MK_MASK_CONST(0xffff) << OWR_EPROM_0_STATUS_BYTES_TRANSFER_SHIFT)
+#define OWR_EPROM_0_STATUS_BYTES_TRANSFER_RANGE                 31:16
+#define OWR_EPROM_0_STATUS_BYTES_TRANSFER_WOFFSET                       0x0
+#define OWR_EPROM_0_STATUS_BYTES_TRANSFER_DEFAULT                       _MK_MASK_CONST(0x0)
+#define OWR_EPROM_0_STATUS_BYTES_TRANSFER_DEFAULT_MASK                  _MK_MASK_CONST(0xffff)
+#define OWR_EPROM_0_STATUS_BYTES_TRANSFER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define OWR_EPROM_0_STATUS_BYTES_TRANSFER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register OWR_WR_RD_TCTL_0  
+#define OWR_WR_RD_TCTL_0                        _MK_ADDR_CONST(0xc)
+#define OWR_WR_RD_TCTL_0_SECURE                         0x0
+#define OWR_WR_RD_TCTL_0_WORD_COUNT                     0x1
+#define OWR_WR_RD_TCTL_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define OWR_WR_RD_TCTL_0_RESET_MASK                     _MK_MASK_CONST(0x3fffffff)
+#define OWR_WR_RD_TCTL_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define OWR_WR_RD_TCTL_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define OWR_WR_RD_TCTL_0_READ_MASK                      _MK_MASK_CONST(0x3fffffff)
+#define OWR_WR_RD_TCTL_0_WRITE_MASK                     _MK_MASK_CONST(0x3fffffff)
+// Active time slot for write or read data,
+// Tslot = N+1 owr clks,    Range = 60 <= tslot < 120
+#define OWR_WR_RD_TCTL_0_TSLOT_SHIFT                    _MK_SHIFT_CONST(0)
+#define OWR_WR_RD_TCTL_0_TSLOT_FIELD                    (_MK_MASK_CONST(0x7f) << OWR_WR_RD_TCTL_0_TSLOT_SHIFT)
+#define OWR_WR_RD_TCTL_0_TSLOT_RANGE                    6:0
+#define OWR_WR_RD_TCTL_0_TSLOT_WOFFSET                  0x0
+#define OWR_WR_RD_TCTL_0_TSLOT_DEFAULT                  _MK_MASK_CONST(0x0)
+#define OWR_WR_RD_TCTL_0_TSLOT_DEFAULT_MASK                     _MK_MASK_CONST(0x7f)
+#define OWR_WR_RD_TCTL_0_TSLOT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define OWR_WR_RD_TCTL_0_TSLOT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Write one time Low, or TLOWR both are same
+// Tlow1 = N+1 owr clks,    Range = 1 <= tlow1 < 15
+// TlowR = N+1 owr clks,    Range = 1 <= tlowR < 15
+#define OWR_WR_RD_TCTL_0_TLOW1_SHIFT                    _MK_SHIFT_CONST(7)
+#define OWR_WR_RD_TCTL_0_TLOW1_FIELD                    (_MK_MASK_CONST(0xf) << OWR_WR_RD_TCTL_0_TLOW1_SHIFT)
+#define OWR_WR_RD_TCTL_0_TLOW1_RANGE                    10:7
+#define OWR_WR_RD_TCTL_0_TLOW1_WOFFSET                  0x0
+#define OWR_WR_RD_TCTL_0_TLOW1_DEFAULT                  _MK_MASK_CONST(0x0)
+#define OWR_WR_RD_TCTL_0_TLOW1_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
+#define OWR_WR_RD_TCTL_0_TLOW1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define OWR_WR_RD_TCTL_0_TLOW1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Write Zero time Low,
+// Tlow0 = N+1 owr clks,    Range = 60 <= tlow0 < tslot < 120
+#define OWR_WR_RD_TCTL_0_TLOW0_SHIFT                    _MK_SHIFT_CONST(11)
+#define OWR_WR_RD_TCTL_0_TLOW0_FIELD                    (_MK_MASK_CONST(0x7f) << OWR_WR_RD_TCTL_0_TLOW0_SHIFT)
+#define OWR_WR_RD_TCTL_0_TLOW0_RANGE                    17:11
+#define OWR_WR_RD_TCTL_0_TLOW0_WOFFSET                  0x0
+#define OWR_WR_RD_TCTL_0_TLOW0_DEFAULT                  _MK_MASK_CONST(0x0)
+#define OWR_WR_RD_TCTL_0_TLOW0_DEFAULT_MASK                     _MK_MASK_CONST(0x7f)
+#define OWR_WR_RD_TCTL_0_TLOW0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define OWR_WR_RD_TCTL_0_TLOW0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Read data valid time,
+// Trdv  = N+1 owr clks,    Range = Exactly 15
+#define OWR_WR_RD_TCTL_0_TRDV_SHIFT                     _MK_SHIFT_CONST(18)
+#define OWR_WR_RD_TCTL_0_TRDV_FIELD                     (_MK_MASK_CONST(0xf) << OWR_WR_RD_TCTL_0_TRDV_SHIFT)
+#define OWR_WR_RD_TCTL_0_TRDV_RANGE                     21:18
+#define OWR_WR_RD_TCTL_0_TRDV_WOFFSET                   0x0
+#define OWR_WR_RD_TCTL_0_TRDV_DEFAULT                   _MK_MASK_CONST(0x0)
+#define OWR_WR_RD_TCTL_0_TRDV_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define OWR_WR_RD_TCTL_0_TRDV_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define OWR_WR_RD_TCTL_0_TRDV_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Release 1-wire Time,
+// Trelease = N owr clks,   Range = 0 <= trelease < 45
+#define OWR_WR_RD_TCTL_0_TRELEASE_SHIFT                 _MK_SHIFT_CONST(22)
+#define OWR_WR_RD_TCTL_0_TRELEASE_FIELD                 (_MK_MASK_CONST(0x3f) << OWR_WR_RD_TCTL_0_TRELEASE_SHIFT)
+#define OWR_WR_RD_TCTL_0_TRELEASE_RANGE                 27:22
+#define OWR_WR_RD_TCTL_0_TRELEASE_WOFFSET                       0x0
+#define OWR_WR_RD_TCTL_0_TRELEASE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define OWR_WR_RD_TCTL_0_TRELEASE_DEFAULT_MASK                  _MK_MASK_CONST(0x3f)
+#define OWR_WR_RD_TCTL_0_TRELEASE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define OWR_WR_RD_TCTL_0_TRELEASE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Read Data Setup,
+// Tsu = N owr clks,        Range = tsu < 1 
+#define OWR_WR_RD_TCTL_0_TSU_SHIFT                      _MK_SHIFT_CONST(28)
+#define OWR_WR_RD_TCTL_0_TSU_FIELD                      (_MK_MASK_CONST(0x3) << OWR_WR_RD_TCTL_0_TSU_SHIFT)
+#define OWR_WR_RD_TCTL_0_TSU_RANGE                      29:28
+#define OWR_WR_RD_TCTL_0_TSU_WOFFSET                    0x0
+#define OWR_WR_RD_TCTL_0_TSU_DEFAULT                    _MK_MASK_CONST(0x0)
+#define OWR_WR_RD_TCTL_0_TSU_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define OWR_WR_RD_TCTL_0_TSU_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define OWR_WR_RD_TCTL_0_TSU_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register OWR_RST_PRESENCE_TCTL_0  
+#define OWR_RST_PRESENCE_TCTL_0                 _MK_ADDR_CONST(0x10)
+#define OWR_RST_PRESENCE_TCTL_0_SECURE                  0x0
+#define OWR_RST_PRESENCE_TCTL_0_WORD_COUNT                      0x1
+#define OWR_RST_PRESENCE_TCTL_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define OWR_RST_PRESENCE_TCTL_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define OWR_RST_PRESENCE_TCTL_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define OWR_RST_PRESENCE_TCTL_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define OWR_RST_PRESENCE_TCTL_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define OWR_RST_PRESENCE_TCTL_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// RESET_TIME_HIGH,
+// Trsth = N+1 owr clks, Range = 480 <= trsth < infinity  
+#define OWR_RST_PRESENCE_TCTL_0_TRSTH_SHIFT                     _MK_SHIFT_CONST(0)
+#define OWR_RST_PRESENCE_TCTL_0_TRSTH_FIELD                     (_MK_MASK_CONST(0x1ff) << OWR_RST_PRESENCE_TCTL_0_TRSTH_SHIFT)
+#define OWR_RST_PRESENCE_TCTL_0_TRSTH_RANGE                     8:0
+#define OWR_RST_PRESENCE_TCTL_0_TRSTH_WOFFSET                   0x0
+#define OWR_RST_PRESENCE_TCTL_0_TRSTH_DEFAULT                   _MK_MASK_CONST(0x0)
+#define OWR_RST_PRESENCE_TCTL_0_TRSTH_DEFAULT_MASK                      _MK_MASK_CONST(0x1ff)
+#define OWR_RST_PRESENCE_TCTL_0_TRSTH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define OWR_RST_PRESENCE_TCTL_0_TRSTH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// RESET_TIME_LOW 
+// Trstl = N+1 owr clks, Range = 480 <= trstl < infinity  
+#define OWR_RST_PRESENCE_TCTL_0_TRSTL_SHIFT                     _MK_SHIFT_CONST(9)
+#define OWR_RST_PRESENCE_TCTL_0_TRSTL_FIELD                     (_MK_MASK_CONST(0x1ff) << OWR_RST_PRESENCE_TCTL_0_TRSTL_SHIFT)
+#define OWR_RST_PRESENCE_TCTL_0_TRSTL_RANGE                     17:9
+#define OWR_RST_PRESENCE_TCTL_0_TRSTL_WOFFSET                   0x0
+#define OWR_RST_PRESENCE_TCTL_0_TRSTL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define OWR_RST_PRESENCE_TCTL_0_TRSTL_DEFAULT_MASK                      _MK_MASK_CONST(0x1ff)
+#define OWR_RST_PRESENCE_TCTL_0_TRSTL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define OWR_RST_PRESENCE_TCTL_0_TRSTL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// PRESENCE_DETECT_HIGH  
+// Tpdh = N+1 owr clks,  Range = 15  <= tpdh < 60  
+#define OWR_RST_PRESENCE_TCTL_0_TPDH_SHIFT                      _MK_SHIFT_CONST(18)
+#define OWR_RST_PRESENCE_TCTL_0_TPDH_FIELD                      (_MK_MASK_CONST(0x3f) << OWR_RST_PRESENCE_TCTL_0_TPDH_SHIFT)
+#define OWR_RST_PRESENCE_TCTL_0_TPDH_RANGE                      23:18
+#define OWR_RST_PRESENCE_TCTL_0_TPDH_WOFFSET                    0x0
+#define OWR_RST_PRESENCE_TCTL_0_TPDH_DEFAULT                    _MK_MASK_CONST(0x0)
+#define OWR_RST_PRESENCE_TCTL_0_TPDH_DEFAULT_MASK                       _MK_MASK_CONST(0x3f)
+#define OWR_RST_PRESENCE_TCTL_0_TPDH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define OWR_RST_PRESENCE_TCTL_0_TPDH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// PRESENCE_DETECT_LOW 
+// Tpdl = N owr clks,    Range = 60  <= tpdl < 240  
+#define OWR_RST_PRESENCE_TCTL_0_TPDL_SHIFT                      _MK_SHIFT_CONST(24)
+#define OWR_RST_PRESENCE_TCTL_0_TPDL_FIELD                      (_MK_MASK_CONST(0xff) << OWR_RST_PRESENCE_TCTL_0_TPDL_SHIFT)
+#define OWR_RST_PRESENCE_TCTL_0_TPDL_RANGE                      31:24
+#define OWR_RST_PRESENCE_TCTL_0_TPDL_WOFFSET                    0x0
+#define OWR_RST_PRESENCE_TCTL_0_TPDL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define OWR_RST_PRESENCE_TCTL_0_TPDL_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
+#define OWR_RST_PRESENCE_TCTL_0_TPDL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define OWR_RST_PRESENCE_TCTL_0_TPDL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register OWR_PPM_CORRECTION_TCTL_0  
+#define OWR_PPM_CORRECTION_TCTL_0                       _MK_ADDR_CONST(0x14)
+#define OWR_PPM_CORRECTION_TCTL_0_SECURE                        0x0
+#define OWR_PPM_CORRECTION_TCTL_0_WORD_COUNT                    0x1
+#define OWR_PPM_CORRECTION_TCTL_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define OWR_PPM_CORRECTION_TCTL_0_RESET_MASK                    _MK_MASK_CONST(0xffff)
+#define OWR_PPM_CORRECTION_TCTL_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define OWR_PPM_CORRECTION_TCTL_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define OWR_PPM_CORRECTION_TCTL_0_READ_MASK                     _MK_MASK_CONST(0xffff)
+#define OWR_PPM_CORRECTION_TCTL_0_WRITE_MASK                    _MK_MASK_CONST(0xffff)
+// PRESENCE PULSE MASK START
+#define OWR_PPM_CORRECTION_TCTL_0_TPPM1_SHIFT                   _MK_SHIFT_CONST(0)
+#define OWR_PPM_CORRECTION_TCTL_0_TPPM1_FIELD                   (_MK_MASK_CONST(0x3f) << OWR_PPM_CORRECTION_TCTL_0_TPPM1_SHIFT)
+#define OWR_PPM_CORRECTION_TCTL_0_TPPM1_RANGE                   5:0
+#define OWR_PPM_CORRECTION_TCTL_0_TPPM1_WOFFSET                 0x0
+#define OWR_PPM_CORRECTION_TCTL_0_TPPM1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define OWR_PPM_CORRECTION_TCTL_0_TPPM1_DEFAULT_MASK                    _MK_MASK_CONST(0x3f)
+#define OWR_PPM_CORRECTION_TCTL_0_TPPM1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define OWR_PPM_CORRECTION_TCTL_0_TPPM1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// PRESENCE PULSE MASK STOP 
+#define OWR_PPM_CORRECTION_TCTL_0_TPPM2_SHIFT                   _MK_SHIFT_CONST(6)
+#define OWR_PPM_CORRECTION_TCTL_0_TPPM2_FIELD                   (_MK_MASK_CONST(0x3ff) << OWR_PPM_CORRECTION_TCTL_0_TPPM2_SHIFT)
+#define OWR_PPM_CORRECTION_TCTL_0_TPPM2_RANGE                   15:6
+#define OWR_PPM_CORRECTION_TCTL_0_TPPM2_WOFFSET                 0x0
+#define OWR_PPM_CORRECTION_TCTL_0_TPPM2_DEFAULT                 _MK_MASK_CONST(0x0)
+#define OWR_PPM_CORRECTION_TCTL_0_TPPM2_DEFAULT_MASK                    _MK_MASK_CONST(0x3ff)
+#define OWR_PPM_CORRECTION_TCTL_0_TPPM2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define OWR_PPM_CORRECTION_TCTL_0_TPPM2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register OWR_PROG_PULSE_TCTL_0  
+#define OWR_PROG_PULSE_TCTL_0                   _MK_ADDR_CONST(0x18)
+#define OWR_PROG_PULSE_TCTL_0_SECURE                    0x0
+#define OWR_PROG_PULSE_TCTL_0_WORD_COUNT                        0x1
+#define OWR_PROG_PULSE_TCTL_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define OWR_PROG_PULSE_TCTL_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
+#define OWR_PROG_PULSE_TCTL_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define OWR_PROG_PULSE_TCTL_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define OWR_PROG_PULSE_TCTL_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define OWR_PROG_PULSE_TCTL_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
+// Delay to program 
+// Tpd = N+1 owr clks, Range = > 5  
+#define OWR_PROG_PULSE_TCTL_0_TPD_SHIFT                 _MK_SHIFT_CONST(0)
+#define OWR_PROG_PULSE_TCTL_0_TPD_FIELD                 (_MK_MASK_CONST(0xf) << OWR_PROG_PULSE_TCTL_0_TPD_SHIFT)
+#define OWR_PROG_PULSE_TCTL_0_TPD_RANGE                 3:0
+#define OWR_PROG_PULSE_TCTL_0_TPD_WOFFSET                       0x0
+#define OWR_PROG_PULSE_TCTL_0_TPD_DEFAULT                       _MK_MASK_CONST(0x0)
+#define OWR_PROG_PULSE_TCTL_0_TPD_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define OWR_PROG_PULSE_TCTL_0_TPD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define OWR_PROG_PULSE_TCTL_0_TPD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Delay to verify
+// Tdv = N owr clks,   Range = > 5       
+#define OWR_PROG_PULSE_TCTL_0_TDV_SHIFT                 _MK_SHIFT_CONST(4)
+#define OWR_PROG_PULSE_TCTL_0_TDV_FIELD                 (_MK_MASK_CONST(0xf) << OWR_PROG_PULSE_TCTL_0_TDV_SHIFT)
+#define OWR_PROG_PULSE_TCTL_0_TDV_RANGE                 7:4
+#define OWR_PROG_PULSE_TCTL_0_TDV_WOFFSET                       0x0
+#define OWR_PROG_PULSE_TCTL_0_TDV_DEFAULT                       _MK_MASK_CONST(0x0)
+#define OWR_PROG_PULSE_TCTL_0_TDV_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define OWR_PROG_PULSE_TCTL_0_TDV_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define OWR_PROG_PULSE_TCTL_0_TDV_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Program Voltage Rise Time
+// Trp = N owr clks    Range = 0.5 to 5 
+#define OWR_PROG_PULSE_TCTL_0_TRP_SHIFT                 _MK_SHIFT_CONST(8)
+#define OWR_PROG_PULSE_TCTL_0_TRP_FIELD                 (_MK_MASK_CONST(0xf) << OWR_PROG_PULSE_TCTL_0_TRP_SHIFT)
+#define OWR_PROG_PULSE_TCTL_0_TRP_RANGE                 11:8
+#define OWR_PROG_PULSE_TCTL_0_TRP_WOFFSET                       0x0
+#define OWR_PROG_PULSE_TCTL_0_TRP_DEFAULT                       _MK_MASK_CONST(0x0)
+#define OWR_PROG_PULSE_TCTL_0_TRP_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define OWR_PROG_PULSE_TCTL_0_TRP_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define OWR_PROG_PULSE_TCTL_0_TRP_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Program Voltage Fall Time
+// Tfp = N owr clks    Range = 0.5 to 5 
+#define OWR_PROG_PULSE_TCTL_0_TFP_SHIFT                 _MK_SHIFT_CONST(12)
+#define OWR_PROG_PULSE_TCTL_0_TFP_FIELD                 (_MK_MASK_CONST(0xf) << OWR_PROG_PULSE_TCTL_0_TFP_SHIFT)
+#define OWR_PROG_PULSE_TCTL_0_TFP_RANGE                 15:12
+#define OWR_PROG_PULSE_TCTL_0_TFP_WOFFSET                       0x0
+#define OWR_PROG_PULSE_TCTL_0_TFP_DEFAULT                       _MK_MASK_CONST(0x0)
+#define OWR_PROG_PULSE_TCTL_0_TFP_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define OWR_PROG_PULSE_TCTL_0_TFP_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define OWR_PROG_PULSE_TCTL_0_TFP_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Program Pulse Width
+// Tpp = N owr clks    Range = 480 to 5000 
+#define OWR_PROG_PULSE_TCTL_0_TPP_SHIFT                 _MK_SHIFT_CONST(16)
+#define OWR_PROG_PULSE_TCTL_0_TPP_FIELD                 (_MK_MASK_CONST(0xffff) << OWR_PROG_PULSE_TCTL_0_TPP_SHIFT)
+#define OWR_PROG_PULSE_TCTL_0_TPP_RANGE                 31:16
+#define OWR_PROG_PULSE_TCTL_0_TPP_WOFFSET                       0x0
+#define OWR_PROG_PULSE_TCTL_0_TPP_DEFAULT                       _MK_MASK_CONST(0x0)
+#define OWR_PROG_PULSE_TCTL_0_TPP_DEFAULT_MASK                  _MK_MASK_CONST(0xffff)
+#define OWR_PROG_PULSE_TCTL_0_TPP_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define OWR_PROG_PULSE_TCTL_0_TPP_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register OWR_READ_ROM0_0  
+#define OWR_READ_ROM0_0                 _MK_ADDR_CONST(0x1c)
+#define OWR_READ_ROM0_0_SECURE                  0x0
+#define OWR_READ_ROM0_0_WORD_COUNT                      0x1
+#define OWR_READ_ROM0_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define OWR_READ_ROM0_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define OWR_READ_ROM0_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define OWR_READ_ROM0_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define OWR_READ_ROM0_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define OWR_READ_ROM0_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
+// Reads the 8 bit family code of ROM 
+#define OWR_READ_ROM0_0_FAMILY_CODE_SHIFT                       _MK_SHIFT_CONST(0)
+#define OWR_READ_ROM0_0_FAMILY_CODE_FIELD                       (_MK_MASK_CONST(0xff) << OWR_READ_ROM0_0_FAMILY_CODE_SHIFT)
+#define OWR_READ_ROM0_0_FAMILY_CODE_RANGE                       7:0
+#define OWR_READ_ROM0_0_FAMILY_CODE_WOFFSET                     0x0
+#define OWR_READ_ROM0_0_FAMILY_CODE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define OWR_READ_ROM0_0_FAMILY_CODE_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define OWR_READ_ROM0_0_FAMILY_CODE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define OWR_READ_ROM0_0_FAMILY_CODE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Reads the first 24 bits of rom  serial number
+#define OWR_READ_ROM0_0_SERIAL_NUM0_SHIFT                       _MK_SHIFT_CONST(8)
+#define OWR_READ_ROM0_0_SERIAL_NUM0_FIELD                       (_MK_MASK_CONST(0xffffff) << OWR_READ_ROM0_0_SERIAL_NUM0_SHIFT)
+#define OWR_READ_ROM0_0_SERIAL_NUM0_RANGE                       31:8
+#define OWR_READ_ROM0_0_SERIAL_NUM0_WOFFSET                     0x0
+#define OWR_READ_ROM0_0_SERIAL_NUM0_DEFAULT                     _MK_MASK_CONST(0x0)
+#define OWR_READ_ROM0_0_SERIAL_NUM0_DEFAULT_MASK                        _MK_MASK_CONST(0xffffff)
+#define OWR_READ_ROM0_0_SERIAL_NUM0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define OWR_READ_ROM0_0_SERIAL_NUM0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register OWR_READ_ROM1_0  
+#define OWR_READ_ROM1_0                 _MK_ADDR_CONST(0x20)
+#define OWR_READ_ROM1_0_SECURE                  0x0
+#define OWR_READ_ROM1_0_WORD_COUNT                      0x1
+#define OWR_READ_ROM1_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define OWR_READ_ROM1_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define OWR_READ_ROM1_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define OWR_READ_ROM1_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define OWR_READ_ROM1_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define OWR_READ_ROM1_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
+// Reads the next 24 bits of rom serial number
+#define OWR_READ_ROM1_0_SERIAL_NUM1_SHIFT                       _MK_SHIFT_CONST(0)
+#define OWR_READ_ROM1_0_SERIAL_NUM1_FIELD                       (_MK_MASK_CONST(0xffffff) << OWR_READ_ROM1_0_SERIAL_NUM1_SHIFT)
+#define OWR_READ_ROM1_0_SERIAL_NUM1_RANGE                       23:0
+#define OWR_READ_ROM1_0_SERIAL_NUM1_WOFFSET                     0x0
+#define OWR_READ_ROM1_0_SERIAL_NUM1_DEFAULT                     _MK_MASK_CONST(0x0)
+#define OWR_READ_ROM1_0_SERIAL_NUM1_DEFAULT_MASK                        _MK_MASK_CONST(0xffffff)
+#define OWR_READ_ROM1_0_SERIAL_NUM1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define OWR_READ_ROM1_0_SERIAL_NUM1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Reads the 8 bit CRC code of ROM
+#define OWR_READ_ROM1_0_CRC_BYTE_SHIFT                  _MK_SHIFT_CONST(24)
+#define OWR_READ_ROM1_0_CRC_BYTE_FIELD                  (_MK_MASK_CONST(0xff) << OWR_READ_ROM1_0_CRC_BYTE_SHIFT)
+#define OWR_READ_ROM1_0_CRC_BYTE_RANGE                  31:24
+#define OWR_READ_ROM1_0_CRC_BYTE_WOFFSET                        0x0
+#define OWR_READ_ROM1_0_CRC_BYTE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define OWR_READ_ROM1_0_CRC_BYTE_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
+#define OWR_READ_ROM1_0_CRC_BYTE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define OWR_READ_ROM1_0_CRC_BYTE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register OWR_INTR_MASK_0  
+#define OWR_INTR_MASK_0                 _MK_ADDR_CONST(0x24)
+#define OWR_INTR_MASK_0_SECURE                  0x0
+#define OWR_INTR_MASK_0_WORD_COUNT                      0x1
+#define OWR_INTR_MASK_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define OWR_INTR_MASK_0_RESET_MASK                      _MK_MASK_CONST(0x3fff)
+#define OWR_INTR_MASK_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define OWR_INTR_MASK_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define OWR_INTR_MASK_0_READ_MASK                       _MK_MASK_CONST(0x3fff)
+#define OWR_INTR_MASK_0_WRITE_MASK                      _MK_MASK_CONST(0x3fff)
+#define OWR_INTR_MASK_0_PRESENCE_ERR_INT_EN_SHIFT                       _MK_SHIFT_CONST(0)
+#define OWR_INTR_MASK_0_PRESENCE_ERR_INT_EN_FIELD                       (_MK_MASK_CONST(0x1) << OWR_INTR_MASK_0_PRESENCE_ERR_INT_EN_SHIFT)
+#define OWR_INTR_MASK_0_PRESENCE_ERR_INT_EN_RANGE                       0:0
+#define OWR_INTR_MASK_0_PRESENCE_ERR_INT_EN_WOFFSET                     0x0
+#define OWR_INTR_MASK_0_PRESENCE_ERR_INT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define OWR_INTR_MASK_0_PRESENCE_ERR_INT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define OWR_INTR_MASK_0_PRESENCE_ERR_INT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define OWR_INTR_MASK_0_PRESENCE_ERR_INT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define OWR_INTR_MASK_0_PRESENCE_ERR_INT_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define OWR_INTR_MASK_0_PRESENCE_ERR_INT_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+#define OWR_INTR_MASK_0_CRC_ERR_INT_EN_SHIFT                    _MK_SHIFT_CONST(1)
+#define OWR_INTR_MASK_0_CRC_ERR_INT_EN_FIELD                    (_MK_MASK_CONST(0x1) << OWR_INTR_MASK_0_CRC_ERR_INT_EN_SHIFT)
+#define OWR_INTR_MASK_0_CRC_ERR_INT_EN_RANGE                    1:1
+#define OWR_INTR_MASK_0_CRC_ERR_INT_EN_WOFFSET                  0x0
+#define OWR_INTR_MASK_0_CRC_ERR_INT_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define OWR_INTR_MASK_0_CRC_ERR_INT_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define OWR_INTR_MASK_0_CRC_ERR_INT_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define OWR_INTR_MASK_0_CRC_ERR_INT_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define OWR_INTR_MASK_0_CRC_ERR_INT_EN_DISABLE                  _MK_ENUM_CONST(0)
+#define OWR_INTR_MASK_0_CRC_ERR_INT_EN_ENABLE                   _MK_ENUM_CONST(1)
+
+#define OWR_INTR_MASK_0_MEM_WR_ERR_INT_EN_SHIFT                 _MK_SHIFT_CONST(2)
+#define OWR_INTR_MASK_0_MEM_WR_ERR_INT_EN_FIELD                 (_MK_MASK_CONST(0x1) << OWR_INTR_MASK_0_MEM_WR_ERR_INT_EN_SHIFT)
+#define OWR_INTR_MASK_0_MEM_WR_ERR_INT_EN_RANGE                 2:2
+#define OWR_INTR_MASK_0_MEM_WR_ERR_INT_EN_WOFFSET                       0x0
+#define OWR_INTR_MASK_0_MEM_WR_ERR_INT_EN_DEFAULT                       _MK_MASK_CONST(0x0)
+#define OWR_INTR_MASK_0_MEM_WR_ERR_INT_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define OWR_INTR_MASK_0_MEM_WR_ERR_INT_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define OWR_INTR_MASK_0_MEM_WR_ERR_INT_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define OWR_INTR_MASK_0_MEM_WR_ERR_INT_EN_DISABLE                       _MK_ENUM_CONST(0)
+#define OWR_INTR_MASK_0_MEM_WR_ERR_INT_EN_ENABLE                        _MK_ENUM_CONST(1)
+
+#define OWR_INTR_MASK_0_ERR_CMD_INT_EN_SHIFT                    _MK_SHIFT_CONST(3)
+#define OWR_INTR_MASK_0_ERR_CMD_INT_EN_FIELD                    (_MK_MASK_CONST(0x1) << OWR_INTR_MASK_0_ERR_CMD_INT_EN_SHIFT)
+#define OWR_INTR_MASK_0_ERR_CMD_INT_EN_RANGE                    3:3
+#define OWR_INTR_MASK_0_ERR_CMD_INT_EN_WOFFSET                  0x0
+#define OWR_INTR_MASK_0_ERR_CMD_INT_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define OWR_INTR_MASK_0_ERR_CMD_INT_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define OWR_INTR_MASK_0_ERR_CMD_INT_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define OWR_INTR_MASK_0_ERR_CMD_INT_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define OWR_INTR_MASK_0_ERR_CMD_INT_EN_DISABLE                  _MK_ENUM_CONST(0)
+#define OWR_INTR_MASK_0_ERR_CMD_INT_EN_ENABLE                   _MK_ENUM_CONST(1)
+
+#define OWR_INTR_MASK_0_RESET_DONE_INT_EN_SHIFT                 _MK_SHIFT_CONST(4)
+#define OWR_INTR_MASK_0_RESET_DONE_INT_EN_FIELD                 (_MK_MASK_CONST(0x1) << OWR_INTR_MASK_0_RESET_DONE_INT_EN_SHIFT)
+#define OWR_INTR_MASK_0_RESET_DONE_INT_EN_RANGE                 4:4
+#define OWR_INTR_MASK_0_RESET_DONE_INT_EN_WOFFSET                       0x0
+#define OWR_INTR_MASK_0_RESET_DONE_INT_EN_DEFAULT                       _MK_MASK_CONST(0x0)
+#define OWR_INTR_MASK_0_RESET_DONE_INT_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define OWR_INTR_MASK_0_RESET_DONE_INT_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define OWR_INTR_MASK_0_RESET_DONE_INT_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define OWR_INTR_MASK_0_RESET_DONE_INT_EN_DISABLE                       _MK_ENUM_CONST(0)
+#define OWR_INTR_MASK_0_RESET_DONE_INT_EN_ENABLE                        _MK_ENUM_CONST(1)
+
+#define OWR_INTR_MASK_0_PRESENCE_DONE_INT_EN_SHIFT                      _MK_SHIFT_CONST(5)
+#define OWR_INTR_MASK_0_PRESENCE_DONE_INT_EN_FIELD                      (_MK_MASK_CONST(0x1) << OWR_INTR_MASK_0_PRESENCE_DONE_INT_EN_SHIFT)
+#define OWR_INTR_MASK_0_PRESENCE_DONE_INT_EN_RANGE                      5:5
+#define OWR_INTR_MASK_0_PRESENCE_DONE_INT_EN_WOFFSET                    0x0
+#define OWR_INTR_MASK_0_PRESENCE_DONE_INT_EN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define OWR_INTR_MASK_0_PRESENCE_DONE_INT_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define OWR_INTR_MASK_0_PRESENCE_DONE_INT_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define OWR_INTR_MASK_0_PRESENCE_DONE_INT_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define OWR_INTR_MASK_0_PRESENCE_DONE_INT_EN_DISABLE                    _MK_ENUM_CONST(0)
+#define OWR_INTR_MASK_0_PRESENCE_DONE_INT_EN_ENABLE                     _MK_ENUM_CONST(1)
+
+#define OWR_INTR_MASK_0_ROM_CMD_DONE_INT_EN_SHIFT                       _MK_SHIFT_CONST(6)
+#define OWR_INTR_MASK_0_ROM_CMD_DONE_INT_EN_FIELD                       (_MK_MASK_CONST(0x1) << OWR_INTR_MASK_0_ROM_CMD_DONE_INT_EN_SHIFT)
+#define OWR_INTR_MASK_0_ROM_CMD_DONE_INT_EN_RANGE                       6:6
+#define OWR_INTR_MASK_0_ROM_CMD_DONE_INT_EN_WOFFSET                     0x0
+#define OWR_INTR_MASK_0_ROM_CMD_DONE_INT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define OWR_INTR_MASK_0_ROM_CMD_DONE_INT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define OWR_INTR_MASK_0_ROM_CMD_DONE_INT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define OWR_INTR_MASK_0_ROM_CMD_DONE_INT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define OWR_INTR_MASK_0_ROM_CMD_DONE_INT_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define OWR_INTR_MASK_0_ROM_CMD_DONE_INT_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+#define OWR_INTR_MASK_0_MEM_CMD_DONE_INT_EN_SHIFT                       _MK_SHIFT_CONST(7)
+#define OWR_INTR_MASK_0_MEM_CMD_DONE_INT_EN_FIELD                       (_MK_MASK_CONST(0x1) << OWR_INTR_MASK_0_MEM_CMD_DONE_INT_EN_SHIFT)
+#define OWR_INTR_MASK_0_MEM_CMD_DONE_INT_EN_RANGE                       7:7
+#define OWR_INTR_MASK_0_MEM_CMD_DONE_INT_EN_WOFFSET                     0x0
+#define OWR_INTR_MASK_0_MEM_CMD_DONE_INT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define OWR_INTR_MASK_0_MEM_CMD_DONE_INT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define OWR_INTR_MASK_0_MEM_CMD_DONE_INT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define OWR_INTR_MASK_0_MEM_CMD_DONE_INT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define OWR_INTR_MASK_0_MEM_CMD_DONE_INT_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define OWR_INTR_MASK_0_MEM_CMD_DONE_INT_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+#define OWR_INTR_MASK_0_TXF_OVF_INT_EN_SHIFT                    _MK_SHIFT_CONST(8)
+#define OWR_INTR_MASK_0_TXF_OVF_INT_EN_FIELD                    (_MK_MASK_CONST(0x1) << OWR_INTR_MASK_0_TXF_OVF_INT_EN_SHIFT)
+#define OWR_INTR_MASK_0_TXF_OVF_INT_EN_RANGE                    8:8
+#define OWR_INTR_MASK_0_TXF_OVF_INT_EN_WOFFSET                  0x0
+#define OWR_INTR_MASK_0_TXF_OVF_INT_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define OWR_INTR_MASK_0_TXF_OVF_INT_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define OWR_INTR_MASK_0_TXF_OVF_INT_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define OWR_INTR_MASK_0_TXF_OVF_INT_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define OWR_INTR_MASK_0_TXF_OVF_INT_EN_DISABLE                  _MK_ENUM_CONST(0)
+#define OWR_INTR_MASK_0_TXF_OVF_INT_EN_ENABLE                   _MK_ENUM_CONST(1)
+
+#define OWR_INTR_MASK_0_RXF_UNR_INT_EN_SHIFT                    _MK_SHIFT_CONST(9)
+#define OWR_INTR_MASK_0_RXF_UNR_INT_EN_FIELD                    (_MK_MASK_CONST(0x1) << OWR_INTR_MASK_0_RXF_UNR_INT_EN_SHIFT)
+#define OWR_INTR_MASK_0_RXF_UNR_INT_EN_RANGE                    9:9
+#define OWR_INTR_MASK_0_RXF_UNR_INT_EN_WOFFSET                  0x0
+#define OWR_INTR_MASK_0_RXF_UNR_INT_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define OWR_INTR_MASK_0_RXF_UNR_INT_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define OWR_INTR_MASK_0_RXF_UNR_INT_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define OWR_INTR_MASK_0_RXF_UNR_INT_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define OWR_INTR_MASK_0_RXF_UNR_INT_EN_DISABLE                  _MK_ENUM_CONST(0)
+#define OWR_INTR_MASK_0_RXF_UNR_INT_EN_ENABLE                   _MK_ENUM_CONST(1)
+
+#define OWR_INTR_MASK_0_DGLITCH_INT_EN_SHIFT                    _MK_SHIFT_CONST(10)
+#define OWR_INTR_MASK_0_DGLITCH_INT_EN_FIELD                    (_MK_MASK_CONST(0x1) << OWR_INTR_MASK_0_DGLITCH_INT_EN_SHIFT)
+#define OWR_INTR_MASK_0_DGLITCH_INT_EN_RANGE                    10:10
+#define OWR_INTR_MASK_0_DGLITCH_INT_EN_WOFFSET                  0x0
+#define OWR_INTR_MASK_0_DGLITCH_INT_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define OWR_INTR_MASK_0_DGLITCH_INT_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define OWR_INTR_MASK_0_DGLITCH_INT_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define OWR_INTR_MASK_0_DGLITCH_INT_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define OWR_INTR_MASK_0_DGLITCH_INT_EN_DISABLE                  _MK_ENUM_CONST(0)
+#define OWR_INTR_MASK_0_DGLITCH_INT_EN_ENABLE                   _MK_ENUM_CONST(1)
+
+#define OWR_INTR_MASK_0_TXFIFO_DATA_REQ_INT_EN_SHIFT                    _MK_SHIFT_CONST(11)
+#define OWR_INTR_MASK_0_TXFIFO_DATA_REQ_INT_EN_FIELD                    (_MK_MASK_CONST(0x1) << OWR_INTR_MASK_0_TXFIFO_DATA_REQ_INT_EN_SHIFT)
+#define OWR_INTR_MASK_0_TXFIFO_DATA_REQ_INT_EN_RANGE                    11:11
+#define OWR_INTR_MASK_0_TXFIFO_DATA_REQ_INT_EN_WOFFSET                  0x0
+#define OWR_INTR_MASK_0_TXFIFO_DATA_REQ_INT_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define OWR_INTR_MASK_0_TXFIFO_DATA_REQ_INT_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define OWR_INTR_MASK_0_TXFIFO_DATA_REQ_INT_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define OWR_INTR_MASK_0_TXFIFO_DATA_REQ_INT_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define OWR_INTR_MASK_0_TXFIFO_DATA_REQ_INT_EN_DISABLE                  _MK_ENUM_CONST(0)
+#define OWR_INTR_MASK_0_TXFIFO_DATA_REQ_INT_EN_ENABLE                   _MK_ENUM_CONST(1)
+
+#define OWR_INTR_MASK_0_RXFIFO_DATA_REQ_INT_EN_SHIFT                    _MK_SHIFT_CONST(12)
+#define OWR_INTR_MASK_0_RXFIFO_DATA_REQ_INT_EN_FIELD                    (_MK_MASK_CONST(0x1) << OWR_INTR_MASK_0_RXFIFO_DATA_REQ_INT_EN_SHIFT)
+#define OWR_INTR_MASK_0_RXFIFO_DATA_REQ_INT_EN_RANGE                    12:12
+#define OWR_INTR_MASK_0_RXFIFO_DATA_REQ_INT_EN_WOFFSET                  0x0
+#define OWR_INTR_MASK_0_RXFIFO_DATA_REQ_INT_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define OWR_INTR_MASK_0_RXFIFO_DATA_REQ_INT_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define OWR_INTR_MASK_0_RXFIFO_DATA_REQ_INT_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define OWR_INTR_MASK_0_RXFIFO_DATA_REQ_INT_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define OWR_INTR_MASK_0_RXFIFO_DATA_REQ_INT_EN_DISABLE                  _MK_ENUM_CONST(0)
+#define OWR_INTR_MASK_0_RXFIFO_DATA_REQ_INT_EN_ENABLE                   _MK_ENUM_CONST(1)
+
+#define OWR_INTR_MASK_0_BIT_TRANSFER_DONE_INT_EN_SHIFT                  _MK_SHIFT_CONST(13)
+#define OWR_INTR_MASK_0_BIT_TRANSFER_DONE_INT_EN_FIELD                  (_MK_MASK_CONST(0x1) << OWR_INTR_MASK_0_BIT_TRANSFER_DONE_INT_EN_SHIFT)
+#define OWR_INTR_MASK_0_BIT_TRANSFER_DONE_INT_EN_RANGE                  13:13
+#define OWR_INTR_MASK_0_BIT_TRANSFER_DONE_INT_EN_WOFFSET                        0x0
+#define OWR_INTR_MASK_0_BIT_TRANSFER_DONE_INT_EN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define OWR_INTR_MASK_0_BIT_TRANSFER_DONE_INT_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define OWR_INTR_MASK_0_BIT_TRANSFER_DONE_INT_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define OWR_INTR_MASK_0_BIT_TRANSFER_DONE_INT_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define OWR_INTR_MASK_0_BIT_TRANSFER_DONE_INT_EN_DISABLE                        _MK_ENUM_CONST(0)
+#define OWR_INTR_MASK_0_BIT_TRANSFER_DONE_INT_EN_ENABLE                 _MK_ENUM_CONST(1)
+
+
+// Register OWR_INTR_STATUS_0  
+#define OWR_INTR_STATUS_0                       _MK_ADDR_CONST(0x28)
+#define OWR_INTR_STATUS_0_SECURE                        0x0
+#define OWR_INTR_STATUS_0_WORD_COUNT                    0x1
+#define OWR_INTR_STATUS_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define OWR_INTR_STATUS_0_RESET_MASK                    _MK_MASK_CONST(0x3fff)
+#define OWR_INTR_STATUS_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define OWR_INTR_STATUS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define OWR_INTR_STATUS_0_READ_MASK                     _MK_MASK_CONST(0x3fff)
+#define OWR_INTR_STATUS_0_WRITE_MASK                    _MK_MASK_CONST(0x27ff)
+// Presence ERROR. This bit is set when device presence not found  
+#define OWR_INTR_STATUS_0_PRESENCE_ERR_SHIFT                    _MK_SHIFT_CONST(0)
+#define OWR_INTR_STATUS_0_PRESENCE_ERR_FIELD                    (_MK_MASK_CONST(0x1) << OWR_INTR_STATUS_0_PRESENCE_ERR_SHIFT)
+#define OWR_INTR_STATUS_0_PRESENCE_ERR_RANGE                    0:0
+#define OWR_INTR_STATUS_0_PRESENCE_ERR_WOFFSET                  0x0
+#define OWR_INTR_STATUS_0_PRESENCE_ERR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define OWR_INTR_STATUS_0_PRESENCE_ERR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define OWR_INTR_STATUS_0_PRESENCE_ERR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define OWR_INTR_STATUS_0_PRESENCE_ERR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define OWR_INTR_STATUS_0_PRESENCE_ERR_SLAVE_DETECTED                   _MK_ENUM_CONST(0)
+#define OWR_INTR_STATUS_0_PRESENCE_ERR_NO_SLAVE_DETECTED                        _MK_ENUM_CONST(1)
+
+// CRC ERROR: Indicates the received data is correct or not
+// Software writes a 1 to clear it. 
+#define OWR_INTR_STATUS_0_CRC_ERR_SHIFT                 _MK_SHIFT_CONST(1)
+#define OWR_INTR_STATUS_0_CRC_ERR_FIELD                 (_MK_MASK_CONST(0x1) << OWR_INTR_STATUS_0_CRC_ERR_SHIFT)
+#define OWR_INTR_STATUS_0_CRC_ERR_RANGE                 1:1
+#define OWR_INTR_STATUS_0_CRC_ERR_WOFFSET                       0x0
+#define OWR_INTR_STATUS_0_CRC_ERR_DEFAULT                       _MK_MASK_CONST(0x0)
+#define OWR_INTR_STATUS_0_CRC_ERR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define OWR_INTR_STATUS_0_CRC_ERR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define OWR_INTR_STATUS_0_CRC_ERR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define OWR_INTR_STATUS_0_CRC_ERR_N0_ERROR                      _MK_ENUM_CONST(0)
+#define OWR_INTR_STATUS_0_CRC_ERR_ERROR                 _MK_ENUM_CONST(1)
+
+// MEM WR ERROR: Indicates the received data from eprom is correct or not
+// Software writes a 1 to clear it. 
+#define OWR_INTR_STATUS_0_MEM_WR_ERR_SHIFT                      _MK_SHIFT_CONST(2)
+#define OWR_INTR_STATUS_0_MEM_WR_ERR_FIELD                      (_MK_MASK_CONST(0x1) << OWR_INTR_STATUS_0_MEM_WR_ERR_SHIFT)
+#define OWR_INTR_STATUS_0_MEM_WR_ERR_RANGE                      2:2
+#define OWR_INTR_STATUS_0_MEM_WR_ERR_WOFFSET                    0x0
+#define OWR_INTR_STATUS_0_MEM_WR_ERR_DEFAULT                    _MK_MASK_CONST(0x0)
+#define OWR_INTR_STATUS_0_MEM_WR_ERR_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define OWR_INTR_STATUS_0_MEM_WR_ERR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define OWR_INTR_STATUS_0_MEM_WR_ERR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define OWR_INTR_STATUS_0_MEM_WR_ERR_N0_ERROR                   _MK_ENUM_CONST(0)
+#define OWR_INTR_STATUS_0_MEM_WR_ERR_ERROR                      _MK_ENUM_CONST(1)
+
+// ERROR CMD:Indicates error command written in the register
+// It should be ignored when transfer is in single bit mode 
+// Software writes a 1 to clear it. 
+#define OWR_INTR_STATUS_0_ERR_CMD_SHIFT                 _MK_SHIFT_CONST(3)
+#define OWR_INTR_STATUS_0_ERR_CMD_FIELD                 (_MK_MASK_CONST(0x1) << OWR_INTR_STATUS_0_ERR_CMD_SHIFT)
+#define OWR_INTR_STATUS_0_ERR_CMD_RANGE                 3:3
+#define OWR_INTR_STATUS_0_ERR_CMD_WOFFSET                       0x0
+#define OWR_INTR_STATUS_0_ERR_CMD_DEFAULT                       _MK_MASK_CONST(0x0)
+#define OWR_INTR_STATUS_0_ERR_CMD_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define OWR_INTR_STATUS_0_ERR_CMD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define OWR_INTR_STATUS_0_ERR_CMD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define OWR_INTR_STATUS_0_ERR_CMD_CORRECT_CMD                   _MK_ENUM_CONST(0)
+#define OWR_INTR_STATUS_0_ERR_CMD_ERROR_CMD                     _MK_ENUM_CONST(1)
+
+// This indicates the master has send the reset, then waits for presence
+// Software writes a 1 to clear it. 
+#define OWR_INTR_STATUS_0_RESET_DONE_SHIFT                      _MK_SHIFT_CONST(4)
+#define OWR_INTR_STATUS_0_RESET_DONE_FIELD                      (_MK_MASK_CONST(0x1) << OWR_INTR_STATUS_0_RESET_DONE_SHIFT)
+#define OWR_INTR_STATUS_0_RESET_DONE_RANGE                      4:4
+#define OWR_INTR_STATUS_0_RESET_DONE_WOFFSET                    0x0
+#define OWR_INTR_STATUS_0_RESET_DONE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define OWR_INTR_STATUS_0_RESET_DONE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define OWR_INTR_STATUS_0_RESET_DONE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define OWR_INTR_STATUS_0_RESET_DONE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define OWR_INTR_STATUS_0_RESET_DONE_NOT_DONE                   _MK_ENUM_CONST(0)
+#define OWR_INTR_STATUS_0_RESET_DONE_DONE                       _MK_ENUM_CONST(1)
+
+// This indicates the presence done, master has detected the device
+// Software writes a 1 to clear it. 
+#define OWR_INTR_STATUS_0_PRESENCE_DONE_SHIFT                   _MK_SHIFT_CONST(5)
+#define OWR_INTR_STATUS_0_PRESENCE_DONE_FIELD                   (_MK_MASK_CONST(0x1) << OWR_INTR_STATUS_0_PRESENCE_DONE_SHIFT)
+#define OWR_INTR_STATUS_0_PRESENCE_DONE_RANGE                   5:5
+#define OWR_INTR_STATUS_0_PRESENCE_DONE_WOFFSET                 0x0
+#define OWR_INTR_STATUS_0_PRESENCE_DONE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define OWR_INTR_STATUS_0_PRESENCE_DONE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define OWR_INTR_STATUS_0_PRESENCE_DONE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define OWR_INTR_STATUS_0_PRESENCE_DONE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define OWR_INTR_STATUS_0_PRESENCE_DONE_NOT_DONE                        _MK_ENUM_CONST(0)
+#define OWR_INTR_STATUS_0_PRESENCE_DONE_DONE                    _MK_ENUM_CONST(1)
+
+// This indicates master has received the rom data from battery
+// Software writes a 1 to clear it. 
+#define OWR_INTR_STATUS_0_ROM_CMD_DONE_SHIFT                    _MK_SHIFT_CONST(6)
+#define OWR_INTR_STATUS_0_ROM_CMD_DONE_FIELD                    (_MK_MASK_CONST(0x1) << OWR_INTR_STATUS_0_ROM_CMD_DONE_SHIFT)
+#define OWR_INTR_STATUS_0_ROM_CMD_DONE_RANGE                    6:6
+#define OWR_INTR_STATUS_0_ROM_CMD_DONE_WOFFSET                  0x0
+#define OWR_INTR_STATUS_0_ROM_CMD_DONE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define OWR_INTR_STATUS_0_ROM_CMD_DONE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define OWR_INTR_STATUS_0_ROM_CMD_DONE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define OWR_INTR_STATUS_0_ROM_CMD_DONE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define OWR_INTR_STATUS_0_ROM_CMD_DONE_NOT_DONE                 _MK_ENUM_CONST(0)
+#define OWR_INTR_STATUS_0_ROM_CMD_DONE_DONE                     _MK_ENUM_CONST(1)
+
+// This Indicates the master has written data into eprom or data received
+// from eprom without any error 
+// Software writes a 1 to clear it. 
+#define OWR_INTR_STATUS_0_MEM_CMD_DONE_SHIFT                    _MK_SHIFT_CONST(7)
+#define OWR_INTR_STATUS_0_MEM_CMD_DONE_FIELD                    (_MK_MASK_CONST(0x1) << OWR_INTR_STATUS_0_MEM_CMD_DONE_SHIFT)
+#define OWR_INTR_STATUS_0_MEM_CMD_DONE_RANGE                    7:7
+#define OWR_INTR_STATUS_0_MEM_CMD_DONE_WOFFSET                  0x0
+#define OWR_INTR_STATUS_0_MEM_CMD_DONE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define OWR_INTR_STATUS_0_MEM_CMD_DONE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define OWR_INTR_STATUS_0_MEM_CMD_DONE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define OWR_INTR_STATUS_0_MEM_CMD_DONE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define OWR_INTR_STATUS_0_MEM_CMD_DONE_NOT_DONE                 _MK_ENUM_CONST(0)
+#define OWR_INTR_STATUS_0_MEM_CMD_DONE_DONE                     _MK_ENUM_CONST(1)
+
+// TX FIFO Overflow: RO.  This bit is set to 1 whenever software tries 
+// to write to a full TX FIFO. 
+// Software writes a 1 to clear this bit. 
+#define OWR_INTR_STATUS_0_TXF_OVF_SHIFT                 _MK_SHIFT_CONST(8)
+#define OWR_INTR_STATUS_0_TXF_OVF_FIELD                 (_MK_MASK_CONST(0x1) << OWR_INTR_STATUS_0_TXF_OVF_SHIFT)
+#define OWR_INTR_STATUS_0_TXF_OVF_RANGE                 8:8
+#define OWR_INTR_STATUS_0_TXF_OVF_WOFFSET                       0x0
+#define OWR_INTR_STATUS_0_TXF_OVF_DEFAULT                       _MK_MASK_CONST(0x0)
+#define OWR_INTR_STATUS_0_TXF_OVF_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define OWR_INTR_STATUS_0_TXF_OVF_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define OWR_INTR_STATUS_0_TXF_OVF_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define OWR_INTR_STATUS_0_TXF_OVF_NOT_EMPTY                     _MK_ENUM_CONST(0)
+#define OWR_INTR_STATUS_0_TXF_OVF_EMPTY                 _MK_ENUM_CONST(1)
+
+// RX FIFO Under run: RO.  This bit is set to 1 whenever software tries to
+// read from an empty RX FIFO. 
+// Software writes a 1 to clear this bit. 
+#define OWR_INTR_STATUS_0_RXF_UNR_SHIFT                 _MK_SHIFT_CONST(9)
+#define OWR_INTR_STATUS_0_RXF_UNR_FIELD                 (_MK_MASK_CONST(0x1) << OWR_INTR_STATUS_0_RXF_UNR_SHIFT)
+#define OWR_INTR_STATUS_0_RXF_UNR_RANGE                 9:9
+#define OWR_INTR_STATUS_0_RXF_UNR_WOFFSET                       0x0
+#define OWR_INTR_STATUS_0_RXF_UNR_DEFAULT                       _MK_MASK_CONST(0x0)
+#define OWR_INTR_STATUS_0_RXF_UNR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define OWR_INTR_STATUS_0_RXF_UNR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define OWR_INTR_STATUS_0_RXF_UNR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define OWR_INTR_STATUS_0_RXF_UNR_NOT_EMPTY                     _MK_ENUM_CONST(0)
+#define OWR_INTR_STATUS_0_RXF_UNR_EMPTY                 _MK_ENUM_CONST(1)
+
+// This bit is set when data is not stable for at least 1us,
+// Software writes a 1 to clear this bit. 
+// if deglitch detected data transfer should start from 1st. 
+#define OWR_INTR_STATUS_0_DGLITCH_SHIFT                 _MK_SHIFT_CONST(10)
+#define OWR_INTR_STATUS_0_DGLITCH_FIELD                 (_MK_MASK_CONST(0x1) << OWR_INTR_STATUS_0_DGLITCH_SHIFT)
+#define OWR_INTR_STATUS_0_DGLITCH_RANGE                 10:10
+#define OWR_INTR_STATUS_0_DGLITCH_WOFFSET                       0x0
+#define OWR_INTR_STATUS_0_DGLITCH_DEFAULT                       _MK_MASK_CONST(0x0)
+#define OWR_INTR_STATUS_0_DGLITCH_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define OWR_INTR_STATUS_0_DGLITCH_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define OWR_INTR_STATUS_0_DGLITCH_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define OWR_INTR_STATUS_0_DGLITCH_DGLITCH_NOT_DETECTED                  _MK_ENUM_CONST(0)
+#define OWR_INTR_STATUS_0_DGLITCH_DGLITCH_DETECTED                      _MK_ENUM_CONST(1)
+
+// TX FIFO data req
+#define OWR_INTR_STATUS_0_TXFIFO_DATA_REQ_SHIFT                 _MK_SHIFT_CONST(11)
+#define OWR_INTR_STATUS_0_TXFIFO_DATA_REQ_FIELD                 (_MK_MASK_CONST(0x1) << OWR_INTR_STATUS_0_TXFIFO_DATA_REQ_SHIFT)
+#define OWR_INTR_STATUS_0_TXFIFO_DATA_REQ_RANGE                 11:11
+#define OWR_INTR_STATUS_0_TXFIFO_DATA_REQ_WOFFSET                       0x0
+#define OWR_INTR_STATUS_0_TXFIFO_DATA_REQ_DEFAULT                       _MK_MASK_CONST(0x0)
+#define OWR_INTR_STATUS_0_TXFIFO_DATA_REQ_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define OWR_INTR_STATUS_0_TXFIFO_DATA_REQ_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define OWR_INTR_STATUS_0_TXFIFO_DATA_REQ_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define OWR_INTR_STATUS_0_TXFIFO_DATA_REQ_TX_NOT_RDY                    _MK_ENUM_CONST(0)
+#define OWR_INTR_STATUS_0_TXFIFO_DATA_REQ_TX_RDY                        _MK_ENUM_CONST(1)
+
+// RX FIFO data req  
+#define OWR_INTR_STATUS_0_RXFIFO_DATA_REQ_SHIFT                 _MK_SHIFT_CONST(12)
+#define OWR_INTR_STATUS_0_RXFIFO_DATA_REQ_FIELD                 (_MK_MASK_CONST(0x1) << OWR_INTR_STATUS_0_RXFIFO_DATA_REQ_SHIFT)
+#define OWR_INTR_STATUS_0_RXFIFO_DATA_REQ_RANGE                 12:12
+#define OWR_INTR_STATUS_0_RXFIFO_DATA_REQ_WOFFSET                       0x0
+#define OWR_INTR_STATUS_0_RXFIFO_DATA_REQ_DEFAULT                       _MK_MASK_CONST(0x0)
+#define OWR_INTR_STATUS_0_RXFIFO_DATA_REQ_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define OWR_INTR_STATUS_0_RXFIFO_DATA_REQ_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define OWR_INTR_STATUS_0_RXFIFO_DATA_REQ_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define OWR_INTR_STATUS_0_RXFIFO_DATA_REQ_RX_NOT_RDY                    _MK_ENUM_CONST(0)
+#define OWR_INTR_STATUS_0_RXFIFO_DATA_REQ_RX_RDY                        _MK_ENUM_CONST(1)
+
+// This bit is set when transfer of each bit done
+// this is set on in one bit transfer mode
+// software writes 1 to clear this bit
+#define OWR_INTR_STATUS_0_BIT_TRANSFER_DONE_SHIFT                       _MK_SHIFT_CONST(13)
+#define OWR_INTR_STATUS_0_BIT_TRANSFER_DONE_FIELD                       (_MK_MASK_CONST(0x1) << OWR_INTR_STATUS_0_BIT_TRANSFER_DONE_SHIFT)
+#define OWR_INTR_STATUS_0_BIT_TRANSFER_DONE_RANGE                       13:13
+#define OWR_INTR_STATUS_0_BIT_TRANSFER_DONE_WOFFSET                     0x0
+#define OWR_INTR_STATUS_0_BIT_TRANSFER_DONE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define OWR_INTR_STATUS_0_BIT_TRANSFER_DONE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define OWR_INTR_STATUS_0_BIT_TRANSFER_DONE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define OWR_INTR_STATUS_0_BIT_TRANSFER_DONE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define OWR_INTR_STATUS_0_BIT_TRANSFER_DONE_NOT_DONE                    _MK_ENUM_CONST(0)
+#define OWR_INTR_STATUS_0_BIT_TRANSFER_DONE_DONE                        _MK_ENUM_CONST(1)
+
+
+// Register OWR_INTR_SOURCE_0  
+#define OWR_INTR_SOURCE_0                       _MK_ADDR_CONST(0x2c)
+#define OWR_INTR_SOURCE_0_SECURE                        0x0
+#define OWR_INTR_SOURCE_0_WORD_COUNT                    0x1
+#define OWR_INTR_SOURCE_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define OWR_INTR_SOURCE_0_RESET_MASK                    _MK_MASK_CONST(0x3fff)
+#define OWR_INTR_SOURCE_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define OWR_INTR_SOURCE_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define OWR_INTR_SOURCE_0_READ_MASK                     _MK_MASK_CONST(0x3fff)
+#define OWR_INTR_SOURCE_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+#define OWR_INTR_SOURCE_0_PRESENCE_ERR_SHIFT                    _MK_SHIFT_CONST(0)
+#define OWR_INTR_SOURCE_0_PRESENCE_ERR_FIELD                    (_MK_MASK_CONST(0x1) << OWR_INTR_SOURCE_0_PRESENCE_ERR_SHIFT)
+#define OWR_INTR_SOURCE_0_PRESENCE_ERR_RANGE                    0:0
+#define OWR_INTR_SOURCE_0_PRESENCE_ERR_WOFFSET                  0x0
+#define OWR_INTR_SOURCE_0_PRESENCE_ERR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define OWR_INTR_SOURCE_0_PRESENCE_ERR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define OWR_INTR_SOURCE_0_PRESENCE_ERR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define OWR_INTR_SOURCE_0_PRESENCE_ERR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define OWR_INTR_SOURCE_0_PRESENCE_ERR_SLAVE_DETECTED                   _MK_ENUM_CONST(0)
+#define OWR_INTR_SOURCE_0_PRESENCE_ERR_NO_SLAVE_DETECTED                        _MK_ENUM_CONST(1)
+
+#define OWR_INTR_SOURCE_0_CRC_ERR_SHIFT                 _MK_SHIFT_CONST(1)
+#define OWR_INTR_SOURCE_0_CRC_ERR_FIELD                 (_MK_MASK_CONST(0x1) << OWR_INTR_SOURCE_0_CRC_ERR_SHIFT)
+#define OWR_INTR_SOURCE_0_CRC_ERR_RANGE                 1:1
+#define OWR_INTR_SOURCE_0_CRC_ERR_WOFFSET                       0x0
+#define OWR_INTR_SOURCE_0_CRC_ERR_DEFAULT                       _MK_MASK_CONST(0x0)
+#define OWR_INTR_SOURCE_0_CRC_ERR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define OWR_INTR_SOURCE_0_CRC_ERR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define OWR_INTR_SOURCE_0_CRC_ERR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define OWR_INTR_SOURCE_0_CRC_ERR_N0_ERROR                      _MK_ENUM_CONST(0)
+#define OWR_INTR_SOURCE_0_CRC_ERR_ERROR                 _MK_ENUM_CONST(1)
+
+#define OWR_INTR_SOURCE_0_MEM_WR_ERR_SHIFT                      _MK_SHIFT_CONST(2)
+#define OWR_INTR_SOURCE_0_MEM_WR_ERR_FIELD                      (_MK_MASK_CONST(0x1) << OWR_INTR_SOURCE_0_MEM_WR_ERR_SHIFT)
+#define OWR_INTR_SOURCE_0_MEM_WR_ERR_RANGE                      2:2
+#define OWR_INTR_SOURCE_0_MEM_WR_ERR_WOFFSET                    0x0
+#define OWR_INTR_SOURCE_0_MEM_WR_ERR_DEFAULT                    _MK_MASK_CONST(0x0)
+#define OWR_INTR_SOURCE_0_MEM_WR_ERR_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define OWR_INTR_SOURCE_0_MEM_WR_ERR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define OWR_INTR_SOURCE_0_MEM_WR_ERR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define OWR_INTR_SOURCE_0_MEM_WR_ERR_N0_ERROR                   _MK_ENUM_CONST(0)
+#define OWR_INTR_SOURCE_0_MEM_WR_ERR_ERROR                      _MK_ENUM_CONST(1)
+
+#define OWR_INTR_SOURCE_0_ERR_CMD_SHIFT                 _MK_SHIFT_CONST(3)
+#define OWR_INTR_SOURCE_0_ERR_CMD_FIELD                 (_MK_MASK_CONST(0x1) << OWR_INTR_SOURCE_0_ERR_CMD_SHIFT)
+#define OWR_INTR_SOURCE_0_ERR_CMD_RANGE                 3:3
+#define OWR_INTR_SOURCE_0_ERR_CMD_WOFFSET                       0x0
+#define OWR_INTR_SOURCE_0_ERR_CMD_DEFAULT                       _MK_MASK_CONST(0x0)
+#define OWR_INTR_SOURCE_0_ERR_CMD_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define OWR_INTR_SOURCE_0_ERR_CMD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define OWR_INTR_SOURCE_0_ERR_CMD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define OWR_INTR_SOURCE_0_ERR_CMD_CORRECT_CMD                   _MK_ENUM_CONST(0)
+#define OWR_INTR_SOURCE_0_ERR_CMD_ERROR_CMD                     _MK_ENUM_CONST(1)
+
+#define OWR_INTR_SOURCE_0_RESET_DONE_SHIFT                      _MK_SHIFT_CONST(4)
+#define OWR_INTR_SOURCE_0_RESET_DONE_FIELD                      (_MK_MASK_CONST(0x1) << OWR_INTR_SOURCE_0_RESET_DONE_SHIFT)
+#define OWR_INTR_SOURCE_0_RESET_DONE_RANGE                      4:4
+#define OWR_INTR_SOURCE_0_RESET_DONE_WOFFSET                    0x0
+#define OWR_INTR_SOURCE_0_RESET_DONE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define OWR_INTR_SOURCE_0_RESET_DONE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define OWR_INTR_SOURCE_0_RESET_DONE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define OWR_INTR_SOURCE_0_RESET_DONE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define OWR_INTR_SOURCE_0_RESET_DONE_NOT_DONE                   _MK_ENUM_CONST(0)
+#define OWR_INTR_SOURCE_0_RESET_DONE_DONE                       _MK_ENUM_CONST(1)
+
+#define OWR_INTR_SOURCE_0_PRESENCE_DONE_SHIFT                   _MK_SHIFT_CONST(5)
+#define OWR_INTR_SOURCE_0_PRESENCE_DONE_FIELD                   (_MK_MASK_CONST(0x1) << OWR_INTR_SOURCE_0_PRESENCE_DONE_SHIFT)
+#define OWR_INTR_SOURCE_0_PRESENCE_DONE_RANGE                   5:5
+#define OWR_INTR_SOURCE_0_PRESENCE_DONE_WOFFSET                 0x0
+#define OWR_INTR_SOURCE_0_PRESENCE_DONE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define OWR_INTR_SOURCE_0_PRESENCE_DONE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define OWR_INTR_SOURCE_0_PRESENCE_DONE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define OWR_INTR_SOURCE_0_PRESENCE_DONE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define OWR_INTR_SOURCE_0_PRESENCE_DONE_NOT_DONE                        _MK_ENUM_CONST(0)
+#define OWR_INTR_SOURCE_0_PRESENCE_DONE_DONE                    _MK_ENUM_CONST(1)
+
+#define OWR_INTR_SOURCE_0_ROM_CMD_DONE_SHIFT                    _MK_SHIFT_CONST(6)
+#define OWR_INTR_SOURCE_0_ROM_CMD_DONE_FIELD                    (_MK_MASK_CONST(0x1) << OWR_INTR_SOURCE_0_ROM_CMD_DONE_SHIFT)
+#define OWR_INTR_SOURCE_0_ROM_CMD_DONE_RANGE                    6:6
+#define OWR_INTR_SOURCE_0_ROM_CMD_DONE_WOFFSET                  0x0
+#define OWR_INTR_SOURCE_0_ROM_CMD_DONE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define OWR_INTR_SOURCE_0_ROM_CMD_DONE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define OWR_INTR_SOURCE_0_ROM_CMD_DONE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define OWR_INTR_SOURCE_0_ROM_CMD_DONE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define OWR_INTR_SOURCE_0_ROM_CMD_DONE_NOT_DONE                 _MK_ENUM_CONST(0)
+#define OWR_INTR_SOURCE_0_ROM_CMD_DONE_DONE                     _MK_ENUM_CONST(1)
+
+#define OWR_INTR_SOURCE_0_MEM_CMD_DONE_SHIFT                    _MK_SHIFT_CONST(7)
+#define OWR_INTR_SOURCE_0_MEM_CMD_DONE_FIELD                    (_MK_MASK_CONST(0x1) << OWR_INTR_SOURCE_0_MEM_CMD_DONE_SHIFT)
+#define OWR_INTR_SOURCE_0_MEM_CMD_DONE_RANGE                    7:7
+#define OWR_INTR_SOURCE_0_MEM_CMD_DONE_WOFFSET                  0x0
+#define OWR_INTR_SOURCE_0_MEM_CMD_DONE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define OWR_INTR_SOURCE_0_MEM_CMD_DONE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define OWR_INTR_SOURCE_0_MEM_CMD_DONE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define OWR_INTR_SOURCE_0_MEM_CMD_DONE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define OWR_INTR_SOURCE_0_MEM_CMD_DONE_NOT_DONE                 _MK_ENUM_CONST(0)
+#define OWR_INTR_SOURCE_0_MEM_CMD_DONE_DONE                     _MK_ENUM_CONST(1)
+
+#define OWR_INTR_SOURCE_0_TXF_OVF_SHIFT                 _MK_SHIFT_CONST(8)
+#define OWR_INTR_SOURCE_0_TXF_OVF_FIELD                 (_MK_MASK_CONST(0x1) << OWR_INTR_SOURCE_0_TXF_OVF_SHIFT)
+#define OWR_INTR_SOURCE_0_TXF_OVF_RANGE                 8:8
+#define OWR_INTR_SOURCE_0_TXF_OVF_WOFFSET                       0x0
+#define OWR_INTR_SOURCE_0_TXF_OVF_DEFAULT                       _MK_MASK_CONST(0x0)
+#define OWR_INTR_SOURCE_0_TXF_OVF_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define OWR_INTR_SOURCE_0_TXF_OVF_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define OWR_INTR_SOURCE_0_TXF_OVF_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define OWR_INTR_SOURCE_0_TXF_OVF_NOT_EMPTY                     _MK_ENUM_CONST(0)
+#define OWR_INTR_SOURCE_0_TXF_OVF_EMPTY                 _MK_ENUM_CONST(1)
+
+#define OWR_INTR_SOURCE_0_RXF_UNR_SHIFT                 _MK_SHIFT_CONST(9)
+#define OWR_INTR_SOURCE_0_RXF_UNR_FIELD                 (_MK_MASK_CONST(0x1) << OWR_INTR_SOURCE_0_RXF_UNR_SHIFT)
+#define OWR_INTR_SOURCE_0_RXF_UNR_RANGE                 9:9
+#define OWR_INTR_SOURCE_0_RXF_UNR_WOFFSET                       0x0
+#define OWR_INTR_SOURCE_0_RXF_UNR_DEFAULT                       _MK_MASK_CONST(0x0)
+#define OWR_INTR_SOURCE_0_RXF_UNR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define OWR_INTR_SOURCE_0_RXF_UNR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define OWR_INTR_SOURCE_0_RXF_UNR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define OWR_INTR_SOURCE_0_RXF_UNR_NOT_EMPTY                     _MK_ENUM_CONST(0)
+#define OWR_INTR_SOURCE_0_RXF_UNR_EMPTY                 _MK_ENUM_CONST(1)
+
+#define OWR_INTR_SOURCE_0_DGLITCH_SHIFT                 _MK_SHIFT_CONST(10)
+#define OWR_INTR_SOURCE_0_DGLITCH_FIELD                 (_MK_MASK_CONST(0x1) << OWR_INTR_SOURCE_0_DGLITCH_SHIFT)
+#define OWR_INTR_SOURCE_0_DGLITCH_RANGE                 10:10
+#define OWR_INTR_SOURCE_0_DGLITCH_WOFFSET                       0x0
+#define OWR_INTR_SOURCE_0_DGLITCH_DEFAULT                       _MK_MASK_CONST(0x0)
+#define OWR_INTR_SOURCE_0_DGLITCH_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define OWR_INTR_SOURCE_0_DGLITCH_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define OWR_INTR_SOURCE_0_DGLITCH_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define OWR_INTR_SOURCE_0_DGLITCH_DGLITCH_NOT_DETECTED                  _MK_ENUM_CONST(0)
+#define OWR_INTR_SOURCE_0_DGLITCH_DGLITCH_DETECTED                      _MK_ENUM_CONST(1)
+
+#define OWR_INTR_SOURCE_0_TXFIFO_DATA_REQ_SHIFT                 _MK_SHIFT_CONST(11)
+#define OWR_INTR_SOURCE_0_TXFIFO_DATA_REQ_FIELD                 (_MK_MASK_CONST(0x1) << OWR_INTR_SOURCE_0_TXFIFO_DATA_REQ_SHIFT)
+#define OWR_INTR_SOURCE_0_TXFIFO_DATA_REQ_RANGE                 11:11
+#define OWR_INTR_SOURCE_0_TXFIFO_DATA_REQ_WOFFSET                       0x0
+#define OWR_INTR_SOURCE_0_TXFIFO_DATA_REQ_DEFAULT                       _MK_MASK_CONST(0x0)
+#define OWR_INTR_SOURCE_0_TXFIFO_DATA_REQ_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define OWR_INTR_SOURCE_0_TXFIFO_DATA_REQ_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define OWR_INTR_SOURCE_0_TXFIFO_DATA_REQ_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define OWR_INTR_SOURCE_0_TXFIFO_DATA_REQ_TX_NOT_RDY                    _MK_ENUM_CONST(0)
+#define OWR_INTR_SOURCE_0_TXFIFO_DATA_REQ_TX_RDY                        _MK_ENUM_CONST(1)
+
+#define OWR_INTR_SOURCE_0_RXFIFO_DATA_REQ_SHIFT                 _MK_SHIFT_CONST(12)
+#define OWR_INTR_SOURCE_0_RXFIFO_DATA_REQ_FIELD                 (_MK_MASK_CONST(0x1) << OWR_INTR_SOURCE_0_RXFIFO_DATA_REQ_SHIFT)
+#define OWR_INTR_SOURCE_0_RXFIFO_DATA_REQ_RANGE                 12:12
+#define OWR_INTR_SOURCE_0_RXFIFO_DATA_REQ_WOFFSET                       0x0
+#define OWR_INTR_SOURCE_0_RXFIFO_DATA_REQ_DEFAULT                       _MK_MASK_CONST(0x0)
+#define OWR_INTR_SOURCE_0_RXFIFO_DATA_REQ_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define OWR_INTR_SOURCE_0_RXFIFO_DATA_REQ_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define OWR_INTR_SOURCE_0_RXFIFO_DATA_REQ_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define OWR_INTR_SOURCE_0_RXFIFO_DATA_REQ_RX_NOT_RDY                    _MK_ENUM_CONST(0)
+#define OWR_INTR_SOURCE_0_RXFIFO_DATA_REQ_RX_RDY                        _MK_ENUM_CONST(1)
+
+#define OWR_INTR_SOURCE_0_BIT_TRANSFER_DONE_SHIFT                       _MK_SHIFT_CONST(13)
+#define OWR_INTR_SOURCE_0_BIT_TRANSFER_DONE_FIELD                       (_MK_MASK_CONST(0x1) << OWR_INTR_SOURCE_0_BIT_TRANSFER_DONE_SHIFT)
+#define OWR_INTR_SOURCE_0_BIT_TRANSFER_DONE_RANGE                       13:13
+#define OWR_INTR_SOURCE_0_BIT_TRANSFER_DONE_WOFFSET                     0x0
+#define OWR_INTR_SOURCE_0_BIT_TRANSFER_DONE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define OWR_INTR_SOURCE_0_BIT_TRANSFER_DONE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define OWR_INTR_SOURCE_0_BIT_TRANSFER_DONE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define OWR_INTR_SOURCE_0_BIT_TRANSFER_DONE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define OWR_INTR_SOURCE_0_BIT_TRANSFER_DONE_NOT_DONE                    _MK_ENUM_CONST(0)
+#define OWR_INTR_SOURCE_0_BIT_TRANSFER_DONE_DONE                        _MK_ENUM_CONST(1)
+
+
+// Register OWR_INTR_SET_0  
+#define OWR_INTR_SET_0                  _MK_ADDR_CONST(0x30)
+#define OWR_INTR_SET_0_SECURE                   0x0
+#define OWR_INTR_SET_0_WORD_COUNT                       0x1
+#define OWR_INTR_SET_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define OWR_INTR_SET_0_RESET_MASK                       _MK_MASK_CONST(0x27ff)
+#define OWR_INTR_SET_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define OWR_INTR_SET_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define OWR_INTR_SET_0_READ_MASK                        _MK_MASK_CONST(0x27ff)
+#define OWR_INTR_SET_0_WRITE_MASK                       _MK_MASK_CONST(0x27ff)
+#define OWR_INTR_SET_0_PRESENCE_ERR_SHIFT                       _MK_SHIFT_CONST(0)
+#define OWR_INTR_SET_0_PRESENCE_ERR_FIELD                       (_MK_MASK_CONST(0x1) << OWR_INTR_SET_0_PRESENCE_ERR_SHIFT)
+#define OWR_INTR_SET_0_PRESENCE_ERR_RANGE                       0:0
+#define OWR_INTR_SET_0_PRESENCE_ERR_WOFFSET                     0x0
+#define OWR_INTR_SET_0_PRESENCE_ERR_DEFAULT                     _MK_MASK_CONST(0x0)
+#define OWR_INTR_SET_0_PRESENCE_ERR_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define OWR_INTR_SET_0_PRESENCE_ERR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define OWR_INTR_SET_0_PRESENCE_ERR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define OWR_INTR_SET_0_PRESENCE_ERR_SLAVE_DETECTED                      _MK_ENUM_CONST(0)
+#define OWR_INTR_SET_0_PRESENCE_ERR_NO_SLAVE_DETECTED                   _MK_ENUM_CONST(1)
+
+#define OWR_INTR_SET_0_CRC_ERR_SHIFT                    _MK_SHIFT_CONST(1)
+#define OWR_INTR_SET_0_CRC_ERR_FIELD                    (_MK_MASK_CONST(0x1) << OWR_INTR_SET_0_CRC_ERR_SHIFT)
+#define OWR_INTR_SET_0_CRC_ERR_RANGE                    1:1
+#define OWR_INTR_SET_0_CRC_ERR_WOFFSET                  0x0
+#define OWR_INTR_SET_0_CRC_ERR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define OWR_INTR_SET_0_CRC_ERR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define OWR_INTR_SET_0_CRC_ERR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define OWR_INTR_SET_0_CRC_ERR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define OWR_INTR_SET_0_CRC_ERR_N0_ERROR                 _MK_ENUM_CONST(0)
+#define OWR_INTR_SET_0_CRC_ERR_ERROR                    _MK_ENUM_CONST(1)
+
+#define OWR_INTR_SET_0_MEM_WR_ERR_SHIFT                 _MK_SHIFT_CONST(2)
+#define OWR_INTR_SET_0_MEM_WR_ERR_FIELD                 (_MK_MASK_CONST(0x1) << OWR_INTR_SET_0_MEM_WR_ERR_SHIFT)
+#define OWR_INTR_SET_0_MEM_WR_ERR_RANGE                 2:2
+#define OWR_INTR_SET_0_MEM_WR_ERR_WOFFSET                       0x0
+#define OWR_INTR_SET_0_MEM_WR_ERR_DEFAULT                       _MK_MASK_CONST(0x0)
+#define OWR_INTR_SET_0_MEM_WR_ERR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define OWR_INTR_SET_0_MEM_WR_ERR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define OWR_INTR_SET_0_MEM_WR_ERR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define OWR_INTR_SET_0_MEM_WR_ERR_N0_ERROR                      _MK_ENUM_CONST(0)
+#define OWR_INTR_SET_0_MEM_WR_ERR_ERROR                 _MK_ENUM_CONST(1)
+
+#define OWR_INTR_SET_0_ERR_CMD_SHIFT                    _MK_SHIFT_CONST(3)
+#define OWR_INTR_SET_0_ERR_CMD_FIELD                    (_MK_MASK_CONST(0x1) << OWR_INTR_SET_0_ERR_CMD_SHIFT)
+#define OWR_INTR_SET_0_ERR_CMD_RANGE                    3:3
+#define OWR_INTR_SET_0_ERR_CMD_WOFFSET                  0x0
+#define OWR_INTR_SET_0_ERR_CMD_DEFAULT                  _MK_MASK_CONST(0x0)
+#define OWR_INTR_SET_0_ERR_CMD_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define OWR_INTR_SET_0_ERR_CMD_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define OWR_INTR_SET_0_ERR_CMD_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define OWR_INTR_SET_0_ERR_CMD_CORRECT_CMD                      _MK_ENUM_CONST(0)
+#define OWR_INTR_SET_0_ERR_CMD_ERROR_CMD                        _MK_ENUM_CONST(1)
+
+#define OWR_INTR_SET_0_RESET_DONE_SHIFT                 _MK_SHIFT_CONST(4)
+#define OWR_INTR_SET_0_RESET_DONE_FIELD                 (_MK_MASK_CONST(0x1) << OWR_INTR_SET_0_RESET_DONE_SHIFT)
+#define OWR_INTR_SET_0_RESET_DONE_RANGE                 4:4
+#define OWR_INTR_SET_0_RESET_DONE_WOFFSET                       0x0
+#define OWR_INTR_SET_0_RESET_DONE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define OWR_INTR_SET_0_RESET_DONE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define OWR_INTR_SET_0_RESET_DONE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define OWR_INTR_SET_0_RESET_DONE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define OWR_INTR_SET_0_RESET_DONE_NOT_DONE                      _MK_ENUM_CONST(0)
+#define OWR_INTR_SET_0_RESET_DONE_DONE                  _MK_ENUM_CONST(1)
+
+#define OWR_INTR_SET_0_PRESENCE_DONE_SHIFT                      _MK_SHIFT_CONST(5)
+#define OWR_INTR_SET_0_PRESENCE_DONE_FIELD                      (_MK_MASK_CONST(0x1) << OWR_INTR_SET_0_PRESENCE_DONE_SHIFT)
+#define OWR_INTR_SET_0_PRESENCE_DONE_RANGE                      5:5
+#define OWR_INTR_SET_0_PRESENCE_DONE_WOFFSET                    0x0
+#define OWR_INTR_SET_0_PRESENCE_DONE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define OWR_INTR_SET_0_PRESENCE_DONE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define OWR_INTR_SET_0_PRESENCE_DONE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define OWR_INTR_SET_0_PRESENCE_DONE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define OWR_INTR_SET_0_PRESENCE_DONE_NOT_DONE                   _MK_ENUM_CONST(0)
+#define OWR_INTR_SET_0_PRESENCE_DONE_DONE                       _MK_ENUM_CONST(1)
+
+#define OWR_INTR_SET_0_ROM_CMD_DONE_SHIFT                       _MK_SHIFT_CONST(6)
+#define OWR_INTR_SET_0_ROM_CMD_DONE_FIELD                       (_MK_MASK_CONST(0x1) << OWR_INTR_SET_0_ROM_CMD_DONE_SHIFT)
+#define OWR_INTR_SET_0_ROM_CMD_DONE_RANGE                       6:6
+#define OWR_INTR_SET_0_ROM_CMD_DONE_WOFFSET                     0x0
+#define OWR_INTR_SET_0_ROM_CMD_DONE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define OWR_INTR_SET_0_ROM_CMD_DONE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define OWR_INTR_SET_0_ROM_CMD_DONE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define OWR_INTR_SET_0_ROM_CMD_DONE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define OWR_INTR_SET_0_ROM_CMD_DONE_NOT_DONE                    _MK_ENUM_CONST(0)
+#define OWR_INTR_SET_0_ROM_CMD_DONE_DONE                        _MK_ENUM_CONST(1)
+
+#define OWR_INTR_SET_0_MEM_CMD_DONE_SHIFT                       _MK_SHIFT_CONST(7)
+#define OWR_INTR_SET_0_MEM_CMD_DONE_FIELD                       (_MK_MASK_CONST(0x1) << OWR_INTR_SET_0_MEM_CMD_DONE_SHIFT)
+#define OWR_INTR_SET_0_MEM_CMD_DONE_RANGE                       7:7
+#define OWR_INTR_SET_0_MEM_CMD_DONE_WOFFSET                     0x0
+#define OWR_INTR_SET_0_MEM_CMD_DONE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define OWR_INTR_SET_0_MEM_CMD_DONE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define OWR_INTR_SET_0_MEM_CMD_DONE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define OWR_INTR_SET_0_MEM_CMD_DONE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define OWR_INTR_SET_0_MEM_CMD_DONE_NOT_DONE                    _MK_ENUM_CONST(0)
+#define OWR_INTR_SET_0_MEM_CMD_DONE_DONE                        _MK_ENUM_CONST(1)
+
+#define OWR_INTR_SET_0_TXF_OVF_SHIFT                    _MK_SHIFT_CONST(8)
+#define OWR_INTR_SET_0_TXF_OVF_FIELD                    (_MK_MASK_CONST(0x1) << OWR_INTR_SET_0_TXF_OVF_SHIFT)
+#define OWR_INTR_SET_0_TXF_OVF_RANGE                    8:8
+#define OWR_INTR_SET_0_TXF_OVF_WOFFSET                  0x0
+#define OWR_INTR_SET_0_TXF_OVF_DEFAULT                  _MK_MASK_CONST(0x0)
+#define OWR_INTR_SET_0_TXF_OVF_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define OWR_INTR_SET_0_TXF_OVF_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define OWR_INTR_SET_0_TXF_OVF_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define OWR_INTR_SET_0_TXF_OVF_NOT_EMPTY                        _MK_ENUM_CONST(0)
+#define OWR_INTR_SET_0_TXF_OVF_EMPTY                    _MK_ENUM_CONST(1)
+
+#define OWR_INTR_SET_0_RXF_UNR_SHIFT                    _MK_SHIFT_CONST(9)
+#define OWR_INTR_SET_0_RXF_UNR_FIELD                    (_MK_MASK_CONST(0x1) << OWR_INTR_SET_0_RXF_UNR_SHIFT)
+#define OWR_INTR_SET_0_RXF_UNR_RANGE                    9:9
+#define OWR_INTR_SET_0_RXF_UNR_WOFFSET                  0x0
+#define OWR_INTR_SET_0_RXF_UNR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define OWR_INTR_SET_0_RXF_UNR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define OWR_INTR_SET_0_RXF_UNR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define OWR_INTR_SET_0_RXF_UNR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define OWR_INTR_SET_0_RXF_UNR_NOT_EMPTY                        _MK_ENUM_CONST(0)
+#define OWR_INTR_SET_0_RXF_UNR_EMPTY                    _MK_ENUM_CONST(1)
+
+#define OWR_INTR_SET_0_DGLITCH_SHIFT                    _MK_SHIFT_CONST(10)
+#define OWR_INTR_SET_0_DGLITCH_FIELD                    (_MK_MASK_CONST(0x1) << OWR_INTR_SET_0_DGLITCH_SHIFT)
+#define OWR_INTR_SET_0_DGLITCH_RANGE                    10:10
+#define OWR_INTR_SET_0_DGLITCH_WOFFSET                  0x0
+#define OWR_INTR_SET_0_DGLITCH_DEFAULT                  _MK_MASK_CONST(0x0)
+#define OWR_INTR_SET_0_DGLITCH_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define OWR_INTR_SET_0_DGLITCH_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define OWR_INTR_SET_0_DGLITCH_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define OWR_INTR_SET_0_DGLITCH_DGLITCH_NOT_DETECTED                     _MK_ENUM_CONST(0)
+#define OWR_INTR_SET_0_DGLITCH_DGLITCH_DETECTED                 _MK_ENUM_CONST(1)
+
+#define OWR_INTR_SET_0_BIT_TRANSFER_DONE_SHIFT                  _MK_SHIFT_CONST(13)
+#define OWR_INTR_SET_0_BIT_TRANSFER_DONE_FIELD                  (_MK_MASK_CONST(0x1) << OWR_INTR_SET_0_BIT_TRANSFER_DONE_SHIFT)
+#define OWR_INTR_SET_0_BIT_TRANSFER_DONE_RANGE                  13:13
+#define OWR_INTR_SET_0_BIT_TRANSFER_DONE_WOFFSET                        0x0
+#define OWR_INTR_SET_0_BIT_TRANSFER_DONE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define OWR_INTR_SET_0_BIT_TRANSFER_DONE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define OWR_INTR_SET_0_BIT_TRANSFER_DONE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define OWR_INTR_SET_0_BIT_TRANSFER_DONE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define OWR_INTR_SET_0_BIT_TRANSFER_DONE_NOT_DONE                       _MK_ENUM_CONST(0)
+#define OWR_INTR_SET_0_BIT_TRANSFER_DONE_DONE                   _MK_ENUM_CONST(1)
+
+
+// Register OWR_STATUS_0  
+#define OWR_STATUS_0                    _MK_ADDR_CONST(0x34)
+#define OWR_STATUS_0_SECURE                     0x0
+#define OWR_STATUS_0_WORD_COUNT                         0x1
+#define OWR_STATUS_0_RESET_VAL                  _MK_MASK_CONST(0x15)
+#define OWR_STATUS_0_RESET_MASK                         _MK_MASK_CONST(0xffffff)
+#define OWR_STATUS_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define OWR_STATUS_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define OWR_STATUS_0_READ_MASK                  _MK_MASK_CONST(0xffffff)
+#define OWR_STATUS_0_WRITE_MASK                         _MK_MASK_CONST(0x60)
+// Ready bit. This bit is set at the end of every transfer and 
+// its cleared by hardware when next transfer starts  
+#define OWR_STATUS_0_RDY_SHIFT                  _MK_SHIFT_CONST(0)
+#define OWR_STATUS_0_RDY_FIELD                  (_MK_MASK_CONST(0x1) << OWR_STATUS_0_RDY_SHIFT)
+#define OWR_STATUS_0_RDY_RANGE                  0:0
+#define OWR_STATUS_0_RDY_WOFFSET                        0x0
+#define OWR_STATUS_0_RDY_DEFAULT                        _MK_MASK_CONST(0x1)
+#define OWR_STATUS_0_RDY_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define OWR_STATUS_0_RDY_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define OWR_STATUS_0_RDY_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define OWR_STATUS_0_RDY_NOT_READY                      _MK_ENUM_CONST(0)
+#define OWR_STATUS_0_RDY_READY                  _MK_ENUM_CONST(1)
+
+// TX FIFO full status: RO.Hardware sets this bit to 1 if TX FIFO is full.
+// Otherwise, this bit is set to 0. 
+#define OWR_STATUS_0_TXF_FULL_SHIFT                     _MK_SHIFT_CONST(1)
+#define OWR_STATUS_0_TXF_FULL_FIELD                     (_MK_MASK_CONST(0x1) << OWR_STATUS_0_TXF_FULL_SHIFT)
+#define OWR_STATUS_0_TXF_FULL_RANGE                     1:1
+#define OWR_STATUS_0_TXF_FULL_WOFFSET                   0x0
+#define OWR_STATUS_0_TXF_FULL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define OWR_STATUS_0_TXF_FULL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define OWR_STATUS_0_TXF_FULL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define OWR_STATUS_0_TXF_FULL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define OWR_STATUS_0_TXF_FULL_NOT_FULL                  _MK_ENUM_CONST(0)
+#define OWR_STATUS_0_TXF_FULL_FULL                      _MK_ENUM_CONST(1)
+
+// TX FIFO empty status: RO.Hardware sets this bit to 1 if TX FIFO is empty
+// Otherwise, this bit is set to 0.   
+#define OWR_STATUS_0_TXF_EMPTY_SHIFT                    _MK_SHIFT_CONST(2)
+#define OWR_STATUS_0_TXF_EMPTY_FIELD                    (_MK_MASK_CONST(0x1) << OWR_STATUS_0_TXF_EMPTY_SHIFT)
+#define OWR_STATUS_0_TXF_EMPTY_RANGE                    2:2
+#define OWR_STATUS_0_TXF_EMPTY_WOFFSET                  0x0
+#define OWR_STATUS_0_TXF_EMPTY_DEFAULT                  _MK_MASK_CONST(0x1)
+#define OWR_STATUS_0_TXF_EMPTY_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define OWR_STATUS_0_TXF_EMPTY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define OWR_STATUS_0_TXF_EMPTY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define OWR_STATUS_0_TXF_EMPTY_NOT_EMPTY                        _MK_ENUM_CONST(0)
+#define OWR_STATUS_0_TXF_EMPTY_EMPTY                    _MK_ENUM_CONST(1)
+
+// RX FIFO full status: RO.Hardware sets this bit to 1 if RX FIFO is full.
+// Otherwise, this bit is set to 0.  
+#define OWR_STATUS_0_RXF_FULL_SHIFT                     _MK_SHIFT_CONST(3)
+#define OWR_STATUS_0_RXF_FULL_FIELD                     (_MK_MASK_CONST(0x1) << OWR_STATUS_0_RXF_FULL_SHIFT)
+#define OWR_STATUS_0_RXF_FULL_RANGE                     3:3
+#define OWR_STATUS_0_RXF_FULL_WOFFSET                   0x0
+#define OWR_STATUS_0_RXF_FULL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define OWR_STATUS_0_RXF_FULL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define OWR_STATUS_0_RXF_FULL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define OWR_STATUS_0_RXF_FULL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define OWR_STATUS_0_RXF_FULL_NOT_FULL                  _MK_ENUM_CONST(0)
+#define OWR_STATUS_0_RXF_FULL_FULL                      _MK_ENUM_CONST(1)
+
+// RX FIFO empty status: RO.Hardware sets this bit to 1 if RX FIFO is empty
+// Otherwise, this bit is set to 0.  
+#define OWR_STATUS_0_RXF_EMPTY_SHIFT                    _MK_SHIFT_CONST(4)
+#define OWR_STATUS_0_RXF_EMPTY_FIELD                    (_MK_MASK_CONST(0x1) << OWR_STATUS_0_RXF_EMPTY_SHIFT)
+#define OWR_STATUS_0_RXF_EMPTY_RANGE                    4:4
+#define OWR_STATUS_0_RXF_EMPTY_WOFFSET                  0x0
+#define OWR_STATUS_0_RXF_EMPTY_DEFAULT                  _MK_MASK_CONST(0x1)
+#define OWR_STATUS_0_RXF_EMPTY_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define OWR_STATUS_0_RXF_EMPTY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define OWR_STATUS_0_RXF_EMPTY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define OWR_STATUS_0_RXF_EMPTY_NOT_EMPTY                        _MK_ENUM_CONST(0)
+#define OWR_STATUS_0_RXF_EMPTY_EMPTY                    _MK_ENUM_CONST(1)
+
+// flush the tx fifo,cleared after fifo is empty 
+#define OWR_STATUS_0_TX_FLUSH_SHIFT                     _MK_SHIFT_CONST(5)
+#define OWR_STATUS_0_TX_FLUSH_FIELD                     (_MK_MASK_CONST(0x1) << OWR_STATUS_0_TX_FLUSH_SHIFT)
+#define OWR_STATUS_0_TX_FLUSH_RANGE                     5:5
+#define OWR_STATUS_0_TX_FLUSH_WOFFSET                   0x0
+#define OWR_STATUS_0_TX_FLUSH_DEFAULT                   _MK_MASK_CONST(0x0)
+#define OWR_STATUS_0_TX_FLUSH_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define OWR_STATUS_0_TX_FLUSH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define OWR_STATUS_0_TX_FLUSH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define OWR_STATUS_0_TX_FLUSH_DISABLE                   _MK_ENUM_CONST(0)
+#define OWR_STATUS_0_TX_FLUSH_ENABLE                    _MK_ENUM_CONST(1)
+
+// flush the rx fifo,cleared after fifo is empty 
+#define OWR_STATUS_0_RX_FLUSH_SHIFT                     _MK_SHIFT_CONST(6)
+#define OWR_STATUS_0_RX_FLUSH_FIELD                     (_MK_MASK_CONST(0x1) << OWR_STATUS_0_RX_FLUSH_SHIFT)
+#define OWR_STATUS_0_RX_FLUSH_RANGE                     6:6
+#define OWR_STATUS_0_RX_FLUSH_WOFFSET                   0x0
+#define OWR_STATUS_0_RX_FLUSH_DEFAULT                   _MK_MASK_CONST(0x0)
+#define OWR_STATUS_0_RX_FLUSH_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define OWR_STATUS_0_RX_FLUSH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define OWR_STATUS_0_RX_FLUSH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define OWR_STATUS_0_RX_FLUSH_DISABLE                   _MK_ENUM_CONST(0)
+#define OWR_STATUS_0_RX_FLUSH_ENABLE                    _MK_ENUM_CONST(1)
+
+// The number of slots to be read from  the rx fifo
+#define OWR_STATUS_0_RX_FIFO_FULL_CNT_SHIFT                     _MK_SHIFT_CONST(7)
+#define OWR_STATUS_0_RX_FIFO_FULL_CNT_FIELD                     (_MK_MASK_CONST(0x3f) << OWR_STATUS_0_RX_FIFO_FULL_CNT_SHIFT)
+#define OWR_STATUS_0_RX_FIFO_FULL_CNT_RANGE                     12:7
+#define OWR_STATUS_0_RX_FIFO_FULL_CNT_WOFFSET                   0x0
+#define OWR_STATUS_0_RX_FIFO_FULL_CNT_DEFAULT                   _MK_MASK_CONST(0x0)
+#define OWR_STATUS_0_RX_FIFO_FULL_CNT_DEFAULT_MASK                      _MK_MASK_CONST(0x3f)
+#define OWR_STATUS_0_RX_FIFO_FULL_CNT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define OWR_STATUS_0_RX_FIFO_FULL_CNT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// The number of slots that can be written to the tx fifo
+#define OWR_STATUS_0_TX_FIFO_EMPTY_CNT_SHIFT                    _MK_SHIFT_CONST(13)
+#define OWR_STATUS_0_TX_FIFO_EMPTY_CNT_FIELD                    (_MK_MASK_CONST(0x3f) << OWR_STATUS_0_TX_FIFO_EMPTY_CNT_SHIFT)
+#define OWR_STATUS_0_TX_FIFO_EMPTY_CNT_RANGE                    18:13
+#define OWR_STATUS_0_TX_FIFO_EMPTY_CNT_WOFFSET                  0x0
+#define OWR_STATUS_0_TX_FIFO_EMPTY_CNT_DEFAULT                  _MK_MASK_CONST(0x0)
+#define OWR_STATUS_0_TX_FIFO_EMPTY_CNT_DEFAULT_MASK                     _MK_MASK_CONST(0x3f)
+#define OWR_STATUS_0_TX_FIFO_EMPTY_CNT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define OWR_STATUS_0_TX_FIFO_EMPTY_CNT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// this is set when rpp reset bit is set in ctl reg(go), 
+// auto cleared on completion of reset initialization sequence.
+#define OWR_STATUS_0_RPP_SHIFT                  _MK_SHIFT_CONST(19)
+#define OWR_STATUS_0_RPP_FIELD                  (_MK_MASK_CONST(0x1) << OWR_STATUS_0_RPP_SHIFT)
+#define OWR_STATUS_0_RPP_RANGE                  19:19
+#define OWR_STATUS_0_RPP_WOFFSET                        0x0
+#define OWR_STATUS_0_RPP_DEFAULT                        _MK_MASK_CONST(0x0)
+#define OWR_STATUS_0_RPP_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define OWR_STATUS_0_RPP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define OWR_STATUS_0_RPP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define OWR_STATUS_0_RPP_IDLE                   _MK_ENUM_CONST(0)
+#define OWR_STATUS_0_RPP_RESET_PRESENCE_PULSE                   _MK_ENUM_CONST(1)
+
+// WRITE 0 : This bit is self clearing,and is cleared 
+// when write zero time slot completes 
+// on write sequence 0  is transfered 
+#define OWR_STATUS_0_WR0_BUSY_SHIFT                     _MK_SHIFT_CONST(20)
+#define OWR_STATUS_0_WR0_BUSY_FIELD                     (_MK_MASK_CONST(0x1) << OWR_STATUS_0_WR0_BUSY_SHIFT)
+#define OWR_STATUS_0_WR0_BUSY_RANGE                     20:20
+#define OWR_STATUS_0_WR0_BUSY_WOFFSET                   0x0
+#define OWR_STATUS_0_WR0_BUSY_DEFAULT                   _MK_MASK_CONST(0x0)
+#define OWR_STATUS_0_WR0_BUSY_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define OWR_STATUS_0_WR0_BUSY_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define OWR_STATUS_0_WR0_BUSY_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define OWR_STATUS_0_WR0_BUSY_IDLE                      _MK_ENUM_CONST(0)
+#define OWR_STATUS_0_WR0_BUSY_BUSY                      _MK_ENUM_CONST(1)
+
+// WRITE1 : This is a self clearing bit and is cleared 
+// when write one time slot completes
+// on write sequence 1  is transfered 
+#define OWR_STATUS_0_WR1_BUSY_SHIFT                     _MK_SHIFT_CONST(21)
+#define OWR_STATUS_0_WR1_BUSY_FIELD                     (_MK_MASK_CONST(0x1) << OWR_STATUS_0_WR1_BUSY_SHIFT)
+#define OWR_STATUS_0_WR1_BUSY_RANGE                     21:21
+#define OWR_STATUS_0_WR1_BUSY_WOFFSET                   0x0
+#define OWR_STATUS_0_WR1_BUSY_DEFAULT                   _MK_MASK_CONST(0x0)
+#define OWR_STATUS_0_WR1_BUSY_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define OWR_STATUS_0_WR1_BUSY_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define OWR_STATUS_0_WR1_BUSY_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define OWR_STATUS_0_WR1_BUSY_IDLE                      _MK_ENUM_CONST(0)
+#define OWR_STATUS_0_WR1_BUSY_BUSY                      _MK_ENUM_CONST(1)
+
+// READ : This is a self clearing bit and is cleared 
+// when read time slot completes
+// on read sequence the sampled read bit is stored in READ_BIT
+#define OWR_STATUS_0_RD_BUSY_SHIFT                      _MK_SHIFT_CONST(22)
+#define OWR_STATUS_0_RD_BUSY_FIELD                      (_MK_MASK_CONST(0x1) << OWR_STATUS_0_RD_BUSY_SHIFT)
+#define OWR_STATUS_0_RD_BUSY_RANGE                      22:22
+#define OWR_STATUS_0_RD_BUSY_WOFFSET                    0x0
+#define OWR_STATUS_0_RD_BUSY_DEFAULT                    _MK_MASK_CONST(0x0)
+#define OWR_STATUS_0_RD_BUSY_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define OWR_STATUS_0_RD_BUSY_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define OWR_STATUS_0_RD_BUSY_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define OWR_STATUS_0_RD_BUSY_IDLE                       _MK_ENUM_CONST(0)
+#define OWR_STATUS_0_RD_BUSY_BUSY                       _MK_ENUM_CONST(1)
+
+// the bit is valid only RD_BUSY is cleared 
+#define OWR_STATUS_0_READ_SAMPLED_BIT_SHIFT                     _MK_SHIFT_CONST(23)
+#define OWR_STATUS_0_READ_SAMPLED_BIT_FIELD                     (_MK_MASK_CONST(0x1) << OWR_STATUS_0_READ_SAMPLED_BIT_SHIFT)
+#define OWR_STATUS_0_READ_SAMPLED_BIT_RANGE                     23:23
+#define OWR_STATUS_0_READ_SAMPLED_BIT_WOFFSET                   0x0
+#define OWR_STATUS_0_READ_SAMPLED_BIT_DEFAULT                   _MK_MASK_CONST(0x0)
+#define OWR_STATUS_0_READ_SAMPLED_BIT_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define OWR_STATUS_0_READ_SAMPLED_BIT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define OWR_STATUS_0_READ_SAMPLED_BIT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define OWR_STATUS_0_READ_SAMPLED_BIT_READ_ZERO                 _MK_ENUM_CONST(0)
+#define OWR_STATUS_0_READ_SAMPLED_BIT_READ_ONE                  _MK_ENUM_CONST(1)
+
+
+// Register OWR_CRC_0  
+#define OWR_CRC_0                       _MK_ADDR_CONST(0x38)
+#define OWR_CRC_0_SECURE                        0x0
+#define OWR_CRC_0_WORD_COUNT                    0x1
+#define OWR_CRC_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define OWR_CRC_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
+#define OWR_CRC_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define OWR_CRC_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define OWR_CRC_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define OWR_CRC_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+// CRC Received on Read Data
+#define OWR_CRC_0_CRC_RECEV_SHIFT                       _MK_SHIFT_CONST(0)
+#define OWR_CRC_0_CRC_RECEV_FIELD                       (_MK_MASK_CONST(0xffff) << OWR_CRC_0_CRC_RECEV_SHIFT)
+#define OWR_CRC_0_CRC_RECEV_RANGE                       15:0
+#define OWR_CRC_0_CRC_RECEV_WOFFSET                     0x0
+#define OWR_CRC_0_CRC_RECEV_DEFAULT                     _MK_MASK_CONST(0x0)
+#define OWR_CRC_0_CRC_RECEV_DEFAULT_MASK                        _MK_MASK_CONST(0xffff)
+#define OWR_CRC_0_CRC_RECEV_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define OWR_CRC_0_CRC_RECEV_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// CRC calculated by owr current wr/rd operation
+#define OWR_CRC_0_CRC_CALC_SHIFT                        _MK_SHIFT_CONST(16)
+#define OWR_CRC_0_CRC_CALC_FIELD                        (_MK_MASK_CONST(0xffff) << OWR_CRC_0_CRC_CALC_SHIFT)
+#define OWR_CRC_0_CRC_CALC_RANGE                        31:16
+#define OWR_CRC_0_CRC_CALC_WOFFSET                      0x0
+#define OWR_CRC_0_CRC_CALC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define OWR_CRC_0_CRC_CALC_DEFAULT_MASK                 _MK_MASK_CONST(0xffff)
+#define OWR_CRC_0_CRC_CALC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define OWR_CRC_0_CRC_CALC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register OWR_BYTE_CNT_0  
+#define OWR_BYTE_CNT_0                  _MK_ADDR_CONST(0x3c)
+#define OWR_BYTE_CNT_0_SECURE                   0x0
+#define OWR_BYTE_CNT_0_WORD_COUNT                       0x1
+#define OWR_BYTE_CNT_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define OWR_BYTE_CNT_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
+#define OWR_BYTE_CNT_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define OWR_BYTE_CNT_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define OWR_BYTE_CNT_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define OWR_BYTE_CNT_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
+// Number of bytes Received on Read Data includes crc byte cnt
+#define OWR_BYTE_CNT_0_RECEIVED_SHIFT                   _MK_SHIFT_CONST(0)
+#define OWR_BYTE_CNT_0_RECEIVED_FIELD                   (_MK_MASK_CONST(0xffff) << OWR_BYTE_CNT_0_RECEIVED_SHIFT)
+#define OWR_BYTE_CNT_0_RECEIVED_RANGE                   15:0
+#define OWR_BYTE_CNT_0_RECEIVED_WOFFSET                 0x0
+#define OWR_BYTE_CNT_0_RECEIVED_DEFAULT                 _MK_MASK_CONST(0x0)
+#define OWR_BYTE_CNT_0_RECEIVED_DEFAULT_MASK                    _MK_MASK_CONST(0xffff)
+#define OWR_BYTE_CNT_0_RECEIVED_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define OWR_BYTE_CNT_0_RECEIVED_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Number of bytes Transmitted on wr cmds or addr sent
+#define OWR_BYTE_CNT_0_TRANSMITTED_SHIFT                        _MK_SHIFT_CONST(16)
+#define OWR_BYTE_CNT_0_TRANSMITTED_FIELD                        (_MK_MASK_CONST(0xffff) << OWR_BYTE_CNT_0_TRANSMITTED_SHIFT)
+#define OWR_BYTE_CNT_0_TRANSMITTED_RANGE                        31:16
+#define OWR_BYTE_CNT_0_TRANSMITTED_WOFFSET                      0x0
+#define OWR_BYTE_CNT_0_TRANSMITTED_DEFAULT                      _MK_MASK_CONST(0x0)
+#define OWR_BYTE_CNT_0_TRANSMITTED_DEFAULT_MASK                 _MK_MASK_CONST(0xffff)
+#define OWR_BYTE_CNT_0_TRANSMITTED_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define OWR_BYTE_CNT_0_TRANSMITTED_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register OWR_TX_FIFO_0  
+#define OWR_TX_FIFO_0                   _MK_ADDR_CONST(0x40)
+#define OWR_TX_FIFO_0_SECURE                    0x0
+#define OWR_TX_FIFO_0_WORD_COUNT                        0x1
+#define OWR_TX_FIFO_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define OWR_TX_FIFO_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
+#define OWR_TX_FIFO_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define OWR_TX_FIFO_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define OWR_TX_FIFO_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define OWR_TX_FIFO_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
+// TX FIFO
+#define OWR_TX_FIFO_0_WR_DATA_SHIFT                     _MK_SHIFT_CONST(0)
+#define OWR_TX_FIFO_0_WR_DATA_FIELD                     (_MK_MASK_CONST(0xffffffff) << OWR_TX_FIFO_0_WR_DATA_SHIFT)
+#define OWR_TX_FIFO_0_WR_DATA_RANGE                     31:0
+#define OWR_TX_FIFO_0_WR_DATA_WOFFSET                   0x0
+#define OWR_TX_FIFO_0_WR_DATA_DEFAULT                   _MK_MASK_CONST(0x0)
+#define OWR_TX_FIFO_0_WR_DATA_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define OWR_TX_FIFO_0_WR_DATA_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define OWR_TX_FIFO_0_WR_DATA_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register OWR_RX_FIFO_0  
+#define OWR_RX_FIFO_0                   _MK_ADDR_CONST(0x44)
+#define OWR_RX_FIFO_0_SECURE                    0x0
+#define OWR_RX_FIFO_0_WORD_COUNT                        0x1
+#define OWR_RX_FIFO_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define OWR_RX_FIFO_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
+#define OWR_RX_FIFO_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define OWR_RX_FIFO_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define OWR_RX_FIFO_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define OWR_RX_FIFO_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+// RX FIFO
+#define OWR_RX_FIFO_0_RD_DATA_SHIFT                     _MK_SHIFT_CONST(0)
+#define OWR_RX_FIFO_0_RD_DATA_FIELD                     (_MK_MASK_CONST(0xffffffff) << OWR_RX_FIFO_0_RD_DATA_SHIFT)
+#define OWR_RX_FIFO_0_RD_DATA_RANGE                     31:0
+#define OWR_RX_FIFO_0_RD_DATA_WOFFSET                   0x0
+#define OWR_RX_FIFO_0_RD_DATA_DEFAULT                   _MK_MASK_CONST(0x0)
+#define OWR_RX_FIFO_0_RD_DATA_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define OWR_RX_FIFO_0_RD_DATA_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define OWR_RX_FIFO_0_RD_DATA_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register OWR_STATE_BITS_0  
+#define OWR_STATE_BITS_0                        _MK_ADDR_CONST(0x48)
+#define OWR_STATE_BITS_0_SECURE                         0x0
+#define OWR_STATE_BITS_0_WORD_COUNT                     0x1
+#define OWR_STATE_BITS_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define OWR_STATE_BITS_0_RESET_MASK                     _MK_MASK_CONST(0xffff)
+#define OWR_STATE_BITS_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define OWR_STATE_BITS_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define OWR_STATE_BITS_0_READ_MASK                      _MK_MASK_CONST(0xffff)
+#define OWR_STATE_BITS_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
+// controls reset initialization sequence , rom cmd and mem cmd
+#define OWR_STATE_BITS_0_OWR_STATE_SHIFT                        _MK_SHIFT_CONST(0)
+#define OWR_STATE_BITS_0_OWR_STATE_FIELD                        (_MK_MASK_CONST(0xf) << OWR_STATE_BITS_0_OWR_STATE_SHIFT)
+#define OWR_STATE_BITS_0_OWR_STATE_RANGE                        3:0
+#define OWR_STATE_BITS_0_OWR_STATE_WOFFSET                      0x0
+#define OWR_STATE_BITS_0_OWR_STATE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define OWR_STATE_BITS_0_OWR_STATE_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define OWR_STATE_BITS_0_OWR_STATE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define OWR_STATE_BITS_0_OWR_STATE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// executes a particular cmd in rom or mem cmd
+#define OWR_STATE_BITS_0_CMD_EXECUTE_STATE_SHIFT                        _MK_SHIFT_CONST(4)
+#define OWR_STATE_BITS_0_CMD_EXECUTE_STATE_FIELD                        (_MK_MASK_CONST(0xf) << OWR_STATE_BITS_0_CMD_EXECUTE_STATE_SHIFT)
+#define OWR_STATE_BITS_0_CMD_EXECUTE_STATE_RANGE                        7:4
+#define OWR_STATE_BITS_0_CMD_EXECUTE_STATE_WOFFSET                      0x0
+#define OWR_STATE_BITS_0_CMD_EXECUTE_STATE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define OWR_STATE_BITS_0_CMD_EXECUTE_STATE_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define OWR_STATE_BITS_0_CMD_EXECUTE_STATE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define OWR_STATE_BITS_0_CMD_EXECUTE_STATE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// executes write time slots
+#define OWR_STATE_BITS_0_WRITE_STATE_SHIFT                      _MK_SHIFT_CONST(8)
+#define OWR_STATE_BITS_0_WRITE_STATE_FIELD                      (_MK_MASK_CONST(0xf) << OWR_STATE_BITS_0_WRITE_STATE_SHIFT)
+#define OWR_STATE_BITS_0_WRITE_STATE_RANGE                      11:8
+#define OWR_STATE_BITS_0_WRITE_STATE_WOFFSET                    0x0
+#define OWR_STATE_BITS_0_WRITE_STATE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define OWR_STATE_BITS_0_WRITE_STATE_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
+#define OWR_STATE_BITS_0_WRITE_STATE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define OWR_STATE_BITS_0_WRITE_STATE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// executes read time slots 
+#define OWR_STATE_BITS_0_READ_STATE_SHIFT                       _MK_SHIFT_CONST(12)
+#define OWR_STATE_BITS_0_READ_STATE_FIELD                       (_MK_MASK_CONST(0xf) << OWR_STATE_BITS_0_READ_STATE_SHIFT)
+#define OWR_STATE_BITS_0_READ_STATE_RANGE                       15:12
+#define OWR_STATE_BITS_0_READ_STATE_WOFFSET                     0x0
+#define OWR_STATE_BITS_0_READ_STATE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define OWR_STATE_BITS_0_READ_STATE_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define OWR_STATE_BITS_0_READ_STATE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define OWR_STATE_BITS_0_READ_STATE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+//
+// REGISTER LIST
+//
+#define LIST_AROWR_REGS(_op_) \
+_op_(OWR_CONTROL_0) \
+_op_(OWR_COMMAND_0) \
+_op_(OWR_EPROM_0) \
+_op_(OWR_WR_RD_TCTL_0) \
+_op_(OWR_RST_PRESENCE_TCTL_0) \
+_op_(OWR_PPM_CORRECTION_TCTL_0) \
+_op_(OWR_PROG_PULSE_TCTL_0) \
+_op_(OWR_READ_ROM0_0) \
+_op_(OWR_READ_ROM1_0) \
+_op_(OWR_INTR_MASK_0) \
+_op_(OWR_INTR_STATUS_0) \
+_op_(OWR_INTR_SOURCE_0) \
+_op_(OWR_INTR_SET_0) \
+_op_(OWR_STATUS_0) \
+_op_(OWR_CRC_0) \
+_op_(OWR_BYTE_CNT_0) \
+_op_(OWR_TX_FIFO_0) \
+_op_(OWR_RX_FIFO_0) \
+_op_(OWR_STATE_BITS_0)
+
+
+//
+// ADDRESS SPACES
+//
+
+#define BASE_ADDRESS_OWR        0x00000000
+
+//
+// AROWR REGISTER BANKS
+//
+
+#define OWR0_FIRST_REG 0x0000 // OWR_CONTROL_0
+#define OWR0_LAST_REG 0x0048 // OWR_STATE_BITS_0
+
+#ifndef _MK_SHIFT_CONST
+  #define _MK_SHIFT_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_MASK_CONST
+  #define _MK_MASK_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_ENUM_CONST
+  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
+#endif
+#ifndef _MK_ADDR_CONST
+  #define _MK_ADDR_CONST(_constant_) _constant_
+#endif
+
+#endif // ifndef ___AROWR_H_INC_
diff --git a/arch/arm/mach-tegra/include/ap20/arslink.h b/arch/arm/mach-tegra/include/ap20/arslink.h
new file mode 100644
index 000000000000..cfd1ef7eed24
--- /dev/null
+++ b/arch/arm/mach-tegra/include/ap20/arslink.h
@@ -0,0 +1,1125 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+//
+// DO NOT EDIT - generated by simspec!
+//
+
+#ifndef ___ARSLINK_H_INC_
+#define ___ARSLINK_H_INC_
+
+// Register SLINK_COMMAND_0  
+#define SLINK_COMMAND_0                 _MK_ADDR_CONST(0x0)
+#define SLINK_COMMAND_0_SECURE                  0x0
+#define SLINK_COMMAND_0_WORD_COUNT                      0x1
+#define SLINK_COMMAND_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_RESET_MASK                      _MK_MASK_CONST(0xf3f33fff)
+#define SLINK_COMMAND_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_READ_MASK                       _MK_MASK_CONST(0xf3f33fff)
+#define SLINK_COMMAND_0_WRITE_MASK                      _MK_MASK_CONST(0xf3f33fff)
+// RD/WD access to Data Register would start the next  transfer. (This allows continuous Receive via RD of Buffer and Automated  Transmit per WD of Buffer Register)
+#define SLINK_COMMAND_0_ENB_SHIFT                       _MK_SHIFT_CONST(31)
+#define SLINK_COMMAND_0_ENB_FIELD                       (_MK_MASK_CONST(0x1) << SLINK_COMMAND_0_ENB_SHIFT)
+#define SLINK_COMMAND_0_ENB_RANGE                       31:31
+#define SLINK_COMMAND_0_ENB_WOFFSET                     0x0
+#define SLINK_COMMAND_0_ENB_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_ENB_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define SLINK_COMMAND_0_ENB_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_ENB_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_ENB_DISABLE                     _MK_ENUM_CONST(0)
+#define SLINK_COMMAND_0_ENB_ENABLE                      _MK_ENUM_CONST(1)
+
+// Program 1 after all the other bits in the COMMAND2 and COMMAND are programmed to start the trasnfer
+// HW clears this bit automatically after the trasnfer is done
+// Clearing of the bit by SW will stop the Shifter  and latch the partial data into buffer
+#define SLINK_COMMAND_0_GO_SHIFT                        _MK_SHIFT_CONST(30)
+#define SLINK_COMMAND_0_GO_FIELD                        (_MK_MASK_CONST(0x1) << SLINK_COMMAND_0_GO_SHIFT)
+#define SLINK_COMMAND_0_GO_RANGE                        30:30
+#define SLINK_COMMAND_0_GO_WOFFSET                      0x0
+#define SLINK_COMMAND_0_GO_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_GO_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define SLINK_COMMAND_0_GO_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_GO_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_GO_STOP                 _MK_ENUM_CONST(0)
+#define SLINK_COMMAND_0_GO_GO                   _MK_ENUM_CONST(1)
+
+//  1 = Hold APB Cycle from writing another data into COMMAND register until RDY 0  = NOP. Use of this bit is deprecated.
+#define SLINK_COMMAND_0_WAIT_SHIFT                      _MK_SHIFT_CONST(29)
+#define SLINK_COMMAND_0_WAIT_FIELD                      (_MK_MASK_CONST(0x1) << SLINK_COMMAND_0_WAIT_SHIFT)
+#define SLINK_COMMAND_0_WAIT_RANGE                      29:29
+#define SLINK_COMMAND_0_WAIT_WOFFSET                    0x0
+#define SLINK_COMMAND_0_WAIT_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_WAIT_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define SLINK_COMMAND_0_WAIT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_WAIT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_WAIT_NOP                        _MK_ENUM_CONST(0)
+#define SLINK_COMMAND_0_WAIT_WAIT                       _MK_ENUM_CONST(1)
+
+// 1 = Master Mode (internal Clock) 0 = Slave Mode  (external Clock)
+#define SLINK_COMMAND_0_M_S_SHIFT                       _MK_SHIFT_CONST(28)
+#define SLINK_COMMAND_0_M_S_FIELD                       (_MK_MASK_CONST(0x1) << SLINK_COMMAND_0_M_S_SHIFT)
+#define SLINK_COMMAND_0_M_S_RANGE                       28:28
+#define SLINK_COMMAND_0_M_S_WOFFSET                     0x0
+#define SLINK_COMMAND_0_M_S_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_M_S_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define SLINK_COMMAND_0_M_S_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_M_S_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_M_S_SLAVE                       _MK_ENUM_CONST(0)
+#define SLINK_COMMAND_0_M_S_MASTER                      _MK_ENUM_CONST(1)
+
+// 11 = Pull High 10 = Pull Low 01 = Driven High 00 =  Driven Low (def)
+#define SLINK_COMMAND_0_IDLE_SCLK_SHIFT                 _MK_SHIFT_CONST(24)
+#define SLINK_COMMAND_0_IDLE_SCLK_FIELD                 (_MK_MASK_CONST(0x3) << SLINK_COMMAND_0_IDLE_SCLK_SHIFT)
+#define SLINK_COMMAND_0_IDLE_SCLK_RANGE                 25:24
+#define SLINK_COMMAND_0_IDLE_SCLK_WOFFSET                       0x0
+#define SLINK_COMMAND_0_IDLE_SCLK_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_IDLE_SCLK_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define SLINK_COMMAND_0_IDLE_SCLK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_IDLE_SCLK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_IDLE_SCLK_DRIVE_LOW                     _MK_ENUM_CONST(0)
+#define SLINK_COMMAND_0_IDLE_SCLK_DRIVE_HIGH                    _MK_ENUM_CONST(1)
+#define SLINK_COMMAND_0_IDLE_SCLK_PULL_LOW                      _MK_ENUM_CONST(2)
+#define SLINK_COMMAND_0_IDLE_SCLK_PULL_HIGH                     _MK_ENUM_CONST(3)
+
+//  1 = CS3 active high  0  = CS3 active low
+#define SLINK_COMMAND_0_CS_POLARITY3_SHIFT                      _MK_SHIFT_CONST(23)
+#define SLINK_COMMAND_0_CS_POLARITY3_FIELD                      (_MK_MASK_CONST(0x1) << SLINK_COMMAND_0_CS_POLARITY3_SHIFT)
+#define SLINK_COMMAND_0_CS_POLARITY3_RANGE                      23:23
+#define SLINK_COMMAND_0_CS_POLARITY3_WOFFSET                    0x0
+#define SLINK_COMMAND_0_CS_POLARITY3_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_CS_POLARITY3_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define SLINK_COMMAND_0_CS_POLARITY3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_CS_POLARITY3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_CS_POLARITY3_LOW                        _MK_ENUM_CONST(0)
+#define SLINK_COMMAND_0_CS_POLARITY3_HIGH                       _MK_ENUM_CONST(1)
+
+//  1 = CS2 active high  0  = CS2 active low
+#define SLINK_COMMAND_0_CS_POLARITY2_SHIFT                      _MK_SHIFT_CONST(22)
+#define SLINK_COMMAND_0_CS_POLARITY2_FIELD                      (_MK_MASK_CONST(0x1) << SLINK_COMMAND_0_CS_POLARITY2_SHIFT)
+#define SLINK_COMMAND_0_CS_POLARITY2_RANGE                      22:22
+#define SLINK_COMMAND_0_CS_POLARITY2_WOFFSET                    0x0
+#define SLINK_COMMAND_0_CS_POLARITY2_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_CS_POLARITY2_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define SLINK_COMMAND_0_CS_POLARITY2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_CS_POLARITY2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_CS_POLARITY2_LOW                        _MK_ENUM_CONST(0)
+#define SLINK_COMMAND_0_CS_POLARITY2_HIGH                       _MK_ENUM_CONST(1)
+
+//  1 = Rising Edge 0 =  Falling Edge (def)
+#define SLINK_COMMAND_0_CK_SDA_SHIFT                    _MK_SHIFT_CONST(21)
+#define SLINK_COMMAND_0_CK_SDA_FIELD                    (_MK_MASK_CONST(0x1) << SLINK_COMMAND_0_CK_SDA_SHIFT)
+#define SLINK_COMMAND_0_CK_SDA_RANGE                    21:21
+#define SLINK_COMMAND_0_CK_SDA_WOFFSET                  0x0
+#define SLINK_COMMAND_0_CK_SDA_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_CK_SDA_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define SLINK_COMMAND_0_CK_SDA_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_CK_SDA_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_CK_SDA_FIRST_CLK_EDGE                   _MK_ENUM_CONST(0)
+#define SLINK_COMMAND_0_CK_SDA_SECOND_CLK_EDGE                  _MK_ENUM_CONST(1)
+
+//  1 = CS1 active high  0  = CS1 active low
+#define SLINK_COMMAND_0_CS_POLARITY1_SHIFT                      _MK_SHIFT_CONST(20)
+#define SLINK_COMMAND_0_CS_POLARITY1_FIELD                      (_MK_MASK_CONST(0x1) << SLINK_COMMAND_0_CS_POLARITY1_SHIFT)
+#define SLINK_COMMAND_0_CS_POLARITY1_RANGE                      20:20
+#define SLINK_COMMAND_0_CS_POLARITY1_WOFFSET                    0x0
+#define SLINK_COMMAND_0_CS_POLARITY1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_CS_POLARITY1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define SLINK_COMMAND_0_CS_POLARITY1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_CS_POLARITY1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_CS_POLARITY1_LOW                        _MK_ENUM_CONST(0)
+#define SLINK_COMMAND_0_CS_POLARITY1_HIGH                       _MK_ENUM_CONST(1)
+
+// 11 = Pull High 10 = Pull Low 01 = Driven High 00  = Driven Low
+#define SLINK_COMMAND_0_IDLE_SDA_SHIFT                  _MK_SHIFT_CONST(16)
+#define SLINK_COMMAND_0_IDLE_SDA_FIELD                  (_MK_MASK_CONST(0x3) << SLINK_COMMAND_0_IDLE_SDA_SHIFT)
+#define SLINK_COMMAND_0_IDLE_SDA_RANGE                  17:16
+#define SLINK_COMMAND_0_IDLE_SDA_WOFFSET                        0x0
+#define SLINK_COMMAND_0_IDLE_SDA_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_IDLE_SDA_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define SLINK_COMMAND_0_IDLE_SDA_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_IDLE_SDA_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_IDLE_SDA_DRIVE_LOW                      _MK_ENUM_CONST(0)
+#define SLINK_COMMAND_0_IDLE_SDA_DRIVE_HIGH                     _MK_ENUM_CONST(1)
+#define SLINK_COMMAND_0_IDLE_SDA_PULL_LOW                       _MK_ENUM_CONST(2)
+#define SLINK_COMMAND_0_IDLE_SDA_PULL_HIGH                      _MK_ENUM_CONST(3)
+
+//  1 = CS0 active high  0  = CS0 active low
+#define SLINK_COMMAND_0_CS_POLARITY0_SHIFT                      _MK_SHIFT_CONST(13)
+#define SLINK_COMMAND_0_CS_POLARITY0_FIELD                      (_MK_MASK_CONST(0x1) << SLINK_COMMAND_0_CS_POLARITY0_SHIFT)
+#define SLINK_COMMAND_0_CS_POLARITY0_RANGE                      13:13
+#define SLINK_COMMAND_0_CS_POLARITY0_WOFFSET                    0x0
+#define SLINK_COMMAND_0_CS_POLARITY0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_CS_POLARITY0_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define SLINK_COMMAND_0_CS_POLARITY0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_CS_POLARITY0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_CS_POLARITY0_LOW                        _MK_ENUM_CONST(0)
+#define SLINK_COMMAND_0_CS_POLARITY0_HIGH                       _MK_ENUM_CONST(1)
+
+//  1 = CS is high  0  = CS is low  
+#define SLINK_COMMAND_0_CS_VALUE_SHIFT                  _MK_SHIFT_CONST(12)
+#define SLINK_COMMAND_0_CS_VALUE_FIELD                  (_MK_MASK_CONST(0x1) << SLINK_COMMAND_0_CS_VALUE_SHIFT)
+#define SLINK_COMMAND_0_CS_VALUE_RANGE                  12:12
+#define SLINK_COMMAND_0_CS_VALUE_WOFFSET                        0x0
+#define SLINK_COMMAND_0_CS_VALUE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_CS_VALUE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define SLINK_COMMAND_0_CS_VALUE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_CS_VALUE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_CS_VALUE_LOW                    _MK_ENUM_CONST(0)
+#define SLINK_COMMAND_0_CS_VALUE_HIGH                   _MK_ENUM_CONST(1)
+
+//  1 = CS controlled by SW   0  = CS controlled by hardware
+#define SLINK_COMMAND_0_CS_SW_SHIFT                     _MK_SHIFT_CONST(11)
+#define SLINK_COMMAND_0_CS_SW_FIELD                     (_MK_MASK_CONST(0x1) << SLINK_COMMAND_0_CS_SW_SHIFT)
+#define SLINK_COMMAND_0_CS_SW_RANGE                     11:11
+#define SLINK_COMMAND_0_CS_SW_WOFFSET                   0x0
+#define SLINK_COMMAND_0_CS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_CS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define SLINK_COMMAND_0_CS_SW_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_CS_SW_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_CS_SW_HARD                      _MK_ENUM_CONST(0)
+#define SLINK_COMMAND_0_CS_SW_SOFT                      _MK_ENUM_CONST(1)
+
+//  1 = both lines transmit/receive   0  = one line transmit and other receive 
+#define SLINK_COMMAND_0_BOTH_EN_SHIFT                   _MK_SHIFT_CONST(10)
+#define SLINK_COMMAND_0_BOTH_EN_FIELD                   (_MK_MASK_CONST(0x1) << SLINK_COMMAND_0_BOTH_EN_SHIFT)
+#define SLINK_COMMAND_0_BOTH_EN_RANGE                   10:10
+#define SLINK_COMMAND_0_BOTH_EN_WOFFSET                 0x0
+#define SLINK_COMMAND_0_BOTH_EN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_BOTH_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define SLINK_COMMAND_0_BOTH_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_BOTH_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_BOTH_EN_DISABLE                 _MK_ENUM_CONST(0)
+#define SLINK_COMMAND_0_BOTH_EN_ENABLE                  _MK_ENUM_CONST(1)
+
+// 31 = Thirty Two words (Max)
+#define SLINK_COMMAND_0_WORD_SIZE_SHIFT                 _MK_SHIFT_CONST(5)
+#define SLINK_COMMAND_0_WORD_SIZE_FIELD                 (_MK_MASK_CONST(0x1f) << SLINK_COMMAND_0_WORD_SIZE_SHIFT)
+#define SLINK_COMMAND_0_WORD_SIZE_RANGE                 9:5
+#define SLINK_COMMAND_0_WORD_SIZE_WOFFSET                       0x0
+#define SLINK_COMMAND_0_WORD_SIZE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_WORD_SIZE_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define SLINK_COMMAND_0_WORD_SIZE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_WORD_SIZE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// 31 = Thirty Two bit Transfers (Max)
+#define SLINK_COMMAND_0_BIT_LENGTH_SHIFT                        _MK_SHIFT_CONST(0)
+#define SLINK_COMMAND_0_BIT_LENGTH_FIELD                        (_MK_MASK_CONST(0x1f) << SLINK_COMMAND_0_BIT_LENGTH_SHIFT)
+#define SLINK_COMMAND_0_BIT_LENGTH_RANGE                        4:0
+#define SLINK_COMMAND_0_BIT_LENGTH_WOFFSET                      0x0
+#define SLINK_COMMAND_0_BIT_LENGTH_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_BIT_LENGTH_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define SLINK_COMMAND_0_BIT_LENGTH_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_BIT_LENGTH_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register SLINK_COMMAND2_0  
+#define SLINK_COMMAND2_0                        _MK_ADDR_CONST(0x4)
+#define SLINK_COMMAND2_0_SECURE                         0x0
+#define SLINK_COMMAND2_0_WORD_COUNT                     0x1
+#define SLINK_COMMAND2_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_RESET_MASK                     _MK_MASK_CONST(0xfcfe1fd3)
+#define SLINK_COMMAND2_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_READ_MASK                      _MK_MASK_CONST(0xfcfe1fd3)
+#define SLINK_COMMAND2_0_WRITE_MASK                     _MK_MASK_CONST(0xfcfe1fd3)
+// Receive enable 
+#define SLINK_COMMAND2_0_RXEN_SHIFT                     _MK_SHIFT_CONST(31)
+#define SLINK_COMMAND2_0_RXEN_FIELD                     (_MK_MASK_CONST(0x1) << SLINK_COMMAND2_0_RXEN_SHIFT)
+#define SLINK_COMMAND2_0_RXEN_RANGE                     31:31
+#define SLINK_COMMAND2_0_RXEN_WOFFSET                   0x0
+#define SLINK_COMMAND2_0_RXEN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_RXEN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define SLINK_COMMAND2_0_RXEN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_RXEN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_RXEN_DISABLE                   _MK_ENUM_CONST(0)
+#define SLINK_COMMAND2_0_RXEN_ENABLE                    _MK_ENUM_CONST(1)
+
+// Transmit enable 
+#define SLINK_COMMAND2_0_TXEN_SHIFT                     _MK_SHIFT_CONST(30)
+#define SLINK_COMMAND2_0_TXEN_FIELD                     (_MK_MASK_CONST(0x1) << SLINK_COMMAND2_0_TXEN_SHIFT)
+#define SLINK_COMMAND2_0_TXEN_RANGE                     30:30
+#define SLINK_COMMAND2_0_TXEN_WOFFSET                   0x0
+#define SLINK_COMMAND2_0_TXEN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_TXEN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define SLINK_COMMAND2_0_TXEN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_TXEN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_TXEN_DISABLE                   _MK_ENUM_CONST(0)
+#define SLINK_COMMAND2_0_TXEN_ENABLE                    _MK_ENUM_CONST(1)
+
+//  1 = bi directional mode 0 = Normal mode
+#define SLINK_COMMAND2_0_SPC0_SHIFT                     _MK_SHIFT_CONST(29)
+#define SLINK_COMMAND2_0_SPC0_FIELD                     (_MK_MASK_CONST(0x1) << SLINK_COMMAND2_0_SPC0_SHIFT)
+#define SLINK_COMMAND2_0_SPC0_RANGE                     29:29
+#define SLINK_COMMAND2_0_SPC0_WOFFSET                   0x0
+#define SLINK_COMMAND2_0_SPC0_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_SPC0_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define SLINK_COMMAND2_0_SPC0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_SPC0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_SPC0_NORMAL                    _MK_ENUM_CONST(0)
+#define SLINK_COMMAND2_0_SPC0_BIDIR                     _MK_ENUM_CONST(1)
+
+// number of cycles between two packs in the DMA. Use of this field is deprecated. Use INT_SIZE 8 = number of cycles between 2 packs (Max) 
+#define SLINK_COMMAND2_0_WAIT_PACK_INT_SHIFT                    _MK_SHIFT_CONST(26)
+#define SLINK_COMMAND2_0_WAIT_PACK_INT_FIELD                    (_MK_MASK_CONST(0x7) << SLINK_COMMAND2_0_WAIT_PACK_INT_SHIFT)
+#define SLINK_COMMAND2_0_WAIT_PACK_INT_RANGE                    28:26
+#define SLINK_COMMAND2_0_WAIT_PACK_INT_WOFFSET                  0x0
+#define SLINK_COMMAND2_0_WAIT_PACK_INT_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_WAIT_PACK_INT_DEFAULT_MASK                     _MK_MASK_CONST(0x7)
+#define SLINK_COMMAND2_0_WAIT_PACK_INT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_WAIT_PACK_INT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Number of transfers the CS should stay low for word sizes more than 32.
+// This will enable to do the trasnfer of word sizes > 32 without using apb-dma
+// 0x00  For word_sizes 1 to 32
+// 0x01  For word_sizes 33 to 64
+// 0x10  For word sizes 65 to 96
+// 0x11  For word sizes 97 to 128
+#define SLINK_COMMAND2_0_FIFO_REFILLS_SHIFT                     _MK_SHIFT_CONST(22)
+#define SLINK_COMMAND2_0_FIFO_REFILLS_FIELD                     (_MK_MASK_CONST(0x3) << SLINK_COMMAND2_0_FIFO_REFILLS_SHIFT)
+#define SLINK_COMMAND2_0_FIFO_REFILLS_RANGE                     23:22
+#define SLINK_COMMAND2_0_FIFO_REFILLS_WOFFSET                   0x0
+#define SLINK_COMMAND2_0_FIFO_REFILLS_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_FIFO_REFILLS_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define SLINK_COMMAND2_0_FIFO_REFILLS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_FIFO_REFILLS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_FIFO_REFILLS_REFILL0                   _MK_ENUM_CONST(0)
+#define SLINK_COMMAND2_0_FIFO_REFILLS_REFILL1                   _MK_ENUM_CONST(1)
+#define SLINK_COMMAND2_0_FIFO_REFILLS_REFILL2                   _MK_ENUM_CONST(2)
+#define SLINK_COMMAND2_0_FIFO_REFILLS_REFILL3                   _MK_ENUM_CONST(3)
+
+// number of cycles CS should stay inactive between packets 4 = number of cycles in setup for chip select (Max)   
+#define SLINK_COMMAND2_0_SS_SETUP_SHIFT                 _MK_SHIFT_CONST(20)
+#define SLINK_COMMAND2_0_SS_SETUP_FIELD                 (_MK_MASK_CONST(0x3) << SLINK_COMMAND2_0_SS_SETUP_SHIFT)
+#define SLINK_COMMAND2_0_SS_SETUP_RANGE                 21:20
+#define SLINK_COMMAND2_0_SS_SETUP_WOFFSET                       0x0
+#define SLINK_COMMAND2_0_SS_SETUP_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_SS_SETUP_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define SLINK_COMMAND2_0_SS_SETUP_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_SS_SETUP_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// 11 = chip select3 10 = chip select2 01 = chip select1 00 = chip select0(def)
+#define SLINK_COMMAND2_0_SS_EN_SHIFT                    _MK_SHIFT_CONST(18)
+#define SLINK_COMMAND2_0_SS_EN_FIELD                    (_MK_MASK_CONST(0x3) << SLINK_COMMAND2_0_SS_EN_SHIFT)
+#define SLINK_COMMAND2_0_SS_EN_RANGE                    19:18
+#define SLINK_COMMAND2_0_SS_EN_WOFFSET                  0x0
+#define SLINK_COMMAND2_0_SS_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_SS_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define SLINK_COMMAND2_0_SS_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_SS_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_SS_EN_CS0                      _MK_ENUM_CONST(0)
+#define SLINK_COMMAND2_0_SS_EN_CS1                      _MK_ENUM_CONST(1)
+#define SLINK_COMMAND2_0_SS_EN_CS2                      _MK_ENUM_CONST(2)
+#define SLINK_COMMAND2_0_SS_EN_CS3                      _MK_ENUM_CONST(3)
+
+// 1 = CS active between two packets 0 = CS inactive between two packets
+#define SLINK_COMMAND2_0_CS_ACTIVE_BETWEEN_SHIFT                        _MK_SHIFT_CONST(17)
+#define SLINK_COMMAND2_0_CS_ACTIVE_BETWEEN_FIELD                        (_MK_MASK_CONST(0x1) << SLINK_COMMAND2_0_CS_ACTIVE_BETWEEN_SHIFT)
+#define SLINK_COMMAND2_0_CS_ACTIVE_BETWEEN_RANGE                        17:17
+#define SLINK_COMMAND2_0_CS_ACTIVE_BETWEEN_WOFFSET                      0x0
+#define SLINK_COMMAND2_0_CS_ACTIVE_BETWEEN_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_CS_ACTIVE_BETWEEN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define SLINK_COMMAND2_0_CS_ACTIVE_BETWEEN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_CS_ACTIVE_BETWEEN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_CS_ACTIVE_BETWEEN_LOW                  _MK_ENUM_CONST(0)
+#define SLINK_COMMAND2_0_CS_ACTIVE_BETWEEN_HIGH                 _MK_ENUM_CONST(1)
+
+// number of IDLE cycles between two packets
+// 31 = thirty two cycles between 2 packets
+#define SLINK_COMMAND2_0_INT_SIZE_SHIFT                 _MK_SHIFT_CONST(8)
+#define SLINK_COMMAND2_0_INT_SIZE_FIELD                 (_MK_MASK_CONST(0x1f) << SLINK_COMMAND2_0_INT_SIZE_SHIFT)
+#define SLINK_COMMAND2_0_INT_SIZE_RANGE                 12:8
+#define SLINK_COMMAND2_0_INT_SIZE_WOFFSET                       0x0
+#define SLINK_COMMAND2_0_INT_SIZE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_INT_SIZE_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define SLINK_COMMAND2_0_INT_SIZE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_INT_SIZE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//  1 = Enable Modef   0 = Disable Modef (def)
+#define SLINK_COMMAND2_0_MODFEN_SHIFT                   _MK_SHIFT_CONST(7)
+#define SLINK_COMMAND2_0_MODFEN_FIELD                   (_MK_MASK_CONST(0x1) << SLINK_COMMAND2_0_MODFEN_SHIFT)
+#define SLINK_COMMAND2_0_MODFEN_RANGE                   7:7
+#define SLINK_COMMAND2_0_MODFEN_WOFFSET                 0x0
+#define SLINK_COMMAND2_0_MODFEN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_MODFEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define SLINK_COMMAND2_0_MODFEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_MODFEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_MODFEN_DISABLE                 _MK_ENUM_CONST(0)
+#define SLINK_COMMAND2_0_MODFEN_ENABLE                  _MK_ENUM_CONST(1)
+
+// When set to 1 SLINK uses only one data line (mosi/miso) for Tx and Rx depending on Master/Slave mode.
+// This has effect only when SPC0 is set to 1
+// 1 = Enable Output buffer 0 = Disable Output buffer (def)
+#define SLINK_COMMAND2_0_BIDIROE_SHIFT                  _MK_SHIFT_CONST(6)
+#define SLINK_COMMAND2_0_BIDIROE_FIELD                  (_MK_MASK_CONST(0x1) << SLINK_COMMAND2_0_BIDIROE_SHIFT)
+#define SLINK_COMMAND2_0_BIDIROE_RANGE                  6:6
+#define SLINK_COMMAND2_0_BIDIROE_WOFFSET                        0x0
+#define SLINK_COMMAND2_0_BIDIROE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_BIDIROE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define SLINK_COMMAND2_0_BIDIROE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_BIDIROE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_BIDIROE_DISABLE                        _MK_ENUM_CONST(0)
+#define SLINK_COMMAND2_0_BIDIROE_ENABLE                 _MK_ENUM_CONST(1)
+
+// 1 = Enable SPIE interrupt 0 = Disable SPIE interrupt
+#define SLINK_COMMAND2_0_SPIE_SHIFT                     _MK_SHIFT_CONST(4)
+#define SLINK_COMMAND2_0_SPIE_FIELD                     (_MK_MASK_CONST(0x1) << SLINK_COMMAND2_0_SPIE_SHIFT)
+#define SLINK_COMMAND2_0_SPIE_RANGE                     4:4
+#define SLINK_COMMAND2_0_SPIE_WOFFSET                   0x0
+#define SLINK_COMMAND2_0_SPIE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_SPIE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define SLINK_COMMAND2_0_SPIE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_SPIE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_SPIE_DISABLE                   _MK_ENUM_CONST(0)
+#define SLINK_COMMAND2_0_SPIE_ENABLE                    _MK_ENUM_CONST(1)
+
+// 1 = Enable 0 = Disable (def)
+#define SLINK_COMMAND2_0_SSOE_SHIFT                     _MK_SHIFT_CONST(1)
+#define SLINK_COMMAND2_0_SSOE_FIELD                     (_MK_MASK_CONST(0x1) << SLINK_COMMAND2_0_SSOE_SHIFT)
+#define SLINK_COMMAND2_0_SSOE_RANGE                     1:1
+#define SLINK_COMMAND2_0_SSOE_WOFFSET                   0x0
+#define SLINK_COMMAND2_0_SSOE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_SSOE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define SLINK_COMMAND2_0_SSOE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_SSOE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_SSOE_DISABLE                   _MK_ENUM_CONST(0)
+#define SLINK_COMMAND2_0_SSOE_ENABLE                    _MK_ENUM_CONST(1)
+
+//  1 = Transmit LSB first 0 = Transmit LSB last
+#define SLINK_COMMAND2_0_LSBFE_SHIFT                    _MK_SHIFT_CONST(0)
+#define SLINK_COMMAND2_0_LSBFE_FIELD                    (_MK_MASK_CONST(0x1) << SLINK_COMMAND2_0_LSBFE_SHIFT)
+#define SLINK_COMMAND2_0_LSBFE_RANGE                    0:0
+#define SLINK_COMMAND2_0_LSBFE_WOFFSET                  0x0
+#define SLINK_COMMAND2_0_LSBFE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_LSBFE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define SLINK_COMMAND2_0_LSBFE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_LSBFE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_LSBFE_LAST                     _MK_ENUM_CONST(0)
+#define SLINK_COMMAND2_0_LSBFE_FIRST                    _MK_ENUM_CONST(1)
+
+
+// Register SLINK_STATUS_0  
+#define SLINK_STATUS_0                  _MK_ADDR_CONST(0x8)
+#define SLINK_STATUS_0_SECURE                   0x0
+#define SLINK_STATUS_0_WORD_COUNT                       0x1
+#define SLINK_STATUS_0_RESET_VAL                        _MK_MASK_CONST(0xa00000)
+#define SLINK_STATUS_0_RESET_MASK                       _MK_MASK_CONST(0xfffdffff)
+#define SLINK_STATUS_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_READ_MASK                        _MK_MASK_CONST(0xfffdffff)
+#define SLINK_STATUS_0_WRITE_MASK                       _MK_MASK_CONST(0xfffdffff)
+//  1 = Controller is Busy 0 =  Controller is Free
+#define SLINK_STATUS_0_BSY_SHIFT                        _MK_SHIFT_CONST(31)
+#define SLINK_STATUS_0_BSY_FIELD                        (_MK_MASK_CONST(0x1) << SLINK_STATUS_0_BSY_SHIFT)
+#define SLINK_STATUS_0_BSY_RANGE                        31:31
+#define SLINK_STATUS_0_BSY_WOFFSET                      0x0
+#define SLINK_STATUS_0_BSY_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_BSY_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define SLINK_STATUS_0_BSY_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_BSY_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_BSY_IDLE                 _MK_ENUM_CONST(0)
+#define SLINK_STATUS_0_BSY_BUSY                 _MK_ENUM_CONST(1)
+
+// 1= contoller is Ready for transfer 0 = controller is Busy. Write 1 to clear the flag
+#define SLINK_STATUS_0_RDY_SHIFT                        _MK_SHIFT_CONST(30)
+#define SLINK_STATUS_0_RDY_FIELD                        (_MK_MASK_CONST(0x1) << SLINK_STATUS_0_RDY_SHIFT)
+#define SLINK_STATUS_0_RDY_RANGE                        30:30
+#define SLINK_STATUS_0_RDY_WOFFSET                      0x0
+#define SLINK_STATUS_0_RDY_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_RDY_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define SLINK_STATUS_0_RDY_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_RDY_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_RDY_NOT_READY                    _MK_ENUM_CONST(0)
+#define SLINK_STATUS_0_RDY_READY                        _MK_ENUM_CONST(1)
+
+// Will be set to 1 by HW when Errors such as Underflow/overflow occurs.Write 1 to clear the flag
+#define SLINK_STATUS_0_ERR_SHIFT                        _MK_SHIFT_CONST(29)
+#define SLINK_STATUS_0_ERR_FIELD                        (_MK_MASK_CONST(0x1) << SLINK_STATUS_0_ERR_SHIFT)
+#define SLINK_STATUS_0_ERR_RANGE                        29:29
+#define SLINK_STATUS_0_ERR_WOFFSET                      0x0
+#define SLINK_STATUS_0_ERR_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_ERR_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define SLINK_STATUS_0_ERR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_ERR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_ERR_OK                   _MK_ENUM_CONST(0)
+#define SLINK_STATUS_0_ERR_ERROR                        _MK_ENUM_CONST(1)
+
+// SCLK input signal State
+#define SLINK_STATUS_0_SCLK_SHIFT                       _MK_SHIFT_CONST(28)
+#define SLINK_STATUS_0_SCLK_FIELD                       (_MK_MASK_CONST(0x1) << SLINK_STATUS_0_SCLK_SHIFT)
+#define SLINK_STATUS_0_SCLK_RANGE                       28:28
+#define SLINK_STATUS_0_SCLK_WOFFSET                     0x0
+#define SLINK_STATUS_0_SCLK_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_SCLK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define SLINK_STATUS_0_SCLK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_SCLK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_SCLK_LOW                 _MK_ENUM_CONST(0)
+#define SLINK_STATUS_0_SCLK_HIGH                        _MK_ENUM_CONST(1)
+
+// Flush the RX FIFO
+#define SLINK_STATUS_0_RX_FLUSH_SHIFT                   _MK_SHIFT_CONST(27)
+#define SLINK_STATUS_0_RX_FLUSH_FIELD                   (_MK_MASK_CONST(0x1) << SLINK_STATUS_0_RX_FLUSH_SHIFT)
+#define SLINK_STATUS_0_RX_FLUSH_RANGE                   27:27
+#define SLINK_STATUS_0_RX_FLUSH_WOFFSET                 0x0
+#define SLINK_STATUS_0_RX_FLUSH_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_RX_FLUSH_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define SLINK_STATUS_0_RX_FLUSH_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_RX_FLUSH_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_RX_FLUSH_NOP                     _MK_ENUM_CONST(0)
+#define SLINK_STATUS_0_RX_FLUSH_FLUSH                   _MK_ENUM_CONST(1)
+
+// Flush the TX FIFO
+#define SLINK_STATUS_0_TX_FLUSH_SHIFT                   _MK_SHIFT_CONST(26)
+#define SLINK_STATUS_0_TX_FLUSH_FIELD                   (_MK_MASK_CONST(0x1) << SLINK_STATUS_0_TX_FLUSH_SHIFT)
+#define SLINK_STATUS_0_TX_FLUSH_RANGE                   26:26
+#define SLINK_STATUS_0_TX_FLUSH_WOFFSET                 0x0
+#define SLINK_STATUS_0_TX_FLUSH_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_TX_FLUSH_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define SLINK_STATUS_0_TX_FLUSH_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_TX_FLUSH_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_TX_FLUSH_NOP                     _MK_ENUM_CONST(0)
+#define SLINK_STATUS_0_TX_FLUSH_FLUSH                   _MK_ENUM_CONST(1)
+
+// RX FIFO Overflow
+#define SLINK_STATUS_0_RX_OVF_SHIFT                     _MK_SHIFT_CONST(25)
+#define SLINK_STATUS_0_RX_OVF_FIELD                     (_MK_MASK_CONST(0x1) << SLINK_STATUS_0_RX_OVF_SHIFT)
+#define SLINK_STATUS_0_RX_OVF_RANGE                     25:25
+#define SLINK_STATUS_0_RX_OVF_WOFFSET                   0x0
+#define SLINK_STATUS_0_RX_OVF_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_RX_OVF_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define SLINK_STATUS_0_RX_OVF_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_RX_OVF_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_RX_OVF_OK                        _MK_ENUM_CONST(0)
+#define SLINK_STATUS_0_RX_OVF_ERROR                     _MK_ENUM_CONST(1)
+
+// TX FIFO Underflow
+#define SLINK_STATUS_0_TX_UNF_SHIFT                     _MK_SHIFT_CONST(24)
+#define SLINK_STATUS_0_TX_UNF_FIELD                     (_MK_MASK_CONST(0x1) << SLINK_STATUS_0_TX_UNF_SHIFT)
+#define SLINK_STATUS_0_TX_UNF_RANGE                     24:24
+#define SLINK_STATUS_0_TX_UNF_WOFFSET                   0x0
+#define SLINK_STATUS_0_TX_UNF_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_TX_UNF_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define SLINK_STATUS_0_TX_UNF_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_TX_UNF_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_TX_UNF_OK                        _MK_ENUM_CONST(0)
+#define SLINK_STATUS_0_TX_UNF_ERROR                     _MK_ENUM_CONST(1)
+
+// RX FIFO Empty
+#define SLINK_STATUS_0_RX_EMPTY_SHIFT                   _MK_SHIFT_CONST(23)
+#define SLINK_STATUS_0_RX_EMPTY_FIELD                   (_MK_MASK_CONST(0x1) << SLINK_STATUS_0_RX_EMPTY_SHIFT)
+#define SLINK_STATUS_0_RX_EMPTY_RANGE                   23:23
+#define SLINK_STATUS_0_RX_EMPTY_WOFFSET                 0x0
+#define SLINK_STATUS_0_RX_EMPTY_DEFAULT                 _MK_MASK_CONST(0x1)
+#define SLINK_STATUS_0_RX_EMPTY_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define SLINK_STATUS_0_RX_EMPTY_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_RX_EMPTY_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_RX_EMPTY_NOT_EMPTY                       _MK_ENUM_CONST(0)
+#define SLINK_STATUS_0_RX_EMPTY_EMPTY                   _MK_ENUM_CONST(1)
+
+// RX FIFO Full
+#define SLINK_STATUS_0_RX_FULL_SHIFT                    _MK_SHIFT_CONST(22)
+#define SLINK_STATUS_0_RX_FULL_FIELD                    (_MK_MASK_CONST(0x1) << SLINK_STATUS_0_RX_FULL_SHIFT)
+#define SLINK_STATUS_0_RX_FULL_RANGE                    22:22
+#define SLINK_STATUS_0_RX_FULL_WOFFSET                  0x0
+#define SLINK_STATUS_0_RX_FULL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_RX_FULL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define SLINK_STATUS_0_RX_FULL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_RX_FULL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_RX_FULL_NOT_FULL                 _MK_ENUM_CONST(0)
+#define SLINK_STATUS_0_RX_FULL_FULL                     _MK_ENUM_CONST(1)
+
+// TX FIFO Empty
+#define SLINK_STATUS_0_TX_EMPTY_SHIFT                   _MK_SHIFT_CONST(21)
+#define SLINK_STATUS_0_TX_EMPTY_FIELD                   (_MK_MASK_CONST(0x1) << SLINK_STATUS_0_TX_EMPTY_SHIFT)
+#define SLINK_STATUS_0_TX_EMPTY_RANGE                   21:21
+#define SLINK_STATUS_0_TX_EMPTY_WOFFSET                 0x0
+#define SLINK_STATUS_0_TX_EMPTY_DEFAULT                 _MK_MASK_CONST(0x1)
+#define SLINK_STATUS_0_TX_EMPTY_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define SLINK_STATUS_0_TX_EMPTY_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_TX_EMPTY_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_TX_EMPTY_NOT_EMPTY                       _MK_ENUM_CONST(0)
+#define SLINK_STATUS_0_TX_EMPTY_EMPTY                   _MK_ENUM_CONST(1)
+
+// TX FIFO Full
+#define SLINK_STATUS_0_TX_FULL_SHIFT                    _MK_SHIFT_CONST(20)
+#define SLINK_STATUS_0_TX_FULL_FIELD                    (_MK_MASK_CONST(0x1) << SLINK_STATUS_0_TX_FULL_SHIFT)
+#define SLINK_STATUS_0_TX_FULL_RANGE                    20:20
+#define SLINK_STATUS_0_TX_FULL_WOFFSET                  0x0
+#define SLINK_STATUS_0_TX_FULL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_TX_FULL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define SLINK_STATUS_0_TX_FULL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_TX_FULL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_TX_FULL_NOT_FULL                 _MK_ENUM_CONST(0)
+#define SLINK_STATUS_0_TX_FULL_FULL                     _MK_ENUM_CONST(1)
+
+// TX FIFO Overflow
+#define SLINK_STATUS_0_TX_OVF_SHIFT                     _MK_SHIFT_CONST(19)
+#define SLINK_STATUS_0_TX_OVF_FIELD                     (_MK_MASK_CONST(0x1) << SLINK_STATUS_0_TX_OVF_SHIFT)
+#define SLINK_STATUS_0_TX_OVF_RANGE                     19:19
+#define SLINK_STATUS_0_TX_OVF_WOFFSET                   0x0
+#define SLINK_STATUS_0_TX_OVF_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_TX_OVF_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define SLINK_STATUS_0_TX_OVF_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_TX_OVF_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_TX_OVF_OK                        _MK_ENUM_CONST(0)
+#define SLINK_STATUS_0_TX_OVF_ERROR                     _MK_ENUM_CONST(1)
+
+// RX FIFO Underflow
+#define SLINK_STATUS_0_RX_UNF_SHIFT                     _MK_SHIFT_CONST(18)
+#define SLINK_STATUS_0_RX_UNF_FIELD                     (_MK_MASK_CONST(0x1) << SLINK_STATUS_0_RX_UNF_SHIFT)
+#define SLINK_STATUS_0_RX_UNF_RANGE                     18:18
+#define SLINK_STATUS_0_RX_UNF_WOFFSET                   0x0
+#define SLINK_STATUS_0_RX_UNF_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_RX_UNF_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define SLINK_STATUS_0_RX_UNF_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_RX_UNF_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_RX_UNF_OK                        _MK_ENUM_CONST(0)
+#define SLINK_STATUS_0_RX_UNF_ERROR                     _MK_ENUM_CONST(1)
+
+// Mode fault
+#define SLINK_STATUS_0_MODF_SHIFT                       _MK_SHIFT_CONST(16)
+#define SLINK_STATUS_0_MODF_FIELD                       (_MK_MASK_CONST(0x1) << SLINK_STATUS_0_MODF_SHIFT)
+#define SLINK_STATUS_0_MODF_RANGE                       16:16
+#define SLINK_STATUS_0_MODF_WOFFSET                     0x0
+#define SLINK_STATUS_0_MODF_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_MODF_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define SLINK_STATUS_0_MODF_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_MODF_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_MODF_OK                  _MK_ENUM_CONST(0)
+#define SLINK_STATUS_0_MODF_ERROR                       _MK_ENUM_CONST(1)
+
+// number of blocks transferred (BLOCK count) during dma
+#define SLINK_STATUS_0_BLK_CNT_SHIFT                    _MK_SHIFT_CONST(0)
+#define SLINK_STATUS_0_BLK_CNT_FIELD                    (_MK_MASK_CONST(0xffff) << SLINK_STATUS_0_BLK_CNT_SHIFT)
+#define SLINK_STATUS_0_BLK_CNT_RANGE                    15:0
+#define SLINK_STATUS_0_BLK_CNT_WOFFSET                  0x0
+#define SLINK_STATUS_0_BLK_CNT_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_BLK_CNT_DEFAULT_MASK                     _MK_MASK_CONST(0xffff)
+#define SLINK_STATUS_0_BLK_CNT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_BLK_CNT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// In GO mode indicates number of words transferred (word count) 
+#define SLINK_STATUS_0_WORD_SHIFT                       _MK_SHIFT_CONST(5)
+#define SLINK_STATUS_0_WORD_FIELD                       (_MK_MASK_CONST(0x1f) << SLINK_STATUS_0_WORD_SHIFT)
+#define SLINK_STATUS_0_WORD_RANGE                       9:5
+#define SLINK_STATUS_0_WORD_WOFFSET                     0x0
+#define SLINK_STATUS_0_WORD_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_WORD_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define SLINK_STATUS_0_WORD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_WORD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// In Go mode indicates mumber of bits trasnferred (bit count)
+#define SLINK_STATUS_0_COUNT_SHIFT                      _MK_SHIFT_CONST(0)
+#define SLINK_STATUS_0_COUNT_FIELD                      (_MK_MASK_CONST(0x1f) << SLINK_STATUS_0_COUNT_SHIFT)
+#define SLINK_STATUS_0_COUNT_RANGE                      4:0
+#define SLINK_STATUS_0_COUNT_WOFFSET                    0x0
+#define SLINK_STATUS_0_COUNT_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_COUNT_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define SLINK_STATUS_0_COUNT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_COUNT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Reserved address 12 [0xc] 
+
+// Register SLINK_MAS_DATA_0  
+#define SLINK_MAS_DATA_0                        _MK_ADDR_CONST(0x10)
+#define SLINK_MAS_DATA_0_SECURE                         0x0
+#define SLINK_MAS_DATA_0_WORD_COUNT                     0x1
+#define SLINK_MAS_DATA_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define SLINK_MAS_DATA_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
+#define SLINK_MAS_DATA_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define SLINK_MAS_DATA_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define SLINK_MAS_DATA_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define SLINK_MAS_DATA_0_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
+// Tx/Rx Shift Pattern
+#define SLINK_MAS_DATA_0_MASTER_BUFFER_SHIFT                    _MK_SHIFT_CONST(0)
+#define SLINK_MAS_DATA_0_MASTER_BUFFER_FIELD                    (_MK_MASK_CONST(0xffffffff) << SLINK_MAS_DATA_0_MASTER_BUFFER_SHIFT)
+#define SLINK_MAS_DATA_0_MASTER_BUFFER_RANGE                    31:0
+#define SLINK_MAS_DATA_0_MASTER_BUFFER_WOFFSET                  0x0
+#define SLINK_MAS_DATA_0_MASTER_BUFFER_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SLINK_MAS_DATA_0_MASTER_BUFFER_DEFAULT_MASK                     _MK_MASK_CONST(0xffffffff)
+#define SLINK_MAS_DATA_0_MASTER_BUFFER_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SLINK_MAS_DATA_0_MASTER_BUFFER_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register SLINK_SLAVE_DATA_0  
+#define SLINK_SLAVE_DATA_0                      _MK_ADDR_CONST(0x14)
+#define SLINK_SLAVE_DATA_0_SECURE                       0x0
+#define SLINK_SLAVE_DATA_0_WORD_COUNT                   0x1
+#define SLINK_SLAVE_DATA_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define SLINK_SLAVE_DATA_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define SLINK_SLAVE_DATA_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define SLINK_SLAVE_DATA_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define SLINK_SLAVE_DATA_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
+#define SLINK_SLAVE_DATA_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
+// Tx/Rx Shift Pattern
+#define SLINK_SLAVE_DATA_0_SLAVE_BUFFER_SHIFT                   _MK_SHIFT_CONST(0)
+#define SLINK_SLAVE_DATA_0_SLAVE_BUFFER_FIELD                   (_MK_MASK_CONST(0xffffffff) << SLINK_SLAVE_DATA_0_SLAVE_BUFFER_SHIFT)
+#define SLINK_SLAVE_DATA_0_SLAVE_BUFFER_RANGE                   31:0
+#define SLINK_SLAVE_DATA_0_SLAVE_BUFFER_WOFFSET                 0x0
+#define SLINK_SLAVE_DATA_0_SLAVE_BUFFER_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SLINK_SLAVE_DATA_0_SLAVE_BUFFER_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
+#define SLINK_SLAVE_DATA_0_SLAVE_BUFFER_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SLINK_SLAVE_DATA_0_SLAVE_BUFFER_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register SLINK_DMA_CTL_0  
+#define SLINK_DMA_CTL_0                 _MK_ADDR_CONST(0x18)
+#define SLINK_DMA_CTL_0_SECURE                  0x0
+#define SLINK_DMA_CTL_0_WORD_COUNT                      0x1
+#define SLINK_DMA_CTL_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define SLINK_DMA_CTL_0_RESET_MASK                      _MK_MASK_CONST(0x8c7fffff)
+#define SLINK_DMA_CTL_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define SLINK_DMA_CTL_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define SLINK_DMA_CTL_0_READ_MASK                       _MK_MASK_CONST(0x8c7fffff)
+#define SLINK_DMA_CTL_0_WRITE_MASK                      _MK_MASK_CONST(0x8c7fffff)
+//  1 = DMA mode is enabled, 0 = DMA disabled
+#define SLINK_DMA_CTL_0_DMA_EN_SHIFT                    _MK_SHIFT_CONST(31)
+#define SLINK_DMA_CTL_0_DMA_EN_FIELD                    (_MK_MASK_CONST(0x1) << SLINK_DMA_CTL_0_DMA_EN_SHIFT)
+#define SLINK_DMA_CTL_0_DMA_EN_RANGE                    31:31
+#define SLINK_DMA_CTL_0_DMA_EN_WOFFSET                  0x0
+#define SLINK_DMA_CTL_0_DMA_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SLINK_DMA_CTL_0_DMA_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define SLINK_DMA_CTL_0_DMA_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SLINK_DMA_CTL_0_DMA_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define SLINK_DMA_CTL_0_DMA_EN_DISABLE                  _MK_ENUM_CONST(0)
+#define SLINK_DMA_CTL_0_DMA_EN_ENABLE                   _MK_ENUM_CONST(1)
+
+// Interrupt enable on receive completion.
+// 1 = Enable interrupt generation at the end of a receive transfer.
+// 0 = Disable interrupt generation for receive.
+#define SLINK_DMA_CTL_0_IE_RXC_SHIFT                    _MK_SHIFT_CONST(27)
+#define SLINK_DMA_CTL_0_IE_RXC_FIELD                    (_MK_MASK_CONST(0x1) << SLINK_DMA_CTL_0_IE_RXC_SHIFT)
+#define SLINK_DMA_CTL_0_IE_RXC_RANGE                    27:27
+#define SLINK_DMA_CTL_0_IE_RXC_WOFFSET                  0x0
+#define SLINK_DMA_CTL_0_IE_RXC_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SLINK_DMA_CTL_0_IE_RXC_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define SLINK_DMA_CTL_0_IE_RXC_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SLINK_DMA_CTL_0_IE_RXC_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define SLINK_DMA_CTL_0_IE_RXC_DISABLE                  _MK_ENUM_CONST(0)
+#define SLINK_DMA_CTL_0_IE_RXC_ENABLE                   _MK_ENUM_CONST(1)
+
+// Interrupt enable on transmit completion.
+// 1 = Enable interrupt generation at the end of a transmit transfer.
+// 0 = Disable interrupt generation for transmit.
+#define SLINK_DMA_CTL_0_IE_TXC_SHIFT                    _MK_SHIFT_CONST(26)
+#define SLINK_DMA_CTL_0_IE_TXC_FIELD                    (_MK_MASK_CONST(0x1) << SLINK_DMA_CTL_0_IE_TXC_SHIFT)
+#define SLINK_DMA_CTL_0_IE_TXC_RANGE                    26:26
+#define SLINK_DMA_CTL_0_IE_TXC_WOFFSET                  0x0
+#define SLINK_DMA_CTL_0_IE_TXC_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SLINK_DMA_CTL_0_IE_TXC_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define SLINK_DMA_CTL_0_IE_TXC_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SLINK_DMA_CTL_0_IE_TXC_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define SLINK_DMA_CTL_0_IE_TXC_DISABLE                  _MK_ENUM_CONST(0)
+#define SLINK_DMA_CTL_0_IE_TXC_ENABLE                   _MK_ENUM_CONST(1)
+
+// Specifies the packet size during the DMA mode
+//             00      = 4 bits in a pack
+//           01      = 8bits in a pack
+//            10      = 16 in a pack
+//               10      = 32 in a pack
+#define SLINK_DMA_CTL_0_PACK_SIZE_SHIFT                 _MK_SHIFT_CONST(21)
+#define SLINK_DMA_CTL_0_PACK_SIZE_FIELD                 (_MK_MASK_CONST(0x3) << SLINK_DMA_CTL_0_PACK_SIZE_SHIFT)
+#define SLINK_DMA_CTL_0_PACK_SIZE_RANGE                 22:21
+#define SLINK_DMA_CTL_0_PACK_SIZE_WOFFSET                       0x0
+#define SLINK_DMA_CTL_0_PACK_SIZE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SLINK_DMA_CTL_0_PACK_SIZE_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define SLINK_DMA_CTL_0_PACK_SIZE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SLINK_DMA_CTL_0_PACK_SIZE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define SLINK_DMA_CTL_0_PACK_SIZE_PACK4                 _MK_ENUM_CONST(0)
+#define SLINK_DMA_CTL_0_PACK_SIZE_PACK8                 _MK_ENUM_CONST(1)
+#define SLINK_DMA_CTL_0_PACK_SIZE_PACK16                        _MK_ENUM_CONST(2)
+#define SLINK_DMA_CTL_0_PACK_SIZE_PACK32                        _MK_ENUM_CONST(3)
+
+// Packed mode enable bit.
+//  1 = Packed mode is enabled. This is only valid if BIT_LENGTH in SBCX_COMMAND register is set to 3, 7, 15 or 31
+// When enabled, all 32-bits of data in the FIFO contains valid
+// data packets of either 8-bit or 16-bit length.
+// 0 = Packed mode is disabled.
+#define SLINK_DMA_CTL_0_PACKED_SHIFT                    _MK_SHIFT_CONST(20)
+#define SLINK_DMA_CTL_0_PACKED_FIELD                    (_MK_MASK_CONST(0x1) << SLINK_DMA_CTL_0_PACKED_SHIFT)
+#define SLINK_DMA_CTL_0_PACKED_RANGE                    20:20
+#define SLINK_DMA_CTL_0_PACKED_WOFFSET                  0x0
+#define SLINK_DMA_CTL_0_PACKED_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SLINK_DMA_CTL_0_PACKED_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define SLINK_DMA_CTL_0_PACKED_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SLINK_DMA_CTL_0_PACKED_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define SLINK_DMA_CTL_0_PACKED_DISABLE                  _MK_ENUM_CONST(0)
+#define SLINK_DMA_CTL_0_PACKED_ENABLE                   _MK_ENUM_CONST(1)
+
+// Receive FIFO trigger level.
+// 00: 1 word. DMA trigger is asserted whenever there is at least 1 word in the RX FIFO.
+// 01: 4 word. DMA trigger is asserted when there are at least 4 words in the RX FIFO.
+// 10: 8 word. DMA trigger is asserted when there are at least 8 words in the RX FIFO.
+// 11: 16 word. DMA trigger is asserted when there are at least 16 words in the RX FIFO.
+#define SLINK_DMA_CTL_0_RX_TRIG_SHIFT                   _MK_SHIFT_CONST(18)
+#define SLINK_DMA_CTL_0_RX_TRIG_FIELD                   (_MK_MASK_CONST(0x3) << SLINK_DMA_CTL_0_RX_TRIG_SHIFT)
+#define SLINK_DMA_CTL_0_RX_TRIG_RANGE                   19:18
+#define SLINK_DMA_CTL_0_RX_TRIG_WOFFSET                 0x0
+#define SLINK_DMA_CTL_0_RX_TRIG_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SLINK_DMA_CTL_0_RX_TRIG_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define SLINK_DMA_CTL_0_RX_TRIG_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SLINK_DMA_CTL_0_RX_TRIG_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define SLINK_DMA_CTL_0_RX_TRIG_TRIG1                   _MK_ENUM_CONST(0)
+#define SLINK_DMA_CTL_0_RX_TRIG_TRIG4                   _MK_ENUM_CONST(1)
+#define SLINK_DMA_CTL_0_RX_TRIG_TRIG8                   _MK_ENUM_CONST(2)
+#define SLINK_DMA_CTL_0_RX_TRIG_TRIG16                  _MK_ENUM_CONST(3)
+
+// Transmit FIFO trigger level.
+// 00: 1 word. DMA trigger is asserted whenever there is at least 1 word in the TX FIFO.
+// 01: 4 word. DMA trigger is asserted when there are at least 4 words in the TX FIFO.
+// 10: 8 word. DMA trigger is asserted when there are at least 8 words in the TX FIFO.
+// 11: 16 word. DMA trigger is asserted when there are at least 16 words in the TX FIFO.
+#define SLINK_DMA_CTL_0_TX_TRIG_SHIFT                   _MK_SHIFT_CONST(16)
+#define SLINK_DMA_CTL_0_TX_TRIG_FIELD                   (_MK_MASK_CONST(0x3) << SLINK_DMA_CTL_0_TX_TRIG_SHIFT)
+#define SLINK_DMA_CTL_0_TX_TRIG_RANGE                   17:16
+#define SLINK_DMA_CTL_0_TX_TRIG_WOFFSET                 0x0
+#define SLINK_DMA_CTL_0_TX_TRIG_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SLINK_DMA_CTL_0_TX_TRIG_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define SLINK_DMA_CTL_0_TX_TRIG_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SLINK_DMA_CTL_0_TX_TRIG_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define SLINK_DMA_CTL_0_TX_TRIG_TRIG1                   _MK_ENUM_CONST(0)
+#define SLINK_DMA_CTL_0_TX_TRIG_TRIG4                   _MK_ENUM_CONST(1)
+#define SLINK_DMA_CTL_0_TX_TRIG_TRIG8                   _MK_ENUM_CONST(2)
+#define SLINK_DMA_CTL_0_TX_TRIG_TRIG16                  _MK_ENUM_CONST(3)
+
+// N = N+1 packets
+// number of packets should be aligned in the packed mode trasnfers.
+// packed mode     --> Number of packets
+//    3                                        multiple of 8
+//    7                                   multiple of 4
+//    15                          multiple of 2
+//    31                          from 0 to N
+#define SLINK_DMA_CTL_0_DMA_BLOCK_SIZE_SHIFT                    _MK_SHIFT_CONST(0)
+#define SLINK_DMA_CTL_0_DMA_BLOCK_SIZE_FIELD                    (_MK_MASK_CONST(0xffff) << SLINK_DMA_CTL_0_DMA_BLOCK_SIZE_SHIFT)
+#define SLINK_DMA_CTL_0_DMA_BLOCK_SIZE_RANGE                    15:0
+#define SLINK_DMA_CTL_0_DMA_BLOCK_SIZE_WOFFSET                  0x0
+#define SLINK_DMA_CTL_0_DMA_BLOCK_SIZE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SLINK_DMA_CTL_0_DMA_BLOCK_SIZE_DEFAULT_MASK                     _MK_MASK_CONST(0xffff)
+#define SLINK_DMA_CTL_0_DMA_BLOCK_SIZE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SLINK_DMA_CTL_0_DMA_BLOCK_SIZE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register SLINK_STATUS2_0  
+#define SLINK_STATUS2_0                 _MK_ADDR_CONST(0x1c)
+#define SLINK_STATUS2_0_SECURE                  0x0
+#define SLINK_STATUS2_0_WORD_COUNT                      0x1
+#define SLINK_STATUS2_0_RESET_VAL                       _MK_MASK_CONST(0x20)
+#define SLINK_STATUS2_0_RESET_MASK                      _MK_MASK_CONST(0x3f003f)
+#define SLINK_STATUS2_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define SLINK_STATUS2_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define SLINK_STATUS2_0_READ_MASK                       _MK_MASK_CONST(0x3f003f)
+#define SLINK_STATUS2_0_WRITE_MASK                      _MK_MASK_CONST(0x3f003f)
+// Indicates the number of words in the receive FIFO 
+#define SLINK_STATUS2_0_RX_FIFO_FULL_COUNT_SHIFT                        _MK_SHIFT_CONST(16)
+#define SLINK_STATUS2_0_RX_FIFO_FULL_COUNT_FIELD                        (_MK_MASK_CONST(0x3f) << SLINK_STATUS2_0_RX_FIFO_FULL_COUNT_SHIFT)
+#define SLINK_STATUS2_0_RX_FIFO_FULL_COUNT_RANGE                        21:16
+#define SLINK_STATUS2_0_RX_FIFO_FULL_COUNT_WOFFSET                      0x0
+#define SLINK_STATUS2_0_RX_FIFO_FULL_COUNT_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SLINK_STATUS2_0_RX_FIFO_FULL_COUNT_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
+#define SLINK_STATUS2_0_RX_FIFO_FULL_COUNT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SLINK_STATUS2_0_RX_FIFO_FULL_COUNT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Indicates the number of empty slots in the transmit FIFO 
+#define SLINK_STATUS2_0_TX_FIFO_EMPTY_COUNT_SHIFT                       _MK_SHIFT_CONST(0)
+#define SLINK_STATUS2_0_TX_FIFO_EMPTY_COUNT_FIELD                       (_MK_MASK_CONST(0x3f) << SLINK_STATUS2_0_TX_FIFO_EMPTY_COUNT_SHIFT)
+#define SLINK_STATUS2_0_TX_FIFO_EMPTY_COUNT_RANGE                       5:0
+#define SLINK_STATUS2_0_TX_FIFO_EMPTY_COUNT_WOFFSET                     0x0
+#define SLINK_STATUS2_0_TX_FIFO_EMPTY_COUNT_DEFAULT                     _MK_MASK_CONST(0x20)
+#define SLINK_STATUS2_0_TX_FIFO_EMPTY_COUNT_DEFAULT_MASK                        _MK_MASK_CONST(0x3f)
+#define SLINK_STATUS2_0_TX_FIFO_EMPTY_COUNT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SLINK_STATUS2_0_TX_FIFO_EMPTY_COUNT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Reserved address 32 [0x20] 
+
+// Reserved address 36 [0x24] 
+
+// Reserved address 40 [0x28] 
+
+// Reserved address 44 [0x2c] 
+
+// Reserved address 48 [0x30] 
+
+// Reserved address 52 [0x34] 
+
+// Reserved address 56 [0x38] 
+
+// Reserved address 60 [0x3c] 
+
+// Reserved address 64 [0x40] 
+
+// Reserved address 68 [0x44] 
+
+// Reserved address 72 [0x48] 
+
+// Reserved address 76 [0x4c] 
+
+// Reserved address 80 [0x50] 
+
+// Reserved address 84 [0x54] 
+
+// Reserved address 88 [0x58] 
+
+// Reserved address 92 [0x5c] 
+
+// Reserved address 96 [0x60] 
+
+// Reserved address 100 [0x64] 
+
+// Reserved address 104 [0x68] 
+
+// Reserved address 108 [0x6c] 
+
+// Reserved address 112 [0x70] 
+
+// Reserved address 116 [0x74] 
+
+// Reserved address 120 [0x78] 
+
+// Reserved address 124 [0x7c] 
+
+// Reserved address 128 [0x80] 
+
+// Reserved address 132 [0x84] 
+
+// Reserved address 136 [0x88] 
+
+// Reserved address 140 [0x8c] 
+
+// Reserved address 144 [0x90] 
+
+// Reserved address 148 [0x94] 
+
+// Reserved address 152 [0x98] 
+
+// Reserved address 156 [0x9c] 
+
+// Reserved address 160 [0xa0] 
+
+// Reserved address 164 [0xa4] 
+
+// Reserved address 168 [0xa8] 
+
+// Reserved address 172 [0xac] 
+
+// Reserved address 176 [0xb0] 
+
+// Reserved address 180 [0xb4] 
+
+// Reserved address 184 [0xb8] 
+
+// Reserved address 188 [0xbc] 
+
+// Reserved address 192 [0xc0] 
+
+// Reserved address 196 [0xc4] 
+
+// Reserved address 200 [0xc8] 
+
+// Reserved address 204 [0xcc] 
+
+// Reserved address 208 [0xd0] 
+
+// Reserved address 212 [0xd4] 
+
+// Reserved address 216 [0xd8] 
+
+// Reserved address 220 [0xdc] 
+
+// Reserved address 224 [0xe0] 
+
+// Reserved address 228 [0xe4] 
+
+// Reserved address 232 [0xe8] 
+
+// Reserved address 236 [0xec] 
+
+// Reserved address 240 [0xf0] 
+
+// Reserved address 244 [0xf4] 
+
+// Reserved address 248 [0xf8] 
+
+// Reserved address 252 [0xfc] 
+
+// Register SLINK_TX_FIFO_0  
+#define SLINK_TX_FIFO_0                 _MK_ADDR_CONST(0x100)
+#define SLINK_TX_FIFO_0_SECURE                  0x0
+#define SLINK_TX_FIFO_0_WORD_COUNT                      0x1
+#define SLINK_TX_FIFO_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define SLINK_TX_FIFO_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define SLINK_TX_FIFO_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define SLINK_TX_FIFO_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define SLINK_TX_FIFO_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define SLINK_TX_FIFO_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Tx/Rx Shift Pattern
+#define SLINK_TX_FIFO_0_TX_FIFO_REGISTER_SHIFT                  _MK_SHIFT_CONST(0)
+#define SLINK_TX_FIFO_0_TX_FIFO_REGISTER_FIELD                  (_MK_MASK_CONST(0xffffffff) << SLINK_TX_FIFO_0_TX_FIFO_REGISTER_SHIFT)
+#define SLINK_TX_FIFO_0_TX_FIFO_REGISTER_RANGE                  31:0
+#define SLINK_TX_FIFO_0_TX_FIFO_REGISTER_WOFFSET                        0x0
+#define SLINK_TX_FIFO_0_TX_FIFO_REGISTER_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SLINK_TX_FIFO_0_TX_FIFO_REGISTER_DEFAULT_MASK                   _MK_MASK_CONST(0xffffffff)
+#define SLINK_TX_FIFO_0_TX_FIFO_REGISTER_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SLINK_TX_FIFO_0_TX_FIFO_REGISTER_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Reserved address 260 [0x104] 
+
+// Reserved address 264 [0x108] 
+
+// Reserved address 268 [0x10c] 
+
+// Reserved address 272 [0x110] 
+
+// Reserved address 276 [0x114] 
+
+// Reserved address 280 [0x118] 
+
+// Reserved address 284 [0x11c] 
+
+// Reserved address 288 [0x120] 
+
+// Reserved address 292 [0x124] 
+
+// Reserved address 296 [0x128] 
+
+// Reserved address 300 [0x12c] 
+
+// Reserved address 304 [0x130] 
+
+// Reserved address 308 [0x134] 
+
+// Reserved address 312 [0x138] 
+
+// Reserved address 316 [0x13c] 
+
+// Reserved address 320 [0x140] 
+
+// Reserved address 324 [0x144] 
+
+// Reserved address 328 [0x148] 
+
+// Reserved address 332 [0x14c] 
+
+// Reserved address 336 [0x150] 
+
+// Reserved address 340 [0x154] 
+
+// Reserved address 344 [0x158] 
+
+// Reserved address 348 [0x15c] 
+
+// Reserved address 352 [0x160] 
+
+// Reserved address 356 [0x164] 
+
+// Reserved address 360 [0x168] 
+
+// Reserved address 364 [0x16c] 
+
+// Reserved address 368 [0x170] 
+
+// Reserved address 372 [0x174] 
+
+// Reserved address 376 [0x178] 
+
+// Reserved address 380 [0x17c] 
+
+// Register SLINK_RX_FIFO_0  
+#define SLINK_RX_FIFO_0                 _MK_ADDR_CONST(0x180)
+#define SLINK_RX_FIFO_0_SECURE                  0x0
+#define SLINK_RX_FIFO_0_WORD_COUNT                      0x1
+#define SLINK_RX_FIFO_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define SLINK_RX_FIFO_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define SLINK_RX_FIFO_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define SLINK_RX_FIFO_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define SLINK_RX_FIFO_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define SLINK_RX_FIFO_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Tx/Rx Shift Pattern
+#define SLINK_RX_FIFO_0_RX_FIFO_REGISTER_SHIFT                  _MK_SHIFT_CONST(0)
+#define SLINK_RX_FIFO_0_RX_FIFO_REGISTER_FIELD                  (_MK_MASK_CONST(0xffffffff) << SLINK_RX_FIFO_0_RX_FIFO_REGISTER_SHIFT)
+#define SLINK_RX_FIFO_0_RX_FIFO_REGISTER_RANGE                  31:0
+#define SLINK_RX_FIFO_0_RX_FIFO_REGISTER_WOFFSET                        0x0
+#define SLINK_RX_FIFO_0_RX_FIFO_REGISTER_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SLINK_RX_FIFO_0_RX_FIFO_REGISTER_DEFAULT_MASK                   _MK_MASK_CONST(0xffffffff)
+#define SLINK_RX_FIFO_0_RX_FIFO_REGISTER_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SLINK_RX_FIFO_0_RX_FIFO_REGISTER_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+//
+// REGISTER LIST
+//
+#define LIST_ARSLINK_REGS(_op_) \
+_op_(SLINK_COMMAND_0) \
+_op_(SLINK_COMMAND2_0) \
+_op_(SLINK_STATUS_0) \
+_op_(SLINK_MAS_DATA_0) \
+_op_(SLINK_SLAVE_DATA_0) \
+_op_(SLINK_DMA_CTL_0) \
+_op_(SLINK_STATUS2_0) \
+_op_(SLINK_TX_FIFO_0) \
+_op_(SLINK_RX_FIFO_0)
+
+
+//
+// ADDRESS SPACES
+//
+
+#define BASE_ADDRESS_SLINK      0x00000000
+
+//
+// ARSLINK REGISTER BANKS
+//
+
+#define SLINK0_FIRST_REG 0x0000 // SLINK_COMMAND_0
+#define SLINK0_LAST_REG 0x0008 // SLINK_STATUS_0
+#define SLINK1_FIRST_REG 0x0010 // SLINK_MAS_DATA_0
+#define SLINK1_LAST_REG 0x001c // SLINK_STATUS2_0
+#define SLINK2_FIRST_REG 0x0100 // SLINK_TX_FIFO_0
+#define SLINK2_LAST_REG 0x0100 // SLINK_TX_FIFO_0
+#define SLINK3_FIRST_REG 0x0180 // SLINK_RX_FIFO_0
+#define SLINK3_LAST_REG 0x0180 // SLINK_RX_FIFO_0
+
+#ifndef _MK_SHIFT_CONST
+  #define _MK_SHIFT_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_MASK_CONST
+  #define _MK_MASK_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_ENUM_CONST
+  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
+#endif
+#ifndef _MK_ADDR_CONST
+  #define _MK_ADDR_CONST(_constant_) _constant_
+#endif
+
+#endif // ifndef ___ARSLINK_H_INC_
diff --git a/arch/arm/mach-tegra/include/ap20/project_relocation_table.h b/arch/arm/mach-tegra/include/ap20/project_relocation_table.h
new file mode 100644
index 000000000000..2276060dd560
--- /dev/null
+++ b/arch/arm/mach-tegra/include/ap20/project_relocation_table.h
@@ -0,0 +1,586 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+#ifndef PROJECT_AP15_RELOCATION_TABLE_SPEC_INC
+#define PROJECT_AP15_RELOCATION_TABLE_SPEC_INC
+
+// ------------------------------------------------------------
+//    hw nvdevids
+// ------------------------------------------------------------
+// Memory Aperture: Internal Memory
+#define NV_DEVID_IMEM                            1
+
+// Memory Aperture: External Memory
+#define NV_DEVID_EMEM                            2
+
+// Memory Aperture: TCRAM
+#define NV_DEVID_TCRAM                           3
+
+// Memory Aperture: IRAM
+#define NV_DEVID_IRAM                            4
+
+// Memory Aperture: NOR FLASH
+#define NV_DEVID_NOR                             5
+
+// Memory Aperture: EXIO
+#define NV_DEVID_EXIO                            6
+
+// Memory Aperture: GART
+#define NV_DEVID_GART                            7
+
+// Device Aperture: Graphics Host (HOST1X)
+#define NV_DEVID_HOST1X                          8
+
+// Device Aperture: ARM PERIPH registers
+#define NV_DEVID_ARM_PERIPH                      9
+
+// Device Aperture: MSELECT
+#define NV_DEVID_MSELECT                         10
+
+// Device Aperture: memory controller
+#define NV_DEVID_MC                              11
+
+// Device Aperture: external memory controller
+#define NV_DEVID_EMC                             12
+
+// Device Aperture: video input
+#define NV_DEVID_VI                              13
+
+// Device Aperture: encoder pre-processor
+#define NV_DEVID_EPP                             14
+
+// Device Aperture: video encoder
+#define NV_DEVID_MPE                             15
+
+// Device Aperture: 3D engine
+#define NV_DEVID_GR3D                            16
+
+// Device Aperture: 2D + SBLT engine
+#define NV_DEVID_GR2D                            17
+
+// Device Aperture: Image Signal Processor
+#define NV_DEVID_ISP                             18
+
+// Device Aperture: DISPLAY
+#define NV_DEVID_DISPLAY                         19
+
+// Device Aperture: UPTAG
+#define NV_DEVID_UPTAG                           20
+
+// Device Aperture - SHR_SEM
+#define NV_DEVID_SHR_SEM                         21
+
+// Device Aperture - ARB_SEM
+#define NV_DEVID_ARB_SEM                         22
+
+// Device Aperture - ARB_PRI
+#define NV_DEVID_ARB_PRI                         23
+
+// Obsoleted for AP15
+#define NV_DEVID_PRI_INTR                        24
+
+// Obsoleted for AP15
+#define NV_DEVID_SEC_INTR                        25
+
+// Device Aperture: Timer Programmable
+#define NV_DEVID_TMR                             26
+
+// Device Aperture: Clock and Reset
+#define NV_DEVID_CAR                             27
+
+// Device Aperture: Flow control
+#define NV_DEVID_FLOW                            28
+
+// Device Aperture: Event
+#define NV_DEVID_EVENT                           29
+
+// Device Aperture: AHB DMA
+#define NV_DEVID_AHB_DMA                         30
+
+// Device Aperture: APB DMA
+#define NV_DEVID_APB_DMA                         31
+
+// Device Aperture: COP Cache Controller
+#define NV_DEVID_COP_CACHE                       32
+
+// Obsolete - use COP_CACHE
+#define NV_DEVID_CC                              32
+
+// Obsolete - use COP_CACHE
+#define NV_DEVID_SYS_REG                         32
+
+// Device Aperture: System Statistic monitor
+#define NV_DEVID_STAT                            33
+
+// Device Aperture: GPIO
+#define NV_DEVID_GPIO                            34
+
+// Device Aperture: Vector Co-Processor 2
+#define NV_DEVID_VCP                             35
+
+// Device Aperture: Arm Vectors
+#define NV_DEVID_VECTOR                          36
+
+// Device: MEM
+#define NV_DEVID_MEM                             37
+
+// Obsolete - use VDE
+#define NV_DEVID_SXE                             38
+
+// Device Aperture: video decoder
+#define NV_DEVID_VDE                             38
+
+// Obsolete - use VDE
+#define NV_DEVID_BSEV                            39
+
+// Obsolete - use VDE
+#define NV_DEVID_MBE                             40
+
+// Obsolete - use VDE
+#define NV_DEVID_PPE                             41
+
+// Obsolete - use VDE
+#define NV_DEVID_MCE                             42
+
+// Obsolete - use VDE
+#define NV_DEVID_TFE                             43
+
+// Obsolete - use VDE
+#define NV_DEVID_PPB                             44
+
+// Obsolete - use VDE
+#define NV_DEVID_VDMA                            45
+
+// Obsolete - use VDE
+#define NV_DEVID_UCQ                             46
+
+// Device Aperture: BSEA (now in AVP cluster)
+#define NV_DEVID_BSEA                            47
+
+// Obsolete - use VDE
+#define NV_DEVID_FRAMEID                         48
+
+// Device Aperture: Misc regs
+#define NV_DEVID_MISC                            49
+
+// Device Aperture: AC97
+#define NV_DEVID_AC97                            50
+
+// Device Aperture: S/P-DIF
+#define NV_DEVID_SPDIF                           51
+
+// Device Aperture: I2S
+#define NV_DEVID_I2S                             52
+
+// Device Aperture: UART
+#define NV_DEVID_UART                            53
+
+// Device Aperture: VFIR
+#define NV_DEVID_VFIR                            54
+
+// Device Aperture: NAND Flash Controller
+#define NV_DEVID_NANDCTRL                        55
+
+// Obsolete - use NANDCTRL
+#define NV_DEVID_NANDFLASH                       55
+
+// Device Aperture: HSMMC
+#define NV_DEVID_HSMMC                           56
+
+// Device Aperture: XIO
+#define NV_DEVID_XIO                             57
+
+// Device Aperture: PWFM
+#define NV_DEVID_PWFM                            58
+
+// Device Aperture: MIPI
+#define NV_DEVID_MIPI_HS                         59
+
+// Device Aperture: I2C
+#define NV_DEVID_I2C                             60
+
+// Device Aperture: TWC
+#define NV_DEVID_TWC                             61
+
+// Device Aperture: SLINK
+#define NV_DEVID_SLINK                           62
+
+// Device Aperture: SLINK4B
+#define NV_DEVID_SLINK4B                         63
+
+// Device Aperture: SPI
+#define NV_DEVID_SPI                             64
+
+// Device Aperture: DVC
+#define NV_DEVID_DVC                             65
+
+// Device Aperture: RTC
+#define NV_DEVID_RTC                             66
+
+// Device Aperture: KeyBoard Controller
+#define NV_DEVID_KBC                             67
+
+// Device Aperture: PMIF
+#define NV_DEVID_PMIF                            68
+
+// Device Aperture: FUSE
+#define NV_DEVID_FUSE                            69
+
+// Device Aperture: L2 Cache Controller
+#define NV_DEVID_CMC                             70
+
+// Device Apertuer: NOR FLASH Controller
+#define NV_DEVID_NOR_REG                         71
+
+// Device Aperture: EIDE
+#define NV_DEVID_EIDE                            72
+
+// Device Aperture: USB
+#define NV_DEVID_USB                             73
+
+// Device Aperture: SDIO
+#define NV_DEVID_SDIO                            74
+
+// Device Aperture: TVO
+#define NV_DEVID_TVO                             75
+
+// Device Aperture: DSI
+#define NV_DEVID_DSI                             76
+
+// Device Aperture: HDMI
+#define NV_DEVID_HDMI                            77
+
+// Device Aperture: Third Interrupt Controller extra registers
+#define NV_DEVID_TRI_INTR                        78
+
+// Device Aperture: Common Interrupt Controller
+#define NV_DEVID_ICTLR                           79
+
+// Non-Aperture Interrupt: DMA TX interrupts
+#define NV_DEVID_DMA_TX_INTR                     80
+
+// Non-Aperture Interrupt: DMA RX interrupts
+#define NV_DEVID_DMA_RX_INTR                     81
+
+// Non-Aperture Interrupt: SW reserved interrupt
+#define NV_DEVID_SW_INTR                         82
+
+// Non-Aperture Interrupt: CPU PMU Interrupt
+#define NV_DEVID_CPU_INTR                        83
+
+// Device Aperture: Timer Free Running MicroSecond
+#define NV_DEVID_TMRUS                           84
+
+// Device Aperture: Interrupt Controller ARB_GNT Registers
+#define NV_DEVID_ICTLR_ARBGNT                    85
+
+// Device Aperture: Interrupt Controller DMA Registers
+#define NV_DEVID_ICTLR_DRQ                       86
+
+// Device Aperture: AHB DMA Channel
+#define NV_DEVID_AHB_DMA_CH                      87
+
+// Device Aperture: APB DMA Channel
+#define NV_DEVID_APB_DMA_CH                      88
+
+// Device Aperture: AHB Arbitration Controller
+#define NV_DEVID_AHB_ARBC                        89
+
+// Obsolete - use AHB_ARBC
+#define NV_DEVID_AHB_ARB_CTRL                    89
+
+// Device Aperture: AHB/APB Debug Bus Registers
+#define NV_DEVID_AHPBDEBUG                       91
+
+// Device Aperture: Secure Boot Register
+#define NV_DEVID_SECURE_BOOT                     92
+
+// Device Aperture: SPROM
+#define NV_DEVID_SPROM                           93
+
+// Memory Aperture: AHB external memory remapping
+#define NV_DEVID_AHB_EMEM                        94
+
+// Non-Aperture Interrupt: External PMU interrupt
+#define NV_DEVID_PMU_EXT                         95
+
+// Device Aperture: AHB EMEM to MC Flush Register
+#define NV_DEVID_PPCS                            96
+
+// Device Aperture: MMU TLB registers for COP/AVP
+#define NV_DEVID_MMU_TLB                         97
+
+// Device Aperture: OVG engine
+#define NV_DEVID_VG                              98
+
+// Device Aperture: CSI
+#define NV_DEVID_CSI                             99
+
+// Device ID for COP
+#define NV_DEVID_AVP                             100
+
+// Device ID for MPCORE
+#define NV_DEVID_CPU                             101
+
+// Device Aperture: ULPI controller
+#define NV_DEVID_ULPI                            102
+
+// Device Aperture: ARM CONFIG registers
+#define NV_DEVID_ARM_CONFIG                      103
+
+// Device Aperture: ARM PL310 (L2 controller)
+#define NV_DEVID_ARM_PL310                       104
+
+// Device Aperture: PCIe
+#define NV_DEVID_PCIE                            105
+
+// Device Aperture: OWR (one wire)
+#define NV_DEVID_OWR                             106
+
+// Device Aperture: AVPUCQ
+#define NV_DEVID_AVPUCQ                          107
+
+// Device Aperture: AVPBSEA (obsolete)
+#define NV_DEVID_AVPBSEA                         108
+
+// Device Aperture: Sync NOR
+#define NV_DEVID_SNOR                            109
+
+// Device Aperture: SDMMC
+#define NV_DEVID_SDMMC                           110
+
+// Device Aperture: KFUSE
+#define NV_DEVID_KFUSE                           111
+
+// Device Aperture: CSITE
+#define NV_DEVID_CSITE                           112
+
+// Non-Aperture Interrupt: ARM Interprocessor Interrupt
+#define NV_DEVID_ARM_IPI                         113
+
+// Device Aperture: ARM Interrupts 0-31
+#define NV_DEVID_ARM_ICTLR                       114
+
+// Device Aperture: IOBIST
+#define NV_DEVID_IOBIST                          115
+
+// Device Aperture: SPEEDO
+#define NV_DEVID_SPEEDO                          116
+
+// Device Aperture: LA
+#define NV_DEVID_LA                              117
+
+// Device Aperture: VS
+#define NV_DEVID_VS                              118
+
+// Device Aperture: VCI
+#define NV_DEVID_VCI                             119
+
+// Device Aperture: APBIF
+#define NV_DEVID_APBIF                           120
+
+// Device Aperture: AHUB
+#define NV_DEVID_AHUB                            121
+
+// Device Aperture: DAM
+#define NV_DEVID_DAM                             122
+
+// ------------------------------------------------------------
+//    hw powergroups
+// ------------------------------------------------------------
+// Always On
+#define NV_POWERGROUP_AO                         0
+
+// Main
+#define NV_POWERGROUP_NPG                        1
+
+// CPU related blocks
+#define NV_POWERGROUP_CPU                        2
+
+// 3D graphics
+#define NV_POWERGROUP_TD                         3
+
+// Video encode engine blocks
+#define NV_POWERGROUP_VE                         4
+
+// PCIe
+#define NV_POWERGROUP_PCIE                       5
+
+// Video decoder
+#define NV_POWERGROUP_VDE                        6
+
+// MPEG encoder
+#define NV_POWERGROUP_MPE                        7
+
+// SW define for Power Group maximum
+#define NV_POWERGROUP_MAX                        8
+
+// non-mapped power group
+#define NV_POWERGROUP_INVALID                    0xffff
+
+// SW table for mapping power group define to register enums (NV_POWERGROUP_INVALID = no mapping)
+//  use as 'int table[NV_POWERGROUP_MAX] = { NV_POWERGROUP_ENUM_TABLE }'
+#define NV_POWERGROUP_ENUM_TABLE                 NV_POWERGROUP_INVALID, NV_POWERGROUP_INVALID, 0, 1, 2, 3, 4, 6
+
+// ------------------------------------------------------------
+//    relocation table data (stored in boot rom)
+// ------------------------------------------------------------
+// relocation table pointer stored at NV_RELOCATION_TABLE_OFFSET
+#define NV_RELOCATION_TABLE_PTR_OFFSET 64
+#define NV_RELOCATION_TABLE_SIZE  628
+#define NV_RELOCATION_TABLE_INIT \
+          0x00000001, 0x00020010, 0x00000000, 0x40000000, 0x00711010, \
+          0x00000000, 0x00000000, 0x00711010, 0x00000000, 0x00000000, \
+          0x00711010, 0x00000000, 0x00000000, 0x00711010, 0x00000000, \
+          0x00000000, 0x00711010, 0x00000000, 0x00000000, 0x00711010, \
+          0x00000000, 0x00000000, 0x00711010, 0x00000000, 0x00000000, \
+          0x00711010, 0x00000000, 0x00000000, 0x00711010, 0x00000000, \
+          0x00000000, 0x00531010, 0x00000000, 0x00000000, 0x00711010, \
+          0x00000000, 0x00000000, 0x00711010, 0x00000000, 0x00000000, \
+          0x005f1010, 0x00000000, 0x00000000, 0x00711010, 0x00000000, \
+          0x00000000, 0x00531010, 0x00000000, 0x00000000, 0x00711010, \
+          0x00000000, 0x00000000, 0x00711010, 0x00000000, 0x00000000, \
+          0x00711010, 0x00000000, 0x00000000, 0x00711010, 0x00000000, \
+          0x00000000, 0x00521010, 0x00000000, 0x00000000, 0x00041110, \
+          0x40000000, 0x00010000, 0x00041110, 0x40010000, 0x00010000, \
+          0x00041110, 0x40020000, 0x00010000, 0x00041110, 0x40030000, \
+          0x00010000, 0x00081010, 0x50000000, 0x00024000, 0x00091020, \
+          0x50040000, 0x00002000, 0x00721020, 0x50041000, 0x00001000, \
+          0x000a1020, 0x50042000, 0x00001000, 0x00681020, 0x50043000, \
+          0x00001000, 0x000f1270, 0x54040000, 0x00040000, 0x000d1140, \
+          0x54080000, 0x00040000, 0x00631140, 0x54080000, 0x00040000, \
+          0x000e1040, 0x540c0000, 0x00040000, 0x00121040, 0x54100000, \
+          0x00040000, 0x00111010, 0x54140000, 0x00040000, 0x00101230, \
+          0x54180000, 0x00040000, 0x00131310, 0x54200000, 0x00040000, \
+          0x00131310, 0x54240000, 0x00040000, 0x004d1210, 0x54280000, \
+          0x00040000, 0x004b1110, 0x542c0000, 0x00040000, 0x004c1010, \
+          0x54300000, 0x00040000, 0x00071110, 0x58000000, 0x02000000, \
+          0x00141010, 0x60000000, 0x00001000, 0x00151010, 0x60001000, \
+          0x00001000, 0x00161010, 0x60002000, 0x00001000, 0x00171010, \
+          0x60003000, 0x00001000, 0x004f1010, 0x60004000, 0x00000040, \
+          0x00551010, 0x60004040, 0x000000c0, 0x004f1110, 0x60004100, \
+          0x00000040, 0x00561010, 0x60004140, 0x00000008, 0x00561110, \
+          0x60004148, 0x00000008, 0x004f1210, 0x60004200, 0x00000040, \
+          0x004f1310, 0x60004300, 0x00000040, 0x001a1010, 0x60005000, \
+          0x00000008, 0x001a1010, 0x60005008, 0x00000008, 0x00541010, \
+          0x60005010, 0x00000040, 0x001a1010, 0x60005050, 0x00000008, \
+          0x001a1010, 0x60005058, 0x00000008, 0x001b1210, 0x60006000, \
+          0x00001000, 0x001c1010, 0x60007000, 0x0000001c, 0x001e1110, \
+          0x60008000, 0x00002000, 0x00571010, 0x60009000, 0x00000020, \
+          0x00571010, 0x60009020, 0x00000020, 0x00571010, 0x60009040, \
+          0x00000020, 0x00571010, 0x60009060, 0x00000020, 0x001f1010, \
+          0x6000a000, 0x00002000, 0x00581010, 0x6000b000, 0x00000020, \
+          0x00581010, 0x6000b020, 0x00000020, 0x00581010, 0x6000b040, \
+          0x00000020, 0x00581010, 0x6000b060, 0x00000020, 0x00581010, \
+          0x6000b080, 0x00000020, 0x00581010, 0x6000b0a0, 0x00000020, \
+          0x00581010, 0x6000b0c0, 0x00000020, 0x00581010, 0x6000b0e0, \
+          0x00000020, 0x00581010, 0x6000b100, 0x00000020, 0x00581010, \
+          0x6000b120, 0x00000020, 0x00581010, 0x6000b140, 0x00000020, \
+          0x00581010, 0x6000b160, 0x00000020, 0x00581010, 0x6000b180, \
+          0x00000020, 0x00581010, 0x6000b1a0, 0x00000020, 0x00581010, \
+          0x6000b1c0, 0x00000020, 0x00581010, 0x6000b1e0, 0x00000020, \
+          0x00201010, 0x6000c000, 0x00000400, 0x00591010, 0x6000c004, \
+          0x0000010c, 0x005b1010, 0x6000c150, 0x000000a6, 0x005c1010, \
+          0x6000c200, 0x00000004, 0x00211010, 0x6000c400, 0x00000400, \
+          0x00222010, 0x6000d000, 0x00000880, 0x00222010, 0x6000d080, \
+          0x00000880, 0x00222010, 0x6000d100, 0x00000880, 0x00222010, \
+          0x6000d180, 0x00000880, 0x00222010, 0x6000d200, 0x00000880, \
+          0x00222010, 0x6000d280, 0x00000880, 0x00222010, 0x6000d300, \
+          0x00000880, 0x00231010, 0x6000e000, 0x00001000, 0x00241010, \
+          0x6000f000, 0x00001000, 0x006b1010, 0x60010000, 0x00000100, \
+          0x002f1110, 0x60011000, 0x00001000, 0x00261260, 0x6001a000, \
+          0x00003c00, 0x00312010, 0x70000000, 0x00001000, 0x00731010, \
+          0x70001000, 0x00000100, 0x00731010, 0x70001100, 0x00000100, \
+          0x00731010, 0x70001300, 0x00000100, 0x00731010, 0x70001400, \
+          0x00000100, 0x00731010, 0x70001800, 0x00000200, 0x00741010, \
+          0x70001f00, 0x00000008, 0x00741010, 0x70001f08, 0x00000008, \
+          0x00321110, 0x70002000, 0x00000200, 0x00331010, 0x70002400, \
+          0x00000200, 0x00341110, 0x70002800, 0x00000100, 0x00341110, \
+          0x70002a00, 0x00000100, 0x00351210, 0x70006000, 0x00000040, \
+          0x00351210, 0x70006040, 0x00000040, 0x00361010, 0x70006100, \
+          0x00000100, 0x00351210, 0x70006200, 0x00000100, 0x00351210, \
+          0x70006300, 0x00000100, 0x00351210, 0x70006400, 0x00000100, \
+          0x00371210, 0x70008000, 0x00000100, 0x00381010, 0x70008500, \
+          0x00000100, 0x00391010, 0x70008a00, 0x00000200, 0x006d1010, \
+          0x70009000, 0x00001000, 0x003a1010, 0x7000a000, 0x00000100, \
+          0x003b1010, 0x7000b000, 0x00000100, 0x003c1210, 0x7000c000, \
+          0x00000100, 0x003d1010, 0x7000c100, 0x00000100, 0x00401010, \
+          0x7000c380, 0x00000080, 0x003c1210, 0x7000c400, 0x00000100, \
+          0x003c1210, 0x7000c500, 0x00000100, 0x006a1010, 0x7000c600, \
+          0x00000050, 0x00411110, 0x7000d000, 0x00000200, 0x003e1110, \
+          0x7000d400, 0x00000200, 0x003e1110, 0x7000d600, 0x00000200, \
+          0x003e1110, 0x7000d800, 0x00000200, 0x003e1110, 0x7000da00, \
+          0x00000200, 0x00421100, 0x7000e000, 0x00000100, 0x00431100, \
+          0x7000e200, 0x00000100, 0x00441200, 0x7000e400, 0x00000200, \
+          0x000b1110, 0x7000f000, 0x00000400, 0x000c1210, 0x7000f400, \
+          0x00000400, 0x00451110, 0x7000f800, 0x00000400, 0x006f1010, \
+          0x7000fc00, 0x00000400, 0x00751010, 0x70010000, 0x00002000, \
+          0x00701010, 0x70040000, 0x00040000, 0x00691050, 0x80000000, \
+          0x40000000, 0x005e1010, 0x80000000, 0x40000000, 0x00481010, \
+          0xc3000000, 0x01000000, 0x00601010, 0xc4000000, 0x00010000, \
+          0x00491510, 0xc5000000, 0x00004000, 0x00491610, 0xc5004000, \
+          0x00004000, 0x00491710, 0xc5008000, 0x00004000, 0x006e2010, \
+          0xc8000000, 0x00000200, 0x006e2010, 0xc8000200, 0x00000200, \
+          0x006e2010, 0xc8000400, 0x00000200, 0x006e2010, 0xc8000600, \
+          0x00000200, 0x00051110, 0xd0000000, 0x10000000, 0x00060010, \
+          0xe0000000, 0x08000000, 0x00060010, 0xe8000000, 0x08000000, \
+          0x00611010, 0xf000f000, 0x00001000, 0x00000000, 0x81b00108, \
+          0x81b0020e, 0x81b00306, 0x81b0040f, 0x81b0050a, 0x81b00601, \
+          0x81b00707, 0x81b00804, 0x81b0090b, 0x83100a19, 0x81b00b0d, \
+          0x81b00c00, 0x83400d16, 0x81b00e03, 0x83100f18, 0x81b01005, \
+          0x81b01109, 0x81b01202, 0x81b0130c, 0x8340141f, 0xc3401900, \
+          0xa3401901, 0xc3401902, 0xa3401903, 0x83401e04, 0x83401f05, \
+          0x83402106, 0x83402207, 0x83402308, 0x83402509, 0x8340260a, \
+          0x8340270b, 0x8340280c, 0xa2f02c04, 0xc2f02c05, 0xc2f02c06, \
+          0xa2f02c07, 0xa2f02d1c, 0xc2f02d1d, 0x8310321e, 0x8310331f, \
+          0x82f03600, 0x82f03701, 0x83103909, 0x83103a0a, 0xa3103c0b, \
+          0xc3103c0c, 0xa2f03d1b, 0xc3103d1d, 0xa2f0421a, 0xc310421c, \
+          0x83105716, 0x83105800, 0x83105901, 0x83105a02, 0x83105b03, \
+          0x83105c17, 0x83405d17, 0x83405e19, 0x82f05f19, 0x82f06112, \
+          0x82f0620b, 0x82f06309, 0x82f0630a, 0x82f0630c, 0x82f06308, \
+          0x82f06311, 0x83406410, 0x83406418, 0x83406c11, 0x83206c00, \
+          0x83206c12, 0x83306c00, 0x83306c12, 0x83106d0d, 0x83206d03, \
+          0x83206d04, 0x83306d03, 0x83306d04, 0x82f06e0d, 0x83206e02, \
+          0x83206e01, 0x83306e01, 0x83306e02, 0x82f06f03, 0x83206f06, \
+          0x83206f05, 0x83306f05, 0x83306f06, 0x83107004, 0x83207008, \
+          0x83307008, 0x83107105, 0x83207109, 0x83307109, 0x83107214, \
+          0x83207211, 0x83307211, 0x8310730e, 0x8320730a, 0x8330730a, \
+          0x8340741a, 0x8320740e, 0x8330740e, 0x8340751b, 0x8320750f, \
+          0x8330750f, 0x82f07618, 0x82f07716, 0x82f07810, 0x83507900, \
+          0x83107b0f, 0x83107c06, 0x83207c0c, 0x83307c0c, 0x83107d08, \
+          0x83207d0b, 0x83307d0b, 0x83107e07, 0x83207e07, 0x83307e07, \
+          0x83407f14, 0x83207f0d, 0x83307f0d, 0x8340801c, 0x83208010, \
+          0x83308010, 0x82f0811e, 0x83108215, 0x8310831b, 0x83408412, \
+          0x83408513, 0x8340861d, 0x82f08702, 0x83408815, 0x83408a0d, \
+          0x83408b0e, 0x83509002, 0x83509003, 0x83509004, 0x82f09217, \
+          0x82f09414, 0x82f09515, 0x83509601, 0x82f0970e, 0x82f0980f, \
+          0x82f09913, 0x82f09a1f, 0x00000000
+#endif
diff --git a/arch/arm/mach-tegra/include/avp.h b/arch/arm/mach-tegra/include/avp.h
new file mode 100644
index 000000000000..249a28cd44db
--- /dev/null
+++ b/arch/arm/mach-tegra/include/avp.h
@@ -0,0 +1,144 @@
+/*
+ * Copyright (c) 2010 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_AVP_H
+#define INCLUDED_AVP_H
+
+#include "ap15/arictlr.h"
+#include "ap15/artimer.h"
+// FIXME: get the ararmev header
+
+// 3 controllers in contiguous memory starting at INTERRUPT_BASE, each
+// controller's aperture is INTERRUPT_SIZE large
+#define INTERRUPT_BASE 0x60004000
+#define INTERRUPT_SIZE 0x100
+#define INTERRUPT_NUM_CONTROLLERS 3
+
+#define INTERRUPT_PENDING( ctlr ) \
+    (INTERRUPT_BASE + ((ctlr) * INTERRUPT_SIZE) + ICTLR_VIRQ_COP_0)
+
+#define INTERRUPT_SET( ctlr ) \
+    (INTERRUPT_BASE + ((ctlr) * INTERRUPT_SIZE) + ICTLR_COP_IER_SET_0)
+
+#define INTERRUPT_CLR( ctlr ) \
+    (INTERRUPT_BASE + ((ctlr) * INTERRUPT_SIZE) + ICTLR_COP_IER_CLR_0)
+
+#define OSC_CTRL        ( 0x60006000 + 0x50 )
+#define OSC_FREQ_DET    ( 0x60006000 + 0x58 )
+#define OSC_DET_STATUS  ( 0x60006000 + 0x5C )
+
+#define TIMER_USEC      ( 0x60005010 )
+#define TIMER_CFG       ( 0x60005014 )
+#define TIMER_0_BASE    ( 0x60005000 )
+#define TIMER_0         ( TIMER_0_BASE + TIMER_TMR_PTV_0 )
+#define TIMER_0_CLEAR   ( TIMER_0_BASE + TIMER_TMR_PCR_0 )
+#define TIMER_1_BASE    ( 0x60005008 )
+#define TIMER_1         ( TIMER_1_BASE + TIMER_TMR_PTV_0 )
+#define TIMER_1_CLEAR   ( TIMER_1_BASE + TIMER_TMR_PCR_0 )
+
+#define CLOCK_RST_LO    (0x60006004)
+#define CLOCK_CTLR_HI   (0x60006014)
+#define CLOCK_CTLR_LO   (0x60006010)
+
+#define CACHE_CTLR      (0x6000C000)
+#define CACHE_CONTROL_0         (0x0)
+
+#define PPI_INTR_ID_TIMER_0     (0)
+#define PPI_INTR_ID_TIMER_1     (1)
+#define PPI_INTR_ID_TIMER_2     (9)
+#define PPI_INTR_ID_TIMER_3     (10)
+
+/* flow controller */
+#define FLOW_CONTROLLER     (0x60007004)
+
+/* exception vectors */
+#define VECTOR_BASE             ( 0x6000F200 )
+#define VECTOR_RESET            ( VECTOR_BASE + 0 )
+#define VECTOR_UNDEF            ( VECTOR_BASE + 4 )
+#define VECTOR_SWI              ( VECTOR_BASE + 8 )
+#define VECTOR_PREFETCH_ABORT   ( VECTOR_BASE + 12 )
+#define VECTOR_DATA_ABORT       ( VECTOR_BASE + 16 )
+#define VECTOR_IRQ              ( VECTOR_BASE + 24 )
+#define VECTOR_FIQ              ( VECTOR_BASE + 28 )
+
+#define MODE_DISABLE_INTR 0xc0
+#define MODE_USR 0x10
+#define MODE_FIQ 0x11
+#define MODE_IRQ 0x12
+#define MODE_SVC 0x13
+#define MODE_ABT 0x17
+#define MODE_UND 0x1B
+#define MODE_SYS 0x1F
+
+#define AP15_CACHE_LINE_SIZE            32
+
+#define AP15_APB_L2_CACHE_BASE 0x7000e800 
+#define AP15_APB_CLK_RST_BASE  0x60006000
+#define AP15_APB_MISC_BASE     0x70000000
+
+#define AP10_APB_CLK_RST_BASE  0x60006000
+#define AP10_APB_MISC_BASE     0x70000000
+
+#define MMU_TLB_BASE              0xf000f000
+#define MMU_TLB_CACHE_WINDOW_0    0x40
+#define MMU_TLB_CACHE_OPTIONS_0   0x44
+
+#define AP15_PINMUX_CFG_CTL_0   0x70000024
+#define AP15_AVP_JTAG_ENABLE    0xC0
+
+#define PMC_SCRATCH22_REG_LP0   0x7000e4a8
+
+#define AVP_WDT_RESET   0x2F00BAD0
+
+/* Cached to uncached offset for AVP
+ *
+ * Hardware has uncached remap aperture for AVP as AVP doesn't have MMU
+ * but still has cache (named COP cache).
+ *
+ * This aperture moved between AP15 and AP20.
+ */
+#define AP15_CACHED_TO_UNCACHED_OFFSET 0x90000000
+#define AP20_CACHED_TO_UNCACHED_OFFSET 0x80000000
+
+#define APXX_EXT_MEM_START      0x00000000
+#define APXX_EXT_MEM_END        0x40000000
+
+#define APXX_MMIO_START         0x40000000
+#define APXX_MMIO_END           0xFFF00000
+
+#define TXX_EXT_MEM_START       0x80000000
+#define TXX_EXT_MEM_END         0xc0000000
+
+#define TXX_MMIO_START          0x40000000
+#define TXX_MMIO_END            0x80000000
+
+#endif
diff --git a/arch/arm/mach-tegra/include/mach/nvrm_linux.h b/arch/arm/mach-tegra/include/mach/nvrm_linux.h
new file mode 100644
index 000000000000..38d51969fa50
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/nvrm_linux.h
@@ -0,0 +1,82 @@
+/*
+ * Copyright (c) 2008-2010 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/*  This header file defines shared structures used by Linux drivers
+ *  integrating with Tegra NvRM.
+ */
+
+#ifndef INCLUDED_nvrm_linux_H
+#define INCLUDED_nvrm_linux_H
+
+/* nvcommon.h exepcts NV_DEBUG to be defined */
+#ifndef NV_DEBUG
+#ifdef DEBUG
+#define NV_DEBUG DEBUG
+#else
+#define NV_DEBUG 0
+#endif
+#endif
+
+#include <nvrm_init.h>
+#include <nvrm_gpio.h>
+
+extern NvRmDeviceHandle s_hRmGlobal;
+extern NvRmGpioHandle s_hGpioGlobal;
+
+int tegra_get_partition_info_by_name(const char *PartName,
+	NvU64 *pSectorStart, NvU64 *pSectorLength, NvU32 *pSectorSize);
+
+int tegra_get_partition_info_by_num(int PartitionNum, char **pName,
+	NvU64 *pSectorStart, NvU64 *pSectorEnd, NvU32 *pSectorSize);
+
+int tegra_was_boot_device(const char *pBootDev);
+
+NvU32 NvRmDmaUnreservedChannels(void);
+
+#ifndef CONFIG_SERIAL_TEGRA_UARTS
+#define TEGRA_SYSTEM_DMA_CH_UART 0
+#else
+#define TEGRA_SYSTEM_DMA_CH_UART (2*CONFIG_SERIAL_TEGRA_UARTS)
+#endif
+
+#ifdef CONFIG_TEGRA_SYSTEM_DMA
+#define TEGRA_SYSTEM_DMA_CH_NUM (1 + TEGRA_SYSTEM_DMA_CH_UART)
+#else
+#define TEGRA_SYSTEM_DMA_CH_NUM (0)
+#endif
+
+/* DMA channels available to system DMA driver */
+#define TEGRA_SYSTEM_DMA_CH_MIN NvRmDmaUnreservedChannels()
+#define TEGRA_SYSTEM_DMA_CH_MAX \
+	(TEGRA_SYSTEM_DMA_CH_MIN+TEGRA_SYSTEM_DMA_CH_NUM)
+
+#endif
diff --git a/arch/arm/mach-tegra/include/mach/pinmux.h b/arch/arm/mach-tegra/include/mach/pinmux.h
index 3828ec5fe048..29148a904bb1 100644
--- a/arch/arm/mach-tegra/include/mach/pinmux.h
+++ b/arch/arm/mach-tegra/include/mach/pinmux.h
@@ -256,6 +256,7 @@ void tegra_pinmux_config_tristate_table(const struct tegra_pingroup_config *conf
 					int len, tegra_tristate_t tristate);
 void tegra_pinmux_config_pullupdown_table(const struct tegra_pingroup_config *config,
 					  int len, tegra_pullupdown_t pupd);
+int tegra_pinmux_get_vddio(tegra_pingroup_t pg);
 void tegra_pinmux_set_vddio_tristate(tegra_vddio_t vddio,
 				     tegra_tristate_t tristate);
 #endif
diff --git a/arch/arm/mach-tegra/include/nvcolor.h b/arch/arm/mach-tegra/include/nvcolor.h
new file mode 100644
index 000000000000..da1218197cd3
--- /dev/null
+++ b/arch/arm/mach-tegra/include/nvcolor.h
@@ -0,0 +1,471 @@
+/*
+ * Copyright (c) 2006-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_NVCOLOR_H
+#define INCLUDED_NVCOLOR_H
+
+/*
+ * We provide a very generic, orthogonal way to specify color formats.  There
+ * are four steps in specifying a color format:
+ * 1. What is the data type of the color components?
+ * 2. How are the color components packed into words of memory?
+ * 3. How are those color components swizzled into an (x,y,z,w) color vector?
+ * 4. How is that vector interpreted as a color?
+ *
+ * These correspond to NvColorDataType, NvColorComponentPacking,
+ * NV_COLOR_SWIZZLE_*, and NvColorSpace, respectively.
+ *
+ * First, you need to understand NVIDIA's standard way of describing color
+ * units (used in several business units within NVIDIA).  Within a word, color
+ * components are ordered from most-significant bit to least-significant bit.
+ * Words are separated by underscores.  For example:
+ *
+ * A8R8B8G8 = a single 32-bit word containing 8 bits alpha, 8 bits red, 8 bits
+ * green, 8 bits blue.
+ *
+ * In little endian:  Byte      3  ||   2  ||   1  ||   0
+ *                    Bits 31                              0
+ *                          AAAAAAAARRRRRRRRGGGGGGGGBBBBBBBB
+ *
+ * In big endian:     Byte      0  ||   1  ||   2  ||   3
+ *                    Bits 31                              0
+ *                          AAAAAAAARRRRRRRRGGGGGGGGBBBBBBBB
+ *
+ * R8_G8_B8_A8 = four consecutive 8-bit words, consisting the red, green, blue,
+ * and alpha components (in that order).
+ *
+ * In little endian:  Byte      0  ||   1  ||   2  ||   3
+ *                    Bits  76543210765432107654321076543210
+ *                          RRRRRRRRGGGGGGGGBBBBBBBBAAAAAAAA
+ *
+ * In big endian:     Byte      0  ||   1  ||   2  ||   3
+ *                    Bits  76543210765432107654321076543210
+ *                          RRRRRRRRGGGGGGGGBBBBBBBBAAAAAAAA
+ *
+ * R5G6B5 = a single 16-bit word containing 5 bits red, 6 bits green, 5 bits
+ * blue.
+ *
+ * In little endian:  Byte      1  ||   0
+ *                    Bits 15              0
+ *                          RRRRRGGGGGGBBBBB
+ *
+ * In big endian:     Byte      0  ||   1
+ *                    Bits 15              0
+ *                          RRRRRGGGGGGBBBBB
+ *
+ * In cases where a word is less than 8 bits (e.g. an A1 1-bit alpha mask
+ * bitmap), pixels are ordered from LSB to MSB within a word.  That is, the LSB
+ * of the byte is the pixel at x%8 == 0, while the MSB of the byte is the pixel
+ * at x%8 == 7.
+ *
+ * Also, note equivalences such as the following.
+ *
+ * In little endian: R8_G8_B8_A8 = A8B8G8R8.
+ * In big endian:    R8_G8_B8_A8 = R8G8B8A8.
+ *
+ * Some YUV "422" formats have different formats for pixels whose X is even vs.
+ * those whose X is odd.  Every pixel contains a Y component, while (for
+ * example) only even pixels might contain a U component and only odd pixels
+ * might contain a V component.  Such formats use a double-underscore to
+ * separate the even pixels from the odd pixels.  For example, the format just
+ * described might be referred to as Y8_U8__Y8_V8.
+ *
+ * Here is how we would we go about mapping a color format (say, R5G6B5) to the
+ * NvColorFormat enums.
+ *
+ * 1. Remove the color information and rename the component R,G,B to generic
+ * names X,Y,Z.  Our NvColorComponentPacking is therefore X5Y6Z5.
+ *
+ * 2. Pick the appropriate color space.  This is plain old RGBA, so we pick
+ * NvColorSpace_LinearRGBA.
+ *
+ * 3. Determine what swizzle to use.  We need R=X, G=Y, B=Z, and A=1, so we
+ * pick the "XYZ1" swizzle.
+ *
+ * 4. Pick the data type of the color components. This is just plain integers,
+ * so NvColorDataType_Integer is our choice.
+ */
+
+/**
+ * We provide a flexible way to map the input vector (x,y,z,w) to an output
+ * vector (x',y',z',w').  Each output component can select any of the input
+ * components or the constants zero or one.  For example, the swizzle "XXX1"
+ * can be used to create a luminance pixel from the input x component, while
+ * the swizzle "ZYXW" swaps the X and Z components (converts between RGBA and
+ * BGRA).
+ */
+#define NV_COLOR_SWIZZLE_X 0
+#define NV_COLOR_SWIZZLE_Y 1
+#define NV_COLOR_SWIZZLE_Z 2
+#define NV_COLOR_SWIZZLE_W 3
+#define NV_COLOR_SWIZZLE_0 4
+#define NV_COLOR_SWIZZLE_1 5
+
+#define NV_COLOR_MAKE_SWIZZLE(x,y,z,w) \
+    ((NV_COLOR_SWIZZLE_##x) | ((NV_COLOR_SWIZZLE_##y) << 3) | \
+     ((NV_COLOR_SWIZZLE_##z) << 6) | ((NV_COLOR_SWIZZLE_##w) << 9))
+
+#define NV_COLOR_SWIZZLE_GET_X(swz) (((swz)     ) & 7)
+#define NV_COLOR_SWIZZLE_GET_Y(swz) (((swz) >> 3) & 7)
+#define NV_COLOR_SWIZZLE_GET_Z(swz) (((swz) >> 6) & 7)
+#define NV_COLOR_SWIZZLE_GET_W(swz) (((swz) >> 9) & 7)
+
+#define NV_COLOR_SWIZZLE_XYZW NV_COLOR_MAKE_SWIZZLE(X,Y,Z,W)
+#define NV_COLOR_SWIZZLE_ZYXW NV_COLOR_MAKE_SWIZZLE(Z,Y,X,W)
+#define NV_COLOR_SWIZZLE_WZYX NV_COLOR_MAKE_SWIZZLE(W,Z,Y,X)
+#define NV_COLOR_SWIZZLE_YZWX NV_COLOR_MAKE_SWIZZLE(Y,Z,W,X)
+#define NV_COLOR_SWIZZLE_XYZ1 NV_COLOR_MAKE_SWIZZLE(X,Y,Z,1)
+#define NV_COLOR_SWIZZLE_YZW1 NV_COLOR_MAKE_SWIZZLE(Y,Z,W,1)
+#define NV_COLOR_SWIZZLE_XXX1 NV_COLOR_MAKE_SWIZZLE(X,X,X,1)
+#define NV_COLOR_SWIZZLE_XZY1 NV_COLOR_MAKE_SWIZZLE(X,Z,Y,1)
+#define NV_COLOR_SWIZZLE_ZYX1 NV_COLOR_MAKE_SWIZZLE(Z,Y,X,1)
+#define NV_COLOR_SWIZZLE_WZY1 NV_COLOR_MAKE_SWIZZLE(W,Z,Y,1)
+#define NV_COLOR_SWIZZLE_X000 NV_COLOR_MAKE_SWIZZLE(X,0,0,0)
+#define NV_COLOR_SWIZZLE_0X00 NV_COLOR_MAKE_SWIZZLE(0,X,0,0)
+#define NV_COLOR_SWIZZLE_00X0 NV_COLOR_MAKE_SWIZZLE(0,0,X,0)
+#define NV_COLOR_SWIZZLE_000X NV_COLOR_MAKE_SWIZZLE(0,0,0,X)
+#define NV_COLOR_SWIZZLE_0XY0 NV_COLOR_MAKE_SWIZZLE(0,X,Y,0)
+#define NV_COLOR_SWIZZLE_XXXY NV_COLOR_MAKE_SWIZZLE(X,X,X,Y)
+#define NV_COLOR_SWIZZLE_YYYX NV_COLOR_MAKE_SWIZZLE(Y,Y,Y,X)
+
+/**
+ * This macro extracts the number of bits per pixel out of an NvColorFormat or
+ * NvColorComponentPacking.
+ */
+#define NV_COLOR_GET_BPP(fmt) (((NvU32)(fmt)) >> 24)
+
+/**
+ * This macro encodes the number of bits per pixel into an
+ * NvColorComponentPacking enum.
+ */
+#define NV_COLOR_SET_BPP(bpp) ((bpp) << 24)
+
+/**
+ * NvColorComponentPacking enumerates the possible ways to pack color
+ * components into words in memory.
+ */
+typedef enum
+{
+    NvColorComponentPacking_X1              = 0x01 | NV_COLOR_SET_BPP(1),
+    NvColorComponentPacking_X2              = 0x02 | NV_COLOR_SET_BPP(2),
+    NvColorComponentPacking_X4              = 0x03 | NV_COLOR_SET_BPP(4),
+    NvColorComponentPacking_X8              = 0x04 | NV_COLOR_SET_BPP(8),
+    NvColorComponentPacking_X3Y3Z2          = 0x05 | NV_COLOR_SET_BPP(8),
+    NvColorComponentPacking_Y4X4            = 0x06 | NV_COLOR_SET_BPP(8),
+    NvColorComponentPacking_X16             = 0x07 | NV_COLOR_SET_BPP(16),
+    NvColorComponentPacking_X4Y4Z4W4        = 0x08 | NV_COLOR_SET_BPP(16),
+    NvColorComponentPacking_X1Y5Z5W5        = 0x09 | NV_COLOR_SET_BPP(16),
+    NvColorComponentPacking_X5Y6Z5          = 0x0A | NV_COLOR_SET_BPP(16),
+    NvColorComponentPacking_X8_Y8           = 0x0B | NV_COLOR_SET_BPP(16),
+    NvColorComponentPacking_X8_Y8__X8_Z8    = 0x0C | NV_COLOR_SET_BPP(16),
+    NvColorComponentPacking_Y8_X8__Z8_X8    = 0x0D | NV_COLOR_SET_BPP(16),
+    NvColorComponentPacking_Y6X10           = 0x0E | NV_COLOR_SET_BPP(16),
+    NvColorComponentPacking_Y4X12           = 0x0F | NV_COLOR_SET_BPP(16),
+    NvColorComponentPacking_Y2X14           = 0x10 | NV_COLOR_SET_BPP(16),
+    NvColorComponentPacking_X5Y5Z5W1        = 0x11 | NV_COLOR_SET_BPP(16),
+    NvColorComponentPacking_X8_Y8_Z8        = 0x12 | NV_COLOR_SET_BPP(24),
+    NvColorComponentPacking_X32             = 0x13 | NV_COLOR_SET_BPP(32),
+    NvColorComponentPacking_X8Y8Z8W8        = 0x14 | NV_COLOR_SET_BPP(32),
+    NvColorComponentPacking_X11Y11Z10       = 0x15 | NV_COLOR_SET_BPP(32),
+    NvColorComponentPacking_X16Y16          = 0x16 | NV_COLOR_SET_BPP(32),
+    NvColorComponentPacking_X16_Y16         = 0x17 | NV_COLOR_SET_BPP(32),
+    NvColorComponentPacking_X16_Y16_Z16     = 0x18 | NV_COLOR_SET_BPP(48),
+    NvColorComponentPacking_X16_Y16_Z16_W16 = 0x19 | NV_COLOR_SET_BPP(64),
+    NvColorComponentPacking_X16Y16Z16W16    = 0x20 | NV_COLOR_SET_BPP(64),
+    NvColorComponentPacking_X32_Y32         = 0x21 | NV_COLOR_SET_BPP(64),
+    NvColorComponentPacking_X32_Y32_Z32     = 0x22 | NV_COLOR_SET_BPP(96),
+    NvColorComponentPacking_X32_Y32_Z32_W32 = 0x23 | NV_COLOR_SET_BPP(128),
+    NvColorComponentPacking_X32Y32Z32W32    = 0x24 | NV_COLOR_SET_BPP(128),
+
+    NvColorComponentPacking_Force32 = 0x7FFFFFFF
+} NvColorComponentPacking;
+
+/**
+ * NvColorDataType defines the data type of color components.
+ *
+ * The default datatype of color components is 'Integer' which should be used
+ * when the color value is to be intepreted as an integer value ranging from 0
+ * to the maximum value representable by the width of the components (as
+ * specified by the packing of the component). Use 'Integer' also when the
+ * interpretation of color value bits is not known, does not matter or is
+ * context dependent.
+ *
+ * A data type of 'Float' indicates that float values are stored in the
+ * components of the color. The combination of data type 'Float' and the
+ * bit width of the component packing defines the final data format of the
+ * individual component.
+ *
+ * The list below defines the accepted combinations, when adding new
+ * float formats please add an entry into this list.
+ *
+ * - DataType = Float, Component bit width = 32:
+ *      A IEEE 754 single precision float (binary32) with 1 sign bit,
+ *      8 exponent bits and 23 mantissa bits.
+ *
+ * - DataType = Float, Component bit width = 16:
+ *      A IEEE 754 half precision float (binary16) with 1 sign bit,
+ *      5 exponent bits and 10 mantissa bits.
+ *
+ * - DataType = Float, Component bit width = 10:
+ *      An unsigned nvfloat with 5 exponent bits and 5 mantissa bits.
+ *
+ * - DataType = Float, Component bit width = 11:
+ *      An unsigned nvfloat with 5 exponent bits and 6 mantissa bits.
+ *
+ */
+typedef enum
+{
+    NvColorDataType_Integer     = 0x0,
+    NvColorDataType_Float       = 0x1,
+
+    NvColorDataType_Force32 = 0x7FFFFFFF    
+} NvColorDataType;
+
+/**
+ * NvColorSpace defines a number of ways of interpreting an (x,y,z,w) tuple as
+ * a color.  The most common and basic is linear RGBA, which simply maps X->R,
+ * Y->G, Z->B, and W->A, but various other color spaces also exist.
+ *
+ * Some future candidates for expansion are premultiplied alpha formats and
+ * Z/stencil formats.  They have been omitted for now until there is a need.
+ */
+typedef enum
+{
+    /** Linear RGBA color space. */
+    NvColorSpace_LinearRGBA = 1,
+
+    /** sRGB color space with linear alpha. */
+    NvColorSpace_sRGB,
+
+    /** Paletted/color index color space. (data is meaningless w/o the palette)
+     */
+    NvColorSpace_ColorIndex,
+
+    /** YCbCr ITU-R BT.601 color space. */
+    NvColorSpace_YCbCr601,
+
+    /** YCbCr ITU-R BT.601 color space with range reduced YCbCr for VC1 decoded
+     *  surfaces. If picture layer of VC1 bit stream has RANGEREDFRM bit set,
+     *  decoded YUV data has to be scaled up (range expanded). 
+     * For this type of surface, clients should range expand Y,Cb,Cr as follows:
+     * Y  = clip( (( Y-128)*2) + 128 ); 
+     * Cb = clip( ((Cb-128)*2) + 128 ); 
+     * Cr = clip( ((Cr-128)*2) + 128 ); 
+     */
+    NvColorSpace_YCbCr601_RR,
+
+    /** YCbCr ITU-R BT.709 color space. */
+    NvColorSpace_YCbCr709,
+
+    /**
+     * Bayer format with the X component mapped to samples as follows.
+     *   span 1: R G R G R G R G
+     *   span 2: G B G B G B G B
+     * (Y,Z,W are discarded.)
+     */
+    NvColorSpace_BayerRGGB,
+
+    /**
+     * Bayer format with the X component mapped to samples as follows.
+     *   span 1: B G B G B G B G
+     *   span 2: G R G R G R G R
+     * (Y,Z,W are discarded.)
+     */
+    NvColorSpace_BayerBGGR,
+
+    /**
+     * Bayer format with the X component mapped to samples as follows.
+     *   span 1: G R G R G R G R
+     *   span 2: B G B G B G B G
+     * (Y,Z,W are discarded.)
+     */
+    NvColorSpace_BayerGRBG,
+
+    /**
+     * Bayer format with the X component mapped to samples as follows.
+     *   span 1: G B G B G B G B
+     *   span 2: R G R G R G R G
+     * (Y,Z,W are discarded.)
+     */
+    NvColorSpace_BayerGBRG,
+
+    /**
+     * Noncolor data (for example depth, stencil, coverage). 
+     */
+    NvColorSpace_NonColor,
+
+    NvColorSpace_Force32 = 0x7FFFFFFF
+} NvColorSpace;
+
+/**
+ * NV_COLOR_MAKE_FORMAT_XXX macros build NvColor values out of the
+ * constituent parts.
+ *
+ * NV_COLOR_MAKE_FORMAT_GENERIC is the generic form that accepts
+ * the NvColorDataType of the format as the fourth parameter.
+ *
+ * NV_COLOR_MAKE_FORMAT is used to build DataType = Integer formats.
+ * This special case macro exists because integer formats are the
+ * overwhelming majority and for retaining backwards compatibility with
+ * code written before addition of NvColor data types.
+ */
+
+#define NV_COLOR_MAKE_FORMAT_GENERIC(ColorSpace, Swizzle, ComponentPacking, DataType) \
+    (((NvColorSpace_##ColorSpace) << 20) | \
+     ((NV_COLOR_SWIZZLE_##Swizzle) << 8) | \
+     ((NvColorDataType_##DataType) << 6) |  \
+     (NvColorComponentPacking_##ComponentPacking))
+
+#define NV_COLOR_MAKE_FORMAT(ColorSpace, Swizzle, ComponentPacking) \
+    NV_COLOR_MAKE_FORMAT_GENERIC(ColorSpace, Swizzle, ComponentPacking, Integer)
+
+#define NV_COLOR_GET_COLOR_SPACE(fmt) ((NvU32)(((fmt) >> 20) & 0xF))
+#define NV_COLOR_GET_SWIZZLE(fmt) ((NvU32)(((fmt) >> 8) & 0xFFF))
+#define NV_COLOR_GET_COMPONENT_PACKING(fmt) ((NvU32)((fmt) & 0xFF00003F))
+#define NV_COLOR_GET_DATA_TYPE(fmt) ((NvU32)(((fmt) >> 6) & 0x3))
+
+/**
+ * Each value of NvColorFormat represents a way of laying out pixels in memory.
+ * Some of the most common color formats are listed here, but other formats can
+ * be constructed freely using NV_COLOR_MAKE_FORMAT, so you should generally
+ * use NV_COLOR_GET_* to extract out the constituent parts of the color format
+ * if if you want to provide fully general color format support.  (There is no
+ * requirement, of course, that any particular API must support all conceivable
+ * color formats.)
+ */
+typedef enum
+{
+    /**
+     * In some cases we don't know or don't care about the color format of a
+     * block of data.  This value can be used as a placeholder.  It is
+     * guaranteed that this value (zero) will never collide with any real color
+     * format, based on the way that we construct color format enums.
+     */
+    NvColorFormat_Unspecified = 0,
+
+    // RGBA color formats
+    NvColorFormat_R3G3B2   = NV_COLOR_MAKE_FORMAT(LinearRGBA, XYZ1, X3Y3Z2),
+    NvColorFormat_A4R4G4B4 = NV_COLOR_MAKE_FORMAT(LinearRGBA, YZWX, X4Y4Z4W4),
+    NvColorFormat_R4G4B4A4 = NV_COLOR_MAKE_FORMAT(LinearRGBA, XYZW, X4Y4Z4W4),
+    NvColorFormat_A1R5G5B5 = NV_COLOR_MAKE_FORMAT(LinearRGBA, YZWX, X1Y5Z5W5),
+    NvColorFormat_R5G5B5A1 = NV_COLOR_MAKE_FORMAT(LinearRGBA, XYZW, X5Y5Z5W1),
+    NvColorFormat_R5G6B5   = NV_COLOR_MAKE_FORMAT(LinearRGBA, XYZ1, X5Y6Z5),
+    NvColorFormat_R8_G8_B8 = NV_COLOR_MAKE_FORMAT(LinearRGBA, XYZ1, X8_Y8_Z8),
+    NvColorFormat_B8_G8_R8 = NV_COLOR_MAKE_FORMAT(LinearRGBA, ZYX1, X8_Y8_Z8),
+    NvColorFormat_A8R8G8B8 = NV_COLOR_MAKE_FORMAT(LinearRGBA, YZWX, X8Y8Z8W8),
+    NvColorFormat_A8B8G8R8 = NV_COLOR_MAKE_FORMAT(LinearRGBA, WZYX, X8Y8Z8W8),
+    NvColorFormat_R8G8B8A8 = NV_COLOR_MAKE_FORMAT(LinearRGBA, XYZW, X8Y8Z8W8),
+    NvColorFormat_B8G8R8A8 = NV_COLOR_MAKE_FORMAT(LinearRGBA, ZYXW, X8Y8Z8W8),
+    NvColorFormat_X8R8G8B8 = NV_COLOR_MAKE_FORMAT(LinearRGBA, YZW1, X8Y8Z8W8),
+    NvColorFormat_R8G8B8X8 = NV_COLOR_MAKE_FORMAT(LinearRGBA, XYZ1, X8Y8Z8W8),
+    NvColorFormat_X8B8G8R8 = NV_COLOR_MAKE_FORMAT(LinearRGBA, WZY1, X8Y8Z8W8),
+    NvColorFormat_B8G8R8X8 = NV_COLOR_MAKE_FORMAT(LinearRGBA, ZYX1, X8Y8Z8W8),
+    
+    NvColorFormat_Float_B10G11R11     = NV_COLOR_MAKE_FORMAT_GENERIC(LinearRGBA, ZYX1, X11Y11Z10, Float),
+    NvColorFormat_Float_A16B16G16R16  = NV_COLOR_MAKE_FORMAT_GENERIC(LinearRGBA, WZYX, X16Y16Z16W16, Float),
+    NvColorFormat_Float_X16B16G16R16  = NV_COLOR_MAKE_FORMAT_GENERIC(LinearRGBA, WZY1, X16Y16Z16W16, Float),   
+    
+    // Luminance color formats
+    NvColorFormat_L1  = NV_COLOR_MAKE_FORMAT(LinearRGBA, XXX1, X1),
+    NvColorFormat_L2  = NV_COLOR_MAKE_FORMAT(LinearRGBA, XXX1, X2),
+    NvColorFormat_L4  = NV_COLOR_MAKE_FORMAT(LinearRGBA, XXX1, X4),
+    NvColorFormat_L8  = NV_COLOR_MAKE_FORMAT(LinearRGBA, XXX1, X8),
+    NvColorFormat_L16 = NV_COLOR_MAKE_FORMAT(LinearRGBA, XXX1, X16),
+    NvColorFormat_L32 = NV_COLOR_MAKE_FORMAT(LinearRGBA, XXX1, X32),
+    
+    NvColorFormat_Float_L16     = NV_COLOR_MAKE_FORMAT_GENERIC(LinearRGBA, XXX1, X16, Float),
+    NvColorFormat_Float_A16L16  = NV_COLOR_MAKE_FORMAT_GENERIC(LinearRGBA, YYYX, X16Y16, Float),
+
+    // Alpha color formats
+    NvColorFormat_A1  = NV_COLOR_MAKE_FORMAT(LinearRGBA, 000X, X1),
+    NvColorFormat_A2  = NV_COLOR_MAKE_FORMAT(LinearRGBA, 000X, X2),
+    NvColorFormat_A4  = NV_COLOR_MAKE_FORMAT(LinearRGBA, 000X, X4),
+    NvColorFormat_A8  = NV_COLOR_MAKE_FORMAT(LinearRGBA, 000X, X8),
+    NvColorFormat_A16 = NV_COLOR_MAKE_FORMAT(LinearRGBA, 000X, X16),
+    NvColorFormat_A32 = NV_COLOR_MAKE_FORMAT(LinearRGBA, 000X, X32),
+    
+    NvColorFormat_Float_A16 = NV_COLOR_MAKE_FORMAT_GENERIC(LinearRGBA, 000X, X16, Float),
+
+    // Color index formats
+    NvColorFormat_I1 = NV_COLOR_MAKE_FORMAT(ColorIndex, X000, X1),
+    NvColorFormat_I2 = NV_COLOR_MAKE_FORMAT(ColorIndex, X000, X2),
+    NvColorFormat_I4 = NV_COLOR_MAKE_FORMAT(ColorIndex, X000, X4),
+    NvColorFormat_I8 = NV_COLOR_MAKE_FORMAT(ColorIndex, X000, X8),
+
+    // YUV interleaved color formats
+    NvColorFormat_Y8_U8_V8 = NV_COLOR_MAKE_FORMAT(YCbCr601, XYZ1, X8_Y8_Z8),
+    NvColorFormat_UYVY     = NV_COLOR_MAKE_FORMAT(YCbCr601, XYZ1, Y8_X8__Z8_X8),
+    NvColorFormat_VYUY     = NV_COLOR_MAKE_FORMAT(YCbCr601, XZY1, Y8_X8__Z8_X8),
+    NvColorFormat_YUYV     = NV_COLOR_MAKE_FORMAT(YCbCr601, XYZ1, X8_Y8__X8_Z8),
+    NvColorFormat_YVYU     = NV_COLOR_MAKE_FORMAT(YCbCr601, XZY1, X8_Y8__X8_Z8),
+
+    // YUV planar color formats
+    NvColorFormat_Y8       = NV_COLOR_MAKE_FORMAT(YCbCr601, X000, X8),
+    NvColorFormat_U8       = NV_COLOR_MAKE_FORMAT(YCbCr601, 0X00, X8),
+    NvColorFormat_V8       = NV_COLOR_MAKE_FORMAT(YCbCr601, 00X0, X8),
+    NvColorFormat_U8_V8    = NV_COLOR_MAKE_FORMAT(YCbCr601, 0XY0, X8_Y8),
+
+    // Range Reduced YUV planar color formats
+    NvColorFormat_Y8_RR    = NV_COLOR_MAKE_FORMAT(YCbCr601_RR, X000, X8),
+    NvColorFormat_U8_RR    = NV_COLOR_MAKE_FORMAT(YCbCr601_RR, 0X00, X8),
+    NvColorFormat_V8_RR    = NV_COLOR_MAKE_FORMAT(YCbCr601_RR, 00X0, X8),
+    NvColorFormat_U8_V8_RR = NV_COLOR_MAKE_FORMAT(YCbCr601_RR, 0XY0, X8_Y8),
+
+    // Bayer color formats
+    NvColorFormat_Bayer8RGGB    = NV_COLOR_MAKE_FORMAT(BayerRGGB, X000, X8),
+    NvColorFormat_Bayer8BGGR    = NV_COLOR_MAKE_FORMAT(BayerBGGR, X000, X8),
+    NvColorFormat_Bayer8GRBG    = NV_COLOR_MAKE_FORMAT(BayerGRBG, X000, X8),
+    NvColorFormat_Bayer8GBRG    = NV_COLOR_MAKE_FORMAT(BayerGBRG, X000, X8),
+    NvColorFormat_X6Bayer10RGGB = NV_COLOR_MAKE_FORMAT(BayerRGGB, X000, Y6X10),
+    NvColorFormat_X6Bayer10BGGR = NV_COLOR_MAKE_FORMAT(BayerBGGR, X000, Y6X10),
+    NvColorFormat_X6Bayer10GRBG = NV_COLOR_MAKE_FORMAT(BayerGRBG, X000, Y6X10),
+    NvColorFormat_X6Bayer10GBRG = NV_COLOR_MAKE_FORMAT(BayerGBRG, X000, Y6X10),
+    NvColorFormat_X4Bayer12RGGB = NV_COLOR_MAKE_FORMAT(BayerRGGB, X000, Y4X12),
+    NvColorFormat_X4Bayer12BGGR = NV_COLOR_MAKE_FORMAT(BayerBGGR, X000, Y4X12),
+    NvColorFormat_X4Bayer12GRBG = NV_COLOR_MAKE_FORMAT(BayerGRBG, X000, Y4X12),
+    NvColorFormat_X4Bayer12GBRG = NV_COLOR_MAKE_FORMAT(BayerGBRG, X000, Y4X12),
+    NvColorFormat_X2Bayer14RGGB = NV_COLOR_MAKE_FORMAT(BayerRGGB, X000, Y2X14),
+    NvColorFormat_X2Bayer14BGGR = NV_COLOR_MAKE_FORMAT(BayerBGGR, X000, Y2X14),
+    NvColorFormat_X2Bayer14GRBG = NV_COLOR_MAKE_FORMAT(BayerGRBG, X000, Y2X14),
+    NvColorFormat_X2Bayer14GBRG = NV_COLOR_MAKE_FORMAT(BayerGBRG, X000, Y2X14),
+    NvColorFormat_Bayer16RGGB   = NV_COLOR_MAKE_FORMAT(BayerRGGB, X000, X16),
+    NvColorFormat_Bayer16BGGR   = NV_COLOR_MAKE_FORMAT(BayerBGGR, X000, X16),
+    NvColorFormat_Bayer16GRBG   = NV_COLOR_MAKE_FORMAT(BayerGRBG, X000, X16),
+    NvColorFormat_Bayer16GBRG   = NV_COLOR_MAKE_FORMAT(BayerGBRG, X000, X16),
+    
+    // Non color formats
+    NvColorFormat_X4C4          = NV_COLOR_MAKE_FORMAT(NonColor, X000, Y4X4),   // VCAA
+    
+    NvColorFormat_Force32 = 0x7FFFFFFF
+} NvColorFormat;
+
+#endif // INCLUDED_NVCOLOR_H
diff --git a/arch/arm/mach-tegra/include/nvodm_gpio_ext.h b/arch/arm/mach-tegra/include/nvodm_gpio_ext.h
new file mode 100644
index 000000000000..6004963b8b6d
--- /dev/null
+++ b/arch/arm/mach-tegra/include/nvodm_gpio_ext.h
@@ -0,0 +1,155 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/**
+ * @file
+ * <b>NVIDIA Tegra ODM Kit:
+ *         External GPIO Interface</b>
+ *
+ * @b Description: Defines the ODM adaptation interface for GPIO
+ *    pins that are sourced from off-chip peripherals.
+ */
+
+#ifndef INCLUDED_NVODM_GPIO_EXT_H
+#define INCLUDED_NVODM_GPIO_EXT_H
+
+#include "nvcommon.h"
+#include "nvodm_services.h"
+
+/**
+ * @defgroup nvodm_gpio_ext External GPIO Interface
+ *
+ * Your clients do not use the API functions defined here. Instead, they
+ * make use of the ::NvOdmExternalGpioPort enumeration, which defines 
+ * logical GPIO ports that may be included in the Peripheral DB entries.
+ * The ODM developer is responsible to write the external GPIO handler in
+ * your ODM Adaptation implementation.
+ * 
+ * This feature makes it possible to treat GPIOs sourced from an external
+ * peripheral as if they came from the Tegra application processor itself
+ * (thus, allowing for the use of the NvOdmGpio* functions). This makes
+ * it possible for some adaptation client implementations to remain
+ * unchanged if the pin gets moved from an external to an internal device.
+ *
+ * For instance, the PMU sources a GPIO pin for the backlight, but the
+ * display adaptation just requests the GPIO for this function from the
+ * Peripheral DB. The PMU adaptation implements the actual handling of
+ * the external GPIO. As an alternative, the backlight could be switched
+ * on or off via a GPIO pin from the chip. In that case, the peripheral
+ * DB will get updated, but the display adaptation can remain unchanged,
+ * which is the advantage of this feature.
+ *
+ * @ingroup nvodm_adaptation
+ * @{
+ */
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+
+/** External GPIO device context. */
+typedef struct GpioExtDeviceRec* NvOdmGpioExtHandle;
+
+/**
+ * @brief Defines the external GPIO ports.  These definitions 
+ *        are generic placeholders, as they map to off-chip
+ *        GPIOs as defined by the ODM. The ODM is
+ *        responsible for documenting and using these
+ *        pre-defined ports consistently between their
+ *        adaptation client and their implementation of the
+ *        Peripheral Discovery DB entries.
+ */
+typedef enum {
+    NVODM_GPIO_EXT_PORT_0 = 0xD0,
+    NVODM_GPIO_EXT_PORT_1,
+    NVODM_GPIO_EXT_PORT_2,
+    NVODM_GPIO_EXT_PORT_3,
+    NVODM_GPIO_EXT_PORT_4,
+    NVODM_GPIO_EXT_PORT_5,
+    NVODM_GPIO_EXT_PORT_6,
+    NVODM_GPIO_EXT_PORT_7,
+    NVODM_GPIO_EXT_PORT_8,
+    NVODM_GPIO_EXT_PORT_9,
+    NVODM_GPIO_EXT_PORT_A,
+    NVODM_GPIO_EXT_PORT_B,
+    NVODM_GPIO_EXT_PORT_C,
+    NVODM_GPIO_EXT_PORT_D,
+    NVODM_GPIO_EXT_PORT_E,
+    NVODM_GPIO_EXT_PORT_F,
+} NvOdmExternalGpioPort;
+
+/**
+ * This is an ODM-specific adaptation that writes the output 
+ * state of external (off-chip) GPIO pins for the specified 
+ * port. This function is not called directly by the client 
+ * that uses the external GPIOs, but rather called indirectly 
+ * via NvOdmGpioSetState().
+ *
+ * @sa NvOdmGpioOpen(), NvOdmExternalGpioReadPins()
+ *
+ * @param Port The specified external GPIO port.
+ * @param Pin The specified GPIO pin.
+ * @param PinValue The pin state to set. 0 means drive low, 1 means drive high.
+ */
+void
+NvOdmExternalGpioWritePins(
+    NvU32 Port,
+    NvU32 Pin,
+    NvU32 PinValue);
+
+/**
+ * This is an ODM-specific adaptation that reads the output 
+ * state of external (off-chip) GPIO pins for the specified 
+ * port. This function is not called directly by the client 
+ * that uses the external GPIOs, but rather called indirectly 
+ * via NvOdmGpioGetState(). 
+ *
+ * @sa NvOdmGpioOpen(), NvOdmExternalGpioWritePins()
+ *  
+ * @param Port The specified external GPIO port.
+ * @param Pin The specified GPIO pin. 
+ *  
+ * @return The current state of the specified port+pin.
+ */
+NvU32
+NvOdmExternalGpioReadPins(
+    NvU32 Port,
+    NvU32 Pin);
+
+#if defined(__cplusplus)
+}
+#endif
+
+/** @} */
+#endif  // INCLUDED_NVODM_GPIO_EXT_H
diff --git a/arch/arm/mach-tegra/include/nvodm_kbc.h b/arch/arm/mach-tegra/include/nvodm_kbc.h
new file mode 100644
index 000000000000..db8da306a3ed
--- /dev/null
+++ b/arch/arm/mach-tegra/include/nvodm_kbc.h
@@ -0,0 +1,93 @@
+/*
+ * Copyright (c) 2006-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/** 
+ * @file
+ * <b>NVIDIA Tegra ODM Kit:
+ *         KBC Adaptation Interface</b>
+ *
+ * @b Description: Defines the ODM adaptation interface for KBC keypad.
+ * 
+ */
+
+#ifndef INCLUDED_NVODM_KBC_H
+#define INCLUDED_NVODM_KBC_H
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+#include "nvodm_services.h"
+
+/**
+ * @defgroup nvodm_kbc Keyboard Controller Adaptation Interface
+ * This is the keyboard controller (KBC) ODM adaptation interface.
+ * See also the \link nvodm_query_kbc ODM Query KBC Interface\endlink.
+ * @ingroup nvodm_adaptation
+ * @{
+ */
+/**
+ * This API takes the keys that have been pressed as input and filters out the
+ * the keys that may have been caused due to ghosting effect and key roll-over.
+ *
+ * @note The row and column numbers of the keys that have been left after the 
+ * filtering are stored in the \a pRows and \a pCols arrays. The extra keys must be 
+ * deleted from the array.
+ *
+ * @param pRows A pointer to the array of the row numbers of the keys that have 
+ * been detected. This array contains \a NumOfKeysPressed elements.
+ *
+ * @param pCols A pointer to the array of the column numbers of the keys that have 
+ * been detected. This array contains \a NumOfKeysPressed elements. 
+ * 
+ * @param NumOfKeysPressed The number of key presses that have been detected by 
+ * the driver.
+ *
+ * @return The number of keys pressed after the filter has been applied.
+ *
+*/
+NvU32
+NvOdmKbcFilterKeys(
+    NvU32 *pRows,
+    NvU32 *pCols,
+    NvU32 NumOfKeysPressed);
+
+
+#if defined(__cplusplus)
+    }
+#endif
+    
+/** @} */
+    
+#endif // INCLUDED_NVODM_KBC_H
+
diff --git a/arch/arm/mach-tegra/include/nvodm_kbc_keymapping.h b/arch/arm/mach-tegra/include/nvodm_kbc_keymapping.h
new file mode 100644
index 000000000000..1cc64fd0b4d6
--- /dev/null
+++ b/arch/arm/mach-tegra/include/nvodm_kbc_keymapping.h
@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2006-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/** 
+ * @file
+ * <b>NVIDIA Tegra ODM Kit:
+ *         Keyboard Controller virtula key mapping</b>
+ *
+ * @b Description: Defines the ODM keyboard mapping to the platform 
+ *                  specific.
+ */
+
+#ifndef INCLUDED_NVODM_KBC_KEYMAPPING_H
+#define INCLUDED_NVODM_KBC_KEYMAPPING_H
+
+#include "nvcommon.h"
+
+struct NvOdmKeyVirtTableDetail
+{   
+    NvU32 StartScanCode;
+    NvU32 EndScanCode;
+    NvU32 *pVirtualKeyTable;
+};
+
+/**
+ * Get the virtual key table list with start and end scan code address.
+ * @param pVirtKeyTableList Pointer to the structure of the virtual key table 
+ * list.
+ * @retval Return the Number of entry on the list.
+ * 
+ */
+NvU32 
+NvOdmKbcKeyMappingGetVirtualKeyMappingList(
+    const struct NvOdmKeyVirtTableDetail ***pVirtKeyTableList);
+
+
+/** @} */
+#endif // INCLUDED_NVODM_KBC_KEYMAPPING_H
+
diff --git a/arch/arm/mach-tegra/include/nvodm_keylist_reserved.h b/arch/arm/mach-tegra/include/nvodm_keylist_reserved.h
new file mode 100644
index 000000000000..036eb390bef6
--- /dev/null
+++ b/arch/arm/mach-tegra/include/nvodm_keylist_reserved.h
@@ -0,0 +1,80 @@
+/*
+ * Copyright (c) 2008-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/**
+ * @file
+ * <b>NVIDIA Tegra ODM Kit:
+ *         Reserved Key ID Definition</b>
+ *
+ * @b Description: Defines the reserved key IDs for the default keys provided
+ *                 by the ODM key/value list service.
+ */
+
+#ifndef INCLUDED_NVODM_KEYLIST_RESERVED_H
+#define INCLUDED_NVODM_KEYLIST_RESERVED_H
+
+/**
+ * @addtogroup nvodm_services
+ * @{
+ */
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+/**
+ * Defines the list of reserved key IDs for the ODM key/value list service.
+ * These keys may be read by calling NvOdmServicesGetKeyValue(), but they
+ * may not be modified.
+ */
+enum 
+{
+    /// Specifies the starting range of key IDs reserved for use by NVIDIA.
+    NvOdmKeyListId_ReservedAreaStart = 0x6fff0000UL,
+
+    /** Returns the value stored in the CustomerOption field of the BCT,
+     *  which was specified when the device was flashed. If no value was
+     *  specified when flashing, a default value of 0 will be returned. */
+    NvOdmKeyListId_ReservedBctCustomerOption = NvOdmKeyListId_ReservedAreaStart,
+
+    /// Specifes the last ID of the reserved key area.
+    NvOdmKeyListId_ReservedAreaEnd = 0x6ffffffeUL
+
+};
+
+#if defined(__cplusplus)
+}
+#endif
+
+/** @} */
+#endif
diff --git a/arch/arm/mach-tegra/include/nvodm_modules.h b/arch/arm/mach-tegra/include/nvodm_modules.h
new file mode 100644
index 000000000000..cd107c8214ef
--- /dev/null
+++ b/arch/arm/mach-tegra/include/nvodm_modules.h
@@ -0,0 +1,116 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/**
+ * @file
+ * <b>NVIDIA Tegra ODM Kit:
+ *         I/O Module Definitions</b>
+ *
+ * @b Description: Defines all of the I/O module types (buses, I/Os, etc.)
+ *                 that may exist on an application processor.
+ */
+
+#ifndef INCLUDED_NVODM_MODULES_H
+#define INCLUDED_NVODM_MODULES_H
+
+/**
+ * @addtogroup nvodm_services
+ * @{
+ */
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+/**
+ * Defines I/O module types.
+ * Application processors provide a multitude of interfaces for connecting
+ * to external peripheral devices. These take the forms of individual pins
+ * (such as GPIOs), buses (such as USB), and power rails. Each interface
+ * may have zero, one, or multiple instantiations on the application processor;
+ * see the technical notes to determine the availability of interconnects for
+ * your platform.
+ */
+typedef enum
+{
+    NvOdmIoModule_Ata,
+    NvOdmIoModule_Crt,
+    NvOdmIoModule_Csi,
+    NvOdmIoModule_Dap,
+    NvOdmIoModule_Display,
+    NvOdmIoModule_Dsi,
+    NvOdmIoModule_Gpio,
+    NvOdmIoModule_Hdcp,
+    NvOdmIoModule_Hdmi,
+    NvOdmIoModule_Hsi,
+    NvOdmIoModule_Hsmmc,
+    NvOdmIoModule_I2s,
+    NvOdmIoModule_I2c,
+    NvOdmIoModule_I2c_Pmu,
+    NvOdmIoModule_Kbd,
+    NvOdmIoModule_Mio,
+    NvOdmIoModule_Nand,
+    NvOdmIoModule_Pwm,
+    NvOdmIoModule_Sdio,
+    NvOdmIoModule_Sflash,
+    NvOdmIoModule_Slink,
+    NvOdmIoModule_Spdif,
+    NvOdmIoModule_Spi,
+    NvOdmIoModule_Twc,
+    NvOdmIoModule_Tvo,
+    NvOdmIoModule_Uart,
+    NvOdmIoModule_Usb,
+    NvOdmIoModule_Vdd,
+    NvOdmIoModule_VideoInput,
+    NvOdmIoModule_Xio,
+    NvOdmIoModule_ExternalClock,
+    NvOdmIoModule_Ulpi,
+    NvOdmIoModule_OneWire,
+    NvOdmIoModule_SyncNor,
+    NvOdmIoModule_PciExpress,
+    NvOdmIoModule_Trace,
+    NvOdmIoModule_Tsense,
+    NvOdmIoModule_BacklightPwm,
+
+    NvOdmIoModule_Num,
+    NvOdmIoModule_Force32 = 0x7fffffffUL
+} NvOdmIoModule;
+
+
+#if defined(__cplusplus)
+}
+#endif
+
+/** @} */
+
+#endif  // INCLUDED_NVODM_MODULES_H
diff --git a/arch/arm/mach-tegra/include/nvodm_pmu.h b/arch/arm/mach-tegra/include/nvodm_pmu.h
new file mode 100644
index 000000000000..2b768edbe5b4
--- /dev/null
+++ b/arch/arm/mach-tegra/include/nvodm_pmu.h
@@ -0,0 +1,468 @@
+/*
+ * Copyright (c) 2006-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/** 
+ * @file
+ * <b>NVIDIA Tegra ODM Kit:
+ *         Power Management Unit Interface</b>
+ *
+ * @b Description: Defines the ODM interface for NVIDIA PMU devices.
+ * 
+ */
+
+#ifndef INCLUDED_NVODM_PMU_H
+#define INCLUDED_NVODM_PMU_H
+
+#include "nvcommon.h"
+#include "nvodm_query.h"
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+/**
+ * @defgroup nvodm_pmu Power Management Unit Adaptation Interface 
+ *   
+ * This is the power management unit (PMU) ODM adaptation interface, which
+ * handles the abstraction of external power management devices.
+ * For NVIDIA&reg; Driver Development Kit (DDK) clients, PMU is a 
+ * set of voltages used to provide power to the SoC or to monitor low battery 
+ * conditions. The API allows DDK clients to determine whether the
+ * particular voltage is supported by the ODM platform, retrieve the
+ * capabilities of PMU, and get/set voltage levels at runtime. 
+ * On systems without power a management device, APIs should be dummy implemented.
+ *
+ * All voltage rails are referenced using ODM-assigned unsigned integers. ODMs
+ * may select any convention for assigning these values; however, the values
+ * accepted as input parameters by the PMU ODM adaptation interface must
+ * match the values stored in the address field of ::NvOdmIoModule_Vdd buses
+ * defined in the Peripheral Discovery ODM adaptation.
+ * 
+ * @ingroup nvodm_adaptation
+ * @{
+ */
+
+
+/**
+ * Defines an opaque handle that exists for each PMU device in the
+ * system, each of which is defined by the customer implementation.
+ */
+typedef struct NvOdmPmuDeviceRec *NvOdmPmuDeviceHandle;
+
+/**
+ * Combines information for the particular PMU Vdd rail.
+ */
+typedef struct NvOdmPmuVddRailCapabilitiesRec
+{
+    /// Specifies ODM protection attribute; if \c NV_TRUE PMU hardware
+    ///  or ODM Kit would protect this voltage from being changed by NvDdk client.
+    NvBool OdmProtected;
+
+    /// Specifies the minimum voltage level in mV.
+    NvU32 MinMilliVolts;
+
+    /// Specifies the step voltage level in mV.
+    NvU32 StepMilliVolts;
+
+    /// Specifies the maximum voltage level in mV.
+    NvU32 MaxMilliVolts;
+
+    /// Specifies the request voltage level in mV.
+    NvU32 requestMilliVolts;
+} NvOdmPmuVddRailCapabilities;
+
+/// Special level to indicate voltage plane is turned off.
+#define ODM_VOLTAGE_OFF (0UL)
+
+/// Special level to enable voltage plane on/off control
+///  by the external signal (e.g., low power request from SoC).
+#define ODM_VOLTAGE_ENABLE_EXT_ONOFF (0xFFFFFFFFUL)
+
+/// Special level to disable voltage plane on/off control
+///  by the external signal (e.g., low power request from SoC).
+#define ODM_VOLTAGE_DISABLE_EXT_ONOFF (0xFFFFFFFEUL)
+
+/**
+ * Gets capabilities for the specified PMU voltage.
+ *
+ * @param vddId The ODM-defined PMU rail ID.
+ * @param pCapabilities A pointer to the targeted
+ *  capabilities returned by the ODM.
+ * 
+ */
+void
+NvOdmPmuGetCapabilities(
+    NvU32 vddId,
+    NvOdmPmuVddRailCapabilities* pCapabilities);
+
+
+/**
+ * Gets current voltage level for the specified PMU voltage.
+ *
+ * @param hDevice A handle to the PMU.
+ * @param vddId The ODM-defined PMU rail ID.
+ * @param pMilliVolts A pointer to the voltage level returned
+ *  by the ODM.
+ * 
+ * @return NV_TRUE if successful, or NV_FALSE otherwise.
+ */
+NvBool
+NvOdmPmuGetVoltage(
+    NvOdmPmuDeviceHandle hDevice,
+    NvU32 vddId,
+    NvU32* pMilliVolts);
+
+
+/**
+ * Sets new voltage level for the specified PMU voltage.
+ *
+ * @param hDevice A handle to the PMU.
+ * @param vddId The ODM-defined PMU rail ID.
+ * @param MilliVolts The new voltage level to be set in millivolts (mV).
+ * - Set to ::ODM_VOLTAGE_OFF to turn off the target voltage.
+ * - Set to ::ODM_VOLTAGE_ENABLE_EXT_ONOFF to enable external control of
+ *   target voltage.
+ * - Set to ::ODM_VOLTAGE_DISABLE_EXT_ONOFF to disable external control of
+ *   target voltage.
+ * @param pSettleMicroSeconds A pointer to the settling time in microseconds (uS),
+ *  which is the time for supply voltage to settle after this function 
+ *  returns; this may or may not include PMU control interface transaction time, 
+ *  depending on the ODM implementation. If NULL this parameter is ignored, and the
+ *  function must return only after the supply voltage has settled.
+ * 
+ * @return NV_TRUE if successful, or NV_FALSE otherwise.
+ */
+NvBool
+NvOdmPmuSetVoltage(
+    NvOdmPmuDeviceHandle hDevice,
+    NvU32 vddId,
+    NvU32 MilliVolts,
+    NvU32* pSettleMicroSeconds);
+
+/**
+ * Gets a handle to the PMU in the system.
+ *
+ * @param hDevice A pointer to the handle of the PMU.
+ * 
+ * @return NV_TRUE if successful, or NV_FALSE otherwise.
+ */
+NvBool
+NvOdmPmuDeviceOpen( NvOdmPmuDeviceHandle *hDevice );
+
+
+/**
+ *  Releases the PMU handle. 
+ *
+ * @param hDevice The PMU handle to be released. If 
+ *     NULL, this API has no effect.
+ */
+void NvOdmPmuDeviceClose(NvOdmPmuDeviceHandle hDevice);
+
+
+/**
+ * Defines AC status.
+ */
+typedef enum
+{
+    /// Specifies AC is offline.
+    NvOdmPmuAcLine_Offline,
+
+    /// Specifies AC is online.
+    NvOdmPmuAcLine_Online,
+
+    /// Specifies backup power.
+    NvOdmPmuAcLine_BackupPower,
+
+    NvOdmPmuAcLine_Num,
+    NvOdmPmuAcLine_Force32 = 0x7FFFFFFF
+}NvOdmPmuAcLineStatus;
+
+/** @name Battery Status Defines */
+/*@{*/
+
+#define NVODM_BATTERY_STATUS_HIGH               0x01
+#define NVODM_BATTERY_STATUS_LOW                0x02
+#define NVODM_BATTERY_STATUS_CRITICAL           0x04
+#define NVODM_BATTERY_STATUS_CHARGING           0x08
+#define NVODM_BATTERY_STATUS_NO_BATTERY         0x80
+#define NVODM_BATTERY_STATUS_UNKNOWN            0xFF
+
+/*@}*/
+/** @name Battery Data Defines */
+/*@{*/
+#define NVODM_BATTERY_DATA_UNKNOWN              0x7FFFFFFF
+
+/*@}*/
+/**
+ * Defines battery instances.
+ */
+typedef enum
+{
+    /// Specifies main battery.
+    NvOdmPmuBatteryInst_Main,
+
+    /// Specifies backup battery.
+    NvOdmPmuBatteryInst_Backup,
+
+    NvOdmPmuBatteryInst_Num,
+    NvOdmPmuBatteryInst_Force32 = 0x7FFFFFFF
+    
+}NvOdmPmuBatteryInstance;
+
+/**
+ * Defines battery data.
+ */
+typedef struct NvOdmPmuBatteryDataRec
+{
+    /// Specifies battery life percent.
+    NvU32 batteryLifePercent;
+
+    /// Specifies battery life time.
+    NvU32 batteryLifeTime;
+
+    /// Specifies voltage.
+    NvU32 batteryVoltage;
+
+    /// Specifies battery current.
+    NvS32 batteryCurrent;
+
+    /// Specifies battery average current.
+    NvS32 batteryAverageCurrent;
+
+    /// Specifies battery interval.
+    NvU32 batteryAverageInterval;
+
+    /// Specifies the mAH consumed.
+    NvU32 batteryMahConsumed;
+
+    /// Specifies battery temperature.
+    NvU32 batteryTemperature;
+    
+}NvOdmPmuBatteryData;
+
+/**
+ * Defines battery chemistry.
+ */
+typedef enum
+{
+    /// Specifies an alkaline battery.
+    NvOdmPmuBatteryChemistry_Alkaline,
+
+    /// Specifies a nickel-cadmium (NiCd) battery.
+    NvOdmPmuBatteryChemistry_NICD,
+
+    /// Specifies a nickel-metal hydride (NiMH) battery.
+    NvOdmPmuBatteryChemistry_NIMH,
+
+    /// Specifies a lithium-ion (Li-ion) battery.
+    NvOdmPmuBatteryChemistry_LION,
+
+    /// Specifies a lithium-ion polymer (Li-poly) battery.
+    NvOdmPmuBatteryChemistry_LIPOLY,
+
+    /// Specifies a zinc-air battery.
+    NvOdmPmuBatteryChemistry_XINCAIR,
+
+    NvOdmPmuBatteryChemistry_Num,
+    NvOdmPmuBatteryChemistry_Force32 = 0x7FFFFFFF
+}NvOdmPmuBatteryChemistry;
+
+/**
+ * Gets the AC line status.
+ *
+ * @param hDevice A handle to the PMU.
+ * @param pStatus A pointer to the AC line
+ *  status returned by the ODM.
+ * 
+ * @return NV_TRUE if successful, or NV_FALSE otherwise.
+ */
+NvBool 
+NvOdmPmuGetAcLineStatus(
+    NvOdmPmuDeviceHandle hDevice, 
+    NvOdmPmuAcLineStatus *pStatus);
+
+
+/**
+ * Gets the battery status.
+ *
+ * @param hDevice A handle to the PMU.
+ * @param batteryInst The battery type.
+ * @param pStatus A pointer to the battery
+ *  status returned by the ODM.
+ * 
+ * @return NV_TRUE if successful, or NV_FALSE otherwise.
+ */
+NvBool 
+NvOdmPmuGetBatteryStatus(
+    NvOdmPmuDeviceHandle hDevice, 
+    NvOdmPmuBatteryInstance batteryInst,
+    NvU8 *pStatus);
+
+/**
+ * Gets the battery data.
+ *
+ * @param hDevice A handle to the PMU.
+ * @param batteryInst The battery type.
+ * @param pData A pointer to the battery
+ *  data returned by the ODM.
+ * 
+ * @return NV_TRUE if successful, or NV_FALSE otherwise.
+ */
+NvBool
+NvOdmPmuGetBatteryData(
+    NvOdmPmuDeviceHandle hDevice, 
+    NvOdmPmuBatteryInstance batteryInst,
+    NvOdmPmuBatteryData *pData);
+
+
+/**
+ * Gets the battery full life time.
+ *
+ * @param hDevice A handle to the PMU.
+ * @param batteryInst The battery type.
+ * @param pLifeTime A pointer to the battery
+ *  full life time returned by the ODM.
+ * 
+ */
+void
+NvOdmPmuGetBatteryFullLifeTime(
+    NvOdmPmuDeviceHandle hDevice, 
+    NvOdmPmuBatteryInstance batteryInst,
+    NvU32 *pLifeTime);
+
+
+/**
+ * Gets the battery chemistry.
+ *
+ * @param hDevice A handle to the PMU.
+ * @param batteryInst The battery type.
+ * @param pChemistry A pointer to the battery
+ *  chemistry returned by the ODM.
+ * 
+ */
+void
+NvOdmPmuGetBatteryChemistry(
+    NvOdmPmuDeviceHandle hDevice, 
+    NvOdmPmuBatteryInstance batteryInst,
+    NvOdmPmuBatteryChemistry *pChemistry);
+
+
+/** 
+* Defines the charging path. 
+*/ 
+typedef enum 
+{ 
+    /// Specifies external wall plug charger.
+    NvOdmPmuChargingPath_MainPlug, 
+ 
+    /// Specifies external USB bus charger.
+    NvOdmPmuChargingPath_UsbBus, 
+ 
+    NvOdmPmuChargingPath_Num, 
+    /// Ignore. Forces compilers to make 32-bit enums.
+    NvOdmPmuChargingPath_Force32 = 0x7FFFFFFF 
+ 
+}NvOdmPmuChargingPath; 
+
+/// Special level to indicate dumb charger current limit.
+#define NVODM_DUMB_CHARGER_LIMIT (0xFFFFFFFFUL)
+
+/// Special level to indicate USB Host mode current limit.
+#define NVODM_USB_HOST_MODE_LIMIT (0x80000000UL)
+
+/** 
+* Sets the charging current limit. 
+* 
+* @param hDevice A handle to the PMU. 
+* @param chargingPath The charging path. 
+* @param chargingCurrentLimitMa The charging current limit in mA. 
+* @param ChargerType The charger type.
+* @return NV_TRUE if successful, or NV_FALSE otherwise. 
+*/ 
+NvBool 
+NvOdmPmuSetChargingCurrent( 
+    NvOdmPmuDeviceHandle hDevice, 
+    NvOdmPmuChargingPath chargingPath, 
+    NvU32 chargingCurrentLimitMa,
+    NvOdmUsbChargerType ChargerType); 
+
+
+/**
+ * Handles the PMU interrupt.
+ *
+ * @param hDevice A handle to the PMU.
+ */
+void NvOdmPmuInterruptHandler( NvOdmPmuDeviceHandle  hDevice);
+
+/**
+ * Gets the count in seconds of the current external RTC (in PMU).
+ *
+ * @param hDevice A handle to the PMU.
+ * @param Count A pointer to where to return the current counter in sec.
+ * @return NV_TRUE if successful, or NV_FALSE otherwise. 
+ */
+NvBool
+NvOdmPmuReadRtc(
+    NvOdmPmuDeviceHandle hDevice,
+    NvU32* Count);
+
+/**
+ * Updates current RTC value.
+ *
+ * @param hDevice A handle to the PMU.
+ * @param Count data with which to update the current counter in sec.
+ * @return NV_TRUE if successful, or NV_FALSE otherwise.
+ */
+NvBool
+NvOdmPmuWriteRtc(
+    NvOdmPmuDeviceHandle hDevice,
+    NvU32 Count);
+
+/**
+ * Returns whether or not the RTC is initialized.
+ *
+ * @param hDevice A handle to the PMU.
+  * @return NV_TRUE if initialized, or NV_FALSE otherwise.
+ */
+NvBool
+NvOdmPmuIsRtcInitialized(
+    NvOdmPmuDeviceHandle hDevice);
+
+
+#if defined(__cplusplus)
+}
+#endif
+
+/** @} */
+
+#endif // INCLUDED_NVODM_PMU_H
diff --git a/arch/arm/mach-tegra/include/nvodm_query.h b/arch/arm/mach-tegra/include/nvodm_query.h
new file mode 100644
index 000000000000..a7656cfc7cae
--- /dev/null
+++ b/arch/arm/mach-tegra/include/nvodm_query.h
@@ -0,0 +1,1382 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/**
+ * @file
+ * <b>NVIDIA Tegra ODM Kit:
+ *         ODM Query API</b>
+ *
+ * @b Description: Defines a set of query functions for ODMs that may be
+ *                 accessed at boot-time, runtime, or anywhere in between.
+ */
+
+#ifndef INCLUDED_NVODM_QUERY_H
+#define INCLUDED_NVODM_QUERY_H
+
+/**
+ * @defgroup groupODMQueryAPI ODM Query API
+ * @ingroup nvodm_query
+ * @{
+ */
+
+#include "nvcommon.h"
+#include "nvodm_modules.h"
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+/**
+ * Defines the memory types for which configuration data may be retrieved.
+ */
+typedef enum
+{
+    /// Specifies SDRAM memory; target memory for runtime image and heap.
+    NvOdmMemoryType_Sdram,
+
+    /// Specifies NAND ROM; storage (may include the bootloader).
+    NvOdmMemoryType_Nand,
+
+    /// Specifies NOR ROM; storage (may include the bootloader).
+    NvOdmMemoryType_Nor,
+
+    /// Specifies EEPROM; storage (may include the bootloader).
+    NvOdmMemoryType_I2CEeprom,
+
+    /// Specifies HSMMC NAND; storage (may include the bootloader).
+    NvOdmMemoryType_Hsmmc,
+
+    /// Memory mapped I/O device.
+    NvOdmMemoryType_Mio,
+
+    /// Specifies DPRAM memory
+    NvOdmMemoryType_Dpram,
+
+    NvOdmMemoryType_Num,
+    /// Ignore -- Forces compilers to make 32-bit enums.
+    NvOdmMemoryType_Force32 = 0x7FFFFFFF
+} NvOdmMemoryType;
+
+/**
+ * Defines the devices that can serve as the debug console.
+ */
+typedef enum
+{
+    /// Specifies that the debug console is undefined.
+    NvOdmDebugConsole_Undefined,
+
+    /// Specifies that no debug console is to be used.
+    NvOdmDebugConsole_None,
+
+    /// Specifies that the ARM Debug Communication Channel
+    /// (Dcc) port is the debug console
+    NvOdmDebugConsole_Dcc,
+
+    /// Specifies that UART-A is the debug console.
+    NvOdmDebugConsole_UartA,
+
+    /// Specifies that UART-B is the debug console.
+    NvOdmDebugConsole_UartB,
+
+    /// Specifies that UART-C is the debug console.
+    NvOdmDebugConsole_UartC,
+
+    /// Specifies that UART-D is the debug console (not available on AP15/AP16).
+    NvOdmDebugConsole_UartD,
+
+    /// Specifies that UART-E is the debug console (not available on AP15/AP16).
+    NvOdmDebugConsole_UartE,
+
+    NvOdmDebugConsole_Num,
+    /// Ignore -- Forces compilers to make 32-bit enums.
+    NvOdmDebugConsole_Force32 = 0x7FFFFFFF
+} NvOdmDebugConsole;
+
+
+/**
+ * Defines the devices that can serve as the download transport.
+ */
+typedef enum
+{
+    /// Specifies that the download transport is undefined.
+    NvOdmDownloadTransport_Undefined = 0,
+
+    /// Specifies that no download transport device is to be used.
+    NvOdmDownloadTransport_None,
+
+    /// Specifies that an ODM-specific external Ethernet adapter
+    /// is the download transport device.
+    NvOdmDownloadTransport_MioEthernet,
+
+    /// Deprecated name -- retained for backward compatibility.
+    NvOdmDownloadTransport_Ethernet = NvOdmDownloadTransport_MioEthernet,
+
+    /// Specifies that USB is the download transport device.
+    NvOdmDownloadTransport_Usb,
+
+    /// Specifies that SPI (Ethernet) is the download transport device.
+    NvOdmDownloadTransport_SpiEthernet,
+
+    /// Deprecated name -- retained for backward compatibility.
+    NvOdmDownloadTransport_Spi = NvOdmDownloadTransport_SpiEthernet,
+
+    /// Specifies that UART-A is the download transport device.
+    NvOdmDownloadTransport_UartA,
+
+    /// Specifies that UART-B is the download transport device.
+    NvOdmDownloadTransport_UartB,
+
+    /// Specifies that UART-C is the download transport device.
+    NvOdmDownloadTransport_UartC,
+
+    /// Specifies that UART-D is the download transport device (not available on AP15/AP16).
+    NvOdmDownloadTransport_UartD,
+
+    /// Specifies that UART-E is the download transport device (not available on AP15/AP16).
+    NvOdmDownloadTransport_UartE,
+
+    NvOdmDownloadTransport_Num,
+    /// Ignore -- Forces compilers to make 32-bit enums.
+    NvOdmDownloadTransport_Force32 = 0x7FFFFFFF
+} NvOdmDownloadTransport;
+
+/** 
+ * Contains information and settings for the display (such as the default 
+ * backlight intensity level). 
+ */ 
+typedef struct 
+{ 
+    /// Default backlight intensity (scaled from 0 to 255). 
+    NvU8 BacklightIntensity; 
+} NvOdmQueryDisplayInfo; 
+
+/**
+ * Defines the SPI signal mode for SPI communications to the device.
+ */
+typedef enum
+{
+    /// Specifies the invalid signal mode.
+    NvOdmQuerySpiSignalMode_Invalid = 0x0,
+
+    /// Specifies mode 0 (CPOL=0, CPHA=0) of SPI controller.
+    NvOdmQuerySpiSignalMode_0,
+
+    /// Specifies mode 1 (CPOL=0, CPHA=1) of SPI controller.
+    NvOdmQuerySpiSignalMode_1,
+
+    /// Specifies mode 2 (CPOL=1, CPHA=0) of SPI controller.
+    NvOdmQuerySpiSignalMode_2,
+
+    /// Specifies mode 3 (CPOL=1, CPHA=1) of SPI controller.
+    NvOdmQuerySpiSignalMode_3,
+
+    /// Ignore -- Forces compilers to make 32-bit enums.
+    NvOdmQuerySpiSignalMode_Force32 = 0x7FFFFFFF
+} NvOdmQuerySpiSignalMode;
+
+/**
+ * Holds the SPI device information.
+ */
+typedef struct
+{
+    /// Holds the signal mode for the SPI interfacing.
+    NvOdmQuerySpiSignalMode SignalMode;
+
+    /// If this is NV_TRUE, then this device's chip select is an active-low signal
+    /// (the device is selected by driving its chip select line low). If this
+    /// is NV_FALSE, then this device's chip select is an active-high signal.
+    NvBool ChipSelectActiveLow;
+
+    /// If this is NV_TRUE, then this device is an SPI slave.
+    NvBool IsSlave;
+} NvOdmQuerySpiDeviceInfo;
+
+/**
+ * Defines the SPI signal state in idle state, i.e., when no transaction is going on.
+ */
+typedef struct
+{
+    /// Specifies the signal idle state, whether it is normal or tristate.
+    NvBool IsTristate;
+
+    /// Specifies the signal mode for idle state.
+    NvOdmQuerySpiSignalMode SignalMode;
+
+    /// Specifies the idle state data out level.
+    NvBool IsIdleDataOutHigh;
+
+} NvOdmQuerySpiIdleSignalState;
+
+/**
+ * Defines the SDIO slot usage.
+ */
+typedef enum
+{
+    /** Unused interface. */
+    NvOdmQuerySdioSlotUsage_unused = 0x0,
+
+    /** Specifies a Wireless LAN device. */
+    NvOdmQuerySdioSlotUsage_wlan = 0x1,
+
+    /** Specifies the boot slot (contains the operating system code,
+     *  typically populated by an eMMC). */
+    NvOdmQuerySdioSlotUsage_Boot = 0x2,
+    
+    /** Specifies the media slot, used for user data like audio/video/images. */
+    NvOdmQuerySdioSlotUsage_Media = 0x4,
+
+    /** Ignore -- Forces compilers to make 32-bit enums. */
+    NvOdmQuerySdioSlotUsage_Force32 = 0x7FFFFFFF,
+
+} NvOdmQuerySdioSlotUsage;
+
+/**
+ * Holds the SDIO interface properties.
+ */
+typedef struct
+{
+    /// Holds a flag indicating whether or not the eMMC card connected to the
+    /// SDIO interface is pluggable on the board.
+    ///
+    /// @note If a GPIO is already assigned by NvOdmGpioPinGroup::NvOdmGpioPinGroup_Sdio,
+    /// then this value is ignored. 
+    ///
+    /// If this is NV_TRUE, the eMMC card is pluggable on the board.
+    /// If this is NV_FALSE, the eMMC card is fixed permanently (or soldered) on the board.
+    /// For more information, see NvDdkSdioIsCardInserted().
+    NvBool IsCardRemovable;
+
+    /// Holds SDIO card HW settling time after reset, i.e., before reading the OCR.
+    NvU32 SDIOCardSettlingDelayMSec;
+
+    /// Indicates to the driver whether the card must be re-enumerated after returning
+    /// from suspend or deep sleep modes, because of power loss to the card during those
+    /// modes. NV_TRUE means that the card is powered even though the device enters
+    /// suspend or deep sleep mode, and there is no need to re-enumerate the card after
+    /// returning from suspend/deep sleep.
+    NvBool AlwaysON;
+
+    /// Indicates the tap delay to adjust the track delay on the PCB/Boards from SOC to connector.
+    NvU32 TapDelay;
+
+    /// Defines what the slot is used for.
+    NvOdmQuerySdioSlotUsage usage;
+
+} NvOdmQuerySdioInterfaceProperty;
+
+/**
+ * Defines the bus width used by the HSMMC controller on the platform.
+ */
+typedef enum
+{
+    /// Specifies the invalid bus width.
+    NvOdmQueryHsmmcBusWidth_Invalid = 0x0,
+
+    /// Specifies 4-bit wide bus.
+    NvOdmQueryHsmmcBusWidth_FourBitWide,
+
+    /// Specifies 8-bit wide bus.
+    NvOdmQueryHsmmcBusWidth_EightBitWide,
+
+    /// Ignore -- Forces compilers to make 32-bit enums.
+    NvOdmQueryHsmmcBusWidth_Force32 = 0x7FFFFFFF
+} NvOdmQueryHsmmcBusWidth;
+
+/**
+ * Holds the HSMMC interface properties.
+ */
+typedef struct
+{
+    /// Holds a flag to indicate whether or not the eMMC card connected to
+    /// the HSMMC interface is pluggable on the board. Set this to NV_TRUE
+    /// if the eMMC card is pluggable on the board. If the eMMC card is fixed
+    /// permanently (or soldered) on the board, then set this variable to NV_FALSE.
+    ///
+    /// @note If a GPIO is already assigned by NvOdmGpioPinGroup::NvOdmGpioPinGroup_Hsmmc,
+    /// then this value is ignored. 
+    /// For more information, see NvDdkHsmmcIsCardInserted().
+    NvBool IsCardRemovable;
+
+    /// Holds the bus width supported by the platform for the HSMMC controller.
+    NvOdmQueryHsmmcBusWidth Buswidth;
+} NvOdmQueryHsmmcInterfaceProperty;
+
+/**
+* Defines the OWR device details.
+*/ 
+typedef struct
+{
+    /** Flag to indicate if the "Byte transfer mode" is supported for the given
+     *  OWR device. If not supported for a given device, the driver uses
+     *  "Bit transfer mode" for reading/writing data to the device.
+     */
+    NvBool IsByteModeSupported;
+
+    /** Read data setup, Tsu = N owr clks, Range = tsu < 1. */
+    NvU32 Tsu;
+    /** Release 1-wire time, Trelease = N owr clks, Range = 0 <= trelease < 45. */
+    NvU32 TRelease;
+    /**  Read data valid time, Trdv = N+1 owr clks, Range = Exactly 15. */
+    NvU32 TRdv;
+    /** Write zero time low, Tlow0 = N+1 owr clks, Range = 60 <= tlow0 < tslot < 120. */
+    NvU32 TLow0;
+    /** Write one time low, or TLOWR both are same Tlow1 = N+1 owr clks, 
+     *  Range = 1 <= tlow1 < 15 TlowR = N+1 owr clks, Range = 1 <= tlowR < 15.
+     */
+    NvU32 TLow1;        
+    /** Active time slot for write or read data, Tslot = N+1 owr clks, 
+     *  Range = 60 <= tslot < 120.
+     */
+    NvU32 TSlot;
+
+
+    /** ::PRESENCE_DETECT_LOW Tpdl = N owr clks, Range = 60 <= tpdl < 240.  */
+    NvU32 Tpdl;
+    /** ::PRESENCE_DETECT_HIGH Tpdh = N+1 owr clks, Range = 15 <= tpdh < 60.  */
+    NvU32 Tpdh;
+    /** ::RESET_TIME_LOW Trstl = N+1 owr clks, Range = 480 <= trstl < infinity.  */
+    NvU32 TRstl;        
+    /** ::RESET_TIME_HIGH, Trsth = N+1 owr clks, Range = 480 <= trsth < infinity.  */
+    NvU32 TRsth;            
+
+    /** Program pulse width, Tpp = N owr clks Range = 480 to 5000.  */
+    NvU32 Tpp;
+    /** Program voltage fall time, Tfp = N owr clks Range = 0.5 to 5. */
+    NvU32 Tfp;
+    /** Program voltage rise time, Trp = N owr clks Range = 0.5 to 5. */
+    NvU32 Trp;
+    /** Delay to verify, Tdv = N owr clks, Range = > 5.  */
+    NvU32 Tdv;    
+    /** Delay to program, Tpd = N+1 owr clks, Range = > 5. */
+    NvU32 Tpd;
+
+    /** Should be less than or equal to (tlow1 - 6) clks, 6 clks are used for Deglitch,
+     *  if Deglitch bypassed it is 3 clks.
+     */
+    NvU32 ReadDataSampleClk;
+    /** Should be less than or equal to (tpdl - 6) clks, 6 clks are used for dglitch,
+     *  if Deglitch bypassed it is 3 clks.
+     */
+    NvU32 PresenceSampleClk;
+
+    /** OWR device memory address size. */
+    NvU32 AddressSize;
+    /** OWR device Memory size. */
+    NvU32 MemorySize;
+} NvOdmQueryOwrDeviceInfo;
+
+/**
+ * Defines the functional mode for the I2S channel.
+ */
+typedef enum
+{
+    /// Specifies the I2S controller will generate the clock.
+    NvOdmQueryI2sMode_Master = 1,
+
+    /// Specifies the I2S controller will not generate the clock;
+    /// the audio codec will generate the clock.
+    NvOdmQueryI2sMode_Slave,
+
+    /// Specifies the I2S communication is internal to audio codec.
+    NvOdmQueryI2sMode_Internal,
+
+    /// Ignore -- Forces compilers to make 32-bit enums.
+    NvOdmQueryI2sMode_Force32 = 0x7FFFFFFF
+} NvOdmQueryI2sMode;
+
+/**
+ * Defines the left and right channel data selection control for the audio.
+ */
+typedef enum
+{
+    /// Specifies the left channel when left/right line control signal is low.
+    NvOdmQueryI2sLRLineControl_LeftOnLow = 1,
+
+    /// Specifies the right channel when left/right line control signal is low.
+    NvOdmQueryI2sLRLineControl_RightOnLow,
+
+    /// Ignore -- Forces compilers to make 32-bit enums.
+    NvOdmQueryI2sLRLineControl_Force32 = 0x7FFFFFFF
+} NvOdmQueryI2sLRLineControl;
+
+/**
+ * Defines the possible I2S data communication formats with the audio codec.
+ */
+typedef enum
+{
+    /// Specifies the I2S format for data communication.
+    NvOdmQueryI2sDataCommFormat_I2S = 0x1,
+
+    /// Specifies right-justified format for data communication.
+    NvOdmQueryI2sDataCommFormat_RightJustified,
+
+    /// Specifies left-justified format for data communication.
+    NvOdmQueryI2sDataCommFormat_LeftJustified,
+
+    /// Specifies DSP format for data communication.
+    NvOdmQueryI2sDataCommFormat_Dsp,
+
+    /// Ignore -- Forces compilers to make 32-bit enums.
+    NvOdmQueryI2sDataCommFormat_Force32 = 0x7FFFFFFF
+} NvOdmQueryI2sDataCommFormat;
+
+
+/**
+ * Combines the one-time configuration property for the I2S interface with
+ * audio codec.
+ */
+typedef struct
+{
+    /// Holds the I2S controller functional mode.
+    NvOdmQueryI2sMode Mode;
+
+    /// Holds the left and right channel control.
+    NvOdmQueryI2sLRLineControl I2sLRLineControl;
+
+    /// Holds the information about the I2S data communication format.
+    NvOdmQueryI2sDataCommFormat  I2sDataCommunicationFormat;
+
+    /// Specifies the codec needs a fixed MCLK when I2s acts as Master
+    NvBool IsFixedMCLK;
+
+    /// Specifies the Fixed MCLK Frequency in Khz.
+    /// Supports only three fixed frequencies: 11289, 12288, and 12000.
+    NvU32  FixedMCLKFrequency;
+    
+} NvOdmQueryI2sInterfaceProperty;
+
+/**
+ * Defines the left and right channel data selection control.
+ */
+typedef enum
+{
+    /// Specifies the left channel when left/right line control signal is low.
+    NvOdmQuerySpdifDataCaptureControl_FromLeft = 1,
+
+    /// Specifies the right channel when left/right line control signal is low.
+    NvOdmQuerySpdifDataCaptureControl_FromRight,
+
+    /// Ignore -- Forces compilers to make 32-bit enums.
+    NvOdmQuerySpdifDataCaptureControl_Force32 = 0x7FFFFFFF
+} NvOdmQuerySpdifDataCaptureControl;
+
+/**
+ * Combines the one time configuration property for the SPDIF interface.
+ */
+typedef struct NvOdmQuerySpdifInterfacePropertyRec
+{
+    /// Holds the left and right channel control.
+    NvOdmQuerySpdifDataCaptureControl SpdifDataCaptureControl;
+} NvOdmQuerySpdifInterfaceProperty;
+
+/**
+ * Combines the one-time configuration property for the AC97 interface.
+ */
+typedef struct
+{
+    /// Identifies whether secondary codec is available.
+    NvBool IsSecondoaryCodecAvailable;
+
+    /// Identifies whether left/right surround sound is enabled.
+    NvBool IsLRSurroundSoundEnable;
+
+    /// Identifies whether LFE is enabled.
+    NvBool IsLFEEnable;
+
+    /// Identifies whether center speaker is enabled.
+    NvBool IsCenterSpeakerEnable;
+
+    /// Identifies whether left right PCM is enabled.
+    NvBool IsLRPcmEnable;
+} NvOdmQueryAc97InterfaceProperty;
+
+/**
+ * Combines the one-time configuration property for the audio codec interfaced
+ * by I2S.
+ */
+typedef struct
+{
+    /// Holds whether the audio codec is in master mode or in slave mode.
+    NvBool IsCodecMasterMode;
+
+    /// Holds the dap port index used to connect to the codec.
+    NvU32  DapPortIndex;
+
+    /// Holds the device address if it is an I2C interface, else the chip
+    /// select ID if it is an SPI interface.
+    NvU32 DeviceAddress;
+
+    /// Tells whether it is the USB mode or normal mode of interfacing for the
+    /// audio codec.
+    NvU32 IsUsbMode;
+
+    /// Holds the left and right channel control.
+    NvOdmQueryI2sLRLineControl I2sCodecLRLineControl;
+
+    /// Holds the information about the I2S data communication format.
+    NvOdmQueryI2sDataCommFormat  I2sCodecDataCommFormat;
+} NvOdmQueryI2sACodecInterfaceProp;
+
+/**
+ * Defines the oscillator source.
+ */
+typedef enum
+{
+    /// Specifies the cyrstal oscillator as the clock source.
+    NvOdmQueryOscillator_Xtal = 1,
+
+    /// Specifies an external clock source (bypass mode).
+    NvOdmQueryOscillator_External,
+
+    /// Ignore -- Forces compilers to make 32-bit enums.
+    NvOdmQueryOscillator_Force32 = 0x7FFFFFFF
+} NvOdmQueryOscillator;
+
+/**
+ *  Defines the wakeup polarity.
+ */
+typedef enum
+{
+    NvOdmWakeupPadPolarity_Low = 0,
+    NvOdmWakeupPadPolarity_High,
+    NvOdmWakeupPadPolarity_AnyEdge,
+    NvOdmWakeupPadPolarity_Force32 = 0x7FFFFFFF
+} NvOdmWakeupPadPolarity;
+
+/** Defines the wakeup pad attributes. */
+typedef struct
+{
+    /// Specifies to enable this pad as wakeup or not.
+    NvBool  enable;
+
+    /// Specifies the wake up pad number. Valid values for AP15 are 0 to 15.
+    NvU32   WakeupPadNumber;
+
+    /// Specifies wake up polarity.
+    NvOdmWakeupPadPolarity Polarity;
+
+} NvOdmWakeupPadInfo;
+
+/**
+ * Defines the index for possible connection based on the use case.
+ */
+typedef enum
+{
+    /// Specifies the default music path.
+    NvOdmDapConnectionIndex_Music_Path = 0,
+
+    /// Specifies the voice call without Bluetooth.
+    NvOdmDapConnectionIndex_VoiceCall_NoBlueTooth = 1,
+    
+    /// Specifies the HD radio.
+    NvOdmDapConnectionIndex_HD_Radio,
+
+    /// Specifies the voice call with Bluetooth.
+    NvOdmDapConnectionIndex_VoiceCall_WithBlueTooth,
+
+    /// Specifies the Bluetooth to codec.
+    NvOdmDapConnectionIndex_BlueTooth_Codec,
+
+    /// Specifies DAC1-to-DAP2 bypass, used for h/w verification.
+    NvOdmDapConnectionIndex_DAC1_DAP2,
+
+    /// Specifies DAC1-to-DAP3 bypass, used for h/w verification.
+    NvOdmDapConnectionIndex_DAC1_DAP3,
+
+    /// Specifies DAC1-to-DAP4 bypass, used for h/w verification.
+    NvOdmDapConnectionIndex_DAC1_DAP4,
+
+    /// Specifies DAC2-to-DAP2 bypass, used for hardware verification.
+    NvOdmDapConnectionIndex_DAC2_DAP2,
+
+    /// Specifies DAC2-to-DAP3 bypass, used for hardware verification.
+    NvOdmDapConnectionIndex_DAC2_DAP3,
+
+    /// Specifies DAC2-to-DAP4 bypass, used for hardware verification.
+    NvOdmDapConnectionIndex_DAC2_DAP4,
+
+    /// Specifies a custom type connection.
+    NvOdmDapConnectionIndex_Custom,
+
+    /// Specifies unknown.
+    NvOdmDapConnectionIndex_Unknown,
+    /// Ignore -- Forces compilers to make 32-bit enums.
+    NvOdmDapConnectionIndex_Force32 = 0x7FFFFFFF
+
+}NvOdmDapConnectionIndex;
+
+/**
+ * Defines the DAP port source and destination enumerations.
+ */
+typedef enum
+{
+    /// NONE DAP port - no connection.
+    NvOdmDapPort_None = 0,
+
+    /// Specifies DAP port 1.
+    NvOdmDapPort_Dap1,
+
+    /// Specifies DAP port 2.
+    NvOdmDapPort_Dap2,
+
+    /// Specifies DAP port 3.
+    NvOdmDapPort_Dap3,
+
+    /// Specifies DAP port 4.
+    NvOdmDapPort_Dap4,
+
+    /// Specifies DAP port 5.
+    NvOdmDapPort_Dap5,
+
+    /// Specifies I2S DAP port 1.
+    NvOdmDapPort_I2s1,
+
+    /// Specifies I2S DAP port 2.
+    NvOdmDapPort_I2s2,
+
+    /// Specifies AC97 DAP port.
+    NvOdmDapPort_Ac97,
+
+    /// Specifies baseband DAP port.
+    NvOdmDapPort_BaseBand,
+
+    /// Specifies Bluetooth DAP port.
+    NvOdmDapPort_BlueTooth,
+
+    /// Specifies media type DAP port.
+    NvOdmDapPort_MediaType,
+
+    /// Specifies voice type DAP port.
+    NvOdmDapPort_VoiceType,
+
+    /// Specifies high fidelity codec DAP port.
+    NvOdmDapPort_HifiCodecType,
+
+    /// Specifies voice codec DAP port.
+    NvOdmDapPort_VoiceCodecType,
+    
+    /// Ignore -- Forces compilers to make 32-bit enums.
+    NvOdmDapPort_Force32 = 0x7FFFFFFF
+} NvOdmDapPort;
+
+#define NvOdmDapPort_Max NvOdmDapPort_Dap5+1
+/**
+ * Combines the one-time configuration property for DAP device wired to the DAP port.
+ * Currently define only for best suited values. If the device can support more ranges,
+ * you have to consider it accordingly.
+ */
+typedef struct NvOdmDapDevicePropertyRec
+{
+    /// Specifies the number of channels, such as 2 for stereo.
+    NvU32 NumberOfChannels;
+
+    /// Specifies the number of bits per sample, such as 8 or 16 bits.
+    NvU32 NumberOfBitsPerSample;
+
+    /// Specifies the sampling rate in Hz, such as 8000 for 8 kHz, 44100
+    /// for 44.1 kHz.
+    NvU32 SamplingRateInHz;
+
+    /// Holds the information DAP port data communication format.
+    NvOdmQueryI2sDataCommFormat  DapPortCommunicationFormat;
+
+}NvOdmDapDeviceProperty;
+
+/**
+*  Defines the connection line and connection table.
+*/
+typedef struct NvOdmQueryDapPortConnectionLinesRec
+{
+    /// Specifies the source for the connection line.
+    NvOdmDapPort Source;
+
+    /// Specifies the destination for the connection line.
+    NvOdmDapPort Destination;
+
+    /// Specifies the source to act as master or slave.
+    NvBool       IsSourceMaster;
+
+}NvOdmQueryDapPortConnectionLines;
+
+/**
+*  Increases the maximum connection line based on use case connection needed.
+*/
+#define NVODM_MAX_CONNECTIONLINES 8
+
+/**
+*    Defines the DAP port connection.
+*/
+typedef struct NvOdmQueryDapPortConnectionRec
+{
+    /// Specifie the connection use case from the enum provided.
+    NvU32 UseIndex;
+
+    /// Specifies the number of connection line for the table.
+    NvU32 NumofEntires;
+
+    /// Specifies the connection lines for the table.
+    NvOdmQueryDapPortConnectionLines DapPortConnectionLines[NVODM_MAX_CONNECTIONLINES];
+
+}NvOdmQueryDapPortConnection;
+/**
+ * Combines the one-time configuration property for DAP port setting.
+ */
+typedef struct NvOdmQueryDapPortPropertyRec
+{
+    /// Specifies the source for the DAP port.
+    NvOdmDapPort DapSource;
+
+    /// Specifies the destination for the DAP port.
+    NvOdmDapPort DapDestination;
+
+    /// Specified the property of device wired to DAP port.
+    NvOdmDapDeviceProperty DapDeviceProperty;
+
+} NvOdmQueryDapPortProperty;
+
+/**
+ *  Defines ODM interrupt polarity.
+ */
+typedef enum
+{
+    NvOdmInterruptPolarity_Low = 1,
+    NvOdmInterruptPolarity_High,
+    NvOdmInterruptPolarity_Force32 = 0x7FFFFFFF
+} NvOdmInterruptPolarity;
+
+/**
+ *  Defines core power request polarity, as required by a PMU.
+ */
+typedef enum
+{
+  NvOdmCorePowerReqPolarity_Low,
+  NvOdmCorePowerReqPolarity_High,
+  NvOdmCorePowerReqPolarity_Force32 = 0x7FFFFFFF
+}NvOdmCorePowerReqPolarity;
+
+/**
+ *  Defines system clock request polarity, as required by the clock source.
+ */
+typedef enum
+{
+  NvOdmSysClockReqPolarity_Low,
+  NvOdmSysClockReqPolarity_High,
+  NvOdmSysClockReqPolarity_Force32 = 0x7FFFFFFF
+}NvOdmSysClockReqPolarity;
+
+
+/**
+ * Combines PMU configuration properties.
+ */
+typedef struct NvOdmPmuPropertyRec
+{
+    /// Specifies if PMU interrupt is connected to SoC.
+    NvBool IrqConnected;
+
+    /// Specifies the time required for power to be stable (in 32 kHz counts).
+    NvU32   PowerGoodCount;
+
+    /// Specifies the PMU interrupt polarity.
+    NvOdmInterruptPolarity IrqPolarity;
+
+    /// Specifies the core power request signal polarity.
+    NvOdmCorePowerReqPolarity CorePowerReqPolarity;
+
+    /// Specifies the system clock request signal polarity.
+    NvOdmSysClockReqPolarity SysClockReqPolarity;
+
+    /// Specifies whether or not only one power request input on PMU is available. 
+    /// Relevant for SoCs with separate CPU and core power request outputs:
+    /// - NV_TRUE specifies PMU has single power request input, in this case SoC 
+    /// CPU and core power requests must be combined by external logic with
+    /// proper pull-up/pull-down.
+    /// - NV_FALSE specifies PMU has at least two power request inputs, in this
+    /// case SoC CPU and core power requests are connected separately to
+    /// the respective PMU inputs.
+    NvBool CombinedPowerReq;
+
+    /// Specifies the time required for CPU power to be stable (in US).
+    /// Relevant for SoC with separate CPU and core power request outputs.
+    NvU32 CpuPowerGoodUs;
+
+    /// Specifies whether or not CPU voltage will switch back to OTP (default)
+    /// value after CPU request on-off-on transition (typically this transition
+    /// happens on entry/exit to/from low power states). Relevant for SoCs with
+    /// separate CPU and core power request outputs:
+    /// - NV_TRUE specifies PMU will switch CPU voltage to default level after
+    /// CPU request  on-off-on transition. This PMU mode is not compatible with
+    /// DVFS core voltage scaling, which will be disabled in this case.
+    /// - NV_FALSE specifies PMU will restore CPU voltage after CPU request
+    ///  on-off-on transition to the level it has just before the transition
+    /// happens. In this case DVFS core voltage scaling can be enabled.
+    NvBool  VCpuOTPOnWakeup;
+
+    /// Specifies PMU Core and CPU voltage regulation accuracy in percent
+    NvU32 AccuracyPercent;
+
+} NvOdmPmuProperty;
+
+/**
+ *  Defines SOC power states.
+ */
+typedef enum
+{
+  /// State where power to non-always-on (non-AO) partitions are
+  /// removed, and double-data rate (DDR) SDRAM is in self-refresh
+  /// mode. Wake up by any enabled \a external event/interrupt.
+  NvOdmSocPowerState_DeepSleep,
+
+  /// State where the CPU is halted by the flow controller and power
+  /// is gated, plus DDR is in self-refresh. Wake up by any enabled interrupt.
+  NvOdmSocPowerState_Suspend,
+
+  /// Specifies to disable the SOC power state.
+  NvOdmSocPowerState_Active,
+
+  /// Ignore -- Forces compilers to make 32-bit enums.
+  NvOdmSocPowerState_Force32 = 0x7FFFFFFFUL
+
+} NvOdmSocPowerState;
+
+/**
+ *  SOC power state information.
+ */
+typedef struct NvOdmSocPowerStateInfoRec
+{
+    // Specifies the lowest supported power state.
+    NvOdmSocPowerState LowestPowerState;
+
+    // Specifies the idle time (in Msecs) threshold to enter the power state.
+    NvU32 IdleThreshold;
+
+} NvOdmSocPowerStateInfo;
+
+/**  External interface type for USB controllers */
+typedef enum
+{
+    /// Specifies the USB controller is connected to a standard UTMI interface
+    /// (only valid for ::NvOdmIoModule_Usb).
+    NvOdmUsbInterfaceType_Utmi = 1,
+
+    /// Specifies the USB controller is connected to a phy-less ULPI interface
+    /// (only valid for ::NvOdmIoModule_Ulpi).
+    NvOdmUsbInterfaceType_UlpiNullPhy,
+
+    /// Specifies the USB controller is connected to a ULPI interface that has an
+    /// external phy (only valid for \c NvOdmIoModule_Ulpi).
+    NvOdmUsbInterfaceType_UlpiExternalPhy,
+
+    /// Ignore -- Forces compilers to make 32-bit enums.
+    NvOdmUsbInterfaceType_Force32 = 0x7FFFFFFFUL
+
+} NvOdmUsbInterfaceType;
+
+
+/** Defines the USB line states. */ 
+typedef enum 
+{
+    /// Specifies USB host based charging type.
+    NvOdmUsbChargerType_UsbHost = 0,
+
+    /// Specifies charger type 0, USB compliant charger, when D+ and D- are at low voltage.
+    NvOdmUsbChargerType_SE0 = 1,
+
+    /// Specifies charger type 1, when D+ is high and D- is low.
+    NvOdmUsbChargerType_SJ = 2,
+
+    /// Specifies charger type 2, when D+ is low and D- is high.
+    NvOdmUsbChargerType_SK = 4,
+
+    /// Specifies charger type 3, when D+ and D- are at high voltage.
+    NvOdmUsbChargerType_SE1 = 8,
+
+    /// Specifies charger type 4, D+ and D- are undefined.
+    /// @note If dummy charger is selected, then charger type will be always 
+    /// dummy and other type chargers are detected but treated as dummy.
+    NvOdmUsbChargerType_Dummy = 0x10,
+
+    /// Ignore -- Forces compilers to make 32-bit enums.
+    NvOdmUsbChargerType_Force32 = 0x7FFFFFFF,
+} NvOdmUsbChargerType;
+
+/** Defines the USB mode for the instance. */ 
+typedef enum 
+{
+    /// Specifies the instance is not present or cannot be used for USB.
+    NvOdmUsbModeType_None = 0,
+
+    /// Specifies the instance as USB host.
+    NvOdmUsbModeType_Host = 1,
+
+    /// Specifies the instance as USB Device.
+    NvOdmUsbModeType_Device = 2,
+
+    /// Specifies the instance as USB OTG.
+    NvOdmUsbModeType_OTG= 4,
+
+    /// Ignore -- Forces compilers to make 32-bit enums.
+    NvOdmUsbModeType_Force32 = 0x7FFFFFFF,
+} NvOdmUsbModeType;
+
+/** Defines the USB ID pin detection type. */ 
+typedef enum 
+{
+    /// Specifies there is no ID pin detection mechanism.
+    NvOdmUsbIdPinType_None = 0,
+
+    /// Specifies ID pin detection is done with GPIO.
+    NvOdmUsbIdPinType_Gpio= 1,
+
+    /// Specifies ID pin detection is done with cable ID.
+    NvOdmUsbIdPinType_CableId= 2,
+
+    /// Ignore -- Forces compilers to make 32-bit enums.
+    NvOdmUsbIdPinType_Force32 = 0x7FFFFFFF,
+} NvOdmUsbIdPinType;
+
+/** Defines the USB connectors multiplex type. */ 
+typedef enum 
+{
+    /// Specifies there is no connectors mux  mechanism
+   NvOdmUsbConnectorsMuxType_None = 0,
+
+    /// Specifies microAB/TypeA mux is available. 
+    NvOdmUsbConnectorsMuxType_MicroAB_TypeA= 1,
+
+    /// Ignore -- Forces compilers to make 32-bit enums.
+    NvOdmUsbConnectorsMuxType_Force32 = 0x7FFFFFFF,
+} NvOdmUsbConnectorsMuxType;
+
+/**
+ *  Defines the USB trimmer control values. Keep all values zero unless the
+ *  default trimmer values programmed in DDK do not work on the customer board.
+ */
+typedef struct NvOdmUsbTrimmerCtrlRec
+{
+    /// Programmable delay on the Shadow ULPI Clock (0 ~ 31)
+    NvU8 UlpiShadowClkDelay;
+
+    /// Programmable delay on the ULPI Clock out (0 ~ 31)
+    NvU8 UlpiClockOutDelay;
+
+    /// ULPI Data Trimmer Value (0 ~ 7)
+    NvU8 UlpiDataTrimmerSel;
+
+    /// ULPI STP/DIR/NXT Trimmer Value (0 ~ 7)
+    NvU8 UlpiStpDirNxtTrimmerSel;
+} NvOdmUsbTrimmerCtrl;
+
+/**  Defines USB interface properties. */
+typedef struct NvOdmUsbPropertyRec
+{
+    ///  Specifies the USB controller's external interface type.
+    ///  @see NvOdmUsbInterfaceType
+    NvOdmUsbInterfaceType UsbInterfaceType;
+
+    /// Specifies the charger types supported on this interface.
+    /// If dummy charger is selected then other type chargers are detected as dummy.
+    /// @see NvOdmUsbChargerType
+    NvU32 SupportedChargers;
+
+    /// Specifies the time required to wait before checking for the line status.
+    /// @see NvOdmUsbChargerType
+    NvU32 ChargerDetectTimeMs;
+
+    /// Specifies internal PHY to use as source for VBUS detection in the low power mode.
+    /// Set to NV_TRUE to use internal PHY for VBUS detection.
+    /// Set to NV_FALSE to use PMU interrupt for VBUS detection.
+    NvBool UseInternalPhyWakeup;
+
+    /// Specifies the USB mode for the instance.
+    /// @see NvOdmUsbModeType
+    NvU32 UsbMode;
+
+    /// Specifies the USB ID pin detection type.
+    /// @see NvOdmUsbIdPinType
+    NvU32 IdPinDetectionType;
+
+    /// Specifies the USB connectors multiplex type.
+    /// @see NvOdmUsbConnectorsMuxType
+    NvOdmUsbConnectorsMuxType   ConMuxType;
+
+    /// Specifies Usb rail to  power off or not  in the deep sleep mode.
+    /// Set to NV_TRUE to specify usb rail power off in the deep sleep
+    /// Set to NV_FALSE to specify usb rail can not be power off in the deep sleep
+    NvBool UsbRailPoweOffInDeepSleep;
+
+    /// Specifies the USB trimmer values. The default value will be used if all values are zeros.
+    /// @see NvOdmUsbTrimmerCtrl
+    NvOdmUsbTrimmerCtrl TrimmerCtrl;
+} NvOdmUsbProperty;
+
+/** Defines wakeup sources. */
+typedef enum
+{
+    NvOdmGpioWakeupSource_Invalid = 0,
+    NvOdmGpioWakeupSource_RIL,
+    NvOdmGpioWakeupSource_UART,
+    NvOdmGpioWakeupSource_BluetoothIrq,
+    NvOdmGpioWakeupSource_HDMIDetection,
+    NvOdmGpioWakeupSource_USB,
+    NvOdmGpioWakeupSource_Lid,
+    NvOdmGpioWakeupSource_AudioIrq,
+    NvOdmGpioWakeupSource_ACCIrq,
+    NvOdmGpioWakeupSource_HSMMCCardDetect,
+    NvOdmGpioWakeupSource_SdioDat1,
+    NvOdmGpioWakeupSource_SdioCardDetect,
+    NvOdmGpioWakeupSource_KBC,
+    NvOdmGpioWakeupSource_PWR,
+    NvOdmGpioWakeupSource_BasebandModem,
+    NvOdmGpioWakeupSource_DVI,
+    NvOdmGpioWakeupSource_GpsOnOff,
+    NvOdmGpioWakeupSource_GpsInterrupt,
+    NvOdmGpioWakeupSource_Accelerometer,
+    NvOdmGpioWakeupSource_HeadsetDetect,
+    NvOdmGpioWakeupSource_PenInterrupt,
+    NvOdmGpioWakeupSource_WlanInterrupt,
+    NvOdmGpioWakeupSource_UsbVbus,
+    NvOdmGpioWakeupSource_Force32 = 0x7FFFFFFF,
+} NvOdmGpioWakeupSource;
+
+/**
+ * Gets the total memory size for the specified memory type.
+ *
+ * @note The implementation of this function must not make reference to
+ * any global or static variables of any kind whatsoever.
+ *
+ * @param MemType Specifies the memory type.
+ *
+ * @return The memory size (in bytes), or 0 if no memory of that type exists.
+ */
+NvU32 NvOdmQueryMemSize(NvOdmMemoryType MemType);
+
+/**
+ * Gets the memory occupied by the secure region. Must be 1 MB aligned.
+ *
+ * @returns The memory occupied (in bytes).
+ */
+NvU32 NvOdmQuerySecureRegionSize(void);
+
+/**
+ * Gets the size of the carveout region.
+ *
+ * The carveout memory region is contiguous physical memory used by some
+ * software modules instead of allocating memory from the OS heap. This memory
+ * is separate from the operating system's heap.
+ *
+ * The carveout memory region is useful because the OS heap often becomes
+ * fragmented after boot time, making it difficult to obtain physically
+ * contiguous memory.
+ */
+NvU32 NvOdmQueryCarveoutSize(void);
+
+/**
+ * Gets the port to use as the debug console.
+ *
+ * @return The debug console ID.
+ */
+NvOdmDebugConsole NvOdmQueryDebugConsole(void);
+
+/**
+ * Gets the device to use as the download transport.
+ *
+ * @return The download transport device ID.
+ */
+NvOdmDownloadTransport NvOdmQueryDownloadTransport(void);
+
+/**
+ * Gets the null-terminated device name prefix string (i.e., that
+ * part of a device name that is common to all devices of this type).
+ *
+ * @return The device name prefix string.
+ */
+const NvU8* NvOdmQueryDeviceNamePrefix(void);
+
+/** 
+ * Gets the configuration info for the display. 
+ * 
+ * @param Instance The instance number of the display controller. 
+ * @return A pointer to the structure containing the display information. 
+ */
+const NvOdmQueryDisplayInfo * 
+NvOdmQueryGetDisplayInfo(
+    NvU32 Instance); 
+
+/**
+ * Gets the interfacing properties of the device connected to a given chip
+ * select on a given SPI controller.
+ *
+ * @param OdmIoModule The ODM I/O module name, such as SPI, S-LINK, or S-Flash.
+ * @param ControllerId The SPI instance ID.
+ * @param ChipSelect The chip select ID from the connected device.
+ *
+ * @return A pointer to a structure describing the device's properties.
+ */
+const NvOdmQuerySpiDeviceInfo *
+NvOdmQuerySpiGetDeviceInfo(
+    NvOdmIoModule OdmIoModule,
+    NvU32 ControllerId,
+    NvU32 ChipSelect);
+
+
+/**
+ * Gets the default signal level of the SPI interfacing lines.
+ * This indicates whether signal lines are in the tristate or not, and if not,
+ * then indicates what is the normal state of the SCLK and data out line.
+ * This state is set once the transaction is completed.
+ * During the transaction, the chip-specific setting is done.
+ *
+ * @param OdmIoModule The ODM I/O module name, such as SPI, S-LINK, or S-Flash.
+ * @param ControllerId The SPI instance ID.
+ *
+ * @return A pointer to a structure describing the idle signal state.
+ */
+const NvOdmQuerySpiIdleSignalState *
+NvOdmQuerySpiGetIdleSignalState(
+    NvOdmIoModule OdmIoModule,
+    NvU32 ControllerId);
+
+/**
+ * Gets the S/PDIF interfacing property parameters with the audio codec that
+ * are set for the data transfer.
+ *
+ * @param SpdifInstanceId The S/PDIF controller instance ID.
+ *
+ * @return A pointer to a structure describing the I2S interface properties.
+ */
+const NvOdmQuerySpdifInterfaceProperty *
+NvOdmQuerySpdifGetInterfaceProperty(
+    NvU32 SpdifInstanceId);
+
+ /**
+ * Gets the I2S interfacing property parameter, which is set for
+ * the data transfer.
+ *
+ * @param I2sInstanceId The I2S controller instance ID.
+ *
+ * @return A pointer to a structure describing the I2S interface properties.
+ *
+ */
+const NvOdmQueryI2sInterfaceProperty *
+NvOdmQueryI2sGetInterfaceProperty(
+    NvU32 I2sInstanceId);
+
+/**
+ * Gets the AC97 interfacing property with AC97 codec parameters that are set
+ * for the data transfer.
+ *
+ * @param Ac97InstanceId The instance ID for the AC97 cotroller.
+ *
+ * @return A pointer to a structure describing the AC97 interface properties.
+ *
+ */
+const NvOdmQueryAc97InterfaceProperty *
+NvOdmQueryAc97GetInterfaceProperty(
+    NvU32 Ac97InstanceId);
+
+/**
+ * Gets the DAP port property.
+ *
+ * This shows how the DAP connection is made along with
+ * the format and mode it supports.
+ *
+ * @param DapPortId The DAP port.
+ *
+ * @return A pointer to a structure holding the DAP port connection properties.
+ */
+const NvOdmQueryDapPortProperty *
+NvOdmQueryDapPortGetProperty(
+    NvU32 DapPortId);
+
+/**
+ * Gets the DAP port connection table.
+ *
+ * This shows how the connections are made along with
+ * the use case.
+ *
+ * @param ConnectionIndex The index to ConnectionTable based on the use case.
+ *
+ * @return A pointer to a structure holding the connection lines.
+ */
+const NvOdmQueryDapPortConnection*
+NvOdmQueryDapPortGetConnectionTable(
+    NvU32 ConnectionIndex);
+
+/**
+ * Gets the I2S audio codec interfacing property.
+ *
+ * @param AudioCodecId The instance ID or the audio codec cotroller.
+ *
+ * @return A pointer to a structure describing the audio codec interface
+ *           properties.
+ */
+const NvOdmQueryI2sACodecInterfaceProp *
+NvOdmQueryGetI2sACodecInterfaceProperty(
+    NvU32 AudioCodecId);
+
+/**
+ * Gets the oscillator source.
+ *
+ * @see NvOdmQueryOscillator
+ *
+ * @return The oscillator source.
+ */
+NvOdmQueryOscillator NvOdmQueryGetOscillatorSource(void);
+
+/**
+ * Gets the oscillator drive strength setting.
+ *
+ * @return The oscillator drive strength setting.
+ */
+NvU32 NvOdmQueryGetOscillatorDriveStrength(void);
+
+/**
+ * Gets the null-terminated device manufacturer string.
+ *
+ * @return A pointer to the device manufacturer string.
+ */
+const NvU8* NvOdmQueryManufacturer(void);
+
+/**
+ * Gets the null-terminated device model string.
+ *
+ * @return A pointer to the device model string.
+ */
+const NvU8* NvOdmQueryModel(void);
+
+/**
+ * Gets the null-terminated device platform string.
+ *
+ * @return A pointer to the device platform string.
+ */
+const NvU8* NvOdmQueryPlatform(void);
+
+/**
+ * Gets the null-terminated device project name string.
+ *
+ * @return A pointer to the device project name string.
+ */
+const NvU8* NvOdmQueryProjectName(void);
+
+/**
+ * Gets the wake pads configuration table.
+ *
+ * @param entries A pointer to a variable that this function sets to the
+ * number of entries in the configuration table.
+ *
+ * @return A pointer to the configuration table.
+ */
+const NvOdmWakeupPadInfo *NvOdmQueryGetWakeupPadTable(NvU32 *entries);
+
+/**
+ * Gets the external PMU property.
+ *
+ * @param pPmuProperty A pointer to the returned PMU property structure.
+ *
+ * @return NV_TRUE if successful, or NV_FALSE otherwise.
+ */
+NvBool NvOdmQueryGetPmuProperty(NvOdmPmuProperty* pPmuProperty);
+
+/**
+ * Gets the lowest SOC power state info supported by the ODM.
+ *
+ * @return A pointer to the NvOdmSocPowerStateInfo structure
+ */
+const NvOdmSocPowerStateInfo* NvOdmQueryLowestSocPowerState(void);
+
+/**
+ * Returns the type of the USB interface based on module ID and
+ * instance. The \a Module and \a Instance parameter are identical to the
+ * \a IoModule parameter and array index, respectively, used in the 
+ * NvOdmQueryPinMux() and NvOdmQueryClockLimits() APIs.
+ *
+ * @return The properties structure for the USB interface.
+ */
+const NvOdmUsbProperty*
+NvOdmQueryGetUsbProperty(NvOdmIoModule Module, NvU32 Instance);
+
+/**
+ * Gets the interface properties of the SDIO controller.
+ *
+ * @param Instance The instance number of the SDIO controller.
+ * @return A pointer to the structure containing the SDIO interface property.
+ */
+ 
+const NvOdmQuerySdioInterfaceProperty*
+NvOdmQueryGetSdioInterfaceProperty(
+        NvU32 Instance);
+
+/**
+ * Gets the interface properties of the HSMMC controller.
+ *
+ * @param Instance The instance number of the HSMMC controller.
+ * @return A pointer to the structure containing the HSMMC interface property.
+ */
+ 
+const NvOdmQueryHsmmcInterfaceProperty*
+NvOdmQueryGetHsmmcInterfaceProperty(
+        NvU32 Instance);
+
+/**
+ * Gets the ODM-specific sector size for block devices.
+ *
+ * @param OdmIoModule The ODM I/O module type.
+ * @return An integer indicating the sector size if non-zero, or 
+ *      zero if the sector size equals the actual device-reported sector size.
+ */
+NvU32
+NvOdmQueryGetBlockDeviceSectorSize(NvOdmIoModule OdmIoModule);
+
+/**
+ * Gets the OWR device information.
+ *
+ * @param Instance The instance number of the OWR controller.
+ * @return A pointer to the structure containing the OWR device info.
+ */
+const NvOdmQueryOwrDeviceInfo* NvOdmQueryGetOwrDeviceInfo(NvU32 Instance);
+
+/**
+ * Gets the list of supported wakeup sources.
+ *
+ * @param pCount The number of wakeup sources.
+ * @return A pointer to the array containing the wakeup sources.
+ */
+const NvOdmGpioWakeupSource *NvOdmQueryGetWakeupSources(NvU32 *pCount);
+
+#if defined(__cplusplus)
+}
+#endif
+
+/** @} */
+
+#endif // INCLUDED_NVODM_QUERY_H
diff --git a/arch/arm/mach-tegra/include/nvodm_query_discovery.h b/arch/arm/mach-tegra/include/nvodm_query_discovery.h
new file mode 100644
index 000000000000..1a109fd8381e
--- /dev/null
+++ b/arch/arm/mach-tegra/include/nvodm_query_discovery.h
@@ -0,0 +1,371 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/**
+ * @file
+ * <b>NVIDIA Tegra ODM Kit:
+ *         ODM Peripheral Discovery API</b>
+ *
+ * @b Description: Defines a query interface for enumerating peripherals
+ *                 and the board-specific topology that may be called during
+ *                 boot and at run-time.
+ */
+
+#ifndef INCLUDED_NVODM_QUERY_DISCOVERY_H
+#define INCLUDED_NVODM_QUERY_DISCOVERY_H
+
+/**
+ * @defgroup nvodm_discovery ODM Peripheral Discovery Interface
+ *
+ * This is the ODM query interface allowing ODMs to specify the connectivity
+ * of peripherals on their boards to I/Os on an NVIDIA&reg; Application Processor
+ * without modifying the driver libraries.
+ *
+ * All peripherals connected to the application processor are referenced by
+ * their Global Unique Identifier code, or GUID. The GUID is an ODM-defined
+ * 64-bit value (8-character code) that uniquely identifies each peripheral,
+ * i.e., each peripheral will have exactly one GUID, and each GUID will refer
+ * to exactly one peripheral.
+ * 
+ * The implementation of this API is similar to a simple database: tables are
+ * provided by the ODMs that, for every peripheral, define the peripheral's
+ * GUID, and specify the bus, or set of buses, to which the peripheral is
+ * connected. As an example, an audio codec peripheral with GUID 0 could be
+ * connected to the application processor by DAP instance 0, I2C instance 1
+ * (address 0x80), and voltage rail 3. The functions provided by this API
+ * provide facilities enabling the boot process and driver libraries to
+ * enumerate the set of peripherals attached to a specific bus, the set of
+ * peripherals with specific functionality (such as display outputs), and the
+ * set of buses connected to a specific peripheral.
+ * @ingroup nvodm_query
+ * @{
+ */
+
+#include "nvodm_modules.h"
+#include "nvodm_services.h"
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+/**
+ * The NV_ODM_GUID macro is used to convert ASCII 8-character codes into the
+ * 64-bit globally-unique identifiers that identify each peripheral.
+ *
+ * @note GUIDs beginning with the characters <b>nv</b>, <b>Nv</b>, <b>nV</b>,
+ * and <b>NV</b> are reserved for use by NVIDIA; all other values may be
+ * assigned by the ODM as desired.
+ */
+#define NV_ODM_GUID(a,b,c,d,e,f,g,h) \
+    ((NvU64) ((((a)&0xffULL)<<56ULL) | (((b)&0xffULL)<<48ULL) | \
+              (((c)&0xffULL)<<40ULL) | (((d)&0xffULL)<<32ULL) | \
+              (((e)&0xffULL)<<24ULL) | (((f)&0xffULL)<<16ULL) | \
+              (((g)&0xffULL)<< 8ULL) | (((h)&0xffULL))))
+
+/**
+ * Reserved GUIDs.
+ */
+#define NV_VDD_RTC_ODM_ID       (NV_ODM_GUID('N','V','D','D','_','R','T','C'))
+#define NV_VDD_CORE_ODM_ID      (NV_ODM_GUID('N','V','D','D','C','O','R','E'))
+#define NV_VDD_CPU_ODM_ID       (NV_ODM_GUID('N','V','D','D','_','C','P','U'))
+
+#define NV_VDD_PLLA_ODM_ID      (NV_ODM_GUID('N','V','D','D','P','L','L','A'))
+#define NV_VDD_PLLM_ODM_ID      (NV_ODM_GUID('N','V','D','D','P','L','L','M'))
+#define NV_VDD_PLLP_ODM_ID      (NV_ODM_GUID('N','V','D','D','P','L','L','P'))
+#define NV_VDD_PLLC_ODM_ID      (NV_ODM_GUID('N','V','D','D','P','L','L','C'))
+#define NV_VDD_PLLD_ODM_ID      (NV_ODM_GUID('N','V','D','D','P','L','L','D'))
+#define NV_VDD_PLLE_ODM_ID      (NV_ODM_GUID('N','V','D','D','P','L','L','E'))
+#define NV_VDD_PLLU_ODM_ID      (NV_ODM_GUID('N','V','D','D','P','L','L','U'))
+#define NV_VDD_PLLU1_ODM_ID     (NV_ODM_GUID('N','V','D','P','L','L','U','1'))
+#define NV_VDD_PLLHDMI_ODM_ID   (NV_ODM_GUID('N','V','D','P','L','L','H','D'))
+#define NV_VDD_OSC_ODM_ID       (NV_ODM_GUID('N','V','D','D','_','O','S','C'))
+#define NV_VDD_PLLS_ODM_ID      (NV_ODM_GUID('N','V','D','D','P','L','L','S'))
+#define NV_VDD_PLLX_ODM_ID      (NV_ODM_GUID('N','V','D','D','P','L','L','X'))
+#define NV_VDD_PLL_USB_ODM_ID   (NV_ODM_GUID('N','V','D','P','L','L','U','S'))
+#define NV_VDD_PLL_PEX_ODM_ID   (NV_ODM_GUID('N','V','D','P','L','L','P','X'))
+
+#define NV_VDD_SYS_ODM_ID       (NV_ODM_GUID('N','V','D','D','_','S','Y','S'))
+#define NV_VDD_USB_ODM_ID       (NV_ODM_GUID('N','V','D','D','_','U','S','B'))
+#define NV_VDD_HDMI_ODM_ID      (NV_ODM_GUID('N','V','D','D','H','D','M','I'))
+#define NV_VDD_MIPI_ODM_ID      (NV_ODM_GUID('N','V','D','D','M','I','P','I'))
+#define NV_VDD_LCD_ODM_ID       (NV_ODM_GUID('N','V','D','D','_','L','C','D'))
+#define NV_VDD_AUD_ODM_ID       (NV_ODM_GUID('N','V','D','D','_','A','U','D'))
+#define NV_VDD_DDR_ODM_ID       (NV_ODM_GUID('N','V','D','D','_','D','D','R'))
+#define NV_VDD_DDR_RX_ODM_ID    (NV_ODM_GUID('N','V','D','D','D','R','R','X'))
+#define NV_VDD_NAND_ODM_ID      (NV_ODM_GUID('N','V','D','D','N','A','N','D'))
+#define NV_VDD_UART_ODM_ID      (NV_ODM_GUID('N','V','D','D','U','A','R','T'))
+#define NV_VDD_SDIO_ODM_ID      (NV_ODM_GUID('N','V','D','D','S','D','I','O'))
+#define NV_VDD_VDAC_ODM_ID      (NV_ODM_GUID('N','V','D','D','V','D','A','C'))
+#define NV_VDD_VI_ODM_ID        (NV_ODM_GUID('N','V','D','D','_','_','V','I'))
+#define NV_VDD_BB_ODM_ID        (NV_ODM_GUID('N','V','D','D','_','_','B','B'))
+#define NV_VDD_VBUS_ODM_ID      (NV_ODM_GUID('N','V','D','D','V','B','U','S'))
+#define NV_VDD_USB2_VBUS_ODM_ID (NV_ODM_GUID('N','V','D','V','B','U','S','2'))
+#define NV_VDD_USB3_VBUS_ODM_ID (NV_ODM_GUID('N','V','D','V','B','U','S','3'))
+
+#define NV_VDD_HSIC_ODM_ID      (NV_ODM_GUID('N','V','D','D','H','S','I','C'))
+#define NV_VDD_USB_IC_ODM_ID    (NV_ODM_GUID('N','V','D','D','U','S','B','I'))
+#define NV_VDD_PEX_ODM_ID       (NV_ODM_GUID('N','V','D','D','_','P','E','X'))
+#define NV_VDD_PEX_CLK_ODM_ID   (NV_ODM_GUID('N','V','D','D','P','E','X','C'))
+#define NV_VDD_SoC_ODM_ID       (NV_ODM_GUID('N','V','D','D','_','S','O','C'))
+
+#define NV_PMU_TRANSPORT_ODM_ID (NV_ODM_GUID('N','V','P','M','U','T','R','N'))
+
+/**
+ * Some of the NVIDIA driver libraries enumerate peripherals based on the
+ * logical functionality that the peripheral performs, rather than by the
+ * bus that connects it. An example of this is the camera driver, which
+ * enumerates all peripherals supporting camera functionality on an ODM's
+ * system (depending on the target market, 0, 1, or multiple cameras may
+ * be present). To support this abstract functionality-based query, each
+ * peripheral is assigned a class based on the user-level functionality it
+ * provides.
+ */
+typedef enum
+{
+    /// Specifies a display output peripheral, such as an LCD or attached TV.
+    NvOdmPeripheralClass_Display = 1,
+
+    /// Specifies a camera (imager) input peripheral.
+    NvOdmPeripheralClass_Imager,
+
+    /// Specifies a mass-storage device, such as a NAND flash controller.
+    NvOdmPeripheralClass_Storage,
+
+    /// Specifies a human-computer input, such as a keypad or touch panel.
+    NvOdmPeripheralClass_HCI,
+
+    /// Specifies a peripheral that does not fall into the other classes.
+    NvOdmPeripheralClass_Other,
+
+    NvOdmPeripheralClass_Num,
+    /// Ignore -- Forces compilers to make 32-bit enums.
+    NvOdmPeripheralClass_Force32 = 0x7fffffffUL
+} NvOdmPeripheralClass;
+
+/** 
+ * Defines the unique address on a bus where a peripheral is connected.
+ */
+typedef struct 
+{
+    /// Specifies the type of bus or I/O (I2C, DAP, GPIO) for this connection.
+    NvOdmIoModule Interface;
+
+    /**
+     * Some buses or I/Os on an application processor have multiple instances,
+     * such as the 3 SPI controllers on AP15, or multiple GPIO ports. This
+     * value specifies to which instance of a multi-instance bus is the
+     * peripheral connected. The instance value should be the same value
+     * passed to the instance parameter in the ODM service APIs (e.g.,
+     * NvOdmI2cOpen()).
+     *
+     * @note For GPIOs, this value refers to the GPIO port.
+     */
+    NvU32 Instance;
+
+    /**
+     * Some buses, such as I2C and SPI, support multiple slave devices on
+     * a single bus, through the use of peripheral addresses and/or chip 
+     * select signals. This value specifies the appropriate address or chip
+     * select required to communicate with the peripheral.
+     *
+     * @note This value differs depending on usage:
+     *       - For GPIOs, this value specifies the GPIO pin.
+     *       - For VDDs, this value is ODM-defined PMU rail ID.
+     *       - For board designs where the LCD bus is connected to a main
+     *       display and sub-display (e.g., a clam-shell cellular phone),
+     *       address 0 should refer to the main panel, and 1 to the sub-panel.
+     */
+    NvU32 Address;
+} NvOdmIoAddress;
+
+/**
+ * Defines the full bus connectivity for peripherals connected to the
+ * application processor.
+ */
+typedef struct 
+{
+    /// The ODM-defined 64-bit GUID that identifies this peripheral.
+    NvU64 Guid;
+
+    /**
+     * The list of all I/Os and buses connecting this peripheral to the AP.
+     * @see NvOdmIoAddress
+     */
+    const NvOdmIoAddress *AddressList;
+
+    /// The number of entries in the \a addressList array.
+    NvU32 NumAddress;
+
+    /// The functionality class of this peripheral.
+    NvOdmPeripheralClass Class;
+} NvOdmPeripheralConnectivity;
+
+
+/// Defines different criteria for searching through the peripheral database.
+typedef enum 
+{
+    /// Searches for peripherals that are members of the specified class.
+    NvOdmPeripheralSearch_PeripheralClass,
+
+    /// Searches for peripherals connected to the specified I/O module.
+    NvOdmPeripheralSearch_IoModule,
+
+    /** 
+     * Searches for peripherals connected to the specified bus instance.
+     *
+     * @note This value will be compared against all entries in \a addressList.
+     */
+    NvOdmPeripheralSearch_Instance,
+
+    /**
+     * Searches for peripherals matching the specified address or chip select.
+     *
+     * @note This value will be compared against all entries in \a addressList.
+     */
+    NvOdmPeripheralSearch_Address,
+
+    NvOdmPeripheralSearch_Num,
+    /** Ignore -- Forces compilers to make 32-bit enums. */
+    NvOdmPeripheralSearch_Force32 = 0x7fffffffUL
+} NvOdmPeripheralSearch;
+
+/** 
+ * Defines the data structure that describes each sub-assembly of the
+ * development platform.  This data is read from EEPROMs on each of the sub-
+ * assemblies, which is saved with the following format:
+ * <pre>
+ *      E-xxxx-yyyy-0zz XN
+ * </pre>
+ *
+ * Where:
+ *
+ * - xxxx is the board ID number 0-9999 (2 byte number) 
+ * - yyyy is the SKU number 0-9999 (2 byte number) 
+ * - zz is the FAB number 0-99 (1 byte number) 
+ * - X is the major revision, (1 byte ASCII character), e.g., 'A', 'B', etc.
+ * - N is the minor revision, (1 byte number, 0 - 9)
+ */
+typedef struct 
+{
+    /// Specifies the board number.
+    NvU16 BoardID;
+
+    /// Specifies the SKU number.
+    NvU16 SKU;
+
+    /// Specifies the FAB number.
+    NvU8 Fab;
+
+    /// Specifies the part revision.
+    NvU8 Revision;
+
+    /// Specifies the minor revision level
+    NvU8 MinorRevision;
+} NvOdmBoardInfo;
+
+/**
+ * Searches through the database of connected peripherals for peripherals
+ * matching the specified search criteria.
+ *
+ * Search criteria are supplied by paired attribute-value lists; if multiple
+ * criteria are specified, the returned peripherals represent the intersection
+ * (boolean AND) of the supplied search criteria.
+ *
+ * This function is expected to be called twice with the same search criteria.
+ * In the first call, \a guidList should be NULL.  The number of peripherals
+ * matching the search criteria will be returned.
+ *
+ * In the second call, \a guidList should point to an array of NvU64s; the GUIDs
+ * of up to \a numGuids peripherals matching the search critiera will be written
+ * to \a guidList. The number of stored GUIDs will be returned.
+ *
+ * @param searchAttrs The array of search attributes (::NvOdmPeripheralSearch).
+ * @param searchVals The array of values for each search attribute.
+ * @param numCriteria The number of entries in the attribute-value lists.
+ * @param guidList The array of output GUIDs. If NULL, no GUIDs are returned.
+ * @param numGuids The number of entries in \a guidList.
+ * @return The number of GUIDs written to \a guidList, or the total number of
+ *          peripherals matching the search criteria if \a guidList is NULL.
+ */
+NvU32
+NvOdmPeripheralEnumerate(
+    const NvOdmPeripheralSearch *searchAttrs,
+    const NvU32 *searchVals,
+    NvU32 numCriteria,
+    NvU64 *guidList,
+    NvU32 numGuids);
+
+/**
+ * Searches through the database of connected peripherals for the peripheral
+ * matching the specified GUID and returns that peripheral's connectivity 
+ * structure.
+ *
+ * @note If the ODM system supports hot-pluggable peripherals (e.g., an 
+ * external TV-out display), the connectivity structure should only be returned
+ * when the peripheral is useable by the NVIDIA driver libraries. If hot-plug
+ * detection is not supported, the peripheral's connectivity structure may
+ * always be returned.
+ *
+ * @see NvOdmPeripheralConnectivity
+ *
+ * @param searchGuid The GUID value of the queried peripheral.
+ *
+ * @return A pointer to the peripheral's bus connectivity structure if a
+ * peripheral matching \a searchGuid is found, or NULL if no peripheral is found.
+ */
+const NvOdmPeripheralConnectivity *
+NvOdmPeripheralGetGuid(NvU64 searchGuid);
+
+/**
+ * Gets the ::NvOdmBoardInfo data structure values for the given board ID.
+ * 
+ * @param BoardId Identifies the board for which the BoardInfo data is to be retrieved.
+ *  @note The \a BoardId is in Binary Encoded Decimal (BCD) format. For example,
+ *  E920 is identified by a \a BoardId of 0x0920 and E9820 would be 0x9820.
+ * @param pBoardInfo A pointer to the location where the requested \a BoardInfo data
+ *  shall be saved.
+ * 
+ * @return NV_TRUE if successful, or NV_FALSE otherwise.
+ */
+NvBool
+NvOdmPeripheralGetBoardInfo(
+    NvU16 BoardId,
+    NvOdmBoardInfo* pBoardInfo);
+
+#if defined(__cplusplus)
+}
+#endif
+
+/** @} */
+
+#endif // INCLUDED_NVODM_QUERY_DISCOVERY_H
diff --git a/arch/arm/mach-tegra/include/nvodm_query_gpio.h b/arch/arm/mach-tegra/include/nvodm_query_gpio.h
new file mode 100644
index 000000000000..dd6461a2483d
--- /dev/null
+++ b/arch/arm/mach-tegra/include/nvodm_query_gpio.h
@@ -0,0 +1,380 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/**
+ * @file
+ * <b>NVIDIA Tegra ODM Kit:
+ *         GPIO Query Interface</b>
+ *
+ * @b Description: Defines the ODM query interface for GPIO pins.
+ */
+
+#ifndef INCLUDED_NVODM_QUERY_GPIO_H
+#define INCLUDED_NVODM_QUERY_GPIO_H
+/**
+ * @defgroup nvodm_gpio GPIO Query Interface
+ * This is the ODM query interface for GPIO configurations.
+ * @ingroup nvodm_query
+ * @{
+ */
+#include "nvcommon.h"
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+/**
+ * Defines GPIO pin groups.
+ */
+typedef enum
+{
+    /// Specifies a NULL display group.
+    NvOdmGpioPinGroup_None = 0,
+
+    /// Specifies a display pin group.
+    NvOdmGpioPinGroup_Display,
+
+    /// Specifies a keypad column pin group--used only if the system uses
+    /// GPIO-based keypad.
+    NvOdmGpioPinGroup_keypadColumns,
+
+    /// Specifies a keypad rows pin group--used only if the system uses
+    /// GPIO-based keypad.
+    NvOdmGpioPinGroup_keypadRows,
+
+    /// Specifies a special key for a keypad--This is used in both KBC based
+    /// keypad and GPIO-based keypad.
+    NvOdmGpioPinGroup_keypadSpecialKeys,
+
+    /// Specifies a pin group representing all the other keypad GPIOs.
+    NvOdmGpioPinGroup_keypadMisc,
+
+    /// Specifies an SDIO pin group. This pin group has 2 instances.
+    /// @note If this value is set, NvOdmQuerySdioInterfaceProperty::IsCardRemovable
+    /// is ignored.
+    NvOdmGpioPinGroup_Sdio,
+
+    /// Specifies an HSMMC pin group.
+    /// @note If this value is set, NvOdmQueryHsmmcInterfaceProperty::IsCardRemovable
+    /// is ignored.
+    NvOdmGpioPinGroup_Hsmmc,
+
+    /// Specifies a USB pin group.
+    NvOdmGpioPinGroup_Usb,
+
+    /// Specifies an IDE function pin group.
+    NvOdmGpioPinGroup_Ide,
+
+    /// Specifies an OEM pin group.
+    NvOdmGpioPinGroup_OEM,
+
+    /// Specifies a test pin group used by the internal tests.
+    NvOdmGpioPinGroup_Test,
+
+    /// Specifies a group used by the external MIO Ethernet adapter.
+    NvOdmGpioPinGroup_MioEthernet,
+
+    /// Deprecated name -- retained for backward compatibility.
+    NvOdmGpioPinGroup_Ethernet = NvOdmGpioPinGroup_MioEthernet,
+
+    /// Specifies a group used for NAND flash write protect.
+    NvOdmGpioPinGroup_NandFlash,
+
+    /// Specifies a group used for scroll wheel pins.
+    NvOdmGpioPinGroup_ScrollWheel,
+
+    /// Specifies a group used for MIO bus control signals.
+    NvOdmGpioPinGroup_Mio,
+
+    /// Specifies a group used for bluetooth control signals.
+    NvOdmGpioPinGroup_Bluetooth,
+
+    /// Specifies a group used for WLAN control signals.
+    NvOdmGpioPinGroup_Wlan,
+
+    /// Specifies a group for HDMI.
+    NvOdmGpioPinGroup_Hdmi,
+
+    /// Specifies a group for CRT.
+    NvOdmGpioPinGroup_Crt,
+
+    /// Specifies a group for SPI.
+    NvOdmGpioPinGroup_SpiEthernet,
+
+    /// Deprecated name -- retained for backward compatibility.
+    NvOdmGpioPinGroup_Spi = NvOdmGpioPinGroup_SpiEthernet,
+
+    /// Specifies a group for Vi.
+    NvOdmGpioPinGroup_Vi,
+
+    /// Specifies a group for DSI.
+    NvOdmGpioPinGroup_Dsi,
+
+    
+    /// Specifies a group for keys used to suspend/resume/shutdown.
+    NvOdmGpioPinGroup_Power,
+
+    /// Specifies a group for keys used to resume from EC keyboard.
+    NvOdmGpioPinGroup_WakeFromECKeyboard,
+
+    /// Specifies a group for Battery
+    NvOdmGpioPinGroup_Battery,
+
+    /// Specifies the total number of pin groups.
+    NvOdmGpioPinGroup_Num,
+    NvOdmGpioPinGroup_Force32 = 0x7FFFFFFF,
+} NvOdmGpioPinGroup;
+
+/**  @name Display GPIO Pins
+ *  Each panel uses some number of GPIO pins for configuring the panel. The
+ *  usage and the number of pins vary from panel to panel. One main board can
+ *  support multiple panels. In such cases, GPIOs used by all the panels must
+ *  be reserved. GPIO pin table exported by display pin group is a set of all
+ *  the panels it supports--one set for each panel. The client of this API is
+ *  the display ODM adaptation. Display ODM adaptation is written once for a
+ *  panel and all the board-specific changes are abstratced in this API.
+ *
+ *  If the ODM implements its own display adaptation, rather than the using the
+ *  display adaptation provided by NVIDIA, there is no need to implement
+ *  display virtual pin map.
+ *
+ *  Please refer to the documentation for the mapping between physical panel
+ *  and panel index used here.
+ */
+/*@{*/
+#define NvOdmGpioPin_DisplayPanel0Pincount   (6)
+#define NvOdmGpioPin_DisplayPanel0Start      (0)
+#define NvOdmGpioPin_DisplayPanel0End        (NvOdmGpioPin_DisplayPanel0Start + NvOdmGpioPin_DisplayPanel0Pincount - 1)
+
+#define NvOdmGpioPin_DisplayPanel1Pincount   (4)
+#define NvOdmGpioPin_DisplayPanel1Start      (NvOdmGpioPin_DisplayPanel0End + 1)
+#define NvOdmGpioPin_DisplayPanel1End        (NvOdmGpioPin_DisplayPanel1Start + NvOdmGpioPin_DisplayPanel1Pincount - 1)
+
+#define NvOdmGpioPin_DisplayPanel2Pincount   (1)
+#define NvOdmGpioPin_DisplayPanel2Start      (NvOdmGpioPin_DisplayPanel1End + 1)
+#define NvOdmGpioPin_DisplayPanel2End        (NvOdmGpioPin_DisplayPanel2Start + NvOdmGpioPin_DisplayPanel2Pincount - 1)
+
+#define NvOdmGpioPin_DisplayPanel3Pincount   (21)
+#define NvOdmGpioPin_DisplayPanel3Start      (NvOdmGpioPin_DisplayPanel2End + 1)
+#define NvOdmGpioPin_DisplayPanel3End        (NvOdmGpioPin_DisplayPanel3Start + NvOdmGpioPin_DisplayPanel3Pincount - 1)
+
+#define NvOdmGpioPin_DisplayPanel4Pincount   (1)
+#define NvOdmGpioPin_DisplayPanel4Start      (NvOdmGpioPin_DisplayPanel3End + 1)
+
+#define NvOdmGpioPin_DisplayPanel4End        (NvOdmGpioPin_DisplayPanel4Start + NvOdmGpioPin_DisplayPanel4Pincount - 1)
+
+#define NvOdmGpioPin_DisplayPanel5Pincount   (4)
+#define NvOdmGpioPin_DisplayPanel5Start      (NvOdmGpioPin_DisplayPanel4End + 1)
+
+#define NvOdmGpioPin_DisplayPanel5End        (NvOdmGpioPin_DisplayPanel5Start + NvOdmGpioPin_DisplayPanel5Pincount - 1)
+
+#define NvOdmGpioPin_DisplayPinCount         (NvOdmGpioPin_DisplayPanel5End + 1)
+
+/*@}*/
+/**@name Keypad Virtual Pins */
+/*@{*/
+/** Max GPIOs that can be used for as rows in GPIO-based keypad. For chips
+ * later than AP15, silicon supports a dedicated KBC controller.
+ * If using GPIO-based keypad driver, it has the upper limit on the number of
+ * the rows defined by this macro.
+ * When the NvOdmQueryGpioPinMap() is called with virtual pin group of
+ * ::NvOdmGpioPinGroup_keypadColumns, ODM should return an array
+ * of GPIOs mapped for column keys. Array size should not be more than 32. This
+ * upper limit is just for saftey checks and in no sense inidicates the
+ * limitations of the NVIDIA driver. */
+#define NvOdmGpioPin_keypadColumnsPinCountMax       (32)
+
+/** Max GPIOs that can be used for as rows in GPIO  based keypad. For chips
+ * later than AP15, silicon supports a dedicated KBC controller.
+ * If using GPIO-based keypad driver, it has the upper limit on the number of
+ * the rows defined by this macro.
+ * When NvOdmQueryGpioPinMap() is called with virtual pin group of
+ * ::NvOdmGpioPinGroup_keypadRows, ODM should return a array
+ * of GPIOs mapped for row keys. Array size should not be more than
+ * ::NvOdmGpioPin_keypadRowsPinCountMax.
+ * This upper limit is just for saftey checks and does not inidicate the
+ * limitations of the NVIDIA driver. */
+#define NvOdmGpioPin_keypadRowsPinCountMax          (32)
+
+/** Max GPIOs that can be used for the special keys. Driver is limited by this
+ * number of special keys. When NvOdmQueryGpioPinMap() is called with virtual
+ * pin group of ::NvOdmGpioPinGroup_keypadSpecialKeys, ODM should return an array
+ * of GPIOs mapped for special keys. Array size should not be more than 32. This
+ * upper limit is just for saftey checks and in no sense inidicates the
+ * limitations of the NVIDIA driver. */
+#define NvOdmGpioPin_keypadSpecialKeysCountMax      (32)
+
+/*@}*/
+/** @name Misc Keypad GPIOs */
+/*@{*/
+/** GPIO used to control illuminating the keypad. This GPIO line is set to
+ * active state when a key is pressed. */
+#define NvOdmGpioPin_keypadMiscBackLight         (0)
+/** When this key is in pressed state all the inputs are disabled. */
+#define NvOdmGpioPin_keypadMiscHoldKey           (NvOdmGpioPin_keypadMiscBackLight + 1)
+/** Total count pin count for keypad pin group */
+#define NvOdmGpioPin_keypadMiscPinCount          (NvOdmGpioPin_keypadMiscHoldKey + 1)
+
+/*@}*/
+/** @name HSMMC Virtual Pins */
+/*@{*/
+#define NvOdmGpioPin_HsmmcCardDetect        (0)
+#define NvOdmGpioPin_HsmmcWriteProtect      (NvOdmGpioPin_HsmmcCardDetect + 1)
+#define NvOdmGpioPin_HsmmcPinCount          (NvOdmGpioPin_HsmmcWriteProtect + 1)
+
+/*@}*/
+/** @name SDIO Virtual Pins */
+/*@{*/
+#define NvOdmGpioPin_SdioCardDetect         (0)
+#define NvOdmGpioPin_SdioWriteProtect       (NvOdmGpioPin_SdioCardDetect +1)
+#define NvOdmGpioPin_SdioPinCount           (NvOdmGpioPin_SdioWriteProtect + 1)
+
+/*@}*/
+/** @name USB GPIO Pins */
+/*@{*/
+#define NvOdmGpioPin_UsbCableId    (0)
+#define NvOdmGpioPin_UsbPinCount           (NvOdmGpioPin_UsbCableId + 1)
+
+/*@}*/
+/** @name IDE Function GPIO Pins */
+/*@{*/
+#define NvOdmGpioPin_IdePowerEnable (0)
+#define NvOdmGpioPin_IdePinCount (NvOdmGpioPin_IdePowerEnable + 1)
+
+/*@}*/
+/** @name Test Pin Groups */
+/*@{*/
+#define NvOdmGpioPin_Test1                  (0)
+#define NvOdmGpioPin_Test2                  (1)
+#define NvOdmGpioPin_TestPinCount           (NvOdmGpioPin_Test2 + 1)
+
+/*@}*/
+/** @name External Ethernet Adapter Pin Groups */
+/*@{*/
+#define NvOdmGpioPin_Ethernet               (0)
+#define NvOdmGpioPin_EthernetCount          (NvOdmGpioPin_Ethernet + 1)
+
+/*@}*/
+/** @name NAND Flash WP Pin Groups */
+/*@{*/
+#define NvOdmGpioPin_NandFlash              (0)
+#define NvOdmGpioPin_NandFlashCount         (NvOdmGpioPin_NandFlash + 1)
+
+/*@}*/
+/** @name Scroll Wheel Pin Groups */
+/*@{*/
+#define NvOdmGpioPin_ScrollWheelInputPin1   (0)
+#define NvOdmGpioPin_ScrollWheelOnOff       (NvOdmGpioPin_ScrollWheelInputPin1 + 1)
+#define NvOdmGpioPin_ScrollWheelSelectPin   (NvOdmGpioPin_ScrollWheelOnOff + 1)
+#define NvOdmGpioPin_ScrollWheelInputPin2   (NvOdmGpioPin_ScrollWheelSelectPin + 1)
+/*@}*/
+/** @name Bluetooth Control Pin Groups */
+/*@{*/
+#define NvOdmGpioPin_Bluetooth   (0)
+#define NvOdmGpioPin_BluetoothReset        (NvOdmGpioPin_Bluetooth + 1)
+
+/*@}*/
+/** @name WLAN Control Pin Groups */
+/*@{*/
+#define NvOdmGpioPin_Wlan   (0)
+#define NvOdmGpioPin_WlanPower             (NvOdmGpioPin_Wlan + 1)
+#define NvOdmGpioPin_WlanReset             (NvOdmGpioPin_WlanPower + 1)
+
+/*@}*/
+/** @name DSI Pin Groups */
+/*@{*/
+#define NvOdmGpioPin_DsiLcdResetId               (0)
+#define NvOdmGpioPin_DsiLcdTeId          (NvOdmGpioPin_DsiLcdResetId + 1)
+#define NvOdmGpioPin_DsiLcdHsIntId          (NvOdmGpioPin_DsiLcdTeId + 1)
+/*@}*/
+
+/**
+ *  Defines the active state of the pin. For example, a USB cable connect pin
+ *  might be configured to have a active state of low when the cable is
+ *  connetced. On some boards the same pin can be configured as active high.
+ *  This enum abstracts this information.
+ */
+typedef enum
+{
+    NvOdmGpioPinActiveState_Low = 0,
+    NvOdmGpioPinActiveState_High,
+    NvOdmGpioPinActiveState_Force32 = 0x7FFFFFFF,
+} NvOdmGpioPinActiveState;
+
+/**
+ * Holds the GPIO pin information.
+ */
+typedef struct  NvOdmGpioPinInfo_t {
+    /// Holds the physical port mapped to the virtual pin group \c vGroup/virtual pin \c vPin.
+    NvU32 Port;
+    /// Holds the physical pin mapped to the virtual pin group \c vGroup/virtual pin \c vPin.
+    NvU32 Pin;
+    /// Holds the active state of the pin. This is valid only for the input pins. Active
+    /// state is defined by each pin. For example, for a USB cable connect virtual pin,
+    /// the active state is when the cable is connected.
+    NvOdmGpioPinActiveState activeState;
+} NvOdmGpioPinInfo;
+
+#define NVODM_GPIO_INVALID_PORT 0xFF
+#define NVODM_GPIO_INVALID_PIN  0xFF
+
+/// Connected imager devices use the camera reserved GPIOs.
+/// Valid GPIO pins are between 0 and 6, and map to the external
+/// pins referred to as VGP0 thru VGP6, with the exception of 1 and 2.
+/// VGP1 and VGP2 are used for the camera I2C, so the VD10 and VD11 pins
+/// are substituted, via this interface, so as to avoid accidental use.
+#define NVODM_GPIO_CAMERA_PORT  0xFE
+
+/**
+ * Gets the pin mappings for a virtual group. For optimal access the table should be
+ * sorted using the vPin value.
+ *
+ * @see NvOdmGpioPinGroup
+ *
+ * @param Group The pin group for which the query is being made.
+ * @param instance The instance of the pin group. For example, there are 2 instances
+ * of the SDIO pin group.
+ * @param count A pointer to the count of entires in the ::NvOdmGpioPinInfo.
+ *
+ * @return A const pointer to the pin info table if the pin group
+ * has valid GPIO configuration.
+ */
+const NvOdmGpioPinInfo *NvOdmQueryGpioPinMap(NvOdmGpioPinGroup Group, NvU32 instance, NvU32 *count);
+
+#if defined(__cplusplus)
+}
+#endif
+
+/** @} */
+
+#endif  // INCLUDED_NVODM_QUERY_GPIO_H
diff --git a/arch/arm/mach-tegra/include/nvodm_query_kbc.h b/arch/arm/mach-tegra/include/nvodm_query_kbc.h
new file mode 100644
index 000000000000..f8078961978e
--- /dev/null
+++ b/arch/arm/mach-tegra/include/nvodm_query_kbc.h
@@ -0,0 +1,130 @@
+/*
+ * Copyright (c) 2006-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/** 
+ * @file
+ * <b>NVIDIA Tegra ODM Kit:
+ *         Keyboard Controller Interface</b>
+ *
+ * @b Description: Defines the ODM query interface for NVIDIA keyboard 
+ *                 controller (KBC) adaptation.
+ * 
+ */
+
+#ifndef INCLUDED_NVODM_QUERY_KBC_H
+#define INCLUDED_NVODM_QUERY_KBC_H
+
+#include "nvcommon.h"
+
+/**
+ * @defgroup nvodm_query_kbc Keyboard Controller Query Interface
+ * This is the keyboard controller (KBC) ODM Query interface.
+ * See also the \link nvodm_kbc KBC ODM Adaptation Interface\endlink.
+ * @ingroup nvodm_query
+ * @{
+ */
+
+/**
+ * Defines the parameters associated with this device.
+ */
+typedef enum
+{
+    NvOdmKbcParameter_NumOfRows=1,
+    NvOdmKbcParameter_NumOfColumns,
+    NvOdmKbcParameter_DebounceTime,
+    NvOdmKbcParameter_RepeatCycleTime,
+    NvOdmKbcParameter_Force32 = 0x7FFFFFFF
+} NvOdmKbcParameter;
+
+/**
+ * Queries the peripheral device for its current settings.
+ * 
+ * @see NvOdmKbcParameter
+ *
+ * @param param  Specifies which parameter value to get.
+ * @param sizeOfValue  The length of the parameter data (in bytes).
+ * @param value  A pointer to the location where the requested parameter shall
+ *     be stored.
+ * 
+ */
+void 
+NvOdmKbcGetParameter(
+        NvOdmKbcParameter param,
+        NvU32 sizeOfValue,
+        void *value);
+
+/**
+ * Gets the key code depending upon the row and column values.
+ * 
+ * @param Row  The value of the row.
+ * @param Column The value of the column.
+ * @param RowCount The number of the rows present in the keypad matrix.
+ * @param ColumnCount The number of the columns present in the keypad matrix.
+ * 
+ * @return The appropriate key code.
+ */
+NvU32 
+NvOdmKbcGetKeyCode(
+    NvU32 Row, 
+    NvU32 Column,
+    NvU32 RowCount,
+    NvU32 ColumnCount);
+
+/**
+ * Queries if wake-up only on selected keys is enabled for WPC-like
+ * configurations. If it is enabled, returns the pointers to the static array
+ * containing the row and columns numbers. If this is enabled and \a NumOfKeys
+ * selected is zero, all the keys are disabled for wake-up when system is
+ * suspended.
+ * 
+ * @note The selected keys must not be a configuration of type 1x1, 1x2, etc. 
+ * In other words, a minimum of two rows must be enabled due to hardware
+ * limitations.
+ *
+ * @param pRowNumber A pointer to the static array containing the row 
+ *                   numbers of the keys.
+ * @param pColNumber A pointer to the static array containing the column 
+ *                   numbers of the keys.
+ * @param NumOfKeys A pointer to the number of keys that must be enabled.
+ *                  This indicates the number of elements in the arrays pointer by
+ *                   \a pRowNumber and \a pColNumber.
+ * @return NV_TRUE if successful, or NV_FALSE otherwise.
+ */
+NvBool
+NvOdmKbcIsSelectKeysWkUpEnabled(
+    NvU32 **pRowNumber,
+    NvU32 **pColNumber,
+    NvU32 *NumOfKeys);
+
+/** @} */
+#endif // INCLUDED_NVODM_QUERY_KBC_H
+
diff --git a/arch/arm/mach-tegra/include/nvodm_query_memc.h b/arch/arm/mach-tegra/include/nvodm_query_memc.h
new file mode 100644
index 000000000000..57dfae9afb2d
--- /dev/null
+++ b/arch/arm/mach-tegra/include/nvodm_query_memc.h
@@ -0,0 +1,251 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/**
+ * @file
+ * <b>NVIDIA Tegra ODM Kit:
+ *         Memory Controller Query Interface</b>
+ *
+ * @b Description: Defines the ODM query interface for Memory Controller.
+ */
+
+#ifndef INCLUDED_NVODM_QUERY_MEMC_H
+#define INCLUDED_NVODM_QUERY_MEMC_H
+
+/**
+ * @defgroup nvodm_memc Memory Controller Query Interface
+ * This is the ODM query interface for memory controller.
+ * @ingroup nvodm_query
+ * @{
+ */
+
+#include "nvcommon.h"
+#include "nvodm_query.h"
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+/**
+ * Holds the configuration parameters for asynchronous memory like NOR flash
+ * or Memory Mapped I/O (MIO).
+ */
+
+typedef struct
+{
+    /// Holds TRUE for enabling access time extension using ROM busy pin.
+    NvBool isRomBusyEnable;
+
+    /// Holds the dead time in nano seconds between the end of a write access and
+    /// the start of the following access (write or read) for NOR/MIO memory.
+    NvU32 WriteDeadTime;
+
+    /// Holds the access time in nano seconds for which write signal is asserted
+    /// during a write access for MIO/NOR memory.
+    NvU32 WriteAccessTime;
+
+    /// Holds the dead time in nano seconds between the end of a read access and
+    /// the start of the following access (write or read) for MIO/NOR memory.
+    NvU32 ReadDeadTime;
+
+    /// Holds the access time in nano seconds for which read signal is asserted
+    /// during a read access.
+    NvU32 ReadAccessTime;
+
+} NvOdmAsynchMemConfig;
+
+/**
+ * Holds synchronous memory (SDRAM) controller configuration parameters for the
+ * specified SDRAM frequency and controller core voltage. This structure is
+ * assigned fixed revision 1.0.
+ */
+typedef struct NvOdmSdramControllerConfigRec
+{
+    /// Holds the SDRAM frequency in kHz.
+    NvU32 SdramKHz;
+
+    /// Holds minimum core voltage in mV for memory controller operations at
+    /// the specified SDRAM frequency. Actual core voltage can be set higher by
+    /// DVFS depending on the operation requirements for other SoC modules.
+    NvU32 EmcCoreVoltageMv;
+ 
+    /// Holds the memory controller timing parameter 0.
+    NvU32 EmcTiming0;
+ 
+    /// Holds the memory controller timing parameter 1.
+    NvU32 EmcTiming1;
+ 
+    /// Holds the memory controller timing parameter 2.
+    NvU32 EmcTiming2;
+ 
+    /// Holds the memory controller timing parameter 3.
+    NvU32 EmcTiming3;
+ 
+    /// Holds the memory controller timing parameter 4.
+    NvU32 EmcTiming4;
+ 
+    /// Holds the memory controller timing parameter 5.
+    NvU32 EmcTiming5;
+ 
+    /// Holds the memory controller FBIO configuration parameter 6.
+    NvU32 EmcFbioCfg6;
+ 
+    /// Holds the memory controller FBIO QSIB delay parameter.
+    NvU32 EmcFbioDqsibDly;
+ 
+    /// Holds the emory controller FBIO QUSE delay parameter.
+    NvU32 EmcFbioQuseDly;
+} NvOdmSdramControllerConfig;
+
+/// Defines revision for basic memory controller configuration structure,
+/// i.e., 0x10 is Rev 1.0.
+#define NV_EMC_BASIC_REV    (0x10)
+
+/// Defines maximum number of advanced memory controller timing parameters.
+#define NV_EMC_ADV_PARAM_NUM_MAX    (50)
+
+/**
+ * Holds synchronous memory (SDRAM) advanced controller configuration
+ * parameters for the specified SDRAM frequency and controller core voltage.
+ * The revision of this structure is started with 2.0, and it is embedded as
+ * the structure field.
+ */
+typedef struct NvOdmSdramControllerConfigAdvRec
+{
+    /// Holds revision of this structure, e.g., 0x20 is Rev 2.0.
+    NvU32 Revision;
+
+    /// Holds the SDRAM frequency in kHz.
+    NvU32 SdramKHz;
+
+    /// Holds minimum core voltage in mV for memory controller operations at
+    /// the specified SDRAM frequency. Actual core voltage can be set higher by
+    /// DVFS depending on the operation requirements for other SoC modules.
+    NvU32 EmcCoreVoltageMv;
+
+    /// Holds the number of advanced memory controller timing parameters.
+    NvU32 EmcTimingParamNum;
+ 
+    /// Holds the advanced memory controller timing parameters.
+    NvU32 EmcTimingParameters[NV_EMC_ADV_PARAM_NUM_MAX];
+} NvOdmSdramControllerConfigAdv;
+
+/**
+ * Gets the device memory controller configuration.
+ *
+ * @note This function is called early from the boot process where
+ * global variables are not yet valid. Care must be taken not to
+ * use global variables in the implementation of this function.
+ *
+ * @note The implementation of this function must not make reference to
+ * any global or static variables of any kind whatsoever.
+ *
+ * @see NvOdmAsynchMemConfig
+ *
+ * @param ChipSelect The chip select for which configuration
+ * is required:
+ * - 0 means chip select A
+ * - 1 means chip select B
+ * - 2 means chip select C
+ * - and so on.
+ *
+ * @param pMemConfig A pointer to the returned NOR memory configuration.
+ *
+ * @return NV_TRUE if successful, or NV_FALSE otherwise.
+ *
+ */
+NvBool NvOdmQueryAsynchMemConfig(NvU32 ChipSelect, NvOdmAsynchMemConfig *pMemConfig);
+
+
+/**
+ * Gets the configuration table that provides SDRAM controller parameters for
+ * the selected set of SDRAM frequencies and controller core voltages. This
+ * table is used by the memory controller DVFS.
+ * 
+ * @sa NvOdmSdramControllerConfig structure description for the format of each
+ * table entry, revision 1.0.
+ * @sa NvOdmSdramControllerConfigAdv structure description for the format of
+ * each table entry, revision 2.0.
+ * 
+ * @note The maximum scaled SDRAM frequency Fmax is limited by boot configuration
+ * of memory:
+ * <pre>
+ *    PLL - PLLM: Fmax = (PLLM boot output frequency)/2 
+ * </pre>
+ * The minimum scaled SDRAM frequency is fixed as
+ * <pre>
+ *    Fmin = 12MHz
+ * </pre>
+ *
+ * @par SDRAM Frequency Ladders
+ * 
+ * Revision 1.0 - Only entries for Fmax and evenly
+ * divided from Fmax SDRAM frequencies above Fmin are used by DVFS (e.g. Fmax,
+ * Fmax/2, Fmax/4, Fmax/6, etc). All other entries are ignored. Hence, one
+ * table can contain entries for all different PLLM configurations used for the
+ * particular ODM platform, and DVFS will automatically select the frequency ladder
+ * based on the boot settings. For example, the table can mix entries for Fmax
+ * = 166MHz ladder (166/83/41.5/27.6) and Fmax = 133MHz ladder (133/66.5/33.25/
+ * 21.16). The table is not required to be sorted in any way.
+ * 
+ * Revision 2.0 - Only entries for Fmax and .... 
+ * ladders 
+ * 
+ * The memory controller DVFS is enabled, provided all of the following
+ * conditions are true:
+ * - This function returns a non-NULL pointer to the table.
+ * - The table includes an entry for Fmax SDRAM frequency.
+ * - The table includes an entry for boot SDRAM frequency (if boot configuration
+ * utilizes EMC divider to set initial SDRAM frequency different from Fmax).
+ * This condition is applicable only to Revision 1.0 configuration.
+ * If any of the above conditions are not met, memory controller DVFS will be
+ * disabled and boot SDRAM configuration is preserved during run time.
+ * 
+ * @param pEntries A pointer to a variable which this function sets to the
+ * number of entires in the configuration table.
+ * @param pRevision A pointer to a variable which this function sets to the
+ * revision number of the configuration table entry structure.
+ *
+ * @return A const pointer to the configuration table, or NULL if EMC DVFS
+ *   is disabled.
+ */
+const void*
+NvOdmQuerySdramControllerConfigGet(NvU32 *pEntries, NvU32 *pRevision); 
+
+#if defined(__cplusplus)
+}
+#endif
+
+/** @} */
+
+#endif // INCLUDED_NVODM_QUERY_MEMC_H
diff --git a/arch/arm/mach-tegra/include/nvodm_query_nand.h b/arch/arm/mach-tegra/include/nvodm_query_nand.h
new file mode 100644
index 000000000000..0b8964844895
--- /dev/null
+++ b/arch/arm/mach-tegra/include/nvodm_query_nand.h
@@ -0,0 +1,332 @@
+/*
+ * Copyright (c) 2006-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/**
+ * @file
+ * <b>NVIDIA Tegra ODM Kit:
+ *         NAND Memory Query Interface</b>
+ *
+ * @b Description: Defines the ODM query interface for NVIDIA NAND memory adaptation.
+ *
+ */
+#ifndef INCLUDED_NVODM_QUERY_NAND_H
+#define INCLUDED_NVODM_QUERY_NAND_H
+
+#include "nvcommon.h"
+#include "nvodm_modules.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/**
+ * @defgroup nvodm_query_Nand NAND Memory Query Interface
+ * This is the ODM query interface for NAND configurations.
+ * @ingroup nvodm_query
+ * @{
+ */
+
+#define FLASH_TYPE_SHIFT 16
+#define DEVICE_SHIFT 8
+#define FOURTH_ID_SHIFT 24
+/**
+ *  Defines the list of various capabilities of the NAND devices.
+ */
+typedef enum
+{
+    /// Specifies detected NAND device has only one plane; interleave not
+    /// supported.
+    SINGLE_PLANE,
+    /// Specifies detected NAND device has only one plane; but interleave is
+    /// supported for page programming.
+    SINGLE_PLANE_INTERLEAVE,
+    /// Specifies all types of multiplane capabilities should be declared after
+    /// this.
+    MULTI_PLANE,
+    /// Specifies detected NAND device has multiple planes, and each plane is
+    /// formed with alternate blocks from each bank.
+    MULTIPLANE_ALT_BLOCK,
+    /// Specifies detected NAND device has multiple planes, and each plane is
+    /// formed with sequential blocks from each bank.
+    MULTIPLANE_ALT_PLANE,
+    /// Specifies detected NAND device has multiple planes, and each plane is
+    /// formed with alternate blocks from each bank. Interleaving operation is
+    /// supported across the banks.
+    MULTIPLANE_ALT_BLOCK_INTERLEAVE,
+    /// Specifies detected NAND device has multiple planes, and each plane is
+    /// formed with sequential blocks from each bank. Interleaving operation is
+    /// supported across the banks.
+    MULTIPLANE_ALT_PLANE_INTERLEAVE
+}NvOdmNandInterleaveCapability;
+
+/**
+ * Specifies the NAND Flash type.
+ */
+typedef enum
+{
+    /// Specifies NAND flash type is not known.
+    NvOdmNandFlashType_UnKnown,
+    /// Specifies SLC NAND flash type.
+    NvOdmNandFlashType_Slc,
+    /// Specifies MLC NAND flash type.
+    NvOdmNandFlashType_Mlc,
+    /// Ignore. Forces compilers to make 32-bit enums.
+    NvOdmNandFlashType_Force32 = 0x7FFFFFFF
+}NvOdmNandFlashType;
+
+/// Defines the type of algorithm for error-correcting code (ECC).
+typedef enum
+{
+    /// Specifies Hamming ECC.
+    NvOdmNandECCAlgorithm_Hamming = 0,
+    /// Specifies Reed-Solomon ECC.
+    NvOdmNandECCAlgorithm_ReedSolomon,
+    /// Specifies BCH ECC.
+    NvOdmNandECCAlgorithm_BCH,
+    /// Specifies to disable ECC, if the the NAND flash part being used
+    /// has error correction capability within itself.
+    NvOdmNandECCAlgorithm_NoEcc,
+    /// Ignore. Forces compilers to make 32-bit enums.
+    NvOdmNandECCAlgorithm_Force32 = 0x7FFFFFFF
+}NvOdmNandECCAlgorithm;
+
+/// Defines the number of skip spare bytes.
+typedef enum
+{
+    NvOdmNandSkipSpareBytes_0,
+    NvOdmNandSkipSpareBytes_4,
+    NvOdmNandSkipSpareBytes_8,
+    NvOdmNandSkipSpareBytes_12,
+    NvOdmNandSkipSpareBytes_16,
+    NvOdmNandSkipSpareBytes_Force32 = 0x7FFFFFFF
+}NvOdmNandSkipSpareBytes;
+
+/**
+ * Defines the number of symbol errors correctable per each 512 continous
+ * bytes of the flash area when Reed-Solomon algorithm is chosen for error
+ * correction. Here each symbol is of 9 contiguous bits in the flash.
+ *
+ * @note Based on the chosen number of errors correctable, parity bytes
+ * required to be stored in the spare area of NAND flash will vary. For 4
+ * correctable errors the number of parity bytes required are 36 bytes.
+ * Similarly, for 6 and 8 symbol error correction, 56 and 72 parity bytes
+ * must be stored in the spare area. As we also must use the spare area for
+ * bad block management and wear levelling, we need to have 12 bytes for that
+ * in the spare area. So, the spare area size should be able to accommodate
+ * parity bytes and bytes required for bad block management.
+ * Hence fill this parameter based on the spare area size of the flash being
+ * used.
+ */
+typedef enum
+{
+    /// Specifies 4 symbol error correction per 512 byte area of NAND flash.
+    NvOdmNandNumberOfCorrectableSymbolErrors_Four,
+    /// Specifies 6 symbol error correction per 512 byte area of NAND flash.
+    NvOdmNandNumberOfCorrectableSymbolErrors_Six,
+    /// Specifies 8 symbol error correction per 512 byte area of NAND flash.
+    NvOdmNandNumberOfCorrectableSymbolErrors_Eight,
+    /// Ignore. Forces compilers to make 32-bit enums.
+    NvOdmNandNumberOfCorrectableSymbolErrors_Force32 = 0x7FFFFFFF
+}NvOdmNandNumberOfCorrectableSymbolErrors;
+
+/// Defines the NAND flash command set.
+typedef enum
+{
+    /// Specifies to read command 1st cycle.
+    NvOdmNandCommandList_Read = 0x00,
+    /// Specifies to read command start 2nd cycle.
+    NvOdmNandCommandList_Read_Start = 0x30,
+    /// Specifies to read copy back 1st cycle.
+    NvOdmNandCommandList_Read_Cpy_Bck = 0x00,
+    /// Specifies to read copy back start 2nd cycle.
+    NvOdmNandCommandList_Read_Cpy_Bck_Start = 0x35,
+    /// Specifies to cache the read command.
+    NvOdmNandCommandList_Cache_Read = 0x31,
+    /// Specifies the last command to end cache read operation.
+    NvOdmNandCommandList_Cache_ReadEnd = 0x3F,
+    /// Specifies to read device ID.
+    NvOdmNandCommandList_Read_Id = 0x90,
+    /// Specifies to reset the device.
+    NvOdmNandCommandList_Reset = 0xFF,
+    /// Specifies to program/write page 1st cycle.
+    NvOdmNandCommandList_Page_Program = 0x80,
+    /// Specifies to program/write page 2nd cycle.
+    NvOdmNandCommandList_Page_Program_Start = 0x10,
+    /// Specifies to cache program 1st cycle.
+    NvOdmNandCommandList_Cache_Program = 0x80,
+    /// Specifies to cache program 2nd cycle.
+    NvOdmNandCommandList_Cache_Program_Start = 0x15,
+    /// Specifies to erase block.
+    NvOdmNandCommandList_Block_Erase = 0x60,
+    /// Specifies erase block start.
+    NvOdmNandCommandList_Block_Erase_Start = 0xD0,
+    /// Specifies copy back data.
+    NvOdmNandCommandList_Copy_Back = 0x85,
+    /// Specifies random data write.
+    NvOdmNandCommandList_Random_Data_Input = 0x85,
+    /// Specifies random data read.
+    NvOdmNandCommandList_Random_Data_Out = 0x05,
+    /// Specifies random data read start.
+    NvOdmNandCommandList_Random_Data_Out_Start = 0xE0,
+    /// Specifies multi page command.
+    NvOdmNandCommandList_MultiPage = 0x11,
+    NvOdmNandCommandList_MultiPageProgPlane2 = 0x81,
+    /// Specifies read device status.
+    NvOdmNandCommandList_Status = 0x70,
+    /// Specifies read status of chip 1.
+    NvOdmNandCommandList_Status_1 = 0xF1,
+    /// Specifies read status of chip 2.
+    NvOdmNandCommandList_Status_2 = 0xF2,
+    /// Specifies ONFI read ID command.
+    NvOdmNandCommandList_ONFIReadId = 0xEC,
+    /// Ignore -- Forces compilers to make 32-bit enums.
+    NvOdmNandCommandList_Force32 = 0x7FFFFFFF
+}NvOdmNandCommandList;
+
+/// Defines NAND flash types (42nm NAND or normal NAND).
+typedef enum
+{
+    /// Specifies conventional NAND flash (50nm, 60nm).
+    NvOdmNandDeviceType_Type1,
+    /// Specifies 42nm technology NAND flash.
+    NvOdmNandDeviceType_Type2,
+    NvOdmNandDeviceType_Force32 = 0x7FFFFFFF
+}NvOdmNandDeviceType;
+
+/**
+ * This structure holds various NAND flash parameters.
+ */
+typedef struct NvOdmNandFlashParamsRec
+{
+    /// Holds the vendor ID code.
+    NvU8 VendorId;
+    /// Holds the device ID code.
+    NvU8 DeviceId;
+    /// Holds the device type.
+    NvOdmNandFlashType NandType;
+    /// Holds the information whether the used NAND flash supports internal
+    /// copy back command.
+    NvBool IsCopyBackCommandSupported;
+    /// Holds the information whether the used NAND flash supports cache
+    /// write operations.
+    NvBool IsCacheWriteSupported;
+    /// Holds the size of the flash (in megabytes).
+    NvU32 CapacityInMB;
+    /// Holds the Zones per flash device--minimum value possible is 1.
+    /// Zone is a group of contiguous blocks among which internal copy back can
+    /// be performed, if the chip supports copy-back operation.
+    /// Zone is also referred as plane or district by some flashes.
+    NvU32 ZonesPerDevice;
+    /// Holds the blocks per Zone of the flash.
+    NvU32 BlocksPerZone;
+    /// Holds the expected flash response for READ STATUS command
+    /// when requested previous operation is successful.
+    NvU32 OperationSuccessStatus;
+    /// Holds the interleave mechanism supported by the flash.
+    NvOdmNandInterleaveCapability InterleaveCapability;
+    /// Holds the ECC algorithm to be used for error correction.
+    NvOdmNandECCAlgorithm EccAlgorithm;
+    /// Holds the number of errors that can be corrected per 512 byte area of NAND
+    /// flash using Reed-Solomon algorithm.
+    NvOdmNandNumberOfCorrectableSymbolErrors ErrorsCorrectable;
+    /// Holds the number of bytes to be skipped in spare area, starting from
+    /// spare byte 0.
+    NvOdmNandSkipSpareBytes SkippedSpareBytes;
+    /// Flash timing parameters, which are all to be filled in nSec.
+    /// Holds read pulse width in nSec.
+    NvU32 TRP;
+    /// Holds read hold delay in nSec.
+    NvU32 TRH;
+    /// Holds write pulse width in nSec.
+    NvU32 TWP;
+    /// Holds write hold delay in nSec.
+    NvU32 TWH;
+    /// Holds CE# setup time.
+    NvU32 TCS;
+    /// Holds write hold to read delay in nSec.
+    NvU32 TWHR;
+    /// Holds WE to BSY set wait time in nSec.
+    NvU32 TWB;
+    /// Holds read pulse width for PIO read commands.
+    NvU32 TREA;
+    /// Holds time from final rising edge of WE of addrress input to
+    /// first rising edge of WE for data input.
+    NvU32 TADL;
+    /*
+        tCLH, tALH, tCH, tCLS, tALS params are also
+        required to calculate tCS value.
+    */
+    /// Holds CLE setup time.
+    NvU32 TCLS;
+    /// Holds CLE hold time.
+    NvU32 TCLH;
+    /// Holds CE# hold time.
+    NvU32 TCH;
+    /// Holds ALE setup time.
+    NvU32 TALS;
+    /// Holds ALE hold time.
+    NvU32 TALH;
+    /// Holds Read Cycle hold time.
+    NvU32 TRC;
+    /// Holds Write Cycle hold time.
+    NvU32 TWC;
+    /// Holds CLE High to Read Delay Some data sheets refer it as TCLR.
+    NvU32 TCR;
+    /// Holds ALE High to Read Delay 
+    NvU32 TAR;
+    /// Holds RBSY High to Read Delay 
+    NvU32 TRR;
+    /// Describes whether the NAND is 42 nm NAND or normal.
+    NvOdmNandDeviceType NandDeviceType;
+
+    /// Holds the 4th ID data of the read ID command (as given by the data sheet)
+    /// here to differentiate between 42 nm and other flashes that have the
+    /// same ManufaturerId, DevId, and Flash type (e.g., K9LBG08U0M & K9LBG08U0D).
+    NvU8 ReadIdFourthByte;
+}NvOdmNandFlashParams;
+
+/**
+ * Gets the NAND flash device information.
+ *
+ * @param ReadID The NAND flash ID value that is read from the flash.
+ * @return NULL if unsuccessful, or the appropriate flash params structure.
+ */
+NvOdmNandFlashParams *NvOdmNandGetFlashInfo (NvU32 ReadID);
+
+/** @}*/
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif  // INCLUDED_NVODM_QUERY_NAND_H
+
diff --git a/arch/arm/mach-tegra/include/nvodm_query_pinmux.h b/arch/arm/mach-tegra/include/nvodm_query_pinmux.h
new file mode 100644
index 000000000000..5365201b8457
--- /dev/null
+++ b/arch/arm/mach-tegra/include/nvodm_query_pinmux.h
@@ -0,0 +1,534 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/**
+ * @file
+ * <b>NVIDIA Tegra ODM Kit:
+ *         Pin-Mux Query Interface</b>
+ *
+ * @b Description: Defines the ODM query interface for Pin-Mux configurations.
+ */
+
+#ifndef INCLUDED_NVODM_QUERY_PINMUX_H
+#define INCLUDED_NVODM_QUERY_PINMUX_H
+
+/**
+ * @defgroup nvodm_pinmux PinMux Query Interface
+ * This is the ODM query interface for pin mux configurations.
+ * 
+ * Pin-mux configurations are logical definitions. Each I/O module defines
+ * their configurations (simply an enum), which may be found in the ODM 
+ * adaptation headers.
+ * 
+ * Every platform defines a unique set of configuration tables. There exists a
+ * configuration table for each I/O module and each entry in the table
+ * represents the configuration for an I/O module instance.
+ * 
+ * This interface is used to query the pin-mux configuration tables defined by
+ * the ODM, because these configurations are platform-specific.
+ * @ingroup nvodm_query
+ * @{
+ */
+
+#include "nvcommon.h"
+#include "nvodm_modules.h"
+
+#define NVODM_QUERY_PINMAP_MULTIPLEXED 0x40000000UL
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+/* --- Pin-mux Configurations (for each controller) --- */
+
+/**
+ * Defines the ATA pin-mux configurations.
+ */
+typedef enum
+{
+    NvOdmAtaPinMap_Config1 = 1,
+
+    /** Ignore -- Forces compilers to make 32-bit enums. */
+    NvOdmAtaPinMap_Force32 = 0x7FFFFFFF,
+} NvOdmAtaPinMap;
+
+/**
+ * Defines the external clock (CDEV, CSUS) pin-mux configurations.
+ */
+typedef enum
+{
+    NvOdmExternalClockPinMap_Config1 = 1,
+    NvOdmExternalClockPinMap_Config2,
+    NvOdmExternalClockPinMap_Config3,
+    /** Ignore -- Forces compilers to make 32-bit enums. */
+    NvOdmExternalClockPinMap_Force32 = 0x7FFFFFFF
+} NvOdmExternalClockPinMap;
+
+/**
+ * Defines the CRT pin-mux configurations.
+ */
+typedef enum
+{
+    NvOdmCrtPinMap_Config1 = 1,
+    NvOdmCrtPinMap_Config2,
+    NvOdmCrtPinMap_Config3,
+    NvOdmCrtPinMap_Config4,
+    /** Ignore -- Forces compilers to make 32-bit enums. */
+    NVOdmCrtPinMap_Force32 = 0x7FFFFFFF,
+} NvOdmCrtPinMap;
+
+/**
+ * Defines the DAP pin-mux configurations.
+ */
+typedef enum
+{
+    NvOdmDapPinMap_Config1 = 1,
+
+    /** Ignore -- Forces compilers to make 32-bit enums. */
+    NvOdmDapPinMap_Force32 = 0x7FFFFFFF,
+} NvOdmDapPinMap;
+
+/**
+ * Defines the display pin-mux configurations.
+ */
+typedef enum
+{
+    NvOdmDisplayPinMap_Config1 = 1,
+    NvOdmDisplayPinMap_Config2,
+    NvOdmDisplayPinMap_Config3,
+    NvOdmDisplayPinMap_Config4,
+    NvOdmDisplayPinMap_Config5,
+    NvOdmDisplayPinMap_Config6,
+    /** Ignore -- Forces compilers to make 32-bit enums. */
+    NvOdmDisplayPinMap_Force32 = 0x7FFFFFFFUL,
+} NvOdmDisplayPinMap;
+
+/**
+ * Defines the blacklight PWM pin-mux configurations.
+ */
+typedef enum
+{
+    NvOdmBacklightPwmPinMap_Config1 = 1,
+    NvOdmBacklightPwmPinMap_Config2,
+    NvOdmBacklightPwmPinMap_Config3,
+    /** Ignore -- Forces compilers to make 32-bit enums. */
+    NvOdmBacklightPwmPinMap_Force32 = 0x7FFFFFFFUL,
+} NvOdmBacklightPwmPinMap;
+
+/**
+ * Defines the HDCP pin-mux configurations.
+ */
+typedef enum
+{
+    NvOdmHdcpPinMap_Config1 = 1,
+    NvOdmHdcpPinMap_Config2,
+    NvOdmHdcpPinMap_Config3,
+    NvOdmHdcpPinMap_Config4,
+
+    /** Ignore -- Forces compilers to make 32-bit enums. */
+    NvOdmHdcpPinMap_Force32 = 0x7FFFFFFF,
+} NvOdmHdcpPinMap;
+
+/**
+ * Defines the HDCMI pin-mux configurations.
+ */
+typedef enum
+{
+    NvOdmHdmiPinMap_Config1 = 1,
+
+    /** Ignore -- Forces compilers to make 32-bit enums. */
+    NvOdmHdmiPinMap_Force32 = 0x7FFFFFFF,
+} NvOdmHdmiPinMap;
+
+/**
+ * Defines the HSI pin-mux configurations.
+ */
+typedef enum
+{
+    NvOdmHsiPinMap_Config1 = 1,
+
+    /** Ignore -- Forces compilers to make 32-bit enums. */
+    NvOdmHsiPinMap_Force32 = 0x7FFFFFFF,
+} NvOdmHsiPinMap;
+
+/**
+ * Defines the HSMMC pin-mux configurations.
+ */
+typedef enum
+{
+    NvOdmHsmmcPinMap_Config1 = 1,
+    NvOdmHsmmcPinMap_Config2,
+
+    /** Ignore -- Forces compilers to make 32-bit enums. */
+    NvOdmHsmmcPinMap_Force32 = 0x7FFFFFFF,
+} NvOdmHsmmcPinMap;
+
+/**
+ * Defines the OWR pin-mux configurations.
+ */
+typedef enum
+{
+    NvOdmOwrPinMap_Config1 = 1,
+    NvOdmOwrPinMap_Config2,
+    NvOdmOwrPinMap_Config3,
+
+    /**
+     * This configuration disables (tristates) OWR pins. This option may be
+     * used to change which pins an attached OWR device is using at runtime.
+     * In some cases, one device might set up OWR, communicate across this bus,
+     * and then set the OWR bus configuration to "multiplexed" so that another
+     * device can opt to use OWR with its own configurations at a later time.
+     */
+    NvOdmOwrPinMap_Multiplexed = NVODM_QUERY_PINMAP_MULTIPLEXED,
+    /** Ignore -- Forces compilers to make 32-bit enums. */
+    NvOdmOwrPinMap_Force32 = 0x7FFFFFFF,
+} NvOdmOwrPinMap;
+
+/**
+ * Defines I2C pin-mux configurations.
+ */
+typedef enum
+{
+    NvOdmI2cPinMap_Config1 = 1,
+    NvOdmI2cPinMap_Config2,
+    NvOdmI2cPinMap_Config3,
+    NvOdmI2cPinMap_Config4,
+
+    /**
+     * This configuration disables (tristates) I2C pins. This option may be
+     * used to change which pins an attached I2C device is using at runtime.
+     * 
+     * In some cases, one device might set up I2C, communicate across this bus,
+     * and then set the I2C bus configuration to "multiplexed" so that another
+     * device can opt to use I2C with its own configurations at a later time.
+     *
+     * This option is only supported on the I2C_2 controller (AP15, AP16, AP20).
+     */
+    NvOdmI2cPinMap_Multiplexed = NVODM_QUERY_PINMAP_MULTIPLEXED,
+    /** Ignore -- Forces compilers to make 32-bit enums. */
+    NvOdmI2cPinMap_Force32 = 0x7FFFFFFF,
+} NvOdmI2cPinMap;
+
+/**
+ * Defines the I2C PMU pin-mux configurations.
+ */
+typedef enum
+{
+    NvOdmI2cPmuPinMap_Config1 = 1,
+
+    /** Ignore -- Forces compilers to make 32-bit enums. */
+    NvOdmI2cPmuPinMap_Force32 = 0x7FFFFFFF,
+} NvOdmI2cPmuPinMap;
+
+/**
+ * Defines the PWM pin-mux configurations.
+ */
+typedef enum
+{
+    NvOdmPwmPinMap_Config1 = 1,
+    NvOdmPwmPinMap_Config2,
+    NvOdmPwmPinMap_Config3,
+    NvOdmPwmPinMap_Config4,
+    NvOdmPwmPinMap_Config5,
+    NvOdmPwmPinMap_Config6,
+
+    /** Ignore -- Forces compilers to make 32-bit enums. */
+    NvOdmPwmPinMap_Force32 = 0x7FFFFFFF,
+} NvOdmPwmPinMap;
+
+/**
+ * Defines KBD pin-mux configurations.
+ */
+typedef enum
+{
+    NvOdmKbdPinMap_Config1 = 1,
+    NvOdmKbdPinMap_Config2,
+    NvOdmKbdPinMap_Config3,
+    NvOdmKbdPinMap_Config4,
+
+    /** Ignore -- Forces compilers to make 32-bit enums. */
+    NvOdmKbdPinMap_Forc32 = 0x7FFFFFFF,
+} NvOdmKbdPinMap;
+
+/**
+ * Defines MIO pin-mux configurations.
+ */
+typedef enum
+{
+    NvOdmMioPinMap_Config1 = 1,
+
+    /** Ignore -- Forces compilers to make 32-bit enums. */
+    NvOdmMioPinMap_Forc32 = 0x7FFFFFFF,
+} NvOdmMioPinMap;
+
+/**
+ * Defines NAND pin-mux configurations.
+ */
+typedef enum
+{
+    NvOdmNandPinMap_Config1 = 1,
+    NvOdmNandPinMap_Config2,
+    NvOdmNandPinMap_Config3,
+    NvOdmNandPinMap_Config4,
+    NvOdmNandPinMap_Config5,
+    NvOdmNandPinMap_Config6,
+
+    /** Ignore -- Forces compilers to make 32-bit enums. */
+    NvOdmNandPinMap_Force32 = 0x7FFFFFFF,
+} NvOdmNandPinMap;
+
+/**
+ * Defines the SDIO pin-mux configurations.
+ */
+typedef enum
+{
+    NvOdmSdioPinMap_Config1 = 1,
+    NvOdmSdioPinMap_Config2,
+    NvOdmSdioPinMap_Config3,
+    NvOdmSdioPinMap_Config4,
+    NvOdmSdioPinMap_Config5,
+
+    /** Ignore -- Forces compilers to make 32-bit enums. */
+    NvOdmSdioPinMap_Force32 = 0x7FFFFFFF,
+} NvOdmSdioPinMap;
+
+/**
+ * Defines the SFLASH pin-mux configurations.
+ */
+typedef enum
+{
+    NvOdmSflashPinMap_Config1 = 1,
+    NvOdmSflashPinMap_Config2,
+    NvOdmSflashPinMap_Config3,
+    NvOdmSflashPinMap_Config4,
+
+    /** Ignore -- Forces compilers to make 32-bit enums. */
+    NvOdmSflashPinMap_Force32 = 0x7FFFFFFF,
+} NvOdmSflashPinMap;
+
+/**
+ * Defines the SPDIF pin-mux configurations.
+ */
+typedef enum
+{
+    NvOdmSpdifPinMap_Config1 = 1,   /**< Default SPDIF configuration. */
+    NvOdmSpdifPinMap_Config2,
+    NvOdmSpdifPinMap_Config3,
+
+    /** Ignore -- Forces compilers to make 32-bit enums. */
+    NvOdmSpdifPinMap_Force32 = 0x7FFFFFFF,
+} NvOdmSpdifPinMap;
+
+/**
+ * Defines the SPI pin-mux configurations.
+ */
+typedef enum
+{
+    NvOdmSpiPinMap_Config1 = 1,
+    NvOdmSpiPinMap_Config2,
+    NvOdmSpiPinMap_Config3,
+    NvOdmSpiPinMap_Config4,
+    NvOdmSpiPinMap_Config5,
+    NvOdmSpiPinMap_Config6,
+
+    /**
+     * This configuration disables (tristates) SPI pins. This option may be
+     * used to change which pins an attached SPI device is using at runtime.
+     * 
+     * In some cases, one device might set up SPI, communicate across this bus,
+     * and then set the SPI bus configuration to "multiplexed" so that another
+     * device can opt to use SPI with its own configurations at a later time.
+     *
+     * This option is only supported on SPI_3 (AP15, AP16).
+     */
+    NvOdmSpiPinMap_Multiplexed = NVODM_QUERY_PINMAP_MULTIPLEXED,
+
+    /** Ignore -- Forces compilers to make 32-bit enums. */
+    NvOdmSpiPinMap_Force32 = 0x7FFFFFFF,
+} NvOdmSpiPinMap;
+
+/**
+ * Defines the TV-out pin-mux configurations.
+ */
+typedef enum
+{
+    NvOdmTvoPinMap_Config1 = 1,
+
+    /** Ignore -- Forces compilers to make 32-bit enums. */
+    NvOdmTvoPinMap_Force32 = 0x7FFFFFFF,
+} NvOdmTvoPinMap;
+
+/**
+ * Defines the USB-ULPI pin-mux configurations.
+ */
+typedef enum
+{
+    NvOdmUsbPinMap_Config1 = 1,
+
+    /** Ignore -- Forces compilers to make 32-bit enums. */
+    NvOdmUsbPinMap_Force32 = 0x7FFFFFFF,
+} NvOdmUsbPinMap;
+
+
+/**
+ * Defines the TWC pin-mux configurations.
+ */
+typedef enum
+{
+    NvOdmTwcPinMap_Config1 = 1,
+    NvOdmTwcPinMap_Config2,
+
+    /** Ignore -- Forces compilers to make 32-bit enums. */
+    NvOdmTwcPinMap_Force32 = 0x7FFFFFFF,
+} NvOdmTwcPinMap;
+
+/**
+ * Defines the UART pin-mux configurations.
+ */
+typedef enum
+{
+    NvOdmUartPinMap_Config1 = 1,
+    NvOdmUartPinMap_Config2,
+    NvOdmUartPinMap_Config3,
+    NvOdmUartPinMap_Config4,
+    NvOdmUartPinMap_Config5,
+    NvOdmUartPinMap_Config6,
+    NvOdmUartPinMap_Config7,
+
+    /** Ignore -- Forces compilers to make 32-bit enums. */
+    NvOdmUartPinMap_Force32 = 0x7FFFFFFF,
+} NvOdmUartPinMap;
+
+/**
+ * Defines the video input pin-mux configurations.
+ */
+typedef enum
+{
+    NvOdmVideoInputPinMap_Config1 = 1,
+    NvOdmVideoInputPinMap_Config2,
+    /** Ignore -- Forces compilers to make 32-bit enums. */
+    NvOdmVideoInputPinMap_Force32 = 0x7FFFFFFFUL,
+} NvOdmVideoInputPinMap;
+
+/**
+ * Defines the PCI-Express pin-mux configurations.
+ */
+typedef enum
+{
+    NvOdmPciExpressPinMap_Config1 = 1,
+    NvOdmPciExpressPinMap_Force32 = 0x7FFFFFFFUL,
+} NvOdmPciExpressPinMap;
+
+/**
+ * Defines the SyncNor / OneNAND pin-mux configurations.
+ */
+typedef enum
+{
+    NvOdmSyncNorPinMap_Config1 = 1,
+    NvOdmSyncNorPinMap_Config2,
+    NvOdmSyncNorPinMap_Config3,
+    NvOdmSyncNorPinMap_Force32 = 0x7FFFFFFFUL,
+} NvOdmSyncNorPinMap;
+
+/**
+ * Defines the PTM pin-mux configurations.
+ */
+typedef enum
+{
+    NvOdmPtmPinMap_Config1 = 1,
+    NvOdmPtmPinMap_Force32 = 0x7FFFFFFFUL,
+} NvOdmPtmPinMap;
+
+/**
+ * Defines the one-wire pin-mux configurations.
+ */
+typedef enum
+{
+    NvOdmOneWirePinMap_Config1 = 1,
+    NvOdmOneWirePinMap_Config2,
+    NvOdmOneWirePinMap_Config3,
+    NvOdmOneWirePinMap_Force32 = 0x7FFFFFFFUL,
+} NvOdmOneWirePinMap;
+
+
+/**
+ * Defines the ULPI pin-mux configurations.
+ */
+typedef enum
+{
+    NvOdmUlpiPinMap_Config1 = 1,
+    NvOdmUlpiPinMap_Force32 = 0x7FFFFFFFUL,
+} NvOdmUlpiPinMap;
+
+/* --- Pin-mux API --- */
+
+/**
+ * Gets the pinmux configuration table for a given module.
+ *
+ * @param IoModule The I/O module to query.
+ * @param pPinMuxConfigTable A const pointer to the module's configuration
+ *  table. Each entry in the table represents the configuration for the I/O
+ *  module instance, where the instance indices start from 0.
+ * @param pCount A pointer to a variable that this function sets to the
+ *  number of entires in the configuration table.
+ */
+void
+NvOdmQueryPinMux(
+    NvOdmIoModule IoModule,
+    const NvU32 **pPinMuxConfigTable,
+    NvU32 *pCount);
+
+/**
+ * Gets the maximum clock speed for a given module as imposed by a board.
+ *
+ * @param IoModule The I/O module to query.
+ * @param pClockSpeedLimits A const pointer to the module's clock speed limit.
+ *  Each entry in the array represents the clock speed limit for the I/O
+ *  module instance, where the instance indices start from 0.
+ * @param pCount A pointer to a variable that this function sets to the
+ *  number of entries in the \a pClockSpeedLimits array.
+ */
+
+void
+NvOdmQueryClockLimits(
+    NvOdmIoModule IoModule,
+    const NvU32 **pClockSpeedLimits,
+    NvU32 *pCount);
+
+#if defined(__cplusplus)
+}
+#endif
+
+/** @} */
+
+#endif  // INCLUDED_NVODM_QUERY_PINMUX_H
diff --git a/arch/arm/mach-tegra/include/nvodm_query_pins.h b/arch/arm/mach-tegra/include/nvodm_query_pins.h
new file mode 100644
index 000000000000..6c769213689e
--- /dev/null
+++ b/arch/arm/mach-tegra/include/nvodm_query_pins.h
@@ -0,0 +1,106 @@
+/*
+ * Copyright (c) 2008-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/**
+ * @file
+ * <b>NVIDIA Tegra ODM Kit:
+ *         Pin Attributes Query Interface</b>
+ *
+ * @b Description: Provides a mechanism for ODMs to specify electrical
+ *                 attributes, such as drive strength, for pins.
+ */
+
+#ifndef INCLUDED_NVODM_QUERY_PINS_H
+#define INCLUDED_NVODM_QUERY_PINS_H
+
+/**
+ * @defgroup nvodm_pins Pin Electrical Attributes Query Interface
+ * This is the ODM query interface for pin electrical attributes.
+ *
+ * Pin attribute settings match the hardware register definitions very
+ * closely, and as such are specified in a chip-specific format.  C-language
+ * pre-processor macros are provided to allow for as much code readability
+ * and maintainability as possible. Because the organization and the
+ * electrical fine-tuning capabilities of the pins may change between
+ * products, ODMs should ensure that they are using the macros that match
+ * the SOC in their product.
+ * @ingroup nvodm_query
+ * @{
+ */
+
+#include "nvcommon.h"
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+
+/**
+ * Defines the pin attributes record.
+ */
+typedef struct NvOdmPinAttribRec
+{
+    ///  Specifies the configuration register to assign, which should be
+    ///  one of the application processor's NvOdmPinRegister enumerants.
+    NvU32 ConfigRegister;
+
+    ///  Specifies the value to assign to the specified configuration register.
+    ///  Each application processor's header file provides pre-processor
+    ///  macros to assist in defining this value.
+    NvU32 Value;
+} NvOdmPinAttrib;
+
+/**
+ * Gets a list of [configuration register, value] pairs that are applied
+ * to the application processor's pin configuration registers. Any
+ * pin configuration register that is not specified in this list is left at
+ * its current state.
+ *
+ * @param pPinAttributes A returned pointer to an array of constant pin
+ *  configuration attributes, or NULL if no pin configuration registers
+ *  should be programmed.
+ *
+ * @return The number of pin configuration attributes in \a pPinAttributes, or
+ *  0 if none.
+ */
+
+NvU32
+NvOdmQueryPinAttributes(const NvOdmPinAttrib **pPinAttributes);
+
+#if defined(__cplusplus)
+}
+#endif
+
+/** @} */
+#endif
+
diff --git a/arch/arm/mach-tegra/include/nvodm_query_pins_ap20.h b/arch/arm/mach-tegra/include/nvodm_query_pins_ap20.h
new file mode 100644
index 000000000000..ca8adc014c83
--- /dev/null
+++ b/arch/arm/mach-tegra/include/nvodm_query_pins_ap20.h
@@ -0,0 +1,420 @@
+/*
+ * Copyright (c) 2008-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/** @file
+ * <b>NVIDIA Tegra ODM Kit:
+ *        Pin configurations for NVIDIA AP20 processors</b>
+ * 
+ * @b Description: Defines the names and configurable settings for pin electrical
+ *                 attributes, such as drive strength and slew.
+ */
+
+// This is an auto-generated file.  Do not edit.
+// Regenerate with "genpadconfig.py ap20 drivers/hwinc/ap20/arapb_misc.h"
+
+#ifndef INCLUDED_NVODM_QUERY_PINS_AP20_H
+#define INCLUDED_NVODM_QUERY_PINS_AP20_H
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/**
+ * This specifies the list of pin configuration registers supported by
+ * AP20-compatible products.  This should be used to generate the pin
+ * pin-attribute query array.
+ * @see NvOdmQueryPinAttributes.
+ * @ingroup nvodm_pins
+ * @{
+ */
+
+typedef enum
+{
+
+    /// Pin configuration registers for NVIDIA AP20 products
+    NvOdmPinRegister_Ap20_PullUpDown_A = 0x200000A0UL,
+    NvOdmPinRegister_Ap20_PullUpDown_B = 0x200000A4UL,
+    NvOdmPinRegister_Ap20_PullUpDown_C = 0x200000A8UL,
+    NvOdmPinRegister_Ap20_PullUpDown_D = 0x200000ACUL,
+    NvOdmPinRegister_Ap20_PullUpDown_E = 0x200000B0UL,
+    NvOdmPinRegister_Ap20_PadCtrl_AOCFG1PADCTRL = 0x20000868UL,
+    NvOdmPinRegister_Ap20_PadCtrl_AOCFG2PADCTRL = 0x2000086CUL,
+    NvOdmPinRegister_Ap20_PadCtrl_ATCFG1PADCTRL = 0x20000870UL,
+    NvOdmPinRegister_Ap20_PadCtrl_ATCFG2PADCTRL = 0x20000874UL,
+    NvOdmPinRegister_Ap20_PadCtrl_CDEV1CFGPADCTRL = 0x20000878UL,
+    NvOdmPinRegister_Ap20_PadCtrl_CDEV2CFGPADCTRL = 0x2000087CUL,
+    NvOdmPinRegister_Ap20_PadCtrl_CSUSCFGPADCTRL = 0x20000880UL,
+    NvOdmPinRegister_Ap20_PadCtrl_DAP1CFGPADCTRL = 0x20000884UL,
+    NvOdmPinRegister_Ap20_PadCtrl_DAP2CFGPADCTRL = 0x20000888UL,
+    NvOdmPinRegister_Ap20_PadCtrl_DAP3CFGPADCTRL = 0x2000088CUL,
+    NvOdmPinRegister_Ap20_PadCtrl_DAP4CFGPADCTRL = 0x20000890UL,
+    NvOdmPinRegister_Ap20_PadCtrl_DBGCFGPADCTRL = 0x20000894UL,
+    NvOdmPinRegister_Ap20_PadCtrl_LCDCFG1PADCTRL = 0x20000898UL,
+    NvOdmPinRegister_Ap20_PadCtrl_LCDCFG2PADCTRL = 0x2000089CUL,
+    NvOdmPinRegister_Ap20_PadCtrl_SDIO2CFGPADCTRL = 0x200008A0UL,
+    NvOdmPinRegister_Ap20_PadCtrl_SDIO3CFGPADCTRL = 0x200008A4UL,
+    NvOdmPinRegister_Ap20_PadCtrl_SPICFGPADCTRL = 0x200008A8UL,
+    NvOdmPinRegister_Ap20_PadCtrl_UAACFGPADCTRL = 0x200008ACUL,
+    NvOdmPinRegister_Ap20_PadCtrl_UABCFGPADCTRL = 0x200008B0UL,
+    NvOdmPinRegister_Ap20_PadCtrl_UART2CFGPADCTRL = 0x200008B4UL,
+    NvOdmPinRegister_Ap20_PadCtrl_UART3CFGPADCTRL = 0x200008B8UL,
+    NvOdmPinRegister_Ap20_PadCtrl_VICFG1PADCTRL = 0x200008BCUL,
+    NvOdmPinRegister_Ap20_PadCtrl_VICFG2PADCTRL = 0x200008C0UL,
+    NvOdmPinRegister_Ap20_PadCtrl_XM2CFGAPADCTRL = 0x200008C4UL,
+    NvOdmPinRegister_Ap20_PadCtrl_XM2CFGCPADCTRL = 0x200008C8UL,
+    NvOdmPinRegister_Ap20_PadCtrl_XM2CFGDPADCTRL = 0x200008CCUL,
+    NvOdmPinRegister_Ap20_PadCtrl_XM2CLKCFGPADCTRL = 0x200008D0UL,
+    NvOdmPinRegister_Ap20_PadCtrl_XM2COMPPADCTRL = 0x200008D4UL,
+    NvOdmPinRegister_Ap20_PadCtrl_XM2VTTGENPADCTRL = 0x200008D8UL,
+    NvOdmPinRegister_Ap20_PadCtrl_SDIO1CFGPADCTRL = 0x200008E0UL,
+    NvOdmPinRegister_Ap20_PadCtrl_XM2CFGCPADCTRL2 = 0x200008E4UL,
+    NvOdmPinRegister_Ap20_PadCtrl_XM2CFGDPADCTRL2 = 0x200008E8UL,
+    NvOdmPinRegister_Ap20_PadCtrl_CRTCFGPADCTRL = 0x200008ECUL,
+    NvOdmPinRegister_Ap20_PadCtrl_DDCCFGPADCTRL = 0x200008F0UL,
+    NvOdmPinRegister_Ap20_PadCtrl_GMACFGPADCTRL = 0x200008F4UL,
+    NvOdmPinRegister_Ap20_PadCtrl_GMBCFGPADCTRL = 0x200008F8UL,
+    NvOdmPinRegister_Ap20_PadCtrl_GMCCFGPADCTRL = 0x200008FCUL,
+    NvOdmPinRegister_Ap20_PadCtrl_GMDCFGPADCTRL = 0x20000900UL,
+    NvOdmPinRegister_Ap20_PadCtrl_GMECFGPADCTRL = 0x20000904UL,
+    NvOdmPinRegister_Ap20_PadCtrl_OWRCFGPADCTRL = 0x20000908UL,
+    NvOdmPinRegister_Ap20_PadCtrl_UADCFGPADCTRL = 0x2000090CUL,
+
+    NvOdmPinRegister_Force32 = 0x7fffffffUL,
+} NvOdmPinRegister;
+
+/*
+ * C pre-processor macros are provided below to help ODMs specify
+ * pin electrical attributes in a more readable and maintainable fashion
+ * than hardcoding hexadecimal numbers directly.  Please refer to the
+ * Electrical, Thermal and Mechanical data sheet for your product for more
+ * detailed information regarding the effects these values have
+ */
+
+/**
+ * Use this macro to program the PullUpDown_A register.
+ *
+ * @param ATA : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param ATB : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param ATC : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param ATD : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param ATE : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param DAP1 : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param DAP2 : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param DAP3 : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param DAP4 : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param DTA : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param DTB : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param DTC : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param DTD : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param DTE : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param DTF : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param GPV : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ */
+
+#define NVODM_QUERY_PIN_AP20_PULLUPDOWN_A(ATA, ATB, ATC, ATD, ATE, DAP1, DAP2, DAP3, DAP4, DTA, DTB, DTC, DTD, DTE, DTF, GPV) \
+    ((((ATA)&3UL) << 0) | (((ATB)&3UL) << 2) | (((ATC)&3UL) << 4) | \
+     (((ATD)&3UL) << 6) | (((ATE)&3UL) << 8) | (((DAP1)&3UL) << 10) | \
+     (((DAP2)&3UL) << 12) | (((DAP3)&3UL) << 14) | (((DAP4)&3UL) << 16) | \
+     (((DTA)&3UL) << 18) | (((DTB)&3UL) << 20) | (((DTC)&3UL) << 22) | \
+     (((DTD)&3UL) << 24) | (((DTE)&3UL) << 26) | (((DTF)&3UL) << 28) | \
+     (((GPV)&3UL) << 30))
+
+/**
+ * Use this macro to program the PullUpDown_B register.
+ *
+ * @param RM : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param I2CP : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param PTA : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param GPU7 : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param KBCA : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param KBCB : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param KBCC : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param KBCD : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param SPDI : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param SPDO : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param GPU : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param SLXA : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param CRTP : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param SLXC : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param SLXD : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param SLXK : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ */
+
+#define NVODM_QUERY_PIN_AP20_PULLUPDOWN_B(RM, I2CP, PTA, GPU7, KBCA, KBCB, KBCC, KBCD, SPDI, SPDO, GPU, SLXA, CRTP, SLXC, SLXD, SLXK) \
+    ((((RM)&3UL) << 0) | (((I2CP)&3UL) << 2) | (((PTA)&3UL) << 4) | \
+     (((GPU7)&3UL) << 6) | (((KBCA)&3UL) << 8) | (((KBCB)&3UL) << 10) | \
+     (((KBCC)&3UL) << 12) | (((KBCD)&3UL) << 14) | (((SPDI)&3UL) << 16) | \
+     (((SPDO)&3UL) << 18) | (((GPU)&3UL) << 20) | (((SLXA)&3UL) << 22) | \
+     (((CRTP)&3UL) << 24) | (((SLXC)&3UL) << 26) | (((SLXD)&3UL) << 28) | \
+     (((SLXK)&3UL) << 30))
+
+/**
+ * Use this macro to program the PullUpDown_C register.
+ *
+ * @param CDEV1 : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param CDEV2 : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param SPIA : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param SPIB : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param SPIC : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param SPID : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param SPIE : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param SPIF : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param SPIG : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param SPIH : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param IRTX : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param IRRX : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param GME : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param XM2D : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param XM2C : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ */
+
+#define NVODM_QUERY_PIN_AP20_PULLUPDOWN_C(CDEV1, CDEV2, SPIA, SPIB, SPIC, SPID, SPIE, SPIF, SPIG, SPIH, IRTX, IRRX, GME, XM2D, XM2C) \
+    ((((CDEV1)&3UL) << 0) | (((CDEV2)&3UL) << 2) | (((SPIA)&3UL) << 4) | \
+     (((SPIB)&3UL) << 6) | (((SPIC)&3UL) << 8) | (((SPID)&3UL) << 10) | \
+     (((SPIE)&3UL) << 12) | (((SPIF)&3UL) << 14) | (((SPIG)&3UL) << 16) | \
+     (((SPIH)&3UL) << 18) | (((IRTX)&3UL) << 20) | (((IRRX)&3UL) << 22) | \
+     (((GME)&3UL) << 24) | (((XM2D)&3UL) << 28) | (((XM2C)&3UL) << 30))
+
+/**
+ * Use this macro to program the PullUpDown_D register.
+ *
+ * @param UAA : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param UAB : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param UAC : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param UAD : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param UCA : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param UCB : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param LD17_0 : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param LD19_18 : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param LD21_20 : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param LD23_22 : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param LS : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param LC : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param CSUS : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param DDRC : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param SDC : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param SDD : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ */
+
+#define NVODM_QUERY_PIN_AP20_PULLUPDOWN_D(UAA, UAB, UAC, UAD, UCA, UCB, LD17_0, LD19_18, LD21_20, LD23_22, LS, LC, CSUS, DDRC, SDC, SDD) \
+    ((((UAA)&3UL) << 0) | (((UAB)&3UL) << 2) | (((UAC)&3UL) << 4) | \
+     (((UAD)&3UL) << 6) | (((UCA)&3UL) << 8) | (((UCB)&3UL) << 10) | \
+     (((LD17_0)&3UL) << 12) | (((LD19_18)&3UL) << 14) | (((LD21_20)&3UL) << 16) | \
+     (((LD23_22)&3UL) << 18) | (((LS)&3UL) << 20) | (((LC)&3UL) << 22) | \
+     (((CSUS)&3UL) << 24) | (((DDRC)&3UL) << 26) | (((SDC)&3UL) << 28) | \
+     (((SDD)&3UL) << 30))
+
+/**
+ * Use this macro to program the PullUpDown_E register.
+ *
+ * @param KBCF : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param KBCE : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param PMCA : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param PMCB : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param PMCC : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param PMCD : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param PMCE : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param CK32 : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param UDA : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param SDIO1 : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param GMA : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param GMB : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param GMC : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param GMD : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param DDC : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param OWC : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ */
+
+#define NVODM_QUERY_PIN_AP20_PULLUPDOWN_E(KBCF, KBCE, PMCA, PMCB, PMCC, PMCD, PMCE, CK32, UDA, SDIO1, GMA, GMB, GMC, GMD, DDC, OWC) \
+    ((((KBCF)&3UL) << 0) | (((KBCE)&3UL) << 2) | (((PMCA)&3UL) << 4) | \
+     (((PMCB)&3UL) << 6) | (((PMCC)&3UL) << 8) | (((PMCD)&3UL) << 10) | \
+     (((PMCE)&3UL) << 12) | (((CK32)&3UL) << 14) | (((UDA)&3UL) << 16) | \
+     (((SDIO1)&3UL) << 18) | (((GMA)&3UL) << 20) | (((GMB)&3UL) << 22) | \
+     (((GMC)&3UL) << 24) | (((GMD)&3UL) << 26) | (((DDC)&3UL) << 28) | \
+     (((OWC)&3UL) << 30))
+
+/**
+ * Use this macro to program the PadCtrl_AOCFG1PADCTRL, 
+ * PadCtrl_AOCFG2PADCTRL, PadCtrl_ATCFG1PADCTRL, PadCtrl_ATCFG2PADCTRL, 
+ * PadCtrl_CDEV1CFGPADCTRL, PadCtrl_CDEV2CFGPADCTRL, PadCtrl_CSUSCFGPADCTRL, 
+ * PadCtrl_DAP1CFGPADCTRL, PadCtrl_DAP2CFGPADCTRL, PadCtrl_DAP3CFGPADCTRL, 
+ * PadCtrl_DAP4CFGPADCTRL, PadCtrl_DBGCFGPADCTRL, PadCtrl_LCDCFG1PADCTRL, 
+ * PadCtrl_LCDCFG2PADCTRL, PadCtrl_SDIO2CFGPADCTRL, PadCtrl_SDIO3CFGPADCTRL, 
+ * PadCtrl_SPICFGPADCTRL, PadCtrl_UAACFGPADCTRL, PadCtrl_UABCFGPADCTRL, 
+ * PadCtrl_UART2CFGPADCTRL, PadCtrl_UART3CFGPADCTRL, PadCtrl_VICFG1PADCTRL, 
+ * PadCtrl_VICFG2PADCTRL, PadCtrl_SDIO1CFGPADCTRL, PadCtrl_CRTCFGPADCTRL, 
+ * PadCtrl_DDCCFGPADCTRL, PadCtrl_GMACFGPADCTRL, PadCtrl_GMBCFGPADCTRL, 
+ * PadCtrl_GMCCFGPADCTRL, PadCtrl_GMDCFGPADCTRL, PadCtrl_GMECFGPADCTRL, 
+ * PadCtrl_OWRCFGPADCTRL and PadCtrl_UADCFGPADCTRL registers.
+ *
+ * @param HSM_EN : Enable high-speed mode (0 = disable).  Valid Range 0 - 1
+ * @param SCHMT_EN : Schmitt trigger enable (0 = disable).  Valid Range 0 - 1
+ * @param LPMD : Low-power current/impedance selection (0 = 400 ohm, 1 = 200 ohm, 2 = 100 ohm, 3 = 50 ohm).  Valid Range 0 - 3
+ * @param CAL_DRVDN : Pull-down drive strength.  Valid Range 0 - 31
+ * @param CAL_DRVUP : Pull-up drive strength.  Valid Range 0 - 31
+ * @param CAL_DRVDN_SLWR : Pull-up slew control (0 = max).  Valid Range 0 - 3
+ * @param CAL_DRVUP_SLWF : Pull-down slew control (0 = max).  Valid Range 0 - 3
+ */
+
+#define NVODM_QUERY_PIN_AP20_PADCTRL_AOCFG1PADCTRL(HSM_EN, SCHMT_EN, LPMD, CAL_DRVDN, CAL_DRVUP, CAL_DRVDN_SLWR, CAL_DRVUP_SLWF) \
+    ((((HSM_EN)&1UL) << 2) | (((SCHMT_EN)&1UL) << 3) | (((LPMD)&3UL) << 4) | \
+     (((CAL_DRVDN)&31UL) << 12) | (((CAL_DRVUP)&31UL) << 20) | \
+     (((CAL_DRVDN_SLWR)&3UL) << 28) | (((CAL_DRVUP_SLWF)&3UL) << 30))
+
+/**
+ * Use this macro to program the PadCtrl_XM2CFGAPADCTRL register.
+ *
+ * @param BYPASS_EN : .  Valid Range 0 - 1
+ * @param PREEMP_EN : .  Valid Range 0 - 1
+ * @param CLK_SEL : .  Valid Range 0 - 1
+ * @param CAL_DRVDN : Pull-down drive strength.  Valid Range 0 - 31
+ * @param CAL_DRVUP : Pull-up drive strength.  Valid Range 0 - 31
+ * @param CAL_DRVDN_SLWR : Pull-up slew control (0 = max).  Valid Range 0 - 15
+ * @param CAL_DRVUP_SLWF : Pull-down slew control (0 = max).  Valid Range 0 - 15
+ */
+
+#define NVODM_QUERY_PIN_AP20_PADCTRL_XM2CFGAPADCTRL(BYPASS_EN, PREEMP_EN, CLK_SEL, CAL_DRVDN, CAL_DRVUP, CAL_DRVDN_SLWR, CAL_DRVUP_SLWF) \
+    ((((BYPASS_EN)&1UL) << 4) | (((PREEMP_EN)&1UL) << 5) | \
+     (((CLK_SEL)&1UL) << 6) | (((CAL_DRVDN)&31UL) << 14) | \
+     (((CAL_DRVUP)&31UL) << 19) | (((CAL_DRVDN_SLWR)&15UL) << 24) | \
+     (((CAL_DRVUP_SLWF)&15UL) << 28))
+
+/**
+ * Use this macro to program the PadCtrl_XM2CFGCPADCTRL and 
+ * PadCtrl_XM2CFGDPADCTRL registers.
+ *
+ * @param SCHMT_EN : Schmitt trigger enable (0 = disable).  Valid Range 0 - 1
+ * @param CAL_DRVDN_TERM : Pull-down drive strength.  Valid Range 0 - 31
+ * @param CAL_DRVUP_TERM : Pull-up drive strength.  Valid Range 0 - 31
+ * @param CAL_DRVDN : Pull-down drive strength.  Valid Range 0 - 31
+ * @param CAL_DRVUP : Pull-up drive strength.  Valid Range 0 - 31
+ * @param CAL_DRVDN_SLWR : Pull-up slew control (0 = max).  Valid Range 0 - 15
+ * @param CAL_DRVUP_SLWF : Pull-down slew control (0 = max).  Valid Range 0 - 15
+ */
+
+#define NVODM_QUERY_PIN_AP20_PADCTRL_XM2CFGCPADCTRL(SCHMT_EN, CAL_DRVDN_TERM, CAL_DRVUP_TERM, CAL_DRVDN, CAL_DRVUP, CAL_DRVDN_SLWR, CAL_DRVUP_SLWF) \
+    ((((SCHMT_EN)&1UL) << 3) | (((CAL_DRVDN_TERM)&31UL) << 4) | \
+     (((CAL_DRVUP_TERM)&31UL) << 9) | (((CAL_DRVDN)&31UL) << 14) | \
+     (((CAL_DRVUP)&31UL) << 19) | (((CAL_DRVDN_SLWR)&15UL) << 24) | \
+     (((CAL_DRVUP_SLWF)&15UL) << 28))
+
+/**
+ * Use this macro to program the PadCtrl_XM2CLKCFGPADCTRL register.
+ *
+ * @param BYPASS_EN : .  Valid Range 0 - 1
+ * @param PREEMP_EN : .  Valid Range 0 - 1
+ * @param CAL_BYPASS_EN : .  Valid Range 0 - 1
+ * @param CAL_DRVDN : Pull-down drive strength.  Valid Range 0 - 31
+ * @param CAL_DRVUP : Pull-up drive strength.  Valid Range 0 - 31
+ * @param CAL_DRVDN_SLWR : Pull-up slew control (0 = max).  Valid Range 0 - 15
+ * @param CAL_DRVUP_SLWF : Pull-down slew control (0 = max).  Valid Range 0 - 15
+ */
+
+#define NVODM_QUERY_PIN_AP20_PADCTRL_XM2CLKCFGPADCTRL(BYPASS_EN, PREEMP_EN, CAL_BYPASS_EN, CAL_DRVDN, CAL_DRVUP, CAL_DRVDN_SLWR, CAL_DRVUP_SLWF) \
+    ((((BYPASS_EN)&1UL) << 1) | (((PREEMP_EN)&1UL) << 2) | \
+     (((CAL_BYPASS_EN)&1UL) << 3) | (((CAL_DRVDN)&31UL) << 14) | \
+     (((CAL_DRVUP)&31UL) << 19) | (((CAL_DRVDN_SLWR)&15UL) << 24) | \
+     (((CAL_DRVUP_SLWF)&15UL) << 28))
+
+/**
+ * Use this macro to program the PadCtrl_XM2COMPPADCTRL register.
+ *
+ * @param VREF_SEL : .  Valid Range 0 - 15
+ * @param TESTOUT_EN : .  Valid Range 0 - 1
+ * @param BIAS_SEL : .  Valid Range 0 - 7
+ * @param DRVDN : Pull-down drive strength.  Valid Range 0 - 31
+ * @param DRVUP : Pull-up drive strength.  Valid Range 0 - 31
+ */
+
+#define NVODM_QUERY_PIN_AP20_PADCTRL_XM2COMPPADCTRL(VREF_SEL, TESTOUT_EN, BIAS_SEL, DRVDN, DRVUP) \
+    ((((VREF_SEL)&15UL) << 0) | (((TESTOUT_EN)&1UL) << 4) | \
+     (((BIAS_SEL)&7UL) << 5) | (((DRVDN)&31UL) << 12) | (((DRVUP)&31UL) << 20))
+
+/**
+ * Use this macro to program the PadCtrl_XM2VTTGENPADCTRL register.
+ *
+ * @param SHORT : .  Valid Range 0 - 1
+ * @param SHORT_PWRGND : .  Valid Range 0 - 1
+ * @param VCLAMP_LEVEL : .  Valid Range 0 - 7
+ * @param VAUXP_LEVEL : .  Valid Range 0 - 7
+ * @param CAL_DRVDN : Pull-down drive strength.  Valid Range 0 - 7
+ * @param CAL_DRVUP : Pull-up drive strength.  Valid Range 0 - 7
+ */
+
+#define NVODM_QUERY_PIN_AP20_PADCTRL_XM2VTTGENPADCTRL(SHORT, SHORT_PWRGND, VCLAMP_LEVEL, VAUXP_LEVEL, CAL_DRVDN, CAL_DRVUP) \
+    ((((SHORT)&1UL) << 0) | (((SHORT_PWRGND)&1UL) << 1) | \
+     (((VCLAMP_LEVEL)&7UL) << 8) | (((VAUXP_LEVEL)&7UL) << 12) | \
+     (((CAL_DRVDN)&7UL) << 16) | (((CAL_DRVUP)&7UL) << 24))
+
+/**
+ * Use this macro to program the PadCtrl_XM2CFGCPADCTRL2 register.
+ *
+ * @param RX_FT_REC_EN : .  Valid Range 0 - 1
+ * @param BYPASS_EN : .  Valid Range 0 - 1
+ * @param PREEMP_EN : .  Valid Range 0 - 1
+ * @param CTT_HIZ_EN : .  Valid Range 0 - 1
+ * @param VREF_DQS_EN : .  Valid Range 0 - 1
+ * @param VREF_DQ_EN : .  Valid Range 0 - 1
+ * @param CLKSEL_DQ : .  Valid Range 0 - 1
+ * @param CLKSEL_DQS : .  Valid Range 0 - 1
+ * @param VREF_DQS : .  Valid Range 0 - 15
+ * @param VREF_DQ : .  Valid Range 0 - 15
+ */
+
+#define NVODM_QUERY_PIN_AP20_PADCTRL_XM2CFGCPADCTRL2(RX_FT_REC_EN, BYPASS_EN, PREEMP_EN, CTT_HIZ_EN, VREF_DQS_EN, VREF_DQ_EN, CLKSEL_DQ, CLKSEL_DQS, VREF_DQS, VREF_DQ) \
+    ((((RX_FT_REC_EN)&1UL) << 0) | (((BYPASS_EN)&1UL) << 1) | \
+     (((PREEMP_EN)&1UL) << 2) | (((CTT_HIZ_EN)&1UL) << 3) | \
+     (((VREF_DQS_EN)&1UL) << 4) | (((VREF_DQ_EN)&1UL) << 5) | \
+     (((CLKSEL_DQ)&1UL) << 6) | (((CLKSEL_DQS)&1UL) << 7) | \
+     (((VREF_DQS)&15UL) << 16) | (((VREF_DQ)&15UL) << 24))
+
+/**
+ * Use this macro to program the PadCtrl_XM2CFGDPADCTRL2 register.
+ *
+ * @param RX_FT_REC : .  Valid Range 0 - 1
+ * @param BYPASS : .  Valid Range 0 - 1
+ * @param PREEMP : .  Valid Range 0 - 1
+ * @param CTT_HIZ : .  Valid Range 0 - 1
+ */
+
+#define NVODM_QUERY_PIN_AP20_PADCTRL_XM2CFGDPADCTRL2(RX_FT_REC, BYPASS, PREEMP, CTT_HIZ) \
+    ((((RX_FT_REC)&1UL) << 0) | (((BYPASS)&1UL) << 1) | (((PREEMP)&1UL) << 2) | \
+     (((CTT_HIZ)&1UL) << 3))
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */
+#endif // INCLUDED_NVODM_QUERY_PINS_AP20_H
+
diff --git a/arch/arm/mach-tegra/include/nvodm_sdio.h b/arch/arm/mach-tegra/include/nvodm_sdio.h
new file mode 100644
index 000000000000..ba30d74712d3
--- /dev/null
+++ b/arch/arm/mach-tegra/include/nvodm_sdio.h
@@ -0,0 +1,104 @@
+/*
+ * Copyright (c) 2006-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/** 
+ * @file
+ * <b>NVIDIA Tegra ODM Kit:
+ *         SDIO Adaptation Interface</b>
+ *
+ * @b Description: Defines the ODM adaptation interface for SDIO devices.
+ * 
+ */
+
+#ifndef INCLUDED_NVODM_SDIO_H
+#define INCLUDED_NVODM_SDIO_H
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+#include "nvodm_services.h"
+#include "nverror.h"
+
+/**
+ * @defgroup nvodm_sdio SDIO Adaptation Interface
+ *
+ * This is the SDIO ODM adaptation interface.
+ *
+ * @ingroup nvodm_adaptation
+ * @{
+ */
+ 
+
+/**
+ * Defines an opaque handle that exists for each SDIO device in the
+ * system, each of which is defined by the customer implementation.
+ */
+typedef struct NvOdmSdioRec *NvOdmSdioHandle;
+
+/**
+ * Gets a handle to the SDIO device.
+ *
+ * @return A handle to the SDIO device.
+ */
+NvOdmSdioHandle NvOdmSdioOpen(NvU32 Instance);
+
+/**
+ * Closes the SDIO handle. 
+ *
+ * @param hOdmSdio The SDIO handle to be closed.
+ */
+void NvOdmSdioClose(NvOdmSdioHandle hOdmSdio);
+
+/**
+ * Suspends the SDIO device.
+ * @param hOdmSdio The handle to SDIO device.
+ * @return NV_TRUE if successful, or NV_FALSE otherwise.
+ */
+NvBool NvOdmSdioSuspend(NvOdmSdioHandle hOdmSdio);
+
+/**
+ * Resumes the SDIO device from suspend mode.
+ * @param hOdmSdio The handle to SDIO device.
+ * @return NV_TRUE if successful, or NV_FALSE otherwise.
+ */
+NvBool NvOdmSdioResume(NvOdmSdioHandle hOdmSdio);
+
+
+#if defined(__cplusplus)
+}
+#endif
+
+/** @} */
+
+#endif // INCLUDED_NVODM_Sdio_H
diff --git a/arch/arm/mach-tegra/include/nvodm_services.h b/arch/arm/mach-tegra/include/nvodm_services.h
new file mode 100644
index 000000000000..53b4fa5eecd7
--- /dev/null
+++ b/arch/arm/mach-tegra/include/nvodm_services.h
@@ -0,0 +1,1701 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/**
+ * @file
+ * <b>NVIDIA Tegra ODM Kit:
+ *         ODM Services API</b>
+ *
+ * @b Description: Defines the abstraction to SOC resources used by
+ *                 external peripherals.
+ */
+
+#ifndef INCLUDED_NVODM_SERVICES_H
+#define INCLUDED_NVODM_SERVICES_H
+
+// Using addtogroup when defgroup resides in another file
+/**
+ * @addtogroup nvodm_services
+ * @{
+ */
+
+#include "nvcommon.h"
+#include "nvodm_modules.h"
+#include "nvassert.h"
+#include "nvcolor.h"
+#include "nvodm_query_pinmux.h"
+#include "nvodm_query.h"
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+/*
+ * This header is split into two sections: OS abstraction APIs and basic I/O
+ * driver APIs.
+ */
+
+/** @name OS Abstraction APIs
+ * The Operating System APIs are portable to any NVIDIA-supported operating
+ * system and will appear in all of the engineering sample code.
+ */
+/*@{*/
+
+/**
+ * Outputs a message to the console, if present. Do not use this for
+ * interacting with a user from an application.
+ *
+ * @param format A pointer to the format string. The format string and variable
+ * parameters exactly follow the posix printf standard.
+ */
+void
+NvOdmOsPrintf( const char *format, ...);
+
+/**
+ * Outputs a message to the debugging console, if present. Do not use this for
+ * interacting with a user from an application.
+ *
+ * @param format A pointer to the format string. The format string and variable
+ * parameters exactly follow the posix printf standard.
+ */
+void
+NvOdmOsDebugPrintf( const char *format, ... );
+
+/**
+ * Dynamically allocates memory. Alignment, if desired, must be done by the
+ * caller.
+ *
+ * @param size The size, in bytes, of the allocation request.
+ */
+void *
+NvOdmOsAlloc(size_t size);
+
+/**
+ * Frees a dynamic memory allocation.
+ *
+ * Freeing a NULL value is supported.
+ *
+ * @param ptr A pointer to the memory to free, which should be from NvOdmOsAlloc().
+ */
+void
+NvOdmOsFree(void *ptr);
+
+typedef struct NvOdmOsMutexRec *NvOdmOsMutexHandle;
+typedef struct NvOdmOsSemaphoreRec *NvOdmOsSemaphoreHandle;
+typedef struct NvOdmOsThreadRec *NvOdmOsThreadHandle;
+
+/**
+ * Copies a specified number of bytes from a source memory location to
+ * a destination memory location.
+ *
+ *  @param dest A pointer to the destination of the copy.
+ *  @param src A pointer to the source memory.
+ *  @param size The length of the copy in bytes.
+ */
+void
+NvOdmOsMemcpy(void *dest, const void *src, size_t size);
+
+/**
+ * Sets a region of memory to a value.
+ *
+ *  @param s A pointer to the memory region.
+ *  @param c The value to set.
+ *  @param size The length of the region in bytes.
+ */
+void
+NvOdmOsMemset(void *s, NvU8 c, size_t size);
+
+/**
+ * Create a new mutex.
+ *
+ * @note Mutexes can be locked recursively; if a thread owns the lock,
+ * it can lock it again as long as it unlocks it an equal number of times.
+ *
+ * @return NULL on failure.
+ */
+NvOdmOsMutexHandle
+NvOdmOsMutexCreate( void );
+
+/**
+ * Locks the given unlocked mutex.
+ *
+ * @note This is a recursive lock.
+ *
+ * @param mutex The mutex to lock.
+ */
+void
+NvOdmOsMutexLock( NvOdmOsMutexHandle mutex );
+
+/**
+ * Unlock a locked mutex.
+ *
+ * A mutex must be unlocked exactly as many times as it has been locked.
+ *
+ * @param mutex The mutex to unlock.
+ */
+void
+NvOdmOsMutexUnlock( NvOdmOsMutexHandle mutex );
+
+/**
+ * Frees the resources held by a mutex.
+ *
+ * @param mutex The mutex to destroy. Passing a NULL mutex is supported.
+ */
+void
+NvOdmOsMutexDestroy( NvOdmOsMutexHandle mutex );
+
+/**
+ * Creates a counting semaphore.
+ *
+ * @param value The initial semaphore value.
+ *
+ * @return NULL on failure.
+ */
+NvOdmOsSemaphoreHandle
+NvOdmOsSemaphoreCreate( NvU32 value );
+
+/**
+ * Waits until the semaphore value becomes non-zero.
+ *
+ * @param semaphore The semaphore for which to wait.
+ */
+void
+NvOdmOsSemaphoreWait( NvOdmOsSemaphoreHandle semaphore );
+
+/**
+ * Waits for the given semaphore value to become non-zero with timeout.
+ *
+ * @param semaphore The semaphore for which to wait.
+ * @param msec The timeout value in milliseconds. Use ::NV_WAIT_INFINITE
+ * to wait forever.
+ *
+ * @return NV_FALSE if the wait expires.
+ */
+NvBool
+NvOdmOsSemaphoreWaitTimeout( NvOdmOsSemaphoreHandle semaphore, NvU32 msec );
+
+/**
+ * Increments the semaphore value.
+ *
+ * @param semaphore The semaphore to signal.
+ */
+void
+NvOdmOsSemaphoreSignal( NvOdmOsSemaphoreHandle semaphore );
+
+/**
+ * Frees resources held by the semaphore.
+ *
+ * @param semaphore The semaphore to destroy. Passing in a NULL semaphore
+ * is supported (no op).
+ */
+void
+NvOdmOsSemaphoreDestroy( NvOdmOsSemaphoreHandle semaphore );
+
+/**
+ * Entry point for a thread.
+ */
+typedef void (*NvOdmOsThreadFunction)(void *args);
+
+/**
+ * Creates a thread.
+ *
+ *  @param function The thread entry point.
+ *  @param args The thread arguments.
+ *
+ * @return The thread handle, or NULL on failure.
+ */
+NvOdmOsThreadHandle
+NvOdmOsThreadCreate(
+    NvOdmOsThreadFunction function,
+    void *args);
+
+/**
+ * Waits for the given thread to exit.
+ *
+ *  The joined thread will be destroyed automatically. All OS resources
+ *  will be reclaimed. There is no method for terminating a thread
+ *  before it exits naturally.
+ *
+ *  Passing in a NULL thread ID is ok (no op).
+ *
+ *  @param thread The thread to wait for.
+ */
+void
+NvOdmOsThreadJoin(NvOdmOsThreadHandle thread);
+
+/**
+ *  Unschedules the calling thread for at least the given
+ *      number of milliseconds.
+ *
+ *  Other threads may run during the sleep time.
+ *
+ *  @param msec The number of milliseconds to sleep. This API should not be
+ *  called from an ISR, can be called from the IST though!
+ */
+void
+NvOdmOsSleepMS(NvU32 msec);
+
+
+/**
+ * Stalls the calling thread for at least the given number of
+ * microseconds. The actual time waited might be longer, so you cannot
+ * depend on this function for precise timing.
+ *
+ * @note It is safe to use this function at ISR time.
+ *
+ * @param usec The number of microseconds to wait.
+ */
+void
+NvOdmOsWaitUS(NvU32 usec);
+
+/**
+ * Gets the system time in milliseconds.
+ * The returned values are guaranteed to be monotonically increasing,
+ * but may wrap back to zero (after about 50 days of runtime).
+ *
+ * @return The system time in milliseconds.
+ */
+NvU32
+NvOdmOsGetTimeMS(void);
+
+/// Defines possible operating system types.
+typedef enum
+{
+    NvOdmOsOs_Unknown,
+    NvOdmOsOs_Windows,
+    NvOdmOsOs_Linux,
+    NvOdmOsOs_Aos,
+    NvOdmOsOs_Force32 = 0x7fffffffUL,
+} NvOdmOsOs;
+
+/// Defines possible operating system SKUs.
+typedef enum
+{
+    NvOdmOsSku_Unknown,
+    NvOdmOsSku_CeBase,
+    NvOdmOsSku_Mobile_SmartFon,
+    NvOdmOsSku_Mobile_PocketPC,
+    NvOdmOsSku_Android,
+    NvOdmOsSku_Force32 = 0x7fffffffUL,
+} NvOdmOsSku;
+
+/// Defines the OS information record.
+typedef struct NvOdmOsOsInfoRec
+{
+    NvOdmOsOs  OsType;
+    NvOdmOsSku Sku;
+    NvU16   MajorVersion;
+    NvU16   MinorVersion;
+    NvU32   SubVersion;
+    NvU32   Caps;
+} NvOdmOsOsInfo;
+
+/**
+ * Gets the current OS version.
+ *
+ * @param pOsInfo A pointer to the OS version.
+ * @return NV_TRUE if successful, or NV_FALSE otherwise.
+ */
+NvBool
+NvOdmOsGetOsInformation( NvOdmOsOsInfo *pOsInfo );
+
+/*@}*/
+/** @name Basic I/O Driver APIs
+ * The basic I/O driver APIs are a set of common input/outputs
+ * that can be used to extend the functionality of the software stack
+ * for new devices that aren't explicity handled by the stack.
+ * GPIO, I2C, and SPI are currently supported.
+*/
+/*@{*/
+
+/**
+ * Defines an opaque handle to the ODM Services GPIO rec interface.
+ */
+typedef struct NvOdmServicesGpioRec *NvOdmServicesGpioHandle;
+/**
+ * Defines an opaque handle to the ODM Services GPIO intr interface.
+ */
+typedef struct NvOdmServicesGpioIntrRec *NvOdmServicesGpioIntrHandle;
+/**
+ * Defines an opaque handle to the ODM Services SPI interface.
+ */
+typedef struct NvOdmServicesSpiRec *NvOdmServicesSpiHandle;
+/**
+ * Defines an opaque handle to the ODM Services I2C interface.
+ */
+typedef struct NvOdmServicesI2cRec *NvOdmServicesI2cHandle;
+/**
+ * Defines an opaque handle to the ODM Services PMU interface.
+ */
+typedef struct NvOdmServicesPmuRec *NvOdmServicesPmuHandle;
+/**
+ * Defines an opaque handle to the ODM Services PWM interface.
+ */
+typedef struct NvOdmServicesPwmRec *NvOdmServicesPwmHandle;
+/**
+ * Defines an opaque handle to the ODM Services key list interface.
+ */
+typedef struct NvOdmServicesKeyList *NvOdmServicesKeyListHandle;
+
+/**
+ * Defines an interrupt handler.
+ */
+typedef void (*NvOdmInterruptHandler)(void *args);
+
+/**
+ * @brief Defines the possible GPIO pin modes.
+ */
+typedef enum
+{
+    /// Specifies that that the pin is tristated, which will consume less power.
+    NvOdmGpioPinMode_Tristate = 1,
+
+    /// Specifies input mode with active low interrupt.
+    NvOdmGpioPinMode_InputInterruptLow,
+
+    /// Specifies input mode with active high interrupt.
+    NvOdmGpioPinMode_InputInterruptHigh,
+
+    /// Specifies input mode with no events.
+    NvOdmGpioPinMode_InputData,
+
+    /// Specifies output mode.
+    NvOdmGpioPinMode_Output,
+
+    /// Specifies special function.
+    NvOdmGpioPinMode_Function,
+
+    /// Specifies input and interrupt on any edge.
+    NvOdmGpioPinMode_InputInterruptAny,
+
+    /// Specifies input and interrupt on rising edge.
+    NvOdmGpioPinMode_InputInterruptRisingEdge,
+
+    /// Specifies output and interrupt on falling edge.
+    NvOdmGpioPinMode_InputInterruptFallingEdge,
+
+    /// Ignore -- Forces compilers to make 32-bit enums.
+    NvOdmGpioPinMode_Force32 = 0x7fffffff
+
+} NvOdmGpioPinMode;
+
+/**
+ * Defines the opaque handle to the GPIO pin.
+ */
+typedef struct NvOdmGpioPinRec *NvOdmGpioPinHandle;
+
+/**
+ * Creates and opens a GPIO handle. The handle can then be used to
+ * access GPIO functions.
+ *
+ * @see NvOdmGpioClose
+ *
+ * @return The handle to the GPIO controller, or NULL if an error occurred.
+ */
+NvOdmServicesGpioHandle NvOdmGpioOpen(void);
+
+/**
+ * Closes the GPIO handle. Any pin settings made while this handle is
+ * open will remain. All events enabled by this handle are
+ * disabled.
+ *
+ * @see NvOdmGpioOpen
+ *
+ * @param hOdmGpio The GPIO handle.
+ */
+void NvOdmGpioClose(NvOdmServicesGpioHandle hOdmGpio);
+
+/**
+ * Acquires a pin handle to be used in subsequent calls to
+ * access the pin.
+ *
+ * @see NvOdmGpioClose
+ *
+ * @param hOdmGpio The GPIO handle.
+ * @param port The port.
+ * @param Pin The pin for which to return the handle.
+ *
+ * @return The pin handle, or NULL if an error occurred.
+ */
+NvOdmGpioPinHandle
+NvOdmGpioAcquirePinHandle(NvOdmServicesGpioHandle hOdmGpio,
+        NvU32 port, NvU32 Pin);
+
+/**
+ * Releases the pin handle that was acquired by NvOdmGpioAcquirePinHandle()
+ * and used by the rest of the GPIO ODM APIs.
+ *
+ * @see NvOdmGpioAcquirePinHandle
+ *
+ * @param hOdmGpio The GPIO handle.
+ * @param hPin The pin handle to release.
+ */
+void
+NvOdmGpioReleasePinHandle(NvOdmServicesGpioHandle hOdmGpio,
+        NvOdmGpioPinHandle hPin);
+/**
+ * Sets the output state of a set of GPIO pins.
+ *
+ * @see NvOdmGpioOpen, NvOdmGpioGetState
+ *
+ * @param hOdmGpio The GPIO handle.
+ * @param hGpioPin The pin handle.
+ * @param PinValue The pin state to set. 0 means drive low, 1 means drive high.
+ */
+void
+NvOdmGpioSetState(NvOdmServicesGpioHandle hOdmGpio,
+    NvOdmGpioPinHandle hGpioPin,
+    NvU32 PinValue);
+
+/**
+ * Gets the output state of a specified set of GPIO pins in the port.
+ *
+ * @see NvOdmGpioOpen, NvOdmGpioSetState
+ *
+ * @param hOdmGpio The GPIO handle.
+ * @param hGpioPin The pin handle.
+ * @param pPinStateValue A pointer to the returned current state of the pin.
+ */
+void
+NvOdmGpioGetState(NvOdmServicesGpioHandle hOdmGpio,
+    NvOdmGpioPinHandle hGpioPin,
+    NvU32 *pPinStateValue);
+
+/**
+ * Configures the GPIO to specific mode. Don't use this API to configure the pin
+ * as interrupt pin, instead use the NvOdmGpioInterruptRegister
+ *  and NvOdmGpioInterruptUnregister APIs which internally call this function.
+ *
+ * @param hOdmGpio  The GPIO handle.
+ * @param hGpioPin  The pin handle.
+ * @param Mode      The mode type to configure.
+ */
+void
+NvOdmGpioConfig(NvOdmServicesGpioHandle hOdmGpio,
+    NvOdmGpioPinHandle hGpioPin,
+    NvOdmGpioPinMode Mode);
+
+/**
+ * Registers an interrupt callback function and the mode of interrupt for the
+ * GPIO pin specified.
+ *
+ * Callback uses the interrupt thread and the interrupt stack on Linux
+ * and IST on Windows CE; so, care should be taken on all the APIs used in
+ * the callback function.
+ *
+ * Interrupts are masked when they are triggered. It is up to the caller to
+ * re-enable the interrupts by calling NvOdmGpioInterruptDone().
+ *  
+ * @param hOdmGpio  The GPIO handle.
+ * @param hGpioIntr A pointer to the GPIO interrupt handle. Use this 
+ *  handle while unregistering the interrupt. On failure to hook
+ *  up the interrupt, a NULL handle is returned.
+ * @param hGpioPin  The pin handle.
+ * @param Mode      The mode type to configure. Allowed mode values are:
+ *  - NvOdmGpioPinMode_InputInterruptFallingEdge
+ *  - NvOdmGpioPinMode_InputInterruptRisingEdge
+ *  - NvOdmGpioPinMode_InputInterruptAny
+ *  - NvOdmGpioPinMode_InputInterruptLow
+ *  - NvOdmGpioPinMode_InputInterruptHigh
+ *  
+ * @param Callback The callback function that is called when 
+ *  the interrupt triggers.
+ * @param arg The argument used when the callback is called by the ISR. 
+ * @param DebounceTime The debounce time in milliseconds.
+ *
+ * @return NV_TRUE if successful, or NV_FALSE otherwise.
+ */
+NvBool
+NvOdmGpioInterruptRegister(NvOdmServicesGpioHandle hOdmGpio,
+    NvOdmServicesGpioIntrHandle *hGpioIntr,
+    NvOdmGpioPinHandle hGpioPin,
+    NvOdmGpioPinMode Mode,
+    NvOdmInterruptHandler Callback,
+    void *arg,
+    NvU32 DebounceTime);
+
+/**
+ *  Client of GPIO interrupt to re-enable the interrupt after
+ *  the handling the interrupt.
+ *
+ *  @param handle GPIO interrupt handle returned by a sucessfull call to
+ *  NvOdmGpioInterruptRegister().
+ */
+void NvOdmGpioInterruptDone( NvOdmServicesGpioIntrHandle handle );
+
+/**
+ * Mask/Unmask a gpio interrupt.
+ *
+ * Drivers can use this API to fend off interrupts. Mask means interrupts are
+ * not forwarded to the CPU. Unmask means, interrupts are forwarded to the CPU.
+ * In case of SMP systems, this API masks the interrutps to all the CPU, not
+ * just the calling CPU.
+ *
+ *
+ * @param handle    Interrupt handle returned by NvOdmGpioInterruptRegister API.
+ * @param mask      NV_FALSE to forrward the interrupt to CPU. NV_TRUE to 
+ * mask the interupts to CPU.
+ */
+void
+NvOdmGpioInterruptMask(NvOdmServicesGpioIntrHandle handle, NvBool mask);
+
+/**
+ * Unregisters the GPIO interrupt handler.
+ *
+ * @param hOdmGpio  The GPIO handle.
+ * @param hGpioPin  The pin handle.
+ * @param handle The interrupt handle returned by a successfull call to
+ * NvOdmGpioInterruptRegister().
+ *
+ */
+void
+NvOdmGpioInterruptUnregister(NvOdmServicesGpioHandle hOdmGpio,
+    NvOdmGpioPinHandle hGpioPin,
+    NvOdmServicesGpioIntrHandle handle);
+
+/**
+ * Obtains a handle that can be used to access one of the serial peripheral
+ * interface (SPI) controllers.
+ *
+ * There may be one or more instances of the SPI, depending upon the SOC,
+ * and these instances start from 0.
+ *
+ * @see NvOdmSpiClose
+ *
+ * @param OdmIoModule  The ODM I/O module for the SFLASH, SPI, or SLINK.
+ * @param ControllerId  The SPI controlled ID for which a handle is required.
+ *     Valid SPI channel IDs start from 0.
+ *
+ *
+ * @return The handle to the SPI controller, or NULL if an error occurred.
+ */
+NvOdmServicesSpiHandle NvOdmSpiOpen(NvOdmIoModule OdmIoModule, NvU32 ControllerId);
+
+/**
+ * Obtains a handle that can be used to access one of the serial peripheral
+ * interface (SPI) controllers, for SPI controllers which are multiplexed
+ * between multiple pin mux configurations. The SPI controller's pin mux
+ * will be reset to the specified value every transaction, so that two handles
+ * to the same controller may safely interleave across pin mux configurations.
+ *
+ * The ODM pin mux query for the specified controller must be
+ * NvOdmSpiPinMap_Multiplexed in order to create a handle using this function.
+ *
+ * There may be one or more instances of the SPI, depending upon the SOC,
+ * and these instances start from 0.
+ *
+ * Currently, this function is only supported for OdmIoModule_Spi, instance 2.
+ *
+ * @see NvOdmSpiClose
+ *
+ * @param OdmIoModule  The ODM I/O module for the SFLASH, SPI, or SLINK.
+ * @param ControllerId  The SPI controlled ID for which a handle is required.
+ *     Valid SPI channel IDs start from 0.
+ * @param PinMap The pin mux configuration to use for every transaction.
+ *
+ * @return The handle to the SPI controller, or NULL if an error occurred.
+ */
+NvOdmServicesSpiHandle 
+NvOdmSpiPinMuxOpen(NvOdmIoModule OdmIoModule,
+                   NvU32 ControllerId,
+                   NvOdmSpiPinMap PinMap);
+
+
+/**
+ * Obtains a handle that can be used to access one of the serial peripheral
+ * interface (SPI) controllers in slave mode.
+ *
+ * There may be one or more instances of the SPI, depending upon the SOC,
+ * and these instances start from 0.
+ *
+ * @see NvOdmSpiClose
+ *
+ * @param OdmIoModule  The ODM I/O module for the SFLASH, SPI, or SLINK.
+ * @param ControllerId  The SPI controlled ID for which a handle is required.
+ *     Valid SPI channel IDs start from 0.
+ *
+ *
+ * @return The handle to the SPI controller, or NULL if an error occurred.
+ */
+NvOdmServicesSpiHandle NvOdmSpiSlaveOpen(NvOdmIoModule OdmIoModule, NvU32 ControllerId);
+
+
+/**
+ * Releases a handle to an SPI controller. This API must be called once per
+ * successful call to NvOdmSpiOpen().
+ *
+ * @param hOdmSpi A SPI handle allocated in a call to \c NvOdmSpiOpen.  If \em hOdmSpi
+ *     is NULL, this API has no effect.
+ */
+void NvOdmSpiClose(NvOdmServicesSpiHandle hOdmSpi);
+
+/**
+ * Performs an SPI controller transaction. Every SPI transaction is by
+ * definition a simultaneous read and write transaction, so there are no
+ * separate APIs for read versus write. However, if you only need to do a read or
+ * write, this API allows you to declare that you are not interested in the read
+ * data, or that the write data is not of interest.
+ *
+ * This is a blocking API. When it returns, all of the data has been sent out
+ * over the pins of the SOC (the transaction). This is true even if the read data
+ * is being discarded, as it cannot merely have been queued up.
+ *
+ * Several SPI transactions may be performed in a single call to this API, but
+ * only if all of the transactions are to the same chip select and have the same
+ * packet size.
+ *
+ * Transaction sizes from 1 bit to 32 bits are supported. However, all
+ * of the buffers in memory are byte-aligned. To perform one transaction,
+ * the \em Size argument should be:
+ *
+ * <tt> <!-- typewriter font formats this nicely in the output document -->
+ *   (PacketSize + 7)/8
+ * </tt>
+ *
+ * To perform n transactions, \em Size should be:
+ *
+ * <tt>
+ *   n*((PacketSize + 7)/8)
+ * </tt>
+ *
+ * Within a given
+ * transaction with the packet size larger than 8 bits, the bytes are stored in 
+ * order of the MSB (most significant byte) first.
+ * The Packet is formed with the first Byte will be in MSB and then next byte 
+ * will be in the  next MSB towards the LSB.
+ *
+ * For the example, if One packet need to be send and its size is the 20 bit 
+ * then it will require the 3 bytes in the pWriteBuffer and arrangement of the 
+ * data  are as follows:
+ * The packet is 0x000ABCDE (Packet with length of 20 bit).
+ * pWriteBuff[0] = 0x0A
+ * pWriteBuff[1] = 0xBC
+ * pWtriteBuff[2] = 0xDE
+ *
+ * The most significant bit will be transmitted first i.e. bit20 is transmitted 
+ * first and bit 0 will be transmitted last.
+ *
+ * If the transmitted packet (command + receive data) is more than 32 like 33 and 
+ * want to transfer in the single call (CS should be active) then it can be transmitted
+ * in following way:
+ * The transfer is command(8 bit)+Dummy(1bit)+Read (24 bit) = 33 bit of transfer.
+ * - Send 33 bit as 33 byte and each byte have the 1 valid bit, So packet bit length = 1 and
+ * bytes requested = 33.
+ * NvU8 pSendData[33], pRecData[33];
+ *  pSendData[0] = (Comamnd >>7) & 0x1;
+ *  pSendData[1] = (Command >> 6)& 0x1; 
+ * ::::::::::::::
+ * pSendData[8] = DummyBit;
+ * pSendData[9] to pSendData[32] = 0;
+ * Call NvOdmSpiTransaction(hRmSpi,ChipSelect,ClockSpeedInKHz,pRecData, pSendData, 33,1);
+ * Now You will get the read data from pRecData[9] to pRecData[32] on bit 0 on each byte.
+ *
+ * - The 33 bit transfer can be also done as 11 byte and each byte have the 3 valid bits.
+ * This need to rearrange the command in the pSendData in such a way that each byte have the
+ * 3 valid bits.
+ * NvU8 pSendData[11], pRecData[11];
+ *  pSendData[0] = (Comamnd >>4) & 0x7;
+ *  pSendData[1] = (Command >> 1)& 0x7; 
+ *  pSendData[2] = (((Command)& 0x3) <<1) | DummyBit; 
+ * pSendData[3] to pSendData[10] = 0;
+ * 
+ * Call NvOdmSpiTransaction(hRmSpi, ChipSelect,ClockSpeedInKHz,pRecData, pSendData, 11,3);
+ * Now You will get the read data from pRecData[4] to pRecData[10] on lower 3 bits on each byte.
+ *
+ * Similarly the 33 bit transfer can also be done as 6 byte and each 2 bytes contain the 11 valid bits.
+ * Call NvOdmSpiTransaction(hRmSpi, ChipSelect,ClockSpeedInKHz,pRecData, pSendData, 6,11);
+ *
+ *
+ * \em ReadBuf and \em WriteBuf may be the same pointer, in which case the write
+ * data is destroyed as we read in the read data. Unless they are identical pointers,
+ * however, \em ReadBuf and \em WriteBuf must not overlap.
+ *
+ * @param hOdmSpi The SPI handle allocated in a call to NvOdmSpiOpen().
+ * @param ChipSelect Select with which of the several external devices (attached
+ *     to a single controller) we are communicating. Chip select indices
+ *     start at 0.
+ * @param ClockSpeedInKHz The speed in kHz on which the device can communicate.
+ * @param ReadBuf A pointer to buffer to be filled in with read data. If this
+ *     pointer is NULL, the read data will be discarded.
+ * @param WriteBuf A pointer to a buffer from which to obtain write data. If this
+ *     pointer is NULL, the write data will be all zeros.
+ * @param Size The size of \em ReadBuf and \em WriteBuf buffers in bytes.
+ * @param PacketSize The packet size in bits of each SPI transaction.
+ */
+void
+NvOdmSpiTransaction(
+    NvOdmServicesSpiHandle hOdmSpi,
+    NvU32 ChipSelect,
+    NvU32 ClockSpeedInKHz,
+    NvU8 *ReadBuf,
+    const NvU8 *WriteBuf,
+    NvU32 Size,
+    NvU32 PacketSize);
+
+
+/**
+ * Starts an SPI controller read and write simultaneously in the slave mode.
+ *
+ * This is a nonblocking API, which starts the data transfer and returns
+ * to the caller without waiting for the data transfer completion. 
+ *
+ * @note This API is only supported for the SPI handle, which is opened in
+ * slave mode using NvOdmSpiSlaveOpen(). This API asserts if the opened SPI
+ * handle is the master type.
+ *
+ * @see NvOdmSpiSlaveGetTransactionData
+ *
+ * @par Read or Write Transactions
+ *
+ * Every SPI transaction is by definition a simultaneous read and write 
+ * transaction, so there are no separate APIs for read versus write. 
+ * However, if you only need to start a read or write transaction, this API 
+ * allows you to declare that you are not interested in the read data, 
+ * or that the write data is not of interest. If only read
+ * is required to start, then the client can pass NV_TRUE to the \a IsReadTransfer
+ * parameter and a NULL pointer to \a pWriteBuffer. The state of the data out 
+ * will be set by NvOdmQuerySpiIdleSignalState::IsIdleDataOutHigh  
+ * in nvodm_query.h. Similarly, if the client wants to send data only
+ * then it can pass NV_FALSE to the \a IsReadTransfer parameter.
+ *
+ * @par Transaction Sizes
+ *
+ * Transaction sizes from 1 to 32 bits are supported. However, all of the 
+ * packets are byte-aligned in memory. So, if \a packetBitLength is 12 bits 
+ * then the client needs the 2nd byte for the 1 packet. New packets start from the
+ * new bytes, e.g., byte0 and byte1 contain the first packet and byte2 and byte3
+ * will contain the second packets.
+ *
+ * To perform one transaction, the \a BytesRequested argument should be:
+ * <pre>
+ *   (PacketSizeInBits + 7)/8
+ * </pre>
+ *
+ * To perform \a n transactions, \a BytesRequested should be:
+ * <pre>
+ *   n*((PacketSizeInBits + 7)/8)
+ * </pre>
+ *
+ * Within a given transaction with the packet size larger than 8 bits,
+ * the bytes are stored in the order of the LSB (least significant byte) first.
+ * The packet is formed with the first byte will be in LSB and then next byte 
+ * will be in the next LSB towards the MSB.
+ *  
+ * For example, if one packet needs to be sent and its size is 20 bits, 
+ * then it will require the 3 bytes in the \a pWriteBuffer and arrangement of
+ * the data  are as follows:
+ * - The packet is 0x000ABCDE (Packet with length of 20 bit).
+ * - pWriteBuff[0] = 0xDE
+ * - pWriteBuff[1] = 0xBC
+ * - pWtriteBuff[2] = 0x0A
+ *
+ * The most significant bit will be transmitted first, i.e., bit20 is transmitted 
+ * first and bit0 will be transmitted last.
+ *
+ * @par Transfer Size Limitations
+ *
+ * The limitation on the maximum transfer size of SPI slave communication
+ * depends upon the hardware. The maximum size of byte transfer is 64 K bytes
+ * if the number of packets requested is a multiple of: 
+ * - 4 for 8-bit packet length, or 
+ * - 2 for 16-bit packet length, or 
+ * - any number of packets for 32-bit packet length. 
+ *
+ * For all other cases, the maximum transfer bytes size is limited to 16 K
+ * packets, that is:
+ * <pre>
+ * 16K*((PacketBitLength +7)/8))
+ * </pre>
+ * 
+ * For the example: 
+ * - Non-multiples of 4 for the 8-bit packet length 
+ * - Non multiples of 2 for the 16-bit packet length 
+ * - Any other bit length except for the 32-bit packet length
+ * 
+ * This limitation comes from the:
+ * - Maximum HW DMA transfer of 64 KB
+ * - Maximum packet transfer for HW S-LINK controller of 64 K packets 
+ * - The design of packed/unpacked format of the S-LINK controller
+ *
+ * @par CAIF Use Case
+ * 
+ * The following describes a typical use case for the CAIF interface. The steps
+ * for doing the transfer are:
+ * -# ACPU calls the NvOdmSpiSlaveStartTransaction() to configure the SPI 
+ * controller to set in the receive or transmit mode and make ready for the 
+ * data transfer.
+ * -# ACPU then send the signal to the CCPU to send the SPICLK (by activating 
+ * the SPI_INT) and start the transaction. CCPU get this signal and start sending 
+ * SPICLK.
+ * -# ACPU will call the NvOdmSpiSlaveGetTransactionData() to get the 
+ * data/information about the transaction.
+ * -# After completion of the transfer ACPU inactivate the SPI_INT.
+ *
+ * @param hOdmSpi The SPI handle allocated in a call to NvOdmSpiSlaveOpen().
+ * @param ChipSelectId The chip select ID on which device is connected.
+ * @param ClockSpeedInKHz The clock speed in kHz on which device can communicate.
+ * @param IsReadTransfer Tells that whether or not the read transfer is required.
+ * If it is NV_TRUE then read transfer is required and the read data will be 
+ * available in the local buffer of the driver. The client will get the received
+ * data after calling the \c NvRmSpiGetTransactionData() function.
+ * @param pWriteBuffer A pointer to a buffer from which to obtain write data. 
+ * If this pointer is NULL, the write data will be all zeros.
+ * @param BytesRequested The size of \a pReadBuffer and \a pWriteBuffer buffers
+ * in bytes.
+ * @param PacketSizeInBits The packet size in bits of each SPI transaction.
+ *
+ * @return NV_TRUE if successful, or NV_FALSE otherwise.
+ */
+ NvBool NvOdmSpiSlaveStartTransaction( 
+    NvOdmServicesSpiHandle hOdmSpi,
+    NvU32 ChipSelectId,
+    NvU32 ClockSpeedInKHz,
+    NvBool IsReadTransfer,
+    NvU8 * pWriteBuffer,
+    NvU32 BytesRequested,
+    NvU32 PacketSizeInBits );
+
+/**
+ * Gets the SPI transaction status that is started for the slave mode and waits,
+ * if required, until the transfer completes for a given timeout error.
+ * If a read transaction has been started, then it returns the receive data to 
+ * the client.
+ *
+ * This is a blocking API and waits for the data transfer completion until the
+ * transfer completes or a timeout happens.
+ *
+ * @see NvOdmSpiSlaveStartTransaction
+ *
+ * @param hOdmSpi The SPI handle allocated in a call to NvOdmSpiSlaveOpen().
+ * @param pReadBuffer A pointer to a buffer to be filled in with read data. If this
+ * pointer is NULL, the read data will be discarded.
+ * @param BytesRequested The size of \a pReadBuffer and \a pWriteBuffer buffers
+ * in bytes.
+ * @param pBytesTransfererd A pointer to the number of bytes transferred.
+ * @param WaitTimeout The timeout in millisecond to wait for the transaction to be 
+ * completed.
+ *
+ * @return NV_TRUE if successful, or NV_FALSE otherwise.
+ *
+ */
+  NvBool NvOdmSpiSlaveGetTransactionData( 
+    NvOdmServicesSpiHandle hOdmSpi,
+    NvU8 * pReadBuffer,
+    NvU32 BytesRequested,
+    NvU32 * pBytesTransfererd,
+    NvU32 WaitTimeout );
+
+/**
+ * Sets the signal mode for the SPI communication for a given chip select.
+ * After calling this API, further communication happens with the newly 
+ * configured signal modes.
+ * The default value of the signal mode is taken from ODM Query, and this
+ * API overrides the signal mode that is read from the query.
+ *
+ * @param hOdmSpi The SPI handle allocated in a call to NvOdmSpiOpen().
+ * @param ChipSelectId The chip select ID to which the device is connected.
+ * @param SpiSignalMode The ODM signal mode to be set.
+ *
+ */
+void
+NvOdmSpiSetSignalMode(
+    NvOdmServicesSpiHandle hOdmSpi,
+    NvU32 ChipSelectId,
+    NvOdmQuerySpiSignalMode SpiSignalMode);
+
+/// Contains the error flags for the I2C transaction.
+typedef enum
+{
+    NvOdmI2cStatus_Success = 0,
+    NvOdmI2cStatus_Timeout,
+    NvOdmI2cStatus_SlaveNotFound,
+    NvOdmI2cStatus_InvalidTransferSize,
+    NvOdmI2cStatus_ReadFailed,
+    NvOdmI2cStatus_WriteFailed,
+    NvOdmI2cStatus_InternalError,
+    NvOdmI2cStatus_ArbitrationFailed,
+    NvOdmI2cStatus_Force32 = 0x7FFFFFFF
+} NvOdmI2cStatus;
+
+/// Flag to indicate the I2C write/read operation.
+#define NVODM_I2C_IS_WRITE            0x00000001
+/// Flag to indicate the I2C slave address type as 10-bit or 7-bit.
+#define NVODM_I2C_IS_10_BIT_ADDRESS   0x00000002
+/// Flag to indicate the I2C transaction with repeat start.
+#define NVODM_I2C_USE_REPEATED_START  0x00000004
+/// Flag to indicate that the I2C slave will not generate ACK.
+#define NVODM_I2C_NO_ACK              0x00000008
+/// Flag to indicate software I2C using GPIO.
+#define NVODM_I2C_SOFTWARE_CONTROLLER 0x00000010
+
+
+/// Contians the I2C transaction details.
+typedef struct
+{
+    /// Flags to indicate the transaction details, like write/read operation,
+    /// slave address type 10-bit or 7-bit and the transaction uses repeat
+    /// start or a normal transaction.
+    NvU32 Flags;
+    /// I2C slave device address.
+    NvU32 Address;
+    /// Number of bytes to be transferred.
+    NvU32 NumBytes;
+    /// Send/receive buffer. For I2C send operation this buffer should be
+    /// filled with the data to be sent to the slave device. For I2C receive
+    /// operation this buffer is filled with the data received from the slave device.
+    NvU8 *Buf;
+} NvOdmI2cTransactionInfo;
+
+/**
+ * Initializes and opens the I2C channel. This function allocates the
+ * handle for the I2C channel and provides it to the client.
+ *
+ * @see NvOdmI2cClose
+ *
+ * @param OdmIoModuleId  The ODM I/O module for I2C.
+ * @param instance The instance of the I2C driver to be opened.
+ *
+ * @return The handle to the I2C controller, or NULL if an error occurred.
+ */
+NvOdmServicesI2cHandle
+NvOdmI2cOpen(
+    NvOdmIoModule OdmIoModuleId,
+    NvU32 instance);
+
+/**
+ * Obtains a handle that can be used to access one of the I2C controllers, 
+ * for I2C controllers which are multiplexed between multiple pin mux 
+ * configurations. The I2C controller's pin mux will be reset to the specified 
+ * value every transaction, so that two handles to the same controller may 
+ * safely interleave across pin mux configurations.
+ *
+ * The ODM pin mux query for the specified controller must be
+ * NvOdmI2cPinMap_Multiplexed in order to create a handle using this function.
+ *
+ * There may be one or more instances of the I2C, depending upon the SOC,
+ * and these instances start from 0.
+ *
+ * Currently, this function is only supported for OdmIoModule_I2C, instance 1.
+ *
+ * @see NvOdmI2cClose
+ *
+ * @param OdmIoModule  The ODM I/O module for the I2C.
+ * @param ControllerId  The I2C controlled ID for which a handle is required.
+ *     Valid I2C controller IDs start from 0.
+ * @param PinMap The pin mux configuration to use for every transaction.
+ *
+ * @return The handle to the I2C controller, or NULL if an error occurred.
+ */
+NvOdmServicesI2cHandle 
+NvOdmI2cPinMuxOpen(NvOdmIoModule OdmIoModule,
+                   NvU32 ControllerId,
+                   NvOdmI2cPinMap PinMap);
+
+/**
+ * Closes the I2C channel. This function frees the memory allocated for
+ * the I2C handle and de-initializes the I2C ODM channel.
+ *
+ * @see NvOdmI2cOpen
+ *
+ * @param hOdmI2c The handle to the I2C channel.
+ */
+void NvOdmI2cClose(NvOdmServicesI2cHandle hOdmI2c);
+
+/**
+ * Does the I2C send or receive transactions with the slave deivces. This is a
+ * blocking call (with timeout). This API works for both the normal I2C transactions
+ * or I2C transactions in repeat start mode.
+ *
+ * For the I2C transactions with slave devices, a pointer to the list of required
+ * transactions must be passed and the corresponding number of transactions must
+ * be passed.
+ *
+ * The transaction information structure contains the flags (to indicate the
+ * transaction information, such as read or write transaction, transaction is with
+ * repeat-start or normal transaction and the slave device address type is 7-bit or
+ * 10-bit), slave deivce address, buffer to be transferred and number of bytes
+ * to be transferred.
+ *
+ * @param hOdmI2c The handle to the I2C channel.
+ * @param TransactionInfo A pointer to the array of I2C transaction structures.
+ * @param NumberOfTransactions The number of I2C transactions.
+ * @param ClockSpeedKHz Specifies the clock speed for the I2C transactions.
+ * @param WaitTimeoutInMilliSeconds The timeout in milliseconds.
+ *  ::NV_WAIT_INFINITE specifies to wait forever.
+ *
+ * @retval NvOdmI2cStatus_Success If successful, or the appropriate error code.
+ */
+NvOdmI2cStatus
+NvOdmI2cTransaction(
+    NvOdmServicesI2cHandle hOdmI2c,
+    NvOdmI2cTransactionInfo *TransactionInfo,
+    NvU32 NumberOfTransactions,
+    NvU32 ClockSpeedKHz,
+    NvU32 WaitTimeoutInMilliSeconds);
+
+/**
+ *  Defines the PMU VDD rail capabilities.
+ */
+typedef struct NvOdmServicesPmuVddRailCapabilitiesRec
+{
+    /// Specifies ODM protection attribute; if \c NV_TRUE PMU hardware
+    ///  or ODM Kit would protect this voltage from being changed by NvDdk client.
+    NvBool RmProtected;
+
+    /// Specifies the minimum voltage level in mV.
+    NvU32 MinMilliVolts;
+
+    /// Specifies the step voltage level in mV.
+    NvU32 StepMilliVolts;
+
+    /// Specifies the maximum voltage level in mV.
+    NvU32 MaxMilliVolts;
+
+    /// Specifies the request voltage level in mV.
+    NvU32 requestMilliVolts;
+
+} NvOdmServicesPmuVddRailCapabilities;
+
+/// Special level to indicate voltage plane is disabled.
+#define NVODM_VOLTAGE_OFF (0UL)
+
+/**
+ * Initializes and opens the PMU driver. The handle that is returned by this
+ * driver is used for all the other PMU operations.
+ *
+ * @see NvOdmPmuClose
+ *
+ * @return The handle to the PMU driver, or NULL if an error occurred.
+ */
+NvOdmServicesPmuHandle NvOdmServicesPmuOpen(void);
+
+/**
+ * Closes the PMU handle.
+ *
+ * @see NvOdmServicesPmuOpen
+ *
+ * @param handle The handle to the PMU driver.
+ */
+void NvOdmServicesPmuClose(NvOdmServicesPmuHandle handle);
+
+/**
+ * Gets capabilities for the specified PMU rail.
+ *
+ * @param handle The handle to the PMU driver.
+ * @param vddId The ODM-defined PMU rail ID.
+ * @param pCapabilities A pointer to the targeted
+ *  capabilities returned by the ODM.
+ *
+ */
+void NvOdmServicesPmuGetCapabilities(
+        NvOdmServicesPmuHandle handle,
+        NvU32 vddId,
+        NvOdmServicesPmuVddRailCapabilities * pCapabilities );
+
+/**
+ * Gets current voltage level for the specified PMU rail.
+ *
+ * @param handle The handle to the PMU driver.
+ * @param vddId The ODM-defined PMU rail ID.
+ * @param pMilliVolts A pointer to the voltage level returned
+ *  by the ODM.
+ */
+void NvOdmServicesPmuGetVoltage(
+        NvOdmServicesPmuHandle handle,
+        NvU32 vddId,
+        NvU32 * pMilliVolts );
+
+/**
+ * Sets new voltage level for the specified PMU rail.
+ *
+ * @param handle The handle to the PMU driver.
+ * @param vddId The ODM-defined PMU rail ID.
+ * @param MilliVolts The new voltage level to be set in millivolts (mV).
+ *  Set to ::NVODM_VOLTAGE_OFF to turn off the target voltage.
+ * @param pSettleMicroSeconds A pointer to the settling time in microseconds (uS),
+ *  which is the time for supply voltage to settle after this function
+ *  returns; this may or may not include PMU control interface transaction time,
+ *  depending on the ODM implementation. If NULL this parameter is ignored.
+ */
+void NvOdmServicesPmuSetVoltage(
+        NvOdmServicesPmuHandle handle,
+        NvU32 vddId,
+        NvU32 MilliVolts,
+        NvU32 * pSettleMicroSeconds );
+
+/**
+ * Configures SoC power rail controls for the upcoming PMU voltage transition.
+ *
+ * @note Should be called just before PMU rail On/Off, or Off/On transition.
+ *  Should not be called if rail voltage level is changing within On range.
+ * 
+ * @param handle The handle to the PMU driver.
+ * @param vddId The ODM-defined PMU rail ID.
+ * @param Enable Set NV_TRUE if target voltage is about to be turned On, or
+ *  NV_FALSE if target voltage is about to be turned Off.
+ */
+void NvOdmServicesPmuSetSocRailPowerState(
+        NvOdmServicesPmuHandle handle,
+        NvU32 vddId, 
+        NvBool Enable );
+
+/**
+ * Defines battery instances.
+ */
+typedef enum
+{
+    /// Specifies main battery.
+    NvOdmServicesPmuBatteryInst_Main,
+
+    /// Specifies backup battery.
+    NvOdmServicesPmuBatteryInst_Backup,
+
+    /// Ignore -- Forces compilers to make 32-bit enums.
+    NvOdmServicesPmuBatteryInstance_Force32 = 0x7FFFFFFF
+} NvOdmServicesPmuBatteryInstance;
+
+/**
+ * Gets the battery status.
+ *
+ * @param handle The handle to the PMU driver.
+ * @param batteryInst The battery type.
+ * @param pStatus A pointer to the battery
+ *  status returned by the ODM.
+ * 
+ * @return NV_TRUE if successful, or NV_FALSE otherwise.
+ */
+NvBool 
+NvOdmServicesPmuGetBatteryStatus(
+    NvOdmServicesPmuHandle handle,
+    NvOdmServicesPmuBatteryInstance batteryInst,
+    NvU8 * pStatus);
+
+/**
+ * Defines battery data.
+ */
+typedef struct NvOdmServicesPmuBatteryDataRec
+{
+    /// Specifies battery life percent.
+    NvU32 batteryLifePercent;
+
+    /// Specifies battery life time.
+    NvU32 batteryLifeTime;
+
+    /// Specifies voltage.
+    NvU32 batteryVoltage;
+    
+    /// Specifies battery current.
+    NvS32 batteryCurrent;
+
+    /// Specifies battery average current.
+    NvS32 batteryAverageCurrent;
+
+    /// Specifies battery interval.
+    NvU32 batteryAverageInterval;
+
+    /// Specifies the mAH consumed.
+    NvU32 batteryMahConsumed;
+
+    /// Specifies battery temperature.
+    NvU32 batteryTemperature;
+} NvOdmServicesPmuBatteryData;
+
+/**
+ * Gets the battery data.
+ *
+ * @param handle The handle to the PMU driver.
+ * @param batteryInst The battery type.
+ * @param pData A pointer to the battery
+ *  data returned by the ODM.
+ * 
+ * @return NV_TRUE if successful, or NV_FALSE otherwise.
+ */
+NvBool
+NvOdmServicesPmuGetBatteryData(
+    NvOdmServicesPmuHandle handle,
+    NvOdmServicesPmuBatteryInstance batteryInst,
+    NvOdmServicesPmuBatteryData * pData);
+
+/**
+ * Gets the battery full lifetime.
+ *
+ * @param handle The handle to the PMU driver.
+ * @param batteryInst The battery type.
+ * @param pLifeTime A pointer to the battery
+ *  full lifetime returned by the ODM.
+ */
+void
+NvOdmServicesPmuGetBatteryFullLifeTime(
+    NvOdmServicesPmuHandle handle,
+    NvOdmServicesPmuBatteryInstance batteryInst,
+    NvU32 * pLifeTime);
+
+/**
+ * Defines battery chemistry.
+ */
+typedef enum
+{
+    /// Specifies an alkaline battery.
+    NvOdmServicesPmuBatteryChemistry_Alkaline,
+
+    /// Specifies a nickel-cadmium (NiCd) battery.
+    NvOdmServicesPmuBatteryChemistry_NICD,
+
+    /// Specifies a nickel-metal hydride (NiMH) battery.
+    NvOdmServicesPmuBatteryChemistry_NIMH,
+
+    /// Specifies a lithium-ion (Li-ion) battery.
+    NvOdmServicesPmuBatteryChemistry_LION,
+
+    /// Specifies a lithium-ion polymer (Li-poly) battery.
+    NvOdmServicesPmuBatteryChemistry_LIPOLY,
+
+    /// Specifies a zinc-air battery.
+    NvOdmServicesPmuBatteryChemistry_XINCAIR,
+
+    /// Ignore -- Forces compilers to make 32-bit enums.
+    NvOdmServicesPmuBatteryChemistry_Force32 = 0x7FFFFFFF
+} NvOdmServicesPmuBatteryChemistry;
+
+/**
+ * Gets the battery chemistry.
+ *
+ * @param handle The handle to the PMU driver.
+ * @param batteryInst The battery type.
+ * @param pChemistry A pointer to the battery
+ *  chemistry returned by the ODM.
+ */
+void
+NvOdmServicesPmuGetBatteryChemistry(
+    NvOdmServicesPmuHandle handle,
+    NvOdmServicesPmuBatteryInstance batteryInst,
+    NvOdmServicesPmuBatteryChemistry * pChemistry);
+
+/**
+ * Defines the charging path.
+ */
+typedef enum
+{
+    /// Specifies external wall plug charger.
+    NvOdmServicesPmuChargingPath_MainPlug, 
+
+    /// Specifies external USB bus charger.
+    NvOdmServicesPmuChargingPath_UsbBus,
+
+    /// Ignore -- Forces compilers to make 32-bit enums.
+    NvOdmServicesPmuChargingPath_Force32 = 0x7FFFFFFF
+} NvOdmServicesPmuChargingPath;
+
+/** 
+* Sets the charging current limit. 
+* 
+* @param handle The Rm device handle.
+* @param ChargingPath The charging path. 
+* @param ChargingCurrentLimitMa The charging current limit in mA. 
+* @param ChargerType The charger type.
+*/
+void 
+NvOdmServicesPmuSetChargingCurrentLimit( 
+    NvOdmServicesPmuHandle handle,
+    NvOdmServicesPmuChargingPath ChargingPath,
+    NvU32 ChargingCurrentLimitMa,
+    NvOdmUsbChargerType ChargerType);
+
+/**
+ * Obtains a handle to set or get state of keys, for example, the state of the
+ * hold switch.
+ *
+ * @see NvOdmServicesKeyListClose()
+ *
+ * @return A handle to the key-list, or NULL if this open call fails.
+ */
+NvOdmServicesKeyListHandle
+NvOdmServicesKeyListOpen(void);
+
+/**
+ * Releases the handle obtained during the NvOdmServicesKeyListOpen() call and
+ * any other resources allocated.
+ *
+ * @param handle The handle returned from the \c NvOdmServicesKeyListOpen call.
+ */
+void NvOdmServicesKeyListClose(NvOdmServicesKeyListHandle handle);
+
+/**
+ * Searches the list of keys present and returns the value of the appropriate
+ * key.
+ * @param handle The handle obtained from NvOdmServicesKeyListOpen().
+ * @param KeyID The ID of the key whose value is required.
+ *
+ * @return The value of the corresponding key, or 0 if the key is not
+ * present in the list.
+ */
+NvU32
+NvOdmServicesGetKeyValue(
+            NvOdmServicesKeyListHandle handle,
+            NvU32 KeyID);
+
+/**
+ * Searches the list of keys present and sets the value of the key to the value
+ * given. If the key is not present, it adds the key to the list and sets the
+ * value.
+ * @param handle The handle obtained from NvOdmServicesKeyListOpen().
+ * @param Key The ID of the key whose value is to be set.
+ * @param Value The value to be set for the corresponding key.
+ *
+ * @return NV_TRUE if successful, or NV_FALSE otherwise.
+ */
+NvBool
+NvOdmServicesSetKeyValuePair(
+            NvOdmServicesKeyListHandle handle,
+            NvU32 Key,
+            NvU32 Value);
+
+/**
+ * @brief Defines the possible PWM modes.
+ */
+
+typedef enum
+{
+    /// Specifies Pwm disabled mode.
+    NvOdmPwmMode_Disable = 1,
+
+    /// Specifies Pwm enabled mode.
+    NvOdmPwmMode_Enable,
+
+    /// Specifies Blink LED enabled mode
+    NvOdmPwmMode_Blink_LED,
+
+    /// Specifies Blink output 32KHz clock enable mode
+    NvOdmPwmMode_Blink_32KHzClockOutput,
+
+    /// Specifies Blink disabled mode
+    NvOdmPwmMode_Blink_Disable,
+
+    NvOdmPwmMode_Force32 = 0x7fffffffUL
+
+} NvOdmPwmMode;
+
+/**
+ * @brief Defines the possible PWM output pin.
+ */
+
+typedef enum
+{
+    /// Specifies PWM Output-0.
+    NvOdmPwmOutputId_PWM0 = 1,
+
+    /// Specifies PWM Output-1.
+    NvOdmPwmOutputId_PWM1,
+
+    /// Specifies PWM Output-2.
+    NvOdmPwmOutputId_PWM2,
+
+    /// Specifies PWM Output-3.
+    NvOdmPwmOutputId_PWM3,
+
+    /// Specifies PMC Blink LED.
+    NvOdmPwmOutputId_Blink, 
+
+    NvOdmPwmOutputId_Force32 = 0x7fffffffUL
+
+} NvOdmPwmOutputId;
+
+/**
+ * Creates and opens a PWM handle. The handle can be used to
+ * access PWM functions.
+ *
+ * @note Only the service client knows when the service can go idle,
+ * like in the case of vibrator, so the client suspend entry code
+ * must call NvOdmPwmClose() to close the PWM service.
+ *
+ * @return The handle to the PWM controller, or NULL if an error occurred.
+ */
+NvOdmServicesPwmHandle NvOdmPwmOpen(void);
+
+/**
+ * Releases a handle to a PWM controller. This API must be called once per
+ * successful call to NvOdmPwmOpen().
+ *
+ * @param hOdmPwm The handle to the PWM controller.
+ */
+void NvOdmPwmClose(NvOdmServicesPwmHandle hOdmPwm);
+
+/**
+ *  @brief Configures PWM module as disable/enable. This API is also
+ *  used to set the PWM duty cycle and frequency. Beside that, it is 
+ *  used to configure PMC' blinking LED if OutputId is 
+ *  NvOdmPwmOutputId_Blink
+ *
+ *  @param hOdmPwm The PWM handle obtained from NvOdmPwmOpen().
+ *  @param OutputId The PWM output pin to configure. Allowed values are
+ *   defined in ::NvOdmPwmOutputId.
+ *  @param Mode The mode type to configure. Allowed values are
+ *   defined in ::NvOdmPwmMode.
+ *  @param DutyCycle The duty cycle is an unsigned 15.16 fixed point
+ *   value that represents the PWM duty cycle in percentage range from
+ *   0.00 to 100.00. For example, 10.5 percentage duty cycle would be
+ *   represented as 0x000A8000. This parameter is ignored if NvOdmPwmMode
+ *   is NvOdmMode_Blink_32KHzClockOutput or NvOdmMode_Blink_Disable
+ *  @param pRequestedFreqHzOrPeriod A pointer to the request frequency in Hz
+ *   or period in second
+ *   A requested frequency value beyond the maximum supported value will be
+ *   clamped to the maximum supported value. If \em pRequestedFreqHzOrPeriod 
+ *   is NULL, it returns the maximum supported frequency. This parameter is 
+ *   ignored if NvOdmPwmMode is NvOdmMode_Blink_32KHzClockOutput or
+ *   NvOdmMode_Blink_Disable
+ *  @param pCurrentFreqHzOrPeriod A pointer to the returned frequency of 
+ *   that mode. If PMC Blink LED is used then it is the pointer to the returns 
+ *   period time. This parameter is ignored if NvOdmPwmMode is
+ *   NvOdmMode_Blink_32KHzClockOutput or NvOdmMode_Blink_Disable
+ */
+void
+NvOdmPwmConfig(NvOdmServicesPwmHandle hOdmPwm,
+    NvOdmPwmOutputId OutputId, 
+    NvOdmPwmMode Mode,            
+    NvU32 DutyCycle,
+    NvU32 *pRequestedFreqHzOrPeriod,
+    NvU32 *pCurrentFreqHzOrPeriod);
+
+/**
+ * Enables and disables external clock interfaces (e.g., CDEV and CSUS pins)
+ * for the specified peripheral. External clock sources should be enabled
+ * prior to programming peripherals reliant on them. If multiple peripherals use
+ * the same external clock source, it is safe to call this API multiple times.
+ *
+ * @param Guid The ODM-defined GUID of the peripheral to be configured. The
+ *             peripheral should have an @see NvOdmIoAddress entry for the
+ *             NvOdmIoModule_ExternalClock device interface. If multiple
+ *             external clock interfaces are specified, all will be
+ *             enabled (disabled).
+ *
+ * @param EnableTristate NV_TRUE will tristate the specified clock sources,
+ *             NV_FALSE will drive them.
+ *  
+ * @param pInstances Returns the list of clocks that were enabled.
+ *  
+ * @param pFrequencies Returns the frequency, in kHz, that is 
+ *                     being output on each clock pin
+ *  
+ * @param pNum Returns the number of clocks that were enabled.
+ *
+ * @return NV_TRUE if successful, or NV_FALSE otherwise.
+ */
+NvBool
+NvOdmExternalClockConfig(
+    NvU64 Guid,
+    NvBool EnableTristate,
+    NvU32 *pInstances,
+    NvU32 *pFrequencies,
+    NvU32 *pNum);
+
+/**
+ *  Defines SoC strap groups.
+ */
+typedef enum
+{
+    /// Specifies the ram_code strap group.
+    NvOdmStrapGroup_RamCode = 1,
+
+    NvOdmStrapGroup_Num,
+    NvOdmStrapGroup_Force32 = 0x7FFFFFFF
+} NvOdmStrapGroup;
+
+/**
+ * Gets SoC strap value for the given strap group.
+ * 
+ * @note The strap assignment on each platform must be consistent with SoC
+ *  bootrom specifications and platform-specific BCT contents. The strap
+ *  value usage in ODM queries, however, is not limited to bootrom defined
+ *  functionality. The mapping between strap values and platforms is the ODM's
+ *  responsibility. ODMs should also ensure that they are using strap groups
+ *  that match the SOC in their product.
+ * 
+ * @param StrapGroup The strap group to be read.
+ * @param pStrapValue A pointer to the returned strap group value.
+ *  This value can be used by ODM queries to identify ODM platforms and to
+ *  provide the respective configuration settings.
+ *  
+ * @return NV_TRUE if successful, or NV_FALSE otherwise.
+ */
+NvBool NvOdmGetStraps(NvOdmStrapGroup StrapGroup, NvU32* pStrapValue);
+
+/**
+ * File input/output.
+ */
+typedef void* NvOdmOsFileHandle;
+
+/**
+ *  Defines the OS file types.
+ */
+typedef enum
+{
+    NvOdmOsFileType_Unknown = 0,
+    NvOdmOsFileType_File,
+    NvOdmOsFileType_Directory,
+    NvOdmOsFileType_Fifo,
+
+    NvOdmOsFileType_Force32 = 0x7FFFFFFF
+} NvOdmOsFileType;
+
+/**
+ *  Defines the OS status type.
+ */
+typedef struct NvOdmOsStatTypeRec
+{
+    NvU64 size;
+    NvOdmOsFileType type;
+} NvOdmOsStatType;
+
+/** Open a file with read permissions. */
+#define NVODMOS_OPEN_READ    0x1
+
+/** Open a file with write persmissions. */
+#define NVODMOS_OPEN_WRITE   0x2
+
+/** Create a file if is not present on the file system. */
+#define NVODMOS_OPEN_CREATE  0x4
+
+/**
+ *  Opens a file stream.
+ *
+ *  If the ::NVODMOS_OPEN_CREATE flag is specified, ::NVODMOS_OPEN_WRITE must also
+ *  be specified.
+ *
+ *  If ::NVODMOS_OPEN_WRITE is specified the file will be opened for write and
+ *  will be truncated if it was previously existing.
+ *
+ *  If ::NVODMOS_OPEN_WRITE and ::NVODMOS_OPEN_READ is specified the file will not
+ *  be truncated.
+ *
+ *  @param path A pointer to the path to the file.
+ *  @param flags ORed flags for the open operation (NVODMOS_OPEN_*).
+ *  @param file [out] A pointer to the file that will be opened, if successful.
+ *
+ *  @return NV_TRUE if successful, or NV_FALSE otherwise.
+ */
+NvBool
+NvOdmOsFopen(const char *path, NvU32 flags, NvOdmOsFileHandle *file);
+
+/**
+ *  Closes a file stream.
+ *  Passing in a NULL handle is okay.
+ *
+ *  @param stream The file stream to close.
+ */
+void NvOdmOsFclose(NvOdmOsFileHandle stream);
+
+/**
+ *  Writes to a file stream.
+ *
+ *  @param stream The file stream.
+ *  @param ptr A pointer to the data to write.
+ *  @param size The length of the write.
+ *
+ *  @return NV_TRUE if successful, or NV_FALSE otherwise.
+ */
+NvBool
+NvOdmOsFwrite(NvOdmOsFileHandle stream, const void *ptr, size_t size);
+
+/**
+ *  Reads a file stream.
+ *
+ *  To detect short reads (less that specified amount), pass in \a bytes
+ *  and check its value to the expected value. The \a bytes parameter may
+ *  be NULL.
+ *
+ *  @param stream The file stream.
+ *  @param ptr A pointer to the buffer for the read data.
+ *  @param size The length of the read.
+ *  @param bytes [out] A pointer to the number of bytes read -- may be NULL.
+ *
+ *  @return NV_TRUE if successful, or NV_FALSE otherwise.
+ */
+NvBool
+NvOdmOsFread(NvOdmOsFileHandle stream, void *ptr, size_t size, size_t *bytes);
+
+/**
+ *  Gets file information.
+ *
+ *  @param filename A pointer to the file to get information about.
+ *  @param stat [out] A pointer to the information structure.
+ *
+ *  @return NV_TRUE if successful, or NV_FALSE otherwise.
+ */
+NvBool
+NvOdmOsStat(const char *filename, NvOdmOsStatType *stat);
+
+/**
+ * Enables or disables USB OTG circuitry.
+ *
+ * @param Enable NV_TRUE to enable, or NV_FALSE to disable.
+ */
+void NvOdmEnableOtgCircuitry(NvBool Enable);
+
+/**
+ * Checks whether or not USB is connected.
+ *
+ * @pre The USB circuit is enabled by calling NvOdmEnableOtgCircuitry().
+ * To reduce power consumption, disable the USB circuit when not connected
+ * by calling \c NvOdmEnableOtgCircuitry(NV_FALSE).
+ *
+ * @return NV_TRUE if USB is successfully connected, otherwise NV_FALSE.
+ */
+NvBool NvOdmUsbIsConnected(void);
+
+/**
+ * Checks the current charging type.
+ *
+ * @pre The USB circuit is enabled by calling NvOdmEnableOtgCircuitry().
+ * To reduce power consumption, disable the USB circuit when not connected
+ * by calling \c NvOdmEnableOtgCircuitry(NV_FALSE).
+ *
+ * @param Instance Set to 0 by default.
+ * @return The current charging type.
+ */
+NvOdmUsbChargerType NvOdmUsbChargingType(NvU32 Instance);
+
+/**
+ * Enables/Disables the USB power rail.
+ *
+ * @param Enable NV_TRUE to enable, or NV_FALSE to disable.
+ */
+void NvOdmEnableUsbPhyPowerRail(NvBool Enable);
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*@}*/
+/** @} */
+
+#endif // INCLUDED_NVODM_SERVICES_H
diff --git a/arch/arm/mach-tegra/include/nvodm_tmon.h b/arch/arm/mach-tegra/include/nvodm_tmon.h
new file mode 100644
index 000000000000..ebe90f2b7079
--- /dev/null
+++ b/arch/arm/mach-tegra/include/nvodm_tmon.h
@@ -0,0 +1,296 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/** 
+ * @file
+ * <b>NVIDIA Tegra ODM Kit:
+ *         Temperature Monitor Interface</b>
+ *
+ * @b Description: Defines the ODM interface for Temperature Monitor (TMON).
+ * 
+ */
+
+#ifndef INCLUDED_NVODM_TMON_H
+#define INCLUDED_NVODM_TMON_H
+
+#include "nvcommon.h"
+#include "nvodm_services.h"
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+/**
+ * @defgroup nvodm_tmon Temperature Monitor Adaptation Interface 
+ *   
+ * This is the temperature monitor (TMON) ODM adaptation interface, which
+ * handles the abstraction of external devices monitoring temperature zones
+ * on NVIDIA SoC based platforms. For the clients of this API, each zone has
+ * its own monitoring device. Dependencies introduced by multi-channel devices
+ * capable of monitoring several zones are resolved inside the implementation
+ * layer.
+ * 
+ * @ingroup nvodm_adaptation
+ * @{
+ */
+
+/**
+ * Defines an opaque handle for TMON device.
+ */
+typedef struct NvOdmTmonDeviceRec *NvOdmTmonDeviceHandle;
+
+/**
+ * Defines an opaque handle to the TMON interrupt interface.
+ */
+typedef struct NvOdmTmonIntrRec *NvOdmTmonIntrHandle;
+
+/**
+ * Defines temperature zones.
+ */
+typedef enum
+{
+    /// Specifies ambient temperature zone.
+    NvOdmTmonZoneID_Ambient = 1,
+
+    /// Specifies SoC core temperature zone.
+    NvOdmTmonZoneID_Core,
+
+    NvOdmTmonZoneID_Num,
+    /// Ignore -- Forces compilers to make 32-bit enums.
+    NvOdmTmonZoneID_Force32 = 0x7FFFFFFFUL
+} NvOdmTmonZoneID;
+
+/**
+ * Defines temperature monitoring configuration parameters.
+ */
+typedef enum
+{
+    /// Identifies temperature sampling interval in ms.
+    NvOdmTmonConfigParam_SampleMs = 1,
+
+    /// Identifies High temperature boundary for TMON out of limit
+    ///  interrupt (in degrees C).
+    NvOdmTmonConfigParam_IntrLimitHigh,
+
+    /// Identifies Low temperature boundary for TMON out of limit
+    ///  interrupt (in degrees C).
+    NvOdmTmonConfigParam_IntrLimitLow,
+
+    /// Identifies temperature threshold for TMON comparator that
+    ///  controls h/w critical shutdown mechanism (in degrees C).
+    NvOdmTmonConfigParam_HwLimitCrit,
+
+    NvOdmTmonConfigParam_Num,
+    /// Ignore -- Forces compilers to make 32-bit enums.
+    NvOdmTmonConfigParam_Force32 = 0x7FFFFFFFUL
+} NvOdmTmonConfigParam;
+
+/// Special value for configuration parameters.
+#define ODM_TMON_PARAMETER_UNSPECIFIED (0x7FFFFFFF)
+
+/**
+ * Holds configuration parameter capabilities.
+ */
+typedef struct NvOdmTmonParameterCapsRec
+{ 
+    /// Specifies maximum parameter value (units depend on the parameter).
+    NvS32 MaxValue;
+
+    /// Specifies minimum parameter value (units depend on the parameter).
+    NvS32 MinValue;
+
+    /// Specifies ODM protection attribute; if \c NV_TRUE TMON ODM Kit would
+    ///  not allow to change the parameter.
+    NvBool OdmProtected;
+} NvOdmTmonParameterCaps;
+
+/**
+ * Holds temperature monitoring device capabilities.
+ */
+typedef struct NvOdmTmonCapabilitiesRec
+{ 
+    /// Specifies maximum temperature limit for TMON operations (in degrees C).
+    NvS32 Tmax;
+
+    /// Specifies minimum temperature limit for TMON operations (in degrees C).
+    NvS32 Tmin;
+
+    /// Specifies support for TMON out of limit interrupt.
+    NvBool IntrSupported;
+
+    /// Specifies support for TMON hardware critical shutdown mechanism.
+    NvBool HwCriticalSupported;
+
+    /// Specifies support for TMON hardware auto-cooling mechanism (e.g., fan).
+    NvBool HwCoolingSupported;
+} NvOdmTmonCapabilities;
+
+
+/**
+ * Gets a handle to the TMON in the specified zone.
+ *
+ * @param ZoneId The targeted temperature zone.
+ * 
+ * @return TMON handle, NULL if zone is not monitored.
+ */
+NvOdmTmonDeviceHandle
+NvOdmTmonDeviceOpen(NvOdmTmonZoneID ZoneId);
+
+/**
+ * Closes the TMON handle. 
+ *
+ * @param hTmon The TMON handle to be closed.
+ *  If NULL, this API has no effect.
+ */
+void NvOdmTmonDeviceClose(NvOdmTmonDeviceHandle hTmon);
+
+/**
+ * Gets TMON device capabilities.
+ *
+ * @param hTmon A handle to the TMON device.
+ * @param pCaps A pointer to the TMON device capabilities returned by the ODM.
+ */
+void
+NvOdmTmonCapabilitiesGet(
+    NvOdmTmonDeviceHandle hTmon,
+    NvOdmTmonCapabilities* pCaps);
+
+/**
+ * Gets TMON configuration parameter capabilities.
+ *
+ * @param hTmon A handle to the TMON device.
+ * @param ParamId The targeted parameter. 
+ * @param pCaps A pointer to the targeted parameter capabilities
+ *  returned by the ODM.
+ * 
+ *  Special value ::ODM_TMON_PARAMETER_UNSPECIFIED is returned as maximum and
+ *  minimum value in capabilities structure if the targeted parameter is not
+ *  supported.
+ */
+void
+NvOdmTmonParameterCapsGet(
+    NvOdmTmonDeviceHandle hTmon,
+    NvOdmTmonConfigParam ParamId,
+    NvOdmTmonParameterCaps* pCaps);
+
+/**
+ * Gets current zone temperature.
+ *
+ * @param hTmon A handle to the TMON device.
+ * @param pDegreesC A pointer to the zone temperature (in degrees C)
+ *  returned by the ODM.
+ * 
+ * @return NV_TRUE if successful, or NV_FALSE otherwise.
+ */
+NvBool
+NvOdmTmonTemperatureGet(
+    NvOdmTmonDeviceHandle hTmon,
+    NvS32* pDegreesC);
+
+/**
+ * Configures specified TMON parameter for the temperature zone.
+ *
+ * @param hTmon A handle to the TMON device.
+ * @param ParamId The targeted parameter to be updated. 
+ * @param pSetting A pointer to a variable with parameter settings.
+ *  On entry, specifies new requested settings, on exit, actually configured
+ *  settings as the best approximation of the request.
+ * 
+ *  The requested setting is clipped to the maximum/minimum values for the
+ *  respective parameter. If special value ::ODM_TMON_PARAMETER_UNSPECIFIED is
+ *  specified on entry, current parameter value is preserved and retrieved on
+ *  exit. If special value \c ODM_TMON_PARAMETER_UNSPECIFIED is returned on exit,
+ *  the targeted parameter is not supported for the given zone.
+ * 
+ * @return NV_TRUE if successful, or NV_FALSE otherwise
+ */
+NvBool
+NvOdmTmonParameterConfig(
+    NvOdmTmonDeviceHandle hTmon,
+    NvOdmTmonConfigParam ParamId,
+    NvS32* pSetting);
+
+/**
+ * Suspends temperature zone monitoring.
+ * 
+ * @param hTmon A handle to the TMON device.
+ * 
+ * @return NV_TRUE if successful, or NV_FALSE otherwise.
+ */
+NvBool NvOdmTmonSuspend(NvOdmTmonDeviceHandle hTmon);
+
+/**
+ * Resumes temperature zone monitoring.
+ * 
+ * @param hTmon A handle to the TMON device.
+ * 
+ * @return NV_TRUE if successful, or NV_FALSE otherwise.
+ */
+NvBool NvOdmTmonResume(NvOdmTmonDeviceHandle hTmon);
+
+/**
+ * Registers for TMON out of limit interrupt.
+ * 
+ * @param hTmon A handle to the TMON device.
+ * @param Callback The callback function that is called when TMON
+ *  interrupt triggers.
+ * @param arg The argument passed to the callback when it is
+ *  invoked by TMON IST.
+ * 
+ * @return TMON interrupt handle, NULL if failed to register.
+ */
+NvOdmTmonIntrHandle
+NvOdmTmonIntrRegister(
+    NvOdmTmonDeviceHandle hTmon,
+    NvOdmInterruptHandler Callback,
+    void* arg);
+
+/**
+ * Unregisters TMON interrupt.
+ * 
+ * @param hTmon A handle to the TMON device.
+ * @param hIntr A TMON interrupt handle.
+ *  If NULL, this API has no effect.
+ */
+void
+NvOdmTmonIntrUnregister(
+    NvOdmTmonDeviceHandle hTmon,
+    NvOdmTmonIntrHandle hIntr);
+
+#if defined(__cplusplus)
+}
+#endif
+
+/** @} */
+
+#endif // INCLUDED_NVODM_TMON_H
diff --git a/arch/arm/mach-tegra/include/nvodm_uart.h b/arch/arm/mach-tegra/include/nvodm_uart.h
new file mode 100644
index 000000000000..a3e338e0c2f4
--- /dev/null
+++ b/arch/arm/mach-tegra/include/nvodm_uart.h
@@ -0,0 +1,105 @@
+/*
+ * Copyright (c) 2006-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/** 
+ * @file
+ * <b>NVIDIA Tegra ODM Kit:
+ *         UART Adaptation Interface</b>
+ *
+ * @b Description: Defines the ODM adaptation interface for UART devices.
+ * 
+ */
+
+#ifndef INCLUDED_NVODM_UART_H
+#define INCLUDED_NVODM_UART_H
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+#include "nvodm_services.h"
+#include "nverror.h"
+
+/**
+ * @defgroup nvodm_uart UART Adaptation Interface
+ * 
+ * This is the UART ODM adaptation interface. 
+ * 
+ * @ingroup nvodm_adaptation
+ * @{
+ */
+
+/**
+ * Defines an opaque handle that exists for each UART device in the
+ * system, each of which is defined by the customer implementation.
+ */
+typedef struct NvOdmUartRec *NvOdmUartHandle;
+
+/**
+ * Gets a handle to the UART device.
+ *
+ * @param Instance         [IN] UART instance number
+ *
+ * @return A handle to the UART device.
+ */
+NvOdmUartHandle NvOdmUartOpen(NvU32 Instance);
+
+/**
+ * Closes the UART handle. 
+ *
+ * @param hOdmUart The UART handle to be closed.
+ */
+void NvOdmUartClose(NvOdmUartHandle hOdmUart);
+
+/**
+ * Call this API whenever the UART device goes into suspend mode.
+ *
+ * @param hOdmUart The UART handle.
+  */
+NvBool NvOdmUartSuspend(NvOdmUartHandle hOdmUart);
+
+/**
+ * Call this API whenever the UART device resumes from the suspend mode.
+ *
+ * @param hOdmUart The UART handle.
+  */
+NvBool NvOdmUartResume(NvOdmUartHandle hOdmUart);
+
+
+#if defined(__cplusplus)
+}
+#endif
+
+/** @} */
+
+#endif // INCLUDED_NVODM_uart_H
diff --git a/arch/arm/mach-tegra/include/nvodm_usbulpi.h b/arch/arm/mach-tegra/include/nvodm_usbulpi.h
new file mode 100644
index 000000000000..024996dad757
--- /dev/null
+++ b/arch/arm/mach-tegra/include/nvodm_usbulpi.h
@@ -0,0 +1,95 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/** 
+ * @file
+ * <b>NVIDIA Tegra ODM Kit:
+ *         USB ULPI Interface</b>
+ *
+ * @b Description: Defines the ODM interface for USB ULPI device.
+ */
+
+#ifndef INCLUDED_NVODM_USBULPI_H
+#define INCLUDED_NVODM_USBULPI_H
+
+
+/**
+ * @defgroup nvodm_usbulpi USB ULPI Adaptation Interface
+ *
+ * This is the USB ULPI ODM adaptation interface, which
+ * handles the abstraction of opening and closing of the USB ULPI device.
+ * For NVIDIA Driver Development Kit (NvDDK) clients, USB ULPI device
+ * means a USB controller connected to a ULPI interface that has an
+ * external phy. This API allows NvDDK clients to open the USB ULPI device by
+ * setting the ODM specific clocks to ULPI controller or external phy, so that USB ULPI
+ * device can be used.
+ *
+ * @ingroup nvodm_adaptation
+ * @{
+ */
+#if defined(_cplusplus)
+extern "C"
+{
+#endif
+
+#include "nvcommon.h"
+
+
+/**
+ * Defines the USB ULPI context.
+ */
+typedef struct NvOdmUsbUlpiRec * NvOdmUsbUlpiHandle;
+
+/**
+ * Opens the USB ULPI device by setting the ODM-specific clocks 
+ * and/or settings related to USB ULPI controller and external phy.
+ * @param Instance The ULPI instance number.
+ * @return A USB ULPI device handle on success, or NULL on failure.
+*/
+NvOdmUsbUlpiHandle  NvOdmUsbUlpiOpen(NvU32 Instance);
+
+/** 
+ * Closes the USB ULPI device handle by clearing 
+ * the related ODM-specific clocks and settings.
+ * @param hUsbUlpi A handle to USB ULPI device.
+*/
+void NvOdmUsbUlpiClose(NvOdmUsbUlpiHandle hUsbUlpi);
+
+
+#if defined(_cplusplus)
+}
+#endif
+
+/** @} */
+
+#endif // INCLUDED_NVODM_USBULPI_H
+
diff --git a/arch/arm/mach-tegra/include/nvrm_analog.h b/arch/arm/mach-tegra/include/nvrm_analog.h
new file mode 100644
index 000000000000..fd53d1e62c9d
--- /dev/null
+++ b/arch/arm/mach-tegra/include/nvrm_analog.h
@@ -0,0 +1,217 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_nvrm_analog_H
+#define INCLUDED_nvrm_analog_H
+
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+#include "nvrm_module.h"
+#include "nvrm_init.h"
+
+#include "nvodm_query.h"
+
+/**
+ * List of controllable analog interfaces.  Multiple instances of any
+ * particlar interface will be handled by the NVRM_ANALOG_INTERFACE macro
+ * below.
+ */
+
+typedef enum
+{
+    NvRmAnalogInterface_Dsi,
+    NvRmAnalogInterface_ExternalMemory,
+    NvRmAnalogInterface_Hdmi,
+    NvRmAnalogInterface_Lcd,
+    NvRmAnalogInterface_Uart,
+    NvRmAnalogInterface_Usb,
+    NvRmAnalogInterface_Sdio,
+    NvRmAnalogInterface_Tv,
+    NvRmAnalogInterface_VideoInput,
+    NvRmAnalogInterface_Num,
+    NvRmAnalogInterface_Force32 = 0x7FFFFFFF
+} NvRmAnalogInterface;
+
+/**
+ * Defines the USB Line state 
+ */
+
+typedef enum
+{
+    NvRmUsbLineStateType_SE0 = 0,
+    NvRmUsbLineStateType_SJ = 1,
+    NvRmUsbLineStateType_SK = 2,
+    NvRmUsbLineStateType_SE1 = 3,
+    NvRmUsbLineStateType_Num,
+    NvRmUsbLineStateType_Force32 = 0x7FFFFFFF
+} NvRmUsbLineStateType;
+
+/**
+ * List of analog TV DAC type
+ */
+
+typedef enum
+{
+    NvRmAnalogTvDacType_CRT,
+    NvRmAnalogTvDacType_SDTV,
+    NvRmAnalogTvDacType_HDTV,
+    NvRmAnalogTvDacType_Num,
+    NvRmAnalogTvDacType_Force32 = 0x7FFFFFFF
+} NvRmAnalogTvDacType;
+
+/**
+ * Create an analog interface id with multiple instances.
+ */
+#define NVRM_ANALOG_INTERFACE( id, instance ) \
+    ((NvRmAnalogInterface)( (instance) << 16 | id ))
+
+/**
+ * Get the interface id.
+ */
+#define NVRM_ANALOG_INTERFACE_ID( id ) ((id) & 0xFFFF)
+
+/**
+ * Get the interface instance.
+ */
+#define NVRM_ANALOG_INTERFACE_INSTANCE( id ) (((id) >> 16) & 0xFFFF)
+
+/**
+ * Control I/O pads, DACs, or PHYs, either enable or disable, with an optional
+ * configuration structure, which may be defined per module.
+ *
+ * @param hDevice Handle to the RM device
+ * @param Interface The physical interface to configure
+ * @param Enable enable/disable bit
+ * @param Config extra configuration options for each module, if necessary
+ * @param ConfigLength the size in bytes of the configuration structure
+ */
+
+ NvError NvRmAnalogInterfaceControl( 
+    NvRmDeviceHandle hDevice,
+    NvRmAnalogInterface Interface,
+    NvBool Enable,
+    void* Config,
+    NvU32 ConfigLength );
+
+/**
+ * Get TV DAC Configuration
+ *
+ * @param hDevice Handle to the RM device
+ * @param Type The analog TV DAC type 
+ * @return The analog TV DAC Configuration value
+ */
+
+ NvU8 NvRmAnalogGetTvDacConfiguration( 
+    NvRmDeviceHandle hDevice,
+    NvRmAnalogTvDacType Type );
+
+/**
+ * Detect if USB is connected or not
+ *
+ * @param hDevice Handle to the RM device
+ * @return TRUE means USB is connected
+ */
+
+ NvBool NvRmUsbIsConnected( 
+    NvRmDeviceHandle hDevice );
+
+/**
+ * Detect charger type
+ *
+ * @param hDevice Handle to the RM device
+ * @param wait Delay time and ready to get the correct charger type
+ * @return USB charger type
+ */
+
+ NvU32 NvRmUsbDetectChargerState( 
+    NvRmDeviceHandle hDevice,
+    NvU32 wait );
+
+/**
+ * Extended configuration structures for NvRmAnalogInterfaceControl.
+ */
+
+typedef struct NvRmAnalogTvDacConfigRec
+{
+
+    /* The DAC input source, may be a Display controller or the TVO engine */
+        NvRmModuleID Source;
+
+    /* The DAC output amplitude */
+        NvU8 DacAmplitude;
+} NvRmAnalogTvDacConfig;
+
+/**
+ * List of USB analog status check parameters
+ */
+
+typedef enum
+{
+    NvRmAnalogUsbInputParam_CheckCableStatus,
+    NvRmAnalogUsbInputParam_CheckChargerStatus,
+    NvRmAnalogUsbInputParam_CheckIdStatus,
+    NvRmAnalogUsbInputParam_WaitForPhyClock,
+    NvRmAnalogUsbInputParam_ConfigureUsbPhy,
+    NvRmAnalogUsbInputParam_ChargerDetection,
+    NvRmAnalogUsbInputParam_SetUlpiNullTrimmers,
+    NvRmAnalogUsbInputParam_ConfigureUlpiNullClock,
+    NvRmAnalogUsbInputParam_SetNullUlpiPinMux,
+    NvRmAnalogUsbInputParam_SetUlpiLinkTrimmers,
+    NvRmAnalogUsbInputParam_VbusInterrupt,
+    NvRmAnalogUsbInputParam_IdInterrupt,
+    NvRmAnalogUsbInputParam_Num,
+    NvRmAnalogUsbInputParam_Force32 = 0x7FFFFFFF
+} NvRmAnalogUsbInputParam;
+
+/**
+ * Extended configuration structures for NvRmAnalogInterfaceControl for USB.
+ */
+
+typedef struct NvRmAnalogUsbConfigRec
+{
+
+    /* The USB Status check parameter */
+        NvRmAnalogUsbInputParam InParam;
+    NvBool UsbCableDetected;
+    NvBool UsbChargerDetected;
+    NvBool UsbIdDetected;
+} NvRmAnalogUsbConfig;
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif
diff --git a/arch/arm/mach-tegra/include/nvrm_arm_cp.h b/arch/arm/mach-tegra/include/nvrm_arm_cp.h
new file mode 100644
index 000000000000..30bdd971f4cf
--- /dev/null
+++ b/arch/arm/mach-tegra/include/nvrm_arm_cp.h
@@ -0,0 +1,189 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+
+#ifndef INCLUDED_ARM_CP_H
+#define INCLUDED_ARM_CP_H
+
+#include "nvassert.h"
+
+#ifdef  __cplusplus
+extern "C" {
+#endif
+
+//==========================================================================
+// Compiler-specific status and coprocessor register abstraction macros.
+//==========================================================================
+
+#if defined(_MSC_VER) && NVOS_IS_WINDOWS_CE // Microsoft compiler on WinCE
+
+    // Define the standard ARM coprocessor register names because the ARM compiler requires
+    // that we use the names and the Microsoft compiler requires that we use the numbers for
+    // its intrinsic functions _MoveToCoprocessor() and _MoveFromCoprocessor().
+    #define p14     14
+    #define p15     15
+    #define c0      0
+    #define c1      1
+    #define c2      2
+    #define c3      3
+    #define c4      4
+    #define c5      5
+    #define c6      6
+    #define c7      7
+    #define c8      8
+    #define c9      9
+    #define c10     10
+    #define c11     11
+    #define c12     12
+    #define c13     13
+    #define c14     14
+    #define c15     15
+
+    /*
+     *  @brief Macro to abstract writing of a ARM coprocessor register via the MCR instruction.
+     *  @param cp is the coprocessor name (e.g., p15)
+     *  @param op1 is a coprocessor-specific operation code (must be a manifest constant).
+     *  @param Rd is a variable that will receive the value read from the coprocessor register.
+     *  @param CRn is the destination coprocessor register (e.g., c7).
+     *  @param CRm is an additional destination coprocessor register (e.g., c2).
+     *  @param op2 is a coprocessor-specific operation code (must be a manifest constant).
+    */
+    #define MCR(cp,op1,Rd,CRn,CRm,op2)  _MoveToCoprocessor((NvU32)(Rd), cp, op1, CRn, CRm, op2)
+
+    /*
+     *  @brief Macro to abstract reading of a ARM coprocessor register via the MRC instruction.
+     *  @param cp is the coprocessor name (e.g., p15)
+     *  @param op1 is a coprocessor-specific operation code (must be a manifest constant).
+     *  @param Rd is a variable that will receive the value read from the coprocessor register.
+     *  @param CRn is the destination coprocessor register (e.g., c7).
+     *  @param CRm is an additional destination coprocessor register (e.g., c2).
+     *  @param op2 is a coprocessor-specific operation code (must be a manifest constant).
+    */
+    #define MRC(cp,op1,Rd,CRn,CRm,op2)  *((NvU32*)(&(Rd))) = _MoveFromCoprocessor(cp, op1, CRn, CRm, op2)
+
+#elif defined(__ARMCC_VERSION)  // ARM compiler
+
+    /*
+     *  @brief Macro to abstract writing of a ARM coprocessor register via the MCR instruction.
+     *  @param cp is the coprocessor name (e.g., p15)
+     *  @param op1 is a coprocessor-specific operation code (must be a manifest constant).
+     *  @param Rd is a variable that will be written to the coprocessor register.
+     *  @param CRn is the destination coprocessor register (e.g., c7)
+     *  @param CRm is an additional destination coprocessor register (e.g., c2).
+     *  @param op2 is a coprocessor-specific operation code (must be a manifest constant).
+    */
+    #define MCR(cp,op1,Rd,CRn,CRm,op2)  __asm { MCR cp, op1, Rd, CRn, CRm, op2 }
+
+    /*
+     *  @brief Macro to abstract reading of a ARM coprocessor register via the MRC instruction.
+     *  @param cp is the coprocessor name (e.g., p15)
+     *  @param op1 is a coprocessor-specific operation code (must be a manifest constant).
+     *  @param Rd is a variable that will receive the value read from the coprocessor register.
+     *  @param CRn is the destination coprocessor register (e.g., c7).
+     *  @param CRm is an additional destination coprocessor register (e.g., c2).
+     *  @param op2 is a coprocessor-specific operation code (must be a manifest constant).
+    */
+    #define MRC(cp,op1,Rd,CRn,CRm,op2)  __asm { MRC cp, op1, Rd, CRn, CRm, op2 }
+
+#elif NVOS_IS_LINUX || __GNUC__ // linux compilers
+
+    #if defined(__arm__)    // ARM GNU compiler
+
+    // Define the standard ARM coprocessor register names because the ARM compiler requires
+    // that we use the names and the GNU compiler requires that we use the numbers.
+    #define p14     14
+    #define p15     15
+    #define c0      0
+    #define c1      1
+    #define c2      2
+    #define c3      3
+    #define c4      4
+    #define c5      5
+    #define c6      6
+    #define c7      7
+    #define c8      8
+    #define c9      9
+    #define c10     10
+    #define c11     11
+    #define c12     12
+    #define c13     13
+    #define c14     14
+    #define c15     15
+
+    /*
+     *  @brief Macro to abstract writing of a ARM coprocessor register via the MCR instruction.
+     *  @param cp is the coprocessor name (e.g., p15)
+     *  @param op1 is a coprocessor-specific operation code (must be a manifest constant).
+     *  @param Rd is a variable that will receive the value read from the coprocessor register.
+     *  @param CRn is the destination coprocessor register (e.g., c7).
+     *  @param CRm is an additional destination coprocessor register (e.g., c2).
+     *  @param op2 is a coprocessor-specific operation code (must be a manifest constant).
+    */
+    #define MCR(cp,op1,Rd,CRn,CRm,op2)  asm(" MCR " #cp",%1,%2,"#CRn","#CRm ",%5" \
+        : : "i" (cp), "i" (op1), "r" (Rd), "i" (CRn), "i" (CRm), "i" (op2))
+
+    /*
+     *  @brief Macro to abstract reading of a ARM coprocessor register via the MRC instruction.
+     *  @param cp is the coprocessor name (e.g., p15)
+     *  @param op1 is a coprocessor-specific operation code (must be a manifest constant).
+     *  @param Rd is a variable that will receive the value read from the coprocessor register.
+     *  @param CRn is the destination coprocessor register (e.g., c7).
+     *  @param CRm is an additional destination coprocessor register (e.g., c2).
+     *  @param op2 is a coprocessor-specific operation code (must be a manifest constant).
+    */
+    #define MRC(cp,op1,Rd,CRn,CRm,op2)  asm( " MRC " #cp",%2,%0," #CRn","#CRm",%5" \
+        : "=r" (Rd) : "i" (cp), "i" (op1), "i" (CRn), "i" (CRm), "i" (op2))
+
+    #else
+    
+    /* x86 processor. No such instructions. Callers should not call these macros
+     * when running on x86. If they do, it will compile but will not work. */
+    #define MCR(cp,op1,Rd,CRn,CRm,op2)  do { Rd = Rd; NV_ASSERT(0); } while (0)
+    #define MRC(cp,op1,Rd,CRn,CRm,op2)  do { Rd = 0; /*NV_ASSERT(0);*/ } while (0)
+
+    #endif
+#else
+
+    // !!!FIXME!!! TEST FOR ALL KNOWN COMPILERS -- FOR NOW JUST DIE AT RUN-TIME
+    // #error "Unknown compiler"
+    #define MCR(cp,op1,Rd,CRn,CRm,op2)  do { Rd = Rd; NV_ASSERT(0); } while (0)
+    #define MRC(cp,op1,Rd,CRn,CRm,op2)  do { Rd = 0; /*NV_ASSERT(0);*/ } while (0)
+
+#endif
+
+
+#ifdef  __cplusplus
+}
+#endif
+
+#endif // INCLUDED_ARM_CP_H
+
diff --git a/arch/arm/mach-tegra/include/nvrm_avp_shrd_interrupt.h b/arch/arm/mach-tegra/include/nvrm_avp_shrd_interrupt.h
new file mode 100644
index 000000000000..579aab3c240d
--- /dev/null
+++ b/arch/arm/mach-tegra/include/nvrm_avp_shrd_interrupt.h
@@ -0,0 +1,117 @@
+/*
+ * Copyright (c) 2010 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_nvrm_avp_shrd_interrupt_H
+#define INCLUDED_nvrm_avp_shrd_interrupt_H
+
+#include "nvos.h"
+#include "nvrm_init.h"
+#include "nvrm_module.h"
+#include "nvrm_interrupt.h"
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+/* Max number of clients with shared interrupt handler */
+enum {MAX_SHRDINT_CLIENTS = 32};
+
+/* Now AP15 support only VDE interrupts 6 */
+enum {MAX_SHRDINT_INTERRUPTS = 6};
+    /* VDE Sync Token Interrupt */
+enum {AP15_SYNC_TOKEN_INTERRUPT_INDEX = 0};
+    /* VDE BSE-V Interrupt */
+enum {AP15_BSE_V_INTERRUPT_INDEX = 1};
+    /* VDE BSE-A Interrupt */
+enum {AP15_BSE_A_INTERRUPT_INDEX = 2};
+    /* VDE SXE Interrupt */
+enum {AP15_SXE_INTERRUPT_INDEX = 3};
+    /* VDE UCQ Error Interrupt */
+enum {AP15_UCQ_INTERRUPT_INDEX = 4};
+    /* VDE Interrupt */
+enum {AP15_VDE_INTERRUPT_INDEX = 5};
+
+/* Now AP20 support only VDE interrupts 5 */
+enum {AP20_MAX_SHRDINT_INTERRUPTS = 5};
+    /* VDE Sync Token Interrupt */
+enum {AP20_SYNC_TOKEN_INTERRUPT_INDEX = 0};
+    /* VDE BSE-V Interrupt */
+enum {AP20_BSE_V_INTERRUPT_INDEX = 1};
+    /* VDE SXE Interrupt */
+enum {AP20_SXE_INTERRUPT_INDEX = 2};
+    /* VDE UCQ Error Interrupt */
+enum {AP20_UCQ_INTERRUPT_INDEX = 3};
+    /* VDE Interrupt */
+enum {AP20_VDE_INTERRUPT_INDEX = 4};
+
+enum
+{
+    NvRmArbSema_Vde = 0,
+    NvRmArbSema_Bsea,
+    //This should be last
+    NvRmArbSema_Num,
+};
+
+/* Shared interrupt private init , init done during RM init on AVP */
+NvError NvRmAvpShrdInterruptPrvInit(NvRmDeviceHandle hRmDevice);
+
+/* Shared interrupt private de-init , de-init done during RM close on AVP */
+void NvRmAvpShrdInterruptPrvDeinit(NvRmDeviceHandle hRmDevice);
+
+/* Get logical interrupt for a module*/
+NvU32 NvRmAvpShrdInterruptGetIrqForLogicalInterrupt(NvRmDeviceHandle hRmDevice,
+                                                    NvRmModuleID ModuleID,
+                                                    NvU32 Index);
+/* Register for shared interrpt */
+NvError NvRmAvpShrdInterruptRegister(NvRmDeviceHandle hRmDevice,
+                                     NvU32 IrqListSize,
+                                     const NvU32 *pIrqList,
+                                     const NvOsInterruptHandler *pIrqHandlerList,
+                                     void *pContext,
+                                     NvOsInterruptHandle *handle,
+                                     NvU32 *ClientIndex);
+/* Un-register a shared interrpt */
+void NvRmAvpShrdInterruptUnregister(NvRmDeviceHandle hRmDevice,
+                                    NvOsInterruptHandle handle,
+                                    NvU32 ClientIndex);
+/* Get exclisive access to a hardware(VDE) block */
+NvError NvRmAvpShrdInterruptAquireHwBlock(NvRmModuleID ModuleID, NvU32 ClientId);
+
+/* Release exclisive access to a hardware(VDE) block */
+NvError NvRmAvpShrdInterruptReleaseHwBlock(NvRmModuleID ModuleID, NvU32 ClientId);
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif //INCLUDED_nvrm_avp_shrd_interrupt_H
diff --git a/arch/arm/mach-tegra/include/nvrm_boot.h b/arch/arm/mach-tegra/include/nvrm_boot.h
new file mode 100644
index 000000000000..75258d068ec9
--- /dev/null
+++ b/arch/arm/mach-tegra/include/nvrm_boot.h
@@ -0,0 +1,58 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_NVRM_BOOT_H
+#define INCLUDED_NVRM_BOOT_H
+
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+#include "nvrm_init.h"
+
+/**
+ * Sets the RM chip shmoo data as a boot argument from the system's
+ * boot loader.
+ * 
+ * @param hRmDevice The RM device handle.
+ * 
+ * @retval NvSuccess If successful, or the appropriate error code.
+ */
+NvError NvRmBootArgChipShmooSet(NvRmDeviceHandle hRmDevice);
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif // INCLUDED_NVRM_BOOT_H
diff --git a/arch/arm/mach-tegra/include/nvrm_diag.h b/arch/arm/mach-tegra/include/nvrm_diag.h
new file mode 100644
index 000000000000..4ec86ed55f7e
--- /dev/null
+++ b/arch/arm/mach-tegra/include/nvrm_diag.h
@@ -0,0 +1,552 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_nvrm_diag_H
+#define INCLUDED_nvrm_diag_H
+
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+#include "nvrm_init.h"
+
+#include "nvcommon.h"
+
+/**
+ * All of the hardware modules.  Multiple instances are handled by the
+ * NVRM_DIAG_MODULE macro.
+ */
+
+typedef enum
+{
+    NvRmDiagModuleID_Cache = 1,
+    NvRmDiagModuleID_Vcp,
+    NvRmDiagModuleID_Host1x,
+    NvRmDiagModuleID_Display,
+    NvRmDiagModuleID_Ide,
+    NvRmDiagModuleID_3d,
+    NvRmDiagModuleID_Isp,
+    NvRmDiagModuleID_Usb,
+    NvRmDiagModuleID_2d,
+    NvRmDiagModuleID_Vi,
+    NvRmDiagModuleID_Epp,
+    NvRmDiagModuleID_I2s,
+    NvRmDiagModuleID_Pwm,
+    NvRmDiagModuleID_Twc,
+    NvRmDiagModuleID_Hsmmc,
+    NvRmDiagModuleID_Sdio,
+    NvRmDiagModuleID_NandFlash,
+    NvRmDiagModuleID_I2c,
+    NvRmDiagModuleID_Spdif,
+    NvRmDiagModuleID_Gpio,
+    NvRmDiagModuleID_Uart,
+    NvRmDiagModuleID_Timer,
+    NvRmDiagModuleID_Rtc,
+    NvRmDiagModuleID_Ac97,
+    NvRmDiagModuleID_Coprocessor,
+    NvRmDiagModuleID_Cpu,
+    NvRmDiagModuleID_Bsev,
+    NvRmDiagModuleID_Bsea,
+    NvRmDiagModuleID_Vde,
+    NvRmDiagModuleID_Mpe,
+    NvRmDiagModuleID_Emc,
+    NvRmDiagModuleID_Sprom,
+    NvRmDiagModuleID_Tvdac,
+    NvRmDiagModuleID_Csi,
+    NvRmDiagModuleID_Hdmi,
+    NvRmDiagModuleID_MipiBaseband,
+    NvRmDiagModuleID_Tvo,
+    NvRmDiagModuleID_Dsi,
+    NvRmDiagModuleID_Dvc,
+    NvRmDiagModuleID_Sbc,
+    NvRmDiagModuleID_Xio,
+    NvRmDiagModuleID_Spi,
+    NvRmDiagModuleID_NorFlash,
+    NvRmDiagModuleID_Slc,
+    NvRmDiagModuleID_Fuse,
+    NvRmDiagModuleID_Pmc,
+    NvRmDiagModuleID_StatMon,
+    NvRmDiagModuleID_Kbc,
+    NvRmDiagModuleID_Vg,
+    NvRmDiagModuleID_ApbDma,
+    NvRmDiagModuleID_Mc,
+    NvRmDiagModuleID_SpdifIn,
+    NvRmDiagModuleID_Vfir,
+    NvRmDiagModuleID_Cve,
+    NvRmDiagModuleID_ViSensor,
+    NvRmDiagModuleID_SystemReset,
+    NvRmDiagModuleID_AvpUcq,
+    NvRmDiagModuleID_KFuse,
+    NvRmDiagModuleID_OneWire,
+    NvRmDiagModuleID_SyncNor,
+    NvRmDiagModuleID_Pcie,
+    NvRmDiagModuleID_Num,
+    NvRmDiagModuleID_Force32 = 0x7FFFFFFF
+} NvRmDiagModuleID;
+
+/**
+ * Create a diag module id with multiple instances.
+ */
+#define NVRM_DIAG_MODULE( id, instance ) \
+    ((NvRmDiagModuleID)( (instance) << 16 | id ))
+
+/**
+ * Get the module id.
+ */
+#define NVRM_DIAG_MODULE_ID( id ) ((id) & 0xFFFF)
+
+/**
+ * Get the module instance.
+ */
+#define NVRM_DIAG_MODULE_INSTANCE( id ) (((id) >> 16) & 0xFFFF)
+
+/**
+ * Enable/disable support for individual clock diagnostic lock
+ */
+#define NVRM_DIAG_LOCK_SUPPORTED (0)
+
+/**
+ * Append clock configuration flags with diagnostic lock flag
+ */
+#define NvRmClockConfig_DiagLock ((NvRmClockConfigFlags_Num & (~0x01)) << 1)
+
+/**
+ * Defines clock source types
+ */
+
+typedef enum
+{
+
+    /// Clock source with fixed frequency
+        NvRmDiagClockSourceType_Oscillator = 1,
+
+    /// PLL clock source
+        NvRmDiagClockSourceType_Pll,
+
+    /// Clock scaler derives its clock from oscillators, PLLs or other scalers
+        NvRmDiagClockSourceType_Scaler,
+    NvRmDiagClockSourceType_Num,
+    NvRmDiagClockSourceType_Force32 = 0x7FFFFFFF
+} NvRmDiagClockSourceType;
+
+/**
+ * Defines types of clock scalers. Scale coefficient for all clock scalers
+ * is specified as (m, n) pair of 32-bit values. The interpretation of the
+ * m, n values for each type is clarified below.
+ */
+
+typedef enum
+{
+
+    /// No clock scaler: m = n = 1 always
+        NvRmDiagClockScalerType_NoScaler = 1,
+
+    /// Clock divider with m = 1 always, and n = 31.1 format
+    /// with half-step lowest bit
+        NvRmDiagClockScalerType_Divider_1_N,
+
+    /// Clock divider with rational (m+1)/(n+1) coefficient; m and n are
+    /// integeres, scale 1:1 is applied if m >= n
+        NvRmDiagClockScalerType_Divider_M_N,
+
+    /// Clock divider with rational (m+1)/16 coefficient, i.e., n = 16 always;
+    /// m is integer, scale 1:1 is applied if m >= 15 ("keeps" m + 1 clocks
+    /// out of every 16)
+        NvRmDiagClockScalerType_Divider_M_16,
+
+    /// Clock doubler: scale 2:1 if m != 0, scale 1:1 if m = 0,
+    /// n = 1 always 
+        NvRmDiagClockScalerType_Doubler,
+    NvRmDiagClockScalerType_Num,
+    NvRmDiagClockScalerType_Force32 = 0x7FFFFFFF
+} NvRmDiagClockScalerType;
+
+/**
+ * Defines RM thermal monitoring zones.
+ */
+
+typedef enum
+{
+
+    /// Specifies ambient temperature zone.
+        NvRmTmonZoneId_Ambient = 1,
+
+    /// Specifies SoC core temperature zone.
+        NvRmTmonZoneId_Core,
+    NvRmTmonZoneId_Num,
+    NvRmTmonZoneId_Force32 = 0x7FFFFFFF
+} NvRmTmonZoneId;
+
+/// Clock source opaque handle (TODO: replace forward idl declaration
+/// of <enum> with forward declaration of <handle>, when it is supported 
+typedef struct NvRmClockSourceInfoRec* NvRmDiagClockSourceHandle;
+
+/// Power rail opaque handle
+
+typedef struct NvRmDiagPowerRailRec *NvRmDiagPowerRailHandle;
+
+/**
+ * Enables diagnostic mode (disable is not allowed).  Clock, voltage, etc.,
+ * will no longer be controlled by the Resource Manager. The NvRmDiag
+ * interfaces should be used instead.
+ * 
+ * @param hDevice The RM device handle.
+ * 
+ * @retval NvSuccess if diagnostic mode is successfully enabled.
+ * @retval NvError_InsufficientMemory if failed to allocate memory for
+ *  diagnostic mode.
+ */
+
+ NvError NvRmDiagEnable( 
+    NvRmDeviceHandle hDevice );
+
+/**
+ * Lists modules present in the chip and available for diagnostic.
+ * 
+ * @param pListSize Pointer to the list size. On entry specifies list size
+ *  allocated by the client, on exit - actual number of Ids returned. If
+ *  entry size is 0, maximum list size is returned. 
+ * @param pIdList Pointer to the list of combined module Id/Instance values
+ *  to be filled in by this function. Ignored if input list size is 0.
+ * 
+ * @retval NvSuccess if the module list is successfully returned.
+ * @retval NvError_NotInitialized if diagnostic mode is not enabled.
+ */                               
+
+ NvError NvRmDiagListModules( 
+    NvU32 * pListSize,
+    NvRmDiagModuleID * pIdList );
+
+/**
+ * Lists available SoC clock sources.
+ * 
+ * @param pListSize Pointer to the list size. On entry specifies list size
+ *  allocated by the client, on exit - actual number of source handles
+ *  returned. If entry size is 0, maximum list size is returned.
+ * @param phSourceList Pointer to the list of source handles to be filled
+ *  in by this function. Ignored if input list size is 0.
+ * 
+ * @retval NvSuccess if the source list is successfully returned.
+ * @retval NvError_NotInitialized if diagnostic mode is not enabled.
+ */                               
+
+ NvError NvRmDiagListClockSources( 
+    NvU32 * pListSize,
+    NvRmDiagClockSourceHandle * phSourceList );
+
+/**
+ * Lists clock sources for the specified module.
+ * 
+ * @param id Combined Id and instance for the target module.
+ * @param pListSize Pointer to the list size. On entry specifies list size
+ *  allocated by the client, on exit - actual number of source handles
+ *  returned. If entry size is 0, maximum list size is returned.
+ * @param phSourceList Pointer to the list of source handles to be filled
+ *  in by this function. Ignored if input list size is 0.
+ * 
+ * @retval NvSuccess if the source list is successfully returned.
+ * @retval NvError_NotInitialized if diagnostic mode is not enabled.
+ */
+
+ NvError NvRmDiagModuleListClockSources( 
+    NvRmDiagModuleID id,
+    NvU32 * pListSize,
+    NvRmDiagClockSourceHandle * phSourceList );
+
+/**
+ * Enables/Disables specified module clock.
+ * 
+ * @param id Combined Id and instance for the target module.
+ * @param enable Requested clock state - enabled if true, disabled if false
+ * 
+ * @retval NvSuccess if clock state changed successfully.
+ * @retval NvError_NotInitialized if diagnostic mode is not enabled.
+ */
+
+ NvError NvRmDiagModuleClockEnable( 
+    NvRmDiagModuleID id,
+    NvBool enable );
+
+/**
+ * Configures the clock for the specified module.
+ *
+ * @param id Combined Id and instance for the target module.
+ * @param hSource The handle of the clock source to drive the given module.
+ * @param divider 31.1 format: lowest bit is half-step. No range checking.
+ *  Half-step bit is ignored if module divider is not fractional. High 
+ *  bits are silently truncated if the value is out of h/w field range.
+ * @param Source1st If true, clock source is updated 1st, and the divider
+ *  is modified after the chip specific delay. If false, the order of update
+ *  is the reversed.
+ * 
+ * @retval NvSuccess if clock state changed successfully.
+ * @retval NvError_NotInitialized if diagnostic mode is not enabled.
+ */
+
+ NvError NvRmDiagModuleClockConfigure( 
+    NvRmDiagModuleID id,
+    NvRmDiagClockSourceHandle hSource,
+    NvU32 divider,
+    NvBool Source1st );
+
+/**
+ * Gets the name of the given clock source..
+ *
+ * @param hSource The target clock source handle.
+ * 
+ * @return The 64-bit packed 8-character name of the given clock source. Zero
+ *  will be returned if diagnostic mode is not enabled or the source is invalid.
+ */
+
+ NvU64 NvRmDiagClockSourceGetName( 
+    NvRmDiagClockSourceHandle hSource );
+
+/**
+ * Gets the type of the given clock source.
+ *
+ * @param hSource The target clock source handle.
+ * 
+ * @return The type of the given clock source. Zero will be returned if
+ *  diagnostic mode is not enabled or the source is invalid.
+ */
+
+ NvRmDiagClockSourceType NvRmDiagClockSourceGetType( 
+    NvRmDiagClockSourceHandle hSource );
+
+/**
+ * Gets the type of the scaler for the given clock source.
+ *
+ * @param hSource The target clock source handle.
+ * 
+ * @return The type of the scaler for the given clock source. Zero will be
+ *  be returned if diagnostic mode is not enabled or the source is invalid.
+ */
+
+ NvRmDiagClockScalerType NvRmDiagClockSourceGetScaler( 
+    NvRmDiagClockSourceHandle hSource );
+
+/**
+ * Lists input clock sources for the specified clock source.
+ * Primary oscillators have no input sources, and always return 0 as
+ * list size. Other sources (secondary sources with fixed frequency,
+ * PLLs and scalers) have 1 + input sources.
+ * 
+ * @param hSource The target clock source handle.
+ * @param pListSize Pointer to the list size. On entry specifies list size
+ *  allocated by the client, on exit - actual number of source handles
+ *  returned. If entry size is 0, maximum list size is returned.
+ * @param phSourceList Pointer to the list of source handles to be filled
+ *  in by this function. Ignored if input list size is 0.
+ * 
+ * @retval NvSuccess if the source list is successfully returned.
+ * @retval NvError_NotInitialized if diagnostic mode is not enabled.
+ */
+
+ NvError NvRmDiagClockSourceListSources( 
+    NvRmDiagClockSourceHandle hSource,
+    NvU32 * pListSize,
+    NvRmDiagClockSourceHandle * phSourceList );
+
+/**
+ * Gets the given oscillator frequency in kHz.
+ *
+ * @param hOscillator The targeted oscillator/fixed frequency source handle.
+ * 
+ * @return The oscillator frequency in kHz. Zero will be returned if
+ *  diagnostic mode is not enabled or the target source is invalid.
+ */
+
+ NvU32 NvRmDiagOscillatorGetFreq( 
+    NvRmDiagClockSourceHandle hOscillator );
+
+/**
+ * Configures given PLL. Switches PLL in bypass mode, changes PLL settings,
+ * waits for PLL stabilization, and switches back to PLL output.
+ * 
+ * @param hPll The targeted PLL  handle.
+ * @param M Input divider settings (32-bit integer value)
+ * @param N Feedback divider settings (32-bit integer value)
+ * @param P Post divider settings (32-bit integer value)
+ *  If either M or N is zero PLL is left disabled and bypassed. Bsides that,
+ *  no other M, N, P parameters validation. High bits are silently truncated
+ *  if value is out of h/w field range.
+ * 
+ * @retval NvSuccess if clock state changed successfully.
+ * @retval NvError_NotInitialized if diagnostic mode is not enabled.
+ */
+
+ NvError NvRmDiagPllConfigure( 
+    NvRmDiagClockSourceHandle hPll,
+    NvU32 M,
+    NvU32 N,
+    NvU32 P );
+
+/**
+ * Configures specified clock scaler.
+ *
+ * @param hScaler The targeted Clock Scaler handle.
+ * @param hInput The handle of the input clock source to drive the
+ *  targeted scaler.
+ * @param M The dividend in the scaler coefficient (M/N) - 31.1 format:
+ *  lowest bit is half-step.
+ * @param N The divisor in the scaler coefficient (M/N) - 31.1 format:
+ *  lowest bit is half-step.
+ *  No range checking for M, N parameters. Half-step bit is ignored if
+ *  the scaler is not fractional. High bits are silently truncated if
+ *  the value is out of h/w field range.
+ *
+ * @retval NvSuccess if clock state changed successfully.
+ * @retval NvError_NotInitialized if diagnostic mode is not enabled.
+ */
+
+ NvError NvRmDiagClockScalerConfigure( 
+    NvRmDiagClockSourceHandle hScaler,
+    NvRmDiagClockSourceHandle hInput,
+    NvU32 M,
+    NvU32 N );
+
+/**
+ * Resets module.
+ * 
+ * @param id Combined Id and instance for the target module.
+ * @param KeepAsserted If true, reset will be kept asserted on exit.
+ *  If false, reset is kept asserted for chip specific delay, and
+ *  de-asserted on exit.
+ * 
+ * @retval NvSuccess if module reset completed successfully.
+ * @retval NvError_NotInitialized if diagnostic mode is not enabled.
+ */
+
+ NvError NvRmDiagModuleReset( 
+    NvRmDiagModuleID id,
+    NvBool KeepAsserted );
+
+/**
+ * Lists power rails.
+ * 
+ * @param pListSize Pointer to the list size. On entry specifies list size
+ *  allocated by the client, on exit - actual number of rail handles
+ *  returned. If entry size is 0, maximum list size is returned.
+ * @param phSourceList Pointer to the list of power rail handles to be filled
+ *  in by this function. Ignored if input list size is 0.
+ * 
+ * @retval NvSuccess if the source list is successfully returned.
+ * @retval NvError_NotInitialized if diagnostic mode is not enabled.
+ */                               
+
+ NvError NvRmDiagListPowerRails( 
+    NvU32 * pListSize,
+    NvRmDiagPowerRailHandle * phRailList );
+
+/**
+ * Gets the name of the given power rail.
+ *
+ * @param hRail The target power rail handle.
+ * 
+ * @return The 64-bit packed 8-character name of the given rail. Zero will be
+ *  returned if diagnostic mode is not enabled or the rail is invalid.
+ */
+
+ NvU64 NvRmDiagPowerRailGetName( 
+    NvRmDiagPowerRailHandle hRail );
+
+/**
+ * Lists power rails for the specified module.
+ * 
+ * @param id Combined Id and instance for the target module.
+ * @param pListSize Pointer to the list size. On entry specifies list size
+ *  allocated by the client, on exit - actual number of power rail handles
+ *  returned. If entry size is 0, maximum list size is returned.
+ * @param phRailList Pointer to the list of source handles to be filled
+ *  in by this function. Ignored if input list size is 0.
+ * 
+ * @retval NvSuccess if the power rail list is successfully returned.
+ * @retval NvError_NotInitialized if diagnostic mode is not enabled.
+ */
+
+ NvError NvRmDiagModuleListPowerRails( 
+    NvRmDiagModuleID id,
+    NvU32 * pListSize,
+    NvRmDiagPowerRailHandle * phRailList );
+
+/**
+ * Configures power rail voltage.
+ * 
+ * @param hRail The target power rail handle.
+ * @param VoltageMV The requested voltage level in millivolts.
+ * 
+ * @retval NvSuccess if the power rail is successfully configured.
+ * @retval NvError_NotInitialized if diagnostic mode is not enabled.
+ */
+
+ NvError NvRmDiagConfigurePowerRail( 
+    NvRmDiagPowerRailHandle hRail,
+    NvU32 VoltageMV );
+
+/**
+ * Verifies support for individual clock diagnostic lock (if supported
+ * clock frequency can be locked when diagnostic mode is disabled).
+ * 
+ * @retval NV_TRUE if individual clock diagnostic lock is supported.
+ * @retval NV_FALSE if individual clock diagnostic lock is not supported.
+ */
+
+ NvBool NvRmDiagIsLockSupported( 
+    void  );
+
+/**
+ * Gets temperature in the specified thermal zone (used for
+ * thermal profiling, does not require diagnostic mode to be enabled)
+ * 
+ * @param hRmDeviceHandle The RM device handle.
+ * @param ZoneId The targeted thermal zone ID.
+ * @param pTemperatureC Output storage pointer for zone temperature
+ *  (in degrees C).
+ * 
+ * @retval NvSuccess if temperature is returned successfully.
+ * @retval NvError_Busy if attempt to access temperature monitoring
+ *  device failed.
+ * @retval NvError_NotSupported if the specified zone is not monitored.
+ */
+
+ NvError NvRmDiagGetTemperature( 
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvRmTmonZoneId ZoneId,
+    NvS32 * pTemperatureC );
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif
diff --git a/arch/arm/mach-tegra/include/nvrm_dma.h b/arch/arm/mach-tegra/include/nvrm_dma.h
new file mode 100644
index 000000000000..2ff199ae03f5
--- /dev/null
+++ b/arch/arm/mach-tegra/include/nvrm_dma.h
@@ -0,0 +1,384 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_nvrm_dma_H
+#define INCLUDED_nvrm_dma_H
+
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+#include "nvrm_module.h"
+#include "nvrm_init.h"
+
+/** 
+ * @file
+ * @brief <b>nVIDIA Driver Development Kit: 
+ *           DMA Resource manager </b>
+ *
+ * @b Description: Defines the interface to the NvRM DMA.
+ * 
+ */
+
+/**
+ * @defgroup nvrm_dma Direct Memory Access (DMA) Controller API
+ * 
+ * This is the Dma interface.  These API provides the data transfer from memory
+ * to the selected destination and vice versa. The one end is the memory and 
+ * other end is the module selected by the dma module Id.
+ * This API allocates the channel based on priority request. Higher priority 
+ * channel can not be shared by other dma requestors. The low priority channel 
+ * is shared between the different requestors.
+ *
+ * @ingroup nvddk_rm
+ * 
+ * @{
+ */
+
+#include "nvos.h"
+
+/** 
+ * NvRmDmaHandle is an opaque context to the NvRmDmaRec interface
+ */
+
+typedef struct NvRmDmaRec *NvRmDmaHandle;
+
+/**
+ * @brief Defines the DMA capability structure for getting the capability of 
+ * the data transfer and any limitation if the dma manager have.
+ */
+
+typedef struct NvRmDmaCapabilitiesRec
+{
+
+    /// Holds the granularity of the data length for dma transfer in bytes
+        NvU32 DmaGranularitySize;
+
+    /// Holds the information if there is any address alignment limitation
+    /// is available in term of bytes.  if this value is 1 then there is no
+    /// limitation, any dma can transfer the data from any address. If this
+    /// value is 2 then the address should be 2 byte aligned always to do
+    /// the dma  transfer. If this value is 4 
+    /// then the address should be 4 byte aligned always to do the dma
+    /// transfer.
+        NvU32 DmaAddressAlignmentSize;
+} NvRmDmaCapabilities;
+
+/**
+ * @brief Defines the DMA client buffer information which is transferred 
+ * recently. The direction of data transfer decides based on this address. The 
+ * source address and destination address should be in line with the source 
+ * module Id and destination module Id.
+ */
+
+typedef struct NvRmDmaClientBufferRec
+{
+
+    /// Specifies the dma source buffer physical address for dma transfer. 
+        NvRmPhysAddr SourceBufferPhyAddress;
+
+    /// Specifies the dma destination buffer physical address for dma transfer.
+        NvRmPhysAddr DestinationBufferPhyAddress;
+
+    /// Source address wrap size in bytes. It tells that after how much bytes, 
+    /// it will be wrapped.
+    /// If it is zero then wrapping for source address is disabled.
+        NvU32 SourceAddressWrapSize;
+
+    /// Destination address wrap size in bytes. It tells that after how much 
+    /// bytes, it will be wrapped. If it is zero then wrapping for destination 
+    /// address is disabled.
+        NvU32 DestinationAddressWrapSize;
+
+    /// Specifies the size of the buffer in bytes which is requested for
+    /// transfer.
+        NvU32 TransferSize;
+} NvRmDmaClientBuffer;
+
+/**
+ * @brief Specify the name of modules which can be supported by nvrm dma
+ * drivers.  These dma modules can be either source or destination based on
+ * direction.
+ */
+
+typedef enum
+{
+
+    /// Specifies the dma module Id as Invalid
+        NvRmDmaModuleID_Invalid = 0x0,
+
+    /// Specifies the dma module Id for memory
+        NvRmDmaModuleID_Memory,
+
+    /// Specifies the dma module Id for I2s controller.
+        NvRmDmaModuleID_I2s,
+
+    /// Specifies the dma module Id for Ac97 controller.
+        NvRmDmaModuleID_Ac97,
+
+    /// Specifies the dma module Id for Spdif controller.
+        NvRmDmaModuleID_Spdif,
+
+    /// Specifies the dma module Id for uart controller.
+        NvRmDmaModuleID_Uart,
+
+    /// Specifies the dma module Id for Vfir controller.
+        NvRmDmaModuleID_Vfir,
+
+    /// Specifies the dma module Id for Mipi controller.
+        NvRmDmaModuleID_Mipi,
+
+    /// Specifies the dma module Id for spi controller.
+        NvRmDmaModuleID_Spi,
+
+    /// Specifies the dma module Id for slink controller.
+        NvRmDmaModuleID_Slink,
+
+    /// Specifies the dma module Id for I2c controller.
+        NvRmDmaModuleID_I2c,
+
+    /// Specifies the dma module Id for Dvc I2c controller.
+        NvRmDmaModuleID_Dvc,
+
+    /// Specifies the maximum number of modules supported.
+        NvRmDmaModuleID_Max,
+    NvRmDmaModuleID_Num,
+    NvRmDmaModuleID_Force32 = 0x7FFFFFFF
+} NvRmDmaModuleID;
+
+/**
+ * @brief Specify the direction of the transfer, either outbound data
+ * (source -> dest) or inboud data (source <- dest)
+ */
+
+typedef enum
+{
+
+    /// Specifies the direction of the transfer to be srcdevice -> dstdevice
+        NvRmDmaDirection_Forward = 0x1,
+
+    /// Specifies the direction of the transfer to be dstdevice -> srcdevice
+        NvRmDmaDirection_Reverse,
+    NvRmDmaDirection_Num,
+    NvRmDmaDirection_Force32 = 0x7FFFFFFF
+} NvRmDmaDirection;
+
+/**
+ * @brief Specify the priority of the dma either low priority or high priority.
+ */
+
+typedef enum
+{
+
+    /// Low priority DMA, no guarantee of latency to start transactions
+        NvRmDmaPriority_Low = 0x1,
+
+    /// High priority DMA guarantees the first buffer you send the 
+    /// NvRmDmaStartDmaTransfer() will begin immediately.
+        NvRmDmaPriority_High,
+    NvRmDmaPriority_Num,
+    NvRmDmaPriority_Force32 = 0x7FFFFFFF
+} NvRmDmaPriority;
+
+/**
+ * @brief Get the capabilities of the dma channels.
+ * 
+ * @param hDevice Handle to RM device.
+ * @param pRmDmaCaps Pointer to the capability structure where the cpas value 
+ * will be stored.
+ *
+ * @retval NvSuccess Indicates the function completed successfully.
+ */
+
+ NvError NvRmDmaGetCapabilities( 
+    NvRmDeviceHandle hDevice,
+    NvRmDmaCapabilities * pRmDmaCaps );
+
+/**
+ * @brief Allocate the DMA channel for the data transfer. The dma is allocated
+ * based on the dma device Id information. Most of the configuration is also
+ * done based on the source/destination device Id during the channel
+ * allocation.  It initializes the channel also with standard configuration
+ * based on source/ destination device.  The data is transferred from memory to
+ * the dma requestor device or vice versa.  The dma requestors device can be
+ * memory or any peripheral device listed in the NvRmDmaDeviceId.
+ * 
+ * Assert encountered in debug mode if passed parameter is invalid.
+ *
+ * @param hRmDevice Handle to RM device.
+ * @param phDma Pointer to the dma handle where the allocated dma handle
+ * will be stored.
+ * @param Enable32bitSwap if set to NV_TRUE will unconditionally reverse the
+ * memory order of bytes on 4-byte chunks.  D3:D2:D1:D0 becomes D0:D1:D2:D3
+ * @param Priority Selects either Hi or Low priority.  A Low priority
+ * allocation will only fail if the system is out of memory, and transfers on a
+ * Low priority channel will be intermixed with other clients of that channel.
+ * Hi priority allocations may fail if there is not a dedicated channel
+ * available for the Hi priority client.  Hi priority channels should only be
+ * used if you have very specific latency requirements.
+ * @param DmaRequestorModuleId Specifies a source module Id.
+ * @param DmaRequestorInstanceId Specifies the instance of the source module.
+ * 
+ * @retval NvSuccess Indicates the function completed successfully.
+ * @retval NvDMAChannelNotAvailable Indicates that there is no channel
+ * available for allocation.
+ * @retval NvError_InsufficientMemory Indicates that it will not able to
+ * allocate the memory for dma handles.
+ * @retval NvDMAInvalidSourceId Indicates that device requested is not the
+ * valid device.
+ * @retval NvError_MemoryMapFailed Indicates that the memory mapping for 
+ * controller register failed.
+ * @retval NvError_MutexCreateFailed Indicates that the creation of mutex
+ * failed.  Mutex is required to provide the thread safety.
+ * @retval NvError_SemaphoreCreateFailed Indicates that the creation of 
+ * semaphore failed. Semaphore is required to provide the synchronization and 
+ * also used in synchronous operation.
+ *
+ */
+
+ NvError NvRmDmaAllocate( 
+    NvRmDeviceHandle hRmDevice,
+    NvRmDmaHandle * phDma,
+    NvBool Enable32bitSwap,
+    NvRmDmaPriority Priority,
+    NvRmDmaModuleID DmaRequestorModuleId,
+    NvU32 DmaRequestorInstanceId );
+
+/**
+ * Frees the channel so that it can be reused by other clients.  This function
+ * will block until all currently enqueued transfers complete.
+ *
+ * @note: We may change the functionality so that Free() returns immediately
+ * but internally the channel remains in an alloc'd state until all transfers
+ * complete.
+ *
+ * @param hDma A DMA handle from NvRmDmaAllocate.  If hDma is NULL, this API has
+ *     no effect.
+ */
+
+ void NvRmDmaFree( 
+    NvRmDmaHandle hDma );
+
+/**
+ * @brief Starts the DMA channel for data transfer.
+ * 
+ * Assert encountered in debug mode if passed parameter is invalid.
+ *
+ * @param hDma Specifies a DMA handle which is allocated by the Rm dma from 
+ * NvRmDmaAllocate.
+ * @param pClientBuffer Specifies a pointer to the client information which 
+ * contains the start buffer, destination buffer, and number of bytes 
+ * transferred.
+ * @param DmaDirection Specifies whether the transfer is Forward src->dst or
+ * Reverse dst->src direction.
+ * @param WaitTimeoutInMilliSecond The time need to wait in milliseconds. If it
+ * is zero then it will be returned immediately as asynchronous operation. If
+ * is non zero then it will wait for a requested timeout. If it is
+ * NV_WAIT_INFINITE then it will wait for infinitely till transaction
+ * completes.
+ * @param AsynchSemaphoreId The semaphore Id which need to be signal if client 
+ * is requested for asynchronous operation.  Pass NULL if not semaphore should 
+ * be signalled when the transfer is complete.
+ * 
+ * @retval NvSuccess Indicates the function completed successfully.
+ * @retval NvError_InvalidAddress Indicates that the address for source or 
+ * destination is invalid.
+ * @retval NvError_InvalidSize Indicates that the bytes requested is invalid.
+ * @retval NvError_Timeout Indicates that transfer is not completed in a
+ * expected time and timeout happen.
+ */
+
+ NvError NvRmDmaStartDmaTransfer( 
+    NvRmDmaHandle hDma,
+    NvRmDmaClientBuffer * pClientBuffer,
+    NvRmDmaDirection DmaDirection,
+    NvU32 WaitTimeoutInMilliSecond,
+    NvOsSemaphoreHandle AsynchSemaphoreId );
+
+/**
+ * @brief Aborts the currently running transfer as well as any other transfers 
+ * that are queued up behind the currently running transfer.
+ * 
+ * @param hDma Specifies a DMA handle which is allocated by the Rm dma from 
+ * NvRmDmaAllocate.
+ */
+
+ void NvRmDmaAbort( 
+    NvRmDmaHandle hDma );
+
+/**
+ * @brief Get the number of bytes transferred by the dma in current tranaction 
+ * from the last.
+ * 
+ * This will tell the number of bytes has been transferred by the dma yet from 
+ * the last transfer completes.
+ *
+ * @param hDma Specifies a DMA handle which is allocated by the Rm dma from 
+ * NvRmDmaAllocate.
+ * @param pTransferCount Pointer to the variable where number of bytes transferred 
+ * by dma will be stored.
+ * @param IsTransferStop Tells whether the current transfer is stopped or not.
+ *
+ * @retval NvSuccess Indicates the function completed successfully.
+ * @retval NvError_InvalidState The transfer is not going on.
+ */
+
+ NvError NvRmDmaGetTransferredCount( 
+    NvRmDmaHandle hDma,
+    NvU32 * pTransferCount,
+    NvBool IsTransferStop );
+
+/**
+ * @brief Tells whether the transfer is completed or not for the given dma transfer.
+ * 
+ * This will tells the first or second half of the buffer transfer for the requestor
+ * who uses the double buffering mechanism like i2s.
+ *
+ * @param hDma Specifies a DMA handle which is allocated by the Rm dma from 
+ * NvRmDmaAllocate.
+ * @param IsFirstHalfBuffer Tells whether the first half or second half of the dma transfer.
+ *
+ * @retval NV_TRUE indicates that the transfre has been completed.
+ * @retval NV_FALSE Indicates that the transfre is going on.
+ */
+
+ NvBool NvRmDmaIsDmaTransferCompletes( 
+    NvRmDmaHandle hDma,
+    NvBool IsFirstHalfBuffer );
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif
diff --git a/arch/arm/mach-tegra/include/nvrm_drf.h b/arch/arm/mach-tegra/include/nvrm_drf.h
new file mode 100644
index 000000000000..cc5cbe0cb4a3
--- /dev/null
+++ b/arch/arm/mach-tegra/include/nvrm_drf.h
@@ -0,0 +1,156 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_NVRM_DRF_H
+#define INCLUDED_NVRM_DRF_H
+
+/**
+ *  @defgroup nvrm_drf RM DRF Macros
+ * 
+ *  @ingroup nvddk_rm
+ * 
+ * The following suite of macros are used for generating values to write into
+ * hardware registers, or for extracting fields from read registers.  The
+ * hardware headers have a RANGE define for each field in the register in the
+ * form of x:y, 'x' being the high bit, 'y' the lower.  Through a clever use
+ * of the C ternary operator, x:y may be passed into the macros below to
+ * geneate masks, shift values, etc.
+ *
+ * There are two basic flavors of DRF macros, the first is used to define
+ * a new register value from 0, the other is modifiying a field given a
+ * register value.  An example of the first:
+ *
+ * reg = NV_DRF_DEF( HW, REGISTER0, FIELD0, VALUE0 )
+ *     | NV_DRF_DEF( HW, REGISTER0, FIELD3, VALUE2 );
+ *
+ * To modify 'reg' from the previous example:
+ *
+ * reg = NV_FLD_SET_DRF_DEF( HW, REGISTER0, FIELD2, VALUE1, reg );
+ *
+ * To pass in numeric values instead of defined values from the header:
+ *
+ * reg = NV_DRF_NUM( HW, REGISTER3, FIELD2, 1024 );
+ *
+ * To read a value from a register:
+ *
+ * val = NV_DRF_VAL( HW, REGISTER3, FIELD2, reg );
+ *
+ * Some registers have non-zero reset values which may be extracted from the
+ * hardware headers via NV_RESETVAL.
+ */
+
+/*
+ * The NV_FIELD_* macros are helper macros for the public NV_DRF_* macros.
+ */
+#define NV_FIELD_LOWBIT(x)      (0?x)
+#define NV_FIELD_HIGHBIT(x)     (1?x)
+#define NV_FIELD_SIZE(x)        (NV_FIELD_HIGHBIT(x)-NV_FIELD_LOWBIT(x)+1)
+#define NV_FIELD_SHIFT(x)       ((0?x)%32)
+#define NV_FIELD_MASK(x)        (0xFFFFFFFFUL>>(31-((1?x)%32)+((0?x)%32)))
+#define NV_FIELD_BITS(val, x)   (((val) & NV_FIELD_MASK(x))<<NV_FIELD_SHIFT(x))
+#define NV_FIELD_SHIFTMASK(x)   (NV_FIELD_MASK(x)<< (NV_FIELD_SHIFT(x)))
+
+/** NV_DRF_DEF - define a new register value.
+
+    @ingroup nvrm_drf
+ 
+    @param d register domain (hardware block)
+    @param r register name
+    @param f register field
+    @param c defined value for the field
+ */
+#define NV_DRF_DEF(d,r,f,c) \
+    ((d##_##r##_0_##f##_##c) << NV_FIELD_SHIFT(d##_##r##_0_##f##_RANGE))
+
+/** NV_DRF_NUM - define a new register value.
+
+    @ingroup nvrm_drf
+ 
+    @param d register domain (hardware block)
+    @param r register name
+    @param f register field
+    @param n numeric value for the field
+ */
+#define NV_DRF_NUM(d,r,f,n) \
+    (((n)& NV_FIELD_MASK(d##_##r##_0_##f##_RANGE)) << \
+        NV_FIELD_SHIFT(d##_##r##_0_##f##_RANGE))
+
+/** NV_DRF_VAL - read a field from a register.
+
+    @ingroup nvrm_drf
+
+    @param d register domain (hardware block)
+    @param r register name
+    @param f register field
+    @param v register value
+ */
+#define NV_DRF_VAL(d,r,f,v) \
+    (((v)>> NV_FIELD_SHIFT(d##_##r##_0_##f##_RANGE)) & \
+        NV_FIELD_MASK(d##_##r##_0_##f##_RANGE))
+
+/** NV_FLD_SET_DRF_NUM - modify a register field.
+
+    @ingroup nvrm_drf
+
+    @param d register domain (hardware block)
+    @param r register name
+    @param f register field
+    @param n numeric field value
+    @param v register value
+ */
+#define NV_FLD_SET_DRF_NUM(d,r,f,n,v) \
+    ((v & ~NV_FIELD_SHIFTMASK(d##_##r##_0_##f##_RANGE)) | NV_DRF_NUM(d,r,f,n))
+
+/** NV_FLD_SET_DRF_DEF - modify a register field.
+
+    @ingroup nvrm_drf
+
+    @param d register domain (hardware block)
+    @param r register name
+    @param f register field
+    @param c defined field value
+    @param v register value
+ */
+#define NV_FLD_SET_DRF_DEF(d,r,f,c,v) \
+    (((v) & ~NV_FIELD_SHIFTMASK(d##_##r##_0_##f##_RANGE)) | \
+        NV_DRF_DEF(d,r,f,c))
+
+/** NV_RESETVAL - get the reset value for a register.
+
+    @ingroup nvrm_drf
+
+    @param d register domain (hardware block)
+    @param r register name
+ */
+#define NV_RESETVAL(d,r)    (d##_##r##_0_RESET_VAL)
+
+#endif // INCLUDED_NVRM_DRF_H
diff --git a/arch/arm/mach-tegra/include/nvrm_gpio.h b/arch/arm/mach-tegra/include/nvrm_gpio.h
new file mode 100644
index 000000000000..62a711638621
--- /dev/null
+++ b/arch/arm/mach-tegra/include/nvrm_gpio.h
@@ -0,0 +1,389 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_nvrm_gpio_H
+#define INCLUDED_nvrm_gpio_H
+
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+#include "nvrm_init.h"
+
+
+/** @file
+ * @brief <b>NVIDIA Driver Development Kit NvRm gpio APIs</b>
+ *
+ * @b Description: Declares Interface for NvRm gpio module.
+ */
+
+ /**
+ * @defgroup nvrm_gpio RM GPIO Services
+ * 
+ * This is the Resource Manager interface to general-purpose input-output
+ * (GPIO) services. Fundamental abstraction of this API is a "pin handle", which
+ * of type NvRmGpioPinHandle. A Pin handle is acquired by making a call to 
+ * NvRmGpioAcquirePinHandle API. This API returns a pin handle which is
+ * subsequently used by the rest of the GPIO APIs.
+ *
+ * @ingroup nvddk_rm
+ * @{
+ */
+
+#include "nvcommon.h"
+#include "nvos.h"
+
+/**
+ *  NvRmGpioHandle is an opaque handle to the GPIO device on the chip.
+ */
+
+typedef struct NvRmGpioRec *NvRmGpioHandle;
+
+/**
+ * @brief GPIO pin handle which describes the physical pin. This values should
+ * not be cached or hardcoded by the drivers. This can vary from chip to chip
+ * and board to board.
+ */
+ 
+typedef NvU32 NvRmGpioPinHandle;
+
+/**
+ * @brief Defines the possible gpio pin modes.
+ */
+
+typedef enum
+{
+
+    /**
+     * Specifies the gpio pin as not in use. When in this state, the RM or
+     * ODM Kit may park the pin in a board-specific state in order to
+     * minimize leakage current.
+     */
+    NvRmGpioPinMode_Inactive = 1,
+
+    /// Specifies the gpio pin mode as input and enable interrupt for level low.
+    NvRmGpioPinMode_InputInterruptLow,
+
+    /// Specifies the gpio pin mode as input and enable interrupt for level high.
+    NvRmGpioPinMode_InputInterruptHigh,
+
+    /// Specifies the gpio pin mode as input and no interrupt configured.
+    NvRmGpioPinMode_InputData,
+
+    /// Specifies the gpio pin mode as output.
+    NvRmGpioPinMode_Output,
+
+    /// Specifies the gpio pin mode as a special function.
+    NvRmGpioPinMode_Function,
+
+    /// Specifies the gpio pin as input and interrupt configured to any edge.
+    /// i.e seamphore will be signaled for both the rising and failling edges.
+    NvRmGpioPinMode_InputInterruptAny,
+
+    /// Sepciifed the gpio pin a input and interrupt configured to rising edge.
+    NvRmGpioPinMode_InputInterruptRisingEdge,
+
+    /// Sepciifed the gpio pin a input and interrupt configured to falling edge.
+    NvRmGpioPinMode_InputInterruptFallingEdge,
+    NvRmGpioPinMode_Num,
+    NvRmGpioPinMode_Force32 = 0x7FFFFFFF
+} NvRmGpioPinMode;
+
+/** 
+ * @brief Defines the pin state
+ */
+
+typedef enum
+{
+
+   // Pin state high 
+    NvRmGpioPinState_Low = 0,
+
+    // Pin is high
+    NvRmGpioPinState_High,
+  
+    // Pin is in tri state 
+    NvRmGpioPinState_TriState,
+    NvRmGpioPinState_Num,
+    NvRmGpioPinState_Force32 = 0x7FFFFFFF
+} NvRmGpioPinState;
+
+// Gnerates a contruct the pin handle till the NvRmGpioAcquirePinHandle
+// API is implemented.
+#define GPIO_MAKE_PIN_HANDLE(inst, port, pin)  (0x80000000 | (((NvU32)(pin) & 0xFF)) | (((NvU32)(port) & 0xff) << 8) | (((NvU32)(inst) & 0xff )<< 16))
+#define NVRM_GPIO_CAMERA_PORT (0xfe)
+#define NVRM_GPIO_CAMERA_INST (0xfe)
+
+/**
+ * Creates and opens a GPIO handle. The handle can then be used to
+ * access GPIO functions.
+ * 
+ * @param hRmDevice The RM device handle.
+ * @param phGpio Specifies a pointer to the gpio handle where the
+ * allocated handle is stored. The memory for handle is allocated
+ * inside this API.
+ * 
+ * @retval NvSuccess gpio initialization is successful.
+ */
+
+ NvError NvRmGpioOpen( 
+    NvRmDeviceHandle hRmDevice,
+    NvRmGpioHandle * phGpio );
+
+/**
+ * Closes the GPIO handle. Any pin settings made while this handle was
+ * open will remain. All events enabled by this handle will be
+ * disabled.
+ * 
+ * @param hGpio A handle from NvRmGpioOpen().  If hGpio is NULL, this API does
+ *     nothing.
+ */
+
+ void NvRmGpioClose( 
+    NvRmGpioHandle hGpio );
+
+/** Get NvRmGpioPinHandle from the physical port and pin number. If a driver
+ * acquires a pin handle another driver will not be able to use this until the
+ * pin is released.
+ *
+ * @param hGpio A handle from NvRmGpioOpen().
+ * @param port Physical gpio ports which are chip specific.
+ * @param pinNumber pin number in that port.
+ * @param phGpioPin Pointer to the GPIO pin handle.
+ */
+
+ NvError NvRmGpioAcquirePinHandle( 
+    NvRmGpioHandle hGpio,
+    NvU32 port,
+    NvU32 pin,
+    NvRmGpioPinHandle * phPin );
+
+/** Releases the pin handles acquired by NvRmGpioAcquirePinHandle API.
+ *
+ * @param hGpio A handle got from NvRmGpioOpen().
+ * @param hPin Array of pin handles got from NvRmGpioAcquirePinHandle().
+ * @param pinCount Size of pin handles array.
+ */
+
+ void NvRmGpioReleasePinHandles( 
+    NvRmGpioHandle hGpio,
+    NvRmGpioPinHandle * hPin,
+    NvU32 pinCount );
+
+/**
+ * Sets the state of array of pins.
+ *
+ * NOTE:  When multiple pins are specified (pinCount is greater than
+ * one), ODMs should not make assumptions about the order in which
+ * pins are updated.  The implementation will attempt to coalesce
+ * updates to occur atomically; however, this can not be guaranteed in
+ * all cases, and may not occur if the list of pins includes pins from
+ * multiple ports.
+ *
+ * @param hGpio Specifies the gpio handle.
+ * @param pin Array of pin handles.
+ * @param pinState Array of elements specifying the pin state (of type
+ * NvRmGpioPinState).
+ * @param pinCount Number of elements in the array.
+ */
+
+ void NvRmGpioWritePins( 
+    NvRmGpioHandle hGpio,
+    NvRmGpioPinHandle * pin,
+    NvRmGpioPinState * pinState,
+    NvU32 pinCount );
+
+/**
+ * Reads the state of array of pins.
+ * 
+ * @param hGpio The gpio handle.
+ * @param pin Array of pin handles.
+ * @param pinState Array of elements specifying the pin state (of type
+ * NvRmGpioPinState).
+ * @param pinCount Number of elements in the array.
+ */
+
+ void NvRmGpioReadPins( 
+    NvRmGpioHandle hGpio,
+    NvRmGpioPinHandle * pin,
+    NvRmGpioPinState * pPinState,
+    NvU32 pinCount );
+
+/**
+ * Configures a set of GPIO pins to a specified mode. Don't use this API for
+ * the interrupt modes. For interrupt modes, use NvRmGpioInterruptRegister and
+ * NvRmGpioInterruptUnregister APIs.
+ *
+ * @param hGpio The gpio handle.
+ * @param pin Pin handle array returned by a calls to NvRmGpioAcquirePinHandle()
+ * @param pinCount Number elements in the pin handle array.
+ *
+ * @param Mode Pin mode of type NvRmGpioPinMode.
+ * 
+ * 
+ * @retval NvSuccess requested operation is successful.
+ */
+
+ NvError NvRmGpioConfigPins( 
+    NvRmGpioHandle hGpio,
+    NvRmGpioPinHandle * pin,
+    NvU32 pinCount,
+    NvRmGpioPinMode Mode );
+
+/*
+ *  Get the IRQs associated with the pin handles. So that the client can
+ *  register the interrupt callback for that using interrupt APIs
+ */
+
+ NvError NvRmGpioGetIrqs( 
+    NvRmDeviceHandle hRmDevice,
+    NvRmGpioPinHandle * pin,
+    NvU32 * Irq,
+    NvU32 pinCount );
+
+/** 
+ *   Opaque handle to the GPIO interrupt.
+ */
+
+typedef struct NvRmGpioInterruptRec *NvRmGpioInterruptHandle;
+
+
+/* NOTE: Use the 2 APIs below to configure the gpios to interrupt mode and to
+ * have callabck functions. For the test case of how to use this APIs refer to
+ * the nvrm_gpio_unit_test applicaiton. 
+ * 
+ *  Since the ISR is written by the clients of the API, care should be taken to
+ *  clear the interrupt before the ISR is returned. If one fails to do that,
+ *  interrupt will be triggered soon after the ISR returns.
+ */
+
+/**
+ * Registers an interrupt callback function and the mode of interrupt for the
+ * gpio pin specified.
+ *  
+ * Callback will be using the interrupt thread an the interrupt stack on linux
+ * and IST on wince. So, care should be taken on what APIs can be used on the
+ * callback function. Not all the nvos functions are available in the interrupt
+ * context. Check the nvos.h header file for the list of the functions available.
+ * When the callback is called, the interrupt on the pin is disabled. As soon as
+ * the callback exists, the interrupt is re-enabled. So, external interrupts
+ * should be cleared and then only the callback should be returned.
+ *
+ * @param hGpio The gpio handle.
+ * @param hRm The RM device handle.
+ * @param hPin The handle to a GPIO pin.
+ * @param Callback Callback function which will be caused when the interrupt
+ * triggers.
+ * @param Mode Interrupt mode. See @NvRmGpioPinMode
+ * @param CallbackArg Argument used when the callback is called by the ISR.
+ * @param hGpioInterrupt Interrupt handle for this registered intterrupt. This
+ * handle should be used while calling NvRmGpioInterruptUnregister for
+ * unregistering the interrupt.
+ * @param DebounceTime The debounce time in milliseconds
+ * @retval NvSuccess requested operation is successful.
+ */
+NvError 
+NvRmGpioInterruptRegister(
+    NvRmGpioHandle hGpio,
+    NvRmDeviceHandle hRm,
+    NvRmGpioPinHandle hPin, 
+    NvOsInterruptHandler Callback,
+    NvRmGpioPinMode Mode,
+    void *CallbackArg,
+    NvRmGpioInterruptHandle *hGpioInterrupt,
+    NvU32 DebounceTime);
+
+/**
+ * Unregister the GPIO interrupt handler.
+ *
+ * @param hGpio The gpio handle.
+ * @param hRm The RM device handle.
+ * @param handle The interrupt handle returned by a successfull call to the
+ * NvRmGpioInterruptRegister API.
+ *
+ */
+void 
+NvRmGpioInterruptUnregister(
+    NvRmGpioHandle hGpio,
+    NvRmDeviceHandle hRm,
+    NvRmGpioInterruptHandle handle);
+
+/**
+ * Enable the GPIO interrupt handler.
+ *
+ * @param handle The interrupt handle returned by a successfull call to the
+ * NvRmGpioInterruptRegister API.
+ *
+ * @retval "NvError_BadParameter" if handle is not valid
+ * @retval "NvError_InsufficientMemory" if interupt enable failed.
+ * @retval "NvSuccess" if registration is successfull.
+*/
+NvError
+NvRmGpioInterruptEnable(NvRmGpioInterruptHandle handle);
+
+/* 
+ * Callback used to re-enable the interrupts.
+ *
+ * @param handle The interrupt handle returned by a successfull call to the
+ * NvRmGpioInterruptRegister API.
+ */
+void
+NvRmGpioInterruptDone( NvRmGpioInterruptHandle handle );
+
+
+
+/**
+ * Mask/Unmask a gpio interrupt.
+ *
+ * Drivers can use this API to fend off interrupts. Mask means interrupts are
+ * not forwarded to the CPU. Unmask means, interrupts are forwarded to the CPU.
+ * In case of SMP systems, this API masks the interrutps to all the CPU, not
+ * just the calling CPU.
+ *
+ *
+ * @param handle    Interrupt handle returned by NvRmGpioInterruptRegister API.
+ * @param mask      NV_FALSE to forrward the interrupt to CPU. NV_TRUE to 
+ * mask the interupts to CPU.
+ */
+void
+NvRmGpioInterruptMask(NvRmGpioInterruptHandle hGpioInterrupt, NvBool mask);
+
+
+/** @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif
diff --git a/arch/arm/mach-tegra/include/nvrm_hardware_access.h b/arch/arm/mach-tegra/include/nvrm_hardware_access.h
new file mode 100644
index 000000000000..497fd94e57a1
--- /dev/null
+++ b/arch/arm/mach-tegra/include/nvrm_hardware_access.h
@@ -0,0 +1,151 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_NVRM_HARDWARE_ACCESS_H
+#define INCLUDED_NVRM_HARDWARE_ACCESS_H
+
+#include "nvcommon.h"
+#include "nvrm_init.h"
+#include "nvos.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif  /* __cplusplus */
+
+#if !defined(NV_OAL)
+#define NV_OAL 0
+#endif
+
+// By default, sim is supported on WinXP/x86 and Linux/x86 builds only.
+#if !defined(NV_DEF_ENVIRONMENT_SUPPORTS_SIM)
+#if NVCPU_IS_X86 && ((NVOS_IS_WINDOWS && !NVOS_IS_WINDOWS_CE) || NVOS_IS_LINUX) && !NV_OAL
+#define NV_DEF_ENVIRONMENT_SUPPORTS_SIM 1
+#else
+#define NV_DEF_ENVIRONMENT_SUPPORTS_SIM 0
+#endif
+#endif
+
+/**
+ * NV_WRITE* and NV_READ* - low level read/write api to hardware.
+ *
+ * These macros should be used to read and write registers and memory
+ * in NvDDKs so that the DDK will work on simulation and real hardware
+ * with no changes.
+ *
+ * This is for hardware modules that are NOT behind the host.  Modules that
+ * are behind the host should use nvrm_channel.h.
+ *
+ * A DDK can obtain a mapping to its registers by using the
+ * NvRmPhysicalMemMap() function.  This mapping is always uncached.  The
+ * resulting pointer can then be used with NV_READ and NV_WRITE.
+ */
+
+/*
+ * Maps the given physical address to the user's virtual address space.
+ *
+ * @param phys The physical address to map into the virtual address space
+ * @param size The size of the mapping
+ * @param flags Any flags for the mapping -- exactly match's NVOS_MAP_*
+ * @param memType The memory mapping to use (uncached, write-combined, etc.)
+ * @param ptr Output -- the resulting virtual pointer
+ */
+// FIXME: NvOs needs to take this up, however I think this is more
+// complex than just mapping.  E.G. does it map into the kernel vaddr, or
+// the current process vaddr? And how does this work on windows and
+// windows-ce?
+NvError NvRmPhysicalMemMap(NvRmPhysAddr phys, size_t size, NvU32 flags,
+    NvOsMemAttribute memType, void **ptr );
+
+/*
+ * Unmaps the given virtual address from NvRmPhysicalMemMap.
+ */
+void NvRmPhysicalMemUnmap(void *ptr, size_t size);
+
+/**
+ * NV_WRITE[8|16|32|64] - Writes N data bits to hardware.
+ *
+ *   @param a The address to write.
+ *   @param d The data to write.
+ */
+
+/**
+ * NV_READ[8|16|32|64] - Reads N bits from hardware.
+ *
+ * @param a The address to read.
+ */
+
+void NvWrite08(void *addr, NvU8 data);
+void NvWrite16(void *addr, NvU16 data);
+void NvWrite32(void *addr, NvU32 data);
+void NvWrite64(void *addr, NvU64 data);
+NvU8 NvRead08(void *addr);
+NvU16 NvRead16(void *addr);
+NvU32 NvRead32(void *addr);
+NvU64 NvRead64(void *addr);
+void NvWriteBlk(void *dst, const void *src, NvU32 length);
+void NvReadBlk(void *dst, const void *src, NvU32 length);
+
+#if NV_DEF_ENVIRONMENT_SUPPORTS_SIM == 1
+
+#define NV_WRITE08(a,d)     NvWrite08((void *)(a),(d))
+#define NV_WRITE16(a,d)     NvWrite16((void *)(a),(d))
+#define NV_WRITE32(a,d)     NvWrite32((void *)(a),(d))
+#define NV_WRITE64(a,d)     NvWrite64((void *)(a),(d))
+#define NV_READ8(a)         NvRead08((void *)(a))
+#define NV_READ16(a)        NvRead16((void *)(a))
+#define NV_READ32(a)        NvRead32((void *)(a))
+#define NV_READ64(a)        NvRead64((void *)(a))
+#define NV_WRITE(dst, src, len) NvWriteBlk(dst, src, len)
+#define NV_READ(dst, src, len)  NvReadBlk(dst, src, len)
+
+#else
+/* connected to hardware */
+
+#define NV_WRITE08(a,d)     *((volatile NvU8 *)(a)) = (d)
+#define NV_WRITE16(a,d)     *((volatile NvU16 *)(a)) = (d)
+#define NV_WRITE32(a,d)     *((volatile NvU32 *)(a)) = (d)
+#define NV_WRITE64(a,d)     *((volatile NvU64 *)(a)) = (d)
+#define NV_READ8(a)         *((const volatile NvU8 *)(a))
+#define NV_READ16(a)        *((const volatile NvU16 *)(a))
+#define NV_READ32(a)        *((const volatile NvU32 *)(a))
+#define NV_READ64(a)        *((const volatile NvU64 *)(a))
+#define NV_WRITE(dst, src, len)  NvOsMemcpy(dst, src, len)
+#define NV_READ(dst, src, len)   NvOsMemcpy(dst, src, len)
+
+#endif // !hardware
+
+#ifdef __cplusplus
+}
+#endif  /* __cplusplus */
+
+#endif // INCLUDED_NVRM_HARDWARE_ACCESS_H
diff --git a/arch/arm/mach-tegra/include/nvrm_i2c.h b/arch/arm/mach-tegra/include/nvrm_i2c.h
new file mode 100644
index 000000000000..5cc245def79b
--- /dev/null
+++ b/arch/arm/mach-tegra/include/nvrm_i2c.h
@@ -0,0 +1,216 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_nvrm_i2c_H
+#define INCLUDED_nvrm_i2c_H
+
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+#include "nvrm_pinmux.h"
+#include "nvrm_module.h"
+#include "nvrm_init.h"
+
+#include "nvos.h"
+#include "nvcommon.h"
+
+/**
+ * NvRmI2cHandle is an opaque handle to the NvRmI2cStructRec interface
+ */
+ 
+typedef struct NvRmI2cRec *NvRmI2cHandle;
+
+/**
+ * @brief Defines the I2C capability structure. It contains the 
+ * capabilities/limitations (like maximum bytes transferred,  
+ * supported clock speed) of the hardware.
+ */
+ 
+typedef struct NvRmI2cCapabilitiesRec
+{
+
+    /**
+     * Maximum number of packet length in bytes which can be transferred
+     * between start and the stop pulses.
+     */
+    NvU32 MaximumPacketLengthInBytes;
+
+    /// Maximum speed which I2C controller can support.
+    NvU32 MaximumClockSpeed;
+
+    /// Minimum speed which I2C controller can support.
+    NvU32 MinimumClockSpeed;
+} NvRmI2cCapabilities;
+
+/**
+ * @brief Initializes and opens the i2c channel. This function allocates the
+ * handle for the i2c channel and provides it to the client.
+ *
+ * Assert encountered in debug mode if passed parameter is invalid.
+ *
+ * @param hDevice Handle to the Rm device which is required by Rm to acquire
+ * the resources from RM.
+ * @param IoModule The IO module to set, it is either NvOdmIoModule_I2c
+ * or NvOdmIoModule_I2c_Pmu
+ * @param instance Instance of the i2c driver to be opened.
+ * @param phI2c Points to the location where the I2C handle shall be stored.
+ *
+ * @retval NvSuccess Indicates that the I2c channel has successfully opened.
+ * @retval NvError_InsufficientMemory Indicates that function fails to allocate
+ * the memory.
+ * @retval NvError_NotInitialized Indicates the I2c initialization failed.
+ */
+
+ NvError NvRmI2cOpen( 
+    NvRmDeviceHandle hDevice,
+    NvU32 IoModule,
+    NvU32 instance,
+    NvRmI2cHandle * phI2c );
+
+/** 
+ * @brief Closes the i2c channel. This function frees the memory allocated for
+ * the i2c handle for the i2c channel.
+ * This function de-initializes the i2c channel. This API never fails.
+ *
+ * @param hI2c A handle from NvRmI2cOpen().  If hI2c is NULL, this API does
+ *     nothing.
+ */
+
+ void NvRmI2cClose( 
+    NvRmI2cHandle hI2c );
+
+// Maximum number of bytes that can be sent between the i2c start and stop conditions
+#define NVRM_I2C_PACKETSIZE (8)
+
+// Maximum number of bytes that can be sent between the i2c start and repeat start condition.
+#define NVRM_I2C_PACKETSIZE_WITH_NOSTOP (4)
+
+/// Indicates a I2C read transaction.
+#define NVRM_I2C_READ (0x1)
+
+/// Indicates that it is a write transaction
+#define NVRM_I2C_WRITE (0x2)
+
+/// Indicates that there is no STOP following this transaction. This also implies
+/// that there is always one more transaction following a transaction with
+/// NVRM_I2C_NOSTOP attribute.
+#define NVRM_I2C_NOSTOP (0x4)
+
+//  Some devices doesn't support ACK. By, setting this flag, master will not
+//  expect the generation of ACK from the device.
+#define NVRM_I2C_NOACK (0x8)
+
+// Software I2C using GPIO. Doesn't use the hardware controllers. This path
+// should be used only for testing.
+#define NVRM_I2C_SOFTWARE_CONTROLLER (0x10)
+
+typedef struct NvRmI2cTransactionInfoRec
+{
+
+    /// Flags to indicate the transaction details, like write/read or read
+    /// without a stop or write without a stop.
+        NvU32 Flags;
+
+    /// Number of bytes to be transferred.
+        NvU32 NumBytes;
+
+    /// I2C slave device address
+        NvU32 Address;
+
+    /// Indicates that the address is a 10-bit address.
+        NvBool Is10BitAddress;
+} NvRmI2cTransactionInfo;
+
+/** 
+ * @brief Does multiple I2C transactions. Each transaction can be a read or write.
+ *
+ *  AP15 I2C controller has the following limitations:
+ *  - Any read/write transaction is limited to NVRM_I2C_PACKETSIZE
+ *  - All transactions will be terminated by STOP unless NVRM_I2C_NOSTOP flag
+ *  is specified. Specifying NVRM_I2C_NOSTOP means, *next* transaction will start
+ *  with a repeat start, with NO stop between transactions.
+ *  - When NVRM_I2C_NOSTOP is specified for a transaction - 
+ *      1. Next transaction will start with repeat start.
+ *      2. Next transaction is mandatory.
+ *      3. Next Next transaction cannot have NVRM_I2C_NOSTOP flag set. i.e no
+ *         back to back repeat starts.
+ *      4. Current and next transactions are limited to size
+ *         NVRM_I2C_PACKETSIZE_WITH_NOSTOP.
+ *      5. Finally, current transactions and next Transaction should be of same
+ *         size.
+ *
+ *  This imposes some limitations on how the hardware can be used. However, the
+ *  API itself doesn't have any limitations. If the HW cannot be used, it falls
+ *  back to GPIO based I2C. Gpio I2C bypasses Hw controller and bit bangs the
+ *  SDA/SCL lines of I2C.
+ * 
+ * @param hI2c Handle to the I2C channel.
+ * @param I2cPinMap for I2C controllers which are being multiplexed across
+ *        multiple pin mux configurations, this specifies which pin mux configuration
+ *        should be used for the transaction.  Must be 0 when the ODM pin mux query
+ *        specifies a non-multiplexed configuration for the controller.
+ * @param WaitTimeoutInMilliSeconds Timeout for the transcation. 
+ * @param ClockSpeedKHz Clock speed in KHz.
+ * @param Data Continous stream of data
+ * @param DataLength Length of the data stream
+ * @param Transcations Pointer to the NvRmI2cTransactionInfo structure
+ * @param NumOfTransactions Number of transcations
+ *
+ *
+ * @retval NvSuccess Indicates the operation succeeded.
+ * @retval NvError_NotSupported Indicates assumption on parameter values violated.
+ * @retval NvError_InvalidState Indicates that the last read call is not
+ * completed.
+ * @retval NvError_ControllerBusy Indicates controller is presently busy with an
+ * i2c transaction.
+ * @retval NvError_InvalidDeviceAddress Indicates that the slave device address
+ * is invalid
+ */
+
+ NvError NvRmI2cTransaction( 
+    NvRmI2cHandle hI2c,
+    NvU32 I2cPinMap,
+    NvU32 WaitTimeoutInMilliSeconds,
+    NvU32 ClockSpeedKHz,
+    NvU8 * Data,
+    NvU32 DataLen,
+    NvRmI2cTransactionInfo * Transaction,
+    NvU32 NumOfTransactions );
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif
diff --git a/arch/arm/mach-tegra/include/nvrm_init.h b/arch/arm/mach-tegra/include/nvrm_init.h
new file mode 100644
index 000000000000..5aaa410d5b17
--- /dev/null
+++ b/arch/arm/mach-tegra/include/nvrm_init.h
@@ -0,0 +1,142 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_nvrm_init_H
+#define INCLUDED_nvrm_init_H
+
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+
+#include "nvcommon.h"
+#include "nverror.h"
+
+/**
+ * NvRmDeviceHandle is an opaque handle to an RM device.
+ */
+
+typedef struct NvRmDeviceRec *NvRmDeviceHandle;
+
+/**
+ * A physical address type sized such that it matches the addressing support of
+ * the hardware modules RM typically interfaces with.  May be smaller than an
+ * NvOsPhysAddr.
+ *
+ * XXX We should probably get rid of this and just use NvU32.  It's rather
+ * difficult to explain what exactly NvRmPhysAddr is.  Also, what if some units
+ * are upgraded to do 64-bit addressing and others remain 32?  Would we really
+ * want to increase NvRmPhysAddr to NvU64 across the board?
+ *
+ * Another option would be to put the following types in nvcommon.h:
+ *   typedef NvU32 NvPhysAddr32;
+ *   typedef NvU64 NvPhysAddr64;
+ * Using these types would then be purely a form of documentation and nothing
+ * else.
+ *
+ * This header file is a somewhat odd place to put this type.  Putting it in
+ * memmgr would be even worse, though, because then a lot of header files would
+ * all suddenly need to #include nvrm_memmgr.h just to get the NvRmPhysAddr
+ * type.  (They already all include this header anyway.)
+ */
+
+typedef NvU32 NvRmPhysAddr;
+
+/**
+ * Opens the Resource Manager for a given device.
+ *
+ * Can be called multiple times for a given device.  Subsequent
+ * calls will not necessarily return the same handle.  Each call to
+ * NvRmOpen() must be paired with a corresponding call to NvRmClose().
+ *
+ * Assert encountered in debug mode if DeviceId value is invalid.
+ *
+ * This call is not intended to perform any significant hardware
+ * initialization of the device; rather its primary purpose is to
+ * initialize RM's internal data structures that are involved in
+ * managing the device.
+ * 
+ * @param pHandle the RM handle is stored here.
+ * @param DeviceId implementation-dependent value specifying the device
+ *     to be opened.  Currently must be set to zero.
+ *
+ * @retval NvSuccess Indicates that RM was successfully opened.
+ * @retval NvError_InsufficientMemory Indicates that RM was unable to allocate
+ *     memory for its internal data structures.
+ */
+
+ NvError NvRmOpen( 
+    NvRmDeviceHandle * pHandle,
+    NvU32 DeviceId );
+
+/**
+ * Called by the platform/OS code to initialize the Rm. Usage and
+ * implementation of this API is platform specific.
+ *  
+ * This APIs should not be called by the normal clients of the Rm.
+ *    
+ * This APIs is guaranteed to succeed on the supported platforms.
+ *
+ * @param pHandle the RM handle is stored here.
+ */
+
+ void NvRmInit( 
+    NvRmDeviceHandle * pHandle );
+
+/**
+ * Temporary version of NvRmOpen lacking the DeviceId parameter
+ */
+
+ NvError NvRmOpenNew( 
+    NvRmDeviceHandle * pHandle );
+
+/**
+ * Closes the Resource Manager for a given device.
+ *
+ * Each call to NvRmOpen() must be paired with a corresponding call 
+ * to NvRmClose().
+ *
+ * @param hDevice The RM handle.  If hDevice is NULL, this API has no effect.
+ */
+
+ void NvRmClose( 
+    NvRmDeviceHandle hDevice );
+
+/** @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif
diff --git a/arch/arm/mach-tegra/include/nvrm_interrupt.h b/arch/arm/mach-tegra/include/nvrm_interrupt.h
new file mode 100644
index 000000000000..ad06f78b1c8b
--- /dev/null
+++ b/arch/arm/mach-tegra/include/nvrm_interrupt.h
@@ -0,0 +1,271 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_nvrm_interrupt_H
+#define INCLUDED_nvrm_interrupt_H
+
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+#include "nvrm_module.h"
+#include "nvrm_init.h"
+
+#include "nvos.h"
+
+/** @file
+ * @brief <b>NVIDIA Driver Development Kit:
+ *     Resource Manager %Interrupt API</b>
+ *
+ * @b Description: Declares the interrupt API for use by NvDDK modules.
+ */
+
+/**
+ * @defgroup nvrm_interrupt RM Interrupt Management Services
+ *
+ * @ingroup nvddk_rm
+ * @{
+ *
+ * IRQ Numbers
+ * -----------
+ * In most cases, we are using the CPU's legacy interrupt support, rather than
+ * the new MPCore interrupt controller.  This means that we only have one ISR
+ * shared between all of the devices in our chip.  To determine which device is
+ * interrupting us, we have to read some registers.  We assign each interrupt
+ * source an "IRQ number".  IRQ numbers are OS-independent and HW-dependent (a
+ * given device may have a different IRQ number from chip to chip).
+ *
+ * It is arbitrary how far we decode interrupts as part of determining the IRQ
+ * number.  Normally we might assign one IRQ number to each interrupt line that
+ * feeds into the main interrupt controller (typically one per device in the
+ * chip), but we can decode further if we want.  For example, there are several
+ * GPIO controllers, each of which controls 32 GPIO lines.  The GPIO controller
+ * interrupt line is constructed by OR'ing together the interrupt lines for each
+ * of the 32 GPIO pins.  If we want, we can assign each GPIO controller 32
+ * separate IRQ numbers, one per GPIO line; this simply means we have to sub-
+ * decode the interrupts a little further inside the ISR.
+ *
+ * The main advantage of doing this sub-decoding is that only a single driver is
+ * allowed to hook each interrupt source -- if multiple drivers both want to
+ * register interrupt handlers for the same interrupt source, the drivers will
+ * fight with one another trying to handle the same interrupt, so this is an
+ * error.  At the same time, it's entirely plausible that out of a group of 32
+ * GPIO pins, multiple different drivers care about different groups of those
+ * pins.  In the absence of sub-decoding, we would have to implement a "GPIO
+ * driver" whose sole purpose was to allow those other drivers to register for
+ * GPIO notifications, and then use driver-to-driver signaling to indicate when
+ * a pin has transitioned state.  This is an extra level of overhead compared
+ * to if drivers are allowed to directly hook the interrupts for the pins they
+ * care about.
+ *
+ * Because IRQ numbers change from chip to chip, you must ask the RM for the IRQ
+ * number of the device when you want to hook its interrupt.  This can be
+ * accomplished using the NvRmGetIrqForLogicalInterrupt() API.  You pass it an
+ * [NvRmModuleID, Index] pair telling it what device you are interested in, and
+ * which sub-interrupt within that device.  Often Index is just zero (many
+ * devices only have one IRQ number).  For GPIO it might by the pin number
+ * within the GPIO controller.  For UART, you might (entirely hypothetically --
+ * there is no requirement that you do this) have Index=0 for the receive
+ * interrupt and Index=1 for the send interrupt.
+ *
+ * Hooking an Interrupt
+ * --------------------
+ * Once you have the IRQ number(s), you can hook the interrupt(s) by calling
+ * NvRmInterruptRegister().  At driver shutdown, you can unhook the interrupt(s)
+ * by calling NvRmInterruptUnregister().
+ *
+ * NvRmInterruptRegister takes a list of IRQs and a list of callback functions to be
+ * called when the corresponding interrupt has fired.  The callback functions
+ * will be passed an extra "void *context" parameter, typically a pointer to
+ * your private driver structure that keeps track of the state of your device.
+ * For example, the NAND driver might pass the NvDdkNandHandle as the context
+ * param.
+ *
+ * Drivers that care about more than one IRQ should call NvRmInterruptRegister only
+ * once.  Calling NvRmInterruptRegister twice (each time with a single IRQ number)
+ * may consume more system resources than calling NvRmInterruptRegister once with
+ * a list of 2 IRQ numbers and 2 callbacks.
+ *
+ * Rules for Interrupt Handlers
+ * ----------------------------
+ * We assume that all interrupt handlers (i.e. the callbacks passed to
+ * NvRmInterruptRegister) are "fast": that is, any complex processing that cannot
+ * complete in a tightly bounded amount of time, such as polling registers to
+ * wait for the HW to complete some processing, is not done in the ISR proper.
+ * Instead, the ISR would signal a semaphore, clear the interrupt, and pass off
+ * the rest of the work to another thread.
+ *
+ * To be more precise about this, we expect all interrupt handlers to follow
+ * these rules:
+ * - They may only call a subset of NvOs functions.  The exact subset is
+ *   documented in nvos.h.
+ * - No floating-point.  (We don't want to have to save and restore the
+ *   floating point registers on an interrupt.)
+ * - They should use as little stack space as possible.  They certainly should
+ *   not use any recursive algorithms, for example.  (For example, if they need
+ *   to look up a node in a red-black tree, they must use an iterative version
+ *   of the tree search rather than recursion.)  Straw man: 256B maximum?
+ * - Any control flow structure that involves looping (like a "for" or "while"
+ *   statement) must be guaranteed to terminate within a clearly understood
+ *   time limit.  We don't have a strict upper bound, but if it takes
+ *   milliseconds, it's out of the question.
+ * - The callback function _must_ clear the cause of the interrupt.  Upon
+ *   returning from the callback the interrupt will be automatically re-enabled.
+ *   If the cause is not cleared the system will be stuck in an infinite loop
+ *   taking interrupts.
+ */
+
+/**
+ * A Logical Interrupt is a tuple that includes the class of interrupts
+ * (i.e., a module), an instance of that module, and the specific interrupt
+ * within that instance (an index).  This is an abstraction for the
+ * actual interrupt bits implemented on the SOC.
+ */
+
+typedef struct NvRmLogicalIntrRec
+{
+
+    /**
+     * Interrupt index within the current instance of specified Module.
+     * This identifies a specific interrupt.  This is an enumerated index
+     * and not a bit-mask.
+     */
+        NvU8 Index;
+
+    /**
+     * The SOC hardware controller class identifier
+     */
+        NvRmModuleID ModuleID;
+} NvRmLogicalIntr;
+
+/**
+ * Translate a given logical interrupt to its corresponding IRQ number.
+ *
+ * @param hRmDevice The RM device handle
+ * @param ModuleID The module of interest
+ * @param Index Zero-based interrupt index within the module
+ *
+ * @return The IRQ number.
+ */
+
+ NvU32 NvRmGetIrqForLogicalInterrupt( 
+    NvRmDeviceHandle hRmDevice,
+    NvRmModuleID ModuleID,
+    NvU32 Index );
+
+/**
+ * Retrieve the number of IRQs associated with a particular module instance.
+ *
+ * @param hRmDevice The RM device handle
+ * @param ModuleID The module of interest
+ *
+ * @return The number of IRQs.
+ */
+
+ NvU32 NvRmGetIrqCountForLogicalInterrupt( 
+    NvRmDeviceHandle hRmDevice,
+    NvRmModuleID ModuleID );
+
+/*
+ * Register the interrupt with the given interrupt handler.
+ *
+ * Assert encountered in debug mode if irq number is not valid.
+ *
+ * @see NvRmInterruptEnable()
+ *
+ * @param hRmDevice The RM device handle.
+ * @param IrqListSize size of the IrqList passed in for registering the irq
+ *    handlers for each irq number.
+ * @param pIrqList Array of IRQ numbers for which interupt handlers to be
+ * registerd.
+ * @param pIrqHandlerList array intrupt routine to be called when interrupt
+ * occures.
+ * @param context pointer to the registrer's context handle
+ * @param handle handle to the registered interrupts. This handle is used by for
+ * unregistering the interrupt.
+ * @param InterruptEnable If true, immediately enable interrupt.  Otherwise
+ *  enable interrupt only after calling NvRmInterruptEnable().
+ *
+ * @retval "NvError_IrqRegistrationFailed" if interupt is already registred.
+ * @retval "NvSuccess" if registration is successfull.
+ */
+NvError
+NvRmInterruptRegister(
+    NvRmDeviceHandle hRmDevice,
+    NvU32 IrqListSize,
+    const NvU32 *pIrqList,
+    const NvOsInterruptHandler *pIrqHandlerList,
+    void *context,
+    NvOsInterruptHandle *handle,
+    NvBool InterruptEnable);
+
+/**
+ * Un-registers the interrupt handler from the associated interrupt handle which
+ * is returned by the NvRmInterruptRegister API.
+ *
+ * @param handle Handle returned when the interrupt is registered.
+ */
+void
+NvRmInterruptUnregister(
+    NvRmDeviceHandle hRmDevice,
+    NvOsInterruptHandle handle);
+
+/**
+ * Enable the interrupt handler from the associated interrupt handle which
+ * is returned by the NvRmInterruptRegister API.
+ *
+ * @param handle Handle returned when the interrupt is registered.
+ * 
+ * @retval "NvError_BadParameter" if handle is not valid
+ * @retval "NvError_InsufficientMemory" if interupt enable failed.
+ * @retval "NvSuccess" if registration is successfull.
+ */
+NvError
+NvRmInterruptEnable(
+    NvRmDeviceHandle hRmDevice,
+    NvOsInterruptHandle handle);
+
+/**
+ *  Called by the interrupt callaback to re-enable the interrupt.
+ */
+
+void
+NvRmInterruptDone( NvOsInterruptHandle handle );
+
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif
diff --git a/arch/arm/mach-tegra/include/nvrm_keylist.h b/arch/arm/mach-tegra/include/nvrm_keylist.h
new file mode 100644
index 000000000000..350282791e8c
--- /dev/null
+++ b/arch/arm/mach-tegra/include/nvrm_keylist.h
@@ -0,0 +1,96 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_nvrm_keylist_H
+#define INCLUDED_nvrm_keylist_H
+
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+#include "nvrm_module.h"
+#include "nvrm_init.h"
+
+/** @file
+ * @brief <b>NVIDIA Driver Development Kit:
+ *     Resource Manager Key-List APIs</b>
+ *
+ * @b Description: This API, defines a simple means to set/get the state 
+ * of ODM-Defined Keys.
+ */
+
+#include "nvos.h"
+#include "nvodm_keylist_reserved.h"
+
+/**
+ * Searches the List of Keys present and returns
+ * the Value of the appropriate Key.
+ * 
+ * @param hRm Handle to the RM Device.
+ * @param KeyID ID of the key whose value is required.
+ * 
+ * @retval returns the value of the corresponding key. If the Key is not 
+ * present in the list, it returns 0.
+ */
+
+
+
+ NvU32 NvRmGetKeyValue( 
+    NvRmDeviceHandle hRm,
+    NvU32 KeyID );
+
+/**
+ * Searches the List of Keys Present and sets the value of the Key to the value 
+ * given. If the Key is not present, it adds the key to the list and sets the 
+ * value.
+ * 
+ * @param hRM Handle to the RM Device.
+ * @param KeyID ID of the key whose value is to be set.
+ * @param Value Value to be set for the corresponding key.
+ * 
+ * @retval NvSuccess Value has been successfully set.
+ * @retval NvError_InsufficientMemory Operation has failed while adding the 
+ * key to the existing list.
+ */
+
+ NvError NvRmSetKeyValuePair( 
+    NvRmDeviceHandle hRm,
+    NvU32 KeyID,
+    NvU32 Value );
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif
diff --git a/arch/arm/mach-tegra/include/nvrm_memctrl.h b/arch/arm/mach-tegra/include/nvrm_memctrl.h
new file mode 100644
index 000000000000..b760dd538c12
--- /dev/null
+++ b/arch/arm/mach-tegra/include/nvrm_memctrl.h
@@ -0,0 +1,189 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_nvrm_memctrl_H
+#define INCLUDED_nvrm_memctrl_H
+
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+#include "nvrm_module.h"
+#include "nvrm_init.h"
+
+#include "nvcommon.h"
+#include "nvassert.h"
+#include "nvos.h"
+
+/*
+ * @ingroup nvrm_memctrl
+ * @{
+ */
+
+/**
+ * NvRmDeviceHandle is an opaque handle to an RM device.
+ */
+
+/**
+ * Start collecting statistics for specified clients. (2 normal clients and 1 llc client)
+ *
+ * @param rm the RM handle is stored here.
+ * @param client_id_0 the ID of the first client
+ * @param client_id_1 the ID of the second client
+ * @param llc_client_id the ID of the llc client
+ *
+ */
+
+ void McStat_Start( 
+    NvRmDeviceHandle rm,
+    NvU32 client_id_0,
+    NvU32 client_id_1,
+    NvU32 llc_client_id );
+
+/**
+ * Stop the counter for collecting statistics for specified clinets
+ * @param rm the RM handle is stored here
+ * @param client_0_cycles pointer to the number of cycles of client_0
+ * @param client_1_cycles pointer to the number of cycles of client_1
+ * @param llc_client_cycles pointer to the number of cycles of llc client
+ * @param llc_client_clocks pointer to the llc client's clock
+ * @param mc_clocks pointer to the memory controller's clock
+ */
+
+ void McStat_Stop( 
+    NvRmDeviceHandle rm,
+    NvU32 * client_0_cycles,
+    NvU32 * client_1_cycles,
+    NvU32 * llc_client_cycles,
+    NvU32 * llc_client_clocks,
+    NvU32 * mc_clocks );
+
+/**
+ * Print out the collected memory control stat data
+ * @param client_id_0 the first client's ID
+ * @param client_0_cycles the number of cycles of client_0 from start to stop
+ * @param client_id_1 the second client's ID
+ * @param client_1_cycles the number of cycles of client_1 from start to stop
+ * @param llc_client_id the ID of llc client
+ * @param llc_client_clocks the clocks of llc client
+ * @param llc_client_cycles the number of cycles of llc client
+ * @param mc_clocks the memory controller's clock
+ */
+
+ void McStat_Report( 
+    NvU32 client_id_0,
+    NvU32 client_0_cycles,
+    NvU32 client_id_1,
+    NvU32 client_1_cycles,
+    NvU32 llc_client_id,
+    NvU32 llc_client_clocks,
+    NvU32 llc_client_cycles,
+    NvU32 mc_clocks );
+
+/**
+ * Read the data of specified module and bit field 
+ * @param modId the specified module ID
+ * @param start_index the start index of the required data
+ * @param length the length of the data
+ * @param value pointer to the variable that will store the data specified
+ *
+ * @retval NvSuccess Indicate the the data is read successfully
+ */
+
+ NvError ReadObsData( 
+    NvRmDeviceHandle rm,
+    NvRmModuleID modId,
+    NvU32 start_index,
+    NvU32 length,
+    NvU32 * value );
+
+/**
+ * Starts CPU performance monitors for the specified list of events
+ * (if monitors were already running they are restarted).
+ * 
+ * @param hRmDevice The RM device handle.
+ * @param pEventListSize Pointer to the event list size. On entry specifies
+ *  list size allocated by the client, on exit - actual number of event monitors
+ *  started. If entry size is 0, maximum number of monitored events is returned.
+ * @param pEventList Pointer to the list of events to be monitored. Ignored
+ *  if input list size is 0. Monitors run status is not affected in this case.
+ * 
+ * @note No event validation is performed. It is caller responsibility to pass
+ *  valid event codes. See ARM control coprocessor CP15 specification for the
+ *  list of event numbers and the respective event definitions.
+ * 
+ * @retval NvSuccess if monitoring start function completed successfully.
+ * @retval NvError_NotSupported if core performance monitoring is not supported.
+ */                               
+
+ NvError NvRmCorePerfMonStart( 
+    NvRmDeviceHandle hRmDevice,
+    NvU32 * pEventListSize,
+    NvU32 * pEventList );
+
+/**
+ * Stops CPU performance monitors and returns event counts.
+ * 
+ * @param hRmDevice The RM device handle.
+ * @param pCountListSize Pointer to the count list size. On entry specifies
+ *  list size allocated by the client, on exit - actual number of event counts
+ *  returned.
+ * @param pCountList Pointer to the list filled in by this function with event
+ *  counts since performance monitoring started. The order of returned counts
+ *  is the same as the order of events specified by NvRmCorePerfMonStart()
+ *  call. If input list size exceeds number of started event monitors the extra
+ *  counts are meaningless. If input list size is 0, this parameter is ignored,
+ *  and no event counts are returned.
+ * @param pTotalCycleCount Pointer to the total number of CPU clock cycles
+ *  since performance monitoring started.
+ * 
+ * @retval NvSuccess if monitoring results are retrieved successfully.
+ * @retval NvError_InvalidState if core performance monitoring has not been
+ *  started or monitor overflow has occurred.
+ * @retval NvError_NotSupported if core performance monitoring is not supported.
+ */                               
+
+ NvError NvRmCorePerfMonStop( 
+    NvRmDeviceHandle hRmDevice,
+    NvU32 * pCountListSize,
+    NvU32 * pCountList,
+    NvU32 * pTotalCycleCount );
+
+/** @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif
diff --git a/arch/arm/mach-tegra/include/nvrm_memmgr.h b/arch/arm/mach-tegra/include/nvrm_memmgr.h
new file mode 100644
index 000000000000..cc431c8763f7
--- /dev/null
+++ b/arch/arm/mach-tegra/include/nvrm_memmgr.h
@@ -0,0 +1,1013 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_nvrm_memmgr_H
+#define INCLUDED_nvrm_memmgr_H
+
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+#include "nvrm_init.h"
+
+#include "nvos.h"
+
+/**
+ * FAQ for commonly asked questions:
+ *
+ * Q) Why can NvRmMemMap fail?
+ * A) Some operating systems don't allow user mode applications to map arbitrary
+ *    memory regions, this is a huge security hole.  In other environments, such
+ *    as simulation, its just not even possible to get a direct pointer to 
+ *    the memory, because the simulation is in a different process.
+ *
+ * Q) What do I do if NvRmMemMap fails?
+ * A) Driver writers have two choices.  If the driver must have a mapping, for
+ *    example direct draw requires a pointer to the memory then the driver
+ *    will have to fail whatever operation it is doing and return an error.
+ *    The other choice is to fall back to using NvRmMemRead/Write functions
+ *    or NvRmMemRdxx/NvRmMemWrxx functions, which are guaranteed to succeed.
+ *
+ * Q) Why should I use NvRmMemMap instead of NvOsPhysicalMemMap?
+ * A) NvRmMemMap will do a lot of extra work in an OS like WinCE to create
+ *    a new mapping to the memory in your process space.  NvOsPhysicalMemMap
+ *    will is for mapping registers and other non-memory locations.  Using
+ *    this API on WindowsCE will cause WindowsCE to crash.
+ */
+
+
+
+/**
+ * UNRESOLVED ISSUES:
+ *
+ * 1. Should we have NvRmFill* APIs in addition to NvRmWrite*?  Say, if you just
+ *    want to clear a buffer to zero?
+ *
+ * 2. There is currently an issue with a memhandle that is shared across
+ *    processes.  If a MemHandle is created, and then duplicated into another
+ *    process uesing NvRmMemHandleGetId/NvRmMemHandleFromId it's not clear
+ *    what would happen if both processes tried to do an NvRmAlloc on a handle.
+ *    Perhaps make NvRmMemHandleGetId fail if the memory is not already
+ *    allocated.
+ *
+ * 3. It may be desirable to have more hMem query functions, for debuggability.
+ *    Part of the information associated with a memory buffer will live in
+ *    kernel space, and not be accesible efficiently from a user process.
+ *    Knowing which heap a buffer is in, or whether a buffer is pinned or
+ *    mapped could be useful.  Note that queries like this could involve race
+ *    conditions.  For example, memory could be moved from one heap to another
+ *    the moment after you ask what heap it's in.
+ */
+
+/**
+ * @defgroup nvrm_memmgr RM Memory Management Services
+ * 
+ * @ingroup nvddk_rm
+ * 
+ * The APIs in this header file are intended to be used for allocating and
+ * managing memory that needs to be accessed by HW devices.  It is not intended
+ * as a replacement for malloc() -- that functionality is provided by
+ * NvOsAlloc().  If only the CPU will ever access the memory, this API is
+ * probably extreme overkill for your needs.
+ *
+ * Memory allocated by NvRmMemAlloc() is intended to be asynchronously movable
+ * by the RM at any time.  Although discouraged, it is possible to permanently
+ * lock down ("pin") a memory buffer such that it can never be moved.  Normally,
+ * however, the intent is that you would only pin a buffer for short periods of
+ * time, on an as-needed basis.
+ *
+ * The first step to allocating memory is allocating a handle to refer to the
+ * allocation.  The handle has a separate lifetime from the underlying buffer.
+ * Some properties of the memory, such as its size in bytes, must be declared at
+ * handle allocation time and can never be changed.
+ *
+ * After successfully allocating a handle, you can specify properties of the
+ * memory buffer that are allowed to change over time.  (Currently no such
+ * properties exist, but in the past a "priority" attribute existed and may
+ * return some day in the future.)
+ *
+ * After specifying the properties of the memory buffer, it can be allocated.
+ * Some additional properties, such as the set of heaps that the memory is
+ * permitted to be allocated from, must be specified at allocation time and
+ * cannot be changed over the buffer's lifetime of the buffer.
+ *
+ * The contents of memory can be examined and modified using a variety of read
+ * and write APIs, such as NvRmMemRead and NvRmMemWrite.  However, in some
+ * cases, it is necessary for the driver or application to be able to directly
+ * read or write the buffer using a pointer.  In this case, the NvRmMemMap API
+ * can be used to obtain such a mapping into the current process's virtual
+ * address space.  It is important to note that the map operation is not
+ * guaranteed to succeed.  Drivers that use mappings are strongly encouraged
+ * to support two code paths: one for when the mapping succeeds, and one for
+ * when the mapping fails.  A memory buffer is allowed to be mapped multiple
+ * times, and the mappings are permitted to be of subregions of the buffer if
+ * desired.
+ *
+ * Before the memory buffer is used, it must be pinned.  While pinned, the
+ * buffer will not be moved, and its physical address can be safely queried.  A
+ * memory buffer can be pinned multiple times, and the pinning will be reference
+ * counted.  Assuming a valid handle and a successful allocation, pinning can
+ * never fail.
+ *
+ * After the memory buffer is done being used, it should be unpinned.  Unpinning
+ * never fails.  Any unpinned memory is free to be moved to any location which
+ * satisfies the current properties in the handle.  Drivers are strongly
+ * encouraged to unpin memory when they reach a quiescent state.  It is not
+ * unreasonable to have a goal that all memory buffers (with the possible
+ * exception of memory being continuously scanned out by the display) be
+ * unpinned when the system is idle.
+ *
+ * The NvRmMemPin API is only one of the two ways to pin a buffer.  In the case
+ * of modules that are programmed through command buffers submitted through
+ * host, it is not the preferred way to pin a buffer.  The "RELOC" facility in
+ * the stream API should be used instead if possible.  It is conceivable that in
+ * the distant future, the NvRmMemPin API might be removed.  In such a world,
+ * all graphics modules would be expected to use the RELOC API or a similar API,
+ * and all IO modules would be expected to use zero-copy DMA directly from the
+ * application buffer using NvOsPageLock.
+ *
+ * Some properties of a buffer can be changed at any point in its handle's
+ * lifetime.  Properties that are changed while a memory buffer is pinned will
+ * have no effect until the memory is unpinned.
+ *
+ * After you are done with a memory buffer, you must free its handle.  This
+ * automatically unpins the memory (if necessary) and frees the storage (if any)
+ * associated with it.
+ *
+ * @ingroup nvrm_memmgr
+ * @{
+ */
+
+
+/**
+ * A type-safe handle for a memory buffer.
+ */
+
+typedef struct NvRmMemRec *NvRmMemHandle;
+
+/**
+ * Define for invalid Physical address
+ */
+#define NV_RM_INVALID_PHYS_ADDRESS (0xffffffff)
+
+/**
+ * NvRm heap identifiers.
+ */
+
+typedef enum
+{
+
+    /**
+     * External (non-carveout, i.e., OS-managed) memory heap.
+     */
+    NvRmHeap_External = 1,
+
+    /**
+     * GART memory heap.  The GART heap is really an alias for the External
+     * heap.  All GART allocations will come out of the External heap, but
+     * additionally all such allocations will be mapped in the GART.  Calling
+     * NvRmMemGetAddress() on a buffer allocated in the GART heap will return
+     * the GART address, not the underlying memory address.
+     */
+    NvRmHeap_GART,
+
+    /**
+     * Carve-out memory heap within external memory.
+     */
+    NvRmHeap_ExternalCarveOut,
+
+    /**
+     * IRAM memory heap.
+     */
+    NvRmHeap_IRam,
+    NvRmHeap_Num,
+    NvRmHeap_Force32 = 0x7FFFFFFF
+} NvRmHeap;
+
+/**
+ * NvRm heap statistics. See NvRmMemGetStat() for further details.
+ */
+
+typedef enum
+{
+
+    /**
+     * Total number of bytes reserved for the carveout heap.
+     */
+    NvRmMemStat_TotalCarveout = 1,
+
+    /**
+     * Number of bytes used in the carveout heap.
+     */
+    NvRmMemStat_UsedCarveout,
+
+    /**
+     * Size of the largest free block in the carveout heap. 
+     * Size can be less than the difference of total and 
+     * used memory.
+     */
+    NvRmMemStat_LargestFreeCarveoutBlock,
+
+    /**
+     * Total number of bytes in the GART heap. 
+     */
+    NvRmMemStat_TotalGart,
+
+    /**
+     * Number of bytes reserved from the GART heap.
+     */
+    NvRmMemStat_UsedGart,
+
+    /**
+     * Size of the largest free block in GART heap. Size can be 
+     * less than the difference of total and used memory.
+     */
+    NvRmMemStat_LargestFreeGartBlock,
+    NvRmMemStat_Num,
+    NvRmMemStat_Force32 = 0x7FFFFFFF
+} NvRmMemStat;
+
+/**
+ * Allocates a memory handle that can be used to specify a memory allocation
+ * request and manipulate the resulting storage.
+ *
+ * @see NvRmMemHandleFree()
+ *
+ * @param hDevice An RM device handle.
+ * @param phMem A pointer to an opaque handle that will be filled in with the
+ *     new memory handle.
+ * @param Size Specifies the requested size of the memory buffer in bytes.
+ *
+ * @retval NvSuccess Indicates the memory handle was successfully allocated.
+ * @retval NvError_InsufficientMemory Insufficient system memory exists to
+ *     allocate the memory handle.
+ */
+
+ NvError NvRmMemHandleCreate( 
+    NvRmDeviceHandle hDevice,
+    NvRmMemHandle * phMem,
+    NvU32 Size );
+
+/**
+ * Looks up a pre-existing memory handle whose allocation was preserved through
+ * the boot process.
+ *
+ * Looking up a memory handle is a one-time event.  Once a preserved handle
+ * has been successfully looked up, it may not be looked up again.  Memory
+ * handles created with this mechanism behave identically to memory handles
+ * created through NvRmMemHandleCreate, including freeing the allocation with
+ * NvRmMemHandleFree.
+ *
+ * @param hDevice An RM device handle.
+ * @param Key The key value that was returned by the earlier call to
+ *    @see NvRmMemHandlePreserveHandle.
+ * @param phMem A pointer to an opaque handle that will be filled in with the
+ *    queried memory handle, if a preserved handle matching the key is found.
+ *
+ * @retval NvSuccess Indicates that the key was found and the memory handle
+ *    was successfully created.
+ * @retval NvError_InsufficientMemory Insufficient system memory was available
+ *    to perform the operation, or if no memory handle exists for the specified
+ *    Key.
+ */
+
+ NvError NvRmMemHandleClaimPreservedHandle( 
+    NvRmDeviceHandle hDevice,
+    NvU32 Key,
+    NvRmMemHandle * phMem );
+
+/**
+ * Adds a memory handle to the set of memory handles which will be preserved
+ * between the current OS context and a subsequent OS context.
+ *
+ * @param hMem The handle which will be marked for preservation
+ * @param Key  A key which can be used to claim the memory handle in a
+ *    different OS context.
+ *
+ * @retval NvSuccess Indicates that the memory handle will be preserved
+ * @retval NvError_InsufficientMemory Insufficient system or BootArg memory
+ *    was avaialable to mark the memory handle as preserved.
+ */
+
+ NvError NvRmMemHandlePreserveHandle( 
+    NvRmMemHandle hMem,
+    NvU32 * Key );
+
+/**
+ * Frees a memory handle obtained from NvRmMemHandleCreate(),
+ * or NvRmMemHandleFromId().
+ *
+ * Fully disposing of a handle requires calling this API one time, plus one
+ * time for each NvRmMemHandleFromId().  When the internal reference count of
+ * the handle reaches zero, all resources for the handle will be released, even
+ * if the memory is marked as pinned and/or mapped.  It is the caller's
+ * responsibility to ensure mappings are released before calling this API.
+ *
+ * When the last handle is closed, the associated storage will be implicitly
+ * unpinned and freed.
+ *
+ * This API cannot fail.
+ *
+ * @see NvRmMemHandleCreate()
+ * @see NvRmMemHandleFromId()
+ *
+ * @param hMem A previously allocated memory handle.  If hMem is NULL, this API
+ *     has no effect.
+ */
+
+ void NvRmMemHandleFree( 
+    NvRmMemHandle hMem );
+
+/**
+ * Allocate storage for a memory handle.  The storage must satisfy:
+ *  1) all specified properties in the hMem handle
+ *  2) the alignment parameters
+ *
+ * Memory allocated by this API is intended to be used by modules which
+ * control hardware devices such as media accelerators or I/O controllers.
+ *
+ * The memory will initially be in an unpinned state.
+ *
+ * Assert encountered in debug mode if alignment was not a power of two, 
+ *     or coherency is not one of NvOsMemAttribute_Uncached,
+ *     NvOsMemAttribute_WriteBack or NvOsMemAttribute_WriteCombined.
+ *
+ * @see NvRmMemPin()
+ *
+ * @param hMem The memory handle to allocate storage for.
+ * @param Heaps[] An array of heap enumerants that indicate which heaps the
+ *     memory buffer is allowed to live in.  When a memory buffer is requested
+ *     to be allocated or needs to be moved, Heaps[0] will be the first choice
+ *     to allocate from or move to, Heaps[1] will be the second choice, and so
+ *     on until the end of the array.
+ * @params NumHeaps The size of the Heaps[] array.  If NumHeaps is zero, then
+ *     Heaps must also be NULL, and the RM will select a default list of heaps
+ *     on the client's behalf.
+ * @param Alignment Specifies the requested alignment of the buffer, measured in
+ *     bytes.  Must be a power of two.
+ * @param Coherency Specifies the cache coherency mode desired if the memory
+ *     is ever mapped.
+ *
+ * @retval NvSuccess Indicates the memory buffer was successfully
+ *     allocated.
+ * @retval NvError_InsufficientMemory Insufficient memory exists that
+ *     satisfies the specified memory handle properties and API parameters.
+ * @retval NvError_AlreadyAllocated hMem already has a memory buffer
+ *     allocated.
+ */
+
+ NvError NvRmMemAlloc( 
+    NvRmMemHandle hMem,
+    const NvRmHeap * Heaps,
+    NvU32 NumHeaps,
+    NvU32 Alignment,
+    NvOsMemAttribute Coherency );
+
+/**
+ * Attempts to lock down a piece of previously allocated memory.  By default
+ * memory is "movable" until it is pinned -- the RM is free to relocate it from
+ * one address or heap to another at any time for any reason (say, to defragment
+ * a heap).  This function can be called to prevent the RM from moving the
+ * memory.
+ *
+ * While a memory buffer is pinned, its physical address can safely be queried
+ * with NvRmMemGetAddress().
+ *
+ * This API always succeeds.
+ *
+ * Pins are reference counted, so the memory will remain pinned until all Pin
+ * calls have had a matching Unpin call.
+ *
+ * Pinning and mapping a memory buffer are completely orthogonal.  It is not
+ * necessary to pin a buffer before mapping it.  Mapping a buffer does not imply
+ * that it is pinned.
+ *
+ * @see NvRmMemGetAddress()
+ * @see NvRmMemUnpin()
+ *
+ * @param hMem A memory handle returned from NvRmMemHandleCreate,
+ *              NvRmMemHandleFromId.
+ *
+ * @returns The physical address of the first byte in the specified memory
+ *     handle's storage.  If the memory is mapped through the GART, the
+ *     GART address will be returned, not the address of the underlying memory.
+ */
+
+ NvU32 NvRmMemPin( 
+    NvRmMemHandle hMem );
+
+ /**
+  * A multiple handle version of NvRmMemPin to reduce kernel trap overhead.
+  * 
+  * @see NvRmMemPin
+  *
+  * @param hMems An array of memory handles to pin
+  * @param Addrs An arary of address (the result of the pin)
+  * @param Count The number of handles and addresses
+  */
+
+ void NvRmMemPinMult( 
+    NvRmMemHandle * hMems,
+    NvU32 * Addrs,
+    NvU32 Count );
+
+/**
+ * Retrieves a physical address for an hMem handle and an offset into that
+ * handle's memory buffer.
+ *
+ * If the memory referred to by hMem is not pinned, the return value is
+ * undefined, and an assert will fire in a debug build.
+ *
+ * @see NvRmMemPin()
+ *
+ * @param hMem A memory handle returned from NvRmMemHandleCreate/FromId.
+ * @param Offset The offset into the memory buffer for which the
+ *     address is desired.
+ *
+ * @returns The physical address of the specified byte within the specified
+ *     memory handle's storage.  If the memory is mapped through the GART, the
+ *     GART address will be returned, not the address of the underlying memory.
+ */
+
+ NvU32 NvRmMemGetAddress( 
+    NvRmMemHandle hMem,
+    NvU32 Offset );
+
+/**
+ * Unpins a memory buffer so that it is once again free to be moved.  Pins are
+ * reference counted, so the memory will not become movable until all Pin calls
+ * have had a matching Unpin call.
+ *
+ * If the pin count is already zero when this API is called, the behavior is
+ * undefined, and an assert will fire in a debug build.
+ *
+ * This API cannot fail.
+ *
+ * @see NvRmMemPin()
+ *
+ * @param hMem A memory handle returned from NvRmMemHandleCreate/FromId.
+ *     If hMem is NULL, this API will do nothing.
+ */
+
+ void NvRmMemUnpin( 
+    NvRmMemHandle hMem );
+
+ /**
+  * A multiple handle version of NvRmMemUnpin to reduce kernel trap overhead.
+  * 
+  * @see NvRmMemPin
+  *
+  * @param hMems An array of memory handles to unpin
+  * @param Count The number of handles and addresses
+  */
+
+ void NvRmMemUnpinMult( 
+    NvRmMemHandle * hMems,
+    NvU32 Count );
+
+/**
+ * Attempts to map a memory buffer into the process's virtual address space.
+ *
+ * It is recommended that mappings be short-lived as some systems have a limited
+ * number of concurrent mappings that can be supported, or because virtual
+ * address space may be scarce.
+ *
+ * It is legal to have multiple concurrent mappings of a single memory buffer.
+ *
+ * Pinning and mapping a memory buffer are completely orthogonal.  It is not
+ * necessary to pin a buffer before mapping it.  Mapping a buffer does not imply
+ * that it is pinned.
+ *
+ * There is no guarantee that the mapping will succeed.  For example, on some
+ * operating systems, the OS's security mechanisms make it impossible for
+ * untrusted applications to map certain types of memory.  A mapping might also
+ * fail due to exhaustion of memory or virtual address space.  Therefore, you
+ * must implement code paths that can handle mapping failures.  For example, if
+ * the mapping fails, you may want to fall back to using NvRmMemRead() and
+ * NvRmMemWrite().  Alternatively, you may want to consider avoiding the use of
+ * this API altogether, unless there is a compelling reason why you need
+ * mappings.
+ *
+ * @see NvRmMemUnmap()
+ *
+ * @param hMem A memory handle returned from NvRmMemHandleCreate/FromId.
+ * @param Offset Byte offset within the memory buffer to start the map at.
+ * @param Size Size in bytes of mapping requested.  Must be greater than 0.
+ * @param Flags Special flags -- use NVOS_MEM_* (see nvos.h for details)
+ * @param pVirtAddr If the mapping is successful, provides a virtual
+ *     address through which the memory buffer can be accessed.
+ *
+ * @retval NvSuccess Indicates that the memory was successfully mapped.
+ * @retval NvError_InsufficientMemory The mapping was unsuccessful.
+ *     This can occur if it is impossible to map the memory, or if offset+size
+ *     is greater than the size of the buffer referred to by hMem.
+ * @retval NvError_NotSupported Mapping not allowed (e.g., for GART heap)
+ */
+
+NvError
+NvRmMemMap(
+    NvRmMemHandle  hMem,
+    NvU32          Offset,
+    NvU32          Size,
+    NvU32          Flags,
+    void          **pVirtAddr);
+
+/**
+ * Unmaps a memory buffer from the process's virtual address space.  This API
+ * cannot fail.
+ *
+ * If hMem is NULL, this API will do nothing.
+ * If pVirtAddr is NULL, this API will do nothing.
+ *
+ * @see NvRmMemMap()
+ *
+ * @param hMem A memory handle returned from NvRmMemHandleCreate/FromId.
+ * @param pVirtAddr The virtual address returned by a previous call to
+ *     NvRmMemMap with hMem.
+ * @param Size The size in bytes of the mapped region.  Must be the same as the
+ *     Size value originally passed to NvRmMemMap.
+ */
+
+void NvRmMemUnmap(NvRmMemHandle hMem, void *pVirtAddr, NvU32 Size);
+ 
+/**
+ * Reads 8 bits of data from a buffer.  This API cannot fail.
+ *
+ * If hMem refers to an unallocated memory buffer, this function's behavior is
+ * undefined and an assert will trigger in a debug build. 
+ * 
+ * @param hMem A memory handle returned from NvRmMemHandleCreate/FromId.
+ * @param Offset Byte offset relative to the base of hMem.
+ *     May be arbitrarily aligned -- need not be a multiple of 2 or 4.
+ *
+ * @returns The value read from the memory location.
+ */
+
+NvU8 NvRmMemRd08(NvRmMemHandle hMem, NvU32 Offset);
+
+/**
+ * Reads 16 bits of data from a buffer.  This API cannot fail.
+ *
+ * If hMem refers to an unallocated memory buffer, this function's behavior is
+ * undefined and an assert will trigger in a debug build. 
+ * 
+ * @param hMem A memory handle returned from NvRmMemHandleCreate/FromId.
+ * @param Offset Byte offset relative to the base of hMem.
+ *     Must be a multiple of 2.
+ *
+ * @returns The value read from the memory location.
+ */
+
+NvU16 NvRmMemRd16(NvRmMemHandle hMem, NvU32 Offset);
+
+/**
+ * Reads 32 bits of data from a buffer.  This API cannot fail.
+ *
+ * If hMem refers to an unallocated memory buffer, this function's behavior is
+ * undefined and an assert will trigger in a debug build. 
+ * 
+ * @param hMem A memory handle returned from NvRmMemHandleCreate/FromId.
+ * @param Offset Byte offset relative to the base of hMem.
+ *     Must be a multiple of 4.
+ *
+ * @returns The value read from the memory location.
+ */
+
+NvU32 NvRmMemRd32(NvRmMemHandle hMem, NvU32 Offset);
+
+/**
+ * Writes 8 bits of data to a buffer.  This API cannot fail.
+ *
+ * If hMem refers to an unallocated memory buffer, this function's behavior is
+ * undefined and an assert will trigger in a debug build. 
+ * 
+ * @param hMem A memory handle returned from NvRmMemHandleCreate/FromId.
+ * @param Offset Byte offset relative to the base of hMem.
+ *     May be arbitrarily aligned -- need not be a multiple of 2 or 4.
+ * @param Data The data to write to the memory location.
+ */
+
+void NvRmMemWr08(NvRmMemHandle hMem, NvU32 Offset, NvU8 Data);
+
+/**
+ * Writes 16 bits of data to a buffer.  This API cannot fail.
+ *
+ * If hMem refers to an unallocated memory buffer, this function's behavior is
+ * undefined and an assert will trigger in a debug build. 
+ *
+ * @param hMem A memory handle returned from NvRmMemHandleCreate/FromId.
+ * @param Offset Byte offset relative to the base of hMem.
+ *     Must be a multiple of 2.
+ * @param Data The data to write to the memory location.
+ */
+
+void NvRmMemWr16(NvRmMemHandle hMem, NvU32 Offset, NvU16 Data);
+
+/**
+ * Writes 32 bits of data to a buffer.  This API cannot fail.
+ *
+ * If hMem refers to an unallocated memory buffer, this function's behavior is
+ * undefined and an assert will trigger in a debug build. 
+ *
+ * @param hMem A memory handle returned from NvRmMemHandleCreate/FromId.
+ * @param Offset Byte offset relative to the base of hMem.
+ *     Must be a multiple of 4.
+ * @param Data The data to write to the memory location.
+ */
+
+void NvRmMemWr32(NvRmMemHandle hMem, NvU32 Offset, NvU32 Data);
+
+/**
+ * Reads a block of data from a buffer.  This API cannot fail.
+ *
+ * If hMem refers to an unallocated memory buffer, this function's behavior is
+ * undefined and an assert will trigger in a debug build. 
+ *
+ * @param hMem A memory handle returned from NvRmMemHandleCreate/FromId.
+ * @param Offset Byte offset relative to the base of hMem.
+ *     May be arbitrarily aligned -- need not be a multiple of 2 or 4.
+ * @param pDst The buffer where the data should be placed.
+ *     May be arbitrarily aligned -- need not be located at a word boundary.
+ * @param Size The number of bytes of data to be read.
+ *     May be arbitrarily sized -- need not be a multiple of 2 or 4.
+ */
+void NvRmMemRead(NvRmMemHandle hMem, NvU32 Offset, void *pDst, NvU32 Size);
+
+/**
+ * Writes a block of data to a buffer.  This API cannot fail.
+ *
+ * If hMem refers to an unallocated memory buffer, this function's behavior is
+ * undefined and an assert will trigger in a debug build. 
+ *
+ * @param hMem A memory handle returned from NvRmMemHandleCreate/FromId.
+ * @param Offset Byte offset relative to the base of hMem.
+ *     May be arbitrarily aligned -- need not be a multiple of 2 or 4.
+ * @param pSrc The buffer to obtain the data from.
+ *     May be arbitrarily aligned -- need not be located at a word boundary.
+ * @param Size The number of bytes of data to be written.
+ *     May be arbitrarily sized -- need not be a multiple of 2 or 4.
+ */
+void NvRmMemWrite(
+    NvRmMemHandle hMem,
+    NvU32 Offset,
+    const void *pSrc,
+    NvU32 Size);
+
+/**
+ * Reads a strided series of blocks of data from a buffer.  This API cannot
+ * fail.
+ *
+ * The total number of bytes copied is Count*ElementSize.
+ *
+ * If hMem refers to an unallocated memory buffer, this function's behavior is
+ * undefined and an assert will trigger in a debug build. 
+ *
+ * @param hMem A memory handle returned from NvRmMemHandleCreate.
+ * @param Offset Byte offset relative to the base of hMem.
+ *     May be arbitrarily aligned -- need not be a multiple of 2 or 4.
+ * @param SrcStride The number of bytes separating each source element.
+ *     May be arbitrarily aligned -- need not be a multiple of 2 or 4.
+ * @param pDst The buffer where the data should be placed.
+ *     May be arbitrarily aligned -- need not be located at a word boundary.
+ * @param DstStride The number of bytes separating each destination element.
+ *     May be arbitrarily aligned -- need not be a multiple of 2 or 4.
+ * @param ElementSize The number of bytes in each element.
+ *     May be arbitrarily sized -- need not be a multiple of 2 or 4.
+ * @param Count The number of destination elements.
+ */
+void NvRmMemReadStrided(
+    NvRmMemHandle hMem,
+    NvU32 Offset,
+    NvU32 SrcStride,
+    void *pDst,
+    NvU32 DstStride,
+    NvU32 ElementSize,
+    NvU32 Count);
+
+/**
+ * Writes a strided series of blocks of data to a buffer.  This API cannot
+ * fail.
+ *
+ * The total number of bytes copied is Count*ElementSize.
+ *
+ * If hMem refers to an unallocated memory buffer, this function's behavior is
+ * undefined and an assert will trigger in a debug build. 
+ *
+ * @param hMem A memory handle returned from NvRmMemHandleCreate.
+ * @param Offset Byte offset relative to the base of hMem.
+ *     May be arbitrarily aligned -- need not be a multiple of 2 or 4.
+ * @param DstStride The number of bytes separating each destination element.
+ *     May be arbitrarily aligned -- need not be a multiple of 2 or 4.
+ * @param pSrc The buffer to obtain the data from.
+ *     May be arbitrarily aligned -- need not be located at a word boundary.
+ * @param SrcStride The number of bytes separating each source element.
+ *     May be arbitrarily aligned -- need not be a multiple of 2 or 4.
+ * @param ElementSize The number of bytes in each element.
+ *     May be arbitrarily sized -- need not be a multiple of 2 or 4.
+ * @param Count The number of source elements.
+ */
+void NvRmMemWriteStrided(
+    NvRmMemHandle hMem,
+    NvU32 Offset,
+    NvU32 DstStride,
+    const void *pSrc,
+    NvU32 SrcStride,
+    NvU32 ElementSize,
+    NvU32 Count);
+
+/**
+ * Moves (copies) a block of data to a different (or the same) hMem.  This
+ * API cannot fail.  Overlapping copies are supported.
+ * 
+ * NOTE: While easy to use, this is NOT the fastest way to copy memory.  Using
+ * the 2D engine to perform a blit can be much faster than this function.
+ *
+ * If hDstMem or hSrcMem refers to an unallocated memory buffer, this function's
+ * behavior is undefined and an assert will trigger in a debug build. 
+ *
+ * @param hDstMem A memory handle returned from NvRmMemHandleCreate/FromId.
+ * @param DstOffset Byte offset relative to the base of hMem.
+ *     May be arbitrarily aligned -- need not be a multiple of 2 or 4.
+ * @param hSrcMem A memory handle returned from NvRmMemHandleCreate/FromId.
+ * @param SrcOffset Byte offset relative to the base of hMem.
+ *     May be arbitrarily aligned -- need not be a multiple of 2 or 4.
+ * @param Size The number of bytes of data to be copied from hSrcMem to hDstMem.
+ *     May be arbitrarily sized -- need not be a multiple of 2 or 4.
+ */
+
+ void NvRmMemMove( 
+    NvRmMemHandle hDstMem,
+    NvU32 DstOffset,
+    NvRmMemHandle hSrcMem,
+    NvU32 SrcOffset,
+    NvU32 Size );
+
+/**
+ * Optionally writes back and/or invalidates a range of the memory from the
+ * data cache, if applicable.  Does nothing for memory that was not allocated
+ * as cached. Memory must be mapped into the calling process.
+ *
+ * @param hMem A memory handle returned from NvRmMemHandleCreate/FromId.
+ * @param pMapping Starting address (must be within the mapped region of the
+       hMem) to clean
+ * @param Size The number of bytes of data to be written.
+ *     May be arbitrarily sized -- need not be a multiple of 2 or 4.
+ */
+
+void NvRmMemCacheMaint(
+    NvRmMemHandle hMem,
+    void         *pMapping,
+    NvU32         Size,
+    NvBool        WriteBack,
+    NvBool        Invalidate);
+
+/**
+ * Get the size of the buffer associated with a memory handle.
+ *
+ * @param hMem A memory handle returned from NvRmMemHandleCreate/FromId.
+ *
+ * @returns Size in bytes of memory allocated for this handle.
+ */
+
+ NvU32 NvRmMemGetSize( 
+    NvRmMemHandle hMem );
+
+/**
+ * Get the alignment of the buffer associated with a memory handle.
+ *
+ * @param hMem A memory handle returned from NvRmMemHandleCreate/FromId.
+ *
+ * @returns Alignment in bytes of memory allocated for this handle.
+ */
+
+ NvU32 NvRmMemGetAlignment( 
+    NvRmMemHandle hMem );
+
+/**
+ * Queries the maximum cache line size (in bytes) for all of the caches
+ * L1 and L2 in the system
+ *
+ * @returns The largest cache line size of the system
+ */
+
+ NvU32 NvRmMemGetCacheLineSize( 
+    void  );
+
+/**
+ * Queries for the heap type associated with a given memory handle.  Also
+ * returns base physical address for the buffer, if the type is carveout or
+ * GART.  For External type, this parameter does not make sense.
+ * 
+ * @param hMem A memory handle returned from NvRmMemHandleCreate/FromId.
+ * @param BasePhysAddr Output parameter receives the physical address of the
+ *           buffer.
+ *
+ * @returns The heap type allocated for this memory handle.
+ */
+
+ NvRmHeap NvRmMemGetHeapType( 
+    NvRmMemHandle hMem,
+    NvU32 * BasePhysAddr );
+
+/**
+ * Dynamically allocates memory, on CPU this will result in a call to 
+ * NvOsAlloc and on AVP, memAPI's are used to allocate memory.
+ * @param size The memory size to be allocated.
+ * @returns Pointer to the allocated buffer.
+ */
+void* NvRmHostAlloc(size_t Size);
+
+/**
+ * Frees a dynamic memory allocation, previously allocated using NvRmHostAlloc.
+ * 
+ * @param ptr The pointer to buffer which need to be deallocated.
+ */
+void NvRmHostFree(void* ptr);
+
+/** 
+ * This is generally not a publically available function.  It is only available
+ * on WinCE to the nvrm device driver.  Attempting to use this function will
+ * result in a linker error, you should use NvRmMemMap instead, which will do
+ * the "right" thing for all platforms.
+ *
+ * Under WinCE NvRmMemMap has a custom marshaller, the custom marshaller will 
+ * do the following:
+ *  - Allocate virtual space
+ *  - ioctl to the nvrm driver
+ *    - nvrm driver will create a mapping from the allocated buffer to
+ *      the newly allocated virtual space.
+ */
+NvError NvRmMemMapIntoCallerPtr(
+    NvRmMemHandle hMem,
+    void  *pCallerPtr,
+    NvU32 Offset,
+    NvU32 Size);
+
+/**
+ * Create a unique identifier which can be used from any process/processor
+ * to generate a new memory handle.  This can be used to share a memory handle
+ * between processes, or from AVP and CPU.  
+ *
+ *  Typical usage would be
+ *    GetId
+ *    Pass Id to client process/procssor
+ *    Client calls:  NvRmMemHandleFromId
+ *
+ *  See Also NvRmMemHandleFromId
+ *
+ * NOTE: Getting an id _does not_ increment the reference count of the
+ *       memory handle.  You must be sure that whichever process/processor
+ *       that is passed an Id calls @NvRmMemHandleFromId@ before you free
+ *       a handle.
+ *
+ * @param hMem The memory handle to retrieve the id for.
+ * @returns a unique id that identifies the memory handle.
+ */
+
+ NvU32 NvRmMemGetId( 
+    NvRmMemHandle hMem );
+
+/**
+ * Create a new memory handle, which refers to the memory handle identified
+ * by @id@.  This function will increment the reference count on the handle.
+ *
+ *  See Also NvRmMemGetId
+ *
+ * @param id value that refers to a memory handle, returned from NvRmMemGetId
+ * @param hMem The newly created memory handle
+ * @returns NvSuccess if a unique id is created.
+ */
+
+ NvError NvRmMemHandleFromId( 
+    NvU32 id,
+    NvRmMemHandle * hMem );
+
+/**
+ * Get a memory statistics value. 
+ *
+ * Querying values may have an effect on  system performance and may include 
+ * processing, like heap traversal.
+ *
+ * @param Stat NvRmMemStat value that chooses the value to return.
+ * @param Result Result, if the call was successful. Otherwise value 
+ *      is not touched.
+ * @returns NvSuccess on success, NvError_BadParameter if Stat is 
+ *      not a valid value, NvError_NotSupported if the Stat is 
+ *      not available for some reason, or
+ *      NvError_InsufficientMemory.
+ */
+
+ NvError NvRmMemGetStat( 
+    NvRmMemStat Stat,
+    NvS32 * Result );
+
+#define NVRM_MEM_CHECK_ID  0
+#define NVRM_MEM_TRACE     0
+#if     NVRM_MEM_TRACE
+#ifndef NV_IDL_IS_STUB
+#ifndef NV_IDL_IS_DISPATCH
+#define NvRmMemHandleCreate(d,m,s) \
+        NvRmMemHandleCreateTrace(d,m,s,__FILE__,__LINE__)
+#define NvRmMemHandleFree(m) \
+        NvRmMemHandleFreeTrace(m,__FILE__,__LINE__)
+#define NvRmMemGetId(m) \
+        NvRmMemGetIdTrace(m,__FILE__,__LINE__)
+#define NvRmMemHandleFromId(i,m) \
+        NvRmMemHandleFromIdTrace(i,m,__FILE__,__LINE__)
+
+static NV_INLINE NvError NvRmMemHandleCreateTrace( 
+    NvRmDeviceHandle hDevice,
+    NvRmMemHandle * phMem,
+    NvU32 Size,
+    const char *file,
+    NvU32 line)
+{
+    NvError err;
+    err = (NvRmMemHandleCreate)(hDevice, phMem, Size);
+    NvOsDebugPrintf("RMMEMTRACE: Create %08x at %s:%d %s\n",
+        (int)*phMem,
+        file,
+        line,
+        err?"FAILED":"");
+    return err;
+}
+
+static NV_INLINE void NvRmMemHandleFreeTrace( 
+    NvRmMemHandle hMem,
+    const char *file,
+    NvU32 line)
+{
+    NvOsDebugPrintf("RMMEMTRACE: Free   %08x at %s:%d\n",
+        (int)hMem,
+        file,
+        line);
+    (NvRmMemHandleFree)(hMem);
+}
+
+static NV_INLINE NvU32 NvRmMemGetIdTrace( 
+    NvRmMemHandle hMem,
+    const char *file,
+    NvU32 line)
+{
+    NvOsDebugPrintf("RMMEMTRACE: GetId  %08x at %s:%d\n",
+        (int)hMem,
+        file,
+        line);
+    return (NvRmMemGetId)(hMem);
+}
+
+static NV_INLINE NvError NvRmMemHandleFromIdTrace( 
+    NvU32 id,
+    NvRmMemHandle * hMem,
+    const char *file,
+    NvU32 line)
+{
+    NvOsDebugPrintf("RMMEMTRACE: FromId %08x at %s:%d\n",
+        id,
+        file,
+        line);
+    return (NvRmMemHandleFromId)(id,hMem);
+}
+
+#endif // NV_IDL_IS_DISPATCH
+#endif // NV_IDL_IS_STUB
+#endif // NVRM_MEM_TRACE
+
+/** @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif
diff --git a/arch/arm/mach-tegra/include/nvrm_minikernel.h b/arch/arm/mach-tegra/include/nvrm_minikernel.h
new file mode 100644
index 000000000000..79b198b3f7d3
--- /dev/null
+++ b/arch/arm/mach-tegra/include/nvrm_minikernel.h
@@ -0,0 +1,57 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_NVRM_MINIKERNEL_H
+#define INCLUDED_NVRM_MINIKERNEL_H
+
+#include "nvrm_init.h"
+
+/**
+ * Called by the secure OS code to initialize the Rm. Usage and
+ * implementation of this API is platform specific.
+ *
+ * This APIs should not be called by the non secure clients of the Rm.
+ *
+ * This APIs is guaranteed to succeed on the supported platforms.
+ *
+ * @param pHandle the RM handle is stored here.
+ */
+void NvRmBasicInit( NvRmDeviceHandle *pHandle );
+
+/**
+ * Closes the Resource Manager for secure os.
+ *
+ * @param hDevice The RM handle.  If hDevice is NULL, this API has no effect.
+ */
+void NvRmBasicClose( NvRmDeviceHandle hDevice );
+
+#endif // INCLUDED_NVRM_MINIKERNEL_H
diff --git a/arch/arm/mach-tegra/include/nvrm_module.h b/arch/arm/mach-tegra/include/nvrm_module.h
new file mode 100644
index 000000000000..7fed6a90268e
--- /dev/null
+++ b/arch/arm/mach-tegra/include/nvrm_module.h
@@ -0,0 +1,745 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_nvrm_module_H
+#define INCLUDED_nvrm_module_H
+
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+#include "nvrm_init.h"
+
+#include "nvrm_drf.h"
+
+/**
+ * SOC hardware controller class identifiers.
+ */
+
+typedef enum
+{
+
+    /// Specifies an invalid module ID.
+        NvRmModuleID_Invalid = 0,
+
+    /// Specifies the application processor.
+        NvRmModuleID_Cpu,
+
+    /// Specifies the Audio Video Processor
+        NvRmModuleID_Avp,
+
+    /// Specifies the Vector Co Processor
+        NvRmModuleID_Vcp,
+
+    /// Specifies the display controller.
+        NvRmModuleID_Display,
+
+    /// Specifies the IDE controller.
+        NvRmModuleID_Ide,
+
+    /// Graphics Host
+        NvRmModuleID_GraphicsHost,
+
+    /// Specifies 2D graphics controller
+        NvRmModuleID_2D,
+
+    /// Specifies 3D graphics controller
+        NvRmModuleID_3D,
+
+    /// Specifies VG graphics controller
+        NvRmModuleID_VG,
+
+    /// NV epp (encoder pre-processor)
+        NvRmModuleID_Epp,
+
+    /// NV isp (image signal processor)
+        NvRmModuleID_Isp,
+
+    /// NV vi (video input)
+        NvRmModuleID_Vi,
+
+    /// Specifies USB2 OTG controller
+        NvRmModuleID_Usb2Otg,
+
+    /// Specifies the I2S controller.
+        NvRmModuleID_I2s,
+
+    /// Specifies the Pulse Width Modulator controller.
+        NvRmModuleID_Pwm,
+
+    /// Specifies the Three Wire controller.
+        NvRmModuleID_Twc,
+
+    /// HSMMC controller
+        NvRmModuleID_Hsmmc,
+
+    /// Specifies SDIO controller
+        NvRmModuleID_Sdio,
+
+    /// Specifies the NAND controller.
+        NvRmModuleID_Nand,
+
+    /// Specifies the I2C controller.
+        NvRmModuleID_I2c,
+
+    /// Specifies the Sony Phillips Digital Interface Format controller.
+        NvRmModuleID_Spdif,
+
+    /// Specifies the %UART controller.
+        NvRmModuleID_Uart,
+
+    /// Specifies the timer controller.
+        NvRmModuleID_Timer,
+
+    /// Specifies the timer controller microsecond counter.
+        NvRmModuleID_TimerUs,
+
+    /// Real time clock controller.
+        NvRmModuleID_Rtc,
+
+    /// Specifies the Audio Codec 97 controller.
+        NvRmModuleID_Ac97,
+
+    /// Specifies Audio Bit Stream Engine
+        NvRmModuleID_BseA,
+
+    /// Specifies Video decoder
+        NvRmModuleID_Vde,
+
+    /// Specifies Video encoder (Motion Picture Encoder)
+        NvRmModuleID_Mpe,
+
+    /// Specifies Camera Serial Interface
+        NvRmModuleID_Csi,
+
+    /// Specifies High-Bandwidth Digital Content Protection interface
+        NvRmModuleID_Hdcp,
+
+    /// Specifies High definition Multimedia Interface
+        NvRmModuleID_Hdmi,
+
+    /// Specifies MIPI baseband controller
+        NvRmModuleID_Mipi,
+
+    /// Specifies TV out controller
+        NvRmModuleID_Tvo,
+
+    /// Specifies Serial Display
+        NvRmModuleID_Dsi,
+
+    /// Specifies Dynamic Voltage Controller
+        NvRmModuleID_Dvc,
+
+    /// Specifies the eXtended I/O controller.
+        NvRmModuleID_Xio,
+
+    /// SPI controller
+        NvRmModuleID_Spi,
+
+    /// Specifies SLink controller
+        NvRmModuleID_Slink,
+
+    /// Specifies FUSE controller
+        NvRmModuleID_Fuse,
+
+    /// Specifies KFUSE controller
+        NvRmModuleID_KFuse,
+
+    /// Specifies EthernetMIO controller
+        NvRmModuleID_Mio,
+
+    /// Specifies keyboard controller
+        NvRmModuleID_Kbc,
+
+    /// Specifies Pmif controller
+        NvRmModuleID_Pmif,
+
+    /// Specifies Unified Command Queue
+        NvRmModuleID_Ucq,
+
+    /// Specifies Event controller
+        NvRmModuleID_EventCtrl,
+
+    /// Specifies Flow controller
+        NvRmModuleID_FlowCtrl,
+
+    /// Resource Semaphore
+        NvRmModuleID_ResourceSema,
+
+    /// Arbitration Semaphore
+        NvRmModuleID_ArbitrationSema,
+
+    /// Specifies Arbitration Priority
+        NvRmModuleID_ArbPriority,
+
+    /// Specifies Cache Memory Controller
+        NvRmModuleID_CacheMemCtrl,
+
+    /// Specifies very fast infra red controller
+        NvRmModuleID_Vfir,
+
+    /// Specifies Exception Vector
+        NvRmModuleID_ExceptionVector,
+
+    /// Specifies Boot Strap Controller
+        NvRmModuleID_BootStrap,
+
+    /// Specifies System Statistics Monitor controller
+        NvRmModuleID_SysStatMonitor,
+
+    /// Specifies System 
+        NvRmModuleID_Cdev,
+ 
+    /// Misc module ID which contains registers for PInmux/DAP control etc.
+        NvRmModuleID_Misc,
+
+    // PCIE Device attached to AP20
+        NvRmModuleID_PcieDevice,
+
+    // One-wire interface controller
+        NvRmModuleID_OneWire,
+
+    // Sync NOR controller
+        NvRmModuleID_SyncNor,
+
+    // NOR Memory aperture
+        NvRmModuleID_Nor,
+
+    // AVP UCQ module.
+        NvRmModuleID_AvpUcq,
+
+    /// clock and reset controller
+        NvRmPrivModuleID_ClockAndReset,
+
+    /// interrupt controller
+        NvRmPrivModuleID_Interrupt,
+
+    /// interrupt controller Arbitration Semaphore grant registers
+        NvRmPrivModuleID_InterruptArbGnt,
+
+    /// interrupt controller DMA Tx/Rx DRQ registers
+        NvRmPrivModuleID_InterruptDrq,
+
+    /// interrupt controller special SW interrupt
+        NvRmPrivModuleID_InterruptSw,
+
+    /// interrupt controller special CPU interrupt
+        NvRmPrivModuleID_InterruptCpu,
+
+    /// Apb Dma controller
+        NvRmPrivModuleID_ApbDma,
+
+    /// Apb Dma Channel
+        NvRmPrivModuleID_ApbDmaChannel,
+
+    /// Gpio controller
+        NvRmPrivModuleID_Gpio,
+
+    /// Pin-Mux Controller
+        NvRmPrivModuleID_PinMux,
+
+    /// memory configuation
+        NvRmPrivModuleID_Mselect,
+
+    /// memory controller (internal memory and memory arbitration)
+        NvRmPrivModuleID_MemoryController,
+
+    /// external memory (ddr ram, etc.)
+        NvRmPrivModuleID_ExternalMemoryController,
+
+    /// Processor Id
+        NvRmPrivModuleID_ProcId,
+
+    /// Entire System (used for system reset)
+        NvRmPrivModuleID_System,
+
+    /* CC device id (not sure what it actually does, but it is needed to
+     * set the mem_init_done bit so that memory works).
+     */
+        NvRmPrivModuleID_CC,
+
+    /// AHB Arbitration Control
+        NvRmPrivModuleID_Ahb_Arb_Ctrl,
+
+    /// AHB Gizmo Control
+        NvRmPrivModuleID_Ahb_Gizmo_Ctrl,
+
+    /// External memory
+        NvRmPrivModuleID_ExternalMemory,
+
+    /// Internal memory
+        NvRmPrivModuleID_InternalMemory,
+
+    /// TCRAM 
+        NvRmPrivModuleID_Tcram,
+
+    /// IRAM
+        NvRmPrivModuleID_Iram,
+
+    /// GART 
+        NvRmPrivModuleID_Gart,
+
+    /// MIO/EXIO
+        NvRmPrivModuleID_Mio_Exio,
+
+    /* External PMU */
+        NvRmPrivModuleID_PmuExt,
+
+    /* One module ID for all peripherals which includes cache controller, 
+     * SCU and interrupt controller */
+        NvRmPrivModuleID_ArmPerif,
+    NvRmPrivModuleID_ArmInterruptctrl,
+
+    /* PCIE Root Port internally is made up of 3 major blocks. These 3 blocks
+     * have seperate reset and clock domains. So, the driver treats these 
+     *  
+     *  AFI is the wrapper on the top of the PCI core.
+     *  PCIe refers to the core PCIe state machine module.
+     *  PcieXclk refers to the transmit/receive logic which runs at different
+     *  clock and have different reset.
+     * */
+        NvRmPrivModuleID_Afi,
+    NvRmPrivModuleID_Pcie,
+    NvRmPrivModuleID_PcieXclk,
+
+    /* PL310 */
+        NvRmPrivModuleID_Pl310,
+
+    /* 
+     * AHB re-map aperture seen from AVP. Use this aperture for AVP to have
+     * uncached access to SDRAM.
+     */
+        NvRmPrivModuleID_AhbRemap,
+    NvRmModuleID_Num,
+    NvRmModuleID_Force32 = 0x7FFFFFFF
+} NvRmModuleID;
+
+/* FIXME 
+ * Hack to make the existing drivers work. 
+ * NvRmPriv* should be renamed to NvRm*
+ */
+#define NvRmPrivModuleID_Num  NvRmModuleID_Num
+
+/**
+ * Multiple module instances are handled by packing the instance number into
+ * the high bits of the module id.  This avoids ponderous apis with both
+ * module ids and instance numbers.
+ */
+
+/**
+ * Module bitfields that are compatible with the NV_DRF macros.
+ */
+#define NVRM_MODULE_0                   (0x0)
+#define NVRM_MODULE_0_ID_RANGE          15:0
+#define NVRM_MODULE_0_INSTANCE_RANGE    19:16
+#define NVRM_MODULE_0_BAR_RANGE         23:20
+
+/**
+ * Create a module id with a given instance.
+ */
+#define NVRM_MODULE_ID( id, instance ) \
+    (NvRmModuleID)( \
+          NV_DRF_NUM( NVRM, MODULE, ID, (id) ) \
+        | NV_DRF_NUM( NVRM, MODULE, INSTANCE, (instance) ) )
+
+/**
+ * Get the actual module id.
+ */
+#define NVRM_MODULE_ID_MODULE( id ) \
+    NV_DRF_VAL( NVRM, MODULE, ID, (id) )
+
+/**
+ * Get the instance number of the module id.
+ */
+#define NVRM_MODULE_ID_INSTANCE( id ) \
+    NV_DRF_VAL( NVRM, MODULE, INSTANCE, (id) )
+
+/**
+ * Get the bar number for the module.
+ */
+#define NVRM_MODULE_ID_BAR( id ) \
+    NV_DRF_VAL( NVRM, MODULE, BAR, (id) )
+
+/**
+ * Module Information structure
+ */
+
+typedef struct NvRmModuleInfoRec
+{
+    NvU32 Instance;
+    NvU32 Bar;
+    NvRmPhysAddr BaseAddress;
+    NvU32 Length;
+} NvRmModuleInfo;
+
+/**
+ * Returns list of available module instances and their information.
+ *
+ * @param hRmDeviceHandle The RM device handle
+ * @param Module The module for which to get the number of instances.
+ * @param pNum Unsigned integer indicating the number of module information
+ *      structures in the array pModuleInfo.
+ * @param pModuleInfo A pointer to an array of module information structure,
+ *      where the size of array is determined by the value in pNum.
+ *
+ * @retval NvSuccess If successful, or the appropriate error.
+ */
+
+ NvError NvRmModuleGetModuleInfo( 
+    NvRmDeviceHandle hDevice,
+    NvRmModuleID module,
+    NvU32 * pNum,
+    NvRmModuleInfo * pModuleInfo );
+
+/**
+ * Returns a physical address associated with a hardware module.
+ * (To be depcreated and replaced by NvRmModuleGetModuleInfo)
+ *
+ * @param hRmDeviceHandle The RM device handle
+ * @param Module the module for which to get addresses.
+ * @param pBaseAddress a pointer to the beginning of the
+ * hardware register bank is stored here.
+ * @param pSize the length of the aperture in bytes is stored
+ * here.
+ */
+
+ void NvRmModuleGetBaseAddress( 
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvRmModuleID Module,
+    NvRmPhysAddr * pBaseAddress,
+    NvU32 * pSize );
+
+/**
+ * Returns the number of instances of a particular hardware module.
+ * (To be depcreated and replaced by NvRmModuleGetModuleInfo)
+ *
+ * @param hRmDeviceHandle The RM device handle
+ * @param Module The module for which to get the number of instances.
+ *
+ * @returns Number of instances.
+ */
+
+ NvU32 NvRmModuleGetNumInstances( 
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvRmModuleID Module );
+
+/**
+ * Resets the module controller hardware.
+ *
+ * @param hRmDeviceHandle The RM device handle
+ * @param Module The module to reset
+ */
+
+ void NvRmModuleReset( 
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvRmModuleID Module );
+
+/** 
+ *  Resets the controller with an option to hold the controller in the reset.
+ *  
+ *  @param hRmDeviceHandle Rm device handle
+ *  @param Module The module to be reset
+ *  @param bHold If NV_TRUE hold the module in reset, If NV_TRUE pulse the
+ *  reset.
+ *
+ *  So, to keep the module in reset and do something 
+ *  NvRmModuleResetWithHold(hRm, ModId, NV_TRUE)
+ *  ... update some registers
+ *  NvRmModuleResetWithHold(hRm, ModId, NV_FALSE)
+ */
+
+ void NvRmModuleResetWithHold( 
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvRmModuleID Module,
+    NvBool bHold );
+
+/**
+ * DDK capability encapsualtion. See NvRmModuleGetCapabilities().
+ */
+
+typedef struct NvRmModuleCapabilityRec
+{
+    NvU8 MajorVersion;
+    NvU8 MinorVersion;
+    NvU8 EcoLevel;
+    void* Capability;
+} NvRmModuleCapability;
+
+/**
+ * Returns a pointer to a class-specific capabilities structure.
+ *
+ * Each DDK will supply a list of NvRmCapability structures sorted by module
+ * Minor and Eco levels (assuming that no DDK supports two Major versions
+ * simulatenously).  The last cap in the list that matches the hardware's
+ * version and eco level will be returned.  If the current hardware's eco
+ * level is higher than the given module capability list, the last module
+ * capability with the highest eco level (the last in the list) will be
+ * returned.
+ * 
+ * @param hRmDeviceHandle The RM device handle
+ * @param Module the target module
+ * @param pCaps Pointer to the capability list
+ * @param NumCaps The number of capabilities in the list
+ * @param Capability Out parameter: the cap that maches the current hardware
+ *
+ * Example usage:
+ *
+ * typedef struct FakeDdkCapRec
+ * {
+ *     NvU32 FeatureBits;
+ * } FakeDdkCap;
+ *
+ * FakeDdkCap cap1;
+ * FakeDdkCap cap2;
+ * FakeDdkCap *cap;
+ * NvRmModuleCapability caps[] =
+ *       { { 1, 0, 0, &fcap1 },
+ *         { 1, 1, 0, &fcap2 },
+ *       };
+ * cap1.bits = ...;
+ * cap2.bits = ...;
+ * err = NvRmModuleGetCapabilities( hDevice, NvRmModuleID_FakeDDK, caps, 2,
+ *     (void *)&cap );
+ * ...
+ * if( cap->FeatureBits & FAKEDKK_SOME_FEATURE )
+ * {
+ *     ...
+ * }
+ */
+
+ NvError NvRmModuleGetCapabilities( 
+    NvRmDeviceHandle hDeviceHandle,
+    NvRmModuleID Module,
+    NvRmModuleCapability * pCaps,
+    NvU32 NumCaps,
+    void* * Capability );
+
+/**
+ * @brief Queries for the device unique ID.
+ *
+ * @pre Not callable from early boot.
+ *
+ * @param pId A pointer to an area of caller-allocated memory to hold the
+ * unique ID.
+ * @param pIdSize an input, a pointer to a variable containing the size of
+ * the caller-allocated memory to hold the unique ID pointed to by \em pId.
+ * Upon successful return, this value is updated to reflect the actual
+ * size of the unique ID returned in \em pId.
+ *
+ * @retval ::NvError_Success \em pId points to the unique ID and \em pIdSize
+ * points to the actual size of the ID.
+ * @retval ::NvError_BadParameter
+ * @retval ::NvError_NotSupported
+ * @retval ::NvError_InsufficientMemory
+ */
+ 
+ NvError NvRmQueryChipUniqueId( 
+    NvRmDeviceHandle hDevHandle,
+    NvU32 IdSize,
+    void* pId );
+
+/**
+ * @brief Returns random bytes using hardware sources of entropy
+ *
+ * @param hRmDeviceHandle The RM device handle
+ * @param NumBytes Number of random bytes to return in pBytes.
+ * @param pBytes Array where the random bytes should be stored
+ *
+ * @retval ::NvError_Success
+ * @retval ::NvError_BadParameter
+ * @retval ::NvError_NotSupported If no hardware entropy source is available
+ */
+ 
+ NvError NvRmGetRandomBytes( 
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvU32 NumBytes,
+    void* pBytes );
+
+/*
+ * Module access functions below. 
+ * NOTE: Rm doesn't gaurantee access to all the modules as it only maps a few
+ * modules.
+ * This is not meant to be a primary mechanism to access the module registers.
+ * Clients should map their register address and access the registers.
+ */
+
+/**
+ * NV_REGR: register read from hardware.
+ *
+ * @param rm The resource manager istance
+ * @param aperture The register aperture
+ * @param instance The module instance
+ * @param offset The offset inside the aperture
+ *
+ * Note that the aperture comes from the RM's private module id enumeration,
+ * which is a superset of the public enumeration from nvrm_module.h.
+ */
+
+/**
+ * NV_REGW: register write to hardware.
+ * 
+ * @param rm The resource manager istance
+ * @param aperture The register aperture
+ * @param instance The module instance
+ * @param offset The offset inside the aperture
+ * @param data The data to write
+ *
+ * see the note regarding apertures for NV_REGR.
+ */
+#define NV_REGR(rm, aperture, instance, offset) \
+    NvRegr((rm),(NvRmModuleID)NVRM_MODULE_ID((aperture),(instance)),(offset))
+
+#define NV_REGW(rm, aperture, instance, offset, data) \
+    NvRegw((rm),(NvRmModuleID)NVRM_MODULE_ID((aperture),(instance)),(offset),(data))
+
+
+ NvU32 NvRegr( 
+    NvRmDeviceHandle hDeviceHandle,
+    NvRmModuleID aperture,
+    NvU32 offset );
+
+ void NvRegw( 
+    NvRmDeviceHandle hDeviceHandle,
+    NvRmModuleID aperture,
+    NvU32 offset,
+    NvU32 data );
+
+/**
+ * NV_REGR_MULT: read multiple registers from hardware
+ *
+ * @param rm The resource manager istance
+ * @param aperture The register aperture
+ * @param instance The module instance
+ * @param num The number of registers
+ * @param offsets The register offsets
+ * @param values The register values
+ */
+
+/**
+ * NV_REGW_MULT: write multiple registers from hardware
+ *
+ * @param rm The resource manager istance
+ * @param aperture The register aperture
+ * @param instance The module instance
+ * @param num The number of registers
+ * @param offsets The register offsets
+ * @param values The register values
+ */
+
+/**
+ * NV_REGW_BLOCK: write a block of registers to hardware
+ *
+ * @param rm The resource manager istance
+ * @param aperture The register aperture
+ * @param instance The module instance
+ * @param num The number of registers
+ * @param offset The beginning register offset
+ * @param values The register values
+ */
+
+/**
+ * NV_REGR_BLOCK: read a block of registers from hardware
+ *
+ * @param rm The resource manager istance
+ * @param aperture The register aperture
+ * @param instance The module instance
+ * @param num The number of registers
+ * @param offset The beginning register offset
+ * @param values The register values
+ */
+
+#define NV_REGR_MULT(rm, aperture, instance, num, offsets, values) \
+    NvRegrm((rm),(NvRmModuleID)NVRM_MODULE_ID((aperture),(instance)),(num),(offsets),(values))
+
+#define NV_REGW_MULT(rm, aperture, instance, num, offsets, values) \
+    NvRegwm((rm),(NvRmModuleID)NVRM_MODULE_ID((aperture),(instance)),(num),(offsets),(values))
+
+#define NV_REGW_BLOCK(rm, aperture, instance, num, offset, values) \
+    NvRegwb((rm),(NvRmModuleID)NVRM_MODULE_ID((aperture),(instance)),(num),(offset),(values))
+
+#define NV_REGR_BLOCK(rm, aperture, instance, num, offset, values) \
+    NvRegrb((rm),(NvRmModuleID)NVRM_MODULE_ID((aperture),(instance)),(num),(offset),(values))
+
+ void NvRegrm( 
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvRmModuleID aperture,
+    NvU32 num,
+    const NvU32 * offsets,
+    NvU32 * values );
+
+ void NvRegwm( 
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvRmModuleID aperture,
+    NvU32 num,
+    const NvU32 * offsets,
+    const NvU32 * values );
+
+ void NvRegwb( 
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvRmModuleID aperture,
+    NvU32 num,
+    NvU32 offset,
+    const NvU32 * values );
+
+ void NvRegrb( 
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvRmModuleID aperture,
+    NvU32 num,
+    NvU32 offset,
+    NvU32 * values );
+
+#define NV_REGR08(rm, aperture, instance, offset) \
+    NvRegr08((rm),(NvRmModuleID)NVRM_MODULE_ID((aperture),(instance)),(offset))
+
+#define NV_REGW08(rm, aperture, instance, offset, data) \
+    NvRegw08((rm),(NvRmModuleID)NVRM_MODULE_ID((aperture),(instance)),(offset),(data))
+
+ NvU8 NvRegr08( 
+    NvRmDeviceHandle hDeviceHandle,
+    NvRmModuleID aperture,
+    NvU32 offset );
+
+ void NvRegw08( 
+    NvRmDeviceHandle rm,
+    NvRmModuleID aperture,
+    NvU32 offset,
+    NvU8 data );
+
+/** @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif
diff --git a/arch/arm/mach-tegra/include/nvrm_owr.h b/arch/arm/mach-tegra/include/nvrm_owr.h
new file mode 100644
index 000000000000..8aebb28e4ad0
--- /dev/null
+++ b/arch/arm/mach-tegra/include/nvrm_owr.h
@@ -0,0 +1,179 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_nvrm_owr_H
+#define INCLUDED_nvrm_owr_H
+
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+#include "nvrm_pinmux.h"
+#include "nvrm_module.h"
+#include "nvrm_init.h"
+
+#include "nvos.h"
+#include "nvcommon.h"
+
+/**
+ * NvRmOwrHandle is an opaque handle for the RM OWR driver.
+ */
+
+typedef struct NvRmOwrRec *NvRmOwrHandle;
+
+/**
+ * @brief Open the OWR driver. This function allocates the
+ * RM OWR handle.
+ *
+ * Assert encountered in debug mode if passed parameter is invalid.
+ *
+ * @param hDevice Handle to the Rm device which is required by Rm to acquire
+ * the resources from RM.
+ * @param instance Instance of the OWR controller to be opened. Starts from 0.
+ * @param phOwr Points to the location where the OWR handle shall be stored.
+ *
+ * @retval NvSuccess OWR driver opened successfully.
+ * @retval NvError_InsufficientMemory Indicates that function fails to allocate
+ * the memory.
+ */
+
+ NvError NvRmOwrOpen(
+    NvRmDeviceHandle hDevice,
+    NvU32 instance,
+    NvRmOwrHandle * hOwr );
+
+/**
+ * @brief Closes the OWR driver. Disables the clock and invalidates the OWR handle.
+ * This API never fails.
+ *
+ * @param hOwr A handle from NvRmOwrOpen().  If hOwr is NULL, this API does
+ *     nothing.
+ */
+
+ void NvRmOwrClose(
+    NvRmOwrHandle hOwr );
+
+/**
+ * Defines OWR transaction flags.
+ */
+
+typedef enum
+{
+
+      /// OWR read the unique address of the device.
+          NvRmOwr_ReadAddress = 1,
+
+      /// OWR memory read transaction.
+          NvRmOwr_MemRead,
+
+      /// OWR memory write transaction.
+          NvRmOwr_MemWrite,
+
+      /// OWR memory readbyte transaction.
+          NvRmOwr_ReadByte,
+
+      /// OWR memory writebyte transaction.
+          NvRmOwr_WriteByte,
+
+      /// OWR memory Check Presence
+          NvRmOwr_CheckPresence,
+
+      /// OWR readbit transaction.
+      /// The LSB will be received first.
+          NvRmOwr_ReadBit,
+
+      /// OWR writebit transaction.
+      /// The LSB will be transmitted first.
+          NvRmOwr_WriteBit,
+
+    NvRmOwrTransactionFlags_Num,
+    NvRmOwrTransactionFlags_Force32 = 0x7FFFFFFF
+} NvRmOwrTransactionFlags;
+
+/**
+ * Defines OWR transaction info structure. Contains details of the transaction.
+ */
+
+typedef struct NvRmOwrTransactionInfoRec
+{
+
+    /// Transaction type flags. See @NvRmOwrTransactionFlags
+        NvU32 Flags;
+
+    /// Offset in the OWR device where Memory read/write operations need to be performed.
+        NvU32 Offset;
+
+    /// Number of bytes to read/write.
+        NvU32 NumBytes;
+
+    /// OWR device ROM Id. This can be zero, if there is a single OWR device on the bus.
+        NvU32 Address;
+} NvRmOwrTransactionInfo;
+
+/**
+ * @brief Does multiple OWR transactions. Each transaction can be a read or write.
+ *
+ * @param hOwr Handle to the OWR channel.
+ * @param OwrPinMap for OWR controllers which are being multiplexed across
+ *        multiple pin mux configurations, this specifies which pin mux configuration
+ *        should be used for the transaction.  Must be 0 when the ODM pin mux query
+ *        specifies a non-multiplexed configuration for the controller.
+ * @param Data Pointer to the buffer for all the required read, write transactions.
+ * @param DataLength Length of the data buffer.
+ * @param Transcations Pointer to the NvRmOwrTransactionInfo structure.
+ * See @NvRmOwrTransactionInfo
+ * @param NumOfTransactions Number of transcations
+ *
+ *
+ * @retval NvSuccess OWR Transaction succeeded.
+ * @retval NvError_NotSupported Indicates assumption on parameter values violated.
+ * @retval NvError_InvalidState Indicates that the last read or write call is not
+ * completed.
+ * @retval NvError_ControllerBusy Indicates controller is presently busy with an
+ * OWR transaction.
+ */
+
+ NvError NvRmOwrTransaction(
+    NvRmOwrHandle hOwr,
+    NvU32 OwrPinMap,
+    NvU8 * Data,
+    NvU32 DataLen,
+    NvRmOwrTransactionInfo * Transaction,
+    NvU32 NumOfTransactions );
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif
diff --git a/arch/arm/mach-tegra/include/nvrm_pinmux.h b/arch/arm/mach-tegra/include/nvrm_pinmux.h
new file mode 100644
index 000000000000..bafe6a2655b4
--- /dev/null
+++ b/arch/arm/mach-tegra/include/nvrm_pinmux.h
@@ -0,0 +1,222 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_nvrm_pinmux_H
+#define INCLUDED_nvrm_pinmux_H
+
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+#include "nvrm_module.h"
+#include "nvrm_init.h"
+
+#include "nvodm_modules.h"
+
+/**
+ * For each module that has pins (an I/O module), there may be several muxing
+ * configurations. This allows a driver to select or query a particular
+ * configuration per I/O module.  I/O modules may be instantiated on the
+ * chip multiple times.
+ *
+ * Certain combinations of modules configurations may not be physically
+ * possible; say that a hypothetical SPI controller configuration 3 uses pins
+ * that are shared by a hypothectial UART configuration 2.  Presently, these
+ * conflicting configurations are managed via an external tool provided by
+ * SysEng, which identifies the configurations for the ODM pin-mux tables
+ * depending upon choices made by the ODM.
+ */
+
+/**
+ * Sets the module to tristate configuration. 
+ * Use enable to release the pinmux.  The pins will be
+ * tri-stated when not in use to save power.
+ *
+ * @param hDevice The RM instance
+ * @param RmModule The module to set
+ * @param EnableTristate NV_TRUE will tristate the specified pins, NV_FALSE will un-tristate
+ */
+
+ NvError NvRmSetModuleTristate( 
+    NvRmDeviceHandle hDevice,
+    NvRmModuleID RmModule,
+    NvBool EnableTristate );
+
+/**
+ * Sets an ODM module ID to tristate configuration.  Analagous to @see NvRmSetModuleTristate,
+ * but indexed based on the ODM module ID, rather than the controller ID.
+ *
+ * @param hDevice The RM instance
+ * @param OdmModule The module to set (should be of type NvOdmIoModule)
+ * @param OdmInstance The instance of the module to set
+ * @param EnableTristate NV_TRUE will tristate the specified pins, NV_FALSE will un-tristate
+ */
+
+ NvError NvRmSetOdmModuleTristate( 
+    NvRmDeviceHandle hDevice,
+    NvU32 OdmModule,
+    NvU32 OdmInstance,
+    NvBool EnableTristate );
+
+/**
+ * Configures modules which can provide clock sources to peripherals.
+ * If a Tegra application processor is expected to provide a clock source
+ * to an external peripheral, this API should be called to configure the
+ * clock source and to ensure that its pins are driven prior to attempting
+ * to program the peripheral through a command interface (e.g., SPI).
+ *
+ * @param hDevice The RM instance
+ * @param IoModule The module to set, must be NvOdmIoModule_ExternalClock
+ * @param Instance The instance of the I/O module to be set.
+ * @param Config The pin map configuration for the I/O module.
+ * @param EnableTristate NV_TRUE will tristate the specified clock source,
+ *                       NV_FALSE will drive it.
+ * 
+ * @retval Returns the clock frequency, in KHz, that is output on the
+ *  designated pin (or '0' if no clock frequency is specified or found).
+ */
+
+ NvU32 NvRmExternalClockConfig( 
+    NvRmDeviceHandle hDevice,
+    NvU32 IoModule,
+    NvU32 Instance,
+    NvU32 Config,
+    NvBool EnableTristate );
+
+typedef struct NvRmModuleSdmmcInterfaceCapsRec
+{
+
+   ///  Maximum bus width supported by the physical interface
+   ///  Will be 2, 4 or 8 depending on the selected pin mux
+       NvU32 MmcInterfaceWidth;
+} NvRmModuleSdmmcInterfaceCaps;
+
+typedef struct NvRmModulePcieInterfaceCapsRec
+{
+
+   ///  Maximum bus type supported by the physical interface
+   ///  Will be 4X1 or 2X2 depending on the selected pin mux
+       NvU32 PcieNumEndPoints;
+    NvU32 PcieLanesPerEp;
+} NvRmModulePcieInterfaceCaps;
+
+typedef struct NvRmModulePwmInterfaceCapsRec
+{
+
+   ///  The OR bits value of PWM Output IDs supported by the 
+   ///  physical interface depending on the selected pin mux.
+   ///  Hence, PwmOutputId_PWM0 = bit 0, PwmOutputId_PWM1 = bit 1,
+   ///  PwmOutputId_PWM2 = bit 2, PwmOutputId_PWM3 = bit 3
+       NvU32 PwmOutputIdSupported;
+} NvRmModulePwmInterfaceCaps;
+
+typedef struct NvRmModuleNandInterfaceCapsRec
+{
+
+   ///  Maximum bus width supported by the physical interface
+   ///  Will be 8 or 16 depending on the selected pin mux
+       NvU8 NandInterfaceWidth;
+    NvBool IsCombRbsyMode;
+} NvRmModuleNandInterfaceCaps;
+
+typedef struct NvRmModuleUartInterfaceCapsRec
+{
+
+   ///  Maximum number of the interface lines supported by the physical interface.
+   ///  Will be 0, 2, 4 or 8 depending on the selected pin mux.
+   ///  0 means there is no physical interface for the uart.
+   ///  2 means only rx/tx lines are supported.
+   ///  4 means only rx/tx/rtx/cts lines are supported.
+   ///  8 means full modem lines are supported.
+       NvU32 NumberOfInterfaceLines;
+} NvRmModuleUartInterfaceCaps;
+
+/**
+ * @brief Query the board-defined capabilities of an I/O controller
+ *
+ * This API will return capabilities for controller modules based on
+ * interface properties defined by ODM query interfaces, such as the
+ * pin mux query.
+ *
+ * pCap should be a pointer to the matching NvRmxxxInterfaceCaps structure
+ * (defined above) for the ModuleId, and CapStructSize should be
+ * the sizeof(structure type). and also should be word aligned.
+ * 
+ * @retval NvError_NotSupported if the specified ModuleID does not
+ *     exist on the current platform.
+ */
+
+ NvError NvRmGetModuleInterfaceCapabilities( 
+    NvRmDeviceHandle hRm,
+    NvRmModuleID ModuleId,
+    NvU32 CapStructSize,
+    void* pCaps );
+
+/**
+ * Defines SoC strap groups.
+ */
+
+typedef enum
+{
+
+    /// ram_code strap group  
+        NvRmStrapGroup_RamCode = 1,
+    NvRmStrapGroup_Num,
+    NvRmStrapGroup_Force32 = 0x7FFFFFFF
+} NvRmStrapGroup;
+
+/**
+ * Gets SoC strap value for the given strap group.
+ * 
+ * @param hDevice The RM instance
+ * @param StrapGroup Strap group to be read.
+ * @pStrapValue A pointer to the returned strap group value.
+ * 
+ * @retval NvSuccess if strap value is read successfully
+ * @retval NvError_NotSupported if the specified strap group does not
+ *   exist on the current SoC.
+ */
+
+ NvError NvRmGetStraps( 
+    NvRmDeviceHandle hDevice,
+    NvRmStrapGroup StrapGroup,
+    NvU32 * pStrapValue );
+
+/** @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif
diff --git a/arch/arm/mach-tegra/include/nvrm_pmu.h b/arch/arm/mach-tegra/include/nvrm_pmu.h
new file mode 100644
index 000000000000..7ab6fa92d309
--- /dev/null
+++ b/arch/arm/mach-tegra/include/nvrm_pmu.h
@@ -0,0 +1,420 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_nvrm_pmu_H
+#define INCLUDED_nvrm_pmu_H
+
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+#include "nvrm_init.h"
+
+/**
+ * @defgroup nvrm_pmu 
+ *   
+ * This is the power management unit (PMU) API for Rm, which
+ * handles the abstraction of external power management devices.
+ * For NVIDIA&reg; Driver Development Kit (DDK) clients, PMU is a 
+ * set of voltages used to provide power to the SoC or to monitor low battery 
+ * conditions. The API allows DDK clients to determine whether the
+ * particular voltage is supported by the ODM platform, retrieve the
+ * capabilities of PMU, and get/set voltage levels at runtime. 
+ *
+ * All voltage rails are referenced using ODM-assigned unsigned integers. ODMs
+ * may select any convention for assigning these values; however, the values
+ * accepted as input parameters by the PMU ODM adaptation interface must
+ * match the values stored in the address field of \c NvRmIoModule_Vdd buses
+ * defined in the Peripheral Discovery ODM adaptation.
+ * 
+ *
+ * @ingroup nvrm_pmu
+ * @{
+ */
+
+/**
+ * Combines information for the particular PMU Vdd rail.
+ */
+
+typedef struct NvRmPmuVddRailCapabilitiesRec
+{
+
+    /// Specifies ODM protection attribute; if \c NV_TRUE PMU hardware
+    ///  or ODM Kit would protect this voltage from being changed by NvDdk client.
+        NvBool RmProtected;
+
+    /// Specifies the minimum voltage level in mV.
+        NvU32 MinMilliVolts;
+
+    /// Specifies the step voltage level in mV.
+        NvU32 StepMilliVolts;
+
+    /// Specifies the maximum voltage level in mV.
+        NvU32 MaxMilliVolts;
+
+    /// Specifies the request voltage level in mV.
+        NvU32 requestMilliVolts;
+} NvRmPmuVddRailCapabilities;
+
+/// Special level to indicate voltage plane is disabled.
+#define ODM_VOLTAGE_OFF (0UL)
+
+/**
+ * Gets capabilities for the specified PMU voltage.
+ *
+ * @param vddId The ODM-defined PMU rail ID.
+ * @param pCapabilities A pointer to the targeted
+ *  capabilities returned by the ODM.
+ */
+
+ void NvRmPmuGetCapabilities( 
+    NvRmDeviceHandle hDevice,
+    NvU32 vddId,
+    NvRmPmuVddRailCapabilities * pCapabilities );
+
+/**
+ * Gets current voltage level for the specified PMU voltage.
+ *
+ * @param hDevice The Rm device handle.
+ * @param vddId The ODM-defined PMU rail ID.
+ * @param pMilliVolts A pointer to the voltage level returned
+ *  by the ODM.
+ */
+
+ void NvRmPmuGetVoltage( 
+    NvRmDeviceHandle hDevice,
+    NvU32 vddId,
+    NvU32 * pMilliVolts );
+
+/**
+ * Sets new voltage level for the specified PMU voltage.
+ *
+ * @param hDevice The Rm device handle.
+ * @param vddId The ODM-defined PMU rail ID.
+ * @param MilliVolts The new voltage level to be set in millivolts (mV).
+ *  Set to \c ODM_VOLTAGE_OFF to turn off the target voltage.
+ * @param pSettleMicroSeconds A pointer to the settling time in microseconds (uS),
+ *  which is the time for supply voltage to settle after this function 
+ *  returns; this may or may not include PMU control interface transaction time, 
+ *  depending on the ODM implementation. If null this parameter is ignored. 
+ */
+
+ void NvRmPmuSetVoltage( 
+    NvRmDeviceHandle hDevice,
+    NvU32 vddId,
+    NvU32 MilliVolts,
+    NvU32 * pSettleMicroSeconds );
+
+/**
+ * Configures SoC power rail controls for the upcoming PMU voltage transition.
+ *
+ * @note Should be called just before PMU rail On/Off, or Off/On transition.
+ *  Should not be called if rail voltage level is changing within On range.
+ * 
+ * @param hDevice The Rm device handle.
+ * @param vddId The ODM-defined PMU rail ID.
+ * @param Enable Set NV_TRUE if target voltage is about to be turned On, or
+ *  NV_FALSE if target voltage is about to be turned Off.
+ */
+
+ void NvRmPmuSetSocRailPowerState( 
+    NvRmDeviceHandle hDevice,
+    NvU32 vddId,
+    NvBool Enable );
+
+/**
+ * Defines Charging path.
+ */
+
+typedef enum
+{
+
+    /// Specifies external wall plug charger.
+        NvRmPmuChargingPath_MainPlug,
+
+    /// Specifies external USB bus charger.
+        NvRmPmuChargingPath_UsbBus,
+    NvRmPmuChargingPath_Num,
+    NvRmPmuChargingPath_Force32 = 0x7FFFFFFF
+} NvRmPmuChargingPath;
+
+/// Special level to indicate dumb charger current limit.
+#define NVODM_DUMB_CHARGER_LIMIT (0xFFFFFFFFUL)
+
+/**
+ * Defines AC status.
+ */
+
+typedef enum
+{
+
+    /// Specifies AC is offline.
+        NvRmPmuAcLine_Offline,
+
+    /// Specifies AC is online.
+        NvRmPmuAcLine_Online,
+
+    /// Specifies backup power.
+        NvRmPmuAcLine_BackupPower,
+    NvRmPmuAcLineStatus_Num,
+    NvRmPmuAcLineStatus_Force32 = 0x7FFFFFFF
+} NvRmPmuAcLineStatus;
+
+/** @name Battery Status Defines */
+/*@{*/
+
+#define NVODM_BATTERY_STATUS_HIGH               0x01
+#define NVODM_BATTERY_STATUS_LOW                0x02
+#define NVODM_BATTERY_STATUS_CRITICAL           0x04
+#define NVODM_BATTERY_STATUS_CHARGING           0x08
+#define NVODM_BATTERY_STATUS_NO_BATTERY         0x80
+#define NVODM_BATTERY_STATUS_UNKNOWN            0xFF
+
+/*@}*/
+/** @name Battery Data Defines */
+/*@{*/
+#define NVODM_BATTERY_DATA_UNKNOWN              0x7FFFFFFF
+
+/*@}*/
+
+/**
+ * Defines battery instances.
+ */
+
+typedef enum
+{
+
+    /// Specifies main battery.
+        NvRmPmuBatteryInst_Main,
+    NvRmPmuBatteryInst_Backup,
+    NvRmPmuBatteryInstance_Num,
+    NvRmPmuBatteryInstance_Force32 = 0x7FFFFFFF
+} NvRmPmuBatteryInstance;
+
+/**
+ * Defines battery data.
+ */
+
+typedef struct NvRmPmuBatteryDataRec
+{
+
+    /// Specifies battery life percent.
+        NvU32 batteryLifePercent;
+
+    /// Specifies battery life time.
+        NvU32 batteryLifeTime;
+
+    /// Specifies voltage.
+        NvU32 batteryVoltage;
+
+    /// Specifies battery current.
+        NvS32 batteryCurrent;
+
+    /// Specifies battery average current.
+        NvS32 batteryAverageCurrent;
+
+    /// Specifies battery interval.
+        NvU32 batteryAverageInterval;
+
+    /// Specifies the mAH consumed.
+        NvU32 batteryMahConsumed;
+
+    /// Specifies battery temperature.
+        NvU32 batteryTemperature;
+} NvRmPmuBatteryData;
+
+/**
+ * Defines battery chemistry.
+ */
+
+typedef enum
+{
+
+    /// Specifies an alkaline battery.
+        NvRmPmuBatteryChemistry_Alkaline,
+
+    /// Specifies a nickel-cadmium (NiCd) battery.
+        NvRmPmuBatteryChemistry_NICD,
+
+    /// Specifies a nickel-metal hydride (NiMH) battery.
+        NvRmPmuBatteryChemistry_NIMH,
+
+    /// Specifies a lithium-ion (Li-ion) battery.
+        NvRmPmuBatteryChemistry_LION,
+
+    /// Specifies a lithium-ion polymer (Li-poly) battery.
+        NvRmPmuBatteryChemistry_LIPOLY,
+
+    /// Specifies a zinc-air battery.
+        NvRmPmuBatteryChemistry_XINCAIR,
+    NvRmPmuBatteryChemistry_Num,
+    NvRmPmuBatteryChemistry_Force32 = 0x7FFFFFFF
+} NvRmPmuBatteryChemistry;
+
+/** 
+* Sets the charging current limit. 
+* 
+* @param hRmDevice The Rm device handle.
+* @param ChargingPath The charging path. 
+* @param ChargingCurrentLimitMa The charging current limit in mA. 
+* @param ChargerType Type of the charger detected 
+*        @see NvOdmUsbChargerType
+*/
+
+ void NvRmPmuSetChargingCurrentLimit( 
+    NvRmDeviceHandle hRmDevice,
+    NvRmPmuChargingPath ChargingPath,
+    NvU32 ChargingCurrentLimitMa,
+    NvU32 ChargerType );
+
+/**
+ * Gets the AC line status.
+ *
+ * @param hDevice The Rm device handle.
+ * @param pStatus A pointer to the AC line
+ *  status returned by the ODM.
+ * 
+ * @return NV_TRUE if successful, or NV_FALSE otherwise.
+ */
+
+ NvBool NvRmPmuGetAcLineStatus( 
+    NvRmDeviceHandle hRmDevice,
+    NvRmPmuAcLineStatus * pStatus );
+
+/**
+ * Gets the battery status.
+ *
+ * @param hDevice The Rm device handle.
+ * @param batteryInst The battery type.
+ * @param pStatus A pointer to the battery
+ *  status returned by the ODM.
+ * 
+ * @return NV_TRUE if successful, or NV_FALSE otherwise.
+ */
+
+ NvBool NvRmPmuGetBatteryStatus( 
+    NvRmDeviceHandle hRmDevice,
+    NvRmPmuBatteryInstance batteryInst,
+    NvU8 * pStatus );
+
+/**
+ * Gets the battery data.
+ *
+ * @param hDevice The Rm device handle.
+ * @param batteryInst The battery type.
+ * @param pData A pointer to the battery
+ *  data returned by the ODM.
+ * 
+ * @return NV_TRUE if successful, or NV_FALSE otherwise.
+ */
+
+ NvBool NvRmPmuGetBatteryData( 
+    NvRmDeviceHandle hRmDevice,
+    NvRmPmuBatteryInstance batteryInst,
+    NvRmPmuBatteryData * pData );
+
+/**
+ * Gets the battery full life time.
+ *
+ * @param hDevice The Rm device handle.
+ * @param batteryInst The battery type.
+ * @param pLifeTime A pointer to the battery
+ *  full life time returned by the ODM.
+ * 
+ */
+
+ void NvRmPmuGetBatteryFullLifeTime( 
+    NvRmDeviceHandle hRmDevice,
+    NvRmPmuBatteryInstance batteryInst,
+    NvU32 * pLifeTime );
+
+/**
+ * Gets the battery chemistry.
+ *
+ * @param hDevice The Rm device handle.
+ * @param batteryInst The battery type.
+ * @param pChemistry A pointer to the battery
+ *  chemistry returned by the ODM.
+ * 
+ */
+
+ void NvRmPmuGetBatteryChemistry( 
+    NvRmDeviceHandle hRmDevice,
+    NvRmPmuBatteryInstance batteryInst,
+    NvRmPmuBatteryChemistry * pChemistry );
+
+/**
+ * Reads current RTC count in seconds.
+ *
+ * @param hRmDevice The Rm device handle.
+ * @param Count A pointer to the RTC count returned by this function.
+ * 
+ * @return NV_TRUE if successful, or NV_FALSE otherwise. 
+ */
+
+ NvBool NvRmPmuReadRtc( 
+    NvRmDeviceHandle hRmDevice,
+    NvU32 * pCount );
+
+/**
+ * Updates current RTC seconds count.
+ *
+ * @param hRmDevice The Rm device handle.
+ * @param Count Seconds count to update the RTC counter.
+ * 
+ * @return NV_TRUE if successful, or NV_FALSE otherwise.
+ */
+
+ NvBool NvRmPmuWriteRtc( 
+    NvRmDeviceHandle hRmDevice,
+    NvU32 Count );
+
+/**
+ * Verifies whether the RTC is initialized.
+ *
+ * @param hRmDevice The Rm device handle.
+ * 
+ * @return NV_TRUE if initialized, or NV_FALSE otherwise.
+ */
+
+ NvBool NvRmPmuIsRtcInitialized( 
+    NvRmDeviceHandle hRmDevice );
+
+/** @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif
diff --git a/arch/arm/mach-tegra/include/nvrm_power.h b/arch/arm/mach-tegra/include/nvrm_power.h
new file mode 100644
index 000000000000..e8be8c9bf4cf
--- /dev/null
+++ b/arch/arm/mach-tegra/include/nvrm_power.h
@@ -0,0 +1,1326 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_nvrm_power_H
+#define INCLUDED_nvrm_power_H
+
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+#include "nvrm_module.h"
+#include "nvrm_init.h"
+
+#include "nvos.h"
+
+/**
+ * Frequency data type, expressed in KHz.
+ */
+
+typedef NvU32 NvRmFreqKHz;
+
+/**
+ * Special value for an unspecified or default frequency.
+ */
+static const NvRmFreqKHz NvRmFreqUnspecified = 0xFFFFFFFF;
+
+/**
+ * Special value for the maximum possible frequency.
+ */
+static const NvRmFreqKHz NvRmFreqMaximum = 0xFFFFFFFD;
+
+/**
+ * Voltage data type, expressed in millivolts.
+ */
+
+typedef NvU32 NvRmMilliVolts;
+
+/**
+ * Special value for an unspecified or default voltage.
+ */
+static const NvRmMilliVolts NvRmVoltsUnspecified = 0xFFFFFFFF;
+
+/**
+ * Special value for the maximum possible voltage.
+ */
+static const NvRmMilliVolts NvRmVoltsMaximum = 0xFFFFFFFD;
+
+/**
+ * Special value for voltage / power disable.
+ */
+static const NvRmMilliVolts NvRmVoltsCycled = 0xFFFFFFFC;
+
+/**
+ * Special value for voltage / power disable.
+ */
+static const NvRmMilliVolts NvRmVoltsOff = 0;
+
+/**
+ * Defines possible power management events
+ */
+
+typedef enum
+{
+
+    /// Specifies no outstanding events
+        NvRmPowerEvent_NoEvent = 1,
+
+    /// Specifies wake from LP0
+        NvRmPowerEvent_WakeLP0,
+
+    /// Specifies wake from LP1
+        NvRmPowerEvent_WakeLP1,
+    NvRmPowerEvent_Num,
+    NvRmPowerEvent_Force32 = 0x7FFFFFFF
+} NvRmPowerEvent;
+
+/**
+ * Defines combined RM clients power state
+ */
+
+typedef enum
+{
+
+    /// Specifies boot state ("RM is not open, yet")
+        NvRmPowerState_Boot = 1,
+
+    /// Specifies active state ("not ready-to-suspend")
+    /// This state is entered if any client enables power to any module, other
+    /// than NvRmPrivModuleID_System, via NvRmPowerVoltageControl() API
+        NvRmPowerState_Active,
+
+    /// Specifies h/w autonomous state ("ready-to-core-power-on-suspend")
+    /// This state is entered if all RM clients enable power only for
+    /// NvRmPrivModuleID_System, via NvRmPowerVoltageControl() API
+        NvRmPowerState_AutoHw,
+
+    /// Specifies idle state ("ready-to-core-power-off-suspend")
+    /// This state is entered if none of the RM clients enables power
+    /// to any module.
+        NvRmPowerState_Idle,
+
+    /// Specifies LP0 state ("main power-off suspend")
+        NvRmPowerState_LP0,
+
+    /// Specifies LP1 state ("main power-on suspend")
+        NvRmPowerState_LP1,
+
+    /// Specifies Skipped LP0 state (set when LP0 entry error is
+    /// detected, SoC resumes operations without entering LP0 state)
+        NvRmPowerState_SkippedLP0,
+    NvRmPowerState_Num,
+    NvRmPowerState_Force32 = 0x7FFFFFFF
+} NvRmPowerState;
+
+/** Defines the clock configuration flags which are applicable for some modules.
+ * Multiple flags can be OR'ed and passed to the NvRmPowerModuleClockConfig API.
+*/
+
+typedef enum
+{
+
+    /// Use external clock for the pads of the module.
+        NvRmClockConfig_ExternalClockForPads = 0x1,
+
+    /// Use internal clock for the pads of the module
+        NvRmClockConfig_InternalClockForPads = 0x2,
+
+    /// Use external clock for the core of the module, or
+    /// module is in slave mode
+        NvRmClockConfig_ExternalClockForCore = 0x4,
+
+    /// Use Internal clock for the core of the module, or
+    /// module is in master mode.
+        NvRmClockConfig_InternalClockForCore = 0x8,
+ 
+    /// Use inverted clock for the module. i.e the polarity of the clock used is
+    /// inverted with respect to the source clock.
+        NvRmClockConfig_InvertedClock = 0x10,
+ 
+    /// Configure target module sub-clock
+    /// - Target Display: configure Display and TVDAC
+    /// - Target TVO: configure CVE and TVDAC only
+    /// - Target VI: configure VI_SENSOR only
+    /// - Target SPDIF: configure SPDIFIN only
+        NvRmClockConfig_SubConfig = 0x20,
+ 
+    /// Use MIPI PLL as Display clock source
+        NvRmClockConfig_MipiSync = 0x40,
+ 
+    /// Adjust Audio PLL to match requested I2S or SPDIF frequency
+        NvRmClockConfig_AudioAdjust = 0x80,
+ 
+    /// Disable TVDAC along with Display configuration
+        NvRmClockConfig_DisableTvDAC = 0x100,
+ 
+    /// Do not fail clock configuration request with specific target frequency
+    /// above Hw limit - just configure clock at Hw limit. (Note that caller
+    /// can request NvRmFreqMaximum to configure clock at Hw limit, regardless
+    /// of this flag presence).
+        NvRmClockConfig_QuietOverClock = 0x200,
+    NvRmClockConfigFlags_Num,
+    NvRmClockConfigFlags_Force32 = 0x7FFFFFFF
+} NvRmClockConfigFlags;
+
+/**
+ * Defines SOC-wide clocks controlled by Dynamic Frequency Scaling (DFS)
+ * that can be targeted by Starvation and Busy hints
+ */
+
+typedef enum
+{
+
+    /// Specifies CPU clock
+        NvRmDfsClockId_Cpu = 1,
+
+    /// Specifies AVP clock
+        NvRmDfsClockId_Avp,
+
+    /// Specifies System bus clock
+        NvRmDfsClockId_System,
+
+    /// Specifies AHB bus clock
+        NvRmDfsClockId_Ahb,
+
+    /// Specifies APB bus clock
+        NvRmDfsClockId_Apb,
+
+    /// Specifies video pipe clock
+        NvRmDfsClockId_Vpipe,
+
+    /// Specifies external memory controller clock
+        NvRmDfsClockId_Emc,
+    NvRmDfsClockId_Num,
+    NvRmDfsClockId_Force32 = 0x7FFFFFFF
+} NvRmDfsClockId;
+
+/**
+ * Defines DFS manager run states
+ */
+
+typedef enum
+{
+
+    /// DFS is in invalid, not initialized state
+        NvRmDfsRunState_Invalid = 0,
+
+    /// DFS is disabled / not supported (terminal state)
+        NvRmDfsRunState_Disabled = 1,
+
+    /// DFS is stopped - no automatic clock control. Starvation and Busy hints
+    /// are recorded but have no affect.
+        NvRmDfsRunState_Stopped,
+
+    /// DFS is running in closed loop - full automatic control of SoC-wide
+    /// clocks based on clock activity measuremnets. Starvation and Busy hints
+    /// are functional as well.
+        NvRmDfsRunState_ClosedLoop,
+
+    /// DFS is running in closed loop with profiling (can not be set on non
+    /// profiling build).
+        NvRmDfsRunState_ProfiledLoop,
+    NvRmDfsRunState_Num,
+    NvRmDfsRunState_Force32 = 0x7FFFFFFF
+} NvRmDfsRunState;
+
+/**
+ * Defines DFS profile targets
+ */
+
+typedef enum
+{
+
+    /// DFS algorithm within ISR
+        NvRmDfsProfileId_Algorithm = 1,
+
+    /// DFS Interrupt service - includes algorithm plus OS locking and
+    ///  signaling calls; hence, includes blocking time (if any) as well
+        NvRmDfsProfileId_Isr,
+
+    /// DFS clock control time - includes PLL stabilazation time, OS locking
+    /// and signalling calls; hence, includes blocking time (if any) as well 
+        NvRmDfsProfileId_Control,
+    NvRmDfsProfileId_Num,
+    NvRmDfsProfileId_Force32 = 0x7FFFFFFF
+} NvRmDfsProfileId;
+
+/**
+ * Defines voltage rails that are controlled in conjunction with dynamic
+ * frequency scaling.
+ */
+
+typedef enum
+{
+
+    /// SoC core rail
+        NvRmDfsVoltageRailId_Core = 1,
+
+    /// Dedicated CPU rail
+        NvRmDfsVoltageRailId_Cpu,
+    NvRmDfsVoltageRailId_Num,
+    NvRmDfsVoltageRailId_Force32 = 0x7FFFFFFF
+} NvRmDfsVoltageRailId;
+
+/**
+ * Defines busy hint API synchronization modes.
+ */
+
+typedef enum
+{
+
+    /// Asynchronous mode (non-blocking API)
+        NvRmDfsBusyHintSyncMode_Async = 1,
+
+    /// Synchronous mode (blocking API)
+        NvRmDfsBusyHintSyncMode_Sync,
+    NvRmDfsBusyHintSyncMode_Num,
+    NvRmDfsBusyHintSyncMode_Force32 = 0x7FFFFFFF
+} NvRmDfsBusyHintSyncMode;
+
+/**
+ * Holds information on DFS clock domain utilization
+ */
+
+typedef struct NvRmDfsClockUsageRec
+{
+
+    /// Minimum clock domain frequency
+        NvRmFreqKHz MinKHz;
+
+    /// Maximum clock domain frequency
+        NvRmFreqKHz MaxKHz;
+
+    /// Low corner frequency - current low boundary for DFS control algorithm.
+    /// Can be dynamically adjusted via APIs: NvRmDfsSetLowCorner() for all DFS
+    /// domains, NvRmDfsSetCpuEnvelope() for CPU, and NvRmDfsSetEmcEnvelope()
+    /// for EMC. When all DFS domains hit low corner, DFS stops waking up CPU
+    ///  from low power state.
+        NvRmFreqKHz LowCornerKHz;
+
+    /// High corner frequency - current high boundary for DFS control algorithm.
+    /// Can be dynamically adjusted via APIs: NvRmDfsSetCpuEnvelope() for Cpu,
+    /// NvRmDfsSetEmcEnvelope() for Emc, and NvRmDfsSetAvHighCorner() for other
+    //  DFS domains.
+        NvRmFreqKHz HighCornerKHz;
+
+    /// Current clock domain frequency
+        NvRmFreqKHz CurrentKHz;
+
+    /// Average frequency of domain *activity* (not average frequency). For
+    /// domains that do not have activity monitors reported as unspecified.
+        NvRmFreqKHz AverageKHz;
+} NvRmDfsClockUsage;
+
+/**
+ * Holds information on DFS busy hint
+ */
+
+typedef struct NvRmDfsBusyHintRec
+{
+
+    /// Target clock domain ID
+        NvRmDfsClockId ClockId;
+
+    /// Requested boost duration in milliseconds
+        NvU32 BoostDurationMs;
+
+    /// Requested clock frequency level in kHz
+        NvRmFreqKHz BoostKHz;
+
+    /// Busy pulse mode indicator - if true, busy boost is completely removed
+    /// after busy time has expired; if false, DFS will gradually lower domain
+    /// frequency after busy boost.
+        NvBool BusyAttribute;
+} NvRmDfsBusyHint;
+
+/**
+ * Holds information on DFS starvation hint
+ */
+
+typedef struct NvRmDfsStarvationHintRec
+{
+
+    /// Target clock domain ID
+        NvRmDfsClockId ClockId;
+
+    /// The starvation indicator for the target domain
+        NvBool Starving;
+} NvRmDfsStarvationHint;
+
+/**
+ * The NVRM_POWER_CLIENT_TAG macro is used to convert ASCII 4-character codes
+ * into the 32-bit tag that can be used to identify power manager clients for
+ * logging purposes.
+ */
+#define NVRM_POWER_CLIENT_TAG(a,b,c,d) \
+    ((NvU32) ((((a)&0xffUL)<<24UL) |  \
+              (((b)&0xffUL)<<16UL) |  \
+              (((c)&0xffUL)<< 8UL) |  \
+              (((d)&0xffUL))))
+
+/**
+ * Registers RM power client.
+ *
+ * @param hRmDeviceHandle The RM device handle.
+ * @param hEventSemaphore The client semaphore for power management event
+ *  signaling. If null, no events will be signaled to the particular client.
+ * @param pClientId A pointer to the storage that on entry contains client
+ *  tag (optional), and on exit returns client ID, assigned by power manager.
+ *
+ * @retval NvSuccess if registration was successful.
+ * @retval NvError_InsufficientMemory if failed to allocate memory for client
+ *  registration.
+ */
+
+ NvError NvRmPowerRegister( 
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvOsSemaphoreHandle hEventSemaphore,
+    NvU32 * pClientId );
+
+/**
+ * Unregisters RM power client. Power and clock for the modules enabled by this
+ * client are disabled and any starvation or busy requests are cancelled during
+ * the unregistration.
+ *
+ * @param hRmDeviceHandle The RM device handle.
+ * @param ClientId The client ID obtained during registration.
+ */
+
+ void NvRmPowerUnRegister( 
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvU32 ClientId );
+
+/**
+ * Gets last detected and not yet retrieved power management event.
+ * Returns no outstanding event if no events has been detected since the
+ * client registration or the last call to this function.
+ *
+ * @param hRmDeviceHandle The RM device handle.
+ * @param ClientId The client ID obtained during registration.
+ * @param pEvent Output storage pointer for power event identifier.
+ *
+ * @retval NvSuccess if event identifier was retrieved successfully.
+ * @retval NvError_BadValue if specified client ID is not registered.
+ */
+
+ NvError NvRmPowerGetEvent( 
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvU32 ClientId,
+    NvRmPowerEvent * pEvent );
+
+/**
+ * Notifies RM about power management event. Provides an interface for
+ * OS power manager to report system power events to RM.
+ *
+ * @param hRmDeviceHandle The RM device handle.
+ * @param Event The event RM power manager is to be aware of.
+ */
+
+ void NvRmPowerEventNotify( 
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvRmPowerEvent Event );
+
+/**
+ * Gets combined RM clients power state.
+ *
+ * @param hRmDeviceHandle The RM device handle.
+ * @param pState Output storage pointer for combined RM clients power state.
+ *
+ * @retval NvSuccess if power state was retrieved successfully.
+ */
+
+ NvError NvRmPowerGetState( 
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvRmPowerState * pState );
+
+/**
+ * Gets SoC primary oscillator/input frequency.
+ *
+ * @param hRmDeviceHandle The RM device handle.
+ *
+ * @retval Primary frequency in KHz.
+ */
+
+ NvRmFreqKHz NvRmPowerGetPrimaryFrequency( 
+    NvRmDeviceHandle hRmDeviceHandle );
+
+/**
+ * Gets maximum frequency limit for the module clock.
+ *
+ * @param hRmDeviceHandle The RM device handle.
+ * @param ModuleId The combined module ID and instance of the target module.
+ * 
+ * @retval Module clock maximum frequency in KHz.
+ */
+
+ NvRmFreqKHz NvRmPowerModuleGetMaxFrequency( 
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvRmModuleID ModuleId );
+
+/**
+ *  This API is used to set the clock configuration of the module clock.
+ *  This API can also be used to query the existing configuration.
+ * 
+ *  Usage example:
+ * 
+ *  NvError Error;
+ *  NvRmFreqKHz MyFreqKHz = 0;
+ *  ModuleId = NVRM_MODULE_ID(NvRmModuleID_Uart, 0);
+ * 
+ *  // Get current frequency settings
+ *  Error = NvRmPowerModuleClockConfig(RmHandle, ModuleId, ClientId,
+ *                                      0, 0, NULL, 0, &MyFreqKHz, 0);
+ * 
+ * // Set target frequency within HW defined limits
+ * MyFreqKHz = TARGET_FREQ;
+ * Error = NvRmPowerModuleClockConfig(RmHandle, ModuleId, ClientId,
+ *                                    NvRmFreqUnspecified, NvRmFreqUnspecified,
+ *                                    &MyFreqKHz, 1, &MyFreqKHz);
+ * 
+ * @param hRmDeviceHandle The RM device handle.
+ * @param ModuleId The combined module ID and instance of the target module.
+ * @param ClientId The client ID obtained during registration.
+ * @param MinFreq Requested minimum frequency for hardware module operation.
+ *      If the value is NvRmFreqUnspecified, RM uses the the min freq that this
+ *      module can operate. 
+ *      If the value specified is more than the Hw minimum, passed value is used.
+ *      If the value specified is less than the Hw minimum, it will be clipped to
+ *      the HW minimum value.
+ * @param MaxFreq Requested maximum frequency for hardware module operation.
+ *      If the value is NvRmFreqUnspecified, RM uses the the max freq that this
+ *      module can run.
+ *      If the value specified is less than the Hw maximum, that value is used.
+ *      If the value specified is more than the Hw limit, it will be clipped to
+ *      the HW maximum.
+ * @param PrefFreqList Pointer to a list of preferred frequencies, sorted in the
+ *      decresing order of priority. Use NvRmFreqMaximum to request Hw maximum.
+ * @param PrefFreqListCount Number of entries in the PrefFreqList array.
+ * @param CurrentFreq Returns the current clock frequency of that module. NULL
+ *      is a valid value for this parameter.
+ * @param flags Module specific flags. Thse flags are valid only for some
+ *      modules. See @NvRmClockConfigFlags
+ * 
+ * @retval NvSuccess if clock control request completed successfully.
+ * @retval NvError_ModuleNotPresent if the module ID or instance is invalid.
+ * @retval NvError_NotSupported if failed to configure requested frequency (e.g.,
+ *  output frequency for possible divider settings is outside specified range).
+ */
+
+ NvError NvRmPowerModuleClockConfig( 
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvRmModuleID ModuleId,
+    NvU32 ClientId,
+    NvRmFreqKHz MinFreq,
+    NvRmFreqKHz MaxFreq,
+    const NvRmFreqKHz * PrefFreqList,
+    NvU32 PrefFreqListCount,
+    NvRmFreqKHz * CurrentFreq,
+    NvU32 flags );
+
+/**
+ *  This API is used to enable and disable the module clock.
+ *
+ * @param hRmDeviceHandle The RM device handle.
+ * @param ModuleId The combined module ID and instance of the target module.
+ * @param ClientId The client ID obtained during registration.
+ * @param Enable Enables/diables the module clock.
+ * 
+ * @retval NvSuccess if the module is enabled.
+ * @retval NvError_ModuleNotPresent if the module ID or instance is invalid.
+ */
+
+ NvError NvRmPowerModuleClockControl( 
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvRmModuleID ModuleId,
+    NvU32 ClientId,
+    NvBool Enable );
+
+/**
+ * Request the voltage range for a hardware module. As power planes are shared
+ * between different modules, in the majority of cases the RM will choose the
+ * appropriate voltage, and module owners only need to enable or disable power
+ * for a module. Enable request is always completed (i.e., voltage is applied
+ * to the module) before this function returns. Disable request just means that
+ * the client is ready for module power down. Actually the power may be removed
+ * within the call or any time later, depending on other client needs and power
+ * plane dependencies with other modules.
+ * 
+ * Assert encountered in debug mode if the module ID or instance is invalid.
+ *
+ * Usage example:
+ * 
+ * NvError Error;
+ * ModuleId = NVRM_MODULE_ID(NvRmModuleID_Uart, 0);
+ * 
+ * // Enable module power
+ * Error = NvRmPowerVoltageControl(RmHandle, ModuleId, ClientId,
+ *          NvRmVoltsUnspecified, NvRmVoltsUnspecified,
+ *          NULL, 0, NULL);
+ * 
+ * // Disable module power
+ * Error = NvRmPowerVoltageControl(RmHandle, ModuleId, ClientId,
+ *          NvRmVoltsOff, NvRmVoltsOff,
+ *          NULL, 0, NULL);
+ * 
+ * @param hRmDeviceHandle The RM device handle
+ * @param ModuleId The combined module ID and instance of the target module
+ * @param ClientId The client ID obtained during registration
+ * @param MinVolts Requested minimum voltage for hardware module operation
+ * @param MaxVolts Requested maximum voltage for hardware module operation
+ *  Set to NvRmVoltsUnspecified when enabling power for a module, or to
+ *  NvRmVoltsOff when disabling.
+ * @param PrefVoltageList Pointer to a list of preferred voltages, ordered from
+ *  lowest to highest, and terminated with a voltage of NvRmVoltsUnspecified.
+ *  This parameter is optional - ignored if null.
+ * @param PrefVoltageListCount Number of entries in the PrefVoltageList array.
+ * @param CurrentVolts Output storage pointer for resulting module voltage.
+ *  NvRmVoltsUnspecified is returned if module power is On and was not cycled,
+ *   since the last voltage request with the same ClientId and ModuleId;
+ *  NvRmVoltsCycled is returned if module power is On but was powered down,
+ *   since the last voltage request with the same ClientId and ModuleId;
+ *  NvRmVoltsOff  is returned if module power is Off.
+ *  This parameter is optional - ignored  if null.
+ * 
+ * @retval NvSuccess if voltage control request completed successfully.
+ * @retval NvError_BadValue if specified client ID is not registered.
+ * @retval NvError_InsufficientMemory if failed to allocate memory for
+ *  voltage request.
+ */
+
+ NvError NvRmPowerVoltageControl( 
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvRmModuleID ModuleId,
+    NvU32 ClientId,
+    NvRmMilliVolts MinVolts,
+    NvRmMilliVolts MaxVolts,
+    const NvRmMilliVolts * PrefVoltageList,
+    NvU32 PrefVoltageListCount,
+    NvRmMilliVolts * CurrentVolts );
+
+/**
+ * Lists modules registered by power clients for voltage control.
+ * 
+ * @param pListSize Pointer to the list size. On entry specifies list size
+ *  allocated by the caller, on exit - actual number of Ids returned. If
+ *  entry size is 0, maximum list size is returned. 
+ * @param pIdList Pointer to the list of combined module Id/Instance values
+ *  to be filled in by this function. Ignored if input list size is 0.
+ * @param pActiveList Pointer to the list of modules Active attributes
+ *  to be filled in by this function. Ignored if input list size is 0.
+ */                               
+
+ void NvRmListPowerAwareModules( 
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvU32 * pListSize,
+    NvRmModuleID * pIdList,
+    NvBool * pActiveList );
+
+/**
+ * Requests immediate frequency boost for SOC-wide clocks. In general, the RM
+ * DFS manages SOC-wide clocks by measuring the average use of clock cycles,
+ * and adjusting clock rates to minimize wasted clocks. It is preferable and
+ * expected that modules consume clock cycles at a more-or-less constant rate.
+ * Under some circumstances this will not be the case. For example, many cycles
+ * may be consumed to prime a new media processing activity. If power client
+ * anticipates such circumstances, it may sparingly use this API to alert the RM
+ * that a temporary spike in clock usage is about to occur.
+ *
+ * Usage example:
+ * 
+ * // Busy hint for CPU clock
+ * NvError Error;
+ * Error = NvRmPowerBusyHint(RmHandle, NvRmDfsClockId_Cpu, ClientId,
+ *          BoostDurationMs, BoostFreqKHz);
+ *
+ * Clients should not call this API in an attempt to micro-manage a particular
+ * clock frequency as that is the responsibility of the RM.
+ *
+ * @param hRmDeviceHandle The RM device handle.
+ * @param ClockId The DFS ID of the clock targeted by this hint.
+ * @param ClientId The client ID obtained during registration.
+ * @param BoostDurationMs The estimate of the boost duration in milliseconds.
+ *  Use NV_WAIT_INFINITE to specify busy until canceled. Use 0 to request
+ *  instantaneous spike in frequency and let DFS to scale down. 
+ * @param BoostKHz The requirements for the boosted clock frequency in kHz.
+ *  Use NvRmFreqMaximum to request maximum domain frequency. Use 0 to cancel
+ *  all busy hints reported by the specified client for the specified domain.
+ *
+ * @retval NvSuccess if busy request completed successfully.
+ * @retval NvError_BadValue if specified client ID is not registered.
+ * @retval NvError_InsufficientMemory if failed to allocate memory for
+ *  busy hint.
+ */
+
+ NvError NvRmPowerBusyHint( 
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvRmDfsClockId ClockId,
+    NvU32 ClientId,
+    NvU32 BoostDurationMs,
+    NvRmFreqKHz BoostKHz );
+
+/**
+ * Requests immediate frequency boost for multiple SOC-wide clock domains. 
+ * @sa NvRmPowerBusyHint() for detailed explanation of busy hint effects. 
+ *
+ * @param hRmDeviceHandle The RM device handle.
+ * @param ClientId The client ID obtained during registration.
+ * @param pMultiHint Pointer to a list of busy hint records for
+ *  targeted clocks.
+ * @param NumHints Number of entries in pMultiHint array.
+ * @param Mode Synchronization mode. In asynchronous mode this API returns to
+ *  the caller after request is signaled to power manager (non-blocking call).
+ *  In synchronous mode the API returns after busy hints are processed by power
+ *  manager (blocking call).
+ * 
+ * @note It is recommended to use synchronous mode only when low frequency
+ *  may result in functional failure. Otherwise, use asynchronous mode or
+ *  NvRmPowerBusyHint API, which is always executed as non-blocking request.
+ *  Synchronous mode must not be used by PMU transport.
+ * 
+ *
+ * @retval NvSuccess if busy hint request completed successfully.
+ * @retval NvError_BadValue if specified client ID is not registered.
+ * @retval NvError_InsufficientMemory if failed to allocate memory for
+ *  busy hints.
+ */
+
+ NvError NvRmPowerBusyHintMulti( 
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvU32 ClientId,
+    const NvRmDfsBusyHint * pMultiHint,
+    NvU32 NumHints,
+    NvRmDfsBusyHintSyncMode Mode );
+
+/**
+ * Request frequency increase for SOC-wide clock to avoid real-time starvation
+ * conditions. Allows modules to contribute to the detection and avoidance of
+ * clock starvation for DFS controlled clocks.
+ * 
+ * This API should be called to indicate starvation threat and also to cancel
+ * request when a starvation condition has eased.
+ * 
+ * @note Although the RM DFS does its best to manage clocks without starving
+ * the system for clock cycles, bursty clock usage can occasionally cause
+ * short-term clock starvation. One solution is to leave a large enough clock
+ * rate guard band such that any possible burst in clock usage will be absorbed.
+ * This approach tends to waste clock cycles, and worsen power management.
+ * 
+ * By allowing power clients to participate in the avoidance of system clock
+ * starvation situations, detection responsibility can be moved closer to the
+ * hardware buffers and processors where starvation occurs, while leaving the
+ * overall dynamic clocking policy to the RM. A typical client would be a module
+ * that manages media processing and is able to determine when it is falling
+ * behind by watching buffer levels or some other module-specific indicator. In
+ * response to the starvation request the RM increases gradually the respective
+ * clock frequency until the request vis cancelled by the client.
+ * 
+ * Usage example:
+ * 
+ * NvError Error;
+ * 
+ * // Request CPU clock frequency increase to avoid starvation
+ * Error = NvRmPowerStarvationHint(
+ *          RmHandle, NvRmDfsClockId_Cpu, ClientId, NV_TRUE);
+ * 
+ * // Cancel starvation request for CPU clock frequency
+ * Error = NvRmPowerStarvationHint(
+ *          RmHandle, NvRmDfsClockId_Cpu, ClientId, NV_FALSE);
+ * 
+ * @param hRmDeviceHandle The RM device handle.
+ * @param ClockId The DFS ID of the clock targeted by this hint.
+ * @param ClientId The client ID obtained during registration.
+ * @param Starving The starvation indicator for the target module. If true,
+ *  the client is requesting target frequency increase to avoid starvation
+ *  If false, the indication is that the imminent starvation is no longer a
+ *  concern for this particular client.
+ * 
+ * @retval NvSuccess if starvation request completed successfully.
+ * @retval NvError_BadValue if specified client ID is not registered.
+ * @retval NvError_InsufficientMemory if failed to allocate memory for
+ *  starvation hint.
+ */
+
+ NvError NvRmPowerStarvationHint( 
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvRmDfsClockId ClockId,
+    NvU32 ClientId,
+    NvBool Starving );
+
+/**
+ * Request frequency increase for multiple SOC-wide clock domains to avoid
+ * real-time starvation conditions.
+ * @sa NvRmPowerStarvationHint() for detailed explanation of starvation hint
+ * effects.
+ *
+ * @param hRmDeviceHandle The RM device handle.
+ * @param ClientId The client ID obtained during registration.
+ * @param pMultiHint Pointer to a list of starvation hint records for
+ *  targeted clocks.
+ * @param NumHints Number of entries in pMultiHint array.
+ *
+ * @retval NvSuccess if starvation hint request completed successfully.
+ * @retval NvError_BadValue if specified client ID is not registered.
+ * @retval NvError_InsufficientMemory if failed to allocate memory for
+ *  starvation hints.
+ */
+
+ NvError NvRmPowerStarvationHintMulti( 
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvU32 ClientId,
+    const NvRmDfsStarvationHint * pMultiHint,
+    NvU32 NumHints );
+
+/**
+ * Notifies the RM about DDK module activity.
+ * 
+ * @note This function lets DDK modules notify the RM about interesting system
+ * activities. Not all modules will need to make this indication, typically only
+ * modules involved in user input or output activities. However, with current
+ * SOC power management architecture such activities will be detected by the OS
+ * adaptation layer, not RM. This API is not removed, just in case, we will find
+ * out that RM still need to participate in user activity detection. In general,
+ * modules should call this interface sparingly, no more than once every few
+ * seconds.
+ * 
+ * In current power management architecture user activity is handled by OS
+ * (nor RM) power manager, and activity API is not used at all.
+ * 
+ * Assert encountered in debug mode if the module ID or instance is invalid.
+ *
+ * TODO: Remove this API?
+ *
+ * @param hRmDeviceHandle The RM device handle.
+ * @param ModuleId The combined module ID and instance of the target module.
+ * @param ClientId The client ID obtained during registration.
+ * @param ActivityDurationMs The duration of the module activity.
+ * 
+ * For cases when activity is a series of discontinuous events (keypresses, for
+ * example), this parameter should simply be set to 1.
+ * 
+ * For lengthy, continuous activities, this parameter is set to the estimated
+ * length of the activity in milliseconds. This can reduce the number of calls
+ * made to this API.
+ * 
+ * A value of 0 in this parameter indicates that the module is not active and
+ * can be used to signal the end of a previously estimated continuous activity.
+ * 
+ * @retval NvSuccess if clock control request completed successfully.
+ */
+
+ NvError NvRmPowerActivityHint( 
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvRmModuleID ModuleId,
+    NvU32 ClientId,
+    NvU32 ActivityDurationMs );
+
+/**
+ * Gets DFS run sate.
+ * 
+ * @param hRmDeviceHandle The RM device handle.
+ * 
+ * @return Current DFS run state.
+ */
+
+ NvRmDfsRunState NvRmDfsGetState( 
+    NvRmDeviceHandle hRmDeviceHandle );
+
+/**
+ * Gets information on DFS controlled clock utilization. If DFS is stopped
+ * or disabled the average frequency is always equal to current frequency.
+ * 
+ * @param hRmDeviceHandle The RM device handle.
+ * @param ClockId The DFS ID of the clock targeted by this request.
+ * @param pClockInfo Output storage pointer for clock utilization information.
+ * 
+ * @return NvSuccess if clock usage information is returned successfully.
+ */
+
+ NvError NvRmDfsGetClockUtilization( 
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvRmDfsClockId ClockId,
+    NvRmDfsClockUsage * pClockUsage );
+
+/**
+ * Sets DFS run state. Allows to stop or re-start DFS as well as switch
+ * between open and closed loop operations.
+ * 
+ * On transition to the DFS stopped state, the DFS clocks are just kept at
+ * current frequencies. On transition to DFS run states, DFS sampling data
+ * is re-initialized only if originally DFS was stopped. Transition between
+ * running states has no additional effects, besides operation mode changes.
+ * 
+ * @param hRmDeviceHandle The RM device handle.
+ * @param NewDfsRunState The DFS run state to be set.
+ * 
+ * @retval NvSuccess if DFS state was set successfully.
+ * @retval NvError_NotSupported if DFS was disabled initially, in attempt
+ * to disable initially enabled DFS, or in attempt to run profiled loop
+ * on non profiling build.
+ */
+
+ NvError NvRmDfsSetState( 
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvRmDfsRunState NewDfsRunState );
+
+/**
+ * Sets DFS low corner frequencies - low boundaries for DFS clocks when DFS.
+ * is running. If all DFS domains hit low corner, DFS will no longer wake
+ * CPU from low power state.  
+ *
+ * @note When CPU envelope is set via NvRmDfsSetCpuEnvelope() API the CPU
+ *  low corner boundary can not be changed by this function.
+ * @note When EMC envelope is set via NvRmDfsSetEmcEnvelope() API the EMC
+ *  low corner boundary can not be changed by this function.
+ * 
+ * Usage example:
+ * 
+ * NvError Error;
+ * NvRmFreqKHz LowCorner[NvRmDfsClockId_Num];
+ * 
+ * // Fill in low corner array
+ * LowCorner[NvRmDfsClockId_Cpu] = NvRmFreqUnspecified;
+ * LowCorner[NvRmDfsClockId_Avp] = ... ;
+ * LowCorner[NvRmDfsClockId_System] = ...;
+ * LowCorner[NvRmDfsClockId_Ahb] = ...;
+ * LowCorner[NvRmDfsClockId_Apb] = ...;
+ * LowCorner[NvRmDfsClockId_Vpipe] = ...;
+ * LowCorner[NvRmDfsClockId_Emc] = ...;
+ * 
+ * // Set new low corner for domains other than CPU, and preserve CPU boundary
+ * Error = NvRmDfsSetLowCorner(RmHandle, NvRmDfsClockId_Num, LowCorner);
+ * 
+ * @param hRmDeviceHandle The RM device handle.
+ * @param DfsFreqListCount Number of entries in the pDfsLowFreqList array.
+ *  Must be always equal to NvRmDfsClockId_Num.
+ * @param pDfsLowFreqList Pointer to a list of low corner frequencies, ordered
+ *  according to NvRmDfsClockId enumeration. If the list entry is set to
+ *  NvRmFreqUnspecified, the respective low corner boundary is not modified.
+ * 
+ * @retval NvSuccess if low corner frequencies were updated successfully.
+ * @retval NvError_NotSupported if DFS is disabled.
+ */
+
+ NvError NvRmDfsSetLowCorner( 
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvU32 DfsFreqListCount,
+    const NvRmFreqKHz * pDfsLowFreqList );
+
+/**
+ * Sets DFS target frequencies. If DFS is stopped clocks for the DFS domains
+ * will be targeted with the specified frequencies. In any other DFS state
+ * this function has no effect.
+ *
+ * Usage example:
+ * 
+ * NvError Error;
+ * NvRmFreqKHz Target[NvRmDfsClockId_Num];
+ * 
+ * // Fill in target frequencies array
+ * Target[NvRmDfsClockId_Cpu] = ... ;
+ * Target[NvRmDfsClockId_Avp] = ... ;
+ * Target[NvRmDfsClockId_System] = ...;
+ * Target[NvRmDfsClockId_Ahb] = ...;
+ * Target[NvRmDfsClockId_Apb] = ...;
+ * Target[NvRmDfsClockId_Vpipe] = ...;
+ * Target[NvRmDfsClockId_Emc] = ...;
+ * 
+ * // Set new target
+ * Error = NvRmDfsSetTarget(RmHandle, NvRmDfsClockId_Num, Target);
+ * 
+ * @param hRmDeviceHandle The RM device handle.
+ * @param DfsFreqListCount Number of entries in the pDfsTargetFreqList array.
+ *  Must be always equal to NvRmDfsClockId_Num.
+ * @param pDfsTargetFreqList Pointer to a list of target frequencies, ordered
+ *  according to NvRmDfsClockId enumeration. If the list entry is set to
+ *  NvRmFreqUnspecified, the current domain frequency is used as a target.
+ * 
+ * @retval NvSuccess if target frequencies were updated successfully.
+ * @retval NvError_NotSupported if DFS is not stopped (disabled, or running).
+ */
+
+ NvError NvRmDfsSetTarget( 
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvU32 DfsFreqListCount,
+    const NvRmFreqKHz * pDfsTargetFreqList );
+
+/**
+ * Sets DFS high and low boundaries for CPU domain clock frequency.
+ * 
+ * Usage example:
+ *
+ * NvError Error;
+ * 
+ * // Set CPU envelope boundaries to LowKHz : HighKHz
+ * Error = NvRmDfsSetCpuEnvelope(RmHandle, LowKHz, HighKHz);
+ * 
+ * // Change CPU envelope high boundary to HighKHz
+ * Error = NvRmDfsSetCpuEnvelope(RmHandle, NvRmFreqUnspecified, HighKHz);
+ *
+ * // Release CPU envelope back to HW limits
+ * Error = NvRmDfsSetCpuEnvelope(RmHandle, 0, NvRmFreqMaximum);
+ *
+ * @param hRmDeviceHandle The RM device handle.
+ * @param DfsCpuEnvelopeLowKHz Requested low boundary in kHz.
+ * @param DfsCpuEnvelopeHighKHz Requested high limit in kHz.
+ * 
+ * Envelope parameters are clipped to the HW defined CPU domain range.
+ * If envelope parameter is set to NvRmFreqUnspecified, the respective
+ * CPU boundary is not modified, unless it violates the new setting for
+ * the other boundary; in the latter case both boundaries are set to the
+ * new specified value.
+ * 
+ * @retval NvSuccess if DFS envelope for for CPU domain was updated
+ *  successfully.
+ * @retval NvError_BadValue if reversed boundaries are specified.
+ * @retval NvError_NotSupported if DFS is disabled.
+ */
+
+ NvError NvRmDfsSetCpuEnvelope( 
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvRmFreqKHz DfsCpuLowCornerKHz,
+    NvRmFreqKHz DfsCpuHighCornerKHz );
+
+/**
+ * Sets DFS high and low boundaries for EMC domain clock frequency.
+ * 
+ * Usage example:
+ *
+ * NvError Error;
+ * 
+ * // Set EMC envelope boundaries to LowKHz : HighKHz
+ * Error = NvRmDfsSetEmcEnvelope(RmHandle, LowKHz, HighKHz);
+ * 
+ * // Change EMC envelope high boundary to HighKHz
+ * Error = NvRmDfsSetEmcEnvelope(RmHandle, NvRmFreqUnspecified, HighKHz);
+ *
+ * // Release EMC envelope back to HW limits
+ * Error = NvRmDfsSetEmcEnvelope(RmHandle, 0, NvRmFreqMaximum);
+ *
+ * @param hRmDeviceHandle The RM device handle.
+ * @param DfsEmcEnvelopeLowKHz Requested low boundary in kHz.
+ * @param DfsEmcEnvelopeHighKHz Requested high limit in kHz.
+ * 
+ * Envelope parameters are clipped to the ODM defined EMC configurations
+ * within HW defined EMC domain range. If envelope parameter is set to
+ * NvRmFreqUnspecified, the respective EMC boundary is not modified, unless
+ * it violates the new setting for the other boundary; in the latter case
+ * both boundaries are set to the new specified value.
+ * 
+ * @retval NvSuccess if DFS envelope for for EMC domain was updated
+ *  successfully.
+ * @retval NvError_BadValue if reversed boundaries are specified.
+ * @retval NvError_NotSupported if DFS is disabled.
+ */
+
+ NvError NvRmDfsSetEmcEnvelope( 
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvRmFreqKHz DfsEmcLowCornerKHz,
+    NvRmFreqKHz DfsEmcHighCornerKHz );
+
+/**
+ * Sets DFS high boundaries for CPU and EMC.
+ * 
+ * @note When either CPU or EMC envelope is set via NvRmDfsSetXxxEnvelope()
+ * API, neither CPU nor EMC boundary is changed by this function.
+ * 
+ * Usage example:
+ *
+ * NvError Error;
+ * 
+ * // Set CPU subsystem clock limit to CpuHighKHz and Emc clock limit
+ * // to EmcHighKHz
+ * Error = NvRmDfsSetCpuEmcHighCorner(RmHandle, CpuHighKHz, EmcHighKHz);
+ * 
+ * @param hRmDeviceHandle The RM device handle.
+ * @param DfsCpuHighKHz Requested high boundary in kHz for CPU.
+ * @param DfsEmcHighKHz Requested high limit in kHz for EMC.
+ * 
+ * Requested parameters are clipped to the respective HW defined domain
+ * ranges, as well as to ODM defined EMC configurations. If any parameter
+ * is set to NvRmFreqUnspecified, the respective boundary is not modified.
+ * 
+ * @retval NvSuccess if high corner for AV subsystem was updated successfully.
+ * @retval NvError_NotSupported if DFS is disabled.
+ */
+
+ NvError NvRmDfsSetCpuEmcHighCorner( 
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvRmFreqKHz DfsCpuHighKHz,
+    NvRmFreqKHz DfsEmcHighKHz );
+
+/**
+ * Sets DFS high boundaries for AV subsystem clocks.
+ * 
+ * Usage example:
+ *
+ * NvError Error;
+ * 
+ * // Set AVP clock limit to AvpHighKHz, Vde clock limit to VpipeHighKHz,
+ * // and preserve System bus clock limit provided it is above requested
+ * // AVP and Vpipe levels.
+ * Error = NvRmDfsSetAvHighCorner(
+ *          RmHandle, NvRmFreqUnspecified, AvpHighKHz, VpipeHighKHz);
+ * 
+ *@note System bus clock limit must be always above AvpHighKHz, and above
+ * VpipeHighKHz. Therefore it may be adjusted up, as a result of this call,
+ * even though, it is marked unspecified.
+ * 
+ * @param hRmDeviceHandle The RM device handle.
+ * @param DfsSysHighKHz Requested high boundary in kHz for System bus.
+ * @param DfsAvpHighKHz Requested high boundary in kHz for AVP.
+ * @param DfsVdeHighCornerKHz Requested high limit in kHz for Vde pipe.
+ * 
+ * Requested parameter is clipped to the respective HW defined domain
+ * range. If  parameter is set to NvRmFreqUnspecified, the respective
+ * boundary is not modified.
+ * 
+ * @retval NvSuccess if high corner for AV subsystem was updated successfully.
+ * @retval NvError_NotSupported if DFS is disabled.
+ */
+
+ NvError NvRmDfsSetAvHighCorner( 
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvRmFreqKHz DfsSystemHighKHz,
+    NvRmFreqKHz DfsAvpHighKHz,
+    NvRmFreqKHz DfsVpipeHighKHz );
+
+/**
+ * Gets DFS profiling information.
+ * 
+ * DFS profiling starts/re-starts every time NvRmDfsRunState_ProfiledLoop
+ * state is set via NvRmDfsSetState(). DFS profiling stops when any other
+ * sate is set.
+ * 
+ * @param hRmDeviceHandle The RM device handle.
+ * @param DfsProfileCount Number of DFS profiles. Must be always equal to
+ *  NvRmDfsProfileId_Num.
+ * @param pSamplesNoList Output storage pointer to an array of sample counts
+ *  for each profile target ordered according to NvRmDfsProfileId enumeration.
+ * @param pProfileTimeUsList Output storage pointer to an array of cummulative
+ *  execution time in microseconds for each profile target ordered according
+ *  to NvRmDfsProfileId enumeration.
+ * @param pDfsPeriodUs Output storage pointer for average DFS sample
+ *  period in microseconds.
+ * 
+ * @retval NvSuccess if profile information is returned successfully.
+ * @retval NvError_NotSupported if DFS is not ruuning in profiled loop.
+ */
+
+ NvError NvRmDfsGetProfileData( 
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvU32 DfsProfileCount,
+    NvU32 * pSamplesNoList,
+    NvU32 * pProfileTimeUsList,
+    NvU32 * pDfsPeriodUs );
+
+/**
+ * Starts/Re-starts NV DFS logging.
+ * 
+ * @param hRmDeviceHandle The RM device handle.
+ */
+
+ void NvRmDfsLogStart( 
+    NvRmDeviceHandle hRmDeviceHandle );
+
+/**
+ * Stops DFS logging and gets cumulative mean values of DFS domains frequencies
+ *  over logging time.
+ *
+ * @param hRmDeviceHandle The RM device handle.
+ * @param LogMeanFreqListCount Number of entries in the pLogMeanFreqList array.
+ *  Must be always equal to NvRmDfsClockId_Num.
+ * @param pLogMeanFreqList Pointer to a list filled with mean values of DFS
+ *  frequencies, ordered according to NvRmDfsClockId enumeration.
+ * @param pLogLp2TimeMs Pointer to a variable filled with cumulative time spent
+ *  in LP2 in milliseconds.
+ * @param pLogLp2Entries Pointer to a variable filled with cumulative number of
+ *  LP2 mode entries.
+ * 
+ * @retval NvSuccess if mean values are returned successfully.
+ * @retval NvError_NotSupported if DFS is disabled.
+ */
+
+ NvError NvRmDfsLogGetMeanFrequencies( 
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvU32 LogMeanFreqListCount,
+    NvRmFreqKHz * pLogMeanFreqList,
+    NvU32 * pLogLp2TimeMs,
+    NvU32 * pLogLp2Entries );
+
+/**
+ * Gets specified entry of the detailed DFS activity log.
+ *
+ * @param hRmDeviceHandle The RM device handle.
+ * @param EntryIndex Log entrty index.
+ * @param LogDomainsCount The size of activity arrays.
+ *  Must be always equal to NvRmDfsClockId_Num.
+ * @param pIntervalMs Pointer to a variable filled with sample interval time
+ *  in milliseconds.
+ * @param pLp2TimeMs Pointer to a variable filled with time spent in LP2
+ *  in milliseconds.
+ * @param pActiveCyclesList Pointer to a list filled with domain active cycles
+ *  within sample interval.
+ * @param pAveragesList Pointer to a list filled with average domain activity
+ *  over DFS moving window.
+ * @param pFrequenciesList Pointer to a list filled with instantaneous domains
+ *  frequencies.
+ *  All lists are ordered according to NvRmDfsClockId enumeration.
+ * 
+ * @retval NvSuccess if log entry is retrieved successfully.
+ * @retval NvError_InvalidAddress if requetsed entry is empty.
+ * @retval NvError_NotSupported if DFS is disabled, or detailed logging
+ *  is not supported.
+ */
+
+ NvError NvRmDfsLogActivityGetEntry( 
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvU32 EntryIndex,
+    NvU32 LogDomainsCount,
+    NvU32 * pIntervalMs,
+    NvU32 * pLp2TimeMs,
+    NvU32 * pActiveCyclesList,
+    NvRmFreqKHz * pAveragesList,
+    NvRmFreqKHz * pFrequenciesList );
+
+/**
+ * Gets specified entry of the detailed DFS starvation hints log.
+ *
+ * @param hRmDeviceHandle The RM device handle.
+ * @param EntryIndex Log entrty index.
+ * @param pSampleIndex Pointer to a variable filled with sample interval
+ *  index in the activity log when this hint is associated with.
+ * @param pStarvationHint Pointer to a variable filled with starvation
+ *  hint record.
+ * 
+ * @retval NvSuccess if next entry is retrieved successfully.
+ * @retval NvError_InvalidAddress if requetsed entry is empty.
+ * @retval NvError_NotSupported if DFS is disabled, or detailed logging
+ *  is not supported.
+ */
+
+ NvError NvRmDfsLogStarvationGetEntry( 
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvU32 EntryIndex,
+    NvU32 * pSampleIndex,
+    NvU32 * pClientId,
+    NvU32 * pClientTag,
+    NvRmDfsStarvationHint * pStarvationHint );
+
+/**
+ * Gets specified entry of the detailed DFS busy hints log.
+ *
+ * @param hRmDeviceHandle The RM device handle.
+ * @param EntryIndex Log entrty index.
+ * @param pSampleIndex Pointer to a variable filled with sample interval
+ *  index in the activity log when this hint is associated with.
+ * @param pBusyHint Pointer to a variable filled with busy
+ *  hint record.
+ * 
+ * @retval NvSuccess if next entry is retrieved successfully.
+ * @retval NvError_InvalidAddress if requetsed entry is empty.
+ * @retval NvError_NotSupported if DFS is disabled, or detailed logging
+ *  is not supported.
+ */
+
+ NvError NvRmDfsLogBusyGetEntry( 
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvU32 EntryIndex,
+    NvU32 * pSampleIndex,
+    NvU32 * pClientId,
+    NvU32 * pClientTag,
+    NvRmDfsBusyHint * pBusyHint );
+
+/**
+ * Gets low threshold and present voltage on the given rail.
+ * 
+ * @param hRmDeviceHandle The RM device handle.
+ * @param RailId The targeted voltage rail ID.
+ * @param pLowMv Output storage pointer for low voltage threshold (in 
+ *  millivolt). NvRmVoltsUnspecified is returned if targeted rail does
+ *  not exist on SoC.
+ * @param pPresentMv Output storage pointer for present rail voltage (in 
+ *  millivolt). NvRmVoltsUnspecified is returned if targeted rail does
+ *  not exist on SoC.
+ */
+
+ void NvRmDfsGetLowVoltageThreshold( 
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvRmDfsVoltageRailId RailId,
+    NvRmMilliVolts * pLowMv,
+    NvRmMilliVolts * pPresentMv );
+
+/**
+ * Sets low threshold for the given rail. The actual rail voltage is scaled
+ *  to match SoC clock frequencies, but not below the specified threshold.
+ * 
+ * @param hRmDeviceHandle The RM device handle.
+ * @param RailId The targeted voltage rail ID.
+ * @param LowMv Low voltage threshold (in millivolts) for the targeted rail.
+ *  Ignored if targeted rail does not exist on SoC.
+ */
+
+ void NvRmDfsSetLowVoltageThreshold( 
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvRmDfsVoltageRailId RailId,
+    NvRmMilliVolts LowMv );
+
+/**
+ * Notifies RM Kernel about entering Suspend state.
+ * 
+ * @param hRmDeviceHandle The RM device handle.
+ *
+ * @retval NvSuccess if notifying RM entering Suspend state successfully.
+ */
+
+ NvError NvRmKernelPowerSuspend( 
+    NvRmDeviceHandle hRmDeviceHandle );
+
+/**
+ * Notifies RM kernel about entering Resume state.
+ * 
+ * @param hRmDeviceHandle The RM device handle.
+ *
+ * @retval NvSuccess if notifying RM entering Resume state successfully.
+ */
+
+ NvError NvRmKernelPowerResume( 
+    NvRmDeviceHandle hRmDeviceHandle );
+
+/** @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif
diff --git a/arch/arm/mach-tegra/include/nvrm_power_private.h b/arch/arm/mach-tegra/include/nvrm_power_private.h
new file mode 100644
index 000000000000..f4adaa0c64ca
--- /dev/null
+++ b/arch/arm/mach-tegra/include/nvrm_power_private.h
@@ -0,0 +1,597 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_NVRM_POWER_PRIVATE_H
+#define INCLUDED_NVRM_POWER_PRIVATE_H
+
+#include "nvrm_power.h"
+#include "nvodm_query.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif  /* __cplusplus */
+
+// Power detect cell stabilization delay
+#define NVRM_PWR_DET_DELAY_US (3)
+
+// Minimum DFS clock domain busy time and busy hints list purge time
+#define NVRM_DFS_BUSY_MIN_MS (10)
+#define NVRM_DFS_BUSY_PURGE_MS (500)
+
+// Temporary definitions for AP20 bring up
+#define NVRM_POWER_AP20_BRINGUP_RETURN(hRm, cond) \
+    if (((hRm)->ChipId.Id == 0x20) && ((cond))) \
+        return
+
+/**
+ * Defines the DFS status flags used by OS kernel to configure SoC for
+ * low power state (multiple flags can be OR'ed).
+ */
+typedef enum
+{
+    // Pause DFS during low power state
+    NvRmDfsStatusFlags_Pause = 0x01,
+
+    // Stop PLL during low power state
+    NvRmDfsStatusFlags_StopPllM0 = 0x02,
+    NvRmDfsStatusFlags_StopPllC0 = 0x04,
+    NvRmDfsStatusFlags_StopPllP0 = 0x08,
+    NvRmDfsStatusFlags_StopPllA0 = 0x10,
+    NvRmDfsStatusFlags_StopPllD0 = 0x20,
+    NvRmDfsStatusFlags_StopPllU0 = 0x40,
+    NvRmDfsStatusFlags_StopPllX0 = 0x80,
+
+    NvRmDfsStatusFlags_Force32 = 0x7FFFFFFF
+} NvRmDfsStatusFlags;
+
+// Defines maximum number of CPUs (must be power of 2)
+#define NVRM_MAX_NUM_CPU_LOG2 (8)
+
+/**
+ * Defines RM power manager requests to OS kernel
+ */
+typedef enum
+{
+    NvRmPmRequest_None = 0,
+
+    // The CPU number is interpreted based on the request flag it is
+    // combined (ORed) with
+    NvRmPmRequest_CpuNumMask = (0x1 << NVRM_MAX_NUM_CPU_LOG2) - 1,
+
+    // Request to abort RM power manager (CPU number is ignored)
+    NvRmPmRequest_ExitFlag,
+
+    // Request to turn On/Off CPU (CPU number specifies target
+    // CPU within current CPU cluster)
+    NvRmPmRequest_CpuOnFlag = NvRmPmRequest_ExitFlag << 1,
+    NvRmPmRequest_CpuOffFlag = NvRmPmRequest_CpuOnFlag << 1,
+
+    // Request to switch between CPU clusters (CPU number specifies target
+    // CPU cluster)
+    NvRmPmRequest_CpuClusterSwitchFlag = NvRmPmRequest_CpuOffFlag << 1,
+
+    NvRmPmRequest_Force32 = 0x7FFFFFFF
+} NvRmPmRequest;
+
+/**
+ * NVRM PM function called within OS shim high priority thread
+ */
+NvRmPmRequest NvRmPrivPmThread(void);
+
+/**
+ * Sets combined RM clients power state in the storage shared with OS
+ * adaptation layer (OAL). While the system is running RM power manger
+ * calls this function to specify idle or active state based on client
+ * requests. On entry to system low power state OAL calls this function
+ * to store the respective LPx id.
+ *
+ * @param hRmDeviceHandle The RM device handle
+ * @param RmState The overall power state to be set
+ */
+void
+NvRmPrivPowerSetState(
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvRmPowerState RmState);
+
+/**
+ * Reads combined RM clients power state from the storage shared with OS
+ * adaptation layer (OAL). While the system is running both RM and OAL may
+ * call this function to read the power state. On exit from the system low
+ * power state OAL uses this function to find out which LPx state is exited.
+ *
+ * @param hRmDeviceHandle The RM device handle
+ *
+ * @return RM power state
+ */
+NvRmPowerState
+NvRmPrivPowerGetState(NvRmDeviceHandle hRmDeviceHandle);
+
+/**
+ * Updates DFS pause flag in the storage shared by RM and NV boot loader
+ *
+ * @param hRmDeviceHandle The RM device handle
+ * @param Pause If NV_TRUE, set DFS pause flag,
+ *  if NV_FALSE, clear DFS pause flag
+ *
+ */
+void
+NvRmPrivUpdateDfsPauseFlag(
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvBool Pause);
+
+/**
+ * Reads DFS status flags from the storage shared by RM and NV boot loader.
+ *
+ * @param hRmDeviceHandle The RM device handle
+ *
+ * @return DFS status flags as defined @NvRmDfsStatusFlags
+ */
+NvU32
+NvRmPrivGetDfsFlags(NvRmDeviceHandle hRmDeviceHandle);
+
+/**
+ * Sets download transport in the storage shared by RM and NV boot loader
+ *
+ * @param hRmDeviceHandle The RM device handle
+ * @param Transport current download transport (NvOdmDownloadTransport_None
+ *  if no transport or it is not active)
+ */
+void
+NvRmPrivSetDownloadTransport(
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvOdmDownloadTransport Transport);
+
+/**
+ * Reads download transport from the storage shared by RM and NV boot loader.
+ *
+ * @param hRmDeviceHandle The RM device handle
+ *
+ * @return current download transport (NvOdmDownloadTransport_None
+ *  if no transport or it is not active)
+ */
+NvOdmDownloadTransport
+NvRmPrivGetDownloadTransport(NvRmDeviceHandle hRmDeviceHandle);
+
+/**
+ * Save LP2 time in the storage shared by RM and NV boot loader.
+ *
+ * @param hRmDeviceHandle The RM device handle
+ * @param TimeUS Time in microseconds CPU was in LP2 state (power gated)
+ */
+void
+NvRmPrivSetLp2TimeUS(
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvU32 TimeUS);
+
+/**
+ * Reads LP2 time from the storage shared by RM and NV boot loader.
+ *
+ * @param hRmDeviceHandle The RM device handle
+ *
+ * @return Time in microseconds CPU was in LP2 state (power gated)
+ */
+NvU32
+NvRmPrivGetLp2TimeUS(NvRmDeviceHandle hRmDeviceHandle);
+
+/**
+ * Initializes RM access to the storage shared by RM and NV boot loader
+ *
+ * @param hRmDeviceHandle The RM device handle
+ *
+ * @return NvSuccess if initialization completed successfully
+ * or one of common error codes on failure
+ */
+NvError NvRmPrivOalIntfInit(NvRmDeviceHandle hRmDeviceHandle);
+
+/**
+ * Deinitializes RM access to the storage shared by RM and NV boot loader
+ *
+ * @param hRmDeviceHandle The RM device handle
+ */
+void NvRmPrivOalIntfDeinit(NvRmDeviceHandle hRmDeviceHandle);
+
+/**
+ * Initializes RM DFS manager
+ *
+ * @param hRmDeviceHandle The RM device handle
+ *
+ * @return NvSuccess if initialization completed successfully
+ * or one of common error codes on failure
+ */
+NvError NvRmPrivDfsInit(NvRmDeviceHandle hRmDeviceHandle);
+
+/**
+ * Deinitializes RM DFS manager
+ *
+ * @param hRmDeviceHandle The RM device handle
+ */
+void NvRmPrivDfsDeinit(NvRmDeviceHandle hRmDeviceHandle);
+
+/**
+ * Initializes RM DTT manager
+ *
+ * @param hRmDeviceHandle The RM device handle
+ */
+void NvRmPrivDttInit(NvRmDeviceHandle hRmDeviceHandle);
+
+/**
+ * Deinitializes RM DTT manager
+ */
+void NvRmPrivDttDeinit(void);
+
+/**
+ * Initializes RM power manager
+ *
+ * @param hRmDeviceHandle The RM device handle
+ *
+ * @return NvSuccess if initialization completed successfully
+ * or one of common error codes on failure
+ */
+NvError
+NvRmPrivPowerInit(NvRmDeviceHandle hRmDeviceHandle);
+
+/**
+ * Deinitializes RM power manager
+ *
+ * @param hRmDeviceHandle The RM device handle
+ */
+void
+NvRmPrivPowerDeinit(NvRmDeviceHandle hRmDeviceHandle);
+
+/**
+ * Initializes IO power rails control
+ *
+ * @param hRmDeviceHandle The RM device handle
+ */
+void NvRmPrivIoPowerControlInit(NvRmDeviceHandle hRmDeviceHandle);
+
+/**
+ * Starts IO power rails level detection
+ *
+ * @param hRmDeviceHandle The RM device handle
+ * @param PwrDetMask The bit mask of power detection cells to be activated
+ */
+void NvRmPrivIoPowerDetectStart(
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvU32 PwrDetMask);
+
+/**
+ * Resets enabled power detect cells (chip-specific).
+ *
+ * @param hRmDeviceHandle The RM device handle
+ */
+void NvRmPrivAp15IoPowerDetectReset(NvRmDeviceHandle hRmDeviceHandle);
+void NvRmPrivAp20IoPowerDetectReset(NvRmDeviceHandle hRmDeviceHandle);
+
+/**
+ * Latches the results of IO power rails level detection
+ *
+ * @param hRmDeviceHandle The RM device handle
+ */
+void NvRmPrivIoPowerDetectLatch(NvRmDeviceHandle hRmDeviceHandle);
+
+/**
+ * Enables/Disables IO pads on specified power rails
+ *
+ * @param hRmDeviceHandle The RM device handle
+ * @param NoIoPwrMask Bit mask of affected power rails
+ * @param Enable Set NV_TRUE to enable IO pads, or NV_FALSE to disable.
+ */
+void NvRmPrivIoPowerControl(
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvU32 NoIoPwrMask,
+    NvBool Enable);
+
+/**
+ * Configures SoC power rail controls for the upcoming PMU voltage transition.
+ *
+ * @note Should be called just before PMU rail On/Off, or Off/On transition.
+ *  Should not be called if rail voltage level is changing within On range.
+ *
+ * @param hDevice The Rm device handle.
+ * @param PmuRailAddress PMU address (id) for targeted power rail.
+ * @param Enable Set NV_TRUE if target voltage is about to be turned On, or
+ *  NV_FALSE if target voltage is about to be turned Off.
+ * @param pIoPwrDetectMask A pointer to a variable filled with the bit mask
+ *  of activated IO power detection cells to be latched by the caller after
+ *  Off/On transition (set to 0 for On/Off transition).
+ * @param pNoIoPwrMask A pointer to a variable filled with the bit mask of IO
+ *  power pads to be enabled by the caller after Off/On transition (set to 0
+ *  for On/Off transition).
+ */
+void
+NvRmPrivSetSocRailPowerState(
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvU32 PmuRailAddress,
+    NvBool Enable,
+    NvU32* pIoPwrDetectMask,
+    NvU32* pNoIoPwrMask);
+
+/**
+ * Initializes core SoC power rail.
+ *
+ * @param hDevice The Rm device handle.
+ */
+void NvRmPrivCoreVoltageInit(NvRmDeviceHandle hRmDevice);
+
+/**
+ * Request nominal core (and rtc) voltage.
+ *
+ * @param hRmDeviceHandle The RM device handle
+ */
+void
+NvRmPrivSetNominalCoreVoltage(NvRmDeviceHandle hRmDevice);
+
+/**
+ * Initializes power group control table (chip-specific)
+ * 
+ * @param pPowerGroupIdsTable 
+ * @param pPowerGroupIdsTable A pointer to a pointer which this function sets
+ *  to the chip specific map between power group number and power gate ID. 
+ * @param pPowerGroupIdsTableSize A pointer to a variable which this function
+ *  sets to the power group IDs table size.
+ * 
+ */
+void
+NvRmPrivAp15PowerGroupTableInit(
+    const NvU32** pPowerGroupIdsTable,
+    NvU32* pPowerGroupIdsTableSize);
+
+void
+NvRmPrivAp20PowerGroupTableInit(
+    const NvU32** pPowerGroupIdsTable,
+    NvU32* pPowerGroupIdsTableSize);
+
+/**
+ * Initializes power group control.
+ * 
+ * @param hRmDeviceHandle The RM device handle
+ */
+void NvRmPrivPowerGroupControlInit(NvRmDeviceHandle hRmDeviceHandle);
+
+/**
+ * Enables/disables power for the specified power group
+ *
+ * @param hRmDeviceHandle The RM device handle
+ * @param PowerGroup targeted power group
+ * @param Enable If NV_TRUE, enable power to the specified power group,
+ *  if NV_FALSE, disable power (power gate) the specified power group
+ */
+void
+NvRmPrivPowerGroupControl(
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvU32 PowerGroup,
+    NvBool Enable);
+
+/**
+ * Retrieves given power group voltage
+ *
+ * @param hRmDeviceHandle The RM device handle
+ * @param PowerGroup targeted power group
+ *
+ * @return NvRmVoltsUnspecified if power group is On,
+ *  and NvRmVoltsOff if it is power gated
+ */
+NvRmMilliVolts
+NvRmPrivPowerGroupGetVoltage(
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvU32 PowerGroup);
+
+
+/**
+ * Gate/ungate power groups on entry/exit to/from low power state.
+ *
+ * @param hRmDeviceHandle The RM device handle.
+ */
+void NvRmPrivPowerGroupSuspend(NvRmDeviceHandle hRmDeviceHandle);
+void NvRmPrivPowerGroupResume(NvRmDeviceHandle hRmDeviceHandle);
+
+/**
+ * Controls power state and clamping for PCIEXCLK/PLLE (chip-specific).
+ *
+ * @param hRmDevice The RM device handle.
+ * @param Enable If NV_TRUE, power up PCIEXCLK and remove clamps,
+ *  if NV_FALSE, power down PCIEXCLK  and set clamps.
+ */
+void
+NvRmPrivAp20PowerPcieXclkControl(
+    NvRmDeviceHandle hRmDevice,
+    NvBool Enable);
+
+/**
+ * Verifies if the specified DFS clock domain is starving.
+ *
+ * @param ClockId The DFS ID of the clock domain to be checked.
+ *
+ * @retval NV_TRUE if domain is starving
+ * @retval NV_FALSE if domain is not starving
+ */
+NvBool NvRmPrivDfsIsStarving(NvRmDfsClockId ClockId);
+
+/**
+ * Gets current busy boost frequency and pulse mode requested for the
+ *  specified DFS clock domain.
+ *
+ * @param ClockId The DFS ID of the targeted clock domain.
+ * @param pBusyKHz A pointer to a variable filled with boost frequency in kHz.
+ * @param pBusyKHz A pointer to a variable filled with pulse mode indicator.
+ * @param pBusyExpireMs A pointer to a variable filled with busy boost
+ *  expiration interval in ms.
+ */
+void NvRmPrivDfsGetBusyHint(
+    NvRmDfsClockId ClockId,
+    NvRmFreqKHz* pBusyKHz,
+    NvBool* pBusyPulseMode,
+    NvU32* pBusyExpireMs);
+
+/**
+ * Gets maximum frequency for the specified DFS clock domain.
+ *
+ * @param ClockId The DFS ID of the targeted clock domain.
+ *
+ * @return Maximum domain frequency in kHz
+ */
+NvRmFreqKHz NvRmPrivDfsGetMaxKHz(NvRmDfsClockId ClockId);
+
+/**
+ * Gets minimum frequency for the specified DFS clock domain.
+ *
+ * @param ClockId The DFS ID of the targeted clock domain.
+ *
+ * @return Minimum domain frequency in kHz
+ */
+NvRmFreqKHz NvRmPrivDfsGetMinKHz(NvRmDfsClockId ClockId);
+
+/**
+ * Gets current frequency for the specified DFS clock domain.
+ *
+ * @param ClockId The DFS ID of the targeted clock domain.
+ *
+ * @return Current domain frequency in kHz
+ */
+NvRmFreqKHz NvRmPrivDfsGetCurrentKHz(NvRmDfsClockId ClockId);
+
+/**
+ * Signals DFS clock control thread
+ * 
+ * @param Mode Synchronization mode. In synchronous mode this function returns
+ *  to the caller after DFS clock control procedure is executed (blocking call).
+ *  In asynchronous mode returns immediately after control thread is signaled.
+ */
+void NvRmPrivDfsSignal(NvRmDfsBusyHintSyncMode Mode);
+
+/**
+ * Synchronize DFS samplers with current clock frequencies
+ */
+void NvRmPrivDfsResync(void);
+
+/**
+ * Gets DFS ready for low power state entry.
+ *
+ * @param state Target low power state.
+ *
+ */
+void NvRmPrivDfsSuspend(NvOdmSocPowerState state);
+
+/**
+ * Restore clock sources after exit from low power state.
+ *
+ * @param hRmDevice The RM device handle.
+ */
+void
+NvRmPrivClocksResume(NvRmDeviceHandle hRmDevice);
+
+
+/**
+ * Initializes DVS settings
+ */
+void NvRmPrivDvsInit(void);
+
+/**
+ * Scales core voltage according to DFS controlled clock frequencies.
+ *
+ * @param BeforeFreqChange Indicates whether this function is called
+ *  before (NV_TRUE) or after (NV_FALSE) frequency change.
+ * @param CpuMv Core voltage in mV required to run CPU at clock source
+ *  frequency selected by DFS.
+ * @param SystemMv Core voltage in mV required to run AVP/System at clock
+ *  source frequency selected by DFS.
+ * @param EmcMv Core voltage in mV required to run EMC/DDR at clock source
+ *  frequency selected by DFS.
+ */
+void NvRmPrivVoltageScale(
+    NvBool BeforeFreqChange,
+    NvRmMilliVolts CpuMv,
+    NvRmMilliVolts SystemMv,
+    NvRmMilliVolts EmcMv);
+
+/**
+ * Requests core voltage update.
+ *
+ * @param TargetMv Requested core voltage level in mV.
+ */
+void NvRmPrivDvsRequest(NvRmMilliVolts TargetMv);
+
+/**
+ * Gets low threshold and present voltage on the given rail.
+ *
+ * @param RailId The targeted voltage rail ID.
+ * @param pLowMv Output storage pointer for low voltage threshold (in
+ *  millivolt).
+ * @param pPresentMv Output storage pointer for present rail voltage (in
+ *  millivolt). This parameter is optional, set to NULL if only low
+ *  threshold is to be retrieved.
+ *
+ *  NvRmVoltsUnspecified is returned if targeted rail does not exist on SoC.
+ */
+void
+NvRmPrivGetLowVoltageThreshold(
+    NvRmDfsVoltageRailId RailId,
+    NvRmMilliVolts* pLowMv,
+    NvRmMilliVolts* pPresentMv);
+
+/**
+ * Outputs debug messages for starvation hints sent by the specified client.
+ *
+ * @param ClientId The client ID assigned by the RM power manager.
+ * @param ClientTag The client tag reported to the RM power manager.
+ * @param pMultiHint Pointer to a list of starvation hints sent by the client.
+ * @param NumHints Number of entries in the pMultiHint list.
+ *
+ */
+void NvRmPrivStarvationHintPrintf(
+    NvU32 ClientId,
+    NvU32 ClientTag,
+    const NvRmDfsStarvationHint* pMultiHint,
+    NvU32 NumHints);
+
+/**
+ * Outputs debug messages for busy hints sent by the specified client.
+ *
+ * @param ClientId The client ID assigned by the RM power manager.
+ * @param ClientTag The client tag reported to the RM power manager.
+ * @param pMultiHint Pointer to a list of busy hints sent by the client.
+ * @param NumHints Number of entries in the pMultiHint list.
+ *
+ */
+void NvRmPrivBusyHintPrintf(
+    NvU32 ClientId,
+    NvU32 ClientTag,
+    const NvRmDfsBusyHint* pMultiHint,
+    NvU32 NumHints);
+
+#ifdef __cplusplus
+}
+#endif  /* __cplusplus */
+
+#endif // INCLUDED_NVRM_POWER_PRIVATE_H
diff --git a/arch/arm/mach-tegra/include/nvrm_pwm.h b/arch/arm/mach-tegra/include/nvrm_pwm.h
new file mode 100644
index 000000000000..d1011dc77439
--- /dev/null
+++ b/arch/arm/mach-tegra/include/nvrm_pwm.h
@@ -0,0 +1,180 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_nvrm_pwm_H
+#define INCLUDED_nvrm_pwm_H
+
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+#include "nvrm_pinmux.h"
+#include "nvrm_module.h"
+#include "nvrm_init.h"
+
+#include "nvos.h"
+#include "nvcommon.h"
+
+/**
+ * NvRmPwmHandle is an opaque handle to the NvRmPwmStructRec interface
+ */
+ 
+typedef struct NvRmPwmRec *NvRmPwmHandle;
+
+/**
+ * Defines possible PWM modes.
+ */
+
+typedef enum
+{
+
+    /// Specifies Pwm disable mode
+        NvRmPwmMode_Disable = 1,
+
+    /// Specifies Pwm enable mode
+        NvRmPwmMode_Enable,
+
+    /// Specifies Blink LED enabled mode
+        NvRmPwmMode_Blink_LED,
+
+    /// Specifies Blink output 32KHz clock enable mode
+        NvRmPwmMode_Blink_32KHzClockOutput,
+
+    /// Specifies Blink disabled mode
+        NvRmPwmMode_Blink_Disable,
+    NvRmPwmMode_Num,
+    NvRmPwmMode_Force32 = 0x7FFFFFFF
+} NvRmPwmMode;
+
+/**
+ * Defines the possible PWM output pin
+ */
+
+typedef enum
+{
+
+    /// Specifies PWM Output-0
+        NvRmPwmOutputId_PWM0 = 1,
+
+    /// Specifies PWM Output-1
+        NvRmPwmOutputId_PWM1,
+
+    /// Specifies PWM Output-2
+        NvRmPwmOutputId_PWM2,
+
+    /// Specifies PWM Output-3
+        NvRmPwmOutputId_PWM3,
+
+    /// Specifies PMC Blink LED
+        NvRmPwmOutputId_Blink,
+    NvRmPwmOutputId_Num,
+    NvRmPwmOutputId_Force32 = 0x7FFFFFFF
+} NvRmPwmOutputId;
+
+/**
+ * @brief Initializes and opens the pwm channel. This function allocates the
+ * handle for the pwm channel and provides it to the client.
+ *
+ * Assert encountered in debug mode if passed parameter is invalid.
+ *
+ * @param hDevice Handle to the Rm device which is required by Rm to acquire
+ *  the resources from RM.
+ * @param phPwm Points to the location where the Pwm handle shall be stored.
+ *
+ * @retval NvSuccess Indicates that the Pwm channel has successfully opened.
+ * @retval NvError_InsufficientMemory Indicates that function fails to allocate
+ *  the memory.
+ * @retval NvError_NotInitialized Indicates the Pwm initialization failed.
+ */
+
+ NvError NvRmPwmOpen( 
+    NvRmDeviceHandle hDevice,
+    NvRmPwmHandle * phPwm );
+
+/** 
+ * @brief Closes the Pwm channel. This function frees the memory allocated for
+ *  the pwm handle for the pwm channel.
+ *  This function de-initializes the pwm channel. This API never fails.
+ *
+ * @param hPwm A handle from NvRmPwmOpen().  If hPwm is NULL, this API does
+ *     nothing.
+ */
+
+ void NvRmPwmClose( 
+    NvRmPwmHandle hPwm );
+
+/** 
+ * @brief Configure PWM module as disable/enable. Also, it is used
+ *  to set the PWM duty cycle and frequency. Beside that, it is 
+ *  used to configure PMC' blinking LED if OutputId is NvRmPwmOutputId_Blink
+ *
+ * @param hPwm Handle to the PWM channel.
+ * * @param OutputId The output pin to config. Allowed OutputId values are
+ *   defined in ::NvRmPwmOutputId
+ * @param Mode The mode type to config. Allowed mode values are
+ *   defined in ::NvRmPwmMode
+ * @param DutyCycle The duty cycle is an unsigned 15.16 fixed point
+ *   value that represents PWM duty cycle in percentage range from
+ *   0.00 to 100.00. For example, 10.5 percentage duty cycle would be
+ *   represented as 0x000A8000. This parameter is ignored if NvRmPwmMode
+ *   is NvRmPwmMode_Blink_32KHzClockOutput or NvRmPwmMode_Blink_Disable
+ * @param RequestedFreqHzOrPeriod The requested frequency in Hz or Period
+ *  A requested frequency value beyond the max supported value will be
+ *  clamped to the max supported value.
+ *  If PMC Blink LED is used, this parameter is represented as
+ *  request period time in second unit. This parameter is ignored if 
+ *  NvRmPwmMode is NvRmPwmMode_Blink_32KHzClockOutput or 
+ *  NvRmPwmMode_Blink_Disable
+ *
+ * @param pCurrentFreqHzOrPeriod Pointer to the returns frequency of 
+ *  that mode. If PMC Blink LED is used then it is the pointer to 
+ *  the returns period time. This parameter is ignored if NvRmPwmMode
+ *  is NvRmPwmMode_Blink_32KHzClockOutput or NvRmPwmMode_Blink_Disable
+ *
+ * @retval NvSuccess Indicates the configuration succeeded.
+ */
+
+ NvError NvRmPwmConfig( 
+    NvRmPwmHandle hPwm,
+    NvRmPwmOutputId OutputId,
+    NvRmPwmMode Mode,
+    NvU32 DutyCycle,
+    NvU32 RequestedFreqHzOrPeriod,
+    NvU32 * pCurrentFreqHzOrPeriod );
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif
diff --git a/arch/arm/mach-tegra/include/nvrm_rmctrace.h b/arch/arm/mach-tegra/include/nvrm_rmctrace.h
new file mode 100644
index 000000000000..22a9eb45eb71
--- /dev/null
+++ b/arch/arm/mach-tegra/include/nvrm_rmctrace.h
@@ -0,0 +1,147 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_NVRM_RMCTRACE_H
+#define INCLUDED_NVRM_RMCTRACE_H
+
+#include "nvcommon.h"
+#include "nvos.h"
+#include "nvrm_init.h"
+
+/**
+ * RMC is a file format for capturing accesses to hardware, both memory
+ * and register, that may be played back against a simulator.  Drivers
+ * are expected to emit RMC tracing if RMC tracing is enabled.
+ *
+ * The RM will already have an RMC file open before any drivers are expected
+ * to access it, so it is not necessary for NvRmRmcOpen or Close to be called
+ * by anyone except the RM itself (but drivers may want to if capturing a
+ * subset of commands is useful).
+ */
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif  /* __cplusplus */
+
+#if !defined(NV_OAL)
+#define NV_OAL 0
+#endif
+
+// FIXME: better rmc compile time macros
+#if !defined(NV_DEF_RMC_TRACE)
+#if NV_DEBUG && !NV_OAL
+#define NV_DEF_RMC_TRACE 1
+#else
+#define NV_DEF_RMC_TRACE 0
+#endif
+#endif
+
+/**
+ * exposed structure for RMC files.
+ */
+typedef struct NvRmRMCFile_t
+{
+    NvOsFileHandle file;
+    NvBool enable; /* enable bit for writes */
+} NvRmRmcFile;
+
+/**
+ * opens the an RMC file.
+ *
+ * @param name The name of the rmc file
+ * @param rmc Out param - the opened rmc file (if successful)
+ *
+ * NvOsFile* operatations should not be used directly since RMC commands
+ * or comments may be emited to the file on open/close/etc.
+ */
+NvError
+NvRmRmcOpen( const char *name, NvRmRmcFile *rmc );
+
+/**
+ * closes an RMC file.
+ *
+ * @param rmc The rmc file to close.
+ */
+void
+NvRmRmcClose( NvRmRmcFile *rmc );
+
+/**
+ * emits a string to the RMC file.
+ *
+ * @param file The RMC file
+ * @param format Printf style argument format string
+ *
+ * NvRmRmcOpen must be called before this function.
+ *
+ * This function should be called via a macro so that it may be compiled out.
+ * Note that double parens will be needed:
+ *
+ *     NVRM_RMC_TRACE(( file, "# filling memory with stuff\n" ));
+ */
+void
+NvRmRmcTrace( NvRmRmcFile *rmc, const char *format, ... );
+
+/**
+ * retrieves the RM's global RMC file.
+ *
+ * @param hDevice The RM instance
+ * @param file Output param: the RMC file
+ */
+NvError
+NvRmGetRmcFile( NvRmDeviceHandle hDevice, NvRmRmcFile **file );
+
+#if NV_DEF_RMC_TRACE
+#define NVRM_RMC_TRACE(a) NvRmRmcTrace a
+/**
+ * enable or disable RMC tracing at runtime.
+ *
+ * @param file The RMC file
+ * @param enable Either enable or disable rmc tracing
+ */
+#define NVRM_RMC_ENABLE(f, e) \
+    ((f)->enable = (e))
+
+#define NVRM_RMC_IS_ENABLED(f) \
+    ((f)->enable != 0)
+
+#else
+#define NVRM_RMC_TRACE(a) (void)0
+#define NVRM_RMC_ENABLE(f,e) (void)0
+#define NVRM_RMC_IS_ENABLED(f) (void)0
+#endif
+
+#ifdef __cplusplus
+}
+#endif  /* __cplusplus */
+
+#endif /* NVRM_RMCTRACE_H */
diff --git a/arch/arm/mach-tegra/include/nvrm_spi.h b/arch/arm/mach-tegra/include/nvrm_spi.h
new file mode 100644
index 000000000000..e5bee1e1bd1c
--- /dev/null
+++ b/arch/arm/mach-tegra/include/nvrm_spi.h
@@ -0,0 +1,370 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_nvrm_spi_H
+#define INCLUDED_nvrm_spi_H
+
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+#include "nvrm_pinmux.h"
+#include "nvrm_module.h"
+#include "nvrm_init.h"
+
+#include "nvcommon.h"
+
+/**
+ * NvRmSpiHandle is an opaque context to the NvRmSpiRec interface.
+ */
+
+typedef struct NvRmSpiRec *NvRmSpiHandle;
+
+/**
+ * Open the handle for the spi/sflash controller. This api initalise the 
+ * sflash/spi controller.
+ * The Instance Id for the sflash and spi controller start from 0.
+ * The handle for the spi/sflash is open in master and slave mode based on the
+ * parameter passed. If the spi handle is opened in master mode the the SPICLK
+ * is generated from the spi controller and it acts like a master for all the 
+ * transaction.
+ *
+ * If the spi handle is opened in master mode then the controller can be shared 
+ * between different chip select client but if the spi handle is created in the 
+ * slave mode then it can not be shared by other client and only one client is
+ * allowed to open the spi handle for the slave mode.
+ *
+ * Assert encountered in debug mode if invalid parameter passed.
+ *
+ * @param hRmDevice Handle to the Rm device.
+ * @param IoModule The Rm IO module to set whether this is the 
+ * NvOdmIoModule_Sflash or NvOdmIoModule_Slink or NvOdmIoModule_Spi.
+ * @param InstanceId  The Instance Id which starts from the 0.
+ * @param IsMasterMode  Tells whether the controller will be open in master mode
+ * or the slave mode?
+ * @param phRmSpi  Pointer to the sflash/spi handle where the allocated handle 
+ * will be stored.
+ *
+ * @retval NvSuccess Indicates the function is successfully completed
+ * @retval NvError_MemoryMappingFail Indicates the address mapping of the
+ * register failed.
+ * @retval NvError_InsufficientMemory Indicates that memory allocation is
+ * failed.
+ * @retval NvError_NotSupported Indicases that the spi is not supported.
+ * @retval NvError_AlreadyAllocated Indicases that the spi handle is already 
+ * allocated to the other slave client.
+ */
+
+ NvError NvRmSpiOpen( 
+    NvRmDeviceHandle hRmDevice,
+    NvU32 IoModule,
+    NvU32 InstanceId,
+    NvBool IsMasterMode,
+    NvRmSpiHandle * phRmSpi );
+
+/**
+ * Deinitialize the spi controller, disable the clock and release the spi
+ * handle.
+ *
+ * @param hRmSpi A handle from NvRmSpiOpen().  If hRmSpi is NULL, this API does
+ *     nothing.
+ */
+
+ void NvRmSpiClose( 
+    NvRmSpiHandle hRmSpi );
+
+/**
+ * Performs an Spi controller read and write simultaneously in master mode. 
+ * This apis is only supported if the handle is open in master mode.
+ *
+ * Every Spi transaction is by definition a simultaneous read and write transaction, so 
+ * there are no separate APIs for read versus write. However, if you only need 
+ * to do a read or write, this API allows you to declare that you are not 
+ * interested in the read data, or that the write data is not of interest.
+ * If only read is required then client can pass the NULL pointer to the 
+ * pWriteBuffer. Zeros will be sent in this case.
+ * Similarly, if client wants to send data only then he can pass the 
+ * pReadBuffer as NULL.
+ * If Read and write is required and he wants to first send the command and 
+ * then want to read the response, then he need to send both the valid pointer
+ * read and write. In this case the bytesRequested will be the sum of the
+ * send command size and response size. The size of the pReadBuffer and 
+ * pWriteBuffer should be equal to the bytes requetsed.
+ * E.g. Client want to send the 4byte command first and the wants to read the
+ * 4 byte response, then he need a 8 byte pWriteBuffer and 8 byte pReadBuffer.
+ * He will fill the first 4 byte of pWriteBuffer with the command which he
+ * wants to send. After calling this api, he needs to ignore the first 4 bytes
+ * and use the next 4 byte as valid response data in the pReadBuffer.
+ *
+ * This is a blocking API. It will returns when all the data has been transferred
+ * over the pins of the SOC (the transaction).
+ *
+ * Several Spi transactions may be performed in a single call to this API, but
+ * only if all of the transactions are to the same chip select and have the same
+ * packet size.
+ *
+ * Transaction sizes from 1 to 32 bits are supported. However, all of the 
+ * packets are byte-aligned in memory. Like, if packetBitLength is 12 bit 
+ * then client needs the 2 byte for the 1 packet. New packets start from the
+ * new bytes e.g. byte0 and byte1 contain the first packet and byte2 and byte3
+ * will contain the second packets.
+ *
+ * To perform one transaction, the BytesRequested argument should be:
+ *
+ *   (PacketSizeInBits + 7)/8
+ *
+ * To perform n transactions, BytesRequested should be:
+ *
+ *   n*((PacketSizeInBits + 7)/8)
+ *
+ * Within a given
+ * transaction with the packet size larger than 8 bits, the bytes are stored in 
+ * order of the MSB (most significant byte) first.
+ * The Packet is formed with the first Byte will be in MSB and then next byte 
+ * will be in the  next MSB towards the LSB.
+ *	
+ * For the example, if One packet need to be send and its size is the 20 bit 
+ * then it will require the 3 bytes in the pWriteBuffer and arrangement of the 
+ * data	 are as follows:
+ * The packet is 0x000ABCDE (Packet with length of 20 bit).
+ * pWriteBuff[0] = 0x0A
+ * pWriteBuff[1] = 0xBC
+ * pWtriteBuff[2] = 0xDE
+ *
+ * The most significant bit will be transmitted first i.e. bit20 is transmitted 
+ * first and bit 0 will be transmitted last.
+ *
+ * If the transmitted packet (command + receive data) is more than 32 like 33 and 
+ * want to transfer in the single call (CS should be active) then it can be transmitted
+ * in following way:
+ * The transfer is command(8 bit)+Dummy(1bit)+Read (24 bit) = 33 bit of transfer.
+ * - Send 33 bit as 33 byte and each byte have the 1 valid bit, So packet bit length = 1 and
+ * bytes requested = 33.
+ * NvU8 pSendData[33], pRecData[33];
+ *  pSendData[0] = (Comamnd >>7) & 0x1;
+ *  pSendData[1] = (Command >> 6)& 0x1; 
+ * ::::::::::::::
+ * pSendData[8] = DummyBit;
+ * pSendData[9] to pSendData[32] = 0;
+ * Call NvRmSpiTransaction(hRmSpi,SpiPinMap,ChipSelect,ClockSpeedInKHz,pRecData, pSendData, 33,1);
+ * Now You will get the read data from pRecData[9] to pRecData[32] on bit 0 on each byte.
+ *
+ * - The 33 bit transfer can be also done as 11 byte and each byte have the 3 valid bits.
+ * This need to rearrange the command in the pSendData in such a way that each byte have the
+ * 3 valid bits.
+ * NvU8 pSendData[11], pRecData[11];
+ *  pSendData[0] = (Comamnd >>4) & 0x7;
+ *  pSendData[1] = (Command >> 1)& 0x7; 
+ *  pSendData[2] = (((Command)& 0x3) <<1) | DummyBit; 
+ * pSendData[3] to pSendData[10] = 0;
+ * 
+ * Call NvRmSpiTransaction(hRmSpi,SpiPinMap,ChipSelect,ClockSpeedInKHz,pRecData, pSendData, 11,3);
+ * Now You will get the read data from pRecData[4] to pRecData[10] on lower 3 bits on each byte.
+ *
+ * Similarly the 33 bit transfer can also be done as 6 byte and each 2 bytes contain the 11 valid bits.
+ * Call NvRmSpiTransaction(hRmSpi,SpiPinMap,ChipSelect,ClockSpeedInKHz,pRecData, pSendData, 6,11);
+ *
+ * pReadBuffer and pWriteBuffer may be the same pointer, in which case the 
+ * write data is destroyed as we read in the read data. Unless they are 
+ * identical pointers, however, pReadBuffer and pWriteBuffer must not overlap.
+ *
+ * @param hOdmSpi The Spi handle allocated in a call to NvOdmSpiOpen().
+ * @param SpiPinMap For SPI master-mode controllers which are being multiplexed across
+ *        multiple pin mux configurations, this specifies which pin mux configuration
+ *        should be used for the transaction.  Must be 0 when the ODM pin mux query
+ *        specifies a non-multiplexed configuration for the controller.
+ * @param ChipSelectId The chip select Id on which device is connected.
+ * @param ClockSpeedInKHz The clock speed in KHz on which device can communicate.
+ * @param pReadBuffer A pointer to buffer to be filled in with read data. If this
+ *     pointer is NULL, the read data will be discarded.
+ * @param pWriteBuffer A pointer to a buffer from which to obtain write data. If this
+ *     pointer is NULL, the write data will be all zeros.
+ * @param BytesRequested The size of pReadBuffer and pWriteBuffer buffers in bytes.
+ * @param PacketSizeInBits The packet size in bits of each Spi transaction.
+ *
+ */
+ 
+ void NvRmSpiTransaction( 
+    NvRmSpiHandle hRmSpi,
+    NvU32 SpiPinMap,
+    NvU32 ChipSelectId,
+    NvU32 ClockSpeedInKHz,
+    NvU8 * pReadBuffer,
+    NvU8 * pWriteBuffer,
+    NvU32 BytesRequested,
+    NvU32 PacketSizeInBits );
+
+/**
+ * Start an Spi controller read and write simultaneously in the slave mode. 
+ * This API is only supported for the spi handle which is opened in slave mode. 
+ *
+ * This API will assert if opened spi handle is the master type.
+ *
+ * Every Spi  transaction is by definition a simultaneous read and write 
+ * transaction, so there are no separate APIs for read versus write. 
+ * However, if you only need to start a read or write transaction, this API 
+ * allows you to declare that you are not interested in the read data, 
+ * or that the write data is not of interest.
+ * If only read is required to start then client can pass NV_TRUE to the the
+ * IsReadTransfer and NULL pointer to the pWriteBuffer. The state of the dataout 
+ * will be set by IsIdleDataOutHigh of the structure NvOdmQuerySpiIdleSignalState 
+ * in nvodm_query.h.
+ * Similarly, if client wants to send data only then he can pass NV_FALSE to the
+ * IsReadTransfer.
+ *
+ * This is a nonblocking API. This api start the data transfer and returns to the
+ * caller without waiting for the data transfer completion.
+ *
+ * Transaction sizes from 1 to 32 bits are supported. However, all of the 
+ * packets are byte-aligned in memory. Like, if packetBitLength is 12 bit 
+ * then client needs the 2 byte for the 1 packet. New packets start from the
+ * new bytes e.g. byte0 and byte1 contain the first packet and byte2 and byte3
+ * will contain the second packets.
+ *
+ * To perform one transaction, the BytesRequested argument should be:
+ *
+ *   (PacketSizeInBits + 7)/8
+ *
+ * To perform n transactions, BytesRequested should be:
+ *
+ *   n*((PacketSizeInBits + 7)/8)
+ *
+ * Within a given
+ * transaction with the packet size larger than 8 bits, the bytes are stored in 
+ * order of the LSB (least significant byte) first.
+ * The Packet is formed with the first Byte will be in LSB and then next byte 
+ * will be in the  next LSB towards the MSB.
+ *	
+ * For the example, if One packet need to be send and its size is the 20 bit 
+ * then it will require the 3 bytes in the pWriteBuffer and arrangement of the 
+ * data	 are as follows:
+ * The packet is 0x000ABCDE (Packet with length of 20 bit).
+ * pWriteBuff[0] = 0xDE
+ * pWriteBuff[1] = 0xBC
+ * pWtriteBuff[2] = 0x0A
+ *
+ * The most significant bit will be transmitted first i.e. bit20 is transmitted 
+ * first and bit 0 will be transmitted last.
+ *
+ * @see NvRmSpiGetTransactionData
+ * Typical usecase for the CAIF interface.  The step for doing the transfer is:
+ * 1. ACPU calls the NvRmSpiStartTransaction() to configure the spi controller
+ * to set in the receive or transmit mode and make ready for the data transfer.
+ * 2. ACPU then send the signal to the CCPU to send the SPICLK (by activating 
+ * the SPI_INT) and start the transaction. CCPU get this signal and start sending 
+ * SPICLK.
+ * 3. ACPU will call the NvRmSpiGetTransactionData() to get the data/information 
+ * about the transaction.
+ * 4. After completion of the transfer ACPU inactivate the SPI_INT.
+ *
+ * @param hOdmSpi The Spi handle allocated in a call to NvOdmSpiOpen().
+ * @param ChipSelectId The chip select Id on which device is connected.
+ * @param ClockSpeedInKHz The clock speed in KHz on which device can communicate.
+ * @param IsReadTransfer It tells that whether the read transfer is required or 
+ * not. If it is NV_TRUE then read transfer is required and the read data will be 
+ * available in the local buffer of the driver. The client will get the received
+ * data after calling the NvRmSpiGetTransactionData().
+ * @param pWriteBuffer A pointer to a buffer from which to obtain write data. If this
+ *     pointer is NULL, the write data will be all zeros.
+ * @param BytesRequested The size of pReadBuffer and pWriteBuffer buffers in bytes.
+ * @param PacketSizeInBits The packet size in bits of each Spi transaction.
+ *
+ */
+ 
+ NvError NvRmSpiStartTransaction( 
+    NvRmSpiHandle hRmSpi,
+    NvU32 ChipSelectId,
+    NvU32 ClockSpeedInKHz,
+    NvBool IsReadTransfer,
+    NvU8 * pWriteBuffer,
+    NvU32 BytesRequested,
+    NvU32 PacketSizeInBits );
+
+/**
+ * Get the spi transaction status that is started for the slave mode and wait
+ * if required till the transfer completes for a given timeout error.
+ * If read transaction has been started then it will return the receive data to 
+ * the client.
+ *
+ * This is a blocking API and wait for the data transfer completion till the
+ * data requested transfer completes or the timeout happen.
+ *
+ * @see NvRmSpiStartTransaction
+ *
+ * @param hOdmSpi The Spi handle allocated in a call to NvOdmSpiOpen().
+ * @param pReadBuffer A pointer to buffer to be filled in with read data. If this
+ *     pointer is NULL, the read data will be discarded.
+ * @param BytesRequested The size of pReadBuffer and pWriteBuffer buffers in bytes.
+ * @param BytesTransfererd The number of bytes transferred.
+ * @param WaitTimeout The timeout in millisecond to wait for the trsnaction to be 
+ * completed.
+ *
+ * @retval NvSuccess Indicates that the operation succeeded.
+ * @retval NvError_Timeout Indicates that the timeout happen.
+ * @retval NvError_InvalidState Indicates that the transfer has not been started.
+ *
+ */
+ 
+ NvError NvRmSpiGetTransactionData( 
+    NvRmSpiHandle hRmSpi,
+    NvU8 * pReadBuffer,
+    NvU32 BytesRequested,
+    NvU32 * pBytesTransfererd,
+    NvU32 WaitTimeout );
+
+/**
+ * Set the signal mode for the spi communication for a given chip select.
+ * After calling this API, the further communication happen with the new 
+ * configured signal modes.
+ * The default value of the signal mode is taken from nvodm query and this
+ * api will override the signal mode which is read from query.
+ *
+ * @see NvRmSpiStartTransaction
+ *
+ * @param hOdmSpi The Spi handle allocated in a call to NvOdmSpiOpen().
+ * @param ChipSelectId The chip select Id on which device is connected.
+ * @param SpiSignalMode The nvodm signal modes which need to be set.
+ *
+ */
+ 
+ void NvRmSpiSetSignalMode( 
+    NvRmSpiHandle hRmSpi,
+    NvU32 ChipSelectId,
+    NvU32 SpiSignalMode );
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif
diff --git a/arch/arm/mach-tegra/include/nvrm_transport.h b/arch/arm/mach-tegra/include/nvrm_transport.h
new file mode 100644
index 000000000000..179f63223ed5
--- /dev/null
+++ b/arch/arm/mach-tegra/include/nvrm_transport.h
@@ -0,0 +1,361 @@
+/*
+ * Copyright (c) 2010 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_nvrm_transport_H
+#define INCLUDED_nvrm_transport_H
+
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+#include "nvrm_module.h"
+#include "nvrm_init.h"
+
+/** @file
+ * @brief <b>NVIDIA Driver Development Kit:
+ *     Resource Manager Transport APIs</b>
+ *
+ * @b Description: This is the Transport API, which defines a simple means to
+ * pass messages across a lower level connection (generally between
+ * processors).
+ *
+ */
+
+/** @defgroup nvrm_transport RM Transport API
+ * 
+ * The Transport API defines a simple protocol through which clients and
+ * services may connect and communicate--normally, though not necessarily,
+ * across separate processors.  Clients to this interface mostly include
+ * audio-visual applications whose code may reside on either the MPCore or AVP
+ * processors.  These applications (and there could be many concurrently) may
+ * utilize this transport API to synchronize their operations.  How the
+ * Transport API shepherds messages through these connections is not visible to
+ * the client.
+ * 
+ * To setup a new connection, both the client and the service must open a port
+ * (whose name is agreed upon before compile-time).  The service waits for a
+ * client to connect; this "handshake" allows a connection to be established.
+ * Once a client has established a connection with the service, they may send
+ * and receive messages.
+ * 
+ * @ingroup nvddk_rm
+ * @{
+ */
+
+#include "nvos.h"
+
+/**
+ * A type-safe handle for the transport connection.
+ */
+
+typedef struct NvRmTransportRec *NvRmTransportHandle;
+
+/**
+ * Creates one end of a transport connection.  Both the service and client
+ * to the service must call this API to create each endpoint of the connection
+ * through a specified port (whose name is agreed upon before compile-time).
+ * A connection is not established between the service and client until a 
+ * handshake is completed (via calls to NvRmTransportWaitForConnect() and
+ * NvRmTransportConnect() respectively).
+ *
+ * Assert in debug mode encountered if PortName is too long or does not exist 
+ *
+ * @see NvRmTransportWaitForConnect()
+ * @see NvRmTransportConnect()
+ * @see NvRmTransportClose()
+ *
+ * @param hRmDevice Handle to RM device
+ * @param pPortName A character string that identifies the name of the port.
+ * This value must be 16 bytes or less, otherwise the caller receives an error.
+ * You can optionally pass NULL for this parameter, in which case a unique
+ * name will  be assigned.  And you can call NvRmTransporGetPortName to retrieve
+ * the name.
+ * @param RecvMessageSemaphore The externally created semaphore that the
+ * transport  connection will signal upon receipt of a message.
+ * @param phTransport Points to the location where the transport handle shall
+ * be stored
+ * 
+ * @retval NvSuccess Transport endpoint successfully allocated
+ * @retval NvError_InsufficientMemory Not enough memory to allocate endpoint
+ * @retval NvError_MutexCreateFailed Creaion of mutex failed.
+ * @retval NvError_SemaphoreCreateFailed Creaion of semaphore failed.
+ * @retval NvError_SharedMemAllocFailed Creaion of shared memory allocation
+ * failed.
+ * @retval NvError_NotInitialized The transport is not able to initialzed the
+ * threads.
+ */
+
+ NvError NvRmTransportOpen( 
+    NvRmDeviceHandle hRmDevice,
+    char * pPortName,
+    NvOsSemaphoreHandle RecvMessageSemaphore,
+    NvRmTransportHandle * phTransport );
+
+/**
+ * Retrieve the name associated with a port.
+ *
+ * Assert in debug mode encountered if PortName is too long or does not exist 
+ *
+ * @see NvRmTransportOpen()
+ *
+ * @param hTransport Handle to the port that you want the name of.
+ * @param PortName A character string that identifies the name of the port.
+ * @param PortNameSize Length of the PortName buffer.
+ * 
+ */
+
+ void NvRmTransportGetPortName( 
+    NvRmTransportHandle hTransport,
+    NvU8 * PortName,
+    NvU32 PortNameSize );
+
+/**
+ * Closes a transport connection.  Proper closure of this connection requires
+ * that both the client and service call this API.  Therefore, it is expected
+ * that the client and service message one another to coordinate the close.
+ *
+ * @see NvRmTransportOpen()
+ * 
+ * @param hTransport Specifies the transport connection to close.  If hTransport
+ *     is NULL, this API does nothing.
+ */
+
+ void NvRmTransportClose( 
+    NvRmTransportHandle hTransport );
+
+/**
+ * Initializes the transport.
+ *
+ * @param hRmDevice Handle to RM device
+ *
+ */
+
+ NvError NvRmTransportInit( 
+    NvRmDeviceHandle hRmDevice );
+
+/**
+ * Deinitializes the transport.
+ *
+ * @param hRmDevice Handle to RM device
+ *
+ */
+
+ void NvRmTransportDeInit( 
+    NvRmDeviceHandle hRmDevice );
+
+/**
+ * This handshake API is called by the service, which waits for a client to
+ * establish a connection via a call to NvRmTransportConnect().  Messages 
+ * cannot be sent and received until this handshake is completed.
+ * 
+ * To ensure a client has sufficient opportunity to establish a connection
+ * from the other end, a large timeout value (such as NV_WAIT_INFINITE) is
+ * recommended here.
+ *
+ * @see NvRmTransportConnect()
+ *
+ * @param hTransport Specifies the transport connection
+ * @param TimeoutMS Specifies the amount of time (in milliseconds) to wait for
+ *   connection to be established.  A value of NV_WAIT_INFINITE means "wait
+ *   indefinitely."  A value of zero (0) will timeout immediately, which is
+ *   not recommended for this function call.
+ * 
+ * @retval NvSuccess Service is waiting to receive a "connect" from client
+ * @retval NvError_NotInitialized hTransport is not open
+ * @retval NvError_Timeout Timed out waiting for service to respond
+ */
+
+ NvError NvRmTransportWaitForConnect( 
+    NvRmTransportHandle hTransport,
+    NvU32 TimeoutMS );
+
+/**
+ * This blocking handshake API is called by the client, which seeks a
+ * service (as specified by a handle) to establish a connection.  Messages
+ * cannot be sent and received until this handshake is completed.
+ *
+ * @see NvRmTransportWaitForConnect()
+ *
+ * @param hTransport Specifies the transport connection
+ * @param TimeoutMS Specifies the amount of time (in milliseconds) to wait for
+ *   connection to be established.  A value of NV_WAIT_INFINITE means "wait
+ *   indefinitely."  A value of zero (0) will timeout immediately, but
+ *   this function will at least take time to check if the port is open and
+ *   waiting for a connection--if so, a connection will be established.
+ * 
+ * @retval NvSuccess Transport connection successfully established
+ * @retval NvError_NotInitialized hTransport is not open
+ * @retval NvError_Timeout Timed out waiting for service to respond.
+ */
+
+ NvError NvRmTransportConnect( 
+    NvRmTransportHandle hTransport,
+    NvU32 TimeoutMS );
+
+/**
+ * Set the max size of the message queue (FIFO) deptha nd length which can be 
+ * send and receive from this port. The programmer must decide the
+ * queue depth that's appropriate for their design.  If this function is not
+ * called, the queue depth is set to one (1) and message size is 256 bytes.  
+ * 
+ *
+ * @see NvRmTransportSendMsg()
+ * @see NvRmTransportRecvMsg()
+ *
+ * @param hTransport Specifies the transport connection
+ * @param MaxQueueDepth The maximum number of message which can be queued for 
+ * this port for receiving and sending. The receive message can queue message 
+ * till this count for this port. If receive queue is full for this port and
+ * if other port send the message to this port then receive queue error status
+ * will turn as overrun and ignore the incoming message.
+ * If send message queue is full and client request to send message then he
+ * will wait for time provided by the parameter.
+ * @param MaxMessageSize Specifies the maximum size of the message in bytes
+ * which client can receive and transmit through this port. 
+ * 
+ * @retval NvSuccess New queue depth is set
+ * @retval NvError_NotInitialized hTransport is not open.
+ * @retval NvError_BadValue The parameter passed is not correct. There is 
+ * limitation for maximum message q and message length from the driver and if 
+ * this parameter is larger than those value then it returns this error.
+ *
+ */
+
+ NvError NvRmTransportSetQueueDepth( 
+    NvRmTransportHandle hTransport,
+    NvU32 MaxQueueDepth,
+    NvU32 MaxMessageSize );
+
+/**
+ * Sends a message to the other port which is connected to this port.
+ * This will use the copy method to copy the client buffer message to
+ * transport message buffer. This function queue the message to the transmit
+ * queue. the data will be send later based on the physical transfer channel
+ * availablity.
+ *
+ * @see NvRmTransportOpen()
+ * @see NvRmTransportSetQueueDepth()
+ * @see NvRmTransportRecvMsg()
+ *
+ * @param hTransport Specifies the transport connection
+ * @param pMessageBuffer The pointer to the message buffer where message which 
+ * need to be send is available.
+ * @param MessageSize Specifies the size of the message.
+ * @param TimeoutMS Specifies the amount of time (in milliseconds) to wait for
+ * sent message to be queued for the transfer. If the transmit queue if full
+ * then this function will block the client till maximum of timeout to queue
+ * this message. If meesage queue is available before timeout then it will
+ * queue the message and comeout. If message queue is full and timeout happen
+ * the it will return the timeout error.
+ * if zero timeout is selecetd and the message queue is full then it will be
+ * return NvError_TransportMessageBoxFull error.
+ * Avalue of NV_WAIT_INFINITE means "wait indefinitely" for queueing the
+ * message.
+ * 
+ * @retval NvSuccess Message is queued successfully.
+ * @retval NvError_NotInitialized hTransport is not open.
+ * @retval NvError_BadValue The parameter passed is not valid.
+ * @retval NvError_InvalidState The port is not connected to the other port and
+ * it is not ready for sending the message.
+ * @retval NvError_Timeout Timed out waiting for message to be queue if send 
+ * message queue.
+ * @retval NvError_TransportMessageBoxFull Message box is full and it is not
+ * able to queue the message.
+ */
+
+ NvError NvRmTransportSendMsg( 
+    NvRmTransportHandle hTransport,
+    void* pMessageBuffer,
+    NvU32 MessageSize,
+    NvU32 TimeoutMS );
+
+/**
+ * Sends a message to the other port which is connected to this port.
+ * This function is to be used ONLY when we're about to enter LP0!
+ * There is no synchronization in this function as only one person
+ * should be talking to the AVP at the time of LP0. The message is sent
+ * on the RPC_AVP_PORT. In the future, there might be instances where
+ * we need to talk on a different port in LP0. 
+ *
+ * @retval NvSuccess Message is queued successfully.
+ * @retval NvError_TransportMessageBoxFull Message box is full and it is not
+ * able to queue the message.
+ */
+
+ NvError NvRmTransportSendMsgInLP0( 
+    NvRmTransportHandle hPort,
+    void* message,
+    NvU32 MessageSize );
+
+/**
+ * Receive the message from the port. This will read the message if it is 
+ * available for this port otherwise it will return the
+ * NvError_TransportMessageBoxEmpty error.
+ *
+ * @see NvRmTransportOpen()
+ * @see NvRmTransportSetQueueDepth()
+ * @see NvRmTransportSendMsg()
+ *
+ * @param hTransport Specifies the transport connection
+ * @param pMessageBuffer The pointer to the receive message buffer where the
+ * received message will be copied.
+ * @param MaxSize The maximum size in bytes that may be copied to the buffer
+ * @param pMessageSize Pointer to the variable where the length of the message 
+ * will be stored.
+ * 
+ * @retval NvSuccess Message received successfully.
+ * @retval NvError_NotInitialized hTransport is not open.
+ * @retval NvError_InvalidState The port is not connection state.
+ * @retval NvError_TransportMessageBoxEmpty The message box empty and not able 
+ * to receive the message.
+ * @retval NvError_TransportIncompleteMessage The received message for this
+ * port is longer than the configured message length for this port. It copied
+ * the maximm size of the configured length of the message for this port and
+ * return the incomplete message buffer.
+ * @retval NvError_TransportMessageOverflow The port receives the message more
+ * than the configured queue depth count for this port and hence message
+ * overflow has been ocuured.
+ */
+
+ NvError NvRmTransportRecvMsg( 
+    NvRmTransportHandle hTransport,
+    void* pMessageBuffer,
+    NvU32 MaxSize,
+    NvU32 * pMessageSize );
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif
diff --git a/arch/arm/mach-tegra/include/nvrm_xpc.h b/arch/arm/mach-tegra/include/nvrm_xpc.h
new file mode 100644
index 000000000000..69b61d8d1147
--- /dev/null
+++ b/arch/arm/mach-tegra/include/nvrm_xpc.h
@@ -0,0 +1,157 @@
+/*
+ * Copyright (c) 2010 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_nvrm_xpc_H
+#define INCLUDED_nvrm_xpc_H
+
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+#include "nvrm_module.h"
+#include "nvrm_init.h"
+
+#include "nvcommon.h"
+#include "nvos.h"
+#include "nvrm_init.h"
+#include "nvrm_interrupt.h"
+
+/** 
+ * @brief 16 Byte allignment for the shared memory message transfer.
+ */
+
+typedef enum
+{
+    XPC_MESSAGE_ALIGNMENT_SIZE = 0x10,
+    Xpc_Alignment_Num,
+    Xpc_Alignment_Force32 = 0x7FFFFFFF
+} Xpc_Alignment;
+
+/**
+ * NvRmPrivXpcMessageHandle is an opaque handle to NvRmPrivXpcMessage.
+ * 
+ * @ingroup nvrm_xpc
+ */
+
+typedef struct NvRmPrivXpcMessageRec *NvRmPrivXpcMessageHandle;
+
+/**
+ * Create the xpc message handles for sending/receiving the message to/from 
+ * target processor.
+ * This function allocates the memory (from multiprocessor shared memory 
+ * region) and os resources for the message transfer and synchrnoisation.
+ *
+ * @see NvRmPrivXpcSendMessage()
+ * @see NvRmPrivXpcGetMessage()
+ *
+ * @param hDevice Handle to the Rm device which is required by Ddk to acquire 
+ * the resources from RM.
+ * @param phXpcMessage Pointer to the handle to Xpc message where created 
+ * Xpc message handle is stored.
+ *
+ * @retval NvSuccess Indicates the message queue is successfully created.
+ * @retval NvError_BadValue The parameter passed are incorrect.
+ * @retval NvError_InsufficientMemory Indicates that function fails to allocate the 
+ * memory for message queue.
+ * @retval NvError_MemoryMapFailed Indicates that the memory mapping for xpc 
+ * controller register failed.
+ * @retval NvError_NotSupported Indicates that the requested operation is not 
+ * supported for the given target processor/Instance.
+ * 
+ */
+ 
+ NvError NvRmPrivXpcCreate( 
+    NvRmDeviceHandle hDevice,
+    NvRmPrivXpcMessageHandle * phXpcMessage );
+
+/**
+ * Destroy the created Xpc message handle. This frees all the resources
+ * allocated for the xpc message handle.
+ *
+ * @note After calling this function client will not able to  send/receive any 
+ * message.
+ *
+ * @see NvRmPrivXpcMessageCreate()
+ *
+ * @param hXpcMessage Xpc message queue handle which need to be destroy. 
+ * This cas created when function NvRmPrivXpcMessageCreate() was called.
+ *
+ */
+
+ void NvRmPrivXpcDestroy( 
+    NvRmPrivXpcMessageHandle hXpcMessage );
+
+ NvError NvRmPrivXpcSendMessage( 
+    NvRmPrivXpcMessageHandle hXpcMessage,
+    NvU32 data );
+
+ NvU32 NvRmPrivXpcGetMessage( 
+    NvRmPrivXpcMessageHandle hXpcMessage );
+
+/**
+ * Initializes the Arbitration semaphore system for cross processor synchronization.
+ *
+ * @param hDevice The RM handle.
+ *
+ * @retval "NvError_IrqRegistrationFailed" if interupt is already registred.
+ * @retval "NvSuccess" if successfull.
+ */
+
+ NvError NvRmXpcInitArbSemaSystem( 
+    NvRmDeviceHandle hDevice );
+
+/**
+ * Tries to obtain a hw arbitration semaphore. This API is used to
+ * synchronize access to hw blocks across processors.
+ *
+ * @param modId The module that we need to cross-processor safe access to.
+ */
+
+ void NvRmXpcModuleAcquire( 
+    NvRmModuleID modId );
+
+/**
+ * Releases the arbitration semaphore corresponding to the given module id.
+ *
+ * @param modId The module that we are releasing.
+ */
+
+ void NvRmXpcModuleRelease( 
+    NvRmModuleID modId );
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif
diff --git a/arch/arm/mach-tegra/include/rm_spi_slink.h b/arch/arm/mach-tegra/include/rm_spi_slink.h
new file mode 100644
index 000000000000..61714a1333c6
--- /dev/null
+++ b/arch/arm/mach-tegra/include/rm_spi_slink.h
@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_RM_SPI_SLINK_H
+#define INCLUDED_RM_SPI_SLINK_H
+
+#include "nvrm_spi.h"
+
+typedef struct NvRmSpiTransactionInfoRec
+{
+    NvU8 *rxBuffer;
+    NvU8 *txBuffer;
+    NvU32 len;
+} NvRmSpiTransactionInfo;
+
+
+void NvRmSpiMultipleTransactions(
+    NvRmSpiHandle hRmSpi,
+    NvU32 SpiPinMap,
+    NvU32 ChipSelectId,
+    NvU32 ClockSpeedInKHz,
+    NvU32 PacketSizeInBits,
+    NvRmSpiTransactionInfo *t,
+    NvU32 NumOfTransactions);
+
+#endif // INCLUDED_RM_SPI_SLINK_H
+
diff --git a/arch/arm/mach-tegra/nvodm/Makefile b/arch/arm/mach-tegra/nvodm/Makefile
new file mode 100644
index 000000000000..fe2e42c05fde
--- /dev/null
+++ b/arch/arm/mach-tegra/nvodm/Makefile
@@ -0,0 +1,11 @@
+ccflags-y += -DNV_IS_AVP=0
+ccflags-y += -DNV_OAL=0
+ccflags-y += -DNV_USE_FUSE_CLOCK_ENABLE=0
+ifeq ($(CONFIG_MACH_TEGRA_GENERIC_DEBUG),y)
+ccflags-y += -DNV_DEBUG=1
+else
+ccflags-y += -DNV_DEBUG=0
+endif
+
+obj-y += nvodm_services.o
+obj-y += nvodm_services_os.o
diff --git a/arch/arm/mach-tegra/nvodm/nvodm_services.c b/arch/arm/mach-tegra/nvodm/nvodm_services.c
new file mode 100644
index 000000000000..c965cdd9fdbc
--- /dev/null
+++ b/arch/arm/mach-tegra/nvodm/nvodm_services.c
@@ -0,0 +1,1071 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include "nvodm_services.h"
+#include "nvrm_gpio.h"
+#include "nvrm_spi.h"
+#include "nvrm_i2c.h"
+#include "nvassert.h"
+#include "nvos.h"
+#include "nvodm_query_gpio.h"
+#include "nvodm_query_discovery.h"
+#include "nvrm_pmu.h"
+#include "nvrm_keylist.h"
+#include "nvrm_pwm.h"
+#include "nvrm_power.h"
+#include "nvrm_analog.h"
+#include "nvrm_pinmux.h"
+#include "nvrm_init.h"
+
+
+typedef struct NvOdmServicesGpioRec
+{
+    NvRmDeviceHandle hRmDev;
+    NvRmGpioHandle hGpio;
+} NvOdmServicesGpio;
+
+typedef struct NvOdmServicesSpiRec
+{
+    NvRmDeviceHandle hRmDev;
+    NvRmSpiHandle hSpi;
+    NvOdmSpiPinMap SpiPinMap;
+} NvOdmServicesSpi;
+
+typedef struct NvOdmServicesI2cRec
+{
+    NvRmDeviceHandle hRmDev;
+    NvRmI2cHandle hI2c;
+    NvOdmI2cPinMap I2cPinMap;
+} NvOdmServicesI2c;
+
+typedef struct NvOdmServicesPwmRec
+{
+    NvRmDeviceHandle hRmDev;
+    NvRmPwmHandle hPwm;
+} NvOdmServicesPwm;
+// ----------------------- GPIO IMPLEMENTATION ------------
+
+NvOdmServicesGpioHandle NvOdmGpioOpen(void)
+{
+    NvError e;
+    NvOdmServicesGpio *pOdmServices = NULL;
+
+    // Allocate memory for the handle.
+    pOdmServices = NvOsAlloc(sizeof(NvOdmServicesGpio));
+    if (!pOdmServices)
+        return NULL;
+    NvOsMemset(pOdmServices, 0, sizeof(NvOdmServicesGpio));
+
+    // Open RM device and RM GPIO handles
+    NV_CHECK_ERROR_CLEANUP(NvRmOpen(&pOdmServices->hRmDev, 0));
+    NV_CHECK_ERROR_CLEANUP(NvRmGpioOpen(
+        pOdmServices->hRmDev, &pOdmServices->hGpio));
+
+    return pOdmServices;
+
+fail:
+    NvOdmGpioClose(pOdmServices);
+    return NULL;
+}
+
+void NvOdmGpioClose(NvOdmServicesGpioHandle hOdmGpio)
+{
+    if (!hOdmGpio)
+        return;
+    NvRmGpioClose(hOdmGpio->hGpio);
+    NvRmClose(hOdmGpio->hRmDev);
+    NvOsFree(hOdmGpio);
+}
+
+NvOdmGpioPinHandle 
+NvOdmGpioAcquirePinHandle(NvOdmServicesGpioHandle hOdmGpio, 
+        NvU32 Port, NvU32 Pin)
+{
+    NvError e;
+    NvRmGpioPinHandle hGpioPin;
+
+    if (!hOdmGpio || Port == NVODM_GPIO_INVALID_PORT || Pin == NVODM_GPIO_INVALID_PIN)
+        return NULL;
+
+    NV_CHECK_ERROR_CLEANUP(NvRmGpioAcquirePinHandle(
+            hOdmGpio->hGpio, Port, Pin, &hGpioPin)); 
+
+    return (NvOdmGpioPinHandle)hGpioPin;
+
+fail:
+    return NULL;
+}
+
+void
+NvOdmGpioReleasePinHandle(NvOdmServicesGpioHandle hOdmGpio, 
+        NvOdmGpioPinHandle hPin)
+{
+    NvRmGpioPinHandle hRmPin = (NvRmGpioPinHandle)hPin;
+    if (hOdmGpio && hPin)
+        NvRmGpioReleasePinHandles(hOdmGpio->hGpio, &hRmPin, 1);
+}
+
+void
+NvOdmGpioSetState(
+    NvOdmServicesGpioHandle hOdmGpio,
+    NvOdmGpioPinHandle hGpioPin,
+    NvU32 PinValue)
+{
+    NvRmGpioPinState val = (NvRmGpioPinState)PinValue;
+    NvRmGpioPinHandle hRmPin = (NvRmGpioPinHandle)hGpioPin;
+    if (hOdmGpio == NULL || hGpioPin == NULL)
+        return;
+
+    NvRmGpioWritePins( hOdmGpio->hGpio, &hRmPin, &val, 1);
+}
+
+void
+NvOdmGpioGetState(
+    NvOdmServicesGpioHandle hOdmGpio,
+    NvOdmGpioPinHandle hGpioPin,
+    NvU32 *PinValue)
+{
+    NvRmGpioPinState val;
+    NvRmGpioPinHandle hRmPin = (NvRmGpioPinHandle)hGpioPin;
+
+    if (hOdmGpio == NULL || hGpioPin == NULL)
+        return;
+
+    NvRmGpioReadPins(hOdmGpio->hGpio, &hRmPin, &val, 1);
+    *PinValue = val;
+}
+
+void
+NvOdmGpioConfig( 
+    NvOdmServicesGpioHandle hOdmGpio, 
+    NvOdmGpioPinHandle hGpioPin,
+    NvOdmGpioPinMode mode)
+{
+    NvRmGpioPinHandle hRmPin = (NvRmGpioPinHandle)hGpioPin;
+    if (hOdmGpio == NULL || hGpioPin == NULL)
+        return;
+
+    NV_ASSERT_SUCCESS(
+        NvRmGpioConfigPins(hOdmGpio->hGpio, &hRmPin, 1, (NvRmGpioPinMode)mode)
+    );
+}
+
+NvBool
+NvOdmGpioInterruptRegister(NvOdmServicesGpioHandle hOdmGpio,
+    NvOdmServicesGpioIntrHandle *hGpioIntr,
+    NvOdmGpioPinHandle hGpioPin,
+    NvOdmGpioPinMode Mode, 
+    NvOdmInterruptHandler Callback,
+    void *arg,
+    NvU32 DebounceTime)
+{
+    NvRmGpioInterruptHandle handle;
+    NvError err;
+
+    err = NvRmGpioInterruptRegister(
+        hOdmGpio->hGpio,
+        hOdmGpio->hRmDev,
+        (NvRmGpioPinHandle)hGpioPin,
+        (NvOsInterruptHandler)Callback,
+        (NvRmGpioPinMode)Mode,
+        arg,
+        &handle,
+        DebounceTime);
+
+    if (err == NvSuccess)
+    {
+        *hGpioIntr = (NvOdmServicesGpioIntrHandle)handle;
+        err = NvRmGpioInterruptEnable(handle);
+        if (err != NvSuccess)
+        {
+            NvRmGpioInterruptUnregister(hOdmGpio->hGpio,
+                hOdmGpio->hRmDev,
+                (NvRmGpioInterruptHandle)handle);
+            *hGpioIntr = NULL;
+            return NV_FALSE;
+        }
+        return NV_TRUE;
+    }
+    else
+    {
+        *hGpioIntr = NULL;
+        return NV_FALSE;
+    }
+}
+
+void
+NvOdmGpioInterruptMask(NvOdmServicesGpioIntrHandle handle, NvBool mask)
+{
+    NvRmGpioInterruptMask( (NvRmGpioInterruptHandle)handle, mask);
+}
+
+void
+NvOdmGpioInterruptUnregister(NvOdmServicesGpioHandle hOdmGpio,
+    NvOdmGpioPinHandle hGpioPin,
+    NvOdmServicesGpioIntrHandle handle)
+{
+    NvRmGpioInterruptUnregister(hOdmGpio->hGpio,
+            hOdmGpio->hRmDev,
+            (NvRmGpioInterruptHandle)handle);
+}
+
+void NvOdmGpioInterruptDone( NvOdmServicesGpioIntrHandle handle )
+{
+    NvRmGpioInterruptDone((NvRmGpioInterruptHandle)handle);
+}
+
+NvBool
+NvOdmExternalClockConfig(
+    NvU64 Guid,
+    NvBool EnableTristate,
+    NvU32 *pInstances,
+    NvU32 *pFrequencies,
+    NvU32 *pNum)
+{
+    const NvOdmPeripheralConnectivity *pConn = NULL;
+    const NvOdmIoAddress *pIo = NULL;
+    const NvU32 *pOdmConfigs = NULL;
+    NvU32 NumOdmConfigs;
+    NvRmDeviceHandle hRmDev = NULL;
+    NvBool result = NV_TRUE;
+    NvU32 i;
+    NvU32 ClockListEntries = 0;
+
+    NV_ASSERT(pInstances);
+    NV_ASSERT(pFrequencies);
+    NV_ASSERT(pNum);
+
+    pConn = NvOdmPeripheralGetGuid(Guid);
+    NvOdmQueryPinMux(NvOdmIoModule_ExternalClock, &pOdmConfigs, &NumOdmConfigs);
+    
+    if (NvRmOpen(&hRmDev,0)!=NvSuccess)
+        return NV_FALSE;
+
+    if (pConn && pConn->AddressList && pConn->NumAddress)
+    {
+        NvBool found = NV_FALSE;
+        pIo = pConn->AddressList;
+        for (i=0; i<pConn->NumAddress; pIo++, i++)
+        {
+            if (pIo->Interface == NvOdmIoModule_ExternalClock)
+            {
+                found = NV_TRUE;
+
+                if (pIo->Instance >= NumOdmConfigs)
+                    result = NV_FALSE;
+                else 
+                {
+                    pInstances[ClockListEntries] = pIo->Instance;
+                    pFrequencies[ClockListEntries] = NvRmExternalClockConfig(
+                        hRmDev, NvOdmIoModule_ExternalClock, pIo->Instance, 
+                        pOdmConfigs[pIo->Instance], EnableTristate);
+                    ClockListEntries++;
+                }
+            }
+        }
+        result = result && found;
+    }
+    else
+        result = NV_FALSE;
+
+    *pNum = ClockListEntries;
+    NvRmClose(hRmDev);
+    return result;
+}
+
+NvBool NvOdmGetStraps(NvOdmStrapGroup StrapGroup, NvU32* pStrapValue)
+{
+/*
+    NvRmDeviceHandle hRmDevice = NULL;
+    NV_ASSERT(NvOdmStrapGroup_Num == NvRmStrapGroup_Num);
+
+    if (NvRmOpen(&hRmDevice, 0) == NvSuccess)
+    {
+        if (NvRmGetStraps(
+            hRmDevice, (NvRmStrapGroup)StrapGroup, pStrapValue) == NvSuccess)
+            return NV_TRUE;
+    }
+*/    
+    return NV_FALSE;
+}
+
+// ----------------------- I2C IMPLEMENTATION ------------
+
+// Maximum number of bytes that can be sent between the i2c start and stop conditions
+#define NVODM_I2C_PACKETSIZE   8
+
+// Maximum number of bytes that can be sent between the i2c start and repeat start condition.
+#define NVODM_I2C_REPEAT_START_PACKETSIZE   4
+
+NvOdmServicesI2cHandle
+NvOdmI2cOpen(
+    NvOdmIoModule OdmIoModuleId,
+    NvU32 instance)
+{
+    NvError e;
+    NvOdmServicesI2c *pOdmServices = NULL;
+    const NvU32 *pOdmConfigs;
+    NvU32 NumOdmConfigs;
+
+    if (OdmIoModuleId != NvOdmIoModule_I2c &&
+        OdmIoModuleId != NvOdmIoModule_I2c_Pmu)
+        return NULL;
+    
+    NvOdmQueryPinMux(OdmIoModuleId, &pOdmConfigs, &NumOdmConfigs);
+    if (instance>=NumOdmConfigs || !pOdmConfigs[instance] ||
+        (pOdmConfigs[instance]==NvOdmI2cPinMap_Multiplexed))
+        return NULL;
+
+    // Allocate memory for the handle.
+    pOdmServices = NvOsAlloc(sizeof(NvOdmServicesI2c));
+    if (!pOdmServices)
+        return NULL;
+    NvOsMemset(pOdmServices, 0, sizeof(NvOdmServicesI2c));
+
+    // Open RM device and RM I2C handles
+    NV_CHECK_ERROR_CLEANUP(NvRmOpen(&pOdmServices->hRmDev, 0));
+    NV_CHECK_ERROR_CLEANUP(NvRmI2cOpen(
+        pOdmServices->hRmDev, OdmIoModuleId, instance, &pOdmServices->hI2c));
+
+    pOdmServices->I2cPinMap = 0;
+    return pOdmServices;
+
+fail:
+    NvOdmI2cClose(pOdmServices);
+    return NULL;
+}
+
+NvOdmServicesI2cHandle
+NvOdmI2cPinMuxOpen(
+    NvOdmIoModule OdmIoModuleId,
+    NvU32 instance,
+    NvOdmI2cPinMap PinMap)
+{
+    NvError e;
+    NvOdmServicesI2c *pOdmServices = NULL;
+    const NvU32 *pOdmConfigs;
+    NvU32 NumOdmConfigs;
+
+    if (OdmIoModuleId != NvOdmIoModule_I2c &&
+        OdmIoModuleId != NvOdmIoModule_I2c_Pmu)
+        return NULL;
+    
+    NvOdmQueryPinMux(OdmIoModuleId, &pOdmConfigs, &NumOdmConfigs);
+    if (instance>=NumOdmConfigs ||
+        (pOdmConfigs[instance]!=NvOdmI2cPinMap_Multiplexed))
+        return NULL;
+
+    // Allocate memory for the handle.
+    pOdmServices = NvOsAlloc(sizeof(NvOdmServicesI2c));
+    if (!pOdmServices)
+        return NULL;
+    NvOsMemset(pOdmServices, 0, sizeof(NvOdmServicesI2c));
+
+    // Open RM device and RM I2C handles
+    NV_CHECK_ERROR_CLEANUP(NvRmOpen(&pOdmServices->hRmDev, 0));
+    NV_CHECK_ERROR_CLEANUP(NvRmI2cOpen(
+        pOdmServices->hRmDev, OdmIoModuleId, instance, &pOdmServices->hI2c));
+
+    pOdmServices->I2cPinMap = PinMap;
+    return pOdmServices;
+
+fail:
+    NvOdmI2cClose(pOdmServices);
+    return NULL;
+}
+
+void NvOdmI2cClose(NvOdmServicesI2cHandle hOdmI2c)
+{
+    if (!hOdmI2c)
+        return;
+    NvRmI2cClose(hOdmI2c->hI2c);
+    NvRmClose(hOdmI2c->hRmDev);
+    NvOsFree(hOdmI2c);
+}
+
+
+NvOdmI2cStatus
+NvOdmI2cTransaction(
+    NvOdmServicesI2cHandle hOdmI2c,
+    NvOdmI2cTransactionInfo *TransactionInfo,
+    NvU32 NumberOfTransactions,
+    NvU32 ClockSpeedKHz,
+    NvU32 WaitTimeoutInMilliSeconds)
+{
+    NvU32 len = 0;
+    NvU8 *buffer = NULL;
+    NvU8 stack_buffer[64];
+    NvRmI2cTransactionInfo stack_t[8];
+    NvRmI2cTransactionInfo *t = NULL;
+    NvOdmI2cStatus status = NvOdmI2cStatus_Success;
+    NvError err;
+    NvU32 i;
+    NvU8 *tempBuffer;
+
+    NV_ASSERT(hOdmI2c);
+    NV_ASSERT(TransactionInfo);
+    NV_ASSERT(NumberOfTransactions);
+    NV_ASSERT(WaitTimeoutInMilliSeconds);
+
+    for (i=0; i < NumberOfTransactions; i++)
+    {
+        len += TransactionInfo[i].NumBytes;
+    }
+
+    if (len > 64)
+    {
+        buffer = NvOsAlloc(len);
+        if (!buffer)
+        {
+            status = NvOdmI2cStatus_InternalError;
+            goto fail;
+        }
+    } else
+    {
+        buffer = stack_buffer;
+    }
+
+    if (NumberOfTransactions > 8)
+    {
+        t = NvOsAlloc(sizeof(NvRmI2cTransactionInfo) * NumberOfTransactions);
+        if (!t)
+        {
+            status = NvOdmI2cStatus_InternalError;
+            goto fail;
+        }
+    } else
+    {
+        t = stack_t;
+    }
+
+    NvOsMemset(buffer, 0, len);
+    NvOsMemset(t, 0, sizeof(NvRmI2cTransactionInfo) * NumberOfTransactions);
+
+    tempBuffer = buffer;
+    for (i=0; i < NumberOfTransactions; i++)
+    {
+        if ( TransactionInfo[i].Flags & NVODM_I2C_SOFTWARE_CONTROLLER )
+        {
+            t[i].Flags |= NVRM_I2C_SOFTWARE_CONTROLLER;
+        } 
+
+        if ( TransactionInfo[i].Flags & NVODM_I2C_USE_REPEATED_START )
+        {
+            t[i].Flags |= NVRM_I2C_NOSTOP;
+        } 
+
+        if ( TransactionInfo[i].Flags & NVODM_I2C_NO_ACK )
+        {
+            t[i].Flags |= NVRM_I2C_NOACK;
+        } 
+
+        if ( TransactionInfo[i].Flags & NVODM_I2C_IS_WRITE )
+        {
+            t[i].Flags |= NVRM_I2C_WRITE;
+            /* Copy the data */
+            NvOsMemcpy(tempBuffer, TransactionInfo[i].Buf, TransactionInfo[i].NumBytes);
+        } else
+        {
+            t[i].Flags |= NVRM_I2C_READ;
+        }
+
+        tempBuffer += TransactionInfo[i].NumBytes;
+        t[i].NumBytes = TransactionInfo[i].NumBytes;
+        t[i].Is10BitAddress = (NvBool)(TransactionInfo[i].Flags & NVODM_I2C_IS_10_BIT_ADDRESS);
+        t[i].Address = (TransactionInfo[i].Address) & ~0x1;
+    }
+
+    err = NvRmI2cTransaction(hOdmI2c->hI2c, 
+            hOdmI2c->I2cPinMap,
+            WaitTimeoutInMilliSeconds,
+            ClockSpeedKHz,
+            buffer,
+            len,
+            t,
+            NumberOfTransactions);
+    if (err != NvSuccess)
+    {    
+        switch ( err )
+        {
+            case NvError_I2cDeviceNotFound:
+                status =  NvOdmI2cStatus_SlaveNotFound;
+                break;
+            case NvError_I2cReadFailed:
+                status = NvOdmI2cStatus_ReadFailed;
+                break;
+            case NvError_I2cWriteFailed:
+                status = NvOdmI2cStatus_WriteFailed;
+                break;
+            case NvError_I2cArbitrationFailed:
+                status = NvOdmI2cStatus_ArbitrationFailed;
+                break;
+            case NvError_I2cInternalError:
+                status = NvOdmI2cStatus_InternalError;
+                break;
+            case NvError_Timeout:
+            default:
+                status = NvOdmI2cStatus_Timeout;
+                break;
+        }
+        goto fail;
+    }
+
+    tempBuffer = buffer;
+    for (i=0; i < NumberOfTransactions; i++)
+    {
+        if (t[i].Flags & NVRM_I2C_READ)
+        {
+            NvOsMemcpy(TransactionInfo[i].Buf, tempBuffer, TransactionInfo[i].NumBytes);
+        }
+        tempBuffer += TransactionInfo[i].NumBytes;
+    }
+
+fail:
+
+    if (t != NULL && t != stack_t)
+    {
+        NvOsFree(t);
+    }
+
+    if (buffer != NULL && buffer != stack_buffer)
+    {
+        NvOsFree(buffer);
+    }
+
+    return status;
+}
+
+NvOdmServicesSpiHandle NvOdmSpiOpen(NvOdmIoModule OdmIoModule, NvU32 ControllerId)
+{
+    NvError e;
+    NvOdmServicesSpi *pOdmServices;
+    const NvU32 *pOdmConfigs;
+    NvU32 NumOdmConfigs;
+
+    // Supporting the odm_sflash and odm_spi only.
+    if (OdmIoModule != NvOdmIoModule_Sflash &&
+        OdmIoModule != NvOdmIoModule_Spi)
+        return NULL;
+
+    NvOdmQueryPinMux(OdmIoModule, &pOdmConfigs, &NumOdmConfigs);
+    if (ControllerId>=NumOdmConfigs || !pOdmConfigs[ControllerId] ||
+        (pOdmConfigs[ControllerId]==NvOdmSpiPinMap_Multiplexed))
+        return NULL;
+
+    // Allocate memory for the handle.
+    pOdmServices = NvOsAlloc(sizeof(NvOdmServicesSpi));
+    if (!pOdmServices)
+        return NULL;
+    NvOsMemset(pOdmServices, 0, sizeof(NvOdmServicesSpi));
+
+    // Open RM device and RM SPI handles
+    NV_CHECK_ERROR_CLEANUP(NvRmOpen(&pOdmServices->hRmDev, 0));
+    NV_CHECK_ERROR_CLEANUP(NvRmSpiOpen(
+        pOdmServices->hRmDev, OdmIoModule, ControllerId, NV_TRUE, &pOdmServices->hSpi));
+
+    pOdmServices->SpiPinMap = 0;
+    return pOdmServices;
+
+fail:
+    NvOdmSpiClose(pOdmServices);
+    return NULL;
+}
+
+NvOdmServicesSpiHandle
+NvOdmSpiPinMuxOpen(NvOdmIoModule OdmIoModule, 
+                   NvU32 ControllerId, 
+                   NvOdmSpiPinMap PinMap)
+{
+    NvError e;
+    NvOdmServicesSpi *pOdmServices;
+    const NvU32 *pOdmConfigs;
+    NvU32 NumOdmConfigs;
+
+    if (OdmIoModule != NvOdmIoModule_Sflash &&
+        OdmIoModule != NvOdmIoModule_Spi)
+        return NULL;
+
+    NvOdmQueryPinMux(OdmIoModule, &pOdmConfigs, &NumOdmConfigs);
+    if ((ControllerId >= NumOdmConfigs) ||
+        (pOdmConfigs[ControllerId]!=NvOdmSpiPinMap_Multiplexed))
+        return NULL;
+
+    // Allocate memory for the handle.
+    pOdmServices = NvOsAlloc(sizeof(NvOdmServicesSpi));
+    if (!pOdmServices)
+        return NULL;
+    NvOsMemset(pOdmServices, 0, sizeof(NvOdmServicesSpi));
+
+    // Open RM device and RM SPI handles
+    NV_CHECK_ERROR_CLEANUP(NvRmOpen(&pOdmServices->hRmDev, 0));
+    NV_CHECK_ERROR_CLEANUP(NvRmSpiOpen(
+        pOdmServices->hRmDev, OdmIoModule, ControllerId, NV_TRUE, &pOdmServices->hSpi));
+
+    pOdmServices->SpiPinMap = PinMap;
+
+    return pOdmServices;
+
+fail:
+    NvOdmSpiClose(pOdmServices);
+    return NULL;
+}
+
+NvOdmServicesSpiHandle 
+NvOdmSpiSlaveOpen(
+    NvOdmIoModule OdmIoModule, 
+    NvU32 ControllerId)
+{
+    NvError e;
+    NvOdmServicesSpi *pOdmServices;
+    const NvU32 *pOdmConfigs;
+    NvU32 NumOdmConfigs;
+
+    // Supporting the odm_sflash and odm_spi only.
+    if (OdmIoModule != NvOdmIoModule_Sflash &&
+        OdmIoModule != NvOdmIoModule_Spi)
+        return NULL;
+
+    NvOdmQueryPinMux(OdmIoModule, &pOdmConfigs, &NumOdmConfigs);
+    if (ControllerId>=NumOdmConfigs || !pOdmConfigs[ControllerId] ||
+        (pOdmConfigs[ControllerId]==NvOdmSpiPinMap_Multiplexed))
+        return NULL;
+
+    // Allocate memory for the handle.
+    pOdmServices = NvOsAlloc(sizeof(NvOdmServicesSpi));
+    if (!pOdmServices)
+        return NULL;
+    NvOsMemset(pOdmServices, 0, sizeof(NvOdmServicesSpi));
+
+    // Open RM device and RM SPI handles
+    NV_CHECK_ERROR_CLEANUP(NvRmOpen(&pOdmServices->hRmDev, 0));
+    NV_CHECK_ERROR_CLEANUP(NvRmSpiOpen(
+        pOdmServices->hRmDev, OdmIoModule, ControllerId, NV_FALSE, &pOdmServices->hSpi));
+
+    pOdmServices->SpiPinMap = 0;
+    return pOdmServices;
+
+fail:
+    NvOdmSpiClose(pOdmServices);
+    return NULL;
+
+}
+
+
+
+void NvOdmSpiClose(NvOdmServicesSpiHandle hOdmSpi)
+{
+    if (!hOdmSpi)
+        return;
+
+    // clean up
+    NvRmSpiClose(hOdmSpi->hSpi);
+    NvRmClose(hOdmSpi->hRmDev);
+    NvOsFree(hOdmSpi);
+}
+
+void
+NvOdmSpiTransaction(
+    NvOdmServicesSpiHandle hOdmSpi,
+    NvU32 ChipSelect,
+    NvU32 ClockSpeedInKHz,
+    NvU8 *ReadBuf,
+    const NvU8 *WriteBuf,
+    NvU32 Size,
+    NvU32 PacketSize)
+{
+    NvRmSpiTransaction(hOdmSpi->hSpi, hOdmSpi->SpiPinMap, ChipSelect,
+        ClockSpeedInKHz, ReadBuf, (NvU8 *)WriteBuf, Size, PacketSize);
+}
+
+NvBool 
+NvOdmSpiSlaveStartTransaction( 
+    NvOdmServicesSpiHandle hOdmSpi,
+    NvU32 ChipSelectId,
+    NvU32 ClockSpeedInKHz,
+    NvBool IsReadTransfer,
+    NvU8 * pWriteBuffer,
+    NvU32 BytesRequested,
+    NvU32 PacketSizeInBits )
+{
+    NvError Error;
+    Error = NvRmSpiStartTransaction(hOdmSpi->hSpi, ChipSelectId,
+        ClockSpeedInKHz, IsReadTransfer, (NvU8 *)pWriteBuffer, 
+        BytesRequested, PacketSizeInBits);
+    if (Error)
+        return NV_FALSE;
+    return NV_TRUE;        
+    
+}
+
+NvBool 
+NvOdmSpiSlaveGetTransactionData( 
+    NvOdmServicesSpiHandle hOdmSpi,
+    NvU8 * pReadBuffer,
+    NvU32 BytesRequested,
+    NvU32 * pBytesTransfererd,
+    NvU32 WaitTimeout )
+{
+    NvError Error;
+    Error = NvRmSpiGetTransactionData(hOdmSpi->hSpi, pReadBuffer, 
+                BytesRequested, pBytesTransfererd, WaitTimeout);
+
+    if (Error)
+        return NV_FALSE;
+    return NV_TRUE;
+}
+
+void
+NvOdmSpiSetSignalMode(
+    NvOdmServicesSpiHandle hOdmSpi,
+    NvU32 ChipSelectId,
+    NvOdmQuerySpiSignalMode SpiSignalMode)
+{
+    NvRmSpiSetSignalMode(hOdmSpi->hSpi, ChipSelectId, SpiSignalMode);
+}
+
+
+
+
+NvOdmServicesPmuHandle NvOdmServicesPmuOpen(void)
+{
+    NvRmDeviceHandle hRmDev;
+
+    if (NvRmOpen(&hRmDev, 0) != NvError_Success)
+    {
+        return (NvOdmServicesPmuHandle)0;
+    }
+
+    return (NvOdmServicesPmuHandle)hRmDev;
+}
+
+void NvOdmServicesPmuClose(NvOdmServicesPmuHandle handle)
+{
+    NvRmClose((NvRmDeviceHandle)handle);
+    return;
+}
+
+void NvOdmServicesPmuGetCapabilities( 
+        NvOdmServicesPmuHandle handle,
+        NvU32 vddId, 
+        NvOdmServicesPmuVddRailCapabilities *pCapabilities )
+{
+    NvRmDeviceHandle hRmDev = (NvRmDeviceHandle)handle;
+
+    NV_ASSERT(sizeof(NvRmPmuVddRailCapabilities) == 
+            sizeof(NvOdmServicesPmuVddRailCapabilities));
+
+    NvRmPmuGetCapabilities(hRmDev, vddId, 
+        (NvRmPmuVddRailCapabilities *)pCapabilities);
+    return;
+}
+
+void NvOdmServicesPmuGetVoltage( 
+        NvOdmServicesPmuHandle handle,
+        NvU32 vddId, 
+        NvU32 * pMilliVolts )
+{
+    NvRmDeviceHandle hRmDev = (NvRmDeviceHandle)handle;
+    NvRmPmuGetVoltage(hRmDev, vddId, pMilliVolts);
+}
+
+void NvOdmServicesPmuSetVoltage( 
+        NvOdmServicesPmuHandle handle,
+        NvU32 vddId, 
+        NvU32 MilliVolts, 
+        NvU32 * pSettleMicroSeconds )
+{
+    NvRmDeviceHandle hRmDev = (NvRmDeviceHandle)handle;
+    NvRmPmuSetVoltage(hRmDev, vddId, MilliVolts, pSettleMicroSeconds);
+}
+
+void NvOdmServicesPmuSetSocRailPowerState(
+        NvOdmServicesPmuHandle handle,
+        NvU32 vddId, 
+        NvBool Enable )
+{
+    NvRmDeviceHandle hRmDev = (NvRmDeviceHandle)handle;
+    NvRmPmuSetSocRailPowerState(hRmDev, vddId, Enable);
+}
+
+NvBool 
+NvOdmServicesPmuGetBatteryStatus(
+    NvOdmServicesPmuHandle handle,
+    NvOdmServicesPmuBatteryInstance batteryInst,
+    NvU8 * pStatus)
+{
+    return NvRmPmuGetBatteryStatus(
+        (NvRmDeviceHandle)handle,
+        (NvRmPmuBatteryInstance)batteryInst,
+        pStatus);
+}
+
+NvBool
+NvOdmServicesPmuGetBatteryData(
+    NvOdmServicesPmuHandle handle,
+    NvOdmServicesPmuBatteryInstance batteryInst,
+    NvOdmServicesPmuBatteryData * pData)
+{
+    return NvRmPmuGetBatteryData(
+        (NvRmDeviceHandle)handle,
+        (NvRmPmuBatteryInstance)batteryInst,
+        (NvRmPmuBatteryData *)pData);
+}
+
+void
+NvOdmServicesPmuGetBatteryFullLifeTime(
+    NvOdmServicesPmuHandle handle,
+    NvOdmServicesPmuBatteryInstance batteryInst,
+    NvU32 * pLifeTime)
+{
+    NvRmPmuGetBatteryFullLifeTime(
+        (NvRmDeviceHandle)handle,
+        (NvRmPmuBatteryInstance)batteryInst,
+        pLifeTime);
+}
+
+void
+NvOdmServicesPmuGetBatteryChemistry(
+    NvOdmServicesPmuHandle handle,
+    NvOdmServicesPmuBatteryInstance batteryInst,
+    NvOdmServicesPmuBatteryChemistry * pChemistry)
+{
+    NvRmPmuGetBatteryChemistry(
+        (NvRmDeviceHandle)handle,
+        (NvRmPmuBatteryInstance)batteryInst,
+        (NvRmPmuBatteryChemistry *)pChemistry);
+}
+
+void 
+NvOdmServicesPmuSetChargingCurrentLimit( 
+    NvOdmServicesPmuHandle handle,
+    NvOdmServicesPmuChargingPath ChargingPath,
+    NvU32 ChargingCurrentLimitMa,
+    NvOdmUsbChargerType ChargerType)
+{
+    NvRmPmuSetChargingCurrentLimit(
+        (NvRmDeviceHandle)handle,
+        (NvRmPmuChargingPath)ChargingPath,
+        ChargingCurrentLimitMa,
+        ChargerType);
+}
+
+// ----------------------- PWM IMPLEMENTATION ------------
+
+NvOdmServicesPwmHandle NvOdmPwmOpen(void)
+{
+    NvError e;
+    NvOdmServicesPwm *pOdmServices = NULL;
+
+    // Allocate memory for the handle.
+    pOdmServices = NvOsAlloc(sizeof(NvOdmServicesPwm));
+    if (!pOdmServices)
+        return NULL;
+    NvOsMemset(pOdmServices, 0, sizeof(NvOdmServicesPwm));
+
+    // Open RM device and RM PWM handles
+    NV_CHECK_ERROR_CLEANUP(NvRmOpen(&pOdmServices->hRmDev, 0));
+    NV_CHECK_ERROR_CLEANUP(NvRmPwmOpen(
+        pOdmServices->hRmDev, &pOdmServices->hPwm));
+
+    return pOdmServices;
+
+fail:
+    NvOdmPwmClose(pOdmServices);
+    return NULL;
+}
+
+void NvOdmPwmClose(NvOdmServicesPwmHandle hOdmPwm)
+{
+    if (!hOdmPwm)
+        return;
+    NvRmPwmClose(hOdmPwm->hPwm);
+    NvRmClose(hOdmPwm->hRmDev);
+    NvOsFree(hOdmPwm);
+}
+
+void
+NvOdmPwmConfig(NvOdmServicesPwmHandle hOdmPwm,
+    NvOdmPwmOutputId OutputId,
+    NvOdmPwmMode Mode,            
+    NvU32 DutyCycle,
+    NvU32 *pRequestedFreqHzOrPeriod,
+    NvU32 *pCurrentFreqHzOrPeriod)
+{
+    NvU32 RequestedFreqHzOrPeriod = 0;
+
+    if (pRequestedFreqHzOrPeriod == NULL)
+        RequestedFreqHzOrPeriod = NvRmFreqMaximum;
+    else
+        RequestedFreqHzOrPeriod = *pRequestedFreqHzOrPeriod;
+
+    NvRmPwmConfig(hOdmPwm->hPwm,
+        (NvRmPwmOutputId)OutputId, 
+        (NvRmPwmMode)Mode,
+        DutyCycle,
+        RequestedFreqHzOrPeriod,
+        pCurrentFreqHzOrPeriod);
+}
+
+void
+NvOdmEnableUsbPhyPowerRail(
+    NvBool Enable)
+{
+    NvU32 i;
+    NvU32 settle_time_us;
+    NvU64 guid = NV_VDD_USB_ODM_ID;
+    NvOdmPeripheralConnectivity const *pConnectivity;
+    NvRmDeviceHandle hRmDevice;
+    /* get the connectivity info */
+    pConnectivity = NvOdmPeripheralGetGuid( guid );
+    if( !pConnectivity )
+    {
+        // Do nothing if no power rail info is discovered
+        return;
+    }
+
+    if (NvRmOpen(&hRmDevice, 0) != NvSuccess)
+    {
+        return;
+    }
+
+    /* enable the power rail */
+    if (Enable)
+    {
+        for( i = 0; i < pConnectivity->NumAddress; i++ )
+        {
+            if( pConnectivity->AddressList[i].Interface == NvOdmIoModule_Vdd )
+            {
+                NvRmPmuVddRailCapabilities cap;
+
+                /* address is the vdd rail id */
+                NvRmPmuGetCapabilities(
+                    hRmDevice,
+                    pConnectivity->AddressList[i].Address, &cap );
+
+                /* set the rail volatage to the recommended */
+                NvRmPmuSetVoltage(
+                    hRmDevice, pConnectivity->AddressList[i].Address,
+                    cap.requestMilliVolts, &settle_time_us );
+
+                /* wait for the rail to settle */
+                NvOsWaitUS( settle_time_us );
+            }
+        }
+    }
+    else
+    {
+        for( i = 0; i < pConnectivity->NumAddress; i++ )
+        {
+            if( pConnectivity->AddressList[i].Interface == NvOdmIoModule_Vdd )
+            {
+                /* set the rail volatage to the recommended */
+                NvRmPmuSetVoltage(
+                    hRmDevice, pConnectivity->AddressList[i].Address,
+                    ODM_VOLTAGE_OFF, 0 );
+            }
+        }
+    }
+
+
+    NvRmClose(hRmDevice);
+}
+
+
+void NvOdmEnableOtgCircuitry(NvBool Enable)
+{
+    const NvOdmUsbProperty *pProperty = NULL;
+    static NvBool s_PowerEnabled = NV_FALSE;
+
+    if ((s_PowerEnabled && Enable) || (!s_PowerEnabled && !Enable))
+        return;
+
+    pProperty = NvOdmQueryGetUsbProperty(NvOdmIoModule_Usb, 0);
+
+    if (pProperty && (!pProperty->UseInternalPhyWakeup) &&
+        ((pProperty->UsbMode == NvOdmUsbModeType_Device) ||
+         (pProperty->UsbMode == NvOdmUsbModeType_OTG)))
+    {
+        NvOdmEnableUsbPhyPowerRail(s_PowerEnabled = Enable);
+    }
+}
+
+
+NvBool NvOdmUsbIsConnected(void)
+{
+    NV_ASSERT("Not Supported ");
+    return NV_FALSE;
+}
+
+NvOdmUsbChargerType NvOdmUsbChargingType(NvU32 Instance)
+{
+    NV_ASSERT("Not Supported ");
+    return NvOdmUsbChargerType_Dummy;
+}
+
+NvU32 NvOdmServicesGetKeyValue(
+    NvOdmServicesKeyListHandle handle,
+    NvU32 Key)
+{
+    return NvRmGetKeyValue((NvRmDeviceHandle)handle, Key);
+}
+
+NvBool NvOdmServicesSetKeyValuePair(
+    NvOdmServicesKeyListHandle handle,
+    NvU32 Key,
+    NvU32 Value)
+{
+    if (NvRmSetKeyValuePair((NvRmDeviceHandle)handle, Key, Value) != NvSuccess)
+    {
+        return NV_FALSE;
+    }
+    return NV_TRUE;
+}
+
+NvOdmServicesKeyListHandle
+NvOdmServicesKeyListOpen(void)
+{
+    NvRmDeviceHandle hRm;
+    NvError Error;
+
+    Error = NvRmOpen(&hRm, 0);
+    if (Error != NvSuccess)
+    {
+        return NULL;
+    }
+    return (NvOdmServicesKeyListHandle)hRm;
+}
+
+void NvOdmServicesKeyListClose(NvOdmServicesKeyListHandle handle)
+{
+    NvRmClose((NvRmDeviceHandle)handle);
+}
+
diff --git a/arch/arm/mach-tegra/nvodm/nvodm_services_os.c b/arch/arm/mach-tegra/nvodm/nvodm_services_os.c
new file mode 100644
index 000000000000..d2e090627f2f
--- /dev/null
+++ b/arch/arm/mach-tegra/nvodm/nvodm_services_os.c
@@ -0,0 +1,247 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include "nvcommon.h"
+#include "nvodm_services.h"
+#include "nvos.h"
+#include "nvassert.h"
+
+void NvOdmOsPrintf( const char *format, ...)
+{
+
+    va_list ap;
+
+    va_start(ap, format);
+    NvOsDebugVprintf(format, ap);
+    va_end(ap);
+
+}
+
+void NvOdmOsDebugPrintf( const char *format, ... )
+{
+#if NV_DEBUG
+    va_list ap;
+    va_start( ap, format );
+    NvOsDebugVprintf( format, ap );
+    va_end( ap );
+#endif
+}
+
+void *NvOdmOsAlloc(size_t size)
+{
+    return NvOsAlloc( size );
+}
+
+void NvOdmOsFree(void *ptr)
+{
+    NvOsFree( ptr );
+}
+
+void NvOdmOsMemcpy(void *dest, const void *src, size_t size)
+{
+    NvOsMemcpy(dest, src, size);
+}
+
+void NvOdmOsMemset(void *s, NvU8 c, size_t size)
+{
+    NvOsMemset(s, c, size);
+}
+
+NvOdmOsMutexHandle NvOdmOsMutexCreate(void)
+{
+    NvError err;
+    NvOsMutexHandle m;
+
+    err = NvOsMutexCreate(&m);
+    if( err == NvSuccess )
+    {
+        return (NvOdmOsMutexHandle)m;
+    }
+
+    return NULL;
+}
+
+void NvOdmOsMutexLock(NvOdmOsMutexHandle mutex)
+{
+    NvOsMutexLock((NvOsMutexHandle)mutex);
+}
+
+void NvOdmOsMutexUnlock(NvOdmOsMutexHandle mutex)
+{
+    NvOsMutexUnlock((NvOsMutexHandle)mutex);
+}
+
+void NvOdmOsMutexDestroy(NvOdmOsMutexHandle mutex)
+{
+    NvOsMutexDestroy((NvOsMutexHandle)mutex);
+}
+
+NvOdmOsSemaphoreHandle NvOdmOsSemaphoreCreate(NvU32 value)
+{
+    NvError err;
+    NvOsSemaphoreHandle s;
+
+    err = NvOsSemaphoreCreate(&s, value);
+    if( err == NvSuccess )
+    {
+        return (NvOdmOsSemaphoreHandle)s;
+    }
+
+    return NULL;
+}
+
+void NvOdmOsSemaphoreWait(NvOdmOsSemaphoreHandle semaphore)
+{
+    NvOsSemaphoreWait((NvOsSemaphoreHandle)semaphore);
+}
+
+NvBool NvOdmOsSemaphoreWaitTimeout(NvOdmOsSemaphoreHandle semaphore,
+    NvU32 msec)
+{
+    NvError err;
+
+    err = NvOsSemaphoreWaitTimeout((NvOsSemaphoreHandle)semaphore, msec);
+    if (err == NvError_Timeout)
+    {
+        return NV_FALSE;
+    }
+
+    return NV_TRUE;
+}
+
+void NvOdmOsSemaphoreSignal(NvOdmOsSemaphoreHandle semaphore)
+{
+    NvOsSemaphoreSignal( (NvOsSemaphoreHandle)semaphore );
+}
+
+void NvOdmOsSemaphoreDestroy(NvOdmOsSemaphoreHandle semaphore)
+{
+    NvOsSemaphoreDestroy((NvOsSemaphoreHandle)semaphore);
+}
+
+NvOdmOsThreadHandle NvOdmOsThreadCreate(NvOdmOsThreadFunction function,
+    void *args)
+{
+    NvError err;
+    NvOsThreadHandle t;
+
+    err = NvOsThreadCreate((NvOsThreadFunction)function, args, &t);
+    if (err == NvSuccess)
+    {
+        return (NvOdmOsThreadHandle)t;
+    }
+
+    return NULL;
+}
+
+void NvOdmOsThreadJoin(NvOdmOsThreadHandle thread)
+{
+    NvOsThreadJoin((NvOsThreadHandle)thread);
+}
+
+void NvOdmOsWaitUS(NvU32 usec)
+{
+    NvOsWaitUS(usec);
+}
+
+void NvOdmOsSleepMS(NvU32 msec)
+{
+    NvOsSleepMS(msec);
+}
+
+NvU32 NvOdmOsGetTimeMS(void)
+{
+    return NvOsGetTimeMS();
+}
+
+// Assert that the types defined in nvodm_services.h map correctly to their
+// corresponding nvos types.
+NV_CT_ASSERT(NVOS_OPEN_READ == NVODMOS_OPEN_READ);
+NV_CT_ASSERT(NVOS_OPEN_WRITE == NVODMOS_OPEN_WRITE);
+NV_CT_ASSERT(NVOS_OPEN_CREATE == NVODMOS_OPEN_CREATE);
+
+NV_CT_ASSERT(NvOsFileType_File == NvOdmOsFileType_File);
+NV_CT_ASSERT(NvOsFileType_Directory == NvOdmOsFileType_Directory);
+NV_CT_ASSERT(sizeof(NvOsStatType) == sizeof(NvOdmOsStatType));
+
+NvBool NvOdmOsFopen(const char *path, NvU32 flags, NvOdmOsFileHandle *file)
+{
+    return (NvOsFopen(path, flags, (NvOsFileHandle*)file) == NvSuccess);
+}
+
+void NvOdmOsFclose(NvOdmOsFileHandle stream)
+{
+    NvOsFclose((NvOsFileHandle)stream);
+}
+
+NvBool NvOdmOsFwrite(NvOdmOsFileHandle stream, const void *ptr, size_t size)
+{
+    return (NvOsFwrite((NvOsFileHandle)stream, ptr, size) == NvSuccess);
+}
+
+NvBool NvOdmOsFread(NvOdmOsFileHandle stream, void *ptr, size_t size,
+    size_t *bytes)
+{
+    return (NvOsFread((NvOsFileHandle)stream, ptr, size, bytes) == NvSuccess);
+}
+
+NvBool NvOdmOsStat(const char *filename, NvOdmOsStatType *stat)
+{
+    return (NvOsStat(filename, (NvOsStatType*)stat) == NvSuccess);
+}
+
+NvBool NvOdmOsGetOsInformation(NvOdmOsOsInfo *pOsInfo)
+{
+    NvOsOsInfo info;
+    NvError e;
+
+    if (!pOsInfo)
+    {
+        return NV_FALSE;
+    }
+
+    e = NvOsGetOsInformation(&info);
+    if (e != NvSuccess)
+    {
+        return NV_FALSE;
+    }
+
+    pOsInfo->OsType = NvOdmOsOs_Linux;
+    pOsInfo->Sku = NvOdmOsSku_Unknown;
+    pOsInfo->MajorVersion = info.MajorVersion;
+    pOsInfo->MinorVersion = info.MinorVersion;
+    pOsInfo->SubVersion = info.SubVersion;
+    pOsInfo->Caps = info.Caps;
+
+    return NV_TRUE;
+}
+
diff --git a/arch/arm/mach-tegra/nvrm/Makefile b/arch/arm/mach-tegra/nvrm/Makefile
new file mode 100644
index 000000000000..ee4c2ad6a43f
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/Makefile
@@ -0,0 +1,17 @@
+ccflags-y += -DNV_IS_AVP=0
+ccflags-y += -DNV_OAL=0
+ccflags-y += -DNV_USE_FUSE_CLOCK_ENABLE=0
+ifeq ($(CONFIG_MACH_TEGRA_GENERIC_DEBUG),y)
+ccflags-y += -DNV_DEBUG=1
+else
+ccflags-y += -DNV_DEBUG=0
+endif
+
+obj-y += core/ap15/
+obj-y += core/ap20/
+obj-y += core/common/
+
+obj-y += io/common/
+obj-y += io/ap15/
+obj-y += io/ap20/
+
diff --git a/arch/arm/mach-tegra/nvrm/core/ap15/Makefile b/arch/arm/mach-tegra/nvrm/core/ap15/Makefile
new file mode 100644
index 000000000000..2c87c36b3245
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/core/ap15/Makefile
@@ -0,0 +1,35 @@
+ccflags-y += -DNV_IS_AVP=0
+ccflags-y += -DNV_OAL=0
+ccflags-y += -DNV_USE_FUSE_CLOCK_ENABLE=0
+ifeq ($(CONFIG_MACH_TEGRA_GENERIC_DEBUG),y)
+ccflags-y += -DNV_DEBUG=1
+else
+ccflags-y += -DNV_DEBUG=0
+endif
+
+ccflags-y += -Iarch/arm/mach-tegra/nvrm/core/common
+ccflags-y += -Iarch/arm/mach-tegra/nvrm/core
+
+obj-y += ap15rm_interrupt_generic.o
+obj-y += ap15rm_hwmap.o
+obj-y += ap15rm_clocks.o
+obj-y += ap15rm_clock_config.o
+obj-y += ap15rm_clocks_info.o
+obj-y += nvrm_clocks.o
+obj-y += ap15rm_pinmux.o
+obj-y += ap15rm_pinmux_tables.o
+obj-y += ap16rm_pinmux_tables.o
+obj-y += ap15rm_power.o
+obj-y += ap15rm_power_dfs.o
+obj-y += ap15rm_power_oalintf.o
+obj-y += ap15rm_clock_misc.o
+obj-y += ap15rm_memctrl.o
+obj-y += ap15rm_fuse.o
+obj-y += nvrm_diag.o
+obj-y += ap15rm_reloctable.o
+obj-y += ap16rm_reloctable.o
+obj-y += ap15rm_init.o
+obj-y += ap15rm_init_common.o
+obj-y += ap15rm_interrupt.o
+obj-y += ap15rm_xpc.o
+obj-y += ap15rm_xpc_hw_private.o
diff --git a/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_clock_config.c b/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_clock_config.c
new file mode 100644
index 000000000000..f13ef4797306
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_clock_config.c
@@ -0,0 +1,2723 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include "nvcommon.h"
+#include "nvassert.h"
+#include "nvrm_clocks.h"
+#include "nvrm_hwintf.h"
+#include "nvrm_module.h"
+#include "nvrm_drf.h"
+#include "ap15/aremc.h"
+#include "ap15/arclk_rst.h"
+#include "ap15/arapb_misc.h"
+#include "ap15rm_clocks.h"
+#include "ap15rm_private.h"
+#include "nvrm_pmu_private.h"
+#include "nvodm_query_discovery.h"
+#include "nvodm_query_memc.h"
+#include "ap20/ap20rm_clocks.h"
+
+// TODO: CAR and EMC access macros for time critical access
+
+/*****************************************************************************/
+
+static const NvU32 s_Ap15OscFreqKHz[] = { 13000, 19200, 12000, 26000 };
+
+static void
+Ap15PllPConfigure(NvRmDeviceHandle hRmDevice);
+
+static void
+Ap15MioReconfigure(NvRmDeviceHandle hRmDevice, NvRmFreqKHz MioKHz);
+
+static void
+Ap15AudioSyncInit(NvRmDeviceHandle hRmDevice, NvRmFreqKHz AudioSyncKHz);
+
+static NvError
+NvRmPrivOscDoublerConfigure(NvRmDeviceHandle hRmDevice, NvRmFreqKHz OscKHz)
+{
+    switch (hRmDevice->ChipId.Id)
+    {
+        case 0x15:
+        case 0x16:
+            return NvRmPrivAp15OscDoublerConfigure(hRmDevice, OscKHz);
+        case 0x20:
+            return NvRmPrivAp20OscDoublerConfigure(hRmDevice, OscKHz);
+        default:
+            NV_ASSERT(!"Unsupported chip ID");
+            return NvError_NotSupported;
+    }
+}
+
+void
+NvRmPrivClockSourceFreqInit(
+    NvRmDeviceHandle hRmDevice,
+    NvU32* pClockSourceFreq)
+{
+    NvU32 reg;
+    const NvRmCoreClockInfo* pCore = NULL;
+
+    NV_ASSERT(hRmDevice);
+    NV_ASSERT(pClockSourceFreq);
+
+    /*
+     * Fixed clock sources: 32kHz, main oscillator and doubler
+     * (OSC control should be already configured by the boot code)
+     */
+    pClockSourceFreq[NvRmClockSource_ClkS] = 32;
+
+    reg = NV_REGR(hRmDevice, NvRmPrivModuleID_ClockAndReset, 0,
+                  CLK_RST_CONTROLLER_OSC_CTRL_0);
+    pClockSourceFreq[NvRmClockSource_ClkM] =
+        s_Ap15OscFreqKHz[NV_DRF_VAL(CLK_RST_CONTROLLER, OSC_CTRL, OSC_FREQ, reg)];
+
+    if (NvSuccess == NvRmPrivOscDoublerConfigure(
+        hRmDevice, pClockSourceFreq[NvRmClockSource_ClkM]))
+    {
+        pClockSourceFreq[NvRmClockSource_ClkD] =
+            pClockSourceFreq[NvRmClockSource_ClkM] << 1;
+    }
+    else
+        pClockSourceFreq[NvRmClockSource_ClkD] = 0;
+
+    /*
+     * PLLs and secondary PLL dividers
+     */
+    #define INIT_PLL_FREQ(PllId) \
+    do\
+    {\
+        pClockSourceFreq[NvRmClockSource_##PllId] = NvRmPrivAp15PllFreqGet( \
+         hRmDevice, NvRmPrivGetClockSourceHandle(NvRmClockSource_##PllId)->pInfo.pPll); \
+    } while(0)
+
+    // PLLX (check if present, keep boot settings
+    // and just init frequency table)
+    if (NvRmPrivGetClockSourceHandle(NvRmClockSource_PllX0))
+    {
+        INIT_PLL_FREQ(PllX0);
+    }
+    // PLLC with output divider (if enabled keep boot settings and just init
+    // frequency table, if disbled or bypassed - configure)
+    INIT_PLL_FREQ(PllC0);
+    if (pClockSourceFreq[NvRmClockSource_PllC0] <=
+        pClockSourceFreq[NvRmClockSource_ClkM])
+    {
+        NvRmFreqKHz f = NVRM_PLLC_DEFAULT_FREQ_KHZ;
+        NvRmPrivAp15PllConfigureSimple(hRmDevice, NvRmClockSource_PllC0, f, &f);
+    }
+    pClockSourceFreq[NvRmClockSource_PllC1] = NvRmPrivDividerFreqGet(hRmDevice,
+        NvRmPrivGetClockSourceHandle(NvRmClockSource_PllC1)->pInfo.pDivider);
+
+    // PLLM with output divider (keep boot settings
+    // and just init frequency)
+    INIT_PLL_FREQ(PllM0);
+    pClockSourceFreq[NvRmClockSource_PllM1] = NvRmPrivDividerFreqGet(hRmDevice,
+        NvRmPrivGetClockSourceHandle(NvRmClockSource_PllM1)->pInfo.pDivider);
+#if !NV_OAL
+    // PLLD and PLLU with no output dividers (keep boot settings
+    // and just init frequency table)
+    INIT_PLL_FREQ(PllD0);
+    INIT_PLL_FREQ(PllU0);
+#endif
+
+    // PLLP and output dividers: set PLLP fixed frequency and enable dividers
+    // with fixed settings in override mode, so they can be changed later, as
+    // necessary. Switch system clock to oscillator during PLLP reconfiguration
+    INIT_PLL_FREQ(PllP0);
+    if (pClockSourceFreq[NvRmClockSource_PllP0] != NVRM_PLLP_FIXED_FREQ_KHZ)
+    {
+        pCore = NvRmPrivGetClockSourceHandle(
+            NvRmClockSource_SystemBus)->pInfo.pCore;
+        reg = NV_REGR(hRmDevice, NvRmPrivModuleID_ClockAndReset, 0,
+                      pCore->SelectorOffset);
+        NvRmPrivCoreClockSet(hRmDevice, pCore, NvRmClockSource_ClkM, 0, 0);
+        Ap15PllPConfigure(hRmDevice);
+        NV_REGW(hRmDevice, NvRmPrivModuleID_ClockAndReset, 0,
+                pCore->SelectorOffset, reg);
+    }
+    NV_ASSERT(pClockSourceFreq[NvRmClockSource_PllP0] == NVRM_PLLP_FIXED_FREQ_KHZ);
+    NvRmPrivDividerSet(
+        hRmDevice,
+        NvRmPrivGetClockSourceHandle(NvRmClockSource_PllP1)->pInfo.pDivider,
+        NVRM_FIXED_PLLP1_SETTING);
+    NvRmPrivDividerSet(
+        hRmDevice,
+        NvRmPrivGetClockSourceHandle(NvRmClockSource_PllP2)->pInfo.pDivider,
+        NVRM_FIXED_PLLP2_SETTING);
+    NvRmPrivDividerSet(
+        hRmDevice,
+        NvRmPrivGetClockSourceHandle(NvRmClockSource_PllP3)->pInfo.pDivider,
+        NVRM_FIXED_PLLP3_SETTING);
+    NvRmPrivDividerSet(
+        hRmDevice,
+        NvRmPrivGetClockSourceHandle(NvRmClockSource_PllP4)->pInfo.pDivider,
+        NVRM_FIXED_PLLP4_SETTING);
+
+    // PLLA and output divider must be init after PLLP1, used as a
+    // reference (keep boot settings and just init frequency table)
+    INIT_PLL_FREQ(PllA1);
+    pClockSourceFreq[NvRmClockSource_PllA0] = NvRmPrivDividerFreqGet(hRmDevice,
+        NvRmPrivGetClockSourceHandle(NvRmClockSource_PllA0)->pInfo.pDivider);
+
+    #undef INIT_PLL_FREQ
+
+    /*
+     * Core and bus clock sources
+     * - Leave CPU bus as set by boot-loader
+     * - Leave System bus as set by boot-loader, make sure all bus dividers are 1:1
+     */
+    pCore = NvRmPrivGetClockSourceHandle(NvRmClockSource_CpuBus)->pInfo.pCore;
+    pClockSourceFreq[NvRmClockSource_CpuBus] =
+        NvRmPrivCoreClockFreqGet(hRmDevice, pCore);
+    if (NvRmPrivGetClockSourceHandle(NvRmClockSource_CpuBridge))
+    {
+        pClockSourceFreq[NvRmClockSource_CpuBridge] = NvRmPrivDividerFreqGet(hRmDevice,
+            NvRmPrivGetClockSourceHandle(NvRmClockSource_CpuBridge)->pInfo.pDivider);
+    }
+    pCore = NvRmPrivGetClockSourceHandle(NvRmClockSource_SystemBus)->pInfo.pCore;
+    pClockSourceFreq[NvRmClockSource_SystemBus] =
+        NvRmPrivCoreClockFreqGet(hRmDevice, pCore);
+    NvRmPrivBusClockInit(
+        hRmDevice, pClockSourceFreq[NvRmClockSource_SystemBus]);
+
+    /*
+     * Initialize AudioSync clocks (PLLA will be re-configured if necessary)
+     */
+    Ap15AudioSyncInit(hRmDevice, NVRM_AUDIO_SYNC_KHZ);
+}
+
+void
+NvRmPrivBusClockInit(NvRmDeviceHandle hRmDevice, NvRmFreqKHz SystemFreq)
+{
+    /*
+     * Set all bus clock frequencies equal to the system clock frequency,
+     * and clear AVP clock skipper i.e., set all bus clock dividers 1:1.
+     * If APB clock is limited below system clock for a particular SoC,
+     * set the APB divider to satisfy this limitation.
+     */
+    NvRmFreqKHz AhbFreq, ApbFreq;
+    NvRmFreqKHz ApbMaxFreq = SystemFreq;
+    if (hRmDevice->ChipId.Id == 0x20)
+    {
+        ApbMaxFreq = NVRM_AP20_APB_MAX_KHZ; // AP20 limitation
+    }
+    AhbFreq = SystemFreq;
+    ApbFreq = NV_MIN(SystemFreq, ApbMaxFreq);
+
+    NvRmPrivBusClockFreqSet(
+        hRmDevice, SystemFreq, &SystemFreq, &AhbFreq, &ApbFreq, ApbMaxFreq);
+    NV_REGW(hRmDevice, NvRmPrivModuleID_ClockAndReset, 0,
+            CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0, 0x0);
+}
+
+/*****************************************************************************/
+/*****************************************************************************/
+
+static const NvRmFreqKHz s_PllLpCpconSelectionTable[] =
+{
+    NVRM_PLL_LP_CPCON_SELECT_STEPS_KHZ
+};
+static const NvU32 s_PllLpCpconSelectionTableSize =
+NV_ARRAY_SIZE(s_PllLpCpconSelectionTable);
+
+static const NvU32 s_PllMipiCpconSelectionTable[] =
+{
+    NVRM_PLL_MIPI_CPCON_SELECT_STEPS_N_DIVIDER
+};
+static const NvU32 s_PllMipiCpconSelectionTableSize =
+NV_ARRAY_SIZE(s_PllMipiCpconSelectionTable);
+
+static void
+PllLpGetTypicalControls(
+    NvRmFreqKHz InputKHz,
+    NvU32 M,
+    NvU32 N,
+    NvU32* pCpcon)
+{
+    NvU32 i;
+    if (N >= NVRM_PLL_LP_MIN_N_FOR_CPCON_SELECTION)
+    {
+        // CPCON depends on comparison frequency
+        for (i = 0; i < s_PllLpCpconSelectionTableSize; i++)
+        {
+            if (InputKHz >= s_PllLpCpconSelectionTable[i] * M)
+                break;
+        }
+        *pCpcon = i + 1;
+    }
+    else    // CPCON is 1, regardless of frequency
+    {
+        *pCpcon = 1;
+    }
+}
+
+static void
+PllMipiGetTypicalControls(
+    NvU32 N,
+    NvU32* pCpcon,
+    NvU32* pLfCon)
+{
+    NvU32 i;
+
+    // CPCON depends on feedback divider
+    for (i = 0; i < s_PllMipiCpconSelectionTableSize; i++)
+    {
+        if (N <= s_PllMipiCpconSelectionTable[i])
+            break;
+    }
+    *pCpcon = i + 1;
+    *pLfCon = (N >= NVRM_PLL_MIPI_LFCON_SELECT_N_DIVIDER) ? 1 : 0;
+}
+
+void
+NvRmPrivAp15PllSet(
+    NvRmDeviceHandle hRmDevice,
+    const NvRmPllClockInfo* pCinfo,
+    NvU32 M,
+    NvU32 N,
+    NvU32 P,
+    NvU32 StableDelayUs,
+    NvU32 cpcon,
+    NvU32 lfcon,
+    NvBool TypicalControls,
+    NvU32 flags)
+{
+    NvU32 base, misc;
+    NvU32 old_base, old_misc;
+    NvU32 delay = 0;
+    NvU32 override = 0;
+
+    NV_ASSERT(hRmDevice);
+    NV_ASSERT(pCinfo);
+    NV_ASSERT(pCinfo->PllBaseOffset);
+    NV_ASSERT(pCinfo->PllMiscOffset);
+
+    /*
+     * PLL control fields used below have the same layout for all PLLs with
+     * the following exceptions:
+     *
+     * a) PLLP base register OVERRIDE field has to be set in order to enable
+     *  PLLP re-configuration in diagnostic mode. For other PLLs this field is
+     *  "Don't care".
+     * b) PLLU HS P divider field is one bit, inverse logic field. Other control
+     *  bits, that are mapped to P divider in common layout should be set to 0.
+     *
+     * PLLP h/w field definitions will be used in DRF macros to construct base
+     * values for all PLLs, with special care of a) and b). All base fields not
+     * explicitly used below are set to 0 for all PLLs.
+     *
+     * c) PLLD/PLLU miscellaneous register has a unique fields determined based
+     *  on the input flags. For other PLLs these fields have different meaning,
+     *  and will be preserved. 
+     *
+     *  PLLP h/w field definitions will be used in DRF macros to construct
+     *  miscellaneous values with common layout. For unique fields PLLD h/w
+     *  definitions will be used. All miscellaneous fields not explicitly used
+     *  below are preserved for all PLLs.
+     */
+    base = NV_REGR(hRmDevice, NvRmPrivModuleID_ClockAndReset, 0, pCinfo->PllBaseOffset);
+    old_base = base;
+
+    // Disable PLL if either input or feedback divider setting is zero
+    if ((M == 0) || (N == 0))
+    {
+        base = NV_FLD_SET_DRF_DEF(CLK_RST_CONTROLLER, PLLP_BASE, PLLP_BYPASS, DISABLE, base);
+        base = NV_FLD_SET_DRF_DEF(CLK_RST_CONTROLLER, PLLP_BASE, PLLP_ENABLE, DISABLE, base);
+        NV_REGW(hRmDevice, NvRmPrivModuleID_ClockAndReset, 0, pCinfo->PllBaseOffset, base);
+        NvRmPrivPllFreqUpdate(hRmDevice, pCinfo);
+        return;
+    }
+
+    // Determine type-specific controls, construct new misc settings
+    misc = NV_REGR(hRmDevice, NvRmPrivModuleID_ClockAndReset, 0, pCinfo->PllMiscOffset);
+    old_misc = misc;
+    if (pCinfo->PllType == NvRmPllType_MIPI)
+    {
+        if (flags & NvRmPllConfigFlags_SlowMode)
+        {
+            misc = NV_FLD_SET_DRF_NUM(  // "1" = slow (/8) MIPI clock output
+                    CLK_RST_CONTROLLER, PLLD_MISC, PLLD_FO_MODE, 1, misc);
+        }
+        else if (flags & NvRmPllConfigFlags_FastMode)
+        {
+            misc = NV_FLD_SET_DRF_NUM(  // "0" = fast MIPI clock output
+                    CLK_RST_CONTROLLER, PLLD_MISC, PLLD_FO_MODE, 0, misc);
+        }
+        if (flags & NvRmPllConfigFlags_DiffClkEnable)
+        {
+            misc = NV_FLD_SET_DRF_NUM(  // Enable differential clocks
+                    CLK_RST_CONTROLLER, PLLD_MISC, PLLD_CLKENABLE, 1, misc);
+        }
+        else if (flags & NvRmPllConfigFlags_DiffClkDisable)
+        {
+            misc = NV_FLD_SET_DRF_NUM(  // Disable differential clocks
+                    CLK_RST_CONTROLLER, PLLD_MISC, PLLD_CLKENABLE, 0, misc);
+        }
+        if (TypicalControls)
+        {
+            PllMipiGetTypicalControls(N, &cpcon, &lfcon);
+        }
+        delay = NVRM_PLL_MIPI_STABLE_DELAY_US;
+    }
+    else if (pCinfo->PllType == NvRmPllType_LP)
+    {
+        if (flags & NvRmPllConfigFlags_DccEnable)
+        {
+            misc = NV_FLD_SET_DRF_NUM(  // "1" = enable DCC
+                    CLK_RST_CONTROLLER, PLLP_MISC, PLLP_DCCON, 1, misc);
+        }
+        else if (flags & NvRmPllConfigFlags_DccDisable)
+        {
+            misc = NV_FLD_SET_DRF_NUM(  // "0" = disable DCC
+                    CLK_RST_CONTROLLER, PLLP_MISC, PLLP_DCCON, 0, misc);
+        }
+        if (TypicalControls)
+        {
+            NvRmFreqKHz InputKHz = NvRmPrivGetClockSourceFreq(pCinfo->InputId);
+            PllLpGetTypicalControls(InputKHz, M, N, &cpcon);
+        }
+        lfcon = 0; // always for LP PLL
+        delay = NVRM_PLL_LP_STABLE_DELAY_US;
+    }
+    else if (pCinfo->PllType == NvRmPllType_UHS)
+    {
+        if (TypicalControls)    // Same as MIPI typical controls
+        {
+            PllMipiGetTypicalControls(N, &cpcon, &lfcon);
+        }
+        delay = NVRM_PLL_MIPI_STABLE_DELAY_US;
+        P = (P == 0) ? 1 : 0;   // P-divider is 1 bit, inverse logic
+    }
+    else
+    {
+        NV_ASSERT(!"Invalid PLL type");
+    }
+    misc = NV_FLD_SET_DRF_NUM(CLK_RST_CONTROLLER, PLLP_MISC, PLLP_CPCON, cpcon, misc);
+    misc = NV_FLD_SET_DRF_NUM(CLK_RST_CONTROLLER, PLLP_MISC, PLLP_LFCON, lfcon, misc);
+
+    // Construct new base setting
+    // Override is PLLP specific, and it is just ignored by other PLLs;
+    override = ((flags & NvRmPllConfigFlags_Override) != 0) ?
+                CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BASE_OVRRIDE_ENABLE :
+                CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BASE_OVRRIDE_DISABLE;
+    {   // Compiler failed to generate correct code for the base fields
+        // concatenation without the split below
+        volatile NvU32 prebase =
+            NV_DRF_DEF(CLK_RST_CONTROLLER, PLLP_BASE, PLLP_BYPASS, ENABLE) |
+            NV_DRF_DEF(CLK_RST_CONTROLLER, PLLP_BASE, PLLP_ENABLE, ENABLE) |
+            NV_DRF_DEF(CLK_RST_CONTROLLER, PLLP_BASE, PLLP_REF_DIS, REF_ENABLE);
+        base = prebase |
+            NV_DRF_NUM(CLK_RST_CONTROLLER, PLLP_BASE, PLLP_BASE_OVRRIDE, override) |
+            NV_DRF_NUM(CLK_RST_CONTROLLER, PLLP_BASE, PLLP_DIVP, P) |
+            NV_DRF_NUM(CLK_RST_CONTROLLER, PLLP_BASE, PLLP_DIVN, N) |
+            NV_DRF_NUM(CLK_RST_CONTROLLER, PLLP_BASE, PLLP_DIVM, M);
+    }
+
+    // If PLL is not bypassed, and new configurations is the same as the old
+    // one - exit without overwriting h/w. Otherwise, bypass PLL before
+    // changing configuration.
+    if (NV_DRF_VAL(CLK_RST_CONTROLLER, PLLP_BASE, PLLP_BYPASS, old_base) ==
+        CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BYPASS_DISABLE)
+    {
+        old_base = NV_FLD_SET_DRF_DEF(
+            CLK_RST_CONTROLLER, PLLP_BASE, PLLP_BYPASS, ENABLE, old_base);
+        if ((base == old_base) && (misc == old_misc))
+        {
+            NvRmPrivPllFreqUpdate(hRmDevice, pCinfo);
+            return;
+        }
+        NV_REGW(hRmDevice, NvRmPrivModuleID_ClockAndReset, 0,
+                pCinfo->PllBaseOffset, old_base);
+    }
+
+    // Configure and enable PLL, keep it bypassed
+    NV_REGW(hRmDevice, NvRmPrivModuleID_ClockAndReset, 0, pCinfo->PllMiscOffset, misc);
+    NV_REGW(hRmDevice, NvRmPrivModuleID_ClockAndReset, 0, pCinfo->PllBaseOffset, base);
+
+    // Wait for PLL to stabilize and switch to PLL output
+    NV_ASSERT(StableDelayUs);
+    if (StableDelayUs > delay)
+        StableDelayUs = delay;
+    NvOsWaitUS(StableDelayUs);
+
+    base = NV_FLD_SET_DRF_DEF(CLK_RST_CONTROLLER, PLLP_BASE, PLLP_BYPASS, DISABLE, base);
+    NV_REGW(hRmDevice, NvRmPrivModuleID_ClockAndReset, 0, pCinfo->PllBaseOffset, base);
+    NvRmPrivPllFreqUpdate(hRmDevice, pCinfo);
+}
+
+NvRmFreqKHz
+NvRmPrivAp15PllFreqGet(
+    NvRmDeviceHandle hRmDevice,
+    const NvRmPllClockInfo* pCinfo)
+{
+    NvU32 M, N, P;
+    NvU32 base, misc;
+    NvRmFreqKHz PllKHz;
+
+    NV_ASSERT(hRmDevice);
+    NV_ASSERT(pCinfo);
+    NV_ASSERT(pCinfo->PllBaseOffset);
+    NV_ASSERT(pCinfo->PllMiscOffset);
+
+    /*
+     * PLL control fields used below have the same layout for all PLLs with
+     * the following exceptions:
+     *
+     * a) PLLP base register OVERRIDE field ("Don't care" for other PLLs).
+     *  Respectively, PLLP h/w field definitions will be used in DRF macros
+     *  to construct base values for all PLLs.
+     *
+     * b) PLLD/PLLU miscellaneous register fast/slow mode control (does not
+     *  affect output frequency for other PLLs). Respectively, PLLD h/w field
+     *  definitions will be used in DRF macros to construct miscellaneous values.
+     */
+    base = NV_REGR(
+        hRmDevice, NvRmPrivModuleID_ClockAndReset, 0, pCinfo->PllBaseOffset);
+    PllKHz = NvRmPrivGetClockSourceFreq(pCinfo->InputId);
+    NV_ASSERT(PllKHz);
+    NV_ASSERT(NV_DRF_VAL(CLK_RST_CONTROLLER, PLLP_BASE, PLLP_REF_DIS, base) ==
+              CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_REF_DIS_REF_ENABLE);
+
+    if (NV_DRF_VAL(CLK_RST_CONTROLLER, PLLP_BASE, PLLP_BYPASS, base) ==
+        CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BYPASS_DISABLE)
+    {
+        // Special cases: PLL is disabled, or in fixed mode (PLLP only)
+        if (NV_DRF_VAL(CLK_RST_CONTROLLER, PLLP_BASE, PLLP_ENABLE, base) ==
+            CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_ENABLE_DISABLE)
+            return 0;
+        if ((pCinfo->SourceId == NvRmClockSource_PllP0) &&
+            (NV_DRF_VAL(CLK_RST_CONTROLLER, PLLP_BASE, PLLP_BASE_OVRRIDE, base) ==
+             CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BASE_OVRRIDE_DISABLE))
+            return NV_BOOT_PLLP_FIXED_FREQ_KHZ;
+
+        // PLL formula - Output F = (Reference F * N) / (M * 2^P)
+        M = NV_DRF_VAL(CLK_RST_CONTROLLER, PLLP_BASE, PLLP_DIVM, base);
+        N = NV_DRF_VAL(CLK_RST_CONTROLLER, PLLP_BASE, PLLP_DIVN, base);
+        P = NV_DRF_VAL(CLK_RST_CONTROLLER, PLLP_BASE, PLLP_DIVP, base);
+        NV_ASSERT((M != 0) && (N != 0));
+
+        if (pCinfo->PllType == NvRmPllType_UHS)
+        {
+            // Adjust P divider field size and inverse logic for USB HS PLL
+            P = (P & 0x1) ? 0 : 1;
+        }
+        PllKHz = ((PllKHz * N) / M) >> P;
+
+        // Check slow/fast mode selection for MIPI PLLs
+        if (pCinfo->PllType == NvRmPllType_MIPI)
+        {
+            misc = NV_REGR(hRmDevice, NvRmPrivModuleID_ClockAndReset, 0,
+                           pCinfo->PllMiscOffset);
+            if (NV_DRF_VAL(CLK_RST_CONTROLLER, PLLD_MISC, PLLD_FO_MODE, misc) == 1)
+            {
+                PllKHz = PllKHz >> 3;   // In slow mode output is divided by 8
+            }
+        }
+    }
+    if (pCinfo->SourceId == NvRmClockSource_PllD0)
+    {
+        PllKHz = PllKHz >> 1;   // PLLD output always divided by 2
+    }
+    return PllKHz;
+}
+
+static void
+Ap15PllControl(
+    NvRmDeviceHandle hRmDevice,
+    NvRmClockSource PllId,
+    NvBool Enable)
+{
+    NvU32 base;
+    NvU32 delay = 0;
+    const NvRmPllClockInfo* pCinfo =
+        NvRmPrivGetClockSourceHandle(PllId)->pInfo.pPll;
+
+    NV_ASSERT(hRmDevice);
+    NV_ASSERT(pCinfo->PllBaseOffset);
+
+    /*
+     * PLL control fields used below have the same layout for all PLLs.
+     * PLLP h/w field definitions will be used in DRF macros to construct base
+     * values for all PLLs.
+     */
+    base = NV_REGR(hRmDevice, NvRmPrivModuleID_ClockAndReset, 0, pCinfo->PllBaseOffset);
+
+    if (Enable)
+    {
+        // No need to enable already enabled PLL - do nothing
+        if (NV_DRF_VAL(CLK_RST_CONTROLLER, PLLP_BASE, PLLP_ENABLE, base) ==
+            CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_ENABLE_ENABLE)
+            return;
+
+        // Get ready stabilization delay
+        if ((pCinfo->PllType == NvRmPllType_MIPI) ||
+            (pCinfo->PllType == NvRmPllType_UHS))
+            delay = NVRM_PLL_MIPI_STABLE_DELAY_US;
+        else if (pCinfo->PllType == NvRmPllType_LP)
+            delay = NVRM_PLL_LP_STABLE_DELAY_US;
+        else
+            NV_ASSERT(!"Invalid PLL type");
+
+        // Bypass PLL => Enable PLL => wait for PLL to stabilize
+        // => switch to PLL output. All other settings preserved.
+        base = NV_FLD_SET_DRF_DEF(CLK_RST_CONTROLLER, PLLP_BASE, PLLP_BYPASS, ENABLE, base);
+        NV_REGW(hRmDevice, NvRmPrivModuleID_ClockAndReset, 0, pCinfo->PllBaseOffset, base);
+        base = NV_FLD_SET_DRF_DEF(CLK_RST_CONTROLLER, PLLP_BASE, PLLP_ENABLE, ENABLE, base);
+        NV_REGW(hRmDevice, NvRmPrivModuleID_ClockAndReset, 0, pCinfo->PllBaseOffset, base);
+
+        NvOsWaitUS(delay);
+
+        base = NV_FLD_SET_DRF_DEF(CLK_RST_CONTROLLER, PLLP_BASE, PLLP_BYPASS, DISABLE, base);
+        NV_REGW(hRmDevice, NvRmPrivModuleID_ClockAndReset, 0, pCinfo->PllBaseOffset, base);
+    }
+    else
+    {
+        // Disable PLL, no bypass. All other settings preserved.
+        base = NV_FLD_SET_DRF_DEF(CLK_RST_CONTROLLER, PLLP_BASE, PLLP_BYPASS, DISABLE, base);
+        base = NV_FLD_SET_DRF_DEF(CLK_RST_CONTROLLER, PLLP_BASE, PLLP_ENABLE, DISABLE, base);
+        NV_REGW(hRmDevice, NvRmPrivModuleID_ClockAndReset, 0, pCinfo->PllBaseOffset, base);
+    }
+    NvRmPrivPllFreqUpdate(hRmDevice, pCinfo);
+}
+
+void
+NvRmPrivAp15PllConfigureSimple(
+    NvRmDeviceHandle hRmDevice,
+    NvRmClockSource PllId,
+    NvRmFreqKHz MaxOutKHz,
+    NvRmFreqKHz* pPllOutKHz)
+{
+#define NVRM_PLL_FCMP_1 (1000)
+#define NVRM_PLL_VCO_RANGE_1 (1000000)
+#define NVRM_PLL_FCMP_2 (2000)
+#define NVRM_PLL_VCO_RANGE_2 (2000000)
+
+    /*
+     * Simple PLL configuration (assuming that target output frequency is
+     * always in VCO range, and does not exceed 2GHz).
+     * - output divider is set 1:1
+     * - input divider is set to get comparison frequency equal or slightly
+     *   above 1MHz if VCO is below 1GHz . Otherwise, input divider is set
+     *   to get comparison frequency equal or slightly below 2MHz.
+     * - feedback divider is calculated based on target output frequency
+     * With simple configuration the absolute output frequency error does not
+     * exceed half of comparison frequency. It has been verified that simple
+     * configuration provides necessary accuracy for all display pixel clocks
+     * use cases.
+     */
+    NvU32 M, N, P;
+    NvRmFreqKHz RefKHz, VcoKHz;
+    const NvRmPllClockInfo* pCinfo =
+        NvRmPrivGetClockSourceHandle(PllId)->pInfo.pPll;
+    NvU32 flags = 0;
+
+    NV_ASSERT(hRmDevice);
+    VcoKHz = *pPllOutKHz;
+    P = 0;
+
+    if (pCinfo->SourceId == NvRmClockSource_PllD0)
+    {   // PLLD output is always divided by 2 (after P-divider)
+        VcoKHz = VcoKHz << 1;
+        MaxOutKHz = MaxOutKHz << 1;
+        while (VcoKHz < pCinfo->PllVcoMin)
+        {
+            VcoKHz = VcoKHz << 1;
+            MaxOutKHz = MaxOutKHz << 1;
+            P++;
+        }
+        NV_ASSERT(P <= CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVP_DEFAULT_MASK);
+        flags = NvRmPllConfigFlags_DiffClkEnable;
+    }
+    if (pCinfo->SourceId == NvRmClockSource_PllX0)
+    {
+        flags = VcoKHz < NVRM_PLLX_DCC_VCO_MIN ?
+            NvRmPllConfigFlags_DccDisable : NvRmPllConfigFlags_DccEnable;
+    }
+    NV_ASSERT((pCinfo->PllVcoMin <= VcoKHz) && (VcoKHz <= pCinfo->PllVcoMax));
+    NV_ASSERT(VcoKHz <= NVRM_PLL_VCO_RANGE_2);
+    NV_ASSERT(VcoKHz <= MaxOutKHz);
+
+    RefKHz = NvRmPrivGetClockSourceFreq(pCinfo->InputId);
+    NV_ASSERT(RefKHz);
+    if (VcoKHz <= NVRM_PLL_VCO_RANGE_1)
+        M = RefKHz / NVRM_PLL_FCMP_1;
+    else
+        M = (RefKHz + NVRM_PLL_FCMP_2 - 1) / NVRM_PLL_FCMP_2;
+    N = (RefKHz + ((VcoKHz * M) << 1) ) / (RefKHz << 1);
+    if ((RefKHz * N) > (MaxOutKHz * M))
+        N--;    // use floor if rounding violates client's max limit
+
+    NvRmPrivAp15PllSet(
+        hRmDevice, pCinfo, M, N, P, (NvU32)-1, 0, 0, NV_TRUE, flags);
+    *pPllOutKHz = NvRmPrivGetClockSourceFreq(pCinfo->SourceId);
+}
+
+
+// Fixed list of PLL HDMI configurations for different reference frequencies
+// arranged according to CLK_RST_CONTROLLER_OSC_CTRL_0_OSC_FREQ_FIELD enum
+static const NvRmPllFixedConfig s_Ap15HdmiPllConfigurations[] =
+{
+    NVRM_PLLHD_AT_13MHZ,
+    NVRM_PLLHD_AT_19MHZ,
+    NVRM_PLLHD_AT_12MHZ,
+    NVRM_PLLHD_AT_26MHZ
+};
+
+void
+NvRmPrivAp15PllConfigureHdmi(
+    NvRmDeviceHandle hRmDevice,
+    NvRmClockSource PllId,
+    NvRmFreqKHz* pPllOutKHz)
+{
+    NvU32 reg;
+    NvRmPllFixedConfig HdmiConfig = {0};
+    const NvRmPllClockInfo* pCinfo =
+        NvRmPrivGetClockSourceHandle(PllId)->pInfo.pPll;
+
+    // Only PLLD or PLLC should be configured here
+    NV_ASSERT((PllId == NvRmClockSource_PllD0) ||
+              (PllId == NvRmClockSource_PllC0));
+
+    reg = NV_REGR(hRmDevice, NvRmPrivModuleID_ClockAndReset, 0,
+                  CLK_RST_CONTROLLER_OSC_CTRL_0);
+    HdmiConfig = s_Ap15HdmiPllConfigurations[NV_DRF_VAL(
+        CLK_RST_CONTROLLER, OSC_CTRL, OSC_FREQ, reg)];
+
+    NvRmPrivAp15PllSet(hRmDevice, pCinfo, HdmiConfig.M, HdmiConfig.N,
+                       HdmiConfig.P, (NvU32)-1, 0, 0, NV_TRUE, 0);
+    *pPllOutKHz = NvRmPrivGetClockSourceFreq(pCinfo->SourceId);
+}
+
+/*****************************************************************************/
+
+// Fixed list of PLLP configurations for different reference frequencies
+// arranged according to CLK_RST_CONTROLLER_OSC_CTRL_0_OSC_FREQ_FIELD enum
+static const NvRmPllFixedConfig s_Ap15PllPConfigurations[] =
+{
+    NVRM_PLLP_AT_13MHZ,
+    NVRM_PLLP_AT_19MHZ,
+    NVRM_PLLP_AT_12MHZ,
+    NVRM_PLLP_AT_26MHZ
+};
+
+static void
+Ap15PllPConfigure(NvRmDeviceHandle hRmDevice)
+{
+    NvU32 reg;
+    NvRmFreqKHz PllKHz;
+    NvRmPllFixedConfig PllPConfig = {0};
+
+    const NvRmPllClockInfo* pCinfo =
+        NvRmPrivGetClockSourceHandle(NvRmClockSource_PllP0)->pInfo.pPll;
+    NV_ASSERT(hRmDevice);
+
+    // Configure and enable PllP at RM fixed frequency,
+    // if it is not already enabled
+    PllKHz = NvRmPrivGetClockSourceFreq(pCinfo->SourceId);
+    if (PllKHz == NVRM_PLLP_FIXED_FREQ_KHZ)
+        return;
+
+    // Get fixed PLLP configuration for current oscillator  frequency.
+    reg = NV_REGR(hRmDevice, NvRmPrivModuleID_ClockAndReset, 0,
+                  CLK_RST_CONTROLLER_OSC_CTRL_0);
+    PllPConfig = s_Ap15PllPConfigurations[NV_DRF_VAL(
+        CLK_RST_CONTROLLER, OSC_CTRL, OSC_FREQ, reg)];
+
+    // Configure and enable PLLP
+    NvRmPrivAp15PllSet(hRmDevice, pCinfo, PllPConfig.M, PllPConfig.N,
+                       PllPConfig.P, (NvU32)-1, 0, 0, NV_TRUE,
+                       NvRmPllConfigFlags_Override);
+}
+
+/*****************************************************************************/
+
+// Fixed list of PLLU configurations for different reference frequencies
+// arranged according to CLK_RST_CONTROLLER_OSC_CTRL_0_OSC_FREQ_FIELD enum
+static const NvRmPllFixedConfig s_Ap15UsbPllConfigurations[] =
+{
+    NVRM_PLLU_AT_13MHZ,
+    NVRM_PLLU_AT_19MHZ,
+    NVRM_PLLU_AT_12MHZ,
+    NVRM_PLLU_AT_26MHZ
+};
+
+static const NvRmPllFixedConfig s_Ap15UlpiPllConfigurations[] =
+{
+    NVRM_PLLU_ULPI_AT_13MHZ,
+    NVRM_PLLU_ULPI_AT_19MHZ,
+    NVRM_PLLU_ULPI_AT_12MHZ,
+    NVRM_PLLU_ULPI_AT_26MHZ
+};
+
+static const NvRmPllFixedConfig s_Ap15UhsPllConfigurations[] =
+{
+    NVRM_PLLU_HS_AT_13MHZ,
+    NVRM_PLLU_HS_AT_19MHZ,
+    NVRM_PLLU_HS_AT_12MHZ,
+    NVRM_PLLU_HS_AT_26MHZ
+};
+
+static void
+PllUmipiConfigure(NvRmDeviceHandle hRmDevice, NvRmFreqKHz TargetFreq)
+{
+    NvU32 reg;
+    NvRmPllFixedConfig UsbConfig = {0};
+    const NvRmPllClockInfo* pCinfo =
+        NvRmPrivGetClockSourceHandle(NvRmClockSource_PllU0)->pInfo.pPll;
+    NvRmFreqKHz CurrentFreq = NvRmPrivGetClockSourceFreq(pCinfo->SourceId);
+    NV_ASSERT(hRmDevice);
+
+    if (CurrentFreq == TargetFreq)
+        return;     // PLLU is already configured at target frequency - exit
+
+    // Index into fixed PLLU configuration tables based on oscillator frequency
+    reg = NV_REGR(hRmDevice, NvRmPrivModuleID_ClockAndReset, 0,
+                  CLK_RST_CONTROLLER_OSC_CTRL_0);
+    reg = NV_DRF_VAL(CLK_RST_CONTROLLER, OSC_CTRL, OSC_FREQ, reg);
+
+    if (TargetFreq == NvRmFreqUnspecified)
+    {
+        // By default set standard USB frequency, if PLLU is not configured
+        if ((CurrentFreq == s_Ap15UsbPllConfigurations[reg].OutputKHz) ||
+            (CurrentFreq == s_Ap15UlpiPllConfigurations[reg].OutputKHz))
+        {
+            return; // PLLU is already configured at supported frequency - exit
+        }
+        UsbConfig = s_Ap15UsbPllConfigurations[reg];
+    }
+    else if (TargetFreq == s_Ap15UsbPllConfigurations[reg].OutputKHz)
+    {
+        UsbConfig = s_Ap15UsbPllConfigurations[reg];
+    }
+    else if (TargetFreq == s_Ap15UlpiPllConfigurations[reg].OutputKHz)
+    {
+        UsbConfig = s_Ap15UlpiPllConfigurations[reg];
+    }
+    else
+    {
+        NV_ASSERT(!"Invalid target frequency");
+        return;
+    }
+    // Configure and enable PLLU
+    NvRmPrivAp15PllSet(hRmDevice, pCinfo, UsbConfig.M, UsbConfig.N,
+                       UsbConfig.P, (NvU32)-1, 0, 0, NV_TRUE, 0);
+}
+
+static void
+PllUhsConfigure(NvRmDeviceHandle hRmDevice, NvRmFreqKHz TargetFreq)
+{
+    NvU32 reg;
+    NvRmPllFixedConfig UsbConfig = {0};
+    const NvRmPllClockInfo* pCinfo =
+        NvRmPrivGetClockSourceHandle(NvRmClockSource_PllU0)->pInfo.pPll;
+    NvRmFreqKHz CurrentFreq = NvRmPrivGetClockSourceFreq(pCinfo->SourceId);
+    NV_ASSERT(hRmDevice);
+
+    // Index into fixed PLLU configuration tables based on oscillator frequency
+    reg = NV_REGR(hRmDevice, NvRmPrivModuleID_ClockAndReset, 0,
+                  CLK_RST_CONTROLLER_OSC_CTRL_0);
+    reg = NV_DRF_VAL(CLK_RST_CONTROLLER, OSC_CTRL, OSC_FREQ, reg);
+
+    // If PLLU is already configured - exit 
+    if (CurrentFreq == s_Ap15UhsPllConfigurations[reg].OutputKHz)
+        return;
+
+    /*
+     * Target may be unspecified, or any of the standard USB, ULPI, or UHS
+     * frequencies. In any case, main PLLU HS output is configured at UHS
+     * frequency, with ULPI and USB frequencies are generated on secondary
+     * outputs by fixed post dividers
+     */
+    if (!( (TargetFreq == NvRmFreqUnspecified) ||
+           (TargetFreq == s_Ap15UsbPllConfigurations[reg].OutputKHz) ||
+           (TargetFreq == s_Ap15UlpiPllConfigurations[reg].OutputKHz) ||
+           (TargetFreq == s_Ap15UhsPllConfigurations[reg].OutputKHz) )
+        )
+    {
+        NV_ASSERT(!"Invalid target frequency");
+        return;
+    }
+    // Configure and enable PLLU
+    UsbConfig = s_Ap15UhsPllConfigurations[reg];
+    NvRmPrivAp15PllSet(hRmDevice, pCinfo, UsbConfig.M, UsbConfig.N,
+                       UsbConfig.P, (NvU32)-1, 0, 0, NV_TRUE, 0);
+}
+
+static void
+Ap15PllUConfigure(NvRmDeviceHandle hRmDevice, NvRmFreqKHz TargetFreq)
+{
+    const NvRmPllClockInfo* pCinfo =
+        NvRmPrivGetClockSourceHandle(NvRmClockSource_PllU0)->pInfo.pPll;
+
+    if (pCinfo->PllType == NvRmPllType_MIPI)
+        PllUmipiConfigure(hRmDevice, TargetFreq);
+    else if (pCinfo->PllType == NvRmPllType_UHS)
+        PllUhsConfigure(hRmDevice, TargetFreq);
+}
+
+/*****************************************************************************/
+
+// Fixed list of PLLA configurations for supported audio clocks
+static const NvRmPllFixedConfig s_Ap15AudioPllConfigurations[] =
+{
+    NVRM_PLLA_CONFIGURATIONS
+};
+
+static void
+Ap15PllAConfigure(
+    NvRmDeviceHandle hRmDevice,
+    NvRmFreqKHz* pAudioTargetKHz)
+{
+// The reminder bits used to check divisibility
+#define REMINDER_BITS (6)
+
+    NvU32 i, rem;
+    NvRmFreqKHz OutputKHz;
+    NvU32 BestRem = (0x1 << REMINDER_BITS);
+    NvU32 BestIndex = NV_ARRAY_SIZE(s_Ap15AudioPllConfigurations) - 1;
+
+    NvRmPllFixedConfig AudioConfig = {0};
+    const NvRmPllClockInfo* pPllCinfo =
+        NvRmPrivGetClockSourceHandle(NvRmClockSource_PllA1)->pInfo.pPll;
+    const NvRmDividerClockInfo* pDividerCinfo =
+        NvRmPrivGetClockSourceHandle(NvRmClockSource_PllA0)->pInfo.pDivider;
+    NV_ASSERT(hRmDevice);
+    NV_ASSERT(*pAudioTargetKHz);
+
+    // Fixed PLLA FPGA configuration
+    if (NvRmPrivGetExecPlatform(hRmDevice) == ExecPlatform_Fpga)
+    {
+        *pAudioTargetKHz = NvRmPrivGetClockSourceFreq(pDividerCinfo->SourceId);
+        return;
+    }
+    // Find PLLA configuration with smallest output frequency that can be
+    // divided by fractional divider into the closest one to the target.
+    for (i = 0; i < NV_ARRAY_SIZE(s_Ap15AudioPllConfigurations); i++)
+    {
+        OutputKHz = s_Ap15AudioPllConfigurations[i].OutputKHz;
+        if (*pAudioTargetKHz > OutputKHz)
+            continue;
+        rem = ((OutputKHz << (REMINDER_BITS + 1)) / (*pAudioTargetKHz)) &
+              ((0x1 << REMINDER_BITS) - 1);
+        if (rem < BestRem)
+        {
+            BestRem = rem;
+            BestIndex = i;
+            if (rem == 0)
+                break;
+        }
+    }
+
+    // Configure PLLA and output divider
+    AudioConfig = s_Ap15AudioPllConfigurations[BestIndex];
+    NvRmPrivAp15PllSet(hRmDevice, pPllCinfo, AudioConfig.M, AudioConfig.N,
+                       AudioConfig.P, (NvU32)-1, 0, 0, NV_TRUE, 0);
+    NvRmPrivDividerSet(
+        hRmDevice, pDividerCinfo, AudioConfig.D);
+    *pAudioTargetKHz = NvRmPrivGetClockSourceFreq(pDividerCinfo->SourceId);
+}
+
+static void
+Ap15PllAControl(
+    NvRmDeviceHandle hRmDevice,
+    NvBool Enable)
+{
+    const NvRmDividerClockInfo* pCinfo =
+        NvRmPrivGetClockSourceHandle(NvRmClockSource_PllA0)->pInfo.pDivider;
+    if (NvRmPrivGetExecPlatform(hRmDevice) == ExecPlatform_Fpga)
+        return; // No PLLA control on FPGA
+
+    if (Enable)
+    {
+        Ap15PllControl(hRmDevice, NvRmClockSource_PllA1, NV_TRUE);
+    }
+    else
+    {
+        // Disable provided PLLA is not used as a source for any clock
+        if (NvRmPrivGetDfsFlags(hRmDevice) & NvRmDfsStatusFlags_StopPllA0)
+            Ap15PllControl(hRmDevice, NvRmClockSource_PllA1, NV_FALSE);
+    }
+    NvRmPrivDividerFreqUpdate(hRmDevice, pCinfo);
+}
+
+static void
+Ap15AudioSyncInit(NvRmDeviceHandle hRmDevice, NvRmFreqKHz AudioSyncKHz)
+{
+    NvRmFreqKHz AudioTargetKHz;
+    NvRmClockSource AudioSyncSource;
+    const NvRmSelectorClockInfo* pCinfo;
+    NV_ASSERT(hRmDevice);
+
+    // Configure PLLA. Requested frequency must always exactly match one of the
+    // fixed audio frequencies.
+    AudioTargetKHz = AudioSyncKHz;
+    Ap15PllAConfigure(hRmDevice, &AudioTargetKHz);
+    NV_ASSERT(AudioTargetKHz == AudioSyncKHz);
+
+    // Use PLLA as audio sync source, and disable doublers.
+    // (verify if SoC supports audio sync selectors)
+    AudioSyncSource = NvRmClockSource_PllA0;
+    if (NvRmPrivGetClockSourceHandle(NvRmClockSource_AudioSync))
+    {
+        pCinfo = NvRmPrivGetClockSourceHandle(
+            NvRmClockSource_AudioSync)->pInfo.pSelector;
+        NvRmPrivSelectorClockSet(hRmDevice, pCinfo, AudioSyncSource, NV_FALSE);
+    }
+    if (NvRmPrivGetClockSourceHandle(NvRmClockSource_MpeAudio))
+    {
+        pCinfo = NvRmPrivGetClockSourceHandle(
+            NvRmClockSource_MpeAudio)->pInfo.pSelector;
+        NvRmPrivSelectorClockSet(hRmDevice, pCinfo, AudioSyncSource, NV_FALSE);
+    }
+}
+
+/*****************************************************************************/
+
+static void
+Ap15PllDControl(
+    NvRmDeviceHandle hRmDevice,
+    NvBool Enable)
+{
+    NvU32 reg;
+    NvRmModuleClockInfo* pCinfo = NULL;
+    NvRmModuleClockState* pCstate = NULL;
+    NV_ASSERT_SUCCESS(NvRmPrivGetClockState(
+        hRmDevice, NvRmModuleID_Dsi, &pCinfo, &pCstate));
+    
+    if (Enable)
+    {
+        Ap15PllControl(hRmDevice, NvRmClockSource_PllD0, NV_TRUE);
+        pCstate->actual_freq =
+            NvRmPrivGetClockSourceFreq(NvRmClockSource_PllD0);
+        return;
+    }
+
+    // Disable PLLD if it is not used by either display head or DSI
+    reg = NV_REGR(hRmDevice, NvRmPrivModuleID_ClockAndReset, 0,
+                  pCinfo->ClkEnableOffset);
+    if (NvRmPrivIsSourceSelectedByModule(hRmDevice, NvRmClockSource_PllD0,
+                                   NVRM_MODULE_ID(NvRmModuleID_Display, 0)) ||
+        NvRmPrivIsSourceSelectedByModule(hRmDevice, NvRmClockSource_PllD0,
+                                   NVRM_MODULE_ID(NvRmModuleID_Display, 1)) ||
+        ((reg & pCinfo->ClkEnableField) == pCinfo->ClkEnableField))
+        return;
+
+    Ap15PllControl(hRmDevice, NvRmClockSource_PllD0, NV_FALSE);
+    pCstate->actual_freq =
+        NvRmPrivGetClockSourceFreq(NvRmClockSource_PllD0);
+}
+
+static void
+Ap15PllDConfigure(
+    NvRmDeviceHandle hRmDevice,
+    NvRmFreqKHz TargetFreq)
+{
+    NvRmFreqKHz MaxFreq = NvRmPrivGetSocClockLimits(NvRmModuleID_Dsi)->MaxKHz;
+    NvRmModuleClockInfo* pCinfo = NULL;
+    NvRmModuleClockState* pCstate = NULL;
+    NV_ASSERT_SUCCESS(NvRmPrivGetClockState(
+        hRmDevice, NvRmModuleID_Dsi, &pCinfo, &pCstate));
+
+    /*
+     * PLLD is adjusted when DDK/ODM is initializing DSI or reconfiguring
+     * display clock (for HDMI, DSI, or in some cases CRT).
+     */
+    if (NvRmIsFixedHdmiKHz(TargetFreq))
+    {
+        // 480p or 720p or 1080i/1080p HDMI - use fixed PLLD configuration
+        NvRmPrivAp15PllConfigureHdmi(
+            hRmDevice, NvRmClockSource_PllD0, &TargetFreq);
+    }
+    else
+    {
+        // for other targets use simple variable configuration
+        NV_ASSERT(TargetFreq <= MaxFreq);
+        NvRmPrivAp15PllConfigureSimple(
+            hRmDevice, NvRmClockSource_PllD0, MaxFreq, &TargetFreq);
+    }
+
+    // Update DSI clock state (PLLD is a single source, no divider)
+    pCstate->SourceClock = 0;
+    pCstate->Divider = 1;
+    pCstate->actual_freq =
+        NvRmPrivGetClockSourceFreq(NvRmClockSource_PllD0);
+    NvRmPrivModuleVscaleReAttach(hRmDevice,
+        pCinfo, pCstate, pCstate->actual_freq, pCstate->actual_freq, NV_FALSE);
+}
+
+/*****************************************************************************/
+/*****************************************************************************/
+
+static void
+Ap15DisplayClockConfigure(
+    NvRmDeviceHandle hRmDevice,
+    NvRmModuleClockInfo *pCinfo,
+    NvRmFreqKHz MinFreq,
+    NvRmFreqKHz MaxFreq,
+    NvRmFreqKHz TargetFreq,
+    NvRmModuleClockState* pCstate,
+    NvU32 flags)
+{
+    NvU32 i;
+    NvRmClockSource SourceId;
+    NvRmFreqKHz PixelFreq = TargetFreq;
+    NvRmFreqKHz SourceClockFreq = NvRmPrivGetClockSourceFreq(NvRmClockSource_ClkM);
+
+    // Clip target to maximum - we still may be able to configure frequency
+    // within tolearnce range
+    PixelFreq = TargetFreq = NV_MIN(TargetFreq, MaxFreq);
+
+    /*
+     * Display clock source selection policy:
+     * - if MIPI flag is specified - use PLLD, and reconfigure it as necessary
+     * - else if Oscillator output provides required accuracy - use Oscillator
+     * - else if PLLP fixed output provides required accuracy - use fixed PLLP
+     * - else if PPLC is used by other head - use PLLD, and reconfigure it as
+     *   necessary
+     * - else - use use PLLC, and reconfigure it as necessary
+     */
+    if (flags & NvRmClockConfig_MipiSync)
+    {
+        // PLLD requested
+        SourceId = NvRmClockSource_PllD0;
+        Ap15PllDConfigure(hRmDevice, TargetFreq);
+    }
+    else if (NvRmIsFreqRangeReachable(
+        SourceClockFreq, MinFreq, MaxFreq, NVRM_DISPLAY_DIVIDER_MAX))
+    {
+        // Target frequency is reachable from Oscillator - nothing to do
+        SourceId = NvRmClockSource_ClkM;
+    }
+    else if (NvRmIsFreqRangeReachable(NVRM_PLLP_FIXED_FREQ_KHZ,
+                MinFreq, MaxFreq, NVRM_DISPLAY_DIVIDER_MAX))
+    {
+        // Target frequency is reachable from PLLP0 - make sure it is enabled
+        SourceId = NvRmClockSource_PllP0;
+        Ap15PllPConfigure(hRmDevice);
+    }
+    else if (NvRmPrivIsSourceSelectedByModule(hRmDevice, NvRmClockSource_PllC0,
+                NVRM_MODULE_ID(pCinfo->Module, (1 - pCinfo->Instance))))
+    {
+        // PLLC is used by the other head - only PLLD left
+        SourceId = NvRmClockSource_PllD0;
+        Ap15PllDConfigure(hRmDevice, TargetFreq);
+    }
+    else
+    {
+        // PLLC is available - use it
+        SourceId = NvRmClockSource_PllC0;
+        if (!NvRmIsFixedHdmiKHz(TargetFreq))    // don't touch HDMI targets
+        {
+            TargetFreq = NvRmPrivGetMaxFreqPllC(hRmDevice); // Target PLLC max
+            if (!NvRmIsFreqRangeReachable(
+                TargetFreq, MinFreq, MaxFreq, NVRM_DISPLAY_DIVIDER_MAX))
+            {
+                TargetFreq = MaxFreq;               // Target pixel range max
+            }
+        }
+        NvRmPrivReConfigurePllC(hRmDevice, TargetFreq);
+    }
+
+    // Fill in clock state
+    for (i = 0; i < NvRmClockSource_Num; i++)
+    {
+        if (pCinfo->Sources[i] == SourceId)
+            break;
+    }
+    NV_ASSERT(i < NvRmClockSource_Num);
+    pCstate->SourceClock = i;       // source index
+    pCstate->Divider = 1;           // no divider (display driver has its own)
+    pCstate->actual_freq = NvRmPrivGetClockSourceFreq(SourceId); // source KHz
+    NV_ASSERT(NvRmIsFreqRangeReachable(
+        pCstate->actual_freq, MinFreq, MaxFreq, NVRM_DISPLAY_DIVIDER_MAX));
+
+    if (flags & NvRmClockConfig_SubConfig)
+    {
+        NvRmModuleClockInfo* pTvDacInfo = NULL;
+        NvRmModuleClockState* pTvDacState = NULL;
+        NV_ASSERT_SUCCESS(NvRmPrivGetClockState(
+            hRmDevice, NvRmModuleID_Tvo, &pTvDacInfo, &pTvDacState));
+
+        // TVDAC is the 2nd TVO subclock (CVE is the 1st one)
+        pTvDacInfo += 2;
+        pTvDacState += 2;
+        NV_ASSERT(pTvDacInfo->Module == NvRmModuleID_Tvo);
+        NV_ASSERT(pTvDacInfo->SubClockId == 2);
+
+        // enable the tvdac clock
+        if ((hRmDevice->ChipId.Id == 0x15) || (hRmDevice->ChipId.Id == 0x16))
+            Ap15EnableTvDacClock(hRmDevice, ModuleClockState_Enable);
+        else if (hRmDevice->ChipId.Id == 0x20)
+            Ap20EnableTvDacClock(hRmDevice, ModuleClockState_Enable);
+
+        // Set TVDAC = pixel clock (same source index and calculate divider
+        // exactly as dc_hal.c does)
+        pTvDacState->SourceClock = i;
+        pTvDacState->Divider =
+            (((pCstate->actual_freq * 2 ) + PixelFreq / 2) / PixelFreq) - 2;
+        pTvDacState->actual_freq =
+            (pCstate->actual_freq * 2 ) / (pTvDacState->Divider + 2);
+        NvRmPrivModuleClockSet(hRmDevice, pTvDacInfo, pTvDacState); 
+    }
+    if (flags & NvRmClockConfig_DisableTvDAC)
+    {
+        // disable the tvdac clock
+        if ((hRmDevice->ChipId.Id == 0x15) || (hRmDevice->ChipId.Id == 0x16))
+            Ap15EnableTvDacClock(hRmDevice, ModuleClockState_Disable);
+        else if (hRmDevice->ChipId.Id == 0x20)
+            Ap20EnableTvDacClock(hRmDevice, ModuleClockState_Disable);
+    }
+}
+
+NvBool
+NvRmPrivAp15IsModuleClockException(
+    NvRmDeviceHandle hRmDevice,
+    NvRmModuleClockInfo *pCinfo,
+    NvU32 ClockSourceCount,
+    NvRmFreqKHz MinFreq,
+    NvRmFreqKHz MaxFreq,
+    const NvRmFreqKHz* PrefFreqList,
+    NvU32 PrefCount,
+    NvRmModuleClockState* pCstate,
+    NvU32 flags)
+{
+    NvU32 i;
+    NvRmFreqKHz FreqKHz;
+    NvRmClockSource SourceId;
+
+    NV_ASSERT(hRmDevice);
+    NV_ASSERT(pCinfo && PrefFreqList && pCstate);
+
+    switch (pCinfo->Module)
+    {
+        case NvRmModuleID_Display:
+            /*
+             * Special handling for display clocks. Must satisfy requirements
+             * for the 1st requested frequency and complete configuration.
+             * Note that AP15 display divider is within module itself, so the
+             * input request is for pisxel clock, but output *pCstate specifies
+             * source frequency. Display driver will configure divider.
+             */
+            Ap15DisplayClockConfigure(hRmDevice, pCinfo,
+                MinFreq, MaxFreq, PrefFreqList[0], pCstate, flags);
+            return NV_TRUE;
+
+        case NvRmModuleID_Dsi:
+            /*
+             * Reconfigure PLLD to match requested frequency, and update DSI
+             * clock state.
+             */ 
+            Ap15PllDConfigure(hRmDevice, PrefFreqList[0]);
+            NV_ASSERT((MinFreq <= pCstate->actual_freq) &&
+                      (pCstate->actual_freq <= MaxFreq));
+            return NV_TRUE;
+
+        case NvRmModuleID_Hdmi:
+            /*
+             * Complete HDMI configuration; choose among possible sources:
+             * PLLP, PLLD, PLLC in the same order as for display (PLLD or
+             * PLLC should be already configured properly for display)
+             */
+            if (flags & NvRmClockConfig_MipiSync)
+                SourceId = NvRmClockSource_PllD0;
+            else if (NvRmIsFreqRangeReachable(NVRM_PLLP_FIXED_FREQ_KHZ,
+                         MinFreq, MaxFreq, NVRM_DISPLAY_DIVIDER_MAX))
+                SourceId = NvRmClockSource_PllP0;
+            else
+                SourceId = NvRmClockSource_PllC0;
+
+            // HDMI clock state with selected source
+            for (i = 0; i < NvRmClockSource_Num; i++)
+            {
+                if (pCinfo->Sources[i] == SourceId)
+                    break;
+            }
+            NV_ASSERT(i < NvRmClockSource_Num);
+            pCstate->SourceClock = i;       // source index
+            FreqKHz = NvRmPrivGetClockSourceFreq(SourceId);
+            pCstate->Divider = ((FreqKHz << 2) + PrefFreqList[0]) /
+                               (PrefFreqList[0] << 1) - 2;
+            pCstate->actual_freq = (FreqKHz << 1) / (pCstate->Divider + 2);
+            NV_ASSERT(pCstate->Divider <= pCinfo->DivisorFieldMask);
+            NV_ASSERT((MinFreq <= pCstate->actual_freq) &&
+                      (pCstate->actual_freq <= MaxFreq));
+            return NV_TRUE;
+
+        case NvRmModuleID_Spdif:
+            if (flags & NvRmClockConfig_SubConfig)
+                return NV_FALSE; // Nothing special for SPDIFIN
+            // fall through for SPDIFOUT
+        case NvRmModuleID_I2s:
+            /*
+             * If requested, reconfigure PLLA to match target frequency, and
+             * complete clock configuration with PLLA as a source. Otherwise,
+             * make sure PLLA is enabled (at current configuration), and
+             * continue regular configuration for SPDIFOUT and I2S.
+             */
+            if (flags & NvRmClockConfig_AudioAdjust)
+            {
+                FreqKHz = PrefFreqList[0];
+                Ap15PllAConfigure(hRmDevice, &FreqKHz);
+
+                pCstate->SourceClock = 0;   // PLLA source index
+                pCstate->Divider = ((FreqKHz << 2) + PrefFreqList[0]) /
+                                    (PrefFreqList[0] << 1) - 2;
+                pCstate->actual_freq = (FreqKHz << 1) / (pCstate->Divider + 2);
+                if (NvRmPrivGetExecPlatform(hRmDevice) == ExecPlatform_Fpga)
+                {   // Fake return on FPGA (PLLA is not configurable, anyway)
+                    pCstate->actual_freq = PrefFreqList[0]; 
+                }
+                NV_ASSERT(pCinfo->Sources[pCstate->SourceClock] ==
+                          NvRmClockSource_PllA0);
+                NV_ASSERT(pCstate->Divider <= pCinfo->DivisorFieldMask);
+                NV_ASSERT((MinFreq <= pCstate->actual_freq) &&
+                          (pCstate->actual_freq <= MaxFreq));
+                return NV_TRUE;
+            }
+            Ap15PllAControl(hRmDevice, NV_TRUE);
+            return NV_FALSE;
+
+        case NvRmModuleID_Usb2Otg:
+            /*
+             * Reconfigure PLLU to match requested frequency, and complete USB
+             * clock configuration (PLLU is a single source, no divider)
+             */ 
+            Ap15PllUConfigure(hRmDevice, PrefFreqList[0]);
+            pCstate->SourceClock = 0;
+            pCstate->Divider = 1;
+            pCstate->actual_freq =
+                NvRmPrivGetClockSourceFreq(pCinfo->Sources[0]);
+            return NV_TRUE;
+
+        default:
+            // No exception for other modules - continue regular configuration
+            return NV_FALSE;
+    }
+}
+
+/*****************************************************************************/
+
+void
+NvRmPrivAp15DisablePLLs(
+    NvRmDeviceHandle hRmDevice,
+    const NvRmModuleClockInfo* pCinfo,
+    const NvRmModuleClockState* pCstate)
+{
+#if !NV_OAL
+    switch (pCinfo->Module)
+    {
+        case NvRmModuleID_Display:
+            NvRmPrivBoostPllC(hRmDevice);
+            Ap15PllDControl(hRmDevice, NV_FALSE);
+            break;
+
+        case NvRmModuleID_Spdif:
+        case NvRmModuleID_I2s:
+            Ap15PllAControl(hRmDevice, NV_FALSE);
+            break;
+
+        default:
+            break;
+    }
+#endif
+}
+
+void
+NvRmPrivAp15PllDPowerControl(
+    NvRmDeviceHandle hRmDevice,
+    NvBool ConfigEntry,
+    NvBool* pMipiPllVddOn)
+{
+#if !NV_OAL
+    if (ConfigEntry)
+    {
+        // On entry to display clock configuration get PLLD power ready
+        if (!(*pMipiPllVddOn))
+        {
+            NvRmPrivPmuRailControl(hRmDevice, NV_VDD_PLLD_ODM_ID, NV_TRUE);
+            *pMipiPllVddOn = NV_TRUE;
+        }
+    }
+    else
+    {
+        // On exit from display clock configuration turn off PLLD power
+        // if it is disabled
+        if ((*pMipiPllVddOn) &&
+            (NvRmPrivGetClockSourceFreq(NvRmClockSource_PllD0) == 0))
+        {
+            NvRmPrivPmuRailControl(hRmDevice, NV_VDD_PLLD_ODM_ID, NV_FALSE);
+            *pMipiPllVddOn = NV_FALSE;
+        }
+    }
+#endif
+}
+
+void
+NvRmPrivConfigureClockSource(
+        NvRmDeviceHandle hRmDevice,
+        NvRmModuleID ModuleId,
+        NvBool enable)
+{
+    // Extract module and instance from composite module id.
+    NvU32 Module   = NVRM_MODULE_ID_MODULE( ModuleId );
+
+    switch (Module)
+    {
+        case NvRmModuleID_Usb2Otg:
+            // Do not disable the PLLU clock once it is enabled
+            // Set PLLU default configuration if it is not already configured
+            if (enable)
+                Ap15PllUConfigure(hRmDevice, NvRmFreqUnspecified);
+            break;
+#if !NV_OAL
+        case NvRmModuleID_Spdif:
+        case NvRmModuleID_I2s:
+            if (enable)
+            {
+                // Do not enable if PLLA is not used as a source for any clock
+                if (NvRmPrivGetDfsFlags(hRmDevice) & NvRmDfsStatusFlags_StopPllA0)
+                    break;
+            }
+            // fall through
+        case NvRmModuleID_Mpe:
+            Ap15PllAControl(hRmDevice, enable);
+            break;
+
+        case NvRmModuleID_Dsi:
+            Ap15PllDControl(hRmDevice, enable);
+            break;
+
+        case NvRmPrivModuleID_Pcie:
+            NvRmPrivAp20PllEControl(hRmDevice, enable);
+            break;
+#endif
+        default:
+            break;
+    }
+    return;
+}
+
+/*****************************************************************************/
+/*****************************************************************************/
+
+/*
+ * Basic DFS clock control policy outline:
+ * - Oscillator ClkM, doubler ClkD, and memory PLLM0 - always available, fixed
+ *   frequency sources.
+ * - Peripheral PLLP0 may be dynamically enabled / disabled when DFS is stopped
+ *   and CPU is power gated. Hence, when DFS is running it is always enabled
+ *   and configured at fixed PLLP0 frequency.
+ * - Cpu PLLC0 may be dynamically enabled / disabled when DFS is stopped and
+ *   CPU is power gated. Hence, when DFS is running it is always enabled. PLLC0
+ *   is commonly configured at maximum CPU domain frequency. If necessary, it
+ *   may be adjusted to provide required display pixel clock frequency.
+ * - System buses, and MC/EMC configuration, clock source multiplexes and
+ *   dividers, as well as PLLP2, PLLP4 and PLLM1 dividers are under exclusive
+ *   DFS control, and are not accessed by any other code except bootloader
+ *   before RM is open.
+ */
+
+// Limit frequencies ratio for Vpipe : System >= 1 : 2^(value - 1)
+#define LIMIT_SYS_TO_VDE_RATIO (2)
+
+// Limit frequencies ratio for AHB : System >= 1:2 and APB : System >= 1 : 4
+#define LIMIT_SYS_TO_AHB_APB_RATIOS (1)
+
+// PLLP2 must be used as a variable source for System clock.
+#define PLLP_POLICY_ENTRY(KHz) \
+ { NvRmClockSource_PllP2,\
+   (NVRM_PLLP_FIXED_FREQ_KHZ * 2)/((NVRM_PLLP_FIXED_FREQ_KHZ * 2)/KHz),\
+   ((NVRM_PLLP_FIXED_FREQ_KHZ * 2)/KHz - 2)\
+ },
+static const NvRmDfsSource s_Ap15PllPSystemClockPolicy[] =
+{
+    NVRM_AP15_PLLP_POLICY_SYSTEM_CLOCK
+};
+static const NvU32 s_Ap15PllPSystemClockPolicyEntries =
+    NV_ARRAY_SIZE(s_Ap15PllPSystemClockPolicy);
+#undef PLLP_POLICY_ENTRY
+
+
+// PLLP4 must be used as a variable source for cpu clock.
+#define PLLP_POLICY_ENTRY(KHz) \
+ { NvRmClockSource_PllP4,\
+   (NVRM_PLLP_FIXED_FREQ_KHZ * 2)/((NVRM_PLLP_FIXED_FREQ_KHZ * 2)/KHz),\
+   ((NVRM_PLLP_FIXED_FREQ_KHZ * 2)/KHz - 2)\
+ },
+static const NvRmDfsSource s_Ap15PllPCpuClockPolicy[] =
+{
+    NVRM_AP15_PLLP_POLICY_CPU_CLOCK
+};
+static const NvU32 s_Ap15PllPCpuClockPolicyEntries =
+    NV_ARRAY_SIZE(s_Ap15PllPCpuClockPolicy);
+#undef PLLP_POLICY_ENTRY
+
+/*
+ * Sorted list of timing parameters for discrete set of EMC frequencies used
+ * by DFS: entry 0 specifies timing parameters for PLLM0 output frequency,
+ * entry n (n = 1, 2, ... number of EMC steps-1) specifies timing parameters
+ * for EMC frequency = PLLM0 frequency / (2 * n); thus only frequencies evenly
+ * divided down from PLLM0 will be used by DFS
+ */
+static NvRmAp15EmcTimingConfig
+s_Ap15EmcConfigSortedTable[NVRM_AP15_DFS_EMC_FREQ_STEPS];
+
+static struct MemClocksRec
+{
+    // Index of selected EMC configuration entry
+    NvU32 Index;
+
+    // Pointers to EMC and MC clock descriptors
+    NvRmModuleClockInfo* pEmcInfo;
+    NvRmModuleClockInfo* pMcInfo;
+
+    // Pointers to EMC and MC clock state records
+    NvRmModuleClockState* pEmcState;
+    NvRmModuleClockState* pMcState;
+
+} s_MemClocks = {0};
+
+static const NvU32 s_Cpu2EmcRatioPolicyTable[] =
+{
+    NVRM_AP15_CPU_EMC_RATIO_POLICY
+};
+
+/*****************************************************************************/
+
+static void
+Ap15Emc2xFreqGet(
+    NvRmDeviceHandle hRmDevice)
+{
+    NvU32 reg;
+    NvRmFreqKHz SourceClockFreq;
+    NvRmModuleClockInfo* pCinfo = s_MemClocks.pEmcInfo;
+    NvRmModuleClockState* pCstate = s_MemClocks.pEmcState;
+
+    NV_ASSERT(pCinfo && pCstate);
+
+    // Determine EMC2x source and divider setting; update EMC2x clock state
+    reg = NV_REGR(hRmDevice,
+                  NvRmPrivModuleID_ClockAndReset, 0, pCinfo->ClkSourceOffset);
+    pCstate->Divider =
+        ((reg >> pCinfo->DivisorFieldShift) & pCinfo->DivisorFieldMask);
+    pCstate->SourceClock =
+        ((reg >> pCinfo->SourceFieldShift) & pCinfo->SourceFieldMask);
+    SourceClockFreq =
+        NvRmPrivGetClockSourceFreq(pCinfo->Sources[pCstate->SourceClock]);
+
+    // Fractional divider output = (Source Frequency * 2) / (divider + 2)
+    pCstate->actual_freq = ((SourceClockFreq << 1) / (pCstate->Divider + 2));
+}
+
+// Enable/Disable EMC low-latency return-fifo reservation scheme
+// (enable requires confirmation polling)
+#define NVRM_AP15_EMCLL_RETRSV_ENABLE \
+do\
+{\
+    NvU32 reg; \
+    reg = NV_REGR(hRmDevice, NvRmPrivModuleID_ExternalMemoryController, \
+                  0, EMC_LL_ARB_CONFIG_0); \
+    reg = NV_FLD_SET_DRF_DEF( \
+        EMC, LL_ARB_CONFIG, LL_RETRSV_ENABLE, ENABLED, reg); \
+    NV_REGW(hRmDevice, NvRmPrivModuleID_ExternalMemoryController, \
+            0, EMC_LL_ARB_CONFIG_0, reg); \
+    while (reg != NV_REGR(hRmDevice, NvRmPrivModuleID_ExternalMemoryController,\
+                          0, EMC_LL_ARB_CONFIG_0)) \
+        ; \
+} while(0)
+
+#define NVRM_AP15_EMCLL_RETRSV_DISABLE \
+do\
+{\
+    NvU32 reg; \
+    reg = NV_REGR(hRmDevice, NvRmPrivModuleID_ExternalMemoryController, \
+                  0, EMC_LL_ARB_CONFIG_0); \
+    reg = NV_FLD_SET_DRF_DEF( \
+        EMC, LL_ARB_CONFIG, LL_RETRSV_ENABLE, DISABLED, reg); \
+    NV_REGW(hRmDevice, NvRmPrivModuleID_ExternalMemoryController, \
+            0, EMC_LL_ARB_CONFIG_0, reg); \
+} while (0)
+
+void
+NvRmPrivAp15SetEmcForCpuSrcSwitch(NvRmDeviceHandle hRmDevice)
+{
+    NVRM_AP15_EMCLL_RETRSV_ENABLE;
+}
+
+void
+NvRmPrivAp15SetEmcForCpuDivSwitch(
+    NvRmDeviceHandle hRmDevice,
+    NvRmFreqKHz CpuFreq,
+    NvBool Before)
+{
+    NvRmFreqKHz EmcFreq = (s_MemClocks.pEmcState->actual_freq >> 1);
+    if (Before && (CpuFreq < EmcFreq))
+    {
+         NVRM_AP15_EMCLL_RETRSV_ENABLE;
+    }
+    else if (!Before && (CpuFreq >= EmcFreq))
+    {
+        NVRM_AP15_EMCLL_RETRSV_DISABLE;
+    }
+}
+
+static void
+Ap15EmcTimingSet(
+    NvRmDeviceHandle hRmDevice,
+    NvBool FreqRising,
+    NvBool BeforeDividerChange,
+    const NvRmAp15EmcTimingConfig* pEmcConfig)
+{
+    // Write shadow timing registers
+    if (FreqRising == BeforeDividerChange)  // "overlap down" parameters
+    {
+        NV_REGW(hRmDevice, NvRmPrivModuleID_ExternalMemoryController, 0,
+                EMC_TIMING0_0, pEmcConfig->Timing0Reg);
+        NV_REGW(hRmDevice, NvRmPrivModuleID_ExternalMemoryController, 0,
+                EMC_TIMING1_0, pEmcConfig->Timing1Reg);
+        NV_REGW(hRmDevice, NvRmPrivModuleID_ExternalMemoryController, 0,
+                EMC_TIMING2_0, pEmcConfig->Timing2Reg);
+        NV_REGW(hRmDevice, NvRmPrivModuleID_ExternalMemoryController, 0,
+                EMC_TIMING3_0, pEmcConfig->Timing3Reg);
+        NV_REGW(hRmDevice, NvRmPrivModuleID_ExternalMemoryController, 0,
+                EMC_TIMING5_0, pEmcConfig->Timing5Reg);
+    }
+    else                                    // "overlap up" parameters
+    {
+        NV_REGW(hRmDevice, NvRmPrivModuleID_ExternalMemoryController, 0,
+                EMC_TIMING4_0, pEmcConfig->Timing4Reg);
+
+        NV_REGW(hRmDevice, NvRmPrivModuleID_ExternalMemoryController, 0,
+                EMC_FBIO_CFG6_0, pEmcConfig->FbioCfg6Reg);
+        NV_REGW(hRmDevice, NvRmPrivModuleID_ExternalMemoryController, 0,
+                EMC_FBIO_DQSIB_DLY_0, pEmcConfig->FbioDqsibDly);
+        NV_REGW(hRmDevice, NvRmPrivModuleID_ExternalMemoryController, 0,
+                EMC_FBIO_QUSE_DLY_0, pEmcConfig->FbioQuseDly);
+    }
+    // Trigger active register update from shadow
+    NV_REGW(hRmDevice, NvRmPrivModuleID_ExternalMemoryController, 0,
+            EMC_TIMING_CONTROL_0, 0x1);
+
+    // Make sure update from shadow is completed
+    if (FreqRising == BeforeDividerChange)
+    {
+        while((NV_REGR(hRmDevice, NvRmPrivModuleID_ExternalMemoryController, 0,
+                       EMC_TIMING0_0)) != pEmcConfig->Timing0Reg);
+    }
+    else
+    {
+        while((NV_REGR(hRmDevice, NvRmPrivModuleID_ExternalMemoryController, 0,
+                       EMC_TIMING4_0)) != pEmcConfig->Timing4Reg);
+        // Re-trigger active register update (need it for trimmers only)
+        NV_REGW(hRmDevice, NvRmPrivModuleID_ExternalMemoryController, 0,
+                EMC_TIMING_CONTROL_0, 0x1);
+    }
+}
+
+static void
+Ap15Emc2xClockSet(
+    NvRmDeviceHandle hRmDevice,
+    NvBool FreqRising,
+    const NvRmAp15EmcTimingConfig* pEmcConfig)
+{
+    NvU32 reg = NV_REGR(hRmDevice, NvRmPrivModuleID_ClockAndReset, 0,
+                        CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0);
+    reg = NV_FLD_SET_DRF_NUM(CLK_RST_CONTROLLER, CLK_SOURCE_EMC,
+                         EMC_2X_CLK_DIVISOR, pEmcConfig->Emc2xDivisor, reg);
+    NV_ASSERT(pEmcConfig->Emc2xKHz);    // validate table entry
+
+    // Update EMC state
+    s_MemClocks.pEmcState->actual_freq = pEmcConfig->Emc2xKHz;
+    s_MemClocks.pEmcState->Divider = pEmcConfig->Emc2xDivisor;
+
+    // Set EMC parameters and EMC divisor (the EMC clock source is always
+    // PLLM0 starting from BL)
+    Ap15EmcTimingSet(hRmDevice, FreqRising, NV_TRUE, pEmcConfig);
+    NV_REGW(hRmDevice, NvRmPrivModuleID_ClockAndReset, 0,
+            CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0, reg);
+    Ap15EmcTimingSet(hRmDevice, FreqRising, NV_FALSE, pEmcConfig);
+}
+
+static void
+Ap15McClockSet(
+    NvRmDeviceHandle hRmDevice,
+    const NvRmAp15EmcTimingConfig* pEmcConfig)
+{
+    NvU32 src, div;
+    NvU32 reg = NV_REGR(hRmDevice, NvRmPrivModuleID_ClockAndReset, 0,
+                        CLK_RST_CONTROLLER_CLK_SOURCE_MEM_0);
+    src = NV_DRF_VAL(CLK_RST_CONTROLLER, CLK_SOURCE_MEM, MEM_CLK_SRC, reg);
+    div = NV_DRF_VAL(CLK_RST_CONTROLLER, CLK_SOURCE_MEM, MEM_CLK_DIVISOR, reg);
+
+    // Update MC state
+    s_MemClocks.pMcState->actual_freq = pEmcConfig->McKHz;
+    s_MemClocks.pMcState->SourceClock = pEmcConfig->McClockSource;
+    s_MemClocks.pMcState->Divider = pEmcConfig->McDivisor;
+
+    // Set MC divisor before source, if new value is bigger than the old one
+    if (pEmcConfig->McDivisor > div)
+    {
+        reg = NV_FLD_SET_DRF_NUM(CLK_RST_CONTROLLER, CLK_SOURCE_MEM,
+            MEM_CLK_DIVISOR, pEmcConfig->McDivisor, reg);
+        NV_REGW(hRmDevice, NvRmPrivModuleID_ClockAndReset, 0,
+                CLK_RST_CONTROLLER_CLK_SOURCE_MEM_0, reg);
+        NvOsWaitUS(NVRM_CLOCK_CHANGE_DELAY);
+    }
+
+    // Modify MC source if it is to be changed
+    if (pEmcConfig->McClockSource != src)
+    {
+        NvRmPrivMemoryClockReAttach(
+            hRmDevice, s_MemClocks.pMcInfo, s_MemClocks.pMcState);
+        reg = NV_FLD_SET_DRF_NUM(CLK_RST_CONTROLLER, CLK_SOURCE_MEM,
+            MEM_CLK_SRC, pEmcConfig->McClockSource, reg);
+        NV_REGW(hRmDevice, NvRmPrivModuleID_ClockAndReset, 0,
+                CLK_RST_CONTROLLER_CLK_SOURCE_MEM_0, reg);
+        NvOsWaitUS(NVRM_CLOCK_CHANGE_DELAY);
+    }
+
+    // Set MC divisor after source, if new value is smaller than the old one
+    if (pEmcConfig->McDivisor < div)
+    {
+        reg = NV_FLD_SET_DRF_NUM(CLK_RST_CONTROLLER, CLK_SOURCE_MEM,
+            MEM_CLK_DIVISOR, pEmcConfig->McDivisor, reg);
+        NV_REGW(hRmDevice, NvRmPrivModuleID_ClockAndReset, 0,
+                CLK_RST_CONTROLLER_CLK_SOURCE_MEM_0, reg);
+        NvOsWaitUS(NVRM_CLOCK_CHANGE_DELAY);
+    }
+}
+
+void
+NvRmPrivAp15EmcConfigInit(NvRmDeviceHandle hRmDevice)
+{
+    NvU32 i, j, k, reg=0;
+    NvU32 ConfigurationsCount;
+    NvRmFreqKHz Emc2xKHz, McKHz, McMax;
+    NvRmFreqKHz PllM0KHz = NvRmPrivGetClockSourceFreq(NvRmClockSource_PllM0);
+    const NvOdmSdramControllerConfig* pEmcConfigurations =
+        NvOdmQuerySdramControllerConfigGet(&ConfigurationsCount, &reg);
+
+    // Init memory configuration structure
+    NV_ASSERT_SUCCESS(NvRmPrivGetClockState(
+        hRmDevice, NvRmPrivModuleID_ExternalMemoryController,
+        &s_MemClocks.pEmcInfo, &s_MemClocks.pEmcState));
+     NV_ASSERT_SUCCESS(NvRmPrivGetClockState(
+         hRmDevice, NvRmPrivModuleID_MemoryController,
+         &s_MemClocks.pMcInfo, &s_MemClocks.pMcState));
+     s_MemClocks.Index = NVRM_AP15_DFS_EMC_FREQ_STEPS;  // invalid index
+     NvOsMemset(s_Ap15EmcConfigSortedTable, 0,          // clean table
+                sizeof(s_Ap15EmcConfigSortedTable));
+
+     // Get EMC2x clock state from h/w
+     Ap15Emc2xFreqGet(hRmDevice);
+
+    // Check if configuration table is provided by ODM
+    if ((ConfigurationsCount == 0) || (pEmcConfigurations == NULL))
+    {
+        s_Ap15EmcConfigSortedTable[0].Emc2xKHz = 0; // invalidate PLLM0 entry
+        return;
+    }
+    if (reg != NV_EMC_BASIC_REV)
+    {
+        s_Ap15EmcConfigSortedTable[0].Emc2xKHz = 0; // invalidate PLLM0 entry
+        NV_ASSERT(!"Invalid configuration table revision");
+        return;
+    }
+
+    // Check PLLM0 range
+    NV_ASSERT(PllM0KHz);
+    if (PllM0KHz > (NvRmPrivGetSocClockLimits(
+        NvRmPrivModuleID_ExternalMemoryController)->MaxKHz))
+    {
+        s_Ap15EmcConfigSortedTable[0].Emc2xKHz = 0; // invalidate PLLM0 entry
+        NV_ASSERT(!"PLLM0 is outside supported EMC range");
+        return;
+    }
+
+    // Check if PLLM0 is configured by boot loader as EMC clock source
+    // (it can not and will not be changed by RM)
+    if (s_MemClocks.pEmcState->SourceClock !=
+        CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_SRC_PLLM_OUT0)
+    {
+        s_Ap15EmcConfigSortedTable[0].Emc2xKHz = 0; // invalidate PLLM0 entry
+        NV_ASSERT(!"Other than PLLM0 clock source is used for EMC");
+        return;
+    }
+
+    // Sort list of EMC timing parameters in descending order of frequencies
+    // evenly divided down from PLLM0; find matching entry for boot divisor
+    for (i = 0, k = 0, Emc2xKHz = PllM0KHz; i < NVRM_AP15_DFS_EMC_FREQ_STEPS; )
+    {
+        s_Ap15EmcConfigSortedTable[i].Emc2xKHz = 0; // mark entry invalid
+        for (j = 0; j < ConfigurationsCount; j++)
+        {
+            // Find match with 1MHz tolerance for allowed configuration
+            if ((Emc2xKHz <= (pEmcConfigurations[j].SdramKHz * 2 + 1000)) &&
+                (Emc2xKHz >= (pEmcConfigurations[j].SdramKHz * 2 - 1000)))
+            {
+                s_Ap15EmcConfigSortedTable[i].Timing0Reg = pEmcConfigurations[j].EmcTiming0;
+                s_Ap15EmcConfigSortedTable[i].Timing1Reg = pEmcConfigurations[j].EmcTiming1;
+                s_Ap15EmcConfigSortedTable[i].Timing2Reg = pEmcConfigurations[j].EmcTiming2;
+                s_Ap15EmcConfigSortedTable[i].Timing3Reg = pEmcConfigurations[j].EmcTiming3;
+                s_Ap15EmcConfigSortedTable[i].Timing4Reg = pEmcConfigurations[j].EmcTiming4;
+                s_Ap15EmcConfigSortedTable[i].Timing5Reg = pEmcConfigurations[j].EmcTiming5;
+
+                s_Ap15EmcConfigSortedTable[i].FbioCfg6Reg =
+                    pEmcConfigurations[j].EmcFbioCfg6;
+                s_Ap15EmcConfigSortedTable[i].FbioDqsibDly =
+                    pEmcConfigurations[j].EmcFbioDqsibDly +
+                    NvRmPrivGetEmcDqsibOffset(hRmDevice);
+                s_Ap15EmcConfigSortedTable[i].FbioQuseDly = 
+                    pEmcConfigurations[j].EmcFbioQuseDly;
+                s_Ap15EmcConfigSortedTable[i].CoreVoltageMv =
+                    pEmcConfigurations[j].EmcCoreVoltageMv;
+
+                // Determine EMC and MC clock divisors, MC clock source
+                // (EMC always uses PLLM0 as a source), and CPU clock limit
+                s_Ap15EmcConfigSortedTable[i].Emc2xKHz = Emc2xKHz; // accurate KHz
+                if (i == 0)
+                {
+                    /*
+                     * The first table entry specifies parameters for EMC2xFreq
+                     * = PLLM0 frequency; the divisor field in EMC fractional
+                     * divider register is set to "0". The divisor field in MC
+                     * divider is set to "1", so that Emc1xFreq ~ 75% of McFreq
+                     * using PLLM0 as MC clock source, if maximum MC frequency
+                     * limit is not violated. Otherwise, find the highest MC
+                     * frequency below the limit with PLLP0 as a source.
+                     */
+                    s_Ap15EmcConfigSortedTable[i].Emc2xDivisor = 0;
+                    McKHz = (PllM0KHz * 2) / 3;
+                    McMax = NvRmPrivGetSocClockLimits(
+                        NvRmPrivModuleID_MemoryController)->MaxKHz;
+                    NV_ASSERT(McMax);
+                    if (McKHz <= McMax)
+                    {
+                        s_Ap15EmcConfigSortedTable[i].McDivisor = 1;
+                        s_Ap15EmcConfigSortedTable[i].McClockSource =
+                            CLK_RST_CONTROLLER_CLK_SOURCE_MEM_0_MEM_CLK_SRC_PLLM_OUT0;
+                    }
+                    else if (NVRM_PLLP_FIXED_FREQ_KHZ <= McMax)
+                    {
+                        McKHz = NVRM_PLLP_FIXED_FREQ_KHZ;
+                        s_Ap15EmcConfigSortedTable[i].McDivisor = 0;
+                        s_Ap15EmcConfigSortedTable[i].McClockSource =
+                            CLK_RST_CONTROLLER_CLK_SOURCE_MEM_0_MEM_CLK_SRC_PLLP_OUT0;
+                    }
+                    else
+                    {
+                        reg = (2 * NVRM_PLLP_FIXED_FREQ_KHZ + McMax - 1) / McMax;
+                        McKHz = (2 * NVRM_PLLP_FIXED_FREQ_KHZ) / reg;
+                        s_Ap15EmcConfigSortedTable[i].McDivisor = reg - 2;
+                        s_Ap15EmcConfigSortedTable[i].McClockSource =
+                            CLK_RST_CONTROLLER_CLK_SOURCE_MEM_0_MEM_CLK_SRC_PLLP_OUT0;
+                    }
+                }
+                else
+                {
+                    /*
+                     * If i = 1, 2, ... the table entry specifies parameters
+                     * for EMC2xFreq = PLLM0 frequency/(2 * k); the divisor
+                     * field in EMC fractional divider register should be set
+                     * as 2 * (2 * k) - 2 = 4 * k - 2. The divisor field in MC
+                     * divider is determined so that Emc1xFreq ~ 85% of McFreq
+                     * using the same PLLM0 as MC clock source
+                     */
+                    s_Ap15EmcConfigSortedTable[i].Emc2xDivisor = (k << 2) - 2;
+                    s_Ap15EmcConfigSortedTable[i].McDivisor = (19 +
+                         17 * s_Ap15EmcConfigSortedTable[i].Emc2xDivisor) / 10;
+                    s_Ap15EmcConfigSortedTable[i].McClockSource =
+                        CLK_RST_CONTROLLER_CLK_SOURCE_MEM_0_MEM_CLK_SRC_PLLM_OUT0;
+                    McKHz = 2 * PllM0KHz /
+                        (s_Ap15EmcConfigSortedTable[i].McDivisor + 2);
+                }
+                if (s_Ap15EmcConfigSortedTable[i].Emc2xDivisor ==
+                    s_MemClocks.pEmcState->Divider)
+                {
+                    s_MemClocks.Index = i;      // Boot configuration found
+                }
+                s_Ap15EmcConfigSortedTable[i].McKHz = McKHz;
+                /*
+                 * H/w CPU clock limit is determined from inequality:
+                 * 1 mcclk period + 12 cpuclk periods >= 2 emcclck periods, or
+                 * CpuKHz <= 11.9 * McKHz * Emc2xKHz / (4 * McKHz - Emc2xKHz)
+                 * with 0.1/12 ~ 0.8% margin
+                 * S/w CPU clock limit is determined per s/w policy:
+                 * CpuKHz <= CpuMax * PolicyTabel[PLLM0/(2*EMC2xKHz)] / 256
+                 * Final CPU clock limit is minimum of the above limits
+                 */
+                s_Ap15EmcConfigSortedTable[i].CpuLimitKHz =
+                    (NvU32)NvDiv64(((NvU64)Emc2xKHz * McKHz * 119), 
+                                (((McKHz << 2) - Emc2xKHz) * 10));
+                reg = NvRmPrivGetSocClockLimits(NvRmModuleID_Cpu)->MaxKHz;
+                if (k != 0)
+                {
+                    NV_ASSERT(k < NV_ARRAY_SIZE(s_Cpu2EmcRatioPolicyTable));
+                    reg = (reg * s_Cpu2EmcRatioPolicyTable[k]) >> 8;
+                }
+                if (s_Ap15EmcConfigSortedTable[i].CpuLimitKHz > reg)
+                    s_Ap15EmcConfigSortedTable[i].CpuLimitKHz = reg;
+
+                break;
+            }
+        }
+        if (s_Ap15EmcConfigSortedTable[i].Emc2xKHz != 0)
+            i++;                // Entry found - advance sorting index
+        else if (i == 0)
+            break;              // PLLM0 entry not found - abort sorting 
+
+        Emc2xKHz = PllM0KHz / ((++k) << 1);
+        if (Emc2xKHz < NvRmPrivGetSocClockLimits(
+            NvRmPrivModuleID_ExternalMemoryController)->MinKHz)
+            break;              // Abort sorting at minimum EMC frequency
+    }
+    // Check if match for boot configuration found
+    if (s_MemClocks.Index == NVRM_AP15_DFS_EMC_FREQ_STEPS)
+        s_Ap15EmcConfigSortedTable[0].Emc2xKHz = 0; // invalidate PLLM0 entry
+}
+
+static NvBool
+Ap15Emc2xClockSourceFind(
+    NvRmDeviceHandle hRmDevice,
+    NvRmFreqKHz MaxKHz,
+    NvRmFreqKHz DomainKHz,
+    NvRmFreqKHz* pCpuTargetKHz,
+    NvRmDfsSource* pDfsSource)
+{
+    NvU32 i;
+    NvBool FinalStep = NV_TRUE;
+    NV_ASSERT(DomainKHz <= MaxKHz);
+    pDfsSource->DividerSetting = 0; // no divider
+
+    // If PLLM0 entry in EMC frequeuncies table is invalid, EMC frequency
+    // will not be scaled; just fill in current EMC frequency
+    if (s_Ap15EmcConfigSortedTable[0].Emc2xKHz == 0)
+    {
+        pDfsSource->SourceId = NvRmClockSource_Invalid;
+        pDfsSource->SourceKHz = s_MemClocks.pEmcState->actual_freq;
+        pDfsSource->MinMv = NvRmVoltsMaximum; // no v-scaling in this case
+        return FinalStep;
+    }
+
+    // Only PLLM0 is used as EMC frequency source by DFS; its frequency is
+    // always within h/w limits
+    pDfsSource->SourceId = NvRmClockSource_PllM0;
+    NV_ASSERT(s_Ap15EmcConfigSortedTable[0].Emc2xKHz <= MaxKHz);
+
+    // Search sorted pre-defind EMC frequencies (divided down from PLLM0) for
+    // the entry above and closest to the traget that also has CPU limit above
+    // the CPU target. Use PLLM0 entry if not found.
+    for (i = NVRM_AP15_DFS_EMC_FREQ_STEPS; i > 0;)
+    {
+        i--;
+        if ((DomainKHz <= s_Ap15EmcConfigSortedTable[i].Emc2xKHz) &&
+            (*pCpuTargetKHz <= s_Ap15EmcConfigSortedTable[i].CpuLimitKHz))
+            break;
+    }
+
+    // Make sure the new entry is adjacent to the current (one step at a time)
+    if (i > (s_MemClocks.Index + 1))
+    {
+        i = s_MemClocks.Index + 1;
+        FinalStep = NV_FALSE;    // need more steps to reach target
+    }
+    else if ((i + 1) < s_MemClocks.Index)
+    {
+        i = s_MemClocks.Index - 1;
+        FinalStep = NV_FALSE;    // need more steps to reach target
+    }
+
+    // Record found EMC entry, and limit CPU target if necessary
+    pDfsSource->DividerSetting = i;
+    pDfsSource->SourceKHz = s_Ap15EmcConfigSortedTable[i].Emc2xKHz;
+    if (*pCpuTargetKHz > s_Ap15EmcConfigSortedTable[i].CpuLimitKHz)
+        *pCpuTargetKHz = s_Ap15EmcConfigSortedTable[i].CpuLimitKHz;
+    pDfsSource->MinMv = s_Ap15EmcConfigSortedTable[i].CoreVoltageMv;
+    return FinalStep;
+}
+
+static void
+Ap15Emc2xClockConfigure(
+    NvRmDeviceHandle hRmDevice,
+    NvRmFreqKHz MaxKHz,
+    NvRmFreqKHz* pDomainKHz,
+    const NvRmDfsSource* pDfsSource)
+{
+    NvU32 Index;
+    NvRmFreqKHz CpuFreq = NvRmPrivGetClockSourceFreq(NvRmClockSource_CpuBus);
+
+    // Always return the requested source frequency
+    *pDomainKHz = pDfsSource->SourceKHz;
+    NV_ASSERT(*pDomainKHz);
+
+    // If other than PLLM0 source is selected, EMC frequency is not scaled.
+    if (pDfsSource->SourceId != NvRmClockSource_PllM0)
+        return;
+
+    // Divider settings in EMC source descriptor is an index into the table of
+    // pre-defined EMC configurations in descending frequency order.
+    Index = pDfsSource->DividerSetting;
+    if (Index == s_MemClocks.Index)
+        return;     // do nothing new index is the same as current
+
+    // In case of EMC frequency increase:  check if EMC LL reservation should
+    // be enabled, reconfigure EMC, then MC (make sure MC never exceeds EMC2x)
+    // In case of EMC frequency decrease: reconfigure MC, then EMC (make sure
+    // MC never exceeds EMC2x) and check if EMC LL reservation can be disabled
+    if (Index < s_MemClocks.Index)
+    {
+        if (CpuFreq < (*pDomainKHz >> 1))
+        {
+            NVRM_AP15_EMCLL_RETRSV_ENABLE;
+        }
+        Ap15Emc2xClockSet(
+            hRmDevice, NV_TRUE, &s_Ap15EmcConfigSortedTable[Index]);
+        Ap15McClockSet(hRmDevice, &s_Ap15EmcConfigSortedTable[Index]);
+    }
+    else
+    {
+        Ap15McClockSet(hRmDevice, &s_Ap15EmcConfigSortedTable[Index]);
+        Ap15Emc2xClockSet(
+            hRmDevice, NV_FALSE, &s_Ap15EmcConfigSortedTable[Index]);
+
+        if (CpuFreq >= (*pDomainKHz >> 1))
+        {
+            NVRM_AP15_EMCLL_RETRSV_DISABLE;
+        }
+    }
+    s_MemClocks.Index = Index;
+}
+
+void
+NvRmPrivAp15FastClockConfig(NvRmDeviceHandle hRmDevice)
+{
+#if !NV_OAL
+    NvU32 divm1, divp2;
+    NvRmFreqKHz SclkKHz, CpuKHz, PllP2KHz, PllM1KHz;
+    NvRmFreqKHz FreqKHz = NvRmPrivGetClockSourceFreq(NvRmClockSource_PllM0);
+
+    // Set fastest EMC/MC configuration provided PLLM0 boot frequency matches
+    // one of the pre-defined configurations, i.e, it is the first entry in the
+    // sorted table
+    if (s_Ap15EmcConfigSortedTable[0].Emc2xKHz == FreqKHz)
+    {
+        for (;;)
+        {
+            Ap15Emc2xClockSet(
+                hRmDevice, NV_TRUE, &s_Ap15EmcConfigSortedTable[s_MemClocks.Index]);
+            Ap15McClockSet(hRmDevice, &s_Ap15EmcConfigSortedTable[s_MemClocks.Index]);
+            if (s_MemClocks.Index == 0)
+                break;
+            s_MemClocks.Index--;
+        }
+    }
+
+    // Set AVP/System Bus clock (now, with nominal core voltage it can be up
+    // to SoC maximum). First determine settings for PLLP and PLLM dividers
+    // to get maximum possible frequency on PLLP_OUT2 and PLLM_OUT1 outputs.
+    SclkKHz = NvRmPrivGetSocClockLimits(NvRmPrivModuleID_System)->MaxKHz;
+    NV_ASSERT(SclkKHz);
+
+    FreqKHz = NVRM_PLLP_FIXED_FREQ_KHZ;
+    PllP2KHz = SclkKHz;
+    divp2 = NvRmPrivFindFreqMaxBelow(
+        NvRmClockDivider_Fractional_2, FreqKHz, PllP2KHz, &PllP2KHz);
+
+    FreqKHz = NvRmPrivGetClockSourceFreq(NvRmClockSource_PllM0);
+    PllM1KHz = SclkKHz;
+    divm1 = NvRmPrivFindFreqMaxBelow(
+        NvRmClockDivider_Fractional_2, FreqKHz, PllM1KHz, &PllM1KHz);
+
+    // Now configure both dividers and select the output with highest frequency
+    // as a source for the system bus clock; reconfigure MIO as necessary
+    SclkKHz = NV_MAX(PllM1KHz, PllP2KHz); 
+    FreqKHz = NvRmPrivGetClockSourceFreq(NvRmClockSource_SystemBus);
+    if (FreqKHz < SclkKHz)
+    {
+        Ap15MioReconfigure(hRmDevice, SclkKHz);
+    }
+    NvRmPrivDividerSet(
+        hRmDevice,
+        NvRmPrivGetClockSourceHandle(NvRmClockSource_PllP2)->pInfo.pDivider,
+        divp2);
+    NvRmPrivDividerSet(
+        hRmDevice,
+        NvRmPrivGetClockSourceHandle(NvRmClockSource_PllM1)->pInfo.pDivider,
+        divm1);
+    if (SclkKHz == PllP2KHz)
+    {
+        NvRmPrivCoreClockSet(hRmDevice,
+            NvRmPrivGetClockSourceHandle(NvRmClockSource_SystemBus)->pInfo.pCore,
+            NvRmClockSource_PllP2, 0, 0);
+    }
+    else
+    {
+        NvRmPrivCoreClockSet(hRmDevice,
+            NvRmPrivGetClockSourceHandle(NvRmClockSource_SystemBus)->pInfo.pCore,
+            NvRmClockSource_PllM1, 0, 0);
+    }
+    if (FreqKHz >= SclkKHz)
+    {
+        Ap15MioReconfigure(hRmDevice, SclkKHz);
+    }
+    NvRmPrivBusClockInit(hRmDevice, SclkKHz);
+
+    // Set PLLC and CPU clock to SoC maximum - can be done now, when core
+    // voltage is guaranteed to be nominal, provided none of the display
+    // heads is already using PLLC as pixel clock source.
+    CpuKHz = NvRmPrivGetSocClockLimits(NvRmModuleID_Cpu)->MaxKHz;
+    FreqKHz = NvRmPrivGetClockSourceFreq(NvRmClockSource_PllC0);
+    if (CpuKHz != FreqKHz)
+    {
+        NvRmPrivBoostPllC(hRmDevice);
+    }
+    NvRmPrivCoreClockSet(hRmDevice,
+        NvRmPrivGetClockSourceHandle(NvRmClockSource_CpuBus)->pInfo.pCore,
+        NvRmClockSource_PllC0, 0, 0);
+#endif
+}
+
+void
+NvRmPrivAp15ClipCpuEmcHighLimits(
+    NvRmDeviceHandle hRmDevice,
+    NvRmFreqKHz* pCpuHighKHz,
+    NvRmFreqKHz* pEmcHighKHz)
+{
+#if !NV_OAL
+    NvU32 i;
+    NvRmFreqKHz EmcKHz;
+    NvRmFreqKHz MinKHz = NvRmPrivDfsGetMinKHz(NvRmDfsClockId_Emc);
+    NV_ASSERT(pEmcHighKHz && pCpuHighKHz);
+
+    // Nothing to do if no EMC scaling.
+    if (s_Ap15EmcConfigSortedTable[0].Emc2xKHz == 0)
+        return;
+
+    // Clip strategy: "throttling" - find the floor for EMC high limit
+    // (above domain minimum, of course)
+    if ((*pEmcHighKHz) < MinKHz)
+        *pEmcHighKHz = MinKHz;
+    for (i = 0; i < NVRM_AP15_DFS_EMC_FREQ_STEPS; i++)
+    {
+        EmcKHz = s_Ap15EmcConfigSortedTable[i].Emc2xKHz >> 1;
+        if (EmcKHz <= (*pEmcHighKHz))
+            break;
+    }
+    if ((i == NVRM_AP15_DFS_EMC_FREQ_STEPS) || (EmcKHz < MinKHz))
+    {
+        i--;
+        EmcKHz = s_Ap15EmcConfigSortedTable[i].Emc2xKHz >> 1;
+    }
+    *pEmcHighKHz = EmcKHz;
+
+    // Clip strategy: "throttling" - restrict CPU high limit by EMC
+    // configuration ((above domain minimum, of course)
+    if ((*pCpuHighKHz) > s_Ap15EmcConfigSortedTable[i].CpuLimitKHz)
+        (*pCpuHighKHz) = s_Ap15EmcConfigSortedTable[i].CpuLimitKHz;
+    if ((*pCpuHighKHz) < NvRmPrivDfsGetMinKHz(NvRmDfsClockId_Cpu))
+        *pCpuHighKHz = NvRmPrivDfsGetMinKHz(NvRmDfsClockId_Cpu);
+#endif
+}
+
+NvRmFreqKHz
+NvRmPrivAp15GetEmcSyncFreq(
+    NvRmDeviceHandle hRmDevice,
+    NvRmModuleID Module)
+{
+    NvRmFreqKHz FreqKHz = NvRmPrivGetClockSourceFreq(NvRmClockSource_PllM0);
+
+    switch (Module)
+    {
+        case NvRmModuleID_2D:
+        case NvRmModuleID_Epp:
+            // 2D/EPP frequency is dynamically synchronized with current EMC speed
+            // (high if EMC divisor 0, and low otherwise)
+            if (s_MemClocks.pEmcState && (s_MemClocks.pEmcState->Divider != 0))
+                FreqKHz = FreqKHz / NVRM_PLLM_2D_LOW_SPEED_RATIO;
+            else
+                FreqKHz = FreqKHz / NVRM_PLLM_2D_HIGH_SPEED_RATIO;
+            break;
+
+        case NvRmModuleID_GraphicsHost:
+            // Host frequency is static, synchronized with EMC range set by BCT
+            FreqKHz = FreqKHz / NVRM_PLLM_HOST_SPEED_RATIO;
+            break;
+
+        default:
+            NV_ASSERT(!"Invalid module for EMC synchronization");
+            FreqKHz = NvRmPrivGetSocClockLimits(Module)->MaxKHz;
+            break;
+    }
+    return FreqKHz;
+}
+
+/*****************************************************************************/
+
+static void
+Ap15SystemClockSourceFind(
+    NvRmDeviceHandle hRmDevice,
+    NvRmFreqKHz MaxKHz,
+    NvRmFreqKHz DomainKHz,
+    NvRmDfsSource* pDfsSource)
+{
+    NvU32 i;
+    NvRmFreqKHz SourceKHz;
+    NV_ASSERT(DomainKHz <= MaxKHz);
+    pDfsSource->DividerSetting = 0; // no divider
+
+    // 1st try oscillator
+    SourceKHz = NvRmPrivGetClockSourceFreq(NvRmClockSource_ClkM);
+    NV_ASSERT(SourceKHz <= MaxKHz);
+    if (DomainKHz <= SourceKHz)
+    {
+        pDfsSource->SourceId = NvRmClockSource_ClkM;
+        pDfsSource->SourceKHz = SourceKHz;
+        goto get_mv;
+    }
+
+    // 2nd choice - doubler
+    SourceKHz = NvRmPrivGetClockSourceFreq(NvRmClockSource_ClkD);
+    NV_ASSERT(SourceKHz <= MaxKHz);
+    if (DomainKHz <= SourceKHz)
+    {
+        pDfsSource->SourceId = NvRmClockSource_ClkD;
+        pDfsSource->SourceKHz = SourceKHz;
+        goto get_mv;
+    }
+
+    /*
+     * 3rd option - PLLP divider per policy specification. Find
+     * the policy entry with source frequency closest and above requested.
+     * If requested frequency exceeds all policy options within domain
+     * maximum limit, select the entry with the highest possible frequency.
+     */
+    for (i = 0; i < s_Ap15PllPSystemClockPolicyEntries; i++)
+    {
+        SourceKHz = s_Ap15PllPSystemClockPolicy[i].SourceKHz;
+        if (SourceKHz > MaxKHz)
+        {
+            NV_ASSERT(i);
+            i--;
+            break;
+        }
+        if (DomainKHz <= SourceKHz)
+        {
+            break;
+        }
+    }
+    if (i == s_Ap15PllPSystemClockPolicyEntries)
+    {
+        i--;    // last/highest source is the best we can do
+    }
+    pDfsSource->SourceId = s_Ap15PllPSystemClockPolicy[i].SourceId;
+    pDfsSource->SourceKHz = s_Ap15PllPSystemClockPolicy[i].SourceKHz;
+    pDfsSource->DividerSetting = s_Ap15PllPSystemClockPolicy[i].DividerSetting;
+
+    /*
+     * 4st and final option - PLLM divider fixed at maximum possible frequency
+     * during initialization. Select PLLP/PLLM divider according to the 
+     * following rule: select the divider with smaller frequency if it is equal
+     * or above the target frequency, otherwise select the divider with bigger
+     * output frequency.
+     */
+    SourceKHz = NvRmPrivGetClockSourceFreq(NvRmClockSource_PllM1);
+    NV_ASSERT(SourceKHz <= MaxKHz);
+    if (SourceKHz > pDfsSource->SourceKHz)
+    {
+        if (pDfsSource->SourceKHz >= DomainKHz)
+            goto get_mv;    // keep PLLP divider as a source
+    }
+    else // SourceKHz <= pDfsSource->SourceKHz
+    {
+        if (SourceKHz < DomainKHz)
+            goto get_mv;    // keep PLLP divider as a source
+    }
+    // Select PLLM_OUT1 divider as a source (considered as a fixed source -
+    // divider settings are ignored)
+    pDfsSource->SourceId = NvRmClockSource_PllM1;
+    pDfsSource->SourceKHz = SourceKHz;
+
+get_mv:
+    // Finally get operational voltage for found source
+    pDfsSource->MinMv = NvRmPrivModuleVscaleGetMV(
+        hRmDevice, NvRmPrivModuleID_System, pDfsSource->SourceKHz);
+}
+
+static void
+Ap15CpuClockSourceFind(
+    NvRmDeviceHandle hRmDevice,
+    NvRmFreqKHz MaxKHz,
+    NvRmFreqKHz DomainKHz,
+    NvRmDfsSource* pDfsSource)
+{
+    NvU32 i;
+    NvRmFreqKHz SourceKHz;
+    NV_ASSERT(DomainKHz <= MaxKHz);
+    pDfsSource->DividerSetting = 0; // no divider
+
+    // 1st try oscillator
+    SourceKHz = NvRmPrivGetClockSourceFreq(NvRmClockSource_ClkM);
+    NV_ASSERT(SourceKHz <= MaxKHz);
+    if (DomainKHz <= SourceKHz)
+    {
+        pDfsSource->SourceId = NvRmClockSource_ClkM;
+        pDfsSource->SourceKHz = SourceKHz;
+        goto get_mv;
+    }
+
+    // 2nd choice - doubler - no longer supported
+    // 3rd choice - PLLP divider per policy specification
+    SourceKHz =
+        s_Ap15PllPCpuClockPolicy[s_Ap15PllPCpuClockPolicyEntries-1].SourceKHz;
+    NV_ASSERT(SourceKHz <= MaxKHz);
+    if (DomainKHz <= SourceKHz)
+    {
+        // The requested frequency is within PLLP divider policy table, and all
+        // policy entries are within domain maximum limit. Then, find the entry
+        // with source frequency closest and above the requested.
+        for (i = 0; i < s_Ap15PllPCpuClockPolicyEntries; i++)
+        {
+            SourceKHz = s_Ap15PllPCpuClockPolicy[i].SourceKHz;
+            if (DomainKHz <= SourceKHz)
+                break;
+        }
+        if (s_Ap15PllPCpuClockPolicy[i].DividerSetting == 0)
+            pDfsSource->SourceId = NvRmClockSource_PllP0;   // Bypass 1:1 divider
+        else
+            pDfsSource->SourceId = s_Ap15PllPCpuClockPolicy[i].SourceId;
+        pDfsSource->SourceKHz = s_Ap15PllPCpuClockPolicy[i].SourceKHz;
+        pDfsSource->DividerSetting = s_Ap15PllPCpuClockPolicy[i].DividerSetting;
+        goto get_mv;
+    }
+
+    // 4th choice PLLM base output
+    SourceKHz = NvRmPrivGetClockSourceFreq(NvRmClockSource_PllM0);
+    NV_ASSERT(SourceKHz <= MaxKHz);
+    if (DomainKHz <= SourceKHz)
+    {
+        pDfsSource->SourceId = NvRmClockSource_PllM0;
+        pDfsSource->SourceKHz = SourceKHz;
+        goto get_mv;
+    }
+
+    // 5th choice PLLP base output (not used - covered by 3rd choice, case 1:1)
+    // 6th and final choice - PLLC base output at domain limit
+    pDfsSource->SourceId = NvRmClockSource_PllC0;
+    pDfsSource->SourceKHz = MaxKHz;
+
+get_mv:
+    // Finally get operational voltage for found source
+    pDfsSource->MinMv = NvRmPrivModuleVscaleGetMV(
+        hRmDevice, NvRmModuleID_Cpu, pDfsSource->SourceKHz);
+}
+
+static void
+Ap15SystemBusClockConfigure(
+    NvRmDeviceHandle hRmDevice,
+    NvRmFreqKHz MaxKHz,
+    NvRmFreqKHz* pDomainKHz,
+    const NvRmDfsSource* pDfsSource)
+{
+    NvRmClockSource SourceId = pDfsSource->SourceId;
+    const NvRmCoreClockInfo* pCinfo =
+        NvRmPrivGetClockSourceHandle(NvRmClockSource_SystemBus)->pInfo.pCore;
+
+    switch(SourceId)
+    {
+        case NvRmClockSource_PllP2:
+            // Reconfigure PLLP variable divider if it is used as a source
+            NvRmPrivDividerSet(hRmDevice,
+                NvRmPrivGetClockSourceHandle(SourceId)->pInfo.pDivider,
+                pDfsSource->DividerSetting);
+            // fall through
+        case NvRmClockSource_PllM1:
+        case NvRmClockSource_ClkD:
+        case NvRmClockSource_ClkM:
+            break;  // fixed sources - do nothing
+        default:
+            NV_ASSERT(!"Invalid source (per policy)");
+    }
+    NV_ASSERT_SUCCESS(NvRmPrivCoreClockConfigure(
+        hRmDevice, pCinfo, MaxKHz, pDomainKHz, &SourceId));
+}
+
+static void
+Ap15CpuBusClockConfigure(
+    NvRmDeviceHandle hRmDevice,
+    NvRmFreqKHz MaxKHz,
+    NvRmFreqKHz* pDomainKHz,
+    const NvRmDfsSource* pDfsSource)
+{
+    NvRmClockSource SourceId = pDfsSource->SourceId;
+    const NvRmCoreClockInfo* pCinfo =
+        NvRmPrivGetClockSourceHandle(NvRmClockSource_CpuBus)->pInfo.pCore;
+
+    switch(SourceId)
+    {
+        case NvRmClockSource_PllC0:
+            // DFS PLLC policy - configure PLLC if disabled; otherwise keep
+            // keep it as is (the latter means either DFS has already set it
+            // to domain limit, or PLLC is used as display pixel clock source)
+            if (NvRmPrivGetClockSourceFreq(NvRmClockSource_PllC0) <=
+                NvRmPrivGetClockSourceFreq(NvRmClockSource_ClkM))
+            {
+                NvRmFreqKHz TargetKHz = pDfsSource->SourceKHz;
+                NvRmPrivAp15PllConfigureSimple(
+                    hRmDevice, SourceId, MaxKHz, &TargetKHz);
+            }
+            break;
+        case NvRmClockSource_PllP4:
+            // Reconfigure PLLP variable divider if it is used as a source;
+            // If source frequency is going down, get EMC configuration is ready
+            if (pDfsSource->SourceKHz < NvRmPrivGetClockSourceFreq(SourceId))
+                NvRmPrivAp15SetEmcForCpuSrcSwitch(hRmDevice);
+            NvRmPrivDividerSet(hRmDevice,
+                NvRmPrivGetClockSourceHandle(SourceId)->pInfo.pDivider,
+                pDfsSource->DividerSetting);
+            // fall through
+        case NvRmClockSource_PllP0:
+        case NvRmClockSource_PllM0:
+        case NvRmClockSource_ClkD:
+        case NvRmClockSource_ClkM:
+            break;  // fixed sources - do nothing
+        default:
+            NV_ASSERT(!"Invalid source (per policy)");
+    }
+    NV_ASSERT_SUCCESS(NvRmPrivCoreClockConfigure(
+        hRmDevice, pCinfo, MaxKHz, pDomainKHz, &SourceId));
+}
+
+/*****************************************************************************/
+/* If time is specified in ns, and frequency in KHz, then cycles =
+ * (ns * KHz / 10^6) = (ns * (KHz * 2^20 / 10^6) / 2^20) = (ns * KiHz / 2^20),
+ * where KiHz = (KHz * 2^20 / 10^6) ~ (KHz * 4295 / 4096) with error < 0.001%.
+ */
+#define NVRM_TIME_TO_CYCLES(ns, KiHz) (((ns * KiHz) + (0x1 << 20)- 1) >> 20)
+
+#define NV_DRF_MAX_NUM(d,r,f,n) \
+    ((((n) <= NV_FIELD_MASK(d##_##r##_0_##f##_RANGE)) ? \
+      (n) : NV_FIELD_MASK(d##_##r##_0_##f##_RANGE)) << \
+     NV_FIELD_SHIFT(d##_##r##_0_##f##_RANGE))
+
+static void
+Ap15MioReconfigure(
+        NvRmDeviceHandle hRmDevice,
+        NvRmFreqKHz MioKHz)
+{
+    NvU32 reg, mask;
+    NvU32 MioKiHz = ((MioKHz * 4295) >> 12);
+    NvOdmAsynchMemConfig  MemConfig;
+    /*
+     * Reconfigure MIO timing when clock frequency changes. Check only Async
+     * Memory devices connected to CS1/MIO_B and CS3/MIO_A (CS0 is dedicated
+     * for NOR, we do not care after boot, and CS2 is dedicated to SDRAM with
+     * its own clock)
+     */
+    if (NvOdmQueryAsynchMemConfig(1, &MemConfig) == NV_TRUE)
+    {
+        reg = NV_REGR(hRmDevice, NvRmModuleID_Misc, 0, APB_MISC_PP_XMB_MIO_CFG_0);
+        mask =
+            NV_DRF_NUM(APB_MISC_PP, XMB_MIO_CFG, MIO_B_WR_DEAD_TIME, 0xFFFFFFFFUL) |
+            NV_DRF_NUM(APB_MISC_PP, XMB_MIO_CFG, MIO_B_WR_TIME, 0xFFFFFFFFUL) |
+            NV_DRF_NUM(APB_MISC_PP, XMB_MIO_CFG, MIO_B_RD_DEAD_TIME, 0xFFFFFFFFUL) |
+            NV_DRF_NUM(APB_MISC_PP, XMB_MIO_CFG, MIO_B_RD_TIME, 0xFFFFFFFFUL);
+        reg = (reg & (~mask)) |
+            NV_DRF_MAX_NUM(APB_MISC_PP, XMB_MIO_CFG, MIO_B_WR_DEAD_TIME,
+                NVRM_TIME_TO_CYCLES(MemConfig.WriteDeadTime, MioKiHz)) |
+            NV_DRF_MAX_NUM(APB_MISC_PP, XMB_MIO_CFG, MIO_B_WR_TIME,
+                NVRM_TIME_TO_CYCLES(MemConfig.WriteAccessTime, MioKiHz)) |
+            NV_DRF_MAX_NUM(APB_MISC_PP, XMB_MIO_CFG, MIO_B_RD_DEAD_TIME,
+                NVRM_TIME_TO_CYCLES(MemConfig.ReadDeadTime, MioKiHz)) |
+            NV_DRF_MAX_NUM(APB_MISC_PP, XMB_MIO_CFG, MIO_B_RD_TIME,
+                NVRM_TIME_TO_CYCLES(MemConfig.ReadAccessTime, MioKiHz));
+        NV_REGW(hRmDevice, NvRmModuleID_Misc, 0,  APB_MISC_PP_XMB_MIO_CFG_0, reg);
+    }
+    if (NvOdmQueryAsynchMemConfig(3, &MemConfig) == NV_TRUE)
+    {
+        reg = NV_REGR(hRmDevice, NvRmModuleID_Misc, 0, APB_MISC_PP_XMB_MIO_CFG_0);
+        mask =
+            NV_DRF_NUM(APB_MISC_PP, XMB_MIO_CFG, MIO_A_WR_DEAD_TIME, 0xFFFFFFFFUL) |
+            NV_DRF_NUM(APB_MISC_PP, XMB_MIO_CFG, MIO_A_WR_TIME, 0xFFFFFFFFUL) |
+            NV_DRF_NUM(APB_MISC_PP, XMB_MIO_CFG, MIO_A_RD_DEAD_TIME, 0xFFFFFFFFUL) |
+            NV_DRF_NUM(APB_MISC_PP, XMB_MIO_CFG, MIO_A_RD_TIME, 0xFFFFFFFFUL);
+        reg = (reg & (~mask)) |
+            NV_DRF_MAX_NUM(APB_MISC_PP, XMB_MIO_CFG, MIO_A_WR_DEAD_TIME,
+                NVRM_TIME_TO_CYCLES(MemConfig.WriteDeadTime, MioKiHz)) |
+            NV_DRF_MAX_NUM(APB_MISC_PP, XMB_MIO_CFG, MIO_A_WR_TIME,
+                NVRM_TIME_TO_CYCLES(MemConfig.WriteAccessTime, MioKiHz)) |
+            NV_DRF_MAX_NUM(APB_MISC_PP, XMB_MIO_CFG, MIO_A_RD_DEAD_TIME,
+                NVRM_TIME_TO_CYCLES(MemConfig.ReadDeadTime, MioKiHz)) |
+            NV_DRF_MAX_NUM(APB_MISC_PP, XMB_MIO_CFG, MIO_A_RD_TIME,
+                NVRM_TIME_TO_CYCLES(MemConfig.ReadAccessTime, MioKiHz));
+        NV_REGW(hRmDevice, NvRmModuleID_Misc, 0,  APB_MISC_PP_XMB_MIO_CFG_0, reg);
+    }
+}
+
+NvBool NvRmPrivAp15DfsClockConfigure(
+    NvRmDeviceHandle hRmDevice,
+    const NvRmDfsFrequencies* pMaxKHz,
+    NvRmDfsFrequencies* pDfsKHz)
+{
+    NvU32 i;
+    NvBool Status;
+    NvRmFreqKHz FreqKHz;
+    NvRmDfsSource CpuClockSource;
+    NvRmDfsSource SystemClockSource;
+    NvRmDfsSource Emc2xClockSource;
+    NvBool CpuKHzUp = pDfsKHz->Domains[NvRmDfsClockId_Cpu] >
+        NvRmPrivGetClockSourceFreq(NvRmClockSource_CpuBus);
+
+    NV_ASSERT(hRmDevice);
+    NV_ASSERT(pMaxKHz && pDfsKHz);
+
+    /*
+     * Adjust System bus core clock. It should be sufficient to supply AVP,
+     * and all bus clocks. Also make sure that AHB bus frequency is above
+     * the one requested for APB clock.
+     */
+    for (FreqKHz = 0, i = 1; i < NvRmDfsClockId_Num; i++)
+    {
+        if ((i != NvRmDfsClockId_Cpu) &&
+            (i != NvRmDfsClockId_Emc))
+        {
+            FreqKHz = (FreqKHz > pDfsKHz->Domains[i]) ?
+                            FreqKHz : pDfsKHz->Domains[i];
+        }
+    }
+    pDfsKHz->Domains[NvRmDfsClockId_System] = FreqKHz;
+
+#if LIMIT_SYS_TO_VDE_RATIO
+    if (pDfsKHz->Domains[NvRmDfsClockId_Vpipe] <
+        (FreqKHz >> (LIMIT_SYS_TO_VDE_RATIO - 1)))
+    {
+        pDfsKHz->Domains[NvRmDfsClockId_Vpipe] =
+            (FreqKHz >> (LIMIT_SYS_TO_VDE_RATIO - 1));
+    }
+#endif
+
+#if LIMIT_SYS_TO_AHB_APB_RATIOS
+    if (pDfsKHz->Domains[NvRmDfsClockId_Apb] < (FreqKHz >> 2))
+    {
+        pDfsKHz->Domains[NvRmDfsClockId_Apb] = (FreqKHz >> 2);
+    }
+    if (pDfsKHz->Domains[NvRmDfsClockId_Ahb] < (FreqKHz >> 1))
+    {
+        pDfsKHz->Domains[NvRmDfsClockId_Ahb] = (FreqKHz >> 1);
+    }
+#endif
+    if (pDfsKHz->Domains[NvRmDfsClockId_Ahb] <
+        pDfsKHz->Domains[NvRmDfsClockId_Apb])
+    {
+        pDfsKHz->Domains[NvRmDfsClockId_Ahb] =
+            pDfsKHz->Domains[NvRmDfsClockId_Apb];
+    }
+
+    // Find clock sources for CPU, System and Memory clocks. H/w requirement
+    // to increase memory clocks in steps, may limit CPU clock as well
+    Ap15SystemClockSourceFind(hRmDevice,
+        pMaxKHz->Domains[NvRmDfsClockId_System],
+        pDfsKHz->Domains[NvRmDfsClockId_System],
+        &SystemClockSource);
+    Status = Ap15Emc2xClockSourceFind(hRmDevice,
+        (pMaxKHz->Domains[NvRmDfsClockId_Emc] << 1),
+        (pDfsKHz->Domains[NvRmDfsClockId_Emc] << 1),
+        &pDfsKHz->Domains[NvRmDfsClockId_Cpu],
+        &Emc2xClockSource);
+    Ap15CpuClockSourceFind(hRmDevice,
+        pMaxKHz->Domains[NvRmDfsClockId_Cpu],
+        pDfsKHz->Domains[NvRmDfsClockId_Cpu],
+        &CpuClockSource);
+
+#if !NV_OAL
+    // Adjust core voltage for the new clock sources before actual change
+    NvRmPrivVoltageScale(NV_TRUE, CpuClockSource.MinMv,
+                         SystemClockSource.MinMv, Emc2xClockSource.MinMv);
+#endif
+
+    // Configure System bus and derived clocks. Note that APB is the only
+    // clock in system complex that may have different (lower) maximum
+    // limit - pass it explicitly to set function.
+    if (FreqKHz < NvRmPrivGetClockSourceFreq(NvRmClockSource_SystemBus))
+        FreqKHz = NvRmPrivGetClockSourceFreq(NvRmClockSource_SystemBus);
+    Ap15MioReconfigure(hRmDevice, FreqKHz); // MIO timing for max frequency
+    Ap15SystemBusClockConfigure(hRmDevice,
+        pMaxKHz->Domains[NvRmDfsClockId_System],
+        &pDfsKHz->Domains[NvRmDfsClockId_System],
+        &SystemClockSource);
+    pDfsKHz->Domains[NvRmDfsClockId_Avp] =
+        pDfsKHz->Domains[NvRmDfsClockId_System];        // no AVP clock skipping
+    NvRmPrivBusClockFreqSet(hRmDevice,
+        pDfsKHz->Domains[NvRmDfsClockId_System],
+        &pDfsKHz->Domains[NvRmDfsClockId_Vpipe],
+        &pDfsKHz->Domains[NvRmDfsClockId_Ahb],
+        &pDfsKHz->Domains[NvRmDfsClockId_Apb],
+        pMaxKHz->Domains[NvRmDfsClockId_Apb]);
+    Ap15MioReconfigure(hRmDevice, pDfsKHz->Domains[NvRmDfsClockId_Ahb]);
+
+    // Configure CPU core clock before Memory if CPU frequency goes down
+    if (!CpuKHzUp)
+    {
+        Ap15CpuBusClockConfigure(hRmDevice,
+            pMaxKHz->Domains[NvRmDfsClockId_Cpu],
+            &pDfsKHz->Domains[NvRmDfsClockId_Cpu],
+            &CpuClockSource);
+    }
+    // Configure Memory clocks and convert frequency to DFS EMC 1x domain
+    FreqKHz = pDfsKHz->Domains[NvRmDfsClockId_Emc] << 1;
+    Ap15Emc2xClockConfigure(hRmDevice,
+        (pMaxKHz->Domains[NvRmDfsClockId_Emc] << 1),
+        &FreqKHz, &Emc2xClockSource);
+    pDfsKHz->Domains[NvRmDfsClockId_Emc] = FreqKHz >> 1;
+    // Configure CPU core clock after Memory if CPU frequency goes up
+    if (CpuKHzUp)
+    {
+        Ap15CpuBusClockConfigure(hRmDevice,
+            pMaxKHz->Domains[NvRmDfsClockId_Cpu],
+            &pDfsKHz->Domains[NvRmDfsClockId_Cpu],
+            &CpuClockSource);
+    }
+
+#if !NV_OAL
+    // Adjust core voltage for the new clock sources after actual change
+    NvRmPrivVoltageScale(NV_FALSE, CpuClockSource.MinMv,
+                         SystemClockSource.MinMv, Emc2xClockSource.MinMv);
+#endif
+    return Status;
+}
+
+void
+NvRmPrivAp15DfsClockFreqGet(
+    NvRmDeviceHandle hRmDevice,
+    NvRmDfsFrequencies* pDfsKHz)
+{
+    NvRmFreqKHz SystemFreq;
+    const NvRmCoreClockInfo* pCinfo;
+    NV_ASSERT(hRmDevice && pDfsKHz);
+
+    // Get frequencies of the System core clock, AVP clock (the same as System
+    // - no clock skipping), AHB, APB, and V-pipe bus clock frequencies
+    pCinfo = NvRmPrivGetClockSourceHandle(NvRmClockSource_SystemBus)->pInfo.pCore;
+    SystemFreq = NvRmPrivCoreClockFreqGet(hRmDevice, pCinfo);
+    pDfsKHz->Domains[NvRmDfsClockId_System] = SystemFreq;
+    pDfsKHz->Domains[NvRmDfsClockId_Avp] = SystemFreq;
+
+    NvRmPrivBusClockFreqGet(
+        hRmDevice, SystemFreq,
+        &pDfsKHz->Domains[NvRmDfsClockId_Vpipe],
+        &pDfsKHz->Domains[NvRmDfsClockId_Ahb],
+        &pDfsKHz->Domains[NvRmDfsClockId_Apb]);
+
+    // Get CPU core clock frequencies
+    pCinfo = NvRmPrivGetClockSourceHandle(NvRmClockSource_CpuBus)->pInfo.pCore;
+    pDfsKHz->Domains[NvRmDfsClockId_Cpu] =
+        NvRmPrivCoreClockFreqGet(hRmDevice, pCinfo);
+
+    // Get EMC clock frequency (DFS monitors EMC 1x domain)
+    Ap15Emc2xFreqGet(hRmDevice);   // Get EMC2x clock state from h/w
+    pDfsKHz->Domains[NvRmDfsClockId_Emc] =
+        (s_MemClocks.pEmcState->actual_freq >> 1);
+}
+
+void
+NvRmPrivAp15DfsVscaleFreqGet(
+    NvRmDeviceHandle hRmDevice,
+    NvRmMilliVolts TargetMv,
+    NvRmDfsFrequencies* pDfsKHz)
+{
+    NvU32 i;
+    NvRmMilliVolts v;
+    NvRmFreqKHz Fa, Fb, f;
+    NvRmDfsSource DfsClockSource;
+    NvRmFreqKHz CpuMaxKHz = NvRmPrivGetSocClockLimits(NvRmModuleID_Cpu)->MaxKHz;
+    NvRmFreqKHz SysMaxKHz =
+        NvRmPrivGetSocClockLimits(NvRmPrivModuleID_System)->MaxKHz;
+    NV_ASSERT(hRmDevice && pDfsKHz);
+
+    // If PLLM0 entry in EMC scaling table is valid, search the table for
+    // the entry below and closest to the traget voltage. Otherwise, there
+    // is no EMC scaling - just return current EMC frequency.
+    pDfsKHz->Domains[NvRmDfsClockId_Emc] =
+        (s_MemClocks.pEmcState->actual_freq >> 1);
+    f = NvRmFreqMaximum;    // assume CPU is not throttled by EMC
+    if (s_Ap15EmcConfigSortedTable[0].Emc2xKHz != 0)
+    {
+        for (i = 0; i < (NVRM_AP15_DFS_EMC_FREQ_STEPS - 1); i++)
+        {
+            if ((s_Ap15EmcConfigSortedTable[i+1].Emc2xKHz == 0) ||
+                (s_Ap15EmcConfigSortedTable[i].CoreVoltageMv <= TargetMv))
+                break;  // exit if found entry or next entry is invalid 
+        }
+        pDfsKHz->Domains[NvRmDfsClockId_Emc] =
+            (s_Ap15EmcConfigSortedTable[i].Emc2xKHz >> 1);
+        f = s_Ap15EmcConfigSortedTable[i].CpuLimitKHz;  // throttle CPU
+    }
+
+    // Binary search for maximum CPU frequency, with source that can be used
+    // at target voltage or below
+    Fb = NV_MIN(CpuMaxKHz, f); 
+    Fa = NvRmPrivGetClockSourceFreq(NvRmClockSource_ClkM);
+    NV_ASSERT(Fa <= Fb);
+    while ((Fb - Fa) > 1000)    // 1MHz resolution
+    {
+        f = (Fa + Fb) >> 1;
+        Ap15CpuClockSourceFind(hRmDevice, CpuMaxKHz, f, &DfsClockSource);
+        v = DfsClockSource.MinMv;
+        if (v <= TargetMv)
+            Fa = f;
+        else
+            Fb = f;
+    }
+    pDfsKHz->Domains[NvRmDfsClockId_Cpu] = Fa;
+
+    // Binary search for maximum System/Avp frequency, with source that can be used
+    // at target voltage or below
+    Fb = SysMaxKHz; 
+    Fa = NvRmPrivGetClockSourceFreq(NvRmClockSource_ClkM);
+    NV_ASSERT(Fa <= Fb);
+    while ((Fb - Fa) > 1000)    // 1MHz resolution
+    {
+        f = (Fa + Fb) >> 1;
+        Ap15SystemClockSourceFind(hRmDevice, SysMaxKHz, f, &DfsClockSource);
+        v = DfsClockSource.MinMv;
+        if (v <= TargetMv)
+            Fa = f;
+        else
+            Fb = f;
+    }
+    pDfsKHz->Domains[NvRmDfsClockId_System] = Fa;
+    pDfsKHz->Domains[NvRmDfsClockId_Avp] = Fa;
+    pDfsKHz->Domains[NvRmDfsClockId_Ahb] = Fa;
+    pDfsKHz->Domains[NvRmDfsClockId_Apb] = Fa;
+    pDfsKHz->Domains[NvRmDfsClockId_Vpipe] = Fa;
+}
+
+/*****************************************************************************/
+
diff --git a/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_clock_misc.c b/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_clock_misc.c
new file mode 100644
index 000000000000..97835ad98399
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_clock_misc.c
@@ -0,0 +1,511 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include "nvcommon.h"
+#include "nvassert.h"
+#include "nvos.h"
+#include "nvrm_init.h"
+#include "nvrm_drf.h"
+#include "nvrm_hwintf.h"
+#include "nvrm_clocks.h"
+#include "nvrm_chiplib.h"
+#include "nvrm_hardware_access.h"
+#include "ap15rm_private.h"
+#include "ap15rm_clocks.h"
+#include "ap16/arapb_misc.h"
+#include "ap15/arahb_arbc.h"
+#include "ap15/armc.h"
+#include "ap15/aremc.h"
+#include "ap15/arfuse.h"
+#include "ap15/arclk_rst.h"
+
+
+// This list requires pre-sorted info in bond-out registers order and bond-out
+// register bit shift order (MSB-to-LSB).
+static const NvU32 s_Ap15BondOutTable[] =
+{
+    // BOND_OUT_L bits
+    NVRM_DEVICE_UNKNOWN,  // NV_DEVID_CPU
+    NVRM_DEVICE_UNKNOWN,
+    NVRM_DEVICE_UNKNOWN,
+    NVRM_MODULE_ID( NvRmModuleID_Ac97,                          0 ),
+    NVRM_MODULE_ID( NvRmModuleID_Rtc,                           0 ),
+    NVRM_MODULE_ID( NvRmModuleID_Timer,                         0 ),
+    NVRM_MODULE_ID( NvRmModuleID_Uart,                          0 ),
+    NVRM_MODULE_ID( NvRmModuleID_Uart,                          1 ),
+    NVRM_MODULE_ID( NvRmPrivModuleID_Gpio,                      0 ),
+    NVRM_MODULE_ID( NvRmModuleID_Sdio,                          1 ),
+    NVRM_MODULE_ID( NvRmModuleID_Spdif,                         0 ),
+    NVRM_MODULE_ID( NvRmModuleID_I2s,                           0 ),
+    NVRM_MODULE_ID( NvRmModuleID_I2c,                           0 ),
+    NVRM_MODULE_ID( NvRmModuleID_Nand,                          0 ),
+    NVRM_MODULE_ID( NvRmModuleID_Sdio,                          0 ),
+    NVRM_MODULE_ID( NvRmModuleID_Hsmmc,                         0 ),
+    NVRM_MODULE_ID( NvRmModuleID_Twc,                           0 ),
+    NVRM_MODULE_ID( NvRmModuleID_Pwm,                           0 ),
+    NVRM_MODULE_ID( NvRmModuleID_I2s,                           1 ),
+    NVRM_MODULE_ID( NvRmModuleID_Epp,                           0 ),
+    NVRM_MODULE_ID( NvRmModuleID_Vi,                            0 ),
+    NVRM_MODULE_ID( NvRmModuleID_2D,                            0 ),
+    NVRM_MODULE_ID( NvRmModuleID_Usb2Otg,                       0 ),
+    NVRM_MODULE_ID( NvRmModuleID_Isp,                           0 ),
+    NVRM_MODULE_ID( NvRmModuleID_3D,                            0 ),
+    NVRM_MODULE_ID( NvRmModuleID_Ide,                           0 ),
+    NVRM_MODULE_ID( NvRmModuleID_Display,                       1 ),
+    NVRM_MODULE_ID( NvRmModuleID_Display,                       0 ),
+    NVRM_MODULE_ID( NvRmModuleID_GraphicsHost,                  0 ),
+    NVRM_MODULE_ID( NvRmModuleID_Vcp,                           0 ),
+    NVRM_MODULE_ID( NvRmModuleID_CacheMemCtrl,                  0 ),
+    NVRM_DEVICE_UNKNOWN,    // NV_DEVID_COP_CACHE
+
+    // BOND_OUT_H bits
+    NVRM_MODULE_ID( NvRmPrivModuleID_MemoryController,          0 ),
+    NVRM_DEVICE_UNKNOWN,    // NV_DEVID_AHB_DMA
+    NVRM_MODULE_ID( NvRmPrivModuleID_ApbDma,                    0 ),
+    NVRM_DEVICE_UNKNOWN,
+    NVRM_MODULE_ID( NvRmModuleID_Kbc,                           0 ),
+    NVRM_MODULE_ID( NvRmModuleID_SysStatMonitor,                0 ),
+    NVRM_DEVICE_UNKNOWN,    // PMC
+    NVRM_MODULE_ID( NvRmModuleID_Fuse,                          0 ),
+    NVRM_MODULE_ID( NvRmModuleID_Slink,                         0 ),
+    NVRM_DEVICE_UNKNOWN,    // SBC1
+    NVRM_MODULE_ID( NvRmModuleID_Nor,                           0 ),
+    NVRM_MODULE_ID( NvRmModuleID_Spi,                           0 ),
+    NVRM_DEVICE_UNKNOWN,    // SBC2
+    NVRM_MODULE_ID( NvRmModuleID_Xio,                           0 ),
+    NVRM_DEVICE_UNKNOWN,    // SBC3
+    NVRM_MODULE_ID( NvRmModuleID_Dvc,                           0 ),
+    NVRM_MODULE_ID( NvRmModuleID_Dsi,                           0 ),
+    NVRM_MODULE_ID( NvRmModuleID_Tvo,                           0 ),
+    NVRM_MODULE_ID( NvRmModuleID_Mipi,                          0 ),
+    NVRM_MODULE_ID( NvRmModuleID_Hdmi,                          0 ),
+    NVRM_MODULE_ID( NvRmModuleID_Csi,                           0 ),
+    NVRM_DEVICE_UNKNOWN,    // TVDAC
+    NVRM_MODULE_ID( NvRmModuleID_I2c,                           1 ),
+    NVRM_MODULE_ID( NvRmModuleID_Uart,                          2 ),
+    NVRM_DEVICE_UNKNOWN,    // SPROM
+    NVRM_MODULE_ID( NvRmPrivModuleID_ExternalMemoryController,  0 ),
+    NVRM_DEVICE_UNKNOWN,
+    NVRM_DEVICE_UNKNOWN,
+    NVRM_MODULE_ID( NvRmModuleID_Mpe,                           0 ),
+    NVRM_MODULE_ID( NvRmModuleID_Vde,                           0 ),
+    NVRM_MODULE_ID( NvRmModuleID_BseA,                          0 ),
+    NVRM_DEVICE_UNKNOWN,    //BSEV
+};
+
+/**
+ * Enable HDCP and Macrovision
+ */
+static void
+NvRmPrivContentProtectionFuses( NvRmDeviceHandle hRm )
+{
+    NvU32 reg;
+    NvU32 clk_rst;
+
+    /* need to set FUSEWRDATA3_RESERVED_PRODUCTION__PRI_ALIAS to 0x3 and
+     * enable the bypass.
+     *
+     * bit 0: macrovision
+     * bit 1: hdcp
+     */
+
+#if NV_USE_FUSE_CLOCK_ENABLE
+    // Enable fuse clock
+    Ap15EnableModuleClock(hRm, NvRmModuleID_Fuse, NV_TRUE);
+#endif
+
+    clk_rst = NV_REGR( hRm, NvRmPrivModuleID_ClockAndReset, 0,
+        CLK_RST_CONTROLLER_MISC_CLK_ENB_0 );
+    clk_rst = NV_FLD_SET_DRF_NUM( CLK_RST_CONTROLLER, MISC_CLK_ENB,
+        CFG_ALL_VISIBLE, 1, clk_rst );
+    NV_REGW( hRm, NvRmPrivModuleID_ClockAndReset, 0,
+        CLK_RST_CONTROLLER_MISC_CLK_ENB_0, clk_rst );
+
+    reg = NV_DRF_NUM( FUSE, FUSEWRDATA3,
+        FUSEWRDATA_RESERVED_PRODUCTION__PRI_ALIAS_0, 0x3 );
+    NV_REGW( hRm, NvRmModuleID_Fuse, 0, FUSE_FUSEWRDATA3_0, reg );
+
+    reg = NV_DRF_DEF( FUSE, FUSEBYPASS, FUSEBYPASS_VAL, ENABLED );
+    NV_REGW( hRm, NvRmModuleID_Fuse, 0, FUSE_FUSEBYPASS_0, reg );
+
+    clk_rst = NV_FLD_SET_DRF_NUM( CLK_RST_CONTROLLER, MISC_CLK_ENB,
+        CFG_ALL_VISIBLE, 0, clk_rst );
+    NV_REGW( hRm, NvRmPrivModuleID_ClockAndReset, 0,
+        CLK_RST_CONTROLLER_MISC_CLK_ENB_0, clk_rst );
+
+#if NV_USE_FUSE_CLOCK_ENABLE
+    // Disable fuse clock
+    Ap15EnableModuleClock(hRm, NvRmModuleID_Fuse, NV_FALSE);
+#endif
+}
+
+#define NVRM_CONFIG_CLOCK(Module, SrcDef, DivNum) \
+do\
+{\
+    reg = NV_REGR(rm, NvRmPrivModuleID_ClockAndReset, 0, \
+                  CLK_RST_CONTROLLER_CLK_SOURCE_##Module##_0); \
+    if ((DivNum) > NV_DRF_VAL(CLK_RST_CONTROLLER, CLK_SOURCE_##Module, \
+                            Module##_CLK_DIVISOR, reg)) \
+    {\
+        reg = NV_FLD_SET_DRF_NUM(CLK_RST_CONTROLLER, CLK_SOURCE_##Module, \
+                                 Module##_CLK_DIVISOR, (DivNum), reg); \
+        NV_REGW(rm, NvRmPrivModuleID_ClockAndReset, 0, \
+                CLK_RST_CONTROLLER_CLK_SOURCE_##Module##_0, reg); \
+        NvOsWaitUS(NVRM_CLOCK_CHANGE_DELAY); \
+    }\
+    reg = NV_FLD_SET_DRF_DEF(CLK_RST_CONTROLLER, CLK_SOURCE_##Module, \
+                             Module##_CLK_SRC, SrcDef, reg); \
+    NV_REGW(rm, NvRmPrivModuleID_ClockAndReset, 0, \
+            CLK_RST_CONTROLLER_CLK_SOURCE_##Module##_0, reg); \
+    NvOsWaitUS(NVRM_CLOCK_CHANGE_DELAY); \
+    if ((DivNum) < NV_DRF_VAL(CLK_RST_CONTROLLER, CLK_SOURCE_##Module, \
+                            Module##_CLK_DIVISOR, reg))\
+    {\
+        reg = NV_FLD_SET_DRF_NUM(CLK_RST_CONTROLLER, CLK_SOURCE_##Module, \
+                                 Module##_CLK_DIVISOR, (DivNum), reg); \
+        NV_REGW(rm, NvRmPrivModuleID_ClockAndReset, 0, \
+                CLK_RST_CONTROLLER_CLK_SOURCE_##Module##_0, reg); \
+        NvOsWaitUS(NVRM_CLOCK_CHANGE_DELAY);\
+    }\
+} while(0)
+
+#define NVRM_SET_OSC_CLOCK(ClkModule, RstModule, H_L) \
+do\
+{\
+    if (RstOut##H_L & \
+        CLK_RST_CONTROLLER_RST_DEVICES_##H_L##_0_SWR_##RstModule##_RST_FIELD) \
+    {\
+        reg = NV_REGR(rm, NvRmPrivModuleID_ClockAndReset, 0, \
+                      CLK_RST_CONTROLLER_CLK_SOURCE_##ClkModule##_0); \
+        reg = NV_FLD_SET_DRF_DEF(CLK_RST_CONTROLLER, CLK_SOURCE_##ClkModule, \
+                                 ClkModule##_CLK_SRC, CLK_M, reg); \
+        NV_REGW(rm, NvRmPrivModuleID_ClockAndReset, 0, \
+                CLK_RST_CONTROLLER_CLK_SOURCE_##ClkModule##_0, reg); \
+    }\
+} while(0)
+
+/**
+ * brings the minimum modules out of reset.
+ */
+void
+NvRmPrivAp15BasicReset( NvRmDeviceHandle rm )
+{
+#if !NV_OAL
+    NvU32 reg, RstOutL, RstOutH, ClkOutL, ClkOutH;
+    ExecPlatform env;
+
+    if (NvRmIsSimulation())
+    {
+        /* the memory system can't be used until the mem_init_done bit has
+         * been set.  This is done by the bootrom for production systems.
+         */
+        reg = NV_REGR( rm, NvRmPrivModuleID_Ahb_Arb_Ctrl, 0,
+                       AHB_ARBITRATION_XBAR_CTRL_0 );
+        reg = NV_FLD_SET_DRF_DEF( AHB_ARBITRATION, XBAR_CTRL, MEM_INIT_DONE,
+                                  DONE, reg );
+        NV_REGW( rm, NvRmPrivModuleID_Ahb_Arb_Ctrl, 0,
+                 AHB_ARBITRATION_XBAR_CTRL_0, reg );
+    }
+
+    // FIXME: this takes the Big Hammer Approach.  Take everything out
+    // of reset and enable all of the clocks. Then keep enabled only boot
+    // clocks and graphics host.
+
+    // get boot module reset state
+    RstOutL = NV_REGR(rm, NvRmPrivModuleID_ClockAndReset, 0,
+                      CLK_RST_CONTROLLER_RST_DEVICES_L_0);
+    RstOutH = NV_REGR(rm, NvRmPrivModuleID_ClockAndReset, 0,
+                      CLK_RST_CONTROLLER_RST_DEVICES_H_0);
+
+    // save boot clock enable state
+    ClkOutL = NV_REGR(rm, NvRmPrivModuleID_ClockAndReset, 0,
+                      CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0);
+    ClkOutH = NV_REGR(rm, NvRmPrivModuleID_ClockAndReset, 0,
+                      CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0);
+
+    /* write clk_out_enb_l */
+    NV_REGW( rm, NvRmPrivModuleID_ClockAndReset, 0,
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0, 0xFFFFFFFF );
+
+    /* write clk_out_enb_h */
+    NV_REGW( rm, NvRmPrivModuleID_ClockAndReset, 0,
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0, 0xFFFFFFFF );
+
+    // For AP15 default clock source selection is out of range for many modules
+    // Just copnfigure clocks so that reset is propagated correctly
+    env = NvRmPrivGetExecPlatform(rm);
+    if (env == ExecPlatform_Soc)
+    {
+        /*
+         * For peripheral modules that are not taken from reset, yet,
+         * use oscillator as a safe clock
+         */
+        NVRM_SET_OSC_CLOCK(I2S1, I2S1, L);
+        NVRM_SET_OSC_CLOCK(I2S2, I2S2, L);
+
+        NVRM_SET_OSC_CLOCK(I2C1, I2C1, L);
+        NVRM_SET_OSC_CLOCK(I2C2, I2C2, H);
+        NVRM_SET_OSC_CLOCK(DVC_I2C, DVC_I2C, H);
+
+        NVRM_SET_OSC_CLOCK(PWM, PWM, L);
+        NVRM_SET_OSC_CLOCK(XIO, XIO, H);
+        NVRM_SET_OSC_CLOCK(TWC, TWC, L);
+        NVRM_SET_OSC_CLOCK(HSMMC, HSMMC, L);
+
+        NVRM_SET_OSC_CLOCK(VFIR, UARTB, L);
+        NVRM_SET_OSC_CLOCK(UARTA, UARTA, L);
+        NVRM_SET_OSC_CLOCK(UARTB, UARTB, L);
+        NVRM_SET_OSC_CLOCK(UARTC, UARTC, H);
+
+        NVRM_SET_OSC_CLOCK(NDFLASH, NDFLASH, L);
+        NVRM_SET_OSC_CLOCK(IDE, IDE, L);
+        NVRM_SET_OSC_CLOCK(MIPI, MIPI, H);
+        NVRM_SET_OSC_CLOCK(SDIO1, SDIO1, L);
+        NVRM_SET_OSC_CLOCK(SDIO2, SDIO2, L);
+
+        NVRM_SET_OSC_CLOCK(SPI1, SPI1, H);
+        NVRM_SET_OSC_CLOCK(SBC1, SBC1, H);
+        NVRM_SET_OSC_CLOCK(SBC2, SBC2, H);
+        NVRM_SET_OSC_CLOCK(SBC3, SBC3, H);
+
+        NVRM_SET_OSC_CLOCK(DISP1, DISP1, L);
+        NVRM_SET_OSC_CLOCK(DISP2, DISP2, L);
+        NVRM_SET_OSC_CLOCK(TVO, TVO, H);
+        NVRM_SET_OSC_CLOCK(CVE, TVO, H);
+        NVRM_SET_OSC_CLOCK(HDMI, HDMI, H);
+        NVRM_SET_OSC_CLOCK(TVDAC, TVDAC, H);
+
+        // Special case SPDIF (set OUT on OSC; IN on PLLP_OUT0/(1+10/2))
+        if (RstOutL & CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SPDIF_RST_FIELD)
+        {
+            reg = NV_DRF_DEF(CLK_RST_CONTROLLER, CLK_SOURCE_SPDIF,
+                             SPDIFOUT_CLK_SRC, CLK_M) |
+                  NV_DRF_DEF(CLK_RST_CONTROLLER, CLK_SOURCE_SPDIF,
+                             SPDIFIN_CLK_SRC, PLLP_OUT0) |
+                  NV_DRF_NUM(CLK_RST_CONTROLLER, CLK_SOURCE_SPDIF,
+                             SPDIFIN_CLK_DIVISOR, 10);
+            NV_REGW( rm, NvRmPrivModuleID_ClockAndReset, 0,
+                CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0, reg);
+        }
+
+        /*
+         * For graphic clocks use PLLM_OUT0 (max 400MHz) as a source, and set
+         * divider so that initial frequency is below maximum module limit
+         * (= PLLM_OUT0 / (1 + DIVIDER/2)
+         */
+        #define G_DIVIDER (2)
+        NVRM_CONFIG_CLOCK(HOST1X, PLLM_OUT0, G_DIVIDER);
+        NVRM_CONFIG_CLOCK(EPP, PLLM_OUT0, G_DIVIDER);
+        NVRM_CONFIG_CLOCK(G2D, PLLM_OUT0, G_DIVIDER);
+        NVRM_CONFIG_CLOCK(G3D, PLLM_OUT0, G_DIVIDER);
+        NVRM_CONFIG_CLOCK(MPE, PLLM_OUT0, G_DIVIDER);
+        #define VI_DIVIDER (4)
+        NVRM_CONFIG_CLOCK(VI, PLLM_OUT0, VI_DIVIDER);
+        NVRM_CONFIG_CLOCK(VI_SENSOR, PLLM_OUT0, VI_DIVIDER);
+
+        NvOsWaitUS(NVRM_RESET_DELAY);
+    }
+    // Make sure Host1x clock will be kept enabled
+    ClkOutL = NV_FLD_SET_DRF_DEF(CLK_RST_CONTROLLER, CLK_OUT_ENB_L,
+                                 CLK_ENB_HOST1X, ENABLE, ClkOutL);
+    // Make sure VDE, BSEV and BSEA clocks will be kept disabled
+    ClkOutH = NV_FLD_SET_DRF_DEF(CLK_RST_CONTROLLER, CLK_OUT_ENB_H,
+                                 CLK_ENB_VDE, DISABLE, ClkOutH);
+    ClkOutH = NV_FLD_SET_DRF_DEF(CLK_RST_CONTROLLER, CLK_OUT_ENB_H,
+                                 CLK_ENB_BSEV, DISABLE, ClkOutH);
+    ClkOutH = NV_FLD_SET_DRF_DEF(CLK_RST_CONTROLLER, CLK_OUT_ENB_H,
+                                 CLK_ENB_BSEA, DISABLE, ClkOutH);
+
+    /* write rst_devices_l */
+    NV_REGW( rm, NvRmPrivModuleID_ClockAndReset, 0,
+        CLK_RST_CONTROLLER_RST_DEVICES_L_0, 0 );
+
+    /* write rst_devies_h */
+    NV_REGW( rm, NvRmPrivModuleID_ClockAndReset, 0,
+        CLK_RST_CONTROLLER_RST_DEVICES_H_0, 0 );
+
+    // restore clock enable state (= disable those clocks that
+    // were disabled on boot)
+    NV_REGW( rm, NvRmPrivModuleID_ClockAndReset, 0,
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0, ClkOutL );
+    NV_REGW( rm, NvRmPrivModuleID_ClockAndReset, 0,
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0, ClkOutH );
+
+    /* enable hdcp and macrovision */
+    NvRmPrivContentProtectionFuses( rm );
+
+    // 10jun2008: jn turning this back on.  Still need to solve the QT
+    //            issue.
+    // FIXME:  On Quickturn and FPGA we are using normal sdram, not mobile
+    //         ram.  Need some way to determine if we have normal sdram
+    //         or mobile sdram. Actually these bits should be set by BCT.
+    reg = NV_REGR(rm, NvRmPrivModuleID_ExternalMemoryController, 0,
+        EMC_CFG_0);
+    reg = NV_FLD_SET_DRF_DEF(EMC, CFG, DRAM_CLKSTOP, ENABLED, reg);
+    reg = NV_FLD_SET_DRF_DEF(EMC, CFG, DRAM_ACPD, ACTIVE_POWERDOWN, reg);
+    NV_REGW( rm, NvRmPrivModuleID_ExternalMemoryController, 0,
+             EMC_CFG_0, reg);
+
+    // Enable stop clock to CPU, while it is halted
+    reg = NV_REGR(rm, NvRmPrivModuleID_ClockAndReset, 0,
+        CLK_RST_CONTROLLER_CLK_MASK_ARM_0);
+    reg = NV_FLD_SET_DRF_NUM(CLK_RST_CONTROLLER, CLK_MASK_ARM,
+        CLK_MASK_CPU_HALT, 1, reg );
+    NV_REGW(rm, NvRmPrivModuleID_ClockAndReset, 0,
+        CLK_RST_CONTROLLER_CLK_MASK_ARM_0, reg);
+
+    if (rm->ChipId.Id == 0x16)
+    {
+        NvU32 Reg = 0;
+        // If USB main clock source is not enabled then disable the clocks to USB0 and USB1
+        Reg = NV_REGR(rm, NvRmPrivModuleID_ClockAndReset, 0, CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0);
+        if (!NV_DRF_VAL(CLK_RST_CONTROLLER, CLK_OUT_ENB_L, CLK_ENB_USBD, Reg))
+        {
+            // Disable clocks for USB1 and USB2 controllers.Should be enabled on need basis.
+            Reg = NV_REGR(rm, NvRmModuleID_Misc, 0, APB_MISC_PP_MISC_USB_CLK_RST_CTL_0);
+            Reg = NV_FLD_SET_DRF_DEF(APB_MISC_PP,MISC_USB_CLK_RST_CTL, MISC_USB_CE, DISABLE, Reg);
+            Reg = NV_FLD_SET_DRF_DEF(APB_MISC_PP,MISC_USB_CLK_RST_CTL, MISC_USB2_CE, DISABLE, Reg);
+            NV_REGW(rm, NvRmModuleID_Misc, 0, APB_MISC_PP_MISC_USB_CLK_RST_CTL_0, Reg);
+        }
+    }
+
+#endif // !NV_OAL
+}
+
+static void
+NvRmPrivAp15GetBondOut( NvRmDeviceHandle hDevice,
+                        const NvU32      **pTable,
+                        NvU32            *bondOut )
+{
+    *pTable = s_Ap15BondOutTable;
+    bondOut[0] = NV_REGR(hDevice, NvRmPrivModuleID_ClockAndReset, 0,
+                                    CLK_RST_CONTROLLER_BOND_OUT_L_0);
+    bondOut[1] = NV_REGR(hDevice, NvRmPrivModuleID_ClockAndReset, 0,
+                                    CLK_RST_CONTROLLER_BOND_OUT_H_0);
+}
+
+
+#define NVRM_MAX_BOND_OUT_REG    3
+
+/*
+ * Check BondOut register to determine which module and/or module instance
+ * is not available.
+ */
+void
+NvRmPrivCheckBondOut( NvRmDeviceHandle hDevice )
+{
+    NvRmModuleTable     *mod_table = 0;
+    NvRmModule          *modules = 0;
+    NvRmModuleInstance  *instance = 0;
+    NvRmChipId          *id = 0;
+    NvU32               bondOut[NVRM_MAX_BOND_OUT_REG] = {0, 0, 0};
+    NvU32               j, i, k;
+    const NvU32         *table = NULL;
+    NvU8                *pb = NULL;
+    NvU8                val;
+
+    NV_ASSERT( hDevice );
+
+    id = NvRmPrivGetChipId( hDevice );
+    switch (id->Id)
+    {
+        case 0x15:
+        case 0x16:
+            NvRmPrivAp15GetBondOut(hDevice, &table, bondOut);
+            break;
+        case 0x20:
+            NvRmPrivAp20GetBondOut(hDevice, &table, bondOut);
+            break;
+        default:
+            return;     // no support
+    }
+
+    if ( !bondOut[0] && !bondOut[1] && !bondOut[2] )
+        return;
+
+    mod_table = NvRmPrivGetModuleTable( hDevice );
+    modules = mod_table->Modules;
+
+    for ( i = 0, j = 0; j < NVRM_MAX_BOND_OUT_REG; j++ )
+    {
+        if ( !bondOut[j] )
+        {
+            i += 32;        // skip full 32-bit
+            continue;
+        }
+        pb = (NvU8 *)&bondOut[j];
+        for ( k = 0; k < 4; k++ )
+        {
+            val = *pb++;
+            if ( !val )
+            {
+                i += 8;
+                continue;
+            }
+            for( ; ; )
+            {
+                if ( val & 1 )
+                {
+                    NvU32   moduleIdInst = table[i];
+                    if ( NVRM_DEVICE_UNKNOWN != moduleIdInst )
+                    {
+                        if ( NvSuccess == NvRmPrivGetModuleInstance(hDevice,
+                                                        moduleIdInst, &instance) )
+                        {
+                            /* Mark instance's DevIdx to invalid value -1.  if all
+                               instances for the module are invalid, mark the module
+                               itself INVALID.
+                               Keep instance->DeviceId to maintain instance ordering
+                               since we could be bonding out, say, UARTA but UARTB and
+                               UARTC still available. */
+                            NvRmModuleID moduleId =
+                                            NVRM_MODULE_ID_MODULE( moduleIdInst );
+                            instance->DevIdx = (NvU8)-1;
+                            if (0 == NvRmModuleGetNumInstances( hDevice, moduleId ))
+                                modules[moduleId].Index = NVRM_MODULE_INVALID;
+                        }
+                    }
+                }
+                val = val >> 1;     // Use ARM's clz?
+                if ( !val )
+                {
+                    i = (i + 8) & ~7;       // skip to next byte
+                    break;
+                }
+                i++;
+            }
+        }
+    }
+}
+
+/*****************************************************************************/
+
diff --git a/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_clocks.c b/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_clocks.c
new file mode 100644
index 000000000000..4154c83e3d1b
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_clocks.c
@@ -0,0 +1,931 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include "nvcommon.h"
+#include "nvassert.h"
+#include "nvrm_clocks.h"
+#include "nvrm_hwintf.h"
+#include "nvrm_module.h"
+#include "nvrm_drf.h"
+#include "ap15/aremc.h"
+#include "ap15/arclk_rst.h"
+#include "ap15/arapbpm.h"
+#include "ap16/arapb_misc.h"
+#include "ap15rm_clocks.h"
+#include "ap15rm_private.h"
+
+
+
+/*****************************************************************************/
+
+static void NvRmPrivWaitUS(
+    NvRmDeviceHandle hDevice,
+    NvU32 usec)
+{
+    NvU32 t, start;
+
+    start = NV_REGR(hDevice, NvRmModuleID_TimerUs, 0, 0);
+    for (;;)
+    {
+        t = NV_REGR(hDevice, NvRmModuleID_TimerUs, 0, 0);
+        if ( ((NvU32)(t - start)) >= usec )
+            break;
+    }
+}
+
+#define CLOCK_ENABLE( rm, offset, field, EnableState ) \
+    do { \
+        regaddr = (CLK_RST_CONTROLLER_##offset##_0); \
+        NvOsMutexLock((rm)->CarMutex); \
+        reg = NV_REGR((rm), NvRmPrivModuleID_ClockAndReset, 0, regaddr); \
+        reg = NV_FLD_SET_DRF_NUM(CLK_RST_CONTROLLER, offset, field, EnableState, reg); \
+        NV_REGW((rm), NvRmPrivModuleID_ClockAndReset, 0, regaddr, reg); \
+        NvOsMutexUnlock((rm)->CarMutex); \
+    } while( 0 )
+
+/*****************************************************************************/
+void
+Ap15EnableModuleClock(
+    NvRmDeviceHandle hDevice,
+    NvRmModuleID ModuleId,
+    ModuleClockState ClockState)
+{
+    // Extract module and instance from composite module id.
+    NvU32 Module   = NVRM_MODULE_ID_MODULE( ModuleId );
+    NvU32 Instance = NVRM_MODULE_ID_INSTANCE( ModuleId );
+    NvU32 reg;
+    NvU32 regaddr;
+
+    if (ClockState == ModuleClockState_Enable)
+    {
+        NvRmPrivConfigureClockSource(hDevice, ModuleId, NV_TRUE);
+    }
+
+    switch ( Module ) {
+        case NvRmModuleID_CacheMemCtrl:
+            NV_ASSERT( Instance < 2 );
+            if( Instance == 0 )
+            {
+                CLOCK_ENABLE( hDevice, CLK_OUT_ENB_L, CLK_ENB_CACHE1, ClockState );
+            }
+            else if( Instance == 1 )
+            {
+                CLOCK_ENABLE( hDevice, CLK_OUT_ENB_L, CLK_ENB_CACHE2, ClockState );
+            }
+            break;
+        case NvRmModuleID_Vcp:
+            NV_ASSERT( Instance == 0 );
+            CLOCK_ENABLE( hDevice, CLK_OUT_ENB_L, CLK_ENB_VCP, ClockState );
+            break;
+        case NvRmModuleID_GraphicsHost:
+            // FIXME: should this be allowed?
+            NV_ASSERT( Instance == 0 );
+            CLOCK_ENABLE( hDevice, CLK_OUT_ENB_L, CLK_ENB_HOST1X, ClockState );
+            break;
+        case NvRmModuleID_Display:
+            NV_ASSERT( Instance < 2 );
+            if( Instance == 0 )
+            {
+                CLOCK_ENABLE( hDevice, CLK_OUT_ENB_L, CLK_ENB_DISP1, ClockState );
+            }
+            else if( Instance == 1 )
+            {
+                CLOCK_ENABLE( hDevice, CLK_OUT_ENB_L, CLK_ENB_DISP2, ClockState );
+            }
+            break;
+        case NvRmModuleID_Ide:
+            NV_ASSERT( Instance == 0 );
+            CLOCK_ENABLE( hDevice, CLK_OUT_ENB_L, CLK_ENB_IDE, ClockState );
+            break;
+        case NvRmModuleID_3D:
+            NV_ASSERT( Instance == 0 );
+            CLOCK_ENABLE( hDevice, CLK_OUT_ENB_L, CLK_ENB_3D, ClockState );
+            break;
+        case NvRmModuleID_Isp:
+            NV_ASSERT( Instance == 0 );
+            CLOCK_ENABLE( hDevice, CLK_OUT_ENB_L, CLK_ENB_ISP, ClockState );
+            break;
+        case NvRmModuleID_Usb2Otg:
+            NV_ASSERT( Instance < 2 );
+            if ((hDevice->ChipId.Id == 0x16) && (ClockState == NV_FALSE))
+            {
+                NvU32 RegVal = 0;
+                // On AP16 USB clock source is shared for both USB controllers
+                // Disabling the main clock source will disable both controllers
+                // when disabling the clock make sure that both controllers are disabled.
+                RegVal = NV_REGR(hDevice, NvRmModuleID_Misc, 0, APB_MISC_PP_MISC_USB_CLK_RST_CTL_0);
+
+                if (!(NV_DRF_VAL(APB_MISC_PP, MISC_USB_CLK_RST_CTL, MISC_USB_CE, RegVal)) &&
+                    !(NV_DRF_VAL(APB_MISC_PP, MISC_USB_CLK_RST_CTL, MISC_USB2_CE, RegVal)) )
+                {
+                    /// Disable USBD clock for both the instances 0 and 1
+                    CLOCK_ENABLE( hDevice, CLK_OUT_ENB_L, CLK_ENB_USBD, ClockState );
+                }
+            }
+            else
+            {
+                /// Enable/Disable USBD clock 
+                CLOCK_ENABLE( hDevice, CLK_OUT_ENB_L, CLK_ENB_USBD, ClockState );
+            }
+            break;
+        case NvRmModuleID_2D:
+            NV_ASSERT( Instance == 0 );
+            CLOCK_ENABLE( hDevice, CLK_OUT_ENB_L, CLK_ENB_2D, ClockState );
+            break;
+        case NvRmModuleID_Epp:
+            NV_ASSERT( Instance == 0 );
+            CLOCK_ENABLE( hDevice, CLK_OUT_ENB_L, CLK_ENB_EPP, ClockState );
+            break;
+        case NvRmModuleID_Vi:
+            NV_ASSERT( Instance == 0 );
+            CLOCK_ENABLE( hDevice, CLK_OUT_ENB_L, CLK_ENB_VI, ClockState );
+            break;
+        case NvRmModuleID_I2s:
+            NV_ASSERT( Instance < 2 );
+            if( Instance == 0 )
+            {
+                CLOCK_ENABLE( hDevice, CLK_OUT_ENB_L, CLK_ENB_I2S1, ClockState );
+            }
+            else if( Instance == 1 )
+            {
+                CLOCK_ENABLE( hDevice, CLK_OUT_ENB_L, CLK_ENB_I2S2, ClockState );
+            }
+            break;
+        case NvRmModuleID_Hsmmc:
+            NV_ASSERT( Instance == 0 );
+            CLOCK_ENABLE( hDevice, CLK_OUT_ENB_L, CLK_ENB_HSMMC, ClockState );
+            break;
+        case NvRmModuleID_Twc:
+            NV_ASSERT( Instance == 0 );
+            CLOCK_ENABLE( hDevice, CLK_OUT_ENB_L, CLK_ENB_TWC, ClockState );
+            break;
+        case NvRmModuleID_Pwm:
+            NV_ASSERT( Instance == 0 );
+            CLOCK_ENABLE( hDevice, CLK_OUT_ENB_L, CLK_ENB_PWM, ClockState );
+            break;
+        case NvRmModuleID_Sdio:
+            NV_ASSERT( Instance < 2 );
+            if( Instance == 0 )
+            {
+                CLOCK_ENABLE( hDevice, CLK_OUT_ENB_L, CLK_ENB_SDIO1, ClockState );
+            }
+            else if( Instance == 1 )
+            {
+                CLOCK_ENABLE( hDevice, CLK_OUT_ENB_L, CLK_ENB_SDIO2, ClockState );
+            }
+            break;
+        case NvRmModuleID_Spdif:
+            NV_ASSERT( Instance < 1 );
+            CLOCK_ENABLE( hDevice, CLK_OUT_ENB_L, CLK_ENB_SPDIF, ClockState );
+            break;
+        case NvRmModuleID_Nand:
+            NV_ASSERT( Instance == 0 );
+            CLOCK_ENABLE( hDevice, CLK_OUT_ENB_L, CLK_ENB_NDFLASH, ClockState );
+            break;
+        case NvRmModuleID_I2c:
+            NV_ASSERT( Instance < 2 );
+            if( Instance == 0 )
+            {
+                CLOCK_ENABLE( hDevice, CLK_OUT_ENB_L, CLK_ENB_I2C1, ClockState );
+            }
+            else if( Instance == 1 )
+            {
+                CLOCK_ENABLE( hDevice, CLK_OUT_ENB_H, CLK_ENB_I2C2, ClockState );
+            }
+            break;
+        case NvRmPrivModuleID_Gpio:
+            NV_ASSERT( Instance == 0 );
+            CLOCK_ENABLE( hDevice, CLK_OUT_ENB_L, CLK_ENB_GPIO, ClockState );
+            break;
+        case NvRmModuleID_Uart:
+            NV_ASSERT( Instance < 3 );
+            if( Instance == 0 )
+            {
+                CLOCK_ENABLE( hDevice, CLK_OUT_ENB_L, CLK_ENB_UARTA, ClockState );
+            }
+            else if( Instance == 1 )
+            {
+                CLOCK_ENABLE( hDevice, CLK_OUT_ENB_L, CLK_ENB_UARTB, ClockState );
+            }
+            else if ( Instance == 2)
+            {
+                CLOCK_ENABLE( hDevice, CLK_OUT_ENB_H, CLK_ENB_UARTC, ClockState );
+            }
+            break;
+        case NvRmModuleID_Vfir:
+            // Same as UARTB
+            NV_ASSERT( Instance == 0 );
+            CLOCK_ENABLE( hDevice, CLK_OUT_ENB_L, CLK_ENB_UARTB, ClockState );
+            break;
+        case NvRmModuleID_Ac97:
+            NV_ASSERT( Instance == 0 );
+            CLOCK_ENABLE( hDevice, CLK_OUT_ENB_L, CLK_ENB_AC97, ClockState );
+            break;
+        case NvRmModuleID_Rtc:
+            NV_ASSERT( Instance == 0 );
+            CLOCK_ENABLE( hDevice, CLK_OUT_ENB_L, CLK_ENB_RTC, ClockState );
+            break;
+        case NvRmModuleID_Timer:
+            NV_ASSERT( Instance == 0 );
+            CLOCK_ENABLE( hDevice, CLK_OUT_ENB_L, CLK_ENB_TMR, ClockState );
+            break;
+        case NvRmModuleID_BseA:
+            NV_ASSERT( Instance == 0 );
+            CLOCK_ENABLE( hDevice, CLK_OUT_ENB_H, CLK_ENB_BSEA, ClockState );
+            break;
+        case NvRmModuleID_Vde:
+            NV_ASSERT( Instance == 0 );
+            CLOCK_ENABLE( hDevice, CLK_OUT_ENB_H, CLK_ENB_VDE, ClockState );
+            CLOCK_ENABLE( hDevice, CLK_OUT_ENB_H, CLK_ENB_BSEV, ClockState );
+            break;
+        case NvRmModuleID_Mpe:
+            NV_ASSERT( Instance == 0 );
+            CLOCK_ENABLE( hDevice, CLK_OUT_ENB_H, CLK_ENB_MPE, ClockState );
+            break;
+        case NvRmModuleID_Tvo:
+            NV_ASSERT( Instance == 0 );
+            CLOCK_ENABLE( hDevice, CLK_OUT_ENB_H, CLK_ENB_TVO, ClockState );
+            CLOCK_ENABLE( hDevice, CLK_OUT_ENB_H, CLK_ENB_TVDAC, ClockState );
+            break;
+        case NvRmModuleID_Csi:
+            NV_ASSERT( Instance == 0 );
+            CLOCK_ENABLE( hDevice, CLK_OUT_ENB_H, CLK_ENB_CSI, ClockState );
+            break;
+        case NvRmModuleID_Hdmi:
+            NV_ASSERT( Instance == 0 );
+            CLOCK_ENABLE( hDevice, CLK_OUT_ENB_H, CLK_ENB_HDMI, ClockState );
+            break;
+        case NvRmModuleID_Mipi:
+            NV_ASSERT( Instance == 0 );
+            CLOCK_ENABLE( hDevice, CLK_OUT_ENB_H, CLK_ENB_MIPI, ClockState );
+            break;
+        case NvRmModuleID_Dsi:
+            NV_ASSERT( Instance == 0 );
+            CLOCK_ENABLE( hDevice, CLK_OUT_ENB_H, CLK_ENB_DSI, ClockState );
+            break;
+        case NvRmModuleID_Xio:
+            NV_ASSERT( Instance == 0 );
+            CLOCK_ENABLE( hDevice, CLK_OUT_ENB_H, CLK_ENB_XIO, ClockState );
+            break;
+        case NvRmModuleID_Spi:
+            NV_ASSERT( Instance == 0 );
+            CLOCK_ENABLE( hDevice, CLK_OUT_ENB_H, CLK_ENB_SPI1, ClockState );
+            break;
+        case NvRmModuleID_Fuse:
+            NV_ASSERT( Instance == 0 );
+            CLOCK_ENABLE( hDevice, CLK_OUT_ENB_H, CLK_ENB_FUSE, ClockState );
+            break;
+        case NvRmModuleID_Slink:
+            // Supporting only the slink controller.
+            NV_ASSERT( Instance < 3 );
+            if( Instance == 0 )
+            {
+                CLOCK_ENABLE( hDevice, CLK_OUT_ENB_H, CLK_ENB_SBC1, ClockState );
+            }
+            else if( Instance == 1 )
+            {
+                CLOCK_ENABLE( hDevice, CLK_OUT_ENB_H, CLK_ENB_SBC2, ClockState );
+            }
+            else if ( Instance == 2)
+            {
+                CLOCK_ENABLE( hDevice, CLK_OUT_ENB_H, CLK_ENB_SBC3, ClockState );
+            }
+            break;
+        case NvRmModuleID_Dvc:
+            NV_ASSERT( Instance == 0 );
+            CLOCK_ENABLE( hDevice, CLK_OUT_ENB_H, CLK_ENB_DVC_I2C, ClockState );
+            break;
+        case NvRmModuleID_Pmif:
+            NV_ASSERT( Instance == 0 );
+            // PMC clock must not be disabled
+            if (ClockState == ModuleClockState_Enable)
+                CLOCK_ENABLE( hDevice, CLK_OUT_ENB_H, CLK_ENB_PMC, ClockState );
+            break;
+        case NvRmModuleID_SysStatMonitor:
+            NV_ASSERT( Instance == 0 );
+            CLOCK_ENABLE( hDevice, CLK_OUT_ENB_H, CLK_ENB_STAT_MON, ClockState );
+            break;
+        case NvRmModuleID_Kbc:
+            NV_ASSERT( Instance == 0 );
+            CLOCK_ENABLE( hDevice, CLK_OUT_ENB_H, CLK_ENB_KBC, ClockState );
+            break;
+        case NvRmPrivModuleID_ApbDma:
+            NV_ASSERT( Instance == 0 );
+            CLOCK_ENABLE( hDevice, CLK_OUT_ENB_H, CLK_ENB_APBDMA, ClockState );
+            break;
+        case NvRmPrivModuleID_MemoryController:
+            // FIXME: should this be allowed?
+            NV_ASSERT( Instance == 0 );
+            CLOCK_ENABLE( hDevice, CLK_OUT_ENB_H, CLK_ENB_MEM, ClockState );
+            break;
+        case NvRmPrivModuleID_ExternalMemoryController:
+            // FIXME: should this be allowed?
+            NV_ASSERT( Instance == 0 );
+            CLOCK_ENABLE( hDevice, CLK_OUT_ENB_H, CLK_ENB_EMC, ClockState );
+            CLOCK_ENABLE( hDevice, CLK_SOURCE_EMC, EMC_2X_CLK_ENB, ClockState );
+            CLOCK_ENABLE( hDevice, CLK_SOURCE_EMC, EMC_1X_CLK_ENB, ClockState );
+            break;
+        case NvRmModuleID_Cpu:
+            // FIXME: should this be allowed?
+            NV_ASSERT( Instance == 0 );
+            CLOCK_ENABLE( hDevice, CLK_OUT_ENB_L, CLK_ENB_CPU, ClockState );
+            break;
+        default:
+            NV_ASSERT(!" Unknown NvRmModuleID passed to Ap15EnableModuleClock(). ");
+    }
+
+    if (ClockState == ModuleClockState_Disable)
+    {
+        NvRmPrivConfigureClockSource(hDevice, ModuleId, NV_FALSE);
+    }
+}
+
+void
+Ap15EnableTvDacClock(
+    NvRmDeviceHandle hDevice,
+    ModuleClockState ClockState)
+{
+    NvU32 reg;
+    NvU32 regaddr;
+
+    CLOCK_ENABLE( hDevice, CLK_OUT_ENB_H, CLK_ENB_TVDAC, ClockState );
+}
+
+/*****************************************************************************/
+
+    // Note that VDE has different reset sequence requirement
+    // FIMXE: NV blocks - hot reset issues
+    #define RESET( rm, offset, field, delay ) \
+        do { \
+             regaddr = (CLK_RST_CONTROLLER_##offset##_0); \
+            NvOsMutexLock((rm)->CarMutex); \
+            reg = NV_REGR((rm), NvRmPrivModuleID_ClockAndReset, 0, regaddr); \
+            reg = NV_FLD_SET_DRF_NUM( \
+                CLK_RST_CONTROLLER, offset, field, 1, reg); \
+            NV_REGW((rm), NvRmPrivModuleID_ClockAndReset, 0, regaddr, reg); \
+            if (Hold) \
+            {\
+                NvOsMutexUnlock((rm)->CarMutex); \
+                break; \
+            }\
+            NvRmPrivWaitUS( (rm), (delay) ); \
+            reg = NV_FLD_SET_DRF_NUM( \
+                CLK_RST_CONTROLLER, offset, field, 0, reg); \
+            NV_REGW((rm), NvRmPrivModuleID_ClockAndReset, 0, regaddr, reg); \
+            NvOsMutexUnlock((rm)->CarMutex); \
+        } while( 0 )
+
+// KBC reset is available in the pmc control register.
+static void RESET_KBC(NvRmDeviceHandle rm, NvU32 delay, NvBool Hold)
+{
+    NvU32 reg;
+    NvU32 regaddr;
+
+    regaddr = (APBDEV_PMC_CNTRL_0);
+    NvOsMutexLock((rm)->CarMutex);
+    reg = NV_REGR((rm), NvRmModuleID_Pmif, 0, regaddr);
+    reg = NV_FLD_SET_DRF_DEF(APBDEV_PMC, CNTRL, KBC_RST, ENABLE, reg);
+    NV_REGW((rm), NvRmModuleID_Pmif, 0, regaddr, reg);
+    if (Hold)
+    {
+        NvOsMutexUnlock((rm)->CarMutex);
+        return;
+    }
+    NvRmPrivWaitUS( (rm), (delay) );
+    reg = NV_FLD_SET_DRF_DEF(APBDEV_PMC, CNTRL, KBC_RST, DISABLE, reg);
+    NV_REGW((rm), NvRmModuleID_Pmif, 0, regaddr, reg);
+    NvOsMutexUnlock((rm)->CarMutex);
+}
+        
+
+// Use PMC control to reset the entire SoC. Just wait forever after reset is
+// issued - h/w would auto-clear it and restart SoC
+static void RESET_SOC(NvRmDeviceHandle rm)
+{
+    NvU32 reg;
+    NvU32 regaddr;
+
+    volatile NvBool b = NV_TRUE;
+    regaddr = (APBDEV_PMC_CNTRL_0);
+    reg = NV_REGR((rm), NvRmModuleID_Pmif, 0, regaddr);
+    reg = NV_FLD_SET_DRF_DEF(APBDEV_PMC, CNTRL, MAIN_RST, ENABLE, reg);
+    NV_REGW((rm), NvRmModuleID_Pmif, 0, regaddr, reg);
+    while (b) { ; }
+}
+
+
+void AP15ModuleReset(
+    NvRmDeviceHandle hDevice,
+    NvRmModuleID ModuleId,
+    NvBool Hold)
+{
+    // Extract module and instance from composite module id.
+    NvU32 Module   = NVRM_MODULE_ID_MODULE( ModuleId );
+    NvU32 Instance = NVRM_MODULE_ID_INSTANCE( ModuleId );
+    NvU32 reg;
+    NvU32 regaddr;
+
+    switch( Module ) {
+    case NvRmPrivModuleID_MemoryController:
+        // FIXME: should this be allowed?
+        NV_ASSERT( Instance == 0 );
+        RESET( hDevice, RST_DEVICES_H, SWR_MEM_RST, NVRM_RESET_DELAY );
+        break;
+    case NvRmModuleID_Kbc:
+        NV_ASSERT( Instance == 0 );
+        RESET_KBC(hDevice, NVRM_RESET_DELAY, Hold);
+        break;
+    case NvRmModuleID_SysStatMonitor:
+        NV_ASSERT( Instance == 0 );
+        RESET( hDevice, RST_DEVICES_H, SWR_STAT_MON_RST, NVRM_RESET_DELAY );
+        break;
+    case NvRmModuleID_Pmif:
+        NV_ASSERT( Instance == 0 );
+        NV_ASSERT(!"PMC reset is not allowed, and does nothing on AP15");
+        // RESET( hDevice, RST_DEVICES_H, SWR_PMC_RST, NVRM_RESET_DELAY );
+        break;
+    case NvRmModuleID_Fuse:
+        NV_ASSERT( Instance == 0 );
+        RESET( hDevice, RST_DEVICES_H, SWR_FUSE_RST, NVRM_RESET_DELAY );
+        break;
+    case NvRmModuleID_Slink:
+        // Supporting only the slink controller.
+        NV_ASSERT( Instance < 3 );
+        if( Instance == 0 )
+        {
+            RESET( hDevice, RST_DEVICES_H, SWR_SBC1_RST, NVRM_RESET_DELAY );
+        }
+        else if( Instance == 1 )
+        {
+            RESET( hDevice, RST_DEVICES_H, SWR_SBC2_RST, NVRM_RESET_DELAY );
+        }
+        else if ( Instance == 2)
+        {
+            RESET( hDevice, RST_DEVICES_H, SWR_SBC3_RST, NVRM_RESET_DELAY );
+        }
+        break;
+    case NvRmModuleID_Spi:
+        NV_ASSERT( Instance == 0 );
+        RESET( hDevice, RST_DEVICES_H, SWR_SPI1_RST, NVRM_RESET_DELAY );
+        break;
+    case NvRmModuleID_Xio:
+        NV_ASSERT( Instance == 0 );
+        RESET( hDevice, RST_DEVICES_H, SWR_XIO_RST, NVRM_RESET_DELAY );
+        break;
+    case NvRmModuleID_Dvc:
+        NV_ASSERT( Instance == 0 );
+        RESET( hDevice, RST_DEVICES_H, SWR_DVC_I2C_RST, NVRM_RESET_DELAY );
+        break;
+    case NvRmModuleID_Dsi:
+        NV_ASSERT( Instance == 0 );
+        RESET( hDevice, RST_DEVICES_H, SWR_DSI_RST, NVRM_RESET_DELAY );
+        break;
+    case NvRmModuleID_Tvo:
+        NV_ASSERT( Instance == 0 );
+        RESET( hDevice, RST_DEVICES_H, SWR_TVO_RST, NVRM_RESET_DELAY );
+        RESET( hDevice, RST_DEVICES_H, SWR_TVDAC_RST, NVRM_RESET_DELAY );
+        break;
+    case NvRmModuleID_Mipi:
+        NV_ASSERT( Instance == 0 );
+        RESET( hDevice, RST_DEVICES_H, SWR_MIPI_RST, NVRM_RESET_DELAY );
+        break;
+    case NvRmModuleID_Hdmi:
+        NV_ASSERT( Instance == 0 );
+        RESET( hDevice, RST_DEVICES_H, SWR_HDMI_RST, NVRM_RESET_DELAY );
+        break;
+    case NvRmModuleID_Csi:
+        NV_ASSERT( Instance == 0 );
+        RESET( hDevice, RST_DEVICES_H, SWR_CSI_RST, NVRM_RESET_DELAY );
+        break;
+    case NvRmModuleID_I2c:
+        NV_ASSERT( Instance < 2 );
+        if( Instance == 0 )
+        {
+            RESET( hDevice, RST_DEVICES_L, SWR_I2C1_RST, NVRM_RESET_DELAY );
+        }
+        else if( Instance == 1 )
+        {
+            RESET( hDevice, RST_DEVICES_H, SWR_I2C2_RST, NVRM_RESET_DELAY );
+        }
+        break;
+    case NvRmModuleID_Mpe:
+        NV_ASSERT( Instance == 0 );
+        RESET( hDevice, RST_DEVICES_H, SWR_MPE_RST, NVRM_RESET_DELAY );
+        break;
+    case NvRmModuleID_Vde:
+        NV_ASSERT( Instance == 0 );
+        {
+            NvU32 reg;
+            NvOsMutexLock(hDevice->CarMutex);
+            reg = NV_REGR(hDevice, NvRmPrivModuleID_ClockAndReset, 0,
+                            CLK_RST_CONTROLLER_RST_DEVICES_H_0);
+            reg = NV_FLD_SET_DRF_NUM(CLK_RST_CONTROLLER, RST_DEVICES_H,
+                            SWR_VDE_RST, 1, reg);
+            NV_REGW(hDevice, NvRmPrivModuleID_ClockAndReset, 0,
+                            CLK_RST_CONTROLLER_RST_DEVICES_H_0, reg);
+            reg = NV_FLD_SET_DRF_NUM(CLK_RST_CONTROLLER, RST_DEVICES_H,
+                            SWR_BSEV_RST, 1, reg);
+            NV_REGW(hDevice, NvRmPrivModuleID_ClockAndReset, 0,
+                            CLK_RST_CONTROLLER_RST_DEVICES_H_0, reg);
+            if (Hold)
+            {
+                NvOsMutexUnlock(hDevice->CarMutex);
+                break;
+            }
+            NvRmPrivWaitUS( hDevice, NVRM_RESET_DELAY );
+            reg = NV_FLD_SET_DRF_NUM(CLK_RST_CONTROLLER, RST_DEVICES_H,
+                            SWR_BSEV_RST, 0, reg);
+            NV_REGW(hDevice, NvRmPrivModuleID_ClockAndReset, 0,
+                            CLK_RST_CONTROLLER_RST_DEVICES_H_0, reg);
+            reg = NV_FLD_SET_DRF_NUM(CLK_RST_CONTROLLER, RST_DEVICES_H,
+                            SWR_VDE_RST, 0, reg);
+            NV_REGW(hDevice, NvRmPrivModuleID_ClockAndReset, 0,
+                            CLK_RST_CONTROLLER_RST_DEVICES_H_0, reg);
+            NvOsMutexUnlock(hDevice->CarMutex);
+        }
+        break;
+    case NvRmModuleID_BseA:
+        NV_ASSERT( Instance == 0 );
+        RESET( hDevice, RST_DEVICES_H, SWR_BSEA_RST, NVRM_RESET_DELAY );
+        break;
+    case NvRmModuleID_Cpu:
+        // FIXME: should this be allowed?
+        NV_ASSERT( Instance == 0 );
+        RESET( hDevice, RST_DEVICES_L, SWR_CPU_RST, NVRM_RESET_DELAY );
+        break;
+    case NvRmModuleID_Avp:
+        // FIXME: should this be allowed?
+        NV_ASSERT( Instance == 0 );
+        RESET( hDevice, RST_DEVICES_L, SWR_COP_RST, NVRM_RESET_DELAY );
+        break;
+    case NvRmPrivModuleID_System:
+        // THIS WILL DO A FULL SYSTEM RESET
+        NV_ASSERT( Instance == 0 );
+        RESET_SOC(hDevice);
+        break;
+    case NvRmModuleID_Ac97:
+        NV_ASSERT( Instance == 0 );
+        RESET( hDevice, RST_DEVICES_L, SWR_AC97_RST, NVRM_RESET_DELAY );
+        break;
+    case NvRmModuleID_Rtc:
+        NV_ASSERT( Instance == 0 );
+        RESET( hDevice, RST_DEVICES_L, SWR_RTC_RST, NVRM_RESET_DELAY );
+        break;
+    case NvRmModuleID_Timer:
+        NV_ASSERT( Instance == 0 );
+        // Timer reset (which also affects microsecond timer) is not allowed
+        // RESET( hDevice, RST_DEVICES_L, SWR_TMR_RST, NVRM_RESET_DELAY );
+        NV_ASSERT(!"Timer reset is not allowed");
+        break;
+    case NvRmModuleID_Uart:
+        NV_ASSERT( Instance < 3 );
+        if( Instance == 0 )
+        {
+            RESET( hDevice, RST_DEVICES_L, SWR_UARTA_RST, NVRM_RESET_DELAY );
+        }
+        else if( Instance == 1 )
+        {
+            RESET( hDevice, RST_DEVICES_L, SWR_UARTB_RST, NVRM_RESET_DELAY );
+        }
+        else if ( Instance == 2)
+        {
+            RESET( hDevice, RST_DEVICES_H, SWR_UARTC_RST, NVRM_RESET_DELAY );
+        }
+        break;
+    case NvRmModuleID_Vfir:
+        // Same as UARTB
+        NV_ASSERT( Instance == 0 );
+        RESET( hDevice, RST_DEVICES_L, SWR_UARTB_RST, NVRM_RESET_DELAY );
+        break;
+    case NvRmModuleID_Sdio:
+        NV_ASSERT( Instance < 2 );
+        if( Instance == 0 )
+        {
+            RESET( hDevice, RST_DEVICES_L, SWR_SDIO1_RST, NVRM_RESET_DELAY );
+        }
+        else if( Instance == 1 )
+        {
+            RESET( hDevice, RST_DEVICES_L, SWR_SDIO2_RST, NVRM_RESET_DELAY );
+        }
+        break;
+    case NvRmModuleID_Spdif:
+        NV_ASSERT( Instance == 0 );
+        RESET( hDevice, RST_DEVICES_L, SWR_SPDIF_RST, NVRM_RESET_DELAY );
+        break;
+    case NvRmModuleID_I2s:
+        NV_ASSERT( Instance < 2 );
+        if( Instance == 0 )
+        {
+            RESET( hDevice, RST_DEVICES_L, SWR_I2S1_RST, NVRM_RESET_DELAY );
+        }
+        else if( Instance == 1 )
+        {
+            RESET( hDevice, RST_DEVICES_L, SWR_I2S2_RST, NVRM_RESET_DELAY );
+        }
+        break;
+    case NvRmModuleID_Nand:
+        NV_ASSERT( Instance == 0 );
+        RESET( hDevice, RST_DEVICES_L, SWR_NDFLASH_RST, NVRM_RESET_DELAY );
+        break;
+    case NvRmModuleID_Hsmmc:
+        NV_ASSERT( Instance == 0 );
+        RESET( hDevice, RST_DEVICES_L, SWR_HSMMC_RST, NVRM_RESET_DELAY );
+        break;
+    case NvRmModuleID_Twc:
+        NV_ASSERT( Instance == 0 );
+        RESET( hDevice, RST_DEVICES_L, SWR_TWC_RST, NVRM_RESET_DELAY );
+        break;
+    case NvRmModuleID_Pwm:
+        NV_ASSERT( Instance == 0 );
+        RESET( hDevice, RST_DEVICES_L, SWR_PWM_RST, NVRM_RESET_DELAY );
+        break;
+    case NvRmModuleID_Epp:
+        NV_ASSERT( Instance == 0 );
+        RESET( hDevice, RST_DEVICES_L, SWR_EPP_RST, NVRM_RESET_DELAY );
+        break;
+    case NvRmModuleID_Vi:
+        NV_ASSERT( Instance == 0 );
+        RESET( hDevice, RST_DEVICES_L, SWR_VI_RST, NVRM_RESET_DELAY );
+        break;
+    case NvRmModuleID_3D:
+        NV_ASSERT( Instance == 0 );
+        RESET( hDevice, RST_DEVICES_L, SWR_3D_RST, NVRM_RESET_DELAY );
+        break;
+    case NvRmModuleID_2D:
+        NV_ASSERT( Instance == 0 );
+        // RESET( hDevice, RST_DEVICES_L, SWR_2D_RST, NVRM_RESET_DELAY );
+        // WAR for bug 364497, se also NvRmPrivAP15Reset2D()
+        NV_ASSERT(!"2D reset after RM open is no longer allowed");
+        break;
+    case NvRmModuleID_Usb2Otg:
+        {
+#if !NV_OAL
+            NvU32 RegVal = 0;
+            NV_ASSERT( Instance < 2 );
+            if (hDevice->ChipId.Id == 0x16)
+            {
+                RegVal = NV_REGR(hDevice, NvRmModuleID_Misc, 0, APB_MISC_PP_MISC_USB_CLK_RST_CTL_0);
+                if (!(NV_DRF_VAL(APB_MISC_PP, MISC_USB_CLK_RST_CTL, MISC_USB_CE, RegVal)) &&
+                    !(NV_DRF_VAL(APB_MISC_PP, MISC_USB_CLK_RST_CTL, MISC_USB2_CE, RegVal)) )
+                {
+                    /// Reset USBD if USB1/USB2 is not enabled already
+                    RESET( hDevice, RST_DEVICES_L, SWR_USBD_RST, NVRM_RESET_DELAY );
+                }
+            }
+            else
+           {
+               /// Reset USBD
+               RESET( hDevice, RST_DEVICES_L, SWR_USBD_RST, NVRM_RESET_DELAY );
+           }
+#else
+            /// Reset USBD
+            RESET( hDevice, RST_DEVICES_L, SWR_USBD_RST, NVRM_RESET_DELAY );
+#endif
+        }
+        break;
+    case NvRmModuleID_Isp:
+        NV_ASSERT( Instance == 0 );
+        RESET( hDevice, RST_DEVICES_L, SWR_ISP_RST, NVRM_RESET_DELAY );
+        break;
+    case NvRmModuleID_Ide:
+        NV_ASSERT( Instance == 0 );
+        RESET( hDevice, RST_DEVICES_L, SWR_IDE_RST, NVRM_RESET_DELAY );
+        break;
+    case NvRmModuleID_Display:
+        NV_ASSERT( Instance < 2 );
+        if( Instance == 0 )
+        {
+            RESET( hDevice, RST_DEVICES_L, SWR_DISP1_RST, NVRM_RESET_DELAY );
+        }
+        else if( Instance == 1 )
+        {
+            RESET( hDevice, RST_DEVICES_L, SWR_DISP2_RST, NVRM_RESET_DELAY );
+        }
+        break;
+    case NvRmModuleID_Vcp:
+        NV_ASSERT( Instance == 0 );
+        RESET( hDevice, RST_DEVICES_L, SWR_VCP_RST, NVRM_RESET_DELAY );
+        break;
+    case NvRmModuleID_CacheMemCtrl:
+        NV_ASSERT( Instance < 2 );
+        if( Instance == 0 )
+        {
+            RESET( hDevice, RST_DEVICES_L, SWR_CACHE1_RST, NVRM_RESET_DELAY );
+        }
+        else if( Instance == 1 )
+        {
+            RESET( hDevice, RST_DEVICES_L, SWR_CACHE2_RST, NVRM_RESET_DELAY );
+        }
+        break;
+    case NvRmPrivModuleID_ApbDma:
+        NV_ASSERT( Instance == 0 );
+        RESET( hDevice, RST_DEVICES_H, SWR_APBDMA_RST, NVRM_RESET_DELAY );
+        break;
+    case NvRmPrivModuleID_Gpio:
+        NV_ASSERT( Instance == 0 );
+        RESET( hDevice, RST_DEVICES_L, SWR_GPIO_RST, NVRM_RESET_DELAY );
+        break;
+    case NvRmModuleID_GraphicsHost:
+        // FIXME: should this be allowed?
+        NV_ASSERT( Instance == 0 );
+        RESET( hDevice, RST_DEVICES_L, SWR_HOST1X_RST, NVRM_RESET_DELAY );
+        break;
+    default:
+        NV_ASSERT(!"Invalid ModuleId");
+    }
+
+    #undef RESET
+}
+
+/*****************************************************************************/
+
+void
+NvRmPrivAp15Reset2D(NvRmDeviceHandle hRmDevice)
+{
+#if !NV_OAL
+    NvU32 reg, offset;
+    /*
+     * WAR for bug 364497: 2D can not be taken out of reset if VI clock is
+     * running. Therefore, make sure VI clock is disabled and reset 2D here
+     * during RM initialization.
+     */
+    Ap15EnableModuleClock(hRmDevice, NvRmModuleID_Vi, ModuleClockState_Disable);
+
+    // Assert reset to 2D module
+    offset = CLK_RST_CONTROLLER_RST_DEVICES_L_0;
+    reg = NV_REGR(hRmDevice, NvRmPrivModuleID_ClockAndReset, 0, offset);
+    reg = NV_FLD_SET_DRF_DEF(
+        CLK_RST_CONTROLLER, RST_DEVICES_L, SWR_2D_RST, ENABLE, reg);
+    NV_REGW(hRmDevice, NvRmPrivModuleID_ClockAndReset, 0, offset, reg);
+
+    // Enable "known good" configuartion for 2D clock (PLLM divided by 2)
+    offset = CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0;
+    NV_REGW(hRmDevice, NvRmPrivModuleID_ClockAndReset, 0, offset,
+            (NV_DRF_NUM(CLK_RST_CONTROLLER, CLK_SOURCE_G2D, G2D_CLK_DIVISOR, 2) |
+             NV_DRF_DEF(CLK_RST_CONTROLLER, CLK_SOURCE_G2D, G2D_CLK_SRC, PLLM_OUT0)));
+    Ap15EnableModuleClock(hRmDevice, NvRmModuleID_2D, ModuleClockState_Enable);
+    NvOsWaitUS(NVRM_RESET_DELAY);
+
+    // Take 2D out of reset and disable 2D clock. Both VI and 2D clocks are
+    // left disabled -it is up to the resepctive drivers to configure and enable
+    // them later.
+    offset = CLK_RST_CONTROLLER_RST_DEVICES_L_0;
+    reg = NV_FLD_SET_DRF_DEF(
+        CLK_RST_CONTROLLER, RST_DEVICES_L, SWR_2D_RST, DISABLE, reg);
+    NV_REGW(hRmDevice, NvRmPrivModuleID_ClockAndReset, 0, offset, reg);
+    Ap15EnableModuleClock(hRmDevice, NvRmModuleID_2D, ModuleClockState_Disable);
+#endif
+}
+
+void
+NvRmPrivAp15ClockConfigEx(
+    NvRmDeviceHandle hDevice,
+    NvRmModuleID Module,
+    NvU32 ClkSourceOffset,
+    NvU32 flags)
+{
+    NvU32 reg;
+
+    if ((Module == NvRmModuleID_Vi) &&
+        (!(flags & NvRmClockConfig_SubConfig)) &&
+         (flags & (NvRmClockConfig_InternalClockForPads |
+                   NvRmClockConfig_ExternalClockForPads |
+                   NvRmClockConfig_InternalClockForCore |
+                   NvRmClockConfig_ExternalClockForCore)))
+    {
+#ifdef CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_PD2VI_CLK_SEL_FIELD
+        reg = NV_REGR(
+            hDevice, NvRmPrivModuleID_ClockAndReset, 0, ClkSourceOffset);
+
+        /* Default is pads use External and Core use internal */
+        reg = NV_FLD_SET_DRF_NUM(
+            CLK_RST_CONTROLLER, CLK_SOURCE_VI, PD2VI_CLK_SEL, 0, reg);
+        reg = NV_FLD_SET_DRF_NUM(
+            CLK_RST_CONTROLLER, CLK_SOURCE_VI, VI_CLK_SEL, 0, reg);
+
+        /* This is an invalid setting. */
+        NV_ASSERT(!((flags & NvRmClockConfig_InternalClockForPads) &&
+                    (flags & NvRmClockConfig_ExternalClockForCore)));
+
+        if (flags & NvRmClockConfig_InternalClockForPads)
+            reg = NV_FLD_SET_DRF_NUM(
+                CLK_RST_CONTROLLER, CLK_SOURCE_VI, PD2VI_CLK_SEL, 1, reg);
+        if (flags & NvRmClockConfig_ExternalClockForCore)
+            reg = NV_FLD_SET_DRF_NUM(
+                CLK_RST_CONTROLLER, CLK_SOURCE_VI, VI_CLK_SEL, 1, reg);
+
+        NV_REGW(hDevice, NvRmPrivModuleID_ClockAndReset, 0,
+                ClkSourceOffset, reg);
+#endif
+    }
+    if (Module == NvRmModuleID_I2s)
+    {
+        reg = NV_REGR(
+            hDevice, NvRmPrivModuleID_ClockAndReset, 0, ClkSourceOffset);
+
+        if (flags & NvRmClockConfig_ExternalClockForCore)
+        {
+            // Set I2S in slave mode (field definition is the same for I2S1 and I2S2)
+            reg = NV_FLD_SET_DRF_NUM(
+                CLK_RST_CONTROLLER, CLK_SOURCE_I2S1, I2S1_MASTER_CLKEN, 0, reg);
+            NV_REGW(hDevice, NvRmPrivModuleID_ClockAndReset, 0,
+                    ClkSourceOffset, reg);
+        }
+        else if (flags & NvRmClockConfig_InternalClockForCore)
+        {
+            // Set I2S in master mode (field definition is the same for I2S1 and I2S2)
+            reg = NV_FLD_SET_DRF_NUM(
+                CLK_RST_CONTROLLER, CLK_SOURCE_I2S1, I2S1_MASTER_CLKEN, 1, reg);
+            NV_REGW(hDevice, NvRmPrivModuleID_ClockAndReset, 0,
+                    ClkSourceOffset, reg);
+        }
+    }
+}
+
+void NvRmPrivAp15SimPllInit(NvRmDeviceHandle hRmDevice)
+{
+    NvU32 RegData;
+
+    //Enable the plls in simulation. We can just use PLLC as the template
+    //and replicate across pllM and pllP since the offsets are the same.
+    RegData = NV_DRF_NUM (CLK_RST_CONTROLLER, PLLC_BASE, PLLC_DIVP, 0) 
+          | NV_DRF_NUM (CLK_RST_CONTROLLER, PLLC_BASE, PLLC_DIVM, 0) 
+          | NV_DRF_NUM (CLK_RST_CONTROLLER, PLLC_BASE, PLLC_DIVN, 0)
+          | NV_DRF_DEF (CLK_RST_CONTROLLER, PLLC_BASE, PLLC_BYPASS, DISABLE)
+          | NV_DRF_DEF (CLK_RST_CONTROLLER, PLLC_BASE, PLLC_ENABLE, ENABLE) ;
+
+    NV_REGW(hRmDevice, NvRmPrivModuleID_ClockAndReset, 0,
+            CLK_RST_CONTROLLER_PLLM_BASE_0, RegData);
+    NV_REGW(hRmDevice, NvRmPrivModuleID_ClockAndReset, 0,
+            CLK_RST_CONTROLLER_PLLC_BASE_0, RegData);
+    NV_REGW(hRmDevice, NvRmPrivModuleID_ClockAndReset, 0,
+            CLK_RST_CONTROLLER_PLLP_BASE_0, RegData);
+}
+
+NvError
+NvRmPrivAp15OscDoublerConfigure(
+    NvRmDeviceHandle hRmDevice,
+    NvRmFreqKHz OscKHz)
+{
+    NvU32 reg, Taps;
+    NvError error = NvRmPrivGetOscDoublerTaps(hRmDevice, OscKHz, &Taps);
+
+    if (error == NvSuccess)
+    {
+        // Program delay
+        reg = NV_REGR(hRmDevice, NvRmPrivModuleID_ClockAndReset, 0,
+                      CLK_RST_CONTROLLER_PROG_DLY_CLK_0);
+        reg = NV_FLD_SET_DRF_NUM(
+            CLK_RST_CONTROLLER, PROG_DLY_CLK, CLK_D_DELCLK_SEL, Taps, reg);
+        NV_REGW(hRmDevice, NvRmPrivModuleID_ClockAndReset, 0,
+                CLK_RST_CONTROLLER_PROG_DLY_CLK_0, reg);
+        // Enable doubler
+        reg = NV_REGR(hRmDevice, NvRmPrivModuleID_ClockAndReset, 0,
+                      CLK_RST_CONTROLLER_MISC_CLK_ENB_0);
+        reg = NV_FLD_SET_DRF_NUM(
+            CLK_RST_CONTROLLER, MISC_CLK_ENB, CLK_M_DOUBLER_ENB, 1, reg);
+    }
+    else
+    {
+        // Disable doubler
+        reg = NV_REGR(hRmDevice, NvRmPrivModuleID_ClockAndReset, 0,
+                      CLK_RST_CONTROLLER_MISC_CLK_ENB_0);
+        reg = NV_FLD_SET_DRF_NUM(
+            CLK_RST_CONTROLLER, MISC_CLK_ENB, CLK_M_DOUBLER_ENB, 0, reg);
+    }
+    NV_REGW(hRmDevice, NvRmPrivModuleID_ClockAndReset, 0,
+            CLK_RST_CONTROLLER_MISC_CLK_ENB_0, reg);
+    return error;
+}
+
+/*****************************************************************************/
+
diff --git a/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_clocks.h b/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_clocks.h
new file mode 100644
index 000000000000..9033261ba9ac
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_clocks.h
@@ -0,0 +1,460 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_AP15RM_CLOCKS_H
+#define INCLUDED_AP15RM_CLOCKS_H
+
+#include "nvrm_clocks.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif  /* __cplusplus */
+
+extern const NvRmModuleClockInfo g_Ap15ModuleClockTable[];
+extern const NvU32 g_Ap15ModuleClockTableSize;
+
+// PLLM ratios for graphic clocks
+#define NVRM_PLLM_HOST_SPEED_RATIO (4)
+#define NVRM_PLLM_2D_LOW_SPEED_RATIO (3)
+#define NVRM_PLLM_2D_HIGH_SPEED_RATIO (2)
+
+/**
+ * Defines frequency steps derived from PLLP0 fixed output to be used as System
+ * clock source frequency. The frequency specified in kHz, and it will be rounded
+ * up to the closest divider output. 
+ */
+#define NVRM_AP15_PLLP_POLICY_SYSTEM_CLOCK \
+    PLLP_POLICY_ENTRY(54000)   /* PLLP divider  6, output frequency  54,000kHz */ \
+    PLLP_POLICY_ENTRY(72000)   /* PLLP divider  4, output frequency  72,000kHz */ \
+    PLLP_POLICY_ENTRY(108000)  /* PLLP divider  2, output frequency 108,000kHz */ \
+    PLLP_POLICY_ENTRY(144000)  /* PLLP divider  1, output frequency 144,000kHz */ \
+    PLLP_POLICY_ENTRY(216000)  /* PLLP divider  0, output frequency 216,000kHz */
+
+/**
+ * Defines frequency steps derived from PLLP0 fixed output to be used as CPU
+ * clock source frequency. The frequency specified in kHz, and it will be rounded
+ * up to the closest divider output. 
+ */
+#define NVRM_AP15_PLLP_POLICY_CPU_CLOCK \
+    PLLP_POLICY_ENTRY(24000)   /* PLLP divider 16, output frequency  24,000kHz */ \
+    PLLP_POLICY_ENTRY(54000)   /* PLLP divider  6, output frequency  54,000kHz */ \
+    PLLP_POLICY_ENTRY(108000)  /* PLLP divider  2, output frequency 108,000kHz */ \
+    PLLP_POLICY_ENTRY(216000)  /* PLLP divider  0, output frequency 216,000kHz */ \
+
+/**
+ * Combines EMC 2x frequency and the respective set of EMC timing parameters for
+ * pre-defined EMC configurations (DDR clock is running at EMC 1x frequency)
+ */
+typedef struct NvRmAp15EmcTimingConfigRec
+{
+    NvRmFreqKHz Emc2xKHz;
+    NvU32 Timing0Reg;
+    NvU32 Timing1Reg;
+    NvU32 Timing2Reg;
+    NvU32 Timing3Reg;
+    NvU32 Timing4Reg;
+    NvU32 Timing5Reg;
+    NvU32 FbioCfg6Reg;
+    NvU32 FbioDqsibDly;
+    NvU32 FbioQuseDly;
+    NvU32 Emc2xDivisor;
+    NvRmFreqKHz McKHz;
+    NvU32 McDivisor;
+    NvU32 McClockSource;
+    NvRmFreqKHz CpuLimitKHz;
+    NvRmMilliVolts CoreVoltageMv;
+} NvRmAp15EmcTimingConfig;
+
+// Defines number of EMC frequency steps for DFS 
+#define NVRM_AP15_DFS_EMC_FREQ_STEPS (5)
+
+// Dfines CPU and EMC ratio policy as 
+// CpuKHz/CpuMax <= PolicyTabel[PLLM0/(2*EMC2xKHz)] / 256
+#define NVRM_AP15_CPU_EMC_RATIO_POLICY \
+    256, 192, 144, 122, 108, 98, 91, 86, 81, 77
+
+/*****************************************************************************/
+
+/**
+ * Enables/disables module clock.
+ * 
+ * @param hDevice The RM device handle.
+ * @param ModuleId Combined module ID and instance of the target module.
+ * @param ClockState Target clock state.
+ */
+void
+Ap15EnableModuleClock(
+    NvRmDeviceHandle hDevice,
+    NvRmModuleID ModuleId, 
+    ModuleClockState ClockState);
+
+// Separate API to control TVDAC clock independently of TVO
+// (when TVDAC is used for CRT)  
+void
+Ap15EnableTvDacClock(
+    NvRmDeviceHandle hDevice,
+    ModuleClockState ClockState);
+
+/**
+ * Resets module (assert/delay/deassert reset signal) if the hold paramter is
+ * NV_FLASE. If the hols paramter is NV_TRUE, just assert the reset and return.
+ * 
+ * @param hDevice The RM device handle.
+ * @param Module Combined module ID and instance of the target module.
+ * @param hold      To hold or relese the reset.
+ */
+void AP15ModuleReset(NvRmDeviceHandle hDevice, NvRmModuleID ModuleId, NvBool hold);
+
+/*****************************************************************************/
+
+/**
+ * Initializes PLL references table.
+ * 
+ * @param pPllReferencesTable A pointer to a pointer which this function sets
+ *  to the PLL reference table base. 
+ * @param pPllReferencesTableSize A pointer to a variable which this function
+ *  sets to the PLL reference table size.
+ */
+void
+NvRmPrivAp15PllReferenceTableInit(
+    NvRmPllReference** pPllReferencesTable,
+    NvU32* pPllReferencesTableSize);
+
+/**
+ * Initializes EMC clocks configuration structures and tables.
+ * 
+ * @param hRmDevice The RM device handle. 
+ */
+void
+NvRmPrivAp15EmcConfigInit(NvRmDeviceHandle hRmDevice);
+
+/**
+ * Resets 2D module.
+ * 
+ * @param hRmDevice The RM device handle. 
+ */
+void
+NvRmPrivAp15Reset2D(NvRmDeviceHandle hRmDevice);
+
+/**
+ * Initializes clock source table.
+ * 
+ * @return Pointer to the clock sources descriptor table.
+ */
+NvRmClockSourceInfo* NvRmPrivAp15ClockSourceTableInit(void);
+
+/**
+ * Sets "as is" specified PLL configuration: switches PLL in bypass mode,
+ * changes PLL settings, waits for PLL stabilization, and switches to PLL
+ * output.
+ * 
+ * @param hRmDevice The RM device handle.
+ * @param pCinfo Pointer to the PLL description structure.
+ * @param M PLL input divider setting.
+ * @param N PLL feedback divider setting.
+ * @param P PLL output divider setting.
+ *  PLL is left disabled (not bypassed) if either M or N setting is zero:
+ *  M = 0 or N = 0; otherwise, M, N, P validation is caller responsibility.
+ * @param StableDelayUs PLL stabilization delay in microseconds. If specified
+ *  value is above guaranteed stabilization time, the latter one is used.
+ * @param cpcon PLL charge pump control setting; ignored if TypicalControls
+ *  is true.
+ * @param lfcon PLL loop filter control setting; ignored if TypicalControls
+ *  is true.
+ * @param TypicalControls If true, both charge pump and loop filter parameters
+ *  are ignored and typical controls that corresponds to specified M, N, P
+ *  values will be set. If false, the cpcon and lfcon parameters are set; in
+ *  this case parameter validation is caller responsibility.
+ * @param flags PLL specific flags. Thse flags are valid only for some PLLs,
+ *  see @NvRmPllConfigFlags.
+ */
+void
+NvRmPrivAp15PllSet(
+    NvRmDeviceHandle hRmDevice,
+    const NvRmPllClockInfo* pCinfo,
+    NvU32 M,
+    NvU32 N,
+    NvU32 P,
+    NvU32 StableDelayUs,
+    NvU32 cpcon,
+    NvU32 lfcon,
+    NvBool TypicalControls,
+    NvU32 flags);
+
+/**
+ * Configures output frequency for specified PLL.
+ * 
+ * @param hRmDevice The RM device handle.
+ * @param PllId Targeted PLL ID.
+ * @param MaxOutKHz Upper limit for PLL output frequency.
+ * @param pPllOutKHz A pointer to the requested PLL frequency on entry,
+ *  and to the actually configured frequency on exit.
+ */
+void
+NvRmPrivAp15PllConfigureSimple(
+    NvRmDeviceHandle hRmDevice,
+    NvRmClockSource PllId,
+    NvRmFreqKHz MaxOutKHz,
+    NvRmFreqKHz* pPllOutKHz);
+
+/**
+ * Configures specified PLL output to the CM of fixed HDMI frequencies.
+ *
+ * @param hRmDevice The RM device handle.
+ * @param PllId Targeted PLL ID.
+ * @param pPllOutKHz A pointer to the actually configured frequency on exit.
+ */
+void
+NvRmPrivAp15PllConfigureHdmi(
+    NvRmDeviceHandle hRmDevice,
+    NvRmClockSource PllId,
+    NvRmFreqKHz* pPllOutKHz);
+
+/**
+ * Gets PLL output frequency.
+ * 
+ * @param hRmDevice The RM device handle.
+ * @param pCinfo Pointer to the PLL description structure.
+ * 
+ * @return PLL output frequency in kHz (reference frequency if PLL
+ *  is by-passed; zero if PLL is disabled and not by-passed).
+ */
+NvRmFreqKHz
+NvRmPrivAp15PllFreqGet(
+    NvRmDeviceHandle hRmDevice,
+    const NvRmPllClockInfo* pCinfo);
+
+/**
+ * Gets frequencies of DFS controlled clocks
+ * 
+ * @param hRmDevice The RM device handle.
+ * @param pDfsKHz Output storage pointer for DFS clock frequencies structure
+ *  (all frequencies returned in kHz).
+ */
+void
+NvRmPrivAp15DfsClockFreqGet(
+    NvRmDeviceHandle hRmDevice,
+    NvRmDfsFrequencies* pDfsKHz);
+
+/**
+ * Configures DFS controlled clocks
+ * 
+ * @param hRmDevice The RM device handle.
+ * @param pMaxKHz Pointer to the DFS clock frequencies upper limits
+ * @param pDfsKHz Pointer to the target DFS frequencies structure on entry;
+ *  updated with actual DFS clock frequencies on exit.
+ * 
+ * @return NV_TRUE if clock configuration is completed; NV_FALSE if this
+ *  function has to be called again to complete configuration.
+ */
+NvBool
+NvRmPrivAp15DfsClockConfigure(
+    NvRmDeviceHandle hRmDevice,
+    const NvRmDfsFrequencies* pMaxKHz,
+    NvRmDfsFrequencies* pDfsKHz);
+
+/**
+ * Gets maximum DFS domains frequencies that can be used at specified
+ *  core voltage.
+ * 
+ * @param hRmDevice The RM device handle.
+ * @param TargetMv Targeted core voltage in mV.
+ * @param pDfsKHz Pointer to a structure filled in by this function with
+ *  output clock frequencies.
+ */
+void
+NvRmPrivAp15DfsVscaleFreqGet(
+    NvRmDeviceHandle hRmDevice,
+    NvRmMilliVolts TargetMv,
+    NvRmDfsFrequencies* pDfsKHz);
+
+/**
+ * Determines if module clock configuration requires AP15-specific handling,
+ * and configures the clock if yes.
+ * 
+ * @param hRmDevice The RM device handle.
+ * @param pCinfo Pointer to the module clock descriptor. 
+ * @param ClockSourceCount Number of module clock sources.
+ * @param MinFreq Requested minimum module clock frequency.
+ * @param MaxFreq Requested maximum module clock frequency.
+ * @param PrefFreqList Pointer to a list of preferred frequencies sorted
+ *  in the decreasing order of priority.
+ * @param PrefCount Number of entries in the PrefFreqList array.
+ * @param pCstate Pointer to module state structure filled in if special
+ *  handling is completed.
+ * @param flags Module specific flags
+ *
+ * @return True indicates that module clock is configured, and regular
+ *  configuration should be aborted; False indicates that regular clock
+ *  configuration should proceed.
+ */
+NvBool
+NvRmPrivAp15IsModuleClockException(
+    NvRmDeviceHandle hRmDevice,
+    NvRmModuleClockInfo *pCinfo,
+    NvU32 ClockSourceCount,
+    NvRmFreqKHz MinFreq,
+    NvRmFreqKHz MaxFreq,
+    const NvRmFreqKHz* PrefFreqList,
+    NvU32 PrefCount,
+    NvRmModuleClockState* pCstate,
+    NvU32 flags);
+
+/**
+ * Configures EMC low-latency fifo for CPU clock source switch.
+ * 
+ * @param hRmDevice The RM device handle.
+ */
+void
+NvRmPrivAp15SetEmcForCpuSrcSwitch(NvRmDeviceHandle hRmDevice);
+
+/**
+ * Configures EMC low-latency fifo for CPU clock divider switch.
+ *
+ * @param hRmDevice The RM device handle.
+ * @param CpuFreq Resulting CPU frequency after divider switch
+ * @param Before Specifies if this function is called before (True)
+ *  or after (False) divider changes.
+ */
+void
+NvRmPrivAp15SetEmcForCpuDivSwitch(
+    NvRmDeviceHandle hRmDevice,
+    NvRmFreqKHz CpuFreq,
+    NvBool Before);
+
+/**
+ * Configures maximum core and memory clocks.
+ * 
+ * @param hRmDevice The RM device handle.
+ */
+void
+NvRmPrivAp15FastClockConfig(NvRmDeviceHandle hRmDevice);
+
+/**
+ * Gets module frequency synchronized with EMC speed.
+ * 
+ * @param hRmDevice The RM device handle.
+ * @param Module The target module ID.
+ * 
+ * @return Module frequency in kHz.
+ */
+NvRmFreqKHz NvRmPrivAp15GetEmcSyncFreq(
+    NvRmDeviceHandle hRmDevice,
+    NvRmModuleID Module);
+
+/**
+ * Disables PLLs
+ * 
+ * @param hRmDevice The RM device handle.
+ * @param pCinfo Pointer to the last configured module clock descriptor. 
+ * @param pCstate Pointer to the last configured module state structure.
+ */
+void
+NvRmPrivAp15DisablePLLs(
+    NvRmDeviceHandle hRmDevice,
+    const NvRmModuleClockInfo* pCinfo,
+    const NvRmModuleClockState* pCstate);
+
+/**
+ * Turns PLLD (MIPI PLL) power On/Off
+ * 
+ * @param hRmDevice The RM device handle.
+ * @param ConfigEntry NV_TRUE if this function is called before display
+ *  clock configuration; NV_FALSE otherwise.
+ * @param Pointer to the current state of MIPI PLL power rail, updated
+ *  by this function.
+ */
+void
+NvRmPrivAp15PllDPowerControl(
+    NvRmDeviceHandle hRmDevice,
+    NvBool ConfigEntry,
+    NvBool* pMipiPllVddOn);
+
+/**
+ * Clips EMC frequency high limit to one of the fixed DFS EMC configurations,
+ * and if necessary adjust CPU high limit respectively.
+ * 
+ * @param hRmDevice The RM device handle.
+ * @param pCpuHighKHz A pointer to the variable, which contains CPU frequency
+ *  high limit in KHz (on entry - requested limit, on exit - clipped limit)
+ * @param pEmcHighKHz A pointer to the variable, which contains EMC frequency
+ *  high limit in KHz (on entry - requested limit, on exit - clipped limit)
+ */
+void
+NvRmPrivAp15ClipCpuEmcHighLimits(
+    NvRmDeviceHandle hRmDevice,
+    NvRmFreqKHz* pCpuHighKHz,
+    NvRmFreqKHz* pEmcHighKHz);
+
+
+/**
+ * Configures some special bits in the clock source register for given module.
+ * 
+ * @param hRmDevice The RM device handle.
+ * @param Module Target module ID.
+ * @param ClkSourceOffset Clock source register offset.
+ * @param flags Module specific clock configuration flags.
+ */
+void
+NvRmPrivAp15ClockConfigEx(
+    NvRmDeviceHandle hRmDevice,
+    NvRmModuleID Module,
+    NvU32 ClkSourceOffset,
+    NvU32 flags);
+
+/**
+ * Enables PLL in simulation.
+ * 
+ * @param hRmDevice The RM device handle.
+ */
+void NvRmPrivAp15SimPllInit(NvRmDeviceHandle hRmDevice);
+
+/**
+ * Configures oscillator (main) clock doubler.
+ * 
+ * @param hRmDevice The RM device handle.
+ * @param OscKHz Oscillator (main) clock frequency in kHz.
+ * 
+ * @return NvSuccess if the specified oscillator frequency is supported, and
+ * NvError_NotSupported, otherwise.
+ */
+NvError
+NvRmPrivAp15OscDoublerConfigure(
+    NvRmDeviceHandle hRmDevice,
+    NvRmFreqKHz OscKHz);
+
+#ifdef __cplusplus
+}
+#endif  /* __cplusplus */
+
+#endif  // INCLUDED_AP15RM_CLOCKS_H 
diff --git a/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_clocks_info.c b/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_clocks_info.c
new file mode 100644
index 000000000000..b63198419fd4
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_clocks_info.c
@@ -0,0 +1,1673 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include "nvcommon.h"
+#include "nvrm_drf.h"
+#include "ap15rm_clocks.h"
+#include "ap15rm_private.h"
+#include "ap15/arclk_rst.h"
+#include "ap15/project_relocation_table.h"
+
+#define NV_COMMON_CLK_RST_FIELDS_INFO(MODULE, H_L) \
+        CLK_RST_CONTROLLER_CLK_SOURCE_##MODULE##_0, \
+        CLK_RST_CONTROLLER_CLK_SOURCE_##MODULE##_0_##MODULE##_CLK_SRC_DEFAULT_MASK, \
+        CLK_RST_CONTROLLER_CLK_SOURCE_##MODULE##_0_##MODULE##_CLK_SRC_SHIFT, \
+        CLK_RST_CONTROLLER_CLK_SOURCE_##MODULE##_0_##MODULE##_CLK_DIVISOR_DEFAULT_MASK, \
+        CLK_RST_CONTROLLER_CLK_SOURCE_##MODULE##_0_##MODULE##_CLK_DIVISOR_SHIFT, \
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_##H_L##_0, \
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_##H_L##_0_CLK_ENB_##MODULE##_FIELD, \
+        CLK_RST_CONTROLLER_RST_DEVICES_##H_L##_0, \
+        CLK_RST_CONTROLLER_RST_DEVICES_##H_L##_0_SWR_##MODULE##_RST_FIELD 
+        
+const NvRmModuleClockInfo g_Ap15ModuleClockTable[] =
+{
+    {   /* Invalid module */
+        NvRmPrivModuleID_System, 0, 0,
+        {
+            NvRmClockSource_SystemBus
+        },
+        NvRmClockDivider_None,
+        0, 0, 0, 0, 0,
+        
+        0,0,
+        CLK_RST_CONTROLLER_RST_DEVICES_L_0,
+        CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TRIG_SYS_RST_FIELD,
+        NvRmDiagModuleID_SystemReset
+    },
+    {   /* VI controller module - VI clock */
+        NvRmModuleID_Vi, 0 , 0,
+        {
+            NvRmClockSource_PllM0,
+            NvRmClockSource_PllC0,
+            NvRmClockSource_PllP0,
+            NvRmClockSource_PllA0
+        },
+        NvRmClockDivider_Fractional_2,
+        CLK_RST_CONTROLLER_CLK_SOURCE_VI_0,
+        CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SRC_DEFAULT_MASK,
+        CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SRC_SHIFT,
+        CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_DIVISOR_DEFAULT_MASK,
+        CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_DIVISOR_SHIFT,
+
+        // Combined VI and VI sensor reset and clock enable controls
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0,
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_VI_FIELD,
+        CLK_RST_CONTROLLER_RST_DEVICES_L_0,
+        CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_VI_RST_FIELD, 
+        NvRmDiagModuleID_Vi
+    },
+    {   /* VI controller module - VI sensor clock
+         * Module sub clock must immediately follow main clock
+         */
+        NvRmModuleID_Vi, 0 , 1,
+        {
+            NvRmClockSource_PllM0,
+            NvRmClockSource_PllC0,
+            NvRmClockSource_PllP0,
+            NvRmClockSource_PllA0
+        },
+        NvRmClockDivider_Fractional_2,
+        CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0,
+        CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_VI_SENSOR_CLK_SRC_DEFAULT_MASK,
+        CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_VI_SENSOR_CLK_SRC_SHIFT,
+        CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_VI_SENSOR_CLK_DIVISOR_DEFAULT_MASK,
+        CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_VI_SENSOR_CLK_DIVISOR_SHIFT,
+
+        // Combined VI and VI sensor reset and clock enable controls
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0,
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_VI_FIELD,
+        CLK_RST_CONTROLLER_RST_DEVICES_L_0,
+        CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_VI_RST_FIELD, 
+        NvRmDiagModuleID_ViSensor
+    },
+
+    {   /* I2S1 controller module */
+        NvRmModuleID_I2s, 0, 0,
+        {
+            NvRmClockSource_PllA0,
+            NvRmClockSource_AudioSync,
+            NvRmClockSource_PllP0,
+            NvRmClockSource_ClkM
+        },
+        NvRmClockDivider_Fractional_2,
+        NV_COMMON_CLK_RST_FIELDS_INFO(I2S1, L),
+        NvRmDiagModuleID_I2s
+    },
+    
+    {   /* I2S2 controller module */
+        NvRmModuleID_I2s, 1, 0,
+        {
+            NvRmClockSource_PllA0,
+            NvRmClockSource_AudioSync,
+            NvRmClockSource_PllP0,
+            NvRmClockSource_ClkM
+        },
+        NvRmClockDivider_Fractional_2,
+        NV_COMMON_CLK_RST_FIELDS_INFO(I2S2, L),
+        NvRmDiagModuleID_I2s
+    },
+
+    {   /* I2C1 controller module */
+        NvRmModuleID_I2c, 0, 0,
+        {
+            NvRmClockSource_PllP0,
+            NvRmClockSource_PllC0,
+            NvRmClockSource_PllM0,
+            NvRmClockSource_ClkM
+        },
+        NvRmClockDivider_Integer_1,
+        NV_COMMON_CLK_RST_FIELDS_INFO(I2C1, L),
+        NvRmDiagModuleID_I2c
+    },
+
+    {   /* I2C2 controller module */
+        NvRmModuleID_I2c, 1, 0,
+        {
+            NvRmClockSource_PllP0,
+            NvRmClockSource_PllC0,
+            NvRmClockSource_PllM0,
+            NvRmClockSource_ClkM
+        },
+        NvRmClockDivider_Integer_1,
+        NV_COMMON_CLK_RST_FIELDS_INFO(I2C2, H),
+        NvRmDiagModuleID_I2c
+    },
+
+    {   /* Hsmmc controller module */
+        NvRmModuleID_Hsmmc, 0, 0,
+        {
+            NvRmClockSource_PllP0,
+            NvRmClockSource_PllC0,
+            NvRmClockSource_PllM0,
+            NvRmClockSource_ClkM
+        },
+        NvRmClockDivider_Fractional_2,
+        NV_COMMON_CLK_RST_FIELDS_INFO(HSMMC, L),
+        NvRmDiagModuleID_Hsmmc
+    },
+
+    {   /* S/PDIF controller module - S/PDIF OUT clock */
+        NvRmModuleID_Spdif, 0, 0,
+        {
+            NvRmClockSource_PllA0,
+            NvRmClockSource_AudioSync,
+            NvRmClockSource_PllP0,
+            NvRmClockSource_ClkM
+        },
+        NvRmClockDivider_Fractional_2,
+        CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0,
+        CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0_SPDIFOUT_CLK_SRC_DEFAULT_MASK,
+        CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0_SPDIFOUT_CLK_SRC_SHIFT,
+        CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0_SPDIFOUT_CLK_DIVISOR_DEFAULT_MASK,
+        CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0_SPDIFOUT_CLK_DIVISOR_SHIFT,
+
+        // Combined SPDIF reset and and clock enable controls
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0,
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SPDIF_FIELD,
+        CLK_RST_CONTROLLER_RST_DEVICES_L_0,
+        CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SPDIF_RST_FIELD,
+        NvRmDiagModuleID_Spdif
+    },
+    {   /* S/PDIF controller module - S/PDIF IN clock
+         * Module sub clock must immediately follow main clock
+         */
+        NvRmModuleID_Spdif, 0, 1,
+        {
+            NvRmClockSource_PllP0,
+            NvRmClockSource_PllC0,
+            NvRmClockSource_PllM0
+        },
+        NvRmClockDivider_Fractional_2,
+        CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0,
+        CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0_SPDIFIN_CLK_SRC_DEFAULT_MASK,
+        CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0_SPDIFIN_CLK_SRC_SHIFT,
+        CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0_SPDIFIN_CLK_DIVISOR_DEFAULT_MASK,
+        CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0_SPDIFIN_CLK_DIVISOR_SHIFT,
+
+        // Combined SPDIF reset and and clock enable controls
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0,
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SPDIF_FIELD,
+        CLK_RST_CONTROLLER_RST_DEVICES_L_0,
+        CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SPDIF_RST_FIELD,
+        NvRmDiagModuleID_SpdifIn
+    },
+
+    {   /* PWM controller module */
+        NvRmModuleID_Pwm, 0, 0,
+        {
+            NvRmClockSource_PllP0,
+            NvRmClockSource_PllC0,
+            NvRmClockSource_AudioSync,
+            NvRmClockSource_ClkM
+        },
+        NvRmClockDivider_Fractional_2,
+        NV_COMMON_CLK_RST_FIELDS_INFO(PWM, L),
+        NvRmDiagModuleID_Pwm
+    },
+
+    {   /* SPI controller module */
+        NvRmModuleID_Spi, 0, 0,
+        {
+            NvRmClockSource_PllP0,
+            NvRmClockSource_PllC0,
+            NvRmClockSource_PllM0,
+            NvRmClockSource_ClkM
+        },
+        NvRmClockDivider_Fractional_2,
+        NV_COMMON_CLK_RST_FIELDS_INFO(SPI1, H),
+        NvRmDiagModuleID_Spi
+    },
+
+    {   /* SBC1 controller module */
+        NvRmModuleID_Slink, 0, 0,
+        {
+            NvRmClockSource_PllP0,
+            NvRmClockSource_PllC0,
+            NvRmClockSource_PllM0,
+            NvRmClockSource_ClkM
+        },
+        NvRmClockDivider_Fractional_2,
+        NV_COMMON_CLK_RST_FIELDS_INFO(SBC1, H),
+        NvRmDiagModuleID_Sbc
+    },
+
+    {   /* SBC2 controller module */
+        NvRmModuleID_Slink, 1, 0,
+        {
+            NvRmClockSource_PllP0,
+            NvRmClockSource_PllC0,
+            NvRmClockSource_PllM0,
+            NvRmClockSource_ClkM
+        },
+        NvRmClockDivider_Fractional_2,
+        NV_COMMON_CLK_RST_FIELDS_INFO(SBC2, H),
+        NvRmDiagModuleID_Sbc
+    },
+
+    {   /* SBC3 controller module */
+        NvRmModuleID_Slink, 2, 0,
+        {
+            NvRmClockSource_PllP0,
+            NvRmClockSource_PllC0,
+            NvRmClockSource_PllM0,
+            NvRmClockSource_ClkM
+        },
+        NvRmClockDivider_Fractional_2,
+        NV_COMMON_CLK_RST_FIELDS_INFO(SBC3, H),
+        NvRmDiagModuleID_Sbc
+    },
+
+    {   /* SLC controller module */
+        NvRmModuleID_Invalid, 0, 0,
+        {
+            NvRmClockSource_PllP0,
+            NvRmClockSource_PllC0,
+            NvRmClockSource_PllM0,
+            NvRmClockSource_ClkM
+        },
+        NvRmClockDivider_Fractional_2,
+        NV_COMMON_CLK_RST_FIELDS_INFO(SLC1, H),
+        NvRmDiagModuleID_Slc
+    },
+
+    {   /* TWC controller module */
+        NvRmModuleID_Twc, 0, 0,
+        {
+            NvRmClockSource_PllP0,
+            NvRmClockSource_PllC0,
+            NvRmClockSource_PllM0,
+            NvRmClockSource_ClkM
+        },
+        NvRmClockDivider_Fractional_2,
+        NV_COMMON_CLK_RST_FIELDS_INFO(TWC, L),
+        NvRmDiagModuleID_Twc
+    },
+
+    {   /* XIO controller module */
+        NvRmModuleID_Xio, 0, 0,
+        {
+            NvRmClockSource_PllP0,
+            NvRmClockSource_PllC0,
+            NvRmClockSource_PllM0,
+            NvRmClockSource_ClkM
+        },
+        NvRmClockDivider_Fractional_2,
+        NV_COMMON_CLK_RST_FIELDS_INFO(XIO, H),
+        NvRmDiagModuleID_Xio
+    },
+
+    {   /* IDE controller module */
+        NvRmModuleID_Ide, 0, 0,
+        {
+            NvRmClockSource_PllP0,
+            NvRmClockSource_PllC0,
+            NvRmClockSource_PllM0,
+            NvRmClockSource_ClkM
+        },
+        NvRmClockDivider_Fractional_2,
+        NV_COMMON_CLK_RST_FIELDS_INFO(IDE, L),
+        NvRmDiagModuleID_Ide
+    },
+
+    {   /* SDIO1 controller module */
+        NvRmModuleID_Sdio, 0, 0,
+        {
+            NvRmClockSource_PllP0,
+            NvRmClockSource_PllC0,
+            NvRmClockSource_PllM0,
+            NvRmClockSource_ClkM
+        },
+        NvRmClockDivider_Fractional_2,
+        NV_COMMON_CLK_RST_FIELDS_INFO(SDIO1, L),
+        NvRmDiagModuleID_Sdio
+    },
+
+    {   /* SDIO2 controller module */
+        NvRmModuleID_Sdio, 1, 0,
+        {
+            NvRmClockSource_PllP0,
+            NvRmClockSource_PllC0,
+            NvRmClockSource_PllM0,
+            NvRmClockSource_ClkM
+        },
+        NvRmClockDivider_Fractional_2,
+        NV_COMMON_CLK_RST_FIELDS_INFO(SDIO2, L),
+        NvRmDiagModuleID_Sdio
+    },
+
+    {   /* NAND Flash controller module */
+        NvRmModuleID_Nand, 0, 0,
+        {
+            NvRmClockSource_PllP0,
+            NvRmClockSource_PllC0,
+            NvRmClockSource_PllM0,
+            NvRmClockSource_ClkM
+        },
+        NvRmClockDivider_Fractional_2,
+        NV_COMMON_CLK_RST_FIELDS_INFO(NDFLASH, L),
+        NvRmDiagModuleID_NandFlash
+    },
+
+    {   /*  MIPI BB controller module */
+        NvRmModuleID_Mipi, 0, 0,
+        {
+            NvRmClockSource_PllP0,
+            NvRmClockSource_PllC0,
+            NvRmClockSource_PllM0,
+            NvRmClockSource_ClkM
+        },
+        NvRmClockDivider_Fractional_2,
+        NV_COMMON_CLK_RST_FIELDS_INFO(MIPI, H),
+        NvRmDiagModuleID_MipiBaseband
+    },
+
+    {   /* DVC controller module */
+        NvRmModuleID_Dvc, 0, 0,
+        {
+            NvRmClockSource_PllP0,
+            NvRmClockSource_PllC0,
+            NvRmClockSource_PllM0,
+            NvRmClockSource_ClkM
+        },
+        NvRmClockDivider_Integer_1,
+        NV_COMMON_CLK_RST_FIELDS_INFO(DVC_I2C, H),
+        NvRmDiagModuleID_Dvc
+    },
+
+    {   /* UARTA controller module */
+        NvRmModuleID_Uart, 0, 0,
+        {
+            NvRmClockSource_PllP0,
+            NvRmClockSource_PllC0,
+            NvRmClockSource_PllM0,
+            NvRmClockSource_ClkM
+        },
+        NvRmClockDivider_None,
+        CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0,
+        CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_SRC_DEFAULT_MASK,
+        CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_SRC_SHIFT,
+        0, 0,
+
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0,
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_UARTA_FIELD,
+        CLK_RST_CONTROLLER_RST_DEVICES_L_0,
+        CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_UARTA_RST_FIELD,
+        NvRmDiagModuleID_Uart
+    },
+
+    {   /* UARTB controller module */
+        NvRmModuleID_Uart, 1, 0,
+        {
+            NvRmClockSource_PllP0,
+            NvRmClockSource_PllC0,
+            NvRmClockSource_PllM0,
+            NvRmClockSource_ClkM
+        },
+        NvRmClockDivider_None,
+        CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0,
+        CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_CLK_SRC_DEFAULT_MASK,
+        CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_CLK_SRC_SHIFT,
+        0, 0,
+
+        // Combined UARTB and VFIR reset and clock enable controls
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0,
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_UARTB_FIELD,
+        CLK_RST_CONTROLLER_RST_DEVICES_L_0,
+        CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_UARTB_RST_FIELD,
+        NvRmDiagModuleID_Uart
+    },
+
+    {   /* UARTC controller module */
+        NvRmModuleID_Uart, 2, 0,
+        {
+            NvRmClockSource_PllP0,
+            NvRmClockSource_PllC0,
+            NvRmClockSource_PllM0,
+            NvRmClockSource_ClkM
+        },
+        NvRmClockDivider_None,
+        CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0,
+        CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_SRC_DEFAULT_MASK,
+        CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_SRC_SHIFT,
+        0, 0,
+
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0,
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_UARTC_FIELD,
+        CLK_RST_CONTROLLER_RST_DEVICES_H_0,
+        CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_UARTC_RST_FIELD,
+        NvRmDiagModuleID_Uart
+    },
+
+    {   /* VFIR controller module */
+        NvRmModuleID_Vfir, 0, 0,
+        {
+            NvRmClockSource_PllP0,
+            NvRmClockSource_PllC0,
+            NvRmClockSource_PllM0,
+            NvRmClockSource_ClkM
+        },
+        NvRmClockDivider_Fractional_2,
+        CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0,
+        CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_VFIR_CLK_SRC_DEFAULT_MASK,
+        CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_VFIR_CLK_SRC_SHIFT,
+        CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_VFIR_CLK_DIVISOR_DEFAULT_MASK,
+        CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_VFIR_CLK_DIVISOR_SHIFT,
+
+        // Combined UARTB and VFIR reset and clock enable controls
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0,
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_UARTB_FIELD,
+        CLK_RST_CONTROLLER_RST_DEVICES_L_0,
+        CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_UARTB_RST_FIELD,
+        NvRmDiagModuleID_Vfir
+    },
+
+    {   /* Host1x module */
+        NvRmModuleID_GraphicsHost, 0, 0,
+        {
+            NvRmClockSource_PllM0,
+            NvRmClockSource_PllC0,
+            NvRmClockSource_PllP0,
+            NvRmClockSource_PllA0
+        },
+        NvRmClockDivider_Fractional_2,
+        NV_COMMON_CLK_RST_FIELDS_INFO(HOST1X, L),
+        NvRmDiagModuleID_Host1x
+    },
+
+    {   /* EPP controller module */
+        NvRmModuleID_Epp, 0, 0,
+        {
+            NvRmClockSource_PllM0,
+            NvRmClockSource_PllC0,
+            NvRmClockSource_PllP0,
+            NvRmClockSource_PllA0
+        },
+        NvRmClockDivider_Fractional_2,
+        NV_COMMON_CLK_RST_FIELDS_INFO(EPP, L),
+        NvRmDiagModuleID_Epp
+    },
+
+    {   /* MPE controller module */
+        NvRmModuleID_Mpe, 0, 0,
+        {
+            NvRmClockSource_PllM0,
+            NvRmClockSource_PllC0,
+            NvRmClockSource_PllP0,
+            NvRmClockSource_PllA0
+        },
+        NvRmClockDivider_Fractional_2,
+        NV_COMMON_CLK_RST_FIELDS_INFO(MPE, H),
+        NvRmDiagModuleID_Mpe
+    },
+
+    {   /* 2D controller module */
+        NvRmModuleID_2D, 0, 0,
+        {
+            NvRmClockSource_PllM0,
+            NvRmClockSource_PllC0,
+            NvRmClockSource_PllP0,
+            NvRmClockSource_PllA0
+        },
+        NvRmClockDivider_Fractional_2,
+        CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0,
+        CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_G2D_CLK_SRC_DEFAULT_MASK,
+        CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_G2D_CLK_SRC_SHIFT,
+        CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_G2D_CLK_DIVISOR_DEFAULT_MASK,
+        CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_G2D_CLK_DIVISOR_SHIFT,
+
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0,
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_2D_FIELD,
+        CLK_RST_CONTROLLER_RST_DEVICES_L_0,
+        CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_2D_RST_FIELD, 
+        NvRmDiagModuleID_2d
+    },
+
+    {   /* 3D controller module */
+        NvRmModuleID_3D, 0, 0,
+        {
+            NvRmClockSource_PllM0,
+            NvRmClockSource_PllC0,
+            NvRmClockSource_PllP0,
+            NvRmClockSource_PllA0
+        },
+        NvRmClockDivider_Fractional_2,
+        CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0,
+        CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_G3D_CLK_SRC_DEFAULT_MASK,
+        CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_G3D_CLK_SRC_SHIFT,
+        CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_G3D_CLK_DIVISOR_DEFAULT_MASK,
+        CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_G3D_CLK_DIVISOR_SHIFT,
+
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0,
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_3D_FIELD,
+        CLK_RST_CONTROLLER_RST_DEVICES_L_0,
+        CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_3D_RST_FIELD, 
+        NvRmDiagModuleID_3d
+    },
+
+    {   /* Display 1 controller module */
+        NvRmModuleID_Display, 0, 0,
+        {
+            NvRmClockSource_PllP0,
+            NvRmClockSource_PllD0,
+            NvRmClockSource_PllC0,
+            NvRmClockSource_ClkM
+        },
+        NvRmClockDivider_None,
+        CLK_RST_CONTROLLER_CLK_SOURCE_DISP1_0,
+        CLK_RST_CONTROLLER_CLK_SOURCE_DISP1_0_DISP1_CLK_SRC_DEFAULT_MASK,
+        CLK_RST_CONTROLLER_CLK_SOURCE_DISP1_0_DISP1_CLK_SRC_SHIFT,
+        0, 0,
+
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0,
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_DISP1_FIELD,
+        CLK_RST_CONTROLLER_RST_DEVICES_L_0,
+        CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_DISP1_RST_FIELD, 
+        NvRmDiagModuleID_Display
+    },
+
+    {   /* Display 2 controller module */
+        NvRmModuleID_Display, 1, 0,
+        {
+            NvRmClockSource_PllP0,
+            NvRmClockSource_PllD0,
+            NvRmClockSource_PllC0,
+            NvRmClockSource_ClkM
+        },
+        NvRmClockDivider_None,
+        CLK_RST_CONTROLLER_CLK_SOURCE_DISP2_0,
+        CLK_RST_CONTROLLER_CLK_SOURCE_DISP2_0_DISP2_CLK_SRC_DEFAULT_MASK,
+        CLK_RST_CONTROLLER_CLK_SOURCE_DISP2_0_DISP2_CLK_SRC_SHIFT,
+        0, 0,
+
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0,
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_DISP2_FIELD,
+        CLK_RST_CONTROLLER_RST_DEVICES_L_0,
+        CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_DISP2_RST_FIELD, 
+        NvRmDiagModuleID_Display
+    },
+
+    {   /* TVO controller module - TVO clock */
+        NvRmModuleID_Tvo, 0, 0,
+        {
+            NvRmClockSource_PllP0,
+            NvRmClockSource_PllD0,
+            NvRmClockSource_PllC0,
+            NvRmClockSource_ClkM
+        },
+        NvRmClockDivider_Fractional_2,
+        CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0,
+        CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_TVO_CLK_SRC_DEFAULT_MASK,
+        CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_TVO_CLK_SRC_SHIFT,
+        CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_TVO_CLK_DIVISOR_DEFAULT_MASK,
+        CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_TVO_CLK_DIVISOR_SHIFT,
+
+        // Combined TVO, and CVE reset and and clock enable controls
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0,
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_TVO_FIELD,
+        CLK_RST_CONTROLLER_RST_DEVICES_H_0,
+        CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_TVO_RST_FIELD,
+        NvRmDiagModuleID_Tvo
+    },
+    {   /* TVO controller module - CVE clock
+         * Module sub clocks must immediately follow main clock
+         */
+        NvRmModuleID_Tvo, 0, 1,
+        {
+            NvRmClockSource_PllP0,
+            NvRmClockSource_PllD0,
+            NvRmClockSource_PllC0,
+            NvRmClockSource_ClkM
+        },
+        NvRmClockDivider_Fractional_2,
+        CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0,
+        CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_CVE_CLK_SRC_DEFAULT_MASK,
+        CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_CVE_CLK_SRC_SHIFT,
+        CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_CVE_CLK_DIVISOR_DEFAULT_MASK,
+        CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_CVE_CLK_DIVISOR_SHIFT,
+
+        // Combined TVO, and CVE reset and and clock enable controls
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0,
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_TVO_FIELD,
+        CLK_RST_CONTROLLER_RST_DEVICES_H_0,
+        CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_TVO_RST_FIELD,
+        NvRmDiagModuleID_Cve
+    },
+    {   /* TVO controller module - TVDAC clock
+         * Module sub clocks must immediately follow main clock
+         */
+        NvRmModuleID_Tvo, 0, 2,
+        {
+            NvRmClockSource_PllP0,
+            NvRmClockSource_PllD0,
+            NvRmClockSource_PllC0,
+            NvRmClockSource_ClkM
+        },
+        NvRmClockDivider_Fractional_2,
+        CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0,
+        CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_TVDAC_CLK_SRC_DEFAULT_MASK,
+        CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_TVDAC_CLK_SRC_SHIFT,
+        CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_TVDAC_CLK_DIVISOR_DEFAULT_MASK,
+        CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_TVDAC_CLK_DIVISOR_SHIFT,
+
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0,
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_TVDAC_FIELD,
+        CLK_RST_CONTROLLER_RST_DEVICES_H_0,
+        CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_TVDAC_RST_FIELD,
+        NvRmDiagModuleID_Tvdac
+    },
+
+    {   /* HDMI controller module */
+        NvRmModuleID_Hdmi, 0, 0,
+        {
+            NvRmClockSource_PllP0,
+            NvRmClockSource_PllD0,
+            NvRmClockSource_PllC0,
+            NvRmClockSource_ClkM
+        },
+        NvRmClockDivider_Fractional_2,
+        NV_COMMON_CLK_RST_FIELDS_INFO(HDMI, H),
+        NvRmDiagModuleID_Hdmi
+    },
+
+    {   /* VDE controller module (VDE and BSEV clocks)
+         * These clocks does not have source selector/divider registers,
+         * and should always be enabled/reset in sync. Threfore, no need
+         * for separate VDE and BSEV subclock descriptors
+         */
+        NvRmModuleID_Vde, 0, 0,
+        {
+            NvRmClockSource_Vbus
+        },
+        NvRmClockDivider_None,
+        0, 0, 0, 0, 0,
+
+       // Combined VDE and BSEV reset and and clock enable controls
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0,
+        (CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_VDE_FIELD |
+         CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_BSEV_FIELD),
+        CLK_RST_CONTROLLER_RST_DEVICES_H_0,
+        (CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_VDE_RST_FIELD |
+        CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_BSEV_RST_FIELD),
+        NvRmDiagModuleID_Vde
+    },
+
+    {   /*  BSEA controller module */
+        NvRmModuleID_BseA, 0, 0,
+        {
+            NvRmClockSource_SystemBus
+        },
+        NvRmClockDivider_None,
+        0, 0, 0, 0, 0,
+
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0,
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_BSEA_FIELD,
+        CLK_RST_CONTROLLER_RST_DEVICES_H_0,
+        CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_BSEA_RST_FIELD,
+        NvRmDiagModuleID_Bsea
+    },
+
+    {   /* VCP controller module */
+        NvRmModuleID_Vcp, 0, 0,
+        {
+            NvRmClockSource_SystemBus
+        },
+        NvRmClockDivider_None,
+        0, 0, 0, 0, 0,
+
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0,
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_VCP_FIELD,
+        CLK_RST_CONTROLLER_RST_DEVICES_L_0,
+        CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_VCP_RST_FIELD,
+        NvRmDiagModuleID_Vcp
+    },
+
+    {   /* Timer controller module */
+        NvRmModuleID_Timer, 0, 0,
+        {
+            NvRmClockSource_SystemBus
+        },
+        NvRmClockDivider_None,
+        0, 0, 0, 0, 0,
+
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0,
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_TMR_FIELD,
+        CLK_RST_CONTROLLER_RST_DEVICES_L_0,
+        CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TMR_RST_FIELD,
+        NvRmDiagModuleID_Timer
+    },
+
+    {   /*  System Monitor controller module */
+        NvRmModuleID_SysStatMonitor, 0, 0,
+        {
+            NvRmClockSource_SystemBus
+        },
+        NvRmClockDivider_None,
+        0, 0, 0, 0, 0,
+
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0,
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_STAT_MON_FIELD,
+        CLK_RST_CONTROLLER_RST_DEVICES_H_0,
+        CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_STAT_MON_RST_FIELD,
+        NvRmDiagModuleID_StatMon
+    },
+
+    {   /* GPIO controller module */
+        NvRmPrivModuleID_Gpio, 0, 0,
+        {
+            NvRmClockSource_SystemBus
+        },
+        NvRmClockDivider_None,
+        0, 0, 0, 0, 0,
+
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0,
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_GPIO_FIELD,
+        CLK_RST_CONTROLLER_RST_DEVICES_L_0,
+        CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_GPIO_RST_FIELD,
+        NvRmDiagModuleID_Gpio
+    },
+
+    {   /* USB controller module */
+        NvRmModuleID_Usb2Otg, 0, 0,
+        {
+            NvRmClockSource_PllU0
+        },
+        NvRmClockDivider_None,
+        0, 0, 0, 0, 0,
+
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0,
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_USBD_FIELD,
+        CLK_RST_CONTROLLER_RST_DEVICES_L_0,
+        CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_USBD_RST_FIELD,
+        NvRmDiagModuleID_Usb
+    },
+
+    {   /* USB controller module */
+        NvRmModuleID_Usb2Otg, 1, 0,
+        {
+            NvRmClockSource_PllU0
+        },
+        NvRmClockDivider_None,
+        0, 0, 0, 0, 0,
+
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0,
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_USBD_FIELD,
+        CLK_RST_CONTROLLER_RST_DEVICES_L_0,
+        CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_USBD_RST_FIELD,
+        NvRmDiagModuleID_Usb
+    },
+
+    {   /*  APB DMA controller module */
+        NvRmPrivModuleID_ApbDma, 0, 0,
+        {
+            NvRmClockSource_Apb
+        },
+        NvRmClockDivider_None,
+        0, 0, 0, 0, 0,
+
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0,
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_APBDMA_FIELD,
+        CLK_RST_CONTROLLER_RST_DEVICES_H_0,
+        CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_APBDMA_RST_FIELD,
+        NvRmDiagModuleID_ApbDma
+    },
+
+    {   /*  AC97 controller module */
+        NvRmModuleID_Ac97, 0, 0,
+        {
+            NvRmClockSource_Apb
+        },
+        NvRmClockDivider_None,
+        0, 0, 0, 0, 0,
+
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0,
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_AC97_FIELD,
+        CLK_RST_CONTROLLER_RST_DEVICES_L_0,
+        CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_AC97_RST_FIELD,
+        NvRmDiagModuleID_Ac97
+    },
+
+    {   /*  Keyboard controller module */
+        NvRmModuleID_Kbc, 0, 0,
+        {
+            NvRmClockSource_Apb
+        },
+        NvRmClockDivider_None,
+        0, 0, 0, 0, 0,
+
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0,
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_KBC_FIELD,
+        CLK_RST_CONTROLLER_RST_DEVICES_H_0,
+        CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_KBC_RST_FIELD,
+        NvRmDiagModuleID_Kbc
+    },
+
+    {   /* RTC  controller module */
+        NvRmModuleID_Rtc, 0, 0,
+        {
+            NvRmClockSource_Apb
+        },
+        NvRmClockDivider_None,
+        0, 0, 0, 0, 0,
+
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0,
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_RTC_FIELD,
+        CLK_RST_CONTROLLER_RST_DEVICES_L_0,
+        CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_RTC_RST_FIELD,
+        NvRmDiagModuleID_Rtc
+    },
+
+    {   /*  Fuse controller module */
+        NvRmModuleID_Fuse, 0, 0,
+        {
+            NvRmClockSource_Apb
+        },
+        NvRmClockDivider_None,
+        0, 0, 0, 0, 0,
+
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0,
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_FUSE_FIELD,
+        CLK_RST_CONTROLLER_RST_DEVICES_H_0,
+        CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_FUSE_RST_FIELD,
+        NvRmDiagModuleID_Fuse
+    },
+
+    {   /*  Power Management controller module */
+        NvRmModuleID_Pmif, 0, 0,
+        {
+            NvRmClockSource_Apb
+        },
+        NvRmClockDivider_None,
+        0, 0, 0, 0, 0,
+
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0,
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_PMC_FIELD,
+        CLK_RST_CONTROLLER_RST_DEVICES_H_0,
+        CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_PMC_RST_FIELD,
+        NvRmDiagModuleID_Pmc
+    },
+
+    {   /* CPU cache controller module */
+        NvRmModuleID_CacheMemCtrl, 0, 0,
+        {
+            NvRmClockSource_CpuBus
+        },
+        NvRmClockDivider_None,
+        0, 0, 0, 0, 0,
+
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0,
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CACHE1_FIELD,
+        CLK_RST_CONTROLLER_RST_DEVICES_L_0,
+        CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CACHE1_RST_FIELD,
+        NvRmDiagModuleID_Cache
+    },
+    {   /* COP (AVP) cache controller module */
+        NvRmModuleID_CacheMemCtrl, 1, 0,
+        {
+            NvRmClockSource_SystemBus
+        },
+        NvRmClockDivider_None,
+        0, 0, 0, 0, 0,
+
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0,
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CACHE2_FIELD,
+        CLK_RST_CONTROLLER_RST_DEVICES_L_0,
+        CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CACHE2_RST_FIELD,
+        NvRmDiagModuleID_Cache
+    },
+
+    {   /* DSI controller module */
+        NvRmModuleID_Dsi, 0, 0,
+        {
+            NvRmClockSource_PllD0
+        },
+        NvRmClockDivider_None,
+        0, 0, 0, 0, 0,
+
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0,
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_DSI_FIELD,
+        CLK_RST_CONTROLLER_RST_DEVICES_H_0,
+        CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_DSI_RST_FIELD,
+        NvRmDiagModuleID_Dsi
+    },
+
+    {   /* CSI  controller module */
+        NvRmModuleID_Csi, 0, 0,
+        {
+            NvRmClockSource_SystemBus // TODO: find a proper clock source
+        },
+        NvRmClockDivider_None,
+        0, 0, 0, 0, 0,
+
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0,
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_CSI_FIELD,
+        CLK_RST_CONTROLLER_RST_DEVICES_H_0,
+        CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_CSI_RST_FIELD,
+        NvRmDiagModuleID_Csi
+    },
+
+    {   /* ISP controller module */
+        NvRmModuleID_Isp, 0, 0,
+        {
+            NvRmClockSource_SystemBus // TODO: find a proper clock source
+        },
+        NvRmClockDivider_None,
+        0, 0, 0, 0, 0,
+
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0,
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_ISP_FIELD,
+        CLK_RST_CONTROLLER_RST_DEVICES_L_0,
+        CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_ISP_RST_FIELD,
+        NvRmDiagModuleID_Isp
+    },
+
+    {   /*  CPU module */
+        NvRmModuleID_Cpu, 0, 0,
+        {
+            NvRmClockSource_CpuBus
+        },
+        NvRmClockDivider_None,
+        0, 0, 0, 0, 0,
+
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0,
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CPU_FIELD,
+        CLK_RST_CONTROLLER_RST_DEVICES_L_0,
+        CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CPU_RST_FIELD,
+        NvRmDiagModuleID_Cpu
+    },
+
+    {   /*  COP (AVP) module */
+        NvRmModuleID_Avp, 0, 0,
+        {
+            NvRmClockSource_SystemBus // TODO: Add COP skipper source?
+        },
+        NvRmClockDivider_None,
+        0, 0, 0, 0, 0,
+
+        0, 0,
+        CLK_RST_CONTROLLER_RST_DEVICES_L_0,
+        CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_COP_RST_FIELD,
+        NvRmDiagModuleID_Coprocessor
+    },
+
+    {   /*  Memory controller module */
+        NvRmPrivModuleID_MemoryController, 0, 0,
+        {
+            NvRmClockSource_ClkM,
+            NvRmClockSource_PllC0,
+            NvRmClockSource_ClkS,
+            NvRmClockSource_PllM0,
+            NvRmClockSource_PllP0,
+            NvRmClockSource_PllP4,
+            NvRmClockSource_PllP3,
+            NvRmClockSource_ClkD
+        },
+        NvRmClockDivider_Fractional_2,
+        NV_COMMON_CLK_RST_FIELDS_INFO(MEM, H),
+        NvRmDiagModuleID_Mc
+    },
+
+    {   /*  External Memory controller module */
+        NvRmPrivModuleID_ExternalMemoryController, 0, 0,
+        {
+            NvRmClockSource_PllM0,
+            NvRmClockSource_PllC0,
+            NvRmClockSource_PllP0,
+            NvRmClockSource_ClkM,
+        },
+        NvRmClockDivider_Fractional_2,
+        CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0,
+        CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_SRC_DEFAULT_MASK,
+        CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_SRC_SHIFT,
+        CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_DIVISOR_DEFAULT_MASK,
+        CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_DIVISOR_SHIFT,
+
+        // EMC has 1x and 2x domains clock enable bits located in the source
+        // register. There is also a gloabl clock enable bit in CLK_OUT_ENB_L_0
+        // register, which is not described here. All 3 bits are set/cleared
+        // in Ap15EnableModuleClock() function below.
+        CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0,
+        (CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_ENB_FIELD |
+         CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_1X_CLK_ENB_FIELD),
+        CLK_RST_CONTROLLER_RST_DEVICES_H_0,
+        CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_EMC_RST_FIELD,
+        NvRmDiagModuleID_Emc
+    }
+};
+
+NvU32 const g_Ap15ModuleClockTableSize = NV_ARRAY_SIZE(g_Ap15ModuleClockTable);
+
+/*****************************************************************************/
+/*****************************************************************************/
+// Clock sources
+
+static const NvRmFixedClockInfo s_Ap15FixedClockTable[] =
+{
+    {
+        NvRmClockSource_ClkS,
+        NvRmClockSource_Invalid,
+        0, 0
+    },
+    {
+        NvRmClockSource_ClkM,
+        NvRmClockSource_Invalid,
+        0, 0
+    },
+    {
+        NvRmClockSource_ClkD,
+        NvRmClockSource_ClkM,
+        CLK_RST_CONTROLLER_MISC_CLK_ENB_0,
+        CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_M_DOUBLER_ENB_FIELD
+    },
+
+    {
+        NvRmClockSource_ExtSpdf,
+        NvRmClockSource_Invalid,
+        0, 0
+    },
+    {
+        NvRmClockSource_ExtI2s1,
+        NvRmClockSource_Invalid,
+        0, 0
+    },
+    {
+        NvRmClockSource_ExtI2s2,
+        NvRmClockSource_Invalid,
+        0, 0
+    },
+    {
+        NvRmClockSource_ExtAc97,
+        NvRmClockSource_Invalid,
+        0, 0
+    },
+    {
+        NvRmClockSource_ExtAudio1,
+        NvRmClockSource_Invalid,
+        0, 0
+    },
+    {
+        NvRmClockSource_ExtAudio2,
+        NvRmClockSource_Invalid,
+        0, 0
+    },
+    {
+        NvRmClockSource_ExtVi,
+        NvRmClockSource_Invalid,
+        0, 0
+    }
+};
+
+static const NvU32 s_Ap15FixedClockTableSize = NV_ARRAY_SIZE(s_Ap15FixedClockTable);
+
+/*****************************************************************************/
+
+// TODO: Specify PLL ref divider in OSC control reg as PLL C, D, M, P, U source
+
+/*
+ * Notation clarification: in h/w documentation PLL base outputs (except PLLA
+ * output) are denoted as PllX_OUT0, and the seconadry PLL outputs (if any)
+ * after fractional dividers are denoted as PllX_OUT1, PllX_OUT2, .... However,
+ * no h/w name is defined for the base PLLA output, and the output of the PLLA
+ * secondary divider is marked as PllA_OUT0 (not PllA_OUT1). Threfore, we use
+ * PllA1 (not PllA0) to denote base PLLA clock.
+ */
+static const NvRmPllClockInfo s_Ap15PllClockTable[] =
+{
+    {   /* PLLA base output */
+        NvRmClockSource_PllA1,
+        NvRmClockSource_PllP1,
+        NvRmPllType_LP,
+        CLK_RST_CONTROLLER_PLLA_BASE_0,
+        CLK_RST_CONTROLLER_PLLA_MISC_0,
+        50000,
+        1000000
+    },
+
+    {   /* PLLC base output */
+        NvRmClockSource_PllC0,
+        NvRmClockSource_ClkM,
+        NvRmPllType_LP,
+        CLK_RST_CONTROLLER_PLLC_BASE_0,
+        CLK_RST_CONTROLLER_PLLC_MISC_0,
+        100000,
+        1400000
+    },
+
+    {   /* PLLM base output */
+        NvRmClockSource_PllM0,
+        NvRmClockSource_ClkM,
+        NvRmPllType_LP,
+        CLK_RST_CONTROLLER_PLLM_BASE_0,
+        CLK_RST_CONTROLLER_PLLM_MISC_0,
+        100000,
+        1000000
+    },
+
+    {   /* PLLP base output */
+        NvRmClockSource_PllP0,
+        NvRmClockSource_ClkM,
+        NvRmPllType_LP,
+        CLK_RST_CONTROLLER_PLLP_BASE_0,
+        CLK_RST_CONTROLLER_PLLP_MISC_0,
+        100000,
+        1000000
+    },
+
+    {   /* PLLD base output */
+        NvRmClockSource_PllD0,
+        NvRmClockSource_ClkM,
+        NvRmPllType_MIPI,
+        CLK_RST_CONTROLLER_PLLD_BASE_0,
+        CLK_RST_CONTROLLER_PLLD_MISC_0,
+        100000,
+        1000000
+    },
+
+    {   /* PLLU base output */
+        NvRmClockSource_PllU0,
+        NvRmClockSource_ClkM,
+        NvRmPllType_MIPI,
+        CLK_RST_CONTROLLER_PLLU_BASE_0,
+        CLK_RST_CONTROLLER_PLLU_MISC_0,
+        100000,
+        1000000
+    }
+};
+
+static const NvU32 s_Ap15PllClockTableSize = NV_ARRAY_SIZE(s_Ap15PllClockTable);
+
+/*****************************************************************************/
+
+static const NvRmDividerClockInfo s_Ap15DividerClockTable[] =
+{
+    {   /* PLLA0 - PLLA secondary output */
+        NvRmClockSource_PllA0,
+        NvRmClockSource_PllA1,
+        NvRmClockDivider_Fractional_2,
+
+        CLK_RST_CONTROLLER_PLLA_OUT_0,
+        CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RATIO_DEFAULT_MASK,
+        CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RATIO_SHIFT,
+
+        CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_CLKEN_FIELD |
+         CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RSTN_FIELD,
+
+        ((CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_CLKEN_ENABLE <<
+          CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_CLKEN_SHIFT) |
+         (CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RSTN_RESET_DISABLE <<
+          CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RSTN_SHIFT)),
+
+        ((CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_CLKEN_DISABLE <<
+          CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_CLKEN_SHIFT) |
+         (CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RSTN_RESET_DISABLE <<
+          CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RSTN_SHIFT)),
+
+        NVRM_VARIABLE_DIVIDER
+    },
+
+    {   /* PLLC1 - PLLC secondary output */
+        NvRmClockSource_PllC1,
+        NvRmClockSource_PllC0,
+        NvRmClockDivider_Fractional_2,
+
+        CLK_RST_CONTROLLER_PLLC_OUT_0,
+        CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_RATIO_DEFAULT_MASK,
+        CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_RATIO_SHIFT,
+
+        CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_CLKEN_FIELD |
+         CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_RSTN_FIELD,
+
+        ((CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_CLKEN_ENABLE <<
+          CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_CLKEN_SHIFT) |
+         (CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_RSTN_RESET_DISABLE <<
+          CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_RSTN_SHIFT)),
+
+        ((CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_CLKEN_DISABLE <<
+          CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_CLKEN_SHIFT) |
+         (CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_RSTN_RESET_DISABLE <<
+          CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_RSTN_SHIFT)),
+
+        NVRM_VARIABLE_DIVIDER
+    },
+
+    {   /* PLLM1 - PLLM secondary ouput */
+        NvRmClockSource_PllM1,
+        NvRmClockSource_PllM0,
+        NvRmClockDivider_Fractional_2,
+
+        CLK_RST_CONTROLLER_PLLM_OUT_0,
+        CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_RATIO_DEFAULT_MASK,
+        CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_RATIO_SHIFT,
+
+        CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_CLKEN_FIELD |
+         CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_RSTN_FIELD,
+
+        ((CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_CLKEN_ENABLE <<
+          CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_CLKEN_SHIFT) |
+         (CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_RSTN_RESET_DISABLE <<
+          CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_RSTN_SHIFT)),
+
+        ((CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_CLKEN_DISABLE <<
+          CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_CLKEN_SHIFT) |
+         (CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_RSTN_RESET_DISABLE <<
+          CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_RSTN_SHIFT)),
+
+        NVRM_VARIABLE_DIVIDER
+    },
+
+    {   /* PLLP1 - PLLP secondary output (overridden) */
+        NvRmClockSource_PllP1,
+        NvRmClockSource_PllP0,
+        NvRmClockDivider_Fractional_2,
+
+        CLK_RST_CONTROLLER_PLLP_OUTA_0,
+        CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_RATIO_DEFAULT_MASK,
+        CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_RATIO_SHIFT,
+
+        CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_OVRRIDE_FIELD |
+         CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_CLKEN_FIELD |
+         CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_RSTN_FIELD,
+
+        ((CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_OVRRIDE_ENABLE <<
+          CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_OVRRIDE_SHIFT) |
+         (CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_CLKEN_ENABLE <<
+          CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_CLKEN_SHIFT) |
+         (CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_RSTN_RESET_DISABLE <<
+          CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_RSTN_SHIFT)),
+
+        ((CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_OVRRIDE_DISABLE <<
+          CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_OVRRIDE_SHIFT) |
+         (CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_CLKEN_DISABLE <<
+          CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_CLKEN_SHIFT) |
+         (CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_RSTN_RESET_DISABLE <<
+          CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_RSTN_SHIFT)),
+
+        NVRM_VARIABLE_DIVIDER
+    },
+
+    {   /* PLLP2 - PLLP secondary output (overridden) */
+        NvRmClockSource_PllP2,
+        NvRmClockSource_PllP0,
+        NvRmClockDivider_Fractional_2,
+
+        CLK_RST_CONTROLLER_PLLP_OUTA_0,
+        CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_RATIO_DEFAULT_MASK,
+        CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_RATIO_SHIFT,
+
+        CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_OVRRIDE_FIELD |
+         CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_CLKEN_FIELD |
+         CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_RSTN_FIELD,
+
+        ((CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_OVRRIDE_ENABLE <<
+          CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_OVRRIDE_SHIFT) |
+         (CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_CLKEN_ENABLE <<
+          CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_CLKEN_SHIFT) |
+         (CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_RSTN_RESET_DISABLE <<
+          CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_RSTN_SHIFT)),
+
+        ((CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_OVRRIDE_DISABLE <<
+          CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_OVRRIDE_SHIFT) |
+         (CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_CLKEN_DISABLE <<
+          CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_CLKEN_SHIFT) |
+         (CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_RSTN_RESET_DISABLE <<
+          CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_RSTN_SHIFT)),
+
+        NVRM_VARIABLE_DIVIDER
+    },
+
+    {   /* PLLP3 - PLLP secondary output (overridden)  */
+        NvRmClockSource_PllP3,
+        NvRmClockSource_PllP0,
+        NvRmClockDivider_Fractional_2,
+
+        CLK_RST_CONTROLLER_PLLP_OUTB_0,
+        CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_RATIO_DEFAULT_MASK,
+        CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_RATIO_SHIFT,
+
+        CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_OVRRIDE_FIELD |
+         CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_CLKEN_FIELD |
+         CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_RSTN_FIELD,
+
+        ((CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_OVRRIDE_ENABLE <<
+          CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_OVRRIDE_SHIFT) |
+         (CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_CLKEN_ENABLE <<
+          CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_CLKEN_SHIFT) |
+         (CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_RSTN_RESET_DISABLE <<
+          CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_RSTN_SHIFT)),
+
+        ((CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_OVRRIDE_DISABLE <<
+          CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_OVRRIDE_SHIFT) |
+         (CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_CLKEN_DISABLE <<
+          CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_CLKEN_SHIFT) |
+         (CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_RSTN_RESET_DISABLE <<
+          CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_RSTN_SHIFT)),
+
+        NVRM_VARIABLE_DIVIDER
+    },
+
+    {   /* PLLP4 - PLLP secondary output (overridden) */
+        NvRmClockSource_PllP4,
+        NvRmClockSource_PllP0,
+        NvRmClockDivider_Fractional_2,
+
+        CLK_RST_CONTROLLER_PLLP_OUTB_0,
+        CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_RATIO_DEFAULT_MASK,
+        CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_RATIO_SHIFT,
+
+        CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_OVRRIDE_FIELD |
+         CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_CLKEN_FIELD |
+         CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_RSTN_FIELD,
+
+        ((CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_OVRRIDE_ENABLE <<
+          CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_OVRRIDE_SHIFT) |
+         (CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_CLKEN_ENABLE <<
+          CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_CLKEN_SHIFT) |
+         (CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_RSTN_RESET_DISABLE <<
+          CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_RSTN_SHIFT)),
+
+        ((CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_OVRRIDE_DISABLE <<
+          CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_OVRRIDE_SHIFT) |
+         (CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_CLKEN_DISABLE <<
+          CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_CLKEN_SHIFT) |
+         (CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_RSTN_RESET_DISABLE <<
+          CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_RSTN_SHIFT)),
+
+        NVRM_VARIABLE_DIVIDER
+    },
+
+    {   /* AHB bus clock divider */
+        NvRmClockSource_Ahb,
+        NvRmClockSource_SystemBus,
+        NvRmClockDivider_Integer_1,
+
+        CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0,
+        CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_AHB_RATE_DEFAULT_MASK,
+        CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_AHB_RATE_SHIFT,
+
+        CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_HCLK_DIS_FIELD,
+        (0x0 << CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_HCLK_DIS_SHIFT),
+        (0x1 << CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_HCLK_DIS_SHIFT),
+         NVRM_VARIABLE_DIVIDER
+    },
+
+    {   /* APB bus clock divider */
+        NvRmClockSource_Apb,
+        NvRmClockSource_Ahb,
+        NvRmClockDivider_Integer_1,
+
+        CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0,
+        CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_APB_RATE_DEFAULT_MASK,
+        CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_APB_RATE_SHIFT,
+
+        CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_PCLK_DIS_FIELD,
+        (0x0 << CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_PCLK_DIS_SHIFT),
+        (0x1 << CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_PCLK_DIS_SHIFT),
+        NVRM_VARIABLE_DIVIDER
+    },
+
+    {   /* V-pipe clock divider */
+        NvRmClockSource_Vbus,
+        NvRmClockSource_SystemBus,
+        NvRmClockDivider_Keeper16,
+
+        CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0,
+        CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_VCLK_RATE_DEFAULT_MASK,
+        CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_VCLK_RATE_SHIFT,
+        0, 0, 0,
+        NVRM_VARIABLE_DIVIDER
+    },
+
+    // TODO: PLL ref divider
+};
+
+static const NvU32 s_Ap15DividerClockTableSize = NV_ARRAY_SIZE(s_Ap15DividerClockTable);
+
+/*****************************************************************************/
+
+static const NvRmCoreClockInfo s_Ap15CoreClockTable[] =
+{
+    {
+        NvRmClockSource_CpuBus,
+        {
+            NvRmClockSource_ClkM,
+            NvRmClockSource_PllC0,
+            NvRmClockSource_ClkS,
+            NvRmClockSource_PllM0,
+            NvRmClockSource_PllP0,
+            NvRmClockSource_PllP4,
+            NvRmClockSource_PllP3,
+            NvRmClockSource_ClkD
+        },
+
+        CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0,
+        CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_STATE_DEFAULT_MASK,
+        CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_STATE_SHIFT,
+        {
+            0,
+            CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IDLE_SOURCE_DEFAULT_MASK,
+            CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_RUN_SOURCE_DEFAULT_MASK,
+            CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IRQ_SOURCE_DEFAULT_MASK,
+            CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_FIQ_SOURCE_DEFAULT_MASK
+
+        },
+        {
+            0,
+            CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IDLE_SOURCE_SHIFT,
+            CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_RUN_SOURCE_SHIFT,
+            CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IRQ_SOURCE_SHIFT,
+            CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_FIQ_SOURCE_SHIFT
+        },
+
+        CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0,
+        CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_ENB_DEFAULT_MASK,
+        CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_ENB_SHIFT,
+        CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIVIDEND_DEFAULT_MASK,
+        CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIVIDEND_SHIFT,
+        NV_FIELD_SIZE(CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIVIDEND_RANGE),
+        CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIVISOR_DEFAULT_MASK,
+        CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIVISOR_SHIFT,
+        NV_FIELD_SIZE(CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIVISOR_RANGE)
+    },
+    {
+        NvRmClockSource_SystemBus,
+        {
+            NvRmClockSource_ClkM,
+            NvRmClockSource_PllC1,
+            NvRmClockSource_PllP4,
+            NvRmClockSource_PllP3,
+            NvRmClockSource_PllP2,
+            NvRmClockSource_ClkD,
+            NvRmClockSource_ClkS,
+            NvRmClockSource_PllM1,
+        },
+
+        CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0,
+        CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SYS_STATE_DEFAULT_MASK,
+        CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SYS_STATE_SHIFT,
+        {
+            0,
+            CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IDLE_SOURCE_DEFAULT_MASK,
+            CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_RUN_SOURCE_DEFAULT_MASK,
+            CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IRQ_SOURCE_DEFAULT_MASK,
+            CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_FIQ_SOURCE_DEFAULT_MASK
+
+        },
+        {
+            0,
+            CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IDLE_SOURCE_SHIFT,
+            CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_RUN_SOURCE_SHIFT,
+            CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IRQ_SOURCE_SHIFT,
+            CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_FIQ_SOURCE_SHIFT
+        },
+
+        CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0,
+        CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_ENB_DEFAULT_MASK,
+        CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_ENB_SHIFT,
+        CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIVIDEND_DEFAULT_MASK,
+        CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIVIDEND_SHIFT,
+        NV_FIELD_SIZE(CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIVIDEND_RANGE),
+        CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIVISOR_DEFAULT_MASK,
+        CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIVISOR_SHIFT,
+        NV_FIELD_SIZE(CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIVISOR_RANGE)
+    }
+};
+
+static const NvU32 s_Ap15CoreClockTableSize = NV_ARRAY_SIZE(s_Ap15CoreClockTable);
+
+/*****************************************************************************/
+
+static const NvRmSelectorClockInfo s_Ap15SelectorClockTable[] =
+{
+    {
+        NvRmClockSource_AudioSync,
+        {
+            NvRmClockSource_ExtSpdf,
+            NvRmClockSource_ExtI2s1,
+            NvRmClockSource_ExtI2s2,
+            NvRmClockSource_ExtAc97,
+            NvRmClockSource_PllA0,
+            NvRmClockSource_ExtAudio2,
+            NvRmClockSource_ExtAudio1,
+            NvRmClockSource_ExtVi
+        },
+        CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0,
+
+        CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_SYNC_CLK_RATE_DEFAULT_MASK,
+        CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_SYNC_CLK_RATE_SHIFT,
+
+        CLK_RST_CONTROLLER_MISC_CLK_ENB_0,
+        CLK_RST_CONTROLLER_MISC_CLK_ENB_0_SYNC_CLK_DOUBLER_ENB_FIELD
+    },
+    {
+        NvRmClockSource_MpeAudio,
+        {
+            NvRmClockSource_ExtSpdf,
+            NvRmClockSource_ExtI2s1,
+            NvRmClockSource_ExtI2s2,
+            NvRmClockSource_ExtAc97,
+            NvRmClockSource_PllA0,
+            NvRmClockSource_ExtAudio2,
+            NvRmClockSource_ExtAudio1,
+            NvRmClockSource_ExtVi
+        },
+        CLK_RST_CONTROLLER_CLK_SOURCE_MPE_AUDIO_0,
+
+        CLK_RST_CONTROLLER_CLK_SOURCE_MPE_AUDIO_0_MPE_AUDIO_CLK_SRC_DEFAULT_MASK,
+        CLK_RST_CONTROLLER_CLK_SOURCE_MPE_AUDIO_0_MPE_AUDIO_CLK_SRC_SHIFT,
+        0, 0
+    }
+};
+
+static const NvU32 s_Ap15SelectorClockTableSize = NV_ARRAY_SIZE(s_Ap15SelectorClockTable);
+
+/*****************************************************************************/
+/*****************************************************************************/
+
+static NvRmClockSourceInfo s_Ap15ClockSourceTable[NvRmClockSource_Num] = {{0}};
+
+NvRmClockSourceInfo* NvRmPrivAp15ClockSourceTableInit(void)
+{
+    NvRmClockSourceInfoPtr Src;
+
+#define PARSE_SOURCE_TABLE(type) \
+do\
+{\
+    Src.p##type = (NvRm##type##ClockInfo*)s_Ap15##type##ClockTable;\
+    NvRmPrivParseClockSources( \
+        s_Ap15ClockSourceTable, NvRmClockSource_Num, \
+        Src, s_Ap15##type##ClockTableSize, NvRmClockSourceType_##type); \
+} while(0)
+
+        NvOsMemset(s_Ap15ClockSourceTable, 0, sizeof(s_Ap15ClockSourceTable));
+
+        PARSE_SOURCE_TABLE(Fixed);
+        PARSE_SOURCE_TABLE(Pll);
+        PARSE_SOURCE_TABLE(Divider);
+        PARSE_SOURCE_TABLE(Core);
+        PARSE_SOURCE_TABLE(Selector);
+
+#undef PARSE_SOURCE_TABLE
+
+        return &s_Ap15ClockSourceTable[0];
+}
+
+/*****************************************************************************/
+
+static NvBool s_Ap15PllM0Clocks[NV_ARRAY_SIZE(g_Ap15ModuleClockTable)] = {0};
+static NvBool s_Ap15PllC0Clocks[NV_ARRAY_SIZE(g_Ap15ModuleClockTable)] = {0};
+static NvBool s_Ap15PllP0Clocks[NV_ARRAY_SIZE(g_Ap15ModuleClockTable)] = {0};
+static NvBool s_Ap15PllA0Clocks[NV_ARRAY_SIZE(g_Ap15ModuleClockTable)] = {0};
+static NvBool s_Ap15PllD0Clocks[NV_ARRAY_SIZE(g_Ap15ModuleClockTable)] = {0};
+
+static NvRmPllReference s_Ap15PllReferencesTable[] = 
+{
+    { NvRmClockSource_PllM0, NvRmDfsStatusFlags_StopPllM0, 0, s_Ap15PllM0Clocks, 0 },
+    { NvRmClockSource_PllC0, NvRmDfsStatusFlags_StopPllC0, 0, s_Ap15PllC0Clocks, 0 },
+    { NvRmClockSource_PllP0, NvRmDfsStatusFlags_StopPllP0, 0, s_Ap15PllP0Clocks, 0 },
+    { NvRmClockSource_PllA0, NvRmDfsStatusFlags_StopPllA0, 0, s_Ap15PllA0Clocks, 0 },
+    { NvRmClockSource_PllD0, NvRmDfsStatusFlags_StopPllD0, 0, s_Ap15PllD0Clocks, 0 },
+};
+static const NvU32 s_Ap15PllReferencesTableSize =
+    NV_ARRAY_SIZE(s_Ap15PllReferencesTable);
+
+void
+NvRmPrivAp15PllReferenceTableInit(
+    NvRmPllReference** pPllReferencesTable,
+    NvU32* pPllReferencesTableSize)
+{
+    NvU32 i;
+    for (i = 0; i < s_Ap15PllReferencesTableSize; i++)
+    {
+        NvOsMemset(s_Ap15PllReferencesTable[i].AttachedModules, 0,
+                   sizeof(NvBool) * g_Ap15ModuleClockTableSize);
+        s_Ap15PllReferencesTable[i].ReferenceCnt = 0;
+        s_Ap15PllReferencesTable[i].ExternalClockRefCnt = 0;
+    }
+    *pPllReferencesTable = s_Ap15PllReferencesTable;
+    *pPllReferencesTableSize = s_Ap15PllReferencesTableSize;
+}
+
+/*****************************************************************************/
+
+// Power Gating Ids for each Power Group specified in re-location table header
+static const NvU32 s_Ap15PowerGroupIds[] = { NV_POWERGROUP_ENUM_TABLE };
+
+void
+NvRmPrivAp15PowerGroupTableInit(
+    const NvU32** pPowerGroupIdsTable,
+    NvU32* pPowerGroupIdsTableSize)
+{
+    *pPowerGroupIdsTable = s_Ap15PowerGroupIds;
+    *pPowerGroupIdsTableSize = NV_ARRAY_SIZE(s_Ap15PowerGroupIds);
+}
+
+/*****************************************************************************/
+
diff --git a/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_fuse.c b/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_fuse.c
new file mode 100644
index 000000000000..0e0a8b21adab
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_fuse.c
@@ -0,0 +1,104 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/** @file
+ * @brief <b>NVIDIA Driver Development Kit: Fuse API</b>
+ *
+ * @b Description: Contains the NvRM Chip unique id implementation.
+ */
+#include "nvassert.h"
+#include "nvrm_drf.h"
+#include "nvos.h"
+#include "nvrm_module.h"
+#include "nvrm_hardware_access.h"
+#include "nvrm_hwintf.h"
+#include "ap15/arclk_rst.h"
+#include "ap15/arfuse.h"
+#include "ap15/ap15rm_private.h"
+#include "ap15rm_clocks.h"
+
+NvError NvRmPrivAp15ChipUniqueId(NvRmDeviceHandle hDevHandle,void* pId)
+{
+    NvU32   OldRegData;            // Old register contents
+    NvU32   NewRegData;            // New register contents
+    NvU64   Temp;                  // Temp buffer to read the contents of fuses
+    NV_ASSERT(hDevHandle);
+    NV_ASSERT(pId);
+
+#if NV_USE_FUSE_CLOCK_ENABLE
+    // Enable fuse clock
+    Ap15EnableModuleClock(hDevHandle, NvRmModuleID_Fuse, NV_TRUE);
+#endif
+
+    // Access to unique id is protected, so make sure all registers visible
+    // first.
+    OldRegData = NV_REGR(hDevHandle, 
+                        NvRmPrivModuleID_ClockAndReset,
+                         0, 
+                        CLK_RST_CONTROLLER_MISC_CLK_ENB_0);
+    NewRegData = NV_FLD_SET_DRF_NUM(CLK_RST_CONTROLLER,
+                                     MISC_CLK_ENB,
+                                     CFG_ALL_VISIBLE,
+                                     1,
+                                     OldRegData);
+    NV_REGW(hDevHandle,
+             NvRmPrivModuleID_ClockAndReset,
+             0,
+             CLK_RST_CONTROLLER_MISC_CLK_ENB_0,
+             NewRegData);
+
+    // Read the secure id from the fuse registers in to a local buffer
+    Temp = ((NvU64)NV_REGR(hDevHandle,
+                            (NvRmPrivModuleID)NvRmModuleID_Fuse,
+                             0,
+                             FUSE_JTAG_SECUREID_0_0)) |
+            (((NvU64)NV_REGR(hDevHandle,
+                             (NvRmPrivModuleID)NvRmModuleID_Fuse,
+                              0,
+                             FUSE_JTAG_SECUREID_1_0)) << 32);
+    // Copy the read data to output buffer
+    NvOsMemcpy(pId,&Temp,sizeof(NvU64));
+
+    // Restore the protected registers enable to the way we found it.
+    NV_REGW(hDevHandle,
+         NvRmPrivModuleID_ClockAndReset,
+         0,
+         CLK_RST_CONTROLLER_MISC_CLK_ENB_0,
+         OldRegData);
+
+#if NV_USE_FUSE_CLOCK_ENABLE
+    // Disable fuse clock
+    Ap15EnableModuleClock(hDevHandle, NvRmModuleID_Fuse, NV_FALSE);
+#endif
+
+    return NvError_Success;
+}
diff --git a/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_hwmap.c b/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_hwmap.c
new file mode 100644
index 000000000000..050abdfd7147
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_hwmap.c
@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include "nvcommon.h"
+#include "nvos.h"
+#include "nvassert.h"
+#include "nvrm_chiplib.h"
+
+NvError NvRmPhysicalMemMap(
+    NvRmPhysAddr     phys,
+    size_t           size,
+    NvU32            flags,
+    NvOsMemAttribute memType,
+    void           **ptr )
+{
+    return NvOsPhysicalMemMap(phys, size, memType, flags, ptr);
+}
+
+void NvRmPhysicalMemUnmap(void *ptr, size_t size)
+{
+    NvOsPhysicalMemUnmap(ptr, size);
+}
diff --git a/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_init.c b/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_init.c
new file mode 100644
index 000000000000..85b6dddd6add
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_init.c
@@ -0,0 +1,682 @@
+/*
+ * Copyright (c) 2007-2010 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include "nvcommon.h"
+#include "nvos.h"
+#include "nvutil.h"
+#include "nvassert.h"
+#include "nvrm_drf.h"
+#include "nvrm_init.h"
+#include "nvrm_rmctrace.h"
+#include "nvrm_configuration.h"
+#include "nvrm_chiplib.h"
+#include "nvrm_pmu_private.h"
+#include "nvrm_processor.h"
+#include "nvrm_xpc.h"
+#include "ap15rm_private.h"
+#include "nvrm_structure.h"
+#include "ap15rm_private.h"
+#include "ap15rm_clocks.h"
+#include "nvodm_query.h"
+#include "nvodm_query_pins.h"
+#include "common/nvrm_hwintf.h"
+#include "ap15/armc.h"
+#include "ap15/aremc.h"
+#include "ap15/project_relocation_table.h"
+#include "ap15/arapb_misc.h"
+#include "ap15/arapbpm.h"
+#include "nvrm_pinmux_utils.h"
+#include "ap15/arfuse.h"
+#include "nvbootargs.h"
+
+static NvRmDevice gs_Rm;
+
+extern NvRmCfgMap g_CfgMap[];
+
+void NvRmPrivMemoryInfo( NvRmDeviceHandle hDevice );
+extern NvError NvRmPrivMapApertures( NvRmDeviceHandle rm );
+extern void NvRmPrivUnmapApertures( NvRmDeviceHandle rm );
+extern NvError NvRmPrivPwmInit(NvRmDeviceHandle hRm);
+extern void NvRmPrivPwmDeInit(NvRmDeviceHandle hRm);
+extern NvU32 NvRmPrivGetBctCustomerOption(NvRmDeviceHandle hRm);
+extern void NvRmPrivReadChipId( NvRmDeviceHandle rm );
+extern NvU32 *NvRmPrivGetRelocationTable( NvRmDeviceHandle hDevice );
+static void NvRmPrivInitPinAttributes(NvRmDeviceHandle rm);
+static void NvRmPrivBasicReset( NvRmDeviceHandle rm );
+static NvError NvRmPrivMcErrorMonitorStart( NvRmDeviceHandle rm );
+static void NvRmPrivMcErrorMonitorStop( NvRmDeviceHandle rm );
+
+#if !NV_OAL
+/* This function sets some performance timings for Mc & Emc.  Numbers are from
+ * the Arch team.
+ */
+static void
+NvRmPrivSetupMc(NvRmDeviceHandle hRm)
+{
+    switch (hRm->ChipId.Id) {
+    case 0x15:
+    case 0x16:
+        NvRmPrivAp15SetupMc(hRm);
+        break;
+    case 0x20:
+        NvRmPrivAp20SetupMc(hRm);
+        break;
+    default:
+        NV_ASSERT(!"Unsupported chip ID");
+        break;
+    }
+}
+#endif
+
+NvError
+NvRmOpen(NvRmDeviceHandle *pHandle, NvU32 DeviceId ) {
+    return NvRmOpenNew(pHandle);
+}
+
+void NvRmInit(
+    NvRmDeviceHandle * pHandle )
+{
+    NvU32 *table = 0;
+    NvRmDevice *rm = 0;
+    rm = &gs_Rm;
+
+    if( rm->bPreInit )
+    {
+        return;
+    }
+
+    /* Read the chip Id and store in the Rm structure. */
+    NvRmPrivReadChipId( rm );
+
+    /* parse the relocation table */
+    table = NvRmPrivGetRelocationTable( rm );
+    NV_ASSERT(table != NULL);
+
+    NV_ASSERT_SUCCESS(NvRmPrivModuleInit( &rm->ModuleTable, table ));
+
+    NvRmPrivMemoryInfo( rm );
+
+    NvRmPrivInterruptTableInit( rm );
+
+    rm->bPreInit = NV_TRUE;
+    *pHandle = rm;
+
+    return;
+}
+
+NvError
+NvRmOpenNew(NvRmDeviceHandle *pHandle)
+{
+    NvError err;
+    NvRmDevice *rm = 0;
+    NvU32 *table = 0;
+
+    NvU32 BctCustomerOption = 0;
+    NvU64 Uid = 0;
+
+    NvOsMutexHandle rmMutex = NULL;
+
+    /* open the nvos trace file */
+    NVOS_TRACE_LOG_START;
+
+    // OAL does not support these mutexes
+    if (gs_Rm.mutex == NULL)
+    {
+        err = NvOsMutexCreate(&rmMutex);
+        if (err != NvSuccess)
+            return err;
+
+        if (NvOsAtomicCompareExchange32((NvS32*)&gs_Rm.mutex, 0,
+                (NvS32)rmMutex) != 0)
+            NvOsMutexDestroy(rmMutex);
+    }
+
+    NvOsMutexLock(gs_Rm.mutex);
+    rm = &gs_Rm;
+
+    if(rm->refcount )
+    {
+        rm->refcount++;
+        *pHandle = rm;
+        NvOsMutexUnlock(gs_Rm.mutex);
+        return NvSuccess;
+    }
+
+    rmMutex = gs_Rm.mutex;
+    gs_Rm.mutex = rmMutex;
+
+    // create the memmgr mutex
+    err = NvOsMutexCreate(&rm->MemMgrMutex);
+    if (err)
+        goto fail;
+
+    // create mutex for the clock and reset r-m-w top level registers access
+    err = NvOsMutexCreate(&rm->CarMutex);
+    if (err)
+        goto fail;
+
+    /* NvRmOpen needs to be re-entrant to allow I2C, GPIO and KeyList ODM
+     * services to be available to the ODM query.  Therefore, the refcount is
+     * bumped extremely early in initialization, and if any initialization
+     * fails the refcount is reset to 0.
+     */
+    rm->refcount = 1;
+
+    if( !rm->bBasicInit )
+    {
+        /* get the default configuration */
+        err = NvRmPrivGetDefaultCfg( g_CfgMap, &rm->cfg );
+        if( err != NvSuccess )
+        {
+            goto fail;
+        }
+
+        /* get the requested configuration */
+        err = NvRmPrivReadCfgVars( g_CfgMap, &rm->cfg );
+        if( err != NvSuccess )
+        {
+            goto fail;
+        }
+    }
+
+    /* start chiplib */
+    if (rm->cfg.Chiplib[0] != '\0')
+    {
+        err = NvRmPrivChiplibStartup( rm->cfg.Chiplib, rm->cfg.ChiplibArgs,
+            NULL );
+        if( err != NvSuccess )
+        {
+            goto fail;
+        }
+    }
+
+    /* open the RMC file */
+    err = NvRmRmcOpen( rm->cfg.RMCTraceFileName, &rm->rmc );
+    if( err != NvSuccess )
+    {
+        goto fail;
+    }
+
+    if( !rm->bPreInit )
+    {
+        /* Read the chip Id and store in the Rm structure. */
+        NvRmPrivReadChipId( rm );
+
+        /* parse the relocation table */
+        table = NvRmPrivGetRelocationTable( rm );
+        if( !table )
+        {
+            goto fail;
+        }
+
+        err = NvRmPrivModuleInit( &rm->ModuleTable, table );
+        if( err != NvSuccess )
+        {
+            goto fail;
+        }
+        NvRmPrivMemoryInfo( rm );
+
+        // Now populate the logical interrupt table.
+        NvRmPrivInterruptTableInit( rm );
+    }
+
+    if( !rm->bBasicInit && !NVOS_IS_WINDOWS_X86 )
+    {
+        err = NvRmPrivMapApertures( rm );
+        if( err != NvSuccess )
+        {
+            goto fail;
+        }
+
+        // Initializing the ODM-defined key list
+        //  This gets initialized first, since the RMs calls into
+        //  the ODM query may result in the ODM query calling
+        //  back into the RM to get this value!
+        BctCustomerOption = NvRmPrivGetBctCustomerOption(rm);
+        err = NvRmPrivInitKeyList(rm, &BctCustomerOption, 1);
+        if (err != NvSuccess)
+        {
+            goto fail;
+        }
+    }
+
+    // prevent re-inits
+    rm->bBasicInit = NV_TRUE;
+    rm->bPreInit = NV_TRUE;
+
+
+    if (!NVOS_IS_WINDOWS_X86)
+    {
+        NvRmPrivCheckBondOut( rm );
+
+        /* bring modules out of reset */
+        NvRmPrivBasicReset( rm );
+
+        /* initialize power manager before any other module that may access
+         * clock or voltage resources
+         */
+        err = NvRmPrivPowerInit(rm);
+        if( err != NvSuccess )
+        {
+            goto fail;
+        }
+
+        NvRmPrivInterruptStart( rm );
+
+        // Initializing pins attributes
+        NvRmPrivInitPinAttributes(rm);
+
+        // Initialize RM pin-mux (init's the state of internal shadow
+        // register variables)
+        NvRmInitPinMux(rm, NV_TRUE);
+
+        // Initalize the module clocks.
+        err = NvRmPrivClocksInit( rm );
+        if( err != NvSuccess )
+        {
+            goto fail;
+        }
+    }
+
+    if (!NVOS_IS_WINDOWS_X86)
+    {
+        // FIXME: this crashes in simulation
+        // Enabling only for the non simulation modes.
+        if ((rm->ChipId.Major == 0) && (rm->ChipId.Netlist == 0))
+        {
+            // this is the csim case, so we don't do this here.
+        }
+        else
+        {
+            // Initializing the dma.
+            err = NvRmPrivDmaInit(rm);
+            if( err != NvSuccess )
+            {
+                goto fail;
+            }
+
+            // Initializing the Spi and Slink.
+            err = NvRmPrivSpiSlinkInit(rm);
+            if( err != NvSuccess )
+            {
+                goto fail;
+            }
+
+            //  Complete pin mux initialization
+            NvRmInitPinMux(rm, NV_FALSE);
+
+            // Initializing the dfs
+            err = NvRmPrivDfsInit(rm);
+            if( err != NvSuccess )
+            {
+                goto fail;
+            }
+        }
+
+        // Initializing the Pwm
+        err = NvRmPrivPwmInit(rm);
+        if (err != NvSuccess)
+        {
+            goto fail;
+        }
+
+        // PMU interface init utilizes ODM services that reenter NvRmOpen().
+        // Therefore, it shall be performed after refcount is set so that
+        // reentry has no side-effects except bumping refcount. The latter
+        // is reset below so that RM can be eventually closed.
+        err = NvRmPrivPmuInit(rm);
+        if( err != NvSuccess )
+        {
+            goto fail;
+        }
+
+        // set the mc & emc tuning parameters
+        NvRmPrivSetupMc(rm);
+        if (!NvRmIsSimulation())
+        {
+            // Configure PLL rails, boost core power and clocks
+            // Initialize and start temperature monitoring
+            NvRmPrivPllRailsInit(rm);
+            NvRmPrivBoostClocks(rm);
+            NvRmPrivDttInit(rm);
+        }
+
+        // Asynchronous interrupts must be disabled until the very end of
+        // RmOpen. They can be enabled just before releasing rm mutex after
+        // completion of all initialization calls.
+        NvRmPrivPmuInterruptEnable(rm);
+
+        // Start Memory Controller Error monitoring.
+        err = NvRmPrivMcErrorMonitorStart(rm);
+        if( err != NvSuccess )
+        {
+            goto fail;
+        }
+
+        // WAR for bug 600821
+        if ((rm->ChipId.Id == 0x20) && 
+            (rm->ChipId.Major == 0x1) && (rm->ChipId.Minor == 0x2))
+        {
+            err = NvRmQueryChipUniqueId(rm, sizeof (NvU64), &Uid);
+            if ((Uid>>32) == 0x08080105)
+            {
+                NV_REGW(rm, NvRmModuleID_Pmif, 0, 0xD0, 0xFFFFFFEF);
+            }
+        }
+    }
+    err = NvRmXpcInitArbSemaSystem(rm);
+    if( err != NvSuccess )
+    {
+        goto fail;
+    }
+
+    /* assign the handle pointer */
+    *pHandle = rm;
+
+    NvOsMutexUnlock(gs_Rm.mutex);
+    return NvSuccess;
+
+fail:
+    // FIXME: free rm if it becomes dynamically allocated
+    // BUG:  there are about ten places that we go to fail, and we make no
+    // effort here to clean anything up.
+    NvOsMutexUnlock(gs_Rm.mutex);
+    NV_DEBUG_PRINTF(("RM init failed\n"));
+    rm->refcount = 0;
+    return err;
+}
+
+void
+NvRmClose(NvRmDeviceHandle handle)
+{
+    if( !handle )
+    {
+        return;
+    }
+
+    NV_ASSERT( handle->mutex );
+
+    /* decrement refcount */
+    NvOsMutexLock( handle->mutex );
+    handle->refcount--;
+
+    /* do deinit if refcount is zero */
+    if( handle->refcount == 0 )
+    {
+        if (!NVOS_IS_WINDOWS_X86)
+        {
+            // PMU and DTT deinit through ODM services reenters NvRmClose().
+            // The refcount will wrap around and this will be the only reentry
+            // side-effect, which is compensated after deint exit.
+            NvRmPrivDttDeinit();
+            handle->refcount = 0;
+            NvRmPrivPmuDeinit(handle);
+            handle->refcount = 0;
+
+        }
+
+        if (!NVOS_IS_WINDOWS_X86)
+        {
+            /* disable modules */
+            // Enabling only for the non simulation modes.
+            if ((handle->ChipId.Major == 0) && (handle->ChipId.Netlist == 0))
+            {
+                // this is the csim case, so we don't do this here.
+            }
+            else
+            {
+                NvRmPrivDmaDeInit();
+
+                NvRmPrivSpiSlinkDeInit();
+
+                NvRmPrivDfsDeinit(handle);
+            }
+
+            /* deinit clock manager */
+            NvRmPrivClocksDeinit(handle);
+
+            /* deinit power manager */
+            NvRmPrivPowerDeinit(handle);
+
+            NvRmPrivDeInitKeyList(handle);
+            NvRmPrivPwmDeInit(handle);
+            // Stop Memory controller error monitoring.
+            NvRmPrivMcErrorMonitorStop(handle);
+
+            /* if anyone left an interrupt registered, this will clear it. */
+            NvRmPrivInterruptShutdown(handle);
+
+            /* unmap the apertures */
+            NvRmPrivUnmapApertures( handle );
+
+            if (NvRmIsSimulation())
+                NvRmPrivChiplibShutdown();
+
+        }
+
+        NvRmRmcClose( &handle->rmc );
+
+        /* deallocate the instance table */
+        NvRmPrivModuleDeinit( &handle->ModuleTable );
+
+        /* free up the CAR mutex */
+        NvOsMutexDestroy(handle->CarMutex);
+
+        /* free up the memmgr mutex */
+        NvOsMutexDestroy(handle->MemMgrMutex);
+
+        /* close the nvos trace file */
+        NVOS_TRACE_LOG_END;
+    }
+    NvOsMutexUnlock( handle->mutex );
+
+#if NVOS_IS_WINDOWS && !NVOS_IS_WINDOWS_CE
+    if( handle->refcount == 0 )
+    {
+        NvOsMutexDestroy(handle->mutex);
+        gs_Rm.mutex = 0;
+    }
+#endif
+}
+
+void
+NvRmPrivMemoryInfo( NvRmDeviceHandle hDevice )
+{
+    NvRmModuleTable *tbl;
+    NvRmModuleInstance *inst;
+
+    tbl = &hDevice->ModuleTable;
+
+    /* Get External memory module info */
+    inst = tbl->ModInst +
+        (tbl->Modules)[NvRmPrivModuleID_ExternalMemory].Index;
+
+    hDevice->ExtMemoryInfo.base = inst->PhysAddr;
+    hDevice->ExtMemoryInfo.size = inst->Length;
+
+    /* Get Iram Memory Module Info .Special handling since iram has 4 banks
+     * and each has a different instance in the relocation table
+     */
+
+    inst = tbl->ModInst + (tbl->Modules)[NvRmPrivModuleID_Iram].Index;
+    hDevice->IramMemoryInfo.base = inst->PhysAddr;
+    hDevice->IramMemoryInfo.size = inst->Length;
+
+    inst++;
+    // Below loop works assuming that relocation table parsing compacted
+    // scattered multiple instances into sequential list
+    while(NvRmPrivDevToModuleID(inst->DeviceId) == NvRmPrivModuleID_Iram)
+    {
+        // The IRAM banks are contigous address of memory. Cannot handle
+        // non-contigous memory for now
+        NV_ASSERT(hDevice->IramMemoryInfo.base +
+            hDevice->IramMemoryInfo.size == inst->PhysAddr);
+
+        hDevice->IramMemoryInfo.size += inst->Length;
+        inst++;
+    }
+
+}
+
+NvError
+NvRmGetRmcFile( NvRmDeviceHandle hDevice, NvRmRmcFile **file )
+{
+    NV_ASSERT(hDevice);
+
+    *file = &hDevice->rmc;
+    return NvSuccess;
+}
+
+NvRmDeviceHandle NvRmPrivGetRmDeviceHandle()
+{
+    return &gs_Rm;
+}
+
+/**
+ * Initializes pins attributes
+ * @param hRm The RM device handle
+ */
+static void
+NvRmPrivInitPinAttributes(NvRmDeviceHandle rm)
+{
+    NvU32 Count = 0, Offset = 0, Value = 0;
+    NvU32 Major = 0;
+    NvU32 Minor = 0;
+    NvOdmPinAttrib *pPinAttribTable = NULL;
+    NvRmModuleCapability caps[4];
+    NvRmModuleCapability *pCap = NULL;
+
+    NV_ASSERT( rm );
+
+    NvOsMemset(caps, 0, sizeof(caps));
+
+    caps[0].MajorVersion = 1;
+    caps[0].MinorVersion = 0;
+    caps[0].EcoLevel = 0;
+    caps[0].Capability = &caps[0];
+
+    caps[1].MajorVersion = 1;
+    caps[1].MinorVersion = 1;
+    caps[1].EcoLevel = 0;
+
+    caps[2].MajorVersion = 1;
+    caps[2].MinorVersion = 2;
+    caps[2].EcoLevel = 0;
+
+    //  the pin attributes for v 1.0 and v1.1 of the misc module
+    //  are fully compatible, so the version comparison is made against 1.0
+    // Treating 1.2 same as 1.0/1.1.
+    caps[1].Capability = &caps[0];
+    caps[2].Capability = &caps[0];
+
+    /* AP20 misc module pin attributes, set differently than AP15 as the pin
+     * attribute registers in misc module changed */
+    caps[3].MajorVersion = 2;
+    caps[3].MinorVersion = 0;
+    caps[3].EcoLevel = 0;
+    caps[3].Capability = &caps[3];
+
+    NV_ASSERT_SUCCESS(NvRmModuleGetCapabilities(
+            rm,
+            NvRmModuleID_Misc,
+            caps,
+            sizeof(caps)/sizeof(caps[0]),
+            (void**)&pCap));
+
+    Count = NvOdmQueryPinAttributes((const NvOdmPinAttrib **)&pPinAttribTable);
+
+    for ( ; Count ; Count--, pPinAttribTable++)
+    {
+        Major = (pPinAttribTable->ConfigRegister >> 28);
+        Minor = (pPinAttribTable->ConfigRegister >> 24) & 0xF;
+        if ((Major == pCap->MajorVersion) && (Minor == pCap->MinorVersion))
+        {
+            Offset = pPinAttribTable->ConfigRegister & 0xFFFF;
+            Value = pPinAttribTable->Value;
+            NV_REGW(rm, NvRmModuleID_Misc, 0, Offset, Value);
+        }
+    }
+}
+
+
+static void NvRmPrivBasicReset( NvRmDeviceHandle rm )
+{
+    switch (rm->ChipId.Id) {
+    case 0x15:
+    case 0x16:
+        NvRmPrivAp15BasicReset(rm);
+        return;
+    case 0x20:
+        NvRmPrivAp20BasicReset(rm);
+        return;
+    default:
+        NV_ASSERT(!"Unsupported chip ID");
+        return;
+    }
+}
+
+NvError NvRmPrivMcErrorMonitorStart( NvRmDeviceHandle rm )
+{
+    NvError e = NvError_NotSupported;
+
+    switch (rm->ChipId.Id) {
+    case 0x15:
+    case 0x16:
+        e = NvRmPrivAp15McErrorMonitorStart(rm);
+        break;
+    case 0x20:
+        e = NvRmPrivAp20McErrorMonitorStart(rm);
+        break;
+    default:
+        NV_ASSERT(!"Unsupported chip ID");
+        break;
+    }
+    return e;
+}
+
+void NvRmPrivMcErrorMonitorStop( NvRmDeviceHandle rm )
+{
+    switch (rm->ChipId.Id) {
+    case 0x15:
+    case 0x16:
+        NvRmPrivAp15McErrorMonitorStop(rm);
+        break;
+    case 0x20:
+        NvRmPrivAp20McErrorMonitorStop(rm);
+        break;
+    default:
+        NV_ASSERT(!"Unsupported chip ID");
+        break;
+    }
+}
+
+
diff --git a/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_init_common.c b/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_init_common.c
new file mode 100644
index 000000000000..fe3496ed65cd
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_init_common.c
@@ -0,0 +1,521 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include "nvcommon.h"
+#include "nvos.h"
+#include "nvutil.h"
+#include "nvassert.h"
+#include "nvrm_drf.h"
+#include "nvrm_init.h"
+#include "nvrm_rmctrace.h"
+#include "nvrm_configuration.h"
+#include "nvrm_chiplib.h"
+#include "nvrm_pmu_private.h"
+#include "nvrm_processor.h"
+#include "nvrm_structure.h"
+#include "ap15rm_private.h"
+#include "ap15rm_private.h"
+#include "ap15rm_clocks.h"
+#include "nvodm_query.h"
+#include "nvodm_query_pins.h"
+#include "common/nvrm_hwintf.h"
+#include "nvrm_pinmux_utils.h"
+#include "nvrm_minikernel.h"
+#include "ap15/arapb_misc.h" // chipid, has to be the same for all chips
+#include "ap15/arapbpm.h"
+#include "ap15/arfuse.h"
+
+extern NvRmCfgMap g_CfgMap[];
+
+void NvRmPrivMemoryInfo( NvRmDeviceHandle hDevice );
+void NvRmPrivReadChipId( NvRmDeviceHandle rm );
+void NvRmPrivGetSku( NvRmDeviceHandle rm );
+/** Returns the pointer to the relocation table */
+NvU32 *NvRmPrivGetRelocationTable( NvRmDeviceHandle hDevice );
+NvError NvRmPrivMapApertures( NvRmDeviceHandle rm );
+void NvRmPrivUnmapApertures( NvRmDeviceHandle rm );
+NvU32 NvRmPrivGetBctCustomerOption(NvRmDeviceHandle hRm);
+
+NvRmCfgMap g_CfgMap[] =
+{
+    { "NV_CFG_RMC_FILE", NvRmCfgType_String, (void *)"",
+        STRUCT_OFFSET(RmConfigurationVariables, RMCTraceFileName) },
+
+    /* don't need chiplib for non-sim builds */
+    { "NV_CFG_CHIPLIB", NvRmCfgType_String, (void *)"",
+        STRUCT_OFFSET(RmConfigurationVariables, Chiplib) },
+
+    { "NV_CFG_CHIPLIB_ARGS", NvRmCfgType_String, (void *)"",
+        STRUCT_OFFSET(RmConfigurationVariables, ChiplibArgs) },
+
+    { 0 }
+};
+
+NvRmModuleTable *
+NvRmPrivGetModuleTable(
+    NvRmDeviceHandle hDevice )
+{
+    return &hDevice->ModuleTable;
+}
+
+NvU32 *
+NvRmPrivGetRelocationTable( NvRmDeviceHandle hDevice )
+{
+    switch( hDevice->ChipId.Id ) {
+    case 0x15:
+        return NvRmPrivAp15GetRelocationTable( hDevice );
+    case 0x16:
+        return NvRmPrivAp16GetRelocationTable( hDevice );
+    case 0x20:
+        return NvRmPrivAp20GetRelocationTable( hDevice );
+    default:
+        NV_ASSERT(!"Invalid Chip" );
+        return 0;
+    }
+}
+
+void
+NvRmPrivReadChipId( NvRmDeviceHandle rm )
+{
+#if (NVCPU_IS_X86 && NVOS_IS_WINDOWS)
+    NvRmChipId *id;
+    NV_ASSERT( rm );
+
+    id = &rm->ChipId;
+
+    id->Family = NvRmChipFamily_HandheldSoc;
+    id->Id = 0x15;
+    id->Major = 0x0;
+    id->Minor = 0x0;
+    id->SKU = 0x0;
+    id->Netlist = 0x0;
+    id->Patch = 0x0;
+#else
+    NvU32 reg;
+    NvRmChipId *id;
+    NvU32 fam;
+    char *s;
+    NvU8 *VirtAddr;
+    NvError e;
+
+    NV_ASSERT( rm );
+    id = &rm->ChipId;
+
+    /* Hard coding the address of the chip ID address space, as we haven't yet
+     * parsed the relocation table.
+     */
+    e = NvRmPhysicalMemMap(0x70000000, 0x1000, NVOS_MEM_READ_WRITE,
+        NvOsMemAttribute_Uncached, (void **)&VirtAddr);
+    if (e != NvSuccess)
+    {
+        NV_DEBUG_PRINTF(("APB misc aperture map failure\n"));
+        return;
+    }
+
+    /* chip id is in the misc aperture */
+    reg = NV_READ32( VirtAddr + APB_MISC_GP_HIDREV_0 );
+    id->Id = (NvU16)NV_DRF_VAL( APB_MISC_GP, HIDREV, CHIPID, reg );
+    id->Major = (NvU8)NV_DRF_VAL( APB_MISC_GP, HIDREV, MAJORREV, reg );
+    id->Minor = (NvU8)NV_DRF_VAL( APB_MISC_GP, HIDREV, MINORREV, reg );
+
+    fam = NV_DRF_VAL( APB_MISC_GP, HIDREV, HIDFAM, reg );
+    switch( fam ) {
+    case APB_MISC_GP_HIDREV_0_HIDFAM_GPU:
+        id->Family = NvRmChipFamily_Gpu;
+        s = "GPU";
+        break;
+    case APB_MISC_GP_HIDREV_0_HIDFAM_HANDHELD:
+        id->Family = NvRmChipFamily_Handheld;
+        s = "Handheld";
+        break;
+    case APB_MISC_GP_HIDREV_0_HIDFAM_BR_CHIPS:
+        id->Family = NvRmChipFamily_BrChips;
+        s = "BrChips";
+        break;
+    case APB_MISC_GP_HIDREV_0_HIDFAM_CRUSH:
+        id->Family = NvRmChipFamily_Crush;
+        s = "Crush";
+        break;
+    case APB_MISC_GP_HIDREV_0_HIDFAM_MCP:
+        id->Family = NvRmChipFamily_Mcp;
+        s = "MCP";
+        break;
+    case APB_MISC_GP_HIDREV_0_HIDFAM_CK:
+        id->Family = NvRmChipFamily_Ck;
+        s = "Ck";
+        break;
+    case APB_MISC_GP_HIDREV_0_HIDFAM_VAIO:
+        id->Family = NvRmChipFamily_Vaio;
+        s = "Vaio";
+        break;
+    case APB_MISC_GP_HIDREV_0_HIDFAM_HANDHELD_SOC:
+        id->Family = NvRmChipFamily_HandheldSoc;
+        s = "Handheld SOC";
+        break;
+    default:
+        NV_ASSERT( !"bad chip family" );
+        NvRmPhysicalMemUnmap(VirtAddr, 0x1000);
+        return;
+    }
+
+    reg = NV_READ32( VirtAddr + APB_MISC_GP_EMU_REVID_0 );
+    id->Netlist = (NvU16)NV_DRF_VAL( APB_MISC_GP, EMU_REVID, NETLIST, reg );
+    id->Patch = (NvU16)NV_DRF_VAL( APB_MISC_GP, EMU_REVID, PATCH, reg );
+
+    if( id->Major == 0 )
+    {
+        char *emu;
+        if( id->Netlist == 0 )
+        {
+            NvOsDebugPrintf( "Simulation Chip: 0x%x\n", id->Id );
+        }
+        else
+        {
+            if( id->Minor == 0 )
+            {
+                emu = "QuickTurn";
+            }
+            else
+            {
+                emu = "FPGA";
+            }
+
+            NvOsDebugPrintf( "Emulation (%s) Chip: 0x%x Netlist: 0x%x "
+                "Patch: 0x%x\n", emu, id->Id, id->Netlist, id->Patch );
+        }
+    }
+    else
+    {
+        // on real silicon
+
+        NvRmPrivGetSku( rm );
+
+        NvOsDebugPrintf( "Chip Id: 0x%x (%s) Major: 0x%x Minor: 0x%x "
+            "SKU: 0x%x\n", id->Id, s, id->Major, id->Minor, id->SKU );
+    }
+
+    // add a sanity check here, so that if we think we are on sim, but don't
+    // detect a sim/quickturn netlist bail out with an error
+    if ( NvRmIsSimulation() && id->Major != 0 )
+    {
+        // this should all get optimized away in release builds because the
+        // above will get evaluated to if ( 0 )
+        NV_ASSERT(!"invalid major version number for simulation");
+    }
+    NvRmPhysicalMemUnmap(VirtAddr, 0x1000);
+#endif
+}
+
+void
+NvRmPrivGetSku( NvRmDeviceHandle rm )
+{
+    NvError e;
+    NvRmChipId *id;
+    NvU8 *FuseVirt;
+    NvU32 reg;
+
+#if NV_USE_FUSE_CLOCK_ENABLE
+    NvU8 *CarVirt = 0;
+#endif
+
+    NV_ASSERT( rm );
+    id = &rm->ChipId;
+
+#if NV_USE_FUSE_CLOCK_ENABLE
+    // Enable fuse clock
+    e = NvRmPhysicalMemMap(0x60006000, 0x1000, NVOS_MEM_READ_WRITE,
+        NvOsMemAttribute_Uncached, (void **)&CarVirt);
+    if (e == NvSuccess)
+    {
+       reg = NV_READ32(CarVirt + CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0);
+       reg |= 0x80;
+       NV_WRITE32(CarVirt + CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0, reg);
+    }
+#endif
+
+    /* Read the fuse only on real silicon, as it was not gauranteed to be
+     * preset on the eluation/simulation platforms.
+     */
+    e = NvRmPhysicalMemMap(0x7000f800, 0x400, NVOS_MEM_READ_WRITE,
+        NvOsMemAttribute_Uncached, (void **)&FuseVirt);
+    if (e == NvSuccess)
+    {
+        // Read the SKU from the fuse module.
+        reg = NV_READ32( FuseVirt + FUSE_SKU_INFO_0 );
+        id->SKU = (NvU16)reg;
+        NvRmPhysicalMemUnmap(FuseVirt, 0x400);
+
+#if NV_USE_FUSE_CLOCK_ENABLE
+        // Disable fuse clock
+        if (CarVirt)
+        {
+            reg = NV_READ32(CarVirt + CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0);
+            reg &= ~0x80;
+            NV_WRITE32(CarVirt + CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0, reg);
+            NvRmPhysicalMemUnmap(CarVirt, 0x1000);
+        }
+#endif
+    } else
+    {
+        NV_ASSERT(!"Cannot map the FUSE aperture to get the SKU");
+        id->SKU = 0;
+    }
+}
+
+NvError
+NvRmPrivMapApertures( NvRmDeviceHandle rm )
+{
+    NvRmModuleTable *tbl;
+    NvRmModuleInstance *inst;
+    NvRmModule *mod;
+    NvU32 devid;
+    NvU32 i;
+    NvError e;
+
+    NV_ASSERT( rm );
+
+    /* loop over the instance list and map everything */
+    tbl = &rm->ModuleTable;
+    mod = tbl->Modules;
+    for( i = 0; i < NvRmPrivModuleID_Num; i++ )
+    {
+        if( mod[i].Index == NVRM_MODULE_INVALID )
+        {
+            continue;
+        }
+
+        if ((i != NvRmPrivModuleID_Ahb_Arb_Ctrl ) &&
+            (i != NvRmPrivModuleID_ApbDma ) &&
+            (i != NvRmPrivModuleID_ApbDmaChannel ) &&
+            (i != NvRmPrivModuleID_ClockAndReset ) &&
+            (i != NvRmPrivModuleID_ExternalMemoryController ) &&
+            (i != NvRmPrivModuleID_Gpio ) &&
+            (i != NvRmPrivModuleID_Interrupt ) &&
+            (i != NvRmPrivModuleID_InterruptArbGnt ) &&
+            (i != NvRmPrivModuleID_InterruptDrq ) &&
+            (i != NvRmPrivModuleID_MemoryController ) &&
+            (i != NvRmModuleID_Misc) &&
+            (i != NvRmPrivModuleID_ArmPerif) &&
+            (i != NvRmModuleID_3D) &&
+            (i != NvRmModuleID_CacheMemCtrl ) &&
+            (i != NvRmModuleID_Display) &&
+            (i != NvRmModuleID_Dvc) &&
+            (i != NvRmModuleID_FlowCtrl ) &&
+            (i != NvRmModuleID_Fuse ) &&
+            (i != NvRmModuleID_GraphicsHost ) &&
+            (i != NvRmModuleID_I2c) &&
+            (i != NvRmModuleID_Isp) &&
+            (i != NvRmModuleID_Mpe) &&
+            (i != NvRmModuleID_Pmif ) &&
+            (i != NvRmModuleID_Mipi ) &&
+            (i != NvRmModuleID_ResourceSema ) &&
+            (i != NvRmModuleID_SysStatMonitor ) &&
+            (i != NvRmModuleID_TimerUs ) &&
+            (i != NvRmModuleID_Vde ) &&
+            (i != NvRmModuleID_ExceptionVector ) &&
+            (i != NvRmModuleID_Usb2Otg ) &&
+            (i != NvRmModuleID_Vi)
+            )
+        {
+            continue;
+        }
+
+        /* FIXME If the multiple instances of the same module is adjacent to
+         * each other then we can do one allocation for all those modules.
+         */
+
+        /* map all of the device instances */
+        inst = tbl->ModInst + mod[i].Index;
+        devid = inst->DeviceId;
+        while( devid == inst->DeviceId )
+        {
+            /* If this is a device that actually has an aperture... */
+            if (inst->PhysAddr)
+            {
+                e = NvRmPhysicalMemMap(
+                        inst->PhysAddr, inst->Length, NVOS_MEM_READ_WRITE,
+                        NvOsMemAttribute_Uncached, &inst->VirtAddr);
+                if (e != NvSuccess)
+                {
+                    NV_DEBUG_PRINTF(("Device %d at physical addr 0x%X has no "
+                        "virtual mapping\n", devid, inst->PhysAddr));
+                    return e;
+                }
+            }
+
+            inst++;
+        }
+    }
+
+    return NvSuccess;
+}
+
+void
+NvRmPrivUnmapApertures( NvRmDeviceHandle rm )
+{
+    NvRmModuleTable *tbl;
+    NvRmModuleInstance *inst;
+    NvRmModule *mod;
+    NvU32 devid;
+    NvU32 i;
+
+    NV_ASSERT( rm );
+
+    /* loop over the instance list and unmap everything */
+    tbl = &rm->ModuleTable;
+    mod = tbl->Modules;
+    for( i = 0; i < NvRmPrivModuleID_Num; i++ )
+    {
+        if( mod[i].Index == NVRM_MODULE_INVALID )
+        {
+            continue;
+        }
+
+        /* map all of the device instances */
+        inst = tbl->ModInst + mod[i].Index;
+        devid = inst->DeviceId;
+        while( devid == inst->DeviceId )
+        {
+            NvRmPhysicalMemUnmap( inst->VirtAddr, inst->Length );
+            inst++;
+        }
+    }
+}
+
+NvU32
+NvRmPrivGetBctCustomerOption(NvRmDeviceHandle hRm)
+{
+    if (!NvRmIsSimulation())
+    {
+        return NV_REGR(hRm, NvRmModuleID_Pmif, 0, APBDEV_PMC_SCRATCH20_0);
+    }
+    else
+    {
+        return 0;
+    }
+}
+
+NvRmChipId *
+NvRmPrivGetChipId(
+    NvRmDeviceHandle hDevice )
+{
+    return &hDevice->ChipId;
+}
+
+#if !NV_OAL
+void NvRmBasicInit(NvRmDeviceHandle * pHandle)
+{
+    NvRmDevice *rm = 0;
+    NvError err;
+    NvU32 *table = 0;
+    NvU32 BctCustomerOption = 0;
+
+    *pHandle = 0;
+    rm = NvRmPrivGetRmDeviceHandle();
+
+    if( rm->bBasicInit )
+    {
+        *pHandle = rm;
+        return; 
+    }
+
+    /* get the default configuration */
+    err = NvRmPrivGetDefaultCfg( g_CfgMap, &rm->cfg );
+    if( err != NvSuccess )
+    {
+        goto fail;
+    }
+
+    /* get the requested configuration */
+    err = NvRmPrivReadCfgVars( g_CfgMap, &rm->cfg );
+    if( err != NvSuccess )
+    {
+        goto fail;
+    }
+
+    /* Read the chip Id and store in the Rm structure. */
+    NvRmPrivReadChipId( rm );
+
+    // init the module control (relocation table, resets, etc.)
+    table = NvRmPrivGetRelocationTable( rm );
+    if( !table )
+    {
+        goto fail;
+    }
+
+    err = NvRmPrivModuleInit( &rm->ModuleTable, table );
+    if( err != NvSuccess )
+    {
+        goto fail;
+    }
+
+    NvRmPrivMemoryInfo( rm );
+
+    // setup the hw apertures
+    err = NvRmPrivMapApertures( rm );
+    if( err != NvSuccess )
+    {
+        goto fail;
+    }
+
+    BctCustomerOption = NvRmPrivGetBctCustomerOption(rm);
+    err = NvRmPrivInitKeyList(rm, &BctCustomerOption, 1);
+    if (err != NvSuccess)
+    {
+        goto fail;
+    }
+
+    // Now populate the logical interrupt table.
+    NvRmPrivInterruptTableInit( rm );
+
+    rm->bBasicInit = NV_TRUE;
+    // basic init is a super-set of preinit
+    rm->bPreInit = NV_TRUE;
+    *pHandle = rm;
+
+fail:
+    return;
+}
+
+void
+NvRmBasicClose(NvRmDeviceHandle handle)
+{
+    if (!NVOS_IS_WINDOWS_X86)
+    {
+        NvRmPrivDeInitKeyList(handle);
+        /* unmap the apertures */
+        NvRmPrivUnmapApertures( handle );
+        /* deallocate the instance table */
+        NvRmPrivModuleDeinit( &handle->ModuleTable );
+    }
+}
+#endif
diff --git a/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_interrupt.c b/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_interrupt.c
new file mode 100644
index 000000000000..db6c1beb2d66
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_interrupt.c
@@ -0,0 +1,314 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include "nvos.h"
+#include "nvrm_module.h"
+#include "nvrm_interrupt.h"
+#include "nvrm_processor.h"
+#include "nvassert.h"
+#include "nvrm_relocation_table.h"
+#include "nvrm_chiplib.h"
+#include "nvrm_hwintf.h"
+#include "nvrm_drf.h"
+#include "nvrm_structure.h"
+#include "ap15rm_private.h"
+#include "ap15/arictlr.h"
+
+#define NVRM_ENABLE_PRINTF          0  // Module debug: 0=disable, 1=enable
+
+#if (NV_DEBUG && NVRM_ENABLE_PRINTF)
+#define NVRM_INTERRUPT_PRINTF(x)   NvOsDebugPrintf x
+#else
+#define NVRM_INTERRUPT_PRINTF(x)
+#endif
+
+//-----------------------------------------------------------------------------
+// Register access macros
+//-----------------------------------------------------------------------------
+
+#define NV_INTR_REGR(rm,inst,reg)              NV_REGR(rm, NvRmPrivModuleID_Interrupt, inst, ICTLR_##reg##_0)
+#define NV_INTR_REGW(rm,inst,reg,data)         NV_REGW(rm, NvRmPrivModuleID_Interrupt, inst, ICTLR_##reg##_0, data)
+
+#define NV_REGA(rm, aperture, instance, offset) \
+    ((volatile void*)((NvUPtr)(((rm)->ModuleTable.ModInst + (rm)->ModuleTable.Modules[(aperture)].Index + (instance))->VirtAddr) + (offset)))
+
+#define NV_INTR_REG_READ(pIntr, reg)    NV_READ32((((NvUPtr)(pIntr)) + ICTLR_##reg##_0))
+
+NvRmIntrDecoder gs_Ap15PrimaryDecoder =
+    /* AP15 Primary interrupt controller */
+    {NvRmPrivModuleID_Interrupt,
+        NVRM_IRQS_PER_INTR_CTLR, 0, {0}, {0}, {0} };
+
+NvRmIntrDecoder gs_Ap20PrimaryDecoder =
+    /* AP20 Primary interrupt controller */
+    {NvRmPrivModuleID_ArmPerif,
+        NVRM_IRQS_PER_INTR_CTLR * 5, 0, {0}, {0}, {0} };
+
+
+NvRmIntrDecoder *gs_PrimaryDecoder = &gs_Ap15PrimaryDecoder;
+
+NvRmIntrDecoder gs_SubDecoder[] =
+{
+    /* Secondary interrupt controllers */
+
+    /* Secondary interrupt controller for APB DMA */
+    {NvRmPrivModuleID_ApbDma,
+        NVRM_MAX_DMA_CHANNELS, 0, {0}, {0}, {0}},
+
+    /* GPIO secondary interrupt controller */
+    {NvRmPrivModuleID_Gpio,
+        NVRM_IRQS_PER_GPIO_CTLR, 0, {0}, {0}, {0}},
+};
+
+
+
+static NvU16
+NvRmPrivSubControllerInit(
+    NvRmDeviceHandle hRmDevice,
+    NvRmIntrDecoderHandle pDecoder,
+    NvU16 Irq)
+{
+    NvRmModuleInstance  *inst;      // Pointer to the module instance
+    NvU8                num;        // Number of instances/loop index
+    NvU32               devid;      // Hardware device id
+    NvError             e;
+
+    NV_ASSERT( hRmDevice );
+
+    NV_CHECK_ERROR_CLEANUP( NvRmPrivGetModuleInstance( hRmDevice, 
+        pDecoder->ModuleID, &inst) );
+    NV_ASSERT(inst != NULL);
+
+    num = 0;
+    devid = inst->DeviceId;
+    /* Get all the instances of that sub-controller */
+    while ( devid == inst->DeviceId )
+    {
+        NV_ASSERT( inst->IrqMap != NULL );
+        NV_ASSERT( num < NVRM_MAX_INSTANCES);
+
+        /* For modules which are sub-interrupt controllers, IRQ value in the
+         * IrqMap[0] represents the IRQ of the main interrupt controller. Sub
+         * IRQs for that controller can be computed from IndexMax and IndexBase
+         * members */
+        inst->IrqMap->IndexMax  = pDecoder->SubIrqCount;
+        inst->IrqMap->IndexBase = Irq;
+
+        pDecoder->MainIrq[num] = inst->IrqMap->Irq[0];
+        pDecoder->SubIrqFirst[num] = Irq;
+        pDecoder->SubIrqLast[num]  = Irq + pDecoder->SubIrqCount - 1;
+
+        Irq += pDecoder->SubIrqCount;
+        inst++;
+        num++;
+    }
+    pDecoder->NumberOfInstances = num;
+
+    return Irq;
+fail:
+    NV_ASSERT(!"Invalid ModuleID or Instance in ap15rm_interrupt");
+    return 0;
+}
+
+static
+NvU16 NvRmPrivMainControllerInit(NvRmDeviceHandle hRmDevice,
+    NvRmIntrDecoder *pDecoder)
+{
+    NvRmModuleInstance  *inst;  // Pointer to the module instance
+    NvU32 num = 0;
+    NvU16 irq = 0;  // Primary controller will start with IRQ 0.
+    NvU16 devid;
+    NvError e;
+    
+    NV_CHECK_ERROR_CLEANUP(
+        NvRmPrivGetModuleInstance( hRmDevice, pDecoder->ModuleID, &inst)
+    );
+
+    NV_ASSERT(inst != NULL);
+    devid = inst->DeviceId;
+
+    while( devid == inst->DeviceId )
+    {
+        pDecoder->SubIrqFirst[num] = irq;
+        pDecoder->SubIrqLast[num] = irq + pDecoder->SubIrqCount - 1;
+        pDecoder->MainIrq[num] = NVRM_IRQ_INVALID;
+
+        irq += pDecoder->SubIrqCount;
+        num++;
+        inst++;
+    }
+
+    pDecoder->NumberOfInstances = num;
+    return irq;
+fail:
+    NV_ASSERT(!"Invalid ModuleID or Instance in ap15rm_interrupt");
+    return 0;
+}
+
+void NvRmPrivInterruptTableInit( NvRmDeviceHandle hRmDevice )
+{
+    NvU16 irq;
+    NvU32 subDecoder;
+
+    NV_ASSERT( hRmDevice );
+
+    NVRM_CAP_CLEAR(hRmDevice,  NvRmCaps_HasFalconInterruptController);
+    NVRM_CAP_CLEAR(hRmDevice,  NvRmCaps_Has128bitInterruptSerializer);
+
+    // WARNING: the falcon interrupt controller is not in simulation!
+    if( NvRmIsSimulation() == NV_FALSE && hRmDevice->ChipId.Id >= 0x20)
+    {
+        NVRM_CAP_SET(hRmDevice,  NvRmCaps_HasFalconInterruptController);
+
+        if (hRmDevice->ChipId.Major == 0
+        &&  hRmDevice->ChipId.Netlist != 0
+        &&  hRmDevice->ChipId.Minor != 0 )
+        {
+            /* PALAU has 128-bit interrupt serializer and needs some WARs to
+             * compensate for the delays in interrupt arrival at interrupt
+             * controller */
+            NVRM_CAP_SET(hRmDevice,  NvRmCaps_Has128bitInterruptSerializer);
+        }
+    }
+
+    if (!NVRM_IS_CAP_SET(hRmDevice, NvRmCaps_HasFalconInterruptController))
+    {
+        gs_PrimaryDecoder = &gs_Ap15PrimaryDecoder;
+    }
+    else
+    {
+        gs_PrimaryDecoder = &gs_Ap20PrimaryDecoder;
+    }
+
+    irq = NvRmPrivMainControllerInit(hRmDevice, gs_PrimaryDecoder);
+
+    subDecoder = NV_ARRAY_SIZE(gs_SubDecoder);
+    while (subDecoder)
+    {
+        subDecoder --;
+        irq = NvRmPrivSubControllerInit(hRmDevice,
+             &(gs_SubDecoder[subDecoder]), irq);
+    }
+
+    hRmDevice->MaxIrqs = irq;
+    NVRM_INTERRUPT_PRINTF(("MAX IRQs: %d\n", irq));
+}
+
+NvU32 NvRmGetIrqForLogicalInterrupt(
+    NvRmDeviceHandle hRmDevice,
+    NvRmModuleID ModuleID,
+    NvU32 Index)
+{
+    NvRmModuleInstance* inst = NULL;       // Pointer to module instance
+    NvRmModuleIrqMap*   pIrqMap;    // Pointer to module IRQ map
+    NvU16 irq = 0;
+    NvError e;
+    NV_ASSERT( hRmDevice );
+
+
+    NV_CHECK_ERROR_CLEANUP( NvRmPrivGetModuleInstance( hRmDevice, 
+        ModuleID, &inst) );
+    if ( inst == NULL || inst->IrqMap == NULL)
+    {
+        // NV_ASSERT(!"Illegal call\n");
+        // Is this legal? Some clients like NVBL
+        // is calling this API blindly as they don't know if this module
+        // supports interrupt or not. I don't know if this good or bad. Why
+        // would a clinet request IRQ, if they know the underying module
+        // doesn'tsupport interrupts.
+        return NVRM_IRQ_INVALID;
+    }
+
+    pIrqMap = inst->IrqMap;
+
+    /* Check if this the interrupt for this module is routed to secondary
+     * interrupt controller or to the main controller */
+    /* FIXME rename IndexMax and IndexBase variables to SubInterruptCount and
+     * SubInterruptBase */
+    if (pIrqMap->IndexMax == 0)
+    {
+        NV_ASSERT (Index < pIrqMap->IrqCount);
+        NV_ASSERT(pIrqMap->Irq[Index] != NVRM_IRQ_INVALID);
+
+        irq = pIrqMap->Irq[Index];
+    }
+    /* Secondary interrupt controller */
+    else
+    {
+        // Requesting controller's main interrupt? This is a hack used by the
+        // OAL to get the main IRQ line for the sub-deocders. OAL builds a list
+        // of all the main IRQs for the sub-decoders and asserts if someone
+        // tries to register an interrupt handler for the main IRQ line.
+        if (Index == 0xFF)
+        {
+            NV_ASSERT (pIrqMap->Irq[0] != NVRM_IRQ_INVALID);
+            irq = pIrqMap->Irq[0];
+        } else
+        {
+            /* Index cannot be more than the Max IRQs registered by that
+             * secondary interrupt controller */
+            NV_ASSERT( Index < pIrqMap->IndexMax );
+            irq = pIrqMap->IndexBase + Index;
+        }
+    }
+    return irq;
+fail:
+    NV_ASSERT(!"Invalid ModuleID or Instance in ap15rm_interrupt");
+    return 0;
+}
+
+NvU32 NvRmGetIrqCountForLogicalInterrupt(
+    NvRmDeviceHandle hRmDevice,
+    NvRmModuleID ModuleID)
+{
+    NvRmModuleInstance *inst = NULL;
+    NvError e;
+    
+    NV_ASSERT( hRmDevice );
+
+    NV_CHECK_ERROR_CLEANUP( NvRmPrivGetModuleInstance( hRmDevice, 
+        ModuleID, &inst) );
+    if ( inst == NULL || inst->IrqMap == NULL)
+    {
+        // NV_ASSERT(!"Illegal call\n");
+        // Is this legal? Some clients like NVBL are calling this API blindly
+        // as they don't know if this module supports interrupt or not.
+        // I don't know if this good or bad. Why would a clinet request IRQ,
+        // if they know the underying module doesn't support interrupts.
+        return 0;
+    }
+
+    return inst->IrqMap->IrqCount;
+fail:
+    NV_ASSERT(!"Invalid ModuleID or Instance in ap15rm_interrupt");
+    return 0;
+}
diff --git a/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_interrupt_generic.c b/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_interrupt_generic.c
new file mode 100644
index 000000000000..e3d6bead5a9f
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_interrupt_generic.c
@@ -0,0 +1,86 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include "nvos.h"
+#include "ap15rm_private.h"
+#include "nvrm_interrupt.h"
+
+NvError NvRmInterruptRegister(
+    NvRmDeviceHandle hRmDevice,
+    NvU32 IrqListSize,
+    const NvU32 *pIrqList,
+    const NvOsInterruptHandler *pIrqHandlerList,
+    void *context,
+    NvOsInterruptHandle *handle,
+    NvBool InterruptEnable)
+{
+    NvError err;
+
+    err = NvOsInterruptRegister(IrqListSize,
+            pIrqList,
+            pIrqHandlerList,
+            context,
+            handle,
+            InterruptEnable);
+
+    return err;
+}
+
+void NvRmInterruptUnregister(
+    NvRmDeviceHandle hRmDevice,
+    NvOsInterruptHandle handle)
+{
+    NvOsInterruptUnregister( handle );
+}
+
+NvError NvRmInterruptEnable(
+    NvRmDeviceHandle hRmDevice,
+    NvOsInterruptHandle handle)
+{
+    return NvOsInterruptEnable(handle);
+}
+
+void NvRmInterruptDone( NvOsInterruptHandle handle )
+{
+    NvOsInterruptDone( handle );
+}
+
+void NvRmPrivInterruptStart(NvRmDeviceHandle hRmDevice)
+{
+    return;
+}
+
+void NvRmPrivInterruptShutdown(NvRmDeviceHandle handle)
+{
+    return;
+}
+
diff --git a/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_memctrl.c b/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_memctrl.c
new file mode 100644
index 000000000000..e5da471f42a8
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_memctrl.c
@@ -0,0 +1,611 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include "nvrm_init.h"
+#include "nvassert.h"
+#include "nvos.h"
+#include "nvrm_module.h"
+#include "ap15/aremc.h"
+#include "ap15/armc.h"
+#include "ap15/arapb_misc.h"
+#include "ap15rm_private.h"
+#include "nvrm_drf.h"
+#include "nvrm_hwintf.h"
+#include "nvrm_memctrl.h"
+#include "nvrm_clocks.h"
+#include "nvrm_structure.h"
+#include "nvrm_arm_cp.h"
+#include "nvrm_processor.h"
+
+//define obs_struct
+typedef struct ObsInfoRec
+{
+  NvRmModuleID modSelect;
+  NvU32 partSelect;
+} ObsInfo;
+
+#define OBS_INFO_FIELD(modID, partition) \
+    { \
+    NvRmModuleID_##modID, \
+    APB_MISC_GP_OBSCTRL_0_OBS_PART_SEL_##partition \
+    }
+
+// static table correspond to enum NvRmModuleID in \include\nvrm_module.idl    
+// Expand this table to add more moduleID - partition map entries. 
+static const ObsInfo ObsInfoTable[] =
+{
+  OBS_INFO_FIELD(Cpu, CPU),
+  OBS_INFO_FIELD(Display, DIS),
+  OBS_INFO_FIELD(Csi, DIS),
+  OBS_INFO_FIELD(Hdmi, DIS),
+  OBS_INFO_FIELD(Tvo, DIS),
+  OBS_INFO_FIELD(Dsi, DIS),
+  OBS_INFO_FIELD(2D, GR),
+  OBS_INFO_FIELD(Fuse, GR),
+  OBS_INFO_FIELD(Vde, VDE),
+  OBS_INFO_FIELD(Isp, VE)
+};
+
+static const NvU32 ObsInfoTableSize =
+    NV_ARRAY_SIZE(ObsInfoTable);
+
+
+static void
+McStatAp1x_Start(
+        NvRmDeviceHandle rm,
+        NvU32 client_id_0,
+        NvU32 client_id_1,
+        NvU32 llc_client_id)
+{
+    NvU32 emc_ctrl = 
+      (AREMC_STAT_CONTROL_MODE_BANDWIDTH << AREMC_STAT_CONTROL_MODE_SHIFT) |
+      (AREMC_STAT_CONTROL_EVENT_QUALIFIED << AREMC_STAT_CONTROL_EVENT_SHIFT) |
+      (AREMC_STAT_CONTROL_CLIENT_TYPE_CMCR << 
+         AREMC_STAT_CONTROL_CLIENT_TYPE_SHIFT) |  // default is CMC Read client
+      (AREMC_STAT_CONTROL_FILTER_CLIENT_ENABLE << 
+         AREMC_STAT_CONTROL_FILTER_CLIENT_SHIFT) |
+      (AREMC_STAT_CONTROL_FILTER_ADDR_DISABLE << 
+         AREMC_STAT_CONTROL_FILTER_ADDR_SHIFT);
+    
+    NvU32 mc_filter_client_0 = (ARMC_STAT_CONTROL_FILTER_CLIENT_ENABLE <<
+                   ARMC_STAT_CONTROL_FILTER_CLIENT_SHIFT);
+
+    NvU32 mc_filter_client_1 = (ARMC_STAT_CONTROL_FILTER_CLIENT_ENABLE <<
+                   ARMC_STAT_CONTROL_FILTER_CLIENT_SHIFT);
+
+    if (client_id_0 == 0xffffffff)
+    {
+        mc_filter_client_0 = (ARMC_STAT_CONTROL_FILTER_CLIENT_DISABLE <<
+                   ARMC_STAT_CONTROL_FILTER_CLIENT_SHIFT);
+        client_id_0 = 0;
+    }
+
+    if (client_id_1 == 0xffffffff)
+    {
+        mc_filter_client_1 = (ARMC_STAT_CONTROL_FILTER_CLIENT_DISABLE <<
+                   ARMC_STAT_CONTROL_FILTER_CLIENT_SHIFT);
+        client_id_1 = 0;
+    }
+
+    if(llc_client_id == 1)
+        emc_ctrl |= AREMC_STAT_CONTROL_CLIENT_TYPE_MPCORER << 
+                    AREMC_STAT_CONTROL_CLIENT_TYPE_SHIFT; 
+                    // overwrite with MPCore read
+        NV_REGW(rm, NvRmPrivModuleID_ExternalMemoryController, 
+                0, EMC_STAT_CONTROL_0, 
+                NV_DRF_DEF(EMC, STAT_CONTROL, LLMC_GATHER,DISABLE));
+        NV_REGW(rm, NvRmPrivModuleID_ExternalMemoryController, 
+                0, EMC_STAT_LLMC_CLOCK_LIMIT_0, 0xffffffff);
+        NV_REGW(rm, NvRmPrivModuleID_ExternalMemoryController, 
+                0, EMC_STAT_LLMC_CONTROL_0_0, emc_ctrl);
+        NV_REGW(rm, NvRmPrivModuleID_ExternalMemoryController, 
+                0, EMC_STAT_CONTROL_0, 
+                NV_DRF_DEF(EMC, STAT_CONTROL, LLMC_GATHER, CLEAR));
+        NV_REGW(rm, NvRmPrivModuleID_ExternalMemoryController,
+                0, EMC_STAT_CONTROL_0, 
+                NV_DRF_DEF(EMC, STAT_CONTROL, LLMC_GATHER, ENABLE));
+        NV_REGW(rm, NvRmPrivModuleID_MemoryController,
+                0, MC_STAT_CONTROL_0, 
+                NV_DRF_DEF(MC, STAT_CONTROL, EMC_GATHER, DISABLE));
+        NV_REGW(rm, NvRmPrivModuleID_MemoryController,
+                0, MC_STAT_EMC_CLOCK_LIMIT_0, 0xffffffff);
+        NV_REGW(rm, NvRmPrivModuleID_MemoryController,
+                0, MC_STAT_EMC_CONTROL_0_0,
+                (ARMC_STAT_CONTROL_MODE_BANDWIDTH << 
+                   ARMC_STAT_CONTROL_MODE_SHIFT) |
+                (client_id_0 << ARMC_STAT_CONTROL_CLIENT_ID_SHIFT) |
+                (ARMC_STAT_CONTROL_EVENT_QUALIFIED << 
+                   ARMC_STAT_CONTROL_EVENT_SHIFT) |
+                mc_filter_client_0 |
+                (ARMC_STAT_CONTROL_FILTER_ADDR_DISABLE << 
+                   ARMC_STAT_CONTROL_FILTER_ADDR_SHIFT) |
+                (ARMC_STAT_CONTROL_FILTER_PRI_DISABLE <<
+                   ARMC_STAT_CONTROL_FILTER_PRI_SHIFT) |
+                (ARMC_STAT_CONTROL_FILTER_COALESCED_DISABLE << 
+                   ARMC_STAT_CONTROL_FILTER_COALESCED_SHIFT));
+        NV_REGW(rm, NvRmPrivModuleID_MemoryController,
+                0, MC_STAT_EMC_CONTROL_1_0,
+                (ARMC_STAT_CONTROL_MODE_BANDWIDTH <<
+                   ARMC_STAT_CONTROL_MODE_SHIFT) |
+                (client_id_1 << ARMC_STAT_CONTROL_CLIENT_ID_SHIFT) |
+                (ARMC_STAT_CONTROL_EVENT_QUALIFIED <<
+                   ARMC_STAT_CONTROL_EVENT_SHIFT) |
+                mc_filter_client_1 |
+                (ARMC_STAT_CONTROL_FILTER_ADDR_DISABLE <<
+                   ARMC_STAT_CONTROL_FILTER_ADDR_SHIFT) |
+                (ARMC_STAT_CONTROL_FILTER_PRI_DISABLE <<
+                   ARMC_STAT_CONTROL_FILTER_PRI_SHIFT) |
+                (ARMC_STAT_CONTROL_FILTER_COALESCED_DISABLE <<
+                   ARMC_STAT_CONTROL_FILTER_COALESCED_SHIFT));
+
+        NV_REGW(rm, NvRmPrivModuleID_MemoryController,
+                0, MC_STAT_CONTROL_0, 
+                NV_DRF_DEF(MC, STAT_CONTROL, EMC_GATHER, CLEAR));
+        NV_REGW(rm, NvRmPrivModuleID_MemoryController, 
+                0, MC_STAT_CONTROL_0,
+                NV_DRF_DEF(MC, STAT_CONTROL, EMC_GATHER, ENABLE));
+}
+
+void
+McStat_Start(
+        NvRmDeviceHandle rm,
+        NvU32 client_id_0,
+        NvU32 client_id_1,
+        NvU32 llc_client_id)
+{
+    switch (rm->ChipId.Id)
+    {
+        case 0x15:
+        case 0x16:
+            McStatAp1x_Start(rm, client_id_0, client_id_1, llc_client_id);
+            break;
+        case 0x20:
+            McStatAp20_Start(rm, client_id_0, client_id_1, llc_client_id);
+            break;
+        default:
+            NV_ASSERT(!"Unsupported chip ID");
+            break;
+    }
+}
+
+static void
+McStatAp1x_Stop(
+        NvRmDeviceHandle rm,
+        NvU32 *client_0_cycles,
+        NvU32 *client_1_cycles,
+        NvU32 *llc_client_cycles,
+        NvU32 *llc_client_clocks,
+        NvU32 *mc_clocks)
+{
+    *llc_client_cycles = NV_REGR(rm, NvRmPrivModuleID_ExternalMemoryController, 
+                           0, EMC_STAT_LLMC_COUNT_0_0);
+    *llc_client_clocks = NV_REGR(rm, NvRmPrivModuleID_ExternalMemoryController, 
+                           0, EMC_STAT_LLMC_CLOCKS_0);
+    *client_0_cycles = NV_REGR(rm, NvRmPrivModuleID_MemoryController, 
+                         0, MC_STAT_EMC_COUNT_0_0);
+    *client_1_cycles = NV_REGR(rm, NvRmPrivModuleID_MemoryController,
+                         0, MC_STAT_EMC_COUNT_1_0);
+    *mc_clocks = NV_REGR(rm, NvRmPrivModuleID_MemoryController, 
+                   0, MC_STAT_EMC_CLOCKS_0);
+}
+
+void
+McStat_Stop(
+        NvRmDeviceHandle rm,
+        NvU32 *client_0_cycles,
+        NvU32 *client_1_cycles,
+        NvU32 *llc_client_cycles,
+        NvU32 *llc_client_clocks,
+        NvU32 *mc_clocks)
+{
+    switch (rm->ChipId.Id)
+    {
+        case 0x15:
+        case 0x16:
+            McStatAp1x_Stop(rm, client_0_cycles, client_1_cycles, llc_client_cycles, llc_client_clocks, mc_clocks );
+            break;
+        case 0x20:
+            McStatAp20_Stop(rm, client_0_cycles, client_1_cycles, llc_client_cycles, llc_client_clocks, mc_clocks );
+            break;
+        default:
+            NV_ASSERT(!"Unsupported chip ID");
+            break;
+    }
+}
+
+
+void
+McStat_Report(
+        NvU32 client_id_0,
+        NvU32 client_0_cycles,
+        NvU32 client_id_1,
+        NvU32 client_1_cycles,
+        NvU32 llc_client_id,
+        NvU32 llc_client_clocks,
+        NvU32 llc_client_cycles,
+        NvU32 mc_clocks)
+{
+    NvOsDebugPrintf("LLC Client %d Count:  0x%.8X, %u\n", 
+      llc_client_id, llc_client_cycles, llc_client_cycles);
+    NvOsDebugPrintf("LLC Client %d Clocks: 0x%.8X, %u\n",
+      llc_client_id, llc_client_clocks, llc_client_clocks);
+    NvOsDebugPrintf("Client %.3d Count: 0x%.8X, %u\n",
+      client_id_0, client_0_cycles, client_0_cycles);
+    NvOsDebugPrintf("Client %.3d Count: 0x%.8X, %u\n",
+      client_id_1, client_1_cycles, client_1_cycles);
+    NvOsDebugPrintf("Total MC Clocks:   0x%.8X, %u\n", mc_clocks, mc_clocks);
+}
+
+//API to read data from OBS bus
+// The OBS_PART_SEL is mapped to the specified modID by obsInfoTable which is public in this file. 
+
+NvError
+ReadObsData(
+        NvRmDeviceHandle rm,
+        NvRmModuleID modID,
+        NvU32 start_index,
+        NvU32 length,
+        NvU32 *value)
+{
+    NvU32 i = 0, offset = 0, value1, value2;
+    NvU32 timeout;
+    NvU32 partID = 0xffffffff;
+    NvU32 index, temp;
+
+    for (i = 0; i < ObsInfoTableSize; i++)
+    {
+        if (modID == ObsInfoTable[i].modSelect)
+        {
+        partID = ObsInfoTable[i].partSelect;
+        break;
+        }
+    }
+    if (i == ObsInfoTableSize)
+    {  
+        return NvError_BadParameter;
+    }
+
+    for(offset = 0; offset < length; offset++)
+    {
+        index = start_index + offset;
+        temp = NV_DRF_DEF(APB_MISC_GP, OBSCTRL, OBS_EN, ENABLE) | 
+            NV_DRF_NUM(APB_MISC_GP, OBSCTRL, OBS_MOD_SEL, modID) | 
+            NV_DRF_NUM(APB_MISC_GP, OBSCTRL, OBS_PART_SEL, partID) | 
+            NV_DRF_NUM(APB_MISC_GP, OBSCTRL, OBS_SIG_SEL, index) ;
+        NV_REGW(rm, NvRmModuleID_Misc, 0, APB_MISC_GP_OBSCTRL_0, temp);
+        value1 = NV_REGR(rm, NvRmModuleID_Misc, 0, APB_MISC_GP_OBSCTRL_0);
+        timeout = 100;
+        do {
+            value2 = value1;
+            value1 = NV_REGR(rm, NvRmModuleID_Misc, 0, APB_MISC_GP_OBSDATA_0);
+            timeout --;
+        } while (value1 != value2 && timeout);
+        NvOsDebugPrintf("OBS bus modID 0x%x index 0x%x = value 0x%x", 
+                modID, index, value1);
+        value[offset] = value1;
+    }
+    return NvSuccess;
+}
+
+/******************************************************************************/
+
+#define NVRM_AP15_MONITORED_EVENTS_MAX (2)
+
+// AP15 CP15 performance monitor control register layout
+#define AP15_CP15_PMNC_0_ENABLE_RANGE           0:0
+#define AP15_CP15_PMNC_0_EVENT_CNTS_RESET_RANGE 1:1
+#define AP15_CP15_PMNC_0_CYCLE_CNT_RESET_RANGE  2:2
+#define AP15_CP15_PMNC_0_EVENT0_CNT_OV_RANGE    8:8
+#define AP15_CP15_PMNC_0_EVENT1_CNT_OV_RANGE    9:9
+#define AP15_CP15_PMNC_0_CYCLE_CNT_OV_RANGE     10:10
+#define AP15_CP15_PMNC_0_EVENT0_RANGE           19:12
+#define AP15_CP15_PMNC_0_EVENT1_RANGE           27:20
+
+static void Ap15CorePerfMonDisable(void)
+{
+    // Disable all performance counters
+    NvU32 RegValue = NV_DRF_NUM(AP15_CP15, PMNC, ENABLE, 0);
+    MCR(p15, 0, RegValue, c15, c12, 0);
+}
+
+static NvError Ap15CorePerfMonCheckStatus(void)
+{
+    // Check if performance counters are enabled and no overflow has occurred
+    NvU32 RegValue;
+    MRC(p15, 0, RegValue, c15, c12, 0);
+    if ((NV_DRF_VAL(AP15_CP15, PMNC, ENABLE, RegValue) == 0) ||
+        (NV_DRF_VAL(AP15_CP15, PMNC, CYCLE_CNT_OV, RegValue) == 1) ||
+        (NV_DRF_VAL(AP15_CP15, PMNC, EVENT0_CNT_OV, RegValue) == 1) ||
+        (NV_DRF_VAL(AP15_CP15, PMNC, EVENT1_CNT_OV, RegValue) == 1))
+        return NvError_InvalidState;
+    else
+        return NvSuccess;
+}
+
+static void Ap15CorePerfMonStart(NvU32* pEventList, NvU32* pEventListSize)
+{
+    NvU32 RegValue, Event0, Event1;
+
+    // Just return maximum monitored events if no input list, otherwise
+    // get both events ready (set the same if only one specified)
+    if (*pEventListSize == 0)
+    {
+        *pEventListSize = NVRM_AP15_MONITORED_EVENTS_MAX;
+        return;
+    }
+    Event0 = Event1 = pEventList[0];
+    if (*pEventListSize >= NVRM_AP15_MONITORED_EVENTS_MAX)
+    {
+        Event1 = pEventList[1];
+        *pEventListSize = NVRM_AP15_MONITORED_EVENTS_MAX;
+    }
+
+    // Reset, clear overflow flags and enable 3 performance counters:
+    // total cycle counter and 2 event counters
+    RegValue =
+        NV_DRF_NUM(AP15_CP15, PMNC, ENABLE, 1) |
+        NV_DRF_NUM(AP15_CP15, PMNC, EVENT_CNTS_RESET, 1) |
+        NV_DRF_NUM(AP15_CP15, PMNC, CYCLE_CNT_RESET, 1) |
+        NV_DRF_NUM(AP15_CP15, PMNC, CYCLE_CNT_OV, 1) |
+        NV_DRF_NUM(AP15_CP15, PMNC, EVENT0_CNT_OV, 1) |
+        NV_DRF_NUM(AP15_CP15, PMNC, EVENT1_CNT_OV, 1) |
+        NV_DRF_NUM(AP15_CP15, PMNC, EVENT0, Event0) |
+        NV_DRF_NUM(AP15_CP15, PMNC, EVENT1, Event1);
+    MCR(p15, 0, RegValue, c15, c12, 0);
+}
+
+static NvError Ap15CorePerfMonStop(
+    NvU32* pCountListSize,
+    NvU32* pCountList,
+    NvU32* pTotalCycleCount)
+{
+    NvU32 ccnt, pmn0, pmn1;
+
+    // Disable monotors and check status
+    NvError err = Ap15CorePerfMonCheckStatus();
+    Ap15CorePerfMonDisable();
+    if (err != NvSuccess)
+        return err;
+
+    // Read back cycle and event counters
+    MRC(p15, 0, ccnt, c15, c12, 1);
+    MRC(p15, 0, pmn0, c15, c12, 2);
+    MRC(p15, 0, pmn1, c15, c12, 3);
+
+    // Return total cycle count always, and event counts depending on
+    // the room provided by the caller
+    *pTotalCycleCount = ccnt;
+    if (*pCountListSize == 0)
+        return NvSuccess;
+
+    pCountList[0] = pmn1;       // ARM spec Event0 <=> Counter 1 (not a typo)
+    if (*pCountListSize >= NVRM_AP15_MONITORED_EVENTS_MAX)
+    {
+        pCountList[1] = pmn0;   // ARM spec Event1 <=> Counter 0 (not a typo)
+        *pCountListSize = NVRM_AP15_MONITORED_EVENTS_MAX;
+    }
+    return NvSuccess;
+}
+
+NvError
+NvRmCorePerfMonStart(
+    NvRmDeviceHandle hRmDevice,
+    NvU32* pEventListSize,
+    NvU32* pEventList)
+{
+    NvU32 cpst;
+    NV_ASSERT(hRmDevice);
+    NV_ASSERT(pEventListSize);
+    NV_ASSERT ((*pEventListSize == 0) || pEventList);
+
+    // Monitoring is supported only for SoC environment in one
+    // of the privileged modes
+    GET_CPSR(cpst);
+    if(IS_USER_MODE(cpst))
+        return NvError_NotSupported;
+    if (NvRmPrivGetExecPlatform(hRmDevice) != ExecPlatform_Soc)
+        return NvError_NotSupported;
+
+    switch (hRmDevice->ChipId.Id)
+    {
+        case 0x15:
+        case 0x16:
+            Ap15CorePerfMonStart(pEventList, pEventListSize);
+            return NvSuccess;
+        case 0x20:
+            return NvError_NotSupported;
+        default:
+            NV_ASSERT(!"Invalid chip ID");
+            return NvError_NotSupported;
+    }
+}
+
+NvError
+NvRmCorePerfMonStop(
+    NvRmDeviceHandle hRmDevice,
+    NvU32* pCountListSize,
+    NvU32* pCountList,
+    NvU32* pTotalCycleCount)
+{
+    NvU32 cpst;
+    NV_ASSERT(hRmDevice);
+    NV_ASSERT(pTotalCycleCount);
+    NV_ASSERT(pCountListSize);
+    NV_ASSERT ((*pCountListSize == 0) || pCountList);
+
+    // Monitoring is supported only for SoC environment in one
+    // of the privileged modes
+    GET_CPSR(cpst);
+    if(IS_USER_MODE(cpst))
+        return NvError_NotSupported;
+    if (NvRmPrivGetExecPlatform(hRmDevice) != ExecPlatform_Soc)
+        return NvError_NotSupported;
+
+    switch (hRmDevice->ChipId.Id)
+    {
+        case 0x15:
+        case 0x16:
+            return Ap15CorePerfMonStop(
+                pCountListSize, pCountList, pTotalCycleCount);
+        case 0x20:
+            return NvError_NotSupported;
+        default:
+            NV_ASSERT(!"Invalid chip ID");
+            return NvError_NotSupported;
+    }
+}
+
+static NvOsInterruptHandle s_McInterruptHandle = NULL;
+static void McErrorIntHandler(void* args)
+{
+    NvU32 RegVal;
+    NvU32 IntStatus;
+    NvU32 IntClear = 0;
+    NvRmDeviceHandle hRm = (NvRmDeviceHandle)args;
+    
+    IntStatus = NV_REGR(hRm, NvRmPrivModuleID_MemoryController, 0, MC_INTSTATUS_0);
+    if ( NV_DRF_VAL(MC, INTSTATUS, DECERR_AXI_INT, IntStatus) )
+    {
+        IntClear |= NV_DRF_DEF(MC, INTSTATUS, DECERR_AXI_INT, SET);
+        RegVal = NV_REGR(hRm, NvRmPrivModuleID_MemoryController, 0, 
+                     MC_DECERR_AXI_ADR_0);
+        NvOsDebugPrintf("AXI DecErrAddress=0x%x ", RegVal);
+        RegVal = NV_REGR(hRm, NvRmPrivModuleID_MemoryController, 0, 
+                     MC_DECERR_AXI_STATUS_0);
+        NvOsDebugPrintf("AXI DecErrStatus=0x%x ", RegVal);
+    }
+    if ( NV_DRF_VAL(MC, INTSTATUS, DECERR_EMEM_OTHERS_INT, IntStatus) )
+    {
+        IntClear |= NV_DRF_DEF(MC, INTSTATUS, DECERR_EMEM_OTHERS_INT, SET);
+        RegVal = NV_REGR(hRm, NvRmPrivModuleID_MemoryController, 0, 
+                     MC_DECERR_EMEM_OTHERS_ADR_0);
+        NvOsDebugPrintf("EMEM DecErrAddress=0x%x ", RegVal);
+        RegVal = NV_REGR(hRm, NvRmPrivModuleID_MemoryController, 0, 
+                     MC_DECERR_EMEM_OTHERS_STATUS_0);
+        NvOsDebugPrintf("EMEM DecErrStatus=0x%x ", RegVal);
+    }
+    if ( NV_DRF_VAL(MC, INTSTATUS, INVALID_GART_PAGE_INT, IntStatus) )
+    {
+        IntClear |= NV_DRF_DEF(MC, INTSTATUS, INVALID_GART_PAGE_INT, SET);
+        RegVal = NV_REGR(hRm, NvRmPrivModuleID_MemoryController, 0, 
+                     MC_GART_ERROR_ADDR_0);
+        NvOsDebugPrintf("GART DecErrAddress=0x%x ", RegVal);
+        RegVal = NV_REGR(hRm, NvRmPrivModuleID_MemoryController, 0, 
+                     MC_GART_ERROR_REQ_0);
+        NvOsDebugPrintf("GART DecErrStatus=0x%x ", RegVal);
+    }
+    
+    NV_ASSERT(!"MC Decode Error ");
+    // Clear the interrupt.
+    NV_REGW(hRm, NvRmPrivModuleID_MemoryController, 0, MC_INTSTATUS_0, IntClear);
+    NvRmInterruptDone(s_McInterruptHandle);
+}
+
+NvError NvRmPrivAp15McErrorMonitorStart(NvRmDeviceHandle hRm)
+{
+    NvU32 val;
+    NvU32 IrqList;
+    NvError e = NvSuccess;
+    NvOsInterruptHandler handler;
+    
+    if (s_McInterruptHandle == NULL)
+    {
+        // Install an interrupt handler.
+        handler = McErrorIntHandler;
+        IrqList = NvRmGetIrqForLogicalInterrupt(hRm,
+                      NvRmPrivModuleID_MemoryController, 0);
+        NV_CHECK_ERROR( NvRmInterruptRegister(hRm, 1, &IrqList,  &handler, 
+            hRm, &s_McInterruptHandle, NV_TRUE) );
+        // Enable Dec Err interrupts in memory Controller.
+        val = NV_DRF_DEF(MC, INTMASK, DECERR_AXI_INTMASK, UNMASKED) |
+              NV_DRF_DEF(MC, INTMASK, DECERR_EMEM_OTHERS_INTMASK, UNMASKED) |
+              NV_DRF_DEF(MC, INTMASK, INVALID_GART_PAGE_INTMASK, UNMASKED);
+        NV_REGW(hRm, NvRmPrivModuleID_MemoryController, 0, MC_INTMASK_0, val);
+    }
+    return e;
+}
+
+void NvRmPrivAp15McErrorMonitorStop(NvRmDeviceHandle hRm)
+{
+    NvRmInterruptUnregister(hRm, s_McInterruptHandle);
+    s_McInterruptHandle = NULL;
+}
+
+/* This function sets some performance timings for Mc & Emc.  Numbers are from
+ * the Arch team.
+ *
+ */
+void NvRmPrivAp15SetupMc(NvRmDeviceHandle hRm)
+{
+    NvU32   reg, mask;
+    reg = NV_REGR(hRm, NvRmPrivModuleID_MemoryController, 0, 
+              MC_LOWLATENCY_CONFIG_0);
+    mask = NV_DRF_DEF(MC, LOWLATENCY_CONFIG, CMCR_LL_CTRL, ENABLE) |
+           NV_DRF_DEF(MC, LOWLATENCY_CONFIG, CMCR_LL_SEND_BOTH, ENABLE) |
+           NV_DRF_DEF(MC, LOWLATENCY_CONFIG, MPCORER_LL_CTRL, ENABLE) |
+           NV_DRF_DEF(MC, LOWLATENCY_CONFIG, MPCORER_LL_SEND_BOTH, ENABLE);
+    if ( mask != (reg & mask) )
+        NV_ASSERT(!"MC LL Path not enabled!");
+
+    /* 1) TIMEOUT value for VDE is 256 cycles, 3D, 2D timeouts are disabled, all others 512 cycles. */
+    NV_REGW(hRm, NvRmPrivModuleID_MemoryController, 0, MC_TIMEOUT_CTRL_0,    0x00000028);
+    NV_REGW(hRm, NvRmPrivModuleID_MemoryController, 0, MC_TIMEOUT_CMC_0,     0x88888888);
+    NV_REGW(hRm, NvRmPrivModuleID_MemoryController, 0, MC_TIMEOUT_DC_0,      0x88888888);
+    NV_REGW(hRm, NvRmPrivModuleID_MemoryController, 0, MC_TIMEOUT_DCB_0,     0x88888888);
+    NV_REGW(hRm, NvRmPrivModuleID_MemoryController, 0, MC_TIMEOUT_EPP_0,     0x88888888);
+    NV_REGW(hRm, NvRmPrivModuleID_MemoryController, 0, MC_TIMEOUT_G2_0,      0x0);
+    NV_REGW(hRm, NvRmPrivModuleID_MemoryController, 0, MC_TIMEOUT_HC_0,      0x88888888);
+    NV_REGW(hRm, NvRmPrivModuleID_MemoryController, 0, MC_TIMEOUT_ISP_0,     0x88888888);
+    NV_REGW(hRm, NvRmPrivModuleID_MemoryController, 0, MC_TIMEOUT_MPCORE_0,  0x88888888);
+    NV_REGW(hRm, NvRmPrivModuleID_MemoryController, 0, MC_TIMEOUT_MPEA_0,    0x88888888);
+    NV_REGW(hRm, NvRmPrivModuleID_MemoryController, 0, MC_TIMEOUT_MPEB_0,    0x88888888);
+    NV_REGW(hRm, NvRmPrivModuleID_MemoryController, 0, MC_TIMEOUT_MPEC_0,    0x88888888);
+    NV_REGW(hRm, NvRmPrivModuleID_MemoryController, 0, MC_TIMEOUT_NV_0,      0x0);
+    NV_REGW(hRm, NvRmPrivModuleID_MemoryController, 0, MC_TIMEOUT_PPCS_0,    0x88888888);
+    NV_REGW(hRm, NvRmPrivModuleID_MemoryController, 0, MC_TIMEOUT_VDE_0,     0x44444444);
+    NV_REGW(hRm, NvRmPrivModuleID_MemoryController, 0, MC_TIMEOUT1_VDE_0,    0x44444444);
+    NV_REGW(hRm, NvRmPrivModuleID_MemoryController, 0, MC_TIMEOUT_VI_0,      0x88888888);
+
+    /* 2) Command Queue values should be 2,2,6 for better performance. */
+    NV_REGW(hRm, NvRmPrivModuleID_ExternalMemoryController, 0, EMC_CMDQ_0,   0x00002206);
+    
+    /* 3) MC_EMEM_ARB_CFG0_0 Should have optimal values for 166Mhz DRAM.
+     *    27:22 EMEM_BANKCNT_NSP_TH (0xC seems to be better for 166Mhz)
+     *    21:16 EMEM_BANKCNT_TH     (0x8 seems to be better for 166Mhz)
+     *
+     *    MC_EMEM_ARB_CFG0_0 <= 0x0308_1010 
+     */
+    
+    NV_REGW(hRm, NvRmPrivModuleID_MemoryController, 0, MC_EMEM_ARB_CFG0_0,    0x03081010);
+}
+
+/******************************************************************************/
diff --git a/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_pinmux.c b/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_pinmux.c
new file mode 100644
index 000000000000..0b4e65ee9f3e
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_pinmux.c
@@ -0,0 +1,398 @@
+/*
+ * Copyright (c) 2009-2010 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include "nvcommon.h"
+#include "nvrm_pinmux.h"
+#include "nvrm_drf.h"
+#include "nvassert.h"
+#include "nvrm_hwintf.h"
+#include "ap15/ap15rm_private.h"
+#include "ap15/arapb_misc.h"
+#include "nvrm_pinmux_utils.h"
+#include "ap15/ap15rm_pinmux_utils.h"
+#include "nvodm_query_pinmux.h"
+
+/*  FindConfigStart searches through an array of configuration data to find the
+ *  starting position of a particular configuration in a module instance array.
+ *  The stop position is programmable, so that sub-routines can be placed after
+ *  the last valid true configuration */
+
+const NvU32* NvRmPrivAp15FindConfigStart(
+    const NvU32* Instance,
+    NvU32 Config,
+    NvU32 EndMarker)
+{
+    NvU32 Cnt = 0;
+    while ((Cnt < Config) && (*Instance!=EndMarker))
+    {
+        switch (NV_DRF_VAL(MUX, ENTRY, STATE, *Instance))
+        {
+            case PinMuxConfig_BranchLink:
+            case PinMuxConfig_OpcodeExtend:
+                if (*Instance==CONFIGEND())
+                    Cnt++;
+                Instance++;
+                break;
+            default:
+                Instance += NVRM_PINMUX_SET_OPCODE_SIZE;
+                break;
+        }
+    }
+
+    /* Ugly postfix.  In modules with bonafide subroutines, the last
+     * configuration CONFIGEND() will be followed by a MODULEDONE()
+     * token, with the first Set/Unset/Branch of the subroutine
+     * following that.  To avoid leaving the "PC" pointing to a
+     * MODULEDONE() in the case where the first subroutine should be
+     * executed, fudge the "PC" up by one, to point to the subroutine. */
+    if (EndMarker==SUBROUTINESDONE() && *Instance==MODULEDONE())
+        Instance++;
+
+    if (*Instance==EndMarker)
+        Instance = NULL;
+
+    return Instance;
+}
+
+/*  NvRmSetPadTristates will increment/decrement the reference count for
+ *  each pad group's global tristate value for each "ConfigSet" command in
+ *  a pad group configuration, and update the register as needed */
+void NvRmPrivAp15SetPadTristates(
+    NvRmDeviceHandle hDevice,
+    const NvU32* Module,
+    NvU32 Config,
+    NvBool EnableTristate)
+{
+    int StackDepth = 0;
+    const NvU32 *Instance = NULL;
+    const NvU32 *ReturnStack[MAX_NESTING_DEPTH+1];
+
+    /* The re-multiplexing configuration is stored in program 0,
+     * along with the reset config. */
+    if (Config==NVODM_QUERY_PINMAP_MULTIPLEXED)
+        Config = 0;
+
+    Instance = NvRmPrivAp15FindConfigStart(Module, Config, MODULEDONE());
+    /* The first stack return entry is NULL, so that when a ConfigEnd is
+     * encountered in the "main" configuration program, we pop off a NULL
+     * pointer, which causes the configuration loop to terminate. */
+    ReturnStack[0] = NULL;
+
+    /*  This loop iterates over all of the pad groups that need to be updated,
+     *  and updates the reference count for each appropriately.  */
+
+    NvOsMutexLock(hDevice->mutex);
+
+    while (Instance)
+    {
+        switch (NV_DRF_VAL(MUX,ENTRY, STATE, *Instance))
+        {
+            case PinMuxConfig_OpcodeExtend:
+                /* Pop the most recent return address off of the return stack
+                 * (which will be NULL if no values have been pushed onto the
+                 * stack) */
+                if (NV_DRF_VAL(MUX,ENTRY, OPCODE_EXTENSION,
+                               *Instance)==PinMuxOpcode_ConfigEnd)
+                {
+                    Instance = ReturnStack[StackDepth--];
+                }
+                /* ModuleDone & SubroutinesDone should never be encountered
+                 * during execution, for properly-formatted tables. */
+                else
+                {
+                    NV_ASSERT(0 && "Logical entry in table!\n");
+                }
+                break;
+            case PinMuxConfig_BranchLink:
+                /*  Push the next instruction onto the return stack if nesting space
+                    is available, and jump to the target. */
+                NV_ASSERT(StackDepth<MAX_NESTING_DEPTH);
+                ReturnStack[++StackDepth] = Instance+1;
+                Instance = NvRmPrivAp15FindConfigStart(Module,
+                               NV_DRF_VAL(MUX,ENTRY,BRANCH_ADDRESS,*Instance),
+                               SUBROUTINESDONE());
+                NV_ASSERT(Instance && "Invalid branch configuration in table!\n");
+                break;
+            case PinMuxConfig_Set:
+            {
+                NvS16 SkipUpdate;
+                NvU32 TsOffs = NV_DRF_VAL(MUX,ENTRY, TS_OFFSET, *Instance);
+                NvU32 TsShift = NV_DRF_VAL(MUX,ENTRY, TS_SHIFT, *Instance);
+
+/*  abuse pre/post-increment, to ensure that skipUpdate is 0 when the
+ *  register needs to be programmed (i.e., enabling and previous value was 0,
+ *  or disabling and new value is 0).
+ */
+                if (EnableTristate)
+#if (SKIP_TRISTATE_REFCNT == 0)
+                    SkipUpdate =  --hDevice->TristateRefCount[TsOffs*32 + TsShift];
+                else
+                    SkipUpdate = hDevice->TristateRefCount[TsOffs*32 + TsShift]++;
+#else
+                    SkipUpdate = 1;
+                else
+                    SkipUpdate = 0;
+#endif
+
+#if (SKIP_TRISTATE_REFCNT == 0)
+                if (SkipUpdate < 0)
+                {
+                    hDevice->TristateRefCount[TsOffs*32 + TsShift] = 0;
+                    NV_DEBUG_PRINTF(("(%s:%s) Negative reference count detected "
+                                     "on TRISTATE_REG_%c_0, bit %u\n",
+                        __FILE__, __LINE__, ('A'+(TsOffs)), TsShift));
+                    //NV_ASSERT(SkipUpdate>=0);
+                }
+#endif
+
+                if (!SkipUpdate)
+                {
+                    NvU32 Curr = NV_REGR(hDevice,
+                        NvRmModuleID_Misc, 0,
+                        APB_MISC_PP_TRISTATE_REG_A_0 + 4*TsOffs);
+                    Curr &= ~(1<<TsShift);
+#if (SKIP_TRISTATE_REFCNT == 0)
+                    Curr |= (EnableTristate?1:0)<<TsShift;
+#endif
+                    NV_REGW(hDevice, NvRmModuleID_Misc, 0,
+                        APB_MISC_PP_TRISTATE_REG_A_0 + 4*TsOffs, Curr);
+
+#if NVRM_PINMUX_DEBUG_FLAG
+                    NV_DEBUG_PRINTF(("Setting TRISTATE_REG_%s to %s\n",
+                        (const char*)Instance[2],
+                        (EnableTristate)?"TRISTATE" : "NORMAL"));
+#endif
+                }
+            }
+            /* fall through.
+             * The "Unset" configurations are not applicable to tristate
+             * configuration, so skip over them. */
+            case PinMuxConfig_Unset:
+                Instance += NVRM_PINMUX_SET_OPCODE_SIZE;
+                break;
+        }
+    }
+    NvOsMutexUnlock(hDevice->mutex);
+}
+
+/*  NvRmSetPinMuxCtl will apply new pin mux configurations to the pin mux
+ *  control registers.  */
+void NvRmPrivAp15SetPinMuxCtl(
+    NvRmDeviceHandle hDevice,
+    const NvU32* Module,
+    NvU32 Config)
+{
+    NvU32 MuxCtlOffset, MuxCtlShift, MuxCtlMask, MuxCtlSet, MuxCtlUnset;
+    const NvU32 *ReturnStack[MAX_NESTING_DEPTH+1];
+    const NvU32 *Instance;
+    int StackDepth = 0;
+    NvU32 Curr;
+
+    ReturnStack[0] = NULL;
+    Instance = Module;
+
+    NvOsMutexLock(hDevice->mutex);
+
+    /* The re-multiplexing configuration is stored in program 0,
+     * along with the reset config. */
+    if (Config==NVODM_QUERY_PINMAP_MULTIPLEXED)
+        Config = 0;
+
+    Instance = NvRmPrivAp15FindConfigStart(Module, Config, MODULEDONE());
+
+    //  Apply the new configuration, setting / unsetting as appropriate
+    while (Instance)
+    {
+        switch (NV_DRF_VAL(MUX,ENTRY, STATE, *Instance))
+        {
+            case PinMuxConfig_OpcodeExtend:
+                if (NV_DRF_VAL(MUX,ENTRY, OPCODE_EXTENSION,
+                               *Instance)==PinMuxOpcode_ConfigEnd)
+                {
+                    Instance = ReturnStack[StackDepth--];
+                }
+                else
+                {
+                    NV_ASSERT(0 && "Logical entry in table!\n");
+                }
+                break;
+            case PinMuxConfig_BranchLink:
+                NV_ASSERT(StackDepth<MAX_NESTING_DEPTH);
+                ReturnStack[++StackDepth] = Instance+1;
+                Instance = NvRmPrivAp15FindConfigStart(Module,
+                               NV_DRF_VAL(MUX,ENTRY,BRANCH_ADDRESS,*Instance),
+                               SUBROUTINESDONE());
+                NV_ASSERT(Instance && "Invalid branch configuration in table!\n");
+                break;
+            default:
+            {
+                MuxCtlOffset = NV_DRF_VAL(MUX,ENTRY, MUX_CTL_OFFSET, *Instance);
+                MuxCtlShift = NV_DRF_VAL(MUX,ENTRY, MUX_CTL_SHIFT, *Instance);
+                MuxCtlUnset = NV_DRF_VAL(MUX,ENTRY, MUX_CTL_UNSET, *Instance);
+                MuxCtlSet = NV_DRF_VAL(MUX,ENTRY, MUX_CTL_SET, *Instance);
+                MuxCtlMask = NV_DRF_VAL(MUX, ENTRY, MUX_CTL_MASK, *Instance);
+
+                Curr = NV_REGR(hDevice, NvRmModuleID_Misc, 0,
+                    APB_MISC_PP_PIN_MUX_CTL_A_0 + 4*MuxCtlOffset);
+
+                if (NV_DRF_VAL(MUX,ENTRY,STATE,*Instance)==PinMuxConfig_Set)
+                {
+                    Curr &= ~(MuxCtlMask<<MuxCtlShift);
+                    Curr |= (MuxCtlSet<<MuxCtlShift);
+#if NVRM_PINMUX_DEBUG_FLAG
+                    NV_DEBUG_PRINTF(("Configuring PINMUX_CTL_%s\n",
+                                     (const char *)Instance[1]));
+#endif
+
+                }
+                else if (((Curr>>MuxCtlShift)&MuxCtlMask)==MuxCtlUnset)
+                {
+                    NV_ASSERT(NV_DRF_VAL(MUX,ENTRY,STATE,
+                                         *Instance)==PinMuxConfig_Unset);
+                    Curr &= ~(MuxCtlMask<<MuxCtlShift);
+                    Curr |= (MuxCtlSet<<MuxCtlShift);
+#if NVRM_PINMUX_DEBUG_FLAG
+                    NV_DEBUG_PRINTF(("Unconfiguring PINMUX_CTL_%s\n",
+                                     (const char *)Instance[1]));
+#endif
+                }
+
+                NV_REGW(hDevice, NvRmModuleID_Misc, 0,
+                    APB_MISC_PP_PIN_MUX_CTL_A_0 + 4*MuxCtlOffset, Curr);
+                Instance += NVRM_PINMUX_SET_OPCODE_SIZE;
+                break;
+            }
+        }
+    }
+    NvOsMutexUnlock(hDevice->mutex);
+}
+
+void NvRmPrivAp15InitTrisateRefCount(NvRmDeviceHandle hDevice)
+{
+    NvU32 i, j, curr;
+
+    NvOsMutexLock(hDevice->mutex);
+    NvOsMemset(hDevice->TristateRefCount, 0,
+        sizeof(hDevice->TristateRefCount));
+
+    for (i=0; i<=((APB_MISC_PP_TRISTATE_REG_D_0-
+                   APB_MISC_PP_TRISTATE_REG_A_0)>>2); i++)
+    {
+        curr = NV_REGR(hDevice, NvRmModuleID_Misc, 0,
+                       APB_MISC_PP_TRISTATE_REG_A_0 + 4*i);
+        // swap from 0=normal, 1=tristate to 0=tristate, 1=normal
+        curr = ~curr;
+        for (j=0; curr; j++, curr>>=1)
+        {
+            /* the oppositely-named tristate reference count keeps track
+             * of the number of active users of each pad group, and
+             * enables tristate when the count reaches zero. */
+            hDevice->TristateRefCount[i*32 + j] = (NvS16)(curr & 0x1);
+        }
+    }
+    NvOsMutexUnlock(hDevice->mutex);
+}
+
+void NvRmAp15SetDefaultTristate(NvRmDeviceHandle hDevice)
+{
+    return;
+}
+
+void NvRmPrivAp15SetGpioTristate(
+    NvRmDeviceHandle hDevice,
+    NvU32 Port,
+    NvU32 Pin,
+    NvBool EnableTristate)
+{
+    NvU32 Mapping = 0;
+    NvS16 SkipUpdate;
+    NvBool ret = NV_FALSE;
+
+    NV_ASSERT(hDevice);
+
+    switch (hDevice->ChipId.Id)
+    {
+        case 0x15:
+        case 0x16:
+            ret = NvRmAp15GetPinGroupForGpio(hDevice, Port, Pin, &Mapping);
+            break;
+        default:
+            NV_ASSERT(!"Chip ID not supported");
+            return;
+    }
+
+    if (ret)
+    {
+        NvU32 TsOffs  = NV_DRF_VAL(MUX, GPIOMAP, TS_OFFSET, Mapping);
+        NvU32 TsShift = NV_DRF_VAL(MUX, GPIOMAP, TS_SHIFT, Mapping);
+
+        NvOsMutexLock(hDevice->mutex);
+
+        if (EnableTristate)
+#if (SKIP_TRISTATE_REFCNT == 0)
+            SkipUpdate = --hDevice->TristateRefCount[TsOffs*32 + TsShift];
+        else
+            SkipUpdate = hDevice->TristateRefCount[TsOffs*32 + TsShift]++;
+#else
+            SkipUpdate = 1;
+        else
+            SkipUpdate = 0;
+#endif
+
+#if (SKIP_TRISTATE_REFCNT == 0)
+        if (SkipUpdate < 0)
+        {
+            hDevice->TristateRefCount[TsOffs*32 + TsShift] = 0;
+            NV_DEBUG_PRINTF(("(%s:%s) Negative reference count detected on "
+                "TRISTATE_REG_%c_0, bit %u\n", __FILE__, __LINE__,
+                ('A'+(TsOffs)), TsShift));
+            //NV_ASSERT(SkipUpdate>=0);
+        }
+#endif
+
+        if (!SkipUpdate)
+        {
+            NvU32 Curr = NV_REGR(hDevice,
+                NvRmModuleID_Misc, 0,
+                APB_MISC_PP_TRISTATE_REG_A_0 + 4*TsOffs);
+            Curr &= ~(1<<TsShift);
+#if (SKIP_TRISTATE_REFCNT == 0)
+            Curr |= (EnableTristate?1:0)<<TsShift;
+#endif
+            NV_REGW(hDevice, NvRmModuleID_Misc, 0,
+                APB_MISC_PP_TRISTATE_REG_A_0 + 4*TsOffs, Curr);
+        }
+
+        NvOsMutexUnlock(hDevice->mutex);
+    }
+}
+
diff --git a/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_pinmux_tables.c b/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_pinmux_tables.c
new file mode 100644
index 000000000000..cb9e81566ecb
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_pinmux_tables.c
@@ -0,0 +1,1185 @@
+/*
+ * Copyright (c) 2008-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include "nvcommon.h"
+#include "nvrm_pinmux.h"
+#include "nvrm_drf.h"
+#include "nvassert.h"
+#include "nvrm_hwintf.h"
+#include "ap15rm_private.h"
+#include "ap15/arapb_misc.h"
+#include "ap15/arclk_rst.h"
+#include "ap15rm_pinmux_utils.h"
+#include "nvodm_query_pinmux.h"
+#include "nvrm_clocks.h"
+
+/**
+ *  Each of the pin mux configurations defined in the pin mux spreadsheet are
+ *  stored in tables below.  For each configuration, every pad group that
+ *  must be programmed is stored as a single 32b entry, where the register
+ *  offset (for both the tristate and pin mux control registers), field bit
+ *  position (ditto), pin mux mask, and new pin mux state are programmed.
+ *
+ *  Furthermore, a simple state machine is implemented, so that pin mux
+ *  registers can be "unprogrammed," in order to disown pad groups which
+ *  may be pointing to a controller which is about to be programmed.  The
+ *  state machine also has no-op states which indicate when all necessary
+ *  register programming for a configuration is complete, as well as when the
+ *  last configuration for a module instance has been reached.
+ *
+ *  Each module instance array has a reserved "reset" configuration at index
+ *  zero.  This special configuration is used in order to disown all pad
+ *  groups whose reset state refers to the module instance.  When a module
+ *  instance configuration is to be applied, the reset configuration will
+ *  first be applied, to ensure that no conflicts will arise between register
+ *  reset values and the new configuration, followed by the application of
+ *  the requested configuration.
+ *
+ *  Furthermore, for controllers which support dynamic pinmuxing (i.e.,
+ *  the "Multiplexed" pin map option), the last table entry is reserved for
+ *  a "global unset," which will ensure that all configurations are disowned.
+ *  This Multiplexed configuration should be applied before transitioning
+ *  from one configuration to a second one.
+ *
+ *  The table data has been packed into a single 32b entry to minimize code
+ *  footprint using macros similar to the hardware register definitions, so
+ *  that all of the shift and mask operations can be performed with the DRF
+ *  macros.
+ */
+
+/*  Below are the tables for all of the pin mux configurations for each
+ *  controller.  The first (zero-index) entry in each table is a "reset"
+ *  configuration.  This is used to disown all pads whose reset state
+ *  corresponds to the controller function.  When a new configuration is
+ *  applied, the driver will first apply the reset configuration to ensure
+ *  that no conflicts will occur due to identical signals being routed to
+ *  multiple pad groups.
+ */
+
+const NvU32 g_Ap15MuxI2c1[] = {
+    //  Reset config -- disown GEN1_I2C pads
+    UNCONFIG(A, RM,I2C, RSVD1), CONFIGEND(),
+    //  I2C1, Config 1 (GEN1_I2C pads)
+    CONFIG(A,A,RM,I2C), CONFIGEND(),
+    //  I2C1, Config 2 (SPDIF pads) -- disown GEN1_I2C pads
+    CONFIG(B,D,SPDO,I2C), CONFIG(B,D,SPDI,I2C), CONFIGEND(),
+    //  I2C1, Config 3 (SPI2 pads)
+    CONFIG(B,D,SPIG,I2C),CONFIG(B,D,SPIH,I2C), CONFIGEND(),
+    MODULEDONE()
+};
+
+/*  I2C_2 instance 1 supports dynamic pin-muxing for CAM_I2C and GEN2_I2C;
+ *  PinMap_Multiplex is intended to release all pads to a nominal
+ *  state, so it is implemented at the end of the list using UNCONFIG
+ *  options, so that no pad groups are trying to use I2C_2.
+ */
+const NvU32 g_Ap15MuxI2c2[] = {
+    //  Reset & multiplexed config -- disown GEN2_I2C2 pads
+    UNCONFIG(G,PTA,I2C2,RSVD1),UNCONFIG(G,DTF,I2C2,RSVD1),UNCONFIG(E,LVP0,I2C2,RSVD),
+    UNCONFIG(E,LM1,I2C2,DISPLAYA),UNCONFIG(G,LHP0,I2C2,DISPLAYA),
+    UNCONFIG(G,LVP1,I2C2,DISPLAYA),CONFIGEND(),
+    //  CAM_I2C pads
+    CONFIG(D,G,DTF,I2C2), CONFIGEND(),
+    //  GEN2_I2C pads
+    CONFIG(A,G,PTA,I2C2), CONFIGEND(),
+    //  LCD control pads
+    CONFIG(C,E,LVP0,I2C2), CONFIG(C,E,LM1,I2C2), CONFIGEND(),
+    //  alternate LCD control pads
+    CONFIG(C,G,LHP0,I2C2), CONFIG(C,G,LVP1,I2C2), CONFIGEND(),
+    MODULEDONE()
+};
+
+const NvU32* g_Ap15MuxI2c[] = {
+    &g_Ap15MuxI2c1[0],
+    &g_Ap15MuxI2c2[0],
+    NULL
+};
+
+const NvU32 g_Ap15MuxI2c_Pmu[] = {
+    //  Reset config -- disown I2CP pads
+    UNCONFIG(C,I2CP,I2C, RSVD2), CONFIGEND(),
+    //  I2CP pads
+    CONFIG(A,C,I2CP,I2C), CONFIGEND(),
+    MODULEDONE()
+};
+
+const NvU32* g_Ap15MuxI2cPmu[] = {
+    &g_Ap15MuxI2c_Pmu[0],
+    NULL
+};
+
+const NvU32 g_Ap15Mux_Mmc[] = {
+    CONFIGEND(), // no pad groups reset to MMC, so nothing to disown for reset config
+    CONFIG(A,A,ATB,HSMMC), CONFIG(A,A,ATD,HSMMC), CONFIG(B,A,ATE,HSMMC), CONFIGEND(),
+    CONFIG(A,A,ATB,HSMMC),CONFIG(A,A,ATD,HSMMC),CONFIGEND(),
+    MODULEDONE()
+};
+
+const NvU32* g_Ap15MuxMmc[] = {
+    &g_Ap15Mux_Mmc[0],
+    NULL
+};
+
+const NvU32 g_Ap15MuxSdio2[] = {
+    //  Reset config - abandon SDB, SLXK,SLXA,SLXB,SLXC,SLXD .chosen RSVD,SLINK4B
+    UNCONFIG(D,SDB,SDIO2,RSVD), UNCONFIG(B,SLXK,SDIO1,SLINK4B), UNCONFIG(B,SLXB,SDIO1,SLINK4B),
+    UNCONFIG(B,SLXC,SDIO1,SLINK4B),UNCONFIG(B,SLXD,SDIO1,SLINK4B),UNCONFIG(B,SLXA,SDIO1,SLINK4B),
+    CONFIGEND(),
+    //  config 1 SDB + SLXK,SLXA,SLXB,SLXC,SLXD pads
+    CONFIG(B,D,SDB,SDIO2), CONFIG(B,B,SLXK,SDIO1), CONFIG(B,B,SLXB,SDIO1),
+    CONFIG(B,B,SLXC,SDIO1), CONFIG(B,B,SLXD,SDIO1), CONFIG(B,B,SLXA,SDIO1),CONFIGEND(),
+    // config 2 KBCB,KBCE,KBCD pads
+    CONFIG(A,C,KBCB,SDIO1),CONFIG(A,A,KBCE,SDIO1),CONFIG(D,G,KBCD,SDIO1),
+    CONFIGEND(),
+    //config 3   KBCB pads
+    CONFIG(A,C,KBCB,SDIO1), CONFIGEND(),
+    //  config 4 DAP1, SPDO, SPDI pads
+    CONFIG(A,C,DAP1,SDIO1), CONFIG(B,D,SPDO,SDIO1), CONFIG(B,D,SPDI,SDIO1), CONFIGEND(),
+    //  config 5  DTA,DTD pads
+    CONFIG(A,B,DTA,SDIO1), CONFIG(A,B,DTD,SDIO1), CONFIGEND(),
+    MODULEDONE()
+};
+
+const NvU32 g_Ap15MuxSdio3[] = {
+    // no pad groups reset to SDIO3, so nothing to disown for reset config
+    CONFIGEND(),
+    //  config1  SDD + SDC+SLXK+SLXA+SLXB pads
+    CONFIG(B,D,SDD,SDIO2), CONFIG(B,D,SDC,SDIO2), CONFIG(B,D,SDB,SDIO2_ALT),
+    CONFIG(B,B,SLXA,SDIO2), CONFIG(B,B,SLXK,SDIO2), CONFIG(B,B,SLXB,SDIO2), CONFIGEND(),
+    //  congig 2 SDD, SDC  pads
+    CONFIG(B,D,SDD,SDIO2), CONFIG(B,D,SDC,SDIO2), CONFIGEND(),
+    MODULEDONE()
+};
+
+const NvU32* g_Ap15MuxSdio[] = {
+    &g_Ap15MuxSdio2[0],
+    &g_Ap15MuxSdio3[0],
+    NULL
+};
+
+const NvU32 g_Ap15Mux_Spdif[] = {
+    //  Reset config - abandon SPDO, SPDI .chosen RSVD.
+    UNCONFIG(D,SPDO,SPDIF,RSVD), UNCONFIG(D,SPDI,SPDIF,RSVD),CONFIGEND(),
+    //  config1  SPDO+ SPDI pads
+    CONFIG(B,D,SPDO,SPDIF), CONFIG(B,D,SPDI,SPDIF), CONFIGEND(),
+    //  congig 2 SLXD, SLXC  pads
+    CONFIG(B,B,SLXD,SPDIF), CONFIG(B,B,SLXC,SPDIF), CONFIGEND(),
+    //  congig 3 UAD, pads
+    CONFIG(B,A,UAD,SPDIF), CONFIGEND(),
+    MODULEDONE()
+};
+
+const NvU32* g_Ap15MuxSpdif[] = {
+    &g_Ap15Mux_Spdif[0],
+    NULL
+};
+
+static const NvU32 g_Ap15MuxUart1[] = {
+    //  Reset config - abandon IRRX, IRTX &amp; SDD
+    UNCONFIG(C,IRRX,UARTA,RSVD2), UNCONFIG(C,IRTX,UARTA,RSVD2), UNCONFIG(D,SDD,UARTA,PWM), CONFIGEND(),
+    //  8b UAA + UAB pads
+    CONFIG(B,A,UAA,UARTA), CONFIG(B,A,UAB,UARTA), CONFIGEND(),
+    //  4b UAA pads
+    CONFIG(B,A,UAA,UARTA_ALT3), CONFIGEND(),
+    //  8b GPU pads
+    CONFIG(A,D,GPU,UARTA), CONFIGEND(),
+    //  4b VFIR + UAD pads
+    CONFIG(A,C,IRRX,UARTA), CONFIG(A,C,IRTX,UARTA), CONFIG(B,A,UAD,UARTA), CONFIGEND(),
+    //  2b VFIR pads
+    CONFIG(A,C,IRRX,UARTA), CONFIG(A,C,IRTX,UARTA), CONFIGEND(),
+    //  2b SDIO pads
+    CONFIG(B,D,SDD,UARTA), CONFIGEND(),
+    MODULEDONE()
+};
+
+static const NvU32 g_Ap15MuxUart2[] = {
+//  Reset config - abandon UAD. pads.chosen SFLASH pads
+    UNCONFIG(A,UAD,IRDA,SFLASH), CONFIGEND(),
+//  4b UAD + IRRX + IRTX pads
+    CONFIG(B,A,UAD,IRDA), CONFIG(A,C,IRRX,UARTB), CONFIG(A,C,IRTX,UARTB), CONFIGEND(),
+//  4b UAB pads
+    CONFIG(B,A,UAB,UARTB), CONFIGEND(),
+//..2b UAB pads
+    CONFIG(B,A,UAD,IRDA), CONFIGEND(),
+    MODULEDONE()
+};
+
+static const NvU32 g_Ap15MuxUart3[] = {
+    //  Reset config - abandon UCA. chosen RSVD1
+    UNCONFIG(B,UCA,UARTC,RSVD1), CONFIGEND(),
+    //  4b UCA + UCB pads
+    CONFIG(B,B,UCA,UARTC), CONFIG(B,B,UCB,UARTC), CONFIGEND(),
+    //  2b UCA pads
+    CONFIG(B,B,UCA,UARTC), CONFIGEND(),
+    MODULEDONE()
+};
+
+static const NvU32* g_Ap15MuxUart[] = {
+    &g_Ap15MuxUart1[0],
+    &g_Ap15MuxUart2[0],
+    &g_Ap15MuxUart3[0],
+    NULL
+};
+
+const NvU32 g_Ap15MuxSpi1[] = {
+    //  Reset config - abandon SPIC, SPIB, SPIA, pads.
+    UNCONFIG(D,SPIC,SPI1,RSVD), UNCONFIG(D,SPIB,SPI1,RSVD),
+    UNCONFIG(D,SPIA,SPI1,RSVD), CONFIGEND(),
+    //  SPIE,SPIF,SPID pads
+    CONFIG(B,D,SPIE,SPI1),CONFIG(B,D,SPIF,SPI1),CONFIG(B,D,SPID,SPI1), CONFIGEND(),
+    //  DTE, DTB pads
+    CONFIG(A,B,DTE,SPI1), CONFIG(A,B,DTB,SPI1), CONFIGEND(),
+    //  SPIC,SPIB,SPIA pads
+    CONFIG(B,D,SPIC,SPI1), CONFIG(B,D,SPIB,SPI1), CONFIG(B,D,SPIA,SPI1), CONFIGEND(),
+    //  LHP2,LHP1,LHP0,LVP1,LDI,LPP pads
+    CONFIG(C,G,LHP2,SPI1), CONFIG(C,G,LHP1,SPI1), CONFIG(C,G,LHP0,SPI1),
+    CONFIG(C,G,LVP1,SPI1), CONFIG(D,G,LDI,SPI1), CONFIG(D,G,LPP,SPI1), CONFIGEND(),
+    MODULEDONE()
+};
+
+const NvU32 g_Ap15MuxSpi2[] = {
+    //  Reset config - abandon UAB, pads.  MIPI_HS chosen
+    UNCONFIG(A,UAB,SPI2,MIPI_HS), UNCONFIG(D,SPID,SPI2,RSVD),
+    UNCONFIG(D,SPIE,SPI2,RSVD), CONFIGEND(),
+    //..SPIC,SPIB,SPIA,SPIG, SPIH Pads
+    CONFIG(B,D,SPIC,SPI2), CONFIG(B,D,SPIB,SPI2), CONFIG(B,D,SPIA,SPI2),
+    CONFIG(B,D,SPIG,SPI2), CONFIG(B,D,SPIH,SPI2), CONFIGEND(),
+    //  UAB pads
+    CONFIG(B,A,UAB,SPI2), CONFIGEND(),
+    //  SPIE,SPIF,SPID,SPIG,SPIH pads
+    CONFIG(B,D,SPIE,SPI2_ALT),CONFIG(B,D,SPIF,SPI2),CONFIG(B,D,SPID,SPI2_ALT),
+    CONFIG(B,D,SPIG,SPI2_ALT),CONFIG(B,D,SPIH,SPI2_ALT), CONFIGEND(),
+    //  SLXC,SLXK,SLXA,SLXB,SLXD pads
+    CONFIG(B,B,SLXC,SPI2), CONFIG(B,B,SLXK,SPI2), CONFIG(B,B,SLXA,SPI2),
+    CONFIG(B,B,SLXB,SPI2),CONFIG(B,B,SLXD,SPI2), CONFIGEND(),
+    MODULEDONE()
+};
+
+/*  SPI instance 3 supports dynamic pin-muxing for audio-codec &amp;
+ *  display, PinMap_Multiplex is intended to release all pads to a nominal
+ *  state, so it is implemented at the end of the list using UNCONFIG
+ *  options, so that no pad groups are trying to use SPI3.
+ */
+const NvU32 g_Ap15MuxSpi3[] = {
+/*  Reset config - abandon UAA, SPIF, SPIG, SPIH pads.  SPI2_ALT chosen
+ *  as the reset state for SPIG/SPIH, since this will either be clobbered
+ *  by Spi2 SpiPinMap_Config1, I2c1 I2cPinMap_Config3, correct (for Spi2
+ *  SpiPinMap_Config3), or irrelevant */
+    UNCONFIG(A,UAA,SPI3,MIPI_HS), UNCONFIG(D,SPIF,SPI3,RSVD),
+    UNCONFIG(D,SPIG,SPI3,SPI2_ALT), UNCONFIG(D,SPIH,SPI3,SPI2_ALT),
+    //  multiplex unconfiguration
+    UNCONFIG(C,XM2A,SPI3,SPROM), // multiplex config 1 to SPROM
+    UNCONFIG(E,LSC1,SPI3,DISPLAYA), UNCONFIG(E,LPW2,SPI3,DISPLAYA), // mux config 2 to displaya
+    UNCONFIG(E,LPW0,SPI3,DISPLAYA), UNCONFIG(E,LM0,SPI3,DISPLAYA),
+    UNCONFIG(E,LSCK,SPI3,DISPLAYA), UNCONFIG(E,LSDI,SPI3,DISPLAYA), // mux config 3 to displaya
+    UNCONFIG(D,SPIC,SPI3,RSVD),UNCONFIG(D,SPIB,SPI3,RSVD), // config 5 to rsvd
+    UNCONFIG(D,SPIA,SPI3,RSVD),
+    UNCONFIG(D,SDD,SPI3,PWM),UNCONFIG(D,SDC,SPI3,TWC), // config 6 to PWM & TWC
+    CONFIGEND(),
+    //  XM2A pads
+    CONFIG(B,C,XM2A,SPI3), CONFIGEND(),
+    //  LCD pads
+    CONFIG(C,E,LSC1,SPI3), CONFIG(D,E,LPW2,SPI3), CONFIG(D,E,LPW0,SPI3), CONFIG(C,E,LM0,SPI3), CONFIGEND(),
+    //  Alternate LCD pads
+    CONFIG(C,E,LSCK,SPI3), CONFIG(D,E,LSDI,SPI3), CONFIG(D,E,LSDA,SPI3), CONFIG(C,E,LCSN,SPI3), CONFIGEND(),
+    //  UAA pads
+    CONFIG(B,A,UAA,SPI3), CONFIGEND(),
+    //  SPI pads
+    CONFIG(B,D,SPIA,SPI3), CONFIG(B,D,SPIB,SPI3), CONFIG(B,D,SPIC,SPI3), CONFIGEND(),
+    //  2CS SPI3 on SDIO pads
+    CONFIG(B,D,SDC,SPI3), CONFIG(B,D,SDD,SPI3), CONFIGEND(),
+    MODULEDONE()
+};
+
+const NvU32* g_Ap15MuxSpi[] = {
+    &g_Ap15MuxSpi1[0],
+    &g_Ap15MuxSpi2[0],
+    &g_Ap15MuxSpi3[0],
+    NULL
+};
+
+//  Sflash should always be after PWM in the module order, since
+//  the reset value for UCB muxes from both controllers, so the
+//  reset configuration for Sflash assumes that Pwm has executed first.
+NV_CT_ASSERT((NvU32)NvOdmIoModule_Sflash > (NvU32)NvOdmIoModule_Pwm);
+
+const NvU32 g_Ap15Mux_Sflash[] = {
+    /*  Reset config.  Normally, this would disown the UCB pads; HOWEVER,
+     *  the reset value for this pad group actually muxes from 2 controllers:
+     *  PWM goes to UART3_RTS, and SFLASH goes to UART3_CTS.  Since the PWM
+     *  controller is initialized before Spi Flash, it is possible for the
+     *  UCB pads to be correctly configured to mux 0 before reaching here.
+     *  Therefore, the correct thing to do is to skip the UNCONFIG for this
+     *  pad group, since PWM will already handle this.
+     */
+    /*UNCONFIG(B,UCB,PWM0,RSVD2),*/ CONFIGEND(),
+    //  config 1 XM2S + XM2A pads
+    CONFIG(B,C,XM2S,SPI), CONFIG(B,C,XM2A,SPI), CONFIGEND(),
+    //  config2 XM2S + UAD +XM2A pads
+    CONFIG(B,C,XM2S,SPI), CONFIG(B,A,UAD,SFLASH), CONFIG(B,C,XM2A,SPI), CONFIGEND(),
+    //  config 3 XM2S + UCB +XM2A pads
+    CONFIG(B,C,XM2S,SPI), CONFIG(B,B,UCB,PWM0), CONFIG(B,C,XM2A,SPI), CONFIGEND(),
+    //  config 4 XM2A UAD UCB XM2A pads
+    CONFIG(B,C,XM2S,SPI), CONFIG(B,A,UAD,SFLASH), CONFIG(B,B,UCB,PWM0),
+    CONFIG(B,C,XM2A,SPI), CONFIGEND(),
+    MODULEDONE()
+};
+
+const NvU32* g_Ap15MuxSflash[] = {
+    &g_Ap15Mux_Sflash[0],
+    NULL
+};
+
+
+const NvU32 g_Ap15Mux_Twc[] = {
+    // no pad groups reset to TWC, so nothing to disown for reset config
+     CONFIGEND(),
+    //  DAP2 pads
+    CONFIG(A,C,DAP2,TWC), CONFIGEND(),
+    //  SDC pads
+    CONFIG(B,D,SDC,TWC), CONFIGEND(),
+    MODULEDONE()
+};
+
+const NvU32* g_Ap15MuxTwc[] = {
+    &g_Ap15Mux_Twc[0],
+    NULL
+};
+
+const NvU32 g_Ap15Mux_Ata[] = {
+    // Reset config --  abandon ATA, ATC, ATB, ATD, ATE pads. NAND RSVD as chosenpads
+    UNCONFIG(A,ATC,IDE,RSVD), UNCONFIG(A,ATD,IDE,NAND), UNCONFIG(A,ATE,IDE,NAND),
+    UNCONFIG(A,ATA,IDE,RSVD), UNCONFIG(A,ATB,IDE,NAND), CONFIGEND(),
+    // ATA, Config 1 (Nand pads)
+    CONFIG(A,A,ATC,IDE), CONFIG(A,A,ATD,IDE), CONFIG(B,A,ATE,IDE), CONFIG(A,A,ATA,IDE),
+    CONFIG(A,A,ATB,IDE), CONFIGEND(),
+    MODULEDONE()
+};
+
+const NvU32* g_Ap15MuxAta[] = {
+    &g_Ap15Mux_Ata[0],
+    NULL
+};
+
+const NvU32 g_Ap15Mux_Pwm[] = {
+    // Reset config -- disown SDC,UCB pads SDIO2, RSVD2 as chosen pads
+    UNCONFIG(D,SDC,PWM,SDIO2), UNCONFIG(B,UCB,PWM0,RSVD2), CONFIGEND(),
+    // PWM, Config 1 (SDC pads)
+    CONFIG(B,D,SDC,PWM), CONFIGEND(),
+    // PWM, Config 2 (UCB ,SDDpads)
+    CONFIG(B,B,UCB,PWM0), CONFIG(B,D,SDD,PWM), CONFIGEND(),
+    // PWM, Config 2 (UCB ,SDDpads)
+    CONFIG(B,B,UCB,PWM0), CONFIGEND(),
+    CONFIG(B,D,SDD,PWM), CONFIGEND(),
+    MODULEDONE()
+};
+
+const NvU32* g_Ap15MuxPwm[] = {
+    &g_Ap15Mux_Pwm[0],
+    NULL
+};
+
+const NvU32 g_Ap15Mux_Hsi[] = {
+    CONFIGEND(), // no pad groups reset to HSI, so nothing to disown for reset config
+    CONFIG(B,A,UAA,MIPI_HS), CONFIG(B,A,UAB,MIPI_HS), CONFIGEND(),
+    MODULEDONE()
+};
+
+const NvU32 *g_Ap15MuxHsi[] = {
+    &g_Ap15Mux_Hsi[0],
+    NULL
+};
+
+const NvU32 g_Ap15Mux_Nand[] = {
+    CONFIGEND(), // no pad groups reset to NAND, so nothing to disown for reset config
+    //  config 1 ATA,ATB,ATC,ATD,ATE pads
+    CONFIG(A,A,ATA,NAND_ALT), CONFIG(A,A,ATB,NAND_ALT), CONFIG(A,A,ATC,NAND),
+    CONFIG(A,A,ATD,NAND), CONFIG(B,A,ATE,NAND), CONFIGEND(),
+    //  config 1 ATA,ATB,ATC,ATD,ATE pads
+    CONFIG(A,A,ATA,NAND), CONFIG(A,A,ATB,NAND), CONFIG(A,A,ATC,NAND),
+    CONFIG(A,A,ATD,NAND), CONFIG(B,A,ATE,NAND), CONFIGEND(),
+    //  config 1 ATA,ATC,ATE pads
+    CONFIG(A,A,ATA,NAND), CONFIG(A,A,ATC,NAND),
+    CONFIG(B,A,ATE,NAND_ALT), CONFIGEND(),
+    //  config 1 ATA,ATB,ATC,ATD,ATE pads
+    CONFIG(A,A,ATA,NAND), CONFIG(A,A,ATB,NAND), CONFIG(A,A,ATC,NAND),
+    CONFIG(A,A,ATD,NAND_ALT), CONFIG(B,A,ATE,NAND_ALT), CONFIGEND(),
+    //  config 1 ATA,ATC pads
+    CONFIG(A,A,ATA,NAND), CONFIG(A,A,ATC,NAND), CONFIGEND(),
+    //  config 1 ATA,ATB,ATC pads
+    CONFIG(A,A,ATA,NAND), CONFIG(A,A,ATB,NAND),
+    CONFIG(A,A,ATC,NAND), CONFIGEND(),
+    MODULEDONE()
+};
+
+const NvU32* g_Ap15MuxNand[] = {
+    &g_Ap15Mux_Nand[0],
+    NULL
+};
+
+const NvU32 g_Ap15MuxDap1[] = {
+    //  Reset config - abandon ,DAP1.. RSVD2 chosen
+    UNCONFIG(C,DAP1,DAP1,RSVD2), CONFIGEND(),
+    //  config1  DAP1 pads
+    CONFIG(A,C,DAP1,DAP1), CONFIGEND(),
+    MODULEDONE()
+};
+
+const NvU32 g_Ap15MuxDap2[] = {
+    //  Reset config - abandon ,DAP2... RSVD3 chosen
+    UNCONFIG(C,DAP2,DAP2,RSVD3), CONFIGEND(),
+    //  config1  DAP2 pads
+    CONFIG(A,C,DAP2,DAP2), CONFIGEND(),
+    //  congig 2 SLXD, SLXC  pads
+    MODULEDONE()
+};
+
+const NvU32 g_Ap15MuxDap3[] = {
+    //  Reset config - abandon ,DAP3... RSVD2 chosen
+    UNCONFIG(C,DAP3,DAP3,RSVD2), CONFIGEND(),
+    //  config1  DAP3 pads
+    CONFIG(A,C,DAP3,DAP3), CONFIGEND(),
+    MODULEDONE()
+};
+
+const NvU32 g_Ap15MuxDap4[] = {
+    //  Reset config - abandon ,DAP4...RSVD2 chosen
+    UNCONFIG(C,DAP4,DAP4,RSVD2), CONFIGEND(),
+    //  config1  DAP4 pads
+    CONFIG(A,C,DAP4,DAP4), CONFIGEND(),
+    MODULEDONE()
+};
+
+const NvU32* g_Ap15MuxDap[] = {
+    &g_Ap15MuxDap1[0],
+    &g_Ap15MuxDap2[0],
+    &g_Ap15MuxDap3[0],
+    &g_Ap15MuxDap4[0],
+    NULL
+};
+
+const NvU32 g_Ap15Mux_Kbc[] = {
+    //  Reset config - abandon ,RSVD2, RSVD1 chosen
+    UNCONFIG(C,KBCA,KBC,RSVD2), UNCONFIG(C,KBCB,KBC,RSVD2), UNCONFIG(A,KBCE,KBC,RSVD1),
+    UNCONFIG(C,KBCC,KBC,RSVD2), UNCONFIG(G,KBCD,KBC,RSVD2), UNCONFIG(A,KBCF,KBC,RSVD1), CONFIGEND(),
+    //  KBCA,KBCB,KBCC,KBCD,KBCE,KBCF  pads
+    CONFIG(A,C,KBCA,KBC), CONFIG(A,C,KBCB,KBC), CONFIG(A,A,KBCE,KBC),
+    CONFIG(B,C,KBCC,KBC), CONFIG(D,G,KBCD,KBC), CONFIG(A,A,KBCF,KBC), CONFIGEND(),
+    //  KBCA,KBCC,KBCD,KBCE,KBCF  pads
+    CONFIG(A,C,KBCA,KBC), CONFIG(A,A,KBCE,KBC),
+    CONFIG(B,C,KBCC,KBC), CONFIG(D,G,KBCD,KBC), CONFIG(A,A,KBCF,KBC), CONFIGEND(),
+    //  KBCA,KBCC,KBCF,  pads
+    CONFIG(A,C,KBCA,KBC), CONFIG(B,C,KBCC,KBC), CONFIG(A,A,KBCF,KBC), CONFIGEND(),
+    //  KBCA,KBCC  pads
+    CONFIG(A,C,KBCA,KBC), CONFIG(B,C,KBCC,KBC), CONFIGEND(),
+    MODULEDONE()
+};
+
+const NvU32* g_Ap15MuxKbc[] = {
+    &g_Ap15Mux_Kbc[0],
+    NULL
+};
+
+NvU32 g_Ap15Mux_Hdcp[] = {
+    CONFIGEND(), // no pad groups reset to HDCP, so nothing to disown for reset config
+    CONFIG(A,G,PTA,HDMI), CONFIGEND(),
+    CONFIG(C,E,LSCK,HDMI), CONFIG(D,E,LSDA,HDMI), CONFIGEND(),
+    CONFIG(D,E,LPW2,HDMI), CONFIG(D,E,LPW0,HDMI), CONFIGEND(),
+    CONFIG(C,E,LSC1,HDMI), CONFIG(D,E,LPW0,HDMI), CONFIGEND(),
+    MODULEDONE()
+};
+
+const NvU32* g_Ap15MuxHdcp[] = {
+    &g_Ap15Mux_Hdcp[0],
+    NULL
+};
+
+const NvU32 g_Ap15Mux_Hdmi[] = {
+    //  HDINT resets to HDINT, so move it to a reserved pin
+    UNCONFIG(B,HDINT,RSVD1,RSVD2), CONFIGEND(),
+    CONFIG(C,B,HDINT,RSVD1), CONFIGEND(),
+    MODULEDONE()
+};
+
+const NvU32* g_Ap15MuxHdmi[] = {
+    &g_Ap15Mux_Hdmi[0],
+    NULL
+};
+
+const NvU32 g_Ap15Mux_Mio[] = {
+    CONFIGEND(), // no pad groups reset to MIO, so nothing to disown for reset config
+    CONFIG(A,A,KBCF,MIO), CONFIG(D,G,KBCD,MIO), CONFIG(A,C,KBCB,MIO), CONFIGEND(),
+    MODULEDONE()
+};
+
+const NvU32* g_Ap15MuxMio[] = {
+    &g_Ap15Mux_Mio[0],
+    NULL
+};
+
+const NvU32 g_Ap15Mux_Slink[] = {
+    CONFIGEND(), // no pad groups reset to SLINK, so nothing to disown for reset config
+    CONFIG(B,B,SLXK,SLINK4B), CONFIG(B,B,SLXA,SLINK4B), CONFIG(B,B,SLXB,SLINK4B),
+    CONFIG(B,B,SLXC,SLINK4B), CONFIG(B,B,SLXD,SLINK4B), CONFIGEND(),
+    MODULEDONE()
+};
+
+const NvU32* g_Ap15MuxSlink[] = {
+    &g_Ap15Mux_Slink[0],
+    NULL
+};
+
+const NvU32 g_Ap15Mux_Vi[] = {
+    CONFIGEND(), // no pad groups reset to VI so nothing to disown for reset config
+    //  config 1 DTA - DTF pads
+    BRANCH(NvOdmVideoInputPinMap_Config2), CONFIG(D,G,DTF,VI), CONFIGEND(),
+    //  config 2 DTA - DTE and CSUS pads
+    CONFIG(A,B,DTA,VI), CONFIG(A,B,DTB,VI), CONFIG(A,B,DTC,VI),
+    CONFIG(A,B,DTD,VI), CONFIG(A,B,DTE,VI), CONFIGEND(),
+    MODULEDONE(),
+    SUBROUTINESDONE(),
+};
+
+const NvU32* g_Ap15MuxVi[] = {
+    &g_Ap15Mux_Vi[0],
+    NULL
+};
+
+const NvU32 g_Ap15Mux_Crt[] = {
+    //  Need  to confirm and fix it ,but none of docs specifies about tv pad group
+    CONFIGEND(), // no pad groups reset to CRT so nothing to disown for reset config
+    //  config 1 LHS, LVS,  pads
+    CONFIG(D,E,LHS,CRT), CONFIG(C,E,LVS,CRT), CONFIGEND(),
+    //  config 2 LHP2,LPW1  pads
+    CONFIG(C,G,LHP2,CRT), CONFIG(D,E,LPW1,CRT), CONFIGEND(),
+    //  config 3 LM1,LPW1  pads
+    CONFIG(C,E,LM1,CRT), CONFIG(D,E,LPW1,CRT), CONFIGEND(),
+    //  config 4 LHP2,LCSN  pads
+    CONFIG(C,G,LHP2,CRT), CONFIG(C,E,LCSN,CRT), CONFIGEND(),
+    MODULEDONE()
+};
+
+const NvU32* g_Ap15MuxCrt[] = {
+    &g_Ap15Mux_Crt[0],
+    NULL
+};
+
+const NvU32 g_Ap15Mux_BacklightDisplay1Pwm0[] = {
+    CONFIGEND(),
+    // Config 1 LPW0 pad
+    CONFIG(D,E,LPW0,DISPLAYA), CONFIGEND(),
+    // Config 2 LPW2 pad
+    CONFIG(D,E,LPW2,DISPLAYA), CONFIGEND(),
+    // Config 3 LM0 pad
+    CONFIG(C,E,LM0,DISPLAYA), CONFIGEND(),
+    MODULEDONE()
+};
+
+const NvU32 g_Ap15Mux_BacklightDisplay1Pwm1[] = {
+    CONFIGEND(),
+    // Config 1 LM1 pad
+    CONFIG(C,E,LM1,DISPLAYA), CONFIGEND(),
+    // Config 2 LDC pad
+    CONFIG(C,E,LDC,DISPLAYA), CONFIGEND(),
+    // Config 3 LPW1 pad
+    CONFIG(D,E,LPW1,DISPLAYA), CONFIGEND(),
+    MODULEDONE()
+};
+
+const NvU32 g_Ap15Mux_BacklightDisplay2Pwm0[] = {
+    CONFIGEND(),
+    // Config 1 LPW0 pad
+    CONFIG(D,E,LPW0,DISPLAYB), CONFIGEND(),
+    // Config 2 LPW2 pad
+    CONFIG(D,E,LPW2,DISPLAYB), CONFIGEND(),
+    // Config 3 LM0 pad
+    CONFIG(C,E,LM0,DISPLAYB), CONFIGEND(),
+    MODULEDONE()
+};
+
+const NvU32 g_Ap15Mux_BacklightDisplay2Pwm1[] = {
+    CONFIGEND(),
+    // Config 1 LM1 pad
+    CONFIG(C,E,LM1,DISPLAYB), CONFIGEND(),
+    // Config 2 LDC pad
+    CONFIG(C,E,LDC,DISPLAYB), CONFIGEND(),
+    // Config 3 LPW1 pad
+    CONFIG(D,E,LPW1,DISPLAYB), CONFIGEND(),
+    MODULEDONE()
+};
+
+const NvU32* g_Ap15MuxBacklight[] = {
+    &g_Ap15Mux_BacklightDisplay1Pwm0[0],
+    &g_Ap15Mux_BacklightDisplay1Pwm1[0],
+    &g_Ap15Mux_BacklightDisplay2Pwm0[0],
+    &g_Ap15Mux_BacklightDisplay2Pwm1[0],
+    NULL
+};
+
+const NvU32 g_Ap15Mux_Display1[] = {
+    CONFIGEND(),
+    //  config 1, 24b RGB.  Pure superset of Config2 (18b RGB)
+    BRANCH(2),
+    CONFIG(C,G,LHP1,DISPLAYA),CONFIG(C,G,LHP2,DISPLAYA),CONFIG(C,G,LVP1,DISPLAYA),
+    CONFIG(C,G,LHP0,DISPLAYA),CONFIG(D,G,LDI,DISPLAYA),CONFIG(D,G,LPP,DISPLAYA),
+    CONFIGEND(),
+    //  config 2, 18b RGB.
+    BRANCH(7),
+    CONFIG(C,E,LVS,DISPLAYA), CONFIG(D,E,LHS,DISPLAYA), CONFIG(D,E,LSPI,DISPLAYA),
+    CONFIGEND(),
+    // config 3, 8 & 9b CPU.
+    CONFIG(C,G,LHP1,DISPLAYA), CONFIG(C,G,LHP2,DISPLAYA), CONFIG(C,G,LVP1,DISPLAYA),
+    CONFIG(C,G,LHP0,DISPLAYA), CONFIG(D,G,LDI,DISPLAYA), CONFIG(D,G,LPP,DISPLAYA),
+    CONFIG(D,E,LPW0,DISPLAYA), CONFIG(D,E,LPW1,DISPLAYA), CONFIG(D,E,LPW2,DISPLAYA),
+    CONFIG(C,E,LSC1,DISPLAYA), CONFIG(C,E,LM1,DISPLAYA),
+    CONFIG(C,E,LVP0,DISPLAYA), CONFIGEND(),
+    // config 4.  SPI
+    CONFIG(D,E,LPW0,DISPLAYA), CONFIG(D,E,LPW2,DISPLAYA), CONFIG(C,E,LSC1,DISPLAYA),
+    CONFIG(C,E,LM0,DISPLAYA), CONFIG(C,E,LVP0,DISPLAYA), CONFIGEND(),
+    // Config 5. Panel 86
+    BRANCH(7),CONFIG(C,E,LSC1,DISPLAYA),CONFIG(C,E,LM1,DISPLAYA),CONFIGEND(),
+    // config 6. 16/18b smart panels
+    BRANCH(7),CONFIG(C,E,LDC,DISPLAYA),CONFIG(D,E,LSPI,DISPLAYA),CONFIGEND(),
+    MODULEDONE(),
+    //  subroutine 1. - 18b data + clock
+    CONFIG(C,F,LD0,DISPLAYA), CONFIG(C,F,LD1,DISPLAYA), CONFIG(C,F,LD2,DISPLAYA),
+    CONFIG(C,F,LD3,DISPLAYA), CONFIG(C,F,LD4,DISPLAYA), CONFIG(C,F,LD5,DISPLAYA),
+    CONFIG(C,F,LD6,DISPLAYA), CONFIG(C,F,LD7,DISPLAYA), CONFIG(C,F,LD8,DISPLAYA),
+    CONFIG(C,F,LD9,DISPLAYA), CONFIG(C,F,LD10,DISPLAYA), CONFIG(C,F,LD11,DISPLAYA),
+    CONFIG(C,F,LD12,DISPLAYA), CONFIG(C,F,LD13,DISPLAYA), CONFIG(C,F,LD14,DISPLAYA),
+    CONFIG(C,F,LD15,DISPLAYA), CONFIG(C,G,LD16,DISPLAYA), CONFIG(C,G,LD17,DISPLAYA),
+    CONFIG(C,E,LSC0,DISPLAYA), CONFIGEND(),
+    SUBROUTINESDONE(),  // This is required, since BRANCH is used.
+/* For handy reference, here is the complete list of CONFIG macros for the display
+   pad groups, in case any more configurations are defined in the future.
+    CONFIG(C,F,LD0,DISPLAYA), CONFIG(C,F,LD1,DISPLAYA), CONFIG(C,F,LD2,DISPLAYA),
+    CONFIG(C,F,LD3,DISPLAYA), CONFIG(C,F,LD4,DISPLAYA), CONFIG(C,F,LD5,DISPLAYA),
+    CONFIG(C,F,LD6,DISPLAYA), CONFIG(C,F,LD7,DISPLAYA), CONFIG(C,F,LD8,DISPLAYA),
+    CONFIG(C,F,LD9,DISPLAYA), CONFIG(C,F,LD10,DISPLAYA), CONFIG(C,F,LD11,DISPLAYA),
+    CONFIG(C,F,LD12,DISPLAYA),
+    CONFIG(C,F,LD13,DISPLAYA), CONFIG(C,F,LD14,DISPLAYA), CONFIG(C,F,LD15,DISPLAYA),
+    CONFIG(C,G,LD16,DISPLAYA), CONFIG(C,G,LD17,DISPLAYA),CONFIG(C,E,LSC0,DISPLAYA),
+    CONFIG(C,E,LVS,DISPLAYA), CONFIG(D,E,LHS,DISPLAYA), CONFIG(D,E,LSPI,DISPLAYA),
+    CONFIG(C,G,LHP1,DISPLAYA), CONFIG(C,G,LHP2,DISPLAYA), CONFIG(C,G,LHP0,DISPLAYA),
+    CONFIG(C,G,LVP1,DISPLAYA), CONFIG(D,G,LDI,DISPLAYA), CONFIG(D,G,LPP,DISPLAYA),
+    CONFIG(C,E,LCSN,DISPLAYA), CONFIG(C,E,LM1,DISPLAYA),CONFIG(C,E,LM0,DISPLAYA),
+    CONFIG(D,E,LPW0,DISPLAYA),CONFIG(D,E,LPW2,DISPLAYA), CONFIG(D,E,LPW1,DISPLAYA),
+    CONFIG(C,E,LVP0,DISPLAYA), CONFIG(C,E,LDC,DISPLAYA), CONFIG(C,E,LSC1,DISPLAYA),
+    CONFIG(D,E,LSDI,DISPLAYA),
+    */
+};
+
+const NvU32 g_Ap15Mux_Display2[] = {
+    CONFIGEND(),
+    //  config 1, 24b RGB.  Pure superset of Config2 (18b RGB)
+    BRANCH(2),
+    CONFIG(C,G,LHP1,DISPLAYB),CONFIG(C,G,LHP2,DISPLAYB),CONFIG(C,G,LVP1,DISPLAYB),
+    CONFIG(C,G,LHP0,DISPLAYB),CONFIG(D,G,LDI,DISPLAYB),CONFIG(D,G,LPP,DISPLAYB),
+    CONFIGEND(),
+    //  config 2, 18b RGB.
+    BRANCH(7),
+    CONFIG(C,E,LVS,DISPLAYB), CONFIG(D,E,LHS,DISPLAYB), CONFIG(D,E,LSPI,DISPLAYB),
+    CONFIGEND(),
+    // config 3, 8 & 9b CPU.
+    CONFIG(C,G,LHP1,DISPLAYB), CONFIG(C,G,LHP2,DISPLAYB), CONFIG(C,G,LVP1,DISPLAYB),
+    CONFIG(C,G,LHP0,DISPLAYB), CONFIG(D,G,LDI,DISPLAYB), CONFIG(D,G,LPP,DISPLAYB),
+    CONFIG(D,E,LPW0,DISPLAYB), CONFIG(D,E,LPW1,DISPLAYB), CONFIG(D,E,LPW2,DISPLAYB),
+    CONFIG(C,E,LSC1,DISPLAYB), CONFIG(C,E,LM1,DISPLAYB),
+    CONFIG(C,E,LVP0,DISPLAYB), CONFIGEND(),
+    // config 4.  SPI
+    CONFIG(D,E,LPW0,DISPLAYB), CONFIG(D,E,LPW2,DISPLAYB), CONFIG(C,E,LSC1,DISPLAYB),
+    CONFIG(C,E,LM0,DISPLAYB), CONFIG(C,E,LVP0,DISPLAYB), CONFIGEND(),
+    // Config 5. USed only for Sony VGA panel
+    BRANCH(7),CONFIG(C,E,LSC1,DISPLAYB),CONFIG(C,E,LM1,DISPLAYB),CONFIGEND(),
+    // config 6. 16/18b smart panels
+    BRANCH(7),CONFIG(C,E,LDC,DISPLAYB),CONFIG(D,E,LSPI,DISPLAYB),CONFIGEND(),
+    MODULEDONE(),
+    //  subroutine 1. (config 7)
+    CONFIG(C,F,LD0,DISPLAYB), CONFIG(C,F,LD1,DISPLAYB), CONFIG(C,F,LD2,DISPLAYB),
+    CONFIG(C,F,LD3,DISPLAYB), CONFIG(C,F,LD4,DISPLAYB), CONFIG(C,F,LD5,DISPLAYB),
+    CONFIG(C,F,LD6,DISPLAYB), CONFIG(C,F,LD7,DISPLAYB), CONFIG(C,F,LD8,DISPLAYB),
+    CONFIG(C,F,LD9,DISPLAYB), CONFIG(C,F,LD10,DISPLAYB), CONFIG(C,F,LD11,DISPLAYB),
+    CONFIG(C,F,LD12,DISPLAYB), CONFIG(C,F,LD13,DISPLAYB), CONFIG(C,F,LD14,DISPLAYB),
+    CONFIG(C,F,LD15,DISPLAYB), CONFIG(C,G,LD16,DISPLAYB), CONFIG(C,G,LD17,DISPLAYB),
+    CONFIG(C,E,LSC0,DISPLAYB), CONFIGEND(),
+    SUBROUTINESDONE(),
+};
+
+const NvU32* g_Ap15MuxDisplay[] = {
+    &g_Ap15Mux_Display1[0],
+    &g_Ap15Mux_Display2[0],
+    NULL
+};
+
+const NvU32 g_Ap15Mux_Cdev1[] = {
+    //  reset config - no-op
+    CONFIGEND(),
+    CONFIG(A,C,CDEV1,PLLA_OUT), CONFIGEND(),
+    CONFIG(A,C,CDEV1,OSC), CONFIGEND(),
+    MODULEDONE()
+};
+
+const NvU32 g_Ap15Mux_Cdev2[] = {
+    CONFIGEND(),
+    CONFIG(A,C,CDEV2,AHB_CLK), CONFIGEND(),
+    CONFIG(A,C,CDEV2,OSC), CONFIGEND(),
+    MODULEDONE()
+};
+
+const NvU32 g_Ap15Mux_Csus[] = {
+    CONFIGEND(),
+    CONFIG(A,C,CSUS,VI_SENSOR_CLK),  CONFIGEND(),
+    MODULEDONE()
+};
+
+const NvU32* g_Ap15MuxCdev[] =
+{
+    &g_Ap15Mux_Cdev1[0],
+    &g_Ap15Mux_Cdev2[0],
+    &g_Ap15Mux_Csus[0],
+    NULL
+};
+
+/*  Array of all the controller types in the system, pointing to the array of
+ *  instances of each controller.  Indexed using the NvRmIoModule value.
+ */
+static const NvU32** g_Ap15MuxControllers[] = {
+    &g_Ap15MuxAta[0],
+    &g_Ap15MuxCrt[0],
+    NULL, // no options for CSI
+    &g_Ap15MuxDap[0],
+    &g_Ap15MuxDisplay[0],
+    NULL, // no options for DSI
+    NULL, // no options for GPIO
+    &g_Ap15MuxHdcp[0],
+    &g_Ap15MuxHdmi[0],
+    &g_Ap15MuxHsi[0],
+    &g_Ap15MuxMmc[0],
+    NULL, // no options for I2S
+    &g_Ap15MuxI2c[0],
+    &g_Ap15MuxI2cPmu[0],
+    &g_Ap15MuxKbc[0],
+    &g_Ap15MuxMio[0],
+    &g_Ap15MuxNand[0],
+    &g_Ap15MuxPwm[0],
+    &g_Ap15MuxSdio[0],
+    &g_Ap15MuxSflash[0],
+    &g_Ap15MuxSlink[0],
+    &g_Ap15MuxSpdif[0],
+    &g_Ap15MuxSpi[0],
+    &g_Ap15MuxTwc[0],
+    NULL, //  no options for TVO
+    &g_Ap15MuxUart[0],
+    NULL, //  no options for USB
+    NULL, //  no options for VDD
+    &g_Ap15MuxVi[0],
+    NULL, //  no options for XIO
+    &g_Ap15MuxCdev[0],
+    NULL, //  no options for Ulpi
+    NULL, //  no options for one wire
+    NULL, //  no options for sync NOR
+    NULL, //  no options for PCI-E
+    NULL, //  no options for ETM
+    NULL, //  no options for TSENSor
+    &g_Ap15MuxBacklight[0],
+};
+
+NV_CT_ASSERT(NV_ARRAY_SIZE(g_Ap15MuxControllers)==NvOdmIoModule_Num);
+
+const NvU32***
+NvRmAp15GetPinMuxConfigs(NvRmDeviceHandle hDevice)
+{
+    NV_ASSERT(hDevice);
+    return (const NvU32***) g_Ap15MuxControllers;
+}
+
+/* Define the GPIO port/pin to tristate mappings */
+
+const NvU16 g_Ap15GpioPadGroupMapping[] =
+{
+    //  Port A
+    GPIO_TRISTATE(B,SDB), GPIO_TRISTATE(B,UCB), GPIO_TRISTATE(A,DAP2), GPIO_TRISTATE(A,DAP2),
+    GPIO_TRISTATE(A,DAP2), GPIO_TRISTATE(A,DAP2), GPIO_TRISTATE(B,SDD), GPIO_TRISTATE(B,SDD),
+    //  Port B
+    GPIO_TRISTATE(B,XM2A), GPIO_TRISTATE(B,XM2A), GPIO_TRISTATE(D,LPW0), GPIO_TRISTATE(C,LSC0),
+    GPIO_TRISTATE(B,SDC), GPIO_TRISTATE(B,SDC), GPIO_TRISTATE(B,SDC), GPIO_TRISTATE(B,SDC),
+    //  Port C
+    GPIO_TRISTATE(B,UCB), GPIO_TRISTATE(D,LPW1), GPIO_TRISTATE(B,UAD), GPIO_TRISTATE(B,UAD),
+    GPIO_TRISTATE(A,RM), GPIO_TRISTATE(A,RM), GPIO_TRISTATE(D,LPW2), GPIO_TRISTATE(B,XM2C),
+    //  Port D
+    GPIO_TRISTATE(B,SLXK), GPIO_TRISTATE(B,SLXA), GPIO_TRISTATE(B,SLXB), GPIO_TRISTATE(B,SLXC),
+    GPIO_TRISTATE(B,SLXD), GPIO_TRISTATE(A,DTA), GPIO_TRISTATE(A,DTC), GPIO_TRISTATE(A,DTC),
+    //  Port E
+    GPIO_TRISTATE(C,LD0), GPIO_TRISTATE(C,LD1), GPIO_TRISTATE(C,LD2), GPIO_TRISTATE(C,LD3),
+    GPIO_TRISTATE(C,LD4), GPIO_TRISTATE(C,LD5), GPIO_TRISTATE(C,LD6), GPIO_TRISTATE(C,LD7),
+    //  Port F
+    GPIO_TRISTATE(C, LD8), GPIO_TRISTATE(C,LD9), GPIO_TRISTATE(C,LD10), GPIO_TRISTATE(C,LD11),
+    GPIO_TRISTATE(C, LD12), GPIO_TRISTATE(C,LD13), GPIO_TRISTATE(C, LD14), GPIO_TRISTATE(C,LD15),
+    //  Port G
+    GPIO_TRISTATE(A,ATC), GPIO_TRISTATE(A,ATC),GPIO_TRISTATE(A,ATC), GPIO_TRISTATE(A,ATC),
+    GPIO_TRISTATE(A,ATC), GPIO_TRISTATE(A,ATC),GPIO_TRISTATE(A,ATC), GPIO_TRISTATE(A,ATC),
+    //  Port H
+    GPIO_TRISTATE(A,ATD), GPIO_TRISTATE(A,ATD),GPIO_TRISTATE(A,ATD), GPIO_TRISTATE(A,ATD),
+    GPIO_TRISTATE(B,ATE), GPIO_TRISTATE(B,ATE),GPIO_TRISTATE(B,ATE), GPIO_TRISTATE(B,ATE),
+    //  Port I
+    GPIO_TRISTATE(A,ATC), GPIO_TRISTATE(A,ATC), GPIO_TRISTATE(A,ATA), GPIO_TRISTATE(A,ATA),
+    GPIO_TRISTATE(A,ATA), GPIO_TRISTATE(A,ATB), GPIO_TRISTATE(A,ATB), GPIO_TRISTATE(A,ATC),
+    //  Port J
+    GPIO_TRISTATE(B,XM2S), GPIO_TRISTATE(D,LSPI), GPIO_TRISTATE(B,XM2S), GPIO_TRISTATE(D,LHS),
+    GPIO_TRISTATE(C,LVS), GPIO_TRISTATE(A,IRTX), GPIO_TRISTATE(A,IRRX), GPIO_TRISTATE(B,XM2A),
+    //  Port K
+    GPIO_TRISTATE(A,ATC), GPIO_TRISTATE(A,ATC), GPIO_TRISTATE(A,ATC), GPIO_TRISTATE(A,ATC),
+    GPIO_TRISTATE(A,ATC), GPIO_TRISTATE(B,SPDO), GPIO_TRISTATE(B,SPDI), GPIO_TRISTATE(B,XM2A),
+    //  Port L
+    GPIO_TRISTATE(A,DTD), GPIO_TRISTATE(A,DTD), GPIO_TRISTATE(A,DTD), GPIO_TRISTATE(A,DTD),
+    GPIO_TRISTATE(A,DTD), GPIO_TRISTATE(A,DTD), GPIO_TRISTATE(A,DTD), GPIO_TRISTATE(A,DTD),
+    //  Port M
+    GPIO_TRISTATE(C,LD16), GPIO_TRISTATE(C,LD17), GPIO_TRISTATE(C,LHP1), GPIO_TRISTATE(C,LHP2),
+    GPIO_TRISTATE(C,LVP1), GPIO_TRISTATE(C,LHP0), GPIO_TRISTATE(D,LDI), GPIO_TRISTATE(D,LPP),
+    //  Port N
+    GPIO_TRISTATE(A,DAP1), GPIO_TRISTATE(A,DAP1), GPIO_TRISTATE(A,DAP1), GPIO_TRISTATE(A,DAP1),
+    GPIO_TRISTATE(C,LCSN), GPIO_TRISTATE(D,LSDA), GPIO_TRISTATE(C,LDC), GPIO_TRISTATE(C,HDINT),
+    //  Port O
+    GPIO_TRISTATE(B,UAB), GPIO_TRISTATE(B,UAA), GPIO_TRISTATE(B,UAA), GPIO_TRISTATE(B,UAA),
+    GPIO_TRISTATE(B,UAA), GPIO_TRISTATE(B,UAB), GPIO_TRISTATE(B,UAB), GPIO_TRISTATE(B,UAB),
+    //  Port P
+    GPIO_TRISTATE(A,DAP3), GPIO_TRISTATE(A,DAP3), GPIO_TRISTATE(A,DAP3), GPIO_TRISTATE(A,DAP3),
+    GPIO_TRISTATE(A,DAP4), GPIO_TRISTATE(A,DAP4), GPIO_TRISTATE(A,DAP4), GPIO_TRISTATE(A,DAP4),
+    //  Port Q
+    GPIO_TRISTATE(A,KBCF), GPIO_TRISTATE(A,KBCF), GPIO_TRISTATE(A,KBCF), GPIO_TRISTATE(A,KBCF),
+    GPIO_TRISTATE(A,PMC), GPIO_TRISTATE(A,PMC), GPIO_TRISTATE(A,I2CP), GPIO_TRISTATE(A,I2CP),
+    //  Port R
+    GPIO_TRISTATE(A,KBCA), GPIO_TRISTATE(A,KBCA), GPIO_TRISTATE(A,KBCA), GPIO_TRISTATE(A,KBCE),
+    GPIO_TRISTATE(D,KBCD), GPIO_TRISTATE(D,KBCD), GPIO_TRISTATE(D,KBCD), GPIO_TRISTATE(A,KBCB),
+    //  Port S
+    GPIO_TRISTATE(A,KBCB), GPIO_TRISTATE(A,KBCB), GPIO_TRISTATE(A,KBCB), GPIO_TRISTATE(A,KBCB),
+    GPIO_TRISTATE(A,KBCB), GPIO_TRISTATE(B,KBCC), GPIO_TRISTATE(B,KBCC), GPIO_TRISTATE(B,KBCC),
+    //  Port T
+    GPIO_TRISTATE(A,DTD), GPIO_TRISTATE(A,CSUS), GPIO_TRISTATE(A,DTB), GPIO_TRISTATE(A,DTB),
+    GPIO_TRISTATE(A,PTA), GPIO_TRISTATE(A,PTA), GPIO_TRISTATE(A,PTA), GPIO_TRISTATE(A,PTA),
+    //  Port U
+    GPIO_TRISTATE(A,GPU), GPIO_TRISTATE(A,GPU), GPIO_TRISTATE(A,GPU), GPIO_TRISTATE(A,GPU),
+    GPIO_TRISTATE(A,GPU), GPIO_TRISTATE(A,GPU), GPIO_TRISTATE(A,GPU), GPIO_TRISTATE(D,GPU7),
+    //  Port V
+    GPIO_TRISTATE(B,UAC), GPIO_TRISTATE(B,UAC), GPIO_TRISTATE(B,UAC), GPIO_TRISTATE(B,UAC),
+    GPIO_TRISTATE(A,GPV), GPIO_TRISTATE(A,GPV), GPIO_TRISTATE(A,GPV), GPIO_TRISTATE(C,LVP0),
+    //  Port W
+    GPIO_TRISTATE(C,LM0), GPIO_TRISTATE(C,LM1), GPIO_TRISTATE(B,SPIG), GPIO_TRISTATE(B,SPIH),
+    GPIO_TRISTATE(A,CDEV1), GPIO_TRISTATE(A,CDEV2), GPIO_TRISTATE(B,UCA), GPIO_TRISTATE(B,UCA),
+    //  Port X
+    GPIO_TRISTATE(B,SPIA), GPIO_TRISTATE(B,SPIB), GPIO_TRISTATE(B,SPIC), GPIO_TRISTATE(B,SPIC),
+    GPIO_TRISTATE(B,SPID), GPIO_TRISTATE(B,SPIE), GPIO_TRISTATE(B,SPIE), GPIO_TRISTATE(B,SPIF)
+};
+
+NvBool
+NvRmAp15GetPinGroupForGpio(NvRmDeviceHandle hDevice,
+                           NvU32 Port,
+                           NvU32 Pin,
+                           NvU32 *pMapping)
+{
+    const NvU32 GpiosPerPort = 8;
+    NvU32 Index = Port*GpiosPerPort + Pin;
+
+    if ((Pin >= GpiosPerPort) || (Index >= NV_ARRAY_SIZE(g_Ap15GpioPadGroupMapping)))
+        return NV_FALSE;
+
+    *pMapping = (NvU32)g_Ap15GpioPadGroupMapping[Index];
+    return NV_TRUE;
+}
+
+// Top level AP15 clock enable register control macro
+#define CLOCK_ENABLE( rm, offset, field, EnableState ) \
+    do { \
+        regaddr = (CLK_RST_CONTROLLER_##offset##_0); \
+        NvOsMutexLock((rm)->CarMutex); \
+        reg = NV_REGR((rm), NvRmPrivModuleID_ClockAndReset, 0, regaddr); \
+        reg = NV_FLD_SET_DRF_NUM(CLK_RST_CONTROLLER, offset, field, EnableState, reg); \
+        NV_REGW((rm), NvRmPrivModuleID_ClockAndReset, 0, regaddr, reg); \
+        NvOsMutexUnlock((rm)->CarMutex); \
+    } while( 0 )
+
+void NvRmPrivAp15EnableExternalClockSource(
+    NvRmDeviceHandle hDevice,
+    const NvU32* Instance,
+    NvU32 Config,
+    NvBool ClockState)
+{
+    NvU32 MuxCtlShift, MuxCtlSet;
+    NvU32 reg;
+    NvU32 regaddr;
+
+    MuxCtlShift = NV_DRF_VAL(MUX,ENTRY, MUX_CTL_SHIFT, *Instance);
+    MuxCtlSet = NV_DRF_VAL(MUX,ENTRY, MUX_CTL_SET, *Instance);
+
+    if (MuxCtlShift == APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV1_SEL_SHIFT)
+    {
+        if (MuxCtlSet == APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV1_SEL_PLLA_OUT)
+        {
+            NvRmPrivExternalClockAttach(
+                hDevice, NvRmClockSource_PllA0, ClockState);
+        }
+        CLOCK_ENABLE(hDevice, MISC_CLK_ENB, CLK_ENB_DEV1_OUT, ClockState);
+    }
+    else if (MuxCtlShift == APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV2_SEL_SHIFT)
+    {
+        CLOCK_ENABLE(hDevice, MISC_CLK_ENB, CLK_ENB_DEV2_OUT, ClockState);
+    }
+    else if (MuxCtlShift == APB_MISC_PP_PIN_MUX_CTL_C_0_CSUS_SEL_SHIFT)
+    {
+        CLOCK_ENABLE(hDevice, MISC_CLK_ENB, CLK_ENB_SUS_OUT, ClockState);
+    }
+}
+
+NvU32
+NvRmPrivAp15GetExternalClockSourceFreq(
+    NvRmDeviceHandle hDevice,
+    const NvU32* Instance,
+    NvU32 Config)
+{
+    NvU32 MuxCtlShift, MuxCtlSet;
+    NvU32 ClockFreqInKHz = 0;
+
+    MuxCtlShift = NV_DRF_VAL(MUX,ENTRY, MUX_CTL_SHIFT, *Instance);
+    MuxCtlSet = NV_DRF_VAL(MUX,ENTRY, MUX_CTL_SET, *Instance);
+
+    if (MuxCtlShift == APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV1_SEL_SHIFT)
+    {
+        if (MuxCtlSet == APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV1_SEL_PLLA_OUT)
+            ClockFreqInKHz = NvRmPrivGetClockSourceFreq(NvRmClockSource_PllA0);
+
+        else if (MuxCtlSet == APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV1_SEL_OSC)
+            ClockFreqInKHz = NvRmPrivGetClockSourceFreq(NvRmClockSource_ClkM);
+    }
+    else if (MuxCtlShift == APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV2_SEL_SHIFT)
+    {
+        if (MuxCtlSet == APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV2_SEL_AHB_CLK)
+            ClockFreqInKHz = NvRmPrivGetClockSourceFreq(NvRmClockSource_Ahb);
+
+        else if (MuxCtlSet == APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV2_SEL_OSC)
+            ClockFreqInKHz = NvRmPrivGetClockSourceFreq(NvRmClockSource_ClkM);
+    }
+    else if (MuxCtlShift == APB_MISC_PP_PIN_MUX_CTL_C_0_CSUS_SEL_SHIFT)
+    {
+        if (MuxCtlSet == APB_MISC_PP_PIN_MUX_CTL_C_0_CSUS_SEL_VI_SENSOR_CLK)
+        {
+            if (NvRmPowerModuleClockConfig(hDevice, NvRmModuleID_Vi, 0, 0, 0,
+                NULL, 0, &ClockFreqInKHz, NvRmClockConfig_SubConfig) != NvSuccess)
+            {
+                ClockFreqInKHz = 0;
+            }
+        }
+    }
+    return ClockFreqInKHz;
+}
+
+/*  These functions will map from the RM's internal definition of module
+ *  instances to the ODM definition.  Since the RM is controller-centric,
+ *  and the ODM pin mux query is interface-centric, the mapping is not
+ *  always one-to-one */
+
+NvBool NvRmPrivAp15RmModuleToOdmModule(
+    NvRmModuleID RmModule,
+    NvOdmIoModule *OdmModule,
+    NvU32 *OdmInstance,
+    NvU32 *pCnt)
+{
+    NvRmModuleID Module = NVRM_MODULE_ID_MODULE(RmModule);
+
+    switch (Module)
+    {
+    case NvRmPrivModuleID_Mio_Exio:
+        *OdmModule = NvOdmIoModule_Mio;
+        *OdmInstance = 0; // since there is only one MIO bus on AP15/AP16.
+        *pCnt = 1;
+        return NV_TRUE;
+    default:
+        break;
+    }
+
+    return NV_FALSE;
+}
+
+NvError
+NvRmPrivAp15GetModuleInterfaceCaps(
+    NvOdmIoModule Module,
+    NvU32 Instance,
+    NvU32 PinMap,
+    void *pCaps)
+{
+    NvError err = NvError_NotSupported;
+
+    switch (Module)
+    {
+        case NvOdmIoModule_Sdio:
+        {
+            NvRmModuleSdmmcInterfaceCaps *pSdmmcCaps =
+                (NvRmModuleSdmmcInterfaceCaps *)pCaps;
+            if (Instance==0 &&
+                (PinMap == NvOdmSdioPinMap_Config2 ||
+                 PinMap == NvOdmSdioPinMap_Config5))
+                pSdmmcCaps->MmcInterfaceWidth = 8;
+            else if (Instance==1 && PinMap==NvOdmSdioPinMap_Config1)
+                pSdmmcCaps->MmcInterfaceWidth = 8;
+            else
+                pSdmmcCaps->MmcInterfaceWidth = 4;
+            err = NvSuccess;
+            break;
+        }
+        case NvOdmIoModule_Hsmmc:
+        {
+            NvRmModuleSdmmcInterfaceCaps *pSdmmcCaps =
+                (NvRmModuleSdmmcInterfaceCaps *)pCaps;
+            if (Instance==0 && PinMap==NvOdmHsmmcPinMap_Config2)
+                pSdmmcCaps->MmcInterfaceWidth = 4;
+            else
+                pSdmmcCaps->MmcInterfaceWidth = 8;
+            err = NvSuccess;
+            break;
+        }
+        case NvOdmIoModule_Pwm:
+        {
+            NvRmModulePwmInterfaceCaps *pPwmCaps =
+                (NvRmModulePwmInterfaceCaps *)pCaps;
+            err = NvSuccess;
+            if (Instance == 0 && (PinMap == NvOdmPwmPinMap_Config1))
+                pPwmCaps->PwmOutputIdSupported = 15;
+            else if (Instance == 0 && (PinMap == NvOdmPwmPinMap_Config2))
+                pPwmCaps->PwmOutputIdSupported = 13;
+            else if (Instance == 0 && (PinMap == NvOdmPwmPinMap_Config3))
+                pPwmCaps->PwmOutputIdSupported = 1;
+            else if (Instance == 0 && (PinMap == NvOdmPwmPinMap_Config4))
+                pPwmCaps->PwmOutputIdSupported = 12;
+            else
+            {
+                pPwmCaps->PwmOutputIdSupported = 0;
+                err = NvError_NotSupported;
+            }
+            break;
+        }
+        case NvOdmIoModule_Nand:
+        {
+            NvRmModuleNandInterfaceCaps *pNandCaps =
+                (NvRmModuleNandInterfaceCaps *)pCaps;
+            if (Instance == 0)
+            {
+                pNandCaps->IsCombRbsyMode = NV_TRUE;
+                pNandCaps->NandInterfaceWidth = 8;
+
+                if (PinMap == NvOdmNandPinMap_Config4)
+                    pNandCaps->IsCombRbsyMode = NV_FALSE;
+
+                if ((PinMap == NvOdmNandPinMap_Config1) ||
+                    (PinMap == NvOdmNandPinMap_Config2))
+                    pNandCaps->NandInterfaceWidth = 16;
+
+                err =  NvSuccess;
+            }
+            else
+            {
+                NV_ASSERT(NV_FALSE);
+                err = NvError_NotSupported;
+            }
+            break;
+        }
+        case NvOdmIoModule_Uart:
+        {
+            NvRmModuleUartInterfaceCaps *pUartCaps =
+                (NvRmModuleUartInterfaceCaps *)pCaps;
+            err =  NvSuccess;
+            if (Instance == 0)
+            {
+                if (PinMap == NvOdmUartPinMap_Config1)
+                    pUartCaps->NumberOfInterfaceLines = 8;
+                else if (PinMap == NvOdmUartPinMap_Config3)
+                    pUartCaps->NumberOfInterfaceLines = 7;
+                else if ((PinMap == NvOdmUartPinMap_Config2) ||
+                         (PinMap == NvOdmUartPinMap_Config4))
+                    pUartCaps->NumberOfInterfaceLines = 4;
+                else if ((PinMap == NvOdmUartPinMap_Config5) ||
+                         (PinMap == NvOdmUartPinMap_Config6))
+                    pUartCaps->NumberOfInterfaceLines = 2;
+                else
+                    pUartCaps->NumberOfInterfaceLines = 0;
+            }
+            else if (Instance == 1)
+            {
+                if ((PinMap == NvOdmUartPinMap_Config1) ||
+                    (PinMap == NvOdmUartPinMap_Config2))
+                    pUartCaps->NumberOfInterfaceLines = 4;
+                else if (PinMap == NvOdmUartPinMap_Config3)
+                    pUartCaps->NumberOfInterfaceLines = 2;
+                else
+                    pUartCaps->NumberOfInterfaceLines = 0;
+            }
+            else if (Instance == 2)
+            {
+                if (PinMap == NvOdmUartPinMap_Config1)
+                    pUartCaps->NumberOfInterfaceLines = 4;
+                else if (PinMap == NvOdmUartPinMap_Config2)
+                    pUartCaps->NumberOfInterfaceLines = 2;
+                else
+                    pUartCaps->NumberOfInterfaceLines = 0;
+            }
+            else
+            {
+                NV_ASSERT(NV_FALSE);
+                err = NvError_NotSupported;
+            }
+            break;
+        }
+        default:
+            break;
+    }
+    return err;
+}
+
+NvError
+NvRmAp15GetStraps(
+    NvRmDeviceHandle hDevice,
+    NvRmStrapGroup StrapGroup,
+    NvU32* pStrapValue)
+{
+    NvU32 reg = NV_REGR(
+        hDevice, NvRmModuleID_Misc, 0, APB_MISC_PP_STRAPPING_OPT_A_0);
+
+    switch (StrapGroup)
+    {
+        case NvRmStrapGroup_RamCode:
+            reg = NV_DRF_VAL(APB_MISC_PP, STRAPPING_OPT_A, RAM_CODE, reg);
+            break;
+        default:
+            return NvError_NotSupported;
+    }
+    *pStrapValue = reg;
+    return NvSuccess;
+}
+
diff --git a/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_pinmux_utils.h b/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_pinmux_utils.h
new file mode 100644
index 000000000000..f9fd782a3315
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_pinmux_utils.h
@@ -0,0 +1,147 @@
+/*
+ * Copyright (c) 2009-2010 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef AP15RM_PINMUX_UTILS_H
+#define AP15RM_PINMUX_UTILS_H
+
+/*
+ * ap15rm_pinmux_utils.h defines the pinmux macros to implement for the resource
+ * manager.
+ */
+
+#include "nvrm_pinmux_utils.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif  /* __cplusplus */
+
+/* When the state is BranchLink, this is the number of words to increment
+ * the current "PC"
+ */
+#define MUX_ENTRY_0_BRANCH_ADDRESS_RANGE 31:2
+//  The incr1 offset from TRISTATE_REG_A_0 to the pad group's tristate register
+#define MUX_ENTRY_0_TS_OFFSET_RANGE 31:26
+//  The bit position within the tristate register for the pad group
+#define MUX_ENTRY_0_TS_SHIFT_RANGE 25:21
+//  The incr1 offset from PIN_MUX_CTL_A_0 to the pad group's pin mux control register
+#define MUX_ENTRY_0_MUX_CTL_OFFSET_RANGE 20:17
+//  The bit position within the pin mux control register for the pad group
+#define MUX_ENTRY_0_MUX_CTL_SHIFT_RANGE 16:12
+//  The mask for the pad group -- expanded to 3b for forward-compatibility
+#define MUX_ENTRY_0_MUX_CTL_MASK_RANGE 10:8
+//  When a pad group needs to be owned (or disowned), this value is applied
+#define MUX_ENTRY_0_MUX_CTL_SET_RANGE 7:5
+//  This value is compared against, to determine if the pad group should be disowned
+#define MUX_ENTRY_0_MUX_CTL_UNSET_RANGE 4:2
+//  for extended opcodes, this field is set with the extended opcode
+#define MUX_ENTRY_0_OPCODE_EXTENSION_RANGE 3:2
+//  The state for this entry
+#define MUX_ENTRY_0_STATE_RANGE 1:0
+
+/*  This macro is used to generate 32b value to program the  tristate& pad mux control
+ *  registers for config/unconfig for a padgroup
+ */
+#define PIN_MUX_ENTRY(TSOFF,TSSHIFT,MUXOFF,MUXSHIFT,MUXMASK,MUXSET,MUXUNSET,STAT) \
+    (NV_DRF_NUM(MUX, ENTRY, TS_OFFSET, TSOFF) | NV_DRF_NUM(MUX, ENTRY, TS_SHIFT, TSSHIFT) | \
+    NV_DRF_NUM(MUX, ENTRY, MUX_CTL_OFFSET, MUXOFF) | NV_DRF_NUM(MUX, ENTRY, MUX_CTL_SHIFT, MUXSHIFT) | \
+    NV_DRF_NUM(MUX, ENTRY,MUX_CTL_MASK, MUXMASK) | NV_DRF_NUM(MUX, ENTRY,MUX_CTL_SET, MUXSET) | \
+    NV_DRF_NUM(MUX, ENTRY, MUX_CTL_UNSET,MUXUNSET) | NV_DRF_NUM(MUX, ENTRY, STATE,STAT))
+
+//  This is used to program the tristate & pad mux control registers for a pad group
+#define CONFIG_VAL(TRISTATE_REG, MUXCTL_REG, PADGROUP, MUX) \
+    (PIN_MUX_ENTRY(((APB_MISC_PP_TRISTATE_REG_##TRISTATE_REG##_0 - APB_MISC_PP_TRISTATE_REG_A_0)>>2), \
+                APB_MISC_PP_TRISTATE_REG_##TRISTATE_REG##_0_Z_##PADGROUP##_SHIFT, \
+                ((APB_MISC_PP_PIN_MUX_CTL_##MUXCTL_REG##_0 - APB_MISC_PP_PIN_MUX_CTL_A_0) >> 2), \
+                APB_MISC_PP_PIN_MUX_CTL_##MUXCTL_REG##_0_##PADGROUP##_SEL_SHIFT, \
+                APB_MISC_PP_PIN_MUX_CTL_##MUXCTL_REG##_0_##PADGROUP##_SEL_DEFAULT_MASK, \
+                APB_MISC_PP_PIN_MUX_CTL_##MUXCTL_REG##_0_##PADGROUP##_SEL_##MUX, \
+                0, PinMuxConfig_Set))
+
+/* This macro is used to compare a pad group against a potentially conflicting
+ * enum (where the conflict is caused by setting a new config), and to resolve
+ * the conflict by setting the conflicting pad group to a different,
+ * non-conflicting option. Read this as: if (PADGROUP) is equal to
+ * (CONFLICTMUX), replace it with (RESOLUTIONMUX)
+ */
+#define UNCONFIG_VAL(MUXCTL_REG, PADGROUP, CONFLICTMUX, RESOLUTIONMUX) \
+    (PIN_MUX_ENTRY(0, 0, \
+                  ((APB_MISC_PP_PIN_MUX_CTL_##MUXCTL_REG##_0 - APB_MISC_PP_PIN_MUX_CTL_A_0) >> 2), \
+                  APB_MISC_PP_PIN_MUX_CTL_##MUXCTL_REG##_0_##PADGROUP##_SEL_SHIFT, \
+                  APB_MISC_PP_PIN_MUX_CTL_##MUXCTL_REG##_0_##PADGROUP##_SEL_DEFAULT_MASK, \
+                  APB_MISC_PP_PIN_MUX_CTL_##MUXCTL_REG##_0_##PADGROUP##_SEL_##RESOLUTIONMUX, \
+                  APB_MISC_PP_PIN_MUX_CTL_##MUXCTL_REG##_0_##PADGROUP##_SEL_##CONFLICTMUX, \
+                  PinMuxConfig_Unset))
+// TODO: Need to implement in PINMUX_DEBUG_MODE
+#define TRISTATE_UNUSED(PADGROUP, TRISTATE_REG) \
+        (PIN_MUX_ENTRY(((APB_MISC_PP_TRISTATE_REG_##TRISTATE_REG##_0 - APB_MISC_PP_TRISTATE_REG_A_0)>>2), \
+                APB_MISC_PP_TRISTATE_REG_##TRISTATE_REG##_0_Z_##PADGROUP##_SHIFT, \
+                0, 0, 0, 0, 0, -1))
+
+
+#if NVRM_PINMUX_DEBUG_FLAG
+#define CONFIG(TRISTATE_REG, MUXCTL_REG, PADGROUP, MUX) \
+    (CONFIG_VAL(TRISTATE_REG, MUXCTL_REG, PADGROUP, MUX)), \
+    (NvU32)(const void*)(#MUXCTL_REG "_0_" #PADGROUP "_SEL to " #MUX), \
+    (NvU32)(const void*)(#TRISTATE_REG "_0_Z_" #PADGROUP)
+
+#define UNCONFIG(MUXCTL_REG, PADGROUP, CONFLICTMUX, RESOLUTIONMUX) \
+    (UNCONFIG_VAL(MUXCTL_REG, PADGROUP, CONFLICTMUX, RESOLUTIONMUX)), \
+    (NvU32)(const void*)(#MUXCTL_REG "_0_" #PADGROUP "_SEL from " #CONFLICTMUX " to " #RESOLUTIONMUX), \
+    (NvU32)(const void*)(NULL)
+#else
+#define CONFIG(TRISTATE_REG, MUXCTL_REG, PADGROUP, MUX) \
+    (CONFIG_VAL(TRISTATE_REG, MUXCTL_REG, PADGROUP, MUX))
+#define UNCONFIG(MUXCTL_REG, PADGROUP, CONFLICTMUX, RESOLUTIONMUX) \
+    (UNCONFIG_VAL(MUXCTL_REG, PADGROUP, CONFLICTMUX, RESOLUTIONMUX))
+#endif
+
+//  The below entries define the table format for GPIO Port/Pin-to-Tristate register mappings
+//  Each table entry is 16b, and one is stored for every GPIO Port/Pin on the chip
+#define MUX_GPIOMAP_0_TS_OFFSET_RANGE 15:10
+//  Defines where in the 32b register the tristate control is located
+#define MUX_GPIOMAP_0_TS_SHIFT_RANGE  4:0
+
+#define TRISTATE_ENTRY(TSOFFS, TSSHIFT) \
+    ((NvU16)(NV_DRF_NUM(MUX,GPIOMAP,TS_OFFSET,(TSOFFS)) | \
+             NV_DRF_NUM(MUX,GPIOMAP,TS_SHIFT,(TSSHIFT))))
+
+#define GPIO_TRISTATE(TRIREG,PADGROUP) \
+    (TRISTATE_ENTRY(((APB_MISC_PP_TRISTATE_REG_##TRIREG##_0 - APB_MISC_PP_TRISTATE_REG_A_0)>>2), \
+        APB_MISC_PP_TRISTATE_REG_##TRIREG##_0_Z_##PADGROUP##_SHIFT))
+
+#ifdef __cplusplus
+}
+#endif  /* __cplusplus */
+
+#endif // AP15RM_PINMUX_UTILS_H
+
diff --git a/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_pmc_scratch_map.h b/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_pmc_scratch_map.h
new file mode 100644
index 000000000000..38cae693e547
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_pmc_scratch_map.h
@@ -0,0 +1,73 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/**
+ * @file
+ * @brief <b>nVIDIA Driver Development Kit:
+ *           Power Management Controller (PMC) scratch registers fields
+ *           definitions</b>
+ *
+ * @b Description: Defines SW-allocated fields in the PMC scratch registers
+ *  shared by boot and power management code in RM and OAL.
+ *
+ */
+
+
+#ifndef INCLUDED_AP15RM_PMC_SCRATCH_MAP_H
+#define INCLUDED_AP15RM_PMC_SCRATCH_MAP_H
+
+/*
+ * Scratch registers offsets are part of the HW specification in the below
+ * include file. Scratch registers fields are defined in this header via
+ * bit ranges compatible with nvrm_drf macros.
+ */
+#include "ap15/arapbpm.h"
+
+// Register APBDEV_PMC_SCRATCH0_0 (this is the only scratch register cleared on reset)
+//
+
+// RM clients combined power state (bits 4-7)
+#define APBDEV_PMC_SCRATCH0_0_RM_PWR_STATE_RANGE        11:8
+#define APBDEV_PMC_SCRATCH0_0_RM_LOAD_TRANSPORT_RANGE   15:12
+#define APBDEV_PMC_SCRATCH0_0_RM_DFS_FLAG_RANGE         27:16
+#define APBDEV_PMC_SCRATCH0_0_UPDATE_MODE_FLAG_RANGE     29:28
+#define APBDEV_PMC_SCRATCH0_0_OAL_RTC_INIT_RANGE        30:30
+#define APBDEV_PMC_SCRATCH0_0_RST_PWR_DET_RANGE         31:31
+
+// Register APBDEV_PMC_SCRATCH20_0, used to store the ODM customer data from the BCT
+#define APBDEV_PMC_SCRATCH20_0_BCT_ODM_DATA_RANGE       31:0
+
+// Register APBDEV_PMC_SCRATCH21_0
+//
+#define APBDEV_PMC_SCRATCH21_0_LP2_TIME_US              31:0
+
+#endif // INCLUDED_AP15RM_PMC_SCRATCH_MAP_H
diff --git a/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_power.c b/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_power.c
new file mode 100644
index 000000000000..d9fd9f3d1251
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_power.c
@@ -0,0 +1,663 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/**
+ * @file
+ * @brief <b>nVIDIA Driver Development Kit:
+ *           Power Resource manager </b>
+ *
+ * @b Description: Implements the interface of the NvRM Power.
+ *
+ */
+
+#include "nvrm_power_private.h"
+#include "nvrm_pmu.h"
+#include "nvrm_pmu_private.h"
+#include "nvassert.h"
+#include "nvrm_drf.h"
+#include "nvrm_hwintf.h"
+#include "nvodm_query_discovery.h"
+#include "ap15rm_private.h"
+#include "ap15rm_clocks.h"
+#include "ap15/arapbpm.h"
+#include "ap15/project_relocation_table.h"
+
+// TODO: Always Disable before check-in
+// Module debug: 0=disable, 1=enable
+#define NVRM_ENABLE_PRINTF (0)
+
+#if (NV_DEBUG && NVRM_ENABLE_PRINTF)
+#define NVRM_POWER_PRINTF(x)   NvOsDebugPrintf x
+#else
+#define NVRM_POWER_PRINTF(x)
+#endif
+
+
+#if !NV_OAL
+/*****************************************************************************/
+/*****************************************************************************/
+
+#define NV_POWER_GATE_TD    (1)
+#define NV_POWER_GATE_PCIE  (1)
+//  TODO: check VDE/BSEV/NSEA voltage control calls before enabling
+#define NV_POWER_GATE_VDE   (0)
+//  TODO: check MPE voltage control calls before enabling
+#define NV_POWER_GATE_MPE   (0)
+
+// Power Group -to- Power Gating Ids mapping
+static const NvU32* s_PowerGroupIds = NULL;
+static NvBool s_UngateOnResume[NV_POWERGROUP_MAX] = {0};
+
+/*****************************************************************************/
+
+static NvBool IsRunTimePowerGateSupported(NvU32 PowerGroup)
+{
+    // 1st check h/w support capabilities
+    NV_ASSERT(s_PowerGroupIds);
+    if (s_PowerGroupIds[PowerGroup] == NV_POWERGROUP_INVALID)
+        return NV_FALSE;
+
+    // now check s/w support
+    switch (PowerGroup)
+    {
+        case NV_POWERGROUP_TD:
+            return NV_POWER_GATE_TD;
+        case NV_POWERGROUP_PCIE:
+            return NV_POWER_GATE_PCIE;
+        case NV_POWERGROUP_VDE:
+            return NV_POWER_GATE_VDE;
+        case NV_POWERGROUP_MPE:
+            return NV_POWER_GATE_MPE;
+        default:
+            return NV_FALSE;
+    }
+}
+
+static NvBool IsSuspendPowerGateForced(NvU32 PowerGroup)
+{
+    // 1st check h/w support capabilities
+    NV_ASSERT(s_PowerGroupIds);
+    if (s_PowerGroupIds[PowerGroup] == NV_POWERGROUP_INVALID)
+        return NV_FALSE;
+
+    // now check s/w support
+    switch (PowerGroup)
+    {
+        case NV_POWERGROUP_TD:
+        case NV_POWERGROUP_PCIE:
+        case NV_POWERGROUP_VDE:
+        case NV_POWERGROUP_VE:
+        case NV_POWERGROUP_MPE:
+            return NV_TRUE;
+        default:
+            return NV_FALSE;
+    }
+}
+
+static void PowerGroupResetControl(
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvU32 PowerGroup,
+    NvBool Assert)
+{
+    switch (PowerGroup)
+    {
+        case NV_POWERGROUP_TD:
+            NvRmModuleResetWithHold(hRmDeviceHandle, NvRmModuleID_3D, Assert);
+            break;
+        case NV_POWERGROUP_PCIE:
+            NvRmModuleResetWithHold(
+                hRmDeviceHandle, NvRmPrivModuleID_Pcie, Assert);
+            NvRmModuleResetWithHold(
+                hRmDeviceHandle, NvRmPrivModuleID_Afi, Assert);
+            if (Assert)     // Keep PCIEXCLK in reset - let driver to take it out
+            {
+                NvRmModuleResetWithHold(
+                    hRmDeviceHandle, NvRmPrivModuleID_PcieXclk, Assert);
+            }
+            NvRmPrivAp20PowerPcieXclkControl(hRmDeviceHandle, !Assert);
+            break;
+        case NV_POWERGROUP_VDE:
+            NvRmModuleResetWithHold(hRmDeviceHandle, NvRmModuleID_Vde, Assert);
+            break;
+        case NV_POWERGROUP_VE:
+            NvRmModuleResetWithHold(hRmDeviceHandle, NvRmModuleID_Vi, Assert);
+            NvRmModuleResetWithHold(hRmDeviceHandle, NvRmModuleID_Csi, Assert);
+            NvRmModuleResetWithHold(hRmDeviceHandle, NvRmModuleID_Isp, Assert);
+            NvRmModuleResetWithHold(hRmDeviceHandle, NvRmModuleID_Epp, Assert);
+            break;
+        case NV_POWERGROUP_MPE:
+            NvRmModuleResetWithHold(hRmDeviceHandle, NvRmModuleID_Mpe, Assert);
+            break;
+        default:
+            break;
+    }
+}
+
+static void  PowerGroupClockControl(
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvU32 PowerGroup,
+    NvBool Enable)
+{
+    ModuleClockState ClockState =
+        Enable ? ModuleClockState_Enable : ModuleClockState_Disable;
+
+    switch (PowerGroup)
+    {
+        case NV_POWERGROUP_TD:
+            NvRmPrivEnableModuleClock(
+                hRmDeviceHandle, NvRmModuleID_3D, ClockState);
+            break;
+        case NV_POWERGROUP_PCIE:
+            NvRmPrivEnableModuleClock(
+                hRmDeviceHandle, NvRmPrivModuleID_Pcie, ClockState);
+            break;
+        case NV_POWERGROUP_VDE:
+            NvRmPrivEnableModuleClock(
+                hRmDeviceHandle, NvRmModuleID_Vde, ClockState);
+            break;
+        case NV_POWERGROUP_VE:
+            NvRmPrivEnableModuleClock(
+                hRmDeviceHandle, NvRmModuleID_Vi, ClockState);
+            NvRmPrivEnableModuleClock(
+                hRmDeviceHandle, NvRmModuleID_Csi, ClockState);
+            NvRmPrivEnableModuleClock(
+                hRmDeviceHandle, NvRmModuleID_Isp, ClockState);
+            NvRmPrivEnableModuleClock(
+                hRmDeviceHandle, NvRmModuleID_Epp, ClockState);
+            break;
+        case NV_POWERGROUP_MPE:
+            NvRmPrivEnableModuleClock(
+                hRmDeviceHandle, NvRmModuleID_Mpe, ClockState);
+            break;
+        default:
+            break;
+    }
+}
+
+static void
+PowerGroupPowerControl(
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvU32 PowerGroup,
+    NvBool Enable)
+{
+    NvU32 reg, Id, Mask, Status;
+
+    // Do nothing if not SoC platform
+    NV_ASSERT(hRmDeviceHandle);
+    if (NvRmPrivGetExecPlatform(hRmDeviceHandle) != ExecPlatform_Soc)
+        return;
+
+    // Do nothing if power group is already in requested state
+    NV_ASSERT(s_PowerGroupIds[PowerGroup] != NV_POWERGROUP_INVALID);
+    Id = s_PowerGroupIds[PowerGroup];
+    Mask = (0x1 << Id);
+    Status = Mask & NV_REGR(hRmDeviceHandle, NvRmModuleID_Pmif, 0,
+                            APBDEV_PMC_PWRGATE_STATUS_0);
+    if (Enable == (Status != 0x0))
+        return;
+
+    /*
+     * Gating procedure:
+     * - assert resets to all modules in power group
+     * - toggle power gate
+     *
+     * Ungating procedure
+     * - assert resets to all modules in power group (redundunt)
+     * - toggle power gate
+     * - enable clocks to all modules in power group
+     * - reset propagation delay
+     * - remove clamping
+     * - de-assert reset to all modules in power group
+     * - disable clocks to all modules in power group
+     *
+     * Special note on toggle timers( shared with OAL which does CPU power
+     * gating): per convention with OAL default settings are never changed.
+     */
+    PowerGroupResetControl(hRmDeviceHandle, PowerGroup, NV_TRUE);
+
+    reg = NV_DRF_DEF(APBDEV_PMC, PWRGATE_TOGGLE, START, ENABLE) | Id;
+    NV_REGW(hRmDeviceHandle, NvRmModuleID_Pmif, 0,
+            APBDEV_PMC_PWRGATE_TOGGLE_0, reg);
+    for (;;)
+    {
+        reg = NV_REGR(hRmDeviceHandle, NvRmModuleID_Pmif, 0,
+                      APBDEV_PMC_PWRGATE_STATUS_0);
+        if (Status != (reg & Mask))
+            break;
+    }
+    if (Enable)
+    {
+        PowerGroupClockControl(hRmDeviceHandle, PowerGroup, NV_TRUE);
+        NvOsWaitUS(NVRM_RESET_DELAY);
+
+        // PCIE and VDE clamping masks are swapped relatively to
+        // partition Ids (bug 602975)
+        if (PowerGroup == NV_POWERGROUP_PCIE)
+            Mask = 0x1 << s_PowerGroupIds[NV_POWERGROUP_VDE];
+        else if (PowerGroup == NV_POWERGROUP_VDE)
+            Mask = 0x1 << s_PowerGroupIds[NV_POWERGROUP_PCIE];
+
+        NV_REGW(hRmDeviceHandle, NvRmModuleID_Pmif, 0,
+                APBDEV_PMC_REMOVE_CLAMPING_CMD_0, Mask);
+        for (;;)
+        {
+            reg = NV_REGR(hRmDeviceHandle, NvRmModuleID_Pmif, 0,
+                          APBDEV_PMC_REMOVE_CLAMPING_CMD_0);
+            if (reg == 0)
+                break;
+        }
+        PowerGroupResetControl(hRmDeviceHandle, PowerGroup, NV_FALSE);
+        PowerGroupClockControl(hRmDeviceHandle, PowerGroup, NV_FALSE);
+    }
+}
+
+void
+NvRmPrivPowerGroupControl(
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvU32 PowerGroup,
+    NvBool Enable)
+{
+    NVRM_POWER_PRINTF(("%s Power Group %d\n",
+                       (Enable ? "Enable" : "Disable"), PowerGroup));
+
+    // Do nothing if dynamic power gating is not supported for this group
+    if (PowerGroup >= NV_POWERGROUP_MAX)
+        return;             // "virtual" groups are always On
+    if (!IsRunTimePowerGateSupported(PowerGroup))
+        return;
+
+    // Gate/ungate the group
+    PowerGroupPowerControl(hRmDeviceHandle, PowerGroup, Enable);
+}
+
+NvRmMilliVolts
+NvRmPrivPowerGroupGetVoltage(
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvU32 PowerGroup)
+{
+    NvRmMilliVolts Voltage = NvRmVoltsUnspecified;
+    if (PowerGroup >= NV_POWERGROUP_MAX)
+        return Voltage;     // "virtual" groups are always On
+
+    // Do not check non-gated power group  - it is On by definition
+    if (s_PowerGroupIds[PowerGroup] != NV_POWERGROUP_INVALID)
+    {
+        NvU32 reg = NV_REGR(
+            hRmDeviceHandle, NvRmModuleID_Pmif, 0, APBDEV_PMC_PWRGATE_STATUS_0);
+        if ((reg & (0x1 << s_PowerGroupIds[PowerGroup])) == 0x0)
+        {
+            // Specified power group is gated
+            Voltage = NvRmVoltsOff;
+        }
+    }
+    return Voltage;
+}
+
+void NvRmPrivPowerGroupSuspend(NvRmDeviceHandle hRmDeviceHandle)
+{
+    NvU32 i;
+
+    // On suspend entry power gate core group that is still On, but must be Off
+    for (i = 0; i < NV_POWERGROUP_MAX; i++)
+    {
+        if (!IsSuspendPowerGateForced(i) ||
+            (NvRmPrivPowerGroupGetVoltage(hRmDeviceHandle, i) == NvRmVoltsOff))
+        {
+            s_UngateOnResume[i] = NV_FALSE;
+            continue;
+        }
+
+        s_UngateOnResume[i] = NV_TRUE;
+        PowerGroupPowerControl(hRmDeviceHandle, i, NV_FALSE);
+    }
+}
+
+void NvRmPrivPowerGroupResume(NvRmDeviceHandle hRmDeviceHandle)
+{
+    NvU32 i;
+
+    // On resume ungate core group that was forcefully gated on suspend entry
+    for (i = 0; i < NV_POWERGROUP_MAX; i++)
+    {
+        if (s_UngateOnResume[i] == NV_TRUE)
+            PowerGroupPowerControl(hRmDeviceHandle, i, NV_TRUE);
+    }
+}
+
+void NvRmPrivPowerGroupControlInit(NvRmDeviceHandle hRmDeviceHandle)
+{
+    NvU32 i, Size;
+
+    // Init chip specific power group map
+    if ((hRmDeviceHandle->ChipId.Id == 0x15) ||
+        (hRmDeviceHandle->ChipId.Id == 0x16))
+    {
+        NvRmPrivAp15PowerGroupTableInit(&s_PowerGroupIds, &Size);
+    }
+    else if (hRmDeviceHandle->ChipId.Id == 0x20)
+    {
+        NvRmPrivAp20PowerGroupTableInit(&s_PowerGroupIds, &Size);
+    }
+    else
+    {
+        NV_ASSERT(!"Unsupported chip ID");
+    }
+    NV_ASSERT(Size == NV_POWERGROUP_MAX);
+
+    // Power gate supported partitions
+    for (i = 0; i < NV_POWERGROUP_MAX; i++)
+        NvRmPrivPowerGroupControl(hRmDeviceHandle, i, NV_FALSE);
+}
+
+#endif  // !NV_OAL
+/*****************************************************************************/
+/*****************************************************************************/
+
+#define NV_NO_IOPOWER_CONTROL (1)
+#define NV_RAIL_ADDR_INVALID ((NvU32)-1)
+
+typedef struct IoPowerDetectInfoRec
+{
+    // SoC Power rail GUID
+    NvU64 PowerRailId;
+
+    // IO Power rail disable bit mask
+    NvU32 DisableRailMask;
+
+    // IO Power Detect cell enable bit mask
+    NvU32 EnablePwrDetMask;
+
+    // PMU Rail Address
+    NvU32 PmuRailAddress;
+
+} IoPowerDetectInfo;
+
+static IoPowerDetectInfo s_IoPowerDetectMap[] =
+{
+    {NV_VDD_SYS_ODM_ID,  (0x1 << 0), (0x1 << 0), 0},
+    {NV_VDD_NAND_ODM_ID, (0x1 << 1), (0x1 << 1), 0},
+    {NV_VDD_UART_ODM_ID, (0x1 << 2), (0x1 << 2), 0},
+    {NV_VDD_BB_ODM_ID,   (0x1 << 3), (0x1 << 3), 0},
+
+    {NV_VDD_VI_ODM_ID,   (0x1 << 4), (0x1 << 4), 0},
+    {NV_VDD_AUD_ODM_ID,  (0x1 << 5), (0x1 << 5), 0},
+    {NV_VDD_LCD_ODM_ID,  (0x1 << 6), (0x1 << 6), 0},
+    {NV_VDD_DDR_ODM_ID,  (0x1 << 7), (0x1 << 7), 0},
+
+    {NV_VDD_SDIO_ODM_ID, (0x1 << 8), (0x1 << 8), 0},
+    {NV_VDD_MIPI_ODM_ID, (0x1 << 9),      (0x0), 0} // No detect cell
+};
+
+static void IoPowerMapRail(
+    NvU32 PmuRailAddress,
+    NvU32* pIoPwrDetectMask,
+    NvU32* pNoIoPwrMask)
+{
+    NvU32 i;
+    *pIoPwrDetectMask = 0;
+    *pNoIoPwrMask = 0;
+
+    // Find all power detect cells and controls on this IO rail
+    for (i = 0; i < NV_ARRAY_SIZE(s_IoPowerDetectMap); i++)
+    {
+        if (s_IoPowerDetectMap[i].PmuRailAddress == PmuRailAddress)
+        {
+            *pIoPwrDetectMask |= s_IoPowerDetectMap[i].EnablePwrDetMask;
+            *pNoIoPwrMask |= s_IoPowerDetectMap[i].DisableRailMask;
+        }
+    }
+}
+
+void NvRmPrivIoPowerControlInit(NvRmDeviceHandle hRmDeviceHandle)
+{
+    NvU32 i, v;
+    NvU32 NoIoPwrMask = 0;
+    const NvOdmPeripheralConnectivity* pPmuRail = NULL;
+
+    if (NvRmPrivGetExecPlatform(hRmDeviceHandle) != ExecPlatform_Soc)
+    {
+        // Invalidate IO Power detect map if not SoC platform
+        for (i = 0; i < NV_ARRAY_SIZE(s_IoPowerDetectMap); i++)
+            s_IoPowerDetectMap[i].PmuRailAddress = NV_RAIL_ADDR_INVALID;
+        return;
+    }
+
+    for (i = 0; i < NV_ARRAY_SIZE(s_IoPowerDetectMap); i++)
+    {
+        // Fill in PMU rail addresses in IO Power detect map
+        pPmuRail = NvOdmPeripheralGetGuid(s_IoPowerDetectMap[i].PowerRailId);
+        NV_ASSERT(pPmuRail && pPmuRail->NumAddress);
+        s_IoPowerDetectMap[i].PmuRailAddress = pPmuRail->AddressList[0].Address;
+
+        // Find all unpowered rails
+        v = NvRmPrivPmuRailGetVoltage(
+            hRmDeviceHandle, s_IoPowerDetectMap[i].PowerRailId);
+        if (v == ODM_VOLTAGE_OFF)
+            NoIoPwrMask |= s_IoPowerDetectMap[i].DisableRailMask;
+    }
+
+    // Latch already powered IO rails
+    NvRmPrivIoPowerDetectLatch(hRmDeviceHandle);
+
+    // Disable IO pads for unpowered rails
+    if (NoIoPwrMask)
+        NvRmPrivIoPowerControl(hRmDeviceHandle, NoIoPwrMask, NV_FALSE);
+}
+
+void NvRmPrivIoPowerDetectStart(
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvU32 PwrDetMask)
+{
+// (1) Enable specified power detect cell
+    NV_REGW(hRmDeviceHandle,
+            NvRmModuleID_Pmif, 0, APBDEV_PMC_PWR_DET_0, PwrDetMask);
+
+// (2-3) Set power detect latches for enabled cells to safe "1" (high) value
+    if ((hRmDeviceHandle->ChipId.Id == 0x15) ||
+        (hRmDeviceHandle->ChipId.Id == 0x16))
+    {
+        // On AP15/AP16 set/clear reset bit in PMC scratch0 
+        NvRmPrivAp15IoPowerDetectReset(hRmDeviceHandle);
+
+        // For AP15 A01 chip the above reset does nothing, therefore
+        // need to set latch "pass-thru" before transition
+        if ((hRmDeviceHandle->ChipId.Id == 0x15) &&
+            (hRmDeviceHandle->ChipId.Major == 0x01) &&
+            (hRmDeviceHandle->ChipId.Minor == 0x01))
+        {
+            NvOsWaitUS(NVRM_PWR_DET_DELAY_US);
+            NV_REGW(hRmDeviceHandle,
+                    NvRmModuleID_Pmif, 0, APBDEV_PMC_PWR_DET_LATCH_0, 1);
+        }
+    }
+    else
+    {
+        // On AP20+ reset high values directly
+        NvRmPrivAp20IoPowerDetectReset(hRmDeviceHandle);
+    }
+}
+//
+//  (4) Power rail OFF -> ON transition and stabilization
+//
+void NvRmPrivIoPowerDetectLatch(NvRmDeviceHandle hRmDeviceHandle)
+{
+// (5) Set latch "pass-thru"
+// (6) Latch results
+// (7) Disable all power detect cells
+    NV_REGW(hRmDeviceHandle,
+            NvRmModuleID_Pmif, 0, APBDEV_PMC_PWR_DET_LATCH_0, 1);
+    NV_REGW(hRmDeviceHandle,
+            NvRmModuleID_Pmif, 0, APBDEV_PMC_PWR_DET_LATCH_0, 0);
+    NV_REGW(hRmDeviceHandle,
+            NvRmModuleID_Pmif, 0, APBDEV_PMC_PWR_DET_0, 0);
+}
+
+void NvRmPrivIoPowerControl(
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvU32 NoIoPwrMask,
+    NvBool Enable)
+{
+    NvU32 reg = NV_REGR(
+        hRmDeviceHandle, NvRmModuleID_Pmif, 0, APBDEV_PMC_NO_IOPOWER_0);
+    reg = Enable ? (reg & (~NoIoPwrMask)) : (reg | NoIoPwrMask);
+
+#if NV_NO_IOPOWER_CONTROL
+    NV_REGW(hRmDeviceHandle,
+            NvRmModuleID_Pmif, 0, APBDEV_PMC_NO_IOPOWER_0, reg);
+#endif
+}
+
+void
+NvRmPrivSetSocRailPowerState(
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvU32 PmuRailAddress,
+    NvBool Enable,
+    NvU32* pIoPwrDetectMask,
+    NvU32* pNoIoPwrMask)
+{
+    IoPowerMapRail(PmuRailAddress, pIoPwrDetectMask, pNoIoPwrMask);
+    if ((*pIoPwrDetectMask == 0) && (*pNoIoPwrMask == 0))
+        return;     // Exit if not mapped rail
+
+    if (Enable)
+    {
+        // On/Off transition: activate power detect cells and keep control
+        // masks so that the results can be latched and IO pads enabled after
+        // the transition is completed
+        if (*pIoPwrDetectMask != 0)
+            NvRmPrivIoPowerDetectStart(hRmDeviceHandle, *pIoPwrDetectMask);
+    }
+    else
+    {
+        // Off/On transition: disable IO pads, and clear control masks,
+        // as no action is required after the transition is completed
+        if (*pNoIoPwrMask != 0)
+            NvRmPrivIoPowerControl(hRmDeviceHandle, *pNoIoPwrMask, NV_FALSE);
+        *pIoPwrDetectMask = *pNoIoPwrMask = 0;
+    }
+}
+
+/*****************************************************************************/
+
+void NvRmPrivCoreVoltageInit(NvRmDeviceHandle hRmDevice)
+{
+    NvU32 CoreRailAddress, RtcRailAddress, CpuRailAddress;
+    const NvOdmPeripheralConnectivity* pPmuRail;
+    NvRmMilliVolts CurrentCoreMv = 0;
+    NvRmMilliVolts CurrentRtcMv = 0;
+    NvRmMilliVolts NominalCoreMv = NvRmPrivGetNominalMV(hRmDevice);
+
+    NV_ASSERT(hRmDevice);
+
+    if (NvRmPrivGetExecPlatform(hRmDevice) != ExecPlatform_Soc)
+    {
+        return;
+    }
+
+    pPmuRail = NvOdmPeripheralGetGuid(NV_VDD_CORE_ODM_ID);
+    NV_ASSERT(pPmuRail);
+    NV_ASSERT(pPmuRail->NumAddress);
+    CoreRailAddress = pPmuRail->AddressList[0].Address;
+
+    pPmuRail = NvOdmPeripheralGetGuid(NV_VDD_RTC_ODM_ID);
+    NV_ASSERT(pPmuRail);
+    NV_ASSERT(pPmuRail->NumAddress);
+    RtcRailAddress = pPmuRail->AddressList[0].Address;
+
+    // This function is called during PMU initialization when current (= boot)
+    // core voltage is expected to be within one safe step from nominal, and
+    // RTC voltage must be within one safe step from the core. Set nominal
+    // voltage (bump PMU ref count), if the above conditions are true.
+    NvRmPmuGetVoltage(hRmDevice, CoreRailAddress, &CurrentCoreMv);
+    NvRmPmuGetVoltage(hRmDevice, RtcRailAddress, &CurrentRtcMv);
+    if((CurrentCoreMv > (NominalCoreMv + NVRM_SAFE_VOLTAGE_STEP_MV)) ||
+       ((CurrentCoreMv + NVRM_SAFE_VOLTAGE_STEP_MV) < NominalCoreMv))
+    {
+        NV_ASSERT(!"Unexpected initial core voltage");
+        return;
+    }
+    if((CurrentRtcMv > (CurrentCoreMv + NVRM_SAFE_VOLTAGE_STEP_MV)) ||
+       ((CurrentRtcMv + NVRM_SAFE_VOLTAGE_STEP_MV) < CurrentCoreMv))
+    {
+        NV_ASSERT(!"Unexpected initial RTC voltage");
+        return;
+    }
+    // If core voltage is going up, update it before CPU
+    if (CurrentCoreMv <= NominalCoreMv)
+    {
+        NvRmPmuSetVoltage(hRmDevice, RtcRailAddress, NominalCoreMv, NULL);
+        NvRmPmuSetVoltage(hRmDevice, CoreRailAddress, NominalCoreMv, NULL);
+    }
+
+    // If the platform has dedicated CPU voltage rail, make sure it is set to
+    // nominal level as well (bump PMU ref count along the way).
+    if (NvRmPrivIsCpuRailDedicated(hRmDevice))
+    {
+        NvRmPmuVddRailCapabilities cap;
+        NvRmMilliVolts NominalCpuMv = NvRmPrivModuleVscaleGetMV(
+            hRmDevice, NvRmModuleID_Cpu,
+            NvRmPrivGetSocClockLimits(NvRmModuleID_Cpu)->MaxKHz);
+
+        pPmuRail = NvOdmPeripheralGetGuid(NV_VDD_CPU_ODM_ID);
+        NV_ASSERT(pPmuRail);
+        NV_ASSERT(pPmuRail->NumAddress);
+        CpuRailAddress = pPmuRail->AddressList[0].Address;
+
+        // Clip nominal CPU voltage to minimal PMU capabilities, and set it.
+        // (note: PMU with CPU voltage range above nominal is temporary
+        // accepted exception; for other limit violations: PMU maximum level
+        // for CPU is not high enough, or PMU core range does not include
+        // nominal core voltage, assert is fired inside NvRmPmuSetVoltage())
+        NvRmPmuGetCapabilities(hRmDevice, CpuRailAddress, &cap);
+        NominalCpuMv = NV_MAX(NominalCpuMv, cap.MinMilliVolts);
+        NvRmPmuSetVoltage(hRmDevice, CpuRailAddress, NominalCpuMv, NULL);
+        if (CurrentCoreMv > NominalCoreMv)
+            NvOsWaitUS(NVRM_CPU_TO_CORE_DOWN_US); // delay if core to go down
+    }
+
+    // If core voltage is going down, update it after CPU voltage
+    if (CurrentCoreMv > NominalCoreMv)
+    {
+        NvRmPmuSetVoltage(hRmDevice, RtcRailAddress, NominalCoreMv, NULL);
+        NvRmPmuSetVoltage(hRmDevice, CoreRailAddress, NominalCoreMv, NULL);
+    }
+
+    // Always On System I/O, DDR IO and RX DDR (if exist) - set nominal,
+    // bump ref count
+    NvRmPrivPmuRailControl(hRmDevice, NV_VDD_SYS_ODM_ID, NV_TRUE);
+    NvRmPrivPmuRailControl(hRmDevice, NV_VDD_DDR_ODM_ID, NV_TRUE);
+    if (NvOdmPeripheralGetGuid(NV_VDD_DDR_RX_ODM_ID))
+        NvRmPrivPmuRailControl(hRmDevice, NV_VDD_DDR_RX_ODM_ID, NV_TRUE);
+}
+
+/*****************************************************************************/
+
diff --git a/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_power_dfs.c b/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_power_dfs.c
new file mode 100644
index 000000000000..9f19d6c9a12a
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_power_dfs.c
@@ -0,0 +1,544 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/** 
+ * @file
+ * @brief <b>nVIDIA Driver Development Kit: 
+ *           Dynamic Frequency Scaling manager </b>
+ *
+ * @b Description: Implements NvRM Dynamic Frequency Scaling (DFS)
+ *                  manager for SOC-wide clock domains.
+ * 
+ */
+
+#include "nvrm_power_dfs.h"
+#include "nvassert.h"
+#include "nvrm_drf.h"
+#include "nvrm_hwintf.h"
+#include "nvrm_pmu.h"
+#include "ap15rm_power_dfs.h"
+#include "ap15/arstat_mon.h"
+#include "ap15/arvde_mon.h"
+#include "ap15/aremc.h"
+#include "ap15/arclk_rst.h"
+#include "ap15/arapb_misc.h"
+#include "ap15/artimerus.h"
+
+/*****************************************************************************/
+
+// Regsiter access macros for System Statistic module
+#define NV_SYSTAT_REGR(pSystatRegs, reg) \
+            NV_READ32((((NvU32)(pSystatRegs)) + STAT_MON_##reg##_0))
+#define NV_SYSTAT_REGW(pSystatRegs, reg, val) \
+            NV_WRITE32((((NvU32)(pSystatRegs)) + STAT_MON_##reg##_0), (val))
+
+// Regsiter access macros for VDE module
+#define NV_VDE_REGR(pVdeRegs, reg) \
+            NV_READ32((((NvU32)(pVdeRegs)) + ARVDE_PPB_##reg##_0))
+#define NV_VDE_REGW(pVdeRegs, reg, val) \
+            NV_WRITE32((((NvU32)(pVdeRegs)) + ARVDE_PPB_##reg##_0), (val))
+
+// Regsiter access macros for EMC module
+#define NV_EMC_REGR(pEmcRegs, reg) \
+            NV_READ32((((NvU32)(pEmcRegs)) + EMC_##reg##_0))
+#define NV_EMC_REGW(pEmcRegs, reg, val) \
+            NV_WRITE32((((NvU32)(pEmcRegs)) + EMC_##reg##_0), (val))
+
+// Regsiter access macros for CAR module
+#define NV_CAR_REGR(pCarRegs, reg) \
+         NV_READ32((((NvU32)(pCarRegs)) + CLK_RST_CONTROLLER_##reg##_0))
+#define NV_CAR_REGW(pCarRegs, reg, val) \
+         NV_WRITE32((((NvU32)(pCarRegs)) + CLK_RST_CONTROLLER_##reg##_0), (val))
+
+// Regsiter access macros for APB MISC module
+#define NV_APB_REGR(pApbRegs, reg) \
+         NV_READ32((((NvU32)(pApbRegs)) + APB_MISC_##reg##_0))
+#define NV_APB_REGW(pApbRegs, reg, val) \
+         NV_WRITE32((((NvU32)(pApbRegs)) + APB_MISC_##reg##_0), (val))
+
+/*****************************************************************************/
+// SYSTEM STATISTIC MODULE INTERFACES
+/*****************************************************************************/
+
+NvError NvRmPrivAp15SystatMonitorsInit(NvRmDfs* pDfs)
+{
+    NvError error;
+    NvU32 RegValue;
+    void* pSystatRegs = pDfs->Modules[NvRmDfsModuleId_Systat].pBaseReg;
+    NV_ASSERT(pSystatRegs);
+
+    /*
+     * System Statistic Monitor module belongs to DFS, therefore it is full
+     * initialization: Enable Clock => Reset => clear all control registers
+     * including interrupt status flags (cleared by writing "1"). Note that
+     * all monitors - used, or not used by DFS - are initialized. (The VPIPE
+     * monitor in this module does not provide neccessary data for DFS; the
+     * VDE idle monitor is employed for video-pipe domain control)
+     */
+    error = NvRmPowerModuleClockControl(
+        pDfs->hRm, NvRmModuleID_SysStatMonitor, pDfs->PowerClientId, NV_TRUE);
+    if (error != NvSuccess)
+    {
+        return error;
+    }
+    NvRmModuleReset(pDfs->hRm, NvRmModuleID_SysStatMonitor);
+
+    RegValue = NV_DRF_NUM(STAT_MON, CPU_MON_CTRL, INT, 1);
+    NV_SYSTAT_REGW(pSystatRegs, CPU_MON_CTRL, RegValue);
+
+    RegValue = NV_DRF_NUM(STAT_MON, COP_MON_CTRL, INT, 1);
+    NV_SYSTAT_REGW(pSystatRegs, COP_MON_CTRL, RegValue);
+
+    RegValue = NV_DRF_NUM(STAT_MON, CACHE2_MON_CTRL, INT, 1);
+    NV_SYSTAT_REGW(pSystatRegs, CACHE2_MON_CTRL, RegValue);
+
+    RegValue = NV_DRF_NUM(STAT_MON, AHB_MON_CTRL, INT, 1);
+    NV_SYSTAT_REGW(pSystatRegs, AHB_MON_CTRL, RegValue);
+
+    RegValue = NV_DRF_NUM(STAT_MON, APB_MON_CTRL, INT, 1);
+    NV_SYSTAT_REGW(pSystatRegs, APB_MON_CTRL, RegValue);
+
+    RegValue = NV_DRF_NUM(STAT_MON, VPIPE_MON_CTRL, INT, 1);
+    NV_SYSTAT_REGW(pSystatRegs, VPIPE_MON_CTRL, RegValue);
+
+    RegValue = NV_DRF_NUM(STAT_MON, SMP_MON_CTRL, INT, 1);
+    NV_SYSTAT_REGW(pSystatRegs, SMP_MON_CTRL, RegValue);
+
+    return NvSuccess;
+}
+
+void NvRmPrivAp15SystatMonitorsDeinit(NvRmDfs* pDfs)
+{
+    // First initialize monitor, and then just turn off the clock (twice to
+    // balance the clock control)
+    (void)NvRmPrivAp15SystatMonitorsInit(pDfs);
+    (void)NvRmPowerModuleClockControl(
+        pDfs->hRm, NvRmModuleID_SysStatMonitor, pDfs->PowerClientId, NV_FALSE);
+    (void)NvRmPowerModuleClockControl(
+        pDfs->hRm, NvRmModuleID_SysStatMonitor, pDfs->PowerClientId, NV_FALSE);
+
+}
+
+void
+NvRmPrivAp15SystatMonitorsStart(
+    const NvRmDfs* pDfs,
+    const NvRmDfsFrequencies* pDfsKHz,
+    const NvU32 IntervalMs)
+{
+    NvU32 RegValue;
+    NvU32 msec = IntervalMs - 1; // systat monitors use (n+1) ms counters
+    void* pSystatRegs = pDfs->Modules[NvRmDfsModuleId_Systat].pBaseReg;
+
+    /*
+     * Start AVP (COP) monitor for the next sample period. Interrupt is
+     * cleared (by writing "1") and left disabled. Monitor is counting
+     * System clock cycles while AVP is halted by flow controller. Note
+     * that AVP monitor is counting System (not AVP!) clock cycles
+     */
+    RegValue = NV_DRF_DEF(STAT_MON, COP_MON_CTRL, ENB, ENABLE) |
+               NV_DRF_NUM(STAT_MON, COP_MON_CTRL, INT, 1) |
+               NV_DRF_NUM(STAT_MON, COP_MON_CTRL, SAMPLE_PERIOD, msec);
+    NV_SYSTAT_REGW(pSystatRegs, COP_MON_CTRL, RegValue);
+
+    /*
+     * Start AHB monitor for the next sample period. Interrupt is cleared
+     * (by writing "1") and left disabled. Monitor is counting AHB clock
+     * cycles while there is no data transfer on AHB initiated by any master
+     */
+    RegValue = NV_DRF_DEF(STAT_MON, AHB_MON_CTRL, ENB, ENABLE) |
+               NV_DRF_NUM(STAT_MON, AHB_MON_CTRL, INT, 1) |
+               NV_DRF_DEF(STAT_MON, AHB_MON_CTRL, MST_NUMBER, DEFAULT_MASK) |
+               NV_DRF_NUM(STAT_MON, AHB_MON_CTRL, SAMPLE_PERIOD, msec);
+    NV_SYSTAT_REGW(pSystatRegs, AHB_MON_CTRL, RegValue);
+
+    /*
+     * Start APB monitor for the next sample period. Interrupt is cleared
+     * (by writing "1") and left disabled. Monitor is counting APB clock
+     * cycles while there is no data transfer on APB targeted to any slave 
+     */
+    RegValue = NV_DRF_DEF(STAT_MON, APB_MON_CTRL, ENB, ENABLE) |
+               NV_DRF_NUM(STAT_MON, APB_MON_CTRL, INT, 1) |
+               NV_DRF_DEF(STAT_MON, APB_MON_CTRL, SLV_NUMBER, DEFAULT_MASK) |
+               NV_DRF_NUM(STAT_MON, APB_MON_CTRL, SAMPLE_PERIOD, msec);
+    NV_SYSTAT_REGW(pSystatRegs, APB_MON_CTRL, RegValue);
+
+    /*
+     * Start CPU monitor for the next sample period. Interrupt is cleared
+     * (by writing "1") and enabled, since CPU monitor is used to generate
+     * DFS interrupt. Monitor is counting System clock cycles while CPU is
+     * halted by flow controller. Note: CPU monitor is counting System (not
+     * CPU!) clock cycles
+     */
+    RegValue = NV_DRF_DEF(STAT_MON, CPU_MON_CTRL, ENB, ENABLE) |
+               NV_DRF_DEF(STAT_MON, CPU_MON_CTRL, INT_EN, ENABLE) |
+               NV_DRF_NUM(STAT_MON, CPU_MON_CTRL, INT, 1) |
+               NV_DRF_NUM(STAT_MON, CPU_MON_CTRL, SAMPLE_PERIOD, msec);
+    NV_SYSTAT_REGW(pSystatRegs, CPU_MON_CTRL, RegValue);
+
+    // Initialize LP2 time storage (WAR for bug 429585)
+    NvRmPrivSetLp2TimeUS(pDfs->hRm, 0);
+}
+
+void
+NvRmPrivAp15SystatMonitorsRead(
+    const NvRmDfs* pDfs,
+    const NvRmDfsFrequencies* pDfsKHz,
+    NvRmDfsIdleData* pIdleData)
+{
+    NvU32 RegValue;
+    NvU64 temp;
+    void* pSystatRegs = pDfs->Modules[NvRmDfsModuleId_Systat].pBaseReg;
+    NvBool NoLp2Offset = pDfs->Modules[NvRmDfsModuleId_Systat].Offset !=
+        NVRM_CPU_IDLE_LP2_OFFSET;
+
+    /*
+     * Read AVP (COP) monitor: disable it (=stop, the readings are preserved)
+     * and clear interrupt status bit (by writing "1"). Then, read AVP idle
+     * count. Since AVP monitor is counting System (not AVP!) clock cycles,
+     * the monitor reading is converted to AVP clocks before storing it in
+     * idle data packet.
+     */
+    RegValue = NV_DRF_NUM(STAT_MON, COP_MON_CTRL, INT, 1);
+    NV_SYSTAT_REGW(pSystatRegs, COP_MON_CTRL, RegValue);
+
+    RegValue = NV_SYSTAT_REGR(pSystatRegs, COP_MON_STATUS);
+    RegValue = NV_DRF_VAL(STAT_MON, COP_MON_STATUS, COUNT, RegValue);
+
+    temp = ((NvU64)RegValue * pDfsKHz->Domains[NvRmDfsClockId_Avp]);
+    temp = NvDiv64(temp, pDfsKHz->Domains[NvRmDfsClockId_System]);
+
+    pIdleData->Readings[NvRmDfsClockId_Avp] = (NvU32)temp;
+
+    /*
+     * Read AHB monitor: disable it (=stop, the readings are preserved) and
+     * clear interrupt status bit (by writing "1"). Then, read AHB idle count
+     * (in AHB clock cycles) and store it in idle data packet.
+     */
+    RegValue = NV_DRF_NUM(STAT_MON, AHB_MON_CTRL, INT, 1);
+    NV_SYSTAT_REGW(pSystatRegs, AHB_MON_CTRL, RegValue);
+
+    RegValue = NV_SYSTAT_REGR(pSystatRegs, AHB_MON_STATUS);
+    pIdleData->Readings[NvRmDfsClockId_Ahb] = 
+        NV_DRF_VAL(STAT_MON, AHB_MON_STATUS, COUNT, RegValue);
+
+    /*
+     * Read APB monitor: disable it (=stop, the readings are preserved) and
+     * clear interrupt status bit (by writing "1"). Then, read APB idle count
+     * (in APB clock cycles) and store it in idle data packet.
+     */
+    RegValue = NV_DRF_NUM(STAT_MON, APB_MON_CTRL, INT, 1);
+    NV_SYSTAT_REGW(pSystatRegs, APB_MON_CTRL, RegValue);
+
+    RegValue = NV_SYSTAT_REGR(pSystatRegs, APB_MON_STATUS);
+    pIdleData->Readings[NvRmDfsClockId_Apb] = 
+        NV_DRF_VAL(STAT_MON, APB_MON_STATUS, COUNT, RegValue);
+
+    /*
+     * Read CPU monitor: read current sampling period and store it in idle
+     * data packet. Disable monitor (=stop, the readings are preserved) and
+     * clear interrupt status bit (by writing "1"). Read CPU idle count.
+     * Since CPU monitor is counting System (not CPU!) cycles, the monitor
+     * readings are converted to CPU clocks before storing in idle data packet
+     */
+    RegValue = NV_SYSTAT_REGR(pSystatRegs, CPU_MON_CTRL);
+    pIdleData->CurrentIntervalMs = 1 +  // systat monitors use (n+1) ms counters
+        NV_DRF_VAL(STAT_MON, CPU_MON_CTRL, SAMPLE_PERIOD, RegValue);
+
+    RegValue = NV_DRF_NUM(STAT_MON, CPU_MON_CTRL, INT, 1);
+    NV_SYSTAT_REGW(pSystatRegs, CPU_MON_CTRL, RegValue);
+
+    // Add LP2 time to idle measurements (WAR for bug 429585)
+    // For logging only - use 2^10 ~ 1000, and round up
+    RegValue = NvRmPrivGetLp2TimeUS(pDfs->hRm);
+    pIdleData->Lp2TimeMs = (RegValue + (0x1 << 10) - 1) >> 10;
+    if ((RegValue == 0) || NoLp2Offset)
+    {
+        pIdleData->Readings[NvRmDfsClockId_Cpu] = 0;
+    }
+    else if (RegValue < NVRM_DFS_MAX_SAMPLE_MS * 1000)
+    {   //  (US * KHz) / 1000 ~ (US * 131 * KHz) / (128 * 1024)
+        pIdleData->Readings[NvRmDfsClockId_Cpu] =
+            (NvU32)(((NvU64)(RegValue * 131) *
+                     pDfsKHz->Domains[NvRmDfsClockId_Cpu]) >> 17);
+    }
+    else
+    {
+        pIdleData->Readings[NvRmDfsClockId_Cpu] = 0xFFFFFFFFUL;
+        return; // the entire sample is idle, anyway
+    }
+    RegValue = NV_SYSTAT_REGR(pSystatRegs, CPU_MON_STATUS);
+    RegValue = NV_DRF_VAL(STAT_MON, CPU_MON_STATUS, COUNT, RegValue);
+
+    temp = ((NvU64)RegValue * pDfsKHz->Domains[NvRmDfsClockId_Cpu]);
+    temp = NvDiv64(temp, pDfsKHz->Domains[NvRmDfsClockId_System]);
+
+    pIdleData->Readings[NvRmDfsClockId_Cpu] += (NvU32)temp;
+}
+
+/*****************************************************************************/
+// VDE MODULE INTERFACES
+/*****************************************************************************/
+
+NvError NvRmPrivAp15VdeMonitorsInit(NvRmDfs* pDfs)
+{
+    NvU32 RegValue;
+    void* pVdeRegs = pDfs->Modules[NvRmDfsModuleId_Vde].pBaseReg;
+    NV_ASSERT(pVdeRegs);
+
+    /*
+     * Video pipe monitor belongs to VDE module - just clear monitor control
+     * register including interrupt status bit, and do not touch anything
+     * else in VDE 
+     */ 
+    RegValue = NV_DRF_NUM(ARVDE_PPB, IDLE_MON, INT_STATUS, 1);
+    NV_VDE_REGW(pVdeRegs, IDLE_MON, RegValue);
+
+    return NvSuccess;
+}
+
+void NvRmPrivAp15VdeMonitorsDeinit(NvRmDfs* pDfs)
+{
+    // Stop monitor using initialization procedure
+    (void)NvRmPrivAp15VdeMonitorsInit(pDfs);
+}
+
+void
+NvRmPrivAp15VdeMonitorsStart(
+    const NvRmDfs* pDfs,
+    const NvRmDfsFrequencies* pDfsKHz,
+    const NvU32 IntervalMs)
+{
+    NvU32 RegValue;
+    NvU32 cycles = IntervalMs * pDfsKHz->Domains[NvRmDfsClockId_Vpipe];
+    void* pVdeRegs = pDfs->Modules[NvRmDfsModuleId_Vde].pBaseReg;
+
+    /*
+     * Start VDE vpipe monitor for the next sample period. Interrupt status bit
+     * is cleared by writing "1" (it is not connected to interrupt controller,
+     * just "count end" status bit). Monitor is counting v-clock cycles while
+     * all VDE submodules are idle. The sample period is specified in v-clock
+     * cycles rather than in time units. 
+     */
+    RegValue = NV_DRF_NUM(ARVDE_PPB, IDLE_MON, ENB, 1) |
+               NV_DRF_NUM(ARVDE_PPB, IDLE_MON, INT_STATUS, 1) |
+               NV_DRF_NUM(ARVDE_PPB, IDLE_MON, SAMPLE_PERIOD, cycles);
+    NV_VDE_REGW(pVdeRegs, IDLE_MON, RegValue);
+}
+
+void
+NvRmPrivAp15VdeMonitorsRead(
+    const NvRmDfs* pDfs,
+    const NvRmDfsFrequencies* pDfsKHz,
+    NvRmDfsIdleData* pIdleData)
+{
+    // CAR module virtual base address
+    static void* s_pCarBaseReg = NULL;
+    NvU32 RegValue;
+    void* pVdeRegs = pDfs->Modules[NvRmDfsModuleId_Vde].pBaseReg;
+
+    if (s_pCarBaseReg == NULL)
+    {
+        NvRmModuleTable *tbl = NvRmPrivGetModuleTable(pDfs->hRm);
+        s_pCarBaseReg = (tbl->ModInst +
+            tbl->Modules[NvRmPrivModuleID_ClockAndReset].Index)->VirtAddr;
+    }
+    RegValue = NV_CAR_REGR(s_pCarBaseReg, CLK_OUT_ENB_H);
+
+    // If VDE clock is disabled set idle count to maximum
+    if (!(RegValue & CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_VDE_FIELD))
+    {
+        pIdleData->Readings[NvRmDfsClockId_Vpipe] = (NvU32)-1;
+        return;
+    }
+
+    /*
+     * Read VDE vpipe monitor: disable it (=stop, the readings are preserved) and
+     * clear count done status bit (by writing "1"). Then, read VDE idle count (in
+     * v-clock cycles) and store it in idle data packet.
+     */
+    RegValue = NV_DRF_NUM(ARVDE_PPB, IDLE_MON, INT_STATUS, 1);
+    NV_VDE_REGW(pVdeRegs, IDLE_MON, RegValue);
+
+    RegValue = NV_VDE_REGR(pVdeRegs, IDLE_STATUS);
+    pIdleData->Readings[NvRmDfsClockId_Vpipe] = 
+        NV_DRF_VAL(ARVDE_PPB, IDLE_STATUS, COUNT, RegValue);
+}
+
+/*****************************************************************************/
+// EMC MODULE INTERFACES
+/*****************************************************************************/
+
+NvError NvRmPrivAp15EmcMonitorsInit(NvRmDfs* pDfs)
+{
+    NvU32 RegValue;
+    void* pEmcRegs = pDfs->Modules[NvRmDfsModuleId_Emc].pBaseReg;
+    NV_ASSERT(pEmcRegs);
+
+    /*
+     * EMC power management monitor belongs to EMC module - just reset it,
+     * and do not touch anything else in EMC.
+     */ 
+    RegValue = NV_EMC_REGR(pEmcRegs, STAT_CONTROL);
+    RegValue = NV_FLD_SET_DRF_DEF(EMC, STAT_CONTROL, PWR_GATHER, RST, RegValue);
+    NV_EMC_REGW(pEmcRegs, STAT_CONTROL, RegValue);
+
+    /*
+    * EMC active clock cycles = EMC monitor reading * 2^M, where M depends
+    * on DRAM type and bus width. Power M is stored as EMC readouts scale
+    */
+    #define COUNT_SHIFT_SDRAM_X32 (2)
+    #define COUNT_SHIFT_DDR1_X32 (1)
+    RegValue = NV_EMC_REGR(pEmcRegs, FBIO_CFG5);
+    switch (NV_DRF_VAL(EMC, FBIO_CFG5, DRAM_TYPE, RegValue))
+    {
+        case EMC_FBIO_CFG5_0_DRAM_TYPE_SDR:
+            pDfs->Modules[NvRmDfsModuleId_Emc].Scale = COUNT_SHIFT_SDRAM_X32;
+            break;
+        case EMC_FBIO_CFG5_0_DRAM_TYPE_DDR1:
+            pDfs->Modules[NvRmDfsModuleId_Emc].Scale = COUNT_SHIFT_DDR1_X32;
+            break;
+        default:
+            NV_ASSERT(!"Not supported DRAM type");
+    }
+    if (NV_DRF_VAL(EMC, FBIO_CFG5, DRAM_WIDTH, RegValue) ==
+        EMC_FBIO_CFG5_0_DRAM_WIDTH_X16)
+    {
+        pDfs->Modules[NvRmDfsModuleId_Emc].Scale++;
+    }
+    return NvSuccess;
+}
+
+void NvRmPrivAp15EmcMonitorsDeinit(NvRmDfs* pDfs)
+{
+     // Stop monitor using initialization procedure
+    (void)NvRmPrivAp15EmcMonitorsInit(pDfs);
+}
+
+void
+NvRmPrivAp15EmcMonitorsStart(
+    const NvRmDfs* pDfs,
+    const NvRmDfsFrequencies* pDfsKHz,
+    const NvU32 IntervalMs)
+{
+    NvU32 RegValue, SavedRegValue;
+    void* pEmcRegs = pDfs->Modules[NvRmDfsModuleId_Emc].pBaseReg;
+
+    // EMC sample period is specified in EMC clock cycles, accuracy 0-16 cycles.
+    #define MEAN_EMC_LIMIT_ERROR (8)
+    NvU32 cycles = IntervalMs * pDfsKHz->Domains[NvRmDfsClockId_Emc] +
+                    MEAN_EMC_LIMIT_ERROR;
+    /*
+     * Start EMC power monitor for the next sample period: clear EMC counters,
+     * set sample interval limit in EMC cycles, enable monitoring. Monitor is
+     * counting EMC 1x clock cycles while any memory access is detected. 
+     */
+    SavedRegValue = NV_EMC_REGR(pEmcRegs, STAT_CONTROL);
+    RegValue = NV_FLD_SET_DRF_DEF(EMC, STAT_CONTROL, PWR_GATHER, CLEAR, SavedRegValue);
+    NV_EMC_REGW(pEmcRegs, STAT_CONTROL, RegValue);
+
+    RegValue = NV_DRF_NUM(EMC, STAT_PWR_CLOCK_LIMIT, PWR_CLOCK_LIMIT, cycles);
+    NV_EMC_REGW(pEmcRegs, STAT_PWR_CLOCK_LIMIT, RegValue);
+
+    RegValue = NV_FLD_SET_DRF_DEF(EMC, STAT_CONTROL, PWR_GATHER, ENABLE, SavedRegValue);
+    NV_EMC_REGW(pEmcRegs, STAT_CONTROL, RegValue);
+}
+
+void
+NvRmPrivAp15EmcMonitorsRead(
+    const NvRmDfs* pDfs,
+    const NvRmDfsFrequencies* pDfsKHz,
+    NvRmDfsIdleData* pIdleData)
+{
+    NvU32 RegValue, TotalClocks;
+    NvU32 CountShift = pDfs->Modules[NvRmDfsModuleId_Emc].Scale;
+    void* pEmcRegs = pDfs->Modules[NvRmDfsModuleId_Emc].pBaseReg;
+
+    /*
+     * Read EMC monitor: disable it (=stop, the readings are preserved), and
+     * determine idle count based on total and active clock counts. Monitor
+     * readings are multiplied by 2^M factor to determine active count, where
+     * power M depends on DRAM type and bus width. Store result in the idle
+     * data packet.
+     */
+    RegValue = NV_EMC_REGR(pEmcRegs, STAT_CONTROL);
+    RegValue = NV_FLD_SET_DRF_DEF(EMC, STAT_CONTROL, PWR_GATHER, DISABLE, RegValue);
+    NV_EMC_REGW(pEmcRegs, STAT_CONTROL, RegValue);
+
+    RegValue = NV_EMC_REGR(pEmcRegs, STAT_PWR_CLOCKS);
+    TotalClocks = NV_DRF_VAL(EMC, STAT_PWR_CLOCKS, PWR_CLOCKS, RegValue);
+    RegValue = NV_EMC_REGR(pEmcRegs, STAT_PWR_COUNT);
+    RegValue = NV_DRF_VAL(EMC, STAT_PWR_COUNT, PWR_COUNT, RegValue) << CountShift;
+
+    pIdleData->Readings[NvRmDfsClockId_Emc] = 
+        (TotalClocks > RegValue) ? (TotalClocks - RegValue) : 0;
+}
+
+/*****************************************************************************/
+
+void
+NvRmPrivAp15SetSvopControls(
+    NvRmDeviceHandle hRm,
+    NvU32 SvopSetting)
+{
+#define SVOP_MASK \
+    (NV_DRF_NUM(APB_MISC, GP_ASDBGREG, CFG2TMC_RAM_SVOP_DP, 0xFFFFFFFFUL) |  \
+     NV_DRF_NUM(APB_MISC, GP_ASDBGREG, CFG2TMC_RAM_SVOP_PDP, 0xFFFFFFFFUL) | \
+     NV_DRF_NUM(APB_MISC, GP_ASDBGREG, CFG2TMC_RAM_SVOP_REG, 0xFFFFFFFFUL) | \
+     NV_DRF_NUM(APB_MISC, GP_ASDBGREG, CFG2TMC_RAM_SVOP_SP, 0xFFFFFFFFUL))
+
+    NvU32 reg;
+    static void* s_pApbBaseReg = NULL;  // APB MISC module virtual base address
+
+    if (s_pApbBaseReg == NULL)
+    {
+        NvRmModuleTable *tbl = NvRmPrivGetModuleTable(hRm);
+        s_pApbBaseReg = (tbl->ModInst +
+            tbl->Modules[NvRmModuleID_Misc].Index)->VirtAddr;
+    }
+    NV_ASSERT((SvopSetting & (~SVOP_MASK)) == 0);
+    reg = NV_APB_REGR(s_pApbBaseReg, GP_ASDBGREG);  // RAM timing control
+    reg = (reg & (~SVOP_MASK)) | SvopSetting;
+    NV_APB_REGW(s_pApbBaseReg, GP_ASDBGREG, reg); 
+}
+
+/*****************************************************************************/
+
+void* NvRmPrivAp15GetTimerUsVirtAddr(NvRmDeviceHandle hRm)
+{
+    NvRmModuleTable *tbl = NvRmPrivGetModuleTable(hRm);
+    void* va = (void*)((NvUPtr)((tbl->ModInst + 
+        tbl->Modules[NvRmModuleID_TimerUs].Index)->VirtAddr) +
+        TIMERUS_CNTR_1US_0);
+    return va;
+}
+
+/*****************************************************************************/
diff --git a/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_power_dfs.h b/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_power_dfs.h
new file mode 100644
index 000000000000..10889666d25c
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_power_dfs.h
@@ -0,0 +1,314 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/** 
+ * @file
+ * @brief <b>nVIDIA Driver Development Kit: 
+ *           Power Resource manager </b>
+ *
+ * @b Description: NvRM DFS parameters. 
+ * 
+ */
+
+#ifndef INCLUDED_AP15RM_POWER_DFS_H
+#define INCLUDED_AP15RM_POWER_DFS_H
+
+#include "nvrm_power.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif  /* __cplusplus */
+
+// Min KHz for CPU and AVP with regards to JTAG support - 1MHz * 8  = 8MHz
+// TODO: any other limitations on min KHz?
+// TODO: adjust boost parameters based on testing
+
+/**
+ * Default DFS algorithm parameters for CPU domain
+ */
+#define NVRM_DFS_PARAM_CPU_AP15 \
+    NvRmFreqMaximum, /* Maximum domain frequency set to h/w limit */ \
+    10000,  /* Minimum domain frequency 10 MHz */ \
+    1000,   /* Frequency change upper band 1 MHz */ \
+    1000,   /* Frequency change lower band 1 MHz */ \
+    {          /* RT starvation control parameters */ \
+        32000, /* Fixed frequency boost increase 32 MHz */ \
+        255,   /* Proportional frequency boost increase 255/256 ~ 100% */ \
+        128,   /* Proportional frequency boost decrease 128/256 ~ 50% */  \
+    },\
+    {          /* NRT starvation control parameters */ \
+        4000,  /* Fixed frequency boost increase 4 MHz */ \
+        255,   /* Proportional frequency boost increase 255/256 ~ 100% */ \
+        128,   /* Proportional frequency boost decrease 128/256 ~ 50% */  \
+    },\
+    3,      /* Relative adjustement of average freqiency 1/2^3 ~ 12% */ \
+    1,      /* Number of smaple intervals with NRT to trigger boost = 2 */ \
+    1       /* NRT idle cycles threshold = 1 */ 
+
+/**
+ *  Default DFS algorithm parameters for AVP domain
+ */
+#define NVRM_DFS_PARAM_AVP_AP15 \
+    NvRmFreqMaximum, /* Maximum domain frequency set to h/w limit */ \
+    24000,  /* Minimum domain frequency 24 MHz */ \
+    1000,   /* Frequency change upper band 1 MHz */ \
+    1000,   /* Frequency change lower band 1 MHz */ \
+    {          /* RT starvation control parameters */ \
+        8000,  /* Fixed frequency boost increase 8 MHz */ \
+        255,   /* Proportional frequency boost increase 255/256 ~ 100% */ \
+        128,   /* Proportional frequency boost decrease 128/256 ~ 50% */  \
+    },\
+    {          /* NRT starvation control parameters */ \
+        1000,  /* Fixed frequency NRT boost increase 1 MHz */ \
+        255,   /* Proportional frequency boost increase 255/256 ~ 100% */ \
+        128,   /* Proportional frequency boost decrease 128/256 ~ 50% */  \
+    },\
+    3,      /* Relative adjustement of average freqiency 1/2^3 ~ 12% */ \
+    2,      /* Number of smaple intervals with NRT to trigger boost = 3 */ \
+    1       /* NRT idle cycles threshold = 1 */ 
+
+/**
+ * Default DFS algorithm parameters for System clock domain
+ */
+#define NVRM_DFS_PARAM_SYSTEM_AP15 \
+    NvRmFreqMaximum, /* Maximum domain frequency set to h/w limit */ \
+    24000,  /* Minimum domain frequency 24 MHz */ \
+    1000,   /* Frequency change upper band 1 MHz */ \
+    1000,   /* Frequency change lower band 1 MHz */ \
+    {          /* RT starvation control parameters */ \
+        8000,  /* Fixed frequency boost increase 8 MHz */ \
+        255,   /* Proportional frequency boost increase 255/256 ~ 100% */ \
+        128,   /* Proportional frequency boost decrease 128/256 ~ 50% */  \
+    },\
+    {          /* NRT starvation control parameters */ \
+        1000,  /* Fixed frequency NRT boost increase 1 MHz */ \
+        255,   /* Proportional frequency boost increase 255/256 ~ 100% */ \
+        32,    /* Proportional frequency boost decrease 32/256 ~ 12% */  \
+    },\
+    5,      /* Relative adjustement of average freqiency 1/2^5 ~ 3% */ \
+    2,      /* Number of smaple intervals with NRT to trigger boost = 3 */ \
+    1       /* NRT idle cycles threshold = 1 */ 
+
+/**
+ * Default DFS algorithm parameters for AHB clock domain
+ */
+#define NVRM_DFS_PARAM_AHB_AP15 \
+    NvRmFreqMaximum, /* Maximum domain frequency set to h/w limit */ \
+    24000,  /* Minimum domain frequency 24 MHz */ \
+    1000,   /* Frequency change upper band 1 MHz */ \
+    1000,   /* Frequency change lower band 1 MHz */ \
+    {          /* RT starvation control parameters */ \
+        8000,  /* Fixed frequency boost increase 8 MHz */ \
+        255,   /* Proportional frequency boost increase 255/256 ~ 100% */ \
+        128,   /* Proportional frequency boost decrease 128/256 ~ 50% */  \
+    },\
+    {          /* NRT starvation control parameters */ \
+        1000,  /* Fixed frequency NRT boost increase 1 MHz */ \
+        255,   /* Proportional frequency boost increase 255/256 ~ 100% */ \
+        32,    /* Proportional frequency boost decrease 32/256 ~ 12% */  \
+    },\
+    0,      /* Relative adjustement of average freqiency 1/2^0 ~ 100% */ \
+    0,      /* Number of smaple intervals with NRT to trigger boost = 1 */ \
+    1       /* NRT idle cycles threshold = 1 */ 
+
+/**
+ * Default DFS algorithm parameters for APB clock domain
+ */
+#define NVRM_DFS_PARAM_APB_AP15 \
+    NvRmFreqMaximum, /* Maximum domain frequency set to h/w limit */ \
+    15000,  /* Minimum domain frequency 15 MHz */ \
+    1000,   /* Frequency change upper band 1 MHz */ \
+    1000,   /* Frequency change lower band 1 MHz */ \
+    {          /* RT starvation control parameters */ \
+        8000,  /* Fixed frequency boost increase 8 MHz */ \
+        255,   /* Proportional frequency boost increase 255/256 ~ 100% */ \
+        128,   /* Proportional frequency boost decrease 128/256 ~ 50% */  \
+    },\
+    {          /* NRT starvation control parameters */ \
+        1000,  /* Fixed frequency NRT boost increase 1 MHz */ \
+        255,   /* Proportional frequency boost increase 255/256 ~ 100% */ \
+        32,    /* Proportional frequency boost decrease 32/256 ~ 12% */  \
+    },\
+    0,      /* Relative adjustement of average freqiency 1/2^0 ~ 100% */ \
+    0,      /* Number of smaple intervals with NRT to trigger boost = 1 */ \
+    1       /* NRT idle cycles threshold = 1 */ 
+
+/**
+ * Default DFS algorithm parameters for Video-pipe clock domain
+ */
+#define NVRM_DFS_PARAM_VPIPE_AP15 \
+    NvRmFreqMaximum, /* Maximum domain frequency set to h/w limit */ \
+    24000,  /* Minimum domain frequency 24 MHz */ \
+    1000,   /* Frequency change upper band 1 MHz */ \
+    1000,   /* Frequency change lower band 1 MHz */ \
+    {          /* RT starvation control parameters */ \
+        16000, /* Fixed frequency RT boost increase 16 MHz */ \
+        255,   /* Proportional frequency boost increase 255/256 ~ 100% */ \
+        128,   /* Proportional frequency boost decrease 128/256 ~ 50% */  \
+    },\
+    {          /* NRT starvation control parameters */ \
+        1000,  /* Fixed frequency NRT boost increase 1 MHz */ \
+        255,   /* Proportional frequency boost increase 255/256 ~ 100% */ \
+        128,   /* Proportional frequency boost decrease 128/256 ~ 50% */  \
+    },\
+    5,      /* Relative adjustement of average freqiency 1/2^5 ~ 3% */ \
+    3,      /* Number of smaple intervals with NRT to trigger boost = 4 */ \
+    1       /* NRT idle cycles threshold = 1 */ 
+
+/**
+ * Default DFS algorithm parameters for EMC clock domain
+ */
+#define NVRM_DFS_PARAM_EMC_AP15 \
+    NvRmFreqMaximum, /* Maximum domain frequency set to h/w limit */ \
+    16000,  /* Minimum domain frequency 16 MHz */ \
+    1000,   /* Frequency change upper band 1 MHz */ \
+    1000,   /* Frequency change lower band 1 MHz */ \
+    {          /* RT starvation control parameters */ \
+        16000, /* Fixed frequency RT boost increase 16 MHz */ \
+        255,   /* Proportional frequency boost increase 255/256 ~ 100% */ \
+        128,   /* Proportional frequency boost decrease 128/256 ~ 50% */  \
+    },\
+    {          /* NRT starvation control parameters */ \
+        1000,  /* Fixed frequency NRT boost increase 1 MHz */ \
+        255,   /* Proportional frequency boost increase 255/256 ~ 100% */ \
+        128,   /* Proportional frequency boost decrease 128/256 ~ 50% */  \
+    },\
+    0,      /* Relative adjustement of average freqiency 1/2^0 ~ 100% */ \
+    0,      /* Number of smaple intervals with NRT to trigger boost = 1 */ \
+    1       /* NRT idle cycles threshold = 1 */ 
+
+/// Default low corner for core voltage
+#define NVRM_AP15_LOW_CORE_MV (950)
+
+/// Core voltage in suspend
+#define NVRM_AP15_SUSPEND_CORE_MV (1000)
+
+/*****************************************************************************/
+
+/**
+ * Initializes activity monitors within the DFS module. Only activity
+ * monitors are affected. The rest of module's h/w is preserved.
+ * 
+ * @param pDfs - A pointer to DFS structure.
+ * 
+ * @return NvSuccess if initialization completed successfully
+ * or one of common error codes on failure.
+ */
+NvError NvRmPrivAp15SystatMonitorsInit(NvRmDfs* pDfs);
+NvError NvRmPrivAp15VdeMonitorsInit(NvRmDfs* pDfs);
+NvError NvRmPrivAp15EmcMonitorsInit(NvRmDfs* pDfs);
+
+/**
+ * Deinitializes activity monitors within the DFS module. Only activity
+ * monitors are affected. The rest of module's h/w is preserved.
+ * 
+ * @param pDfs - A pointer to DFS structure.
+ */
+void NvRmPrivAp15SystatMonitorsDeinit(NvRmDfs* pDfs);
+void NvRmPrivAp15VdeMonitorsDeinit(NvRmDfs* pDfs);
+void NvRmPrivAp15EmcMonitorsDeinit(NvRmDfs* pDfs);
+
+/**
+ * Starts activity monitors in the DFS module for the next sample interval.
+ * 
+ * @param pDfs - A pointer to DFS structure.
+ * @param pDfsKHz - A pointer to current DFS clock frequencies structure.
+ * @param IntervalMs Next sampling interval in ms.
+ */
+void
+NvRmPrivAp15SystatMonitorsStart(
+    const NvRmDfs* pDfs,
+    const NvRmDfsFrequencies* pDfsKHz,
+    const NvU32 IntervalMs);
+void
+NvRmPrivAp15VdeMonitorsStart(
+    const NvRmDfs* pDfs,
+    const NvRmDfsFrequencies* pDfsKHz,
+    const NvU32 IntervalMs);
+void
+NvRmPrivAp15EmcMonitorsStart(
+    const NvRmDfs* pDfs,
+    const NvRmDfsFrequencies* pDfsKHz,
+    const NvU32 IntervalMs);
+
+/**
+ * Reads idle count from activity monitors in the DFS module. The monitors are
+ * stopped.
+ * 
+ * @param pDfs - A pointer to DFS structure.
+ * @param pDfsKHz - A pointer to current DFS clock frequencies structure.
+ * @param pIdleData - A pointer to idle cycles structure to be filled in with
+ *  data read from the monitor.
+ * 
+ */
+void
+NvRmPrivAp15SystatMonitorsRead(
+    const NvRmDfs* pDfs,
+    const NvRmDfsFrequencies* pDfsKHz,
+    NvRmDfsIdleData* pIdleData);
+void
+NvRmPrivAp15VdeMonitorsRead(
+    const NvRmDfs* pDfs,
+    const NvRmDfsFrequencies* pDfsKHz,
+    NvRmDfsIdleData* pIdleData);
+void
+NvRmPrivAp15EmcMonitorsRead(
+    const NvRmDfs* pDfs,
+    const NvRmDfsFrequencies* pDfsKHz,
+    NvRmDfsIdleData* pIdleData);
+
+/**
+ * Changes RAM timing SVOP settings.
+ * 
+ * @param hRm The RM device handle.
+ * @param SvopSetting New SVOP setting.
+ */
+void
+NvRmPrivAp15SetSvopControls(
+    NvRmDeviceHandle hRm,
+    NvU32 SvopSetting);
+
+/**
+ * Gets uS Timer RM virtual address,
+ * 
+ * @param hRm The RM device handle.
+ * 
+ * @return uS Timer RM virtual address mapped by RM
+ */
+void* NvRmPrivAp15GetTimerUsVirtAddr(NvRmDeviceHandle hRm);
+
+#ifdef __cplusplus
+}
+#endif  /* __cplusplus */
+
+#endif // INCLUDED_AP15RM_POWER_DFS_H
diff --git a/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_power_oalintf.c b/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_power_oalintf.c
new file mode 100644
index 000000000000..e26d5b6e8376
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_power_oalintf.c
@@ -0,0 +1,334 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/** 
+ * @file
+ * @brief <b>nVIDIA Driver Development Kit: 
+ *           Power Resource manager API shared with OS adaptation layer</b>
+ *
+ * @b Description: Implements private HW interface shared by the NvRM Power
+ *  manager and OS adaptation layer (OAL). 
+ * 
+ */
+
+#include "nvrm_power.h"
+#include "nvrm_clocks.h"
+#include "nvrm_module.h"
+#include "nvrm_drf.h"
+#include "nvrm_hwintf.h"
+#include "ap15rm_private.h"
+#include "nvrm_structure.h"
+#include "ap15/arapb_misc.h"
+#include "ap15rm_pmc_scratch_map.h" 
+#include "common/nvrm_chiplib.h"
+#include "nvassert.h"
+
+/*****************************************************************************/
+
+/*
+ * Macros for power state register field access.
+ * AP15+: a dedicated bits in PMC scratch register 0 are allocated for RM power
+ * state fields.
+ */
+#define SET_POWER_FLD_AP15(rm, FieldName, FieldValue) \
+   do \
+   { \
+       if (!NvRmIsSimulation())\
+       {\
+           NvU32 RegValue; \
+           NvU32 RegOffset = APBDEV_PMC_SCRATCH0_0; \
+           NvOsSpinMutexLock(s_hPmcScratchMutex); \
+           RegValue = NV_REGR(rm, NvRmModuleID_Pmif, 0, RegOffset); \
+           RegValue = NV_FLD_SET_DRF_NUM(\
+               APBDEV_PMC, SCRATCH0, FieldName, FieldValue, RegValue); \
+           NV_REGW(rm, NvRmModuleID_Pmif, 0, RegOffset, RegValue); \
+           NvOsSpinMutexUnlock(s_hPmcScratchMutex); \
+       }\
+   } while (0)
+
+#define GET_POWER_FLD_AP15(rm, FieldName) \
+           NV_DRF_VAL(APBDEV_PMC, SCRATCH0, FieldName, \
+                     (NV_REGR(rm, NvRmModuleID_Pmif, 0, APBDEV_PMC_SCRATCH0_0)));
+
+/*****************************************************************************/
+
+// Mutex for thread-safe access to PMC scratch fields
+static NvOsSpinMutexHandle s_hPmcScratchMutex = NULL;
+
+// Pointer to LP2 Time storage
+static NvUPtr s_pLp2Time = 0;
+
+NvError NvRmPrivOalIntfInit(NvRmDeviceHandle hRmDeviceHandle)
+{
+    NvError e;
+    NV_ASSERT(hRmDeviceHandle);
+
+    // Create PMC scratch register access mutex
+    s_pLp2Time = 0;
+    s_hPmcScratchMutex = NULL;
+    NV_CHECK_ERROR_CLEANUP(NvOsSpinMutexCreate(&s_hPmcScratchMutex));
+
+    // Clear DFS flags; other fields initialized by OAL and preserved by RM
+    SET_POWER_FLD_AP15(hRmDeviceHandle, RM_DFS_FLAG, 0);
+    return NvSuccess;
+
+fail:
+    NvRmPrivOalIntfDeinit(hRmDeviceHandle);
+    return e;
+}
+
+void NvRmPrivOalIntfDeinit(NvRmDeviceHandle hRmDeviceHandle)
+{
+    NvOsSpinMutexDestroy(s_hPmcScratchMutex);
+    s_hPmcScratchMutex = NULL;
+}
+
+/*****************************************************************************/
+
+/*
+ * Write synchronization with the OAL is responsibility of the OAL, i.e., OAL
+ * calls set state function only on entry to LPx state in single-thread
+ * environment
+ */
+void
+NvRmPrivPowerSetState(NvRmDeviceHandle hRmDeviceHandle, NvRmPowerState RmState)
+{
+    SET_POWER_FLD_AP15(hRmDeviceHandle, RM_PWR_STATE, RmState);
+}
+
+NvRmPowerState
+NvRmPrivPowerGetState(NvRmDeviceHandle hRmDeviceHandle)
+{
+    NvRmPowerState state = 0;
+
+    if (!NvRmIsSimulation())
+    {
+        state = GET_POWER_FLD_AP15(hRmDeviceHandle, RM_PWR_STATE);
+    }
+    return state;
+}
+
+/*****************************************************************************/
+
+/*
+ * Read synchronization with the OAL is responsibility of the OAL, i.e., OAL
+ * calls get flags function only on entry to LPx state in single-thread
+ * environment
+ */
+NvU32
+NvRmPrivGetDfsFlags(NvRmDeviceHandle hRmDeviceHandle)
+{
+    NvU32 Flags = 0;
+    if (!NvRmIsSimulation())
+    {
+        Flags = GET_POWER_FLD_AP15(hRmDeviceHandle, RM_DFS_FLAG);
+        if (!(Flags & NvRmDfsStatusFlags_StopPllA0))
+            Flags &= (~NvRmDfsStatusFlags_StopPllP0); // PLLA input from PLLP
+    }
+    return Flags;
+}
+
+void
+NvRmPrivUpdateDfsPauseFlag(
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvBool Pause)
+{
+    if (!NvRmIsSimulation())
+    {
+        NvU32 RegValue;
+        NvU32 RegOffset = APBDEV_PMC_SCRATCH0_0;
+        NvU32 mask = (NvRmDfsStatusFlags_Pause <<
+                      NV_FIELD_SHIFT(APBDEV_PMC_SCRATCH0_0_RM_DFS_FLAG_RANGE));
+
+        NvOsSpinMutexLock(s_hPmcScratchMutex);
+
+        RegValue = NV_REGR(hRmDeviceHandle, NvRmModuleID_Pmif, 0, RegOffset);
+        if (Pause)
+            RegValue |= mask;
+        else
+            RegValue &= ~mask;
+        NV_REGW(hRmDeviceHandle, NvRmModuleID_Pmif, 0, RegOffset, RegValue);
+
+        NvOsSpinMutexUnlock(s_hPmcScratchMutex);
+    }
+}
+
+void
+NvRmPrivPllRefUpdate(
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvRmPllReference* pPllRef,
+    NvBool Increment)
+{
+#if !NV_OAL
+    NvU32 RegValue, mask;
+    NvU32 RegOffset = APBDEV_PMC_SCRATCH0_0;
+
+    // Do nothing for platforms other, than SoC
+    if (NvRmPrivGetExecPlatform(hRmDeviceHandle) != ExecPlatform_Soc)
+        return;
+
+    NV_ASSERT(pPllRef);
+    NV_ASSERT(pPllRef->StopFlag <=
+              NV_FIELD_MASK(APBDEV_PMC_SCRATCH0_0_RM_DFS_FLAG_RANGE));
+    mask = (pPllRef->StopFlag <<
+            NV_FIELD_SHIFT(APBDEV_PMC_SCRATCH0_0_RM_DFS_FLAG_RANGE));
+
+    NvOsSpinMutexLock(s_hPmcScratchMutex);
+
+    if (Increment)
+    {
+        pPllRef->ReferenceCnt++;
+        if (pPllRef->ReferenceCnt == 1)
+        {
+            RegValue = (~mask) &
+                (NV_REGR(hRmDeviceHandle, NvRmModuleID_Pmif, 0, RegOffset));
+            NV_REGW(hRmDeviceHandle, NvRmModuleID_Pmif, 0, RegOffset, RegValue);
+        }
+    }
+    else
+    {
+        NV_ASSERT(pPllRef->ReferenceCnt);
+        if (pPllRef->ReferenceCnt)
+        {
+            pPllRef->ReferenceCnt--;
+            if (pPllRef->ReferenceCnt == 0)
+            {
+                RegValue = mask |
+                    (NV_REGR(hRmDeviceHandle, NvRmModuleID_Pmif, 0, RegOffset));
+                NV_REGW(
+                    hRmDeviceHandle, NvRmModuleID_Pmif, 0, RegOffset, RegValue);
+            }
+        }
+    }
+    NvOsSpinMutexUnlock(s_hPmcScratchMutex);
+#endif
+}
+
+/*****************************************************************************/
+
+/*
+ * Write synchronization with the OAL is responsibility of the OAL, i.e., OAL
+ * calls set state function only in OEMInit() single-thread environment
+ */
+void
+NvRmPrivSetDownloadTransport(
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvOdmDownloadTransport Transport)
+{
+    NV_ASSERT(Transport <=
+              NV_FIELD_MASK(APBDEV_PMC_SCRATCH0_0_RM_LOAD_TRANSPORT_RANGE));
+    SET_POWER_FLD_AP15(hRmDeviceHandle, RM_LOAD_TRANSPORT, Transport);
+}
+
+NvOdmDownloadTransport
+NvRmPrivGetDownloadTransport(NvRmDeviceHandle hRmDeviceHandle)
+{
+    NvOdmDownloadTransport Transport = NvOdmDownloadTransport_None;
+    if (!NvRmIsSimulation())
+    {
+        Transport = GET_POWER_FLD_AP15(hRmDeviceHandle, RM_LOAD_TRANSPORT);
+    }
+    return Transport;
+}
+
+/*****************************************************************************/
+
+void NvRmPrivAp15IoPowerDetectReset(NvRmDeviceHandle hRmDeviceHandle)
+{
+    if (!NvRmIsSimulation())
+    {
+        NvU32 RegValue;
+        NvU32 RegOffset = APBDEV_PMC_SCRATCH0_0;
+        NvOsSpinMutexLock(s_hPmcScratchMutex);
+
+        RegValue =
+            NV_REGR(hRmDeviceHandle, NvRmModuleID_Pmif, 0, RegOffset);
+        RegValue = NV_FLD_SET_DRF_NUM(
+            APBDEV_PMC, SCRATCH0, RST_PWR_DET, 1, RegValue);
+        NV_REGW(hRmDeviceHandle,
+                NvRmModuleID_Pmif, 0, RegOffset, RegValue);
+        RegValue = NV_FLD_SET_DRF_NUM(
+            APBDEV_PMC, SCRATCH0, RST_PWR_DET, 0, RegValue);
+        NV_REGW(hRmDeviceHandle,
+                NvRmModuleID_Pmif, 0, RegOffset, RegValue);
+
+        NvOsSpinMutexUnlock(s_hPmcScratchMutex);
+    }
+}
+
+/*****************************************************************************/
+
+/*
+ * PMC scratch register 21 is dedicated as LP2 time storage.
+ * Write synchronization with the OAL is responsibility of the OAL, i.e., OAL
+ * calls access this register only in single-thread environment.
+ */
+void
+NvRmPrivSetLp2TimeUS(
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvU32 TimeUS)
+{
+    if (NvRmIsSimulation())
+        return;
+
+    {
+        if (s_pLp2Time == 0)
+        {
+            NvRmModuleTable* tbl = NvRmPrivGetModuleTable(hRmDeviceHandle);
+            s_pLp2Time = ((NvUPtr)(tbl->ModInst + 
+                tbl->Modules[NvRmModuleID_Pmif].Index)->VirtAddr) +
+                APBDEV_PMC_SCRATCH21_0;
+        }
+        NV_WRITE32(s_pLp2Time, TimeUS);
+    }
+}
+
+NvU32
+NvRmPrivGetLp2TimeUS(NvRmDeviceHandle hRmDeviceHandle)
+{
+    if (NvRmIsSimulation())
+        return 0;
+
+    {
+        if (s_pLp2Time == 0)
+        {
+            NvRmModuleTable* tbl = NvRmPrivGetModuleTable(hRmDeviceHandle);
+            s_pLp2Time = ((NvUPtr)(tbl->ModInst + 
+                tbl->Modules[NvRmModuleID_Pmif].Index)->VirtAddr) +
+                APBDEV_PMC_SCRATCH21_0;
+        }
+        return NV_READ32(s_pLp2Time);
+    }
+}
+
+/*****************************************************************************/
+
diff --git a/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_private.h b/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_private.h
new file mode 100644
index 000000000000..ed39fe1826b5
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_private.h
@@ -0,0 +1,331 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef AP15RM_PRIVATE_H
+#define AP15RM_PRIVATE_H
+
+/*
+ * ap15rm_private.h defines the private implementation functions for the
+ * resource manager.
+ */
+
+#include "nvcommon.h"
+#include "nvrm_structure.h"
+#include "nvrm_power_private.h"
+#include "nvodm_query.h"
+#include "nvos.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif  /* __cplusplus */
+
+// Enable this macro to catch spurious interrupts. By default this is disabled
+// as we allow spurious interrupts from GPIO controller.
+#if 0
+#define NVRM_INTR_DECODE_ASSERT(x) NV_ASSERT(x)
+#else
+#define NVRM_INTR_DECODE_ASSERT(x) 
+#endif
+
+/**
+ * Find a module given its physical register address
+ *
+ * @param hDevice The RM instance
+ * @param Address Physical base address of the module's registers
+ * @param ModuleId Output parameter to hold the Id of the module (includes
+ *  instance).
+ *
+ * @retval NvSuccess The module id was successfully identified.
+ * @retval NvError_NotSupported No module exists at the specified
+ *  physical base address.
+ * @retval NvError_BadValue Invalid input parameters.
+ */
+NvError
+NvRmPrivFindModule(NvRmDeviceHandle hDevice, NvU32 Address,
+    NvRmPrivModuleID* ModuleId);
+
+/** Driver init for interrupts.
+ */
+void
+NvRmPrivInterruptTableInit( NvRmDeviceHandle hDevice );
+
+/**
+ * Enable interrupt source for interrupt decoder.
+ */
+/**
+ * Disable interrupt source for interrupt decoder.
+ */
+
+/**
+ * Main controller interrupt enable/disable for sub-controllers.
+ */
+
+/**
+ * Interrupt source enable/disable for AP15 main interrupt controllers.
+ */
+
+/**
+ * Chip unque id for AP15 and ap16.
+ */
+NvError
+NvRmPrivAp15ChipUniqueId(
+    NvRmDeviceHandle hDevHandle,
+    void* pId);
+
+// Initialize/deinitialize for various RM submodules.
+NvError NvRmPrivDmaInit(NvRmDeviceHandle hDevice);
+void NvRmPrivDmaDeInit(void);
+
+NvError NvRmPrivSpiSlinkInit(NvRmDeviceHandle hDevice);
+void NvRmPrivSpiSlinkDeInit(void);
+
+/**
+ * Retrieves module instance record pointer given module ID
+ *
+ * @param hDevice The RM device handle
+ * @param ModuleId The combined module ID and instance of the target module
+ * @param out Output storage pointer for instance record pointer
+ *
+ * @retval NvSuccess if instance pointer was successfully retrieved
+ * @retval NvError_BadValue if module ID is invalid
+ */
+NvError
+NvRmPrivGetModuleInstance(
+     NvRmDeviceHandle hDevice,
+     NvRmModuleID ModuleId,
+     NvRmModuleInstance **out);
+
+/*
+ *  OS specific interrupt initialization
+ */
+void
+NvRmPrivInterruptStart(NvRmDeviceHandle hDevice);
+
+/**
+ * Clear out anything that registered for an interrupt but didn't clean up
+ * afteritself.
+ */
+
+void
+NvRmPrivInterruptShutdown(NvRmDeviceHandle hDevice);
+
+/**
+ * Initializes the RM's internal state for tracking the pin-mux register
+ * configurations.  This is done by iteratively applying the pre-defined
+ * configurations from ODM Query (see nvodm_query_pinmux.c).  This function
+ * applies an "enable" setting when there's a match against the static
+ * declarations (in ODM Query).
+ *
+ * As this function walks the configuration list defined in ODM Query, it does
+ * *not* disable (apply tristate settings to) unused pin-groups for a given I/O
+ * module's configuration.  That would be an exercise in futility, since the
+ * current I/O module cannot know if another I/O module is using any unclaimed
+ * pin-groups which the current I/O module configuration might otherwise use.
+ * That system-wide view of pin-group resources is the responsibility of the
+ * System Designer who selects pin-group combinations from the pin-mux
+ * documentation (see //sw/mobile/docs/hw/ap15/pin_mux_configurations.xls).
+ * The selected combination of pin-mux settings (which cannot be in conflict)
+ * are then saved to the configuration tables in ODM Query.
+ *
+ * Further, this initialization routine enables the configuration identified by
+ * the ODM Query tables.  Any pre-existing settings are not changed, except as
+ * defined by the static configuration tables in ODM Query.  Therefore, the
+ * System Designer *must* also account for pre-existing power-on-reset (POR)
+ * values when determining the valid pin-mux configurations saved in ODM Query.
+ *
+ * Finally, any use of the pin-mux registers prior to RM initialization *must*
+ * be consistent with the ODM Query tables, otherwise the system configuration
+ * is not deterministic (and may violate the definition applied by the System
+ * Designer).  Once RM initializes its pin-mux state, any direct access to the
+ * pin-mux registers (ie, not using the RM PinMux API) is strictly prohibited.
+ *
+ * @param hDevice The RM device handle.
+ */
+void
+NvRmPrivInitPinMux(NvRmDeviceHandle hDevice);
+
+/**
+ * Initializes the clock manager.
+ *
+ * @param hRmDevice The RM device handle
+ *
+ * @return NvSuccess if initialization completed successfully
+ *  or one of common error codes on failure
+ */
+NvError
+NvRmPrivClocksInit(NvRmDeviceHandle hRmDevice);
+
+/**
+ * Deinitializes the clock manager.
+ *
+ * @param hRmDevice The RM device handle
+ */
+void
+NvRmPrivClocksDeinit(NvRmDeviceHandle hRmDevice);
+
+
+/*** Private Interrupt API's ***/
+
+
+/**
+ * Performs primary interrupt decode for IRQ interrupts in the main
+ * interrupt controllers.
+ *
+ * @param hRmDevice The RM device handle.
+ * @returns The IRQ number of the interrupting device or NVRM_IRQ_INVALID
+ * if no interrupting device was found.
+ */
+
+
+/**
+ * Performs secondary IRQ interrupt decode for interrupting devices
+ * that are interrupt sub-controllers.
+ *
+ * @param hRmDevice The RM device handle.
+ * @param Irq Primary IRQ number returned from NvRmInterruptPrimaryDecodeIrq().
+ * @returns The IRQ number of the interrupting device.
+ */
+
+
+
+/**
+ * Performs primary interrupt decode for FIQ interrupts in the main
+ * interrupt controllers.
+ *
+ * @param hRmDevice The RM device handle.
+ * @returns The IRQ number of the interrupting device or NVRM_IRQ_INVALID
+ * if no interrupting device was found.
+ */
+
+
+
+/**
+ * Performs secondary FIQ interrupt decode for interrupting devices
+ * that are interrupt sub-controllers.
+ *
+ * @param hRmDevice The RM device handle.
+ * @param Fiq Primary FIQ number returned from NvRmInterruptPrimaryDecodeFiq().
+ * @returns The FIQ number of the interrupting device.
+ */
+
+
+/**
+ * Suspend the dma.
+ */
+NvError NvRmPrivDmaSuspend(void);
+
+/**
+ * Resume the dma.
+ */
+NvError NvRmPrivDmaResume(void);
+
+/**
+ * Check Bond Out to make a module/instance invalid.
+ *
+ * @param hRm The RM device handle
+ */
+void NvRmPrivCheckBondOut( NvRmDeviceHandle hDevice );
+
+/** Returns bond out values and table for AP20 */
+void NvRmPrivAp20GetBondOut( NvRmDeviceHandle hDevice,
+                        const NvU32 **pTable, NvU32 *bondOut );
+
+/**
+ * This API should be sapringly used. There is a bug in the chiplib where the
+ * interrupt handler is not passed an argument. So, the handler will call this
+ * function to get the Rm handle.
+ */
+NvRmDeviceHandle NvRmPrivGetRmDeviceHandle( void );
+
+/** Returns the pointer to the relocation table of AP15 chip */
+NvU32 *NvRmPrivAp15GetRelocationTable( NvRmDeviceHandle hDevice );
+
+/** Returns the pointer to the relocation table of AP16 chip */
+NvU32 *NvRmPrivAp16GetRelocationTable( NvRmDeviceHandle hDevice );
+
+/** Returns the pointer to the relocation table of AP20 chip */
+NvU32 *NvRmPrivAp20GetRelocationTable( NvRmDeviceHandle hDevice );
+
+/** Basic reset of AP15 chip modules */
+void NvRmPrivAp15BasicReset( NvRmDeviceHandle hDevice );
+/** Basic reset of AP20 chip modules */
+void NvRmPrivAp20BasicReset( NvRmDeviceHandle hDevice );
+
+/** This API starts the memory controller error monitoring for AP15/AP16. */
+NvError NvRmPrivAp15McErrorMonitorStart( NvRmDeviceHandle hDevice );
+
+/** This API stops the memory controller error monitoring for AP15/AP16. */
+void NvRmPrivAp15McErrorMonitorStop( NvRmDeviceHandle hDevice );
+
+/** This API starts the memory controller error monitoring for AP20. */
+NvError NvRmPrivAp20McErrorMonitorStart( NvRmDeviceHandle hDevice );
+
+/** This API stops the memory controller error monitoring for AP20. */
+void NvRmPrivAp20McErrorMonitorStop( NvRmDeviceHandle hDevice );
+
+/** This API sets up the memory controller for AP15/AP16. */
+void NvRmPrivAp15SetupMc(NvRmDeviceHandle hRm);
+
+/** This API sets up the memory controller for AP20. */
+void NvRmPrivAp20SetupMc(NvRmDeviceHandle hRm);
+
+/** This API sets up AP20 MC for stat collection */
+void McStatAp20_Start(NvRmDeviceHandle rm, NvU32 client_id_0, NvU32 client_id_1, NvU32 llc_client_id);
+
+/** This API stops stat collection  for AP20 MC */
+void McStatAp20_Stop(NvRmDeviceHandle rm, NvU32 *client_0_cycles,
+                      NvU32 *client_1_cycles, NvU32 *llc_client_cycles,
+                      NvU32 *llc_client_clocks, NvU32 *mc_clocks);
+
+
+/* init and deinit the keylist */
+NvError NvRmPrivInitKeyList(NvRmDeviceHandle hRm, const NvU32*, NvU32);
+void NvRmPrivDeInitKeyList(NvRmDeviceHandle hRm);
+
+/**
+ * @brief Query the max interface freq supported by the board for a given
+ * Module.
+ *
+ * This API returns the max interface freq supported by the board based on the 
+ * ODM query. 
+ */
+NvRmFreqKHz
+NvRmPrivGetInterfaceMaxClock(
+    NvRmDeviceHandle hRmDevice,
+    NvRmModuleID ModuleId);
+
+#ifdef __cplusplus
+}
+#endif  /* __cplusplus */
+
+#endif // AP15RM_PRIVATE_H
diff --git a/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_reloctable.c b/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_reloctable.c
new file mode 100644
index 000000000000..1854820e6de9
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_reloctable.c
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include "nvcommon.h"
+#include "nvos.h"
+#include "nvrm_init.h"
+#include "common/nvrm_hwintf.h"
+#include "ap15/project_relocation_table.h"
+#include "ap15rm_private.h"
+
+static NvU32 s_RelocationTable[] =
+{
+    NV_RELOCATION_TABLE_INIT
+};
+
+NvU32 *
+NvRmPrivAp15GetRelocationTable( NvRmDeviceHandle hDevice )
+{
+    return s_RelocationTable;
+}
+
diff --git a/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_xpc.c b/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_xpc.c
new file mode 100644
index 000000000000..8b92ae4b5933
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_xpc.c
@@ -0,0 +1,432 @@
+/*
+ * Copyright (c) 2010 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/** 
+ * @file
+ * @brief <b>nVIDIA Driver Development Kit: 
+ *           Cross Proc Communication driver </b>
+ *
+ * @b Description: Implements the interface to the NvDdk XPC.
+ * 
+ */
+
+#include "nvrm_xpc.h"
+#include "nvrm_memmgr.h"
+#include "ap15rm_xpc_hw_private.h"
+#include "nvrm_hardware_access.h"
+#include "nvassert.h"
+#include "ap15/ararb_sema.h"
+#include "ap15/arictlr_arbgnt.h"
+#include "nvrm_avp_shrd_interrupt.h"
+
+// Minimum sdram offset required so that avp can access the address which is 
+// passed.
+// AVP can not access the 0x0000:0000 to 0x0000:0040
+enum { MIN_SDRAM_OFFSET = 0x100};
+
+
+//There are only 32 arb semaphores
+#define MAX_ARB_NUM 32
+
+#define ARBSEMA_REG_READ(pArbSemaVirtAdd, reg) \
+        NV_READ32(pArbSemaVirtAdd + (ARB_SEMA_##reg##_0))
+
+#define ARBSEMA_REG_WRITE(pArbSemaVirtAdd, reg, data) \
+        NV_WRITE32(pArbSemaVirtAdd + (ARB_SEMA_##reg##_0), (data));
+
+#define ARBGNT_REG_READ(pArbGntVirtAdd, reg) \
+        NV_READ32(pArbGntVirtAdd + (ARBGNT_##reg##_0))
+
+#define ARBGNT_REG_WRITE(pArbGntVirtAdd, reg, data) \
+        NV_WRITE32(pArbGntVirtAdd + (ARBGNT_##reg##_0), (data));
+
+static NvOsInterruptHandle s_arbInterruptHandle = NULL;
+
+// Combines the Processor Xpc system details. This contains the details of the
+// receive/send message queue and messaging system.
+typedef struct NvRmPrivXpcMessageRec
+{
+    NvRmDeviceHandle hDevice;
+
+    // Hw mail box register.
+    CpuAvpHwMailBoxReg HwMailBoxReg;
+
+} NvRmPrivXpcMessage;
+
+typedef struct NvRmPrivXpcArbSemaRec
+{
+    NvRmDeviceHandle hDevice;
+    NvU8 *pArbSemaVirtAddr;
+    NvU8 *pArbGntVirtAddr;
+    NvOsSemaphoreHandle semaphore[MAX_ARB_NUM];
+    NvOsMutexHandle mutex[MAX_ARB_NUM];
+    NvOsIntrMutexHandle hIntrMutex;
+
+} NvRmPrivXpcArbSema;
+
+static NvRmPrivXpcArbSema s_ArbSema;
+
+//Forward declarations
+static NvError InitArbSemaSystem(NvRmDeviceHandle hDevice);
+static void ArbSemaIsr(void *args);
+NvU32 GetArbIdFromRmModuleId(NvRmModuleID modId);
+/**
+ * Initialize the cpu avp hw mail box address and map the hw register address 
+ * to virtual address.
+ * Thread Safety: Caller responsibility
+ */
+static NvError 
+InitializeCpuAvpHwMailBoxRegister(NvRmPrivXpcMessageHandle hXpcMessage)
+{
+    NvError e;
+    NvRmPhysAddr ResourceSemaPhysAddr;
+
+    // Get base address of the hw mail box register. This register is in the set
+    // of resource semaphore module Id.
+    NvRmModuleGetBaseAddress(hXpcMessage->hDevice,
+        NVRM_MODULE_ID(NvRmModuleID_ResourceSema, 0),
+        &ResourceSemaPhysAddr, &hXpcMessage->HwMailBoxReg.BankSize);
+
+    // Map the base address to the virtual address.                
+    hXpcMessage->HwMailBoxReg.pHwMailBoxRegBaseVirtAddr = NULL;
+    NV_CHECK_ERROR(NvRmPhysicalMemMap(
+        ResourceSemaPhysAddr, hXpcMessage->HwMailBoxReg.BankSize,
+        NVOS_MEM_READ_WRITE, NvOsMemAttribute_Uncached,
+        (void **)&hXpcMessage->HwMailBoxReg.pHwMailBoxRegBaseVirtAddr));
+
+    NvRmPrivXpcHwResetOutbox(&hXpcMessage->HwMailBoxReg);
+
+    return NvSuccess;
+}
+
+/**
+ * DeInitialize the cpu avp hw mail box address and unmap the hw register address 
+ * virtual address.
+ * Thread Safety: Caller responsibility
+ */
+static void DeInitializeCpuAvpHwMailBoxRegister(NvRmPrivXpcMessageHandle hXpcMessage)
+{
+    // Unmap the hw register base virtual address
+    NvRmPhysicalMemUnmap(hXpcMessage->HwMailBoxReg.pHwMailBoxRegBaseVirtAddr,
+                        hXpcMessage->HwMailBoxReg.BankSize);
+    hXpcMessage->HwMailBoxReg.pHwMailBoxRegBaseVirtAddr = NULL;        
+}
+
+/**
+ * Create the cpu-avp messaging system.
+ * This function will call other helper function to create the messaging technique 
+ * used for cpu-avp communication.
+ * Thread Safety: Caller responsibility
+ */
+static NvError 
+CreateCpuAvpMessagingSystem(NvRmPrivXpcMessageHandle hXpcMessage)
+{
+    NvError Error = NvSuccess;
+
+    Error = InitializeCpuAvpHwMailBoxRegister(hXpcMessage);
+
+#if NV_IS_AVP
+    hXpcMessage->HwMailBoxReg.IsCpu = NV_FALSE;
+#else            
+    hXpcMessage->HwMailBoxReg.IsCpu = NV_TRUE;
+#endif            
+    
+    // If error found then destroy all the allocation and initialization,
+    if (Error)
+        DeInitializeCpuAvpHwMailBoxRegister(hXpcMessage);
+
+    return Error;
+}
+
+
+/**
+ * Destroy the cpu-avp messaging system.
+ * This function destroy all the allocation/initialization done for creating
+ * the cpu-avp messaging system.
+ * Thread Safety: Caller responsibility
+ */
+static void DestroyCpuAvpMessagingSystem(NvRmPrivXpcMessageHandle hXpcMessage)
+{
+    // Destroy the cpu-avp hw mail box registers. 
+    DeInitializeCpuAvpHwMailBoxRegister(hXpcMessage);
+    hXpcMessage->HwMailBoxReg.pHwMailBoxRegBaseVirtAddr = NULL;
+    hXpcMessage->HwMailBoxReg.BankSize = 0;
+}
+
+
+NvError 
+NvRmPrivXpcCreate(
+    NvRmDeviceHandle hDevice,
+    NvRmPrivXpcMessageHandle *phXpcMessage)
+{
+    NvError Error = NvSuccess;
+    NvRmPrivXpcMessageHandle hNewXpcMsgHandle = NULL;
+
+    *phXpcMessage = NULL;
+
+    // Allocates the memory for the xpc message handle.
+    hNewXpcMsgHandle = NvOsAlloc(sizeof(*hNewXpcMsgHandle));
+    if (!hNewXpcMsgHandle)
+    {
+        return NvError_InsufficientMemory;
+    }
+
+    // Initialize all the members of the xpc message handle.
+    hNewXpcMsgHandle->hDevice = hDevice;
+    hNewXpcMsgHandle->HwMailBoxReg.pHwMailBoxRegBaseVirtAddr = NULL;
+    hNewXpcMsgHandle->HwMailBoxReg.BankSize = 0;
+
+    // Create the messaging system between the processors.
+    Error = CreateCpuAvpMessagingSystem(hNewXpcMsgHandle);
+
+    // if error the destroy all allocations done here.    
+    if (Error)
+    {
+        NvOsFree(hNewXpcMsgHandle);
+        hNewXpcMsgHandle = NULL;
+    }
+
+#if NV_IS_AVP
+    Error = InitArbSemaSystem(hDevice);
+    if (Error)
+    {
+        NvOsFree(hNewXpcMsgHandle);
+        hNewXpcMsgHandle = NULL;
+    }
+#endif
+
+    // Copy the new xpc message handle into the passed parameter.
+    *phXpcMessage = hNewXpcMsgHandle;
+    return Error;
+}
+
+
+/**
+ * Destroy the Rm Xpc message handle.
+ * Thread Safety: It is provided inside the function.
+ */
+void NvRmPrivXpcDestroy(NvRmPrivXpcMessageHandle hXpcMessage)
+{
+    // If not a null pointer then destroy.
+    if (hXpcMessage)
+    {
+        // Destroy the messaging system between processor.
+        DestroyCpuAvpMessagingSystem(hXpcMessage);
+
+        // Free the allocated memory for the xpc message handle.
+        NvOsFree(hXpcMessage);
+    }
+}
+
+
+// Set the outbound mailbox with the given data.  We might have to spin until
+// it's safe to send the message.
+NvError
+NvRmPrivXpcSendMessage(NvRmPrivXpcMessageHandle hXpcMessage, NvU32 data)
+{
+    NvRmPrivXpcHwSendMessageToTarget(&hXpcMessage->HwMailBoxReg, data);
+    return NvSuccess;
+}
+
+
+// Get the value currently in the inbox register.  This read clears the incoming
+// interrupt.
+NvU32
+NvRmPrivXpcGetMessage(NvRmPrivXpcMessageHandle hXpcMessage)
+{
+    NvU32 data;
+    NvRmPrivXpcHwReceiveMessageFromTarget(&hXpcMessage->HwMailBoxReg, &data);
+    return data;
+}
+
+NvError NvRmXpcInitArbSemaSystem(NvRmDeviceHandle hDevice)
+{
+#if NV_IS_AVP
+    return NvSuccess;
+#else
+    return InitArbSemaSystem(hDevice);
+#endif
+}
+
+static NvError InitArbSemaSystem(NvRmDeviceHandle hDevice)
+{
+    NvOsInterruptHandler ArbSemaHandler;
+    NvRmPhysAddr ArbSemaBase, ArbGntBase;
+    NvU32        ArbSemaSize, ArbGntSize;
+    NvU32 irq;
+    NvError e;
+    NvU32 i = 0;
+
+    irq = NvRmGetIrqForLogicalInterrupt(
+             hDevice, NvRmModuleID_ArbitrationSema, 0);
+
+    ArbSemaHandler = ArbSemaIsr;
+
+    NV_CHECK_ERROR_CLEANUP(
+        NvRmInterruptRegister(hDevice, 1, &irq, &ArbSemaHandler,
+            hDevice, &s_arbInterruptHandle, NV_TRUE)
+    );
+    
+    NvRmModuleGetBaseAddress(hDevice,
+            NVRM_MODULE_ID(NvRmModuleID_ArbitrationSema, 0), 
+            &ArbSemaBase, &ArbSemaSize);
+    
+    NvRmModuleGetBaseAddress(hDevice,
+            NVRM_MODULE_ID(NvRmPrivModuleID_InterruptArbGnt, 0), 
+            &ArbGntBase, &ArbGntSize);
+
+    NV_CHECK_ERROR_CLEANUP(
+        NvRmPhysicalMemMap(ArbSemaBase, ArbSemaSize, NVOS_MEM_READ_WRITE,
+            NvOsMemAttribute_Uncached, (void**)&s_ArbSema.pArbSemaVirtAddr)
+    );
+
+    NV_CHECK_ERROR_CLEANUP(
+        NvRmPhysicalMemMap(ArbGntBase, ArbGntSize, NVOS_MEM_READ_WRITE,
+            NvOsMemAttribute_Uncached, (void**)&s_ArbSema.pArbGntVirtAddr)
+    );
+
+    //Initialize all the semaphores and mutexes
+    for (i=0;i<MAX_ARB_NUM;i++)
+    {
+        NV_CHECK_ERROR_CLEANUP(
+            NvOsSemaphoreCreate(&s_ArbSema.semaphore[i], 0)
+        );
+
+        NV_CHECK_ERROR_CLEANUP(
+            NvOsMutexCreate(&s_ArbSema.mutex[i])
+        );
+    }
+
+    NV_CHECK_ERROR_CLEANUP(
+        NvOsIntrMutexCreate(&s_ArbSema.hIntrMutex)
+    );
+
+fail:
+
+    return e;
+}
+
+
+static void ArbSemaIsr(void *args)
+{
+    NvU32 int_mask, proc_int_enable, arb_gnt, i = 0;
+
+    NvOsIntrMutexLock(s_ArbSema.hIntrMutex);
+    //Check which arb semaphores have been granted to this processor
+    arb_gnt = ARBSEMA_REG_READ(s_ArbSema.pArbSemaVirtAddr, SMP_GNT_ST);
+
+    //Figure out which arb semaphores were signalled and then disable them.
+#if NV_IS_AVP
+    proc_int_enable = ARBGNT_REG_READ(s_ArbSema.pArbGntVirtAddr, COP_ENABLE);
+    int_mask = arb_gnt & proc_int_enable;
+    ARBGNT_REG_WRITE(s_ArbSema.pArbGntVirtAddr, 
+        COP_ENABLE, (proc_int_enable & ~int_mask));
+#else
+    proc_int_enable = ARBGNT_REG_READ(s_ArbSema.pArbGntVirtAddr, CPU_ENABLE);
+    int_mask = arb_gnt & proc_int_enable;
+    ARBGNT_REG_WRITE(s_ArbSema.pArbGntVirtAddr, 
+        CPU_ENABLE, (proc_int_enable & ~int_mask));
+#endif
+        
+    //Signal all the required semaphores
+    do
+    {
+        if (int_mask & 0x1)
+        {
+            NvOsSemaphoreSignal(s_ArbSema.semaphore[i]);
+        }
+        int_mask >>= 1;
+        i++;
+        
+    } while (int_mask);
+
+    NvOsIntrMutexUnlock(s_ArbSema.hIntrMutex);
+    NvRmInterruptDone(s_arbInterruptHandle);
+}
+
+NvU32 GetArbIdFromRmModuleId(NvRmModuleID modId)
+{
+    NvU32 arbId;
+
+    switch(modId)
+    {
+        case NvRmModuleID_BseA:
+            arbId = NvRmArbSema_Bsea;
+            break;
+        case NvRmModuleID_Vde:
+        default:
+            arbId = NvRmArbSema_Vde;
+            break;
+    }
+    
+    return arbId;
+}
+
+void NvRmXpcModuleAcquire(NvRmModuleID modId)
+{
+    NvU32 RequestedSemaNum;
+    NvU32 reg;
+
+    RequestedSemaNum = GetArbIdFromRmModuleId(modId);
+
+    NvOsMutexLock(s_ArbSema.mutex[RequestedSemaNum]);
+    NvOsIntrMutexLock(s_ArbSema.hIntrMutex);
+
+    //Try to grab the lock
+    ARBSEMA_REG_WRITE(s_ArbSema.pArbSemaVirtAddr, SMP_GET, 1 << RequestedSemaNum);
+
+    //Enable arb sema interrupt
+#if NV_IS_AVP
+    reg = ARBGNT_REG_READ(s_ArbSema.pArbGntVirtAddr, COP_ENABLE);
+    reg |= (1 << RequestedSemaNum);
+    ARBGNT_REG_WRITE(s_ArbSema.pArbGntVirtAddr, COP_ENABLE, reg);
+#else
+    reg = ARBGNT_REG_READ(s_ArbSema.pArbGntVirtAddr, CPU_ENABLE);
+    reg |= (1 << RequestedSemaNum);
+    ARBGNT_REG_WRITE(s_ArbSema.pArbGntVirtAddr, CPU_ENABLE, reg);
+#endif
+
+    NvOsIntrMutexUnlock(s_ArbSema.hIntrMutex);
+    NvOsSemaphoreWait(s_ArbSema.semaphore[RequestedSemaNum]);
+}
+
+void NvRmXpcModuleRelease(NvRmModuleID modId)
+{
+    NvU32 RequestedSemaNum;
+
+    RequestedSemaNum = GetArbIdFromRmModuleId(modId);
+
+    //Release the lock
+    ARBSEMA_REG_WRITE(s_ArbSema.pArbSemaVirtAddr, SMP_PUT, 1 << RequestedSemaNum);
+
+    NvOsMutexUnlock(s_ArbSema.mutex[RequestedSemaNum]);
+}
diff --git a/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_xpc_hw_private.c b/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_xpc_hw_private.c
new file mode 100644
index 000000000000..ffd1dc5d6ebd
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_xpc_hw_private.c
@@ -0,0 +1,165 @@
+/*
+ * Copyright (c) 2010 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/** 
+ * @file
+ * @brief <b>nVIDIA Driver Development Kit: 
+ *           Cross Processor Communication driver </b>
+ *
+ * @b Description: Implements the cross processor communication Hw Access APIs
+ * 
+ */
+ 
+#include "nvcommon.h"
+#include "nvassert.h"
+#include "nvrm_drf.h"
+#include "nvrm_hardware_access.h"
+#include "ap15rm_xpc_hw_private.h"
+#include "ap15/arres_sema.h"
+
+enum {MESSAGE_BOX_MESSAGE_LENGTH_BITS = 28};
+#define RESSEMA_REG_READ32(pResSemaHwRegVirtBaseAdd, reg) \
+    NV_READ32((pResSemaHwRegVirtBaseAdd) + (RES_SEMA_##reg##_0)/4)
+
+#define RESSEMA_REG_WRITE32(pResSemaHwRegVirtBaseAdd, reg, val) \
+   do { \
+         NV_WRITE32(((pResSemaHwRegVirtBaseAdd) + ((RES_SEMA_##reg##_0)/4)), (val)); \
+   } while(0)
+
+void NvRmPrivXpcHwResetOutbox(CpuAvpHwMailBoxReg *pHwMailBoxReg)
+{
+    NvU32 OutboxMessage;
+    NvU32 OutboxVal;
+
+    OutboxMessage = 0;
+
+    // Write Outbox in the message box
+    // Enable the Valid tag
+    // Enable interrupt
+#if NV_IS_AVP
+    OutboxVal = RESSEMA_REG_READ32(pHwMailBoxReg->pHwMailBoxRegBaseVirtAddr,SHRD_INBOX);
+    OutboxVal = NV_FLD_SET_DRF_NUM(RES_SEMA, SHRD_INBOX, IN_BOX_STAT, 0, OutboxVal);
+    OutboxVal = NV_FLD_SET_DRF_NUM(RES_SEMA, SHRD_INBOX, IN_BOX_DATA, 0, OutboxVal);
+    OutboxVal = NV_FLD_SET_DRF_NUM(RES_SEMA, SHRD_INBOX, IN_BOX_CMD, 0, OutboxVal);
+    OutboxVal |= OutboxMessage;
+    OutboxVal = NV_FLD_SET_DRF_NUM(RES_SEMA, SHRD_INBOX, IE_IBE, 0, OutboxVal);
+    OutboxVal = NV_FLD_SET_DRF_NUM(RES_SEMA, SHRD_INBOX, TAG, 0, OutboxVal);
+    RESSEMA_REG_WRITE32(pHwMailBoxReg->pHwMailBoxRegBaseVirtAddr, SHRD_INBOX, OutboxVal);
+#else        
+    OutboxVal = RESSEMA_REG_READ32(pHwMailBoxReg->pHwMailBoxRegBaseVirtAddr,SHRD_OUTBOX);
+    OutboxVal = NV_FLD_SET_DRF_NUM(RES_SEMA, SHRD_OUTBOX, OUT_BOX_CMD, 0, OutboxVal);
+    OutboxVal = NV_FLD_SET_DRF_NUM(RES_SEMA, SHRD_OUTBOX, OUT_BOX_STAT, 0, OutboxVal);
+    OutboxVal = NV_FLD_SET_DRF_NUM(RES_SEMA, SHRD_OUTBOX, OUT_BOX_DATA, 0, OutboxVal);
+    OutboxVal |= OutboxMessage;
+    OutboxVal = NV_FLD_SET_DRF_NUM(RES_SEMA, SHRD_OUTBOX, IE_OBE, 0, OutboxVal);
+    OutboxVal = NV_FLD_SET_DRF_NUM(RES_SEMA, SHRD_OUTBOX, TAG, 0, OutboxVal);
+    RESSEMA_REG_WRITE32(pHwMailBoxReg->pHwMailBoxRegBaseVirtAddr, SHRD_OUTBOX, OutboxVal);
+#endif        
+}
+
+
+/**
+ * Send message to the target.
+ */
+void
+NvRmPrivXpcHwSendMessageToTarget(
+    CpuAvpHwMailBoxReg *pHwMailBoxReg,
+    NvRmPhysAddr MessageAddress)
+{
+    NvU32 OutboxMessage;
+    NvU32 OutboxVal = 0;
+
+    OutboxMessage = ((NvU32)(MessageAddress)) >> (32 - MESSAGE_BOX_MESSAGE_LENGTH_BITS);
+    
+    // Write Outbox in the message box
+    // Enable the Valid tag
+    // Enable interrupt
+#if NV_IS_AVP
+    // !!! not sure why this would need to be read/modify/write
+//    OutboxVal = RESSEMA_REG_READ32(pHwMailBoxReg->pHwMailBoxRegBaseVirtAddr,SHRD_INBOX);
+    OutboxVal = NV_FLD_SET_DRF_NUM(RES_SEMA, SHRD_INBOX, IN_BOX_STAT, 0, OutboxVal);
+    OutboxVal = NV_FLD_SET_DRF_NUM(RES_SEMA, SHRD_INBOX, IN_BOX_DATA, 0, OutboxVal);
+    OutboxVal = NV_FLD_SET_DRF_NUM(RES_SEMA, SHRD_INBOX, IN_BOX_CMD, 0, OutboxVal);
+    OutboxVal |= OutboxMessage;
+    OutboxVal = NV_FLD_SET_DRF_DEF(RES_SEMA, SHRD_INBOX, IE_IBF, FULL, OutboxVal);
+//    OutboxVal = NV_FLD_SET_DRF_DEF(RES_SEMA, SHRD_INBOX, IE_IBE, EMPTY, OutboxVal);
+    OutboxVal = NV_FLD_SET_DRF_DEF(RES_SEMA, SHRD_INBOX, TAG, VALID, OutboxVal);
+    RESSEMA_REG_WRITE32(pHwMailBoxReg->pHwMailBoxRegBaseVirtAddr, SHRD_INBOX, OutboxVal);
+#else        
+    // !!! not sure why this would need to be read/modify/write
+//    OutboxVal = RESSEMA_REG_READ32(pHwMailBoxReg->pHwMailBoxRegBaseVirtAddr,SHRD_OUTBOX);
+    OutboxVal = NV_FLD_SET_DRF_NUM(RES_SEMA, SHRD_OUTBOX, OUT_BOX_CMD, 0, OutboxVal);
+    OutboxVal = NV_FLD_SET_DRF_NUM(RES_SEMA, SHRD_OUTBOX, OUT_BOX_STAT, 0, OutboxVal);
+    OutboxVal = NV_FLD_SET_DRF_NUM(RES_SEMA, SHRD_OUTBOX, OUT_BOX_DATA, 0, OutboxVal);
+    OutboxVal |= OutboxMessage;
+    OutboxVal = NV_FLD_SET_DRF_DEF(RES_SEMA, SHRD_OUTBOX, IE_OBF, FULL, OutboxVal);
+//    OutboxVal = NV_FLD_SET_DRF_DEF(RES_SEMA, SHRD_OUTBOX, IE_OBE, EMPTY, OutboxVal);
+    OutboxVal = NV_FLD_SET_DRF_DEF(RES_SEMA, SHRD_OUTBOX, TAG, VALID, OutboxVal);
+    RESSEMA_REG_WRITE32(pHwMailBoxReg->pHwMailBoxRegBaseVirtAddr, SHRD_OUTBOX, OutboxVal);
+#endif        
+}
+
+
+
+/**
+ * Receive message from the target.
+ */
+void
+NvRmPrivXpcHwReceiveMessageFromTarget(
+    CpuAvpHwMailBoxReg *pHwMailBoxReg,
+    NvRmPhysAddr *pMessageAddress)
+{
+    NvU32 InboxMessage = 0;
+    NvU32 InboxVal;
+
+    // Read the inbox. Lower 28 bit contains the message.
+#if NV_IS_AVP        
+    InboxVal = RESSEMA_REG_READ32(pHwMailBoxReg->pHwMailBoxRegBaseVirtAddr,SHRD_OUTBOX);
+    RESSEMA_REG_WRITE32(pHwMailBoxReg->pHwMailBoxRegBaseVirtAddr, SHRD_OUTBOX, 0);
+#else        
+    InboxVal = RESSEMA_REG_READ32(pHwMailBoxReg->pHwMailBoxRegBaseVirtAddr,SHRD_INBOX);
+    RESSEMA_REG_WRITE32(pHwMailBoxReg->pHwMailBoxRegBaseVirtAddr, SHRD_INBOX, 0);
+#endif        
+    if (InboxVal & NV_DRF_DEF(RES_SEMA, SHRD_INBOX, TAG, VALID))
+    {
+         pHwMailBoxReg->MailBoxData = InboxVal;
+    }
+
+    InboxVal = (pHwMailBoxReg->MailBoxData) & (0xFFFFFFFFUL >> (32 - MESSAGE_BOX_MESSAGE_LENGTH_BITS));
+    InboxMessage = (InboxVal << (32 - MESSAGE_BOX_MESSAGE_LENGTH_BITS));
+
+    *pMessageAddress = InboxMessage;
+}
+
+
+
+
diff --git a/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_xpc_hw_private.h b/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_xpc_hw_private.h
new file mode 100644
index 000000000000..c5822526b9c8
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_xpc_hw_private.h
@@ -0,0 +1,92 @@
+/*
+ * Copyright (c) 2010 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/** 
+ * @file
+ * @brief <b>nVIDIA Driver Development Kit: 
+ *           Priate Hw access function for XPC driver </b>
+ *
+ * @b Description: Defines the private interface functions for the xpc 
+ * 
+ */
+
+#ifndef INCLUDED_RM_XPC_HW_PRIVATE_H
+#define INCLUDED_RM_XPC_HW_PRIVATE_H
+
+
+#include "nvcommon.h"
+#include "nvrm_init.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+// Combines the cpu avp hw mail baox system information.
+typedef struct CpuAvpHwMailBoxRegRec
+{
+    // Hw mail box register virtual base address.
+    NvU32 *pHwMailBoxRegBaseVirtAddr;
+    
+    // Bank size of the hw regsiter.
+    NvU32 BankSize;
+
+    // Tells whether this is on cpu or on Avp
+    NvBool IsCpu;
+
+    // Mail box data which was read last time.
+    NvU32 MailBoxData;
+} CpuAvpHwMailBoxReg;
+
+void NvRmPrivXpcHwResetOutbox(CpuAvpHwMailBoxReg *pHwMailBoxReg);
+
+/**
+ * Send message to the target.
+ */
+void
+NvRmPrivXpcHwSendMessageToTarget(
+    CpuAvpHwMailBoxReg *pHwMailBoxReg,
+    NvRmPhysAddr MessageAddress);
+
+/**
+ * Receive message from the target.
+ */
+void
+NvRmPrivXpcHwReceiveMessageFromTarget(
+    CpuAvpHwMailBoxReg *pHwMailBoxReg,
+    NvRmPhysAddr *pMessageAddress);
+
+
+#if defined(__cplusplus)
+ }
+#endif
+
+#endif  // INCLUDED_RM_XPC_HW_PRIVATE_H
diff --git a/arch/arm/mach-tegra/nvrm/core/ap15/ap16rm_pinmux_tables.c b/arch/arm/mach-tegra/nvrm/core/ap15/ap16rm_pinmux_tables.c
new file mode 100644
index 000000000000..09c53e93d9af
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/core/ap15/ap16rm_pinmux_tables.c
@@ -0,0 +1,323 @@
+/*
+ * Copyright (c) 2008-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include "nvcommon.h"
+#include "nvrm_pinmux.h"
+#include "nvrm_drf.h"
+#include "nvassert.h"
+#include "nvrm_hwintf.h"
+#include "ap15rm_private.h"
+#include "ap16/arapb_misc.h"
+#include "ap15/arclk_rst.h"
+#include "ap15rm_pinmux_utils.h"
+#include "nvodm_query_pinmux.h"
+#include "nvrm_clocks.h"
+
+extern const NvU32 g_Ap15MuxI2c1[];
+extern const NvU32 g_Ap15MuxI2c2[];
+extern const NvU32* g_Ap15MuxI2c[];
+
+extern const NvU32 g_Ap15MuxI2c_Pmu[];
+extern const NvU32* g_Ap15MuxI2cPmu[];
+
+extern const NvU32 g_Ap15Mux_Mmc[];
+extern const NvU32* g_Ap15MuxMmc[];
+
+extern const NvU32 g_Ap15MuxSdio2[];
+extern const NvU32 g_Ap15MuxSdio3[];
+extern const NvU32* g_Ap15MuxSdio[];
+
+extern const NvU32 g_Ap15Mux_Spdif[];
+extern const NvU32* g_Ap15MuxSpdif[];
+
+static const NvU32 g_Ap16MuxUart1[] = {
+    //  Reset config - abandon IRRX, IRTX &amp; SDD
+    UNCONFIG(C,IRRX,UARTA,RSVD2), UNCONFIG(C,IRTX,UARTA,RSVD2), UNCONFIG(D,SDD,UARTA,PWM), CONFIGEND(),
+    //  8b UAA + UAB pads
+    CONFIG(B,A,UAA,UARTA), CONFIG(B,A,UAB,UARTA), CONFIGEND(),
+    //  4b UAA pads
+    CONFIG(B,A,UAA,UARTA), CONFIGEND(),
+     //  7b GPU pads
+    CONFIG(A,D,GPU,UARTA), CONFIGEND(),
+    //  4b VFIR + UAD pads
+    CONFIG(A,C,IRRX,UARTA), CONFIG(A,C,IRTX,UARTA), CONFIG(B,A,UAD,UARTA), CONFIGEND(),
+    //  2b VFIR pads
+    CONFIG(A,C,IRRX,UARTA), CONFIG(A,C,IRTX,UARTA), CONFIGEND(),
+    //  2b SDIO pads
+    CONFIG(B,D,SDD,UARTA), CONFIGEND(),
+    MODULEDONE()
+};
+static const NvU32 g_Ap16MuxUart2[] = {
+//  Reset config - abandon UAD. pads.chosen SFLASH pads
+    UNCONFIG(A,UAD,IRDA,SFLASH), CONFIGEND(),
+//  4b UAD + IRRX + IRTX pads
+    CONFIG(B,A,UAD,IRDA), CONFIG(A,C,IRRX,UARTB), CONFIG(A,C,IRTX,UARTB), CONFIGEND(),
+//..2b UAD pads
+    CONFIG(B,A,UAD,IRDA), CONFIGEND(),
+    MODULEDONE()
+};
+
+static const NvU32 g_Ap16MuxUart3[] = {
+    //  Reset config - abandon UCA. chosen RSVD1
+    UNCONFIG(B,UCA,UARTC,RSVD1), CONFIGEND(),
+    //  4b UCA + UCB pads
+    CONFIG(B,B,UCA,UARTC), CONFIG(B,B,UCB,UARTC), CONFIGEND(),
+    //  2b UCA pads
+    CONFIG(B,B,UCA,UARTC), CONFIGEND(),
+    MODULEDONE()
+};
+
+static const NvU32* g_Ap16MuxUart[] = {
+    &g_Ap16MuxUart1[0],
+    &g_Ap16MuxUart2[0],
+    &g_Ap16MuxUart3[0],
+    NULL
+};
+extern const NvU32 g_Ap15MuxSpi1[];
+extern const NvU32 g_Ap15MuxSpi2[];
+extern const NvU32 g_Ap15MuxSpi3[];
+extern const NvU32* g_Ap15MuxSpi[];
+
+extern const NvU32 g_Ap15Mux_Sflash[];
+extern const NvU32* g_Ap15MuxSflash[];
+
+extern const NvU32 g_Ap15Mux_Twc[];
+extern const NvU32* g_Ap15MuxTwc[];
+
+extern const NvU32 g_Ap15Mux_Ata[];
+extern const NvU32* g_Ap15MuxAta[];
+
+extern const NvU32 g_Ap15Mux_Pwm[];
+extern const NvU32* g_Ap15MuxPwm[];
+
+extern const NvU32 g_Ap15Mux_Hsi[];
+extern const NvU32 *g_Ap15MuxHsi[];
+
+extern const NvU32 g_Ap15Mux_Nand[];
+extern const NvU32* g_Ap15MuxNand[];
+
+extern const NvU32 g_Ap15MuxDap1[];
+extern const NvU32 g_Ap15MuxDap2[];
+extern const NvU32 g_Ap15MuxDap3[];
+extern const NvU32 g_Ap15MuxDap4[];
+extern const NvU32* g_Ap15MuxDap[];
+
+extern const NvU32 g_Ap15Mux_Kbc[];
+extern const NvU32* g_Ap15MuxKbc[];
+
+extern const NvU32 g_Ap15Mux_Hdcp[];
+extern const NvU32* g_Ap15MuxHdcp[];
+
+extern const NvU32 g_Ap15Mux_Hdmi[];
+extern const NvU32* g_Ap15MuxHdmi[];
+
+extern const NvU32 g_Ap15Mux_Mio[];
+extern const NvU32* g_Ap15MuxMio[];
+
+extern const NvU32 g_Ap15Mux_Slink[];
+extern const NvU32* g_Ap15MuxSlink[];
+
+extern const NvU32 g_Ap15Mux_Vi[];
+extern const NvU32* g_Ap15MuxVi[];
+
+extern const NvU32 g_Ap15Mux_Crt[];
+extern const NvU32* g_Ap15MuxCrt[];
+
+extern const NvU32 g_Ap15Mux_Display1[];
+extern const NvU32 g_Ap15Mux_Display2[];
+extern const NvU32* g_Ap15MuxDisplay[];
+
+extern const NvU32 g_Ap15Mux_Cdev1[];
+
+extern const NvU32 g_Ap15Mux_Cdev2[];
+extern const NvU32 g_Ap15Mux_Csus[];
+extern const NvU32* g_Ap15MuxCdev[];
+
+extern const NvU32 g_Ap15Mux_BacklightDisplay1Pwm0[];
+extern const NvU32 g_Ap15Mux_BacklightDisplay1Pwm1[];
+extern const NvU32 g_Ap15Mux_BacklightDisplay2Pwm0[];
+extern const NvU32 g_Ap15Mux_BacklightDisplay2Pwm1[];
+extern const NvU32* g_Ap15MuxBacklight[];
+
+static const NvU32 g_Ap16Mux_Ulpi[] = {
+    CONFIGEND(), // no pad groups reset to ULPI, so nothing to disown for reset config
+    CONFIG(B,A,UAA,ULPI), CONFIG(B,A,UAB,ULPI), CONFIG(B,A,UAC,ULPI), CONFIGEND(),
+    MODULEDONE()
+};
+static const NvU32* g_Ap16MuxUlpi[] = {
+    &g_Ap16Mux_Ulpi[0],
+    NULL
+};
+/*  Array of all the controller types in the system, pointing to the array of
+ *  instances of each controller.  Indexed using the NvRmIoModule value.
+ */
+static const NvU32** g_Ap16MuxControllers[] = {
+    &g_Ap15MuxAta[0],
+    &g_Ap15MuxCrt[0],
+    NULL, // no options for CSI
+    &g_Ap15MuxDap[0],
+    &g_Ap15MuxDisplay[0],
+    NULL, // no options for DSI
+    NULL, // no options for GPIO
+    &g_Ap15MuxHdcp[0],
+    &g_Ap15MuxHdmi[0],
+    &g_Ap15MuxHsi[0],
+    &g_Ap15MuxMmc[0],
+    NULL, // no options for I2S
+    &g_Ap15MuxI2c[0],
+    &g_Ap15MuxI2cPmu[0],
+    &g_Ap15MuxKbc[0],
+    &g_Ap15MuxMio[0],
+    &g_Ap15MuxNand[0],
+    &g_Ap15MuxPwm[0],
+    &g_Ap15MuxSdio[0],
+    &g_Ap15MuxSflash[0],
+    &g_Ap15MuxSlink[0],
+    &g_Ap15MuxSpdif[0],
+    &g_Ap15MuxSpi[0],
+    &g_Ap15MuxTwc[0],
+    NULL, //  no options for TVO
+    &g_Ap16MuxUart[0],
+    NULL, //  no options for USB
+    NULL, //  no options for VDD
+    &g_Ap15MuxVi[0],
+    NULL, //  no options for XIO
+    &g_Ap15MuxCdev[0],
+    &g_Ap16MuxUlpi[0],
+    NULL,
+    NULL,
+    NULL,
+    NULL,
+    NULL, //  no options for TSENSor
+    &g_Ap15MuxBacklight[0],
+};
+
+NV_CT_ASSERT(NV_ARRAY_SIZE(g_Ap16MuxControllers)==NvOdmIoModule_Num);
+
+const NvU32***
+NvRmAp16GetPinMuxConfigs(NvRmDeviceHandle hDevice)
+{
+    NV_ASSERT(hDevice);
+    return (const NvU32***) g_Ap16MuxControllers;
+}
+
+NvBool NvRmPrivAp16RmModuleToOdmModule(
+    NvRmModuleID RmModule,
+    NvOdmIoModule *OdmModule,
+    NvU32 *OdmInstance,
+    NvU32 *pCnt)
+{
+    NvRmModuleID Module = NVRM_MODULE_ID_MODULE(RmModule);
+    NvU32 Instance = NVRM_MODULE_ID_INSTANCE(RmModule);
+
+    *OdmInstance = Instance;
+
+    switch (Module)
+    {
+    case NvRmModuleID_Usb2Otg:
+        if (Instance == 0)
+        {
+            *OdmModule = NvOdmIoModule_Usb;
+            *OdmInstance = 0;
+        }
+        else
+        {
+            // stop here for instance otherthan one
+            NV_ASSERT(Instance == 1);
+            *OdmModule = NvOdmIoModule_Ulpi;
+            *OdmInstance = 0;
+        }
+        *pCnt = 1;
+        return NV_TRUE;
+    default:
+        break;
+    }
+
+    return NvRmPrivAp15RmModuleToOdmModule(RmModule,
+               OdmModule, OdmInstance, pCnt);
+}
+
+
+NvError
+NvRmPrivAp16GetModuleInterfaceCaps(
+    NvOdmIoModule Module,
+    NvU32 Instance,
+    NvU32 PinMap,
+    void *pCaps)
+{
+    switch (Module)
+    {
+        case NvOdmIoModule_Uart:
+            if (Instance == 0)
+            {
+                if (PinMap == NvOdmUartPinMap_Config1)
+                    ((NvRmModuleUartInterfaceCaps *)pCaps)->NumberOfInterfaceLines = 8;
+                else if (PinMap == NvOdmUartPinMap_Config3)
+                    ((NvRmModuleUartInterfaceCaps *)pCaps)->NumberOfInterfaceLines = 7;
+                else if ((PinMap == NvOdmUartPinMap_Config2) || (PinMap == NvOdmUartPinMap_Config4))
+                    ((NvRmModuleUartInterfaceCaps *)pCaps)->NumberOfInterfaceLines = 4;
+                else if ((PinMap == NvOdmUartPinMap_Config5) || (PinMap == NvOdmUartPinMap_Config6))
+                    ((NvRmModuleUartInterfaceCaps *)pCaps)->NumberOfInterfaceLines = 2;
+                else
+                    ((NvRmModuleUartInterfaceCaps *)pCaps)->NumberOfInterfaceLines = 0;
+            }
+            else if (Instance == 1)
+            {
+                if (PinMap == NvOdmUartPinMap_Config1)
+                    ((NvRmModuleUartInterfaceCaps *)pCaps)->NumberOfInterfaceLines = 4;
+                else if (PinMap == NvOdmUartPinMap_Config2)
+                    ((NvRmModuleUartInterfaceCaps *)pCaps)->NumberOfInterfaceLines = 2;
+                else
+                    ((NvRmModuleUartInterfaceCaps *)pCaps)->NumberOfInterfaceLines = 0;
+            }
+            else if (Instance == 2)
+            {
+                if (PinMap == NvOdmUartPinMap_Config1)
+                    ((NvRmModuleUartInterfaceCaps *)pCaps)->NumberOfInterfaceLines = 4;
+                else if (PinMap == NvOdmUartPinMap_Config2)
+                    ((NvRmModuleUartInterfaceCaps *)pCaps)->NumberOfInterfaceLines = 2;
+                else
+                    ((NvRmModuleUartInterfaceCaps *)pCaps)->NumberOfInterfaceLines = 0;
+            }
+            else
+            {
+                NV_ASSERT(NV_FALSE);
+                return NvError_NotSupported;
+            }
+            return NvSuccess;
+
+        default:
+            break;
+    }
+    return NvRmPrivAp15GetModuleInterfaceCaps(Module, Instance, PinMap, pCaps);
+}
+
diff --git a/arch/arm/mach-tegra/nvrm/core/ap15/ap16rm_reloctable.c b/arch/arm/mach-tegra/nvrm/core/ap15/ap16rm_reloctable.c
new file mode 100644
index 000000000000..99a689921161
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/core/ap15/ap16rm_reloctable.c
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2008-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include "nvcommon.h"
+#include "nvos.h"
+#include "nvrm_init.h"
+#include "common/nvrm_hwintf.h"
+#include "ap16/project_relocation_table.h"
+#include "ap15rm_private.h"
+
+static NvU32 s_RelocationTable[] =
+{
+    NV_RELOCATION_TABLE_INIT
+};
+
+NvU32 *
+NvRmPrivAp16GetRelocationTable( NvRmDeviceHandle hDevice )
+{
+    return s_RelocationTable;
+}
+
diff --git a/arch/arm/mach-tegra/nvrm/core/ap15/nvrm_clocks.c b/arch/arm/mach-tegra/nvrm/core/ap15/nvrm_clocks.c
new file mode 100644
index 000000000000..40e8837f9e11
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/core/ap15/nvrm_clocks.c
@@ -0,0 +1,3311 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/**
+ * @file
+ * @brief <b>nVIDIA Driver Development Kit:
+ *           Clock Resource manager </b>
+ *
+ * @b Description: Implements Clock control API. All code in this file chip
+ * independent. All chip dependent code should move to ap15rm_clocks.c file.
+ */
+
+#include "nvrm_clocks.h"
+#include "nvassert.h"
+#include "nvrm_drf.h"
+#include "nvrm_chiplib.h"
+#include "nvrm_hwintf.h"
+#include "ap15rm_private.h"
+#include "ap15rm_clocks.h"
+#include "ap20/ap20rm_clocks.h"
+#include "nvrm_pmu_private.h"
+#include "nvrm_pinmux_utils.h"
+#include "nvodm_query_pinmux.h"
+#include "nvodm_query_discovery.h"
+
+// Module debug: 0=disable, 1=enable
+#define NVRM_ENABLE_PRINTF (0)
+
+#if (NV_DEBUG && NVRM_ENABLE_PRINTF)
+#define NVRM_POWER_PRINTF(x)   NvOsDebugPrintf x
+#else
+#define NVRM_POWER_PRINTF(x)
+#endif
+
+// TODO: Replace NvOsWaitUS() with NvRmPrivWaitUS()
+// TODO: CAR access macro
+
+// Actual FPGA clock frequency for all modules is 8.33MHz
+// (display is exception)
+#define FPGA_MODULE_KHZ_AP15 (8330)
+#define FPGA_MODULE_KHZ_AP20 (13000)
+#define FPGA_DISPLAY_KHZ (27000)
+
+// QT clock frequency used as a special value (actual frequency is irrelevant)
+#define QT_MODULE_KHZ (1)
+
+// UART rate divider is part of the UART module and it is not discribed
+// in central module clock information table. Hence, need this define.
+#define NVRM_UART_TIMING_DIVISOR_MAX (0xFFFFUL)
+
+/*****************************************************************************/
+
+// Clock source descriptors and frequencies
+static NvRmClockSourceInfo* s_ClockSourceTable = NULL;
+static NvU32 s_ClockSourceFreq[NvRmClockSource_Num];
+static NvRmSystemBusComplexInfo s_SystemBusComplex = {0};
+
+// Module clocks frequency limits
+static const NvRmModuleClockLimits* s_ModuleClockLimits;
+
+// Module clocks descriptors and module clock state arrays of the same size
+static const NvRmModuleClockInfo *s_moduleClockTable;
+static NvU32 s_moduleClockTableSize;
+static NvRmModuleClockState *s_moduleClockState = NULL;
+
+// PLL references
+static NvRmPllReference* s_PllReferencesTable;
+static NvU32 s_PllReferencesTableSize;
+static NvBool s_MipiPllVddOn = NV_FALSE;
+
+// Mutex for thread-safe access to clock control records and h/w
+static NvOsSpinMutexHandle s_hClockMutex = NULL;
+
+// Mutex for thread-safe access to shared PLLs
+static NvOsMutexHandle s_hPllMutex = NULL;
+
+/*****************************************************************************/
+
+NvError
+NvRmPrivGetClockState(
+    NvRmDeviceHandle hDevice,
+    NvRmModuleID ModuleId,
+    NvRmModuleClockInfo** CinfoOut,
+    NvRmModuleClockState** StateOut)
+{
+    NvRmModuleInstance* inst;
+
+    NV_ASSERT( hDevice );
+    NV_ASSERT(s_moduleClockState);
+
+    if (NvRmPrivGetModuleInstance(hDevice, ModuleId, &inst) != NvSuccess)
+    {
+        return NvError_ModuleNotPresent;
+    }
+    if (inst->ModuleData)
+    {
+        *CinfoOut = (NvRmModuleClockInfo*)inst->ModuleData;
+        *StateOut = &s_moduleClockState[(*CinfoOut) - s_moduleClockTable];
+        return NvSuccess;
+    }
+    else
+    {
+        // Starting with AP20 no dedicated HSMMC clock (mapped to SDMMC)
+        if ((ModuleId == NvRmModuleID_Hsmmc) &&
+            (hDevice->ChipId.Id != 0x15) && (hDevice->ChipId.Id != 0x16))
+        {
+            return NvError_ModuleNotPresent;
+        }
+        NV_ASSERT(!"module clock info missing --"
+                   " fillup the [apxx]rm_clocks_info.c file");
+        return NvError_NotSupported;
+    }
+}
+
+/*****************************************************************************/
+
+static void
+NvRmPrivPllDPowerControl(
+    NvRmDeviceHandle hDevice,
+    NvBool ConfigEntry,
+    NvBool* pMipiPllVddOn)
+{
+    NvRmPrivAp15PllDPowerControl(hDevice, ConfigEntry, pMipiPllVddOn);
+}
+
+static void
+NvRmPrivDisablePLLs(
+    NvRmDeviceHandle hDevice,
+    const NvRmModuleClockInfo* cinfo,
+    const NvRmModuleClockState* state)
+{
+    NvRmPrivAp15DisablePLLs(hDevice, cinfo, state);
+}
+
+static NvRmClockSource
+NvRmPrivGetImplicitPllSource(
+    NvRmDeviceHandle hRmDevice,
+    NvRmModuleID Module)
+{
+    switch (Module)
+    {
+        // DSI, CSI, I2C and UART modules are implicitely attached to PLLP3
+        // output derived from primary PLLP0.
+        case NvRmModuleID_Dsi:
+        case NvRmModuleID_Csi:
+        case NvRmModuleID_I2c:
+        case NvRmModuleID_Uart:
+            return NvRmClockSource_PllP0;
+
+        // MPE depends on PLLA for audio in AP15/16
+        case NvRmModuleID_Mpe:
+            if ((hRmDevice->ChipId.Id == 0x15) || (hRmDevice->ChipId.Id == 0x16))
+                return NvRmClockSource_PllA0;
+        // fall through
+
+        // No implicit dependencies for other modules
+        default:
+            return NvRmClockSource_Invalid;
+    }
+}
+
+static void
+NvRmPrivModuleClockAttach(
+    NvRmDeviceHandle hDevice,
+    const NvRmModuleClockInfo* cinfo,
+    const NvRmModuleClockState* state,
+    NvBool Enable)
+{
+    NvU32 i, reg;
+    NvBool Enabled;
+    NvRmClockSource SubSourceId = NvRmClockSource_Invalid;
+    NvRmClockSource SourceId = cinfo->Sources[state->SourceClock];
+
+    if ((cinfo->Module == NvRmModuleID_Spdif) ||
+        (cinfo->Module == NvRmModuleID_Vi) ||
+        (cinfo->Module == NvRmModuleID_Tvo))
+    {
+        // Find secondary source for modules with explicit subclocks; subclock
+        // descriptor and state are located after main ones, respectively
+        SubSourceId = (cinfo + 1)->Sources[(state + 1)->SourceClock];
+    }
+    else
+    {
+        // Find implicit secondary source (if any) for other modules
+        SubSourceId = NvRmPrivGetImplicitPllSource(hDevice, cinfo->Module);
+
+    }
+
+    NV_ASSERT(cinfo->ClkEnableOffset);
+    reg = NV_REGR(hDevice, NvRmPrivModuleID_ClockAndReset, 0, 
+                  cinfo->ClkEnableOffset);
+    Enabled = ((reg & cinfo->ClkEnableField) == cinfo->ClkEnableField);
+    if (Enabled == Enable)
+        return; // Exit if no changes in clock status
+
+    for (i = 0; i < s_PllReferencesTableSize; i++)
+    {
+        // If module clock is to be enabled - attach sources (inc ref count)
+        // If module clock is to be disabled - detach sources (dec ref count)
+        if (s_PllReferencesTable[i].SourceId == SourceId)
+            NvRmPrivPllRefUpdate(hDevice, &s_PllReferencesTable[i], Enable);
+        if (s_PllReferencesTable[i].SourceId == SubSourceId)
+            NvRmPrivPllRefUpdate(hDevice, &s_PllReferencesTable[i], Enable);
+    }
+}
+
+void
+NvRmPrivModuleClockReAttach(
+    NvRmDeviceHandle hDevice,
+    const NvRmModuleClockInfo* cinfo,
+    const NvRmModuleClockState* state)
+{
+    NvU32 i, reg;
+    NvRmClockSource SourceId = cinfo->Sources[state->SourceClock];
+
+    for (i = 0; i < s_PllReferencesTableSize; i++)
+    {
+        NvBool* pAttached =
+         &s_PllReferencesTable[i].AttachedModules[cinfo - s_moduleClockTable];
+        NvBool WasAttached = *pAttached;
+        NvBool IsAttached = (s_PllReferencesTable[i].SourceId == SourceId);
+
+        if (WasAttached != IsAttached)
+        {
+            // Changes in source reference always recorded but affect
+            // ref count only when the module clock is enabled
+            if(cinfo->ClkEnableOffset != 0)
+            {
+                reg = NV_REGR(hDevice, NvRmPrivModuleID_ClockAndReset, 0,
+                              cinfo->ClkEnableOffset);
+                if ((reg & cinfo->ClkEnableField) == cinfo->ClkEnableField)
+                {
+                    NvRmPrivPllRefUpdate(
+                        hDevice, &s_PllReferencesTable[i], IsAttached);
+                }
+            }
+            *pAttached = IsAttached;
+        }
+    }
+}
+
+static void
+NvRmPrivCoreClockReAttach(
+    NvRmDeviceHandle hDevice,
+    NvRmClockSource CoreId,
+    NvRmClockSource SourceId)
+{
+    static NvU32 s_CpuModuleIndex = (NvU32)-1;
+    static NvU32 s_AvpModuleIndex = (NvU32)-1;
+
+    NvU32 i, ModuleIndex;
+
+    // Map core bus clock to processor module. CPU, AVP are not in relocation
+    // table, can not use module instance shortcut - search clock descriptors.
+    if (CoreId == NvRmClockSource_CpuBus)
+    {
+        if (s_CpuModuleIndex == (NvU32)-1)
+        {
+            for (i = 0; i < s_moduleClockTableSize; i++)
+            {
+                if (s_moduleClockTable[i].Module == NvRmModuleID_Cpu)
+                    break;
+            }
+            s_CpuModuleIndex = i;
+        }
+        NV_ASSERT(s_CpuModuleIndex < s_moduleClockTableSize);
+        ModuleIndex = s_CpuModuleIndex;
+    }
+    else if (CoreId == NvRmClockSource_SystemBus)
+    {
+        if (s_AvpModuleIndex == (NvU32)-1)
+        {
+            for (i = 0; i < s_moduleClockTableSize; i++)
+            {
+                if (s_moduleClockTable[i].Module == NvRmModuleID_Avp)
+                    break;
+            }
+            s_AvpModuleIndex = i;
+        }
+        NV_ASSERT(s_AvpModuleIndex < s_moduleClockTableSize);
+        ModuleIndex = s_AvpModuleIndex;
+    }
+    else
+    {
+        NV_ASSERT(!"Invalid core id");
+        return;
+    }
+
+    // Map secondary divided PLL outputs to primary PLLs
+    switch (SourceId)
+    {
+        case NvRmClockSource_PllC1:
+            SourceId = NvRmClockSource_PllC0;
+            break;
+        case NvRmClockSource_PllM1:
+            SourceId = NvRmClockSource_PllM0;
+            break;
+        case NvRmClockSource_PllP1:
+        case NvRmClockSource_PllP2:
+        case NvRmClockSource_PllP3:
+        case NvRmClockSource_PllP4:
+            SourceId = NvRmClockSource_PllP0;
+            break;
+        default:
+            break;
+    }
+
+    // Record changes in PLL references and update ref count
+    for (i = 0; i < s_PllReferencesTableSize; i++)
+    {
+        NvBool* pAttached =
+         &s_PllReferencesTable[i].AttachedModules[ModuleIndex];
+        NvBool WasAttached = *pAttached;
+        NvBool IsAttached = (s_PllReferencesTable[i].SourceId == SourceId);
+
+        if (WasAttached != IsAttached)
+        {
+            *pAttached = IsAttached;
+            NvRmPrivPllRefUpdate(hDevice, &s_PllReferencesTable[i], IsAttached);
+        }
+    }
+}
+
+void
+NvRmPrivMemoryClockReAttach(
+    NvRmDeviceHandle hDevice,
+    const NvRmModuleClockInfo* cinfo,
+    const NvRmModuleClockState* state)
+{
+    NvU32 i;
+    NvRmClockSource SourceId = cinfo->Sources[state->SourceClock];
+
+    // MC clock on AP20 and newer chips is always the same as EMC1x domain clock
+    // So there is no need for source reference double-counting.
+    if ((hDevice->ChipId.Id >= 0x20) &&
+        (cinfo->Module == NvRmPrivModuleID_MemoryController))
+        return;
+
+    for (i = 0; i < s_PllReferencesTableSize; i++)
+    {
+        NvBool* pAttached =
+         &s_PllReferencesTable[i].AttachedModules[cinfo - s_moduleClockTable];
+        NvBool WasAttached = *pAttached;
+        NvBool IsAttached = (s_PllReferencesTable[i].SourceId == SourceId);
+
+        // Record changes in PLL references and update ref count.
+        // TODO: secondary PLL outputs mapping (only primary PLLs are used now)
+        if (WasAttached != IsAttached)
+        {
+            *pAttached = IsAttached;
+            NvRmPrivPllRefUpdate(hDevice, &s_PllReferencesTable[i], IsAttached);
+        }
+    }
+}
+
+void
+NvRmPrivExternalClockAttach( 
+    NvRmDeviceHandle hDevice,
+    NvRmClockSource SourceId,
+    NvBool Enable)
+{
+    NvU32 i;
+
+    // Map secondary divided PLL outputs to primary PLLs
+    switch (SourceId)
+    {
+        case NvRmClockSource_PllC1:
+            SourceId = NvRmClockSource_PllC0;
+            break;
+        case NvRmClockSource_PllM1:
+            SourceId = NvRmClockSource_PllM0;
+            break;
+        case NvRmClockSource_PllP1:
+        case NvRmClockSource_PllP2:
+        case NvRmClockSource_PllP3:
+        case NvRmClockSource_PllP4:
+            SourceId = NvRmClockSource_PllP0;
+            break;
+        default:
+            break;
+    }
+
+    // Attach external clock
+    for (i = 0; i < s_PllReferencesTableSize; i++)
+    {
+        if (s_PllReferencesTable[i].SourceId == SourceId)
+        {
+            // If ext clock is enabled - attach source (inc ref count)
+            // If ext clock is disabled - detach source (dec ref count)
+            NvOsSpinMutexLock(s_hClockMutex);
+            s_PllReferencesTable[i].ExternalClockRefCnt += (Enable ? 1 : (-1));
+            NvRmPrivPllRefUpdate(hDevice, &s_PllReferencesTable[i], Enable);
+
+            // Configure clock source if necessary (required for PLLA)
+            if (SourceId == NvRmClockSource_PllA0)
+                NvRmPrivConfigureClockSource(hDevice, NvRmModuleID_I2s, Enable);
+            NvOsSpinMutexUnlock(s_hClockMutex);
+        }
+    }
+}
+
+/*****************************************************************************/
+
+void 
+NvRmPrivEnableModuleClock(
+    NvRmDeviceHandle hRmDevice,
+    NvRmModuleID ModuleId,
+    ModuleClockState ClockState)
+{
+    switch (hRmDevice->ChipId.Id)
+    {
+        case 0x15:
+        case 0x16:
+            Ap15EnableModuleClock(hRmDevice, ModuleId, ClockState); 
+            break;
+        case 0x20:
+            Ap20EnableModuleClock(hRmDevice, ModuleId, ClockState); 
+            break;
+        default:
+            NV_ASSERT(!"Unsupported chip ID");
+    }
+}
+
+NvError NvRmPowerModuleClockControl(
+    NvRmDeviceHandle hDevice,
+    NvRmModuleID ModuleId,
+    NvU32 ClientId,
+    NvBool Enable)
+{
+    NvRmModuleClockInfo *cinfo;
+    NvRmModuleClockState *state;
+    NvRmMilliVolts v = NvRmVoltsUnspecified;
+    NvError err;
+    ModuleClockState ClockState =
+        Enable ? ModuleClockState_Enable : ModuleClockState_Disable;
+    NvRmModuleID ModuleName = NVRM_MODULE_ID_MODULE(ModuleId);
+    // Clock control/configurations shared between drivers and DVFS
+    NvBool SharedModule = ((ModuleName == NvRmModuleID_Display) ||
+                           (ModuleName == NvRmModuleID_Dsi) ||
+                           (ModuleName == NvRmModuleID_Vde));
+
+    if (NvRmPrivIsDiagMode(ModuleId))
+        return NvSuccess;
+
+    // Get pointers to module clock info and current module clock state
+    err = NvRmPrivGetClockState(hDevice, ModuleId, &cinfo, &state);
+    if (err != NvSuccess)
+        return err;
+
+    // Protect access to clocks that shared control (directly, or via PLLs)
+    // with DVFS. Made sure DSI power rail is up if DSI clock is enabled.
+    if (SharedModule)
+    {
+        NvOsMutexLock(s_hPllMutex);
+        if (Enable && (ModuleName == NvRmModuleID_Dsi))
+            NvRmPrivPllDPowerControl(hDevice, NV_TRUE, &s_MipiPllVddOn);
+    }
+    NvOsSpinMutexLock(s_hClockMutex);
+
+    // Check if voltage scaling is required before module clock is enabled.
+    // Core voltage access is shared with DVFS. PMU access transport must
+    // *not* be scalable.
+    if (Enable)
+    {
+        // Preview, don't update scaling ref counts if voltage going up
+        v = NvRmPrivModuleVscaleAttach(
+            hDevice, cinfo, state, Enable, NV_TRUE);
+
+        if ((v != NvRmVoltsUnspecified) &&
+            (v != NvRmVoltsOff))
+        {
+            // Preview reported voltage increase - set target pending to
+            // prevent DVFS scaling down, while lock is released
+            NvRmPrivModuleVscaleSetPending(hDevice, v);
+
+            NvOsSpinMutexUnlock(s_hClockMutex);
+            if (!SharedModule)
+                NvOsMutexLock(s_hPllMutex);
+            NvRmPrivDvsRequest(v);
+            if (!SharedModule)
+                NvOsMutexUnlock(s_hPllMutex);
+            NvOsSpinMutexLock(s_hClockMutex);
+
+            // Now, after voltage is increased - update scaling ref counts
+            // and cancel pending request
+            v = NvRmPrivModuleVscaleAttach(
+                hDevice, cinfo, state, Enable, NV_FALSE);
+            NvRmPrivModuleVscaleSetPending(hDevice, NvRmVoltsOff);
+        }
+    }
+
+    // Restart reference counting if it is the 1st clock control call
+    if (!state->FirstReference)
+    {
+        state->FirstReference = NV_TRUE;
+        state->refCount = 0;
+    }
+
+    // Update reference count, and exit if
+    // - clock enable requested and module clock is already enabled
+    // - clock disable requested, but not all enable requests have been matched
+    if (Enable)
+    {
+        if (state->refCount != 0)
+        {
+            state->refCount++;
+            goto leave; // err = NvSuccess already
+        }
+        state->refCount = 1;
+    }
+    else if (state->refCount != 0)
+    {
+        state->refCount --;
+        if (state->refCount != 0)
+        {
+            goto leave; // err = NvSuccess already
+        }
+    }
+    else
+    {
+        // TODO: assert on disable without enable
+        NvOsDebugPrintf(
+            "Clock control balance failed for module %d, instance %d\n",
+            NVRM_MODULE_ID_MODULE(ModuleId), NVRM_MODULE_ID_INSTANCE(ModuleId));
+        // NV_ASSERT(!"Clock control balance violation");
+    }
+    NvRmPrivModuleClockAttach(hDevice, cinfo, state, Enable);
+    NvRmPrivEnableModuleClock(hDevice, ModuleId, ClockState);
+
+    // Check if voltage can be lowered after module clock is disabled.
+    if (!Enable)
+    {
+        v = NvRmPrivModuleVscaleAttach(
+            hDevice, cinfo, state, Enable, NV_FALSE);
+        if (v == NvRmVoltsOff)
+            NvRmPrivDvsRequest(v);  // No transaction, just set update flag
+    }
+
+    // Common exit
+leave:
+    NvOsSpinMutexUnlock(s_hClockMutex);
+    if (SharedModule)
+    {
+        if (!Enable && (ModuleName == NvRmModuleID_Dsi))
+            NvRmPrivPllDPowerControl(hDevice, NV_FALSE, &s_MipiPllVddOn);
+        NvOsMutexUnlock(s_hPllMutex);
+    }
+    return err;
+}
+
+/*****************************************************************************/
+
+ExecPlatform NvRmPrivGetExecPlatform(NvRmDeviceHandle hRmDeviceHandle)
+{
+    if (hRmDeviceHandle->ChipId.Major != 0)
+    {
+        return ExecPlatform_Soc;
+    }
+    if (NvRmIsSimulation())
+    {
+        return ExecPlatform_Sim;
+    }
+    if (hRmDeviceHandle->ChipId.Minor != 0)
+    {
+        return ExecPlatform_Fpga;
+    }
+    return ExecPlatform_Qt;
+}
+
+/*****************************************************************************/
+
+/* Sets module clock source/divider register */
+void NvRmPrivModuleClockSet(
+    NvRmDeviceHandle hDevice,
+    const NvRmModuleClockInfo* cinfo,
+    const NvRmModuleClockState* state)
+{
+    NvU32 reg, divisor;
+
+    NV_ASSERT(cinfo->ClkSourceOffset);
+    reg = NV_REGR(hDevice, NvRmPrivModuleID_ClockAndReset, 0, cinfo->ClkSourceOffset);
+    divisor = (reg >> cinfo->DivisorFieldShift) & cinfo->DivisorFieldMask;
+    if ((cinfo->Divider  != NvRmClockDivider_None) &&
+        (state->Divider > divisor))
+    {
+        // Switch divider 1st, source 2nd, if new divisor is bigger
+        NV_ASSERT(state->Divider <= cinfo->DivisorFieldMask);
+        reg &= ~(cinfo->DivisorFieldMask << cinfo->DivisorFieldShift);
+        reg |= state->Divider << cinfo->DivisorFieldShift;
+        NV_REGW(hDevice, NvRmPrivModuleID_ClockAndReset, 0, cinfo->ClkSourceOffset, reg);
+        NvOsWaitUS(NVRM_CLOCK_CHANGE_DELAY);
+    }
+
+    NV_ASSERT(state->SourceClock <= cinfo->SourceFieldMask);
+    reg &= (~(cinfo->SourceFieldMask << cinfo->SourceFieldShift));
+    reg |= ( state->SourceClock << cinfo->SourceFieldShift);
+    NV_REGW(hDevice, NvRmPrivModuleID_ClockAndReset, 0, cinfo->ClkSourceOffset, reg);
+    NvOsWaitUS(NVRM_CLOCK_CHANGE_DELAY);
+
+    if ((cinfo->Divider  != NvRmClockDivider_None) &&
+        (state->Divider < divisor))
+    {
+        // Switch source 1st, divider 2nd, if new divisor is smaller
+        reg &= ~(cinfo->DivisorFieldMask << cinfo->DivisorFieldShift);
+        reg |= state->Divider << cinfo->DivisorFieldShift;
+        NV_REGW(hDevice, NvRmPrivModuleID_ClockAndReset, 0, cinfo->ClkSourceOffset, reg);
+        NvOsWaitUS(NVRM_CLOCK_CHANGE_DELAY);
+    }
+}
+
+static NvRmFreqKHz
+NvRmPrivGetEmcSyncFreq(
+    NvRmDeviceHandle hDevice,
+    NvRmModuleID Module)
+{
+    switch (hDevice->ChipId.Id)
+    {
+        case 0x15:
+        case 0x16:
+            return NvRmPrivAp15GetEmcSyncFreq(hDevice, Module);
+        case 0x20:
+            return NvRmPrivAp20GetEmcSyncFreq(hDevice, Module);
+        default:
+            NV_ASSERT(!"Unsupported chip ID");
+            return NvRmFreqMaximum;
+    }
+}
+
+static NvBool
+NvRmPrivIsModuleClockException(
+    NvRmDeviceHandle hDevice,
+    NvRmModuleClockInfo *cinfo,
+    NvU32 clockSourceCount,
+    NvU32 MinFreq,
+    NvU32 MaxFreq,
+    const NvRmFreqKHz* PrefFreqList,
+    NvU32 PrefCount,
+    NvRmModuleClockState *state,
+    NvU32 flags)
+{
+    return NvRmPrivAp15IsModuleClockException(
+        hDevice, cinfo, clockSourceCount, MinFreq, MaxFreq,
+        PrefFreqList, PrefCount, state, flags);
+}
+
+/* Returns the best source clock and the best divider */
+static NvError NvRmFindBestClockSource(
+    NvRmDeviceHandle hDevice,
+    NvRmModuleClockInfo *cinfo,
+    NvU32 clockSourceCount,
+    NvU32 MinFreq,
+    NvU32 MaxFreq,
+    const NvRmFreqKHz* PrefFreqList,
+    NvU32 PrefCount,
+    NvRmModuleClockState *state,
+    NvU32 flags)
+{
+    NvU32 bestdiff = 0x7FFFFFFF;
+    NvU32 bestdiv = 0x0;
+    NvU32 SourceClock = (NvU32)-1;
+    NvU32 SourceClockFreq = 0;
+    NvU32 i = 0,j = 0;
+    NvRmFreqKHz freq = 0, ReachedFreq = 0;
+    NvU32 temp = 0, div = 0, mantissa = 0;
+    NvS32 diff = 0;
+
+    NV_ASSERT((MinFreq != 0) && (MinFreq <= MaxFreq));
+
+    // Check if exceptional handling is required this module clock, and exit
+    // if it is completed
+    if (NvRmPrivIsModuleClockException(hDevice, cinfo, clockSourceCount,
+          MinFreq, MaxFreq, PrefFreqList, PrefCount, state, flags))
+        return NvSuccess;
+
+    for (j=0; j< PrefCount; j++)        // loop through target frequencies
+    {
+        freq = (PrefFreqList[j] == NvRmFreqMaximum) ? MaxFreq : PrefFreqList[j];
+        if (flags & NvRmClockConfig_QuietOverClock)
+            freq = (PrefFreqList[j] > MaxFreq) ? MaxFreq : PrefFreqList[j];
+        if ((freq < MinFreq) || (freq > MaxFreq))
+            continue;
+
+        for (i=0; i< clockSourceCount; i++) // loop through avilable sources
+        {
+            NV_ASSERT(cinfo->Sources[i] < NvRmClockSource_Num);
+            if (cinfo->Sources[i] == NvRmClockSource_Invalid)
+                break;
+
+            SourceClockFreq = s_ClockSourceFreq[(cinfo->Sources[i])];
+            if (SourceClockFreq < MinFreq)
+                continue;
+            if (NvRmPrivIsSourceProtected(
+                hDevice, cinfo->Module, cinfo->Sources[i]))
+                continue;
+
+            if ((cinfo->Divider == NvRmClockDivider_None) ||
+                (SourceClockFreq <= freq))
+            {
+                div = 1;
+                if (cinfo->Module == NvRmModuleID_Uart)
+                {
+                    // If target is not reachable from the source by integer
+                    // division - reject the source
+                    if (!NvRmIsFreqRangeReachable(SourceClockFreq,
+                            MinFreq, MaxFreq, NVRM_UART_TIMING_DIVISOR_MAX))
+                        continue;
+                }
+                else if (SourceClockFreq > MaxFreq)
+                    continue;
+            }
+            else    // Divider, SourceClockFreq > freq
+            {
+                // Default integer divider: Freq = SourceClockFreq / div
+                // where div = h/w divisor field
+                NvU32 MaxDivisor = cinfo->DivisorFieldMask;
+                NV_ASSERT(MaxDivisor);
+
+                if (cinfo->Divider == NvRmClockDivider_Integer_1)
+                {
+                    // Integer divider: Freq = SourceClockFreq / div
+                    // where div = h/w divisor field + 1
+                    MaxDivisor += 1;
+                }
+                else if (cinfo->Divider == NvRmClockDivider_Fractional_2)
+                {
+                    // Fractional divider: Freq = (SourceClockFreq * 2) / div
+                    // where div = h/w divisor field + 2
+                    SourceClockFreq = (SourceClockFreq << 1);
+                    MaxDivisor += 2;
+                }
+
+                // Find divisor floor / freq ceiling, and
+                // the 1st bit of the fractional part
+                temp = (SourceClockFreq << 1) / freq;
+                div = temp >> 1;
+                mantissa = temp & 0x01;
+
+                // Check if divisor value fits divisor field
+                if (div >= MaxDivisor)
+                {
+                    div = MaxDivisor;
+                    if (SourceClockFreq > div * (NvU64)MaxFreq)
+                        continue;   // max boundary violation at max divisor
+                }
+                else if (SourceClockFreq > div * (NvU64)MaxFreq)
+                {
+                    div += 1; // divisor ceiling / freq floor
+                    if (SourceClockFreq < div * (NvU64)MinFreq)
+                        continue;   // both max and min boundaries violation
+                }
+                else if (mantissa)
+                {
+                    div += 1; // divisor ceiling / freq floor
+                    if (SourceClockFreq < div * (NvU64)MinFreq)
+                        div -= 1; // fall back to divisor floor / freq ceiling
+                }
+            }
+            // Check if new traget frequency approximation is the best, so far
+            ReachedFreq = SourceClockFreq / div;
+            diff = freq - ReachedFreq;
+            if (diff < 0)
+                diff *= -1;
+            if ( ((NvU32) diff < bestdiff) ||
+                 (((NvU32) diff == bestdiff) && (div < bestdiv)) )
+            {
+                SourceClock = i;
+                bestdiv = div;
+                bestdiff = (NvU32)diff;
+            }
+        }
+        // stop searching if "perfect" match found
+        if (!bestdiff)
+            break;
+    }
+
+    if ((bestdiv == 0) || (SourceClock == (NvU32) -1))
+    {
+        NV_ASSERT(!"No clock source found for this panel");
+        return NvError_NotSupported;
+    }
+
+    // Fill in clock state taking into account different types of dividers
+    state->Divider = bestdiv;
+    state->SourceClock = SourceClock;
+    SourceClockFreq = s_ClockSourceFreq[cinfo->Sources[SourceClock]];
+
+    if (cinfo->Divider == NvRmClockDivider_Integer_1)
+    {
+        state->Divider = bestdiv - 1;
+    }
+    else if (cinfo->Divider == NvRmClockDivider_Fractional_2)
+    {
+        if (bestdiv == 1)
+            bestdiv = 2; // cast pass thru case into generic formula
+        state->Divider = (bestdiv - 2);
+        SourceClockFreq = (SourceClockFreq << 1);
+    }
+
+    state->actual_freq = SourceClockFreq / bestdiv;
+
+    return NvSuccess;
+}
+
+/*****************************************************************************/
+
+static void RmReset2D(NvRmDeviceHandle hRmDevice)
+{
+    switch (hRmDevice->ChipId.Id)
+    {
+        case 0x15:
+        case 0x16:
+            NvRmPrivAp15Reset2D(hRmDevice);
+            return;
+        case 0x20:
+            NvRmPrivAp20Reset2D(hRmDevice);
+            return;
+        default:
+            NV_ASSERT(!"Unsupported chip ID");
+            return;
+    }
+}
+
+static void ScaledClockConfigInit(NvRmDeviceHandle hRmDevice)
+{
+    if (NvRmPrivGetExecPlatform(hRmDevice) != ExecPlatform_Soc)
+        return;     // Initialize scaled clock configuration only on SoC
+
+    switch (hRmDevice->ChipId.Id)
+    {
+        case 0x15:
+        case 0x16:
+            NvRmPrivAp15EmcConfigInit(hRmDevice);
+            return;
+        case 0x20:
+            NvRmPrivAp20ScaledClockConfigInit(hRmDevice);
+            return;
+        default:
+            NV_ASSERT(!"Unsupported chip ID");
+            return;
+    }
+}
+
+static void ModuleClockStateInit(NvRmDeviceHandle hRmDevice)
+{
+    NvError e;
+    NvU32 i, j, flags, reg;
+    NvRmModuleID ModuleId;
+    NvRmClockSource ImplicitPll;
+    const NvRmModuleClockInfo* cinfo;
+    NvRmModuleClockState *state;
+
+    for (i = 0; i < s_moduleClockTableSize; i++)
+    {
+        flags = 0;
+        ImplicitPll = NvRmClockSource_Invalid;
+        cinfo = &s_moduleClockTable[i];
+        state = &s_moduleClockState[i];
+        ModuleId = NVRM_MODULE_ID(cinfo->Module, cinfo->Instance);
+
+        if (cinfo->SubClockId)
+        {
+            // Check module subclock configuration
+            if ((cinfo->Module == NvRmModuleID_Spdif) ||
+                (cinfo->Module == NvRmModuleID_Vi) ||
+                (cinfo->Module == NvRmModuleID_Tvo))
+                flags = NvRmClockConfig_SubConfig;
+        }
+        else
+        {
+            // Check implicit attachment to PLLs for main clocks only
+            ImplicitPll =
+                NvRmPrivGetImplicitPllSource(hRmDevice, cinfo->Module);
+            NV_ASSERT((ImplicitPll == NvRmClockSource_Invalid) ||
+                      (cinfo->ClkEnableOffset));
+        }
+
+        // Fill in module clock state, attach explicit PLL sources for clocks
+        // and subclocks. Special cases: CPU and AVP are not in the relocation
+        // table, and attached to PLL via CPU and System bus, respectively
+        e = NvRmPowerModuleClockConfig(
+            hRmDevice, ModuleId, 0, 0, 0, NULL, 0, NULL, flags);
+        NV_ASSERT((e == NvSuccess) || (e == NvError_ModuleNotPresent));
+        if (e == NvSuccess)
+        {
+            NvRmMilliVolts v;   // can be ignored as we always boot at max V
+            NvRmFreqKHz SourceClockFreq =
+                s_ClockSourceFreq[(cinfo->Sources[state->SourceClock])];
+            NvRmPrivModuleSetScalingAttribute(hRmDevice, cinfo, state);
+            v = NvRmPrivModuleVscaleReAttach(hRmDevice,
+                cinfo, state, state->actual_freq, SourceClockFreq, NV_FALSE);
+            (void)v;
+        }
+        else if ((cinfo->Module == NvRmModuleID_Cpu) ||
+                 (cinfo->Module == NvRmModuleID_Avp))
+        {
+            const NvRmCoreClockInfo* pCore =
+                NvRmPrivGetClockSourceHandle(cinfo->Sources[0])->pInfo.pCore;
+            NvRmClockSource SourceId = 
+                NvRmPrivCoreClockSourceGet(hRmDevice, pCore);
+            NvRmPrivCoreClockReAttach(hRmDevice, pCore->SourceId, SourceId);
+        }
+
+        // Attach implicit PLL sources and update reference count
+        // for enabled main clocks
+        if (flags == NvRmClockConfig_SubConfig)
+            continue;
+
+        if (cinfo->ClkEnableOffset)
+        {
+            reg = NV_REGR(hRmDevice, NvRmPrivModuleID_ClockAndReset, 0,
+                cinfo->ClkEnableOffset);
+            if ((reg & cinfo->ClkEnableField) == cinfo->ClkEnableField)
+            {
+                for (j = 0; j < s_PllReferencesTableSize; j++)
+                {
+                    if (s_PllReferencesTable[j].SourceId == ImplicitPll)
+                        NvRmPrivPllRefUpdate(
+                            hRmDevice, &s_PllReferencesTable[j], NV_TRUE);
+                }
+                state->refCount = 1;
+            }
+        }
+        else
+            state->refCount = 1;    // free running clock
+    }
+}
+
+NvError
+NvRmPrivClocksInit(NvRmDeviceHandle hRmDevice)
+{
+    NvRmModuleID ModuleId;
+    NvU32 i = 0;
+    NvU32 fpgaModuleFreq = 0;
+    ExecPlatform env;
+    NvError e;
+
+    NV_ASSERT(hRmDevice);
+    env = NvRmPrivGetExecPlatform(hRmDevice);
+
+    NV_CHECK_ERROR_CLEANUP(NvOsSpinMutexCreate(&s_hClockMutex));
+    NV_CHECK_ERROR_CLEANUP(NvOsMutexCreate(&s_hPllMutex));
+
+    /*
+     * Clock tree descriptors and reference tables initialization
+     */
+    if ((hRmDevice->ChipId.Id == 0x15) || (hRmDevice->ChipId.Id == 0x16))
+    {
+        s_moduleClockTable = g_Ap15ModuleClockTable;
+        s_moduleClockTableSize = g_Ap15ModuleClockTableSize;
+        NvRmPrivAp15PllReferenceTableInit(&s_PllReferencesTable, 
+                &s_PllReferencesTableSize);
+        s_ClockSourceTable = NvRmPrivAp15ClockSourceTableInit();
+        fpgaModuleFreq = FPGA_MODULE_KHZ_AP15;
+    }
+    else if (hRmDevice->ChipId.Id == 0x20)
+    {
+        s_moduleClockTable = g_Ap20ModuleClockTable;
+        s_moduleClockTableSize = g_Ap20ModuleClockTableSize;
+        NvRmPrivAp20PllReferenceTableInit(&s_PllReferencesTable, 
+                &s_PllReferencesTableSize);
+        s_ClockSourceTable = NvRmPrivAp20ClockSourceTableInit();
+        fpgaModuleFreq = FPGA_MODULE_KHZ_AP20;
+    }
+    else
+        NV_ASSERT(!"Unsupported chip ID");
+
+    /*
+     * Allocate module clock state array, and map module clock descriptors
+     * to module instances.
+     */
+    s_moduleClockState = (NvRmModuleClockState *)
+        NvOsAlloc(sizeof (NvRmModuleClockState) * s_moduleClockTableSize);
+    if (s_moduleClockState == NULL)
+    {
+        e = NvError_InsufficientMemory;
+        goto fail;
+    }
+    NvOsMemset(s_moduleClockState, 0,
+            sizeof(NvRmModuleClockState) * s_moduleClockTableSize);
+
+    for (i = 0; i < s_moduleClockTableSize; i++)
+    {
+        NvRmModuleInstance* inst;
+        ModuleId = NVRM_MODULE_ID(
+            s_moduleClockTable[i].Module, s_moduleClockTable[i].Instance);
+
+        if (s_moduleClockTable[i].SubClockId)
+            continue;   // skip subclocks
+
+        if (NvRmPrivGetModuleInstance(hRmDevice, ModuleId, &inst) == NvSuccess)
+        {
+            inst->ModuleData = (void *)&s_moduleClockTable[i];
+        }
+        else
+        {
+            // NvOsDebugPrintf(
+            // "No module found for clock descriptor with module ID %d\n", ModuleID);
+        }
+    }
+
+    /*
+     * Clock limits and sources initialization
+     */
+    s_ModuleClockLimits = NvRmPrivClockLimitsInit(hRmDevice);
+    s_ClockSourceFreq[NvRmClockSource_Invalid] = 0;
+    s_SystemBusComplex.BusRateOffset = 0;
+    {
+        if (env == ExecPlatform_Fpga)
+        {
+            s_ClockSourceFreq[NvRmClockSource_ClkS] = 32;
+            s_ClockSourceFreq[NvRmClockSource_ClkM] = fpgaModuleFreq;
+            s_ClockSourceFreq[NvRmClockSource_ClkD] = fpgaModuleFreq;
+            s_ClockSourceFreq[NvRmClockSource_PllA0] = 12288;
+            s_ClockSourceFreq[NvRmClockSource_PllP0] = fpgaModuleFreq;
+            s_ClockSourceFreq[NvRmClockSource_PllC0] = fpgaModuleFreq;
+            s_ClockSourceFreq[NvRmClockSource_PllM0] = fpgaModuleFreq;
+            s_ClockSourceFreq[NvRmClockSource_PllX0] = fpgaModuleFreq;
+            s_ClockSourceFreq[NvRmClockSource_CpuBus] = fpgaModuleFreq;
+            s_ClockSourceFreq[NvRmClockSource_SystemBus] = fpgaModuleFreq;
+            NvRmPrivBusClockInit(
+                hRmDevice, s_ClockSourceFreq[NvRmClockSource_SystemBus]);
+        }
+        else if ((env == ExecPlatform_Qt) || (env == ExecPlatform_Sim))
+        {
+            s_ClockSourceFreq[NvRmClockSource_ClkS] = 32;
+            if (env == ExecPlatform_Sim) // On sim set main frequency 13MHz
+            {
+                s_ClockSourceFreq[NvRmClockSource_ClkM] = 13000;
+                s_ClockSourceFreq[NvRmClockSource_ClkD] = 26000;
+            }
+            else                        // On Qt keep 12MHz
+            {
+                s_ClockSourceFreq[NvRmClockSource_ClkM] = 12000;
+                s_ClockSourceFreq[NvRmClockSource_ClkD] = 24000;
+            }
+            s_ClockSourceFreq[NvRmClockSource_PllA0] =  12288;
+            s_ClockSourceFreq[NvRmClockSource_PllP0] = 432000;
+            s_ClockSourceFreq[NvRmClockSource_PllP1] =  28800;
+            s_ClockSourceFreq[NvRmClockSource_PllP2] =  48000;
+            s_ClockSourceFreq[NvRmClockSource_PllP3] =  72000;
+            s_ClockSourceFreq[NvRmClockSource_PllP4] = 108000;
+            s_ClockSourceFreq[NvRmClockSource_PllC0] = 600000;
+            s_ClockSourceFreq[NvRmClockSource_PllM0] = 333000;
+            s_ClockSourceFreq[NvRmClockSource_SystemBus] = 150000;
+            NvRmPrivAp15SimPllInit(hRmDevice); // Enable plls in simulation
+            NvRmPrivBusClockInit(
+                hRmDevice, s_ClockSourceFreq[NvRmClockSource_SystemBus]);
+        }
+        else if (env == ExecPlatform_Soc)
+        {
+            NvRmPrivClockSourceFreqInit(hRmDevice, s_ClockSourceFreq);
+        }
+        else
+        {
+            NV_ASSERT(!"Not supported execution platform");
+        }
+        RmReset2D(hRmDevice);
+    }
+
+    /*
+     * Initialize current modules clock state
+     */
+    if (env == ExecPlatform_Fpga)
+    {
+        for (i = 0; i < s_moduleClockTableSize; i++)
+        {                        
+            s_moduleClockState[i].actual_freq = fpgaModuleFreq;
+        }
+    }
+    else if (env == ExecPlatform_Qt)
+    {
+        for (i = 0; i < s_moduleClockTableSize; i++)
+        {
+            s_moduleClockState[i].actual_freq = QT_MODULE_KHZ;
+        }
+    }
+    ModuleClockStateInit(hRmDevice);
+    ScaledClockConfigInit(hRmDevice);
+
+    /* debug info... print out some initial frequencies */
+    {
+        NvU32 freq;
+
+        if (NvRmPrivGetClockSourceHandle(NvRmClockSource_PllX0))
+        {
+            NvOsDebugPrintf("NVRM CLOCKS: PLLX0:      %d Khz\n",
+                            s_ClockSourceFreq[NvRmClockSource_PllX0]);
+        }
+        NvOsDebugPrintf("NVRM CLOCKS: PLLM0:      %d Khz\n",
+                        s_ClockSourceFreq[NvRmClockSource_PllM0]);
+        NvOsDebugPrintf("NVRM CLOCKS: PLLC0:      %d Khz\n",
+                        s_ClockSourceFreq[NvRmClockSource_PllC0]);
+        NvOsDebugPrintf("NVRM CLOCKS: PLLP0:      %d Khz\n",
+                        s_ClockSourceFreq[NvRmClockSource_PllP0]);
+        NvOsDebugPrintf("NVRM CLOCKS: PLLA0:      %d Khz\n",
+                        s_ClockSourceFreq[NvRmClockSource_PllA0]);
+        NvOsDebugPrintf("NVRM CLOCKS: CPU:        %d Khz\n",
+                        s_ClockSourceFreq[NvRmClockSource_CpuBus]);
+        NvOsDebugPrintf("NVRM CLOCKS: AVP:        %d Khz\n",
+                        s_ClockSourceFreq[NvRmClockSource_SystemBus]);
+        NvOsDebugPrintf("NVRM CLOCKS: System Bus: %d Khz\n",
+                        s_ClockSourceFreq[NvRmClockSource_SystemBus]);
+
+        NV_ASSERT_SUCCESS(NvRmPowerModuleClockConfig(
+            hRmDevice, NvRmPrivModuleID_MemoryController,
+            0, 0, 0, NULL, 0, &freq, 0));
+        NvOsDebugPrintf("NVRM CLOCKS: Memory Controller: %d\n", freq);
+
+        NV_ASSERT_SUCCESS(NvRmPowerModuleClockConfig(
+            hRmDevice, NvRmPrivModuleID_ExternalMemoryController,
+            0, 0, 0, NULL, 0, &freq, 0));
+        NvOsDebugPrintf("NVRM CLOCKS: External Memory Controller: %d\n", freq);
+    }
+
+    return NvSuccess;
+
+fail:
+    NvOsFree(s_moduleClockState);
+    s_moduleClockState = NULL;
+    NvOsMutexDestroy(s_hPllMutex);
+    s_hPllMutex = NULL;
+    NvOsSpinMutexDestroy(s_hClockMutex);
+    s_hClockMutex = NULL;
+    return e;
+}
+
+void
+NvRmPrivClocksDeinit(NvRmDeviceHandle hRmDevice)
+{
+    NV_ASSERT(hRmDevice);
+
+    if (s_moduleClockState != NULL)
+    {
+        // TODO: check refrence counts for "clock leakage"
+    }
+    NvOsFree(s_moduleClockState);
+    s_moduleClockState = NULL;
+    NvOsMutexDestroy(s_hPllMutex);
+    s_hPllMutex = NULL;
+    NvOsSpinMutexDestroy(s_hClockMutex);
+    s_hClockMutex = NULL;
+}
+
+void
+NvRmPrivBoostClocks(NvRmDeviceHandle hRmDevice)
+{
+    NvRmFreqKHz FreqKHz;
+
+    // Initialize core voltage control
+    NvRmPrivDvsInit();
+
+    // Configure fast memory and core clocks (nominal core, CPU and memory
+    // voltages are already set by this time during PMU initialization)
+    if ((hRmDevice->ChipId.Id == 0x15) || (hRmDevice->ChipId.Id == 0x16))
+    {
+        NvRmPrivAp15FastClockConfig(hRmDevice);
+    }
+    else if (hRmDevice->ChipId.Id == 0x20)
+    {
+        NvRmPrivAp20FastClockConfig(hRmDevice);
+    }
+
+    // Print fast clocks
+    NvOsDebugPrintf("ADJUSTED CLOCKS:\n");
+    NV_ASSERT_SUCCESS(NvRmPowerModuleClockConfig(
+        hRmDevice, NvRmPrivModuleID_MemoryController,
+        0, 0, 0, NULL, 0, &FreqKHz, 0));
+    NvOsDebugPrintf("MC clock is set to %6d KHz\n", FreqKHz);
+
+    NV_ASSERT_SUCCESS(NvRmPowerModuleClockConfig(
+        hRmDevice, NvRmPrivModuleID_ExternalMemoryController,
+        0, 0, 0, NULL, 0, &FreqKHz, 0));
+    NvOsDebugPrintf("EMC clock is set to %6d KHz (DDR clock is at %6d KHz)\n",
+                    FreqKHz, FreqKHz/2);
+
+    if (NvRmPrivGetClockSourceHandle(NvRmClockSource_PllX0))
+    {
+        FreqKHz = NvRmPrivGetClockSourceFreq(NvRmClockSource_PllX0);
+        NvOsDebugPrintf("PLLX0 clock is set to %6d KHz\n", FreqKHz);
+    }
+    FreqKHz = NvRmPrivGetClockSourceFreq(NvRmClockSource_PllC0);
+    NvOsDebugPrintf("PLLC0 clock is set to %6d KHz\n", FreqKHz);
+    FreqKHz = NvRmPrivGetClockSourceFreq(NvRmClockSource_CpuBus);
+    NvOsDebugPrintf("CPU clock is set to %6d KHz\n", FreqKHz);
+    FreqKHz = NvRmPrivGetClockSourceFreq(NvRmClockSource_SystemBus);
+    NvOsDebugPrintf("System and AVP clock is set to %6d KHz\n", FreqKHz);
+
+    // Print GPU clocks
+    #define DEBUG_PRINT_MODULE_CLOCK(Name) \
+    do\
+    {\
+        NV_ASSERT_SUCCESS(NvRmPowerModuleClockConfig( \
+            hRmDevice, NvRmModuleID_##Name, 0, 0, 0, NULL, 0, &FreqKHz, 0)); \
+        NvOsDebugPrintf(#Name " clock is set to %6d KHz\n", FreqKHz); \
+    } while (0)
+
+    DEBUG_PRINT_MODULE_CLOCK(GraphicsHost);
+    DEBUG_PRINT_MODULE_CLOCK(3D);
+    DEBUG_PRINT_MODULE_CLOCK(2D);
+    DEBUG_PRINT_MODULE_CLOCK(Epp);
+    DEBUG_PRINT_MODULE_CLOCK(Mpe);
+    DEBUG_PRINT_MODULE_CLOCK(Vde);
+    #undef DEBUG_PRINT_MODULE_CLOCK
+}
+
+typedef struct NvRmPllRailMapRec
+{
+    // PLL Clock Source Id
+    NvRmClockSource PllId;
+
+    // Power rail GUID
+    NvU64 PllRailId;
+} NvRmPllRailMap;
+
+static const NvRmPllRailMap s_PllRailMap[] =
+{
+    { NvRmClockSource_ClkM, NV_VDD_OSC_ODM_ID},
+    { NvRmClockSource_PllA1, NV_VDD_PLLA_ODM_ID},
+    { NvRmClockSource_PllC0, NV_VDD_PLLC_ODM_ID},
+    { NvRmClockSource_PllD0, NV_VDD_PLLD_ODM_ID},
+    { NvRmClockSource_PllM0, NV_VDD_PLLM_ODM_ID},
+    { NvRmClockSource_PllP0, NV_VDD_PLLP_ODM_ID},
+    { NvRmClockSource_PllU0, NV_VDD_PLLU1_ODM_ID},
+    { NvRmClockSource_PllX0, NV_VDD_PLLX_ODM_ID},
+};
+
+void
+NvRmPrivPllRailsInit(NvRmDeviceHandle hRmDevice)
+{
+    NvU32 i;
+
+    for (i = 0; i < NV_ARRAY_SIZE(s_PllRailMap); i++)
+    {
+        NvU64 PllRailId = s_PllRailMap[i].PllRailId;
+        NvRmClockSource PllId = s_PllRailMap[i].PllId;
+        switch (PllId)
+        {
+            // If present PLLX is treated as other boot PLLs
+            case NvRmClockSource_PllX0:
+                if (!NvRmPrivGetClockSourceHandle(NvRmClockSource_PllX0))
+                    break;
+                // fall through
+
+            // Oscillator and boot PLLs are already running - turn the
+            // respective rails On, anyway, to sync ref count
+            case NvRmClockSource_ClkM:
+            case NvRmClockSource_PllC0:
+            case NvRmClockSource_PllM0:
+            case NvRmClockSource_PllP0:
+                NvRmPrivPmuRailControl(hRmDevice, PllRailId, NV_TRUE);
+                break;
+
+            // If PLLA rail is turned On by BL - update ref count, otherwise
+            // turn rail On, but leave PLLA disabled
+            case NvRmClockSource_PllA1:
+                if (NvRmPrivPmuRailGetVoltage(hRmDevice, PllRailId) == 0)
+                {
+                    NvRmPrivAp15PllSet(hRmDevice,
+                        NvRmPrivGetClockSourceHandle(PllId)->pInfo.pPll,
+                        0, 0, 0, (NvU32)-1, 0, 0, NV_TRUE, 0);
+                }
+                NvRmPrivPmuRailControl(hRmDevice, PllRailId, NV_TRUE);
+                break;
+
+            // If PLLD rail is turned On by BL - update ref count, otherwise
+            // keep it Off and disable PLLD; initialize PLLD rail status
+            case NvRmClockSource_PllD0:
+                if (NvRmPrivPmuRailGetVoltage(hRmDevice, PllRailId) != 0)
+                {
+                    s_MipiPllVddOn = NV_TRUE;
+                    NvRmPrivPmuRailControl(hRmDevice, PllRailId, NV_TRUE);
+                }
+                else
+                {
+                    s_MipiPllVddOn = NV_FALSE;
+                    NvRmPrivAp15PllSet(hRmDevice,
+                        NvRmPrivGetClockSourceHandle(PllId)->pInfo.pPll,
+                        0, 0, 0, (NvU32)-1, 0, 0, NV_TRUE, 0);
+                }
+                break;
+
+            // PLLU rail is controlled by USB stack - don't touch it, unless
+            // USB download transport is active. In the latter case update ref
+            // counts for PLLU and USB power rails
+            case NvRmClockSource_PllU0:
+                if (NvRmPrivGetDownloadTransport(hRmDevice) ==
+                    NvOdmDownloadTransport_Usb)
+                {
+                    NvRmPrivPmuRailControl(hRmDevice, PllRailId, NV_TRUE);
+                    NvRmPrivPmuRailControl(hRmDevice, NV_VDD_USB_ODM_ID, NV_TRUE);
+                }
+                break;
+
+            default:
+                NV_ASSERT(!"Invalid Id");
+        }
+    }
+}
+
+void
+NvRmPrivClocksResume(NvRmDeviceHandle hRmDevice)
+{
+    // Sync clock sources after LP0
+    NvRmPrivClockSourceFreqInit(hRmDevice, s_ClockSourceFreq);
+    ScaledClockConfigInit(hRmDevice);
+    if ((hRmDevice->ChipId.Id == 0x15) || (hRmDevice->ChipId.Id == 0x16))
+        NvRmPrivAp15FastClockConfig(hRmDevice);
+    else if (hRmDevice->ChipId.Id == 0x20)
+        NvRmPrivAp20FastClockConfig(hRmDevice);
+
+}
+
+/*****************************************************************************/
+
+NvRmFreqKHz
+NvRmPrivGetInterfaceMaxClock(NvRmDeviceHandle hRmDevice, NvRmModuleID ModuleId)
+{
+
+    NvU32 OdmModules[4];
+    NvU32 OdmInstances[4];        
+    NvU32* pMaxClockSpeed = NULL;
+    NvU32 count = 0;
+    NvU32 i = 0;
+    NvU32 instance = 0;
+    NvU32 NumOdmModules = 0;
+    NvU32 MaxFreq = 0;
+
+    MaxFreq = NvRmFreqMaximum;
+
+    NumOdmModules = NvRmPrivRmModuleToOdmModule(hRmDevice->ChipId.Id,
+                        ModuleId, (NvOdmIoModule *)OdmModules, OdmInstances);
+
+    for(i = 0; i < NumOdmModules; i++)
+    {
+        instance = OdmInstances[i];
+        NvOdmQueryClockLimits(OdmModules[i], (const NvU32 **)&pMaxClockSpeed, &count);
+        if ((pMaxClockSpeed) && (instance < count))
+        {       
+            MaxFreq = pMaxClockSpeed[instance];
+        }            
+    }
+
+    return MaxFreq;    
+}
+
+NvRmFreqKHz
+NvRmPrivModuleGetMaxSrcKHz(
+    NvRmDeviceHandle hRmDevice,
+    const NvRmModuleClockInfo* cinfo)
+{
+    NvU32 i;
+    NvRmFreqKHz SourceClockFreq = 0;
+
+    for (i=0; i < NvRmClockSource_Num; i++)
+    {
+        NV_ASSERT(cinfo->Sources[i] < NvRmClockSource_Num);
+        if (cinfo->Sources[i] == NvRmClockSource_Invalid)
+            break;
+        if (NvRmPrivIsSourceProtected(
+            hRmDevice, cinfo->Module, cinfo->Sources[i]))
+            continue;
+        SourceClockFreq =
+            NV_MAX(SourceClockFreq, s_ClockSourceFreq[(cinfo->Sources[i])]);
+    }
+    return SourceClockFreq;
+}
+
+static NvRmMilliVolts ModuleVscaleConfig(
+    NvRmDeviceHandle hRmDevice,
+    const NvRmModuleClockInfo* cinfo,
+    NvRmModuleClockState *state,
+    NvRmFreqKHz MaxFreq,
+    NvBool Preview)
+{
+    NvRmFreqKHz f, SourceClockFreq;
+    NvRmMilliVolts v = NvRmVoltsUnspecified;
+    NvRmModuleID ModuleName = cinfo->Module;
+
+    if (!state->Vscale)
+        return v;
+
+    // Find voltage level for the actually configured frequency. For Display,
+    // UART and USB use maximum requested frequency, instead (Display and UART
+    // actual clock configuration is completed outside CAR but it will not
+    // exceed maximum requested boundary level; actual USB frequency is always
+    // set to fixed PLLU output, but maximum boundary is used by driver to
+    // communicate scaled voltage requirements).
+    SourceClockFreq =
+        s_ClockSourceFreq[(cinfo->Sources[state->SourceClock])];
+
+    if ((ModuleName == NvRmModuleID_Display) ||
+        (ModuleName == NvRmModuleID_Uart) ||
+        (ModuleName == NvRmModuleID_Usb2Otg))
+        f = MaxFreq;
+    else
+        f = state->actual_freq;
+
+    v = NvRmPrivModuleVscaleReAttach(
+        hRmDevice, cinfo, state, f, SourceClockFreq, Preview);
+    return v;
+}
+
+NvError
+NvRmPowerModuleClockConfig (
+    NvRmDeviceHandle hDevice,
+    NvRmModuleID ModuleId,
+    NvU32 ClientId,
+    NvRmFreqKHz MinFreq,
+    NvRmFreqKHz MaxFreq,
+    const NvRmFreqKHz* PrefFreqList,
+    NvU32 PrefFreqListCount,
+    NvRmFreqKHz* CurrentFreq,
+    NvU32 flags)
+{
+    NvError err = NvSuccess;
+    NvRmModuleClockInfo *cinfo = NULL;
+    NvU32 divisor = 0x0;
+    NvU32 reg = 0x0;
+    NvRmFreqKHz f, SourceClockFreq;
+    ExecPlatform env;
+    NvRmModuleClockState *state;
+    NvRmMilliVolts v = NvRmVoltsOff;
+    NvRmModuleID ModuleName = NVRM_MODULE_ID_MODULE( ModuleId );
+    NvU32 MaxInterfaceClock = 0;
+
+    NvBool DiagMode = NvRmPrivIsDiagMode(ModuleId);
+
+    /* validate the Rm Handle */
+    NV_ASSERT(hDevice);
+    env = NvRmPrivGetExecPlatform(hDevice);
+
+    // Get pointers to module clock info and current module clock state
+    err = NvRmPrivGetClockState(hDevice, ModuleId, &cinfo, &state);
+    if (err != NvSuccess)
+        return err;
+
+    if ((flags & NvRmClockConfig_SubConfig) &&
+        ((ModuleName == NvRmModuleID_Spdif) ||
+         (ModuleName == NvRmModuleID_Vi) ||
+         (ModuleName == NvRmModuleID_Tvo)))
+    {
+        // Module subclock is to be configured. Use subclock descriptor
+        // and subclock state (located immediately after main descriptor,
+        // and state, respectively)
+        state++;
+        cinfo++;
+        NV_ASSERT(cinfo->Module == ModuleName);
+        NV_ASSERT(cinfo->SubClockId == 1);
+    }
+    else if (PrefFreqList && (PrefFreqList[0] == NvRmFreqMaximum) &&
+             ((ModuleName == NvRmModuleID_2D)  ||
+              (ModuleName == NvRmModuleID_Epp) ||
+              (ModuleName == NvRmModuleID_GraphicsHost)))
+    {
+        // Maximum frequency for these modules is synchronized with EMC
+        f = NvRmPrivGetEmcSyncFreq(hDevice, ModuleName);
+        if (f == state->actual_freq)
+        {
+            if (CurrentFreq)
+                *CurrentFreq = f;
+            return err;             // already in sync
+        }
+        MaxFreq = f + 1;            // 1 kHz margin
+    }
+    else if (PrefFreqList &&
+             ((ModuleName == NvRmModuleID_Vde) ||
+              (ModuleName == NvRmPrivModuleID_MemoryController) ||
+              (ModuleName == NvRmPrivModuleID_ExternalMemoryController)))
+    {   // CPU, AVP are not allowed too, but failed get state if tried
+        NV_ASSERT(!"MC/EMC, VDE clock configuration is not allowed here");
+        return NvError_NotSupported;
+    }
+
+    // Clip frequency boundaries to h/w limitations
+    if (PrefFreqList)
+    {
+        const NvRmModuleClockLimits* pClimits =
+            NvRmPrivGetSocClockLimits(cinfo->Module);
+        if ((MinFreq == NvRmFreqUnspecified) ||
+            (MinFreq < pClimits->MinKHz))
+        {
+            MinFreq = pClimits->MinKHz;
+        }
+        MaxInterfaceClock = NV_MIN(pClimits->MaxKHz,
+            NvRmPrivGetInterfaceMaxClock(hDevice, ModuleId));
+        if ((MaxFreq == NvRmFreqUnspecified) ||
+            (MaxFreq > MaxInterfaceClock))
+        {
+            MaxFreq = MaxInterfaceClock;
+        }
+    }
+
+#if NVRM_DIAG_LOCK_SUPPORTED
+    // Check/set individual diag lock for this clock only
+    DiagMode |= state->DiagLock;
+    if (flags & NvRmClockConfig_DiagLock)
+        state->DiagLock = NV_TRUE;
+#endif
+
+    // Display/DSI clock configuration also affects PLLs shared with DVFS
+    // and involves PLLD power control. Always perform at nominal voltage.
+    // PMU access transport must *not* be scalable (PMU transport API must
+    // be called outside clock mutex).
+    if (PrefFreqList && (!DiagMode) &&
+        ((ModuleName == NvRmModuleID_Display) ||
+         (ModuleName == NvRmModuleID_Dsi)))
+    {
+        NvOsMutexLock(s_hPllMutex);
+        NvRmPrivPllDPowerControl(hDevice, NV_TRUE, &s_MipiPllVddOn);
+        NvRmPrivDvsRequest(NvRmVoltsMaximum);
+    }
+
+    NvOsSpinMutexLock(s_hClockMutex);
+    {
+        if (env == ExecPlatform_Fpga || env == ExecPlatform_Qt)
+        {
+            // Clock configuration only supported for the i2s, VI, i2c, 
+            // dvc and HSMMC on this environment
+            if (!(ModuleName == NvRmModuleID_I2s ||
+                    ModuleName == NvRmModuleID_Vi ||
+                    ModuleName == NvRmModuleID_Dvc ||
+                    ModuleName == NvRmModuleID_I2c ||
+                    ModuleName == NvRmModuleID_Hsmmc ||
+                    ModuleName == NvRmModuleID_OneWire
+                    ))
+            {
+                // Return actual display clock only on FPGA
+                if ((env == ExecPlatform_Fpga) &&
+                    (ModuleName == NvRmModuleID_Display))
+                {
+                    state->actual_freq = FPGA_DISPLAY_KHZ;
+                }
+
+                goto end;
+            }
+        }
+        if (PrefFreqList && (!DiagMode))
+        {
+            if ((ModuleName != NvRmModuleID_Dsi) &&
+                (ModuleName != NvRmModuleID_Usb2Otg))
+                NV_ASSERT(cinfo->SourceFieldMask || cinfo->DivisorFieldMask);
+
+            // Get the best module source clock and divider
+            err = NvRmFindBestClockSource(hDevice, cinfo, NvRmClockSource_Num,
+                   MinFreq, MaxFreq, PrefFreqList, PrefFreqListCount, state, flags);
+            if (err != NvSuccess)
+            {
+                goto leave;
+            }
+            NV_ASSERT(state->SourceClock <= cinfo->SourceFieldMask);
+
+            // For "shared" clocks (Display/DSI) voltage is already at max;
+            // just record new voltage requirements
+            if ((ModuleName == NvRmModuleID_Display) ||
+                (ModuleName == NvRmModuleID_Dsi))
+            {
+                NvRmPrivModuleVscaleSetPending(hDevice, NvRmVoltsMaximum);
+                v = ModuleVscaleConfig(
+                    hDevice, cinfo, state, MaxFreq, NV_FALSE);
+                NvRmPrivModuleVscaleSetPending(hDevice, NvRmVoltsOff);
+            }
+            else
+            {
+                // Preview, don't update scaling ref counts if voltage going up
+                v = ModuleVscaleConfig(
+                    hDevice, cinfo, state, MaxFreq, NV_TRUE);
+
+                if ((v != NvRmVoltsOff) &&
+                    (v != NvRmVoltsUnspecified))
+                {
+                    // Preview reported voltage increase - set target
+                    // pending to prevent DVFS scaling down
+                    NvRmPrivModuleVscaleSetPending(hDevice, v);
+
+                    NvOsSpinMutexUnlock(s_hClockMutex);
+                    NvOsMutexLock(s_hPllMutex);
+                    NvRmPrivDvsRequest(v);
+                    NvOsMutexUnlock(s_hPllMutex);
+                    NvOsSpinMutexLock(s_hClockMutex);
+
+                    // Now, after voltage is increased - update scaling counts
+                    // and cancel pending request
+                    v = ModuleVscaleConfig(
+                        hDevice, cinfo, state, MaxFreq, NV_FALSE);
+                    NvRmPrivModuleVscaleSetPending(hDevice, NvRmVoltsOff);
+                }
+            }
+
+            // Finally change clock configuration
+            if ((ModuleName != NvRmModuleID_Dsi) &&
+                (ModuleName != NvRmModuleID_Usb2Otg))
+            {
+                // Set new clock state
+                NvRmPrivModuleClockSet(hDevice, cinfo, state);
+                if ((ModuleName == NvRmModuleID_Tvo) &&
+                    (cinfo->SubClockId == 1))   // if CVE - sync TVDAC
+                {
+                    NV_ASSERT(((cinfo + 1)->Module == NvRmModuleID_Tvo) &&
+                              ((cinfo + 1)->SubClockId == 2));
+                    *(state + 1) = *state;
+                    NvRmPrivModuleClockSet(hDevice, (cinfo + 1), state);
+                }
+                NvRmPrivModuleClockReAttach(hDevice, cinfo, state);
+                NvRmPrivDisablePLLs(hDevice, cinfo, state);
+            }
+            if (v == NvRmVoltsOff)
+                NvRmPrivDvsRequest(v); // No transaction, just set update flag
+
+            // FIXME is this a hack just for the AP15 FPGA
+            // Special treatment to the i2s on the fpga to do the workaround
+            // for the i2s recording, the clock source to i2s should be less than
+            // the system clock frequency 8.33MHz for the fpga, so dividing by 2
+            // if its more than
+            if ((hDevice->ChipId.Id == 0x15 || hDevice->ChipId.Id == 0x16) && 
+                    (env == ExecPlatform_Fpga) && (ModuleName == NvRmModuleID_I2s))
+            {
+                reg = NV_REGR(hDevice, NvRmPrivModuleID_ClockAndReset, 0,
+                              cinfo->ClkSourceOffset);
+                if (!(reg & 0x7f))
+                {
+                    reg |= 1;
+                    NV_REGW(hDevice, NvRmPrivModuleID_ClockAndReset, 0,
+                            cinfo->ClkSourceOffset, reg);
+                    state->actual_freq = state->actual_freq/2;
+                }
+            }
+            // Hack: on FPGA OneWire divider is implemented as integer divider
+            // (on SoC it is fractional divider)
+            if ((env == ExecPlatform_Fpga) &&
+                (ModuleName == NvRmModuleID_OneWire))
+            {
+                reg = NV_REGR(hDevice, NvRmPrivModuleID_ClockAndReset, 0,
+                              cinfo->ClkSourceOffset);
+                reg &= ~(cinfo->DivisorFieldMask << cinfo->DivisorFieldShift);
+                reg |= (state->Divider >> 1) << cinfo->DivisorFieldShift;
+                NV_REGW(hDevice, NvRmPrivModuleID_ClockAndReset, 0,
+                        cinfo->ClkSourceOffset, reg);
+            }
+        }
+        else    // No target list just update state from h/w and return current frequency
+        {
+            if (cinfo->SourceFieldMask != 0)
+            {
+                NV_ASSERT(cinfo->ClkSourceOffset);
+                state->SourceClock = NV_REGR(
+                    hDevice, NvRmPrivModuleID_ClockAndReset, 0, cinfo->ClkSourceOffset);
+                state->SourceClock >>= cinfo->SourceFieldShift;
+                state->SourceClock &= cinfo->SourceFieldMask;
+                SourceClockFreq = s_ClockSourceFreq[(cinfo->Sources[state->SourceClock])];
+            }
+            else
+            {
+                // If source is Fixed source always at index 0
+                SourceClockFreq = s_ClockSourceFreq[(cinfo->Sources[0])];
+            }
+            if ((ModuleName == NvRmPrivModuleID_MemoryController) ||
+                (ModuleName == NvRmPrivModuleID_ExternalMemoryController))
+                NvRmPrivMemoryClockReAttach(hDevice, cinfo, state);
+            else
+                NvRmPrivModuleClockReAttach(hDevice, cinfo, state);
+
+            if ( cinfo->Divider  != NvRmClockDivider_None )
+            {
+                NV_ASSERT(cinfo->ClkSourceOffset);
+                state->Divider = NV_REGR(
+                    hDevice, NvRmPrivModuleID_ClockAndReset, 0, cinfo->ClkSourceOffset);
+                state->Divider >>= cinfo->DivisorFieldShift;
+                state->Divider &= cinfo->DivisorFieldMask;
+
+                divisor = state->Divider;
+                if (cinfo->Divider == NvRmClockDivider_Integer_1)
+                {
+                    divisor += 1;
+                }
+                else if (cinfo->Divider == NvRmClockDivider_Fractional_2)
+                {
+                    divisor += 2;
+                    SourceClockFreq = (SourceClockFreq << 1);
+                }
+                else if (cinfo->Divider == NvRmClockDivider_Integer_2)
+                {
+                    divisor += 2;
+                }
+            }
+            else
+            {
+                state->Divider = 1;
+                divisor = 1;
+            }
+            NV_ASSERT(divisor);
+            state->actual_freq = SourceClockFreq / divisor;
+        }
+
+        /*
+         * VI and I2S has some special bits in the clock register
+         */
+        NvRmPrivAp15ClockConfigEx(
+            hDevice, ModuleName, cinfo->ClkSourceOffset, flags);
+
+
+        /* 
+         * SDMMC internal feedback tap delay adjustment
+         * This is required for the ap20 based boards.
+        */            
+        if ((PrefFreqListCount) && (hDevice->ChipId.Id == 0x20) && 
+                (ModuleName == NvRmModuleID_Sdio))
+        {
+            NvRmPrivAp20SdioTapDelayConfigure(hDevice, ModuleId,
+                    cinfo->ClkSourceOffset, state->actual_freq); 
+        }
+    }
+
+end:
+    if (CurrentFreq)
+    {
+        *CurrentFreq = state->actual_freq;
+    }
+leave:
+    NvOsSpinMutexUnlock(s_hClockMutex);
+    if (PrefFreqList && (!DiagMode) &&
+        ((ModuleName == NvRmModuleID_Display) ||
+         (ModuleName == NvRmModuleID_Dsi)))
+    {
+        NvRmPrivPllDPowerControl(hDevice, NV_FALSE, &s_MipiPllVddOn);
+        NvRmPrivDvsRequest(NvRmVoltsOff);
+        NvOsMutexUnlock(s_hPllMutex);
+    }
+    return err;
+}
+
+/*****************************************************************************/
+
+NvRmClockSource
+NvRmPrivCoreClockSourceGet(
+    NvRmDeviceHandle hRmDevice,
+    const NvRmCoreClockInfo* pCinfo)
+{
+    NvU32 i, reg;
+    NvU32 ModeField;
+
+    NV_ASSERT(hRmDevice);
+    NV_ASSERT(pCinfo);
+
+    reg = NV_REGR(hRmDevice, NvRmPrivModuleID_ClockAndReset, 0, pCinfo->SelectorOffset);
+    ModeField = (reg >> pCinfo->ModeFieldShift) & pCinfo->ModeFieldMask;
+    if (ModeField == 0)
+    {
+        // One fixed 32kHz clock source, if mode field is cleared
+        return NvRmClockSource_ClkS;
+    }
+    // Selected Clock Mode = 1 + LOG2(mode field)
+    for (i = 0; ModeField != 0; ModeField >>= 1, i++);
+    NV_ASSERT(i < NvRmCoreClockMode_Num);
+
+    // Source selection index = source field value for currently selected mode
+    reg = (reg >> pCinfo->SourceFieldShifts[i]) & pCinfo->SourceFieldMasks[i];
+    NV_ASSERT(reg < NvRmClockSource_Num);
+
+    return pCinfo->Sources[reg];
+}
+
+NvRmFreqKHz
+NvRmPrivCoreClockFreqGet(
+    NvRmDeviceHandle hRmDevice,
+    const NvRmCoreClockInfo* pCinfo)
+{
+    NvU32 reg, n, m;
+    NvRmFreqKHz ClkFreq;
+    NvRmClockSource ClkSrcId;
+
+    NV_ASSERT(hRmDevice);
+    NV_ASSERT(pCinfo);
+
+    // Get source frequency
+    ClkSrcId = NvRmPrivCoreClockSourceGet(hRmDevice, pCinfo);
+    ClkFreq = s_ClockSourceFreq[ClkSrcId];
+    NV_ASSERT(ClkFreq);
+
+    // Get divider settings and calculate clock frequency
+    reg = NV_REGR(hRmDevice, NvRmPrivModuleID_ClockAndReset, 0, pCinfo->DividerOffset);
+    m = (reg >> pCinfo->DividendFieldShift) & pCinfo->DividendFieldMask;
+    n = (reg >> pCinfo->DivisorFieldShift) & pCinfo->DivisorFieldMask;
+    if ((reg >> pCinfo->DividerEnableFiledShift) & pCinfo->DividerEnableFiledMask)
+    {
+        if (m < n)  // if enabled and dividend below divisor
+        {
+            if (n == pCinfo->DivisorFieldMask)
+            {
+                // special divisor DFS is using
+                ClkFreq = (ClkFreq * (m + 1)) >> pCinfo->DivisorFieldSize;
+            }
+            else
+            {
+                // initially may be general divisor
+                ClkFreq = (ClkFreq * (m + 1)) / (n + 1);
+            }
+        }
+    }
+    return ClkFreq;
+}
+
+static void
+CoreClockSwitch(
+    NvRmDeviceHandle hRmDevice,
+    const NvRmCoreClockInfo* pCinfo,
+    NvU32 SourceIndex,
+    NvU32 Divider,
+    NvBool SrcFirst,
+    NvRmFreqKHz CoreFreq)
+{
+    NvU32 reg;
+    
+    // Construct core source control register settings.
+    // Always use Idle clock mode; mode field = 2 ^ (Mode - 1)
+    NV_ASSERT(pCinfo->SelectorOffset);
+    NV_ASSERT(SourceIndex <= pCinfo->SourceFieldMasks[NvRmCoreClockMode_Idle]);
+        
+    reg = ( ((0x1 << (NvRmCoreClockMode_Idle - 1)) << pCinfo->ModeFieldShift) |
+            (SourceIndex << pCinfo->SourceFieldShifts[NvRmCoreClockMode_Idle]) );    
+    
+    if (reg != NV_REGR(
+        hRmDevice, NvRmPrivModuleID_ClockAndReset, 0, pCinfo->SelectorOffset))
+    {
+        // Update PLL reference
+        NvRmPrivCoreClockReAttach(
+            hRmDevice, pCinfo->SourceId, pCinfo->Sources[SourceIndex]);
+    }
+
+    // Switch source and divider according to specified order. This guarantees
+    // that core frequency stays below maximum of "old" and "new" settings. 
+    // Configure EMC LL path before and after clock switch.
+    if (pCinfo->SourceId == NvRmClockSource_CpuBus)
+        if ((hRmDevice->ChipId.Id == 0x15) || (hRmDevice->ChipId.Id == 0x16))
+            NvRmPrivAp15SetEmcForCpuSrcSwitch(hRmDevice);
+    if (SrcFirst)
+    {
+        NV_REGW(hRmDevice, NvRmPrivModuleID_ClockAndReset, 0, 
+                pCinfo->SelectorOffset, reg);
+        NvOsWaitUS(NVRM_CLOCK_CHANGE_DELAY);
+    }
+    NV_REGW(hRmDevice, NvRmPrivModuleID_ClockAndReset, 0,
+            pCinfo->DividerOffset, Divider);
+    NvOsWaitUS(NVRM_CLOCK_CHANGE_DELAY);
+    if (!SrcFirst)
+    {
+        NV_REGW(hRmDevice, NvRmPrivModuleID_ClockAndReset, 0,
+                pCinfo->SelectorOffset, reg);
+        NvOsWaitUS(NVRM_CLOCK_CHANGE_DELAY);
+    }
+    if (pCinfo->SourceId == NvRmClockSource_CpuBus)
+        if ((hRmDevice->ChipId.Id == 0x15) || (hRmDevice->ChipId.Id == 0x16))
+            NvRmPrivAp15SetEmcForCpuDivSwitch(hRmDevice, CoreFreq, NV_FALSE);
+}
+
+void
+NvRmPrivCoreClockSourceIndexFind(
+    const NvRmCoreClockInfo* pCinfo,
+    NvRmClockSource SourceId,
+    NvU32* pSourceIndex)
+{
+    NvU32 i;
+    NV_ASSERT(pSourceIndex && pCinfo);
+    *pSourceIndex = NvRmClockSource_Num; // source index out of valid range
+
+    // Find core descriptor index for the specified clock source
+    for (i = 0; i < NvRmClockSource_Num; i++)
+    {
+        if (pCinfo->Sources[i] == SourceId)
+        {
+            *pSourceIndex = i;
+            break;
+        }
+    }
+}
+
+void
+NvRmPrivCoreClockBestSourceFind(
+    const NvRmCoreClockInfo* pCinfo,
+    NvRmFreqKHz MaxFreq,
+    NvRmFreqKHz TargetFreq,
+    NvRmFreqKHz* pSourceFreq,
+    NvU32* pSourceIndex)
+{
+    NvU32 i;
+    NvRmFreqKHz SrcFreq = 0;
+    NvRmFreqKHz BestSrcFreq = 0;
+    NvU32 SrcIndex = NvRmClockSource_Num; // source index out of valid range
+
+    NV_ASSERT(pSourceFreq && pSourceIndex && pCinfo);
+
+    /*
+     * Find valid source with frequency closest to the requested one from
+     * the above; if such source does not exist, find source with frequency
+     * closest to the requested one from the below
+     */
+    for (i = 0; i < NvRmClockSource_Num; i++)
+    {
+        SrcFreq = s_ClockSourceFreq[pCinfo->Sources[i]];
+        if (SrcFreq == 0)
+            continue;
+        if (SrcFreq <= MaxFreq)
+        {
+            if (((BestSrcFreq < SrcFreq) && (BestSrcFreq < TargetFreq)) ||
+                ((BestSrcFreq >= SrcFreq) && (SrcFreq >= TargetFreq)))
+            {
+                SrcIndex = i;
+                BestSrcFreq = SrcFreq;
+            }
+        }
+    }
+    *pSourceIndex = SrcIndex;
+    *pSourceFreq = BestSrcFreq;
+}
+
+NvError
+NvRmPrivCoreClockConfigure(
+    NvRmDeviceHandle hRmDevice,
+    const NvRmCoreClockInfo* pCinfo,
+    NvRmFreqKHz MaxFreq,
+    NvRmFreqKHz* pFreq,
+    NvRmClockSource* pSourceId)
+{
+    NvU32 m, n, reg;
+    NvBool SrcFirst;
+    NvRmFreqKHz ClkFreq;
+    NvRmFreqKHz SrcFreq = 0;
+    NvU32 SrcIndex = NvRmClockSource_Num; // source index out of valid range
+
+    NV_ASSERT(hRmDevice);
+    NV_ASSERT(pFreq && pSourceId && pCinfo);
+    NV_ASSERT(*pSourceId < NvRmClockSource_Num);
+
+    // 0 kHz is not achievable, anyway; changing target to 1 kHz will result in
+    // minimum configurable frequency
+    ClkFreq = *pFreq;
+    if (ClkFreq == 0)
+        ClkFreq = 1;
+
+    /*
+     * If no valid source explicitly specified by the caller, determine the
+     * best clock source for the requested frequency. Otherwise, just use the
+     * requested source.
+     */
+    if (*pSourceId == NvRmClockSource_Invalid)
+    {
+        NvRmPrivCoreClockBestSourceFind(
+            pCinfo, MaxFreq, ClkFreq, &SrcFreq, &SrcIndex);
+    }
+    else
+    {
+        SrcFreq = s_ClockSourceFreq[*pSourceId];
+        if (SrcFreq <= MaxFreq)
+        {
+            NvRmPrivCoreClockSourceIndexFind(pCinfo, *pSourceId, &SrcIndex);
+        }
+    }
+    if (SrcIndex >= NvRmClockSource_Num)
+    {
+        // Could not find source
+        return NvError_NotSupported;
+    }
+    NV_ASSERT(SrcFreq);
+
+    /*
+     * Determine super divider settings and enable divider if necessary. Always
+     * use maximum possible divisor n = divisor mask, so n+1 = 2^(divisor size).
+     * Hence, Fout = Fin * (m+1) / (n+1) = (Fin * (m+1)) >> (divisor size), and
+     * respectively, m = ((Fout << (divisor size)) / Fin) - do not subtract 1
+     * as integer division would round down, anyway. Determine switching order:
+     * switch source 1st if new divider quotient is bigger than the old one.
+     */
+    n = pCinfo->DivisorFieldMask;
+    m = (ClkFreq << pCinfo->DivisorFieldSize) / (SrcFreq + 1);
+    if ((m < n) && (m <= pCinfo->DividendFieldMask))
+    {
+        NvU32 m_old, n_old;
+        SrcFirst = NV_FALSE;
+        reg = NV_REGR(
+            hRmDevice, NvRmPrivModuleID_ClockAndReset, 0, pCinfo->DividerOffset);
+        if ( ((reg >> pCinfo->DividerEnableFiledShift) &
+              pCinfo->DividerEnableFiledMask) == pCinfo->DividerEnableFiledMask )
+        {
+            m_old = (reg >> pCinfo->DividendFieldShift) & pCinfo->DividendFieldMask;
+            n_old = (reg >> pCinfo->DivisorFieldShift) & pCinfo->DivisorFieldMask;
+            if ( ((m + 1) * (n_old + 1)) >  ((n + 1) * (m_old + 1)) )
+                SrcFirst = NV_TRUE;
+        }
+        reg = (pCinfo->DividerEnableFiledMask << pCinfo->DividerEnableFiledShift) |
+              (m << pCinfo->DividendFieldShift) | (n << pCinfo->DivisorFieldShift);
+        // return actual clock frequency from the divider
+        *pFreq = (SrcFreq * (m + 1)) >> pCinfo->DivisorFieldSize;
+    }
+    else
+    {
+        SrcFirst = NV_TRUE;
+        reg = 0; // clear = disable divider
+        // return actual clock frequency from the source directly
+        *pFreq = SrcFreq;
+    }
+    // Finally set new core clock
+    CoreClockSwitch(hRmDevice, pCinfo, SrcIndex, reg, SrcFirst, *pFreq);
+
+    // return selected source id and update core bus frequency
+    *pSourceId = pCinfo->Sources[SrcIndex];
+    s_ClockSourceFreq[pCinfo->SourceId] = *pFreq;
+    if ((pCinfo->SourceId == NvRmClockSource_CpuBus) &&
+        NvRmPrivGetClockSourceHandle(NvRmClockSource_CpuBridge))
+    {
+        s_ClockSourceFreq[NvRmClockSource_CpuBridge] = NvRmPrivDividerFreqGet(
+            hRmDevice,
+            NvRmPrivGetClockSourceHandle(NvRmClockSource_CpuBridge)->pInfo.pDivider);
+    }
+    return NvSuccess;
+}
+
+void
+NvRmPrivCoreClockSet(
+    NvRmDeviceHandle hRmDevice,
+    const NvRmCoreClockInfo* pCinfo,
+    NvRmClockSource SourceId,
+    NvU32 m,
+    NvU32 n)
+{
+    NvU32 reg;
+    NvBool SrcFirst;
+    NvRmFreqKHz CoreFreq = 0;
+    NvU32 SrcIndex = NvRmClockSource_Num; // source index out of valid range
+    ExecPlatform env;
+    
+
+    NV_ASSERT(hRmDevice);
+    NV_ASSERT(pCinfo);
+    
+    env = NvRmPrivGetExecPlatform(hRmDevice);
+    
+    if (env == ExecPlatform_Fpga)
+        return;
+
+    NvRmPrivCoreClockSourceIndexFind(pCinfo, SourceId, &SrcIndex);
+    NV_ASSERT(SrcIndex < NvRmClockSource_Num);
+
+    /*
+     * Set divide: just cut off MSbits out of dividend and divisor range, and
+     * enable divider if m/n ration is below 1. Update new core frequency.
+     * Determine switching order: switch source 1st if new divider quotient is
+     * bigger than the old one.
+     */
+    m &= pCinfo->DividendFieldMask;
+    n &= pCinfo->DivisorFieldMask;
+    CoreFreq = s_ClockSourceFreq[SourceId];
+    if (m < n)
+    {
+        NvU32 m_old, n_old;
+        SrcFirst = NV_FALSE;
+        reg = NV_REGR(
+            hRmDevice, NvRmPrivModuleID_ClockAndReset, 0, pCinfo->DividerOffset);
+        if ( ((reg >> pCinfo->DividerEnableFiledShift) &
+              pCinfo->DividerEnableFiledMask) == pCinfo->DividerEnableFiledMask )
+        {
+            m_old = (reg >> pCinfo->DividendFieldShift) & pCinfo->DividendFieldMask;
+            n_old = (reg >> pCinfo->DivisorFieldShift) & pCinfo->DivisorFieldMask;
+            if ( ((m + 1) * (n_old + 1)) >  ((n + 1) * (m_old + 1)) )
+                SrcFirst = NV_TRUE;
+        }
+        reg = (pCinfo->DividerEnableFiledMask << pCinfo->DividerEnableFiledShift) |
+              (m << pCinfo->DividendFieldShift) | (n << pCinfo->DivisorFieldShift);
+        CoreFreq = (CoreFreq * (m + 1)) / (n + 1);
+    }
+    else
+    {
+        SrcFirst = NV_TRUE;
+        reg = 0; // clear = disable divider
+    }
+    // Finally set new core clock
+    CoreClockSwitch(hRmDevice, pCinfo, SrcIndex, reg, SrcFirst, CoreFreq);
+
+    // update core bus frequency
+    s_ClockSourceFreq[pCinfo->SourceId] = CoreFreq;
+    if ((pCinfo->SourceId == NvRmClockSource_CpuBus) &&
+        NvRmPrivGetClockSourceHandle(NvRmClockSource_CpuBridge))
+    {
+        s_ClockSourceFreq[NvRmClockSource_CpuBridge] = NvRmPrivDividerFreqGet(
+            hRmDevice,
+            NvRmPrivGetClockSourceHandle(NvRmClockSource_CpuBridge)->pInfo.pDivider);
+    }
+}
+
+/*****************************************************************************/
+
+static NvRmSystemBusComplexInfo*
+GetSystemBusComplexHandle(NvRmDeviceHandle hRmDevice)
+{
+    if (s_SystemBusComplex.BusRateOffset == 0)
+    {
+        NvU32 i, m;
+        const NvRmDividerClockInfo* pAhb =
+            NvRmPrivGetClockSourceHandle(NvRmClockSource_Ahb)->pInfo.pDivider;
+        const NvRmDividerClockInfo* pApb =
+            NvRmPrivGetClockSourceHandle(NvRmClockSource_Apb)->pInfo.pDivider;
+        NvOsMemset(&s_SystemBusComplex, 0, sizeof(s_SystemBusComplex));
+
+        // Confirm implied fixed AHB and APB dividers configuration and
+        // fill in other AHB and APB dividers parameters
+        NV_ASSERT(pAhb->Divider == NvRmClockDivider_Integer_1);
+        NV_ASSERT(pAhb->ClkControlField == pAhb->ClkDisableSettings);
+        NV_ASSERT(pApb->Divider == NvRmClockDivider_Integer_1);
+        NV_ASSERT(pApb->ClkControlField == pApb->ClkDisableSettings);
+        NV_ASSERT(pAhb->ClkControlOffset == pApb->ClkControlOffset);
+
+        s_SystemBusComplex.BusRateOffset = pAhb->ClkControlOffset;
+        s_SystemBusComplex.BusClockDisableFields =
+            pAhb->ClkControlField | pApb->ClkControlField;
+
+        s_SystemBusComplex.HclkDivisorFieldShift = pAhb->ClkRateFieldShift;
+        s_SystemBusComplex.HclkDivisorFieldMask = pAhb->ClkRateFieldMask;
+        for (i = 0, m = pAhb->ClkRateFieldMask; (m >> i) != 0; i++);
+        s_SystemBusComplex.HclkDivisorFieldSize = i;
+
+        s_SystemBusComplex.PclkDivisorFieldShift = pApb->ClkRateFieldShift;
+        s_SystemBusComplex.PclkDivisorFieldMask = pApb->ClkRateFieldMask;
+        for (i = 0, m = pApb->ClkRateFieldMask; (m >> i) != 0; i++);
+        s_SystemBusComplex.PclkDivisorFieldSize = i;
+
+        // Comfirm implied VDE divider configuration, and fill in VDE divider
+        // parameters provided System bus complex includes VDE clock; otherwise
+        //  leave all VDE parameters cleared.
+        if (NvRmPrivGetClockSourceHandle(NvRmClockSource_Vbus))
+        {
+            const NvRmDividerClockInfo* pVbus =
+                NvRmPrivGetClockSourceHandle(NvRmClockSource_Vbus)->pInfo.pDivider;
+
+            NV_ASSERT(pVbus->Divider == NvRmClockDivider_Keeper16);
+            NV_ASSERT(pAhb->ClkControlOffset == pVbus->ClkControlOffset);
+
+            s_SystemBusComplex.VclkDividendFieldShift = pVbus->ClkRateFieldShift;
+            s_SystemBusComplex.VclkDividendFieldMask = pVbus->ClkRateFieldMask;
+            for (i = 0, m = pVbus->ClkRateFieldMask; (m >> i) != 0; i++);
+            s_SystemBusComplex.VclkDividendFieldSize = i;
+        }
+    }
+    return &s_SystemBusComplex; 
+}
+
+void
+NvRmPrivBusClockFreqSet(
+    NvRmDeviceHandle hRmDevice,
+    NvRmFreqKHz SystemFreq,
+    NvRmFreqKHz* pVclkFreq,
+    NvRmFreqKHz* pHclkFreq,
+    NvRmFreqKHz* pPclkFreq,
+    NvRmFreqKHz PclkMaxFreq)
+{
+    NvU32 VclkDividend, HclkDivisor, PclkDivisor, reg;
+    NvRmFreqKHz ClkFreq;
+    const NvRmSystemBusComplexInfo* pCinfo =
+        GetSystemBusComplexHandle(hRmDevice);
+
+    NV_ASSERT(hRmDevice);
+    NV_ASSERT(SystemFreq);
+    NV_ASSERT(pHclkFreq && pPclkFreq);
+
+    /*
+     * AHB clock divider: Fout = System Frequency / (n+1). Divider settings
+     * n = System Frequency / Hclk Frequency - 1. Avoid division for extreme
+     * cases of very small, or very large request via direct comparison.
+     */
+    ClkFreq = *pHclkFreq;
+    if ((ClkFreq << pCinfo->HclkDivisorFieldSize) <= SystemFreq)
+    {
+        HclkDivisor = pCinfo->HclkDivisorFieldMask;
+        *pHclkFreq = SystemFreq >> pCinfo->HclkDivisorFieldSize;
+    }
+    else if ((ClkFreq << 1) > SystemFreq)
+    {
+        HclkDivisor = 0;
+        *pHclkFreq = SystemFreq;
+    }
+    else
+    {
+        HclkDivisor = (SystemFreq / ClkFreq) - 1;
+        *pHclkFreq = SystemFreq / (HclkDivisor + 1);
+    }
+    s_ClockSourceFreq[NvRmClockSource_Ahb] = *pHclkFreq;
+
+    /*
+     * APB clock divider: Fout = AHB Frequency / (n+1). Divider settings
+     * n = AHB Frequency / Pclk Frequency - 1. Avoid division for extreme
+     * cases of very small, or very large request via direct comparison.
+     * Check against clock frequency maximum - this the only one bus clock
+     * that may have different (lower) maximum limit.
+     */
+    ClkFreq = *pPclkFreq;
+    NV_ASSERT(ClkFreq <= PclkMaxFreq);
+    if ((ClkFreq << pCinfo->PclkDivisorFieldSize) <= (*pHclkFreq))
+    {
+        PclkDivisor = pCinfo->PclkDivisorFieldMask;
+        *pPclkFreq = (*pHclkFreq) >> pCinfo->PclkDivisorFieldSize;
+        NV_ASSERT(*pPclkFreq <= PclkMaxFreq);
+    }
+    else if ((ClkFreq << 1) > (*pHclkFreq))
+    {
+        PclkDivisor = ((*pHclkFreq) <= PclkMaxFreq)? 0 : 1;
+        *pPclkFreq = (*pHclkFreq) >> PclkDivisor;
+    }
+    else
+    {
+        PclkDivisor = ((*pHclkFreq) / ClkFreq);
+        if ((*pHclkFreq) <= PclkMaxFreq * PclkDivisor)
+            PclkDivisor--;
+        *pPclkFreq = (*pHclkFreq) / (PclkDivisor + 1);
+    }
+    s_ClockSourceFreq[NvRmClockSource_Apb] = *pPclkFreq;
+
+    /*
+     * V-clock divider: Fout = System Frequency * (n + 1) / 2 ^ dividend size.
+     * Divider settings n = (Vclk Frequency << dividend size) / System Frequency.
+     * Do not subtract 1 as integer division would round down, anyway. If VDE
+     * clock is decoupled from the System bus, clear dividend and return 0 kHz.
+     */
+    if (pCinfo->VclkDividendFieldMask)
+    {
+        NV_ASSERT(pVclkFreq);
+        if ((*pVclkFreq) >= SystemFreq)
+        {
+            VclkDividend = pCinfo->VclkDividendFieldMask;
+            *pVclkFreq = SystemFreq;
+        }
+        else
+        {
+            VclkDividend =
+                ((*pVclkFreq) << pCinfo->VclkDividendFieldSize) / (SystemFreq + 1);
+            *pVclkFreq =
+                (SystemFreq * (VclkDividend + 1)) >> pCinfo->VclkDividendFieldSize;
+        }
+        s_ClockSourceFreq[NvRmClockSource_Vbus] = *pVclkFreq;
+    }
+    else
+    {
+        VclkDividend = 0;
+        if (pVclkFreq)
+            *pVclkFreq = 0;
+        s_ClockSourceFreq[NvRmClockSource_Vbus] = 0;
+    }
+    
+    /*
+     * Set bus clocks dividers in bus rate control register.
+     * Always enable all bus clocks.
+     */
+    reg = NV_REGR(hRmDevice, NvRmPrivModuleID_ClockAndReset, 0, pCinfo->BusRateOffset);
+    reg &= ((~pCinfo->BusClockDisableFields) &
+            (~(pCinfo->HclkDivisorFieldMask << pCinfo->HclkDivisorFieldShift)) &
+            (~(pCinfo->PclkDivisorFieldMask << pCinfo->PclkDivisorFieldShift)) &
+            (~(pCinfo->VclkDividendFieldMask << pCinfo->VclkDividendFieldShift)));
+    reg |= ((HclkDivisor << pCinfo->HclkDivisorFieldShift) |
+            (PclkDivisor << pCinfo->PclkDivisorFieldShift) |
+            (VclkDividend << pCinfo->VclkDividendFieldShift));
+    NV_REGW(hRmDevice, NvRmPrivModuleID_ClockAndReset, 0, pCinfo->BusRateOffset, reg);
+}
+
+void
+NvRmPrivBusClockFreqGet(
+    NvRmDeviceHandle hRmDevice,
+    NvRmFreqKHz SystemFreq,
+    NvRmFreqKHz* pVclkFreq,
+    NvRmFreqKHz* pHclkFreq,
+    NvRmFreqKHz* pPclkFreq)
+{
+    NvU32 VclkDividend, HclkDivisor, PclkDivisor, reg;
+    const NvRmSystemBusComplexInfo* pCinfo =
+        GetSystemBusComplexHandle(hRmDevice);
+
+    NV_ASSERT(hRmDevice);
+    NV_ASSERT(SystemFreq);
+    NV_ASSERT(pHclkFreq && pPclkFreq);
+
+    // Get current bus dividers settings
+    reg = NV_REGR(hRmDevice, NvRmPrivModuleID_ClockAndReset, 0, pCinfo->BusRateOffset);
+    NV_ASSERT((reg & pCinfo->BusClockDisableFields) == 0);
+
+    HclkDivisor = (reg >> pCinfo->HclkDivisorFieldShift) & pCinfo->HclkDivisorFieldMask;
+    PclkDivisor = (reg >> pCinfo->PclkDivisorFieldShift) & pCinfo->PclkDivisorFieldMask;
+    VclkDividend = (reg >> pCinfo->VclkDividendFieldShift) & pCinfo->VclkDividendFieldMask;
+
+    /*
+     * AHB clock divider: Fout = System Frequency / (n+1). Avoid division
+     * for extreme cases of min/max divider values.
+     */
+    if (HclkDivisor == 0)
+        *pHclkFreq = SystemFreq;
+    else if (HclkDivisor == pCinfo->HclkDivisorFieldMask)
+        *pHclkFreq = SystemFreq >> pCinfo->HclkDivisorFieldSize;
+    else
+        *pHclkFreq = SystemFreq / (HclkDivisor + 1);
+
+    /*
+     * APB clock divider: Fout = AHB Frequency / (n+1).  Avoid division
+     * for extreme cases of min/max divider values.
+     */
+    if (PclkDivisor == 0)
+        *pPclkFreq = *pHclkFreq;
+    else if (PclkDivisor == pCinfo->PclkDivisorFieldMask)
+        *pPclkFreq = (*pHclkFreq) >> pCinfo->PclkDivisorFieldSize;
+    else
+        *pPclkFreq = (*pHclkFreq) / (PclkDivisor + 1);
+
+    /*
+     * V-clock divider: Fout = System Frequency * (n + 1) / 2 ^ dividend size.
+     * If VDE clock is decoupled from the System bus, return 0 kHz.
+     */
+    if (pCinfo->VclkDividendFieldMask)
+    {
+        NV_ASSERT(pVclkFreq);
+        *pVclkFreq = 
+        (SystemFreq * (VclkDividend + 1)) >> pCinfo->VclkDividendFieldSize;
+    }
+    else if (pVclkFreq)
+        *pVclkFreq = 0;
+}
+
+/*****************************************************************************/
+
+void
+NvRmPrivPllFreqUpdate(
+    NvRmDeviceHandle hRmDevice,
+    const NvRmPllClockInfo* pCinfo)
+{
+    NV_ASSERT(hRmDevice);
+    NV_ASSERT(pCinfo);
+
+    s_ClockSourceFreq[pCinfo->SourceId] =
+        NvRmPrivAp15PllFreqGet(hRmDevice, pCinfo);
+}
+
+void
+NvRmPrivDividerFreqUpdate(
+    NvRmDeviceHandle hRmDevice,
+    const NvRmDividerClockInfo* pCinfo)
+{
+    NV_ASSERT(hRmDevice);
+    NV_ASSERT(pCinfo);
+
+    s_ClockSourceFreq[pCinfo->SourceId] =
+        NvRmPrivDividerFreqGet(hRmDevice, pCinfo);
+}
+
+void
+NvRmPrivDividerSet(
+    NvRmDeviceHandle hRmDevice,
+    const NvRmDividerClockInfo* pCinfo,
+    NvU32 setting)
+{
+    NvU32 reg;
+
+    NV_ASSERT(hRmDevice);
+    NV_ASSERT(pCinfo);
+    NV_ASSERT(pCinfo->ClkControlOffset);
+
+    reg = NV_REGR(
+        hRmDevice, NvRmPrivModuleID_ClockAndReset, 0, pCinfo->ClkControlOffset);
+
+    // Make sure divider is enabled. Update rate field for divider with
+    // variable divisor
+    reg &= (~(pCinfo->ClkControlField));
+    reg |= pCinfo->ClkEnableSettings;
+    if (pCinfo->FixedRateSetting ==  NVRM_VARIABLE_DIVIDER)
+    {
+        reg &= (~(pCinfo->ClkRateFieldMask << pCinfo->ClkRateFieldShift));
+        reg |= ((setting & pCinfo->ClkRateFieldMask) << pCinfo->ClkRateFieldShift);
+    }
+    NV_REGW(hRmDevice, NvRmPrivModuleID_ClockAndReset, 0, pCinfo->ClkControlOffset, reg);
+    NvOsWaitUS(NVRM_CLOCK_CHANGE_DELAY);
+    s_ClockSourceFreq[pCinfo->SourceId] = NvRmPrivDividerFreqGet(hRmDevice, pCinfo);
+}
+
+NvRmFreqKHz
+NvRmPrivDividerFreqGet(
+    NvRmDeviceHandle hRmDevice,
+    const NvRmDividerClockInfo* pCinfo)
+{
+    NvRmFreqKHz DividerKHz;
+    NvU32 reg, n;
+
+    NV_ASSERT(hRmDevice);
+    NV_ASSERT(pCinfo);
+    NV_ASSERT(pCinfo->ClkControlOffset);
+
+    reg = NV_REGR(
+        hRmDevice, NvRmPrivModuleID_ClockAndReset, 0, pCinfo->ClkControlOffset);
+
+    // Return 0 kHz if divider is disabled
+    if ((pCinfo->ClkControlField != 0) &&
+        ((reg & pCinfo->ClkControlField) == pCinfo->ClkDisableSettings))
+    {
+        return 0;
+    }
+    // Determine divider rate setting
+    n = pCinfo->FixedRateSetting;
+    if (n == NVRM_VARIABLE_DIVIDER)
+    {
+        n = ((reg >> pCinfo->ClkRateFieldShift) & pCinfo->ClkRateFieldMask);
+    }
+
+    // Calculate output frequency
+    DividerKHz = s_ClockSourceFreq[pCinfo->InputId];
+    switch (pCinfo->Divider)
+    {
+        case NvRmClockDivider_Keeper16:
+            return ((DividerKHz * (n + 1)) >> 4);
+        case NvRmClockDivider_Skipper16:
+            return ((DividerKHz * (16 - n)) >> 4);
+        case NvRmClockDivider_Fractional_2:
+            n += 2;
+            DividerKHz = DividerKHz << 1;
+            break;
+        case NvRmClockDivider_Integer_1:
+            n += 1;
+            break;
+        case NvRmClockDivider_Integer:
+            break;
+        default:
+            NV_ASSERT(!"Invalid divider type");
+            return 0;
+    }
+    NV_ASSERT(n != 0);
+    return (DividerKHz / n);
+}
+
+
+// Shortcut (this mask can be retrieved from module clock information table)
+#define NVRM_FRACTIONAL_DIVISOR_FIELD_MASK (0xFF)
+
+NvU32
+NvRmPrivFindFreqMinAbove(
+    NvRmClockDivider DividerType,
+    NvRmFreqKHz SourceKHz,
+    NvRmFreqKHz MaxKHz,
+    NvRmFreqKHz* pTargetKHz)
+{
+    NvU32 n;
+    NV_ASSERT(pTargetKHz);
+    NV_ASSERT( ((*pTargetKHz) != 0) && ((*pTargetKHz) <= MaxKHz) );
+    NV_ASSERT(DividerType == NvRmClockDivider_Fractional_2); // only this type
+
+    /*
+     * Get fractional divider setting n for the best target approximation from
+     * the above. Fractional divider: FoutKHz = (2 * FinKHz) / (n + 2)
+     */
+    if ((*pTargetKHz) < SourceKHz)
+    {
+        SourceKHz = SourceKHz << 1;
+        n = SourceKHz / (*pTargetKHz);
+        if (SourceKHz > n * MaxKHz)
+            n++;
+        *pTargetKHz = SourceKHz / n;
+        n = n - 2;
+    }
+    else
+    {
+        n = 0;
+        *pTargetKHz = SourceKHz;
+    }
+    NV_ASSERT(n <= NVRM_FRACTIONAL_DIVISOR_FIELD_MASK);
+    return n;
+}
+
+NvU32
+NvRmPrivFindFreqMaxBelow(
+    NvRmClockDivider DividerType,
+    NvRmFreqKHz SourceKHz,
+    NvRmFreqKHz MaxKHz,
+    NvRmFreqKHz* pTargetKHz)
+{
+    NvU32 n;
+    NV_ASSERT(pTargetKHz);
+    NV_ASSERT( ((*pTargetKHz) != 0) && ((*pTargetKHz) <= MaxKHz) );
+    NV_ASSERT(DividerType == NvRmClockDivider_Fractional_2); // only this type
+
+    /*
+     * Get fractional divider setting n for the best target approximation from
+     * the below. Fractional divider: FoutKHz = (2 * FinKHz) / (n + 2)
+     */
+    if ((*pTargetKHz) < SourceKHz)
+    {
+        SourceKHz = SourceKHz << 1;
+        n = (SourceKHz + (*pTargetKHz) - 1) / (*pTargetKHz);
+        *pTargetKHz = SourceKHz / n;
+        n = n - 2;
+    }
+    else
+    {
+        n = 0;
+        *pTargetKHz = SourceKHz;
+    }
+    NV_ASSERT(n <= NVRM_FRACTIONAL_DIVISOR_FIELD_MASK);
+    return n;
+}
+
+void
+NvRmPrivSelectorClockSet(
+    NvRmDeviceHandle hRmDevice,
+    const NvRmSelectorClockInfo* pCinfo,
+    NvRmClockSource SourceId,
+    NvBool Double)
+{
+    NvU32 i, reg;
+    NvRmFreqKHz SourceFreq;
+    NvU32 SrcIndex = NvRmClockSource_Num; // source index out of valid range
+
+    NV_ASSERT(hRmDevice);
+    NV_ASSERT(pCinfo);
+    NV_ASSERT(pCinfo->SelectorOffset);
+
+    // Find selector index for the specified input clock source
+    for (i = 0; i < NvRmClockSource_Num; i++)
+    {
+        if (pCinfo->Sources[i] == SourceId)
+        {
+            SrcIndex = i;
+            break;
+        }
+    }
+    NV_ASSERT(SrcIndex < NvRmClockSource_Num);
+
+    // Select specified clock source
+    NV_ASSERT(SrcIndex <= pCinfo->SourceFieldMask);
+    reg = NV_REGR(hRmDevice, NvRmPrivModuleID_ClockAndReset, 0, pCinfo->SelectorOffset);
+    reg &= (~(pCinfo->SourceFieldMask << pCinfo->SourceFieldShift));
+    reg |= (SrcIndex << pCinfo->SourceFieldShift);
+    NV_REGW(hRmDevice, NvRmPrivModuleID_ClockAndReset, 0, pCinfo->SelectorOffset, reg);
+    SourceFreq = s_ClockSourceFreq[SourceId];
+
+    // Enable/Disable doubler
+    if (pCinfo->DoublerEnableField != 0)
+    {
+        reg = NV_REGR(hRmDevice, NvRmPrivModuleID_ClockAndReset, 0,
+                      pCinfo->DoublerEnableOffset);
+        if (Double)
+        {
+            reg |= pCinfo->DoublerEnableField;
+            SourceFreq = SourceFreq << 1;
+        }
+        else
+        {
+            reg &= (~pCinfo->DoublerEnableField);
+            SourceFreq = 0; // no clock out if doubler disabled
+        }
+        NV_REGW(hRmDevice, NvRmPrivModuleID_ClockAndReset, 0,
+                pCinfo->DoublerEnableOffset, reg);
+    }
+    s_ClockSourceFreq[pCinfo->SourceId] = SourceFreq;
+}
+
+/*****************************************************************************/
+
+void NvRmPrivParseClockSources(
+    NvRmClockSourceInfo* pDst,
+    NvU32 DestinationTableSize,
+    NvRmClockSourceInfoPtr Src,
+    NvU32 SourceTableSize,
+    NvRmClockSourceType SourceType)
+{
+    NvU32 i;
+    NvRmClockSource id = NvRmClockSource_Invalid;
+    NV_ASSERT(pDst);
+
+    for (i = 0; i < SourceTableSize; i++)
+    {
+        // Bsed on specified source type retrieve source id
+        // from the source table
+        switch (SourceType)
+        {
+            case NvRmClockSourceType_Fixed:
+                id = Src.pFixed[i].SourceId;
+                pDst[id].pInfo.pFixed = &Src.pFixed[i];
+                break;
+            case NvRmClockSourceType_Pll:
+                id = Src.pPll[i].SourceId;
+                pDst[id].pInfo.pPll = &Src.pPll[i];
+                break;
+            case NvRmClockSourceType_Divider:
+                id = Src.pDivider[i].SourceId;
+                pDst[id].pInfo.pDivider = &Src.pDivider[i];
+                break;
+            case NvRmClockSourceType_Core:
+                id = Src.pCore[i].SourceId;
+                pDst[id].pInfo.pCore = &Src.pCore[i];
+                break;
+            case NvRmClockSourceType_Selector:
+                id = Src.pSelector[i].SourceId;
+                pDst[id].pInfo.pSelector = &Src.pSelector[i];
+                break;
+            default:
+                NV_ASSERT(!"Not defined source type");
+        }
+        // Fill in destination table
+        NV_ASSERT((NvU32)id < DestinationTableSize);
+        NV_ASSERT(pDst[id].SourceId == NvRmClockSource_Invalid);
+        pDst[id].SourceId = id;
+        pDst[id].SourceType = SourceType;
+    }
+}
+
+NvRmClockSourceInfo* NvRmPrivGetClockSourceHandle(NvRmClockSource id)
+{
+    NvRmClockSourceInfo* pSource = NULL;
+
+    NV_ASSERT((id != NvRmClockSource_Invalid) && (id < NvRmClockSource_Num));
+    if (s_ClockSourceTable[id].SourceId == id)
+    {
+         pSource = &s_ClockSourceTable[id];
+         NV_ASSERT(pSource->pInfo.pFixed);
+    }
+    return pSource;
+}
+
+NvRmFreqKHz
+NvRmPrivGetClockSourceFreq(NvRmClockSource id)
+{
+    NV_ASSERT(id < NvRmClockSource_Num);
+    return s_ClockSourceFreq[id];
+}
+
+NvRmFreqKHz
+NvRmPowerGetPrimaryFrequency(
+    NvRmDeviceHandle hRmDeviceHandle)
+{
+    return s_ClockSourceFreq[NvRmClockSource_ClkM];
+}
+
+NvBool
+NvRmPrivIsSourceSelectedByModule(
+    NvRmDeviceHandle hRmDevice,
+    NvRmClockSource SourceId,
+    NvRmModuleID ModuleId)
+{
+    NvError Error;
+    NvU32 SourceIndex = 0;
+    NvRmModuleClockInfo* pCinfo;
+    NvRmModuleInstance* pInst = NULL;
+    NV_ASSERT(hRmDevice);
+
+    Error = NvRmPrivGetModuleInstance(hRmDevice, ModuleId, &pInst);
+    if (Error != NvSuccess)
+        return NV_FALSE;     // Module is not present - not using anything
+
+    pCinfo = (NvRmModuleClockInfo*)pInst->ModuleData;
+    if (pCinfo->ClkSourceOffset != 0)
+    {
+        SourceIndex = NV_REGR(
+            hRmDevice, NvRmPrivModuleID_ClockAndReset, 0, pCinfo->ClkSourceOffset);
+        SourceIndex =
+            (SourceIndex >> pCinfo->SourceFieldShift) & pCinfo->SourceFieldMask;
+    }
+    return (pCinfo->Sources[SourceIndex] == SourceId);
+}
+
+NvBool
+NvRmIsFreqRangeReachable(
+    NvRmFreqKHz SourceFreq,
+    NvRmFreqKHz MinFreq,
+    NvRmFreqKHz MaxFreq,
+    NvU32 MaxDivisor)
+{
+    NvU32 divisor;
+    NV_ASSERT(SourceFreq && MaxFreq);
+    NV_ASSERT(MinFreq <= MaxFreq);
+
+    // Determine minimum divisor that satisfies maximum boundary
+    divisor = SourceFreq / MaxFreq;
+    if ((divisor * MaxFreq) < SourceFreq)
+    {
+        divisor += 1;
+    }
+    // The specified range is reachable if minimum divisor is
+    // fits divisor field and satisfies minimum boundary
+    if ((divisor <= MaxDivisor) &&
+        ((divisor * MinFreq) <= SourceFreq))
+    {
+        return NV_TRUE;
+    }
+    return NV_FALSE;
+}
+
+const NvRmModuleClockLimits*
+NvRmPrivGetSocClockLimits(NvRmModuleID Module)
+{
+    NV_ASSERT(Module < NvRmPrivModuleID_Num);
+    return &s_ModuleClockLimits[Module];
+}
+
+void NvRmPrivLockSharedPll(void)
+{
+    NvOsMutexLock(s_hPllMutex);
+}
+
+void NvRmPrivUnlockSharedPll(void)
+{
+    NvOsMutexUnlock(s_hPllMutex);
+}
+
+void NvRmPrivLockModuleClockState(void)
+{
+    NvOsSpinMutexLock(s_hClockMutex);
+}
+
+void NvRmPrivUnlockModuleClockState(void)
+{
+    NvOsSpinMutexUnlock(s_hClockMutex);
+}
+
+/*****************************************************************************/
+/*****************************************************************************/
+
+// PLLC may be selected as a source only for Display, TVO, GPU, and VDE
+// modules. (It is also used for CPU and System/Avp core clocks, controlled
+// by DFS with its own configuration path - no need to specify here) 
+static const NvRmModuleID s_Ap15PllC0UsagePolicy[] =
+{
+    NvRmModuleID_Display,
+    NvRmModuleID_3D,
+    NvRmModuleID_2D,
+    NvRmModuleID_Mpe,
+    NvRmModuleID_Hdmi,
+};
+
+static const NvRmModuleID s_Ap20PllC0UsagePolicy[] =
+{
+    NvRmModuleID_Display,
+    NvRmModuleID_Tvo,
+    NvRmModuleID_3D,
+    NvRmModuleID_2D,
+    NvRmModuleID_Epp,
+    NvRmModuleID_Mpe,
+    NvRmModuleID_Hdmi,
+    NvRmModuleID_Vde
+};
+
+// PLLM may be selected as a source for GPU, UART and VDE modules. (It is also
+// used for EMC, CPU and System/Avp core clocks, controlled by DFS with its
+// own configuration path - no need to specify here) 
+static const NvRmModuleID s_Ap15PllM0UsagePolicy[] =
+{
+    NvRmModuleID_GraphicsHost,
+    NvRmModuleID_Vi,
+    NvRmModuleID_3D,
+    NvRmModuleID_2D,
+    NvRmModuleID_Epp,
+    NvRmModuleID_Mpe,
+    NvRmModuleID_Vde,
+    NvRmModuleID_Uart
+};
+
+// PLLD may be selected as a source only for Display, HDMI, and DSI modules.
+static const NvRmModuleID s_Ap15PllD0UsagePolicy[] =
+{
+    NvRmModuleID_Display,
+    NvRmModuleID_Hdmi,
+    NvRmModuleID_Dsi
+};
+
+// PLLA may be selected as a source only for I2S and SPDIF modules.
+static const NvRmModuleID s_Ap15PllA0UsagePolicy[] =
+{
+    NvRmModuleID_I2s,
+    NvRmModuleID_Spdif,
+};
+
+static const NvRmModuleID*
+GetPolicySourceToModuleList(
+    NvRmDeviceHandle hRmDevice,
+    NvRmClockSource SourceId,
+    NvU32* pListSize)
+{
+    NV_ASSERT(hRmDevice && pListSize);
+
+    // Unless explicitly overwritten, use AP15 policy as a base for all SoCs;
+    // return list of modules that may use specified source
+    switch (SourceId)
+    {
+        case NvRmClockSource_PllC0:
+            if (hRmDevice->ChipId.Id == 0x20)
+            {
+                *pListSize = NV_ARRAY_SIZE(s_Ap20PllC0UsagePolicy);
+                return s_Ap20PllC0UsagePolicy;
+            }
+            *pListSize = NV_ARRAY_SIZE(s_Ap15PllC0UsagePolicy);
+            return s_Ap15PllC0UsagePolicy;
+
+        case NvRmClockSource_PllM0:
+            *pListSize = NV_ARRAY_SIZE(s_Ap15PllM0UsagePolicy);
+            return s_Ap15PllM0UsagePolicy;
+
+        case NvRmClockSource_PllD0:
+            *pListSize = NV_ARRAY_SIZE(s_Ap15PllD0UsagePolicy);
+            return s_Ap15PllD0UsagePolicy;
+
+        case NvRmClockSource_PllA0:
+        case NvRmClockSource_AudioSync:
+            *pListSize = NV_ARRAY_SIZE(s_Ap15PllA0UsagePolicy);
+            return s_Ap15PllA0UsagePolicy;
+
+        default:
+            *pListSize = 0;
+            return NULL;    // No policy - any module may use the source
+    }
+}
+
+NvBool
+NvRmPrivIsSourceProtected(
+    NvRmDeviceHandle hRmDevice,
+    NvRmModuleID Module,
+    NvRmClockSource SourceId)
+{
+    NvU32 i, ListSize;
+    const NvRmModuleID* pModuleList = GetPolicySourceToModuleList(
+        hRmDevice, SourceId, &ListSize);
+
+    if (pModuleList)
+    {
+        // Policy in place - check the module against it
+        NV_ASSERT(ListSize);
+        for (i = 0; i < ListSize; i++)
+        {
+            if (Module == pModuleList[i])
+                return NV_FALSE;
+        }
+        return NV_TRUE;
+    }
+    else
+    {
+        // No policy for this source - just make sure I2C module is
+        // on main clock only
+        if (SourceId != NvRmClockSource_ClkM)
+        {
+            if ((Module == NvRmModuleID_Dvc) ||
+                (Module == NvRmModuleID_I2c))
+                return NV_TRUE;
+        }
+        return NV_FALSE;
+    }
+}
+
+/*****************************************************************************/
+
+void
+NvRmPrivReConfigurePllX(
+    NvRmDeviceHandle hRmDevice,
+    NvRmFreqKHz TargetFreq)
+{
+    NvRmClockSource SourceId;
+    NvRmFreqKHz f = NvRmPrivGetClockSourceFreq(NvRmClockSource_PllX0);
+    const NvRmCoreClockInfo* pCinfo =
+        NvRmPrivGetClockSourceHandle(NvRmClockSource_CpuBus)->pInfo.pCore;
+    NvRmFreqKHz MaxFreq = NvRmPrivGetSocClockLimits(NvRmModuleID_Cpu)->MaxKHz;
+
+    NV_ASSERT(NvRmPrivGetClockSourceHandle(NvRmClockSource_PllX0));
+    NV_ASSERT(TargetFreq <= MaxFreq);
+
+    // Do nothing if current PLLX frequency is below
+    // and close enough to the target
+    if (f <= TargetFreq)                            // if below - DVS-safe
+    {
+        f += (MaxFreq >> pCinfo->DivisorFieldSize); // CPU divider resolution
+        if (f >= TargetFreq)
+            return;
+    }
+
+    /*
+     * If PLLX is in use by CPU switch CPU to back-up PLLP0 source during PLLX
+     * reconfiguration. This is DVS safe as per DFS policy, PLLX is used for
+     * high frequencies above PLLP0 output. In any case, configure PLLX target
+     * frequency, and let the caller to complete CPU clock configuration (PLLX
+     * is used for CPU only, so the caller is always CPU DVFS)
+     */
+    SourceId = NvRmPrivCoreClockSourceGet(hRmDevice, pCinfo);
+    if (SourceId == NvRmClockSource_PllX0)
+    {
+        SourceId = NvRmClockSource_PllP0;
+        f = NvRmPrivGetClockSourceFreq(SourceId);
+        NV_ASSERT(f <= MaxFreq);
+        NV_ASSERT_SUCCESS(NvRmPrivCoreClockConfigure(
+            hRmDevice, pCinfo, MaxFreq, &f, &SourceId));
+    }
+    SourceId = NvRmClockSource_PllX0;
+    NvRmPrivAp15PllConfigureSimple(hRmDevice, SourceId, TargetFreq, &TargetFreq);
+}
+
+/*****************************************************************************/
+
+static void BackupClockSource(
+    NvRmDeviceHandle hRmDevice,
+    NvRmModuleClockInfo* pCinfo,
+    NvRmClockSource BackupSource)
+{
+    NvBool Disabled;
+    NvU32 reg, SourceIndex;
+    NvRmModuleID ModuleId;
+
+    NV_ASSERT(pCinfo); 
+    ModuleId = NVRM_MODULE_ID(pCinfo->Module, pCinfo->Instance);
+
+    // Check if currently clock is disabled
+    NV_ASSERT(pCinfo->ClkEnableOffset);
+    reg = NV_REGR(hRmDevice, NvRmPrivModuleID_ClockAndReset, 0,
+                  pCinfo->ClkEnableOffset);
+    Disabled = ((reg & pCinfo->ClkEnableField) != pCinfo->ClkEnableField);
+
+    // Find backup source index
+    for (SourceIndex = 0; SourceIndex < NvRmClockSource_Num; SourceIndex++)
+    {
+        if (pCinfo->Sources[SourceIndex] == BackupSource)
+            break;
+    }
+    NV_ASSERT(SourceIndex < NvRmClockSource_Num);
+
+    // Switch module to backup source clock. If module clock is disabled,
+    // temporarily enable it.
+    if (Disabled)
+    {
+        NvRmPrivEnableModuleClock(hRmDevice, ModuleId, ModuleClockState_Enable);
+    }
+    reg = NV_REGR(hRmDevice, NvRmPrivModuleID_ClockAndReset, 0,
+                  pCinfo->ClkSourceOffset);
+    reg &= (~(pCinfo->SourceFieldMask << pCinfo->SourceFieldShift));
+    reg |= (SourceIndex << pCinfo->SourceFieldShift);
+    NV_REGW(hRmDevice, NvRmPrivModuleID_ClockAndReset, 0,
+            pCinfo->ClkSourceOffset, reg);
+    NvOsWaitUS(NVRM_CLOCK_CHANGE_DELAY);
+    if (Disabled)
+    {
+        NvRmPrivEnableModuleClock(hRmDevice, ModuleId, ModuleClockState_Disable);
+    }
+}
+
+static void RestoreClockSource(
+    NvRmDeviceHandle hRmDevice,
+    NvRmModuleClockInfo* pCinfo,
+    NvRmModuleClockState* pCstate,
+    NvRmFreqKHz NewSourceFreq)
+{
+    NvU32 reg;
+    NvBool Disabled;
+    NvRmModuleID ModuleId;
+
+    NV_ASSERT(pCinfo && pCstate); 
+    ModuleId = NVRM_MODULE_ID(pCinfo->Module, pCinfo->Instance);
+
+    // Check if currently clock is disabled
+    NV_ASSERT(pCinfo->ClkEnableOffset);
+    reg = NV_REGR(hRmDevice, NvRmPrivModuleID_ClockAndReset, 0,
+                  pCinfo->ClkEnableOffset);
+    Disabled = ((reg & pCinfo->ClkEnableField) != pCinfo->ClkEnableField);
+
+    // Restore module clock source  If module clock is disabled, temporarily
+    // enable it. Update module v-scale requirements.
+    if (Disabled)
+    {
+        NvRmPrivEnableModuleClock(hRmDevice, ModuleId, ModuleClockState_Enable);
+    }
+    NvRmPrivModuleClockSet(hRmDevice, pCinfo, pCstate);
+    if (Disabled)
+    {
+        NvRmPrivEnableModuleClock(hRmDevice, ModuleId, ModuleClockState_Disable);
+    }
+    NvRmPrivModuleVscaleReAttach(hRmDevice,
+        pCinfo, pCstate, pCstate->actual_freq, NewSourceFreq, NV_FALSE);
+}
+
+static void BackupModuleClocks(
+    NvRmDeviceHandle hRmDevice,
+    NvRmModuleID Module,
+    NvRmClockSource UpdatedSource,
+    NvRmClockSource BackupSource)
+{
+    NvU32 j;
+    NvBool SubClock = NV_FALSE;
+    NvRmModuleClockInfo* pCinfo = NULL;
+    NvRmModuleClockState* pCstate = NULL;
+
+    for (j = NvRmModuleGetNumInstances(hRmDevice, Module); j != 0; j--)
+    {
+        NV_ASSERT_SUCCESS(NvRmPrivGetClockState(
+            hRmDevice, NVRM_MODULE_ID(Module, j-1), &pCinfo, &pCstate));
+        do
+        {
+            // If on updated source, switch module to backup source. Note
+            // that module clock state records are preserved and will be used
+            // to restore clock configuration after source update completed.
+            NV_ASSERT(NvRmPrivGetClockSourceFreq(BackupSource) <=
+                      NvRmPrivGetClockSourceFreq(UpdatedSource));
+            if (pCinfo->Sources[pCstate->SourceClock] == UpdatedSource)
+                BackupClockSource(hRmDevice, pCinfo, BackupSource);
+
+            // Check if module subclock should be backed up as well
+            // TODO: boundary check
+            pCinfo++;
+            pCstate++;
+            SubClock = (pCinfo->Module == Module) &&
+                       (pCinfo->Instance == (j - 1));
+        } while (SubClock);
+    }
+}
+
+static void
+RestoreModuleClocks(
+    NvRmDeviceHandle hRmDevice,
+    NvRmModuleID Module,
+    NvRmClockSource UpdatedSource,
+    NvRmFreqKHz NewSourceFreq)
+{
+    NvU32 j;
+    NvRmFreqKHz MaxFreq;
+    NvBool SubClock = NV_FALSE;
+    NvRmModuleClockInfo* pCinfo = NULL;
+    NvRmModuleClockState* pCstate = NULL;
+
+    MaxFreq = NvRmPrivGetSocClockLimits(Module)->MaxKHz;
+    for (j = NvRmModuleGetNumInstances(hRmDevice, Module); j != 0; j--)
+    {
+        NV_ASSERT_SUCCESS(NvRmPrivGetClockState(
+            hRmDevice, NVRM_MODULE_ID(Module, j-1), &pCinfo, &pCstate));
+        do
+        {
+            // Restore updated module clock source, and set divider to get as
+            // close/above to previous frequency as new source output allows.
+            if (pCinfo->Sources[pCstate->SourceClock] == UpdatedSource)
+            {
+                pCstate->Divider = NvRmPrivFindFreqMinAbove(
+                    pCinfo->Divider, NewSourceFreq, MaxFreq, &pCstate->actual_freq);
+                RestoreClockSource(hRmDevice, pCinfo, pCstate, NewSourceFreq);
+            }
+
+            // Check if module subclock should be backed up as well
+            // TODO: boundary check
+            pCinfo++;
+            pCstate++;
+            SubClock = (pCinfo->Module == Module) &&
+                       (pCinfo->Instance == (j - 1));
+        } while (SubClock);
+    }
+}
+
+/*****************************************************************************/
+
+static void PllCBackupModuleClocks(NvRmDeviceHandle hRmDevice)
+{
+    NvU32 i, ListSize;
+    NvRmModuleID Module;
+    const NvRmModuleID* pModuleList = GetPolicySourceToModuleList(
+        hRmDevice, NvRmClockSource_PllC0, &ListSize);
+    NV_ASSERT(pModuleList && ListSize);
+
+    // Check all modules that can use PLLC0 as a source, and switch to PLLP0
+    // as a backcup source
+    for (i = 0; i < ListSize; i++)
+    {
+        Module = pModuleList[i];
+        BackupModuleClocks(
+            hRmDevice, Module, NvRmClockSource_PllC0, NvRmClockSource_PllP0);
+    }
+}
+
+static void
+PllCRestoreModuleClocks(
+    NvRmDeviceHandle hRmDevice,
+    NvRmFreqKHz NewPllCFreq)
+{
+    NvU32 i, ListSize;
+    NvRmModuleID Module;
+    const NvRmModuleID* pModuleList = GetPolicySourceToModuleList(
+        hRmDevice, NvRmClockSource_PllC0, &ListSize);
+    NV_ASSERT(pModuleList && ListSize);
+
+    // Check all modules that can use PLLC0 as a source, and restore source
+    // configuration
+    for (i = 0; i < ListSize; i++)
+    {
+        // Skip display (PLLC is adjusted as part of display configuration)
+        Module = pModuleList[i];
+        if (Module == NvRmModuleID_Display)
+            continue;
+
+        RestoreModuleClocks(
+            hRmDevice, Module, NvRmClockSource_PllC0, NewPllCFreq);
+    }
+}
+
+static NvRmFreqKHz PllCBackupCpuClock(NvRmDeviceHandle hRmDevice)
+{
+    NvRmClockSource SourceId;
+    NvRmFreqKHz OldCpuFreq = 0;
+    const NvRmCoreClockInfo* pCinfo =
+        NvRmPrivGetClockSourceHandle(NvRmClockSource_CpuBus)->pInfo.pCore;
+
+    // If PLLC0 is used as a source for CPU clock - switch CPU to PLLP0, and
+    // return saved CPU clock frequency (to be restored). Note that DVFS uses
+    // PLLC0 as a source only for frequencies above PLLP0
+    SourceId = NvRmPrivCoreClockSourceGet(hRmDevice, pCinfo);
+    if (SourceId == NvRmClockSource_PllC0)
+    {
+        OldCpuFreq = NvRmPrivGetClockSourceFreq(NvRmClockSource_CpuBus);
+        NV_ASSERT(NvRmPrivGetClockSourceFreq(NvRmClockSource_PllP0) <=
+                  OldCpuFreq);
+        NV_ASSERT(NvRmPrivGetClockSourceFreq(NvRmClockSource_PllP0) <=
+                  NvRmPrivGetSocClockLimits(NvRmModuleID_Cpu)->MaxKHz);
+        NvRmPrivCoreClockSet(hRmDevice, pCinfo, NvRmClockSource_PllP0, 0, 0);
+    }
+    return OldCpuFreq; // frequency for restoration, or 0 if no restoration
+}
+
+static void
+PllCRestoreCpuClock(
+    NvRmDeviceHandle hRmDevice,
+    NvRmFreqKHz NewPllCFreq,
+    NvRmFreqKHz OldCpuFreq)
+{
+    // Restore CPU clock as high as new PLLC0 output allows, provoded PLLC0
+    // was used as a source for CPU 
+    if (OldCpuFreq != 0)
+    {
+        NvRmClockSource SourceId = NvRmClockSource_PllC0;
+        NvRmFreqKHz CpuFreq = NV_MIN(NewPllCFreq, OldCpuFreq);
+        const NvRmCoreClockInfo* pCinfo =
+            NvRmPrivGetClockSourceHandle(NvRmClockSource_CpuBus)->pInfo.pCore;
+        NvRmFreqKHz MaxFreq =
+            NvRmPrivGetSocClockLimits(NvRmModuleID_Cpu)->MaxKHz;
+
+        NV_ASSERT_SUCCESS(NvRmPrivCoreClockConfigure(
+            hRmDevice, pCinfo, MaxFreq, &CpuFreq, &SourceId));
+    }
+}
+
+static NvRmFreqKHz PllCBackupSystemClock(NvRmDeviceHandle hRmDevice)
+{
+    NvRmClockSource SourceId;
+    NvRmFreqKHz OldSysFreq = 0;
+    const NvRmCoreClockInfo* pCinfo =
+        NvRmPrivGetClockSourceHandle(NvRmClockSource_SystemBus)->pInfo.pCore;
+
+    // If PLLC1 divider output is used as a source for System clock - switch
+    // System clock to to PLLP2, and return saved System clock frequency (to
+    // be restored). Note that DVFS uses PLLC1 as a source starting with AP20
+    SourceId = NvRmPrivCoreClockSourceGet(hRmDevice, pCinfo);
+    if (SourceId == NvRmClockSource_PllC1)
+    {
+        OldSysFreq = NvRmPrivGetClockSourceFreq(NvRmClockSource_SystemBus);
+        NV_ASSERT(hRmDevice->ChipId.Id >= 0x20);
+        NV_ASSERT(NvRmPrivGetClockSourceFreq(NvRmClockSource_PllP2) <=
+                  NvRmPrivGetSocClockLimits(NvRmPrivModuleID_System)->MaxKHz);
+        NvRmPrivCoreClockSet(hRmDevice, pCinfo, NvRmClockSource_PllP2, 0, 0);
+    }
+    return OldSysFreq; // frequency for restoration, or 0 if no restoration
+}
+
+static void
+PllCRestoreSystemClock(
+    NvRmDeviceHandle hRmDevice,
+    NvRmFreqKHz NewPllCFreq,
+    NvRmFreqKHz OldSysFreq)
+{
+    NvU32 divc1;
+    NvRmFreqKHz SysFreq;
+    const NvRmClockSourceInfo* pSrcCinfo;
+    NvRmClockSource SourceId = NvRmClockSource_PllC1;
+    NvRmFreqKHz MaxFreq =
+        NvRmPrivGetSocClockLimits(NvRmPrivModuleID_System)->MaxKHz;
+
+    // Reconfigure PLLC1 divider at maximum possible frequency
+    SysFreq = MaxFreq;
+    divc1 = NvRmPrivFindFreqMaxBelow(
+        NvRmClockDivider_Fractional_2, NewPllCFreq, MaxFreq, &SysFreq);
+    pSrcCinfo = NvRmPrivGetClockSourceHandle(NvRmClockSource_PllC1);
+    NvRmPrivDividerSet(hRmDevice, pSrcCinfo->pInfo.pDivider, divc1);
+
+    // Restore System clock as high as new PLLC1 output allows, provoded PLLC1
+    // was used as a source for System clock 
+    if (OldSysFreq != 0)
+    {
+        SysFreq = NV_MIN(SysFreq, OldSysFreq);
+        pSrcCinfo = NvRmPrivGetClockSourceHandle(NvRmClockSource_SystemBus);
+        NV_ASSERT_SUCCESS(NvRmPrivCoreClockConfigure(
+            hRmDevice, pSrcCinfo->pInfo.pCore, MaxFreq, &SysFreq, &SourceId));
+        NvRmPrivBusClockInit(hRmDevice, SysFreq);
+    }
+}
+
+NvRmFreqKHz NvRmPrivGetMaxFreqPllC(NvRmDeviceHandle hRmDevice)
+{
+    // PLLC maximum limit is fixed for SoC with dedicated CPU PLLX; otherwise
+    // it is equal to CPU maximum frequency, as PLLC is a primary CPU source.
+    if (NvRmPrivGetClockSourceHandle(NvRmClockSource_PllX0))
+        return NVRM_PLLC_DEFAULT_FREQ_KHZ;
+    else
+        return NvRmPrivGetSocClockLimits(NvRmModuleID_Cpu)->MaxKHz;
+}
+
+/*
+ * PLLC is reconfigured:  
+ * (a) when RM is setting fast clocks during boot/resume from deep sleep,
+ *     provided PLLC is not already in use by any of the display heads
+ * (b) when DDK/ODM is reconfiguring display clock (typically PLLC is required
+ *     for CRT)
+ * 
+ * In both cases core voltage is set at nominal - reconfiguration is DVS-save.
+ * Core clocks that use PLLC: CPU and System bus (starting with AP20) - are
+ * switched to PLLP during reconfiguration and restored afterwards. Module
+ * clocks that use PLLC are backed up to PLLP and then restored as well, with
+ * the exception of display, which does not need restoration in a process of
+ * reconfiguration (case b).
+ */
+void
+NvRmPrivReConfigurePllC(
+    NvRmDeviceHandle hRmDevice,
+    NvRmFreqKHz TargetFreq)
+{
+    NvRmFreqKHz CpuFreq, SysFreq, MaxFreq;
+    const NvRmCoreClockInfo* pCinfo =
+        NvRmPrivGetClockSourceHandle(NvRmClockSource_CpuBus)->pInfo.pCore;
+    NvBool IsHdmi = NvRmIsFixedHdmiKHz(TargetFreq);
+
+    // If maximum PLLC target is requested, and current PLLC output is close
+    // enough - exit without adjusting PLLC (use CPU divider resolution as
+    // "close enough" criteria). For specific PLLC target, find multiple of
+    // target frequency as close as possible to PLLC maximum limit.
+    MaxFreq = NvRmPrivGetMaxFreqPllC(hRmDevice);
+    if (TargetFreq == NvRmFreqMaximum)
+    {
+        TargetFreq = NvRmPrivGetClockSourceFreq(NvRmClockSource_PllC0);
+        if (TargetFreq <= MaxFreq)
+        {
+             TargetFreq += (MaxFreq >> pCinfo->DivisorFieldSize);
+             if (TargetFreq >= MaxFreq)
+                 return;
+        }
+        TargetFreq = MaxFreq;
+    }
+    NV_ASSERT(TargetFreq <= MaxFreq);
+    NV_ASSERT((TargetFreq * NVRM_DISPLAY_DIVIDER_MAX) >= MaxFreq);
+    TargetFreq = (MaxFreq / TargetFreq) * TargetFreq;
+
+    // Backup core and/or module clocks that are using PLLC as a clock source
+    // at the moment. Reconfigure PLLC to the new target, and restore backuped
+    // clocks as close as possible with the new PLLC output frequency
+    CpuFreq = PllCBackupCpuClock(hRmDevice);
+    SysFreq = PllCBackupSystemClock(hRmDevice);
+    PllCBackupModuleClocks(hRmDevice);
+
+    // For 720p or 1080i/1080p HDMI - use fixed PLLC configuration;
+    // for other targets use simple variable configuration
+    if (IsHdmi)
+        NvRmPrivAp15PllConfigureHdmi(
+            hRmDevice, NvRmClockSource_PllC0, &TargetFreq);
+    else
+        NvRmPrivAp15PllConfigureSimple(
+            hRmDevice, NvRmClockSource_PllC0, TargetFreq, &TargetFreq);
+
+    PllCRestoreCpuClock(hRmDevice, TargetFreq, CpuFreq);
+    PllCRestoreSystemClock(hRmDevice, TargetFreq, SysFreq);
+    PllCRestoreModuleClocks(hRmDevice, TargetFreq);
+
+#if !NV_OAL
+        // Resync DFS as PLLC may be reconfigured for display "behind DFS back"
+        if (NvRmPrivGetExecPlatform(hRmDevice) == ExecPlatform_Soc)
+            NvRmPrivDfsResync();
+#endif
+}
+
+void NvRmPrivBoostPllC(NvRmDeviceHandle hRmDevice)
+{
+    // Boost PLLC to maximum output, if it is not used as pixel clock source
+    if (!NvRmPrivIsSourceSelectedByModule(hRmDevice, NvRmClockSource_PllC0,
+            NVRM_MODULE_ID(NvRmModuleID_Display, 0)) &&
+        !NvRmPrivIsSourceSelectedByModule(hRmDevice, NvRmClockSource_PllC0,
+            NVRM_MODULE_ID(NvRmModuleID_Display, 1))
+        )
+        NvRmPrivReConfigurePllC(hRmDevice, NvRmFreqMaximum);
+}
+
+/*****************************************************************************/
+
+
+
diff --git a/arch/arm/mach-tegra/nvrm/core/ap15/nvrm_diag.c b/arch/arm/mach-tegra/nvrm/core/ap15/nvrm_diag.c
new file mode 100644
index 000000000000..f8b1b7322232
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/core/ap15/nvrm_diag.c
@@ -0,0 +1,1376 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include "nvrm_diag.h"
+#include "nvrm_clocks.h"
+#include "nvassert.h"
+#include "nvrm_hwintf.h"
+#include "nvrm_pmu.h"
+#include "nvrm_pmu_private.h"
+#include "nvodm_query_discovery.h"
+#include "ap15rm_private.h"
+#include "ap15/ap15rm_clocks.h"
+#include "ap20/ap20rm_clocks.h"
+#include "ap15/project_relocation_table.h"
+
+#if (NV_DEBUG)
+#define NVRM_DIAG_PRINTF(x)   NvOsDebugPrintf x
+#else
+#define NVRM_DIAG_PRINTF(x)
+#endif
+
+// TODO: remove this define when it is added to re-location table header
+#if !defined(NV_POWERGROUP_INVALID)
+#define NV_POWERGROUP_INVALID (0xFFFF)
+#endif
+
+/*
+ * Holds mapping information between diagnostic module Ids and pointers to
+ * clock information structures
+ */
+typedef struct DiagModuleMappingRec
+{
+    // Index mapping diagnostic module Id into the base pointer to the
+    // respective module clock information structure
+    NvU32 BaseIndex;
+
+    // Total number of the module instances 
+    NvU32 InstancesNum;
+} DiagModuleMapping;
+
+/*
+ * Combines modules diagnostic information
+ */
+typedef struct NvRmDiagModulesRec
+{
+    // Size of module information table
+    NvU32 ModuleClockTableSize;
+
+    // Module clock and reset information table
+    const NvRmModuleClockInfo* ModuleClockTable;
+
+    // Table of module instnace pointers into the information table
+    const NvRmModuleClockInfo** pInstancePtrs;
+
+    // Mapping indexes of module insatances
+    DiagModuleMapping InstancesMap[NvRmDiagModuleID_Num];
+} NvRmDiagModules;
+
+/*
+ * Combines clock sources diagnostic information
+ */
+typedef struct NvRmDiagSourcesRec
+{
+    // Total number of available clock sources
+    NvU32 ClockSourcesNum;
+
+    // Map between clock source IDs and handles
+    NvRmDiagClockSourceHandle hSources[NvRmClockSource_Num]; 
+} NvRmDiagSources;
+
+// RM handle for diagnostic mode
+NvRmDeviceHandle s_hDiagRm = NULL;
+
+/*
+ * Holds mapping information between power rails and module power
+ * groups
+ */
+typedef struct NvRmDiagPowerRailRec
+{
+    // Power rail GUID 
+    NvU64 PowerRailId;
+
+    // List of power group IDs mapped to this rail, terminated
+    // by invalid power group ID
+    NvU32 PowerRailGroups[NV_POWERGROUP_MAX + 1];
+} NvRmDiagPowerRail;
+
+/*
+ * Combines power rails diagnostic information
+ */
+typedef struct NvRmDiagRailsRec
+{
+    // Total number of available module rails
+    NvU32 PowerRailsNum;
+
+    // Power Rails information table
+    const NvRmDiagPowerRail* PowerRailsTable;
+
+    // Combined Module ID and instance of the PMU communication
+    // interface controller
+    NvRmDiagModuleID PmuBusHostDiagId;
+    NvRmModuleID PmuBusHostRmId;
+} NvRmDiagRails;
+
+/*****************************************************************************/
+
+static const NvRmDiagPowerRail s_Ap15PowerRailsTable[] =
+{
+    {
+        NV_VDD_RTC_ODM_ID,
+        {
+            NV_POWERGROUP_AO,
+            NV_POWERGROUP_INVALID
+        }
+    },
+
+    {
+        NV_VDD_CORE_ODM_ID,
+        {
+            NV_POWERGROUP_NPG,
+            NV_POWERGROUP_CPU,
+            NV_POWERGROUP_TD,
+            NV_POWERGROUP_VE, 
+            NV_POWERGROUP_INVALID
+        }
+    },
+
+    {
+        NV_VDD_PLLA_ODM_ID,
+        {
+            NV_POWERGROUP_INVALID
+        }
+    },
+    {
+        NV_VDD_PLLM_ODM_ID,
+        {
+            NV_POWERGROUP_INVALID
+        }
+    },
+    {
+        NV_VDD_PLLP_ODM_ID,
+        {
+            NV_POWERGROUP_INVALID
+        }
+    },
+    {
+        NV_VDD_PLLC_ODM_ID,
+        {
+            NV_POWERGROUP_INVALID
+        }
+    },
+    {
+        NV_VDD_PLLD_ODM_ID,
+        {
+            NV_POWERGROUP_INVALID
+        }
+    },
+    {
+        NV_VDD_PLLU_ODM_ID,
+        {
+            NV_POWERGROUP_INVALID
+        }
+    },
+    {
+        NV_VDD_PLLU1_ODM_ID,
+        {
+            NV_POWERGROUP_INVALID
+        }
+    },
+    {
+        NV_VDD_PLLHDMI_ODM_ID,
+        {
+            NV_POWERGROUP_INVALID
+        }
+    },
+    {
+        NV_VDD_OSC_ODM_ID,
+        {
+            NV_POWERGROUP_INVALID
+        }
+    },
+
+    {
+        NV_VDD_SYS_ODM_ID,
+        {
+            NV_POWERGROUP_INVALID
+        }
+    },
+    {
+        NV_VDD_USB_ODM_ID,
+        {
+            NV_POWERGROUP_INVALID
+        }
+    },
+    {
+        NV_VDD_HDMI_ODM_ID,
+        {
+            NV_POWERGROUP_INVALID
+        }
+    },
+    {
+        NV_VDD_MIPI_ODM_ID,
+        {
+            NV_POWERGROUP_INVALID
+        }
+    },
+    {
+        NV_VDD_LCD_ODM_ID,
+        {
+            NV_POWERGROUP_INVALID
+        }
+    },
+    {
+        NV_VDD_AUD_ODM_ID,
+        {
+            NV_POWERGROUP_INVALID
+        }
+    },
+    {
+        NV_VDD_DDR_ODM_ID,
+        {
+            NV_POWERGROUP_INVALID
+        }
+    },
+    {
+        NV_VDD_NAND_ODM_ID,
+        {
+            NV_POWERGROUP_INVALID
+        }
+    },
+    {
+        NV_VDD_UART_ODM_ID,
+        {
+            NV_POWERGROUP_INVALID
+        }
+    },
+    {
+        NV_VDD_SDIO_ODM_ID,
+        {
+            NV_POWERGROUP_INVALID
+        }
+    },
+    {
+        NV_VDD_VDAC_ODM_ID,
+        {
+            NV_POWERGROUP_INVALID
+        }
+    },
+    {
+        NV_VDD_VI_ODM_ID,
+        {
+            NV_POWERGROUP_INVALID
+        }
+    },
+    {
+        NV_VDD_BB_ODM_ID,
+        {
+            NV_POWERGROUP_INVALID
+        }
+    }
+};
+static const NvU32 s_Ap15PowerRailsTableSize = NV_ARRAY_SIZE(s_Ap15PowerRailsTable);
+
+static const NvRmDiagPowerRail s_Ap20PowerRailsTable[] =
+{
+    {
+        NV_VDD_RTC_ODM_ID,
+        {
+            NV_POWERGROUP_AO,
+            NV_POWERGROUP_INVALID
+        }
+    },
+
+    {
+        NV_VDD_CORE_ODM_ID,
+        {
+            NV_POWERGROUP_NPG,
+            NV_POWERGROUP_TD,
+            NV_POWERGROUP_VE, 
+            NV_POWERGROUP_INVALID
+        }
+    },
+
+    {
+        NV_VDD_CPU_ODM_ID,
+        {
+            NV_POWERGROUP_CPU,
+            NV_POWERGROUP_INVALID
+        }
+    },
+
+    {
+        NV_VDD_PLLA_ODM_ID,
+        {
+            NV_POWERGROUP_INVALID
+        }
+    },
+    {
+        NV_VDD_PLLM_ODM_ID,
+        {
+            NV_POWERGROUP_INVALID
+        }
+    },
+    {
+        NV_VDD_PLLP_ODM_ID,
+        {
+            NV_POWERGROUP_INVALID
+        }
+    },
+    {
+        NV_VDD_PLLC_ODM_ID,
+        {
+            NV_POWERGROUP_INVALID
+        }
+    },
+    {
+        NV_VDD_PLLD_ODM_ID,
+        {
+            NV_POWERGROUP_INVALID
+        }
+    },
+    {
+        NV_VDD_PLLU_ODM_ID,
+        {
+            NV_POWERGROUP_INVALID
+        }
+    },
+    {
+        NV_VDD_PLLU1_ODM_ID,
+        {
+            NV_POWERGROUP_INVALID
+        }
+    },
+    {
+        NV_VDD_PLLHDMI_ODM_ID,
+        {
+            NV_POWERGROUP_INVALID
+        }
+    },
+    {
+        NV_VDD_PLLX_ODM_ID,
+        {
+            NV_POWERGROUP_INVALID
+        }
+    },
+    {
+        NV_VDD_OSC_ODM_ID,
+        {
+            NV_POWERGROUP_INVALID
+        }
+    },
+
+    {
+        NV_VDD_SYS_ODM_ID,
+        {
+            NV_POWERGROUP_INVALID
+        }
+    },
+    {
+        NV_VDD_USB_ODM_ID,
+        {
+            NV_POWERGROUP_INVALID
+        }
+    },
+    {
+        NV_VDD_HDMI_ODM_ID,
+        {
+            NV_POWERGROUP_INVALID
+        }
+    },
+    {
+        NV_VDD_MIPI_ODM_ID,
+        {
+            NV_POWERGROUP_INVALID
+        }
+    },
+    {
+        NV_VDD_LCD_ODM_ID,
+        {
+            NV_POWERGROUP_INVALID
+        }
+    },
+    {
+        NV_VDD_AUD_ODM_ID,
+        {
+            NV_POWERGROUP_INVALID
+        }
+    },
+    {
+        NV_VDD_DDR_ODM_ID,
+        {
+            NV_POWERGROUP_INVALID
+        }
+    },
+    {
+        NV_VDD_NAND_ODM_ID,
+        {
+            NV_POWERGROUP_INVALID
+        }
+    },
+    {
+        NV_VDD_UART_ODM_ID,
+        {
+            NV_POWERGROUP_INVALID
+        }
+    },
+    {
+        NV_VDD_SDIO_ODM_ID,
+        {
+            NV_POWERGROUP_INVALID
+        }
+    },
+    {
+        NV_VDD_VDAC_ODM_ID,
+        {
+            NV_POWERGROUP_INVALID
+        }
+    },
+    {
+        NV_VDD_VI_ODM_ID,
+        {
+            NV_POWERGROUP_INVALID
+        }
+    },
+    {
+        NV_VDD_BB_ODM_ID,
+        {
+            NV_POWERGROUP_INVALID
+        }
+    }
+};
+static const NvU32 s_Ap20PowerRailsTableSize = NV_ARRAY_SIZE(s_Ap20PowerRailsTable);
+
+static const NvU64 s_ApClockSourceNames[] =
+{
+    0x0,
+#define NVRM_CLOCK_SOURCE(A, B, C, D, E, F, G, H, x) \
+((NvU64)((((A)&0xFFULL)<<56) | \
+         (((B)&0xFFULL)<<48) | \
+         (((C)&0xFFULL)<<40) | \
+         (((D)&0xFFULL)<<32) | \
+         (((E)&0xFFULL)<<24) | \
+         (((F)&0xFFULL)<<16) | \
+         (((G)&0xFFULL)<<8)  | \
+         (((H)&0xFFULL))) ),
+    #include "nvrm_clockids.h"
+#undef NVRM_CLOCK_SOURCE
+};
+
+// Power rails diagnostic information
+NvRmDiagRails s_Rails = {0};
+
+// Modules diagnostic information
+NvRmDiagModules s_Modules = {0};
+
+// Clock sources diagnostic information
+NvRmDiagSources s_Sources = {0};
+
+/*****************************************************************************/
+
+static NvRmModuleID MapDiagIdToRmId(NvRmDiagModuleID DiagId);
+
+/*****************************************************************************/
+
+NvError
+NvRmDiagEnable(NvRmDeviceHandle hRmDevice)
+{
+    NvU32 i, index;
+    size_t s;
+    NvError error;
+    void* p = NULL;
+
+    /*
+     * Initialize RM handle, which indicates enabled diagnastic mode
+     */
+    NV_ASSERT(hRmDevice);
+    if (s_hDiagRm != NULL)
+        return NvSuccess;   // Already enabled and initialized
+    s_hDiagRm = hRmDevice;
+
+    /*
+     * Fill in modules information clear instance map, and allocate
+     * module instance pointers table
+     */
+    if (hRmDevice->ChipId.Id == 0x20)
+    {
+        s_Modules.ModuleClockTableSize = g_Ap20ModuleClockTableSize;
+        s_Modules.ModuleClockTable = g_Ap20ModuleClockTable;
+        s_Rails.PowerRailsNum = s_Ap20PowerRailsTableSize;
+        s_Rails.PowerRailsTable = s_Ap20PowerRailsTable;
+    } else
+    {
+        s_Modules.ModuleClockTableSize = g_Ap15ModuleClockTableSize;
+        s_Modules.ModuleClockTable = g_Ap15ModuleClockTable;
+        s_Rails.PowerRailsNum = s_Ap15PowerRailsTableSize;
+        s_Rails.PowerRailsTable = s_Ap15PowerRailsTable;
+    }
+
+    s_Rails.PmuBusHostDiagId = NvRmDiagModuleID_Dvc;  // Default for AP15
+
+
+    NV_ASSERT(s_Modules.ModuleClockTableSize);
+
+    NvOsMemset(s_Modules.InstancesMap, 0, sizeof(s_Modules.InstancesMap));
+    s = sizeof(NvRmModuleClockInfo*) * s_Modules.ModuleClockTableSize;
+    p = NvOsAlloc(s);
+    if (!p)
+    {
+        error = NvError_InsufficientMemory;
+        goto failed;
+    }
+    NvOsMemset(p, 0, s);
+    s_Modules.pInstancePtrs = p;
+
+    /*
+     * Parse module clock/reset information table and fill in mapping arrays.
+     * The table lists all valid (present) modules and only valid modules.
+     */
+    // 1st pass - count module instances
+    for (i = 0; i < s_Modules.ModuleClockTableSize; i++)
+    {
+        NvRmDiagModuleID id = s_Modules.ModuleClockTable[i].DiagModuleID;
+        NV_ASSERT((0 < id) && (id < NvRmDiagModuleID_Num));
+        s_Modules.InstancesMap[id].InstancesNum++; 
+    }
+
+    // 2nd pass - fill in mapping indexes
+    for (index = 0, i = 0; i < NvRmDiagModuleID_Num; i++)
+    {
+        DiagModuleMapping* pMapping = &s_Modules.InstancesMap[i];
+        if (pMapping->InstancesNum != 0)
+        {
+            pMapping->BaseIndex = index;
+            index += pMapping->InstancesNum;
+            NV_ASSERT(index <= s_Modules.ModuleClockTableSize);
+        }
+    }
+
+    // 3rd pass - fill in instance pointers
+    for (i = 0; i < s_Modules.ModuleClockTableSize; i++)
+    {
+        DiagModuleMapping* pMapping =
+            &s_Modules.InstancesMap[s_Modules.ModuleClockTable[i].DiagModuleID];
+        NvU32 instance = s_Modules.ModuleClockTable[i].Instance;
+        index = pMapping->BaseIndex + instance;
+
+        NV_ASSERT(instance < pMapping->InstancesNum);
+        NV_ASSERT(s_Modules.pInstancePtrs[index] == NULL);
+
+        s_Modules.pInstancePtrs[index] = &s_Modules.ModuleClockTable[i];
+    }
+
+    // Convert PMU Host diagnostic ID to common RM ID
+    s_Rails.PmuBusHostRmId = MapDiagIdToRmId(s_Rails.PmuBusHostDiagId);
+
+    /*
+     * Parse clock sources information table and map clock source IDs
+     * to handles. Count total available sources.
+     */
+    NvOsMemset(s_Sources.hSources, 0, sizeof(s_Sources.hSources));
+    for (s_Sources.ClockSourcesNum = 0, i = 1; i < NvRmClockSource_Num; i++)
+    {
+        s_Sources.hSources[i] = NvRmPrivGetClockSourceHandle(i);
+        if (s_Sources.hSources[i] != NULL)
+            s_Sources.ClockSourcesNum++;
+    }
+
+    // Make sure DFS is not running
+    NvRmDfsSetState(s_hDiagRm, NvRmDfsRunState_Stopped);
+    return NvSuccess;
+
+failed:
+    NvOsFree(p);
+    NvOsMemset(&s_Modules, 0, sizeof(s_Modules));
+    NvOsMemset(&s_Sources, 0, sizeof(s_Sources));
+    s_hDiagRm = NULL;
+    return error;
+}
+
+/*****************************************************************************/
+
+NvError
+NvRmDiagListModules(
+    NvU32* pListSize,
+    NvRmDiagModuleID* pIdList)
+{
+    NvU32 ModulesNum, i;
+
+    NV_ASSERT(pListSize);
+    NV_ASSERT(pIdList);
+
+    if (s_hDiagRm == NULL)
+    {
+        return NvError_NotInitialized;
+    }
+    ModulesNum = s_Modules.ModuleClockTableSize;
+
+    // Return total number of modules if no room for the output list
+    if ((*pListSize) == 0)
+    {
+        *pListSize = ModulesNum;
+        return NvSuccess;
+    }
+
+    // Return modules list (min of requested and total size)
+    if ((*pListSize) > ModulesNum)
+    {
+        (*pListSize) = ModulesNum;
+    }
+    for (i = 0; i < (*pListSize); i++, pIdList++)
+    {
+        const NvRmModuleClockInfo* pCinfo = &s_Modules.ModuleClockTable[i];
+        *pIdList = NVRM_DIAG_MODULE(pCinfo->DiagModuleID, pCinfo->Instance);
+    }
+    return NvSuccess;
+}
+
+NvError
+NvRmDiagListClockSources(
+    NvU32* pListSize,
+    NvRmDiagClockSourceHandle* phSourceList)
+{
+    NvU32 SourcesNum, i;
+    NV_ASSERT(pListSize);    
+    NV_ASSERT(phSourceList);
+
+    if (s_hDiagRm == NULL)
+    {
+        return NvError_NotInitialized;
+    }
+
+    // Return total number of sources if no room for the output list
+    if ((*pListSize) == 0)
+    {
+        *pListSize = s_Sources.ClockSourcesNum;
+        return NvSuccess;
+    }
+
+    // Return sources list (min of requested and total size)
+    for (SourcesNum = 0, i = 0; i < NvRmClockSource_Num; i++)
+    {
+        NvRmDiagClockSourceHandle hSource = s_Sources.hSources[i];
+        if (hSource != NULL)
+        {
+            SourcesNum++;
+            *(phSourceList++) = hSource;
+            if (SourcesNum >= (*pListSize))
+                    break;
+        }
+    }
+    *pListSize = SourcesNum;
+    return NvSuccess;
+}
+
+/*****************************************************************************/
+
+NvError
+NvRmDiagModuleListClockSources(
+    NvRmDiagModuleID id,
+    NvU32 * pListSize,
+    NvRmDiagClockSourceHandle* phSourceList)
+{
+    NvU32 SourcesNum, i;
+    const NvRmModuleClockInfo* pCinfo = NULL;
+    NvU32 Instance = NVRM_DIAG_MODULE_INSTANCE(id);
+    NvRmDiagModuleID Module = NVRM_DIAG_MODULE_ID(id);
+
+    NV_ASSERT(pListSize);    
+    NV_ASSERT(phSourceList);
+
+    if (s_hDiagRm == NULL)
+    {
+        return NvError_NotInitialized;
+    }
+
+    // Verify module id and get module info
+    NV_ASSERT((Module < NvRmDiagModuleID_Num) &&
+        (Instance < s_Modules.InstancesMap[Module].InstancesNum));
+    pCinfo =
+        s_Modules.pInstancePtrs[s_Modules.InstancesMap[Module].BaseIndex + Instance];
+
+    /*
+     * Return total number of module sources if no room for the output list,
+     * otherwise return module sources list (min of requested and total size)
+     */
+    for (SourcesNum = 0, i = 0; i < NvRmClockSource_Num; i++)
+    {
+        NvRmClockSource source = pCinfo->Sources[i];
+        NV_ASSERT(source < NvRmClockSource_Num);
+        if (source != NvRmClockSource_Invalid)
+        {
+            SourcesNum++;
+            if ((*pListSize) != 0)
+            {
+                *phSourceList = s_Sources.hSources[source];
+                NV_ASSERT(*phSourceList);
+                phSourceList++;
+                if (SourcesNum >= (*pListSize))
+                    break;
+            }
+        }
+    }
+    *pListSize = SourcesNum;
+    return NvSuccess;
+}
+
+NvError
+NvRmDiagModuleClockEnable(
+    NvRmDiagModuleID id,
+    NvBool enable)
+{
+    NvU32 reg, offset;
+    const NvRmModuleClockInfo* pCinfo = NULL;
+    NvU32 Instance = NVRM_DIAG_MODULE_INSTANCE(id);
+    NvRmDiagModuleID Module = NVRM_DIAG_MODULE_ID(id);
+
+    if (s_hDiagRm == NULL)
+    {
+        return NvError_NotInitialized;
+    }
+
+    // Verify module id and get module info
+    NV_ASSERT((Module < NvRmDiagModuleID_Num) &&
+        (Instance < s_Modules.InstancesMap[Module].InstancesNum));
+    pCinfo =
+        s_Modules.pInstancePtrs[s_Modules.InstancesMap[Module].BaseIndex + Instance];
+
+    // Set/Clear clock control bit(s), if any
+    if (pCinfo->ClkEnableField != 0)
+    {
+        offset = pCinfo->ClkEnableOffset;
+        NV_ASSERT(offset);
+        reg = NV_REGR(s_hDiagRm, NvRmPrivModuleID_ClockAndReset, 0, offset);
+        reg = enable ?
+            (reg | pCinfo->ClkEnableField) : (reg & (~ pCinfo->ClkEnableField));
+        NV_REGW(s_hDiagRm, NvRmPrivModuleID_ClockAndReset, 0, offset, reg);
+    }
+    return NvSuccess;
+}
+
+NvError
+NvRmDiagModuleClockConfigure(
+    NvRmDiagModuleID id,
+    NvRmDiagClockSourceHandle hSource,
+    NvU32 divider,
+    NvBool Source1st)
+{
+    NvU32 reg, offset, SrcIndex;
+    const NvRmModuleClockInfo* pCinfo = NULL;
+    NvU32 Instance = NVRM_DIAG_MODULE_INSTANCE(id);
+    NvRmDiagModuleID Module = NVRM_DIAG_MODULE_ID(id);
+
+    if (s_hDiagRm == NULL)
+    {
+        return NvError_NotInitialized;
+    }
+    
+    // Verify source handle, module id, and get module info
+    NV_ASSERT((hSource != NULL) &&
+        (Module < NvRmDiagModuleID_Num) &&
+        (Instance < s_Modules.InstancesMap[Module].InstancesNum));
+    pCinfo =
+        s_Modules.pInstancePtrs[s_Modules.InstancesMap[Module].BaseIndex + Instance];
+
+    /*
+     * Find source index for the specified module and source handle. If not
+     * found report invalid handle. If module has fixed clock source and no
+     * divider, return success.
+     */
+    for (SrcIndex = 0; SrcIndex < NvRmClockSource_Num; SrcIndex++)
+    {
+        if (hSource->SourceId == pCinfo->Sources[SrcIndex])
+            break;
+    }
+    NV_ASSERT(SrcIndex != NvRmClockSource_Num);
+    if ((pCinfo->SourceFieldMask == 0) && (pCinfo->DivisorFieldMask == 0))
+    {
+        return NvSuccess; 
+    }
+    NV_ASSERT(SrcIndex <= pCinfo->SourceFieldMask);
+
+    /*
+    * Adjust divider valuse: if module divider is not fractional, shift out
+    * half step bit. In any case truncate high divider bits to fit module
+    * divider field.
+    */
+    if (pCinfo->Divider != NvRmClockDivider_Fractional_2)
+    {
+        divider >>= 1;
+    }
+    divider &= pCinfo->DivisorFieldMask;
+
+    /*
+     * Update clock control register. The order of source and divider fields
+     * update is specified by the caller. Insert delay between the updates.
+     */
+    offset = pCinfo->ClkSourceOffset;
+    NV_ASSERT(offset);
+    reg = NV_REGR(s_hDiagRm, NvRmPrivModuleID_ClockAndReset, 0, offset);
+    if (Source1st)
+    {
+        reg &= (~(pCinfo->SourceFieldMask << pCinfo->SourceFieldShift));
+        reg |= (SrcIndex << pCinfo->SourceFieldShift);
+        NV_REGW(s_hDiagRm, NvRmPrivModuleID_ClockAndReset, 0, offset, reg);
+        NvOsWaitUS(NVRM_CLOCK_CHANGE_DELAY);
+    }
+    if (pCinfo->Divider != NvRmClockDivider_None)
+    {
+        reg &= (~(pCinfo->DivisorFieldMask << pCinfo->DivisorFieldShift));
+        reg |= (divider << pCinfo->DivisorFieldShift);
+        NV_REGW(s_hDiagRm, NvRmPrivModuleID_ClockAndReset, 0, offset, reg);
+        NvOsWaitUS(NVRM_CLOCK_CHANGE_DELAY);
+    }
+    if (!Source1st)
+    {
+        reg &= (~(pCinfo->SourceFieldMask << pCinfo->SourceFieldShift));
+        reg |= (SrcIndex << pCinfo->SourceFieldShift);
+        NV_REGW(s_hDiagRm, NvRmPrivModuleID_ClockAndReset, 0, offset, reg);
+        NvOsWaitUS(NVRM_CLOCK_CHANGE_DELAY);
+    }
+    return NvSuccess;
+}
+
+NvError
+NvRmDiagModuleReset(
+    NvRmDiagModuleID id,
+    NvBool KeepAsserted)
+{
+    NvU32 reg, offset;
+    const NvRmModuleClockInfo* pCinfo = NULL;
+    NvU32 Instance = NVRM_DIAG_MODULE_INSTANCE(id);
+    NvRmDiagModuleID Module = NVRM_DIAG_MODULE_ID(id);
+
+    if (s_hDiagRm == NULL)
+    {
+        return NvError_NotInitialized;
+    }
+
+    // Verify module id and get module info
+    NV_ASSERT((Module < NvRmDiagModuleID_Num) &&
+        (Instance < s_Modules.InstancesMap[Module].InstancesNum));
+    pCinfo =
+        s_Modules.pInstancePtrs[s_Modules.InstancesMap[Module].BaseIndex + Instance];
+
+    /*
+     * Assert reset bit and keep it asserted if requested by the caller.
+     * Otherwise de-assert reset after the delay.
+     */
+    offset = pCinfo->ClkResetOffset;
+    NV_ASSERT(offset);
+    reg = NV_REGR(s_hDiagRm, NvRmPrivModuleID_ClockAndReset, 0, offset);
+    reg |= pCinfo->ClkResetField;
+    NV_REGW(s_hDiagRm, NvRmPrivModuleID_ClockAndReset, 0, offset, reg);
+    if (!KeepAsserted)
+    {
+        NvOsWaitUS(NVRM_RESET_DELAY);
+        reg &= (~(pCinfo->ClkResetField));
+        NV_REGW(s_hDiagRm, NvRmPrivModuleID_ClockAndReset, 0, offset, reg);
+    }
+    return NvSuccess;
+}
+
+/*****************************************************************************/
+
+NvU64 NvRmDiagClockSourceGetName(
+    NvRmDiagClockSourceHandle hSource)
+{
+    if ((s_hDiagRm == NULL) ||
+        (hSource == NULL) ||
+        (hSource->SourceId == NvRmClockSource_Invalid) ||
+        (hSource->SourceId >= NvRmClockSource_Num))
+    {
+        return 0;
+    }
+    return s_ApClockSourceNames[hSource->SourceId];
+}
+
+NvRmDiagClockSourceType
+NvRmDiagClockSourceGetType(NvRmDiagClockSourceHandle hSource)
+{
+    if ((s_hDiagRm == NULL) || (hSource == NULL))
+    {
+        return 0;
+    }
+    // Map RM source types to diagnostic source types
+    switch (hSource->SourceType)
+    {
+        case NvRmClockSourceType_Fixed:
+            return NvRmDiagClockSourceType_Oscillator;
+        case NvRmClockSourceType_Pll:
+            return NvRmDiagClockSourceType_Pll;
+        case NvRmClockSourceType_Divider:
+        case NvRmClockSourceType_Core:
+        case NvRmClockSourceType_Selector:
+            return NvRmDiagClockSourceType_Scaler;
+        default:
+            NV_ASSERT(!"Invalid source type");
+            return 0;
+    }
+}
+
+// TODO: does diagnostic scripts really need these details on scaler types?
+NvRmDiagClockScalerType
+NvRmDiagClockSourceGetScaler(NvRmDiagClockSourceHandle hSource)
+{
+    if ((s_hDiagRm == NULL) || (hSource == NULL))
+    {
+        return 0;
+    }
+    // Map RM divider types to diagnostic scaler types
+    switch (hSource->SourceType)
+    {
+        case NvRmClockSourceType_Fixed:
+        case NvRmClockSourceType_Pll:
+            return NvRmDiagClockScalerType_NoScaler;
+        case NvRmClockSourceType_Divider:
+            switch (hSource->pInfo.pDivider->Divider)
+            {
+                case NvRmClockDivider_Keeper16:
+                case NvRmClockDivider_Skipper16:
+                    return NvRmDiagClockScalerType_Divider_M_16;
+                case NvRmClockDivider_Fractional_2:
+                case NvRmClockDivider_Integer_1:
+                case NvRmClockDivider_Integer:
+                    return NvRmDiagClockScalerType_Divider_1_N;
+                default:
+                    NV_ASSERT(!"Invalid divider type");
+                    return 0;
+            }
+        case NvRmClockSourceType_Core:
+            return NvRmDiagClockScalerType_Divider_M_N;
+        case NvRmClockSourceType_Selector:
+            return NvRmDiagClockScalerType_Doubler;
+        default:
+            NV_ASSERT(!"Invalid source type");
+            return 0;
+    }
+}
+
+NvError
+NvRmDiagClockSourceListSources( 
+    NvRmDiagClockSourceHandle hSource,
+    NvU32* pListSize,
+    NvRmDiagClockSourceHandle * phSourceList)
+{
+    NvRmClockSource source = NvRmClockSource_Invalid;
+    NvRmClockSource* Sources = NULL;
+
+    NV_ASSERT(pListSize);    
+    NV_ASSERT(phSourceList);
+
+    if (s_hDiagRm == NULL)
+    {
+        return NvError_NotInitialized;
+    }
+    NV_ASSERT((hSource != NULL) &&
+        (hSource->SourceId != NvRmClockSource_Invalid) &&
+        (hSource->SourceId < NvRmClockSource_Num));
+
+    switch (hSource->SourceType)
+    {
+        // Get input clock ID for single-input clock sources;
+        // (may be invalid for primary sources)
+        case NvRmClockSourceType_Fixed:
+            source = hSource->pInfo.pFixed->InputId;
+            break;
+        case NvRmClockSourceType_Pll:
+            source = hSource->pInfo.pPll->InputId;
+            break;
+        case NvRmClockSourceType_Divider:
+            source = hSource->pInfo.pDivider->InputId;
+            break;
+        // Get pointer to the source array for core and selector sources
+        // (must be valid)
+        case NvRmClockSourceType_Core:
+            Sources = hSource->pInfo.pCore->Sources;
+            NV_ASSERT(Sources);
+            break;
+        case NvRmClockSourceType_Selector:
+            Sources = hSource->pInfo.pSelector->Sources;
+            NV_ASSERT(Sources);
+            break;
+        default:
+            NV_ASSERT(!"Invalid source type");
+    }
+    if (Sources != NULL)
+    {
+        // Return total number of input sources if no room for the output list,
+        // otherwise return sources list (min of requested and total size)
+        NvU32 SourcesNum, i; 
+        for (SourcesNum = 0, i = 0; i < NvRmClockSource_Num; i++)
+        {
+            NvRmClockSource source = Sources[i];
+            NV_ASSERT(source < NvRmClockSource_Num);
+            if (source != NvRmClockSource_Invalid)
+            {
+                SourcesNum++;
+                if ((*pListSize) != 0)
+                {
+                    *phSourceList = s_Sources.hSources[source];
+                    NV_ASSERT(*phSourceList);
+                    phSourceList++;
+                    if (SourcesNum >= (*pListSize))
+                        break;
+                }
+            }
+        }
+        *pListSize = SourcesNum;
+    }
+    else if (source != NvRmClockSource_Invalid)
+    {
+        //Only one input source is available. Return the resepctive handle
+        // if requested.
+        NV_ASSERT(source < NvRmClockSource_Num);
+        if ((*pListSize) != 0)
+            *phSourceList = s_Sources.hSources[source];
+        *pListSize = 1;
+    }
+    else
+    {
+        // Primary source (e.g., oscillator). No (= zero) input sources.
+        *pListSize = 0;
+    }
+    return NvSuccess;
+}
+
+/*****************************************************************************/
+
+NvU32 NvRmDiagOscillatorGetFreq(NvRmDiagClockSourceHandle hOscillator)
+{
+
+    if ((s_hDiagRm == NULL) || (hOscillator == NULL) ||
+        (hOscillator->SourceId == NvRmClockSource_Invalid) ||
+        (hOscillator->SourceType != NvRmClockSourceType_Fixed))
+    {
+        return 0;
+    }
+    return NvRmPrivGetClockSourceFreq(hOscillator->SourceId);
+}
+
+NvError
+NvRmDiagPllConfigure( 
+    NvRmDiagClockSourceHandle hPll,
+    NvU32 M,
+    NvU32 N,
+    NvU32 P)
+{
+    if (s_hDiagRm == NULL)
+    {
+        return NvError_NotInitialized;
+    }
+    NV_ASSERT((hPll != NULL) &&
+        (hPll->SourceId != NvRmClockSource_Invalid) &&
+        (hPll->SourceType == NvRmClockSourceType_Pll));
+
+    NvRmPrivAp15PllSet(s_hDiagRm, hPll->pInfo.pPll, M, N, P, (NvU32)-1,
+                       0, 0, NV_TRUE, NvRmPllConfigFlags_Override);
+    return NvSuccess;
+}
+
+NvError
+NvRmDiagClockScalerConfigure( 
+    NvRmDiagClockSourceHandle hScaler,
+    NvRmDiagClockSourceHandle hInput,
+    NvU32 M,
+    NvU32 N)
+{
+    NvU32 setting = 0;
+
+    if (s_hDiagRm == NULL)
+    {
+        return NvError_NotInitialized;
+    }
+    NV_ASSERT(hScaler != NULL);
+
+    switch (hScaler->SourceType)
+    {
+        case NvRmClockSourceType_Divider:
+            switch (hScaler->pInfo.pDivider->Divider)
+            {
+                case NvRmClockDivider_Keeper16:
+                    setting = M >> 1;
+                    break;
+                case NvRmClockDivider_Skipper16:
+                    setting = (~(M >> 1));
+                    break;
+                case NvRmClockDivider_Fractional_2:
+                    setting = N;
+                    break;
+                case NvRmClockDivider_Integer_1:
+                case NvRmClockDivider_Integer:
+                    setting = N >> 1;
+                    break;
+                default:
+                    NV_ASSERT(!"Invalid divider type");
+            }
+            NvRmPrivDividerSet(s_hDiagRm, hScaler->pInfo.pDivider, setting);
+            return NvSuccess;
+
+        case NvRmClockSourceType_Core:
+            NvRmPrivCoreClockSet(s_hDiagRm, hScaler->pInfo.pCore,
+                                        hInput->SourceId, (M >> 1), (N >> 1));
+            break;
+        case NvRmClockSourceType_Selector:
+            NvRmPrivSelectorClockSet(s_hDiagRm, hScaler->pInfo.pSelector,
+                                         hInput->SourceId, (M != 0));
+            break;
+        case NvRmClockSourceType_Pll:
+        case NvRmClockSourceType_Fixed:
+            NV_ASSERT(!" Diag Clock Scaler Config: illegal clock source. ");
+            break;
+        default:
+            NV_ASSERT(!"Invalid source type");
+            break;
+    }
+    return NvSuccess;
+}
+
+/*****************************************************************************/
+
+/*
+ * Gets power group for the specified module if it is one of system modules, not
+ * present in the relocation table. Otherwise, returns NV_POWERGROUP_INVALID.
+ */
+static NvU32
+DiagGetSystemModulePowerGroup(const NvRmModuleClockInfo* pCinfo);
+
+static NvU32
+DiagGetSystemModulePowerGroup(const NvRmModuleClockInfo* pCinfo)
+{
+    NvU32 PowerGroup = NV_POWERGROUP_INVALID;
+    switch (pCinfo->Module)
+    {
+        case NvRmModuleID_CacheMemCtrl:
+            if (pCinfo->Instance == 0)
+                break; // CPU cache controller is present
+        // fall through if AVP cache controller
+        case NvRmModuleID_Invalid:
+        case NvRmPrivModuleID_System:
+        case NvRmModuleID_Avp:
+            PowerGroup = NV_POWERGROUP_NPG;
+            break;
+        case NvRmModuleID_Cpu:
+            PowerGroup = NV_POWERGROUP_CPU;
+            break;
+        default:
+            break;
+    }
+    return PowerGroup;
+}
+
+NvError
+NvRmDiagListPowerRails(
+    NvU32* pListSize,
+    NvRmDiagPowerRailHandle* phRailList)
+{
+    NvU32 RailsNum, i;
+
+    NV_ASSERT(pListSize);
+    NV_ASSERT(phRailList);
+
+    if (s_hDiagRm == NULL)
+    {
+        return NvError_NotInitialized;
+    }
+    RailsNum = s_Rails.PowerRailsNum;
+
+    // Return total number of rails if no room for the output list
+    if ((*pListSize) == 0)
+    {
+        *pListSize = RailsNum;
+        return NvSuccess;
+    }
+
+    // Return rails list (min of requested and total size)
+    if ((*pListSize) > RailsNum)
+    {
+        (*pListSize) = RailsNum;
+    }
+    for (i = 0; i < (*pListSize); i++, phRailList++)
+    {
+        *phRailList = (NvRmDiagPowerRailHandle)&s_Rails.PowerRailsTable[i];
+    }
+    return NvSuccess;
+}
+
+NvU64
+NvRmDiagPowerRailGetName(NvRmDiagPowerRailHandle hRail)
+{
+    if ((s_hDiagRm == NULL) || (hRail == NULL))
+    {
+        return 0;
+    }
+    return hRail->PowerRailId;
+}
+
+NvError
+NvRmDiagModuleListPowerRails(
+    NvRmDiagModuleID id,
+    NvU32* pListSize,
+    NvRmDiagPowerRailHandle* phRailList)
+{
+
+    NvU32 ModulePowerGroup, i;
+    const NvRmDiagPowerRail* pRail = NULL;
+    const NvRmModuleClockInfo* pCinfo = NULL;
+    NvU32 Instance = NVRM_DIAG_MODULE_INSTANCE(id);
+    NvRmDiagModuleID Module = NVRM_DIAG_MODULE_ID(id);
+
+    NV_ASSERT(pListSize);    
+    NV_ASSERT(phRailList);
+
+    if (s_hDiagRm == NULL)
+    {
+        return NvError_NotInitialized;
+    }
+
+    // Verify module id
+    NV_ASSERT((Module < NvRmDiagModuleID_Num) &&
+        (Instance < s_Modules.InstancesMap[Module].InstancesNum));
+
+    // One rail per module; just return if no room to return handle
+    if ((*pListSize) == 0)
+    {
+        *pListSize = 1;
+        return NvSuccess;
+    }
+
+    // Get module power group
+    pCinfo =
+        s_Modules.pInstancePtrs[s_Modules.InstancesMap[Module].BaseIndex + Instance];
+    ModulePowerGroup = DiagGetSystemModulePowerGroup(pCinfo);
+    if (ModulePowerGroup == NV_POWERGROUP_INVALID)
+    {
+        NvRmModuleInstance* pInst = NULL;
+        NV_ASSERT_SUCCESS(NvRmPrivGetModuleInstance(
+            s_hDiagRm, NVRM_MODULE_ID(pCinfo->Module, pCinfo->Instance), &pInst));
+        ModulePowerGroup = pInst->DevPowerGroup;
+    }
+    NV_ASSERT(ModulePowerGroup != NV_POWERGROUP_INVALID);
+
+    // Find the power rail for the group
+    for (i = 0; i < s_Rails.PowerRailsNum; i++)
+    {
+        const NvU32* pPowerGroup = s_Rails.PowerRailsTable[i].PowerRailGroups;
+        while ((*pPowerGroup) != NV_POWERGROUP_INVALID)
+        {
+            if ((*pPowerGroup) == ModulePowerGroup)
+            {
+                pRail = &s_Rails.PowerRailsTable[i];
+                break;
+            }
+            pPowerGroup++;
+            NV_ASSERT(pPowerGroup < (s_Rails.PowerRailsTable[i].PowerRailGroups +
+                      NV_ARRAY_SIZE(s_Rails.PowerRailsTable[i].PowerRailGroups)));
+        }
+        if (pRail)
+            break;
+    }
+
+    // Return power rail found
+    NV_ASSERT(pRail);
+    *phRailList = (NvRmDiagPowerRailHandle)pRail;
+    *pListSize = 1;
+    return NvSuccess;
+}
+
+NvError
+NvRmDiagConfigurePowerRail(
+    NvRmDiagPowerRailHandle hRail,
+    NvU32 VoltageMV)
+{
+    NvU32 TimeUs = 0;
+    NvU32 RailAddress = 0;
+    const NvOdmPeripheralConnectivity* pPmuRail = NULL;
+
+    if (s_hDiagRm == NULL)
+    {
+        return NvError_NotInitialized;
+    }
+
+    // Verify that targeted rail can be found on the board, and
+    // it is connected to PMU
+    if (hRail != NULL)
+    {
+        pPmuRail = NvOdmPeripheralGetGuid(hRail->PowerRailId);
+    }
+    if((pPmuRail == NULL) || (pPmuRail->NumAddress == 0))
+    {
+        NV_ASSERT(!"Invalid power rail");
+        return NvError_NotSupported;
+    }
+
+    // Change voltage, and wait for settling time.
+    RailAddress = pPmuRail->AddressList[0].Address;
+    NVRM_DIAG_PRINTF(("Setting PMU rail %2d to %5dmV\n", RailAddress, VoltageMV));
+    if (NvRmPrivDiagPmuSetVoltage(s_hDiagRm, RailAddress, VoltageMV, &TimeUs))
+    {
+        NvOsWaitUS(TimeUs);
+        return NvSuccess;
+    }
+    return NvError_Busy;
+}
+
+/*****************************************************************************/
+
+static NvRmModuleID
+MapDiagIdToRmId(NvRmDiagModuleID DiagId)
+{
+    const NvRmModuleClockInfo* pCinfo = NULL;
+    NvU32 Instance = NVRM_DIAG_MODULE_INSTANCE(DiagId);
+    NvRmDiagModuleID Module = NVRM_DIAG_MODULE_ID(DiagId);
+
+    NvRmModuleID RmId = NvRmModuleID_Invalid;
+    if ((Module < NvRmDiagModuleID_Num) &&
+        (Instance < s_Modules.InstancesMap[Module].InstancesNum))
+    {
+        pCinfo = s_Modules.pInstancePtrs[
+            s_Modules.InstancesMap[Module].BaseIndex + Instance];
+        RmId = NVRM_MODULE_ID(pCinfo->Module, pCinfo->Instance);
+    }
+    return RmId;
+}
+
+NvBool NvRmPrivIsDiagMode(NvRmModuleID ModuleId)
+{
+    if (s_hDiagRm == NULL)
+        return NV_FALSE;    // Report no diagnostic in progress
+
+    if (ModuleId == NvRmModuleID_Invalid)
+        return NV_TRUE;     // Report diagnostic is in progress
+    
+    // Report diagnostic is in progress for any module except PMU bus host
+    return (ModuleId != s_Rails.PmuBusHostRmId);
+}
+
+NvBool NvRmDiagIsLockSupported(void)
+{
+#if NVRM_DIAG_LOCK_SUPPORTED
+    return NV_TRUE;
+#else
+    return NV_FALSE;
+#endif
+}
+
+/*****************************************************************************/
+
diff --git a/arch/arm/mach-tegra/nvrm/core/ap20/Makefile b/arch/arm/mach-tegra/nvrm/core/ap20/Makefile
new file mode 100644
index 000000000000..ba4cd877b0fb
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/core/ap20/Makefile
@@ -0,0 +1,20 @@
+ccflags-y += -DNV_IS_AVP=0
+ccflags-y += -DNV_OAL=0
+ccflags-y += -DNV_USE_FUSE_CLOCK_ENABLE=0
+ifeq ($(CONFIG_MACH_TEGRA_GENERIC_DEBUG),y)
+ccflags-y += -DNV_DEBUG=1
+else
+ccflags-y += -DNV_DEBUG=0
+endif
+
+ccflags-y += -Iarch/arm/mach-tegra/nvrm/core/common
+ccflags-y += -Iarch/arm/mach-tegra/nvrm/core
+
+obj-y += ap20rm_reloctable.o
+obj-y += ap20rm_clocks.o
+obj-y += ap20rm_clock_config.o
+obj-y += ap20rm_memctrl.o
+obj-y += ap20rm_power_dfs.o
+obj-y += ap20rm_pinmux_tables.o
+obj-y += ap20rm_fuse.o
+obj-y += ap20rm_clocks_info.o
diff --git a/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_clock_config.c b/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_clock_config.c
new file mode 100644
index 000000000000..b28aac4e1b10
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_clock_config.c
@@ -0,0 +1,1710 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include "nvcommon.h"
+#include "nvassert.h"
+#include "nvrm_clocks.h"
+#include "nvrm_hwintf.h"
+#include "nvrm_drf.h"
+#include "ap20rm_clocks.h"
+#include "ap20/aremc.h"
+#include "ap20/arclk_rst.h"
+#include "ap20/arapbpm.h"
+#include "ap15/ap15rm_private.h"
+#include "nvodm_query.h"
+
+// Enable CPU/EMC ratio policy
+#define NVRM_LIMIT_CPU_EMC_RATIO (1)
+
+// Use DRAM power down mode with EMC clock change
+#define NVRM_EMC_CLKCHANGE_PD (1)
+
+// Default CPU power good delay
+#define NVRM_DEFAULT_CPU_PWRGOOD_US (2000) 
+
+// Default PMU accuracy %
+#define NVRM_DEFAULT_PMU_ACCURACY_PCT (3)
+
+// Minimum core over CPU voltage margin (at SoC)
+#define NV_AP20_CORE_OVER_CPU_MV (120)
+
+/*****************************************************************************/
+
+/*
+ * TODO: Basic DFS clock control policy outline:
+ */
+
+// Limit frequencies ratio for AHB : System >= 1:2 and APB : System >= 1 : 4
+#define LIMIT_SYS_TO_AHB_APB_RATIOS (1)
+
+// PLLP2 must be used as a variable low frequency source for System clock.
+#define PLLP_POLICY_ENTRY(KHz) \
+ { NvRmClockSource_PllP2,\
+   (NVRM_PLLP_FIXED_FREQ_KHZ * 2)/((NVRM_PLLP_FIXED_FREQ_KHZ * 2)/KHz),\
+   ((NVRM_PLLP_FIXED_FREQ_KHZ * 2)/KHz - 2)\
+ },
+static const NvRmDfsSource s_Ap20PllPSystemClockPolicy[] =
+{
+    NVRM_AP20_PLLP_POLICY_SYSTEM_CLOCK
+};
+static const NvU32 s_Ap20PllPSystemClockPolicyEntries =
+    NV_ARRAY_SIZE(s_Ap20PllPSystemClockPolicy);
+#undef PLLP_POLICY_ENTRY
+
+
+// PLLP4 must be used as a variable low frequency source for cpu clock.
+#define PLLP_POLICY_ENTRY(KHz) \
+ { NvRmClockSource_PllP4,\
+   (NVRM_PLLP_FIXED_FREQ_KHZ * 2)/((NVRM_PLLP_FIXED_FREQ_KHZ * 2)/KHz),\
+   ((NVRM_PLLP_FIXED_FREQ_KHZ * 2)/KHz - 2)\
+ },
+static const NvRmDfsSource s_Ap20PllPCpuClockPolicy[] =
+{
+    NVRM_AP20_PLLP_POLICY_CPU_CLOCK
+};
+static const NvU32 s_Ap20PllPCpuClockPolicyEntries =
+    NV_ARRAY_SIZE(s_Ap20PllPCpuClockPolicy);
+#undef PLLP_POLICY_ENTRY
+
+// EMC timing registers
+static const NvU32 s_EmcTimingRegAddrRev20[] =
+{
+    EMC_RC_0,                   /* RC */
+    EMC_RFC_0,                  /* RFC */
+    EMC_RAS_0,                  /* RAS */
+    EMC_RP_0,                   /* RP */
+    EMC_R2W_0,                  /* R2W */
+    EMC_W2R_0,                  /* W2R */
+    EMC_R2P_0,                  /* R2P */
+    EMC_W2P_0,                  /* W2P */
+    EMC_RD_RCD_0,               /* RD_RCD */
+    EMC_WR_RCD_0,               /* WR_RCD */
+    EMC_RRD_0,                  /* RRD */
+    EMC_REXT_0,                 /* REXT */
+    EMC_WDV_0,                  /* WDV */
+    EMC_QUSE_0,                 /* QUSE */
+    EMC_QRST_0,                 /* QRST */
+    EMC_QSAFE_0,                /* QSAFE */
+    EMC_RDV_0,                  /* RDV */
+    EMC_REFRESH_0,              /* REFRESH */
+    EMC_BURST_REFRESH_NUM_0,    /* BURST_REFRESH_NUM */
+    EMC_PDEX2WR_0,              /* PDEX2WR */
+    EMC_PDEX2RD_0,              /* PDEX2RD */
+    EMC_PCHG2PDEN_0,            /* PCHG2PDEN */
+    EMC_ACT2PDEN_0,             /* ACT2PDEN */
+    EMC_AR2PDEN_0,              /* AR2PDEN */
+    EMC_RW2PDEN_0,              /* RW2PDEN */
+    EMC_TXSR_0,                 /* TXSR */
+    EMC_TCKE_0,                 /* TCKE */
+    EMC_TFAW_0,                 /* TFAW */
+    EMC_TRPAB_0,                /* TRPAB */
+    EMC_TCLKSTABLE_0,           /* TCLKSTABLE */
+    EMC_TCLKSTOP_0,             /* TCLKSTOP */
+    EMC_TREFBW_0,               /* TREFBW */
+    EMC_QUSE_EXTRA_0,           /* QUSE_EXTRA */
+    EMC_FBIO_CFG6_0,            /* FBIO_CFG6 */
+    EMC_ODT_WRITE_0,            /* ODT_WRITE */
+    EMC_ODT_READ_0,             /* ODT_READ */
+    EMC_FBIO_CFG5_0,            /* FBIO_CFG5 */
+    EMC_CFG_DIG_DLL_0,          /* CFG_DIG_DLL */
+    EMC_DLL_XFORM_DQS_0,        /* DLL_XFORM_DQS */
+    EMC_DLL_XFORM_QUSE_0,       /* DLL_XFORM_QUSE */
+    EMC_ZCAL_REF_CNT_0,         /* ZCAL_REF_CNT */
+    EMC_ZCAL_WAIT_CNT_0,        /* ZCAL_WAIT_CNT */
+    EMC_AUTO_CAL_INTERVAL_0,    /* AUTO_CAL_INTERVAL */
+    EMC_CFG_CLKTRIM_0_0,        /* CFG_CLKTRIM_0 */
+    EMC_CFG_CLKTRIM_1_0,        /* CFG_CLKTRIM_1 */
+    EMC_CFG_CLKTRIM_2_0,        /* CFG_CLKTRIM_2 */
+};
+
+// Sorted list of timing parameters for discrete set of EMC frequencies used
+// by DFS; entry 0 specifies timing parameters for PLLM0 output frequency.
+static NvRmAp20EmcTimingConfig
+s_Ap20EmcConfigSortedTable[NVRM_AP20_DFS_EMC_FREQ_STEPS];
+
+static struct Ap20EmcConfigRec
+{
+    // Index of selected EMC configuration entry
+    NvU32 Index;
+
+    // Status of undivided PLLM0 path
+    NvBool UdPllM0;
+
+    // Pointers to EMC clock state
+    NvRmModuleClockState* pEmc2xState;
+
+    // Pointers to EMC clock descriptors
+    NvRmModuleClockInfo* pEmcInfo;
+
+    // Array of EMC timing registers
+    const NvU32* pEmcTimingReg;
+
+    // Total number of EMC timing registers
+    NvU32 EmcTimingRegNum;
+
+} s_Ap20EmcConfig = {0};
+
+static struct Ap20VdeConfigRec
+{
+    // Pointer to VDE clock descriptor
+    NvRmModuleClockInfo* pVdeInfo;
+
+    // Pointer to VDE clock state
+    NvRmModuleClockState* pVdeState;
+
+} s_Ap20VdeConfig = {0};
+
+static struct Ap20CpuConfigRec
+{
+    // Number of PLLX frequency steps
+    NvU32 PllXStepsNo;
+
+    // PLLX frequency steps table pointer 
+    const NvRmFreqKHz* pPllXStepsKHz;
+
+    // CPU power good delay in microseconds
+    NvU32 CpuPowerGoodUs;
+
+    // Core over CPU voltage dependency parameters:
+    // Vcore >= CoreOverCpuSlope * Vcpu + CoreOverCpuOffset
+    NvU32 CoreOverCpuOffset;
+    NvU32 CoreOverCpuSlope;
+
+} s_Ap20CpuConfig = {0};
+
+/*****************************************************************************/
+/*****************************************************************************/
+
+static void
+Ap20Emc2xClockStateUpdate(
+    NvRmDeviceHandle hRmDevice)
+{
+    NvU32 reg;
+    NvRmFreqKHz SourceClockFreq;
+    NvRmModuleClockInfo* pCinfo = s_Ap20EmcConfig.pEmcInfo;
+    NvRmModuleClockState* pCstate = s_Ap20EmcConfig.pEmc2xState;
+
+    NV_ASSERT(pCinfo && pCstate);
+
+    // Determine EMC2x source and divider setting; update EMC2x clock state
+    reg = NV_REGR(hRmDevice,
+                  NvRmPrivModuleID_ClockAndReset, 0, pCinfo->ClkSourceOffset);
+    pCstate->Divider =
+        ((reg >> pCinfo->DivisorFieldShift) & pCinfo->DivisorFieldMask);
+    pCstate->SourceClock =
+        ((reg >> pCinfo->SourceFieldShift) & pCinfo->SourceFieldMask);
+    s_Ap20EmcConfig.UdPllM0 = NV_DRF_VAL(CLK_RST_CONTROLLER,
+        CLK_SOURCE_EMC, USE_PLLM_UD, reg) ? NV_TRUE : NV_FALSE;
+    if (s_Ap20EmcConfig.UdPllM0)
+    {
+        NV_ASSERT(  // policy: Src/Div settings must be synced with UD path
+            (pCstate->Divider == 0) && (pCstate->SourceClock ==
+            CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_SRC_PLLM_OUT0));
+    }
+    SourceClockFreq =
+        NvRmPrivGetClockSourceFreq(pCinfo->Sources[pCstate->SourceClock]);
+
+    // Fractional divider output = (Source Frequency * 2) / (divider + 2)
+    pCstate->actual_freq = ((SourceClockFreq << 1) / (pCstate->Divider + 2));
+}
+
+static NvBool
+Ap20EmcClkChangeConfig(
+    NvRmDeviceHandle hRmDevice)
+{
+// NO-DEVICE for dummy MRW/MRS commands
+#define NULL_DEV_SELECTN (3)
+
+    NvU32 cfg2, cfg5;
+
+    cfg2 = NV_REGR(hRmDevice, NvRmPrivModuleID_ExternalMemoryController, 0,
+                   EMC_CFG_2_0);
+    cfg5 = NV_REGR(hRmDevice, NvRmPrivModuleID_ExternalMemoryController, 0,
+                   EMC_FBIO_CFG5_0);
+
+    switch (NV_DRF_VAL(EMC, FBIO_CFG5, DRAM_TYPE, cfg5))
+    {
+        case EMC_FBIO_CFG5_0_DRAM_TYPE_LPDDR2:
+#if NVRM_EMC_CLKCHANGE_PD
+            // Dummy mode control command to activate PD state machine
+            NV_REGW(hRmDevice,
+                    NvRmPrivModuleID_ExternalMemoryController, 0, EMC_MRW_0,
+                    NV_DRF_NUM(EMC, MRW, MRW_DEV_SELECTN, NULL_DEV_SELECTN));
+            NvOsWaitUS(NVRM_CLOCK_CHANGE_DELAY);
+
+            cfg2 = NV_FLD_SET_DRF_DEF(
+                EMC, CFG_2, CLKCHANGE_PD_ENABLE, ENABLED, cfg2);
+            cfg2 = NV_FLD_SET_DRF_DEF(
+                EMC, CFG_2, CLKCHANGE_SR_ENABLE, DISABLED, cfg2);
+            break;
+#endif
+        case EMC_FBIO_CFG5_0_DRAM_TYPE_DDR2:
+#if NVRM_EMC_CLKCHANGE_PD
+            // Dummy mode control command to activate PD state machine
+            NV_REGW(hRmDevice,
+                    NvRmPrivModuleID_ExternalMemoryController, 0, EMC_MRS_0,
+                    NV_DRF_NUM(EMC, MRS, MRS_DEV_SELECTN, NULL_DEV_SELECTN));
+            NvOsWaitUS(NVRM_CLOCK_CHANGE_DELAY);
+#endif
+            cfg2 = NV_FLD_SET_DRF_DEF(
+                EMC, CFG_2, CLKCHANGE_PD_ENABLE, DISABLED, cfg2);
+            cfg2 = NV_FLD_SET_DRF_DEF(
+                EMC, CFG_2, CLKCHANGE_SR_ENABLE, ENABLED, cfg2);
+            break;
+        default:
+            NV_ASSERT(!"Not supported DRAM type");
+            return NV_FALSE;
+    }
+    cfg2 = NV_FLD_SET_DRF_DEF(
+        EMC, CFG_2, CLKCHANGE_REQ_ENABLE, ENABLED, cfg2);
+    NV_REGW(hRmDevice, NvRmPrivModuleID_ExternalMemoryController, 0,
+                   EMC_CFG_2_0, cfg2);
+    return NV_TRUE;
+}
+
+static NvRmFreqKHz Ap20CpuToEmcRatio(NvRmFreqKHz Emc2xKHz)
+{
+#if NVRM_LIMIT_CPU_EMC_RATIO
+    /*
+     * CPU/EMC ratio is limited by the policy curve tabulated below: when cpu
+     * frequency is reduced by 25%, emc frequency along the curve is reduced
+     * by 50%.
+     */
+    static const NvU32 CpuToEmc[] = { 0,
+        7,  10, 11, 13, 14, 15, 17, 18, 18, 19, 20, 21, 22, 22, 23, 24,
+        24, 25, 25, 26, 26, 27, 27, 28, 28, 29, 29, 30, 30, 31, 31, 32
+    };
+    #define CPU_TO_EMC_MAX_RATIO (10)
+    
+    NvRmFreqKHz CpuKHz;
+    NvRmFreqKHz CpuMaxKHz = NvRmPrivGetSocClockLimits(NvRmModuleID_Cpu)->MaxKHz;
+    NvRmFreqKHz Emc2xMaxKHz = NvRmPrivGetClockSourceFreq(NvRmClockSource_PllM0);
+
+    NvU32 M = NV_ARRAY_SIZE(CpuToEmc) - 1;
+    NvU32 x = (Emc2xKHz * M + Emc2xMaxKHz - 1) / Emc2xMaxKHz;
+    NV_ASSERT((x >= 1) && (x <= M));
+    CpuKHz = (CpuMaxKHz * CpuToEmc[x] + M - 1) / M;
+    CpuKHz = NV_MIN(CpuKHz, (Emc2xKHz * (CPU_TO_EMC_MAX_RATIO / 2)));
+
+    return CpuKHz;
+#else
+    return NvRmFreqMaximum;
+#endif
+}
+
+static void Ap20EmcConfigInit(NvRmDeviceHandle hRmDevice)
+{
+    NvRmFreqKHz Emc2xKHz, SourceKHz;
+    NvU32 i, j, k, Source, ConfigurationsCount, UndividedIndex;
+    NvU32 Revision = 0;
+    
+    NvRmFreqKHz PllM0KHz = NvRmPrivGetClockSourceFreq(NvRmClockSource_PllM0);
+    NvRmFreqKHz PllP0KHz = NvRmPrivGetClockSourceFreq(NvRmClockSource_PllP0);
+    const NvRmModuleClockLimits* pEmcClockLimits =
+         NvRmPrivGetSocClockLimits(NvRmPrivModuleID_ExternalMemoryController);
+    const NvOdmSdramControllerConfigAdv* pEmcConfigurations =
+        NvOdmQuerySdramControllerConfigGet(&ConfigurationsCount, &Revision);
+
+    // Init memory configuration structure
+    NV_ASSERT_SUCCESS(NvRmPrivGetClockState(
+        hRmDevice, NvRmPrivModuleID_ExternalMemoryController,
+        &s_Ap20EmcConfig.pEmcInfo, &s_Ap20EmcConfig.pEmc2xState));
+
+     s_Ap20EmcConfig.pEmcTimingReg = &s_EmcTimingRegAddrRev20[0];
+     s_Ap20EmcConfig.EmcTimingRegNum = NV_ARRAY_SIZE(s_EmcTimingRegAddrRev20);
+     s_Ap20EmcConfig.Index = NVRM_AP20_DFS_EMC_FREQ_STEPS; // invalid index
+
+     // Clean table, which invalidates PLLM0 entry - no EMC DFS if exits
+     // before sorting below
+     NvOsMemset(s_Ap20EmcConfigSortedTable, 0,
+                sizeof(s_Ap20EmcConfigSortedTable));
+
+     // Get EMC2x clock state from h/w
+     Ap20Emc2xClockStateUpdate(hRmDevice);
+
+     // Configure EMC clock change mechanism - exit if not supported
+     if (!Ap20EmcClkChangeConfig(hRmDevice))
+         return;
+
+     // Check if configuration table is provided by ODM
+     if ((ConfigurationsCount == 0) || (pEmcConfigurations == NULL))
+         return;
+
+    // EMC DVFS is supported on AP20 starting with A02 chip
+    if ((hRmDevice->ChipId.Major == 1) && (hRmDevice->ChipId.Minor <= 1))
+        return;
+
+    // Only 2.0 table revision is supported
+    if (Revision != 0x20)
+    {
+        NV_ASSERT(!"Invalid configuration table revision");
+        return;
+    }
+
+     // Check PLLs clock range
+     if ((PllP0KHz < pEmcClockLimits->MinKHz) ||
+         (PllP0KHz > pEmcClockLimits->MaxKHz))
+     {
+         NV_ASSERT(!"PLLP0 is outside supported EMC range");
+         return;
+     }
+     if ((PllM0KHz < pEmcClockLimits->MinKHz) ||
+         (PllM0KHz > pEmcClockLimits->MaxKHz))
+     {
+         NV_ASSERT(!"PLLM0 is outside supported EMC range");
+         return;
+     }
+
+     // Check if PLLM0 is configured by boot loader as EMC clock source
+     if (s_Ap20EmcConfig.pEmc2xState->SourceClock !=
+         CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_SRC_PLLM_OUT0)
+     {
+         NV_ASSERT(!"Other than PLLM0 clock source is used for EMC");
+         return;
+     }
+
+     // Sort list of EMC timing parameters in descending order of frequencies
+     // evenly divided down from the selected source. Supported sources: PLLM0
+     // PLLP0, and Oscillator
+     Source = CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_SRC_PLLM_OUT0;
+     for (i = 0; i < NVRM_AP20_DFS_EMC_FREQ_STEPS; )
+     {
+         SourceKHz = Emc2xKHz = NvRmPrivGetClockSourceFreq(
+             s_Ap20EmcConfig.pEmcInfo->Sources[Source]);
+
+         for (k = 0, UndividedIndex = i; i < NVRM_AP20_DFS_EMC_FREQ_STEPS; )
+         {
+             s_Ap20EmcConfigSortedTable[i].Emc2xKHz = 0; // mark entry invalid
+             for (j = 0; j < ConfigurationsCount; j++)
+             {
+                 // Find match with 0.4% accuracy for ODM configuration
+                 if (((pEmcConfigurations[j].SdramKHz * 2) <=
+                      (Emc2xKHz + (Emc2xKHz >> 8))) &&
+                     ((pEmcConfigurations[j].SdramKHz * 2) >=
+                      (Emc2xKHz - (Emc2xKHz >> 8))))
+                 {
+                     NV_ASSERT(pEmcConfigurations[j].Revision == Revision);
+                     NV_ASSERT(pEmcConfigurations[j].EmcTimingParamNum ==
+                               s_Ap20EmcConfig.EmcTimingRegNum);
+
+                     s_Ap20EmcConfigSortedTable[i].pOdmEmcConfig =
+                         &pEmcConfigurations[j];
+
+                     s_Ap20EmcConfigSortedTable[i].Emc2xClockSource = Source;
+                     s_Ap20EmcConfigSortedTable[i].Emc2xUndividedIndex =
+                         UndividedIndex;
+                     s_Ap20EmcConfigSortedTable[i].Emc2xKHz = Emc2xKHz;
+
+                     /*
+                      * The undivided table entry specifies parameters for
+                      * EMC2xKHz = SourceKHz; the EMC divisor field is set to
+                      * "0". Next table entries specify parameters for EMC2xKHz
+                      * = SourceKHz / (2 * k); the EMC divisor field should be
+                      * set as 2 * (2 * k) - 2 = 4 * k - 2.
+                      */
+                     if (k == 0)
+                         s_Ap20EmcConfigSortedTable[i].Emc2xDivisor = 0;
+                     else
+                         s_Ap20EmcConfigSortedTable[i].Emc2xDivisor =
+                                                            (k << 2) - 2;
+                     // Check boot configuration (to be recognized boot Src/Div
+                     // settings must be synced with UD path)
+                     if ((SourceKHz == PllM0KHz) &&
+                         (s_Ap20EmcConfigSortedTable[i].Emc2xDivisor ==
+                          s_Ap20EmcConfig.pEmc2xState->Divider))
+                     {
+                         if (s_Ap20EmcConfig.UdPllM0 == (i == 0))
+                             s_Ap20EmcConfig.Index = i;
+                     }
+                     s_Ap20EmcConfigSortedTable[i].CpuLimitKHz =
+                         Ap20CpuToEmcRatio(Emc2xKHz);
+                     break;
+                 }
+             }
+             if (s_Ap20EmcConfigSortedTable[i].Emc2xKHz != 0)
+                 i++;       // Entry found - advance sorting index
+             else if (k == 0)
+                 break;     // Abort sorting if undiveded source not found
+
+             Emc2xKHz = SourceKHz / ((++k) << 1);
+             if (Emc2xKHz < pEmcClockLimits->MinKHz)
+                 break;     // Abort sorting if min frequency reached
+         }
+
+         if (i == 0) 
+             break;         // Finish sorting if PLLM0 entry not found
+
+         // Next source selection
+         if (Source ==
+             CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_SRC_PLLM_OUT0)
+         {
+             Source =       // After PLLM0 try PLLP0 as a source
+             CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_SRC_PLLP_OUT0;
+         }
+         else
+             break;     // Finish sorting
+     }
+}
+
+static void
+Ap20EmcTimingSet(
+    NvRmDeviceHandle hRmDevice,
+    const NvRmAp20EmcTimingConfig* pEmcConfig)
+{
+    NvU32 i, a, d;
+
+    // EMC module virtual base address to speed up timing update
+    static void* s_pEmcBaseReg = NULL;
+
+    if (s_pEmcBaseReg == NULL)
+    {
+        NvRmModuleTable *tbl = NvRmPrivGetModuleTable(hRmDevice);
+        s_pEmcBaseReg = (tbl->ModInst +
+             tbl->Modules[NvRmPrivModuleID_ExternalMemoryController].Index)->VirtAddr;
+    }
+    a = (NvU32)s_pEmcBaseReg;
+
+    for (i = 0; i < s_Ap20EmcConfig.EmcTimingRegNum; i++)
+    {
+        d = pEmcConfig->pOdmEmcConfig->EmcTimingParameters[i];
+        a = (((NvU32)(s_pEmcBaseReg)) + s_Ap20EmcConfig.pEmcTimingReg[i]);
+        NV_WRITE32(a, d);
+    }
+    d = NV_READ32(a);   // make sure writes are completed
+}
+
+static void
+Ap20EmcDividerBackgroundSet( 
+    NvRmDeviceHandle hRmDevice,
+    NvU32 value)
+{
+    NvU32 cfg2, clk;
+
+    // Check if divider is actually to be changed - exit if not
+    clk = cfg2 = NV_REGR(hRmDevice, NvRmPrivModuleID_ClockAndReset, 0,
+                  CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0);
+    clk = NV_FLD_SET_DRF_NUM(CLK_RST_CONTROLLER, CLK_SOURCE_EMC,
+                             EMC_2X_CLK_DIVISOR, value, clk);
+    if (cfg2 == clk)
+        return;
+
+    // Disable EMC clock change request, so that following EMC clock divider
+    // change will not trigger EMC timing switch ("background change")
+    cfg2 = NV_REGR(hRmDevice, NvRmPrivModuleID_ExternalMemoryController, 0,
+                   EMC_CFG_2_0);
+    NV_ASSERT(NV_DRF_VAL(EMC, CFG_2, CLKCHANGE_REQ_ENABLE, cfg2) == 1);
+    cfg2 = NV_FLD_SET_DRF_DEF(EMC, CFG_2, CLKCHANGE_REQ_ENABLE,
+                              DISABLED, cfg2);
+    NV_REGW(hRmDevice, NvRmPrivModuleID_ExternalMemoryController, 0,
+            EMC_CFG_2_0, cfg2);
+    cfg2 = NV_REGR(hRmDevice, NvRmPrivModuleID_ExternalMemoryController, 0,
+                   EMC_CFG_2_0);    // make sure write is completed
+
+    // Set EMC clock divider (UD bit must be set during "background change")
+    NV_ASSERT(NV_DRF_VAL(CLK_RST_CONTROLLER, CLK_SOURCE_EMC, USE_PLLM_UD, clk));
+    NV_REGW(hRmDevice, NvRmPrivModuleID_ClockAndReset, 0,
+            CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0, clk);
+    NvOsWaitUS(NVRM_CLOCK_CHANGE_DELAY);
+
+    // Restore EMC clock change request
+    cfg2 = NV_FLD_SET_DRF_DEF(EMC, CFG_2, CLKCHANGE_REQ_ENABLE,
+                              ENABLED, cfg2);
+    NV_REGW(hRmDevice, NvRmPrivModuleID_ExternalMemoryController, 0,
+            EMC_CFG_2_0, cfg2);
+    cfg2 = NV_REGR(hRmDevice, NvRmPrivModuleID_ExternalMemoryController, 0,
+                   EMC_CFG_2_0);    // make sure write is completed
+}
+
+static void
+Ap20EmcSwitchToUndividedPllM0(
+        NvRmDeviceHandle hRmDevice,
+        const NvRmAp20EmcTimingConfig* pEmcConfig)
+{
+    NvU32 reg;
+    NV_ASSERT(pEmcConfig->Emc2xKHz);    // validate table entry
+
+    // Update EMC shadow registers
+    Ap20EmcTimingSet(hRmDevice, pEmcConfig);
+
+    // Set EMC clock source as undivided PLLM0 (divider is "don't care" in this
+    // case, so keep it as is to satisfy restriction: source and divider can not
+    // be changed simultaneously)
+    reg = NV_REGR(hRmDevice, NvRmPrivModuleID_ClockAndReset, 0,
+                  CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0);
+    reg = NV_FLD_SET_DRF_NUM(CLK_RST_CONTROLLER, CLK_SOURCE_EMC,
+                  EMC_2X_CLK_SRC, pEmcConfig->Emc2xClockSource, reg);
+    reg = NV_FLD_SET_DRF_NUM(CLK_RST_CONTROLLER, CLK_SOURCE_EMC,
+                             USE_PLLM_UD, 1, reg);
+    NV_REGW(hRmDevice, NvRmPrivModuleID_ClockAndReset, 0,
+            CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0, reg);
+    NvOsWaitUS(NVRM_CLOCK_CHANGE_DELAY);
+
+    // Now set new divider value. Note that PLLM_UD bit is already set, so
+    // the actual EMC frequency is not changed. Hence, no need to update EMC
+    // timing - the old settings already match the frequency.
+    Ap20EmcDividerBackgroundSet(hRmDevice, pEmcConfig->Emc2xDivisor);
+
+    // Update EMC state
+    s_Ap20EmcConfig.UdPllM0 = NV_TRUE;
+    s_Ap20EmcConfig.pEmc2xState->SourceClock = pEmcConfig->Emc2xClockSource;
+    s_Ap20EmcConfig.pEmc2xState->Divider = pEmcConfig->Emc2xDivisor;
+    s_Ap20EmcConfig.pEmc2xState->actual_freq = pEmcConfig->Emc2xKHz;
+    NvRmPrivMemoryClockReAttach(
+        hRmDevice, s_Ap20EmcConfig.pEmcInfo, s_Ap20EmcConfig.pEmc2xState);
+}
+
+static void
+Ap20EmcSwitchFromUndividedPllM0(
+        NvRmDeviceHandle hRmDevice,
+        const NvRmAp20EmcTimingConfig* pEmcConfig)
+{
+    NvU32 reg;
+    NV_ASSERT(pEmcConfig->Emc2xKHz);    // validate table entry
+
+    // 1st set new divider value. Note that PLLM_UD bit is still set, so the
+    // actual EMC frequency is not changed. Hence, no need to update EMC
+    // timing - the old settings already match the frequency.
+    Ap20EmcDividerBackgroundSet(hRmDevice, pEmcConfig->Emc2xDivisor);
+
+    // Update EMC shadow registers
+    Ap20EmcTimingSet(hRmDevice, pEmcConfig);
+
+    // Now set new EMC clock source and disable undivided path (can be done
+    // in one shot - cumulatively it is considered as source change only)
+    reg = NV_REGR(hRmDevice, NvRmPrivModuleID_ClockAndReset, 0,
+                  CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0);
+    reg = NV_FLD_SET_DRF_NUM(CLK_RST_CONTROLLER, CLK_SOURCE_EMC,
+                  EMC_2X_CLK_SRC, pEmcConfig->Emc2xClockSource, reg);
+    reg = NV_FLD_SET_DRF_NUM(CLK_RST_CONTROLLER, CLK_SOURCE_EMC,
+                             USE_PLLM_UD, 0, reg);
+    NV_REGW(hRmDevice, NvRmPrivModuleID_ClockAndReset, 0,
+            CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0, reg);
+    NvOsWaitUS(NVRM_CLOCK_CHANGE_DELAY);
+
+    // Update EMC state
+    s_Ap20EmcConfig.UdPllM0 = NV_FALSE;
+    s_Ap20EmcConfig.pEmc2xState->SourceClock = pEmcConfig->Emc2xClockSource;
+    s_Ap20EmcConfig.pEmc2xState->Divider = pEmcConfig->Emc2xDivisor;
+    s_Ap20EmcConfig.pEmc2xState->actual_freq = pEmcConfig->Emc2xKHz;
+    NvRmPrivMemoryClockReAttach(
+        hRmDevice, s_Ap20EmcConfig.pEmcInfo, s_Ap20EmcConfig.pEmc2xState);
+}
+
+static void
+Ap20EmcSwitchDividedSources(
+        NvRmDeviceHandle hRmDevice,
+        const NvRmAp20EmcTimingConfig* pEmcConfig)
+{
+    NvU32 reg, div, src;
+    NV_ASSERT(pEmcConfig->Emc2xKHz);    // validate table entry
+
+    // Update EMC shadow registers
+    Ap20EmcTimingSet(hRmDevice, pEmcConfig);
+
+    // This switch must be called only when original and target configurations
+    // have either common source or common divider - switch in one shot.
+    reg = NV_REGR(hRmDevice, NvRmPrivModuleID_ClockAndReset, 0,
+                  CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0);
+    src = NV_DRF_VAL(
+        CLK_RST_CONTROLLER, CLK_SOURCE_EMC, EMC_2X_CLK_SRC, reg);
+    div = NV_DRF_VAL(
+        CLK_RST_CONTROLLER, CLK_SOURCE_EMC, EMC_2X_CLK_DIVISOR, reg);
+    NV_ASSERT((src == pEmcConfig->Emc2xClockSource) ||
+              (div == pEmcConfig->Emc2xDivisor));
+
+    reg = NV_FLD_SET_DRF_NUM(CLK_RST_CONTROLLER, CLK_SOURCE_EMC,
+                  EMC_2X_CLK_DIVISOR, pEmcConfig->Emc2xDivisor, reg);
+    reg = NV_FLD_SET_DRF_NUM(CLK_RST_CONTROLLER, CLK_SOURCE_EMC,
+                  EMC_2X_CLK_SRC, pEmcConfig->Emc2xClockSource, reg);
+    NV_REGW(hRmDevice, NvRmPrivModuleID_ClockAndReset, 0,
+            CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0, reg);
+    NvOsWaitUS(NVRM_CLOCK_CHANGE_DELAY);
+
+    // Update EMC state (undivided path status not changed)
+    NV_ASSERT(!s_Ap20EmcConfig.UdPllM0);
+    s_Ap20EmcConfig.pEmc2xState->SourceClock = pEmcConfig->Emc2xClockSource;
+    s_Ap20EmcConfig.pEmc2xState->Divider = pEmcConfig->Emc2xDivisor;
+    s_Ap20EmcConfig.pEmc2xState->actual_freq = pEmcConfig->Emc2xKHz;
+    NvRmPrivMemoryClockReAttach(
+        hRmDevice, s_Ap20EmcConfig.pEmcInfo, s_Ap20EmcConfig.pEmc2xState);
+}
+
+static NvBool
+Ap20Emc2xClockSourceFind(
+    NvRmDeviceHandle hRmDevice,
+    NvRmFreqKHz MaxKHz,
+    NvRmFreqKHz DomainKHz,
+    NvRmFreqKHz* pCpuTargetKHz,
+    NvRmDfsSource* pDfsSource)
+{
+    NvU32 i;
+    NvBool FinalStep = NV_TRUE;
+    NV_ASSERT(DomainKHz <= MaxKHz);
+    NV_ASSERT(s_Ap20EmcConfigSortedTable[0].Emc2xKHz <= MaxKHz);
+
+    // If PLLM0 entry in EMC frequeuncies table is invalid, EMC frequency
+    // will not be scaled; just fill in current EMC frequency
+    if (s_Ap20EmcConfigSortedTable[0].Emc2xKHz == 0)
+    {
+        pDfsSource->SourceId = NvRmClockSource_Invalid;  // invalidate source
+        pDfsSource->DividerSetting = NVRM_AP20_DFS_EMC_FREQ_STEPS;
+        pDfsSource->SourceKHz = s_Ap20EmcConfig.pEmc2xState->actual_freq;
+        pDfsSource->MinMv = NvRmVoltsMaximum; // no v-scaling in this case
+        return FinalStep;
+    }
+
+    // Search sorted pre-defind EMC frequencies for the entry above and closest
+    // to the traget that also has CPU limit above the CPU target. Use PLLM0
+    // entry if not found.
+    for (i = NVRM_AP20_DFS_EMC_FREQ_STEPS; i > 0;)
+    {
+        i--;
+        if ((DomainKHz <= s_Ap20EmcConfigSortedTable[i].Emc2xKHz) &&
+            (*pCpuTargetKHz <= s_Ap20EmcConfigSortedTable[i].CpuLimitKHz))
+            break;
+    }
+
+    // Target can be reached in one step, provided: 
+    // - either current or target entry is PLLM0     OR
+    // - current and target entries have same source OR
+    // - current and target entries have same divider
+    if ((i != 0) && (s_Ap20EmcConfig.Index != 0) &&
+        (s_Ap20EmcConfigSortedTable[i].Emc2xDivisor !=
+         s_Ap20EmcConfigSortedTable[s_Ap20EmcConfig.Index].Emc2xDivisor) &&
+        (s_Ap20EmcConfigSortedTable[i].Emc2xClockSource !=
+         s_Ap20EmcConfigSortedTable[s_Ap20EmcConfig.Index].Emc2xClockSource))
+    {
+        i = 0;  // one-step check failed - use PLLM0 as intermediate target
+        FinalStep = NV_FALSE;
+    }
+
+    // Record found EMC target, and limit CPU target if necessary
+    pDfsSource->DividerSetting = i;
+    pDfsSource->SourceId = s_Ap20EmcConfig.pEmcInfo->Sources[
+        s_Ap20EmcConfigSortedTable[i].Emc2xClockSource];
+    pDfsSource->SourceKHz = s_Ap20EmcConfigSortedTable[i].Emc2xKHz;
+    pDfsSource->MinMv =
+        s_Ap20EmcConfigSortedTable[i].pOdmEmcConfig->EmcCoreVoltageMv;
+    if (*pCpuTargetKHz > s_Ap20EmcConfigSortedTable[i].CpuLimitKHz)
+        *pCpuTargetKHz = s_Ap20EmcConfigSortedTable[i].CpuLimitKHz;
+    return FinalStep;
+}
+
+static void
+Ap20Emc2xClockConfigure(
+    NvRmDeviceHandle hRmDevice,
+    NvRmFreqKHz MaxKHz,
+    NvRmFreqKHz* pDomainKHz,
+    const NvRmDfsSource* pDfsSource)
+{
+    NvU32 Index;
+
+    // Always return the requested source frequency
+    *pDomainKHz = pDfsSource->SourceKHz;
+    NV_ASSERT(*pDomainKHz);
+
+    // If no valid source is found, EMC frequency is not scaled.
+    if (pDfsSource->SourceId == NvRmClockSource_Invalid)
+        return;
+
+    // Divider settings in EMC source descriptor is an index into the table of
+    // pre-defined EMC configurations in descending frequency order.
+    Index = pDfsSource->DividerSetting;
+    if (Index == s_Ap20EmcConfig.Index)
+        return;     // do nothing if new index is the same as current
+
+    // Switch EMC to the new target
+    if (Index == 0)
+    {
+        Ap20EmcSwitchToUndividedPllM0(
+            hRmDevice, &s_Ap20EmcConfigSortedTable[Index]);
+    }
+    else if (s_Ap20EmcConfig.Index == 0)
+    {
+        Ap20EmcSwitchFromUndividedPllM0(
+            hRmDevice, &s_Ap20EmcConfigSortedTable[Index]);
+    }
+    else
+    {
+        Ap20EmcSwitchDividedSources(
+            hRmDevice, &s_Ap20EmcConfigSortedTable[Index]);
+    }
+    s_Ap20EmcConfig.Index = Index;
+}
+
+/*****************************************************************************/
+
+NvRmFreqKHz
+NvRmPrivAp20GetEmcSyncFreq(
+    NvRmDeviceHandle hRmDevice,
+    NvRmModuleID Module)
+{
+    NvRmFreqKHz FreqKHz;
+
+    switch (Module)
+    {
+        case NvRmModuleID_2D:
+        case NvRmModuleID_Epp:
+            // Scale down 2D/EPP whith EMC clock (set 2D/EPP frequency at
+            // 50% of max when EMC clock is at or below 50% of max)
+            FreqKHz = NvRmPrivGetSocClockLimits(Module)->MaxKHz;
+            if ((0 < s_Ap20EmcConfig.Index) &&
+                (s_Ap20EmcConfig.Index < NVRM_AP20_DFS_EMC_FREQ_STEPS))
+                FreqKHz >>= 1;
+            break;
+
+        case NvRmModuleID_GraphicsHost:
+            FreqKHz = NVRM_AP20_HOST_KHZ;
+            break;
+
+        default:
+            NV_ASSERT(!"Invalid module for EMC synchronization");
+            FreqKHz = NvRmPrivGetSocClockLimits(Module)->MaxKHz;
+            break;
+    }
+    return FreqKHz;
+}
+
+void
+NvRmPrivAp20ClipCpuEmcHighLimits(
+    NvRmDeviceHandle hRmDevice,
+    NvRmFreqKHz* pCpuHighKHz,
+    NvRmFreqKHz* pEmcHighKHz)
+{
+#if !NV_OAL
+    NvU32 i;
+    NvRmFreqKHz EmcKHz;
+    NvRmFreqKHz MinKHz = NvRmPrivDfsGetMinKHz(NvRmDfsClockId_Emc);
+    NV_ASSERT(pEmcHighKHz && pCpuHighKHz);
+
+    // Nothing to do if no EMC scaling.
+    if (s_Ap20EmcConfigSortedTable[0].Emc2xKHz == 0)
+        return;
+
+    // Clip strategy: "throttling" - find the floor for EMC high limit
+    // (above domain minimum, of course)
+    if ((*pEmcHighKHz) < MinKHz)
+        *pEmcHighKHz = MinKHz;
+    for (i = 0; i < NVRM_AP20_DFS_EMC_FREQ_STEPS; i++)
+    {
+        EmcKHz = s_Ap20EmcConfigSortedTable[i].Emc2xKHz >> 1;
+        if (EmcKHz <= (*pEmcHighKHz))
+            break;
+    }
+    if ((i == NVRM_AP20_DFS_EMC_FREQ_STEPS) || (EmcKHz < MinKHz))
+    {
+        i--;
+        EmcKHz = s_Ap20EmcConfigSortedTable[i].Emc2xKHz >> 1;
+    }
+    *pEmcHighKHz = EmcKHz;
+
+#if NVRM_LIMIT_CPU_EMC_RATIO
+    // Clip strategy: "throttling" - restrict CPU high limit by EMC
+    // configuration ((above domain minimum, of course)
+    if ((*pCpuHighKHz) > s_Ap20EmcConfigSortedTable[i].CpuLimitKHz)
+        (*pCpuHighKHz) = s_Ap20EmcConfigSortedTable[i].CpuLimitKHz;
+    if ((*pCpuHighKHz) < NvRmPrivDfsGetMinKHz(NvRmDfsClockId_Cpu))
+        *pCpuHighKHz = NvRmPrivDfsGetMinKHz(NvRmDfsClockId_Cpu);
+#endif
+#endif
+}
+
+static void
+Ap20VdeClockStateUpdate(
+    NvRmDeviceHandle hRmDevice)
+{
+    NvU32 reg;
+    NvRmFreqKHz SourceClockFreq;
+    NvRmModuleClockInfo* pCinfo = s_Ap20VdeConfig.pVdeInfo;
+    NvRmModuleClockState* pCstate = s_Ap20VdeConfig.pVdeState;
+
+    NV_ASSERT(pCinfo && pCstate);
+
+    // Determine VDE source and divider setting; update VDE clock state
+    reg = NV_REGR(hRmDevice,
+                  NvRmPrivModuleID_ClockAndReset, 0, pCinfo->ClkSourceOffset);
+    pCstate->Divider =
+        ((reg >> pCinfo->DivisorFieldShift) & pCinfo->DivisorFieldMask);
+    pCstate->SourceClock =
+        ((reg >> pCinfo->SourceFieldShift) & pCinfo->SourceFieldMask);
+    SourceClockFreq =
+        NvRmPrivGetClockSourceFreq(pCinfo->Sources[pCstate->SourceClock]);
+
+    // Fractional divider output = (Source Frequency * 2) / (divider + 2)
+    pCstate->actual_freq = ((SourceClockFreq << 1) / (pCstate->Divider + 2));
+}
+
+static void Ap20VdeConfigInit(NvRmDeviceHandle hRmDevice)
+{
+    // Init VDE configuration shadow structure
+    NV_ASSERT_SUCCESS(NvRmPrivGetClockState(
+        hRmDevice, NvRmModuleID_Vde,
+        &s_Ap20VdeConfig.pVdeInfo, &s_Ap20VdeConfig.pVdeState));
+
+     // Get VDE clock state from h/w
+     Ap20VdeClockStateUpdate(hRmDevice);
+}
+
+static void
+Ap20VdeClockSourceFind(
+    NvRmDeviceHandle hRmDevice,
+    NvRmFreqKHz MaxKHz,
+    NvRmFreqKHz DomainKHz,
+    NvRmDfsSource* pDfsSource)
+{
+    NvU32 c, m, p;
+    NvRmFreqKHz SourceKHz, ReachedKHzP, ReachedKHzC, ReachedKHzM, BestKHz;
+    NV_ASSERT(DomainKHz <= MaxKHz);
+
+    // VDE clock is disabled - can not change configuration at all,
+    // and does not have any voltage requirements
+    if (s_Ap20VdeConfig.pVdeState->refCount == 0)
+    {
+        pDfsSource->SourceId = NvRmClockSource_Invalid;
+        pDfsSource->MinMv = NvRmVoltsUnspecified;
+        return;
+    }
+
+    // 1st try oscillator through VDE divider
+    SourceKHz = NvRmPrivGetClockSourceFreq(NvRmClockSource_ClkM);
+    if (DomainKHz <= SourceKHz)
+    {
+        pDfsSource->SourceId = NvRmClockSource_ClkM;
+        pDfsSource->DividerSetting = NvRmPrivFindFreqMinAbove(
+            s_Ap20VdeConfig.pVdeInfo->Divider, SourceKHz, MaxKHz, &DomainKHz);
+        goto get_mv;
+    }
+
+    // 2nd option - PLLP0 through VDE divider selected unconditionally if
+    // target is below half of PLLP0 output (divider granularity is "fair"
+    ReachedKHzP = DomainKHz;
+    SourceKHz = NvRmPrivGetClockSourceFreq(NvRmClockSource_PllP0);
+    p = NvRmPrivFindFreqMinAbove(
+        s_Ap20VdeConfig.pVdeInfo->Divider, SourceKHz, MaxKHz, &ReachedKHzP);
+    if (DomainKHz <= (SourceKHz >> 1))
+    {
+        pDfsSource->SourceId = NvRmClockSource_PllP0;
+        pDfsSource->DividerSetting = p;
+        DomainKHz = ReachedKHzP;
+        goto get_mv;
+    }
+
+    /*
+     * For high target frequencies add 3rd and 4th options - PLLC0, or PLLM0
+     * through VDE divider, respectively. Select the option that provides
+     * minimum output frequency equal or above the target, if all output
+     * frequencies within domain maximum limit are below the target, select
+     * the option with maximum output frequency.
+     */
+    ReachedKHzC = ReachedKHzM = DomainKHz;
+    SourceKHz = NvRmPrivGetClockSourceFreq(NvRmClockSource_PllC0);
+    c = NvRmPrivFindFreqMinAbove(
+        s_Ap20VdeConfig.pVdeInfo->Divider, SourceKHz, MaxKHz, &ReachedKHzC);
+    SourceKHz = NvRmPrivGetClockSourceFreq(NvRmClockSource_PllM0);
+    m = NvRmPrivFindFreqMinAbove(
+        s_Ap20VdeConfig.pVdeInfo->Divider, SourceKHz, MaxKHz, &ReachedKHzM);
+
+    BestKHz = NV_MAX(NV_MAX(ReachedKHzP, ReachedKHzC), ReachedKHzM);
+    if ((DomainKHz <= ReachedKHzP) && (ReachedKHzP < BestKHz))
+        BestKHz = ReachedKHzP;
+    if ((DomainKHz <= ReachedKHzC) && (ReachedKHzC < BestKHz))
+        BestKHz = ReachedKHzC;
+    // PLLM0 may be selected as the last resort if two others are below target
+
+    // Set souce clock parameters for selected option
+    if (BestKHz == ReachedKHzP)
+    {
+        SourceKHz = NvRmPrivGetClockSourceFreq(NvRmClockSource_PllP0);
+        pDfsSource->SourceId = NvRmClockSource_PllP0;
+        pDfsSource->DividerSetting = p;
+        DomainKHz = ReachedKHzP;             // use PLLP0 as source
+    }
+    else if (BestKHz == ReachedKHzC)
+    {
+        SourceKHz = NvRmPrivGetClockSourceFreq(NvRmClockSource_PllC0);
+        pDfsSource->SourceId = NvRmClockSource_PllC0;
+        pDfsSource->DividerSetting = c;
+        DomainKHz = ReachedKHzC;             // use PLLC0 as source
+    }
+    else
+    {
+        SourceKHz = NvRmPrivGetClockSourceFreq(NvRmClockSource_PllM0);
+        pDfsSource->SourceId = NvRmClockSource_PllM0;
+        pDfsSource->DividerSetting = m;
+        DomainKHz = ReachedKHzM;            // use PLLM0 as source
+    }
+
+get_mv:
+    // Finally update VDE v-scale references, get operational voltage for the
+    // found source/divider settings, and store new domain frequency
+    NvRmPrivLockModuleClockState();
+    pDfsSource->MinMv = NvRmPrivModuleVscaleReAttach(
+        hRmDevice, s_Ap20VdeConfig.pVdeInfo, s_Ap20VdeConfig.pVdeState,
+        DomainKHz, SourceKHz, NV_FALSE);
+    NvRmPrivUnlockModuleClockState();
+    pDfsSource->SourceKHz = DomainKHz;
+}
+
+static void
+Ap20VdeClockConfigure(
+    NvRmDeviceHandle hRmDevice,
+    NvRmFreqKHz MaxKHz,
+    NvRmFreqKHz* pDomainKHz,
+    const NvRmDfsSource* pDfsSource)
+{
+// Shortcut - number of AP20 VDE sources (instead of checking descriptor)
+#define AP20_VDE_SOURCES_NUMBER (4)
+
+    NvU32 SourceIndex;
+    NvRmModuleClockInfo* pCinfo = s_Ap20VdeConfig.pVdeInfo;
+    NvRmModuleClockState* pCstate = s_Ap20VdeConfig.pVdeState;
+
+    // Configuration can not be changed (VDE clock disabled) - exit
+    if (pDfsSource->SourceId == NvRmClockSource_Invalid)
+    {
+        *pDomainKHz = pCstate->actual_freq;
+        return;
+    }
+
+    // Convert Source ID into VDE source selector index
+    for (SourceIndex = 0; SourceIndex < AP20_VDE_SOURCES_NUMBER; SourceIndex++)
+    {
+        NvRmClockSource SourceId = pCinfo->Sources[SourceIndex];
+        if (SourceId == pDfsSource->SourceId)
+            break;
+    }
+    NV_ASSERT(SourceIndex < AP20_VDE_SOURCES_NUMBER);
+
+    // No changes in VDE clock configuration - exit
+    if ((pCstate->SourceClock == SourceIndex) &&
+        (pCstate->Divider == pDfsSource->DividerSetting))
+    {
+        *pDomainKHz = pCstate->actual_freq;
+        return;
+    }
+
+    // Set new VDE clock state and update PLL references
+    NvRmPrivLockModuleClockState();
+    pCstate->SourceClock = SourceIndex;
+    pCstate->Divider = pDfsSource->DividerSetting;
+    pCstate->actual_freq = pDfsSource->SourceKHz;
+    NvRmPrivModuleClockSet(hRmDevice, pCinfo, pCstate);
+    NvRmPrivModuleClockReAttach(hRmDevice, pCinfo, pCstate);
+    NvRmPrivUnlockModuleClockState();
+
+    *pDomainKHz = pCstate->actual_freq;
+}
+
+/*****************************************************************************/
+
+static void
+Ap20SystemClockSourceFind(
+    NvRmDeviceHandle hRmDevice,
+    NvRmFreqKHz MaxKHz,
+    NvRmFreqKHz DomainKHz,
+    NvRmDfsSource* pDfsSource)
+{
+    NvU32 i;
+    NvRmMilliVolts DivMv;
+    NvRmFreqKHz SourceKHz, M1KHz, C1KHz;
+    NV_ASSERT(DomainKHz <= MaxKHz);
+    DivMv = pDfsSource->DividerSetting = 0; // no 2ndary divider by default
+
+    // 1st try oscillator
+    SourceKHz = NvRmPrivGetClockSourceFreq(NvRmClockSource_ClkM);
+    NV_ASSERT(SourceKHz <= MaxKHz);
+    if (DomainKHz <= SourceKHz)
+    {
+        pDfsSource->SourceId = NvRmClockSource_ClkM;
+        pDfsSource->SourceKHz = SourceKHz;
+        goto get_mv;
+    }
+
+    // 2nd choice - doubler
+    SourceKHz = NvRmPrivGetClockSourceFreq(NvRmClockSource_ClkD);
+    NV_ASSERT(SourceKHz <= MaxKHz);
+    if (DomainKHz <= SourceKHz)
+    {
+        pDfsSource->SourceId = NvRmClockSource_ClkD;
+        pDfsSource->SourceKHz = SourceKHz;
+        goto get_mv;
+    }
+
+    /*
+     * 3rd option - PLLP divider per policy specification. Find
+     * the policy entry with source frequency closest and above requested.
+     * If requested frequency exceeds all policy options within domain
+     * maximum limit, select the entry with the highest possible frequency.
+     */
+    for (i = 0; i < s_Ap20PllPSystemClockPolicyEntries; i++)
+    {
+        SourceKHz = s_Ap20PllPSystemClockPolicy[i].SourceKHz;
+        if (SourceKHz > MaxKHz)
+        {
+            NV_ASSERT(i);
+            i--;
+            break;
+        }
+        if (DomainKHz <= SourceKHz)
+        {
+            break;
+        }
+    }
+    if (i == s_Ap20PllPSystemClockPolicyEntries)
+    {
+        i--;    // last/highest source is the best we can do
+    }
+    SourceKHz = s_Ap20PllPSystemClockPolicy[i].SourceKHz;
+
+    /*
+     * 4th and 5th options - PLLM1 and PLLC1 secondary dividers are configured
+     * at maximum possible frequency during initialization or whenever base PLL
+     * settings are changed. Used these options only if PLLP can not provide
+     * high enough source frequency for the requested target. Always select the
+     * source (PLLM1 or PLLC1) with bigger frequency.
+     */
+    if (SourceKHz < DomainKHz)
+    {
+        M1KHz = NvRmPrivGetClockSourceFreq(NvRmClockSource_PllM1);
+        C1KHz = NvRmPrivGetClockSourceFreq(NvRmClockSource_PllC1);
+        if ((M1KHz > SourceKHz) || (C1KHz > SourceKHz))
+        {
+            if (M1KHz > C1KHz)
+            {
+                pDfsSource->SourceKHz = M1KHz;  // Selected PLLM 2ndary divider
+                pDfsSource->SourceId = NvRmClockSource_PllM1;
+                DivMv = NvRmPrivSourceVscaleGetMV(hRmDevice,
+                    NvRmPrivGetClockSourceFreq(NvRmClockSource_PllM0));
+            }
+            else
+            {
+                pDfsSource->SourceKHz = C1KHz;  // Selected PLLC 2ndary divider
+                pDfsSource->SourceId = NvRmClockSource_PllC1;
+                DivMv = NvRmPrivSourceVscaleGetMV(hRmDevice,
+                    NvRmPrivGetClockSourceFreq(NvRmClockSource_PllC0));
+            }
+            goto get_mv;
+        }
+    }
+    pDfsSource->SourceKHz = SourceKHz;          // Selected PLLP 2ndary divider
+    pDfsSource->SourceId = s_Ap20PllPSystemClockPolicy[i].SourceId;
+    pDfsSource->DividerSetting = s_Ap20PllPSystemClockPolicy[i].DividerSetting;
+    DivMv = NvRmPrivSourceVscaleGetMV(hRmDevice,
+        NvRmPrivGetClockSourceFreq(NvRmClockSource_PllP0));
+
+get_mv:
+    // Finally get operational voltage for found source
+    pDfsSource->MinMv = NvRmPrivModuleVscaleGetMV(
+        hRmDevice, NvRmPrivModuleID_System, pDfsSource->SourceKHz);
+    if (pDfsSource->MinMv < DivMv)
+        pDfsSource->MinMv = DivMv;
+}
+
+static void
+Ap20SystemBusClockConfigure(
+    NvRmDeviceHandle hRmDevice,
+    NvRmFreqKHz MaxKHz,
+    NvRmFreqKHz* pDomainKHz,
+    const NvRmDfsSource* pDfsSource)
+{
+    NvRmClockSource SourceId = pDfsSource->SourceId;
+    const NvRmCoreClockInfo* pCinfo =
+        NvRmPrivGetClockSourceHandle(NvRmClockSource_SystemBus)->pInfo.pCore;
+
+    switch(SourceId)
+    {
+        case NvRmClockSource_PllP2:
+            // Reconfigure PLLP variable divider if it is used as a source
+            NvRmPrivDividerSet(hRmDevice,
+                NvRmPrivGetClockSourceHandle(SourceId)->pInfo.pDivider,
+                pDfsSource->DividerSetting);
+            // fall through
+        case NvRmClockSource_PllC1:
+        case NvRmClockSource_PllM1:
+        case NvRmClockSource_ClkD:
+        case NvRmClockSource_ClkM:
+            break;  // fixed sources - do nothing
+        default:
+            NV_ASSERT(!"Invalid source (per policy)");
+    }
+    NV_ASSERT_SUCCESS(NvRmPrivCoreClockConfigure(
+        hRmDevice, pCinfo, MaxKHz, pDomainKHz, &SourceId));
+}
+
+static void
+Ap20SetCpuPowerGoodDelay(
+    NvRmDeviceHandle hRmDevice,
+    NvRmFreqKHz ApbKHz)
+{
+    NvU32 reg;
+    NV_ASSERT(s_Ap20CpuConfig.CpuPowerGoodUs);
+
+    // AP20 CPU power good delay is counted by h/w in APB clocks (use 
+    // 1/1000 ~ 17/16384 with 3% margin)
+    reg = ((ApbKHz * 17) >> 14) * s_Ap20CpuConfig.CpuPowerGoodUs;
+    reg = NV_DRF_NUM(APBDEV_PMC, CPUPWRGOOD_TIMER, DATA, reg);
+    NV_REGW(hRmDevice, NvRmModuleID_Pmif, 0,
+            APBDEV_PMC_CPUPWRGOOD_TIMER_0, reg);
+}
+
+/*****************************************************************************/
+
+// Fixed point calculation bits
+#define FIXED_POINT_BITS (10)
+
+static void Ap20CpuConfigInit(NvRmDeviceHandle hRmDevice)
+{
+    NvOdmPmuProperty PmuProperty;
+
+    // Init PLLX frequency steps table based on chacterization data, so that
+    // each entry corresponds to the v-scale level
+    s_Ap20CpuConfig.pPllXStepsKHz = NvRmPrivModuleVscaleGetMaxKHzList(
+        hRmDevice, NvRmModuleID_Cpu, &s_Ap20CpuConfig.PllXStepsNo);
+    NV_ASSERT(s_Ap20CpuConfig.pPllXStepsKHz && s_Ap20CpuConfig.PllXStepsNo);
+    NV_ASSERT(s_Ap20CpuConfig.pPllXStepsKHz[0] >= NVRM_PLLP_FIXED_FREQ_KHZ);
+
+    // Init CPU power good delay and Core over CPU voltage dependency
+    // parameters based on PMU property.
+    if (!NvOdmQueryGetPmuProperty(&PmuProperty))
+    {
+        PmuProperty.CpuPowerGoodUs = NVRM_DEFAULT_CPU_PWRGOOD_US;
+        PmuProperty.AccuracyPercent = NVRM_DEFAULT_PMU_ACCURACY_PCT;
+    }
+    NV_ASSERT(PmuProperty.CpuPowerGoodUs && PmuProperty.AccuracyPercent);
+    NV_ASSERT(PmuProperty.AccuracyPercent < 5);  // 5% is a must for PMU
+
+    s_Ap20CpuConfig.CpuPowerGoodUs = PmuProperty.CpuPowerGoodUs;
+    s_Ap20CpuConfig.CoreOverCpuOffset = (NV_AP20_CORE_OVER_CPU_MV * 100) /
+                                        (100 - PmuProperty.AccuracyPercent);
+    s_Ap20CpuConfig.CoreOverCpuSlope =
+        ((0x1 << FIXED_POINT_BITS) * (100 + PmuProperty.AccuracyPercent)) /
+        (100 - PmuProperty.AccuracyPercent);
+}
+
+static void
+Ap20CpuClockSourceFind(
+    NvRmDeviceHandle hRmDevice,
+    NvRmFreqKHz MaxKHz,
+    NvRmFreqKHz DomainKHz,
+    NvRmDfsSource* pDfsSource,
+    NvRmMilliVolts* pSystemMv)
+{
+    NvU32 i;
+    NvRmMilliVolts DivMv = 0;
+    NvRmMilliVolts CpuMv = 0;
+    NvRmFreqKHz SourceKHz;
+
+    NV_ASSERT(DomainKHz <= MaxKHz);
+    NV_ASSERT(s_Ap20CpuConfig.pPllXStepsKHz);
+    pDfsSource->DividerSetting = 0; // no 2ndary divider by default
+
+    // 1st try oscillator
+    SourceKHz = NvRmPrivGetClockSourceFreq(NvRmClockSource_ClkM);
+    NV_ASSERT(SourceKHz <= MaxKHz);
+    if (DomainKHz <= SourceKHz)
+    {
+        pDfsSource->SourceId = NvRmClockSource_ClkM;
+        pDfsSource->SourceKHz = SourceKHz;
+        goto get_mv;
+    }
+
+    // 2nd choice - PLLP divider per policy specification
+    SourceKHz =
+        s_Ap20PllPCpuClockPolicy[s_Ap20PllPCpuClockPolicyEntries-1].SourceKHz;
+    NV_ASSERT(SourceKHz <= MaxKHz);
+    if (DomainKHz <= SourceKHz)
+    {
+        // The requested frequency is within PLLP divider policy table, and all
+        // policy entries are within domain maximum limit. Then, find the entry
+        // with source frequency closest and above the requested.
+        for (i = 0; i < s_Ap20PllPCpuClockPolicyEntries; i++)
+        {
+            SourceKHz = s_Ap20PllPCpuClockPolicy[i].SourceKHz;
+            if (DomainKHz <= SourceKHz)
+                break;
+        }
+        if (s_Ap20PllPCpuClockPolicy[i].DividerSetting == 0)
+            pDfsSource->SourceId = NvRmClockSource_PllP0;   // Bypass 1:1 divider
+        else
+        {
+            pDfsSource->SourceId = s_Ap20PllPCpuClockPolicy[i].SourceId;
+            DivMv = NvRmPrivSourceVscaleGetMV(hRmDevice,
+                NvRmPrivGetClockSourceFreq(NvRmClockSource_PllP0));
+        }
+        pDfsSource->SourceKHz = s_Ap20PllPCpuClockPolicy[i].SourceKHz;
+        pDfsSource->DividerSetting = s_Ap20PllPCpuClockPolicy[i].DividerSetting;
+        goto get_mv;
+    }
+
+    /*
+     * 3rd and final choice - PLLX base output. Clip PllX policy entries to
+     * domain maximum limit, and find the entry with source frequency closest
+     * and above the requested. If not found, use the last entry with the
+     * highest frequency. 
+     */
+    for (i = 0; i < s_Ap20CpuConfig.PllXStepsNo; i++)
+    {
+        SourceKHz = NV_MIN(s_Ap20CpuConfig.pPllXStepsKHz[i], MaxKHz);
+        if (DomainKHz <= SourceKHz)
+            break;
+    }
+    pDfsSource->SourceId = NvRmClockSource_PllX0;
+    pDfsSource->SourceKHz = SourceKHz;
+
+get_mv:
+    // Finally get operational voltage for found source
+    pDfsSource->MinMv = NvRmPrivModuleVscaleGetMV(
+        hRmDevice, NvRmModuleID_Cpu, pDfsSource->SourceKHz);
+#if !NV_OAL
+    NvRmPrivGetLowVoltageThreshold(NvRmDfsVoltageRailId_Cpu, &CpuMv, NULL);
+#endif
+    CpuMv = NV_MAX(CpuMv, pDfsSource->MinMv);
+    *pSystemMv = ((CpuMv * s_Ap20CpuConfig.CoreOverCpuSlope) >>
+                  FIXED_POINT_BITS) + s_Ap20CpuConfig.CoreOverCpuOffset;
+    *pSystemMv = NV_MAX(DivMv, (*pSystemMv));
+}
+
+static void
+Ap20CpuBusClockConfigure(
+    NvRmDeviceHandle hRmDevice,
+    NvRmFreqKHz MaxKHz,
+    NvRmFreqKHz* pDomainKHz,
+    const NvRmDfsSource* pDfsSource)
+{
+    NvRmFreqKHz SourceKHz = pDfsSource->SourceKHz;
+    NvRmClockSource SourceId = pDfsSource->SourceId;
+    const NvRmCoreClockInfo* pCinfo =
+        NvRmPrivGetClockSourceHandle(NvRmClockSource_CpuBus)->pInfo.pCore;
+
+    switch(SourceId)
+    {
+        case NvRmClockSource_PllX0:
+            // Reconfigure PLLX if it is used as a source
+            NvRmPrivReConfigurePllX(hRmDevice, SourceKHz);
+            break;
+        case NvRmClockSource_PllP4:
+            // Reconfigure PLLP variable divider if it is used as a source
+            NvRmPrivDividerSet(hRmDevice,
+                NvRmPrivGetClockSourceHandle(SourceId)->pInfo.pDivider,
+                pDfsSource->DividerSetting);
+            // fall through
+        case NvRmClockSource_PllP0:
+        case NvRmClockSource_ClkM:
+            break;  // fixed sources - do nothing
+        default:
+            NV_ASSERT(!"Invalid source (per policy)");
+    }
+    NV_ASSERT_SUCCESS(NvRmPrivCoreClockConfigure(
+        hRmDevice, pCinfo, MaxKHz, pDomainKHz, &SourceId));
+}
+
+/*****************************************************************************/
+/*****************************************************************************/
+
+void
+NvRmPrivAp20ScaledClockConfigInit(NvRmDeviceHandle hRmDevice)
+{
+    Ap20EmcConfigInit(hRmDevice);
+    Ap20VdeConfigInit(hRmDevice);
+    Ap20CpuConfigInit(hRmDevice);
+}
+
+NvBool NvRmPrivAp20DfsClockConfigure(
+    NvRmDeviceHandle hRmDevice,
+    const NvRmDfsFrequencies* pMaxKHz,
+    NvRmDfsFrequencies* pDfsKHz)
+{
+    NvBool Status;
+    NvRmFreqKHz FreqKHz;
+    NvRmMilliVolts SystemMv;
+    NvRmDfsSource CpuClockSource, Emc2xClockSource;
+    NvRmDfsSource SystemClockSource, VdeClockSource;
+
+    NV_ASSERT(hRmDevice);
+    NV_ASSERT(pMaxKHz && pDfsKHz);
+
+    /*
+     * Adjust System bus core clock. It should be sufficient to supply AVP,
+     * and all bus clocks. Also make sure that AHB bus frequency is above
+     * the one requested for APB clock.
+     */
+    pDfsKHz->Domains[NvRmDfsClockId_Ahb] = NV_MAX(
+        pDfsKHz->Domains[NvRmDfsClockId_Ahb],
+        pDfsKHz->Domains[NvRmDfsClockId_Apb]);
+    FreqKHz = pDfsKHz->Domains[NvRmDfsClockId_System];
+    FreqKHz = NV_MAX(FreqKHz, pDfsKHz->Domains[NvRmDfsClockId_Ahb]);
+    FreqKHz = NV_MAX(FreqKHz, pDfsKHz->Domains[NvRmDfsClockId_Avp]);
+    pDfsKHz->Domains[NvRmDfsClockId_System] = FreqKHz;
+
+#if LIMIT_SYS_TO_AHB_APB_RATIOS
+    if (pDfsKHz->Domains[NvRmDfsClockId_Apb] < (FreqKHz >> 2))
+    {
+        pDfsKHz->Domains[NvRmDfsClockId_Apb] = (FreqKHz >> 2);
+    }
+    if (pDfsKHz->Domains[NvRmDfsClockId_Ahb] < (FreqKHz >> 1))
+    {
+        pDfsKHz->Domains[NvRmDfsClockId_Ahb] = (FreqKHz >> 1);
+    }
+#endif
+
+    // Find clock sources for CPU, System, VDE and Memory clocks.
+    Ap20VdeClockSourceFind(hRmDevice,
+        pMaxKHz->Domains[NvRmDfsClockId_Vpipe],
+        pDfsKHz->Domains[NvRmDfsClockId_Vpipe],
+        &VdeClockSource);
+    Ap20SystemClockSourceFind(hRmDevice,
+        pMaxKHz->Domains[NvRmDfsClockId_System],
+        pDfsKHz->Domains[NvRmDfsClockId_System],
+        &SystemClockSource);
+    Status = Ap20Emc2xClockSourceFind(hRmDevice,
+        (pMaxKHz->Domains[NvRmDfsClockId_Emc] << 1),
+        (pDfsKHz->Domains[NvRmDfsClockId_Emc] << 1),
+        &pDfsKHz->Domains[NvRmDfsClockId_Cpu], // Need for CPU/EMC ratio policy
+        &Emc2xClockSource);
+    Ap20CpuClockSourceFind(hRmDevice,
+        pMaxKHz->Domains[NvRmDfsClockId_Cpu],
+        pDfsKHz->Domains[NvRmDfsClockId_Cpu],
+        &CpuClockSource, &SystemMv);
+    // CPU clock source may affect system core voltage as well
+    SystemMv = NV_MAX(SystemMv, SystemClockSource.MinMv);
+
+#if !NV_OAL
+    // Adjust core and cpu voltage for the new clock sources before actual
+    // change. Note that only voltage requirements for always running clocks
+    // (CPU, System, EMC) are specified explicitely. VDE voltage requirement
+    // is already integrated with other clock-gated modules.
+    NvRmPrivVoltageScale(NV_TRUE, CpuClockSource.MinMv,
+                         SystemMv, Emc2xClockSource.MinMv);
+#endif
+
+    // Configure VDE, System bus and derived clocks (do not care about MIO on
+    // AP20). Note that APB is the only clock in system complex that may have
+    // different (lower) maximum limit - pass it explicitly to set function.
+    Ap20SystemBusClockConfigure(hRmDevice,
+        pMaxKHz->Domains[NvRmDfsClockId_System],
+        &pDfsKHz->Domains[NvRmDfsClockId_System],
+        &SystemClockSource);
+    pDfsKHz->Domains[NvRmDfsClockId_Avp] = FreqKHz = // no AVP clock skipping
+        pDfsKHz->Domains[NvRmDfsClockId_System];        
+    NvRmPrivBusClockFreqSet(hRmDevice,
+        pDfsKHz->Domains[NvRmDfsClockId_System],
+        &FreqKHz,                                       // VDE decoupled
+        &pDfsKHz->Domains[NvRmDfsClockId_Ahb],
+        &pDfsKHz->Domains[NvRmDfsClockId_Apb],
+        pMaxKHz->Domains[NvRmDfsClockId_Apb]);
+    Ap20SetCpuPowerGoodDelay(hRmDevice, pDfsKHz->Domains[NvRmDfsClockId_Apb]);
+    Ap20VdeClockConfigure(hRmDevice,
+        pMaxKHz->Domains[NvRmDfsClockId_Vpipe],
+        &pDfsKHz->Domains[NvRmDfsClockId_Vpipe],
+        &VdeClockSource);
+
+    // Configure Memory clocks and convert frequency to DFS EMC 1x domain
+    FreqKHz = pDfsKHz->Domains[NvRmDfsClockId_Emc] << 1;
+    Ap20Emc2xClockConfigure(hRmDevice,
+        (pMaxKHz->Domains[NvRmDfsClockId_Emc] << 1),
+        &FreqKHz, &Emc2xClockSource);
+    pDfsKHz->Domains[NvRmDfsClockId_Emc] = FreqKHz >> 1;
+
+    // Configure CPU core clock 
+    Ap20CpuBusClockConfigure(hRmDevice,
+        pMaxKHz->Domains[NvRmDfsClockId_Cpu],
+        &pDfsKHz->Domains[NvRmDfsClockId_Cpu],
+        &CpuClockSource);
+
+#if !NV_OAL
+    // Adjust core and cpu voltage after actual clock change.
+    NvRmPrivVoltageScale(NV_FALSE, CpuClockSource.MinMv,
+                         SystemMv, Emc2xClockSource.MinMv);
+#endif
+    return Status;
+}
+
+void
+NvRmPrivAp20DfsClockFreqGet(
+    NvRmDeviceHandle hRmDevice,
+    NvRmDfsFrequencies* pDfsKHz)
+{
+    NvRmFreqKHz SystemFreq;
+    const NvRmCoreClockInfo* pCinfo;
+    NV_ASSERT(hRmDevice && pDfsKHz);
+
+    // Get frequencies of the System core clock, AVP clock (the same as System
+    // - no clock skipping), AHB, APB, and V-pipe bus clock. Note that on AP20
+    // V-pipe is decoupled from the System bus, and has its own controls.
+    pCinfo = NvRmPrivGetClockSourceHandle(NvRmClockSource_SystemBus)->pInfo.pCore;
+    SystemFreq = NvRmPrivCoreClockFreqGet(hRmDevice, pCinfo);
+    pDfsKHz->Domains[NvRmDfsClockId_System] = SystemFreq;
+    pDfsKHz->Domains[NvRmDfsClockId_Avp] = SystemFreq;
+
+    NvRmPrivBusClockFreqGet(
+        hRmDevice, SystemFreq,
+        &pDfsKHz->Domains[NvRmDfsClockId_Vpipe],
+        &pDfsKHz->Domains[NvRmDfsClockId_Ahb],
+        &pDfsKHz->Domains[NvRmDfsClockId_Apb]);
+    Ap20VdeClockStateUpdate(hRmDevice);
+    pDfsKHz->Domains[NvRmDfsClockId_Vpipe] =
+        s_Ap20VdeConfig.pVdeState->actual_freq;
+
+    // Get CPU core clock frequencies
+    pCinfo = NvRmPrivGetClockSourceHandle(NvRmClockSource_CpuBus)->pInfo.pCore;
+    pDfsKHz->Domains[NvRmDfsClockId_Cpu] =
+        NvRmPrivCoreClockFreqGet(hRmDevice, pCinfo);
+
+    // Get EMC clock frequency (DFS monitors EMC 1x domain)
+    Ap20Emc2xClockStateUpdate(hRmDevice);   // Get EMC2x clock state from h/w
+    pDfsKHz->Domains[NvRmDfsClockId_Emc] =
+        (s_Ap20EmcConfig.pEmc2xState->actual_freq >> 1);
+}
+
+void
+NvRmPrivAp20DfsSuspendFreqGet(
+    NvRmDeviceHandle hRmDevice,
+    NvRmMilliVolts TargetMv,
+    NvRmDfsFrequencies* pDfsKHz)
+{
+    NvU32 i;
+    NvRmMilliVolts v;
+    NvRmFreqKHz Fa, Fb, f;
+    NvRmDfsSource DfsClockSource;
+    NvRmFreqKHz CpuMaxKHz =
+        NvRmPrivGetSocClockLimits(NvRmModuleID_Cpu)->MaxKHz;
+    NvRmFreqKHz SysMaxKHz =
+        NvRmPrivGetSocClockLimits(NvRmPrivModuleID_System)->MaxKHz;
+    NV_ASSERT(hRmDevice && pDfsKHz);
+
+    // Binary search for maximum System/Avp frequency, with source that
+    // can be used at target voltage or below
+    Fb = SysMaxKHz;
+    Fa = NvRmPrivGetClockSourceFreq(NvRmClockSource_ClkM);
+    NV_ASSERT(Fa <= Fb);
+    while ((Fb - Fa) > 1000)    // 1MHz resolution
+    {
+        f = (Fa + Fb) >> 1;
+        Ap20SystemClockSourceFind(hRmDevice, SysMaxKHz, f, &DfsClockSource);
+        v = DfsClockSource.MinMv;
+        if (v <= TargetMv)
+            Fa = f;
+        else
+            Fb = f;
+    }
+    pDfsKHz->Domains[NvRmDfsClockId_System] = Fa;
+    pDfsKHz->Domains[NvRmDfsClockId_Avp] = Fa;
+    pDfsKHz->Domains[NvRmDfsClockId_Ahb] = Fa;
+    pDfsKHz->Domains[NvRmDfsClockId_Apb] = Fa;
+    // On AP20 Vde clock has its own voltage scale; however, it is disabled
+    // on suspend entry; hence, the setting below is "don't care"
+    pDfsKHz->Domains[NvRmDfsClockId_Vpipe] = Fa;
+
+    // If PLLM0 entry in EMC scaling table is valid, search the table for
+    // the entry below and closest to the traget voltage. Otherwise, there
+    // is no EMC scaling - just return current EMC frequency.
+    pDfsKHz->Domains[NvRmDfsClockId_Emc] =
+        (s_Ap20EmcConfig.pEmc2xState->actual_freq >> 1);
+    if (s_Ap20EmcConfigSortedTable[0].Emc2xKHz != 0)
+    {
+        for (i = 0; i < (NVRM_AP20_DFS_EMC_FREQ_STEPS - 1); i++)
+        {
+            if ((s_Ap20EmcConfigSortedTable[i+1].Emc2xKHz == 0) ||
+                (s_Ap20EmcConfigSortedTable[i].pOdmEmcConfig->EmcCoreVoltageMv
+                 <= TargetMv))
+                break;  // exit if found entry or next entry is invalid
+        }
+        pDfsKHz->Domains[NvRmDfsClockId_Emc] =
+            (s_Ap20EmcConfigSortedTable[i].Emc2xKHz >> 1);
+        f = s_Ap20EmcConfigSortedTable[i].CpuLimitKHz;
+        CpuMaxKHz = NV_MIN(CpuMaxKHz, f);     // throttle CPU if necessary
+    }
+
+    // CPU voltage is turned Off in suspend. Use CPU frequency derived from
+    // PLLP as LP1 resume start-up clock
+    f = s_Ap20PllPCpuClockPolicy[s_Ap20PllPCpuClockPolicyEntries-1].SourceKHz;
+    pDfsKHz->Domains[NvRmDfsClockId_Cpu] = NV_MIN(CpuMaxKHz, f);
+
+    NvOsDebugPrintf("LP1 entry/exit kHz: Cpu = %6d, Emc = %6d, Sys = %6d\n",
+                    pDfsKHz->Domains[NvRmDfsClockId_Cpu],
+                    pDfsKHz->Domains[NvRmDfsClockId_Emc],
+                    pDfsKHz->Domains[NvRmDfsClockId_System]);
+}
+
+/*****************************************************************************/
+/*****************************************************************************/
+
+void
+NvRmPrivAp20FastClockConfig(NvRmDeviceHandle hRmDevice)
+{
+#if !NV_OAL
+    NvU32 divc1, divm1, divp2;
+    NvRmFreqKHz SclkKHz, CpuKHz, PllP2KHz, PllM1KHz, PllC1KHz;
+    NvRmDfsSource VdeSource;
+
+    NvRmFreqKHz FreqKHz = NvRmPrivGetClockSourceFreq(NvRmClockSource_PllM0);
+    if (NvRmPrivGetExecPlatform(hRmDevice) != ExecPlatform_Soc)
+        return; // fast clocks on SoC only
+
+    // Set fastest EMC/MC configuration provided PLLM0 boot frequency matches
+    // one of the pre-defined configurations, i.e, it is the first entry in the
+    // sorted table
+    if ((s_Ap20EmcConfigSortedTable[0].Emc2xKHz == FreqKHz) &&
+        (s_Ap20EmcConfig.Index != 0))
+    {
+        Ap20EmcSwitchToUndividedPllM0(hRmDevice, s_Ap20EmcConfigSortedTable);
+        s_Ap20EmcConfig.Index = 0;
+    }
+
+    // Set AVP/System Bus clock (now, with nominal core voltage it can be up
+    // to SoC maximum). First determine settings for PLLP/PLLM/PLLC secondary
+    // dividers to get maximum possible frequency on PLLP_OUT2, or PLLM_OUT1
+    // or PLLC_OUT1 outputs.
+    SclkKHz = NvRmPrivGetSocClockLimits(NvRmModuleID_Avp)->MaxKHz;
+    NV_ASSERT(SclkKHz);
+
+    FreqKHz = NvRmPrivGetClockSourceFreq(NvRmClockSource_PllP0);
+    PllP2KHz = SclkKHz;
+    divp2 = NvRmPrivFindFreqMaxBelow(
+        NvRmClockDivider_Fractional_2, FreqKHz, PllP2KHz, &PllP2KHz);
+
+    FreqKHz = NvRmPrivGetClockSourceFreq(NvRmClockSource_PllM0);
+    PllM1KHz = SclkKHz;
+    divm1 = NvRmPrivFindFreqMaxBelow(
+        NvRmClockDivider_Fractional_2, FreqKHz, PllM1KHz, &PllM1KHz);
+
+    FreqKHz = NvRmPrivGetClockSourceFreq(NvRmClockSource_PllC0);
+    PllC1KHz = SclkKHz;
+    divc1 = NvRmPrivFindFreqMaxBelow(
+        NvRmClockDivider_Fractional_2, FreqKHz, PllC1KHz, &PllC1KHz);
+
+    // Now configure secondary dividers and select the output with highest
+    // frequency // as a source for the system bus clock.
+    SclkKHz = NV_MAX(PllC1KHz, NV_MAX(PllM1KHz, PllP2KHz)); 
+    NvRmPrivDividerSet(
+        hRmDevice,
+        NvRmPrivGetClockSourceHandle(NvRmClockSource_PllP2)->pInfo.pDivider,
+        divp2);
+    NvRmPrivDividerSet(
+        hRmDevice,
+        NvRmPrivGetClockSourceHandle(NvRmClockSource_PllM1)->pInfo.pDivider,
+        divm1);
+    NvRmPrivDividerSet(
+        hRmDevice,
+        NvRmPrivGetClockSourceHandle(NvRmClockSource_PllC1)->pInfo.pDivider,
+        divc1);
+    if (SclkKHz == PllP2KHz)
+    {
+        NvRmPrivCoreClockSet(hRmDevice,
+            NvRmPrivGetClockSourceHandle(NvRmClockSource_SystemBus)->pInfo.pCore,
+            NvRmClockSource_PllP2, 0, 0);
+    }
+    else if (SclkKHz == PllM1KHz)
+    {
+        NvRmPrivCoreClockSet(hRmDevice,
+            NvRmPrivGetClockSourceHandle(NvRmClockSource_SystemBus)->pInfo.pCore,
+            NvRmClockSource_PllM1, 0, 0);
+    }
+    else
+    {
+        NvRmPrivCoreClockSet(hRmDevice,
+            NvRmPrivGetClockSourceHandle(NvRmClockSource_SystemBus)->pInfo.pCore,
+            NvRmClockSource_PllC1, 0, 0);
+    }
+    NvRmPrivBusClockInit(hRmDevice, SclkKHz);
+    Ap20SetCpuPowerGoodDelay(
+        hRmDevice, NvRmPrivGetClockSourceFreq(NvRmClockSource_Apb));
+
+    // Set VDE maximum clock (VDE is disabled after basic reset - need to
+    // temporary enable it for configuration)
+    FreqKHz = NvRmPrivGetSocClockLimits(NvRmModuleID_Vde)->MaxKHz;
+    NvRmPowerModuleClockControl(hRmDevice, NvRmModuleID_Vde, 0, NV_TRUE);
+    Ap20VdeClockSourceFind(hRmDevice, FreqKHz, FreqKHz, &VdeSource);
+    Ap20VdeClockConfigure(hRmDevice, FreqKHz, &FreqKHz, &VdeSource);
+    NvRmPowerModuleClockControl(hRmDevice, NvRmModuleID_Vde, 0, NV_FALSE);
+
+    // Set PLLX0 and CPU clock to SoC maximum (can be done now, when core
+    // voltage is guaranteed to be nominal)
+    CpuKHz = NvRmPrivGetSocClockLimits(NvRmModuleID_Cpu)->MaxKHz;
+    FreqKHz = NvRmPrivGetClockSourceFreq(NvRmClockSource_PllX0);
+    if (CpuKHz != FreqKHz)
+    {
+        NvRmPrivReConfigurePllX(hRmDevice, CpuKHz);
+    }
+    NvRmPrivCoreClockSet(hRmDevice,
+        NvRmPrivGetClockSourceHandle(NvRmClockSource_CpuBus)->pInfo.pCore,
+        NvRmClockSource_PllX0, 0, 0);
+
+    // Set PLLP4 fixed frequency to be used by external device(s)
+    NvRmPrivDividerSet(
+        hRmDevice,
+        NvRmPrivGetClockSourceHandle(NvRmClockSource_PllP4)->pInfo.pDivider,
+        NVRM_AP20_FIXED_PLLP4_SETTING);
+#endif
+}
+
+/*****************************************************************************/
+
+void
+NvRmPrivAp20SdioTapDelayConfigure(
+    NvRmDeviceHandle hRmDevice,
+    NvRmModuleID ModuleId,
+    NvU32 ClkSourceOffset,
+    NvRmFreqKHz ConfiguredFreqKHz)
+{
+    NvU32 Module   = NVRM_MODULE_ID_MODULE( ModuleId );
+    NvU32 Instance = NVRM_MODULE_ID_INSTANCE( ModuleId );
+    const NvOdmQuerySdioInterfaceProperty *pSdioInterfaceProps = NULL;
+    NvU32 ClkSrcReg;
+    
+    if (Module != NvRmModuleID_Sdio)
+        return;
+    pSdioInterfaceProps = NvOdmQueryGetSdioInterfaceProperty(Instance);
+    if (pSdioInterfaceProps == NULL)
+        return;
+
+    // Allow only less than 16 as tap delay.
+    NV_ASSERT(pSdioInterfaceProps->TapDelay < 0x10);
+    
+    if (pSdioInterfaceProps->TapDelay > 0)
+    {
+        ClkSrcReg = NV_REGR(hRmDevice, NvRmPrivModuleID_ClockAndReset, 0, 
+                        ClkSourceOffset);
+
+        // CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_INT_FB_SEL_RANGE 
+        ClkSrcReg = NV_FLD_SET_DRF_NUM(CLK_RST_CONTROLLER, CLK_SOURCE_SDMMC1,
+                                SDMMC1_INT_FB_SEL, 1, ClkSrcReg);
+        
+        // CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_INT_FB_DLY_RANGE
+        ClkSrcReg = NV_FLD_SET_DRF_NUM(CLK_RST_CONTROLLER, CLK_SOURCE_SDMMC1,
+                            SDMMC1_INT_FB_DLY, pSdioInterfaceProps->TapDelay, ClkSrcReg);
+        NV_REGW(hRmDevice, NvRmPrivModuleID_ClockAndReset, 0, 
+                        ClkSourceOffset, ClkSrcReg);
+    }
+}
+
+/*****************************************************************************/
diff --git a/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_clocks.c b/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_clocks.c
new file mode 100644
index 000000000000..8351a096e773
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_clocks.c
@@ -0,0 +1,1323 @@
+/*
+ * Copyright (c) 2008-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include "nvcommon.h"
+#include "nvassert.h"
+#include "nvrm_clocks.h"
+#include "nvrm_chiplib.h"
+#include "nvrm_hwintf.h"
+#include "nvrm_module.h"
+#include "nvrm_drf.h"
+#include "nvrm_pmu_private.h"
+#include "ap20/arclk_rst.h"
+#include "ap20/arahb_arbc.h"
+#include "ap20/arapbpm.h"
+#include "ap15/ap15rm_private.h"
+#include "ap20rm_clocks.h"
+#include "ap20/arfuse.h"
+
+
+// This list requires pre-sorted info in bond-out registers order and bond-out
+// register bit shift order (MSB-to-LSB).
+static const NvU32 s_Ap20BondOutTable[] =
+{
+    // BOND_OUT_L bits
+    NVRM_DEVICE_UNKNOWN,  // NV_DEVID_CPU
+    NVRM_DEVICE_UNKNOWN,
+    NVRM_DEVICE_UNKNOWN,
+    NVRM_MODULE_ID( NvRmModuleID_Ac97,                          0 ),
+    NVRM_MODULE_ID( NvRmModuleID_Rtc,                           0 ),
+    NVRM_MODULE_ID( NvRmModuleID_Timer,                         0 ),
+    NVRM_MODULE_ID( NvRmModuleID_Uart,                          0 ),
+    NVRM_MODULE_ID( NvRmModuleID_Uart,                          1 ),
+    NVRM_MODULE_ID( NvRmPrivModuleID_Gpio,                      0 ),
+    NVRM_MODULE_ID( NvRmModuleID_Sdio,                          1 ),
+    NVRM_MODULE_ID( NvRmModuleID_Spdif,                         0 ),
+    NVRM_MODULE_ID( NvRmModuleID_I2s,                           0 ),
+    NVRM_MODULE_ID( NvRmModuleID_I2c,                           0 ),
+    NVRM_MODULE_ID( NvRmModuleID_Nand,                          0 ),
+    NVRM_MODULE_ID( NvRmModuleID_Sdio,                          0 ),
+    NVRM_MODULE_ID( NvRmModuleID_Sdio,                          3 ),
+    NVRM_MODULE_ID( NvRmModuleID_Twc,                           0 ),
+    NVRM_MODULE_ID( NvRmModuleID_Pwm,                           0 ),
+    NVRM_MODULE_ID( NvRmModuleID_I2s,                           1 ),
+    NVRM_MODULE_ID( NvRmModuleID_Epp,                           0 ),
+    NVRM_MODULE_ID( NvRmModuleID_Vi,                            0 ),
+    NVRM_MODULE_ID( NvRmModuleID_2D,                            0 ),
+    NVRM_MODULE_ID( NvRmModuleID_Usb2Otg,                       0 ),
+    NVRM_MODULE_ID( NvRmModuleID_Isp,                           0 ),
+    NVRM_MODULE_ID( NvRmModuleID_3D,                            0 ),
+    NVRM_MODULE_ID( NvRmModuleID_Ide,                           0 ),
+    NVRM_MODULE_ID( NvRmModuleID_Display,                       1 ),
+    NVRM_MODULE_ID( NvRmModuleID_Display,                       0 ),
+    NVRM_MODULE_ID( NvRmModuleID_GraphicsHost,                  0 ),
+    NVRM_MODULE_ID( NvRmModuleID_Vcp,                           0 ),
+    NVRM_MODULE_ID( NvRmModuleID_CacheMemCtrl,                  0 ),
+    NVRM_DEVICE_UNKNOWN,    // NV_DEVID_COP_CACHE
+
+    // BOND_OUT_H bits
+    NVRM_MODULE_ID( NvRmPrivModuleID_MemoryController,          0 ),
+    NVRM_DEVICE_UNKNOWN,    // NV_DEVID_AHB_DMA
+    NVRM_MODULE_ID( NvRmPrivModuleID_ApbDma,                    0 ),
+    NVRM_DEVICE_UNKNOWN,
+    NVRM_MODULE_ID( NvRmModuleID_Kbc,                           0 ),
+    NVRM_MODULE_ID( NvRmModuleID_SysStatMonitor,                0 ),
+    NVRM_DEVICE_UNKNOWN,    // PMC
+    NVRM_MODULE_ID( NvRmModuleID_Fuse,                          0 ),
+    NVRM_MODULE_ID( NvRmModuleID_KFuse,                         0 ),
+    NVRM_DEVICE_UNKNOWN,    // SBC1
+    NVRM_MODULE_ID( NvRmModuleID_Nor,                           0 ),
+    NVRM_MODULE_ID( NvRmModuleID_Spi,                           0 ),
+    NVRM_DEVICE_UNKNOWN,    // SBC2
+    NVRM_MODULE_ID( NvRmModuleID_Xio,                           0 ),
+    NVRM_DEVICE_UNKNOWN,    // SBC3
+    NVRM_MODULE_ID( NvRmModuleID_Dvc,                           0 ),
+    NVRM_MODULE_ID( NvRmModuleID_Dsi,                           0 ),
+    NVRM_MODULE_ID( NvRmModuleID_Tvo,                           0 ),
+    NVRM_MODULE_ID( NvRmModuleID_Mipi,                          0 ),
+    NVRM_MODULE_ID( NvRmModuleID_Hdmi,                          0 ),
+    NVRM_MODULE_ID( NvRmModuleID_Csi,                           0 ),
+    NVRM_DEVICE_UNKNOWN,    // TVDAC
+    NVRM_MODULE_ID( NvRmModuleID_I2c,                           1 ),
+    NVRM_MODULE_ID( NvRmModuleID_Uart,                          2 ),
+    NVRM_DEVICE_UNKNOWN,    // SPROM
+    NVRM_MODULE_ID( NvRmPrivModuleID_ExternalMemoryController,  0 ),
+    NVRM_MODULE_ID( NvRmModuleID_Usb2Otg,                       1 ),
+    NVRM_MODULE_ID( NvRmModuleID_Usb2Otg,                       2 ),
+    NVRM_MODULE_ID( NvRmModuleID_Mpe,                           0 ),
+    NVRM_MODULE_ID( NvRmModuleID_Vde,                           0 ),
+    NVRM_MODULE_ID( NvRmModuleID_BseA,                          0 ),
+    NVRM_DEVICE_UNKNOWN,    // BSEV
+
+    // BOND_OUT_U bits
+    NVRM_DEVICE_UNKNOWN,    // SPEEDO
+    NVRM_MODULE_ID( NvRmModuleID_Uart, 3),
+    NVRM_MODULE_ID( NvRmModuleID_Uart, 4),
+    NVRM_MODULE_ID( NvRmModuleID_I2c, 2),
+    NVRM_DEVICE_UNKNOWN,    // SBC4
+    NVRM_MODULE_ID( NvRmModuleID_Sdio, 2),
+    NVRM_MODULE_ID( NvRmPrivModuleID_Pcie, 0),
+    NVRM_MODULE_ID( NvRmModuleID_OneWire, 0),
+    NVRM_DEVICE_UNKNOWN,    // AFI
+    NVRM_DEVICE_UNKNOWN,    // CSTIE
+    NVRM_DEVICE_UNKNOWN,
+    NVRM_MODULE_ID( NvRmModuleID_AvpUcq, 0),
+    NVRM_DEVICE_UNKNOWN,
+    NVRM_DEVICE_UNKNOWN,
+    NVRM_DEVICE_UNKNOWN,
+    NVRM_DEVICE_UNKNOWN,
+    NVRM_DEVICE_UNKNOWN,
+    NVRM_DEVICE_UNKNOWN,
+    NVRM_DEVICE_UNKNOWN,
+    NVRM_DEVICE_UNKNOWN,
+    NVRM_DEVICE_UNKNOWN,    // IRAMA
+    NVRM_DEVICE_UNKNOWN,    // IRAMB
+    NVRM_DEVICE_UNKNOWN,    // IRAMC
+    NVRM_DEVICE_UNKNOWN,    // IRAMD
+    NVRM_DEVICE_UNKNOWN,    // CRAM2
+    NVRM_DEVICE_UNKNOWN,    // SYNC_CLOCK_DOUBLER
+    NVRM_DEVICE_UNKNOWN,    // CLK_M_DOUBLER
+    NVRM_DEVICE_UNKNOWN,
+    NVRM_DEVICE_UNKNOWN,    // SUS_OUT
+    NVRM_DEVICE_UNKNOWN,    // DEV2_OUT
+    NVRM_DEVICE_UNKNOWN,    // DEV1_OUT
+    NVRM_DEVICE_UNKNOWN,
+};
+
+void
+NvRmPrivAp20GetBondOut( NvRmDeviceHandle hDevice,
+                        const NvU32      **pTable,
+                        NvU32            *bondOut )
+{
+    *pTable = s_Ap20BondOutTable;
+    bondOut[0] = NV_REGR(hDevice, NvRmPrivModuleID_ClockAndReset, 0,
+                                    CLK_RST_CONTROLLER_BOND_OUT_L_0);
+    bondOut[1] = NV_REGR(hDevice, NvRmPrivModuleID_ClockAndReset, 0,
+                                    CLK_RST_CONTROLLER_BOND_OUT_H_0);
+    bondOut[2] = NV_REGR(hDevice, NvRmPrivModuleID_ClockAndReset, 0,
+                                    CLK_RST_CONTROLLER_BOND_OUT_U_0);
+}
+
+
+// Top level AP20 clock enable register control macro
+#define CLOCK_ENABLE( rm, offset, field, Enable) \
+    do \
+    {   \
+        NvU32 regaddr; \
+        NvU32 reg = 0; \
+        if (Enable == ModuleClockState_Enable) \
+        {   \
+            reg = NV_FLD_SET_DRF_NUM(CLK_RST_CONTROLLER, CLK_ENB_##offset##_SET, SET_CLK_ENB_##field, 1, reg); \
+            regaddr = CLK_RST_CONTROLLER_CLK_ENB_##offset##_SET_0; \
+        }   \
+        else \
+        {   \
+            reg = NV_FLD_SET_DRF_NUM(CLK_RST_CONTROLLER, CLK_ENB_##offset##_CLR, CLR_CLK_ENB_##field, 1, reg); \
+            regaddr = CLK_RST_CONTROLLER_CLK_ENB_##offset##_CLR_0; \
+        }   \
+        NV_REGW((rm), NvRmPrivModuleID_ClockAndReset, 0, regaddr, reg); \
+    } while (0)
+
+
+
+void
+Ap20EnableModuleClock(
+    NvRmDeviceHandle hDevice,
+    NvRmModuleID ModuleId,
+    ModuleClockState ClockState)
+{
+    // Extract module and instance from composite module id.
+    NvU32 Module   = NVRM_MODULE_ID_MODULE( ModuleId );
+    NvU32 Instance = NVRM_MODULE_ID_INSTANCE( ModuleId );
+
+    if (ClockState == ModuleClockState_Enable)
+    {
+        NvRmPrivConfigureClockSource(hDevice, ModuleId, NV_TRUE);
+    }
+    switch ( Module ) {
+        case NvRmModuleID_CacheMemCtrl:
+            NV_ASSERT( Instance < 2 );
+            if( Instance == 0 )
+            {
+                NV_ASSERT(!"AP20 doesn't have such device");
+            }
+            else if( Instance == 1 )
+            {
+                CLOCK_ENABLE( hDevice, L, CACHE2, ClockState );
+            }
+            break;
+        case NvRmModuleID_Vcp:
+            NV_ASSERT( Instance == 0 );
+            CLOCK_ENABLE( hDevice, L, VCP, ClockState );
+            break;
+        case NvRmModuleID_GraphicsHost:
+            NV_ASSERT( Instance == 0 );
+            CLOCK_ENABLE( hDevice, L, HOST1X, ClockState );
+            break;
+        case NvRmModuleID_Display:
+            NV_ASSERT( Instance < 2 );
+            if( Instance == 0 )
+            {
+                CLOCK_ENABLE( hDevice, L, DISP1, ClockState );
+            }
+            else if( Instance == 1 )
+            {
+                CLOCK_ENABLE( hDevice, L, DISP2, ClockState );
+            }
+            break;
+        case NvRmModuleID_Ide:
+            NV_ASSERT( Instance == 0 );
+            CLOCK_ENABLE( hDevice, L, IDE, ClockState );
+            break;
+        case NvRmModuleID_3D:
+            NV_ASSERT( Instance == 0 );
+            CLOCK_ENABLE( hDevice, L, 3D, ClockState );
+            break;
+        case NvRmModuleID_Isp:
+            NV_ASSERT( Instance == 0 );
+            CLOCK_ENABLE( hDevice, L, ISP, ClockState );
+            break;
+        case NvRmModuleID_Usb2Otg:
+            if (Instance == 0)
+            {
+                CLOCK_ENABLE( hDevice, L, USBD, ClockState );
+            }
+            else if (Instance == 1)
+            {
+                CLOCK_ENABLE( hDevice, H, USB2, ClockState );
+            }
+            else if (Instance == 2)
+            {
+                CLOCK_ENABLE( hDevice, H, USB3, ClockState );
+            }
+            else
+            {
+                NV_ASSERT(!"Invalid USB instance");
+            }
+            break;
+        case NvRmModuleID_2D:
+            NV_ASSERT( Instance == 0 );
+            CLOCK_ENABLE( hDevice, L, 2D, ClockState );
+            break;
+        case NvRmModuleID_Epp:
+            NV_ASSERT( Instance == 0 );
+            CLOCK_ENABLE( hDevice, L, EPP, ClockState );
+            break;
+        case NvRmModuleID_Vi:
+            NV_ASSERT( Instance == 0 );
+            CLOCK_ENABLE( hDevice, L, VI, ClockState );
+            break;
+        case NvRmModuleID_I2s:
+            if( Instance == 0 )
+            {
+                CLOCK_ENABLE( hDevice, L, I2S1, ClockState );
+            }
+            else if( Instance == 1 )
+            {
+                CLOCK_ENABLE( hDevice, L, I2S2, ClockState );
+            } else
+            {
+                NV_ASSERT(!"Invalid I2S instance");
+            }
+            break;
+        case NvRmModuleID_Twc:
+            NV_ASSERT( Instance == 0 );
+            CLOCK_ENABLE( hDevice, L, TWC, ClockState );
+            break;
+        case NvRmModuleID_Pwm:
+            NV_ASSERT( Instance == 0 );
+            CLOCK_ENABLE( hDevice, L, PWM, ClockState );
+            break;
+        case NvRmModuleID_Sdio:
+            if( Instance == 0 )
+            {
+                CLOCK_ENABLE( hDevice, L, SDMMC1, ClockState );
+            }
+            else if( Instance == 1 )
+            {
+                CLOCK_ENABLE( hDevice, L, SDMMC2, ClockState );
+            } else if (Instance == 2)
+            {
+                CLOCK_ENABLE( hDevice, U, SDMMC3, ClockState );
+            } else if (Instance == 3)
+            {
+                CLOCK_ENABLE( hDevice, L, SDMMC4, ClockState );
+            } else
+            {
+                NV_ASSERT(!"Invalid SDIO instance");
+            }
+            break;
+        case NvRmModuleID_Spdif:
+            NV_ASSERT( Instance < 1 );
+            CLOCK_ENABLE( hDevice, L, SPDIF, ClockState );
+            break;
+        case NvRmModuleID_Nand:
+            NV_ASSERT( Instance == 0 );
+            CLOCK_ENABLE( hDevice, L, NDFLASH, ClockState );
+            break;
+        case NvRmModuleID_I2c:
+            if( Instance == 0 )
+            {
+                CLOCK_ENABLE( hDevice, L, I2C1, ClockState );
+            }
+            else if( Instance == 1 )
+            {
+                CLOCK_ENABLE( hDevice, H, I2C2, ClockState );
+            } else if (Instance == 2)
+            {
+                CLOCK_ENABLE( hDevice, U, I2C3, ClockState );
+            } else
+            {
+                NV_ASSERT(!"Invalid I2C instance");
+            }
+            break;
+        case NvRmPrivModuleID_Gpio:
+            NV_ASSERT( Instance == 0 );
+            CLOCK_ENABLE( hDevice, L, GPIO, ClockState );
+            break;
+        case NvRmModuleID_Uart:
+            if( Instance == 0 )
+            {
+                CLOCK_ENABLE( hDevice, L, UARTA, ClockState );
+            }
+            else if( Instance == 1 )
+            {
+                CLOCK_ENABLE( hDevice, L, UARTB, ClockState );
+            }
+            else if ( Instance == 2)
+            {
+                CLOCK_ENABLE( hDevice, H, UARTC, ClockState );
+            } else if (Instance == 3)
+            {
+                CLOCK_ENABLE( hDevice, U, UARTD, ClockState );
+            } else if ( Instance == 4)
+            {
+                CLOCK_ENABLE( hDevice, U, UARTE, ClockState );
+            } else
+            {
+                NV_ASSERT(!"Invlaid UART instance");
+            }
+            break;
+        case NvRmModuleID_Vfir:
+            // Same as UARTB
+            NV_ASSERT( Instance == 0 );
+            CLOCK_ENABLE( hDevice, L, UARTB, ClockState );
+            break;
+        case NvRmModuleID_Ac97:
+            NV_ASSERT( Instance == 0 );
+            CLOCK_ENABLE( hDevice, L, AC97, ClockState );
+            break;
+        case NvRmModuleID_Rtc:
+            NV_ASSERT( Instance == 0 );
+            CLOCK_ENABLE( hDevice, L, RTC, ClockState );
+            break;
+        case NvRmModuleID_Timer:
+            NV_ASSERT( Instance == 0 );
+            CLOCK_ENABLE( hDevice, L, TMR, ClockState );
+            break;
+        case NvRmModuleID_BseA:
+            NV_ASSERT( Instance == 0 );
+            CLOCK_ENABLE( hDevice, H, BSEA, ClockState );
+            break;
+        case NvRmModuleID_Vde:
+            NV_ASSERT( Instance == 0 );
+            CLOCK_ENABLE( hDevice, H, VDE, ClockState );
+            CLOCK_ENABLE( hDevice, H, BSEV, ClockState );
+            break;
+        case NvRmModuleID_Mpe:
+            NV_ASSERT( Instance == 0 );
+            CLOCK_ENABLE( hDevice, H, MPE, ClockState );
+            break;
+        case NvRmModuleID_Tvo:
+            NV_ASSERT( Instance == 0 );
+            CLOCK_ENABLE( hDevice, H, TVO, ClockState );
+            CLOCK_ENABLE( hDevice, H, TVDAC, ClockState );
+            break;
+        case NvRmModuleID_Csi:
+            NV_ASSERT( Instance == 0 );
+            CLOCK_ENABLE( hDevice, H, CSI, ClockState );
+            break;
+        case NvRmModuleID_Hdmi:
+            NV_ASSERT( Instance == 0 );
+            CLOCK_ENABLE( hDevice, H, HDMI, ClockState );
+            break;
+        case NvRmModuleID_Mipi:
+            NV_ASSERT( Instance == 0 );
+            CLOCK_ENABLE( hDevice, H, MIPI, ClockState );
+            break;
+        case NvRmModuleID_Dsi:
+            NV_ASSERT( Instance == 0 );
+            CLOCK_ENABLE( hDevice, H, DSI, ClockState );
+            break;
+        case NvRmModuleID_Xio:
+            NV_ASSERT( Instance == 0 );
+            CLOCK_ENABLE( hDevice, H, XIO, ClockState );
+            break;
+        case NvRmModuleID_Spi:
+            NV_ASSERT( Instance == 0 );
+            CLOCK_ENABLE( hDevice, H, SPI1, ClockState );
+            break;
+        case NvRmModuleID_Fuse:
+            NV_ASSERT( Instance == 0 );
+            CLOCK_ENABLE( hDevice, H, FUSE, ClockState );
+            break;
+        case NvRmModuleID_KFuse:
+            NV_ASSERT( Instance == 0 );
+            CLOCK_ENABLE( hDevice, H, KFUSE, ClockState );
+            break;
+        case NvRmModuleID_Slink:
+            // Supporting only the slink controller.
+            NV_ASSERT( Instance < 4 );
+            if( Instance == 0 )
+            {
+                CLOCK_ENABLE( hDevice, H, SBC1, ClockState );
+            }
+            else if( Instance == 1 )
+            {
+                CLOCK_ENABLE( hDevice, H, SBC2, ClockState );
+            }
+            else if ( Instance == 2)
+            {
+                CLOCK_ENABLE( hDevice, H, SBC3, ClockState );
+            }
+            else if ( Instance == 3)
+            {
+                CLOCK_ENABLE( hDevice, U, SBC4, ClockState );
+            }
+            break;
+        case NvRmModuleID_Dvc:
+            NV_ASSERT( Instance == 0 );
+            CLOCK_ENABLE( hDevice, H, DVC_I2C, ClockState );
+            break;
+        case NvRmModuleID_Pmif:
+            NV_ASSERT( Instance == 0 );
+            // PMC clock must not be disabled
+            if (ClockState == ModuleClockState_Enable)
+                CLOCK_ENABLE( hDevice, H, PMC, ClockState );
+            break;
+        case NvRmModuleID_SysStatMonitor:
+            NV_ASSERT( Instance == 0 );
+            CLOCK_ENABLE( hDevice, H, STAT_MON, ClockState );
+            break;
+        case NvRmModuleID_Kbc:
+            NV_ASSERT( Instance == 0 );
+            CLOCK_ENABLE( hDevice, H, KBC, ClockState );
+            break;
+        case NvRmPrivModuleID_ApbDma:
+            NV_ASSERT( Instance == 0 );
+            CLOCK_ENABLE( hDevice, H, APBDMA, ClockState );
+            break;
+        case NvRmPrivModuleID_MemoryController:
+            // FIXME: should this be allowed?
+            NV_ASSERT( Instance == 0 );
+            CLOCK_ENABLE( hDevice, H, MEM, ClockState );
+            break;
+        case NvRmPrivModuleID_ExternalMemoryController:
+            {
+                // FIXME: should this be allowed?
+                NvU32 reg;
+
+                NV_ASSERT( Instance == 0 );
+                CLOCK_ENABLE( hDevice, H, EMC, ClockState );
+
+                reg = NV_REGR(hDevice, NvRmPrivModuleID_ClockAndReset, 0, CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0);
+                reg = NV_FLD_SET_DRF_NUM(CLK_RST_CONTROLLER, CLK_SOURCE_EMC, EMC_2X_CLK_ENB, 1, reg);
+                reg = NV_FLD_SET_DRF_NUM(CLK_RST_CONTROLLER, CLK_SOURCE_EMC, EMC_1X_CLK_ENB, 1, reg);
+                NV_REGW(hDevice, NvRmPrivModuleID_ClockAndReset, 0, CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0, reg);
+            }
+            break;
+        case NvRmModuleID_Cpu:
+            // FIXME: should this be allowed?
+            NV_ASSERT( Instance == 0 );
+            CLOCK_ENABLE( hDevice, L, CPU, ClockState );
+            break ;
+        case NvRmModuleID_SyncNor:
+            NV_ASSERT( Instance == 0 );
+            CLOCK_ENABLE( hDevice, H, SNOR, ClockState );
+            break;
+        case NvRmModuleID_AvpUcq:
+            NV_ASSERT( Instance == 0 );
+            CLOCK_ENABLE( hDevice, U, AVPUCQ, ClockState );
+            break;
+        case NvRmModuleID_OneWire:
+            NV_ASSERT( Instance == 0 );
+            CLOCK_ENABLE( hDevice, U, OWR, ClockState );
+            break;
+        case NvRmPrivModuleID_Pcie:
+            NV_ASSERT( Instance == 0 );
+            // Keep in sync both PCIE wrapper (AFI) and core clocks
+            CLOCK_ENABLE( hDevice, U, PCIE, ClockState );
+            CLOCK_ENABLE( hDevice, U, AFI, ClockState );
+            break;
+
+        default:
+            NV_ASSERT(!" Unknown NvRmModuleID passed to Ap20EnableModuleClock(). ");
+    }
+
+    if (ClockState == ModuleClockState_Disable)
+    {
+        NvRmPrivConfigureClockSource(hDevice, ModuleId, NV_FALSE);
+    }
+}
+
+void
+Ap20EnableTvDacClock(
+    NvRmDeviceHandle hDevice,
+    ModuleClockState ClockState)
+{
+    CLOCK_ENABLE( hDevice, H, TVDAC, ClockState );
+}
+
+/*****************************************************************************/
+
+void
+NvRmPrivAp20SetPmuIrqPolarity(
+    NvRmDeviceHandle hRmDevice,
+    NvOdmInterruptPolarity Polarity)
+{
+    NvU32 value = (Polarity == NvOdmInterruptPolarity_Low) ? 1 : 0;
+
+    // PMU interrupt polarity is set via PMC control register. OS kernel access
+    // to this register is limited to single thread env. On RM level this r-m-w
+    // is protected by RmOpen() serialization.
+    NvU32 reg = NV_REGR(hRmDevice, NvRmModuleID_Pmif, 0, APBDEV_PMC_CNTRL_0);
+    reg = NV_FLD_SET_DRF_NUM(APBDEV_PMC, CNTRL, INTR_POLARITY, value, reg);
+    NV_REGW(hRmDevice, NvRmModuleID_Pmif, 0, APBDEV_PMC_CNTRL_0, reg);
+}
+
+// KBC reset is available in the pmc control register.
+#define RESET_KBC( rm, delay ) \
+    do { \
+        NvU32 reg; \
+        reg = NV_REGR((rm), NvRmModuleID_Pmif, 0, APBDEV_PMC_CNTRL_0); \
+        reg = NV_FLD_SET_DRF_DEF(APBDEV_PMC, CNTRL, KBC_RST, ENABLE, reg); \
+        NV_REGW((rm), NvRmModuleID_Pmif, 0, APBDEV_PMC_CNTRL_0, reg); \
+        if (hold) \
+        {\
+            break; \
+        }\
+        NvOsWaitUS(delay); \
+        reg = NV_REGR((rm), NvRmModuleID_Pmif, 0, APBDEV_PMC_CNTRL_0); \
+        reg = NV_FLD_SET_DRF_DEF(APBDEV_PMC, CNTRL, KBC_RST, DISABLE, reg); \
+        NV_REGW((rm), NvRmModuleID_Pmif, 0, APBDEV_PMC_CNTRL_0, reg); \
+    } while( 0 )
+
+// Use PMC control to reset the entire SoC. Just wait forever after reset is
+// issued - h/w would auto-clear it and restart SoC
+#define RESET_SOC( rm ) \
+    do { \
+        volatile NvBool b = NV_TRUE; \
+        NvU32 reg; \
+        reg = NV_REGR((rm), NvRmModuleID_Pmif, 0, APBDEV_PMC_CNTRL_0); \
+        reg = NV_FLD_SET_DRF_DEF(APBDEV_PMC, CNTRL, MAIN_RST, ENABLE, reg); \
+        NV_REGW((rm), NvRmModuleID_Pmif, 0, APBDEV_PMC_CNTRL_0, reg); \
+        while (b) { ; } \
+    } while( 0 )
+
+void AP20ModuleReset(NvRmDeviceHandle hDevice, NvRmModuleID ModuleId, NvBool hold)
+{
+    // Extract module and instance from composite module id.
+    NvU32 Module   = NVRM_MODULE_ID_MODULE( ModuleId );
+    NvU32 Instance = NVRM_MODULE_ID_INSTANCE( ModuleId );
+
+    // Note that VDE has different reset sequence requirement
+    // FIMXE: NV blocks - hot reset issues
+    #define RESET( rm, offset, field, delay ) \
+        do { \
+            NvU32 reg; \
+            reg = NV_DRF_NUM(CLK_RST_CONTROLLER, RST_DEV_##offset##_SET, SET_##field##_RST, 1); \
+            NV_REGW((rm), NvRmPrivModuleID_ClockAndReset, 0, CLK_RST_CONTROLLER_RST_DEV_##offset##_SET_0, reg); \
+            if (hold) \
+            {  \
+                break; \
+            } \
+            NvOsWaitUS( (delay) ); \
+            reg = NV_DRF_NUM(CLK_RST_CONTROLLER, RST_DEV_##offset##_CLR, CLR_##field##_RST, 1); \
+            NV_REGW((rm), NvRmPrivModuleID_ClockAndReset, 0, CLK_RST_CONTROLLER_RST_DEV_##offset##_CLR_0, reg); \
+        } while( 0 )
+
+
+    switch( Module ) {
+    case NvRmPrivModuleID_MemoryController:
+        // FIXME: should this be allowed?
+        NV_ASSERT( Instance == 0 );
+        RESET( hDevice, H, MEM, NVRM_RESET_DELAY );
+        break;
+    case NvRmModuleID_Kbc:
+        NV_ASSERT( Instance == 0 );
+        RESET_KBC(hDevice, NVRM_RESET_DELAY );
+        break;
+    case NvRmModuleID_SysStatMonitor:
+        NV_ASSERT( Instance == 0 );
+        RESET( hDevice, H, STAT_MON, NVRM_RESET_DELAY );
+        break;
+    case NvRmModuleID_Pmif:
+        NV_ASSERT( Instance == 0 );
+        NV_ASSERT(!"PMC reset is not allowed, and does nothing on AP20");
+        break;
+    case NvRmModuleID_Fuse:
+        NV_ASSERT( Instance == 0 );
+        RESET( hDevice, H, FUSE, NVRM_RESET_DELAY );
+        break;
+    case NvRmModuleID_KFuse:
+        NV_ASSERT( Instance == 0 );
+        RESET( hDevice, H, KFUSE, NVRM_RESET_DELAY );
+        break;
+    case NvRmModuleID_Slink:
+        // Supporting only the slink controller.
+        NV_ASSERT( Instance < 4 );
+        if( Instance == 0 )
+        {
+            RESET( hDevice, H, SBC1, NVRM_RESET_DELAY );
+        }
+        else if( Instance == 1 )
+        {
+            RESET( hDevice, H, SBC2, NVRM_RESET_DELAY );
+        }
+        else if (Instance == 2)
+        {
+            RESET( hDevice, H, SBC3, NVRM_RESET_DELAY );
+        } else if (Instance == 3)
+        {
+            RESET( hDevice, U, SBC4, NVRM_RESET_DELAY );
+        }
+        break;
+    case NvRmModuleID_Spi:
+        NV_ASSERT( Instance == 0 );
+        RESET( hDevice, H, SPI1, NVRM_RESET_DELAY );
+        break;
+    case NvRmModuleID_Xio:
+        NV_ASSERT( Instance == 0 );
+        RESET( hDevice, H, XIO, NVRM_RESET_DELAY );
+        break;
+    case NvRmModuleID_Dvc:
+        NV_ASSERT( Instance == 0 );
+        RESET( hDevice, H, DVC_I2C, NVRM_RESET_DELAY );
+        break;
+    case NvRmModuleID_Dsi:
+        NV_ASSERT( Instance == 0 );
+        RESET( hDevice, H, DSI, NVRM_RESET_DELAY );
+        break;
+    case NvRmModuleID_Tvo:
+        NV_ASSERT( Instance == 0 );
+        RESET( hDevice, H, TVO, NVRM_RESET_DELAY );
+        RESET( hDevice, H, TVDAC, NVRM_RESET_DELAY );
+        break;
+    case NvRmModuleID_Mipi:
+        NV_ASSERT( Instance == 0 );
+        RESET( hDevice, H, MIPI, NVRM_RESET_DELAY );
+        break;
+    case NvRmModuleID_Hdmi:
+        NV_ASSERT( Instance == 0 );
+        RESET( hDevice, H, HDMI, NVRM_RESET_DELAY );
+        break;
+    case NvRmModuleID_Csi:
+        NV_ASSERT( Instance == 0 );
+        RESET( hDevice, H, CSI, NVRM_RESET_DELAY );
+        break;
+    case NvRmModuleID_I2c:
+        if( Instance == 0 )
+        {
+            RESET( hDevice, L, I2C1, NVRM_RESET_DELAY );
+        }
+        else if( Instance == 1 )
+        {
+            RESET( hDevice, H, I2C2, NVRM_RESET_DELAY );
+        } else if (Instance == 2)
+        {
+            RESET( hDevice, U, I2C3, NVRM_RESET_DELAY );
+        } else
+        {
+            NV_ASSERT(!"Invalid I2C instace");
+        }
+        break;
+    case NvRmModuleID_Mpe:
+        NV_ASSERT( Instance == 0 );
+        RESET( hDevice, H, MPE, NVRM_RESET_DELAY );
+        break;
+    case NvRmModuleID_Vde:
+        NV_ASSERT( Instance == 0 );
+        {
+            NvU32 reg;
+
+            reg = NV_DRF_NUM(CLK_RST_CONTROLLER, RST_DEV_H_SET,
+                    SET_VDE_RST, 1)
+                | NV_DRF_NUM(CLK_RST_CONTROLLER, RST_DEV_H_SET,
+                    SET_BSEV_RST, 1);
+            NV_REGW(hDevice, NvRmPrivModuleID_ClockAndReset, 0,
+                CLK_RST_CONTROLLER_RST_DEV_H_SET_0, reg);
+
+            if (hold)
+            {
+                break;
+            }
+            NvOsWaitUS( NVRM_RESET_DELAY );
+
+            reg = NV_DRF_NUM(CLK_RST_CONTROLLER, RST_DEV_H_CLR,
+                    CLR_VDE_RST, 1)
+                | NV_DRF_NUM(CLK_RST_CONTROLLER, RST_DEV_H_CLR,
+                    CLR_BSEV_RST, 1);
+            NV_REGW(hDevice, NvRmPrivModuleID_ClockAndReset, 0,
+                CLK_RST_CONTROLLER_RST_DEV_H_CLR_0, reg);
+        }
+        break;
+    case NvRmModuleID_BseA:
+        NV_ASSERT( Instance == 0 );
+        RESET( hDevice, H, BSEA, NVRM_RESET_DELAY );
+        break;
+    case NvRmModuleID_Cpu:
+        // FIXME: should this be allowed?
+        NV_ASSERT( Instance == 0 );
+        RESET( hDevice, L, CPU, NVRM_RESET_DELAY );
+        break;
+    case NvRmModuleID_Avp:
+        // FIXME: should this be allowed?
+        NV_ASSERT( Instance == 0 );
+        RESET( hDevice, L, COP, NVRM_RESET_DELAY );
+        break;
+    case NvRmPrivModuleID_System:
+        /* THIS WILL DO A FULL SYSTEM RESET */
+        NV_ASSERT( Instance == 0 );
+        RESET_SOC(hDevice);
+        break;
+    case NvRmModuleID_Ac97:
+        NV_ASSERT( Instance == 0 );
+        RESET( hDevice, L, AC97, NVRM_RESET_DELAY );
+        break;
+    case NvRmModuleID_Rtc:
+        NV_ASSERT( Instance == 0 );
+        RESET( hDevice, L, RTC, NVRM_RESET_DELAY );
+        break;
+    case NvRmModuleID_Timer:
+        NV_ASSERT( Instance == 0 );
+        RESET( hDevice, L, TMR, NVRM_RESET_DELAY );
+        break;
+    case NvRmModuleID_Uart:
+        if( Instance == 0 )
+        {
+            RESET( hDevice, L, UARTA, NVRM_RESET_DELAY );
+        }
+        else if( Instance == 1 )
+        {
+            RESET( hDevice, L, UARTB, NVRM_RESET_DELAY );
+        }
+        else if ( Instance == 2)
+        {
+            RESET( hDevice, H, UARTC, NVRM_RESET_DELAY );
+        } else if (Instance == 3)
+        {
+            RESET( hDevice, U, UARTD, NVRM_RESET_DELAY );
+        } else if (Instance == 4)
+        {
+            RESET( hDevice, U, UARTE, NVRM_RESET_DELAY );
+        } else
+        {
+            NV_ASSERT(!"Invalid UART instance");
+        }
+        break;
+    case NvRmModuleID_Vfir:
+        // Same as UARTB
+        NV_ASSERT( Instance == 0 );
+        RESET( hDevice, L, UARTB, NVRM_RESET_DELAY );
+        break;
+    case NvRmModuleID_Sdio:
+        if( Instance == 0 )
+        {
+            RESET( hDevice, L, SDMMC1, NVRM_RESET_DELAY );
+        }
+        else if( Instance == 1 )
+        {
+            RESET( hDevice, L, SDMMC2, NVRM_RESET_DELAY );
+        } else if (Instance == 2)
+        {
+            RESET( hDevice, U, SDMMC3, NVRM_RESET_DELAY );
+        } else if (Instance == 3)
+        {
+            RESET( hDevice, L, SDMMC4, NVRM_RESET_DELAY );
+        } else
+        {
+            NV_ASSERT(!"Invalid SDIO instance");
+        }
+        break;
+    case NvRmModuleID_Spdif:
+        NV_ASSERT( Instance == 0 );
+        RESET( hDevice, L, SPDIF, NVRM_RESET_DELAY );
+        break;
+    case NvRmModuleID_I2s:
+        if( Instance == 0 )
+        {
+            RESET( hDevice, L, I2S1, NVRM_RESET_DELAY );
+        }
+        else if( Instance == 1 )
+        {
+            RESET( hDevice, L, I2S2, NVRM_RESET_DELAY );
+        } else
+        {
+            NV_ASSERT(!"Invalid I2S instance");
+        }
+        break;
+    case NvRmModuleID_Nand:
+        NV_ASSERT( Instance == 0 );
+        RESET( hDevice, L, NDFLASH, NVRM_RESET_DELAY );
+        break;
+    case NvRmModuleID_Twc:
+        NV_ASSERT( Instance == 0 );
+        RESET( hDevice, L, TWC, NVRM_RESET_DELAY );
+        break;
+    case NvRmModuleID_Pwm:
+        NV_ASSERT( Instance == 0 );
+        RESET( hDevice, L, PWM, NVRM_RESET_DELAY );
+        break;
+    case NvRmModuleID_Epp:
+        NV_ASSERT( Instance == 0 );
+        RESET( hDevice, L, EPP, NVRM_RESET_DELAY );
+        break;
+    case NvRmModuleID_Vi:
+        NV_ASSERT( Instance == 0 );
+        RESET( hDevice, L, VI, NVRM_RESET_DELAY );
+        break;
+    case NvRmModuleID_3D:
+        NV_ASSERT( Instance == 0 );
+        RESET( hDevice, L, 3D, NVRM_RESET_DELAY );
+        break;
+    case NvRmModuleID_2D:
+        NV_ASSERT( Instance == 0 );
+        // RESET( hDevice, L, 2D, NVRM_RESET_DELAY );
+        // WAR for bug 364497, se also NvRmPrivAP20Reset2D()
+        NV_ASSERT(!"2D reset after RM open is no longer allowed");
+        break;
+    case NvRmModuleID_Usb2Otg:
+        if (Instance == 0)
+        {
+            RESET( hDevice, L, USBD, NVRM_RESET_DELAY );
+        } else if (Instance == 1)
+        {
+            RESET( hDevice, H, USB2, NVRM_RESET_DELAY );
+        } else if (Instance == 2)
+        {
+            RESET( hDevice, H, USB3, NVRM_RESET_DELAY );
+        } else
+        {
+            NV_ASSERT(!"Invalid USB instance");
+        }
+        break;
+    case NvRmModuleID_Isp:
+        NV_ASSERT( Instance == 0 );
+        RESET( hDevice, L, ISP, NVRM_RESET_DELAY );
+        break;
+    case NvRmModuleID_Ide:
+        NV_ASSERT( Instance == 0 );
+        RESET( hDevice, L, IDE, NVRM_RESET_DELAY );
+        break;
+    case NvRmModuleID_Display:
+        NV_ASSERT( Instance < 2 );
+        if( Instance == 0 )
+        {
+            RESET( hDevice, L, DISP1, NVRM_RESET_DELAY );
+        }
+        else if( Instance == 1 )
+        {
+            RESET( hDevice, L, DISP2, NVRM_RESET_DELAY );
+        }
+        break;
+    case NvRmModuleID_Vcp:
+        NV_ASSERT( Instance == 0 );
+        RESET( hDevice, L, VCP, NVRM_RESET_DELAY );
+        break;
+    case NvRmModuleID_CacheMemCtrl:
+        NV_ASSERT( Instance < 2 );
+        if( Instance == 0 )
+        {
+            NV_ASSERT(!"There is not such module on AP20");
+        }
+        else if ( Instance == 1 )
+        {
+            RESET( hDevice, L, CACHE2, NVRM_RESET_DELAY );
+        }
+        break;
+    case NvRmPrivModuleID_ApbDma:
+        NV_ASSERT( Instance == 0 );
+        RESET( hDevice, H, APBDMA, NVRM_RESET_DELAY );
+        break;
+    case NvRmPrivModuleID_Gpio:
+        NV_ASSERT( Instance == 0 );
+        RESET( hDevice, L, GPIO, NVRM_RESET_DELAY );
+        break;
+    case NvRmModuleID_GraphicsHost:
+        // FIXME: should this be allowed?
+        NV_ASSERT( Instance == 0 );
+        RESET( hDevice, L, HOST1X, NVRM_RESET_DELAY );
+        break;
+    case NvRmPrivModuleID_PcieXclk:
+        NV_ASSERT( Instance == 0 );
+        RESET( hDevice, U, PCIEXCLK, NVRM_RESET_DELAY );
+        break;
+    case NvRmPrivModuleID_Pcie:
+        NV_ASSERT( Instance == 0 );
+        RESET( hDevice, U, PCIE, NVRM_RESET_DELAY );
+        break;
+    case NvRmPrivModuleID_Afi:
+        NV_ASSERT( Instance == 0 );
+        RESET( hDevice, U, AFI, NVRM_RESET_DELAY );
+        break;
+    case NvRmModuleID_SyncNor:
+        NV_ASSERT( Instance == 0 );
+        RESET( hDevice, H, SNOR, NVRM_RESET_DELAY );
+        break;
+    case NvRmModuleID_AvpUcq:
+        NV_ASSERT( Instance == 0 );
+        RESET( hDevice, U, AVPUCQ, NVRM_RESET_DELAY );
+        break;
+    case NvRmModuleID_OneWire:
+        NV_ASSERT( Instance == 0 );
+        RESET( hDevice, U, OWR, NVRM_RESET_DELAY );
+        break;
+
+    default:
+        NV_ASSERT(!"Invalid ModuleId");
+    }
+
+    #undef RESET
+}
+
+static void
+NvRmPrivContentProtectionFuses( NvRmDeviceHandle hRm )
+{
+    NvU32 reg;
+    NvU32 clk_rst;
+
+    /* need to set FUSE_RESERVED_PRODUCTION_0 to 0x3,
+     * enable the bypass and write access
+     *
+     * bit 0: macrovision
+     * bit 1: hdcp
+     */
+
+#if NV_USE_FUSE_CLOCK_ENABLE
+    // Enable fuse clock
+    Ap20EnableModuleClock(hRm, NvRmModuleID_Fuse, NV_TRUE);
+#endif
+
+    /**
+     * This order is IMPORTANT. Fuse bypass doesn't seem to work with
+     * different ordering.
+     */
+
+    clk_rst = NV_REGR( hRm, NvRmPrivModuleID_ClockAndReset, 0,
+        CLK_RST_CONTROLLER_MISC_CLK_ENB_0 );
+    clk_rst = NV_FLD_SET_DRF_NUM( CLK_RST_CONTROLLER, MISC_CLK_ENB,
+        CFG_ALL_VISIBLE, 1, clk_rst );
+    NV_REGW( hRm, NvRmPrivModuleID_ClockAndReset, 0,
+        CLK_RST_CONTROLLER_MISC_CLK_ENB_0, clk_rst );
+
+    reg = NV_REGR( hRm, NvRmModuleID_Fuse, 0, FUSE_FUSEBYPASS_0);
+    reg = NV_FLD_SET_DRF_DEF( FUSE, FUSEBYPASS, FUSEBYPASS_VAL, ENABLED, reg );
+    NV_REGW( hRm, NvRmModuleID_Fuse, 0, FUSE_FUSEBYPASS_0, reg );
+
+    reg = NV_REGR( hRm, NvRmModuleID_Fuse, 0, FUSE_WRITE_ACCESS_SW_0);
+    reg = NV_FLD_SET_DRF_DEF( FUSE, WRITE_ACCESS_SW, WRITE_ACCESS_SW_CTRL,
+            READWRITE, reg);
+    NV_REGW( hRm, NvRmModuleID_Fuse, 0, FUSE_WRITE_ACCESS_SW_0, reg );
+
+    reg = NV_REGR( hRm, NvRmModuleID_Fuse, 0, FUSE_RESERVED_PRODUCTION_0);
+    reg = NV_FLD_SET_DRF_NUM( FUSE, RESERVED_PRODUCTION,
+            RESERVED_PRODUCTION, 0x3, reg );
+    NV_REGW( hRm, NvRmModuleID_Fuse, 0, FUSE_RESERVED_PRODUCTION_0, reg );
+
+    clk_rst = NV_FLD_SET_DRF_NUM( CLK_RST_CONTROLLER, MISC_CLK_ENB,
+        CFG_ALL_VISIBLE, 0, clk_rst );
+    NV_REGW( hRm, NvRmPrivModuleID_ClockAndReset, 0,
+        CLK_RST_CONTROLLER_MISC_CLK_ENB_0, clk_rst );
+
+#if NV_USE_FUSE_CLOCK_ENABLE
+    // Disable fuse clock
+    Ap20EnableModuleClock(hRm, NvRmModuleID_Fuse, NV_FALSE);
+#endif
+}
+
+// Safe PLLM (max 1000MHz) divider for GPU modules
+#define NVRM_SAFE_GPU_DIVIDER (10)
+
+void
+NvRmPrivAp20Reset2D(NvRmDeviceHandle hRmDevice)
+{
+#if !NV_OAL
+    NvU32 reg, offset;
+    /*
+     * WAR for bug 364497: 2D can not be taken out of reset if VI clock is
+     * running. Therefore, make sure VI clock is disabled and reset 2D here
+     * during RM initialization.
+     */
+    Ap20EnableModuleClock(hRmDevice, NvRmModuleID_Vi,
+        ModuleClockState_Disable);
+
+    // Assert reset to 2D module
+    offset = CLK_RST_CONTROLLER_RST_DEV_L_SET_0;
+    reg = NV_DRF_NUM(CLK_RST_CONTROLLER, RST_DEV_L_SET, SET_2D_RST, 1);
+    NV_REGW(hRmDevice, NvRmPrivModuleID_ClockAndReset, 0, offset, reg);
+
+    // Enable "known good" configuartion for 2D clock (PLLM as a source)
+    offset = CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0;
+    NV_REGW(hRmDevice, NvRmPrivModuleID_ClockAndReset, 0, offset,
+            (NV_DRF_NUM(CLK_RST_CONTROLLER, CLK_SOURCE_G2D, G2D_CLK_DIVISOR,
+                        NVRM_SAFE_GPU_DIVIDER) |
+             NV_DRF_DEF(CLK_RST_CONTROLLER, CLK_SOURCE_G2D, G2D_CLK_SRC,
+                        PLLM_OUT0))
+            );
+    Ap20EnableModuleClock(hRmDevice, NvRmModuleID_2D, ModuleClockState_Enable);
+    NvOsWaitUS(NVRM_RESET_DELAY);
+
+    // Take 2D out of reset and disable 2D clock. Both VI and 2D clocks are
+    // left disabled -it is up to the resepctive drivers to configure and
+    // enable them later.
+    offset = CLK_RST_CONTROLLER_RST_DEV_L_CLR_0;
+    reg = NV_DRF_NUM(CLK_RST_CONTROLLER, RST_DEV_L_CLR, CLR_2D_RST, 1);
+    NV_REGW(hRmDevice, NvRmPrivModuleID_ClockAndReset, 0, offset, reg);
+    Ap20EnableModuleClock(hRmDevice, NvRmModuleID_2D,
+        ModuleClockState_Disable);
+#endif
+}
+
+#define NVRM_CONFIG_CLOCK(Module, SrcDef, DivNum) \
+do\
+{\
+    reg = NV_REGR(rm, NvRmPrivModuleID_ClockAndReset, 0, \
+                  CLK_RST_CONTROLLER_CLK_SOURCE_##Module##_0); \
+    if ((DivNum) > NV_DRF_VAL(CLK_RST_CONTROLLER, CLK_SOURCE_##Module, \
+                            Module##_CLK_DIVISOR, reg)) \
+    {\
+        reg = NV_FLD_SET_DRF_NUM(CLK_RST_CONTROLLER, CLK_SOURCE_##Module, \
+                                 Module##_CLK_DIVISOR, (DivNum), reg); \
+        NV_REGW(rm, NvRmPrivModuleID_ClockAndReset, 0, \
+                CLK_RST_CONTROLLER_CLK_SOURCE_##Module##_0, reg); \
+        NvOsWaitUS(NVRM_CLOCK_CHANGE_DELAY); \
+    }\
+    reg = NV_FLD_SET_DRF_DEF(CLK_RST_CONTROLLER, CLK_SOURCE_##Module, \
+                             Module##_CLK_SRC, SrcDef, reg); \
+    NV_REGW(rm, NvRmPrivModuleID_ClockAndReset, 0, \
+            CLK_RST_CONTROLLER_CLK_SOURCE_##Module##_0, reg); \
+    NvOsWaitUS(NVRM_CLOCK_CHANGE_DELAY); \
+    if ((DivNum) < NV_DRF_VAL(CLK_RST_CONTROLLER, CLK_SOURCE_##Module, \
+                            Module##_CLK_DIVISOR, reg))\
+    {\
+        reg = NV_FLD_SET_DRF_NUM(CLK_RST_CONTROLLER, CLK_SOURCE_##Module, \
+                                 Module##_CLK_DIVISOR, (DivNum), reg); \
+        NV_REGW(rm, NvRmPrivModuleID_ClockAndReset, 0, \
+                CLK_RST_CONTROLLER_CLK_SOURCE_##Module##_0, reg); \
+        NvOsWaitUS(NVRM_CLOCK_CHANGE_DELAY);\
+    }\
+} while(0)
+
+void
+NvRmPrivAp20BasicReset( NvRmDeviceHandle rm )
+{
+#if !NV_OAL
+    NvU32 reg, ClkOutL, ClkOutH, ClkOutU;
+    ExecPlatform env;
+
+    if (NvRmIsSimulation())
+    {
+        /* the memory system can't be used until the mem_init_done bit has
+         * been set.  This is done by the bootrom for production systems.
+         */
+        reg = NV_REGR( rm, NvRmPrivModuleID_Ahb_Arb_Ctrl, 0,
+                       AHB_ARBITRATION_XBAR_CTRL_0 );
+        reg = NV_FLD_SET_DRF_DEF( AHB_ARBITRATION, XBAR_CTRL, MEM_INIT_DONE,
+                                  DONE, reg );
+        NV_REGW( rm, NvRmPrivModuleID_Ahb_Arb_Ctrl, 0,
+                 AHB_ARBITRATION_XBAR_CTRL_0, reg );
+    }
+
+    // FIXME: this takes the Big Hammer Approach.  Take everything out
+    // of reset and enable all of the clocks. Then keep enabled only boot
+    // clocks and graphics host.
+
+    // save boot clock enable state
+    ClkOutL = NV_REGR(rm, NvRmPrivModuleID_ClockAndReset, 0,
+                      CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0);
+    ClkOutH = NV_REGR(rm, NvRmPrivModuleID_ClockAndReset, 0,
+                      CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0);
+    ClkOutU = NV_REGR(rm, NvRmPrivModuleID_ClockAndReset, 0,
+                      CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0);
+
+    // Enable module clocks
+    // (for U register module clocks are in the low word only)
+    NV_REGW( rm, NvRmPrivModuleID_ClockAndReset, 0,
+        CLK_RST_CONTROLLER_CLK_ENB_L_SET_0, 0xFFFFFFFF );
+    NV_REGW( rm, NvRmPrivModuleID_ClockAndReset, 0,
+        CLK_RST_CONTROLLER_CLK_ENB_H_SET_0, 0xFFFFFFFF );
+    NV_REGW( rm, NvRmPrivModuleID_ClockAndReset, 0,
+        CLK_RST_CONTROLLER_CLK_ENB_U_SET_0, 0x0000FFFF );
+
+    // For AP20 default clock source selection is out of range for some modules
+    // Just copnfigure safe clocks so that reset is propagated correctly
+    env = NvRmPrivGetExecPlatform(rm);
+    if (env == ExecPlatform_Soc)
+    {
+        /*
+         * For peripheral modules default clock source is oscillator, and
+         * it is safe. Special case SPDIFIN - set on PLLP_OUT0/(1+10/2)
+         * and VDE - set on PLLP_OUT0/(1+1/2)
+         */
+        reg = NV_REGR(rm, NvRmPrivModuleID_ClockAndReset, 0,
+                      CLK_RST_CONTROLLER_RST_DEVICES_L_0);
+        if (reg & CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SPDIF_RST_FIELD)
+        {
+            reg = NV_DRF_DEF(CLK_RST_CONTROLLER, CLK_SOURCE_SPDIF_IN,
+                             SPDIFIN_CLK_SRC, PLLP_OUT0) |
+                  NV_DRF_NUM(CLK_RST_CONTROLLER, CLK_SOURCE_SPDIF_IN,
+                             SPDIFIN_CLK_DIVISOR, 10);
+            NV_REGW( rm, NvRmPrivModuleID_ClockAndReset, 0,
+                CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0, reg);
+        }
+        NVRM_CONFIG_CLOCK(VDE, PLLP_OUT0, 1);
+
+        /*
+         * For graphic clocks use PLLM_OUT0 as a source, and set divider
+         * so that initial frequency is below maximum module limit
+         */
+        NVRM_CONFIG_CLOCK(HOST1X, PLLM_OUT0, NVRM_SAFE_GPU_DIVIDER);
+        NVRM_CONFIG_CLOCK(EPP, PLLM_OUT0, NVRM_SAFE_GPU_DIVIDER);
+        NVRM_CONFIG_CLOCK(G2D, PLLM_OUT0, NVRM_SAFE_GPU_DIVIDER);
+        NVRM_CONFIG_CLOCK(G3D, PLLM_OUT0, NVRM_SAFE_GPU_DIVIDER);
+        NVRM_CONFIG_CLOCK(MPE, PLLM_OUT0, NVRM_SAFE_GPU_DIVIDER);
+        NVRM_CONFIG_CLOCK(VI, PLLM_OUT0, NVRM_SAFE_GPU_DIVIDER);
+        NVRM_CONFIG_CLOCK(VI_SENSOR, PLLM_OUT0, NVRM_SAFE_GPU_DIVIDER);
+
+        /* Using 144MHz for coresight */
+        NVRM_CONFIG_CLOCK(CSITE, PLLP_OUT0, 1);
+
+        NvOsWaitUS(NVRM_RESET_DELAY);
+    }
+    // Make sure Host1x clock will be kept enabled
+    ClkOutL = NV_FLD_SET_DRF_DEF(CLK_RST_CONTROLLER, CLK_OUT_ENB_L,
+                                 CLK_ENB_HOST1X, ENABLE, ClkOutL);
+    // Make sure VDE, BSEV and BSEA clocks will be kept disabled
+    ClkOutH = NV_FLD_SET_DRF_DEF(CLK_RST_CONTROLLER, CLK_OUT_ENB_H,
+                                 CLK_ENB_VDE, DISABLE, ClkOutH);
+    ClkOutH = NV_FLD_SET_DRF_DEF(CLK_RST_CONTROLLER, CLK_OUT_ENB_H,
+                                 CLK_ENB_BSEV, DISABLE, ClkOutH);
+    ClkOutH = NV_FLD_SET_DRF_DEF(CLK_RST_CONTROLLER, CLK_OUT_ENB_H,
+                                 CLK_ENB_BSEA, DISABLE, ClkOutH);
+    // Make sure SNOR clock will be kept disabled
+    ClkOutH = NV_FLD_SET_DRF_DEF(CLK_RST_CONTROLLER, CLK_OUT_ENB_H,
+                                 CLK_ENB_SNOR, DISABLE, ClkOutH);
+
+    // restore clock enable state (= disable those clocks that
+    // were disabled on boot)
+    NV_REGW( rm, NvRmPrivModuleID_ClockAndReset, 0,
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0, ClkOutL );
+    NV_REGW( rm, NvRmPrivModuleID_ClockAndReset, 0,
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0, ClkOutH );
+    NV_REGW( rm, NvRmPrivModuleID_ClockAndReset, 0,
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0, ClkOutU );
+
+    /* enable hdcp and macrovision */
+    NvRmPrivContentProtectionFuses( rm );
+
+    // AP15 BasicReset() sets DRAM_CLKSTOP and DRAM_ACPD here.
+    // Should be done by BCT - removing for AP20.
+
+    // AP15 BasicReset() enables stop clock to CPU, while it is halted.
+    // Removed in AP20 as halt on dual core is actually WFE
+#endif // !NV_OAL
+}
+
+void NvRmPrivAp20IoPowerDetectReset(NvRmDeviceHandle hRmDeviceHandle)
+{
+    NV_REGW(hRmDeviceHandle, NvRmModuleID_Pmif, 0,
+            APBDEV_PMC_PWR_DET_VAL_0, APBDEV_PMC_PWR_DET_VAL_0_RESET_VAL);
+}
+
+/*****************************************************************************/
+
+NvError
+NvRmPrivAp20OscDoublerConfigure(
+    NvRmDeviceHandle hRmDevice,
+    NvRmFreqKHz OscKHz)
+{
+    NvU32 reg, Taps;
+    NvError error = NvRmPrivGetOscDoublerTaps(hRmDevice, OscKHz, &Taps);
+
+    if (error == NvSuccess)
+    {
+        // Program delay
+        reg = NV_REGR(hRmDevice, NvRmPrivModuleID_ClockAndReset, 0,
+                      CLK_RST_CONTROLLER_PROG_DLY_CLK_0);
+        reg = NV_FLD_SET_DRF_NUM(
+            CLK_RST_CONTROLLER, PROG_DLY_CLK, CLK_D_DELCLK_SEL, Taps, reg);
+        NV_REGW(hRmDevice, NvRmPrivModuleID_ClockAndReset, 0,
+                CLK_RST_CONTROLLER_PROG_DLY_CLK_0, reg);
+        // Enable doubler
+        reg = NV_DRF_NUM(
+            CLK_RST_CONTROLLER, CLK_ENB_U_SET, SET_CLK_M_DOUBLER_ENB, 1);
+        NV_REGW(hRmDevice, NvRmPrivModuleID_ClockAndReset, 0,
+                CLK_RST_CONTROLLER_CLK_ENB_U_SET_0, reg);
+    }
+    else
+    {
+        // Disable doubler
+        reg = NV_DRF_NUM(
+            CLK_RST_CONTROLLER, CLK_ENB_U_CLR, CLR_CLK_M_DOUBLER_ENB, 1);
+        NV_REGW(hRmDevice, NvRmPrivModuleID_ClockAndReset, 0,
+                CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0, reg);
+    }
+    return error;
+}
+
+#define APBDEV_PMC_SCRATCH42_0_PCX_CLAMP_RANGE  0:0
+
+#define NVRM_PCIE_REF_FREQUENCY (12000)
+
+void NvRmPrivAp20PllEControl(NvRmDeviceHandle hRmDevice, NvBool Enable)
+{
+    static NvBool s_Started = NV_FALSE;
+
+    NvU32 base, reg, offset;
+
+    if (NvRmPrivGetExecPlatform(hRmDevice) != ExecPlatform_Soc)
+        return;
+
+    if (NvRmPowerGetPrimaryFrequency(hRmDevice) != NVRM_PCIE_REF_FREQUENCY)
+    {
+        NV_ASSERT(!"Not supported primary frequency");
+        return;
+    }
+
+    // No run time power management for PCIE PLL - once started, it will never
+    // be disabled
+    if (s_Started || !Enable)
+        return;
+
+    // Do not start PLLE while it is clamped
+    offset = APBDEV_PMC_SCRATCH42_0;
+    reg = NV_REGR(hRmDevice, NvRmModuleID_Pmif, 0, offset);
+    if (NV_DRF_VAL(APBDEV_PMC, SCRATCH42, PCX_CLAMP, reg) && Enable)
+        return;
+
+    s_Started = NV_TRUE;
+
+    // Set PLLE base = 0x0D18C801 (configured, but disabled)
+    offset = CLK_RST_CONTROLLER_PLLE_BASE_0;
+    base= NV_DRF_DEF(CLK_RST_CONTROLLER, PLLE_BASE, PLLE_ENABLE_CML, DISABLE) |
+          NV_DRF_DEF(CLK_RST_CONTROLLER, PLLE_BASE, PLLE_ENABLE, DISABLE)     |
+          NV_DRF_NUM(CLK_RST_CONTROLLER, PLLE_BASE, PLLE_PLDIV_CML,  0x0D)    |
+          NV_DRF_NUM(CLK_RST_CONTROLLER, PLLE_BASE, PLLE_PLDIV,      0x18)    |
+          NV_DRF_NUM(CLK_RST_CONTROLLER, PLLE_BASE, PLLE_NDIV,       0xC8)    |
+          NV_DRF_NUM(CLK_RST_CONTROLLER, PLLE_BASE, PLLE_MDIV,       0x01);
+    NV_REGW(hRmDevice, NvRmPrivModuleID_ClockAndReset, 0, offset, base);
+
+    // Pulse IDDQ/clamp signal to start training
+    offset = APBDEV_PMC_SCRATCH42_0;
+    reg = NV_REGR(hRmDevice, NvRmModuleID_Pmif, 0, offset);
+    reg = NV_FLD_SET_DRF_NUM(APBDEV_PMC, SCRATCH42, PCX_CLAMP, 0x1, reg);
+    NV_REGW(hRmDevice, NvRmModuleID_Pmif, 0, offset, reg);
+
+    NvOsWaitUS(NVRM_CLOCK_CHANGE_DELAY); // wait > 1us
+
+    reg = NV_FLD_SET_DRF_NUM(APBDEV_PMC, SCRATCH42, PCX_CLAMP, 0x0, reg);
+    NV_REGW(hRmDevice, NvRmModuleID_Pmif, 0, offset, reg);
+
+    // Poll PLLE ready
+    offset = CLK_RST_CONTROLLER_PLLE_MISC_0;
+    reg = NV_REGR(hRmDevice, NvRmPrivModuleID_ClockAndReset, 0, offset);
+    while (!(NV_DRF_VAL(CLK_RST_CONTROLLER, PLLE_MISC, PLLE_PLL_READY, reg)))
+    {
+        reg = NV_REGR(hRmDevice, NvRmPrivModuleID_ClockAndReset, 0, offset);
+    }
+
+    // Set PLLE base = 0xCD18C801 (configured and enabled)
+    offset = CLK_RST_CONTROLLER_PLLE_BASE_0;
+    base = NV_FLD_SET_DRF_DEF(
+        CLK_RST_CONTROLLER, PLLE_BASE, PLLE_ENABLE_CML, ENABLE, base);
+    base = NV_FLD_SET_DRF_DEF(
+        CLK_RST_CONTROLLER, PLLE_BASE, PLLE_ENABLE, ENABLE, base);
+    NV_REGW(hRmDevice, NvRmPrivModuleID_ClockAndReset, 0, offset, base);
+
+    // use MIPI PLL delay for now - TODO: confirm or find PLLE specific
+    NvOsWaitUS(NVRM_PLL_MIPI_STABLE_DELAY_US);
+}
+
+void
+NvRmPrivAp20PowerPcieXclkControl(
+    NvRmDeviceHandle hRmDevice,
+    NvBool Enable)
+{
+    NvU32 reg, offset;
+
+    offset = APBDEV_PMC_SCRATCH42_0;
+    reg = NV_REGR(hRmDevice, NvRmModuleID_Pmif, 0, offset);
+    reg = NV_FLD_SET_DRF_NUM(
+        APBDEV_PMC, SCRATCH42, PCX_CLAMP, Enable ? 0x0 : 0x1, reg);
+    NV_REGW(hRmDevice, NvRmModuleID_Pmif, 0, offset, reg);
+}
+
diff --git a/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_clocks.h b/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_clocks.h
new file mode 100644
index 000000000000..04d9bf0734b1
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_clocks.h
@@ -0,0 +1,294 @@
+/*
+ * Copyright (c) 2008-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+
+#ifndef INCLUDED_AP20RM_CLOCKS_H
+#define INCLUDED_AP20RM_CLOCKS_H
+
+#include "nvrm_clocks.h"
+#include "nvodm_query_memc.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif  /* __cplusplus */
+
+extern const NvRmModuleClockInfo g_Ap20ModuleClockTable[];
+extern const NvU32 g_Ap20ModuleClockTableSize;
+
+// Minimum PLLX VCO frequency for reliable operation of DCC circuit
+#define NVRM_PLLX_DCC_VCO_MIN (600000)
+
+// Default PLLC output frequency
+#define NVRM_PLLC_DEFAULT_FREQ_KHZ (600000)
+
+// Defines number of EMC frequency steps for DFS 
+#define NVRM_AP20_DFS_EMC_FREQ_STEPS (8)
+
+// Defines maximum APB frequency (bug 559823)
+#define NVRM_AP20_APB_MAX_KHZ (125000)
+
+// Defines graphics Host frequency
+#define NVRM_AP20_HOST_KHZ (108000)
+
+/**
+ * Defines frequency steps derived from PLLP0 fixed output to be used as System
+ * clock source frequency. The frequency specified in kHz, and it will be rounded
+ * up to the closest divider output. 
+ */
+#define NVRM_AP20_PLLP_POLICY_SYSTEM_CLOCK \
+    PLLP_POLICY_ENTRY(54000)   /* PLLP divider  6, output frequency  54,000kHz */ \
+    PLLP_POLICY_ENTRY(72000)   /* PLLP divider  4, output frequency  72,000kHz */ \
+    PLLP_POLICY_ENTRY(108000)  /* PLLP divider  2, output frequency 108,000kHz */ \
+    PLLP_POLICY_ENTRY(144000)  /* PLLP divider  1, output frequency 144,000kHz */ \
+    PLLP_POLICY_ENTRY(216000)  /* PLLP divider  0, output frequency 216,000kHz */
+
+/**
+ * Defines frequency steps derived from PLLP0 fixed output to be used as CPU
+ * clock source frequency. The frequency specified in kHz, and it will be rounded
+ * up to the closest divider output. On AP20 we will use only main PLLP0 output,
+ * and no divided down steps, so that PLLP_OUT4 divider output is available as
+ * a source for external devices.
+ */
+#define NVRM_AP20_PLLP_POLICY_CPU_CLOCK \
+    PLLP_POLICY_ENTRY(216000)  /* PLLP divider  0, output frequency 216,000kHz */
+
+// On AP20 PLLP4 is used as 24MHz source for external devices. This setting will
+// overwrite initial PLLP4 frequency after boot/resume from LP0.
+#define NVRM_AP20_FIXED_PLLP4_SETTING (16)   /* 216 / (1 + 16/2) = 24 */
+
+/**
+ * Combines EMC 2x frequency and the respective set of EMC timing parameters for
+ * pre-defined EMC configurations (DDR clock is running at EMC 1x frequency)
+ */
+typedef struct NvRmAp20EmcTimingConfigRec
+{
+    NvRmFreqKHz Emc2xKHz;
+    const NvOdmSdramControllerConfigAdv* pOdmEmcConfig;
+    NvU32 Emc2xClockSource;
+    NvU32 Emc2xDivisor;
+    NvU32 Emc2xUndividedIndex;
+    NvRmFreqKHz CpuLimitKHz;
+} NvRmAp20EmcTimingConfig;
+
+/*****************************************************************************/
+
+/**
+ * Enables/disables module clock.
+ * 
+ * @param hDevice The RM device handle.
+ * @param ModuleId Combined module ID and instance of the target module.
+ * @param ClockState Target clock state.
+ */
+void
+Ap20EnableModuleClock(
+    NvRmDeviceHandle hDevice,
+    NvRmModuleID ModuleId,
+    ModuleClockState ClockState);
+
+// Separate API to control TVDAC clock independently of TVO
+// (when TVDAC is used for CRT)  
+void
+Ap20EnableTvDacClock(
+    NvRmDeviceHandle hDevice,
+    ModuleClockState ClockState);
+
+/**
+ * Resets module (assert/delay/deassert reset signal) if the hold paramter is
+ * NV_FLASE. If the hols paramter is NV_TRUE, just assert the reset and return.
+ * 
+ * @param hDevice The RM device handle.
+ * @param Module Combined module ID and instance of the target module.
+ * @param hold      To hold or relese the reset.
+ */
+void 
+AP20ModuleReset(NvRmDeviceHandle hDevice, NvRmModuleID ModuleId, NvBool hold);
+
+/**
+ * Resets 2D module.
+ * 
+ * @param hRmDevice The RM device handle. 
+ */
+void
+NvRmPrivAp20Reset2D(NvRmDeviceHandle hRmDevice);
+
+/**
+ * Initializes clock source table.
+ * 
+ * @return Pointer to the clock sources descriptor table.
+ */
+NvRmClockSourceInfo* NvRmPrivAp20ClockSourceTableInit(void);
+
+/**
+ * Initializes PLL references table.
+ * 
+ * @param pPllReferencesTable A pointer to a pointer which this function sets
+ *  to the PLL reference table base. 
+ * @param pPllReferencesTableSize A pointer to a variable which this function
+ *  sets to the PLL reference table size.
+ */
+void
+NvRmPrivAp20PllReferenceTableInit(
+    NvRmPllReference** pPllReferencesTable,
+    NvU32* pPllReferencesTableSize);
+
+/**
+ * Controls PLLE.
+ * 
+ * @param hRmDevice The RM device handle.
+ * @param Enable Specifies if PLLE should be enabled or disabled (PLLE power
+ *  management is not supported, and it is never disabled as of now).
+ */
+void NvRmPrivAp20PllEControl(NvRmDeviceHandle hRmDevice, NvBool Enable);
+
+/**
+ * Initializes configuration structures and tables for DVFS controlled clocks.
+ * 
+ * @param hRmDevice The RM device handle. 
+ */
+void
+NvRmPrivAp20ScaledClockConfigInit(NvRmDeviceHandle hRmDevice);
+
+/**
+ * Configures oscillator (main) clock doubler.
+ * 
+ * @param hRmDevice The RM device handle.
+ * @param OscKHz Oscillator (main) clock frequency in kHz.
+ * 
+ * @return NvSuccess if the specified oscillator frequency is supported, and
+ * NvError_NotSupported, otherwise.
+ */
+NvError
+NvRmPrivAp20OscDoublerConfigure(
+    NvRmDeviceHandle hRmDevice,
+    NvRmFreqKHz OscKHz);
+
+/**
+ * Configures maximum core and memory clocks.
+ * 
+ * @param hRmDevice The RM device handle.
+ */
+void
+NvRmPrivAp20FastClockConfig(NvRmDeviceHandle hRmDevice);
+
+/**
+ * Gets module frequency synchronized with EMC speed.
+ * 
+ * @param hRmDevice The RM device handle.
+ * @param Module The target module ID.
+ * 
+ * @return Module frequency in kHz.
+ */
+NvRmFreqKHz NvRmPrivAp20GetEmcSyncFreq(
+    NvRmDeviceHandle hRmDevice,
+    NvRmModuleID Module);
+
+/**
+ * Clips EMC frequency high limit to one of the fixed DFS EMC configurations,
+ * and if necessary adjust CPU high limit respectively.
+ * 
+ * @param hRmDevice The RM device handle.
+ * @param pCpuHighKHz A pointer to the variable, which contains CPU frequency
+ *  high limit in KHz (on entry - requested limit, on exit - clipped limit)
+ * @param pEmcHighKHz A pointer to the variable, which contains EMC frequency
+ *  high limit in KHz (on entry - requested limit, on exit - clipped limit)
+ */
+void
+NvRmPrivAp20ClipCpuEmcHighLimits(
+    NvRmDeviceHandle hRmDevice,
+    NvRmFreqKHz* pCpuHighKHz,
+    NvRmFreqKHz* pEmcHighKHz);
+
+/**
+ * Gets frequencies of DFS controlled clocks
+ * 
+ * @param hRmDevice The RM device handle.
+ * @param pDfsKHz Output storage pointer for DFS clock frequencies structure
+ *  (all frequencies returned in kHz).
+ */
+void
+NvRmPrivAp20DfsClockFreqGet(
+    NvRmDeviceHandle hRmDevice,
+    NvRmDfsFrequencies* pDfsKHz);
+
+/**
+ * Configures DFS controlled clocks
+ * 
+ * @param hRmDevice The RM device handle.
+ * @param pMaxKHz Pointer to the DFS clock frequencies upper limits
+ * @param pDfsKHz Pointer to the target DFS frequencies structure on entry;
+ *  updated with actual DFS clock frequencies on exit.
+ * 
+ * @return NV_TRUE if clock configuration is completed; NV_FALSE if this
+ *  function has to be called again to complete configuration.
+ */
+NvBool
+NvRmPrivAp20DfsClockConfigure(
+    NvRmDeviceHandle hRmDevice,
+    const NvRmDfsFrequencies* pMaxKHz,
+    NvRmDfsFrequencies* pDfsKHz);
+
+/**
+ * Gets DFS domains frequencies to be set for suspend (LP1) entry/exit.
+ *
+ * @param hRmDevice The RM device handle.
+ * @param TargetMv Targeted suspend core voltage in mV.
+ * @param pDfsKHz Pointer to a structure filled in by this function with
+ *  output clock frequencies.
+ */
+void
+NvRmPrivAp20DfsSuspendFreqGet(
+    NvRmDeviceHandle hRmDevice,
+    NvRmMilliVolts TargetMv,
+    NvRmDfsFrequencies* pDfsKHz);
+
+/**
+ * Configures the sdio tap delay
+ * 
+ * @param hRmDevice The RM device handle.
+ * @param Module The target module ID.
+ * @param ClkSourceOffset Clock source offset.
+ * @param ConfiguredFreqKHz The configured frequency in KHz.
+ * 
+ */
+void
+NvRmPrivAp20SdioTapDelayConfigure(
+    NvRmDeviceHandle hRmDevice,
+    NvRmModuleID ModuleId,
+    NvU32 ClkSourceOffset,
+    NvRmFreqKHz ConfiguredFreqKHz);
+
+#ifdef __cplusplus
+}
+#endif  /* __cplusplus */
+
+#endif  // INCLUDED_AP20RM_CLOCKS_H 
diff --git a/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_clocks_info.c b/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_clocks_info.c
new file mode 100644
index 000000000000..0bca2b233664
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_clocks_info.c
@@ -0,0 +1,1827 @@
+/*
+ * Copyright (c) 2008-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include "nvcommon.h"
+#include "nvrm_drf.h"
+#include "ap20rm_clocks.h"
+#include "ap20/arclk_rst.h"
+#include "nvrm_moduleids.h"
+#include "ap20/project_relocation_table.h"
+
+#define NV_COMMON_CLK_RST_FIELDS_INFO(MODULE, H_L) \
+        CLK_RST_CONTROLLER_CLK_SOURCE_##MODULE##_0, \
+        CLK_RST_CONTROLLER_CLK_SOURCE_##MODULE##_0_##MODULE##_CLK_SRC_DEFAULT_MASK, \
+        CLK_RST_CONTROLLER_CLK_SOURCE_##MODULE##_0_##MODULE##_CLK_SRC_SHIFT, \
+        CLK_RST_CONTROLLER_CLK_SOURCE_##MODULE##_0_##MODULE##_CLK_DIVISOR_DEFAULT_MASK, \
+        CLK_RST_CONTROLLER_CLK_SOURCE_##MODULE##_0_##MODULE##_CLK_DIVISOR_SHIFT, \
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_##H_L##_0, \
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_##H_L##_0_CLK_ENB_##MODULE##_FIELD, \
+        CLK_RST_CONTROLLER_RST_DEVICES_##H_L##_0, \
+        CLK_RST_CONTROLLER_RST_DEVICES_##H_L##_0_SWR_##MODULE##_RST_FIELD 
+        
+const NvRmModuleClockInfo g_Ap20ModuleClockTable[] =
+{
+    {   /* Invalid module */
+        NvRmPrivModuleID_System, 0, 0,
+        {
+            NvRmClockSource_SystemBus
+        },
+        NvRmClockDivider_None,
+        0, 0, 0, 0, 0,
+        
+        0,0,
+        CLK_RST_CONTROLLER_RST_DEVICES_L_0,
+        CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TRIG_SYS_RST_FIELD,
+        NvRmDiagModuleID_SystemReset
+    },
+    {   /* VI controller module - VI clock */
+        NvRmModuleID_Vi, 0 , 0,
+        {
+            NvRmClockSource_PllM0,
+            NvRmClockSource_PllC0,
+            NvRmClockSource_PllP0,
+            NvRmClockSource_PllA0
+        },
+        NvRmClockDivider_Fractional_2,
+        CLK_RST_CONTROLLER_CLK_SOURCE_VI_0,
+        CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SRC_DEFAULT_MASK,
+        CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SRC_SHIFT,
+        CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_DIVISOR_DEFAULT_MASK,
+        CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_DIVISOR_SHIFT,
+
+        // Combined VI and VI sensor reset and clock enable controls
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0,
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_VI_FIELD,
+        CLK_RST_CONTROLLER_RST_DEVICES_L_0,
+        CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_VI_RST_FIELD, 
+        NvRmDiagModuleID_Vi
+    },
+    {   /* VI controller module - VI sensor clock
+         * Module sub clock must immediately follow main clock
+         */
+        NvRmModuleID_Vi, 0 , 1,
+        {
+            NvRmClockSource_PllM0,
+            NvRmClockSource_PllC0,
+            NvRmClockSource_PllP0,
+            NvRmClockSource_PllA0
+        },
+        NvRmClockDivider_Fractional_2,
+        CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0,
+        CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_VI_SENSOR_CLK_SRC_DEFAULT_MASK,
+        CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_VI_SENSOR_CLK_SRC_SHIFT,
+        CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_VI_SENSOR_CLK_DIVISOR_DEFAULT_MASK,
+        CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_VI_SENSOR_CLK_DIVISOR_SHIFT,
+
+        // Combined VI and VI sensor reset and clock enable controls
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0,
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_VI_FIELD,
+        CLK_RST_CONTROLLER_RST_DEVICES_L_0,
+        CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_VI_RST_FIELD, 
+        NvRmDiagModuleID_ViSensor
+    },
+
+    {   /* I2S1 controller module */
+        NvRmModuleID_I2s, 0, 0,
+        {
+            NvRmClockSource_PllA0,
+            NvRmClockSource_AudioSync,
+            NvRmClockSource_PllP0,
+            NvRmClockSource_ClkM
+        },
+        NvRmClockDivider_Fractional_2,
+        NV_COMMON_CLK_RST_FIELDS_INFO(I2S1, L),
+        NvRmDiagModuleID_I2s
+    },
+    
+    {   /* I2S2 controller module */
+        NvRmModuleID_I2s, 1, 0,
+        {
+            NvRmClockSource_PllA0,
+            NvRmClockSource_AudioSync,
+            NvRmClockSource_PllP0,
+            NvRmClockSource_ClkM
+        },
+        NvRmClockDivider_Fractional_2,
+        NV_COMMON_CLK_RST_FIELDS_INFO(I2S2, L),
+        NvRmDiagModuleID_I2s
+    },
+
+    {   /* I2C1 controller module */
+        NvRmModuleID_I2c, 0, 0,
+        {
+            NvRmClockSource_PllP0,
+            NvRmClockSource_PllC0,
+            NvRmClockSource_PllM0,
+            NvRmClockSource_ClkM
+        },
+        NvRmClockDivider_Integer_1,
+        NV_COMMON_CLK_RST_FIELDS_INFO(I2C1, L),
+        NvRmDiagModuleID_I2c
+    },
+
+    {   /* I2C2 controller module */
+        NvRmModuleID_I2c, 1, 0,
+        {
+            NvRmClockSource_PllP0,
+            NvRmClockSource_PllC0,
+            NvRmClockSource_PllM0,
+            NvRmClockSource_ClkM
+        },
+        NvRmClockDivider_Integer_1,
+        NV_COMMON_CLK_RST_FIELDS_INFO(I2C2, H),
+        NvRmDiagModuleID_I2c
+    },
+    {   /* I2C2 controller module */
+        NvRmModuleID_I2c, 2, 0,
+        {
+            NvRmClockSource_PllP0,
+            NvRmClockSource_PllC0,
+            NvRmClockSource_PllM0,
+            NvRmClockSource_ClkM
+        },
+        NvRmClockDivider_Integer_1,
+        NV_COMMON_CLK_RST_FIELDS_INFO(I2C3, U),
+        NvRmDiagModuleID_I2c
+    },
+
+    {   /* S/PDIF controller module - S/PDIF OUT clock */
+        NvRmModuleID_Spdif, 0, 0,
+        {
+            NvRmClockSource_PllA0,
+            NvRmClockSource_AudioSync,
+            NvRmClockSource_PllP0,
+            NvRmClockSource_ClkM
+        },
+        NvRmClockDivider_Fractional_2,
+        CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0,
+        CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_SPDIFOUT_CLK_SRC_DEFAULT_MASK,
+        CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_SPDIFOUT_CLK_SRC_SHIFT,
+        CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_SPDIFOUT_CLK_DIVISOR_DEFAULT_MASK,
+        CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_SPDIFOUT_CLK_DIVISOR_SHIFT,
+
+        // Combined SPDIF reset and and clock enable controls
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0,
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SPDIF_FIELD,
+        CLK_RST_CONTROLLER_RST_DEVICES_L_0,
+        CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SPDIF_RST_FIELD,
+        NvRmDiagModuleID_Spdif
+    },
+    {   /* S/PDIF controller module - S/PDIF IN clock
+         * Module sub clock must immediately follow main clock
+         */
+        NvRmModuleID_Spdif, 0, 1,
+        {
+            NvRmClockSource_PllP0,
+            NvRmClockSource_PllC0,
+            NvRmClockSource_PllM0
+        },
+        NvRmClockDivider_Fractional_2,
+        CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0,
+        CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_SPDIFIN_CLK_SRC_DEFAULT_MASK,
+        CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_SPDIFIN_CLK_SRC_SHIFT,
+        CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_SPDIFIN_CLK_DIVISOR_DEFAULT_MASK,
+        CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_SPDIFIN_CLK_DIVISOR_SHIFT,
+
+        // Combined SPDIF reset and and clock enable controls
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0,
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SPDIF_FIELD,
+        CLK_RST_CONTROLLER_RST_DEVICES_L_0,
+        CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SPDIF_RST_FIELD,
+        NvRmDiagModuleID_SpdifIn
+    },
+
+    {   /* PWM controller module */
+        NvRmModuleID_Pwm, 0, 0,
+        {
+            NvRmClockSource_PllP0,
+            NvRmClockSource_PllC0,
+            NvRmClockSource_AudioSync,
+            NvRmClockSource_ClkM
+        },
+        NvRmClockDivider_Fractional_2,
+        NV_COMMON_CLK_RST_FIELDS_INFO(PWM, L),
+        NvRmDiagModuleID_Pwm
+    },
+
+    {   /* SPI controller module */
+        NvRmModuleID_Spi, 0, 0,
+        {
+            NvRmClockSource_PllP0,
+            NvRmClockSource_PllC0,
+            NvRmClockSource_PllM0,
+            NvRmClockSource_ClkM
+        },
+        NvRmClockDivider_Fractional_2,
+        NV_COMMON_CLK_RST_FIELDS_INFO(SPI1, H),
+        NvRmDiagModuleID_Spi
+    },
+
+    {   /* SBC1 controller module */
+        NvRmModuleID_Slink, 0, 0,
+        {
+            NvRmClockSource_PllP0,
+            NvRmClockSource_PllC0,
+            NvRmClockSource_PllM0,
+            NvRmClockSource_ClkM
+        },
+        NvRmClockDivider_Fractional_2,
+        NV_COMMON_CLK_RST_FIELDS_INFO(SBC1, H),
+        NvRmDiagModuleID_Sbc
+    },
+
+    {   /* SBC2 controller module */
+        NvRmModuleID_Slink, 1, 0,
+        {
+            NvRmClockSource_PllP0,
+            NvRmClockSource_PllC0,
+            NvRmClockSource_PllM0,
+            NvRmClockSource_ClkM
+        },
+        NvRmClockDivider_Fractional_2,
+        NV_COMMON_CLK_RST_FIELDS_INFO(SBC2, H),
+        NvRmDiagModuleID_Sbc
+    },
+
+    {   /* SBC3 controller module */
+        NvRmModuleID_Slink, 2, 0,
+        {
+            NvRmClockSource_PllP0,
+            NvRmClockSource_PllC0,
+            NvRmClockSource_PllM0,
+            NvRmClockSource_ClkM
+        },
+        NvRmClockDivider_Fractional_2,
+        NV_COMMON_CLK_RST_FIELDS_INFO(SBC3, H),
+        NvRmDiagModuleID_Sbc
+    },
+
+    {   /* SBC4 controller module */
+        NvRmModuleID_Slink, 3, 0,
+        {
+            NvRmClockSource_PllP0,
+            NvRmClockSource_PllC0,
+            NvRmClockSource_PllM0,
+            NvRmClockSource_ClkM
+        },
+        NvRmClockDivider_Fractional_2,
+        NV_COMMON_CLK_RST_FIELDS_INFO(SBC4, U),
+        NvRmDiagModuleID_Sbc
+    },
+
+    {   /* TWC controller module */
+        NvRmModuleID_Twc, 0, 0,
+        {
+            NvRmClockSource_PllP0,
+            NvRmClockSource_PllC0,
+            NvRmClockSource_PllM0,
+            NvRmClockSource_ClkM
+        },
+        NvRmClockDivider_Fractional_2,
+        NV_COMMON_CLK_RST_FIELDS_INFO(TWC, L),
+        NvRmDiagModuleID_Twc
+    },
+
+    {   /* XIO controller module */
+        NvRmModuleID_Xio, 0, 0,
+        {
+            NvRmClockSource_PllP0,
+            NvRmClockSource_PllC0,
+            NvRmClockSource_PllM0,
+            NvRmClockSource_ClkM
+        },
+        NvRmClockDivider_Fractional_2,
+        NV_COMMON_CLK_RST_FIELDS_INFO(XIO, H),
+        NvRmDiagModuleID_Xio
+    },
+
+    {   /* IDE controller module */
+        NvRmModuleID_Ide, 0, 0,
+        {
+            NvRmClockSource_PllP0,
+            NvRmClockSource_PllC0,
+            NvRmClockSource_PllM0,
+            NvRmClockSource_ClkM
+        },
+        NvRmClockDivider_Fractional_2,
+        NV_COMMON_CLK_RST_FIELDS_INFO(IDE, L),
+        NvRmDiagModuleID_Ide
+    },
+
+    {   /* SDIO1 controller module */
+        NvRmModuleID_Sdio, 0, 0,
+        {
+            NvRmClockSource_PllP0,
+            NvRmClockSource_PllC0,
+            NvRmClockSource_PllM0,
+            NvRmClockSource_ClkM
+        },
+        NvRmClockDivider_Fractional_2,
+        NV_COMMON_CLK_RST_FIELDS_INFO(SDMMC1, L),
+        NvRmDiagModuleID_Sdio
+    },
+
+    {   /* SDIO2 controller module */
+        NvRmModuleID_Sdio, 1, 0,
+        {
+            NvRmClockSource_PllP0,
+            NvRmClockSource_PllC0,
+            NvRmClockSource_PllM0,
+            NvRmClockSource_ClkM
+        },
+        NvRmClockDivider_Fractional_2,
+        NV_COMMON_CLK_RST_FIELDS_INFO(SDMMC2, L),
+        NvRmDiagModuleID_Sdio
+    },
+
+    {   /* SDIO3 controller module */
+        NvRmModuleID_Sdio, 2, 0,
+        {
+            NvRmClockSource_PllP0,
+            NvRmClockSource_PllC0,
+            NvRmClockSource_PllM0,
+            NvRmClockSource_ClkM
+        },
+        NvRmClockDivider_Fractional_2,
+        NV_COMMON_CLK_RST_FIELDS_INFO(SDMMC3, U),
+        NvRmDiagModuleID_Sdio
+    },
+
+    {   /* SDIO4 controller module */
+        NvRmModuleID_Sdio, 3, 0,
+        {
+            NvRmClockSource_PllP0,
+            NvRmClockSource_PllC0,
+            NvRmClockSource_PllM0,
+            NvRmClockSource_ClkM
+        },
+        NvRmClockDivider_Fractional_2,
+        NV_COMMON_CLK_RST_FIELDS_INFO(SDMMC4, L),
+        NvRmDiagModuleID_Sdio
+    },
+
+    {   /* NAND Flash controller module */
+        NvRmModuleID_Nand, 0, 0,
+        {
+            NvRmClockSource_PllP0,
+            NvRmClockSource_PllC0,
+            NvRmClockSource_PllM0,
+            NvRmClockSource_ClkM
+        },
+        NvRmClockDivider_Fractional_2,
+        NV_COMMON_CLK_RST_FIELDS_INFO(NDFLASH, L),
+        NvRmDiagModuleID_NandFlash
+    },
+
+    {   /*  MIPI BB controller module */
+        NvRmModuleID_Mipi, 0, 0,
+        {
+            NvRmClockSource_PllP0,
+            NvRmClockSource_PllC0,
+            NvRmClockSource_PllM0,
+            NvRmClockSource_ClkM
+        },
+        NvRmClockDivider_Fractional_2,
+        NV_COMMON_CLK_RST_FIELDS_INFO(MIPI, H),
+        NvRmDiagModuleID_MipiBaseband
+    },
+
+    {   /* DVC controller module */
+        NvRmModuleID_Dvc, 0, 0,
+        {
+            NvRmClockSource_PllP0,
+            NvRmClockSource_PllC0,
+            NvRmClockSource_PllM0,
+            NvRmClockSource_ClkM
+        },
+        NvRmClockDivider_Integer_1,
+        NV_COMMON_CLK_RST_FIELDS_INFO(DVC_I2C, H),
+        NvRmDiagModuleID_Dvc
+    },
+
+    {   /* UARTA controller module */
+        NvRmModuleID_Uart, 0, 0,
+        {
+            NvRmClockSource_PllP0,
+            NvRmClockSource_PllC0,
+            NvRmClockSource_PllM0,
+            NvRmClockSource_ClkM
+        },
+        NvRmClockDivider_None,
+        CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0,
+        CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_SRC_DEFAULT_MASK,
+        CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_SRC_SHIFT,
+        0, 0,
+
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0,
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_UARTA_FIELD,
+        CLK_RST_CONTROLLER_RST_DEVICES_L_0,
+        CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_UARTA_RST_FIELD,
+        NvRmDiagModuleID_Uart
+    },
+
+    {   /* UARTB controller module */
+        NvRmModuleID_Uart, 1, 0,
+        {
+            NvRmClockSource_PllP0,
+            NvRmClockSource_PllC0,
+            NvRmClockSource_PllM0,
+            NvRmClockSource_ClkM
+        },
+        NvRmClockDivider_None,
+        CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0,
+        CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_CLK_SRC_DEFAULT_MASK,
+        CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_CLK_SRC_SHIFT,
+        0, 0,
+
+        // Combined UARTB and VFIR reset and clock enable controls
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0,
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_UARTB_FIELD,
+        CLK_RST_CONTROLLER_RST_DEVICES_L_0,
+        CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_UARTB_RST_FIELD,
+        NvRmDiagModuleID_Uart
+    },
+
+    {   /* UARTC controller module */
+        NvRmModuleID_Uart, 2, 0,
+        {
+            NvRmClockSource_PllP0,
+            NvRmClockSource_PllC0,
+            NvRmClockSource_PllM0,
+            NvRmClockSource_ClkM
+        },
+        NvRmClockDivider_None,
+        CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0,
+        CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_SRC_DEFAULT_MASK,
+        CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_SRC_SHIFT,
+        0, 0,
+
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0,
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_UARTC_FIELD,
+        CLK_RST_CONTROLLER_RST_DEVICES_H_0,
+        CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_UARTC_RST_FIELD,
+        NvRmDiagModuleID_Uart
+    },
+
+    {   /* UARTD controller module */
+        NvRmModuleID_Uart, 3, 0,
+        {
+            NvRmClockSource_PllP0,
+            NvRmClockSource_PllC0,
+            NvRmClockSource_PllM0,
+            NvRmClockSource_ClkM
+        },
+        NvRmClockDivider_None,
+        CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0,
+        CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_CLK_SRC_DEFAULT_MASK,
+        CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_CLK_SRC_SHIFT,
+        0, 0,
+
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0,
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_UARTD_FIELD,
+        CLK_RST_CONTROLLER_RST_DEVICES_U_0,
+        CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_UARTD_RST_FIELD,
+        NvRmDiagModuleID_Uart
+    },
+
+    {   /* UARTE controller module */
+        NvRmModuleID_Uart, 4, 0,
+        {
+            NvRmClockSource_PllP0,
+            NvRmClockSource_PllC0,
+            NvRmClockSource_PllM0,
+            NvRmClockSource_ClkM
+        },
+        NvRmClockDivider_None,
+        CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0,
+        CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_UARTE_CLK_SRC_DEFAULT_MASK,
+        CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_UARTE_CLK_SRC_SHIFT,
+        0, 0,
+
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0,
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_UARTE_FIELD,
+        CLK_RST_CONTROLLER_RST_DEVICES_U_0,
+        CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_UARTE_RST_FIELD,
+        NvRmDiagModuleID_Uart
+    },
+
+    {   /* VFIR controller module */
+        NvRmModuleID_Vfir, 0, 0,
+        {
+            NvRmClockSource_PllP0,
+            NvRmClockSource_PllC0,
+            NvRmClockSource_PllM0,
+            NvRmClockSource_ClkM
+        },
+        NvRmClockDivider_Fractional_2,
+        CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0,
+        CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_VFIR_CLK_SRC_DEFAULT_MASK,
+        CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_VFIR_CLK_SRC_SHIFT,
+        CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_VFIR_CLK_DIVISOR_DEFAULT_MASK,
+        CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_VFIR_CLK_DIVISOR_SHIFT,
+
+        // Combined UARTB and VFIR reset and clock enable controls
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0,
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_UARTB_FIELD,
+        CLK_RST_CONTROLLER_RST_DEVICES_L_0,
+        CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_UARTB_RST_FIELD,
+        NvRmDiagModuleID_Vfir
+    },
+
+    {   /* Host1x module */
+        NvRmModuleID_GraphicsHost, 0, 0,
+        {
+            NvRmClockSource_PllM0,
+            NvRmClockSource_PllC0,
+            NvRmClockSource_PllP0,
+            NvRmClockSource_PllA0
+        },
+        NvRmClockDivider_Fractional_2,
+        NV_COMMON_CLK_RST_FIELDS_INFO(HOST1X, L),
+        NvRmDiagModuleID_Host1x
+    },
+
+    {   /* EPP controller module */
+        NvRmModuleID_Epp, 0, 0,
+        {
+            NvRmClockSource_PllM0,
+            NvRmClockSource_PllC0,
+            NvRmClockSource_PllP0,
+            NvRmClockSource_PllA0
+        },
+        NvRmClockDivider_Fractional_2,
+        NV_COMMON_CLK_RST_FIELDS_INFO(EPP, L),
+        NvRmDiagModuleID_Epp
+    },
+
+    {   /* MPE controller module */
+        NvRmModuleID_Mpe, 0, 0,
+        {
+            NvRmClockSource_PllM0,
+            NvRmClockSource_PllC0,
+            NvRmClockSource_PllP0,
+            NvRmClockSource_PllA0
+        },
+        NvRmClockDivider_Fractional_2,
+        NV_COMMON_CLK_RST_FIELDS_INFO(MPE, H),
+        NvRmDiagModuleID_Mpe
+    },
+
+    {   /* 2D controller module */
+        NvRmModuleID_2D, 0, 0,
+        {
+            NvRmClockSource_PllM0,
+            NvRmClockSource_PllC0,
+            NvRmClockSource_PllP0,
+            NvRmClockSource_PllA0
+        },
+        NvRmClockDivider_Fractional_2,
+        CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0,
+        CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_G2D_CLK_SRC_DEFAULT_MASK,
+        CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_G2D_CLK_SRC_SHIFT,
+        CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_G2D_CLK_DIVISOR_DEFAULT_MASK,
+        CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_G2D_CLK_DIVISOR_SHIFT,
+
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0,
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_2D_FIELD,
+        CLK_RST_CONTROLLER_RST_DEVICES_L_0,
+        CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_2D_RST_FIELD, 
+        NvRmDiagModuleID_2d
+    },
+
+    {   /* 3D controller module */
+        NvRmModuleID_3D, 0, 0,
+        {
+            NvRmClockSource_PllM0,
+            NvRmClockSource_PllC0,
+            NvRmClockSource_PllP0,
+            NvRmClockSource_PllA0
+        },
+        NvRmClockDivider_Fractional_2,
+        CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0,
+        CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_G3D_CLK_SRC_DEFAULT_MASK,
+        CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_G3D_CLK_SRC_SHIFT,
+        CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_G3D_CLK_DIVISOR_DEFAULT_MASK,
+        CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_G3D_CLK_DIVISOR_SHIFT,
+
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0,
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_3D_FIELD,
+        CLK_RST_CONTROLLER_RST_DEVICES_L_0,
+        CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_3D_RST_FIELD, 
+        NvRmDiagModuleID_3d
+    },
+
+    {   /* Display 1 controller module */
+        NvRmModuleID_Display, 0, 0,
+        {
+            NvRmClockSource_PllP0,
+            NvRmClockSource_PllD0,
+            NvRmClockSource_PllC0,
+            NvRmClockSource_ClkM
+        },
+        NvRmClockDivider_None,
+        CLK_RST_CONTROLLER_CLK_SOURCE_DISP1_0,
+        CLK_RST_CONTROLLER_CLK_SOURCE_DISP1_0_DISP1_CLK_SRC_DEFAULT_MASK,
+        CLK_RST_CONTROLLER_CLK_SOURCE_DISP1_0_DISP1_CLK_SRC_SHIFT,
+        0, 0,
+
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0,
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_DISP1_FIELD,
+        CLK_RST_CONTROLLER_RST_DEVICES_L_0,
+        CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_DISP1_RST_FIELD, 
+        NvRmDiagModuleID_Display
+    },
+
+    {   /* Display 2 controller module */
+        NvRmModuleID_Display, 1, 0,
+        {
+            NvRmClockSource_PllP0,
+            NvRmClockSource_PllD0,
+            NvRmClockSource_PllC0,
+            NvRmClockSource_ClkM
+        },
+        NvRmClockDivider_None,
+        CLK_RST_CONTROLLER_CLK_SOURCE_DISP2_0,
+        CLK_RST_CONTROLLER_CLK_SOURCE_DISP2_0_DISP2_CLK_SRC_DEFAULT_MASK,
+        CLK_RST_CONTROLLER_CLK_SOURCE_DISP2_0_DISP2_CLK_SRC_SHIFT,
+        0, 0,
+
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0,
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_DISP2_FIELD,
+        CLK_RST_CONTROLLER_RST_DEVICES_L_0,
+        CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_DISP2_RST_FIELD, 
+        NvRmDiagModuleID_Display
+    },
+
+    {   /* TVO controller module - TVO clock */
+        NvRmModuleID_Tvo, 0, 0,
+        {
+            NvRmClockSource_PllP0,
+            NvRmClockSource_PllD0,
+            NvRmClockSource_PllC0,
+            NvRmClockSource_ClkM
+        },
+        NvRmClockDivider_Fractional_2,
+        CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0,
+        CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_TVO_CLK_SRC_DEFAULT_MASK,
+        CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_TVO_CLK_SRC_SHIFT,
+        CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_TVO_CLK_DIVISOR_DEFAULT_MASK,
+        CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_TVO_CLK_DIVISOR_SHIFT,
+
+        // Combined TVO, and CVE reset and and clock enable controls
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0,
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_TVO_FIELD,
+        CLK_RST_CONTROLLER_RST_DEVICES_H_0,
+        CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_TVO_RST_FIELD,
+        NvRmDiagModuleID_Tvo
+    },
+    {   /* TVO controller module - CVE clock
+         * Module sub clocks must immediately follow main clock
+         */
+        NvRmModuleID_Tvo, 0, 1,
+        {
+            NvRmClockSource_PllP0,
+            NvRmClockSource_PllD0,
+            NvRmClockSource_PllC0,
+            NvRmClockSource_ClkM
+        },
+        NvRmClockDivider_Fractional_2,
+        CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0,
+        CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_CVE_CLK_SRC_DEFAULT_MASK,
+        CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_CVE_CLK_SRC_SHIFT,
+        CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_CVE_CLK_DIVISOR_DEFAULT_MASK,
+        CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_CVE_CLK_DIVISOR_SHIFT,
+
+        // Combined TVO, and CVE reset and and clock enable controls
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0,
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_TVO_FIELD,
+        CLK_RST_CONTROLLER_RST_DEVICES_H_0,
+        CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_TVO_RST_FIELD,
+        NvRmDiagModuleID_Cve
+    },
+    {   /* TVO controller module - TVDAC clock
+         * Module sub clocks must immediately follow main clock
+         */
+        NvRmModuleID_Tvo, 0, 2,
+        {
+            NvRmClockSource_PllP0,
+            NvRmClockSource_PllD0,
+            NvRmClockSource_PllC0,
+            NvRmClockSource_ClkM
+        },
+        NvRmClockDivider_Fractional_2,
+        CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0,
+        CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_TVDAC_CLK_SRC_DEFAULT_MASK,
+        CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_TVDAC_CLK_SRC_SHIFT,
+        CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_TVDAC_CLK_DIVISOR_DEFAULT_MASK,
+        CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_TVDAC_CLK_DIVISOR_SHIFT,
+
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0,
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_TVDAC_FIELD,
+        CLK_RST_CONTROLLER_RST_DEVICES_H_0,
+        CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_TVDAC_RST_FIELD,
+        NvRmDiagModuleID_Tvdac
+    },
+
+    {   /* HDMI controller module */
+        NvRmModuleID_Hdmi, 0, 0,
+        {
+            NvRmClockSource_PllP0,
+            NvRmClockSource_PllD0,
+            NvRmClockSource_PllC0,
+            NvRmClockSource_ClkM
+        },
+        NvRmClockDivider_Fractional_2,
+        NV_COMMON_CLK_RST_FIELDS_INFO(HDMI, H),
+        NvRmDiagModuleID_Hdmi
+    },
+
+    {   /* VDE controller module (VDE and BSEV clocks)
+         * These clocks should always be enabled/reset in sync. Threfore,
+         * no need for separate VDE and BSEV subclock descriptors
+         */
+        NvRmModuleID_Vde, 0, 0,
+        {
+            NvRmClockSource_PllP0,
+            NvRmClockSource_PllC0,
+            NvRmClockSource_PllM0,
+            NvRmClockSource_ClkM
+        },
+        NvRmClockDivider_Fractional_2,
+        CLK_RST_CONTROLLER_CLK_SOURCE_VDE_0,
+        CLK_RST_CONTROLLER_CLK_SOURCE_VDE_0_VDE_CLK_SRC_DEFAULT_MASK,
+        CLK_RST_CONTROLLER_CLK_SOURCE_VDE_0_VDE_CLK_SRC_SHIFT,
+        CLK_RST_CONTROLLER_CLK_SOURCE_VDE_0_VDE_CLK_DIVISOR_DEFAULT_MASK,
+        CLK_RST_CONTROLLER_CLK_SOURCE_VDE_0_VDE_CLK_DIVISOR_SHIFT,
+
+       // Combined VDE and BSEV reset and and clock enable controls
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0,
+        (CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_VDE_FIELD |
+         CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_BSEV_FIELD),
+        CLK_RST_CONTROLLER_RST_DEVICES_H_0,
+        (CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_VDE_RST_FIELD |
+        CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_BSEV_RST_FIELD),
+        NvRmDiagModuleID_Vde
+    },
+
+    {   /*  BSEA controller module */
+        NvRmModuleID_BseA, 0, 0,
+        {
+            NvRmClockSource_SystemBus
+        },
+        NvRmClockDivider_None,
+        0, 0, 0, 0, 0,
+
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0,
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_BSEA_FIELD,
+        CLK_RST_CONTROLLER_RST_DEVICES_H_0,
+        CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_BSEA_RST_FIELD,
+        NvRmDiagModuleID_Bsea
+    },
+
+    {   /* VCP controller module */
+        NvRmModuleID_Vcp, 0, 0,
+        {
+            NvRmClockSource_SystemBus
+        },
+        NvRmClockDivider_None,
+        0, 0, 0, 0, 0,
+
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0,
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_VCP_FIELD,
+        CLK_RST_CONTROLLER_RST_DEVICES_L_0,
+        CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_VCP_RST_FIELD,
+        NvRmDiagModuleID_Vcp
+    },
+
+    {   /* Timer controller module */
+        NvRmModuleID_Timer, 0, 0,
+        {
+            NvRmClockSource_SystemBus
+        },
+        NvRmClockDivider_None,
+        0, 0, 0, 0, 0,
+
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0,
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_TMR_FIELD,
+        CLK_RST_CONTROLLER_RST_DEVICES_L_0,
+        CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TMR_RST_FIELD,
+        NvRmDiagModuleID_Timer
+    },
+
+    {   /*  System Monitor controller module */
+        NvRmModuleID_SysStatMonitor, 0, 0,
+        {
+            NvRmClockSource_SystemBus
+        },
+        NvRmClockDivider_None,
+        0, 0, 0, 0, 0,
+
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0,
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_STAT_MON_FIELD,
+        CLK_RST_CONTROLLER_RST_DEVICES_H_0,
+        CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_STAT_MON_RST_FIELD,
+        NvRmDiagModuleID_StatMon
+    },
+
+    {   /* GPIO controller module */
+        NvRmPrivModuleID_Gpio, 0, 0,
+        {
+            NvRmClockSource_SystemBus
+        },
+        NvRmClockDivider_None,
+        0, 0, 0, 0, 0,
+
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0,
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_GPIO_FIELD,
+        CLK_RST_CONTROLLER_RST_DEVICES_L_0,
+        CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_GPIO_RST_FIELD,
+        NvRmDiagModuleID_Gpio
+    },
+
+    {   /* USB controller module */
+        NvRmModuleID_Usb2Otg, 0, 0,
+        {
+            NvRmClockSource_PllU0
+        },
+        NvRmClockDivider_None,
+        0, 0, 0, 0, 0,
+
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0,
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_USBD_FIELD,
+        CLK_RST_CONTROLLER_RST_DEVICES_L_0,
+        CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_USBD_RST_FIELD,
+        NvRmDiagModuleID_Usb
+    },
+
+    {   /* USB2 controller module */
+        NvRmModuleID_Usb2Otg, 1, 0,
+        {
+            NvRmClockSource_PllU0
+        },
+        NvRmClockDivider_None,
+        0, 0, 0, 0, 0,
+
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0,
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_USB2_FIELD,
+        CLK_RST_CONTROLLER_RST_DEVICES_H_0,
+        CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_USB2_RST_FIELD,
+        NvRmDiagModuleID_Usb
+    },
+
+    {   /* USB3 controller module */
+        NvRmModuleID_Usb2Otg, 2, 0,
+        {
+            NvRmClockSource_PllU0
+        },
+        NvRmClockDivider_None,
+        0, 0, 0, 0, 0,
+
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0,
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_USB3_FIELD,
+        CLK_RST_CONTROLLER_RST_DEVICES_H_0,
+        CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_USB3_RST_FIELD,
+        NvRmDiagModuleID_Usb
+    },
+
+    {   /*  APB DMA controller module */
+        NvRmPrivModuleID_ApbDma, 0, 0,
+        {
+            NvRmClockSource_Apb
+        },
+        NvRmClockDivider_None,
+        0, 0, 0, 0, 0,
+
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0,
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_APBDMA_FIELD,
+        CLK_RST_CONTROLLER_RST_DEVICES_H_0,
+        CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_APBDMA_RST_FIELD,
+        NvRmDiagModuleID_ApbDma
+    },
+
+    {   /*  AC97 controller module */
+        NvRmModuleID_Ac97, 0, 0,
+        {
+            NvRmClockSource_Apb
+        },
+        NvRmClockDivider_None,
+        0, 0, 0, 0, 0,
+
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0,
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_AC97_FIELD,
+        CLK_RST_CONTROLLER_RST_DEVICES_L_0,
+        CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_AC97_RST_FIELD,
+        NvRmDiagModuleID_Ac97
+    },
+
+    {   /*  Keyboard controller module */
+        NvRmModuleID_Kbc, 0, 0,
+        {
+            NvRmClockSource_Apb
+        },
+        NvRmClockDivider_None,
+        0, 0, 0, 0, 0,
+
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0,
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_KBC_FIELD,
+        CLK_RST_CONTROLLER_RST_DEVICES_H_0,
+        CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_KBC_RST_FIELD,
+        NvRmDiagModuleID_Kbc
+    },
+
+    {   /* RTC  controller module */
+        NvRmModuleID_Rtc, 0, 0,
+        {
+            NvRmClockSource_Apb
+        },
+        NvRmClockDivider_None,
+        0, 0, 0, 0, 0,
+
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0,
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_RTC_FIELD,
+        CLK_RST_CONTROLLER_RST_DEVICES_L_0,
+        CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_RTC_RST_FIELD,
+        NvRmDiagModuleID_Rtc
+    },
+
+    {   /*  Fuse controller module */
+        NvRmModuleID_Fuse, 0, 0,
+        {
+            NvRmClockSource_Apb
+        },
+        NvRmClockDivider_None,
+        0, 0, 0, 0, 0,
+
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0,
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_FUSE_FIELD,
+        CLK_RST_CONTROLLER_RST_DEVICES_H_0,
+        CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_FUSE_RST_FIELD,
+        NvRmDiagModuleID_Fuse
+    },
+
+    {   /*  KFuse controller module */
+        NvRmModuleID_KFuse, 0, 0,
+        {
+            NvRmClockSource_Apb
+        },
+        NvRmClockDivider_None,
+        0, 0, 0, 0, 0,
+
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0,
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_KFUSE_FIELD,
+        CLK_RST_CONTROLLER_RST_DEVICES_H_0,
+        CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_KFUSE_RST_FIELD,
+        NvRmDiagModuleID_KFuse
+    },
+
+    {   /*  Power Management controller module */
+        NvRmModuleID_Pmif, 0, 0,
+        {
+            NvRmClockSource_Apb
+        },
+        NvRmClockDivider_None,
+        0, 0, 0, 0, 0,
+
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0,
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_PMC_FIELD,
+        CLK_RST_CONTROLLER_RST_DEVICES_H_0,
+        CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_PMC_RST_FIELD,
+        NvRmDiagModuleID_Pmc
+    },
+
+    {   /* COP (AVP) cache controller module */
+        NvRmModuleID_CacheMemCtrl, 0, 0,
+        {
+            NvRmClockSource_SystemBus
+        },
+        NvRmClockDivider_None,
+        0, 0, 0, 0, 0,
+
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0,
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CACHE2_FIELD,
+        CLK_RST_CONTROLLER_RST_DEVICES_L_0,
+        CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CACHE2_RST_FIELD,
+        NvRmDiagModuleID_Cache
+    },
+
+    {   /* DSI controller module */
+        NvRmModuleID_Dsi, 0, 0,
+        {
+            NvRmClockSource_PllD0
+        },
+        NvRmClockDivider_None,
+        0, 0, 0, 0, 0,
+
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0,
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_DSI_FIELD,
+        CLK_RST_CONTROLLER_RST_DEVICES_H_0,
+        CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_DSI_RST_FIELD,
+        NvRmDiagModuleID_Dsi
+    },
+
+    {   /* CSI  controller module */
+        NvRmModuleID_Csi, 0, 0,
+        {
+            NvRmClockSource_SystemBus // TODO: find a proper clock source
+        },
+        NvRmClockDivider_None,
+        0, 0, 0, 0, 0,
+
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0,
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_CSI_FIELD,
+        CLK_RST_CONTROLLER_RST_DEVICES_H_0,
+        CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_CSI_RST_FIELD,
+        NvRmDiagModuleID_Csi
+    },
+
+    {   /* ISP controller module */
+        NvRmModuleID_Isp, 0, 0,
+        {
+            NvRmClockSource_SystemBus // TODO: find a proper clock source
+        },
+        NvRmClockDivider_None,
+        0, 0, 0, 0, 0,
+
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0,
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_ISP_FIELD,
+        CLK_RST_CONTROLLER_RST_DEVICES_L_0,
+        CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_ISP_RST_FIELD,
+        NvRmDiagModuleID_Isp
+    },
+
+    {   /*  CPU module */
+        NvRmModuleID_Cpu, 0, 0,
+        {
+            NvRmClockSource_CpuBus
+        },
+        NvRmClockDivider_None,
+        0, 0, 0, 0, 0,
+
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0,
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CPU_FIELD,
+        CLK_RST_CONTROLLER_RST_DEVICES_L_0,
+        CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CPU_RST_FIELD,
+        NvRmDiagModuleID_Cpu
+    },
+
+    {   /*  COP (AVP) module */
+        NvRmModuleID_Avp, 0, 0,
+        {
+            NvRmClockSource_SystemBus // TODO: Add COP skipper source?
+        },
+        NvRmClockDivider_None,
+        0, 0, 0, 0, 0,
+
+        0, 0,
+        CLK_RST_CONTROLLER_RST_DEVICES_L_0,
+        CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_COP_RST_FIELD,
+        NvRmDiagModuleID_Coprocessor
+    },
+
+    {
+        NvRmModuleID_OneWire, 0, 0,
+        {
+            NvRmClockSource_PllP0,
+            NvRmClockSource_PllC0,
+            NvRmClockSource_PllM0,
+            NvRmClockSource_ClkM,
+        },
+        NvRmClockDivider_Fractional_2,
+        NV_COMMON_CLK_RST_FIELDS_INFO(OWR,U),
+        NvRmDiagModuleID_OneWire
+    },
+
+    {
+        NvRmModuleID_SyncNor, 0, 0,
+        {
+            NvRmClockSource_PllP0,
+            NvRmClockSource_PllC0,
+            NvRmClockSource_PllM0,
+            NvRmClockSource_ClkM,
+        },
+        NvRmClockDivider_Fractional_2,
+        CLK_RST_CONTROLLER_CLK_SOURCE_NOR_0,
+        CLK_RST_CONTROLLER_CLK_SOURCE_NOR_0_SNOR_CLK_SRC_DEFAULT_MASK,
+        CLK_RST_CONTROLLER_CLK_SOURCE_NOR_0_SNOR_CLK_SRC_SHIFT,
+        CLK_RST_CONTROLLER_CLK_SOURCE_NOR_0_SNOR_CLK_DIVISOR_DEFAULT_MASK,
+        CLK_RST_CONTROLLER_CLK_SOURCE_NOR_0_SNOR_CLK_DIVISOR_SHIFT,
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0,
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SNOR_FIELD,
+        CLK_RST_CONTROLLER_RST_DEVICES_H_0,
+        CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SNOR_RST_FIELD,
+        NvRmDiagModuleID_SyncNor
+    },
+
+    {
+        NvRmModuleID_AvpUcq, 0, 0,
+        {
+            NvRmClockSource_SystemBus // TODO: Add COP skipper source?
+        },
+        NvRmClockDivider_None,
+        0, 0, 0, 0, 0,
+
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0,
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_AVPUCQ_FIELD,
+        CLK_RST_CONTROLLER_RST_DEVICES_U_0,
+        CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_AVPUCQ_RST_FIELD,
+        NvRmDiagModuleID_AvpUcq
+    },
+
+    {
+        NvRmPrivModuleID_Pcie, 0, 0,
+        {
+            NvRmClockSource_CpuBridge
+        },
+        NvRmClockDivider_None,
+        0, 0, 0, 0, 0,
+
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0,
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_PCIE_FIELD,
+        CLK_RST_CONTROLLER_RST_DEVICES_U_0,
+        CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_PCIE_RST_FIELD,
+        NvRmDiagModuleID_Pcie
+    },
+
+    {   /*  Memory controller module */
+        NvRmPrivModuleID_MemoryController, 0, 0,
+        {
+            NvRmClockSource_PllM0,
+            NvRmClockSource_PllC0,
+            NvRmClockSource_PllP0,
+            NvRmClockSource_ClkM,
+        },
+        // MC clock is the same as EMC1x domain clock
+        NvRmClockDivider_Integer_2,
+        CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0,
+        CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_SRC_DEFAULT_MASK,
+        CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_SRC_SHIFT,
+        CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_DIVISOR_DEFAULT_MASK,
+        CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_DIVISOR_SHIFT,
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0,
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MEM_FIELD,
+        CLK_RST_CONTROLLER_RST_DEVICES_H_0,
+        CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MEM_RST_FIELD,
+        NvRmDiagModuleID_Mc
+    },
+
+    {   /*  External Memory controller module */
+        NvRmPrivModuleID_ExternalMemoryController, 0, 0,
+        {
+            NvRmClockSource_PllM0,
+            NvRmClockSource_PllC0,
+            NvRmClockSource_PllP0,
+            NvRmClockSource_ClkM,
+        },
+        NvRmClockDivider_Fractional_2,
+        CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0,
+        CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_SRC_DEFAULT_MASK,
+        CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_SRC_SHIFT,
+        CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_DIVISOR_DEFAULT_MASK,
+        CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_DIVISOR_SHIFT,
+
+        // EMC has 1x and 2x domains clock enable bits located in the source
+        // register. There is also a gloabl clock enable bit in CLK_OUT_ENB_L_0
+        // register, which is not described here. All 3 bits are set/cleared
+        // in Ap20EnableModuleClock() function below.
+        CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0,
+        (CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_ENB_FIELD |
+         CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_1X_CLK_ENB_FIELD),
+        CLK_RST_CONTROLLER_RST_DEVICES_H_0,
+        CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_EMC_RST_FIELD,
+        NvRmDiagModuleID_Emc
+    }
+};
+
+NvU32 const g_Ap20ModuleClockTableSize = NV_ARRAY_SIZE(g_Ap20ModuleClockTable);
+
+/*****************************************************************************/
+/*****************************************************************************/
+// Clock sources
+
+static const NvRmFixedClockInfo s_Ap20FixedClockTable[] =
+{
+    {
+        NvRmClockSource_ClkS,
+        NvRmClockSource_Invalid,
+        0, 0
+    },
+    {
+        NvRmClockSource_ClkM,
+        NvRmClockSource_Invalid,
+        0, 0
+    },
+    {
+        NvRmClockSource_ClkD,
+        NvRmClockSource_ClkM,
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0,
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_M_DOUBLER_ENB_FIELD
+    },
+
+    {
+        NvRmClockSource_ExtSpdf,
+        NvRmClockSource_Invalid,
+        0, 0
+    },
+    {
+        NvRmClockSource_ExtI2s1,
+        NvRmClockSource_Invalid,
+        0, 0
+    },
+    {
+        NvRmClockSource_ExtI2s2,
+        NvRmClockSource_Invalid,
+        0, 0
+    },
+    {
+        NvRmClockSource_ExtAc97,
+        NvRmClockSource_Invalid,
+        0, 0
+    },
+    {
+        NvRmClockSource_ExtAudio1,
+        NvRmClockSource_Invalid,
+        0, 0
+    },
+    {
+        NvRmClockSource_ExtAudio2,
+        NvRmClockSource_Invalid,
+        0, 0
+    },
+    {
+        NvRmClockSource_ExtVi,
+        NvRmClockSource_Invalid,
+        0, 0
+    }
+};
+
+static const NvU32 s_Ap20FixedClockTableSize = NV_ARRAY_SIZE(s_Ap20FixedClockTable);
+
+/*****************************************************************************/
+
+// TODO: Specify PLL ref divider in OSC control reg as PLL C, D, M, P, U source
+
+/*
+ * Notation clarification: in h/w documentation PLL base outputs (except PLLA
+ * output) are denoted as PllX_OUT0, and the seconadry PLL outputs (if any)
+ * after fractional dividers are denoted as PllX_OUT1, PllX_OUT2, .... However,
+ * no h/w name is defined for the base PLLA output, and the output of the PLLA
+ * secondary divider is marked as PllA_OUT0 (not PllA_OUT1). Threfore, we use
+ * PllA1 (not PllA0) to denote base PLLA clock.
+ */
+static const NvRmPllClockInfo s_Ap20PllClockTable[] =
+{
+    {   /* PLLA base output */
+        NvRmClockSource_PllA1,
+        NvRmClockSource_PllP1,
+        NvRmPllType_LP,
+        CLK_RST_CONTROLLER_PLLA_BASE_0,
+        CLK_RST_CONTROLLER_PLLA_MISC_0,
+        50000,
+        1400000
+    },
+
+    {   /* PLLC base output */
+        NvRmClockSource_PllC0,
+        NvRmClockSource_ClkM,
+        NvRmPllType_LP,
+        CLK_RST_CONTROLLER_PLLC_BASE_0,
+        CLK_RST_CONTROLLER_PLLC_MISC_0,
+        100000,
+        1400000
+    },
+
+    {   /* PLLM base output */
+        NvRmClockSource_PllM0,
+        NvRmClockSource_ClkM,
+        NvRmPllType_LP,
+        CLK_RST_CONTROLLER_PLLM_BASE_0,
+        CLK_RST_CONTROLLER_PLLM_MISC_0,
+        100000,
+        1200000
+    },
+
+    {   /* PLLX base output */
+        NvRmClockSource_PllX0,
+        NvRmClockSource_ClkM,
+        NvRmPllType_LP,
+        CLK_RST_CONTROLLER_PLLX_BASE_0,
+        CLK_RST_CONTROLLER_PLLX_MISC_0,
+        100000,
+        1400000
+    },
+
+    {   /* PLLP base output */
+        NvRmClockSource_PllP0,
+        NvRmClockSource_ClkM,
+        NvRmPllType_LP,
+        CLK_RST_CONTROLLER_PLLP_BASE_0,
+        CLK_RST_CONTROLLER_PLLP_MISC_0,
+        100000,
+        1400000
+    },
+
+    {   /* PLLD base output */
+        NvRmClockSource_PllD0,
+        NvRmClockSource_ClkM,
+        NvRmPllType_MIPI,
+        CLK_RST_CONTROLLER_PLLD_BASE_0,
+        CLK_RST_CONTROLLER_PLLD_MISC_0,
+        100000,
+        1000000
+    },
+
+    {   /* PLLU base output */
+        NvRmClockSource_PllU0,
+        NvRmClockSource_ClkM,
+        NvRmPllType_UHS,
+        CLK_RST_CONTROLLER_PLLU_BASE_0,
+        CLK_RST_CONTROLLER_PLLU_MISC_0,
+        480000,
+        960000
+    }
+};
+
+static const NvU32 s_Ap20PllClockTableSize = NV_ARRAY_SIZE(s_Ap20PllClockTable);
+
+/*****************************************************************************/
+
+static const NvRmDividerClockInfo s_Ap20DividerClockTable[] =
+{
+    {   /* PLLA0 - PLLA secondary output */
+        NvRmClockSource_PllA0,
+        NvRmClockSource_PllA1,
+        NvRmClockDivider_Fractional_2,
+
+        CLK_RST_CONTROLLER_PLLA_OUT_0,
+        CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RATIO_DEFAULT_MASK,
+        CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RATIO_SHIFT,
+
+        CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_CLKEN_FIELD |
+         CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RSTN_FIELD,
+
+        ((CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_CLKEN_ENABLE <<
+          CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_CLKEN_SHIFT) |
+         (CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RSTN_RESET_DISABLE <<
+          CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RSTN_SHIFT)),
+
+        ((CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_CLKEN_DISABLE <<
+          CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_CLKEN_SHIFT) |
+         (CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RSTN_RESET_DISABLE <<
+          CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RSTN_SHIFT)),
+
+        NVRM_VARIABLE_DIVIDER
+    },
+
+    {   /* PLLC1 - PLLC secondary output */
+        NvRmClockSource_PllC1,
+        NvRmClockSource_PllC0,
+        NvRmClockDivider_Fractional_2,
+
+        CLK_RST_CONTROLLER_PLLC_OUT_0,
+        CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_RATIO_DEFAULT_MASK,
+        CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_RATIO_SHIFT,
+
+        CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_CLKEN_FIELD |
+         CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_RSTN_FIELD,
+
+        ((CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_CLKEN_ENABLE <<
+          CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_CLKEN_SHIFT) |
+         (CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_RSTN_RESET_DISABLE <<
+          CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_RSTN_SHIFT)),
+
+        ((CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_CLKEN_DISABLE <<
+          CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_CLKEN_SHIFT) |
+         (CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_RSTN_RESET_DISABLE <<
+          CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_RSTN_SHIFT)),
+
+        NVRM_VARIABLE_DIVIDER
+    },
+
+    {   /* PLLM1 - PLLM secondary ouput */
+        NvRmClockSource_PllM1,
+        NvRmClockSource_PllM0,
+        NvRmClockDivider_Fractional_2,
+
+        CLK_RST_CONTROLLER_PLLM_OUT_0,
+        CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_RATIO_DEFAULT_MASK,
+        CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_RATIO_SHIFT,
+
+        CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_CLKEN_FIELD |
+         CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_RSTN_FIELD,
+
+        ((CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_CLKEN_ENABLE <<
+          CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_CLKEN_SHIFT) |
+         (CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_RSTN_RESET_DISABLE <<
+          CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_RSTN_SHIFT)),
+
+        ((CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_CLKEN_DISABLE <<
+          CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_CLKEN_SHIFT) |
+         (CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_RSTN_RESET_DISABLE <<
+          CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_RSTN_SHIFT)),
+
+        NVRM_VARIABLE_DIVIDER
+    },
+
+    {   /* PLLP1 - PLLP secondary output (overridden) */
+        NvRmClockSource_PllP1,
+        NvRmClockSource_PllP0,
+        NvRmClockDivider_Fractional_2,
+
+        CLK_RST_CONTROLLER_PLLP_OUTA_0,
+        CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_RATIO_DEFAULT_MASK,
+        CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_RATIO_SHIFT,
+
+        CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_OVRRIDE_FIELD |
+         CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_CLKEN_FIELD |
+         CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_RSTN_FIELD,
+
+        ((CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_OVRRIDE_ENABLE <<
+          CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_OVRRIDE_SHIFT) |
+         (CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_CLKEN_ENABLE <<
+          CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_CLKEN_SHIFT) |
+         (CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_RSTN_RESET_DISABLE <<
+          CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_RSTN_SHIFT)),
+
+        ((CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_OVRRIDE_DISABLE <<
+          CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_OVRRIDE_SHIFT) |
+         (CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_CLKEN_DISABLE <<
+          CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_CLKEN_SHIFT) |
+         (CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_RSTN_RESET_DISABLE <<
+          CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_RSTN_SHIFT)),
+
+        NVRM_VARIABLE_DIVIDER
+    },
+
+    {   /* PLLP2 - PLLP secondary output (overridden) */
+        NvRmClockSource_PllP2,
+        NvRmClockSource_PllP0,
+        NvRmClockDivider_Fractional_2,
+
+        CLK_RST_CONTROLLER_PLLP_OUTA_0,
+        CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_RATIO_DEFAULT_MASK,
+        CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_RATIO_SHIFT,
+
+        CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_OVRRIDE_FIELD |
+         CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_CLKEN_FIELD |
+         CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_RSTN_FIELD,
+
+        ((CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_OVRRIDE_ENABLE <<
+          CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_OVRRIDE_SHIFT) |
+         (CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_CLKEN_ENABLE <<
+          CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_CLKEN_SHIFT) |
+         (CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_RSTN_RESET_DISABLE <<
+          CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_RSTN_SHIFT)),
+
+        ((CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_OVRRIDE_DISABLE <<
+          CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_OVRRIDE_SHIFT) |
+         (CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_CLKEN_DISABLE <<
+          CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_CLKEN_SHIFT) |
+         (CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_RSTN_RESET_DISABLE <<
+          CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_RSTN_SHIFT)),
+
+        NVRM_VARIABLE_DIVIDER
+    },
+
+    {   /* PLLP3 - PLLP secondary output (overridden)  */
+        NvRmClockSource_PllP3,
+        NvRmClockSource_PllP0,
+        NvRmClockDivider_Fractional_2,
+
+        CLK_RST_CONTROLLER_PLLP_OUTB_0,
+        CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_RATIO_DEFAULT_MASK,
+        CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_RATIO_SHIFT,
+
+        CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_OVRRIDE_FIELD |
+         CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_CLKEN_FIELD |
+         CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_RSTN_FIELD,
+
+        ((CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_OVRRIDE_ENABLE <<
+          CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_OVRRIDE_SHIFT) |
+         (CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_CLKEN_ENABLE <<
+          CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_CLKEN_SHIFT) |
+         (CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_RSTN_RESET_DISABLE <<
+          CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_RSTN_SHIFT)),
+
+        ((CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_OVRRIDE_DISABLE <<
+          CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_OVRRIDE_SHIFT) |
+         (CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_CLKEN_DISABLE <<
+          CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_CLKEN_SHIFT) |
+         (CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_RSTN_RESET_DISABLE <<
+          CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_RSTN_SHIFT)),
+
+        NVRM_VARIABLE_DIVIDER
+    },
+
+    {   /* PLLP4 - PLLP secondary output (overridden) */
+        NvRmClockSource_PllP4,
+        NvRmClockSource_PllP0,
+        NvRmClockDivider_Fractional_2,
+
+        CLK_RST_CONTROLLER_PLLP_OUTB_0,
+        CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_RATIO_DEFAULT_MASK,
+        CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_RATIO_SHIFT,
+
+        CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_OVRRIDE_FIELD |
+         CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_CLKEN_FIELD |
+         CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_RSTN_FIELD,
+
+        ((CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_OVRRIDE_ENABLE <<
+          CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_OVRRIDE_SHIFT) |
+         (CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_CLKEN_ENABLE <<
+          CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_CLKEN_SHIFT) |
+         (CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_RSTN_RESET_DISABLE <<
+          CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_RSTN_SHIFT)),
+
+        ((CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_OVRRIDE_DISABLE <<
+          CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_OVRRIDE_SHIFT) |
+         (CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_CLKEN_DISABLE <<
+          CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_CLKEN_SHIFT) |
+         (CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_RSTN_RESET_DISABLE <<
+          CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_RSTN_SHIFT)),
+
+        NVRM_VARIABLE_DIVIDER
+    },
+
+    {   /* AHB bus clock divider */
+        NvRmClockSource_Ahb,
+        NvRmClockSource_SystemBus,
+        NvRmClockDivider_Integer_1,
+
+        CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0,
+        CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_AHB_RATE_DEFAULT_MASK,
+        CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_AHB_RATE_SHIFT,
+
+        CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_HCLK_DIS_FIELD,
+        (0x0 << CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_HCLK_DIS_SHIFT),
+        (0x1 << CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_HCLK_DIS_SHIFT),
+         NVRM_VARIABLE_DIVIDER
+    },
+
+    {   /* APB bus clock divider */
+        NvRmClockSource_Apb,
+        NvRmClockSource_Ahb,
+        NvRmClockDivider_Integer_1,
+
+        CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0,
+        CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_APB_RATE_DEFAULT_MASK,
+        CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_APB_RATE_SHIFT,
+
+        CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_PCLK_DIS_FIELD,
+        (0x0 << CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_PCLK_DIS_SHIFT),
+        (0x1 << CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_PCLK_DIS_SHIFT),
+        NVRM_VARIABLE_DIVIDER
+    },
+
+    {   /* CPU bridge clock divider */
+        NvRmClockSource_CpuBridge,
+        NvRmClockSource_CpuBus,
+        NvRmClockDivider_Integer_1,
+
+        CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0,
+        CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0_CPU_BRIDGE_CLKDIV_DEFAULT_MASK,
+        CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0_CPU_BRIDGE_CLKDIV_SHIFT,
+        0, 0, 0,
+
+        NVRM_VARIABLE_DIVIDER
+    },
+
+    // TODO: PLL ref divider, CLK_M input divider
+};
+
+static const NvU32 s_Ap20DividerClockTableSize = NV_ARRAY_SIZE(s_Ap20DividerClockTable);
+
+/*****************************************************************************/
+
+static const NvRmCoreClockInfo s_Ap20CoreClockTable[] =
+{
+    {
+        NvRmClockSource_CpuBus,
+        {
+            NvRmClockSource_ClkM,
+            NvRmClockSource_PllC0,
+            NvRmClockSource_ClkS,
+            NvRmClockSource_PllM0,
+            NvRmClockSource_PllP0,
+            NvRmClockSource_PllP4,
+            NvRmClockSource_PllP3,
+            NvRmClockSource_ClkD,
+            NvRmClockSource_PllX0
+        },
+
+        CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0,
+        CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_STATE_DEFAULT_MASK,
+        CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_STATE_SHIFT,
+        {
+            0,
+            CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IDLE_SOURCE_DEFAULT_MASK,
+            CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_RUN_SOURCE_DEFAULT_MASK,
+            CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IRQ_SOURCE_DEFAULT_MASK,
+            CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_FIQ_SOURCE_DEFAULT_MASK
+
+        },
+        {
+            0,
+            CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IDLE_SOURCE_SHIFT,
+            CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_RUN_SOURCE_SHIFT,
+            CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IRQ_SOURCE_SHIFT,
+            CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_FIQ_SOURCE_SHIFT
+        },
+
+        CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0,
+        CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_ENB_DEFAULT_MASK,
+        CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_ENB_SHIFT,
+        CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIVIDEND_DEFAULT_MASK,
+        CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIVIDEND_SHIFT,
+        NV_FIELD_SIZE(CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIVIDEND_RANGE),
+        CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIVISOR_DEFAULT_MASK,
+        CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIVISOR_SHIFT,
+        NV_FIELD_SIZE(CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIVISOR_RANGE)
+    },
+    {
+        NvRmClockSource_SystemBus,
+        {
+            NvRmClockSource_ClkM,
+            NvRmClockSource_PllC1,
+            NvRmClockSource_PllP4,
+            NvRmClockSource_PllP3,
+            NvRmClockSource_PllP2,
+            NvRmClockSource_ClkD,
+            NvRmClockSource_ClkS,
+            NvRmClockSource_PllM1,
+        },
+
+        CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0,
+        CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SYS_STATE_DEFAULT_MASK,
+        CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SYS_STATE_SHIFT,
+        {
+            0,
+            CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IDLE_SOURCE_DEFAULT_MASK,
+            CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_RUN_SOURCE_DEFAULT_MASK,
+            CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IRQ_SOURCE_DEFAULT_MASK,
+            CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_FIQ_SOURCE_DEFAULT_MASK
+
+        },
+        {
+            0,
+            CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IDLE_SOURCE_SHIFT,
+            CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_RUN_SOURCE_SHIFT,
+            CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IRQ_SOURCE_SHIFT,
+            CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_FIQ_SOURCE_SHIFT
+        },
+
+        CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0,
+        CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_ENB_DEFAULT_MASK,
+        CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_ENB_SHIFT,
+        CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIVIDEND_DEFAULT_MASK,
+        CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIVIDEND_SHIFT,
+        NV_FIELD_SIZE(CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIVIDEND_RANGE),
+        CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIVISOR_DEFAULT_MASK,
+        CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIVISOR_SHIFT,
+        NV_FIELD_SIZE(CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIVISOR_RANGE)
+    }
+};
+
+static const NvU32 s_Ap20CoreClockTableSize = NV_ARRAY_SIZE(s_Ap20CoreClockTable);
+
+/*****************************************************************************/
+
+static const NvRmSelectorClockInfo s_Ap20SelectorClockTable[] =
+{
+    {
+        NvRmClockSource_AudioSync,
+        {
+            NvRmClockSource_ExtSpdf,
+            NvRmClockSource_ExtI2s1,
+            NvRmClockSource_ExtI2s2,
+            NvRmClockSource_ExtAc97,
+            NvRmClockSource_PllA0,
+            NvRmClockSource_ExtAudio2,
+            NvRmClockSource_ExtAudio1,
+            NvRmClockSource_ExtVi
+        },
+        CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_RATE_0,
+
+        CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_RATE_0_SYNC_CLK_RATE_DEFAULT_MASK,
+        CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_RATE_0_SYNC_CLK_RATE_SHIFT,
+
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0,
+        CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_SYNC_CLK_DOUBLER_ENB_FIELD
+    },
+};
+
+static const NvU32 s_Ap20SelectorClockTableSize = NV_ARRAY_SIZE(s_Ap20SelectorClockTable);
+
+/*****************************************************************************/
+/*****************************************************************************/
+
+static NvRmClockSourceInfo s_Ap20ClockSourceTable[NvRmClockSource_Num] = {{0}};
+
+NvRmClockSourceInfo* NvRmPrivAp20ClockSourceTableInit(void)
+{
+    NvRmClockSourceInfoPtr Src;
+
+#define PARSE_SOURCE_TABLE(type) \
+do\
+{\
+    Src.p##type = (NvRm##type##ClockInfo*)s_Ap20##type##ClockTable;\
+    NvRmPrivParseClockSources( \
+        s_Ap20ClockSourceTable, NvRmClockSource_Num, \
+        Src, s_Ap20##type##ClockTableSize, NvRmClockSourceType_##type); \
+} while(0)
+
+        NvOsMemset(s_Ap20ClockSourceTable, 0, sizeof(s_Ap20ClockSourceTable));
+
+        PARSE_SOURCE_TABLE(Fixed);
+        PARSE_SOURCE_TABLE(Pll);
+        PARSE_SOURCE_TABLE(Divider);
+        PARSE_SOURCE_TABLE(Core);
+        PARSE_SOURCE_TABLE(Selector);
+
+#undef PARSE_SOURCE_TABLE
+
+        return &s_Ap20ClockSourceTable[0];
+}
+
+/*****************************************************************************/
+
+static NvBool s_Ap20PllM0Clocks[NV_ARRAY_SIZE(g_Ap20ModuleClockTable)] = {0};
+static NvBool s_Ap20PllC0Clocks[NV_ARRAY_SIZE(g_Ap20ModuleClockTable)] = {0};
+static NvBool s_Ap20PllP0Clocks[NV_ARRAY_SIZE(g_Ap20ModuleClockTable)] = {0};
+static NvBool s_Ap20PllA0Clocks[NV_ARRAY_SIZE(g_Ap20ModuleClockTable)] = {0};
+static NvBool s_Ap20PllD0Clocks[NV_ARRAY_SIZE(g_Ap20ModuleClockTable)] = {0};
+static NvBool s_Ap20PllX0Clocks[NV_ARRAY_SIZE(g_Ap20ModuleClockTable)] = {0};
+
+static NvRmPllReference s_Ap20PllReferencesTable[] = 
+{
+    { NvRmClockSource_PllM0, NvRmDfsStatusFlags_StopPllM0, 0, s_Ap20PllM0Clocks, 0 },
+    { NvRmClockSource_PllC0, NvRmDfsStatusFlags_StopPllC0, 0, s_Ap20PllC0Clocks, 0 },
+    { NvRmClockSource_PllP0, NvRmDfsStatusFlags_StopPllP0, 0, s_Ap20PllP0Clocks, 0 },
+    { NvRmClockSource_PllA0, NvRmDfsStatusFlags_StopPllA0, 0, s_Ap20PllA0Clocks, 0 },
+    { NvRmClockSource_PllD0, NvRmDfsStatusFlags_StopPllD0, 0, s_Ap20PllD0Clocks, 0 },
+    { NvRmClockSource_PllX0, NvRmDfsStatusFlags_StopPllX0, 0, s_Ap20PllX0Clocks, 0 },
+};
+static const NvU32 s_Ap20PllReferencesTableSize =
+    NV_ARRAY_SIZE(s_Ap20PllReferencesTable);
+
+void
+NvRmPrivAp20PllReferenceTableInit(
+    NvRmPllReference** pPllReferencesTable,
+    NvU32* pPllReferencesTableSize)
+{
+    NvU32 i;
+    for (i = 0; i < s_Ap20PllReferencesTableSize; i++)
+    {
+        NvOsMemset(s_Ap20PllReferencesTable[i].AttachedModules, 0,
+                   sizeof(NvBool) * g_Ap20ModuleClockTableSize);
+        s_Ap20PllReferencesTable[i].ReferenceCnt = 0;
+        s_Ap20PllReferencesTable[i].ExternalClockRefCnt = 0;
+    }
+    *pPllReferencesTable = s_Ap20PllReferencesTable;
+    *pPllReferencesTableSize = s_Ap20PllReferencesTableSize;
+}
+
+/*****************************************************************************/
+
+// Power Gating Ids for each Power Group specified in re-location table header
+static const NvU32 s_Ap20PowerGroupIds[] = { NV_POWERGROUP_ENUM_TABLE };
+
+void
+NvRmPrivAp20PowerGroupTableInit(
+    const NvU32** pPowerGroupIdsTable,
+    NvU32* pPowerGroupIdsTableSize)
+{
+    *pPowerGroupIdsTable = s_Ap20PowerGroupIds;
+    *pPowerGroupIdsTableSize = NV_ARRAY_SIZE(s_Ap20PowerGroupIds);
+}
+
+/*****************************************************************************/
+
diff --git a/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_fuse.c b/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_fuse.c
new file mode 100644
index 000000000000..a609581c87b0
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_fuse.c
@@ -0,0 +1,78 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/** @file
+ * @brief <b>NVIDIA Driver Development Kit: Fuse API</b>
+ *
+ * @b Description: Contains the NvRM chip unique id implementation.
+ */
+#include "nvassert.h"
+#include "nvrm_drf.h"
+#include "nvos.h"
+#include "nvrm_module.h"
+#include "nvrm_hardware_access.h"
+#include "nvrm_hwintf.h"
+#include "ap20/arclk_rst.h"
+#include "ap20/arfuse.h"
+#include "ap20/ap20rm_misc_private.h"
+#include "ap20rm_clocks.h"
+
+NvError NvRmPrivAp20ChipUniqueId(NvRmDeviceHandle hDevHandle,void* pId)
+{
+    NvU64*  pOut = (NvU64*)pId; // Pointer to output buffer
+    NvU32   OldRegData;                // Old register contents
+    NvU32   NewRegData;                // New register contents
+
+    NV_ASSERT(hDevHandle);
+    NV_ASSERT(pId);
+#if NV_USE_FUSE_CLOCK_ENABLE
+    // Enable fuse clock
+    Ap20EnableModuleClock(hDevHandle, NvRmModuleID_Fuse, NV_TRUE);
+#endif
+    // Access to unique id is protected, so make sure all registers visible first.
+    OldRegData = NV_REGR(hDevHandle, NvRmPrivModuleID_ClockAndReset, 0, CLK_RST_CONTROLLER_MISC_CLK_ENB_0);
+    NewRegData = NV_FLD_SET_DRF_NUM(CLK_RST_CONTROLLER, MISC_CLK_ENB, CFG_ALL_VISIBLE, 1, OldRegData);
+    NV_REGW(hDevHandle, NvRmPrivModuleID_ClockAndReset, 0, CLK_RST_CONTROLLER_MISC_CLK_ENB_0, NewRegData);
+
+    // Read the secure id from the fuse registers and copy to the output buffer.
+    *pOut = ((NvU64)NV_REGR(hDevHandle, (NvRmPrivModuleID)NvRmModuleID_Fuse, 0, FUSE_JTAG_SECUREID_0_0)) |
+            (((NvU64)NV_REGR(hDevHandle, (NvRmPrivModuleID)NvRmModuleID_Fuse, 0, FUSE_JTAG_SECUREID_1_0)) << 32);
+
+    // Restore the protected registers enable to the way we found it.
+    NV_REGW(hDevHandle, NvRmPrivModuleID_ClockAndReset, 0, CLK_RST_CONTROLLER_MISC_CLK_ENB_0, OldRegData);
+#if NV_USE_FUSE_CLOCK_ENABLE
+    // Disable fuse clock
+    Ap20EnableModuleClock(hDevHandle, NvRmModuleID_Fuse, NV_FALSE);
+#endif
+    return NvError_Success;
+}
+
diff --git a/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_memctrl.c b/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_memctrl.c
new file mode 100644
index 000000000000..d589049ed4b4
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_memctrl.c
@@ -0,0 +1,275 @@
+/*
+ * Copyright (c) 2008-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include "nvrm_init.h"
+#include "nvassert.h"
+#include "nvos.h"
+#include "nvrm_module.h"
+#include "ap20/armc.h"
+#include "ap20/aremc.h"
+#include "ap20/arahb_arbc.h"
+#include "nvrm_drf.h"
+#include "nvrm_hwintf.h"
+#include "nvrm_structure.h"
+
+NvError NvRmPrivAp20McErrorMonitorStart(NvRmDeviceHandle hRm);
+void NvRmPrivAp20McErrorMonitorStop(NvRmDeviceHandle hRm);
+void NvRmPrivAp20SetupMc(NvRmDeviceHandle hRm);
+static void McErrorIntHandler(void* args);
+static NvOsInterruptHandle s_McInterruptHandle = NULL;
+
+void
+McStatAp20_Start(
+        NvRmDeviceHandle rm,
+        NvU32 client_id_0,
+        NvU32 client_id_1,
+        NvU32 llc_client_id);
+void
+McStatAp20_Stop(
+        NvRmDeviceHandle rm,
+        NvU32 *client_0_cycles,
+        NvU32 *client_1_cycles,
+        NvU32 *llc_client_cycles,
+        NvU32 *llc_client_clocks,
+        NvU32 *mc_clocks);
+
+void McErrorIntHandler(void* args)
+{
+    NvU32 RegVal;
+    NvU32 IntStatus;
+    NvU32 IntClear = 0;
+    NvRmDeviceHandle hRm = (NvRmDeviceHandle)args;
+    
+    IntStatus = NV_REGR(hRm, NvRmPrivModuleID_MemoryController, 0, MC_INTSTATUS_0);
+    if ( NV_DRF_VAL(MC, INTSTATUS, SECURITY_VIOLATION_INT, IntStatus) )
+    {
+        IntClear |= NV_DRF_DEF(MC, INTSTATUS, SECURITY_VIOLATION_INT, SET);
+        RegVal = NV_REGR(hRm, NvRmPrivModuleID_MemoryController, 0, 
+                     MC_SECURITY_VIOLATION_ADR_0);
+        NvOsDebugPrintf("SECURITY_VIOLATION DecErrAddress=0x%x ", RegVal);
+        RegVal = NV_REGR(hRm, NvRmPrivModuleID_MemoryController, 0, 
+                     MC_SECURITY_VIOLATION_STATUS_0);
+        NvOsDebugPrintf("SECURITY_VIOLATION DecErrStatus=0x%x ", RegVal);
+    }
+    if ( NV_DRF_VAL(MC, INTSTATUS, DECERR_EMEM_OTHERS_INT, IntStatus) )
+    {
+        IntClear |= NV_DRF_DEF(MC, INTSTATUS, DECERR_EMEM_OTHERS_INT, SET);
+        RegVal = NV_REGR(hRm, NvRmPrivModuleID_MemoryController, 0, 
+                     MC_DECERR_EMEM_OTHERS_ADR_0);
+        NvOsDebugPrintf("EMEM DecErrAddress=0x%x ", RegVal);
+        RegVal = NV_REGR(hRm, NvRmPrivModuleID_MemoryController, 0, 
+                     MC_DECERR_EMEM_OTHERS_STATUS_0);
+        NvOsDebugPrintf("EMEM DecErrStatus=0x%x ", RegVal);
+    }
+    if ( NV_DRF_VAL(MC, INTSTATUS, INVALID_GART_PAGE_INT, IntStatus) )
+    {
+        IntClear |= NV_DRF_DEF(MC, INTSTATUS, INVALID_GART_PAGE_INT, SET);
+        RegVal = NV_REGR(hRm, NvRmPrivModuleID_MemoryController, 0, 
+                     MC_GART_ERROR_ADDR_0);
+        NvOsDebugPrintf("GART DecErrAddress=0x%x ", RegVal);
+        RegVal = NV_REGR(hRm, NvRmPrivModuleID_MemoryController, 0, 
+                     MC_GART_ERROR_REQ_0);
+        NvOsDebugPrintf("GART DecErrStatus=0x%x ", RegVal);
+    }
+    
+    NV_ASSERT(!"MC Decode Error ");
+    // Clear the interrupt.
+    NV_REGW(hRm, NvRmPrivModuleID_MemoryController, 0, MC_INTSTATUS_0, IntClear);
+    NvRmInterruptDone(s_McInterruptHandle);
+}
+
+NvError NvRmPrivAp20McErrorMonitorStart(NvRmDeviceHandle hRm)
+{
+    NvU32 val;
+    NvU32 IrqList;
+    NvError e = NvSuccess;
+    NvOsInterruptHandler handler;
+    
+    if (s_McInterruptHandle == NULL)
+    {
+        // Install an interrupt handler.
+        handler = McErrorIntHandler;
+        IrqList = NvRmGetIrqForLogicalInterrupt(hRm,
+                      NvRmPrivModuleID_MemoryController, 0);
+        NV_CHECK_ERROR( NvRmInterruptRegister(hRm, 1, &IrqList,  &handler, 
+            hRm, &s_McInterruptHandle, NV_TRUE) );
+        // Enable Dec Err interrupts in memory Controller.
+        val = NV_DRF_DEF(MC, INTMASK, SECURITY_VIOLATION_INTMASK, UNMASKED) |
+              NV_DRF_DEF(MC, INTMASK, DECERR_EMEM_OTHERS_INTMASK, UNMASKED) |
+              NV_DRF_DEF(MC, INTMASK, INVALID_GART_PAGE_INTMASK, UNMASKED);
+        NV_REGW(hRm, NvRmPrivModuleID_MemoryController, 0, MC_INTMASK_0, val);
+    }
+    return e;
+}
+
+void NvRmPrivAp20McErrorMonitorStop(NvRmDeviceHandle hRm)
+{
+    NvRmInterruptUnregister(hRm, s_McInterruptHandle);
+    s_McInterruptHandle = NULL;
+}
+
+/* This function sets some performance timings for Mc & Emc.  Numbers are from
+ * the Arch team.
+ *
+ */
+void NvRmPrivAp20SetupMc(NvRmDeviceHandle hRm)
+{
+    NvU32   reg, mask;
+    reg = NV_REGR(hRm, NvRmPrivModuleID_MemoryController, 0, 
+              MC_LOWLATENCY_CONFIG_0);
+    mask = NV_DRF_DEF(MC, LOWLATENCY_CONFIG, MPCORER_LL_CTRL, ENABLE) |
+           NV_DRF_DEF(MC, LOWLATENCY_CONFIG, MPCORER_LL_SEND_BOTH, ENABLE);
+    if ( mask != (reg & mask) )
+        NV_ASSERT(!"MC LL Path not enabled!");
+    // For AP20, no need to program any MC timeout registers here. Default 
+    // values should be good enough.
+}
+
+
+
+void
+McStatAp20_Start(
+        NvRmDeviceHandle rm,
+        NvU32 client_id_0,
+        NvU32 client_id_1,
+        NvU32 llc_client_id)
+{
+    NvU32 emc_ctrl =
+      (AREMC_STAT_CONTROL_MODE_BANDWIDTH << AREMC_STAT_CONTROL_MODE_SHIFT) |
+      (AREMC_STAT_CONTROL_EVENT_QUALIFIED << AREMC_STAT_CONTROL_EVENT_SHIFT) |
+      (AREMC_STAT_CONTROL_CLIENT_TYPE_MPCORER <<
+         AREMC_STAT_CONTROL_CLIENT_TYPE_SHIFT) |  // default is MPCORE Read client
+      (AREMC_STAT_CONTROL_FILTER_CLIENT_ENABLE <<
+         AREMC_STAT_CONTROL_FILTER_CLIENT_SHIFT) |
+      (AREMC_STAT_CONTROL_FILTER_ADDR_DISABLE <<
+         AREMC_STAT_CONTROL_FILTER_ADDR_SHIFT);
+
+    NvU32 mc_filter_client_0 = (ARMC_STAT_CONTROL_FILTER_CLIENT_ENABLE <<
+                   ARMC_STAT_CONTROL_FILTER_CLIENT_SHIFT);
+
+    NvU32 mc_filter_client_1 = (ARMC_STAT_CONTROL_FILTER_CLIENT_ENABLE <<
+                   ARMC_STAT_CONTROL_FILTER_CLIENT_SHIFT);
+
+    if (client_id_0 == 0xffffffff)
+    {
+        mc_filter_client_0 = (ARMC_STAT_CONTROL_FILTER_CLIENT_DISABLE <<
+                   ARMC_STAT_CONTROL_FILTER_CLIENT_SHIFT);
+        client_id_0 = 0;
+    }
+
+    if (client_id_1 == 0xffffffff)
+    {
+        mc_filter_client_1 = (ARMC_STAT_CONTROL_FILTER_CLIENT_DISABLE <<
+                   ARMC_STAT_CONTROL_FILTER_CLIENT_SHIFT);
+        client_id_1 = 0;
+    }
+
+    if(llc_client_id == 1)
+        emc_ctrl |= AREMC_STAT_CONTROL_CLIENT_TYPE_MPCORER <<
+                    AREMC_STAT_CONTROL_CLIENT_TYPE_SHIFT;
+                    // overwrite with MPCore read
+        NV_REGW(rm, NvRmPrivModuleID_ExternalMemoryController,
+                0, EMC_STAT_CONTROL_0,
+                NV_DRF_DEF(EMC, STAT_CONTROL, LLMC_GATHER,DISABLE));
+        NV_REGW(rm, NvRmPrivModuleID_ExternalMemoryController,
+                0, EMC_STAT_LLMC_CLOCK_LIMIT_0, 0xffffffff);
+        NV_REGW(rm, NvRmPrivModuleID_ExternalMemoryController,
+                0, EMC_STAT_LLMC_CONTROL_0_0, emc_ctrl);
+        NV_REGW(rm, NvRmPrivModuleID_ExternalMemoryController,
+                0, EMC_STAT_CONTROL_0,
+                NV_DRF_DEF(EMC, STAT_CONTROL, LLMC_GATHER, CLEAR));
+        NV_REGW(rm, NvRmPrivModuleID_ExternalMemoryController,
+                0, EMC_STAT_CONTROL_0,
+                NV_DRF_DEF(EMC, STAT_CONTROL, LLMC_GATHER, ENABLE));
+        NV_REGW(rm, NvRmPrivModuleID_MemoryController,
+                0, MC_STAT_CONTROL_0,
+                NV_DRF_DEF(MC, STAT_CONTROL, EMC_GATHER, DISABLE));
+        NV_REGW(rm, NvRmPrivModuleID_MemoryController,
+                0, MC_STAT_EMC_CLOCK_LIMIT_0, 0xffffffff);
+        NV_REGW(rm, NvRmPrivModuleID_MemoryController,
+                0, MC_STAT_EMC_CONTROL_0_0,
+                (ARMC_STAT_CONTROL_MODE_BANDWIDTH <<
+                   ARMC_STAT_CONTROL_MODE_SHIFT) |
+                (client_id_0 << ARMC_STAT_CONTROL_CLIENT_ID_SHIFT) |
+                (ARMC_STAT_CONTROL_EVENT_QUALIFIED <<
+                   ARMC_STAT_CONTROL_EVENT_SHIFT) |
+                mc_filter_client_0 |
+                (ARMC_STAT_CONTROL_FILTER_ADDR_DISABLE <<
+                   ARMC_STAT_CONTROL_FILTER_ADDR_SHIFT) |
+                (ARMC_STAT_CONTROL_FILTER_PRI_DISABLE <<
+                   ARMC_STAT_CONTROL_FILTER_PRI_SHIFT) |
+                (ARMC_STAT_CONTROL_FILTER_COALESCED_DISABLE <<
+                   ARMC_STAT_CONTROL_FILTER_COALESCED_SHIFT));
+        NV_REGW(rm, NvRmPrivModuleID_MemoryController,
+                0, MC_STAT_EMC_CONTROL_1_0,
+                (ARMC_STAT_CONTROL_MODE_BANDWIDTH <<
+                   ARMC_STAT_CONTROL_MODE_SHIFT) |
+                (client_id_1 << ARMC_STAT_CONTROL_CLIENT_ID_SHIFT) |
+                (ARMC_STAT_CONTROL_EVENT_QUALIFIED <<
+                   ARMC_STAT_CONTROL_EVENT_SHIFT) |
+                mc_filter_client_1 |
+                (ARMC_STAT_CONTROL_FILTER_ADDR_DISABLE <<
+                   ARMC_STAT_CONTROL_FILTER_ADDR_SHIFT) |
+                (ARMC_STAT_CONTROL_FILTER_PRI_DISABLE <<
+                   ARMC_STAT_CONTROL_FILTER_PRI_SHIFT) |
+                (ARMC_STAT_CONTROL_FILTER_COALESCED_DISABLE <<
+                   ARMC_STAT_CONTROL_FILTER_COALESCED_SHIFT));
+
+        NV_REGW(rm, NvRmPrivModuleID_MemoryController,
+                0, MC_STAT_CONTROL_0,
+                NV_DRF_DEF(MC, STAT_CONTROL, EMC_GATHER, CLEAR));
+        NV_REGW(rm, NvRmPrivModuleID_MemoryController,
+                0, MC_STAT_CONTROL_0,
+                NV_DRF_DEF(MC, STAT_CONTROL, EMC_GATHER, ENABLE));
+}
+
+
+void
+McStatAp20_Stop(
+        NvRmDeviceHandle rm,
+        NvU32 *client_0_cycles,
+        NvU32 *client_1_cycles,
+        NvU32 *llc_client_cycles,
+        NvU32 *llc_client_clocks,
+        NvU32 *mc_clocks)
+{
+    *llc_client_cycles = NV_REGR(rm, NvRmPrivModuleID_ExternalMemoryController,
+                           0, EMC_STAT_LLMC_COUNT_0_0);
+    *llc_client_clocks = NV_REGR(rm, NvRmPrivModuleID_ExternalMemoryController,
+                           0, EMC_STAT_LLMC_CLOCKS_0);
+    *client_0_cycles = NV_REGR(rm, NvRmPrivModuleID_MemoryController,
+                         0, MC_STAT_EMC_COUNT_0_0);
+    *client_1_cycles = NV_REGR(rm, NvRmPrivModuleID_MemoryController,
+                         0, MC_STAT_EMC_COUNT_1_0);
+    *mc_clocks = NV_REGR(rm, NvRmPrivModuleID_MemoryController,
+                   0, MC_STAT_EMC_CLOCKS_0);
+}
diff --git a/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_misc_private.h b/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_misc_private.h
new file mode 100644
index 000000000000..9d790ef85e0f
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_misc_private.h
@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2008-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef AP20RM_MISC_PRIVATE_H
+#define AP20RM_MISC_PRIVATE_H
+
+/*
+ * ap20rm_misc_private.h defines the miscellenious private implementation functions for the resource
+ * manager for ap20 chip.
+ */
+
+#include "nvcommon.h"
+#include "nvos.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif  /* __cplusplus */
+
+
+/**
+ * Chip unque id for AP15 and ap16.
+ */
+NvError
+NvRmPrivAp20ChipUniqueId(
+    NvRmDeviceHandle hDevHandle,
+    void* pId);
+
+
+#ifdef __cplusplus
+}
+#endif  /* __cplusplus */
+
+#endif // AP20RM_MISC_PRIVATE_H
diff --git a/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_pinmux_tables.c b/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_pinmux_tables.c
new file mode 100644
index 000000000000..145a36e50fac
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_pinmux_tables.c
@@ -0,0 +1,328 @@
+/*
+ * Copyright (c) 2008-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include "nvcommon.h"
+#include "nvrm_pinmux.h"
+#include "nvrm_drf.h"
+#include "nvassert.h"
+#include "nvrm_hwintf.h"
+#include "ap20/arapb_misc.h"
+#include "ap20/arclk_rst.h"
+#include "ap15/ap15rm_pinmux_utils.h"
+#include "nvrm_clocks.h"
+#include "nvodm_query_pinmux.h"
+
+NvU32
+NvRmPrivAp20GetExternalClockSourceFreq(
+    NvRmDeviceHandle hDevice,
+    struct tegra_pingroup_config *pin_config,
+    int len)
+{
+	NvU32 ClockFreqInKHz = 0;
+	if (len != 1)
+		return 0;
+
+	switch(pin_config[0].pingroup) {
+	case TEGRA_PINGROUP_CDEV1:
+		if (pin_config[0].func == TEGRA_MUX_PLLA_OUT)
+		    ClockFreqInKHz = NvRmPrivGetClockSourceFreq(NvRmClockSource_PllA0);
+		else if (pin_config[0].func == TEGRA_MUX_OSC)
+		    ClockFreqInKHz = NvRmPrivGetClockSourceFreq(NvRmClockSource_ClkM);
+		break;
+
+	case TEGRA_PINGROUP_CDEV2:
+		if (pin_config[0].func == TEGRA_MUX_AHB_CLK)
+		    ClockFreqInKHz = NvRmPrivGetClockSourceFreq(NvRmClockSource_Ahb);
+		else if (pin_config[0].func == TEGRA_MUX_OSC)
+		    ClockFreqInKHz = NvRmPrivGetClockSourceFreq(NvRmClockSource_ClkM);
+		else if (pin_config[0].func == TEGRA_MUX_PLLP_OUT4)
+		    ClockFreqInKHz = NvRmPrivGetClockSourceFreq(NvRmClockSource_PllP4);
+		break;
+
+	case TEGRA_PINGROUP_CSUS:
+		if (pin_config[0].func == TEGRA_MUX_VI_SENSOR_CLK)
+		{
+		    if (NvRmPowerModuleClockConfig(hDevice, NvRmModuleID_Vi, 0, 0, 0,
+			NULL, 0, &ClockFreqInKHz, NvRmClockConfig_SubConfig) != NvSuccess)
+		    {
+			ClockFreqInKHz = 0;
+		    }
+		}
+		break;
+	default:
+		ClockFreqInKHz = 0;
+		break;
+    }
+
+    return ClockFreqInKHz;
+}
+
+void NvRmPrivAp20EnableExternalClockSource(
+    NvRmDeviceHandle hDevice,
+    struct tegra_pingroup_config *pin_config,
+    int len,
+    NvBool ClockState)
+{
+    NvU32 ClkEnbShift = ~0;
+
+    if (len != 1)
+	    return;
+
+    switch(pin_config[0].pingroup) {
+    case TEGRA_PINGROUP_CDEV1:
+	    ClkEnbShift = CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_DEV1_OUT_SHIFT;
+	    if (pin_config[0].func == TEGRA_MUX_PLLA_OUT) {
+		    NvRmPrivExternalClockAttach(
+			hDevice, NvRmClockSource_PllA0, ClockState);
+	    }
+	    break;
+
+     case TEGRA_PINGROUP_CDEV2:
+	     ClkEnbShift = CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_DEV2_OUT_SHIFT;
+	     if (pin_config[0].func == TEGRA_MUX_PLLP_OUT4)
+	     {
+		 NvRmPrivExternalClockAttach(
+		     hDevice, NvRmClockSource_PllP4, ClockState);
+	     }
+	     break;
+
+    case TEGRA_PINGROUP_CSUS:
+	    ClkEnbShift = CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_SUS_OUT_SHIFT;
+	    break;
+    default:
+	return;
+    }
+    if (ClockState)
+    {
+        NV_REGW(hDevice, NvRmPrivModuleID_ClockAndReset, 0,
+                CLK_RST_CONTROLLER_CLK_ENB_U_SET_0, (1UL<<ClkEnbShift));
+    }
+    else
+    {
+        NV_REGW(hDevice, NvRmPrivModuleID_ClockAndReset, 0,
+                CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0, (1UL<<ClkEnbShift));
+    }
+}
+
+NvBool NvRmPrivAp20RmModuleToOdmModule(
+    NvRmModuleID RmModule,
+    NvOdmIoModule *OdmModule,
+    NvU32 *OdmInstance,
+    NvU32 *pCnt)
+{
+    NvRmModuleID Module = NVRM_MODULE_ID_MODULE(RmModule);
+    NvU32 Instance = NVRM_MODULE_ID_INSTANCE(RmModule);
+    NvBool Success = NV_TRUE;
+    *pCnt = 1;
+    switch (Module)
+    {
+    case NvRmModuleID_Usb2Otg:
+        switch (Instance)
+        {
+        case 0:
+            *OdmModule = NvOdmIoModule_Usb;
+            *OdmInstance = 0;
+            break;
+        case 1:
+            *OdmModule = NvOdmIoModule_Ulpi;
+            *OdmInstance = 0;
+            break;
+        case 2:
+            *OdmModule = NvOdmIoModule_Usb;
+            *OdmInstance = 1;
+            break;
+        default:
+            NV_ASSERT(!"Invalid USB instance");
+            break;
+        }
+        break;
+    case NvRmModuleID_OneWire:
+        *OdmModule = NvOdmIoModule_OneWire;
+        *OdmInstance = Instance;
+        break;
+    case NvRmModuleID_SyncNor:
+        *OdmModule = NvOdmIoModule_SyncNor;
+        *OdmInstance = Instance;
+        break;
+    case NvRmPrivModuleID_Pcie:
+        *OdmModule = NvOdmIoModule_PciExpress;
+        *OdmInstance = Instance;
+        break;
+    default:
+        Success = NV_FALSE;
+        *pCnt = 0;
+        break;
+    }
+    return  Success;
+}
+
+NvError
+NvRmPrivAp20GetModuleInterfaceCaps(
+    NvOdmIoModule Module,
+    NvU32 Instance,
+    NvU32 PinMap,
+    void *pCaps)
+{
+    switch (Module)
+    {
+    case NvOdmIoModule_Sdio:
+        if (Instance == 1)
+        {
+            if (PinMap == NvOdmSdioPinMap_Config2 || PinMap == NvOdmSdioPinMap_Config4)
+                ((NvRmModuleSdmmcInterfaceCaps *)pCaps)->MmcInterfaceWidth = 8;
+            else if (PinMap == NvOdmSdioPinMap_Config1 ||
+            PinMap == NvOdmSdioPinMap_Config3 || PinMap == NvOdmSdioPinMap_Config5)
+                ((NvRmModuleSdmmcInterfaceCaps *)pCaps)->MmcInterfaceWidth = 4;
+            else
+            {
+                NV_ASSERT(NV_FALSE);
+                return NvError_NotSupported;
+            }
+        }
+        else if (Instance==2 && PinMap==NvOdmSdioPinMap_Config1)
+            ((NvRmModuleSdmmcInterfaceCaps *)pCaps)->MmcInterfaceWidth = 8;
+        else if (Instance==3 && (PinMap==NvOdmSdioPinMap_Config1 || PinMap==NvOdmSdioPinMap_Config2))
+            ((NvRmModuleSdmmcInterfaceCaps *)pCaps)->MmcInterfaceWidth = 8;
+        else
+            ((NvRmModuleSdmmcInterfaceCaps *)pCaps)->MmcInterfaceWidth = 4;
+        return NvError_Success;
+
+    case NvOdmIoModule_Pwm:
+        if (Instance == 0 && (PinMap == NvOdmPwmPinMap_Config1))
+            ((NvRmModulePwmInterfaceCaps *)pCaps)->PwmOutputIdSupported = 15;
+        else if (Instance == 0 && (PinMap == NvOdmPwmPinMap_Config2))
+            ((NvRmModulePwmInterfaceCaps *)pCaps)->PwmOutputIdSupported = 13;
+        else if (Instance == 0 && (PinMap == NvOdmPwmPinMap_Config3))
+            ((NvRmModulePwmInterfaceCaps *)pCaps)->PwmOutputIdSupported = 1;
+        else if (Instance == 0 && (PinMap == NvOdmPwmPinMap_Config4))
+            ((NvRmModulePwmInterfaceCaps *)pCaps)->PwmOutputIdSupported = 12;
+        else if (Instance == 0 && (PinMap == NvOdmPwmPinMap_Config5))
+            ((NvRmModulePwmInterfaceCaps *)pCaps)->PwmOutputIdSupported = 15;
+        else if (Instance == 0 && (PinMap == NvOdmPwmPinMap_Config6))
+            ((NvRmModulePwmInterfaceCaps *)pCaps)->PwmOutputIdSupported = 3;
+        else
+        {
+            ((NvRmModulePwmInterfaceCaps *)pCaps)->PwmOutputIdSupported = 0;
+            return NvError_NotSupported;
+        }
+        return NvError_Success;
+    case NvOdmIoModule_Nand:
+        if (Instance == 0 && (PinMap == NvOdmNandPinMap_Config1 || PinMap ==
+        NvOdmNandPinMap_Config3))
+        {
+            ((NvRmModuleNandInterfaceCaps*)pCaps)->IsCombRbsyMode = NV_TRUE;
+            ((NvRmModuleNandInterfaceCaps*)pCaps)->NandInterfaceWidth = 16;
+        }
+        else if (Instance == 0 && (PinMap == NvOdmNandPinMap_Config2 ||
+            PinMap == NvOdmNandPinMap_Config4))
+        {
+            ((NvRmModuleNandInterfaceCaps*)pCaps)->IsCombRbsyMode = NV_TRUE;
+            ((NvRmModuleNandInterfaceCaps*)pCaps)->NandInterfaceWidth = 8;
+        }
+        else
+        {
+            NV_ASSERT(NV_FALSE);
+            return NvError_NotSupported;
+        }
+        return NvSuccess;
+    case NvOdmIoModule_Uart:
+        if (Instance == 0)
+        {
+            if (PinMap == NvOdmUartPinMap_Config1)
+                ((NvRmModuleUartInterfaceCaps *)pCaps)->NumberOfInterfaceLines = 8;
+            else if (PinMap == NvOdmUartPinMap_Config2)
+                ((NvRmModuleUartInterfaceCaps *)pCaps)->NumberOfInterfaceLines = 7;
+            else if ((PinMap == NvOdmUartPinMap_Config3) || (PinMap == NvOdmUartPinMap_Config6))
+                ((NvRmModuleUartInterfaceCaps *)pCaps)->NumberOfInterfaceLines = 4;
+            else if ((PinMap == NvOdmUartPinMap_Config4) || (PinMap == NvOdmUartPinMap_Config5))
+                ((NvRmModuleUartInterfaceCaps *)pCaps)->NumberOfInterfaceLines = 2;
+            else if (PinMap == NvOdmUartPinMap_Config7)
+                ((NvRmModuleUartInterfaceCaps *)pCaps)->NumberOfInterfaceLines = 6;
+            else
+                ((NvRmModuleUartInterfaceCaps *)pCaps)->NumberOfInterfaceLines = 0;
+        }
+        else if ((Instance == 1) || (Instance == 2))
+        {
+            if (PinMap == NvOdmUartPinMap_Config1)
+                ((NvRmModuleUartInterfaceCaps *)pCaps)->NumberOfInterfaceLines = 4;
+            else if (PinMap == NvOdmUartPinMap_Config2)
+                ((NvRmModuleUartInterfaceCaps *)pCaps)->NumberOfInterfaceLines = 2;
+            else
+                ((NvRmModuleUartInterfaceCaps *)pCaps)->NumberOfInterfaceLines = 0;
+        }
+        else if ((Instance == 3) || (Instance == 4))
+        {
+            if ((PinMap == NvOdmUartPinMap_Config1) || (PinMap == NvOdmUartPinMap_Config2))
+                ((NvRmModuleUartInterfaceCaps *)pCaps)->NumberOfInterfaceLines = 4;
+            else
+                ((NvRmModuleUartInterfaceCaps *)pCaps)->NumberOfInterfaceLines = 0;
+        }
+        else
+        {
+            NV_ASSERT(NV_FALSE);
+            return NvError_NotSupported;
+        }
+        return NvSuccess;
+
+    default:
+        break;
+    }
+
+    return NvError_NotSupported;
+}
+
+NvError
+NvRmAp20GetStraps(
+    NvRmDeviceHandle hDevice,
+    NvRmStrapGroup StrapGroup,
+    NvU32* pStrapValue)
+{
+    NvU32 reg = NV_REGR(
+        hDevice, NvRmModuleID_Misc, 0, APB_MISC_PP_STRAPPING_OPT_A_0);
+
+    switch (StrapGroup)
+    {
+        case NvRmStrapGroup_RamCode:
+            reg = NV_DRF_VAL(APB_MISC_PP, STRAPPING_OPT_A, RAM_CODE, reg);
+            break;
+        default:
+            return NvError_NotSupported;
+    }
+    *pStrapValue = reg;
+    return NvSuccess;
+}
+
+void NvRmAp20SetDefaultTristate(NvRmDeviceHandle hDevice)
+{
+    tegra_pinmux_set_vddio_tristate(TEGRA_VDDIO_NAND, TEGRA_TRI_TRISTATE);
+}
+
diff --git a/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_power_dfs.c b/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_power_dfs.c
new file mode 100644
index 000000000000..a5ddb03870db
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_power_dfs.c
@@ -0,0 +1,454 @@
+/*
+ * Copyright (c) 2008-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include "ap20rm_power_dfs.h"
+#include "nvassert.h"
+#include "nvrm_drf.h"
+#include "nvrm_hwintf.h"
+#include "nvrm_pmu.h"
+#include "ap20/aremc.h"
+#include "ap20/arclk_rst.h"
+#include "ap20/arapb_misc.h"
+
+/*****************************************************************************/
+
+// Regsiter access macros for EMC module
+#define NV_EMC_REGR(pEmcRegs, reg) \
+            NV_READ32((((NvU32)(pEmcRegs)) + EMC_##reg##_0))
+#define NV_EMC_REGW(pEmcRegs, reg, val) \
+            NV_WRITE32((((NvU32)(pEmcRegs)) + EMC_##reg##_0), (val))
+
+// Regsiter access macros for APB MISC module
+#define NV_APB_REGR(pApbRegs, reg) \
+         NV_READ32((((NvU32)(pApbRegs)) + APB_MISC_##reg##_0))
+#define NV_APB_REGW(pApbRegs, reg, val) \
+         NV_WRITE32((((NvU32)(pApbRegs)) + APB_MISC_##reg##_0), (val))
+
+// TODO: Always Disable before check-in
+#define NVRM_TEST_PMREQUEST_UP_MODE (0)
+
+/*****************************************************************************/
+// EMC MODULE INTERFACES
+/*****************************************************************************/
+
+void NvRmPrivAp20EmcParametersAdjust(NvRmDfs* pDfs)
+{
+    NvRmDfsParam EmcParamDddr2 = { NVRM_DFS_PARAM_EMC_AP20_DDR2 };
+    NvRmDfsParam EmcParamLpDddr2 = { NVRM_DFS_PARAM_EMC_AP20_LPDDR2 };
+
+    NvU32 RegValue = NV_REGR(pDfs->hRm,
+        NvRmPrivModuleID_ExternalMemoryController, 0, EMC_FBIO_CFG5_0);
+
+    switch (NV_DRF_VAL(EMC, FBIO_CFG5, DRAM_TYPE, RegValue))
+    {
+        case EMC_FBIO_CFG5_0_DRAM_TYPE_LPDDR2:
+            pDfs->DfsParameters[NvRmDfsClockId_Emc] = EmcParamLpDddr2;
+            break;
+
+        case EMC_FBIO_CFG5_0_DRAM_TYPE_DDR2:
+            pDfs->DfsParameters[NvRmDfsClockId_Emc] = EmcParamDddr2;
+            break;
+
+        default:
+            NV_ASSERT(!"Not supported DRAM type");
+    }
+}
+
+NvError NvRmPrivAp20EmcMonitorsInit(NvRmDfs* pDfs)
+{
+    NvU32 RegValue;
+    void* pEmcRegs = pDfs->Modules[NvRmDfsModuleId_Emc].pBaseReg;
+    NV_ASSERT(pEmcRegs);
+
+    /*
+     * EMC power management monitor belongs to EMC module - just reset it,
+     * and do not touch anything else in EMC.
+     */ 
+    RegValue = NV_EMC_REGR(pEmcRegs, STAT_CONTROL);
+    RegValue = NV_FLD_SET_DRF_DEF(EMC, STAT_CONTROL, PWR_GATHER, RST, RegValue);
+    NV_EMC_REGW(pEmcRegs, STAT_CONTROL, RegValue);
+
+    /*
+    * EMC active clock cycles = EMC monitor reading * 2^M, where M depends
+    * on DRAM type and bus width. Power M is stored as EMC readouts scale
+    */
+    #define COUNT_SHIFT_DDR1_X32 (1)
+    RegValue = NV_EMC_REGR(pEmcRegs, FBIO_CFG5);
+    switch (NV_DRF_VAL(EMC, FBIO_CFG5, DRAM_TYPE, RegValue))
+    {
+        case EMC_FBIO_CFG5_0_DRAM_TYPE_DDR1:
+        case EMC_FBIO_CFG5_0_DRAM_TYPE_LPDDR2:
+        case EMC_FBIO_CFG5_0_DRAM_TYPE_DDR2:
+            pDfs->Modules[NvRmDfsModuleId_Emc].Scale = COUNT_SHIFT_DDR1_X32;
+            break;
+        default:
+            NV_ASSERT(!"Not supported DRAM type");
+    }
+    if (NV_DRF_VAL(EMC, FBIO_CFG5, DRAM_WIDTH, RegValue) ==
+        EMC_FBIO_CFG5_0_DRAM_WIDTH_X16)
+    {
+        pDfs->Modules[NvRmDfsModuleId_Emc].Scale++;
+    }
+    return NvSuccess;
+}
+
+void NvRmPrivAp20EmcMonitorsDeinit(NvRmDfs* pDfs)
+{
+     // Stop monitor using initialization procedure
+    (void)NvRmPrivAp20EmcMonitorsInit(pDfs);
+}
+
+void
+NvRmPrivAp20EmcMonitorsStart(
+    const NvRmDfs* pDfs,
+    const NvRmDfsFrequencies* pDfsKHz,
+    const NvU32 IntervalMs)
+{
+    NvU32 RegValue, SavedRegValue;
+    void* pEmcRegs = pDfs->Modules[NvRmDfsModuleId_Emc].pBaseReg;
+
+    // EMC sample period is specified in EMC clock cycles, accuracy 0-16 cycles.
+    #define MEAN_EMC_LIMIT_ERROR (8)
+    NvU32 cycles = IntervalMs * pDfsKHz->Domains[NvRmDfsClockId_Emc] +
+                    MEAN_EMC_LIMIT_ERROR;
+    /*
+     * Start EMC power monitor for the next sample period: clear EMC counters,
+     * set sample interval limit in EMC cycles, enable monitoring. Monitor is
+     * counting EMC 1x clock cycles while any memory access is detected. 
+     */
+    SavedRegValue = NV_EMC_REGR(pEmcRegs, STAT_CONTROL);
+    RegValue = NV_FLD_SET_DRF_DEF(EMC, STAT_CONTROL, PWR_GATHER, CLEAR, SavedRegValue);
+    NV_EMC_REGW(pEmcRegs, STAT_CONTROL, RegValue);
+
+    RegValue = NV_DRF_NUM(EMC, STAT_PWR_CLOCK_LIMIT, PWR_CLOCK_LIMIT, cycles);
+    NV_EMC_REGW(pEmcRegs, STAT_PWR_CLOCK_LIMIT, RegValue);
+
+    RegValue = NV_FLD_SET_DRF_DEF(EMC, STAT_CONTROL, PWR_GATHER, ENABLE, SavedRegValue);
+    NV_EMC_REGW(pEmcRegs, STAT_CONTROL, RegValue);
+}
+
+void
+NvRmPrivAp20EmcMonitorsRead(
+    const NvRmDfs* pDfs,
+    const NvRmDfsFrequencies* pDfsKHz,
+    NvRmDfsIdleData* pIdleData)
+{
+    NvU32 RegValue, TotalClocks;
+    NvU32 CountShift = pDfs->Modules[NvRmDfsModuleId_Emc].Scale;
+    void* pEmcRegs = pDfs->Modules[NvRmDfsModuleId_Emc].pBaseReg;
+
+    /*
+     * Read EMC monitor: disable it (=stop, the readings are preserved), and
+     * determine idle count based on total and active clock counts. Monitor
+     * readings are multiplied by 2^M factor to determine active count, where
+     * power M depends on DRAM type and bus width. Store result in the idle
+     * data packet.
+     */
+    RegValue = NV_EMC_REGR(pEmcRegs, STAT_CONTROL);
+    RegValue = NV_FLD_SET_DRF_DEF(EMC, STAT_CONTROL, PWR_GATHER, DISABLE, RegValue);
+    NV_EMC_REGW(pEmcRegs, STAT_CONTROL, RegValue);
+
+    RegValue = NV_EMC_REGR(pEmcRegs, STAT_PWR_CLOCKS);
+    TotalClocks = NV_DRF_VAL(EMC, STAT_PWR_CLOCKS, PWR_CLOCKS, RegValue);
+    RegValue = NV_EMC_REGR(pEmcRegs, STAT_PWR_COUNT);
+    RegValue = NV_DRF_VAL(EMC, STAT_PWR_COUNT, PWR_COUNT, RegValue) << CountShift;
+
+    pIdleData->Readings[NvRmDfsClockId_Emc] = 
+        (TotalClocks > RegValue) ? (TotalClocks - RegValue) : 0;
+}
+
+/*****************************************************************************/
+
+// AP20 Thermal policy definitions
+
+#define NVRM_DTT_DEGREES_HIGH           (85L)
+#define NVRM_DTT_DEGREES_LOW            (60L)
+#define NVRM_DTT_DEGREES_HYSTERESIS     (5L)
+
+#define NVRM_DTT_VOLTAGE_THROTTLE_MV    (900UL)
+#define NVRM_DTT_CPU_DELTA_KHZ          (100000UL)
+
+#define NVRM_DTT_POLL_MS_SLOW           (2000UL)
+#define NVRM_DTT_POLL_MS_FAST           (1000UL)
+#define NVRM_DTT_POLL_MS_CRITICAL       (500UL)
+
+typedef enum
+{
+    NvRmDttAp20PolicyRange_Unknown = 0,
+
+    // No throttling
+    NvRmDttAp20PolicyRange_FreeRunning,
+
+    // Keep CPU frequency below low voltage threshold
+    NvRmDttAp20PolicyRange_LimitVoltage,
+
+    // Decrease CPU frequency in steps over time
+    NvRmDttAp20PolicyRange_ThrottleDown,
+
+    NvRmDttAp20PolicyRange_Num,
+    NvRmDttAp20PolicyRange_Force32 = 0x7FFFFFFFUL
+} NvRmDttAp20PolicyRange;
+
+static NvRmFreqKHz s_CpuThrottleMaxKHz = 0;
+static NvRmFreqKHz s_CpuThrottleMinKHz = 0;
+static NvRmFreqKHz s_CpuThrottleKHz = 0;
+
+void
+NvRmPrivAp20DttPolicyUpdate(
+    NvRmDeviceHandle hRmDevice,
+    NvS32 TemperatureC,
+    NvRmDtt* pDtt)
+{
+    NvRmDttAp20PolicyRange Range;
+
+    // CPU throttling limits are set at 50% of CPU frequency range (no
+    // throttling below this value), and at CPU frequency boundary that
+    // matches specified voltage throttling limit.
+    if ((!s_CpuThrottleMaxKHz) || (!s_CpuThrottleMinKHz))
+    {
+        NvU32 steps;
+        const NvRmFreqKHz* p = NvRmPrivModuleVscaleGetMaxKHzList(
+            hRmDevice, NvRmModuleID_Cpu, &steps);
+        NV_ASSERT(p && steps);
+        for (; steps != 0 ; steps--)
+        {
+            if (NVRM_DTT_VOLTAGE_THROTTLE_MV >= NvRmPrivModuleVscaleGetMV(
+                hRmDevice, NvRmModuleID_Cpu, p[steps-1]))
+                break;
+        }
+        NV_ASSERT(steps);
+        s_CpuThrottleMaxKHz = NV_MIN(
+            NvRmPrivGetSocClockLimits(NvRmModuleID_Cpu)->MaxKHz, p[steps-1]);
+        s_CpuThrottleMinKHz =
+            NvRmPrivGetSocClockLimits(NvRmModuleID_Cpu)->MaxKHz / 2;
+        NV_ASSERT(s_CpuThrottleMaxKHz > s_CpuThrottleMinKHz); 
+        NV_ASSERT(s_CpuThrottleMinKHz > NVRM_DTT_CPU_DELTA_KHZ); 
+
+        s_CpuThrottleKHz = s_CpuThrottleMaxKHz;
+
+        NV_ASSERT(pDtt->TcoreCaps.Tmin <
+                  (NVRM_DTT_DEGREES_LOW - NVRM_DTT_DEGREES_HYSTERESIS));
+        NV_ASSERT(pDtt->TcoreCaps.Tmax > NVRM_DTT_DEGREES_HIGH);
+    }
+
+    // Advanced policy range state machine (one step at a time)
+    Range = (NvRmDttAp20PolicyRange)pDtt->TcorePolicy.PolicyRange;
+    switch (Range)
+    {
+        case NvRmDttAp20PolicyRange_Unknown:
+            Range = NvRmDttAp20PolicyRange_FreeRunning;
+            // fall through
+        case NvRmDttAp20PolicyRange_FreeRunning:
+            if (TemperatureC >= NVRM_DTT_DEGREES_LOW)
+                Range = NvRmDttAp20PolicyRange_LimitVoltage;
+            break;
+
+        case NvRmDttAp20PolicyRange_LimitVoltage:
+            if (TemperatureC <=
+                (NVRM_DTT_DEGREES_LOW - NVRM_DTT_DEGREES_HYSTERESIS))
+                Range = NvRmDttAp20PolicyRange_FreeRunning;
+            else if (TemperatureC >= NVRM_DTT_DEGREES_HIGH)
+                Range = NvRmDttAp20PolicyRange_ThrottleDown;
+            break;
+
+        case NvRmDttAp20PolicyRange_ThrottleDown:
+            if (TemperatureC <=
+                (NVRM_DTT_DEGREES_HIGH - NVRM_DTT_DEGREES_HYSTERESIS))
+                Range = NvRmDttAp20PolicyRange_LimitVoltage;
+            break;
+
+        default:
+            break;
+    }
+
+    /*
+     * Fill in new policy. Temperature limits are set around current
+     * temperature for the next out-of-limit interrupt (possible exception
+     * - temperature "jump" over two ranges would result in two interrupts
+     * in a row before limits cover the temperature). Polling time is set
+     * always in ThrottleDown range, and only for poll mode in other ranges.
+     */
+    pDtt->CoreTemperatureC = TemperatureC;
+    switch (Range)
+    {
+        case NvRmDttAp20PolicyRange_FreeRunning:
+            pDtt->TcorePolicy.LowLimit = pDtt->TcoreLowLimitCaps.MinValue;
+            pDtt->TcorePolicy.HighLimit = NVRM_DTT_DEGREES_LOW;
+            pDtt->TcorePolicy.UpdateIntervalUs = pDtt->UseIntr ?
+                NV_WAIT_INFINITE : (NVRM_DTT_POLL_MS_SLOW * 1000);
+            break;
+
+        case NvRmDttAp20PolicyRange_LimitVoltage:
+            pDtt->TcorePolicy.LowLimit =
+                NVRM_DTT_DEGREES_LOW - NVRM_DTT_DEGREES_HYSTERESIS;
+            pDtt->TcorePolicy.HighLimit = NVRM_DTT_DEGREES_HIGH;
+            pDtt->TcorePolicy.UpdateIntervalUs = pDtt->UseIntr ?
+                NV_WAIT_INFINITE : (NVRM_DTT_POLL_MS_FAST * 1000);
+            break;
+
+        case NvRmDttAp20PolicyRange_ThrottleDown:
+            pDtt->TcorePolicy.LowLimit =
+                NVRM_DTT_DEGREES_HIGH - NVRM_DTT_DEGREES_HYSTERESIS;
+            pDtt->TcorePolicy.HighLimit = pDtt->TcoreHighLimitCaps.MaxValue;
+            pDtt->TcorePolicy.UpdateIntervalUs = NVRM_DTT_POLL_MS_CRITICAL * 1000;
+            break;
+
+        default:
+            NV_ASSERT(!"Invalid DTT policy range");
+            NvOsDebugPrintf("DTT: Invalid Range = %d\n", Range);
+            pDtt->TcorePolicy.HighLimit = ODM_TMON_PARAMETER_UNSPECIFIED;
+            pDtt->TcorePolicy.LowLimit = ODM_TMON_PARAMETER_UNSPECIFIED;
+            pDtt->TcorePolicy.PolicyRange = NvRmDttAp20PolicyRange_Unknown;
+            return;
+    }
+    pDtt->TcorePolicy.PolicyRange = (NvU32)Range;
+}
+
+
+NvBool
+NvRmPrivAp20DttClockUpdate(
+    NvRmDeviceHandle hRmDevice,
+    NvS32 TemperatureC,
+    const NvRmTzonePolicy* pDttPolicy,
+    const NvRmDfsFrequencies* pCurrentKHz,
+    NvRmDfsFrequencies* pDfsKHz)
+{
+    switch ((NvRmDttAp20PolicyRange)pDttPolicy->PolicyRange)
+    {
+        case NvRmDttAp20PolicyRange_LimitVoltage:
+            s_CpuThrottleKHz = s_CpuThrottleMaxKHz;
+            break;
+
+        case NvRmDttAp20PolicyRange_ThrottleDown:
+            if (pDttPolicy->UpdateFlag)
+                s_CpuThrottleKHz -= NVRM_DTT_CPU_DELTA_KHZ;
+            s_CpuThrottleKHz = NV_MAX(s_CpuThrottleKHz, s_CpuThrottleMinKHz); 
+            break;
+
+        // No throttling by default (just reset throttling limit to max)
+        default:
+            s_CpuThrottleKHz = s_CpuThrottleMaxKHz;
+            return NV_FALSE;
+    }
+    pDfsKHz->Domains[NvRmDfsClockId_Cpu] =
+        NV_MIN(pDfsKHz->Domains[NvRmDfsClockId_Cpu], s_CpuThrottleKHz);
+
+    // Throttling step is completed - no need to force extra DVFS update
+    return NV_FALSE;
+}
+
+/*****************************************************************************/
+
+NvRmPmRequest 
+NvRmPrivAp20GetPmRequest(
+    NvRmDeviceHandle hRmDevice,
+    const NvRmDfsSampler* pCpuSampler,
+    NvRmFreqKHz* pCpuKHz)
+{
+    // Assume initial slave CPU1 On request
+    static NvRmPmRequest s_LastPmRequest = (NvRmPmRequest_CpuOnFlag | 0x1);
+    static NvRmFreqKHz s_Cpu1OnMinKHz = 0, s_Cpu1OffMaxKHz = 0;
+    static NvU32 s_Cpu1OnPendingCnt = 0, s_Cpu1OffPendingCnt = 0;
+
+    NvRmPmRequest PmRequest = NvRmPmRequest_None;
+    NvBool Cpu1Off =
+        (0 != NV_DRF_VAL(CLK_RST_CONTROLLER, RST_CPU_CMPLX_SET, SET_CPURESET1,
+                         NV_REGR(hRmDevice, NvRmPrivModuleID_ClockAndReset, 0,
+                                 CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0)));
+    NvRmFreqKHz CpuLoadGaugeKHz = *pCpuKHz;
+
+    // Slave CPU1 power management policy thresholds:
+    // - use fixed values if they are defined explicitly, otherwise
+    // - set CPU1 OffMax threshold at 2/3 of cpu frequency range,
+    //   and half of that frequency as CPU1 OnMin threshold
+    if ((s_Cpu1OffMaxKHz == 0) && (s_Cpu1OnMinKHz == 0))
+    {
+        NvRmFreqKHz MaxKHz =
+            NvRmPrivGetSocClockLimits(NvRmModuleID_Cpu)->MaxKHz;
+
+        s_Cpu1OnMinKHz = NVRM_CPU1_ON_MIN_KHZ ?
+                         NVRM_CPU1_ON_MIN_KHZ : (MaxKHz / 3);
+        s_Cpu1OffMaxKHz = NVRM_CPU1_OFF_MAX_KHZ ?
+                          NVRM_CPU1_OFF_MAX_KHZ : (2 * MaxKHz / 3);
+        NV_ASSERT(s_Cpu1OnMinKHz < s_Cpu1OffMaxKHz);
+    }
+
+    /*
+     * Request OS kernel to turn CPU1 Off if all of the following is true:
+     * (a) CPU frequency is below OnMin threshold, 
+     * (b) Last request was CPU1 On request
+     * (c) CPU1 is actually On
+     *
+     * Request OS kernel to turn CPU1 On if all of the following is true:
+     * (a) CPU frequency is above OffMax threshold 
+     * (b) Last request was CPU1 Off request
+     * (c) CPU1 is actually Off
+     */
+    if (CpuLoadGaugeKHz < s_Cpu1OnMinKHz)
+    {
+        s_Cpu1OnPendingCnt = 0;
+        if (s_Cpu1OffPendingCnt < NVRM_CPU1_OFF_PENDING_CNT)
+        {
+            s_Cpu1OffPendingCnt++;
+            return PmRequest;
+        }
+        if ((s_LastPmRequest & NvRmPmRequest_CpuOnFlag) && (!Cpu1Off))
+            s_LastPmRequest = PmRequest = (NvRmPmRequest_CpuOffFlag | 0x1);
+#if NVRM_TEST_PMREQUEST_UP_MODE
+        NV_REGW(hRmDevice, NvRmPrivModuleID_ClockAndReset, 0,
+            CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0,
+            CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_CPURESET1_FIELD);
+#endif
+    }
+    else if (CpuLoadGaugeKHz > s_Cpu1OffMaxKHz)
+    {
+        s_Cpu1OffPendingCnt = 0;
+        if (s_Cpu1OnPendingCnt < NVRM_CPU1_ON_PENDING_CNT)
+        {
+            s_Cpu1OnPendingCnt++;
+            return PmRequest;
+        }
+        if ((s_LastPmRequest & NvRmPmRequest_CpuOffFlag) && Cpu1Off)
+        {
+            s_LastPmRequest = PmRequest = (NvRmPmRequest_CpuOnFlag | 0x1);
+            *pCpuKHz = NvRmPrivGetSocClockLimits(NvRmModuleID_Cpu)->MaxKHz;
+        }
+#if NVRM_TEST_PMREQUEST_UP_MODE
+        NV_REGW(hRmDevice, NvRmPrivModuleID_ClockAndReset, 0,
+            CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0,
+            CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_CPURESET1_FIELD);
+#endif
+    }
+    return PmRequest;
+}
+
+/*****************************************************************************/
diff --git a/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_power_dfs.h b/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_power_dfs.h
new file mode 100644
index 000000000000..97e6cd09310c
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_power_dfs.h
@@ -0,0 +1,384 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/** 
+ * @file
+ * @brief <b>nVIDIA Driver Development Kit: 
+ *           Power Resource manager </b>
+ *
+ * @b Description: NvRM DFS parameters. 
+ * 
+ */
+
+#ifndef INCLUDED_AP20RM_POWER_DFS_H
+#define INCLUDED_AP20RM_POWER_DFS_H
+
+#include "nvrm_power_dfs.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif  /* __cplusplus */
+
+// Min KHz for CPU and AVP with regards to JTAG support - 1MHz * 8  = 8MHz
+// TODO: any other limitations on min KHz?
+// TODO: adjust boost parameters based on testing
+
+/**
+ * Default DFS algorithm parameters for CPU domain
+ */
+#define NVRM_DFS_PARAM_CPU_AP20 \
+    NvRmFreqMaximum, /* Maximum domain frequency set to h/w limit */ \
+    40000,  /* Minimum domain frequency 40 MHz */ \
+    1000,   /* Frequency change upper band 1 MHz */ \
+    1000,   /* Frequency change lower band 1 MHz */ \
+    {          /* RT starvation control parameters */ \
+        32000, /* Fixed frequency boost increase 32 MHz */ \
+        255,   /* Proportional frequency boost increase 255/256 ~ 100% */ \
+        128,   /* Proportional frequency boost decrease 128/256 ~ 50% */  \
+    },\
+    {          /* NRT starvation control parameters */ \
+        10000, /* Fixed frequency boost increase 10 MHz */ \
+        255,   /* Proportional frequency boost increase 255/256 ~ 100% */ \
+        32,    /* Proportional frequency boost decrease 32/256 ~ 12% */  \
+    },\
+    3,      /* Relative adjustement of average freqiency 1/2^3 ~ 12% */ \
+    1,      /* Number of smaple intervals with NRT to trigger boost = 2 */ \
+    1       /* NRT idle cycles threshold = 1 */ 
+
+/**
+ *  Default DFS algorithm parameters for AVP domain
+ */
+#define NVRM_DFS_PARAM_AVP_AP20 \
+    NvRmFreqMaximum, /* Maximum domain frequency set to h/w limit */ \
+    24000,  /* Minimum domain frequency 24 MHz */ \
+    1000,   /* Frequency change upper band 1 MHz */ \
+    1000,   /* Frequency change lower band 1 MHz */ \
+    {          /* RT starvation control parameters */ \
+        8000,  /* Fixed frequency boost increase 8 MHz */ \
+        255,   /* Proportional frequency boost increase 255/256 ~ 100% */ \
+        128,   /* Proportional frequency boost decrease 128/256 ~ 50% */  \
+    },\
+    {          /* NRT starvation control parameters */ \
+        2000,  /* Fixed frequency NRT boost increase 2 MHz */ \
+        255,   /* Proportional frequency boost increase 255/256 ~ 100% */ \
+        128,   /* Proportional frequency boost decrease 128/256 ~ 50% */  \
+    },\
+    3,      /* Relative adjustement of average freqiency 1/2^3 ~ 12% */ \
+    3,      /* Number of smaple intervals with NRT to trigger boost = 4 */ \
+    1       /* NRT idle cycles threshold = 1 */ 
+
+/**
+ * Default DFS algorithm parameters for System clock domain
+ */
+#define NVRM_DFS_PARAM_SYSTEM_AP20 \
+    NvRmFreqMaximum, /* Maximum domain frequency set to h/w limit */ \
+    24000,  /* Minimum domain frequency 24 MHz */ \
+    1000,   /* Frequency change upper band 1 MHz */ \
+    1000,   /* Frequency change lower band 1 MHz */ \
+    {          /* RT starvation control parameters */ \
+        8000,  /* Fixed frequency boost increase 8 MHz */ \
+        255,   /* Proportional frequency boost increase 255/256 ~ 100% */ \
+        128,   /* Proportional frequency boost decrease 128/256 ~ 50% */  \
+    },\
+    {          /* NRT starvation control parameters */ \
+        1000,  /* Fixed frequency NRT boost increase 1 MHz */ \
+        255,   /* Proportional frequency boost increase 255/256 ~ 100% */ \
+        32,    /* Proportional frequency boost decrease 32/256 ~ 12% */  \
+    },\
+    5,      /* Relative adjustement of average freqiency 1/2^5 ~ 3% */ \
+    2,      /* Number of smaple intervals with NRT to trigger boost = 3 */ \
+    1       /* NRT idle cycles threshold = 1 */ 
+
+/**
+ * Default DFS algorithm parameters for AHB clock domain
+ */
+#define NVRM_DFS_PARAM_AHB_AP20 \
+    NvRmFreqMaximum, /* Maximum domain frequency set to h/w limit */ \
+    24000,  /* Minimum domain frequency 24 MHz */ \
+    1000,   /* Frequency change upper band 1 MHz */ \
+    1000,   /* Frequency change lower band 1 MHz */ \
+    {          /* RT starvation control parameters */ \
+        8000,  /* Fixed frequency boost increase 8 MHz */ \
+        255,   /* Proportional frequency boost increase 255/256 ~ 100% */ \
+        128,   /* Proportional frequency boost decrease 128/256 ~ 50% */  \
+    },\
+    {          /* NRT starvation control parameters */ \
+        1000,  /* Fixed frequency NRT boost increase 1 MHz */ \
+        255,   /* Proportional frequency boost increase 255/256 ~ 100% */ \
+        32,    /* Proportional frequency boost decrease 32/256 ~ 12% */  \
+    },\
+    0,      /* Relative adjustement of average freqiency 1/2^0 ~ 100% */ \
+    0,      /* Number of smaple intervals with NRT to trigger boost = 1 */ \
+    1       /* NRT idle cycles threshold = 1 */ 
+
+/**
+ * Default DFS algorithm parameters for APB clock domain
+ */
+#define NVRM_DFS_PARAM_APB_AP20 \
+    NVRM_AP20_APB_MAX_KHZ, /* AP20 APB limit is lower than other buses */ \
+    24000,  /* Minimum domain frequency 24 MHz */ \
+    1000,   /* Frequency change upper band 1 MHz */ \
+    1000,   /* Frequency change lower band 1 MHz */ \
+    {          /* RT starvation control parameters */ \
+        8000,  /* Fixed frequency boost increase 8 MHz */ \
+        255,   /* Proportional frequency boost increase 255/256 ~ 100% */ \
+        128,   /* Proportional frequency boost decrease 128/256 ~ 50% */  \
+    },\
+    {          /* NRT starvation control parameters */ \
+        1000,  /* Fixed frequency NRT boost increase 1 MHz */ \
+        255,   /* Proportional frequency boost increase 255/256 ~ 100% */ \
+        32,    /* Proportional frequency boost decrease 32/256 ~ 12% */  \
+    },\
+    0,      /* Relative adjustement of average freqiency 1/2^0 ~ 100% */ \
+    0,      /* Number of smaple intervals with NRT to trigger boost = 1 */ \
+    1       /* NRT idle cycles threshold = 1 */ 
+
+/**
+ * Default DFS algorithm parameters for Video-pipe clock domain
+ */
+#define NVRM_DFS_PARAM_VPIPE_AP20 \
+    NvRmFreqMaximum, /* Maximum domain frequency set to h/w limit */ \
+    24000,  /* Minimum domain frequency 24 MHz */ \
+    1000,   /* Frequency change upper band 1 MHz */ \
+    1000,   /* Frequency change lower band 1 MHz */ \
+    {          /* RT starvation control parameters */ \
+        16000, /* Fixed frequency RT boost increase 16 MHz */ \
+        255,   /* Proportional frequency boost increase 255/256 ~ 100% */ \
+        128,   /* Proportional frequency boost decrease 128/256 ~ 50% */  \
+    },\
+    {          /* NRT starvation control parameters */ \
+        1000,  /* Fixed frequency NRT boost increase 1 MHz */ \
+        255,   /* Proportional frequency boost increase 255/256 ~ 100% */ \
+        128,   /* Proportional frequency boost decrease 128/256 ~ 50% */  \
+    },\
+    5,      /* Relative adjustement of average freqiency 1/2^5 ~ 3% */ \
+    3,      /* Number of smaple intervals with NRT to trigger boost = 4 */ \
+    1       /* NRT idle cycles threshold = 1 */ 
+
+/**
+ * Default DFS algorithm parameters for EMC clock domain
+ */
+
+// Defines minimum scaling limit for each supported SDRAM type
+#define NVRM_AP20_DDR2_MIN_KHZ (50000)
+#define NVRM_AP20_LPDDR2_MIN_KHZ (18000)
+
+#define NVRM_DFS_PARAM_EMC_AP20_DDR2 \
+    NvRmFreqMaximum, /* Maximum domain frequency set to h/w limit */ \
+    NVRM_AP20_DDR2_MIN_KHZ,  /* Minimum domain frequency for DDR2 */ \
+    1000,   /* Frequency change upper band 1 MHz */ \
+    1000,   /* Frequency change lower band 1 MHz */ \
+    {          /* RT starvation control parameters */ \
+        16000, /* Fixed frequency RT boost increase 16 MHz */ \
+        255,   /* Proportional frequency boost increase 255/256 ~ 100% */ \
+        128,   /* Proportional frequency boost decrease 128/256 ~ 50% */  \
+    },\
+    {          /* NRT starvation control parameters */ \
+        1000,  /* Fixed frequency NRT boost increase 1 MHz */ \
+        255,   /* Proportional frequency boost increase 255/256 ~ 100% */ \
+        128,   /* Proportional frequency boost decrease 128/256 ~ 50% */  \
+    },\
+    1,      /* Relative adjustement of average freqiency 1/2^1 ~ 50% */ \
+    0,      /* Number of smaple intervals with NRT to trigger boost = 1 */ \
+    1       /* NRT idle cycles threshold = 1 */
+
+#define NVRM_DFS_PARAM_EMC_AP20_LPDDR2 \
+    NvRmFreqMaximum, /* Maximum domain frequency set to h/w limit */ \
+    NVRM_AP20_LPDDR2_MIN_KHZ,  /* Minimum domain frequency for LPDDR2 */ \
+    1000,   /* Frequency change upper band 1 MHz */ \
+    1000,   /* Frequency change lower band 1 MHz */ \
+    {          /* RT starvation control parameters */ \
+        16000, /* Fixed frequency RT boost increase 16 MHz */ \
+        255,   /* Proportional frequency boost increase 255/256 ~ 100% */ \
+        128,   /* Proportional frequency boost decrease 128/256 ~ 50% */  \
+    },\
+    {          /* NRT starvation control parameters */ \
+        1000,  /* Fixed frequency NRT boost increase 1 MHz */ \
+        255,   /* Proportional frequency boost increase 255/256 ~ 100% */ \
+        128,   /* Proportional frequency boost decrease 128/256 ~ 50% */  \
+    },\
+    0,      /* Relative adjustement of average freqiency 1/2^0 ~ 100% */ \
+    0,      /* Number of smaple intervals with NRT to trigger boost = 1 */ \
+    1       /* NRT idle cycles threshold = 1 */
+
+#define NVRM_DFS_PARAM_EMC_AP20 NVRM_DFS_PARAM_EMC_AP20_LPDDR2
+
+/**
+ * Defines CPU frequency threshold for slave CPU1 power management:
+ * - CPU1 is turned Off when cpu clock is below ON_MIN for
+ *   ON_PENDING DFS ticks (10ms) in a row
+ * - CPU1 is turned On when cpu clock is above OFF_MAX for
+ *   OFF_PENDING DFS ticks (10ms) in a row
+ * If thresholds are set to 0, the values are derived at run time from the
+ * characterization data
+ */
+#define NVRM_CPU1_ON_MIN_KHZ (0)
+#define NVRM_CPU1_OFF_MAX_KHZ (0)
+
+#define NVRM_CPU1_ON_PENDING_CNT (250)
+#define NVRM_CPU1_OFF_PENDING_CNT (100)
+
+/// Default low corners for core and dedicated CPU voltages
+#define NVRM_AP20_LOW_CORE_MV (950)
+#define NVRM_AP20_LOW_CPU_MV (750)
+
+/// Core voltage in suspend
+#define NVRM_AP20_SUSPEND_CORE_MV (1000)
+
+/*****************************************************************************/
+
+/**
+ * Adjust EMC scaling algorithm parameters based on the SDRAM type selected by
+ * current EMC configuration.
+ *
+ * @param pDfs - A pointer to DFS structure.
+ */
+void NvRmPrivAp20EmcParametersAdjust(NvRmDfs* pDfs);
+
+/**
+ * Initializes activity monitors within the DFS module. Only activity
+ * monitors are affected. The rest of module's h/w is preserved.
+ * 
+ * @param pDfs - A pointer to DFS structure.
+ * 
+ * @return NvSuccess if initialization completed successfully
+ * or one of common error codes on failure.
+ */
+NvError NvRmPrivAp20EmcMonitorsInit(NvRmDfs* pDfs);
+
+/**
+ * Deinitializes activity monitors within the DFS module. Only activity
+ * monitors are affected. The rest of module's h/w is preserved.
+ * 
+ * @param pDfs - A pointer to DFS structure.
+ */
+void NvRmPrivAp20EmcMonitorsDeinit(NvRmDfs* pDfs);
+
+/**
+ * Starts activity monitors in the DFS module for the next sample interval.
+ * 
+ * @param pDfs - A pointer to DFS structure.
+ * @param pDfsKHz - A pointer to current DFS clock frequencies structure.
+ * @param IntervalMs Next sampling interval in ms.
+ */
+void
+NvRmPrivAp20EmcMonitorsStart(
+    const NvRmDfs* pDfs,
+    const NvRmDfsFrequencies* pDfsKHz,
+    const NvU32 IntervalMs);
+
+/**
+ * Reads idle count from activity monitors in the DFS module. The monitors are
+ * stopped.
+ * 
+ * @param pDfs - A pointer to DFS structure.
+ * @param pDfsKHz - A pointer to current DFS clock frequencies structure.
+ * @param pIdleData - A pointer to idle cycles structure to be filled in with
+ *  data read from the monitor.
+ * 
+ */
+void
+NvRmPrivAp20EmcMonitorsRead(
+    const NvRmDfs* pDfs,
+    const NvRmDfsFrequencies* pDfsKHz,
+    NvRmDfsIdleData* pIdleData);
+
+/**
+ * Changes core and rtc voltages, keeping them in synch
+ * 
+ * @param hRm The RM device handle.
+ * @param A pointer to DVS structure.
+ * @param TargetMv Requested core/rtc voltage in mV.
+ * 
+ */
+void
+NvRmPrivAp20DvsChangeCoreVoltage(
+    NvRmDeviceHandle hRm,
+    NvRmDvs* pDvs,
+    NvRmMilliVolts TargetMv);
+
+/**
+ * Updates thermal policy according to current temperature.
+ * 
+ * @param hRmDevice The RM device handle.
+ * @param TemperatureC Current core temperature in degrees C.
+ * @param pDtt A pointer to dynamic thermal throttling structure.
+ */
+
+void
+NvRmPrivAp20DttPolicyUpdate(
+    NvRmDeviceHandle hRmDevice,
+    NvS32 TemperatureC,
+    NvRmDtt* pDt);
+
+/**
+ * Throttles DFS target clocks.
+ * 
+ * @param hRmDevice The RM device handle.
+ * @param TemperatureC Current core temperature in degrees C.
+ * @param pPolicy A pointer to current throttling policy.
+ * @param pCurrentKHz A pointer to current DFS clock frequencies structure.
+ * @param pDfsKHz A pointer to DFS clock structure with target frequencies
+ *  on entry, and throttled frequencies on exit.
+ * 
+ * @return NV_TRUE if throttling requires additional DVFS scaling steps,
+ *  and NV_FALSE otherwise.
+ */
+NvBool
+NvRmPrivAp20DttClockUpdate(
+    NvRmDeviceHandle hRmDevice,
+    NvS32 TemperatureC,
+    const NvRmTzonePolicy* pDttPolicy,
+    const NvRmDfsFrequencies* pCurrentKHz,
+    NvRmDfsFrequencies* pDfsKHz);
+
+/**
+ * Determines PM request to change CPU(s) power state.
+ * 
+ * @param hRmDevice The RM device handle.
+ * @param pCpuSampler Pointer to the DFS CPU clock sampling records
+ * @param pCpuKHz Pointer to the CPU clock frequency target
+ * 
+ * @return New PM request to change CPU power state
+ */
+NvRmPmRequest 
+NvRmPrivAp20GetPmRequest(
+    NvRmDeviceHandle hRmDevice,
+    const NvRmDfsSampler* pCpuSampler,
+    NvRmFreqKHz* pCpuKHz);
+
+#ifdef __cplusplus
+}
+#endif  /* __cplusplus */
+
+#endif // INCLUDED_AP20RM_POWER_DFS_H
diff --git a/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_reloctable.c b/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_reloctable.c
new file mode 100644
index 000000000000..75c5004b65a6
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_reloctable.c
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2008-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include "nvcommon.h"
+#include "nvos.h"
+#include "nvrm_init.h"
+#include "common/nvrm_hwintf.h"
+#include "ap20/project_relocation_table.h"
+#include "ap15/ap15rm_private.h"
+
+static NvU32 s_RelocationTable[] =
+{
+    NV_RELOCATION_TABLE_INIT
+};
+
+NvU32 *
+NvRmPrivAp20GetRelocationTable( NvRmDeviceHandle hDevice )
+{
+    return s_RelocationTable;
+}
+
diff --git a/arch/arm/mach-tegra/nvrm/core/common/Makefile b/arch/arm/mach-tegra/nvrm/core/common/Makefile
new file mode 100644
index 000000000000..9adfebb4cf81
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/core/common/Makefile
@@ -0,0 +1,27 @@
+ccflags-y += -DNV_IS_AVP=0
+ccflags-y += -DNV_OAL=0
+ccflags-y += -DNV_USE_FUSE_CLOCK_ENABLE=0
+ccflags-y += -DNV_SHMOO_DATA_INIT=0
+ifeq ($(CONFIG_MACH_TEGRA_GENERIC_DEBUG),y)
+ccflags-y += -DNV_DEBUG=1
+else
+ccflags-y += -DNV_DEBUG=0
+endif
+
+ccflags-y += -Iarch/arm/mach-tegra/nvrm/core/common
+ccflags-y += -Iarch/arm/mach-tegra/nvrm/core
+
+obj-y += nvrm_pinmux.o
+obj-y += nvrm_keylist.o
+obj-y += nvrm_configuration.o
+obj-y += nvrm_pmu.o
+obj-y += nvrm_module.o
+obj-y += nvrm_hwintf.o
+obj-y += nvrm_chiplib.o
+obj-y += nvrm_clocks_limits.o
+obj-y += nvrm_clocks_limits_stub.o
+obj-y += nvrm_power.o
+obj-y += nvrm_power_dfs.o
+obj-y += nvrm_rmctrace.o
+obj-y += nvrm_relocation_table.o
+obj-y += nvrm_transport.o
diff --git a/arch/arm/mach-tegra/nvrm/core/common/chiplib_interface.h b/arch/arm/mach-tegra/nvrm/core/common/chiplib_interface.h
new file mode 100644
index 000000000000..9b27133fd7d2
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/core/common/chiplib_interface.h
@@ -0,0 +1,182 @@
+/*
+ * Copyright (c) 2006-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_CHIPLIB_INTERFACE_H
+#define INCLUDED_CHIPLIB_INTERFACE_H
+
+#include "nvcommon.h"
+
+// IIfaceObject and bootstrapping logic
+typedef enum
+{
+    IID_QUERY_IFACE         = 0,
+    IID_CHIP_IFACE          = 1,
+    IID_INTERRUPT_IFACE     = 8,
+    IID_BUSMEM_IFACE        = 16,
+    IID_LAST_IFACE          = 0xFFFF
+} IID_TYPE;
+
+struct IIfaceObjectRec;
+
+typedef struct IIfaceObjectVtableRec
+{
+    void *Unused1;
+    void *Unused2;
+
+    // IIfaceObject interface
+    void (*AddRef)(struct IIfaceObjectRec *pThis);
+    void (*Release)(struct IIfaceObjectRec *pThis);
+    struct IIfaceObjectRec *(*QueryIface)(struct IIfaceObjectRec *pThis,
+        IID_TYPE id);
+} IIfaceObjectVtable;
+
+typedef struct IIfaceObjectRec
+{
+    IIfaceObjectVtable *pVtable;
+} IIfaceObject;
+
+typedef IIfaceObject *(*QueryIfaceFn)(IID_TYPE id);
+#define QUERY_PROC_NAME "QueryIface"
+
+// IChip
+typedef enum
+{
+    ELEVEL_UNKNOWN    = 0,
+    ELEVEL_HW         = 1,
+    ELEVEL_RTL        = 2,
+    ELEVEL_CMODEL     = 3
+} ELEVEL;
+
+struct IChipRec;
+
+typedef struct IChipVtableRec
+{
+    void *Unused1;
+    void *Unused2;
+
+    // IIfaceObject interface
+    void (*AddRef)(struct IChipRec *pThis);
+    void (*Release)(struct IChipRec *pThis);
+    IIfaceObject *(*QueryIface)(struct IChipRec *pThis, IID_TYPE id);
+
+    void *Unused3;
+
+    // IChip interface
+    int (*Startup)(struct IChipRec *pThis, IIfaceObject* system, char** argv,
+        int argc);
+    void (*Shutdown)(struct IChipRec *pThis);
+    int (*AllocSysMem)(struct IChipRec *pThis, int numBytes, NvU32* physAddr);
+    void (*FreeSysMem)(struct IChipRec *pThis, NvU32 physAddr);
+    void (*ClockSimulator)(struct IChipRec *pThis, NvS32 numClocks);
+    void (*Delay)(struct IChipRec *pThis, NvU32 numMicroSeconds);
+    int (*EscapeWrite)(struct IChipRec *pThis, char* path, NvU32 index,
+        NvU32 size, NvU32 value);
+    int (*EscapeRead)(struct IChipRec *pThis, char* path, NvU32 index,
+        NvU32 size, NvU32* value);
+    int (*FindPCIDevice)(struct IChipRec *pThis, NvU16 vendorId,
+        NvU16 deviceId, int index, NvU32* address);
+    int (*FindPCIClassCode)(struct IChipRec *pThis, NvU32 classCode, int index,
+        NvU32* address);
+    int (*GetSimulatorTime)(struct IChipRec *pThis, NvU64* simTime);
+    double (*GetSimulatorTimeUnitsNS)(struct IChipRec *pThis);
+    int (*GetPCIBaseAddress)(struct IChipRec *pThis, NvU32 cfgAddr, int index,
+        NvU32* pAddress, NvU32* pSize);
+    ELEVEL (*GetChipLevel)(struct IChipRec *pThis);
+} IChipVtable;
+
+typedef struct IChipRec
+{
+    IChipVtable *pVtable;
+} IChip;
+
+// IBusMem
+typedef enum
+{
+    BUSMEM_HANDLED      = 0,
+    BUSMEM_NOTHANDLED   = 1,
+} BusMemRet;
+
+struct IBusMemRec;
+
+typedef struct IBusMemVtableRec
+{
+    void *Unused1;
+    void *Unused2;
+
+    // IIfaceObject interface
+    void (*AddRef)(struct IBusMemRec *pThis);
+    void (*Release)(struct IBusMemRec *pThis);
+    IIfaceObject *(*QueryIface)(struct IBusMemRec *pThis, IID_TYPE id);
+
+    void *Unused3;
+
+    // IBusMem interface
+    BusMemRet (*BusMemWrBlk)(struct IBusMemRec *pThis, NvU64 address,
+        const void *appdata, NvU32 count);
+    BusMemRet (*BusMemRdBlk)(struct IBusMemRec *pThis, NvU64 address,
+        void *appdata, NvU32 count);
+    BusMemRet (*BusMemCpBlk)(struct IBusMemRec *pThis, NvU64 dest,
+        NvU64 source, NvU32 count);
+    BusMemRet (*BusMemSetBlk)(struct IBusMemRec *pThis, NvU64 address,
+        NvU32 size, void* data, NvU32 data_size);
+} IBusMemVtable;
+
+typedef struct IBusMemRec
+{
+    IBusMemVtable *pVtable;
+} IBusMem;
+
+struct IInterruptRec;
+
+typedef struct IInterruptVtableRec
+{
+    void *Unused1;
+    void *Unused2;
+
+    // IIfaceObject interface
+    void (*AddRef)(struct IInterruptRec *pThis);
+    void (*Release)(struct IInterruptRec *pThis);
+    IIfaceObject *(*QueryIface)(struct IInterruptRec *pThis, IID_TYPE id);
+
+    void *Unused3;
+
+    // IInterrupt interface
+    void (*HandleInterrupt)( struct IInterruptRec *pThis );
+
+} IInterruptVtable;
+
+typedef struct IInterruptRec
+{
+    IInterruptVtable *pVtable;
+} IInterrupt;
+
+#endif // INCLUDED_CHIPLIB_INTERFACE_H
diff --git a/arch/arm/mach-tegra/nvrm/core/common/nvrm_chipid.h b/arch/arm/mach-tegra/nvrm/core/common/nvrm_chipid.h
new file mode 100644
index 000000000000..52742c0a287e
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/core/common/nvrm_chipid.h
@@ -0,0 +1,101 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_NVRM_CHIPID_H
+#define INCLUDED_NVRM_CHIPID_H
+
+#include "nvcommon.h"
+#include "nvrm_init.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif  /* __cplusplus */
+
+/* Chip Id */
+typedef enum
+{
+    NvRmChipFamily_Gpu = 0,
+    NvRmChipFamily_Handheld = 1,
+    NvRmChipFamily_BrChips = 2,
+    NvRmChipFamily_Crush = 3,
+    NvRmChipFamily_Mcp = 4,
+    NvRmChipFamily_Ck = 5,
+    NvRmChipFamily_Vaio = 6,
+    NvRmChipFamily_HandheldSoc = 7,
+
+    NvRmChipFamily_Force32 = 0x7FFFFFFF,
+} NvRmChipFamily;
+
+typedef enum
+{
+    NvRmCaps_HasFalconInterruptController = 0,
+    NvRmCaps_Has128bitInterruptSerializer,
+    NvRmCaps_Num,
+    NvRmCaps_Force32 = 0x7FFFFFFF,
+}  NvRmCaps;
+
+typedef struct NvRmChipIdRec
+{
+    NvU16 Id;
+    NvRmChipFamily Family;
+    NvU8 Major;
+    NvU8 Minor;
+    NvU16 SKU;
+
+    /* the following only apply for emulation -- Major will be 0 and
+     * Minor is either 0 for quickturn or 1 for fpga
+     */
+    NvU16 Netlist;
+    NvU16 Patch;
+
+    /* List of features and bug WARs */
+    NvU32 Flags[(NvRmCaps_Num+31)/32];
+} NvRmChipId;
+
+#define NVRM_IS_CAP_SET(h, bit) (((h)->ChipId.Flags)[(bit) >> 5] & (1 << ((bit) & 31)))
+#define NVRM_CAP_SET(h, bit) (((h)->ChipId.Flags)[(bit) >> 5] |= (1U << ((bit) & 31U)))
+#define NVRM_CAP_CLEAR(h, bit) (((h)->ChipId.Flags)[(bit) >> 5] &= ~(1U << ((bit) & 31U)))
+
+/**
+ * Gets the chip id.
+ *
+ * @param hDevice The RM instance
+ */
+NvRmChipId *
+NvRmPrivGetChipId( NvRmDeviceHandle hDevice );
+
+#ifdef __cplusplus
+}
+#endif  /* __cplusplus */
+
+#endif // INCLUDED_NVRM_CHIPID_H
diff --git a/arch/arm/mach-tegra/nvrm/core/common/nvrm_chiplib.c b/arch/arm/mach-tegra/nvrm/core/common/nvrm_chiplib.c
new file mode 100644
index 000000000000..5df00be58843
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/core/common/nvrm_chiplib.c
@@ -0,0 +1,846 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include "nvcommon.h"
+#include "nvrm_hardware_access.h"
+#include "nvassert.h"
+#include "nvos.h"
+#include "chiplib_interface.h"
+#include "nvrm_chiplib.h"
+#include "nvrm_init.h"
+
+/**
+ * NOTE: newer versions of chiplib (t30) use GCC 4, which changes the virtual
+ * table layout. To get around this, C wrapper functions were added, so this
+ * needs to check for 'QueryIface_C', which will return a struct full of
+ * C function wrappers rather than the old method, which is to overlay a C
+ * structure manually.
+ */
+
+/* table for virtual to physical lookups */
+typedef struct RmAddrMap_t
+{
+    NvRmPhysAddr phys;
+    void *virt;
+    size_t size;
+} RmAddrMap;
+
+#define RM_ADDR_MAP_SIZE 256
+
+static RmAddrMap s_AddrMap[ RM_ADDR_MAP_SIZE ];
+static NvBool s_Shutdown;
+
+static NvOsLibraryHandle s_chiplib = 0;
+static IChip *s_IChip = 0;
+static IBusMem *s_IBusMem = 0;
+static NvOsMutexHandle s_ChiplibMutex = 0;
+
+static NvOsThreadHandle s_clockThreadId = NULL;
+static volatile NvBool s_bShutdownClockThread = NV_FALSE;
+
+static NvOsMutexHandle s_simIstMutex;
+
+/**
+ * IInterrupt support
+ */
+static IInterrupt s_Interrupt;
+static void AddRef_IInterrupt(struct IInterruptRec *pThis) { }
+static void Release_IInterrupt(struct IInterruptRec *pThis) { }
+
+static void
+NvRmPrivChiplibInterruptHandler( void );
+
+static IIfaceObject *
+QueryIface_IInterrupt(struct IInterruptRec *pThis,
+    IID_TYPE id)
+{
+    IIfaceObject *ret;
+
+    switch (id)  {
+    case IID_INTERRUPT_IFACE:
+        ret = (IIfaceObject *)&s_Interrupt;
+        break;
+    case IID_CHIP_IFACE:
+        // fall through
+    case IID_BUSMEM_IFACE:
+        // fall through
+    default:
+        ret = 0;
+    }
+
+    return ret;
+}
+
+/**
+ * Note about deadlock: the interrupt handler must not be called with
+ * s_ChiplibMutex locked, otherwise there are lock ordering issues. The
+ * best solution is to force cooperative threading.  The second best is to
+ * use an indirection thread to actually execute the handler.
+ */
+
+static ChiplibHandleInterrupt s_HandleInterrupt;
+static NvOsSemaphoreHandle s_IsrSemaphore;
+static NvOsThreadHandle s_IsrThread;
+
+static void
+NvRmPrivChiplibInterruptThread( void *args )
+{
+    for( ;; )
+    {
+        NvOsSemaphoreWait( s_IsrSemaphore );
+        if( s_Shutdown )
+        {
+            break;
+        }
+
+        if( !s_IChip )
+        {
+            break;
+        }
+
+        if( s_HandleInterrupt )
+        {
+            s_HandleInterrupt();
+        }
+    }
+}
+
+static void
+HandleInterrupt_IInterrupt(struct IInterruptRec *pThis)
+{
+    if( s_IsrThread && s_IsrSemaphore )
+    {
+        NvOsSemaphoreSignal( s_IsrSemaphore );
+    }
+}
+
+static void
+NvRmPrivChiplibClockthread( void *args )
+{
+    NvError err;
+    NvBool bSleep = NV_FALSE;
+
+    err = NvOsThreadSetLowPriority();
+    if( err != NvSuccess )
+    {
+        bSleep = NV_TRUE;
+    }
+
+    while( s_bShutdownClockThread == NV_FALSE )
+    {
+        if( s_IChip )
+        {
+            NvS32 clocks;
+            if( bSleep )
+            {
+                clocks = 500;
+            } else
+            {
+                clocks = 32;
+            }
+
+            NV_ASSERT(s_ChiplibMutex);
+            NvOsMutexLock(s_ChiplibMutex);
+            s_IChip->pVtable->ClockSimulator(s_IChip, clocks);
+            NvOsMutexUnlock(s_ChiplibMutex);
+        }
+
+        /* thread package might not support low priority threads, emulate it.
+         */
+        if( bSleep )
+        {
+            NvOsSleepMS( 50 );
+        }
+        else
+        {
+            NvOsThreadYield();
+        }
+    }
+}
+
+static NvBool
+NvRmPrivParseCommandline(const char *cmdline, int *argc, char ***argv,
+    char ***argvbuf, char **pCopy);
+
+#if NV_DEF_ENVIRONMENT_SUPPORTS_SIM
+NvBool
+NvRmIsSimulation(void)
+{
+    return (NvBool)(s_chiplib != NULL);
+}
+#endif
+
+typedef void *(*QueryIfaceCFn)( IID_TYPE id );
+
+NvError
+NvRmPrivChiplibStartup(const char *lib, const char *cmdline,
+    ChiplibHandleInterrupt handler)
+{
+    NvError err;
+    void *sym;
+    QueryIfaceFn query;
+    QueryIfaceCFn c_wrap;
+    char *copy = 0;
+    char **argvbuf = 0;
+    char **argv = 0;
+    int argc = 0;
+    int e;
+
+    NV_ASSERT(lib);
+
+    if( lib[0] == 0 )
+    {
+        /* no chiplib defined */
+        return NvSuccess;
+    }
+
+    /* all chiplib accesses must be synchronized - do not use a multi-process
+     * mutex since that prevents other simulation instances on the same
+     * machine.
+     */
+    err = NvOsMutexCreate( &s_ChiplibMutex );
+    if (err != NvSuccess)
+    {
+        goto fail;
+    }
+
+    err = NvOsSemaphoreCreate( &s_IsrSemaphore, 0 );
+    if( err != NvSuccess )
+    {
+        goto fail;
+    }
+
+    s_Shutdown = NV_FALSE;
+    err = NvOsThreadCreate( NvRmPrivChiplibInterruptThread, 0, &s_IsrThread );
+    if( err != NvSuccess )
+    {
+        goto fail;
+    }
+
+    /* open the chiplib .so */
+    err = NvOsLibraryLoad( lib, &s_chiplib );
+    if( err != NvSuccess )
+    {
+        goto fail;
+    }
+
+    /* try to find the C wrapper struct, if not, fallback to the old way of
+     * doing thigs.
+     */
+    c_wrap = NvOsLibraryGetSymbol( s_chiplib, "QueryIface_C" );
+    if( c_wrap )
+    {
+        s_IChip = (IChip *)c_wrap( IID_CHIP_IFACE );
+    }
+    else
+    {
+        /* get a chiplib instance - QUERY_PROC_NAME, etc., are from chiplib
+         * headers.
+         */
+        sym = NvOsLibraryGetSymbol( s_chiplib, QUERY_PROC_NAME );
+        if( sym == NULL )
+        {
+            goto fail;
+        }
+
+        query = (QueryIfaceFn)sym;
+        s_IChip = (IChip *)query( IID_CHIP_IFACE );
+    }
+    if( !s_IChip )
+    {
+        goto fail;
+    }
+
+    // FIXME: should probably check for errors
+    (void)NvRmPrivParseCommandline(cmdline, &argc, &argv, &argvbuf, &copy);
+
+    /* setup the interrupt handler */
+    s_Interrupt.pVtable = NvOsAlloc(sizeof(IInterruptVtable));
+    if( !s_Interrupt.pVtable )
+    {
+        goto fail;
+    }
+    s_Interrupt.pVtable->AddRef = AddRef_IInterrupt;
+    s_Interrupt.pVtable->Release = Release_IInterrupt;
+    s_Interrupt.pVtable->QueryIface = QueryIface_IInterrupt;
+    s_Interrupt.pVtable->HandleInterrupt = HandleInterrupt_IInterrupt;
+
+    /* Use the default handler if the passed handler is NULL */
+    if( handler == NULL )
+    {
+        s_HandleInterrupt = NvRmPrivChiplibInterruptHandler;
+    }
+
+    /* start chiplib */
+    e = s_IChip->pVtable->Startup(s_IChip, (IIfaceObject *)&s_Interrupt,
+        argv, argc );
+    if( e )
+    {
+        goto fail;
+    }
+
+    /* get the bus interface */
+    s_IBusMem = (IBusMem *)s_IChip->pVtable->QueryIface( s_IChip,
+        IID_BUSMEM_IFACE );
+    if( !s_IBusMem )
+    {
+        goto fail;
+    }
+
+    if( NvRmIsSimulation() )
+    {
+        s_bShutdownClockThread = NV_FALSE;
+
+        err = NvOsMutexCreate( &s_simIstMutex );
+        if( err != NvSuccess )
+        {
+            goto fail;
+        }
+
+        err = NvOsThreadCreate(NvRmPrivChiplibClockthread, NULL,
+            &s_clockThreadId);
+        if (err != NvSuccess)
+        {
+            goto fail;
+        }
+    }
+
+    NvOsFree( copy );
+    NvOsFree( argvbuf );
+    return NvSuccess;
+
+fail:
+    NvOsFree( copy );
+    NvOsFree( argvbuf );
+    NvOsMutexDestroy(s_ChiplibMutex);
+    NvOsLibraryUnload(s_chiplib);
+    s_chiplib = 0;
+    s_IChip = 0;
+    s_IBusMem = 0;
+
+    if( s_IsrSemaphore && s_IsrThread )
+    {
+        NvOsSemaphoreSignal( s_IsrSemaphore );
+        NvOsThreadJoin( s_IsrThread );
+    }
+    NvOsSemaphoreDestroy( s_IsrSemaphore );
+    s_IsrSemaphore = 0;
+
+    return NvError_RmInitFailed;
+}
+
+void
+NvRmPrivChiplibShutdown(void)
+{
+    /* First shtdown the interrupt thread */
+    if( s_IsrSemaphore && s_IsrThread )
+    {
+        s_Shutdown = NV_TRUE;
+        NvOsSemaphoreSignal( s_IsrSemaphore );
+        NvOsThreadJoin( s_IsrThread );
+        s_Shutdown = NV_FALSE;
+    }
+    NvOsSemaphoreDestroy( s_IsrSemaphore );
+    s_IsrSemaphore = 0;
+
+    /* next shutdown the clocking thread */
+    if (NvRmIsSimulation())
+    {
+        s_bShutdownClockThread = NV_TRUE;
+        NvOsThreadJoin( s_clockThreadId );
+        NvOsMutexDestroy(s_simIstMutex);
+        s_simIstMutex = 0;
+        s_clockThreadId = 0;
+    }
+
+    /* Finally shutdown the chiplib */
+    NvOsMutexLock(s_ChiplibMutex);
+    if (s_IChip)
+    {
+        s_IChip->pVtable->Shutdown(s_IChip);
+        s_IChip->pVtable->Release(s_IChip);
+        s_IChip = NULL;
+    }
+    if (s_IBusMem)
+    {
+        s_IBusMem->pVtable->Release(s_IBusMem);
+        s_IBusMem = NULL;
+    }
+
+    if (s_Interrupt.pVtable)
+    {
+        s_Interrupt.pVtable->Release(&s_Interrupt);
+        NvOsFree(s_Interrupt.pVtable);
+    }
+    NvOsMutexDestroy(s_ChiplibMutex);
+}
+
+static NvBool
+NvRmPrivParseCommandline( const char *cmdline, int *argc, char ***argv,
+    char ***pArgv, char **pCopy )
+{
+    /* keep some amount of stack space to prevent dynamic allocation in the
+     * average case.
+     */
+    #define TOKEN_SIZE_GUESS 16
+
+    static char *s_argv[ TOKEN_SIZE_GUESS ];
+    char *env = 0;
+    char *start = 0;
+    char *end = 0;
+    char *copy = 0;
+    NvU32 size;
+    NvU32 len;
+    NvU32 index;
+
+    /* get the command line */
+    env = (char *)cmdline;
+
+    /*
+     * this needs to do two passes over the environment string. can't think
+     * of a way to do it with one pass without using realloc.  performace
+     * should be ok either way and doesn't really matter anyway.
+     *
+     * just allocate one copy of the env string, then replace the spaces
+     * with nulls, assign the tokens into argv - this avoids strcpy and
+     * an allocation per token.
+     */
+
+    /* count the number of tokens and env string length */
+    size = 1; /* (should) always be at least one token */
+    len = 0;
+    start = env;
+    while (*start)
+    {
+        if (*start == ' ')
+        {
+            size++;
+        }
+
+        start++;
+        len++;
+    }
+
+    if (len == 0)
+    {
+        return NV_FALSE;
+    }
+
+    /* allocate argv */
+    size++; /* executable name */
+    size++; /* null terminate array */
+    if (size >= TOKEN_SIZE_GUESS)
+    {
+        *argv = NvOsAlloc(size * sizeof(char *));
+        if (!(*argv))
+        {
+            return NV_FALSE;
+        }
+        *pArgv = *argv;
+    }
+    else
+    {
+        /* guess that most argv arrays are TOKEN_SIZE_GUESS or less long */
+        *argv = s_argv;
+    }
+
+    /* assign argc */
+    *argc = size - 1; /* don't include null termination */
+
+    (*argv)[ size ] = 0;
+    // FIXME: should get the execuable name
+    (*argv)[ 0 ] = "bogus"; /* executable name */
+
+    /* allocate and copy the string */
+    len++;
+    copy = NvOsAlloc(len);
+    if (copy == 0)
+    {
+        goto fail;
+    }
+
+    *pCopy = copy;
+
+    NvOsStrncpy(copy, env, len - 1);
+    copy[ len - 1 ] = 0;
+
+    /* fill argv - find each token - assign to argv */
+    index = 1;
+    start = copy;
+    while (*start)
+    {
+        /* find a token */
+        end = start;
+        while (*end && *end != ' ')
+        {
+            end++;
+        }
+
+        /* assign to argv */
+        (*argv)[ index ] = start;
+        index++;
+
+        start = end;
+        if (*end == ' ')
+        {
+            /* replace space with null and move to next token */
+            *end = 0;
+            start++;
+        }
+    }
+
+    return NV_TRUE;
+
+fail:
+    NvOsFree(*pArgv);
+    *pArgv = 0;
+    NvOsFree(copy);
+    *pCopy = 0;
+
+    #undef TOKEN_SIZE_GUESS
+
+    return NV_FALSE;
+}
+
+void *
+NvRmPrivChiplibMap(NvRmPhysAddr addr, size_t size)
+{
+    NvError err;
+    void *virt;
+    NvU32 i;
+    RmAddrMap *map = 0;
+
+    /* map some bogus memory with guard page */
+    err = NvOsPhysicalMemMap(addr, size + 4096, NvOsMemAttribute_WriteBack,
+        NVOS_MEM_NONE, &virt);
+    if (err != NvSuccess)
+    {
+        return 0;
+    }
+
+    /* find a free entry */
+    for (i = 0; i < RM_ADDR_MAP_SIZE; i++)
+    {
+        if (s_AddrMap[i].phys == 0 &&
+            s_AddrMap[i].virt == 0)
+        {
+            map = &s_AddrMap[i];
+            break;
+        }
+    }
+
+    if (!map)
+    {
+        NvOsPhysicalMemUnmap(virt, size + 4096);
+        return 0;
+    }
+
+    /* setup entry */
+    map->phys = addr;
+    map->virt = virt;
+    map->size = size;
+
+    return virt;
+}
+
+void
+NvRmPrivChiplibUnmap(void *addr)
+{
+    NvU32 i;
+
+    if( !addr )
+    {
+        return;
+    }
+
+    for( i = 0; i < RM_ADDR_MAP_SIZE; i++ )
+    {
+        if( s_AddrMap[i].virt == addr )
+        {
+            /* unmap (don't forget the guard page) */
+            NvOsPhysicalMemUnmap(addr, s_AddrMap[i].size + 4096);
+            NvOsMemset(&s_AddrMap[i], 0, sizeof(s_AddrMap[i]));
+            break;
+        }
+    }
+}
+
+static NvBool
+NvRmPrivVirtToPhys(const void *virt, NvRmPhysAddr *phys)
+{
+    NvU32 i;
+    RmAddrMap *map;
+    NvRmPhysAddr addr;
+    NvRmPhysAddr base;
+
+    addr = (NvRmPhysAddr)virt;
+
+    /* find the address range and convert to a physical address, use
+     * physical address type just to be safe.
+     */
+    for( i = 0; i < RM_ADDR_MAP_SIZE; i++ )
+    {
+        map = &s_AddrMap[i];
+        base = (NvRmPhysAddr)map->virt;
+        if( addr >= base && addr < (base + map->size) )
+        {
+            *phys = addr - base + map->phys;
+            return NV_TRUE;
+        }
+    }
+
+    return NV_FALSE;
+}
+
+void NvWrite08(void *addr, NvU8 data)
+{
+    BusMemRet err;
+    NvRmPhysAddr phys;
+
+    if (!s_IBusMem || !NvRmPrivVirtToPhys(addr, &phys))
+    {
+        *(NvU8 *)addr = data;
+    }
+    else
+    {
+        NvOsMutexLock(s_ChiplibMutex);
+        err = s_IBusMem->pVtable->BusMemWrBlk(s_IBusMem, phys, &data,
+            sizeof(data));
+        NV_ASSERT(err == BUSMEM_HANDLED);
+        NvOsMutexUnlock(s_ChiplibMutex);
+    }
+}
+
+void NvWrite16(void *addr, NvU16 data)
+{
+    BusMemRet err;
+    NvRmPhysAddr phys;
+
+    if (!s_IBusMem || !NvRmPrivVirtToPhys(addr, &phys))
+    {
+        *(NvU16 *)addr = data;
+    }
+    else
+    {
+        NvOsMutexLock(s_ChiplibMutex);
+        err = s_IBusMem->pVtable->BusMemWrBlk(s_IBusMem, phys, &data,
+            sizeof(data));
+        NV_ASSERT(err == BUSMEM_HANDLED);
+        NvOsMutexUnlock(s_ChiplibMutex);
+    }
+}
+
+void NvWrite32(void *addr, NvU32 data)
+{
+    BusMemRet err;
+    NvRmPhysAddr phys;
+
+    if (!s_IBusMem || !NvRmPrivVirtToPhys(addr, &phys))
+    {
+        *(NvU32 *)addr = data;
+    }
+    else
+    {
+        NvOsMutexLock(s_ChiplibMutex);
+        err = s_IBusMem->pVtable->BusMemWrBlk(s_IBusMem, phys, &data,
+            sizeof(data));
+        NV_ASSERT(err == BUSMEM_HANDLED);
+        NvOsMutexUnlock(s_ChiplibMutex);
+    }
+}
+
+void NvWrite64(void *addr, NvU64 data)
+{
+    BusMemRet err;
+    NvRmPhysAddr phys;
+
+    if (!s_IBusMem || !NvRmPrivVirtToPhys(addr, &phys))
+    {
+        *(NvU64 *)addr = data;
+    }
+    else
+    {
+        NvOsMutexLock(s_ChiplibMutex);
+        err = s_IBusMem->pVtable->BusMemWrBlk(s_IBusMem, phys, &data,
+            sizeof(data));
+        NV_ASSERT(err == BUSMEM_HANDLED);
+        NvOsMutexUnlock(s_ChiplibMutex);
+    }
+}
+
+NvU8 NvRead08(void *addr)
+{
+    BusMemRet err;
+    NvRmPhysAddr phys;
+    NvU8 ret;
+
+    if (!s_IBusMem || !NvRmPrivVirtToPhys(addr, &phys))
+    {
+        ret = *(NvU8 *)addr;
+    }
+    else
+    {
+        NvOsMutexLock(s_ChiplibMutex);
+        err = s_IBusMem->pVtable->BusMemRdBlk(s_IBusMem, phys, &ret,
+            sizeof(ret));
+        NV_ASSERT(err == BUSMEM_HANDLED);
+        NvOsMutexUnlock(s_ChiplibMutex);
+    }
+
+    return ret;
+}
+
+NvU16 NvRead16(void *addr)
+{
+    BusMemRet err;
+    NvRmPhysAddr phys;
+    NvU16 ret;
+
+    if (!s_IBusMem || !NvRmPrivVirtToPhys(addr, &phys))
+    {
+        ret = *(NvU16 *)addr;
+    }
+    else
+    {
+        NvOsMutexLock(s_ChiplibMutex);
+        err = s_IBusMem->pVtable->BusMemRdBlk(s_IBusMem, phys, &ret,
+            sizeof(ret));
+        NV_ASSERT(err == BUSMEM_HANDLED);
+        NvOsMutexUnlock(s_ChiplibMutex);
+    }
+
+    return ret;
+}
+
+NvU32 NvRead32(void *addr)
+{
+    BusMemRet err;
+    NvRmPhysAddr phys;
+    NvU32 ret;
+
+    if (!s_IBusMem || !NvRmPrivVirtToPhys(addr, &phys))
+    {
+        ret = *(NvU32 *)addr;
+    }
+    else
+    {
+        NvOsMutexLock(s_ChiplibMutex);
+        err = s_IBusMem->pVtable->BusMemRdBlk(s_IBusMem, phys, &ret,
+            sizeof(ret));
+        NV_ASSERT(err == BUSMEM_HANDLED);
+        NvOsMutexUnlock(s_ChiplibMutex);
+    }
+
+    return ret;
+}
+
+NvU64 NvRead64(void *addr)
+{
+    BusMemRet err;
+    NvRmPhysAddr phys;
+    NvU64 ret;
+
+    if (!s_IBusMem || !NvRmPrivVirtToPhys(addr, &phys))
+    {
+        ret = *(NvU64 *)addr;
+    }
+    else
+    {
+        NvOsMutexLock(s_ChiplibMutex);
+        err = s_IBusMem->pVtable->BusMemRdBlk(s_IBusMem, phys, &ret,
+            sizeof(ret));
+        NV_ASSERT(err == BUSMEM_HANDLED);
+        NvOsMutexUnlock(s_ChiplibMutex);
+    }
+
+    return ret;
+}
+
+void NvWriteBlk(void *dst, const void *src, NvU32 length)
+{
+    BusMemRet err;
+    NvRmPhysAddr phys;
+
+    if (!s_IBusMem || !NvRmPrivVirtToPhys(dst, &phys))
+    {
+        NvOsMemcpy(dst, src, length);
+    }
+    else
+    {
+        NvOsMutexLock(s_ChiplibMutex);
+        err = s_IBusMem->pVtable->BusMemWrBlk(s_IBusMem, phys, src, length);
+        NV_ASSERT(err == BUSMEM_HANDLED);
+        NvOsMutexUnlock(s_ChiplibMutex);
+    }
+}
+
+void NvReadBlk(void *dst, const void *src, NvU32 length)
+{
+    BusMemRet err;
+    NvRmPhysAddr phys;
+
+    if (!s_IBusMem || !NvRmPrivVirtToPhys(src, &phys))
+    {
+        NvOsMemcpy(dst, src, length);
+    }
+    else
+    {
+        NvOsMutexLock(s_ChiplibMutex);
+        err = s_IBusMem->pVtable->BusMemRdBlk(s_IBusMem, phys, dst, length);
+        NV_ASSERT(err == BUSMEM_HANDLED);
+        NvOsMutexUnlock(s_ChiplibMutex);
+    }
+}
+
+extern void
+NvRmPrivHandleOsInterrupt( void *arg );
+
+static void
+NvRmPrivChiplibInterruptHandler( void )
+{
+    if (NvRmIsSimulation())
+    {
+        NvOsMutexLock(s_simIstMutex);
+    }
+
+    /* Chiplib and AOS share the interrpt handling code. 
+     * No chiplib interrupt support for wince and linux ARM port 
+     */
+#if !NVCPU_IS_ARM
+    NvRmPrivHandleOsInterrupt(NULL);
+#endif
+
+    if (NvRmIsSimulation())
+    {
+        NvOsMutexUnlock(s_simIstMutex);
+    }
+}
diff --git a/arch/arm/mach-tegra/nvrm/core/common/nvrm_chiplib.h b/arch/arm/mach-tegra/nvrm/core/common/nvrm_chiplib.h
new file mode 100644
index 000000000000..b617e7b41c25
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/core/common/nvrm_chiplib.h
@@ -0,0 +1,94 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_NVRM_CHIPLIB_H
+#define INLCUDED_NVRM_CHIPLIB_H
+
+#include "nvcommon.h"
+#include "nvrm_hardware_access.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif  /* __cplusplus */
+
+/**
+ * Chiplib interrupt handler function.
+ */
+typedef void (* ChiplibHandleInterrupt)( void );
+
+#if NV_DEF_ENVIRONMENT_SUPPORTS_SIM == 1
+NvBool NvRmIsSimulation(void);
+#else
+#define NvRmIsSimulation() NV_FALSE
+#endif
+
+/**
+ * starts chiplib.
+ *
+ * @param lib The chiplib name
+ * @param cmdline The chiplib command line
+ * @param handle The interrupt handler - will be called by chiplib
+ */
+NvError
+NvRmPrivChiplibStartup( const char *lib, const char *cmdline,
+    ChiplibHandleInterrupt handler );
+
+/**
+ * stops chiplib.
+ */
+void
+NvRmPrivChiplibShutdown( void );
+
+/**
+ * maps a bogus virtual address to a physical address.
+ *
+ * @param addr The physical address to map
+ * @param size The size of the mapping
+ */
+void *
+NvRmPrivChiplibMap( NvRmPhysAddr addr, size_t size );
+
+/**
+ * unmaps a previously mapped pointer from NvRmPrivChiplibMap.
+ *
+ * @param addr The virtual address to unmap
+ */
+void
+NvRmPrivChiplibUnmap( void *addr );
+
+
+#ifdef __cplusplus
+}
+#endif  /* __cplusplus */
+
+#endif
diff --git a/arch/arm/mach-tegra/nvrm/core/common/nvrm_clockids.h b/arch/arm/mach-tegra/nvrm/core/common/nvrm_clockids.h
new file mode 100644
index 000000000000..79364f3f47eb
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/core/common/nvrm_clockids.h
@@ -0,0 +1,86 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/** @file ap15rm_clockids.h
+    Clock List & string names
+*/
+
+/* This is the list of all clock sources available on AP15 and AP20.
+ */
+
+// 32 KHz clock - A.K.A relaxation oscillator.
+NVRM_CLOCK_SOURCE('C', 'l', 'k', 'S', ' ', ' ', ' ', ' ', ClkS)
+// Main clock (crystal or input)
+NVRM_CLOCK_SOURCE('C', 'l', 'k', 'M', ' ', ' ', ' ', ' ', ClkM)
+// Always double the Clock M
+NVRM_CLOCK_SOURCE('C', 'l', 'k', 'D', ' ', ' ', ' ', ' ', ClkD)
+
+// PLL clocks
+NVRM_CLOCK_SOURCE('P', 'l', 'l', 'A', '0', ' ', ' ', ' ', PllA0)
+NVRM_CLOCK_SOURCE('P', 'l', 'l', 'A', '1', ' ', ' ', ' ', PllA1)
+
+NVRM_CLOCK_SOURCE('P', 'l', 'l', 'C', '0', ' ', ' ', ' ', PllC0)
+NVRM_CLOCK_SOURCE('P', 'l', 'l', 'C', '1', ' ', ' ', ' ', PllC1)
+NVRM_CLOCK_SOURCE('P', 'l', 'l', 'D', '0', ' ', ' ', ' ', PllD0)
+NVRM_CLOCK_SOURCE('P', 'l', 'l', 'E', '0', ' ', ' ', ' ', PllE0)
+NVRM_CLOCK_SOURCE('P', 'l', 'l', 'M', '0', ' ', ' ', ' ', PllM0)
+NVRM_CLOCK_SOURCE('P', 'l', 'l', 'M', '1', ' ', ' ', ' ', PllM1)
+
+NVRM_CLOCK_SOURCE('P', 'l', 'l', 'P', '0', ' ', ' ', ' ', PllP0)
+NVRM_CLOCK_SOURCE('P', 'l', 'l', 'P', '1', ' ', ' ', ' ', PllP1)
+NVRM_CLOCK_SOURCE('P', 'l', 'l', 'P', '2', ' ', ' ', ' ', PllP2)
+NVRM_CLOCK_SOURCE('P', 'l', 'l', 'P', '3', ' ', ' ', ' ', PllP3)
+NVRM_CLOCK_SOURCE('P', 'l', 'l', 'P', '4', ' ', ' ', ' ', PllP4)
+NVRM_CLOCK_SOURCE('P', 'l', 'l', 'S', '0', ' ', ' ', ' ', PllS0)
+NVRM_CLOCK_SOURCE('P', 'l', 'l', 'U', '0', ' ', ' ', ' ', PllU0)
+NVRM_CLOCK_SOURCE('P', 'l', 'l', 'X', '0', ' ', ' ', ' ', PllX0)
+
+// External and recovered bit clock sources
+NVRM_CLOCK_SOURCE('E', 'x', 't', 'S', 'p', 'd', 'f', ' ', ExtSpdf)
+NVRM_CLOCK_SOURCE('E', 'x', 't', 'I', '2', 's', '1', ' ', ExtI2s1)
+NVRM_CLOCK_SOURCE('E', 'x', 't', 'I', '2', 's', '2', ' ', ExtI2s2)
+NVRM_CLOCK_SOURCE('E', 'x', 't', 'A', 'c', '9', '7', ' ', ExtAc97)
+NVRM_CLOCK_SOURCE('E', 'x', 't', 'A', 'u', 'd', 'i', '1', ExtAudio1)
+NVRM_CLOCK_SOURCE('E', 'x', 't', 'A', 'u', 'd', 'i', '2', ExtAudio2)
+NVRM_CLOCK_SOURCE('E', 'x', 't', 'V', 'i', ' ', ' ', ' ', ExtVi)
+
+// Audio Clocks
+NVRM_CLOCK_SOURCE('A', 'u', 'd', 'i', 'S', 'y', 'n', 'c', AudioSync)
+NVRM_CLOCK_SOURCE('M', 'p', 'e', 'A', 'u', 'd', 'o', ' ', MpeAudio)
+
+// Internal bus sources
+NVRM_CLOCK_SOURCE('C', 'p', 'u', 'B', 'u', 's', ' ', ' ', CpuBus)
+NVRM_CLOCK_SOURCE('C', 'p', 'u', 'B', 'r', 'd', 'g', ' ', CpuBridge)
+NVRM_CLOCK_SOURCE('S', 'y', 's', 't', 'B', 'u', 's', ' ', SystemBus)
+NVRM_CLOCK_SOURCE('A', 'h', 'B', 'u', 's', ' ', ' ', ' ', Ahb)
+NVRM_CLOCK_SOURCE('A', 'p', 'B', 'u', 's', ' ', ' ', ' ', Apb)
+NVRM_CLOCK_SOURCE('V', 'd', 'e', 'B', 'u', 's', ' ', ' ', Vbus)
diff --git a/arch/arm/mach-tegra/nvrm/core/common/nvrm_clocks.h b/arch/arm/mach-tegra/nvrm/core/common/nvrm_clocks.h
new file mode 100644
index 000000000000..bef73d86bd9d
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/core/common/nvrm_clocks.h
@@ -0,0 +1,1387 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_NVRM_CLOCKS_H
+#define INCLUDED_NVRM_CLOCKS_H
+
+#include "nvrm_clocks_limits_private.h"
+#include "nvrm_module.h"
+#include "nvrm_diag.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif  /* __cplusplus */
+
+#define NVRM_RESET_DELAY            (10)
+#define NVRM_CLOCK_CHANGE_DELAY     (2)
+#define NVRM_VARIABLE_DIVIDER       ((NvU32)-1)
+
+// Fixed HDMI frequencies
+#define NVRM_HDMI_480p_FIXED_FREQ_KHZ (27000)
+#define NVRM_HDMI_720p_FIXED_FREQ_KHZ (74250)
+#define NVRM_HDMI_1080p_FIXED_FREQ_KHZ (148500)
+
+#define NvRmIsFixedHdmiKHz(KHz) \
+    (((KHz) == NVRM_HDMI_480p_FIXED_FREQ_KHZ) || \
+     ((KHz) == NVRM_HDMI_720p_FIXED_FREQ_KHZ) || \
+     ((KHz) == NVRM_HDMI_1080p_FIXED_FREQ_KHZ))
+
+// BR-fixed PLLP output frequency in kHz (override disabled) 
+#define NV_BOOT_PLLP_FIXED_FREQ_KHZ (432000)
+
+// RM-fixed PLLP output frequency in kHz (override enabled)
+#define NVRM_PLLP_FIXED_FREQ_KHZ (216000)
+
+// PLLP1-PLLP4 configurations set by RM during initialization and resume
+// from LP0 state. PLLP1 and PLLP3 settings are never changed. PLLP2 and
+// PLLP4 settings are overwritten according to SoC-specific DVFS policy.
+// PLLPx output frequency = NVRM_PLLP_FIXED_FREQ_KHZ / (1 + setting/2)
+#define NVRM_FIXED_PLLP1_SETTING (13)
+#define NVRM_FIXED_PLLP2_SETTING (7)
+#define NVRM_FIXED_PLLP3_SETTING (4)
+#define NVRM_FIXED_PLLP4_SETTING (2)
+
+/// Guaranteed MIPI PLL Stabilization Delay
+#define NVRM_PLL_MIPI_STABLE_DELAY_US (1000)
+
+/**
+ * MIPI PLL feedback divider N threshold for loop filter control setting:
+ * LFCON = 1 if N is above threshold, and LFCON = 0, otherwise
+ */
+#define NVRM_PLL_MIPI_LFCON_SELECT_N_DIVIDER (600)
+
+/**
+ * MIPI PLL feedback divider N thresholds for charge pump control setting
+ * selection.
+ */
+#define NVRM_PLL_MIPI_CPCON_SELECT_STEPS_N_DIVIDER \
+    0,      /* CPCON = 1 if feedback divider  N = 0 (invalid setting)*/ \
+    50,     /* CPCON = 2 if feedback divider  N <= 50 */ \
+    175,    /* CPCON = 3 if feedback divider  N = ( 50 - 175] */ \
+    300,    /* CPCON = 4 if feedback divider  N = (175 - 300] */ \
+    375,    /* CPCON = 5 if feedback divider  N = (300 - 375] */ \
+    450,    /* CPCON = 6 if feedback divider  N = (375 - 450] */ \
+    525,    /* CPCON = 7 if feedback divider  N = (450 - 525] */ \
+    600,    /* CPCON = 8 if feedback divider  N = (525 - 600] */ \
+    700,    /* CPCON = 9 if feedback divider  N = (600 - 700] */ \
+    800,    /* CPCON = 10 if feedback divider N = (700 - 800] */ \
+    900,    /* CPCON = 11 if feedback divider N = (800 - 900] */ \
+    1000    /* CPCON = 12 if feedback divider N = (900 - 1000] */
+            /* CPCON = 13 if feedback divider N > 1000 (invalid setting) */
+
+/// Guaranteed Low power PLL Stabilization Delay
+#define NVRM_PLL_LP_STABLE_DELAY_US (300)
+
+/**
+ * Low power PLL feedback divider N threshold for charge pump control. For N
+ * values below threshold charge pump control is always set to 1. For N values
+ * above threshold charge pump control setting depends on comparison frequency
+ * as specified in the table below.
+ */
+#define NVRM_PLL_LP_MIN_N_FOR_CPCON_SELECTION (200)
+
+/**
+ * Low power PLL comparison frequency Fcomp = Din/M thresholds for charge pump
+ * control setting selection.
+ */
+#define NVRM_PLL_LP_CPCON_SELECT_STEPS_KHZ \
+    6000,   /* CPCON = 1 if Fin/M >= 6000 kHz (outside valid range)*/ \
+    4000,   /* CPCON = 2 if Fin/M = [4000 - 6000) kHz */ \
+    3000,   /* CPCON = 3 if Fin/M = [3000 - 4000) kHz */ \
+    2000,   /* CPCON = 4 if Fin/M = [2000 - 3000) kHz */ \
+    1750,   /* CPCON = 5 if Fin/M = [1750 - 2000) kHz */ \
+    1500,   /* CPCON = 6 if Fin/M = [1500 - 1750) kHz */ \
+    1250,   /* CPCON = 7 if Fin/M = [1250 - 1500) kHz */ \
+    1000    /* CPCON = 8 if Fin/M = [1000 - 1250) kHz */
+            /* CPCON = 9 if Fin/M < 1000 kHz (outside valid range) */
+
+/// Combines PLL and PLL output divider settings for fixed pre-defined frequency
+typedef struct NvRmPllFixedConfigRec
+{
+    // Output pre-defined frequency
+    NvRmFreqKHz OutputKHz;
+
+    // Interanl PLL dividers settings
+    NvU32 M;
+    NvU32 N;
+    NvU32 P;
+
+    // Exteranl output divider settings
+    // (ignored if there is no output divider)
+    NvU32 D;
+} NvRmPllFixedConfig;
+
+/**
+ * Defines list of supported PLLA configurations (2 entries for 12.2896
+ * frequency that can be either truncated or rounded to KHz). The reference
+ * frequency for PLLA is fixed at 28.8MHz, therefore there is no dependency on
+ * oscillator frequency. Output frequency is divided by PLLA_OUT0 fractional
+ * divider.
+ */
+#define NVRM_PLLA_CONFIGURATIONS \
+    { 11289, 25, 49, 0, 8}, \
+    { 11290, 25, 49, 0, 8}, \
+    { 12000, 24, 50, 0, 8}, \
+    { 12288, 25, 64, 0, 10}, \
+    { 56448, 25, 49, 0, 0}, \
+    { 73728, 25, 64, 0, 0}
+
+// Default audio sync frequency
+#define NVRM_AUDIO_SYNC_KHZ (11289)
+
+/**
+ * Defines PLLU configurations for different oscillator frequencies. Output
+ * frequency is 12MHz for USB with no ULPI support, or 60MHz if null ULPI is
+ * supported, or 480MHz for HS PLL. PLLU_OUT0 does not have output divider.
+ * 
+ */
+#define NVRM_PLLU_AT_12MHZ { 12000, 12, 384, 5, 0}
+#define NVRM_PLLU_AT_13MHZ { 12000, 13, 384, 5, 0}
+#define NVRM_PLLU_AT_19MHZ { 12000,  4,  80, 5, 0}
+#define NVRM_PLLU_AT_26MHZ { 12000, 26, 384, 5, 0}
+
+#define NVRM_PLLU_ULPI_AT_12MHZ { 60000, 12, 240, 2, 0}
+#define NVRM_PLLU_ULPI_AT_13MHZ { 60000, 13, 240, 2, 0}
+#define NVRM_PLLU_ULPI_AT_19MHZ { 60000,  4,  50, 2, 0}
+#define NVRM_PLLU_ULPI_AT_26MHZ { 60000, 26, 240, 2, 0}
+
+#define NVRM_PLLU_HS_AT_12MHZ { 480000, 12, 960, 1, 0}
+#define NVRM_PLLU_HS_AT_13MHZ { 480000, 13, 960, 1, 0}
+#define NVRM_PLLU_HS_AT_19MHZ { 480000,  4, 200, 1, 0}
+#define NVRM_PLLU_HS_AT_26MHZ { 480000, 26, 960, 1, 0}
+
+/**
+ * Defines PLLP configurations for different oscillator frequencies. Output
+ * frequency is always the same. PLLP_OUT0 does not have output divider
+ * 
+ */
+#define NVRM_PLLP_AT_12MHZ { NVRM_PLLP_FIXED_FREQ_KHZ, 12, 432, 1, 0}
+#define NVRM_PLLP_AT_13MHZ { NVRM_PLLP_FIXED_FREQ_KHZ, 13, 432, 1, 0}
+#define NVRM_PLLP_AT_19MHZ { NVRM_PLLP_FIXED_FREQ_KHZ,  4,  90, 1, 0}
+#define NVRM_PLLP_AT_26MHZ { NVRM_PLLP_FIXED_FREQ_KHZ, 26, 432, 1, 0}
+
+/**
+ * Defines PLLD/PLLC 720p/1080i HDMI configurations for different oscillator
+ * frequencies. For both PLLC and PLLD output frequency is fixed as 4 * 74250
+ * = 594000. However, PLLC_OUT0 will be running at this frequency exactly, while
+ * PLLD_OUT0 will be runnig at half frequency 297000 (h/w divide by 2 always). 
+ * This difference in source frequency is will be taken care by Display and
+ * HDMI clock dividers.
+ */
+#define NVRM_PLLHD_AT_12MHZ { 594000, 12, 594, 0, 0}
+#define NVRM_PLLHD_AT_13MHZ { 594000, 13, 594, 0, 0}
+#define NVRM_PLLHD_AT_19MHZ { 594000, 16, 495, 0, 0}
+#define NVRM_PLLHD_AT_26MHZ { 594000, 26, 594, 0, 0}
+
+// Display divider is part of the display module and it is not described
+// in central module clock information table. Hence, need this define.
+#define NVRM_DISPLAY_DIVIDER_MAX (128)
+
+/*****************************************************************************/
+/*****************************************************************************/
+
+/*
+ * Defines module clock state
+ */ 
+typedef enum 
+{
+    // Module clock disable
+    ModuleClockState_Disable = 0, 
+
+    // Module clock enable
+    ModuleClockState_Enable = 1, 
+
+    ModuleClockState_Force32 = 0x7FFFFFFF
+} ModuleClockState;
+
+
+typedef enum
+{
+    NvRmClockSource_Invalid = 0,
+#define NVRM_CLOCK_SOURCE(A, B, C, D, E, F, G, H, x) NvRmClockSource_##x,
+#include "nvrm_clockids.h"
+#undef NVRM_CLOCK_SOURCE
+    NvRmClockSource_Num,
+    NvRmClockSource_Force32 = 0x7FFFFFFF
+} NvRmClockSource;
+
+
+typedef enum
+{
+    // Clock source with fixed frequency (e.g., oscillator, not configurable
+    // PLL, external clock, etc.)
+    NvRmClockSourceType_Fixed = 1,
+
+    // Clock source from configurable PLL
+    NvRmClockSourceType_Pll,
+
+    // Secondary clock source derived from oscillator, PLL or other secondary
+    // source via clock divider
+    NvRmClockSourceType_Divider,
+
+    // Core clock source derived from several input sources via 2-stage selector
+    // and rational super-clock divider
+    NvRmClockSourceType_Core,
+
+    // Selector clock source derived from several input sources via 1-stage selector
+    // and optional clock frequency doubler
+    NvRmClockSourceType_Selector,
+
+    NvRmClockSourceType_Num,
+    NvRmClockSourceType_Force32 = 0x7FFFFFFF
+} NvRmClockSourceType;
+
+typedef enum
+{
+    // No divider
+    NvRmClockDivider_None = 1,
+
+    // Integer divider by N
+    NvRmClockDivider_Integer,
+
+    // Integer divider by (N + 1)
+    NvRmClockDivider_Integer_1,
+
+    // Fractional divider by (N/2 + 1)
+    NvRmClockDivider_Fractional_2,
+
+    // Skipping N clocks out of every 16, i.e fout = fin * (16-N)/16
+    // (= to Keeper16 with 1-complemented settings N = 15 - M)
+    NvRmClockDivider_Skipper16,
+
+    // Keep M+1 clocks out of every 16, fout = fin * (M+1)/16
+    // (= to Skipper16 with 1-complemented setting M = 15 - N)
+    NvRmClockDivider_Keeper16,
+
+    // Integer divider by (N + 2) = cascade Fractional : Fixed 1/2
+    NvRmClockDivider_Integer_2,
+
+    NvRmClockDivider_Num,
+    NvRmClockDivider_Force32 = 0x7FFFFFFF
+} NvRmClockDivider;
+
+typedef enum
+{
+    // AP10 PLLs (PLLC and PLLA)
+    NvRmPllType_AP10 = 1,
+
+    // MIPI PLLs (PLLD and PLLU on AP15)
+    NvRmPllType_MIPI,
+
+    // Low Power PLLs (PLLA, PLLC, PLLM, PLLP, PLLX, PLLS) 
+    NvRmPllType_LP,
+
+    // AP20 USB HS PLL (PLLU on AP20) 
+    NvRmPllType_UHS,
+
+    NvRmPllType_Num,
+    NvRmPllType_Force32 = 0x7FFFFFFF
+} NvRmPllType;
+
+/**
+ * Defines PLL configuration flags which are applicable for some PLLs.
+ * Multiple flags can be OR'ed and passed to the NvRmPrivAp15PllSet() API.
+ */
+typedef enum
+{
+    /// Use Slow Mode output for MIPI PLL
+    NvRmPllConfigFlags_SlowMode = 0x1,
+
+    /// Use Fast Mode output for MIPI PLL
+    NvRmPllConfigFlags_FastMode = 0x2,
+
+    /// Enable differential outputs for MIPI PLL
+    NvRmPllConfigFlags_DiffClkEnable = 0x4,
+
+    /// Disable differential outputs for MIPI PLL
+    NvRmPllConfigFlags_DiffClkDisable = 0x8,
+
+    /// Override fixed configuration for PLLP
+    NvRmPllConfigFlags_Override = 0x10,
+
+    /// Enable duty cycle correction for LP PLL
+    NvRmPllConfigFlags_DccEnable = 0x20,
+
+    /// Disable duty cycle correction for LP PLL
+    NvRmPllConfigFlags_DccDisable = 0x40,
+
+    NvRmPllConfigFlags_Num,
+    NvRmPllConfigFlags_Force32 = 0x7FFFFFFF
+} NvRmPllConfigFlags;
+
+/*****************************************************************************/
+
+// Holds source selection and divider configuration for module clock as well
+// as module reset information.
+typedef struct NvRmModuleClockInfoRec
+{
+    NvRmModuleID Module;
+    NvU32 Instance;
+    NvU32 SubClockId;
+
+    NvRmClockSource Sources[NvRmClockSource_Num];
+    NvRmClockDivider Divider;
+
+    NvU32 ClkSourceOffset;
+
+    NvU32 SourceFieldMask;
+    NvU32 SourceFieldShift;
+
+    NvU32 DivisorFieldMask;
+    NvU32 DivisorFieldShift;
+
+    NvU32 ClkEnableOffset;
+    NvU32 ClkEnableField;
+    NvU32 ClkResetOffset;
+    NvU32 ClkResetField;
+
+    NvRmDiagModuleID DiagModuleID;
+}NvRmModuleClockInfo;
+
+typedef struct NvRmModuleClockStateRec
+{
+    NvU32 Divider;
+    NvU32 SourceClock;
+    NvRmFreqKHz actual_freq;
+    NvU32 refCount;
+    NvU32 Vstep;
+    NvBool Vscale;
+    NvBool FirstReference;
+#if NVRM_DIAG_LOCK_SUPPORTED
+    NvBool DiagLock;    // once locked, can not be changed
+#endif
+} NvRmModuleClockState;
+
+/*****************************************************************************/
+
+// Holds configuration information about the fixed clock source that can be
+// only enabled/disabled (e.g, oscillator, external clock, fixed frequency PLL).
+typedef struct NvRmFixedClockInfoRec
+{
+    // Source ID
+    NvRmClockSource SourceId;
+
+    // Fixed source input (must be fixed source as well). For primary sources
+    // this field is set to NvRmClockSource_Invalid
+    NvRmClockSource InputId;
+
+    // Enable register offset and field
+    NvU32 ClkEnableOffset;
+    NvU32 ClkEnableField;
+} NvRmFixedClockInfo;
+
+
+// Holds configuration information about configurable PLL 
+typedef struct NvRmPllClockInfoRec
+{
+    // PLL output ID
+    NvRmClockSource SourceId;
+
+    // PLL reference clock ID
+    NvRmClockSource InputId;
+
+    // PLL type
+    NvRmPllType PllType;
+
+    // Ofsets of PLL registers
+    NvU32 PllBaseOffset;
+    NvU32 PllMiscOffset;
+
+    // PLL VCO range
+    NvRmFreqKHz PllVcoMin;
+    NvRmFreqKHz PllVcoMax;
+} NvRmPllClockInfo;
+
+
+// Holds configuration information about secondary clock source derived
+// from one input source via clock divider
+typedef struct NvRmDividerClockInfoRec
+{
+    // Divider output clock ID
+    NvRmClockSource SourceId;
+
+    // Divider input clock ID
+    NvRmClockSource InputId;
+
+    // Type of the divider
+    NvRmClockDivider Divider;
+
+    // Divider control register offset
+    NvU32 ClkControlOffset;
+
+    // Clock rate parameter field;
+    // ignored for divider with fixed setting
+    NvU32 ClkRateFieldMask;
+    NvU32 ClkRateFieldShift;
+
+    // Divider control field
+    NvU32 ClkControlField;
+    NvU32 ClkEnableSettings;
+    NvU32 ClkDisableSettings;
+
+    // Fixed divider rate parameter setting;
+    // NVRM_VARIABLE_DIVIDER if divider is variable
+    NvU32 FixedRateSetting;
+} NvRmDividerClockInfo;
+
+
+typedef enum
+{
+    // The enumeartion values must not be changed for Mode(ModeField) formula
+    // below to work properly 
+    NvRmCoreClockMode_Suspend = 0,
+    NvRmCoreClockMode_Idle = 1,
+    NvRmCoreClockMode_Run = 2,
+    NvRmCoreClockMode_Irq = 3,
+    NvRmCoreClockMode_Fiq = 4,
+
+    NvRmCoreClockMode_Num,
+    NvRmCoreClockMode_Force32 = 0x7FFFFFFF
+} NvRmCoreClockMode;
+
+// Holds configuration information about core clock source derived from several
+// input sources via 2-stage selector and rational super-clock divider  
+typedef struct NvRmCoreClockInfoRec
+{
+    // Core clock ID
+    NvRmClockSource SourceId;
+
+    // Super clock input sources, same in each mode
+    NvRmClockSource Sources[NvRmClockSource_Num];
+
+    // Offset of the core clock input source selector register
+    NvU32 SelectorOffset;
+
+    // Clock mode field: 
+    // 0 => NvRmCoreClockMode_Suspend (0)
+    // 1 => NvRmCoreClockMode_Idle (1)
+    // 2-3 => NvRmCoreClockMode_Run (2)
+    // 4-7 => NvRmCoreClockMode_Irq (3)
+    // 8-15 => NvRmCoreClockMode_Fiq (4)
+    // Mode = (ModeField == 0) ? NvRmCoreClockMode_Suspend : (1 + LOG2(ModeField))
+    NvU32 ModeFieldMask;
+    NvU32 ModeFieldShift;
+
+    // Sorce selection fileds for each mode
+    NvU32 SourceFieldMasks[NvRmCoreClockMode_Num];
+    NvU32 SourceFieldShifts[NvRmCoreClockMode_Num];
+
+    // Offset of the divider register
+    NvU32 DividerOffset;
+
+    // Divider enable field (divider is by-passed if disabled)
+    // Fout = Fin * (Dividend + 1) / (Divisor + 1)
+    NvU32 DividerEnableFiledMask;
+    NvU32 DividerEnableFiledShift;
+
+    // Dividend field
+    NvU32 DividendFieldMask;
+    NvU32 DividendFieldShift;
+    NvU32 DividendFieldSize;
+
+    // Divisor field
+    NvU32 DivisorFieldMask;
+    NvU32 DivisorFieldShift;
+    NvU32 DivisorFieldSize;
+} NvRmCoreClockInfo;
+
+// Holds configuration information about secondary clock source derived from
+// several input sources via 1-stage selector and clock frequency doubler 
+typedef struct NvRmSelectorClockInfoRec
+{
+    // Selector output clock ID
+    NvRmClockSource SourceId;
+
+    // Selector input sources
+    NvRmClockSource Sources[NvRmClockSource_Num];
+
+    // Offset of the input source selector register
+    NvU32 SelectorOffset;
+
+    // Source selection field
+    NvU32 SourceFieldMask;
+    NvU32 SourceFieldShift;
+
+    // Doubler control (optional - set field to 0, if no doubler)
+    NvU32 DoublerEnableOffset;
+    NvU32 DoublerEnableField;
+} NvRmSelectorClockInfo;
+
+// Holds information on system bus clock dividers
+typedef struct NvRmSystemBusComplexInfoRec
+{
+    // Offset of the Bus Rates control register
+    NvU32 BusRateOffset;
+
+    // Combined bus clocks disable fields (1 = disable)
+    NvU32 BusClockDisableFields;
+
+    // V-pipe vclk divider field: vclk rate = system core rate * (n+1) /16
+    // All fields are 0, if VDE (V-pipe) clock is decoupled from the System bus
+    NvU32 VclkDividendFieldMask;
+    NvU32 VclkDividendFieldShift;
+    NvU32 VclkDividendFieldSize;
+
+    // AHB hclk divider field: hclk rate = system core rate / (n+1)
+    NvU32 HclkDivisorFieldMask;
+    NvU32 HclkDivisorFieldShift;
+    NvU32 HclkDivisorFieldSize;
+
+    // APB pclk divider field: pclk rate = hclk rate / (n+1)
+    NvU32 PclkDivisorFieldMask;
+    NvU32 PclkDivisorFieldShift;
+    NvU32 PclkDivisorFieldSize;
+} NvRmSystemBusComplexInfo;
+
+/*****************************************************************************/
+
+typedef union
+{
+    NvRmFixedClockInfo* pFixed;
+    NvRmPllClockInfo* pPll;
+    NvRmDividerClockInfo* pDivider;
+    NvRmCoreClockInfo* pCore;
+    NvRmSelectorClockInfo* pSelector;
+} NvRmClockSourceInfoPtr;
+
+// Abstarcts clock source information for different source types.
+typedef struct NvRmClockSourceInfoRec
+{
+    // Clock source ID
+    NvRmClockSource SourceId;
+
+    // Clock source type
+    NvRmClockSourceType SourceType;
+
+    // Pointer to clock source information
+    NvRmClockSourceInfoPtr pInfo;
+} NvRmClockSourceInfo;
+
+/*****************************************************************************/
+
+// Holds PLL references
+typedef struct NvRmPllReferenceRec
+{
+    // PLL ID
+    NvRmClockSource SourceId;
+
+    // Stop PLL during low power state flag (reported by DFS to kernel)
+    NvRmDfsStatusFlags StopFlag;
+
+    // Reference counter
+    NvU32 ReferenceCnt;
+
+    // Module clocks reference array
+    NvBool* AttachedModules; 
+
+    // External clock attachment reference count (debugging only)
+    NvU32 ExternalClockRefCnt;
+} NvRmPllReference;
+
+/**
+ * Holds DFS clock source configuration record
+ */
+typedef struct NvRmDfsSourceRec
+{
+    // DFS Clock Source Id
+    NvRmClockSource SourceId;
+
+    // DFS Clock Source frequency
+    // CPU and System/AVP clock domains: this field holds input frequency
+    // of core super-divider (from base PLL output or secondary PLL divider) 
+    // V-pipe domain (if it is decoupled from System bus): this field holds
+    // output frequency of VDE module divider = VDE domain frequency
+    // EMC domain: this field holds EMC2x frequency specified in selected
+    // entry in EMC configuration table
+    NvRmFreqKHz SourceKHz;
+
+    // DFS Clock Source divider setting
+    // CPU and System/AVP clock domains: this field holds settings for
+    // secondary PLL divider between base PLL output and super-divider
+    // V-pipe domain (if it is decoupled from System bus): this field holds
+    // settings for VDE module clock divider
+    // EMC domain: this field holds index into EMC configuration table
+    NvU32 DividerSetting;
+
+    // Minimum Voltage required to run DFS domain from this source 
+    NvRmMilliVolts MinMv;
+} NvRmDfsSource;
+
+/**
+ * Combines frequencies for DFS controlled clock domains
+ */
+typedef struct NvRmDfsFrequenciesRec
+{
+    NvRmFreqKHz Domains[NvRmDfsClockId_Num];
+} NvRmDfsFrequencies;
+
+/*****************************************************************************/
+
+/*
+ * Defines execution platforms
+ */
+typedef enum
+{
+    // SoC Chip
+    ExecPlatform_Soc = 0x1,
+
+    // FPGA
+    ExecPlatform_Fpga,
+
+    // QuickTurn
+    ExecPlatform_Qt,
+
+    // Simulation
+    ExecPlatform_Sim,
+
+    ExecPlatform_Force32 = 0x7FFFFFFF
+} ExecPlatform;
+
+/*****************************************************************************/
+/*****************************************************************************/
+
+/**
+ * Determines execution platform.
+ * 
+ * @param hRmDeviceHandle The RM device handle.
+ * 
+ * @return Execution platform ID.
+ */
+ExecPlatform NvRmPrivGetExecPlatform(NvRmDeviceHandle hRmDeviceHandle);
+
+/**
+ * Initializes clock sources frequencies.
+ * 
+ * @param hRmDevice The RM device handle. 
+ * @param pClockSourceFreq A pointer to the source frequencies table to be
+ *  filled in by this function.
+ */
+void
+NvRmPrivClockSourceFreqInit(
+    NvRmDeviceHandle hRmDevice,
+    NvU32* pClockSourceFreq);
+
+/**
+ * Initializes bus clocks.
+ * 
+ * @param hRmDevice The RM device handle. 
+ * @param SystemFreq The system bus frequency
+ */
+void
+NvRmPrivBusClockInit(NvRmDeviceHandle hRmDevice, NvRmFreqKHz SystemFreq);
+
+/**
+ * Initializes PLL power rails and synchronizes PMU ref count
+ * 
+ * @param hRmDevice The RM device handle.
+ */
+void
+NvRmPrivPllRailsInit(NvRmDeviceHandle hRmDevice);
+
+/**
+ * Set nominal core and DDR I/O voltages and boosts core and memory
+ * clocks to maximum.
+ * 
+ * @param hRmDevice The RM device handle.
+ */
+void
+NvRmPrivBoostClocks(NvRmDeviceHandle hRmDevice);
+
+/**
+ * Enables/disables module clock (private utility directly accessing h/w,
+ * no ref counting).
+ * 
+ * @param hDevice The RM device handle.
+ * @param ModuleId Combined module ID and instance of the target module.
+ * @param ClockState Target clock state.
+ */
+void
+NvRmPrivEnableModuleClock(
+    NvRmDeviceHandle hRmDevice,
+    NvRmModuleID ModuleId,
+    ModuleClockState ClockState);
+
+/**
+ * Gets currently selected clock source for the specified core clock.
+ * 
+ * @param hRmDevice The RM device handle.
+ * @param pCinfo Pointer to the core clock description structure.
+ * 
+ * @return Core clock source ID.
+ */
+NvRmClockSource
+NvRmPrivCoreClockSourceGet(
+    NvRmDeviceHandle hRmDevice,
+    const NvRmCoreClockInfo* pCinfo);
+
+/**
+ * Gets core clock frequency.
+ * 
+ * @param hRmDevice The RM device handle.
+ * @param pCinfo Pointer to the core clock description structure.
+ * 
+ * @return Core clock frequency in kHz.
+ */
+NvRmFreqKHz
+NvRmPrivCoreClockFreqGet(
+    NvRmDeviceHandle hRmDevice,
+    const NvRmCoreClockInfo* pCinfo);
+
+/**
+ * Finds the slection index of the specified core clock source.
+ * 
+ * @param pCinfo Pointer to the core clock description structure.
+ * @param SourceId Id of the clock source to find index of 
+ * @param pSourceIndex Output storage pointer for the clock source index;
+ *  returns NvRmClockSource_Num if specified source Id can not be found
+ *  in the core clock descriptor.
+ */
+void
+NvRmPrivCoreClockSourceIndexFind(
+    const NvRmCoreClockInfo* pCinfo,
+    NvRmClockSource SourceId,
+    NvU32* pSourceIndex);
+
+/**
+ * Finds the best source for the target core clock frequency.
+ * The best source is a valid source with frequency above and closest
+ * to the target; if such source does not exist, the best source is a
+ * valid source below and closest to the target. If no valid source
+ * exists (i.e., all available find source are above maximum domain
+ * frequency)
+ * 
+ * @param pCinfo Pointer to the core clock description structure.
+ * @param MaxFreq Upper limit for source frequency in kHz
+ * @param Target frequency in kHz
+ * @param pSourceFreq Output storage pointer for the best source frequency;
+ *  returns 0 if no valid source below upper limit was found
+ * @param pSourceIndex Output storage pointer for the best source index in
+ *  core clock descriptor; returns NvRmClockSource_Num if no valid source
+ *  was found
+ */
+void
+NvRmPrivCoreClockBestSourceFind(
+    const NvRmCoreClockInfo* pCinfo,
+    NvRmFreqKHz MaxFreq,
+    NvRmFreqKHz TargetFreq,
+    NvRmFreqKHz* pSourceFreq,
+    NvU32* pSourceIndex);
+
+/**
+ * Sets "as is" specified core clock configuration.
+ * 
+ * @param hRmDevice The RM device handle.
+ * @param pCinfo Pointer to the core clock description structure.
+ * @param SourceId The ID of the clock source to drive core clock.
+ * @param m Superdivider dividend value.
+ * @param n Superdivider divisor value.
+ * 
+ * There is no error return status for this API call.
+ * If specified source can not be selected(not present 
+ * in core clock descriptor), asserts are encountered.
+ */
+void
+NvRmPrivCoreClockSet(
+    NvRmDeviceHandle hRmDevice,
+    const NvRmCoreClockInfo* pCinfo,
+    NvRmClockSource SourceId,
+    NvU32 m,
+    NvU32 n);
+
+/**
+ * Configures core clock frequency.
+ * 
+ * @param hRmDevice The RM device handle.
+ * @param pCinfo Pointer to the core clock description structure.
+ * @param MaxFreq Upper limit for clock source frequency in kHz.
+ * @param pFreq Pointer to the target frequency in kHz on entry; updated
+ *  with actual clock frequencies on exit.
+ * @param pSourceId Pointer to the target clock source ID on entry; if set
+ *  to NvRmClockSource_Num, no source target is specified, and the best source
+ *  for the target frequency is selected automatically. On exit, points to the
+ *  actually selected source ID.
+ * 
+ * @retval NvSuccess if core clock was configured successfully.
+ * @retval NvError_NotSupported if the specified target source is invalid or
+ *  no target source specified and no valid source was found. 
+ */
+NvError
+NvRmPrivCoreClockConfigure(
+    NvRmDeviceHandle hRmDevice,
+    const NvRmCoreClockInfo* pCinfo,
+    NvRmFreqKHz MaxFreq,
+    NvRmFreqKHz* pFreq,
+    NvRmClockSource* pSourceId);
+
+/**
+ * Gets bus clocks frequencies.
+ * 
+ * @param hRmDevice The RM device handle.
+ * @param SystemFreq System core clock frequency in kHz.
+ * @param pVclkFreq Output storage pointer for V-bus clock frequency in kHz.
+ *  If VDE clock is decoupled from the System bus, 0kHz will be returned.
+ * @param pHclkFreq Output storage pointer for AHB clock frequency in kHz.
+ * @param pPclkFreq Output storage pointer for APB clock frequency in kHz.
+ */
+void
+NvRmPrivBusClockFreqGet(
+    NvRmDeviceHandle hRmDevice,
+    NvRmFreqKHz SystemFreq,
+    NvRmFreqKHz* pVclkFreq,
+    NvRmFreqKHz* pHclkFreq,
+    NvRmFreqKHz* pPclkFreq);
+
+/**
+ * Configures bus clocks frequencies.
+ * 
+ * @param hRmDevice The RM device handle.
+ * @param SystemFreq System core clock frequency in kHz.
+ * @param pVclkFreq Pointer to the target V-bus clock frequency in kHz
+ *  on entry, updated with actually set frequency on exit. If VDE clock
+ *  is decoupled from the System bus, 0kHz will be returned.
+ * @param pHclkFreq Pointer to the target AHB clock frequency in kHz
+ *  on entry, updated with actually set frequency on exit.
+ * @param pPclkFreq Pointer to the target APB clock frequency in kHz
+ *  on entry, updated with actually set frequency on exit.
+ * @param PclkMaxFreq APB clock maximum frequency; APB is the only clock
+ *  in the system complex that may have different (lower) maximum limit. 
+ */
+void
+NvRmPrivBusClockFreqSet(
+    NvRmDeviceHandle hRmDevice,
+    NvRmFreqKHz SystemFreq,
+    NvRmFreqKHz* pVclkFreq,
+    NvRmFreqKHz* pHclkFreq,
+    NvRmFreqKHz* pPclkFreq,
+    NvRmFreqKHz PclkMaxFreq);
+
+/**
+ * Reconfigures PLLX0 to specified frequency (and switches CPU to back-up
+ * PLLP0 if PLLX0 is currently used as CPU source).
+ * 
+ * @param hRmDevice The RM device handle.
+ * @param TargetFreq New PLLX0 output frequency.
+ */
+void
+NvRmPrivReConfigurePllX(
+    NvRmDeviceHandle hRmDevice,
+    NvRmFreqKHz TargetFreq);
+
+/**
+ * Reconfigures PLLC0 to specified frequency (switches to PLLP0 all modules
+ * that use PLLC0 as a source, and then restores source configuration back).
+ * Should be called only when core voltage is set at nominal.
+ * 
+ * @param hRmDevice The RM device handle.
+ * @param TargetFreq New PLLC0 output frequency.
+ */
+void
+NvRmPrivReConfigurePllC(
+    NvRmDeviceHandle hRmDevice,
+    NvRmFreqKHz TargetFreq);
+
+/**
+ * Gets maximum PLLC0 frequency set as a default target, when there are no
+ * fixed frequency requirements.
+ * 
+ * @param hRmDevice The RM device handle.
+ * 
+ * @return Maximum target for PLLC0 frequency.
+ */
+NvRmFreqKHz NvRmPrivGetMaxFreqPllC(NvRmDeviceHandle hRmDevice);
+
+/**
+ * Configures PLLC0 at maximum frequency, when there are no fixed frequency
+ * requirements. Should be called only when core voltage is set at nominal.
+ * 
+ * @param hRmDevice The RM device handle.
+ * 
+ * @return Maximum target for PLLC0 frequency.
+ */
+void NvRmPrivBoostPllC(NvRmDeviceHandle hRmDevice);
+
+/**
+ * Updates PLL frequency entry in the clock source table.
+ * 
+ * @param hRmDevice The RM device handle.
+ * @param pCinfo Pointer to the PLL description structure.
+ */
+void
+NvRmPrivPllFreqUpdate(
+    NvRmDeviceHandle hRmDevice,
+    const NvRmPllClockInfo* pCinfo);
+
+/**
+ * Updates divider frequency entry in the clock source table.
+ * 
+ * @param hRmDevice The RM device handle.
+ * @param pCinfo Pointer to the divider clock description structure.
+ */
+void
+NvRmPrivDividerFreqUpdate(
+    NvRmDeviceHandle hRmDevice,
+    const NvRmDividerClockInfo* pCinfo);
+
+/**
+ * Sets "as is" specified divider parmeter.
+ * 
+ * @param hRmDevice The RM device handle.
+ * @param pCinfo Pointer to the divider clock description structure.
+ * @param setting Divider setting
+ */
+void
+NvRmPrivDividerSet(
+    NvRmDeviceHandle hRmDevice,
+    const NvRmDividerClockInfo* pCinfo,
+    NvU32 setting);
+
+/**
+ * Gets divider output frequency.
+ * 
+ * @param hRmDevice The RM device handle.
+ * @param pCinfo Pointer to the divider clock description structure.
+ * 
+ * @return Divider output frequency in kHz; zero if divider itself or
+ *  divider's input clock is disabled.
+ */
+NvRmFreqKHz
+NvRmPrivDividerFreqGet(
+    NvRmDeviceHandle hRmDevice,
+    const NvRmDividerClockInfo* pCinfo);
+
+/**
+ * Finds minimum divider output frequency, which is above the specified
+ *  target frequency.
+ * 
+ * @param DividerType Divider type (only fractional dividers for now).
+ * @param pCinfo SourceKHz Divider source (input) frequency in kHz.
+ * @param MaxKHz Output divider frequency upper limit. Target frequency must
+ *  be below this limit. If no frequency above the target but within the limit
+ *  can be found, then maximum frequency within the limit is returned.
+ * @param pTargetKHz A pointer to the divider output frequency. On entry
+ *  specifies target; on exit - found frequency.  
+ * 
+ * @return Divider setting to get found frequency from the given source.
+ */
+NvU32
+NvRmPrivFindFreqMinAbove(
+    NvRmClockDivider DividerType,
+    NvRmFreqKHz SourceKHz,
+    NvRmFreqKHz MaxKHz,
+    NvRmFreqKHz* pTargetKHz);
+
+/**
+ * Finds maximum divider output frequency, which is below the specified
+ *  target frequency.
+ * 
+ * @param DividerType Divider type (only fractional dividers for now).
+ * @param pCinfo SourceKHz Divider source (input) frequency in kHz.
+ * @param MaxKHz Output divider frequency upper limit. Target frequency must
+ *  be below this limit.
+ * @param pTargetKHz A pointer to the divider output frequency. On entry
+ *  specifies target; on exit - found frequency.  
+ * 
+ * @return Divider setting to get found frequency from the given source.
+ */
+NvU32
+NvRmPrivFindFreqMaxBelow(
+    NvRmClockDivider DividerType,
+    NvRmFreqKHz SourceKHz,
+    NvRmFreqKHz MaxKHz,
+    NvRmFreqKHz* pTargetKHz);
+
+/**
+ * Sets "as is" specified slector clock configuration.
+ * 
+ * @param hRmDevice The RM device handle.
+ * @param pCinfo Pointer to the selector clock description structure.
+ * @param SourceId The ID of the input clock source to select.
+ * @param Double If true, enable output doubler. If false, disable
+ *  output doubler.
+ * 
+ * There is no error return status for this API call.
+ * If specified source can not be selected(not present 
+ * in core clock descriptor), asserts are encountered.
+ */
+void
+NvRmPrivSelectorClockSet(
+    NvRmDeviceHandle hRmDevice,
+    const NvRmSelectorClockInfo* pCinfo,
+    NvRmClockSource SourceId,
+    NvBool Double);
+
+/**
+ * Parses clock sources configuration table of the given type.
+ * 
+ * @param pDst The pointer to the list of the clock source records the results
+ *  of parsing are to be stored in. The records in this list are arranged in
+ *  the order of source IDs.
+ * @param DestinationTableSize Maximum number of sources that can be recorded.
+ * @param The clock source configuration table to be parsed.
+ * @param SourceTableSize Number of records to be parsed.
+ * @param SourceType The type of source records to be parsed.
+ */
+void
+NvRmPrivParseClockSources(
+    NvRmClockSourceInfo* pDst,
+    NvU32 DestinationTableSize,
+    NvRmClockSourceInfoPtr Src,
+    NvU32 SourceTableSize,
+    NvRmClockSourceType SourceType);
+
+/**
+ * Gets pointer to the given clock source descriptor.
+ * 
+ * @param id The targeted clock source ID.
+ * 
+ * @return A pointer to the specified clock source descriptor.
+ *  NULL is returned, if the target clock source is not valid.
+ */
+NvRmClockSourceInfo* NvRmPrivGetClockSourceHandle(NvRmClockSource id);
+
+/**
+ * Gets given clock source frequency,
+ * 
+ * @param id The targeted clock source ID.
+ * 
+ * @return Clock source frequency in KHz.
+ */
+NvRmFreqKHz NvRmPrivGetClockSourceFreq(NvRmClockSource id);
+
+/**
+ * Verifies if the specified clock source is currently selected
+ * by the specified module.
+ * 
+ * @param hRmDevice The RM device handle.
+ * @param SourceId The clock source ID to be verified. 
+ * @param ModuleId The combined module id and instance of the module in question.
+ * 
+ * @return True if specified clock source is selected by the module;
+ *  False returned, otherwise.
+ */
+NvBool
+NvRmPrivIsSourceSelectedByModule(
+    NvRmDeviceHandle hRmDevice,
+    NvRmClockSource SourceId,
+    NvRmModuleID ModuleId);
+
+/**
+ * Verifies if specified frequency range is reachable from the given
+ *  clock source. 
+ * 
+ * @param SourceFreq Clock source frequency in KHz.
+ * @param MinFreq Frequency range low boundary in KHz. 
+ * @param MaxFreq Frequency range high boundary in KHz.
+ * @param MaxDivisor Maximum possible source clock divisor.
+ * 
+ * @return True, if whole divisor can be found so that divided source
+ *  frequency is within the range boundaries; False, otherwise.
+ */
+NvBool
+NvRmIsFreqRangeReachable(
+    NvRmFreqKHz SourceFreq,
+    NvRmFreqKHz MinFreq,
+    NvRmFreqKHz MaxFreq,
+    NvU32 MaxDivisor);
+
+/**
+ * Reports if clock/voltage diagnostic is in progress for the specified module.
+ * 
+ * @param ModuleId The combined module id and instance of the module in question.
+ *  If set to NvRmModuleID_Invalid reports if diagnostic is in progress for any
+ *  module.
+ * 
+ * @return True, if clock/voltage diagnostic is in progress; False, otherwise.
+ */
+NvBool NvRmPrivIsDiagMode(NvRmModuleID ModuleId);
+
+/**
+ * Gets clock frequency limits for the specified SoC module.
+ * 
+ * @param ModuleId The targeted module ID.
+ * 
+ * @return The pointer to the clock limts structure for the given module ID.
+ */
+const NvRmModuleClockLimits* NvRmPrivGetSocClockLimits(NvRmModuleID Module);
+
+/** 
+ * Locks/Unclocks acces to shared PLL
+ */
+void NvRmPrivLockSharedPll(void);
+void NvRmPrivUnlockSharedPll(void);
+
+/**
+ * Locks/Unclocks acces to module clock state
+ */
+void NvRmPrivLockModuleClockState(void);
+void NvRmPrivUnlockModuleClockState(void);
+
+/** 
+ * Enable/Disable the clock source for the module. 
+ *
+ * @param hRmDevice The RM device handle.
+ * @param ModuleId Module ID and instace information.
+ * @param enbale Should the clock source be enabled or disabled.
+ */
+void
+NvRmPrivConfigureClockSource(
+        NvRmDeviceHandle hRmDevice, 
+        NvRmModuleID ModuleId, 
+        NvBool enable);
+
+/** 
+ * Gets pointers to clock descriptor and clock state for the given module.
+ *
+ * @param hDevice The RM device handle.
+ * @param ModuleId Module ID and instance information.
+ * @param CinfoOut A pointer to a variable that this function sets to the
+ *  clock descriptor pointer.
+ * @param StateOut A pointer to a variable that this function sets to the
+ *  clock state pointer.
+ * 
+ * @retval NvSuccess if busy request completed successfully.
+ * @retval NvError_NotSupported if no clock descriptor for the given module.
+ * @retval NvError_ModuleNotPresent if the given module is not listed in
+ *  relocation table.
+ */
+NvError
+NvRmPrivGetClockState(
+    NvRmDeviceHandle hDevice,
+    NvRmModuleID ModuleId,
+    NvRmModuleClockInfo** CinfoOut,
+    NvRmModuleClockState** StateOut);
+
+/**
+ * Updates memory controller clock source reference counts.
+ * 
+ * @param hDevice The RM device handle.
+ * @param pCinfo Pointer to the memory controller clock descriptor.
+ * @param pCstate Pointer to the memory controller clock state.
+ */
+void
+NvRmPrivMemoryClockReAttach(
+    NvRmDeviceHandle hDevice,
+    const NvRmModuleClockInfo* pCinfo,
+    const NvRmModuleClockState* pCstate);
+
+/**
+ * Updates generic module clock source reference counts.
+ * 
+ * @param hRmDevice The RM device handle.
+ * @param pCinfo Pointer to the targeted module clock descriptor.
+ * @param pCstate Pointer to the targeted module clock state.
+ */
+void
+NvRmPrivModuleClockReAttach(
+    NvRmDeviceHandle hRmDevice,
+    const NvRmModuleClockInfo* cinfo,
+    const NvRmModuleClockState* state);
+
+/**
+ * Updates external clock source references.
+ * 
+ * @param hDevice The RM device handle.
+ * @param SourceId The external clock source ID.
+ * @param Enable NV_TRUE if external clock is enabled;
+ *  NV_FALSE if external clock is disabled.
+ */
+void
+NvRmPrivExternalClockAttach( 
+    NvRmDeviceHandle hDevice,
+    NvRmClockSource SourceId,
+    NvBool Enable);
+
+/**
+ * Updates PLL attachment reference count and PLL stop flag in the storage
+ *  shared by RM and NV boot loader.
+ * 
+ * @param hRmDeviceHandle The RM device handle.
+ * @param pPllRef Pointer to the PLL references record.
+ * @param Increment If NV_TRUE, increment PLL reference count,
+ *  if NV_FALSE, decrement PLL reference count.
+ */
+void
+NvRmPrivPllRefUpdate(
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvRmPllReference* pPllRef,
+    NvBool Increment);
+
+/**
+ * Verifies if the targeted module is prohibited to use the specified clock
+ *  source per clock manager policy.
+ * 
+ * @param hRmDevice The RM device handle.
+ * @param Module Target module ID.
+ * @param SourceId Clock source ID.
+ * 
+ * @return NV_TRUE if the targeted module is prohibited to use the specified
+ *  clock source; NV_FALSE if the targeted module can use the specified clock
+ *  source.
+ */
+NvBool
+NvRmPrivIsSourceProtected(
+    NvRmDeviceHandle hRmDevice,
+    NvRmModuleID Module,
+    NvRmClockSource SourceId);
+
+/**
+ * Gets maximum avilable clock source frequency for the specified module
+ *  per clock manager policy.
+ * 
+ * @param hRmDevice The RM device handle.
+ * @param pCinfo Pointer to the targeted module clock descriptor.
+ * 
+ * @return Source frequency in kHz.
+ */
+NvRmFreqKHz
+NvRmPrivModuleGetMaxSrcKHz(
+    NvRmDeviceHandle hRmDevice,
+    const NvRmModuleClockInfo* pCinfo);
+
+/**
+ * Similar to the Rm pulbic Module reset API, but have the option of either
+ * pulsing or keeping the reset line active.
+ *
+ * @param hold  if NV_TRUE keep the asserting the reset. If the value is
+ * NV_FALSE pulse a reset to the hardware module.
+ *
+ */
+void 
+NvRmPrivModuleReset(NvRmDeviceHandle hDevice, NvRmModuleID ModuleId, NvBool hold);
+
+/**
+ * Updates voltage scaling references, when the specified module clock
+ * is enabled, or disabled.
+ * 
+ * @param hRmDeviceHandle The RM device handle.
+ * @param pCinfo Pointer to the targeted module clock descriptor.
+ * @param pCstate Pointer to the targeted module clock state.
+ * @param Enable NV_TRUE if module clock is about to be enabled;
+ *  NV_FALSE if module clock has just been disabled.
+ * @param Preview NV_TRUE if scaling references should be preserved when
+ *  voltage increase is required, NV_FALSE if scaling references should
+ *  be updated in any case.
+ * 
+ * @return Core voltage level in mV required for the new module configuration.
+ *  NvRmVoltsUnspecified is returned if module clock can be enabled without
+ *  changing voltage requirements. NvRmVoltsOff is returned when module clock
+ *  is disabled.
+ */
+NvRmMilliVolts
+NvRmPrivModuleVscaleAttach(
+    NvRmDeviceHandle hRmDevice,
+    const NvRmModuleClockInfo* pCinfo,
+    NvRmModuleClockState* pCstate,
+    NvBool Enable,
+    NvBool Preview);
+
+/**
+ * Updates voltage scaling references, when the clock frequency for the
+ * specified module is re-configured.
+ * 
+ * @param hRmDeviceHandle The RM device handle.
+ * @param pCinfo Pointer to the targeted module clock descriptor.
+ * @param pCstate Pointer to the targeted module clock state.
+ * @param TargetModuleKHz Traget module frequency in kHz.
+ * @param TargetSrcKHz Clock source frequency for the traget module in kHz.
+ * @param Preview NV_TRUE if scaling references should be preserved when
+ *  voltage increase is required, NV_FALSE if scaling references should
+ *  be updated in any case.
+ *
+ * @return Core voltage level in mV required for new module configuration.
+ *  NvRmVoltsUnspecified is returned if all specified frequencies can be
+ *  configured without changing voltage requirements. NvRmVoltsOff is returned
+ *  if new configuration may lower voltage requirements.
+ */
+NvRmMilliVolts
+NvRmPrivModuleVscaleReAttach(
+    NvRmDeviceHandle hRmDevice,
+    const NvRmModuleClockInfo* pCinfo,
+    NvRmModuleClockState* pCstate,
+    NvRmFreqKHz TargetModuleKHz,
+    NvRmFreqKHz TargetSrcKHz,
+    NvBool Preview);
+
+/**
+ * Updates target level, and reference count for pending voltage scaling
+ * transactions.
+ *
+ * @param hRmDevice The RM device handle.
+ * @param Set PendingMv pending transaction target; NvRmVoltsOff is used
+ *  to indicate completed transaction.
+ *
+ */
+void NvRmPrivModuleVscaleSetPending(
+    NvRmDeviceHandle hRmDevice,
+    NvRmMilliVolts PendingMv);
+
+/**
+ * Sets voltage scaling attribute for the specified module clock.
+ * 
+ * @param hRmDeviceHandle The RM device handle.
+ * @param pCinfo Pointer to the targeted module clock descriptor.
+ * @param pCstate Pointer to the targeted module clock state, which is updated
+ *  by this function. 
+ * 
+ * @note The scaling attribute in the clock state structure is set NV_FALSE for
+ *  all core clocks (CPU, AVP, system buses, memory). For modules designated
+ *  clocks it is set NV_FALSE if any frequency within module clock limits can
+ *  be selected at any core voltage level within SoC operational range.
+ *  Otherwise, the attribute is set NV_TRUE.
+ */
+void
+NvRmPrivModuleSetScalingAttribute(
+    NvRmDeviceHandle hRmDevice,
+    const NvRmModuleClockInfo* pCinfo,
+    NvRmModuleClockState* pCstate);
+
+/**
+ * Sets "as is" module clock configuration as specified by the given
+ * clock state structure.
+ *
+ * @param hRmDevice The RM device handle.
+ * @param pCinfo Pointer to the targeted module clock descriptor.
+ * @param pCstate Pointer to the targeted module clock state to be set
+ *  by this function. 
+ */
+void
+NvRmPrivModuleClockSet(
+    NvRmDeviceHandle hRmDevice,
+    const NvRmModuleClockInfo* pCinfo,
+    const NvRmModuleClockState* pCstate);
+
+#ifdef __cplusplus
+}
+#endif  /* __cplusplus */
+
+#endif  // INCLUDED_NVRM_CLOCKS_H
diff --git a/arch/arm/mach-tegra/nvrm/core/common/nvrm_clocks_limits.c b/arch/arm/mach-tegra/nvrm/core/common/nvrm_clocks_limits.c
new file mode 100644
index 000000000000..8935101c4929
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/core/common/nvrm_clocks_limits.c
@@ -0,0 +1,1070 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include "nvcommon.h"
+#include "nvrm_clocks.h"
+#include "nvassert.h"
+#include "nvrm_drf.h"
+#include "nvrm_hwintf.h"
+#include "nvrm_boot.h"
+#include "nvbootargs.h"
+#include "nvrm_memmgr.h"
+#include "ap15/ap15rm_private.h"
+#include "ap15/project_relocation_table.h"
+
+
+#define NvRmPrivGetStepMV(hRmDevice, step) \
+         (s_ChipFlavor.pSocShmoo->ShmooVoltages[(step)])
+
+// Extended clock limits IDs
+typedef enum
+{
+    // Last Module ID
+    NvRmClkLimitsExtID_LastModuleID = NvRmPrivModuleID_Num,
+
+    // Extended ID for display A pixel clock limits
+    NvRmClkLimitsExtID_DisplayA,
+
+    // Extended ID for display B pixel clock limits
+    NvRmClkLimitsExtID_DisplayB,
+
+    // Extended ID for CAR clock sources limits
+    NvRmClkLimitsExtID_ClkSrc,
+
+    NvRmClkLimitsExtID_Num,
+    NvRmClkLimitsExtID_Force32 = 0x7FFFFFFF,
+} NvRmClkLimitsExtID;
+
+/*
+ * Module clocks frequency limits table ordered by s/w module ids.
+ * Display is a special case and has 3 entries associated:
+ * - one entry that corresponds to display ID specifies pixel clock limit used
+ * for CAR clock sources configuration; it is retrieved by RM clock manager
+ * via private interface (same limit for both CAR display clock selectors);
+ * - two entries appended at the end of the table specify pixel clock limits
+ * for two display heads used for DDK clock configuration, these limits will
+ * be retrieved by DDK via public interface
+ * Also appended at the end of the table limits for clock sources (PLLs) forced
+ * by CAR clock dividers
+ */
+static NvRmModuleClockLimits s_ClockRangeLimits[NvRmClkLimitsExtID_Num];
+
+// Translation table for module clock limits scaled with voltage
+static const NvRmFreqKHz* s_pClockScales[NvRmClkLimitsExtID_Num];
+
+// Reference counts of clocks that require the respective core voltage to run
+// (appended with pending voltage change reference count)
+static NvU32 s_VoltageStepRefCounts[NVRM_VOLTAGE_STEPS + 1];
+static NvU32 s_VoltagePendingMv = 0;
+#define NVRM_VOLTAGE_PENDING_STEP (NVRM_VOLTAGE_STEPS)
+
+// Chip shmoo data records
+static NvRmChipFlavor s_ChipFlavor;
+static NvRmSocShmoo s_SocShmoo;
+static NvRmCpuShmoo s_CpuShmoo;
+static void* s_pShmooData = NULL;
+
+static NvError
+NvRmBootArgChipShmooGet(
+    NvRmDeviceHandle hRmDevice,
+    NvRmChipFlavor* pChipFlavor);
+
+static void NvRmPrivChipFlavorInit(NvRmDeviceHandle hRmDevice);
+static void NvRmPrivChipFlavorInit(NvRmDeviceHandle hRmDevice)
+{
+    NvOsMemset((void*)&s_ChipFlavor, 0, sizeof(s_ChipFlavor));
+
+    if (NvRmPrivChipShmooDataInit(hRmDevice, &s_ChipFlavor) == NvSuccess)
+    {
+        NvOsDebugPrintf("NVRM Initialized shmoo database\n");
+        return;
+    }
+    if (NvRmBootArgChipShmooGet(hRmDevice, &s_ChipFlavor) == NvSuccess)
+    {
+        NvOsDebugPrintf("NVRM Got shmoo boot argument (at 0x%x)\n",
+                        ((NvUPtr)s_pShmooData));
+        return;
+    }
+    NV_ASSERT(!"Failed to set clock limits");
+}
+
+const NvRmModuleClockLimits*
+NvRmPrivClockLimitsInit(NvRmDeviceHandle hRmDevice)
+{
+    NvU32 i;
+    NvRmFreqKHz CpuMaxKHz, AvpMaxKHz, VdeMaxKHz, TDMaxKHz, DispMaxKHz;
+    const NvRmSKUedLimits* pSKUedLimits;
+    const NvRmScaledClkLimits* pHwLimits;
+    const NvRmSocShmoo* pShmoo;
+
+    NV_ASSERT(hRmDevice);
+    NvRmPrivChipFlavorInit(hRmDevice);
+    pShmoo = s_ChipFlavor.pSocShmoo;
+    pHwLimits = &pShmoo->ScaledLimitsList[0];
+    pSKUedLimits = pShmoo->pSKUedLimits;
+    NvOsDebugPrintf("NVRM corner (%d, %d)\n",
+        s_ChipFlavor.corner, s_ChipFlavor.CpuCorner);
+
+    NvOsMemset((void*)s_pClockScales, 0, sizeof(s_pClockScales));
+    NvOsMemset(s_ClockRangeLimits, 0, sizeof(s_ClockRangeLimits));
+    NvOsMemset(s_VoltageStepRefCounts, 0, sizeof(s_VoltageStepRefCounts));
+    s_VoltageStepRefCounts[0] = NvRmPrivModuleID_Num; // all at minimum step
+
+    // Combine AVP/System clock absolute limit with scaling V/F ladder upper
+    // boundary, and set default clock range for all present modules the same
+    // as for AVP/System clock
+    AvpMaxKHz = pSKUedLimits->AvpMaxKHz;
+    for (i = 0; i < pShmoo->ScaledLimitsListSize; i++)
+    {
+        if (pHwLimits[i].HwDeviceId == NV_DEVID_AVP)
+        {
+            AvpMaxKHz = NV_MIN(
+                AvpMaxKHz, pHwLimits[i].MaxKHzList[pShmoo->ShmooVmaxIndex]);
+            break;
+        }
+    }
+
+    for (i = 0; i < NvRmPrivModuleID_Num; i++)
+    {
+        NvRmModuleInstance *inst;
+        if (NvRmPrivGetModuleInstance(hRmDevice, i, &inst) == NvSuccess)
+        {
+            s_ClockRangeLimits[i].MaxKHz = AvpMaxKHz;
+            s_ClockRangeLimits[i].MinKHz = NVRM_BUS_MIN_KHZ;
+
+        }
+    }
+
+    // Fill in limits for modules with slectable clock sources and/or dividers
+    // as specified by the h/w table according to the h/w device ID
+    // (CPU and AVP are not in relocation table - need translate id explicitly)
+    // TODO: need separate subclock limits? (current implementation applies
+    // main clock limits to all subclocks)
+    for (i = 0; i < pShmoo->ScaledLimitsListSize; i++)
+    {
+        NvRmModuleID id;
+        if (pHwLimits[i].HwDeviceId == NV_DEVID_CPU)
+            id = NvRmModuleID_Cpu;
+        else if (pHwLimits[i].HwDeviceId == NV_DEVID_AVP)
+            id = NvRmModuleID_Avp;
+        else if (pHwLimits[i].HwDeviceId == NVRM_DEVID_CLK_SRC)
+            id = NvRmClkLimitsExtID_ClkSrc;
+        else
+            id = NvRmPrivDevToModuleID(pHwLimits[i].HwDeviceId);
+        if ((id != NVRM_DEVICE_UNKNOWN) &&
+            (pHwLimits[i].SubClockId == 0))
+        {
+            s_ClockRangeLimits[id].MinKHz = pHwLimits[i].MinKHz;
+            s_ClockRangeLimits[id].MaxKHz =
+                pHwLimits[i].MaxKHzList[pShmoo->ShmooVmaxIndex];
+            s_pClockScales[id] = pHwLimits[i].MaxKHzList;
+        }
+    }
+    // Fill in CPU scaling data if SoC has dedicated CPU rail, and CPU clock
+    // characterization data is separated from other modules on common core rail
+    if (s_ChipFlavor.pCpuShmoo)
+    {
+        const NvRmScaledClkLimits* pCpuLimits =
+            s_ChipFlavor.pCpuShmoo->pScaledCpuLimits;
+        NV_ASSERT(pCpuLimits && (pCpuLimits->HwDeviceId == NV_DEVID_CPU));
+
+        s_ClockRangeLimits[NvRmModuleID_Cpu].MinKHz = pCpuLimits->MinKHz;
+        s_ClockRangeLimits[NvRmModuleID_Cpu].MaxKHz =
+            pCpuLimits->MaxKHzList[s_ChipFlavor.pCpuShmoo->ShmooVmaxIndex];
+        s_pClockScales[NvRmModuleID_Cpu] = pCpuLimits->MaxKHzList;
+    }
+
+    // Set AVP upper clock boundary with combined Absolute/Scaled limit;
+    // Sync System clock with AVP (System is not in relocation table) 
+    s_ClockRangeLimits[NvRmModuleID_Avp].MaxKHz = AvpMaxKHz;
+    s_ClockRangeLimits[NvRmPrivModuleID_System].MaxKHz =
+        s_ClockRangeLimits[NvRmModuleID_Avp].MaxKHz;
+    s_ClockRangeLimits[NvRmPrivModuleID_System].MinKHz =
+        s_ClockRangeLimits[NvRmModuleID_Avp].MinKHz;
+    s_pClockScales[NvRmPrivModuleID_System] = s_pClockScales[NvRmModuleID_Avp];
+
+    // Set VDE upper clock boundary with combined Absolute/Scaled limit (on
+    // AP15/Ap16 VDE clock derived from the system bus, and VDE maximum limit
+    // must be the same as AVP/System).
+    VdeMaxKHz = pSKUedLimits->VdeMaxKHz;
+    VdeMaxKHz = NV_MIN(
+        VdeMaxKHz, s_ClockRangeLimits[NvRmModuleID_Vde].MaxKHz);
+    if ((hRmDevice->ChipId.Id == 0x15) || (hRmDevice->ChipId.Id == 0x16))
+    {
+        NV_ASSERT(VdeMaxKHz == AvpMaxKHz);
+    }
+    s_ClockRangeLimits[NvRmModuleID_Vde].MaxKHz = VdeMaxKHz;
+
+    // Set upper clock boundaries for devices on CPU bus (CPU, Mselect,
+    // CMC) with combined Absolute/Scaled limits
+    CpuMaxKHz = pSKUedLimits->CpuMaxKHz;
+    CpuMaxKHz = NV_MIN(
+        CpuMaxKHz, s_ClockRangeLimits[NvRmModuleID_Cpu].MaxKHz);
+    s_ClockRangeLimits[NvRmModuleID_Cpu].MaxKHz = CpuMaxKHz;
+    if ((hRmDevice->ChipId.Id == 0x15) || (hRmDevice->ChipId.Id == 0x16))
+    {
+        s_ClockRangeLimits[NvRmModuleID_CacheMemCtrl].MaxKHz = CpuMaxKHz;
+        s_ClockRangeLimits[NvRmPrivModuleID_Mselect].MaxKHz = CpuMaxKHz;
+        NV_ASSERT(s_ClockRangeLimits[NvRmClkLimitsExtID_ClkSrc].MaxKHz >=
+                  CpuMaxKHz);
+    }
+    else if (hRmDevice->ChipId.Id == 0x20)
+    {
+        // No CMC; TODO: Mselect/CPU <= 1/4? 
+        s_ClockRangeLimits[NvRmPrivModuleID_Mselect].MaxKHz = CpuMaxKHz >> 2;
+    }
+    else
+    {
+        NV_ASSERT(!"Unsupported chip ID");
+    }
+
+    // Fill in memory controllers absolute range (scaled data is on ODM level)
+    s_ClockRangeLimits[NvRmPrivModuleID_MemoryController].MaxKHz =
+        pSKUedLimits->McMaxKHz;
+    s_ClockRangeLimits[NvRmPrivModuleID_ExternalMemoryController].MaxKHz =
+        pSKUedLimits->Emc2xMaxKHz;
+    s_ClockRangeLimits[NvRmPrivModuleID_ExternalMemoryController].MinKHz =
+        NVRM_SDRAM_MIN_KHZ * 2;
+    s_ClockRangeLimits[NvRmPrivModuleID_ExternalMemory].MaxKHz =
+        pSKUedLimits->Emc2xMaxKHz / 2;
+    s_ClockRangeLimits[NvRmPrivModuleID_ExternalMemory].MinKHz =
+        NVRM_SDRAM_MIN_KHZ;
+
+    // Set 3D upper clock boundary with combined Absolute/Scaled limit.
+    TDMaxKHz = pSKUedLimits->TDMaxKHz;
+    TDMaxKHz = NV_MIN(
+        TDMaxKHz, s_ClockRangeLimits[NvRmModuleID_3D].MaxKHz);
+    s_ClockRangeLimits[NvRmModuleID_3D].MaxKHz = TDMaxKHz;
+
+    // Set Display upper clock boundary with combined Absolute/Scaled limit.
+    // (fill in clock limits for both display heads)
+    DispMaxKHz = NV_MAX(pSKUedLimits->DisplayAPixelMaxKHz,
+                        pSKUedLimits->DisplayBPixelMaxKHz);
+    DispMaxKHz = NV_MIN(
+        DispMaxKHz, s_ClockRangeLimits[NvRmModuleID_Display].MaxKHz);
+    s_ClockRangeLimits[NvRmClkLimitsExtID_DisplayA].MaxKHz =
+        NV_MIN(DispMaxKHz, pSKUedLimits->DisplayAPixelMaxKHz);
+    s_ClockRangeLimits[NvRmClkLimitsExtID_DisplayA].MinKHz =
+            s_ClockRangeLimits[NvRmModuleID_Display].MinKHz;
+    s_ClockRangeLimits[NvRmClkLimitsExtID_DisplayB].MaxKHz =
+        NV_MIN(DispMaxKHz, pSKUedLimits->DisplayBPixelMaxKHz);
+    s_ClockRangeLimits[NvRmClkLimitsExtID_DisplayB].MinKHz =
+            s_ClockRangeLimits[NvRmModuleID_Display].MinKHz;
+
+    return s_ClockRangeLimits;
+}
+
+NvRmFreqKHz
+NvRmPowerModuleGetMaxFrequency(
+    NvRmDeviceHandle hRmDevice,
+    NvRmModuleID ModuleId)
+{
+    NvU32 Instance = NVRM_MODULE_ID_INSTANCE(ModuleId);
+    NvRmModuleID Module = NVRM_MODULE_ID_MODULE(ModuleId);
+    NV_ASSERT(Module < NvRmPrivModuleID_Num);
+    NV_ASSERT(hRmDevice);
+
+    // For all modules, except display, ignore instance, and return
+    // max frequency for the clock generated from CAR dividers
+    if (Module != NvRmModuleID_Display)
+        return s_ClockRangeLimits[Module].MaxKHz;
+
+    // For display return pixel clock for the respective head
+    if (Instance == 0)
+        return s_ClockRangeLimits[NvRmClkLimitsExtID_DisplayA].MaxKHz;
+    else if (Instance == 1)
+        return s_ClockRangeLimits[NvRmClkLimitsExtID_DisplayB].MaxKHz;
+    else
+    {
+        NV_ASSERT(!"Inavlid display instance");
+        return 0;
+    }
+}
+
+NvRmMilliVolts
+NvRmPrivGetNominalMV(NvRmDeviceHandle hRmDevice)
+{
+    const NvRmSocShmoo* p = s_ChipFlavor.pSocShmoo;
+    return p->ShmooVoltages[p->ShmooVmaxIndex];
+}
+
+void
+NvRmPrivGetSvopParameters(
+    NvRmDeviceHandle hRmDevice,
+    NvRmMilliVolts* pSvopLowMv,
+    NvU32* pSvopLvSetting,
+    NvU32* pSvopHvSetting)
+{
+    const NvRmSocShmoo* p = s_ChipFlavor.pSocShmoo;
+
+    NV_ASSERT(pSvopLowMv && pSvopLvSetting && pSvopHvSetting);
+    *pSvopLowMv = p->SvopLowVoltage;
+    *pSvopLvSetting = p->SvopLowSetting;
+    *pSvopHvSetting = p->SvopHighSetting;
+}
+
+NvRmMilliVolts
+NvRmPrivSourceVscaleGetMV(NvRmDeviceHandle hRmDevice, NvRmFreqKHz FreqKHz)
+{
+    NvU32 i;
+    const NvU32* pScaleSrc = s_pClockScales[NvRmClkLimitsExtID_ClkSrc];
+
+    for (i = 0; i < s_ChipFlavor.pSocShmoo->ShmooVmaxIndex; i++)
+    {
+        if (FreqKHz <= pScaleSrc[i])
+            break;
+    }
+    return NvRmPrivGetStepMV(hRmDevice, i);
+}
+
+NvRmMilliVolts
+NvRmPrivModulesGetOperationalMV(NvRmDeviceHandle hRmDevice)
+{
+    NvU32 i;
+    NV_ASSERT(hRmDevice);
+
+    for (i = s_ChipFlavor.pSocShmoo->ShmooVmaxIndex; i != 0; i--)
+    {
+        if (s_VoltageStepRefCounts[i])
+            break;
+    }
+    return NV_MAX(NvRmPrivGetStepMV(hRmDevice, i), s_VoltagePendingMv);
+}
+
+NvRmMilliVolts
+NvRmPrivModuleVscaleGetMV(
+    NvRmDeviceHandle hRmDevice,
+    NvRmModuleID Module,
+    NvRmFreqKHz FreqKHz)
+{
+    NvU32 i;
+    const NvRmFreqKHz* pScale;
+    NV_ASSERT(hRmDevice);
+    NV_ASSERT(Module < NvRmPrivModuleID_Num);
+
+    // If no scaling for this module - exit
+    pScale = s_pClockScales[Module];
+    if(!pScale)
+        return NvRmPrivGetStepMV(hRmDevice, 0);
+
+    // Find voltage step for the requested frequency, and convert it to MV
+    // Use CPU specific voltage ladder if SoC has dedicated CPU rail
+    if (s_ChipFlavor.pCpuShmoo && (Module == NvRmModuleID_Cpu))
+    {
+        for (i = 0; i < s_ChipFlavor.pCpuShmoo->ShmooVmaxIndex; i++)
+        {
+            if (FreqKHz <= pScale[i])
+                break;
+        }
+        return s_ChipFlavor.pCpuShmoo->ShmooVoltages[i];
+    }
+    // Use common ladder for all other modules or CPU on core rail
+    for (i = 0; i < s_ChipFlavor.pSocShmoo->ShmooVmaxIndex; i++)
+    {
+        if (FreqKHz <= pScale[i])
+            break;
+    }
+    return NvRmPrivGetStepMV(hRmDevice, i);
+}
+
+const NvRmFreqKHz*
+NvRmPrivModuleVscaleGetMaxKHzList(
+    NvRmDeviceHandle hRmDevice,
+    NvRmModuleID Module,
+    NvU32* pListSize)
+{
+    NV_ASSERT(hRmDevice);
+    NV_ASSERT(pListSize && (Module < NvRmPrivModuleID_Num));
+
+    // Use CPU specific voltage ladder if SoC has dedicated CPU rail
+    if (s_ChipFlavor.pCpuShmoo && (Module == NvRmModuleID_Cpu))
+        *pListSize = s_ChipFlavor.pCpuShmoo->ShmooVmaxIndex + 1;
+    else
+        *pListSize = s_ChipFlavor.pSocShmoo->ShmooVmaxIndex + 1;
+
+    return s_pClockScales[Module];
+}
+
+NvRmMilliVolts
+NvRmPrivModuleVscaleAttach(
+    NvRmDeviceHandle hRmDevice,
+    const NvRmModuleClockInfo* pCinfo,
+    NvRmModuleClockState* pCstate,
+    NvBool Enable,
+    NvBool Preview)
+{
+    NvBool Enabled;
+    NvU32 reg, vstep1, vstep2, VstepMax;
+    NvRmMilliVolts VoltageRequirement = NvRmVoltsUnspecified;
+    NvBool CheckSubclock = ((pCinfo->Module == NvRmModuleID_Spdif) ||
+                            (pCinfo->Module == NvRmModuleID_Vi) ||
+                            (pCinfo->Module == NvRmModuleID_Tvo));
+
+    NV_ASSERT(hRmDevice);
+    NV_ASSERT(pCinfo && pCstate);
+
+    // If no scaling for this module - exit
+    if (!pCstate->Vscale)
+        return VoltageRequirement;
+
+    //Check changes in clock status - exit if none (if clock is already
+    // enabled || if clock still enabled => if enabled)
+    NV_ASSERT(pCinfo->ClkEnableOffset);
+    reg = NV_REGR(hRmDevice, NvRmPrivModuleID_ClockAndReset, 0,
+        pCinfo->ClkEnableOffset);
+    Enabled = ((reg & pCinfo->ClkEnableField) == pCinfo->ClkEnableField);
+    if (Enabled)
+        return VoltageRequirement;
+
+    // Find maximum operational voltage step for all already attached modules,
+    // and voltage steps for this module including subclock if any (subclock
+    // state is located immediately after main one)
+    for (VstepMax = s_ChipFlavor.pSocShmoo->ShmooVmaxIndex;
+          VstepMax != 0; VstepMax--)
+    {
+        if (s_VoltageStepRefCounts[VstepMax])
+            break;
+    }
+    vstep1 = pCstate->Vstep;
+    if (CheckSubclock)
+        vstep2 = pCstate[1].Vstep;
+    else
+        vstep2 = 0;
+
+    // Specify new required voltage if module clock is to be enabled and need
+    // voltage increase, leave requirements unspecified if current operational
+    // voltage is enough, return "Off" indicator if module is to be disabled.
+    if (Enable)
+    {
+        if (VstepMax < NV_MAX(vstep1, vstep2))
+        {
+            VstepMax = NV_MAX(vstep1, vstep2);
+            VoltageRequirement = NvRmPrivGetStepMV(hRmDevice, VstepMax);
+
+            // If preview and voltage increase - return without count update
+            if (Preview)
+                return VoltageRequirement;
+        }
+    }
+    else
+    {
+        VoltageRequirement = NvRmVoltsOff;
+    }
+
+    // Update ref counts for module clock and subclock if any
+    if (Enable)
+    {
+        s_VoltageStepRefCounts[vstep1]++;
+        if ((pCinfo->Module == NvRmModuleID_Usb2Otg) &&
+            (hRmDevice->ChipId.Id == 0x16))
+        {
+            // Two AP16 USB modules share clock enable control
+            s_VoltageStepRefCounts[vstep1]++;
+        }
+    }
+    else
+    {
+        NV_ASSERT(s_VoltageStepRefCounts[vstep1]);
+        s_VoltageStepRefCounts[vstep1]--;
+        if ((pCinfo->Module == NvRmModuleID_Usb2Otg) &&
+            (hRmDevice->ChipId.Id == 0x16))
+        {   
+            // Two AP16 USB modules share clock enable control
+            NV_ASSERT(s_VoltageStepRefCounts[vstep1]);
+            s_VoltageStepRefCounts[vstep1]--;
+        }
+    }
+    if (CheckSubclock)
+    {
+        if (Enable)
+        {
+            s_VoltageStepRefCounts[vstep2]++;
+        }
+        else
+        {
+            NV_ASSERT(s_VoltageStepRefCounts[vstep2]);
+            s_VoltageStepRefCounts[vstep2]--;
+        }
+    }
+    return VoltageRequirement;
+}
+
+
+NvRmMilliVolts
+NvRmPrivModuleVscaleReAttach(
+    NvRmDeviceHandle hRmDevice,
+    const NvRmModuleClockInfo* pCinfo,
+    NvRmModuleClockState* pCstate,
+    NvRmFreqKHz TargetModuleKHz,
+    NvRmFreqKHz TargetSrcKHz,
+    NvBool Preview)
+{
+    NvU32 i, j, reg, VstepMax;
+    const NvRmFreqKHz* pScale;
+    NvRmFreqKHz FreqKHz;
+    NvRmMilliVolts VoltageRequirement = NvRmVoltsUnspecified;
+
+    NV_ASSERT(hRmDevice);
+    NV_ASSERT(pCinfo && pCstate);
+
+    // No scaling for this module - exit
+    if (!pCstate->Vscale)
+        return VoltageRequirement;
+
+    // Find current maximum module voltage step
+    for (VstepMax = s_ChipFlavor.pSocShmoo->ShmooVmaxIndex;
+          VstepMax != 0; VstepMax--)
+    {
+        if (s_VoltageStepRefCounts[VstepMax])
+            break;
+    }
+
+    // Clip target frequency to module clock limits and find voltage step for
+    // running at target frequency
+    FreqKHz = s_ClockRangeLimits[pCinfo->Module].MinKHz;
+    FreqKHz = NV_MAX(FreqKHz, TargetModuleKHz);
+    if (FreqKHz > s_ClockRangeLimits[pCinfo->Module].MaxKHz)
+        FreqKHz = s_ClockRangeLimits[pCinfo->Module].MaxKHz;
+
+    pScale = s_pClockScales[pCinfo->Module];
+    NV_ASSERT(pScale);
+    for (i = 0; i < s_ChipFlavor.pSocShmoo->ShmooVmaxIndex; i++)
+    {
+        if (FreqKHz <= pScale[i])
+            break;
+    }
+
+    // Find voltage step for using the target source, and select maximum
+    // step required for both module and its source to operate 
+    pScale = s_pClockScales[NvRmClkLimitsExtID_ClkSrc];
+    NV_ASSERT(pScale);
+    for (j = 0; j < s_ChipFlavor.pSocShmoo->ShmooVmaxIndex; j++)
+    {
+        if (TargetSrcKHz <= pScale[j])
+            break;
+    }
+    i = NV_MAX(i, j);
+
+    // If voltage step has changed, always update module state, and update
+    // ref count provided module clock is enabled
+    if (pCstate->Vstep != i)
+    {
+        NV_ASSERT(pCinfo->ClkEnableOffset);
+        reg = NV_REGR(hRmDevice, NvRmPrivModuleID_ClockAndReset, 0,
+            pCinfo->ClkEnableOffset);
+        if ((reg & pCinfo->ClkEnableField) == pCinfo->ClkEnableField)
+        {
+            // Specify new required voltage if module clock is enabled and need
+            // voltage increase, return "Off" indicator if module operational
+            // volatge is going down; otherwise leave requirements unspecified
+            if (i > VstepMax)
+            {
+                VoltageRequirement = NvRmPrivGetStepMV(hRmDevice, i);
+
+                // If preview and voltage increase - return without count update
+                if (Preview)
+                    return VoltageRequirement;
+            }
+            else if ((i < pCstate->Vstep) && (VstepMax == pCstate->Vstep))
+            {
+                VoltageRequirement = NvRmVoltsOff;
+            }
+
+            // Update ref counts
+            NV_ASSERT(s_VoltageStepRefCounts[pCstate->Vstep]);
+            s_VoltageStepRefCounts[pCstate->Vstep]--;
+            s_VoltageStepRefCounts[i]++;
+        }
+        pCstate->Vstep = i;
+    }
+    return VoltageRequirement;
+}
+
+void NvRmPrivModuleVscaleSetPending(
+    NvRmDeviceHandle hRmDevice,
+    NvRmMilliVolts PendingMv)
+{
+    if (PendingMv != NvRmVoltsOff)
+    {
+        s_VoltageStepRefCounts[NVRM_VOLTAGE_PENDING_STEP]++;
+        s_VoltagePendingMv = NV_MAX(s_VoltagePendingMv, PendingMv);
+
+    }
+    else
+    {
+        NV_ASSERT(s_VoltageStepRefCounts[NVRM_VOLTAGE_PENDING_STEP]);
+        if (s_VoltageStepRefCounts[NVRM_VOLTAGE_PENDING_STEP])
+            s_VoltageStepRefCounts[NVRM_VOLTAGE_PENDING_STEP]--;
+
+        if (s_VoltageStepRefCounts[NVRM_VOLTAGE_PENDING_STEP] == 0)
+            s_VoltagePendingMv = NvRmVoltsOff;
+    }
+}
+
+void
+NvRmPrivModuleSetScalingAttribute(
+    NvRmDeviceHandle hRmDevice,
+    const NvRmModuleClockInfo* pCinfo,
+    NvRmModuleClockState* pCstate)
+{
+    const NvRmFreqKHz* pScale;
+
+    NV_ASSERT(hRmDevice);
+    NV_ASSERT(pCinfo && pCstate);
+
+    // Voltage scaling for free running core clocks is done by DFS
+    // independently from module clock control. Therefore modules
+    // that have core clock as a source do not have their own v-scale
+    // attribute set
+    switch (pCinfo->Sources[0])
+    {
+        case NvRmClockSource_CpuBus:
+        case NvRmClockSource_SystemBus:
+        case NvRmClockSource_Ahb:
+        case NvRmClockSource_Apb:
+        case NvRmClockSource_Vbus:
+            pCstate->Vscale = NV_FALSE;
+            return;
+        default:
+            break;
+    }
+
+    // Memory controller scale is specified separately on ODM layer, as
+    // it is board dependent; TVDAC scaling always follow CVE (TV) or
+    // display (CRT); PMU transport must work at any volatge - no
+    // v-scale attribute for these modules
+    switch (pCinfo->Module)
+    {
+        case NvRmModuleID_Dvc:  // TOD0: check PMU transport with ODM DB
+        case NvRmPrivModuleID_MemoryController:
+        case NvRmPrivModuleID_ExternalMemoryController:
+            pCstate->Vscale = NV_FALSE;
+            return;
+        case NvRmModuleID_Tvo:
+            if (pCinfo->SubClockId == 2)
+            {   // TVDAC is TVO subclock 2
+                pCstate->Vscale = NV_FALSE;
+                return;
+            }
+            break;
+        default:
+            break;
+    }
+
+    // Check if this module can run at maximum frequency at all
+    // voltages - no v-scale for this module as well
+    pScale = s_pClockScales[pCinfo->Module];
+    if(!pScale)
+    {
+        NV_ASSERT(!"Need scaling information");
+        pCstate->Vscale = NV_FALSE;
+        return;
+    }
+    if (pScale[0] == pScale[s_ChipFlavor.pSocShmoo->ShmooVmaxIndex])
+    {
+        NvRmMilliVolts SrcMaxMv = NvRmPrivSourceVscaleGetMV(
+            hRmDevice, NvRmPrivModuleGetMaxSrcKHz(hRmDevice, pCinfo));
+        if (SrcMaxMv == NvRmPrivGetStepMV(hRmDevice, 0))
+        {
+            pCstate->Vscale = NV_FALSE;
+            return;
+        }
+    }
+    // Other modules have v-scale
+    pCstate->Vscale = NV_TRUE;
+}
+
+NvU32
+NvRmPrivGetEmcDqsibOffset(NvRmDeviceHandle hRmDevice)
+{
+    const NvRmSocShmoo* p = s_ChipFlavor.pSocShmoo;
+    return p->DqsibOffset;
+}
+
+NvError
+NvRmPrivGetOscDoublerTaps(
+    NvRmDeviceHandle hRmDevice,
+    NvRmFreqKHz OscKHz,
+    NvU32* pTaps)
+{
+    NvU32 i;
+    NvU32 size = s_ChipFlavor.pSocShmoo->OscDoublerCfgListSize;
+    const NvRmOscDoublerConfig* p = s_ChipFlavor.pSocShmoo->OscDoublerCfgList;
+
+    // Find doubler settings for the specified oscillator frequency, and
+    // return the number of taps for the SoC corner
+    for (i = 0; i < size; i++)
+    {
+        if (p[i].OscKHz == OscKHz)
+        {
+            *pTaps = p[i].Taps[s_ChipFlavor.corner];
+            return NvSuccess;
+        }
+    }
+    return NvError_NotSupported;     // Not supported oscillator frequency
+}
+
+NvBool NvRmPrivIsCpuRailDedicated(NvRmDeviceHandle hRmDevice)
+{
+    const NvRmCpuShmoo* p = s_ChipFlavor.pCpuShmoo;
+    return (p != NULL);
+}
+
+/*****************************************************************************/
+
+// TODO: clock limits deinit in NvRmClose() - free s_pShmooData
+// TODO: remove after RM partition is completed
+#define NVRM_BOOT_USE_BOOTARG_SHMOO (1)
+
+static NvError NvRmBootArgChipShmooGet(
+    NvRmDeviceHandle hRmDevice,
+    NvRmChipFlavor* pChipFlavor)
+{
+#if NVRM_BOOT_USE_BOOTARG_SHMOO
+
+    NvU32 offset, size, TotalSize = 0;
+    NvBootArgsChipShmoo BootArgSh;
+    NvBootArgsChipShmooPhys BootArgShPhys;
+    void* pBootShmooData = NULL;
+    NvRmMemHandle hMem = NULL;
+    NvError err = NvSuccess;
+    ExecPlatform env;
+
+    // Retrieve shmoo data
+    err = NvOsBootArgGet(NvBootArgKey_ChipShmoo, &BootArgSh, sizeof(BootArgSh));
+    if (err != NvSuccess)
+    {
+        err = NvError_BadParameter;
+        goto fail;
+    }
+
+    if (BootArgSh.MemHandleKey != 0)
+    {
+        err = NvRmMemHandleClaimPreservedHandle(
+            hRmDevice, BootArgSh.MemHandleKey, &hMem);
+        if (err != NvSuccess) 
+        {
+            goto fail;
+        }
+
+        TotalSize = NvRmMemGetSize(hMem);
+        NV_ASSERT(TotalSize);
+        err = NvRmMemMap(hMem, 0, TotalSize, NVOS_MEM_READ, &pBootShmooData);
+        if( err != NvSuccess )
+        {
+            goto fail;
+        }
+
+        // Use OS memory to keep shmoo data, and release carveout buffer
+        s_pShmooData = NvOsAlloc(TotalSize);
+        if (!s_pShmooData)
+        {
+            err = NvError_InsufficientMemory;
+            goto fail;
+        }
+        NvOsMemcpy(s_pShmooData, pBootShmooData, TotalSize);
+        NvRmMemUnmap(hMem, pBootShmooData, TotalSize);
+        NvRmMemHandleFree(hMem);
+    }
+    else
+    {
+        env = NvRmPrivGetExecPlatform(hRmDevice);
+        if (env != ExecPlatform_Fpga)
+        {
+            err = NvError_BadParameter;
+            goto fail;
+        }
+
+        err = NvOsBootArgGet(NvBootArgKey_ChipShmooPhys, &BootArgShPhys, sizeof(BootArgShPhys));
+        if ((err != NvSuccess) || (BootArgShPhys.PhysShmooPtr == 0))
+        {
+            err = NvError_BadParameter;
+            goto fail;
+        }
+
+        TotalSize = BootArgShPhys.Size;
+        NV_ASSERT(TotalSize);
+
+        // Use OS memory to keep shmoo data
+        s_pShmooData = NvOsAlloc(TotalSize);
+        if (!s_pShmooData)
+        {
+            err = NvError_InsufficientMemory;
+            goto fail;
+        }
+        
+        // Map the physical shmoo address passed by the backdoor loader
+        err = NvOsPhysicalMemMap(BootArgShPhys.PhysShmooPtr, TotalSize,
+            NvOsMemAttribute_WriteBack, 0, &pBootShmooData);
+        if (err != NvSuccess)
+        {
+            goto fail;
+        }
+
+        // Copy the shmoo data and unmap the backdoor shmoo pointer.
+        NvOsMemcpy(s_pShmooData, pBootShmooData, TotalSize);
+        NvOsPhysicalMemUnmap(pBootShmooData, TotalSize);
+        pBootShmooData = NULL;
+    }
+
+    // Fill in shmoo data records
+    pChipFlavor->sku = hRmDevice->ChipId.SKU;
+    pChipFlavor->corner = BootArgSh.CoreCorner;
+    pChipFlavor->CpuCorner = BootArgSh.CpuCorner;
+
+    // Shmoo data for core domain
+    pChipFlavor->pSocShmoo = &s_SocShmoo;
+
+    offset = BootArgSh.CoreShmooVoltagesListOffset;
+    size = BootArgSh.CoreShmooVoltagesListSize;
+    NV_ASSERT (offset + size <= TotalSize);
+    s_SocShmoo.ShmooVoltages = (const NvU32*)((NvUPtr)s_pShmooData + offset);
+    size /= sizeof(*s_SocShmoo.ShmooVoltages); 
+    NV_ASSERT((size * sizeof(*s_SocShmoo.ShmooVoltages) ==
+              BootArgSh.CoreShmooVoltagesListSize) && (size > 1));
+    s_SocShmoo.ShmooVmaxIndex = size - 1;
+
+    offset = BootArgSh.CoreScaledLimitsListOffset;
+    size = BootArgSh.CoreScaledLimitsListSize;
+    NV_ASSERT (offset + size <= TotalSize);
+    s_SocShmoo.ScaledLimitsList =
+        (const NvRmScaledClkLimits*) ((NvUPtr)s_pShmooData + offset);
+    size /= sizeof(*s_SocShmoo.ScaledLimitsList);
+    NV_ASSERT((size * sizeof(*s_SocShmoo.ScaledLimitsList) ==
+              BootArgSh.CoreScaledLimitsListSize) && size);
+    s_SocShmoo.ScaledLimitsListSize = size;
+
+    offset = BootArgSh.OscDoublerListOffset;
+    size = BootArgSh.OscDoublerListSize;
+    NV_ASSERT (offset + size <= TotalSize);
+    s_SocShmoo.OscDoublerCfgList =
+        (const NvRmOscDoublerConfig*)((NvUPtr)s_pShmooData + offset);
+    size /= sizeof(*s_SocShmoo.OscDoublerCfgList);
+    NV_ASSERT((size * sizeof(*s_SocShmoo.OscDoublerCfgList) ==
+              BootArgSh.OscDoublerListSize) && size);
+    s_SocShmoo.OscDoublerCfgListSize = size;
+
+    offset = BootArgSh.SKUedLimitsOffset;
+    size = BootArgSh.SKUedLimitsSize;
+    NV_ASSERT (offset + size <= TotalSize);
+    s_SocShmoo.pSKUedLimits =
+        (const NvRmSKUedLimits*)((NvUPtr)s_pShmooData + offset);
+    NV_ASSERT(size == sizeof(*s_SocShmoo.pSKUedLimits));
+
+    s_SocShmoo.DqsibOffset = BootArgSh.Dqsib;
+    s_SocShmoo.SvopHighSetting = BootArgSh.SvopHighSetting;
+    s_SocShmoo.SvopLowSetting = BootArgSh.SvopLowSetting;
+    s_SocShmoo.SvopLowVoltage = BootArgSh.SvopLowVoltage;
+
+    if (BootArgSh.CpuShmooVoltagesListSize && BootArgSh.CpuScaledLimitsSize)
+    {
+        // Shmoo data for dedicated CPU domain
+        pChipFlavor->pCpuShmoo = &s_CpuShmoo;
+
+        offset = BootArgSh.CpuShmooVoltagesListOffset;
+        size = BootArgSh.CpuShmooVoltagesListSize;
+        NV_ASSERT (offset + size <= TotalSize);
+        s_CpuShmoo.ShmooVoltages =(const NvU32*)((NvUPtr)s_pShmooData + offset);
+        size /= sizeof(*s_CpuShmoo.ShmooVoltages);
+        NV_ASSERT((size * sizeof(*s_CpuShmoo.ShmooVoltages) ==
+              BootArgSh.CpuShmooVoltagesListSize) && (size > 1));
+        s_CpuShmoo.ShmooVmaxIndex = size - 1;
+
+        offset = BootArgSh.CpuScaledLimitsOffset;
+        size = BootArgSh.CpuScaledLimitsSize;
+        NV_ASSERT (offset + size <= TotalSize);
+        s_CpuShmoo.pScaledCpuLimits =
+            (const NvRmScaledClkLimits*)((NvUPtr)s_pShmooData + offset);
+        NV_ASSERT(size == sizeof(*s_CpuShmoo.pScaledCpuLimits));
+    }
+    else
+    {
+        pChipFlavor->pCpuShmoo = NULL;
+    }
+    return err;
+
+fail:
+    NvRmMemUnmap(hMem, pBootShmooData, TotalSize);
+    NvRmMemHandleFree(hMem);
+    NvOsFree(s_pShmooData);
+    s_pShmooData = NULL;
+    return err;
+#else
+    s_pShmooData = NULL;
+    s_SocShmoo.ShmooVoltages = NULL;
+    s_CpuShmoo.ShmooVoltages = NULL:
+    return NvError_NotSupported;
+#endif
+}
+
+NvError NvRmBootArgChipShmooSet(NvRmDeviceHandle hRmDevice)
+{
+#if NVRM_BOOT_USE_BOOTARG_SHMOO
+
+// Alignment and size to get boot shmoo data into carveout memory
+#define NVRM_BOOT_MEM_ALIGNMENT (0x1 << 12)
+#define NVRM_BOOT_MEM_SIZE (0x1 << 13)
+
+    static const NvRmHeap s_heaps[] = 
+    {
+        NvRmHeap_ExternalCarveOut,
+    };
+
+    NvBootArgsChipShmoo BootArgSh;
+    NvRmChipFlavor* pChipFlavor = &s_ChipFlavor;
+    NvRmMemHandle hMem = NULL;
+    void* p = NULL;
+    NvError err = NvSuccess;
+    NvU32 size = 0;
+
+    NV_ASSERT(pChipFlavor->pSocShmoo);
+
+    // Pack shmoo arrays and structures (all members are of NvU32 type).
+    // Start with core domain.
+    BootArgSh.CoreShmooVoltagesListOffset = size;
+    BootArgSh.CoreShmooVoltagesListSize = 
+        (pChipFlavor->pSocShmoo->ShmooVmaxIndex + 1) *
+        sizeof(*pChipFlavor->pSocShmoo->ShmooVoltages);
+    size += BootArgSh.CoreShmooVoltagesListSize;
+
+    BootArgSh.CoreScaledLimitsListOffset = size;
+    BootArgSh.CoreScaledLimitsListSize = 
+        pChipFlavor->pSocShmoo->ScaledLimitsListSize *
+        sizeof(*pChipFlavor->pSocShmoo->ScaledLimitsList);
+    size += BootArgSh.CoreScaledLimitsListSize;
+
+    BootArgSh.OscDoublerListOffset = size;
+    BootArgSh.OscDoublerListSize =
+        pChipFlavor->pSocShmoo->OscDoublerCfgListSize *
+        sizeof(*pChipFlavor->pSocShmoo->OscDoublerCfgList);
+    size += BootArgSh.OscDoublerListSize;
+
+    BootArgSh.SKUedLimitsOffset = size;
+    BootArgSh.SKUedLimitsSize = 
+        sizeof(*pChipFlavor->pSocShmoo->pSKUedLimits);
+    size += BootArgSh.SKUedLimitsSize;
+
+    if (pChipFlavor->pCpuShmoo)
+    {
+        // Add data for dedicated CPU domain
+        BootArgSh.CpuShmooVoltagesListOffset = size;
+        BootArgSh.CpuShmooVoltagesListSize = 
+            (pChipFlavor->pCpuShmoo->ShmooVmaxIndex + 1) *
+            sizeof(*pChipFlavor->pCpuShmoo->ShmooVoltages);
+        size += BootArgSh.CpuShmooVoltagesListSize;
+
+        BootArgSh.CpuScaledLimitsOffset = size;
+        BootArgSh.CpuScaledLimitsSize = 
+            sizeof(*pChipFlavor->pCpuShmoo->pScaledCpuLimits);
+        size += BootArgSh.CpuScaledLimitsSize;
+    }
+    else
+    {
+        BootArgSh.CpuShmooVoltagesListOffset =
+            BootArgSh.CpuScaledLimitsOffset = size;
+        BootArgSh.CpuShmooVoltagesListSize = 0;
+        BootArgSh.CpuScaledLimitsSize = 0;
+    }
+
+    // Align, allocate, and fill in shmoo packed data buffer
+    size = NV_MAX(size, NVRM_BOOT_MEM_SIZE);
+
+    err = NvRmMemHandleCreate(hRmDevice, &hMem, size);
+    if( err!= NvSuccess )
+    {
+        goto fail;
+    }
+    err = NvRmMemAlloc(hMem, s_heaps, NV_ARRAY_SIZE(s_heaps),
+                       NVRM_BOOT_MEM_ALIGNMENT, NvOsMemAttribute_Uncached);
+    if( err != NvSuccess )
+    {
+        goto fail;
+    }
+    err = NvRmMemMap(hMem, 0, size, 0, &p);
+    if( err != NvSuccess )
+    {
+        goto fail;
+    }
+
+    NvOsMemset(p, 0, size);
+    NvRmMemWrite(hMem, BootArgSh.CoreShmooVoltagesListOffset,
+        pChipFlavor->pSocShmoo->ShmooVoltages,
+        BootArgSh.CoreShmooVoltagesListSize);
+    NvRmMemWrite(hMem, BootArgSh.CoreScaledLimitsListOffset,
+        pChipFlavor->pSocShmoo->ScaledLimitsList,
+        BootArgSh.CoreScaledLimitsListSize);
+    NvRmMemWrite(hMem, BootArgSh.OscDoublerListOffset,
+        pChipFlavor->pSocShmoo->OscDoublerCfgList,
+        BootArgSh.OscDoublerListSize);
+    NvRmMemWrite(hMem, BootArgSh.SKUedLimitsOffset,
+        pChipFlavor->pSocShmoo->pSKUedLimits, BootArgSh.SKUedLimitsSize);
+
+    if (pChipFlavor->pCpuShmoo)
+    {
+        NvRmMemWrite(hMem, BootArgSh.CpuShmooVoltagesListOffset,
+            pChipFlavor->pCpuShmoo->ShmooVoltages, 
+            BootArgSh.CpuShmooVoltagesListSize);
+        NvRmMemWrite(hMem, BootArgSh.CpuScaledLimitsOffset,
+            pChipFlavor->pCpuShmoo->pScaledCpuLimits, 
+            BootArgSh.CpuScaledLimitsSize);
+    }
+
+    // Preserve packed shmoo data buffer, and complete boot arg setting
+    err = NvRmMemHandlePreserveHandle(hMem, &BootArgSh.MemHandleKey);
+    if ( err != NvSuccess )
+    {
+        goto fail;
+    }
+    BootArgSh.Dqsib = pChipFlavor->pSocShmoo->DqsibOffset;
+    BootArgSh.SvopHighSetting = pChipFlavor->pSocShmoo->SvopHighSetting;
+    BootArgSh.SvopLowSetting = pChipFlavor->pSocShmoo->SvopLowSetting;
+    BootArgSh.SvopLowVoltage = pChipFlavor->pSocShmoo->SvopLowVoltage;
+    BootArgSh.CoreCorner = pChipFlavor->corner;
+    BootArgSh.CpuCorner = pChipFlavor->CpuCorner;
+
+    err = NvOsBootArgSet(NvBootArgKey_ChipShmoo, &BootArgSh, sizeof(BootArgSh));
+    if ( err != NvSuccess )
+    {
+        goto fail;
+    }
+    return err;
+
+fail:
+    NvRmMemHandleFree(hMem);
+    return err;
+#else
+    return NvSuccess;
+#endif
+}
+
+/*****************************************************************************/
+
diff --git a/arch/arm/mach-tegra/nvrm/core/common/nvrm_clocks_limits_private.h b/arch/arm/mach-tegra/nvrm/core/common/nvrm_clocks_limits_private.h
new file mode 100644
index 000000000000..fb8bb3b0e781
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/core/common/nvrm_clocks_limits_private.h
@@ -0,0 +1,308 @@
+/*
+ * Copyright (c) 2008-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_NVRM_CLOCKS_LIMITS_PRIVATE_H
+#define INCLUDED_NVRM_CLOCKS_LIMITS_PRIVATE_H
+
+#include "nvrm_power_private.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif  /* __cplusplus */
+
+// Maximum supported SoC process corners
+#define NVRM_PROCESS_CORNERS (4)
+
+// Maximum supported core and/or CPU voltage characterization steps
+#define NVRM_VOLTAGE_STEPS (7)
+
+// Minimum required core voltage resolution
+#define NVRM_CORE_RESOLUTION_MV (25)
+
+/// Maximum safe core voltage step
+#define NVRM_SAFE_VOLTAGE_STEP_MV (100)
+
+// Minimum system bus frequency
+#define NVRM_BUS_MIN_KHZ (32)
+
+// Minimum SDRAM bus frequency
+#define NVRM_SDRAM_MIN_KHZ (12000)
+
+// ID used by RM to record clock sources V/F dependencies
+#define NVRM_DEVID_CLK_SRC (1000)
+
+/**
+ * Oscillator (main) clock doubler configuration record
+ */
+typedef struct NvRmOscDoublerConfigRec
+{
+    NvRmFreqKHz OscKHz;
+    NvU32 Taps[NVRM_PROCESS_CORNERS];
+} NvRmOscDoublerConfig;
+
+/**
+ * Module clocks limits arranged according to the HW module IDs.
+ */
+typedef struct NvRmScaledClkLimitsRec
+{
+    NvU32 HwDeviceId;
+    NvU32 SubClockId;
+    NvRmFreqKHz MinKHz;
+    NvRmFreqKHz MaxKHzList[NVRM_VOLTAGE_STEPS];
+} NvRmScaledClkLimits;
+
+/**
+ * Combines maximum limits for modules depended on SoC SKU
+ */
+typedef struct NvRmSKUedLimitsRec
+{
+    NvRmFreqKHz CpuMaxKHz;
+    NvRmFreqKHz AvpMaxKHz;
+    NvRmFreqKHz VdeMaxKHz;
+    NvRmFreqKHz McMaxKHz;
+    NvRmFreqKHz Emc2xMaxKHz;
+    NvRmFreqKHz TDMaxKHz;
+    NvRmFreqKHz DisplayAPixelMaxKHz;
+    NvRmFreqKHz DisplayBPixelMaxKHz;
+    NvRmMilliVolts NominalCoreMv;   // for common core rail
+    NvRmMilliVolts NominalCpuMv;    // for dedicated CPU rail
+} NvRmSKUedLimits;
+
+/**
+ * Combines SoC frequency/voltage shmoo data
+ * (includes data for CPU on the common core rail)
+ */
+typedef struct NvRmSocShmooRec
+{
+    const NvU32* ShmooVoltages;
+    NvU32 ShmooVmaxIndex;
+
+    const NvRmScaledClkLimits* ScaledLimitsList;
+    NvU32 ScaledLimitsListSize;
+
+    const NvRmSKUedLimits* pSKUedLimits;
+
+    const NvRmOscDoublerConfig* OscDoublerCfgList;
+    NvU32 OscDoublerCfgListSize;
+
+    NvU32 DqsibOffset;
+    NvRmMilliVolts SvopLowVoltage;
+    NvU32 SvopLowSetting;
+    NvU32 SvopHighSetting;
+} NvRmSocShmoo;
+
+/**
+ * Combines frequency/voltage shmoo data for CPU on the dedicated voltage rail
+ * (separated from common SoC core rail)
+ */
+typedef struct NvRmCpuShmooRec
+{
+    const NvU32* ShmooVoltages;
+    NvU32 ShmooVmaxIndex;
+
+    const NvRmScaledClkLimits* pScaledCpuLimits;
+} NvRmCpuShmoo;
+
+/**
+ * Combines chip SKU and process corner records with shmoo data
+ */
+typedef struct NvRmChipFlavorRec
+{
+    NvU16 sku;
+
+    NvU16 corner;
+    const NvRmSocShmoo* pSocShmoo; // shmoo core rail (may include CPU)
+
+    NvU16 CpuCorner;
+    const NvRmCpuShmoo* pCpuShmoo; // shmoo dedicated CPU rail (NULL if none)
+} NvRmChipFlavor;
+
+/**
+ * Combines module clock frequency limits
+ */
+typedef struct NvRmModuleClockLimitsRec
+{
+    NvRmFreqKHz MinKHz;
+    NvRmFreqKHz MaxKHz;
+} NvRmModuleClockLimits;
+
+/**
+ * Initializes module clock limits table.
+ * 
+ * @param hRmDevice The RM device handle. 
+ * 
+ * @return A pointer to the module clock limits table
+ */
+const NvRmModuleClockLimits*
+NvRmPrivClockLimitsInit(NvRmDeviceHandle hRmDevice);
+
+/**
+ * Gets list of maximum frequencies for the specified module clock in
+ * ascending order of scaling voltage levels.
+ * 
+ * @param hRmDevice The RM device handle.
+ * @param Module  The targeted module ID.
+ * @param pListSize A pointer to a variable filled with list size (i.e.,
+ *  number of scaling voltage levels)
+ * 
+ * @return Pointer to the frequencies list (NULL if the module is not present,
+ *  or the list does not exist)
+ */
+const NvRmFreqKHz*
+NvRmPrivModuleVscaleGetMaxKHzList(
+    NvRmDeviceHandle hRmDevice,
+    NvRmModuleID Module,
+    NvU32* pListSize);
+
+/**
+ * Gets core voltage level required for operation of the specified module
+ * at the specified frequency.
+ * 
+ * @param hRmDevice The RM device handle.
+ * @param Module  The targeted module ID.
+ * @param FreqKHz The trageted module frequency in kHz.
+ * 
+ * @return Core voltage level in mV.
+ */
+NvRmMilliVolts
+NvRmPrivModuleVscaleGetMV(
+    NvRmDeviceHandle hRmDevice,
+    NvRmModuleID Module,
+    NvRmFreqKHz FreqKHz);
+
+/**
+ * Gets minimum core voltage level required for operation of all non-DFS
+ * modules at current frequencies.
+ * 
+ * @param hRmDevice The RM device handle.
+ * 
+ * @return Core voltage level in mV.
+ */
+NvRmMilliVolts
+NvRmPrivModulesGetOperationalMV(NvRmDeviceHandle hRmDevice);
+
+/**
+ * Gets minimum core voltage level required to use module clock source with
+ * specified frequency.
+ * 
+ * @param hRmDevice The RM device handle.
+ * 
+ * @return Core voltage level in mV.
+ */
+NvRmMilliVolts
+NvRmPrivSourceVscaleGetMV(NvRmDeviceHandle hRmDevice, NvRmFreqKHz FreqKHz);
+
+/**
+ * Gets SoC nominal core voltage.
+ * 
+ * @param hRmDevice The RM device handle.
+ * 
+ * @return Nominal core voltage in mV.
+ */
+NvRmMilliVolts
+NvRmPrivGetNominalMV(NvRmDeviceHandle hRmDevice);
+
+/**
+ * Gets number of delay taps for Oscillator Doubler.
+ * 
+ * @param hRmDevice The RM device handle.
+ * @param OscKHz Oscillator (main) frequency in KHz.
+ * @param pTaps A pointer to the variable, filled with number of delay taps.
+ * 
+ * @return NvSuccess if the specified oscillator frequency is supported, and
+ * NvError_NotSupported, otherwise.
+ */
+NvError
+NvRmPrivGetOscDoublerTaps(
+    NvRmDeviceHandle hRmDevice,
+    NvRmFreqKHz OscKHz,
+    NvU32* pTaps);
+
+/**
+ * Gets RAM SVOP low voltage parameters.
+ * 
+ * @param hRmDevice The RM device handle.
+ * @param pSvopLowMv A pointer to a variable filled with SVOP low voltage
+ *  threshold in mv.
+ * @param pSvopLvSetting A pointer to a variable filled with SVOP low voltage
+ *  settings.
+ * @param pSvopHvSetting A pointer to a variable filled with SVOP high voltage
+ *  settings.
+ */
+void
+NvRmPrivGetSvopParameters(
+    NvRmDeviceHandle hRmDevice,
+    NvRmMilliVolts* pSvopLowMv,
+    NvU32* pSvopLvSetting,
+    NvU32* pSvopHvSetting);
+
+/**
+ * Gets 32-bit offset to ODM EMC DQSIB settings.
+ * 
+ * @param hRmDevice The RM device handle.
+ * 
+ * @return DQSIB offset.
+ */
+NvU32
+NvRmPrivGetEmcDqsibOffset(NvRmDeviceHandle hRmDevice);
+
+/**
+ * Verifies if SoC has dedicated CPU voltage rail.
+ * 
+ * @param hRmDevice The RM device handle.
+ * 
+ * @return NV_TRUE if SoC has dedicated CPU voltage rail,
+ *  and NV_FALSE if CPU is on common SoC core rail.
+ */
+NvBool NvRmPrivIsCpuRailDedicated(NvRmDeviceHandle hRmDevice);
+
+/**
+ * Initializes SoC characterization data base
+ * 
+ * @param hRmDevice The RM device handle.
+ * @param pChipFlavor a pointer to the chip "flavor" structure
+ *  that this function fills in
+ * 
+ * @return NvSuccess if completed successfully, or NvError_NotSupported,
+ *  otherwise.
+ */
+NvError
+NvRmPrivChipShmooDataInit(
+    NvRmDeviceHandle hRmDevice,
+    NvRmChipFlavor* pChipFlavor);
+
+#ifdef __cplusplus
+}
+#endif  /* __cplusplus */
+
+#endif  // INCLUDED_NVRM_CLOCKS_LIMITS_PRIVATE_H
diff --git a/arch/arm/mach-tegra/nvrm/core/common/nvrm_clocks_limits_stub.c b/arch/arm/mach-tegra/nvrm/core/common/nvrm_clocks_limits_stub.c
new file mode 100644
index 000000000000..1185ad9275e9
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/core/common/nvrm_clocks_limits_stub.c
@@ -0,0 +1,49 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include "nvcommon.h"
+#include "nvrm_clocks.h"
+
+#if !defined(NV_SHMOO_DATA_INIT)
+#define NV_SHMOO_DATA_INIT (0)
+#endif
+
+#if !NV_SHMOO_DATA_INIT
+NvError
+NvRmPrivChipShmooDataInit(
+    NvRmDeviceHandle hRmDevice,
+    NvRmChipFlavor* pChipFlavor)
+{
+    return NvError_NotSupported;
+}
+
+#endif
diff --git a/arch/arm/mach-tegra/nvrm/core/common/nvrm_configuration.c b/arch/arm/mach-tegra/nvrm/core/common/nvrm_configuration.c
new file mode 100644
index 000000000000..5e8f30f0f078
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/core/common/nvrm_configuration.c
@@ -0,0 +1,146 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include "nvrm_configuration.h"
+#include "nvos.h"
+#include "nvassert.h"
+#include "nvutil.h"
+
+NvError
+NvRmPrivGetDefaultCfg( NvRmCfgMap *map, void *cfg )
+{
+    NvU32 i;
+
+    /* Configure configuration variable defaults */
+    for( i = 0; map[i].name; i++ )
+    {
+        if( map[i].type == NvRmCfgType_Char )
+        {
+            *(char*)((NvU32)cfg + (NvU32)map[i].offset) =
+                (char)(NvU32)map[i].initial;
+            NV_DEBUG_PRINTF(( "Default: %s=%c\n", map[i].name,
+                (char)(NvU32)map[i].initial));
+        } 
+        else if( map[i].type == NvRmCfgType_String )
+        {
+            const char *val = (const char *)map[i].initial;
+            NvU32 len = NvOsStrlen( val );
+            if( len >= NVRM_CFG_MAXLEN )
+            {
+                len = NVRM_CFG_MAXLEN - 1;
+            }
+
+            NvOsStrncpy( (char *)(NvU32)cfg + (NvU32)map[i].offset, val, len );
+            NV_DEBUG_PRINTF(("Default: %s=%s\n", map[i].name, val));
+        }
+        else 
+        {
+            *(NvU32*)((NvU32)cfg + (NvU32)map[i].offset) =
+                (NvU32)map[i].initial;
+            if( map[i].type == NvRmCfgType_Hex )
+            {
+                NV_DEBUG_PRINTF(("Default: %s=0x%08x\n", map[i].name,
+                    (NvU32)map[i].initial));
+            }
+            else
+            {
+                NV_DEBUG_PRINTF(("Default: %s=%d\n", map[i].name,
+                    (NvU32)map[i].initial));
+            }
+        }
+    }
+
+    return NvSuccess;
+}
+
+NvError
+NvRmPrivReadCfgVars( NvRmCfgMap *map, void *cfg )
+{
+    NvU32 tmp;
+    NvU32 i;
+    char val[ NVRM_CFG_MAXLEN ];
+    NvError err;
+
+    /* the last cfg var entry is all zeroes */
+    for( i = 0; i < (NvU32)map[i].name; i++ )
+    {
+        err = NvOsGetConfigString( map[i].name, val, NVRM_CFG_MAXLEN );
+        if( err != NvSuccess )
+        {
+            /* no config var set, try the next one */
+            continue;
+        }
+
+        /* parse the config var and print it */
+        switch( map[i].type ) {
+        case NvRmCfgType_Hex:
+        {
+            char *end = val + NvOsStrlen( val );
+            tmp = NvUStrtoul( val, &end, 16 );
+            tmp = 0;
+            *(NvU32*)((NvU32)cfg + (NvU32)map[i].offset) = tmp;
+            NV_DEBUG_PRINTF(("Request: %s=0x%08x\n", map[i].name, tmp));
+            break;
+        }
+        case NvRmCfgType_Char:
+            *(char*)((NvU32)cfg + (NvU32)map[i].offset) = val[0];
+            NV_DEBUG_PRINTF(("Request: %s=%c\n", map[i].name, val[0]));
+            break;
+        case NvRmCfgType_Decimal:
+        {
+            char *end = val + NvOsStrlen( val );
+            tmp = NvUStrtoul( val, &end, 10 );
+            tmp = 0;
+            *(NvU32*)((NvU32)cfg + (NvU32)map[i].offset) = tmp;
+            NV_DEBUG_PRINTF(("Request: %s=%d\n", map[i].name, tmp));
+            break;
+        }
+        case NvRmCfgType_String:
+        {
+            NvU32 len = NvOsStrlen( val );
+            if( len >= NVRM_CFG_MAXLEN )
+            {
+                len = NVRM_CFG_MAXLEN - 1;
+            }
+            NvOsMemset( (char *)(NvU32)cfg + (NvU32)map[i].offset, 0,
+                NVRM_CFG_MAXLEN );
+            NvOsStrncpy( (char *)(NvU32)cfg + (NvU32)map[i].offset, val, len );
+            NV_DEBUG_PRINTF(("Request: %s=%s\n", map[i].name, val));
+            break;
+        }
+        default:
+            NV_ASSERT(!" Illegal RM Configuration type. ");
+        }
+    }
+
+    return NvSuccess;
+}
diff --git a/arch/arm/mach-tegra/nvrm/core/common/nvrm_configuration.h b/arch/arm/mach-tegra/nvrm/core/common/nvrm_configuration.h
new file mode 100644
index 000000000000..f5b3ff0e1ae8
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/core/common/nvrm_configuration.h
@@ -0,0 +1,105 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_NVRM_CONFIGURATION_H
+#define INCLUDED_NVRM_CONFIGURATION_H
+
+#include "nvcommon.h"
+#include "nverror.h"
+
+/**
+ * The RM configuration variables are represented by two structures:
+ * a configuration map, which lists all of the variables, their default
+ * values and types, and a struct of strings, which holds the runtime value of
+ * the variables.  The map holds the index into the runtime structure.
+ *
+ */
+
+/**
+ * The configuration varible type.
+ */
+typedef enum
+{
+    /* String should be parsed as a decimal */
+    NvRmCfgType_Decimal = 0,
+
+    /* String should be parsed as a hexadecimal */
+    NvRmCfgType_Hex = 1,
+
+    /* String should be parsed as a character */
+    NvRmCfgType_Char = 2,
+
+    /* String used as-is. */
+    NvRmCfgType_String = 3,
+} NvRmCfgType;
+
+/**
+ * The configuration map (all possible variables).  The map must be
+ * null terminated.  Each Rm instance (for each chip) can/will have
+ * different configuration maps.
+ */
+typedef struct NvRmCfgMap_t
+{  
+    const char *name;
+    NvRmCfgType type; 
+    void *initial; /* default value of the variable */
+    void *offset; /* the index into the string structure */
+} NvRmCfgMap;
+
+/* helper macro for generating the offset for the map */
+#define STRUCT_OFFSET( s, e )       (void *)(&(((s*)0)->e))
+
+/* maximum size of a configuration variable */
+#define NVRM_CFG_MAXLEN NVOS_PATH_MAX
+
+/**
+ * get the default configuration variables.
+ *
+ * @param map The configuration map
+ * @param cfg The configuration runtime values
+ */
+NvError
+NvRmPrivGetDefaultCfg( NvRmCfgMap *map, void *cfg );
+
+/**
+ * get requested configuration.
+ *
+ * @param map The configuration map
+ * @param cfg The configuration runtime values
+ *
+ * Note: 'cfg' should have already been initialized with
+ * NvRmPrivGetDefaultCfg()  before calling this.
+ */
+NvError
+NvRmPrivReadCfgVars( NvRmCfgMap *map, void *cfg );
+
+#endif
diff --git a/arch/arm/mach-tegra/nvrm/core/common/nvrm_hw_devids.h b/arch/arm/mach-tegra/nvrm/core/common/nvrm_hw_devids.h
new file mode 100644
index 000000000000..9ce89e16b3b3
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/core/common/nvrm_hw_devids.h
@@ -0,0 +1,447 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_NVRM_HW_DEVIDS_H
+#define INCLUDED_NVRM_HW_DEVIDS_H
+
+// Memory Aperture: Internal Memory
+#define NVRM_DEVID_IMEM                            1
+
+// Memory Aperture: External Memory
+#define NVRM_DEVID_EMEM                            2
+
+// Memory Aperture: TCRAM
+#define NVRM_DEVID_TCRAM                           3
+
+// Memory Aperture: IRAM
+#define NVRM_DEVID_IRAM                            4
+
+// Memory Aperture: NOR FLASH
+#define NVRM_DEVID_NOR                             5
+
+// Memory Aperture: EXIO
+#define NVRM_DEVID_EXIO                            6
+
+// Memory Aperture: GART
+#define NVRM_DEVID_GART                            7
+
+// Device Aperture: Graphics Host (HOST1X)
+#define NVRM_DEVID_HOST1X                          8
+
+// Device Aperture: ARM PERIPH registers
+#define NVRM_DEVID_ARM_PERIPH                      9
+
+// Device Aperture: MSELECT
+#define NVRM_DEVID_MSELECT                         10
+
+// Device Aperture: memory controller
+#define NVRM_DEVID_MC                              11
+
+// Device Aperture: external memory controller
+#define NVRM_DEVID_EMC                             12
+
+// Device Aperture: video input
+#define NVRM_DEVID_VI                              13
+
+// Device Aperture: encoder pre-processor
+#define NVRM_DEVID_EPP                             14
+
+// Device Aperture: video encoder
+#define NVRM_DEVID_MPE                             15
+
+// Device Aperture: 3D engine
+#define NVRM_DEVID_GR3D                            16
+
+// Device Aperture: 2D + SBLT engine
+#define NVRM_DEVID_GR2D                            17
+
+// Device Aperture: Image Signal Processor
+#define NVRM_DEVID_ISP                             18
+
+// Device Aperture: DISPLAY
+#define NVRM_DEVID_DISPLAY                         19
+
+// Device Aperture: UPTAG
+#define NVRM_DEVID_UPTAG                           20
+
+// Device Aperture - SHR_SEM
+#define NVRM_DEVID_SHR_SEM                         21
+
+// Device Aperture - ARB_SEM
+#define NVRM_DEVID_ARB_SEM                         22
+
+// Device Aperture - ARB_PRI
+#define NVRM_DEVID_ARB_PRI                         23
+
+// Obsoleted for AP15
+#define NVRM_DEVID_PRI_INTR                        24
+
+// Obsoleted for AP15
+#define NVRM_DEVID_SEC_INTR                        25
+
+// Device Aperture: Timer Programmable
+#define NVRM_DEVID_TMR                             26
+
+// Device Aperture: Clock and Reset
+#define NVRM_DEVID_CAR                             27
+
+// Device Aperture: Flow control
+#define NVRM_DEVID_FLOW                            28
+
+// Device Aperture: Event
+#define NVRM_DEVID_EVENT                           29
+
+// Device Aperture: AHB DMA
+#define NVRM_DEVID_AHB_DMA                         30
+
+// Device Aperture: APB DMA
+#define NVRM_DEVID_APB_DMA                         31
+
+// Obsolete - use AVP_CACHE
+#define NVRM_DEVID_CC                              32
+
+// Device Aperture: COP Cache Controller
+#define NVRM_DEVID_AVP_CACHE                       32
+
+// Device Aperture: SYS_REG
+#define NVRM_DEVID_SYS_REG                         32
+
+// Device Aperture: System Statistic monitor
+#define NVRM_DEVID_STAT                            33
+
+// Device Aperture: GPIO
+#define NVRM_DEVID_GPIO                            34
+
+// Device Aperture: Vector Co-Processor 2
+#define NVRM_DEVID_VCP                             35
+
+// Device Aperture: Arm Vectors
+#define NVRM_DEVID_VECTOR                          36
+
+// Device: MEM
+#define NVRM_DEVID_MEM                             37
+
+// Obsolete - use VDE
+#define NVRM_DEVID_SXE                             38
+
+// Device Aperture: video decoder
+#define NVRM_DEVID_VDE                             38
+
+// Obsolete - use VDE
+#define NVRM_DEVID_BSEV                            39
+
+// Obsolete - use VDE
+#define NVRM_DEVID_MBE                             40
+
+// Obsolete - use VDE
+#define NVRM_DEVID_PPE                             41
+
+// Obsolete - use VDE
+#define NVRM_DEVID_MCE                             42
+
+// Obsolete - use VDE
+#define NVRM_DEVID_TFE                             43
+
+// Obsolete - use VDE
+#define NVRM_DEVID_PPB                             44
+
+// Obsolete - use VDE
+#define NVRM_DEVID_VDMA                            45
+
+// Obsolete - use VDE
+#define NVRM_DEVID_UCQ                             46
+
+// Device Aperture: BSEA (now in AVP cluster)
+#define NVRM_DEVID_BSEA                            47
+
+// Obsolete - use VDE
+#define NVRM_DEVID_FRAMEID                         48
+
+// Device Aperture: Misc regs
+#define NVRM_DEVID_MISC                            49
+
+// Obsolete
+#define NVRM_DEVID_AC97                            50
+
+// Device Aperture: S/P-DIF
+#define NVRM_DEVID_SPDIF                           51
+
+// Device Aperture: I2S
+#define NVRM_DEVID_I2S                             52
+
+// Device Aperture: UART
+#define NVRM_DEVID_UART                            53
+
+// Device Aperture: VFIR
+#define NVRM_DEVID_VFIR                            54
+
+// Device Aperture: NAND Flash Controller
+#define NVRM_DEVID_NANDCTRL                        55
+
+// Obsolete - use NANDCTRL
+#define NVRM_DEVID_NANDFLASH                       55
+
+// Device Aperture: HSMMC
+#define NVRM_DEVID_HSMMC                           56
+
+// Device Aperture: XIO
+#define NVRM_DEVID_XIO                             57
+
+// Device Aperture: PWFM
+#define NVRM_DEVID_PWFM                            58
+
+// Device Aperture: MIPI
+#define NVRM_DEVID_MIPI_HS                         59
+
+// Device Aperture: I2C
+#define NVRM_DEVID_I2C                             60
+
+// Device Aperture: TWC
+#define NVRM_DEVID_TWC                             61
+
+// Device Aperture: SLINK
+#define NVRM_DEVID_SLINK                           62
+
+// Device Aperture: SLINK4B
+#define NVRM_DEVID_SLINK4B                         63
+
+// Device Aperture: SPI
+#define NVRM_DEVID_SPI                             64
+
+// Device Aperture: DTV
+#define NVRM_DEVID_DTV                             64
+
+// Device Aperture: DVC
+#define NVRM_DEVID_DVC                             65
+
+// Device Aperture: RTC
+#define NVRM_DEVID_RTC                             66
+
+// Device Aperture: KeyBoard Controller
+#define NVRM_DEVID_KBC                             67
+
+// Device Aperture: PMIF
+#define NVRM_DEVID_PMIF                            68
+
+// Device Aperture: FUSE
+#define NVRM_DEVID_FUSE                            69
+
+// Device Aperture: L2 Cache Controller
+#define NVRM_DEVID_CMC                             70
+
+// Device Apertuer: NOR FLASH Controller
+#define NVRM_DEVID_NOR_REG                         71
+
+// Device Aperture: EIDE
+#define NVRM_DEVID_EIDE                            72
+
+// Device Aperture: USB
+#define NVRM_DEVID_USB                             73
+
+// Device Aperture: SDIO
+#define NVRM_DEVID_SDIO                            74
+
+// Device Aperture: TVO
+#define NVRM_DEVID_TVO                             75
+
+// Device Aperture: DSI
+#define NVRM_DEVID_DSI                             76
+
+// Device Aperture: HDMI
+#define NVRM_DEVID_HDMI                            77
+
+// Device Aperture: Third Interrupt Controller extra registers
+#define NVRM_DEVID_TRI_INTR                        78
+
+// Device Aperture: Common Interrupt Controller
+#define NVRM_DEVID_ICTLR                           79
+
+// Non-Aperture Interrupt: DMA TX interrupts
+#define NVRM_DEVID_DMA_TX_INTR                     80
+
+// Non-Aperture Interrupt: DMA RX interrupts
+#define NVRM_DEVID_DMA_RX_INTR                     81
+
+// Non-Aperture Interrupt: SW reserved interrupt
+#define NVRM_DEVID_SW_INTR                         82
+
+// Non-Aperture Interrupt: CPU PMU Interrupt
+#define NVRM_DEVID_CPU_INTR                        83
+
+// Device Aperture: Timer Free Running MicroSecond
+#define NVRM_DEVID_TMRUS                           84
+
+// Device Aperture: Interrupt Controller ARB_GNT Registers
+#define NVRM_DEVID_ICTLR_ARBGNT                    85
+
+// Device Aperture: Interrupt Controller DMA Registers
+#define NVRM_DEVID_ICTLR_DRQ                       86
+
+// Device Aperture: AHB DMA Channel
+#define NVRM_DEVID_AHB_DMA_CH                      87
+
+// Device Aperture: APB DMA Channel
+#define NVRM_DEVID_APB_DMA_CH                      88
+
+// Device Aperture: AHB Arbitration Controller
+#define NVRM_DEVID_AHB_ARBC                        89
+
+// Obsolete - use AHB_ARBC
+#define NVRM_DEVID_AHB_ARB_CTRL                    89
+
+// Device Aperture: AHB/APB Debug Bus Registers
+#define NVRM_DEVID_AHPBDEBUG                       91
+
+// Device Aperture: Secure Boot Register
+#define NVRM_DEVID_SECURE_BOOT                     92
+
+// Device Aperture: SPROM
+#define NVRM_DEVID_SPROM                           93
+
+// Memory Aperture: AHB external memory remapping
+#define NVRM_DEVID_AHB_EMEM                        94
+
+// Non-Aperture Interrupt: External PMU interrupt
+#define NVRM_DEVID_PMU_EXT                         95
+
+// Device Aperture: AHB EMEM to MC Flush Register
+#define NVRM_DEVID_PPCS                            96
+
+// Device Aperture: MMU TLB registers for COP/AVP
+#define NVRM_DEVID_MMU_TLB                         97
+
+// Device Aperture: OVG engine
+#define NVRM_DEVID_VG                              98
+
+// Device Aperture: CSI
+#define NVRM_DEVID_CSI                             99
+
+// Device ID for COP
+#define NVRM_DEVID_AVP                             100
+
+// Device ID for MPCORE
+#define NVRM_DEVID_CPU                             101
+
+// Device Aperture: ULPI controller
+#define NVRM_DEVID_ULPI                            102
+
+// Device Aperture: ARM CONFIG registers
+#define NVRM_DEVID_ARM_CONFIG                      103
+
+// Device Aperture: ARM PL310 (L2 controller)
+#define NVRM_DEVID_ARM_PL310                       104
+
+// Device Aperture: PCIe
+#define NVRM_DEVID_PCIE                            105
+
+// Device Aperture: OWR (one wire)
+#define NVRM_DEVID_OWR                             106
+
+// Device Aperture: AVPUCQ
+#define NVRM_DEVID_AVPUCQ                          107
+
+// Device Aperture: AVPBSEA (obsolete)
+#define NVRM_DEVID_AVPBSEA                         108
+
+// Device Aperture: Sync NOR
+#define NVRM_DEVID_SNOR                            109
+
+// Device Aperture: SDMMC
+#define NVRM_DEVID_SDMMC                           110
+
+// Device Aperture: KFUSE
+#define NVRM_DEVID_KFUSE                           111
+
+// Device Aperture: CSITE
+#define NVRM_DEVID_CSITE                           112
+
+// Non-Aperture Interrupt: ARM Interprocessor Interrupt
+#define NVRM_DEVID_ARM_IPI                         113
+
+// Device Aperture: ARM Interrupts 0-31
+#define NVRM_DEVID_ARM_ICTLR                       114
+
+// Device Aperture: IOBIST
+#define NVRM_DEVID_IOBIST                          115
+
+// Device Aperture: SPEEDO
+#define NVRM_DEVID_SPEEDO                          116
+
+// Device Aperture: LA
+#define NVRM_DEVID_LA                              117
+
+// Device Aperture: VS
+#define NVRM_DEVID_VS                              118
+
+// Device Aperture: VCI
+#define NVRM_DEVID_VCI                             119
+
+// Device Aperture: APBIF
+#define NVRM_DEVID_APBIF                           120
+
+// Device Aperture: AUDIO
+#define NVRM_DEVID_AUDIO                           121
+
+// Device Aperture: DAM
+#define NVRM_DEVID_DAM                             122
+
+// Device Aperture: TSENSOR
+#define NVRM_DEVID_TSENSOR                         123
+
+// Device Aperture: SE
+#define NVRM_DEVID_SE                              124
+
+// Device Aperture: TZRAM
+#define NVRM_DEVID_TZRAM                           125
+
+// Device Aperture: AUDIO_CLUSTER
+#define NVRM_DEVID_AUDIO_CLUSTER                   126
+
+// Device Aperture: HDA
+#define NVRM_DEVID_HDA                             127
+
+// Device Aperture: SATA
+#define NVRM_DEVID_SATA                            128
+
+// Device Aperture: ATOMICS
+#define NVRM_DEVID_ATOMICS                         129
+
+// Device Aperture: IPATCH
+#define NVRM_DEVID_IPATCH                          130
+
+// Device Aperture: Activity Monitor
+#define NVRM_DEVID_ACTMON                          131
+
+// Device Aperture: Watch Dog Timer
+#define NVRM_DEVID_WDT                             132
+
+#endif // INCLUDED_NVRM_HW_DEVIDS_H
diff --git a/arch/arm/mach-tegra/nvrm/core/common/nvrm_hwintf.c b/arch/arm/mach-tegra/nvrm/core/common/nvrm_hwintf.c
new file mode 100644
index 000000000000..4f829630005e
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/core/common/nvrm_hwintf.c
@@ -0,0 +1,198 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#if NV_IS_AVP
+#define NV_DEF_RMC_TRACE                0   // NO TRACING FOR AVP
+#endif
+
+#include "nvcommon.h"
+#include "nvassert.h"
+#include "nvrm_hardware_access.h"
+#include "nvrm_module_private.h"
+#include "nvrm_rmctrace.h"
+#include "nvrm_chiplib.h"
+#include "nvrm_hwintf.h"
+
+// FIXME:  This file needs to be split up, when we build user/kernel 
+//         The NvRegr/NvRegw should thunk to the kernel since the rm
+//         handle is not usable in user space.
+//
+//         NvRmPhysicalMemMap/NvRmPhysicalMemUnmap need to be in user space.
+//
+
+static NvRmModuleInstance *
+get_instance( NvRmDeviceHandle rm, NvRmModuleID aperture )
+{
+    NvRmModuleTable *tbl;
+    NvRmModuleInstance *inst;
+    NvU32 Module   = NVRM_MODULE_ID_MODULE( aperture );
+    NvU32 Instance = NVRM_MODULE_ID_INSTANCE( aperture );
+    NvU32 Bar      = NVRM_MODULE_ID_BAR( aperture );
+    NvU32 DeviceId;
+    NvU32 idx = 0;
+
+    tbl = NvRmPrivGetModuleTable( rm );
+
+    inst = tbl->ModInst + tbl->Modules[Module].Index;
+    NV_ASSERT( inst );
+    NV_ASSERT( inst < tbl->LastModInst );
+
+    DeviceId = inst->DeviceId;
+
+    // find the right instance and bar
+    while( inst->DeviceId == DeviceId )
+    {
+        if( idx == Instance && inst->Bar == Bar )
+        {
+            break;
+        }
+        if( inst->Bar == 0 )
+        {
+            idx++;
+        }
+
+        inst++;
+    }
+
+    NV_ASSERT( inst->DeviceId == DeviceId );
+    NV_ASSERT( inst->VirtAddr );
+
+    return inst;
+}
+
+NvU32 NvRegr( NvRmDeviceHandle rm, NvRmModuleID aperture, NvU32 offset )
+{
+    void *addr;
+    NvRmModuleInstance *inst;
+
+    inst = get_instance(rm, aperture);
+    addr = (void *)((NvUPtr)inst->VirtAddr + offset);
+
+    return NV_READ32( addr );
+}
+
+void NvRegw( NvRmDeviceHandle rm, NvRmModuleID aperture, NvU32 offset,
+    NvU32 data )
+{
+    void *addr;
+    NvRmModuleInstance *inst;
+
+    inst = get_instance(rm, aperture);
+    addr = (void *)((NvUPtr)inst->VirtAddr + offset);
+
+    NV_WRITE32( addr, data );
+}
+
+NvU8 NvRegr08( NvRmDeviceHandle rm, NvRmModuleID aperture, NvU32 offset )
+{
+    void *addr;
+    NvRmModuleInstance *inst;
+
+    inst = get_instance(rm, aperture);
+    addr = (void *)((NvUPtr)inst->VirtAddr + offset);
+
+    return NV_READ8( addr );
+}
+
+
+void NvRegw08( NvRmDeviceHandle rm, NvRmModuleID aperture, NvU32 offset,
+    NvU8 data )
+{
+    void *addr;
+    NvRmModuleInstance *inst;
+
+    inst = get_instance(rm, aperture);
+    addr = (void *)((NvUPtr)inst->VirtAddr + offset);
+
+    NV_WRITE08( addr, data );
+}
+
+
+
+void NvRegrm( NvRmDeviceHandle rm, NvRmModuleID aperture, NvU32 num,
+    const NvU32 *offsets, NvU32 *values )
+{
+    void *addr;
+    NvRmModuleInstance *inst;
+    NvU32 i;
+
+    inst = get_instance(rm, aperture);
+
+    for( i = 0; i < num; i++ )
+    {
+        addr = (void *)((NvUPtr)inst->VirtAddr + offsets[i]);
+
+        values[i] = NV_READ32( addr );
+    }
+}
+
+void NvRegwm( NvRmDeviceHandle rm, NvRmModuleID aperture, NvU32 num,
+    const NvU32 *offsets, const NvU32 *values )
+{
+    void *addr;
+    NvRmModuleInstance *inst;
+    NvU32 i;
+
+    inst = get_instance(rm, aperture);
+
+    for( i = 0; i < num; i++ )
+    {
+        addr = (void *)((NvUPtr)inst->VirtAddr + offsets[i]);
+
+        NV_WRITE32( addr, values[i] );
+    }
+}
+
+void NvRegwb( NvRmDeviceHandle rm, NvRmModuleID aperture, NvU32 num,
+    NvU32 offset, const NvU32 *values )
+{
+    void *addr;
+    NvRmModuleInstance *inst;
+
+    inst = get_instance(rm, aperture);
+
+    addr = (void *)((NvUPtr)inst->VirtAddr + offset);
+    NV_WRITE( addr, values, (num << 2) );
+}
+
+void NvRegrb( NvRmDeviceHandle rm, NvRmModuleID aperture, NvU32 num,
+    NvU32 offset, NvU32 *values )
+{
+    void *addr;
+    NvRmModuleInstance *inst;
+
+    inst = get_instance(rm, aperture);
+
+    addr = (void *)((NvUPtr)inst->VirtAddr + offset);
+    NV_READ( values, addr, (num << 2 ) );
+}
+
diff --git a/arch/arm/mach-tegra/nvrm/core/common/nvrm_hwintf.h b/arch/arm/mach-tegra/nvrm/core/common/nvrm_hwintf.h
new file mode 100644
index 000000000000..07017fb9b337
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/core/common/nvrm_hwintf.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef NVRM_HWINTF_H
+#define NVRM_HWINTF_H
+
+#include "nvcommon.h"
+#include "nvrm_init.h"
+#include "nvrm_module.h"
+#include "nvrm_module_private.h"
+#include "nvrm_hardware_access.h"
+
+#endif  /* NVRM_HWINTF_H */
diff --git a/arch/arm/mach-tegra/nvrm/core/common/nvrm_keylist.c b/arch/arm/mach-tegra/nvrm/core/common/nvrm_keylist.c
new file mode 100644
index 000000000000..8471e134366d
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/core/common/nvrm_keylist.c
@@ -0,0 +1,197 @@
+/*
+ * Copyright (c) 2008-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include "nvcommon.h"
+#include "nvutil.h"
+#include "nvrm_keylist.h"
+
+#define NVRM_KEY_ARRAY_LEN 15
+
+// Key node structure
+typedef struct KeyRec
+{
+    NvU32 KeyID[NVRM_KEY_ARRAY_LEN];
+    NvU32 Value[NVRM_KEY_ARRAY_LEN];
+    NvU32 Count;
+    struct KeyRec *pNextKey;
+}Key;
+
+// Pointer to the Key Linked-List
+static Key s_InitialKeyList;
+static Key* s_pKeyList = NULL;
+
+// Handle to mutex for tread safety
+static NvOsMutexHandle s_Mutex = NULL;
+
+// Add a new key node to the existing list
+static NvError AddKeyToList(NvU32 KeyID, NvU32 Value);
+
+// Frees the Linked-List
+static void FreeKeyList(void);
+
+void NvRmPrivDeInitKeyList(NvRmDeviceHandle hRm);
+
+NvError NvRmPrivInitKeyList(
+    NvRmDeviceHandle hRm,
+    const NvU32 * InitialValues,
+    NvU32 InitialCount);
+
+NvError NvRmPrivInitKeyList(NvRmDeviceHandle hRm, 
+                            const NvU32 *InitialValues,
+                            NvU32 InitialCount)
+{
+    NvError Error;
+    NvU32 i;
+
+    Error = NvOsMutexCreate(&s_Mutex);
+    if (Error!=NvSuccess)
+        return Error;
+
+    if (!s_pKeyList)
+    {
+        s_pKeyList = &s_InitialKeyList;
+        s_InitialKeyList.Count = 0;
+        s_InitialKeyList.pNextKey = NULL;
+        for (i=0; i<InitialCount; i++)
+        {
+            AddKeyToList(NvOdmKeyListId_ReservedAreaStart + i, 
+                InitialValues[i]);
+        }
+    }
+
+    // Creating the Mutex
+    return Error;
+}
+
+void NvRmPrivDeInitKeyList(NvRmDeviceHandle hRm)
+{
+    NvOsMutexLock(s_Mutex);
+    FreeKeyList();
+    s_pKeyList = NULL;
+    NvOsMutexUnlock(s_Mutex);
+    NvOsMutexDestroy(s_Mutex);
+}
+
+NvU32 NvRmGetKeyValue(NvRmDeviceHandle hRm, NvU32 KeyID)
+{
+    Key *pList = s_pKeyList;
+    NvU32 Value = 0;
+    unsigned int i;
+
+    NvOsMutexLock(s_Mutex);
+    while (pList)
+    {
+        for (i=0; i<pList->Count; i++)
+        {
+            if (pList->KeyID[i] == KeyID)
+            {
+                Value = pList->Value[i];
+                goto cleanup;
+            }
+        }
+        pList = pList->pNextKey;
+    }
+cleanup:
+    NvOsMutexUnlock(s_Mutex);
+    // Returning value as 0 since key is not present
+    return Value;
+}
+
+NvError NvRmSetKeyValuePair(NvRmDeviceHandle hRm, NvU32 KeyID, NvU32 Value)
+{
+    Key *pList = s_pKeyList;
+    NvError e = NvSuccess;
+    unsigned int i;
+
+    if (KeyID >= NvOdmKeyListId_ReservedAreaStart &&
+        KeyID <= NvOdmKeyListId_ReservedAreaEnd)
+        return NvError_NotSupported;
+
+    NvOsMutexLock(s_Mutex);
+    // Checking if key already exists
+    while (pList)
+    {
+        for (i=0; i<pList->Count; i++)
+        {
+            if (pList->KeyID[i] == KeyID)
+            {
+                pList->Value[i] = Value;
+                goto cleanup;
+            }
+        }
+        pList = pList->pNextKey;
+    }
+    // Adding The new key to the list
+    e = AddKeyToList(KeyID, Value);
+cleanup:
+    NvOsMutexUnlock(s_Mutex);
+    return e;
+}
+
+
+NvError AddKeyToList(NvU32 KeyID, NvU32 Value)
+{
+    Key *pList;
+
+    if (s_pKeyList->Count < NVRM_KEY_ARRAY_LEN)
+    {
+        s_pKeyList->KeyID[s_pKeyList->Count] = KeyID;
+        s_pKeyList->Value[s_pKeyList->Count] = Value;
+        s_pKeyList->Count++;
+    }
+    else
+    {
+        pList = NvOsAlloc(sizeof(Key));
+
+        if (pList == NULL)
+            return NvError_InsufficientMemory;
+
+        pList->KeyID[0] = KeyID;
+        pList->Value[0] = Value;
+        pList->Count = 1;
+        pList->pNextKey = s_pKeyList;
+        s_pKeyList = pList;
+    }
+
+    return NvSuccess;
+}
+
+void FreeKeyList(void)
+{
+    Key *pTemp = s_pKeyList;
+    while (s_pKeyList != &s_InitialKeyList)
+    {
+        pTemp = s_pKeyList->pNextKey ;
+        NvOsFree(s_pKeyList);
+        s_pKeyList = pTemp;
+    }
+}
diff --git a/arch/arm/mach-tegra/nvrm/core/common/nvrm_message.h b/arch/arm/mach-tegra/nvrm/core/common/nvrm_message.h
new file mode 100644
index 000000000000..e32033f6aa05
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/core/common/nvrm_message.h
@@ -0,0 +1,270 @@
+/*
+ * Copyright (c) 2010 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_NVRM_MESSAGE_H
+#define INCLUDED_NVRM_MESSAGE_H
+
+#include "nvrm_memmgr.h"
+#include "nvrm_module.h"
+#include "nvrm_transport.h"
+#include "nvrm_power.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif  /* __cplusplus */
+
+// Maximum message queue depth
+enum {MAX_QUEUE_DEPTH = 5};
+// Maximum message length
+enum {MAX_MESSAGE_LENGTH = 256};
+// Maximum argument size
+enum {MAX_ARGS_SIZE = 220};
+// Max String length
+enum {MAX_STRING_LENGTH = 200};
+
+typedef struct NvRmRPCRec 
+{
+    NvRmTransportHandle svcTransportHandle;
+    NvOsSemaphoreHandle TransportRecvSemId;
+    NvOsMutexHandle RecvLock;
+    NvRmDeviceHandle hRmDevice;
+    NvBool isConnected;
+} NvRmRPC;
+
+typedef struct NvRmRPCRec *NvRmRPCHandle;
+
+void NvRmPrivProcessMessage(NvRmRPCHandle hRPCHandle, char *pRecvMessage, int messageLength);
+
+typedef enum
+{
+    NvRmMsg_MemHandleCreate = 0x0,
+    NvRmMsg_MemHandleCreate_Response,
+    NvRmMsg_MemHandleOpen,
+    NvRmMsg_MemHandleFree,
+    NvRmMsg_MemAlloc,
+    NvRmMsg_MemAlloc_Response,
+    NvRmMsg_MemPin,
+    NvRmMsg_MemPin_Response,
+    NvRmMsg_MemUnpin,
+    NvRmMsg_MemUnpin_Response,
+    NvRmMsg_MemGetAddress,
+    NvRmMsg_MemGetAddress_Response,
+    NvRmMsg_HandleFromId,
+    NvRmMsg_HandleFromId_Response,
+    NvRmMsg_PowerModuleClockControl,
+    NvRmMsg_PowerModuleClockControl_Response,
+    NvRmMsg_ModuleReset,
+    NvRmMsg_ModuleReset_Response,
+    NvRmMsg_PowerRegister,
+    NvRmMsg_PowerUnRegister,    
+    NvRmMsg_PowerStarvationHint,
+    NvRmMsg_PowerBusyHint,
+    NvRmMsg_PowerBusyMultiHint,
+    NvRmMsg_PowerDfsGetState,    
+    NvRmMsg_PowerDfsGetState_Response,
+    NvRmMsg_PowerResponse,
+    NvRmMsg_PowerModuleGetMaxFreq,
+    NvRmMsg_InitiateLP0,
+    NvRmMsg_InitiateLP0_Response,
+    NvRmMsg_RemotePrintf,
+    NvRmMsg_AttachModule,
+    NvRmMsg_AttachModule_Response,
+    NvRmMsg_DetachModule,
+    NvRmMsg_DetachModule_Response,
+    NvRmMsg_AVP_Reset,
+    NvRmMsg_Force32 = 0x7FFFFFFF
+}NvRmMsg;
+
+typedef struct{
+    NvRmMsg         msg;
+    NvU32           size;
+}NvRmMessage_HandleCreat;
+
+typedef struct{
+    NvRmMsg         msg;
+    NvRmMemHandle   hMem;
+    NvError         error;
+}NvRmMessage_HandleCreatResponse;
+
+typedef struct{
+    NvRmMsg        msg;
+    NvRmMemHandle  hMem;
+}NvRmMessage_HandleFree;
+
+typedef struct{
+    NvRmMsg     msg;
+    NvError     error;
+}NvRmMessage_Response;
+
+typedef struct{
+    NvRmMsg             msg;
+    NvRmMemHandle       hMem;
+    NvRmHeap            Heaps[NvRmHeap_Num];
+    NvU32               NumHeaps;
+    NvU32               Alignment;
+    NvOsMemAttribute    Coherency;
+}NvRmMessage_MemAlloc;
+
+typedef struct{
+    NvRmMsg       msg;
+    NvRmMemHandle hMem;
+    NvU32         Offset;
+}NvRmMessage_GetAddress;
+
+typedef struct{
+    NvRmMsg       msg;
+    NvU32         address;
+}NvRmMessage_GetAddressResponse;
+
+typedef struct{
+    NvRmMsg       msg;
+    NvU32         id;
+}NvRmMessage_HandleFromId;
+
+typedef struct{
+    NvRmMsg       msg;
+    NvRmMemHandle hMem;
+}NvRmMessage_Pin;
+
+typedef struct{
+    NvRmMsg       msg;
+    NvU32         address;
+}NvRmMessage_PinResponse;
+
+typedef struct{
+    NvRmMsg         msg;
+    NvRmModuleID    ModuleId;
+    NvU32           ClientId;
+    NvBool          Enable;
+}NvRmMessage_Module;
+
+typedef struct{
+    NvRmMsg msg;
+    NvU32 clientId;
+    NvOsSemaphoreHandle eventSema;    
+}NvRmMessage_PowerRegister;
+
+typedef struct{
+    NvRmMsg msg;    
+    NvU32 clientId;
+}NvRmMessage_PowerUnRegister;
+
+typedef struct{
+    NvRmMsg msg;
+    NvRmDfsClockId clockId;
+    NvU32 clientId;
+    NvBool starving;
+}NvRmMessage_PowerStarvationHint;
+
+typedef struct{
+    NvRmMsg msg;
+    NvRmDfsClockId clockId;
+    NvU32 clientId;
+    NvU32 boostDurationMS;
+    NvRmFreqKHz boostKHz;
+}NvRmMessage_PowerBusyHint;
+
+typedef struct{
+    NvRmMsg msg;
+    NvU32 numHints;
+    NvU8 busyHints[MAX_STRING_LENGTH];
+}NvRmMessage_PowerBusyMultiHint;
+
+typedef struct{
+    NvRmMsg msg;
+}NvRmMessage_PowerDfsGetState;
+
+typedef struct{
+    NvRmMsg msg;
+    NvError error;
+    NvU32 clientId;
+}NvRmMessage_PowerRegister_Response;
+
+typedef struct{
+    NvRmMsg msg;
+    NvRmDfsRunState state;
+}NvRmMessage_PowerDfsGetState_Response;
+
+typedef struct{
+    NvRmMsg msg;
+    NvRmModuleID moduleID;
+}NvRmMessage_PowerModuleGetMaxFreq;
+
+typedef struct{
+    NvRmMsg msg;
+    NvRmFreqKHz freqKHz;
+}NvRmMessage_PowerModuleGetMaxFreq_Response;
+
+typedef struct{
+    NvRmMsg msg;
+    NvU32 sourceAddr;
+    NvU32 bufferAddr;
+    NvU32 bufferSize;
+} NvRmMessage_InitiateLP0;
+
+typedef struct{
+    NvRmMsg msg;
+    const char string[MAX_STRING_LENGTH];
+} NvRmMessage_RemotePrintf;
+
+
+typedef struct{
+    NvRmMsg       msg;
+    NvU32         entryAddress;
+    NvU32         size;
+    char          args[MAX_ARGS_SIZE];
+    NvU32         reason;
+}NvRmMessage_AttachModule;
+
+typedef struct{
+    NvRmMsg       msg;
+    NvError       error;
+}NvRmMessage_AttachModuleResponse;
+
+typedef struct{
+    NvRmMsg       msg;
+    NvU32         reason;
+    NvU32         entryAddress;
+}NvRmMessage_DetachModule;
+
+typedef struct{
+    NvRmMsg       msg;
+    NvError       error;
+}NvRmMessage_DetachModuleResponse;
+
+#ifdef __cplusplus
+}
+#endif  /* __cplusplus */
+
+
+#endif
diff --git a/arch/arm/mach-tegra/nvrm/core/common/nvrm_module.c b/arch/arm/mach-tegra/nvrm/core/common/nvrm_module.c
new file mode 100644
index 000000000000..6d9bd1b2ea72
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/core/common/nvrm_module.c
@@ -0,0 +1,487 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#if NV_IS_AVP
+#define NV_DEF_RMC_TRACE                0   // NO TRACING FOR AVP
+#endif
+
+#include "nvcommon.h"
+#include "nvassert.h"
+#include "nvos.h"
+#include "nvrm_hwintf.h"
+#include "nvrm_module.h"
+#include "nvrm_module_private.h"
+#include "nvrm_moduleids.h"
+#include "nvrm_chipid.h"
+#include "nvrm_drf.h"
+#include "nvrm_power.h"
+#include "nvrm_structure.h"
+#include "ap15/ap15rm_private.h"
+#include "ap20/ap20rm_misc_private.h"
+#include "ap15/arclk_rst.h"
+
+#define NVRM_ENABLE_PRINTF          0  // Module debug: 0=disable, 1=enable
+
+#if (NV_DEBUG && NVRM_ENABLE_PRINTF)
+#define NVRM_MODULE_PRINTF(x)   NvOsDebugPrintf x
+#else
+#define NVRM_MODULE_PRINTF(x)
+#endif
+
+
+// FIXME: this is hacked
+// Handled thru RmTransportMessaging to CPU
+void ap15Rm_AvpModuleReset(NvRmDeviceHandle hDevice, NvRmModuleID ModuleId);
+
+void AP15ModuleReset(NvRmDeviceHandle hDevice, NvRmModuleID ModuleId, NvBool hold);
+void AP20ModuleReset(NvRmDeviceHandle hDevice, NvRmModuleID ModuleId, NvBool hold);
+
+void
+NvRmModuleResetWithHold(NvRmDeviceHandle hDevice, NvRmModuleID ModuleId, NvBool hold)
+{
+#if !NV_IS_AVP
+    if ( hDevice->ChipId.Id == 0x15 || hDevice->ChipId.Id == 0x16)
+    {
+        AP15ModuleReset(hDevice, ModuleId, hold);
+    } else
+    {
+        AP20ModuleReset(hDevice, ModuleId, hold);
+    }
+#else
+    ap15Rm_AvpModuleReset(hDevice, ModuleId);
+#endif
+}
+
+void NvRmModuleReset(NvRmDeviceHandle hDevice, NvRmModuleID ModuleId)
+{
+    NvRmModuleResetWithHold(hDevice, ModuleId, NV_FALSE);
+}
+
+NvError
+NvRmModuleGetCapabilities(
+    NvRmDeviceHandle hDevice,
+    NvRmModuleID ModuleId,
+    NvRmModuleCapability *pCaps,
+    NvU32 NumCaps,
+    void **Capability )
+{
+    NvError err;
+    NvRmModuleCapability *cap;
+    NvRmModuleInstance *inst;
+    NvBool found = NV_FALSE;
+    void *ret = 0;
+    NvU32 i;
+    NvRmChipId *id;
+
+    err = NvRmPrivGetModuleInstance( hDevice, ModuleId, &inst );
+    if( err != NvSuccess )
+    {
+        return err;
+    }
+
+    id = NvRmPrivGetChipId( hDevice );
+
+    for( i = 0; i < NumCaps; i++ )
+    {
+        cap = &pCaps[i];
+        ret = cap->Capability;
+
+        /* HW bug 574527 - version numbers for USB are wrong in the AP20 relocation table.*/
+        if (NVRM_MODULE_ID_MODULE( ModuleId ) == NvRmModuleID_Usb2Otg)
+        {
+            if (id->Id == 0x20)
+            {
+                NvU32 instance = NVRM_MODULE_ID_INSTANCE( ModuleId );
+
+                if (((cap->MinorVersion == 5) && (instance == 0)) ||
+                    ((cap->MinorVersion == 6) && (instance == 1))||
+                    ((cap->MinorVersion == 7) && (instance == 2)))
+                {
+                    found = NV_TRUE;
+                    break;
+                }
+                continue;
+            }
+        }
+
+        if( ( cap->MajorVersion == inst->MajorVersion ) &&
+            ( cap->MinorVersion == inst->MinorVersion ) )
+        {
+            // FIMXE: ignoring eco levels for now (properly)
+            // HACK:  except display with AP16 A03/sim/emul (bug 515059)
+            if ( NVRM_MODULE_ID_MODULE( ModuleId ) == NvRmModuleID_Display )
+            {
+                if (id->Id == 0x16 &&
+                        (id->Minor == 0x3 || id->Major == 0))
+                {
+                    // Only accepts cap of (1,2,3) for this chipId
+                    if (cap->MajorVersion == 1 && cap->MinorVersion == 2 &&
+                            cap->EcoLevel == 0x3)
+                    {
+                        found = NV_TRUE;
+                        break;
+                    }
+                    // else not found and continue on to next cap
+                    continue;
+                }
+            }
+
+            found = NV_TRUE;
+            break;
+        }
+    }
+
+    if( !found )
+    {
+        NV_ASSERT(!"Could not find matching version of module in table");
+        *Capability = 0;
+        return NvError_NotSupported;
+    }
+
+    *Capability = ret;
+    return NvSuccess;
+}
+
+NvError
+NvRmPrivFindModule( NvRmDeviceHandle hDevice, NvU32 Address,
+    NvRmPrivModuleID* pModuleId )
+{
+    NvU32 i;
+    NvU32 devid;
+    NvRmModuleTable *tbl;
+    NvRmModuleInstance *inst;
+    NvRmModule *mod;
+    NvU16 num;
+
+    NV_ASSERT((pModuleId != NULL) && (hDevice != NULL));
+
+    tbl = NvRmPrivGetModuleTable( hDevice );
+
+    mod = tbl->Modules;
+    for( i = 0; i < NvRmPrivModuleID_Num; i++ )
+    {
+        if( mod[i].Index == NVRM_MODULE_INVALID )
+        {
+            continue;
+        }
+
+        // For each instance of the module id ...
+        inst = tbl->ModInst + mod[i].Index;
+        devid = inst->DeviceId;
+        num = 0;
+
+        while( devid == inst->DeviceId )
+        {
+            // Is the device address matches
+            if( inst->PhysAddr == Address )
+            {
+                // Return the module id and instance information.
+                *pModuleId = (NvRmPrivModuleID)NVRM_MODULE_ID(i, num);
+                return NvSuccess;
+            }
+
+            inst++;
+            num++;
+        }
+    }
+
+    // we are here implies no matching module was found.
+    return NvError_ModuleNotPresent;
+}
+
+NvError
+NvRmQueryChipUniqueId(NvRmDeviceHandle hDevHandle, NvU32 IdSize, void* pId)
+{
+    NvU32   Size = IdSize;    // Size of the output buffer
+    NvError err = NvError_NotSupported;
+
+    NV_ASSERT(hDevHandle);
+    NV_ASSERT(pId);
+   // Update the intended size
+    IdSize = sizeof(NvU64);
+    if ((pId == NULL)||(Size < IdSize))
+    {
+        return NvError_BadParameter;
+    }
+
+    switch (hDevHandle->ChipId.Id)
+    {
+    case 0x15:
+    case 0x16:      // ap16 should use same space of ap15 for fuse info.
+        NvOsMemset(pId, 0, Size);
+        err = NvRmPrivAp15ChipUniqueId(hDevHandle,pId);
+        break;
+    case 0x20:
+        NvOsMemset(pId, 0, Size);
+        err = NvRmPrivAp20ChipUniqueId(hDevHandle,pId);
+        break;
+    default:
+        NV_ASSERT(!"Unsupported chip ID");
+        return err;
+    }
+    return err;
+}
+
+NvError NvRmGetRandomBytes(
+    NvRmDeviceHandle hRm,
+    NvU32 NumBytes,
+    void *pBytes)
+{
+    NvU8 *Array = (NvU8 *)pBytes;
+    NvU16 Val;
+
+    if (!hRm || !pBytes)
+        return NvError_BadParameter;
+
+    while (NumBytes)
+    {
+        Val = (NvU16) NV_REGR(hRm, NvRmPrivModuleID_ClockAndReset, 0,
+                              CLK_RST_CONTROLLER_PLL_LFSR_0);
+        *Array++ = (Val & 0xff);
+        Val>>=8;
+        NumBytes--;
+        if (NumBytes)
+        {
+            *Array++ = (Val & 0xff);
+            NumBytes--;
+        }
+    }
+
+    return NvSuccess;
+}
+
+NvError
+NvRmPrivModuleInit( NvRmModuleTable *mod_table, NvU32 *reloc_table )
+{
+    NvError err;
+    NvU32 i;
+
+    /* invalidate the module table */
+    for( i = 0; i < NvRmPrivModuleID_Num; i++ )
+    {
+        mod_table->Modules[i].Index = NVRM_MODULE_INVALID;
+    }
+
+    /* clear the irq map */
+    NvOsMemset( &mod_table->IrqMap, 0, sizeof(mod_table->IrqMap) );
+
+    err = NvRmPrivRelocationTableParse( reloc_table,
+        &mod_table->ModInst, &mod_table->LastModInst,
+        mod_table->Modules, &mod_table->IrqMap );
+    if( err != NvSuccess )
+    {
+        NV_ASSERT( !"NvRmPrivModuleInit failed" );
+        return err;
+    }
+
+    NV_ASSERT( mod_table->LastModInst);
+    NV_ASSERT( mod_table->ModInst );
+
+    mod_table->NumModuleInstances = mod_table->LastModInst -
+        mod_table->ModInst;
+
+    return NvSuccess;
+}
+
+void
+NvRmPrivModuleDeinit( NvRmModuleTable *mod_table )
+{
+}
+
+NvError
+NvRmPrivGetModuleInstance( NvRmDeviceHandle hDevice, NvRmModuleID ModuleId,
+    NvRmModuleInstance **out )
+{
+    NvRmModuleTable *tbl;
+    NvRmModule *module;             // Pointer to module table
+    NvRmModuleInstance *inst;       // Pointer to device instance
+    NvU32 DeviceId;                 // Hardware device id
+    NvU32 Module;
+    NvU32 Instance;
+    NvU32 Bar;
+    NvU32 idx;
+
+    *out = NULL;
+
+    NV_ASSERT( hDevice );
+
+    tbl = NvRmPrivGetModuleTable( hDevice );
+
+    Module   = NVRM_MODULE_ID_MODULE( ModuleId );
+    Instance = NVRM_MODULE_ID_INSTANCE( ModuleId );
+    Bar      = NVRM_MODULE_ID_BAR( ModuleId );
+    NV_ASSERT( (NvU32)Module < (NvU32)NvRmPrivModuleID_Num );
+
+    // Get a pointer to the first instance of this module id type.
+    module = tbl->Modules;
+
+    // Check whether the index is valid or not.
+    if (module[Module].Index == NVRM_MODULE_INVALID)
+    {
+        return NvError_NotSupported;
+    }
+
+    inst = tbl->ModInst + module[Module].Index;
+
+    // Get its device id.
+    DeviceId = inst->DeviceId;
+
+    // find the right instance and bar
+    idx = 0;
+    while( inst->DeviceId == DeviceId )
+    {
+        if( idx == Instance && inst->Bar == Bar )
+        {
+            break;
+        }
+        if( inst->Bar == 0 )
+        {
+            idx++;
+        }
+
+        inst++;
+    }
+
+    // Is this a valid instance and is it of the same hardware type?
+    if( (inst >= tbl->LastModInst) || (DeviceId != inst->DeviceId) )
+    {
+        // Invalid instance.
+        return NvError_BadValue;
+    }
+
+    *out = inst;
+
+    // Check if instance is still valid and not bonded out.
+    // Still returning inst structure.
+    if ( (NvU8)-1 == inst->DevIdx )
+        return NvError_NotSupported;
+
+    return NvSuccess;
+}
+
+void
+NvRmModuleGetBaseAddress( NvRmDeviceHandle hDevice,
+    NvRmModuleID ModuleId, NvRmPhysAddr* pBaseAddress,
+    NvU32* pSize )
+{
+    NvRmModuleInstance *inst;
+
+    NV_ASSERT_SUCCESS(
+        NvRmPrivGetModuleInstance(hDevice, ModuleId, &inst)
+    );
+
+    if (pBaseAddress)
+        *pBaseAddress = inst->PhysAddr;
+    if (pSize)
+        *pSize = inst->Length;
+}
+
+NvU32
+NvRmModuleGetNumInstances(
+    NvRmDeviceHandle hDevice,
+    NvRmModuleID Module)
+{
+    NvError e;
+    NvRmModuleInstance *inst;
+    NvU32 n;
+    NvU32 id;
+
+    e = NvRmPrivGetModuleInstance( hDevice, NVRM_MODULE_ID(Module, 0), &inst);
+    if( e != NvSuccess )
+    {
+        return 0;
+    }
+
+    n = 0;
+    id = inst->DeviceId;
+    while( inst->DeviceId == id )
+    {
+        if( inst->Bar == 0 )
+        {
+            n++;
+        }
+
+        inst++;
+    }
+
+    return n;
+}
+
+NvError
+NvRmModuleGetModuleInfo(
+    NvRmDeviceHandle    hDevice,
+    NvRmModuleID        module,
+    NvU32 *             pNum,
+    NvRmModuleInfo      *pModuleInfo )
+{
+    NvU32   instance = 0;
+    NvU32   i = 0;
+
+    if ( NULL == pNum )
+        return NvError_BadParameter;
+
+    // if !pModuleInfo, returns total number of entries
+    while ( (NULL == pModuleInfo) || (i < *pNum) )
+    {
+        NvRmModuleInstance *inst;
+        NvError e = NvRmPrivGetModuleInstance(
+            hDevice, NVRM_MODULE_ID(module, instance), &inst);
+        if (e != NvSuccess)
+        {
+            if ( !(inst && ((NvU8)-1 == inst->DevIdx)) )
+                break;
+
+             /* else if a module instance not avail (bonded out), continue
+              *  looking for next instance
+              */
+        }
+        else
+        {
+            if ( pModuleInfo )
+            {
+                pModuleInfo->Instance = instance;
+                pModuleInfo->Bar = inst->Bar;
+                pModuleInfo->BaseAddress = inst->PhysAddr;
+                pModuleInfo->Length = inst->Length;
+                pModuleInfo++;
+            }
+
+            i++;
+        }
+
+        instance++;
+    }
+
+    *pNum = i;
+
+    return NvSuccess;
+}
diff --git a/arch/arm/mach-tegra/nvrm/core/common/nvrm_module_private.h b/arch/arm/mach-tegra/nvrm/core/common/nvrm_module_private.h
new file mode 100644
index 000000000000..0648911e0b1c
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/core/common/nvrm_module_private.h
@@ -0,0 +1,79 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef NVRM_MODULE_PRIVATE_H
+#define NVRM_MODULE_PRIVATE_H
+
+#include "nvcommon.h"
+#include "nvrm_init.h"
+#include "nvrm_relocation_table.h"
+#include "nvrm_moduleids.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif  /* __cplusplus */
+
+typedef struct NvRmModuleTableRec
+{
+    NvRmModule Modules[NvRmPrivModuleID_Num];
+    NvRmModuleInstance *ModInst;
+    NvRmModuleInstance *LastModInst;
+    NvU32 NumModuleInstances;
+    NvRmIrqMap IrqMap;
+} NvRmModuleTable;
+
+/**
+ * Initialize the module info via the relocation table.
+ *
+ * @param mod_table The module table
+ * @param reloc_table The relocation table
+ * @param modid The module id conversion function
+ */
+NvError
+NvRmPrivModuleInit(
+    NvRmModuleTable *mod_table,
+    NvU32 *reloc_table);
+
+void
+NvRmPrivModuleDeinit(
+    NvRmModuleTable *mod_table );
+
+NvRmModuleTable *
+NvRmPrivGetModuleTable(
+    NvRmDeviceHandle hDevice );
+
+#ifdef __cplusplus
+}
+#endif  /* __cplusplus */
+
+#endif // NVRM_MODULE_PRIVATE_H
diff --git a/arch/arm/mach-tegra/nvrm/core/common/nvrm_moduleids.h b/arch/arm/mach-tegra/nvrm/core/common/nvrm_moduleids.h
new file mode 100644
index 000000000000..3d63f093b932
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/core/common/nvrm_moduleids.h
@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef NVRM_MODULEIDS_H
+#define NVRM_MODULEIDS_H
+
+#include "nvcommon.h"
+#include "nvrm_module.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif  /* __cplusplus */
+
+/* FIXME - This is depricated. Use NvRmModuleID instead*/ 
+typedef NvRmModuleID NvRmPrivModuleID;
+
+#ifdef __cplusplus
+}
+#endif  /* __cplusplus */
+
+#endif // NVRM_MODULEIDS_H
diff --git a/arch/arm/mach-tegra/nvrm/core/common/nvrm_pinmux.c b/arch/arm/mach-tegra/nvrm/core/common/nvrm_pinmux.c
new file mode 100644
index 000000000000..c792010a0849
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/core/common/nvrm_pinmux.c
@@ -0,0 +1,755 @@
+/*
+ * Copyright (c) 2008-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include "nvcommon.h"
+#include "nvrm_pinmux.h"
+#include "nvrm_drf.h"
+#include "nvassert.h"
+#include "nvrm_hwintf.h"
+#include "ap15/ap15rm_private.h"
+#include "nvrm_pinmux_utils.h"
+#include "nvodm_query_pinmux.h"
+#include <linux/module.h>
+
+#include <mach/pinmux.h>
+#include "../../../gpio-names.h"
+
+/*  Each of the pin mux configurations defined in the pin mux spreadsheet are
+ *  stored in chip-specific tables.  For each configuration, every pad group
+ *  that must be programmed is stored as a single 32b entry, where the register
+ *  offset (for both the tristate and pin mux control registers), field bit
+ *  position (ditto), pin mux mask, and new pin mux state are programmed.
+ *
+ *  The tables are microcode for a simple state machine.  The state machine
+ *  supports subroutine call/return (up to 4 levels of nesting), so that
+ *  pin mux configurations which have substantial repetition can be
+ *  represented compactly by separating common portion of the configurations
+ *  into a subroutine.  Additionally, the state machine supports
+ *  "unprogramming" of the pin mux registers, so that pad groups which are
+ *  incorrectly programmed to mux from a controller may be safely disowned,
+ *  ensuring that no conflicts exist where multiple pad groups are muxing
+ *  the same set of signals.
+ *
+ *  Each module instance array has a reserved "reset" configuration at index
+ *  zero.  This special configuration is used in order to disown all pad
+ *  groups whose reset state refers to the module instance.  When a module
+ *  instance configuration is to be applied, the reset configuration will
+ *  first be applied, to ensure that no conflicts will arise between register
+ *  reset values and the new configuration, followed by the application of
+ *  the requested configuration.
+ *
+ *  Furthermore, for controllers which support dynamic pinmuxing (i.e.,
+ *  the "Multiplexed" pin map option), the last table entry is reserved for
+ *  a "global unset," which will ensure that all configurations are disowned.
+ *  This Multiplexed configuration should be applied before transitioning
+ *  from one configuration to a second one.
+ *
+ *  The table data has been packed into a single 32b entry to minimize code
+ *  footprint using macros similar to the hardware register definitions, so
+ *  that all of the shift and mask operations can be performed with the DRF
+ *  macros.
+ */
+
+#define IO_MODULES() \
+    iomodule_devid(Ata, 1,  "ide")                                         \
+    iomodule_devid(Crt, 1, "crt")                                          \
+    iomodule_devid(Csi, 1, "csi")                                          \
+    iomodule_devid(Dap, 5, "i2s.0", "i2s.1", "i2s.2",                      \
+                                "i2s.3", "i2s.4")                          \
+    iomodule_devid(Display,2, "displaya", "displayb")                      \
+    iomodule_devid(Dsi, 1,  "dsi")                                         \
+    iomodule_devid(Gpio,1,  "gpio")                                        \
+    iomodule_devid(Hdcp,1,  "hdcp")                                        \
+    iomodule_devid(Hdmi,1,  "hdmi")                                        \
+    iomodule_devid(Hsi,1, "hsi")                                           \
+    iomodule_devid(Hsmmc,1, "hsmmc")                                       \
+    iomodule_devid(I2s,1, "i2s")                                           \
+    iomodule_devid(I2c,3, "tegra_i2c.1", "tegra_i2c.2", "tegra_i2c.3")     \
+    iomodule_devid(I2c_Pmu,1, "tegra_i2c.0")                               \
+    iomodule_devid(Kbd, 1, "tegra_kbc")                                    \
+    iomodule_devid(Mio, 1, "mio")                                          \
+    iomodule_devid(Nand,1, "tegra_nand")                                   \
+    iomodule_devid(Pwm, 1, "pwm")                                          \
+    iomodule_devid(Sdio,4, "tegra-sdhci.0", "tegra-sdhci.1",               \
+                        "tegra-sdhci.2", "tegra-sdhci.3")                  \
+    iomodule_devid(Sflash,1, "tegra_spi.4")                                \
+    iomodule_devid(Slink,1, "slink")                                       \
+    iomodule_devid(Spdif,1, "spdif")                                       \
+    iomodule_devid(Spi, 4, "tegra_spi.0", "tegra_spi.1", "tegra_spi.2",    \
+                        "tegra_spi.3")                                     \
+    iomodule_devid(Twc, 1, "twc")                                          \
+    iomodule_devid(Tvo, 1, "tvo")                                          \
+    iomodule_devid(Uart, 5, "tegra_uart.0", "tegra_uart.1",                \
+                        "tegra_uart.2", "tegra_uart.3",                    \
+                        "tegra_uart.4")                                    \
+    iomodule_devid(Usb, 1, "Usb")                                          \
+    iomodule_devid(Vdd, 1, "Vdd")                                          \
+    iomodule_devid(VideoInput, 1, "vi")                                    \
+    iomodule_devid(Xio, 1, "xio")                                          \
+    iomodule_devid(ExternalClock, 3, "extclk.0", "extclk.1", "extclk.2")   \
+    iomodule_devid(Ulpi, 1, "tegra-ehci.1")                                \
+    iomodule_devid(OneWire, 1, "tegra_w1")                                 \
+    iomodule_devid(SyncNor, 1, "snor")                                     \
+    iomodule_devid(PciExpress, 1, "tegra_pcie")                            \
+    iomodule_devid(Trace, 1, "etm")                                        \
+    iomodule_devid(Tsense,1, "tsensor")                                    \
+    iomodule_devid(BacklightPwm,4, "blight.d1.p0", "blight.d1.p1",         \
+                                 "blight.d2.p0", "blight.d2.p1")
+
+struct tegra_iomodule_devlist
+{
+    int t_inst;
+    const char **dev_list;
+};
+
+#define iomodule_devid(mod, tinst, ...) \
+    static const char *tegra_iomodule_##mod[] = {__VA_ARGS__};
+IO_MODULES()
+
+#undef iomodule_devid
+#define iomodule_devid(mod, tinst, ...)    \
+    [NvOdmIoModule_##mod] = {              \
+         .t_inst = tinst,                  \
+         .dev_list = tegra_iomodule_##mod, \
+     },
+
+static const struct  tegra_iomodule_devlist iomodule_devlist[NvOdmIoModule_Num] = {
+    IO_MODULES()
+};
+
+extern struct tegra_pingroup_config *tegra_pinmux_get(const char *dev_id,
+         int config, int *len);
+extern int gpio_get_pinmux_group(int gpio_nr);
+
+typedef struct
+{
+    void
+    (*pfnEnableExtClock)(
+        NvRmDeviceHandle hDevice,
+        struct tegra_pingroup_config *pin_config,
+        int len,
+        NvBool ClockState);
+    NvU32
+    (*pfnGetExtClockFreq)(
+        NvRmDeviceHandle hDevice,
+        struct tegra_pingroup_config *pin_config,
+        int len);
+    NvError
+    (*pfnInterfaceCaps)(
+        NvOdmIoModule Module,
+        NvU32 Instance,
+        NvU32 PinMap,
+        void *pCaps);
+    NvError
+    (*pfnGetStraps)(
+        NvRmDeviceHandle hDevice,
+        NvRmStrapGroup StrapGroup,
+        NvU32* pStrapValue);
+    void
+    (*pfnSetDefaultTristate)(
+        NvRmDeviceHandle hDevice);
+} NvPinmuxPrivMethods;
+
+static NvPinmuxPrivMethods* NvRmPrivGetPinmuxMethods(NvRmDeviceHandle hDevice)
+{
+    static NvPinmuxPrivMethods *p;
+    static NvPinmuxPrivMethods s_Ap20Methods =
+    {
+        NvRmPrivAp20EnableExternalClockSource,
+        NvRmPrivAp20GetExternalClockSourceFreq,
+        NvRmPrivAp20GetModuleInterfaceCaps,
+        NvRmAp20GetStraps,
+        NvRmAp20SetDefaultTristate
+    };
+
+    NV_ASSERT(hDevice);
+    if (hDevice->ChipId.Id == 0x20)
+    {
+        p = &s_Ap20Methods;
+    }
+    else
+    {
+        NV_ASSERT(!"Unsupported chip ID");
+        p = NULL;
+    }
+    return p;
+}
+
+static void NvRmPrivApplyAllModuleTypePinMuxes(
+    NvRmDeviceHandle hDevice,
+    NvU32 IoModule,
+    NvBool ApplyReset,
+    NvBool ApplyActual)
+{
+    const NvU32 *OdmConfigs;
+    NvU32 NumOdmConfigs;
+    struct tegra_pingroup_config *pin_config;
+    int len = 0;
+    int Instance = 0;
+    NvU32 config;
+
+    if (ApplyActual)
+        NvOdmQueryPinMux(IoModule, &OdmConfigs, &NumOdmConfigs);
+    else
+    {
+        OdmConfigs = NULL;
+        NumOdmConfigs = 0;
+    }
+
+    for (Instance = 0; Instance < iomodule_devlist[IoModule].t_inst; ++Instance)
+    {
+        /*  Apply the reset configuration to ensure that the module is in
+         *  a sane state, then apply the ODM configuration, if one is specified
+         */
+        if (ApplyReset)
+        {
+            if (iomodule_devlist[IoModule].dev_list[Instance] != NULL)
+            {
+                pin_config = tegra_pinmux_get(iomodule_devlist[IoModule].dev_list[Instance],
+                            0, &len);
+                    if (pin_config != NULL)
+                    {
+                        tegra_pinmux_config_pinmux_table(pin_config, len, false);
+                    }
+            }
+        }
+        if (NumOdmConfigs && ApplyActual)
+        {
+            config = *OdmConfigs;
+            if (config)
+            {
+                if (iomodule_devlist[IoModule].dev_list[Instance] != NULL)
+                {
+                    pin_config = tegra_pinmux_get(
+                                        iomodule_devlist[IoModule].dev_list[Instance],
+                                        config, &len);
+                    if (pin_config != NULL)
+                    {
+                        tegra_pinmux_config_pinmux_table(pin_config, len, true);
+                    }
+                }
+            }
+            NumOdmConfigs--;
+            OdmConfigs++;
+        }
+    }
+
+    /*  If the ODM pin mux table is created correctly, there should be
+    *  the same number of ODM configs as module instances; however, we
+    *  allow the ODM to specify fewer configs than instances with assumed
+    *  zeros for undefined modules */
+    while (NumOdmConfigs)
+    {
+        NV_ASSERT((*OdmConfigs==0) &&
+                    "More ODM configs than module instances!\n");
+        NumOdmConfigs--;
+        OdmConfigs++;
+    }
+}
+
+static void NvRmPrivApplyAllPinMuxes(
+    NvRmDeviceHandle hDevice,
+    NvBool First)
+{
+    NvOdmIoModule IoModule;
+
+    for (IoModule = NvOdmIoModule_Ata; IoModule < NvOdmIoModule_Num; IoModule++)
+    {
+        NvBool ApplyActual = NV_TRUE;
+        /* During early boot, the only device that has its pin mux correctly
+         * initialized is the I2C PMU controller, so that primitive peripherals
+         * (EEPROMs, PMU, RTC) can be accessed during the boot process */
+        if (First)
+            ApplyActual = (IoModule==NvOdmIoModule_I2c_Pmu);
+
+        NvRmPrivApplyAllModuleTypePinMuxes(hDevice, IoModule, First,
+                                           ApplyActual);
+    }
+}
+/**
+ * RmInitPinMux will program the pin mux settings for all IO controllers to
+ * the ODM-selected value (or a safe reset value, if no value is defined in
+ * the ODM query.
+ *
+ * It will also read the current value of the tristate registers, to
+ * initialize the reference count
+ */
+void NvRmInitPinMux(
+    NvRmDeviceHandle hDevice,
+    NvBool First)
+{
+    NvPinmuxPrivMethods *p = NvRmPrivGetPinmuxMethods(hDevice);
+    if (First)
+        (p->pfnSetDefaultTristate)(hDevice);
+
+#if (!NVOS_IS_WINDOWS_CE || NV_OAL)
+    NvRmPrivApplyAllPinMuxes(hDevice, First);
+#endif
+}
+
+/* RmPinMuxConfigSelect sets a specific module to a specific configuration.
+ * It is used for multiplexed controllers, and should only be called by the
+ * ODM service function NvOdmPinMuxSet */
+void NvRmPinMuxConfigSelect(
+    NvRmDeviceHandle hDevice,
+    NvOdmIoModule IoModule,
+    NvU32 Instance,
+    NvU32 Configuration)
+{
+    struct tegra_pingroup_config *pin_config;
+    int len = 0;
+
+    NV_ASSERT(hDevice);
+    if (!hDevice)
+        return;
+    if (Instance >= iomodule_devlist[IoModule].t_inst)
+	return;
+
+    if (iomodule_devlist[IoModule].dev_list[Instance] != NULL)
+    {
+        pin_config = tegra_pinmux_get(iomodule_devlist[IoModule].dev_list[Instance],
+                            Configuration, &len);
+        if (pin_config != NULL)
+        {
+            tegra_pinmux_config_pinmux_table(pin_config, len, true);
+        }
+    }
+}
+
+/* RmPinMuxConfigSetTristate will either enable or disable the tristate for a
+ * specific IO module configuration.  It is called by the ODM service function
+ * OdmPinMuxConfigSetTristate, and by the RM function SetModuleTristate.  RM
+ * client drivers should only call RmSetModuleTristate, which will program the
+ * tristate correctly based on the ODM query configuration. */
+void NvRmPinMuxConfigSetTristate(
+    NvRmDeviceHandle hDevice,
+    NvOdmIoModule IoModule,
+    NvU32 Instance,
+    NvU32 Configuration,
+    NvBool EnableTristate)
+{
+    struct tegra_pingroup_config *pin_config;
+    int len = 0;
+    tegra_tristate_t tristate;
+
+    NV_ASSERT(hDevice);
+    if (!hDevice)
+        return;
+
+    if (Instance >= iomodule_devlist[IoModule].t_inst)
+        return;
+
+    if (iomodule_devlist[IoModule].dev_list[Instance] != NULL)
+    {
+        pin_config = tegra_pinmux_get(iomodule_devlist[IoModule].dev_list[Instance],
+                        Configuration, &len);
+        if (pin_config != NULL)
+        {
+            tristate = (EnableTristate)? TEGRA_TRI_TRISTATE: TEGRA_TRI_NORMAL;
+            tegra_pinmux_config_tristate_table(pin_config, len, tristate);
+        }
+    }
+}
+
+NvError NvRmSetOdmModuleTristate(
+    NvRmDeviceHandle hDevice,
+    NvU32 OdmModule,
+    NvU32 OdmInstance,
+    NvBool EnableTristate)
+{
+    const NvU32 *OdmConfigs;
+    NvU32 NumOdmConfigs;
+
+    NV_ASSERT(hDevice);
+    if (!hDevice)
+        return NvError_BadParameter;
+
+    NvOdmQueryPinMux(OdmModule, &OdmConfigs, &NumOdmConfigs);
+
+    if ((OdmInstance >= NumOdmConfigs) || !OdmConfigs[OdmInstance])
+        return NvError_NotSupported;
+
+    NvRmPinMuxConfigSetTristate(hDevice, OdmModule,
+        OdmInstance, OdmConfigs[OdmInstance], EnableTristate);
+
+    return NvSuccess;
+}
+
+NvU32 NvRmPrivRmModuleToOdmModule(
+    NvU32 ChipId,
+    NvU32 RmModule,
+    NvOdmIoModule *pOdmModules,
+    NvU32 *pOdmInstances)
+{
+    NvU32 Cnt = 0;
+    NvBool Result = NV_FALSE;
+
+    NV_ASSERT(pOdmModules && pOdmInstances);
+
+    if (ChipId==0x20)
+    {
+        Result = NvRmPrivAp20RmModuleToOdmModule(RmModule,
+             pOdmModules, pOdmInstances, &Cnt);
+    } else {
+        return 0;
+    }
+
+    /*  A default mapping is provided for all standard I/O controllers,
+     *  if the chip-specific implementation does not implement a mapping */
+    if (!Result)
+    {
+        NvRmModuleID Module = NVRM_MODULE_ID_MODULE(RmModule);
+        NvU32 Instance = NVRM_MODULE_ID_INSTANCE(RmModule);
+
+        Cnt = 1;
+        switch (Module) {
+        case NvRmModuleID_Display:
+            *pOdmModules = NvOdmIoModule_Display;
+            *pOdmInstances = Instance;
+            break;
+        case NvRmModuleID_Ide:
+            *pOdmModules = NvOdmIoModule_Ata;
+            *pOdmInstances = Instance;
+            break;
+        case NvRmModuleID_Vi:
+            *pOdmModules = NvOdmIoModule_VideoInput;
+            *pOdmInstances = Instance;
+            break;
+        case NvRmModuleID_Usb2Otg:
+            *pOdmModules = NvOdmIoModule_Usb;
+            *pOdmInstances = Instance;
+            break;
+        case NvRmModuleID_Pwm:
+            *pOdmModules = NvOdmIoModule_Pwm;
+            *pOdmInstances = Instance;
+            break;
+        case NvRmModuleID_Twc:
+            *pOdmModules = NvOdmIoModule_Twc;
+            *pOdmInstances = Instance;
+            break;
+        case NvRmModuleID_Hsmmc:
+            *pOdmModules = NvOdmIoModule_Hsmmc;
+            *pOdmInstances = Instance;
+            break;
+        case NvRmModuleID_Sdio:
+            *pOdmModules = NvOdmIoModule_Sdio;
+            *pOdmInstances = Instance;
+            break;
+        case NvRmModuleID_Nand:
+            *pOdmModules = NvOdmIoModule_Nand;
+            *pOdmInstances = Instance;
+            break;
+        case NvRmModuleID_I2c:
+            *pOdmModules = NvOdmIoModule_I2c;
+            *pOdmInstances = Instance;
+            break;
+        case NvRmModuleID_Spdif:
+            *pOdmModules = NvOdmIoModule_Spdif;
+            *pOdmInstances = Instance;
+            break;
+        case NvRmModuleID_Uart:
+            *pOdmModules = NvOdmIoModule_Uart;
+            *pOdmInstances = Instance;
+            break;
+        case NvRmModuleID_Csi:
+            *pOdmModules = NvOdmIoModule_Csi;
+            *pOdmInstances = Instance;
+            break;
+        case NvRmModuleID_Hdmi:
+            *pOdmModules = NvOdmIoModule_Hdmi;
+            *pOdmInstances = Instance;
+            break;
+        case NvRmModuleID_Mipi:
+            *pOdmModules = NvOdmIoModule_Hsi;
+            *pOdmInstances = Instance;
+            break;
+        case NvRmModuleID_Tvo:
+            pOdmModules[0] = NvOdmIoModule_Tvo;
+            pOdmModules[1] = NvOdmIoModule_Crt;
+            pOdmInstances[0] = 0;
+            pOdmInstances[1] = 0;
+            Cnt = 2;
+            break;
+        case NvRmModuleID_Dsi:
+            *pOdmModules = NvOdmIoModule_Dsi;
+            *pOdmInstances = Instance;
+            break;
+        case NvRmModuleID_Dvc:
+            *pOdmModules = NvOdmIoModule_I2c_Pmu;
+            *pOdmInstances = Instance;
+            break;
+        case NvRmPrivModuleID_Mio_Exio:
+            *pOdmModules = NvOdmIoModule_Mio;
+            *pOdmInstances = Instance;
+            break;
+        case NvRmModuleID_Xio:
+            *pOdmModules = NvOdmIoModule_Xio;
+            *pOdmInstances = Instance;
+            break;
+        case NvRmModuleID_Spi:
+            *pOdmModules = NvOdmIoModule_Sflash;
+            *pOdmInstances = Instance;
+            break;
+        case NvRmModuleID_Slink:
+            *pOdmModules = NvOdmIoModule_Spi;
+            *pOdmInstances = Instance;
+            break;
+        case NvRmModuleID_Kbc:
+            *pOdmModules = NvOdmIoModule_Kbd;
+            *pOdmInstances = Instance;
+            break;
+        default:
+            //  all the RM modules which have no ODM analogs (like 3d)
+            Cnt = 0;
+            break;
+        }
+    }
+
+    return Cnt;
+}
+
+/* RmSetModuleTristate will enable / disable the pad tristates for the
+ * selected pin mux configuration of an IO module.  */
+NvError NvRmSetModuleTristate(
+    NvRmDeviceHandle hDevice,
+    NvRmModuleID RmModule,
+    NvBool EnableTristate)
+{
+    const NvU32 *OdmConfigs;
+    NvU32 NumOdmConfigs;
+    NvU32 OdmModules[4];
+    NvU32 OdmInstances[4];
+    NvU32 NumOdmModules = 0;
+    NvU32 i;
+
+    NV_ASSERT(hDevice);
+    if (!hDevice)
+        return NvError_BadParameter;
+
+    NumOdmModules =
+        NvRmPrivRmModuleToOdmModule(hDevice->ChipId.Id,
+            RmModule, (NvOdmIoModule*)OdmModules, OdmInstances);
+    if (!NumOdmModules)
+        return NvError_NotSupported;
+
+    /* return NotSupported if the ODM has not defined a pin mux configuration
+     * for this module. */
+    for (i=0; i<NumOdmModules; i++)
+    {
+        NvOdmQueryPinMux(OdmModules[i], &OdmConfigs, &NumOdmConfigs);
+        if ((!NumOdmConfigs) || (!OdmConfigs[OdmInstances[i]]))
+            return NvError_NotSupported;
+        if (OdmInstances[i] >= NumOdmConfigs)
+        {
+            NV_DEBUG_PRINTF(("Attempted to set TRISTATE for Module %u, Instance"
+                " %u (ODM module %u instance %u) with undefined config\n",
+                NVRM_MODULE_ID_MODULE(RmModule),
+                NVRM_MODULE_ID_INSTANCE(RmModule),
+                OdmModules[i], OdmInstances[i]));
+            return NvError_NotSupported;
+            //  NV_ASSERT(OdmInstances[i] < NumOdmConfigs);
+        }
+    }
+
+    for (i=0; i<NumOdmModules; i++)
+    {
+        NvOdmQueryPinMux(OdmModules[i], &OdmConfigs, &NumOdmConfigs);
+        NV_ASSERT(OdmInstances[i] < NumOdmConfigs);
+        NvRmPinMuxConfigSetTristate(hDevice, OdmModules[i],
+            OdmInstances[i], OdmConfigs[OdmInstances[i]], EnableTristate);
+    }
+    return NvSuccess;
+}
+
+void NvRmSetGpioTristate(
+    NvRmDeviceHandle hDevice,
+    NvU32 Port,
+    NvU32 Pin,
+    NvBool EnableTristate)
+{
+    int gpio_nr;
+    tegra_pingroup_t pg;
+    tegra_tristate_t ts;
+    int err;
+
+    gpio_nr = Port*8 + Pin;
+
+    pg = gpio_get_pinmux_group(gpio_nr);
+    if (pg >= 0)
+    {
+        ts = (EnableTristate == NV_TRUE)?TEGRA_TRI_TRISTATE: TEGRA_TRI_NORMAL;
+        err = tegra_pinmux_set_tristate(pg, ts);
+        if (err < 0)
+            printk(KERN_ERR "pinmux: can't set pingroup %d tristate"
+                " to %d: %d\n", pg,
+                ts, err);
+    }
+}
+
+NvU32 NvRmExternalClockConfig(
+    NvRmDeviceHandle hDevice,
+    NvU32 IoModule,
+    NvU32 Instance,
+    NvU32 Config,
+    NvBool EnableTristate)
+{
+    NvU32 ret = 0;
+    struct tegra_pingroup_config *pin_config;
+    int len = 0;
+    tegra_tristate_t tristate;
+    NvPinmuxPrivMethods *p = NvRmPrivGetPinmuxMethods(hDevice);
+
+
+    NV_ASSERT(hDevice);
+
+    if (!hDevice)
+        return 0;
+
+    if (IoModule != NvOdmIoModule_ExternalClock)
+        return 0;
+
+    if (Instance >= iomodule_devlist[IoModule].t_inst)
+        return 0;
+
+    if (iomodule_devlist[IoModule].dev_list[Instance] == NULL)
+        return 0;
+
+    if (!EnableTristate)
+    {
+        if (Config)
+        {
+            pin_config = tegra_pinmux_get(iomodule_devlist[IoModule].dev_list[Instance],
+                            Config, &len);
+            if (pin_config != NULL)
+            {
+                tegra_pinmux_config_pinmux_table(pin_config, len, true);
+            }
+        }
+    }
+
+    /* setting tri state */
+    pin_config = tegra_pinmux_get(iomodule_devlist[IoModule].dev_list[Instance],
+                                   Config, &len);
+    if (pin_config != NULL)
+    {
+        tristate = (EnableTristate)?TEGRA_TRI_TRISTATE: TEGRA_TRI_NORMAL;
+        tegra_pinmux_config_tristate_table(pin_config, len, tristate);
+        (p->pfnEnableExtClock)(hDevice, pin_config, len, !EnableTristate);
+        ret = (p->pfnGetExtClockFreq)(hDevice, pin_config, len);
+    }
+    return ret;
+}
+
+NvError NvRmGetModuleInterfaceCapabilities(
+    NvRmDeviceHandle hRm,
+    NvRmModuleID ModuleId,
+    NvU32 CapStructSize,
+    void *pCaps)
+{
+    NvU32 NumOdmConfigs;
+    const NvU32 *OdmConfigs;
+    NvOdmIoModule OdmModules[4];
+    NvU32 OdmInstances[4];
+    NvU32 NumOdmModules;
+    NvPinmuxPrivMethods *p = NvRmPrivGetPinmuxMethods(hRm);
+
+    NV_ASSERT(hRm);
+    NV_ASSERT(pCaps);
+
+    if (!hRm || !pCaps)
+        return NvError_BadParameter;
+
+    NumOdmModules =
+        NvRmPrivRmModuleToOdmModule(hRm->ChipId.Id, ModuleId,
+            (NvOdmIoModule *)OdmModules, OdmInstances);
+    NV_ASSERT(NumOdmModules<=1);
+
+    if (!NumOdmModules)
+        return NvError_NotSupported;
+
+    switch (OdmModules[0]) {
+    case NvOdmIoModule_Hsmmc:
+    case NvOdmIoModule_Sdio:
+        if (CapStructSize != sizeof(NvRmModuleSdmmcInterfaceCaps))
+        {
+            NV_ASSERT(!"Invalid cap struct size");
+            return NvError_BadParameter;
+        }
+        break;
+    case NvOdmIoModule_Pwm:
+        if (CapStructSize != sizeof(NvRmModulePwmInterfaceCaps))
+        {
+            NV_ASSERT(!"Invalid cap struct size");
+            return NvError_BadParameter;
+        }
+        break;
+    case NvOdmIoModule_Nand:
+        if (CapStructSize != sizeof(NvRmModuleNandInterfaceCaps))
+        {
+            NV_ASSERT(!"Invalid cap struct size");
+            return NvError_BadParameter;
+        }
+        break;
+
+    case NvOdmIoModule_Uart:
+        if (CapStructSize != sizeof(NvRmModuleUartInterfaceCaps))
+        {
+            NV_ASSERT(!"Invalid cap struct size");
+            return NvError_BadParameter;
+        }
+        break;
+
+    default:
+        return NvError_NotSupported;
+    }
+
+    NvOdmQueryPinMux(OdmModules[0], &OdmConfigs, &NumOdmConfigs);
+    if (OdmInstances[0]>=NumOdmConfigs || !OdmConfigs[OdmInstances[0]])
+        return NvError_NotSupported;
+
+    return (p->pfnInterfaceCaps)(OdmModules[0],OdmInstances[0],
+                            OdmConfigs[OdmInstances[0]],pCaps);
+}
+
+NvError NvRmGetStraps(
+    NvRmDeviceHandle hDevice,
+    NvRmStrapGroup StrapGroup,
+    NvU32* pStrapValue)
+{
+    NvPinmuxPrivMethods *p = NvRmPrivGetPinmuxMethods(hDevice);
+    NV_ASSERT(hDevice && pStrapValue);
+
+    if (!hDevice || !pStrapValue)
+        return NvError_BadParameter;
+    return (p->pfnGetStraps)(hDevice, StrapGroup, pStrapValue);
+}
+
diff --git a/arch/arm/mach-tegra/nvrm/core/common/nvrm_pinmux_utils.h b/arch/arm/mach-tegra/nvrm/core/common/nvrm_pinmux_utils.h
new file mode 100644
index 000000000000..3a90c08a9070
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/core/common/nvrm_pinmux_utils.h
@@ -0,0 +1,326 @@
+/*
+ * Copyright (c) 2008-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef NVRM_PINMUX_UTILS_H
+#define NVRM_PINMUX_UTILS_H
+
+/*
+ * nvrm_pinmux_utils.h defines the pinmux macros to implement for the resource
+ * manager.
+ */
+
+#include "nvcommon.h"
+#include "nvrm_pinmux.h"
+#include "nvrm_drf.h"
+#include "nvassert.h"
+#include "nvrm_hwintf.h"
+#include "nvodm_modules.h"
+
+#include <mach/pinmux.h>
+
+// This is to disable trisate refcounting.
+#define SKIP_TRISTATE_REFCNT 0
+
+/*  The pin mux code supports run-time trace debugging of all updates to the
+ *  pin mux & tristate registers by embedding strings (cast to NvU32s) into the
+ *  control tables.
+ */
+#define NVRM_PINMUX_DEBUG_FLAG 0
+#define NVRM_PINMUX_SET_OPCODE_SIZE_RANGE 3:1
+
+
+#if NVRM_PINMUX_DEBUG_FLAG
+NV_CT_ASSERT(sizeof(NvU32)==sizeof(const char*));
+#endif
+
+//  The extra strings bloat the size of Set/Unset opcodes
+#define NVRM_PINMUX_SET_OPCODE_SIZE ((NVRM_PINMUX_DEBUG_FLAG)?NVRM_PINMUX_SET_OPCODE_SIZE_RANGE)
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif  /* __cplusplus */
+
+typedef enum {
+    PinMuxConfig_OpcodeExtend = 0,
+    PinMuxConfig_Set = 1,
+    PinMuxConfig_Unset = 2,
+    PinMuxConfig_BranchLink = 3,
+} PinMuxConfigStates;
+
+typedef enum {
+    PinMuxOpcode_ConfigEnd = 0,
+    PinMuxOpcode_ModuleDone = 1,
+    PinMuxOpcode_SubroutinesDone = 2,
+} PinMuxConfigExtendOpcodes;
+
+//  for extended opcodes, this field is set with the extended opcode
+#define MUX_ENTRY_0_OPCODE_EXTENSION_RANGE 3:2
+//  The state for this entry
+#define MUX_ENTRY_0_STATE_RANGE 1:0
+
+#define MAX_NESTING_DEPTH 4
+
+/*  This macro is used for opcode entries in the tables */
+#define PIN_MUX_OPCODE(_OP_) \
+    (NV_DRF_NUM(MUX,ENTRY,STATE,PinMuxConfig_OpcodeExtend) | \
+     NV_DRF_NUM(MUX,ENTRY,OPCODE_EXTENSION,(_OP_)))
+
+/*  This is a dummy entry in the array which indicates that all setting/unsetting for
+ *  a configuration is complete. */
+#define CONFIGEND() PIN_MUX_OPCODE(PinMuxOpcode_ConfigEnd)
+
+/*  This is a dummy entry in the array which indicates that the last configuration
+ *  for the module instance has been passed. */
+#define MODULEDONE()  PIN_MUX_OPCODE(PinMuxOpcode_ModuleDone)
+
+/*  This is a dummy entry in the array which indicates that all "extra" configurations
+ *  used by sub-routines have been passed. */
+#define SUBROUTINESDONE() PIN_MUX_OPCODE(PinMuxOpcode_SubroutinesDone)
+
+/*  This macro is used to insert a branch-and-link from one configuration to another */
+#define BRANCH(_ADDR_) \
+     (NV_DRF_NUM(MUX,ENTRY,STATE,PinMuxConfig_BranchLink) | \
+      NV_DRF_NUM(MUX,ENTRY,BRANCH_ADDRESS,(_ADDR_)))
+
+/**  RmInitPinMux will program the pin mux settings for all IO controllers to
+  *  the ODM-selected value (or a safe reset value, if no value is defined in
+  *  the ODM query.
+  *  It will also read the current value of the tristate registers, to
+  *  initialize the reference count
+  *
+  * @param hDevice The RM instance
+  * @param First Indicates whether to perform just safe-reset and DVC
+  *     initialization, for early boot, or full initialization
+  */
+void NvRmInitPinMux(
+    NvRmDeviceHandle hDevice,
+    NvBool First);
+
+/**  RmPinMuxConfigSelect sets a specific module to a specific configuration.  It is used
+  *  for multiplexed controllers, and should only be called by modules which support
+  *  multiplexing.  Note that this interface uses the IoModule enumerant, not the RmModule.
+  *
+  *@param hDevice The RM instance
+  *@param IoModule The module to set
+  *@param Instance The instance number of the Module
+  *@param Configuaration The module's configuration to set
+  */
+
+void NvRmPinMuxConfigSelect(
+    NvRmDeviceHandle hDevice,
+    NvOdmIoModule IoModule,
+    NvU32 Instance,
+    NvU32 Configuration);
+
+/** RmPinMuxConfigSetTristate will either enable or disable the tristate for a specific
+  * IO module configuration.  It is used for multiplexed controllers, and should only be
+  * called by modules which support multiplexing.   Note that this interface uses the
+  * IoModule enumerant, not the RmModule.
+  *
+  *@param hDevice The RM instance
+  *@param RMModule The module to set
+  *@param Instance  The instance number of the module.
+  *@param Configuaration The module's configuration to set
+  *@param EnableTristate NV_TRUE will tristate the specified pins, NV_FALSE will un-tristate
+  */
+
+void NvRmPinMuxConfigSetTristate(
+    NvRmDeviceHandle hDevice,
+    NvOdmIoModule IoModule,
+    NvU32 Instance,
+    NvU32 Configuration,
+    NvBool EnableTristate);
+
+/** NvRmSetGpioTristate will either enable or disable the tristate for GPIO ports.
+  * RM client gpio should only call NvRmSetGpioTristate,
+  * which will program the tristate correctly based pins of the particular port.
+  *
+  *@param hDevice The RM instance
+  *@param Port The GPIO port to set
+  *@param Pin The Pinnumber  of the port to set.
+  *@param EnableTristate NV_TRUE will tristate the specified pins, NV_FALSE will un-tristate
+  */
+void NvRmSetGpioTristate(
+    NvRmDeviceHandle hDevice,
+    NvU32 Port,
+    NvU32 Pin,
+    NvBool EnableTristate);
+
+/** NvRmPrivRmModuleToOdmModule will perform the mapping of RM modules to
+ *  ODM modules and instances, using the chip-specific mapping wherever
+ *  necessary */
+NvU32 NvRmPrivRmModuleToOdmModule(
+    NvU32 ChipId,
+    NvU32 RmModule,
+    NvOdmIoModule *pOdmModules,
+    NvU32 *pOdmInstances);
+
+
+//  Forward declarations for all chip-specific helper functions
+NvError NvRmPrivAp15GetModuleInterfaceCaps(
+    NvOdmIoModule Module,
+    NvU32 Instance,
+    NvU32 Config,
+    void* pCaps);
+
+NvError NvRmPrivAp16GetModuleInterfaceCaps(
+    NvOdmIoModule Module,
+    NvU32 Instance,
+    NvU32 Config,
+    void* pCaps);
+
+NvError NvRmPrivAp20GetModuleInterfaceCaps(
+    NvOdmIoModule Module,
+    NvU32 Instance,
+    NvU32 Config,
+    void* pCaps);
+
+const NvU32*** NvRmAp15GetPinMuxConfigs(NvRmDeviceHandle hDevice);
+
+const NvU32*** NvRmAp16GetPinMuxConfigs(NvRmDeviceHandle hDevice);
+
+const NvU32*** NvRmAp20GetPinMuxConfigs(NvRmDeviceHandle hDevice);
+
+NvBool NvRmAp15GetPinGroupForGpio(
+    NvRmDeviceHandle hDevice,
+    NvU32 Port,
+    NvU32 Pin,
+    NvU32 *pMapping);
+
+NvBool NvRmAp20GetPinGroupForGpio(
+    NvRmDeviceHandle hDevice,
+    NvU32 Port,
+    NvU32 Pin,
+    NvU32* pMapping);
+
+void NvRmPrivAp15EnableExternalClockSource(
+   NvRmDeviceHandle hDevice,
+   const NvU32* pModuleProgram,
+   NvU32 Config,
+   NvBool EnableClock);
+
+void NvRmPrivAp20EnableExternalClockSource(
+    NvRmDeviceHandle hDevice,
+    struct tegra_pingroup_config *pin_config,
+    int len,
+    NvBool ClockState);
+
+NvU32 NvRmPrivAp15GetExternalClockSourceFreq(
+    NvRmDeviceHandle hDevice,
+    const NvU32* pModuleProgram,
+    NvU32 Config);
+
+NvU32
+NvRmPrivAp20GetExternalClockSourceFreq(
+    NvRmDeviceHandle hDevice,
+    struct tegra_pingroup_config *pin_config,
+    int len);
+
+NvBool NvRmPrivAp15RmModuleToOdmModule(
+    NvRmModuleID ModuleID,
+    NvOdmIoModule* pOdmModules,
+    NvU32* pOdmInstances,
+    NvU32 *pCnt);
+
+NvBool NvRmPrivAp16RmModuleToOdmModule(
+    NvRmModuleID ModuleID,
+    NvOdmIoModule* pOdmModules,
+    NvU32* pOdmInstances,
+    NvU32 *pCnt);
+
+NvBool NvRmPrivAp20RmModuleToOdmModule(
+    NvRmModuleID ModuldID,
+    NvOdmIoModule* pOdmModules,
+    NvU32* pOdmInstances,
+    NvU32 *pCnt);
+
+/**
+ * Chip-specific functions to get SoC strap value for the given strap group.
+ *
+ * @param hDevice The RM instance
+ * @param StrapGroup Strap group to be read.
+ * @pStrapValue A pointer to the returned strap group value.
+ *
+ * @retval NvSuccess if strap value is read successfully
+ * @retval NvError_NotSupported if the specified strap group does not
+ *   exist on the current SoC.
+ */
+NvError
+NvRmAp15GetStraps(
+    NvRmDeviceHandle hDevice,
+    NvRmStrapGroup StrapGroup,
+    NvU32* pStrapValue);
+
+NvError
+NvRmAp20GetStraps(
+    NvRmDeviceHandle hDevice,
+    NvRmStrapGroup StrapGroup,
+    NvU32* pStrapValue);
+
+void NvRmPrivAp15SetPadTristates(
+    NvRmDeviceHandle hDevice,
+    const NvU32* Module,
+    NvU32 Config,
+    NvBool EnableTristate);
+
+void NvRmPrivAp15SetPinMuxCtl(
+    NvRmDeviceHandle hDevice,
+    const NvU32* Module,
+    NvU32 Config);
+
+void NvRmPrivAp15InitTrisateRefCount(NvRmDeviceHandle hDevice);
+
+const NvU32*
+NvRmPrivAp15FindConfigStart(
+    const NvU32* Instance,
+    NvU32 Config,
+    NvU32 EndMarker);
+
+void
+NvRmPrivAp15SetGpioTristate(
+    NvRmDeviceHandle hDevice,
+    NvU32 Port,
+    NvU32 Pin,
+    NvBool EnableTristate);
+
+void NvRmAp15SetDefaultTristate (NvRmDeviceHandle hDevice);
+
+void NvRmAp20SetDefaultTristate (NvRmDeviceHandle hDevice);
+
+#ifdef __cplusplus
+}
+#endif  /* __cplusplus */
+
+#endif // NVRM_PINMUX_UTILS_H
+
+
diff --git a/arch/arm/mach-tegra/nvrm/core/common/nvrm_pmu.c b/arch/arm/mach-tegra/nvrm/core/common/nvrm_pmu.c
new file mode 100644
index 000000000000..d00fc4b1083b
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/core/common/nvrm_pmu.c
@@ -0,0 +1,641 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include "nvrm_pmu.h"
+#include "nvodm_pmu.h"
+#include "nvassert.h"
+#include "nvrm_interrupt.h"
+#include "nvrm_moduleids.h"
+#include "nvrm_pmu_private.h"
+#include "nvrm_power_private.h"
+#include "nvrm_clocks.h"
+#include "nvrm_structure.h"
+#include "nvodm_query_discovery.h"
+#include "nvodm_query.h"
+
+
+// TODO: after testing is completed, remove this macro
+// "1" - keep PMU rails always On, "0" - allows to power Off PMU rails
+#define PMU_RAILS_NEVER_OFF (0)
+
+// Retry count for voltage control API
+#define VOLTAGE_CONTROL_RETRY_CNT (2)
+
+/*
+ * Combines RM PMU object data
+ */
+typedef struct NvRmPmuRec
+{
+    // RM PMU access mutex
+    NvOsMutexHandle hMutex;
+
+    // ODM PMU device handle
+    NvOdmPmuDeviceHandle hOdmPmu;
+
+    // PMU interrupt handle
+    NvOsInterruptHandle hInterrupt;
+
+    // PMU ISR semaphore
+    NvOsSemaphoreHandle hSemaphore;
+
+    // PMU interrupt thread
+    NvOsThreadHandle hThread; 
+
+    //  PMU interrupt mask state
+    volatile NvBool IntrMasked;
+
+    // PMU interrupt thread abort indicator
+    volatile NvBool AbortThread;
+
+    // IO power rails level detect mask
+    NvU32 IoPwrDetectMask;
+
+    // Unpowered IO rails mask
+    NvU32 NoIoPwrMask;
+} NvRmPmu;
+
+// RM PMU object
+static NvRmPmu s_Pmu;
+
+// PMU supported execution environment flag
+static NvBool s_PmuSupportedEnv = NV_FALSE;
+
+/*****************************************************************************/
+
+static void PmuIsr(void* args)
+{
+    NvRmPmu* pPmu = (NvRmPmu*)args;
+    NvOsSemaphoreSignal(pPmu->hSemaphore);
+}
+
+static void PmuThread(void* args)
+{
+    NvRmPmu* pPmu = (NvRmPmu*)args;
+
+    for (;;)
+    {
+        NvOsSemaphoreWait(pPmu->hSemaphore);
+        if (pPmu->AbortThread)
+        {
+            break;
+        }
+
+        NvOsMutexLock(pPmu->hMutex);
+        if (pPmu->IntrMasked)
+        {
+            NvOsMutexUnlock(pPmu->hMutex);
+            continue;
+        }
+        NvOdmPmuInterruptHandler(pPmu->hOdmPmu);
+        NvOsMutexUnlock(pPmu->hMutex);
+
+        if (pPmu->hInterrupt)
+            NvRmInterruptDone(pPmu->hInterrupt);
+    }
+}
+
+static void PmuThreadTerminate(NvRmPmu* pPmu)
+{
+    /*
+     * Request thread abort, signal semaphore to make sure the thread is
+     * awaken and wait for its self-termination. Do nothing if invalid PMU
+     * structure
+     */
+    if (pPmu)
+    {
+        if (pPmu->hSemaphore && pPmu->hThread)
+        {
+            pPmu->AbortThread = NV_TRUE;
+            NvOsSemaphoreSignal(pPmu->hSemaphore);
+            NvOsThreadJoin(pPmu->hThread);
+        }
+        pPmu->AbortThread = NV_FALSE;
+    }
+}
+
+/*****************************************************************************/
+
+NvError NvRmPrivPmuInit(NvRmDeviceHandle hRmDevice)
+{
+    NvError e;
+    ExecPlatform env;
+    NvOdmPmuProperty PmuProperty;
+
+    NV_ASSERT(hRmDevice);
+    env = NvRmPrivGetExecPlatform(hRmDevice);
+
+    NvOsMemset(&s_Pmu, 0, sizeof(NvRmPmu));
+    s_PmuSupportedEnv = NV_FALSE;
+
+    if (env == ExecPlatform_Soc)
+    {
+        // Set supported environment flag
+        s_PmuSupportedEnv = NV_TRUE;
+
+        // Create the PMU mutex, semaphore, interrupt handler thread,
+        // register PMU interrupt, and get ODM PMU handle
+        NV_CHECK_ERROR_CLEANUP(NvOsMutexCreate(&s_Pmu.hMutex));
+        NV_CHECK_ERROR_CLEANUP(NvOsSemaphoreCreate(&s_Pmu.hSemaphore, 0));
+
+        if (NvOdmQueryGetPmuProperty(&PmuProperty) && PmuProperty.IrqConnected)
+        {
+            if (hRmDevice->ChipId.Id >= 0x20)
+                NvRmPrivAp20SetPmuIrqPolarity(
+                    hRmDevice, PmuProperty.IrqPolarity);
+            else
+                NV_ASSERT(PmuProperty.IrqPolarity ==
+                          NvOdmInterruptPolarity_Low);
+            {
+                NvOsInterruptHandler hPmuIsr = PmuIsr;
+                NvU32 PmuExtIrq = NvRmGetIrqForLogicalInterrupt(
+                    hRmDevice, NVRM_MODULE_ID(NvRmPrivModuleID_PmuExt, 0), 0);
+                NV_CHECK_ERROR_CLEANUP(NvRmInterruptRegister(hRmDevice, 1,
+                    &PmuExtIrq, &hPmuIsr, &s_Pmu, &s_Pmu.hInterrupt, NV_FALSE));
+            }
+        }
+
+        if(!NvOdmPmuDeviceOpen(&s_Pmu.hOdmPmu))
+        {
+            e = NvError_NotInitialized;
+            goto fail;
+        }
+        NV_CHECK_ERROR_CLEANUP(NvOsThreadCreate(PmuThread, &s_Pmu, &s_Pmu.hThread));
+        NvRmPrivIoPowerControlInit(hRmDevice);
+        NvRmPrivCoreVoltageInit(hRmDevice);
+    }
+    return NvSuccess;
+
+fail:
+    NvRmPrivPmuDeinit(hRmDevice);
+    return e;
+}
+
+void NvRmPrivPmuInterruptEnable(NvRmDeviceHandle hRmDevice)
+{
+    if (s_Pmu.hInterrupt)
+        NvRmInterruptEnable(hRmDevice, s_Pmu.hInterrupt);
+}
+
+void NvRmPrivPmuInterruptMask(NvRmDeviceHandle hRmDevice, NvBool mask)
+{
+    if (s_Pmu.hInterrupt)
+    {
+
+        NvOsMutexLock(s_Pmu.hMutex);
+        s_Pmu.IntrMasked = mask;
+        NvOsMutexUnlock(s_Pmu.hMutex);
+
+        NvOsInterruptMask(s_Pmu.hInterrupt, mask);
+    }
+}
+
+void NvRmPrivPmuDeinit(NvRmDeviceHandle hRmDevice)
+{
+    if (s_PmuSupportedEnv == NV_FALSE)
+        return;
+
+    PmuThreadTerminate(&s_Pmu);
+    NvOdmPmuDeviceClose(s_Pmu.hOdmPmu);
+    NvRmInterruptUnregister(hRmDevice, s_Pmu.hInterrupt);
+    NvOsSemaphoreDestroy(s_Pmu.hSemaphore);
+    NvOsMutexDestroy(s_Pmu.hMutex);
+
+    NvOsMemset(&s_Pmu, 0, sizeof(NvRmPmu));
+    s_PmuSupportedEnv = NV_FALSE;
+}
+
+void NvRmPrivPmuLPxStateConfig(
+    NvRmDeviceHandle hRmDevice,
+    NvOdmSocPowerState state,
+    NvBool enter)
+{
+    NvOdmPmuProperty PmuProperty = {0};
+    NvBool HasPmuProperty = NvOdmQueryGetPmuProperty(&PmuProperty);
+    const NvOdmPeripheralConnectivity* pCoreRail =
+        NvOdmPeripheralGetGuid(NV_VDD_CORE_ODM_ID);
+
+    NV_ASSERT(hRmDevice);
+    NV_ASSERT(pCoreRail);
+    NV_ASSERT(pCoreRail->NumAddress);
+
+    // On platforms with combined cpu/core power request core power rail
+    // should be controlled by the combined request only during deep sleep
+    // - enable the On/Off control on entry, and disable on exit
+    if (state == NvOdmSocPowerState_DeepSleep)
+    {
+        if (HasPmuProperty && PmuProperty.CombinedPowerReq)
+        {
+            NvU32 level = enter ?
+                ODM_VOLTAGE_ENABLE_EXT_ONOFF : ODM_VOLTAGE_DISABLE_EXT_ONOFF;
+            NvRmPmuSetVoltage(hRmDevice, pCoreRail->AddressList[0].Address,
+                              level, NULL);
+        }
+    }
+    // Mask/Unmask PMU interrupt on entry/exit to/from suspend or deep sleep
+    if ((state == NvOdmSocPowerState_Suspend) ||
+        (state == NvOdmSocPowerState_DeepSleep))
+        NvRmPrivPmuInterruptMask(hRmDevice, enter);
+}
+
+/*****************************************************************************/
+
+void NvRmPmuGetCapabilities( 
+    NvRmDeviceHandle hDevice,
+    NvU32 vddId,
+    NvRmPmuVddRailCapabilities * pCapabilities )
+{
+    NvOdmPmuVddRailCapabilities RailCap;
+
+    if (!s_PmuSupportedEnv)
+        return;
+
+    NvOdmPmuGetCapabilities(vddId, &RailCap);
+    pCapabilities->MaxMilliVolts = RailCap.MaxMilliVolts;
+    pCapabilities->MinMilliVolts = RailCap.MinMilliVolts;
+    pCapabilities->requestMilliVolts = RailCap.requestMilliVolts;
+    pCapabilities->RmProtected = RailCap.OdmProtected;
+    pCapabilities->StepMilliVolts = RailCap.StepMilliVolts;
+}
+
+void NvRmPmuGetVoltage(
+    NvRmDeviceHandle hDevice,
+    NvU32 vddId,
+    NvU32 * pMilliVolts)
+{
+    NvU32 i;
+    if (!s_PmuSupportedEnv)
+        return;
+
+    NV_ASSERT(s_Pmu.hMutex);
+    NvOsMutexLock(s_Pmu.hMutex);
+    for (i = 0; i < VOLTAGE_CONTROL_RETRY_CNT; i++)
+    {
+        if (NvOdmPmuGetVoltage(s_Pmu.hOdmPmu, vddId, pMilliVolts))
+            break;
+    }
+    NV_ASSERT(i < VOLTAGE_CONTROL_RETRY_CNT);
+    NvOsMutexUnlock(s_Pmu.hMutex);
+}
+
+void NvRmPmuSetVoltage( 
+    NvRmDeviceHandle hDevice,
+    NvU32 vddId,
+    NvU32 MilliVolts,
+    NvU32 * pSettleMicroSeconds)
+{
+    NvU32 i;
+    NvU32 t = NVRM_PWR_DET_DELAY_US;
+    NV_ASSERT(hDevice);
+    
+    if (pSettleMicroSeconds)
+        *pSettleMicroSeconds = 0;
+
+    if (!s_PmuSupportedEnv)
+        return;
+
+    // This API is blocked if diagnostic is in progress for any module 
+    if (NvRmPrivIsDiagMode(NvRmModuleID_Invalid))
+        return;
+
+#if PMU_RAILS_NEVER_OFF
+    if (MilliVolts == ODM_VOLTAGE_OFF)
+        return;
+#endif
+
+    NV_ASSERT(s_Pmu.hMutex);
+    NvOsMutexLock(s_Pmu.hMutex);
+
+    // Set voltage and latch IO level sampling results
+    for (i = 0; i < VOLTAGE_CONTROL_RETRY_CNT; i++)
+    {
+        if (NvOdmPmuSetVoltage(s_Pmu.hOdmPmu, vddId, MilliVolts, pSettleMicroSeconds))
+            break;
+    }
+    NV_ASSERT(i < VOLTAGE_CONTROL_RETRY_CNT);
+
+    if (s_Pmu.IoPwrDetectMask || s_Pmu.NoIoPwrMask)
+    {
+        NV_ASSERT(MilliVolts != ODM_VOLTAGE_OFF);
+        if (pSettleMicroSeconds)
+        {
+            t += (*pSettleMicroSeconds);
+            *pSettleMicroSeconds = 0;           // Don't wait twice
+        }
+        NvOsWaitUS(t);
+
+        if (s_Pmu.IoPwrDetectMask)              // Latch just powered IO rails
+            NvRmPrivIoPowerDetectLatch(hDevice);
+        if (s_Pmu.NoIoPwrMask)                  // Enable just powered IO rails
+            NvRmPrivIoPowerControl(hDevice, s_Pmu.NoIoPwrMask, NV_TRUE);
+        s_Pmu.IoPwrDetectMask = s_Pmu.NoIoPwrMask = 0;
+    }
+    NvOsMutexUnlock(s_Pmu.hMutex);
+}
+
+void
+NvRmPmuSetSocRailPowerState(
+    NvRmDeviceHandle hDevice,
+    NvU32 vddId,
+    NvBool Enable)
+{
+    NV_ASSERT(hDevice);
+    NvRmPrivSetSocRailPowerState(
+        hDevice, vddId, Enable, &s_Pmu.IoPwrDetectMask, &s_Pmu.NoIoPwrMask);
+}
+
+/*****************************************************************************/
+
+void NvRmPmuSetChargingCurrentLimit(
+    NvRmDeviceHandle hRmDevice,
+    NvRmPmuChargingPath ChargingPath,
+    NvU32 ChargingCurrentLimitMa,
+    NvU32 ChargerType)
+{
+    NvU32 i;
+
+    if (!s_PmuSupportedEnv)
+        return;
+
+    NV_ASSERT(s_Pmu.hMutex);
+    NvOsMutexLock(s_Pmu.hMutex);
+    for (i = 0; i < VOLTAGE_CONTROL_RETRY_CNT; i++)
+    {
+        if (NvOdmPmuSetChargingCurrent(
+            s_Pmu.hOdmPmu, (NvOdmPmuChargingPath)ChargingPath, 
+            ChargingCurrentLimitMa, ChargerType))
+            break;
+    }
+    NV_ASSERT(i < VOLTAGE_CONTROL_RETRY_CNT);
+    NvOsMutexUnlock(s_Pmu.hMutex);
+}
+
+/*****************************************************************************/
+
+NvBool NvRmPmuGetAcLineStatus( 
+    NvRmDeviceHandle hRmDevice,
+    NvRmPmuAcLineStatus * pStatus )
+{
+    NvBool ReturnStatus = NV_FALSE;
+
+    if (!s_PmuSupportedEnv)
+        return NV_FALSE;
+
+    NV_ASSERT(s_Pmu.hMutex);
+    NvOsMutexLock(s_Pmu.hMutex);
+    ReturnStatus =
+        NvOdmPmuGetAcLineStatus(s_Pmu.hOdmPmu, (NvOdmPmuAcLineStatus*)pStatus);
+    NvOsMutexUnlock(s_Pmu.hMutex);
+    return ReturnStatus;
+}
+
+ NvBool NvRmPmuGetBatteryStatus( 
+    NvRmDeviceHandle hRmDevice,
+    NvRmPmuBatteryInstance batteryInst,
+    NvU8 * pStatus )
+{
+    NvBool ReturnStatus = NV_FALSE;
+
+    if (!s_PmuSupportedEnv)
+        return NV_FALSE;
+
+    NV_ASSERT(s_Pmu.hMutex);
+    NvOsMutexLock(s_Pmu.hMutex);
+    ReturnStatus = NvOdmPmuGetBatteryStatus(
+        s_Pmu.hOdmPmu, (NvOdmPmuBatteryInstance)batteryInst, pStatus);
+    NvOsMutexUnlock(s_Pmu.hMutex);
+    return ReturnStatus;
+}
+
+/*****************************************************************************/
+
+NvBool NvRmPmuGetBatteryData( 
+    NvRmDeviceHandle hRmDevice,
+    NvRmPmuBatteryInstance batteryInst,
+    NvRmPmuBatteryData * pData )
+{
+    NvOdmPmuBatteryData BatteryData;
+
+    if (!s_PmuSupportedEnv)
+        return NV_FALSE;
+
+    NV_ASSERT(s_Pmu.hMutex);
+    NvOsMutexLock(s_Pmu.hMutex);
+    if (NvOdmPmuGetBatteryData(
+        s_Pmu.hOdmPmu, (NvOdmPmuBatteryInstance)batteryInst, &BatteryData))
+    {
+        pData->batteryAverageCurrent = BatteryData.batteryAverageCurrent;
+        pData->batteryAverageInterval = BatteryData.batteryAverageInterval;
+        pData->batteryCurrent = BatteryData.batteryCurrent;
+        pData->batteryLifePercent = BatteryData.batteryLifePercent;
+        pData->batteryLifeTime = BatteryData.batteryLifeTime;
+        pData->batteryMahConsumed = BatteryData.batteryMahConsumed;
+        pData->batteryTemperature = BatteryData.batteryTemperature;
+        pData->batteryVoltage = BatteryData.batteryVoltage;
+        NvOsMutexUnlock(s_Pmu.hMutex);
+        return NV_TRUE;
+    }
+    NvOsMutexUnlock(s_Pmu.hMutex);
+    return NV_FALSE;
+}
+
+void NvRmPmuGetBatteryFullLifeTime( 
+    NvRmDeviceHandle hRmDevice,
+    NvRmPmuBatteryInstance batteryInst,
+    NvU32 * pLifeTime )
+{
+    if (!s_PmuSupportedEnv)
+        return;
+
+    NV_ASSERT(s_Pmu.hMutex);
+    NvOsMutexLock(s_Pmu.hMutex);
+    NvOdmPmuGetBatteryFullLifeTime(
+        s_Pmu.hOdmPmu,(NvOdmPmuBatteryInstance)batteryInst, pLifeTime);
+    NvOsMutexUnlock(s_Pmu.hMutex);
+}
+
+void NvRmPmuGetBatteryChemistry( 
+    NvRmDeviceHandle hRmDevice,
+    NvRmPmuBatteryInstance batteryInst,
+    NvRmPmuBatteryChemistry * pChemistry )
+{
+    if (!s_PmuSupportedEnv)
+        return;
+
+    NV_ASSERT(s_Pmu.hMutex);
+    NvOsMutexLock(s_Pmu.hMutex);
+    NvOdmPmuGetBatteryChemistry(s_Pmu.hOdmPmu,
+                                (NvOdmPmuBatteryInstance)batteryInst,
+                                (NvOdmPmuBatteryChemistry*)pChemistry);
+    NvOsMutexUnlock(s_Pmu.hMutex);
+}
+
+/*****************************************************************************/
+
+NvBool
+NvRmPmuReadRtc(
+    NvRmDeviceHandle hRmDevice,
+    NvU32* pCount)
+{
+    NvBool ReturnStatus = NV_FALSE;
+
+    if (!s_PmuSupportedEnv)
+        return NV_FALSE;
+
+    NV_ASSERT(s_Pmu.hMutex);
+    NvOsMutexLock(s_Pmu.hMutex);
+    ReturnStatus = NvOdmPmuReadRtc(s_Pmu.hOdmPmu, pCount);
+    NvOsMutexUnlock(s_Pmu.hMutex);
+    return ReturnStatus;
+}
+
+NvBool
+NvRmPmuWriteRtc(
+    NvRmDeviceHandle hRmDevice,
+    NvU32 Count)
+{
+    NvBool ReturnStatus = NV_FALSE;
+
+    if (!s_PmuSupportedEnv)
+        return NV_FALSE;
+
+    NV_ASSERT(s_Pmu.hMutex);
+    NvOsMutexLock(s_Pmu.hMutex);
+    ReturnStatus = NvOdmPmuWriteRtc(s_Pmu.hOdmPmu, Count);
+    NvOsMutexUnlock(s_Pmu.hMutex);
+    return ReturnStatus;
+}
+
+NvBool
+NvRmPmuIsRtcInitialized(
+    NvRmDeviceHandle hRmDevice)
+{
+    NvBool ReturnStatus = NV_FALSE;
+
+    if (!s_PmuSupportedEnv)
+        return NV_FALSE;
+
+    NV_ASSERT(s_Pmu.hMutex);
+    NvOsMutexLock(s_Pmu.hMutex);
+    ReturnStatus = NvOdmPmuIsRtcInitialized(s_Pmu.hOdmPmu);
+    NvOsMutexUnlock(s_Pmu.hMutex);
+    return ReturnStatus;
+}
+
+/*****************************************************************************/
+
+NvBool
+NvRmPrivDiagPmuSetVoltage( 
+    NvRmDeviceHandle hDevice,
+    NvU32 vddId,
+    NvU32 MilliVolts,
+    NvU32 * pSettleMicroSeconds)
+{
+    NvU32 i;
+
+    if (pSettleMicroSeconds)
+        *pSettleMicroSeconds = 0;
+
+    NV_ASSERT(s_PmuSupportedEnv);
+    NV_ASSERT(NvRmPrivIsDiagMode(NvRmModuleID_Invalid));
+
+    NV_ASSERT(s_Pmu.hMutex);
+    NvOsMutexLock(s_Pmu.hMutex);
+    for (i = 0; i < VOLTAGE_CONTROL_RETRY_CNT; i++)
+    {
+        if (NvOdmPmuSetVoltage(s_Pmu.hOdmPmu, vddId, MilliVolts, pSettleMicroSeconds))
+            break;
+    }
+    NvOsMutexUnlock(s_Pmu.hMutex);
+
+    return (i < VOLTAGE_CONTROL_RETRY_CNT);
+}
+
+/*****************************************************************************/
+
+void
+NvRmPrivPmuRailControl(
+    NvRmDeviceHandle hRmDevice,
+    NvU64 NvRailId,
+    NvBool TurnOn)
+{
+    NvU32 RailAddress, TimeUs;
+    const NvOdmPeripheralConnectivity* pPmuRail;
+    NvRmPmuVddRailCapabilities RailCapabilities = {0};
+
+    if (!s_PmuSupportedEnv)
+        return;
+
+    pPmuRail = NvOdmPeripheralGetGuid(NvRailId);
+
+    NV_ASSERT(hRmDevice);
+    NV_ASSERT(pPmuRail);
+    NV_ASSERT(pPmuRail->NumAddress);
+
+    RailAddress = pPmuRail->AddressList[0].Address;
+    if (TurnOn)
+    {
+        NvRmPmuGetCapabilities(hRmDevice, RailAddress, &RailCapabilities);
+        NvRmPmuSetVoltage(hRmDevice, RailAddress,
+                          RailCapabilities.requestMilliVolts, &TimeUs);
+    }
+    else
+    {
+        NvRmPmuSetVoltage(
+            hRmDevice, RailAddress, ODM_VOLTAGE_OFF, &TimeUs);
+    }
+    NvOsWaitUS(TimeUs);
+}
+
+NvU32
+NvRmPrivPmuRailGetVoltage(
+    NvRmDeviceHandle hRmDevice,
+    NvU64 NvRailId)
+{
+    NvU32 RailAddress;
+    const NvOdmPeripheralConnectivity* pPmuRail;
+    NvU32 MilliVolts = NVRM_NO_PMU_DEFAULT_VOLTAGE;
+
+    if (s_PmuSupportedEnv)
+    {
+        pPmuRail = NvOdmPeripheralGetGuid(NvRailId);
+
+        NV_ASSERT(hRmDevice);
+        NV_ASSERT(pPmuRail);
+        NV_ASSERT(pPmuRail->NumAddress);
+
+        RailAddress = pPmuRail->AddressList[0].Address;
+        NvRmPmuGetVoltage(hRmDevice, RailAddress, &MilliVolts);
+    }
+    return MilliVolts;
+}
+
+/*****************************************************************************/
diff --git a/arch/arm/mach-tegra/nvrm/core/common/nvrm_pmu_private.h b/arch/arm/mach-tegra/nvrm/core/common/nvrm_pmu_private.h
new file mode 100644
index 000000000000..6a16c5e4de02
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/core/common/nvrm_pmu_private.h
@@ -0,0 +1,161 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_NVRM_PMU_PRIVATE_H
+#define INCLUDED_NVRM_PMU_PRIVATE_H
+
+#include "nvodm_query.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif  /* __cplusplus */
+
+// CPU rail lowering voltage delay (applicable only to the platforms
+// with dedicated CPU rail)
+#define NVRM_CPU_TO_CORE_DOWN_US (2000)
+
+// Default voltage returned in environment with no PMU support
+#define NVRM_NO_PMU_DEFAULT_VOLTAGE (1)
+
+/**
+ * Initializes RM PMU interface handle
+ *
+ * @param hRmDevice The RM device handle
+ * 
+ * @return NvSuccess if initialization completed successfully
+ *  or one of common error codes on failure
+ */
+NvError
+NvRmPrivPmuInit(NvRmDeviceHandle hRmDevice);
+
+/**
+ * Enables PMU interrupt.
+ *
+ * @param hRmDevice The RM device handle
+ */
+void NvRmPrivPmuInterruptEnable(NvRmDeviceHandle hRmDevice);
+
+/**
+ * Masks/Unmasks OMU interrupt
+ * 
+ * @param hRmDevice The RM device handle
+ * @param mask Set NV_TRUE to maks, and NV_FALSE to unmask PMU interrupt
+ */
+void NvRmPrivPmuInterruptMask(NvRmDeviceHandle hRmDevice, NvBool mask);
+
+/**
+ * Deinitializes RM PMU interface
+ *
+ * @param hRmDevice The RM device handle
+ */
+void
+NvRmPrivPmuDeinit(NvRmDeviceHandle hRmDevice);
+
+/**
+ * Configures PMU on entry/exit to/from low power state.
+ *
+ * @param hRmDevice The RM device handle
+ * @param state - Low Power state the SoC is entering to, or exiting from
+ * @param enter - Set NV_TRUE on entry, and NV_FALSE on exit
+ */
+void NvRmPrivPmuLPxStateConfig(
+    NvRmDeviceHandle hRmDevice,
+    NvOdmSocPowerState state,
+    NvBool enter);
+
+/**
+ * Sets new voltage level for the specified PMU voltage rail.
+ * Private interface for diagnostic mode only.
+ *
+ * @param hDevice The Rm device handle.
+ * @param vddId The ODM-defined PMU rail ID.
+ * @param MilliVolts The new voltage level to be set in millivolts (mV).
+ *  Set to ODM_VOLTAGE_OFF to turn off the target voltage.
+ * @param pSettleMicroSeconds A pointer to the settling time in microseconds (uS),
+ *  which is the time for supply voltage to settle after this function 
+ *  returns; this may or may not include PMU control interface transaction time, 
+ *  depending on the ODM implementation. If null this parameter is ignored.
+ * 
+ * @return NV_TRUE if successful, or NV_FALSE otherwise. 
+ */
+NvBool
+NvRmPrivDiagPmuSetVoltage( 
+    NvRmDeviceHandle hDevice,
+    NvU32 vddId,
+    NvU32 MilliVolts,
+    NvU32 * pSettleMicroSeconds);
+
+/**
+ * Turns PMU rail On/Off
+ *
+ * @param hRmDevice The RM device handle
+ * @param NvRailId The reserved NV rail GUID
+ * @param TurnOn Turn rail ON if True, or turn  rail Off if False
+ */
+void
+NvRmPrivPmuRailControl(
+    NvRmDeviceHandle hRmDevice,
+    NvU64 NvRailId,
+    NvBool TurnOn);
+
+/**
+ * Gets PMU rail voltage
+ *
+ * @param hRmDevice The RM device handle
+ * @param NvRailId The reserved NV rail GUID
+ * 
+ * @return PMU rail voltage in mv
+ */
+NvU32
+NvRmPrivPmuRailGetVoltage(
+    NvRmDeviceHandle hRmDevice,
+    NvU64 NvRailId);
+
+//  Forward declarations for all chip-specific helper functions
+
+/**
+ * Sets polarity of dedicated SoC PMU interrupt input
+ *
+ * @param hRmDevice The RM device handle
+ * @param Polarity PMU interrupt polarity to be set
+ */
+void
+NvRmPrivAp20SetPmuIrqPolarity(
+    NvRmDeviceHandle hRmDevice,
+    NvOdmInterruptPolarity Polarity);
+
+#ifdef __cplusplus
+}
+#endif  /* __cplusplus */
+
+#endif // INCLUDED_NVRM_PMU_PRIVATE_H
diff --git a/arch/arm/mach-tegra/nvrm/core/common/nvrm_power.c b/arch/arm/mach-tegra/nvrm/core/common/nvrm_power.c
new file mode 100644
index 000000000000..aeba057740fe
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/core/common/nvrm_power.c
@@ -0,0 +1,1541 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/**
+ * @file
+ * @brief <b>nVIDIA Driver Development Kit:
+ *           Power Resource manager </b>
+ *
+ * @b Description: Implements the interface of the NvRM Power.
+ *
+ */
+
+#include "nvrm_power_private.h"
+#include "nvrm_pmu_private.h"
+#include "ap15/ap15rm_private.h"
+#include "ap15/project_relocation_table.h"
+#include "nvassert.h"
+#include "nvrm_hwintf.h"
+#include "ap15/arapbpm.h"
+#include "nvrm_clocks.h"
+#include "nvodm_query.h"
+
+// TODO: Always Disable before check-in
+// Module debug: 0=disable, 1=enable
+#define NVRM_POWER_ENABLE_PRINTF (0)
+
+// TODO: Always Disable before check-in
+// Report every change in RM clients power state: 0=disable, 1=enable
+#define NVRM_POWER_VERBOSE_PRINTF (0)
+
+#if NVRM_POWER_ENABLE_PRINTF || NVRM_POWER_VERBOSE_PRINTF
+#define NVRM_POWER_PRINTF(x)   NvOsDebugPrintf x
+#else
+#define NVRM_POWER_PRINTF(x)
+#endif
+
+// Active modules report on suspend entry : 0=disable, 1=enable
+#define NVRM_POWER_DEBUG_SUSPEND_ENTRY (1)
+
+/*****************************************************************************/
+
+// Specifies initial registry size as well as delta for dynamic size change
+#define NVRM_POWER_REGISTRY_DELTA (NvRmPrivModuleID_Num)
+
+/*
+ * Convert registry index to client ID and vice versa: just use
+ * provided mask as high bits combined with index in low bits
+ * (index is expected to not exceed 16 bits ever)
+ */
+#define NVRM_POWER_INDEX2ID(index, mask) (((mask) << 16) | (index))
+#define NVRM_POWER_ID2INDEX(id) ((id) & 0xFFFF)
+
+
+/*
+ * Holds power client voltage request information for a
+ * particular module
+ */
+typedef struct ModuleVoltageReqRec
+{
+    // Target module (combined ID and instance)
+    NvRmModuleID ModuleId;
+
+    // Power group number module belongs to
+    NvU32 PowerGroup;
+
+    // Module power cycle indicator
+    NvBool PowerCycled;
+
+    // Requested voltage range
+    NvRmMilliVolts MinVolts;
+    NvRmMilliVolts MaxVolts;
+
+    // Pointer to the next module info node
+    struct ModuleVoltageReqRec* pNext;
+} ModuleVoltageReq;
+
+/*
+ * Holds power client clock request information for a
+ * particular module
+ */
+typedef struct ModuleClockReqRec
+{
+    // TODO: Define clock request information members
+
+    // Pointer to the next module info node
+    struct ModuleClockReqRec* pNext;
+} ModuleClockReq;
+
+/*
+ * Holds power client busy hint information for a
+ * particular clock domain
+ */
+typedef struct BusyHintReqRec
+{
+    // Requested busy pulse mode
+    NvBool BusyPulseMode;
+
+    // Requested frequency boost in KHz
+    NvRmFreqKHz BoostKHz;
+
+    // Requested boost interval in ms
+    NvU32 IntervalMs;
+
+    // Boost start time in ms
+    NvU32 StartTimeMs;
+
+    // Id of the requester
+    NvU32 ClientId;
+
+    // Pointer to the next busy hint node
+    struct BusyHintReqRec* pNext;
+} BusyHintReq;
+
+/*
+ * Combines voltage and clock requets, starvation and busy hints,
+ * as well as recorded power events for a particular client
+ */
+typedef struct NvRmPowerClientRec
+{
+    // Client registration ID
+    NvU32 id;
+
+    // Client semaphore for power management event signaling
+    NvOsSemaphoreHandle hEventSemaphore;
+
+    // Last detected power management event
+    NvRmPowerEvent Event;
+
+    // Pointer to the array of starvation hints
+    NvBool* pStarvationHints;
+
+    // Head pointer to client volatge request list
+    ModuleVoltageReq* pVoltageReqHead;
+
+    // Head pointer to client clock request list
+    ModuleClockReq* pClockReqHead;
+
+    // Client 4-character tag
+    NvU32 tag;
+} NvRmPowerClient;
+
+/*
+ * Combines information on power clients registred
+ * with RM
+ */
+typedef struct NvRmPowerRegistryRec
+{
+    // Array of pointers to power client records
+    NvRmPowerClient** pPowerClients;
+
+    // Used index range (max used entry index + 1)
+    NvU32 UsedIndexRange;
+
+    // Total number of available entries (array size)
+    NvU32 AvailableEntries;
+} NvRmPowerRegistry;
+
+// RM power clients registry
+static NvRmPowerRegistry s_PowerRegistry;
+
+// Mutex for thread-safe access to RM power clients records
+static NvOsMutexHandle s_hPowerClientMutex = NULL;
+
+// "Power On" request reference count for each SoC Power Group. Appended
+// at the end is a duplicate entry for NPG group that represents power
+// requirements for autonomous h/w operations with no s/w activity
+static NvU32 s_PowerOnRefCounts[NV_POWERGROUP_MAX + 1];
+#define NVRM_POWERGROUP_NPG_AUTO (NV_POWERGROUP_MAX)
+
+// Active starvation hints reference count for each DFS clock domain
+static NvU32 s_StarveOnRefCounts[NvRmDfsClockId_Num];
+
+// Heads of busy hint lists for DFS clock domain
+static BusyHintReq s_BusyReqHeads[NvRmDfsClockId_Num];
+
+
+/*****************************************************************************/
+
+/*
+ * Release memory and system resources allocated for the specified power client
+ */
+static void FreePowerClient(NvRmPowerClient* pPowerClient);
+
+/*
+ * Cancel all requests issued by the specified power client
+ */
+static void CancelPowerRequests(
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvRmPowerClient* pPowerClient);
+
+/*
+ * Notifies RM Clients about power management event
+ */
+static void
+PowerEventNotify(NvRmDeviceHandle hRmDeviceHandle, NvRmPowerEvent Event);
+
+/*
+ * Records power cycle for all RM clients in the specified group
+ */
+static void
+RecordPowerCycle(NvRmDeviceHandle hRmDeviceHandle, NvU32 PowerGroup);
+
+/*
+ * Reports combined RM clients power state to OS adaptation layer
+ * (chip-aware implementation)
+ */
+static void
+ReportRmPowerState(NvRmDeviceHandle hRmDeviceHandle);
+
+/*
+ * Cancels busy hints reported by the specified client for
+ * specified domain
+ */
+static void
+CancelBusyHints(NvRmDfsClockId ClockId, NvU32 ClientId);
+
+/*
+ * Records starvation hints reported against DFS domains by
+ * the specified client
+ */
+static NvError
+RecordStarvationHints(
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvRmPowerClient* pPowerClient,
+    const NvRmDfsStarvationHint* pMultiHint,
+    NvU32 NumHints);
+
+/*
+ * Records busy hints reported against DFS domains by
+ * the specified client
+ */
+static NvError
+RecordBusyHints(
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvU32 ClientId,
+    const NvRmDfsBusyHint* pMultiHint,
+    NvU32 NumHints,
+    NvBool* pSignalDfs);
+
+/* Send a simple message to the AVP indicating that it needs
+ * to save state in preparation for LP0 (explicit case)
+ */
+NvError
+NvRmPrivSendAVPIdleMessage( NvRmDeviceHandle hRmDeviceHandle );
+
+/*****************************************************************************/
+static void FreePowerClient(NvRmPowerClient* pPowerClient)
+{
+    ModuleVoltageReq* pVoltageReq = NULL;
+    ModuleClockReq* pClockReq = NULL;
+
+    // Just return if null-pointer
+    if (pPowerClient == NULL)
+        return;
+
+    // Free memory occupied by voltage requests
+    while (pPowerClient->pVoltageReqHead != NULL)
+    {
+        pVoltageReq = pPowerClient->pVoltageReqHead;
+        pPowerClient->pVoltageReqHead = pVoltageReq->pNext;
+        NvOsFree(pVoltageReq);
+    }
+
+    // Free memory occupied by clock requests
+    while (pPowerClient->pClockReqHead != NULL)
+    {
+        pClockReq = pPowerClient->pClockReqHead;
+        pPowerClient->pClockReqHead = pClockReq->pNext;
+        NvOsFree(pClockReq);
+    }
+
+    // Free memory occupied by starvation hints array
+    NvOsFree(pPowerClient->pStarvationHints);
+
+    // Free power management event semaphore handle
+    NvOsSemaphoreDestroy(pPowerClient->hEventSemaphore);
+
+    // Free memory occupied by the client record
+    NvOsFree(pPowerClient);
+}
+
+static void CancelPowerRequests(
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvRmPowerClient* pPowerClient)
+{
+    NvU32 i;
+    ModuleVoltageReq* pVoltageReq = NULL;
+
+    // Cancel power On requests and update power planes as well as
+    // combined RM clients power state accordingly
+    pVoltageReq = pPowerClient->pVoltageReqHead;
+    while (pVoltageReq != NULL)
+    {
+        if (pVoltageReq->MaxVolts != NvRmVoltsOff)
+        {
+            NvU32 PowerGroup = pVoltageReq->PowerGroup;
+            pVoltageReq->MaxVolts = NvRmVoltsOff;
+
+            NV_ASSERT(s_PowerOnRefCounts[PowerGroup] != 0);
+            s_PowerOnRefCounts[PowerGroup]--;
+            if (s_PowerOnRefCounts[PowerGroup] == 0)
+            {
+                NvRmPrivPowerGroupControl(hRmDeviceHandle, PowerGroup,
+                    NV_FALSE);
+                ReportRmPowerState(hRmDeviceHandle);
+            }
+        }
+        pVoltageReq = pVoltageReq->pNext;
+    }
+    // Cancel starvation hints
+    if (pPowerClient->pStarvationHints != NULL)
+    {
+        for (i = 0; i < NvRmDfsClockId_Num; i++)
+        {
+            if (pPowerClient->pStarvationHints[i])
+            {
+                pPowerClient->pStarvationHints[i] = NV_FALSE;
+                if ((i == NvRmDfsClockId_Cpu) ||
+                    (i == NvRmDfsClockId_Avp) ||
+                    (i == NvRmDfsClockId_Vpipe))
+                {
+                    NV_ASSERT(s_StarveOnRefCounts[NvRmDfsClockId_Emc] != 0);
+                    s_StarveOnRefCounts[NvRmDfsClockId_Emc]--;
+                }
+                NV_ASSERT(s_StarveOnRefCounts[i] != 0);
+                s_StarveOnRefCounts[i]--;
+            }
+        }
+    }
+
+    // Cancle busy hints
+    for (i = 0; i < NvRmDfsClockId_Num; i++)
+    {
+        CancelBusyHints(i, pPowerClient->id);
+    }
+
+    // TODO: Cancel clock requests issued by the client
+}
+
+/*****************************************************************************/
+NvError NvRmPrivPowerInit(NvRmDeviceHandle hRmDeviceHandle)
+{
+    NvError e;
+
+    NV_ASSERT(hRmDeviceHandle);
+
+    // TODO: expand after clock API is completed
+
+    // Initialize registry
+    s_PowerRegistry.pPowerClients = NULL;
+    s_PowerRegistry.AvailableEntries = 0;
+    s_PowerRegistry.UsedIndexRange = 0;
+
+    // Clear busy head pointers as well as starvation and power plane
+    // reference counts. Aalthough power plane references are cleared
+    // here, the combined power state is not updated - it will kept as
+    // set by the boot code, until the 1st client requests power.
+    NvOsMemset(s_BusyReqHeads, 0, sizeof(s_BusyReqHeads));
+    NvOsMemset(s_StarveOnRefCounts, 0, sizeof(s_StarveOnRefCounts));
+    NvOsMemset(s_PowerOnRefCounts, 0, sizeof(s_PowerOnRefCounts));
+
+    // Create the RM registry mutex and initialize RM/OAL interface
+    s_hPowerClientMutex = NULL;
+    NV_CHECK_ERROR_CLEANUP(NvOsMutexCreate(&s_hPowerClientMutex));
+    NV_CHECK_ERROR_CLEANUP(NvRmPrivOalIntfInit(hRmDeviceHandle));
+
+    // Initialize power group control, and power gate SoC partitions
+    NvRmPrivPowerGroupControlInit(hRmDeviceHandle);
+    return NvSuccess;
+
+fail:
+    NvRmPrivOalIntfDeinit(hRmDeviceHandle);
+    NvOsMutexDestroy(s_hPowerClientMutex);
+    s_hPowerClientMutex = NULL;
+    return e;
+}
+
+
+void NvRmPrivPowerDeinit(NvRmDeviceHandle hRmDeviceHandle)
+{
+    NvU32 i;
+    NvRmPowerRegistry* pRegistry = &s_PowerRegistry;
+
+    NV_ASSERT(hRmDeviceHandle);
+
+    // TODO: expand after clock API is completed
+
+    // Free busy hint lists for DFS clock domains
+    for (i = 0; i < NvRmDfsClockId_Num; i++)
+    {
+        while (s_BusyReqHeads[i].pNext != NULL)
+        {
+            BusyHintReq* pBusyHintReq = s_BusyReqHeads[i].pNext;
+            s_BusyReqHeads[i].pNext = pBusyHintReq->pNext;
+            NvOsFree(pBusyHintReq);
+        }
+    }
+    // Free RM power registry memory
+    for (i = 0; i < pRegistry->UsedIndexRange; i++)
+    {
+        FreePowerClient(pRegistry->pPowerClients[i]);
+    }
+    NvOsFree(pRegistry->pPowerClients);
+    pRegistry->pPowerClients = NULL;
+    pRegistry->AvailableEntries = 0;
+    pRegistry->UsedIndexRange = 0;
+
+    // Destroy RM registry mutex and free RM/OAL interface resources
+    NvRmPrivOalIntfDeinit(hRmDeviceHandle);
+    NvOsMutexDestroy(s_hPowerClientMutex);
+    s_hPowerClientMutex = NULL;
+}
+
+/*****************************************************************************/
+
+NvError
+NvRmPowerRegister(
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvOsSemaphoreHandle hEventSemaphore,
+    NvU32* pClientId)
+{
+    NvU32 FreeIndex;
+    NvError error;
+    NvOsSemaphoreHandle hSema = NULL;
+    NvRmPowerClient* pNewClient = NULL;
+    NvRmPowerRegistry* pRegistry = &s_PowerRegistry;
+
+    NV_ASSERT(hRmDeviceHandle);
+    NV_ASSERT(pClientId);
+
+    // If non-zero semaphore handle is passed, duplicate it to be avialable
+    // after the call. Abort registration if non-zero handle is invalid
+    if (hEventSemaphore != NULL)
+    {
+        error = NvOsSemaphoreClone(hEventSemaphore, &hSema);
+        if (error != NvSuccess)
+        {
+            NV_ASSERT(!" Power Register Semaphore Clone error. ");
+        }
+    }
+
+    NvOsMutexLock(s_hPowerClientMutex);
+
+    // Find free registry entry for the new client
+    for (FreeIndex = 0; FreeIndex < pRegistry->UsedIndexRange; FreeIndex++)
+    {
+        if (pRegistry->pPowerClients[FreeIndex] == NULL)
+            break;
+    }
+    if (FreeIndex == pRegistry->AvailableEntries)
+    {
+        // If all avilable entries are used, re-size registry array
+        NvU32 entries = pRegistry->AvailableEntries +
+            NVRM_POWER_REGISTRY_DELTA;
+        size_t s = sizeof(*pRegistry->pPowerClients) * (size_t)entries;
+        NvRmPowerClient** p = NvOsRealloc(pRegistry->pPowerClients, s);
+        if (p == NULL)
+        {
+            NvU32 old_size;
+
+            /* fall back to NvOsAlloc */
+            p = NvOsAlloc( s );
+            if( p == NULL )
+            {
+                goto failed;
+            }
+
+            /* copy the old data, free, etc, */
+            old_size = sizeof(*pRegistry->pPowerClients) *
+                pRegistry->AvailableEntries;
+
+            NvOsMemcpy( p, pRegistry->pPowerClients, old_size );
+            NvOsFree( pRegistry->pPowerClients );
+        }
+        pRegistry->pPowerClients = p;
+        pRegistry->AvailableEntries = entries;
+    }
+    if (FreeIndex == pRegistry->UsedIndexRange)
+    {
+        // If reached used index range boundary, advance it
+        pRegistry->UsedIndexRange++;
+    }
+
+    // Allocate and store new client record pointer in registry (null-pointer
+    // marks registry entry as free, so it's OK to store it before error check)
+    pNewClient = NvOsAlloc(sizeof(*pNewClient));
+    pRegistry->pPowerClients[FreeIndex] = pNewClient;
+    if (pNewClient == NULL)
+    {
+        goto failed;
+    }
+
+    // Fill in new client entry
+    pNewClient->hEventSemaphore = hSema;
+    pNewClient->Event = NvRmPowerEvent_NoEvent;
+    pNewClient->pVoltageReqHead = NULL;
+    pNewClient->pClockReqHead = NULL;
+    pNewClient->pStarvationHints = NULL;
+    pNewClient->tag = *pClientId;
+
+    /*
+     * Combine index with client pointer into registration ID returned to the
+     * client. This will make it a little bit more difficult for not-registered
+     * clients to guess/re-use IDs
+     */
+    pNewClient->id = NVRM_POWER_INDEX2ID(FreeIndex, (NvU32)pClientId);
+    *pClientId = pNewClient->id;
+
+    NvOsMutexUnlock(s_hPowerClientMutex);
+    return NvSuccess;
+
+failed:
+    NvOsFree(pNewClient);
+    NvOsSemaphoreDestroy(hSema);
+    NvOsMutexUnlock(s_hPowerClientMutex);
+    return NvError_InsufficientMemory;
+}
+
+/*****************************************************************************/
+
+void NvRmPowerUnRegister(
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvU32 ClientId)
+{
+    NvRmPowerClient* pPowerClient = NULL;
+    NvRmPowerRegistry* pRegistry = &s_PowerRegistry;
+    NvU32 ClientIndex = NVRM_POWER_ID2INDEX(ClientId);
+
+    NV_ASSERT(hRmDeviceHandle);
+
+    NvOsMutexLock(s_hPowerClientMutex);
+
+    // Check if this ID was registered
+    if (ClientIndex < pRegistry->UsedIndexRange)
+    {
+        pPowerClient = pRegistry->pPowerClients[ClientIndex];
+    }
+    if ((pPowerClient == NULL) || (pPowerClient->id != ClientId))
+    {
+        NvOsMutexUnlock(s_hPowerClientMutex);
+        return;
+    }
+
+    // Cancel power requets issued by the power client to be unregistered
+    CancelPowerRequests(hRmDeviceHandle, pPowerClient);
+
+    // Free power client memory and mark the respectve registry entry as free
+    FreePowerClient(pPowerClient);
+    pRegistry->pPowerClients[ClientIndex] = NULL;
+
+    // Decrement used index range as much as possible
+    while ((pRegistry->UsedIndexRange > 0) &&
+           (pRegistry->pPowerClients[pRegistry->UsedIndexRange - 1] == NULL))
+    {
+        pRegistry->UsedIndexRange--;
+    }
+
+    // Shrink registry if too much free space (keep one delta margin)
+    if ((pRegistry->UsedIndexRange + 2 * NVRM_POWER_REGISTRY_DELTA) <=
+         pRegistry->AvailableEntries)
+    {
+        NvU32 entries = pRegistry->UsedIndexRange + NVRM_POWER_REGISTRY_DELTA;
+        size_t s = sizeof(*pRegistry->pPowerClients) * (size_t)entries;
+        NvRmPowerClient** p = NvOsRealloc(pRegistry->pPowerClients, s);
+        if (p != NULL)
+        {
+            pRegistry->pPowerClients = p;
+            pRegistry->AvailableEntries = entries;
+        }
+
+        // FIXME: handle NvOsRealloc failure -- try NvOsAlloc instead
+    }
+    NvOsMutexUnlock(s_hPowerClientMutex);
+}
+
+/*****************************************************************************/
+
+NvError NvRmPowerGetEvent(
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvU32 ClientId,
+    NvRmPowerEvent* pEvent)
+{
+    NvRmPowerClient* pPowerClient = NULL;
+    NvRmPowerRegistry* pRegistry = &s_PowerRegistry;
+    NvU32 ClientIndex = NVRM_POWER_ID2INDEX(ClientId);
+
+    NV_ASSERT(hRmDeviceHandle);
+    NV_ASSERT(pEvent);
+
+    NvOsMutexLock(s_hPowerClientMutex);
+
+    // Check if this ID was registered; return error otherwise
+    if (ClientIndex < pRegistry->UsedIndexRange)
+    {
+        pPowerClient = pRegistry->pPowerClients[ClientIndex];
+    }
+    if ((pPowerClient == NULL) || (pPowerClient->id != ClientId))
+    {
+        NvOsMutexUnlock(s_hPowerClientMutex);
+        return NvError_BadValue;
+    }
+
+    // Return last recorded power event and set no outstanding events
+    *pEvent = pPowerClient->Event;
+    pPowerClient->Event = NvRmPowerEvent_NoEvent;
+
+    NvOsMutexUnlock(s_hPowerClientMutex);
+    return NvSuccess;
+}
+
+void NvRmPowerEventNotify(
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvRmPowerEvent Event)
+{
+    NV_ASSERT(hRmDeviceHandle);
+
+    // Just in case
+    if (Event == NvRmPowerEvent_NoEvent)
+         return;
+
+    NvOsMutexLock(s_hPowerClientMutex);
+    PowerEventNotify(hRmDeviceHandle, Event);
+    NvOsMutexUnlock(s_hPowerClientMutex);
+}
+
+static void
+PowerEventNotify(
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvRmPowerEvent Event)
+{
+    NvU32 i;
+    NvRmPowerClient* pPowerClient = NULL;
+    NvRmPowerRegistry* pRegistry = &s_PowerRegistry;
+
+    NVRM_POWER_PRINTF(("%s is reported to RM clients\n",
+        (Event == NvRmPowerEvent_WakeLP0)? "Wake from LP0" : "Wake from LP1"));
+
+    // Restore clocks after LP0
+    if (Event == NvRmPowerEvent_WakeLP0)
+        NvRmPrivClocksResume(hRmDeviceHandle);
+
+    // Store event for all registered clients, and signal only those, that
+    // have provided valid semaphore handle; on wake from low power states
+    // set power cycled indicators
+    for (i = 0; i < pRegistry->UsedIndexRange; i++)
+    {
+        pPowerClient = pRegistry->pPowerClients[i];
+        if (pPowerClient != NULL)
+        {
+            ModuleVoltageReq* pVoltageReq = pPowerClient->pVoltageReqHead;
+            while (pVoltageReq != NULL)
+            {
+                if (Event == NvRmPowerEvent_WakeLP0)
+                {
+                    //LP0: all power groups, except AO group, are powered down
+                    // when core power is down
+                    if (pVoltageReq->PowerGroup != NV_POWERGROUP_AO)
+                        pVoltageReq->PowerCycled = NV_TRUE;
+                }
+                else if (Event == NvRmPowerEvent_WakeLP1)
+                {
+                    // LP1: core power is preserved; but all  power groups
+                    // except AO and NPG group are power gated
+                    if ((pVoltageReq->PowerGroup != NV_POWERGROUP_AO) &&
+                        (pVoltageReq->PowerGroup != NV_POWERGROUP_NPG))
+                        pVoltageReq->PowerCycled = NV_TRUE;
+                }
+                pVoltageReq = pVoltageReq->pNext;
+            }
+            pPowerClient->Event = Event;
+            if (pPowerClient->hEventSemaphore != NULL)
+            {
+                NvOsSemaphoreSignal(pPowerClient->hEventSemaphore);
+            }
+        }
+    }
+}
+
+static void
+RecordPowerCycle(
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvU32 PowerGroup)
+{
+    NvU32 i;
+    NvRmPowerClient* pPowerClient = NULL;
+    NvRmPowerRegistry* pRegistry = &s_PowerRegistry;
+
+    NVRM_POWER_PRINTF(("Power Cycled partition: %d\n", PowerGroup));
+
+    // Traverse registered clients, and mark all modules in the specified
+    // power group as power cycled
+    for (i = 0; i < pRegistry->UsedIndexRange; i++)
+    {
+        pPowerClient = pRegistry->pPowerClients[i];
+        if (pPowerClient != NULL)
+        {
+            ModuleVoltageReq* pVoltageReq = pPowerClient->pVoltageReqHead;
+            while (pVoltageReq != NULL)
+            {
+                if (pVoltageReq->PowerGroup == PowerGroup)
+                {
+                    pVoltageReq->PowerCycled = NV_TRUE;
+                }
+                pVoltageReq = pVoltageReq->pNext;
+            }
+        }
+    }
+}
+
+/*****************************************************************************/
+
+static void
+ReportRmPowerState(NvRmDeviceHandle hRmDeviceHandle)
+{
+    NvU32 i;
+    NvRmPowerState OldRmState = NvRmPrivPowerGetState(hRmDeviceHandle);
+    NvRmPowerState NewRmState = NvRmPowerState_Idle;
+
+    // RM clients are in h/w autonomous (bypass) state if there are Power On
+    // references for NPG_AUTO group only; RM clients are in active state if
+    // there are Power On references for any other group
+    if (s_PowerOnRefCounts[NVRM_POWERGROUP_NPG_AUTO] != 0)
+        NewRmState = NvRmPowerState_AutoHw;
+
+    for (i = 0; i < NV_POWERGROUP_MAX; i++)
+    {
+        if (s_PowerOnRefCounts[i] != 0)
+        {
+            NewRmState = NvRmPowerState_Active;
+            break;
+        }
+    }
+    if (NewRmState == OldRmState)
+        return;
+
+#if NVRM_POWER_VERBOSE_PRINTF
+    NVRM_POWER_PRINTF(("RM Clients Power State: %s\n",
+        ((NewRmState == NvRmPowerState_Active) ? "Active" :
+         ((NewRmState == NvRmPowerState_AutoHw) ? "AutoHw" : "Idle"))));
+#endif
+    /*
+     * Set new combined RM clients power state in the storage shared with the
+     * OS adaptation layer. Check the previous state; if it was any of the low
+     * power states (i.e., this is the 1st RM power state report after suspend)
+     * notify all clients about wake up event.
+     */
+    NvRmPrivPowerSetState(hRmDeviceHandle, NewRmState);
+    switch (OldRmState)
+    {
+        case NvRmPowerState_LP0:
+            NvOsDebugPrintf("*** Wakeup from LP0 ***\n");
+            PowerEventNotify(hRmDeviceHandle, NvRmPowerEvent_WakeLP0);
+            break;
+        case NvRmPowerState_LP1:
+            NvOsDebugPrintf("*** Wakeup from LP1 ***\n");
+            PowerEventNotify(hRmDeviceHandle, NvRmPowerEvent_WakeLP1);
+            break;
+        case NvRmPowerState_SkippedLP0:
+            NvOsDebugPrintf("*** Wakeup after Skipped LP0 ***\n");
+            // resume procedure after Skipped LP0 is the same as after LP1
+            PowerEventNotify(hRmDeviceHandle, NvRmPowerEvent_WakeLP1);
+            break;
+        default:
+            break;
+    }
+}
+
+NvError
+NvRmPowerGetState(
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvRmPowerState* pState)
+{
+    NV_ASSERT(hRmDeviceHandle);
+    NV_ASSERT(pState);
+
+    NvOsMutexLock(s_hPowerClientMutex);
+    *pState = NvRmPrivPowerGetState(hRmDeviceHandle);
+    NvOsMutexUnlock(s_hPowerClientMutex);
+    return NvSuccess;
+}
+
+NvError
+NvRmPowerVoltageControl(
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvRmModuleID ModuleId,
+    NvU32 ClientId,
+    NvRmMilliVolts MinVolts,
+    NvRmMilliVolts MaxVolts,
+    const NvRmMilliVolts* PrefVoltageList,
+    NvU32 PrefVoltageListCount,
+    NvRmMilliVolts* pCurrentVolts)
+{
+    NvError error;
+    NvU32 PowerGroup = 0;
+    NvBool PowerChanged = NV_FALSE;
+    NvRmModuleInstance *pInstance = NULL;
+    ModuleVoltageReq* pVoltageReq = NULL;
+    NvRmPowerClient* pPowerClient = NULL;
+    NvRmPowerRegistry* pRegistry = &s_PowerRegistry;
+    NvU32 ClientIndex = NVRM_POWER_ID2INDEX(ClientId);
+
+    /* validate the Rm Handle */
+    NV_ASSERT(hRmDeviceHandle);
+
+    // Validate module ID and get associated Power Group
+    if (ModuleId == NvRmPrivModuleID_System)
+    {
+        PowerGroup = NVRM_POWERGROUP_NPG_AUTO;
+    }
+    else
+    {
+        error = NvRmPrivGetModuleInstance(hRmDeviceHandle, ModuleId, &pInstance);
+        if (error != NvSuccess)
+        {
+            NV_ASSERT(!" Voltage control: Invalid module ID. ");
+            return NvError_ModuleNotPresent;
+        }
+        PowerGroup = pInstance->DevPowerGroup;
+        NV_ASSERT(PowerGroup < NV_POWERGROUP_MAX);
+    }
+
+    NvOsMutexLock(s_hPowerClientMutex);
+
+    // Check if this ID was registered; return error otherwise
+    if (ClientIndex < pRegistry->UsedIndexRange)
+    {
+        pPowerClient = pRegistry->pPowerClients[ClientIndex];
+    }
+    if ((pPowerClient == NULL) || (pPowerClient->id != ClientId))
+    {
+        NvOsMutexUnlock(s_hPowerClientMutex);
+        return NvError_BadValue;
+    }
+
+    // Search for the previously recorded voltage request for this module
+    pVoltageReq = pPowerClient->pVoltageReqHead;
+    while ((pVoltageReq != NULL) && (pVoltageReq->ModuleId != ModuleId))
+    {
+        pVoltageReq = pVoltageReq->pNext;
+    }
+
+    // If it is a new voltage request record, allocate and fill it in,
+    // otherwise just update power status. In both cases determine if
+    // power requirements for the module have changed.
+    if (pVoltageReq == NULL)
+    {
+        pVoltageReq = NvOsAlloc(sizeof(*pVoltageReq));
+        if (pVoltageReq == NULL)
+        {
+            NvOsMutexUnlock(s_hPowerClientMutex);
+            return NvError_InsufficientMemory;
+        }
+        // Link at head
+        pVoltageReq->pNext = pPowerClient->pVoltageReqHead;
+        pPowerClient->pVoltageReqHead = pVoltageReq;
+        pVoltageReq->ModuleId = ModuleId;
+        pVoltageReq->PowerGroup = PowerGroup;
+        pVoltageReq->PowerCycled = NV_FALSE;
+
+        // Only new power On request counts as change
+        PowerChanged = (MaxVolts != NvRmVoltsOff);
+    }
+    else
+    {
+        // Only changes from On to Off or vice versa counts
+        PowerChanged = (pVoltageReq->MaxVolts != MaxVolts) &&
+                       ((pVoltageReq->MaxVolts == NvRmVoltsOff) ||
+                        (MaxVolts == NvRmVoltsOff));
+    }
+    // Record new power request voltages
+    pVoltageReq->MinVolts = MinVolts;
+    pVoltageReq->MaxVolts = MaxVolts;
+
+    // If module power requirements have changed, update power group reference
+    // count, and execute the respective h/w power control procedure
+    if (PowerChanged)
+    {
+        if (MaxVolts != NvRmVoltsOff)
+        {
+            s_PowerOnRefCounts[PowerGroup]++;
+            if (s_PowerOnRefCounts[PowerGroup] == 1)
+            {
+                NvRmMilliVolts v =
+                    NvRmPrivPowerGroupGetVoltage(hRmDeviceHandle, PowerGroup);
+                if (v == NvRmVoltsOff)
+                {
+                    RecordPowerCycle(hRmDeviceHandle, PowerGroup);
+                    NvRmPrivPowerGroupControl(hRmDeviceHandle, PowerGroup, NV_TRUE);
+                }
+            }
+        }
+        else
+        {
+            NV_ASSERT(s_PowerOnRefCounts[PowerGroup] != 0);
+            if (s_PowerOnRefCounts[PowerGroup] == 0)
+            {
+                NVRM_POWER_PRINTF(("Power balance failed: module %d\n", ModuleId));
+            }
+            s_PowerOnRefCounts[PowerGroup]--;
+            if (s_PowerOnRefCounts[PowerGroup] == 0)
+            {
+                NvRmPrivPowerGroupControl(hRmDeviceHandle, PowerGroup, NV_FALSE);
+            }
+        }
+    }
+    ReportRmPowerState(hRmDeviceHandle);
+
+    // Return current voltage, unless this is the first request after module
+    // was power cycled by RM; in the latter case return NvRmVoltsCycled value
+    if (pCurrentVolts != NULL)
+    {
+        *pCurrentVolts = NvRmPrivPowerGroupGetVoltage(hRmDeviceHandle, PowerGroup);
+        if (pVoltageReq->PowerCycled && (*pCurrentVolts != NvRmVoltsOff))
+        {
+            *pCurrentVolts = NvRmVoltsCycled;
+        }
+    }
+    // In any case clear power cycled indicator
+    pVoltageReq->PowerCycled = NV_FALSE;
+
+    NvOsMutexUnlock(s_hPowerClientMutex);
+    return NvSuccess;
+}
+
+void
+NvRmListPowerAwareModules(
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvU32* pListSize,
+    NvRmModuleID* pIdList,
+    NvBool* pActiveList)
+{
+    NvBool active;
+    NvU32 i, ModulesNum, ActiveNum;
+    ModuleVoltageReq* pVoltageReq = NULL;
+    NvRmPowerClient* pPowerClient = NULL;
+    NvRmPowerRegistry* pRegistry = &s_PowerRegistry;
+
+
+    /* validate the Rm Handle */
+    NV_ASSERT(hRmDeviceHandle);
+    NV_ASSERT(pListSize);
+    NV_ASSERT(((*pListSize) == 0) || (pIdList && pActiveList));
+
+    NvOsMutexLock(s_hPowerClientMutex);
+
+    // Count power aware modules, fill in the list
+    for (i = ModulesNum = ActiveNum = 0; i < pRegistry->UsedIndexRange; i++)
+    {
+        pPowerClient = pRegistry->pPowerClients[i];
+        if (pPowerClient)
+        {
+            pVoltageReq = pPowerClient->pVoltageReqHead;
+            while (pVoltageReq != NULL)
+            {
+                ModulesNum++;
+                active = (pVoltageReq->MaxVolts != NvRmVoltsOff);
+                ActiveNum += active ? 1 : 0;
+                if (*pListSize >= ModulesNum)
+                {
+                    *(pIdList++) = pVoltageReq->ModuleId;
+                    *(pActiveList++) = active;
+                }
+                pVoltageReq = pVoltageReq->pNext;
+            }
+        }
+    }
+    // Report number of found modules
+    if ((*pListSize == 0) || (*pListSize > ModulesNum))
+    {
+        *pListSize = ModulesNum;
+    }
+    // Total refcounts must be = number of active modules
+    for (i = 0; i <= NV_POWERGROUP_MAX; i++)
+        ActiveNum -= s_PowerOnRefCounts[i];
+    NV_ASSERT(ActiveNum == 0);
+
+    NvOsMutexUnlock(s_hPowerClientMutex);
+}
+
+/*****************************************************************************/
+
+static NvError
+RecordStarvationHints(
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvRmPowerClient* pPowerClient,
+    const NvRmDfsStarvationHint* pMultiHint,
+    NvU32 NumHints)
+{
+    NvU32 i;
+    NvBool HintChanged = NV_FALSE;
+
+    for (i = 0; i < NumHints; i++)
+    {
+        NvRmDfsClockId ClockId = pMultiHint[i].ClockId;
+        NvBool Starving = pMultiHint[i].Starving;
+        NV_ASSERT((0 < ClockId) && (ClockId < NvRmDfsClockId_Num));
+
+        /*
+         * If this is the first starvation hint, allocate hints array and fill
+         * it in. Otherwise, just update starvation hint status. In both cases
+         * determine if starvation hint for clock domain has changed.
+         */
+        if (pPowerClient->pStarvationHints == NULL)
+        {
+            size_t s = sizeof(NvBool) * (size_t)NvRmDfsClockId_Num;
+            NvBool* p = NvOsAlloc(s);
+            if (p == NULL)
+            {
+                return NvError_InsufficientMemory;
+            }
+            NvOsMemset(p, 0, s);
+            pPowerClient->pStarvationHints = p;
+
+            // Only new Satrvation On hint counts as change
+            HintChanged = Starving;
+        }
+        else
+        {
+            // Only changes from On to Off or vice versa counts
+            HintChanged = (pPowerClient->pStarvationHints[ClockId] != Starving);
+        }
+        pPowerClient->pStarvationHints[ClockId] = Starving;
+
+        // If hint has changed, update clock domain starvation reference count
+        // (hint against CPU, or AVP, or VDE is automatically applied to EMC)
+        if (HintChanged)
+        {
+            if (Starving)
+            {
+                if ((ClockId == NvRmDfsClockId_Cpu) ||
+                    (ClockId == NvRmDfsClockId_Avp) ||
+                    (ClockId == NvRmDfsClockId_Vpipe))
+                {
+                    s_StarveOnRefCounts[NvRmDfsClockId_Emc]++;
+                }
+                s_StarveOnRefCounts[ClockId]++;
+            }
+            else
+            {
+                if ((ClockId == NvRmDfsClockId_Cpu) ||
+                    (ClockId == NvRmDfsClockId_Avp) ||
+                    (ClockId == NvRmDfsClockId_Vpipe))
+                {
+                    NV_ASSERT(s_StarveOnRefCounts[NvRmDfsClockId_Emc] != 0);
+                    s_StarveOnRefCounts[NvRmDfsClockId_Emc]--;
+                }
+                NV_ASSERT(s_StarveOnRefCounts[ClockId] != 0);
+                s_StarveOnRefCounts[ClockId]--;
+            }
+        }
+    }
+    return NvSuccess;
+}
+
+NvBool NvRmPrivDfsIsStarving(NvRmDfsClockId ClockId)
+{
+    NV_ASSERT((0 < ClockId) && (ClockId < NvRmDfsClockId_Num));
+    // Boolean read - no need for lock
+    return (s_StarveOnRefCounts[ClockId] != 0);
+}
+
+NvError
+NvRmPowerStarvationHintMulti(
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvU32 ClientId,
+    const NvRmDfsStarvationHint* pMultiHint,
+    NvU32 NumHints)
+{
+    NvError error;
+    NvRmPowerClient* pPowerClient = NULL;
+    NvRmPowerRegistry* pRegistry = &s_PowerRegistry;
+    NvU32 ClientIndex = NVRM_POWER_ID2INDEX(ClientId);
+
+    NV_ASSERT(hRmDeviceHandle);
+    NV_ASSERT(pMultiHint && NumHints);
+
+    /* Do nothing on platforms where there is no freq scaling like QT and FPGA */
+    if (NvRmPrivGetExecPlatform(hRmDeviceHandle) != ExecPlatform_Soc)
+    {
+        return NvSuccess;
+    }
+    // Do nothing if DFS is disabled, and therefore all clocks are maxed anyway
+    if (NvRmDfsGetState(hRmDeviceHandle) <= NvRmDfsRunState_Disabled)
+    {
+        return NvSuccess;
+    }
+
+    NvOsMutexLock(s_hPowerClientMutex);
+
+    // Check if this client ID was registered; return error otherwise
+    if (ClientIndex < pRegistry->UsedIndexRange)
+    {
+        pPowerClient = pRegistry->pPowerClients[ClientIndex];
+    }
+    if ((pPowerClient == NULL) || (pPowerClient->id != ClientId))
+    {
+        NvOsMutexUnlock(s_hPowerClientMutex);
+        return NvError_BadValue;
+    }
+    // Add new stravtion hint
+    error = RecordStarvationHints(
+        hRmDeviceHandle, pPowerClient, pMultiHint, NumHints);
+
+    NvOsMutexUnlock(s_hPowerClientMutex);
+
+    if (error == NvSuccess)
+        NvRmPrivStarvationHintPrintf(
+            ClientIndex, pPowerClient->tag, pMultiHint, NumHints);
+    return error;
+}
+
+NvError
+NvRmPowerStarvationHint (
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvRmDfsClockId ClockId,
+    NvU32 ClientId,
+    NvBool Starving)
+{
+    NvRmDfsStarvationHint StarvationHint;
+
+    // Pack hit record
+    StarvationHint.ClockId = ClockId;
+    StarvationHint.Starving = Starving;
+
+    return NvRmPowerStarvationHintMulti(
+        hRmDeviceHandle, ClientId, &StarvationHint, 1);
+}
+
+/*****************************************************************************/
+
+static void CancelBusyHints(NvRmDfsClockId ClockId, NvU32 ClientId)
+{
+    BusyHintReq* pBusyHintReq = NULL;
+    BusyHintReq* pBusyHintNext = NULL;
+
+    /*
+     * Traverse busy hints list, starting from the head and looking for hints
+     * reported by the specified client. Remove found hint nodes on the way.
+     */
+    pBusyHintReq = &s_BusyReqHeads[ClockId];
+    if (pBusyHintReq->ClientId == ClientId)
+    {
+        pBusyHintReq->IntervalMs = 0;   // Keep head for just one more sample
+    }
+    while (pBusyHintReq != NULL)
+    {
+        pBusyHintNext = pBusyHintReq->pNext;
+        if ((pBusyHintNext != NULL) && (pBusyHintNext->ClientId == ClientId))
+        {
+            pBusyHintReq->pNext = pBusyHintNext->pNext;
+            NvOsFree(pBusyHintNext);
+            continue;
+        }
+        pBusyHintReq = pBusyHintNext;
+    }
+}
+
+static void PurgeBusyHints(NvRmDfsClockId ClockId, NvU32 msec)
+{
+    static NvU32 s_LastPurgeMs = 0;
+    BusyHintReq* pBusyHintReq = NULL;
+    BusyHintReq* pBusyHintNext = NULL;
+
+    if ((msec - s_LastPurgeMs) <= NVRM_DFS_BUSY_PURGE_MS)
+        return;
+
+    /*
+     * If time to purge the busy hints list, traverse it starting from the
+     * head and looking for the expired hints. Remove found nodes on the way.
+     */
+    pBusyHintReq = &s_BusyReqHeads[ClockId];
+    while (pBusyHintReq != NULL)
+    {
+        pBusyHintNext = pBusyHintReq->pNext;
+        if ( (pBusyHintNext != NULL) &&
+             (pBusyHintNext->IntervalMs < (msec - pBusyHintNext->StartTimeMs)) )
+        {
+            pBusyHintReq->pNext = pBusyHintNext->pNext;
+            NvOsFree(pBusyHintNext);
+            continue;
+        }
+        pBusyHintReq = pBusyHintNext;
+    }
+    s_LastPurgeMs = msec;
+}
+
+static NvError
+RecordBusyHints(
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvU32 ClientId,
+    const NvRmDfsBusyHint* pMultiHint,
+    NvU32 NumHints,
+    NvBool* pSignalDfs)
+{
+    NvU32 i;
+    NvRmFreqKHz MaxKHz;
+    BusyHintReq* pInsert = NULL;
+    BusyHintReq* pBusyHintReq = NULL;
+    NvU32 msec = NvOsGetTimeMS();
+
+    *pSignalDfs = NV_FALSE;
+
+    for (i = 0; i < NumHints; i++)
+    {
+        NvRmDfsClockId ClockId = pMultiHint[i].ClockId;
+        NvRmFreqKHz BoostKHz = pMultiHint[i].BoostKHz;
+        NvU32 BoostDurationMs = pMultiHint[i].BoostDurationMs;
+        NvBool BusyPulseMode = pMultiHint[i].BusyAttribute;
+        NV_ASSERT((0 < ClockId) && (ClockId < NvRmDfsClockId_Num));
+
+        // Clip requested boost frequency to domain maximum
+        MaxKHz = NvRmPrivDfsGetMaxKHz(ClockId);
+        if (BoostKHz > MaxKHz)
+        {
+            BoostKHz = MaxKHz;
+        }
+
+        // Cancel all hints sent by this client if it is no longer busy;
+        // signal DFS boost removed
+        if (BoostKHz == 0)
+        {
+            CancelBusyHints(ClockId, ClientId);
+            *pSignalDfs = NV_TRUE;
+            continue;
+        }
+
+        // Update maximum boost frequency stored in the head entry; signal DFS
+        // boost increase
+        if (s_BusyReqHeads[ClockId].BoostKHz < BoostKHz)
+        {
+            s_BusyReqHeads[ClockId].BoostKHz = BoostKHz;
+            s_BusyReqHeads[ClockId].IntervalMs = BoostDurationMs;
+            s_BusyReqHeads[ClockId].BusyPulseMode = BusyPulseMode;
+            s_BusyReqHeads[ClockId].StartTimeMs = msec;
+            s_BusyReqHeads[ClockId].ClientId = ClientId;
+            *pSignalDfs = NV_TRUE;
+        }
+
+        /*
+         * If it is a short spike no need to store the record, as maximum boost
+         * has been already updated. Otherwise, insert new busy record into the
+         * busy hints list in descending order of requested boost frequencies
+         */
+        if (BoostDurationMs > NVRM_DFS_BUSY_MIN_MS)
+        {
+            for (pInsert = &s_BusyReqHeads[ClockId] ;;)
+            {
+                if ((pInsert->pNext == NULL) ||
+                    (pInsert->pNext->BoostKHz < BoostKHz))
+                {
+                    // Allocate and initialize new boost hint record
+                    pBusyHintReq = NvOsAlloc(sizeof(BusyHintReq));
+                    if (pBusyHintReq == NULL)
+                    {
+                        return NvError_InsufficientMemory;
+                    }
+                    pBusyHintReq->BoostKHz = BoostKHz;
+                    pBusyHintReq->IntervalMs = BoostDurationMs;
+                    pBusyHintReq->BusyPulseMode = BusyPulseMode;
+                    pBusyHintReq->StartTimeMs = msec;
+                    pBusyHintReq->ClientId = ClientId;
+                    pBusyHintReq->pNext = pInsert->pNext;
+                    pInsert->pNext = pBusyHintReq;
+                    break;
+                }
+                else if (pInsert->pNext->BoostKHz == BoostKHz)
+                {
+                    // Combine hints from the same client with the same
+                    // boost level and pulse mode
+                    if ((pInsert->pNext->ClientId == ClientId) &&
+                        (pInsert->pNext->BusyPulseMode == BusyPulseMode))
+                    {
+                        NvU32 t = msec - pInsert->pNext->StartTimeMs;
+                        if ((BoostDurationMs > pInsert->pNext->IntervalMs) ||
+                            (t > (pInsert->pNext->IntervalMs - BoostDurationMs)))
+                        {
+                            pInsert->pNext->StartTimeMs = msec;
+                            pInsert->pNext->IntervalMs = BoostDurationMs;
+                        }
+                        break;
+                    }
+                }
+                pInsert = pInsert->pNext;
+            }
+            PurgeBusyHints(ClockId, msec);  // Purge the list once in a while
+        }
+    }
+    return NvSuccess;
+}
+
+void NvRmPrivDfsGetBusyHint(
+    NvRmDfsClockId ClockId,
+    NvRmFreqKHz* pBusyKHz,
+    NvBool* pBusyPulseMode,
+    NvU32* pBusyExpireMs)
+{
+    NvU32 msec;
+    BusyHintReq* pBusyHintReq;
+
+    NV_ASSERT((0 < ClockId) && (ClockId < NvRmDfsClockId_Num));
+
+    // Boolean read - no need for lock - fast path for most common case
+    // when no busy hints are recoeded
+    if (s_BusyReqHeads[ClockId].BoostKHz == 0)
+    {
+        *pBusyKHz = 0;
+        *pBusyPulseMode = NV_FALSE;
+        *pBusyExpireMs = 0;
+        return;
+    }
+    msec = NvOsGetTimeMS();
+
+    NvOsMutexLock(s_hPowerClientMutex);
+    /*
+     * Get boost frequency from the head. Then, traverse busy hints list,
+     * starting from the head looking for max non-expired frequency boost.
+     * Remove expired nodes on the way. Update head boost frequency.
+     */
+    pBusyHintReq = &s_BusyReqHeads[ClockId];
+    *pBusyKHz = pBusyHintReq->BoostKHz;
+    *pBusyPulseMode = pBusyHintReq->BusyPulseMode;
+    *pBusyExpireMs = 0;     // assume head hint has already expired
+    if (pBusyHintReq->IntervalMs == NV_WAIT_INFINITE)
+        *pBusyExpireMs = NV_WAIT_INFINITE;  // head hint until canceled
+    else if (pBusyHintReq->IntervalMs >= (msec - pBusyHintReq->StartTimeMs))
+        *pBusyExpireMs =                    // non-expired head hint
+        pBusyHintReq->IntervalMs - (msec - pBusyHintReq->StartTimeMs);
+
+    pBusyHintReq = pBusyHintReq->pNext;
+    while (pBusyHintReq != NULL)
+    {
+        BusyHintReq* p;
+        if (pBusyHintReq->IntervalMs >= (msec - pBusyHintReq->StartTimeMs))
+        {
+            break;
+        }
+        p = pBusyHintReq;
+        pBusyHintReq = pBusyHintReq->pNext;
+        NvOsFree(p);
+    }
+    if (pBusyHintReq)
+    {
+        s_BusyReqHeads[ClockId] = *pBusyHintReq;
+        s_BusyReqHeads[ClockId].pNext = pBusyHintReq;
+    }
+    else
+        NvOsMemset(&s_BusyReqHeads[ClockId], 0, sizeof(s_BusyReqHeads[ClockId]));
+    NvOsMutexUnlock(s_hPowerClientMutex);
+}
+
+NvError
+NvRmPowerBusyHintMulti(
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvU32 ClientId,
+    const NvRmDfsBusyHint* pMultiHint,
+    NvU32 NumHints,
+    NvRmDfsBusyHintSyncMode Mode)
+{
+    NvError error;
+    NvRmDfsRunState DfsState;
+    NvBool SignalDfs = NV_FALSE;
+    NvRmPowerClient* pPowerClient = NULL;
+    NvRmPowerRegistry* pRegistry = &s_PowerRegistry;
+    NvU32 ClientIndex = NVRM_POWER_ID2INDEX(ClientId);
+
+    NV_ASSERT(hRmDeviceHandle);
+    NV_ASSERT(pMultiHint && NumHints);
+    DfsState = NvRmDfsGetState(hRmDeviceHandle);
+
+    /* Do nothing on platforms where there is no freq scaling like QT and FPGA */
+    if (NvRmPrivGetExecPlatform(hRmDeviceHandle) != ExecPlatform_Soc)
+    {
+        return NvSuccess;
+    }
+    // Do nothing if DFS is disabled, and therefore all clocks are maxed anyway
+    if (DfsState <= NvRmDfsRunState_Disabled)
+    {
+        return NvSuccess;    // error if disabled
+    }
+
+    NvOsMutexLock(s_hPowerClientMutex);
+
+    // Check if this client ID was registered; return error otherwise
+    if (ClientIndex < pRegistry->UsedIndexRange)
+    {
+        pPowerClient = pRegistry->pPowerClients[ClientIndex];
+    }
+    if ((pPowerClient == NULL) || (pPowerClient->id != ClientId))
+    {
+        NvOsMutexUnlock(s_hPowerClientMutex);
+        return NvError_BadValue;
+    }
+    // Add new busy hint record to the list
+    error = RecordBusyHints(
+        hRmDeviceHandle, ClientId, pMultiHint, NumHints, &SignalDfs);
+
+    NvOsMutexUnlock(s_hPowerClientMutex);
+
+    if (error == NvSuccess)
+    {
+        NvRmPrivBusyHintPrintf(
+            ClientIndex, pPowerClient->tag, pMultiHint, NumHints);
+        if (SignalDfs && (DfsState > NvRmDfsRunState_Stopped))
+        {
+            // Signal DFS clock control provided DFS is running
+            NvRmPrivDfsSignal(Mode);
+        }
+    }
+    return error;
+}
+
+NvError
+NvRmPowerBusyHint (
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvRmDfsClockId ClockId,
+    NvU32 ClientId,
+    NvU32 BoostDurationMs,
+    NvRmFreqKHz BoostKHz)
+{
+    NvRmDfsBusyHint BusyHint;
+
+    // Pack hint record
+    BusyHint.ClockId = ClockId;
+    BusyHint.BoostKHz = BoostKHz;
+    BusyHint.BoostDurationMs = BoostDurationMs;
+    BusyHint.BusyAttribute = NV_FALSE;
+
+    return NvRmPowerBusyHintMulti(hRmDeviceHandle, ClientId, &BusyHint, 1,
+                                  NvRmDfsBusyHintSyncMode_Async);
+}
+
+/*****************************************************************************/
+
+NvError
+NvRmPowerActivityHint (
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvRmModuleID ModuleId,
+    NvU32 ClientId,
+    NvU32 ActivityDurationMs)
+{
+    /* validate the Rm Handle */
+    NV_ASSERT( hRmDeviceHandle );
+
+    return NvError_NotImplemented;
+}
+
+NvError
+NvRmKernelPowerSuspend( NvRmDeviceHandle hRmDeviceHandle )
+{
+    NvOdmSocPowerState state =
+        NvOdmQueryLowestSocPowerState()->LowestPowerState;
+
+    NvRmPrivDfsSuspend(state);
+    if (state ==  NvOdmSocPowerState_Suspend)
+        NvRmPrivPowerGroupSuspend(hRmDeviceHandle);
+    NvRmPrivPmuLPxStateConfig(hRmDeviceHandle, state, NV_TRUE);
+
+#if NVRM_POWER_DEBUG_SUSPEND_ENTRY
+    NvOsMutexLock(s_hPowerClientMutex);
+    {
+        NvU32 i;
+        ModuleVoltageReq* pVoltageReq = NULL;
+        NvRmPowerClient* pPowerClient = NULL;
+        NvRmPowerRegistry* pRegistry = &s_PowerRegistry;
+        NvRmPowerState s = NvRmPrivPowerGetState(hRmDeviceHandle);
+
+        // Report combined RM power stste and active modules
+        NvOsDebugPrintf("RM power state before suspend: %s (%d)\n",
+           ((s == NvRmPowerState_Active) ? "Active" :
+            ((s == NvRmPowerState_AutoHw) ? "AutoHw" : "Idle")), s);
+        if (s == NvRmPowerState_Active)
+        {
+            for (i = 0; i < pRegistry->UsedIndexRange; i++)
+            {
+                pPowerClient = pRegistry->pPowerClients[i];
+                if (pPowerClient)
+                {
+                    pVoltageReq = pPowerClient->pVoltageReqHead;
+                    while (pVoltageReq != NULL)
+                    {
+                        if (pVoltageReq->MaxVolts != NvRmVoltsOff)
+                        {
+                            // could also set some bad e = NvError_Bad???
+                            NvOsDebugPrintf("Active Module: 0x%x",
+                                                pVoltageReq->ModuleId);
+                        }
+                        pVoltageReq = pVoltageReq->pNext;
+                    }
+                }
+            }
+        }
+    }
+    NvOsMutexUnlock(s_hPowerClientMutex);
+#endif
+
+    return NvSuccess;
+}
+
+NvError
+NvRmKernelPowerResume( NvRmDeviceHandle hRmDeviceHandle )
+{
+    NvOdmSocPowerState state =
+        NvOdmQueryLowestSocPowerState()->LowestPowerState;
+
+    NvRmPrivPmuLPxStateConfig(hRmDeviceHandle, state, NV_FALSE);
+    if (state ==  NvOdmSocPowerState_Suspend)
+        NvRmPrivPowerGroupResume(hRmDeviceHandle);
+    return NvSuccess;
+}
+
+
+
diff --git a/arch/arm/mach-tegra/nvrm/core/common/nvrm_power_dfs.c b/arch/arm/mach-tegra/nvrm/core/common/nvrm_power_dfs.c
new file mode 100644
index 000000000000..0f25159a15f6
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/core/common/nvrm_power_dfs.c
@@ -0,0 +1,3670 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/** 
+ * @file
+ * @brief <b>nVIDIA Driver Development Kit: 
+ *           Power Resource manager </b>
+ *
+ * @b Description: Implements NvRM Dynamic Voltage and Frequency Scaling for
+ *                  for SOC-wide clock domains.
+ * 
+ */
+
+#include "nvrm_power_dfs.h"
+#include "nvrm_pmu.h"
+#include "nvrm_pmu_private.h"
+#include "nvassert.h"
+#include "nvrm_hwintf.h"
+#include "nvodm_query_discovery.h"
+#include "ap15/ap15rm_private.h"
+#include "ap15/ap15rm_power_dfs.h"
+#include "ap15/ap15rm_clocks.h"
+#include "ap20/ap20rm_power_dfs.h"
+#include "ap20/ap20rm_clocks.h"
+
+/*****************************************************************************/
+
+// Initial DFS configuration
+#define AP15_FPGA_FREQ (8330)
+#define AP20_FPGA_FREQ (13000)
+#define NVRM_FPGA_INITIAL_DFS_STATE (NvRmDfsRunState_Disabled)
+#define NVRM_AP15_SOC_INITIAL_DFS_STATE (NvRmDfsRunState_Stopped)
+#define NVRM_AP20_SOC_INITIAL_DFS_STATE (NvRmDfsRunState_Stopped)
+#define NVRM_EMC_DFS_DEFAULT_DISABLED (0)
+
+// Low boundaries for DFS clock frequencies imposed by download transports.
+// For Ethernet this limitation is related to MIO WAR, and it is applied only
+// to AP15 A01.
+#define NVRM_USB_AHB_MIN_KHZ (100000)
+#define NVRM_ETHERNET_AHB_MIN_KHZ (30000)
+#define NVRM_ETHERNET_EMC_MIN_KHZ (24000)
+#define NVRM_SPI_CPU_MIN_KHZ (40000)
+#define NVRM_SPI_APB_MIN_KHZ (30000)
+
+// An option to stall average accumulation during busy pulse
+#define NVRM_DFS_STALL_AVERAGE_IN_BUSY_PULSE (0)
+
+// Options for temperature monitoring
+#define NVRM_DTT_DISABLED (0)
+#define NVRM_DTT_USE_INTERRUPT (1)
+#define NVRM_DTT_RANGE_CHANGE_PRINTF (1)
+
+// Allow PMUs with CPU voltage range above chip minimum
+#define NVRM_DVS_ACCEPT_PMU_HIGH_CPU_MIN (1)
+
+/*****************************************************************************/
+
+// TODO: Always Disable before check-in
+// Module debug: 0=disable, 1=enable
+#define NVRM_DFS_ENABLE_PRINTF (0)
+#if NVRM_DFS_ENABLE_PRINTF
+#define NVRM_DFS_PRINTF(x)   NvOsDebugPrintf x
+#else
+#define NVRM_DFS_PRINTF(x)
+#endif
+
+// TODO: Always Disable before check-in
+// DFS profiling: 0=disable, 1=enable (prints from clock control thread)
+#define DFS_PROFILING (0)
+
+// TODO: Always Disable before check-in
+// DFS clients busy and starvation hints report: 0=disable, 1=enable
+// (prints from client API thread)
+#define DFS_HINTS_PRINTF (0)
+
+// TODO: Always Disable before check-in
+// DFS detailed logging: 0=disable, non zero = enable (saves dfs log in memory
+//  for at least specified number of seconds)
+#define DFS_LOGGING_SECONDS (0)
+
+// TODO: Always Disable before check-in
+// DFS sync busy int timeout: 0=disable, non zero = enable (set sync busy hint
+//  timeout for specified number of milliseconds)
+#define DFS_SYNC_BUSY_TIMEOUT_MS (0)
+
+/*****************************************************************************/
+
+// Microsecond timer read macro
+#define NvRmPrivGetUs() NV_READ32(s_pTimerUs)
+
+/*****************************************************************************/
+
+#if DFS_PROFILING
+
+typedef struct DfsProfileRec
+{
+    NvU32 SamplesNo[NvRmDfsProfileId_Num];
+    NvU32 StartUs[NvRmDfsProfileId_Num];
+    NvU32 AccumulatedUs[NvRmDfsProfileId_Num];
+} DfsProfile;
+
+
+#define DfsProfileInit(pDfs) \
+do\
+{\
+    NvU32 i; \
+    NvOsMemset(&s_Profile, 0, sizeof(DfsProfile)); \
+    for (i = 1; i < NvRmDfsProfileId_Num; i++) \
+    {\
+        s_Profile.StartUs[i] = NvRmPrivGetUs(); \
+    }\
+} while(0)
+
+#define DfsProfileStart(pDfs, ProfileId) \
+do\
+{\
+    if ((pDfs)->DfsRunState == NvRmDfsRunState_ProfiledLoop) \
+    {\
+        s_Profile.StartUs[(ProfileId)] = NvRmPrivGetUs(); \
+    }\
+} while(0)
+
+#define DfsProfileSample(pDfs, ProfileId) \
+do\
+{\
+    if ((pDfs)->DfsRunState == NvRmDfsRunState_ProfiledLoop) \
+    {\
+        s_Profile.SamplesNo[(ProfileId)]++; \
+        s_Profile.AccumulatedUs[(ProfileId)] += \
+            (NvRmPrivGetUs() - s_Profile.StartUs[(ProfileId)]); \
+    }\
+} while(0)
+
+static DfsProfile s_Profile = {{0}};
+
+#else
+
+#define DfsProfileInit(pDfs) 
+#define DfsProfileStart(pDfs, ProfileId) 
+#define DfsProfileSample(pDfs, ProfileId) 
+#endif
+
+/*****************************************************************************/
+
+#if DFS_HINTS_PRINTF
+
+#define DfsHintsPrintInit() \
+do\
+{\
+    s_DfsDomainNames[NvRmDfsClockId_Cpu] = "Cpu"; \
+    s_DfsDomainNames[NvRmDfsClockId_Avp] = "Avp"; \
+    s_DfsDomainNames[NvRmDfsClockId_System] = "Sys"; \
+    s_DfsDomainNames[NvRmDfsClockId_Ahb] = "Ahb"; \
+    s_DfsDomainNames[NvRmDfsClockId_Apb] = "Apb"; \
+    s_DfsDomainNames[NvRmDfsClockId_Vpipe] = "Vde"; \
+    s_DfsDomainNames[NvRmDfsClockId_Emc] = "Emc"; \
+} while (0);
+
+static char* s_DfsDomainNames[NvRmDfsClockId_Num];
+
+static void ClientTagToString(NvU32 ClientTag, char ClientName[])
+{
+    NvU32 i;
+
+    // Unpack in reverse order 4 caharacters from 32-bit DFS client tag
+    for (i = 0; i < sizeof(ClientTag); i++)
+    {
+        NvU8 c = (NvU8)(ClientTag & 0xFF);
+        ClientTag >>= 8;
+        if ((c < ' ') || (c > 0x7F))
+            c = '*'; // non-ASCII codes in non-initialized tags
+        ClientName[sizeof(ClientTag) - 1 - i] = c;
+    }
+    ClientName[sizeof(ClientTag)] = 0x00;
+}
+
+#else
+#define DfsHintsPrintInit()
+#endif
+
+/*****************************************************************************/
+
+#if DFS_LOGGING_SECONDS
+
+// Log size, assuming ~100 samples / sec
+#define DFS_LOG_SIZE (100 * DFS_LOGGING_SECONDS)
+
+typedef struct DfsLogEntryRec
+{
+    NvU32 SampleIntervalMs;
+    NvU32 Lp2TimeMs;
+    NvU32 ActiveCycles[NvRmDfsClockId_Num];
+    NvRmDfsFrequencies CurrentKHz;
+    NvRmDfsFrequencies AverageKHz;
+} DfsLogEntry;
+
+typedef struct DfsLogStarvationHintRec
+{
+    NvU32 LogSampleIndex;
+    NvU32 ClientId;
+    NvU32 ClientTag;
+    NvRmDfsStarvationHint StarvationHint;
+} DfsLogStarvationHint;
+
+typedef struct DfsLogBusyHintRec
+{
+    NvU32 LogSampleIndex;
+    NvU32 ClientId;
+    NvU32 ClientTag;
+    NvRmDfsBusyHint BusyHint;
+} DfsLogBusyHint;
+
+static NvU32 s_DfsLogWrIndex = 0;
+static DfsLogEntry s_DfsLog[DFS_LOG_SIZE];
+
+static NvU32 s_DfsLogStarvationWrIndex = 0;
+static DfsLogStarvationHint s_DfsLogStarvation[DFS_LOG_SIZE];
+
+static NvU32 s_DfsLogBusyWrIndex = 0;
+static DfsLogBusyHint s_DfsLogBusy[DFS_LOG_SIZE];
+
+#define DfsLogEnter(pDfs, Lp2Ms) \
+do\
+{\
+    if (s_DfsLogOn && (s_DfsLogWrIndex < DFS_LOG_SIZE)) \
+    {\
+        NvU32 i; \
+        DfsLogEntry* pEntry = &s_DfsLog[s_DfsLogWrIndex++]; \
+        pEntry->SampleIntervalMs = *(pDfs)->SamplingWindow.pLastInterval; \
+        pEntry->Lp2TimeMs = (Lp2Ms); \
+        for (i = 1; i < NvRmDfsClockId_Num; i++) \
+        { \
+            pEntry->ActiveCycles[i] = *(pDfs)->Samplers[i].pLastSample; \
+            pEntry->AverageKHz.Domains[i] = (pDfs)->Samplers[i].AverageKHz; \
+        } \
+        pEntry->CurrentKHz = (pDfs)->CurrentKHz; \
+    }\
+} while(0)
+
+#else
+#define DfsLogEnter(pDfs, Lp2TimeMs)
+#endif
+
+/*****************************************************************************/
+
+#if NVRM_DTT_RANGE_CHANGE_PRINTF
+
+#define DttRangeReport(T, pDtt) \
+do\
+{\
+    NvOsDebugPrintf("DTT: T = %d, Range = %d (%d : %d)\n", \
+        (T), (pDtt)->TcorePolicy.PolicyRange, \
+        (pDtt)->TcorePolicy.LowLimit, (pDtt)->TcorePolicy.HighLimit); \
+} while(0)
+
+#else
+#define DttRangeReport(T, pDtt)
+#endif
+
+/*****************************************************************************/
+
+// DFS object
+static NvRmDfs s_Dfs;
+
+// Execution Platform
+static ExecPlatform s_Platform;
+
+// Microsecond timer virtual address
+static void* s_pTimerUs;
+
+// NV DFS logging enabled indicator
+static NvBool s_DfsLogOn = NV_FALSE;
+
+
+/*****************************************************************************/
+/*****************************************************************************/
+
+/*
+ * Gets monitoring capabilities of the DFS module
+ */
+static NvError SystatMonitorsGetCapabilities(NvRmDfs* pDfs);
+static NvError VdeMonitorsGetCapabilities(NvRmDfs* pDfs);
+static NvError EmcMonitorsGetCapabilities(NvRmDfs* pDfs);
+
+/*                         
+ *  Gets monitoring capabilities of all DFS modules
+ */
+static NvError DfsGetModulesCapabilities(NvRmDfs* pDfs);
+
+/*
+ * Initializes all DFS HW monitors
+ */
+static NvError DfsHwInit(NvRmDfs* pDfs);
+
+/*
+ * Deinitializes all DFS HW monitors
+ */
+static void DfsHwDeinit(NvRmDfs* pDfs);
+
+/*
+ * Starts activity monitors in all DFS modules for the next sample interval
+ * and enables DFS interrupt
+ */
+static void
+DfsStartMonitors(
+    const NvRmDfs* pDfs,
+    const NvRmDfsFrequencies* pDfsKHz,
+    const NvU32 IntervalMs);
+
+/*
+ * Reads idle count from activity monitors in all DFS modules. The monitors are
+ * stopped.
+ */
+static void
+DfsReadMonitors(
+    const NvRmDfs* pDfs,
+    const NvRmDfsFrequencies* pDfsKHz,
+    NvRmDfsIdleData* pIdleData);
+
+/*****************************************************************************/
+
+/*
+ * Initializes DFS algorithm parameters
+ */
+static void DfsParametersInit(NvRmDfs* pDfs);
+
+/*
+ * Initializes DFS samplers for specified frequencies
+ */
+static void DfsSamplersInit(
+    const NvRmDfsFrequencies* pDfsKHz,
+    NvRmDfs* pDfs);
+
+/*****************************************************************************/
+
+/*
+ * DFS ISR (executes DFS algorithm)
+ */
+static void DfsIsr(void* args);
+
+/*
+ * Determines target frequencies for DFS domains
+ */
+static NvBool
+DfsGetTargetFrequencies(
+    const NvRmDfsIdleData* pIdleData,
+    NvRmDfs* pDfs,
+    NvRmDfsFrequencies* pDfsKHz);
+
+/*
+ * Adds new sample interval to the sample window
+ */
+static NvBool
+AddSampleInterval(
+    NvRmDfsSampleWindow* pSampleWindow,
+    NvU32 IntervalMs);
+
+/*
+ * Adds new activity sample to the domain buffer
+ */
+static void
+AddActivitySample(
+    NvRmDfsSampler* pDomainSampler,
+    NvU32 ActiveCount);
+
+// Determine PM thread request for CPU state control
+static NvRmPmRequest 
+DfsGetPmRequest(
+    NvRmDeviceHandle hRmDevice,
+    NvRmDfsSampler* pCpuSampler,
+    NvRmFreqKHz* pCpuKHz);
+
+/*****************************************************************************/
+
+/*
+ * DFS clock control thread entry point and termination function
+ */ 
+static NvRmPmRequest DfsThread(NvRmDfs* pDfs);
+static void DfsThreadTerminate(NvRmDfs* pDfs);
+
+/*
+ * Returns current frequencies of DFS clocks
+ */
+static void
+DfsClockFreqGet(
+    NvRmDeviceHandle hRmDevice,
+    NvRmDfsFrequencies* pDfsKHz);
+
+/*
+ * Configures DFS clocks according to target frequencies,
+ * and returns actual frequencies
+ */
+static NvBool
+DfsClockConfigure(
+    NvRmDeviceHandle hRmDevice,
+    const NvRmDfsFrequencies* pMaxKHz,
+    NvRmDfsFrequencies* pDfsKHz);
+
+/*
+ * Clips EMC frequency high limit to one of the fixed DFS EMC configurations,
+ * and if necessary adjust CPU high limit respectively.
+ */
+static void
+DfsClipCpuEmcHighLimits(
+    NvRmDeviceHandle hRmDevice,
+    NvRmFreqKHz* pCpuHighKHz,
+    NvRmFreqKHz* pEmcHighKHz);
+
+/*
+ * Emulate sampling results to achieve specified average frequency
+ * provided it is bigger than the current one 
+ */
+static void
+DfsSetAverageUp(
+    NvRmDfsClockId ClockId,
+    NvRmFreqKHz AverageKHz,
+    NvRmDfs* pDfs);
+
+/*
+ * Changes core and rtc voltages, keeping them in synch
+ */
+static void
+DvsChangeCoreVoltage(
+    NvRmDeviceHandle hRm,
+    NvRmDvs* pDvs,
+    NvRmMilliVolts TargetMv);
+
+/*
+ * Changes dedicated cpu rail voltage
+ */
+static void
+DvsChangeCpuVoltage(
+    NvRmDeviceHandle hRm,
+    NvRmDvs* pDvs,
+    NvRmMilliVolts TargetMv);
+
+/* 
+ * Enable/Disable voltage scaling
+ */
+static void NvRmPrivDvsRun(void);
+static void NvRmPrivDvsStopAtNominal(void);
+
+/*
+ * Updates thermal state and temperature monitoring policies according
+ * to the new sampled temperature.
+ */
+static void
+DttPolicyUpdate(
+    NvRmDeviceHandle hRm,
+    NvS32 TemperatureC,
+    NvRmDtt* pDtt);
+
+/*
+ * Updates (throttles) target DFS frequencies based on SoC temperature.
+ */
+static NvBool
+DttClockUpdate(
+    const NvRmDfs* pDfs,
+    NvRmDtt* pDtt,
+    NvRmDfsFrequencies* pDfsKHz);
+
+/*
+ * DTT interrupt handler
+ */
+static void DttIntrCallback(void* args);
+
+/*****************************************************************************/
+// MONITORING CAPABILITIES
+/*****************************************************************************/
+
+static NvError SystatMonitorsGetCapabilities(NvRmDfs* pDfs)
+{
+    NvError error;
+
+    NvRmModuleID ModuleId;
+    NvRmDfsModule* pCaps;
+    NvRmDfsModule SystatCaps[1] = {{{0}}};
+    NvRmModuleCapability ModuleCaps[1];
+    NvRmModuleTable *tbl;
+
+    NvRmDeviceHandle hRm = pDfs->hRm;
+
+    tbl = NvRmPrivGetModuleTable( hRm );
+
+    /*
+     * System Statistic module includes activity monitors for CPU, AVP, AHB,
+     * and APB domains. Its presence is required for DFS to work.   
+     */
+    SystatCaps[0].DomainMap[NvRmDfsClockId_Cpu] = NV_TRUE;
+    SystatCaps[0].DomainMap[NvRmDfsClockId_Avp] = NV_TRUE;
+    SystatCaps[0].DomainMap[NvRmDfsClockId_Ahb] = NV_TRUE;
+    SystatCaps[0].DomainMap[NvRmDfsClockId_Apb] = NV_TRUE;
+    SystatCaps[0].Init = NvRmPrivAp15SystatMonitorsInit;
+    SystatCaps[0].Deinit = NvRmPrivAp15SystatMonitorsDeinit;
+    SystatCaps[0].Start = NvRmPrivAp15SystatMonitorsStart;
+    SystatCaps[0].Read = NvRmPrivAp15SystatMonitorsRead;
+
+    ModuleCaps[0].MajorVersion = 1;
+    ModuleCaps[0].MinorVersion = 0;
+    ModuleCaps[0].EcoLevel = 0;
+    ModuleCaps[0].Capability = (void*)SystatCaps;
+
+    ModuleId = NVRM_MODULE_ID(NvRmModuleID_SysStatMonitor, 0);
+    error = NvRmModuleGetCapabilities(hRm, ModuleId, ModuleCaps, 1, (void **)&pCaps);
+    if (error != NvSuccess)
+    {
+        // Get capabilities failed - module is not present, DFS can not start
+        return error;
+    }
+    pCaps->pBaseReg = (tbl->ModInst +
+         tbl->Modules[NvRmModuleID_SysStatMonitor].Index)->VirtAddr;
+
+    // AP15/AP16 h/w bug 429585 - time spent by CPU in LP2 is not counted
+    // as idle - need explicitly offset monitor readings
+    if ((pDfs->hRm->ChipId.Id == 0x15) || (pDfs->hRm->ChipId.Id == 0x16))
+    {
+        pCaps->Offset = NVRM_CPU_IDLE_LP2_OFFSET;
+    }
+    pDfs->Modules[NvRmDfsModuleId_Systat] = *pCaps;
+    return NvSuccess;
+}
+
+static NvError VdeMonitorsGetCapabilities(NvRmDfs* pDfs)
+{
+    NvError error;
+
+    NvRmModuleID ModuleId;
+    NvRmDfsModule* pCaps;
+    NvRmDfsModule VdeCaps[2] = {{{0}}};
+    NvRmModuleCapability ModuleCaps[3];
+    NvRmModuleTable *tbl;
+
+    NvRmDeviceHandle hRm = pDfs->hRm;
+
+    tbl = NvRmPrivGetModuleTable( hRm );
+
+    /*
+     * VDE module includes activity monitor for video-pipe domain. This
+     * monitor may or may not be present on different versions of VDE
+     */
+    VdeCaps[0].DomainMap[NvRmDfsClockId_Vpipe] = NV_FALSE;
+
+    VdeCaps[1].DomainMap[NvRmDfsClockId_Vpipe] = NV_TRUE;
+    VdeCaps[1].Init = NvRmPrivAp15VdeMonitorsInit;
+    VdeCaps[1].Deinit = NvRmPrivAp15VdeMonitorsDeinit;
+    VdeCaps[1].Start = NvRmPrivAp15VdeMonitorsStart;
+    VdeCaps[1].Read = NvRmPrivAp15VdeMonitorsRead;
+
+    ModuleCaps[0].MajorVersion = 1; // AP15 A01
+    ModuleCaps[0].MinorVersion = 0;
+    ModuleCaps[0].EcoLevel = 0;
+    ModuleCaps[0].Capability = (void*)&VdeCaps[1];
+
+    ModuleCaps[1].MajorVersion = 1; // AP15 A02 (same caps as AP15 A01)
+    ModuleCaps[1].MinorVersion = 1;
+    ModuleCaps[1].EcoLevel = 0;
+    ModuleCaps[1].Capability = (void*)&VdeCaps[1];
+
+    ModuleCaps[2].MajorVersion = 1; // AP20 (same caps as AP15 A01)
+    ModuleCaps[2].MinorVersion = 2;
+    ModuleCaps[2].EcoLevel = 0;
+    ModuleCaps[2].Capability = (void*)&VdeCaps[1];
+
+    ModuleId = NVRM_MODULE_ID(NvRmModuleID_Vde, 0);
+    error = NvRmModuleGetCapabilities(hRm, ModuleId, ModuleCaps, 3, (void **)&pCaps);
+
+    if (error == NvSuccess)
+    {
+        if (pCaps->DomainMap[NvRmDfsClockId_Vpipe])
+        {
+            pCaps->pBaseReg =
+                (tbl->ModInst + tbl->Modules[NvRmModuleID_Vde].Index)->VirtAddr;
+        }
+    }
+    else
+    {
+        // If get capabilities failed, set "not present" cpabilities 
+        pCaps = &VdeCaps[0];
+    }
+    pDfs->Modules[NvRmDfsModuleId_Vde] = *pCaps;
+    return NvSuccess;
+}
+
+static NvError EmcMonitorsGetCapabilities(NvRmDfs* pDfs)
+{
+    NvError error;
+
+    NvRmModuleID ModuleId;
+    NvRmDfsModule* pCaps;
+    NvRmDfsModule EmcCaps[3] = {{{0}}};
+    NvRmModuleCapability ModuleCaps[3];
+    NvRmModuleTable *tbl;
+
+    NvRmDeviceHandle hRm = pDfs->hRm;
+
+    tbl = NvRmPrivGetModuleTable( hRm );
+
+    /*
+     * EMC module includes activity monitor for EMC clock domain. This
+     * monitor may, or may not be present on different versions of EMC 
+     */
+    EmcCaps[0].DomainMap[NvRmDfsClockId_Emc] = NV_FALSE;
+
+    EmcCaps[1].DomainMap[NvRmDfsClockId_Emc] = NV_TRUE;
+    EmcCaps[1].Init = NvRmPrivAp15EmcMonitorsInit;
+    EmcCaps[1].Deinit = NvRmPrivAp15EmcMonitorsDeinit;
+    EmcCaps[1].Start = NvRmPrivAp15EmcMonitorsStart;
+    EmcCaps[1].Read = NvRmPrivAp15EmcMonitorsRead;
+
+    EmcCaps[2].DomainMap[NvRmDfsClockId_Emc] = NV_TRUE;
+    EmcCaps[2].Init = NvRmPrivAp20EmcMonitorsInit;
+    EmcCaps[2].Deinit = NvRmPrivAp20EmcMonitorsDeinit;
+    EmcCaps[2].Start = NvRmPrivAp20EmcMonitorsStart;
+    EmcCaps[2].Read = NvRmPrivAp20EmcMonitorsRead;
+
+    ModuleCaps[0].MajorVersion = 1; // AP15 A01       
+    ModuleCaps[0].MinorVersion = 0;
+    ModuleCaps[0].EcoLevel = 0;
+    ModuleCaps[0].Capability = (void*)&EmcCaps[1];
+
+    ModuleCaps[1].MajorVersion = 1; // AP15 A02 (same caps as AP15 A01)
+    ModuleCaps[1].MinorVersion = 1;
+    ModuleCaps[1].EcoLevel = 0;
+    ModuleCaps[1].Capability = (void*)&EmcCaps[1];
+
+    ModuleCaps[2].MajorVersion = 1; // AP20 EMC
+    ModuleCaps[2].MinorVersion = 2;
+    ModuleCaps[2].EcoLevel = 0;
+    ModuleCaps[2].Capability = (void*)&EmcCaps[2];
+
+    ModuleId = NVRM_MODULE_ID(NvRmPrivModuleID_ExternalMemoryController, 0);
+    error = NvRmModuleGetCapabilities(hRm, ModuleId, ModuleCaps, 3, (void **)&pCaps);
+
+    if (error == NvSuccess)
+    {
+        if (pCaps->DomainMap[NvRmDfsClockId_Emc])
+        {       
+            pCaps->pBaseReg = (tbl->ModInst +
+                tbl->Modules[NvRmPrivModuleID_ExternalMemoryController].Index)->VirtAddr;
+        }
+    }
+    else
+    {
+        // If get capabilities failed, set "not present" cpabilities 
+        pCaps = &EmcCaps[0];
+    }
+    pDfs->Modules[NvRmDfsModuleId_Emc] = *pCaps;
+    return NvSuccess;
+}
+
+static NvError DfsGetModulesCapabilities(NvRmDfs* pDfs)
+{
+    NvError error = SystatMonitorsGetCapabilities(pDfs);
+    if (error == NvSuccess)
+    {
+        error = VdeMonitorsGetCapabilities(pDfs);
+    }
+    if (error == NvSuccess)
+    {
+        error = EmcMonitorsGetCapabilities(pDfs);
+    }
+    return error;
+}
+
+/*****************************************************************************/
+// DFS INITIALIZATION PROCEDURES
+/*****************************************************************************/
+
+static void DfsParametersInit(NvRmDfs* pDfs)
+{
+    NvU32 i;
+    NvRmModuleClockLimits HwLimitsKHz[NvRmDfsClockId_Num];
+    const NvRmModuleClockLimits* pClimits;
+
+    // TODO: ODM query for parameters initialization?
+
+    // Macro to initialize scaling algorithm parameters
+    #define INIT_PARAM(Domain, DOMAIN) \
+    do \
+    {  \
+        if ((pDfs->hRm->ChipId.Id == 0x15) || (pDfs->hRm->ChipId.Id == 0x16)) \
+        { \
+            NvRmDfsParam dp = { NVRM_DFS_PARAM_##DOMAIN##_AP15 }; \
+            pDfs->DfsParameters[NvRmDfsClockId_##Domain] = dp; \
+        } \
+        else if (pDfs->hRm->ChipId.Id == 0x20) \
+        { \
+            NvRmDfsParam dp = { NVRM_DFS_PARAM_##DOMAIN##_AP20 }; \
+            pDfs->DfsParameters[NvRmDfsClockId_##Domain] = dp; \
+        } \
+        else \
+            NV_ASSERT(!"Unsupported chip ID"); \
+    } while(0)
+
+    // Initialize scaling algorithm parameters for DFS domains
+    INIT_PARAM(Cpu, CPU);
+    INIT_PARAM(Avp, AVP);
+    INIT_PARAM(System, SYSTEM);
+    INIT_PARAM(Ahb, AHB);
+    INIT_PARAM(Apb, APB);
+    INIT_PARAM(Vpipe, VPIPE);
+    INIT_PARAM(Emc, EMC);
+
+    #undef INIT_PARAM
+
+    // Adjust EMC parameters as required for particular SDRAM type
+    if (pDfs->hRm->ChipId.Id == 0x20)
+        NvRmPrivAp20EmcParametersAdjust(pDfs);
+
+    // Update minimum frequency boundary for DFS clocks as required for
+    // download transport support
+    switch (NvRmPrivGetDownloadTransport(pDfs->hRm))
+    {
+        case NvOdmDownloadTransport_Ethernet:
+            if ((pDfs->hRm->ChipId.Id == 0x15) &&
+                (pDfs->hRm->ChipId.Major == 0x01) &&
+                (pDfs->hRm->ChipId.Minor == 0x01))
+            {
+                pDfs->DfsParameters[NvRmDfsClockId_Apb].MinKHz =
+                pDfs->DfsParameters[NvRmDfsClockId_Ahb].MinKHz =
+                    NVRM_ETHERNET_AHB_MIN_KHZ;
+                pDfs->DfsParameters[NvRmDfsClockId_Emc].MinKHz =
+                    NVRM_ETHERNET_EMC_MIN_KHZ;
+            }
+            break;
+        case NvOdmDownloadTransport_Usb:
+            pDfs->DfsParameters[NvRmDfsClockId_Apb].MinKHz =
+            pDfs->DfsParameters[NvRmDfsClockId_Ahb].MinKHz =
+            pDfs->DfsParameters[NvRmDfsClockId_Emc].MinKHz =
+                NVRM_USB_AHB_MIN_KHZ;
+            break;
+        case NvOdmDownloadTransport_Spi:
+            pDfs->DfsParameters[NvRmDfsClockId_Cpu].MinKHz = NV_MAX(
+                pDfs->DfsParameters[NvRmDfsClockId_Cpu].MinKHz,
+                NVRM_SPI_CPU_MIN_KHZ);
+            if (pDfs->hRm->ChipId.Id == 0x20)
+                pDfs->DfsParameters[NvRmDfsClockId_Apb].MinKHz =
+                    NVRM_SPI_APB_MIN_KHZ;
+            break;
+        default:
+            break;
+    }
+
+    // CPU clock H/w limits
+    pClimits = NvRmPrivGetSocClockLimits(NvRmModuleID_Cpu);
+    HwLimitsKHz[NvRmDfsClockId_Cpu] = *pClimits;
+
+    // System clock H/w limits are applied to AVP, AHB, and APB
+    pClimits = NvRmPrivGetSocClockLimits(NvRmPrivModuleID_System);
+    HwLimitsKHz[NvRmDfsClockId_System] = *pClimits;
+    HwLimitsKHz[NvRmDfsClockId_Avp] = *pClimits;
+    HwLimitsKHz[NvRmDfsClockId_Ahb] = *pClimits;
+    HwLimitsKHz[NvRmDfsClockId_Apb] = *pClimits;
+
+    // V-pipe clock H/w limits
+    pClimits = NvRmPrivGetSocClockLimits(NvRmModuleID_Vde);
+    HwLimitsKHz[NvRmDfsClockId_Vpipe] = *pClimits;
+
+    // EMC clock H/w limits (the limit table specifies EMC2x limits); on SoC
+    // PLLM0 is used as a high limit for DFS
+    pClimits =
+        NvRmPrivGetSocClockLimits(NvRmPrivModuleID_ExternalMemoryController);
+    HwLimitsKHz[NvRmDfsClockId_Emc].MaxKHz = pClimits->MaxKHz / 2;
+    HwLimitsKHz[NvRmDfsClockId_Emc].MinKHz = pClimits->MinKHz / 2;
+    if (s_Platform == ExecPlatform_Soc)
+    {
+        HwLimitsKHz[NvRmDfsClockId_Emc].MaxKHz =
+            NvRmPrivGetClockSourceFreq(NvRmClockSource_PllM0) / 2;
+    }
+
+    // Clip requested clock boundaries to h/w limits, and initialize
+    // low/high corner with minimum/maximum domain frequencies
+    for (i = 1; i < NvRmDfsClockId_Num; i++)
+    {
+        if (pDfs->DfsParameters[i].MaxKHz > HwLimitsKHz[i].MaxKHz)
+            pDfs->DfsParameters[i].MaxKHz = HwLimitsKHz[i].MaxKHz;
+        if (pDfs->DfsParameters[i].MinKHz < HwLimitsKHz[i].MinKHz)
+            pDfs->DfsParameters[i].MinKHz = HwLimitsKHz[i].MinKHz;
+        pDfs->LowCornerKHz.Domains[i] = pDfs->DfsParameters[i].MinKHz;
+        pDfs->HighCornerKHz.Domains[i] = pDfs->DfsParameters[i].MaxKHz;
+    }
+    pDfs->CpuCornersShadow.MinKHz =
+        pDfs->LowCornerKHz.Domains[NvRmDfsClockId_Cpu];
+    pDfs->CpuCornersShadow.MaxKHz =
+        pDfs->HighCornerKHz.Domains[NvRmDfsClockId_Cpu];
+
+#if NVRM_EMC_DFS_DEFAULT_DISABLED
+    pDfs->LowCornerKHz.Domains[NvRmDfsClockId_Emc] =
+        pDfs->DfsParameters[NvRmDfsClockId_Emc].MaxKHz;
+#endif
+    pDfs->CpuEnvelopeSet = NV_FALSE;
+    pDfs->EmcEnvelopeSet = NV_FALSE;
+
+    // Set initial boundaries for sampling interval
+    pDfs->SamplingWindow.MinIntervalMs = NVRM_DFS_MIN_SAMPLE_MS;
+    pDfs->SamplingWindow.MaxIntervalMs = NVRM_DFS_MAX_SAMPLE_MS;
+    if (pDfs->hRm->ChipId.Id == 0x20) // constant for AP20 (TODO: revisit)
+        pDfs->SamplingWindow.MaxIntervalMs = NVRM_DFS_MIN_SAMPLE_MS;
+
+    // Fill in maximum DFS domains frequencies shortcut
+    for (i = 1; i < NvRmDfsClockId_Num; i++)
+        pDfs->MaxKHz.Domains[i] = pDfs->DfsParameters[i].MaxKHz;
+}
+
+static void DfsSamplersInit(
+    const NvRmDfsFrequencies* pDfsKHz,
+    NvRmDfs* pDfs)
+{
+    NvU32 i, j, msec;
+    NvRmDfsSampleWindow* pSampleWindow;
+
+    /*
+     * Clear Low Power Corner indicators, initilize current
+     * and target frequencies
+     */
+    pDfs->LowCornerHit = NV_FALSE;
+    pDfs->LowCornerReport = NV_FALSE;
+    NvRmPrivUpdateDfsPauseFlag(pDfs->hRm, NV_FALSE);
+
+    pDfs->CurrentKHz = *pDfsKHz;
+    pDfs->TargetKHz = pDfs->CurrentKHz;
+
+    /*
+     * Initialize one full sampling window before DFS start. Use minimum
+     * sampling interval.
+     */
+    pSampleWindow = &pDfs->SamplingWindow;
+    msec = pSampleWindow->MinIntervalMs;
+    pSampleWindow->NextIntervalMs = msec;
+    for (j = 0; j < NVRM_DFS_MAX_SAMPLES; j++)
+    {
+        pSampleWindow->IntervalsMs[j] = msec;
+    }
+    pSampleWindow->pLastInterval = pSampleWindow->IntervalsMs;
+    pSampleWindow->SampleWindowMs = (msec << NVRM_DFS_MAX_SAMPLES_LOG2);
+    pSampleWindow->BusyCheckLastUs = 0;
+    pSampleWindow->BusyCheckDelayUs = 0;
+
+    /*
+     * Initialize domain samplers
+     */
+    for (i = 1; i < NvRmDfsClockId_Num; i++)
+    {
+        NvRmFreqKHz khz = pDfs->CurrentKHz.Domains[i];
+        NvRmDfsSampler* pSampler = &pDfs->Samplers[i];
+        NvU32 cycles = khz * msec;
+
+        // Clear busy boost
+        pDfs->BusyKHz.Domains[i] = 0;
+
+        // Store DFS Clock Id
+        pSampler->ClockId = i;
+
+        // Use modules capabilities to determine if domain monitor is present
+        for (j = 1; j < NvRmDfsModuleId_Num; j++)
+        {
+            pSampler->MonitorPresent |=
+                pDfs->Modules[j].DomainMap[i];
+        }
+
+        // Initialize sampler data assuming constant current frequency
+        // for one sampling window before the DFS start
+        for (j = 0; j < NVRM_DFS_MAX_SAMPLES; j++)
+        {
+            pSampler->Cycles[j] = cycles;
+        }
+        pSampler->pLastSample = pSampler->Cycles;
+        pSampler->TotalActiveCycles = (cycles << NVRM_DFS_MAX_SAMPLES_LOG2);
+        if (pSampler->MonitorPresent)
+        {
+            pSampler->AverageKHz = khz;
+            pSampler->BumpedAverageKHz = khz;
+        }
+        else
+        {
+            // For domain without monitor, average frequency is unspecified
+            // and low corner is used as a base for target clalculation
+            pSampler->AverageKHz = NvRmFreqUnspecified;
+            pSampler->BumpedAverageKHz = pDfs->LowCornerKHz.Domains[i];
+        }
+        pSampler->NrtSampleCounter = 0;
+        pSampler->NrtStarveBoostKHz = 0;
+        pSampler->RtStarveBoostKHz = 0;
+        pSampler->BusyPulseMode = NV_FALSE;
+    }
+}
+
+static NvError DfsHwInit(NvRmDfs* pDfs)
+{
+    NvU32 i;
+    NvError error = NvSuccess;
+
+    s_pTimerUs = NvRmPrivAp15GetTimerUsVirtAddr(pDfs->hRm);
+
+    for (i = 1; i < NvRmDfsModuleId_Num; i++)
+    {
+        if (pDfs->Modules[i].Init)
+        {
+            error = pDfs->Modules[i].Init(pDfs);
+            if (error != NvSuccess)
+            {
+                break;
+            }
+        }
+    }
+    return error;
+}
+
+static void DfsHwDeinit(NvRmDfs* pDfs)
+{
+    NvU32 i;
+
+    if (pDfs && pDfs->hRm)
+    {
+        for (i = 1; i < NvRmDfsModuleId_Num; i++)
+        {
+            if (pDfs->Modules[i].Deinit)
+            {
+                pDfs->Modules[i].Deinit(pDfs);
+            }
+        }
+    }
+}
+
+/*****************************************************************************/
+// DFS ALGORITHM IMPLEMENTATION
+/*****************************************************************************/
+
+static void
+DfsStartMonitors(
+    const NvRmDfs* pDfs,
+    const NvRmDfsFrequencies* pDfsKHz,
+    const NvU32 IntervalMs)
+{
+    NvU32 i;
+
+    for (i = 1; i < NvRmDfsModuleId_Num; i++)
+    {
+        FuncPtrModuleMonitorsStart start = pDfs->Modules[i].Start;
+        if (start)
+        {
+            start(pDfs, pDfsKHz, IntervalMs);
+        }
+    }
+}
+
+static void
+DfsReadMonitors(
+    const NvRmDfs* pDfs,
+    const NvRmDfsFrequencies* pDfsKHz,
+    NvRmDfsIdleData* pIdleData)
+{
+    NvU32 i;
+
+    for (i = 1; i < NvRmDfsModuleId_Num; i++)
+    {
+        FuncPtrModuleMonitorsRead read = pDfs->Modules[i].Read;
+        if (read)
+        {
+            read(pDfs, pDfsKHz, pIdleData);
+        }
+    }
+}
+
+static NvRmPmRequest 
+DfsGetPmRequest(
+    NvRmDeviceHandle hRmDevice,
+    NvRmDfsSampler* pCpuSampler,
+    NvRmFreqKHz* pCpuKHz)
+{
+    if (hRmDevice->ChipId.Id == 0x20)
+    {
+        return NvRmPrivAp20GetPmRequest(hRmDevice, pCpuSampler, pCpuKHz);
+    }
+    return NvRmPmRequest_None;
+}
+
+static NvBool
+DfsGetTargetFrequencies(
+    const NvRmDfsIdleData* pIdleData,
+    NvRmDfs* pDfs,
+    NvRmDfsFrequencies* pDfsKHz)
+{
+    static NvRmDfsFrequencies LastKHz = {{0}};
+
+    NvU32 i;
+    NvBool BusyCheckTime;
+    NvBool ReturnValue = NV_FALSE;
+    NvBool LowCornerHit = NV_TRUE;
+    NvU32 msec = pIdleData->CurrentIntervalMs;
+    NvU32 usec = NvRmPrivGetUs();
+
+    // Add current sample interval to sampling window; always signal to clock
+    // control thread if window wraparound; check busy hints expirtaion time
+    ReturnValue = AddSampleInterval(&pDfs->SamplingWindow, msec);
+    pDfs->SamplingWindow.SampleCnt++; 
+    BusyCheckTime = pDfs->SamplingWindow.BusyCheckDelayUs <
+        (usec - pDfs->SamplingWindow.BusyCheckLastUs);
+
+    // Update thermal throttling polling control
+    if (!NVRM_DTT_DISABLED && pDfs->ThermalThrottler.hOdmTcore)
+    {
+        if (pDfs->ThermalThrottler.TcorePolicy.UpdateIntervalUs <
+            (usec - pDfs->ThermalThrottler.TcorePolicy.TimeUs))
+        {
+            pDfs->ThermalThrottler.TcorePolicy.TimeUs = usec;
+            pDfs->ThermalThrottler.TcorePolicy.UpdateFlag = NV_TRUE;
+        }
+    }
+
+    // Update cumulative log time (including LP2 time)
+    if (s_DfsLogOn)
+    {
+        pDfs->SamplingWindow.CumulativeLogMs +=
+            (pIdleData->CurrentIntervalMs + pIdleData->Lp2TimeMs);
+        if (pIdleData->Lp2TimeMs)
+        {
+            pDfs->SamplingWindow.CumulativeLp2TimeMs += pIdleData->Lp2TimeMs;
+            pDfs->SamplingWindow.CumulativeLp2Entries++;
+        }
+    }
+    // Update LP2 indicator to synchronize DVFS state with dedicated CPU
+    // rail after LP2 exit (required if CPU rail returns to default level
+    // by PMU underneath DVFS on every LP2 exit)
+    if (pIdleData->Lp2TimeMs && pDfs->VoltageScaler.VCpuOTPOnWakeup &&
+        NvRmPrivIsCpuRailDedicated(pDfs->hRm))
+    {
+        pDfs->VoltageScaler.Lp2SyncOTPFlag = NV_TRUE;
+        pDfs->VoltageScaler.UpdateFlag = NV_TRUE;
+    }
+
+    // Determine target frequency for each DFS domain
+    for (i = 1; i < NvRmDfsClockId_Num; i++)
+    {
+        NvRmDfsSampler* pDomainSampler = &pDfs->Samplers[i];
+        NvRmDfsParam* pDomainParam = &pDfs->DfsParameters[i];
+        NvRmFreqKHz* pDomainKHz = &pDfsKHz->Domains[i];
+        NvRmFreqKHz CurrentDomainKHz = *pDomainKHz;
+        NvRmFreqKHz LowCornerDomainKHz = pDfs->LowCornerKHz.Domains[i];
+        NvRmFreqKHz HighCornerDomainKHz = pDfs->HighCornerKHz.Domains[i];
+        NvRmFreqKHz DomainBusyKHz = pDfs->BusyKHz.Domains[i]; // from dfs thread
+
+        /*
+         * Find and adjust average activity frequency over the sampling
+         * window
+         */
+        if (pDomainSampler->MonitorPresent)
+        {
+            NvU32 IdleCount = pIdleData->Readings[i];
+            NvU32 ActiveCount = msec * CurrentDomainKHz; // max if never idle
+
+            // Update cumulative number of cycles
+            if (s_DfsLogOn)
+                pDomainSampler->CumulativeLogCycles +=
+                    (ActiveCount + pIdleData->Lp2TimeMs * CurrentDomainKHz);
+
+            // Raw average = Sum(Activity Counts within sampling window)
+            // divided by Sum(Sampling Intervals within sampling window)
+            ActiveCount =
+                (ActiveCount > IdleCount) ? (ActiveCount - IdleCount) : (0);
+#if NVRM_DFS_STALL_AVERAGE_IN_BUSY_PULSE
+            if (!pDomainSampler->BusyPulseMode) 
+#endif
+            {
+                AddActivitySample(pDomainSampler, ActiveCount);
+            }
+
+            pDomainSampler->AverageKHz = (NvU32)NvDiv64(pDomainSampler->TotalActiveCycles,
+                    pDfs->SamplingWindow.SampleWindowMs);
+
+            // Check non real-time starvation
+            if ((IdleCount >= (1 + (ActiveCount >> pDomainParam->RelAdjustBits))) &&
+                (pDomainSampler->BumpedAverageKHz >= pDomainSampler->AverageKHz))
+            {
+                pDomainSampler->NrtSampleCounter = 0;
+                if (pDomainSampler->NrtStarveBoostKHz != 0)
+                {
+                    // Domain is not starving, previously added boost has not been
+                    // removed, yet - decrease starvation boost proportionally
+                    pDomainSampler->NrtStarveBoostKHz = (pDomainSampler->NrtStarveBoostKHz *
+                     ((0x1 << BOOST_FRACTION_BITS) - pDomainParam->NrtStarveParam.BoostDecKoef))
+                      >> BOOST_FRACTION_BITS;
+
+                    if (pDomainSampler->NrtStarveBoostKHz <
+                        pDomainParam->NrtStarveParam.BoostStepKHz)
+                        pDomainSampler->NrtStarveBoostKHz = 0;  // cut tail
+                }
+            }
+            else if (pDomainSampler->NrtSampleCounter < pDomainParam->MinNrtSamples)
+            {
+                pDomainSampler->NrtSampleCounter++;
+            }
+            else
+            {
+                // Domain is starving - increase starvation boost
+                // (proportionally plus a fixed step)
+                pDomainSampler->NrtStarveBoostKHz = ((pDomainSampler->NrtStarveBoostKHz *
+                 ((0x1 << BOOST_FRACTION_BITS) + pDomainParam->NrtStarveParam.BoostIncKoef))
+                  >> BOOST_FRACTION_BITS) + pDomainParam->NrtStarveParam.BoostStepKHz;
+
+                // Make sure the boost value is within domain limits
+                if (pDomainSampler->NrtStarveBoostKHz > pDomainParam->MaxKHz)
+                    pDomainSampler->NrtStarveBoostKHz = pDomainParam->MaxKHz;
+            }
+
+            // Average frequency change is recognized by DFS only if it exceeds
+            // tolerance band. 
+            if ((pDomainSampler->AverageKHz + pDomainParam->LowerBandKHz) <
+                pDomainSampler->BumpedAverageKHz)
+            {
+                pDomainSampler->BumpedAverageKHz =
+                    pDomainSampler->AverageKHz + pDomainParam->LowerBandKHz;
+            }
+            else if (pDomainSampler->AverageKHz > 
+                (pDomainSampler->BumpedAverageKHz + pDomainParam->UpperBandKHz))
+            {
+                pDomainSampler->BumpedAverageKHz =
+                    pDomainSampler->AverageKHz - pDomainParam->UpperBandKHz;
+            }
+
+            // Adjust average frequency up, to probe non real-time starvation
+            pDomainSampler->BumpedAverageKHz +=
+                (pDomainSampler->BumpedAverageKHz >> pDomainParam->RelAdjustBits);
+        }
+        else
+        {
+            // For domain without monitor average frequency is unspecified
+            // and low corner is used as a base for target clalculation
+            pDomainSampler->AverageKHz = NvRmFreqUnspecified;
+            pDomainSampler->BumpedAverageKHz = LowCornerDomainKHz;
+        }
+
+        /*
+         * Check real time starvation
+         */
+        if(NvRmPrivDfsIsStarving(i))
+        {
+            // Domain is starving - increase starvation boost (proportionally
+            // plus a fixed step)
+            pDomainSampler->RtStarveBoostKHz = ((pDomainSampler->RtStarveBoostKHz *
+             ((0x1 << BOOST_FRACTION_BITS) + pDomainParam->RtStarveParam.BoostIncKoef))
+              >> BOOST_FRACTION_BITS) + pDomainParam->RtStarveParam.BoostStepKHz;
+
+            // Make sure the boost value is within domain limits
+            if (pDomainSampler->RtStarveBoostKHz > pDomainParam->MaxKHz)
+                pDomainSampler->RtStarveBoostKHz = pDomainParam->MaxKHz;
+        }
+        else if (pDomainSampler->RtStarveBoostKHz != 0)
+        {
+            // Domain is not starving, previously added boost has not been
+            // removed, yet - decrease starvation boost proportionally
+            pDomainSampler->RtStarveBoostKHz = (pDomainSampler->RtStarveBoostKHz *
+             ((0x1 << BOOST_FRACTION_BITS) - pDomainParam->RtStarveParam.BoostDecKoef))
+              >> BOOST_FRACTION_BITS;
+        }
+
+        /*
+         * Combine average, starvation and busy demands into target frequency,
+         * and clip it to the domain limits. Check low power corner hit. Set
+         * return value if clock update is necessary.
+         */
+        *pDomainKHz = NV_MAX(pDomainSampler->BumpedAverageKHz,
+                             LowCornerDomainKHz);
+        if (pDomainSampler->RtStarveBoostKHz >= pDomainSampler->NrtStarveBoostKHz)
+        {
+            *pDomainKHz += pDomainSampler->RtStarveBoostKHz;
+        }
+        else
+        {
+            *pDomainKHz += pDomainSampler->NrtStarveBoostKHz;
+        }
+
+        if ((*pDomainKHz) < DomainBusyKHz)
+        {
+            (*pDomainKHz) = DomainBusyKHz;
+        }
+        if ((*pDomainKHz) > HighCornerDomainKHz)
+        {
+            *pDomainKHz = HighCornerDomainKHz;
+        }
+
+        /*
+         * Determine if low corner is hit in this domain - clear hit indicator
+         * if new target domain frequency is above low limit (with hysteresis)
+         * For platform with dedicated CPU partition do not include activity
+         * margin when there is no busy or starvation requirements
+         */
+        if (NvRmPrivIsCpuRailDedicated(pDfs->hRm) &&
+            (DomainBusyKHz <= LowCornerDomainKHz) &&
+            ((*pDomainKHz) == pDomainSampler->BumpedAverageKHz))
+        {
+            // Multiplying threshold has the same effect as dividing target
+            // to reduce margin
+            LowCornerDomainKHz +=
+                (LowCornerDomainKHz >> pDomainParam->RelAdjustBits);
+        }
+        if ( ((*pDomainKHz) > 
+              (LowCornerDomainKHz + pDomainParam->NrtStarveParam.BoostStepKHz))
+             || (((*pDomainKHz) > LowCornerDomainKHz) && (!pDfs->LowCornerHit))
+            )
+        {
+            LowCornerHit = NV_FALSE;
+        }
+
+        /*
+         * Update PM request. Set return value if CPU power state change
+         * is requested. 
+         */
+        if (i == NvRmDfsClockId_Cpu)
+        {
+            NvRmPmRequest r =
+                DfsGetPmRequest(pDfs->hRm, pDomainSampler, pDomainKHz);
+            if (r != NvRmPmRequest_None)
+            {
+                pDfs->PmRequest = r;
+                ReturnValue = NV_TRUE;
+            }
+        }
+
+        // Set return value, if the new target is outside the tolerance band
+        // around the last recorded target, or if domain is busy
+        ReturnValue = ReturnValue || (DomainBusyKHz && BusyCheckTime) ||
+            (((*pDomainKHz) + pDomainParam->LowerBandKHz) <= LastKHz.Domains[i]) ||
+            ((*pDomainKHz) >= (LastKHz.Domains[i] + pDomainParam->UpperBandKHz));
+    }
+    // Update low corner hit status if necessary
+    if (pDfs->LowCornerHit != LowCornerHit)
+    {
+        pDfs->LowCornerHit = LowCornerHit;
+        pDfs->LowCornerReport = NV_TRUE;
+        ReturnValue = NV_TRUE;
+    }
+    // Update last recorded target if clock thread is to be signaled
+    if (ReturnValue)
+    {
+        LastKHz = *pDfsKHz;
+    }
+    return ReturnValue;
+}
+
+static NvBool
+AddSampleInterval(
+    NvRmDfsSampleWindow* pSampleWindow,
+    NvU32 IntervalMs)
+{
+    /*
+     * Add current sampling interval to the sampling window (i.e., replace the
+     * first/"oldest" interval with the new one and update window size). 
+     */ 
+    NvBool WrapAround = NV_FALSE;
+
+    NvU32* pFirst = pSampleWindow->pLastInterval + 1; 
+    if (pFirst >= &pSampleWindow->IntervalsMs[
+        NV_ARRAY_SIZE(pSampleWindow->IntervalsMs)])
+    {
+        pFirst = pSampleWindow->IntervalsMs;
+        WrapAround = NV_TRUE;
+    }
+    pSampleWindow->pLastInterval = pFirst;
+
+    pSampleWindow->SampleWindowMs += IntervalMs;
+    pSampleWindow->SampleWindowMs -= (*pFirst);
+    *pFirst = IntervalMs;
+
+    return WrapAround;
+}
+
+static void
+AddActivitySample(
+    NvRmDfsSampler* pDomainSampler,
+    NvU32 ActiveCount)
+{
+    /*
+     * Add new activity sample to the cicular buffer(i.e., replace the
+     * first/"oldest" sample with the new one) and update total cycle count 
+     */ 
+    NvU32* pFirst = pDomainSampler->pLastSample + 1;
+    if (pFirst >= &pDomainSampler->Cycles[
+        NV_ARRAY_SIZE(pDomainSampler->Cycles)])
+    {
+        pFirst = pDomainSampler->Cycles;
+    }
+    pDomainSampler->pLastSample = pFirst;
+
+    pDomainSampler->TotalActiveCycles += ActiveCount;
+    pDomainSampler->TotalActiveCycles -= (*pFirst);
+    *pFirst = ActiveCount;
+}
+
+static void DfsIsr(void* args)
+{
+    NvRmDfs* pDfs = (NvRmDfs*)args;
+    NvBool ClockChange = NV_FALSE;
+    NvRmDfsFrequencies DfsKHz;
+    NvRmDfsIdleData IdleData;
+    NvU32 msec;
+
+    DfsProfileStart(pDfs, NvRmDfsProfileId_Isr);
+    NvOsIntrMutexLock(pDfs->hIntrMutex);
+    DfsProfileStart(pDfs, NvRmDfsProfileId_Algorithm);
+
+    // Input to DFS algorithm from clock control thread: current frequencies
+    DfsKHz = pDfs->CurrentKHz;
+
+    // Adjust next sampling interval based on CPU domain frequency; keep it
+    // minimum if NRT threshold was crossed during the last sample
+    msec = pDfs->SamplingWindow.MinIntervalMs;
+    if (pDfs->Samplers[NvRmDfsClockId_Cpu].NrtSampleCounter == 0)
+    {
+        if (DfsKHz.Domains[NvRmDfsClockId_Cpu] <
+            (pDfs->DfsParameters[NvRmDfsClockId_Cpu].MinKHz +
+             pDfs->DfsParameters[NvRmDfsClockId_Cpu].UpperBandKHz))
+            msec = pDfs->SamplingWindow.MaxIntervalMs;
+    }
+    pDfs->SamplingWindow.NextIntervalMs = msec;
+
+    // Read idle counts from  monitors, which clears DFS interrupt
+    DfsReadMonitors(pDfs, &DfsKHz, &IdleData);
+
+    if (pDfs->DfsRunState > NvRmDfsRunState_Stopped)
+    {
+        // If DFS is running re-start monitors, execute DFS algorithm, and 
+        // determine new target frequencies for the clock control thread
+        DfsStartMonitors(pDfs, &DfsKHz, msec);
+        ClockChange = DfsGetTargetFrequencies(&IdleData, pDfs, &DfsKHz);
+        pDfs->TargetKHz = DfsKHz;
+        ClockChange = ClockChange || pDfs->VoltageScaler.UpdateFlag ||
+            pDfs->ThermalThrottler.TcorePolicy.UpdateFlag;
+    }
+    DfsProfileSample(pDfs, NvRmDfsProfileId_Algorithm);
+    DfsLogEnter(pDfs, IdleData.Lp2TimeMs);
+    NvOsIntrMutexUnlock(pDfs->hIntrMutex);
+
+    // Signal clock control thread if clocks should be changed
+    if (ClockChange)
+    {
+        NvOsSemaphoreSignal(pDfs->hSemaphore);
+    }
+    DfsProfileSample(pDfs, NvRmDfsProfileId_Isr);
+
+    NvRmInterruptDone(pDfs->DfsInterruptHandle);
+}
+
+/*****************************************************************************/
+// DFS CLOCK CONTROL THREAD
+/*****************************************************************************/
+
+static NvRmPmRequest DfsThread(NvRmDfs* pDfs)
+{
+    static NvRmDfsFrequencies LastKHz = {{0}};
+
+    NvRmPowerEvent PowerEvent;
+    NvRmDfsRunState DfsRunState;
+    NvRmDfsFrequencies DfsKHz, HighKHz;
+    NvBool LowCornerHit, LowCornerReport, NeedClockUpdate;
+    NvU32 i, BusyCheckDelayMs;
+
+    NvRmPmRequest PmRequest = NvRmPmRequest_None;
+
+    // Thread has been initialized
+    pDfs->InitializedThread = NV_TRUE;
+
+    // CLOCK CONTROL EXECUTION LOOP //
+    /********************************/
+    {
+        NvOsSemaphoreWait(pDfs->hSemaphore);
+        if (pDfs->AbortThread)
+        {
+            pDfs->AbortThread = NV_FALSE;
+            return NvRmPmRequest_ExitFlag;
+        }
+        DfsProfileStart(pDfs, NvRmDfsProfileId_Control);
+
+        // Save traget frequency and DFS state variables, updated by ISR
+        NvOsIntrMutexLock(pDfs->hIntrMutex);
+        DfsKHz = pDfs->TargetKHz;
+        HighKHz = pDfs->HighCornerKHz;
+        DfsRunState = pDfs->DfsRunState;
+        LowCornerHit = pDfs->LowCornerHit;
+        LowCornerReport = pDfs->LowCornerReport;
+        pDfs->LowCornerReport = NV_FALSE;
+        PmRequest = pDfs->PmRequest;
+        pDfs->PmRequest = NvRmPmRequest_None;
+        NvOsIntrMutexUnlock(pDfs->hIntrMutex);
+
+        /*
+         * On exit from low power state re-initialize DFS h/w, samplers, and
+         * start monitors provided DFS is running. If DFS is stopped just get
+         * DFS h/w ready. 
+         */
+        NV_ASSERT_SUCCESS(NvRmPowerGetEvent(
+            pDfs->hRm, pDfs->PowerClientId, &PowerEvent));
+        if (PowerEvent != NvRmPowerEvent_NoEvent)
+        {
+            // Full h/w re-initialization after LP0
+            if (PowerEvent == NvRmPowerEvent_WakeLP0)
+            {
+                DfsHwDeinit(pDfs);
+                NV_ASSERT_SUCCESS(DfsHwInit(pDfs));
+            }
+            // Re-initialize samplers if DVFS was running, but stopped on
+            // entry to LPx; keep sampling history, if DVFS was not stopped;
+            // restart monitors in either case
+            NvRmPrivLockSharedPll();
+            if (pDfs->DfsLPxSavedState > NvRmDfsRunState_Stopped)
+            {
+                DfsClockFreqGet(pDfs->hRm, &DfsKHz);
+
+                NvOsIntrMutexLock(pDfs->hIntrMutex);
+                if (pDfs->DfsRunState <= NvRmDfsRunState_Stopped)
+                {
+                    pDfs->DfsRunState = pDfs->DfsLPxSavedState;
+                    DfsSamplersInit(&DfsKHz, pDfs);
+                }
+                NV_ASSERT(pDfs->DfsRunState == pDfs->DfsLPxSavedState);
+                pDfs->CurrentKHz = DfsKHz;
+                DfsStartMonitors(
+                    pDfs, &DfsKHz, pDfs->SamplingWindow.MinIntervalMs);
+                NvOsIntrMutexUnlock(pDfs->hIntrMutex);
+            }
+            NvRmPrivDvsRun();   // enable v-scaling even if DFS is stopped
+            NvRmPrivUnlockSharedPll();
+            return PmRequest;
+        }
+
+        /*
+         * Advance busy hint state machine if DFS thread has been signaled by
+         * synchronous busy hint.
+         */
+        if (pDfs->BusySyncState == NvRmDfsBusySyncState_Signal)
+        {
+            pDfs->BusySyncState = NvRmDfsBusySyncState_Execute;
+            pDfs->VoltageScaler.UpdateFlag = NV_TRUE;
+        }
+
+        /*
+         * When DFS is running evaluate busy boost and low corner status;
+         * check if new target frequencies are significantly different from
+         * the previously targeted.
+         */
+        if (DfsRunState > NvRmDfsRunState_Stopped)
+        {
+            NeedClockUpdate = NV_FALSE;
+            BusyCheckDelayMs = NVRM_DFS_BUSY_PURGE_MS;
+            
+            for (i = 1; i < NvRmDfsClockId_Num; i++)
+            {
+                NvRmFreqKHz NewBusyKHz;
+                NvBool NewPulseMode;
+                NvU32 delay;
+                NvRmFreqKHz OldBusyKHz = pDfs->BusyKHz.Domains[i];
+                NvBool OldBusyPulseMode = pDfs->Samplers[i].BusyPulseMode;
+                NvRmPrivDfsGetBusyHint(i, &NewBusyKHz, &NewPulseMode, &delay);
+
+                if ((NewBusyKHz != 0) || (OldBusyKHz != 0))
+                {
+                    // When busy boost decreasing re-init average to the
+                    // boosted level
+                    if (NewBusyKHz < OldBusyKHz)
+                    {
+                        if (!OldBusyPulseMode)
+                        {
+                            NvU32 AverageKHz = OldBusyKHz - (OldBusyKHz / (1 +
+                                (0x1 << pDfs->DfsParameters[i].RelAdjustBits)));
+                            NvOsIntrMutexLock(pDfs->hIntrMutex);
+                            DfsSetAverageUp(i, AverageKHz, pDfs);
+                            NvOsIntrMutexUnlock(pDfs->hIntrMutex);
+                        }
+                        // Make sure new frequency to be set is above max busy
+                        // and update DFS object
+                        if (DfsKHz.Domains[i] < OldBusyKHz)
+                        {
+                            DfsKHz.Domains[i] = OldBusyKHz;
+                        }
+                    }
+                    else
+                    {
+                        // Make sure new frequency to be set is above max busy
+                        // and update DFS object
+                        if (DfsKHz.Domains[i] < NewBusyKHz)
+                        {
+                            DfsKHz.Domains[i] = NewBusyKHz;
+                        }
+                    }
+                    // Clip new dfs target to high domain corner
+                    if (DfsKHz.Domains[i] > HighKHz.Domains[i])
+                    {
+                        DfsKHz.Domains[i] = HighKHz.Domains[i];
+                    }
+                    pDfs->BusyKHz.Domains[i] = NewBusyKHz;
+                    pDfs->Samplers[i].BusyPulseMode = NewPulseMode;
+                    if (BusyCheckDelayMs > delay)
+                        BusyCheckDelayMs = delay;   // Min delay to next check
+                }
+                // Compare new domain target with the previous one - need clock
+                // update if they differ significantly
+                NeedClockUpdate = NeedClockUpdate ||
+                    ((DfsKHz.Domains[i] + pDfs->DfsParameters[i].LowerBandKHz) <= LastKHz.Domains[i]) ||
+                    (DfsKHz.Domains[i] >= (LastKHz.Domains[i] + pDfs->DfsParameters[i].UpperBandKHz));
+            }
+            // Make sure busy hints will be checked in time
+            pDfs->SamplingWindow.BusyCheckLastUs = NvRmPrivGetUs();
+            pDfs->SamplingWindow.BusyCheckDelayUs = BusyCheckDelayMs * 1000;
+
+            // Low corner report
+            if (LowCornerReport)
+            {
+                NVRM_DFS_PRINTF(("DFS got %s low corner\n",
+                                 (LowCornerHit ? "into" : "out of")));
+                NvRmPrivUpdateDfsPauseFlag(pDfs->hRm, LowCornerHit);
+            }
+        }
+        else
+        {
+            // DFS is stopped - thread is signaled by API, always update clock 
+            NeedClockUpdate = NV_TRUE;
+        }
+
+        // Configure DFS clocks and update current frequencies if necessary
+        // (do not touch clocks and voltage if DVS is stopped)
+        if (NeedClockUpdate || pDfs->VoltageScaler.UpdateFlag ||
+            pDfs->ThermalThrottler.TcorePolicy.UpdateFlag)
+        {
+            NvRmPrivLockSharedPll();
+            if (!pDfs->VoltageScaler.StopFlag)
+            {
+                // Check temperature and throttle DFS clocks if necessry. Make
+                // sure V/F scaling is running while throttling is in progress.
+                pDfs->VoltageScaler.UpdateFlag =
+                    DttClockUpdate(pDfs, &pDfs->ThermalThrottler, &DfsKHz);
+                LastKHz = DfsKHz;
+                for (;;)
+                {
+                    if (DfsClockConfigure(pDfs->hRm, &pDfs->MaxKHz, &DfsKHz))
+                        break;
+                    DfsKHz = LastKHz;
+                }
+
+                NvOsIntrMutexLock(pDfs->hIntrMutex);
+                pDfs->CurrentKHz = DfsKHz;
+                NvOsIntrMutexUnlock(pDfs->hIntrMutex);
+            }
+            NvRmPrivUnlockSharedPll();
+
+            // Complete synchronous busy hint processing. 
+            if (pDfs->BusySyncState == NvRmDfsBusySyncState_Execute)
+            {
+                pDfs->BusySyncState = NvRmDfsBusySyncState_Idle;
+                NvOsSemaphoreSignal(pDfs->hSyncBusySemaphore);
+            }
+        }
+        DfsProfileSample(pDfs, NvRmDfsProfileId_Control);
+    }
+    if (PmRequest != NvRmPmRequest_None)
+    {
+        NVRM_DFS_PRINTF(("PM request: 0x%x\n", PmRequest));
+    }
+    return PmRequest;
+}
+
+static void DfsThreadTerminate(NvRmDfs* pDfs)
+{
+    /*
+     * Request thread abort, signal semaphore to make sure the thread is
+     * awaken and wait for its self-termination. Do nothing if invalid DFS
+     * structure
+     */
+    if (pDfs)
+    {
+        if (pDfs->hSemaphore && pDfs->InitializedThread)
+        {
+            pDfs->AbortThread = NV_TRUE;
+            NvOsSemaphoreSignal(pDfs->hSemaphore);
+            for (;;)
+            {
+                if (!pDfs->AbortThread)
+                {
+                    break;
+                }
+                NvOsSleepMS(10);
+            }
+        }
+    }
+}
+
+static void
+DfsSetAverageUp(
+    NvRmDfsClockId ClockId,
+    NvRmFreqKHz AverageKHz,
+    NvRmDfs* pDfs)
+{
+    NvRmDfsSampler* pDomainSampler = &pDfs->Samplers[ClockId];
+
+    // Update monitored domain average frequency up
+    if ((pDomainSampler->MonitorPresent) &&
+        (pDomainSampler->AverageKHz < AverageKHz))
+    {
+        NvU32 cycles, j;
+        NvU64 NewTotalCycles =
+            (NvU64)AverageKHz * pDfs->SamplingWindow.SampleWindowMs;
+        cycles = (NvU32)(NewTotalCycles >> NVRM_DFS_MAX_SAMPLES_LOG2);
+        for (j = 0; j < NV_ARRAY_SIZE(pDomainSampler->Cycles); j++)
+        {
+            pDomainSampler->Cycles[j] = cycles;
+        }
+        pDomainSampler->TotalActiveCycles = NewTotalCycles;
+        pDomainSampler->AverageKHz = AverageKHz;
+    }
+}
+
+static void
+DfsClockFreqGet(
+    NvRmDeviceHandle hRmDevice,
+    NvRmDfsFrequencies* pDfsKHz)
+{
+    NvU32 i;
+ 
+    switch (s_Platform)
+    {
+        case ExecPlatform_Soc:
+            if ((hRmDevice->ChipId.Id == 0x15) || (hRmDevice->ChipId.Id == 0x16))
+                NvRmPrivAp15DfsClockFreqGet(hRmDevice, pDfsKHz);
+            else if (hRmDevice->ChipId.Id == 0x20)
+                NvRmPrivAp20DfsClockFreqGet(hRmDevice, pDfsKHz);
+            else
+                NV_ASSERT(!"Unsupported chip ID");
+            break;
+
+        case ExecPlatform_Fpga:
+            for (i = 1; i < NvRmDfsClockId_Num; i++)
+            {
+                // Set fixed FPGA frequency (default: AP15 FPGA)
+                if (hRmDevice->ChipId.Id == 0x20)
+                    pDfsKHz->Domains[i] = AP20_FPGA_FREQ;
+                else
+                    pDfsKHz->Domains[i] = AP15_FPGA_FREQ;
+            }
+            break;
+
+        default:
+            NV_ASSERT(!"Not supported execution platform for DFS");
+    }
+}
+
+static NvBool
+DfsClockConfigure(
+    NvRmDeviceHandle hRmDevice,
+    const NvRmDfsFrequencies* pMaxKHz,
+    NvRmDfsFrequencies* pDfsKHz)
+{
+    NvU32 i;
+
+    switch (s_Platform)
+    {
+        case ExecPlatform_Soc:
+            if ((hRmDevice->ChipId.Id == 0x15) || (hRmDevice->ChipId.Id == 0x16))
+                return NvRmPrivAp15DfsClockConfigure(
+                    hRmDevice, pMaxKHz, pDfsKHz);
+            else if (hRmDevice->ChipId.Id == 0x20)
+                return NvRmPrivAp20DfsClockConfigure(
+                    hRmDevice, pMaxKHz, pDfsKHz);
+            else
+                NV_ASSERT(!"Unsupported chip ID");
+            break;
+
+        case ExecPlatform_Fpga:
+            for (i = 1; i < NvRmDfsClockId_Num; i++)
+            {
+                // Set fixed FPGA frequency (default: AP15 FPGA)
+                if (hRmDevice->ChipId.Id == 0x20)
+                    pDfsKHz->Domains[i] = AP20_FPGA_FREQ;
+                else
+                    pDfsKHz->Domains[i] = AP15_FPGA_FREQ;
+            }
+            break;
+        default:
+            NV_ASSERT(!"Not supported execution platform for DFS");
+    }
+    return NV_TRUE; // configuration completed
+}
+
+static void
+DfsClipCpuEmcHighLimits(
+    NvRmDeviceHandle hRmDevice,
+    NvRmFreqKHz* pCpuHighKHz,
+    NvRmFreqKHz* pEmcHighKHz)
+{
+    if ((hRmDevice->ChipId.Id == 0x15) || (hRmDevice->ChipId.Id == 0x16))
+        NvRmPrivAp15ClipCpuEmcHighLimits(hRmDevice, pCpuHighKHz, pEmcHighKHz);
+    else if (hRmDevice->ChipId.Id == 0x20)
+        NvRmPrivAp20ClipCpuEmcHighLimits(hRmDevice, pCpuHighKHz, pEmcHighKHz);
+    else
+        NV_ASSERT(!"Unsupported chip ID");
+}
+
+/*****************************************************************************/
+
+static void
+DttPolicyUpdate(
+    NvRmDeviceHandle hRm,
+    NvS32 TemperatureC,
+    NvRmDtt* pDtt)
+{
+    if (hRm->ChipId.Id == 0x20)
+    {
+        NvRmPrivAp20DttPolicyUpdate(hRm, TemperatureC, pDtt);
+        NV_ASSERT(pDtt->TcorePolicy.LowLimit !=
+                  ODM_TMON_PARAMETER_UNSPECIFIED);
+        NV_ASSERT(pDtt->TcorePolicy.HighLimit !=
+                  ODM_TMON_PARAMETER_UNSPECIFIED);
+    }
+    else
+    {
+        // No thermal policy (= do nothing) for this SoC
+        pDtt->TcorePolicy.LowLimit = ODM_TMON_PARAMETER_UNSPECIFIED;
+        pDtt->TcorePolicy.HighLimit = ODM_TMON_PARAMETER_UNSPECIFIED;
+        pDtt->TcorePolicy.UpdateIntervalUs = NV_WAIT_INFINITE;
+        pDtt->TcorePolicy.PolicyRange = 0;
+    }
+}
+
+static NvBool
+DttClockUpdate(
+    const NvRmDfs* pDfs,
+    NvRmDtt* pDtt,
+    NvRmDfsFrequencies* pDfsKHz)
+{
+    NvS32 TemperatureC;
+    NvS32 LowLimit, HighLimit;
+    NvU32 OldRange;
+    NvRmTzonePolicy Policy;
+
+    // Check if thermal throttling is supported
+    if (NVRM_DTT_DISABLED || (!pDtt->hOdmTcore))
+        return NV_FALSE; 
+
+    if (pDtt->TcorePolicy.UpdateFlag)
+    {
+        // Register TMON interrupt, if it is supported by device, and chip
+        // policy, but has not been registered yet. Set initial temperature
+        // limits according to chip specific policy.
+        if (pDtt->UseIntr && !pDtt->hOdmTcoreIntr &&
+            NvOdmTmonTemperatureGet(pDtt->hOdmTcore, &TemperatureC))
+        {
+            DttPolicyUpdate(pDfs->hRm, TemperatureC, pDtt);
+            DttRangeReport(TemperatureC, pDtt);
+            LowLimit = pDtt->TcorePolicy.LowLimit;
+            HighLimit = pDtt->TcorePolicy.HighLimit;
+
+            if ((LowLimit != ODM_TMON_PARAMETER_UNSPECIFIED) &&
+                (HighLimit != ODM_TMON_PARAMETER_UNSPECIFIED))
+            {
+                if(NvOdmTmonParameterConfig(pDtt->hOdmTcore,
+                    NvOdmTmonConfigParam_IntrLimitLow, &LowLimit) &&
+                   NvOdmTmonParameterConfig(pDtt->hOdmTcore,
+                    NvOdmTmonConfigParam_IntrLimitHigh, &HighLimit))
+                {
+                    pDtt->hOdmTcoreIntr = NvOdmTmonIntrRegister(
+                        pDtt->hOdmTcore, DttIntrCallback, (void*)pDfs);
+                }
+            }
+            if (!pDtt->hOdmTcoreIntr)
+                pDtt->UseIntr = NV_FALSE; // registration failed - use polling
+        }
+
+        // Update temperature monitoring policy
+        OldRange = pDtt->TcorePolicy.PolicyRange;
+        if (!pDtt->UseIntr &&
+            NvOdmTmonTemperatureGet(pDtt->hOdmTcore, &TemperatureC))
+        {
+            NvOsIntrMutexLock(pDfs->hIntrMutex);
+            DttPolicyUpdate(pDfs->hRm, TemperatureC, pDtt);
+            Policy = pDtt->TcorePolicy;
+        }
+        else
+        {
+            NvOsIntrMutexLock(pDfs->hIntrMutex);
+            Policy = pDtt->TcorePolicy;
+            TemperatureC = pDtt->CoreTemperatureC;
+        }
+        if (pDfs->DfsRunState > NvRmDfsRunState_Stopped)
+        {
+            pDtt->TcorePolicy.UpdateFlag = NV_FALSE;
+        }
+        NvOsIntrMutexUnlock(pDfs->hIntrMutex);
+
+        // Report range change
+        if (!pDtt->UseIntr && (OldRange != pDtt->TcorePolicy.PolicyRange))
+        {
+            DttRangeReport(TemperatureC, pDtt);
+        }
+    }
+    else
+    {
+        NvOsIntrMutexLock(pDfs->hIntrMutex);
+        Policy = pDtt->TcorePolicy;
+        TemperatureC = pDtt->CoreTemperatureC;
+        NvOsIntrMutexUnlock(pDfs->hIntrMutex);
+    }
+
+    // Throttle clock frequencies, if necessary
+    if (pDfs->hRm->ChipId.Id == 0x20)
+        return NvRmPrivAp20DttClockUpdate(
+            pDfs->hRm, TemperatureC, &Policy, &pDfs->CurrentKHz, pDfsKHz);
+    else
+        return NV_FALSE;    // No throttling policy for this chip ID
+}
+
+static void DttIntrCallback(void* args)
+{
+    NvS32 TemperatureC = 0;
+    NvS32 LowLimit = ODM_TMON_PARAMETER_UNSPECIFIED;
+    NvS32 HighLimit = ODM_TMON_PARAMETER_UNSPECIFIED;
+    NvRmDfs* pDfs = (NvRmDfs*)args;
+    NvRmDtt* pDtt = &pDfs->ThermalThrottler;
+
+    if (NvOdmTmonTemperatureGet(pDtt->hOdmTcore, &TemperatureC))
+    {
+        NvOsIntrMutexLock(pDfs->hIntrMutex);
+        DttPolicyUpdate(pDfs->hRm, TemperatureC, pDtt);
+        LowLimit = pDtt->TcorePolicy.LowLimit;
+        HighLimit = pDtt->TcorePolicy.HighLimit;
+        pDtt->TcorePolicy.UpdateFlag = NV_TRUE;
+        NvOsIntrMutexUnlock(pDfs->hIntrMutex);
+
+        // Clear interrupt condition by setting new limits "around" temperature
+        NV_ASSERT(LowLimit != ODM_TMON_PARAMETER_UNSPECIFIED);
+        NV_ASSERT(HighLimit != ODM_TMON_PARAMETER_UNSPECIFIED);
+        (void)NvOdmTmonParameterConfig(pDtt->hOdmTcore,
+            NvOdmTmonConfigParam_IntrLimitLow, &LowLimit);
+        (void)NvOdmTmonParameterConfig(pDtt->hOdmTcore,
+            NvOdmTmonConfigParam_IntrLimitHigh, &HighLimit);
+        DttRangeReport(TemperatureC, pDtt);
+    }
+}
+
+/*****************************************************************************/
+// DFS PRIVATE INTERFACES
+/*****************************************************************************/
+
+NvError NvRmPrivDfsInit(NvRmDeviceHandle hRmDeviceHandle)
+{
+    NvError error;
+    NvRmDfsFrequencies DfsKHz;
+    NvRmDfs* pDfs = &s_Dfs;
+
+    NV_ASSERT(hRmDeviceHandle);
+    DfsHintsPrintInit();
+
+    NvOsMemset(pDfs, 0, sizeof(NvRmDfs));
+    pDfs->hRm = hRmDeviceHandle;
+    s_Platform = NvRmPrivGetExecPlatform(hRmDeviceHandle);
+    s_DfsLogOn = NV_FALSE;
+
+    /*
+     * Set DFS IRQ invalid to avoid accidental deregeistration of somebody's
+     * else IRQ in case of DFS initialization error. Clear DFS clock control
+     * execution thread state variables
+     */
+    pDfs->IrqNumber = NVRM_IRQ_INVALID;
+    pDfs->InitializedThread = NV_FALSE;
+    pDfs->AbortThread = NV_FALSE;
+    pDfs->BusySyncState = NvRmDfsBusySyncState_Idle;
+    pDfs->PmRequest = NvRmPmRequest_None;
+
+    // DFS interrupt handler mutex
+    error = NvOsIntrMutexCreate(&pDfs->hIntrMutex);
+    if (error != NvSuccess)
+    {
+        goto failed;
+    }
+
+    // DFS algorithm parameters and clock limits
+    DfsParametersInit(pDfs);
+
+    /*
+     * DFS is always disabled in QT and Sim execution environments,
+     * when DFS testing is disabled. The initial DFS state for AP15 SoC and
+     * FPGA is specified by the respective macros.
+     */
+    pDfs->DfsRunState = NvRmDfsRunState_Disabled;
+    switch (s_Platform)
+    {
+        case ExecPlatform_Soc:
+            if ((pDfs->hRm->ChipId.Id == 0x15) || (pDfs->hRm->ChipId.Id == 0x16))
+                pDfs->DfsRunState = NVRM_AP15_SOC_INITIAL_DFS_STATE;
+            else if (pDfs->hRm->ChipId.Id == 0x20)
+                pDfs->DfsRunState = NVRM_AP20_SOC_INITIAL_DFS_STATE;
+            break;
+        case ExecPlatform_Fpga:
+            pDfs->DfsRunState = NVRM_FPGA_INITIAL_DFS_STATE;
+            break;
+        default:
+            break;
+    }
+    pDfs->DfsLPxSavedState = pDfs->DfsRunState;
+    if (pDfs->DfsRunState == NvRmDfsRunState_Disabled)
+    {
+        // If DFS disabled abort initialization and exit
+        return NvSuccess;
+    }
+
+    // DFS signaling semaphore
+    error = NvOsSemaphoreCreate(&pDfs->hSemaphore, 0);
+    if (error != NvSuccess)
+    {
+        goto failed;
+    }
+    // Register DFS as power client and obtain client id
+    error = NvRmPowerRegister(hRmDeviceHandle, pDfs->hSemaphore, &pDfs->PowerClientId);
+    if (error != NvSuccess)
+    {
+        goto failed;
+    }
+
+    // DFS busy hints synchronization objects
+    error = NvOsMutexCreate(&pDfs->hSyncBusyMutex);
+    if (error != NvSuccess)
+    {
+        goto failed;
+    }
+    error = NvOsSemaphoreCreate(&pDfs->hSyncBusySemaphore, 0);
+    if (error != NvSuccess)
+    {
+        goto failed;
+    }
+
+    /* 
+     * Get DFS modules capbilities, check which activity monitors are
+     * supported, and initialize monitor access function pointers. Then
+     * initialize DFS samples and H/w monitors
+     */
+    error = DfsGetModulesCapabilities(pDfs);
+    if (error != NvSuccess)
+    {
+        goto failed;
+    }
+    DfsClockFreqGet(hRmDeviceHandle, &DfsKHz);
+    DfsSamplersInit(&DfsKHz, pDfs);
+    error = DfsHwInit(pDfs);
+    if (error != NvSuccess)
+    {
+        goto failed;
+    }
+
+    /*
+     * Configure System Statistic module interrupt, which will be used to
+     * trigger DFS algorithm execution
+     */
+    {
+        pDfs->IrqNumber = NvRmGetIrqForLogicalInterrupt(hRmDeviceHandle, 
+                NVRM_MODULE_ID(NvRmModuleID_SysStatMonitor, 0), 
+                0);
+    }
+    if (!pDfs->DfsInterruptHandle)
+    {
+        NvU32 IrqList = (NvU32)pDfs->IrqNumber;
+        NvOsInterruptHandler hDfsIsr = DfsIsr;
+        error = NvRmInterruptRegister(hRmDeviceHandle, 1, 
+                &IrqList, &hDfsIsr, pDfs, &pDfs->DfsInterruptHandle, NV_TRUE);
+        if (error != NvSuccess)
+        {
+            // Set IRQ invalid to avoid deregistration of other module interrupt
+            pDfs->IrqNumber = NVRM_IRQ_INVALID;  
+            goto failed;
+        }
+    }
+
+    /*
+     * Provided DFS is initialized in running state, start sampling for the
+     * next sampling interval based on current DFS domain frtequencies and
+     * enable DFS interrupt
+     */
+    if (pDfs->DfsRunState > NvRmDfsRunState_Stopped)
+    {
+        DfsStartMonitors(
+            pDfs, &pDfs->CurrentKHz, pDfs->SamplingWindow.NextIntervalMs);
+    }
+    return NvSuccess;
+
+failed:
+    NvRmPrivDfsDeinit(hRmDeviceHandle);
+    return error;
+}
+
+void NvRmPrivDfsDeinit(NvRmDeviceHandle hRmDeviceHandle)
+{
+    NvRmDfs* pDfs = &s_Dfs;
+    NV_ASSERT(hRmDeviceHandle);
+
+    // Release all DFS resources
+    NvRmInterruptUnregister(hRmDeviceHandle, pDfs->DfsInterruptHandle);
+    pDfs->DfsInterruptHandle = NULL;
+    DfsThreadTerminate(pDfs);
+    DfsHwDeinit(pDfs);
+    NvOsSemaphoreDestroy(pDfs->hSyncBusySemaphore);
+    NvOsMutexDestroy(pDfs->hSyncBusyMutex);
+    NvRmPowerUnRegister(hRmDeviceHandle, pDfs->PowerClientId);
+    NvOsSemaphoreDestroy(pDfs->hSemaphore);
+    NvOsIntrMutexDestroy(pDfs->hIntrMutex); 
+    NvOsMemset(pDfs, 0, sizeof(NvRmDfs));
+}
+
+NvRmFreqKHz NvRmPrivDfsGetMaxKHz(NvRmDfsClockId ClockId)
+{
+    NvRmDfs* pDfs = &s_Dfs;
+    NV_ASSERT((0 < ClockId) && (ClockId < NvRmDfsClockId_Num));
+    return pDfs->DfsParameters[ClockId].MaxKHz;
+}
+
+NvRmFreqKHz NvRmPrivDfsGetMinKHz(NvRmDfsClockId ClockId)
+{
+    NvRmDfs* pDfs = &s_Dfs;
+    NV_ASSERT((0 < ClockId) && (ClockId < NvRmDfsClockId_Num));
+    return pDfs->DfsParameters[ClockId].MinKHz;
+}
+
+NvRmFreqKHz NvRmPrivDfsGetCurrentKHz(NvRmDfsClockId ClockId)
+{
+    NvRmDfs* pDfs = &s_Dfs;
+    NV_ASSERT((0 < ClockId) && (ClockId < NvRmDfsClockId_Num));
+    return pDfs->CurrentKHz.Domains[ClockId];
+}
+
+void NvRmPrivDfsSignal(NvRmDfsBusyHintSyncMode Mode)
+{
+    NvRmDfs* pDfs = &s_Dfs;
+
+    // Just signal clock control thread for asynchronous busy hint or if the
+    // thread has not been created (no DFS execution at all)
+    if (!((Mode == NvRmDfsBusyHintSyncMode_Sync) && pDfs->InitializedThread))
+    {
+        NvOsSemaphoreSignal(pDfs->hSemaphore);
+        return;
+    }
+
+    // Signal clock control thread and wait for clock update before return
+    // to caller for synchronous busy hint
+    NvOsMutexLock(pDfs->hSyncBusyMutex);
+
+    pDfs->BusySyncState = NvRmDfsBusySyncState_Signal;
+    NvOsSemaphoreSignal(pDfs->hSemaphore);
+
+#if !DFS_SYNC_BUSY_TIMEOUT_MS
+    NvOsSemaphoreWait(pDfs->hSyncBusySemaphore);
+#else
+    if(NvError_Timeout == NvOsSemaphoreWaitTimeout(
+        pDfs->hSyncBusySemaphore, DFS_SYNC_BUSY_TIMEOUT_MS))
+    {
+        NvOsDebugPrintf("Syncronous busy hint timeout detected");
+        NV_ASSERT(0);
+    }
+#endif
+    NvOsMutexUnlock(pDfs->hSyncBusyMutex);
+}
+
+void NvRmPrivDfsResync(void)
+{
+    NvRmDfsFrequencies DfsKHz;
+    NvRmDfs* pDfs = &s_Dfs;
+
+    DfsClockFreqGet(pDfs->hRm, &DfsKHz);
+
+    NvOsIntrMutexLock(pDfs->hIntrMutex);
+    pDfs->CurrentKHz = DfsKHz;
+    NvOsIntrMutexUnlock(pDfs->hIntrMutex);
+}
+
+NvRmPmRequest NvRmPrivPmThread(void)
+{
+    return DfsThread(&s_Dfs);
+}
+
+void NvRmPrivStarvationHintPrintf(
+    NvU32 ClientId,
+    NvU32 ClientTag,
+    const NvRmDfsStarvationHint* pMultiHint,
+    NvU32 NumHints)
+{
+#if DFS_HINTS_PRINTF
+    {
+        NvU32 i;
+        char ClientName[sizeof(ClientTag)+ 1];
+        ClientTagToString(ClientTag, ClientName); 
+
+        for (i = 0; i < NumHints; i++)
+        {
+            const NvRmDfsStarvationHint* pHint = &pMultiHint[i];
+            NvOsDebugPrintf("%s starvation hint: %s from client %3d (%s)\n",
+                            s_DfsDomainNames[pHint->ClockId], 
+                            (pHint->Starving ? "TRUE " : "FALSE"),
+                            ClientId, ClientName);
+        }
+    }
+#endif
+#if DFS_LOGGING_SECONDS
+    {
+        NvU32 i, SampleIndex;
+        NvRmDfs* pDfs = &s_Dfs;
+
+        NvOsIntrMutexLock(pDfs->hIntrMutex);
+        if (s_DfsLogOn &&
+            ((s_DfsLogStarvationWrIndex  + NumHints) < DFS_LOG_SIZE))
+        {
+            SampleIndex = s_DfsLogWrIndex;
+            for (i = 0; i < NumHints; i++)
+            {
+                DfsLogStarvationHint* pEntry =
+                    &s_DfsLogStarvation[s_DfsLogStarvationWrIndex++];
+                pEntry->LogSampleIndex = SampleIndex;
+                pEntry->ClientId = ClientId;
+                pEntry->ClientTag = ClientTag;
+                pEntry->StarvationHint = pMultiHint[i];
+            }
+        }
+        NvOsIntrMutexUnlock(pDfs->hIntrMutex);
+    }
+#endif
+}
+
+void NvRmPrivBusyHintPrintf(
+    NvU32 ClientId,
+    NvU32 ClientTag,
+    const NvRmDfsBusyHint* pMultiHint,
+    NvU32 NumHints)
+{
+#if DFS_HINTS_PRINTF
+    {
+        NvU32 i;
+        char ClientName[sizeof(ClientTag)+ 1];
+        ClientTagToString(ClientTag, ClientName); 
+
+        for (i = 0; i < NumHints; i++)
+        {
+            const NvRmDfsBusyHint* pHint = &pMultiHint[i];
+            NvRmFreqKHz BoostKHz = (pHint->BoostKHz == NvRmFreqMaximum) ?
+                NvRmPrivDfsGetMaxKHz(pHint->ClockId) : pHint->BoostKHz;
+            NvOsDebugPrintf("%s busy hint: %6dkHz %4dms from client %3d (%s)\n",
+                            s_DfsDomainNames[pHint->ClockId], BoostKHz,
+                            pHint->BoostDurationMs, ClientId, ClientName);
+        }
+    }
+#endif
+#if DFS_LOGGING_SECONDS
+    {
+        NvU32 i, SampleIndex;
+        NvRmDfs* pDfs = &s_Dfs;
+
+        NvOsIntrMutexLock(pDfs->hIntrMutex);
+        if (s_DfsLogOn && ((s_DfsLogBusyWrIndex + NumHints) < DFS_LOG_SIZE))
+        {
+            SampleIndex = s_DfsLogWrIndex;
+            for (i = 0; i < NumHints; i++)
+            {
+                DfsLogBusyHint* pEntry = &s_DfsLogBusy[s_DfsLogBusyWrIndex++];
+                pEntry->LogSampleIndex = SampleIndex;
+                pEntry->ClientId = ClientId;
+                pEntry->ClientTag = ClientTag;
+                pEntry->BusyHint = pMultiHint[i];
+                if (pEntry->BusyHint.BoostKHz == NvRmFreqMaximum)
+                    pEntry->BusyHint.BoostKHz =
+                    NvRmPrivDfsGetMaxKHz(pEntry->BusyHint.ClockId);
+            }
+        }
+        NvOsIntrMutexUnlock(pDfs->hIntrMutex);
+    }
+#endif
+}
+
+/*****************************************************************************/
+// DVS PRIVATE INTERFACES
+/*****************************************************************************/
+
+static void
+DvsChangeCoreVoltage(
+    NvRmDeviceHandle hRm,
+    NvRmDvs* pDvs,
+    NvRmMilliVolts TargetMv)
+{
+    NvBool WasLow;
+    NvRmMilliVolts CurrentMv = pDvs->CurrentCoreMv;
+
+    NV_ASSERT(TargetMv >= pDvs->MinCoreMv);
+    NV_ASSERT(TargetMv <= pDvs->NominalCoreMv);
+
+    // Go from current to target voltage in safe steps keeping core and
+    // rtc volatges in synch (core voltage above rtc during transition)
+    while (CurrentMv != TargetMv)
+    {
+        WasLow = (CurrentMv < pDvs->LowSvopThresholdMv);
+
+        if (CurrentMv < TargetMv)
+        {
+            CurrentMv += NVRM_SAFE_VOLTAGE_STEP_MV;
+            if (CurrentMv > TargetMv)
+                CurrentMv = TargetMv;
+            NvRmPmuSetVoltage(hRm, pDvs->CoreRailAddress, CurrentMv, NULL);
+            if (pDvs->CoreRailAddress != pDvs->RtcRailAddress)
+                NvRmPmuSetVoltage(hRm, pDvs->RtcRailAddress, CurrentMv, NULL);
+            if (WasLow && (CurrentMv >= pDvs->LowSvopThresholdMv))
+            {
+                // Clear SVOP bits after crossing SVOP threshold up
+                NvRmPrivAp15SetSvopControls(hRm, pDvs->HighSvopSettings);
+            }
+        }
+        else
+        {
+            CurrentMv -= NVRM_SAFE_VOLTAGE_STEP_MV;
+            if (CurrentMv < TargetMv)
+                CurrentMv = TargetMv;
+            if (!WasLow && (CurrentMv < pDvs->LowSvopThresholdMv))
+            {   // Set SVOP bits before crossing SVOP threshold down
+                NvRmPrivAp15SetSvopControls(hRm, pDvs->LowSvopSettings);
+            }
+            NvRmPmuSetVoltage(hRm, pDvs->RtcRailAddress, CurrentMv, NULL);
+            if (pDvs->CoreRailAddress != pDvs->RtcRailAddress)
+                NvRmPmuSetVoltage(hRm, pDvs->CoreRailAddress, CurrentMv, NULL);
+        }
+    }
+    pDvs->CurrentCoreMv = TargetMv;
+}
+
+static void
+DvsChangeCpuVoltage(
+    NvRmDeviceHandle hRm,
+    NvRmDvs* pDvs,
+    NvRmMilliVolts TargetMv)
+{
+    NV_ASSERT(TargetMv >= pDvs->MinCpuMv);
+    NV_ASSERT(TargetMv <= pDvs->NominalCpuMv);
+
+    if (pDvs->CurrentCpuMv != TargetMv)
+    {
+        NvRmPmuSetVoltage(hRm, pDvs->CpuRailAddress, TargetMv, NULL);
+        pDvs->CurrentCpuMv = TargetMv;
+    }
+}
+
+void NvRmPrivDvsInit(void)
+{
+    NvRmPmuVddRailCapabilities cap;
+    NvRmDfs* pDfs = &s_Dfs;
+    NvRmDvs* pDvs = &s_Dfs.VoltageScaler;
+    NvOdmPmuProperty PmuProperty = {0};
+
+    const NvOdmPeripheralConnectivity* pRtcRail =
+        NvOdmPeripheralGetGuid(NV_VDD_RTC_ODM_ID);
+    const NvOdmPeripheralConnectivity* pCoreRail =
+        NvOdmPeripheralGetGuid(NV_VDD_CORE_ODM_ID);
+
+    /* Some systems(ex. FPGA) does have power rail control. */
+    if (!pRtcRail || !pCoreRail)
+        return;
+
+    pDvs->NominalCoreMv = NvRmPrivGetNominalMV(pDfs->hRm);
+    pDvs->MinCoreMv = NvRmPrivSourceVscaleGetMV(pDfs->hRm, 0);
+    pDvs->LowCornerCoreMv = pDvs->MinCoreMv;
+    NvRmPrivGetSvopParameters(pDfs->hRm, &pDvs->LowSvopThresholdMv,
+                              &pDvs->LowSvopSettings, &pDvs->HighSvopSettings);
+    pDvs->UpdateFlag = NV_FALSE;
+    pDvs->StopFlag = NV_FALSE;
+    pDvs->Lp2SyncOTPFlag = NV_FALSE;
+
+    // Get RTC rail address, check range and resolution
+    NV_ASSERT(pRtcRail && pRtcRail->NumAddress);
+    pDvs->RtcRailAddress = pRtcRail->AddressList[0].Address;
+    NvRmPmuGetCapabilities(pDfs->hRm, pDvs->RtcRailAddress, &cap);
+    NV_ASSERT((cap.StepMilliVolts) &&
+              (cap.StepMilliVolts <= NVRM_SAFE_VOLTAGE_STEP_MV));
+    NV_ASSERT(cap.MinMilliVolts <= pDvs->MinCoreMv);
+    NV_ASSERT(cap.MaxMilliVolts >= pDvs->NominalCoreMv);
+
+    // Get Core rail address, check range and resolution
+    NV_ASSERT(pCoreRail && pCoreRail->NumAddress);
+    pDvs->CoreRailAddress = pCoreRail->AddressList[0].Address;
+    NvRmPmuGetCapabilities(pDfs->hRm, pDvs->CoreRailAddress, &cap);
+    NV_ASSERT((cap.StepMilliVolts) &&
+              (cap.StepMilliVolts <= NVRM_SAFE_VOLTAGE_STEP_MV));
+    NV_ASSERT((cap.StepMilliVolts) &&
+              (cap.StepMilliVolts <= NVRM_CORE_RESOLUTION_MV));
+    NV_ASSERT(cap.MinMilliVolts <= pDvs->MinCoreMv);
+    NV_ASSERT(cap.MaxMilliVolts >= pDvs->NominalCoreMv);
+
+    if (NvRmPrivIsCpuRailDedicated(pDfs->hRm))
+    {
+        // Get dedicated CPU rail address, check range and resolution
+        const NvOdmPeripheralConnectivity* pCpuRail =
+            NvOdmPeripheralGetGuid(NV_VDD_CPU_ODM_ID);
+
+        pDvs->NominalCpuMv = NvRmPrivModuleVscaleGetMV(
+            pDfs->hRm, NvRmModuleID_Cpu,
+            NvRmPrivGetSocClockLimits(NvRmModuleID_Cpu)->MaxKHz);
+        pDvs->MinCpuMv = NvRmPrivModuleVscaleGetMV(
+            pDfs->hRm, NvRmModuleID_Cpu,
+            NvRmPrivGetSocClockLimits(NvRmModuleID_Cpu)->MinKHz);
+
+        NV_ASSERT(pCpuRail && pCpuRail->NumAddress);
+        pDvs->CpuRailAddress = pCpuRail->AddressList[0].Address;
+        NvRmPmuGetCapabilities(pDfs->hRm, pDvs->CpuRailAddress, &cap);
+        NV_ASSERT((cap.StepMilliVolts) &&
+                  (cap.StepMilliVolts <= NVRM_SAFE_VOLTAGE_STEP_MV));
+        NV_ASSERT((cap.StepMilliVolts) &&
+                  (cap.StepMilliVolts <= NVRM_CORE_RESOLUTION_MV));
+#if NVRM_DVS_ACCEPT_PMU_HIGH_CPU_MIN
+        pDvs->MinCpuMv = NV_MAX(pDvs->MinCpuMv, cap.MinMilliVolts);
+        pDvs->NominalCpuMv = NV_MAX(pDvs->NominalCpuMv, pDvs->MinCpuMv);
+#else
+        NV_ASSERT(pDvs->MinCpuMv <= pDvs->NominalCpuMv);
+        NV_ASSERT(cap.MinMilliVolts <= pDvs->MinCpuMv);
+#endif
+        NV_ASSERT(cap.MaxMilliVolts >= pDvs->NominalCpuMv);
+        pDvs->CpuOTPMv = cap.requestMilliVolts;
+        pDvs->LowCornerCpuMv = pDvs->MinCpuMv;
+
+        // CPU rail behaviour after CPU request signal On-Off-On transition
+        if (NvOdmQueryGetPmuProperty(&PmuProperty))
+            pDvs->VCpuOTPOnWakeup = PmuProperty.VCpuOTPOnWakeup;
+
+        // Get dedicated CPU rail boot voltage
+        NvRmPmuGetVoltage(pDfs->hRm, pDvs->CpuRailAddress, &pDvs->CurrentCpuMv);
+    }
+
+    // Get boot core voltage.  Check if DFS is disabled - no voltage scaling
+    // in this case. Otherwise, set nominal core and dedicated cpu voltages.
+    // Initialize DVS corner variables.
+    NvRmPmuGetVoltage(pDfs->hRm, pDvs->CoreRailAddress, &pDvs->CurrentCoreMv);
+    if ((pDfs->DfsRunState <= NvRmDfsRunState_Disabled))
+    {
+        pDvs->RtcRailAddress = pDvs->CoreRailAddress = 0;
+        return;
+    }
+
+    if (NvRmPrivIsCpuRailDedicated(pDfs->hRm))
+    {
+        // If core voltage is going up, update it before CPU and vice versa
+        if (pDvs->CurrentCoreMv <= pDvs->NominalCoreMv)
+        {
+            DvsChangeCoreVoltage(pDfs->hRm, pDvs, pDvs->NominalCoreMv);
+        }
+        DvsChangeCpuVoltage(pDfs->hRm, pDvs, pDvs->NominalCpuMv);
+        pDvs->DvsCorner.CpuMv = pDvs->NominalCpuMv;
+
+        if (pDvs->CurrentCoreMv > pDvs->NominalCoreMv)
+        {
+            NvOsWaitUS(NVRM_CPU_TO_CORE_DOWN_US); // delay if core to go down
+            DvsChangeCoreVoltage(pDfs->hRm, pDvs, pDvs->NominalCoreMv);
+        }
+        // No core scaling if CPU voltage is not preserved across LPx
+        if (pDvs->VCpuOTPOnWakeup)
+            pDvs->MinCoreMv = pDvs->NominalCoreMv;
+    }
+    else
+    {
+        DvsChangeCoreVoltage(pDfs->hRm, pDvs, pDvs->NominalCoreMv);
+        pDvs->DvsCorner.CpuMv = pDvs->NominalCoreMv;
+    }
+    pDvs->DvsCorner.SystemMv = pDvs->NominalCoreMv;
+    pDvs->DvsCorner.EmcMv = pDvs->NominalCoreMv;
+    pDvs->DvsCorner.ModulesMv = pDvs->NominalCoreMv;
+
+    if ((pDfs->hRm->ChipId.Id == 0x15) || (pDfs->hRm->ChipId.Id == 0x16))
+    {
+        pDvs->LowCornerCoreMv = NV_MAX(NVRM_AP15_LOW_CORE_MV, pDvs->MinCoreMv);
+        pDvs->LowCornerCoreMv =
+            NV_MIN(pDvs->LowCornerCoreMv, pDvs->NominalCoreMv);
+    }
+    else if (pDfs->hRm->ChipId.Id == 0x20)
+    {
+        pDvs->LowCornerCoreMv = NV_MAX(NVRM_AP20_LOW_CORE_MV, pDvs->MinCoreMv);
+        pDvs->LowCornerCoreMv =
+            NV_MIN(pDvs->LowCornerCoreMv, pDvs->NominalCoreMv);
+
+        pDvs->LowCornerCpuMv = NV_MAX(NVRM_AP20_LOW_CPU_MV, pDvs->MinCpuMv);
+        pDvs->LowCornerCpuMv =
+            NV_MIN(pDvs->LowCornerCpuMv, pDvs->NominalCpuMv);
+    }
+}
+
+void NvRmPrivVoltageScale(
+    NvBool BeforeFreqChange,
+    NvRmMilliVolts CpuMv,
+    NvRmMilliVolts SystemMv,
+    NvRmMilliVolts EmcMv)
+{
+    NvRmMilliVolts TargetMv;
+    NvRmDfs* pDfs = &s_Dfs;
+    NvRmDvs* pDvs = &s_Dfs.VoltageScaler;
+    NvBool DedicatedCpuRail = NvRmPrivIsCpuRailDedicated(pDfs->hRm);
+    
+    /* Some systems(ex. FPGA) does have power rail control. */
+    if (!pDvs->RtcRailAddress || !pDvs->CoreRailAddress)
+        return;
+
+    // Record new DVS threshold and determine new target voltage as maximunm of
+    // all thresholds
+    pDvs->DvsCorner.CpuMv = CpuMv;
+    pDvs->DvsCorner.SystemMv = SystemMv;
+    pDvs->DvsCorner.EmcMv = EmcMv;
+
+    NvRmPrivLockModuleClockState();
+    TargetMv = NvRmPrivModulesGetOperationalMV(pDfs->hRm);
+    NvRmPrivUnlockModuleClockState();
+    pDvs->DvsCorner.ModulesMv = TargetMv;
+
+    if (!DedicatedCpuRail && (TargetMv < CpuMv))
+        TargetMv = CpuMv;
+    if (TargetMv < SystemMv)
+        TargetMv = SystemMv;
+    if (TargetMv < EmcMv)
+        TargetMv = EmcMv;
+
+    // Clip new target voltage to core voltage limits
+    if (TargetMv > pDvs->NominalCoreMv)
+        TargetMv = pDvs->NominalCoreMv;
+    else if (TargetMv < pDvs->LowCornerCoreMv)
+        TargetMv = pDvs->LowCornerCoreMv;
+
+    if (DedicatedCpuRail)
+    {
+        // Clip new CPU voltage to CPU voltage limits
+        if (CpuMv > pDvs->NominalCpuMv)
+            CpuMv = pDvs->NominalCpuMv;
+        else if (CpuMv < pDvs->LowCornerCpuMv)
+            CpuMv = pDvs->LowCornerCpuMv;
+
+        // Increase voltage before changing frequency, and vice versa;
+        // Change core 1st before changing frequency, and vice versa
+        // (to guarantee required margin of core voltage over CPU voltage) 
+        if (BeforeFreqChange)
+        {
+            if (pDvs->Lp2SyncOTPFlag)
+            {
+                // If required, synchronize DVFS state with CPU rail default
+                // level after LP2 exit
+                pDvs->Lp2SyncOTPFlag = NV_FALSE;
+                pDvs->CurrentCpuMv = pDvs->CpuOTPMv;
+            }
+            if (pDvs->CurrentCoreMv < TargetMv)
+                DvsChangeCoreVoltage(pDfs->hRm, pDvs, TargetMv);
+            if (pDvs->CurrentCpuMv < CpuMv)
+                DvsChangeCpuVoltage(pDfs->hRm, pDvs, CpuMv);
+        }
+        else
+        {
+            if (pDvs->CurrentCpuMv > CpuMv)
+            {
+                DvsChangeCpuVoltage(pDfs->hRm, pDvs, CpuMv);
+                // Defer core voltage change to the next DVFS tick to account
+                // for CPU capacitors discharge
+                if (pDvs->CurrentCoreMv > TargetMv)
+                    pDvs->UpdateFlag = NV_TRUE;
+            }
+            else if (pDvs->CurrentCoreMv > TargetMv)
+                DvsChangeCoreVoltage(pDfs->hRm, pDvs, TargetMv);
+        }
+    }
+    else
+    {
+        //  Increase voltage before changing frequency, and vice versa
+        if ((BeforeFreqChange && (pDvs->CurrentCoreMv < TargetMv)) ||
+            (!BeforeFreqChange && (pDvs->CurrentCoreMv > TargetMv)))
+        {
+            DvsChangeCoreVoltage(pDfs->hRm, pDvs, TargetMv);
+        }
+    }
+}
+
+void NvRmPrivDvsRequest(NvRmMilliVolts TargetMv)
+{
+    NvRmDfs* pDfs = &s_Dfs;
+    NvRmDvs* pDvs = &s_Dfs.VoltageScaler;
+
+    // Do nothing for unspecified target.
+    if (TargetMv == NvRmVoltsUnspecified)
+        return;
+
+    /* Some systems(ex. FPGA) does have power rail control. */
+    if (!pDvs->RtcRailAddress || !pDvs->CoreRailAddress)
+        return;
+
+    // Clip new target voltage to core voltage limits
+    if (TargetMv > pDvs->NominalCoreMv)
+        TargetMv = pDvs->NominalCoreMv;
+    else if (TargetMv < pDvs->LowCornerCoreMv)
+        TargetMv = pDvs->LowCornerCoreMv;
+
+    // If new target voltage is above current - update immediately. If target
+    // is below current voltage - just set update flag, so that next DFS ISR
+    // signals DFS thread, which checks operational voltage for all modules.
+    if (TargetMv > pDvs->CurrentCoreMv)
+    {
+        DvsChangeCoreVoltage(pDfs->hRm, pDvs, TargetMv);
+    }
+    else if (TargetMv < pDvs->CurrentCoreMv)
+    {
+        pDvs->UpdateFlag = NV_TRUE;
+    }
+}
+
+void
+NvRmPrivGetLowVoltageThreshold(
+    NvRmDfsVoltageRailId RailId,
+    NvRmMilliVolts* pLowMv,
+    NvRmMilliVolts* pPresentMv)
+{
+    NvRmDfs* pDfs = &s_Dfs;
+    NvRmDvs* pDvs = &s_Dfs.VoltageScaler;
+    NV_ASSERT(pLowMv);
+
+    switch (RailId)
+    {
+        case NvRmDfsVoltageRailId_Core:
+            *pLowMv = pDvs->LowCornerCoreMv;
+            if(pPresentMv)
+                *pPresentMv = pDvs->CurrentCoreMv;
+            break;
+
+        case NvRmDfsVoltageRailId_Cpu:
+            if (NvRmPrivIsCpuRailDedicated(pDfs->hRm))
+            {
+                *pLowMv = pDvs->LowCornerCpuMv;
+                if(pPresentMv)
+                    *pPresentMv = pDvs->CurrentCpuMv;
+                break;
+            }
+            // fall through
+
+        default:
+            *pLowMv = NvRmVoltsUnspecified;
+            if(pPresentMv)
+                *pPresentMv = NvRmVoltsUnspecified;
+            break;
+    }
+}
+
+static void NvRmPrivDvsStopAtNominal(void)
+{
+    NvRmDfs* pDfs = &s_Dfs;
+    NvRmDvs* pDvs = &s_Dfs.VoltageScaler;
+
+    /* Some systems(ex. FPGA) does have power rail control. */
+    if (!pDvs->RtcRailAddress || !pDvs->CoreRailAddress)
+        return;
+
+    // Set nominal voltage
+    DvsChangeCoreVoltage(pDfs->hRm, pDvs, pDvs->NominalCoreMv);
+    if(NvRmPrivIsCpuRailDedicated(pDfs->hRm))
+        DvsChangeCpuVoltage(pDfs->hRm, pDvs, pDvs->NominalCpuMv);
+}
+
+static void NvRmPrivDvsRun(void)
+{
+    NvRmDvs* pDvs = &s_Dfs.VoltageScaler;
+    pDvs->UpdateFlag = NV_TRUE;
+    pDvs->StopFlag = NV_FALSE;
+}
+
+void NvRmPrivDfsSuspend(NvOdmSocPowerState state)
+{
+    NvRmDfs* pDfs = &s_Dfs;
+    NvBool UpdateClocks = NV_FALSE;
+    NvRmDfsFrequencies DfsKHz;
+
+    // Fill in target frequencies for suspend state on the 1st entry
+    // (use invalid domain frequency as 1st flag)
+    if (pDfs->SuspendKHz.Domains[0] == 0)
+    {
+        if ((pDfs->hRm->ChipId.Id == 0x15) || (pDfs->hRm->ChipId.Id == 0x16))
+            NvRmPrivAp15DfsVscaleFreqGet(
+                pDfs->hRm, NVRM_AP15_SUSPEND_CORE_MV, &pDfs->SuspendKHz);
+        else if (pDfs->hRm->ChipId.Id == 0x20)
+            NvRmPrivAp20DfsSuspendFreqGet(
+                pDfs->hRm, NVRM_AP20_SUSPEND_CORE_MV, &pDfs->SuspendKHz);
+        else
+            pDfs->SuspendKHz = pDfs->LowCornerKHz; // Low corner by default
+        pDfs->SuspendKHz.Domains[0] = NvRmFreqMaximum;   
+    }
+    
+    NvRmPrivLockSharedPll();
+    if (state == NvOdmSocPowerState_DeepSleep)
+    {
+        // On entry to deep sleeep (LP0): set nominal voltage level and
+        // stop DVFS at nominal voltage until resume.
+        NvOsIntrMutexLock(pDfs->hIntrMutex);
+        pDfs->DfsLPxSavedState = pDfs->DfsRunState;
+        if (pDfs->DfsLPxSavedState > NvRmDfsRunState_Stopped)
+            pDfs->DfsRunState = NvRmDfsRunState_Stopped;
+        NvOsIntrMutexUnlock(pDfs->hIntrMutex);
+
+        NvRmPrivDvsStopAtNominal();
+        pDfs->VoltageScaler.StopFlag = NV_TRUE;
+    }
+    else if (state == NvOdmSocPowerState_Suspend)
+    {
+        // On entry to suspend (LP1): set target frequencies for all DFS
+        // clock domains, stop DFS monitors, and then configure clocks and
+        // core voltage. Stop DVFS in suspend corner until resume.
+        DfsKHz = pDfs->SuspendKHz;
+
+        NvOsIntrMutexLock(pDfs->hIntrMutex);
+        pDfs->DfsLPxSavedState = pDfs->DfsRunState;
+        if (pDfs->DfsLPxSavedState > NvRmDfsRunState_Stopped)
+        {
+            pDfs->DfsRunState = NvRmDfsRunState_Stopped;
+            pDfs->TargetKHz = DfsKHz;
+            UpdateClocks = NV_TRUE;
+        }
+        NvOsIntrMutexUnlock(pDfs->hIntrMutex);
+
+        for (; UpdateClocks;)
+        {
+            if (DfsClockConfigure(pDfs->hRm, &pDfs->MaxKHz, &DfsKHz))
+            {
+                pDfs->CurrentKHz = DfsKHz;  // DFS is already stopped - no mutex
+                break;
+            }
+            DfsKHz = pDfs->SuspendKHz;
+        }
+
+        if (NvRmPrivIsCpuRailDedicated(pDfs->hRm))
+        {
+            NvRmDvs* pDvs = &s_Dfs.VoltageScaler;
+            NvRmMilliVolts v = NV_MAX(pDvs->DvsCorner.SystemMv,
+                                      NV_MAX(pDvs->DvsCorner.EmcMv,
+                                             pDvs->DvsCorner.ModulesMv));
+
+            // If CPU rail returns to default level by PMU underneath DVFS
+            // need to synchronize voltage after LP1 same way as after LP2
+            if (pDvs->VCpuOTPOnWakeup)
+                pDfs->VoltageScaler.Lp2SyncOTPFlag = NV_TRUE;
+
+            // If core voltage change was deferred until CPU voltage is
+            // settled - do it now
+            if (v < pDvs->CurrentCoreMv)
+            {
+                NvOsWaitUS(NVRM_CPU_TO_CORE_DOWN_US);
+                DvsChangeCoreVoltage(pDfs->hRm, pDvs, v);
+            }
+            NvOsDebugPrintf("DVFS set core at %dmV\n", pDvs->CurrentCoreMv);
+        }
+
+        pDfs->VoltageScaler.StopFlag = NV_TRUE;
+    }
+    NvRmPrivUnlockSharedPll();
+}
+
+/*****************************************************************************/
+// DTT PRIVATE INTERFACES
+/*****************************************************************************/
+
+void NvRmPrivDttInit(NvRmDeviceHandle hRmDeviceHandle)
+{
+    NvRmDfs* pDfs = &s_Dfs;
+    NvRmDtt* pDtt = &pDfs->ThermalThrottler;
+
+    // Make sure TMON h/w is initialized
+    pDtt->hOdmTcore = NvOdmTmonDeviceOpen(NvOdmTmonZoneID_Core);
+
+    // No thermal throttling if DFS is disabled, otherwise start DTTS
+    if (pDfs->DfsRunState < NvRmDfsRunState_Stopped)
+    {
+        NvOdmTmonDeviceClose(pDtt->hOdmTcore);
+        pDtt->hOdmTcore = NULL;
+        return;
+    }
+
+    if (!pDtt->hOdmTcore)
+    {
+        if (pDfs->hRm->ChipId.Id == 0x20)
+        {
+            // TODO: assert?
+            NvOsDebugPrintf("DTT: TMON initialization failed\n");
+        }
+        return;
+    }
+    NvOdmTmonCapabilitiesGet(pDtt->hOdmTcore, &pDtt->TcoreCaps);
+    NvOdmTmonParameterCapsGet(pDtt->hOdmTcore,
+        NvOdmTmonConfigParam_IntrLimitLow, &pDtt->TcoreLowLimitCaps);
+    NvOdmTmonParameterCapsGet(pDtt->hOdmTcore,
+        NvOdmTmonConfigParam_IntrLimitHigh, &pDtt->TcoreHighLimitCaps);
+
+#if !NVRM_DTT_DISABLED
+    // Default policy for room temperature
+    DttPolicyUpdate(hRmDeviceHandle, 25, pDtt);
+    pDtt->TcorePolicy.TimeUs = NvRmPrivGetUs();
+#endif
+
+    if (pDtt->TcoreCaps.IntrSupported &&
+        !pDtt->TcoreLowLimitCaps.OdmProtected &&
+        !pDtt->TcoreHighLimitCaps.OdmProtected)
+    {
+        // Sanity checks to make sure out-of-limit interrupt is available in
+        // the entire temperature range 
+        NV_ASSERT(pDtt->TcoreLowLimitCaps.MinValue <= pDtt->TcoreCaps.Tmin);
+        NV_ASSERT(pDtt->TcoreHighLimitCaps.MinValue <= pDtt->TcoreCaps.Tmin);
+        NV_ASSERT(pDtt->TcoreLowLimitCaps.MaxValue >= pDtt->TcoreCaps.Tmax);
+        NV_ASSERT(pDtt->TcoreHighLimitCaps.MaxValue >= pDtt->TcoreCaps.Tmax);
+#if NVRM_DTT_USE_INTERRUPT
+        pDtt->UseIntr = NV_TRUE;
+#endif
+    }
+}
+
+void NvRmPrivDttDeinit()
+{
+    NvRmDfs* pDfs = &s_Dfs;
+    NvOdmTmonDeviceHandle hOdmTcore = pDfs->ThermalThrottler.hOdmTcore;
+    NvOdmTmonIntrHandle hOdmTcoreIntr = pDfs->ThermalThrottler.hOdmTcoreIntr;
+
+    NvOdmTmonIntrUnregister(hOdmTcore, hOdmTcoreIntr);
+    pDfs->ThermalThrottler.hOdmTcoreIntr = NULL;
+
+    NvOdmTmonDeviceClose(hOdmTcore);
+    pDfs->ThermalThrottler.hOdmTcore = NULL;
+}
+
+/*****************************************************************************/
+// DFS PUBLIC INTERFACES
+/*****************************************************************************/
+
+NvRmDfsRunState
+NvRmDfsGetState(
+    NvRmDeviceHandle hRmDeviceHandle)
+{
+    NvRmDfsRunState state;
+    NvRmDfs* pDfs = &s_Dfs;
+    NV_ASSERT(hRmDeviceHandle);
+
+    if(!pDfs->hIntrMutex)
+        return NvRmDfsRunState_Invalid;
+
+    NvOsIntrMutexLock(pDfs->hIntrMutex);
+    state = pDfs->DfsRunState;
+    NvOsIntrMutexUnlock(pDfs->hIntrMutex);
+    return state;
+}
+
+NvError
+NvRmDfsSetState(
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvRmDfsRunState NewDfsRunState)
+{
+    NvRmDfsRunState OldDfsRunState;
+    NvRmDfsFrequencies DfsKHz;
+    NvError error = NvSuccess;
+    NvRmDfs* pDfs = &s_Dfs;
+    
+    NV_ASSERT(hRmDeviceHandle);
+    NV_ASSERT(pDfs->hIntrMutex);
+    NV_ASSERT((0 < NewDfsRunState) && (NewDfsRunState < NvRmDfsRunState_Num)); 
+
+    NvRmPrivLockSharedPll();
+    DfsClockFreqGet(hRmDeviceHandle, &DfsKHz);
+
+    NvOsIntrMutexLock(pDfs->hIntrMutex);
+    OldDfsRunState = pDfs->DfsRunState;
+
+    // No transition from disabled state is supported
+    if (OldDfsRunState == NvRmDfsRunState_Disabled)
+        NewDfsRunState = NvRmDfsRunState_Invalid;
+
+    /*
+     * State transition procedures
+     */ 
+    switch (NewDfsRunState)
+    {
+        // On transition to running states from stopped state samplers are
+        // initialized and restarted; if profiled loop is supported and it
+        // is specified as a new state, profile is initialized as well
+#if DFS_PROFILING
+        case NvRmDfsRunState_ProfiledLoop:
+            DfsProfileInit(pDfs);
+            // fall through
+#endif
+        case NvRmDfsRunState_ClosedLoop:
+            pDfs->DfsRunState = NewDfsRunState;
+            if (OldDfsRunState == NvRmDfsRunState_Stopped)
+            {
+                DfsSamplersInit(&DfsKHz, pDfs);
+                DfsStartMonitors(
+                    pDfs, &pDfs->CurrentKHz, pDfs->SamplingWindow.NextIntervalMs);
+            }
+            break;
+
+        // On transition to stopped state just stop DFS targets at whatever
+        // frequency they are now
+        case NvRmDfsRunState_Stopped:
+            pDfs->DfsRunState = NewDfsRunState;
+            break;
+
+        // Not supported transition
+        default:
+            error = NvError_NotSupported;
+            break;
+    }
+    pDfs->DfsLPxSavedState = pDfs->DfsRunState;
+    NvOsIntrMutexUnlock(pDfs->hIntrMutex);
+    NvRmPrivUnlockSharedPll();
+    return error;
+}
+
+NvError
+NvRmDfsSetLowCorner(
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvU32 DfsFreqListCount,
+    const NvRmFreqKHz* pDfsLowFreqList)
+{
+    NvU32 i;
+    NvRmDfs* pDfs = &s_Dfs;
+    
+    NV_ASSERT(hRmDeviceHandle);
+    NV_ASSERT(pDfs->hIntrMutex);
+    NV_ASSERT(DfsFreqListCount == NvRmDfsClockId_Num);
+    NV_ASSERT(pDfsLowFreqList);
+
+    NvOsIntrMutexLock(pDfs->hIntrMutex);
+
+    // Nothing to set if DFS is disabled
+    if (pDfs->DfsRunState == NvRmDfsRunState_Disabled)
+    {
+        NvOsIntrMutexUnlock(pDfs->hIntrMutex);
+        return NvError_NotSupported;
+    }
+
+    // Clip requested low corner frequencies to domain limits and update
+    // DFS low corner (keep corner unchanged if new value is "unspecified")
+    for (i = 1; i < NvRmDfsClockId_Num; i++)
+    {
+        NvRmFreqKHz DomainKHz = pDfsLowFreqList[i];
+        // Preserve CPU or EMC low boundary when the respective envelope is set
+        if ((pDfs->CpuEnvelopeSet && (i == NvRmDfsClockId_Cpu)) ||
+            (pDfs->EmcEnvelopeSet && (i == NvRmDfsClockId_Emc)))
+        {
+            continue;
+        }
+        if (DomainKHz != NvRmFreqUnspecified)
+        {
+            if (DomainKHz < pDfs->DfsParameters[i].MinKHz)
+            {
+                DomainKHz = pDfs->DfsParameters[i].MinKHz;
+            }
+            else if (DomainKHz > pDfs->HighCornerKHz.Domains[i])
+            {
+                DomainKHz = pDfs->HighCornerKHz.Domains[i];
+            }
+            pDfs->LowCornerKHz.Domains[i] = DomainKHz;
+            if (i == NvRmDfsClockId_Cpu)
+                pDfs->CpuCornersShadow.MinKHz = DomainKHz;
+        }
+    }
+    NvOsIntrMutexUnlock(pDfs->hIntrMutex);
+    return NvSuccess;
+}
+
+NvError
+NvRmDfsSetAvHighCorner(
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvRmFreqKHz DfsAvSystemHighKHz,
+    NvRmFreqKHz DfsAvpHighKHz,
+    NvRmFreqKHz DfsVpipeHighKHz)
+{
+    NvU32 i;
+    NvRmDfs* pDfs = &s_Dfs;
+
+    NV_ASSERT(hRmDeviceHandle);
+    NV_ASSERT(pDfs->hIntrMutex);
+
+    NvOsIntrMutexLock(pDfs->hIntrMutex);
+
+    // Nothing to set if DFS is disabled
+    if (pDfs->DfsRunState == NvRmDfsRunState_Disabled)
+    {
+        NvOsIntrMutexUnlock(pDfs->hIntrMutex);
+        return NvError_NotSupported;
+    }
+
+    // Clip requested VDE high corner frequency to domain limits
+    // (keep corner unchanged if new value is "unspecified")
+    if (DfsVpipeHighKHz == NvRmFreqUnspecified)
+        DfsVpipeHighKHz = pDfs->HighCornerKHz.Domains[NvRmDfsClockId_Vpipe];
+    else if (DfsVpipeHighKHz > pDfs->DfsParameters[NvRmDfsClockId_Vpipe].MaxKHz)
+        DfsVpipeHighKHz = pDfs->DfsParameters[NvRmDfsClockId_Vpipe].MaxKHz;
+    else if (DfsVpipeHighKHz < pDfs->LowCornerKHz.Domains[NvRmDfsClockId_Vpipe])
+        DfsVpipeHighKHz = pDfs->LowCornerKHz.Domains[NvRmDfsClockId_Vpipe];
+
+    // Clip requested AVP high corner frequency to domain limits
+    // (keep corner unchanged if new value is "unspecified")
+    if (DfsAvpHighKHz == NvRmFreqUnspecified)
+        DfsAvpHighKHz = pDfs->HighCornerKHz.Domains[NvRmDfsClockId_Avp];
+    else if (DfsAvpHighKHz > pDfs->DfsParameters[NvRmDfsClockId_Avp].MaxKHz)
+        DfsAvpHighKHz = pDfs->DfsParameters[NvRmDfsClockId_Avp].MaxKHz;
+    else if (DfsAvpHighKHz < pDfs->LowCornerKHz.Domains[NvRmDfsClockId_Avp])
+        DfsAvpHighKHz = pDfs->LowCornerKHz.Domains[NvRmDfsClockId_Avp];
+
+
+    // Clip requested AVP/System high corner frequency to domain limits
+    // (keep corner unchanged if new value is "unspecified")
+    if (DfsAvSystemHighKHz == NvRmFreqUnspecified)
+        DfsAvSystemHighKHz = pDfs->HighCornerKHz.Domains[NvRmDfsClockId_System];
+    else if (DfsAvSystemHighKHz > pDfs->DfsParameters[NvRmDfsClockId_System].MaxKHz)
+        DfsAvSystemHighKHz = pDfs->DfsParameters[NvRmDfsClockId_System].MaxKHz;
+    else    
+    {   // System high boundary must be above all AV low boundaries
+        for (i = 1; i < NvRmDfsClockId_Num; i++)
+        {
+            if ((i != NvRmDfsClockId_Cpu) &&
+                (i != NvRmDfsClockId_Emc))
+            {
+                if ((i == NvRmDfsClockId_Vpipe) &&
+                    (!NvRmPrivGetClockSourceHandle(NvRmClockSource_Vbus)))
+                    continue; // Skip v-pipe if VDE clock is decoupled from AV
+
+                if (DfsAvSystemHighKHz < pDfs->LowCornerKHz.Domains[i])
+                    DfsAvSystemHighKHz = pDfs->LowCornerKHz.Domains[i];
+            }
+        }
+    }
+
+    // Make sure new System and AVP, VDE high boundaries are consistent
+    if ((DfsAvSystemHighKHz < DfsVpipeHighKHz) &&
+        NvRmPrivGetClockSourceHandle(NvRmClockSource_Vbus))
+    {
+        DfsAvSystemHighKHz = DfsVpipeHighKHz;
+    }
+    if (DfsAvSystemHighKHz < DfsAvpHighKHz)
+    {
+        DfsAvSystemHighKHz = DfsAvpHighKHz;
+    }
+
+    // Finally update high corner
+    pDfs->HighCornerKHz.Domains[NvRmDfsClockId_System] = DfsAvSystemHighKHz;
+    pDfs->HighCornerKHz.Domains[NvRmDfsClockId_Ahb] = NV_MIN(
+        DfsAvSystemHighKHz, pDfs->DfsParameters[NvRmDfsClockId_Ahb].MaxKHz);
+    pDfs->HighCornerKHz.Domains[NvRmDfsClockId_Apb] = NV_MIN(
+        DfsAvSystemHighKHz, pDfs->DfsParameters[NvRmDfsClockId_Apb].MaxKHz);
+
+    pDfs->HighCornerKHz.Domains[NvRmDfsClockId_Avp] = DfsAvpHighKHz;
+    pDfs->HighCornerKHz.Domains[NvRmDfsClockId_Vpipe] = DfsVpipeHighKHz;
+
+    NvOsIntrMutexUnlock(pDfs->hIntrMutex);
+    return NvSuccess;
+}
+
+NvError
+NvRmDfsSetCpuEmcHighCorner(
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvRmFreqKHz DfsCpuHighKHz,
+    NvRmFreqKHz DfsEmcHighKHz)
+{
+    NvRmDfs* pDfs = &s_Dfs;
+
+    NV_ASSERT(hRmDeviceHandle);
+    NV_ASSERT(pDfs->hIntrMutex);
+
+    NvOsIntrMutexLock(pDfs->hIntrMutex);
+
+    // Nothing to set if DFS is disabled
+    if (pDfs->DfsRunState == NvRmDfsRunState_Disabled)
+    {
+        NvOsIntrMutexUnlock(pDfs->hIntrMutex);
+        return NvError_NotSupported;
+    }
+
+    // Preserve CPU and EMC high corners if either CPU or EMC envelope is set
+    if (pDfs->CpuEnvelopeSet || pDfs->EmcEnvelopeSet)
+    {
+        NvOsIntrMutexUnlock(pDfs->hIntrMutex);
+        return NvSuccess;
+    }
+
+    // Keep corner unchanged if new requested value is "unspecified"
+    if (DfsCpuHighKHz == NvRmFreqUnspecified)
+        DfsCpuHighKHz = pDfs->HighCornerKHz.Domains[NvRmDfsClockId_Cpu];
+    if (DfsEmcHighKHz == NvRmFreqUnspecified)
+        DfsEmcHighKHz = pDfs->HighCornerKHz.Domains[NvRmDfsClockId_Emc];
+
+    // Clip requested CPU and EMC high corner frequencies to domain maximum
+    if (DfsCpuHighKHz > pDfs->DfsParameters[NvRmDfsClockId_Cpu].MaxKHz)
+        DfsCpuHighKHz = pDfs->DfsParameters[NvRmDfsClockId_Cpu].MaxKHz;
+    if (DfsEmcHighKHz > pDfs->DfsParameters[NvRmDfsClockId_Emc].MaxKHz)
+        DfsEmcHighKHz = pDfs->DfsParameters[NvRmDfsClockId_Emc].MaxKHz;
+
+    // Clip requested CPU and EMC high corner to supported EMC configuration
+    DfsClipCpuEmcHighLimits(
+        hRmDeviceHandle, &DfsCpuHighKHz, &DfsEmcHighKHz);
+
+    // Clip requested CPU and EMC frequencies to domain low limits
+    if (DfsCpuHighKHz < pDfs->LowCornerKHz.Domains[NvRmDfsClockId_Cpu])
+        DfsCpuHighKHz = pDfs->LowCornerKHz.Domains[NvRmDfsClockId_Cpu];
+    if (DfsEmcHighKHz < pDfs->LowCornerKHz.Domains[NvRmDfsClockId_Emc])
+        DfsEmcHighKHz = pDfs->LowCornerKHz.Domains[NvRmDfsClockId_Emc];
+
+    // Finally update high corner
+    pDfs->HighCornerKHz.Domains[NvRmDfsClockId_Cpu] = DfsCpuHighKHz;
+    pDfs->CpuCornersShadow.MaxKHz = DfsCpuHighKHz;
+    pDfs->HighCornerKHz.Domains[NvRmDfsClockId_Emc] = DfsEmcHighKHz;
+
+    NvOsIntrMutexUnlock(pDfs->hIntrMutex);
+    return NvSuccess;
+}
+
+NvError
+NvRmDfsSetCpuEnvelope(
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvRmFreqKHz DfsCpuLowCornerKHz,
+    NvRmFreqKHz DfsCpuHighCornerKHz)
+{
+    NvRmDfs* pDfs = &s_Dfs;
+
+    NV_ASSERT(hRmDeviceHandle);
+    NV_ASSERT(pDfs->hIntrMutex);
+
+    NvOsIntrMutexLock(pDfs->hIntrMutex);
+
+    // Nothing to set if DFS is disabled
+    if (pDfs->DfsRunState == NvRmDfsRunState_Disabled)
+    {
+        NvOsIntrMutexUnlock(pDfs->hIntrMutex);
+        return NvError_NotSupported;
+    }
+
+    // Preserve unspecified boundary, unless it violates new setting for
+    // the other one; set both boundaries equal in the latter case
+    if (DfsCpuLowCornerKHz == NvRmFreqUnspecified)
+    {
+        DfsCpuLowCornerKHz = pDfs->LowCornerKHz.Domains[NvRmDfsClockId_Cpu];
+        if (DfsCpuLowCornerKHz > DfsCpuHighCornerKHz)
+            DfsCpuLowCornerKHz = DfsCpuHighCornerKHz;
+    }
+    if (DfsCpuHighCornerKHz == NvRmFreqUnspecified)
+    {
+        DfsCpuHighCornerKHz = pDfs->HighCornerKHz.Domains[NvRmDfsClockId_Cpu];
+        if (DfsCpuLowCornerKHz > DfsCpuHighCornerKHz)
+            DfsCpuHighCornerKHz = DfsCpuLowCornerKHz;
+    }
+
+    // Can not set envelope with reversed boundaries
+    if (DfsCpuLowCornerKHz > DfsCpuHighCornerKHz)
+    {
+        NV_ASSERT(!"CPU envelope boundaries are reversed");
+        NvOsIntrMutexUnlock(pDfs->hIntrMutex);
+        return NvError_BadValue;
+    }
+
+    // Clip requested boundaries to CPU domain limits; mark envelope "set" if
+    // any requested boundary is inside the limits
+    pDfs->CpuEnvelopeSet = NV_FALSE;    // assume envelope is open
+
+    if (DfsCpuLowCornerKHz <= pDfs->DfsParameters[NvRmDfsClockId_Cpu].MinKHz)
+        DfsCpuLowCornerKHz = pDfs->DfsParameters[NvRmDfsClockId_Cpu].MinKHz;
+    else
+    {
+        pDfs->CpuEnvelopeSet = NV_TRUE; // envelope sealed
+        if (DfsCpuLowCornerKHz >= pDfs->DfsParameters[NvRmDfsClockId_Cpu].MaxKHz)
+            DfsCpuLowCornerKHz = pDfs->DfsParameters[NvRmDfsClockId_Cpu].MaxKHz;
+    }
+
+    if (DfsCpuHighCornerKHz >= pDfs->DfsParameters[NvRmDfsClockId_Cpu].MaxKHz)
+        DfsCpuHighCornerKHz = pDfs->DfsParameters[NvRmDfsClockId_Cpu].MaxKHz;
+    else
+    {
+        pDfs->CpuEnvelopeSet = NV_TRUE; // envelope sealed
+        if (DfsCpuHighCornerKHz <= pDfs->DfsParameters[NvRmDfsClockId_Cpu].MinKHz)
+            DfsCpuHighCornerKHz = pDfs->DfsParameters[NvRmDfsClockId_Cpu].MinKHz;
+    }
+    // Shadow new limits before they may be throttled by EMC
+    pDfs->CpuCornersShadow.MinKHz = DfsCpuLowCornerKHz;
+    pDfs->CpuCornersShadow.MaxKHz = DfsCpuHighCornerKHz;
+
+    // If EMC envelope is set, move (throttle) CPU envelope as necessary
+    if (pDfs->EmcEnvelopeSet)
+    {
+        NvRmFreqKHz EmcHighKHz = pDfs->HighCornerKHz.Domains[NvRmDfsClockId_Emc];
+        DfsClipCpuEmcHighLimits(
+            hRmDeviceHandle, &DfsCpuHighCornerKHz, &EmcHighKHz);
+        NV_ASSERT(EmcHighKHz == pDfs->HighCornerKHz.Domains[NvRmDfsClockId_Emc]);
+        if (DfsCpuLowCornerKHz > DfsCpuHighCornerKHz)
+            DfsCpuLowCornerKHz = DfsCpuHighCornerKHz;
+    }
+
+    // Finally update CPU limits
+    pDfs->LowCornerKHz.Domains[NvRmDfsClockId_Cpu] = DfsCpuLowCornerKHz;
+    pDfs->HighCornerKHz.Domains[NvRmDfsClockId_Cpu] = DfsCpuHighCornerKHz;
+
+    NvOsIntrMutexUnlock(pDfs->hIntrMutex);
+    return NvSuccess;
+}
+
+NvError
+NvRmDfsSetEmcEnvelope(
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvRmFreqKHz DfsEmcLowCornerKHz,
+    NvRmFreqKHz DfsEmcHighCornerKHz)
+{
+    NvRmDfs* pDfs = &s_Dfs;
+
+    NV_ASSERT(hRmDeviceHandle);
+    NV_ASSERT(pDfs->hIntrMutex);
+
+    NvOsIntrMutexLock(pDfs->hIntrMutex);
+
+    // Nothing to set if DFS is disabled
+    if (pDfs->DfsRunState == NvRmDfsRunState_Disabled)
+    {
+        NvOsIntrMutexUnlock(pDfs->hIntrMutex);
+        return NvError_NotSupported;
+    }
+
+    // Preserve unspecified boundary, unless it violates new setting for
+    // the other one; set both boundaries equal in the latter case
+    if (DfsEmcLowCornerKHz == NvRmFreqUnspecified)
+    {
+        DfsEmcLowCornerKHz = pDfs->LowCornerKHz.Domains[NvRmDfsClockId_Emc];
+        if (DfsEmcLowCornerKHz > DfsEmcHighCornerKHz)
+            DfsEmcLowCornerKHz = DfsEmcHighCornerKHz;
+    }
+    if (DfsEmcHighCornerKHz == NvRmFreqUnspecified)
+    {
+        DfsEmcHighCornerKHz = pDfs->HighCornerKHz.Domains[NvRmDfsClockId_Emc];
+        if (DfsEmcLowCornerKHz > DfsEmcHighCornerKHz)
+            DfsEmcHighCornerKHz = DfsEmcLowCornerKHz;
+    }
+
+    // Can not set envelope with reversed boundaries
+    if (DfsEmcLowCornerKHz > DfsEmcHighCornerKHz)
+    {
+        NV_ASSERT(!"EMC envelope boundaries are reversed");
+        NvOsIntrMutexUnlock(pDfs->hIntrMutex);
+        return NvError_BadValue;
+    }
+
+    // Clip requested boundaries to EMC domain limits; mark envelope "set" if
+    // any requested boundary is inside the limits
+    pDfs->EmcEnvelopeSet = NV_FALSE;    // assume envelope is open
+
+    if (DfsEmcLowCornerKHz <= pDfs->DfsParameters[NvRmDfsClockId_Emc].MinKHz)
+        DfsEmcLowCornerKHz = pDfs->DfsParameters[NvRmDfsClockId_Emc].MinKHz;
+    else
+    {
+        pDfs->EmcEnvelopeSet = NV_TRUE; // envelope sealed
+        if (DfsEmcLowCornerKHz >= pDfs->DfsParameters[NvRmDfsClockId_Emc].MaxKHz)
+            DfsEmcLowCornerKHz = pDfs->DfsParameters[NvRmDfsClockId_Emc].MaxKHz;
+    }
+
+    if (DfsEmcHighCornerKHz >= pDfs->DfsParameters[NvRmDfsClockId_Emc].MaxKHz)
+        DfsEmcHighCornerKHz = pDfs->DfsParameters[NvRmDfsClockId_Emc].MaxKHz;
+    else
+    {
+        pDfs->EmcEnvelopeSet = NV_TRUE; // envelope sealed
+        if (DfsEmcHighCornerKHz <= pDfs->DfsParameters[NvRmDfsClockId_Emc].MinKHz)
+            DfsEmcHighCornerKHz = pDfs->DfsParameters[NvRmDfsClockId_Emc].MinKHz;
+    }
+
+    // Restore CPU corners from shadow. If set, clip EMC envelope to the supported
+    // EMC configuration, and throttle CPU corners as necessary
+    pDfs->LowCornerKHz.Domains[NvRmDfsClockId_Cpu] = pDfs->CpuCornersShadow.MinKHz;
+    pDfs->HighCornerKHz.Domains[NvRmDfsClockId_Cpu] = pDfs->CpuCornersShadow.MaxKHz;
+    if (pDfs->EmcEnvelopeSet)
+    {
+        NvRmFreqKHz CpuHighKHz = pDfs->HighCornerKHz.Domains[NvRmDfsClockId_Cpu];
+        DfsClipCpuEmcHighLimits(
+            hRmDeviceHandle, &CpuHighKHz, &DfsEmcHighCornerKHz);
+        if (DfsEmcLowCornerKHz > DfsEmcHighCornerKHz)
+            DfsEmcLowCornerKHz = DfsEmcHighCornerKHz;
+
+        if (pDfs->HighCornerKHz.Domains[NvRmDfsClockId_Cpu] > CpuHighKHz)
+        {
+            pDfs->HighCornerKHz.Domains[NvRmDfsClockId_Cpu] = CpuHighKHz;
+            if (pDfs->LowCornerKHz.Domains[NvRmDfsClockId_Cpu] > CpuHighKHz)
+                pDfs->LowCornerKHz.Domains[NvRmDfsClockId_Cpu] = CpuHighKHz;
+        }
+    }
+    // Finally update EMC limits
+    pDfs->LowCornerKHz.Domains[NvRmDfsClockId_Emc] = DfsEmcLowCornerKHz;
+    pDfs->HighCornerKHz.Domains[NvRmDfsClockId_Emc] = DfsEmcHighCornerKHz;
+
+    NvOsIntrMutexUnlock(pDfs->hIntrMutex);
+    return NvSuccess;
+}
+
+NvError
+NvRmDfsSetTarget( 
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvU32 DfsFreqListCount,
+    const NvRmFreqKHz* pDfsTargetFreqList)
+{
+    NvU32 i;
+    NvRmDfsFrequencies DfsKHz;
+    NvRmDfs* pDfs = &s_Dfs;
+
+    NV_ASSERT(hRmDeviceHandle);
+    NV_ASSERT(pDfs->hIntrMutex);
+    NV_ASSERT(DfsFreqListCount == NvRmDfsClockId_Num);
+    NV_ASSERT(pDfsTargetFreqList);
+
+    NvRmPrivLockSharedPll();
+    DfsClockFreqGet(hRmDeviceHandle, &DfsKHz);
+
+    NvOsIntrMutexLock(pDfs->hIntrMutex);
+
+    // Do nothing if DFS is not stopped (disabled or running)
+    if (pDfs->DfsRunState != NvRmDfsRunState_Stopped)
+    {
+        NvOsIntrMutexUnlock(pDfs->hIntrMutex);
+        NvRmPrivUnlockSharedPll();
+        return NvError_NotSupported;
+    }
+
+    // Clip requested target frequencies to domain limits
+    // (keep current frequency as a target if new value is "unspecified")
+    for (i = 1; i < NvRmDfsClockId_Num; i++)
+    {
+        NvRmFreqKHz DomainKHz = pDfsTargetFreqList[i];
+        if (DomainKHz != NvRmFreqUnspecified)
+        {
+            if (DomainKHz < pDfs->LowCornerKHz.Domains[i])
+            {
+                DomainKHz = pDfs->LowCornerKHz.Domains[i];
+            }
+            else if (DomainKHz > pDfs->HighCornerKHz.Domains[i])
+            {
+                DomainKHz = pDfs->HighCornerKHz.Domains[i];
+            }
+            DfsKHz.Domains[i] = DomainKHz;
+        }
+    }
+
+    // Set target and signal clock control thread ("manual clock control")
+    pDfs->TargetKHz = DfsKHz;
+    NvOsIntrMutexUnlock(pDfs->hIntrMutex);
+    NvRmPrivUnlockSharedPll();
+    NvOsSemaphoreSignal(pDfs->hSemaphore);
+    return NvSuccess;
+}
+
+NvError
+NvRmDfsGetClockUtilization(
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvRmDfsClockId ClockId,
+    NvRmDfsClockUsage* pClockUsage)
+{
+    NvRmDfsFrequencies DfsKHz;
+    NvRmDfs* pDfs = &s_Dfs;
+
+    NV_ASSERT(hRmDeviceHandle);
+    NV_ASSERT(pDfs->hIntrMutex);
+    NV_ASSERT(pClockUsage);
+    NV_ASSERT((0 < ClockId) && (ClockId < NvRmDfsClockId_Num));
+
+    NvRmPrivLockSharedPll();
+    DfsClockFreqGet(hRmDeviceHandle, &DfsKHz);
+
+    NvOsIntrMutexLock(pDfs->hIntrMutex);
+
+    // If DFS is not running - update current frequencies directly from h/w
+    if (pDfs->DfsRunState <= NvRmDfsRunState_Stopped)
+    {
+        pDfs->CurrentKHz = DfsKHz;
+        if (pDfs->Samplers[ClockId].MonitorPresent)
+            pDfs->Samplers[ClockId].AverageKHz = DfsKHz.Domains[ClockId];
+    }
+    // Update clock info
+    pClockUsage->MinKHz = pDfs->DfsParameters[ClockId].MinKHz;
+    pClockUsage->MaxKHz = pDfs->DfsParameters[ClockId].MaxKHz;
+    pClockUsage->LowCornerKHz = pDfs->LowCornerKHz.Domains[ClockId];
+    pClockUsage->HighCornerKHz = pDfs->HighCornerKHz.Domains[ClockId];
+    pClockUsage->CurrentKHz = pDfs->CurrentKHz.Domains[ClockId];
+    pClockUsage->AverageKHz = pDfs->Samplers[ClockId].AverageKHz; 
+
+    NvOsIntrMutexUnlock(pDfs->hIntrMutex);
+    NvRmPrivUnlockSharedPll();
+    return NvSuccess;
+}
+
+NvError
+NvRmDfsGetProfileData( 
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvU32 DfsProfileCount,
+    NvU32* pSamplesNoList,
+    NvU32* pProfileTimeUsList,
+    NvU32* pDfsPeriodUs)
+{
+#if DFS_PROFILING
+    NvU32 i;
+    NvRmDfs* pDfs = &s_Dfs;
+    NV_ASSERT(hRmDeviceHandle);
+    NV_ASSERT(pDfs->hIntrMutex);
+    NV_ASSERT(pProfileTimeUsList && pSamplesNoList && pDfsPeriodUs);
+    NV_ASSERT(DfsProfileCount == NvRmDfsProfileId_Num);
+
+    NvOsIntrMutexLock(pDfs->hIntrMutex);
+
+    // Nothing to return if DFS is not in profiled loop
+    if (pDfs->DfsRunState != NvRmDfsRunState_ProfiledLoop)
+    {
+        NvOsIntrMutexUnlock(pDfs->hIntrMutex);
+        return NvError_NotSupported;
+    }
+    // Return profile data
+    for (i = 1; i < DfsProfileCount; i++)
+    {
+        pSamplesNoList[i] = s_Profile.SamplesNo[i];
+        pProfileTimeUsList[i] = s_Profile.AccumulatedUs[i];
+    }
+    *pDfsPeriodUs = pDfs->SamplingWindow.SampleWindowMs * 1000 /
+        NV_ARRAY_SIZE(pDfs->SamplingWindow.IntervalsMs);
+
+    NvOsIntrMutexUnlock(pDfs->hIntrMutex);
+    return NvSuccess;
+
+#else
+
+    return NvError_NotSupported;
+#endif
+}
+
+void
+NvRmDfsLogStart(NvRmDeviceHandle hRmDeviceHandle)
+{
+    NvU32 i;
+    NvRmDfs* pDfs = &s_Dfs;
+
+    NV_ASSERT(hRmDeviceHandle);
+    NV_ASSERT(pDfs->hIntrMutex);
+
+    NvOsIntrMutexLock(pDfs->hIntrMutex);
+    s_DfsLogOn = NV_TRUE;
+
+    for (i = 1; i < NvRmDfsClockId_Num; i++)
+    {
+        pDfs->Samplers[i].CumulativeLogCycles = 0;
+    }
+    pDfs->SamplingWindow.CumulativeLogMs = 0;
+    pDfs->SamplingWindow.CumulativeLp2TimeMs = 0;
+    pDfs->SamplingWindow.CumulativeLp2Entries = 0;
+    
+#if DFS_LOGGING_SECONDS
+    s_DfsLogWrIndex = 0;
+    s_DfsLogStarvationWrIndex = 0;
+    s_DfsLogBusyWrIndex = 0;
+#endif
+    NvOsIntrMutexUnlock(pDfs->hIntrMutex);
+}
+
+NvError
+NvRmDfsLogGetMeanFrequencies(
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvU32 LogMeanFreqListCount,
+    NvRmFreqKHz* pLogMeanFreqList,
+    NvU32* pLogLp2TimeMs,
+    NvU32* pLogLp2Entries)
+{
+    NvU32 i, msec;
+    NvRmDfs* pDfs = &s_Dfs;
+
+    NV_ASSERT(hRmDeviceHandle);
+    NV_ASSERT(pDfs->hIntrMutex);
+    NV_ASSERT(LogMeanFreqListCount == NvRmDfsClockId_Num);
+    NV_ASSERT(pLogMeanFreqList);
+
+    NvOsIntrMutexLock(pDfs->hIntrMutex);
+    s_DfsLogOn = NV_FALSE;
+
+    // No logging if DFS is disabled
+    if (pDfs->DfsRunState == NvRmDfsRunState_Disabled)
+    {
+        NvOsIntrMutexUnlock(pDfs->hIntrMutex);
+        return NvError_NotSupported;
+    }
+
+    // Return cumulative mean frequencies: (Kcycles/ms) * 1000 = kHz;
+    // (if log never started or running more than 49 days return 0)
+    msec = pDfs->SamplingWindow.CumulativeLogMs;
+    for (i = 1; i < LogMeanFreqListCount; i++)
+    {
+        pLogMeanFreqList[i] = 
+            (NvU32)NvDiv64(pDfs->Samplers[i].CumulativeLogCycles, msec);
+    }
+    // TODO: update if condition SystemKHz = AvpKHz changes
+    pLogMeanFreqList[NvRmDfsClockId_System] =
+        pLogMeanFreqList[NvRmDfsClockId_Avp];
+
+    // Return cumulative LP2 statistic
+    *pLogLp2TimeMs = pDfs->SamplingWindow.CumulativeLp2TimeMs;
+    *pLogLp2Entries = pDfs->SamplingWindow.CumulativeLp2Entries;
+
+    NvOsIntrMutexUnlock(pDfs->hIntrMutex);
+    return NvSuccess;
+}
+
+NvError
+NvRmDfsLogActivityGetEntry( 
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvU32 EntryIndex,
+    NvU32 LogDomainsCount,
+    NvU32* pIntervalMs,
+    NvU32* pLp2TimeMs,
+    NvU32* pActiveCyclesList,
+    NvRmFreqKHz* pAveragesList,
+    NvRmFreqKHz* pFrequenciesList)
+{
+#if DFS_LOGGING_SECONDS
+    NvU32 i;
+    DfsLogEntry* pEntry;
+    NvRmDfs* pDfs = &s_Dfs;
+
+    NV_ASSERT(hRmDeviceHandle);
+    NV_ASSERT(pDfs->hIntrMutex);
+    NV_ASSERT(pFrequenciesList && pActiveCyclesList && pIntervalMs);
+    NV_ASSERT(LogDomainsCount == NvRmDfsClockId_Num);
+
+    NvOsIntrMutexLock(pDfs->hIntrMutex);
+
+    // No logging if DFS is disabled
+    if (pDfs->DfsRunState == NvRmDfsRunState_Disabled)
+    {
+        NvOsIntrMutexUnlock(pDfs->hIntrMutex);
+        return NvError_NotSupported;
+    }
+
+    // Nothing to return if log is empty
+    if (EntryIndex >= s_DfsLogWrIndex)
+    {
+        NvOsIntrMutexUnlock(pDfs->hIntrMutex);
+        return NvError_InvalidAddress;
+    }
+
+    // Return log data
+    NV_ASSERT(EntryIndex < DFS_LOG_SIZE);
+    pEntry = &s_DfsLog[EntryIndex];
+    for (i = 1; i < LogDomainsCount; i++)
+    {
+        pFrequenciesList[i] = pEntry->CurrentKHz.Domains[i];
+        pAveragesList[i] = pEntry->AverageKHz.Domains[i];
+        pActiveCyclesList[i] = pEntry->ActiveCycles[i];
+    }
+    *pIntervalMs = pEntry->SampleIntervalMs;
+    *pLp2TimeMs = pEntry->Lp2TimeMs;
+
+    NvOsIntrMutexUnlock(pDfs->hIntrMutex);
+    return NvSuccess;
+
+#else
+
+    return NvError_NotSupported;
+#endif
+}
+
+NvError
+NvRmDfsLogStarvationGetEntry( 
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvU32 EntryIndex,
+    NvU32* pSampleIndex,
+    NvU32* pClientId,
+    NvU32* pClientTag,
+    NvRmDfsStarvationHint* pStarvationHint)
+{
+#if DFS_LOGGING_SECONDS
+    NvRmDfs* pDfs = &s_Dfs;
+
+    NV_ASSERT(hRmDeviceHandle);
+    NV_ASSERT(pDfs->hIntrMutex);
+    NV_ASSERT(pSampleIndex && pStarvationHint);
+
+    NvOsIntrMutexLock(pDfs->hIntrMutex);
+
+    // No logging if DFS is disabled
+    if (pDfs->DfsRunState == NvRmDfsRunState_Disabled)
+    {
+        NvOsIntrMutexUnlock(pDfs->hIntrMutex);
+        return NvError_NotSupported;
+    }
+
+    // Nothing to return if requested entry index is empty
+    if (EntryIndex >= s_DfsLogStarvationWrIndex)
+    {
+        NvOsIntrMutexUnlock(pDfs->hIntrMutex);
+        return NvError_InvalidAddress;
+    }
+
+    // Return log data
+    NV_ASSERT(EntryIndex < DFS_LOG_SIZE);
+    *pSampleIndex = s_DfsLogStarvation[EntryIndex].LogSampleIndex;
+    *pClientId = s_DfsLogStarvation[EntryIndex].ClientId;
+    *pClientTag = s_DfsLogStarvation[EntryIndex].ClientTag;
+    *pStarvationHint = s_DfsLogStarvation[EntryIndex].StarvationHint;
+
+    NvOsIntrMutexUnlock(pDfs->hIntrMutex);
+    return NvSuccess;
+
+#else
+
+    return NvError_NotSupported;
+#endif
+}
+
+NvError
+NvRmDfsLogBusyGetEntry( 
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvU32 EntryIndex,
+    NvU32* pSampleIndex,
+    NvU32* pClientId,
+    NvU32* pClientTag,
+    NvRmDfsBusyHint* pBusyHint)
+{
+#if DFS_LOGGING_SECONDS
+    NvRmDfs* pDfs = &s_Dfs;
+
+    NV_ASSERT(hRmDeviceHandle);
+    NV_ASSERT(pDfs->hIntrMutex);
+    NV_ASSERT(pSampleIndex && pBusyHint);
+
+    NvOsIntrMutexLock(pDfs->hIntrMutex);
+
+    // No logging if DFS is disabled
+    if (pDfs->DfsRunState == NvRmDfsRunState_Disabled)
+    {
+        NvOsIntrMutexUnlock(pDfs->hIntrMutex);
+        return NvError_NotSupported;
+    }
+
+    // Nothing to return if requested entry index is empty
+    if (EntryIndex >= s_DfsLogBusyWrIndex)
+    {
+        NvOsIntrMutexUnlock(pDfs->hIntrMutex);
+        return NvError_InvalidAddress;
+    }
+
+    // Return log data
+    NV_ASSERT(EntryIndex < DFS_LOG_SIZE);
+    *pSampleIndex = s_DfsLogBusy[EntryIndex].LogSampleIndex;
+    *pClientId = s_DfsLogBusy[EntryIndex].ClientId;
+    *pClientTag = s_DfsLogBusy[EntryIndex].ClientTag;
+    *pBusyHint = s_DfsLogBusy[EntryIndex].BusyHint;
+
+    NvOsIntrMutexUnlock(pDfs->hIntrMutex);
+    return NvSuccess;
+
+#else
+
+    return NvError_NotSupported;
+#endif
+}
+
+/*****************************************************************************/
+// DVS PUBLIC INTERFACES
+/*****************************************************************************/
+
+void
+NvRmDfsGetLowVoltageThreshold(
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvRmDfsVoltageRailId RailId,
+    NvRmMilliVolts* pLowMv,
+    NvRmMilliVolts* pPresentMv)
+{
+    NV_ASSERT(hRmDeviceHandle);
+
+    NvRmPrivLockSharedPll();
+    NvRmPrivGetLowVoltageThreshold(RailId, pLowMv, pPresentMv);
+    NvRmPrivUnlockSharedPll();
+}
+
+void
+NvRmDfsSetLowVoltageThreshold(
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvRmDfsVoltageRailId RailId,
+    NvRmMilliVolts LowMv)
+{
+    NvRmDvs* pDvs = &s_Dfs.VoltageScaler;
+
+    NV_ASSERT(hRmDeviceHandle);
+
+    // Low threshold is not specified - exit
+    if (LowMv == NvRmVoltsUnspecified)
+        return;
+
+    NvRmPrivLockSharedPll();
+
+    switch (RailId)
+    {
+        case NvRmDfsVoltageRailId_Core:
+            // Clip specified voltage level to core voltage range,
+            // and update low voltage settings
+            if (LowMv > pDvs->NominalCoreMv)
+                LowMv = pDvs->NominalCoreMv;
+            else if (LowMv < pDvs->MinCoreMv)
+                LowMv = pDvs->MinCoreMv;
+            pDvs->LowCornerCoreMv = LowMv;
+            pDvs->UpdateFlag = NV_TRUE;
+            break;
+
+        case NvRmDfsVoltageRailId_Cpu:
+            if (NvRmPrivIsCpuRailDedicated(hRmDeviceHandle))
+            {
+                // Clip specified voltage level to CPU voltage range,
+                // and update low voltage settings
+                if (LowMv > pDvs->NominalCpuMv)
+                    LowMv = pDvs->NominalCpuMv;
+                else if (LowMv < pDvs->MinCpuMv)
+                    LowMv = pDvs->MinCpuMv;
+                pDvs->LowCornerCpuMv = LowMv;
+                pDvs->UpdateFlag = NV_TRUE;
+            }
+            break;
+
+        default:
+            break;
+    }
+    NvRmPrivUnlockSharedPll();
+}
+
+/*****************************************************************************/
+// DTT PUBLIC INTERFACES
+/*****************************************************************************/
+
+NvError
+NvRmDiagGetTemperature( 
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvRmTmonZoneId ZoneId,
+    NvS32* pTemperatureC)
+{
+    NvRmDtt* pDtt = &s_Dfs.ThermalThrottler;
+
+    NV_ASSERT(hRmDeviceHandle);
+
+    switch (ZoneId)
+    {
+        case NvRmTmonZoneId_Core:
+            if (pDtt->hOdmTcore)
+            {
+                if (NvOdmTmonTemperatureGet(pDtt->hOdmTcore, pTemperatureC))
+                    return NvSuccess;
+                return NvError_Busy;
+            }
+            // fall through
+        default:
+            return NvError_NotSupported;
+    }
+}
+
+/*****************************************************************************/
diff --git a/arch/arm/mach-tegra/nvrm/core/common/nvrm_power_dfs.h b/arch/arm/mach-tegra/nvrm/core/common/nvrm_power_dfs.h
new file mode 100644
index 000000000000..65137c83a8ce
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/core/common/nvrm_power_dfs.h
@@ -0,0 +1,576 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/** 
+ * @file
+ * @brief <b>nVIDIA Driver Development Kit: 
+ *           Power Resource manager </b>
+ *
+ * @b Description: NvRM DFS manager definitions. 
+ * 
+ */
+
+#ifndef INCLUDED_NVRM_POWER_DFS_H
+#define INCLUDED_NVRM_POWER_DFS_H
+
+#include "nvrm_power_private.h"
+#include "nvrm_clocks.h"
+#include "nvrm_interrupt.h"
+#include "nvodm_tmon.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif  /* __cplusplus */
+
+/**
+ * Sampling window definitions:
+ * - minimum and maximum sampling interval in ms
+ * - maximum number of intervals in the sampling window
+ * (always defined as power of 2 to simplify calculations)
+ */
+#define NVRM_DFS_MIN_SAMPLE_MS (10)
+#define NVRM_DFS_MAX_SAMPLE_MS (20)
+
+#define NVRM_DFS_MAX_SAMPLES_LOG2 (7)
+#define NVRM_DFS_MAX_SAMPLES (0x1 << NVRM_DFS_MAX_SAMPLES_LOG2)
+
+/// Specifies that CPU idle monitor readings should be explicitly offset
+///  by time spent in LP2
+#define NVRM_CPU_IDLE_LP2_OFFSET (1)
+
+/// Number of bits in the fractional part of boost koefficients
+#define BOOST_FRACTION_BITS (8)
+
+/*****************************************************************************/
+
+/// Enumerates synchronous busy hints states
+typedef enum
+{
+    NvRmDfsBusySyncState_Idle = 0,
+    NvRmDfsBusySyncState_Signal,
+    NvRmDfsBusySyncState_Execute,
+
+    NvRmDfsBusySyncState_Num,
+    NvRmDfsBusySyncState_Force32 = 0x7FFFFFFF
+} NvRmDfsBusySyncState;
+
+/// Enumerates DFS modules = modules, which include activity monitors for clock
+/// domains controlled by DFS
+typedef enum
+{
+    // Specifies system statistic module - includes activity monitors
+    // for CPU, AVP, AHB, and APB clock domains
+    NvRmDfsModuleId_Systat = 1,
+
+    // Specifies VDE module - includes activity monitor
+    // for video-pipe clock domain
+    NvRmDfsModuleId_Vde,
+
+    // Specifies EMC module - includes activity monitor
+    // for EMC 1x clock domain
+    NvRmDfsModuleId_Emc,
+
+    NvRmDfsModuleId_Num,
+    NvRmDfsModuleId_Force32 = 0x7FFFFFFF
+} NvRmDfsModuleId;
+
+/**
+ * Combines idle count readings from DFS activity monitors during current
+ * sample interval
+ */
+typedef struct NvRmDfsIdleDataRec
+{
+    // Current Sample interval in ms
+    NvU32 CurrentIntervalMs;
+
+    // Data readings from DFS activity monitors
+    NvU32 Readings[NvRmDfsClockId_Num];
+
+    // Time spent in LP2 in ms
+    NvU32 Lp2TimeMs;
+} NvRmDfsIdleData;
+
+/**
+ *  DFS module access function pointers
+ */
+typedef struct NvRmDfsRec* NvRmDfsPtr;
+typedef const struct NvRmDfsRec* NvRmConstDfsPtr;
+typedef NvError (*FuncPtrModuleMonitorsInit)(NvRmDfsPtr pDfs);
+typedef void (*FuncPtrModuleMonitorsDeinit)(NvRmDfsPtr pDfs);
+
+typedef void
+(*FuncPtrModuleMonitorsStart)(
+    NvRmConstDfsPtr pDfs,
+    const NvRmDfsFrequencies* pDfsKHz,
+    const NvU32 IntevalMs);
+
+typedef void
+(*FuncPtrModuleMonitorsRead)(
+    NvRmConstDfsPtr pDfs,
+    const NvRmDfsFrequencies* pDfsKHz,
+    NvRmDfsIdleData* pIdleData);
+
+/**
+ * Combines capabilities, access function pointers, and base virtual
+ * addresses of the DFS module
+ */
+typedef struct NvRmDfsModuleRec
+{
+    // Clock domains monitored by this module 
+    NvBool DomainMap[NvRmDfsClockId_Num];
+
+    // Pointer to the function that initializes module activity monitors
+    // (null if module is not present)
+    FuncPtrModuleMonitorsInit Init;
+
+    // Pointer to the function that de-initializes module activity monitors
+    // (null if module is not present)
+    FuncPtrModuleMonitorsDeinit Deinit;
+
+    // Pointer to the function that starts module activity monitors
+    // (null if module is not present)
+    FuncPtrModuleMonitorsStart Start;
+
+    // Pointer to the function that reads module activity monitors
+    // (null if module is not present)
+    FuncPtrModuleMonitorsRead Read;
+
+    // Monitor readouts scale and offset (usage and interpretation may differ
+    // for different monitors)
+    NvU32 Scale;
+    NvU32 Offset;
+
+    // Base virtual address for module registers
+    void* pBaseReg;
+} NvRmDfsModule;
+
+/*****************************************************************************/
+
+/**
+ * Combines DFS starvation control parameters
+ */
+typedef struct NvRmDfsStarveParamRec
+{
+    // Fixed increase in frequency boost for a sample interval the clock
+    // consumer is starving: new boost = old boost +  BoostStepKHz
+    NvRmFreqKHz BoostStepKHz;
+
+    // Proportional increase in frequency boost for a sample interval the
+    // clock consumer is starving (scaled in 0-255 range):
+    // new boost = old boost + old boost * BoostIncKoef / 256
+    NvU8 BoostIncKoef;
+
+    // Proportional decrease in frequency boost for a sample interval the
+    // clock consumer is not starving (scaled in 0-255 range):
+    // new boost = old boost - old boost * BoostDecKoef / 256
+    NvU8 BoostDecKoef;
+} NvRmDfsStarveParam;
+
+
+/**
+ * Combines scaling algorithm parameters for DFS controlled clock domain
+ */
+typedef struct NvRmDfsParamRec
+{
+    // Maximum domain clock frequency
+    NvRmFreqKHz MaxKHz;
+    // Minimum domain clock frequency
+    NvRmFreqKHz MinKHz;
+
+    // Minimum average activity change in upward direction recognized by DFS
+    NvRmFreqKHz UpperBandKHz;
+    // Minimum average activity change in downward direction recognized by DFS
+    NvRmFreqKHz LowerBandKHz;
+
+    // Control parameters for real time starvation reported by the DFS client
+    NvRmDfsStarveParam RtStarveParam;
+
+    // Control parameters for non real time starvation detected by DFS itself
+    NvRmDfsStarveParam NrtStarveParam;
+
+    // Relative adjustment up of average activity applied by DFS:
+    // adjusted frequency = measured average activity * (1 + 2^(-RelAdjustBits))
+    NvU8 RelAdjustBits;
+
+    // Minimum number of sample intervals in a row with non-realtime starvation
+    // that triggers frequency boost (0 = boost trigger on the 1st NRT interval)
+    NvU8 MinNrtSamples;
+
+    // Minimum number of idle cycles in the sample interval required to avoid
+    // non-realtime starvation
+    NvU32 MinNrtIdleCycles;
+} NvRmDfsParam;
+
+/**
+ * Combines sampling statistic and starvation controls for DFS clock domain
+ */
+typedef struct NvRmDfsSamplerRec
+{
+    // Domain clock id
+    NvRmDfsClockId ClockId;
+
+    // Activity monitor present indicator (domain is still controlled by DFS
+    // even if no activity monitor present)
+    NvBool MonitorPresent;
+
+    // Circular buffer of active cycles per sample interval within the
+    // sampling window
+    NvU32 Cycles[NVRM_DFS_MAX_SAMPLES];
+
+    // Pointer to the last ("recent") sample in the sampling window
+    NvU32* pLastSample;
+
+    // Total number of active cycles in the sampling window
+    NvU64 TotalActiveCycles;
+
+    // Measured average clock activity frequency over the sampling window
+    NvRmFreqKHz AverageKHz;
+
+    // Average clock frequency adjusted up by DFS
+    NvRmFreqKHz BumpedAverageKHz;
+
+    // Non-real time starving sample counter
+    NvU32 NrtSampleCounter;
+
+    // Non-real time starvation boost 
+    NvRmFreqKHz NrtStarveBoostKHz;
+
+    // Real time starvation boost 
+    NvRmFreqKHz RtStarveBoostKHz;
+
+    // Busy pulse mode indicator - if true, busy boost is completely removed
+    // after busy time has expired; if false, DFS averaging mechanism is used
+    // to gradually lower frequency after busy boost
+    NvBool BusyPulseMode;
+
+    // Cumulative number of cycles since log start
+    NvU64 CumulativeLogCycles;
+} NvRmDfsSampler;
+
+/**
+ * Holds information for DFS moving sampling window
+ */
+typedef struct NvRmDfsSampleWindowRec
+{
+    // Minimum sampling interval
+    NvU32 MinIntervalMs;
+
+    // Maximum sampling interval
+    NvU32 MaxIntervalMs;
+
+    // Next sample interval
+    NvU32 NextIntervalMs;
+
+    // Circular buffer of sample intervals in the sampling window
+    NvU32 IntervalsMs[NVRM_DFS_MAX_SAMPLES];
+
+    // Pointer to the last ("recent") sample unterval in the sampling window
+    NvU32* pLastInterval;
+
+    // Cumulative width of the sampling window
+    NvU32 SampleWindowMs;
+
+    // Last busy hints check time stamp
+    NvU32 BusyCheckLastUs;
+
+    // Delay before busy hints next check
+    NvU32 BusyCheckDelayUs;
+
+    // Free running sample counter
+    NvU32 SampleCnt;
+
+    // Cumulative DFS time since log start
+    NvU32 CumulativeLogMs;
+
+    // Cumulative LP2 statistic since log start
+    NvU32 CumulativeLp2TimeMs;
+    NvU32 CumulativeLp2Entries;
+} NvRmDfsSampleWindow;
+
+/*****************************************************************************/
+
+/**
+ * Holds voltage corner for DFS domains and non-DFS modules. Each voltage
+ * corner field specifies minimum core voltage required to run the respective
+ * device(s) at current clock frequency.
+ */
+typedef struct NvRmDvsCornerRec
+{
+    // CPU voltage requirements
+    NvRmMilliVolts CpuMv;
+
+    // AVP/System voltage requirements
+    NvRmMilliVolts SystemMv;
+
+    // EMC / DDR voltage requirements
+    NvRmMilliVolts EmcMv;
+
+    // Cumulative voltage requirements for non-DFS modules
+    NvRmMilliVolts ModulesMv;
+} NvRmDvsCorner;
+
+/**
+ * Combines voltage threshold and core rail status and control information
+ */
+typedef struct NvRmDvsRec
+{
+    // Current DVS voltage thresholds
+    NvRmDvsCorner DvsCorner;
+
+    // RTC (AO) rail address (PMU voltage id)
+    NvU32 RtcRailAddress;
+
+    // Core rail address (PMU voltage id)
+    NvU32 CoreRailAddress;
+
+    // Current core rail voltage
+    NvRmMilliVolts CurrentCoreMv;
+
+    // Nominal core rail voltage
+    NvRmMilliVolts NominalCoreMv;
+
+    // Minimum core rail voltage
+    NvRmMilliVolts MinCoreMv;
+
+    // Low corner voltage for core rail loaded by DVS control API
+    NvRmMilliVolts LowCornerCoreMv;
+
+    // Dedicated Cpu rail address (PMU voltage id)
+    NvU32 CpuRailAddress;
+
+    // Current dedicated CPU rail voltage
+    NvRmMilliVolts CurrentCpuMv;
+
+    // Nominal dedicated CPU rail voltage
+    NvRmMilliVolts NominalCpuMv;
+
+    // Minimum dedicated CPU rail voltage
+    NvRmMilliVolts MinCpuMv;
+
+    // Low corner voltage for CPU rail loaded by DVS control API
+    NvRmMilliVolts LowCornerCpuMv;
+
+    // OTP (default) dedicated CPU rail voltage
+    NvRmMilliVolts CpuOTPMv;
+
+    // Specifies whether or not CPU voltage will switch back to OTP
+    // (default) value after CPU request On-Off-On transition
+    NvBool  VCpuOTPOnWakeup;
+
+    // RAM timing SVOP controls low voltage threshold
+    NvRmMilliVolts LowSvopThresholdMv;
+
+    // RAM timing SVOP controls low voltage setting
+    NvU32 LowSvopSettings;
+
+    // RAM timing SVOP controls high voltage setting
+    NvU32 HighSvopSettings;
+
+    // Request core voltage update
+    volatile NvBool UpdateFlag;
+
+    // Stop voltage scaling flag
+    volatile NvBool StopFlag;
+
+    // CPU LP2 state indicator (used on platforms with dedicated CPU rail that
+    // returns to default setting by PMU underneath DVFS on every LP2 exit)
+    volatile NvBool Lp2SyncOTPFlag;
+} NvRmDvs;
+
+/**
+ * RM thermal zone policy
+ */
+typedef struct NvRmTzonePolicyRec
+{
+    // Request policy update
+    volatile NvBool UpdateFlag;
+
+    // Last policy update request time stamp
+    NvU32 TimeUs;
+
+    // Update period (NV_WAIT_INFINITE is allowed in interrupt mode) 
+    NvU32 UpdateIntervalUs;
+
+    // Out of limit interrupt boundaries
+    NvS32 LowLimit;
+    NvS32 HighLimit;
+
+    // Policy range
+    NvU32 PolicyRange;
+} NvRmTzonePolicy;
+
+/**
+ * Combines status and control information for dynamic thermal throttling
+ */
+typedef struct NvRmDttRec
+{
+    // SoC core temperature monitor (TMON) handle
+    NvOdmTmonDeviceHandle hOdmTcore;
+
+    // Core TMON out-of-limit-interrupt handle
+    NvOdmTmonIntrHandle hOdmTcoreIntr;
+
+    // Core TMON capabilities
+    NvOdmTmonCapabilities TcoreCaps;
+
+    // Out of limit interrupt cpabilities for low limit
+    NvOdmTmonParameterCaps TcoreLowLimitCaps;
+
+    // Out-of-limit interrupt cpabilities for high limit
+    NvOdmTmonParameterCaps TcoreHighLimitCaps;
+
+    // Core zone policy
+    NvRmTzonePolicy TcorePolicy;
+
+    // Core temperature
+    NvS32 CoreTemperatureC;
+
+    // Specifies if out-of-limit interrupt is used for temperature update
+    volatile NvBool UseIntr;
+} NvRmDtt;
+
+/*****************************************************************************/
+
+/**
+ * Combines DFS status and control information
+ */
+typedef struct NvRmDfsRec
+{
+    // RM Device handle
+    NvRmDeviceHandle hRm;
+
+    // DFS state variable
+    NvRmDfsRunState DfsRunState;
+
+    // DFS state saved on system suspend entry
+    NvRmDfsRunState DfsLPxSavedState;
+
+    // ID assigned to DFS by RM Power Manager
+    NvU32 PowerClientId;
+
+    // DFS low power corner hit status - true, when all domains (with
+    // possible exception of CPU) are running at minimum frequency
+    NvBool LowCornerHit;
+
+    // Request to report low corner hit status to OS adaptation layer; DFS
+    // interrupt will not wake CPU if it is power gated and low corner is hit
+    NvBool LowCornerReport;
+
+    // PM thread request for CPU state control
+    NvRmPmRequest PmRequest;
+
+    // DFS IRQ number
+    NvU16 IrqNumber;
+
+    // DFS mutex for safe data access by DFS ISR,
+    // clock control thread, and API threads
+    NvOsIntrMutexHandle hIntrMutex;
+
+    // DFS mutex for synchronous busy hints
+    NvOsMutexHandle hSyncBusyMutex;
+
+    // DFS semaphore for synchronous busy hints
+    NvOsSemaphoreHandle hSyncBusySemaphore;
+
+    // Synchronous busy hints state
+    volatile NvRmDfsBusySyncState BusySyncState;
+
+    // Clock control execution thread init indicator
+    volatile NvBool InitializedThread;
+
+    // Clock control execution thread abort indicator
+    volatile NvBool AbortThread;
+
+    // DFS semaphore for sampling interrupt and wake event signaling
+    NvOsSemaphoreHandle hSemaphore;
+
+    // DFS Modules
+    NvRmDfsModule Modules[NvRmDfsModuleId_Num];
+
+    // DFS algorithm parameters 
+    NvRmDfsParam DfsParameters[NvRmDfsClockId_Num];
+
+    // DFS Samplers
+    NvRmDfsSampler Samplers[NvRmDfsClockId_Num];
+
+    // DFS sampling window
+    NvRmDfsSampleWindow SamplingWindow;
+
+    // Maximum DFS domains frequencies (shortcut to the respective parameters)
+    NvRmDfsFrequencies MaxKHz;
+
+    // Target DFS doamins frequencies: output of the DFS algorithm,
+    // input to clock control
+    NvRmDfsFrequencies TargetKHz;
+
+    // Current DFS domains frequencies: output from clock control, input
+    // to DFS algorithm
+    NvRmDfsFrequencies CurrentKHz;
+
+    // DFS domains frequencies set on entry to suspend state
+    NvRmDfsFrequencies SuspendKHz;
+
+    // Busy boost frequencies requested by Busy load API
+    NvRmDfsFrequencies BusyKHz;
+
+    // Low corner frequencies loaded by DFS control API
+    NvRmDfsFrequencies LowCornerKHz;
+
+    // High corner frequencies loaded by DFS control API
+    NvRmDfsFrequencies HighCornerKHz;
+
+    // A shadow of CPU corners (updated by APIs that directly set CPU corners,
+    // preserved when CPU corners are indirectly throttled by EMC envelope)
+    NvRmModuleClockLimits CpuCornersShadow;
+
+    // CPU envelope API indicator (if set supercedes low/high corner APIs)
+    NvBool CpuEnvelopeSet;
+
+    // EMC envelope API indicator (if set supercedes low/high corner APIs)
+    NvBool EmcEnvelopeSet;
+
+    // Voltage Scaler
+    NvRmDvs VoltageScaler;
+
+    // Thermal throttler
+    NvRmDtt ThermalThrottler;
+
+    // nvos interrupt handle for DVS 
+    NvOsInterruptHandle DfsInterruptHandle;
+} NvRmDfs;
+
+#ifdef __cplusplus
+}
+#endif  /* __cplusplus */
+
+#endif // INCLUDED_NVRM_POWER_DFS_H
diff --git a/arch/arm/mach-tegra/nvrm/core/common/nvrm_priv_ap_general.h b/arch/arm/mach-tegra/nvrm/core/common/nvrm_priv_ap_general.h
new file mode 100644
index 000000000000..ded480bdb41d
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/core/common/nvrm_priv_ap_general.h
@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+ /** @file
+  *
+  * @b Description: Contains the maximum instance of the controller on soc.
+  * Must be >= the max of all chips.
+  */
+
+#ifndef INCLUDED_NVRM_PRIV_AP_GENERAL_H
+#define INCLUDED_NVRM_PRIV_AP_GENERAL_H
+
+
+// Dma specific definitions for latest SOC
+
+// Maximum number of DMA channels available on SOC.
+#define MAX_APB_DMA_CHANNELS        32
+
+
+// SPI specific definitions for latest SOC
+#define MAX_SPI_CONTROLLERS         8
+
+#define MAX_SLINK_CONTROLLERS       8
+
+
+// I2C specific definitions for latest soc
+#define MAX_I2C_CONTROLLERS         3
+
+#define MAX_DVC_CONTROLLERS         1
+
+#endif // INCLUDED_NVRM_PRIV_AP_GENERAL_H
diff --git a/arch/arm/mach-tegra/nvrm/core/common/nvrm_processor.h b/arch/arm/mach-tegra/nvrm/core/common/nvrm_processor.h
new file mode 100644
index 000000000000..48c8f57e9f64
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/core/common/nvrm_processor.h
@@ -0,0 +1,145 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_NVRM_PROCESSOR_H
+#define INCLUDED_NVRM_PROCESSOR_H
+
+#include "nvcommon.h"
+
+#ifdef  __cplusplus
+extern "C" {
+#endif
+
+
+//==========================================================================
+//  ARM CPSR/SPSR definitions
+//==========================================================================
+
+#define PSR_MODE_MASK   0x1F
+#define PSR_MODE_USR    0x10
+#define PSR_MODE_FIQ    0x11
+#define PSR_MODE_IRQ    0x12
+#define PSR_MODE_SVC    0x13
+#define PSR_MODE_ABT    0x17
+#define PSR_MODE_UND    0x1B
+#define PSR_MODE_SYS    0x1F    // only available on ARM Arch. v4 and higher
+#define PSR_MODE_MON    0x16    // only available on ARM Arch. v6 and higher with TrustZone extension
+
+
+//==========================================================================
+// Compiler-independent abstraction macros.
+//==========================================================================
+
+#define IS_USER_MODE(cpsr)  ((cpsr & PSR_MODE_MASK) == PSR_MODE_USR)
+
+//==========================================================================
+// Compiler-specific instruction abstraction macros.
+//==========================================================================
+
+#if defined(__arm__) && !defined(__thumb__)  // ARM compiler compiling ARM code
+
+    #if (__GNUC__) // GCC inline assembly syntax
+
+    static NV_INLINE NvU32
+    CountLeadingZeros(NvU32 x)
+    {
+        NvU32 count;
+        __asm__ __volatile__ (      \
+                "clz %0, %1 \r\t"   \
+                :"=r"(count)        \
+                :"r"(x));
+        return count;
+    }
+
+    #define GET_CPSR(x) __asm__ __volatile__ (          \
+                                "mrs %0, cpsr\r\t"     \
+                                : "=r"(x))
+
+    #else   // assume RVDS compiler
+    /*
+     *  @brief Macro to abstract retrieval of the current processor 
+     *  status register (CPSR) value.
+     *  @param x is a variable of type NvU32 that will receive 
+     *  the CPSR value.
+     */
+    #define GET_CPSR(x) __asm { MRS x, CPSR }           // x = CPSR
+    
+    static NV_INLINE NvU32
+    CountLeadingZeros(NvU32 x)
+    {
+        NvU32 count;
+        __asm { CLZ count, x }
+        return count;
+    }
+
+    #endif
+#else
+    /*
+     *  @brief Macro to abstract retrieval of the current processor status register (CPSR) value.
+     *  @param x is a variable of type NvU32 that will receive the CPSR value.
+    */
+    #define GET_CPSR(x) (x = PSR_MODE_USR)  // Always assume USER mode for now
+
+    // If no built-in method for counting leading zeros do it the less efficient way.
+    static NV_INLINE NvU32 
+    CountLeadingZeros(NvU32 x)
+    {
+        NvU32   i;
+
+        if (x)
+        {
+            i = 0;
+
+            do
+            {
+                if (x & 0x80000000)
+                {
+                    break;
+                }
+                x <<= 1;
+            } while (++i < 32);
+        }
+        else
+        {
+            i = 32;
+        }
+
+        return i;
+    }
+
+#endif
+
+#ifdef  __cplusplus
+}
+#endif
+
+#endif // INCLUDED_NVRM_PROCESSOR_H
diff --git a/arch/arm/mach-tegra/nvrm/core/common/nvrm_relocation_table.c b/arch/arm/mach-tegra/nvrm/core/common/nvrm_relocation_table.c
new file mode 100644
index 000000000000..5628d3e24ec3
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/core/common/nvrm_relocation_table.c
@@ -0,0 +1,681 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include "nvcommon.h"
+#include "nvos.h"
+#include "nvassert.h"
+#include "nvrm_relocation_table.h"
+#include "nvrm_hardware_access.h"
+#include "nvrm_module.h"
+#include "nvrm_moduleids.h"
+#include "nvrm_hw_devids.h"
+
+#define NVRM_ENABLE_PRINTF  0 // Module debug: 0=disable, 1=enable
+
+#if (NV_DEBUG && NVRM_ENABLE_PRINTF)
+#define NVRM_MODULE_PRINTF(x)   NvOsDebugPrintf x
+#else
+#define NVRM_MODULE_PRINTF(x)
+#endif
+
+// Relocation table unpacking macros
+#define DEVICE_ID( i )          ( ( (i) & ( 0xFFFFUL << 16 ) ) >> 16 )
+#define DEVICE_MAJOR_REV( i )   ( ( (i) & ( 0xFUL    << 12 ) ) >> 12 )
+#define DEVICE_MINOR_REV( i )   ( ( (i) & ( 0xFUL    << 8  ) ) >> 8  )
+#define DEVICE_POWER_GROUP( i ) ( ( (i) & ( 0xFUL    << 4  ) ) >> 4  )
+#define DEVICE_BAR( i )         ( ( (i) & ( 0xFUL          ) ) )
+#define IRQ_VALID( i )          ( (i) >> 31 )
+#define IRQ_TARGET( i )         ( ( (i) & ( 0x3UL    << 29 ) ) >> 29 )
+#define IRQ_INT_DEV_INDEX( i )  ( ( (i) & ( 0x1FFUL  << 20 ) ) >> 20 )
+#define IRQ_DEVICE_INDEX( i )   ( ( (i) & ( 0xFFUL   << 8  ) ) >> 8  )
+#define IRQ_INT_NUM(i)          ( (i) & 0xFFul )
+
+NvRmModuleInstance s_InstanceTable[NVRM_MAX_MODULE_INSTANCES];
+
+/**
+ * Maps relocation table device ids to software module ids.
+ * NVRM_DEVICE_UNKNOWN for unknown ids (will keep parsing table), 
+ * or NVRM_DEVICE_ERROR if something bad happened
+ * (will stop parsing the table).
+ *
+ * NVRM_DEVICE_UNKOWN can be used to cull the device list to save space by
+ * not allocating memory for devices that won't be used.
+ */
+NvU32
+NvRmPrivDevToModuleID(NvU32 devid)
+{
+    switch( devid ) {
+    /* actual module with registers */
+    case NVRM_DEVID_AC97:
+        return NvRmModuleID_Ac97;
+    case NVRM_DEVID_APB_DMA:
+        return NvRmPrivModuleID_ApbDma;
+    case NVRM_DEVID_APB_DMA_CH:
+        return NvRmPrivModuleID_ApbDmaChannel;
+    case NVRM_DEVID_ARB_PRI:
+        return NvRmModuleID_ArbPriority;
+    case NVRM_DEVID_ARB_SEM:
+        return NvRmModuleID_ArbitrationSema;
+    case NVRM_DEVID_CAR:
+        return NvRmPrivModuleID_ClockAndReset;
+    case NVRM_DEVID_CC:
+        return NvRmPrivModuleID_CC;
+    case NVRM_DEVID_CMC:
+        return NvRmModuleID_CacheMemCtrl;
+    case NVRM_DEVID_BSEA:
+    case NVRM_DEVID_AVPBSEA:
+        /* Module name changed to NVRM_DEVID_AVPBSEA in AP20 */
+        return NvRmModuleID_BseA;
+    case NVRM_DEVID_VDE:
+        return NvRmModuleID_Vde;
+    case NVRM_DEVID_CPU_INTR:
+        return NvRmPrivModuleID_InterruptCpu;
+    case NVRM_DEVID_DISPLAY:
+        return NvRmModuleID_Display;
+    case NVRM_DEVID_DSI:
+        return NvRmModuleID_Dsi;
+    case NVRM_DEVID_DVC:
+        return NvRmModuleID_Dvc;
+    case NVRM_DEVID_EIDE:
+        return NvRmModuleID_Ide;
+    case NVRM_DEVID_EMC:
+        return NvRmPrivModuleID_ExternalMemoryController;
+    case NVRM_DEVID_EPP:
+        return NvRmModuleID_Epp;
+    case NVRM_DEVID_EVENT:
+        return NvRmModuleID_EventCtrl;
+    case NVRM_DEVID_FLOW:
+        return NvRmModuleID_FlowCtrl;
+    case NVRM_DEVID_FUSE:
+        return NvRmModuleID_Fuse;
+    case NVRM_DEVID_KFUSE:
+        return NvRmModuleID_KFuse;
+    case NVRM_DEVID_GPIO:
+        return NvRmPrivModuleID_Gpio;
+    case NVRM_DEVID_GR2D:
+        return NvRmModuleID_2D;
+    case NVRM_DEVID_GR3D:
+        return NvRmModuleID_3D;
+    case NVRM_DEVID_HDMI:
+        return NvRmModuleID_Hdmi;
+    case NVRM_DEVID_HOST1X:
+        return NvRmModuleID_GraphicsHost;
+    case NVRM_DEVID_HSMMC:
+        return NvRmModuleID_Hsmmc;
+    case NVRM_DEVID_I2C:
+        return NvRmModuleID_I2c;
+    case NVRM_DEVID_I2S:
+        return NvRmModuleID_I2s;
+    case NVRM_DEVID_ICTLR:
+        return NvRmPrivModuleID_Interrupt;
+    case NVRM_DEVID_ICTLR_ARBGNT:
+        return NvRmPrivModuleID_InterruptArbGnt;
+    case NVRM_DEVID_ICTLR_DRQ:
+        return NvRmPrivModuleID_InterruptDrq;
+    case NVRM_DEVID_ISP:
+        return NvRmModuleID_Isp;
+    case NVRM_DEVID_KBC:
+        return NvRmModuleID_Kbc;
+    case NVRM_DEVID_MC:
+        return NvRmPrivModuleID_MemoryController;
+    case NVRM_DEVID_MIPI_HS:
+        return NvRmModuleID_Mipi;
+    case NVRM_DEVID_MISC:
+        return NvRmModuleID_Misc;
+    case NVRM_DEVID_MPE:
+        return NvRmModuleID_Mpe;
+    case NVRM_DEVID_MSELECT:
+        return NvRmPrivModuleID_Mselect;
+    case NVRM_DEVID_NANDFLASH:
+        return NvRmModuleID_Nand;
+    case NVRM_DEVID_PMIF:
+        return NvRmModuleID_Pmif;
+    case NVRM_DEVID_PWFM:
+        return NvRmModuleID_Pwm;
+    case NVRM_DEVID_RTC:
+        return NvRmModuleID_Rtc;
+    case NVRM_DEVID_SDMMC:
+    case NVRM_DEVID_SDIO:
+        return NvRmModuleID_Sdio;
+    case NVRM_DEVID_SHR_SEM:
+        return NvRmModuleID_ResourceSema;
+
+    // Supporting only the slink controller for now, returning error for old
+    // slink controller.
+    case NVRM_DEVID_SLINK:
+        return NvRmModuleID_Slink;
+    case NVRM_DEVID_SPDIF:
+        return NvRmModuleID_Spdif;
+    case NVRM_DEVID_SPI:
+        return NvRmModuleID_Spi;
+    case NVRM_DEVID_STAT:
+        return NvRmModuleID_SysStatMonitor;
+    case NVRM_DEVID_SW_INTR:
+        return NvRmPrivModuleID_InterruptSw;
+    case NVRM_DEVID_TMR:
+        return NvRmModuleID_Timer;
+    case NVRM_DEVID_TMRUS:
+        return NvRmModuleID_TimerUs;
+    case NVRM_DEVID_TVO:
+        return NvRmModuleID_Tvo;
+    case NVRM_DEVID_TWC:
+        return NvRmModuleID_Twc;
+    case NVRM_DEVID_UART:
+        return NvRmModuleID_Uart;
+    case NVRM_DEVID_UCQ:
+        return NvRmModuleID_Ucq;
+    case NVRM_DEVID_AVPUCQ:
+        return NvRmModuleID_AvpUcq;
+    case NVRM_DEVID_USB:
+        return NvRmModuleID_Usb2Otg;
+    case NVRM_DEVID_VCP:
+        return NvRmModuleID_Vcp;
+    case NVRM_DEVID_VECTOR:
+        // FIXME: does this make sense?
+        return NvRmModuleID_ExceptionVector;
+    case NVRM_DEVID_VFIR:
+        return NvRmModuleID_Vfir;
+    case NVRM_DEVID_VI:
+        return NvRmModuleID_Vi;
+    case NVRM_DEVID_XIO:
+        return NvRmModuleID_Xio;
+    case NVRM_DEVID_UPTAG:
+        return NvRmPrivModuleID_ProcId;
+    case NVRM_DEVID_AHB_ARBC:
+        return NvRmPrivModuleID_Ahb_Arb_Ctrl;
+
+    /* memory (internal, external, etc - no registers) */
+    case NVRM_DEVID_EMEM:
+        return NvRmPrivModuleID_ExternalMemory;
+
+    case NVRM_DEVID_IMEM:
+        return NvRmPrivModuleID_InternalMemory;
+
+    case NVRM_DEVID_TCRAM:
+        return NvRmPrivModuleID_Tcram;
+
+    case NVRM_DEVID_IRAM:
+        return NvRmPrivModuleID_Iram;
+
+    case NVRM_DEVID_GART:
+        return NvRmPrivModuleID_Gart;
+
+    case NVRM_DEVID_EXIO:
+        return NvRmPrivModuleID_Mio_Exio;
+
+    case NVRM_DEVID_PMU_EXT:
+         return NvRmPrivModuleID_PmuExt;
+            
+    case NVRM_DEVID_NOR:
+        return NvRmModuleID_Nor;
+
+    case NVRM_DEVID_CSI:
+        return NvRmModuleID_Csi;
+
+    case NVRM_DEVID_OWR:
+        return NvRmModuleID_OneWire;
+    case NVRM_DEVID_SNOR:
+        return NvRmModuleID_SyncNor;
+
+    case NVRM_DEVID_ARM_PERIPH:
+        return NvRmPrivModuleID_ArmPerif;
+
+    case NVRM_DEVID_ARM_ICTLR:
+        return NvRmPrivModuleID_ArmInterruptctrl;
+
+    case NVRM_DEVID_PCIE:
+        return NvRmPrivModuleID_Pcie;
+
+    case NVRM_DEVID_AHB_EMEM:
+        return NvRmPrivModuleID_AhbRemap;
+
+    case NVRM_DEVID_ARM_PL310:
+        return NvRmPrivModuleID_Pl310;
+
+    /* unknown or don't care */
+    default:
+        return NVRM_DEVICE_UNKNOWN;
+    }
+}
+
+static NvError
+NvRmPrivParseDevices( const NvU32 *table,
+    NvRmModuleInstance **instances,
+    NvRmModuleInstance **instanceLast,
+    NvRmModule *modules )
+{
+    NvError ret = NvSuccess;
+    NvU32 info;
+    NvU32 devid;
+    NvS32 index;
+    NvU32 count;
+    NvU8 devidx;
+    NvRmModuleInstance *inst = 0;
+    NvU32 modid;
+    NvU32 start;
+    NvU32 length;
+    NvS32 tmp_index;
+    NvU32 tmp_devid;
+    NvU8 tmp_devidx;
+    NvBool skip;
+
+    /* The first 32 bits of the table is the table version number */
+    index = 1;
+
+    /* count the total number of devices and allocate space for them.
+     * for each device, check if the device has already been found (multiply
+     * instantiated), if this is the first device instance, then find
+     * all of the rest of the devices to compact all devices together.
+     *
+     * after the module instances have been compacted, count the number of
+     * unique non-memory device ids and setup the module index table.
+     *
+     * only count devices that the NvRmPrivDevToModuleID function returns a
+     * valid module id for (don't count memory or unknown devices).  it is ok
+     * for NvRmPrivDevToModuleID to return unknown for devices it doesn't care
+     * about.
+     */
+    count = 0;
+    while( NV_READ32( &table[index] ) )
+    {
+        info = NV_READ32( &table[index] );
+        devid = DEVICE_ID( info );
+        modid = NvRmPrivDevToModuleID(devid);
+        if( modid != NVRM_DEVICE_UNKNOWN )
+        {
+            count++;
+        }
+
+        if( modid == NVRM_DEVICE_ERROR )
+        {
+            NV_ASSERT( !"relocation table parsing error" );
+            goto fail;
+        }
+
+        index += 3;
+    }
+
+    /* reset index to the first device */
+    index = 1;
+
+    /* Use Instance array */
+    inst = s_InstanceTable;
+    /* Make sure we are not over stepping the array boundaries */
+    NV_ASSERT(NVRM_MAX_MODULE_INSTANCES >= (count + 1));
+
+    *instances = inst;
+    devidx = (NvU8)-1;      /* -1 is the invalid/unavailable indicator */
+
+    /* pass over the relocation table again to fill in the instance table */
+    while( NV_READ32( &table[index] ) )
+    {
+        skip = NV_FALSE;
+        info = NV_READ32( &table[index++] );
+        start = NV_READ32( &table[index++] );
+        length = NV_READ32( &table[index++] );
+        devidx++;
+
+        devid = DEVICE_ID( info );
+        modid = NvRmPrivDevToModuleID( devid );
+
+        if( modid == NVRM_DEVICE_UNKNOWN )
+        {
+            /* keep going */
+            NVRM_MODULE_PRINTF(( "[Unknwn] devidx: %d devid: %d start: 0x%x "
+                "length: 0x%x\n", devidx, devid, start, length ));
+            continue;
+        }
+        else if( modid == NVRM_DEVICE_ERROR )
+        {
+            NVRM_MODULE_PRINTF(( "[Error] devidx: %d devid: %d start: 0x%x "
+                "length: 0x%x\n", devidx, devid, start, length ));
+            NV_ASSERT( !"relocation table parsing failure" );
+            goto fail;
+        }
+
+        /* search backwards to detect an already found instance */
+        tmp_index = index - 6;
+        while( tmp_index > 1 )
+        {
+            tmp_devid = DEVICE_ID( NV_READ32( &table[tmp_index] ) );
+            if( tmp_devid == devid )
+            {
+                skip = NV_TRUE;
+                break;
+            }
+
+            tmp_index -= 3;
+        }
+
+        /* already found this instance, continue to the next device */
+        if( skip )
+        {
+            continue;
+        }
+
+        /* scan forward to find all instances of this devid */
+        tmp_devid = devid;
+        tmp_index = index;
+        tmp_devidx = devidx;
+        for( ;; )
+        {
+            if( tmp_devid == devid )
+            {
+                inst->PhysAddr = start;
+                inst->Length = length;
+                inst->MajorVersion = (NvU8)DEVICE_MAJOR_REV(info);
+                inst->MinorVersion = (NvU8)DEVICE_MINOR_REV(info);
+                inst->DevPowerGroup = (NvU8)DEVICE_POWER_GROUP(info);
+                inst->Bar = (NvU8)DEVICE_BAR(info);
+                inst->VirtAddr = 0;
+                inst->DeviceId = devid;
+                inst->DevIdx = tmp_devidx;
+
+                NVRM_MODULE_PRINTF(( "[Device] devidx: %d devid: %d "
+                    "addr: 0x%x length: 0x%x major: %d minor: %d\n",
+                    tmp_devidx, devid, start, length,
+                    inst->MajorVersion, inst->MinorVersion ));
+
+                NV_ASSERT( tmp_devidx < (NvU8)-1 );
+                    /* (NvU8)-1 is the indicator for invalid/unavailable
+                       instance and safeguard against overflow on idx too. */
+
+                inst++;
+            }
+
+            if( !NV_READ32( &table[tmp_index] ) )
+            {
+                break;
+            }
+
+            info = NV_READ32( &table[tmp_index++] );
+            start = NV_READ32( &table[tmp_index++] );
+            length = NV_READ32( &table[tmp_index++] );
+            tmp_devidx++;
+
+            tmp_devid = DEVICE_ID( info );
+        }
+    }
+
+    /* zero out the last instance */
+    NvOsMemset( inst, 0, sizeof(*inst) );
+    *instanceLast = inst;
+    inst = *instances;
+
+    /* setup the module index table:
+     * walk to instances - setup the module table.
+     */
+    index = 0;
+    devid = inst->DeviceId;
+    while( inst->DeviceId ) // null terminated instance array
+    {
+        if( devid == inst->DeviceId )
+        {
+            modid = NvRmPrivDevToModuleID(devid);
+            if(( modid != NVRM_DEVICE_UNKNOWN ) && 
+               ( modid != NVRM_DEVICE_ERROR ))
+            {
+                modules[modid].Index = (NvU16)index;
+            }
+            else
+            {
+                NV_ASSERT( !"relocation table parsing error" );
+            }
+        }
+
+        /* skip the rest of the instances */
+        do
+        {
+            inst++;
+            index++;
+        } while( inst->DeviceId == devid );
+
+        devid = inst->DeviceId;
+    }
+
+    return NvSuccess;
+
+fail:
+    *instances = 0;
+    return ret;
+}
+
+static NvRmModuleInstance *
+NvRmPrivGetInstance( NvRmModuleInstance *inst, NvU8 devidx )
+{
+    while( inst->DeviceId )
+    {
+        if( inst->DevIdx == devidx )
+        {
+            return inst;
+        }
+
+        inst++;
+    }
+
+    return 0;
+}
+
+static NvError
+NvRmPrivParseIrqs( const NvU32 *table, NvRmIrqMap *irqs,
+    NvRmModuleInstance *instances )
+{
+    NvU32 info;
+    NvU32 minor;
+    NvU32 index;
+    NvU16 ctlr_index[NVRM_MAX_INTERRUPT_CTLRS];
+    NvU16 ctlr;
+    NvU16 irq;
+    NvU8 devidx = 0;
+    NvU16 intridx = 0;
+    NvRmModuleInstance *inst;
+    NvRmModuleIrqMap *map;
+    NvU8 Valid;
+    NvU16 IntDevIndex;
+    NvU16 IntNum;
+    NvU32 devid;
+    NvU32 Affinity;
+    NvU32 Processor = NV_IS_AVP ? 2 : 1;
+    NvU8 irqBase = 0;
+
+    for (ctlr = 0; ctlr < NVRM_MAX_INTERRUPT_CTLRS; ++ctlr)
+    {
+        ctlr_index[ctlr] = 0xFFFF;
+    }
+
+    /* skip version */
+    index = 1;
+
+    /* find the interrupt controllers */
+    while( NV_READ32( &table[index] ) )
+    {
+        info  = NV_READ32( &table[index] );
+        devid = DEVICE_ID( info );
+
+        // Main interrupt controller?
+        if (devid == NVRM_DEVID_ICTLR)
+        {
+            // The main interrupt controller instances are identified
+            // by their minor revision number.
+            minor = DEVICE_MINOR_REV(info);
+            NV_ASSERT(minor < NVRM_MAX_MAIN_INTR_CTLRS);
+            NV_ASSERT(ctlr_index[minor] == 0xFFFF);
+            ctlr_index[minor] = devidx;
+        }
+        else if (devid == NVRM_DEVID_ARM_ICTLR) 
+        {
+            /* If the falcon interrupt controller is present then the IRQs
+             * start from 32. Falcon controller cannot be used when running on
+             * QT using
+             * EMUTRANS. 
+             */
+#if !(NVCPU_IS_X86 || NV_IS_AVP)
+            irqBase = 32;
+#endif
+        }
+
+        index += 3;
+        devidx++;
+    }
+
+    /* skip the null separator between the device and irq table */
+    index++;
+
+    while( NV_READ32( &table[index] ) )
+    {
+        info = NV_READ32( &table[index++] );
+
+        // Extract the interrupt entry fields.
+        Valid       = (NvU8)IRQ_VALID(info);
+        IntDevIndex = (NvU16)IRQ_INT_DEV_INDEX(info);
+        devidx      = (NvU8)IRQ_DEVICE_INDEX(info);
+        IntNum      = (NvU16)IRQ_INT_NUM(info);
+        Affinity    = IRQ_TARGET(info);
+
+        NV_ASSERT(IntNum < NVRM_IRQS_PER_INTR_CTLR);
+
+        // Retrieve the device instance to which this interrupt belongs.
+        inst = NvRmPrivGetInstance( instances, devidx );
+        if( inst == NULL )
+        {
+            /* interrupt pointing to something that's unknown, skip it. */
+            continue;
+        }
+
+        // Locate the interrupt controller that manages this interrupt
+        irq = NVRM_IRQ_INVALID;
+        for( ctlr = 0; ctlr < NVRM_MAX_INTERRUPT_CTLRS; ctlr++ )
+        {
+            if (ctlr_index[ctlr] != 0xFFFF)
+            {
+                if( ctlr_index[ctlr] == IntDevIndex )
+                {
+                    irq = irqBase + ( ctlr * 32 ) + IntNum;
+                    break;
+                }
+            }
+        }
+
+        /* Don't take care of interrupts routed to interrupts other than main
+         * interrupt controller.
+         * */
+        if (irq == NVRM_IRQ_INVALID) continue;
+
+        map = inst->IrqMap;
+        if( map == 0 )
+        {
+            // Allocate a new device IRQ map.
+            NV_ASSERT(irqs->DeviceCount < NVRM_MAX_IRQ_DEVICES);
+            map = &irqs->DeviceIrq[ irqs->DeviceCount++ ];
+            inst->IrqMap = map;
+        }
+        else
+        {
+            NV_ASSERT(map->IrqCount < NVRM_MAX_DEVICE_IRQS);
+        }
+
+        if (Valid)
+        {
+            /* HW bug 562244 - Affinities are wrong in the relocation table. */
+            if (irq == 29 + irqBase) 
+            {
+                Affinity = 1;
+            }
+            if (irq == 28 + irqBase)
+            {
+                Affinity = 2;
+            }
+
+
+            // Consider this IRQ for mapping only if the IRQ's processor
+            // affinity matches this processor or if the IRQ has no affinity.
+            if ((Affinity == 0)
+            ||  (Affinity == Processor))
+            {
+                // Add the IRQ to the device's IRQ list
+                map->Irq[ map->IrqCount++ ] = irq;
+                NVRM_MODULE_PRINTF(("[Interrupt %d] Device Index: %d "
+                    "IntCtlr: %d IntNum: %d Irq: %d Affinity: %d\n",
+                    intridx, devidx, ctlr, IntNum, irq, Affinity));
+            }
+            else
+            {
+                // This IRQ belongs to the other processor.
+                NVRM_MODULE_PRINTF(("[Interrupt %d] Device Index: %d "
+                    "IntCtlr: %d IntNum: %d Irq: %d Affinity: %d mapped on "
+                    "other processor\n",
+                    intridx, devidx, ctlr, IntNum, irq, Affinity));
+            }
+        }
+        else
+        {
+            // Add placeholder to the device's IRQ list
+            map->Irq[ map->IrqCount++ ] = NVRM_IRQ_INVALID;
+        }
+        intridx++;
+    }
+
+    NVRM_MODULE_PRINTF(("\n"));
+
+    return NvSuccess;
+}
+
+NvError
+NvRmPrivRelocationTableParse(
+    const NvU32 *table,
+    NvRmModuleInstance **instances, NvRmModuleInstance **instanceLast,
+    NvRmModule *modules, NvRmIrqMap *irqs )
+{
+    NvError err;
+
+    /* only know how to parse version 1 tables */
+    NV_ASSERT( NV_READ32( &table[0] ) == 1 );
+
+    NVRM_MODULE_PRINTF(( "Relocation Table:\n" ));
+
+    /* parse the devices */
+    err = NvRmPrivParseDevices( table, instances, instanceLast,
+        modules );
+    if( err != NvSuccess )
+    {
+        return err;
+    }
+
+    /* parse the irq entries */
+    err = NvRmPrivParseIrqs( table, irqs, *instances );
+    if( err != NvSuccess )
+    {
+        return err;
+    }
+
+    return NvSuccess;
+}
diff --git a/arch/arm/mach-tegra/nvrm/core/common/nvrm_relocation_table.h b/arch/arm/mach-tegra/nvrm/core/common/nvrm_relocation_table.h
new file mode 100644
index 000000000000..04b4eacc550b
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/core/common/nvrm_relocation_table.h
@@ -0,0 +1,271 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_NVRM_RELOCATION_TABLE_H
+#define INCLUDED_NVRM_RELOCATION_TABLE_H
+
+#include "nvcommon.h"
+#include "nvrm_init.h"
+
+/**
+ * The AP family supports a Relocation Table which lists the devices in the
+ * system, their version numbers, and their physical base addressess and
+ * aperture size.  Interrupt information is also stored in the table.
+ *
+ * The relcation table format:
+ *
+ * +-------------------( 32 bits )-------------------------------------+
+ * |                    table version                                  |
+ * +-------------------------------------------------------------------+
+ * |               [ device table entries ]                            |
+ * +-------------------------------------------------------------------+
+ * |                    null (0)                                       |
+ * +-------------------------------------------------------------------+
+ * |                [ irq table entries ]                              |
+ * +-------------------------------------------------------------------+
+ * |                    null (0)                                       |
+ * +-------------------------------------------------------------------+
+ *
+ * The device table entry format:
+ *
+ * +-------------------( 32 bits )-------------------------------------+
+ * | id [31:16] | major [15:12] | minor [11:8] | res [7:4] | bar [3:0] |
+ * |-------------------------------------------------------------------|
+ * |                    start address                                  |
+ * |-------------------------------------------------------------------|
+ * |                    length                                         |
+ * +-------------------------------------------------------------------+
+ *
+ * The irq entry format:
+ *
+ * +-------------------( 32 bits )-----------------------------------------+
+ * |V[31]|rsvd[30:29]|IntDevIdx[28:20]|rsvd[19:17]|DevIdx[16:8]|IntNum[7:0]|
+ * +-----------------------------------------------------------------------+
+ *
+ * Every entry (whether valid or not) will always contain an Interrupt
+ * Controller Device Index (IntDevIdx), a Device Index (DevIdx), and an
+ * Interrupt Number (IntNum) value. Whether or not that entry actually
+ * corresponds to an interrupt source is determined by the valid (V) bit.
+ * If the valid bit is 1, the interrupt number corresponds to an actual
+ * interrupt source. If the valid bit is zero, this entry represents an
+ * interrupt source that was present in a prior SOC but that is no longer
+ * used. The slot for that interrupt in the interrupt map table must be
+ * preseved because "indexed" interrupts are determined positionally.
+ * Removal of an interrupt would change the positional assignment of all
+ * following interrupt numbers and would break forward compatibility.
+ */
+
+#define NVRM_DEVICE_UNKNOWN     ((NvU32)-2)
+#define NVRM_DEVICE_ERROR       ((NvU32)-3)
+
+// The module index in the NvRmModule table is invalid; this is not an error.
+#define NVRM_MODULE_INVALID     (0xFFFF)
+
+// Number of interrupt controllers
+#define NVRM_MAX_MAIN_INTR_CTLRS    5
+
+// Number of DMA transmit interrupt controllers
+#define NVRM_MAX_DRQ_INTR_CTLRS     2
+
+// Number of Arbitration Grant interrupt controllers
+#define NVRM_ARB_GNT_INTR_CTLRS     1
+
+// Number of interrupt controllers of all types
+#define NVRM_MAX_INTERRUPT_CTLRS    (NVRM_MAX_MAIN_INTR_CTLRS + \
+    NVRM_MAX_DRQ_INTR_CTLRS + NVRM_ARB_GNT_INTR_CTLRS)
+
+// Relative position of first DMA transmit interrupt controller
+#define NVRM_FIRST_DRQ_INTR_CTLR    (NVRM_MAX_MAIN_INTR_CTLRS)
+
+// Relative position of first Arbitration Grant interrupt controller
+#define NVRM_FIRST_ARB_INTR_CTLR    (NVRM_MAX_MAIN_INTR_CTLRS + \
+    NVRM_MAX_DRQ_INTR_CTLRS)
+
+// Number of IRQs per interrupt controller (main, DRQ, & ARB)
+#define NVRM_IRQS_PER_INTR_CTLR     32
+
+// Number of IRQs per GPIO controller
+#define NVRM_IRQS_PER_GPIO_CTLR     32
+
+// Number of IRQs per AHB DMA channel
+#define NVRM_IRQS_PER_AHB_DMA_CHAN  1
+
+// Number of IRQs per APB DMA channel
+#define NVRM_IRQS_PER_APB_DMA_CHAN  1
+
+// Invalid IRQ valid
+#define NVRM_IRQ_INVALID            0xFFFF
+
+// Maximum number of interrupts per device
+#define NVRM_MAX_DEVICE_IRQS        8
+
+// Maximum number of IRQs
+#define NVRM_MAX_IRQS               500
+
+// Maximum number of devices that can generate IRQs
+// !!!CHECKME!!! CHECK THE SIZING OF THIS VALUE
+#define NVRM_MAX_IRQ_DEVICES        96
+
+// Maximum number of DMA channels 
+#define NVRM_MAX_DMA_CHANNELS       32
+
+// This is the Maximum number of instance of all modules on any chip
+// supported by Rm.
+// Need to increase this value when more modules are added in the up comming
+// chips.
+#define NVRM_MAX_MODULE_INSTANCES   256
+
+/**
+ * Device IRQ assignments structure.
+ */
+typedef struct NvRmModuleIrqMapRec
+{
+    /* Number of IRQs owned by this device */
+    NvU16 IrqCount;
+
+    /* Maximum instance IRQ index */
+    NvU16 IndexMax;
+
+    /* Base IRQ for subcontroller "index" IRQ fanout */
+    NvU16 IndexBase;
+
+    /* IRQs owned by this device */
+    NvU16 Irq[NVRM_MAX_DEVICE_IRQS];
+} NvRmModuleIrqMap;
+
+/**
+ * System IRQ assignments structure.
+ */
+typedef struct NvRmIrqMapRec
+{
+    /* Number of devices owning IRQs */
+    NvU32 DeviceCount;
+
+    /* Device IRQ mapping */
+    NvRmModuleIrqMap DeviceIrq[NVRM_MAX_IRQ_DEVICES];
+} NvRmIrqMap;
+
+/**
+ * Some hardware modules may be instantiated multiple times - all hw modules
+ * are mapped into this structure.
+ */
+typedef struct NvRmModuleInstanceRec
+{
+    /* the base address of the module instance */
+    NvRmPhysAddr PhysAddr;
+
+    /* length of the aperture */
+    NvU32 Length;
+
+    /* bar number */
+    // FIXME: not supported properly - each bar is reported as a different
+    // hardware module instance.
+    NvU8 Bar;
+
+    /* hardware version */
+    NvU8 MajorVersion;
+    NvU8 MinorVersion;
+
+    /* power group */
+    NvU8 DevPowerGroup;
+
+    /* the original index into the relocation table */
+    NvU8 DevIdx;
+
+    /* hardware device id */
+    NvU32 DeviceId;
+
+    /* Irq mapping for this module instance */
+    NvRmModuleIrqMap *IrqMap;
+
+    /* virtual address: will be mapped by a later mechanism.  this is here
+     * as a space optimization.
+     */
+    void *VirtAddr;
+
+    /* Module specific data like clocks, resets etc.. */
+    void *ModuleData;
+} NvRmModuleInstance;
+
+/**
+ * Module index table.  Each index points to the first module instance in the
+ * NvRmModuleInstance table. The NvRmModule table itself is indexed by module
+ * id.
+ */
+typedef struct NvRmModuleRec
+{
+    /* offset into the NvRmModuleInstance table */
+    NvU16 Index;
+} NvRmModule;
+
+/**
+ * Maps relocation table device ids to software module ids.
+ * NVRM_DEVICE_UNKNOWN for unknown ids (will keep parsing table),
+ * or NVRM_DEVICE_ERROR if something bad happened
+ * (will stop parsing the table).
+ *
+ * NVRM_DEVICE_UNKOWN can be used to cull the device list to save space by
+ * not allocating memory for devices that won't be used.
+ */
+NvU32 NvRmPrivDevToModuleID(NvU32 devid);
+
+/**
+ * Parse the relocation table.
+ *
+ * The module instance table (NvRmModuleInstance) will be allocated to exactly
+ * match the number of hardware modules in the system rather than using a
+ * worst-case number of instances for all hardware modules.
+ *
+ * The module table should be allocated prior to this function and should be
+ * sized to the maximum number of module ids.
+ *
+ * The irq map will not be allocated (statically sized).
+ *
+ * The instance array will be null terminated -- the last instance will contain
+ * zero in all of its fields.
+ *
+ * @param hDevice The resource manager instance
+ * @param table The relocation table
+ * @param instances Out param - will contain the allocated instance table
+ * @param instanceLast Out param - will contain the last allocated instance + 1
+ * @param modules Out param - will contain the allocated module table
+ * @param irqs The irq table - will be filled in by the parser
+ */
+NvError
+NvRmPrivRelocationTableParse(
+    const NvU32 *table,
+    NvRmModuleInstance **instances,
+    NvRmModuleInstance **instanceLast,
+    NvRmModule *modules,
+    NvRmIrqMap *irqs );
+
+#endif
diff --git a/arch/arm/mach-tegra/nvrm/core/common/nvrm_rmctrace.c b/arch/arm/mach-tegra/nvrm/core/common/nvrm_rmctrace.c
new file mode 100644
index 000000000000..8e8353739f36
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/core/common/nvrm_rmctrace.c
@@ -0,0 +1,49 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include "nvcommon.h"
+#include "nvrm_rmctrace.h"
+#include "nvos.h"
+#include "nvassert.h"
+
+NvError NvRmRmcOpen( const char *name, NvRmRmcFile *rmc )
+{
+    return NvSuccess;
+}
+
+void NvRmRmcClose( NvRmRmcFile *rmc )
+{
+}
+
+void NvRmRmcTrace( NvRmRmcFile *rmc, const char *format, ... )
+{
+}
diff --git a/arch/arm/mach-tegra/nvrm/core/common/nvrm_structure.h b/arch/arm/mach-tegra/nvrm/core/common/nvrm_structure.h
new file mode 100644
index 000000000000..da3f68423c02
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/core/common/nvrm_structure.h
@@ -0,0 +1,152 @@
+/*
+ * Copyright (c) 2008-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_NVRM_STRUCTURE_H
+#define INCLUDED_NVRM_STRUCTURE_H
+
+/*
+ * nvrm_structure.h defines all of the internal data structures for the
+ * resource manager which are chip independent.
+ *
+ * Don't add chip specific stuff to this file.
+ */
+
+#include "nvcommon.h"
+#include "nvos.h"
+#include "nvrm_module.h"
+#include "nvrm_module_private.h"
+#include "nvrm_chipid.h"
+#include "nvrm_interrupt.h"
+#include "nvrm_memmgr.h"
+#include "nvrm_pinmux.h"
+#include "nvrm_rmctrace.h"
+#include "nvrm_configuration.h"
+#include "nvrm_relocation_table.h"
+#include "nvrm_moduleids.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif  /* __cplusplus */
+
+typedef struct RmConfigurationVariables_t
+{
+    /* RMC Trace file name */
+    char RMCTraceFileName[ NVRM_CFG_MAXLEN ];
+
+    /* chiplib name */
+    char Chiplib[ NVRM_CFG_MAXLEN ];
+
+    /* chiplib args */
+    char ChiplibArgs[ NVRM_CFG_MAXLEN ];
+
+} RmConfigurationVariables;
+
+/* memory pool information */
+typedef struct RmMemoryPool_t
+{
+    NvU32 base;
+    NvU32 size;
+} RmMemoryPool;
+
+/* The state for the resource manager */
+typedef struct NvRmDeviceRec
+{
+    RmConfigurationVariables cfg;
+    NvRmRmcFile rmc;
+    NvBool rmc_enable;
+    NvOsMutexHandle mutex;
+    //  FIXME:  this is hardcoded to the number of tristate registers in AP15.
+    NvS16 TristateRefCount[4 * sizeof(NvU32)*8];
+    NvU32 refcount;
+
+    NvOsMutexHandle MemMgrMutex;
+    NvOsMutexHandle PinMuxMutex;
+    NvOsMutexHandle CarMutex;   /* r-m-w top level CAR registers mutex */
+
+    /* chip id */
+    NvRmChipId ChipId;
+
+    /* module instances and module index table */
+    NvRmModuleTable ModuleTable;
+
+    RmMemoryPool ExtMemoryInfo;
+    RmMemoryPool IramMemoryInfo;
+    RmMemoryPool GartMemoryInfo;
+
+    NvU16 MaxIrqs;
+
+    const NvU32  ***PinMuxTable;
+    // FIXME: get rid of all the various Init and Open functions in favor
+    // of a sane state machine for system boot/initialization
+    NvBool bPreInit;
+    NvBool bBasicInit;
+} NvRmDevice;
+
+// FIXME: This macro should be comming from the relocation table.
+#define NVRM_MAX_INSTANCES 32
+
+/**
+ * Sub-contoller interrupt decoder description forward reference.
+ */
+typedef struct NvRmIntrDecoderRec *NvRmIntrDecoderHandle;
+
+/**
+ * Attributes of the Interrupt sub-decoders.
+ */
+typedef struct NvRmIntrDecoderRec
+{
+    NvRmModuleID ModuleID;
+
+    //  Number of IRQs owned by this sub-controller.
+    //  This value is same for all the instances of the controller.
+    NvU32 SubIrqCount;
+
+    // Number of instance for this sub-decoder
+    NvU32 NumberOfInstances;
+    
+    // Main controller IRQ.
+    NvU16 MainIrq[NVRM_MAX_INSTANCES];
+
+    // First IRQ owned by this sub-controller.
+    NvU16 SubIrqFirst[NVRM_MAX_INSTANCES];
+
+    // Last IRQ owned by this sub-controller.
+    NvU16 SubIrqLast[NVRM_MAX_INSTANCES];
+
+} NvRmIntrDecoder;
+
+#ifdef __cplusplus
+}
+#endif  /* __cplusplus */
+
+#endif // INCLUDED_NVRM_STRUCTURE_H
diff --git a/arch/arm/mach-tegra/nvrm/core/common/nvrm_transport.c b/arch/arm/mach-tegra/nvrm/core/common/nvrm_transport.c
new file mode 100644
index 000000000000..4504b8a01819
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/core/common/nvrm_transport.c
@@ -0,0 +1,1691 @@
+/*
+ * Copyright (c) 2010 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/** @file
+ * @brief <b>NVIDIA Driver Development Kit:
+ *          Transport API</b>
+ *
+ * @b Description: This is the implementation of Transport API, which
+ * implements a simple means to pass messages across a port name regardless of
+ * port exist in what processor (on same processor or other processor).
+ */
+
+#include "nvrm_transport.h"
+#include "nvrm_xpc.h"
+#include "nvrm_interrupt.h"
+#include "nvrm_message.h"
+#include "nvutil.h"
+#include "nvassert.h"
+#include "nvcommon.h"
+#include "avp.h"
+#include <linux/jiffies.h>
+
+#define LOOPBACK_PROFILE 0
+
+// indices where to save data for the loopback test
+#define LOOP_CPU_SEND_INDEX 0
+#define LOOP_AVP_ISR_INDEX  1
+#define LOOP_AVP_RECV_INDEX 2
+#define LOOP_AVP_SEND_INDEX 3
+#define LOOP_CPU_ISR_INDEX  4
+#define LOOP_CPU_RECV_INDEX 5
+
+#define SEMAPHORE_BASED_MUTUAL_EXCLUSION 0
+
+enum {MAX_INT_FOR_TRANSPORT = 2};
+
+// Interrupt bit index in the interrupt controller relocation table.
+enum {CPU_TRANSPORT_INT_OBE = 1};
+enum {CPU_TRANSPORT_INT_IBF = 0};
+enum {AVP_TRANSPORT_INT_OBE = 0};
+enum {AVP_TRANSPORT_INT_IBF = 1};
+
+// Some constraints parameter to develop the transport APIs.
+
+// Maximum port name length
+enum {MAX_PORT_NAME_LENGTH = 16};
+
+// Maximum possible message length between the ports
+#define  MAX_COMMAND_SIZE   16
+
+// Message header size MessageCommand + port Name + message Length (24 Bytes)
+enum {MESSAGE_HEADER_SIZE = 0x20};
+
+// Maximum receive message queue depth
+enum {MAX_MESSAGE_DEPTH = 30};
+
+// Maximum time to wait for the response when open the port.
+enum {MAX_OPEN_TIMEOUT_MS = 200};
+
+// Try to resend the message after this time.
+enum {MESSAGE_RETRY_AFTER_MS = 500 };
+
+// Connection message transfer and response wait timeout.
+enum {MAX_CONNECTION_TIMEOUT_MS = 500 };
+
+
+
+// Transport Commands which uses to do the handshaking and message transfer
+// between the processor. This commands are send to the remote processor
+// when any type if transaction happens.
+typedef enum
+{
+  TransportCmd_None = 0x0,
+
+  // The first transport command from the cpu->avp will inform the
+  // avp of size of the buffer.
+  TransportCmd_SetBufferInfo,
+
+  // Transport command for staring the connection process.
+  TransportCmd_Connect,
+
+  // Transport command for disconnecting the port and deleting the port entry.
+  TransportCmd_Disconnect,
+
+  // Transport command which used for normal message transfer to the port.
+  TransportCmd_Message,
+
+  // When a command requires a response, the value in the command field will
+  // be changed by the called processor here to indicate that the response is ready.
+  TransportCmd_Response,
+
+  TransportCmd_Force32 = 0x7FFFFFFF
+
+} TransportCmd;
+
+
+
+// Ports (endpoint) state.
+typedef enum
+{
+    // Port is opened only.
+    PortState_Open = 0x1,
+
+    // Port is waiting for connection.
+    PortState_Waiting,
+
+    // Port is connected.
+    PortState_Connected,
+
+    // Port has been disconnected from other side.  You can pop out messages
+    // but you can't send anymore
+    PortState_Disconnected,
+
+    // Set to destroy when there is someone waiting for a connection, but
+    // and a different thread calls to kill close the port.
+    PortState_Destroy,
+
+    PortState_Force32 = 0x7FFFFFFF
+} PortState;
+
+
+
+// Message list which will be queued in the port receive message queue.
+typedef struct RmReceiveMessageRec
+{
+    // Length of message.
+    NvU32 MessageLength;
+
+    // Fixed size message buffer where the receiving message will be store.
+    NvU8 MessageBuffer[MAX_MESSAGE_LENGTH];
+} RmReceiveMessage;
+
+
+// Combines the information for keeping the received messages to the
+// corresponding ports.
+typedef struct MessageQueueRec
+{
+    // Receive message Q details to receive the message.  We make the queue 1 extra bigger than the
+    // requested size, and then we can do lockless updates because only the Recv function modifies
+    // ReadIndex, and only the ISR modifies the WriteIndex
+    RmReceiveMessage *pReceiveMsg;
+
+    volatile NvU16 ReadIndex;
+    volatile NvU16 WriteIndex;
+
+    NvU16 QueueSize;
+
+} MessageQueue;
+
+
+
+// Combines all required information for the transport port.
+// The port information  contains the state, recv message q, message depth and
+// message length.
+typedef struct NvRmTransportRec
+{
+    // Name of the port, 1 exra byte for NULL termination
+    char PortName[MAX_PORT_NAME_LENGTH+1];
+
+    // The state of port whether this is open or connected or waiting for
+    // connection.
+    PortState State;
+
+    // Receive message Box which contains the receive messages for this port.
+    MessageQueue RecvMessageQueue;
+
+    // Semaphore which is signal after getting the message for that port.
+    // This is the client passed semaphore.
+    NvOsSemaphoreHandle hOnPushMsgSem;
+
+    // Pointer to the partner port.  If the connect is to a remote partner,
+    // then this pointer is NULL
+    NvRmTransportHandle hConnectedPort;
+
+    // If this is a remote connection, this holds the remote ports "name"
+    NvU32               RemotePort;
+
+    // save a copy of the rm handle.
+    NvRmDeviceHandle hRmDevice; 
+
+    struct NvRmTransportRec *pNext;
+
+    // unlikely to be used members at the end
+    
+    // to be signalled when someone waits for a connector.
+    NvOsSemaphoreHandle hOnConnectSem;
+
+#if LOOPBACK_PROFILE
+    NvBool              bLoopTest;
+#endif
+
+} NvRmTransport;
+
+
+
+// Combines the common information for keeping the transport information and
+// sending and receiving the messages.
+typedef struct NvRmPrivPortsRec
+{
+    // Device handle.
+    NvRmDeviceHandle hDevice;
+
+    // List of port names of the open ports in the system.
+    NvRmTransport   *pPortHead;
+
+    // Mutex for transport
+    NvOsMutexHandle mutex;
+
+    NvRmMemHandle hMessageMem;
+    void          *pTransmitMem;
+    void          *pReceiveMem;
+    NvU32         MessageMemPhysAddr;
+
+    NvRmPrivXpcMessageHandle hXpc;
+
+    // if a message comes in, but the receiver's queue is full,
+    // then we don't clear the inbound message to allow another message
+    // and set this flag.  We use 2 variables here, so we don't need a lock.
+    volatile NvU8  ReceiveBackPressureOn;
+    NvU8           ReceiveBackPressureOff;
+
+#if LOOPBACK_PROFILE
+    volatile NvU32 *pTimer;
+#endif
+} NvRmPrivPorts;
+
+
+// !!! Fixme, this should be part of the rm handle.
+static NvRmPrivPorts s_TransportInfo;
+
+extern NvU32 NvRmAvpPrivGetUncachedAddress(NvU32 addr);
+
+#define MESSAGE_QUEUE_SIZE_IN_BYTES ( sizeof(RmReceiveMessage) * (MAX_MESSAGE_DEPTH+1) )
+static NvU32 s_RpcAvpQueue[ (MESSAGE_QUEUE_SIZE_IN_BYTES + 3) / 4 ];
+static NvU32 s_RpcCpuQueue[ (MESSAGE_QUEUE_SIZE_IN_BYTES + 3) / 4 ];
+static struct NvRmTransportRec s_RpcAvpPortStruct;
+static struct NvRmTransportRec s_RpcCpuPortStruct;
+
+static NvOsInterruptHandle s_TransportInterruptHandle = NULL;
+
+static NvRmTransportHandle
+FindPort(NvRmDeviceHandle hDevice, char *pPortName);
+
+static NvError NvRmPrivTransportSendMessage(NvRmDeviceHandle hDevice,
+    NvU32 *messagehdr, NvU32 MessageHdrLength,
+    NvU32 *Message, NvU32 MessageLength);
+
+static void HandleAVPResetMessage(NvRmDeviceHandle hDevice);
+
+// expect caller to handle mutex
+static char *NvRmPrivTransportUniqueName(void)
+{
+    static char UniqueName[] = "aaaaaaaa+";
+    NvU32 len = 8;
+    NvU32 i;
+
+    // this will roll a new name until we hit zzzz:zzzz
+    // it's not unbounded, but it is a lot of names...
+    // Unique names end in a '+' which won't be allowed in supplied names, to avoid
+    // collision.
+    for (i=0; i < len; ++i)
+    {
+        ++UniqueName[i];
+        if (UniqueName[i] != 'z')
+        {
+            break;
+        }
+        UniqueName[i] = 'a';
+
+    }
+
+    return UniqueName;
+}
+
+
+/* Returns NV_TRUE if the message was inserted ok
+ *  Returns NV_FALSE if message was not inserted because the queue is already full
+
+ */static NvBool
+InsertMessage(NvRmTransportHandle hPort, const NvU8 *message, const NvU32 MessageSize)
+{
+    NvU32 index;
+    NvU32 NextIndex;
+
+    index = (NvU32)hPort->RecvMessageQueue.WriteIndex;
+    NextIndex = index + 1;
+    if (NextIndex == hPort->RecvMessageQueue.QueueSize)
+        NextIndex = 0;
+
+    // check for full condition
+    if (NextIndex == hPort->RecvMessageQueue.ReadIndex)
+        return NV_FALSE;
+
+    // copy in the message
+    NvOsMemcpy(hPort->RecvMessageQueue.pReceiveMsg[index].MessageBuffer,
+               message,
+               MessageSize);
+    hPort->RecvMessageQueue.pReceiveMsg[index].MessageLength = MessageSize;
+
+    hPort->RecvMessageQueue.WriteIndex = (NvU16)NextIndex;
+    return NV_TRUE;
+}
+
+
+static void
+ExtractMessage(NvRmTransportHandle hPort, NvU8 *message, NvU32 *pMessageSize, NvU32 MaxSize)
+{
+    NvU32 NextIndex;
+    NvU32 index = (NvU32)hPort->RecvMessageQueue.ReadIndex;
+    NvU32 size  = hPort->RecvMessageQueue.pReceiveMsg[index].MessageLength;
+
+    NextIndex = index + 1;
+    if (NextIndex == hPort->RecvMessageQueue.QueueSize)
+        NextIndex = 0;
+
+    NV_ASSERT(index != hPort->RecvMessageQueue.WriteIndex); // assert on empty condition
+    NV_ASSERT(size <= MaxSize);
+
+    *pMessageSize = size;
+
+    // only do the copy and update if there is sufficient room, otherwise
+    // the caller will propogate an error up.
+    if (size > MaxSize)
+    {
+        return;
+    }
+    NvOsMemcpy(message,
+               hPort->RecvMessageQueue.pReceiveMsg[index].MessageBuffer,
+               size);
+
+    hPort->RecvMessageQueue.ReadIndex = (NvU16)NextIndex;
+}
+
+
+
+static void *s_TmpIsrMsgBuffer;
+
+/**
+ * Connect message
+ *  [ Transport Command ]
+ *  [ Remote Handle ]
+ *  [ Port Name ]
+ *
+ * Response:
+ *   [ Remote Handle ] <- [ Local Handle ]
+ */
+
+static void
+HandleConnectMessage(NvRmDeviceHandle hDevice, volatile NvU32 *pMessage)
+{
+    char PortName[MAX_PORT_NAME_LENGTH+1];
+    NvU32 RemotePort;
+    NvRmTransportHandle hPort;
+    
+    RemotePort = pMessage[1];
+    NvOsMemcpy(PortName, (void*)&pMessage[2], MAX_PORT_NAME_LENGTH);
+    PortName[MAX_PORT_NAME_LENGTH] = 0;
+
+    // See if there is a local port with that name
+    hPort = FindPort(hDevice, PortName);
+    if (hPort && hPort->State == PortState_Waiting)
+    {
+        NvOsAtomicCompareExchange32((NvS32 *)&hPort->State, PortState_Waiting, PortState_Connected);
+        if (hPort->State == PortState_Connected)
+        {
+            hPort->RemotePort = RemotePort;
+            NvOsSemaphoreSignal(hPort->hOnConnectSem);
+            pMessage[1] = (NvU32)hPort;
+        }
+        else
+        {
+            pMessage[1] = 0;
+        }
+    }
+    else
+    {
+        pMessage[1] = 0;
+    }
+    pMessage[0] = TransportCmd_Response;
+}
+
+
+
+/**
+ * Disconnect message
+ *  [ Transport Command ]
+ *  [ Local Handle ]
+ *
+ * Response:
+ *   [ Local Handle ] <- 0 
+ */
+static void
+HandleDisconnectMessage(NvRmDeviceHandle hDevice, volatile NvU32 *pMessage)
+{
+    NvRmTransportHandle hPort;
+    hPort = (NvRmTransportHandle)pMessage[1];
+
+    // !!! For sanity we should walk the list of open ports to make sure this is a valid port!
+    if (hPort && hPort->State == PortState_Connected)
+    {
+        hPort->State = PortState_Disconnected;
+        hPort->RemotePort = 0;
+    }
+    pMessage[1] = 0;
+    pMessage[0] = TransportCmd_None;
+}
+
+
+/**
+ * Disconnect message
+ *  [ Transport Command ]
+ *  [ Local Handle ]
+ *  [ Message Length ]
+ *  [ Message ]
+ *
+ * Response:
+ *   [ Message Length ] <- NvSuccess 
+ *   [ Transport Command ] <- When we can accept a new message
+ */
+
+static void
+HandlePortMessage(NvRmDeviceHandle hDevice, volatile NvU32 *pMessage)
+{
+    NvRmTransportHandle hPort;
+    NvU32               MessageLength;
+    NvBool              bSuccess;
+
+    hPort         = (NvRmTransportHandle)pMessage[1];
+    MessageLength = pMessage[2];
+
+#if LOOPBACK_PROFILE
+    if (hPort && hPort->bLoopTest)
+    {
+# if NV_IS_AVP
+        pMessage[LOOP_AVP_ISR_INDEX + 3] = *s_TransportInfo.pTimer;
+# else
+        pMessage[LOOP_CPU_ISR_INDEX + 3] = *s_TransportInfo.pTimer;
+# endif
+    }
+#endif
+
+
+    // !!! For sanity we should walk the list of open ports to make sure this is a valid port!
+    // Queue the message even if in the open state as presumably this should only have happened if
+    // due to a race condition with the transport connected messages.
+    if (hPort && (hPort->State == PortState_Connected || hPort->State == PortState_Open))    
+    {
+        bSuccess = InsertMessage(hPort, (NvU8*)&pMessage[3], MessageLength);
+        if (bSuccess)
+        {
+            if (hPort->hOnPushMsgSem)
+                NvOsSemaphoreSignal(hPort->hOnPushMsgSem);
+            pMessage[0] = TransportCmd_None;
+        }
+        else
+        {
+            ++s_TransportInfo.ReceiveBackPressureOn;
+        }
+    }
+}
+
+static void 
+HandleAVPResetMessage(NvRmDeviceHandle hDevice)
+{
+    NvRmTransportHandle hPort;
+    
+    hPort = FindPort(hDevice,(char*)"RPC_CPU_PORT");
+    if (hPort && (hPort->State == PortState_Connected || hPort->State == PortState_Open))
+    {
+        NvU32 message;
+        message = NvRmMsg_AVP_Reset;
+        InsertMessage(hPort, (NvU8*)&message, sizeof(NvU32));
+        if (hPort->hOnPushMsgSem)
+            NvOsSemaphoreSignal(hPort->hOnPushMsgSem);
+        else
+            NV_ASSERT(0);
+    }
+    else
+        NV_ASSERT(0);
+
+}
+
+
+/**
+ * Handle the Inbox full interrupt.
+ */
+static void
+InboxFullIsr(void *args)
+{
+    NvRmDeviceHandle hDevice = (NvRmDeviceHandle)args;
+    NvU32 MessageData;
+    NvU32 MessageCommand;
+    volatile NvU32 *pMessage;
+
+    MessageData = NvRmPrivXpcGetMessage(s_TransportInfo.hXpc);
+    if(MessageData == AVP_WDT_RESET)
+    {
+         HandleAVPResetMessage(hDevice);
+         NvRmInterruptDone(s_TransportInterruptHandle);
+         return;
+    }
+    // if we're on the AVP, the first message we get will configure the message info
+    if (s_TransportInfo.MessageMemPhysAddr == 0)
+    {
+#if NV_IS_AVP
+        MessageData = NvRmAvpPrivGetUncachedAddress(MessageData);
+#else
+        MessageData = MessageData;
+#endif
+        s_TransportInfo.MessageMemPhysAddr = MessageData;
+        s_TransportInfo.pReceiveMem  = (void*)MessageData;
+        s_TransportInfo.pTransmitMem = (void *) (MessageData + MAX_MESSAGE_LENGTH + MAX_COMMAND_SIZE);
+        // ack the message and return.
+        *(NvU32*)s_TransportInfo.pReceiveMem = TransportCmd_None;
+        return;
+    }
+
+    // otherwise decode and dispatch the message.
+
+
+    if (s_TransportInfo.pReceiveMem == NULL)
+    {
+        /* QT/EMUTRANS takes this path. */
+        NvRmMemRead(s_TransportInfo.hMessageMem, MAX_MESSAGE_LENGTH + MAX_COMMAND_SIZE, s_TmpIsrMsgBuffer, MAX_MESSAGE_LENGTH);
+        pMessage = s_TmpIsrMsgBuffer;
+        NvRmMemWrite(s_TransportInfo.hMessageMem, MAX_MESSAGE_LENGTH + MAX_COMMAND_SIZE, s_TmpIsrMsgBuffer, 2*sizeof(NvU32));
+    }
+    else
+    {
+        pMessage = (NvU32*)s_TransportInfo.pReceiveMem;
+    }
+
+    MessageCommand = pMessage[0];
+
+    switch (MessageCommand)
+    {
+    case  TransportCmd_Connect:
+        HandleConnectMessage(hDevice, pMessage);
+        break;
+        
+    case  TransportCmd_Disconnect:
+        HandleDisconnectMessage(hDevice, pMessage);
+        break;
+
+    case TransportCmd_Message:
+        HandlePortMessage(hDevice, pMessage);
+        break;
+            
+    default:
+        NV_ASSERT(0);
+    }
+
+    NvRmInterruptDone(s_TransportInterruptHandle);
+}
+
+
+/**
+ * Handle the outbox empty interrupt.
+ */
+static void
+OutboxEmptyIsr(void *args)
+{
+    // !!! This is not currently used... ignore for now.  Might be required if we find that we
+    //     need to spin for long periods of time waiting for other end of the connection to consume
+    //     messages.
+    //
+    NvRmInterruptDone(s_TransportInterruptHandle);
+}
+
+static void
+NvRmPrivProcIdGetProcessorInfo(
+    NvRmDeviceHandle hDevice,
+    NvRmModuleID *pProcModuleId)
+{
+#if NV_IS_AVP
+    *pProcModuleId = NvRmModuleID_Avp;
+#else
+    *pProcModuleId = NvRmModuleID_Cpu;
+#endif
+}
+
+/**
+ * Register for the transport interrupts.
+ */
+static NvError
+RegisterTransportInterrupt(NvRmDeviceHandle hDevice)
+{
+    NvOsInterruptHandler DmaIntHandlers[MAX_INT_FOR_TRANSPORT];
+    NvU32 IrqList[MAX_INT_FOR_TRANSPORT];
+    NvRmModuleID ProcModuleId;
+
+    if (s_TransportInterruptHandle)
+    {
+        return NvSuccess;
+    }
+    NvRmPrivProcIdGetProcessorInfo(hDevice, &ProcModuleId);
+
+    if (ProcModuleId == NvRmModuleID_Cpu)
+    {
+        IrqList[0] = NvRmGetIrqForLogicalInterrupt(
+            hDevice, NvRmModuleID_ResourceSema, CPU_TRANSPORT_INT_IBF);
+        IrqList[1] = NvRmGetIrqForLogicalInterrupt(
+            hDevice, NvRmModuleID_ResourceSema, CPU_TRANSPORT_INT_OBE);
+    }
+    else
+    {
+        IrqList[0] = NvRmGetIrqForLogicalInterrupt(
+            hDevice, NvRmModuleID_ResourceSema, AVP_TRANSPORT_INT_IBF);
+        IrqList[1] = NvRmGetIrqForLogicalInterrupt(
+            hDevice, NvRmModuleID_ResourceSema, AVP_TRANSPORT_INT_OBE);
+    }
+
+    /* There is no need for registering the OutboxEmptyIsr, so we only register
+     * one interrupt i.e. InboxFullIsr  */
+    DmaIntHandlers[0] = InboxFullIsr;
+    DmaIntHandlers[1] = OutboxEmptyIsr;
+    return NvRmInterruptRegister(hDevice, 1, IrqList, DmaIntHandlers, 
+            hDevice, &s_TransportInterruptHandle, NV_TRUE);
+}
+
+// allocate buffers to be used for sending/receiving messages.
+static void
+NvRmPrivTransportAllocBuffers(NvRmDeviceHandle hRmDevice)
+{
+#if !NV_IS_AVP
+    // These buffers are always allocated on the CPU side.  We'll pass the address over the AVP
+    //
+
+    NvError Error = NvSuccess;
+    NvRmMemHandle hNewMemHandle = NULL;
+
+    // Create memory handle
+    Error = NvRmMemHandleCreate(hRmDevice, &hNewMemHandle, (MAX_MESSAGE_LENGTH + MAX_COMMAND_SIZE)*2);
+    if (Error)
+        goto fail;
+
+    // Allocates the memory from the Heap
+    Error = NvRmMemAlloc(hNewMemHandle, NULL, 0,
+                         XPC_MESSAGE_ALIGNMENT_SIZE, NvOsMemAttribute_Uncached);
+    if (Error)
+        goto fail;
+
+    s_TransportInfo.MessageMemPhysAddr = NvRmMemPin(hNewMemHandle);
+
+    // If it is success to create the memory handle.
+    // We have to be able to get a mapping to this, because it is used at interrupt time!
+    s_TransportInfo.hMessageMem = hNewMemHandle;
+    Error = NvRmMemMap(hNewMemHandle, 0,
+        (MAX_MESSAGE_LENGTH + MAX_COMMAND_SIZE)*2,
+        NVOS_MEM_READ_WRITE,
+        &s_TransportInfo.pTransmitMem);
+    if (Error)
+    {
+        s_TransportInfo.pTransmitMem = NULL;
+        s_TransportInfo.pReceiveMem = NULL;
+    }
+    else
+    {
+        s_TransportInfo.pReceiveMem  = (void *) (((NvUPtr)s_TransportInfo.pTransmitMem) + 
+                                                              MAX_MESSAGE_LENGTH + MAX_COMMAND_SIZE);
+    }
+
+    s_TransportInfo.hMessageMem = hNewMemHandle;
+    NvRmMemWr32(hNewMemHandle, 0, 0xdeadf00d); // set this non-zero to throttle messages to the avp till avp is ready.
+    NvRmMemWr32(hNewMemHandle,  MAX_MESSAGE_LENGTH + MAX_COMMAND_SIZE, 0);
+
+    NvRmPrivXpcSendMessage(s_TransportInfo.hXpc, s_TransportInfo.MessageMemPhysAddr);
+    return;
+    
+
+fail:
+    NvRmMemHandleFree(hNewMemHandle);
+    s_TransportInfo.hMessageMem = NULL;
+    return;
+#else
+    return;
+#endif
+}
+
+
+static void
+NvRmPrivTransportFreeBuffers(NvRmDeviceHandle hRmDevice)
+{
+#if !NV_IS_AVP
+    NvRmMemHandleFree(s_TransportInfo.hMessageMem);
+#endif
+}
+
+static volatile NvBool s_Transport_Inited = NV_FALSE;
+
+/**
+ * Initialize the transport structures, this is callled once
+ * at NvRmOpen time.
+ */
+NvError NvRmTransportInit(NvRmDeviceHandle hRmDevice)
+{
+    NvError err;
+
+    NvOsMemset(&s_TransportInfo, 0, sizeof(s_TransportInfo));
+    s_TransportInfo.hDevice = hRmDevice;
+   
+    err = NvOsMutexCreate(&s_TransportInfo.mutex);
+    if (err)
+        goto fail;
+
+#if !NVOS_IS_WINDOWS || NVOS_IS_WINDOWS_CE 
+    err = NvRmPrivXpcCreate(hRmDevice, &s_TransportInfo.hXpc);
+    if (err)
+        goto fail;
+
+    NvRmPrivTransportAllocBuffers(hRmDevice);
+#endif
+
+    if (1)  // Used in EMUTRANS mode where the buffers cannot be mapped.
+    {
+        s_TmpIsrMsgBuffer = NvOsAlloc(MAX_MESSAGE_LENGTH);
+        if (!s_TmpIsrMsgBuffer)
+            goto fail;
+    }
+
+#if LOOPBACK_PROFILE
+    {
+        NvU32             TimerAddr;
+        NvU32             TimerSize;
+        
+        NvRmModuleGetBaseAddress(hRmDevice, NvRmModuleID_TimerUs, &TimerAddr, &TimerSize);
+        // map the us counter
+        err = NvRmPhysicalMemMap(TimerAddr, TimerSize, NVOS_MEM_READ_WRITE,
+            NvOsMemAttribute_Uncached, (void*)&s_TransportInfo.pTimer);
+        if (err)
+            goto fail;
+    }
+    
+#endif
+
+#if !NVOS_IS_WINDOWS || NVOS_IS_WINDOWS_CE 
+    err = RegisterTransportInterrupt(hRmDevice);
+    if (err)
+        goto fail;
+#endif
+    s_Transport_Inited = NV_TRUE;
+    return NvSuccess;
+
+
+fail:
+#if !NVOS_IS_WINDOWS || NVOS_IS_WINDOWS_CE 
+    NvRmPrivXpcDestroy(s_TransportInfo.hXpc);
+    NvRmPrivTransportFreeBuffers(hRmDevice);
+#endif
+    NvOsFree(s_TmpIsrMsgBuffer);
+    NvOsMutexDestroy(s_TransportInfo.mutex);
+    return err;
+}
+
+/**
+ * DeInitialize the transport structures.
+ */
+void NvRmTransportDeInit(NvRmDeviceHandle hRmDevice)
+{
+    // Unregister the interrupts.
+#if !NVOS_IS_WINDOWS || NVOS_IS_WINDOWS_CE 
+    NvRmPrivXpcDestroy(s_TransportInfo.hXpc);
+    NvRmPrivTransportFreeBuffers(hRmDevice);
+    NvRmInterruptUnregister(hRmDevice, s_TransportInterruptHandle);
+    s_TransportInterruptHandle = NULL;
+#endif
+    NvOsFree(s_TmpIsrMsgBuffer);
+    NvOsMutexDestroy(s_TransportInfo.mutex);
+}
+
+
+static void
+InsertPort(NvRmDeviceHandle hDevice, NvRmTransportHandle hPort)
+{
+    hPort->pNext = s_TransportInfo.pPortHead;
+    s_TransportInfo.pPortHead = hPort;
+}
+
+
+static NvRmTransportHandle
+FindPort(NvRmDeviceHandle hDevice, char *pPortName)
+{
+    NvRmTransportHandle hPort = NULL;
+    NvRmTransportHandle hIter = NULL;
+
+    hIter = s_TransportInfo.pPortHead;
+    while (hIter)
+    {
+        if ( NvOsStrcmp(pPortName, hIter->PortName) == 0)
+        {
+            hPort = hIter;
+            break;
+        }
+        hIter = hIter->pNext;
+    }
+
+    return hPort;
+}
+
+
+// Remove the given hPort from the list of ports
+static void
+DeletePort(NvRmDeviceHandle hRmDevice, const NvRmTransportHandle hPort)
+{
+    // Pointer to the pointer alleviates all special cases in linked list walking.
+    // I wish I was clever enough to have figured this out myself. 
+
+    NvRmTransportHandle *hIter;
+
+    hIter = &s_TransportInfo.pPortHead;
+    while (*hIter)
+    {
+        if ( *hIter == hPort )
+        {
+            *hIter = (*hIter)->pNext;
+            break;
+        }
+        hIter = &(*hIter)->pNext;
+    }
+}
+
+
+
+
+/**
+ * Open the port handle with a given port name. With the same name, only two
+ * port can be open.
+ * Thread Safety: It is done inside the function.
+ */
+
+NvError
+NvRmTransportOpen(
+    NvRmDeviceHandle hRmDevice,
+    char *pPortName,
+    NvOsSemaphoreHandle RecvMessageSemaphore,
+    NvRmTransportHandle *phTransport)
+{
+    NvU32               PortNameLen;
+    NvRmTransportHandle hPartner = NULL;
+    NvRmTransportHandle hPort    = NULL;
+    NvError             err      = NvError_InsufficientMemory;
+    char                TmpName[MAX_PORT_NAME_LENGTH+1];
+
+    while (!s_Transport_Inited) {
+        // This can happen, if this API is called before avp init.
+        NvOsSleepMS(500);
+    }
+    // Look and see if this port exists anywhere.
+    if (pPortName == NULL)
+    {
+        NvOsMutexLock(s_TransportInfo.mutex);
+
+        pPortName = NvRmPrivTransportUniqueName();
+        PortNameLen = NvOsStrlen(pPortName);
+        NvOsStrncpy(TmpName, pPortName, sizeof(TmpName) );
+        pPortName = TmpName;
+
+        NvOsMutexUnlock(s_TransportInfo.mutex);
+    }
+    else
+    {
+        PortNameLen = NvOsStrlen(pPortName);
+        NV_ASSERT(PortNameLen <= MAX_PORT_NAME_LENGTH);
+    }
+
+    NvOsMutexLock(s_TransportInfo.mutex);
+    hPartner = FindPort(hRmDevice, pPortName);
+
+    if (hPartner && hPartner->hConnectedPort != NULL)
+    {
+        NvOsMutexUnlock(s_TransportInfo.mutex);
+        return NvError_TransportPortAlreadyExist;
+    }
+
+    // check if this is one of the special RPC ports used by the rm
+    if ( NvOsStrcmp(pPortName, "RPC_AVP_PORT") == 0)
+    {        
+        //If someone else wants to open this port
+        //just return the one already created.        
+        if (hPartner)
+        {
+            hPort = hPartner;
+            goto success;
+        }
+        else
+        {
+            hPort = &s_RpcAvpPortStruct;
+            hPort->RecvMessageQueue.pReceiveMsg = (void *)&s_RpcAvpQueue[0];
+        }
+    }
+    else if (NvOsStrcmp(pPortName, "RPC_CPU_PORT") == 0)
+    {
+        hPort = &s_RpcCpuPortStruct;
+        hPort->RecvMessageQueue.pReceiveMsg = (void *)&s_RpcCpuQueue[0];
+    }
+    else
+    {
+        // Create a new TransportPort
+        hPort = NvOsAlloc( sizeof(*hPort) );
+        if (!hPort)
+            goto fail;
+
+        NvOsMemset(hPort, 0, sizeof(*hPort) );
+
+        // Allocate the receive queue
+        hPort->RecvMessageQueue.pReceiveMsg = NvOsAlloc( sizeof(RmReceiveMessage) * (MAX_MESSAGE_DEPTH+1));
+        if (!hPort->RecvMessageQueue.pReceiveMsg)
+            goto fail;
+    }
+
+    NvOsStrncpy(hPort->PortName, pPortName, PortNameLen);
+    hPort->State =  PortState_Open;
+    hPort->hConnectedPort = hPartner;
+
+    if (RecvMessageSemaphore)
+    {
+        err = NvOsSemaphoreClone(RecvMessageSemaphore, &hPort->hOnPushMsgSem);
+        if (err)
+            goto fail;
+    }
+
+    hPort->RecvMessageQueue.QueueSize = MAX_MESSAGE_DEPTH+1;
+    hPort->hRmDevice = hRmDevice;
+
+    if (hPort->hConnectedPort != NULL)
+    {
+        hPort->hConnectedPort->hConnectedPort = hPort;
+    }
+    InsertPort(hRmDevice, hPort);
+
+
+    // !!! loopback info
+#if LOOPBACK_PROFILE 
+    if (NvOsStrcmp(hPort->PortName, "LOOPTEST") == 0)
+        hPort->bLoopTest = 1;
+#endif
+
+success:
+    NvOsMutexUnlock(s_TransportInfo.mutex);
+    *phTransport = hPort;
+    return NvSuccess;
+
+fail:
+    if (hPort)
+    {
+        NvOsFree(hPort->RecvMessageQueue.pReceiveMsg);
+        NvOsSemaphoreDestroy(hPort->hOnPushMsgSem);
+        NvOsFree(hPort);
+        hPort = NULL;
+    }
+    NvOsMutexUnlock(s_TransportInfo.mutex);
+
+    return err;
+}
+
+
+/**
+ * Close the transport handle
+ * Thread Safety: It is done inside the function.
+ */
+void NvRmTransportClose(NvRmTransportHandle hPort)
+{
+    NvU32 RemoteMessage[4];
+
+    if (!hPort)
+        return;
+
+    // Look and see if this port exists anywhere.
+    NV_ASSERT(hPort);
+
+    
+    NvOsMutexLock(s_TransportInfo.mutex);
+    DeletePort(hPort->hRmDevice, hPort);  // unlink this port
+
+    // Check if there is already a port waiting to connect, and if there is
+    // switch the port state to _Destroy, and signal the waiters semaphore.
+    // The "State" member is not protected by the mutex because it can be
+    // updated by the ISR.
+    while (hPort->State == PortState_Waiting)
+    {
+        NvOsAtomicCompareExchange32((NvS32*)&hPort->State, PortState_Waiting, PortState_Destroy);
+        if (hPort->State == PortState_Destroy)
+        {
+            NvOsSemaphoreSignal(hPort->hOnConnectSem);
+
+            // in this case, we can't complete the destroy, the signalled thread will
+            // have to complete.  We just return now
+            NvOsMutexUnlock(s_TransportInfo.mutex);
+            return;
+        }
+    }
+
+    if (hPort->hConnectedPort)
+    {
+        // unlink this port from the other side of the connection.
+        hPort->hConnectedPort->hConnectedPort = NULL;
+    }
+    
+    if (hPort->RemotePort)
+    {
+        RemoteMessage[0] = TransportCmd_Disconnect;
+        RemoteMessage[1] = hPort->RemotePort;
+        NvRmPrivTransportSendMessage(hPort->hRmDevice, RemoteMessage,
+            2*sizeof(NvU32), NULL, 0);
+    }
+
+    NvOsSemaphoreDestroy(hPort->hOnPushMsgSem);
+
+
+    if (hPort == &s_RpcAvpPortStruct ||
+        hPort == &s_RpcCpuPortStruct)
+    {
+        // don't free these..
+        NvOsMemset(hPort, 0, sizeof(*hPort));
+    }
+    else
+    {
+        NvOsFree(hPort->RecvMessageQueue.pReceiveMsg);
+        NvOsFree(hPort);
+    }
+
+    NvOsMutexUnlock(s_TransportInfo.mutex);
+}
+
+
+/**
+ * Wait for the connection to the other end.
+ * Thread Safety: It is done inside the function.
+ */
+NvError
+NvRmTransportWaitForConnect(
+    NvRmTransportHandle hPort,
+    NvU32 TimeoutMS)
+{
+    NvOsSemaphoreHandle hSem = NULL;
+    NvError             err  = NvSuccess;
+
+    NvOsMutexLock(s_TransportInfo.mutex);
+    if (hPort->State != PortState_Open)
+    {
+        NvOsMutexUnlock(s_TransportInfo.mutex);
+        err = NvError_TransportPortAlreadyExist;
+        goto exit_gracefully;
+    }
+
+    err = NvOsSemaphoreCreate(&hSem, 0);
+    if (err)
+    {
+        NvOsMutexUnlock(s_TransportInfo.mutex);
+        goto exit_gracefully;
+    }
+    
+    hPort->hOnConnectSem = hSem;
+    hPort->State = PortState_Waiting;
+    NvOsMutexUnlock(s_TransportInfo.mutex);
+
+    err = NvOsSemaphoreWaitTimeout(hSem, TimeoutMS);
+    if (err)
+    {
+        // we have to be careful here, the ISR _might_ happen just after the semaphore
+        // times out.
+        NvOsAtomicCompareExchange32((NvS32 *)&hPort->State, PortState_Waiting, PortState_Open);
+        NV_ASSERT(hPort->State == PortState_Open || hPort->State == PortState_Connected);
+        if (hPort->State == PortState_Connected)
+        {
+            err = NvSuccess;
+        }
+    }
+
+    NvOsMutexLock(s_TransportInfo.mutex);
+    hPort->hOnConnectSem = NULL;
+    NvOsMutexUnlock(s_TransportInfo.mutex);
+
+    if (hPort->State == PortState_Destroy)
+    {
+        // finish the destroy process
+        NvRmTransportClose(hPort);
+        err = NvError_TransportConnectionFailed;
+    }
+
+exit_gracefully:
+    NvOsSemaphoreDestroy(hSem);
+    return err;
+}
+
+
+
+static NvError
+NvRmPrivTransportWaitResponse(NvRmDeviceHandle hDevice, NvU32 *response, NvU32 ResponseLength, NvU32 TimeoutMS)
+{
+    NvU32   CurrentTime;
+    NvU32   StartTime;
+    NvU32   Response;
+    NvBool  GotResponse = NV_TRUE;
+    NvError err         = NvError_Timeout;
+    volatile NvU32 *pXpcMessage = (volatile NvU32*)s_TransportInfo.pTransmitMem;
+
+    if (pXpcMessage == NULL)
+    {
+        if (!NV_IS_AVP)
+        {
+            Response = NvRmMemRd32(s_TransportInfo.hMessageMem, 0);
+        } else
+        {
+            NV_ASSERT(0);
+            return NvSuccess;
+        }
+    }
+    else
+    {
+        Response = pXpcMessage[0];
+    }
+
+    if (Response != TransportCmd_Response)
+    {
+        GotResponse = NV_FALSE;
+
+        // response is not back yet, so spin till its here.
+        StartTime = NvOsGetTimeMS();
+        CurrentTime = StartTime;
+        while ( (CurrentTime - StartTime) < TimeoutMS )
+        {
+            if ( pXpcMessage && (pXpcMessage[0] == TransportCmd_Response) )
+            {
+                GotResponse = NV_TRUE;
+                break;
+            }
+            else if ( !pXpcMessage )
+            {
+                NV_ASSERT(!"Invalid pXpcMessage pointer is accessed");
+            }
+            CurrentTime = NvOsGetTimeMS();
+        }
+    }
+    
+    if ( pXpcMessage && GotResponse )
+    {
+        err = NvSuccess;
+        NvOsMemcpy(response, (void *)pXpcMessage, ResponseLength);
+    }
+
+    return err;
+}
+
+
+static NvError NvRmPrivTransportSendMessage(NvRmDeviceHandle hDevice,
+    NvU32 *MessageHdr, NvU32 MessageHdrLength,
+    NvU32 *Message, NvU32 MessageLength)
+{
+    NvU32 ReadData;
+
+    if (s_TransportInfo.pTransmitMem == NULL)
+    {
+        /* QT/EMUTRANS takes this code path */
+        if (!NV_IS_AVP)
+        {
+            ReadData = NvRmMemRd32(s_TransportInfo.hMessageMem, 0);
+        } else
+        {
+            NV_ASSERT(0);
+            return NvSuccess;
+        }
+    }
+    else
+    {
+        ReadData = ((volatile NvU32*)s_TransportInfo.pTransmitMem)[0];
+    }
+
+    // Check for clear to send
+    if ( ReadData != 0)
+        return NvError_TransportMessageBoxFull;  // someone else is sending a message
+
+    if (s_TransportInfo.pTransmitMem == NULL)
+    {
+        /* QT/EMUTRANS takes this code path */
+        NvRmMemWrite(s_TransportInfo.hMessageMem, 0, MessageHdr, MessageHdrLength);
+        if (Message && MessageLength)
+        {
+            NvRmMemWrite(s_TransportInfo.hMessageMem, MessageHdrLength,
+                Message, MessageLength);
+        }
+    }
+    else
+    {
+        NvOsMemcpy(s_TransportInfo.pTransmitMem, MessageHdr, MessageHdrLength);
+        if (Message && MessageLength)
+        {
+            NvOsMemcpy(s_TransportInfo.pTransmitMem + MessageHdrLength,
+                Message, MessageLength);
+        }
+        NvOsFlushWriteCombineBuffer();
+    }
+    NvRmPrivXpcSendMessage(s_TransportInfo.hXpc, s_TransportInfo.MessageMemPhysAddr);
+    return NvSuccess;
+}
+
+NvError NvRmTransportSendMsgInLP0(NvRmTransportHandle hPort,
+    void *pMessageBuffer, NvU32 MessageSize)
+{
+    NvU32 ReadData;
+    NvU32 MessageHdr[3];
+
+    NV_ASSERT(pMessageBuffer);
+
+    MessageHdr[0] = TransportCmd_Message;
+    MessageHdr[1] = hPort->RemotePort;
+    MessageHdr[2] = MessageSize;
+   
+    ReadData = ((volatile NvU32*)s_TransportInfo.pTransmitMem)[0];
+    
+    // Check for clear to send
+    if ( ReadData != 0)
+        return NvError_TransportMessageBoxFull;  // someone else is sending a message
+
+    NvOsMemcpy(s_TransportInfo.pTransmitMem, MessageHdr, sizeof(MessageHdr));
+    if (MessageSize) {
+        NvOsMemcpy(s_TransportInfo.pTransmitMem + sizeof(MessageHdr),
+            pMessageBuffer, MessageSize);
+    }
+    NvOsFlushWriteCombineBuffer();
+
+    NvRmPrivXpcSendMessage(s_TransportInfo.hXpc, s_TransportInfo.MessageMemPhysAddr);
+    return NvSuccess;
+}
+
+static void
+NvRmPrivTransportClearSend(NvRmDeviceHandle hDevice)
+{
+    if (s_TransportInfo.pTransmitMem == NULL)
+    {
+        /* QT/EMUTRANS take this path */
+        if (!NV_IS_AVP)
+        {
+            NvRmMemWr32(s_TransportInfo.hMessageMem, 0, TransportCmd_None);
+        } else
+        {
+            NV_ASSERT(0);
+        }
+    }
+    else
+    {
+        ((NvU32*)s_TransportInfo.pTransmitMem)[0] = TransportCmd_None;
+    }
+}
+
+/**
+ * Make the connection to the other end.
+ * Thread Safety: It is done inside the function.
+ */
+NvError NvRmTransportConnect(NvRmTransportHandle hPort, NvU32 TimeoutMS)
+{
+    NvRmTransportHandle hPartnerPort;
+    NvU32               StartTime;
+    NvU32               CurrentTime;
+    NvU32               ConnectMessage[ MAX_PORT_NAME_LENGTH/4 + 3];
+    NvError             err;
+    
+
+    // Look and see if there is a local port with the same name that is currently waiting, if there is
+    // mark both ports as connected.
+
+    NV_ASSERT(hPort);
+    NV_ASSERT(hPort->hRmDevice);
+    NV_ASSERT(hPort->State == PortState_Open);
+
+
+    StartTime = NvOsGetTimeMS();
+    for (;;)
+    {
+        // Someone is waiting for a connection here locally.
+        NvOsMutexLock(s_TransportInfo.mutex);
+
+        hPartnerPort = hPort->hConnectedPort;
+        if (hPartnerPort)
+        {
+            // Found a local connection
+            if (hPartnerPort->State == PortState_Waiting)
+            {
+
+                hPartnerPort->State = PortState_Connected;
+                hPartnerPort->hConnectedPort = hPort;
+
+                hPort->State = PortState_Connected;
+                NvOsSemaphoreSignal(hPartnerPort->hOnConnectSem);
+                break;
+            }
+        }
+        else if (s_TransportInfo.hMessageMem || s_TransportInfo.pReceiveMem)  // if no shared buffer, then we can't create a remote connection.
+        {
+            ConnectMessage[0] = TransportCmd_Connect;
+            ConnectMessage[1] = (NvU32)hPort;
+            NvOsMemcpy(&ConnectMessage[2], hPort->PortName, MAX_PORT_NAME_LENGTH);
+            
+            err = NvRmPrivTransportSendMessage(hPort->hRmDevice,
+                      ConnectMessage, sizeof(ConnectMessage), NULL, 0);
+            if (!err)
+            {
+                // should send back 2 words of data.  Give remote side 1000ms to respond, which should be about 100x more
+                // than it needs.
+                NvU32 WaitTime = NV_MAX(1000, TimeoutMS);
+                if (TimeoutMS == NV_WAIT_INFINITE)
+                    TimeoutMS = NV_WAIT_INFINITE;
+
+                // !!! Note, we can do this without holding the mutex...
+                err = NvRmPrivTransportWaitResponse(hPort->hRmDevice, ConnectMessage, 2*sizeof(NvU32), WaitTime);
+                NvRmPrivTransportClearSend(hPort->hRmDevice);
+                if (err)
+                {
+                    // the other side is not responding to messages, doh!
+                    NvOsMutexUnlock(s_TransportInfo.mutex);
+                    return NvError_TransportConnectionFailed;
+                }
+
+                // check the response
+                hPort->RemotePort = ConnectMessage[1];
+                if (hPort->RemotePort != 0)
+                {
+                    hPort->State = PortState_Connected;
+                    break;
+                }
+            }
+        }
+        NvOsMutexUnlock(s_TransportInfo.mutex);
+        NV_ASSERT(hPort->State == PortState_Open);  // it better still be open
+
+        // Didn't find a connection, wait a few ms and then try again
+        CurrentTime = NvOsGetTimeMS();
+        if ( (CurrentTime - StartTime) > TimeoutMS )
+            return NvError_Timeout;
+        
+        NvOsSleepMS(10);
+    }
+
+    NvOsMutexUnlock(s_TransportInfo.mutex);
+    return NvSuccess;
+}
+
+
+/**
+ * Set the queue depth and message size of the transport handle.
+ * Thread Safety: It is done inside the function.
+ */
+NvError NvRmTransportSetQueueDepth(
+    NvRmTransportHandle hPort,
+    NvU32 MaxQueueDepth,
+    NvU32 MaxMessageSize)
+{
+    RmReceiveMessage *pNewReceiveMsg = NULL;
+
+    NV_ASSERT(hPort != NULL);
+    NV_ASSERT(MaxQueueDepth != 0);
+    NV_ASSERT(MaxMessageSize != 0);
+
+    // You cannot change the queue after a connection has been opened
+    NV_ASSERT(hPort->State == PortState_Open);
+
+    // !!! FIXME
+    // Xpc does not allow changing the base message size, so we can't change the message size here (yet!)
+    // Once we have per port message buffers we can set this.
+    NV_ASSERT(MaxMessageSize <= MAX_MESSAGE_LENGTH);
+
+    // These are statically allocated ports, they cannot be modified!
+    // !!! FIXME: this is just a sanity check.  Remove this and make it so that
+    //            cpu/avp rpc doesn't call this function and just knows that the
+    //            transport will give it a port with a large enough queue to support
+    //            rpc, since rpc ports and queue are statically allocated this has to be true.
+    if (hPort == &s_RpcAvpPortStruct ||
+        hPort == &s_RpcCpuPortStruct)
+    {
+        if (MaxMessageSize <= MAX_MESSAGE_LENGTH &&
+            MaxQueueDepth <= MAX_MESSAGE_DEPTH)
+        {
+            return NvSuccess;
+        }
+        
+        NV_ASSERT(!" Illegal meesage length or queue depth. ");
+    }
+
+    // Freeing default allocated message queue.
+    NvOsFree(hPort->RecvMessageQueue.pReceiveMsg);
+    hPort->RecvMessageQueue.pReceiveMsg = NULL;
+    // create a new message queue struct, one longer than requested on purpose.
+    pNewReceiveMsg = NvOsAlloc( sizeof(RmReceiveMessage) * (MaxQueueDepth+1));
+    if (pNewReceiveMsg == NULL)
+        return NvError_InsufficientMemory;
+
+    hPort->RecvMessageQueue.pReceiveMsg = pNewReceiveMsg;
+    hPort->RecvMessageQueue.QueueSize = (NvU16)(MaxQueueDepth+1);
+
+    return NvSuccess;
+}
+
+
+static NvError
+NvRmPrivTransportSendRemoteMsg(
+    NvRmTransportHandle hPort,
+    void* pMessageBuffer,
+    NvU32 MessageSize,
+    NvU32 TimeoutMS)
+{
+    NvError err;
+    NvU32 StartTime;
+    NvU32 CurrentTime;
+    NvU32 MessageHdr[3];
+    NvU32 JiffyTime = jiffies_to_msecs(1);
+
+    NV_ASSERT((MAX_MESSAGE_LENGTH) >= MessageSize);
+
+    StartTime = NvOsGetTimeMS();
+
+    MessageHdr[0] = TransportCmd_Message;
+    MessageHdr[1] = hPort->RemotePort;
+    MessageHdr[2] = MessageSize;
+   
+    for (;;)
+    {
+        NvOsMutexLock(s_TransportInfo.mutex);
+        err = NvRmPrivTransportSendMessage(hPort->hRmDevice,
+                  MessageHdr, sizeof(MessageHdr),
+                  pMessageBuffer, MessageSize);
+        NvOsMutexUnlock(s_TransportInfo.mutex);
+        if (err == NvSuccess)
+        {
+            return NvSuccess;
+        }
+
+        // Sleep and then try again in a few ms to send again
+        CurrentTime = NvOsGetTimeMS();
+        if ( TimeoutMS != NV_WAIT_INFINITE && (CurrentTime - StartTime) > TimeoutMS )
+            return NvError_Timeout;
+        /* Sleeping for 1msec may not sleep exactly for 1msec. It depends
+         * on OS jiffy(tick) time. If jiffy time is much bigger,then this 1msec
+         * sleep would cause performance issues. At the same time, if complete
+         * polling is used, it can potentially block other threads from running.
+         * To reduce the impact of sleep in either ways, poll for one jiffy time
+         * and if operation is not complete then start sleeping.
+         */
+        if ( (CurrentTime - StartTime) > JiffyTime )
+            NvOsSleepMS(1); // try again later...
+    }
+}
+
+
+
+static NvError
+NvRmPrivTransportSendLocalMsg(
+    NvRmTransportHandle hPort,
+    void* pMessageBuffer,
+    NvU32 MessageSize,
+    NvU32 TimeoutMS)
+{
+    NvU32  CurrentTime;
+    NvU32  StartTime;
+    NvError err            = NvSuccess;
+    NvU32 JiffyTime = jiffies_to_msecs(1);
+
+    NvRmTransportHandle hRemotePort;
+
+    NvOsMutexLock(s_TransportInfo.mutex);
+    hRemotePort = hPort->hConnectedPort;
+
+
+    StartTime = NvOsGetTimeMS();
+    CurrentTime = StartTime;
+
+    for (;;)
+    {
+        // try to insert into the message into the receivers queue.
+        NvBool bSuccess = InsertMessage(hRemotePort, (NvU8*)pMessageBuffer, MessageSize);
+        if (bSuccess)
+        {
+            if (hRemotePort->hOnPushMsgSem)
+                NvOsSemaphoreSignal(hRemotePort->hOnPushMsgSem);
+            break;
+        }
+        
+        // The destination port is full.
+        if (TimeoutMS == 0)
+        {
+            err = NvError_TransportMessageBoxFull;
+            break;
+        }
+
+        // The user wants a timeout, so we just sleep a short time so the
+        // other thread can pop a message.  It would be better to use another semaphore
+        // to indicate that the box is not full, but that just seems overkill since this
+        // should rarely happen anyhow.
+        // unlock the mutex, and wait a small amount of time.
+        NvOsMutexUnlock(s_TransportInfo.mutex);
+
+        /* Sleeping for 1msec may not sleep exactly for 1msec. It depends
+         * on OS jiffy(tick) time. If jiffy time is much bigger,then this 1msec
+         * sleep would cause performance issues. At the same time, if complete
+         * polling is used, it can potentially block other threads from running.
+         * To reduce the impact of sleep in either ways, poll for one jiffy time
+         * and if operation is not complete then start sleeping.
+         */
+        if ( (CurrentTime - StartTime) > JiffyTime )
+            NvOsSleepMS(1);
+        NvOsMutexLock(s_TransportInfo.mutex);
+        if (TimeoutMS != NV_WAIT_INFINITE)
+        {
+            // check for a timeout condition.
+            CurrentTime = NvOsGetTimeMS();
+            if ( (CurrentTime - StartTime) >= TimeoutMS)
+            {
+                err = NvError_Timeout;
+                break;
+            }
+        }
+    }
+    NvOsMutexUnlock(s_TransportInfo.mutex);
+
+    return err;
+}
+
+
+/**
+ * Send the message to the other end port.
+ * Thread Safety: It is done inside the function.
+ */
+NvError
+NvRmTransportSendMsg(
+    NvRmTransportHandle hPort,
+    void* pMessageBuffer,
+    NvU32 MessageSize,
+    NvU32 TimeoutMS)
+{
+    NvError err;
+
+    NV_ASSERT(hPort);
+    NV_ASSERT(hPort->State == PortState_Connected);
+    NV_ASSERT(pMessageBuffer);
+
+#if LOOPBACK_PROFILE
+    if (hPort->bLoopTest)
+    {
+# if NV_IS_AVP
+        ((NvU32*)pMessageBuffer)[LOOP_AVP_SEND_INDEX] = *s_TransportInfo.pTimer;
+# else
+        ((NvU32*)pMessageBuffer)[LOOP_CPU_SEND_INDEX] = *s_TransportInfo.pTimer;
+# endif
+    }
+#endif
+
+    if (hPort->hConnectedPort)
+    {
+        err = NvRmPrivTransportSendLocalMsg(hPort, pMessageBuffer, MessageSize, TimeoutMS);
+    }
+    else if (hPort->State == PortState_Connected)
+    {
+        err = NvRmPrivTransportSendRemoteMsg(hPort, pMessageBuffer, MessageSize, TimeoutMS);
+    }
+    else
+    {
+        NV_ASSERT(0);  // someone did something naughty
+        err = NvError_TransportNotConnected;
+    }
+
+    return err;
+}
+
+
+
+/**
+ * Receive the message from the other end port.
+ * Thread Safety: It is done inside the function.
+ */
+NvError
+NvRmTransportRecvMsg(
+    NvRmTransportHandle hPort,
+    void* pMessageBuffer,
+    NvU32 MaxSize,
+    NvU32 *pMessageSize)
+{
+    NvU8 TmpMessage[MAX_MESSAGE_LENGTH];
+
+    NV_ASSERT(hPort);
+    NV_ASSERT( (hPort->State == PortState_Connected) || (hPort->State == PortState_Disconnected) );
+    NV_ASSERT(pMessageBuffer);
+    NV_ASSERT(pMessageSize);
+
+
+    *pMessageSize = 0;
+    NvOsMutexLock(s_TransportInfo.mutex);
+    if (hPort->RecvMessageQueue.ReadIndex == hPort->RecvMessageQueue.WriteIndex)
+    {
+        NvOsMutexUnlock(s_TransportInfo.mutex);
+        return NvError_TransportMessageBoxEmpty;
+    }
+    
+    ExtractMessage(hPort, (NvU8*)pMessageBuffer, pMessageSize, MaxSize);
+    if (*pMessageSize > MaxSize)
+    {
+        // not enough room to copy the message
+        NvOsMutexUnlock(s_TransportInfo.mutex);
+        NV_ASSERT(!" RM Transport: Illegal message size. ");
+        return NvError_InvalidSize;
+    }
+
+
+    // if there was backpressure asserted, try to handle the currently posted message, and re-enable messages
+    if (s_TransportInfo.ReceiveBackPressureOn != s_TransportInfo.ReceiveBackPressureOff)
+    {
+        NV_ASSERT( ((NvU8)s_TransportInfo.ReceiveBackPressureOn) == ((NvU8)(s_TransportInfo.ReceiveBackPressureOff+1)) );
+        ++s_TransportInfo.ReceiveBackPressureOff;
+
+        if (s_TransportInfo.pReceiveMem == NULL)
+        {
+            /* QT/EMUTRANS takes this path. */
+            NvRmMemRead(s_TransportInfo.hMessageMem, 
+                        MAX_MESSAGE_LENGTH + MAX_COMMAND_SIZE,
+                        TmpMessage,
+                        MAX_MESSAGE_LENGTH);
+            HandlePortMessage(hPort->hRmDevice, (volatile void *)TmpMessage);
+            NvRmMemWrite(s_TransportInfo.hMessageMem,
+                         MAX_MESSAGE_LENGTH + MAX_COMMAND_SIZE,
+                         TmpMessage,
+                         2*sizeof(NvU32) );
+        }
+        else
+        {
+            HandlePortMessage(hPort->hRmDevice, (NvU32*)s_TransportInfo.pReceiveMem);
+        }
+    }
+
+#if LOOPBACK_PROFILE
+    if (hPort->bLoopTest)
+    {
+# if NV_IS_AVP
+        ((NvU32*)pMessageBuffer)[LOOP_AVP_RECV_INDEX] = *s_TransportInfo.pTimer;
+# else
+        ((NvU32*)pMessageBuffer)[LOOP_CPU_RECV_INDEX] = *s_TransportInfo.pTimer;
+# endif
+    }
+#endif
+
+    NvOsMutexUnlock(s_TransportInfo.mutex);
+
+    return NvSuccess;
+}
+
+void 
+NvRmTransportGetPortName( 
+    NvRmTransportHandle hPort,
+    NvU8 *PortName,
+    NvU32 PortNameSize )
+{
+    NvU32 len;
+
+    NV_ASSERT(hPort);
+    NV_ASSERT(PortName);
+
+    len = NvOsStrlen(hPort->PortName);
+    if (len >= PortNameSize)
+    {
+        NV_ASSERT(!" RM Transport: Port Name too long. ");
+    }
+
+    NvOsStrncpy((char *)PortName, hPort->PortName, PortNameSize);
+}
+
diff --git a/arch/arm/mach-tegra/nvrm/io/ap15/Makefile b/arch/arm/mach-tegra/nvrm/io/ap15/Makefile
new file mode 100644
index 000000000000..656d900e32ad
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/io/ap15/Makefile
@@ -0,0 +1,28 @@
+ccflags-y += -DNV_IS_AVP=0
+ccflags-y += -DNV_OAL=0
+ccflags-y += -DNV_USE_FUSE_CLOCK_ENABLE=0
+ifeq ($(CONFIG_MACH_TEGRA_GENERIC_DEBUG),y)
+ccflags-y += -DNV_DEBUG=1
+else
+ccflags-y += -DNV_DEBUG=0
+endif
+
+ccflags-y += -Iarch/arm/mach-tegra/nvrm/core/common
+ccflags-y += -Iarch/arm/mach-tegra/nvrm/io/common
+ccflags-y += -Iarch/arm/mach-tegra/nvrm/io
+ccflags-y += -Iarch/arm/mach-tegra/nvrm/core
+
+obj-y += ap15rm_analog.o
+obj-y += rm_dma_hw_private.o
+obj-y += ap15rm_dma_hw_private.o
+obj-y += ap15rm_slink_hw_private.o
+obj-y += rm_common_slink_hw_private.o
+obj-y += ap15rm_i2c.o
+obj-y += ap15rm_pwm.o
+obj-y += ap15rm_gpio_vi.o
+obj-y += nvrm_dma.o
+obj-y += nvrm_gpio.o
+obj-y += nvrm_gpio_stub_helper.o
+obj-y += ap15rm_dma_intr.o
+obj-y += rm_spi_hw_private.o
+obj-y += rm_spi_slink.o
diff --git a/arch/arm/mach-tegra/nvrm/io/ap15/ap15rm_analog.c b/arch/arm/mach-tegra/nvrm/io/ap15/ap15rm_analog.c
new file mode 100644
index 000000000000..e0fdb14938b3
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/io/ap15/ap15rm_analog.c
@@ -0,0 +1,266 @@
+/*
+ * Copyright (c) 2008-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include "nvcommon.h"
+#include "nvrm_structure.h"
+#include "nvrm_analog.h"
+#include "nvrm_drf.h"
+#include "nvassert.h"
+#include "nvrm_hwintf.h"
+#include "nvrm_power.h"
+#include "ap16/arapb_misc.h"
+#include "ap15/arclk_rst.h"
+#include "ap15/arfuse.h"
+#include "nvodm_query.h"
+#include "nvodm_pmu.h"
+#include "nvrm_clocks.h"
+#include "nvrm_module.h"
+
+static NvError
+NvRmPrivTvDcControl( NvRmDeviceHandle hDevice, NvBool enable, NvU32 inst,
+    void *Config, NvU32 ConfigLength )
+{
+    NvRmAnalogTvDacConfig *cfg;
+    NvU32 ctrl, source;
+    NvU32 src_id;
+    NvU32 src_inst;
+
+    NV_ASSERT( ConfigLength == 0 ||
+        ConfigLength == sizeof(NvRmAnalogTvDacConfig) );
+
+    if( enable )
+    {
+        cfg = (NvRmAnalogTvDacConfig *)Config;
+        NV_ASSERT( cfg );
+
+        src_id = NVRM_MODULE_ID_MODULE( cfg->Source );
+        src_inst = NVRM_MODULE_ID_INSTANCE( cfg->Source );
+
+        ctrl = NV_DRF_DEF( APB_MISC_ASYNC, TVDACCNTL, DAC_IDDQ, DISABLE )
+            | NV_DRF_DEF( APB_MISC_ASYNC, TVDACCNTL, DAC_POWERDOWN, DISABLE )
+            | NV_DRF_DEF( APB_MISC_ASYNC, TVDACCNTL, DAC_DETECT_EN, ENABLE )
+            | NV_DRF_DEF( APB_MISC_ASYNC, TVDACCNTL, DAC_SLEEPR, DISABLE )
+            | NV_DRF_DEF( APB_MISC_ASYNC, TVDACCNTL, DAC_SLEEPG, DISABLE )
+            | NV_DRF_DEF( APB_MISC_ASYNC, TVDACCNTL, DAC_SLEEPB, DISABLE )
+            | NV_DRF_DEF( APB_MISC_ASYNC, TVDACCNTL, DAC_COMPR_EN, ENABLE )
+            | NV_DRF_DEF( APB_MISC_ASYNC, TVDACCNTL, DAC_COMPG_EN, ENABLE )
+            | NV_DRF_DEF( APB_MISC_ASYNC, TVDACCNTL, DAC_COMPB_EN, ENABLE );
+
+        if( src_id == NvRmModuleID_Tvo )
+        {
+            source = NV_DRF_DEF( APB_MISC_ASYNC, TVDACDINCONFIG,
+                DAC_SOURCE, TVO );
+        }
+        else
+        {
+            NV_ASSERT( src_id == NvRmModuleID_Display );
+            if( src_inst == 0 )
+            {
+                source = NV_DRF_DEF( APB_MISC_ASYNC, TVDACDINCONFIG,
+                    DAC_SOURCE, DISPLAY );
+            }
+            else
+            {
+                source = NV_DRF_DEF( APB_MISC_ASYNC, TVDACDINCONFIG,
+                    DAC_SOURCE, DISPLAYB );
+            }
+        }
+
+        source = NV_FLD_SET_DRF_NUM( APB_MISC_ASYNC, TVDACDINCONFIG, DAC_AMPIN,
+            cfg->DacAmplitude, source );
+    }
+    else
+    {
+        ctrl = NV_DRF_DEF( APB_MISC_ASYNC, TVDACCNTL, DAC_IDDQ, ENABLE )
+            | NV_DRF_DEF( APB_MISC_ASYNC, TVDACCNTL, DAC_POWERDOWN, ENABLE )
+            | NV_DRF_DEF( APB_MISC_ASYNC, TVDACCNTL, DAC_DETECT_EN, DISABLE )
+            | NV_DRF_DEF( APB_MISC_ASYNC, TVDACCNTL, DAC_SLEEPR, ENABLE )
+            | NV_DRF_DEF( APB_MISC_ASYNC, TVDACCNTL, DAC_SLEEPG, ENABLE )
+            | NV_DRF_DEF( APB_MISC_ASYNC, TVDACCNTL, DAC_SLEEPB, ENABLE )
+            | NV_DRF_DEF( APB_MISC_ASYNC, TVDACCNTL, DAC_COMPR_EN, DISABLE )
+            | NV_DRF_DEF( APB_MISC_ASYNC, TVDACCNTL, DAC_COMPG_EN, DISABLE )
+            | NV_DRF_DEF( APB_MISC_ASYNC, TVDACCNTL, DAC_COMPB_EN, DISABLE );
+        source = NV_DRF_DEF( APB_MISC_ASYNC, TVDACDINCONFIG,
+                    DAC_SOURCE, TVDAC_OFF );
+    }
+
+    NV_REGW( hDevice, NvRmModuleID_Misc, 0, APB_MISC_ASYNC_TVDACCNTL_0,
+        ctrl );
+    NV_REGW( hDevice, NvRmModuleID_Misc, 0,
+        APB_MISC_ASYNC_TVDACDINCONFIG_0, source );
+
+    return NvSuccess;
+}
+
+static NvError
+NvRmPrivVideoInputControl( NvRmDeviceHandle hDevice, NvBool enable,
+    NvU32 inst, void *Config, NvU32 ConfigLength )
+{
+    NvU32 val;
+
+    NV_ASSERT(ConfigLength == 0);
+    NV_ASSERT(Config == 0);
+    NV_ASSERT(inst == 0);
+
+    if( enable )
+    {
+        val = NV_DRF_DEF( APB_MISC_ASYNC, VCLKCTRL, VCLK_PAD_IE, ENABLE );
+    }
+    else
+    {
+        val = NV_DRF_DEF( APB_MISC_ASYNC, VCLKCTRL, VCLK_PAD_IE, DISABLE );
+    }
+
+    NV_REGW( hDevice, NvRmModuleID_Misc, 0, APB_MISC_ASYNC_VCLKCTRL_0,
+        val );
+
+    return NvSuccess;
+}
+
+
+NvError
+NvRmAnalogInterfaceControl(
+    NvRmDeviceHandle hDevice,
+    NvRmAnalogInterface Interface,
+    NvBool Enable,
+    void *Config,
+    NvU32 ConfigLength )
+{
+    NvError err = NvSuccess;
+    NvU32 id;
+    NvU32 inst;
+
+    NV_ASSERT( hDevice );
+
+    id = NVRM_ANALOG_INTERFACE_ID( Interface );
+    inst = NVRM_ANALOG_INTERFACE_INSTANCE( Interface );
+
+    NvOsMutexLock( hDevice->mutex );
+
+    switch( id ) {
+    case NvRmAnalogInterface_Dsi:
+        break;
+    case NvRmAnalogInterface_ExternalMemory:
+        break;
+    case NvRmAnalogInterface_Hdmi:
+        break;
+    case NvRmAnalogInterface_Lcd:
+        break;
+    case NvRmAnalogInterface_Uart:
+        break;
+    case NvRmAnalogInterface_Sdio:
+        break;
+    case NvRmAnalogInterface_Tv:
+        err = NvRmPrivTvDcControl( hDevice, Enable, inst, Config,
+            ConfigLength );
+        break;
+    case NvRmAnalogInterface_VideoInput:
+        err = NvRmPrivVideoInputControl( hDevice, Enable, inst, Config,
+            ConfigLength);
+        break;
+    default:
+        NV_ASSERT(!"Unknown Analog interface passed. ");
+    }
+
+    NvOsMutexUnlock( hDevice->mutex );
+
+    return err;
+}
+
+NvBool
+NvRmUsbIsConnected(
+    NvRmDeviceHandle hDevice)
+{
+    //Do nothing
+    return NV_TRUE;
+}
+
+NvU32
+NvRmUsbDetectChargerState(
+    NvRmDeviceHandle hDevice,
+    NvU32 wait)
+{
+    //Do nothing
+    return NvOdmUsbChargerType_UsbHost;
+}
+
+NvU8
+NvRmAnalogGetTvDacConfiguration(
+    NvRmDeviceHandle hDevice,
+    NvRmAnalogTvDacType Type)
+{
+    NvU8 RetVal = 0;
+    NvU32 OldRegVal = 0;
+    NvU32 NewRegVal = 0;
+
+    NV_ASSERT(hDevice);
+    
+#if NV_USE_FUSE_CLOCK_ENABLE
+    // Enable fuse clock
+    NvRmPowerModuleClockControl(hDevice, NvRmModuleID_Fuse, 0, NV_TRUE);
+#endif    
+
+    // Enable fuse values to be visible before reading the fuses.
+    OldRegVal = NV_REGR(hDevice, NvRmPrivModuleID_ClockAndReset, 0, 
+        CLK_RST_CONTROLLER_MISC_CLK_ENB_0);
+    NewRegVal = NV_FLD_SET_DRF_NUM(CLK_RST_CONTROLLER, MISC_CLK_ENB, 
+        CFG_ALL_VISIBLE, 1, OldRegVal);
+    NV_REGW(hDevice, NvRmPrivModuleID_ClockAndReset, 0, 
+        CLK_RST_CONTROLLER_MISC_CLK_ENB_0, NewRegVal);
+
+    switch (Type)
+    {
+        case NvRmAnalogTvDacType_CRT:
+            RetVal = NV_REGR(hDevice, NvRmModuleID_Fuse, 0, FUSE_DAC_CRT_CALIB_0);
+            break;
+        case NvRmAnalogTvDacType_SDTV:
+            RetVal = NV_REGR(hDevice, NvRmModuleID_Fuse, 0, FUSE_DAC_SDTV_CALIB_0);
+            break;
+        case NvRmAnalogTvDacType_HDTV:
+            RetVal = NV_REGR(hDevice, NvRmModuleID_Fuse, 0, FUSE_DAC_HDTV_CALIB_0);
+            break;
+        default:
+            NV_ASSERT(!"Unsupported this Dac type");
+            break;
+    }
+
+    // Disable fuse values visibility
+    NV_REGW(hDevice, NvRmPrivModuleID_ClockAndReset, 0, 
+        CLK_RST_CONTROLLER_MISC_CLK_ENB_0, OldRegVal);
+
+#if NV_USE_FUSE_CLOCK_ENABLE
+    // Disable fuse clock
+    NvRmPowerModuleClockControl(hDevice, NvRmModuleID_Fuse, 0, NV_FALSE);
+#endif
+
+    return RetVal; 
+}
diff --git a/arch/arm/mach-tegra/nvrm/io/ap15/ap15rm_dma_hw_private.c b/arch/arm/mach-tegra/nvrm/io/ap15/ap15rm_dma_hw_private.c
new file mode 100644
index 000000000000..d42c02701558
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/io/ap15/ap15rm_dma_hw_private.c
@@ -0,0 +1,336 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/** 
+ * @file
+ * @brief <b>nVIDIA Driver Development Kit: 
+ *           DMA Resource manager private API for Hw access </b>
+ *
+ * @b Description: Implements the private interface of the nnvrm dma to access
+ * the hw apb/ahb dma register.
+ *
+ * This files implements the API for accessing the register of the Dma 
+ * controller and configure the dma transfers for Ap15.
+ */
+
+#include "nvrm_dma.h"
+#include "rm_dma_hw_private.h"
+#include "ap20/arapbdma.h"
+#include "ap20/arapbdmachan.h"
+#include "nvrm_drf.h"
+#include "nvassert.h"
+#include "nvrm_hardware_access.h"
+
+#define APBDMACHAN_READ32(pVirtBaseAdd, reg) \
+        NV_READ32((pVirtBaseAdd) + ((APBDMACHAN_CHANNEL_0_##reg##_0)/4))
+#define APBDMACHAN_WRITE32(pVirtBaseAdd, reg, val) \
+    do { \
+        NV_WRITE32(((pVirtBaseAdd) + ((APBDMACHAN_CHANNEL_0_##reg##_0)/4)), (val)); \
+    } while(0)
+
+
+static void
+ConfigureDmaRequestor(
+    DmaChanRegisters *pDmaChRegs,
+    NvRmDmaModuleID DmaReqModuleId,
+    NvU32 DmaReqInstId)
+{
+    // Check for the dma module Id and based on the dma module Id, decide
+    // the trigger requestor source.
+    switch (DmaReqModuleId)
+    {
+        /// Specifies the dma module Id for memory
+        case NvRmDmaModuleID_Memory:
+            // Dma transfer will be from memory to memory.
+            // Use the reset value only for the ahb data transfer.
+            break;
+
+
+        case NvRmDmaModuleID_I2s:
+            // Dma requestor is the I2s controller.
+            NV_ASSERT(DmaReqInstId < 2);
+            if (DmaReqInstId == 0)
+                pDmaChRegs->ControlReg = NV_FLD_SET_DRF_DEF(APBDMACHAN_CHANNEL_0, 
+                                            CSR, REQ_SEL, I2S_1, pDmaChRegs->ControlReg);
+            else 
+                pDmaChRegs->ControlReg = NV_FLD_SET_DRF_DEF(APBDMACHAN_CHANNEL_0, 
+                                            CSR, REQ_SEL, I2S2_1, pDmaChRegs->ControlReg);
+            pDmaChRegs->ControlReg = NV_FLD_SET_DRF_DEF(APBDMACHAN_CHANNEL_0, 
+                                            CSR, FLOW, ENABLE, pDmaChRegs->ControlReg);
+            pDmaChRegs->ApbSequenceReg = NV_FLD_SET_DRF_DEF(APBDMACHAN_CHANNEL_0, 
+                                            APB_SEQ, APB_BUS_WIDTH, BUS_WIDTH_32, 
+                                            pDmaChRegs->ApbSequenceReg);
+            break;
+
+        case NvRmDmaModuleID_Uart:
+            // Dma requestor is the uart.
+            NV_ASSERT(DmaReqInstId < 5);
+            switch (DmaReqInstId)
+            {
+                default:
+                case 0:
+                    pDmaChRegs->ControlReg = NV_FLD_SET_DRF_DEF(APBDMACHAN_CHANNEL_0, 
+                            CSR, REQ_SEL, UART_A, pDmaChRegs->ControlReg);
+                    break;
+                case 1:
+                    pDmaChRegs->ControlReg = NV_FLD_SET_DRF_DEF(APBDMACHAN_CHANNEL_0, 
+                            CSR, REQ_SEL, UART_B, pDmaChRegs->ControlReg);
+                    break;
+                case 2:
+                    pDmaChRegs->ControlReg = NV_FLD_SET_DRF_DEF(APBDMACHAN_CHANNEL_0, 
+                            CSR, REQ_SEL, UART_C, pDmaChRegs->ControlReg);
+                    break;
+                case 3:
+                    pDmaChRegs->ControlReg = NV_FLD_SET_DRF_DEF(APBDMACHAN_CHANNEL_0, 
+                            CSR, REQ_SEL, UART_D, pDmaChRegs->ControlReg);
+                    break;
+                case 4:
+                    pDmaChRegs->ControlReg = NV_FLD_SET_DRF_DEF(APBDMACHAN_CHANNEL_0, 
+                            CSR, REQ_SEL, UART_E, pDmaChRegs->ControlReg);
+                    break;
+            }
+            pDmaChRegs->ControlReg = NV_FLD_SET_DRF_DEF(APBDMACHAN_CHANNEL_0, 
+                                        CSR, FLOW, ENABLE, pDmaChRegs->ControlReg);
+            pDmaChRegs->ApbSequenceReg = NV_FLD_SET_DRF_DEF(APBDMACHAN_CHANNEL_0, 
+                                        APB_SEQ, APB_BUS_WIDTH, BUS_WIDTH_8,
+                                        pDmaChRegs->ApbSequenceReg);
+            break;
+
+        case NvRmDmaModuleID_Vfir:
+            // Dma requestor is the vfir.
+            NV_ASSERT(DmaReqInstId < 1);
+            if (DmaReqInstId == 1)
+                pDmaChRegs->ControlReg = NV_FLD_SET_DRF_DEF(APBDMACHAN_CHANNEL_0, 
+                                            CSR, REQ_SEL, UART_B, pDmaChRegs->ControlReg);
+            pDmaChRegs->ControlReg = NV_FLD_SET_DRF_DEF(APBDMACHAN_CHANNEL_0, 
+                                            CSR, FLOW, ENABLE, pDmaChRegs->ControlReg);
+            pDmaChRegs->ApbSequenceReg = NV_FLD_SET_DRF_DEF(APBDMACHAN_CHANNEL_0, 
+                                            APB_SEQ, APB_BUS_WIDTH, BUS_WIDTH_32,
+                                            pDmaChRegs->ApbSequenceReg);
+            break;
+
+        case NvRmDmaModuleID_Mipi:
+            // Dma requestor is the Mipi controller.
+            NV_ASSERT(DmaReqInstId < 1);
+            pDmaChRegs->ControlReg = NV_FLD_SET_DRF_DEF(APBDMACHAN_CHANNEL_0, 
+                                            CSR, REQ_SEL, MIPI, pDmaChRegs->ControlReg);
+            pDmaChRegs->ControlReg = NV_FLD_SET_DRF_DEF(APBDMACHAN_CHANNEL_0, 
+                                            CSR, FLOW, ENABLE, pDmaChRegs->ControlReg);
+            pDmaChRegs->ApbSequenceReg = NV_FLD_SET_DRF_DEF(APBDMACHAN_CHANNEL_0, 
+                                            APB_SEQ, APB_BUS_WIDTH, BUS_WIDTH_32,
+                                            pDmaChRegs->ApbSequenceReg);
+            break;
+
+        case NvRmDmaModuleID_Spi:
+            // Dma requestor is the Spi controller.
+            NV_ASSERT(DmaReqInstId < 1);
+            pDmaChRegs->ControlReg = NV_FLD_SET_DRF_DEF(APBDMACHAN_CHANNEL_0, 
+                                            CSR, REQ_SEL, SPI, pDmaChRegs->ControlReg);
+            pDmaChRegs->ControlReg = NV_FLD_SET_DRF_NUM(APBDMACHAN_CHANNEL_0, 
+                                            CSR, TRIG_SEL, 0, pDmaChRegs->ControlReg);
+            pDmaChRegs->ControlReg = NV_FLD_SET_DRF_DEF(APBDMACHAN_CHANNEL_0, 
+                                            CSR, FLOW, ENABLE, pDmaChRegs->ControlReg);
+            pDmaChRegs->ApbSequenceReg = NV_FLD_SET_DRF_DEF(APBDMACHAN_CHANNEL_0, 
+                                            APB_SEQ, APB_BUS_WIDTH, BUS_WIDTH_32,
+                                            pDmaChRegs->ApbSequenceReg);
+            break;
+
+        case NvRmDmaModuleID_Slink:
+            // Dma requestor is the Slink controller.
+            NV_ASSERT(DmaReqInstId < 3);
+            if (DmaReqInstId == 0)
+                pDmaChRegs->ControlReg = NV_FLD_SET_DRF_DEF(APBDMACHAN_CHANNEL_0, 
+                                            CSR, REQ_SEL, SL2B1, pDmaChRegs->ControlReg);
+            else if (DmaReqInstId == 1)
+                pDmaChRegs->ControlReg = NV_FLD_SET_DRF_DEF(APBDMACHAN_CHANNEL_0, 
+                                            CSR, REQ_SEL, SL2B2, pDmaChRegs->ControlReg);
+            else
+                pDmaChRegs->ControlReg = NV_FLD_SET_DRF_DEF(APBDMACHAN_CHANNEL_0, 
+                                            CSR, REQ_SEL, SL2B3, pDmaChRegs->ControlReg);
+            
+            pDmaChRegs->ControlReg = NV_FLD_SET_DRF_NUM(APBDMACHAN_CHANNEL_0, 
+                                            CSR, TRIG_SEL, 0, pDmaChRegs->ControlReg);
+            pDmaChRegs->ControlReg = NV_FLD_SET_DRF_DEF(APBDMACHAN_CHANNEL_0, 
+                                            CSR, FLOW, ENABLE, pDmaChRegs->ControlReg);
+            pDmaChRegs->ApbSequenceReg = NV_FLD_SET_DRF_DEF(APBDMACHAN_CHANNEL_0, 
+                                            APB_SEQ, APB_BUS_WIDTH, BUS_WIDTH_32,
+                                            pDmaChRegs->ApbSequenceReg);
+            break;
+
+        case NvRmDmaModuleID_Spdif:
+            // Dma requestor is the Spdif controller.
+            NV_ASSERT(DmaReqInstId < 1);
+            pDmaChRegs->ControlReg = NV_FLD_SET_DRF_DEF(APBDMACHAN_CHANNEL_0, 
+                                            CSR, REQ_SEL, SPD_I, pDmaChRegs->ControlReg);
+            pDmaChRegs->ControlReg = NV_FLD_SET_DRF_DEF(APBDMACHAN_CHANNEL_0, 
+                                            CSR, FLOW, ENABLE, pDmaChRegs->ControlReg);
+            pDmaChRegs->ApbSequenceReg = NV_FLD_SET_DRF_DEF(APBDMACHAN_CHANNEL_0, 
+                                            APB_SEQ, APB_BUS_WIDTH, BUS_WIDTH_32,
+                                            pDmaChRegs->ApbSequenceReg);
+            break;
+
+        case NvRmDmaModuleID_I2c:
+            // Dma requestor is the I2c controller.
+            NV_ASSERT(DmaReqInstId < 3);
+            switch (DmaReqInstId)
+            {
+                default:
+                case 0:
+                    pDmaChRegs->ControlReg = NV_FLD_SET_DRF_DEF(APBDMACHAN_CHANNEL_0, 
+                                                CSR, REQ_SEL, I2C, 
+                                                    pDmaChRegs->ControlReg);
+                    break;
+                case 1:
+                    pDmaChRegs->ControlReg = NV_FLD_SET_DRF_DEF(APBDMACHAN_CHANNEL_0, 
+                                                CSR, REQ_SEL, I2C2, 
+                                                    pDmaChRegs->ControlReg);
+                    break;
+                case 2:
+                    pDmaChRegs->ControlReg = NV_FLD_SET_DRF_DEF(APBDMACHAN_CHANNEL_0, 
+                                                CSR, REQ_SEL, I2C3, 
+                                                    pDmaChRegs->ControlReg);
+                    break;
+            }
+        
+            pDmaChRegs->ControlReg = NV_FLD_SET_DRF_DEF(APBDMACHAN_CHANNEL_0, 
+                                            CSR, FLOW, ENABLE, pDmaChRegs->ControlReg);
+            pDmaChRegs->ApbSequenceReg = NV_FLD_SET_DRF_DEF(APBDMACHAN_CHANNEL_0, 
+                                            APB_SEQ, APB_BUS_WIDTH, BUS_WIDTH_32,
+                                            pDmaChRegs->ApbSequenceReg);
+            break;
+        
+        case NvRmDmaModuleID_Dvc:
+            // Dma requestor is the I2c controller.
+            NV_ASSERT(DmaReqInstId < 1);
+        
+            pDmaChRegs->ControlReg = NV_FLD_SET_DRF_DEF(APBDMACHAN_CHANNEL_0, 
+                                            CSR, REQ_SEL, DVC_I2C, pDmaChRegs->ControlReg);
+            pDmaChRegs->ControlReg = NV_FLD_SET_DRF_DEF(APBDMACHAN_CHANNEL_0, 
+                                            CSR, FLOW, ENABLE, pDmaChRegs->ControlReg);
+            pDmaChRegs->ApbSequenceReg = NV_FLD_SET_DRF_DEF(APBDMACHAN_CHANNEL_0, 
+                                            APB_SEQ, APB_BUS_WIDTH, BUS_WIDTH_32,
+                                            pDmaChRegs->ApbSequenceReg);
+            break;
+
+
+        default:
+            NV_ASSERT(!"Invalid module");
+    }
+}
+
+/**
+ * Configure the Apb dma register as per clients information.
+ * This function do the register setting based on device Id and will  be stored
+ * in the dma handle. This information will be used when there is dma transfer
+ * request and want to configure the dma controller registers.
+ */
+static void 
+InitApbDmaRegisters(
+    DmaChanRegisters *pDmaChRegs,
+    NvRmDmaModuleID DmaReqModuleId,
+    NvU32 DmaReqInstId)
+{
+    pDmaChRegs->pHwDmaChanReg = NULL;
+
+    //  Set the dma register of dma handle to their power on reset values.
+    pDmaChRegs->ControlReg = NV_RESETVAL(APBDMACHAN_CHANNEL_0, CSR);
+    pDmaChRegs->AhbSequenceReg = NV_RESETVAL(APBDMACHAN_CHANNEL_0, AHB_SEQ);
+    pDmaChRegs->ApbSequenceReg = NV_RESETVAL(APBDMACHAN_CHANNEL_0,APB_SEQ);
+
+    // Configure the dma register for the OnceMode
+    pDmaChRegs->ControlReg = NV_FLD_SET_DRF_DEF(APBDMACHAN_CHANNEL_0, CSR, 
+                                ONCE, SINGLE_BLOCK, pDmaChRegs->ControlReg);
+
+    // Configure the dma register for  enabling the interrupt so that it will generate the interrupt
+    // after transfer completes.
+    pDmaChRegs->ControlReg = NV_FLD_SET_DRF_DEF(APBDMACHAN_CHANNEL_0, CSR, 
+                                IE_EOC, ENABLE, pDmaChRegs->ControlReg);
+
+    // Configure the dma register for  interrupting the cpu only.
+    pDmaChRegs->AhbSequenceReg = NV_FLD_SET_DRF_DEF(APBDMACHAN_CHANNEL_0, 
+                                AHB_SEQ, INTR_ENB, CPU, pDmaChRegs->AhbSequenceReg);
+
+    // Configure the dma registers as per requestor information.
+    ConfigureDmaRequestor(pDmaChRegs, DmaReqModuleId, DmaReqInstId);
+}
+
+/**
+ * Set the data transfer mode for the dma transfer.
+ */
+static void 
+SetApbDmaTransferMode(
+    DmaChanRegisters *pDmaChRegs,
+    NvBool IsContinuousMode,
+    NvBool IsDoubleBuffMode)
+{
+    // Configure the dma register for the Continuous Mode
+    if (IsContinuousMode)
+        pDmaChRegs->ControlReg = NV_FLD_SET_DRF_DEF(APBDMACHAN_CHANNEL_0, 
+                                    CSR, ONCE, MULTIPLE_BLOCK, pDmaChRegs->ControlReg);
+    else
+        pDmaChRegs->ControlReg = NV_FLD_SET_DRF_DEF(APBDMACHAN_CHANNEL_0, 
+                                    CSR, ONCE, SINGLE_BLOCK, pDmaChRegs->ControlReg);
+
+    // Configure the dma register for the double buffering Mode
+    if (IsDoubleBuffMode)
+        pDmaChRegs->AhbSequenceReg = NV_FLD_SET_DRF_DEF(APBDMACHAN_CHANNEL_0, 
+                                    AHB_SEQ, DBL_BUF, RELOAD_FOR_2X_BLOCKS, 
+                                    pDmaChRegs->AhbSequenceReg);
+    else
+        pDmaChRegs->AhbSequenceReg = NV_FLD_SET_DRF_DEF(APBDMACHAN_CHANNEL_0, 
+                                    AHB_SEQ, DBL_BUF, RELOAD_FOR_1X_BLOCKS, 
+                                    pDmaChRegs->AhbSequenceReg);
+}
+
+/**
+ * Set the Apb dma direction of data transfer.
+ */
+static void 
+SetApbDmaDirection(
+    DmaChanRegisters *pDmaChRegs,
+    NvBool IsSourceAddPerType)
+{
+    if (IsSourceAddPerType)
+        pDmaChRegs->ControlReg = NV_FLD_SET_DRF_DEF(APBDMACHAN_CHANNEL_0,
+                                    CSR, DIR, AHB_WRITE, pDmaChRegs->ControlReg);
+    else
+        pDmaChRegs->ControlReg = NV_FLD_SET_DRF_DEF(APBDMACHAN_CHANNEL_0,
+                                    CSR, DIR, AHB_READ, pDmaChRegs->ControlReg);
+}
+
+void NvRmPrivDmaInitAp15DmaHwInterfaces(DmaHwInterface *pApbDmaInterface)
+{
+
+    pApbDmaInterface->DmaHwInitRegistersFxn = InitApbDmaRegisters;
+    pApbDmaInterface->DmaHwSetTransferModeFxn = SetApbDmaTransferMode;
+    pApbDmaInterface->DmaHwSetDirectionFxn = SetApbDmaDirection;
+}
diff --git a/arch/arm/mach-tegra/nvrm/io/ap15/ap15rm_dma_intr.c b/arch/arm/mach-tegra/nvrm/io/ap15/ap15rm_dma_intr.c
new file mode 100644
index 000000000000..0e8761264287
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/io/ap15/ap15rm_dma_intr.c
@@ -0,0 +1,94 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/**
+ * @file
+ * @brief <b>nVIDIA Driver Development Kit:
+ *           DMA Resource manager private API for Hw access </b>
+ *
+ * @b Description: Implements the private interface of the hw access NvRM DMA.
+ * This files implements the API for accessing the register of the AP15 Dma
+ * controller.
+ *
+ */
+
+#include "nvcommon.h"
+#include "nvrm_interrupt.h"
+#include "nvassert.h"
+#include "nvrm_hwintf.h"
+#include "nvrm_processor.h"
+#include "nvrm_drf.h"
+#include "ap15/arapbdma.h"
+#include "rm_dma_hw_private.h"
+
+#define NV_APB_DMA_REGR(rm,reg)                NV_REGR(rm, NvRmPrivModuleID_ApbDma, 0, APBDMA_##reg##_0)
+#define NV_APB_DMA_REGW(rm,reg,data)           NV_REGW(rm, NvRmPrivModuleID_ApbDma, 0, APBDMA_##reg##_0, data)
+
+NvU32 NvRmPrivDmaInterruptDecode(NvRmDeviceHandle hRmDevice )
+{
+    NvU32   Channel;
+    NvU32   Reg;
+
+    // Read the APB DMA channel interrupt status register.
+    Reg = NV_APB_DMA_REGR(hRmDevice, IRQ_STA_CPU);
+
+    // Get the interrupting channel number.
+    Channel = 31 - CountLeadingZeros(Reg);
+
+    // Get the interrupt disable mask.
+    Reg = 1 << Channel;
+
+    // Disable the source.
+    NV_APB_DMA_REGW(hRmDevice, IRQ_MASK_CLR, Reg);
+
+    return Channel;
+}
+
+void NvRmPrivDmaInterruptEnable(NvRmDeviceHandle hRmDevice, NvU32 Channel, NvBool Enable )
+{
+    NvU32   Reg;
+
+    // Generate the channel mask.
+    Reg = 1 << Channel;
+
+    if (Enable)
+    {
+        // Enable the channel interrupt.
+        NV_APB_DMA_REGW(hRmDevice, IRQ_MASK_SET, Reg);
+    }
+    else
+    {
+        // Disable the channel interrupt.
+        NV_APB_DMA_REGW(hRmDevice, IRQ_MASK_CLR, Reg);
+    }
+}
+
diff --git a/arch/arm/mach-tegra/nvrm/io/ap15/ap15rm_gpio_vi.c b/arch/arm/mach-tegra/nvrm/io/ap15/ap15rm_gpio_vi.c
new file mode 100644
index 000000000000..c887a592f3f6
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/io/ap15/ap15rm_gpio_vi.c
@@ -0,0 +1,341 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+#include "ap15/ap15rm_gpio_vi.h"
+#include "nvrm_pmu.h"
+#include "nvrm_gpio.h"
+#include "nvos.h"
+#include "ap15/ap15rm_private.h"
+#include "ap15/arvi.h"
+#include "nvrm_structure.h"
+#include "nvrm_hwintf.h"
+#include "nvodm_query_discovery.h"
+#include "nvassert.h"
+
+#define NV_ENABLE_VI_POWER_RAIL 1
+
+static NvU32 s_ViRegState = 0;
+static NvU32 s_ViPowerID = 0;
+static NvU32 s_PowerClientRefCount = 0;
+static NvOdmPeripheralConnectivity const *s_pConnectivity = NULL;
+
+// Use a boolean array for easy lookup of
+// which pins are available. Initialize the useable
+// ones to TRUE. Only hazard, is one could release 
+// an invalid pin, then come back and acquire it.
+// but, that would just be dumb, and it is their own
+// fault for being dumb.
+static NvBool s_AvailableViPinList[] =
+{
+    NV_TRUE,  // VGP0
+    NV_TRUE,  // VD10
+    NV_TRUE,  // VD11
+    NV_TRUE,  // VGP3
+    NV_TRUE,  // VGP4
+    NV_TRUE,  // VGP5
+    NV_TRUE,  // VGP6
+};
+
+NvError
+NvRmPrivGpioViAcquirePinHandle(
+        NvRmDeviceHandle hRm,
+        NvU32 pinNumber)
+{
+    NvU32 addr = VI_PIN_OUTPUT_ENABLE_0*4;
+    NvU32 data = 0;
+    NvError status;
+
+    NV_ASSERT(hRm != NULL);
+
+    if (pinNumber >= NV_ARRAY_SIZE(s_AvailableViPinList))
+    {
+        return NvError_BadValue;
+    }
+
+    // Track the VGP's that VI has
+    if (!s_AvailableViPinList[pinNumber])
+    {
+        return NvError_AlreadyAllocated;
+    }
+
+    // In order to ensure that we don't do all these Power calls more than
+    // once, refcount it.  This function and it's inverse (Acquire/Release)
+    // are protected by a mutex one level up, so this refcount is safe.
+    if (s_PowerClientRefCount == 0)
+    {
+        // turn on vi clock, reset, and power
+        s_ViPowerID = NVRM_POWER_CLIENT_TAG('V','I',' ',' ');
+        status = NvRmPowerRegister(hRm, NULL, &s_ViPowerID);
+        if (status != NvSuccess)
+            goto power_stuff_failed;
+
+        status = NvRmPowerVoltageControl( hRm,
+                                    NvRmModuleID_Vi,
+                                    s_ViPowerID,
+                                    NvRmVoltsUnspecified,
+                                    NvRmVoltsUnspecified,
+                                    NULL, 0, NULL);
+        if (status != NvSuccess)
+            goto power_stuff_failed;
+
+        status = NvRmPowerModuleClockControl(hRm,
+                                    NvRmModuleID_Vi,
+                                    s_ViPowerID,
+                                    NV_TRUE);
+        if (status != NvSuccess)
+            goto power_stuff_failed;
+
+        status = NvRmPowerModuleClockConfig(hRm,
+                                    NvRmModuleID_Vi,
+                                    s_ViPowerID,
+                                    NvRmFreqUnspecified,
+                                    NvRmFreqUnspecified,
+                                    NULL, 0, NULL,
+                                    NvRmClockConfig_ExternalClockForPads |
+                                    NvRmClockConfig_InternalClockForCore);
+        if (status != NvSuccess)
+            goto power_stuff_failed;
+
+#if NV_ENABLE_VI_POWER_RAIL
+        status = NvRmPrivGpioViPowerRailConfig(hRm, NV_TRUE);
+        if (status != NvSuccess)
+            goto power_stuff_failed;
+#endif
+        status = NvRmSetModuleTristate(hRm, NvRmModuleID_Vi, NV_FALSE); 
+        if (status != NvSuccess)
+            goto power_stuff_failed;
+    }
+
+    s_PowerClientRefCount++;
+
+    // We will just go ahead and enable all the output pins
+    // that can be used.
+    #define ENABLE_PIN(_name_) \
+        (VI_PIN_OUTPUT_ENABLE_0_##_name_##_OUTPUT_ENABLE_SHIFT)
+    data |= 1 << ENABLE_PIN(VGP6);
+    data |= 1 << ENABLE_PIN(VGP5);
+    data |= 1 << ENABLE_PIN(VGP4);
+    data |= 1 << ENABLE_PIN(VGP3);
+    data |= 1 << ENABLE_PIN(VD11);
+    data |= 1 << ENABLE_PIN(VD10);
+    data |= 1 << ENABLE_PIN(VGP0);
+    #undef ENABLE_PIN
+    NV_REGW(hRm, NvRmModuleID_Vi, 0, addr, data);
+
+    s_AvailableViPinList[pinNumber] = NV_FALSE;
+    return NvSuccess;
+
+power_stuff_failed:
+
+    // TODO: robustly handle if a few NvRmPower (etc) calls worked before we
+    // hit a failure.  Possibly need to undo each call that succeeded in
+    // reverse order?
+
+    if (s_ViPowerID)
+    {
+        NvRmPowerUnRegister(hRm, s_ViPowerID);
+        s_ViPowerID = 0;
+    }
+
+    return status;
+}
+
+void NvRmPrivGpioViReleasePinHandles(
+        NvRmDeviceHandle hRm,
+        NvU32 pin)
+{
+    NvError status;
+
+    // if already available, return
+    if (s_AvailableViPinList[pin])
+        return;
+
+    // release the pin
+    s_AvailableViPinList[pin] = NV_TRUE;
+
+    s_PowerClientRefCount--;
+
+    if (s_PowerClientRefCount == 0)
+    {
+        // turn off vi clock, reset, and power
+        NV_ASSERT(s_ViPowerID);
+#if NV_ENABLE_VI_POWER_RAIL
+        /* Disable power rail */
+        status = NvRmPrivGpioViPowerRailConfig(hRm, NV_FALSE);
+        NV_ASSERT((status == NvSuccess) && "PowerRailConfig failed");
+#endif
+        /* Power down vi block */
+        // Disable module clock
+        status = NvRmPowerModuleClockControl(hRm,
+                                        NvRmModuleID_Vi,
+                                        s_ViPowerID,
+                                        NV_FALSE);
+        NV_ASSERT((status == NvSuccess) && "PowerModuleClockControl failed");
+
+        // Disable module power
+        status = NvRmPowerVoltageControl(hRm,
+                                    NvRmModuleID_Vi,
+                                    s_ViPowerID,
+                                    NvRmVoltsOff,
+                                    NvRmVoltsOff,
+                                    NULL, 0, NULL);
+        NV_ASSERT((status == NvSuccess) && "PowerVoltageControl failed");
+
+        // Unregister itself as power client
+        NvRmPowerUnRegister(hRm, s_ViPowerID);
+        s_ViPowerID = 0;
+
+        status = NvRmSetModuleTristate(hRm, NvRmModuleID_Vi, NV_TRUE); 
+        NV_ASSERT((status == NvSuccess) && "SetModuleTrisate failed");
+    }
+    return;
+}
+
+static NvU32 TranslatePinToViRegShift(NvU32 pin)
+{
+    NvU32 shift;
+    if ((pin == 1) || (pin == 2)) // mapped to VD10 and VD11
+    {
+        shift = (pin-1) + VI_PIN_OUTPUT_DATA_0_VD10_OUTPUT_DATA_SHIFT;
+    }
+    else if (pin <= 6) // only VGP0 to VGP6 exist
+    {
+        shift = pin + VI_PIN_OUTPUT_DATA_0_VGP0_OUTPUT_DATA_SHIFT;
+    }
+    else
+    {
+        shift = 0xFFFFFFFF; // illegal pin choice
+    }
+    return shift;
+}
+
+NvU32 NvRmPrivGpioViReadPins(
+        NvRmDeviceHandle hRm,
+        NvU32 pin )
+{
+    NvU32 shift = TranslatePinToViRegShift(pin);
+    // just return the shadowed value for now,
+    // since we aren't going to configure the vi gpio for input
+    // as it could potentially conflict with the sensor pins
+    if (shift == 0xFFFFFFFF)
+    {
+        return 0; // illegal pin choice
+    }
+    else
+    {
+        return (s_ViRegState >> shift) & 0x1;
+    }
+}
+
+void NvRmPrivGpioViWritePins(
+        NvRmDeviceHandle hRm,
+        NvU32 pin,
+        NvU32 pinState )
+{
+    NvU32 addr = VI_PIN_OUTPUT_DATA_0*4;
+    NvU32 shift = TranslatePinToViRegShift(pin);
+
+    if (shift == 0xFFFFFFFF)
+    {
+        return; // illegal pin choice
+    }
+
+    s_ViRegState &= ~(1 << shift); // clear
+    if (pinState)
+    {
+        s_ViRegState |= 1 << shift; // set
+    }
+    // write s_ViRegState to VI
+    NV_REGW(hRm, NvRmModuleID_Vi, 0, addr, s_ViRegState);
+    return;
+}
+
+NvBool NvRmPrivGpioViDiscover(
+        NvRmDeviceHandle hRm)
+{
+    NvU64 guid = NV_VDD_VI_ODM_ID;
+
+    if (s_pConnectivity)
+    {
+        return NV_TRUE;
+    }
+
+    /* get the connectivity info */
+    s_pConnectivity = NvOdmPeripheralGetGuid( guid );
+    if ( !s_pConnectivity )
+    {
+        return NV_FALSE;
+    }
+
+    return NV_TRUE;
+}
+
+NvError 
+NvRmPrivGpioViPowerRailConfig(
+        NvRmDeviceHandle hRm,
+        NvBool Enable)
+{
+    NvU32 i;
+    NvRmPmuVddRailCapabilities RailCaps;
+    NvU32 SettlingTime;
+    
+    if ( !NvRmPrivGpioViDiscover(hRm) )
+    {
+        return NvError_ModuleNotPresent;
+    }
+
+    for (i = 0; i < (s_pConnectivity->NumAddress); i++)
+    {
+        // Search for the vdd rail entry
+        if (s_pConnectivity->AddressList[i].Interface == NvOdmIoModule_Vdd)
+        {
+            if (Enable)
+            {
+                NvRmPmuGetCapabilities(hRm,
+                    s_pConnectivity->AddressList[i].Address, &RailCaps);
+                NvRmPmuSetVoltage(hRm,
+                    s_pConnectivity->AddressList[i].Address,
+                    RailCaps.requestMilliVolts, &SettlingTime);
+            }
+            else
+            {
+                NvRmPmuSetVoltage(hRm,
+                    s_pConnectivity->AddressList[i].Address,
+                    ODM_VOLTAGE_OFF, &SettlingTime);
+            }
+            if (SettlingTime)
+                NvOsWaitUS(SettlingTime);
+        }
+    }
+    return NvSuccess;
+ 
+}
+
diff --git a/arch/arm/mach-tegra/nvrm/io/ap15/ap15rm_gpio_vi.h b/arch/arm/mach-tegra/nvrm/io/ap15/ap15rm_gpio_vi.h
new file mode 100644
index 000000000000..07d1c055f2b8
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/io/ap15/ap15rm_gpio_vi.h
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef AP15RM_GPIO_VI_H
+#define AP15RM_GPIO_VI_H
+
+#include "nvcommon.h"
+#include "nvrm_init.h"
+
+NvError
+NvRmPrivGpioViAcquirePinHandle(
+        NvRmDeviceHandle hRm,
+        NvU32 pinNumber);
+
+void NvRmPrivGpioViReleasePinHandles(
+        NvRmDeviceHandle hRm,
+        NvU32 pin);
+
+NvU32 NvRmPrivGpioViReadPins(
+        NvRmDeviceHandle hRm,
+        NvU32 pin );
+
+void NvRmPrivGpioViWritePins(
+        NvRmDeviceHandle hRm,
+        NvU32 pin,
+        NvU32 pinState );
+NvError 
+NvRmPrivGpioViPowerRailConfig(
+        NvRmDeviceHandle hRm,
+        NvBool Enable);
+
+NvBool NvRmPrivGpioViDiscover(
+        NvRmDeviceHandle hRm);
+
+#endif /* AP15RM_GPIO_VI_H */
diff --git a/arch/arm/mach-tegra/nvrm/io/ap15/ap15rm_i2c.c b/arch/arm/mach-tegra/nvrm/io/ap15/ap15rm_i2c.c
new file mode 100644
index 000000000000..7373390ac80b
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/io/ap15/ap15rm_i2c.c
@@ -0,0 +1,742 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/** @file
+ * @brief <b>NVIDIA Driver Development Kit: I2C API</b>
+ *
+ * @b Description: Contains the NvRM I2C implementation.
+ */
+
+#include "nvrm_i2c.h"
+#include "nvrm_i2c_private.h"
+#include "nvrm_drf.h"
+#include "nvos.h"
+#include "nvrm_module.h"
+#include "ap20/ari2c.h"
+#include "nvrm_hardware_access.h"
+#include "nvrm_power.h" 
+#include "nvrm_interrupt.h"
+#include "nvassert.h"
+#include "ap20/ardvc.h"
+#include "nvodm_query_pinmux.h"
+#include "nvrm_pinmux.h"
+#include "nvrm_chiplib.h"
+#include "nvrm_hwintf.h"
+
+
+#define I2C_PACKET_SIZE 8
+
+/* Register access Macros */
+#define I2C_REGR(c, reg) NV_REGR((c)->hRmDevice, (c)->ModuleId, (c)->Instance,  \
+                    (c)->I2cRegisterOffset + I2C_##reg##_0 ); \
+
+#define I2C_REGW(c, reg, val) NV_REGW((c)->hRmDevice, (c)->ModuleId, (c)->Instance, \
+        ((c)->I2cRegisterOffset + I2C_##reg##_0), (val) );
+
+#define DVC_REGR(c, reg)    NV_REGR((c)->hRmDevice, NvRmModuleID_Dvc, (c)->Instance, DVC_##reg##_0)
+#define DVC_REGW(c, reg, val)   NV_REGW((c)->hRmDevice, NvRmModuleID_Dvc, (c)->Instance, DVC_##reg##_0, val )
+
+static void I2cIsr(void* args)
+{
+    NvRmI2cController* c = args;
+    NvU32 status_register;
+    NvU32 FailedByte;
+
+    // Read the status register
+    status_register = I2C_REGR(c, I2C_STATUS);
+
+    if (status_register)
+    {    
+        FailedByte = (NV_DRF_VAL(I2C, I2C_STATUS, CMD1_STAT, status_register) + 
+                NV_DRF_VAL(I2C, I2C_STATUS, CMD2_STAT, status_register));
+        if (FailedByte == 0)
+        {
+            NV_ASSERT(!"Something wrong with the controller, got interrupt when the controller is busy");
+        }
+        if (FailedByte == 1)
+        {
+            /* If the first byte is failed then, it means there is no ACK on the 
+             * address phase.i.e there is no device with that address */
+            c->I2cTransferStatus = NvError_I2cDeviceNotFound;
+        }
+        else 
+        {
+            /* It failed on some subsequent bytes, just report the transcation 
+             * as failed */
+            if (c->TransactionType == I2C_READ)
+            {
+                c->I2cTransferStatus = NvError_I2cReadFailed;
+            }
+            else
+            {
+                c->I2cTransferStatus = NvError_I2cWriteFailed;
+            }
+        }
+        NvOsSemaphoreSignal(c->I2cSyncSemaphore);
+        NvRmInterruptDone(c->I2CInterruptHandle);
+        return;
+    }
+    
+    c->I2cTransferStatus = NvSuccess;
+    NvOsSemaphoreSignal(c->I2cSyncSemaphore);
+
+    NvRmInterruptDone(c->I2CInterruptHandle);
+}
+
+static void DvcIsr(void* args)
+{
+    NvRmI2cController* c = args;
+
+    //  The DVC module interrupt is not cleared until the DVC_STATUS_REG0 register
+    //  is written
+    DVC_REGW(c, STATUS_REG, NV_DRF_NUM(DVC, STATUS_REG, I2C_DONE_INTR, 1));
+    I2cIsr(args);
+}
+
+static void 
+NvRmPrivI2cOalPoll(
+    NvRmI2cController *c)
+{
+    NvU32 busy = 1;
+    NvU32 status_register = 0;
+    NvU32 FailedByte;
+    NvU32 count;
+    NvU32 timeout = c->timeout;
+
+    /* Assume success as a default condition */
+    c->I2cTransferStatus = NvSuccess;
+
+    do
+    {
+        count = 20;
+        while (count)
+        {
+            /* Assume a best case transfer of 400KHz I2C clock and 2 byte transfer: 
+             *  (i.e 1 address byte and 1 data byte )
+             * It should complete in around 50 micro sec */
+            NvOsWaitUS(50);
+            status_register = I2C_REGR(c, I2C_STATUS);
+            busy = NV_DRF_VAL(I2C, I2C_STATUS, BUSY, status_register);
+            if (busy == 0)
+            {
+                goto done_polling;
+            }
+            count -= 1;
+        }
+        /* Above loop takes around 1 msec */
+    } while (timeout-- );
+    
+done_polling:
+
+    if (busy)
+    {
+        /* Something bad happened, controller cannot complete the transaction in
+         * the time specified. */
+        c->I2cTransferStatus = NvError_Timeout;
+    } else 
+    {
+        if (c->ModuleId == NvRmModuleID_Dvc)
+        {
+            DVC_REGW(c, STATUS_REG, NV_DRF_NUM(DVC, STATUS_REG, I2C_DONE_INTR, 1));
+        }
+
+        /* Transfer completed, check the status */
+        FailedByte = NV_DRF_VAL(I2C, I2C_STATUS, CMD1_STAT, status_register) + 
+            NV_DRF_VAL(I2C, I2C_STATUS, CMD2_STAT, status_register);
+
+        if (FailedByte != 0)
+        {
+            if (FailedByte == 1)
+            {
+                /* If the first byte is failed then, it means there is no ACK on the
+                 * address phase.i.e there is no device with that address */
+                c->I2cTransferStatus = NvError_I2cDeviceNotFound;
+            }
+            else
+            {
+                /* It failed on some subsequent bytes, just report the transcation 
+                 * as failed */
+                if (c->TransactionType == I2C_READ)
+                {
+                    c->I2cTransferStatus = NvError_I2cReadFailed;
+                } else
+                {
+                    c->I2cTransferStatus = NvError_I2cWriteFailed;
+                }
+            }
+        }    
+    }
+    return;
+}
+
+static NvBool AP15RmI2cGetGpioPins(
+    NvRmI2cController *c,
+    NvU32 I2cPinMap, 
+    NvU32 *Scl,
+    NvU32 *Sda)
+{
+    NvU32 SclPin = 0;
+    NvU32 SdaPin = 0;
+    NvU32 SclPort = 0;
+    NvU32 SdaPort = 0;
+    NvBool Result = NV_TRUE;
+
+    NV_ASSERT((Scl != NULL) && (Sda != NULL));
+
+    //  FIXME:  All of this should be moved over to the pin mux module,
+    //  rather than the I2C module.
+    if (c->ModuleId == NvRmModuleID_I2c)
+    {
+        switch ((c->Instance<<4) | I2cPinMap)
+        {
+        case ((0<<4) | 1):
+            SclPin = 4;
+            SdaPin = 5;
+            SclPort = 'c' - 'a';
+            SdaPort = 'c' - 'a';
+            break;
+        case ((0<<4) | 2):
+            SclPin = 5;
+            SdaPin = 6;
+            SclPort = 'k' - 'a';
+            SdaPort = 'k' - 'a';
+            break;
+        case ((0<<4) | 3):
+            SclPin = 2;
+            SdaPin = 3;
+            SclPort = 'w' - 'a';
+            SdaPort = 'w' - 'a';
+            break;
+            /*  NOTE:  The pins used in Pin Map 1 do not have a GPIO controller
+             *  connected to them (VGP pins), so the software I2C implementation
+             *  is not supported for this pin mux configuration */
+        case ((1<<4) | 2):
+            SclPin = 5;
+            SdaPin = 6;
+            SclPort = 't' - 'a';
+            SdaPort = 't' - 'a';
+            break;
+        case ((1<<4) | 3):
+            SclPin = 7;
+            SdaPin = 1;
+            SclPort = 'v' - 'a';
+            SdaPort = 'w' - 'a';
+            break;
+        case ((1<<4) | 4):
+            SclPin = 5;
+            SdaPin = 4;
+            SclPort = 'm' - 'a';
+            SdaPort = 'm' - 'a';
+            break;
+        default:
+            Result = NV_FALSE;
+            break;
+        }
+    }
+    else if (c->ModuleId == NvRmModuleID_Dvc && 
+             c->Instance == 0 &&
+             I2cPinMap == NvOdmI2cPmuPinMap_Config1)
+    {
+        SclPin = 6;
+        SdaPin = 7;
+        SclPort = 'q' - 'a';
+        SdaPort = 'q' - 'a';
+    }
+    else
+        Result = NV_FALSE;
+
+    *Scl = SclPin | (SclPort << 16);
+    *Sda = SdaPin | (SdaPort << 16);
+    
+    return Result;
+}
+
+
+static void AP15RmI2cClose(NvRmI2cController *c)
+{
+    if (c->I2cSyncSemaphore)
+    {
+        NvRmInterruptUnregister(c->hRmDevice, c->I2CInterruptHandle);
+        NvOsSemaphoreDestroy(c->I2cSyncSemaphore);
+        c->I2cSyncSemaphore = NULL;
+        c->I2CInterruptHandle = NULL;
+    }
+    c->receive = 0;
+    c->send = 0;
+    c->repeatStart = 0;
+    c->close = 0;
+    c->GetGpioPins = 0;
+}
+
+static NvError 
+AP15RmI2cReceive(
+    NvRmI2cController* c,
+    NvU8*  pBuffer,
+    const NvRmI2cTransactionInfo *pTransaction,
+    NvU32* pBytesTransferred)
+{
+    NvU32 val = 0;
+    NvU32 ByteCount;
+    NvU32 fifo[2];
+
+    NV_ASSERT(pBuffer);
+    NV_ASSERT(pTransaction->NumBytes > 0);
+
+
+    // If requested i2c is dvc i2c, then disable dvc hardware from using the dvc i2c bus.
+    if (c->ModuleId == NvRmModuleID_Dvc)
+    {
+        val = DVC_REGR(c, CTRL_REG3);
+        val = NV_FLD_SET_DRF_DEF(DVC, CTRL_REG3, I2C_HW_SW_PROG, SW, val);
+        val = NV_FLD_SET_DRF_DEF(DVC, CTRL_REG3, I2C_DONE_INTR_EN, ENABLE, val);
+        DVC_REGW(c, CTRL_REG3, val);
+
+        val = DVC_REGR(c, CTRL_REG1);
+        val = NV_FLD_SET_DRF_DEF(DVC, CTRL_REG1, INTR_EN, ENABLE, val);
+        DVC_REGW(c, CTRL_REG1, val);
+    }
+
+    val = 0;
+
+    if (c->EnableNewMaster)
+    {
+        // Enable new master if it is available
+        val |= NV_DRF_DEF(I2C, I2C_CNFG, NEW_MASTER_FSM, ENABLE);
+    }
+
+    /* 7 bit address */
+    if (c->Is10BitAddress == NV_FALSE)
+    {
+        /* write the slave address */
+        I2C_REGW(c, I2C_CMD_ADDR0, (pTransaction->Address | 1));
+
+        // Configure for read trasaction
+        val |= NV_DRF_DEF(I2C, I2C_CNFG, CMD1, ENABLE);
+        // Configure the slave address type as 7bit address
+        val |= NV_DRF_DEF(I2C, I2C_CNFG, A_MOD,
+                        SEVEN_BIT_DEVICE_ADDRESS);
+    }
+     /* 10 bit address */
+    else
+    {
+        /* write the slave address */
+        I2C_REGW(c, I2C_CMD_ADDR0, pTransaction->Address);
+
+        // Configure for read trasaction
+        val |= NV_DRF_DEF(I2C, I2C_CNFG, CMD1, ENABLE);
+        // Configure the slave address type as 10bit address
+        val |= NV_DRF_DEF(I2C, I2C_CNFG, A_MOD,
+                        TEN_BIT_DEVICE_ADDRESS);
+    }
+
+    if (c->NoACK)
+    {
+        val |= NV_DRF_DEF(I2C, I2C_CNFG, NOACK, ENABLE);
+    }
+
+    // Calculate the number of bytes that can be read
+    ByteCount = (pTransaction->NumBytes > I2C_PACKET_SIZE) ?
+                    I2C_PACKET_SIZE : pTransaction->NumBytes;
+
+    // Initialize the I2C param structure
+    c->TransactionType = I2C_READ;
+    c->I2cTransferStatus = NvError_Timeout;
+        
+    // Configure the number of bytes to be read
+    val |= NV_DRF_NUM(I2C, I2C_CNFG, LENGTH, ByteCount - 1);
+    // disable repeated start
+    val |= NV_DRF_DEF(I2C, I2C_CNFG, SLV2, DISABLE);
+    I2C_REGW(c, I2C_CNFG, val);
+        
+    // Start the transaction
+    val |= NV_DRF_DEF(I2C, I2C_CNFG, SEND, GO);
+    I2C_REGW(c, I2C_CNFG, val);
+
+    if (!c->I2cSyncSemaphore)
+    {
+        NvRmPrivI2cOalPoll(c);
+    } else
+    {
+        NvOsSemaphoreWaitTimeout(c->I2cSyncSemaphore, c->timeout);
+    }
+
+    /* Controller should return some sort of error. If not, then there is
+     * something gross happened. */
+    if (c->I2cTransferStatus != NvError_Timeout)
+    {
+        if (c->I2cTransferStatus == NvSuccess)
+        {
+            /* Read the FIFO */
+            fifo[0] = I2C_REGR(c, I2C_CMD_DATA1);
+            fifo[1] = I2C_REGR(c, I2C_CMD_DATA2);
+
+            NvOsMemcpy(pBuffer, (NvU8* )fifo, ByteCount);
+        }
+        if (pBytesTransferred != NULL)
+        {
+            *pBytesTransferred = ByteCount;
+        }
+    }
+    else
+    {           
+        if (pBytesTransferred != NULL)
+        {
+            *pBytesTransferred = ByteCount;
+        }
+        // In case of timeout, reset  the I2C controller
+        NvRmModuleReset(c->hRmDevice, NVRM_MODULE_ID(c->ModuleId, c->Instance));
+    }
+
+    return c->I2cTransferStatus;
+}
+
+static NvError
+AP15RmI2cRepeatStartTransaction(
+    NvRmI2cController *c,
+    NvU8* pBuffer,
+    NvRmI2cTransactionInfo * Transactions,
+    NvU32 NoOfTransations)
+{
+    NvU32 val = 0;
+    NvU32 data = 0;
+    NvU8 *pBuffer1, *pBuffer2;
+
+    NV_ASSERT(pBuffer);
+    NV_ASSERT(Transactions);
+    NV_ASSERT(Transactions[0].NumBytes <= 4);
+    NV_ASSERT(Transactions[1].NumBytes <= 4);
+
+    // If requested i2c is dvc i2c, then disable dvc hardware from using the dvc i2c bus.
+    if (c->ModuleId == NvRmModuleID_Dvc)
+    {
+        val = DVC_REGR(c, CTRL_REG3);
+        val = NV_FLD_SET_DRF_DEF(DVC, CTRL_REG3, I2C_HW_SW_PROG, SW, val);
+        val = NV_FLD_SET_DRF_DEF(DVC, CTRL_REG3, I2C_DONE_INTR_EN, ENABLE, val);
+        DVC_REGW(c, CTRL_REG3, val);
+
+        val = DVC_REGR(c, CTRL_REG1);
+        val = NV_FLD_SET_DRF_DEF(DVC, CTRL_REG1, INTR_EN, ENABLE, val);
+        DVC_REGW(c, CTRL_REG1, val);
+    }
+
+    // There will be always only 2 transations  in normal mode 
+    pBuffer1 = pBuffer;
+    pBuffer2 = (NvU8 *)(( NvU32)pBuffer + Transactions[0].NumBytes);
+
+    if (c->EnableNewMaster)
+    {
+        // Enable new master if it is available
+        val = NV_DRF_DEF(I2C, I2C_CNFG, NEW_MASTER_FSM, ENABLE);
+    }
+
+
+    if (Transactions[0].Flags & NVRM_I2C_WRITE)
+    {
+        // Configure for CMD 1 as write trasaction
+        val |= NV_DRF_DEF(I2C, I2C_CNFG, CMD1, DISABLE);
+
+        // Prepare the data to be written
+        NvOsMemcpy((NvU8* )&data, (void *)pBuffer1, Transactions[0].NumBytes);
+        // Write the data to the controller data registers
+        I2C_REGW(c, I2C_CMD_DATA1, data);
+        // configure slave1 device address
+        I2C_REGW(c, I2C_CMD_ADDR0, Transactions[0].Address);
+    }
+    else
+    {
+        // Configure for CMD 1 as read trasaction
+        val |= NV_DRF_DEF(I2C, I2C_CNFG, CMD1, ENABLE);
+         // configure slave1 device address
+        I2C_REGW(c, I2C_CMD_ADDR0, (Transactions[0].Address | 1));
+    }
+
+    if (Transactions[1].Flags & NVRM_I2C_WRITE)
+    {
+         // Configure for CMD 2 as write trasaction
+         val |= NV_DRF_DEF(I2C, I2C_CNFG, CMD2, DISABLE);
+
+         //Prepare the data to be written
+        NvOsMemcpy((NvU8* )&data, (void *)pBuffer2, Transactions[1].NumBytes);
+
+         // Write the data to the controller data registers
+        I2C_REGW(c, I2C_CMD_DATA2, data);
+
+        /* write the slave 2 address */
+        I2C_REGW(c, I2C_CMD_ADDR1, Transactions[1].Address);
+    }
+    else 
+    {
+         // Configure for CMD 2 as read trasaction
+         val |= NV_DRF_DEF(I2C, I2C_CNFG, CMD2, ENABLE);
+         /* write the slave 2 address */
+        I2C_REGW(c, I2C_CMD_ADDR1, (Transactions[1].Address | 1));
+    }
+
+    /* 7 bit address */
+    if (Transactions[0].Is10BitAddress == NV_FALSE)
+    {       
+        // Configure the slave address type as 7bit address
+        val |= NV_DRF_DEF(I2C, I2C_CNFG, A_MOD,
+                        SEVEN_BIT_DEVICE_ADDRESS);
+    }
+     /* 10 bit address */
+    else
+    {
+        // Configure the slave address type as 10bit address
+        val |= NV_DRF_DEF(I2C, I2C_CNFG, A_MOD,
+                        TEN_BIT_DEVICE_ADDRESS);
+    }
+
+    if (Transactions[0].Flags & NVRM_I2C_NOACK)
+    {
+        val |= NV_DRF_DEF(I2C, I2C_CNFG, NOACK, ENABLE);
+    }
+
+
+    // Initialize the I2C param structure
+    c->TransactionType = I2C_REPEAT_START_TRANSACTION;
+    c->I2cTransferStatus = NvError_Timeout;
+        
+    // Configure the number of bytes to read/write
+    val |= NV_DRF_NUM(I2C, I2C_CNFG, LENGTH,
+                Transactions[0].NumBytes - 1);
+    // Configure the slave 2 as present
+    val |= NV_DRF_DEF(I2C, I2C_CNFG, SLV2, ENABLE);
+
+    I2C_REGW(c, I2C_CNFG, val);
+    
+    // Start the transaction
+    val |= NV_DRF_DEF(I2C, I2C_CNFG, SEND, GO);
+    I2C_REGW(c, I2C_CNFG, val);
+    
+    if (!c->I2cSyncSemaphore)
+    {
+        NvRmPrivI2cOalPoll(c);
+    } else
+    {
+        NvOsSemaphoreWaitTimeout(c->I2cSyncSemaphore, c->timeout);
+    }
+    if (c->I2cTransferStatus != NvError_Timeout)
+    {
+        if (c->I2cTransferStatus == NvSuccess)
+        {
+            if (!(Transactions[0].Flags & NVRM_I2C_WRITE))
+            {
+                // read the data for the first transaction
+                data = I2C_REGR(c, I2C_CMD_DATA1);
+
+                NvOsMemcpy(pBuffer1, (NvU8* )&data, Transactions[0].NumBytes);
+            }
+
+            if (!(Transactions[1].Flags & NVRM_I2C_WRITE))
+            {
+                 // read the data for the second transaction
+                data = I2C_REGR(c, I2C_CMD_DATA2);
+
+                NvOsMemcpy(pBuffer2, (NvU8* )&data, Transactions[1].NumBytes);
+            }
+        }
+    }
+    else
+    {        
+        // In case of timeout, reset  the I2C controller
+        NvRmModuleReset(c->hRmDevice, NVRM_MODULE_ID(c->ModuleId, c->Instance));
+    }
+    return c->I2cTransferStatus;
+}
+
+static NvError
+AP15RmI2cSend(
+    NvRmI2cController *c,
+    NvU8*  pBuffer,
+    const NvRmI2cTransactionInfo *pTransaction,
+    NvU32* pBytesTransferred)
+{
+    NvU32 val = 0;
+    NvU32 fifo[2];
+    NvU32 ByteCount;
+
+    NV_ASSERT(pBuffer);
+    NV_ASSERT(pTransaction->NumBytes > 0);
+
+
+    // If requested i2c is dvc i2c, then disable dvc hardware from using the dvc i2c bus.
+    if (c->ModuleId == NvRmModuleID_Dvc)
+    {
+        val = DVC_REGR(c, CTRL_REG3);
+        val = NV_FLD_SET_DRF_DEF(DVC, CTRL_REG3, I2C_HW_SW_PROG, SW, val);    
+        val = NV_FLD_SET_DRF_DEF(DVC, CTRL_REG3, I2C_DONE_INTR_EN, ENABLE, val);
+        DVC_REGW(c, CTRL_REG3, val);
+
+        val = DVC_REGR(c, CTRL_REG1);
+        val = NV_FLD_SET_DRF_DEF(DVC, CTRL_REG1, INTR_EN, ENABLE, val);
+        DVC_REGW(c, CTRL_REG1, val);
+    }
+
+    val = 0;
+
+    if (c->EnableNewMaster)
+    {
+        // Enable new master if it is available
+        val |= NV_DRF_DEF(I2C, I2C_CNFG, NEW_MASTER_FSM, ENABLE);
+    }
+
+    // Configure the slave address
+    if (c->Is10BitAddress == NV_FALSE)
+    {
+        /* 7 bit address */
+        /* write the slave address */
+        I2C_REGW(c, I2C_CMD_ADDR0, pTransaction->Address);
+        // Configure for write trasaction
+        val |= NV_DRF_DEF(I2C, I2C_CNFG, CMD1, DISABLE);
+        // Configure the slave address type as 7bit address
+        val |= NV_DRF_DEF(I2C, I2C_CNFG, A_MOD, SEVEN_BIT_DEVICE_ADDRESS);
+    }
+    else
+    {
+        /* 10 bit address */
+        
+        /* write the slave address */
+        I2C_REGW(c, I2C_CMD_ADDR0, pTransaction->Address);
+        // Configure for write trasaction
+            val |= NV_DRF_DEF(I2C, I2C_CNFG, CMD1, DISABLE);
+       // Configure the slave address type as 10bit address
+        val |= NV_DRF_DEF(I2C, I2C_CNFG, A_MOD,
+                        TEN_BIT_DEVICE_ADDRESS);
+    }
+
+    if (c->NoACK)
+    {
+        val |= NV_DRF_DEF(I2C, I2C_CNFG, NOACK, ENABLE);
+    }
+
+    // Calculate the number of bytes that can be written 
+    ByteCount = (pTransaction->NumBytes > I2C_PACKET_SIZE) ?
+                    I2C_PACKET_SIZE : pTransaction->NumBytes;
+
+    NvOsMemcpy((NvU8 *)fifo,(void *)pBuffer, ByteCount);
+
+    // Initialize the I2C param structure
+    c->TransactionType = I2C_WRITE;
+    c->I2cTransferStatus = NvError_Timeout;
+
+     // Write the data to the controller data registers
+    I2C_REGW(c, I2C_CMD_DATA1, fifo[0]);
+    I2C_REGW(c, I2C_CMD_DATA2, fifo[1]);
+
+    // Configure the number of bytes to be written
+    val |= NV_DRF_NUM(I2C, I2C_CNFG, LENGTH,
+                                    ByteCount - 1);
+    // disable repeated start
+    val |= NV_DRF_DEF(I2C, I2C_CNFG, SLV2, DISABLE);
+    I2C_REGW(c, I2C_CNFG, val);
+    
+     // Start the transaction
+    val |= NV_DRF_DEF(I2C, I2C_CNFG, SEND, GO);
+    I2C_REGW(c, I2C_CNFG, val);
+
+    if (!c->I2cSyncSemaphore)
+    {
+        // Wait for the transaction to be completed till there is timeout/max retries
+        NvRmPrivI2cOalPoll(c);
+    } else
+    {
+        // Wait for the transaction to be completed till there is timeout
+        NvOsSemaphoreWaitTimeout(c->I2cSyncSemaphore, c->timeout);
+    }
+
+    if (c->I2cTransferStatus == NvSuccess 
+            && pBytesTransferred != NULL)
+    {
+        *pBytesTransferred = ByteCount;
+    }
+    if (c->I2cTransferStatus == NvError_Timeout)
+    {
+         // In case of timeout, reset  the I2C controller
+        NvRmModuleReset(c->hRmDevice, NVRM_MODULE_ID(c->ModuleId, c->Instance));
+    }
+    return c->I2cTransferStatus;
+}
+
+
+NvError AP15RmI2cOpen(NvRmI2cController *c)
+{
+    NvError status = NvSuccess;
+
+    NV_ASSERT(c!= NULL);
+
+    /* Populate the structures */
+    c->receive = AP15RmI2cReceive;
+    c->send = AP15RmI2cSend;
+    c->repeatStart = AP15RmI2cRepeatStartTransaction;
+    c->close = AP15RmI2cClose;
+    c->GetGpioPins = AP15RmI2cGetGpioPins;
+
+    c->I2cRegisterOffset = I2C_I2C_CNFG_0;
+    if (c->ModuleId == NvRmModuleID_Dvc)
+    {
+        c->I2cRegisterOffset = DVC_I2C_CNFG_0;
+    }
+
+    // Create the sync semaphore
+    status = NvOsSemaphoreCreate( &c->I2cSyncSemaphore, 0);
+    
+    if (status == NvSuccess)
+    {
+        NvU32 IrqList;
+        NvOsInterruptHandler IntHandlers;
+
+        /* Install interrupt handler */
+        if (c->ModuleId == NvRmModuleID_Dvc)
+        {
+            IntHandlers = DvcIsr;
+        } else
+        {
+            IntHandlers = I2cIsr;
+        }
+        IrqList = NvRmGetIrqForLogicalInterrupt(
+                c->hRmDevice, NVRM_MODULE_ID(c->ModuleId, c->Instance), 0);
+        
+        status = NvRmInterruptRegister(c->hRmDevice, 1, &IrqList, &IntHandlers, 
+                c, &c->I2CInterruptHandle, NV_TRUE);
+        if (status != NvSuccess)
+        {
+            /* Fall back to Polling mode, but assert in debug build */
+            NV_ASSERT(!"I2C module interrupt register failed!");
+            NvOsSemaphoreDestroy(c->I2cSyncSemaphore);
+            c->I2cSyncSemaphore = 0;
+        }
+    } 
+    
+    return NvSuccess;
+}
+
diff --git a/arch/arm/mach-tegra/nvrm/io/ap15/ap15rm_pwm.c b/arch/arm/mach-tegra/nvrm/io/ap15/ap15rm_pwm.c
new file mode 100644
index 000000000000..d948fa6f2b18
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/io/ap15/ap15rm_pwm.c
@@ -0,0 +1,564 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+
+/** @file
+ * @brief <b>NVIDIA Driver Development Kit: PWM API</b>
+ *
+ * @b Description: Contains the NvRM PWM implementation.
+ */
+
+#include "ap15rm_pwm_private.h"
+#include "nvrm_drf.h"
+#include "nvos.h"
+#include "nvrm_module.h"
+#include "nvrm_hardware_access.h"
+#include "nvrm_power.h" 
+#include "nvrm_interrupt.h"
+#include "nvassert.h"
+#include "nvodm_query_pinmux.h"
+#include "nvodm_modules.h"
+#include "nvrm_pinmux.h"
+#include "nvrm_hwintf.h"
+#include "ap15/arpwfm.h"
+#include "ap15/arapbpm.h"
+
+#define PWM_REGR( VirtualAddress, offset )  \
+        NV_READ32(VirtualAddress + offset)  
+
+#define PWM_REGW( VirtualAddress, offset, value ) \
+        NV_WRITE32(VirtualAddress + offset, value)
+
+#define PMC_REGR( VirtualAddress, offset )  \
+        NV_READ32(VirtualAddress + offset)  
+
+#define PMC_REGW( VirtualAddress, offset, value ) \
+        NV_WRITE32(VirtualAddress + offset, value)
+    
+static NvU32 s_PwmPowerID = 0;
+static NvOsMutexHandle s_hPwmMutex = NULL;
+static NvRmPwmHandle s_hPwm = NULL;
+static NvBool s_IsPwmFirstConfig = NV_FALSE;
+static NvBool s_IsFreqDividerSupported = NV_FALSE;
+
+// Checks whether all the PWM channels are disabled or not.
+// Returns NV_FALSE if any of the channels are enabled
+// else returns NV_TRUE
+static NvBool IsPwmDisabled(NvRmPwmHandle hPwm);
+
+static NvBool IsPwmDisabled(NvRmPwmHandle hPwm)
+{
+    NvU32 RegValue = 0;
+    NvU32 i = 0;
+    NvBool PwmDisabled = NV_TRUE;
+
+    for (i = 0; i < NvRmPwmOutputId_Num-2; i++)
+    {
+        RegValue = PWM_REGR( hPwm->VirtualAddress[i], 0 );
+        if (PWM_GET(CSR_0, ENB, RegValue))
+        {
+            PwmDisabled = NV_FALSE;
+            break;
+        }
+    }
+    return PwmDisabled;
+}
+
+static NvError PwmPowerConfigure(NvRmPwmHandle hPwm, NvBool IsEnablePower)
+{
+    NvError status = NvSuccess;
+
+    if (IsEnablePower == NV_TRUE)
+    {
+        if (!hPwm->PowerEnabled)
+        {
+            // Enable power
+            status = NvRmPowerVoltageControl(hPwm->RmDeviceHandle,
+                        NVRM_MODULE_ID(NvRmModuleID_Pwm, 0),
+                                            s_PwmPowerID,
+                                            NvRmVoltsUnspecified,
+                                            NvRmVoltsUnspecified,
+                                            NULL,
+                                            0,
+                                            NULL);
+            if (status == NvSuccess)
+            {
+                // Enable the clock to the pwm controller
+                status = NvRmPowerModuleClockControl(hPwm->RmDeviceHandle,
+                        NVRM_MODULE_ID(NvRmModuleID_Pwm, 0),
+                        s_PwmPowerID,
+                        NV_TRUE);
+                hPwm->PowerEnabled = NV_TRUE;
+            }
+        }
+    }
+    else
+    {
+        if (hPwm->PowerEnabled)
+        {
+            // Disable the clock to the pwm controller
+            status = NvRmPowerModuleClockControl(hPwm->RmDeviceHandle,
+                        NVRM_MODULE_ID(NvRmModuleID_Pwm, 0),
+                        s_PwmPowerID,
+                        NV_FALSE);
+
+            if(status == NvSuccess)
+            {
+                // Disable power
+                status = NvRmPowerVoltageControl(hPwm->RmDeviceHandle,
+                            NVRM_MODULE_ID(NvRmModuleID_Pwm, 0),
+                            s_PwmPowerID,
+                            NvRmVoltsOff,
+                            NvRmVoltsOff,
+                            NULL,
+                            0,
+                            NULL);
+                hPwm->PowerEnabled = NV_FALSE;
+            }
+        }
+    }
+
+    return status;
+}
+
+
+static NvError PwmCheckValidConfig(NvRmPwmHandle hPwm, 
+        NvRmPwmOutputId OutputId,
+        NvRmPwmMode Mode)
+{
+    NvError status = NvSuccess;
+    NvRmModulePwmInterfaceCaps PwmCaps;
+
+    if ((Mode != NvRmPwmMode_Disable) &&
+        (Mode != NvRmPwmMode_Enable))
+    return NvError_NotSupported;
+
+    status = NvRmGetModuleInterfaceCapabilities(hPwm->RmDeviceHandle,
+                                                 NVRM_MODULE_ID(NvRmModuleID_Pwm, 0),
+                                                 sizeof(NvRmModulePwmInterfaceCaps),
+                                                 &PwmCaps);
+    if (status != NvSuccess)
+        return status;
+    
+    if (PwmCaps.PwmOutputIdSupported & (1 << (OutputId-1)))
+        return status;
+    else
+        return NvError_NotSupported; 
+}
+
+NvError NvRmPrivPwmInit(NvRmDeviceHandle hRm);
+NvError NvRmPrivPwmInit(NvRmDeviceHandle hRm)
+{
+    NvError status = NvSuccess;
+
+    // Creating the Mutex
+    status = NvOsMutexCreate(&s_hPwmMutex);
+    return status;
+}
+
+void NvRmPrivPwmDeInit(NvRmDeviceHandle hRm);
+void NvRmPrivPwmDeInit(NvRmDeviceHandle hRm)
+{
+    NvOsMutexDestroy(s_hPwmMutex);
+}
+
+NvError 
+NvRmPwmOpen(
+    NvRmDeviceHandle hDevice,
+    NvRmPwmHandle *phPwm)
+{
+    NvError status = NvSuccess;
+    NvU32 PwmPhysAddr = 0, i = 0, PmcPhysAddr = 0;
+    NvRmModuleCapability caps[4];  
+    NvRmModuleCapability *pCap = NULL;
+
+    NV_ASSERT(hDevice);
+    NV_ASSERT(phPwm);
+    
+    NvOsMutexLock(s_hPwmMutex);
+    
+    if (s_hPwm)
+    {
+        s_hPwm->RefCount++;
+        goto exit;
+    }
+
+    // Allcoate the memory for the pwm handle
+    s_hPwm = NvOsAlloc(sizeof(NvRmPwm));
+    if (!s_hPwm)
+    {
+        status = NvError_InsufficientMemory;
+        goto fail;
+    }
+    NvOsMemset(s_hPwm, 0, sizeof(NvRmPwm));
+
+    // Set the pwm handle parameters
+    s_hPwm->RmDeviceHandle = hDevice;
+    
+    // Get the pwm physical and virtual base address
+    NvRmModuleGetBaseAddress(hDevice,
+            NVRM_MODULE_ID(NvRmModuleID_Pwm, 0),
+            &PwmPhysAddr, &(s_hPwm->PwmBankSize));
+    s_hPwm->PwmBankSize = PWM_BANK_SIZE;
+    for (i = 0; i < NvRmPwmOutputId_Num-2; i++)
+    {
+        status = NvRmPhysicalMemMap(
+            PwmPhysAddr + i*s_hPwm->PwmBankSize,
+            s_hPwm->PwmBankSize, 
+            NVOS_MEM_READ_WRITE,
+            NvOsMemAttribute_Uncached,
+            (void**)&s_hPwm->VirtualAddress[i]);
+        if (status != NvSuccess)
+        {
+            NvOsFree(s_hPwm);
+            goto fail;
+        }
+    }
+
+    // Get the pmc physical and virtual base address
+    NvRmModuleGetBaseAddress(hDevice,
+            NVRM_MODULE_ID(NvRmModuleID_Pmif, 0),
+            &PmcPhysAddr, &(s_hPwm->PmcBankSize));
+    s_hPwm->PmcBankSize = PMC_BANK_SIZE;
+
+    status = NvRmPhysicalMemMap(
+            PmcPhysAddr,
+            s_hPwm->PmcBankSize, 
+            NVOS_MEM_READ_WRITE,
+            NvOsMemAttribute_Uncached,
+            (void**)&s_hPwm->VirtualAddress[NvRmPwmOutputId_Num-2]);
+    if (status != NvSuccess)
+    {
+        NvOsFree(s_hPwm);
+        goto fail;
+    }
+
+    caps[0].MajorVersion = 1;
+    caps[0].MinorVersion = 0;
+    caps[0].EcoLevel = 0;
+    caps[0].Capability = &caps[0];
+
+    caps[1].MajorVersion = 1;
+    caps[1].MinorVersion = 1;
+    caps[1].EcoLevel = 0;
+    caps[1].Capability = &caps[1];
+
+    caps[2].MajorVersion = 1;
+    caps[2].MinorVersion = 2;
+    caps[2].EcoLevel = 0;
+    caps[2].Capability = &caps[2];
+
+    caps[3].MajorVersion = 2;
+    caps[3].MinorVersion = 0;
+    caps[3].EcoLevel = 0;
+    caps[3].Capability = &caps[3];
+
+    NV_ASSERT_SUCCESS(NvRmModuleGetCapabilities(
+        hDevice,
+        NvRmModuleID_Pwm,
+        caps,
+        sizeof(caps)/sizeof(caps[0]),
+        (void**)&pCap));
+
+    if ((pCap->MajorVersion > 1) ||
+        ((pCap->MajorVersion == 1) && (pCap->MinorVersion > 0)))
+            s_IsFreqDividerSupported = NV_TRUE;
+
+    s_hPwm->RefCount++;
+exit:
+    *phPwm = s_hPwm;
+    NvOsMutexUnlock(s_hPwmMutex);
+    return NvSuccess;
+
+fail:
+    NvOsMutexUnlock(s_hPwmMutex);
+    return status;
+}
+
+void NvRmPwmClose(NvRmPwmHandle hPwm)
+{ 
+    NvU32 i;
+    if (!hPwm)
+        return;
+
+    NV_ASSERT(hPwm->RefCount);    
+
+    NvOsMutexLock(s_hPwmMutex);
+    hPwm->RefCount--;
+    if (hPwm->RefCount == 0)
+    {
+        // Unmap the pwm register virtual address space
+        for (i = 0; i < NvRmPwmOutputId_Num-2; i++)
+        {
+            NvRmPhysicalMemUnmap((void*)s_hPwm->VirtualAddress[i],
+                             s_hPwm->PwmBankSize);
+        }
+        
+        // Unmap the pmc register virtual address space
+        NvRmPhysicalMemUnmap(
+                (void*)s_hPwm->VirtualAddress[NvRmPwmOutputId_Num-2],
+                s_hPwm->PmcBankSize);
+
+        if (s_IsPwmFirstConfig)
+        {
+            // Disable power
+            PwmPowerConfigure(hPwm, NV_FALSE);
+
+            // Unregister with RM power
+            NvRmPowerUnRegister(hPwm->RmDeviceHandle, s_PwmPowerID);
+
+            // Tri-state the pin-mux pins
+            NV_ASSERT_SUCCESS(NvRmSetModuleTristate(hPwm->RmDeviceHandle,
+                NVRM_MODULE_ID(NvRmModuleID_Pwm, 0), NV_TRUE));
+            s_IsPwmFirstConfig = NV_FALSE;
+        }
+        NvOsFree(s_hPwm);
+        s_hPwm = NULL;
+    }
+    NvOsMutexUnlock(s_hPwmMutex);
+}
+
+#define MAX_DUTY_CYCLE 255
+#define PWM_FREQ_FACTOR 256
+
+NvError NvRmPwmConfig(
+    NvRmPwmHandle hPwm,
+    NvRmPwmOutputId OutputId,  
+    NvRmPwmMode Mode, 
+    NvU32 DutyCycle,
+    NvU32 RequestedFreqHzOrPeriod,
+    NvU32 *pCurrentFreqHzOrPeriod)
+{
+    NvError status = NvSuccess;
+    NvU32 RegValue = 0, ResultFreqKHz = 0;
+    NvU8 PwmMode = 0;
+    NvU32 ClockFreqKHz = 0, DCycle = 0, DataOn = 0, DataOff = 0;
+    NvU32 PmcCtrlReg = 0, PmcDpdPadsReg = 0, PmcBlinkTimerReg = 0;
+    NvU32 RequestPeriod = 0, ResultPeriod = 0;
+    NvU32 DataOnRegVal = 0, DataOffRegVal = 0;
+    NvU32 *pPinMuxConfigTable = NULL;
+    NvU32 Count = 0, divider = 1;
+    
+    NvOsMutexLock(s_hPwmMutex);
+    
+    if (OutputId != NvRmPwmOutputId_Blink)
+    {
+        if (!s_IsPwmFirstConfig)
+        {
+            hPwm->PowerEnabled = NV_FALSE;
+            // Register with RM power
+            s_PwmPowerID = NVRM_POWER_CLIENT_TAG('P','W','M',' ');
+            status = NvRmPowerRegister(hPwm->RmDeviceHandle, NULL, &s_PwmPowerID);
+            if (status != NvSuccess)
+                goto fail;
+
+            // Enable power
+            status = PwmPowerConfigure(hPwm, NV_TRUE);
+            if (status != NvSuccess)
+            {
+                NvRmPowerUnRegister(hPwm->RmDeviceHandle, s_PwmPowerID);
+                goto fail;
+            }
+
+            // Reset pwm module
+            NvRmModuleReset(hPwm->RmDeviceHandle, NVRM_MODULE_ID(NvRmModuleID_Pwm, 0));
+
+            // Config pwm pinmux
+            NvOdmQueryPinMux(NvOdmIoModule_Pwm, (const NvU32 **)&pPinMuxConfigTable,
+                        &Count);
+            if (Count != 1)
+            {
+                status = NvError_NotSupported;
+                PwmPowerConfigure(hPwm, NV_FALSE);
+                NvRmPowerUnRegister(hPwm->RmDeviceHandle, s_PwmPowerID);
+                goto fail;
+            }
+            hPwm->PinMap = pPinMuxConfigTable[0];
+            status = NvRmSetModuleTristate(hPwm->RmDeviceHandle,
+                NVRM_MODULE_ID(NvRmModuleID_Pwm, 0), NV_FALSE);
+
+            if (status != NvSuccess)
+            {
+                PwmPowerConfigure(hPwm, NV_FALSE);
+                NvRmPowerUnRegister(hPwm->RmDeviceHandle, s_PwmPowerID);
+                goto fail;
+            }
+            s_IsPwmFirstConfig = NV_TRUE;
+        }
+
+        // Enable power
+        status = PwmPowerConfigure(hPwm, NV_TRUE);
+        if (status != NvSuccess)
+        {
+            NvRmPowerUnRegister(hPwm->RmDeviceHandle, s_PwmPowerID);
+            goto fail;
+        }
+
+
+        // Validate PWM output and pin map config
+        status = PwmCheckValidConfig(hPwm, OutputId, Mode);
+        if (status != NvSuccess)
+            goto fail;
+
+        ClockFreqKHz = (RequestedFreqHzOrPeriod * PWM_FREQ_FACTOR) / 1000;
+        if (ClockFreqKHz == 0)
+            ClockFreqKHz = 1;
+
+        if (RequestedFreqHzOrPeriod == NvRmFreqMaximum)
+            ClockFreqKHz = NvRmFreqMaximum;
+
+        status = NvRmPowerModuleClockConfig(hPwm->RmDeviceHandle, 
+                NVRM_MODULE_ID(NvRmModuleID_Pwm, 0),
+                s_PwmPowerID,
+                NvRmFreqUnspecified,
+                NvRmFreqUnspecified,
+                &ClockFreqKHz,
+                1,
+                &ResultFreqKHz,
+                0);
+        if (status != NvSuccess)
+            goto fail;
+
+        *pCurrentFreqHzOrPeriod = (ResultFreqKHz * 1000) / PWM_FREQ_FACTOR;
+
+        if (Mode == NvRmPwmMode_Disable)
+            PwmMode = 0;
+        else
+            PwmMode = 1;
+
+        /*
+         * Convert from percentage unsigned 15.16 fixed point
+         * format to actual register value
+         */
+        DCycle = (DutyCycle * MAX_DUTY_CYCLE/100)>>16;
+        if (DCycle > MAX_DUTY_CYCLE)
+            DCycle = MAX_DUTY_CYCLE;
+
+        RegValue = PWM_SETNUM(CSR_0, ENB, PwmMode) |
+           PWM_SETNUM(CSR_0, PWM_0, DCycle);
+
+        if (s_IsFreqDividerSupported)
+        {
+            if ((*pCurrentFreqHzOrPeriod > RequestedFreqHzOrPeriod) &&
+                (RequestedFreqHzOrPeriod != 0))
+            {
+                divider = *pCurrentFreqHzOrPeriod/RequestedFreqHzOrPeriod;
+                if ((*pCurrentFreqHzOrPeriod%RequestedFreqHzOrPeriod)*2>RequestedFreqHzOrPeriod)
+                    divider +=1;
+                *pCurrentFreqHzOrPeriod = *pCurrentFreqHzOrPeriod / divider;
+                RegValue |= PWM_SETNUM(CSR_0, PFM_0, divider);
+            }
+        }
+
+        PWM_REGW(hPwm->VirtualAddress[OutputId-1], 0, RegValue);
+
+        // If PWM mode is disabled and all pwd channels are disabled then
+        // disable power to PWM
+        if (!PwmMode)
+        {
+            if (IsPwmDisabled(hPwm))
+            {
+                // Disable power
+                status = PwmPowerConfigure(hPwm, NV_FALSE);
+                if (status != NvSuccess)
+                {
+                    NvRmPowerUnRegister(hPwm->RmDeviceHandle, s_PwmPowerID);
+                    goto fail;
+                }
+            }
+        }
+
+    }
+    else
+    {
+        RequestPeriod = RequestedFreqHzOrPeriod;
+        DCycle = DutyCycle>>16;
+        DataOn = (RequestPeriod * DCycle)/100;
+        if (DataOn > MAX_SUPPORTED_PERIOD)
+        {
+            ResultPeriod = (MAX_SUPPORTED_PERIOD * 100)/DCycle;
+            DataOn = MAX_SUPPORTED_PERIOD;
+        }
+        else
+        {
+            ResultPeriod = RequestPeriod;
+        }
+        DataOff = ResultPeriod - DataOn;
+        DataOnRegVal = DataOn * DATA_ON_FACTOR;
+        if (DataOnRegVal >= MAX_DATA_ON)
+            DataOnRegVal = MAX_DATA_ON;
+        DataOffRegVal = DataOff * DATA_ON_FACTOR;
+        if (DataOffRegVal >= MAX_DATA_ON)
+            DataOffRegVal = MAX_DATA_ON;
+
+        PmcCtrlReg = PMC_REGR(hPwm->VirtualAddress[OutputId-1],
+                                APBDEV_PMC_CNTRL_0);
+        PmcDpdPadsReg = PMC_REGR(hPwm->VirtualAddress[OutputId-1],
+                                APBDEV_PMC_DPD_PADS_ORIDE_0);
+        PmcBlinkTimerReg = PMC_REGR(hPwm->VirtualAddress[OutputId-1],
+                                APBDEV_PMC_BLINK_TIMER_0);
+        PmcBlinkTimerReg &=~PMC_SETNUM(BLINK_TIMER, DATA_OFF, 0xFFFF);
+        PmcBlinkTimerReg &=~PMC_SETNUM(BLINK_TIMER, DATA_ON, 0xFFFF);
+        PmcBlinkTimerReg |=PMC_SETNUM(BLINK_TIMER, DATA_OFF, DataOffRegVal);
+        PmcBlinkTimerReg |=PMC_SETNUM(BLINK_TIMER, DATA_ON, DataOnRegVal);
+        PmcCtrlReg |= PMC_SETDEF(CNTRL, BLINK_EN, ENABLE);
+        PmcDpdPadsReg |= PMC_SETDEF(DPD_PADS_ORIDE, BLINK, ENABLE);
+        if (Mode == NvRmPwmMode_Blink_LED) 
+        {
+            PmcBlinkTimerReg |= (1 << 15);
+        }
+        
+        if (Mode == NvRmPwmMode_Blink_32KHzClockOutput)
+        {
+            PmcBlinkTimerReg &= ~(1 << 15);
+        }
+
+        if (Mode == NvRmPwmMode_Blink_Disable)
+        {
+            PmcCtrlReg &= ~PMC_SETDEF(CNTRL, BLINK_EN, ENABLE);
+            PmcDpdPadsReg &= ~PMC_SETDEF(DPD_PADS_ORIDE, BLINK, ENABLE);
+        }
+        PmcBlinkTimerReg |=PMC_SETNUM(BLINK_TIMER, DATA_OFF, DataOffRegVal)
+                         | PMC_SETNUM(BLINK_TIMER, DATA_ON, DataOnRegVal);
+        PMC_REGW(hPwm->VirtualAddress[OutputId-1], 
+            APBDEV_PMC_CNTRL_0, PmcCtrlReg); 
+        PMC_REGW(hPwm->VirtualAddress[OutputId-1], 
+            APBDEV_PMC_DPD_PADS_ORIDE_0, PmcDpdPadsReg); 
+        PMC_REGW(hPwm->VirtualAddress[OutputId-1], 
+            APBDEV_PMC_BLINK_TIMER_0, PmcBlinkTimerReg);     
+        *pCurrentFreqHzOrPeriod = ResultPeriod;
+    }
+fail:
+    NvOsMutexUnlock(s_hPwmMutex);
+    return status;
+}
+
diff --git a/arch/arm/mach-tegra/nvrm/io/ap15/ap15rm_pwm_private.h b/arch/arm/mach-tegra/nvrm/io/ap15/ap15rm_pwm_private.h
new file mode 100644
index 000000000000..46ce0f3a2c3d
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/io/ap15/ap15rm_pwm_private.h
@@ -0,0 +1,93 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/** @file
+ * @brief <b>NVIDIA Driver Development Kit: Timer API</b>
+ *
+ * @b Description: Contains the pwm declarations.
+ */
+
+#ifndef INCLUDED_PWM_PRIVATE_H
+#define INCLUDED_PWM_PRIVATE_H
+
+#include "nvrm_module.h"
+#include "nvodm_query_pinmux.h"
+#include "nvrm_pwm.h"
+
+#define PWM_BANK_SIZE           16
+#define PMC_BANK_SIZE           192
+#define MAX_SUPPORTED_PERIOD    16
+#define MAX_DATA_ON             0xFFFF
+#define DATA_ON_FACTOR          8194 // 8194 = 1/(4 * 30.51us)
+
+typedef struct NvRmPwmRec
+{
+    // RM device handle
+    NvRmDeviceHandle RmDeviceHandle;
+
+    // Pwm configuration pin-map.
+    NvOdmPwmPinMap PinMap;
+
+    // Pwm open reference count
+    NvU32 RefCount;
+
+    // Pwm virtual base address
+    NvU32   VirtualAddress[NvRmPwmOutputId_Num-1];
+
+    // Pwm bank size
+    NvU32 PwmBankSize;
+
+    // Pmc bank size
+    NvU32 PmcBankSize;
+
+    // pmu powerEnabled flag
+    NvBool PowerEnabled;
+} NvRmPwm;
+
+#define PWM_RESET(r)            NV_RESETVAL(PWM_CONTROLLER_PWM,r)
+#define PWM_SETDEF(r,f,c)       NV_DRF_DEF(PWM_CONTROLLER_PWM,r,f,c)
+#define PWM_SETNUM(r,f,n)       NV_DRF_NUM(PWM_CONTROLLER_PWM,r,f,n)
+#define PWM_GET(r,f,v)          NV_DRF_VAL(PWM_CONTROLLER_PWM,r,f,v)
+#define PWM_CLRSETDEF(v,r,f,c)  NV_FLD_SET_DRF_DEF(PWM_CONTROLLER,r,f,c,v)
+#define PWM_CLRSETNUM(v,r,f,n)  NV_FLD_SET_DRF_NUM(PWM_CONTROLLER,r,f,n,v)
+#define PWM_MASK(x,y)           (1 << (PWM_CONTROLLER_##x##_0 - PWMCONTROLLER_##y##_0))
+
+#define PMC_RESET(r)            NV_RESETVAL(APBDEV_PMC,r)
+#define PMC_SETDEF(r,f,c)       NV_DRF_DEF(APBDEV_PMC,r,f,c)
+#define PMC_SETNUM(r,f,n)       NV_DRF_NUM(APBDEV_PMC,r,f,n)
+#define PMC_GET(r,f,v)          NV_DRF_VAL(APBDEV_PMC,r,f,v)
+#define PMC_CLRSETDEF(v,r,f,c)  NV_FLD_SET_DRF_DEF(APBDEV_PMC,r,f,c,v)
+#define PMC_CLRSETNUM(v,r,f,n)  NV_FLD_SET_DRF_NUM(APBDEV_PMC,r,f,n,v)
+
+#endif  // INCLUDED_PWM_PRIVATE_H
+
+
diff --git a/arch/arm/mach-tegra/nvrm/io/ap15/ap15rm_slink_hw_private.c b/arch/arm/mach-tegra/nvrm/io/ap15/ap15rm_slink_hw_private.c
new file mode 100644
index 000000000000..41c17684a6bc
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/io/ap15/ap15rm_slink_hw_private.c
@@ -0,0 +1,313 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/**
+ * @file
+ * @brief <b>nVIDIA driver Development Kit:
+ *           Private functions implementation for the slink Rm driver</b>
+ *
+ * @b Description:  Implements the private functions for the slink hw interface.
+ *
+ */
+
+// hardware includes
+#include "ap15/arslink.h"
+#include "rm_spi_slink_hw_private.h"
+#include "nvrm_drf.h"
+#include "nvrm_hardware_access.h"
+#include "nvassert.h"
+#include "nvos.h"
+
+#define SLINK_REG_READ32(pSlinkHwRegsVirtBaseAdd, reg) \
+        NV_READ32((pSlinkHwRegsVirtBaseAdd) + ((SLINK_##reg##_0)/4))
+#define SLINK_REG_WRITE32(pSlinkHwRegsVirtBaseAdd, reg, val) \
+    do { \
+        NV_WRITE32((((pSlinkHwRegsVirtBaseAdd) + ((SLINK_##reg##_0)/4))), (val)); \
+    } while(0)
+
+
+#define MAX_SLINK_FIFO_DEPTH 32
+
+#define ALL_SLINK_STATUS_CLEAR \
+        (NV_DRF_NUM(SLINK, STATUS,  RDY, 1) | \
+        NV_DRF_NUM(SLINK, STATUS,  RX_UNF, 1) | \
+        NV_DRF_NUM(SLINK, STATUS,  TX_UNF, 1) | \
+        NV_DRF_NUM(SLINK, STATUS,  TX_OVF, 1) | \
+        NV_DRF_NUM(SLINK, STATUS,  RX_OVF, 1))
+
+static void
+SlinkHwSetSignalMode(
+    SerialHwRegisters *pSlinkHwRegs, 
+    NvOdmQuerySpiSignalMode SignalMode);
+
+/**
+ * Initialize the slink register.
+ */
+static void
+SlinkHwRegisterInitialize(
+    NvU32 SlinkInstanceId, 
+    SerialHwRegisters *pSlinkHwRegs)
+{
+    NvU32 CommandReg1;
+    pSlinkHwRegs->InstanceId = SlinkInstanceId;
+    pSlinkHwRegs->pRegsBaseAdd = NULL;
+    pSlinkHwRegs->RegBankSize = 0;
+    pSlinkHwRegs->HwTxFifoAdd = SLINK_TX_FIFO_0;
+    pSlinkHwRegs->HwRxFifoAdd = SLINK_RX_FIFO_0;
+    pSlinkHwRegs->IsPackedMode = NV_FALSE;
+    pSlinkHwRegs->PacketLength = 1;
+    pSlinkHwRegs->CurrSignalMode = NvOdmQuerySpiSignalMode_Invalid;
+    pSlinkHwRegs->MaxWordTransfer = MAX_SLINK_FIFO_DEPTH;
+    pSlinkHwRegs->IsLsbFirst = NV_FALSE;
+    pSlinkHwRegs->IsMasterMode = NV_TRUE;
+    pSlinkHwRegs->IsNonWordAlignedPackModeSupported = NV_FALSE;
+    pSlinkHwRegs->IsHwChipSelectSupported = NV_FALSE;
+
+    CommandReg1 = NV_RESETVAL(SLINK, COMMAND);
+    
+    // Initialize the chip select bits to select the s/w only
+    CommandReg1 = NV_FLD_SET_DRF_DEF(SLINK, COMMAND, CS_SW, SOFT, CommandReg1);
+
+    // Set chip select to normal high level. (inverted polarity).
+    CommandReg1 = NV_FLD_SET_DRF_DEF(SLINK, COMMAND,  CS_VALUE, HIGH, CommandReg1);
+
+    CommandReg1 = NV_FLD_SET_DRF_DEF(SLINK, COMMAND, M_S, MASTER, CommandReg1);
+
+    if (pSlinkHwRegs->IsIdleDataOutHigh)
+    {
+        CommandReg1 = NV_FLD_SET_DRF_DEF(SLINK, COMMAND, ACTIVE_SDA, DRIVE_HIGH, CommandReg1);
+        CommandReg1 = NV_FLD_SET_DRF_DEF(SLINK, COMMAND, IDLE_SDA, DRIVE_HIGH, CommandReg1);
+    }
+    else
+    {
+        CommandReg1 = NV_FLD_SET_DRF_DEF(SLINK, COMMAND, ACTIVE_SDA, DRIVE_LOW, CommandReg1);
+        CommandReg1 = NV_FLD_SET_DRF_DEF(SLINK, COMMAND, IDLE_SDA, DRIVE_LOW, CommandReg1);
+    }
+    pSlinkHwRegs->HwRegs.SlinkRegs.Command1 = CommandReg1;
+    pSlinkHwRegs->HwRegs.SlinkRegs.Command2 = NV_RESETVAL(SLINK, COMMAND2);
+    pSlinkHwRegs->HwRegs.SlinkRegs.Status = NV_RESETVAL(SLINK, STATUS);
+    pSlinkHwRegs->HwRegs.SlinkRegs.DmaControl = NV_RESETVAL(SLINK, DMA_CTL);
+}
+
+/**
+ * Set the signal mode of communication whether this is the mode  0, 1, 2 or 3.
+ */
+static void
+SlinkHwSetSignalMode(
+    SerialHwRegisters *pSlinkHwRegs, 
+    NvOdmQuerySpiSignalMode SignalMode)
+{
+    NvU32 CommandReg = pSlinkHwRegs->HwRegs.SlinkRegs.Command1;
+    switch (SignalMode)
+    {
+        case NvOdmQuerySpiSignalMode_0:
+            CommandReg = NV_FLD_SET_DRF_DEF(SLINK, COMMAND, ACTIVE_SCLK,
+                DRIVE_LOW, CommandReg);
+            CommandReg = NV_FLD_SET_DRF_DEF(SLINK, COMMAND, IDLE_SCLK,
+                DRIVE_LOW, CommandReg);
+            CommandReg = NV_FLD_SET_DRF_DEF(SLINK, COMMAND, CK_SDA, FIRST_CLK_EDGE,
+                CommandReg);
+            break;
+
+        case NvOdmQuerySpiSignalMode_1:
+            CommandReg = NV_FLD_SET_DRF_DEF(SLINK, COMMAND, ACTIVE_SCLK,
+                DRIVE_LOW, CommandReg);
+            CommandReg = NV_FLD_SET_DRF_DEF(SLINK, COMMAND, IDLE_SCLK,
+                DRIVE_LOW, CommandReg);
+            CommandReg = NV_FLD_SET_DRF_DEF(SLINK, COMMAND, CK_SDA, SECOND_CLK_EDGE,
+                CommandReg);
+            break;
+
+        case NvOdmQuerySpiSignalMode_2:
+            CommandReg = NV_FLD_SET_DRF_DEF(SLINK, COMMAND, ACTIVE_SCLK,
+                DRIVE_HIGH, CommandReg);
+            CommandReg = NV_FLD_SET_DRF_DEF(SLINK, COMMAND, IDLE_SCLK,
+                DRIVE_HIGH, CommandReg);
+            CommandReg = NV_FLD_SET_DRF_DEF(SLINK, COMMAND, CK_SDA, FIRST_CLK_EDGE,
+                CommandReg);
+            break;
+        case NvOdmQuerySpiSignalMode_3:
+            CommandReg = NV_FLD_SET_DRF_DEF(SLINK, COMMAND, ACTIVE_SCLK,
+                DRIVE_HIGH, CommandReg);
+            CommandReg = NV_FLD_SET_DRF_DEF(SLINK, COMMAND, IDLE_SCLK,
+                DRIVE_HIGH, CommandReg);
+            CommandReg = NV_FLD_SET_DRF_DEF(SLINK, COMMAND, CK_SDA, SECOND_CLK_EDGE,
+                CommandReg);
+            break;
+        default:
+            NV_ASSERT(!"Invalid SignalMode");
+
+    }
+    pSlinkHwRegs->HwRegs.SlinkRegs.Command1 = CommandReg;
+    SLINK_REG_WRITE32(pSlinkHwRegs->pRegsBaseAdd, COMMAND, CommandReg);
+    pSlinkHwRegs->CurrSignalMode = SignalMode;
+}
+
+/**
+ * Set the chip select signal level to be default based on device during the
+ * initialization.
+ */
+static void
+SlinkHwSetChipSelectDefaultLevelFxn(
+    SerialHwRegisters *pHwRegs, 
+    NvU32 ChipSelectId,
+    NvBool IsHigh)
+{
+    // No control over the individual cs lines.
+}
+
+/**
+ * Set the chip select signal level.
+ */
+static void
+SlinkHwSetChipSelectLevel(
+    SerialHwRegisters *pSlinkHwRegs, 
+    NvU32 ChipSelectId,
+    NvBool IsHigh)
+{
+    NvU32 CommandReg1 = pSlinkHwRegs->HwRegs.SlinkRegs.Command1;
+    NvU32 CommandReg2 = pSlinkHwRegs->HwRegs.SlinkRegs.Command2;
+
+    // Set the chip select level.
+    if (IsHigh)
+        CommandReg1 = NV_FLD_SET_DRF_DEF(SLINK, COMMAND,  CS_VALUE, LOW, CommandReg1);
+    else
+        CommandReg1 = NV_FLD_SET_DRF_DEF(SLINK, COMMAND,  CS_VALUE, HIGH, CommandReg1);
+
+    switch (ChipSelectId)
+    {
+        case 0:
+            CommandReg2 = NV_FLD_SET_DRF_DEF(SLINK, COMMAND2, SS_EN, CS0, CommandReg2);
+            break;
+        
+        case 1:
+            CommandReg2 = NV_FLD_SET_DRF_DEF(SLINK, COMMAND2, SS_EN, CS1, CommandReg2);
+            break;
+        
+        case 2:
+            CommandReg2 = NV_FLD_SET_DRF_DEF(SLINK, COMMAND2, SS_EN, CS2, CommandReg2);
+            break;
+        
+        case 3:
+            CommandReg2 = NV_FLD_SET_DRF_DEF(SLINK, COMMAND2, SS_EN, CS3, CommandReg2);
+            break;
+        
+        default:
+            NV_ASSERT(!"Invalid ChipSelectId");
+    }     
+    pSlinkHwRegs->HwRegs.SlinkRegs.Command1 = CommandReg1;
+    pSlinkHwRegs->HwRegs.SlinkRegs.Command2 = CommandReg2;
+
+    SLINK_REG_WRITE32(pSlinkHwRegs->pRegsBaseAdd, COMMAND2, 
+                            pSlinkHwRegs->HwRegs.SlinkRegs.Command2);
+    SLINK_REG_WRITE32(pSlinkHwRegs->pRegsBaseAdd, COMMAND, 
+                            pSlinkHwRegs->HwRegs.SlinkRegs.Command1);
+}
+
+/**
+ * Set the chip select signal level based on the transfer size.
+ * it can use the hw based CS or SW based CS based on transfer size and
+ * cpu/apb dma based transfer.
+ * Return NV_TRUE if the SW based chipselection is used otherwise return
+ * NV_FALSE;
+ */
+static NvBool
+SlinkHwSetChipSelectLevelBasedOnPacket(
+    SerialHwRegisters *pSlinkHwRegs, 
+    NvU32 ChipSelectId,
+    NvBool IsHigh,
+    NvU32 PacketRequested,
+    NvU32 PacketPerWord,
+    NvBool IsApbDmaBasedTransfer,
+    NvBool IsOnlyUseSWCS)
+{
+    SlinkHwSetChipSelectLevel(pSlinkHwRegs, ChipSelectId, IsHigh);
+    return NV_TRUE;
+}
+
+/**
+ * Write into the transmit fifo register.
+ * returns the number of words written.
+ */
+static NvU32
+SlinkHwWriteInTransmitFifo(
+    SerialHwRegisters *pSlinkHwRegs, 
+    NvU32 *pTxBuff,  
+    NvU32 WordRequested)
+{
+    NvU32 WordWritten = 0;
+    NvU32 WordsRemaining = NV_MIN(WordRequested, MAX_SLINK_FIFO_DEPTH);
+
+    while (WordsRemaining)
+    {
+        SLINK_REG_WRITE32(pSlinkHwRegs->pRegsBaseAdd, TX_FIFO, *pTxBuff);
+        pTxBuff++;
+        WordsRemaining--;
+        WordWritten++;
+    }
+    return WordWritten;
+}
+
+/**
+ * Read the data from the receive fifo.
+ * Returns the number of words it read.   
+ */
+static NvU32
+SlinkHwReadFromReceiveFifo(
+    SerialHwRegisters *pSlinkHwRegs, 
+    NvU32 *pRxBuff,  
+    NvU32 WordRequested)
+{
+    NvU32 WordsRemaining = WordRequested;
+    while (WordsRemaining)
+    {
+        *pRxBuff = SLINK_REG_READ32(pSlinkHwRegs->pRegsBaseAdd, RX_FIFO);
+        pRxBuff++;
+        WordsRemaining--;
+    }
+    return WordRequested;
+}
+
+/**
+ * Initialize the slink intterface for the hw access.
+ */
+void NvRmPrivSpiSlinkInitSlinkInterface_v1_0(HwInterface *pSlinkInterface)
+{
+    pSlinkInterface->HwRegisterInitializeFxn = SlinkHwRegisterInitialize;
+    pSlinkInterface->HwSetSignalModeFxn = SlinkHwSetSignalMode;
+    pSlinkInterface->HwSetChipSelectDefaultLevelFxn = SlinkHwSetChipSelectDefaultLevelFxn;
+    pSlinkInterface->HwSetChipSelectLevelFxn = SlinkHwSetChipSelectLevel;
+    pSlinkInterface->HwSetChipSelectLevelBasedOnPacketFxn = SlinkHwSetChipSelectLevelBasedOnPacket;
+    pSlinkInterface->HwWriteInTransmitFifoFxn = SlinkHwWriteInTransmitFifo;
+    pSlinkInterface->HwReadFromReceiveFifoFxn =  SlinkHwReadFromReceiveFifo;
+}
+
diff --git a/arch/arm/mach-tegra/nvrm/io/ap15/nvrm_dma.c b/arch/arm/mach-tegra/nvrm/io/ap15/nvrm_dma.c
new file mode 100644
index 000000000000..a08f1d47a98b
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/io/ap15/nvrm_dma.c
@@ -0,0 +1,1936 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/**
+ * @file
+ * @brief <b>nVIDIA Driver Development Kit:
+ *           DMA Resource manager </b>
+ *
+ * @b Description: Implements the interface of the NvRM DMA. This files
+ *  implements the API for the dma for the AP15 Dma controller.
+ *
+ * This file contains the common code for ap15 dma controller to manage
+ * the different operation of the dma.
+ */
+
+/**
+ *                Dma Design details
+ *                ------------------
+ * 1. There is two type of dma allocation i.e low priority and high priority
+ * dma. The low prioirty allocation shares the same dma channel between different
+ * client. The high prioirty allocation does not share the dma channel and the
+ * dma channel is used by the requestd clients only. Hence, the high priority
+ * dma allocation may fail if there is no channel for the allocation but the low
+ * priority channel allocation will not fail till we have the sufficient memory
+ * for the dma handle creation.
+ *
+ * 2. The dma allocation is done based on the requestor module Id. It only
+ * support the dma transfer from teh memory to the apb peripheral or vice versa.
+ *
+ * 3. The DmaTransfer transfers the data from source to dest and dest to source
+ * based on the direction passed. It may be possible to do the dma transfer
+ * from destination to source address by passing the dma direction as reverse.
+ *
+ * 4. The destination and source address may be any type like peripheral or
+ * memory or xmb memory. There is no restriction on passing the source/destn
+ * address by the client. The implementation will take care of proper
+ * configuration of the dma register address.
+ *
+ * 5. It may be possible to free the dma when transfer is going on.
+ * In this case, the dma will be free for the another allocation once the
+ * transfer completes. The dma handle will be destroyed immediately for the
+ * client.
+ *
+ * 6. It is possible to abort the dma transfer for both type of dma, high
+ * priority and low priority. In this case, the dma transfer will be immediatly
+ * stops if the transfer is going on for the requestor client and all  dma
+ * request will be aborted.
+ *
+ * 7. The client can request for any ammount of the data transfer. If dma is not
+ * capable of transferring the data in one transaction, it will do the multiple
+ * transaction internally and will notify the client after last transaction.
+ *
+ *
+ *                Implementation details
+ *                ----------------------
+ *  1. The implementation should support any number of the apb dma
+ * channel on run time. There should not be any static allocation till it
+ * very necessarily. It does not support the ahb dma.
+ *
+ * 2. 1 dma channel allocated for the  low priority dma channel allocation to
+ * allocate the low priority dma handle. These channes are shared between the
+ * low priority reqestor clients.
+ *
+ * 3. The client will abort the dma request done by him only. It can not cancel
+ * the request done by other clients.
+ *
+ * 4. Dma Request can be queued and there is not any limitation to queue the
+ * request till we have the sufficient memory from the os.
+ *
+ * 5. It supports the synchrnous and asynchrnous, both type of the operation.
+ *
+ * 6. For each dma channel, it allocates the memory for keeping the client
+ * request.
+ * if the number of request is more than the allocated number of list then it
+ * again reallocate the memory for the new request and free the already allocated
+ * list. The old request transferered to the new allocated list. the benifit
+ * of this type of method is that we need not to do the allocation to queue the
+ * request for each transfer request. In this way we can avoid the memory
+ * allocation and freeing of the memory for the each time.
+ * We start the allocation of memory from n and if the number of request is more
+ * than this (n) then reallocation is done for the (n +n) request and if it is
+ * full then again reallocation is done for the (2n + 2n). In this way the order
+ * of allocation is Log(n).
+ *
+ * 7. All apb dma channel inetrrupt is handle in single isr.
+ * The detection of the interrupted dma channel is done by scanning all the dma
+ * channels one by one.
+ *
+ * 8. The apb dma hw control api is called using the function pointer. So
+ * whenever there is difefrence in the handling of the dma request for dma
+ * channel, it uses the dma hw interface.
+ *
+ * 9. I2s channels related request will use the continuous double buffering.
+ * Uart receive (from fifo to memory) will use the continuous double buffering
+ * on same buffer.
+ *
+ */
+
+#include "nvrm_dma.h"
+#include "nvrm_interrupt.h"
+#include "nvrm_power.h"
+#include "nvrm_moduleids.h"
+#include "nvrm_hardware_access.h"
+#include "rm_dma_hw_private.h"
+#include "nvassert.h"
+#include "nvrm_priv_ap_general.h"
+#include "mach/nvrm_linux.h"
+
+/* FIXME move these to some header file */
+NvError NvRmPrivDmaInit(NvRmDeviceHandle hDevice);
+void NvRmPrivDmaDeInit(void);
+NvError NvRmPrivDmaSuspend(void);
+NvError NvRmPrivDmaResume(void);
+
+#define MAX_AVP_DMA_CHANNELS 3
+
+// DMA capabilities -- these currently do not vary between chips
+
+// Maximum dma transfer size for one transfer.
+#define DMA_MAX_TRANSFER_SIZE       0x10000
+
+// Address allignment  reequirement for the dma buffer address
+#define DMA_ADDRESS_ALIGNMENT       4
+
+// Transfer size allignment  for the dma transfer.
+#define DMA_TRANSFER_SIZE_ALIGNMENT 4
+
+// Dma transfer request depth for initial req depth
+#define DMA_TRANSFER_REQ_DEPTH 16
+
+// The end index of the list
+#define DMA_NULL_INDEX 0xFFFF
+
+// Defines the dma request states.
+typedef enum
+{
+    // The request has not been started.
+    RmDmaRequestState_NotStarted = 0x1,
+
+    // The request is running state.
+    RmDmaRequestState_Running ,
+
+    // The request is completed state.
+    RmDmaRequestState_Completed ,
+
+    // The request is stopped state.
+    RmDmaRequestState_Stopped,
+
+    // The request is unused state.
+    RmDmaRequestState_Unused,
+
+    RmDmaRequestState_Force32 = 0x7FFFFFFF
+} RmDmaRequestState;
+
+// Defines the dma channel allocation state.
+typedef enum
+{
+    // Dma channel is free and available for the allocation.
+    RmDmaChannelState_Free = 0x1,
+
+    // The dma channel is free from the client but still it has the request
+    // for the data transfer.
+    RmDmaChannelState_MarkedFree ,
+
+    // Dma channel is used by the client.
+    RmDmaChannelState_Used,
+
+    RmDmaChannelState_Force32 = 0x7FFFFFFF
+} RmDmaChannelState;
+
+// Defines the dma channel transfer mode and property.
+typedef enum
+{
+    // initial value of the states.
+    RmDmaTransferMode_Init = 0x0,
+
+    // Dma channel transfer mode is continuous.
+    RmDmaTransferMode_Continuous = 0x1,
+
+    // Dma channel transfer mode is Double buffering.
+    RmDmaTransferMode_DoubleBuff = 0x2,
+
+    // Dma channel transfer mode is to transfer the same buffer afain and again.
+    RmDmaTransferMode_SameBuff = 0x4,
+
+    // Dma channel transfer where source address is the Xmb address.
+    RmDmaTransferMode_SourceXmb = 0x8,
+
+    // Dma channel transfer where source address is the Peripheral address.
+    RmDmaTransferMode_SourcePeripheral = 0x10,
+
+    // Dma channel transfer request is asynchrnous.
+    RmDmaTransferMode_Asynch = 0x20,
+
+    // Dma channel transfer is for the pin interrupt now.
+    RmDmaTransferMode_PingIntMode = 0x40,
+
+    RmDmaTransferMode_Force32 = 0x7FFFFFFF
+} RmDmaTransferMode;
+
+/**
+ * Combines the Dma transfer request information which will be queued and
+ * require to start the transfer and for notification after transfer completes.
+ */
+typedef struct DmaTransReqRec
+{
+    // Unique Id
+    NvU32 UniqueId;
+
+    // Current state of the channel.
+    RmDmaRequestState State;
+
+    // The dema request transfer mode and details of the request.
+    RmDmaTransferMode TransferMode;
+
+    // The Source address for the data transfer.
+    NvRmPhysAddr SourceAdd;
+
+    // The destiniation address for the data transfer.
+    NvRmPhysAddr DestAdd;
+
+    // The source address wrapping.
+    NvU32 SourceAddWrap;
+
+    // The destination address wrapping.
+    NvU32 DestAddWrap;
+
+    // Number of bytes requested.
+    NvU32 BytesRequested;
+
+    // Number of bytes programmed for current data transfer.
+    NvU32 BytesCurrProgram;
+
+    // Number of bytes remaining to transfer.
+    NvU32 BytesRemaining;
+
+    // The configuartion of dma in terms of register content and channel
+    // register info.
+    DmaChanRegisters DmaChanRegs;
+
+    // Semaphore Id which need to be signalled after completion.
+    NvOsSemaphoreHandle hOnDmaCompleteSema;
+
+    // Semaphore Id which need to be signalled after half of the transfer
+    // completion.
+    NvOsSemaphoreHandle hOnHalfDmaCompleteSema;
+
+    // Semaphore Id which need to be destoyed when new request will be placed
+    // by this list memory.
+    NvOsSemaphoreHandle hLastReqSema;
+
+    // Array based the double link list.
+    NvU16 NextIndex;
+
+    NvU16 PrevIndex;
+
+} DmaTransReq;
+
+/**
+ * Combines the channel information, status, requestor information for the
+ * channel dma, type of dma etc.
+ */
+typedef struct RmDmaChannelRec
+{
+    // State of the channel.
+    RmDmaChannelState ChannelState;
+
+    // Dma priority whether this is low priority channel or high prority
+    // channel.
+    NvRmDmaPriority Priority;
+
+    // Pointer to the list of the transfer request.
+    struct DmaTransReqRec *pTransReqList;
+
+    // Currently maximum request possible.
+    NvU16 MaxReqList;
+
+    // Head index to the request
+    NvU16 HeadReqIndex;
+
+    // Tail Index to the request
+    NvU16 TailReqIndex;
+
+    // Head index to the free list.
+    NvU16 HeadFreeIndex;
+
+    // Mutex to provide the thread/interrupt safety for the channel specific
+    // data.
+    NvOsIntrMutexHandle hIntrMutex;
+
+    // The virtual base address of the channel registers.
+    NvU32 *pVirtChannelAdd;
+
+    // Channel address bank size.
+    NvU32 ChannelAddBankSize;
+
+    // Pointer to the dma hw interface apis strcuture.
+    DmaHwInterface *pHwInterface;
+
+    // Log the last requested size
+    NvU32 LastReqSize;
+
+#if NVOS_IS_LINUX
+    // Channel interrupt handle 
+    NvOsInterruptHandle hIntrHandle;
+#endif
+
+} RmDmaChannel, *RmDmaChannelHandle;
+
+/**
+ * Combines the dma information
+ */
+typedef struct
+{
+    // Device handle.
+    NvRmDeviceHandle hDevice;
+
+    // Actual numbers of Apb dma channels available on the soc.
+    NvU32 NumApbDmaChannels;
+
+    RmDmaChannel *pListApbDmaChannel;
+
+    // Apb Dma General registers
+    DmaGenRegisters ApbDmaGenReg;
+
+    // OS mutex for channel allocation and deallocation:  provide thread safety
+    NvOsMutexHandle hDmaAllocMutex;
+} NvRmPrivDmaInfo;
+
+/**
+ * Combines the Dma requestor and related information which is required for
+ * other dma operation request.
+ */
+typedef struct NvRmDmaRec
+{
+    // Store the Rm device handle
+    NvRmDeviceHandle  hRmDevice;
+
+    // Corresponding dma channel pointer to APB dma for this handle.
+    RmDmaChannel *pDmaChannel;
+
+    // Flag to tells whether 32 bit swap is enabled or not.
+    NvBool IsBitSwapEnable;
+
+    // Unique Id
+    NvU32 UniqueId;
+
+    // Dma requestor module Id.
+    NvRmDmaModuleID DmaReqModuleId;
+
+    // dma requestor instance Id.
+    NvU32 DmaReqInstId;
+
+    // Dma register information which contain the configuration for dma when it
+    // was allocated
+    DmaChanRegisters DmaChRegs;
+
+    // NvOs semaphore which will be used when synchrnous operation is requested.
+    NvOsSemaphoreHandle hSyncSema;
+} NvRmDma;
+
+static NvRmPrivDmaInfo s_DmaInfo;
+static DmaHwInterface s_ApbDmaInterface;
+#if !NVOS_IS_LINUX
+static NvOsInterruptHandle s_ApbDmaInterruptHandle = NULL;
+#endif
+
+NvU32 NvRmDmaUnreservedChannels(void)
+{
+    return s_DmaInfo.NumApbDmaChannels - MAX_AVP_DMA_CHANNELS -
+        TEGRA_SYSTEM_DMA_CH_NUM;
+}
+
+
+/**
+ * Deinitialize the apb dma physical/virtual addresses. This function will
+ * unmap the virtual mapping.
+ *
+ * Thread Safety: Caller responsibility.
+ */
+static void DeInitDmaGeneralHwRegsAddress(void)
+{
+    // Unmap the virtual mapping for apb general register.
+    NvRmPhysicalMemUnmap(s_DmaInfo.ApbDmaGenReg.pGenVirtBaseAdd,
+                         s_DmaInfo.ApbDmaGenReg.GenAddBankSize);
+    s_DmaInfo.ApbDmaGenReg.pGenVirtBaseAdd = NULL;
+}
+
+/**
+ * Initialize the apb dma physical/virtual addresses. This function will get
+ * the physical address of Apb dma channel from Nvrm module APIs, get the
+ * virtual address.
+ *
+ * Thread Safety: Caller responsibility.
+ */
+static NvError InitDmaGeneralHwRegsAddress(void)
+{
+    NvError Error = NvSuccess;
+    NvRmDeviceHandle hDevice = NULL;
+    NvRmModuleID ModuleId;
+    NvRmPhysAddr ApbPhysAddr;
+
+    // Required the valid device handles.
+    hDevice = s_DmaInfo.hDevice;
+
+    // Get the physical base address of the apb dma controller general register.
+    ModuleId = NVRM_MODULE_ID(NvRmPrivModuleID_ApbDma, 0);
+    NvRmModuleGetBaseAddress(hDevice, ModuleId,
+        &ApbPhysAddr, &s_DmaInfo.ApbDmaGenReg.GenAddBankSize);
+
+    // Initialize the apb dma register virtual address.
+    s_DmaInfo.ApbDmaGenReg.pGenVirtBaseAdd = NULL;
+
+    // Get the virtual address of apb dma general base address.
+    Error = NvRmPhysicalMemMap(ApbPhysAddr,
+        s_DmaInfo.ApbDmaGenReg.GenAddBankSize, NVOS_MEM_READ_WRITE,
+        NvOsMemAttribute_Uncached,
+        (void **)&s_DmaInfo.ApbDmaGenReg.pGenVirtBaseAdd);
+
+    return Error;
+}
+
+static NvError AllocateReqList(RmDmaChannel *pDmaChannel, NvU16 MoreListSize)
+{
+    NvU16 Index;
+    DmaTransReq *pTransReqList = NULL;
+    DmaTransReq *pExistTransReqList = pDmaChannel->pTransReqList;
+    NvU32 TotalReqSize = (pDmaChannel->MaxReqList + MoreListSize);
+
+    // Allocate the memory for logging the client requests.
+    pTransReqList = NvOsAlloc(TotalReqSize * sizeof(DmaTransReq));
+    if (!pTransReqList)
+        return NvError_InsufficientMemory;
+
+    NvOsMemset(pTransReqList, 0, TotalReqSize * sizeof(DmaTransReq));
+
+    // Copy the existing request if it exist to the new allocated request list.
+    if (pExistTransReqList)
+    {
+        NvOsMemcpy(pTransReqList, pExistTransReqList,
+                    pDmaChannel->MaxReqList * sizeof(DmaTransReq));
+        NvOsFree(pExistTransReqList);
+    }
+
+    for (Index = pDmaChannel->MaxReqList; Index < TotalReqSize; ++Index)
+    {
+        if (Index == pDmaChannel->MaxReqList)
+            pTransReqList[pDmaChannel->MaxReqList].PrevIndex = DMA_NULL_INDEX;
+        else
+            pTransReqList[Index].PrevIndex = Index-1;
+
+        pTransReqList[Index].NextIndex = Index + 1;
+    }
+    pTransReqList[Index-1].NextIndex = DMA_NULL_INDEX;
+    pDmaChannel->pTransReqList = pTransReqList;
+    pDmaChannel->HeadFreeIndex = pDmaChannel->MaxReqList;
+    pDmaChannel->MaxReqList += MoreListSize;
+    return NvSuccess;
+}
+
+/**
+ * Deinitialize the Apb dma channels. It will free all the memory and resource
+ * allocated for the dma channels.
+ *
+ * Thread Safety: Caller responsibility.
+ */
+static void DeInitDmaChannels(RmDmaChannel *pDmaList, NvU32 TotalChannel)
+{
+    NvU32 i;
+    if (!pDmaList)
+        return;
+
+    for (i = 0; i < TotalChannel; i++)
+    {
+        RmDmaChannel *pDmaChannel = &pDmaList[i];
+        if (pDmaChannel)
+        {
+            NvOsFree(pDmaChannel->pTransReqList);
+            pDmaChannel->MaxReqList = 0;
+
+            // Free the dma virtual maping
+            NvRmPhysicalMemUnmap(pDmaChannel->pVirtChannelAdd,
+                pDmaChannel->ChannelAddBankSize);
+            NvOsIntrMutexDestroy(pDmaChannel->hIntrMutex);
+        }
+    }
+    NvOsFree(pDmaList);
+}
+
+/**
+ * Init Apb dma channels.It makes the list of all available dma channesl and
+ * keep in the free channel list so that it will be available for the
+ * allocation.
+ * Once client ask for dma channel, it will look in the free list and remove the
+ * channel from the free list and attach with the dma handle and keep in the
+ * used list. The client data trasfer request is queued for the dma channels.
+ *
+ * Thread Safety: Caller responsibility.
+ */
+static NvError
+InitDmaChannels(
+    NvRmDeviceHandle hDevice,
+    RmDmaChannel **pDmaChannelList,
+    NvU32 TotalChannel,
+
+    NvRmModuleID DmaModuleId)
+{
+    NvU32 ChanIndex;
+    NvError Error = NvSuccess;
+    RmDmaChannel *pDmaChannel = NULL;
+    NvRmModuleID ModuleId = 0;
+    NvRmPhysAddr ChannelPhysAddr;
+    RmDmaChannel *pDmaList = NULL;
+
+    // Allocate the memory to store the all dma channel information.
+    pDmaList = NvOsAlloc(TotalChannel * sizeof(RmDmaChannel));
+    if (!pDmaList)
+        return NvError_InsufficientMemory;
+
+    // Initialize all dma channel structure with default values.
+    for (ChanIndex = 0; ChanIndex < TotalChannel; ++ChanIndex)
+    {
+        pDmaChannel = &pDmaList[ChanIndex];
+
+        // Initialize all channel member to the initial known states.
+        pDmaChannel->ChannelState = RmDmaChannelState_Free;
+        pDmaChannel->Priority = NvRmDmaPriority_High;
+        pDmaChannel->pTransReqList = NULL;
+        pDmaChannel->MaxReqList = 0;
+        pDmaChannel->HeadReqIndex = DMA_NULL_INDEX;
+        pDmaChannel->TailReqIndex = DMA_NULL_INDEX;
+        pDmaChannel->HeadFreeIndex = DMA_NULL_INDEX;
+        pDmaChannel->hIntrMutex = NULL;
+        pDmaChannel->pVirtChannelAdd = NULL;
+        pDmaChannel->ChannelAddBankSize = 0;
+        pDmaChannel->pHwInterface = &s_ApbDmaInterface;
+    }
+
+    // Allocate the resource and register address for each channels.
+    for (ChanIndex = 0; ChanIndex < TotalChannel; ++ChanIndex)
+    {
+        pDmaChannel = &pDmaList[ChanIndex];
+
+        // Allocate the memory for logging the client request.
+        Error = AllocateReqList(pDmaChannel, DMA_TRANSFER_REQ_DEPTH);
+
+        // Create mutex for the channel access.
+        if (!Error)
+            Error = NvOsIntrMutexCreate(&pDmaChannel->hIntrMutex);
+
+        // Initialize the base address of the channel.
+        if (!Error)
+        {
+            ModuleId = NVRM_MODULE_ID(DmaModuleId, ChanIndex);
+            NvRmModuleGetBaseAddress(hDevice, ModuleId, &ChannelPhysAddr,
+                                &pDmaChannel->ChannelAddBankSize);
+            Error = NvRmPhysicalMemMap(ChannelPhysAddr,
+                pDmaChannel->ChannelAddBankSize, NVOS_MEM_READ_WRITE,
+                NvOsMemAttribute_Uncached,
+                (void **)&pDmaChannel->pVirtChannelAdd);
+        }
+        if (Error)
+            break;
+    }
+
+    if (!Error)
+    {
+        // Allocate last channel as a low priority request, others are
+        // high priority channel
+        *pDmaChannelList = (RmDmaChannel *)pDmaList;
+    }
+    else
+    {
+        DeInitDmaChannels(pDmaList, TotalChannel);
+        *pDmaChannelList = (RmDmaChannel *)NULL;
+    }
+    return Error;
+}
+
+/**
+ * Initialize the Apb dma channels.
+ * Thread Safety: Caller responsibility.
+ */
+static NvError InitAllDmaChannels(void)
+{
+    NvError Error = NvSuccess;
+
+    // Initialize the apb dma channel list.
+    Error = InitDmaChannels(s_DmaInfo.hDevice, &s_DmaInfo.pListApbDmaChannel,
+                s_DmaInfo.NumApbDmaChannels, NvRmPrivModuleID_ApbDmaChannel);
+    return Error;
+}
+
+/**
+ * Deinitialize the Apb dma channels.
+ * Thread Safety: Caller responsibility.
+ */
+static void DeInitAllDmaChannels(void)
+{
+    // Deinitialize the apb dma channels.
+    DeInitDmaChannels(s_DmaInfo.pListApbDmaChannel, s_DmaInfo.NumApbDmaChannels);
+    s_DmaInfo.pListApbDmaChannel = NULL;
+}
+
+/**
+ * DeInitialize the Dmas. It include the deinitializaton of Apb dma channels.
+ * It unmap the dma register address, disable clock of dma, reset the dma,
+ * destroy the dma interrupt threads and destroy the list of all channels.
+ *
+ * Thread Safety: Caller responsibility.
+ */
+static void DeInitDmas(void)
+{
+    // Global disable the dma channels.
+    s_ApbDmaInterface.DmaHwGlobalSetFxn(s_DmaInfo.ApbDmaGenReg.pGenVirtBaseAdd,
+                                                        NV_FALSE);
+
+    // Disable the dma clocks.
+    // Disable clock for the apb dma channels.
+    (void)NvRmPowerModuleClockControl(s_DmaInfo.hDevice, NvRmPrivModuleID_ApbDma,
+                                                        0, NV_FALSE);
+
+    // De-Initialize of the dma channel lists.
+    DeInitAllDmaChannels();
+}
+
+/**
+ * Initialize the Dma. It include the initializaton of Apb dma channels.
+ * It initalize the dma register address, clock of dma, do the reset of dma,
+ * create the dma interrupt threads and make the list of all channels
+ * for allocation.
+ *
+ * Thread Safety: Caller responsibility.
+ */
+static NvError InitDmas(NvRmDeviceHandle hRmDevice)
+{
+    NvError Error = NvSuccess;
+
+    // Initialize of the dma channel lists.
+    Error = InitAllDmaChannels();
+
+    // Enable the clocks of dma channels.
+    if (!Error)
+        Error = NvRmPowerModuleClockControl(hRmDevice, NvRmPrivModuleID_ApbDma,
+                                                        0, NV_TRUE);
+    // Reset the dma channels.
+    if (!Error)
+        NvRmModuleReset(hRmDevice, NVRM_MODULE_ID(NvRmPrivModuleID_ApbDma, 0));
+
+    // Global enable the dma channels.
+    if (!Error)
+        s_ApbDmaInterface.DmaHwGlobalSetFxn(s_DmaInfo.ApbDmaGenReg.pGenVirtBaseAdd,
+                                                            NV_TRUE);
+
+    // If error exist then disable the dma clocks.
+    if (Error)
+        DeInitDmas();
+
+    return Error;
+}
+
+
+/**
+ * Continue the current transfer by sending the next chunk of the data from the
+ * current dma transfer request. This may be called when requested size is
+ * larger than the supported dma transfer size in single go by hw.
+ *
+ */
+static void ApbDmaContinueRemainingTransfer(void *pDmaChan)
+{
+    NvU32 CurrProgSize;
+    NvU32 LastTransferSize;
+    DmaTransReq  *pCurrReq = NULL;
+    NvBool IsDoubleBuff;
+    NvBool IsContMode;
+    RmDmaChannel *pDmaChannel = (RmDmaChannel *)pDmaChan;
+
+    pCurrReq = &pDmaChannel->pTransReqList[pDmaChannel->HeadReqIndex];
+
+    // Get the last transfer size in bytes from the start of the source and
+    // destination address
+    LastTransferSize  = pCurrReq->BytesCurrProgram;
+
+    // Calculate the possible transfer size based on remaining bytes and
+    // maximum transfer size. Updates the remaining size, transfer size and
+    // programmed size accordingly.
+    CurrProgSize = NV_MIN(pCurrReq->BytesRemaining, DMA_MAX_TRANSFER_SIZE);
+
+    IsDoubleBuff = (pCurrReq->TransferMode & RmDmaTransferMode_DoubleBuff)? NV_TRUE: NV_FALSE;
+    IsContMode = (pCurrReq->TransferMode & RmDmaTransferMode_Continuous)? NV_TRUE: NV_FALSE;
+
+    // Program the transfer size.
+    pDmaChannel->pHwInterface->DmaHwSetTransferSizeFxn(&pCurrReq->DmaChanRegs,
+                                                CurrProgSize, IsDoubleBuff);
+    pDmaChannel->pHwInterface->DmaHwStartTransferWithAddIncFxn(
+                    &pCurrReq->DmaChanRegs, 0, LastTransferSize, IsContMode);
+
+    // Update the parameter which will be used in future.
+    pCurrReq->BytesRemaining  -= CurrProgSize;
+    pCurrReq->BytesCurrProgram = CurrProgSize;
+}
+
+
+/**
+ * Handle the dma complete interrupt in once mode.
+ *
+ * Thread Safety: Caller responsibility.
+ */
+static void
+OnDmaCompleteInOnceMode(
+    RmDmaChannel *pDmaChannel,
+    DmaTransReq  *pCurrReq)
+{
+    NvOsSemaphoreHandle hSignalSema = NULL;
+    NvU16 CurrHeadIndex;
+
+    pDmaChannel->pHwInterface->DmaHwAckNClearInterruptFxn(&pCurrReq->DmaChanRegs);
+
+    // The transfer was in running state.
+    // Check if there is data remaining to transfer or not from the
+    // current request. If there is bytes remaining for data transfer
+    // then continue the transfer.
+    if (pCurrReq->BytesRemaining)
+    {
+        pDmaChannel->pHwInterface->DmaContinueRemainingTransferFxn(pDmaChannel);
+        return;
+    }
+
+    pCurrReq->State = RmDmaRequestState_Completed;
+
+    // Store the sempahore whihc need to be signal.
+    hSignalSema = pCurrReq->hOnDmaCompleteSema;
+    pDmaChannel->LastReqSize = pCurrReq->BytesRequested;
+
+    // Free this index.
+    CurrHeadIndex = pDmaChannel->HeadReqIndex;
+    pDmaChannel->HeadReqIndex = pDmaChannel->pTransReqList[CurrHeadIndex].NextIndex;
+    pDmaChannel->pTransReqList[CurrHeadIndex].NextIndex = pDmaChannel->HeadFreeIndex;
+    pDmaChannel->HeadFreeIndex = CurrHeadIndex;
+    if (pDmaChannel->HeadReqIndex == DMA_NULL_INDEX)
+    {
+        pDmaChannel->TailReqIndex = DMA_NULL_INDEX;
+
+        // If channel is marked as free by client then make this channel
+        // for next allocation.
+        if (pDmaChannel->ChannelState == RmDmaChannelState_MarkedFree)
+            pDmaChannel->ChannelState = RmDmaChannelState_Free;
+
+        // Notify the client for the data transfers completes.
+        if (hSignalSema)
+            NvOsSemaphoreSignal(hSignalSema);
+        return;
+    }
+    pCurrReq = &pDmaChannel->pTransReqList[pDmaChannel->HeadReqIndex];
+    pCurrReq->State = RmDmaRequestState_Running;
+    pDmaChannel->pHwInterface->DmaHwStartTransferFxn(&pCurrReq->DmaChanRegs);
+
+    // Generate the notification for the current transfer completes.
+    if (hSignalSema)
+        NvOsSemaphoreSignal(hSignalSema);
+}
+
+static void
+OnDmaCompleteInContinuousMode(
+    RmDmaChannel *pDmaChannel,
+    DmaTransReq  *pCurrReq)
+{
+    NvOsSemaphoreHandle hSignalSema = NULL;
+    NvU16 NextHeadIndex;
+    DmaTransReq  *pNextReq = NULL;
+
+    pDmaChannel->pHwInterface->DmaHwAckNClearInterruptFxn(&pCurrReq->DmaChanRegs);
+
+    // The transfer was in running state.
+    // Check if there is data remaining to transfer or not from the
+    // current request. If there is bytes remaining for data transfer
+    // then continue the transfer.
+    if (pCurrReq->BytesRemaining)
+    {
+        if (pCurrReq->TransferMode & RmDmaTransferMode_PingIntMode)
+        {
+            pCurrReq->TransferMode &= ~RmDmaTransferMode_PingIntMode;
+            pDmaChannel->pHwInterface->DmaContinueRemainingTransferFxn(pDmaChannel);
+        }
+        else
+        {
+            pCurrReq->TransferMode |= RmDmaTransferMode_PingIntMode;
+        }
+        return;
+    }
+
+    NextHeadIndex = pDmaChannel->pTransReqList[pDmaChannel->HeadReqIndex].NextIndex;
+    if (NextHeadIndex != DMA_NULL_INDEX)
+        pNextReq = &pDmaChannel->pTransReqList[NextHeadIndex];
+
+    if (pCurrReq->TransferMode & RmDmaTransferMode_PingIntMode)
+    {
+        if (NextHeadIndex != DMA_NULL_INDEX)
+        {
+            pDmaChannel->pHwInterface->DmaHwContinueTransferFxn(&pNextReq->DmaChanRegs);
+            pNextReq->State = RmDmaRequestState_Running;
+            pNextReq->TransferMode |= RmDmaTransferMode_PingIntMode;
+        }
+        pDmaChannel->pHwInterface->DmaHwAddTransferCountFxn(&pCurrReq->DmaChanRegs);
+
+        if (pCurrReq->hOnHalfDmaCompleteSema)
+            NvOsSemaphoreSignal(pCurrReq->hOnHalfDmaCompleteSema);
+
+
+        pCurrReq->TransferMode &= ~RmDmaTransferMode_PingIntMode;
+        return;
+    }
+
+    pCurrReq->State = RmDmaRequestState_Completed;
+
+    // Store the sempahore which need to be signal.
+    hSignalSema = pCurrReq->hOnDmaCompleteSema;
+
+    if (!pNextReq)
+    {
+        if (pCurrReq->TransferMode & RmDmaTransferMode_SameBuff)
+        {
+            pCurrReq->TransferMode |= RmDmaTransferMode_PingIntMode;
+            pCurrReq->State = RmDmaRequestState_Running;
+            if (hSignalSema)
+                NvOsSemaphoreSignal(pCurrReq->hOnDmaCompleteSema);
+            pDmaChannel->pHwInterface->DmaHwAddTransferCountFxn(&pCurrReq->DmaChanRegs);
+            return;
+        }
+        else
+        {
+            pDmaChannel->pHwInterface->DmaHwStopTransferFxn(&pCurrReq->DmaChanRegs);
+
+            pDmaChannel->pTransReqList[pDmaChannel->HeadReqIndex].NextIndex = pDmaChannel->HeadFreeIndex;
+            pDmaChannel->HeadFreeIndex = pDmaChannel->HeadReqIndex;
+            pDmaChannel->HeadReqIndex = DMA_NULL_INDEX;
+            pDmaChannel->TailReqIndex = DMA_NULL_INDEX;
+
+            // If channel is marked as free then make this channel available
+            // for next allocation.
+            if (pDmaChannel->ChannelState == RmDmaChannelState_MarkedFree)
+                pDmaChannel->ChannelState = RmDmaChannelState_Free;
+        }
+    }
+    else
+    {
+        pDmaChannel->pTransReqList[pDmaChannel->HeadReqIndex].NextIndex = pDmaChannel->HeadFreeIndex;
+        pDmaChannel->HeadFreeIndex = pDmaChannel->HeadReqIndex;
+        pDmaChannel->HeadReqIndex = NextHeadIndex;
+
+        // May be we got this request after ping buffer completion.
+        if (pNextReq->State != RmDmaRequestState_Running)
+        {
+            // Start the next request transfer.
+            pDmaChannel->pHwInterface->DmaHwContinueTransferFxn(&pNextReq->DmaChanRegs);
+            pNextReq->State = RmDmaRequestState_Running;
+            pCurrReq->TransferMode |= RmDmaTransferMode_PingIntMode;
+        }
+    }
+
+    // Generate the notification for the current transfer completes.
+    if (hSignalSema)
+        NvOsSemaphoreSignal(hSignalSema);
+}
+
+
+
+#if NVOS_IS_LINUX
+/**
+ * Handle the Apb dma interrupt.
+ */
+static void ApbDmaIsr(void *args)
+{
+    RmDmaChannel *pDmaChannel = (RmDmaChannel *)args;
+    DmaTransReq *pCurrReq;
+    NvBool IsTransferComplete;
+
+    NvOsIntrMutexLock(pDmaChannel->hIntrMutex);
+    if (pDmaChannel->HeadReqIndex == DMA_NULL_INDEX)
+        goto exit;
+
+    pCurrReq = &pDmaChannel->pTransReqList[pDmaChannel->HeadReqIndex];
+    if (pCurrReq->State != RmDmaRequestState_Running)
+        goto exit;
+
+    IsTransferComplete = pDmaChannel->pHwInterface->DmaHwIsTransferCompletedFxn(
+                                            &pCurrReq->DmaChanRegs);
+    if (IsTransferComplete) {
+        if (pCurrReq->TransferMode & RmDmaTransferMode_Continuous)
+            OnDmaCompleteInContinuousMode(pDmaChannel, pCurrReq);
+        else
+            OnDmaCompleteInOnceMode(pDmaChannel, pCurrReq);
+    }
+
+exit:
+    NvOsIntrMutexUnlock(pDmaChannel->hIntrMutex);
+    NvRmInterruptDone(pDmaChannel->hIntrHandle);
+}
+#else
+static void ApbDmaIsr(void *args)
+{
+    RmDmaChannel *pDmaChannel;
+    DmaTransReq *pCurrReq;
+    NvU32 ChanIndex;
+    NvBool IsTransferComplete;
+
+    for (ChanIndex = 0; ChanIndex < s_DmaInfo.NumApbDmaChannels; ++ChanIndex)
+    {
+        pDmaChannel = &s_DmaInfo.pListApbDmaChannel[ChanIndex];
+        if (pDmaChannel->HeadReqIndex == DMA_NULL_INDEX)
+            continue;
+
+        NvOsIntrMutexLock(pDmaChannel->hIntrMutex);
+        if (pDmaChannel->HeadReqIndex == DMA_NULL_INDEX)
+            goto NextLoop;
+
+        pCurrReq = &pDmaChannel->pTransReqList[pDmaChannel->HeadReqIndex];
+        if (pCurrReq->State != RmDmaRequestState_Running)
+            goto NextLoop;
+
+        IsTransferComplete = pDmaChannel->pHwInterface->DmaHwIsTransferCompletedFxn(
+                                                &pCurrReq->DmaChanRegs);
+        if (!IsTransferComplete)
+            goto NextLoop;
+
+        if (pCurrReq->TransferMode & RmDmaTransferMode_Continuous)
+            OnDmaCompleteInContinuousMode(pDmaChannel, pCurrReq);
+        else
+            OnDmaCompleteInOnceMode(pDmaChannel, pCurrReq);
+
+    NextLoop:
+        NvOsIntrMutexUnlock(pDmaChannel->hIntrMutex);
+    }
+
+    NvRmInterruptDone(s_ApbDmaInterruptHandle);
+}
+#endif
+
+
+/**
+ * Register apb Dma interrupt.
+ */
+static NvError RegisterAllDmaInterrupt(NvRmDeviceHandle hDevice)
+{
+    NvRmModuleID ModuleId = NvRmPrivModuleID_ApbDma;
+    NvError Error = NvSuccess;
+    NvOsInterruptHandler DmaIntHandler = ApbDmaIsr;
+    NvU32 Irq = 0;
+    NvU32 i;
+
+    /* Disable interrupts for all channels */
+    for (i=0; i < s_DmaInfo.NumApbDmaChannels; i++)
+    {
+        NvRmPrivDmaInterruptEnable(hDevice, i, NV_FALSE);
+    }
+
+#if NVOS_IS_LINUX
+    /* Register same interrupt hanlder for all APB DMA channels. */
+    for (i=0; i < NvRmDmaUnreservedChannels(); i++)
+    {
+        Irq = NvRmGetIrqForLogicalInterrupt(hDevice, ModuleId, i);
+        Error = NvRmInterruptRegister(hDevice, 1, &Irq,
+            &DmaIntHandler, &s_DmaInfo.pListApbDmaChannel[i], 
+            &(s_DmaInfo.pListApbDmaChannel[i].hIntrHandle), NV_TRUE);
+    }
+#else
+    /* Register one interrupt handler for all APB DMA channels
+     * Pass index 0xFF to get the main IRQ of the ADB DMA sub-interrupt 
+     * controller. */
+    Irq = NvRmGetIrqForLogicalInterrupt(hDevice, ModuleId, 0xFF);
+    Error = NvRmInterruptRegister(hDevice, 1, &Irq,
+            &DmaIntHandler, hDevice, &s_ApbDmaInterruptHandle, NV_TRUE);
+
+#endif
+
+    if (Error != NvSuccess) return Error;
+
+    /* Enable interrupts for all channels */
+    for (i=0; i < s_DmaInfo.NumApbDmaChannels; i++)
+    {
+        NvRmPrivDmaInterruptEnable(hDevice, i, NV_TRUE);
+    }
+    return Error;
+}
+
+/**
+ * Unregister apb Dma interrupts.
+ */
+static void UnregisterAllDmaInterrupt(NvRmDeviceHandle hDevice)
+{
+#if NVOS_IS_LINUX
+    NvU32 i;
+
+    for (i=0; i < NvRmDmaUnreservedChannels(); i++)
+    {
+        NvRmInterruptUnregister(hDevice,
+            s_DmaInfo.pListApbDmaChannel[i].hIntrHandle);
+    }
+#else
+    NvRmInterruptUnregister(hDevice, s_ApbDmaInterruptHandle);
+    s_ApbDmaInterruptHandle = NULL;
+#endif
+}
+
+/**
+ * Destroy the dma informations. It releases all the memory and os resources
+ * which was allocated to create the dma infomation.
+ * PENDING: What happen if there is a request for data transfer and it is ask
+ * for the DeInit().
+ *
+ */
+static void DestroyDmaInfo(void)
+{
+    // Unregister for the dma interrupts.
+    UnregisterAllDmaInterrupt(s_DmaInfo.hDevice);
+
+    // Deinitialize the dmas.
+    DeInitDmas();
+
+    // Destroy the list of dma channels and release memory for all dma channels.
+    NvOsMutexDestroy(s_DmaInfo.hDmaAllocMutex);
+    s_DmaInfo.hDmaAllocMutex = NULL;
+
+    //Deinitialize the dma hw register address.
+    DeInitDmaGeneralHwRegsAddress();
+}
+
+/**
+ * Create the dma information and setup the dma channesl to their initial state.
+ * It enables all dma channels, make list of dma channels, initailize the
+ * registes address, create reosurces for the channel allocation and bring the
+ * dma driver in know states.
+ *
+ * It creates all the mutex which are used for dma channel, register the
+ * interrupt, enable the clock and reset the dma channel.
+ *
+ * Verification of al the steps is done and if it fails then it relases the
+ * resource which were created and it will return error.
+ *
+ */
+static NvError CreateDmaInfo(NvRmDeviceHandle hDevice)
+{
+    NvError Error = NvSuccess;
+
+    s_DmaInfo.hDevice = hDevice;
+    s_DmaInfo.NumApbDmaChannels =
+            NvRmModuleGetNumInstances(hDevice, NvRmPrivModuleID_ApbDmaChannel);
+
+    NV_ASSERT(s_DmaInfo.NumApbDmaChannels > 0);
+    NV_ASSERT(s_DmaInfo.NumApbDmaChannels <= MAX_APB_DMA_CHANNELS);
+
+    // Initialize the dma hw register addresses.
+    Error = InitDmaGeneralHwRegsAddress();
+
+    // Initialze the channel alllocation mutex.
+    if (!Error)
+        Error = NvOsMutexCreate(&s_DmaInfo.hDmaAllocMutex);
+
+    // Initialze the dma channels.
+    if (!Error)
+        Error = InitDmas(hDevice);
+
+    // Register for the dma interrupts.
+    if (!Error)
+        Error = RegisterAllDmaInterrupt(hDevice);
+
+    if (Error)
+        DestroyDmaInfo();
+    return Error;
+}
+
+/**
+ * Start the dma transfer from the head request of the dma channels.
+ * Thread Safety: Caller responsibilty.
+ */
+static void StartDmaTransfer(RmDmaChannel *pDmaChannel)
+{
+    DmaTransReq *pCurrReq = &pDmaChannel->pTransReqList[pDmaChannel->HeadReqIndex];
+
+    // The state of the transfer will be running state.
+    pCurrReq->State = RmDmaRequestState_Running;
+
+    // Start the dma transfer.
+    pDmaChannel->pHwInterface->DmaHwStartTransferFxn(&pCurrReq->DmaChanRegs);
+}
+
+/**
+ * Stop the current transfer on dma channel immediately.
+ *
+ * Thread Safety: It is caller responsibility.
+ */
+static void StopDmaTransfer(RmDmaChannel *pDmaChannel)
+{
+    // Get the curent request of the dma channel.
+    DmaTransReq *pCurrReq = NULL;
+    if (pDmaChannel->HeadReqIndex != DMA_NULL_INDEX)
+    {
+        pCurrReq = &pDmaChannel->pTransReqList[pDmaChannel->HeadReqIndex];
+        if (pCurrReq->State == RmDmaRequestState_Running)
+        {
+            pDmaChannel->pHwInterface->DmaHwStopTransferFxn(&pCurrReq->DmaChanRegs);
+            pCurrReq->State = RmDmaRequestState_Stopped;
+        }
+    }
+}
+
+/**
+ * Set the mode of the data transfer whether this is once mode or continuous mode
+ * or single buffering or double buffering mode.
+ */
+static void
+SetApbDmaSpecialTransferMode(
+    NvRmDmaHandle hDma,
+    NvBool IsSourceAddPerip,
+    DmaTransReq *pCurrReq)
+{
+    // Special mode of dma transfer is not supported for the low priority channel.
+    if (hDma->pDmaChannel->Priority == NvRmDmaPriority_Low)
+        return;
+
+    // For I2s the continuous double buffering is selected.
+    if (hDma->DmaReqModuleId == NvRmDmaModuleID_I2s ||
+        hDma->DmaReqModuleId == NvRmDmaModuleID_Spdif)
+    {
+        pCurrReq->TransferMode |=  (RmDmaTransferMode_Continuous |
+                                   RmDmaTransferMode_DoubleBuff);
+        hDma->pDmaChannel->pHwInterface->DmaHwSetTransferModeFxn(
+                            &pCurrReq->DmaChanRegs, NV_TRUE, NV_TRUE);
+        pCurrReq->hOnHalfDmaCompleteSema = NULL;
+        return;
+    }
+
+    // For Uart only receive mode is supported in the continuous double transfer
+    if ((hDma->DmaReqModuleId == NvRmDmaModuleID_Uart) && (IsSourceAddPerip))
+    {
+        pCurrReq->TransferMode |=  (RmDmaTransferMode_Continuous |
+                                   RmDmaTransferMode_DoubleBuff |
+                                   RmDmaTransferMode_SameBuff);
+        hDma->pDmaChannel->pHwInterface->DmaHwSetTransferModeFxn(
+                            &pCurrReq->DmaChanRegs, NV_TRUE, NV_TRUE);
+        pCurrReq->hOnHalfDmaCompleteSema = pCurrReq->hOnDmaCompleteSema;
+        return;
+    }
+}
+
+/**
+ * Configure the current request of the apb dma transfer into the request
+ * struture.
+ *
+ * It validates the source and destination address for the dma transfers.
+ * It validates the address wrap and get the address wrapping value.
+ * It sets the ahp/apb address as per dma request.
+ * It set the direction of transfer and destination bit swap.
+ *
+ * It break the dma transfer size in multiple transfer if the request transfer
+ * size is more than supported transfer size of one dma transfer.
+ * Thread Safety: Not required as it will not access any shared informations.
+ *
+ */
+static NvError LogApbDmaTransferRequest(NvRmDmaHandle hDma, void *pCurrRequest)
+{
+    NvBool IsSourceAddPerip;
+    NvBool IsDestAddPerip;
+    NvBool IsDoubleBuff;
+    DmaTransReq *pCurrReq = (DmaTransReq *)pCurrRequest;
+
+    // Find which address is the Perip address.
+    IsSourceAddPerip = NvRmPrivDmaHwIsValidPeripheralAddress(pCurrReq->SourceAdd);
+    IsDestAddPerip = NvRmPrivDmaHwIsValidPeripheralAddress(pCurrReq->DestAdd);
+
+    // Only one of the address should be Peripheral address to use the apb dma.
+    if (((IsSourceAddPerip == NV_TRUE) && (IsDestAddPerip == NV_TRUE)) ||
+        ((IsSourceAddPerip == NV_FALSE) && (IsDestAddPerip == NV_FALSE)))
+    {
+        return NvError_NotSupported;
+    }
+
+    if (IsSourceAddPerip)
+        pCurrReq->TransferMode |= RmDmaTransferMode_SourcePeripheral;
+
+    // Configure for address wrapping of the dma register as per source and
+    // destination address wrapping of this transfer request.
+    hDma->pDmaChannel->pHwInterface->DmaHwSetAddressWrappingFxn(
+                                &pCurrReq->DmaChanRegs, pCurrReq->SourceAddWrap,
+                                pCurrReq->DestAddWrap, pCurrReq->BytesRequested,
+                                IsSourceAddPerip);
+
+    // Configure for source and destination address for data transfer.
+    hDma->pDmaChannel->pHwInterface->DmaHwConfigureAddressFxn(
+                                &pCurrReq->DmaChanRegs, pCurrReq->SourceAdd,
+                                pCurrReq->DestAdd, IsSourceAddPerip);
+
+    // Configure the dma register for direction of transfer as per
+    // source/destination address of this transfer request and dma direction
+    hDma->pDmaChannel->pHwInterface->DmaHwSetDirectionFxn(&pCurrReq->DmaChanRegs,
+                        IsSourceAddPerip);
+
+    if (pCurrReq->TransferMode & RmDmaTransferMode_Asynch)
+        SetApbDmaSpecialTransferMode(hDma, IsSourceAddPerip, pCurrReq);
+
+    // Configure the dma register as per the clients byte swap infrmation
+    // It will swap for destination only
+    if (hDma->IsBitSwapEnable)
+        hDma->pDmaChannel->pHwInterface->DmaHwEnableDestBitSwapFxn(
+                                &pCurrReq->DmaChanRegs, IsDestAddPerip);
+
+    // Configure the dma register for the burst size. This is calculated based
+    // on the requested transfer size.
+    hDma->pDmaChannel->pHwInterface->DmaHwSetBurstSizeFxn(&pCurrReq->DmaChanRegs,
+                        hDma->DmaReqModuleId, pCurrReq->BytesRequested);
+
+    // Configure the dma register for the transfer bytes count. The requested
+    // transfer size can go on many dma transfer cycles.
+    pCurrReq->BytesCurrProgram = NV_MIN(pCurrReq->BytesRequested, DMA_MAX_TRANSFER_SIZE);
+    pCurrReq->BytesRemaining = pCurrReq->BytesRequested - pCurrReq->BytesCurrProgram;
+
+    IsDoubleBuff = (pCurrReq->TransferMode & RmDmaTransferMode_DoubleBuff)? NV_TRUE: NV_FALSE;
+    hDma->pDmaChannel->pHwInterface->DmaHwSetTransferSizeFxn(&pCurrReq->DmaChanRegs,
+                pCurrReq->BytesCurrProgram, IsDoubleBuff);
+    return NvSuccess;
+}
+
+
+/**
+ * Initialize the NvRm dma informations and allocates all resources.
+ */
+NvError NvRmPrivDmaInit(NvRmDeviceHandle hDevice)
+{
+
+    s_ApbDmaInterface.DmaContinueRemainingTransferFxn = ApbDmaContinueRemainingTransfer;
+    s_ApbDmaInterface.LogDmaTransferRequestFxn = LogApbDmaTransferRequest;
+
+    NvRmPrivDmaInitDmaHwInterfaces(&s_ApbDmaInterface);
+
+    // Create the dma information.
+    return CreateDmaInfo(hDevice);
+}
+
+/**
+ * Deinitialize the NvRm dma informations and frees all resources.
+ */
+void NvRmPrivDmaDeInit(void)
+{
+    DestroyDmaInfo();
+}
+
+
+/**
+ * Get the RmDma capabilities.
+ */
+NvError
+NvRmDmaGetCapabilities(
+    NvRmDeviceHandle hDevice,
+    NvRmDmaCapabilities *pRmDmaCaps)
+{
+    NV_ASSERT(hDevice);
+    NV_ASSERT(pRmDmaCaps);
+    pRmDmaCaps->DmaAddressAlignmentSize = DMA_ADDRESS_ALIGNMENT;
+    pRmDmaCaps->DmaGranularitySize = DMA_TRANSFER_SIZE_ALIGNMENT;
+    return NvSuccess;
+}
+
+/**
+ * Allocate the dma handles.
+ *
+ * Implementation Details:
+ * For high priority dma handle, it allocated from the available free channel.
+ * If there is not the free channel then it reutrns error. The high priority dma
+ * requestor client owns the dma channel. Such channel will not be shared by
+ * other clients.
+ *
+ * For low priority dma handle, it allocates the handle from the low priotity
+ * channel. The allocation of hande only fails if there is unsufficient memory
+ * to allocate the  handle. The low priority dma requestor client share the
+ * channel with other clients which is requested for the lower priority dma and
+ * so it can suffer the delayed response.
+ *
+ * Validation of the parameter:
+ * It allocates the memory for the dma handle and if memory allocation fails then
+ * it return error.
+ *
+ * Thread safety: Thread safety is provided by locking the mutex for the dma
+ * data. This will avoid to access the dma data by the other threads. This is
+ * require because it allocate the channel for high priority.
+ *
+ */
+NvError
+NvRmDmaAllocate(
+    NvRmDeviceHandle  hRmDevice,
+    NvRmDmaHandle    *phDma,
+    NvBool            Enable32bitSwap,
+    NvRmDmaPriority   Priority,
+    NvRmDmaModuleID   DmaRequestorModuleId,
+    NvU32             DmaRequestorInstanceId)
+{
+    NvError Error = NvSuccess;
+
+    NvU32 UniqueId;
+    RmDmaChannel *pDmaChannel = NULL;
+    NvRmDmaHandle hNewDma = NULL;
+    RmDmaChannel *pChannelList = NULL;
+    NvU32 ChanIndex;
+
+    NV_ASSERT(hRmDevice);
+    NV_ASSERT(phDma);
+
+    // Do not allow mem->mem DMAs, which use AHB DMA;
+    NV_ASSERT(DmaRequestorModuleId != NvRmDmaModuleID_Memory);
+
+    *phDma = NULL;
+
+    if ((DmaRequestorModuleId == NvRmDmaModuleID_Invalid) ||
+        (DmaRequestorModuleId >= NvRmDmaModuleID_Max))
+    {
+        return NvError_InvalidSourceId;
+    }
+
+    // Create the unique Id for each allocation based on requestors
+    UniqueId = ((DmaRequestorModuleId << 24) | (DmaRequestorInstanceId << 16) |
+                    (NvRmDmaModuleID_Memory << 8));
+
+    // Allocate the memory for the new dma handle.
+    hNewDma = NvOsAlloc(sizeof(*hNewDma));
+
+    // If memory allocation fails then it will return error
+    if (!hNewDma)
+        return NvError_InsufficientMemory;
+
+    // Initialize the allocated memory area with 0
+    NvOsMemset(hNewDma, 0, sizeof(*hNewDma));
+
+    // Log all requestor information in the dma handle for future reference.
+    hNewDma->DmaReqModuleId = DmaRequestorModuleId;
+    hNewDma->DmaReqInstId = DmaRequestorInstanceId;
+    hNewDma->IsBitSwapEnable = Enable32bitSwap;
+    hNewDma->hRmDevice = hRmDevice;
+    hNewDma->UniqueId = UniqueId;
+    hNewDma->pDmaChannel = NULL;
+    hNewDma->hSyncSema = NULL;
+
+    // Create the semaphore for synchronous semaphore allocation.
+    Error = NvOsSemaphoreCreate(&hNewDma->hSyncSema, 0);
+
+    // If error the free the allocation and return error.
+    if (Error)
+        goto ErrorExit;
+
+    // Configure the dma channel configuration registers as per requestor.
+    s_ApbDmaInterface.DmaHwInitRegistersFxn(&hNewDma->DmaChRegs,
+                            DmaRequestorModuleId, DmaRequestorInstanceId);
+
+    // If it is the high priority dma request then allocate the channel from
+    // free available channel.Otherwise it will return the handle and will
+    // share the channel across the clients. All clients with low priority dma
+    // requestor will use the low priority channel.
+
+    // For high priority dma channel request, use the free channel. And for low
+    // priority channel use the used channel low priority channels.
+    pChannelList = s_DmaInfo.pListApbDmaChannel;
+
+    // Going to access the data which is shared across the different thread.
+    NvOsMutexLock(s_DmaInfo.hDmaAllocMutex);
+
+    for (ChanIndex = 0; ChanIndex < NvRmDmaUnreservedChannels(); ++ChanIndex)
+    {
+        pDmaChannel = &pChannelList[ChanIndex];
+        if ((Priority == pDmaChannel->Priority) && (pDmaChannel->ChannelState == RmDmaChannelState_Free))
+            break;
+        pDmaChannel = NULL;
+    }
+
+    // If the dma channel is null then it is error.
+    if (!pDmaChannel)
+    {
+        NvOsMutexUnlock(s_DmaInfo.hDmaAllocMutex);
+        Error = NvError_DmaChannelNotAvailable;
+        goto ErrorExit;
+    }
+
+    // If got the free channel for the high priority then mark at used.
+    if (NvRmDmaPriority_High == Priority)
+        pDmaChannel->ChannelState = RmDmaChannelState_Used;
+
+    NvOsMutexUnlock(s_DmaInfo.hDmaAllocMutex);
+
+    // Attach the dma channel in the dma handle.
+    hNewDma->pDmaChannel = pDmaChannel;
+    hNewDma->DmaChRegs.pHwDmaChanReg = pDmaChannel->pVirtChannelAdd;
+
+    *phDma = hNewDma;
+    return Error;
+
+ErrorExit:
+    NvOsSemaphoreDestroy(hNewDma->hSyncSema);
+    NvOsFree(hNewDma);
+    return Error;
+}
+
+
+/**
+ * Free the dma handle which is allocated to the user.
+ * Implementation Details:
+ * For high priority dma handle, mark the channel free if it has pending
+ * transfer request. If the there is no pending request then release the channel
+ * and add in the free list so that it will be allocated to the other clients.
+ *
+ * For Low priority dma handle, it deletes the handle only. The low priority dma
+ * requestor does not own the channel so the channel will not be added in the
+ * free list.
+ *
+ * Thread safety: Done inside the functions.
+ *
+ */
+void NvRmDmaFree(NvRmDmaHandle hDma)
+{
+    RmDmaChannel *pDmaChannel = NULL;
+
+    // If it is null handle then return.
+    if (!hDma)
+        return;
+
+    // Get the dma channels.
+    pDmaChannel = hDma->pDmaChannel;
+
+    // For high priority dma handle, mark the channel is free.
+    // For Low priority dma handle, it deletes the handle only. The low priority
+    // dma requestor does not own the channel.
+
+    if (NvRmDmaPriority_High == pDmaChannel->Priority)
+    {
+        // Thread safety: Avoid any request for this channel
+        NvOsIntrMutexLock(pDmaChannel->hIntrMutex);
+
+        // If there is a transfer request then mark channel as free but does not
+        // free the channel now. This channel will be free after last transfer
+        // is done.
+        // If there is no pending transfer request then free this channel
+        // immediately so that it will be available for the next allocation.
+        if (pDmaChannel->HeadReqIndex != DMA_NULL_INDEX)
+            pDmaChannel->ChannelState = RmDmaChannelState_MarkedFree;
+        else
+        {
+            // Thread Safety: Lock the channel allocation data base to avoid the
+            // access by other threads
+            pDmaChannel->ChannelState = RmDmaChannelState_Free;
+        }
+        NvOsIntrMutexUnlock(pDmaChannel->hIntrMutex);
+    }
+
+    // Release the semaphore created for the synchronous operation.
+    NvOsSemaphoreDestroy(hDma->hSyncSema);
+
+    // Free the dma channels.
+    NvOsFree(hDma);
+}
+
+
+/**
+ * Start the dma transfer. It queued the rwueste if there is already reueet on
+ * the dma channel.
+ * It supports the synchrnous and asynchrnous request both.
+ *
+ * For sync opeartion, it will wait till timeout or till data transfer completes,
+ * whichever happens first.
+ *
+ * For asynch operation it queued the request, start if no data transfer is
+ * going on the channel and return to the caller. This is the caller
+ * resposibility to synchrnoise the request. On completion, it will signal the
+ * semaphore which was passed alongwith request.
+ * If no sempahor is passed then also it queued the request but after
+ * completion it will not signal the semaphore.
+ *
+ * Thread safety: The thread safety is provided inside the function.
+ *
+ */
+
+NvError
+NvRmDmaStartDmaTransfer(
+    NvRmDmaHandle       hDma,
+    NvRmDmaClientBuffer *pClientBuffer,
+    NvRmDmaDirection    DmaDirection,
+    NvU32               WaitTimeoutInMS,
+    NvOsSemaphoreHandle       AsynchSemaphoreId)
+{
+    DmaTransReq  *pCurrReq = NULL;
+    RmDmaChannel *pDmaChannel = NULL;
+    NvOsSemaphoreHandle hOnCompleteSema = NULL;
+    NvOsSemaphoreHandle hClonedSemaphore = NULL;
+    NvError Error = NvSuccess;
+    NvU16 FreeIndex;
+    NvU16 PrevIndex;
+    NvU16 NextIndex;
+
+    NV_ASSERT(hDma);
+    NV_ASSERT(pClientBuffer);
+
+    // Get the dma info and the dma channel and validate that it shoudl not be
+    // null
+    pDmaChannel = hDma->pDmaChannel;
+
+    // Validate for the source and destination address alignment.
+    NV_ASSERT(!(pClientBuffer->SourceBufferPhyAddress & (DMA_ADDRESS_ALIGNMENT-1)));
+    NV_ASSERT(!(pClientBuffer->DestinationBufferPhyAddress & (DMA_ADDRESS_ALIGNMENT-1)));
+
+    // Validate for the transfer size granularity level.
+    NV_ASSERT(!(pClientBuffer->TransferSize & (DMA_TRANSFER_SIZE_ALIGNMENT-1)));
+
+    //Log the notification parameters after completion.
+    if (WaitTimeoutInMS)
+    {
+         hOnCompleteSema = hDma->hSyncSema;
+    }
+    else
+    {
+        if (AsynchSemaphoreId)
+        {
+            Error = NvOsSemaphoreClone(AsynchSemaphoreId, &hClonedSemaphore);
+            if (Error)
+                return Error;
+            hOnCompleteSema = hClonedSemaphore;
+        }
+    }
+
+    NvOsIntrMutexLock(pDmaChannel->hIntrMutex);
+    if (pDmaChannel->HeadFreeIndex == DMA_NULL_INDEX)
+    {
+        Error = AllocateReqList(pDmaChannel, pDmaChannel->MaxReqList);
+        if (Error)
+            goto Exit;
+    }
+
+    pCurrReq = &pDmaChannel->pTransReqList[pDmaChannel->HeadFreeIndex];
+
+    // Delete the semaphore which was cloned during the last req by this list.
+    NvOsSemaphoreDestroy(pCurrReq->hLastReqSema);
+    pCurrReq->hLastReqSema = NULL;
+
+
+    // Configure the request infromation.
+    pCurrReq->UniqueId = hDma->UniqueId;
+    pCurrReq->TransferMode = RmDmaTransferMode_PingIntMode;
+    pCurrReq->State = RmDmaRequestState_NotStarted;
+    pCurrReq->hOnDmaCompleteSema = hOnCompleteSema;
+    pCurrReq->hOnHalfDmaCompleteSema = NULL;
+
+    if (!WaitTimeoutInMS)
+        pCurrReq->TransferMode |= RmDmaTransferMode_Asynch;
+
+    if (DmaDirection ==  NvRmDmaDirection_Forward)
+    {
+       pCurrReq->SourceAdd = pClientBuffer->SourceBufferPhyAddress;
+       pCurrReq->DestAdd = pClientBuffer->DestinationBufferPhyAddress;
+       pCurrReq->SourceAddWrap = pClientBuffer->SourceAddressWrapSize;
+       pCurrReq->DestAddWrap = pClientBuffer->DestinationAddressWrapSize;
+    }
+    else
+    {
+       pCurrReq->SourceAdd = pClientBuffer->DestinationBufferPhyAddress;
+       pCurrReq->DestAdd = pClientBuffer->SourceBufferPhyAddress;;
+       pCurrReq->SourceAddWrap = pClientBuffer->DestinationAddressWrapSize;
+       pCurrReq->DestAddWrap = pClientBuffer->SourceAddressWrapSize;
+    }
+
+    pCurrReq->BytesRequested = pClientBuffer->TransferSize;
+    pCurrReq->BytesCurrProgram = 0;
+    pCurrReq->BytesRemaining = 0;
+
+    // Copy the Client related information from register to the current request.
+    pCurrReq->DmaChanRegs.ControlReg = hDma->DmaChRegs.ControlReg;
+    pCurrReq->DmaChanRegs.AhbSequenceReg = hDma->DmaChRegs.AhbSequenceReg;
+    pCurrReq->DmaChanRegs.ApbSequenceReg = hDma->DmaChRegs.ApbSequenceReg;
+    pCurrReq->DmaChanRegs.XmbSequenceReg = hDma->DmaChRegs.XmbSequenceReg;
+    pCurrReq->DmaChanRegs.pHwDmaChanReg = hDma->pDmaChannel->pVirtChannelAdd;
+
+
+    // Configure registers as per current data request.
+    Error = hDma->pDmaChannel->pHwInterface->LogDmaTransferRequestFxn(hDma, pCurrReq);
+    if (Error)
+        goto Exit;
+
+    // Adding the request on the list
+    FreeIndex = pDmaChannel->HeadFreeIndex;
+    pDmaChannel->HeadFreeIndex = pDmaChannel->pTransReqList[pDmaChannel->HeadFreeIndex].NextIndex;
+
+    PrevIndex = pDmaChannel->TailReqIndex;
+    if (pDmaChannel->HeadReqIndex == DMA_NULL_INDEX)
+    {
+        pDmaChannel->HeadReqIndex = FreeIndex;
+        pDmaChannel->TailReqIndex = FreeIndex;
+        pDmaChannel->pTransReqList[FreeIndex].NextIndex = DMA_NULL_INDEX;
+        StartDmaTransfer(pDmaChannel);
+    }
+    else
+    {
+        pDmaChannel->pTransReqList[pDmaChannel->TailReqIndex].NextIndex = FreeIndex;
+        pDmaChannel->pTransReqList[FreeIndex].NextIndex = DMA_NULL_INDEX;
+        pDmaChannel->pTransReqList[FreeIndex].PrevIndex = pDmaChannel->TailReqIndex;
+        pDmaChannel->TailReqIndex = FreeIndex;
+    }
+
+    // If asynchronous operation then return.
+    if (!WaitTimeoutInMS)
+    {
+        pCurrReq->hLastReqSema = hClonedSemaphore;
+        goto Exit;
+    }
+    NvOsIntrMutexUnlock(pDmaChannel->hIntrMutex);
+
+    // Not worrying about the wait error as the state of the request will decide
+    // the status of the transfer.
+    (void)NvOsSemaphoreWaitTimeout(hOnCompleteSema, WaitTimeoutInMS);
+
+    // Lock the channel to access the request.
+    NvOsIntrMutexLock(pDmaChannel->hIntrMutex);
+
+    // Check for the state of the current transfer.
+    switch (pCurrReq->State)
+    {
+        case RmDmaRequestState_NotStarted :
+            // Free the req list.
+            NextIndex = pDmaChannel->pTransReqList[FreeIndex].NextIndex;
+            pDmaChannel->pTransReqList[FreeIndex].NextIndex = pDmaChannel->HeadFreeIndex;
+            pDmaChannel->HeadFreeIndex = FreeIndex;
+            if (PrevIndex == DMA_NULL_INDEX)
+            {
+                pDmaChannel->HeadReqIndex = NextIndex;
+                if (NextIndex == DMA_NULL_INDEX)
+                    pDmaChannel->TailReqIndex = DMA_NULL_INDEX;
+            }
+            else
+            {
+                pDmaChannel->pTransReqList[PrevIndex].NextIndex = NextIndex;
+                if (NextIndex != DMA_NULL_INDEX)
+                    pDmaChannel->pTransReqList[NextIndex].PrevIndex = PrevIndex;
+            }
+            Error =  NvError_Timeout;
+            break;
+
+        case RmDmaRequestState_Running:
+            // Current transfer is running so stop it now.
+            StopDmaTransfer(pDmaChannel);
+            if (pDmaChannel->pTransReqList[pDmaChannel->HeadReqIndex].NextIndex
+                            == DMA_NULL_INDEX)
+            {
+                pDmaChannel->HeadReqIndex = DMA_NULL_INDEX;
+                pDmaChannel->TailReqIndex = DMA_NULL_INDEX;
+            }
+            else
+            {
+                pDmaChannel->HeadReqIndex = pDmaChannel->pTransReqList[pDmaChannel->HeadReqIndex].NextIndex;
+            }
+            pDmaChannel->pTransReqList[FreeIndex].NextIndex = pDmaChannel->HeadFreeIndex;
+            pDmaChannel->HeadFreeIndex = FreeIndex;
+
+            // if there is more request then Start the transfer now.
+            if (pDmaChannel->HeadReqIndex != DMA_NULL_INDEX)
+                StartDmaTransfer(pDmaChannel);
+            Error =  NvError_Timeout;
+            break;
+
+
+        case RmDmaRequestState_Completed:
+            // If transfer is completed then transfer state will be NvSuccess;
+            Error =  NvSuccess;
+            break;
+
+        default:
+            NV_ASSERT(!"Client Request is in the invalid state");
+            break;
+    }
+
+Exit:
+    NvOsIntrMutexUnlock(pDmaChannel->hIntrMutex);
+    if (Error)
+        NvOsSemaphoreDestroy(hClonedSemaphore);
+
+    return Error;
+}
+
+/**
+ * It Immediately stop the dma transfer in the channel, delete all the request
+ * from the queue,
+ * Free all the memory of requests.
+ *
+ * Thread safety: During killing of all request, the channel specific data
+ * access is locked to avoid the access of these data by the other thread.
+ * This provide the thread safety.
+ *
+ * For async queued request, the semaphore Id which was passed with start
+ * transfer request are not destroyed. This is the caller responsibility to
+ * destroy all the semaphore which was passed.
+ *
+ */
+void NvRmDmaAbort(NvRmDmaHandle hDma)
+{
+    NvU16 ReqIndex;
+    NvU16 NextIndex;
+    NvU16 PrevIndex;
+    RmDmaChannel *pDmaChannel = NULL;
+    NvBool IsRequireToStart = NV_FALSE;
+
+    // If null dma handle then return.
+    if (!hDma)
+        return;
+
+    // Get the dma channel pointer and if its null pointer then return.
+    pDmaChannel = hDma->pDmaChannel;
+
+    // The process of killing all the request is depends on the priority of the
+    // dma.
+    if (NvRmDmaPriority_High == pDmaChannel->Priority)
+    {
+        // Stop the dma transfer.
+        StopDmaTransfer(pDmaChannel);
+
+        // Kill all request
+        // Lock the channel related data base to avoid the access by other
+        // client.
+        NvOsIntrMutexLock(pDmaChannel->hIntrMutex);
+
+        ReqIndex = pDmaChannel->HeadReqIndex;
+        while (ReqIndex != DMA_NULL_INDEX)
+        {
+            NextIndex = pDmaChannel->pTransReqList[ReqIndex].NextIndex;
+            if (pDmaChannel->pTransReqList[ReqIndex].hOnDmaCompleteSema)
+            {
+                NvOsSemaphoreDestroy(pDmaChannel->pTransReqList[ReqIndex].hOnDmaCompleteSema);
+                pDmaChannel->pTransReqList[ReqIndex].hLastReqSema = NULL;
+                pDmaChannel->pTransReqList[ReqIndex].hOnDmaCompleteSema = NULL;
+            }
+
+            if (pDmaChannel->HeadFreeIndex != DMA_NULL_INDEX)
+                pDmaChannel->pTransReqList[ReqIndex].NextIndex = pDmaChannel->HeadFreeIndex;
+            pDmaChannel->HeadFreeIndex = ReqIndex;
+            ReqIndex = NextIndex;
+        }
+        pDmaChannel->HeadReqIndex = DMA_NULL_INDEX;
+        pDmaChannel->TailReqIndex = DMA_NULL_INDEX;
+
+        // Unlock the channel related data base so that it can be access by
+        // other client
+        NvOsIntrMutexUnlock(pDmaChannel->hIntrMutex);
+    }
+    else
+    {
+        // Lock the channel access mutex.
+        NvOsIntrMutexLock(pDmaChannel->hIntrMutex);
+
+        // Check whether the abort request is for current running transfer
+        // or not. The identification is done based on unique Id.
+        IsRequireToStart = NV_FALSE;
+        if (pDmaChannel->pTransReqList[pDmaChannel->HeadReqIndex].UniqueId ==
+                                                            hDma->UniqueId)
+        {
+            // The request need to be abort so stop the dma channel.
+            StopDmaTransfer(pDmaChannel);
+            IsRequireToStart = NV_TRUE;
+        }
+
+        ReqIndex = pDmaChannel->HeadReqIndex;
+        PrevIndex = DMA_NULL_INDEX;
+        while (ReqIndex != DMA_NULL_INDEX)
+        {
+            NextIndex = pDmaChannel->pTransReqList[ReqIndex].NextIndex;
+            if (pDmaChannel->pTransReqList[ReqIndex].UniqueId == hDma->UniqueId)
+            {
+                if (pDmaChannel->pTransReqList[ReqIndex].hOnDmaCompleteSema)
+                {
+                    NvOsSemaphoreDestroy(pDmaChannel->pTransReqList[ReqIndex].hOnDmaCompleteSema);
+                    pDmaChannel->pTransReqList[ReqIndex].hLastReqSema = NULL;
+                    pDmaChannel->pTransReqList[ReqIndex].hOnDmaCompleteSema = NULL;
+                }
+                if (PrevIndex != DMA_NULL_INDEX)
+                    pDmaChannel->pTransReqList[PrevIndex].NextIndex = NextIndex;
+
+                if (NextIndex == DMA_NULL_INDEX)
+                    pDmaChannel->TailReqIndex = PrevIndex;
+                else
+                    pDmaChannel->pTransReqList[NextIndex].PrevIndex = PrevIndex;
+                pDmaChannel->pTransReqList[ReqIndex].NextIndex = pDmaChannel->HeadFreeIndex;
+                pDmaChannel->HeadFreeIndex = ReqIndex;
+            }
+            PrevIndex = ReqIndex;
+            if (pDmaChannel->HeadReqIndex == ReqIndex)
+                    pDmaChannel->HeadReqIndex = NextIndex;
+            ReqIndex = NextIndex;
+        }
+        if (pDmaChannel->HeadReqIndex != DMA_NULL_INDEX)
+        {
+            if (IsRequireToStart)
+                StartDmaTransfer(pDmaChannel);
+        }
+        // Unlock the channel access mutex.
+        NvOsIntrMutexUnlock(pDmaChannel->hIntrMutex);
+    }
+}
+
+#define DEBUG_GET_COUNT 0
+NvError NvRmDmaGetTransferredCount(
+    NvRmDmaHandle hDma,
+    NvU32 *pTransferCount,
+    NvBool IsTransferStop )
+{
+    DmaTransReq  *pCurrReq = NULL;
+    NvError Error = NvSuccess;
+#if DEBUG_GET_COUNT
+    NvBool IsPrint = NV_TRUE;
+#endif
+
+    NV_ASSERT(hDma);
+    NV_ASSERT(pTransferCount);
+
+    NvOsIntrMutexLock(hDma->pDmaChannel->hIntrMutex);
+
+    if (hDma->pDmaChannel->HeadReqIndex == DMA_NULL_INDEX)
+    {
+        *pTransferCount = hDma->pDmaChannel->LastReqSize;
+#if DEBUG_GET_COUNT
+        NvOsDebugPrintf("RmDmaGetTransCount ERROR1\n");
+#endif
+        goto ErrorExit;
+    }
+
+    pCurrReq = &hDma->pDmaChannel->pTransReqList[hDma->pDmaChannel->HeadReqIndex];
+    if ((pCurrReq->State != RmDmaRequestState_Running) &&
+            (pCurrReq->State != RmDmaRequestState_Stopped))
+    {
+        Error = NvError_InvalidState;
+#if DEBUG_GET_COUNT
+        NvOsDebugPrintf("RmDmaGetTransCount ERROR\n");
+#endif
+        goto ErrorExit;
+    }
+
+    if (IsTransferStop)
+    {
+        if (pCurrReq->State == RmDmaRequestState_Running)
+        {
+            *pTransferCount = hDma->pDmaChannel->pHwInterface->DmaHwGetTransferredCountWithStopFxn(
+                                &pCurrReq->DmaChanRegs, NV_TRUE);
+            pCurrReq->State = RmDmaRequestState_Stopped;
+            hDma->pDmaChannel->pHwInterface->DmaHwStopTransferFxn(&pCurrReq->DmaChanRegs);
+        }
+        else
+        {
+            *pTransferCount = hDma->pDmaChannel->pHwInterface->DmaHwGetTransferredCountFxn(
+                                        &pCurrReq->DmaChanRegs);
+        }
+    }
+    else
+    {
+        if (pCurrReq->State == RmDmaRequestState_Stopped)
+        {
+            pCurrReq->State = RmDmaRequestState_Running;
+            hDma->pDmaChannel->pHwInterface->DmaHwStartTransferFxn(&pCurrReq->DmaChanRegs);
+            *pTransferCount = 0;
+#if DEBUG_GET_COUNT
+                IsPrint = NV_FALSE;
+#endif
+        }
+        else
+        {
+            *pTransferCount = hDma->pDmaChannel->pHwInterface->DmaHwGetTransferredCountFxn(
+                                        &pCurrReq->DmaChanRegs);
+        }
+    }
+
+#if DEBUG_GET_COUNT
+          NvOsDebugPrintf("RmDmaGetTransCount() TransferCount 0x%08x \n", *pTransferCount);
+#endif
+
+ErrorExit:
+    NvOsIntrMutexUnlock(hDma->pDmaChannel->hIntrMutex);
+    return Error;
+}
+
+NvBool NvRmDmaIsDmaTransferCompletes(
+    NvRmDmaHandle hDma,
+    NvBool IsFirstHalfBuffer)
+{
+    // This API is not supported in the os level driver.
+    NV_ASSERT(0);
+    return NV_FALSE;
+}
+
+
+NvError NvRmPrivDmaSuspend()
+{
+    // Global disable the dma channels.
+    s_ApbDmaInterface.DmaHwGlobalSetFxn(s_DmaInfo.ApbDmaGenReg.pGenVirtBaseAdd,
+                                                        NV_FALSE);
+    // Disables clocks
+    (void)NvRmPowerModuleClockControl(s_DmaInfo.hDevice, NvRmPrivModuleID_ApbDma,
+                                                        0, NV_FALSE);
+    return NvSuccess;
+}
+
+NvError NvRmPrivDmaResume()
+{
+    // Global enable the dma channels.
+    s_ApbDmaInterface.DmaHwGlobalSetFxn(s_DmaInfo.ApbDmaGenReg.pGenVirtBaseAdd,
+                                                        NV_TRUE);
+    // Enables clocks
+    (void)NvRmPowerModuleClockControl(s_DmaInfo.hDevice, NvRmPrivModuleID_ApbDma,
+                                                        0, NV_TRUE);
+    return NvSuccess;
+}
diff --git a/arch/arm/mach-tegra/nvrm/io/ap15/nvrm_gpio.c b/arch/arm/mach-tegra/nvrm/io/ap15/nvrm_gpio.c
new file mode 100644
index 000000000000..f20aa44712bd
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/io/ap15/nvrm_gpio.c
@@ -0,0 +1,520 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/gpio.h>
+#include <linux/irq.h>
+#include <mach/gpio.h>
+
+#include "nvrm_gpio.h"
+#include "nvos.h"
+#include "nvrm_structure.h"
+#include "nvrm_pmu.h"
+#include "nvrm_pinmux_utils.h"
+#include "ap15/ap15rm_private.h"
+#include "ap15/ap15rm_gpio_vi.h"
+#include "nvodm_gpio_ext.h"
+#include "nvodm_query_discovery.h"
+#include "nvrm_hwintf.h"
+#include "nvassert.h"
+
+/* Treats GPIO pin handle releases like the pin is completely invalidated:
+ * returned to SFIO state and tristated. */
+#define RELEASE_IS_INVALIDATE 1
+#define NV_ENABLE_GPIO_POWER_RAIL 1
+
+#define TOTAL_GPIO_BANK    7
+#define GPIO_PORT_PER_BANK 4
+#define GPIO_PIN_PER_PORT  8
+#define GPIO_PORT_ID(bank, port)  ((((bank)&0xFF) << 2) | (((port) & 0x3)))
+#define GPIO_PIN_ID(bank, port, pin)  ((((bank)&0xFF) << 5) | \
+					(((port) & 0x3) <<3) | ((pin) & 0x7))
+
+#define GET_PIN(h)      ((((NvU32)(h))) & 0xFF)
+#define GET_PORT(h)     ((((NvU32)(h)) >> 8) & 0xFF)
+#define GET_BANK(h)     ((((NvU32)(h)) >> 16) & 0xFF)
+
+#define NVRM_GPIO_CAP_FEAT_EDGE_INTR  0x000000001
+#define GPIO_ARCH_FEATURE  (NVRM_GPIO_CAP_FEAT_EDGE_INTR)
+
+extern int tegra_gpio_io_power_config(int gpio_nr, unsigned int enable);
+
+typedef struct NvRmGpioPinInfoRec {
+	NvBool used;
+	NvU32 port;
+	NvU32 inst;
+	NvU32 pin;
+	NvRmGpioPinMode mode;
+	/* Sets up a chain of pins associated by one semaphore.
+	 * Usefull to parse the pins when an interrupt is received. */
+	NvU32 nextPin;
+	NvU16 irqNumber;
+} NvRmGpioPinInfo;
+
+typedef struct NvRmGpioRec {
+	NvU32 RefCount;
+	NvRmDeviceHandle hRm;
+	NvRmGpioPinInfo *pPinInfo;
+} NvRmGpio;
+
+static NvRmGpioHandle s_hGpio = NULL;
+static NvOsMutexHandle s_GpioMutex = NULL;
+
+NvError NvRmGpioOpen(NvRmDeviceHandle hRm, NvRmGpioHandle * phGpio)
+{
+	NvError err = NvSuccess;
+	NvU32 total_pins;
+	NvU32 i;
+
+	NV_ASSERT(hRm);
+	NV_ASSERT(phGpio);
+
+	if (!s_GpioMutex) {
+		err = NvOsMutexCreate(&s_GpioMutex);
+		if (err != NvSuccess)
+			goto fail;
+	}
+
+	NvOsMutexLock(s_GpioMutex);
+	if (s_hGpio) {
+		s_hGpio->RefCount++;
+		goto exit;
+	}
+
+	s_hGpio = (NvRmGpio *) NvOsAlloc(sizeof(NvRmGpio));
+	if (!s_hGpio) {
+		err = NvError_InsufficientMemory;
+		goto exit;
+	}
+	NvOsMemset(s_hGpio, 0, sizeof(NvRmGpio));
+	s_hGpio->hRm = hRm;
+
+	total_pins = TOTAL_GPIO_BANK * GPIO_PORT_PER_BANK * GPIO_PIN_PER_PORT;
+	s_hGpio->pPinInfo = NvOsAlloc(sizeof(NvRmGpioPinInfo) * total_pins);
+	if (s_hGpio->pPinInfo == NULL) {
+		NvOsFree(s_hGpio);
+		err = NvError_InsufficientMemory;
+		s_hGpio = NULL;
+		goto exit;
+	}
+	NvOsMemset(s_hGpio->pPinInfo, 0, sizeof(NvRmGpioPinInfo) * total_pins);
+	for (i = 0; i < total_pins; i++)
+		s_hGpio->pPinInfo[i].irqNumber = NVRM_IRQ_INVALID;
+	s_hGpio->RefCount++;
+
+exit:
+	*phGpio = s_hGpio;
+	NvOsMutexUnlock(s_GpioMutex);
+
+fail:
+	return err;
+}
+
+void NvRmGpioClose(NvRmGpioHandle hGpio)
+{
+	if (!hGpio)
+		return;
+
+	NV_ASSERT(hGpio->RefCount);
+
+	NvOsMutexLock(s_GpioMutex);
+	hGpio->RefCount--;
+	if (hGpio->RefCount == 0) {
+		NvOsFree(s_hGpio->pPinInfo);
+		NvOsFree(s_hGpio);
+		s_hGpio = NULL;
+	}
+	NvOsMutexUnlock(s_GpioMutex);
+}
+
+NvError
+NvRmGpioAcquirePinHandle(NvRmGpioHandle hGpio,
+			 NvU32 port, NvU32 pinNumber, NvRmGpioPinHandle * phPin)
+{
+	int gpio_nr;
+	int ret_status;
+
+	NV_ASSERT(hGpio != NULL);
+
+	if (port == NVRM_GPIO_CAMERA_PORT) {
+		NvOsMutexLock(s_GpioMutex);
+		/* The Camera has dedicated gpio pins that must be controlled
+		 * through a non-standard gpio port control. */
+		NvRmPrivGpioViAcquirePinHandle(hGpio->hRm, pinNumber);
+		*phPin = GPIO_MAKE_PIN_HANDLE(NVRM_GPIO_CAMERA_INST, port,
+		 					pinNumber);
+		NvOsMutexUnlock(s_GpioMutex);
+	} else if ((port >= NVODM_GPIO_EXT_PORT_0) &&
+		   (port <= NVODM_GPIO_EXT_PORT_F)) {
+		/* Create a pin handle for GPIOs that are
+		 * sourced by external (off-chip) peripherals */
+		*phPin = GPIO_MAKE_PIN_HANDLE((port & 0xFF), port, pinNumber);
+	} else {
+		gpio_nr = GPIO_PIN_ID((port >> 2), (port & 0x3), pinNumber);
+		if ((gpio_nr >= ARCH_NR_GPIOS) ||
+			 (pinNumber >= GPIO_PIN_PER_PORT)) {
+			printk(KERN_ERR "Requested port %d or pin %d  number "
+					" is not supported", port, pinNumber);
+			return NvError_NotSupported;
+		}
+		ret_status = gpio_request(gpio_nr, "nvrm_gpio");
+		if (unlikely(ret_status != 0)) {
+			return NvError_AlreadyAllocated;
+		}
+		*phPin = GPIO_MAKE_PIN_HANDLE((port >> 2), (port & 0x3),
+						 pinNumber);
+	}
+	return NvSuccess;
+}
+
+void NvRmGpioReleasePinHandles(NvRmGpioHandle hGpio,
+			       NvRmGpioPinHandle * hPin, NvU32 pinCount)
+{
+	NvU32 i;
+	NvU32 port;
+	NvU32 pin;
+	NvU32 bank;
+	int gpio_nr;
+	NvU32 alphaPort;
+
+	if (hPin == NULL)
+		return;
+
+	for (i = 0; i < pinCount; i++) {
+		bank = GET_BANK(hPin[i]);
+		port = GET_PORT(hPin[i]);
+		pin = GET_PIN(hPin[i]);
+		NvOsMutexLock(s_GpioMutex);
+		if (port == NVRM_GPIO_CAMERA_PORT) {
+			NvRmPrivGpioViReleasePinHandles(hGpio->hRm, pin);
+		} else if ((port >= NVODM_GPIO_EXT_PORT_0) &&
+			   (port <= NVODM_GPIO_EXT_PORT_F)) {
+			/* Do nothing for now... */
+		} else {
+			gpio_nr = GPIO_PIN_ID(bank, port & 0x3, pin);
+			if (gpio_nr >= ARCH_NR_GPIOS) {
+				printk(KERN_ERR "Illegal pin handle at place "
+						" %u of the list\n",i);
+				NvOsMutexUnlock(s_GpioMutex);
+				continue;
+			}
+			gpio_free(gpio_nr);
+			alphaPort = (NvU32) GPIO_PORT_ID(bank, port);
+			if (s_hGpio->pPinInfo[gpio_nr].used) {
+				NV_DEBUG_PRINTF(("Warning: Releasing in-use "
+					"GPIO pin handle GPIO_P%c.%02u "
+					"(%c=%u)\n", 'A' + alphaPort, pin,
+					'A' + alphaPort, alphaPort));
+#if RELEASE_IS_INVALIDATE
+				tegra_gpio_disable(gpio_nr);
+				NvRmSetGpioTristate(hGpio->hRm,
+					alphaPort, pin, NV_TRUE);
+				s_hGpio->pPinInfo[gpio_nr].used = NV_FALSE;
+#endif
+			}
+		}
+		NvOsMutexUnlock(s_GpioMutex);
+	}
+	return;
+}
+
+void NvRmGpioReadPins(NvRmGpioHandle hGpio,
+		      NvRmGpioPinHandle * hPin,
+		      NvRmGpioPinState * pPinState, NvU32 pinCount)
+{
+	NvU32 bank;
+	NvU32 port;
+	NvU32 pin;
+	NvU32 i;
+	int gpio_nr;
+
+	NV_ASSERT(hPin != NULL);
+	NV_ASSERT(hGpio != NULL);
+
+	for (i = 0; i < pinCount; i++) {
+		port = GET_PORT(hPin[i]);
+		pin = GET_PIN(hPin[i]);
+		bank = GET_BANK(hPin[i]);
+
+		if (port == NVRM_GPIO_CAMERA_PORT) {
+			pPinState[i] = NvRmPrivGpioViReadPins(hGpio->hRm, pin);
+		} else if ((port >= (NvU32) NVODM_GPIO_EXT_PORT_0) &&
+			   (port <= (NvU32) NVODM_GPIO_EXT_PORT_F)) {
+			pPinState[i] = NvOdmExternalGpioReadPins(port, pin);
+		} else {
+			gpio_nr = GPIO_PIN_ID(bank, port, pin);
+			if (gpio_nr >= ARCH_NR_GPIOS) {
+				printk(KERN_ERR "Illegal pin handle at place "
+						" %u of the list\n",i);
+				continue;
+			}
+			pPinState[i] = gpio_get_value(gpio_nr) & 0x1;
+		}
+	}
+}
+
+void NvRmGpioWritePins(NvRmGpioHandle hGpio,
+		       NvRmGpioPinHandle * hPin,
+		       NvRmGpioPinState * pPinState, NvU32 pinCount)
+{
+	NvU32 port;
+	NvU32 pin;
+	NvU32 bank;
+	NvU32 i;
+	int gpio_nr;
+
+	NV_ASSERT(hPin != NULL);
+	NV_ASSERT(hGpio != NULL);
+
+	for (i = 0; i < pinCount; i++) {
+		port = GET_PORT(hPin[i]);
+		pin = GET_PIN(hPin[i]);
+		bank = GET_BANK(hPin[i]);
+
+		if (port == NVRM_GPIO_CAMERA_PORT) {
+			NvRmPrivGpioViWritePins(hGpio->hRm, pin, pPinState[i]);
+		} else if ((port >= (NvU32) NVODM_GPIO_EXT_PORT_0) &&
+			   (port <= (NvU32) NVODM_GPIO_EXT_PORT_F)) {
+			NvOdmExternalGpioWritePins(port, pin, pPinState[i]);
+		} else {
+			gpio_nr = GPIO_PIN_ID(bank, port, pin);
+			if (gpio_nr >= ARCH_NR_GPIOS) {
+				printk(KERN_ERR "Illegal pin handle at place "
+						" %u of the list\n",i);
+				continue;
+			}
+			gpio_set_value(gpio_nr, pPinState[i] & 0x1);
+		}
+	}
+
+	return;
+}
+
+NvError NvRmGpioConfigPins(NvRmGpioHandle hGpio,
+			   NvRmGpioPinHandle * hPin,
+			   NvU32 pinCount, NvRmGpioPinMode Mode)
+{
+	NvError err = NvSuccess;
+	NvU32 i;
+	NvU32 bank;
+	NvU32 port;
+	NvU32 pin;
+	NvU32 alphaPort;
+	int ret_status;
+	int gpio_nr;
+	struct irq_chip *chip;
+	int gpio_irq;
+
+	NvOsMutexLock(s_GpioMutex);
+
+	for (i = 0; i < pinCount; i++) {
+		bank = GET_BANK(hPin[i]);
+		port = GET_PORT(hPin[i]);
+		pin = GET_PIN(hPin[i]);
+
+		if (port == NVRM_GPIO_CAMERA_PORT) {
+			/* If they are trying to do the wrong thing, assert.
+			 * If they are trying to do the only allowed thing,
+			 * quietly skip it, as nothing needs to be done. */
+			if (Mode != NvOdmGpioPinMode_Output) {
+				NV_ASSERT(!"Only output is supported for "
+						"camera gpio.\n");
+			}
+			continue;
+		}
+
+		/* Absolute pin number to index into pPinInfo array and
+		 * the alphabetic port names. */
+		gpio_nr = GPIO_PIN_ID(bank, port, pin);
+		gpio_irq = gpio_to_irq(gpio_nr);
+		if (gpio_nr >= ARCH_NR_GPIOS) {
+			printk(KERN_ERR "Illegal pin handle at place "
+					" %u of the list\n",i);
+			continue;
+		}
+
+		alphaPort = GPIO_PORT_ID(bank, port);
+
+		s_hGpio->pPinInfo[gpio_nr].mode = Mode;
+		s_hGpio->pPinInfo[gpio_nr].inst = bank;
+		s_hGpio->pPinInfo[gpio_nr].port = port;
+		s_hGpio->pPinInfo[gpio_nr].pin = pin;
+
+		/* Don't try to colapse this swtich as the ordering of
+		 * the register writes matter. */
+		switch (Mode) {
+		case NvRmGpioPinMode_Output:
+			tegra_gpio_enable(gpio_nr);
+			ret_status = gpio_direction_output(gpio_nr, 0);
+			if (unlikely(ret_status != 0)) {
+				NV_ASSERT(!"Not initialized");
+				return NvError_NotInitialized;
+			}
+			break;
+
+		case NvRmGpioPinMode_InputData:
+			tegra_gpio_enable(gpio_nr);
+			ret_status = gpio_direction_input(gpio_nr);
+			if (unlikely(ret_status != 0)) {
+				NV_ASSERT(!"Not initialized");
+				return NvError_NotInitialized;
+			}
+			break;
+
+		case NvRmGpioPinMode_InputInterruptLow:
+			gpio_direction_input(gpio_nr);
+			tegra_gpio_enable(gpio_nr);
+			chip = get_irq_chip(gpio_irq);
+			if ((chip) && (chip->set_type))
+				chip->set_type(gpio_irq, IRQ_TYPE_LEVEL_LOW);
+			break;
+
+		case NvRmGpioPinMode_InputInterruptHigh:
+			gpio_direction_input(gpio_nr);
+			tegra_gpio_enable(gpio_nr);
+			chip = get_irq_chip(gpio_irq);
+			if ((chip) && (chip->set_type))
+				chip->set_type(gpio_irq, IRQ_TYPE_LEVEL_HIGH);
+			break;
+
+		case NvRmGpioPinMode_InputInterruptAny:
+			if (GPIO_ARCH_FEATURE & NVRM_GPIO_CAP_FEAT_EDGE_INTR) {
+				gpio_direction_input(gpio_nr);
+				tegra_gpio_enable(gpio_nr);
+				chip = get_irq_chip(gpio_irq);
+				if ((chip) && (chip->set_type))
+					chip->set_type(gpio_irq,
+						       IRQ_TYPE_EDGE_BOTH);
+			} else {
+				NV_ASSERT(!"Not supported");
+			}
+			break;
+
+		case NvRmGpioPinMode_Function:
+			tegra_gpio_disable(gpio_nr);
+			break;
+
+		case NvRmGpioPinMode_Inactive:
+			chip = get_irq_chip(gpio_irq);
+			if ((chip) && (chip->set_type))
+				chip->mask(gpio_irq);
+			tegra_gpio_disable(gpio_nr);
+			break;
+
+		case NvRmGpioPinMode_InputInterruptRisingEdge:
+			if (GPIO_ARCH_FEATURE & NVRM_GPIO_CAP_FEAT_EDGE_INTR) {
+				gpio_direction_input(gpio_nr);
+				tegra_gpio_enable(gpio_nr);
+
+				chip = get_irq_chip(gpio_irq);
+				if ((chip) && (chip->set_type))
+					chip->set_type(gpio_irq,
+						       IRQ_TYPE_EDGE_RISING);
+			} else {
+				NV_ASSERT(!"Not supported");
+			}
+			break;
+
+		case NvRmGpioPinMode_InputInterruptFallingEdge:
+			if (GPIO_ARCH_FEATURE & NVRM_GPIO_CAP_FEAT_EDGE_INTR) {
+				gpio_direction_input(gpio_nr);
+				tegra_gpio_enable(gpio_nr);
+				chip = get_irq_chip(gpio_irq);
+				if ((chip) && (chip->set_type))
+					chip->set_type(gpio_irq,
+						       IRQ_TYPE_EDGE_FALLING);
+			} else {
+				NV_ASSERT(!"Not supported");
+			}
+			break;
+
+		default:
+			NV_ASSERT(!"Invalid gpio mode");
+			break;
+		}
+
+		/*  Pad group global tristates are only modified when
+		 *  the pin transitions from an inactive state to an
+		 *  active one.  Active-to-active and inactive-to-inactive
+		 * transitions are ignored */
+		if ((!s_hGpio->pPinInfo[gpio_nr].used)
+		    && (Mode != NvRmGpioPinMode_Inactive)) {
+#if NV_ENABLE_GPIO_POWER_RAIL
+			ret_status = tegra_gpio_io_power_config(gpio_nr, true);
+			err = (NvError)ret_status;
+#endif
+			NvRmSetGpioTristate(hGpio->hRm,
+					 alphaPort, pin, NV_FALSE);
+		} else if ((s_hGpio->pPinInfo[gpio_nr].used)
+			   && (Mode == NvRmGpioPinMode_Inactive)) {
+#if NV_ENABLE_GPIO_POWER_RAIL
+			ret_status = tegra_gpio_io_power_config(gpio_nr, false);
+			err = (NvError)ret_status;
+#endif
+			NvRmSetGpioTristate(hGpio->hRm,
+				 	alphaPort, pin, NV_TRUE);
+		}
+		if (Mode != NvRmGpioPinMode_Inactive)
+			s_hGpio->pPinInfo[gpio_nr].used = NV_TRUE;
+		else
+			s_hGpio->pPinInfo[gpio_nr].used = NV_FALSE;
+	}
+
+	NvOsMutexUnlock(s_GpioMutex);
+	return err;
+}
+
+NvError NvRmGpioGetIrqs(NvRmDeviceHandle hRmDevice,
+			NvRmGpioPinHandle * hPin, NvU32 * Irq, NvU32 pinCount)
+{
+	NvU32 i;
+	int irq_base;
+	NvU32 bank;
+	NvU32 port;
+	NvU32 pin;
+	int gpio_nr;
+
+	irq_base = gpio_to_irq(0);
+	for (i = 0; i < pinCount; i++) {
+		bank = GET_BANK(hPin[i]);
+		port = GET_PORT(hPin[i]);
+		pin = GET_PIN(hPin[i]);
+		gpio_nr = GPIO_PIN_ID(bank, port, pin);
+		if (gpio_nr >= ARCH_NR_GPIOS) {
+			printk(KERN_ERR "Illegal pin handle at place "
+					" %u of the list\n",i);
+			continue;
+		}
+		Irq[i] = irq_base + gpio_nr;
+	}
+	return NvSuccess;
+}
diff --git a/arch/arm/mach-tegra/nvrm/io/ap15/nvrm_gpio_stub_helper.c b/arch/arm/mach-tegra/nvrm/io/ap15/nvrm_gpio_stub_helper.c
new file mode 100644
index 000000000000..c3ab43cb7842
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/io/ap15/nvrm_gpio_stub_helper.c
@@ -0,0 +1,197 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include "nvassert.h"
+#include "nvos.h"
+#include "nvrm_gpio.h"
+#include "nvrm_interrupt.h"
+#include "nvrm_moduleids.h"
+
+struct NvRmGpioInterruptRec 
+{
+    NvRmDeviceHandle hRm;
+    NvRmGpioHandle hGpio;
+    NvRmGpioPinHandle hPin;
+    NvRmGpioPinMode Mode;
+    NvOsInterruptHandler Callback;
+    void *arg;
+    NvU32 IrqNumber;
+    NvOsInterruptHandle NvOsIntHandle;
+    NvU32 DebounceTime;
+};
+
+static 
+void NvRmPrivGpioIsr(void *arg);
+
+NvError 
+NvRmGpioInterruptRegister(
+    NvRmGpioHandle hGpio,
+    NvRmDeviceHandle hRm,
+    NvRmGpioPinHandle hPin, 
+    NvOsInterruptHandler Callback,
+    NvRmGpioPinMode Mode,
+    void *CallbackArg,
+    NvRmGpioInterruptHandle *hGpioInterrupt,
+    NvU32 DebounceTime)
+{
+    /* Get all these from the handle and/or gpio caps API */
+    NvError err;
+    struct NvRmGpioInterruptRec *h = NULL;
+    NvOsInterruptHandler GpioIntHandler = NvRmPrivGpioIsr;
+
+    NV_ASSERT(Mode == NvRmGpioPinMode_InputInterruptLow || 
+                Mode == NvRmGpioPinMode_InputInterruptRisingEdge ||
+                Mode == NvRmGpioPinMode_InputInterruptFallingEdge || 
+                Mode == NvRmGpioPinMode_InputInterruptHigh || 
+                Mode == NvRmGpioPinMode_InputInterruptAny);
+
+    /* Allocate memory for the  NvRmGpioInterruptHandle */
+    h = (NvRmGpioInterruptHandle)NvOsAlloc(sizeof(struct NvRmGpioInterruptRec));
+    if (h == NULL) 
+    {
+        err = NvError_InsufficientMemory;
+        goto fail;
+    }
+
+    NvOsMemset(h, 0, sizeof(struct NvRmGpioInterruptRec));
+
+    h->hPin = hPin;
+    h->Mode = Mode;
+    h->Callback = Callback;
+    h->hRm = hRm;
+    h->hGpio = hGpio;
+    h->arg = CallbackArg;
+    h->DebounceTime = DebounceTime;
+
+    err = NvRmGpioConfigPins(hGpio, &hPin, 1, Mode);
+    if (err != NvSuccess)
+    {
+        goto fail;
+    }
+
+    if (!h->NvOsIntHandle)
+    {
+        NvRmGpioGetIrqs(hRm, &hPin, &(h->IrqNumber), 1);
+
+        err = NvRmInterruptRegister(hRm, 1, &h->IrqNumber, &GpioIntHandler, 
+                h, &h->NvOsIntHandle, NV_FALSE);
+
+        if (err != NvSuccess)
+        {
+            NvError e;
+            e = NvRmGpioConfigPins(hGpio, &hPin, 1, NvRmGpioPinMode_Inactive);
+            NV_ASSERT(!e);
+            (void)e;
+            goto fail;
+        }
+    }
+
+    NV_ASSERT(h->NvOsIntHandle);
+
+    *hGpioInterrupt = h;
+    return NvSuccess;
+
+fail:
+    NvOsFree(h);
+    *hGpioInterrupt = 0;
+    return err;
+}
+
+NvError
+NvRmGpioInterruptEnable(NvRmGpioInterruptHandle hGpioInterrupt)
+{
+    NV_ASSERT(hGpioInterrupt);
+
+    if (!hGpioInterrupt)
+    {
+        return NvError_BadParameter;
+    }
+
+    return NvRmInterruptEnable(hGpioInterrupt->hRm, hGpioInterrupt->NvOsIntHandle);
+}
+
+void
+NvRmGpioInterruptMask(NvRmGpioInterruptHandle hGpioInterrupt, NvBool mask)
+{
+    NvOsInterruptMask(hGpioInterrupt->NvOsIntHandle, mask);
+    return;
+}
+
+static 
+void NvRmPrivGpioIsr(void *arg)
+{
+    NvU32 i = 0;
+    NvRmGpioInterruptHandle info = (NvRmGpioInterruptHandle)arg;
+
+    if (info->DebounceTime)
+    {
+        NvOsSleepMS(info->DebounceTime);
+        for (i = 0; i < 100; i++)
+            ;
+    }
+    /* Call the clients callback function */
+    (*info->Callback)(info->arg);
+
+    return;
+}
+
+void 
+NvRmGpioInterruptUnregister(
+    NvRmGpioHandle hGpio,
+    NvRmDeviceHandle hRm,
+    NvRmGpioInterruptHandle handle)
+{
+    if (handle == NULL)
+        return;
+
+    NV_ASSERT(hGpio);
+    NV_ASSERT(hRm);
+
+    NV_ASSERT(NvRmGpioConfigPins(hGpio, &handle->hPin, 1, NvRmGpioPinMode_Inactive) 
+            == NvSuccess);
+    NvRmInterruptUnregister(hRm, handle->NvOsIntHandle);
+    handle->NvOsIntHandle = NULL;
+
+    NvOsFree(handle);
+    return;
+}
+
+void
+NvRmGpioInterruptDone( NvRmGpioInterruptHandle handle )
+{
+    if (!(handle->NvOsIntHandle)) 
+    {
+        NV_ASSERT(!"Make sure that interrupt source is enabled AFTER the interrupt is succesfully registered.");
+    }
+    NvRmInterruptDone(handle->NvOsIntHandle);
+}
+
diff --git a/arch/arm/mach-tegra/nvrm/io/ap15/rm_common_slink_hw_private.c b/arch/arm/mach-tegra/nvrm/io/ap15/rm_common_slink_hw_private.c
new file mode 100644
index 000000000000..3065c312323c
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/io/ap15/rm_common_slink_hw_private.c
@@ -0,0 +1,467 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/**
+ * @file
+ * @brief <b>nVIDIA driver Development Kit:
+ *           Private functions implementation for the slink Rm driver</b>
+ *
+ * @b Description:  Implements the private functions for the slink hw interface.
+ *
+ */
+
+// hardware includes
+#include "ap15/arslink.h"
+#include "rm_spi_slink_hw_private.h"
+#include "nvrm_drf.h"
+#include "nvrm_hardware_access.h"
+#include "nvassert.h"
+#include "nvos.h"
+
+#define SLINK_REG_READ32(pSlinkHwRegsVirtBaseAdd, reg) \
+        NV_READ32((pSlinkHwRegsVirtBaseAdd) + ((SLINK_##reg##_0)/4))
+#define SLINK_REG_WRITE32(pSlinkHwRegsVirtBaseAdd, reg, val) \
+    do { \
+        NV_WRITE32((((pSlinkHwRegsVirtBaseAdd) + ((SLINK_##reg##_0)/4))), (val)); \
+    } while(0)
+
+
+#define MAX_SLINK_FIFO_DEPTH 32
+
+#define ALL_SLINK_STATUS_CLEAR \
+        (NV_DRF_NUM(SLINK, STATUS,  RDY, 1) | \
+        NV_DRF_NUM(SLINK, STATUS,  RX_UNF, 1) | \
+        NV_DRF_NUM(SLINK, STATUS,  TX_UNF, 1) | \
+        NV_DRF_NUM(SLINK, STATUS,  TX_OVF, 1) | \
+        NV_DRF_NUM(SLINK, STATUS,  RX_OVF, 1))
+
+#define RX_ERROR_STATUS (NV_DRF_NUM(SLINK, STATUS, RX_UNF, 1) | \
+                            NV_DRF_NUM(SLINK, STATUS, RX_OVF, 1))
+#define TX_ERROR_STATUS (NV_DRF_NUM(SLINK, STATUS, TX_OVF, 1) | \
+                            NV_DRF_NUM(SLINK, STATUS, TX_UNF, 1))
+
+static void SlinkHwControllerInitialize(SerialHwRegisters *pSlinkHwRegs)
+{
+    SLINK_REG_WRITE32(pSlinkHwRegs->pRegsBaseAdd, COMMAND2, 
+                            pSlinkHwRegs->HwRegs.SlinkRegs.Command2);
+    SLINK_REG_WRITE32(pSlinkHwRegs->pRegsBaseAdd, COMMAND, 
+                            pSlinkHwRegs->HwRegs.SlinkRegs.Command1);
+}
+
+
+/**
+ * Set the functional mode whether this is the master or slave mode.
+ */
+static void
+SlinkHwSetFunctionalMode(
+    SerialHwRegisters *pSlinkHwRegs,
+    NvBool IsMasterMode)
+{
+    NvU32 CommandReg = pSlinkHwRegs->HwRegs.SlinkRegs.Command1;
+    if (IsMasterMode)
+        CommandReg = NV_FLD_SET_DRF_DEF(SLINK, COMMAND, M_S, MASTER, CommandReg);
+    else
+        CommandReg = NV_FLD_SET_DRF_DEF(SLINK, COMMAND, M_S, SLAVE, CommandReg);
+
+    pSlinkHwRegs->HwRegs.SlinkRegs.Command1 = CommandReg;
+    SLINK_REG_WRITE32(pSlinkHwRegs->pRegsBaseAdd, COMMAND, CommandReg);
+    pSlinkHwRegs->IsMasterMode = IsMasterMode;
+}
+
+/**
+ * Initialize the slink register.
+ */
+static void
+SlinkHwResetFifo(
+    SerialHwRegisters *pSlinkHwRegs, 
+    SerialHwFifo FifoType)
+{
+    NvU32 ResetBits = 0;
+    NvU32 StatusReg = SLINK_REG_READ32(pSlinkHwRegs->pRegsBaseAdd, STATUS);
+    if (FifoType & SerialHwFifo_Rx)
+        ResetBits = NV_DRF_NUM(SLINK, STATUS, RX_FLUSH, 1);
+    if (FifoType & SerialHwFifo_Tx)
+        ResetBits |= NV_DRF_NUM(SLINK, STATUS, TX_FLUSH, 1);
+
+    StatusReg |= ResetBits;
+    SLINK_REG_WRITE32(pSlinkHwRegs->pRegsBaseAdd, STATUS, StatusReg);
+
+    // Now wait till the flush bits become 0
+    do 
+    {
+        StatusReg = SLINK_REG_READ32(pSlinkHwRegs->pRegsBaseAdd, STATUS);
+    } while (StatusReg & ResetBits);
+}
+
+/**
+ * Findout whether transmit fio is full or not
+ */
+static NvBool SlinkHwIsTransmitFifoFull(SerialHwRegisters *pSpiHwRegs)
+{
+    NvU32 StatusReg = SLINK_REG_READ32(pSpiHwRegs->pRegsBaseAdd, STATUS);
+    if (StatusReg & NV_DRF_DEF(SLINK, STATUS, TX_FULL, FULL))
+        return NV_TRUE;
+    return NV_FALSE;    
+}
+
+    
+/**
+ * Set the transfer order whether the bit will start from the lsb or from
+ * msb.
+ */
+static void
+SlinkHwSetTransferBitOrder(
+    SerialHwRegisters *pSlinkHwRegs, 
+    NvBool IsLsbFirst)
+{
+    NvU32 Command2Reg = pSlinkHwRegs->HwRegs.SlinkRegs.Command2;
+    if (IsLsbFirst)
+        Command2Reg = NV_FLD_SET_DRF_DEF(SLINK, COMMAND2, LSBFE, LAST, Command2Reg);
+    else
+        Command2Reg = NV_FLD_SET_DRF_DEF(SLINK, COMMAND2, LSBFE, FIRST, Command2Reg);
+
+    pSlinkHwRegs->HwRegs.SlinkRegs.Command2 = Command2Reg;
+}
+
+/**
+ * Start the transfer of the communication.
+ */
+static void SlinkHwStartTransfer(SerialHwRegisters *pSlinkHwRegs, NvBool IsReconfigure)
+{
+    NvU32 DmaControlReg = pSlinkHwRegs->HwRegs.SlinkRegs.DmaControl;
+
+    // Program the packed mode
+    if (pSlinkHwRegs->IsPackedMode)
+    {
+        DmaControlReg = NV_FLD_SET_DRF_DEF(SLINK, DMA_CTL,  PACKED, ENABLE,
+            DmaControlReg);
+        SLINK_REG_WRITE32(pSlinkHwRegs->pRegsBaseAdd, DMA_CTL, DmaControlReg);
+
+        // Hw bug: Need to give some delay after setting the packed mode.
+        NvOsWaitUS(1);
+    }
+
+    // Enable the dma bit in the register variable only
+    DmaControlReg = NV_FLD_SET_DRF_DEF(SLINK, DMA_CTL, DMA_EN, ENABLE, DmaControlReg);
+
+    SLINK_REG_WRITE32(pSlinkHwRegs->pRegsBaseAdd, DMA_CTL, DmaControlReg);
+}
+
+/**
+ * Enable/disable the data transfer flow.
+ */
+static void 
+SlinkHwSetDataFlow(
+    SerialHwRegisters *pSlinkHwRegs, 
+    SerialHwDataFlow DataFlow, 
+    NvBool IsEnable)
+{
+    NvU32 CommandReg2 = pSlinkHwRegs->HwRegs.SlinkRegs.Command2;
+    if (DataFlow & SerialHwDataFlow_Rx)
+    {
+        if (IsEnable)
+            CommandReg2 = NV_FLD_SET_DRF_DEF(SLINK, COMMAND2,  RXEN, 
+                            ENABLE, CommandReg2);
+        else
+            CommandReg2 = NV_FLD_SET_DRF_DEF(SLINK, COMMAND2,  RXEN, 
+                            DISABLE, CommandReg2);
+    }
+
+    if (DataFlow & SerialHwDataFlow_Tx)
+    {
+        if (IsEnable)
+            CommandReg2 = NV_FLD_SET_DRF_DEF(SLINK, COMMAND2,  TXEN, 
+                            ENABLE, CommandReg2);
+        else
+            CommandReg2 = NV_FLD_SET_DRF_DEF(SLINK, COMMAND2,  TXEN, 
+                            DISABLE, CommandReg2);
+    }
+    pSlinkHwRegs->HwRegs.SlinkRegs.Command2 = CommandReg2; 
+    SLINK_REG_WRITE32(pSlinkHwRegs->pRegsBaseAdd, COMMAND2, 
+                            pSlinkHwRegs->HwRegs.SlinkRegs.Command2);
+}
+
+
+/**
+ * Set the packet length and packed mode.
+ */
+static void
+SlinkHwSetPacketLength(
+    SerialHwRegisters *pSlinkHwRegs, 
+    NvU32 PacketLength, 
+    NvBool IsPackedMode)
+{
+    NvU32 CommandReg1 = pSlinkHwRegs->HwRegs.SlinkRegs.Command1;
+    NvU32 DmaControlReg = pSlinkHwRegs->HwRegs.SlinkRegs.DmaControl;
+
+    CommandReg1 = NV_FLD_SET_DRF_NUM(SLINK, COMMAND,  BIT_LENGTH, 
+                                            (PacketLength -1), CommandReg1);
+                                            
+    // Unset the packed bit if it is there
+    DmaControlReg = NV_FLD_SET_DRF_DEF(SLINK, DMA_CTL, PACKED, DISABLE, DmaControlReg);
+    SLINK_REG_WRITE32(pSlinkHwRegs->pRegsBaseAdd, DMA_CTL, DmaControlReg);
+
+    if (IsPackedMode)
+    {
+        if (PacketLength == 4)
+            DmaControlReg = NV_FLD_SET_DRF_DEF(SLINK, DMA_CTL, PACK_SIZE, PACK4, 
+                            DmaControlReg);
+        else if (PacketLength == 8)
+            DmaControlReg = NV_FLD_SET_DRF_DEF(SLINK, DMA_CTL, PACK_SIZE, PACK8, 
+                            DmaControlReg);
+        else if (PacketLength == 16)
+            DmaControlReg = NV_FLD_SET_DRF_DEF(SLINK, DMA_CTL, PACK_SIZE, PACK16, 
+                            DmaControlReg);
+        else if (PacketLength == 32)
+            DmaControlReg = NV_FLD_SET_DRF_DEF(SLINK, DMA_CTL, PACK_SIZE, PACK32, 
+                            DmaControlReg);
+    }
+    else
+    {
+        DmaControlReg = NV_FLD_SET_DRF_DEF(SLINK, DMA_CTL, PACK_SIZE, PACK4, 
+                        DmaControlReg);
+    }
+
+    SLINK_REG_WRITE32(pSlinkHwRegs->pRegsBaseAdd, COMMAND, CommandReg1);
+    SLINK_REG_WRITE32(pSlinkHwRegs->pRegsBaseAdd, DMA_CTL, DmaControlReg);
+                    
+    pSlinkHwRegs->HwRegs.SlinkRegs.Command1 = CommandReg1;
+    pSlinkHwRegs->HwRegs.SlinkRegs.DmaControl = DmaControlReg;
+
+    pSlinkHwRegs->PacketLength = PacketLength;
+    pSlinkHwRegs->IsPackedMode = IsPackedMode;
+}
+
+/**
+ * Set the Dma transfer size.
+ */
+static void
+SlinkHwSetDmaTransferSize(
+    SerialHwRegisters *pSlinkHwRegs, 
+    NvU32 DmaBlockSize)
+{
+    pSlinkHwRegs->HwRegs.SlinkRegs.DmaControl = 
+            NV_FLD_SET_DRF_NUM(SLINK, DMA_CTL, DMA_BLOCK_SIZE, (DmaBlockSize-1), 
+                                pSlinkHwRegs->HwRegs.SlinkRegs.DmaControl);
+    SLINK_REG_WRITE32(pSlinkHwRegs->pRegsBaseAdd, DMA_CTL, 
+                                pSlinkHwRegs->HwRegs.SlinkRegs.DmaControl);
+}
+
+static NvU32 SlinkHwGetTransferdCount(SerialHwRegisters *pSlinkHwRegs)
+{
+    NvU32 DmaBlockSize;
+    NvU32 StatusReg = SLINK_REG_READ32(pSlinkHwRegs->pRegsBaseAdd, STATUS);
+    DmaBlockSize = NV_DRF_VAL(SLINK, STATUS, BLK_CNT, StatusReg); 
+    return (DmaBlockSize);
+}
+
+/**
+ * Set the trigger level.
+ */
+static void 
+SlinkHwSetTriggerLevel(
+    SerialHwRegisters *pSlinkHwRegs, 
+    SerialHwFifo FifoType,
+    NvU32 TriggerLevel)
+{
+    NvU32 DmaControlReg = pSlinkHwRegs->HwRegs.SlinkRegs.DmaControl;
+    switch(TriggerLevel)
+    {
+        case 4:
+            if (FifoType & SerialHwFifo_Rx)
+                DmaControlReg = NV_FLD_SET_DRF_DEF(SLINK, DMA_CTL, RX_TRIG, TRIG1, 
+                                                DmaControlReg);
+            if (FifoType & SerialHwFifo_Tx)
+                DmaControlReg = NV_FLD_SET_DRF_DEF(SLINK, DMA_CTL, TX_TRIG, TRIG1, 
+                                                DmaControlReg);
+            break;
+
+        case 16:
+            if (FifoType & SerialHwFifo_Rx)
+                DmaControlReg = NV_FLD_SET_DRF_DEF(SLINK, DMA_CTL, RX_TRIG, TRIG4, 
+                                                DmaControlReg);
+            if (FifoType & SerialHwFifo_Tx)
+                DmaControlReg = NV_FLD_SET_DRF_DEF(SLINK, DMA_CTL, TX_TRIG, TRIG4, 
+                                                DmaControlReg);
+            break;
+
+
+        case 32:
+            if (FifoType & SerialHwFifo_Rx)
+                DmaControlReg = NV_FLD_SET_DRF_DEF(SLINK, DMA_CTL, RX_TRIG, TRIG8, 
+                                                DmaControlReg);
+            if (FifoType & SerialHwFifo_Tx)
+                DmaControlReg = NV_FLD_SET_DRF_DEF(SLINK, DMA_CTL, TX_TRIG, TRIG8, 
+                                                DmaControlReg);
+            break;
+
+        case 64:
+            if (FifoType & SerialHwFifo_Rx)
+                DmaControlReg = NV_FLD_SET_DRF_DEF(SLINK, DMA_CTL, RX_TRIG, TRIG16, 
+                                                DmaControlReg);
+            if (FifoType & SerialHwFifo_Tx)
+                DmaControlReg = NV_FLD_SET_DRF_DEF(SLINK, DMA_CTL, TX_TRIG, TRIG16, 
+                                                DmaControlReg);
+            break;
+
+        default:
+            NV_ASSERT(!"Invalid Triggerlevel");
+    }
+    SLINK_REG_WRITE32(pSlinkHwRegs->pRegsBaseAdd, DMA_CTL, DmaControlReg);
+    pSlinkHwRegs->HwRegs.SlinkRegs.DmaControl = DmaControlReg;
+}
+
+/**
+ * Enable/disable the interrupt source. 
+ */
+static void
+SlinkHwSetInterruptSource(
+    SerialHwRegisters *pSlinkHwRegs, 
+    SerialHwDataFlow DataDirection,
+    NvBool IsEnable)
+{
+#if !NV_OAL
+    NvU32 DmaControlReg = pSlinkHwRegs->HwRegs.SlinkRegs.DmaControl;
+    if (DataDirection & SerialHwDataFlow_Rx)
+    {
+        if (IsEnable)
+        {
+            DmaControlReg = NV_FLD_SET_DRF_DEF(SLINK, DMA_CTL, IE_RXC,
+                ENABLE, DmaControlReg);
+        }
+        else
+        {
+            DmaControlReg = NV_FLD_SET_DRF_DEF(SLINK, DMA_CTL, IE_RXC,
+                DISABLE, DmaControlReg);
+        }
+    }
+    
+    if (DataDirection & SerialHwDataFlow_Tx)
+    {
+        if (IsEnable)
+        {
+            DmaControlReg = NV_FLD_SET_DRF_DEF(SLINK, DMA_CTL, IE_TXC,
+                ENABLE, DmaControlReg);
+        }
+        else
+        {
+            DmaControlReg = NV_FLD_SET_DRF_DEF(SLINK, DMA_CTL, IE_TXC,
+                DISABLE, DmaControlReg);
+        }
+    }
+
+    pSlinkHwRegs->HwRegs.SlinkRegs.DmaControl = DmaControlReg;
+    SLINK_REG_WRITE32(pSlinkHwRegs->pRegsBaseAdd, DMA_CTL, DmaControlReg);
+#endif
+}
+
+/**
+ * Get the transfer status. 
+ */
+static NvError SlinkHwGetTransferStatus(SerialHwRegisters *pSlinkHwRegs,
+            SerialHwDataFlow DataFlow)
+{
+    NvU32 StatusReg = SLINK_REG_READ32(pSlinkHwRegs->pRegsBaseAdd, STATUS);
+    pSlinkHwRegs->HwRegs.SlinkRegs.Status = StatusReg;
+    // Check for the receive error 
+    if (DataFlow & SerialHwDataFlow_Rx)
+    {
+        if (StatusReg & RX_ERROR_STATUS)
+             return NvError_SpiReceiveError;
+    }
+
+    // Check for the transmit error 
+    if (DataFlow & SerialHwDataFlow_Tx)
+    {
+        if (StatusReg & TX_ERROR_STATUS)
+            return NvError_SpiTransmitError;
+    }
+    return NvSuccess;
+}
+
+static void SlinkHwClearTransferStatus(SerialHwRegisters *pSlinkHwRegs,
+            SerialHwDataFlow DataFlow)
+{
+    NvU32 StatusReg = SLINK_REG_READ32(pSlinkHwRegs->pRegsBaseAdd, STATUS);
+
+    // Clear all the write 1 on clear status.
+    StatusReg &= (~ALL_SLINK_STATUS_CLEAR);
+
+    // Make ready clear to 1.
+    StatusReg = NV_FLD_SET_DRF_NUM(SLINK, STATUS, RDY, 1, StatusReg);
+    
+    // Check for the receive error 
+    if (DataFlow & SerialHwDataFlow_Rx)
+         StatusReg |= RX_ERROR_STATUS;
+
+    // Check for the transmit error 
+    if (DataFlow & SerialHwDataFlow_Tx)
+         StatusReg |= TX_ERROR_STATUS;
+
+    // Write on slink status register.     
+    SLINK_REG_WRITE32(pSlinkHwRegs->pRegsBaseAdd, STATUS, StatusReg);
+}
+
+/**
+ *  Check whether transfer is completed or not. 
+ */
+static NvBool SlinkHwIsTransferCompleted( SerialHwRegisters *pSlinkHwRegs)
+{
+    NvU32 StatusReg = SLINK_REG_READ32(pSlinkHwRegs->pRegsBaseAdd, STATUS);
+    if (StatusReg & NV_DRF_DEF(SLINK, STATUS, BSY, BUSY))
+        return NV_FALSE;
+
+    return NV_TRUE;        
+}
+
+/**
+ * Initialize the slink intterface for the hw access.
+ */
+void NvRmPrivSpiSlinkInitSlinkInterface(HwInterface *pSlinkInterface)
+{
+    pSlinkInterface->HwControllerInitializeFxn = SlinkHwControllerInitialize; 
+    pSlinkInterface->HwSetFunctionalModeFxn = SlinkHwSetFunctionalMode;
+    pSlinkInterface->HwResetFifoFxn = SlinkHwResetFifo;
+    pSlinkInterface->HwIsTransmitFifoFull = SlinkHwIsTransmitFifoFull;
+    pSlinkInterface->HwSetTransferBitOrderFxn = SlinkHwSetTransferBitOrder;
+    pSlinkInterface->HwStartTransferFxn = SlinkHwStartTransfer;
+    pSlinkInterface->HwSetDataFlowFxn = SlinkHwSetDataFlow;
+    pSlinkInterface->HwSetPacketLengthFxn = SlinkHwSetPacketLength;
+    pSlinkInterface->HwSetDmaTransferSizeFxn = SlinkHwSetDmaTransferSize;
+    pSlinkInterface->HwGetTransferdCountFxn = SlinkHwGetTransferdCount;
+    pSlinkInterface->HwSetTriggerLevelFxn = SlinkHwSetTriggerLevel;
+    pSlinkInterface->HwSetInterruptSourceFxn = SlinkHwSetInterruptSource;
+    pSlinkInterface->HwGetTransferStatusFxn = SlinkHwGetTransferStatus;
+    pSlinkInterface->HwClearTransferStatusFxn = SlinkHwClearTransferStatus;
+    pSlinkInterface->HwIsTransferCompletedFxn = SlinkHwIsTransferCompleted;
+}
+
diff --git a/arch/arm/mach-tegra/nvrm/io/ap15/rm_dma_hw_private.c b/arch/arm/mach-tegra/nvrm/io/ap15/rm_dma_hw_private.c
new file mode 100644
index 000000000000..9cf0eacd715e
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/io/ap15/rm_dma_hw_private.c
@@ -0,0 +1,566 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/** 
+ * @file
+ * @brief <b>nVIDIA Driver Development Kit: 
+ *           DMA Resource manager private API for Hw access </b>
+ *
+ * @b Description: Implements the private interface of the nvrm dma to access
+ * the hw apb dma register.
+ *
+ * This files implements the API for accessing the register of the Dma 
+ * controller and configure the dma transfers.
+ */
+
+#include "nvrm_dma.h"
+#include "nvrm_drf.h"
+#include "nvrm_hardware_access.h"
+#include "rm_dma_hw_private.h"
+#include "ap15/arapbdma.h"
+#include "ap15/arapbdmachan.h"
+#include "nvrm_drf.h"
+#include "nvassert.h"
+
+#define APBDMACHAN_READ32(pVirtBaseAdd, reg) \
+        NV_READ32((pVirtBaseAdd) + ((APBDMACHAN_CHANNEL_0_##reg##_0)/4))
+#define APBDMACHAN_WRITE32(pVirtBaseAdd, reg, val) \
+    do { \
+        NV_WRITE32(((pVirtBaseAdd) + ((APBDMACHAN_CHANNEL_0_##reg##_0)/4)), (val)); \
+    } while(0)
+
+
+/**
+ * Global Enable/disable the apb dma controller.
+ */
+static void GlobalSetApbDma(NvU32 *pGenVirtBaseAddress, NvBool IsEnable)
+{
+    NvU32 CommandRegs = 0;
+
+    // Read the apb dma command register.
+    CommandRegs = NV_READ32((pGenVirtBaseAddress + (APBDMA_COMMAND_0/4)));
+
+    // Enable/disable the global enable bit of this register.
+    if(IsEnable)
+        CommandRegs = NV_FLD_SET_DRF_DEF(APBDMA, COMMAND, GEN, ENABLE, CommandRegs);
+    else
+        CommandRegs = NV_FLD_SET_DRF_DEF(APBDMA, COMMAND, GEN, DISABLE, CommandRegs);
+
+    // Write into the register.
+    NV_WRITE32( (pGenVirtBaseAddress + ( APBDMA_COMMAND_0/4)),CommandRegs);
+}
+
+
+/**
+ * Configure the address registers of the apb dma for data transfer.
+ */
+static void
+ConfigureApbDmaAddress(
+    DmaChanRegisters *pDmaChRegs,
+    NvRmPhysAddr SourceAdd,
+    NvRmPhysAddr DestAdd,
+    NvBool IsSourceAddPeripheralType)
+{
+    pDmaChRegs->ApbAddressReg = (IsSourceAddPeripheralType)? SourceAdd: DestAdd;
+    pDmaChRegs->AhbAddressReg = (IsSourceAddPeripheralType)? DestAdd: SourceAdd;
+}
+
+
+/**
+ * Set the data transfer size for the apb dma.
+ */
+static void
+SetApbDmaTransferSize(
+    DmaChanRegisters *pDmaChRegs,
+    NvU32 TransferSize,
+    NvBool IsDoubleBuffMode)
+{
+    // If double buff mode the programmed word count will be half of the data 
+    // request.
+    NvU32 WordCount = (IsDoubleBuffMode)? (TransferSize >> 3): (TransferSize >> 2);
+
+    // Configure the word count in the control register.
+    pDmaChRegs->ControlReg = NV_FLD_SET_DRF_NUM(APBDMACHAN_CHANNEL_0, CSR, WCOUNT,
+                                        (WordCount-1), pDmaChRegs->ControlReg);
+}
+
+
+/**
+ * Add the transferred count for apb dma.
+ */
+static void AddApbDmaTransferredCount(DmaChanRegisters *pDmaChRegs)
+{
+    NvU32 ProgrammedWordCount;
+
+    // Get the programmed transfer count.
+    ProgrammedWordCount = NV_DRF_VAL(APBDMACHAN_CHANNEL_0, CSR, WCOUNT,
+                                            pDmaChRegs->ControlReg);
+    ProgrammedWordCount = (ProgrammedWordCount +1) << 2;
+    pDmaChRegs->TransferedCount += ProgrammedWordCount;
+
+    // Limiting the transfer count to not be more than 2 times
+    if (pDmaChRegs->TransferedCount > (ProgrammedWordCount << 1))
+        pDmaChRegs->TransferedCount = ProgrammedWordCount << 1;
+}
+
+static void AckNClearApbDmaInterrupt(DmaChanRegisters *pDmaChRegs)
+{
+    NvU32 DmaStatusReg;
+    // Get the status of the dma channel.
+    DmaStatusReg = APBDMACHAN_READ32(pDmaChRegs->pHwDmaChanReg, STA);
+
+    // Write 1 on clear
+    if (DmaStatusReg & NV_DRF_DEF(APBDMACHAN_CHANNEL_0, STA, ISE_EOC, INTR))
+        APBDMACHAN_WRITE32(pDmaChRegs->pHwDmaChanReg, STA, DmaStatusReg);
+}
+/**
+ * Check whether the dma transfer is completed or not for the given channel.
+ */
+static NvBool IsApbDmaTransferCompleted(DmaChanRegisters *pDmaChRegs)
+{
+    NvU32 DmaStatusReg;
+    
+    // Get the status of the dma channel.
+    DmaStatusReg = APBDMACHAN_READ32(pDmaChRegs->pHwDmaChanReg, STA);
+    if (DmaStatusReg & NV_DRF_DEF(APBDMACHAN_CHANNEL_0, STA, ISE_EOC, INTR))
+    {
+        // Write the status to clear it
+        APBDMACHAN_WRITE32(pDmaChRegs->pHwDmaChanReg, STA, DmaStatusReg);
+        return NV_TRUE;
+    }    
+    else
+        return NV_FALSE;
+}
+
+/**
+ * Get the transferred count for apb dma.
+ */
+static NvU32 GetApbDmaTransferredCount(DmaChanRegisters *pDmaChRegs)
+{
+    NvU32 DmaStatusReg;
+    NvU32 ProgrammedWordCount;
+    NvU32 RemainingWordCount;
+    NvU32 TransferedSize;
+    NvU32 RetTransferSize;
+
+    // Get the status of the dma channel.
+    DmaStatusReg = APBDMACHAN_READ32(pDmaChRegs->pHwDmaChanReg, STA);
+    ProgrammedWordCount = NV_DRF_VAL(APBDMACHAN_CHANNEL_0, CSR, WCOUNT,
+                                            pDmaChRegs->ControlReg);
+    RemainingWordCount = NV_DRF_VAL(APBDMACHAN_CHANNEL_0, STA, COUNT, DmaStatusReg);
+    if (IsApbDmaTransferCompleted(pDmaChRegs))
+        AddApbDmaTransferredCount(pDmaChRegs);
+        
+    if (DmaStatusReg & NV_DRF_DEF(APBDMACHAN_CHANNEL_0, STA, BSY, ACTIVE))
+    {
+        if (RemainingWordCount)
+            TransferedSize = (ProgrammedWordCount - RemainingWordCount);
+        else
+            TransferedSize = (ProgrammedWordCount);
+    }
+    else
+    {
+        TransferedSize = (ProgrammedWordCount +1 );
+    }
+    RetTransferSize = (TransferedSize << 2) + pDmaChRegs->TransferedCount;
+    pDmaChRegs->TransferedCount = 0;
+    return (RetTransferSize);
+}
+
+
+/**
+ * Get the transferred count for apb dma.
+ */
+static NvU32 GetApbDmaTransferredCountWithStop(
+    DmaChanRegisters *pDmaChRegs,
+    NvBool IsTransferStop)
+{
+    NvU32 DmaStatusReg;
+    NvU32 FlowCtrlReg;
+    NvU32 ProgrammedWordCount;
+    NvU32 RemainingWordCount;
+    NvU32 TransferedSize;
+    NvU32 RetTransferSize;
+
+    if (IsApbDmaTransferCompleted(pDmaChRegs))
+        AddApbDmaTransferredCount(pDmaChRegs);
+
+    if (IsTransferStop)
+    {
+        FlowCtrlReg = APBDMACHAN_READ32(pDmaChRegs->pHwDmaChanReg, CSR);
+        FlowCtrlReg = NV_FLD_SET_DRF_DEF(APBDMACHAN_CHANNEL_0, 
+                                    CSR, REQ_SEL, NA31,
+                                    FlowCtrlReg);
+        APBDMACHAN_WRITE32(pDmaChRegs->pHwDmaChanReg, CSR, FlowCtrlReg);
+    }
+
+    // Get the status of the dma channel.
+    DmaStatusReg = APBDMACHAN_READ32(pDmaChRegs->pHwDmaChanReg, STA);
+    ProgrammedWordCount = NV_DRF_VAL(APBDMACHAN_CHANNEL_0, CSR, WCOUNT,
+                                            pDmaChRegs->ControlReg);
+    RemainingWordCount = NV_DRF_VAL(APBDMACHAN_CHANNEL_0, STA, COUNT, DmaStatusReg);
+    if (DmaStatusReg & NV_DRF_DEF(APBDMACHAN_CHANNEL_0, STA, BSY, ACTIVE))
+    {
+        if (RemainingWordCount)
+            TransferedSize = (ProgrammedWordCount - RemainingWordCount);
+        else
+            TransferedSize = (ProgrammedWordCount);
+    }
+    else
+    {
+        TransferedSize = (ProgrammedWordCount+1);
+    }
+    RetTransferSize = (TransferedSize << 2) + pDmaChRegs->TransferedCount;
+    pDmaChRegs->TransferedCount = 0;
+    return (RetTransferSize);
+}
+
+/**
+ * Set the dma burst size in the dma registers.
+ */
+static void
+SetDmaBurstSize(
+    DmaChanRegisters *pDmaChRegs,
+    NvRmDmaModuleID DmaReqModuleId,
+    NvU32 TransferSize)
+{
+    // Check for the dma requestor Id and based on the requestor and module Id
+    // Select the burst size.
+    switch (DmaReqModuleId)
+    {
+        case NvRmDmaModuleID_Uart:
+        case NvRmDmaModuleID_I2c:
+        case NvRmDmaModuleID_Dvc:
+        
+            // Dma requestor is the uart/I2c/DvcI2c.
+            // Set the dma burst size to 1 words.
+            pDmaChRegs->AhbSequenceReg = NV_FLD_SET_DRF_DEF(APBDMACHAN_CHANNEL_0, 
+                                        AHB_SEQ, AHB_BURST, DMA_BURST_1WORDS,
+                                        pDmaChRegs->AhbSequenceReg);
+            break;
+
+        case NvRmDmaModuleID_I2s:
+        case NvRmDmaModuleID_Spdif:
+            // Dma requestor is the i2s.
+            pDmaChRegs->AhbSequenceReg = NV_FLD_SET_DRF_DEF(APBDMACHAN_CHANNEL_0, 
+                                        AHB_SEQ, AHB_BURST, DMA_BURST_4WORDS,
+                                        pDmaChRegs->AhbSequenceReg);
+            break;
+
+        case NvRmDmaModuleID_Slink:
+        case NvRmDmaModuleID_Spi:
+            // Dma requestor is the spi/slink.
+            if ((TransferSize & 0xF) == 0)
+            {
+                // Multiple of 4 words
+                pDmaChRegs->AhbSequenceReg = NV_FLD_SET_DRF_DEF(APBDMACHAN_CHANNEL_0, 
+                                        AHB_SEQ, AHB_BURST, DMA_BURST_4WORDS,
+                                        pDmaChRegs->AhbSequenceReg);
+            }
+            else
+            {
+                // Non multiple of 4 words
+                pDmaChRegs->AhbSequenceReg = NV_FLD_SET_DRF_DEF(APBDMACHAN_CHANNEL_0, 
+                                        AHB_SEQ, AHB_BURST, DMA_BURST_1WORDS,
+                                        pDmaChRegs->AhbSequenceReg);
+            }
+            break;
+
+        case NvRmDmaModuleID_Vfir:
+        case NvRmDmaModuleID_Mipi:
+            if ((TransferSize & 0x1F)) 
+            {
+                // Non multiple of 8 words
+                if (TransferSize & 0xF)
+                {
+                    // Non multiple of 4 words
+                    pDmaChRegs->AhbSequenceReg = NV_FLD_SET_DRF_DEF(
+                                        APBDMACHAN_CHANNEL_0, AHB_SEQ, AHB_BURST, 
+                                        DMA_BURST_1WORDS, pDmaChRegs->AhbSequenceReg);
+                }
+                else
+                {
+                    pDmaChRegs->AhbSequenceReg = NV_FLD_SET_DRF_DEF(
+                                        APBDMACHAN_CHANNEL_0, AHB_SEQ, AHB_BURST, 
+                                        DMA_BURST_4WORDS, pDmaChRegs->AhbSequenceReg);
+                }
+            }
+            else
+            {
+                pDmaChRegs->AhbSequenceReg = NV_FLD_SET_DRF_DEF(
+                                        APBDMACHAN_CHANNEL_0, AHB_SEQ, AHB_BURST, 
+                                        DMA_BURST_8WORDS, pDmaChRegs->AhbSequenceReg);
+            }
+            break;
+
+        default:
+            NV_ASSERT(!"Invalid module");
+    }
+}
+
+
+/**
+ * Enable the bit swap for the destionation address for apb dma.
+ */
+static void
+EnableApbDmaDestBitSwap(
+    DmaChanRegisters *pDmaChRegs,
+    NvBool IsDestAddPeripheralType)
+{
+    // Source to destination address.
+    if (IsDestAddPeripheralType)
+    {
+        // Enable the bit swap to the Peripheral address.
+        pDmaChRegs->ApbSequenceReg = NV_FLD_SET_DRF_DEF(APBDMACHAN_CHANNEL_0, 
+                                    APB_SEQ, APB_DATA_SWAP, ENABLE,
+                                    pDmaChRegs->ApbSequenceReg);
+    }
+    else
+    {
+        // Enable the bit swap to the memory address.
+        pDmaChRegs->AhbSequenceReg = NV_FLD_SET_DRF_NUM(APBDMACHAN_CHANNEL_0, 
+                                    AHB_SEQ, AHB_DATA_SWAP, 1,
+                                    pDmaChRegs->AhbSequenceReg);
+    }
+}
+
+/**
+ * Set the address wrapping information for apb dma.
+ * The different address wrapping is supported by APB dma.
+ */
+static void
+SetApbDmaAddressWrapping(
+    DmaChanRegisters *pDmaChRegs,
+    NvRmPhysAddr SourceAddWrap,
+    NvRmPhysAddr DestAddWrap,
+    NvU32 TransferSize,
+    NvBool IsSourceAddPeripheralType)
+{
+    NvU32 ApbWrapSizeInWords;
+    NvU32 AhbWrapSizeInWords;
+
+    // Supported address wrap on ahb side. These are in word (4 bytes) count.
+    NvU32 SupportedAhbSideAddWrapSize[8] = {0, 32, 64, 128, 256, 512,1024, 2048};
+
+    // Supported address wrap on apb side. These are in words (4 bytes) count.
+    NvU32 SupportedApbSideAddWrapSize[8] = {0, 1, 2, 4, 8, 16, 32, 64};
+
+    int MaxSupportedTable = 8;
+    int ApbWrapIndex = 0;
+    int AhbWrapIndex = 0;
+
+    // Converting the address wrapping size in words and storing in the
+    // variable as per source and destination module type.
+    ApbWrapSizeInWords = (IsSourceAddPeripheralType)? SourceAddWrap: DestAddWrap;
+    AhbWrapSizeInWords = (IsSourceAddPeripheralType)? DestAddWrap : SourceAddWrap;
+
+    ApbWrapSizeInWords = ApbWrapSizeInWords >> 2;
+    AhbWrapSizeInWords = AhbWrapSizeInWords >> 2;
+    
+    // Check for the supported address wrap for APB Side
+    for (ApbWrapIndex = 0; ApbWrapIndex < MaxSupportedTable; ++ApbWrapIndex)
+    {
+        if (ApbWrapSizeInWords == SupportedApbSideAddWrapSize[ApbWrapIndex])
+            break;
+    }
+    NV_ASSERT(ApbWrapIndex < MaxSupportedTable);
+
+    // Check for the supported address wrap for AHB Side
+    for (AhbWrapIndex = 0; AhbWrapIndex < MaxSupportedTable; ++AhbWrapIndex)
+    {
+        if (AhbWrapSizeInWords == SupportedAhbSideAddWrapSize[AhbWrapIndex])
+            break;
+    }
+    NV_ASSERT(AhbWrapIndex < MaxSupportedTable);
+
+    // Configure the registers.
+    pDmaChRegs->ApbSequenceReg = NV_FLD_SET_DRF_NUM(APBDMACHAN_CHANNEL_0,
+                                    APB_SEQ, APB_ADDR_WRAP, ApbWrapIndex, 
+                                    pDmaChRegs->ApbSequenceReg);
+
+    pDmaChRegs->AhbSequenceReg = NV_FLD_SET_DRF_NUM(APBDMACHAN_CHANNEL_0,
+                                    AHB_SEQ, WRAP, AhbWrapIndex, 
+                                    pDmaChRegs->AhbSequenceReg);
+}
+
+/**
+ * Start the apb dma transfer from the current request. This will read the
+ * dma register information  from the dma configuration register and program the
+ * dma register and start the transfer.
+ */
+static void StartApbDmaTransfer(DmaChanRegisters *pDmaChRegs)
+{
+    NvU32 DmaStartCommand;
+
+    pDmaChRegs->TransferedCount = 0;
+
+    // Write configured data into the hw register of dma.
+    APBDMACHAN_WRITE32(pDmaChRegs->pHwDmaChanReg, CSR, pDmaChRegs->ControlReg);
+    APBDMACHAN_WRITE32(pDmaChRegs->pHwDmaChanReg, AHB_SEQ, pDmaChRegs->AhbSequenceReg);
+    APBDMACHAN_WRITE32(pDmaChRegs->pHwDmaChanReg, AHB_PTR, pDmaChRegs->AhbAddressReg);
+    APBDMACHAN_WRITE32(pDmaChRegs->pHwDmaChanReg, APB_SEQ, pDmaChRegs->ApbSequenceReg);
+    APBDMACHAN_WRITE32(pDmaChRegs->pHwDmaChanReg, APB_PTR, pDmaChRegs->ApbAddressReg);
+
+    // Start the dma transfer.
+    DmaStartCommand = NV_FLD_SET_DRF_DEF(APBDMACHAN_CHANNEL_0, CSR, ENB, ENABLE,
+                                                pDmaChRegs->ControlReg);
+    APBDMACHAN_WRITE32(pDmaChRegs->pHwDmaChanReg, CSR, DmaStartCommand);
+}
+
+/**
+ * Continue the apb dma transfer special for the continuous mode.
+ */
+static void ContinueApbDmaTransfer(DmaChanRegisters *pDmaChRegs)
+{
+    NvU32 DmaStartCommand;
+    NvU32 CurrControlReg;
+    NvU32 NewControlReg;
+
+    NewControlReg = NV_FLD_SET_DRF_DEF(APBDMACHAN_CHANNEL_0, CSR, ENB, ENABLE, 
+                                        pDmaChRegs->ControlReg);
+    CurrControlReg = APBDMACHAN_READ32(pDmaChRegs->pHwDmaChanReg, CSR);
+
+    APBDMACHAN_WRITE32(pDmaChRegs->pHwDmaChanReg, AHB_PTR, pDmaChRegs->AhbAddressReg);
+
+    // Write the control register only when there is difference between the 
+    // current setting and new setting.
+    if (NewControlReg != CurrControlReg)
+    {
+        // Start the dma transfer.
+        DmaStartCommand = NV_FLD_SET_DRF_DEF(APBDMACHAN_CHANNEL_0, CSR, ENB, 
+                                ENABLE, pDmaChRegs->ControlReg);
+        APBDMACHAN_WRITE32(pDmaChRegs->pHwDmaChanReg, CSR, DmaStartCommand);
+    }
+}
+
+/**
+ * Start the Apb dma transfer from the current request. This will read the
+ * current configured address from the register and increment them as per
+ * passed parameter and start the dma transfer.
+ */
+static void
+StartApbDmaWithAddInc(
+    DmaChanRegisters *pDmaChRegs,
+    NvU32 PeriAddIncSize,
+    NvU32 MemoryAddIncSize,
+    NvU32 IsContMode)
+{
+    NvU32 NewControlReg;
+    NvU32 CurrControlReg;
+    NvU32 AhbAddress;
+
+    NewControlReg = NV_FLD_SET_DRF_DEF(APBDMACHAN_CHANNEL_0, CSR, ENB, ENABLE,
+                                    pDmaChRegs->ControlReg);
+
+    // Read the addresses programmed in the dma hw registers.
+    AhbAddress = APBDMACHAN_READ32(pDmaChRegs->pHwDmaChanReg, AHB_PTR);
+
+    // Increment the address and write back the new address.
+    APBDMACHAN_WRITE32(pDmaChRegs->pHwDmaChanReg, AHB_PTR, 
+                                            (AhbAddress + MemoryAddIncSize));
+
+    // If it is continuous mode and old control information is same as the new 
+    // one then need nt to rewrite the control resgiter.
+    if (IsContMode)
+    {
+        CurrControlReg = APBDMACHAN_READ32(pDmaChRegs->pHwDmaChanReg, CSR);
+        if (CurrControlReg == NewControlReg)
+            return;
+    }
+    // Start the dma transfer.
+    NewControlReg = NV_FLD_SET_DRF_DEF(APBDMACHAN_CHANNEL_0, CSR, ENB, ENABLE,
+                            NewControlReg);
+    APBDMACHAN_WRITE32(pDmaChRegs->pHwDmaChanReg, CSR, NewControlReg);
+}
+
+
+
+/**
+ * Stop the data transfer in the given APB/AHB dma channel number.
+ */
+static void StopApbDmaTransfer(DmaChanRegisters *pDmaChRegs)
+{
+    NvU32 DmaCommandReg;
+
+    // Stop the dma transfer.
+    // First disable the interrupt and then diasable the dma enable bit.
+    DmaCommandReg = APBDMACHAN_READ32(pDmaChRegs->pHwDmaChanReg, CSR);
+    DmaCommandReg = NV_FLD_SET_DRF_DEF(APBDMACHAN_CHANNEL_0, CSR, IE_EOC, DISABLE, 
+                            DmaCommandReg);
+    APBDMACHAN_WRITE32(pDmaChRegs->pHwDmaChanReg, CSR, DmaCommandReg);
+
+    DmaCommandReg = NV_FLD_SET_DRF_DEF(APBDMACHAN_CHANNEL_0, CSR, ENB, DISABLE, 
+                            DmaCommandReg);
+    APBDMACHAN_WRITE32(pDmaChRegs->pHwDmaChanReg, CSR, DmaCommandReg);
+    AckNClearApbDmaInterrupt(pDmaChRegs);
+}
+
+
+/**
+ * Tells whether the given address is valid peripheral device address or not.
+ */
+NvBool NvRmPrivDmaHwIsValidPeripheralAddress(NvRmPhysAddr PhysAddress)
+{
+    NvU32 Address32Bit;
+    NvU32 MostSignificantNibble;
+
+    // Get the most significant nibble
+    Address32Bit = (NvU32)PhysAddress;
+    MostSignificantNibble = Address32Bit >> 28;
+
+    // Only address start at 7XXX:XXXX address are the valid device address.
+    if (MostSignificantNibble == 7)
+        return NV_TRUE;
+    return NV_FALSE;    
+}
+
+void NvRmPrivDmaInitDmaHwInterfaces(DmaHwInterface *pApbDmaInterface)
+{
+    pApbDmaInterface->DmaHwGlobalSetFxn = GlobalSetApbDma;
+    pApbDmaInterface->DmaHwConfigureAddressFxn = ConfigureApbDmaAddress;
+    pApbDmaInterface->DmaHwSetTransferSizeFxn =  SetApbDmaTransferSize;
+    pApbDmaInterface->DmaHwGetTransferredCountFxn = GetApbDmaTransferredCount;
+    pApbDmaInterface->DmaHwGetTransferredCountWithStopFxn = GetApbDmaTransferredCountWithStop;
+    pApbDmaInterface->DmaHwAddTransferCountFxn = AddApbDmaTransferredCount;
+    pApbDmaInterface->DmaHwSetBurstSizeFxn =  SetDmaBurstSize;
+    pApbDmaInterface->DmaHwEnableDestBitSwapFxn = EnableApbDmaDestBitSwap;
+    pApbDmaInterface->DmaHwSetAddressWrappingFxn = SetApbDmaAddressWrapping;
+    pApbDmaInterface->DmaHwStartTransferFxn = StartApbDmaTransfer;
+    pApbDmaInterface->DmaHwContinueTransferFxn = ContinueApbDmaTransfer;
+    pApbDmaInterface->DmaHwStartTransferWithAddIncFxn = StartApbDmaWithAddInc;
+    pApbDmaInterface->DmaHwStopTransferFxn = StopApbDmaTransfer;
+    pApbDmaInterface->DmaHwIsTransferCompletedFxn = IsApbDmaTransferCompleted;
+    pApbDmaInterface->DmaHwAckNClearInterruptFxn = AckNClearApbDmaInterrupt;
+
+    NvRmPrivDmaInitAp15DmaHwInterfaces(pApbDmaInterface);
+}
+
diff --git a/arch/arm/mach-tegra/nvrm/io/ap15/rm_dma_hw_private.h b/arch/arm/mach-tegra/nvrm/io/ap15/rm_dma_hw_private.h
new file mode 100644
index 000000000000..aa7b4175d8e2
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/io/ap15/rm_dma_hw_private.h
@@ -0,0 +1,271 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/** 
+ * @file
+ * @brief <b>nVIDIA Driver Development Kit: 
+ *           Private functions for the dma resource manager</b>
+ *
+ * @b Description:  Defines the HW access of the apb dma register.
+ * 
+ */
+
+#ifndef INCLUDED_NVRM_DMA_HW_PRIVATE_H
+#define INCLUDED_NVRM_DMA_HW_PRIVATE_H
+
+/**
+ * @defgroup nvrm_dma Direct Memory Access (DMA) Hw controller interface API.
+ * 
+ * This is the Hw Dma controller interface.  These API provides the register 
+ * access of the dma controller register. This configures the hw related dma 
+ * information in the passed parameters.
+ *
+ * @ingroup nvddk_rm
+ * 
+ * @{
+ */
+
+#include "nvcommon.h"
+#include "nvrm_dma.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/**
+ * Combines the apb Dma regsiters physical base address, channel address, 
+ * bank size of the channel address and  general controller address.
+ */
+typedef struct 
+{   
+    NvU32 GenAddBankSize;
+    NvU32 *pGenVirtBaseAdd;
+} DmaGenRegisters;
+
+
+/**
+ * Combines the Dma register which contains the APB register sets.
+ */
+typedef struct
+{
+    // Virtual address Pointer to the dma channel base register. 
+    NvU32 *pHwDmaChanReg; 
+
+    NvU32 ControlReg;
+    NvU32 StatusReg;
+    NvU32 AhbAddressReg;
+    NvU32 ApbAddressReg;
+    NvU32 XmbAddressReg;
+    NvU32 AhbSequenceReg;
+    NvU32 XmbSequenceReg;
+    NvU32 ApbSequenceReg;
+
+    NvU32 TransferedCount;
+} DmaChanRegisters;
+
+
+typedef struct DmaHwInterfaceRec
+{
+    /**
+     * Configure the Apb dma register as per clients information.
+     * This function do the register setting based on device Id and will  be stored 
+     * in the dma handle. This information will be used when there is dma transfer 
+     * request and want to configure the dma controller registers. 
+     */
+    void
+    (*DmaHwInitRegistersFxn)(    
+        DmaChanRegisters *pDmaChRegs,
+        NvRmDmaModuleID DmaReqModuleId,
+        NvU32 DmaReqInstId);
+
+    /**
+     * Global Enable/disable the dma controller.
+     */
+    void (*DmaHwGlobalSetFxn)(NvU32 *pGenVirtBaseAddress, NvBool IsEnable);
+
+    /**
+     * Continue the remaining transfer.
+     */
+    void (*DmaContinueRemainingTransferFxn)(void *pDmaChannel);
+
+    NvError  (*LogDmaTransferRequestFxn)(NvRmDmaHandle hDma, void *pCurrRequest);
+
+    /**
+     * Configure the address registers of the dma from the client buffer
+     * source and destination address.
+     */
+    void
+    (*DmaHwConfigureAddressFxn)(    
+        DmaChanRegisters *pDmaChRegs,
+        NvRmPhysAddr SourceAdd,
+        NvRmPhysAddr DestAdd,
+        NvBool IsSourceAddPeripheralXmbType);
+
+    /**
+     * Set the data transfer size for the apb dma.
+     */
+    void
+    (*DmaHwSetTransferSizeFxn)(    
+        DmaChanRegisters *pDmaChRegs,
+        NvU32 TransferSize,
+        NvBool IsDoubleBuffMode);
+
+    /**
+     * Get the transferred count for apb dma.
+     */
+    NvU32 (*DmaHwGetTransferredCountFxn)(DmaChanRegisters *pDmaChRegs);
+
+    /**
+     * Get the transferred count for apb dma.
+     */
+    NvU32 (*DmaHwGetTransferredCountWithStopFxn)(
+        DmaChanRegisters *pDmaChRegs,
+        NvBool IsTransferStop);
+
+    /**
+     * Add the transfer count in the dma transferred size.
+     */
+    void (*DmaHwAddTransferCountFxn)(DmaChanRegisters *pDmaChRegs);
+
+    /**
+     * Set the transferred mode for apb dma.
+     */
+    void
+    (*DmaHwSetTransferModeFxn)(    
+        DmaChanRegisters *pDmaChRegs,
+        NvBool IsContinuousMode,
+        NvBool IsDoubleBuffMode);
+
+    /**
+     * Set the dma direction of data transfer.
+     */
+    void 
+    (*DmaHwSetDirectionFxn)(
+        DmaChanRegisters *pDmaChRegs, 
+        NvBool IsSourceAddPerXmbType);
+        
+    /**
+     * Set the dma burst size in the dma registers copy.
+     */
+    void
+    (*DmaHwSetBurstSizeFxn)(    
+        DmaChanRegisters *pDmaChRegs,
+        NvRmDmaModuleID DmaReqModuleId,
+        NvU32 TransferSize);
+
+    /**
+     * Enable the bit swap for the destionation address for apb dma.
+     */
+    void
+    (*DmaHwEnableDestBitSwapFxn)(    
+        DmaChanRegisters *pDmaChRegs,
+        NvBool IsDestAddPeripheralXmbType);
+
+    /**
+     * Set the address wrapping information for dma.
+     * The different address wrapping is supported by dma.
+     */
+    void
+    (*DmaHwSetAddressWrappingFxn)(
+        DmaChanRegisters *pDmaChRegs,
+        NvRmPhysAddr SourceAddWrap,
+        NvRmPhysAddr DestAddWrap,
+        NvU32 TransferSize,
+        NvBool IsSourceAddPeripheralXmbType);
+
+    /**
+     * Start the dma transfer from the current request. 
+     * This will start the dma transfer.
+     */
+    void (*DmaHwStartTransferFxn)(DmaChanRegisters *pDmaChRegs);
+
+    /**
+     * Continue the dma transfer special for the continuous mode. 
+     */
+    void (*DmaHwContinueTransferFxn)(DmaChanRegisters *pDmaChRegs);
+
+    /**
+     * Start the dma transfer from the current request. This will read the 
+     * current configured address from the register and increment them as per  
+     * passed parameter and start the dma transfer.
+     */
+    void 
+    (*DmaHwStartTransferWithAddIncFxn)(
+        DmaChanRegisters *pDmaChRegs,
+        NvU32 XmbPeriAddIncSize,
+        NvU32 MemoryAddIncSize,
+        NvU32 IsContMode);
+
+    /**
+     * Stop the data transfer in the given dma channel number.
+     */
+    void (*DmaHwStopTransferFxn)(DmaChanRegisters *pDmaChRegs);
+
+    /**
+     * Check whether the dma transfer is completed or not for the given channel.
+     */
+    NvBool (*DmaHwIsTransferCompletedFxn)(DmaChanRegisters *pDmaChRegs);
+
+    /**
+     * Ack and clear the interrupt of dma channel.
+     */
+    void (*DmaHwAckNClearInterruptFxn)(DmaChanRegisters *pDmaChRegs);
+} DmaHwInterface;
+
+
+
+/**
+ * Tells whether the given address is on Xmb or not.
+ */
+NvBool NvRmPrivDmaHwIsValidXmbAddress(NvRmPhysAddr PhysAddress);
+
+/**
+ * Tells whether the given address is valid peripheral device address or not.
+ */
+NvBool NvRmPrivDmaHwIsValidPeripheralAddress(NvRmPhysAddr PhysAddress) ;
+
+
+void NvRmPrivDmaInitAp15DmaHwInterfaces(DmaHwInterface *pApbDmaInterface);
+
+void NvRmPrivDmaInitDmaHwInterfaces(DmaHwInterface *pApbDmaInterface);
+
+NvU32 NvRmPrivDmaInterruptDecode(NvRmDeviceHandle hRmDevice );
+
+void NvRmPrivDmaInterruptEnable(NvRmDeviceHandle hRmDevice, NvU32 Channel, NvBool Enable );
+
+#if defined(__cplusplus)
+}
+#endif
+
+/** @} */
+
+#endif  // INCLUDED_NVRM_DMA_HW_PRIVATE_H
diff --git a/arch/arm/mach-tegra/nvrm/io/ap15/rm_spi_hw_private.c b/arch/arm/mach-tegra/nvrm/io/ap15/rm_spi_hw_private.c
new file mode 100644
index 000000000000..cb7293e1896a
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/io/ap15/rm_spi_hw_private.c
@@ -0,0 +1,635 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/** 
+ * @file
+ * @brief <b>nVIDIA Driver Development Kit: 
+ *           Private functions implementation for the spi Ddk driver</b>
+ *
+ * @b Description:  Implements the private functions for the spi hw interface.
+ * 
+ */
+ 
+#include "rm_spi_slink_hw_private.h"
+#include "nvrm_drf.h"
+#include "nvrm_hardware_access.h"
+#include "nvassert.h"
+
+// hardware includes
+#include "ap15/arspi.h"
+
+#define SPI_REG_READ32(pSpiHwRegsVirtBaseAdd, reg) \
+        NV_READ32((pSpiHwRegsVirtBaseAdd) + ((SPI_##reg##_0)/4))
+#define SPI_REG_WRITE32(pSpiHwRegsVirtBaseAdd, reg, val) \
+    do { \
+        NV_WRITE32((((pSpiHwRegsVirtBaseAdd) + ((SPI_##reg##_0)/4))), (val)); \
+    } while (0)
+
+#define MAX_SPI_FIFO_DEPTH 4
+
+#define RESET_ALL_CS \
+        (NV_DRF_DEF(SPI, COMMAND,  CS0_EN, ENABLE) | \
+         NV_DRF_DEF(SPI, COMMAND,  CS1_EN, ENABLE) | \
+         NV_DRF_DEF(SPI, COMMAND,  CS2_EN, ENABLE) | \
+         NV_DRF_DEF(SPI, COMMAND,  CS3_EN, ENABLE))
+
+#define ALL_SPI_STATUS_CLEAR \
+        (NV_DRF_NUM(SPI, STATUS,  RDY, 1) | \
+         NV_DRF_NUM(SPI, STATUS,  RXF_UNR, 1) | \
+         NV_DRF_NUM(SPI, STATUS,  TXF_OVF, 1))
+
+static void
+SpiHwSetSignalMode(
+    SerialHwRegisters *pSpiHwRegs, 
+    NvOdmQuerySpiSignalMode SignalMode);
+
+/**
+ * Initialize the spi register.
+ */
+static void
+SpiHwRegisterInitialize(
+    NvU32 SerialInstanceId, 
+    SerialHwRegisters *pSpiHwRegs)
+{
+    NvU32 CommandReg;
+    pSpiHwRegs->InstanceId = SerialInstanceId;
+    pSpiHwRegs->pRegsBaseAdd = NULL;
+    pSpiHwRegs->RegBankSize = 0;
+    pSpiHwRegs->HwTxFifoAdd = SPI_TX_FIFO_0;
+    pSpiHwRegs->HwRxFifoAdd = SPI_RX_FIFO_0;
+    pSpiHwRegs->IsPackedMode = NV_FALSE;
+    pSpiHwRegs->PacketLength = 1;
+    pSpiHwRegs->CurrSignalMode = NvOdmQuerySpiSignalMode_Invalid;
+    pSpiHwRegs->MaxWordTransfer = MAX_SPI_FIFO_DEPTH;
+    pSpiHwRegs->IsLsbFirst = NV_FALSE;
+    pSpiHwRegs->IsMasterMode = NV_TRUE;
+    pSpiHwRegs->IsNonWordAlignedPackModeSupported = NV_TRUE;
+    pSpiHwRegs->IsHwChipSelectSupported = NV_FALSE;
+
+    CommandReg = NV_RESETVAL(SPI, COMMAND);
+    // Initialize the chip select bits to select the s/w only
+    CommandReg = NV_FLD_SET_DRF_NUM(SPI, COMMAND,  CS_SOFT, 1, CommandReg);
+    CommandReg = NV_FLD_SET_DRF_NUM(SPI, COMMAND,  CS_VAL, 1, CommandReg);
+
+    if (pSpiHwRegs->IsIdleDataOutHigh)
+        CommandReg = NV_FLD_SET_DRF_DEF(SPI, COMMAND,  ACTIVE_SDA, DRIVE_HIGH, CommandReg);
+    else
+        CommandReg = NV_FLD_SET_DRF_DEF(SPI, COMMAND,  ACTIVE_SDA, DRIVE_LOW, CommandReg);
+    
+    pSpiHwRegs->HwRegs.SpiRegs.Command = CommandReg;
+    pSpiHwRegs->HwRegs.SpiRegs.Status = NV_RESETVAL(SPI, STATUS);
+    pSpiHwRegs->HwRegs.SpiRegs.DmaControl = NV_RESETVAL(SPI, DMA_CTL);
+}
+
+static void SpiHwControllerInitialize(SerialHwRegisters *pSpiHwRegs)
+{
+    SPI_REG_WRITE32(pSpiHwRegs->pRegsBaseAdd, COMMAND, 
+                pSpiHwRegs->HwRegs.SpiRegs.Command);
+}
+
+/**
+ * Set the functional mode whether this is the master or slave mode.
+ */
+static void
+SpiHwSetFunctionalMode(
+    SerialHwRegisters *pSpiHwRegs,
+    NvBool IsMasterMode)
+{
+    // Slave mode is not supported.
+    if (!IsMasterMode)
+            NV_ASSERT(!"Not Supported");
+}
+
+    
+/**
+ * Initialize the spi register.
+ */
+static void
+SpiHwResetFifo(
+    SerialHwRegisters *pSpiHwRegs, 
+    SerialHwFifo FifoType)
+{
+    NvU32 ResetBits = 0;
+
+    NvU32 StatusReg = SPI_REG_READ32(pSpiHwRegs->pRegsBaseAdd, STATUS);
+    if (FifoType & SerialHwFifo_Rx)
+        ResetBits = NV_DRF_NUM(SPI, STATUS, RXF_FLUSH, 1);
+    if (FifoType & SerialHwFifo_Tx)
+        ResetBits |= NV_DRF_NUM(SPI, STATUS, RXF_FLUSH, 1);
+
+    StatusReg |= ResetBits;
+    SPI_REG_WRITE32(pSpiHwRegs->pRegsBaseAdd, STATUS, StatusReg);
+
+    // Now wait till the flush bits become 0
+    StatusReg = SPI_REG_READ32(pSpiHwRegs->pRegsBaseAdd, STATUS);
+    while (StatusReg & ResetBits)
+    {
+        StatusReg = SPI_REG_READ32(pSpiHwRegs->pRegsBaseAdd, STATUS);
+    }
+}
+
+/**
+ * Findout whether transmit fio is full or not
+ */
+static NvBool SpiHwIsTransmitFifoFull(SerialHwRegisters *pSpiHwRegs)
+{
+    NvU32 StatusReg = SPI_REG_READ32(pSpiHwRegs->pRegsBaseAdd, STATUS);
+    if (StatusReg & NV_DRF_DEF(SPI, STATUS, TXF_FULL, FULL))
+        return NV_TRUE;
+    return NV_FALSE;    
+}
+
+
+/**
+ * Set the signal mode of communication whether this is the mode  0, 1, 2 or 3.
+ */
+static void
+SpiHwSetSignalMode(
+    SerialHwRegisters *pSpiHwRegs, 
+    NvOdmQuerySpiSignalMode SignalMode)
+{
+    NvU32 CommandReg;
+    CommandReg = pSpiHwRegs->HwRegs.SpiRegs.Command;
+    switch (SignalMode)
+    {
+        case NvOdmQuerySpiSignalMode_0:
+            CommandReg = NV_FLD_SET_DRF_DEF(SPI, COMMAND,  ACTIVE_SCLK,
+                                DRIVE_LOW, CommandReg);
+            CommandReg = NV_FLD_SET_DRF_NUM(SPI, COMMAND,  CK_SDA, 0,
+                                CommandReg);
+            break;
+
+        case NvOdmQuerySpiSignalMode_1:
+            CommandReg = NV_FLD_SET_DRF_DEF(SPI, COMMAND,  ACTIVE_SCLK,
+                                DRIVE_LOW, CommandReg);
+            CommandReg = NV_FLD_SET_DRF_NUM(SPI, COMMAND,  CK_SDA, 1,
+                                CommandReg);
+            break;
+
+        case NvOdmQuerySpiSignalMode_2:
+            CommandReg = NV_FLD_SET_DRF_DEF(SPI, COMMAND,  ACTIVE_SCLK,
+                                DRIVE_HIGH, CommandReg);
+            CommandReg = NV_FLD_SET_DRF_NUM(SPI, COMMAND,  CK_SDA, 0,
+                                CommandReg);
+            break;
+        case NvOdmQuerySpiSignalMode_3:
+            CommandReg = NV_FLD_SET_DRF_DEF(SPI, COMMAND,  ACTIVE_SCLK,
+                                DRIVE_HIGH, CommandReg);
+            CommandReg = NV_FLD_SET_DRF_NUM(SPI, COMMAND,  CK_SDA, 1,
+                                CommandReg);
+            break;
+        default:
+            NV_ASSERT(!"Invalid SignalMode");
+    }
+    pSpiHwRegs->HwRegs.SpiRegs.Command = CommandReg;
+    SPI_REG_WRITE32(pSpiHwRegs->pRegsBaseAdd, COMMAND, CommandReg);
+    pSpiHwRegs->CurrSignalMode = SignalMode;
+}
+
+/**
+ * Set the transfer order whether the bit will start from the lsb or from
+ * msb.
+ */
+static void
+SpiHwSetTransferBitOrder(
+    SerialHwRegisters *pSpiHwRegs, 
+    NvBool IsLsbFirst)
+{
+    // This feature is not supported on the spi controller.
+    if (IsLsbFirst)
+        NV_ASSERT(!"Not Supported");
+}
+
+/**
+ * Start the transfer of the communication.
+ */
+static void SpiHwStartTransfer(SerialHwRegisters *pSpiHwRegs, NvBool IsReconfigure)
+{
+    NvU32 DmaControlReg = pSpiHwRegs->HwRegs.SpiRegs.DmaControl;
+
+    // Enable the dma bit in the register variable only
+    DmaControlReg = NV_FLD_SET_DRF_DEF(SPI, DMA_CTL, DMA_EN, ENABLE, DmaControlReg);
+
+    // Now write the command and dma control values into the controller register
+    
+    // Need to write on the command register only if the reconfiguration is done.
+    // Other wise it is not required.
+    if (IsReconfigure)
+        SPI_REG_WRITE32(pSpiHwRegs->pRegsBaseAdd, COMMAND, 
+                    pSpiHwRegs->HwRegs.SpiRegs.Command);
+
+    SPI_REG_WRITE32(pSpiHwRegs->pRegsBaseAdd, DMA_CTL, DmaControlReg);
+}
+
+/**
+ * Enable/disable the data transfer flow.
+ */
+static void 
+SpiHwSetDataFlow(
+SerialHwRegisters *pSerialHwRegs, 
+    SerialHwDataFlow DataFlow, 
+    NvBool IsEnable)
+{
+    NvU32 CommandReg = pSerialHwRegs->HwRegs.SpiRegs.Command;
+    if (DataFlow & SerialHwDataFlow_Rx)
+    {
+        if (IsEnable)
+            CommandReg = NV_FLD_SET_DRF_DEF(SPI, COMMAND,  RXEN, 
+                            ENABLE, CommandReg);
+        else
+            CommandReg = NV_FLD_SET_DRF_DEF(SPI, COMMAND,  RXEN, 
+                            DISABLE, CommandReg);
+    }
+
+    if (DataFlow & SerialHwDataFlow_Tx)
+    {
+        if (IsEnable)
+            CommandReg = NV_FLD_SET_DRF_DEF(SPI, COMMAND,  TXEN, 
+                            ENABLE, CommandReg);
+        else
+            CommandReg = NV_FLD_SET_DRF_DEF(SPI, COMMAND,  TXEN, 
+                            DISABLE, CommandReg);
+    }
+    pSerialHwRegs->HwRegs.SpiRegs.Command = CommandReg; 
+    SPI_REG_WRITE32(pSerialHwRegs->pRegsBaseAdd, COMMAND, 
+                            pSerialHwRegs->HwRegs.SpiRegs.Command);
+}
+
+/**
+ * Set the chip select signal level to be default based on device during the
+ * initialization.
+ */
+static void
+SpiHwSetChipSelectDefaultLevelFxn(
+    SerialHwRegisters *pSpiHwRegs, 
+    NvU32 ChipSelectId,
+    NvBool IsHigh)
+{
+    // No control over the individual cs lines.
+}
+
+/**
+ * Set the chip select signal level.
+ */
+static void
+SpiHwSetChipSelectLevel(
+    SerialHwRegisters *pSpiHwRegs, 
+    NvU32 ChipSelectId,
+    NvBool IsHigh)
+{
+    NvU32 CommandReg = pSpiHwRegs->HwRegs.SpiRegs.Command;
+
+    // Clear all chipselect
+    CommandReg &= ~(RESET_ALL_CS);
+
+    // Set the chip select level.
+    if (IsHigh)
+        CommandReg = NV_FLD_SET_DRF_NUM(SPI, COMMAND,  CS_VAL, 0, CommandReg);
+    else
+        CommandReg = NV_FLD_SET_DRF_NUM(SPI, COMMAND,  CS_VAL, 1, CommandReg);
+
+    switch (ChipSelectId)
+    {
+        case 0:
+            CommandReg = NV_FLD_SET_DRF_DEF(SPI, COMMAND,  CS0_EN, ENABLE,
+                CommandReg);
+            break;
+        case 1:
+            CommandReg = NV_FLD_SET_DRF_DEF(SPI, COMMAND,  CS1_EN, ENABLE,
+                CommandReg);
+            break;
+        case 2:
+            CommandReg = NV_FLD_SET_DRF_DEF(SPI, COMMAND,  CS2_EN, ENABLE,
+                CommandReg);
+            break;
+        case 3:
+            CommandReg = NV_FLD_SET_DRF_DEF(SPI, COMMAND,  CS3_EN, ENABLE,
+                CommandReg);
+            break;
+        default:
+            NV_ASSERT(!"Invalid ChipSelectId");
+    }     
+    pSpiHwRegs->HwRegs.SpiRegs.Command = CommandReg;
+    SPI_REG_WRITE32(pSpiHwRegs->pRegsBaseAdd, COMMAND, CommandReg);
+}
+
+/**
+ * Set the chip select signal level based on the transfer size.
+ * it can use the hw based CS or SW based CS based on transfer size and
+ * cpu/apb dma based transfer.
+ * Return NV_TRUE if the SW based chipselection is used otherwise return
+ * NV_FALSE;
+ */
+static NvBool
+SpiHwSetChipSelectLevelBasedOnPacket(
+    SerialHwRegisters *pSpiHwRegs, 
+    NvU32 ChipSelectId,
+    NvBool IsHigh,
+    NvU32 PacketRequested,
+    NvU32 PacketPerWord,
+    NvBool IsApbDmaBasedTransfer,
+    NvBool IsOnlyUseSWCS)
+{
+    SpiHwSetChipSelectLevel(pSpiHwRegs, ChipSelectId, IsHigh);
+    return NV_TRUE;
+}
+
+/**
+ * Set the packet length and packed mode.
+ */
+static void
+SpiHwSetPacketLength(
+    SerialHwRegisters *pSpiHwRegs, 
+    NvU32 PacketLength, 
+    NvBool IsPackedMode)
+{
+    NvU32 CommandReg = pSpiHwRegs->HwRegs.SpiRegs.Command;
+    NvU32 DmaControlReg = pSpiHwRegs->HwRegs.SpiRegs.DmaControl;
+
+    CommandReg = NV_FLD_SET_DRF_NUM(SPI, COMMAND,  BIT_LENGTH, 
+                    (PacketLength -1), CommandReg);
+    if (IsPackedMode)
+        DmaControlReg = NV_FLD_SET_DRF_DEF(SPI, DMA_CTL,  PACKED, ENABLE,
+            DmaControlReg);
+    else
+        DmaControlReg = NV_FLD_SET_DRF_DEF(SPI, DMA_CTL,  PACKED, DISABLE,
+            DmaControlReg);
+
+    SPI_REG_WRITE32(pSpiHwRegs->pRegsBaseAdd, COMMAND, CommandReg);
+    SPI_REG_WRITE32(pSpiHwRegs->pRegsBaseAdd, DMA_CTL, DmaControlReg);
+            
+    pSpiHwRegs->HwRegs.SpiRegs.Command = CommandReg;
+    pSpiHwRegs->HwRegs.SpiRegs.DmaControl = DmaControlReg;
+    pSpiHwRegs->PacketLength = PacketLength;
+    pSpiHwRegs->IsPackedMode = IsPackedMode;
+}
+
+/**
+ * Set the Dma transfer size.
+ */
+static void
+SpiHwSetDmaTransferSize(
+    SerialHwRegisters *pSpiHwRegs, 
+    NvU32 DmaBlockSize)
+{
+    pSpiHwRegs->HwRegs.SpiRegs.DmaControl = 
+            NV_FLD_SET_DRF_NUM(SPI, DMA_CTL, DMA_BLOCK_SIZE, (DmaBlockSize-1), 
+                    pSpiHwRegs->HwRegs.SpiRegs.DmaControl);
+    SPI_REG_WRITE32(pSpiHwRegs->pRegsBaseAdd, DMA_CTL, pSpiHwRegs->HwRegs.SpiRegs.DmaControl);
+}
+
+static NvU32 SpiHwGetTransferdCount(SerialHwRegisters *pSpiHwRegs)
+{
+    NvU32 DmaBlockSize;
+    NvU32 DmaControlReg = pSpiHwRegs->HwRegs.SpiRegs.DmaControl;
+    DmaBlockSize = NV_DRF_VAL(SPI, DMA_CTL, DMA_BLOCK_SIZE, DmaControlReg); 
+    return (DmaBlockSize +1);
+}
+
+/**
+ * Set the trigger level.
+ */
+static void 
+SpiHwSetTriggerLevel(
+    SerialHwRegisters *pSpiHwRegs, 
+    SerialHwFifo FifoType,
+    NvU32 TriggerLevel)
+{
+    NvU32 DmaControlReg = pSpiHwRegs->HwRegs.SpiRegs.DmaControl;
+    switch(TriggerLevel)
+    {
+        case 4:
+            if (FifoType & SerialHwFifo_Rx)
+                DmaControlReg = NV_FLD_SET_DRF_DEF(SPI, DMA_CTL, RX_TRIG, TRIG1, 
+                                                DmaControlReg);
+            if (FifoType & SerialHwFifo_Tx)
+                DmaControlReg = NV_FLD_SET_DRF_DEF(SPI, DMA_CTL, TX_TRIG, TRIG1, 
+                                                DmaControlReg);
+            break;
+
+        case 16:
+            if (FifoType & SerialHwFifo_Rx)
+                DmaControlReg = NV_FLD_SET_DRF_DEF(SPI, DMA_CTL, RX_TRIG, TRIG4, 
+                                                DmaControlReg);
+            if (FifoType & SerialHwFifo_Tx)
+                DmaControlReg = NV_FLD_SET_DRF_DEF(SPI, DMA_CTL, TX_TRIG, TRIG4, 
+                                                DmaControlReg);
+            break;
+        default:
+            NV_ASSERT(!"Invalid Triggerlevel");
+    }
+    pSpiHwRegs->HwRegs.SpiRegs.DmaControl = DmaControlReg;
+    SPI_REG_WRITE32(pSpiHwRegs->pRegsBaseAdd, DMA_CTL, DmaControlReg);
+}
+
+/**
+ * Write into the transmit fifo register.
+ * returns the number of words written.
+ */
+static NvU32
+SpiHwWriteInTransmitFifo(
+    SerialHwRegisters *pSpiHwRegs, 
+    NvU32 *pTxBuff,  
+    NvU32 WordRequested)
+{
+    NvU32 WordWritten = 0;
+    NvU32 WordsRemaining = NV_MIN(WordRequested, MAX_SPI_FIFO_DEPTH);
+    while (WordsRemaining)
+    {
+        SPI_REG_WRITE32(pSpiHwRegs->pRegsBaseAdd, TX_FIFO, *pTxBuff);
+        pTxBuff++;
+        WordsRemaining--;
+        WordWritten++;
+    }
+    return WordWritten;
+}
+
+/**
+ * Read the data from the receive fifo.
+ * Returns the number of words it read.   
+ */
+static NvU32
+SpiHwReadFromReceiveFifo(
+    SerialHwRegisters *pSpiHwRegs, 
+    NvU32 *pRxBuff,  
+    NvU32 WordRequested)
+{
+    NvU32 WordsRemaining = WordRequested;
+    while (WordsRemaining)
+    {
+        *pRxBuff = SPI_REG_READ32(pSpiHwRegs->pRegsBaseAdd, RX_FIFO);
+        pRxBuff++;
+        WordsRemaining--;
+    }
+    return WordRequested;
+}
+
+/**
+ * Enable/disable the interrupt source. 
+ */
+static void
+SpiHwSetInterruptSource(
+    SerialHwRegisters *pSpiHwRegs, 
+    SerialHwDataFlow DataDirection,
+    NvBool IsEnable)
+{
+    NvU32 DmaControlReg = pSpiHwRegs->HwRegs.SpiRegs.DmaControl;
+    if (DataDirection & SerialHwDataFlow_Rx)
+    {
+        if (IsEnable)
+        {
+            DmaControlReg = NV_FLD_SET_DRF_DEF(SPI, DMA_CTL, IE_RXC,
+                ENABLE, DmaControlReg);
+        }
+        else
+        {
+            DmaControlReg = NV_FLD_SET_DRF_DEF(SPI, DMA_CTL, IE_RXC,
+                DISABLE, DmaControlReg);
+        }
+    }
+    
+    if (DataDirection & SerialHwDataFlow_Tx)
+    {
+        if (IsEnable)
+        {
+            DmaControlReg = NV_FLD_SET_DRF_DEF(SPI, DMA_CTL, IE_TXC,
+                ENABLE, DmaControlReg);
+        }
+        else
+        {
+            DmaControlReg = NV_FLD_SET_DRF_DEF(SPI, DMA_CTL, IE_TXC,
+                DISABLE, DmaControlReg);
+        }
+    }
+
+    pSpiHwRegs->HwRegs.SpiRegs.DmaControl = DmaControlReg;
+}
+
+/**
+ * Get the transfer status. 
+ */
+static NvError SpiHwGetTransferStatus(SerialHwRegisters *pSpiHwRegs,
+            SerialHwDataFlow DataFlow)
+{
+    NvU32 StatusReg = SPI_REG_READ32(pSpiHwRegs->pRegsBaseAdd, STATUS);
+    
+    pSpiHwRegs->HwRegs.SlinkRegs.Status = StatusReg;
+    // Check for the receive error 
+    if (DataFlow & SerialHwDataFlow_Rx)
+    {
+        if (StatusReg & NV_DRF_NUM(SPI, STATUS, RXF_UNR, 1))
+             return NvError_SpiReceiveError;
+    }
+
+    // Check for the transmit error 
+    if (DataFlow & SerialHwDataFlow_Tx)
+    {
+        if (StatusReg & NV_DRF_NUM(SPI, STATUS, TXF_OVF, 1))
+            return NvError_SpiTransmitError;
+    }
+    return NvSuccess;
+}
+
+static void SpiHwClearTransferStatus(SerialHwRegisters *pSpiHwRegs,
+            SerialHwDataFlow DataFlow)
+{
+    NvU32 StatusReg = pSpiHwRegs->HwRegs.SpiRegs.Status ;
+
+    // Clear all the write 1 on clear status.
+    StatusReg &= (~ALL_SPI_STATUS_CLEAR);
+
+    // Make ready clear to 1.
+    StatusReg = NV_FLD_SET_DRF_NUM(SPI, STATUS, RDY, 1, StatusReg);
+    
+    // Check for the receive error 
+    if (DataFlow & SerialHwDataFlow_Rx)
+         StatusReg |= NV_DRF_NUM(SPI, STATUS, RXF_UNR, 1);
+
+    // Check for the transmit error 
+    if (DataFlow & SerialHwDataFlow_Tx)
+         StatusReg |= NV_DRF_NUM(SPI, STATUS, TXF_OVF, 1);
+
+    // Write on slink status register.     
+    SPI_REG_WRITE32(pSpiHwRegs->pRegsBaseAdd, STATUS, StatusReg);
+}
+
+/**
+ * Check whether transfer is completed or not. 
+ */
+static NvBool SpiHwIsTransferCompleted(SerialHwRegisters *pSpiHwRegs)
+{
+    // Read the Status register 
+    NvU32 StatusReg = SPI_REG_READ32(pSpiHwRegs->pRegsBaseAdd, STATUS);
+
+    if (StatusReg & NV_DRF_DEF(SPI, STATUS, BSY, BUSY))
+        return NV_FALSE;
+
+    // Transfer is completed so clear the ready bit by write 1 to clear
+    // Clear all the write 1 on clear status.
+    StatusReg &= (~ALL_SPI_STATUS_CLEAR);
+
+    // Make ready clear to 1.
+    StatusReg = NV_FLD_SET_DRF_NUM(SPI, STATUS, RDY, 1, StatusReg);    
+
+    SPI_REG_WRITE32(pSpiHwRegs->pRegsBaseAdd, STATUS, StatusReg);
+
+    return NV_TRUE;
+}
+
+/**
+ * Initialize the spi intterface for the hw access.
+ */
+void NvRmPrivSpiSlinkInitSpiInterface(HwInterface *pSpiInterface)
+{
+    pSpiInterface->HwRegisterInitializeFxn = SpiHwRegisterInitialize;
+    pSpiInterface->HwControllerInitializeFxn = SpiHwControllerInitialize; 
+    pSpiInterface->HwSetFunctionalModeFxn = SpiHwSetFunctionalMode;
+    pSpiInterface->HwResetFifoFxn = SpiHwResetFifo;
+    pSpiInterface->HwIsTransmitFifoFull = SpiHwIsTransmitFifoFull;
+    pSpiInterface->HwSetSignalModeFxn = SpiHwSetSignalMode;
+    pSpiInterface->HwSetTransferBitOrderFxn = SpiHwSetTransferBitOrder;
+    pSpiInterface->HwStartTransferFxn = SpiHwStartTransfer;
+    pSpiInterface->HwSetDataFlowFxn = SpiHwSetDataFlow;
+    pSpiInterface->HwSetChipSelectDefaultLevelFxn = SpiHwSetChipSelectDefaultLevelFxn;
+    pSpiInterface->HwSetChipSelectLevelFxn = SpiHwSetChipSelectLevel;
+    pSpiInterface->HwSetChipSelectLevelBasedOnPacketFxn = SpiHwSetChipSelectLevelBasedOnPacket;
+    pSpiInterface->HwSetPacketLengthFxn = SpiHwSetPacketLength;
+    pSpiInterface->HwSetDmaTransferSizeFxn = SpiHwSetDmaTransferSize;
+    pSpiInterface->HwGetTransferdCountFxn = SpiHwGetTransferdCount;
+    pSpiInterface->HwSetTriggerLevelFxn = SpiHwSetTriggerLevel;
+    pSpiInterface->HwWriteInTransmitFifoFxn = SpiHwWriteInTransmitFifo;
+    pSpiInterface->HwReadFromReceiveFifoFxn =  SpiHwReadFromReceiveFifo;
+    pSpiInterface->HwSetInterruptSourceFxn = SpiHwSetInterruptSource;
+    pSpiInterface->HwClearTransferStatusFxn = SpiHwClearTransferStatus;
+    pSpiInterface->HwGetTransferStatusFxn = SpiHwGetTransferStatus;
+    pSpiInterface->HwIsTransferCompletedFxn = SpiHwIsTransferCompleted;
+}
diff --git a/arch/arm/mach-tegra/nvrm/io/ap15/rm_spi_slink.c b/arch/arm/mach-tegra/nvrm/io/ap15/rm_spi_slink.c
new file mode 100644
index 000000000000..26fd65121355
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/io/ap15/rm_spi_slink.c
@@ -0,0 +1,2962 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/**
+ * @file
+ * @brief <b>NVIDIA Driver Development Kit:
+ *                  Spi Driver implementation</b>
+ *
+ * @b Description: Implementation of the NvRm SPI API of the OAL and non-OAL
+ *                 version.
+ *
+ */
+
+#include "nvrm_spi.h"
+#include "nvrm_power.h"
+#include "nvrm_interrupt.h"
+#include "nvrm_memmgr.h"
+#include "nvrm_dma.h"
+#include "nvodm_query.h"
+#include "nvodm_query_discovery.h"
+#include "rm_spi_slink_hw_private.h"
+#include "nvrm_hardware_access.h"
+#include "nvassert.h"
+#include "nvodm_query_pinmux.h"
+#include "nvrm_pinmux.h"
+#include "nvrm_pinmux_utils.h"
+#include "nvodm_modules.h"
+#include "rm_spi_slink.h"
+#include "nvrm_priv_ap_general.h"
+#include "ap15/ap15rm_private.h"
+
+
+// Combined maximum spi/slink controllers
+#define MAX_SPI_SLINK_INSTANCE (MAX_SLINK_CONTROLLERS + MAX_SPI_CONTROLLERS)
+
+// Constants used to size arrays for the maximum chipselect available for the
+// per spi/slink channel.
+#define MAX_CHIPSELECT_PER_INSTANCE 4
+
+// The maximum slave size request in words. Maximum 64KB/64K packet
+#define MAXIMUM_SLAVE_TRANSFER_WORD (1 << (16-2))
+
+// Maximum number which  is return by the NvOsGetTimeMS().
+// For NV_OAL, NvOsGetTimeMS() returns the MicroSecond Timer count divided by 1000.
+// and microsecond timer have the maximum count of 0xFFFFFFFF.
+// For Non-NV_OAL, it returned maximum of 0xFFFFFFFF
+#if NV_OAL
+#define MAX_TIME_IN_MS (0xFFFFFFFF/1000)
+#else
+#define MAX_TIME_IN_MS 0xFFFFFFFF
+#endif
+
+// The maximum request size for one transaction using the dma
+enum {DEFAULT_DMA_BUFFER_SIZE = (0x4000)}; // 16KB
+
+// Maximum buffer size when transferring the data using the cpu.
+enum {MAX_CPU_TRANSACTION_SIZE_WORD  = 0x80};  // 256 bytes
+
+// Maximum non dma transfer count for apb dma got hold from allocation
+enum {MAX_DMA_HOLD_TIME = 16};  // Maximum 16 non dma transaction
+
+
+// The maximum number of word on which it can select the polling method when
+// cpu based transaction is selected.
+enum {SLINK_POLLING_HIGH_THRESOLD = 64};
+
+// The dma buffer alignment requirement.
+enum {DMA_BUFFER_ALIGNMENT = 0x10};
+
+// Combined the Details of the current transfer information.
+typedef struct
+{
+    NvU32 *pTxBuff;
+    NvU32 *pRxBuff;
+
+    NvU32 BytesPerPacket;
+    NvU32 PacketBitLength;
+    NvBool IsPackedMode;
+
+    NvU32 PacketsPerWord;
+    NvU32 PacketRequested;
+    NvU32 PacketTransferred;
+    NvU32 TotalPacketsRemaining;
+
+    NvU32 RxPacketsRemaining;
+    NvU32 TxPacketsRemaining;
+
+    NvU32 CurrPacketCount;
+} TransferBufferInfo;
+
+/**
+ * Combines the spi/slink channel information.
+ */
+typedef struct NvRmSpiRec
+{
+    // Nv Rm device handles.
+    NvRmDeviceHandle hDevice;
+
+    // Instance Id
+    NvU32 InstanceId;
+
+    // Is opened in master mode or slave mode.
+    NvBool IsMasterMode;
+
+    // Rm module Id for the reference.
+    NvRmModuleID RmModuleId;
+
+    // Rm IO module Id for the reference.
+    NvOdmIoModule RmIoModuleId;
+
+    // Tells whether this is the spi channel or not.
+    NvBool IsSpiChannel;
+
+    // The channel open count.
+    NvU32 OpenCount;
+
+    // Spi hw register information.
+    SerialHwRegisters HwRegs;
+
+    // Current chipselect id on which data transfer is going on.
+    NvU32 CurrTransferChipSelId;
+
+    // Synchronous sempahore Id which need to be signalled on transfer
+    // completion.
+    NvOsSemaphoreHandle hSynchSema;
+
+    // Mutex to access this channel to provide the mutual exclusion.
+    NvOsMutexHandle hChannelAccessMutex;
+
+    // Tells whether the dma mode is supported or not.
+    NvBool IsApbDmaAllocated;
+
+    NvU32 TransCountFromLastDmaUsage;
+
+    // Read dma handle.
+    NvRmDmaHandle hRmRxDma;
+
+    // Write dma handle.
+    NvRmDmaHandle hRmTxDma;
+
+    // Memory handle to create the uncached memory.
+    NvRmMemHandle hRmMemory;
+
+    // Rx Dma buffer physical address.
+    NvRmPhysAddr DmaRxBuffPhysAdd;
+
+    // Tx Dma buffer physical address.
+    NvRmPhysAddr DmaTxBuffPhysAdd;
+
+    // Virtual pointer to the Rx dma buffer.
+    NvU32 *pRxDmaBuffer;
+
+    // Virtual pointer to the Tx dma buffer.
+    NvU32 *pTxDmaBuffer;
+
+    // Current Dma transfer size for the Rx and tx
+    NvU32 DmaBufferSize;
+
+    // Dma request for Tx
+    NvRmDmaClientBuffer TxDmaReq;
+
+    // Dma request for rx
+    NvRmDmaClientBuffer RxDmaReq;
+
+    // Tell whether it is using the apb dma for the transfer or not.
+    NvBool IsUsingApbDma;
+
+    // Buffer which will be used when cpu does the data receving.
+    NvU32 *pRxCpuBuffer;
+
+    // Buffer which will be used when cpu does the data transmitting.
+    NvU32 *pTxCpuBuffer;
+
+    NvU32 CpuBufferSizeInWords;
+
+    // Details of the current transfer information.
+    TransferBufferInfo CurrTransInfo;
+
+    // The data transfer dirction.
+    SerialHwDataFlow CurrentDirection;
+
+    // The transfer status for the receive and transmit
+    NvError RxTransferStatus;
+    NvError TxTransferStatus;
+
+    // Currently configured clock frequency
+    NvU32 ClockFreqInKHz;
+
+    NvOdmQuerySpiDeviceInfo DeviceInfo[MAX_CHIPSELECT_PER_INSTANCE];
+
+    NvBool IsCurrentChipSelStateHigh[MAX_CHIPSELECT_PER_INSTANCE];
+
+    NvBool IsChipSelSupported[MAX_CHIPSELECT_PER_INSTANCE];
+
+    NvBool IsChipSelConfigured;
+
+    NvBool IsCurrentlySwBasedChipSel;
+    
+    HwInterfaceHandle hHwInterface;
+
+    NvU32 RmPowerClientId;
+
+    NvOsInterruptHandle SpiInterruptHandle;
+
+    // Configured pin mux
+    NvU32 SpiPinMap;
+
+    // Idle signal state for the spi channel.
+    NvBool IsIdleSignalTristate;
+
+    // Frequency requiremets
+    NvRmDfsBusyHint BusyHints[4];
+
+    // Is this interface used for the pmu programmings
+    NvBool IsPmuInterface;
+
+    // If pmu interface then the CS Id for the interfacing.
+    NvU32 PmuChipSelectId;
+
+    // Tells whether frequency is boosted or not.
+    NvBool IsFreqBoosted;
+} NvRmSpi;
+
+/**
+ * Combines the spi/slink structure information.
+ */
+typedef struct
+{
+    // Nv Rm device handles.
+    NvRmDeviceHandle hDevice;
+
+    // Pointer to the list of the handles of the spi/slink channels.
+    NvRmSpiHandle hSpiSlinkChannelList[MAX_SPI_SLINK_INSTANCE];
+
+    // Mutex for spi/slink channel information.
+    NvOsMutexHandle hChannelAccessMutex;
+} NvRmPrivSpiSlinkInfo;
+
+typedef struct
+{
+    NvU32 MajorVersion;
+    NvU32 MinorVersion;
+} SlinkCapabilities;
+
+static NvRmPrivSpiSlinkInfo s_SpiSlinkInfo;
+static HwInterface s_SpiHwInterface;
+static HwInterface s_SlinkHwInterface;
+
+/**
+ * Get the interfacing property for the device connected to given chip select Id.
+ * Returns whether this is supported or not.
+ */
+static NvBool
+SpiSlinkGetDeviceInfo(
+    NvBool IsSpiChannel,
+    NvU32 InstanceId,
+    NvU32 ChipSelect,
+    NvOdmQuerySpiDeviceInfo *pDeviceInfo)
+{
+    const NvOdmQuerySpiDeviceInfo *pSpiDevInfo = NULL;
+    NvOdmIoModule OdmModuleName;
+
+    OdmModuleName = (IsSpiChannel)?  NvOdmIoModule_Sflash: NvOdmIoModule_Spi;
+    pSpiDevInfo = NvOdmQuerySpiGetDeviceInfo(OdmModuleName, InstanceId, ChipSelect);
+    if (!pSpiDevInfo)
+    {
+        // No device info in odm, so set it on default state.
+        pDeviceInfo->SignalMode = NvOdmQuerySpiSignalMode_0;
+        pDeviceInfo->ChipSelectActiveLow = NV_TRUE;
+        return NV_FALSE;
+    }
+    pDeviceInfo->SignalMode = pSpiDevInfo->SignalMode;
+    pDeviceInfo->ChipSelectActiveLow = pSpiDevInfo->ChipSelectActiveLow;
+    return NV_TRUE;
+}
+
+/**
+ * Find whether this interface is the pmu interface or not.
+ * Returns TRUE if the given spi channel is the pmu interface else return 
+ * FALSE.
+ */
+static NvBool
+SpiSlinkIsPmuInterface(
+    NvBool IsSpiChannel,
+    NvU32 InstanceId,
+    NvU32 *pChipSelectId)
+{
+    NvOdmIoModule OdmModuleName;
+    NvU64 Guid = NV_PMU_TRANSPORT_ODM_ID;
+    NvOdmPeripheralConnectivity const *pConnectivity;
+    NvU32 Index;
+
+    OdmModuleName = (IsSpiChannel)?  NvOdmIoModule_Sflash: NvOdmIoModule_Spi;
+    *pChipSelectId = 0xFF;
+
+     /* get the connectivity info */
+    pConnectivity = NvOdmPeripheralGetGuid(Guid);
+    if (!pConnectivity)
+         return NV_FALSE;
+
+    // Search for the Vdd rail and set the proper volage to the rail.
+    for (Index = 0; Index < pConnectivity->NumAddress; ++Index)
+    {
+        if ((pConnectivity->AddressList[Index].Interface == OdmModuleName) &&
+             (pConnectivity->AddressList[Index].Instance == InstanceId))
+        {
+            *pChipSelectId = pConnectivity->AddressList[Index].Address;
+            return NV_TRUE;
+        }
+    }
+    return NV_FALSE;
+}
+
+
+/**
+ * Create the dma buffer memory handle.
+ */
+static NvError
+CreateDmaBufferMemoryHandle(
+    NvRmDeviceHandle hDevice,
+    NvRmMemHandle *phNewMemHandle,
+    NvRmPhysAddr *pNewMemAddr,
+    NvU32 BufferSize)
+{
+    NvError Error = NvSuccess;
+    NvRmMemHandle hNewMemHandle = NULL;
+
+    // Initialize the memory handle with NULL
+    *phNewMemHandle = NULL;
+
+    /// Create memory handle
+    Error = NvRmMemHandleCreate(hDevice, &hNewMemHandle, BufferSize);
+
+    // Allocates the memory from the sdram
+    if (!Error)
+        Error = NvRmMemAlloc(hNewMemHandle, NULL,
+                        0, DMA_BUFFER_ALIGNMENT,
+                        NvOsMemAttribute_Uncached);
+
+    // Pin the memory allocation so that it should not move by memory manager.
+    if (!Error)
+        *pNewMemAddr = NvRmMemPin(hNewMemHandle);
+
+    // If error then free the memory allocation and memory handle.
+    if (Error)
+    {
+        NvRmMemHandleFree(hNewMemHandle);
+        hNewMemHandle = NULL;
+    }
+
+    *phNewMemHandle = hNewMemHandle;
+    return Error;
+}
+
+ /**
+  * Destroy the dma buffer memory handle.
+  * Thread safety: Caller responsibity.
+  */
+static void DestroyDmaBufferMemoryHandle(NvRmMemHandle hMemHandle)
+{
+    // Can accept the null parameter. If it is not null then only destroy.
+    if (hMemHandle)
+    {
+        // Unpin the memory allocation.
+        NvRmMemUnpin(hMemHandle);
+
+        // Free the memory handle.
+        NvRmMemHandleFree(hMemHandle);
+    }
+}
+
+/**
+ * Create the dma transfer buffer for the given handles.
+ * Thread safety: Caller responsibity.
+ */
+static NvError
+CreateDmaTransferBuffer(
+    NvRmDeviceHandle hRmDevice,
+    NvRmMemHandle *phRmMemory,
+    NvRmPhysAddr *pBuffPhysAddr1,
+    void **pBuffPtr1,
+    NvRmPhysAddr *pBuffPhysAddr2,
+    void **pBuffPtr2,
+    NvU32 OneBufferSize)
+{
+    NvError Error = NvSuccess;
+    NvRmMemHandle hRmMemory = NULL;
+    NvRmPhysAddr BuffPhysAddr;
+
+    // Reset all the members realted to the dma buffer.
+    BuffPhysAddr = 0;
+
+    *phRmMemory = NULL;
+    *pBuffPtr1 = (void *)NULL;
+    *pBuffPhysAddr1 = 0;
+    *pBuffPtr2 = (void *)NULL;
+    *pBuffPhysAddr2 = 0;
+
+    // Create the dma buffer memory for receive and transmit.
+    // It will be double of the OneBufferSize
+    Error = CreateDmaBufferMemoryHandle(hRmDevice, &hRmMemory, &BuffPhysAddr,
+                                                            (OneBufferSize <<1));
+    if (!Error)
+    {
+        // 0 to OneBufferSize-1 is buffer 1 and OneBufferSize to 2*OneBufferSize
+        // is second buffer.
+        Error = NvRmMemMap(hRmMemory, 0, OneBufferSize,
+                                        NVOS_MEM_READ_WRITE, pBuffPtr1);
+        if (!Error)
+        {
+            Error = NvRmMemMap(hRmMemory, OneBufferSize, OneBufferSize,
+                                        NVOS_MEM_READ_WRITE, pBuffPtr2);
+            if (Error)
+                NvRmMemUnmap(hRmMemory, pBuffPtr1, OneBufferSize);
+        }
+        // If error then free the allocation and reset all changed value.
+        if (Error)
+        {
+            DestroyDmaBufferMemoryHandle(hRmMemory);
+            hRmMemory = NULL;
+            *pBuffPtr1 = (void *)NULL;
+            *pBuffPtr2 = (void *)NULL;
+            return Error;
+        }
+        *phRmMemory = hRmMemory;
+        *pBuffPhysAddr1 = BuffPhysAddr;
+        *pBuffPhysAddr2 = BuffPhysAddr + OneBufferSize;
+    }
+    return Error;
+}
+
+/**
+ * Destroy the dma transfer buffer.
+ * Thread safety: Caller responsibity.
+ */
+static void
+DestroyDmaTransferBuffer(
+    NvRmMemHandle hRmMemory,
+    void *pBuffPtr1,
+    void *pBuffPtr2,
+    NvU32 OneBufferSize)
+{
+    if (hRmMemory)
+    {
+        if (pBuffPtr1)
+            NvRmMemUnmap(hRmMemory, pBuffPtr1, OneBufferSize);
+        if (pBuffPtr2)
+            NvRmMemUnmap(hRmMemory, pBuffPtr2, OneBufferSize);
+        DestroyDmaBufferMemoryHandle(hRmMemory);
+    }
+}
+
+static NvBool HandleTransferCompletion(NvRmSpiHandle hRmSpiSlink)
+{
+    NvU32 WordsReq;
+    NvU32 WordsRead;
+    NvU32 CurrPacketSize;
+    NvU32 WordsWritten;
+    HwInterfaceHandle hHwInt = hRmSpiSlink->hHwInterface;
+
+    if (hRmSpiSlink->CurrentDirection & SerialHwDataFlow_Tx)
+        hRmSpiSlink->TxTransferStatus =
+            hHwInt->HwGetTransferStatusFxn(&hRmSpiSlink->HwRegs, SerialHwDataFlow_Tx);
+
+    if (hRmSpiSlink->CurrentDirection & SerialHwDataFlow_Rx)
+        hRmSpiSlink->RxTransferStatus =
+            hHwInt->HwGetTransferStatusFxn(&hRmSpiSlink->HwRegs, SerialHwDataFlow_Rx);
+
+    hHwInt->HwClearTransferStatusFxn(&hRmSpiSlink->HwRegs, hRmSpiSlink->CurrentDirection);
+
+    // Any error then stop the transfer and return.
+    if (hRmSpiSlink->RxTransferStatus || hRmSpiSlink->TxTransferStatus)
+    {
+        hHwInt->HwSetDataFlowFxn(&hRmSpiSlink->HwRegs, hRmSpiSlink->CurrentDirection, NV_FALSE);
+        hHwInt->HwResetFifoFxn(&hRmSpiSlink->HwRegs, SerialHwFifo_Both);
+        hRmSpiSlink->CurrTransInfo.PacketTransferred +=
+                            hHwInt->HwGetTransferdCountFxn(&hRmSpiSlink->HwRegs);
+        hRmSpiSlink->CurrentDirection = SerialHwDataFlow_None;
+        return NV_TRUE;
+    }
+
+    // If dma transfer complete then return transfer completion.
+    if (hRmSpiSlink->IsUsingApbDma)
+        return NV_TRUE;
+
+    if ((hRmSpiSlink->CurrentDirection & SerialHwDataFlow_Rx) &&
+                                (hRmSpiSlink->CurrTransInfo.RxPacketsRemaining))
+    {
+        WordsReq = ((hRmSpiSlink->CurrTransInfo.CurrPacketCount) +
+                        ((hRmSpiSlink->CurrTransInfo.PacketsPerWord) -1))/
+                        (hRmSpiSlink->CurrTransInfo.PacketsPerWord);
+
+        WordsRead = hHwInt->HwReadFromReceiveFifoFxn(&hRmSpiSlink->HwRegs,
+                            hRmSpiSlink->CurrTransInfo.pRxBuff, WordsReq);
+        hRmSpiSlink->CurrTransInfo.RxPacketsRemaining -=
+                                hRmSpiSlink->CurrTransInfo.CurrPacketCount;
+        hRmSpiSlink->CurrTransInfo.PacketTransferred +=
+                                hRmSpiSlink->CurrTransInfo.CurrPacketCount;
+        hRmSpiSlink->CurrTransInfo.pRxBuff += WordsRead;
+     }
+
+    if ((hRmSpiSlink->CurrentDirection & SerialHwDataFlow_Tx) &&
+                            (hRmSpiSlink->CurrTransInfo.TxPacketsRemaining))
+    {
+        WordsReq = (hRmSpiSlink->CurrTransInfo.TxPacketsRemaining +
+                        hRmSpiSlink->CurrTransInfo.PacketsPerWord -1)/
+                        hRmSpiSlink->CurrTransInfo.PacketsPerWord;
+
+        WordsWritten = hHwInt->HwWriteInTransmitFifoFxn(
+                            &hRmSpiSlink->HwRegs,
+                            hRmSpiSlink->CurrTransInfo.pTxBuff, WordsReq);
+        CurrPacketSize = NV_MIN(hRmSpiSlink->CurrTransInfo.PacketsPerWord * WordsWritten,
+                            hRmSpiSlink->CurrTransInfo.TxPacketsRemaining);
+        hHwInt->HwSetDmaTransferSizeFxn(&hRmSpiSlink->HwRegs, CurrPacketSize);
+        hHwInt->HwStartTransferFxn(&hRmSpiSlink->HwRegs,
+                                                NV_FALSE);
+        hRmSpiSlink->CurrTransInfo.CurrPacketCount = CurrPacketSize;
+        hRmSpiSlink->CurrTransInfo.TxPacketsRemaining -= CurrPacketSize;
+        hRmSpiSlink->CurrTransInfo.PacketTransferred += CurrPacketSize;
+        hRmSpiSlink->CurrTransInfo.pTxBuff += WordsWritten;
+        return NV_FALSE;
+    }
+
+    // If still need to do the transfer for receiving the data then start now.
+    if ((hRmSpiSlink->CurrentDirection & SerialHwDataFlow_Rx) &&
+                            (hRmSpiSlink->CurrTransInfo.RxPacketsRemaining))
+    {
+        CurrPacketSize = NV_MIN(hRmSpiSlink->CurrTransInfo.RxPacketsRemaining,
+                                (hRmSpiSlink->HwRegs.MaxWordTransfer*
+                                    hRmSpiSlink->CurrTransInfo.PacketsPerWord));
+        hRmSpiSlink->CurrTransInfo.CurrPacketCount = CurrPacketSize;
+        hHwInt->HwSetDmaTransferSizeFxn(&hRmSpiSlink->HwRegs, CurrPacketSize);
+        hHwInt->HwStartTransferFxn(&hRmSpiSlink->HwRegs, NV_FALSE);
+        return NV_FALSE;
+    }
+
+    // All requested transfer is completed.
+    return NV_TRUE;
+}
+
+static void SpiSlinkIsr(void *args)
+{
+    NvRmSpiHandle hRmSpiSlink = args;
+    NvBool IsTransferCompleted;
+
+    IsTransferCompleted = HandleTransferCompletion(hRmSpiSlink);
+    if (IsTransferCompleted)
+        NvOsSemaphoreSignal(hRmSpiSlink->hSynchSema);
+    NvRmInterruptDone(hRmSpiSlink->SpiInterruptHandle);
+}
+
+
+static NvError
+WaitForTransferCompletion(
+    NvRmSpiHandle hRmSpiSlink,
+    NvU32 WaitTimeOutMS,
+    NvBool IsPoll)
+{
+    NvBool IsReady;
+    NvBool IsTransferComplete= NV_FALSE;
+    NvU32 StartTime;
+    NvU32 CurrentTime;
+    NvU32 TimeElapsed;
+    NvBool IsWait = NV_TRUE;
+    NvError Error = NvSuccess;
+    NvU32 DmaRxTransferCountBytes = 0;
+    NvU32 PacketTransferedFromFifoYet = 0;
+    NvU32 CurrentSlinkPacketTransfer;
+    NvU32 PacketsInRxFifo;
+    NvU32 WordsAvailbleInFifo;
+    NvU32 WordsRead;
+    NvU32 *pUpdatedRxBuffer = NULL;
+#if NV_OAL
+    // For oal version, we only use the polling method.
+    IsPoll = NV_TRUE;
+#endif
+
+    if (IsPoll)
+    {
+        StartTime = NvOsGetTimeMS();
+        while (IsWait)
+        {
+            IsReady = hRmSpiSlink->hHwInterface->HwIsTransferCompletedFxn(&hRmSpiSlink->HwRegs);
+            if (IsReady)
+            {
+                IsTransferComplete = HandleTransferCompletion(hRmSpiSlink);
+                if(IsTransferComplete)
+                    break;
+            }
+            if (WaitTimeOutMS != NV_WAIT_INFINITE)
+            {
+                CurrentTime = NvOsGetTimeMS();
+                TimeElapsed = (CurrentTime >= StartTime)? (CurrentTime - StartTime):
+                                    MAX_TIME_IN_MS - StartTime + CurrentTime;
+                IsWait = (TimeElapsed > WaitTimeOutMS)? NV_FALSE: NV_TRUE;
+            }
+        }
+
+        Error = (IsTransferComplete)? NvError_Success: NvError_Timeout;
+#if NV_OAL
+        // If no error and apb dma based transfer then stop the dma transfer to
+        // make the state dma state machine as non busy.
+        if ((!Error) && (hRmSpiSlink->IsUsingApbDma))
+        {
+            if (hRmSpiSlink->CurrentDirection & SerialHwDataFlow_Rx)
+                NvRmDmaAbort(hRmSpiSlink->hRmRxDma);
+            if (hRmSpiSlink->CurrentDirection & SerialHwDataFlow_Tx)
+                NvRmDmaAbort(hRmSpiSlink->hRmTxDma);
+        }
+#endif
+    }
+    else
+    {
+        Error = NvOsSemaphoreWaitTimeout(hRmSpiSlink->hSynchSema, WaitTimeOutMS);
+    }
+
+    // If timeout happen then stop all transfer and exit.
+    if (Error == NvError_Timeout)
+    {
+        // Disable the data flow first.
+        hRmSpiSlink->hHwInterface->HwSetDataFlowFxn(&hRmSpiSlink->HwRegs,
+                                    hRmSpiSlink->CurrentDirection, NV_FALSE);
+
+        // Get the transfer count now.
+        if (hRmSpiSlink->IsUsingApbDma)
+        {
+            if (hRmSpiSlink->CurrentDirection & SerialHwDataFlow_Rx)
+            {
+                // Get the Rx transfer count transferred by Dma.
+                Error = NvRmDmaGetTransferredCount(hRmSpiSlink->hRmRxDma,
+                            &DmaRxTransferCountBytes, NV_TRUE);
+                NV_ASSERT(Error == NvSuccess);
+                if (Error != NvSuccess)
+                    DmaRxTransferCountBytes = 0;
+                PacketTransferedFromFifoYet = (DmaRxTransferCountBytes >> 2) *
+                                                hRmSpiSlink->CurrTransInfo.PacketsPerWord;
+                pUpdatedRxBuffer = hRmSpiSlink->pRxDmaBuffer + (DmaRxTransferCountBytes >> 2);
+                NvRmDmaAbort(hRmSpiSlink->hRmRxDma);
+            }
+
+            if (hRmSpiSlink->CurrentDirection & SerialHwDataFlow_Tx)
+                NvRmDmaAbort(hRmSpiSlink->hRmTxDma);
+        }
+        else
+        {
+            PacketTransferedFromFifoYet = hRmSpiSlink->CurrTransInfo.PacketTransferred;
+            pUpdatedRxBuffer = hRmSpiSlink->CurrTransInfo.pRxBuff;
+        }
+
+        // Check again whether the transfer is completed or not.
+        // It may be possible that transfer is completed when we reach here.
+        // If transfer is completed then we may read 0 from the status
+        // register
+        IsReady = hRmSpiSlink->hHwInterface->HwIsTransferCompletedFxn(&hRmSpiSlink->HwRegs);
+        if (IsReady)
+        {
+            // All requested transfer has been done.
+            CurrentSlinkPacketTransfer = hRmSpiSlink->CurrTransInfo.CurrPacketCount;
+            Error = NvSuccess;
+        }
+        else
+        {
+            // Get the transfer count from status register.
+            CurrentSlinkPacketTransfer =
+                hRmSpiSlink->hHwInterface->HwGetTransferdCountFxn(&hRmSpiSlink->HwRegs);
+
+            // If it is in packed mode and number of received packet is non word
+            // aligned then ignore the packet which does not able to make the word.
+            // This is because we can not read such packet from fifo as this is not
+            // avaiable in the fifo. -- Hw issue
+            if (hRmSpiSlink->CurrentDirection & SerialHwDataFlow_Rx)
+            {
+                if (hRmSpiSlink->CurrTransInfo.PacketsPerWord > 1)
+                    CurrentSlinkPacketTransfer -=
+                                CurrentSlinkPacketTransfer%
+                                            hRmSpiSlink->CurrTransInfo.PacketsPerWord;
+            }
+
+        }
+        hRmSpiSlink->CurrTransInfo.PacketTransferred += CurrentSlinkPacketTransfer;
+
+        // Disable the interrupt.
+        if (!IsPoll)
+            hRmSpiSlink->hHwInterface->HwSetInterruptSourceFxn(&hRmSpiSlink->HwRegs,
+                                        hRmSpiSlink->CurrentDirection, NV_FALSE);
+
+        // For Rx: Dma will always transfer equal to or less than slink has
+        // transferred. If slink has transferred more data and dma have
+        // not transferrd from the fifo to memory then there may be some more
+        // data available into the fifo. Reading those from cpu.
+        // For Tx: The dma will transfer more than slink has and non transferred
+        // data wil be in foopf which will get reset after slink reset. No need
+        // to do any more for tx case.
+        if (hRmSpiSlink->CurrentDirection & SerialHwDataFlow_Rx)
+        {
+            // If slink transfrred word is more than the dma transfer count
+            // then some more data is available into the fifo. Read then
+            // through CPU.
+            if (PacketTransferedFromFifoYet < CurrentSlinkPacketTransfer)
+            {
+                PacketsInRxFifo = CurrentSlinkPacketTransfer - PacketTransferedFromFifoYet;
+                WordsAvailbleInFifo =
+                    (PacketsInRxFifo + hRmSpiSlink->CurrTransInfo.PacketsPerWord -1)/
+                                            hRmSpiSlink->CurrTransInfo.PacketsPerWord;
+                WordsRead = hRmSpiSlink->hHwInterface->HwReadFromReceiveFifoFxn(
+                                &hRmSpiSlink->HwRegs, pUpdatedRxBuffer, WordsAvailbleInFifo);
+
+                // Expecting the WordsRead should be equal to WordsAvailbleInFifo
+                if (WordsRead != WordsAvailbleInFifo)
+                {
+                    NV_ASSERT(WordsRead == WordsAvailbleInFifo);
+                }
+            }
+        }
+
+
+        // The busy bit will still show the busy status so need to reset the
+        // controller.  .. Hw Bug
+        NvRmModuleReset(hRmSpiSlink->hDevice,
+                    NVRM_MODULE_ID(hRmSpiSlink->RmModuleId, hRmSpiSlink->InstanceId));
+        hRmSpiSlink->CurrentDirection = SerialHwDataFlow_None;
+    }
+    return Error;
+}
+
+#if NV_OAL
+static void OalMasterSpiSlinkPoll(NvRmSpiHandle hRmSpiSlink)
+{
+    NvBool IsReady;
+    NvBool TransferComplete = NV_FALSE;
+    //Check for the transfer complete in infinite loop
+    while (1)
+    {
+        IsReady =  hRmSpiSlink->hHwInterface->HwIsTransferCompletedFxn(&hRmSpiSlink->HwRegs);
+        if (IsReady)
+        {
+            TransferComplete = HandleTransferCompletion(hRmSpiSlink);
+            if(TransferComplete)
+                break;
+        }
+    }
+}
+#endif
+
+/**
+ * Register the spi interrupt.
+ * Thread safety: Caller responsibity.
+ */
+static NvError
+RegisterSpiSlinkInterrupt(
+    NvRmDeviceHandle hDevice,
+    NvRmSpiHandle hRmSpiSlink,
+    NvU32 InstanceId)
+{
+    NvU32 IrqList;
+    NvOsInterruptHandler hIntHandlers;
+    if (hRmSpiSlink->SpiInterruptHandle)
+        return NvSuccess;
+
+    IrqList = NvRmGetIrqForLogicalInterrupt(
+            hDevice, NVRM_MODULE_ID(hRmSpiSlink->RmModuleId, InstanceId), 0);
+    hIntHandlers = SpiSlinkIsr;
+    return(NvRmInterruptRegister(hDevice, 1, &IrqList,
+            &hIntHandlers, hRmSpiSlink, &hRmSpiSlink->SpiInterruptHandle, NV_TRUE));
+}
+// Boosting the Emc/Ahb/Apb/Cpu frequency
+static void BoostFrequency(NvRmSpiHandle hRmSpiSlink, NvBool IsBoost, NvU32 TransactionSize)
+{
+    if (IsBoost)
+    {
+        if (TransactionSize > hRmSpiSlink->HwRegs.MaxWordTransfer)
+        {
+            if (!((hRmSpiSlink->IsPmuInterface) &&
+                   (hRmSpiSlink->PmuChipSelectId == hRmSpiSlink->CurrTransferChipSelId)))
+            {
+                hRmSpiSlink->BusyHints[0].BoostKHz = 80000; // Emc
+                hRmSpiSlink->BusyHints[1].BoostKHz = 80000; // Ahb
+                hRmSpiSlink->BusyHints[2].BoostKHz = 80000; // Apb
+                hRmSpiSlink->BusyHints[3].BoostKHz = 240000; // Cpu
+                NvRmPowerBusyHintMulti(hRmSpiSlink->hDevice, hRmSpiSlink->RmPowerClientId,
+                                       hRmSpiSlink->BusyHints, 4,
+                                       NvRmDfsBusyHintSyncMode_Async);
+                hRmSpiSlink->IsFreqBoosted = NV_TRUE;
+            }
+        }
+    }
+    else
+    {
+        if (hRmSpiSlink->IsFreqBoosted)
+        {
+            if (!((hRmSpiSlink->IsPmuInterface) &&
+                   (hRmSpiSlink->PmuChipSelectId == hRmSpiSlink->CurrTransferChipSelId)))
+            {
+                hRmSpiSlink->BusyHints[0].BoostKHz = 0; // Emc
+                hRmSpiSlink->BusyHints[1].BoostKHz = 0; // Ahb
+                hRmSpiSlink->BusyHints[2].BoostKHz = 0; // Apb
+                hRmSpiSlink->BusyHints[3].BoostKHz = 0; // Cpu
+                NvRmPowerBusyHintMulti(hRmSpiSlink->hDevice, hRmSpiSlink->RmPowerClientId,
+                                       hRmSpiSlink->BusyHints, 4,
+                                       NvRmDfsBusyHintSyncMode_Async);
+                hRmSpiSlink->IsFreqBoosted = NV_FALSE;
+            }
+        }
+    }
+}
+
+static NvError SetPowerControl(NvRmSpiHandle hRmSpiSlink, NvBool IsEnable)
+{
+    NvError Error = NvSuccess;
+    NvRmModuleID ModuleId;
+
+    ModuleId = NVRM_MODULE_ID(hRmSpiSlink->RmModuleId, hRmSpiSlink->InstanceId);
+    if (IsEnable)
+    {
+        // Enable power for spi/slink module
+        Error = NvRmPowerVoltageControl(hRmSpiSlink->hDevice, ModuleId,
+                                    hRmSpiSlink->RmPowerClientId,
+                                    NvRmVoltsUnspecified, NvRmVoltsUnspecified,
+                                    NULL, 0, NULL);
+        // Enable the clock.
+        if (!Error)
+            Error = NvRmPowerModuleClockControl(hRmSpiSlink->hDevice, ModuleId,
+                                    hRmSpiSlink->RmPowerClientId, NV_TRUE);
+    }
+    else
+    {
+        // Disable the clocks.
+        (void)NvRmPowerModuleClockControl(hRmSpiSlink->hDevice, ModuleId,
+                        hRmSpiSlink->RmPowerClientId, NV_FALSE);
+
+
+        // Disable the power to the controller.
+        (void)NvRmPowerVoltageControl(hRmSpiSlink->hDevice, ModuleId,
+                                        hRmSpiSlink->RmPowerClientId,
+                                        NvRmVoltsOff, NvRmVoltsOff,
+                                        NULL, 0, NULL);
+    }
+    return Error;
+}
+
+/**
+ * Destroy the handle of spi channel and free all the allocation done for it.
+ * Thread safety: Caller responsibity.
+ */
+static void DestroySpiSlinkChannelHandle(NvRmSpiHandle hRmSpiSlink)
+{
+    NvU32 HandleStartIndex;
+#if !NV_OAL
+    NvRmInterruptUnregister(hRmSpiSlink->hDevice, hRmSpiSlink->SpiInterruptHandle);
+    hRmSpiSlink->SpiInterruptHandle = NULL;
+#endif
+
+
+    // Unmap the virtual mapping of the spi hw register.
+    NvRmPhysicalMemUnmap(hRmSpiSlink->HwRegs.pRegsBaseAdd, hRmSpiSlink->HwRegs.RegBankSize);
+
+    // the clocks should already be disabled for Non-oal. don't disable it here for non-oal
+    // For oal disable here.
+#if NV_OAL
+
+    // Resetting the Emc/Ahb/Apb/Cpu frequency
+    BoostFrequency(hRmSpiSlink, NV_FALSE, 0);
+    (void)SetPowerControl(hRmSpiSlink, NV_FALSE);
+#endif
+
+#if !NV_OAL
+    // Unregister for the power manager.
+    NvRmPowerUnRegister(hRmSpiSlink->hDevice, hRmSpiSlink->RmPowerClientId);
+#endif
+
+    // Tri-State the pin-mux pins
+    NV_ASSERT_SUCCESS(NvRmSetModuleTristate(hRmSpiSlink->hDevice,
+        NVRM_MODULE_ID(hRmSpiSlink->RmModuleId,hRmSpiSlink->InstanceId), NV_TRUE));
+
+    NvOsFree(hRmSpiSlink->pTxCpuBuffer);
+    NvOsFree(hRmSpiSlink->pRxCpuBuffer);
+
+    if (hRmSpiSlink->hRmRxDma)
+    {
+        NvRmDmaAbort(hRmSpiSlink->hRmRxDma);
+        NvRmDmaFree(hRmSpiSlink->hRmRxDma);
+    }
+
+    if (hRmSpiSlink->hRmTxDma)
+    {
+        NvRmDmaAbort(hRmSpiSlink->hRmTxDma);
+        NvRmDmaFree(hRmSpiSlink->hRmTxDma);
+    }
+
+    DestroyDmaTransferBuffer(hRmSpiSlink->hRmMemory, hRmSpiSlink->pRxDmaBuffer,
+                hRmSpiSlink->pTxDmaBuffer, hRmSpiSlink->DmaBufferSize);
+
+#if !NV_OAL
+    // Destroy the mutex allocated for the channel accss.
+    NvOsMutexDestroy(hRmSpiSlink->hChannelAccessMutex);
+
+    // Destroy the sync sempahores.
+    NvOsSemaphoreDestroy(hRmSpiSlink->hSynchSema);
+#endif
+
+    HandleStartIndex = (hRmSpiSlink->IsSpiChannel)? 0: MAX_SPI_CONTROLLERS;
+    s_SpiSlinkInfo.hSpiSlinkChannelList[HandleStartIndex + hRmSpiSlink->InstanceId] = NULL;
+
+    // Free the memory of the spi handles.
+    NvOsFree(hRmSpiSlink);
+}
+
+
+/**
+ * Create the handle for the spi channel.
+ * Thread safety: Caller responsibity.
+ */
+static NvError CreateSpiSlinkChannelHandle(
+    NvRmDeviceHandle hDevice,
+    NvBool IsSpiChannel,
+    NvU32 InstanceId,
+    NvBool IsMasterMode,
+    NvRmSpiHandle *phSpiSlinkChannel)
+{
+    NvError Error = NvSuccess;
+    NvRmSpiHandle hRmSpiSlink = NULL;
+    NvRmModuleID ModuleId;
+    NvU32 ChipSelIndex;
+    NvU32 InstIndexOffset = (IsSpiChannel)? 0: MAX_SPI_CONTROLLERS;
+    const NvU32 *pOdmConfigs;
+    NvU32 NumOdmConfigs;
+    NvU32 CpuBufferSize;
+    NvRmDmaModuleID DmaModuleId;
+    const NvOdmQuerySpiIdleSignalState *pSignalState = NULL;
+
+    *phSpiSlinkChannel = NULL;
+
+    // Allcoate the memory for the spi handle.
+    hRmSpiSlink = NvOsAlloc(sizeof(NvRmSpi));
+    if (!hRmSpiSlink)
+        return NvError_InsufficientMemory;
+
+    NvOsMemset(hRmSpiSlink, 0, sizeof(NvRmSpi));
+
+    // Set the spi handle parameters.
+    hRmSpiSlink->hDevice = hDevice;
+    hRmSpiSlink->InstanceId = InstanceId;
+    hRmSpiSlink->IsSpiChannel = IsSpiChannel;
+    hRmSpiSlink->IsMasterMode = IsMasterMode;
+    hRmSpiSlink->RmModuleId = (IsSpiChannel)?NvRmModuleID_Spi: NvRmModuleID_Slink;
+    hRmSpiSlink->RmIoModuleId = (IsSpiChannel)?NvOdmIoModule_Sflash: NvOdmIoModule_Spi;
+    hRmSpiSlink->OpenCount = 1;
+    hRmSpiSlink->IsApbDmaAllocated = NV_FALSE;
+    hRmSpiSlink->TransCountFromLastDmaUsage = 0;
+    hRmSpiSlink->hRmRxDma = NULL;
+    hRmSpiSlink->hRmMemory = NULL;
+    hRmSpiSlink->hRmTxDma = NULL;
+    hRmSpiSlink->DmaRxBuffPhysAdd = 0;
+    hRmSpiSlink->DmaTxBuffPhysAdd = 0;
+    hRmSpiSlink->pRxDmaBuffer = NULL;
+    hRmSpiSlink->pTxDmaBuffer = NULL;
+    hRmSpiSlink->pTxCpuBuffer = NULL;
+    hRmSpiSlink->pRxCpuBuffer = NULL;
+    hRmSpiSlink->CpuBufferSizeInWords = 0;
+    hRmSpiSlink->hHwInterface = NULL;
+    hRmSpiSlink->RmPowerClientId = 0;
+    hRmSpiSlink->SpiPinMap = 0;
+    hRmSpiSlink->CurrTransferChipSelId = 0;
+    hRmSpiSlink->IsChipSelConfigured = NV_FALSE;
+    hRmSpiSlink->IsCurrentlySwBasedChipSel = NV_TRUE;
+
+    // Initialize the frequncy requirements array
+    hRmSpiSlink->BusyHints[0].ClockId = NvRmDfsClockId_Emc;
+    hRmSpiSlink->BusyHints[0].BoostDurationMs = NV_WAIT_INFINITE;
+    hRmSpiSlink->BusyHints[0].BusyAttribute = NV_TRUE;
+
+    hRmSpiSlink->BusyHints[1].ClockId = NvRmDfsClockId_Ahb;
+    hRmSpiSlink->BusyHints[1].BoostDurationMs = NV_WAIT_INFINITE;
+    hRmSpiSlink->BusyHints[1].BusyAttribute = NV_TRUE;
+
+    hRmSpiSlink->BusyHints[2].ClockId = NvRmDfsClockId_Apb;
+    hRmSpiSlink->BusyHints[2].BoostDurationMs = NV_WAIT_INFINITE;
+    hRmSpiSlink->BusyHints[2].BusyAttribute = NV_TRUE;
+
+    hRmSpiSlink->BusyHints[3].ClockId = NvRmDfsClockId_Cpu;
+    hRmSpiSlink->BusyHints[3].BoostDurationMs = NV_WAIT_INFINITE;
+    hRmSpiSlink->BusyHints[3].BusyAttribute = NV_TRUE;
+
+    hRmSpiSlink->IsFreqBoosted = NV_FALSE;
+    hRmSpiSlink->IsPmuInterface = NV_FALSE;
+    hRmSpiSlink->PmuChipSelectId = 0xFF;
+
+    ModuleId = NVRM_MODULE_ID(hRmSpiSlink->RmModuleId, InstanceId);
+
+    if (IsSpiChannel)
+        hRmSpiSlink->hHwInterface = &s_SpiHwInterface;
+    else
+        hRmSpiSlink->hHwInterface = &s_SlinkHwInterface;
+
+    for (ChipSelIndex = 0; ChipSelIndex < MAX_CHIPSELECT_PER_INSTANCE; ++ChipSelIndex)
+        hRmSpiSlink->IsChipSelSupported[ChipSelIndex] =
+                SpiSlinkGetDeviceInfo(IsSpiChannel, InstanceId, ChipSelIndex,
+                                    &hRmSpiSlink->DeviceInfo[ChipSelIndex]);
+
+    // Findout whether this spi instance is used for the pmu interface or not.
+    hRmSpiSlink->IsPmuInterface = SpiSlinkIsPmuInterface(IsSpiChannel, 
+                                                InstanceId,
+                                                &hRmSpiSlink->PmuChipSelectId);
+
+    // Get the odm pin map
+    NvOdmQueryPinMux(hRmSpiSlink->RmIoModuleId, &pOdmConfigs, &NumOdmConfigs);
+    NV_ASSERT((InstanceId < NumOdmConfigs) && (pOdmConfigs[InstanceId]));
+    hRmSpiSlink->SpiPinMap = pOdmConfigs[InstanceId];
+
+    pSignalState = NvOdmQuerySpiGetIdleSignalState(hRmSpiSlink->RmIoModuleId, InstanceId);
+    if (pSignalState)
+    {
+        hRmSpiSlink->IsIdleSignalTristate = pSignalState->IsTristate;
+        hRmSpiSlink->HwRegs.IdleSignalMode = pSignalState->SignalMode;
+        hRmSpiSlink->HwRegs.IsIdleDataOutHigh = pSignalState->IsIdleDataOutHigh;
+    }
+    else
+    {
+        hRmSpiSlink->IsIdleSignalTristate = NV_FALSE;
+        hRmSpiSlink->HwRegs.IdleSignalMode = NvOdmQuerySpiSignalMode_0;
+        hRmSpiSlink->HwRegs.IsIdleDataOutHigh = NV_FALSE;
+    }
+    Error = NvRmSetModuleTristate(hRmSpiSlink->hDevice, ModuleId,
+                                        hRmSpiSlink->IsIdleSignalTristate);
+    if (Error)
+    {
+        // If error then return from here.
+        NvOsFree(hRmSpiSlink);
+        return Error;
+    }
+
+    hRmSpiSlink->RxTransferStatus = NvSuccess;
+    hRmSpiSlink->TxTransferStatus = NvSuccess;
+
+    hRmSpiSlink->hHwInterface->HwRegisterInitializeFxn(InstanceId, &hRmSpiSlink->HwRegs);
+
+#if !NV_OAL
+    // Create the mutex for channel access.
+    if (!Error)
+        Error = NvOsMutexCreate(&hRmSpiSlink->hChannelAccessMutex);
+
+    // Create the synchronous semaphores.
+    if (!Error)
+        Error = NvOsSemaphoreCreate(&hRmSpiSlink->hSynchSema, 0);
+#endif
+
+    // Get the spi hw physical base address and map in virtual memory space.
+    if (!Error)
+    {
+        NvRmPhysAddr SpiSlinkPhysAddr;
+        NvRmModuleGetBaseAddress(hDevice, ModuleId,
+                        &SpiSlinkPhysAddr, &hRmSpiSlink->HwRegs.RegBankSize);
+
+        hRmSpiSlink->HwRegs.HwRxFifoAdd += SpiSlinkPhysAddr;
+        hRmSpiSlink->HwRegs.HwTxFifoAdd += SpiSlinkPhysAddr;
+        Error = NvRmPhysicalMemMap(SpiSlinkPhysAddr,
+                            hRmSpiSlink->HwRegs.RegBankSize, NVOS_MEM_READ_WRITE,
+                            NvOsMemAttribute_Uncached,
+                            (void **)&hRmSpiSlink->HwRegs.pRegsBaseAdd);
+    }
+
+    // Allocate the dma buffer and the dma channel
+    if (!Error)
+    {
+        hRmSpiSlink->IsApbDmaAllocated = NV_TRUE;
+
+    // Don't go to the dma allocation if the oal and master mode.
+    // It creates the download issue using the spi kitl if dma mode is used.
+#if NV_OAL
+        if (IsMasterMode)
+        {
+            Error = NvError_NotSupported;
+        }
+        else
+        {
+            Error = CreateDmaTransferBuffer(hRmSpiSlink->hDevice, &hRmSpiSlink->hRmMemory,
+                    &hRmSpiSlink->DmaRxBuffPhysAdd, (void **)&hRmSpiSlink->pRxDmaBuffer,
+                    &hRmSpiSlink->DmaTxBuffPhysAdd, (void **)&hRmSpiSlink->pTxDmaBuffer,
+                    DEFAULT_DMA_BUFFER_SIZE);
+        }
+#else
+        Error = CreateDmaTransferBuffer(hRmSpiSlink->hDevice, &hRmSpiSlink->hRmMemory,
+                &hRmSpiSlink->DmaRxBuffPhysAdd, (void **)&hRmSpiSlink->pRxDmaBuffer,
+                &hRmSpiSlink->DmaTxBuffPhysAdd, (void **)&hRmSpiSlink->pTxDmaBuffer,
+                DEFAULT_DMA_BUFFER_SIZE);
+#endif
+        if (!Error)
+        {
+            hRmSpiSlink->DmaBufferSize = DEFAULT_DMA_BUFFER_SIZE;
+            DmaModuleId = (IsSpiChannel)?NvRmDmaModuleID_Spi: NvRmDmaModuleID_Slink;
+
+            // Allocate the dma (for Rx and for Tx) with high priority
+            // Allocate dma now only for the slave mode handle.
+            // For master mode, it will be allaocated based on the transaction size
+            // to make it adaptive.
+            if (!IsMasterMode)
+            {
+                Error = NvRmDmaAllocate(hRmSpiSlink->hDevice, &hRmSpiSlink->hRmRxDma,
+                                 NV_FALSE, NvRmDmaPriority_High, DmaModuleId,
+                                 hRmSpiSlink->InstanceId);
+                if (!Error)
+                {
+                    Error = NvRmDmaAllocate(hRmSpiSlink->hDevice, &hRmSpiSlink->hRmTxDma,
+                                     NV_FALSE, NvRmDmaPriority_High, DmaModuleId,
+                                     hRmSpiSlink->InstanceId);
+                    if (Error)
+                        NvRmDmaFree(hRmSpiSlink->hRmRxDma);
+                }
+                if (Error)
+                {
+                    DestroyDmaTransferBuffer(hRmSpiSlink->hRmMemory,
+                            hRmSpiSlink->pRxDmaBuffer, hRmSpiSlink->pTxDmaBuffer,
+                            hRmSpiSlink->DmaBufferSize);
+                }
+            }
+            else
+            {
+                hRmSpiSlink->IsApbDmaAllocated = NV_FALSE;
+                hRmSpiSlink->hRmRxDma = NULL;
+                hRmSpiSlink->hRmTxDma = NULL;
+            }
+        }
+        if (Error)
+        {
+            hRmSpiSlink->IsApbDmaAllocated = NV_FALSE;
+            hRmSpiSlink->hRmRxDma = NULL;
+            hRmSpiSlink->hRmMemory = NULL;
+            hRmSpiSlink->hRmTxDma = NULL;
+            hRmSpiSlink->DmaRxBuffPhysAdd = 0;
+            hRmSpiSlink->DmaTxBuffPhysAdd = 0;
+            hRmSpiSlink->pRxDmaBuffer = NULL;
+            hRmSpiSlink->pTxDmaBuffer = NULL;
+            Error = NvSuccess;
+        }
+        else
+        {
+            hRmSpiSlink->RxDmaReq.SourceBufferPhyAddress= hRmSpiSlink->HwRegs.HwRxFifoAdd;
+            hRmSpiSlink->RxDmaReq.DestinationBufferPhyAddress = hRmSpiSlink->DmaRxBuffPhysAdd;
+            hRmSpiSlink->RxDmaReq.SourceAddressWrapSize = 4;
+            hRmSpiSlink->RxDmaReq.DestinationAddressWrapSize = 0;
+
+            hRmSpiSlink->TxDmaReq.SourceBufferPhyAddress= hRmSpiSlink->DmaTxBuffPhysAdd;
+            hRmSpiSlink->TxDmaReq.DestinationBufferPhyAddress = hRmSpiSlink->HwRegs.HwTxFifoAdd;
+            hRmSpiSlink->TxDmaReq.SourceAddressWrapSize = 0;
+            hRmSpiSlink->TxDmaReq.DestinationAddressWrapSize = 4;
+        }
+    }
+
+    if (!Error)
+    {
+        // If dma is allocated then allocate the less size of the cpu buffer
+        // otherwise allocate bigger size to get the optimized timing execution.
+        CpuBufferSize = (hRmSpiSlink->IsApbDmaAllocated)?
+                            (MAX_CPU_TRANSACTION_SIZE_WORD << 2): DEFAULT_DMA_BUFFER_SIZE;
+
+        hRmSpiSlink->pRxCpuBuffer = NvOsAlloc(CpuBufferSize);
+        if (!hRmSpiSlink->pRxCpuBuffer)
+            Error = NvError_InsufficientMemory;
+
+        if (!Error)
+        {
+            hRmSpiSlink->pTxCpuBuffer = NvOsAlloc(CpuBufferSize);
+            if (!hRmSpiSlink->pTxCpuBuffer)
+                Error = NvError_InsufficientMemory;
+        }
+        if (!Error)
+            hRmSpiSlink->CpuBufferSizeInWords = CpuBufferSize >> 2;
+    }
+
+#if !NV_OAL
+    // Register slink/spi for Rm power client
+    if (!Error)
+    {
+       hRmSpiSlink->RmPowerClientId = NVRM_POWER_CLIENT_TAG('S','P','I',' ');
+       Error = NvRmPowerRegister(hRmSpiSlink->hDevice, NULL, &hRmSpiSlink->RmPowerClientId);
+    }
+#endif
+
+    // Enable Power/Clock.
+    if (!Error)
+        Error = SetPowerControl(hRmSpiSlink, NV_TRUE);
+
+    // Reset the module.
+    if (!Error)
+        NvRmModuleReset(hDevice, ModuleId);
+
+#if !NV_OAL
+    // Register the interrupt.
+    if (!Error)
+        Error = RegisterSpiSlinkInterrupt(hDevice, hRmSpiSlink, InstanceId);
+#endif
+
+    // Initialize the controller register.
+    if (!Error)
+    {
+        // Set the default signal mode of the spi channel.
+        hRmSpiSlink->hHwInterface->HwSetSignalModeFxn(&hRmSpiSlink->HwRegs, hRmSpiSlink->HwRegs.IdleSignalMode);
+
+        // Set chip select to non active state.
+        hRmSpiSlink->hHwInterface->HwControllerInitializeFxn(&hRmSpiSlink->HwRegs);
+        for (ChipSelIndex = 0; ChipSelIndex < MAX_CHIPSELECT_PER_INSTANCE; ++ChipSelIndex)
+        {
+            hRmSpiSlink->IsCurrentChipSelStateHigh[ChipSelIndex] = NV_TRUE;
+            if (hRmSpiSlink->IsChipSelSupported[ChipSelIndex])
+            {
+                hRmSpiSlink->IsCurrentChipSelStateHigh[ChipSelIndex] =
+                    hRmSpiSlink->DeviceInfo[ChipSelIndex].ChipSelectActiveLow;
+                hRmSpiSlink->hHwInterface->HwSetChipSelectDefaultLevelFxn(
+                            &hRmSpiSlink->HwRegs, ChipSelIndex,
+                            hRmSpiSlink->IsCurrentChipSelStateHigh[ChipSelIndex]);
+            }
+        }
+        // Let chipselect to be stable for 1 ms before doing any transaction.
+        NvOsWaitUS(1000);
+#if !NV_OAL
+        // switch off clock and power to the slink module by default.
+        Error = SetPowerControl(hRmSpiSlink, NV_FALSE);
+#endif
+    }
+
+    // If error then destroy all the allocation done here.
+    if (Error)
+    {
+        DestroySpiSlinkChannelHandle(hRmSpiSlink);
+        hRmSpiSlink = NULL;
+    }
+
+    *phSpiSlinkChannel = hRmSpiSlink;
+    s_SpiSlinkInfo.hSpiSlinkChannelList[InstanceId + InstIndexOffset] = hRmSpiSlink;
+    return Error;
+}
+
+/**
+ * Set the chip select signal level to be active or inactive.
+ */
+static NvError
+SetChipSelectSignalLevel(
+    NvRmSpiHandle hRmSpiSlink,
+    NvU32 ChipSelectId,
+    NvU32 ClockSpeedInKHz,
+    NvBool IsActive,
+    NvBool IsOnlyUseSWCS)
+{
+    NvError Error = NvSuccess;
+    NvBool IsHigh;
+    NvRmModuleID ModuleId;
+    NvU32 PrefClockFreqInKHz;
+    NvU32 ConfiguredClockFreqInKHz = 0;
+    NvOdmQuerySpiDeviceInfo *pDevInfo = &hRmSpiSlink->DeviceInfo[ChipSelectId];
+    HwInterfaceHandle hHwIntf = hRmSpiSlink->hHwInterface;
+    if (IsActive)
+    {
+        if (ClockSpeedInKHz != hRmSpiSlink->ClockFreqInKHz)
+        {
+            ModuleId = NVRM_MODULE_ID(hRmSpiSlink->RmModuleId, hRmSpiSlink->InstanceId);
+
+            // The slink clock source should be 4 times of the interface clock speed
+            PrefClockFreqInKHz = (hRmSpiSlink->RmModuleId == NvRmModuleID_Slink)?
+                                (ClockSpeedInKHz << 2): (ClockSpeedInKHz);
+            Error = NvRmPowerModuleClockConfig(hRmSpiSlink->hDevice,
+                                          ModuleId, 0, PrefClockFreqInKHz,
+                                          NvRmFreqUnspecified, &PrefClockFreqInKHz,
+                                          1, &ConfiguredClockFreqInKHz, 0);
+            if (Error)
+                return Error;
+
+            hRmSpiSlink->ClockFreqInKHz = ClockSpeedInKHz;
+        }
+
+        if (pDevInfo->SignalMode != hRmSpiSlink->HwRegs.CurrSignalMode)
+            hHwIntf->HwSetSignalModeFxn(&hRmSpiSlink->HwRegs, pDevInfo->SignalMode);
+
+        if (hRmSpiSlink->IsMasterMode != hRmSpiSlink->HwRegs.IsMasterMode)
+            hHwIntf->HwSetFunctionalModeFxn(&hRmSpiSlink->HwRegs, hRmSpiSlink->IsMasterMode);
+
+        if (IsOnlyUseSWCS || (!hRmSpiSlink->HwRegs.IsHwChipSelectSupported))
+        {
+            IsHigh = (pDevInfo->ChipSelectActiveLow)? NV_FALSE: NV_TRUE;
+            hHwIntf->HwSetChipSelectLevelFxn(&hRmSpiSlink->HwRegs, ChipSelectId, IsHigh);
+            hRmSpiSlink->IsChipSelConfigured = NV_TRUE;
+            hRmSpiSlink->IsCurrentlySwBasedChipSel = NV_TRUE;
+            hRmSpiSlink->IsCurrentChipSelStateHigh[ChipSelectId] = IsHigh;
+        }
+        else
+        {
+            hRmSpiSlink->IsChipSelConfigured = NV_FALSE;
+        }
+    }
+    else
+    {
+        if (IsOnlyUseSWCS || hRmSpiSlink->IsCurrentlySwBasedChipSel)
+        {
+            IsHigh = (pDevInfo->ChipSelectActiveLow)? NV_TRUE: NV_FALSE;
+            hHwIntf->HwSetChipSelectLevelFxn(&hRmSpiSlink->HwRegs, ChipSelectId, IsHigh);
+            if (hRmSpiSlink->HwRegs.IdleSignalMode != hRmSpiSlink->HwRegs.CurrSignalMode)
+                hHwIntf->HwSetSignalModeFxn(&hRmSpiSlink->HwRegs, hRmSpiSlink->HwRegs.IdleSignalMode);
+
+            hRmSpiSlink->IsCurrentChipSelStateHigh[ChipSelectId] = IsHigh;
+        }
+        hRmSpiSlink->IsChipSelConfigured = NV_FALSE;
+
+    }
+    return NvSuccess;
+}
+
+
+static void
+MakeMasterSpiBufferFromClientBuffer(
+    NvU8 *pTxBuffer,
+    NvU32 *pSpiBuffer,
+    NvU32 BytesRequested,
+    NvU32 PacketBitLength,
+    NvU32 IsPackedMode)
+{
+    NvU32 Shift0;
+    NvU32 MSBMaskData = 0xFF;
+    NvU32 BytesPerPackets;
+    NvU32 Index;
+    NvU32 PacketRequest;
+
+    if (IsPackedMode)
+    {
+        if (PacketBitLength == 8)
+        {
+            NvOsMemcpy(pSpiBuffer, pTxBuffer, BytesRequested);
+            return;
+        }
+
+        BytesPerPackets = (PacketBitLength + 7)/8;
+        PacketRequest = BytesRequested / BytesPerPackets;
+        if (PacketBitLength == 16)
+        {
+            NvU16 *pOutBuffer = (NvU16 *)pSpiBuffer;
+             for (Index =0; Index < PacketRequest; ++Index)
+             {
+                 *pOutBuffer++ = (NvU16)(((*(pTxBuffer  )) << 8) |
+                                         ((*(pTxBuffer+1))& 0xFF));
+                 pTxBuffer += 2;
+             }
+            return;
+        }
+    }
+
+    BytesPerPackets = (PacketBitLength + 7)/8;
+    PacketRequest = BytesRequested / BytesPerPackets;
+
+    Shift0 = (PacketBitLength & 7);
+    if (Shift0)
+        MSBMaskData = (0xFF >> (8-Shift0));
+
+    if (BytesPerPackets == 1)
+    {
+        for (Index = 0; Index < PacketRequest; ++Index)
+        {
+            *pSpiBuffer++ = (NvU32)((*(pTxBuffer))& MSBMaskData);
+            pTxBuffer++;
+        }
+        return;
+    }
+
+    if (BytesPerPackets == 2)
+    {
+        for (Index = 0; Index < PacketRequest; ++Index)
+        {
+            *pSpiBuffer++ = (NvU32)((((*(pTxBuffer))& MSBMaskData) << 8) |
+                                    ((*(pTxBuffer+1))));
+            pTxBuffer += 2;
+        }
+        return;
+    }
+
+    if (BytesPerPackets == 3)
+    {
+        for (Index = 0; Index < PacketRequest; ++Index)
+        {
+            *pSpiBuffer++ = (NvU32)((((*(pTxBuffer)) & MSBMaskData) << 16) |
+                                    ((*(pTxBuffer+1)) << 8) |
+                                    ((*(pTxBuffer+2))));
+            pTxBuffer += 3;
+        }
+        return;
+    }
+
+    if (BytesPerPackets == 4)
+    {
+        for (Index = 0; Index < PacketRequest; ++Index)
+        {
+            *pSpiBuffer++ = (NvU32)((((*(pTxBuffer))& MSBMaskData) << 24) |
+                                    ((*(pTxBuffer+1)) << 16) |
+                                    ((*(pTxBuffer+2)) << 8) |
+                                    ((*(pTxBuffer+3))));
+            pTxBuffer += 4;
+        }
+        return;
+    }
+}
+
+// Similar to MakeMasterSpiBufferFromClientBuffer() except that SPI slave byte order
+// is reversed compared to SPI master
+static void
+MakeSlaveSpiBufferFromClientBuffer(
+    NvU8 *pTxBuffer,
+    NvU32 *pSpiBuffer,
+    NvU32 BytesRequested,
+    NvU32 PacketBitLength,
+    NvU32 IsPackedMode)
+{
+    NvU32 Shift0;
+    NvU32 MSBMaskData = 0xFF;
+    NvU32 BytesPerPackets;
+    NvU32 Index;
+    NvU32 PacketRequest;
+
+    if (IsPackedMode)
+    {
+        /* SPI slave byte order matches processor endianness, so memcpy can be used */
+        if ((PacketBitLength == 8) || (PacketBitLength == 16))
+        {
+            NvOsMemcpy(pSpiBuffer, pTxBuffer, BytesRequested);
+            return;
+        }
+    }
+
+    BytesPerPackets = (PacketBitLength + 7)/8;
+    PacketRequest = BytesRequested / BytesPerPackets;
+
+    Shift0 = (PacketBitLength & 7);
+    if (Shift0)
+        MSBMaskData = (0xFF >> (8-Shift0));
+
+    if (BytesPerPackets == 1)
+    {
+        for (Index = 0; Index < PacketRequest; ++Index)
+        {
+            *pSpiBuffer++ = (NvU32)((*(pTxBuffer))& MSBMaskData);
+            pTxBuffer++;
+        }
+        return;
+    }
+
+    if (BytesPerPackets == 2)
+    {
+        for (Index = 0; Index < PacketRequest; ++Index)
+        {
+            *pSpiBuffer++ = (NvU32)((((*(pTxBuffer+1))& MSBMaskData) << 8) |
+                                    ((*(pTxBuffer))));
+            pTxBuffer += 2;
+        }
+        return;
+    }
+
+    if (BytesPerPackets == 3)
+    {
+        for (Index = 0; Index < PacketRequest; ++Index)
+        {
+            *pSpiBuffer++ = (NvU32)((((*(pTxBuffer+2)) & MSBMaskData) << 16) |
+                                    ((*(pTxBuffer+1)) << 8) |
+                                    ((*(pTxBuffer))));
+            pTxBuffer += 3;
+        }
+        return;
+    }
+
+    if (BytesPerPackets == 4)
+    {
+        for (Index = 0; Index < PacketRequest; ++Index)
+        {
+            *pSpiBuffer++ = (NvU32)((((*(pTxBuffer+3))& MSBMaskData) << 24) |
+                                    ((*(pTxBuffer+2)) << 16) |
+                                    ((*(pTxBuffer+1)) << 8) |
+                                    ((*(pTxBuffer))));
+            pTxBuffer += 4;
+        }
+        return;
+    }
+}
+
+static void
+MakeMasterClientBufferFromSpiBuffer(
+    NvU8 *pRxBuffer,
+    NvU32 *pSpiBuffer,
+    NvU32 BytesRequested,
+    NvU32 PacketBitLength,
+    NvU32 IsPackedMode)
+{
+    NvU32 Shift0;
+    NvU32 MSBMaskData = 0xFF;
+    NvU32 BytesPerPackets;
+    NvU32 Index;
+    NvU32 RxData;
+    NvU32 PacketRequest;
+
+    NvU8 *pOutBuffer = NULL;
+
+    if (IsPackedMode)
+    {
+        if (PacketBitLength == 8)
+        {
+            NvOsMemcpy(pRxBuffer, pSpiBuffer, BytesRequested);
+            return;
+        }
+
+        BytesPerPackets = (PacketBitLength + 7)/8;
+        PacketRequest = BytesRequested / BytesPerPackets;
+        if (PacketBitLength == 16)
+        {
+            pOutBuffer = (NvU8 *)pSpiBuffer;
+            for (Index =0; Index < PacketRequest; ++Index)
+            {
+                *pRxBuffer++  = (NvU8) (*(pOutBuffer+1));
+                *pRxBuffer++  = (NvU8) (*(pOutBuffer));
+                pOutBuffer += 2;
+            }
+            return;
+        }
+    }
+
+    BytesPerPackets = (PacketBitLength + 7)/8;
+    PacketRequest = BytesRequested / BytesPerPackets;
+    Shift0 = (PacketBitLength & 7);
+    if (Shift0)
+        MSBMaskData = (0xFF >> (8-Shift0));
+
+    if (BytesPerPackets == 1)
+    {
+        for (Index = 0; Index < PacketRequest; ++Index)
+            *pRxBuffer++ = (NvU8)((*pSpiBuffer++) & MSBMaskData);
+        return;
+    }
+
+    if (BytesPerPackets == 2)
+    {
+        for (Index = 0; Index < PacketRequest; ++Index)
+        {
+            RxData = *pSpiBuffer++;
+            *pRxBuffer++ = (NvU8)((RxData >> 8) & MSBMaskData);
+            *pRxBuffer++ = (NvU8)((RxData) & 0xFF);
+        }
+        return;
+    }
+
+    if (BytesPerPackets == 3)
+    {
+        for (Index = 0; Index < PacketRequest; ++Index)
+        {
+            RxData = *pSpiBuffer++;
+            *pRxBuffer++ = (NvU8)((RxData >> 16)& MSBMaskData);
+            *pRxBuffer++ = (NvU8)((RxData >> 8)& 0xFF);
+            *pRxBuffer++ = (NvU8)((RxData) & 0xFF);
+        }
+        return;
+    }
+
+    if (BytesPerPackets == 4)
+    {
+        for (Index = 0; Index < PacketRequest; ++Index)
+        {
+            RxData = *pSpiBuffer++;
+            *pRxBuffer++ = (NvU8)((RxData >> 24)& MSBMaskData);
+            *pRxBuffer++ = (NvU8)((RxData >> 16)& 0xFF);
+            *pRxBuffer++ = (NvU8)((RxData >> 8)& 0xFF);
+            *pRxBuffer++ = (NvU8)((RxData) & 0xFF);
+        }
+        return;
+    }
+}
+
+// Similar to MakeMasterClientBufferFromSpiBuffer() except that SPI slave byte order
+// is reversed compared to SPI master
+static void
+MakeSlaveClientBufferFromSpiBuffer(
+    NvU8 *pRxBuffer,
+    NvU32 *pSpiBuffer,
+    NvU32 BytesRequested,
+    NvU32 PacketBitLength,
+    NvU32 IsPackedMode)
+{
+    NvU32 Shift0;
+    NvU32 MSBMaskData = 0xFF;
+    NvU32 BytesPerPackets;
+    NvU32 Index;
+    NvU32 RxData;
+    NvU32 PacketRequest;
+
+    if (IsPackedMode)
+    {
+        /* SPI slave byte order matches processor endianness, so memcpy can be used */
+        if ((PacketBitLength == 8) || (PacketBitLength == 16))
+        {
+            NvOsMemcpy(pRxBuffer, pSpiBuffer, BytesRequested);
+            return;
+        }
+    }
+
+    BytesPerPackets = (PacketBitLength + 7)/8;
+    PacketRequest = BytesRequested / BytesPerPackets;
+    Shift0 = (PacketBitLength & 7);
+    if (Shift0)
+        MSBMaskData = (0xFF >> (8-Shift0));
+
+    if (BytesPerPackets == 1)
+    {
+        for (Index = 0; Index < PacketRequest; ++Index)
+            *pRxBuffer++ = (NvU8)((*pSpiBuffer++) & MSBMaskData);
+        return;
+    }
+
+    if (BytesPerPackets == 2)
+    {
+        for (Index = 0; Index < PacketRequest; ++Index)
+        {
+            RxData = *pSpiBuffer++;
+            *pRxBuffer++ = (NvU8)((RxData) & 0xFF);
+            *pRxBuffer++ = (NvU8)((RxData >> 8) & MSBMaskData);
+        }
+        return;
+    }
+
+    if (BytesPerPackets == 3)
+    {
+        for (Index = 0; Index < PacketRequest; ++Index)
+        {
+            RxData = *pSpiBuffer++;
+            *pRxBuffer++ = (NvU8)((RxData) & 0xFF);
+            *pRxBuffer++ = (NvU8)((RxData >> 8)& 0xFF);
+            *pRxBuffer++ = (NvU8)((RxData >> 16)& MSBMaskData);
+        }
+        return;
+    }
+
+    if (BytesPerPackets == 4)
+    {
+        for (Index = 0; Index < PacketRequest; ++Index)
+        {
+            RxData = *pSpiBuffer++;
+            *pRxBuffer++ = (NvU8)((RxData) & 0xFF);
+            *pRxBuffer++ = (NvU8)((RxData >> 8)& 0xFF);
+            *pRxBuffer++ = (NvU8)((RxData >> 16)& 0xFF);
+            *pRxBuffer++ = (NvU8)((RxData >> 24)& MSBMaskData);
+        }
+        return;
+    }
+}
+
+static NvError
+MasterModeReadWriteCpu(
+    NvRmSpiHandle hRmSpiSlink,
+    NvU8 *pClientRxBuffer,
+    NvU8 *pClientTxBuffer,
+    NvU32 PacketsRequested,
+    NvU32 *pPacketsTransferred,
+    NvU32 IsPackedMode,
+    NvU32 PacketBitLength)
+{
+    NvError Error = NvSuccess;
+    NvU32 CurrentTransWord;
+    NvU32 BufferOffset = 0;
+    NvU32 WordsWritten;
+    NvU32 MaxPacketPerTrans;
+    NvU32 CurrentTransPacket;
+    NvU32 PacketsPerWord;
+    NvU32 MaxPacketTrans;
+    NvBool IsPolling;
+
+    hRmSpiSlink->CurrTransInfo.BytesPerPacket = (PacketBitLength + 7)/8;
+    PacketsPerWord = (IsPackedMode)? 4/hRmSpiSlink->CurrTransInfo.BytesPerPacket:1;
+
+    hRmSpiSlink->IsUsingApbDma = NV_FALSE;
+    hRmSpiSlink->CurrTransInfo.PacketsPerWord =  PacketsPerWord;
+
+    MaxPacketPerTrans = hRmSpiSlink->CpuBufferSizeInWords*PacketsPerWord;
+    hRmSpiSlink->CurrTransInfo.TotalPacketsRemaining = PacketsRequested;
+
+    while (hRmSpiSlink->CurrTransInfo.TotalPacketsRemaining)
+    {
+        MaxPacketTrans = NV_MIN(hRmSpiSlink->CurrTransInfo.TotalPacketsRemaining, MaxPacketPerTrans);
+
+
+        // If hw does not support the nonword alined packed mode then
+        // Transfer the nearest word alligned packet first with packed mode
+        // and then the remaining packet in non packed mode.
+        if (hRmSpiSlink->HwRegs.IsNonWordAlignedPackModeSupported)
+            CurrentTransWord = (MaxPacketTrans + PacketsPerWord -1)/PacketsPerWord;
+        else
+            CurrentTransWord = (MaxPacketTrans)/PacketsPerWord;
+
+        if (!CurrentTransWord)
+        {
+            PacketsPerWord = 1;
+            CurrentTransWord = MaxPacketTrans;
+            hRmSpiSlink->hHwInterface->HwSetPacketLengthFxn(&hRmSpiSlink->HwRegs,
+                PacketBitLength, NV_FALSE);
+            hRmSpiSlink->CurrTransInfo.PacketsPerWord = PacketsPerWord;
+            IsPackedMode = NV_FALSE;
+        }
+
+        CurrentTransPacket = NV_MIN(MaxPacketTrans, CurrentTransWord*PacketsPerWord) ;
+
+        // Select polling if less number of transfer is required.
+        if (CurrentTransWord < SLINK_POLLING_HIGH_THRESOLD)
+        {
+            IsPolling = NV_TRUE;
+            hRmSpiSlink->hHwInterface->HwSetInterruptSourceFxn(&hRmSpiSlink->HwRegs,
+                    hRmSpiSlink->CurrentDirection, NV_FALSE);
+        }
+        else
+        {
+            IsPolling = NV_FALSE;
+            hRmSpiSlink->hHwInterface->HwSetInterruptSourceFxn(&hRmSpiSlink->HwRegs,
+                    hRmSpiSlink->CurrentDirection, NV_TRUE);
+        }
+        hRmSpiSlink->TxTransferStatus = NvSuccess;
+        hRmSpiSlink->RxTransferStatus = NvSuccess;
+        hRmSpiSlink->CurrTransInfo.PacketTransferred  = 0;
+
+        if (pClientRxBuffer)
+        {
+            hRmSpiSlink->CurrTransInfo.pRxBuff = hRmSpiSlink->pRxCpuBuffer;
+            hRmSpiSlink->CurrTransInfo.RxPacketsRemaining = CurrentTransPacket;
+        }
+
+        if (pClientTxBuffer)
+        {
+            MakeMasterSpiBufferFromClientBuffer(pClientTxBuffer + BufferOffset,
+                hRmSpiSlink->pTxCpuBuffer, CurrentTransPacket*hRmSpiSlink->CurrTransInfo.BytesPerPacket,
+                PacketBitLength, IsPackedMode);
+            WordsWritten = hRmSpiSlink->hHwInterface->HwWriteInTransmitFifoFxn(
+                &hRmSpiSlink->HwRegs, hRmSpiSlink->pTxCpuBuffer, CurrentTransWord);
+
+            hRmSpiSlink->CurrTransInfo.CurrPacketCount =
+                    NV_MIN(WordsWritten*PacketsPerWord, CurrentTransPacket);
+
+            hRmSpiSlink->CurrTransInfo.pTxBuff =
+                                    hRmSpiSlink->pTxCpuBuffer + WordsWritten;
+            hRmSpiSlink->CurrTransInfo.TxPacketsRemaining = CurrentTransPacket -
+                                    hRmSpiSlink->CurrTransInfo.CurrPacketCount;
+        }
+        else
+        {
+            hRmSpiSlink->CurrTransInfo.CurrPacketCount =
+                    NV_MIN(hRmSpiSlink->HwRegs.MaxWordTransfer*PacketsPerWord,
+                                        CurrentTransPacket);
+        }
+        if (!hRmSpiSlink->IsChipSelConfigured)
+        {
+            hRmSpiSlink->IsCurrentlySwBasedChipSel = 
+                hRmSpiSlink->hHwInterface->HwSetChipSelectLevelBasedOnPacketFxn(
+                    &hRmSpiSlink->HwRegs, hRmSpiSlink->CurrTransferChipSelId,
+                    !hRmSpiSlink->DeviceInfo[hRmSpiSlink->CurrTransferChipSelId].ChipSelectActiveLow,
+                    PacketsRequested, PacketsPerWord, NV_FALSE, NV_FALSE);
+            hRmSpiSlink->IsChipSelConfigured = NV_TRUE;
+        }
+        
+        hRmSpiSlink->hHwInterface->HwSetDmaTransferSizeFxn(&hRmSpiSlink->HwRegs,
+                                    hRmSpiSlink->CurrTransInfo.CurrPacketCount);
+        hRmSpiSlink->hHwInterface->HwStartTransferFxn(&hRmSpiSlink->HwRegs, NV_TRUE);
+#if NV_OAL
+        OalMasterSpiSlinkPoll(hRmSpiSlink);
+#else
+        WaitForTransferCompletion(hRmSpiSlink, NV_WAIT_INFINITE, IsPolling);
+#endif
+        Error = (hRmSpiSlink->RxTransferStatus)? hRmSpiSlink->RxTransferStatus:
+                                    hRmSpiSlink->TxTransferStatus;
+        if (Error)
+            break;
+
+        if (pClientRxBuffer)
+        {
+            MakeMasterClientBufferFromSpiBuffer(pClientRxBuffer + BufferOffset,
+                hRmSpiSlink->pRxCpuBuffer, CurrentTransPacket*hRmSpiSlink->CurrTransInfo.BytesPerPacket,
+                PacketBitLength, IsPackedMode);
+        }
+
+        BufferOffset += CurrentTransPacket*hRmSpiSlink->CurrTransInfo.BytesPerPacket;
+        hRmSpiSlink->CurrTransInfo.TotalPacketsRemaining -= CurrentTransPacket;
+    }
+
+    *pPacketsTransferred = PacketsRequested - hRmSpiSlink->CurrTransInfo.TotalPacketsRemaining;
+    return Error;
+}
+
+static NvError MasterModeReadWriteDma(
+    NvRmSpiHandle hRmSpiSlink,
+    NvU8 *pClientRxBuffer,
+    NvU8 *pClientTxBuffer,
+    NvU32 PacketsRequested,
+    NvU32 *pPacketsTransferred,
+    NvU32 IsPackedMode,
+    NvU32 PacketBitLength)
+{
+    NvError Error = NvSuccess;
+    NvU32 CurrentTransWord;
+    NvU32 BufferOffset = 0;
+    NvU32 BytesPerPacket = (PacketBitLength +7)/8;
+    NvU32 MaxPacketPerTrans;
+    NvU32 CurrentTransPacket;
+    NvU32 PacketsRemaining;
+    NvU32 PacketsPerWord = (IsPackedMode)?4/BytesPerPacket:1;
+    NvU32 TriggerLevel;
+    NvU32 MaxPacketTransPossible;
+    NvU32 PackSend = 0;
+    NvU8 *pReadReqCpuBuffer = NULL;
+    NvU8 *pWriteReqCpuBuffer = NULL;
+    NvU32 WrittenWord;
+    NvBool IsOnlyUseSWCS;
+
+    hRmSpiSlink->IsUsingApbDma = NV_TRUE;
+    hRmSpiSlink->hHwInterface->HwSetInterruptSourceFxn(&hRmSpiSlink->HwRegs,
+            hRmSpiSlink->CurrentDirection, NV_TRUE);
+
+    hRmSpiSlink->CurrTransInfo.PacketsPerWord =  PacketsPerWord;
+
+
+    MaxPacketPerTrans = (hRmSpiSlink->DmaBufferSize >> 2)*PacketsPerWord;
+    PacketsRemaining = PacketsRequested;
+    while (PacketsRemaining)
+    {
+        MaxPacketTransPossible = NV_MIN(PacketsRemaining, MaxPacketPerTrans);
+
+        // If hw does not support the nonword alined packed mode then
+        // Transfer the nearest word alligned packet first with packed mode
+        // and then the remaining packet in non packed mode.
+        if (hRmSpiSlink->HwRegs.IsNonWordAlignedPackModeSupported)
+            CurrentTransWord = (MaxPacketTransPossible + PacketsPerWord -1)/PacketsPerWord;
+        else
+            CurrentTransWord = (MaxPacketTransPossible)/PacketsPerWord;
+
+        // For the non multiple of the 4 bytes, it can do the transfer using the
+        // cpu for the remaining transfer.
+        if (!CurrentTransWord)
+        {
+            if (pClientRxBuffer)
+                pReadReqCpuBuffer = (pClientRxBuffer + BufferOffset);
+            if (pClientTxBuffer)
+                pWriteReqCpuBuffer = (pClientTxBuffer + BufferOffset);
+
+            hRmSpiSlink->hHwInterface->HwSetPacketLengthFxn(&hRmSpiSlink->HwRegs,
+                                PacketBitLength, NV_FALSE);
+            Error = MasterModeReadWriteCpu(hRmSpiSlink,  pReadReqCpuBuffer,
+                        pWriteReqCpuBuffer, MaxPacketTransPossible,
+                        &PackSend, NV_FALSE, PacketBitLength);
+            PacketsRemaining -= PackSend;
+            break;
+        }
+        if (hRmSpiSlink->HwRegs.IsNonWordAlignedPackModeSupported)
+            CurrentTransPacket = MaxPacketTransPossible;
+        else
+            CurrentTransPacket = CurrentTransWord*PacketsPerWord;
+
+        hRmSpiSlink->TxTransferStatus = NvSuccess;
+        hRmSpiSlink->RxTransferStatus = NvSuccess;
+        hRmSpiSlink->CurrTransInfo.PacketTransferred  = 0;
+        hRmSpiSlink->CurrTransInfo.CurrPacketCount = CurrentTransPacket;
+
+        if (pClientRxBuffer)
+            hRmSpiSlink->CurrTransInfo.RxPacketsRemaining = CurrentTransPacket;
+
+        if (!hRmSpiSlink->IsChipSelConfigured)
+        {
+            IsOnlyUseSWCS = (CurrentTransPacket == PacketsRequested)? NV_FALSE: NV_TRUE;
+            hRmSpiSlink->IsCurrentlySwBasedChipSel = 
+                hRmSpiSlink->hHwInterface->HwSetChipSelectLevelBasedOnPacketFxn(
+                    &hRmSpiSlink->HwRegs, hRmSpiSlink->CurrTransferChipSelId,
+                    !hRmSpiSlink->DeviceInfo[hRmSpiSlink->CurrTransferChipSelId].ChipSelectActiveLow,
+                    PacketsRequested, PacketsPerWord, NV_TRUE, IsOnlyUseSWCS);
+            hRmSpiSlink->IsChipSelConfigured = NV_TRUE;
+        }
+
+        hRmSpiSlink->hHwInterface->HwSetDmaTransferSizeFxn(&hRmSpiSlink->HwRegs,
+                                            CurrentTransPacket);
+
+        TriggerLevel = (CurrentTransWord  & 0x3)? 4: 16;
+        hRmSpiSlink->hHwInterface->HwSetTriggerLevelFxn(&hRmSpiSlink->HwRegs,
+                                            SerialHwFifo_Both , TriggerLevel);
+
+        if (pClientTxBuffer)
+        {
+            MakeMasterSpiBufferFromClientBuffer(pClientTxBuffer + BufferOffset,
+                        hRmSpiSlink->pTxDmaBuffer, CurrentTransPacket*BytesPerPacket,
+                        PacketBitLength, IsPackedMode);
+            hRmSpiSlink->CurrTransInfo.pTxBuff = hRmSpiSlink->pTxDmaBuffer;
+            hRmSpiSlink->TxDmaReq.TransferSize = CurrentTransWord *4;
+
+            // If transfer word is more than fifo size the use the dma
+            // otherwise direct write into the fifo.
+            if (CurrentTransWord >= hRmSpiSlink->HwRegs.MaxWordTransfer)
+            {
+                Error = NvRmDmaStartDmaTransfer(hRmSpiSlink->hRmTxDma,
+                                &hRmSpiSlink->TxDmaReq, NvRmDmaDirection_Forward, 0, NULL);
+                // Wait till fifo full if the transfer size is more than fifo size
+                if (!Error)
+                {
+                    do
+                    {
+                        if (hRmSpiSlink->hHwInterface->HwIsTransmitFifoFull(&hRmSpiSlink->HwRegs))
+                            break;
+                    } while(1);
+                }
+            }
+            else
+            {
+                WrittenWord = hRmSpiSlink->hHwInterface->HwWriteInTransmitFifoFxn(
+                                            &hRmSpiSlink->HwRegs,
+                                                hRmSpiSlink->CurrTransInfo.pTxBuff,
+                                                CurrentTransWord);
+                if (WrittenWord !=  CurrentTransWord)
+                {
+                    NV_ASSERT(WrittenWord == CurrentTransWord);
+                    Error = NvError_Timeout;
+                }
+            }
+        }
+
+        if ((!Error) && (pClientRxBuffer))
+        {
+            hRmSpiSlink->RxDmaReq.TransferSize = CurrentTransWord *4;
+            Error = NvRmDmaStartDmaTransfer(hRmSpiSlink->hRmRxDma, &hRmSpiSlink->RxDmaReq,
+                                        NvRmDmaDirection_Forward, 0, NULL);
+            if ((Error) && (pClientTxBuffer))
+                NvRmDmaAbort(hRmSpiSlink->hRmTxDma);
+        }
+
+        if (!Error)
+            hRmSpiSlink->hHwInterface->HwStartTransferFxn(&hRmSpiSlink->HwRegs, NV_TRUE);
+
+        if (!Error)
+            WaitForTransferCompletion(hRmSpiSlink, NV_WAIT_INFINITE, NV_FALSE);
+
+        Error = (hRmSpiSlink->RxTransferStatus)? hRmSpiSlink->RxTransferStatus:
+                                    hRmSpiSlink->TxTransferStatus;
+        if (Error)
+        {
+            if (pClientRxBuffer)
+                NvRmDmaAbort(hRmSpiSlink->hRmRxDma);
+            if (pClientTxBuffer)
+                NvRmDmaAbort(hRmSpiSlink->hRmTxDma);
+            break;
+        }
+        if (pClientRxBuffer)
+        {
+            MakeMasterClientBufferFromSpiBuffer(pClientRxBuffer + BufferOffset,
+                    hRmSpiSlink->pRxDmaBuffer, CurrentTransPacket*BytesPerPacket,
+                    PacketBitLength, IsPackedMode);
+        }
+
+        BufferOffset += CurrentTransPacket*BytesPerPacket;
+        PacketsRemaining -= CurrentTransPacket;
+    }
+
+    hRmSpiSlink->hHwInterface->HwSetDataFlowFxn(&hRmSpiSlink->HwRegs,
+                                    hRmSpiSlink->CurrentDirection, NV_FALSE);
+    hRmSpiSlink->hHwInterface->HwSetInterruptSourceFxn(&hRmSpiSlink->HwRegs,
+                                    hRmSpiSlink->CurrentDirection, NV_FALSE);
+
+    *pPacketsTransferred = PacketsRequested - PacketsRemaining;
+    return Error;
+}
+static NvError SlaveModeSpiStartReadWriteCpu(
+    NvRmSpiHandle hRmSpiSlink,
+    NvBool IsReadTransfer,
+    NvU8 *pClientTxBuffer,
+    NvU32 PacketsRequested,
+    NvU32 IsPackedMode,
+    NvU32 PacketBitLength)
+{
+    NvError Error = NvSuccess;
+    NvU32 BytesPerPacket;
+    NvU32 WordsWritten;
+    NvU32 PacketsPerWord;
+    NvU32 TotalWordsRequested;
+
+    BytesPerPacket = (PacketBitLength + 7)/8;
+    PacketsPerWord = (IsPackedMode)? 4/BytesPerPacket: 1;
+    TotalWordsRequested = (PacketsRequested + PacketsPerWord -1)/PacketsPerWord;
+
+    hRmSpiSlink->IsUsingApbDma = NV_FALSE;
+
+    hRmSpiSlink->hHwInterface->HwSetPacketLengthFxn(&hRmSpiSlink->HwRegs,
+                        PacketBitLength, IsPackedMode);
+
+    hRmSpiSlink->CurrTransInfo.PacketsPerWord =  PacketsPerWord;
+    hRmSpiSlink->CurrTransInfo.BytesPerPacket =  BytesPerPacket;
+    hRmSpiSlink->CurrTransInfo.PacketBitLength = PacketBitLength;
+    hRmSpiSlink->CurrTransInfo.IsPackedMode =  IsPackedMode;
+
+    hRmSpiSlink->TxTransferStatus = NvSuccess;
+    hRmSpiSlink->RxTransferStatus = NvSuccess;
+
+    hRmSpiSlink->CurrTransInfo.PacketTransferred  = 0;
+
+    hRmSpiSlink->CurrTransInfo.pRxBuff =
+                            (IsReadTransfer)? hRmSpiSlink->pRxCpuBuffer: NULL;
+    hRmSpiSlink->CurrTransInfo.RxPacketsRemaining =
+                            (IsReadTransfer)? PacketsRequested: 0;
+
+    hRmSpiSlink->CurrTransInfo.PacketRequested = PacketsRequested;
+
+    hRmSpiSlink->CurrTransInfo.pTxBuff = NULL;
+    hRmSpiSlink->CurrTransInfo.TxPacketsRemaining = 0;
+
+    WordsWritten = hRmSpiSlink->HwRegs.MaxWordTransfer;
+
+    if (pClientTxBuffer)
+    {
+        MakeSlaveSpiBufferFromClientBuffer(pClientTxBuffer, hRmSpiSlink->pTxCpuBuffer,
+                    PacketsRequested*BytesPerPacket, PacketBitLength,
+                    IsPackedMode);
+        WordsWritten = hRmSpiSlink->hHwInterface->HwWriteInTransmitFifoFxn(
+                        &hRmSpiSlink->HwRegs, hRmSpiSlink->pTxCpuBuffer,
+                        TotalWordsRequested);
+
+        hRmSpiSlink->CurrTransInfo.CurrPacketCount =
+                NV_MIN(WordsWritten*PacketsPerWord, PacketsRequested);
+        hRmSpiSlink->CurrTransInfo.pTxBuff =
+                                    hRmSpiSlink->pTxCpuBuffer + WordsWritten;
+        hRmSpiSlink->CurrTransInfo.TxPacketsRemaining = PacketsRequested -
+                                hRmSpiSlink->CurrTransInfo.CurrPacketCount;
+    }
+    else
+    {
+        hRmSpiSlink->CurrTransInfo.CurrPacketCount =
+                    NV_MIN(WordsWritten*PacketsPerWord, PacketsRequested);
+    }
+
+    hRmSpiSlink->hHwInterface->HwSetDmaTransferSizeFxn(&hRmSpiSlink->HwRegs,
+                    hRmSpiSlink->CurrTransInfo.CurrPacketCount);
+
+    hRmSpiSlink->hHwInterface->HwStartTransferFxn(&hRmSpiSlink->HwRegs, NV_TRUE);
+
+    return Error;
+}
+
+static NvError SlaveModeSpiStartReadWriteDma(
+    NvRmSpiHandle hRmSpiSlink,
+    NvBool IsReadTransfer,
+    NvU8 *pClientTxBuffer,
+    NvU32 PacketsRequested,
+    NvU32 IsPackedMode,
+    NvU32 PacketBitLength)
+{
+    NvError Error = NvSuccess;
+    NvU32 CurrentTransWord;
+    NvU32 BytesPerPacket;
+    NvU32 CurrentTransPacket;
+    NvU32 PacketsPerWord;
+    NvU32 TriggerLevel;
+    NvU32 TotalWordsRequested;
+    NvU32 NewBufferSize;
+
+    BytesPerPacket = (PacketBitLength + 7)/8;
+    PacketsPerWord = (IsPackedMode)? 4/BytesPerPacket: 1;
+    TotalWordsRequested = (PacketsRequested + PacketsPerWord -1)/PacketsPerWord;
+
+    hRmSpiSlink->IsUsingApbDma = NV_TRUE;
+
+    // Create the buffer if the required size of the buffer is not available.
+    if (hRmSpiSlink->DmaBufferSize < (TotalWordsRequested*4))
+    {
+        DestroyDmaTransferBuffer(hRmSpiSlink->hRmMemory,
+                hRmSpiSlink->pRxDmaBuffer, hRmSpiSlink->pTxDmaBuffer,
+                hRmSpiSlink->DmaBufferSize);
+        hRmSpiSlink->hRmMemory = NULL;
+        hRmSpiSlink->pRxDmaBuffer = NULL;
+        hRmSpiSlink->DmaRxBuffPhysAdd = 0;
+
+        // Better to findout the neearest 2powern
+        NewBufferSize = NV_MAX(hRmSpiSlink->DmaBufferSize, (TotalWordsRequested*4));
+        Error = CreateDmaTransferBuffer(hRmSpiSlink->hDevice, &hRmSpiSlink->hRmMemory,
+                &hRmSpiSlink->DmaRxBuffPhysAdd, (void **)&hRmSpiSlink->pRxDmaBuffer,
+                &hRmSpiSlink->DmaTxBuffPhysAdd, (void **)&hRmSpiSlink->pTxDmaBuffer,
+                NewBufferSize);
+
+        if (Error)
+        {
+            hRmSpiSlink->DmaBufferSize = 0;
+            return Error;
+        }
+        hRmSpiSlink->RxDmaReq.DestinationBufferPhyAddress = hRmSpiSlink->DmaRxBuffPhysAdd;
+        hRmSpiSlink->TxDmaReq.SourceBufferPhyAddress = hRmSpiSlink->DmaTxBuffPhysAdd;
+        hRmSpiSlink->DmaBufferSize = NewBufferSize;
+    }
+
+    hRmSpiSlink->CurrTransInfo.PacketsPerWord =  PacketsPerWord;
+    hRmSpiSlink->CurrTransInfo.BytesPerPacket =  BytesPerPacket;
+    hRmSpiSlink->CurrTransInfo.PacketBitLength = PacketBitLength;
+    hRmSpiSlink->CurrTransInfo.IsPackedMode =  IsPackedMode;
+
+    CurrentTransPacket = NV_MIN((TotalWordsRequested*PacketsPerWord), PacketsRequested);
+
+    hRmSpiSlink->CurrTransInfo.PacketTransferred  = 0;
+    hRmSpiSlink->CurrTransInfo.RxPacketsRemaining = 0;
+    hRmSpiSlink->CurrTransInfo.pRxBuff = NULL;
+    hRmSpiSlink->CurrTransInfo.CurrPacketCount = CurrentTransPacket;
+    hRmSpiSlink->CurrTransInfo.PacketRequested = CurrentTransPacket;
+    hRmSpiSlink->TxTransferStatus = NvSuccess;
+    hRmSpiSlink->RxTransferStatus = NvSuccess;
+
+    hRmSpiSlink->CurrTransInfo.pTxBuff = NULL;
+
+    CurrentTransWord = (CurrentTransPacket + PacketsPerWord -1)/PacketsPerWord;
+
+    TriggerLevel = (CurrentTransWord  & 0x3)? 4: 16;
+    hRmSpiSlink->hHwInterface->HwSetTriggerLevelFxn(&hRmSpiSlink->HwRegs,
+                            SerialHwFifo_Both , TriggerLevel);
+
+    hRmSpiSlink->hHwInterface->HwSetDmaTransferSizeFxn(&hRmSpiSlink->HwRegs,
+                                    CurrentTransPacket);
+    if (pClientTxBuffer)
+    {
+        MakeSlaveSpiBufferFromClientBuffer(pClientTxBuffer, hRmSpiSlink->pTxDmaBuffer,
+                    CurrentTransPacket*BytesPerPacket,
+                    PacketBitLength, IsPackedMode);
+        hRmSpiSlink->CurrTransInfo.pTxBuff = hRmSpiSlink->pTxDmaBuffer;
+        hRmSpiSlink->TxDmaReq.TransferSize = CurrentTransWord *4;
+        Error = NvRmDmaStartDmaTransfer(hRmSpiSlink->hRmTxDma, &hRmSpiSlink->TxDmaReq,
+                                        NvRmDmaDirection_Forward, 0, NULL);
+        do
+        {
+            if (hRmSpiSlink->hHwInterface->HwIsTransmitFifoFull(&hRmSpiSlink->HwRegs))
+                break;
+        } while(1);
+    }
+
+    if ((!Error) && (IsReadTransfer))
+    {
+        hRmSpiSlink->RxDmaReq.TransferSize = CurrentTransWord *4;
+        hRmSpiSlink->CurrTransInfo.RxPacketsRemaining = CurrentTransPacket;
+        hRmSpiSlink->CurrTransInfo.pRxBuff = hRmSpiSlink->pRxDmaBuffer;
+
+        Error = NvRmDmaStartDmaTransfer(hRmSpiSlink->hRmRxDma, &hRmSpiSlink->RxDmaReq,
+                        NvRmDmaDirection_Forward, 0, NULL);
+        if ((Error) && (pClientTxBuffer))
+            NvRmDmaAbort(hRmSpiSlink->hRmTxDma);
+    }
+
+    if (!Error)
+        hRmSpiSlink->hHwInterface->HwStartTransferFxn(&hRmSpiSlink->HwRegs, NV_TRUE);
+    return Error;
+}
+
+static NvError SlaveModeSpiCompleteReadWrite(
+    NvRmSpiHandle hRmSpiSlink,
+    NvU8 *pClientRxBuffer,
+    NvU32 *pBytesTransferred,
+    NvU32 TimeoutMs)
+{
+    NvError Error = NvSuccess;
+    NvU32 TransferdPacket;
+    NvU32 ReqSizeInBytes;
+    NvU32 *pRxBuffer = NULL;
+
+    Error = WaitForTransferCompletion(hRmSpiSlink, TimeoutMs, NV_FALSE);
+    if (Error == NvError_Timeout)
+    {
+        TransferdPacket = hRmSpiSlink->CurrTransInfo.PacketTransferred;
+    }
+    else
+    {
+        Error = (hRmSpiSlink->RxTransferStatus)? hRmSpiSlink->RxTransferStatus:
+                                    hRmSpiSlink->TxTransferStatus;
+        if (Error)
+            TransferdPacket = hRmSpiSlink->CurrTransInfo.PacketTransferred;
+        else
+            TransferdPacket = hRmSpiSlink->CurrTransInfo.PacketRequested;
+    }
+    ReqSizeInBytes = NV_MIN(TransferdPacket, hRmSpiSlink->CurrTransInfo.PacketRequested)
+                            *hRmSpiSlink->CurrTransInfo.BytesPerPacket;
+
+    if (pClientRxBuffer)
+    {
+        pRxBuffer = (hRmSpiSlink->IsUsingApbDma)?hRmSpiSlink->pRxDmaBuffer:
+                            hRmSpiSlink->pRxCpuBuffer;
+        MakeSlaveClientBufferFromSpiBuffer(pClientRxBuffer,
+                        pRxBuffer, ReqSizeInBytes,
+                        hRmSpiSlink->CurrTransInfo.PacketBitLength,
+                        hRmSpiSlink->CurrTransInfo.IsPackedMode);
+    }
+
+    *pBytesTransferred = ReqSizeInBytes;
+    hRmSpiSlink->hHwInterface->HwSetInterruptSourceFxn(&hRmSpiSlink->HwRegs,
+                            hRmSpiSlink->CurrentDirection, NV_FALSE);
+    hRmSpiSlink->hHwInterface->HwSetDataFlowFxn(&hRmSpiSlink->HwRegs,
+                            hRmSpiSlink->CurrentDirection, NV_FALSE);
+    hRmSpiSlink->CurrentDirection = SerialHwDataFlow_None;
+    return Error;
+}
+
+
+static void
+InitSlinkInterface(
+    NvRmDeviceHandle hDevice,
+    HwInterface *pSlinkInterface)
+{
+    static SlinkCapabilities s_SpiCap[2];
+    SlinkCapabilities *pSpiCap = NULL;
+    static NvRmModuleCapability s_SpiCapList[] =
+        {
+            {1, 0, 0, &s_SpiCap[0]}, // AP15 version 1.0
+            {1, 1, 0, &s_SpiCap[1]}, // AP20 version 1.1
+        };
+
+    // (AP15) version 1.0
+    s_SpiCap[0].MajorVersion = 1;
+    s_SpiCap[0].MinorVersion = 0;
+
+    // (AP20) version 1.1
+    s_SpiCap[1].MajorVersion = 1;
+    s_SpiCap[1].MinorVersion = 1;
+
+    NV_ASSERT_SUCCESS(NvRmModuleGetCapabilities(hDevice, NVRM_MODULE_ID(NvRmModuleID_Slink, 0),
+                        s_SpiCapList, NV_ARRAY_SIZE(s_SpiCapList), (void**)&(pSpiCap)));
+
+    NvRmPrivSpiSlinkInitSlinkInterface(&s_SlinkHwInterface);
+    if ((pSpiCap->MajorVersion == 1) && (pSpiCap->MinorVersion == 0))
+    {
+        NvRmPrivSpiSlinkInitSlinkInterface_v1_0(&s_SlinkHwInterface);
+    }
+    else // 1.1
+    {
+        NvRmPrivSpiSlinkInitSlinkInterface_v1_1(&s_SlinkHwInterface);
+    }
+}
+
+/**
+ * Initialize the spi info structure.
+ * Thread safety: Caller responsibity.
+ */
+NvError NvRmPrivSpiSlinkInit(NvRmDeviceHandle hDevice)
+{
+    NvError e;
+    NvU32 Index;
+
+    NV_ASSERT(NvRmModuleGetNumInstances(hDevice, NvRmModuleID_Spi) <= MAX_SPI_CONTROLLERS);
+    NV_ASSERT(NvRmModuleGetNumInstances(hDevice, NvRmModuleID_Slink) <= MAX_SLINK_CONTROLLERS);
+
+    NvRmPrivSpiSlinkInitSpiInterface(&s_SpiHwInterface);
+    InitSlinkInterface(hDevice, &s_SlinkHwInterface);
+
+    // Initialize all the parameters.
+    s_SpiSlinkInfo.hDevice = hDevice;
+
+    for (Index = 0; Index < MAX_SPI_SLINK_INSTANCE; ++Index)
+        s_SpiSlinkInfo.hSpiSlinkChannelList[Index] = NULL;
+
+    // Create the mutex to access the spi information.
+    NV_CHECK_ERROR(NvOsMutexCreate(&s_SpiSlinkInfo.hChannelAccessMutex));
+    return NvSuccess;
+}
+
+/**
+ * Destroy all the spi struture information. It frees all the allocated resource.
+ * Thread safety: Caller responsibity.
+ */
+void NvRmPrivSpiSlinkDeInit(void)
+{
+    NvU32 Index;
+
+    // Free all allocations.
+    NvOsMutexLock(s_SpiSlinkInfo.hChannelAccessMutex);
+    for (Index = 0; Index < MAX_SPI_SLINK_INSTANCE; ++Index)
+    {
+        if (s_SpiSlinkInfo.hSpiSlinkChannelList[Index] != NULL)
+        {
+            DestroySpiSlinkChannelHandle(s_SpiSlinkInfo.hSpiSlinkChannelList[Index]);
+            s_SpiSlinkInfo.hSpiSlinkChannelList[Index] = NULL;
+        }
+    }
+    NvOsMutexUnlock(s_SpiSlinkInfo.hChannelAccessMutex);
+
+    NvOsMutexDestroy(s_SpiSlinkInfo.hChannelAccessMutex);
+    s_SpiSlinkInfo.hChannelAccessMutex = NULL;
+    s_SpiSlinkInfo.hDevice = NULL;
+}
+
+/**
+ * Open the handle for the spi.
+ */
+NvError
+NvRmSpiOpen(
+    NvRmDeviceHandle hRmDevice,
+    NvU32 IoModule,
+    NvU32 InstanceId,
+    NvBool IsMasterMode,
+    NvRmSpiHandle * phRmSpi)
+{
+    NvError Error = NvSuccess;
+    NvRmSpiHandle hRmSpiSlink = NULL;
+    NvU32 ContInstanceId;
+    NvBool IsSpiChannel;
+
+    NV_ASSERT(phRmSpi);
+    NV_ASSERT(hRmDevice);
+
+    *phRmSpi = NULL;
+
+    IsSpiChannel = (IoModule == NvOdmIoModule_Sflash)? NV_TRUE: NV_FALSE;
+
+    // SPI controller does not support the slave mode
+    if ((IsSpiChannel) && (!IsMasterMode))
+        return NvError_NotSupported;
+
+    // 0 to (MAX_SPI_CONTROLLERS-1) will be the spi handles and then
+    // slink handles.
+    ContInstanceId = (IsSpiChannel)? InstanceId: (MAX_SPI_CONTROLLERS + InstanceId);
+
+    // Lock the spi info mutex access.
+    NvOsMutexLock(s_SpiSlinkInfo.hChannelAccessMutex);
+
+    if (s_SpiSlinkInfo.hSpiSlinkChannelList[ContInstanceId] == NULL)
+    {
+        Error = CreateSpiSlinkChannelHandle(hRmDevice, IsSpiChannel,
+                    InstanceId, IsMasterMode, &hRmSpiSlink);
+        if (Error)
+            goto FuncExit;
+    }
+    else
+    {
+        // If the handle is not in master mode then not sharing across the
+        // client.
+        if (IsMasterMode)
+        {
+            hRmSpiSlink = s_SpiSlinkInfo.hSpiSlinkChannelList[ContInstanceId];
+            if (hRmSpiSlink->IsMasterMode)
+            {
+                hRmSpiSlink->OpenCount++;
+            }
+            else
+            {
+                Error = NvError_AlreadyAllocated;
+                goto FuncExit;
+            }
+        }
+        else
+        {
+            Error = NvError_AlreadyAllocated;
+            goto FuncExit;
+        }
+    }
+    *phRmSpi = hRmSpiSlink;
+
+FuncExit:
+    NvOsMutexUnlock(s_SpiSlinkInfo.hChannelAccessMutex);
+    return Error;
+}
+
+/**
+ * Close the spi handle.
+ */
+void NvRmSpiClose(NvRmSpiHandle hRmSpi)
+{
+    if (hRmSpi)
+    {
+        NvOsMutexLock(s_SpiSlinkInfo.hChannelAccessMutex);
+        hRmSpi->OpenCount--;
+        if (!hRmSpi->OpenCount)
+            DestroySpiSlinkChannelHandle(hRmSpi);
+
+        NvOsMutexUnlock(s_SpiSlinkInfo.hChannelAccessMutex);
+    }
+}
+
+void NvRmSpiMultipleTransactions(
+    NvRmSpiHandle hRmSpi,
+    NvU32 SpiPinMap,
+    NvU32 ChipSelectId,
+    NvU32 ClockSpeedInKHz,
+    NvU32 PacketSizeInBits,
+    NvRmSpiTransactionInfo *t,
+    NvU32 NumOfTransactions)
+{
+    NvError Error = NvSuccess;
+    NvBool IsPackedMode;
+    NvU32 BytesPerPacket;
+    NvU32 PacketsTransferred;
+    NvU32 PacketsPerWord;
+    NvU32 TotalPacketsRequsted;
+    NvU32 TotalWordsRequested;
+    NvU32 i;
+    NvRmDmaModuleID DmaModuleId;
+    NvRmSpiTransactionInfo *pTrans = t;
+    NvU32 TotalTransByte = 0;
+
+    NV_ASSERT(hRmSpi);
+    NV_ASSERT((PacketSizeInBits > 0) && (PacketSizeInBits <= 32));
+    NV_ASSERT(hRmSpi->IsMasterMode);
+
+    // Chip select should be supported by the odm.
+    NV_ASSERT(hRmSpi->IsChipSelSupported[ChipSelectId]);
+
+    // Proper spi pin map if it is multiplexed otherwise 0.
+    NV_ASSERT(((SpiPinMap) && (hRmSpi->SpiPinMap == NvOdmSpiPinMap_Multiplexed)) ||
+               ((!SpiPinMap) && (hRmSpi->SpiPinMap != NvOdmSpiPinMap_Multiplexed)));
+
+    // Select Packed mode for the 8/16 bit length.
+    BytesPerPacket = (PacketSizeInBits + 7)/8;
+    IsPackedMode = ((PacketSizeInBits == 8) || ((PacketSizeInBits == 16)));
+    PacketsPerWord =  (IsPackedMode)? 4/BytesPerPacket: 1;
+
+    // Lock the channel access by other client till this client finishes the ops
+    NvOsMutexLock(hRmSpi->hChannelAccessMutex);
+
+    hRmSpi->CurrTransferChipSelId = ChipSelectId;
+    
+    // Enable Power/Clock.
+    Error = SetPowerControl(hRmSpi, NV_TRUE);
+    if (Error != NvSuccess)
+        goto cleanup;
+
+    // Boost frequency if the total bytes requetsed is more than thresold.
+    for (i=0; i< NumOfTransactions; i++, pTrans++)
+    {
+        if (!((pTrans->rxBuffer || pTrans->txBuffer) && pTrans->len))
+            continue;
+        TotalTransByte += pTrans->len;
+    }
+
+    BoostFrequency(hRmSpi, NV_TRUE, TotalTransByte);
+
+    hRmSpi->CurrTransInfo.PacketsPerWord = PacketsPerWord;
+    if (SpiPinMap)
+    {
+        NvRmPinMuxConfigSelect(hRmSpi->hDevice,hRmSpi->RmIoModuleId,
+                                                hRmSpi->InstanceId, SpiPinMap);
+        NvRmPinMuxConfigSetTristate(hRmSpi->hDevice,hRmSpi->RmIoModuleId,
+                                        hRmSpi->InstanceId, SpiPinMap, NV_FALSE);
+    }
+    else
+    {
+        if (hRmSpi->IsIdleSignalTristate)
+            NvRmPinMuxConfigSetTristate(hRmSpi->hDevice,hRmSpi->RmIoModuleId,
+                hRmSpi->InstanceId, hRmSpi->SpiPinMap, NV_FALSE);
+    }
+
+    if (!Error)
+        Error = SetChipSelectSignalLevel(hRmSpi, ChipSelectId, ClockSpeedInKHz,
+                       NV_TRUE, NV_TRUE);
+    if (Error)
+        goto cleanup;
+
+    hRmSpi->hHwInterface->HwSetPacketLengthFxn(&hRmSpi->HwRegs,
+        PacketSizeInBits, IsPackedMode);
+
+    for (i=0; i< NumOfTransactions; i++, t++)
+    {
+        if (!((t->rxBuffer || t->txBuffer) && t->len))
+            continue;
+
+        hRmSpi->CurrTransInfo.pRxBuff = NULL;
+        hRmSpi->CurrTransInfo.RxPacketsRemaining = 0;
+        hRmSpi->CurrTransInfo.pTxBuff = NULL;
+        hRmSpi->CurrTransInfo.TxPacketsRemaining = 0;
+
+        /* If not packed mode, packet == word */
+        TotalPacketsRequsted = t->len/BytesPerPacket;
+        TotalWordsRequested = (TotalPacketsRequsted + PacketsPerWord -1)/PacketsPerWord;
+        NV_ASSERT((t->len % BytesPerPacket) == 0);
+        NV_ASSERT(TotalPacketsRequsted);
+
+        // Allocate the dma here if transaction size is more than cpu based
+        // transaction thresold.
+        if ((TotalWordsRequested > hRmSpi->HwRegs.MaxWordTransfer) &&
+                (hRmSpi->DmaBufferSize) &&
+                (!hRmSpi->IsApbDmaAllocated))
+        {
+            hRmSpi->TransCountFromLastDmaUsage = 0;
+            hRmSpi->IsApbDmaAllocated = NV_TRUE;
+            DmaModuleId = (hRmSpi->IsSpiChannel)?NvRmDmaModuleID_Spi: NvRmDmaModuleID_Slink;
+            Error = NvRmDmaAllocate(hRmSpi->hDevice, &hRmSpi->hRmRxDma,
+                             NV_FALSE, NvRmDmaPriority_High, DmaModuleId,
+                             hRmSpi->InstanceId);
+            if (!Error)
+            {
+                Error = NvRmDmaAllocate(hRmSpi->hDevice, &hRmSpi->hRmTxDma,
+                                 NV_FALSE, NvRmDmaPriority_High, DmaModuleId,
+                                 hRmSpi->InstanceId);
+                if (Error)
+                    NvRmDmaFree(hRmSpi->hRmRxDma);
+            }
+            if (Error)
+            {
+                hRmSpi->hRmRxDma = NULL;
+                hRmSpi->hRmTxDma = NULL;
+                hRmSpi->IsApbDmaAllocated = NV_FALSE;
+                Error = NvSuccess;
+            }
+        }
+
+        hRmSpi->CurrentDirection = SerialHwDataFlow_None;
+        if (t->txBuffer)
+            hRmSpi->CurrentDirection |= SerialHwDataFlow_Tx;
+        if (t->rxBuffer)
+            hRmSpi->CurrentDirection |= SerialHwDataFlow_Rx;
+        hRmSpi->hHwInterface->HwSetDataFlowFxn(&hRmSpi->HwRegs,
+            hRmSpi->CurrentDirection, NV_TRUE);
+
+        if ((!hRmSpi->IsApbDmaAllocated) ||
+            (TotalWordsRequested <= hRmSpi->HwRegs.MaxWordTransfer))
+        {
+            hRmSpi->TransCountFromLastDmaUsage++;
+            Error = MasterModeReadWriteCpu(hRmSpi, t->rxBuffer, t->txBuffer,
+                TotalPacketsRequsted, &PacketsTransferred,
+                IsPackedMode, PacketSizeInBits);
+        }
+        else
+        {
+            hRmSpi->TransCountFromLastDmaUsage = 0;
+            Error = MasterModeReadWriteDma(hRmSpi, t->rxBuffer, t->txBuffer,
+                TotalPacketsRequsted, &PacketsTransferred,
+                IsPackedMode, PacketSizeInBits);
+        }
+        hRmSpi->hHwInterface->HwSetDataFlowFxn(&hRmSpi->HwRegs,
+            hRmSpi->CurrentDirection, NV_FALSE);
+    }
+    hRmSpi->CurrentDirection = SerialHwDataFlow_None;
+    (void)SetChipSelectSignalLevel(hRmSpi, ChipSelectId, ClockSpeedInKHz,
+                NV_FALSE, NV_TRUE);
+
+cleanup:
+
+    //  Re-tristate multi-plexed controllers, and re-multiplex the controller.
+    if (SpiPinMap)
+    {
+        NvRmPinMuxConfigSetTristate(hRmSpi->hDevice,hRmSpi->RmIoModuleId,
+            hRmSpi->InstanceId, SpiPinMap, NV_TRUE);
+
+        NvRmPinMuxConfigSelect(hRmSpi->hDevice,hRmSpi->RmIoModuleId,
+            hRmSpi->InstanceId, hRmSpi->SpiPinMap);
+    }
+    else
+    {
+        if (hRmSpi->IsIdleSignalTristate)
+            NvRmPinMuxConfigSetTristate(hRmSpi->hDevice,hRmSpi->RmIoModuleId,
+                hRmSpi->InstanceId, hRmSpi->SpiPinMap, NV_TRUE);
+    }
+    if ((hRmSpi->IsApbDmaAllocated) &&
+            (hRmSpi->TransCountFromLastDmaUsage > MAX_DMA_HOLD_TIME))
+    {
+        NvRmDmaFree(hRmSpi->hRmRxDma);
+        NvRmDmaFree(hRmSpi->hRmTxDma);
+        hRmSpi->hRmRxDma = NULL;
+        hRmSpi->hRmTxDma = NULL;
+        hRmSpi->IsApbDmaAllocated = NV_FALSE;
+    }
+
+    BoostFrequency(hRmSpi, NV_FALSE, 0);
+    SetPowerControl(hRmSpi, NV_FALSE);
+    NvOsMutexUnlock(hRmSpi->hChannelAccessMutex);
+    NV_ASSERT(Error == NvSuccess);
+}
+
+/**
+ * Perform the data transfer.
+ */
+void NvRmSpiTransaction(
+    NvRmSpiHandle hRmSpi,
+    NvU32 SpiPinMap,
+    NvU32 ChipSelectId,
+    NvU32 ClockSpeedInKHz,
+    NvU8 *pReadBuffer,
+    NvU8 *pWriteBuffer,
+    NvU32 BytesRequested,
+    NvU32 PacketSizeInBits)
+{
+    NvError Error = NvSuccess;
+    NvBool IsPackedMode;
+    NvU32 BytesPerPackets;
+    NvU32 PacketsTransferred;
+    NvU32 PacketsPerWord;
+    NvU32 TotalPacketsRequsted;
+    NvU32 TotalWordsRequested;
+    NvRmDmaModuleID DmaModuleId;
+
+    NV_ASSERT(hRmSpi);
+    NV_ASSERT(pReadBuffer || pWriteBuffer);
+
+    // Packet size should be 1 to 32..
+    NV_ASSERT((PacketSizeInBits > 0) && (PacketSizeInBits <= 32));
+
+    NV_ASSERT(hRmSpi->IsMasterMode);
+
+    // Bytes requested should be  multiple of of bytes per packets.
+    BytesPerPackets = (PacketSizeInBits + 7)/8;
+    TotalPacketsRequsted = BytesRequested/BytesPerPackets;
+    NV_ASSERT((BytesRequested % BytesPerPackets) == 0);
+    NV_ASSERT(TotalPacketsRequsted);
+
+    // Chip select should be supported by the odm.
+    NV_ASSERT(hRmSpi->IsChipSelSupported[ChipSelectId]);
+
+    // Proper spi pin map if it is multiplexed otherwise 0.
+    NV_ASSERT(((SpiPinMap) && (hRmSpi->SpiPinMap == NvOdmSpiPinMap_Multiplexed)) ||
+               ((!SpiPinMap) && (hRmSpi->SpiPinMap != NvOdmSpiPinMap_Multiplexed)));
+
+    // Select Packed mode for the 8/16 bit length.
+    IsPackedMode = ((PacketSizeInBits == 8) || ((PacketSizeInBits == 16)));
+    PacketsPerWord =  (IsPackedMode)? 4/BytesPerPackets: 1;
+    TotalWordsRequested = (TotalPacketsRequsted + PacketsPerWord -1)/PacketsPerWord;
+
+#if !NV_OAL
+    // Lock the channel access by other client till this client finishes the ops
+    NvOsMutexLock(hRmSpi->hChannelAccessMutex);
+
+    hRmSpi->CurrTransferChipSelId = ChipSelectId;
+    // Enable Power/Clock.
+    Error = SetPowerControl(hRmSpi, NV_TRUE);
+    if (Error != NvSuccess)
+        goto cleanup;
+    BoostFrequency(hRmSpi, NV_TRUE, BytesRequested);
+
+#else
+    hRmSpi->CurrTransferChipSelId = ChipSelectId;
+#endif
+    hRmSpi->CurrTransInfo.PacketsPerWord = PacketsPerWord;
+
+    // Enable the transmit if the Tx buffer is supplied.
+    hRmSpi->CurrentDirection = (pWriteBuffer)?SerialHwDataFlow_Tx: SerialHwDataFlow_None;
+
+    // Enable the receive if the Rx buffer is supplied.
+    if (pReadBuffer)
+        hRmSpi->CurrentDirection |= SerialHwDataFlow_Rx;
+
+    if (SpiPinMap)
+    {
+
+        NvRmPinMuxConfigSelect(hRmSpi->hDevice,hRmSpi->RmIoModuleId,
+                                                hRmSpi->InstanceId, SpiPinMap);
+
+        NvRmPinMuxConfigSetTristate(hRmSpi->hDevice,hRmSpi->RmIoModuleId,
+                                        hRmSpi->InstanceId, SpiPinMap, NV_FALSE);
+    }
+    else
+    {
+        if (hRmSpi->IsIdleSignalTristate)
+            NvRmPinMuxConfigSetTristate(hRmSpi->hDevice,hRmSpi->RmIoModuleId,
+                hRmSpi->InstanceId, hRmSpi->SpiPinMap, NV_FALSE);
+    }
+
+    hRmSpi->CurrTransInfo.pRxBuff = NULL;
+    hRmSpi->CurrTransInfo.RxPacketsRemaining = 0;
+    hRmSpi->CurrTransInfo.pTxBuff = NULL;
+    hRmSpi->CurrTransInfo.TxPacketsRemaining = 0;
+
+    TotalWordsRequested = (TotalPacketsRequsted + PacketsPerWord -1)/PacketsPerWord;
+
+    // Allocate the dma here if transaction size is more than cpu based
+    // transaction thresold.
+    if ((TotalWordsRequested > hRmSpi->HwRegs.MaxWordTransfer) &&
+            (hRmSpi->DmaBufferSize) &&
+            (!hRmSpi->IsApbDmaAllocated))
+    {
+        hRmSpi->TransCountFromLastDmaUsage = 0;
+        hRmSpi->IsApbDmaAllocated = NV_TRUE;
+        DmaModuleId = (hRmSpi->IsSpiChannel)?NvRmDmaModuleID_Spi: NvRmDmaModuleID_Slink;
+        Error = NvRmDmaAllocate(hRmSpi->hDevice, &hRmSpi->hRmRxDma,
+                         NV_FALSE, NvRmDmaPriority_High, DmaModuleId,
+                         hRmSpi->InstanceId);
+        if (!Error)
+        {
+            Error = NvRmDmaAllocate(hRmSpi->hDevice, &hRmSpi->hRmTxDma,
+                             NV_FALSE, NvRmDmaPriority_High, DmaModuleId,
+                             hRmSpi->InstanceId);
+            if (Error)
+                NvRmDmaFree(hRmSpi->hRmRxDma);
+        }
+        if (Error)
+        {
+            hRmSpi->hRmRxDma = NULL;
+            hRmSpi->hRmTxDma = NULL;
+            hRmSpi->IsApbDmaAllocated = NV_FALSE;
+            Error = NvSuccess;
+        }
+    }
+    Error = SetChipSelectSignalLevel(hRmSpi, ChipSelectId, ClockSpeedInKHz,
+                                        NV_TRUE, NV_FALSE);
+    if (Error)
+        goto cleanup;
+
+    hRmSpi->hHwInterface->HwSetDataFlowFxn(&hRmSpi->HwRegs,
+                                                hRmSpi->CurrentDirection, NV_TRUE);
+
+    hRmSpi->hHwInterface->HwSetPacketLengthFxn(&hRmSpi->HwRegs,
+                                                PacketSizeInBits, IsPackedMode);
+
+    // Use cpu for less number of the data transfer.
+    if ((!hRmSpi->IsApbDmaAllocated) ||
+        (TotalWordsRequested <= hRmSpi->HwRegs.MaxWordTransfer))
+    {
+        hRmSpi->TransCountFromLastDmaUsage++;
+        Error = MasterModeReadWriteCpu(hRmSpi, pReadBuffer, pWriteBuffer,
+            TotalPacketsRequsted, &PacketsTransferred,
+            IsPackedMode, PacketSizeInBits);
+    }
+    else
+    {
+        hRmSpi->TransCountFromLastDmaUsage = 0;
+        Error = MasterModeReadWriteDma(hRmSpi, pReadBuffer, pWriteBuffer,
+            TotalPacketsRequsted, &PacketsTransferred,
+            IsPackedMode, PacketSizeInBits);
+    }
+
+    hRmSpi->hHwInterface->HwSetDataFlowFxn(&hRmSpi->HwRegs,
+                                            hRmSpi->CurrentDirection, NV_FALSE);
+    hRmSpi->CurrentDirection = SerialHwDataFlow_None;
+    (void)SetChipSelectSignalLevel(hRmSpi, ChipSelectId, ClockSpeedInKHz,
+                                   NV_FALSE, NV_FALSE);
+
+cleanup:
+
+    //  Re-tristate multi-plexed controllers, and re-multiplex the controller.
+    if (SpiPinMap)
+    {
+        NvRmPinMuxConfigSetTristate(hRmSpi->hDevice,hRmSpi->RmIoModuleId,
+            hRmSpi->InstanceId, SpiPinMap, NV_TRUE);
+
+        NvRmPinMuxConfigSelect(hRmSpi->hDevice,hRmSpi->RmIoModuleId,
+            hRmSpi->InstanceId, hRmSpi->SpiPinMap);
+    }
+    else
+    {
+        if (hRmSpi->IsIdleSignalTristate)
+            NvRmPinMuxConfigSetTristate(hRmSpi->hDevice,hRmSpi->RmIoModuleId,
+                hRmSpi->InstanceId, hRmSpi->SpiPinMap, NV_TRUE);
+    }
+
+    if ((hRmSpi->IsApbDmaAllocated) &&
+            (hRmSpi->TransCountFromLastDmaUsage > MAX_DMA_HOLD_TIME))
+    {
+        NvRmDmaFree(hRmSpi->hRmRxDma);
+        NvRmDmaFree(hRmSpi->hRmTxDma);
+        hRmSpi->hRmRxDma = NULL;
+        hRmSpi->hRmTxDma = NULL;
+        hRmSpi->IsApbDmaAllocated = NV_FALSE;
+    }
+
+#if !NV_OAL
+    BoostFrequency(hRmSpi, NV_FALSE, 0);
+    SetPowerControl(hRmSpi, NV_FALSE);
+    NvOsMutexUnlock(hRmSpi->hChannelAccessMutex);
+#endif
+
+    NV_ASSERT(Error == NvSuccess);
+
+}
+
+/**
+ * Start the data trasfer in slave mode.
+ */
+NvError NvRmSpiStartTransaction(
+    NvRmSpiHandle hRmSpi,
+    NvU32 ChipSelectId,
+    NvU32 ClockSpeedInKHz,
+    NvBool IsReadTransfer,
+    NvU8 *pWriteBuffer,
+    NvU32 BytesRequested,
+    NvU32 PacketSizeInBits)
+{
+    NvError Error = NvSuccess;
+    NvBool IsPackedMode;
+    NvU32 BytesPerPackets;
+    NvU32 TotalWordsRequested;
+    NvU32 PacketsPerWord;
+    NvU32 TotalPacketsRequsted;
+
+    NV_ASSERT(hRmSpi);
+    NV_ASSERT((IsReadTransfer) || (pWriteBuffer));
+
+    // Packet size should be 1 to 32..
+    NV_ASSERT((PacketSizeInBits > 0) && (PacketSizeInBits <= 32));
+
+    // Transfer is allowed for the slave mode only from this API.
+    NV_ASSERT(!hRmSpi->IsMasterMode);
+
+    BytesPerPackets = (PacketSizeInBits + 7)/8;
+
+    // Packets should be byte alligned.
+    NV_ASSERT((BytesRequested % BytesPerPackets) == 0);
+
+    // Slave mode will take the configuration from the Chip select 0.
+    NV_ASSERT(hRmSpi->IsChipSelSupported[ChipSelectId]);
+
+    TotalPacketsRequsted = BytesRequested/BytesPerPackets;
+
+    // Select Packed mode for the 8/16 bit length.
+    // nonwordaligned packed mode is not supported then check for the wordaligend
+    // packets also.
+    if (hRmSpi->HwRegs.IsNonWordAlignedPackModeSupported)
+    {
+        IsPackedMode = ((PacketSizeInBits == 8) ||(PacketSizeInBits == 16));
+    }
+    else
+    {
+        IsPackedMode = (((PacketSizeInBits == 8) && (!(TotalPacketsRequsted & 0x3))) ||
+                        ((PacketSizeInBits == 16) && (!(TotalPacketsRequsted & 0x1))));
+    }
+    PacketsPerWord =  (IsPackedMode)? 4/BytesPerPackets: 1;
+    hRmSpi->CurrTransInfo.PacketsPerWord = PacketsPerWord;
+
+    TotalWordsRequested = (TotalPacketsRequsted + PacketsPerWord -1)/PacketsPerWord;
+
+    // Total word trasfer should be maximum of 16KW (64KB): Hw Dma constraints
+    NV_ASSERT(TotalWordsRequested <= MAXIMUM_SLAVE_TRANSFER_WORD);
+
+    // Packet requested should not be more than 64KB: Slink controller constraints
+    NV_ASSERT(TotalPacketsRequsted <= (1 << 16));
+
+    // If total transfer word is more than 64KB (dma max transfer) or
+    // number of packet requested is more than 64K (slink max packet transfer)
+    // then return the error as NotSupported.
+    if ((TotalWordsRequested > MAXIMUM_SLAVE_TRANSFER_WORD) ||
+            (TotalPacketsRequsted > (1 << 16)))
+        return NvError_NotSupported;
+
+
+    // Lock the channel access.
+    NvOsMutexLock(hRmSpi->hChannelAccessMutex);
+
+    hRmSpi->CurrTransferChipSelId = ChipSelectId;
+
+    if (hRmSpi->IsIdleSignalTristate)
+        NvRmPinMuxConfigSetTristate(hRmSpi->hDevice,hRmSpi->RmIoModuleId,
+            hRmSpi->InstanceId, hRmSpi->SpiPinMap, NV_FALSE);
+
+    // Enable Power/Clock.
+    Error = SetPowerControl(hRmSpi, NV_TRUE);
+    if (!Error)
+        BoostFrequency(hRmSpi, NV_TRUE, BytesRequested);
+
+    if (!Error)
+        Error = SetChipSelectSignalLevel(hRmSpi, ChipSelectId, ClockSpeedInKHz,
+                                                    NV_TRUE, NV_FALSE);
+
+    if (Error)
+        goto cleanup;
+
+    hRmSpi->CurrentDirection = (IsReadTransfer)?SerialHwDataFlow_Rx : SerialHwDataFlow_None;
+    if (pWriteBuffer)
+        hRmSpi->CurrentDirection |= SerialHwDataFlow_Tx;
+
+    // Set the data direction
+    hRmSpi->hHwInterface->HwSetDataFlowFxn(&hRmSpi->HwRegs,
+                                            hRmSpi->CurrentDirection, NV_TRUE);
+
+    // Use only interrupt mode for transfer
+    hRmSpi->hHwInterface->HwSetInterruptSourceFxn(&hRmSpi->HwRegs,
+                                            hRmSpi->CurrentDirection, NV_TRUE);
+
+    hRmSpi->hHwInterface->HwSetPacketLengthFxn(&hRmSpi->HwRegs,
+                                        PacketSizeInBits, IsPackedMode);
+
+    // Use cpu if the dma is not allocated or the transfer size is less than
+    // one fifo depth
+    if ((!hRmSpi->IsApbDmaAllocated) ||
+                (TotalWordsRequested <= hRmSpi->HwRegs.MaxWordTransfer))
+    {
+        // Non dma mode: The maximum word transfer is the fifo depth.
+        // The word requested should be less than the maximum one transaction.
+        // We can not split the  slave transaction in multiple small transactions
+        NV_ASSERT(TotalWordsRequested <= hRmSpi->HwRegs.MaxWordTransfer);
+
+        Error = SlaveModeSpiStartReadWriteCpu(hRmSpi, IsReadTransfer, pWriteBuffer,
+                    TotalPacketsRequsted, IsPackedMode, PacketSizeInBits);
+    }
+    else
+    {
+        Error = SlaveModeSpiStartReadWriteDma(hRmSpi, IsReadTransfer, pWriteBuffer,
+                    TotalPacketsRequsted, IsPackedMode, PacketSizeInBits);
+    }
+
+    if (!Error)
+        return Error;
+cleanup:
+
+    (void)SetChipSelectSignalLevel(hRmSpi, ChipSelectId, ClockSpeedInKHz, NV_FALSE, NV_TRUE);
+
+    if (hRmSpi->IsIdleSignalTristate)
+        NvRmPinMuxConfigSetTristate(hRmSpi->hDevice,hRmSpi->RmIoModuleId,
+            hRmSpi->InstanceId, hRmSpi->SpiPinMap, NV_TRUE);
+    BoostFrequency(hRmSpi, NV_FALSE, 0);
+    SetPowerControl(hRmSpi, NV_FALSE);
+    NvOsMutexUnlock(hRmSpi->hChannelAccessMutex);
+    return Error;
+}
+
+NvError
+NvRmSpiGetTransactionData(
+    NvRmSpiHandle hRmSpiSlink,
+    NvU8 *pReadBuffer,
+    NvU32 BytesRequested,
+    NvU32 *pBytesTransfererd,
+    NvU32 WaitTimeout)
+{
+    NvError Error = NvSuccess;
+
+    NV_ASSERT(pBytesTransfererd);
+    NV_ASSERT((pReadBuffer && (hRmSpiSlink->CurrentDirection & SerialHwDataFlow_Rx )) ||
+              ((!pReadBuffer) && (!(hRmSpiSlink->CurrentDirection & SerialHwDataFlow_Rx))));
+
+    if (hRmSpiSlink->CurrentDirection == SerialHwDataFlow_None)
+        return NvError_InvalidState;
+
+    Error = SlaveModeSpiCompleteReadWrite(hRmSpiSlink, pReadBuffer,
+                                            pBytesTransfererd, WaitTimeout);
+
+    (void)SetChipSelectSignalLevel(hRmSpiSlink, hRmSpiSlink->CurrTransferChipSelId,
+                                                0, NV_FALSE, NV_TRUE);
+
+    if (hRmSpiSlink->IsIdleSignalTristate)
+        NvRmPinMuxConfigSetTristate(hRmSpiSlink->hDevice,hRmSpiSlink->RmIoModuleId,
+            hRmSpiSlink->InstanceId, hRmSpiSlink->SpiPinMap, NV_TRUE);
+
+    BoostFrequency(hRmSpiSlink, NV_FALSE, 0);
+
+    // Disable Power/Clock.
+    SetPowerControl(hRmSpiSlink, NV_FALSE);
+    NvOsMutexUnlock(hRmSpiSlink->hChannelAccessMutex);
+    return Error;
+}
+
+void
+NvRmSpiSetSignalMode(
+    NvRmSpiHandle hRmSpi,
+    NvU32 ChipSelectId,
+    NvU32 SpiSignalMode)
+{
+    NV_ASSERT(hRmSpi);
+    if (hRmSpi->IsChipSelSupported[ChipSelectId])
+    {
+        NvOsMutexLock(hRmSpi->hChannelAccessMutex);
+        hRmSpi->DeviceInfo[ChipSelectId].SignalMode = (NvOdmQuerySpiSignalMode)SpiSignalMode;
+        NvOsMutexUnlock(hRmSpi->hChannelAccessMutex);
+    }
+}
+
diff --git a/arch/arm/mach-tegra/nvrm/io/ap15/rm_spi_slink_hw_private.h b/arch/arm/mach-tegra/nvrm/io/ap15/rm_spi_slink_hw_private.h
new file mode 100644
index 000000000000..3e1d83fdc229
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/io/ap15/rm_spi_slink_hw_private.h
@@ -0,0 +1,401 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/** 
+ * @file
+ * @brief <b>nVIDIA Driver Development Kit: 
+ *           Private functions for the spi Rm driver</b>
+ *
+ * @b Description:  Defines the private interfacing functions for the spi 
+ * hw interface.
+ * 
+ */
+
+#ifndef INCLUDED_RMSPI_HW_PRIVATE_H
+#define INCLUDED_RMSPI_HW_PRIVATE_H
+
+/**
+ * @defgroup nvrm_spi Synchrnous Peripheral Interface(SPI) Controller hw 
+ * interface API
+ * 
+ * This is the synchrnous peripheral interface (SPI) hw interface controller api
+ * which communicate to the device/other processor using the spi protocols.
+ * 
+ * @ingroup nvddk_modules
+ * @{
+ *
+ */
+
+#include "nvcommon.h"
+#include "nvrm_init.h"
+#include "nvodm_query.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/**
+ * Combines the spi hw register states.
+ */
+typedef struct 
+{
+    NvU32 Command;    
+    NvU32 Status;
+    NvU32 DmaControl;
+} SpiHwRegisters;
+
+/**
+ * Combines the slink hw register states.
+ */
+typedef struct 
+{
+    NvU32 Command1;    
+    NvU32 Command2;    
+    NvU32 Status;
+    NvU32 DmaControl;
+} SlinkHwRegisters;
+
+/**
+ * Making the union of the spi/slink hw register states.
+ */
+typedef union
+{
+    SpiHwRegisters SpiRegs;
+    SlinkHwRegisters SlinkRegs;
+} SerialHwRegistersState;
+
+
+/**
+ * Combines the definition of the spi register and modem signals.
+ */
+typedef struct 
+{
+    // Serial channel Id.
+    NvU32 InstanceId;
+
+    // Virtual base address of the spi hw register.
+    NvU32 *pRegsBaseAdd;
+
+    NvRmPhysAddr HwTxFifoAdd;
+
+    NvRmPhysAddr HwRxFifoAdd;
+
+    NvU32 RegBankSize;
+
+    NvBool IsPackedMode;
+
+    NvU32 PacketLength;
+
+    NvOdmQuerySpiSignalMode CurrSignalMode;
+
+    NvOdmQuerySpiSignalMode IdleSignalMode;
+
+    NvBool IsIdleDataOutHigh;
+    
+    NvBool IsLsbFirst;
+
+    SerialHwRegistersState HwRegs;
+
+    NvU32 MaxWordTransfer;
+    NvBool IsMasterMode;
+
+    // Tells whether the non word aligned packet size is supported or not.
+    // If it is supported then we need not to do any sw workaround otherwise
+    // Transfer the nearest word aligned packet using the packed mode and 
+    // remaining as non-packed format.
+    NvBool IsNonWordAlignedPackModeSupported;
+
+    /// Flag to tell whether the Hw based chipselect is supported or not.
+    NvBool IsHwChipSelectSupported;
+} SerialHwRegisters;
+
+/**
+ * Combines the spi  hw data flow direction where it is the receive side 
+ * or transmit side.
+ */
+typedef enum 
+{
+    // No data transfer.
+    SerialHwDataFlow_None      = 0x0,
+
+    // Receive data flow.
+    SerialHwDataFlow_Rx        = 0x1,
+    
+    // Transmit data flow.
+    SerialHwDataFlow_Tx       = 0x2,
+    
+    SerialHwDataFlow_Force32 = 0x7FFFFFFF
+} SerialHwDataFlow;
+
+/**
+ * Combines the spi interrupt reasons.
+ */
+typedef enum 
+{
+    // No Serial interrupt reason.
+    SerialHwIntReason_None           = 0x0,
+    
+    // Receive error Serial interrupt reason.
+    SerialHwIntReason_RxError   = 0x1,
+
+    // Transmit Error spi interrupt reason.
+    SerialHwIntReason_TxError  = 0x2,
+
+    // Transfer complete interrupt reason.
+    SerialHwIntReason_TransferComplete = 0x4,
+    
+    SerialHwIntReason_Force32 = 0x7FFFFFFF
+} SerialHwIntReason;
+
+/**
+ * Combines the spi hw fifo type.
+ */
+typedef enum 
+{
+    // Receive fifo type.
+    SerialHwFifo_Rx = 0x1,
+
+    // Transmit fifo type.
+    SerialHwFifo_Tx = 0x2,
+
+    // Both Rx and Tx fifo
+    SerialHwFifo_Both = 0x3,
+    
+    SerialHwFifo_Force32 = 0x7FFFFFFF
+    
+} SerialHwFifo;
+
+
+// The structure of the function pointers to provide the interface to access
+// the spi/slink hw registers and their property.
+typedef struct
+{
+    /**
+     * Initialize the spi register.
+     */
+    void (* HwRegisterInitializeFxn)(NvU32 SerialChannelId, SerialHwRegisters *pHwRegs);
+
+    /**
+     * Initialize the spi controller.
+     */
+    void (* HwControllerInitializeFxn)(SerialHwRegisters *pHwRegs);
+
+    /**
+     * Set the functional mode whether this is the master or slave mode.
+     */
+    void (* HwSetFunctionalModeFxn)(SerialHwRegisters *pHwRegs, NvBool IsMasterMode);
+
+    /**
+     * Set the signal mode of communication whether this is the mode  0, 1, 2 or 3.
+     */
+    void (* HwSetSignalModeFxn)(SerialHwRegisters *pHwRegs, NvOdmQuerySpiSignalMode SignalMode);
+
+    /**
+     * Reset the fifo
+     */
+    void (* HwResetFifoFxn)(SerialHwRegisters *pHwRegs, SerialHwFifo FifoType);
+
+    /**
+     * Find out whether transmit fifo is full or not.
+     */
+    NvBool (* HwIsTransmitFifoFull)(SerialHwRegisters *pHwRegs);
+
+    /**
+     * Set the transfer order whether the bit will start from the lsb or from
+     * msb.
+     */
+    void (* HwSetTransferBitOrderFxn)(SerialHwRegisters *pHwRegs, NvBool IsLsbFirst);
+
+    /**
+     * Start the transfer of the communication.
+     */
+    void (* HwStartTransferFxn)(SerialHwRegisters *pHwRegs, NvBool IsReconfigure);
+
+    /**
+     * Enable/disable the data transfer flow.
+     */
+    void 
+    (* HwSetDataFlowFxn)(
+        SerialHwRegisters *pHwRegs, 
+        SerialHwDataFlow DataFlow, 
+        NvBool IsEnable);
+
+    /**
+     * Set the chip select signal level to be default based on device during the
+     * initialization.
+     */
+    void
+    (* HwSetChipSelectDefaultLevelFxn)(
+        SerialHwRegisters *pHwRegs, 
+        NvU32 ChipSelectId,
+        NvBool IsHigh);
+
+   /**
+     * Set the chip select signal level.
+     */
+    void
+    (* HwSetChipSelectLevelFxn)(
+        SerialHwRegisters *pHwRegs, 
+        NvU32 ChipSelectId,
+        NvBool IsHigh);
+        
+    /**
+     * Set the chip select signal level based on the transfer size.
+     * it can use the hw based CS or SW based CS based on transfer size and
+     * cpu/apb dma based transfer.
+     * Return NV_TRUE if the SW based chipselection is used otherwise return
+     * NV_FALSE;
+     */
+    NvBool
+    (* HwSetChipSelectLevelBasedOnPacketFxn)(
+        SerialHwRegisters *pHwRegs, 
+        NvU32 ChipSelectId,
+        NvBool IsHigh,
+        NvU32 PacketRequested,
+        NvU32 PacketPerWord,
+        NvBool IsApbDmaBasedTransfer,
+        NvBool IsOnlyUseSWCS);
+
+
+     /**
+     * Set the packet length.
+     */
+    void
+    (* HwSetPacketLengthFxn)(
+        SerialHwRegisters *pHwRegs, 
+        NvU32 PacketLength, 
+        NvBool IsPackedMode);
+
+    /**
+     * Set the Dma transfer size.
+     */
+    void
+    (* HwSetDmaTransferSizeFxn)(
+        SerialHwRegisters *pHwRegs, 
+        NvU32 DmaBlockSize);
+
+    /**
+     * Get the transferred packet count.
+     */
+    NvU32 (* HwGetTransferdCountFxn)(SerialHwRegisters *pHwRegs);
+
+
+    /**
+     * Set the trigger level.
+     */
+    void 
+    (* HwSetTriggerLevelFxn)(
+        SerialHwRegisters *pHwRegs, 
+        SerialHwFifo FifoType,
+        NvU32 TriggerLevel);
+
+    /**
+     * Write into the transmit fifo register.
+     * returns the number of words written.
+     */
+    NvU32
+    (* HwWriteInTransmitFifoFxn)(
+        SerialHwRegisters *pHwRegs, 
+        NvU32 *pTxBuff,  
+        NvU32 WordRequested);
+        
+    /**
+     * Read the data from the receive fifo.
+     * Returns the number of words it read.   
+     */
+    NvU32
+    (* HwReadFromReceiveFifoFxn)(
+        SerialHwRegisters *pHwRegs, 
+        NvU32 *pRxBuff,  
+        NvU32 WordRequested);
+
+    /**
+     * Enable/disable the interrupt source. 
+     */
+    void
+    (* HwSetInterruptSourceFxn)(
+        SerialHwRegisters *pHwRegs, 
+        SerialHwDataFlow DataDirection,
+        NvBool IsEnable);
+
+    /**
+     * Get the transfer status. 
+     */
+    NvError 
+    (* HwGetTransferStatusFxn)(
+        SerialHwRegisters *pHwRegs,
+        SerialHwDataFlow DataDirection);
+
+    /**
+     * Clear the transfer status. 
+     */
+    void 
+    (* HwClearTransferStatusFxn)(
+        SerialHwRegisters *pHwRegs,
+        SerialHwDataFlow DataDirection);
+
+    /**
+     * Check whether transfer is completed or not. 
+     */
+    NvBool (* HwIsTransferCompletedFxn)( SerialHwRegisters *pHwRegs);
+} HwInterface, *HwInterfaceHandle;
+
+
+/**
+ * Initialize the spi intterface for the hw access.
+ */
+void NvRmPrivSpiSlinkInitSpiInterface(HwInterface *pSpiInterface);
+
+/**
+ * Initialize the slink intterface for the hw access which are common across 
+ * the version.
+ */
+void NvRmPrivSpiSlinkInitSlinkInterface(HwInterface *pSpiInterface);
+
+/**
+ * Initialize the slink interface of version 1.0 for the hw access.
+ */
+void NvRmPrivSpiSlinkInitSlinkInterface_v1_0(HwInterface *pSlinkInterface);
+
+
+/**
+ * Initialize the ap20 slink interface of version 1.1 for the hw access.
+ */
+void NvRmPrivSpiSlinkInitSlinkInterface_v1_1(HwInterface *pSlinkInterface);
+
+/** @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif  // INCLUDED_RMSPI_HW_PRIVATE_H
diff --git a/arch/arm/mach-tegra/nvrm/io/ap20/Makefile b/arch/arm/mach-tegra/nvrm/io/ap20/Makefile
new file mode 100644
index 000000000000..2597d211c3b2
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/io/ap20/Makefile
@@ -0,0 +1,17 @@
+ccflags-y += -DNV_IS_AVP=0
+ccflags-y += -DNV_OAL=0
+ccflags-y += -DNV_USE_FUSE_CLOCK_ENABLE=0
+ifeq ($(CONFIG_MACH_TEGRA_GENERIC_DEBUG),y)
+ccflags-y += -DNV_DEBUG=1
+else
+ccflags-y += -DNV_DEBUG=0
+endif
+
+ccflags-y += -Iarch/arm/mach-tegra/nvrm/core/common
+ccflags-y += -Iarch/arm/mach-tegra/nvrm/io/common
+ccflags-y += -Iarch/arm/mach-tegra/nvrm/io
+ccflags-y += -Iarch/arm/mach-tegra/nvrm/core
+
+obj-y += ap20rm_i2c.o
+obj-y += ap20rm_slink_hw_private.o
+obj-y += ap20rm_owr.o
diff --git a/arch/arm/mach-tegra/nvrm/io/ap20/ap20rm_i2c.c b/arch/arm/mach-tegra/nvrm/io/ap20/ap20rm_i2c.c
new file mode 100644
index 000000000000..c9d40286704b
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/io/ap20/ap20rm_i2c.c
@@ -0,0 +1,1543 @@
+/*
+ * Copyright (c) 2008-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/** @file
+ * @brief <b>NVIDIA Driver Development Kit: I2C API</b>
+ *
+ * @b Description: Contains the NvRM I2C implementation. for Ap20 
+ */
+
+#include "nvrm_i2c.h"
+#include "nvrm_i2c_private.h"
+#include "nvrm_drf.h"
+#include "nvos.h"
+#include "nvrm_module.h"
+#include "ap20/ari2c.h"
+#include "nvrm_hardware_access.h"
+#include "nvrm_power.h" 
+#include "nvrm_interrupt.h"
+#include "nvassert.h"
+#include "ap20/ardvc.h"
+#include "nvodm_query_pinmux.h"
+#include "nvrm_pinmux.h"
+#include "nvrm_chiplib.h"
+#include "nvrm_hwintf.h"
+
+/* Register access Macros */
+#define I2C_REGR(c, reg) NV_REGR((c)->hRmDevice, (c)->ModuleId, (c)->Instance,  \
+        (c)->I2cRegisterOffset + (((c)->ModuleId == NvRmModuleID_Dvc) ? DVC_##reg##_0 : \
+                                                I2C_##reg##_0)) 
+
+#define I2C_REGW(c, reg, val) \
+        do { \
+            NV_REGW((c)->hRmDevice, (c)->ModuleId, (c)->Instance, \
+                ((c)->I2cRegisterOffset + (((c)->ModuleId == NvRmModuleID_Dvc) ? DVC_##reg##_0 : \
+                                            I2C_##reg##_0)), (val)); \
+        } while(0)
+
+#define DVC_REGR(c, reg)    NV_REGR((c)->hRmDevice, NvRmModuleID_Dvc, (c)->Instance, \
+                    DVC_##reg##_0)
+#define DVC_REGW(c, reg, val) \
+        do {    \
+            NV_REGW((c)->hRmDevice, NvRmModuleID_Dvc, (c)->Instance, \
+                    DVC_##reg##_0, val); \
+        } while(0)
+
+
+/* Register access Macros */
+#define I2C2_REGR(c, reg) NV_REGR((c)->hRmDevice, (c)->ModuleId, (c)->Instance,  \
+                    (c)->I2cRegisterOffset + I2C_##reg##_0 )
+
+#define I2C2_REGW(c, reg, val) \
+        do {    \
+                NV_REGW((c)->hRmDevice, (c)->ModuleId, (c)->Instance, \
+                    ((c)->I2cRegisterOffset + I2C_##reg##_0), (val) ); \
+        } while(0);
+                    
+
+#define DEBUG_SEND_PROCESS 0
+#define DEBUG_READ_PROCESS 0
+#define DEBUG_TRACE_PROCESS 0
+
+#if DEBUG_SEND_PROCESS
+#define DEBUG_I2C_SEND(Expr, Format) \
+                    do { \
+                        if (Expr) \
+                        {   \
+                            NvOsDebugPrintf Format; \
+                        }   \
+                    } while(0)
+#else
+#define DEBUG_I2C_SEND(Expr, Format)
+#endif
+
+#if DEBUG_READ_PROCESS
+#define DEBUG_I2C_READ(Expr, Format) \
+                    do { \
+                        if (Expr) \
+                        {   \
+                            NvOsDebugPrintf Format; \
+                        }   \
+                    } while(0)
+#else
+#define DEBUG_I2C_READ(Expr, Format)
+#endif
+
+#if DEBUG_TRACE_PROCESS
+#define DEBUG_I2C_TRACE(Expr, Format) \
+                    do { \
+                        if (Expr) \
+                        {   \
+                            NvOsDebugPrintf Format; \
+                        } \
+                    } while(0)
+#else
+#define DEBUG_I2C_TRACE(Expr, Format)
+#endif
+
+// The maximum transfer size by one transaction.
+enum {MAX_I2C_ONE_TRANSACTION_SIZE = 0x1000}; // 4KB
+
+// The maximum request size for one transaction using the dma.
+// + 64 bytes for the packet header.
+enum {DEFAULT_I2C_DMA_BUFFER_SIZE = (MAX_I2C_ONE_TRANSACTION_SIZE + 0x40)}; // 4KB
+
+// The default request size for one transaction using the nondma mode.
+enum {DEFAULT_I2C_CPU_BUFFER_SIZE = MAX_I2C_ONE_TRANSACTION_SIZE};
+
+// Wait time to poll the status for completion.
+enum { I2C_POLLING_TIMEOUT_STEP_USEC = 1000};
+
+// I2C fifo depth.
+enum { I2C_FIFO_DEPTH = 8};
+
+// I2C Dma/CPU based seletion thresold.
+enum { I2C_MAX_WORD_TO_USE_CPU = 16};
+
+// Holding the apb dma for the continuous non dma transaction count
+enum {HOLDING_DMA_TRANSACTION_COUNT = 15};
+#define I2C_TRANSACTION_STATUS_ERRORS \
+    (NV_DRF_DEF(I2C, INTERRUPT_STATUS_REGISTER, TFIFO_OVF, SET) | \
+     NV_DRF_DEF(I2C, INTERRUPT_STATUS_REGISTER, RFIFO_UNF, SET) | \
+     NV_DRF_DEF(I2C, INTERRUPT_STATUS_REGISTER, ARB_LOST, SET))
+
+#define I2C_ARBITRATION_LOST_ERRORS \
+         (NV_DRF_DEF(I2C, INTERRUPT_STATUS_REGISTER, ARB_LOST, SET))
+
+#define I2C_ERRORS_INTERRUPT_MASK \
+    (NV_DRF_DEF(I2C, INTERRUPT_MASK_REGISTER, TFIFO_OVF_INT_EN, ENABLE) | \
+     NV_DRF_DEF(I2C, INTERRUPT_MASK_REGISTER, RFIFO_UNF_INT_EN, ENABLE) | \
+     NV_DRF_DEF(I2C, INTERRUPT_MASK_REGISTER, ARB_LOST_INT_EN, ENABLE))
+
+#if NV_OAL
+#define USE_POLLING_METHOD 1
+#else
+#define USE_POLLING_METHOD 0
+#endif
+
+#if USE_POLLING_METHOD
+#define RESET_SEMA_COUNT(hSema) 
+#else
+#define RESET_SEMA_COUNT(hSema) \
+    while(NvOsSemaphoreWaitTimeout(hSema, 0) != NvError_Timeout)
+#endif
+
+// Convert the number of bytes to word.
+#define BYTES_TO_WORD(ReqSize) (((ReqSize) + 3) >> 2)
+
+/**
+ * Create the dma buffer memory handle.
+ */
+static NvError
+CreateDmaBufferMemoryHandle(
+    NvRmDeviceHandle hDevice,
+    NvRmMemHandle *phNewMemHandle,
+    NvRmPhysAddr *pNewMemAddr,
+    NvU32 BufferSize)
+{
+    NvError Error = NvSuccess;
+    NvRmMemHandle hNewMemHandle = NULL;
+    static const NvRmHeap HeapProperty[] =
+    {
+        NvRmHeap_ExternalCarveOut,
+        NvRmHeap_External,
+        NvRmHeap_GART,
+    };
+
+    // Initialize the memory handle with NULL
+    *phNewMemHandle = NULL;
+
+    /// Create memory handle
+    Error = NvRmMemHandleCreate(hDevice, &hNewMemHandle, BufferSize);
+
+    // Allocates the memory from the sdram
+    if (!Error)
+        Error = NvRmMemAlloc(hNewMemHandle, HeapProperty,
+                        NV_ARRAY_SIZE(HeapProperty), 4, NvOsMemAttribute_Uncached);
+
+    // Pin the memory allocation so that it should not move by memory manager.
+    if (!Error)
+        *pNewMemAddr = NvRmMemPin(hNewMemHandle);
+
+    // If error then free the memory allocation and memory handle.
+    if (Error)
+    {
+        NvRmMemHandleFree(hNewMemHandle);
+        hNewMemHandle = NULL;
+    }
+
+    *phNewMemHandle = hNewMemHandle;
+    return Error;
+}
+
+ /**
+  * Destroy the dma buffer memory handle.
+  */
+static void DestroyDmaBufferMemoryHandle(NvRmMemHandle hMemHandle)
+{
+    // Can accept the null parameter. If it is not null then only destroy.
+    if (hMemHandle)
+    {
+        // Unpin the memory allocation.
+        NvRmMemUnpin(hMemHandle);
+
+        // Free the memory handle.
+        NvRmMemHandleFree(hMemHandle);
+    }
+}
+
+/**
+ * Create the dma transfer buffer for the given handles.
+ */
+static NvError
+CreateDmaTransferBuffer(
+    NvRmDeviceHandle hRmDevice,
+    NvRmMemHandle *phRmMemory,
+    NvRmPhysAddr *pBuffPhysAddr,
+    void **pBuffPtr,
+    NvU32 BufferSize)
+{
+    NvError Error = NvSuccess;
+    NvRmMemHandle hRmMemory = NULL;
+    NvRmPhysAddr BuffPhysAddr;
+
+    // Reset all the members realted to the dma buffer.
+    BuffPhysAddr = 0;
+
+    *phRmMemory = NULL;
+    *pBuffPtr = (void *)NULL;
+    *pBuffPhysAddr = 0;
+
+    // Create the dma buffer memory for receive and transmit.
+    // It will be double of the OneBufferSize
+    Error = CreateDmaBufferMemoryHandle(hRmDevice, &hRmMemory, 
+                                                &BuffPhysAddr, BufferSize);
+    if (!Error)
+    {
+        // 0 to OneBufferSize-1 is buffer 1 and OneBufferSize to 2*OneBufferSize
+        // is second buffer.
+        Error = NvRmMemMap(hRmMemory, 0, BufferSize, 
+                                                NVOS_MEM_READ_WRITE, pBuffPtr);
+        // If error then free the allocation and reset all changed value.
+        if (Error)
+        {
+            DestroyDmaBufferMemoryHandle(hRmMemory);
+            hRmMemory = NULL;
+            *pBuffPtr = (void *)NULL;
+            return Error;
+        }
+        *phRmMemory = hRmMemory;
+        *pBuffPhysAddr = BuffPhysAddr;
+    }
+    return Error;
+}
+
+/**
+ * Destroy the dma transfer buffer.
+ */
+static void
+DestroyDmaTransferBuffer(
+    NvRmMemHandle hRmMemory,
+    void *pBuffPtr,
+    NvU32 BufferSize)
+{
+    if (hRmMemory)
+    {
+        if (pBuffPtr)
+            NvRmMemUnmap(hRmMemory, pBuffPtr, BufferSize);
+        DestroyDmaBufferMemoryHandle(hRmMemory);
+    }
+}
+
+static void SetTxFifoTriggerLevel(NvRmI2cControllerHandle hRmI2cCont, NvU32 TrigLevel)
+{
+    NvU32 FifoControlReg;
+    NvU32 ActualTriggerLevel = NV_MIN(I2C_FIFO_DEPTH, TrigLevel);
+
+    if (!ActualTriggerLevel)
+        return;
+    
+    FifoControlReg = I2C_REGR (hRmI2cCont, FIFO_CONTROL);
+    FifoControlReg = NV_FLD_SET_DRF_NUM(I2C, FIFO_CONTROL, TX_FIFO_TRIG, 
+                                                ActualTriggerLevel - 1, FifoControlReg);
+    DEBUG_I2C_SEND(1, ("Tx Fifo Control  0x%08x\n", FifoControlReg));
+    I2C_REGW (hRmI2cCont, FIFO_CONTROL, FifoControlReg);
+}
+
+static void SetRxFifoTriggerLevel(NvRmI2cControllerHandle hRmI2cCont, NvU32 TrigLevel)
+{
+    NvU32 FifoControlReg;
+    NvU32 ActualTriggerLevel = NV_MIN(I2C_FIFO_DEPTH, TrigLevel);
+
+    if (!ActualTriggerLevel)
+        return;
+        
+    FifoControlReg = I2C_REGR (hRmI2cCont, FIFO_CONTROL);
+    FifoControlReg = NV_FLD_SET_DRF_NUM(I2C, FIFO_CONTROL, RX_FIFO_TRIG, 
+                                                ActualTriggerLevel - 1, FifoControlReg);
+    DEBUG_I2C_READ(1, ("Rx Fifo Control  0x%08x\n", FifoControlReg));
+    I2C_REGW (hRmI2cCont, FIFO_CONTROL, FifoControlReg);
+}
+
+
+static void ResetTxFifo(NvRmI2cControllerHandle hRmI2cCont)
+{
+    NvU32 FifoControlReg;
+    
+    FifoControlReg = I2C_REGR (hRmI2cCont, FIFO_CONTROL);
+    FifoControlReg = NV_FLD_SET_DRF_DEF(I2C, FIFO_CONTROL, TX_FIFO_FLUSH, 
+                                                SET, FifoControlReg);
+    I2C_REGW (hRmI2cCont, FIFO_CONTROL, FifoControlReg);
+    do
+    {
+        NvOsWaitUS(10);
+        FifoControlReg = I2C_REGR (hRmI2cCont, FIFO_CONTROL);
+    }while(FifoControlReg & NV_DRF_DEF(I2C, FIFO_CONTROL, TX_FIFO_FLUSH, SET));
+}
+
+static void DoDvcI2cControlInitialization(NvRmI2cControllerHandle hRmI2cCont)
+{
+    NvU32 RegVal = 0;
+    
+    RegVal = DVC_REGR(hRmI2cCont, CTRL_REG3);
+    RegVal = NV_FLD_SET_DRF_DEF(DVC, CTRL_REG3, I2C_HW_SW_PROG, SW, RegVal);
+    RegVal = NV_FLD_SET_DRF_DEF(DVC, CTRL_REG3, I2C_DONE_INTR_EN, ENABLE, RegVal);
+    DVC_REGW(hRmI2cCont, CTRL_REG3, RegVal);
+    
+    RegVal = DVC_REGR(hRmI2cCont, CTRL_REG1);
+    RegVal = NV_FLD_SET_DRF_DEF(DVC, CTRL_REG1, INTR_EN, ENABLE, RegVal);
+    DVC_REGW(hRmI2cCont, CTRL_REG1, RegVal);
+}
+
+static void UseDvcI2cNewSlave(NvRmI2cControllerHandle hRmI2cCont)
+{
+    NvU32 RegVal = 0;
+    RegVal = NV_DRF_DEF(I2C, I2C_SL_CNFG, NEWSL, ENABLE);
+    I2C2_REGW(hRmI2cCont, I2C_SL_CNFG, RegVal);
+    
+    RegVal = NV_DRF_NUM(I2C, I2C_SL_ADDR1, SL_ADDR0, 0xF);
+    I2C2_REGW(hRmI2cCont, I2C_SL_ADDR1, RegVal);
+}
+
+static void 
+GetPacketHeaders(
+    NvRmI2cControllerHandle hRmI2cCont,
+    NvRmI2cTransactionInfo *pTransaction,
+    NvU32 PacketId,
+    NvU32 *pPacketHeader1,
+    NvU32 *pPacketHeader2,
+    NvU32 *pPacketHeader3)
+{
+    NvU32 PacketHeader1;
+    NvU32 PacketHeader2;
+    NvU32 PacketHeader3;
+
+    // prepare Generic header1
+    // Header size = 0 Protocol  = I2C,pktType = 0
+    PacketHeader1 = NV_DRF_DEF(I2C, IO_PACKET_HEADER, HDRSZ, ONE) | 
+                              NV_DRF_DEF(I2C, IO_PACKET_HEADER, PROTOCOL, I2C);
+    
+    // Set pkt id as 1
+    PacketHeader1 = NV_FLD_SET_DRF_NUM(I2C, IO_PACKET_HEADER, PKTID, PacketId, PacketHeader1);
+    
+    // Controller id is according to the instance of the i2c/dvc
+    PacketHeader1 = NV_FLD_SET_DRF_NUM(I2C, IO_PACKET_HEADER, 
+                               CONTROLLER_ID, hRmI2cCont->ControllerId, PacketHeader1);
+    
+    PacketHeader2 = NV_FLD_SET_DRF_NUM(I2C, IO_PACKET_HEADER, 
+                                    PAYLOADSIZE, (pTransaction->NumBytes - 1), 0);
+    
+    // prepare IO specific header
+    // Configure the slave address
+    PacketHeader3 = pTransaction->Address;
+    
+    // 10 bit address mode: Set address mode to 10 bit
+    if (hRmI2cCont->Is10BitAddress)
+        PacketHeader3 = NV_FLD_SET_DRF_DEF(I2C, IO_PACKET_HEADER, ADDR_MODE, 
+                                                        TEN_BIT, PacketHeader3);
+    
+    hRmI2cCont->IsCurrentTransferNoAck = NV_FALSE;
+    // Enable mode to handle devices that do not generate ACK 
+    if (pTransaction->Flags & NVRM_I2C_NOACK)
+    {
+        PacketHeader3 = NV_FLD_SET_DRF_DEF(I2C, IO_PACKET_HEADER, CONTUNE_ON_NACK, 
+                                                        ENABLE, PacketHeader3);
+        hRmI2cCont->IsCurrentTransferNoAck = NV_TRUE;
+    }
+    
+    hRmI2cCont->IsCurrentTransferNoStop = NV_FALSE;
+
+    // Enable mode to repeat start if it is configured
+    if (pTransaction->Flags & NVRM_I2C_NOSTOP)
+    {
+        PacketHeader3 = NV_FLD_SET_DRF_DEF(I2C, IO_PACKET_HEADER,REPEAT_START, 
+                                                REPEAT_START, PacketHeader3);
+        hRmI2cCont->IsCurrentTransferNoStop = NV_TRUE;
+    }                                           
+
+    hRmI2cCont->IsCurrentTransferRead = NV_FALSE;
+    // Enable Read if it is required
+    if (!(pTransaction->Flags & NVRM_I2C_WRITE))
+    {
+        PacketHeader3 = NV_FLD_SET_DRF_DEF(I2C, IO_PACKET_HEADER, READ, READ, 
+                                                PacketHeader3);
+        hRmI2cCont->IsCurrentTransferRead = NV_TRUE;
+    }
+
+    *pPacketHeader1 = PacketHeader1;
+    *pPacketHeader2 = PacketHeader2;
+    *pPacketHeader3 = PacketHeader3;
+}
+
+static void StartI2cPacketMode(NvRmI2cControllerHandle hRmI2cCont)
+{
+    NvU32 I2cConfig;
+    // PACKET_MODE_TRANSFER_EN field of I2C Controller configuration Register
+    I2cConfig = NV_DRF_DEF(I2C, I2C_CNFG, NEW_MASTER_FSM, ENABLE);
+    I2cConfig = NV_FLD_SET_DRF_DEF(I2C, I2C_CNFG, PACKET_MODE_EN, GO, I2cConfig);
+    I2C_REGW(hRmI2cCont, I2C_CNFG, I2cConfig);
+}
+
+static void 
+DoTxFifoEmpty(
+    NvRmI2cControllerHandle hRmI2cCont, 
+    NvU32 *pFifoEmptyCount)
+{
+    NvU32 TFifoEmptyCount = 0;
+    NvU32 FifoStatus;
+    
+    // Tx Fifo should be empty. If not force to make it empty
+    FifoStatus = I2C_REGR(hRmI2cCont, FIFO_STATUS);
+    TFifoEmptyCount = NV_DRF_VAL(I2C, FIFO_STATUS, TX_FIFO_EMPTY_CNT, FifoStatus);
+    if (TFifoEmptyCount < I2C_FIFO_DEPTH)
+        ResetTxFifo(hRmI2cCont);
+
+    *pFifoEmptyCount = TFifoEmptyCount;
+}
+
+static void WriteIntMaksReg(NvRmI2cControllerHandle hRmI2cCont)
+{
+#if !USE_POLLING_METHOD
+    I2C_REGW (hRmI2cCont, INTERRUPT_MASK_REGISTER, hRmI2cCont->IntMaskReg);
+#endif
+}
+static void I2cIsr(void* args)
+{
+    NvRmI2cControllerHandle hRmI2cCont = (NvRmI2cControllerHandle)args;
+    NvU32 FifoStatus;
+    NvU32 WordCount;
+    NvU32 FilledSlots;
+    NvU32 MaxWordToRead;
+    NvBool IsFinalIntGot = NV_FALSE;
+    NvU32 FreeSlots;
+    NvU32 MaxWordToWrite;
+    // Read the Interrupt status register & PKT_STATUS
+    hRmI2cCont->ControllerStatus = I2C_REGR(hRmI2cCont, INTERRUPT_STATUS_REGISTER);
+
+    // Write one to clear in the interrupt status register
+    I2C_REGW(hRmI2cCont, INTERRUPT_STATUS_REGISTER, hRmI2cCont->ControllerStatus);
+    FifoStatus = I2C_REGR(hRmI2cCont, FIFO_STATUS);
+
+    DEBUG_I2C_READ(1, ("ISR ContStatus 0x%08x FifoStatus 0x%08x\n", 
+                                    hRmI2cCont->ControllerStatus, FifoStatus));
+
+    if (hRmI2cCont->ControllerStatus & hRmI2cCont->FinalInterrupt)
+        IsFinalIntGot = NV_TRUE;
+
+    // If any error then stop transfer.
+    if (hRmI2cCont->ControllerStatus & I2C_TRANSACTION_STATUS_ERRORS)
+    {
+        NvOsDebugPrintf("Err in I2c transfer: Controller Status 0x%08x \n",
+                                hRmI2cCont->ControllerStatus);
+        IsFinalIntGot = NV_TRUE;
+        goto FinalIntDone;
+    }
+
+    if (hRmI2cCont->IsCurrentTransferRead)
+    {
+        // If there is remianing word to read then read here from fifo.
+        if ((hRmI2cCont->WordRemaining) && (!hRmI2cCont->IsUsingApbDma))
+        {
+            DEBUG_I2C_READ(1, ("Reading RxFifo From Int\n"));
+
+            // Get RFifo full count
+            FilledSlots = NV_DRF_VAL(I2C, FIFO_STATUS, RX_FIFO_FULL_CNT, FifoStatus);
+        
+            MaxWordToRead = NV_MIN(hRmI2cCont->WordRemaining, FilledSlots);
+            for (WordCount = 0; WordCount < MaxWordToRead; ++WordCount)
+            {
+                // Read data from the I2C RX pkt FIFO Register
+                hRmI2cCont->pDataBuffer[hRmI2cCont->WordTransferred] = 
+                                        I2C_REGR(hRmI2cCont, I2C_RX_FIFO);
+                hRmI2cCont->WordTransferred++;
+            }
+            hRmI2cCont->WordRemaining -= MaxWordToRead;
+        
+            if ((IsFinalIntGot) || (hRmI2cCont->WordRemaining == 0))
+                goto FinalIntDone;
+
+            // If still want to receive more than the fifo depth then continue 
+            // the int   
+            if (hRmI2cCont->WordRemaining > I2C_FIFO_DEPTH)
+                goto IntDone;
+
+            if(hRmI2cCont->IsCurrentTransferNoStop)
+            {
+                // If remaining required read is less than fifo depth then enable the
+                // all tranfer interrupt only and disable the fifo trigger level interrupt
+                
+                if (hRmI2cCont->WordRemaining < I2C_FIFO_DEPTH)
+                    SetRxFifoTriggerLevel(hRmI2cCont, hRmI2cCont->WordRemaining);
+                    
+                hRmI2cCont->FinalInterrupt = NV_FLD_SET_DRF_DEF(I2C, INTERRUPT_MASK_REGISTER, 
+                                RFIFO_DATA_REQ_INT_EN, ENABLE, hRmI2cCont->FinalInterrupt);
+            }
+            else
+            {
+                hRmI2cCont->IntMaskReg = NV_FLD_SET_DRF_DEF(I2C, INTERRUPT_MASK_REGISTER, 
+                                          RFIFO_DATA_REQ_INT_EN, DISABLE, hRmI2cCont->IntMaskReg);
+
+                hRmI2cCont->IntMaskReg = NV_FLD_SET_DRF_DEF(I2C, INTERRUPT_MASK_REGISTER, 
+                                ALL_PACKETS_XFER_COMPLETE_INT_EN, ENABLE, hRmI2cCont->IntMaskReg);
+                                
+                
+                hRmI2cCont->FinalInterrupt = NV_FLD_SET_DRF_DEF(I2C, INTERRUPT_MASK_REGISTER, 
+                                ALL_PACKETS_XFER_COMPLETE_INT_EN, ENABLE, hRmI2cCont->FinalInterrupt);
+                WriteIntMaksReg(hRmI2cCont);
+            }
+            goto IntDone;
+        }
+    }
+    else
+    {
+        if (IsFinalIntGot)
+            goto FinalIntDone;
+
+        // If there is remaining word to write then keep writing it.
+        if (hRmI2cCont->WordRemaining)
+        {
+            DEBUG_I2C_SEND(1, ("Writing Tx from int\n"));
+            
+            // Get TFifo empty count
+            FreeSlots = NV_DRF_VAL(I2C, FIFO_STATUS, TX_FIFO_EMPTY_CNT, FifoStatus);
+            MaxWordToWrite = NV_MIN(hRmI2cCont->WordRemaining, FreeSlots);
+            for (WordCount = 0; WordCount < MaxWordToWrite; ++WordCount)
+            {
+                // Write data into the I2C TX pkt FIFO Register
+                I2C_REGW(hRmI2cCont, I2C_TX_PACKET_FIFO, 
+                        hRmI2cCont->pDataBuffer[hRmI2cCont->WordTransferred]);
+                hRmI2cCont->WordTransferred++;
+            }
+            hRmI2cCont->WordRemaining -= MaxWordToWrite;
+
+            if (hRmI2cCont->WordRemaining == 0)
+            {
+                if(hRmI2cCont->IsCurrentTransferNoStop)
+                {
+                    hRmI2cCont->FinalInterrupt = NV_FLD_SET_DRF_DEF(I2C, INTERRUPT_MASK_REGISTER, 
+                                    TFIFO_DATA_REQ_INT_EN, ENABLE, hRmI2cCont->FinalInterrupt);
+                }
+                else
+                {
+                    hRmI2cCont->IntMaskReg = NV_FLD_SET_DRF_DEF(I2C, INTERRUPT_MASK_REGISTER, 
+                                              TFIFO_DATA_REQ_INT_EN, DISABLE, hRmI2cCont->IntMaskReg);
+                
+                    hRmI2cCont->IntMaskReg = NV_FLD_SET_DRF_DEF(I2C, INTERRUPT_MASK_REGISTER, 
+                                    ALL_PACKETS_XFER_COMPLETE_INT_EN, ENABLE, hRmI2cCont->IntMaskReg);
+                                    
+                    
+                    hRmI2cCont->FinalInterrupt = NV_FLD_SET_DRF_DEF(I2C, INTERRUPT_MASK_REGISTER, 
+                                    ALL_PACKETS_XFER_COMPLETE_INT_EN, ENABLE, hRmI2cCont->FinalInterrupt);
+                    WriteIntMaksReg(hRmI2cCont);
+                }                
+            }
+        }
+        goto IntDone;
+    }
+FinalIntDone:    
+    if(IsFinalIntGot)
+    {
+        // Clear interrupt mask register, and DVC interrupt status for DVC I2C.
+        // Note that h/w clean up and use of hRmI2cCont (shared with transaction
+        // API thread) must be completed in ISR before semaphore is signaled.
+        I2C_REGW (hRmI2cCont, INTERRUPT_MASK_REGISTER, 0);
+        hRmI2cCont->IsTransferCompleted = NV_TRUE;
+        if (hRmI2cCont->ModuleId == NvRmModuleID_Dvc)
+            DVC_REGW(hRmI2cCont, STATUS_REG,
+                     NV_DRF_NUM(DVC, STATUS_REG, I2C_DONE_INTR, 1));
+        NvOsSemaphoreSignal(hRmI2cCont->I2cSyncSemaphore);
+        goto Done;
+    }
+
+    NvOsDebugPrintf("AP20 I2c Isr got unwanted interrupt IntStatus 0x%08x\n", 
+                                                    hRmI2cCont->ControllerStatus);
+    NV_ASSERT(0);
+    
+IntDone:    
+    if (hRmI2cCont->ModuleId == NvRmModuleID_Dvc)
+        DVC_REGW(hRmI2cCont, STATUS_REG, NV_DRF_NUM(DVC, STATUS_REG, I2C_DONE_INTR, 1));
+Done:        
+    NvRmInterruptDone(hRmI2cCont->I2CInterruptHandle);
+}
+
+#if USE_POLLING_METHOD
+static NvError WaitForTransactionCompletesPolling(
+    NvRmI2cControllerHandle hRmI2cCont, 
+    NvU32 Timeout)
+{
+    NvU32 RemainingTime;
+    RemainingTime = (Timeout == NV_WAIT_INFINITE)?Timeout:Timeout*1000;
+    do {
+        NvOsWaitUS(I2C_POLLING_TIMEOUT_STEP_USEC);
+
+        // Read the Interrupt status register & PKT_STATUS
+        hRmI2cCont->ControllerStatus = I2C_REGR(hRmI2cCont, INTERRUPT_STATUS_REGISTER);
+        if (hRmI2cCont->ControllerStatus & hRmI2cCont->IntMaskReg)
+        {
+            I2cIsr(hRmI2cCont);
+            if (hRmI2cCont->IsTransferCompleted)
+                break;
+        }
+
+        if (Timeout != NV_WAIT_INFINITE)
+            RemainingTime = (RemainingTime > I2C_POLLING_TIMEOUT_STEP_USEC)? 
+                                    (RemainingTime - I2C_POLLING_TIMEOUT_STEP_USEC): 0;
+    } while(RemainingTime);
+
+    if (!RemainingTime)
+        return NvError_Timeout;
+
+    return NvSuccess;
+}
+#endif
+
+static NvError WaitForTransactionCompletes(
+    NvRmI2cControllerHandle hRmI2cCont, 
+    NvU32 Timeout)
+{
+    NvError Error;
+
+#if USE_POLLING_METHOD
+    hRmI2cCont->IsTransferCompleted = NV_FALSE;
+    Error = WaitForTransactionCompletesPolling(hRmI2cCont, hRmI2cCont->timeout);
+#else
+    // Wait for the  Transfer completes
+    Error = NvOsSemaphoreWaitTimeout(hRmI2cCont->I2cSyncSemaphore, Timeout);
+#endif
+    return Error;
+}
+
+
+static NvError 
+DoOneReceiveTransaction(
+    NvRmI2cControllerHandle hRmI2cCont,
+    NvU32 PacketId,
+    NvU8*  pBuffer,
+    NvRmI2cTransactionInfo *pTransaction,
+    NvU32* pBytesTransferred)
+{
+    NvU32 WordsToRead = 0;
+    NvU32 TFifoEmptyCount = 0;
+    NvError Error = NvSuccess;
+    NvU32 PacketHeader1;
+    NvU32 PacketHeader2;
+    NvU32 PacketHeader3;
+    NvU32 IntMaskReg;
+    NvRmDmaModuleID DmaModuleId = NvRmDmaModuleID_I2c;
+    NvU32 BytesRead;
+
+
+    hRmI2cCont->WordTransferred = 0;
+    hRmI2cCont->WordRemaining = 0;
+    hRmI2cCont->TransCountFromLastDmaUsage++;
+
+    GetPacketHeaders(hRmI2cCont, pTransaction, PacketId, &PacketHeader1, 
+                                            &PacketHeader2, &PacketHeader3);
+    
+    DoTxFifoEmpty(hRmI2cCont, &TFifoEmptyCount);
+    
+    // Enable all possible i2c controller error.
+    IntMaskReg  = I2C_ERRORS_INTERRUPT_MASK;
+
+    if (!hRmI2cCont->IsCurrentTransferNoAck)
+        IntMaskReg = NV_FLD_SET_DRF_DEF(I2C, INTERRUPT_MASK_REGISTER, 
+                                    NOACK_INT_EN, ENABLE, IntMaskReg);
+
+    hRmI2cCont->FinalInterrupt = IntMaskReg;
+
+    // Words to read 
+    WordsToRead = BYTES_TO_WORD(pTransaction->NumBytes);
+    hRmI2cCont->WordTransferred = 0;
+    hRmI2cCont->WordRemaining = WordsToRead;
+
+    hRmI2cCont->IsTransferCompleted = NV_FALSE;
+
+    // If requested size is more than cpu transaction thresold then use dma.
+    if ((hRmI2cCont->DmaBufferSize) && 
+            (hRmI2cCont->WordRemaining > I2C_MAX_WORD_TO_USE_CPU))
+    {
+        if (!hRmI2cCont->IsApbDmaAllocated)
+        {
+            if (hRmI2cCont->ModuleId == NvRmModuleID_Dvc)
+                DmaModuleId =NvRmDmaModuleID_Dvc;
+                
+            Error = NvRmDmaAllocate(hRmI2cCont->hRmDevice, &hRmI2cCont->hRmDma,
+                             NV_FALSE, NvRmDmaPriority_High, DmaModuleId,
+                             hRmI2cCont->Instance);
+            if (!Error)
+                hRmI2cCont->IsApbDmaAllocated = NV_TRUE;
+            Error = NvSuccess;
+        }
+        if (!hRmI2cCont->IsApbDmaAllocated)
+            goto CpuBasedReading;
+        
+        hRmI2cCont->IsUsingApbDma = NV_TRUE;
+        hRmI2cCont->TransCountFromLastDmaUsage = 0;
+        hRmI2cCont->RxDmaReq.TransferSize = hRmI2cCont->WordRemaining << 2;
+        SetRxFifoTriggerLevel(hRmI2cCont, 1);
+        if (hRmI2cCont->IsCurrentTransferNoStop)
+        {
+#if USE_POLLING_METHOD
+            goto CpuBasedReading;
+#else
+            Error = NvRmDmaStartDmaTransfer(hRmI2cCont->hRmDma, &hRmI2cCont->RxDmaReq,
+                    NvRmDmaDirection_Forward, 0, hRmI2cCont->I2cSyncSemaphore);
+#endif                    
+        }
+        else
+        {
+            Error = NvRmDmaStartDmaTransfer(hRmI2cCont->hRmDma, &hRmI2cCont->RxDmaReq,
+                    NvRmDmaDirection_Forward, 0, NULL);
+        }
+        if (!Error)
+        {
+            hRmI2cCont->ControllerStatus = 0;
+            I2C_REGW(hRmI2cCont, I2C_TX_PACKET_FIFO, PacketHeader1);
+            I2C_REGW(hRmI2cCont, I2C_TX_PACKET_FIFO, PacketHeader2);
+            
+            // Write I2C specific header
+            I2C_REGW(hRmI2cCont, I2C_TX_PACKET_FIFO, PacketHeader3);
+        
+            if (!hRmI2cCont->IsCurrentTransferNoStop)
+            {
+                IntMaskReg = NV_FLD_SET_DRF_DEF(I2C, INTERRUPT_MASK_REGISTER, 
+                                ALL_PACKETS_XFER_COMPLETE_INT_EN, ENABLE, IntMaskReg);
+                hRmI2cCont->FinalInterrupt = IntMaskReg;
+            }
+            hRmI2cCont->IntMaskReg = IntMaskReg;
+            WriteIntMaksReg(hRmI2cCont);
+            goto WaitForCompletion;
+        }
+        Error = NvSuccess;
+    }
+
+CpuBasedReading:    
+    hRmI2cCont->IsUsingApbDma = NV_FALSE;
+
+    // Enable the Rx trigger level interrupt if the word to read is more than
+    // fifo depth or no stop transfer is selected
+    if ((hRmI2cCont->WordRemaining > I2C_FIFO_DEPTH) ||
+                                hRmI2cCont->IsCurrentTransferNoStop)
+    {
+        SetRxFifoTriggerLevel(hRmI2cCont, hRmI2cCont->WordRemaining);
+        IntMaskReg = NV_FLD_SET_DRF_DEF(I2C, INTERRUPT_MASK_REGISTER, 
+                                    RFIFO_DATA_REQ_INT_EN, ENABLE, IntMaskReg);
+    }
+    else
+    {
+        IntMaskReg = NV_FLD_SET_DRF_DEF(I2C, INTERRUPT_MASK_REGISTER, 
+                                    ALL_PACKETS_XFER_COMPLETE_INT_EN, ENABLE, IntMaskReg);
+        hRmI2cCont->FinalInterrupt = IntMaskReg;
+    }
+    
+    hRmI2cCont->IntMaskReg = IntMaskReg;
+
+    WriteIntMaksReg(hRmI2cCont);
+
+    //Write Generic Header1 & 2
+    I2C_REGW(hRmI2cCont, I2C_TX_PACKET_FIFO, PacketHeader1);
+    I2C_REGW(hRmI2cCont, I2C_TX_PACKET_FIFO, PacketHeader2);
+    
+    // Write I2C specific header
+    I2C_REGW(hRmI2cCont, I2C_TX_PACKET_FIFO, PacketHeader3);
+
+WaitForCompletion:
+    Error = WaitForTransactionCompletes(hRmI2cCont, hRmI2cCont->timeout);
+    if (Error == NvSuccess)
+    {
+        hRmI2cCont->I2cTransferStatus = NvError_I2cReadFailed;
+        if (hRmI2cCont->ControllerStatus & I2C_TRANSACTION_STATUS_ERRORS)
+        {
+            if (hRmI2cCont->ControllerStatus & I2C_ARBITRATION_LOST_ERRORS)
+                hRmI2cCont->I2cTransferStatus = NvError_I2cArbitrationFailed;
+            else
+                hRmI2cCont->I2cTransferStatus = NvError_I2cInternalError;
+
+            goto ReadExitWithReset;
+        }
+        else
+        {
+            if (!hRmI2cCont->IsCurrentTransferNoAck)
+            {
+                if(hRmI2cCont->ControllerStatus & 
+                    NV_DRF_DEF(I2C, INTERRUPT_MASK_REGISTER, NOACK_INT_EN, ENABLE))
+                {    
+                    hRmI2cCont->I2cTransferStatus = NvError_I2cDeviceNotFound;
+                    goto ReadExitWithReset;
+                }
+            }
+            // Memcopy fifo back to actual buffer given by client
+            if (hRmI2cCont->IsUsingApbDma)
+            {
+                BytesRead = NV_MIN(pTransaction->NumBytes, 
+                                        hRmI2cCont->RxDmaReq.TransferSize);
+                NvOsMemcpy(pBuffer, (NvU8* )hRmI2cCont->pDmaBuffer, BytesRead);
+            }
+            else
+            {
+                BytesRead = NV_MIN(pTransaction->NumBytes, 
+                                        (4*hRmI2cCont->WordTransferred));
+                if (BytesRead != pTransaction->NumBytes)
+                {
+                    hRmI2cCont->I2cTransferStatus = NvError_I2cReadFailed;
+                    goto ReadExitWithReset;
+                }
+                NvOsMemcpy(pBuffer, (NvU8* )hRmI2cCont->pDataBuffer, BytesRead);
+            }
+
+            if (pBytesTransferred != NULL)
+                *pBytesTransferred = BytesRead;
+
+            
+            hRmI2cCont->I2cTransferStatus = NvSuccess;
+            goto ReadExit;
+        }
+    }
+    else if (Error == NvError_Timeout)
+    {
+        DEBUG_I2C_READ(1, ("Read Timeout Error \n"));
+        hRmI2cCont->I2cTransferStatus = NvError_Timeout;
+    }
+
+ReadExitWithReset:
+    // If we reach here then there is something wrong in transfer, reset the module.
+    if (hRmI2cCont->IsUsingApbDma)
+        NvRmDmaAbort(hRmI2cCont->hRmDma);
+
+    // If there is NACK error, then there is possibilty that i2c controller is 
+    // still busy to send the stop signal.
+    // Wait for 2x of i2c clock period is recommended, waiting for 1 ms to use 
+    // the NvOsMsSleep api.
+    NvOsSleepMS(1);
+        
+    NvRmModuleReset(hRmI2cCont->hRmDevice, 
+                NVRM_MODULE_ID(hRmI2cCont->ModuleId, hRmI2cCont->Instance));
+    RESET_SEMA_COUNT(hRmI2cCont->I2cSyncSemaphore);
+ReadExit:    
+    DEBUG_I2C_READ(1, ("Read Transfer Status 0x%08x \n", hRmI2cCont->I2cTransferStatus));
+    
+    // Time to free dma??
+    if ((hRmI2cCont->IsApbDmaAllocated) && 
+        (hRmI2cCont->TransCountFromLastDmaUsage > HOLDING_DMA_TRANSACTION_COUNT))
+    {
+        NvRmDmaFree(hRmI2cCont->hRmDma);
+        hRmI2cCont->hRmDma = NULL;
+        hRmI2cCont->IsApbDmaAllocated = NV_FALSE;
+    }
+    return hRmI2cCont->I2cTransferStatus;
+}
+
+
+static NvError 
+DoOneSendTransaction(
+    NvRmI2cControllerHandle hRmI2cCont,
+    NvU32 PacketId,
+    NvU8*  pBuffer,
+    NvRmI2cTransactionInfo *pTransaction,
+    NvU32* pBytesTransferred)
+{
+    NvU32 WordsToSend = 0;
+    NvU32 TFifoEmptyCount = 0;
+    NvError Error = NvSuccess;
+    NvU32 PacketHeader1;
+    NvU32 PacketHeader2;
+    NvU32 PacketHeader3;
+    NvU32 IntMaskReg;
+    NvU32 WordCount;
+    NvRmDmaModuleID DmaModuleId = NvRmDmaModuleID_I2c;
+
+    hRmI2cCont->WordTransferred = 0;
+    hRmI2cCont->WordRemaining = 0;
+    hRmI2cCont->TransCountFromLastDmaUsage++;
+
+    GetPacketHeaders(hRmI2cCont, pTransaction, PacketId, &PacketHeader1, 
+                                            &PacketHeader2, &PacketHeader3);
+    DoTxFifoEmpty(hRmI2cCont, &TFifoEmptyCount);
+    
+    // Enable all possible i2c controller error.
+    IntMaskReg  = I2C_ERRORS_INTERRUPT_MASK;
+
+    if (!hRmI2cCont->IsCurrentTransferNoAck)
+        IntMaskReg = NV_FLD_SET_DRF_DEF(I2C, INTERRUPT_MASK_REGISTER, 
+                                    NOACK_INT_EN, ENABLE, IntMaskReg);
+
+    hRmI2cCont->FinalInterrupt = IntMaskReg;
+
+    // Words to write 
+    WordsToSend = BYTES_TO_WORD(pTransaction->NumBytes);
+    hRmI2cCont->WordTransferred = 0;
+    hRmI2cCont->WordRemaining = WordsToSend;
+    hRmI2cCont->IsTransferCompleted = NV_FALSE;
+
+    if ((hRmI2cCont->DmaBufferSize) && 
+            (hRmI2cCont->WordRemaining > I2C_MAX_WORD_TO_USE_CPU))
+    {
+        if (!hRmI2cCont->IsApbDmaAllocated)
+        {
+            if (hRmI2cCont->ModuleId == NvRmModuleID_Dvc)
+                DmaModuleId =NvRmDmaModuleID_Dvc;
+                
+            Error = NvRmDmaAllocate(hRmI2cCont->hRmDevice, &hRmI2cCont->hRmDma,
+                             NV_FALSE, NvRmDmaPriority_High, DmaModuleId,
+                             hRmI2cCont->Instance);
+            if (!Error)
+                hRmI2cCont->IsApbDmaAllocated = NV_TRUE;
+            Error = NvSuccess;
+        }
+        if (!hRmI2cCont->IsApbDmaAllocated)
+            goto CpuBasedWriting;
+    
+        hRmI2cCont->IsUsingApbDma = NV_TRUE;
+        hRmI2cCont->TransCountFromLastDmaUsage = 0;
+        hRmI2cCont->pDmaBuffer[0] = PacketHeader1;
+        hRmI2cCont->pDmaBuffer[1] = PacketHeader2;
+        hRmI2cCont->pDmaBuffer[2] = PacketHeader3;
+        hRmI2cCont->TxDmaReq.TransferSize = (hRmI2cCont->WordRemaining + 3) << 2;
+        NvOsMemcpy(hRmI2cCont->pDmaBuffer + 3, (void *)pBuffer, pTransaction->NumBytes);
+        SetTxFifoTriggerLevel(hRmI2cCont, 8);
+        Error = NvRmDmaStartDmaTransfer(hRmI2cCont->hRmDma, &hRmI2cCont->TxDmaReq,
+                NvRmDmaDirection_Forward, 0, NULL);
+        if (!Error)
+        {
+            hRmI2cCont->WordRemaining = 0;
+            if (hRmI2cCont->IsCurrentTransferNoStop)
+            {
+                IntMaskReg = NV_FLD_SET_DRF_DEF(I2C, INTERRUPT_MASK_REGISTER, 
+                                        TFIFO_DATA_REQ_INT_EN, ENABLE, IntMaskReg);
+                hRmI2cCont->FinalInterrupt = IntMaskReg;                        
+            }
+            else
+            {
+                IntMaskReg = NV_FLD_SET_DRF_DEF(I2C, INTERRUPT_MASK_REGISTER, 
+                                ALL_PACKETS_XFER_COMPLETE_INT_EN, ENABLE, IntMaskReg);
+                hRmI2cCont->FinalInterrupt = IntMaskReg;
+            }
+            goto WaitForCompletion;
+        }
+        
+//        NvOsDebugPrintf("Send Using Dma\n");
+        Error = NvSuccess;
+    }
+
+CpuBasedWriting:
+    hRmI2cCont->IsUsingApbDma = NV_FALSE;
+
+    //Write Generic Header1 & 2
+    I2C_REGW(hRmI2cCont, I2C_TX_PACKET_FIFO, PacketHeader1);
+    I2C_REGW(hRmI2cCont, I2C_TX_PACKET_FIFO, PacketHeader2);
+    
+    // Write I2C specific header
+    I2C_REGW(hRmI2cCont, I2C_TX_PACKET_FIFO, PacketHeader3);
+    
+    TFifoEmptyCount -= 3;
+    
+    if (hRmI2cCont->WordRemaining)
+    {
+        NvOsMemcpy(hRmI2cCont->pDataBuffer, (void *)pBuffer, pTransaction->NumBytes);
+        
+        WordsToSend = NV_MIN(hRmI2cCont->WordRemaining, TFifoEmptyCount);
+        for (WordCount = 0; WordCount < WordsToSend; WordCount++)
+        {
+            // Write data into the I2C TX pkt FIFO Register
+            I2C_REGW(hRmI2cCont, I2C_TX_PACKET_FIFO, 
+                        hRmI2cCont->pDataBuffer[hRmI2cCont->WordTransferred]);
+            hRmI2cCont->WordTransferred++;
+        }
+        hRmI2cCont->WordRemaining -= WordsToSend;
+
+        if (hRmI2cCont->WordRemaining == 0)
+        {
+            if (hRmI2cCont->IsCurrentTransferNoStop)
+            {
+                SetTxFifoTriggerLevel(hRmI2cCont, 8);
+                IntMaskReg = NV_FLD_SET_DRF_DEF(I2C, INTERRUPT_MASK_REGISTER, 
+                                        TFIFO_DATA_REQ_INT_EN, ENABLE, IntMaskReg);
+                hRmI2cCont->FinalInterrupt = IntMaskReg;                        
+            }
+            else
+            {
+                IntMaskReg = NV_FLD_SET_DRF_DEF(I2C, INTERRUPT_MASK_REGISTER, 
+                                ALL_PACKETS_XFER_COMPLETE_INT_EN, ENABLE, IntMaskReg);
+                hRmI2cCont->FinalInterrupt = IntMaskReg;
+            }
+        }
+        else
+        {
+            SetTxFifoTriggerLevel(hRmI2cCont, 8);
+            IntMaskReg = NV_FLD_SET_DRF_DEF(I2C, INTERRUPT_MASK_REGISTER, 
+                                    TFIFO_DATA_REQ_INT_EN, ENABLE, IntMaskReg);
+        }
+    }
+
+WaitForCompletion:
+    hRmI2cCont->IntMaskReg = IntMaskReg;
+    WriteIntMaksReg(hRmI2cCont);
+    Error = WaitForTransactionCompletes(hRmI2cCont, hRmI2cCont->timeout);
+    if (Error == NvSuccess)
+    {
+        hRmI2cCont->I2cTransferStatus = NvError_I2cWriteFailed;
+        if (hRmI2cCont->ControllerStatus & I2C_TRANSACTION_STATUS_ERRORS)
+        {
+            if (hRmI2cCont->ControllerStatus & I2C_ARBITRATION_LOST_ERRORS)
+                hRmI2cCont->I2cTransferStatus = NvError_I2cArbitrationFailed;
+            else
+                hRmI2cCont->I2cTransferStatus = NvError_I2cInternalError;
+            goto WriteExitWithReset;
+        }   
+        else
+        {
+            if (!hRmI2cCont->IsCurrentTransferNoAck)
+            {
+                if(hRmI2cCont->ControllerStatus & 
+                    NV_DRF_DEF(I2C, INTERRUPT_MASK_REGISTER, NOACK_INT_EN, ENABLE))
+                {    
+                    hRmI2cCont->I2cTransferStatus = NvError_I2cDeviceNotFound;
+                    goto WriteExitWithReset;
+                }
+            }   
+            if (pBytesTransferred != NULL)
+                *pBytesTransferred = pTransaction->NumBytes;
+            hRmI2cCont->I2cTransferStatus = NvSuccess;
+            goto WriteExit;
+        }
+    }
+    else if (Error == NvError_Timeout)
+    {
+        DEBUG_I2C_SEND(1, ("SEND Timeout Error \n"));
+        hRmI2cCont->I2cTransferStatus = NvError_Timeout;
+    }
+    
+WriteExitWithReset:
+    if (hRmI2cCont->IsUsingApbDma)
+        NvRmDmaAbort(hRmI2cCont->hRmDma);
+
+    // If there is NACK error, then there is possibilty that i2c controller is 
+    // still busy to send the stop signal.
+    // Wait for 2x of i2c clock period is recommended, waiting for 1 ms to use 
+    // the NvOsMsSleep api.
+    NvOsSleepMS(1);
+    
+    // If we reach here then there is something wrong in transfer, reset the module.
+    NvRmModuleReset(hRmI2cCont->hRmDevice, 
+                NVRM_MODULE_ID(hRmI2cCont->ModuleId, hRmI2cCont->Instance));
+    RESET_SEMA_COUNT(hRmI2cCont->I2cSyncSemaphore);
+WriteExit:    
+    DEBUG_I2C_SEND(1, ("Send Transfer Status 0x%08x \n", hRmI2cCont->I2cTransferStatus));
+
+    // Time to free dma??
+    if ((hRmI2cCont->IsApbDmaAllocated) && 
+        (hRmI2cCont->TransCountFromLastDmaUsage > HOLDING_DMA_TRANSACTION_COUNT))
+    {
+        NvRmDmaFree(hRmI2cCont->hRmDma);
+        hRmI2cCont->hRmDma = NULL;
+        hRmI2cCont->IsApbDmaAllocated = NV_FALSE;
+    }
+    
+    return hRmI2cCont->I2cTransferStatus;
+}
+
+
+static NvError 
+DoMultiReceiveTransaction(
+    NvRmI2cControllerHandle hRmI2cCont,
+    NvU32 *pPacketId,
+    NvU8*  pBuffer,
+    const NvRmI2cTransactionInfo *pTransaction,
+    NvU32* pBytesTransferred)
+{
+    NvRmI2cTransactionInfo Transaction;
+    NvU32 BytesTransferredYet = 0;
+    NvU32 TotalBytesRequested;
+    NvU8 *pReadBuffer = pBuffer;
+    NvError Error = NvSuccess;
+    NvU32 CurrBytesRequested;
+    NvU32 PacketId;
+    NvU32 BytesTransferred = 0;
+
+    Transaction.Is10BitAddress = pTransaction->Is10BitAddress;
+    Transaction.Address = pTransaction->Address;
+    TotalBytesRequested = pTransaction->NumBytes;
+    PacketId = *pPacketId;
+    while (TotalBytesRequested)
+    {
+        Transaction.Flags = pTransaction->Flags;
+        CurrBytesRequested = TotalBytesRequested;
+        if (TotalBytesRequested > MAX_I2C_ONE_TRANSACTION_SIZE)
+        {
+            Transaction.Flags |= NVRM_I2C_NOSTOP;
+            CurrBytesRequested = MAX_I2C_ONE_TRANSACTION_SIZE;
+        }
+        Transaction.NumBytes = CurrBytesRequested;
+        Error = DoOneReceiveTransaction(hRmI2cCont, PacketId, pReadBuffer, 
+                                &Transaction, &BytesTransferred);
+        if (Error)
+            break;
+        BytesTransferredYet += CurrBytesRequested;  
+        pReadBuffer += CurrBytesRequested;
+        TotalBytesRequested -= CurrBytesRequested;
+        PacketId++;
+        I2C_REGW(hRmI2cCont, INTERRUPT_MASK_REGISTER, 0);
+    }
+    *pPacketId = PacketId;
+    *pBytesTransferred = BytesTransferredYet;
+    return Error;
+}
+
+static NvError
+DoMultiSendTransaction(
+    NvRmI2cControllerHandle hRmI2cCont,
+    NvU32 *pPacketId,
+    NvU8*  pBuffer,
+    const NvRmI2cTransactionInfo *pTransaction,
+    NvU32* pBytesTransferred)
+
+{
+    NvRmI2cTransactionInfo Transaction;
+    NvU32 BytesTransferredYet = 0;
+    NvU32 TotalBytesRequested;
+    NvU8 *pReadBuffer = pBuffer;
+    NvError Error = NvSuccess;
+    NvU32 CurrBytesRequested;
+    NvU32 PacketId;
+    NvU32 BytesTransferred = 0;
+    
+    Transaction.Is10BitAddress = pTransaction->Is10BitAddress;
+    Transaction.Address = pTransaction->Address;
+    TotalBytesRequested = pTransaction->NumBytes;
+    PacketId = *pPacketId;
+    while (TotalBytesRequested)
+    {
+        Transaction.Flags = pTransaction->Flags;
+        CurrBytesRequested = TotalBytesRequested;
+        if (TotalBytesRequested > MAX_I2C_ONE_TRANSACTION_SIZE)
+        {
+            Transaction.Flags |= NVRM_I2C_NOSTOP;
+            CurrBytesRequested = MAX_I2C_ONE_TRANSACTION_SIZE;
+        }
+        Transaction.NumBytes = CurrBytesRequested;
+        Error = DoOneSendTransaction(hRmI2cCont, PacketId, pReadBuffer, 
+                                &Transaction, &BytesTransferred);
+        if (Error)
+            break;
+        BytesTransferredYet += CurrBytesRequested;  
+        pReadBuffer += CurrBytesRequested;
+        TotalBytesRequested -= CurrBytesRequested;
+        PacketId++;
+        I2C_REGW(hRmI2cCont, INTERRUPT_MASK_REGISTER, 0);
+    }
+    *pPacketId = PacketId;
+    *pBytesTransferred = BytesTransferred;
+    return Error;
+}
+
+
+static NvError 
+AP20RmI2cReceive(
+    NvRmI2cControllerHandle hRmI2cCont,
+    NvU8*  pBuffer,
+    const NvRmI2cTransactionInfo *pTransaction,
+    NvU32* pBytesTransferred)
+{
+    NvError Error = NvSuccess;
+    NvU32 PacketId = 1;
+    
+    NV_ASSERT(pBuffer);
+    NV_ASSERT(pTransaction->NumBytes > 0);
+
+    DEBUG_I2C_TRACE(1, ("AP20RmI2cReceive()++ 0x%08x and add 0x%02x\n", pTransaction->NumBytes, Transaction.Address));
+
+    if (hRmI2cCont->ModuleId == NvRmModuleID_Dvc)
+        DoDvcI2cControlInitialization(hRmI2cCont);
+        
+    // Clear interrupt mask register to avoid any false interrupts.
+    I2C_REGW(hRmI2cCont, INTERRUPT_MASK_REGISTER, 0);
+    
+    // Start the packet mode
+    StartI2cPacketMode(hRmI2cCont);
+
+    Error = DoMultiReceiveTransaction(hRmI2cCont, &PacketId, pBuffer, 
+                                      pTransaction, pBytesTransferred);
+    DEBUG_I2C_TRACE(1, ("AP20RmI2cReceive()-- 0x%08x\n", Error));
+    return Error;
+}
+
+
+static NvError
+AP20RmI2cSend(
+    NvRmI2cControllerHandle hRmI2cCont,
+    NvU8*  pBuffer,
+    const NvRmI2cTransactionInfo *pTransaction,
+    NvU32* pBytesTransferred)
+{
+    NvError Error = NvSuccess;
+    NvU32 PacketId = 1;
+
+    NV_ASSERT(pBuffer);
+    NV_ASSERT(pTransaction->NumBytes > 0);
+
+    DEBUG_I2C_TRACE(1, ("AP20RmI2cSend()++ 0x%08x and 0x%02x\n", pTransaction->NumBytes, Transaction.Address));
+
+    if (hRmI2cCont->ModuleId == NvRmModuleID_Dvc)
+        DoDvcI2cControlInitialization(hRmI2cCont);
+
+    // Clear interrupt mask register to avoid any false interrupts.
+    I2C_REGW(hRmI2cCont, INTERRUPT_MASK_REGISTER, 0);
+    
+    // Start the packet mode
+    StartI2cPacketMode(hRmI2cCont);
+
+    Error = DoMultiSendTransaction(hRmI2cCont, &PacketId, pBuffer, 
+                                   pTransaction, pBytesTransferred);
+    DEBUG_I2C_TRACE(1, ("AP20RmI2cSend()-- 0x%08x\n", Error));
+    return Error;
+}
+
+static NvError
+AP20RmI2cRepeatStartTransaction(
+    NvRmI2cControllerHandle hRmI2cCont,
+    NvU8* pBuffer,
+    NvRmI2cTransactionInfo *pTransactions,
+    NvU32 NoOfTransations)
+{
+    NvError Error = NvSuccess;
+    NvU8 *pReqBuffer = pBuffer;
+    NvU32 BytesSend;
+    NvU32 BytesRecvd;
+    NvU32 PacketId;
+    NvU32 TransCount;
+    
+    NV_ASSERT(pBuffer);
+    NV_ASSERT(pTransactions);
+    NV_ASSERT(pBuffer);
+    
+    DEBUG_I2C_TRACE(1, ("AP20RmI2cRepeatStartTransaction()++ 0x%08x and 0x%02x\n", NoOfTransations, pTransactions[0].Address));
+
+    if (hRmI2cCont->ModuleId == NvRmModuleID_Dvc)
+    {    
+        DoDvcI2cControlInitialization(hRmI2cCont);
+        UseDvcI2cNewSlave(hRmI2cCont);
+    }
+
+    // Clear interrupt mask register to avoid any false interrupts.
+    I2C_REGW(hRmI2cCont, INTERRUPT_MASK_REGISTER, 0);
+    
+    // Start the packet mode
+    StartI2cPacketMode(hRmI2cCont);
+
+    PacketId = 1;
+    for (TransCount = 0; TransCount < NoOfTransations; TransCount++)
+    {
+        if (pTransactions[TransCount].Flags & NVRM_I2C_WRITE) 
+        {
+            Error = DoMultiSendTransaction(hRmI2cCont, &PacketId, 
+                        pReqBuffer, &pTransactions[TransCount], &BytesSend);
+        }
+        else
+        {
+            Error = DoMultiReceiveTransaction(hRmI2cCont, &PacketId, 
+                        pReqBuffer, &pTransactions[TransCount], &BytesRecvd);
+        }
+        if (Error)
+        {
+            DEBUG_I2C_TRACE(1, ("AP20RmI2cRepeatStartTransaction()-- 0x%08x at Transaction %d \n", Error, TransCount));
+            break;
+        }    
+        pReqBuffer += pTransactions[TransCount].NumBytes;
+        
+        I2C_REGW(hRmI2cCont, INTERRUPT_MASK_REGISTER, 0);
+        PacketId++;
+    }
+    DEBUG_I2C_TRACE(1, ("AP20RmI2cRepeatStartTransaction()-- 0x%08x at Transaction %d \n", Error, TransCount));
+    return Error;
+}
+
+static NvBool AP20RmI2cGetGpioPins(
+    NvRmI2cControllerHandle hRmI2cCont,
+    NvU32 I2cPinMap,
+    NvU32 *pScl,
+    NvU32 *pSda)
+{
+    NvU32 SclPin = 0;
+    NvU32 SdaPin = 0;
+    NvU32 SclPort = 0;
+    NvU32 SdaPort = 0;
+    NvBool Result = NV_TRUE;
+
+    NV_ASSERT((pScl!=NULL) && (pSda!=NULL));
+
+    if (hRmI2cCont->ModuleId == NvRmModuleID_I2c)
+    {
+        switch ((hRmI2cCont->Instance<<4) | I2cPinMap)
+        {
+            case ((0<<4) | 1):
+                SclPort = 'c' - 'a';
+                SdaPort = 'c' - 'a';
+                SclPin = 4;
+                SdaPin = 5;
+                break;
+            case ((0<<4) | 2):
+                SclPort = 'k' - 'a';
+                SdaPort = 'k' - 'a';
+                SclPin = 5;
+                SdaPin = 6;
+                break;
+            case ((0<<4) | 3):
+                SclPort = 'w' - 'a';
+                SdaPort = 'w' - 'a';
+                SclPin = 2;
+                SdaPin = 3;
+                break;
+                /*  NOTE:  The pins used by pin map 1 for instance 1 are not
+                 *  connected to a GPIO controller (DDC pins), so the software
+                 *  fallback is not supported for them.  */
+            case ((1<<4) | 2):
+                SclPort = 't' - 'a';
+                SdaPort = 't' - 'a';
+                SclPin = 5;
+                SdaPin = 6;
+                break;
+            case ((2<<4) | 1):
+                //  Port 'BB'
+                SclPort = 'z' - 'a' + 2;
+                SdaPort = 'z' - 'a' + 2;
+                SclPin = 2;
+                SdaPin = 3;
+                break;
+            default:
+                Result = NV_FALSE;
+        }
+    }
+    else if ((hRmI2cCont->ModuleId == NvRmModuleID_Dvc) &&
+                 (hRmI2cCont->Instance == 0) &&
+                     (I2cPinMap == NvOdmI2cPmuPinMap_Config1))
+    {
+        SclPin = 6;
+        SdaPin = 7;
+        SclPort = 'z' - 'a';
+        SdaPort = 'z' - 'a';
+    }
+    else
+        Result = NV_FALSE;
+
+    *pScl = (SclPin | (SclPort<<16));
+    *pSda = (SdaPin | (SdaPort<<16));
+    return Result;
+}
+
+static void AP20RmI2cClose(NvRmI2cControllerHandle hRmI2cCont)
+{
+
+    if (hRmI2cCont->I2cSyncSemaphore)
+    {
+#if !USE_POLLING_METHOD
+        NvRmInterruptUnregister(hRmI2cCont->hRmDevice, hRmI2cCont->I2CInterruptHandle);
+#endif
+        NvOsSemaphoreDestroy(hRmI2cCont->I2cSyncSemaphore);
+        hRmI2cCont->I2cSyncSemaphore = NULL;
+        hRmI2cCont->I2CInterruptHandle = NULL;
+    }
+
+    if (hRmI2cCont->pCpuBuffer)
+    {
+        NvOsFree(hRmI2cCont->pCpuBuffer);
+        hRmI2cCont->pCpuBuffer = NULL;
+        hRmI2cCont->pDataBuffer = NULL;
+    }
+
+    if (hRmI2cCont->hRmDma)
+    {
+        NvRmDmaAbort(hRmI2cCont->hRmDma);
+        NvRmDmaFree(hRmI2cCont->hRmDma);
+    }
+    
+    DestroyDmaTransferBuffer(hRmI2cCont->hRmMemory, hRmI2cCont->pDmaBuffer,
+                hRmI2cCont->DmaBufferSize);
+
+    hRmI2cCont->hRmDma = NULL;
+    hRmI2cCont->hRmMemory = NULL;
+    hRmI2cCont->DmaBuffPhysAdd = 0;
+    hRmI2cCont->pDmaBuffer = NULL;
+
+    hRmI2cCont->receive = 0;
+    hRmI2cCont->send = 0;
+    hRmI2cCont->repeatStart = 0;
+    hRmI2cCont->close = 0;
+    hRmI2cCont->GetGpioPins = 0;
+}
+
+NvError AP20RmI2cOpen(NvRmI2cControllerHandle hRmI2cCont)
+{
+    NvError Error = NvSuccess;
+#if !USE_POLLING_METHOD
+    NvU32 IrqList;
+    NvOsInterruptHandler IntHandlers = I2cIsr;
+#endif
+    NvU32 RxFifoPhyAddress;
+    NvU32 TxFifoPhyAddress;
+    
+    NV_ASSERT(hRmI2cCont);
+    DEBUG_I2C_TRACE(1, ("AP20RmI2cOpen\n"));
+
+    // Polulate the structures 
+    hRmI2cCont->receive = AP20RmI2cReceive;
+    hRmI2cCont->send = AP20RmI2cSend;
+    hRmI2cCont->repeatStart = AP20RmI2cRepeatStartTransaction;
+    hRmI2cCont->close = AP20RmI2cClose;
+    hRmI2cCont->GetGpioPins =  AP20RmI2cGetGpioPins;
+    hRmI2cCont->I2cRegisterOffset = I2C_I2C_CNFG_0;
+    hRmI2cCont->ControllerId = hRmI2cCont->Instance;
+
+    hRmI2cCont->hRmDma = NULL;
+    hRmI2cCont->hRmMemory = NULL;
+    hRmI2cCont->DmaBuffPhysAdd = 0;
+    hRmI2cCont->pDmaBuffer = NULL;
+
+    hRmI2cCont->pCpuBuffer = NULL;
+    hRmI2cCont->pDataBuffer = NULL;
+    hRmI2cCont->I2cSyncSemaphore = NULL;
+    hRmI2cCont->I2CInterruptHandle = NULL;
+    hRmI2cCont->TransCountFromLastDmaUsage = 0;
+
+    TxFifoPhyAddress = hRmI2cCont->I2cRegisterOffset + I2C_I2C_TX_PACKET_FIFO_0;
+    RxFifoPhyAddress = hRmI2cCont->I2cRegisterOffset + I2C_I2C_RX_FIFO_0;
+    
+    if (hRmI2cCont->ModuleId == NvRmModuleID_Dvc)
+    {
+        hRmI2cCont->I2cRegisterOffset = 0;
+        hRmI2cCont->ControllerId = 3;
+        RxFifoPhyAddress = DVC_I2C_RX_FIFO_0;
+        TxFifoPhyAddress = DVC_I2C_TX_PACKET_FIFO_0;
+    }    
+
+    hRmI2cCont->IsApbDmaAllocated = NV_FALSE;
+    hRmI2cCont->hRmDma = NULL;
+
+    // Allocate the dma buffer 
+    hRmI2cCont->DmaBufferSize = 0;
+    Error = CreateDmaTransferBuffer(hRmI2cCont->hRmDevice, &hRmI2cCont->hRmMemory, 
+            &hRmI2cCont->DmaBuffPhysAdd, (void **)&hRmI2cCont->pDmaBuffer,
+            DEFAULT_I2C_DMA_BUFFER_SIZE);
+    if (Error)
+    {
+        hRmI2cCont->hRmMemory = NULL;
+        hRmI2cCont->DmaBuffPhysAdd = 0;
+        hRmI2cCont->pDmaBuffer = NULL;
+        Error = NvSuccess;
+    }
+    else
+    {
+        hRmI2cCont->DmaBufferSize = DEFAULT_I2C_DMA_BUFFER_SIZE;
+        
+        hRmI2cCont->RxDmaReq.SourceBufferPhyAddress= RxFifoPhyAddress;
+        hRmI2cCont->RxDmaReq.DestinationBufferPhyAddress = hRmI2cCont->DmaBuffPhysAdd;
+        hRmI2cCont->RxDmaReq.SourceAddressWrapSize = 4;
+        hRmI2cCont->RxDmaReq.DestinationAddressWrapSize = 0;
+        
+        hRmI2cCont->TxDmaReq.SourceBufferPhyAddress= hRmI2cCont->DmaBuffPhysAdd;
+        hRmI2cCont->TxDmaReq.DestinationBufferPhyAddress = TxFifoPhyAddress;
+        hRmI2cCont->TxDmaReq.SourceAddressWrapSize = 0;
+        hRmI2cCont->TxDmaReq.DestinationAddressWrapSize = 4;
+    }
+
+    if (!Error)
+    {
+        hRmI2cCont->pCpuBuffer = NvOsAlloc(DEFAULT_I2C_CPU_BUFFER_SIZE);
+        if (!hRmI2cCont->pCpuBuffer)
+            Error = NvError_InsufficientMemory;
+    }            
+    
+    if (!Error)
+        hRmI2cCont->pDataBuffer = hRmI2cCont->pCpuBuffer;
+    
+    // Create the sync semaphore for the interrupt synchrnoisation
+    if (!Error)
+        Error = NvOsSemaphoreCreate( &hRmI2cCont->I2cSyncSemaphore, 0);
+
+#if !USE_POLLING_METHOD
+    if (!Error)
+    {
+        IrqList = NvRmGetIrqForLogicalInterrupt(
+                hRmI2cCont->hRmDevice, NVRM_MODULE_ID(hRmI2cCont->ModuleId, hRmI2cCont->Instance), 0);
+
+        Error = NvRmInterruptRegister(hRmI2cCont->hRmDevice, 1, &IrqList, &IntHandlers, 
+                hRmI2cCont, &hRmI2cCont->I2CInterruptHandle, NV_TRUE);
+    }
+#endif
+    // Packet mode initialization
+    hRmI2cCont->RsTransfer =  NV_FALSE;
+
+    // If error then destroy all the allocation done here.
+    if (Error)
+        AP20RmI2cClose(hRmI2cCont);
+    
+    return Error;
+}
diff --git a/arch/arm/mach-tegra/nvrm/io/ap20/ap20rm_owr.c b/arch/arm/mach-tegra/nvrm/io/ap20/ap20rm_owr.c
new file mode 100644
index 000000000000..17f0251003bf
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/io/ap20/ap20rm_owr.c
@@ -0,0 +1,987 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/** @file
+ * @brief <b>NVIDIA Driver Development Kit: OWR API</b>
+ *
+ * @b Description: Contains the NvRM OWR implementation. for Ap20 
+ */
+
+#include "nvrm_owr.h"
+#include "nvrm_drf.h"
+#include "nvos.h"
+#include "nvrm_module.h"
+#include "ap20/arowr.h"
+#include "nvrm_hardware_access.h"
+#include "nvrm_power.h"
+#include "nvrm_interrupt.h"
+#include "nvassert.h"
+#include "nvodm_query_pinmux.h"
+#include "nvrm_pinmux.h"
+#include "nvrm_chiplib.h"
+#include "nvrm_hwintf.h"
+#include "nvrm_owr_private.h"
+#include "nvodm_query.h"
+#include "nvrm_module.h"
+
+// Enable the following flag for debug messages
+#define ENABLE_OWR_DEBUG   0
+
+#if ENABLE_OWR_DEBUG
+#define OWR_PRINT(X)   NvOsDebugPrintf X
+#else
+#define OWR_PRINT(X)
+#endif
+
+// Enabling the following flag for enabling the polling in bit transfer mode
+#define OWR_BIT_TRANSFER_POLLING_MODE   0
+
+/* Timeout for transferring a bit in micro seconds */
+#define BIT_TRASNFER_DONE_TIMEOUT_USEC  1000
+
+/* Polling timeout steps for transferring a bit in micro seconds */
+#define BIT_TRASNFER_DONE_STEP_TIMEOUT_USEC  10
+
+/* Semaphore timeout for bit/byte transfers */
+#define OWR_TRANSFER_TIMEOUT_MILLI_SEC  5000
+
+/* OWR controller errors in byte transfer mode */
+#define OWR_BYTE_TRANSFER_ERRORS  0x70F
+
+/* OWR controller errors in bit transfer mode */
+#define OWR_BIT_TRANSFER_ERRORS 0x1
+
+/* OWR CRC size in bytes */
+#define OWR_CRC_SIZE_BYTES  1
+
+/* OWR ROM command size */
+#define OWR_ROM_CMD_SIZE_BYTES  1
+
+/* OWR MEM command size */
+#define OWR_MEM_CMD_SIZE_BYTES  1
+
+/* OWR fifo depth */
+#define OWR_FIFO_DEPTH          32
+/* OWR fifo word size */
+#define OWR_FIFO_WORD_SIZE  4
+
+
+/* default read data clock value */
+#define OWR_DEFAULT_READ_DTA_CLK_VALUE    0x7
+/* default read presence  clock value */
+#define OWR_DEFAULT_PRESENCE_CLK_VALUE    0x50
+/* Default OWR device memory offset size */
+#define OWR_DEFAULT_OFFSET_SIZE_BYTES   2
+/* Default OWR memory size */
+#define OWR_DEFAULT_MEMORY_SIZE     0x80
+
+/* Register access Macros */
+#define OWR_REGR(OwrVirtualAddress, reg) \
+        NV_READ32((OwrVirtualAddress) + ((OWR_##reg##_0)/4))
+
+#define OWR_REGW(OwrVirtualAddress, reg, val) \
+    do\
+    {\
+        NV_WRITE32((((OwrVirtualAddress) + ((OWR_##reg##_0)/4))), (val));\
+    }while (0)
+
+void PrivOwrEnableInterrupts(NvRmOwrController *pOwrInfo, NvU32 OwrIntStatus);
+NvError PrivOwrSendCommand(NvRmOwrController *pOwrInfo, NvU32 Command);
+NvError PrivOwrSendBit(NvRmOwrController *pOwrInfo, NvU32 Bit);
+
+NvError
+PrivOwrCheckBitTransferDone(
+    NvRmOwrController* pOwrInfo,
+    OwrIntrStatus status);
+
+NvError
+PrivOwrReadData(
+    NvRmOwrController *pOwrInfo,
+    NvU8* Buffer,
+    NvU32 NoOfBytes);
+
+NvError
+PrivOwrReadDataBit(
+    NvRmOwrController *pOwrInfo,
+    NvU8* Buffer);
+
+static NvError
+PrivOwrCheckPresence(
+        NvRmOwrController* pOwrInfo,
+        NvU32 ReadDataClk,
+        NvU32 PresenceClk);
+
+static NvError
+PrivOwrReadFifo(
+    NvRmOwrController* pOwrInfo,
+    NvU8*  pBuffer,
+    NvRmOwrTransactionInfo Transaction,
+    const NvOdmQueryOwrDeviceInfo* pOdmInfo,
+    NvU32 NumBytes);
+
+
+void PrivOwrEnableInterrupts(NvRmOwrController *pOwrInfo, NvU32 OwrIntStatus)
+{
+    // Write to the interrupt status register
+    OWR_REGW(pOwrInfo->pOwrVirtualAddress, INTR_MASK, OwrIntStatus);
+}
+
+NvError
+PrivOwrCheckBitTransferDone(
+    NvRmOwrController* pOwrInfo,
+    OwrIntrStatus status)
+{
+
+#if OWR_BIT_TRANSFER_POLLING_MODE
+
+    NvU32 timeout = 0;
+    NvU32 val = 0;
+
+    // Check for presence
+    while(timeout < BIT_TRASNFER_DONE_TIMEOUT_USEC)
+    {
+        val = OWR_REGR(pOwrInfo->pOwrVirtualAddress, INTR_STATUS);
+        if (val & status)
+        {
+             // clear the bit transfer done status
+            OWR_REGW(pOwrInfo->pOwrVirtualAddress, INTR_STATUS, val);
+            break;
+        }
+        NvOsWaitUS(BIT_TRASNFER_DONE_STEP_TIMEOUT_USEC);
+        timeout += BIT_TRASNFER_DONE_STEP_TIMEOUT_USEC;
+    }
+
+    if (timeout >= BIT_TRASNFER_DONE_TIMEOUT_USEC)
+    {
+        return NvError_Timeout;
+    }
+
+   return NvSuccess;
+#else
+        // wait for the read to complete
+        status = NvOsSemaphoreWaitTimeout(pOwrInfo->OwrSyncSemaphore,
+                    OWR_TRANSFER_TIMEOUT_MILLI_SEC);
+        if (status == NvSuccess)
+        {
+            if (pOwrInfo->OwrTransferStatus & OWR_BIT_TRANSFER_ERRORS)
+            {
+                status = NvError_OwrBitTransferFailed;
+                NvRmModuleReset(pOwrInfo->hRmDevice,
+                    NVRM_MODULE_ID(NvRmModuleID_OneWire, pOwrInfo->Instance));
+                OWR_PRINT(("RM_OWR Bit mode error[0x%x]\n",
+                                            pOwrInfo->OwrTransferStatus));
+            }
+            else if(!pOwrInfo->OwrTransferStatus)
+            {
+                status = NvError_OwrBitTransferFailed;
+                NvRmModuleReset(pOwrInfo->hRmDevice,
+                    NVRM_MODULE_ID(NvRmModuleID_OneWire, pOwrInfo->Instance));
+                OWR_PRINT(("RM_OWR bit mode spurious interrupt [0x%x]\n",
+                                    pOwrInfo->OwrTransferStatus));
+                NV_ASSERT(!"RM_OWR spurious interrupt in Bit transfer mode\n");
+            }
+        }
+         pOwrInfo->OwrTransferStatus = 0;
+        return status;
+#endif
+}
+
+NvError PrivOwrSendCommand(NvRmOwrController *pOwrInfo, NvU32 Command)
+{
+    NvU32 val = 0;
+    NvU32 data = Command;
+    NvError status = NvError_Timeout;
+    NvU32 i =0;
+    NvU32 ControlReg = 0;
+
+    val =
+        (NV_DRF_NUM(OWR, CONTROL, RD_DATA_SAMPLE_CLK, 0x7) |
+        NV_DRF_NUM(OWR, CONTROL, PRESENCE_SAMPLE_CLK, 0x50) |
+        NV_DRF_DEF(OWR, CONTROL, DATA_TRANSFER_MODE, BIT_TRANSFER_MODE));
+
+    for (i = 0; i < OWR_NO_OF_BITS_PER_BYTE; i++)
+    {
+
+        if (data & 0x1)
+        {
+            ControlReg =
+                val | (NV_DRF_DEF(OWR, CONTROL, WR1_BIT, TRANSFER_ONE));
+        }
+        else
+        {
+           ControlReg =
+            val | (NV_DRF_DEF(OWR, CONTROL, WR0_BIT, TRANSFER_ZERO));
+        }
+        OWR_REGW(pOwrInfo->pOwrVirtualAddress, CONTROL, ControlReg);
+
+        status = PrivOwrCheckBitTransferDone(pOwrInfo,
+                                    OwrIntrStatus_BitTransferDoneIntEnable);
+        if (status != NvSuccess)
+        {
+            return status;
+        }
+
+        data = (data >> 1);
+    }
+
+    return NvSuccess;
+}
+
+NvError PrivOwrSendBit(NvRmOwrController *pOwrInfo, NvU32 Bit)
+{
+    NvU32 val = 0;
+    NvU32 data = Bit;
+    NvError status = NvError_Timeout;
+    NvU32 ControlReg = 0;
+
+    val =
+        (NV_DRF_NUM(OWR, CONTROL, RD_DATA_SAMPLE_CLK, 0x7) |
+        NV_DRF_NUM(OWR, CONTROL, PRESENCE_SAMPLE_CLK, 0x50) |
+        NV_DRF_DEF(OWR, CONTROL, DATA_TRANSFER_MODE, BIT_TRANSFER_MODE));
+
+    if (data & 0x1)
+    {
+        ControlReg =
+            val | (NV_DRF_DEF(OWR, CONTROL, WR1_BIT, TRANSFER_ONE));
+    }
+    else
+    {
+        ControlReg =
+            val | (NV_DRF_DEF(OWR, CONTROL, WR0_BIT, TRANSFER_ZERO));
+    }
+    OWR_REGW(pOwrInfo->pOwrVirtualAddress, CONTROL, ControlReg);
+
+    status = PrivOwrCheckBitTransferDone(pOwrInfo,
+                                    OwrIntrStatus_BitTransferDoneIntEnable);
+    if (status != NvSuccess)
+    {
+        return status;
+    }
+
+    return NvSuccess;
+}
+
+NvError
+PrivOwrReadData(
+    NvRmOwrController *pOwrInfo,
+    NvU8* Buffer,
+    NvU32 NoOfBytes)
+{
+    NvU32 ControlReg = 0;
+    NvError status = NvError_Timeout;
+    NvU8* pBuf = Buffer;
+    NvU32 val = 0;
+    NvU32 i =0;
+    NvU32 j =0;
+
+    NvOsMemset(pBuf, 0, NoOfBytes);
+
+    ControlReg =
+        NV_DRF_NUM(OWR, CONTROL, RD_DATA_SAMPLE_CLK, 0x7) |
+        NV_DRF_NUM(OWR, CONTROL, PRESENCE_SAMPLE_CLK, 0x50) |
+        NV_DRF_DEF(OWR, CONTROL, DATA_TRANSFER_MODE, BIT_TRANSFER_MODE) |
+        NV_DRF_DEF(OWR, CONTROL, RD_BIT, TRANSFER_READ_SLOT);
+
+    for (i = 0; i < NoOfBytes; i++)
+    {
+        for (j = 0; j < OWR_NO_OF_BITS_PER_BYTE; j++)
+        {
+            OWR_REGW(pOwrInfo->pOwrVirtualAddress, CONTROL, ControlReg);
+            status = PrivOwrCheckBitTransferDone(pOwrInfo,
+                                        OwrIntrStatus_BitTransferDoneIntEnable);
+            if (status != NvSuccess)
+            {
+                return status;
+            }
+            val = OWR_REGR(pOwrInfo->pOwrVirtualAddress, STATUS);
+            val = NV_DRF_VAL(OWR, STATUS, READ_SAMPLED_BIT, val);
+            *pBuf |= (val << j);
+        }
+        pBuf++;
+    }
+    return NvSuccess;
+}
+
+NvError
+PrivOwrReadDataBit(
+    NvRmOwrController *pOwrInfo,
+    NvU8* Buffer)
+{
+    NvU32 ControlReg = 0;
+    NvError status = NvError_Timeout;
+    NvU32 val = 0;
+
+    ControlReg =
+        NV_DRF_NUM(OWR, CONTROL, RD_DATA_SAMPLE_CLK, 0x7) |
+        NV_DRF_NUM(OWR, CONTROL, PRESENCE_SAMPLE_CLK, 0x50) |
+        NV_DRF_DEF(OWR, CONTROL, DATA_TRANSFER_MODE, BIT_TRANSFER_MODE) |
+        NV_DRF_DEF(OWR, CONTROL, RD_BIT, TRANSFER_READ_SLOT);
+
+    OWR_REGW(pOwrInfo->pOwrVirtualAddress, CONTROL, ControlReg);
+    status = PrivOwrCheckBitTransferDone(pOwrInfo,
+        OwrIntrStatus_BitTransferDoneIntEnable);
+    if (status != NvSuccess)
+    {
+        return status;
+    }
+    val = OWR_REGR(pOwrInfo->pOwrVirtualAddress, STATUS);
+    val = NV_DRF_VAL(OWR, STATUS, READ_SAMPLED_BIT, val);
+    *Buffer = val;
+    return NvSuccess;
+}
+
+static NvError
+PrivOwrReadFifo(
+    NvRmOwrController* pOwrInfo,
+    NvU8*  pBuffer,
+    NvRmOwrTransactionInfo Transaction,
+    const NvOdmQueryOwrDeviceInfo* pOdmInfo,
+    NvU32 NumBytes)
+{
+    NvU32 val = 0;
+    NvError status = NvError_OwrReadFailed;
+    NvU32 BytesToRead = 0;
+    NvU32 WordsToRead = 0;
+    NvU32 ReadDataClk = OWR_DEFAULT_READ_DTA_CLK_VALUE;
+    NvU32 PresenceClk = OWR_DEFAULT_PRESENCE_CLK_VALUE;
+    NvU32 i = 0;
+    NvU32 size = OWR_DEFAULT_MEMORY_SIZE;
+    NvU32 value = 0;
+
+    if (pOdmInfo)
+    {
+        ReadDataClk = pOdmInfo->ReadDataSampleClk;
+        PresenceClk = pOdmInfo->PresenceSampleClk;
+        size = pOdmInfo->MemorySize;
+    }
+
+    if ( Transaction.Offset >= size)
+    {
+        status = NvError_OwrInvalidOffset;
+        return status;
+    }
+    // Configure the number of bytes to read
+    value = size - Transaction.Offset - 1;
+    OWR_REGW(pOwrInfo->pOwrVirtualAddress,
+                    EPROM,
+                    value);
+
+    // Configure the read, presence sample clock and
+    // configure for byte transfer mode
+    val = 
+        NV_DRF_NUM(OWR, CONTROL, RD_DATA_SAMPLE_CLK, ReadDataClk) |
+        NV_DRF_NUM(OWR, CONTROL, PRESENCE_SAMPLE_CLK, PresenceClk) |
+        NV_DRF_DEF(OWR, CONTROL, DATA_TRANSFER_MODE, BYTE_TRANSFER_MODE) |
+        NV_DRF_DEF(OWR, CONTROL, RD_MEM_CRC_REQ, CRC_READ) |
+        NV_DRF_DEF(OWR, CONTROL, GO, START_PRESENCE_PULSE);
+    OWR_REGW(pOwrInfo->pOwrVirtualAddress, CONTROL, val);
+
+    // wait for the read to complete
+    status = NvOsSemaphoreWaitTimeout(pOwrInfo->OwrSyncSemaphore,
+                                            OWR_TRANSFER_TIMEOUT_MILLI_SEC);
+    if (status == NvSuccess)
+    {
+        if (pOwrInfo->OwrTransferStatus & OWR_BYTE_TRANSFER_ERRORS)
+        {
+            NvRmModuleReset(pOwrInfo->hRmDevice,
+                NVRM_MODULE_ID(NvRmModuleID_OneWire, pOwrInfo->Instance));
+            OWR_PRINT(("RM_OWR Byte mode error interrupt[0x%x]\n",
+                                        pOwrInfo->OwrTransferStatus));
+            return NvError_OwrReadFailed;
+        }
+        else if (pOwrInfo->OwrTransferStatus & OwrIntrStatus_MemCmdDoneIntEnable)
+        {
+            // Read the data
+            if (Transaction.Flags == NvRmOwr_ReadAddress)
+            {
+                // Read and copy and the ROM ID
+                val = OWR_REGR(pOwrInfo->pOwrVirtualAddress, READ_ROM0);
+                NvOsMemcpy(pBuffer, &val, 4);
+                pBuffer += 4;
+
+                val = OWR_REGR(pOwrInfo->pOwrVirtualAddress, READ_ROM1);
+                NvOsMemcpy(pBuffer, &val, 4);
+            }
+            else if (Transaction.Flags == NvRmOwr_MemRead)
+            {
+                val = OWR_REGR(pOwrInfo->pOwrVirtualAddress, BYTE_CNT);
+                val = NV_DRF_VAL(OWR, BYTE_CNT, RECEIVED, val);
+                /** Decrement the number of bytes to read count as it includes
+                 * one byte CRC.
+                 */
+                val--;
+
+                BytesToRead = (val > NumBytes) ? NumBytes : val;
+                WordsToRead =  BytesToRead / OWR_FIFO_WORD_SIZE;
+                for (i = 0; i < WordsToRead; i++)
+                {
+                    val = OWR_REGR(pOwrInfo->pOwrVirtualAddress, RX_FIFO);
+                    NvOsMemcpy(pBuffer, &val, OWR_FIFO_WORD_SIZE);
+                    pBuffer += OWR_FIFO_WORD_SIZE;
+                }
+
+                BytesToRead = (BytesToRead % OWR_FIFO_WORD_SIZE);
+                if (BytesToRead)
+                {
+                      val = OWR_REGR(pOwrInfo->pOwrVirtualAddress, RX_FIFO);
+                       NvOsMemcpy(pBuffer, &val, BytesToRead);
+                }
+            }
+        }
+        else
+        {
+            OWR_PRINT(("RM_OWR Byte mode spurious interrupt[0x%x]\n",
+                            pOwrInfo->OwrTransferStatus));
+            NV_ASSERT(!"RM_OWR spurious interrupt\n");
+            NvRmModuleReset(pOwrInfo->hRmDevice,
+                NVRM_MODULE_ID(NvRmModuleID_OneWire, pOwrInfo->Instance));
+            return NvError_OwrReadFailed;
+        }
+    }
+    return status;
+}
+
+static NvError
+PrivOwrWriteFifo(
+    NvRmOwrController* pOwrInfo,
+    NvU8*  pBuffer,
+    NvRmOwrTransactionInfo Transaction,
+    const NvOdmQueryOwrDeviceInfo* pOdmInfo,
+    NvU32 NumBytes)
+{
+    NvU32 val = 0;
+    NvError status = NvError_OwrWriteFailed;
+    NvU32 ReadDataClk = OWR_DEFAULT_READ_DTA_CLK_VALUE;
+    NvU32 PresenceClk = OWR_DEFAULT_PRESENCE_CLK_VALUE;
+    NvU32 i = 0;
+
+    if (pOdmInfo)
+    {
+        ReadDataClk = pOdmInfo->ReadDataSampleClk;
+        PresenceClk = pOdmInfo->PresenceSampleClk;
+    }
+    // Configure the number of bytes to write
+    OWR_REGW(pOwrInfo->pOwrVirtualAddress, EPROM, (NumBytes - 1));
+
+    // Write data into the FIFO
+    for (i = NumBytes; i > 0; )
+    {
+        NvU32 BytesToWrite = NV_MIN(sizeof(NvU32),i);
+        val = 0;
+        switch (BytesToWrite)
+        {
+        case 4: val |= pBuffer[3]; i--;           // fallthrough
+        case 3: val <<=8; val |= pBuffer[2]; i--; // fallthrough
+        case 2: val <<=8; val |= pBuffer[1]; i--; // fallthrough
+        case 1: val <<=8; val |= pBuffer[0]; i--;
+            OWR_REGW(pOwrInfo->pOwrVirtualAddress, TX_FIFO, val);
+            pBuffer += BytesToWrite;
+            break;
+        }
+    }
+
+    // Configure the read, presence sample clock and
+    // configure for byte transfer mode
+    val =
+        NV_DRF_NUM(OWR, CONTROL, RD_DATA_SAMPLE_CLK, ReadDataClk) |
+        NV_DRF_NUM(OWR, CONTROL, PRESENCE_SAMPLE_CLK, PresenceClk) |
+        NV_DRF_DEF(OWR, CONTROL, DATA_TRANSFER_MODE, BYTE_TRANSFER_MODE) |
+        NV_DRF_DEF(OWR, CONTROL, GO, START_PRESENCE_PULSE);
+    OWR_REGW(pOwrInfo->pOwrVirtualAddress, CONTROL, val);
+
+    // wait for the write to complete
+    status = NvOsSemaphoreWaitTimeout(pOwrInfo->OwrSyncSemaphore,
+                                            OWR_TRANSFER_TIMEOUT_MILLI_SEC);
+    if (status == NvSuccess)
+    {
+        if (pOwrInfo->OwrTransferStatus & OWR_BYTE_TRANSFER_ERRORS)
+        {
+            NvRmModuleReset(pOwrInfo->hRmDevice,
+                NVRM_MODULE_ID(NvRmModuleID_OneWire, pOwrInfo->Instance));
+            OWR_PRINT(("RM_OWR Byte mode error interrupt[0x%x]\n",
+                                        pOwrInfo->OwrTransferStatus));
+            return NvError_OwrWriteFailed;
+        }
+        else if (pOwrInfo->OwrTransferStatus & OwrIntrStatus_MemCmdDoneIntEnable)
+        {
+            val = OWR_REGR(pOwrInfo->pOwrVirtualAddress, BYTE_CNT);
+            val = NV_DRF_VAL(OWR, BYTE_CNT, RECEIVED, val);
+
+            /** byte count includes ROM, Mem command size and Memory
+             * address size. So, subtract ROM, Mem Command size and
+             * memory address size from byte count.
+             */
+            val -= OWR_MEM_CMD_SIZE_BYTES;
+            val -= OWR_MEM_CMD_SIZE_BYTES;
+            val -= OWR_DEFAULT_OFFSET_SIZE_BYTES;
+
+            /** Assert if the actual bytes written is
+             * not equal to the bytes written
+             */
+            NV_ASSERT(val == NumBytes);
+        }
+        else
+        {
+            OWR_PRINT(("RM_OWR Byte mode spurious interrupt[0x%x]\n",
+                            pOwrInfo->OwrTransferStatus));
+            NV_ASSERT(!"RM_OWR spurious interrupt\n");
+            NvRmModuleReset(pOwrInfo->hRmDevice,
+                NVRM_MODULE_ID(NvRmModuleID_OneWire, pOwrInfo->Instance));
+            return NvError_OwrWriteFailed;
+        }
+    }
+    return status;
+}
+
+NvError
+PrivOwrCheckPresence(
+        NvRmOwrController* pOwrInfo,
+        NvU32 ReadDataClk,
+        NvU32 PresenceClk)
+{
+        NvError status = NvSuccess;
+        NvU32 val = 0;
+
+        // Enable the bit transfer done interrupt
+        PrivOwrEnableInterrupts(pOwrInfo, OwrIntrStatus_PresenceDoneIntEnable);
+        pOwrInfo->OwrTransferStatus = 0;
+
+        // Configure for presence
+        val =
+            NV_DRF_NUM(OWR, CONTROL, RD_DATA_SAMPLE_CLK, ReadDataClk) |
+            NV_DRF_NUM(OWR, CONTROL, PRESENCE_SAMPLE_CLK, PresenceClk) |
+            NV_DRF_DEF(OWR, CONTROL, DATA_TRANSFER_MODE, BIT_TRANSFER_MODE) |
+            NV_DRF_DEF(OWR, CONTROL, GO, START_PRESENCE_PULSE);
+
+        OWR_REGW(pOwrInfo->pOwrVirtualAddress, CONTROL, val);
+
+        // Check for presence
+        status = PrivOwrCheckBitTransferDone(pOwrInfo,
+                                    OwrIntrStatus_PresenceDoneIntEnable);
+        return status;
+}
+
+/****************************************************************************/
+
+static void OwrIsr(void* args)
+{
+    NvRmOwrController* pOwrInfo = args;
+    NvU32 IntStatus;
+
+    // Read the interrupt status register
+    IntStatus = OWR_REGR(pOwrInfo->pOwrVirtualAddress, INTR_STATUS);
+
+    // Save the status
+    pOwrInfo->OwrTransferStatus = IntStatus;
+
+    // Clear the interrupt status register
+    OWR_REGW(pOwrInfo->pOwrVirtualAddress, INTR_STATUS, IntStatus);
+
+    // Signal the sema
+    NvOsSemaphoreSignal(pOwrInfo->OwrSyncSemaphore);
+    NvRmInterruptDone(pOwrInfo->OwrInterruptHandle);
+}
+
+static void AP20RmOwrClose(NvRmOwrController *pOwrInfo)
+{
+    if (pOwrInfo->OwrSyncSemaphore)
+    {
+#if !OWR_BIT_TRANSFER_POLLING_MODE
+        NvRmInterruptUnregister(pOwrInfo->hRmDevice,
+                        pOwrInfo->OwrInterruptHandle);
+#endif
+        NvOsSemaphoreDestroy(pOwrInfo->OwrSyncSemaphore);
+        pOwrInfo->OwrSyncSemaphore = NULL;
+        pOwrInfo->OwrInterruptHandle = NULL;
+    }
+    pOwrInfo->read = 0;
+    pOwrInfo->write = 0;
+    pOwrInfo->close = 0;
+    NvRmPhysicalMemUnmap(pOwrInfo->pOwrVirtualAddress, pOwrInfo->OwrBankSize);
+}
+
+static NvError
+AP20RmOwrRead(
+    NvRmOwrController* pOwrInfo,
+    NvU8*  pBuffer,
+    NvRmOwrTransactionInfo Transaction)
+{
+    NvU32 val = 0;
+    NvError status = NvError_BadParameter;
+    NvBool IsByteModeSupported = NV_FALSE;
+    const NvOdmQueryOwrDeviceInfo* pOwrOdmInfo = NULL;
+    NvU32 ReadDataClk = OWR_DEFAULT_READ_DTA_CLK_VALUE;
+    NvU32 PresenceClk = OWR_DEFAULT_PRESENCE_CLK_VALUE;
+    NvU32 DeviceOffsetSize = OWR_DEFAULT_OFFSET_SIZE_BYTES;
+    NvU32 TotalBytesToRead = 0;
+    NvU32 BytesRead = 0;
+    NvU32 FifoSize = 0;
+    NvU32 i = 0;
+    NvU8* pReadPtr = pBuffer;
+
+    if ((Transaction.Flags == NvRmOwr_MemRead) && (!Transaction.NumBytes))
+    {
+        return NvError_BadParameter;
+    }
+
+    pOwrOdmInfo = NvOdmQueryGetOwrDeviceInfo(pOwrInfo->Instance);
+    if (!pOwrOdmInfo)
+    {
+        IsByteModeSupported = NV_FALSE;
+
+         // program the default timing registers
+        OWR_REGW(pOwrInfo->pOwrVirtualAddress, WR_RD_TCTL, 0x13fde0f7);
+        OWR_REGW(pOwrInfo->pOwrVirtualAddress, RST_PRESENCE_TCTL, 0x787bbfdf);
+        OWR_REGW(pOwrInfo->pOwrVirtualAddress, PROG_PULSE_TCTL, 0x01e05555);
+    }
+    else
+    {
+        IsByteModeSupported = pOwrOdmInfo->IsByteModeSupported;
+        ReadDataClk = pOwrOdmInfo->ReadDataSampleClk;
+        PresenceClk = pOwrOdmInfo->PresenceSampleClk;
+        DeviceOffsetSize = pOwrOdmInfo->AddressSize;
+
+         // program the timing registers
+        val =
+            NV_DRF_NUM(OWR, WR_RD_TCTL, TSLOT, pOwrOdmInfo->TSlot) |
+            NV_DRF_NUM(OWR, WR_RD_TCTL, TLOW1, pOwrOdmInfo->TLow1) |
+            NV_DRF_NUM(OWR, WR_RD_TCTL, TLOW0, pOwrOdmInfo->TLow0) |
+            NV_DRF_NUM(OWR, WR_RD_TCTL, TRDV, pOwrOdmInfo->TRdv) |
+            NV_DRF_NUM(OWR, WR_RD_TCTL, TRELEASE, pOwrOdmInfo->TRelease) |
+            NV_DRF_NUM(OWR, WR_RD_TCTL, TSU, pOwrOdmInfo->Tsu);
+        OWR_REGW(pOwrInfo->pOwrVirtualAddress, WR_RD_TCTL, val);
+
+        val =
+            NV_DRF_NUM(OWR, RST_PRESENCE_TCTL, TRSTH, pOwrOdmInfo->TRsth) |
+            NV_DRF_NUM(OWR, RST_PRESENCE_TCTL, TRSTL, pOwrOdmInfo->TRstl) |
+            NV_DRF_NUM(OWR, RST_PRESENCE_TCTL, TPDH, pOwrOdmInfo->Tpdh) |
+            NV_DRF_NUM(OWR, RST_PRESENCE_TCTL, TPDL, pOwrOdmInfo->Tpdl);
+        OWR_REGW(pOwrInfo->pOwrVirtualAddress, RST_PRESENCE_TCTL, val);
+
+        val =
+            NV_DRF_NUM(OWR, PROG_PULSE_TCTL, TPD, pOwrOdmInfo->Tpd) |
+            NV_DRF_NUM(OWR, PROG_PULSE_TCTL, TDV, pOwrOdmInfo->Tdv) |
+            NV_DRF_NUM(OWR, PROG_PULSE_TCTL, TRP, pOwrOdmInfo->Trp) |
+            NV_DRF_NUM(OWR, PROG_PULSE_TCTL, TFP, pOwrOdmInfo->Tfp) |
+            NV_DRF_NUM(OWR, PROG_PULSE_TCTL, TPP, pOwrOdmInfo->Tpp);
+        OWR_REGW(pOwrInfo->pOwrVirtualAddress, PROG_PULSE_TCTL, val);
+    }
+
+    if (Transaction.Flags == NvRmOwr_CheckPresence)
+    {
+        NV_ASSERT(!IsByteModeSupported);
+        status = PrivOwrCheckPresence(pOwrInfo, ReadDataClk, PresenceClk);
+    }
+    else if (Transaction.Flags == NvRmOwr_ReadByte)
+    {
+        NV_ASSERT(!IsByteModeSupported);
+
+        pOwrInfo->OwrTransferStatus = 0;
+        // Enable the bit transfer done interrupt
+        PrivOwrEnableInterrupts(pOwrInfo,
+                                    OwrIntrStatus_BitTransferDoneIntEnable);
+        status =
+            PrivOwrReadData(pOwrInfo, pReadPtr, 1);
+    }
+    else if (Transaction.Flags == NvRmOwr_ReadBit)
+    {
+        NV_ASSERT(!IsByteModeSupported);
+        pOwrInfo->OwrTransferStatus = 0;
+        // Enable the bit transfer done interrupt
+        PrivOwrEnableInterrupts(pOwrInfo,
+                                    OwrIntrStatus_BitTransferDoneIntEnable);
+        status = PrivOwrReadDataBit(pOwrInfo, pReadPtr);
+    }
+    else if ((Transaction.Flags == NvRmOwr_MemRead) ||
+                 (Transaction.Flags == NvRmOwr_ReadAddress))
+    {
+        if (!IsByteModeSupported)
+        {
+            // Bit transfer mode
+            status = PrivOwrCheckPresence(pOwrInfo, ReadDataClk, PresenceClk);
+            if (status != NvSuccess)
+                return status;
+
+            if (Transaction.Flags == NvRmOwr_ReadAddress)
+            {
+
+                // Send the ROM Read Command
+                NV_ASSERT_SUCCESS(PrivOwrSendCommand(pOwrInfo,
+                            OWR_ROM_READ_COMMAND));
+
+                // Read byte
+                status = PrivOwrReadData(pOwrInfo, pReadPtr, OWR_ROM_ID_SIZE_BYTES);
+            }
+            else
+            {
+                // Skip the ROM Read Command
+                NV_ASSERT_SUCCESS(
+                PrivOwrSendCommand(pOwrInfo, OWR_ROM_SKIP_COMMAND));
+
+                // Send the Mem Read Command
+                NV_ASSERT_SUCCESS(
+                PrivOwrSendCommand(pOwrInfo, OWR_MEM_READ_COMMAND));
+
+                // Send offset in memory
+                for (i = 0; i < DeviceOffsetSize; i++)
+                {
+                val = (Transaction.Offset >> i) & 0xFF;
+                NV_ASSERT_SUCCESS(PrivOwrSendCommand(pOwrInfo, val));
+                }
+
+                // Read the CRC
+                NV_ASSERT_SUCCESS(
+                PrivOwrReadData(pOwrInfo, pReadPtr, OWR_CRC_SIZE_BYTES));
+
+                // TODO: Need to compute the CRC and compare with the CRC read
+
+                // Read Mem data
+                status = PrivOwrReadData(pOwrInfo, pReadPtr, Transaction.NumBytes);
+            }
+        }
+        else
+        {
+            // Byte transfer Mode
+            // Enable the interrupts
+            PrivOwrEnableInterrupts(pOwrInfo,
+                        (OwrIntrStatus_PresenceErrIntEnable |
+                         OwrIntrStatus_CrcErrIntEnable |
+                         OwrIntrStatus_MemWriteErrIntEnable |
+                         OwrIntrStatus_ErrCommandIntEnable |
+                         OwrIntrStatus_MemCmdDoneIntEnable|
+                         OwrIntrStatus_TxfOvfIntEnable |
+                         OwrIntrStatus_RxfUnrIntEnable));
+
+            // Configure the Rom command and the eeprom starting address
+            val = (
+                NV_DRF_NUM(OWR, COMMAND, ROM_CMD, OWR_ROM_READ_COMMAND) |
+                NV_DRF_NUM(OWR, COMMAND, MEM_CMD, OWR_MEM_READ_COMMAND) |
+                NV_DRF_NUM(OWR, COMMAND, MEM_ADDR, Transaction.Offset));
+            OWR_REGW(pOwrInfo->pOwrVirtualAddress, COMMAND, val);
+
+            /** We can't porgam ROM ID read alone, memory read should also be given
+            * along with ROM ID read. So, preogramming memory read of 1byte even
+            * for ROM ID read.
+            */
+            TotalBytesToRead = (Transaction.NumBytes) ? Transaction.NumBytes : 1;
+            FifoSize = (OWR_FIFO_DEPTH * OWR_FIFO_WORD_SIZE);
+            while(TotalBytesToRead)
+            {
+                BytesRead =
+                    (TotalBytesToRead > FifoSize) ? FifoSize : TotalBytesToRead;
+                pOwrInfo->OwrTransferStatus = 0;
+                status =
+                    PrivOwrReadFifo(pOwrInfo, pReadPtr, Transaction,
+                                        pOwrOdmInfo, BytesRead);
+                if (status != NvSuccess)
+                {
+                    break;
+                }
+                TotalBytesToRead -= BytesRead;
+                pReadPtr += BytesRead;
+            }
+        }
+    }
+    return status;
+}
+
+static NvError
+AP20RmOwrWrite(
+    NvRmOwrController *pOwrInfo,
+    NvU8*  pBuffer,
+    NvRmOwrTransactionInfo Transaction)
+{
+    NvU32 val = 0;
+    NvError status = NvError_BadParameter;
+    NvBool IsByteModeSupported = NV_FALSE;
+    const NvOdmQueryOwrDeviceInfo* pOwrOdmInfo = NULL;
+    NvU32 TotalBytesToWrite = 0;
+    NvU32 BytesWritten = 0;
+    NvU32 FifoSize = 0;
+    NvU8* pWritePtr = pBuffer;
+
+    if ((Transaction.Flags == NvRmOwr_MemWrite) && (!Transaction.NumBytes))
+    {
+        return NvError_BadParameter;
+    }
+
+    pOwrOdmInfo = NvOdmQueryGetOwrDeviceInfo(pOwrInfo->Instance);
+    if (!pOwrOdmInfo)
+    {
+        IsByteModeSupported = NV_FALSE;
+
+         // program the default timing registers
+        OWR_REGW(pOwrInfo->pOwrVirtualAddress, WR_RD_TCTL, 0x13fde0f7);
+        OWR_REGW(pOwrInfo->pOwrVirtualAddress, RST_PRESENCE_TCTL, 0x787bbfdf);
+        OWR_REGW(pOwrInfo->pOwrVirtualAddress, PROG_PULSE_TCTL, 0x01e05555);
+    }
+    else
+    {
+        IsByteModeSupported = pOwrOdmInfo->IsByteModeSupported;
+
+         // program the timing registers
+        val =
+            NV_DRF_NUM(OWR, WR_RD_TCTL, TSLOT, pOwrOdmInfo->TSlot) |
+            NV_DRF_NUM(OWR, WR_RD_TCTL, TLOW1, pOwrOdmInfo->TLow1) |
+            NV_DRF_NUM(OWR, WR_RD_TCTL, TLOW0, pOwrOdmInfo->TLow0) |
+            NV_DRF_NUM(OWR, WR_RD_TCTL, TRDV, pOwrOdmInfo->TRdv) |
+            NV_DRF_NUM(OWR, WR_RD_TCTL, TRELEASE, pOwrOdmInfo->TRelease) |
+            NV_DRF_NUM(OWR, WR_RD_TCTL, TSU, pOwrOdmInfo->Tsu);
+        OWR_REGW(pOwrInfo->pOwrVirtualAddress, WR_RD_TCTL, val);
+
+        val =
+            NV_DRF_NUM(OWR, RST_PRESENCE_TCTL, TRSTH, pOwrOdmInfo->TRsth) |
+            NV_DRF_NUM(OWR, RST_PRESENCE_TCTL, TRSTL, pOwrOdmInfo->TRstl) |
+            NV_DRF_NUM(OWR, RST_PRESENCE_TCTL, TPDH, pOwrOdmInfo->Tpdh) |
+            NV_DRF_NUM(OWR, RST_PRESENCE_TCTL, TPDL, pOwrOdmInfo->Tpdl);
+        OWR_REGW(pOwrInfo->pOwrVirtualAddress, RST_PRESENCE_TCTL, val);
+
+        val =
+            NV_DRF_NUM(OWR, PROG_PULSE_TCTL, TPD, pOwrOdmInfo->Tpd) |
+            NV_DRF_NUM(OWR, PROG_PULSE_TCTL, TDV, pOwrOdmInfo->Tdv) |
+            NV_DRF_NUM(OWR, PROG_PULSE_TCTL, TRP, pOwrOdmInfo->Trp) |
+            NV_DRF_NUM(OWR, PROG_PULSE_TCTL, TFP, pOwrOdmInfo->Tfp) |
+            NV_DRF_NUM(OWR, PROG_PULSE_TCTL, TPP, pOwrOdmInfo->Tpp);
+        OWR_REGW(pOwrInfo->pOwrVirtualAddress, PROG_PULSE_TCTL, val);
+    }
+
+    if (Transaction.Flags == NvRmOwr_MemWrite)
+    {
+        // Only Byte transfer Mode is supported for writes
+        NV_ASSERT(IsByteModeSupported == NV_TRUE);
+
+        // Enable the interrupts
+        PrivOwrEnableInterrupts(pOwrInfo,
+                        (OwrIntrStatus_PresenceErrIntEnable |
+                         OwrIntrStatus_CrcErrIntEnable |
+                         OwrIntrStatus_MemWriteErrIntEnable |
+                         OwrIntrStatus_ErrCommandIntEnable |
+                         OwrIntrStatus_MemCmdDoneIntEnable|
+                         OwrIntrStatus_TxfOvfIntEnable |
+                         OwrIntrStatus_RxfUnrIntEnable));
+
+        // Configure the Rom command and the eeprom starting address
+        val = (
+                NV_DRF_NUM(OWR, COMMAND, ROM_CMD, OWR_ROM_READ_COMMAND) |
+                NV_DRF_NUM(OWR, COMMAND, MEM_CMD, OWR_MEM_WRITE_COMMAND) |
+                NV_DRF_NUM(OWR, COMMAND, MEM_ADDR, Transaction.Offset));
+        OWR_REGW(pOwrInfo->pOwrVirtualAddress, COMMAND, val);
+
+        TotalBytesToWrite = Transaction.NumBytes;
+        FifoSize = (OWR_FIFO_DEPTH * OWR_FIFO_WORD_SIZE);
+        while(TotalBytesToWrite)
+        {
+            BytesWritten =
+                (TotalBytesToWrite > FifoSize) ? FifoSize : TotalBytesToWrite;
+            pOwrInfo->OwrTransferStatus = 0;
+            status =
+                PrivOwrWriteFifo(pOwrInfo, pWritePtr, Transaction,
+                                    pOwrOdmInfo, BytesWritten);
+            if (status != NvSuccess)
+            {
+                break;
+            }
+            TotalBytesToWrite -= BytesWritten;
+            pWritePtr += BytesWritten;
+        }
+    }
+    else if(Transaction.Flags == NvRmOwr_WriteByte)
+    {
+        // Enable the bit transfer done interrupt
+        PrivOwrEnableInterrupts(pOwrInfo, OwrIntrStatus_BitTransferDoneIntEnable);
+        pOwrInfo->OwrTransferStatus = 0;
+        status = PrivOwrSendCommand(pOwrInfo, (NvU32)(*pWritePtr));
+    }
+    else if(Transaction.Flags == NvRmOwr_WriteBit)
+    {
+        // Enable the bit transfer done interrupt
+        PrivOwrEnableInterrupts(pOwrInfo, OwrIntrStatus_BitTransferDoneIntEnable);
+        pOwrInfo->OwrTransferStatus = 0;
+        status = PrivOwrSendBit(pOwrInfo, (NvU32)(*pWritePtr));
+    }
+
+    return status;
+}
+
+NvError AP20RmOwrOpen(NvRmOwrController *pOwrInfo)
+{
+    NvError status = NvSuccess;
+
+    NV_ASSERT(pOwrInfo != NULL);
+
+    /* Polulate the structures */
+    pOwrInfo->read = AP20RmOwrRead;
+    pOwrInfo->write = AP20RmOwrWrite;
+    pOwrInfo->close = AP20RmOwrClose;
+
+    NvRmModuleGetBaseAddress(
+        pOwrInfo->hRmDevice,
+        NVRM_MODULE_ID(NvRmModuleID_OneWire, pOwrInfo->Instance),
+        &pOwrInfo->OwrPhysicalAddress,
+        &pOwrInfo->OwrBankSize);
+
+    NV_ASSERT_SUCCESS(NvRmPhysicalMemMap(
+        pOwrInfo->OwrPhysicalAddress,
+        pOwrInfo->OwrBankSize, NVOS_MEM_READ_WRITE,
+        NvOsMemAttribute_Uncached,
+        (void **)&pOwrInfo->pOwrVirtualAddress));
+
+        // Create the sync semaphore
+    status = NvOsSemaphoreCreate( &pOwrInfo->OwrSyncSemaphore, 0);
+
+    if (pOwrInfo->OwrSyncSemaphore)
+    {
+        NvU32 IrqList;
+        NvOsInterruptHandler IntHandlers;
+
+        IntHandlers = OwrIsr;
+        IrqList = NvRmGetIrqForLogicalInterrupt(
+                pOwrInfo->hRmDevice,
+                NVRM_MODULE_ID(pOwrInfo->ModuleId, pOwrInfo->Instance), 0);
+
+#if !OWR_BIT_TRANSFER_POLLING_MODE
+        status = NvRmInterruptRegister(pOwrInfo->hRmDevice, 1, &IrqList,
+                    &IntHandlers, pOwrInfo,
+                    &pOwrInfo->OwrInterruptHandle, NV_TRUE);
+#endif
+
+        if (status != NvSuccess)
+        {
+            NV_ASSERT(!"OWR module interrupt register failed!");
+            NvOsSemaphoreDestroy(pOwrInfo->OwrSyncSemaphore);
+            pOwrInfo->OwrSyncSemaphore = 0;
+        }
+    }
+
+    return status;
+}
+
diff --git a/arch/arm/mach-tegra/nvrm/io/ap20/ap20rm_slink_hw_private.c b/arch/arm/mach-tegra/nvrm/io/ap20/ap20rm_slink_hw_private.c
new file mode 100644
index 000000000000..dfee4becc53b
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/io/ap20/ap20rm_slink_hw_private.c
@@ -0,0 +1,420 @@
+/*
+ * Copyright (c) 2008-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+/**
+ * @file
+ * @brief <b>nVIDIA driver Development Kit:
+ *           Private functions implementation for the slink Rm driver</b>
+ *
+ * @b Description:  Implements the private functions for the slink hw interface.
+ *
+ */
+
+// hardware includes
+#include "ap20/arslink.h"
+#include "../ap15/rm_spi_slink_hw_private.h"
+#include "nvrm_drf.h"
+#include "nvrm_hardware_access.h"
+#include "nvassert.h"
+#include "nvos.h"
+
+// Enable the hw based chipselect
+#define ENABLE_HW_BASED_CS 0
+
+#define SLINK_REG_READ32(pSlinkHwRegsVirtBaseAdd, reg) \
+        NV_READ32((pSlinkHwRegsVirtBaseAdd) + ((SLINK_##reg##_0)/4))
+#define SLINK_REG_WRITE32(pSlinkHwRegsVirtBaseAdd, reg, val) \
+    do { \
+        NV_WRITE32((((pSlinkHwRegsVirtBaseAdd) + ((SLINK_##reg##_0)/4))), (val)); \
+    } while(0)
+
+
+#define MAX_SLINK_FIFO_DEPTH 32
+#define MAX_SLINK_WORD_FOR_HW_CS 128
+#define MAX_SLINK_PACKET_FOR_HW_CS 64*1024
+
+#define ALL_SLINK_STATUS_CLEAR \
+        (NV_DRF_NUM(SLINK, STATUS,  RDY, 1) | \
+        NV_DRF_NUM(SLINK, STATUS,  RX_UNF, 1) | \
+        NV_DRF_NUM(SLINK, STATUS,  TX_UNF, 1) | \
+        NV_DRF_NUM(SLINK, STATUS,  TX_OVF, 1) | \
+        NV_DRF_NUM(SLINK, STATUS,  RX_OVF, 1))
+
+static void
+SlinkHwSetSignalMode(
+    SerialHwRegisters *pSlinkHwRegs, 
+    NvOdmQuerySpiSignalMode SignalMode);
+
+/**
+ * Initialize the slink register.
+ */
+static void
+SlinkHwRegisterInitialize(
+    NvU32 SlinkInstanceId, 
+    SerialHwRegisters *pSlinkHwRegs)
+{
+    NvU32 CommandReg1;
+    NvU32 CommandReg2;
+    pSlinkHwRegs->InstanceId = SlinkInstanceId;
+    pSlinkHwRegs->pRegsBaseAdd = NULL;
+    pSlinkHwRegs->RegBankSize = 0;
+    pSlinkHwRegs->HwTxFifoAdd = SLINK_TX_FIFO_0;
+    pSlinkHwRegs->HwRxFifoAdd = SLINK_RX_FIFO_0;
+    pSlinkHwRegs->IsPackedMode = NV_FALSE;
+    pSlinkHwRegs->PacketLength = 1;
+    pSlinkHwRegs->CurrSignalMode = NvOdmQuerySpiSignalMode_Invalid;
+    pSlinkHwRegs->MaxWordTransfer = MAX_SLINK_FIFO_DEPTH;
+    pSlinkHwRegs->IsLsbFirst = NV_FALSE;
+    pSlinkHwRegs->IsMasterMode = NV_TRUE;
+    pSlinkHwRegs->IsNonWordAlignedPackModeSupported = NV_TRUE;
+    pSlinkHwRegs->IsHwChipSelectSupported = NV_TRUE;
+
+    CommandReg1 = NV_RESETVAL(SLINK, COMMAND);
+    CommandReg2 = NV_RESETVAL(SLINK, COMMAND2);
+    
+    // Do not toggle the CS between each packet.
+    CommandReg2 = NV_FLD_SET_DRF_DEF(SLINK, COMMAND2, CS_ACTIVE_BETWEEN, HIGH,
+                    CommandReg2);
+
+    CommandReg1 = NV_FLD_SET_DRF_DEF(SLINK, COMMAND, M_S, MASTER, CommandReg1);
+
+    if (pSlinkHwRegs->IsIdleDataOutHigh)
+        CommandReg1 = NV_FLD_SET_DRF_DEF(SLINK, COMMAND, IDLE_SDA, DRIVE_HIGH, CommandReg1);
+    else
+        CommandReg1 = NV_FLD_SET_DRF_DEF(SLINK, COMMAND, IDLE_SDA, DRIVE_LOW, CommandReg1);
+    
+    pSlinkHwRegs->HwRegs.SlinkRegs.Command1 = CommandReg1;
+    pSlinkHwRegs->HwRegs.SlinkRegs.Command2 = CommandReg2;
+    pSlinkHwRegs->HwRegs.SlinkRegs.Status = NV_RESETVAL(SLINK, STATUS);
+    pSlinkHwRegs->HwRegs.SlinkRegs.DmaControl = NV_RESETVAL(SLINK, DMA_CTL);
+}
+
+/**
+ * Set the signal mode of communication whether this is the mode  0, 1, 2 or 3.
+ */
+static void
+SlinkHwSetSignalMode(
+    SerialHwRegisters *pSlinkHwRegs, 
+    NvOdmQuerySpiSignalMode SignalMode)
+{
+    NvU32 CommandReg = pSlinkHwRegs->HwRegs.SlinkRegs.Command1;
+    switch (SignalMode)
+    {
+        case NvOdmQuerySpiSignalMode_0:
+            CommandReg = NV_FLD_SET_DRF_DEF(SLINK, COMMAND, IDLE_SCLK,
+                DRIVE_LOW, CommandReg);
+            CommandReg = NV_FLD_SET_DRF_DEF(SLINK, COMMAND, CK_SDA, FIRST_CLK_EDGE,
+                CommandReg);
+            break;
+
+        case NvOdmQuerySpiSignalMode_1:
+            CommandReg = NV_FLD_SET_DRF_DEF(SLINK, COMMAND, IDLE_SCLK,
+                DRIVE_LOW, CommandReg);
+            CommandReg = NV_FLD_SET_DRF_DEF(SLINK, COMMAND, CK_SDA, SECOND_CLK_EDGE,
+                CommandReg);
+            break;
+
+        case NvOdmQuerySpiSignalMode_2:
+            CommandReg = NV_FLD_SET_DRF_DEF(SLINK, COMMAND, IDLE_SCLK,
+                DRIVE_HIGH, CommandReg);
+            CommandReg = NV_FLD_SET_DRF_DEF(SLINK, COMMAND, CK_SDA, FIRST_CLK_EDGE,
+                CommandReg);
+            break;
+        case NvOdmQuerySpiSignalMode_3:
+            CommandReg = NV_FLD_SET_DRF_DEF(SLINK, COMMAND, IDLE_SCLK,
+                DRIVE_HIGH, CommandReg);
+            CommandReg = NV_FLD_SET_DRF_DEF(SLINK, COMMAND, CK_SDA, SECOND_CLK_EDGE,
+                CommandReg);
+            break;
+        default:
+            NV_ASSERT(!"Invalid SignalMode");
+
+    }
+    pSlinkHwRegs->HwRegs.SlinkRegs.Command1 = CommandReg;
+    SLINK_REG_WRITE32(pSlinkHwRegs->pRegsBaseAdd, COMMAND, CommandReg);
+    pSlinkHwRegs->CurrSignalMode = SignalMode;
+}
+
+/**
+ * Set the chip select polarity bit in the command register.
+ */
+static NvU32
+SetPolarityBits(
+    NvU32 ChipSelectId,
+    NvBool IsHigh,
+    NvU32 Command1)
+{
+    NvU32 CSPolVal = (IsHigh)?0:1;
+    NvU32 CommandReg1 = Command1;
+    switch (ChipSelectId)
+    {
+        case 0:
+            CommandReg1 = NV_FLD_SET_DRF_NUM(SLINK, COMMAND, CS_POLARITY0, 
+                                                       CSPolVal, CommandReg1);
+            break;
+        
+        case 1:
+            CommandReg1 = NV_FLD_SET_DRF_NUM(SLINK, COMMAND, CS_POLARITY1, 
+                                                       CSPolVal, CommandReg1);
+            break;
+        
+        case 2:
+            CommandReg1 = NV_FLD_SET_DRF_NUM(SLINK, COMMAND, CS_POLARITY2, 
+                                                       CSPolVal, CommandReg1);
+            break;
+        
+        case 3:
+            CommandReg1 = NV_FLD_SET_DRF_NUM(SLINK, COMMAND, CS_POLARITY3, 
+                                                       CSPolVal, CommandReg1);
+            break;
+        
+        default:
+            NV_ASSERT(!"Invalid ChipSelectId");
+    }     
+    return CommandReg1;
+}
+
+/**
+ * Set the chip select numbers in the command register.
+ */
+static NvU32
+SetCSNumber(
+    NvU32 ChipSelectId,
+    NvU32 Command2)
+{
+    NvU32 CommandReg2 = Command2;
+    switch (ChipSelectId)
+    {
+        case 0:
+            CommandReg2 = NV_FLD_SET_DRF_DEF(SLINK, COMMAND2, SS_EN, CS0, CommandReg2);
+            break;
+        
+        case 1:
+            CommandReg2 = NV_FLD_SET_DRF_DEF(SLINK, COMMAND2, SS_EN, CS1, CommandReg2);
+            break;
+        
+        case 2:
+            CommandReg2 = NV_FLD_SET_DRF_DEF(SLINK, COMMAND2, SS_EN, CS2, CommandReg2);
+            break;
+        
+        case 3:
+            CommandReg2 = NV_FLD_SET_DRF_DEF(SLINK, COMMAND2, SS_EN, CS3, CommandReg2);
+            break;
+        
+        default:
+            NV_ASSERT(!"Invalid ChipSelectId");
+    }     
+    return CommandReg2;
+}
+
+/**
+ * Set the chip select signal level to be default based on device during the
+ * initialization.
+ */
+static void
+SlinkHwSetChipSelectDefaultLevel(
+    SerialHwRegisters *pSlinkHwRegs, 
+    NvU32 ChipSelectId,
+    NvBool IsHigh)
+{
+    NvU32 CommandReg1;
+    CommandReg1 = SetPolarityBits(ChipSelectId, IsHigh, 
+                            pSlinkHwRegs->HwRegs.SlinkRegs.Command1);
+    pSlinkHwRegs->HwRegs.SlinkRegs.Command1 = CommandReg1;
+    SLINK_REG_WRITE32(pSlinkHwRegs->pRegsBaseAdd, COMMAND, CommandReg1);
+}
+
+/**
+ * Set the chip select signal level.
+ */
+static void
+SlinkHwSetChipSelectLevel(
+    SerialHwRegisters *pSlinkHwRegs, 
+    NvU32 ChipSelectId,
+    NvBool IsHigh)
+{
+    NvU32 CommandReg1;
+    NvU32 CommandReg2;
+
+    // Select SW based CS
+    CommandReg1 = SetPolarityBits(ChipSelectId, IsHigh, 
+                                pSlinkHwRegs->HwRegs.SlinkRegs.Command1);
+    CommandReg1 = NV_FLD_SET_DRF_DEF(SLINK, COMMAND, CS_SW, SOFT, CommandReg1);
+
+    pSlinkHwRegs->HwRegs.SlinkRegs.Command1 = CommandReg1;
+    SLINK_REG_WRITE32(pSlinkHwRegs->pRegsBaseAdd, COMMAND, CommandReg1);
+
+
+    CommandReg2 = SetCSNumber(ChipSelectId, pSlinkHwRegs->HwRegs.SlinkRegs.Command2);
+    pSlinkHwRegs->HwRegs.SlinkRegs.Command2 = CommandReg2;
+    SLINK_REG_WRITE32(pSlinkHwRegs->pRegsBaseAdd, COMMAND2, 
+                            pSlinkHwRegs->HwRegs.SlinkRegs.Command2);
+}
+/**
+ * Set the chip select signal level based on the transfer size.
+ * it can use the hw based CS or SW based CS based on transfer size and
+ * cpu/apb dma based transfer.
+ * Return NV_TRUE if the SW based chipselection is used otherwise return
+ * NV_FALSE;
+ */
+static NvBool
+SlinkHwSetChipSelectLevelBasedOnPacket(
+    SerialHwRegisters *pSlinkHwRegs, 
+    NvU32 ChipSelectId,
+    NvBool IsHigh,
+    NvU32 PacketRequested,
+    NvU32 PacketPerWord,
+    NvBool IsApbDmaBasedTransfer,
+    NvBool IsOnlyUseSWCS)
+{
+    NvU32 MaxWordReq;
+    NvU32 CommandReg1;
+    NvU32 CommandReg2;
+    NvU32 RefillCount = 0;
+#if ENABLE_HW_BASED_CS 
+    NvBool UseSWBaseCS = IsOnlyUseSWCS;
+#else    
+    NvBool UseSWBaseCS = NV_TRUE;
+#endif    
+    
+    if (!UseSWBaseCS)
+    {
+        if (IsApbDmaBasedTransfer)
+        {
+            UseSWBaseCS = (PacketRequested <= MAX_SLINK_PACKET_FOR_HW_CS)? 
+                                NV_FALSE: NV_TRUE;
+        }    
+        else
+        {
+            MaxWordReq = (PacketRequested + PacketPerWord -1)/PacketPerWord;
+            NV_ASSERT(MaxWordReq);
+            if (MaxWordReq <= MAX_SLINK_WORD_FOR_HW_CS)
+            {
+                RefillCount = (MaxWordReq)/MAX_SLINK_FIFO_DEPTH;
+                UseSWBaseCS = NV_FALSE;    
+            }
+            else
+            {
+                UseSWBaseCS = NV_TRUE;
+            }
+        }
+    }
+    if (UseSWBaseCS)
+    {
+        SlinkHwSetChipSelectLevel(pSlinkHwRegs, ChipSelectId, IsHigh);
+        return NV_TRUE;
+    }
+    
+    // Select HW based chipselect.
+    CommandReg1 = NV_FLD_SET_DRF_DEF(SLINK, COMMAND, CS_SW, HARD, 
+                                    pSlinkHwRegs->HwRegs.SlinkRegs.Command1);
+    
+    CommandReg2 = SetCSNumber(ChipSelectId, 
+                                    pSlinkHwRegs->HwRegs.SlinkRegs.Command2);
+    if (!IsApbDmaBasedTransfer)
+        CommandReg2 = NV_FLD_SET_DRF_NUM(SLINK, COMMAND2, FIFO_REFILLS, 
+                                        RefillCount, CommandReg2);
+                                        
+    pSlinkHwRegs->HwRegs.SlinkRegs.Command1 = CommandReg1;
+    SLINK_REG_WRITE32(pSlinkHwRegs->pRegsBaseAdd, COMMAND, 
+                            pSlinkHwRegs->HwRegs.SlinkRegs.Command1);
+    
+    pSlinkHwRegs->HwRegs.SlinkRegs.Command2 = CommandReg2;
+    SLINK_REG_WRITE32(pSlinkHwRegs->pRegsBaseAdd, COMMAND2, 
+                            pSlinkHwRegs->HwRegs.SlinkRegs.Command2);
+                            
+    return NV_FALSE;
+}
+
+/**
+ * Write into the transmit fifo register.
+ * returns the number of words written.
+ */
+static NvU32
+SlinkHwWriteInTransmitFifo(
+    SerialHwRegisters *pSlinkHwRegs, 
+    NvU32 *pTxBuff,  
+    NvU32 WordRequested)
+{
+    NvU32 WordWritten = 0;
+    NvU32 WordsRemaining;
+    NvU32 SlinkFifoEmptyCountReg = SLINK_REG_READ32(pSlinkHwRegs->pRegsBaseAdd, STATUS2);
+    SlinkFifoEmptyCountReg = NV_DRF_VAL(SLINK, STATUS2, TX_FIFO_EMPTY_COUNT, SlinkFifoEmptyCountReg);
+    WordsRemaining = NV_MIN(WordRequested, SlinkFifoEmptyCountReg);
+    WordWritten = WordsRemaining;
+    while (WordsRemaining)
+    {
+        SLINK_REG_WRITE32(pSlinkHwRegs->pRegsBaseAdd, TX_FIFO, *pTxBuff);
+        pTxBuff++;
+        WordsRemaining--;
+    }
+    return WordWritten;
+}
+
+/**
+ * Read the data from the receive fifo.
+ * Returns the number of words it read.   
+ */
+static NvU32
+SlinkHwReadFromReceiveFifo(
+    SerialHwRegisters *pSlinkHwRegs, 
+    NvU32 *pRxBuff,  
+    NvU32 WordRequested)
+{
+    NvU32 WordsRemaining;
+    NvU32 SlinkFifoFullCountReg =  SLINK_REG_READ32(pSlinkHwRegs->pRegsBaseAdd, STATUS2);
+    NvU32 WordsRead;
+   
+    SlinkFifoFullCountReg = NV_DRF_VAL(SLINK, STATUS2, RX_FIFO_FULL_COUNT, SlinkFifoFullCountReg);
+    WordsRemaining = NV_MIN(WordRequested, SlinkFifoFullCountReg);
+    WordsRead = WordsRemaining;
+    while (WordsRemaining)
+    {
+        *pRxBuff = SLINK_REG_READ32(pSlinkHwRegs->pRegsBaseAdd, RX_FIFO);
+        pRxBuff++;
+        WordsRemaining--;
+    }
+    return WordsRead;
+}
+
+/**
+ * Initialize the slink intterface for the hw access.
+ */
+void NvRmPrivSpiSlinkInitSlinkInterface_v1_1(HwInterface *pSlinkInterface)
+{
+    pSlinkInterface->HwRegisterInitializeFxn = SlinkHwRegisterInitialize;
+    pSlinkInterface->HwSetSignalModeFxn = SlinkHwSetSignalMode;
+    pSlinkInterface->HwSetChipSelectDefaultLevelFxn = SlinkHwSetChipSelectDefaultLevel;
+    pSlinkInterface->HwSetChipSelectLevelFxn = SlinkHwSetChipSelectLevel;
+    pSlinkInterface->HwSetChipSelectLevelBasedOnPacketFxn = SlinkHwSetChipSelectLevelBasedOnPacket;
+    pSlinkInterface->HwWriteInTransmitFifoFxn = SlinkHwWriteInTransmitFifo;
+    pSlinkInterface->HwReadFromReceiveFifoFxn =  SlinkHwReadFromReceiveFifo;
+}
diff --git a/arch/arm/mach-tegra/nvrm/io/common/Makefile b/arch/arm/mach-tegra/nvrm/io/common/Makefile
new file mode 100644
index 000000000000..20dd00daed21
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/io/common/Makefile
@@ -0,0 +1,17 @@
+ccflags-y += -DNV_IS_AVP=0
+ccflags-y += -DNV_OAL=0
+ccflags-y += -DNV_USE_FUSE_CLOCK_ENABLE=0
+ifeq ($(CONFIG_MACH_TEGRA_GENERIC_DEBUG),y)
+ccflags-y += -DNV_DEBUG=1
+else
+ccflags-y += -DNV_DEBUG=0
+endif
+
+ccflags-y += -Iarch/arm/mach-tegra/nvrm/core/common
+ccflags-y += -Iarch/arm/mach-tegra/nvrm/io/common
+ccflags-y += -Iarch/arm/mach-tegra/nvrm/io
+ccflags-y += -Iarch/arm/mach-tegra/nvrm/core
+
+obj-y += nvrm_i2c.o
+obj-y += nvrm_gpioi2c.o
+obj-y += nvrm_owr.o
diff --git a/arch/arm/mach-tegra/nvrm/io/common/nvrm_gpioi2c.c b/arch/arm/mach-tegra/nvrm/io/common/nvrm_gpioi2c.c
new file mode 100644
index 000000000000..8dd5d910047b
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/io/common/nvrm_gpioi2c.c
@@ -0,0 +1,463 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include "nvrm_i2c_private.h"
+#include "nvassert.h"
+
+#define NVRM_SOFT_I2C_ENABLE_PRINTF (0)
+
+#if (NV_DEBUG && NVRM_SOFT_I2C_ENABLE_PRINTF)
+#define  I2C_DUMP1(x)   NvOsDebugPrintf x
+#define  I2C_DUMP(x)   NvOsDebugPrintf x
+#else
+#define  I2C_DUMP1(x)
+#define  I2C_DUMP(x)
+#endif
+
+#define WAIT_USEC(x)   NvOsWaitUS(x)
+
+static void I2CSetHigh( NvRmI2cController *c );
+static void I2CStart( NvRmI2cController *c );
+static void I2CStop( NvRmI2cController *c );
+
+static NvU8 I2CReadByte( NvRmI2cController *c );
+static NvError I2CWriteByte( NvRmI2cController *c, NvU8 data);
+
+static NvU8 I2CReadBit( NvRmI2cController *c );
+static NvError I2CWriteBit( NvRmI2cController *c, NvU8 bit);
+
+NV_INLINE static void I2CClockHigh(NvRmI2cController *c);
+NV_INLINE static void I2CClockLow(NvRmI2cController *c);
+NV_INLINE static void I2CDataHigh( NvRmI2cController *c );
+NV_INLINE static void I2CDataLow(NvRmI2cController *c);
+NV_INLINE static void I2CWaitDataHigh(NvRmI2cController *c);
+NV_INLINE static NvU8 I2CDataRead( NvRmI2cController *c );
+
+NvError
+NvRmGpioI2cRead( NvRmI2cController *c,
+         NvU32          slaveAddr,
+         NvU8           *pDataBytes,
+         NvU32          len,
+         NvU32          flags);
+
+NvError
+NvRmGpioI2cWrite( NvRmI2cController *c,
+          NvU32         slaveAddr,
+          NvU8          *pDataBytes,
+          NvU32         len,
+          NvU32         flags);
+
+NvError NvRmGpioI2cTransaction(
+        NvRmI2cController *c, 
+        NvU32 I2cPinMap,
+        NvU8 *Data, 
+        NvU32 DataLength, 
+        NvRmI2cTransactionInfo * Transaction, 
+        NvU32 NumOfTransactions)
+{
+    NvU32 i;
+    NvError status = NvSuccess;
+    NvU32 clockPeriod;
+    NvRmGpioPinState val = 0;
+
+    NV_ASSERT(Transaction);
+    NV_ASSERT(Data);
+    NV_ASSERT((c->hSdaPin && !I2cPinMap) ||
+              (!c->hSdaPin && I2cPinMap));
+
+    /* Convert frequency to period */
+    clockPeriod =  (NvU32)(1000 / c->clockfreq);
+    if (clockPeriod * c->clockfreq  < 1000) 
+    {
+        /* This is a ciel operation */
+        clockPeriod++;
+    }
+    c->I2cClockPeriod = clockPeriod;
+
+    if (I2cPinMap)
+    {
+        NvU32 scl, sda;
+        if ((c->GetGpioPins)(c, I2cPinMap, &scl, &sda))
+        {
+            status = NvRmGpioAcquirePinHandle(c->hGpio, (scl>>16), (scl&0xffff),
+                                     &c->hSclPin);
+            if(!status)
+                status = NvRmGpioAcquirePinHandle(c->hGpio, (sda>>16), (sda&0xffff),
+                                         &c->hSdaPin);
+            if(status)
+            {
+                NvRmGpioReleasePinHandles(c->hGpio, &c->hSclPin, 1);
+                NvRmGpioReleasePinHandles(c->hGpio, &c->hSdaPin, 1);
+                c->hSclPin = 0;
+                c->hSdaPin = 0;
+                return status;
+            }
+        }
+        else
+            return NvError_NotSupported;
+    }
+
+    NV_ASSERT(c->hSclPin && c->hSdaPin);
+
+    I2C_DUMP1(("Clock period = %d", clockPeriod));
+
+    /* Load the outputs register to 0, as we always drive the pin low, if at all
+     * we are driving the pin. Otherwise, we make put the pin input mode,
+     * causing the pin to be tristated. */
+    NvRmGpioWritePins(c->hGpio, &c->hSdaPin, &val, 1);
+    NvRmGpioWritePins(c->hGpio, &c->hSclPin, &val, 1);
+
+    NvRmGpioConfigPins(c->hGpio, &c->hSdaPin, 1, NvRmGpioPinMode_InputData);
+    NvRmGpioConfigPins(c->hGpio, &c->hSclPin, 1, NvRmGpioPinMode_InputData);
+
+    /* No support yet for repeat start */
+    i = 0;
+    while ( i < NumOfTransactions )
+    {
+        if ( Transaction[i].Flags & NVRM_I2C_WRITE )
+        {
+            status = NvRmGpioI2cWrite(c, Transaction[i].Address, 
+                    Data, Transaction[i].NumBytes, Transaction[i].Flags);
+        }            
+        else if ( Transaction[i].Flags & NVRM_I2C_READ )
+        {
+            status = NvRmGpioI2cRead(c, Transaction[i].Address, Data, 
+                    Transaction[i].NumBytes, Transaction[i].Flags);
+        }
+        Data += Transaction[i].NumBytes;
+        i++;
+
+        if (status != NvSuccess)
+            break;
+    }
+
+    /* Put back the pins in function mode */
+    NvRmGpioConfigPins(c->hGpio, &c->hSdaPin, 1, NvRmGpioPinMode_Function);
+    NvRmGpioConfigPins(c->hGpio, &c->hSclPin, 1, NvRmGpioPinMode_Function);
+
+    if (I2cPinMap)
+    {
+        NvRmGpioReleasePinHandles(c->hGpio, &c->hSclPin, 1);
+        NvRmGpioReleasePinHandles(c->hGpio, &c->hSdaPin, 1);
+        c->hSclPin = 0;
+        c->hSdaPin = 0;
+    }
+
+    return status;
+}
+
+NvError
+NvRmGpioI2cRead( NvRmI2cController *c,
+         NvU32          slaveAddr,
+         NvU8           *pDataBytes,
+         NvU32          len,
+         NvU32          flags)
+{
+    NV_ASSERT(c->hGpio);
+
+    /* LSB is always 1 for reads */
+    slaveAddr = slaveAddr | 0x1;
+    I2CStart( c );
+
+    if (I2CWriteByte( c, (NvU8)slaveAddr)  != NvSuccess)
+    {
+        I2C_DUMP1(("I2CReadPacket : no ACK for the slave address %x", (slaveAddr >> 1)));
+        I2CStop( c );
+        return NvError_I2cDeviceNotFound;
+    }
+
+    while ( len-- )
+    {
+        *pDataBytes++ = I2CReadByte( c );
+
+        /* For all reads execpt the last byte, master should send the ACK. For
+         * the last byte, it should send the NAK */
+        if (!len)
+        {
+            I2CDataHigh( c );
+        } else
+        {
+            I2CDataLow( c );
+        }
+
+        /* Pulse the clock line */
+        I2CClockHigh( c );
+        WAIT_USEC( (c->I2cClockPeriod + 1) / 2 );
+        I2CClockLow( c );
+        WAIT_USEC( (c->I2cClockPeriod + 1) / 2 );
+
+        /* Release the data line */
+        I2CDataHigh( c );
+    }
+
+    if (flags & NVRM_I2C_NOSTOP)
+    {
+        I2CSetHigh( c );
+    } else
+    {
+        I2CStop( c );
+    }
+
+    return NvSuccess;
+}
+
+NvError
+NvRmGpioI2cWrite( NvRmI2cController *c,
+          NvU32         slaveAddr,
+          NvU8          *pDataBytes,
+          NvU32         len,
+          NvU32         flags)
+{
+    NvError err = NvSuccess;
+
+    NV_ASSERT(c);
+
+    slaveAddr = slaveAddr & ~0x1;
+
+    I2CStart( c );
+
+    if (I2CWriteByte( c, (NvU8)slaveAddr ) != NvSuccess)
+    {
+        I2C_DUMP1(("I2CWrite : no ACK for the slave address %x", slaveAddr));
+        err = NvError_I2cDeviceNotFound;
+        goto fail;
+    }
+
+    while ( len-- )
+    {
+        if (I2CWriteByte( c, *pDataBytes++ ) != NvSuccess)
+        {
+            I2C_DUMP(("I2CWrite: no ACK for the data\r\n"));
+            err = NvError_I2cDeviceNotFound;
+            goto fail;
+        }
+    }
+
+    if (flags & NVRM_I2C_NOSTOP)
+    {
+        I2CSetHigh(c);
+    } else
+fail: 
+    {
+        I2CStop( c );
+    }
+    return err;
+}
+
+static void
+I2CSetHigh( NvRmI2cController *c )
+{
+    I2CWaitDataHigh( c );
+    I2CClockHigh( c );
+}
+
+static void
+I2CStart( NvRmI2cController *c )
+{
+
+    I2CDataLow( c );
+    I2CClockLow( c );
+
+}
+
+static void
+I2CStop( NvRmI2cController *c )
+{
+
+    I2CDataLow( c );
+    I2CClockHigh( c );
+    I2CDataHigh( c );
+
+}
+
+static NvU8
+I2CReadByte( NvRmI2cController *c )
+{
+    int     ctr;
+    NvU8   data;
+
+
+    data = 0;
+    for ( ctr = 0; ctr < 8; ctr++ )
+    {
+       data = (data << 1) | I2CReadBit( c );
+    }
+
+    return data;
+}
+
+static NvError
+I2CWriteByte( NvRmI2cController *c,
+              NvU8     data )
+{
+    NvU32 err = NvSuccess;
+    NvU32       SDA = 0;
+    NvU8        ctr, bit;
+
+    for ( ctr = 0; ctr < 8; ctr++ )
+    {
+       bit = (data >> (7 - ctr)) & 0x01;
+       (void)I2CWriteBit( c, bit );
+    }
+   
+    /* Wait for ACK from slave i.e tristate the Data and pulse the clock and
+     * check if the data line is driven low during the clock high stage.
+     */
+    I2CDataHigh( c );
+    I2CClockHigh( c );
+
+    WAIT_USEC( (c->I2cClockPeriod + 1) / 2 );
+    
+    SDA = I2CDataRead( c );
+    if (SDA)
+    {
+        err = NvError_I2cDeviceNotFound;
+    }
+
+    I2CClockLow( c );
+
+    WAIT_USEC( (c->I2cClockPeriod + 1) / 2 );
+
+    return err;
+}
+
+static NvU8
+I2CReadBit( NvRmI2cController *c )
+{
+    NvU8   SDA = 0;
+
+    I2CDataHigh( c );    // DATA set to high first
+    I2CClockHigh( c );
+    
+    WAIT_USEC( (c->I2cClockPeriod + 1) / 2 );
+
+    SDA = I2CDataRead( c );
+
+    I2CClockLow( c );
+
+    WAIT_USEC( (c->I2cClockPeriod + 1) / 2 );
+
+    return SDA;
+}
+
+static NvError
+I2CWriteBit( NvRmI2cController *c,
+             NvU8      bit )
+{
+    if ( bit & 0x1 )
+        I2CDataHigh( c );
+    else
+        I2CDataLow( c );
+
+    I2CClockHigh( c );
+    WAIT_USEC( (c->I2cClockPeriod + 1) / 2 );
+    I2CClockLow( c );
+    WAIT_USEC( (c->I2cClockPeriod + 1) / 2 );
+
+    return NvSuccess;
+}
+
+static void
+I2CClockHigh( NvRmI2cController *c )
+{
+    // The scheme is to make SCL pin in tri-state, thus depends on
+    // outside pull-up to generate High condition.  To be in this
+    // tri-state, enable SCL pin with IN direction.  Then, always
+    // clear the latched SDA and SCL bits in the register in preparation
+    // for any next switching to Data Low condition (pin direction changed
+    // to OUT).
+    NvU32 timeout = c->timeout * 1000 / c->I2cClockPeriod ;
+    NvU32   inout;
+
+    NvRmGpioConfigPins(c->hGpio, &c->hSclPin, 1, NvRmGpioPinMode_InputData);
+
+    // check whether slave doesn't hold SCL low
+    // if so, wait for certain timeout for release by slave    
+    do
+    {
+        WAIT_USEC( c->I2cClockPeriod );
+        NvRmGpioReadPins(c->hGpio, &c->hSclPin, (NvRmGpioPinState *)&inout, 1);
+        if ( inout )
+        {
+            return;
+        }
+    } while ( timeout-- );
+}
+
+NV_INLINE static void
+I2CClockLow( NvRmI2cController *c )
+{
+    NvRmGpioConfigPins(c->hGpio, &c->hSclPin, 1, NvRmGpioPinMode_Output);
+}
+
+NV_INLINE static void
+I2CDataHigh( NvRmI2cController *c )
+{
+    NvRmGpioConfigPins(c->hGpio, &c->hSdaPin, 1, NvRmGpioPinMode_InputData);
+}
+
+NV_INLINE static void
+I2CDataLow( NvRmI2cController *c )
+{
+    NvRmGpioConfigPins(c->hGpio, &c->hSdaPin, 1, NvRmGpioPinMode_Output);
+}
+
+NV_INLINE static void
+I2CWaitDataHigh( NvRmI2cController *c )
+{
+    NvU32 timeout = c->timeout * 1000 / c->I2cClockPeriod ;
+    NvU32   inout;
+
+    do
+    {
+        WAIT_USEC( c->I2cClockPeriod );
+
+        NvRmGpioConfigPins(c->hGpio, &c->hSdaPin, 1, NvRmGpioPinMode_InputData);
+        NvRmGpioReadPins(c->hGpio, &c->hSdaPin, (NvRmGpioPinState *)&inout, 1);
+        if ( inout )
+        {
+            return;
+        }
+    } while ( timeout-- );
+}
+
+NV_INLINE static NvU8
+I2CDataRead( NvRmI2cController *c )
+{
+    NvU32   data;
+
+    NvRmGpioConfigPins(c->hGpio, &c->hSdaPin, 1, NvRmGpioPinMode_InputData);
+    NvRmGpioReadPins(c->hGpio, &c->hSdaPin, (NvRmGpioPinState *)&data, 1);
+
+    return (NvU8)(data);
+}
+
diff --git a/arch/arm/mach-tegra/nvrm/io/common/nvrm_i2c.c b/arch/arm/mach-tegra/nvrm/io/common/nvrm_i2c.c
new file mode 100644
index 000000000000..bfc37c1d2a11
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/io/common/nvrm_i2c.c
@@ -0,0 +1,678 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+
+/** @file
+ * @brief <b>NVIDIA Driver Development Kit: I2C API</b>
+ *
+ * @b Description: Contains the NvRM I2C implementation.
+ */
+
+#include "nvrm_i2c.h"
+#include "nvrm_i2c_private.h"
+#include "nvrm_drf.h"
+#include "nvos.h"
+#include "nvrm_module.h"
+#include "nvrm_hardware_access.h"
+#include "nvrm_power.h"
+#include "nvrm_interrupt.h"
+#include "nvassert.h"
+#include "nvodm_query_pinmux.h"
+#include "nvrm_pinmux.h"
+#include "nvrm_chiplib.h"
+#include "nvrm_hwintf.h"
+#include "nvodm_modules.h"
+#include "nvrm_structure.h"
+#include "nvrm_pinmux_utils.h"
+
+/* Array of controllers */
+static NvRmI2cController gs_I2cControllers[MAX_I2C_INSTANCES];
+static NvRmI2cController *gs_Cont = NULL;
+
+// Maximum I2C instances present in this SOC
+static NvU32 MaxI2cControllers;
+static NvU32 MaxDvcControllers;
+static NvU32 MaxI2cInstances;
+
+static NvError PrivI2cSetSpeed(NvRmI2cController *c);
+static NvError PrivI2cConfigurePower(NvRmI2cController *c, NvBool IsEnablePower);
+
+/**
+ * Get the I2C  SOC capability.
+ *
+ */
+static void
+I2cGetSocCapabilities(
+    NvRmDeviceHandle hDevice,
+    NvRmModuleID ModuleId,
+    NvU32 Instance,
+    SocI2cCapability *pI2cSocCaps)
+{
+    static SocI2cCapability s_SocI2cCapsList[2];
+    NvRmModuleCapability I2cCapsList[3];
+    SocI2cCapability *pI2cCaps = NULL;
+
+    if (ModuleId == NvRmModuleID_I2c)
+    {
+        I2cCapsList[0].MajorVersion = 1;
+        I2cCapsList[0].MinorVersion = 0;
+        I2cCapsList[0].EcoLevel = 0;
+        I2cCapsList[0].Capability = &s_SocI2cCapsList[0];
+
+        I2cCapsList[1].MajorVersion = 1;
+        I2cCapsList[1].MinorVersion = 1;
+        I2cCapsList[1].EcoLevel = 0;
+        I2cCapsList[1].Capability = &s_SocI2cCapsList[0];
+
+        //AP15 A01P and A02 does not support packet interface
+        s_SocI2cCapsList[0].IsNewMasterAvailable = NV_FALSE;
+
+        I2cCapsList[2].MajorVersion = 1;
+        I2cCapsList[2].MinorVersion = 2;
+        I2cCapsList[2].EcoLevel = 0;
+        I2cCapsList[2].Capability = &s_SocI2cCapsList[1];
+
+        // AP20 supports Packet based interface with new master enable
+        s_SocI2cCapsList[1].IsNewMasterAvailable= NV_TRUE;
+
+        // Get the capability from modules files.
+        NV_ASSERT_SUCCESS(NvRmModuleGetCapabilities(hDevice,
+                    NVRM_MODULE_ID(ModuleId, Instance), I2cCapsList,
+                    NV_ARRAY_SIZE(I2cCapsList), (void **)&pI2cCaps));
+    }
+    else if (ModuleId == NvRmModuleID_Dvc)
+    {
+        I2cCapsList[0].MajorVersion = 1;
+        I2cCapsList[0].MinorVersion = 0;
+        I2cCapsList[0].EcoLevel = 0;
+        I2cCapsList[0].Capability = &s_SocI2cCapsList[0];
+
+        // AP15 does not support new master interface
+        s_SocI2cCapsList[0].IsNewMasterAvailable= NV_FALSE;
+
+        I2cCapsList[1].MajorVersion = 1;
+        I2cCapsList[1].MinorVersion = 1;
+        I2cCapsList[1].EcoLevel = 0;
+        I2cCapsList[1].Capability = &s_SocI2cCapsList[1];
+
+        // AP20 supports new master interface ans capable of doing the
+        // packed mode transfer.
+        s_SocI2cCapsList[1].IsNewMasterAvailable= NV_TRUE;
+
+        // Get the capability from modules files.
+        NV_ASSERT_SUCCESS(NvRmModuleGetCapabilities(hDevice,
+                    NVRM_MODULE_ID(ModuleId, Instance), I2cCapsList,
+                    NV_ARRAY_SIZE(I2cCapsList), (void **)&pI2cCaps));
+    }
+    if (pI2cCaps)
+        pI2cSocCaps->IsNewMasterAvailable= pI2cCaps->IsNewMasterAvailable;
+    else
+        NV_ASSERT(!"Invalid ModuleId is passed to I2cGetSocCapabilities() ");
+}
+
+NvError
+NvRmI2cOpen(
+    NvRmDeviceHandle hRmDevice,
+    NvU32 IoModule,
+    NvU32 instance,
+    NvRmI2cHandle *phI2c)
+{
+    NvError status = NvSuccess;
+    NvU32 PrefClockFreq = MAX_I2C_CLOCK_SPEED_KHZ;
+    NvU32 Index = instance;
+    NvRmModuleID ModuleID = NvRmModuleID_I2c;
+    NvRmI2cController *c;
+    NvOsMutexHandle hThreadSaftyMutex = NULL;
+    const NvU32 *pOdmConfigs;
+    NvU32 NumOdmConfigs;
+
+
+    NV_ASSERT(hRmDevice);
+    NV_ASSERT(phI2c);
+    NV_ASSERT((IoModule == NvOdmIoModule_I2c) || (IoModule == NvOdmIoModule_I2c_Pmu));
+
+    *phI2c = 0;
+    /* If none of the controller is opened, allocate memory for all controllers
+    * in the system */
+    if (gs_Cont == NULL)
+    {
+        gs_Cont = gs_I2cControllers;
+        MaxI2cControllers = NvRmModuleGetNumInstances(hRmDevice, NvRmModuleID_I2c);
+        MaxDvcControllers = NvRmModuleGetNumInstances(hRmDevice, NvRmModuleID_Dvc);
+        MaxI2cInstances = MaxI2cControllers + MaxDvcControllers;
+    }
+    /* Validate the instance number passed and return the Index of the
+     * controller to the caller.
+     *
+     */
+    if (IoModule == NvOdmIoModule_I2c)
+    {
+        NV_ASSERT(instance < MaxI2cControllers);
+        ModuleID = NvRmModuleID_I2c;
+        Index = instance;
+    }
+    else  if (IoModule == NvOdmIoModule_I2c_Pmu)
+    {
+        NV_ASSERT(instance < MaxDvcControllers);
+        ModuleID = NvRmModuleID_Dvc;
+        Index = MaxI2cControllers + instance;
+    }
+    else
+    {
+        NV_ASSERT(!"Invalid IO module");
+        return NvError_NotSupported;
+    }
+
+    c = &(gs_Cont[Index]);
+
+    // Create the mutex for providing the thread safety for i2c API
+    if ((c->NumberOfClientsOpened == 0) && (c->I2cThreadSafetyMutex == NULL))
+    {
+        status = NvOsMutexCreate(&hThreadSaftyMutex);
+        if (status)
+            return status;
+
+        if (NvOsAtomicCompareExchange32((NvS32*)&c->I2cThreadSafetyMutex, 0,
+                                                    (NvS32)hThreadSaftyMutex)!=0)
+        {
+            NvOsMutexDestroy(hThreadSaftyMutex);
+            hThreadSaftyMutex = NULL;
+        }
+    }
+
+    NvOsMutexLock(c->I2cThreadSafetyMutex);
+    // If no clients are opened yet, initialize the i2c controller
+    if (c->NumberOfClientsOpened == 0)
+    {
+        /* Polulate the controller structure */
+        c->hRmDevice = hRmDevice;
+        c->OdmIoModule = IoModule;
+        c->ModuleId = ModuleID;
+        c->Instance = instance;
+
+        c->I2cPowerClientId = 0;
+        c->receive  = NULL;
+        c->send = NULL;
+        c->close = NULL;
+        c->GetGpioPins = NULL;
+        c->hGpio = NULL;
+        c->hSclPin = 0;
+        c->hSdaPin = 0;
+
+
+        I2cGetSocCapabilities(hRmDevice, ModuleID, instance, &(c->SocI2cCaps));
+        c->EnableNewMaster = c->SocI2cCaps.IsNewMasterAvailable;
+
+        NvOdmQueryPinMux(IoModule, &pOdmConfigs, &NumOdmConfigs);
+        NV_ASSERT((instance < NumOdmConfigs) && (pOdmConfigs[instance]));
+        if ((instance >= NumOdmConfigs) || (!pOdmConfigs[instance]))
+        {
+            status = NvError_NotSupported;
+            goto fail_1;
+        }
+        c->PinMapConfig = pOdmConfigs[instance];
+
+        /* Call appropriate open function according to the controller
+         * supports packet mode or not. If packet mode is supported
+         * call AP20RmI2cOpen for packet mode funcitons. Other wise
+         * use normal mode */
+        if (c->SocI2cCaps.IsNewMasterAvailable)
+            status = AP20RmI2cOpen(c);
+        else
+            status = AP15RmI2cOpen(c);
+
+        if (status)
+            goto fail_1;
+        /* Make sure that all the functions are polulated by the HAL driver */
+        NV_ASSERT(c->receive && c->send && c->close);
+
+        status = NvRmSetModuleTristate(c->hRmDevice,
+                        NVRM_MODULE_ID(c->ModuleId, c->Instance), NV_FALSE);
+        if (status != NvSuccess)
+        {
+            goto fail_1;
+        }
+
+        /* Initalize the GPIO handles only */
+        if (c->GetGpioPins)
+        {
+            status = NvRmGpioOpen(c->hRmDevice, &c->hGpio);
+            if(status)
+                goto fail_1;
+        }
+
+        c->I2cPowerClientId = NVRM_POWER_CLIENT_TAG('I','2','C',' ');
+        status = NvRmPowerRegister(hRmDevice, NULL, &c->I2cPowerClientId);
+        if (status != NvSuccess)
+        {
+            goto fail_2;
+        }
+
+        /* Enable power rail, enable clock, configure clock to right freq,
+         * reset, disable clock, notify to disable power rail.
+         *
+         *  All of this is done to just reset the controller.
+         * */
+        PrivI2cConfigurePower(c, NV_TRUE);
+        status = NvRmPowerModuleClockConfig(hRmDevice,
+                NVRM_MODULE_ID(ModuleID, instance), c->I2cPowerClientId,
+                PrefClockFreq, NvRmFreqUnspecified, &PrefClockFreq, 1, NULL, 0);
+        if (status != NvSuccess)
+        {
+            goto fail_3;
+        }
+        NvRmModuleReset(hRmDevice, NVRM_MODULE_ID(ModuleID, instance));
+
+        PrivI2cConfigurePower(c, NV_FALSE);
+    }
+    c->NumberOfClientsOpened++;
+    NvOsMutexUnlock(c->I2cThreadSafetyMutex);
+
+    /*
+     * We cannot return handle with a value of 0, as some clients check the
+     * handle to ne non-zero. So, to get around that we set MSB bit to 1.
+     */
+    *phI2c = (NvRmI2cHandle)(Index | 0x80000000);
+    return NvSuccess;
+
+fail_3:
+    PrivI2cConfigurePower(c, NV_FALSE);
+
+fail_2:
+    NvRmPowerUnRegister(hRmDevice, c->I2cPowerClientId);
+    c->I2cPowerClientId = 0;
+
+fail_1:
+    (c->close)(c);
+    *phI2c = 0;
+    NvRmGpioReleasePinHandles(c->hGpio, &c->hSclPin, 1);
+    NvRmGpioReleasePinHandles(c->hGpio, &c->hSdaPin, 1);
+    NvRmGpioClose(c->hGpio);
+    NvOsMutexUnlock(c->I2cThreadSafetyMutex);
+    NvOsMutexDestroy(c->I2cThreadSafetyMutex);
+    NvOsMemset(c, 0, sizeof(*c));
+
+    return status;
+}
+
+void NvRmI2cClose(NvRmI2cHandle hI2c)
+{
+    NvU32 Index;
+    NvRmI2cController *c;
+
+    if (hI2c == NULL)
+        return;
+
+    Index = ((NvU32) hI2c) & 0xFF;
+    if (Index < MaxI2cInstances)
+    {
+        c = &(gs_Cont[Index]);
+
+        NvOsMutexLock(c->I2cThreadSafetyMutex);
+        c->NumberOfClientsOpened--;
+        if (c->NumberOfClientsOpened == 0)
+        {
+
+            if(c->GetGpioPins)
+            {
+                if (c->hSclPin)
+                    NvRmGpioReleasePinHandles(c->hGpio, &c->hSclPin, 1);
+                if (c->hSdaPin)
+                    NvRmGpioReleasePinHandles(c->hGpio, &c->hSdaPin, 1);
+                c->hSdaPin = 0;
+                c->hSclPin = 0;
+            }
+            NvRmGpioClose(c->hGpio);
+
+            /* Unregister the power client ID */
+            NvRmPowerUnRegister(c->hRmDevice, c->I2cPowerClientId);
+            c->I2cPowerClientId = 0;
+
+            NV_ASSERT_SUCCESS( NvRmSetModuleTristate(c->hRmDevice,
+            NVRM_MODULE_ID(c->ModuleId, c->Instance), NV_TRUE ));
+
+            NV_ASSERT(c->close);
+            (c->close)(c);
+
+            /* FIXME: There is a race here. After the Mutex is unlocked someone can
+            * call NvRmI2cOpen and create the mutex, which will then destropyed
+            * here?
+            * */
+            NvOsMutexUnlock(c->I2cThreadSafetyMutex);
+            NvOsMutexDestroy(c->I2cThreadSafetyMutex);
+            c->I2cThreadSafetyMutex = NULL;
+        }
+        else
+        {
+            NvOsMutexUnlock(c->I2cThreadSafetyMutex);
+        }
+    }
+}
+
+static NvError PrivI2cSetSpeed(NvRmI2cController *c)
+{
+    NvError status;
+    NvRmModuleID ModuleId = NVRM_MODULE_ID(c->ModuleId, c->Instance);
+
+    // It seems like the I2C Controller has an hidden clock divider whose value
+    // is 8. So, request for clock value multipled by 8.
+    NvU32 PrefClockFreq = c->clockfreq * 8;
+
+    status = NvRmPowerModuleClockConfig(
+                c->hRmDevice,
+                ModuleId,
+                c->I2cPowerClientId,
+                NvRmFreqUnspecified,
+                PrefClockFreq,
+                &PrefClockFreq,
+                1,
+                NULL,
+                0);
+    return status;
+}
+
+static NvError PrivI2cConfigurePower(NvRmI2cController *c, NvBool IsEnablePower)
+{
+    NvError status = NvSuccess;
+    NvRmModuleID ModuleId = NVRM_MODULE_ID(c->ModuleId, c->Instance);
+
+    if (IsEnablePower == NV_TRUE)
+    {
+#if !NV_OAL
+        status = NvRmPowerVoltageControl(
+                c->hRmDevice,
+                ModuleId,
+                c->I2cPowerClientId,
+                NvRmVoltsUnspecified,
+                NvRmVoltsUnspecified,
+                NULL,
+                0,
+                NULL);
+#endif
+        if(status == NvSuccess)
+        {
+            // Enable the clock to the i2c controller
+            NV_ASSERT_SUCCESS(NvRmPowerModuleClockControl(c->hRmDevice,
+                        ModuleId,
+                        c->I2cPowerClientId,
+                        NV_TRUE));
+        }
+    }
+    else
+    {
+       // Disable the clock to the i2c controller
+        NV_ASSERT_SUCCESS(NvRmPowerModuleClockControl(c->hRmDevice,
+                    ModuleId,
+                    c->I2cPowerClientId,
+                    NV_FALSE));
+
+#if !NV_OAL
+        //disable power
+        status = NvRmPowerVoltageControl(c->hRmDevice,
+                ModuleId,
+                c->I2cPowerClientId,
+                NvRmVoltsOff,
+                NvRmVoltsOff,
+                NULL,
+                0,
+                NULL);
+#endif
+    }
+    return status;
+}
+
+NvError NvRmI2cTransaction(
+    NvRmI2cHandle hI2c,
+    NvU32 I2cPinMap,
+    NvU32 WaitTimeoutInMilliSeconds,
+    NvU32 ClockSpeedKHz,
+    NvU8 *Data,
+    NvU32 DataLength,
+    NvRmI2cTransactionInfo * Transaction,
+    NvU32 NumOfTransactions)
+{
+    NvU32 len = 0;
+    NvError status;
+    NvU32 i;
+    NvU32 BytesTransferred = 0;
+    NvBool useGpioI2c = NV_FALSE;
+    NvRmI2cController* c;
+    NvU32 Index;
+    NvU32 RSCount  = 0; // repeat start count
+    NvS32 StartTransIndex = -1;
+    NvU32 scl, sda;
+
+    Index = ((NvU32)hI2c) & 0x7FFFFFFF;
+
+    NV_ASSERT(((NvU32)hI2c) & 0x80000000);
+    NV_ASSERT(Index < MaxI2cInstances);
+    NV_ASSERT(Transaction);
+    NV_ASSERT(Data);
+    NV_ASSERT(ClockSpeedKHz <= MAX_I2C_CLOCK_SPEED_KHZ);
+
+    c = &(gs_Cont[Index]);
+    if (c->SocI2cCaps.IsNewMasterAvailable == NV_FALSE)
+    {
+        c->timeout = WaitTimeoutInMilliSeconds;
+    }
+    else
+    {
+        c->timeout = 1000;
+    }
+    c->clockfreq = ClockSpeedKHz;
+
+    NV_ASSERT(((c->PinMapConfig == NvOdmI2cPinMap_Multiplexed) && (I2cPinMap)) ||
+              ((c->PinMapConfig != NvOdmI2cPinMap_Multiplexed) && (!I2cPinMap)));
+
+    if (NvRmIsSimulation())
+        return NvError_NotSupported;
+
+    NvOsMutexLock(c->I2cThreadSafetyMutex);
+
+    // If I2C does not support pkt format use narmal mode to transfer the data
+    if (c->SocI2cCaps.IsNewMasterAvailable == NV_FALSE)
+    {
+        /* Do all the transactions using software GPIO, if one of the transactions
+        * failed to satisfy the hardware requirements. */
+        for (i=0; i< NumOfTransactions; i++)
+        {
+            if (Transaction[i].Flags & NVRM_I2C_NOSTOP)
+            {
+                if ((i+1) >= NumOfTransactions)
+                {
+                    useGpioI2c = NV_TRUE;
+                    break;
+                }
+                else
+                {
+                    if ((Transaction[i].NumBytes > NVRM_I2C_PACKETSIZE_WITH_NOSTOP) ||
+                            (Transaction[i].NumBytes != Transaction[i+1].NumBytes))
+                    {
+                        useGpioI2c = NV_TRUE;
+                        break;
+                    }
+                }
+            }
+            else
+            {
+                if (Transaction[i].NumBytes > NVRM_I2C_PACKETSIZE)
+                {
+                    useGpioI2c = NV_TRUE;
+                    break;
+                }
+            }
+        }
+    }
+    if ((Transaction[0].Flags & NVRM_I2C_SOFTWARE_CONTROLLER) ||
+                            (useGpioI2c == NV_TRUE))
+    {
+        if (c->hGpio == NULL)
+        {
+            status = NvRmGpioOpen(c->hRmDevice, &c->hGpio);
+            if(status)
+            {
+                 NvOsMutexUnlock(c->I2cThreadSafetyMutex);
+                 return status;
+            }
+        }
+        /* Initalize the GPIO pin handles if it is not done */
+        if (c->GetGpioPins)
+        {
+            if (c->PinMapConfig != NvOdmI2cPinMap_Multiplexed)
+	    {
+	         if ((c->hSclPin == 0) || (c->hSdaPin == 0))
+                 {
+                      if ((c->GetGpioPins)(c, c->PinMapConfig, &scl, &sda))
+                      {
+                           status = NvRmGpioAcquirePinHandle(c->hGpio,
+                                          (scl >> 16), (scl & 0xFFFF),
+                                           &c->hSclPin);
+                            if(!status)
+                            {
+                                 status = NvRmGpioAcquirePinHandle(c->hGpio,
+                                           (sda >> 16), (sda & 0xFFFF),
+                                           &c->hSdaPin);
+                                 if(status)
+                                 {
+                                      NvRmGpioReleasePinHandles(c->hGpio,
+                                           &c->hSclPin, 1);
+                                      c->hSclPin = 0;
+                                 }
+                            }
+                       }
+                  }
+            }
+        }
+        else
+        {
+            status = NvError_NotSupported;
+        }
+
+        if (status == NvSuccess)
+            status = NvRmGpioI2cTransaction(c, I2cPinMap, Data, DataLength,
+                                        Transaction, NumOfTransactions);
+        NvOsMutexUnlock(c->I2cThreadSafetyMutex);
+        return status;
+    }
+
+    if (I2cPinMap)
+    {
+        NvRmPinMuxConfigSelect(c->hRmDevice, c->OdmIoModule,
+            c->Instance, I2cPinMap);
+
+        NvRmPinMuxConfigSetTristate(c->hRmDevice, c->OdmIoModule,
+            c->Instance, I2cPinMap, NV_FALSE);
+    }
+
+
+    status = PrivI2cConfigurePower(c, NV_TRUE);
+    if (status != NvSuccess)
+        goto TransactionExit;
+
+    status = PrivI2cSetSpeed(c);
+    if (status != NvSuccess)
+        goto TransactionExit;
+
+    len = 0;
+    StartTransIndex = -1;
+    for (i = 0; i < NumOfTransactions; i++)
+    {
+        c->Is10BitAddress = Transaction[i].Is10BitAddress;
+        c->NoACK = NV_FALSE;
+        if (Transaction[i].Flags & NVRM_I2C_NOACK)
+        {
+            c->NoACK = NV_TRUE;
+        }
+        // Check  wheather this transation is repeat start or not
+        if (!(Transaction[i].Flags & NVRM_I2C_NOSTOP) && (!RSCount))
+        {
+            if (Transaction[i].Flags & NVRM_I2C_WRITE)
+            {
+                // i2c send transaction
+                status = (c->send)(
+                        c,
+                        Data,
+                        &Transaction[i],
+                        &BytesTransferred);
+            }
+            else
+            {
+                // i2c receive transaction
+                status = (c->receive)(
+                        c,
+                        Data,
+                        &Transaction[i],
+                        &BytesTransferred);
+            }
+            Data += Transaction[i].NumBytes;
+        }
+        else
+        {
+            RSCount++;
+            // If transation is repeat start,
+            if (Transaction[i].Flags & NVRM_I2C_NOSTOP)
+            {
+                len += Transaction[i].NumBytes;
+                if (StartTransIndex == -1)
+                    StartTransIndex = i;
+            }
+            else
+            {
+                // i2c transaction with repeat-start
+                status = (c->repeatStart)(c, Data, &(Transaction[StartTransIndex]), RSCount);
+                Data += len + Transaction[i].NumBytes;
+                RSCount = 0;
+                len = 0;
+                StartTransIndex = -1;
+            }
+        }
+        if (status != NvSuccess)
+        {
+            break;
+        }
+    }
+TransactionExit:
+    PrivI2cConfigurePower(c, NV_FALSE);
+
+    //  Re-tristate multi-plexed controllers, and re-multiplex the controller.
+    if (I2cPinMap)
+    {
+        NvRmPinMuxConfigSetTristate(c->hRmDevice, c->OdmIoModule,
+            c->Instance, I2cPinMap, NV_TRUE);
+
+        NvRmPinMuxConfigSelect(c->hRmDevice, c->OdmIoModule,
+            c->Instance, c->PinMapConfig);
+    }
+
+    NvOsMutexUnlock(c->I2cThreadSafetyMutex);
+    return status;
+}
diff --git a/arch/arm/mach-tegra/nvrm/io/common/nvrm_i2c_private.h b/arch/arm/mach-tegra/nvrm/io/common/nvrm_i2c_private.h
new file mode 100644
index 000000000000..e7af0aa7c09c
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/io/common/nvrm_i2c_private.h
@@ -0,0 +1,263 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/** @file
+ *
+ * @b Description: Contains the i2c declarations.
+ */
+
+#ifndef INCLUDED_NVRM_I2C_PRIVATE_H
+#define INCLUDED_NVRM_I2C_PRIVATE_H
+
+#include "nvrm_module.h"
+#include "nvodm_query_pinmux.h"
+#include "nvrm_gpio.h"
+#include "nvrm_i2c.h"
+#include "nvrm_memmgr.h"
+#include "nvrm_dma.h"
+#include "nvrm_priv_ap_general.h"
+
+
+#define MAX_I2C_CLOCK_SPEED_KHZ 400
+
+// Maximum number of i2c instances including i2c and dvc and a dummy instance
+#define MAX_I2C_INSTANCES   ((MAX_I2C_CONTROLLERS) + (MAX_DVC_CONTROLLERS) + 1)
+
+/* Delay used while polling(in polling mode) for the transcation to complete */
+#define I2C_DELAY_USEC 10000
+
+typedef enum
+{
+    // Specifies a read transaction.
+    I2C_READ,
+    // Specifies a write transaction.
+    I2C_WRITE,
+    // Specifies a read transaction using i2c repeat start
+    I2C_REPEAT_START_TRANSACTION
+} I2cTransactionType;
+
+/**
+ * SOC I2C  capability structure.
+ */
+typedef struct SocI2cCapabilityRec
+{
+    // Tells whether new master is available or not
+    NvBool IsNewMasterAvailable;
+} SocI2cCapability;
+
+/* I2C controller state. There are will one instance of this structure for each
+ * I2C controller instance */
+typedef struct NvRmI2cControllerRec
+{
+    /* Controller static Information */
+
+    /* Rm device handle */
+    NvRmDeviceHandle hRmDevice;
+    /* Contains the i2ctransfer status */
+    NvError I2cTransferStatus;
+    /* Contains the number of opened clients */
+    NvU32 NumberOfClientsOpened;
+    /* Contains the semaphore id to block the synchronous i2c client calls */
+    NvOsSemaphoreHandle I2cSyncSemaphore;
+    /* Contains the mutex for providing the thread safety */
+    NvOsMutexHandle I2cThreadSafetyMutex;
+    /* Power clinet ID */
+    NvU32 I2cPowerClientId;
+    /* Contoller module ID. I2C is supported via DVS module and I2C module. */
+    NvRmModuleID ModuleId;
+
+    // Odm io module name
+    NvOdmIoModule OdmIoModule;
+
+    
+    /* Instance of the above specified module */
+    NvU32 Instance;
+    // I2C interrupt handle for this controller instance
+    NvOsInterruptHandle I2CInterruptHandle;
+
+    // I2c Pin mux configuration
+    NvU32 PinMapConfig;
+
+    /* GPIO pin handles for SCL and SDA lines. Used by the GPIO fallback mode */
+    NvRmGpioPinHandle hSclPin;
+    NvRmGpioPinHandle hSdaPin;
+    NvRmGpioHandle hGpio;
+
+    /* Controller run time state. These members will be polulated before the HAL
+     * functions are called. HAL functions should only read these members and
+     * should not clobber these registers. */
+
+    /* I2c clock freq */
+    NvU32 clockfreq;
+    /* Slave device address type */
+    NvBool Is10BitAddress;
+    /* Indictaes that the slave will not generate the ACK */
+    NvBool NoACK;
+    /* timeout for the transfer */
+    NvU32 timeout;
+
+    /* Receive data */
+    NvError (*receive)(struct NvRmI2cControllerRec *c, NvU8 * pBuffer, 
+               const NvRmI2cTransactionInfo *pTransaction, NvU32 * pBytesTransferred);
+    
+    /* Send data */
+    NvError (*send)(struct NvRmI2cControllerRec *c, NvU8 * pBuffer, 
+                const NvRmI2cTransactionInfo *pTransaction, NvU32 * pBytesTransferred);
+
+    /* Repeat start - this is specific to the AP15 and will not be called for
+     * later chips */
+    NvError (*repeatStart)(struct NvRmI2cControllerRec *c, NvU8 * pBuffer,
+            NvRmI2cTransactionInfo *Transactions, NvU32 NoOfTransations);
+
+    /* Return the GPIO pin and port numbers of the SDA and SCL lines for that
+     * controller. */
+    NvBool (*GetGpioPins)(struct NvRmI2cControllerRec *c,
+                        NvU32 PinMap, NvU32 *Scl, NvU32 *Sda);
+
+    /* Shutdown the controller */
+    void (*close)(struct NvRmI2cControllerRec *c);
+
+    /* AP15 controller specific state */
+
+    /* Flag to know whether it is a read or a write transaction */
+    I2cTransactionType TransactionType;
+    /* Though all the controllers have same register spec, their start address
+     * doesn't match. DVC contoller I2C register start address differs from the I2C
+     * controller. */
+    NvU32 I2cRegisterOffset;
+
+    //  I2C capabiity for this SOC only.
+    SocI2cCapability SocI2cCaps;
+
+    /* Repeat start transfer */
+    volatile NvBool RsTransfer;
+
+    /* Clock period in micro-seconds */
+    NvU32 I2cClockPeriod;
+    /* I2c Controller Status variable */
+    NvU32 ControllerStatus;
+
+    /* indicates whether to enable new master or not */
+    NvBool EnableNewMaster;
+
+    NvU32 *pDataBuffer;
+
+    // Amount of word transferred yet    
+    NvU32 WordTransferred;
+
+    // Remaining words to be transfer.
+    NvU32 WordRemaining;
+
+    // Final interrupt condition after that transaction completes.
+    NvU32 FinalInterrupt;
+
+    // Content of the interrupt mask register.
+    NvU32 IntMaskReg;
+
+    // Controller Id for packet mode information.
+    NvU32 ControllerId;
+
+    // Tells whether the current transfer is with NO STOP
+    NvBool IsCurrentTransferNoStop;
+
+    // Tells whether the current transfer is with ack or not
+    NvBool IsCurrentTransferNoAck;
+
+    // Tells whether current transfer is a read or write type.
+    NvBool IsCurrentTransferRead;
+
+    // Tells whether transfer is completed or not
+    NvBool IsTransferCompleted;
+
+    // Apb dma related information
+    // Tells whether the dma mode is supported or not.
+    NvBool IsApbDmaAllocated;
+
+    // Dma handle for the read/write.
+    NvRmDmaHandle hRmDma;
+
+    // Memory handle to create the uncached memory.
+    NvRmMemHandle hRmMemory;
+
+    // Dma buffer physical address.
+    NvRmPhysAddr DmaBuffPhysAdd;
+
+    // Virtual pointer to the dma buffer.
+    NvU32 *pDmaBuffer;
+
+    // Current Dma transfer size for the Rx and tx
+    NvU32 DmaBufferSize;
+
+    // Dma request for read transaction
+    NvRmDmaClientBuffer RxDmaReq;
+
+    // Dma request for write transaction
+    NvRmDmaClientBuffer TxDmaReq;
+
+    // Tell whether it is using the apb dma for the transfer or not.
+    NvBool IsUsingApbDma;
+
+    // Buffer which will be used when cpu does the data receving.
+    NvU32 *pCpuBuffer;
+
+    NvU32 TransCountFromLastDmaUsage;
+
+} NvRmI2cController, *NvRmI2cControllerHandle;
+
+NvError NvRmGpioI2cTransaction( 
+        NvRmI2cController *c, 
+        NvU32 I2cPinMap,
+        NvU8 *Data, 
+        NvU32 DataLength, 
+        NvRmI2cTransactionInfo * Transaction, 
+        NvU32 NumOfTransactions);
+
+
+/**
+ * brief Initialze the AP15 I2C controller to start the data transfer 
+ *
+ * This APIs should always return NvSuccess
+ *
+ * @param c    I2C controller structure.
+ * */
+NvError AP15RmI2cOpen(NvRmI2cController *c);
+
+/**
+ * brief Initialze the controller to start the data transfer 
+ *
+ * This APIs should always return NvSuccess
+ *
+ * @param c    I2C controller structure.
+ * */
+NvError AP20RmI2cOpen(NvRmI2cController *c);
+
+#endif  // INCLUDED_NVRM_I2C_PRIVATE_H
diff --git a/arch/arm/mach-tegra/nvrm/io/common/nvrm_owr.c b/arch/arm/mach-tegra/nvrm/io/common/nvrm_owr.c
new file mode 100644
index 000000000000..5571c64acaf6
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/io/common/nvrm_owr.c
@@ -0,0 +1,390 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/** @file
+ * @brief <b>NVIDIA Driver Development Kit: OWR API</b>
+ *
+ * @b Description: Contains the NvRM OWR implementation.
+ */
+
+#include "nvrm_owr.h"
+#include "nvrm_drf.h"
+#include "nvos.h"
+#include "nvrm_module.h"
+#include "nvrm_hardware_access.h"
+#include "nvrm_power.h" 
+#include "nvrm_interrupt.h"
+#include "nvassert.h"
+#include "nvodm_query_pinmux.h"
+#include "nvrm_pinmux.h"
+#include "nvrm_chiplib.h"
+#include "nvrm_hwintf.h"
+#include "nvodm_modules.h"
+#include "nvrm_structure.h"
+#include "nvrm_pinmux_utils.h"
+#include "nvrm_owr_private.h"
+
+// Mask to get the instance from the OWR handle
+// LSB byte of the OWR handle stores the OWR instance.
+#define OWR_HANDLE_INSTANCE_MASK   0xFF
+
+// MSB bit of the OWR handle. MSB bit of the OWR 
+// handle is always set to 1 to make sure OWR handle is never NULL.
+#define OWR_HANDLE_MSB_BIT  0x80000000
+
+/* Array of controllers */
+static NvRmOwrController gs_OwrControllers[MAX_OWR_INSTANCES];
+static NvRmOwrController *gs_OwrCont = NULL;
+
+// Maximum OWR Instances present in this SOC
+static NvU32 MaxOwrInstances;
+
+
+static void
+PrivOwrConfigurePower(
+    NvRmOwrController *pOwrInfo,
+    NvBool IsEnablePower);
+
+static NvError
+PrivOwrGetCaps(
+    NvRmDeviceHandle hDevice,
+    NvU32 Instance,
+    NvRmOwrCapability** pOwrSocCaps);
+
+
+static void
+PrivOwrConfigurePower(
+    NvRmOwrController *pOwrInfo,
+    NvBool IsEnablePower)
+{
+    NvRmModuleID ModuleId =
+            NVRM_MODULE_ID(pOwrInfo->ModuleId, pOwrInfo->Instance);
+
+    if (IsEnablePower == NV_TRUE)
+    {
+        NV_ASSERT_SUCCESS(NvRmPowerVoltageControl(
+                pOwrInfo->hRmDevice, 
+                ModuleId, 
+                pOwrInfo->OwrPowerClientId, 
+                NvRmVoltsUnspecified, 
+                NvRmVoltsUnspecified, 
+                NULL, 
+                0, 
+                NULL));
+
+            // Enable the clock to the OWR controller
+            NV_ASSERT_SUCCESS(NvRmPowerModuleClockControl(pOwrInfo->hRmDevice,
+                        ModuleId,
+                        pOwrInfo->OwrPowerClientId, 
+                        NV_TRUE));
+    }
+    else
+    {
+        // Disable the clock to the OWR controller
+        NV_ASSERT_SUCCESS(NvRmPowerModuleClockControl(pOwrInfo->hRmDevice, 
+                    ModuleId, 
+                    pOwrInfo->OwrPowerClientId, 
+                    NV_FALSE));
+        
+        //disable power
+        NV_ASSERT_SUCCESS(NvRmPowerVoltageControl(pOwrInfo->hRmDevice,
+                ModuleId,
+                pOwrInfo->OwrPowerClientId,
+                NvRmVoltsOff,
+                NvRmVoltsOff,
+                NULL,
+                0,
+                NULL));
+    }
+}
+
+static NvError
+PrivOwrGetCaps(
+    NvRmDeviceHandle hDevice,
+    NvU32 Instance,
+    NvRmOwrCapability** pOwrSocCaps)
+{
+    static NvRmOwrCapability s_OwrCap0;
+    NvError status = NvSuccess;
+    NvRmOwrCapability *pOwrCaps = NULL;
+    static NvRmModuleCapability s_OwrCaps[] = 
+        { {1, 0, 0, &s_OwrCap0 }
+        };
+    
+    s_OwrCap0.NoOfInstances = 1;
+    // Get the capability from modules files.
+    status = NvRmModuleGetCapabilities(hDevice, 
+                    NVRM_MODULE_ID(NvRmModuleID_OneWire, Instance),
+                    s_OwrCaps, 
+                    NV_ARRAY_SIZE(s_OwrCaps), (void **)&pOwrCaps);
+    if (status == NvSuccess)
+    {
+        *pOwrSocCaps = pOwrCaps;
+    }
+    return status;
+}
+
+NvError
+NvRmOwrOpen(
+    NvRmDeviceHandle hRmDevice,
+    NvU32 Instance,
+    NvRmOwrHandle *phOwr)
+{
+    NvError status = NvSuccess;
+    NvRmOwrController *pOwrInfo;
+    NvU32 PrefClockFreq = MAX_OWR_CLOCK_SPEED_KHZ;
+    NvRmModuleID ModuleId;
+    NvOdmIoModule IoModule = NvOdmIoModule_OneWire;
+    NvRmOwrCapability *OwrSocCaps = NULL;
+
+    NV_ASSERT(hRmDevice);
+    NV_ASSERT(phOwr);
+
+    /** If none of the controller is opened, allocate memory for all controllers
+     * in the system 
+     */
+    if (gs_OwrCont == NULL)
+    {
+        gs_OwrCont = gs_OwrControllers;
+    }
+    
+    /* Validate the Instance number passed */
+    if (IoModule == NvOdmIoModule_OneWire)
+    {
+        MaxOwrInstances =
+                NvRmModuleGetNumInstances(hRmDevice, NvRmModuleID_OneWire);
+        NV_ASSERT(Instance < MaxOwrInstances);
+        ModuleId = NvRmModuleID_OneWire;
+    }
+    else
+    {
+        NV_ASSERT(!"Invalid IO module");
+    }
+
+    status = PrivOwrGetCaps(hRmDevice, Instance, &OwrSocCaps);
+    if (status != NvSuccess)
+    {
+        return NvError_NotInitialized;
+    }
+    
+    pOwrInfo = &(gs_OwrCont[Instance]);
+
+    // Create the mutex for providing the thread safety for OWR API
+    if (pOwrInfo->NumberOfClientsOpened == 0)
+    {
+        status = NvOsMutexCreate(&(pOwrInfo->OwrThreadSafetyMutex));
+        if (status != NvSuccess)
+        {
+            pOwrInfo->OwrThreadSafetyMutex = NULL;
+            return status;
+        }
+    }
+
+    NvOsMutexLock(pOwrInfo->OwrThreadSafetyMutex);
+    // If no clients are opened yet, initialize the OWR controller
+    if (pOwrInfo->NumberOfClientsOpened == 0)
+    {
+        /* Polulate the controller structure */
+        pOwrInfo->hRmDevice = hRmDevice;
+        pOwrInfo->ModuleId = ModuleId;
+        pOwrInfo->Instance = Instance;
+        pOwrInfo->OwrPowerClientId = 0;
+
+        NV_ASSERT_SUCCESS(AP20RmOwrOpen(pOwrInfo));
+
+        /* Make sure that all the functions are populated by the HAL driver */
+        NV_ASSERT(pOwrInfo->read && pOwrInfo->write && pOwrInfo->close);
+
+        status = NvRmSetModuleTristate(pOwrInfo->hRmDevice, 
+            NVRM_MODULE_ID(pOwrInfo->ModuleId, pOwrInfo->Instance), NV_FALSE);
+        if (status != NvSuccess)
+        {
+            goto fail;
+        }
+
+        pOwrInfo->OwrPowerClientId = NVRM_POWER_CLIENT_TAG('O','W','R',' ');
+        status = 
+            NvRmPowerRegister(hRmDevice, NULL, &pOwrInfo->OwrPowerClientId);
+        if (status != NvSuccess)
+        {
+            goto fail;
+        }
+
+        /** Enable power rail, enable clock, configure clock to right freq,
+         * reset, disable clock, notify to disable power rail. 
+         *
+         *  All of this is done to just reset the controller.
+         */
+        PrivOwrConfigurePower(pOwrInfo, NV_TRUE);
+        status = NvRmPowerModuleClockConfig(hRmDevice, 
+                    NVRM_MODULE_ID(ModuleId, Instance), 
+                    pOwrInfo->OwrPowerClientId,
+                    PrefClockFreq, 
+                    NvRmFreqUnspecified, 
+                    &PrefClockFreq, 
+                    1, 
+                    NULL, 
+                    0);
+        if (status != NvSuccess)
+        {
+            PrivOwrConfigurePower(pOwrInfo, NV_FALSE);
+            goto fail;
+        }
+        NvRmModuleReset(hRmDevice, NVRM_MODULE_ID(ModuleId, Instance));
+        PrivOwrConfigurePower(pOwrInfo, NV_FALSE);
+    }
+    pOwrInfo->NumberOfClientsOpened++;
+    NvOsMutexUnlock(pOwrInfo->OwrThreadSafetyMutex);
+
+    /** We cannot return handle with a value of 0, as some clients check the
+     * handle to ne non-zero. So, to get around that we set MSB bit to 1.
+     */
+    *phOwr = (NvRmOwrHandle)(Instance | OWR_HANDLE_MSB_BIT);
+    return NvSuccess;
+
+fail:
+    if (pOwrInfo->OwrPowerClientId)
+    {
+        NvRmPowerUnRegister(hRmDevice, pOwrInfo->OwrPowerClientId);
+        pOwrInfo->OwrPowerClientId = 0;
+    }
+
+    (pOwrInfo->close)(pOwrInfo);
+    *phOwr = 0;
+
+    NvOsMutexUnlock(pOwrInfo->OwrThreadSafetyMutex);
+    NvOsMutexDestroy(pOwrInfo->OwrThreadSafetyMutex);
+
+    return status;
+}
+
+void NvRmOwrClose(NvRmOwrHandle hOwr)
+{
+    NvU32 Index;
+    NvRmOwrController *pOwrInfo;
+
+    if (hOwr == NULL)
+        return;
+
+    Index = ((NvU32) hOwr) & OWR_HANDLE_INSTANCE_MASK;
+    if (Index < MaxOwrInstances)
+    {
+        pOwrInfo = &(gs_OwrCont[Index]);
+
+        NvOsMutexLock(pOwrInfo->OwrThreadSafetyMutex);
+        pOwrInfo->NumberOfClientsOpened--;
+        if (pOwrInfo->NumberOfClientsOpened == 0)
+        {
+            /* Unregister the power client ID */
+            NvRmPowerUnRegister(pOwrInfo->hRmDevice,
+                                    pOwrInfo->OwrPowerClientId);
+            pOwrInfo->OwrPowerClientId = 0;
+
+            NV_ASSERT_SUCCESS( NvRmSetModuleTristate(pOwrInfo->hRmDevice,
+            NVRM_MODULE_ID(pOwrInfo->ModuleId, pOwrInfo->Instance), NV_TRUE ));
+
+            NV_ASSERT(pOwrInfo->close);
+            (pOwrInfo->close)(pOwrInfo);
+
+           /** FIXME: There is a race here. After the Mutex is unlocked someone
+            * can call NvRmOwrOpen and create the mutex, which will then be
+            * destroyed here.
+            */
+            NvOsMutexUnlock(pOwrInfo->OwrThreadSafetyMutex);
+            NvOsMutexDestroy(pOwrInfo->OwrThreadSafetyMutex);
+            pOwrInfo->OwrThreadSafetyMutex = NULL;
+        }
+        else 
+        {
+            NvOsMutexUnlock(pOwrInfo->OwrThreadSafetyMutex);
+        }
+    }
+}
+
+NvError NvRmOwrTransaction( 
+    NvRmOwrHandle hOwr,
+    NvU32 OwrPinMap,
+    NvU8 *Data,
+    NvU32 DataLength,
+    NvRmOwrTransactionInfo * Transaction,
+    NvU32 NumOfTransactions)
+{
+    NvU32 i;
+    NvRmOwrController* pOwrInfo;
+    NvU32 Index;
+    NvError status = NvSuccess;
+
+    Index = ((NvU32)hOwr) & OWR_HANDLE_INSTANCE_MASK;
+
+    NV_ASSERT(Index < MaxOwrInstances);
+    NV_ASSERT(Transaction);
+    NV_ASSERT(Data);
+
+    pOwrInfo = &(gs_OwrCont[Index]);
+
+    NvOsMutexLock(pOwrInfo->OwrThreadSafetyMutex);
+
+    PrivOwrConfigurePower(pOwrInfo, NV_TRUE);
+
+    for (i = 0; i < NumOfTransactions; i++)
+    {
+        if ((Transaction[i].Flags == NvRmOwr_MemWrite) ||
+            (Transaction[i].Flags == NvRmOwr_WriteByte) ||
+            (Transaction[i].Flags == NvRmOwr_WriteBit))
+        {
+            // OWR write transaction
+            status = (pOwrInfo->write)(
+                    pOwrInfo,
+                    Data,
+                    Transaction[i]);
+        }
+        else
+        {
+            // OWR read transaction
+            status = (pOwrInfo->read)(
+                    pOwrInfo,
+                    Data,
+                    Transaction[i]);
+        }
+        Data += Transaction[i].NumBytes;
+        if (status != NvSuccess)
+        {
+            break;
+        }
+    }
+
+    PrivOwrConfigurePower(pOwrInfo, NV_FALSE);
+
+    NvOsMutexUnlock(pOwrInfo->OwrThreadSafetyMutex);
+    return status;
+}
+
diff --git a/arch/arm/mach-tegra/nvrm/io/common/nvrm_owr_private.h b/arch/arm/mach-tegra/nvrm/io/common/nvrm_owr_private.h
new file mode 100644
index 000000000000..efeb0efb2144
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm/io/common/nvrm_owr_private.h
@@ -0,0 +1,244 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/** @file
+ *
+ * @b Description: Contains the OWR declarations.
+ */
+
+#ifndef INCLUDED_NVRM_OWR_PRIVATE_H
+#define INCLUDED_NVRM_OWR_PRIVATE_H
+
+#include "nvrm_module.h"
+#include "nvodm_query_pinmux.h"
+#include "nvrm_gpio.h"
+#include "nvrm_owr.h"
+
+/* Maximum number of OWR controller instances supported */
+#define MAX_OWR_INSTANCES     1
+
+#define MAX_OWR_CLOCK_SPEED_KHZ 1000
+
+#define OWR_NO_OF_BITS_PER_BYTE 8
+
+// ROM id size
+#define OWR_ROM_ID_SIZE_BYTES     8
+
+/* OWR ROM commands */
+#define OWR_ROM_READ_COMMAND    0x33
+#define OWR_ROM_SKIP_COMMAND     0xCC
+
+/* OWR MEM commands */
+#define OWR_MEM_READ_COMMAND    0xF0
+#define OWR_MEM_WRITE_COMMAND   0x0F
+
+/**
+ * @brief OWR interrupt status bits
+ */
+typedef enum
+{
+    // Presence Error Interrupt enable
+    OwrIntrStatus_PresenceErrIntEnable  = 0x1,
+
+    // CRC Error Interrupt enable
+    OwrIntrStatus_CrcErrIntEnable  = 0x2,
+
+    // Mem write Error Interrupt enable
+    OwrIntrStatus_MemWriteErrIntEnable  = 0x4,
+
+    // Error Command Interrupt enable
+    OwrIntrStatus_ErrCommandIntEnable  = 0x8,
+
+    // Reset done Interrupt enable
+    OwrIntrStatus_RstDoneIntEnable  = 0x10,
+
+    // Presence done Interrupt enable
+    OwrIntrStatus_PresenceDoneIntEnable  = 0x20,
+
+    // ROM Command done Interrupt enable
+    OwrIntrStatus_RomCmdDoneIntEnable  = 0x40,
+
+    // MEM Command done Interrupt enable
+    OwrIntrStatus_MemCmdDoneIntEnable  = 0x80,
+
+    // TXF overflow Interrupt enable
+    OwrIntrStatus_TxfOvfIntEnable  = 0x100,
+
+    // RXF underrun Interrupt enable
+    OwrIntrStatus_RxfUnrIntEnable  = 0x200,
+
+    // Dglitch Interrupt enable
+    OwrIntrStatus_DglitchIntEnable  = 0x400,
+
+    // TX FIFO Data Request Interrupt enable
+    OwrIntrStatus_TxFifoDataReqIntEnable  = 0x800,
+
+    // RX FIFO Data Request Interrupt enable
+    OwrIntrStatus_RxFifoDataReqIntEnable  = 0x1000,
+
+    // Bit transfer done Interrupt enable
+    OwrIntrStatus_BitTransferDoneIntEnable  = 0x2000,
+    
+    /** Force to 32 bit */
+    OwrIntrStatus_Force32 = 0x7FFFFFFF
+} OwrIntrStatus;
+
+/**
+ * @brief OWR interrupt status bits
+ */
+typedef enum
+{
+    // Ready bit
+    OwrStatus_Rdy = 0x0,
+
+    // Tx FIFO Full
+    OwrStatus_TxfFull = 0,
+        
+    // Tx FIFO Empty
+    OwrStatus_TxfEmpty = 0,
+
+    // RTx FIFO Full
+    OwrStatus_RxfFull = 0,
+
+    // Rx FIFO Empty
+    OwrStatus_RxfEmpty = 0,
+
+     // Tx Flush
+    OwrStatus_TxfFlush = 0,
+
+     // Rx Flush
+    OwrStatus_RxfFlush = 0,
+
+    // Rx Fifo Full Count
+    OwrStatus_RxFifoFullCnt = 0,
+
+    // Tx Fifo empty Count
+    OwrStatus_TxFifoEmptyCnt = 0,
+
+    // Reset
+    OwrStatus_Rpp = 0,
+
+    // Write bit 0
+    OwrStatus_Write0 = 0,
+
+    // Write bit 1
+    OwrStatus_Write1 = 0,
+
+    // Read bit
+    OwrStatus_Read = 0,
+
+    // Read Sampled bit
+    OwrStatus_ReadSampledBit = 0,
+
+    /** Force to 32 bit */
+    OwrStatus_Force32 = 0x7FFFFFFF
+} OwrStatus;
+
+typedef enum
+{
+    // Specifies a read transaction.
+    OWR_READ,
+    // Specifies a write transaction.
+    OWR_WRITE,
+} OwrTransactionType;
+
+struct NvRmOwrControllerRec;
+
+/* OWR controller state. There are will one instance of this structure for each
+ * OWR controller instance */
+typedef struct NvRmOwrControllerRec
+{
+    /* Controller static Information */
+
+    /* Rm device handle */
+    NvRmDeviceHandle hRmDevice;
+    
+    /* Contains the owrtransfer status */
+    NvU32 OwrTransferStatus;
+    
+    /* Contains the number of opened clients */
+    NvU32 NumberOfClientsOpened;
+    
+    /* Contains the semaphore id to block the synchronous owr client calls */
+    NvOsSemaphoreHandle OwrSyncSemaphore;
+    
+    /* Contains the mutex for providing the thread safety */
+    NvOsMutexHandle OwrThreadSafetyMutex;
+    
+    /* Power clinet ID */
+    NvU32 OwrPowerClientId;
+    
+    /* Contoller module ID. */
+    NvRmModuleID ModuleId;
+    
+    /* Instance of the above specified module */
+    NvU32 Instance;
+    
+    // OWR interrupt handle for this controller instance
+    NvOsInterruptHandle OwrInterruptHandle;
+ 
+    /* Read data */
+    NvError (*read)(struct NvRmOwrControllerRec *c, NvU8 * pBuffer, 
+               NvRmOwrTransactionInfo Transaction);
+    
+    /* Send data */
+    NvError (*write)(struct NvRmOwrControllerRec *c, NvU8 * pBuffer, 
+                NvRmOwrTransactionInfo Transaction);
+
+    /* Shutdown the controller */
+    void (*close)(struct NvRmOwrControllerRec *c);
+
+    //  OWR capabiity for this SOC only.
+    NvU32* pOwrVirtualAddress;
+    NvU32 OwrBankSize;
+    NvRmPhysAddr OwrPhysicalAddress;
+} NvRmOwrController;
+
+/** OWR SOC capability structure. */
+typedef struct SocOwrCapabilityRec
+{
+    NvU32 NoOfInstances;
+} NvRmOwrCapability;
+
+
+/**
+ * brief Initialze the controller to start the data transfer 
+ *
+ * This APIs should always return NvSuccess
+ *
+ * @param c    OWR controller structure.
+ * */
+NvError AP20RmOwrOpen(NvRmOwrController *c);
+
+#endif  // INCLUDED_NVRM_OWR_PRIVATE_H
+
+
diff --git a/arch/arm/mach-tegra/nvrm_user.c b/arch/arm/mach-tegra/nvrm_user.c
new file mode 100644
index 000000000000..0c69fb3ff8ca
--- /dev/null
+++ b/arch/arm/mach-tegra/nvrm_user.c
@@ -0,0 +1,25 @@
+/*
+ * arch/arm/mach-tegra/nvrm_user.c
+ *
+ * User-land access to NvRm APIs
+ *
+ * Copyright (c) 2008-2010, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#include <nvrm_init.h>
+
+NvRmDeviceHandle s_hRmGlobal;
diff --git a/arch/arm/mach-tegra/odm_kit/Kconfig b/arch/arm/mach-tegra/odm_kit/Kconfig
new file mode 100644
index 000000000000..dbf829f1b79e
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/Kconfig
@@ -0,0 +1,16 @@
+if MACH_TEGRA_GENERIC
+
+choice
+	prompt "Select ODM kit target board"
+
+config TEGRA_ODM_HARMONY
+	bool "NVIDIA Harmony development system"
+	depends on ARCH_TEGRA_2x_SOC
+
+config TEGRA_ODM_WHISTLER
+	bool "NVIDIA Whistler development system"
+	depends on ARCH_TEGRA_2x_SOC
+
+endchoice
+
+endif
diff --git a/arch/arm/mach-tegra/odm_kit/Makefile b/arch/arm/mach-tegra/odm_kit/Makefile
new file mode 100644
index 000000000000..a0f0c6670f71
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/Makefile
@@ -0,0 +1,3 @@
+obj-y += adaptations/
+obj-y += platform/
+obj-y += query/
diff --git a/arch/arm/mach-tegra/odm_kit/adaptations/Makefile b/arch/arm/mach-tegra/odm_kit/adaptations/Makefile
new file mode 100644
index 000000000000..9b0d46744489
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/adaptations/Makefile
@@ -0,0 +1,4 @@
+obj-y += gpio_ext/
+obj-y += tmon/
+obj-y += pmu/
+obj-y += misc/
diff --git a/arch/arm/mach-tegra/odm_kit/adaptations/gpio_ext/Makefile b/arch/arm/mach-tegra/odm_kit/adaptations/gpio_ext/Makefile
new file mode 100644
index 000000000000..8500f4a6779a
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/adaptations/gpio_ext/Makefile
@@ -0,0 +1,12 @@
+ccflags-y += -DNV_IS_AVP=0
+ccflags-y += -DNV_OAL=0
+ccflags-y += -DNV_USE_FUSE_CLOCK_ENABLE=0
+ifeq ($(CONFIG_MACH_TEGRA_GENERIC_DEBUG),y)
+ccflags-y += -DNV_DEBUG=1
+else
+ccflags-y += -DNV_DEBUG=0
+endif
+
+obj-y += gpio_ext_hal.o
+obj-y += gpio_ext_null.o
+obj-y += gpio_pcf50626.o
diff --git a/arch/arm/mach-tegra/odm_kit/adaptations/gpio_ext/gpio_ext_hal.c b/arch/arm/mach-tegra/odm_kit/adaptations/gpio_ext/gpio_ext_hal.c
new file mode 100644
index 000000000000..c53fad2da1cd
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/adaptations/gpio_ext/gpio_ext_hal.c
@@ -0,0 +1,92 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include "nvcommon.h"
+#include "nvodm_query_discovery.h"
+#include "nvodm_gpio_ext.h"
+#include "nvodm_services.h"
+#include "gpio_ext_hal.h"
+#include "gpio_ext_null.h"
+#include "gpio_pcf50626.h"
+
+void
+NvOdmExternalGpioWritePins(
+    NvU32 Port,
+    NvU32 Pin,
+    NvU32 PinValue)
+{
+    static NvBool IsInit = NV_FALSE;
+    static NvOdmGpioExtDevice GpioExtDevice;
+
+    if (!IsInit)
+    {
+        NvOdmOsMemset(&GpioExtDevice, 0, sizeof(GpioExtDevice));
+        if (NvOdmPeripheralGetGuid(NV_ODM_GUID('p','c','f','_','p','m','u','0')))
+        {
+            //  fill in HAL function here.
+            GpioExtDevice.pfnWritePins = GPIO_PCF50626_NvOdmExternalGpioWritePins;
+        }
+        else
+        {
+            // NULL implementation
+            GpioExtDevice.pfnWritePins = null_NvOdmExternalGpioWritePins;
+        }
+        IsInit = NV_TRUE;
+    }
+    GpioExtDevice.pfnWritePins(Port, Pin, PinValue);
+}
+
+NvU32
+NvOdmExternalGpioReadPins(
+    NvU32 Port,
+    NvU32 Pin)
+{
+    static NvBool IsInit = NV_FALSE;
+    static NvOdmGpioExtDevice GpioExtDevice;
+
+    if (!IsInit)
+    {
+        NvOdmOsMemset(&GpioExtDevice, 0, sizeof(GpioExtDevice));
+        if (NvOdmPeripheralGetGuid(NV_ODM_GUID('p','c','f','_','p','m','u','0')))
+        {
+            //  fill in HAL function here.
+            GpioExtDevice.pfnReadPins = GPIO_PCF50626_NvOdmExternalGpioReadPins;
+        }
+        else
+        {
+            // NULL implementation
+            GpioExtDevice.pfnReadPins = null_NvOdmExternalGpioReadPins;
+        }
+        IsInit = NV_TRUE;
+    }
+    return GpioExtDevice.pfnReadPins(Port, Pin);
+}
diff --git a/arch/arm/mach-tegra/odm_kit/adaptations/gpio_ext/gpio_ext_hal.h b/arch/arm/mach-tegra/odm_kit/adaptations/gpio_ext/gpio_ext_hal.h
new file mode 100644
index 000000000000..e1ca2c1182f9
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/adaptations/gpio_ext/gpio_ext_hal.h
@@ -0,0 +1,66 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/** 
+ * @file
+ * <b>NVIDIA Tegra ODM Kit:
+ *         Abstraction layer stub for external gpio
+ *         adaptation</b>
+ */
+
+#ifndef INCLUDED_NVODM_GPIO_EXT_ADAPTATION_HAL_H
+#define INCLUDED_NVODM_GPIO_EXT_ADAPTATION_HAL_H
+
+#include "nvodm_gpio_ext.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//  A simple HAL for the External GPIO adaptations.
+typedef void (*pfnExternalGpioWritePins)(NvU32, NvU32, NvU32);
+typedef NvU32 (*pfnExternalGpioReadPins)(NvU32, NvU32);
+
+typedef struct NvOdmGpioExtDeviceRec
+{
+    pfnExternalGpioWritePins    pfnWritePins;
+    pfnExternalGpioReadPins     pfnReadPins;
+
+} NvOdmGpioExtDevice;
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/arch/arm/mach-tegra/odm_kit/adaptations/gpio_ext/gpio_ext_null.c b/arch/arm/mach-tegra/odm_kit/adaptations/gpio_ext/gpio_ext_null.c
new file mode 100644
index 000000000000..4957b099484a
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/adaptations/gpio_ext/gpio_ext_null.c
@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include "nvodm_gpio_ext.h"
+#include "gpio_ext_null.h"
+
+void
+null_NvOdmExternalGpioWritePins(
+    NvU32 Port,
+    NvU32 Pin,
+    NvU32 PinValue)
+{
+    // NULL implementation that does nothing.
+    return;
+}
+
+NvU32
+null_NvOdmExternalGpioReadPins(
+    NvU32 Port,
+    NvU32 Pin)
+{
+    // NULL implementation that does nothing.
+    return 0;
+}
+
diff --git a/arch/arm/mach-tegra/odm_kit/adaptations/gpio_ext/gpio_ext_null.h b/arch/arm/mach-tegra/odm_kit/adaptations/gpio_ext/gpio_ext_null.h
new file mode 100644
index 000000000000..6e38bb31f121
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/adaptations/gpio_ext/gpio_ext_null.h
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_GPIO_EXT_NULL_H
+#define INCLUDED_GPIO_EXT_NULL_H
+
+#include "gpio_ext_hal.h"
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+void null_NvOdmExternalGpioWritePins(NvU32, NvU32, NvU32);
+NvU32 null_NvOdmExternalGpioReadPins(NvU32, NvU32);
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif
diff --git a/arch/arm/mach-tegra/odm_kit/adaptations/gpio_ext/gpio_pcf50626.c b/arch/arm/mach-tegra/odm_kit/adaptations/gpio_ext/gpio_pcf50626.c
new file mode 100644
index 000000000000..5f41b8aee053
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/adaptations/gpio_ext/gpio_pcf50626.c
@@ -0,0 +1,142 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include "nvodm_services.h"
+#include "nvassert.h"
+#include "nvodm_gpio_ext.h"
+#include "gpio_pcf50626.h"
+
+#if NV_DEBUG
+#define ASSERT_SUCCESS( expr ) \
+    do { \
+        NvBool b = (expr); \
+        NV_ASSERT( b == NV_TRUE ); \
+    } while( 0 )
+#else
+#define ASSERT_SUCCESS( expr ) \
+    do { \
+        (void)(expr); \
+    } while( 0 )
+#endif
+
+static NvOdmServicesI2cHandle s_hOdmI2c = NULL;
+
+#define PCF50626_I2C_SPEED_KHZ  400
+#define PCF50626_DEVICE_ADDR    0xE0
+#define PCF50626_GPO2C1_ADDR    0x55
+#define PCF50626_PWM1S_ADDR     0x2D
+#define PCF50626_PWM1D_ADDR     0x2E
+
+static NvBool GPIO_PCF50626_I2cWrite8(NvU8 Addr, NvU8 Data);
+
+void
+GPIO_PCF50626_NvOdmExternalGpioWritePins(
+    NvU32 Port,
+    NvU32 Pin,
+    NvU32 PinValue)
+{
+    NvU8 val;
+    NvBool RetVal = NV_TRUE;
+
+    switch (Port)
+    {
+    case NVODM_GPIO_EXT_PORT_2:
+        if (Pin != 1) // Only Pin 1 is implemented at this time
+            break;
+
+        if (PinValue) // Enable
+        {
+            val = (1UL << 6) // invert polarity
+                | 0x3;       // pwm1 output
+            RetVal = GPIO_PCF50626_I2cWrite8(PCF50626_GPO2C1_ADDR, val);
+        }
+        else // Disable
+        {
+            RetVal = GPIO_PCF50626_I2cWrite8(PCF50626_GPO2C1_ADDR, 0x0);
+        }
+        break;
+    }
+
+    if (RetVal == NV_FALSE)
+    {
+        NvOdmOsDebugPrintf("ERROR: GPIO_PCF50626_I2cWrite8() failed.\n");
+    }
+
+    return;
+}
+
+NvU32
+GPIO_PCF50626_NvOdmExternalGpioReadPins(
+    NvU32 Port,
+    NvU32 Pin)
+{
+    // Implement external GPIO port read routine here.
+    return 0;
+}
+
+static NvBool GPIO_PCF50626_I2cWrite8(
+    NvU8 Addr,
+    NvU8 Data)
+{
+    NvBool RetVal = NV_TRUE;
+    NvU8 WriteBuffer[2];
+    NvOdmI2cStatus status = NvOdmI2cStatus_Success;    
+    NvOdmI2cTransactionInfo TransactionInfo;
+    NvU32 DeviceAddr = (NvU32)PCF50626_DEVICE_ADDR;
+
+    s_hOdmI2c = NvOdmI2cOpen(NvOdmIoModule_I2c_Pmu, 0);
+    if (!s_hOdmI2c)
+    {
+        RetVal = NV_FALSE;
+        goto GPIO_PCF50626_I2cWrite8_exit;
+    }
+
+    WriteBuffer[0] = Addr & 0xFF;   // PMU offset
+    WriteBuffer[1] = Data & 0xFF;   // written data
+
+    TransactionInfo.Address = DeviceAddr;
+    TransactionInfo.Buf = WriteBuffer;
+    TransactionInfo.Flags = NVODM_I2C_IS_WRITE;
+    TransactionInfo.NumBytes = 2;
+
+    status = NvOdmI2cTransaction(s_hOdmI2c, &TransactionInfo, 1, 
+                        PCF50626_I2C_SPEED_KHZ, NV_WAIT_INFINITE);
+    if (status == NvOdmI2cStatus_Success)
+        RetVal = NV_TRUE;
+    else
+        RetVal = NV_FALSE;
+
+GPIO_PCF50626_I2cWrite8_exit:
+    NvOdmI2cClose(s_hOdmI2c);
+    s_hOdmI2c = NULL;
+    return RetVal;
+}
diff --git a/arch/arm/mach-tegra/odm_kit/adaptations/gpio_ext/gpio_pcf50626.h b/arch/arm/mach-tegra/odm_kit/adaptations/gpio_ext/gpio_pcf50626.h
new file mode 100644
index 000000000000..4f78bff05e3f
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/adaptations/gpio_ext/gpio_pcf50626.h
@@ -0,0 +1,58 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_GPIO_PCF50626_H
+#define INCLUDED_GPIO_PCF50626_H
+
+#include "gpio_ext_hal.h"
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+void
+GPIO_PCF50626_NvOdmExternalGpioWritePins(
+    NvU32 Port,
+    NvU32 Pin,
+    NvU32 PinValue);
+
+NvU32
+GPIO_PCF50626_NvOdmExternalGpioReadPins(
+    NvU32 Port,
+    NvU32 Pin);
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif
diff --git a/arch/arm/mach-tegra/odm_kit/adaptations/misc/Makefile b/arch/arm/mach-tegra/odm_kit/adaptations/misc/Makefile
new file mode 100644
index 000000000000..61c287105a48
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/adaptations/misc/Makefile
@@ -0,0 +1,2 @@
+obj-$(CONFIG_TEGRA_ODM_HARMONY)		+= harmony/
+obj-$(CONFIG_TEGRA_ODM_WHISTLER)	+= whistler/
diff --git a/arch/arm/mach-tegra/odm_kit/adaptations/misc/harmony/Makefile b/arch/arm/mach-tegra/odm_kit/adaptations/misc/harmony/Makefile
new file mode 100644
index 000000000000..12af02178d7f
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/adaptations/misc/harmony/Makefile
@@ -0,0 +1,14 @@
+ccflags-y += -DNV_IS_AVP=0
+ccflags-y += -DNV_OAL=0
+ccflags-y += -DNV_USE_FUSE_CLOCK_ENABLE=0
+ifeq ($(CONFIG_MACH_TEGRA_GENERIC_DEBUG),y)
+ccflags-y += -DNV_DEBUG=1
+else
+ccflags-y += -DNV_DEBUG=0
+endif
+
+obj-$(CONFIG_KEYBOARD_TEGRA)	+= nvodm_kbc.o
+obj-$(CONFIG_KEYBOARD_TEGRA)	+= nvodm_kbc_keymapping.o
+obj-y				+= nvodm_sdio.o
+obj-y				+= nvodm_uart.o
+obj-y				+= nvodm_usbulpi.o
diff --git a/arch/arm/mach-tegra/odm_kit/adaptations/misc/harmony/nvodm_kbc.c b/arch/arm/mach-tegra/odm_kit/adaptations/misc/harmony/nvodm_kbc.c
new file mode 100644
index 000000000000..3f07a61a66c4
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/adaptations/misc/harmony/nvodm_kbc.c
@@ -0,0 +1,70 @@
+/*
+ * Copyright (c) 2008-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+ 
+/**
+ * @file          Nvodm_Kbc.c
+ * @brief         <b>KBC odm implementation</b>
+ *
+ * @Description : Implementation of the odm KBC API
+ */
+#include "nvodm_kbc.h"
+#include "../../../query/harmony/nvodm_query_kbc_qwerty_def.h"
+
+NvU32
+NvOdmKbcFilterKeys(
+    NvU32 *pRows,
+    NvU32 *pCols,
+    NvU32 NumOfKeysPressed)
+{
+    NvBool IsFunctionKeyFound = NV_FALSE;
+    NvU32 KeyIndex;
+    
+    for (KeyIndex = 0; KeyIndex < NumOfKeysPressed; ++KeyIndex)
+    {
+        if ((pRows[KeyIndex] == KBC_QWERTY_FUNCTION_KEY_ROW_NUMBER) &&
+                (pCols[KeyIndex] == KBC_QWERTY_FUNCTION_KEY_COLUMN_NUMBER))
+        {
+            IsFunctionKeyFound = NV_TRUE;
+            break;
+        }
+    }
+    if (!IsFunctionKeyFound)
+        return NumOfKeysPressed;
+
+    // Add function row base to treat as special case
+    for (KeyIndex = 0; KeyIndex < NumOfKeysPressed; ++KeyIndex)
+        pRows[KeyIndex] += KBC_QWERTY_FUNCTION_KEY_ROW_BASE;
+        
+    return NumOfKeysPressed;
+}
+
+
diff --git a/arch/arm/mach-tegra/odm_kit/adaptations/misc/harmony/nvodm_kbc_keymapping.c b/arch/arm/mach-tegra/odm_kit/adaptations/misc/harmony/nvodm_kbc_keymapping.c
new file mode 100644
index 000000000000..1b316bc511e8
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/adaptations/misc/harmony/nvodm_kbc_keymapping.c
@@ -0,0 +1,184 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/**
+ * @file
+ * <b>NVIDIA Tegra ODM Kit:
+ *         Keyboard Controller virtual key mapping</b>
+ *
+ * @b Description: Implement the ODM keyboard mapping to the platform
+ *                  specific.
+ */
+#include "nvodm_kbc_keymapping.h"
+#include <linux/input.h>
+
+
+#define KBC_QWERTY_NORMAL_KEY_CODE_BASE          0x1000
+#define KBC_QWERTY_FUNCTION_KEY_CODE_BASE        0x2000
+
+#define KBC_QWERTY_FUNCTION_KEY_ROW_BASE         0x100
+#define KBC_QWERTY_FUNCTION_KEY_ROW_NUMBER       0
+#define KBC_QWERTY_FUNCTION_KEY_COLUMN_NUMBER    7
+
+/**
+ * @brief Scan Code to Virtual Key mappings.
+ */
+
+
+/* The total number of soc scan codes will be (first - last) */
+#define NV_SOC_NORMAL_KEY_SCAN_CODE_TABLE_FIRST      KBC_QWERTY_NORMAL_KEY_CODE_BASE
+#define NV_SOC_NORMAL_KEY_SCAN_CODE_TABLE_LAST       (KBC_QWERTY_NORMAL_KEY_CODE_BASE +0x7F)
+
+#define NV_SOC_FUNCTION_KEY_SCAN_CODE_TABLE_FIRST    KBC_QWERTY_FUNCTION_KEY_CODE_BASE
+#define NV_SOC_FUNCTION_KEY_SCAN_CODE_TABLE_LAST     (KBC_QWERTY_FUNCTION_KEY_CODE_BASE +0x7F)
+
+/**
+ * @brief This is the actual Scan-code-to-VKey mapping table. For new layouts
+ *        this is the only structure which needs to be modified to return the
+ *        proper vkey depending on the scan code.
+ */
+
+#define KEY_UNUSED 0
+
+static NvU32 ScanCodeToVKeyTableKbcQwertyNormal[] =
+{
+    // Row 0-> Unused, Unused, 'W',     'S',    'A',     'Z',       Unused, Function,
+    // Row 1 ->Unused, Unused, Unused,  Unused, Unused,  unused,     Unused, WIN_SPECIAL
+    // Row 2 ->Unused, Unused, Unused,  Unused, Unused,  unused,     Alt,    Alt2
+    // Row 3 ->'5',    '4',    'R',     'E',    'F',     'D',        'X',    Unused,
+    // Row 4 ->'7',    '6',    'T',     'H',    'G',     'V',        'C',    SPACEBAR,
+    // Row 5 ->'9',    '8',    'U',     'Y',    'J',     'N',        'B',    '|\',
+    // Row 6 ->Minus,  '0',    'O',     'I',    'L',     'K',        '<',    M,
+    // Row 7 ->unused, '+',    '}]',    '#',    Unused,  Unused,     Unused, WinSpecial,
+    // Row 8 ->Unused, Unused, Unused,  Unused, SHIFT,   SHIFT,      UnUsed, Unused ,
+    // Row 9 ->Unused, Unused, Unused,  Unused, unused,  Ctrl,       UnUsed, Control,
+    // Row A ->Unused, Unused, Unused,  Unused, unused,  unused,     UnUsed, Unused,
+    // Row B ->'{[',   'P',    '"',     ':;',   '/?,      '>',       UnUsed, Unused,
+    // Row C ->'F10',  'F9',   'BckSpc','3',    '2',     'Up,        Prntscr,Pause
+    // Row D ->INS,    DEL,    Unused,  Pgup,   PgDn,    right,      Down,   Left,
+    // Row E ->F11,    F12,    F8,      'Q',    F4,      F3,         '1',    F7,
+    // Row F ->ESC,    '~',     F5,      TAB,    F1,      F2,         CAPLOCK,F6,
+       KEY_UNUSED,     KEY_UNUSED,     KEY_W,           KEY_S,
+                KEY_A,         KEY_Z,         KEY_UNUSED,    KEY_FN,
+       KEY_UNUSED,       KEY_UNUSED,     KEY_UNUSED,      KEY_UNUSED,
+                KEY_UNUSED,    KEY_UNUSED,    KEY_UNUSED,    KEY_MENU,
+       KEY_UNUSED,     KEY_UNUSED,     KEY_UNUSED,      KEY_UNUSED,
+                KEY_UNUSED,    KEY_UNUSED,    KEY_LEFTALT,     KEY_RIGHTALT,
+       KEY_5,          KEY_4,          KEY_R,           KEY_E,         
+                KEY_F,         KEY_D,         KEY_X,         KEY_UNUSED,
+       KEY_7,          KEY_6,          KEY_T,           KEY_H,         
+                KEY_G,         KEY_V,         KEY_C,         KEY_SPACE,
+       KEY_9,          KEY_8,          KEY_U,           KEY_Y,         
+                KEY_J,         KEY_N,         KEY_B,         KEY_BACKSLASH,
+       KEY_MINUS,      KEY_0,          KEY_O,           KEY_I,         
+                KEY_L,         KEY_K,         KEY_COMMA,     KEY_M,
+       KEY_UNUSED,     KEY_EQUAL,      KEY_RIGHTBRACE,    KEY_ENTER,     
+                KEY_UNUSED,    KEY_UNUSED,     KEY_UNUSED,     KEY_MENU,
+       KEY_UNUSED,     KEY_UNUSED,     KEY_UNUSED,     KEY_UNUSED,     
+                KEY_LEFTSHIFT,     KEY_RIGHTSHIFT,     KEY_UNUSED,     KEY_UNUSED,
+       KEY_UNUSED,     KEY_UNUSED,     KEY_UNUSED,     KEY_UNUSED,     
+                KEY_UNUSED,     KEY_LEFTCTRL,    KEY_UNUSED,     KEY_RIGHTCTRL,
+       KEY_UNUSED,     KEY_UNUSED,     KEY_UNUSED,     KEY_UNUSED,     
+                KEY_UNUSED,     KEY_UNUSED,     KEY_UNUSED,     KEY_UNUSED,
+       KEY_LEFTBRACE,  KEY_P,          KEY_APOSTROPHE,    KEY_SEMICOLON,    
+                KEY_SLASH,    KEY_DOT,    KEY_UNUSED,   KEY_UNUSED,
+       KEY_F10,        KEY_F9,         KEY_BACKSPACE,       KEY_3,      
+                KEY_2,           KEY_UP,         KEY_PRINT,   KEY_PAUSE,
+       KEY_INSERT,     KEY_DELETE,     KEY_UNUSED,     KEY_PAGEUP,      
+                KEY_PAGEDOWN,       KEY_RIGHT,      KEY_DOWN,       KEY_LEFT,
+       KEY_F11,        KEY_F12,        KEY_F8,         KEY_Q,           
+                KEY_F4,         KEY_F3,         KEY_1,           KEY_F7,
+       KEY_ESC,        KEY_GRAVE,      KEY_F5,         KEY_TAB,         
+                KEY_F1,         KEY_F2,          KEY_CAPSLOCK ,    KEY_F6
+};
+
+static NvU32 ScanCodeToVKeyTableKbcQwertyFunction[] =
+{
+    // Row 0-> Unused, Unused, 'W',     'S',    'A',     'Z',       Unused, Function,
+    // Row 1 ->WINSPECIAL, Unused, Unused,  Unused, Unused,  unused,     Unused, Win_special
+    // Row 2 ->Unused, Unused, Unused,  Unused, Unused,  unused,     Alt,    Alt2
+    // Row 3 ->'5',    '4',    'R',     'E',    'F',     'D',        'X',    Unused,
+    // Row 4 ->'7',    '6',    'T',     'H',    'G',     'V',        'C',    SPACEBAR,
+    // Row 5 ->'9',    '8',    'U',     'Y',    'J',     'N',        'B',    '|\',
+    // Row 6 ->Minus,  '0',    'O',     'I',    'L',     'K',        '<',    M,
+    // Row 7 ->unused, '+',    '}]',    '#',    Unused,  Unused,     Unused, WinSpecial,
+    // Row 8 ->Unused, Unused, Unused,  Unused, SHIFT,   SHIFT,      UnUsed, Unused ,
+    // Row 9 ->Unused, Unused, Unused,  Unused, unused,  Ctrl,       UnUsed, Control,
+    // Row A ->Unused, Unused, Unused,  Unused, unused,  unused,     UnUsed, Unused,
+    // Row B ->'{[',   'P',    '"',     ':;',   '/?,      '>',       UnUsed, Unused,
+    // Row C ->'F10',  'F9',   'BckSpc','3',    '2',     'Up,        Prntscr,Pause
+    // Row D ->INS,    DEL,    Unused,  Pgup,   PgDn,    right,      Down,   Left,
+    // Row E ->F11,    F12,    F8,      'Q',    F4,      F3,         '1',    F7,
+    // Row F ->ESC,    '~',     F5,      TAB,    F1,      F2,         CAPLOCK,F6,
+
+    KEY_UNUSED,  KEY_UNUSED,  KEY_UNUSED,  KEY_UNUSED,  KEY_UNUSED,  KEY_UNUSED,  KEY_UNUSED,  KEY_UNUSED,
+    KEY_UNUSED,  KEY_UNUSED,  KEY_UNUSED,  KEY_UNUSED,  KEY_UNUSED,  KEY_UNUSED,  KEY_UNUSED,  KEY_UNUSED,
+    KEY_UNUSED,  KEY_UNUSED,  KEY_UNUSED,  KEY_UNUSED,  KEY_UNUSED,  KEY_UNUSED,  KEY_UNUSED,  KEY_UNUSED,
+    KEY_UNUSED,  KEY_UNUSED,  KEY_UNUSED,  KEY_UNUSED,  KEY_UNUSED,  KEY_UNUSED,  KEY_UNUSED,  KEY_UNUSED,
+    KEY_7,       KEY_UNUSED,  KEY_UNUSED,  KEY_UNUSED,  KEY_UNUSED,  KEY_UNUSED,  KEY_UNUSED,  KEY_UNUSED,
+    KEY_9,       KEY_8,       KEY_4,       KEY_UNUSED,  KEY_1,       KEY_UNUSED,  KEY_UNUSED,  KEY_UNUSED,
+    KEY_UNUSED,  KEY_SLASH,   KEY_6,       KEY_5,       KEY_3,       KEY_2,       KEY_UNUSED,  KEY_0,
+    KEY_UNUSED,  KEY_UNUSED,  KEY_UNUSED,  KEY_UNUSED,  KEY_UNUSED,  KEY_UNUSED,  KEY_UNUSED,  KEY_UNUSED,
+    KEY_UNUSED,  KEY_UNUSED,  KEY_UNUSED,  KEY_UNUSED,  KEY_UNUSED,  KEY_UNUSED,  KEY_UNUSED,  KEY_UNUSED,
+    KEY_UNUSED,  KEY_UNUSED,  KEY_UNUSED,  KEY_UNUSED,  KEY_UNUSED,  KEY_UNUSED,  KEY_UNUSED,  KEY_UNUSED,
+    KEY_UNUSED,  KEY_UNUSED,  KEY_UNUSED,  KEY_UNUSED,  KEY_UNUSED,  KEY_UNUSED,  KEY_UNUSED,  KEY_UNUSED,
+    KEY_UNUSED,  KEY_KPASTERISK,  KEY_UNUSED,  KEY_KPMINUS,  KEY_KPPLUS,  KEY_DOT,  KEY_UNUSED,  KEY_UNUSED,
+    KEY_UNUSED,  KEY_UNUSED,  KEY_UNUSED,  KEY_UNUSED,  KEY_UNUSED,  KEY_VOLUMEUP,  KEY_UNUSED,  KEY_UNUSED,
+    KEY_UNUSED,  KEY_UNUSED,  KEY_UNUSED,  KEY_HOME,    KEY_END,     KEY_BRIGHTNESSUP,  KEY_VOLUMEDOWN,  KEY_BRIGHTNESSDOWN,
+    KEY_NUMLOCK, KEY_SCROLLLOCK,  KEY_MUTE,KEY_UNUSED,  KEY_UNUSED,  KEY_UNUSED,  KEY_UNUSED,  KEY_UNUSED,
+    KEY_UNUSED,  KEY_UNUSED,  KEY_UNUSED,  KEY_UNUSED,  KEY_QUESTION,KEY_UNUSED,  KEY_UNUSED,  KEY_UNUSED
+};
+static struct NvOdmKeyVirtTableDetail s_ScvkQwertyNormalEngUS =
+{
+    NV_SOC_NORMAL_KEY_SCAN_CODE_TABLE_FIRST,    // scan code start
+    NV_SOC_NORMAL_KEY_SCAN_CODE_TABLE_LAST,     // scan code end
+    ScanCodeToVKeyTableKbcQwertyNormal          // Normal Qwerty keyboard
+};
+
+static struct NvOdmKeyVirtTableDetail s_ScvkQwertyFunctionEngUS =
+{
+    NV_SOC_FUNCTION_KEY_SCAN_CODE_TABLE_FIRST,      // scan code start
+    NV_SOC_FUNCTION_KEY_SCAN_CODE_TABLE_LAST,       // scan code end
+    ScanCodeToVKeyTableKbcQwertyFunction            // Function Qwerty keyboard
+};
+
+static const struct NvOdmKeyVirtTableDetail *s_pVirtualKeyTables[] =
+     {&s_ScvkQwertyNormalEngUS, &s_ScvkQwertyFunctionEngUS};
+
+
+NvU32
+NvOdmKbcKeyMappingGetVirtualKeyMappingList(
+    const struct NvOdmKeyVirtTableDetail ***pVirtKeyTableList)
+{
+   *pVirtKeyTableList = s_pVirtualKeyTables;
+   return NV_ARRAY_SIZE(s_pVirtualKeyTables);
+}
diff --git a/arch/arm/mach-tegra/odm_kit/adaptations/misc/harmony/nvodm_sdio.c b/arch/arm/mach-tegra/odm_kit/adaptations/misc/harmony/nvodm_sdio.c
new file mode 100644
index 000000000000..946f4ab9ecc4
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/adaptations/misc/harmony/nvodm_sdio.c
@@ -0,0 +1,326 @@
+/*
+ * Copyright (c) 2008-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+ 
+/**
+ * @file          Nvodm_Sdio.c
+ * @brief         <b>Sdio odm implementation</b>
+ *
+ * @Description : Implementation of the odm sdio API
+ */
+#include "nvodm_sdio.h"
+#include "nvodm_services.h"
+#include "nvodm_query_discovery.h"
+#include "nvodm_services.h"
+#include "nvodm_pmu.h"
+#include "nvos.h"
+
+#ifdef NV_DRIVER_DEBUG
+    #define NV_DRIVER_TRACE(x) NvOdmOsDebugPrintf x
+#else
+    #define NV_DRIVER_TRACE(x)
+#endif
+
+#define WLAN_GUID   NV_ODM_GUID('s','d','i','o','w','l','a','n')
+
+typedef struct NvOdmSdioRec
+{
+    // NvODM PMU device handle
+    NvOdmServicesPmuHandle hPmu;
+    // Gpio Handle
+    NvOdmServicesGpioHandle hGpio;
+    // Pin handle to Wlan Reset Gpio pin
+    NvOdmGpioPinHandle hResetPin;
+    // Pin handle to Wlan PWR GPIO Pin
+    NvOdmGpioPinHandle hPwrPin;
+    NvOdmPeripheralConnectivity *pConnectivity;
+    // Power state
+    NvBool PoweredOn;
+    // Instance
+    NvU32 Instance;
+} NvOdmSdio;
+
+
+
+static void NvOdmSetPowerOnSdio(NvOdmSdioHandle pDevice, NvBool IsEnable);
+static NvBool SdioOdmWlanSetPowerOn(NvOdmSdioHandle hOdmSdio, NvBool IsEnable);
+
+
+static NvBool SdioOdmWlanSetPowerOn(NvOdmSdioHandle hOdmSdio, NvBool IsEnable)
+{
+    if (IsEnable) 
+    {
+        // Wlan Power On Reset Sequence
+        NvOdmGpioSetState(hOdmSdio->hGpio, hOdmSdio->hPwrPin, 0x0);      //PWD -> Low
+        NvOdmGpioSetState(hOdmSdio->hGpio, hOdmSdio->hResetPin, 0x0);    //RST -> Low
+        NvOdmOsWaitUS(2000);
+        NvOdmGpioSetState(hOdmSdio->hGpio, hOdmSdio->hPwrPin, 0x1);      //PWD -> High
+        NvOdmGpioSetState(hOdmSdio->hGpio, hOdmSdio->hResetPin, 0x1);    //RST -> High      
+     }
+     else 
+     {
+         // Power Off sequence
+         NvOdmGpioSetState(hOdmSdio->hGpio, hOdmSdio->hPwrPin, 0x0);     //PWD -> Low
+     }
+
+    return NV_TRUE;
+}
+
+NvOdmSdioHandle NvOdmSdioOpen(NvU32 Instance)
+{
+    static NvOdmSdio *pDevice = NULL;
+    NvOdmServicesGpioHandle hGpioTemp = NULL;
+    NvOdmPeripheralConnectivity *pConnectivity;
+    NvU32 NumOfGuids = 1;
+    NvU64 guid;
+    NvU32 searchVals[2];
+    const NvU32 *pOdmConfigs;
+    NvU32 NumOdmConfigs;
+    NvBool Status = NV_TRUE;
+    const NvOdmPeripheralSearch searchAttrs[] =
+    {
+        NvOdmPeripheralSearch_IoModule,
+        NvOdmPeripheralSearch_Instance,
+    };
+    
+    searchVals[0] =  NvOdmIoModule_Sdio;
+    searchVals[1] =  Instance;
+
+    NvOdmQueryPinMux(NvOdmIoModule_Sdio, &pOdmConfigs, &NumOdmConfigs); 
+    if (Instance >= NumOdmConfigs )
+        return NULL;
+    if( pOdmConfigs[Instance] == 0 )
+        return NULL;
+
+    NumOfGuids = NvOdmPeripheralEnumerate(
+                                                    searchAttrs,
+                                                    searchVals,
+                                                    2,
+                                                    &guid,
+                                                    NumOfGuids);
+
+
+    // Get the peripheral connectivity information
+    pConnectivity = (NvOdmPeripheralConnectivity *)NvOdmPeripheralGetGuid(guid);
+    if (pConnectivity == NULL)
+        return NULL;
+
+    pDevice = NvOdmOsAlloc(sizeof(NvOdmSdio));
+    pDevice->hPmu = NULL;
+    if(pDevice == NULL)
+        return (pDevice);
+
+    if (pDevice->hPmu == NULL)
+    {
+        pDevice->hPmu = NvOdmServicesPmuOpen();
+        if(pDevice->hPmu == NULL)
+        {
+            NvOdmOsFree(pDevice);
+            pDevice = NULL;
+            return (NULL);
+        }
+    }
+
+    pDevice->pConnectivity = pConnectivity;
+    NvOdmSetPowerOnSdio(pDevice, NV_TRUE);
+
+    if (pConnectivity->Guid == WLAN_GUID)
+    {
+        // Getting the OdmGpio Handle
+        hGpioTemp = NvOdmGpioOpen();
+        if (hGpioTemp == NULL)
+        {
+            NvOdmOsFree(pDevice);
+            pDevice = NULL;
+            return (pDevice);
+        }
+    
+        // Search for the Vdd rail and set the proper volage to the rail.
+        if (pConnectivity->AddressList[1].Interface == NvOdmIoModule_Gpio)
+        {
+             // Acquiring Pin Handles for Power Pin
+             pDevice->hPwrPin= NvOdmGpioAcquirePinHandle(hGpioTemp, 
+                   pConnectivity->AddressList[1].Instance,
+                   pConnectivity->AddressList[1].Address);
+        }
+         
+        if (pConnectivity->AddressList[2].Interface == NvOdmIoModule_Gpio)
+        {
+             // Acquiring Pin Handles for Reset Pin
+             pDevice->hResetPin= NvOdmGpioAcquirePinHandle(hGpioTemp, 
+                   pConnectivity->AddressList[2].Instance,
+                   pConnectivity->AddressList[2].Address);
+        }
+
+        // Setting the ON/OFF pin to output mode.
+        NvOdmGpioConfig(hGpioTemp, pDevice->hPwrPin, NvOdmGpioPinMode_Output);
+        NvOdmGpioConfig(hGpioTemp, pDevice->hResetPin, NvOdmGpioPinMode_Output);
+
+        // Setting the Output Pin to Low
+        NvOdmGpioSetState(hGpioTemp, pDevice->hPwrPin, 0x0);
+        NvOdmGpioSetState(hGpioTemp, pDevice->hResetPin, 0x0);
+
+        pDevice->hGpio = hGpioTemp;
+
+        Status = SdioOdmWlanSetPowerOn(pDevice, NV_TRUE);
+        if (Status != NV_TRUE)
+        {
+            NvOdmOsFree(pDevice);
+            pDevice = NULL;
+            return (pDevice);
+        }
+    }
+    pDevice->PoweredOn = NV_TRUE;
+    pDevice->Instance = Instance;
+    NV_DRIVER_TRACE(("Open SDIO%d", Instance));
+    return pDevice;
+}
+
+void NvOdmSdioClose(NvOdmSdioHandle hOdmSdio)
+{
+    const NvOdmPeripheralConnectivity *pConnectivity = NULL;
+
+    NV_DRIVER_TRACE(("Close SDIO%d", hOdmSdio->Instance));
+
+    pConnectivity = hOdmSdio->pConnectivity;
+    if (pConnectivity->Guid == WLAN_GUID)
+    {
+        // Call Turn off power when close is Called
+        (void)SdioOdmWlanSetPowerOn(hOdmSdio, NV_FALSE);
+
+        NvOdmGpioReleasePinHandle(hOdmSdio->hGpio, hOdmSdio->hPwrPin);
+        NvOdmGpioReleasePinHandle(hOdmSdio->hGpio, hOdmSdio->hResetPin);    
+        NvOdmGpioClose(hOdmSdio->hGpio);
+    }
+    NvOdmSetPowerOnSdio(hOdmSdio, NV_FALSE);
+    if (hOdmSdio->hPmu != NULL)
+    {
+         NvOdmServicesPmuClose(hOdmSdio->hPmu);
+    }
+    NvOdmOsFree(hOdmSdio);
+    hOdmSdio = NULL;
+}
+
+static void NvOdmSetPowerOnSdio(NvOdmSdioHandle pDevice,
+                                                                NvBool IsEnable)
+{
+    NvU32 Index = 0;
+    NvOdmServicesPmuVddRailCapabilities RailCaps;
+    NvU32 SettlingTime = 0;
+    const NvOdmPeripheralConnectivity *pConnectivity;
+
+    pConnectivity = pDevice->pConnectivity;
+    if (IsEnable) // Turn on Power
+    {
+        // Search for the Vdd rail and set the proper volage to the rail.
+        for (Index = 0; Index < pConnectivity->NumAddress; ++Index)
+        {
+            if (pConnectivity->AddressList[Index].Interface == NvOdmIoModule_Vdd)
+            {
+                NvOdmServicesPmuGetCapabilities(pDevice->hPmu, pConnectivity->AddressList[Index].Address, &RailCaps);
+                NvOdmServicesPmuSetVoltage(pDevice->hPmu, pConnectivity->AddressList[Index].Address,
+                                RailCaps.requestMilliVolts, &SettlingTime);
+                if (SettlingTime)
+                {
+                    NvOdmOsWaitUS(SettlingTime);
+                }
+            }
+        }
+    }
+    else // Shutdown Power
+    {
+        // Search for the Vdd rail and power Off the module
+        for (Index = 0; Index < pConnectivity->NumAddress; ++Index)
+        {
+            if (pConnectivity->AddressList[Index].Interface == NvOdmIoModule_Vdd)
+            {
+                NvOdmServicesPmuGetCapabilities(pDevice->hPmu, pConnectivity->AddressList[Index].Address, &RailCaps);
+                NvOdmServicesPmuSetVoltage(pDevice->hPmu, pConnectivity->AddressList[Index].Address,
+                                ODM_VOLTAGE_OFF, &SettlingTime);
+                if (SettlingTime)
+                {
+                    NvOdmOsWaitUS(SettlingTime);
+                }
+            }
+        }
+    }
+}
+
+NvBool NvOdmSdioSuspend(NvOdmSdioHandle hOdmSdio)
+{
+
+    const NvOdmPeripheralConnectivity *pConnectivity = NULL;
+    NvBool Status = NV_TRUE;
+
+    if (!hOdmSdio->PoweredOn)
+    {
+        NV_DRIVER_TRACE(("SDIO%d already suspended", hOdmSdio->Instance));
+        return NV_TRUE;
+    }
+
+    NV_DRIVER_TRACE(("Suspend SDIO%d", hOdmSdio->Instance));
+    NvOdmSetPowerOnSdio(hOdmSdio, NV_FALSE);
+
+    pConnectivity = hOdmSdio->pConnectivity;
+    if (pConnectivity->Guid == WLAN_GUID)
+    {
+        // Turn off power
+        Status = SdioOdmWlanSetPowerOn(hOdmSdio, NV_FALSE);
+
+    }
+    hOdmSdio->PoweredOn = NV_FALSE;
+    return Status;
+
+}
+
+NvBool NvOdmSdioResume(NvOdmSdioHandle hOdmSdio)
+{
+    const NvOdmPeripheralConnectivity *pConnectivity = NULL;
+    NvBool Status = NV_TRUE;
+
+    if (hOdmSdio->PoweredOn)
+    {
+        NV_DRIVER_TRACE(("SDIO%d already resumed", hOdmSdio->Instance));
+        return NV_TRUE;
+    }
+
+    NvOdmSetPowerOnSdio(hOdmSdio, NV_TRUE);
+
+    pConnectivity = hOdmSdio->pConnectivity;
+    if (pConnectivity->Guid == WLAN_GUID)
+    {
+        // Turn on power
+        Status = SdioOdmWlanSetPowerOn(hOdmSdio, NV_TRUE);
+    }
+    NV_DRIVER_TRACE(("Resume SDIO%d", hOdmSdio->Instance));
+    hOdmSdio->PoweredOn = NV_TRUE;
+    return Status;
+}
diff --git a/arch/arm/mach-tegra/odm_kit/adaptations/misc/harmony/nvodm_uart.c b/arch/arm/mach-tegra/odm_kit/adaptations/misc/harmony/nvodm_uart.c
new file mode 100644
index 000000000000..a3f09ad89c18
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/adaptations/misc/harmony/nvodm_uart.c
@@ -0,0 +1,138 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+ 
+/**
+ * @file          nvodm_uart.c
+ * @brief         <b>Adaptation for uart </b>
+ *
+ * @Description : Implementation of the uart adaptation.
+ */
+#include "nvodm_uart.h"
+#include "nvodm_services.h"
+#include "nvodm_query_discovery.h"
+#include "nvodm_services.h"
+#include "nvos.h"
+#include "nvodm_pmu.h"
+
+#ifdef NV_DRIVER_DEBUG
+    #define NV_DRIVER_TRACE NvOsDebugPrintf
+#else
+    #define NV_DRIVER_TRACE (void)
+#endif
+
+typedef struct NvOdmUartRec
+{
+    // NvODM PMU device handle
+    NvOdmServicesPmuHandle hPmu;
+    // Gpio Handle
+    NvOdmServicesGpioHandle hGpio;    
+    // Pin handle to Bluetooth Reset Gpio pin
+    NvOdmGpioPinHandle hResetPin;
+    NvOdmPeripheralConnectivity *pConnectivity;
+} NvOdmUart;
+
+NvOdmUartHandle NvOdmUartOpen(NvU32 Instance)
+{
+    NvOdmUart *pDevice = NULL;
+    NvOdmPeripheralConnectivity *pConnectivity;
+    NvU32 NumOfGuids = 1;
+    NvU64 guid;
+    NvU32 searchVals[2];
+    const NvOdmPeripheralSearch searchAttrs[] =
+    {
+        NvOdmPeripheralSearch_IoModule,
+        NvOdmPeripheralSearch_Instance,
+    };
+    
+    searchVals[0] =  NvOdmIoModule_Uart;
+    searchVals[1] =  Instance;
+
+    NumOfGuids = NvOdmPeripheralEnumerate(
+                                                    searchAttrs,
+                                                    searchVals,
+                                                    2,
+                                                    &guid,
+                                                    NumOfGuids); 
+
+    pConnectivity = (NvOdmPeripheralConnectivity *)NvOdmPeripheralGetGuid(guid);
+    if (pConnectivity == NULL)
+        goto ExitUartOdm;
+    
+    pDevice = NvOdmOsAlloc(sizeof(NvOdmUart));
+    if(pDevice == NULL)
+        goto ExitUartOdm;
+    
+    pDevice->hPmu = NvOdmServicesPmuOpen();
+    if(pDevice->hPmu == NULL)
+    {
+        goto ExitUartOdm;
+    }
+
+    // Switch On UART Interface
+
+    pDevice->pConnectivity = pConnectivity;
+   
+    return pDevice;
+
+ExitUartOdm:
+    NvOdmOsFree(pDevice);
+    pDevice = NULL;
+    
+    return NULL;
+}
+
+void NvOdmUartClose(NvOdmUartHandle hOdmUart)
+{
+
+    if (hOdmUart)
+    {
+        // Switch OFF UART Interface
+
+        if (hOdmUart->hPmu != NULL)
+        {
+            NvOdmServicesPmuClose(hOdmUart->hPmu);
+        }
+        NvOdmOsFree(hOdmUart);
+        hOdmUart = NULL;
+    }
+}
+
+NvBool NvOdmUartSuspend(NvOdmUartHandle hOdmUart)
+{
+    return NV_FALSE;
+}
+
+NvBool NvOdmUartResume(NvOdmUartHandle hOdmUart)
+{
+    return NV_FALSE;
+}
+
diff --git a/arch/arm/mach-tegra/odm_kit/adaptations/misc/harmony/nvodm_usbulpi.c b/arch/arm/mach-tegra/odm_kit/adaptations/misc/harmony/nvodm_usbulpi.c
new file mode 100644
index 000000000000..63bdf09a14ae
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/adaptations/misc/harmony/nvodm_usbulpi.c
@@ -0,0 +1,144 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+ 
+/**
+ * @file          nvodm_usbulpi.c
+ * @brief         <b>Adaptation for USB ULPI </b>
+ *
+ * @Description : Implementation of the USB ULPI adaptation.
+ */
+#include "nvodm_usbulpi.h"
+#include "nvodm_services.h"
+#include "nvodm_query_discovery.h"
+#include "nvodm_services.h"
+#include "nvos.h"
+
+#define SMSC3317GUID NV_ODM_GUID('s','m','s','c','3','3','1','7')
+
+#define MAX_CLOCKS 3
+
+#define NVODM_PORT(x) ((x) - 'a')
+#define ULPI_RESET_PORT NVODM_PORT('v')
+#define ULPI_RESET_PIN 1
+
+
+#ifdef NV_DRIVER_DEBUG
+    #define NV_DRIVER_TRACE NvOsDebugPrintf
+#else
+    #define NV_DRIVER_TRACE (void)
+#endif
+
+typedef struct NvOdmUsbUlpiRec
+{
+     NvU64    CurrentGUID;
+} NvOdmUsbUlpi;
+
+static NvOdmServicesGpioHandle s_hGpio = NULL;
+static NvOdmGpioPinHandle s_hResetPin = NULL;
+
+NvOdmUsbUlpiHandle NvOdmUsbUlpiOpen(NvU32 Instance)
+{
+    NvOdmUsbUlpi*pDevice = NULL;
+    NvU32 ClockInstances[MAX_CLOCKS];
+    NvU32 ClockFrequencies[MAX_CLOCKS];
+    NvU32 NumClocks;
+
+    pDevice = NvOdmOsAlloc(sizeof(NvOdmUsbUlpi));
+    if(pDevice == NULL)
+		return NULL;
+    
+    if(!NvOdmExternalClockConfig(SMSC3317GUID, NV_FALSE, ClockInstances,
+					ClockFrequencies, &NumClocks))
+    {
+        NV_DRIVER_TRACE (("ERROR NvOdmUsbUlpiOpen: "
+				"NvOdmExternalClockConfig fail\n"));
+        goto ExitUlpiOdm;
+    }
+    NvOdmOsSleepMS(10);
+
+    if (!s_hGpio)
+        s_hGpio = NvOdmGpioOpen();
+    if (!s_hGpio)
+    {
+        NV_DRIVER_TRACE (("ERROR NvOdmUsbUlpiOpen: "
+				"Not able to open gpio handle\n"));
+        goto ExitUlpiOdm;
+    }
+
+    if (!s_hResetPin)
+        s_hResetPin = NvOdmGpioAcquirePinHandle(s_hGpio, ULPI_RESET_PORT,
+							ULPI_RESET_PIN);
+    if (!s_hResetPin)
+    {
+        NvOdmGpioClose(s_hGpio);
+        s_hGpio = NULL;
+        NV_DRIVER_TRACE (("ERROR NvOdmGpioAcquirePinHandle: "
+					"Not able to Acq pinhandle\n"));
+        goto ExitUlpiOdm;
+    }
+
+    // Pull high on RESETB ( 22nd pin of smsc3315) 
+    // config as out put pin
+    NvOdmGpioConfig(s_hGpio,s_hResetPin, NvOdmGpioPinMode_Output);
+    // Set low to write high on ULPI_RESETB pin
+    NvOdmGpioSetState(s_hGpio, s_hResetPin, 0x01);
+    NvOdmGpioSetState(s_hGpio, s_hResetPin, 0x0);
+    NvOdmOsSleepMS(5);
+    NvOdmGpioSetState(s_hGpio, s_hResetPin, 0x01);
+
+    pDevice->CurrentGUID = SMSC3317GUID;
+    return pDevice;
+
+ExitUlpiOdm:
+    NvOdmOsFree(pDevice);
+    return NULL;
+}
+
+void NvOdmUsbUlpiClose(NvOdmUsbUlpiHandle hOdmUlpi)
+{
+    if (hOdmUlpi)
+    {
+        NvOdmOsFree(hOdmUlpi);
+    }
+    if (s_hResetPin)
+    {
+        NvOdmGpioReleasePinHandle(s_hGpio, s_hResetPin);
+        s_hResetPin = NULL;
+    }
+    if (s_hGpio)
+    {
+        NvOdmGpioClose(s_hGpio);
+        s_hGpio = NULL;
+    }
+
+}
+
diff --git a/arch/arm/mach-tegra/odm_kit/adaptations/misc/whistler/Makefile b/arch/arm/mach-tegra/odm_kit/adaptations/misc/whistler/Makefile
new file mode 100644
index 000000000000..9f3eb8402b6b
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/adaptations/misc/whistler/Makefile
@@ -0,0 +1,15 @@
+ccflags-y += -DNV_IS_AVP=0
+ccflags-y += -DNV_OAL=0
+ccflags-y += -DNV_USE_FUSE_CLOCK_ENABLE=0
+ifeq ($(CONFIG_MACH_TEGRA_GENERIC_DEBUG),y)
+ccflags-y += -DNV_DEBUG=1
+else
+ccflags-y += -DNV_DEBUG=0
+endif
+
+obj-$(CONFIG_KEYBOARD_TEGRA)	+= nvodm_kbc.o
+obj-$(CONFIG_KEYBOARD_TEGRA)	+= nvodm_kbc_keymapping.o
+obj-y				+= nvodm_sdio.o
+obj-y				+= nvodm_uart.o
+obj-y				+= nvodm_usbulpi.o
+
diff --git a/arch/arm/mach-tegra/odm_kit/adaptations/misc/whistler/nvodm_kbc.c b/arch/arm/mach-tegra/odm_kit/adaptations/misc/whistler/nvodm_kbc.c
new file mode 100644
index 000000000000..70b468d9ff51
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/adaptations/misc/whistler/nvodm_kbc.c
@@ -0,0 +1,145 @@
+/*
+ * Copyright (c) 2008-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+ 
+/**
+ * @file          Nvodm_Kbc.c
+ * @brief         <b>KBC odm implementation</b>
+ *
+ * @Description : Implementation of the odm KBC API
+ */
+#include "nvodm_kbc.h"
+
+
+#define KEYPAD_HAS_DIODES 1
+
+NvU32
+NvOdmKbcFilterKeys(
+    NvU32 *pRows,
+    NvU32 *pCols,
+    NvU32 NumOfKeysPressed)
+{
+
+#if KEYPAD_HAS_DIODES
+    return NumOfKeysPressed;
+#else
+    NvU32 i=0;
+    NvU32 j=0;
+    NvU32 k=0;
+    NvU32 FilterKeys[2] = {0};
+    NvBool IsFiltered = NV_FALSE;
+    NvU32 NewKeyPressCount = NumOfKeysPressed;
+    
+    if (NumOfKeysPressed <= 3)
+    {
+        for (i=0; i<NumOfKeysPressed; i++)
+        {
+            for (j=(i+1); j<NumOfKeysPressed; j++)
+            {
+                if ((pRows[i]+1==pRows[j])||(pRows[j]+1==pRows[i]))
+                {
+                    for (k=j; i<(NumOfKeysPressed - 1); i++)
+                    {
+                        pRows[k] = pRows[k+1];
+                        pCols[k] = pCols[k+1];
+                    }
+                    NumOfKeysPressed--;
+                }
+                if ((pCols[i]+1==pCols[j])||(pCols[j]+1==pCols[i]))
+                {
+                    for (k=j; i<(NumOfKeysPressed - 1); i++)
+                    {
+                        pRows[k] = pRows[k+1];
+                        pCols[k] = pCols[k+1];
+                    }
+                    NumOfKeysPressed--;
+                }
+            }
+        }
+        return NumOfKeysPressed;
+    }   
+
+    for (i=0; i<NumOfKeysPressed; i++)
+    {
+        for (j=(i+1); j<NumOfKeysPressed; j++)
+        {
+            if (pRows[i] == pRows[j])
+            {
+                for (k=0; k<NumOfKeysPressed; k++)
+                {
+                    if (k == i)
+                        continue;
+
+                    if(pCols[i] == pCols[k])
+                    {
+                        FilterKeys[0] = k;
+                        IsFiltered = NV_TRUE;
+                    }
+                }
+                for (k=0; k<NumOfKeysPressed; k++)
+                {
+                    if (k == j)
+                        continue;
+                    
+                    if (pCols[j] == pCols[k])
+                    {
+                        FilterKeys[1] = k;
+                        IsFiltered = NV_TRUE;
+                    }
+                }
+                goto end;
+            }
+        }
+    }
+
+    end:
+        if (IsFiltered)
+        {
+            for (i=FilterKeys[0]; i<(NumOfKeysPressed - 1); i++)
+            {
+                pRows[i] = pRows[i+1];
+                pCols[i] = pCols[i+1];
+            }
+            NewKeyPressCount--;
+            for (i=FilterKeys[1]; i<(NumOfKeysPressed - 1); i++)
+            {
+                pRows[i] = pRows[i+1];
+                pCols[i] = pCols[i+1];
+            }
+            NewKeyPressCount--;
+        }
+        NumOfKeysPressed = NewKeyPressCount;
+    return NewKeyPressCount;
+#endif
+    
+}
+
+
diff --git a/arch/arm/mach-tegra/odm_kit/adaptations/misc/whistler/nvodm_kbc_keymapping.c b/arch/arm/mach-tegra/odm_kit/adaptations/misc/whistler/nvodm_kbc_keymapping.c
new file mode 100644
index 000000000000..1f2dd7275eae
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/adaptations/misc/whistler/nvodm_kbc_keymapping.c
@@ -0,0 +1,75 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/** 
+ * @file
+ * <b>NVIDIA Tegra ODM Kit:
+ *         Keyboard Controller virtual key mapping</b>
+ *
+ * @b Description: Implement the ODM keyboard mapping to the platform 
+ *                  specific.
+ */
+#include "nvodm_kbc_keymapping.h"
+#include <linux/input.h>
+
+/* The total number of soc scan codes will be (first - last) */
+#define NV_SOC_NORMAL_KEY_SCAN_CODE_TABLE_FIRST    0
+#define NV_SOC_NORMAL_KEY_SCAN_CODE_TABLE_LAST     3
+
+static NvU32 KbcLayOutVirtualKey[] =
+{
+ KEY_MENU,
+ 0,
+ KEY_HOME,
+ KEY_BACK
+};
+
+static struct NvOdmKeyVirtTableDetail s_ScvkKeyMap =
+{
+    NV_SOC_NORMAL_KEY_SCAN_CODE_TABLE_FIRST,    // scan code start
+    NV_SOC_NORMAL_KEY_SCAN_CODE_TABLE_LAST,     // scan code end
+    KbcLayOutVirtualKey          // Normal Qwerty keyboard
+};
+
+
+static const struct NvOdmKeyVirtTableDetail *s_pVirtualKeyTables[] =
+     {&s_ScvkKeyMap};
+     
+
+NvU32 
+NvOdmKbcKeyMappingGetVirtualKeyMappingList(
+    const struct NvOdmKeyVirtTableDetail ***pVirtKeyTableList)
+{
+   *pVirtKeyTableList = s_pVirtualKeyTables;
+   return NV_ARRAY_SIZE(s_pVirtualKeyTables);
+}
+
diff --git a/arch/arm/mach-tegra/odm_kit/adaptations/misc/whistler/nvodm_sdio.c b/arch/arm/mach-tegra/odm_kit/adaptations/misc/whistler/nvodm_sdio.c
new file mode 100644
index 000000000000..d980dfca3b2b
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/adaptations/misc/whistler/nvodm_sdio.c
@@ -0,0 +1,358 @@
+/*
+ * Copyright (c) 2008-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+ 
+/**
+ * @file          Nvodm_Sdio.c
+ * @brief         <b>Sdio odm implementation</b>
+ *
+ * @Description : Implementation of the odm sdio API
+ */
+#include "nvodm_sdio.h"
+#include "nvodm_services.h"
+#include "nvodm_query_discovery.h"
+#include "nvodm_services.h"
+#include "nvodm_pmu.h"
+
+#ifdef NV_DRIVER_DEBUG
+    #define NV_DRIVER_TRACE(x) NvOdmOsDebugPrintf x
+#else
+    #define NV_DRIVER_TRACE(x)
+#endif
+
+#define WLAN_GUID            NV_ODM_GUID('s','d','i','o','w','l','a','n')
+// Device Board definitions
+#define BOARD_ID_E951        (0x0933) /* Decimal  951. => ((9<<8) | 51)*/
+
+
+typedef enum
+{
+    NvOdmSdioDiscoveryAddress_0 = 0,
+    NvOdmSdioDiscoveryAddress_1,
+    
+    NvOdmSdioDiscoveryAddress_Force32 = 0x7FFFFFFF,
+        
+} NvOdmSdioDiscoveryAddress;
+
+typedef struct NvOdmSdioRec
+{
+    // NvODM PMU device handle
+    NvOdmServicesPmuHandle hPmu;
+    // Gpio Handle
+    NvOdmServicesGpioHandle hGpio;
+    // Pin handle to Wlan Reset Gpio pin
+    NvOdmGpioPinHandle hResetPin;
+    // Pin handle to Wlan PWR GPIO Pin
+    NvOdmGpioPinHandle hPwrPin;
+    NvOdmPeripheralConnectivity *pConnectivity;
+    // Power state
+    NvBool PoweredOn;
+    // Instance
+    NvU32 Instance;
+} NvOdmSdio;
+
+static void NvOdmSetPowerOnSdio(NvOdmSdioHandle pDevice, NvBool IsEnable);
+static NvBool SdioOdmWlanSetPowerOn(NvOdmSdioHandle hOdmSdio, NvBool IsEnable);
+
+
+static NvBool SdioOdmWlanSetPowerOn(NvOdmSdioHandle hOdmSdio, NvBool IsEnable)
+{
+    if (IsEnable) 
+    {
+        // Wlan Power On Reset Sequence
+        NvOdmGpioSetState(hOdmSdio->hGpio, hOdmSdio->hPwrPin, 0x0);      //PWD -> Low
+        NvOdmGpioSetState(hOdmSdio->hGpio, hOdmSdio->hResetPin, 0x0);    //RST -> Low
+        NvOdmOsWaitUS(2000);
+        NvOdmGpioSetState(hOdmSdio->hGpio, hOdmSdio->hPwrPin, 0x1);      //PWD -> High
+        NvOdmGpioSetState(hOdmSdio->hGpio, hOdmSdio->hResetPin, 0x1);    //RST -> High
+     }
+     else 
+     {
+         // Power Off sequence
+         NvOdmGpioSetState(hOdmSdio->hGpio, hOdmSdio->hPwrPin, 0x0);     //PWD -> Low
+     }
+     return NV_TRUE;
+}
+
+NvOdmSdioHandle NvOdmSdioOpen(NvU32 Instance)
+{
+    static NvOdmSdio *pDevice = NULL;
+    NvOdmServicesGpioHandle hGpioTemp = NULL;
+    NvOdmPeripheralConnectivity *pConnectivity;
+    NvU32 NumOfGuids = 1;
+    NvU64 guid;
+    NvU32 searchVals[4];
+    const NvU32 *pOdmConfigs;
+    NvU32 NumOdmConfigs;
+    NvBool Status = NV_TRUE;
+    const NvOdmPeripheralSearch searchAttrs[] =
+    {
+        NvOdmPeripheralSearch_PeripheralClass,
+        NvOdmPeripheralSearch_IoModule,
+        NvOdmPeripheralSearch_Instance,
+        NvOdmPeripheralSearch_Address,
+    };
+    NvOdmBoardInfo BoardInfo;
+    NvBool status = NV_FALSE;
+    
+    searchVals[0] =  NvOdmPeripheralClass_Other;
+    searchVals[1] =  NvOdmIoModule_Sdio;
+    searchVals[2] =  Instance;
+
+    NvOdmQueryPinMux(NvOdmIoModule_Sdio, &pOdmConfigs, &NumOdmConfigs); 
+    if ((Instance == 0) && (pOdmConfigs[0] == NvOdmSdioPinMap_Config1))
+    {
+        // sdio is connected to sdio2 slot.  
+        searchVals[3] =  NvOdmSdioDiscoveryAddress_1;
+    }
+    else
+    {
+        // sdio is connected to wifi module.
+        searchVals[3] =  NvOdmSdioDiscoveryAddress_0;
+    }
+
+    NumOfGuids = NvOdmPeripheralEnumerate(searchAttrs,
+                                          searchVals,
+                                          4,
+                                          &guid,
+                                          NumOfGuids);
+
+    // Get the peripheral connectivity information
+    pConnectivity = (NvOdmPeripheralConnectivity *)NvOdmPeripheralGetGuid(guid);
+    if (pConnectivity == NULL)
+        return NULL;
+
+    pDevice = NvOdmOsAlloc(sizeof(NvOdmSdio));
+    if(pDevice == NULL)
+        return (pDevice);
+
+    pDevice->hPmu = NvOdmServicesPmuOpen();
+    if(pDevice->hPmu == NULL)
+    {
+        NvOdmOsFree(pDevice);
+        pDevice = NULL;
+        return (NULL);
+    }
+
+    if (pConnectivity->Guid == WLAN_GUID)
+    {
+        // WARNING: This function *cannot* be called before RmOpen().
+        status = NvOdmPeripheralGetBoardInfo((BOARD_ID_E951), &BoardInfo);
+        if (NV_TRUE != status)
+        {
+            // whistler should have E951 Module, if it is not presnt return NULL Handle.
+            NvOdmServicesPmuClose(pDevice->hPmu);
+            NvOdmOsFree(pDevice);
+            pDevice = NULL;
+            NvOdmOsDebugPrintf(("No E951 Detected"));
+            return (pDevice);
+        }
+    }
+
+    pDevice->pConnectivity = pConnectivity;
+    NvOdmSetPowerOnSdio(pDevice, NV_TRUE);
+
+    if (pConnectivity->Guid == WLAN_GUID)
+    {
+        // Getting the OdmGpio Handle
+        hGpioTemp = NvOdmGpioOpen();
+        if (hGpioTemp == NULL)
+        {
+            NvOdmServicesPmuClose(pDevice->hPmu);
+            NvOdmOsFree(pDevice);
+            pDevice = NULL;
+            return (pDevice);
+        }
+    
+        // Search for the Vdd rail and set the proper volage to the rail.
+        if (pConnectivity->AddressList[1].Interface == NvOdmIoModule_Gpio)
+        {
+             // Acquiring Pin Handles for Power Pin
+             pDevice->hPwrPin= NvOdmGpioAcquirePinHandle(hGpioTemp, 
+                   pConnectivity->AddressList[1].Instance,
+                   pConnectivity->AddressList[1].Address);
+        }
+         
+        if (pConnectivity->AddressList[2].Interface == NvOdmIoModule_Gpio)
+        {
+             // Acquiring Pin Handles for Reset Pin
+             pDevice->hResetPin= NvOdmGpioAcquirePinHandle(hGpioTemp, 
+                   pConnectivity->AddressList[2].Instance,
+                   pConnectivity->AddressList[2].Address);
+        }
+
+        // Setting the ON/OFF pin to output mode.
+        NvOdmGpioConfig(hGpioTemp, pDevice->hPwrPin, NvOdmGpioPinMode_Output);
+        NvOdmGpioConfig(hGpioTemp, pDevice->hResetPin, NvOdmGpioPinMode_Output);
+
+        // Setting the Output Pin to Low
+        NvOdmGpioSetState(hGpioTemp, pDevice->hPwrPin, 0x0);
+        NvOdmGpioSetState(hGpioTemp, pDevice->hResetPin, 0x0);
+
+        pDevice->hGpio = hGpioTemp;
+
+        Status = SdioOdmWlanSetPowerOn(pDevice, NV_TRUE);
+        if (Status != NV_TRUE)
+        {
+            NvOdmServicesPmuClose(pDevice->hPmu);
+            NvOdmGpioReleasePinHandle(pDevice->hGpio, pDevice->hPwrPin);
+            NvOdmGpioReleasePinHandle(pDevice->hGpio, pDevice->hResetPin);    
+            NvOdmGpioClose(pDevice->hGpio);   
+            NvOdmOsFree(pDevice);
+            pDevice = NULL;
+            return (pDevice);
+        }
+    }
+    pDevice->PoweredOn = NV_TRUE;
+    pDevice->Instance = Instance;
+    NV_DRIVER_TRACE(("Open SDIO%d", Instance));
+    return pDevice;
+}
+
+void NvOdmSdioClose(NvOdmSdioHandle hOdmSdio)
+{
+    const NvOdmPeripheralConnectivity *pConnectivity = NULL;
+
+    NV_DRIVER_TRACE(("Close SDIO%d", hOdmSdio->Instance));
+
+    pConnectivity = hOdmSdio->pConnectivity;
+    if (pConnectivity->Guid == WLAN_GUID)
+    {
+        // Call Turn off power when close is Called
+        (void)SdioOdmWlanSetPowerOn(hOdmSdio, NV_FALSE);
+
+        NvOdmGpioReleasePinHandle(hOdmSdio->hGpio, hOdmSdio->hPwrPin);
+        NvOdmGpioReleasePinHandle(hOdmSdio->hGpio, hOdmSdio->hResetPin);    
+        NvOdmGpioClose(hOdmSdio->hGpio);
+    }
+    NvOdmSetPowerOnSdio(hOdmSdio, NV_FALSE);
+    if (hOdmSdio->hPmu != NULL)
+    {
+         NvOdmServicesPmuClose(hOdmSdio->hPmu);
+    }
+    NvOdmOsFree(hOdmSdio);
+    hOdmSdio = NULL;
+}
+
+static void NvOdmSetPowerOnSdio(NvOdmSdioHandle pDevice, NvBool IsEnable)
+{
+    NvU32 Index = 0;
+    NvOdmServicesPmuVddRailCapabilities RailCaps;
+    NvU32 SettlingTime = 0;
+    const NvOdmPeripheralConnectivity *pConnectivity;
+
+    pConnectivity = pDevice->pConnectivity;
+    if (IsEnable) // Turn on Power
+    {
+        // Search for the Vdd rail and set the proper volage to the rail.
+        for (Index = 0; Index < pConnectivity->NumAddress; ++Index)
+        {
+            if (pConnectivity->AddressList[Index].Interface == NvOdmIoModule_Vdd)
+            {
+                NvOdmServicesPmuGetCapabilities(pDevice->hPmu, pConnectivity->AddressList[Index].Address, &RailCaps);
+                NvOdmServicesPmuSetVoltage(pDevice->hPmu, pConnectivity->AddressList[Index].Address,
+                                RailCaps.requestMilliVolts, &SettlingTime);
+                if (SettlingTime)
+                {
+                    NvOdmOsWaitUS(SettlingTime);
+                }
+            }
+        }
+    }
+    else // Shutdown Power
+    {
+        // Search for the Vdd rail and power Off the module
+        for (Index = 0; Index < pConnectivity->NumAddress; ++Index)
+        {
+            if (pConnectivity->AddressList[Index].Interface == NvOdmIoModule_Vdd)
+            {
+                NvOdmServicesPmuGetCapabilities(pDevice->hPmu, pConnectivity->AddressList[Index].Address, &RailCaps);
+                NvOdmServicesPmuSetVoltage(pDevice->hPmu, pConnectivity->AddressList[Index].Address,
+                                ODM_VOLTAGE_OFF, &SettlingTime);
+                if (SettlingTime)
+                {
+                    NvOdmOsWaitUS(SettlingTime);
+                }
+            }
+        }
+    }
+}
+
+NvBool NvOdmSdioSuspend(NvOdmSdioHandle hOdmSdio)
+{
+
+    const NvOdmPeripheralConnectivity *pConnectivity = NULL;
+    NvBool Status = NV_TRUE;
+
+    if (!hOdmSdio->PoweredOn)
+    {
+        NV_DRIVER_TRACE(("SDIO%d already suspended", hOdmSdio->Instance));
+        return NV_TRUE;
+    }
+
+    NV_DRIVER_TRACE(("Suspend SDIO%d", hOdmSdio->Instance));
+    NvOdmSetPowerOnSdio(hOdmSdio, NV_FALSE);
+
+    pConnectivity = hOdmSdio->pConnectivity;
+    if (pConnectivity->Guid == WLAN_GUID)
+    {
+        // Turn off power
+        Status = SdioOdmWlanSetPowerOn(hOdmSdio, NV_FALSE);
+
+    }
+    hOdmSdio->PoweredOn = NV_FALSE;
+    return Status;
+
+}
+
+NvBool NvOdmSdioResume(NvOdmSdioHandle hOdmSdio)
+{
+    const NvOdmPeripheralConnectivity *pConnectivity = NULL;
+    NvBool Status = NV_TRUE;
+
+    if (hOdmSdio->PoweredOn)
+    {
+        NV_DRIVER_TRACE(("SDIO%d already resumed", hOdmSdio->Instance));
+        return NV_TRUE;
+    }
+
+    NvOdmSetPowerOnSdio(hOdmSdio, NV_TRUE);
+
+    pConnectivity = hOdmSdio->pConnectivity;
+    if (pConnectivity->Guid == WLAN_GUID)
+    {
+        // Turn on power
+        Status = SdioOdmWlanSetPowerOn(hOdmSdio, NV_TRUE);
+    }
+    NV_DRIVER_TRACE(("Resume SDIO%d", hOdmSdio->Instance));
+    hOdmSdio->PoweredOn = NV_TRUE;
+    return Status;
+}
diff --git a/arch/arm/mach-tegra/odm_kit/adaptations/misc/whistler/nvodm_uart.c b/arch/arm/mach-tegra/odm_kit/adaptations/misc/whistler/nvodm_uart.c
new file mode 100644
index 000000000000..a3f09ad89c18
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/adaptations/misc/whistler/nvodm_uart.c
@@ -0,0 +1,138 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+ 
+/**
+ * @file          nvodm_uart.c
+ * @brief         <b>Adaptation for uart </b>
+ *
+ * @Description : Implementation of the uart adaptation.
+ */
+#include "nvodm_uart.h"
+#include "nvodm_services.h"
+#include "nvodm_query_discovery.h"
+#include "nvodm_services.h"
+#include "nvos.h"
+#include "nvodm_pmu.h"
+
+#ifdef NV_DRIVER_DEBUG
+    #define NV_DRIVER_TRACE NvOsDebugPrintf
+#else
+    #define NV_DRIVER_TRACE (void)
+#endif
+
+typedef struct NvOdmUartRec
+{
+    // NvODM PMU device handle
+    NvOdmServicesPmuHandle hPmu;
+    // Gpio Handle
+    NvOdmServicesGpioHandle hGpio;    
+    // Pin handle to Bluetooth Reset Gpio pin
+    NvOdmGpioPinHandle hResetPin;
+    NvOdmPeripheralConnectivity *pConnectivity;
+} NvOdmUart;
+
+NvOdmUartHandle NvOdmUartOpen(NvU32 Instance)
+{
+    NvOdmUart *pDevice = NULL;
+    NvOdmPeripheralConnectivity *pConnectivity;
+    NvU32 NumOfGuids = 1;
+    NvU64 guid;
+    NvU32 searchVals[2];
+    const NvOdmPeripheralSearch searchAttrs[] =
+    {
+        NvOdmPeripheralSearch_IoModule,
+        NvOdmPeripheralSearch_Instance,
+    };
+    
+    searchVals[0] =  NvOdmIoModule_Uart;
+    searchVals[1] =  Instance;
+
+    NumOfGuids = NvOdmPeripheralEnumerate(
+                                                    searchAttrs,
+                                                    searchVals,
+                                                    2,
+                                                    &guid,
+                                                    NumOfGuids); 
+
+    pConnectivity = (NvOdmPeripheralConnectivity *)NvOdmPeripheralGetGuid(guid);
+    if (pConnectivity == NULL)
+        goto ExitUartOdm;
+    
+    pDevice = NvOdmOsAlloc(sizeof(NvOdmUart));
+    if(pDevice == NULL)
+        goto ExitUartOdm;
+    
+    pDevice->hPmu = NvOdmServicesPmuOpen();
+    if(pDevice->hPmu == NULL)
+    {
+        goto ExitUartOdm;
+    }
+
+    // Switch On UART Interface
+
+    pDevice->pConnectivity = pConnectivity;
+   
+    return pDevice;
+
+ExitUartOdm:
+    NvOdmOsFree(pDevice);
+    pDevice = NULL;
+    
+    return NULL;
+}
+
+void NvOdmUartClose(NvOdmUartHandle hOdmUart)
+{
+
+    if (hOdmUart)
+    {
+        // Switch OFF UART Interface
+
+        if (hOdmUart->hPmu != NULL)
+        {
+            NvOdmServicesPmuClose(hOdmUart->hPmu);
+        }
+        NvOdmOsFree(hOdmUart);
+        hOdmUart = NULL;
+    }
+}
+
+NvBool NvOdmUartSuspend(NvOdmUartHandle hOdmUart)
+{
+    return NV_FALSE;
+}
+
+NvBool NvOdmUartResume(NvOdmUartHandle hOdmUart)
+{
+    return NV_FALSE;
+}
+
diff --git a/arch/arm/mach-tegra/odm_kit/adaptations/misc/whistler/nvodm_usbulpi.c b/arch/arm/mach-tegra/odm_kit/adaptations/misc/whistler/nvodm_usbulpi.c
new file mode 100644
index 000000000000..5bd21b2bd51b
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/adaptations/misc/whistler/nvodm_usbulpi.c
@@ -0,0 +1,235 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/**
+ * @file          nvodm_usbulpi.c
+ * @brief         <b>Adaptation for USB ULPI </b>
+ *
+ * @Description : Implementation of the USB ULPI adaptation.
+ */
+#include "nvodm_usbulpi.h"
+#include "nvodm_services.h"
+#include "nvodm_query_discovery.h"
+#include "nvodm_services.h"
+#include "nvodm_keylist_reserved.h"
+#include "nvrm_drf.h"
+#include "nvos.h"
+
+typedef struct NvOdmUsbUlpiRec {
+	NvU64 CurrentGUID;
+} NvOdmUsbUlpi;
+
+/* ST-Ericsson U3XX modem power control */
+struct ste_u3xx_info {
+	NvU32 ste_u3xx_uart_port;
+	NvU32 ste_u3xx_reset_port;
+	NvU32 ste_u3xx_reset_pin;
+	NvU32 ste_u3xx_power_port;
+	NvU32 ste_u3xx_power_pin;
+	NvU32 ste_u3xx_awr_port;
+	NvU32 ste_u3xx_awr_pin;
+	NvU32 ste_u3xx_cwr_port;
+	NvU32 ste_u3xx_cwr_pin;
+	NvU32 ste_u3xx_spi_int_port;
+	NvU32 ste_u3xx_spi_int_pin;
+	NvU32 ste_u3xx_slave_select_port;
+	NvU32 ste_u3xx_slave_select_pin;
+	NvU32 ste_u3xx_slink_instance;
+};
+
+/* ST-Ericsson U3XX modem control */
+static struct ste_u3xx_info ste_u3xx_info;
+static NvOdmServicesGpioHandle ste_u3xx_gpio;
+static NvOdmGpioPinHandle ste_u3xx_reset_gpio_pin;
+static NvOdmGpioPinHandle ste_u3xx_power_gpio_pin;
+static NvOdmGpioPinHandle ste_u3xx_awr_gpio_pin;
+static NvOdmGpioPinHandle ste_u3xx_cwr_gpio_pin;
+
+static int ste_u3xx_query(struct ste_u3xx_info *info)
+{
+	NvU64 guid = NV_ODM_GUID('e', 'm', 'p', ' ', 'M', '5', '7', '0');
+	NvOdmPeripheralConnectivity *pConnectivity;
+
+	/* query odm kit for modem support */
+	pConnectivity =
+	    (NvOdmPeripheralConnectivity *) NvOdmPeripheralGetGuid(guid);
+	if (pConnectivity == NULL)
+		return -1;
+	NV_ASSERT(pConnectivity->NumAddress >= 5);
+
+	/* query for uart port */
+	NV_ASSERT(pConnectivity->AddressList[0].Interface ==
+		  NvOdmIoModule_Uart);
+	info->ste_u3xx_uart_port = pConnectivity->AddressList[0].Instance;
+
+	/* query for reset pin */
+	NV_ASSERT(pConnectivity->AddressList[1].Interface ==
+		  NvOdmIoModule_Gpio);
+	info->ste_u3xx_reset_port = pConnectivity->AddressList[1].Instance;
+	info->ste_u3xx_reset_pin = pConnectivity->AddressList[1].Address;
+
+	/* query for power pin */
+	NV_ASSERT(pConnectivity->AddressList[2].Interface ==
+		  NvOdmIoModule_Gpio);
+	info->ste_u3xx_power_port = pConnectivity->AddressList[2].Instance;
+	info->ste_u3xx_power_pin = pConnectivity->AddressList[2].Address;
+
+	/* query for ACPU wakeup request pin */
+	NV_ASSERT(pConnectivity->AddressList[3].Interface ==
+		  NvOdmIoModule_Gpio);
+	info->ste_u3xx_awr_port = pConnectivity->AddressList[3].Instance;
+	info->ste_u3xx_awr_pin = pConnectivity->AddressList[3].Address;
+
+	/* query for CCPU wakeup request pin */
+	NV_ASSERT(pConnectivity->AddressList[4].Interface ==
+		  NvOdmIoModule_Gpio);
+	info->ste_u3xx_cwr_port = pConnectivity->AddressList[4].Instance;
+	info->ste_u3xx_cwr_pin = pConnectivity->AddressList[4].Address;
+
+	return 0;
+}
+
+static void ste_u3xx_turn_on_modem(struct ste_u3xx_info *info)
+{
+	/* get odm gpio handle */
+	ste_u3xx_gpio = NvOdmGpioOpen();
+	if (!ste_u3xx_gpio)
+		return;
+
+	/* acquire pin handle for reset pin */
+	ste_u3xx_reset_gpio_pin =
+	    NvOdmGpioAcquirePinHandle(ste_u3xx_gpio, info->ste_u3xx_reset_port,
+				      info->ste_u3xx_reset_pin);
+	if (!ste_u3xx_reset_gpio_pin) {
+		NvOdmGpioClose(ste_u3xx_gpio);
+		return;
+	}
+
+	/* acquire pin handle for power pin */
+	ste_u3xx_power_gpio_pin =
+	    NvOdmGpioAcquirePinHandle(ste_u3xx_gpio, info->ste_u3xx_power_port,
+				      info->ste_u3xx_power_pin);
+	if (!ste_u3xx_power_gpio_pin) {
+		NvOdmGpioReleasePinHandle(ste_u3xx_gpio,
+					  ste_u3xx_reset_gpio_pin);
+		NvOdmGpioClose(ste_u3xx_gpio);
+		return;
+	}
+
+	/* acquire pin handle for ACPU wakeup request pin */
+	ste_u3xx_awr_gpio_pin =
+	    NvOdmGpioAcquirePinHandle(ste_u3xx_gpio, info->ste_u3xx_awr_port,
+				      info->ste_u3xx_awr_pin);
+	if (!ste_u3xx_awr_gpio_pin) {
+		NvOdmGpioReleasePinHandle(ste_u3xx_gpio,
+					  ste_u3xx_power_gpio_pin);
+		NvOdmGpioReleasePinHandle(ste_u3xx_gpio,
+					  ste_u3xx_reset_gpio_pin);
+		NvOdmGpioClose(ste_u3xx_gpio);
+		return;
+	}
+
+	/* acquire pin handle for CCPU wakeup request pin */
+	ste_u3xx_cwr_gpio_pin =
+	    NvOdmGpioAcquirePinHandle(ste_u3xx_gpio, info->ste_u3xx_cwr_port,
+				      info->ste_u3xx_cwr_pin);
+	if (!ste_u3xx_cwr_gpio_pin) {
+		NvOdmGpioReleasePinHandle(ste_u3xx_gpio, ste_u3xx_awr_gpio_pin);
+		NvOdmGpioReleasePinHandle(ste_u3xx_gpio,
+					  ste_u3xx_power_gpio_pin);
+		NvOdmGpioReleasePinHandle(ste_u3xx_gpio,
+					  ste_u3xx_reset_gpio_pin);
+		NvOdmGpioClose(ste_u3xx_gpio);
+		return;
+	}
+
+	/* set output levels - start with modem power off, reset deasserted */
+	NvOdmGpioSetState(ste_u3xx_gpio, ste_u3xx_power_gpio_pin, 0);
+	NvOdmGpioSetState(ste_u3xx_gpio, ste_u3xx_reset_gpio_pin, 0);
+	NvOdmGpioConfig(ste_u3xx_gpio, ste_u3xx_power_gpio_pin,
+			NvOdmGpioPinMode_Output);
+	NvOdmGpioConfig(ste_u3xx_gpio, ste_u3xx_reset_gpio_pin,
+			NvOdmGpioPinMode_Output);
+	NvOdmGpioConfig(ste_u3xx_gpio, ste_u3xx_cwr_gpio_pin,
+			NvOdmGpioPinMode_InputData);
+
+	NvOdmOsSleepMS(300);
+	NvOdmGpioSetState(ste_u3xx_gpio, ste_u3xx_reset_gpio_pin, 1);
+
+	/* pulse modem power on for 300 ms */
+	NvOdmOsSleepMS(300);
+	NvOdmGpioSetState(ste_u3xx_gpio, ste_u3xx_power_gpio_pin, 1);
+	NvOdmOsSleepMS(300);
+	NvOdmGpioSetState(ste_u3xx_gpio, ste_u3xx_power_gpio_pin, 0);
+	NvOdmOsSleepMS(100);
+
+	NvOdmGpioReleasePinHandle(ste_u3xx_gpio, ste_u3xx_cwr_gpio_pin);
+	NvOdmGpioReleasePinHandle(ste_u3xx_gpio, ste_u3xx_awr_gpio_pin);
+	NvOdmGpioReleasePinHandle(ste_u3xx_gpio, ste_u3xx_power_gpio_pin);
+	NvOdmGpioReleasePinHandle(ste_u3xx_gpio, ste_u3xx_reset_gpio_pin);
+	NvOdmGpioClose(ste_u3xx_gpio);
+}
+
+NvOdmUsbUlpiHandle NvOdmUsbUlpiOpen(NvU32 Instance)
+{
+	const NvOdmUsbProperty *pUsbProperty =
+		NvOdmQueryGetUsbProperty(NvOdmIoModule_Usb, Instance);
+	NvOdmUsbUlpi *pDevice = NULL;
+
+	pDevice = NvOdmOsAlloc(sizeof(NvOdmUsbUlpi));
+	if (pDevice == NULL)
+		goto ExitUlpiOdm;
+
+	if (pUsbProperty->UsbInterfaceType ==
+		NvOdmUsbInterfaceType_UlpiNullPhy) {
+		/* query the modem control pins */
+		if (ste_u3xx_query(&ste_u3xx_info) < 0)
+			goto ExitUlpiOdm;
+
+		NvOsDebugPrintf("turn modem on\n");
+		ste_u3xx_turn_on_modem(&ste_u3xx_info);
+	}
+	return pDevice;
+
+ExitUlpiOdm:
+	if (pDevice)
+		NvOdmOsFree(pDevice);
+	return NULL;
+}
+
+void NvOdmUsbUlpiClose(NvOdmUsbUlpiHandle hOdmUlpi)
+{
+	if (hOdmUlpi) {
+		NvOdmOsFree(hOdmUlpi);
+		hOdmUlpi = NULL;
+	}
+}
diff --git a/arch/arm/mach-tegra/odm_kit/adaptations/pmu/Makefile b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/Makefile
new file mode 100644
index 000000000000..b19449bd3cfa
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/Makefile
@@ -0,0 +1,18 @@
+ccflags-y += -DNV_IS_AVP=0
+ccflags-y += -DNV_OAL=0
+ccflags-y += -DNV_USE_FUSE_CLOCK_ENABLE=0
+ifeq ($(CONFIG_MACH_TEGRA_GENERIC_DEBUG),y)
+ccflags-y += -DNV_DEBUG=1
+else
+ccflags-y += -DNV_DEBUG=0
+endif
+
+ccflags-y += -Iarch/arm/mach-tegra/odm_kit/adaptations/pmu
+ccflags-y += -Iarch/arm/mach-tegra/odm_kit/adaptations/pmu/max8907b
+ccflags-y += -Iarch/arm/mach-tegra/odm_kit/adaptations/pmu/pcf50626
+ccflags-y += -Iarch/arm/mach-tegra/odm_kit/adaptations/pmu/tps6586x
+
+obj-y += pmu_hal.o
+obj-y += max8907b/
+obj-y += pcf50626/
+obj-y += tps6586x/
diff --git a/arch/arm/mach-tegra/odm_kit/adaptations/pmu/max8907b/Makefile b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/max8907b/Makefile
new file mode 100644
index 000000000000..321377d9317f
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/max8907b/Makefile
@@ -0,0 +1,22 @@
+ccflags-y += -DNV_IS_AVP=0
+ccflags-y += -DNV_OAL=0
+ccflags-y += -DNV_USE_FUSE_CLOCK_ENABLE=0
+ifeq ($(CONFIG_MACH_TEGRA_GENERIC_DEBUG),y)
+ccflags-y += -DNV_DEBUG=1
+else
+ccflags-y += -DNV_DEBUG=0
+endif
+
+ccflags-y += -Iarch/arm/mach-tegra/odm_kit/adaptations/pmu
+ccflags-y += -Iarch/arm/mach-tegra/odm_kit/adaptations/pmu/max8907b
+
+obj-y += ad5258_dpm.o
+obj-y += fan5355_buck_i2c.o
+obj-y += max8907b_adc.o
+obj-y += max8907b_batterycharger.o
+obj-y += max8907b.o
+obj-y += max8907b_i2c.o
+obj-y += max8907b_interrupt.o
+obj-y += max8907b_rtc.o
+obj-y += mic2826_i2c.o
+obj-y += tca6416_expander_i2c.o
diff --git a/arch/arm/mach-tegra/odm_kit/adaptations/pmu/max8907b/ad5258_dpm.c b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/max8907b/ad5258_dpm.c
new file mode 100644
index 000000000000..7f785f920afc
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/max8907b/ad5258_dpm.c
@@ -0,0 +1,193 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include "nvodm_pmu.h"
+#include "nvodm_services.h"
+#include "ad5258_dpm.h"
+
+
+static NvBool
+Ad5258I2cWrite8(
+    NvOdmPmuDeviceHandle hDevice,
+    NvU8 Addr,
+    NvU8 Data)
+{
+    NvU32 i;
+    NvU8 WriteBuffer[2];
+    NvOdmI2cTransactionInfo TransactionInfo;
+    NvOdmI2cStatus status = NvOdmI2cStatus_Success;    
+    Max8907bPrivData *hPmu = (Max8907bPrivData*)hDevice->pPrivate;
+
+    for (i = 0; i < AD5258_I2C_RETRY_CNT; i++)
+    {
+        WriteBuffer[0] = Addr & 0xFF;   // AD5258 address
+        WriteBuffer[1] = Data & 0xFF;   // written data
+
+        TransactionInfo.Address = AD5258_SLAVE_ADDR;
+        TransactionInfo.Buf = &WriteBuffer[0];
+        TransactionInfo.Flags = NVODM_I2C_IS_WRITE;
+        TransactionInfo.NumBytes = 2;
+
+        status = NvOdmI2cTransaction(hPmu->hOdmI2C, &TransactionInfo, 1,
+            AD5258_I2C_SPEED_KHZ, AD5258_I2C_TIMEOUT_MS);
+        if (status == NvOdmI2cStatus_Success)
+            return NV_TRUE;
+    }
+
+    // Transaction Error
+    switch (status)
+    {
+        case NvOdmI2cStatus_Timeout:
+            NVODMPMU_PRINTF(("NvOdmDpmI2cWrite8 Failed: Timeout\n")); 
+            break;
+         case NvOdmI2cStatus_SlaveNotFound:
+         default:
+            NVODMPMU_PRINTF(("NvOdmDpmI2cWrite8 Failed: SlaveNotFound\n"));
+            break;             
+    }
+    return NV_FALSE;
+}
+
+static NvBool
+Ad5258I2cRead8(
+    NvOdmPmuDeviceHandle hDevice,
+    NvU8 Addr,
+    NvU8 *Data)
+{
+    NvU32 i;
+    NvU8 ReadBuffer = 0;
+    NvOdmI2cStatus  status = NvOdmI2cStatus_Success;    
+    Max8907bPrivData *hPmu = (Max8907bPrivData*)hDevice->pPrivate;
+    NvOdmI2cTransactionInfo TransactionInfo[2];
+
+    for (i = 0; i < AD5258_I2C_RETRY_CNT; i++)
+    {
+        // The AD5258 register address
+        ReadBuffer = Addr & 0xFF;
+
+        TransactionInfo[0].Address = AD5258_SLAVE_ADDR;
+        TransactionInfo[0].Buf = &ReadBuffer;
+        TransactionInfo[0].Flags = NVODM_I2C_IS_WRITE;
+        TransactionInfo[0].NumBytes = 1;
+
+        TransactionInfo[1].Address = (AD5258_SLAVE_ADDR | 0x1);;
+        TransactionInfo[1].Buf = &ReadBuffer;
+        TransactionInfo[1].Flags = 0;
+        TransactionInfo[1].NumBytes = 1;
+
+        // Read data from PMU at the specified offset
+        status = NvOdmI2cTransaction(hPmu->hOdmI2C, &TransactionInfo[0], 2, 
+                                     AD5258_I2C_SPEED_KHZ, AD5258_I2C_TIMEOUT_MS);
+        if (status == NvOdmI2cStatus_Success)
+        {
+            *Data = ReadBuffer;
+            return NV_TRUE;
+        }
+    }
+
+    // Transaction Error
+    switch (status)
+    {
+        case NvOdmI2cStatus_Timeout:
+            NVODMPMU_PRINTF(("NvOdmDpmI2cRead8 Failed: Timeout\n")); 
+            break;
+         case NvOdmI2cStatus_SlaveNotFound:
+         default:
+            NVODMPMU_PRINTF(("NvOdmDpmI2cRead8 Failed: SlaveNotFound\n"));
+            break;             
+    }
+    return NV_FALSE;
+}
+
+NvBool 
+Ad5258I2cSetVoltage(
+    NvOdmPmuDeviceHandle hDevice, 
+    NvU32 MilliVolts)
+{
+    static NvU32 s_LastMilliVolts = 0;
+
+    NvU8 Data = 0;
+    NvU8 Addr = AD5258_RDAC_ADDR;
+
+    if (s_LastMilliVolts == 0)
+    {
+        if (!Ad5258I2cGetVoltage(hDevice, &s_LastMilliVolts))
+            return NV_FALSE;
+        NV_ASSERT((s_LastMilliVolts >= AD5258_V0) &&
+                  (s_LastMilliVolts <= AD5258_VMAX));
+    }
+
+    // Change voltage level one maximum allowed step at a time
+    while (s_LastMilliVolts != MilliVolts)
+    {
+        if (MilliVolts > s_LastMilliVolts + AD5258_MAX_STEP_MV)
+            s_LastMilliVolts += AD5258_MAX_STEP_MV;
+        else if (MilliVolts + AD5258_MAX_STEP_MV < s_LastMilliVolts)
+            s_LastMilliVolts -= AD5258_MAX_STEP_MV;
+        else
+            s_LastMilliVolts = MilliVolts;
+
+        // D(Vout) = (Vout - V0) * M1 / 2^b
+        Data = 0;
+        if (s_LastMilliVolts > AD5258_V0)
+        {
+            Data = (NvU8)(((s_LastMilliVolts - AD5258_V0) * AD5258_M1 +
+                           (0x1 << (AD5258_b - 1))) >> AD5258_b);
+            Data++; // account for load
+        }
+        NV_ASSERT(Data <= AD5258_RDAC_MASK);
+        if (!Ad5258I2cWrite8(hDevice, Addr, Data))
+            return NV_FALSE;
+        NvOdmOsWaitUS(AD5258_MAX_STEP_SETTLE_TIME_US);
+    }
+    return NV_TRUE;
+}
+
+NvBool 
+Ad5258I2cGetVoltage(
+    NvOdmPmuDeviceHandle hDevice, 
+    NvU32* pMilliVolts)
+{
+    NvU8 Data = 0;
+    NvU8 Addr = AD5258_RDAC_ADDR;
+
+    if (!Ad5258I2cRead8(hDevice, Addr, &Data))
+        return NV_FALSE;
+
+    // Vout(D) = V0 + (D * M2) / 2^b
+    Data &= AD5258_RDAC_MASK;
+    *pMilliVolts = AD5258_V0 +
+        (((NvU32)Data * AD5258_M2 + (0x1 << (AD5258_b - 1))) >> AD5258_b);
+
+    return NV_TRUE;
+}
+
diff --git a/arch/arm/mach-tegra/odm_kit/adaptations/pmu/max8907b/ad5258_dpm.h b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/max8907b/ad5258_dpm.h
new file mode 100644
index 000000000000..8bfd23eecf59
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/max8907b/ad5258_dpm.h
@@ -0,0 +1,92 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_AD5258_DPM_I2C_H
+#define INCLUDED_AD5258_DPM_I2C_H
+
+#include "nvodm_pmu.h"
+#include "max8907b.h"
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+#define AD5258_SLAVE_ADDR       (0x9C)    // (7'h4E)
+#define AD5258_I2C_SPEED_KHZ    (400)
+#define AD5258_I2C_RETRY_CNT    (2)
+#define AD5258_I2C_TIMEOUT_MS   (1000)
+
+#define AD5258_RDAC_ADDR        (0x0)
+#define AD5258_RDAC_MASK        (0x3F)
+
+/*
+ * Linear approximation of digital potentiometer (DPM) scaling ladder:
+ * D(Vout) = (Vout - V0) * M1 / 2^b
+ * Vout(D) = V0 + (D * M2) / 2^b
+ * D - DPM setting, Vout - output voltage in mV, b - fixed point calculation
+ * precision, approximation parameters V0, M1, M2 are determined for the
+ * particular schematic combining constant resistors, DPM, and DCDC supply.
+ */
+// On Whistler:
+#define AD5258_V0   (815)
+#define AD5258_M1   (229)        
+#define AD5258_M2   (4571)
+#define AD5258_b    (10)
+
+#define AD5258_VMAX (AD5258_V0 + ((AD5258_RDAC_MASK * AD5258_M2 + \
+                     (0x1 << (AD5258_b - 1))) >> AD5258_b))
+
+// Minimum voltage step is determined by DPM resolution, maximum voltage step
+// is limited to keep dynamic over/under shoot within +/- 50mV
+#define AD5258_MIN_STEP_MV ((AD5258_M2 + (0x1 << AD5258_b) - 1) >> AD5258_b)
+#define AD5258_MAX_STEP_MV (50)
+#define AD5258_MAX_STEP_SETTLE_TIME_US (20)
+#define AD5258_TURN_ON_TIME_US (2000)
+
+NvBool 
+Ad5258I2cSetVoltage(
+    NvOdmPmuDeviceHandle hDevice, 
+    NvU32 MilliVolts);
+
+NvBool 
+Ad5258I2cGetVoltage(
+    NvOdmPmuDeviceHandle hDevice, 
+    NvU32* pMilliVolts);
+
+#if defined(__cplusplus)
+}
+#endif
+
+/** @} */
+
+#endif // INCLUDED_AD5258_DPM_I2C_H
diff --git a/arch/arm/mach-tegra/odm_kit/adaptations/pmu/max8907b/fan5355_buck_i2c.c b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/max8907b/fan5355_buck_i2c.c
new file mode 100644
index 000000000000..bb00b0bbab1f
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/max8907b/fan5355_buck_i2c.c
@@ -0,0 +1,123 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include "nvodm_pmu.h"
+#include "nvodm_services.h"
+#include "fan5355_buck_i2c.h"
+#include "fan5355_buck_reg.h"
+
+// Function declaration
+NvBool Fan5355I2cWrite8(
+    NvOdmPmuDeviceHandle hDevice,
+    NvU8 Addr,
+    NvU8 Data)
+{
+    NvU8 WriteBuffer[2];
+    NvOdmI2cTransactionInfo TransactionInfo;
+    NvOdmI2cStatus status = NvOdmI2cStatus_Success;    
+    Max8907bPrivData *hPmu = (Max8907bPrivData*)hDevice->pPrivate;
+
+    WriteBuffer[0] = Addr & 0xFF;   // PMU offset
+    WriteBuffer[1] = Data & 0xFF;   // written data
+
+    TransactionInfo.Address = FAN5335_SLAVE_ADDR;
+    TransactionInfo.Buf = &WriteBuffer[0];
+    TransactionInfo.Flags = NVODM_I2C_IS_WRITE;
+    TransactionInfo.NumBytes = 2;
+
+    status = NvOdmI2cTransaction(hPmu->hOdmI2C, &TransactionInfo, 1,
+                                 FAN5335_I2C_SPEED_KHZ, NV_WAIT_INFINITE);
+    if (status == NvOdmI2cStatus_Success)
+    {
+        return NV_TRUE;
+    }
+    else
+    {
+        switch (status)
+        {
+            case NvOdmI2cStatus_Timeout:
+                NVODMPMU_PRINTF(("NvOdmPmuI2cWrite8 Failed: Timeout\n")); 
+                break;
+             case NvOdmI2cStatus_SlaveNotFound:
+             default:
+                NVODMPMU_PRINTF(("NvOdmPmuI2cWrite8 Failed: SlaveNotFound\n"));
+                break;             
+        }
+    return NV_FALSE;
+    }    
+}
+
+NvBool Fan5355I2cRead8(
+    NvOdmPmuDeviceHandle hDevice,
+    NvU8 Addr,
+    NvU8 *Data)
+{
+    NvU8 ReadBuffer = 0;
+    NvOdmI2cStatus  status = NvOdmI2cStatus_Success;    
+    Max8907bPrivData *hPmu = (Max8907bPrivData*)hDevice->pPrivate;
+    NvOdmI2cTransactionInfo TransactionInfo[2];
+
+    // Write the PMU offset
+    ReadBuffer = Addr & 0xFF;
+
+    TransactionInfo[0].Address = FAN5335_SLAVE_ADDR;
+    TransactionInfo[0].Buf = &ReadBuffer;
+    TransactionInfo[0].Flags = NVODM_I2C_IS_WRITE;
+    TransactionInfo[0].NumBytes = 1;
+
+    TransactionInfo[1].Address = (FAN5335_SLAVE_ADDR | 0x1);;
+    TransactionInfo[1].Buf = &ReadBuffer;
+    TransactionInfo[1].Flags = 0;
+    TransactionInfo[1].NumBytes = 1;
+
+    // Read data from PMU at the specified offset
+    status = NvOdmI2cTransaction(hPmu->hOdmI2C, &TransactionInfo[0], 2, 
+                                 FAN5335_I2C_SPEED_KHZ, NV_WAIT_INFINITE);
+    if (status != NvOdmI2cStatus_Success)
+    {
+        switch (status)
+        {
+            case NvOdmI2cStatus_Timeout:
+                NVODMPMU_PRINTF(("NvOdmPmuI2cRead8 Failed: Timeout\n")); 
+                break;
+             case NvOdmI2cStatus_SlaveNotFound:
+             default:
+                NVODMPMU_PRINTF(("NvOdmPmuI2cRead8 Failed: SlaveNotFound\n"));
+                break;             
+        }
+        return NV_FALSE;
+    }  
+
+    *Data = ReadBuffer;
+    return NV_TRUE;
+}
+
diff --git a/arch/arm/mach-tegra/odm_kit/adaptations/pmu/max8907b/fan5355_buck_i2c.h b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/max8907b/fan5355_buck_i2c.h
new file mode 100644
index 000000000000..7df90a192769
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/max8907b/fan5355_buck_i2c.h
@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_FAN5355_BUCK_I2C_H
+#define INCLUDED_FAN5355_BUCK_I2C_H
+
+#include "nvodm_pmu.h"
+#include "max8907b.h"
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+#define FAN5335_SLAVE_ADDR      0x94    // (7'h4A)
+#define FAN5335_I2C_SPEED_KHZ   400
+
+NvBool Fan5355I2cWrite8(
+    NvOdmPmuDeviceHandle hDevice,
+    NvU8 Addr,
+    NvU8 Data);
+
+NvBool Fan5355I2cRead8(
+    NvOdmPmuDeviceHandle hDevice,
+    NvU8 Addr,
+    NvU8 *Data);
+
+#if defined(__cplusplus)
+}
+#endif
+
+/** @} */
+
+#endif // INCLUDED_FAN5355_BUCK_I2C_H
diff --git a/arch/arm/mach-tegra/odm_kit/adaptations/pmu/max8907b/fan5355_buck_reg.h b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/max8907b/fan5355_buck_reg.h
new file mode 100644
index 000000000000..104be89ac462
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/max8907b/fan5355_buck_reg.h
@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+ 
+#ifndef INCLUDED_FAN5355_BUCK_REG_HEADER
+#define INCLUDED_FAN5355_BUCK_REG_HEADER
+
+// Registers
+
+/* field defines for register bit ops */
+
+#define FAN5335_VSEL0       0x0
+#define FAN5335_VSEL1       0x1
+#define FAN5335_CONTROL1    0x2
+#define FAN5335_CONTROL2    0x3
+
+#define FAN5335_REG_INVALID 0xFF
+
+#endif //INCLUDED_FAN5355_BUCK_REG_HEADER
+
diff --git a/arch/arm/mach-tegra/odm_kit/adaptations/pmu/max8907b/max8907b.c b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/max8907b/max8907b.c
new file mode 100644
index 000000000000..285044034f97
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/max8907b/max8907b.c
@@ -0,0 +1,2324 @@
+/*
+ * Copyright (c) 2007-2010 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include "nvodm_query_discovery.h"
+#include "nvodm_query.h"
+#include "nvodm_services.h"
+#include "max8907b.h"
+#include "max8907b_reg.h"
+#include "max8907b_adc.h"
+#include "max8907b_i2c.h"
+#include "max8907b_interrupt.h"
+#include "max8907b_batterycharger.h"
+#include "max8907b_supply_info_table.h"
+#include "fan5355_buck_reg.h"
+#include "fan5355_buck_i2c.h"
+#include "tca6416_expander_reg.h"
+#include "tca6416_expander_i2c.h"
+#include "mic2826_reg.h"
+#include "mic2826_i2c.h"
+#include "ad5258_dpm.h"
+
+// Private PMU context info
+Max8907bPrivData *hMax8907bPmu;
+
+#define PMUGUID NV_ODM_GUID('m','a','x','8','9','0','7','b')
+
+#define MAX_CHARGER_LIMIT_MA    1000
+
+#define ALWAYS_ONLINE (1)
+
+/**
+ * MAX8907B regulators can be enabled/disabled via s/w I2C commands only
+ * when MAX8907B_SEQSEL_I2CEN_LXX (7) is selected as regulator sequencer.
+ * Otherwise, regulator is controlled by h/w sequencers: SEQ1 (SYSEN),
+ * which is always On when PMU is On, or SEQ2 (PWREN) which is always On,
+ * when system is running (it is Off in LPx mode only).
+ */
+#define MAX8907B_OUT_VOLTAGE_CONTROL_MASK \
+    ((MAX8907B_CTL_SEQ_MASK << MAX8907B_CTL_SEQ_SHIFT) | \
+     MAX8907B_OUT_VOLTAGE_ENABLE_BIT)
+
+#define MAX8907B_OUT_VOLTAGE_CONTROL_DISABLE \
+    (MAX8907B_SEQSEL_I2CEN_LXX << MAX8907B_CTL_SEQ_SHIFT)
+
+// MAX8907B revision that requires s/w WAR to connect PWREN input to
+// sequencer 2 because of the bug in the silicon.
+#define MAX8907B_II2RR_PWREN_WAR (0x12)
+
+/**
+*   The FAN5355 is used to scale the voltage of an external
+*   DC/DC voltage rail (for PCIE).  However, voltage scaling is
+*   not required for this source, since the 1.05V default
+*   voltage when enabled is OK.  On some boards, the FAN5355 may
+*   not function properly, as an I2C re-work may be required
+*   (otherwise, the slave address may not be found).  Therefore,
+*   this feature is disabled by default.
+*/
+#undef MAX8907B_USE_FAN5355_VOLTAGE_SCALING
+
+/*-- Output Voltage tables --*/
+
+// V1, V2 (millivolts x 10)
+static const NvU32 VoltageTable_SD_A[] = {
+     6375,  6500,  6625,  6750,  6875,  7000,  7125,  7250,
+     7375,  7500,  7625,  7750,  7875,  8000,  8125,  8250,
+     8375,  8500,  8625,  8750,  8875,  9000,  9125,  9250,
+     9375,  9500,  9625,  9750,  9875, 10000, 10125, 10250,
+    10375, 10500, 10625, 10750, 10875, 11000, 11125, 11250,
+    11375, 11500, 11625, 11750, 11875, 12000, 12125, 12250,
+    12375, 12500, 12625, 12750, 12875, 13000, 13125, 13250,
+    13375, 13500, 13625, 13750, 13875, 14000, 14125, 14250
+};
+
+// V3, LDO1, LDO4-LDO16, LDO19-20 (millivolts)
+static const NvU32 VoltageTable_SD_B_LDO_B[] = {
+     750,  800,  850,  900,  950, 1000, 1050, 1100,
+    1150, 1200, 1250, 1300, 1350, 1400, 1450, 1500,
+    1550, 1600, 1650, 1700, 1750, 1800, 1850, 1900,
+    1950, 2000, 2050, 2100, 2150, 2200, 2250, 2300,
+    2350, 2400, 2450, 2500, 2550, 2600, 2650, 2700,
+    2750, 2800, 2850, 2900, 2950, 3000, 3050, 3100,
+    3150, 3200, 3250, 3300, 3350, 3400, 3450, 3500,
+    3550, 3600, 3650, 3700, 3750, 3800, 3850, 3900
+};
+
+// LDO2, LDO3, LDO17, LDO18 (millivolts)
+static const NvU32 VoltageTable_LDO_A[] = {
+     650,  675,  700,  725,  750,  775,  800,  825,
+     850,  875,  900,  925,  950,  975, 1000, 1025,
+    1050, 1075, 1100, 1125, 1150, 1175, 1200, 1225,
+    1250, 1275, 1300, 1325, 1350, 1375, 1400, 1425,
+    1450, 1475, 1500, 1525, 1550, 1575, 1600, 1625,
+    1650, 1675, 1700, 1725, 1750, 1775, 1800, 1825,
+    1850, 1875, 1900, 1925, 1950, 1975, 2000, 2025,
+    2050, 2075, 2100, 2125, 2150, 2175, 2200, 2225
+};
+
+// FAN5355 VOUT_02 (millivolts x 10)
+static const NvU32 VoltageTable_VOUT_02[] = {
+     7500,  7625,  7750,  7875,  8000,  8125,  8250,  8375,
+     8500,  8625,  8750,  8875,  9000,  9125,  9250,  9375,
+     9500,  9625,  9750,  9875, 10000, 10125, 10250, 10375,
+    10500, 10625, 10750, 10875, 11000, 11125, 11250, 11375,
+    11500, 11625, 11750, 11875, 12000, 12125, 12250, 12375,
+    12500, 12625, 12750, 12875, 13000, 13125, 13250, 13375,
+    13500, 13625, 13750, 13875, 14000, 14125, 14250, 14375,
+};
+
+/*-- Sequencer table --*/
+
+// Timer period, microseconds (us).
+// Specifies the time between each sequencer event.
+
+// Disable temporarily to keep the compiler happy.
+//static const NvU32 SequencerPeriod[] = { 20, 40, 80, 160, 320, 640, 1280, 2560 };
+
+/*-- Voltage translation functions --*/
+
+// OutVoltageIndex is the lower six bits of the output voltage registers, VO[5:0]
+static NvU32 Max8907bPmuVoltageGet_SD_A(const NvU32 OutVoltageIndex);
+static NvU32 Max8907bPmuVoltageGet_SD_B_LDO_B(const NvU32 OutVoltageIndex);
+static NvU32 Max8907bPmuVoltageGet_LDO_A(const NvU32 OutVoltageIndex);
+
+static NvU32 Max8907bPmuVoltageSet_SD_A(const NvU32 OutMilliVolts);
+static NvU32 Max8907bPmuVoltageSet_SD_B_LDO_B(const NvU32 OutMilliVolts);
+static NvU32 Max8907bPmuVoltageSet_LDO_A(const NvU32 OutMilliVolts);
+
+#define MAX8907B_MAX_OUTPUT_VOLTAGE_INDEX   0x3F
+#define FAN5355_MAX_OUTPUT_VOLTAGE_INDEX    0x37
+
+static NvU32 Max8907bPmuVoltageGet_SD_A(const NvU32 OutVoltageIndex)
+{
+    NV_ASSERT(OutVoltageIndex <= MAX8907B_MAX_OUTPUT_VOLTAGE_INDEX);
+    return VoltageTable_SD_A[OutVoltageIndex]/10;
+}
+
+static NvU32 Max8907bPmuVoltageGet_SD_B_LDO_B(const NvU32 OutVoltageIndex)
+{
+    NV_ASSERT(OutVoltageIndex <= MAX8907B_MAX_OUTPUT_VOLTAGE_INDEX);
+    return VoltageTable_SD_B_LDO_B[OutVoltageIndex];
+}
+
+static NvU32 Max8907bPmuVoltageGet_LDO_A(const NvU32 OutVoltageIndex)
+{
+    NV_ASSERT(OutVoltageIndex <= MAX8907B_MAX_OUTPUT_VOLTAGE_INDEX);
+    return VoltageTable_LDO_A[OutVoltageIndex];
+}
+
+// Secondary PMU MIC2826 API
+static NvBool MIC2826ReadVoltageReg(NvOdmPmuDeviceHandle hDevice,
+                 NvU32 vddRail, NvU32* pMilliVolts);
+
+static NvBool MIC2826WriteVoltageReg( NvOdmPmuDeviceHandle hDevice,
+                 NvU32 vddRail, NvU32  MilliVolts, NvU32* pSettleMicroSeconds);
+
+const NvU8 MIC2826_BUCK_Votage_Table[] =
+{
+   MIC2826_BUCK_OUT_VOLTAGE_0800,
+   MIC2826_BUCK_OUT_VOLTAGE_0825,
+   MIC2826_BUCK_OUT_VOLTAGE_0850,
+   MIC2826_BUCK_OUT_VOLTAGE_0875,
+   MIC2826_BUCK_OUT_VOLTAGE_0900,
+   MIC2826_BUCK_OUT_VOLTAGE_0925,
+   MIC2826_BUCK_OUT_VOLTAGE_0950,
+   MIC2826_BUCK_OUT_VOLTAGE_0975,
+   MIC2826_BUCK_OUT_VOLTAGE_1000,
+   MIC2826_BUCK_OUT_VOLTAGE_1025,
+   MIC2826_BUCK_OUT_VOLTAGE_1050,
+   MIC2826_BUCK_OUT_VOLTAGE_1075,
+   MIC2826_BUCK_OUT_VOLTAGE_1100,
+   MIC2826_BUCK_OUT_VOLTAGE_1125,
+   MIC2826_BUCK_OUT_VOLTAGE_1150,
+   MIC2826_BUCK_OUT_VOLTAGE_1175,
+   MIC2826_BUCK_OUT_VOLTAGE_1200,
+   MIC2826_BUCK_OUT_VOLTAGE_1250,
+   MIC2826_BUCK_OUT_VOLTAGE_1300,
+   MIC2826_BUCK_OUT_VOLTAGE_1350,
+   MIC2826_BUCK_OUT_VOLTAGE_1400,
+   MIC2826_BUCK_OUT_VOLTAGE_1450,
+   MIC2826_BUCK_OUT_VOLTAGE_1500,
+   MIC2826_BUCK_OUT_VOLTAGE_1550,
+   MIC2826_BUCK_OUT_VOLTAGE_1600,
+   MIC2826_BUCK_OUT_VOLTAGE_1650,
+   MIC2826_BUCK_OUT_VOLTAGE_1700,
+   MIC2826_BUCK_OUT_VOLTAGE_1750,
+   MIC2826_BUCK_OUT_VOLTAGE_1800
+};
+
+const NvU8 MIC2826_LDO_Votage_Table[] =
+{
+   MIC2826_LDO_OUT_VOLTAGE_0800,
+   MIC2826_LDO_OUT_VOLTAGE_0850,
+   MIC2826_LDO_OUT_VOLTAGE_0900,
+   MIC2826_LDO_OUT_VOLTAGE_0950,
+   MIC2826_LDO_OUT_VOLTAGE_1000,
+   MIC2826_LDO_OUT_VOLTAGE_1050,
+   MIC2826_LDO_OUT_VOLTAGE_1100,
+   MIC2826_LDO_OUT_VOLTAGE_1150,
+   MIC2826_LDO_OUT_VOLTAGE_1200,
+   MIC2826_LDO_OUT_VOLTAGE_1250,
+   MIC2826_LDO_OUT_VOLTAGE_1300,
+   MIC2826_LDO_OUT_VOLTAGE_1350,
+   MIC2826_LDO_OUT_VOLTAGE_1400,
+   MIC2826_LDO_OUT_VOLTAGE_1450,
+   MIC2826_LDO_OUT_VOLTAGE_1500,
+   MIC2826_LDO_OUT_VOLTAGE_1550,
+   MIC2826_LDO_OUT_VOLTAGE_1600,
+   MIC2826_LDO_OUT_VOLTAGE_1650,
+   MIC2826_LDO_OUT_VOLTAGE_1700,
+   MIC2826_LDO_OUT_VOLTAGE_1750,
+   MIC2826_LDO_OUT_VOLTAGE_1800,
+   MIC2826_LDO_OUT_VOLTAGE_1850,
+   MIC2826_LDO_OUT_VOLTAGE_1900,
+   MIC2826_LDO_OUT_VOLTAGE_1950,
+   MIC2826_LDO_OUT_VOLTAGE_2000,
+   MIC2826_LDO_OUT_VOLTAGE_2050,
+   MIC2826_LDO_OUT_VOLTAGE_2100,
+   MIC2826_LDO_OUT_VOLTAGE_2150,
+   MIC2826_LDO_OUT_VOLTAGE_2200,
+   MIC2826_LDO_OUT_VOLTAGE_2250,
+   MIC2826_LDO_OUT_VOLTAGE_2300,
+   MIC2826_LDO_OUT_VOLTAGE_2350,
+   MIC2826_LDO_OUT_VOLTAGE_2400,
+   MIC2826_LDO_OUT_VOLTAGE_2450,
+   MIC2826_LDO_OUT_VOLTAGE_2500,
+   MIC2826_LDO_OUT_VOLTAGE_2550,
+   MIC2826_LDO_OUT_VOLTAGE_2600,
+   MIC2826_LDO_OUT_VOLTAGE_2650,
+   MIC2826_LDO_OUT_VOLTAGE_2700,
+   MIC2826_LDO_OUT_VOLTAGE_2750,
+   MIC2826_LDO_OUT_VOLTAGE_2800,
+   MIC2826_LDO_OUT_VOLTAGE_2850,
+   MIC2826_LDO_OUT_VOLTAGE_2900,
+   MIC2826_LDO_OUT_VOLTAGE_2950,
+   MIC2826_LDO_OUT_VOLTAGE_3000,
+   MIC2826_LDO_OUT_VOLTAGE_3050,
+   MIC2826_LDO_OUT_VOLTAGE_3100,
+   MIC2826_LDO_OUT_VOLTAGE_3150,
+   MIC2826_LDO_OUT_VOLTAGE_3200,
+   MIC2826_LDO_OUT_VOLTAGE_3250,
+   MIC2826_LDO_OUT_VOLTAGE_3300
+};
+
+#define MIC2826_BUCK_Votage_Table_Size NV_ARRAY_SIZE(MIC2826_BUCK_Votage_Table)
+#define MIC2826_LDO_Votage_Table_Size  NV_ARRAY_SIZE(MIC2826_LDO_Votage_Table)
+
+#ifndef MIN
+#define MIN(a, b)   (a) <= (b) ? (a) : (b)
+#endif
+
+#define MAX8907B_MIN_OUTPUT_VOLTAGE_SD_A_x10          6375  // 637.5 mV
+#define MAX8907B_MIN_OUTPUT_VOLTAGE_SD_B_LDO_B        750   // 750 mV
+#define MAX8907B_MIN_OUTPUT_VOLTAGE_LDO_A             650   // 650 mV
+#define FAN5355_MIN_OUTPUT_VOLTAGE_x10                7500  // 750.0 mV
+
+#define MAX8907B_OUTPUT_VOLTAGE_INCREMENT_SD_A_x10     125  // 12.5 mV
+#define MAX8907B_OUTPUT_VOLTAGE_INCREMENT_SD_B_LDO_B   50   // 50 mV
+#define MAX8907B_OUTPUT_VOLTAGE_INCREMENT_LDO_A        25   // 25 mV
+#define FAN5355_OUTPUT_VOLTAGE_INCREMENT_x10           125  // 12.5 mV
+
+#define MAX8907B_MAX_OUTPUT_VOLTAGE_SD_A_x10         14250  // 1,425.0 mV
+#define MAX8907B_MAX_OUTPUT_VOLTAGE_SD_B_LDO_B       3900   // 3,900 mV
+#define MAX8907B_MAX_OUTPUT_VOLTAGE_LDO_A            2225   // 2,225 mV
+#define FAN5355_MAX_OUTPUT_VOLTAGE_x10               14375  // 1,437.5 mV
+
+#define MAX8907B_MIN_OUTPUT_VOLTAGE_RTC                 0   // 0 mV
+#define MAX8907B_OUTPUT_VOLTAGE_INCREMENT_RTC           1   // Protected; use dummy, non-zero value
+//#define MAX8907B_MAX_OUTPUT_VOLTAGE_RTC              3300   // 3,300 mV
+// WHISTLER/AP16 - Make this 1.2V for now, since ap15rm_power.c expects it that way.
+#define MAX8907B_MAX_OUTPUT_VOLTAGE_RTC              1200
+
+static NvU32 Max8907bPmuVoltageSet_SD_A(const NvU32 OutMilliVolts)
+{
+    if (OutMilliVolts < MAX8907B_MIN_OUTPUT_VOLTAGE_SD_A_x10/10)
+        return 0;
+    else
+        return MIN(                                                 \
+            (OutMilliVolts*10 - MAX8907B_MIN_OUTPUT_VOLTAGE_SD_A_x10) /    \
+            MAX8907B_OUTPUT_VOLTAGE_INCREMENT_SD_A_x10,                 \
+            MAX8907B_MAX_OUTPUT_VOLTAGE_INDEX);
+}
+
+static NvU32 Max8907bPmuVoltageSet_SD_B_LDO_B(const NvU32 OutMilliVolts)
+{
+    if (OutMilliVolts < MAX8907B_MIN_OUTPUT_VOLTAGE_SD_B_LDO_B)
+        return 0;
+    else
+        return MIN(                                                     \
+            (OutMilliVolts - MAX8907B_MIN_OUTPUT_VOLTAGE_SD_B_LDO_B) /  \
+            MAX8907B_OUTPUT_VOLTAGE_INCREMENT_SD_B_LDO_B,               \
+            MAX8907B_MAX_OUTPUT_VOLTAGE_INDEX);
+}
+
+static NvU32 Max8907bPmuVoltageSet_LDO_A(const NvU32 OutMilliVolts)
+{
+    if (OutMilliVolts < MAX8907B_MIN_OUTPUT_VOLTAGE_LDO_A)
+        return 0;
+    else
+        return MIN(                                                 \
+            (OutMilliVolts - MAX8907B_MIN_OUTPUT_VOLTAGE_LDO_A) /   \
+            MAX8907B_OUTPUT_VOLTAGE_INCREMENT_LDO_A,                \
+            MAX8907B_MAX_OUTPUT_VOLTAGE_INDEX);
+}
+
+static NvU32 Fan5355PmuVoltageGet_VOUT_02(const NvU32 OutVoltageIndex)
+{
+    NV_ASSERT(OutVoltageIndex <= FAN5355_MAX_OUTPUT_VOLTAGE_INDEX);
+    return VoltageTable_VOUT_02[OutVoltageIndex]/10;
+}
+
+static NvU32 Fan5355PmuVoltageSet_VOUT_02(const NvU32 OutMilliVolts)
+{
+    if (OutMilliVolts < FAN5355_MIN_OUTPUT_VOLTAGE_x10/10)
+        return 0;
+    else
+        return MIN(                                                 \
+            (OutMilliVolts*10 - FAN5355_MIN_OUTPUT_VOLTAGE_x10) /   \
+            FAN5355_OUTPUT_VOLTAGE_INCREMENT_x10,                   \
+            FAN5355_MAX_OUTPUT_VOLTAGE_x10);
+}
+
+// This board-specific table is indexed by Max8907bPmuSupply
+const Max8907bPmuSupplyInfo Max8907bSupplyInfoTable[] =
+{
+    {
+        Max8907bPmuSupply_Invalid,
+        MAX8907B_REG_INVALID,
+        MAX8907B_REG_INVALID,
+        MAX8907B_REG_INVALID,
+        TCA6416_INVALID_PORT,
+        TCA6416_INVALID_PORT,
+        NULL,
+        NULL,
+        {NV_TRUE, 0, 0, 0, 0},
+    },
+
+    // LX_V1 (V1)
+    {
+        Max8907bPmuSupply_LX_V1,
+        MAX8907B_SDCTL1,
+        MAX8907B_SDSEQCNT1,
+        MAX8907B_SDV1,
+        TCA6416_INVALID_PORT,
+        TCA6416_INVALID_PORT,
+        Max8907bPmuVoltageGet_SD_A,
+        Max8907bPmuVoltageSet_SD_A,
+        {
+            NV_FALSE,
+            MAX8907B_MIN_OUTPUT_VOLTAGE_SD_A_x10/10,
+            MAX8907B_OUTPUT_VOLTAGE_INCREMENT_SD_A_x10/10,
+            MAX8907B_MAX_OUTPUT_VOLTAGE_SD_A_x10/10,
+            MAX8907B_REQUESTVOLTAGE_LX_V1
+        },
+    },
+
+    // LX_V2 (V2)
+    {
+        Max8907bPmuSupply_LX_V2,
+        MAX8907B_SDCTL2,
+        MAX8907B_SDSEQCNT2,
+        MAX8907B_SDV2,
+        TCA6416_INVALID_PORT,
+        TCA6416_INVALID_PORT,
+        Max8907bPmuVoltageGet_SD_A,
+        Max8907bPmuVoltageSet_SD_A,
+        {
+            NV_FALSE,
+            MAX8907B_MIN_OUTPUT_VOLTAGE_SD_A_x10/10,
+            MAX8907B_OUTPUT_VOLTAGE_INCREMENT_SD_A_x10/10,
+            MAX8907B_MAX_OUTPUT_VOLTAGE_SD_A_x10/10,
+            MAX8907B_REQUESTVOLTAGE_LX_V2
+        },
+    },
+
+    // LX_V3 (V3)
+    {
+        Max8907bPmuSupply_LX_V3,
+        MAX8907B_SDCTL3,
+        MAX8907B_SDSEQCNT3,
+        MAX8907B_SDV3,
+        TCA6416_INVALID_PORT,
+        TCA6416_INVALID_PORT,
+        Max8907bPmuVoltageGet_SD_B_LDO_B,
+        Max8907bPmuVoltageSet_SD_B_LDO_B,
+        {
+            NV_FALSE,
+            MAX8907B_MIN_OUTPUT_VOLTAGE_SD_B_LDO_B,
+            MAX8907B_OUTPUT_VOLTAGE_INCREMENT_SD_B_LDO_B,
+            MAX8907B_MAX_OUTPUT_VOLTAGE_SD_B_LDO_B,
+            MAX8907B_REQUESTVOLTAGE_LX_V3
+        },
+    },
+
+    // VRTC (RTC)
+    {
+        Max8907bPmuSupply_VRTC,
+        MAX8907B_REG_INVALID,
+        MAX8907B_REG_INVALID,
+        MAX8907B_REG_INVALID,
+        TCA6416_INVALID_PORT,
+        TCA6416_INVALID_PORT,
+        NULL,
+        NULL,
+        {
+            NV_TRUE,
+            MAX8907B_MIN_OUTPUT_VOLTAGE_RTC,
+            MAX8907B_OUTPUT_VOLTAGE_INCREMENT_RTC,
+            MAX8907B_MAX_OUTPUT_VOLTAGE_RTC,
+            MAX8907B_MAX_OUTPUT_VOLTAGE_RTC
+        },
+    },
+
+    // LDO1 (VOUT1)
+    {
+        Max8907bPmuSupply_LDO1,
+        MAX8907B_LDOCTL1,
+        MAX8907B_LDOSEQCNT1,
+        MAX8907B_LDO1VOUT,
+        TCA6416_INVALID_PORT,
+        TCA6416_INVALID_PORT,
+        Max8907bPmuVoltageGet_SD_B_LDO_B,
+        Max8907bPmuVoltageSet_SD_B_LDO_B,
+        {
+            NV_FALSE,
+            MAX8907B_MIN_OUTPUT_VOLTAGE_SD_B_LDO_B,
+            MAX8907B_OUTPUT_VOLTAGE_INCREMENT_SD_B_LDO_B,
+            MAX8907B_MAX_OUTPUT_VOLTAGE_SD_B_LDO_B,
+            MAX8907B_REQUESTVOLTAGE_LDO1
+        },
+    },
+
+    // LDO2 (VOUT2)
+    {
+        Max8907bPmuSupply_LDO2,
+        MAX8907B_LDOCTL2,
+        MAX8907B_LDOSEQCNT2,
+        MAX8907B_LDO2VOUT,
+        TCA6416_INVALID_PORT,
+        TCA6416_INVALID_PORT,
+        Max8907bPmuVoltageGet_LDO_A,
+        Max8907bPmuVoltageSet_LDO_A,
+        {
+            NV_FALSE,
+            MAX8907B_MIN_OUTPUT_VOLTAGE_LDO_A,
+            MAX8907B_OUTPUT_VOLTAGE_INCREMENT_LDO_A,
+            MAX8907B_MAX_OUTPUT_VOLTAGE_LDO_A,
+            MAX8907B_REQUESTVOLTAGE_LDO2
+        },
+    },
+
+    // LDO3 (VOUT3)
+    {
+        Max8907bPmuSupply_LDO3,
+        MAX8907B_LDOCTL3,
+        MAX8907B_LDOSEQCNT3,
+        MAX8907B_LDO3VOUT,
+        TCA6416_INVALID_PORT,
+        TCA6416_INVALID_PORT,
+        Max8907bPmuVoltageGet_LDO_A,
+        Max8907bPmuVoltageSet_LDO_A,
+        {
+            NV_FALSE,
+            MAX8907B_MIN_OUTPUT_VOLTAGE_LDO_A,
+            MAX8907B_OUTPUT_VOLTAGE_INCREMENT_LDO_A,
+            MAX8907B_MAX_OUTPUT_VOLTAGE_LDO_A,
+            MAX8907B_REQUESTVOLTAGE_LDO3
+        },
+    },
+
+    // LDO4 (VOUT4)
+    {
+        Max8907bPmuSupply_LDO4,
+        MAX8907B_LDOCTL4,
+        MAX8907B_LDOSEQCNT4,
+        MAX8907B_LDO4VOUT,
+        TCA6416_INVALID_PORT,
+        TCA6416_INVALID_PORT,
+        Max8907bPmuVoltageGet_SD_B_LDO_B,
+        Max8907bPmuVoltageSet_SD_B_LDO_B,
+        {
+            NV_FALSE,
+            MAX8907B_MIN_OUTPUT_VOLTAGE_SD_B_LDO_B,
+            MAX8907B_OUTPUT_VOLTAGE_INCREMENT_SD_B_LDO_B,
+            MAX8907B_MAX_OUTPUT_VOLTAGE_SD_B_LDO_B,
+            MAX8907B_REQUESTVOLTAGE_LDO4
+        },
+    },
+
+    // LDO5 (VOUT5)
+    {
+        Max8907bPmuSupply_LDO5,
+        MAX8907B_LDOCTL5,
+        MAX8907B_LDOSEQCNT5,
+        MAX8907B_LDO5VOUT,
+        TCA6416_INVALID_PORT,
+        TCA6416_INVALID_PORT,
+        Max8907bPmuVoltageGet_SD_B_LDO_B,
+        Max8907bPmuVoltageSet_SD_B_LDO_B,
+        {
+            NV_FALSE,
+            MAX8907B_MIN_OUTPUT_VOLTAGE_SD_B_LDO_B,
+            MAX8907B_OUTPUT_VOLTAGE_INCREMENT_SD_B_LDO_B,
+            MAX8907B_MAX_OUTPUT_VOLTAGE_SD_B_LDO_B,
+            MAX8907B_REQUESTVOLTAGE_LDO5
+        },
+    },
+
+    // LDO6 (VOUT6)
+    {
+        Max8907bPmuSupply_LDO6,
+        MAX8907B_LDOCTL6,
+        MAX8907B_LDOSEQCNT6,
+        MAX8907B_LDO6VOUT,
+        TCA6416_INVALID_PORT,
+        TCA6416_INVALID_PORT,
+        Max8907bPmuVoltageGet_SD_B_LDO_B,
+        Max8907bPmuVoltageSet_SD_B_LDO_B,
+        {
+            NV_FALSE,
+            MAX8907B_MIN_OUTPUT_VOLTAGE_SD_B_LDO_B,
+            MAX8907B_OUTPUT_VOLTAGE_INCREMENT_SD_B_LDO_B,
+            MAX8907B_MAX_OUTPUT_VOLTAGE_SD_B_LDO_B,
+            MAX8907B_REQUESTVOLTAGE_LDO6
+        },
+    },
+
+    // LDO7 (VOUT7)
+    {
+        Max8907bPmuSupply_LDO7,
+        MAX8907B_LDOCTL7,
+        MAX8907B_LDOSEQCNT7,
+        MAX8907B_LDO7VOUT,
+        TCA6416_INVALID_PORT,
+        TCA6416_INVALID_PORT,
+        Max8907bPmuVoltageGet_SD_B_LDO_B,
+        Max8907bPmuVoltageSet_SD_B_LDO_B,
+        {
+            NV_FALSE,
+            MAX8907B_MIN_OUTPUT_VOLTAGE_SD_B_LDO_B,
+            MAX8907B_OUTPUT_VOLTAGE_INCREMENT_SD_B_LDO_B,
+            MAX8907B_MAX_OUTPUT_VOLTAGE_SD_B_LDO_B,
+            MAX8907B_REQUESTVOLTAGE_LDO7
+        },
+    },
+
+    // LDO8 (VOUT8)
+    {
+        Max8907bPmuSupply_LDO8,
+        MAX8907B_LDOCTL8,
+        MAX8907B_LDOSEQCNT8,
+        MAX8907B_LDO8VOUT,
+        TCA6416_INVALID_PORT,
+        TCA6416_INVALID_PORT,
+        Max8907bPmuVoltageGet_SD_B_LDO_B,
+        Max8907bPmuVoltageSet_SD_B_LDO_B,
+        {
+            NV_FALSE,
+            MAX8907B_MIN_OUTPUT_VOLTAGE_SD_B_LDO_B,
+            MAX8907B_OUTPUT_VOLTAGE_INCREMENT_SD_B_LDO_B,
+            MAX8907B_MAX_OUTPUT_VOLTAGE_SD_B_LDO_B,
+            MAX8907B_REQUESTVOLTAGE_LDO8
+        },
+    },
+
+    // LDO9 (VOUT9)
+    {
+        Max8907bPmuSupply_LDO9,
+        MAX8907B_LDOCTL9,
+        MAX8907B_LDOSEQCNT9,
+        MAX8907B_LDO9VOUT,
+        TCA6416_INVALID_PORT,
+        TCA6416_INVALID_PORT,
+        Max8907bPmuVoltageGet_SD_B_LDO_B,
+        Max8907bPmuVoltageSet_SD_B_LDO_B,
+        {
+            NV_FALSE,
+            MAX8907B_MIN_OUTPUT_VOLTAGE_SD_B_LDO_B,
+            MAX8907B_OUTPUT_VOLTAGE_INCREMENT_SD_B_LDO_B,
+            MAX8907B_MAX_OUTPUT_VOLTAGE_SD_B_LDO_B,
+            MAX8907B_REQUESTVOLTAGE_LDO9
+        },
+    },
+
+    // LDO10 (VOUT10)
+    {
+        Max8907bPmuSupply_LDO10,
+        MAX8907B_LDOCTL10,
+        MAX8907B_LDOSEQCNT10,
+        MAX8907B_LDO10VOUT,
+        TCA6416_INVALID_PORT,
+        TCA6416_INVALID_PORT,
+        Max8907bPmuVoltageGet_SD_B_LDO_B,
+        Max8907bPmuVoltageSet_SD_B_LDO_B,
+        {
+            NV_FALSE,
+            MAX8907B_MIN_OUTPUT_VOLTAGE_SD_B_LDO_B,
+            MAX8907B_OUTPUT_VOLTAGE_INCREMENT_SD_B_LDO_B,
+            MAX8907B_MAX_OUTPUT_VOLTAGE_SD_B_LDO_B,
+            MAX8907B_REQUESTVOLTAGE_LDO10
+        },
+    },
+
+    // LDO11 (VOUT11)
+    {
+        Max8907bPmuSupply_LDO11,
+        MAX8907B_LDOCTL11,
+        MAX8907B_LDOSEQCNT11,
+        MAX8907B_LDO11VOUT,
+        TCA6416_INVALID_PORT,
+        TCA6416_INVALID_PORT,
+        Max8907bPmuVoltageGet_SD_B_LDO_B,
+        Max8907bPmuVoltageSet_SD_B_LDO_B,
+        {
+            NV_FALSE,
+            MAX8907B_MIN_OUTPUT_VOLTAGE_SD_B_LDO_B,
+            MAX8907B_OUTPUT_VOLTAGE_INCREMENT_SD_B_LDO_B,
+            MAX8907B_MAX_OUTPUT_VOLTAGE_SD_B_LDO_B,
+            MAX8907B_REQUESTVOLTAGE_LDO11
+        },
+    },
+
+    // LDO12 (VOUT12)
+    {
+        Max8907bPmuSupply_LDO12,
+        MAX8907B_LDOCTL12,
+        MAX8907B_LDOSEQCNT12,
+        MAX8907B_LDO12VOUT,
+        TCA6416_INVALID_PORT,
+        TCA6416_INVALID_PORT,
+        Max8907bPmuVoltageGet_SD_B_LDO_B,
+        Max8907bPmuVoltageSet_SD_B_LDO_B,
+        {
+            NV_FALSE,
+            MAX8907B_MIN_OUTPUT_VOLTAGE_SD_B_LDO_B,
+            MAX8907B_OUTPUT_VOLTAGE_INCREMENT_SD_B_LDO_B,
+            MAX8907B_MAX_OUTPUT_VOLTAGE_SD_B_LDO_B,
+            MAX8907B_REQUESTVOLTAGE_LDO12
+        },
+    },
+
+    // LDO13 (VOUT13)
+    {
+        Max8907bPmuSupply_LDO13,
+        MAX8907B_LDOCTL13,
+        MAX8907B_LDOSEQCNT13,
+        MAX8907B_LDO13VOUT,
+        TCA6416_INVALID_PORT,
+        TCA6416_INVALID_PORT,
+        Max8907bPmuVoltageGet_SD_B_LDO_B,
+        Max8907bPmuVoltageSet_SD_B_LDO_B,
+        {
+            NV_FALSE,
+            MAX8907B_MIN_OUTPUT_VOLTAGE_SD_B_LDO_B,
+            MAX8907B_OUTPUT_VOLTAGE_INCREMENT_SD_B_LDO_B,
+            MAX8907B_MAX_OUTPUT_VOLTAGE_SD_B_LDO_B,
+            MAX8907B_REQUESTVOLTAGE_LDO13
+        },
+    },
+
+    // LDO14 (VOUT14)
+    {
+        Max8907bPmuSupply_LDO14,
+        MAX8907B_LDOCTL14,
+        MAX8907B_LDOSEQCNT14,
+        MAX8907B_LDO14VOUT,
+        TCA6416_INVALID_PORT,
+        TCA6416_INVALID_PORT,
+        Max8907bPmuVoltageGet_SD_B_LDO_B,
+        Max8907bPmuVoltageSet_SD_B_LDO_B,
+        {
+            NV_FALSE,
+            MAX8907B_MIN_OUTPUT_VOLTAGE_SD_B_LDO_B,
+            MAX8907B_OUTPUT_VOLTAGE_INCREMENT_SD_B_LDO_B,
+            MAX8907B_MAX_OUTPUT_VOLTAGE_SD_B_LDO_B,
+            MAX8907B_REQUESTVOLTAGE_LDO14
+        },
+    },
+
+    // LDO15 (VOUT15)
+    {
+        Max8907bPmuSupply_LDO15,
+        MAX8907B_LDOCTL15,
+        MAX8907B_LDOSEQCNT15,
+        MAX8907B_LDO15VOUT,
+        TCA6416_INVALID_PORT,
+        TCA6416_INVALID_PORT,
+        Max8907bPmuVoltageGet_SD_B_LDO_B,
+        Max8907bPmuVoltageSet_SD_B_LDO_B,
+        {
+            NV_FALSE,
+            MAX8907B_MIN_OUTPUT_VOLTAGE_SD_B_LDO_B,
+            MAX8907B_OUTPUT_VOLTAGE_INCREMENT_SD_B_LDO_B,
+            MAX8907B_MAX_OUTPUT_VOLTAGE_SD_B_LDO_B,
+            MAX8907B_REQUESTVOLTAGE_LDO15
+        },
+    },
+
+    // LDO16 (VOUT16)
+    {
+        Max8907bPmuSupply_LDO16,
+        MAX8907B_LDOCTL16,
+        MAX8907B_LDOSEQCNT16,
+        MAX8907B_LDO16VOUT,
+        TCA6416_INVALID_PORT,
+        TCA6416_INVALID_PORT,
+        Max8907bPmuVoltageGet_SD_B_LDO_B,
+        Max8907bPmuVoltageSet_SD_B_LDO_B,
+        {
+            NV_FALSE,
+            MAX8907B_MIN_OUTPUT_VOLTAGE_SD_B_LDO_B,
+            MAX8907B_OUTPUT_VOLTAGE_INCREMENT_SD_B_LDO_B,
+            MAX8907B_MAX_OUTPUT_VOLTAGE_SD_B_LDO_B,
+            MAX8907B_REQUESTVOLTAGE_LDO16
+        },
+    },
+
+    // LDO17 (VOUT17)
+    {
+        Max8907bPmuSupply_LDO17,
+        MAX8907B_LDOCTL17,
+        MAX8907B_LDOSEQCNT17,
+        MAX8907B_LDO17VOUT,
+        TCA6416_INVALID_PORT,
+        TCA6416_INVALID_PORT,
+        Max8907bPmuVoltageGet_LDO_A,
+        Max8907bPmuVoltageSet_LDO_A,
+        {
+            NV_FALSE,
+            MAX8907B_MIN_OUTPUT_VOLTAGE_LDO_A,
+            MAX8907B_OUTPUT_VOLTAGE_INCREMENT_LDO_A,
+            MAX8907B_MAX_OUTPUT_VOLTAGE_LDO_A,
+            MAX8907B_REQUESTVOLTAGE_LDO17
+        },
+    },
+
+    // LDO18 (VOUT18)
+    {
+        Max8907bPmuSupply_LDO18,
+        MAX8907B_LDOCTL18,
+        MAX8907B_LDOSEQCNT18,
+        MAX8907B_LDO18VOUT,
+        TCA6416_INVALID_PORT,
+        TCA6416_INVALID_PORT,
+        Max8907bPmuVoltageGet_LDO_A,
+        Max8907bPmuVoltageSet_LDO_A,
+        {
+            NV_FALSE,
+            MAX8907B_MIN_OUTPUT_VOLTAGE_LDO_A,
+            MAX8907B_OUTPUT_VOLTAGE_INCREMENT_LDO_A,
+            MAX8907B_MAX_OUTPUT_VOLTAGE_LDO_A,
+            MAX8907B_REQUESTVOLTAGE_LDO18
+        },
+    },
+
+    // LDO19 (VOUT19)
+    {
+        Max8907bPmuSupply_LDO19,
+        MAX8907B_LDOCTL19,
+        MAX8907B_LDOSEQCNT19,
+        MAX8907B_LDO19VOUT,
+        TCA6416_INVALID_PORT,
+        TCA6416_INVALID_PORT,
+        Max8907bPmuVoltageGet_SD_B_LDO_B,
+        Max8907bPmuVoltageSet_SD_B_LDO_B,
+        {
+            NV_FALSE,
+            MAX8907B_MIN_OUTPUT_VOLTAGE_SD_B_LDO_B,
+            MAX8907B_OUTPUT_VOLTAGE_INCREMENT_SD_B_LDO_B,
+            MAX8907B_MAX_OUTPUT_VOLTAGE_SD_B_LDO_B,
+            MAX8907B_REQUESTVOLTAGE_LDO19
+        },
+    },
+
+    // LDO20 (VOUT20)
+    {
+        Max8907bPmuSupply_LDO20,
+        MAX8907B_LDOCTL20,
+        MAX8907B_LDOSEQCNT20,
+        MAX8907B_LDO20VOUT,
+        TCA6416_INVALID_PORT,
+        TCA6416_INVALID_PORT,
+        Max8907bPmuVoltageGet_SD_B_LDO_B,
+        Max8907bPmuVoltageSet_SD_B_LDO_B,
+        {
+            NV_FALSE,
+            MAX8907B_MIN_OUTPUT_VOLTAGE_SD_B_LDO_B,
+            MAX8907B_OUTPUT_VOLTAGE_INCREMENT_SD_B_LDO_B,
+            MAX8907B_MAX_OUTPUT_VOLTAGE_SD_B_LDO_B,
+            MAX8907B_REQUESTVOLTAGE_LDO20
+        },
+    },
+
+    // WHITE_LED
+    {
+        Max8907bPmuSupply_WHITE_LED,
+        MAX8907B_REG_INVALID,
+        MAX8907B_REG_INVALID,
+        MAX8907B_REG_INVALID,
+        TCA6416_INVALID_PORT,
+        TCA6416_INVALID_PORT,
+        NULL,
+        NULL,
+        {NV_TRUE, 0, 0, 0, 0},
+    },
+
+    // EXT_DC/DC1 (for HDMI, VGA, USB)
+    // By default, this is hard-wired as "always on" (see schematics)
+    {
+        Max8907bPmuSupply_EXT_DCDC_1,
+        MAX8907B_REG_INVALID,
+        MAX8907B_REG_INVALID,
+        MAX8907B_REG_INVALID,
+        TCA6416_INVALID_PORT,
+        TCA6416_INVALID_PORT,
+        NULL,
+        NULL,
+        {
+            NV_TRUE,
+            MAX8907B_REQUESTVOLTAGE_EXT_DCDC_1,
+            0,
+            MAX8907B_REQUESTVOLTAGE_EXT_DCDC_1,
+            MAX8907B_REQUESTVOLTAGE_EXT_DCDC_1
+        },
+    },
+
+    // EXT_DC/DC2 (not connected / reserved)
+    {
+        Max8907bPmuSupply_EXT_DCDC_2,
+        MAX8907B_REG_INVALID,
+        MAX8907B_REG_INVALID,
+        MAX8907B_REG_INVALID,
+        TCA6416_INVALID_PORT,
+        TCA6416_INVALID_PORT,
+        NULL,
+        NULL,
+        {NV_TRUE, 0, 0, 0, 0},
+    },
+
+    // EXT_DC/DC3 (PCI Express)
+    {
+        Max8907bPmuSupply_EXT_DCDC_3,
+        TCA6416_CONFIG_PORT_0,
+        MAX8907B_REG_INVALID,
+        FAN5335_VSEL0,
+        TCA6416_PORT_0,
+        TCA6416_PIN_6,
+        Fan5355PmuVoltageGet_VOUT_02,
+        Fan5355PmuVoltageSet_VOUT_02,
+        {
+            NV_FALSE,
+            FAN5355_MIN_OUTPUT_VOLTAGE_x10/10,
+            FAN5355_OUTPUT_VOLTAGE_INCREMENT_x10/10,
+            FAN5355_MAX_OUTPUT_VOLTAGE_x10/10,
+            MAX8907B_REQUESTVOLTAGE_EXT_DCDC_3
+        },
+    },
+
+    // EXT_DC/DC4 (Backlight-1 Intensity Enable)
+    // By default, this is hard-wired as "always enabled" (see schematics)
+    {
+        Max8907bPmuSupply_EXT_DCDC_4,
+        MAX8907B_REG_INVALID,
+        MAX8907B_REG_INVALID,
+        MAX8907B_REG_INVALID,
+        TCA6416_INVALID_PORT,
+        TCA6416_INVALID_PORT,
+        NULL,
+        NULL,
+        {NV_TRUE, 0, 0, 0, 0},
+    },
+
+    // EXT_DC/DC5 (Backlight-2 Intensity Enable)
+    // By default, this is hard-wired as "always enabled" (see schematics)
+    {
+        Max8907bPmuSupply_EXT_DCDC_5,
+        MAX8907B_REG_INVALID,
+        MAX8907B_REG_INVALID,
+        MAX8907B_REG_INVALID,
+        TCA6416_INVALID_PORT,
+        TCA6416_INVALID_PORT,
+        NULL,
+        NULL,
+        {NV_TRUE, 0, 0, 0, 0},
+    },
+
+    // EXT_DC/DC6 (not connected / reserved)
+    {
+        Max8907bPmuSupply_EXT_DCDC_6,
+        MAX8907B_REG_INVALID,
+        MAX8907B_REG_INVALID,
+        MAX8907B_REG_INVALID,
+        TCA6416_INVALID_PORT,
+        TCA6416_INVALID_PORT,
+        NULL,
+        NULL,
+        {NV_TRUE, 0, 0, 0, 0},
+    },
+
+    // USB1   VBUS is wired from with DCDC_3.
+    {
+        Max8907bPmuSupply_EXT_DCDC_3_USB1,
+        TCA6416_CONFIG_PORT_0,
+        TCA6416_INVALID_PORT,
+        TCA6416_INVALID_PORT,
+        TCA6416_PORT_0,
+        TCA6416_PIN_0,
+        NULL,
+        NULL,
+        {
+            NV_FALSE,
+            FAN5355_MIN_OUTPUT_VOLTAGE_x10/10,
+            FAN5355_OUTPUT_VOLTAGE_INCREMENT_x10/10,
+            FAN5355_MAX_OUTPUT_VOLTAGE_x10/10,
+            MAX8907B_REQUESTVOLTAGE_EXT_DCDC_3
+        },
+    },
+
+    // USB3   VBUS is wired from with DCDC_3.
+    {
+        Max8907bPmuSupply_EXT_DCDC_3_USB3,
+        TCA6416_CONFIG_PORT_0,
+        TCA6416_INVALID_PORT,
+        TCA6416_INVALID_PORT,
+        TCA6416_PORT_0,
+        TCA6416_PIN_1,
+        NULL,
+        NULL,
+        {
+            NV_FALSE,
+            FAN5355_MIN_OUTPUT_VOLTAGE_x10/10,
+            FAN5355_OUTPUT_VOLTAGE_INCREMENT_x10/10,
+            FAN5355_MAX_OUTPUT_VOLTAGE_x10/10,
+            MAX8907B_REQUESTVOLTAGE_EXT_DCDC_3
+        },
+    },
+
+    // MIC2826 BUCK Regulator(BUCK)
+    {
+        MIC2826PmuSupply_BUCK,
+        MIC2826_REG_ADDR_BUCK,
+        MIC2826_REG_INVALID,
+        MIC2826_REG_INVALID,
+        MIC2826_INVALID_PORT,
+        MIC2826_INVALID_PORT,
+        NULL,
+        NULL,
+        {
+            NV_FALSE,
+            MIC2826_BUCK_VOLTAGE_MIN_MV,
+            MIC2826_BUCK_VOLTAGE_STEP_MV,
+            MIC2826_BUCK_VOLTAGE_MAX_MV,
+            MIC2826_BUCK_REQUESTVOLTAGE_MV
+        },
+    },
+    // MIC2826 LDO1
+    {
+        MIC2826PmuSupply_LDO1,
+        MIC2826_REG_ADDR_LD01,
+        MIC2826_REG_INVALID,
+        MIC2826_REG_INVALID,
+        MIC2826_INVALID_PORT,
+        MIC2826_INVALID_PORT,
+        NULL,
+        NULL,
+        {
+            NV_FALSE,
+            MIC2826_LDO_VOLTAGE_MIN_MV,
+            MIC2826_LDO_VOLTAGE_STEP_MV,
+            MIC2826_LDO_VOLTAGE_MAX_MV,
+            MIC2826_LDO1_REQUESTVOLTAGE_MV
+        },
+    },
+
+    // MIC2826 LDO2
+    {
+        MIC2826PmuSupply_LDO2,
+        MIC2826_REG_ADDR_LD02,
+        MIC2826_REG_INVALID,
+        MIC2826_REG_INVALID,
+        MIC2826_INVALID_PORT,
+        MIC2826_INVALID_PORT,
+        NULL,
+        NULL,
+        {
+            NV_FALSE,
+            MIC2826_LDO_VOLTAGE_MIN_MV,
+            MIC2826_LDO_VOLTAGE_STEP_MV,
+            MIC2826_LDO_VOLTAGE_MAX_MV,
+            MIC2826_LDO2_REQUESTVOLTAGE_MV
+        },
+    },
+
+    // LDO3
+    {
+        MIC2826PmuSupply_LDO3,
+        MIC2826_REG_ADDR_LD03,
+        MIC2826_REG_INVALID,
+        MIC2826_REG_INVALID,
+        MIC2826_INVALID_PORT,
+        MIC2826_INVALID_PORT,
+        NULL,
+        NULL,
+        {
+            NV_FALSE,
+            MIC2826_LDO_VOLTAGE_MIN_MV,
+            MIC2826_LDO_VOLTAGE_STEP_MV,
+            MIC2826_LDO_VOLTAGE_MAX_MV,
+            MIC2826_LDO3_REQUESTVOLTAGE_MV
+        },
+    },
+
+    // EXT_DC/DC7 (controlled by LX_V1, scaled by AD5258 DPM)
+    {
+        Max8907bLxV1_Ad5258_DPM_EXT_DCDC_7,
+        AD5258_RDAC_ADDR,
+        MAX8907B_REG_INVALID,
+        MAX8907B_REG_INVALID,
+        TCA6416_INVALID_PORT,
+        TCA6416_INVALID_PORT,
+        NULL,
+        NULL,
+        {
+            NV_FALSE,
+            AD5258_V0,
+            AD5258_MIN_STEP_MV,
+            AD5258_VMAX,
+            MAX8907B_REQUESTVOLTAGE_LX_V1
+        },
+    }
+};
+
+static NvBool
+Max8907bReadVoltageReg(
+    NvOdmPmuDeviceHandle hDevice,
+    NvU32 vddRail,
+    NvU32* pMilliVolts)
+{
+    const Max8907bPmuSupplyInfo *pSupplyInfo = &Max8907bSupplyInfoTable[vddRail];
+    NvU8 data = 0;
+    NvU32 milliVolts = 0;
+
+    NV_ASSERT(pSupplyInfo->supply == (Max8907bPmuSupply)vddRail);
+
+    if (pSupplyInfo->ControlRegAddr != MAX8907B_REG_INVALID)
+    {
+        if (!Max8907bI2cRead8(hDevice, pSupplyInfo->ControlRegAddr, &data))
+            return NV_FALSE;
+
+        if ((data & MAX8907B_OUT_VOLTAGE_CONTROL_MASK) ==
+            MAX8907B_OUT_VOLTAGE_CONTROL_DISABLE)
+        {
+            ((Max8907bPrivData*)hDevice->pPrivate)->pVoltages[vddRail] =
+                ODM_VOLTAGE_OFF;
+            *pMilliVolts = ODM_VOLTAGE_OFF;
+            return NV_TRUE;
+        }
+    }
+
+    if (pSupplyInfo->OutputVoltageRegAddr == MAX8907B_REG_INVALID)
+        return NV_FALSE;
+
+    if (!Max8907bI2cRead8(hDevice, pSupplyInfo->OutputVoltageRegAddr, &data))
+        return NV_FALSE;
+
+    data &= MAX8907B_OUT_VOLTAGE_MASK;
+    if (!data) //OFF
+        milliVolts = ODM_VOLTAGE_OFF;
+    else
+        milliVolts = pSupplyInfo->GetVoltage(data);
+
+    ((Max8907bPrivData*)hDevice->pPrivate)->pVoltages[vddRail] = milliVolts;
+    *pMilliVolts = milliVolts;
+    return NV_TRUE;
+}
+
+static NvBool
+Max8907bWriteVoltageReg(
+    NvOdmPmuDeviceHandle hDevice,
+    NvU32 vddRail,
+    NvU32  MilliVolts,
+    NvU32* pSettleMicroSeconds)
+{
+    const Max8907bPmuSupplyInfo *pSupplyInfo = &Max8907bSupplyInfoTable[vddRail];
+    NvU8 data = 0;
+    NvU32 SettleUS = 0;
+
+    NV_ASSERT(pSupplyInfo->supply == (Max8907bPmuSupply)vddRail);
+
+    if (MilliVolts == ODM_VOLTAGE_OFF)
+    {
+        // check if the supply can be turned off
+        if (((Max8907bPrivData*)hDevice->pPrivate)->supplyRefCntTable[pSupplyInfo->supply] == 1)
+        {
+            // turn off the supply
+            NvOdmServicesPmuSetSocRailPowerState(
+                ((Max8907bPrivData*)hDevice->pPrivate)->hOdmPmuSevice, pSupplyInfo->supply, NV_FALSE);
+
+            // Disable the output (read-modify-write the control register)
+            Max8907bI2cRead8(hDevice, pSupplyInfo->ControlRegAddr, &data);
+            data &= (~MAX8907B_OUT_VOLTAGE_CONTROL_MASK);
+            data |= MAX8907B_OUT_VOLTAGE_CONTROL_DISABLE;
+            if (!Max8907bI2cWrite8(hDevice, pSupplyInfo->ControlRegAddr, data))
+                return NV_FALSE;
+
+            ((Max8907bPrivData*)hDevice->pPrivate)->pVoltages[vddRail] =
+                ODM_VOLTAGE_OFF;
+            SettleUS = MAX8907B_TURN_OFF_TIME_US;
+        }
+
+        if (((Max8907bPrivData*)hDevice->pPrivate)->supplyRefCntTable[pSupplyInfo->supply] != 0)
+            ((Max8907bPrivData*)hDevice->pPrivate)->supplyRefCntTable[pSupplyInfo->supply] --;
+
+        if (pSettleMicroSeconds)
+            *pSettleMicroSeconds = SettleUS;
+        else
+            NvOdmOsWaitUS(SettleUS);
+
+        return NV_TRUE;
+    }
+
+    // Set voltage level
+    data = pSupplyInfo->SetVoltage(MilliVolts);
+    if (!Max8907bI2cWrite8(hDevice, pSupplyInfo->OutputVoltageRegAddr, data))
+        return NV_FALSE;
+    if (MilliVolts >
+        ((Max8907bPrivData*)hDevice->pPrivate)->pVoltages[vddRail])
+    {
+        NvU32 LastMV =
+            ((Max8907bPrivData*)hDevice->pPrivate)->pVoltages[vddRail];
+        SettleUS = (MilliVolts - LastMV) * 1000 / MAX8907B_SCALE_UP_UV_PER_US;
+    }
+    ((Max8907bPrivData*)hDevice->pPrivate)->pVoltages[vddRail] = MilliVolts;
+
+    // turn on supply
+    if (((Max8907bPrivData*)hDevice->pPrivate)->supplyRefCntTable[pSupplyInfo->supply] == 0)
+    {
+        // Enable the output (read-modify-write the control register)
+        Max8907bI2cRead8(hDevice, pSupplyInfo->ControlRegAddr, &data);
+
+        if ((data & MAX8907B_OUT_VOLTAGE_CONTROL_MASK) ==
+            MAX8907B_OUT_VOLTAGE_CONTROL_DISABLE)
+        {
+            // Voltage on/change (supply was off, so it must be turned on)
+            NvOdmServicesPmuSetSocRailPowerState(
+                ((Max8907bPrivData*)(hDevice->pPrivate))->hOdmPmuSevice,
+                pSupplyInfo->supply, NV_TRUE);
+            data |= MAX8907B_OUT_VOLTAGE_ENABLE_BIT;
+            if (!Max8907bI2cWrite8(hDevice, pSupplyInfo->ControlRegAddr, data))
+                return NV_FALSE;
+
+            SettleUS = MAX8907B_TURN_ON_TIME_US;
+        }
+    }
+
+    ((Max8907bPrivData*)hDevice->pPrivate)->supplyRefCntTable[pSupplyInfo->supply] ++;
+
+    if (pSettleMicroSeconds)
+        *pSettleMicroSeconds = SettleUS;
+    else
+        NvOdmOsWaitUS(SettleUS);
+
+    return NV_TRUE;
+}
+
+static NvBool
+Max8907bOnOffConfigure(NvOdmPmuDeviceHandle hDevice)
+{
+    NvU8 data = 0;
+
+    if (!Max8907bI2cRead8(hDevice, MAX8907B_SYSENSEL, &data))
+        return NV_FALSE;
+
+    // Enable hard reset - power-off after ONKEY press for 5 seconds
+    // (must be enabled for thermal auto-shutdown)
+    data |= (MAX8907B_SYSENSEL_HRDSTEN_MASK <<
+             MAX8907B_SYSENSEL_HRDSTEN_SHIFT);
+
+    return Max8907bI2cWrite8(hDevice, MAX8907B_SYSENSEL, data);
+}
+
+static NvBool
+Max8907bPwrEnConfigure(NvOdmPmuDeviceHandle hDevice, NvBool Enable)
+{
+    NvU8 data = 0;
+
+    if (!Max8907bI2cRead8(hDevice, MAX8907B_RESET_CNFG, &data))
+        return NV_FALSE;
+
+    // Enable/disable PWREN h/w control mechanism (PWREN signal must be
+    // inactive = high at this time)
+    if (Enable)
+        data |= (MAX8907B_RESET_CNFG_PWREN_EN_MASK <<
+                 MAX8907B_RESET_CNFG_PWREN_EN_SHIFT);
+    else
+        data &= (~(MAX8907B_RESET_CNFG_PWREN_EN_MASK <<
+                   MAX8907B_RESET_CNFG_PWREN_EN_SHIFT));
+    if (!Max8907bI2cWrite8(hDevice, MAX8907B_RESET_CNFG, data))
+        return NV_FALSE;
+
+    // When enabled, connect PWREN to SEQ2 by clearing SEQ2 configuration
+    // settings for silicon revision that requires s/w WAR. On other MAX8907B
+    // revisions PWREN is always connected to SEQ2.
+    if (Enable)
+    {
+        if (!Max8907bI2cRead8(hDevice, MAX8907B_II2RR, &data))
+            return NV_FALSE;
+
+        if (data == MAX8907B_II2RR_PWREN_WAR)
+        {
+            data = 0x00;
+            if (!Max8907bI2cWrite8(hDevice, MAX8907B_SEQ2CNFG, data))
+                return NV_FALSE;
+        }
+    }
+    return NV_TRUE;
+}
+
+static NvBool
+Max8907bPwrEnAttach(
+    NvOdmPmuDeviceHandle hDevice,
+    Max8907bPmuSupply Supply,
+    NvBool Attach)
+{
+    NvU8 CtlAddr, CtlData, CntAddr, CntData, SeqSel;
+
+    switch (Supply)
+    {
+        case Max8907bPmuSupply_LX_V1:   // CPU
+            // No sequencer delay for CPU rail when it is attached
+            CntData = Attach ?  0x00 : MAX8907B_SEQCNT_DEFAULT_LX_V1;
+            SeqSel = Attach ? MAX8907B_SEQSEL_PWREN_LXX :
+                              MAX8907B_SEQSEL_DEFAULT_LX_V1;
+            break;
+
+        case Max8907bPmuSupply_LX_V2:   // Core
+            // Change CPU sequencer delay when core is attached to assure
+            // order of Core/CPU rails control; clear CPU delay when core
+            // is detached
+            CntAddr = Max8907bSupplyInfoTable[
+                Max8907bPmuSupply_LX_V1].SequencerCountRegAddr;
+            CntData = Attach ?  MAX8907B_SEQCNT_PWREN_LX_V1 : 0x00;
+            if (!Max8907bI2cWrite8(hDevice, CntAddr, CntData))
+                return NV_FALSE;
+
+            CntData = Attach ?  MAX8907B_SEQCNT_PWREN_LX_V2 :
+                                MAX8907B_SEQCNT_DEFAULT_LX_V2;
+            SeqSel = Attach ? MAX8907B_SEQSEL_PWREN_LXX :
+                              MAX8907B_SEQSEL_DEFAULT_LX_V2;
+            break;
+
+        default:
+            NV_ASSERT(!"This supply must not be attached to PWREN");
+            return NV_FALSE;
+    }
+    CtlAddr = Max8907bSupplyInfoTable[Supply].ControlRegAddr;
+    CntAddr = Max8907bSupplyInfoTable[Supply].SequencerCountRegAddr;
+
+    // Read control refgister, and select target sequencer
+    if (!Max8907bI2cRead8(hDevice, CtlAddr, &CtlData))
+        return NV_FALSE;
+    CtlData &= (~(MAX8907B_CTL_SEQ_MASK << MAX8907B_CTL_SEQ_SHIFT ));
+    CtlData |= ((SeqSel & MAX8907B_CTL_SEQ_MASK) << MAX8907B_CTL_SEQ_SHIFT );
+
+    // Attach: set count => set control
+    // Dettach: reset control => reset count
+    if (Attach)
+    {
+        if (!Max8907bI2cWrite8(hDevice, CntAddr, CntData))
+            return NV_FALSE;
+    }
+
+    if (!Max8907bI2cWrite8(hDevice, CtlAddr, CtlData))
+        return NV_FALSE;
+
+    if (!Attach)
+    {
+        if (!Max8907bI2cWrite8(hDevice, CntAddr, CntData))
+            return NV_FALSE;
+    }
+    return NV_TRUE;
+}
+
+static NvBool
+Tca6416ConfigPort(
+    NvOdmPmuDeviceHandle hDevice,
+    NvU32 vddRail,
+    NvBool Enable)
+{
+    const Max8907bPmuSupplyInfo *pSupplyInfo = &Max8907bSupplyInfoTable[vddRail];
+    NvU32 PortNo;
+    NvU32 PinNo;
+
+    // Get port number and pin number
+    PortNo = pSupplyInfo->OutputPort;
+    PinNo = pSupplyInfo->PmuGpio;
+
+    NV_ASSERT(pSupplyInfo->supply == (Max8907bPmuSupply)vddRail);
+
+    if (Enable)
+    {
+        // Configure GPIO as output
+        if (!Tca6416ConfigPortPin(hDevice, PortNo, PinNo, GpioPinMode_Output))
+            return NV_FALSE;
+
+        // Set the output port
+        if (!Tca6416WritePortPin(hDevice, PortNo, PinNo, GpioPinState_High))
+            return NV_FALSE;
+    }
+    else
+    // check if the supply can be turned off
+    {
+        // turn off the supply
+        NvOdmServicesPmuSetSocRailPowerState(
+            ((Max8907bPrivData*)hDevice->pPrivate)->hOdmPmuSevice, pSupplyInfo->supply, NV_FALSE);
+
+        // Configure port pin as output
+        if (!Tca6416ConfigPortPin(hDevice, PortNo, PinNo, GpioPinMode_Output))
+            return NV_FALSE;
+
+        // Set the output port (for disable, data = 0)
+        if (!Tca6416WritePortPin(hDevice, PortNo, PinNo, GpioPinState_Low))
+            return NV_FALSE;
+    }
+    return NV_TRUE;
+}
+
+
+#if defined(MAX8907B_USE_FAN5355_VOLTAGE_SCALING)
+static NvBool
+Fan5355ReadVoltageReg(
+    NvOdmPmuDeviceHandle hDevice,
+    NvU32 vddRail,
+    NvU32* pMilliVolts)
+{
+    const Max8907bPmuSupplyInfo *pSupplyInfo = &Max8907bSupplyInfoTable[vddRail];
+    NvU8 data = 0;
+    NvU32 milliVolts = 0;
+
+    NV_ASSERT(pSupplyInfo->supply == (Max8907bPmuSupply)vddRail);
+
+    if (pSupplyInfo->OutputVoltageRegAddr == FAN5335_REG_INVALID)
+        return NV_FALSE;
+
+    if (!Fan5355I2cRead8(hDevice, pSupplyInfo->OutputVoltageRegAddr, &data))
+        return NV_FALSE;
+
+    if (!data) //OFF
+        milliVolts = 0;
+    else
+        milliVolts = pSupplyInfo->GetVoltage(data);
+
+    *pMilliVolts = milliVolts;
+    return NV_TRUE;
+}
+#endif
+
+static NvBool
+Fan5355WriteVoltageReg(
+    NvOdmPmuDeviceHandle hDevice,
+    NvU32 vddRail,
+    NvU32  MilliVolts)
+{
+    const Max8907bPmuSupplyInfo *pSupplyInfo = NULL;
+    NvU8 data = 0;
+
+    if ((vddRail == Max8907bPmuSupply_EXT_DCDC_3_USB1) ||
+            (vddRail == Max8907bPmuSupply_EXT_DCDC_3_USB3))
+    {
+        vddRail = Max8907bPmuSupply_EXT_DCDC_3;
+    }
+
+    pSupplyInfo = &Max8907bSupplyInfoTable[vddRail];
+
+    NV_ASSERT(pSupplyInfo->supply == (Max8907bPmuSupply)vddRail);
+
+    // TO DO: Account for reference counting
+    if (MilliVolts == ODM_VOLTAGE_OFF)
+    {
+        // check if the supply can be turned off
+        {
+            // turn off the supply
+            NvOdmServicesPmuSetSocRailPowerState(
+                ((Max8907bPrivData*)hDevice->pPrivate)->hOdmPmuSevice, pSupplyInfo->supply, NV_FALSE);
+
+            // Disable the output
+            if (!Tca6416ConfigPort(hDevice, vddRail, NV_FALSE))
+                return NV_FALSE;
+        }
+    }
+    else
+    {
+        // Voltage on/change
+        NvOdmServicesPmuSetSocRailPowerState(
+                ((Max8907bPrivData*)(hDevice->pPrivate))->hOdmPmuSevice, pSupplyInfo->supply, NV_TRUE);
+
+        // Set voltage level
+        data = pSupplyInfo->SetVoltage(MilliVolts);
+#if defined(MAX8907B_USE_FAN5355_VOLTAGE_SCALING)
+        if (!Fan5355I2cWrite8(hDevice, pSupplyInfo->OutputVoltageRegAddr, data))
+            return NV_FALSE;
+#endif
+
+        // Enable the output
+        if (!Tca6416ConfigPort(hDevice, vddRail, NV_TRUE))
+            return NV_FALSE;
+    }
+    return NV_TRUE;
+}
+
+static NvBool
+Max8907bLxV1Ad5258ReadVoltageReg(
+    NvOdmPmuDeviceHandle hDevice,
+    NvU32 vddRail,
+    NvU32* pMilliVolts)
+{
+    const Max8907bPmuSupplyInfo* pSupplyInfo =
+        &Max8907bSupplyInfoTable[vddRail];
+
+    NV_ASSERT(pSupplyInfo->supply == (Max8907bPmuSupply)vddRail);
+
+    // Check if DC/DC has been turned Off (controlled by LxV1 main PMU output)
+    if (((Max8907bPrivData*)hDevice->pPrivate)->supplyRefCntTable[
+        pSupplyInfo->supply] == 0)
+    {
+        if (!Max8907bReadVoltageReg(
+            hDevice, Max8907bPmuSupply_LX_V1, pMilliVolts))
+            return NV_FALSE;
+        if (*pMilliVolts == ODM_VOLTAGE_OFF)
+            return NV_TRUE;
+    }
+
+    // DC/DC is On - now get DPM-scaled voltage
+    return Ad5258I2cGetVoltage(hDevice, pMilliVolts);
+}
+
+static NvBool
+Max8907bLxV1Ad5258WriteVoltageReg(
+    NvOdmPmuDeviceHandle hDevice,
+    NvU32 vddRail,
+    NvU32 MilliVolts,
+    NvU32* pSettleMicroSeconds)
+{
+    const Max8907bPmuSupplyInfo *pSupplyInfo =
+        &Max8907bSupplyInfoTable[vddRail];
+
+    NV_ASSERT(pSupplyInfo->supply == (Max8907bPmuSupply)vddRail);
+
+    if (MilliVolts == ODM_VOLTAGE_OFF)
+    {
+        // Check if the supply can be turned off, and if yes - turn off
+        // LxV1 main PMU output, which controls DC/DC
+        if (((Max8907bPrivData*)hDevice->pPrivate)->supplyRefCntTable[
+            pSupplyInfo->supply] == 1)
+        {
+            if (!Max8907bWriteVoltageReg(hDevice, Max8907bPmuSupply_LX_V1,
+                                         MilliVolts, pSettleMicroSeconds))
+                return NV_FALSE;
+        }
+        if (((Max8907bPrivData*)hDevice->pPrivate)->supplyRefCntTable[
+            pSupplyInfo->supply] != 0)
+        {
+            ((Max8907bPrivData*)hDevice->pPrivate)->supplyRefCntTable[
+            pSupplyInfo->supply] --;
+        }
+        return NV_TRUE;
+    }
+
+    // Set DPM voltage level (includes DPM and DCDC change level settle time)
+    if (!Ad5258I2cSetVoltage(hDevice, MilliVolts))
+        return NV_FALSE;
+
+    // Turn on control LxV1 supply on main PMU if necessary
+    if (((Max8907bPrivData*)hDevice->pPrivate)->supplyRefCntTable[
+        pSupplyInfo->supply] == 0)
+    {
+        if (!Max8907bWriteVoltageReg(hDevice, Max8907bPmuSupply_LX_V1,
+                MAX8907B_REQUESTVOLTAGE_LX_V1, pSettleMicroSeconds))
+            return NV_FALSE;
+
+        // Add external DCDC turning On settling time
+        if (pSettleMicroSeconds)
+            *pSettleMicroSeconds += AD5258_TURN_ON_TIME_US;
+        else
+            NvOdmOsWaitUS(AD5258_TURN_ON_TIME_US);
+    }
+    ((Max8907bPrivData*)hDevice->pPrivate)->supplyRefCntTable[
+        pSupplyInfo->supply] ++;
+
+    return NV_TRUE;
+}
+
+NvBool
+Max8907bSetup(NvOdmPmuDeviceHandle hDevice)
+{
+    NvOdmIoModule I2cModule = NvOdmIoModule_I2c;
+    NvU32  I2cInstance = 0;
+    NvU32  I2cAddress  = 0;
+    NvU32  i           = 0;
+    const NvOdmPeripheralConnectivity *pConnectivity =
+                           NvOdmPeripheralGetGuid(PMUGUID);
+
+    NV_ASSERT(hDevice);
+
+    hMax8907bPmu = (Max8907bPrivData*) NvOdmOsAlloc(sizeof(Max8907bPrivData));
+    if (hMax8907bPmu == NULL)
+    {
+        NVODMPMU_PRINTF(("Error Allocating Max8907bPrivData.\n"));
+        return NV_FALSE;
+    }
+    NvOdmOsMemset(hMax8907bPmu, 0, sizeof(Max8907bPrivData));
+    hDevice->pPrivate = hMax8907bPmu;
+
+    ((Max8907bPrivData*)hDevice->pPrivate)->supplyRefCntTable =
+        NvOdmOsAlloc(sizeof(NvU32) * Max8907bPmuSupply_Num);
+    if (((Max8907bPrivData*)hDevice->pPrivate)->supplyRefCntTable == NULL)
+    {
+        NVODMPMU_PRINTF(("Error Allocating RefCntTable. \n"));
+        goto fail;
+    }
+    ((Max8907bPrivData*)hDevice->pPrivate)->pVoltages =
+        NvOdmOsAlloc(sizeof(NvU32) * Max8907bPmuSupply_Num);
+    if (((Max8907bPrivData*)hDevice->pPrivate)->pVoltages == NULL)
+    {
+        NVODMPMU_PRINTF(("Error Allocating shadow voltages table. \n"));
+        goto fail;
+    }
+
+    // memset
+    for (i = 0; i < Max8907bPmuSupply_Num; i++)
+    {
+        ((Max8907bPrivData*)hDevice->pPrivate)->supplyRefCntTable[i] = 0;
+        // Setting shadow to 0 would cause spare delay on the 1st scaling of
+        // always On rail; however the alternative reading of initial settings
+        // over I2C is even worse.
+        ((Max8907bPrivData*)hDevice->pPrivate)->pVoltages[i] = 0;
+    }
+
+    if (pConnectivity != NULL) // PMU is in database
+    {
+        NvU32 i = 0;
+
+        for (i = 0; i < pConnectivity->NumAddress; i ++)
+        {
+            if (pConnectivity->AddressList[i].Interface == NvOdmIoModule_I2c_Pmu)
+            {
+                I2cModule   = NvOdmIoModule_I2c_Pmu;
+                I2cInstance = pConnectivity->AddressList[i].Instance;
+                I2cAddress  = pConnectivity->AddressList[i].Address;
+                break;
+            }
+        }
+
+        NV_ASSERT(I2cModule  == NvOdmIoModule_I2c_Pmu);
+        NV_ASSERT(I2cAddress != 0);
+
+        ((Max8907bPrivData*)hDevice->pPrivate)->hOdmI2C = NvOdmI2cOpen(I2cModule, I2cInstance);
+        if (!((Max8907bPrivData*)hDevice->pPrivate)->hOdmI2C)
+        {
+            NVODMPMU_PRINTF(("[NVODM PMU]Max8907bSetup: Error Opening I2C device. \n"));
+            NVODMPMU_PRINTF(("[NVODM PMU]Please check PMU device I2C settings. \n"));
+            return NV_FALSE;
+        }
+        ((Max8907bPrivData*)hDevice->pPrivate)->DeviceAddr = I2cAddress;
+        ((Max8907bPrivData*)hDevice->pPrivate)->hOdmPmuSevice = NvOdmServicesPmuOpen();
+    }
+    else
+    {
+        // if PMU is not present in the database, then the platform is PMU-less.
+        NVODMPMU_PRINTF(("[NVODM PMU]Max8907bSetup: The system did not doscover PMU from the data base.\n"));
+        NVODMPMU_PRINTF(("[NVODM PMU]Max8907bSetup: If this is not intended, please check the peripheral database for PMU settings.\n"));
+        return NV_FALSE;
+    }
+
+    // Configure OnOff options
+    if (!Max8907bOnOffConfigure(hDevice))
+    {
+        NVODMPMU_PRINTF(("[NVODM PMU]Max8907bSetup: Max8907bOnOffConfigure() failed. \n"));
+        return NV_FALSE;
+    }
+
+    // Configure PWREN, and attach CPU V1 rail to it.
+    // TODO: h/w events (power cycle, reset, battery low) auto-disables PWREN.
+    // Only soft reset (not supported) requires s/w to disable PWREN explicitly
+    if (!Max8907bPwrEnConfigure(hDevice, NV_TRUE))
+    {
+        NVODMPMU_PRINTF(("[NVODM PMU]Max8907bSetup: Max8907bPwrEnConfigure() failed. \n"));
+        return NV_FALSE;
+    }
+    if (!Max8907bPwrEnAttach(hDevice, Max8907bPmuSupply_LX_V1, NV_TRUE))
+    {
+        NVODMPMU_PRINTF(("[NVODM PMU]Max8907bSetup: Max8907bPwrEnAttach() failed. \n"));
+        return NV_FALSE;
+    }
+
+    //Check battery presence
+    if (!Max8907bBatteryChargerMainBatt(hDevice,&((Max8907bPrivData*)hDevice->pPrivate)->battPresence))
+    {
+        NVODMPMU_PRINTF(("[NVODM PMU]Max8907bSetup: Max8907bBatteryChargerMainBatt() failed. \n"));
+        return NV_FALSE;
+    }
+
+    // Power up Whistler thermal monitor (it is reported "not connected"
+    // if board info ROMs cannot be read when the thermal rail is enabled).
+    // This has to be done as early as possible because of 100ms+ power up
+    // delay before interface level shifters are operational.
+    pConnectivity =
+        NvOdmPeripheralGetGuid(NV_ODM_GUID('a','d','t','7','4','6','1',' '));
+    if (pConnectivity)
+    {
+        for (i = 0; i < pConnectivity->NumAddress; i++)
+        {
+            if (pConnectivity->AddressList[i].Interface == NvOdmIoModule_Vdd)
+            {
+                NvU32 vddRail = pConnectivity->AddressList[i].Address;
+                NvU32 mv =
+                    Max8907bSupplyInfoTable[vddRail].cap.requestMilliVolts;
+                if(!Max8907bSetVoltage(hDevice, vddRail, mv, NULL))
+                {
+                    NVODMPMU_PRINTF(("[NVODM PMU]Max8907bSetup:"
+                                     " Thermal rail setup failed. \n"));
+                }
+            }
+        }
+    }
+
+    // The interrupt assumes not supported until Max8907bInterruptHandler() is called.
+    ((Max8907bPrivData*)hDevice->pPrivate)->pmuInterruptSupported = NV_FALSE;
+
+    return NV_TRUE;
+
+fail:
+    Max8907bRelease(hDevice);
+    return NV_FALSE;
+}
+
+void
+Max8907bRelease(NvOdmPmuDeviceHandle hDevice)
+{
+    if (hDevice->pPrivate != NULL)
+    {
+        if (((Max8907bPrivData*)hDevice->pPrivate)->hOdmPmuSevice != NULL)
+        {
+            NvOdmServicesPmuClose(((Max8907bPrivData*)hDevice->pPrivate)->hOdmPmuSevice);
+            ((Max8907bPrivData*)hDevice->pPrivate)->hOdmPmuSevice = NULL;
+        }
+
+        if (((Max8907bPrivData*)hDevice->pPrivate)->hOdmI2C != NULL)
+        {
+            NvOdmI2cClose(((Max8907bPrivData*)hDevice->pPrivate)->hOdmI2C);
+            ((Max8907bPrivData*)hDevice->pPrivate)->hOdmI2C = NULL;
+        }
+
+        if (((Max8907bPrivData*)hDevice->pPrivate)->supplyRefCntTable != NULL)
+        {
+            NvOdmOsFree(((Max8907bPrivData*)hDevice->pPrivate)->supplyRefCntTable);
+            ((Max8907bPrivData*)hDevice->pPrivate)->supplyRefCntTable = NULL;
+        }
+
+        if (((Max8907bPrivData*)hDevice->pPrivate)->pVoltages != NULL)
+        {
+            NvOdmOsFree(((Max8907bPrivData*)hDevice->pPrivate)->pVoltages);
+            ((Max8907bPrivData*)hDevice->pPrivate)->pVoltages = NULL;
+        }
+
+
+        NvOdmOsFree(hDevice->pPrivate);
+        hDevice->pPrivate = NULL;
+    }
+}
+
+NvBool
+Max8907bGetVoltage(
+    NvOdmPmuDeviceHandle hDevice,
+    NvU32 vddRail,
+    NvU32* pMilliVolts)
+{
+    NV_ASSERT(hDevice);
+    NV_ASSERT(pMilliVolts);
+    NV_ASSERT(vddRail < Max8907bPmuSupply_Num);
+
+    // RTC is a special case, since it's "always on"
+    if (vddRail == Max8907bPmuSupply_VRTC)
+    {
+        // Fixed voltage
+        *pMilliVolts = MAX8907B_MAX_OUTPUT_VOLTAGE_RTC;
+    }
+    else if (vddRail == Max8907bPmuSupply_EXT_DCDC_1)
+    {
+        // Fixed voltage
+        *pMilliVolts = MAX8907B_REQUESTVOLTAGE_EXT_DCDC_1;
+    }
+    else if (vddRail == Max8907bPmuSupply_EXT_DCDC_3)
+    {
+#if defined(MAX8907B_USE_FAN5355_VOLTAGE_SCALING)
+        if (!Fan5355ReadVoltageReg(hDevice, vddRail, pMilliVolts))
+            return NV_FALSE;
+#else
+        // Fixed voltage
+        *pMilliVolts = MAX8907B_REQUESTVOLTAGE_EXT_DCDC_3;
+#endif
+    }
+    else if((vddRail == MIC2826PmuSupply_BUCK) ||
+            (vddRail == MIC2826PmuSupply_LDO1) ||
+            (vddRail == MIC2826PmuSupply_LDO2) ||
+            (vddRail == MIC2826PmuSupply_LDO3))
+    {
+        // Secondary PMU Case
+        if(! MIC2826ReadVoltageReg(hDevice, (vddRail), pMilliVolts))
+            return NV_FALSE;
+    }
+    else if (vddRail == Max8907bLxV1_Ad5258_DPM_EXT_DCDC_7)
+    {
+        // External DCDC controlled by LX_V1, and scaled by DPM
+        if (!Max8907bLxV1Ad5258ReadVoltageReg(hDevice, vddRail, pMilliVolts))
+            return NV_FALSE;
+    }
+    else
+    {
+        if (!Max8907bReadVoltageReg(hDevice, vddRail, pMilliVolts))
+            return NV_FALSE;
+    }
+
+    return NV_TRUE;
+}
+
+
+static  NvBool
+Tca6416UsbVbusControl(
+    NvOdmPmuDeviceHandle hDevice,
+    NvU32 vddRail,
+    NvU32 MilliVolts)
+{
+    const Max8907bPmuSupplyInfo *pSupplyInfo = &Max8907bSupplyInfoTable[vddRail];
+    NvU32 PortNo;
+    NvU32 PinNo;
+
+    // Get port number and pin number
+    PortNo = pSupplyInfo->OutputPort;
+    PinNo = pSupplyInfo->PmuGpio;
+
+    // Configure port pin as output
+    if (!Tca6416ConfigPortPin(hDevice, PortNo, PinNo, GpioPinMode_Output))
+        return NV_FALSE;
+
+    if (MilliVolts == ODM_VOLTAGE_OFF)  // to disable VBUS
+    {
+        // Set Low  on pin
+        if (!Tca6416WritePortPin(hDevice, PortNo, PinNo, GpioPinState_Low))
+            return NV_FALSE;
+    }
+    else  // to Enable VBUS
+    {
+        // Set high  on pin
+        if (!Tca6416WritePortPin(hDevice, PortNo, PinNo, GpioPinState_High))
+            return NV_FALSE;
+    }
+    return NV_TRUE;
+}
+
+NvBool
+Max8907bSetVoltage(
+    NvOdmPmuDeviceHandle hDevice,
+    NvU32 vddRail,
+    NvU32 MilliVolts,
+    NvU32* pSettleMicroSeconds)
+{
+    NV_ASSERT(hDevice);
+    NV_ASSERT(vddRail < Max8907bPmuSupply_Num);
+
+    if ( Max8907bSupplyInfoTable[vddRail].cap.OdmProtected == NV_TRUE)
+    {
+        NVODMPMU_PRINTF(("The voltage is protected and cannot be set.\n"));
+        return NV_TRUE;
+    }
+
+    if ((MilliVolts == ODM_VOLTAGE_ENABLE_EXT_ONOFF) ||
+        (MilliVolts == ODM_VOLTAGE_DISABLE_EXT_ONOFF))
+    {
+        return Max8907bPwrEnAttach(hDevice, (Max8907bPmuSupply)vddRail,
+            (MilliVolts == ODM_VOLTAGE_ENABLE_EXT_ONOFF));
+    }
+
+    if ((MilliVolts == ODM_VOLTAGE_OFF) ||
+        ((MilliVolts <=  Max8907bSupplyInfoTable[vddRail].cap.MaxMilliVolts) &&
+         (MilliVolts >=  Max8907bSupplyInfoTable[vddRail].cap.MinMilliVolts)))
+    {
+        if ((vddRail == Max8907bPmuSupply_EXT_DCDC_1) ||
+            (vddRail == Max8907bPmuSupply_EXT_DCDC_3) ||
+            (vddRail == Max8907bPmuSupply_EXT_DCDC_3_USB1) ||
+            (vddRail == Max8907bPmuSupply_EXT_DCDC_3_USB3))
+        {
+            // Use External DC/DC switcher
+            if (!Fan5355WriteVoltageReg(hDevice, vddRail, MilliVolts))
+                return NV_FALSE;
+        }
+        else if((vddRail == MIC2826PmuSupply_BUCK) ||
+                (vddRail == MIC2826PmuSupply_LDO1) ||
+                (vddRail == MIC2826PmuSupply_LDO2) ||
+                (vddRail == MIC2826PmuSupply_LDO3))
+        {
+            // Secondary PMU Case
+            if (!MIC2826WriteVoltageReg(hDevice, vddRail, MilliVolts, pSettleMicroSeconds))
+                return NV_FALSE;
+        }
+        else if (vddRail == Max8907bLxV1_Ad5258_DPM_EXT_DCDC_7)
+        {
+            // External DCDC controlled by LX_V1, and scaled by DPM
+            if (!Max8907bLxV1Ad5258WriteVoltageReg(
+                hDevice, vddRail, MilliVolts, pSettleMicroSeconds))
+                return NV_FALSE;
+        }
+        else
+        {
+            if (!Max8907bWriteVoltageReg(hDevice, vddRail, MilliVolts, pSettleMicroSeconds))
+                return NV_FALSE;
+        }
+    }
+    else
+    {
+        NVODMPMU_PRINTF(("The requested voltage is not supported.\n"));
+        return NV_FALSE;
+    }
+
+    // Check whether need to enable VBUS for any of the USB Instance
+    if ((vddRail == Max8907bPmuSupply_EXT_DCDC_3_USB1) ||
+        (vddRail == Max8907bPmuSupply_EXT_DCDC_3_USB3))
+    {
+        // Enable  VBUS for USB1 or USB3
+       if (!Tca6416UsbVbusControl(hDevice, vddRail, MilliVolts))
+            return NV_FALSE;
+    }
+    return NV_TRUE;
+}
+
+void
+Max8907bGetCapabilities(
+    NvU32 vddRail,
+    NvOdmPmuVddRailCapabilities* pCapabilities)
+{
+    NV_ASSERT(pCapabilities);
+    NV_ASSERT(vddRail < Max8907bPmuSupply_Num);
+
+    *pCapabilities = Max8907bSupplyInfoTable[vddRail].cap;
+}
+
+NvBool
+Max8907bGetAcLineStatus(
+    NvOdmPmuDeviceHandle hDevice,
+    NvOdmPmuAcLineStatus *pStatus)
+{
+    NvBool acLineStatus = NV_FALSE;
+
+    NV_ASSERT(hDevice);
+    NV_ASSERT(pStatus);
+
+    // check if battery is present
+    if (((Max8907bPrivData*)hDevice->pPrivate)->battPresence == NV_FALSE)
+    {
+        *pStatus = NvOdmPmuAcLine_Online;
+        return NV_TRUE;
+    }
+
+    if ( ((Max8907bPrivData*)hDevice->pPrivate)->pmuInterruptSupported == NV_TRUE )
+    {
+        if ( ((Max8907bPrivData*)hDevice->pPrivate)->pmuStatus.mChgPresent == NV_TRUE )
+        {
+            *pStatus = NvOdmPmuAcLine_Online;
+            acLineStatus = NV_TRUE;
+        }
+        else
+        {
+            *pStatus = NvOdmPmuAcLine_Offline;
+            acLineStatus = NV_FALSE;
+        }
+    }
+    else
+    {
+        // battery is present, now check if charger present
+        if (!Max8907bBatteryChargerOK(hDevice, &acLineStatus))
+        {
+            NVODMPMU_PRINTF(("[NVODM PMU] Max8907bGetAcLineStatus: Error in checking main charger presence.\n"));
+            return NV_FALSE;
+        }
+
+        if (acLineStatus == NV_TRUE)
+            *pStatus = NvOdmPmuAcLine_Online;
+        else
+            *pStatus = NvOdmPmuAcLine_Offline;
+    }
+
+#if ALWAYS_ONLINE
+    // Currently on Whistler battery is not used, and AC is connected to PMU
+    // battery input, causing false battery presence detection. Voyager battery
+    // management is don't care at the moment. Hence, force OnLine status.
+    *pStatus = NvOdmPmuAcLine_Online;
+#endif
+
+    return NV_TRUE;
+}
+
+NvBool
+Max8907bGetBatteryStatus(
+    NvOdmPmuDeviceHandle hDevice,
+    NvOdmPmuBatteryInstance batteryInst,
+    NvU8 *pStatus)
+{
+    NvU8 status = 0;
+
+    NV_ASSERT(hDevice);
+    NV_ASSERT(pStatus);
+    NV_ASSERT(batteryInst <= NvOdmPmuBatteryInst_Num);
+
+    if (batteryInst == NvOdmPmuBatteryInst_Main)
+    {
+        if ( ((Max8907bPrivData*)hDevice->pPrivate)->battPresence == NV_TRUE )
+        {
+            NvOdmPmuAcLineStatus stat = NvOdmPmuAcLine_Offline;
+            NvU32 VBatSense = 0;
+            if (!Max8907bGetAcLineStatus(hDevice, &stat))
+                return NV_FALSE;
+
+            if (stat == NvOdmPmuAcLine_Online)
+            {
+                if ( ((Max8907bPrivData*)hDevice->pPrivate)->pmuInterruptSupported == NV_TRUE )
+                {
+                    if ( ((Max8907bPrivData*)hDevice->pPrivate)->pmuStatus.batFull == NV_FALSE )
+                        status = NVODM_BATTERY_STATUS_CHARGING;
+                }
+                else
+                {
+                    NvBool batFull = NV_FALSE;
+                    if (!Max8907bBatteryChargerMainBattFull(hDevice, &batFull))
+                        return NV_FALSE;
+                    if (batFull == NV_FALSE)
+                        status = NVODM_BATTERY_STATUS_CHARGING;
+                }
+            }
+
+            // Get VBatSense
+            if (!Max8907bAdcVBatSenseRead(hDevice, &VBatSense))
+                return NV_FALSE;
+
+            // TO DO: Update status based on VBatSense
+        }
+        else
+        {
+            /* Battery is actually not present */
+            status = NVODM_BATTERY_STATUS_NO_BATTERY;
+        }
+        *pStatus = status;
+    }
+    else
+    {
+        *pStatus = NVODM_BATTERY_STATUS_UNKNOWN;
+    }
+
+    return NV_TRUE;
+}
+
+NvBool
+Max8907bGetBatteryData(
+    NvOdmPmuDeviceHandle hDevice,
+    NvOdmPmuBatteryInstance batteryInst,
+    NvOdmPmuBatteryData *pData)
+{
+    NvOdmPmuBatteryData batteryData;
+
+    batteryData.batteryAverageCurrent  = NVODM_BATTERY_DATA_UNKNOWN;
+    batteryData.batteryAverageInterval = NVODM_BATTERY_DATA_UNKNOWN;
+    batteryData.batteryCurrent         = NVODM_BATTERY_DATA_UNKNOWN;
+    batteryData.batteryLifePercent     = NVODM_BATTERY_DATA_UNKNOWN;
+    batteryData.batteryLifeTime        = NVODM_BATTERY_DATA_UNKNOWN;
+    batteryData.batteryMahConsumed     = NVODM_BATTERY_DATA_UNKNOWN;
+    batteryData.batteryTemperature     = NVODM_BATTERY_DATA_UNKNOWN;
+    batteryData.batteryVoltage         = NVODM_BATTERY_DATA_UNKNOWN;
+
+    NV_ASSERT(hDevice);
+    NV_ASSERT(pData);
+    NV_ASSERT(batteryInst <= NvOdmPmuBatteryInst_Num);
+
+    if (batteryInst == NvOdmPmuBatteryInst_Main)
+    {
+        NvU32 VBatSense = 0;
+        NvU32 VBatTemp  = 0;
+
+        if (((Max8907bPrivData*)hDevice->pPrivate)->battPresence == NV_TRUE)
+        {
+            /* retrieve Battery voltage and temperature */
+
+            // Get VBatSense
+            if (!Max8907bAdcVBatSenseRead(hDevice, &VBatSense))
+            {
+                NVODMPMU_PRINTF(("Error reading VBATSense. \n"));
+                return NV_FALSE;
+            }
+
+            // Get VBatTemp
+            if (!Max8907bAdcVBatTempRead(hDevice, &VBatTemp))
+            {
+                NVODMPMU_PRINTF(("Error reading VBATSense. \n"));
+                return NV_FALSE;
+            }
+
+            batteryData.batteryVoltage = VBatSense;
+            batteryData.batteryTemperature = Max8907bBatteryTemperature(VBatSense, VBatTemp);
+        }
+
+        *pData = batteryData;
+    }
+    else
+    {
+        *pData = batteryData;
+    }
+
+    return NV_TRUE;
+}
+
+void
+Max8907bGetBatteryFullLifeTime(
+    NvOdmPmuDeviceHandle hDevice,
+    NvOdmPmuBatteryInstance batteryInst,
+    NvU32 *pLifeTime)
+{
+    *pLifeTime = NVODM_BATTERY_DATA_UNKNOWN;
+}
+
+void
+Max8907bGetBatteryChemistry(
+    NvOdmPmuDeviceHandle hDevice,
+    NvOdmPmuBatteryInstance batteryInst,
+    NvOdmPmuBatteryChemistry *pChemistry)
+{
+    *pChemistry = NvOdmPmuBatteryChemistry_LION;
+}
+
+NvBool
+Max8907bSetChargingCurrent(
+    NvOdmPmuDeviceHandle hDevice,
+    NvOdmPmuChargingPath chargingPath,
+    NvU32 chargingCurrentLimitMa,
+    NvOdmUsbChargerType ChargerType)
+{
+    NvU8 data = 0;
+    NvU8 fchg = 0;
+    NV_ASSERT(hDevice);
+
+    // If no battery is connected, then do nothing.
+    if (((Max8907bPrivData*)hDevice->pPrivate)->battPresence == NV_FALSE)
+        return NV_TRUE;
+
+    // If requested current is more than supported maximum then limit to supported.
+    if ( chargingCurrentLimitMa > MAX_CHARGER_LIMIT_MA )
+        chargingCurrentLimitMa = MAX_CHARGER_LIMIT_MA;
+
+    // If dedicated charger is connected, request maximum current.
+    if (chargingPath == NvOdmPmuChargingPath_UsbBus)
+    {
+        switch (ChargerType)
+        {
+            case NvOdmUsbChargerType_SJ:
+            case NvOdmUsbChargerType_SK:
+            case NvOdmUsbChargerType_SE1:
+            case NvOdmUsbChargerType_SE0:
+                chargingCurrentLimitMa = MAX_CHARGER_LIMIT_MA;
+                break;
+            case NvOdmUsbChargerType_UsbHost:
+            default:
+                break;
+        }
+    }
+
+    // Read the current charger setup.
+    if ( !Max8907bI2cRead8(hDevice, MAX8907B_CHG_CNTL1, &data) )
+        return NV_FALSE;
+
+    // Set charging current to the value no larger than requested.
+    // If less than 85mA is requested, set to 85mA.
+    // If larger than 1000mA is requested, set to 1000mA.
+    if (chargingCurrentLimitMa >= 1000)
+        fchg = MAX8907B_CHG_CNTL1_FCHG_1000MA;
+    else if (chargingCurrentLimitMa >= 900)
+        fchg = MAX8907B_CHG_CNTL1_FCHG_900MA;
+    else if (chargingCurrentLimitMa >= 800)
+        fchg = MAX8907B_CHG_CNTL1_FCHG_800MA;
+    else if (chargingCurrentLimitMa >= 700)
+        fchg = MAX8907B_CHG_CNTL1_FCHG_700MA;
+    else if (chargingCurrentLimitMa >= 600)
+        fchg = MAX8907B_CHG_CNTL1_FCHG_600MA;
+    else if (chargingCurrentLimitMa >= 460)
+        fchg = MAX8907B_CHG_CNTL1_FCHG_460MA;
+    else if (chargingCurrentLimitMa >= 300)
+        fchg = MAX8907B_CHG_CNTL1_FCHG_300MA;
+    else
+        fchg = MAX8907B_CHG_CNTL1_FCHG_85MA;
+
+    data &= ~(MAX8907B_CHG_CNTL1_FCHG_MASK <<
+              MAX8907B_CHG_CNTL1_FCHG_SHIFT);
+    data |= fchg << MAX8907B_CHG_CNTL1_FCHG_SHIFT;
+
+    // Turn off the charger path if the requested current limit is 0mA.
+    // Turn on the path otherwise.
+    if ( chargingCurrentLimitMa == 0 )
+    {
+        // off
+        data |= (MAX8907B_CHG_CNTL1_NOT_CHGEN_MASK <<
+                 MAX8907B_CHG_CNTL1_NOT_CHGEN_SHIFT);
+    }
+    else
+    {
+        // on
+        data &= ~(MAX8907B_CHG_CNTL1_NOT_CHGEN_MASK <<
+                  MAX8907B_CHG_CNTL1_NOT_CHGEN_SHIFT);
+    }
+
+    // Update the current charger setup.
+    if ( !Max8907bI2cWrite8(hDevice, MAX8907B_CHG_CNTL1, data) )
+        return NV_FALSE;
+
+    return NV_TRUE;
+}
+
+void Max8907bInterruptHandler( NvOdmPmuDeviceHandle  hDevice)
+{
+    // If the interrupt handle is called, the interrupt is supported.
+    ((Max8907bPrivData*)hDevice->pPrivate)->pmuInterruptSupported = NV_TRUE;
+
+    Max8907bInterruptHandler_int(hDevice, &((Max8907bPrivData*)hDevice->pPrivate)->pmuStatus);
+}
+
+/****************   Secondary PMU MIC2826 Programming  */
+static NvBool
+MIC2826ReadVoltageReg(
+    NvOdmPmuDeviceHandle hDevice,
+    NvU32 vddRail,
+    NvU32* pMilliVolts)
+{
+    NvU32 milliVolts = 0;
+    NvU32 index = 0;
+    NvU8 data = 0;
+    const Max8907bPmuSupplyInfo *pSupplyInfo = &Max8907bSupplyInfoTable[vddRail];
+
+    NV_ASSERT(pSupplyInfo->supply == (Max8907bPmuSupply)vddRail);
+
+    if(! MIC2826I2cRead8(hDevice, pSupplyInfo->ControlRegAddr, &data))
+        return NV_FALSE;
+
+    // convert Data to MilliVolts
+    if (!data) //OFF
+        milliVolts = 0;
+    else
+    {
+        // set voltage
+        if(vddRail == MIC2826PmuSupply_BUCK)
+        {
+            for(index=0;index<MIC2826_BUCK_Votage_Table_Size;index++)
+            {
+                if(data == MIC2826_BUCK_Votage_Table[index])
+                    break;
+            }
+            if(index  < 0x10)
+            {
+                milliVolts = index * MIC2826_BUCK_VOLTAGE_STEP_25MV + MIC2826_BUCK_VOLTAGE_OFFSET ;
+            }else
+            {
+                milliVolts = 1200 + ((index - 0x10) * MIC2826_BUCK_VOLTAGE_STEP_50MV) ;
+            }
+        }
+        else if ( (vddRail == MIC2826PmuSupply_LDO1) ||
+                  (vddRail == MIC2826PmuSupply_LDO2) ||
+                  (vddRail == MIC2826PmuSupply_LDO3))
+        {
+            for(index=0;index<MIC2826_LDO_Votage_Table_Size;index++)
+            {
+                if(data == MIC2826_BUCK_Votage_Table[index])
+                   break;
+            }
+            milliVolts = (index * pSupplyInfo->cap.StepMilliVolts) + MIC2826_LDO_VOLTAGE_OFFSET;
+        }
+    }
+
+    *pMilliVolts = milliVolts;
+
+    return NV_TRUE;
+}
+
+
+static NvBool
+MIC2826WriteVoltageReg(
+    NvOdmPmuDeviceHandle hDevice,
+    NvU32 vddRail,
+    NvU32  MilliVolts,
+    NvU32* pSettleMicroSeconds)
+{
+    NvU8 data = 0;
+    NvU32 index = 0;
+    NvU32 settleTime = 0;
+    const Max8907bPmuSupplyInfo* pSupplyInfo = &Max8907bSupplyInfoTable[vddRail];
+
+    NV_ASSERT(pSupplyInfo->supply == (Max8907bPmuSupply)vddRail);
+
+    // Require to turn off the supply
+    if (MilliVolts == ODM_VOLTAGE_OFF)
+    {
+        // check if the supply can be turned off
+        if (((Max8907bPrivData*)hDevice->pPrivate)->supplyRefCntTable[pSupplyInfo->supply] == 1)
+        {
+
+            // Read the current supply info
+            if(! MIC2826I2cRead8(hDevice, MIC2826_REG_ADDR_ENABLE, &data))
+                return NV_FALSE;
+
+            // turn off the supply of particular rail
+            if(vddRail == MIC2826PmuSupply_BUCK)
+                data &= MIC2826_REG_DISABLE_BK;
+            else if(vddRail == MIC2826PmuSupply_LDO1)
+                data &= MIC2826_REG_DISABLE_LDO1;
+            else if(vddRail == MIC2826PmuSupply_LDO2)
+                data &= MIC2826_REG_DISABLE_LDO2;
+            else if(vddRail == MIC2826PmuSupply_LDO3)
+                data &= MIC2826_REG_DISABLE_LDO3;
+
+            if (!MIC2826I2cWrite8(hDevice, MIC2826_REG_ADDR_ENABLE, data))
+                return NV_FALSE;
+        }
+
+        //TODO: check if the supply input can be turned off
+        if (((Max8907bPrivData*)hDevice->pPrivate)->supplyRefCntTable[pSupplyInfo->supply] != 0)
+            ((Max8907bPrivData*)hDevice->pPrivate)->supplyRefCntTable[pSupplyInfo->supply] --;
+
+        if (pSettleMicroSeconds != NULL)
+            *pSettleMicroSeconds = settleTime;
+        else
+            NvOdmOsWaitUS(settleTime);
+
+        return NV_TRUE;
+    }
+
+    // turn on supply
+    if (((Max8907bPrivData*)hDevice->pPrivate)->supplyRefCntTable[pSupplyInfo->supply] == 0)
+    {
+        {
+            // Read the current supply info
+            if(! MIC2826I2cRead8(hDevice, MIC2826_REG_ADDR_ENABLE, &data))
+                return NV_FALSE;
+
+            // turn on the supply of particular rail
+           if(vddRail == MIC2826PmuSupply_BUCK)
+                data |= MIC2826_REG_ENABLE_BK;
+           else if(vddRail == MIC2826PmuSupply_LDO1)
+                data |= MIC2826_REG_ENABLE_LDO1;
+           else if(vddRail == MIC2826PmuSupply_LDO2)
+                data |= MIC2826_REG_ENABLE_LDO2;
+           else if(vddRail == MIC2826PmuSupply_LDO3)
+                data |= MIC2826_REG_ENABLE_LDO3;
+
+           if (!MIC2826I2cWrite8(hDevice, MIC2826_REG_ADDR_ENABLE, data))
+                return NV_FALSE;
+        }
+    }
+
+    // set voltage
+    if(vddRail == MIC2826PmuSupply_BUCK)
+    {
+       if(MilliVolts < 1200)
+       {
+           index = (MilliVolts - MIC2826_BUCK_VOLTAGE_OFFSET) / MIC2826_BUCK_VOLTAGE_STEP_25MV ;
+       }else
+       {
+           index = 0x10 + ((MilliVolts - 1200) / MIC2826_BUCK_VOLTAGE_STEP_50MV) ;
+       }
+       data = MIC2826_BUCK_Votage_Table[index];
+    }
+    else if ( (vddRail == MIC2826PmuSupply_LDO1) ||
+              (vddRail == MIC2826PmuSupply_LDO2) ||
+              (vddRail == MIC2826PmuSupply_LDO3))
+    {
+        index = (MilliVolts - MIC2826_LDO_VOLTAGE_OFFSET) / pSupplyInfo->cap.StepMilliVolts;
+        data = MIC2826_LDO_Votage_Table[index];
+    }
+
+    // Program the Rail Voltage
+    if(! MIC2826I2cRead8(hDevice, pSupplyInfo->ControlRegAddr, &data))
+         return NV_FALSE;
+
+    ((Max8907bPrivData*)hDevice->pPrivate)->supplyRefCntTable[pSupplyInfo->supply] ++;
+
+    // TODO: turn on supply input if necessary
+    if (pSettleMicroSeconds != NULL)
+        *pSettleMicroSeconds = settleTime;
+    else
+        NvOdmOsWaitUS(settleTime);
+
+    return NV_TRUE;
+}
+
diff --git a/arch/arm/mach-tegra/odm_kit/adaptations/pmu/max8907b/max8907b.h b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/max8907b/max8907b.h
new file mode 100644
index 000000000000..ce66a64c9716
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/max8907b/max8907b.h
@@ -0,0 +1,160 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_PMU_MAX8907B_H
+#define INCLUDED_PMU_MAX8907B_H
+
+#include "nvodm_pmu.h"
+#include"pmu_hal.h"
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+#if (NV_DEBUG)
+#define NVODMPMU_PRINTF(x)   NvOdmOsDebugPrintf x
+#else
+#define NVODMPMU_PRINTF(x)
+#endif
+
+typedef struct Max8907bStatusRec
+{
+    /* Low Battery voltage detected by BVM */
+    NvBool lowBatt;
+
+    /* PMU high temperature */
+    NvBool highTemp;
+
+    /* Main charger Present */
+    NvBool mChgPresent;
+
+    /* battery Full */
+    NvBool batFull;
+
+} Max8907bStatus;
+
+typedef struct
+{
+    /* The handle to the I2C */
+    NvOdmServicesI2cHandle hOdmI2C;
+
+    /* The odm pmu service handle */
+    NvOdmServicesPmuHandle hOdmPmuSevice;
+    
+    /* the PMU I2C device Address */
+    NvU32 DeviceAddr;
+
+    /* the PMU status */
+    Max8907bStatus pmuStatus;
+
+    /* battery presence */
+    NvBool battPresence;
+
+    /* PMU interrupt support enabled */
+    NvBool pmuInterruptSupported;
+
+    /* The ref cnt table of the power supplies */
+    NvU32 *supplyRefCntTable;
+
+    /* The pointer to supply voltages shadow */
+    NvU32 *pVoltages;
+
+} Max8907bPrivData;
+
+NvBool 
+Max8907bSetup(NvOdmPmuDeviceHandle hDevice);
+
+void 
+Max8907bRelease(NvOdmPmuDeviceHandle hDevice);
+
+NvBool
+Max8907bGetVoltage(
+    NvOdmPmuDeviceHandle hDevice,
+    NvU32 vddRail,
+    NvU32* pMilliVolts);
+
+NvBool
+Max8907bSetVoltage(
+    NvOdmPmuDeviceHandle hDevice,
+    NvU32 vddRail,
+    NvU32 MilliVolts,
+    NvU32* pSettleMicroSeconds);
+
+void
+Max8907bGetCapabilities(
+    NvU32 vddRail,
+    NvOdmPmuVddRailCapabilities* pCapabilities);
+
+NvBool
+Max8907bGetAcLineStatus(
+    NvOdmPmuDeviceHandle hDevice,
+    NvOdmPmuAcLineStatus *pStatus);
+
+NvBool
+Max8907bGetBatteryStatus(
+    NvOdmPmuDeviceHandle hDevice,
+    NvOdmPmuBatteryInstance batteryInst,
+    NvU8 *pStatus);
+
+NvBool
+Max8907bGetBatteryData(
+    NvOdmPmuDeviceHandle hDevice,
+    NvOdmPmuBatteryInstance batteryInst,
+    NvOdmPmuBatteryData *pData);
+
+void
+Max8907bGetBatteryFullLifeTime(
+    NvOdmPmuDeviceHandle hDevice,
+    NvOdmPmuBatteryInstance batteryInst,
+    NvU32 *pLifeTime);
+
+void
+Max8907bGetBatteryChemistry(
+    NvOdmPmuDeviceHandle hDevice,
+    NvOdmPmuBatteryInstance batteryInst,
+    NvOdmPmuBatteryChemistry *pChemistry);
+
+NvBool
+Max8907bSetChargingCurrent(
+    NvOdmPmuDeviceHandle hDevice,
+    NvOdmPmuChargingPath chargingPath,
+    NvU32 chargingCurrentLimitMa,
+    NvOdmUsbChargerType ChargerType); 
+
+void Max8907bInterruptHandler( NvOdmPmuDeviceHandle  hDevice);
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif // INCLUDED_PMU_MAX8907B_H
diff --git a/arch/arm/mach-tegra/odm_kit/adaptations/pmu/max8907b/max8907b_adc.c b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/max8907b/max8907b_adc.c
new file mode 100644
index 000000000000..14d2c0d87a1a
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/max8907b/max8907b_adc.c
@@ -0,0 +1,101 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include "max8907b.h"
+#include "max8907b_adc.h"
+#include "max8907b_i2c.h"
+#include "max8907b_reg.h"
+
+NvBool 
+Max8907bAdcVBatSenseRead(
+    NvOdmPmuDeviceHandle hDevice, 
+    NvU32 *volt)
+{
+#if 0
+    NvU32 timeout = 0;
+    NvU8  dataS1  = 0;
+
+    NV_ASSERT(hDevice);
+    NV_ASSERT(volt);
+
+    // Configure ADC (conversion cycle, resolution, etc...)
+
+    // Start conversion
+
+    // Wait for conversion
+
+    // Make sure conversion is complete (or timeout or error)
+
+    // Get result
+    *volt = << compute >>;
+
+#endif
+    *volt = 0;
+    return NV_TRUE;
+}
+
+NvBool 
+Max8907bAdcVBatTempRead(
+    NvOdmPmuDeviceHandle hDevice, 
+    NvU32 *volt)
+{
+#if 0
+    NvU32 timeout = 0;
+    NvU8  dataS1  = 0;
+
+    NV_ASSERT(hDevice);
+    NV_ASSERT(volt);
+
+    // Setup ADC (resolution, etc..)
+
+    // Start conversion
+
+    // Wait for conversion
+
+    // Make sure conversion is complete (or timeout or error)
+
+    // Get result
+    *volt = << compute >>;
+
+#endif
+    *volt = 0;
+    return NV_TRUE;
+}
+
+NvU32
+Max8907bBatteryTemperature(
+    NvU32 VBatSense,
+    NvU32 VBatTemp)
+{
+    return 0;
+}
+
diff --git a/arch/arm/mach-tegra/odm_kit/adaptations/pmu/max8907b/max8907b_adc.h b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/max8907b/max8907b_adc.h
new file mode 100644
index 000000000000..5c3fb34fbf22
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/max8907b/max8907b_adc.h
@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_MAX8907B_ADC_HEADER
+#define INCLUDED_MAX8907B_ADC_HEADER
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+/* read voltage from ... */
+NvBool 
+Max8907bAdcVBatSenseRead(
+    NvOdmPmuDeviceHandle hDevice, 
+    NvU32 *volt);
+
+/* read bat temperature voltage from ADC */
+NvBool 
+Max8907bAdcVBatTempRead(
+    NvOdmPmuDeviceHandle hDevice, 
+    NvU32 *volt);
+
+/* Calculate the battery temperature */
+NvU32
+Max8907bBatteryTemperature(
+    NvU32 VBatSense,
+    NvU32 VBatTemp);
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif // INCLUDED_MAX8907B_ADC_HEADER
diff --git a/arch/arm/mach-tegra/odm_kit/adaptations/pmu/max8907b/max8907b_batterycharger.c b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/max8907b/max8907b_batterycharger.c
new file mode 100644
index 000000000000..00096508b05a
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/max8907b/max8907b_batterycharger.c
@@ -0,0 +1,97 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include "max8907b.h"
+#include "max8907b_batterycharger.h"
+#include "max8907b_reg.h"
+#include "max8907b_i2c.h"
+
+NvBool
+Max8907bBatteryChargerMainBatt(
+    NvOdmPmuDeviceHandle hDevice,
+    NvBool *status)
+{
+    NvU8 data = 0;
+    
+    if(!Max8907bI2cRead8(hDevice, MAX8907B_CHG_STAT, &data))
+        return NV_FALSE;
+
+    data = (data >> MAX8907B_CHG_STAT_MBDET_SHIFT) & MAX8907B_CHG_STAT_MBDET_MASK;
+    *status = (data == 0 ? NV_TRUE : NV_FALSE );    // MBDET low (0) = present
+    return NV_TRUE;
+}
+
+NvBool
+Max8907bBatteryChargerOK(
+    NvOdmPmuDeviceHandle hDevice,
+    NvBool *status)
+{
+    NvU8 data = 0;
+
+    if(!Max8907bI2cRead8(hDevice, MAX8907B_CHG_STAT, &data))
+        return NV_FALSE;
+
+    data = (data >> MAX8907B_CHG_STAT_VCHG_OK_SHIFT) & MAX8907B_CHG_STAT_VCHG_OK_MASK;
+    *status = (data == 0 ? NV_FALSE : NV_TRUE ); 
+    return NV_TRUE;
+}
+
+NvBool
+Max8907bBatteryChargerEnabled(
+    NvOdmPmuDeviceHandle hDevice,
+    NvBool *status)
+{
+    NvU8 data = 0;
+
+    if(!Max8907bI2cRead8(hDevice, MAX8907B_CHG_STAT, &data))
+        return NV_FALSE;
+
+    data = (data >> MAX8907B_CHG_STAT_CHG_EN_STAT_SHIFT) & MAX8907B_CHG_STAT_CHG_EN_STAT_MASK;
+    *status = (data == 0 ? NV_FALSE : NV_TRUE ); 
+    return NV_TRUE;
+}
+
+NvBool
+Max8907bBatteryChargerMainBattFull(
+    NvOdmPmuDeviceHandle hDevice,
+    NvBool *status)
+{
+    NvU8 data = 0;
+
+    if(!Max8907bI2cRead8(hDevice, MAX8907B_CHG_STAT, &data))
+        return NV_FALSE;
+
+    data = (data >> MAX8907B_CHG_STAT_MBATTLOW_SHIFT) & MAX8907B_CHG_STAT_MBATTLOW_MASK;
+    *status = (data == 0 ? NV_FALSE : NV_TRUE ); 
+    return NV_TRUE;
+}
+
diff --git a/arch/arm/mach-tegra/odm_kit/adaptations/pmu/max8907b/max8907b_batterycharger.h b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/max8907b/max8907b_batterycharger.h
new file mode 100644
index 000000000000..ab7d1212a44f
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/max8907b/max8907b_batterycharger.h
@@ -0,0 +1,71 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_MAX8907B_BATTERYCHARGER_HEADER
+#define INCLUDED_MAX8907B_BATTERYCHARGER_HEADER
+
+/* the battery charger functions */
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+/* check main battery presence */
+NvBool
+Max8907bBatteryChargerMainBatt(
+    NvOdmPmuDeviceHandle hDevice,
+    NvBool *status);
+
+/* check charger input voltage */
+NvBool
+Max8907bBatteryChargerOK(
+    NvOdmPmuDeviceHandle hDevice,
+    NvBool *status);
+
+/* check charger enable status */
+NvBool
+Max8907bBatteryChargerEnabled(
+    NvOdmPmuDeviceHandle hDevice,
+    NvBool *status);
+
+/* check main battery voltage status */
+NvBool
+Max8907bBatteryChargerMainBattFull(
+    NvOdmPmuDeviceHandle hDevice,
+    NvBool *status);
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif // INCLUDED_MAX8907B_BATTERYCHARGER_HEADER
+
diff --git a/arch/arm/mach-tegra/odm_kit/adaptations/pmu/max8907b/max8907b_i2c.c b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/max8907b/max8907b_i2c.c
new file mode 100644
index 000000000000..0f7a09446876
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/max8907b/max8907b_i2c.c
@@ -0,0 +1,365 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include "max8907b.h"
+#include "max8907b_i2c.h"
+#include "max8907b_reg.h"
+
+#define MAX8907B_I2C_SPEED_KHZ   400
+#define MAX8907B_I2C_RETRY_CNT     2
+
+// Maximum i2c transaction count
+#define MAX_TRANSACTION_COUNT 5
+
+NvBool Max8907bI2cWrite8(
+   NvOdmPmuDeviceHandle hDevice,
+   NvU8 Addr,
+   NvU8 Data)
+{
+    NvU32 i;
+    NvU8 WriteBuffer[2];
+    NvOdmI2cTransactionInfo TransactionInfo;
+    NvOdmI2cStatus status = NvOdmI2cStatus_Success;
+    Max8907bPrivData *hPmu = (Max8907bPrivData*)hDevice->pPrivate;
+
+    for (i = 0; i < MAX8907B_I2C_RETRY_CNT; i++)
+    {
+        WriteBuffer[0] = Addr & 0xFF;   // PMU offset
+        WriteBuffer[1] = Data & 0xFF;   // written data
+
+        TransactionInfo.Address = hPmu->DeviceAddr;
+        TransactionInfo.Buf = &WriteBuffer[0];
+        TransactionInfo.Flags = NVODM_I2C_IS_WRITE;
+        TransactionInfo.NumBytes = 2;
+
+        status = NvOdmI2cTransaction(hPmu->hOdmI2C, &TransactionInfo, 1,
+            MAX8907B_I2C_SPEED_KHZ, NV_WAIT_INFINITE);
+
+        if (status == NvOdmI2cStatus_Success)
+            return NV_TRUE;
+    }
+
+    // Transaction Error
+    switch (status)
+    {
+        case NvOdmI2cStatus_Timeout:
+            NVODMPMU_PRINTF(("NvOdmPmuI2cWrite8 Failed: Timeout\n"));
+            break;
+        case NvOdmI2cStatus_SlaveNotFound:
+        default:
+            NVODMPMU_PRINTF(("NvOdmPmuI2cWrite8 Failed: SlaveNotFound\n"));
+            break;
+    }
+    return NV_FALSE;
+}
+
+NvBool Max8907bI2cRead8(
+   NvOdmPmuDeviceHandle hDevice,
+   NvU8 Addr,
+   NvU8 *Data)
+{
+    NvU32 i;
+    NvU8 ReadBuffer = 0;
+    NvOdmI2cStatus  status = NvOdmI2cStatus_Success;
+    Max8907bPrivData *hPmu = (Max8907bPrivData*)hDevice->pPrivate;
+    NvOdmI2cTransactionInfo TransactionInfo[2];
+
+    for (i = 0; i < MAX8907B_I2C_RETRY_CNT; i++)
+    {
+        NvU32 TransactionCount = 0;
+        // Write the PMU offset
+        ReadBuffer = Addr & 0xFF;
+
+        TransactionInfo[TransactionCount].Address = hPmu->DeviceAddr;
+        TransactionInfo[TransactionCount].Buf = &ReadBuffer;
+        TransactionInfo[TransactionCount].Flags =
+            NVODM_I2C_IS_WRITE | NVODM_I2C_USE_REPEATED_START;
+        TransactionInfo[TransactionCount++].NumBytes = 1;
+
+        TransactionInfo[TransactionCount].Address = (hPmu->DeviceAddr | 0x1);
+        TransactionInfo[TransactionCount].Buf = &ReadBuffer;
+        TransactionInfo[TransactionCount].Flags = 0;
+        TransactionInfo[TransactionCount++].NumBytes = 1;
+
+        // Read data from PMU at the specified offset
+        status = NvOdmI2cTransaction(hPmu->hOdmI2C, &TransactionInfo[0],
+            TransactionCount, MAX8907B_I2C_SPEED_KHZ, NV_WAIT_INFINITE);
+
+        if (status == NvOdmI2cStatus_Success)
+        {
+            *Data = ReadBuffer;
+            return NV_TRUE;
+        }
+    }
+
+    // Transaction Error
+    switch (status)
+    {
+        case NvOdmI2cStatus_Timeout:
+            NVODMPMU_PRINTF(("NvOdmPmuI2cRead8 Failed: Timeout\n"));
+            break;
+        case NvOdmI2cStatus_SlaveNotFound:
+        default:
+            NVODMPMU_PRINTF(("NvOdmPmuI2cRead8 Failed: SlaveNotFound\n"));
+            break;
+    }
+    return NV_FALSE;
+}
+
+NvBool Max8907bI2cWrite32(
+   NvOdmPmuDeviceHandle hDevice,
+   NvU8 Addr,
+   NvU32 Data)
+{
+    NvU32 i;
+    NvU8 WriteBuffer[5];
+    NvOdmI2cStatus  status = NvOdmI2cStatus_Success;
+    Max8907bPrivData *hPmu = (Max8907bPrivData*)hDevice->pPrivate;
+    NvOdmI2cTransactionInfo TransactionInfo;
+
+    for (i = 0; i < MAX8907B_I2C_RETRY_CNT; i++)
+    {
+        WriteBuffer[0] = (NvU8)(Addr & 0xFF);
+        WriteBuffer[1] = (NvU8)((Data >> 24) & 0xFF);
+        WriteBuffer[2] = (NvU8)((Data >> 16) & 0xFF);
+        WriteBuffer[3] = (NvU8)((Data >>  8) & 0xFF);
+        WriteBuffer[4] = (NvU8)(Data & 0xFF);
+
+        TransactionInfo.Address = hPmu->DeviceAddr;
+        TransactionInfo.Buf = &WriteBuffer[0];
+        TransactionInfo.Flags = NVODM_I2C_IS_WRITE;
+        TransactionInfo.NumBytes = 5;
+
+        status = NvOdmI2cTransaction(hPmu->hOdmI2C, &TransactionInfo, 1,
+            MAX8907B_I2C_SPEED_KHZ, NV_WAIT_INFINITE);
+
+        if (status == NvOdmI2cStatus_Success)
+            return NV_TRUE;
+    }
+
+    // Transaction Error
+    switch (status)
+    {
+        case NvOdmI2cStatus_Timeout:
+            NVODMPMU_PRINTF(("NvOdmPmuI2cWrite32 Failed: Timeout\n"));
+            break;
+        case NvOdmI2cStatus_SlaveNotFound:
+        default:
+            NVODMPMU_PRINTF(("NvOdmPmuI2cWrite32 Failed: SlaveNotFound\n"));
+            break;
+    }
+    return NV_FALSE;
+}
+
+NvBool Max8907bI2cRead32(
+   NvOdmPmuDeviceHandle hDevice,
+   NvU8 Addr,
+   NvU32 *Data)
+{
+    NvU32 i;
+    NvU8 ReadBuffer[5];
+    NvOdmI2cStatus  status = NvOdmI2cStatus_Success;
+    Max8907bPrivData *hPmu = (Max8907bPrivData*)hDevice->pPrivate;
+    NvOdmI2cTransactionInfo TransactionInfo[2];
+
+    for (i = 0; i < MAX8907B_I2C_RETRY_CNT; i++)
+    {
+        NvU32 TransactionCount = 0;
+        ReadBuffer[0] = Addr & 0xFF;
+
+        TransactionInfo[TransactionCount].Address = hPmu->DeviceAddr;
+        TransactionInfo[TransactionCount].Buf = &ReadBuffer[0];
+        TransactionInfo[TransactionCount].Flags =
+            NVODM_I2C_IS_WRITE | NVODM_I2C_USE_REPEATED_START;
+        TransactionInfo[TransactionCount++].NumBytes = 1;
+
+        TransactionInfo[TransactionCount].Address = (hPmu->DeviceAddr | 0x1);
+        TransactionInfo[TransactionCount].Buf = &ReadBuffer[0];
+        TransactionInfo[TransactionCount].Flags = 0;
+        TransactionInfo[TransactionCount++].NumBytes = 4;
+
+        status = NvOdmI2cTransaction(hPmu->hOdmI2C, &TransactionInfo[0],
+            TransactionCount, MAX8907B_I2C_SPEED_KHZ, NV_WAIT_INFINITE);
+
+        if (status == NvOdmI2cStatus_Success)
+        {
+            *Data = (ReadBuffer[0] << 24) | (ReadBuffer[1] << 16) |
+                    (ReadBuffer[2] << 8) | ReadBuffer[3];
+
+            return NV_TRUE;
+        }
+    }
+
+    // Transaction Error
+    switch (status)
+    {
+        case NvOdmI2cStatus_Timeout:
+            NVODMPMU_PRINTF(("NvOdmPmuI2cRead32 Failed: Timeout\n"));
+            break;
+        case NvOdmI2cStatus_SlaveNotFound:
+        default:
+            NVODMPMU_PRINTF(("NvOdmPmuI2cRead32 Failed: SlaveNotFound\n"));
+            break;
+    }
+    return NV_FALSE;
+}
+
+NvBool Max8907bRtcI2cWriteTime(
+   NvOdmPmuDeviceHandle hDevice,
+   NvU8 Addr,
+   NvU32 Data)
+{
+    NvU32 i;
+    NvU8 WriteBuffer[5];
+    NvOdmI2cStatus  status = NvOdmI2cStatus_Success;
+    Max8907bPrivData *hPmu = (Max8907bPrivData*)hDevice->pPrivate;
+    NvOdmI2cTransactionInfo TransactionInfo;
+
+    NVODMPMU_PRINTF(("\n RTC I2C write: Addr=0x%x, Data=0x%x ", Addr, Data));
+    for (i = 0; i < MAX8907B_I2C_RETRY_CNT; i++)
+    {
+        WriteBuffer[0] = (NvU8)(Addr & 0xFF);
+        WriteBuffer[1] = (NvU8)((Data >> 24) & 0xFF);
+        WriteBuffer[2] = (NvU8)((Data >> 16) & 0xFF);
+        WriteBuffer[3] = (NvU8)((Data >>  8) & 0xFF);
+        WriteBuffer[4] = (NvU8)(Data & 0xFF);
+
+        TransactionInfo.Address = MAX8907B_RTC_SLAVE_ADDR;
+        TransactionInfo.Buf = &WriteBuffer[0];
+        TransactionInfo.Flags = NVODM_I2C_IS_WRITE;
+        TransactionInfo.NumBytes = 5;
+
+        status = NvOdmI2cTransaction(hPmu->hOdmI2C, &TransactionInfo, 1,
+            MAX8907B_I2C_SPEED_KHZ, NV_WAIT_INFINITE);
+
+        if (status == NvOdmI2cStatus_Success)
+            return NV_TRUE;
+    }
+
+    // Transaction Error
+    switch (status)
+    {
+        case NvOdmI2cStatus_Timeout:
+            NVODMPMU_PRINTF(("Max8907bRtcI2cWrite32 Failed: Timeout\n"));
+            break;
+        case NvOdmI2cStatus_SlaveNotFound:
+        default:
+            NVODMPMU_PRINTF(("Max8907bRtcI2cWrite32 Failed: SlaveNotFound\n"));
+            break;
+    }
+    return NV_FALSE;
+}
+
+NvBool Max8907bRtcI2cReadTime(
+   NvOdmPmuDeviceHandle hDevice,
+   NvU8 Addr,
+   NvU32 *Data)
+{
+    NvU32 i;
+    NvU8 ReadBuffer[4];
+    NvOdmI2cStatus  status = NvOdmI2cStatus_Success;
+    Max8907bPrivData *hPmu = (Max8907bPrivData*)hDevice->pPrivate;
+    NvOdmI2cTransactionInfo TransactionInfo[MAX_TRANSACTION_COUNT];
+
+    NVODMPMU_PRINTF(("\n RTC I2C read: Addr=0x%x ", Addr));
+    for (i = 0; i < MAX8907B_I2C_RETRY_CNT; i++)
+    {
+        NvU32 TransactionCount = 0;
+        ReadBuffer[0] = Addr & 0xFF;
+
+        TransactionInfo[TransactionCount].Address = MAX8907B_RTC_SLAVE_ADDR;
+        TransactionInfo[TransactionCount].Buf = &ReadBuffer[0];
+        TransactionInfo[TransactionCount].Flags =
+            NVODM_I2C_IS_WRITE | NVODM_I2C_USE_REPEATED_START;
+        TransactionInfo[TransactionCount++].NumBytes = 1;
+
+        // Seconds / day
+        if (TransactionCount >= MAX_TRANSACTION_COUNT)
+            return NV_FALSE;
+        TransactionInfo[TransactionCount].Address =
+            (MAX8907B_RTC_SLAVE_ADDR | 0x1);
+        TransactionInfo[TransactionCount].Buf = &ReadBuffer[0];
+        TransactionInfo[TransactionCount].Flags = 0;
+        TransactionInfo[TransactionCount++].NumBytes = 1;
+
+        // Minutes / month
+        if (TransactionCount >= MAX_TRANSACTION_COUNT)
+            return NV_FALSE;
+        TransactionInfo[TransactionCount].Address =
+            (MAX8907B_RTC_SLAVE_ADDR | 0x1);
+        TransactionInfo[TransactionCount].Buf = &ReadBuffer[1];
+        TransactionInfo[TransactionCount].Flags = 0;
+        TransactionInfo[TransactionCount++].NumBytes = 1;
+
+        // Hours / YY1
+        if (TransactionCount >= MAX_TRANSACTION_COUNT)
+            return NV_FALSE;
+        TransactionInfo[TransactionCount].Address =
+            (MAX8907B_RTC_SLAVE_ADDR | 0x1);
+        TransactionInfo[TransactionCount].Buf = &ReadBuffer[2];
+        TransactionInfo[TransactionCount].Flags = 0;
+        TransactionInfo[TransactionCount++].NumBytes = 1;
+
+        // Weekday / YY2
+        if (TransactionCount >= MAX_TRANSACTION_COUNT)
+            return NV_FALSE;
+        TransactionInfo[TransactionCount].Address =
+            (MAX8907B_RTC_SLAVE_ADDR | 0x1);
+        TransactionInfo[TransactionCount].Buf = &ReadBuffer[3];
+        TransactionInfo[TransactionCount].Flags = 0;
+        TransactionInfo[TransactionCount++].NumBytes = 1;
+
+        status = NvOdmI2cTransaction(hPmu->hOdmI2C, &TransactionInfo[0],
+            TransactionCount, MAX8907B_I2C_SPEED_KHZ, NV_WAIT_INFINITE);
+        if (status == NvOdmI2cStatus_Success)
+        {
+            *Data = (ReadBuffer[0] << 24) | (ReadBuffer[1] << 16) |
+                    (ReadBuffer[2] << 8) | ReadBuffer[3];
+
+            return NV_TRUE;
+        }
+    }
+
+    // Transaction Error
+    switch (status)
+    {
+        case NvOdmI2cStatus_Timeout:
+            NVODMPMU_PRINTF(("Max8907bRtcI2cRead32 Failed: Timeout\n"));
+            break;
+        case NvOdmI2cStatus_SlaveNotFound:
+        default:
+            NVODMPMU_PRINTF(("Max8907bRtcI2cRead32 Failed: SlaveNotFound\n"));
+            break;
+    }
+    return NV_FALSE;
+}
+
diff --git a/arch/arm/mach-tegra/odm_kit/adaptations/pmu/max8907b/max8907b_i2c.h b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/max8907b/max8907b_i2c.h
new file mode 100644
index 000000000000..c4b5c634c4fa
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/max8907b/max8907b_i2c.h
@@ -0,0 +1,82 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_NVODM_PMU_MAX8907B_I2C_H
+#define INCLUDED_NVODM_PMU_MAX8907B_I2C_H
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+// Constant definition
+// #define PMU_MAX8907B_DEVADDR     TBD
+#define PMU_MAX8907B_I2C_SPEED_KHZ   400
+
+// Function declaration
+NvBool Max8907bI2cWrite8(
+   NvOdmPmuDeviceHandle hDevice,
+   NvU8 Addr,
+   NvU8 Data);
+
+NvBool Max8907bI2cRead8(
+   NvOdmPmuDeviceHandle hDevice,
+   NvU8 Addr,
+   NvU8 *Data);
+
+NvBool Max8907bI2cWrite32(
+   NvOdmPmuDeviceHandle hDevice,
+   NvU8 Addr,
+   NvU32 Data);
+
+NvBool Max8907bI2cRead32(
+   NvOdmPmuDeviceHandle hDevice,
+   NvU8 Addr,
+   NvU32 *Data);
+
+NvBool Max8907bRtcI2cWriteTime(
+   NvOdmPmuDeviceHandle hDevice,
+   NvU8 Addr,
+   NvU32 Data);
+
+NvBool Max8907bRtcI2cReadTime(
+   NvOdmPmuDeviceHandle hDevice,
+   NvU8 Addr,
+   NvU32 *Data);
+
+#if defined(__cplusplus)
+}
+#endif
+
+/** @} */
+
+#endif // INCLUDED_NVODM_PMU_MAX8907B_I2C_H
diff --git a/arch/arm/mach-tegra/odm_kit/adaptations/pmu/max8907b/max8907b_interrupt.c b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/max8907b/max8907b_interrupt.c
new file mode 100644
index 000000000000..38110f83c5a0
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/max8907b/max8907b_interrupt.c
@@ -0,0 +1,172 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include "max8907b.h"
+#include "max8907b_interrupt.h"
+#include "max8907b_i2c.h"
+#include "max8907b_reg.h"
+#include "max8907b_batterycharger.h"
+#include "nvodm_services.h"
+
+NvBool 
+Max8907bSetupInterrupt(
+    NvOdmPmuDeviceHandle hDevice,
+    Max8907bStatus *pmuStatus)
+{
+    NvBool status = NV_FALSE;
+    NvU8   data   = 0;    
+
+    NV_ASSERT(hDevice);
+    NV_ASSERT(pmuStatus);
+    
+    /* Init Pmu Status */
+    pmuStatus->lowBatt       = NV_FALSE;
+    pmuStatus->highTemp      = NV_FALSE;
+
+    if (!Max8907bBatteryChargerMainBatt(hDevice, &status))
+        return NV_FALSE;
+    pmuStatus->mChgPresent = status;
+
+    /* Set up Interrupt Mask */
+
+    // CHG_IRQ1
+    data = 0;
+    if (!Max8907bI2cWrite8(hDevice, MAX8907B_CHG_IRQ1, data))
+        return NV_FALSE;
+
+    // CHG_IRQ2
+    data = MAX8907B_CHG_IRQ2_CHG_DONE_MASK      |
+           MAX8907B_CHG_IRQ2_MBATTLOW_F_SHIFT   |
+           MAX8907B_CHG_IRQ2_THM_OK_F_MASK      |
+           MAX8907B_CHG_IRQ2_THM_OK_R_MASK      ;
+    if (!Max8907bI2cWrite8(hDevice, MAX8907B_CHG_IRQ2, data))
+        return NV_FALSE;
+
+    // ON_OFF_IRQ1
+    data = 0;
+    if (!Max8907bI2cWrite8(hDevice, MAX8907B_ON_OFF_IRQ1, data))
+        return NV_FALSE;
+
+    // ON_OFF_IRQ2
+    data = 0;
+    if (!Max8907bI2cWrite8(hDevice, MAX8907B_ON_OFF_IRQ2, data))
+        return NV_FALSE;
+
+    // RTC_IRQ
+    data = 0;
+    if (!Max8907bI2cWrite8(hDevice, MAX8907B_RTC_IRQ, data))
+        return NV_FALSE;
+
+    return NV_TRUE;
+}
+
+void 
+Max8907bInterruptHandler_int(
+    NvOdmPmuDeviceHandle hDevice,
+    Max8907bStatus *pmuStatus)
+{
+    NvU8 data = 0;
+
+    NV_ASSERT(hDevice);
+    NV_ASSERT(pmuStatus);
+
+    /* Check which interrupt... */
+
+    // CHG_IRQ1
+    if (!Max8907bI2cRead8(hDevice, MAX8907B_CHG_IRQ1, &data))
+    {
+        return;
+    }
+
+    if (data)
+    {
+        // VBUS connect interrupt
+        if (data &
+           (MAX8907B_CHG_IRQ1_VCHG_R_MASK << MAX8907B_CHG_IRQ1_VCHG_R_SHIFT))
+        {
+            NvOdmEnableOtgCircuitry(NV_TRUE);
+        }
+        // VBUS dis-connect interrupt
+        else if (data &
+                (MAX8907B_CHG_IRQ1_VCHG_F_MASK << MAX8907B_CHG_IRQ1_VCHG_F_SHIFT))
+        {
+            NvOdmEnableOtgCircuitry(NV_FALSE);
+        }
+    }
+
+    // CHG_IRQ2
+    if (!Max8907bI2cRead8(hDevice, MAX8907B_CHG_IRQ2, &data))
+    {
+        return;
+    }
+    if (data)
+    {
+        if (data & MAX8907B_CHG_IRQ2_CHG_DONE_MASK)
+        {
+            pmuStatus->mChgPresent = NV_TRUE;
+            pmuStatus->batFull = NV_TRUE;
+        }
+        if (data & MAX8907B_CHG_IRQ2_MBATTLOW_F_SHIFT)
+        {
+            pmuStatus->batFull = NV_FALSE;
+        }
+        if (data & MAX8907B_CHG_IRQ2_THM_OK_F_MASK)
+        {
+            pmuStatus->highTemp = NV_TRUE;
+        }
+        if (data & MAX8907B_CHG_IRQ2_THM_OK_R_MASK)
+        {
+            pmuStatus->highTemp = NV_FALSE;
+        }
+    }
+
+    // ON_OFF_IRQ1
+    if (!Max8907bI2cRead8(hDevice, MAX8907B_ON_OFF_IRQ1, &data))
+    {
+        return;
+    }
+
+    // ON_OFF_IRQ2
+    if (!Max8907bI2cRead8(hDevice, MAX8907B_ON_OFF_IRQ2, &data))
+    {
+        return;
+    }
+
+    // RTC_IRQ
+    if (!Max8907bI2cRead8(hDevice, MAX8907B_RTC_IRQ, &data))
+    {
+        return;
+    }
+
+    return;
+}
+
diff --git a/arch/arm/mach-tegra/odm_kit/adaptations/pmu/max8907b/max8907b_interrupt.h b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/max8907b/max8907b_interrupt.h
new file mode 100644
index 000000000000..a00cabc17039
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/max8907b/max8907b_interrupt.h
@@ -0,0 +1,58 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_MAX8907B_INTERRUPT_HEADER
+#define INCLUDED_MAX8907B_INTERRUPT_HEADER
+
+#include "max8907b.h"
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+NvBool 
+Max8907bSetupInterrupt(
+    NvOdmPmuDeviceHandle hDevice,
+    Max8907bStatus *pmuStatus);
+
+void 
+Max8907bInterruptHandler_int(
+    NvOdmPmuDeviceHandle hDevice,
+    Max8907bStatus *pmuStatus);
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif // INCLUDED_MAX8907B_INTERRUPT_HEADER
+
diff --git a/arch/arm/mach-tegra/odm_kit/adaptations/pmu/max8907b/max8907b_reg.h b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/max8907b/max8907b_reg.h
new file mode 100644
index 000000000000..513e2f6a1812
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/max8907b/max8907b_reg.h
@@ -0,0 +1,398 @@
+/*
+ * Copyright (c) 2009-2010 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_MAX8907B_REG_HEADER
+#define INCLUDED_MAX8907B_REG_HEADER
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+// -- MAX8907B Addresses (See Table 71 of data sheet) --
+
+/* MAX8907B Slave Addresses */
+
+#define MAX8907B_PMU_SLAVE_ADDR         0x78
+#define MAX8907B_RTC_SLAVE_ADDR         0xD0
+#define MAX8907B_ADC_SLAVE_ADDR         0x8E
+
+/* MAX8907B Register Addresses  */
+
+// Main-Battery Charger
+#define MAX8907B_CHG_CNTL1          0x7C
+#define MAX8907B_CHG_CNTL2          0x7D
+#define MAX8907B_CHG_IRQ1           0x7E
+#define MAX8907B_CHG_IRQ2           0x7F
+#define MAX8907B_CHG_IRQ1_MASK      0x80
+#define MAX8907B_CHG_IRQ2_MASK      0x81
+#define MAX8907B_CHG_STAT           0x82
+
+// Backup-Battery Charger
+#define MAX8907B_BBATT_CNFG         0x78
+#define MAX8907B_SDBYSEQCNT         0x13
+
+// V1 Step Down Regulator
+#define MAX8907B_SDCTL1             0x04
+#define MAX8907B_SDSEQCNT1          0x05
+#define MAX8907B_SDV1               0x06
+
+// V2 Step Down Regulator
+#define MAX8907B_SDCTL2             0x07
+#define MAX8907B_SDSEQCNT2          0x08
+#define MAX8907B_SDV2               0x09
+
+// V3 Step Down Regulator
+#define MAX8907B_SDCTL3             0x0A
+#define MAX8907B_SDSEQCNT3          0x0B
+#define MAX8907B_SDV3               0x0C
+
+// LDO1 Regulator
+#define MAX8907B_LDOCTL1            0x18
+#define MAX8907B_LDOSEQCNT1         0x19
+#define MAX8907B_LDO1VOUT           0x1A
+
+// LDO2 Regulator
+#define MAX8907B_LDOCTL2            0x1C
+#define MAX8907B_LDOSEQCNT2         0x1D
+#define MAX8907B_LDO2VOUT           0x1E
+
+// LDO3 Regulator
+#define MAX8907B_LDOCTL3            0x20
+#define MAX8907B_LDOSEQCNT3         0x21
+#define MAX8907B_LDO3VOUT           0x22
+
+// LDO4 Regulator
+#define MAX8907B_LDOCTL4            0x24
+#define MAX8907B_LDOSEQCNT4         0x25
+#define MAX8907B_LDO4VOUT           0x26
+
+// LDO5 Regulator
+#define MAX8907B_LDOCTL5            0x28
+#define MAX8907B_LDOSEQCNT5         0x29
+#define MAX8907B_LDO5VOUT           0x2A
+
+// LDO6 Regulator
+#define MAX8907B_LDOCTL6            0x2C
+#define MAX8907B_LDOSEQCNT6         0x2D
+#define MAX8907B_LDO6VOUT           0x2E
+
+// LDO7 Regulator
+#define MAX8907B_LDOCTL7            0x30
+#define MAX8907B_LDOSEQCNT7         0x31
+#define MAX8907B_LDO7VOUT           0x32
+
+// LDO8 Regulator
+#define MAX8907B_LDOCTL8            0x34
+#define MAX8907B_LDOSEQCNT8         0X35
+#define MAX8907B_LDO8VOUT           0x36
+
+// LDO9 Regulator
+#define MAX8907B_LDOCTL9            0x38
+#define MAX8907B_LDOSEQCNT9         0x39
+#define MAX8907B_LDO9VOUT           0x3A
+
+// LDO10 Regulator
+#define MAX8907B_LDOCTL10           0x3C
+#define MAX8907B_LDOSEQCNT10        0x3D
+#define MAX8907B_LDO10VOUT          0x3E
+
+// LDO11 Regulator
+#define MAX8907B_LDOCTL11           0x40
+#define MAX8907B_LDOSEQCNT11        0x41
+#define MAX8907B_LDO11VOUT          0x42
+
+// LDO12 Regulator
+#define MAX8907B_LDOCTL12           0x44
+#define MAX8907B_LDOSEQCNT12        0x45
+#define MAX8907B_LDO12VOUT          0x46
+
+// LDO13 Regulator
+#define MAX8907B_LDOCTL13           0x48
+#define MAX8907B_LDOSEQCNT13        0x49
+#define MAX8907B_LDO13VOUT          0x4A
+
+// LDO14 Regulator
+#define MAX8907B_LDOCTL14           0x4C
+#define MAX8907B_LDOSEQCNT14        0x4D
+#define MAX8907B_LDO14VOUT          0x4E
+
+// LDO15 Regulator
+#define MAX8907B_LDOCTL15           0x50
+#define MAX8907B_LDOSEQCNT15        0x51
+#define MAX8907B_LDO15VOUT          0x52
+
+// LDO16 Regulator
+#define MAX8907B_LDOCTL16           0x10
+#define MAX8907B_LDOSEQCNT16        0x11
+#define MAX8907B_LDO16VOUT          0x12
+
+// LDO17 Regulator
+#define MAX8907B_LDOCTL17           0x14
+#define MAX8907B_LDOSEQCNT17        0x15
+#define MAX8907B_LDO17VOUT          0x16
+
+// LDO18 Regulator
+#define MAX8907B_LDOCTL18           0x72
+#define MAX8907B_LDOSEQCNT18        0x73
+#define MAX8907B_LDO18VOUT          0x74
+
+// LDO19 Regulator
+#define MAX8907B_LDOCTL19           0x5C
+#define MAX8907B_LDOSEQCNT19        0x5D
+#define MAX8907B_LDO19VOUT          0x5E
+
+// LDO20 Regulator
+#define MAX8907B_LDOCTL20           0x9C
+#define MAX8907B_LDOSEQCNT20        0x9D
+#define MAX8907B_LDO20VOUT          0x9E
+
+// OUT5V Regulator
+#define MAX8907B_OUT5VEN            0x54
+#define MAX8907B_OUT5VSEQ           0x55
+
+// OUT3.3V Regulator
+#define MAX8907B_OUT_3_3VEN         0x58
+#define MAX8907B_OUT_3_3VSEQ        0x59
+
+// Main Bias Register
+#define MAX8907B_LBCNFG             0x60
+
+// ON/OFF Controller
+#define MAX8907B_SYSENSEL           0x00
+#define MAX8907B_ON_OFF_IRQ1        0x01
+#define MAX8907B_ON_OFF_IRQ1_MASK   0x02
+#define MAX8907B_ON_OFF_STAT        0x03
+#define MAX8907B_ON_OFF_IRQ2        0x0D
+#define MAX8907B_ON_OFF_IRQ2_MASK   0x0E
+#define MAX8907B_RESET_CNFG         0x0F
+
+// Flexible Power Sequencer
+#define MAX8907B_SEQ1CNFG           0x64
+#define MAX8907B_SEQ2CNFG           0x65
+#define MAX8907B_SEQ3CNFG           0x66
+#define MAX8907B_SEQ4CNFG           0x67
+#define MAX8907B_SEQ5CNFG           0x68
+#define MAX8907B_SEQ6CNFG           0x69
+#define MAX8907B_SEQ7CNFG           0x6A
+
+// RTC Registers
+#define MAX8907B_RTC_SEC            0x00
+#define MAX8907B_RTC_MIN            0x01
+#define MAX8907B_RTC_HOURS          0x02
+#define MAX8907B_RTC_WEEKDAY        0x03
+#define MAX8907B_RTC_DATE           0x04
+#define MAX8907B_RTC_MONTH          0x05
+#define MAX8907B_RTC_YEAR1          0x06
+#define MAX8907B_RTC_YEAR2          0x07
+#define MAX8907B_ALARM0_SEC         0x08
+#define MAX8907B_ALARM0_MIN         0x09
+#define MAX8907B_ALARM0_HOURS       0x0A
+#define MAX8907B_ALARM0_WEEKDAY     0x0B
+#define MAX8907B_ALARM0_DATE        0x0C
+#define MAX8907B_ALARM0_MONTH       0x0D
+#define MAX8907B_ALARM0_YEAR1       0x0E
+#define MAX8907B_ALARM0_YEAR2       0x0F
+#define MAX8907B_ALARM1_SEC         0x10
+#define MAX8907B_ALARM1_MIN         0x11
+#define MAX8907B_ALARM1_HOURS       0x12
+#define MAX8907B_ALARM1_WEEKDAY     0x13
+#define MAX8907B_ALARM1_DATE        0x14
+#define MAX8907B_ALARM1_MONTH       0x15
+#define MAX8907B_ALARM1_YEAR1       0x16
+#define MAX8907B_ALARM1_YEAR2       0x17
+#define MAX8907B_ALARM0_CNTL        0x18
+#define MAX8907B_ALARM1_CNTL        0x19
+#define MAX8907B_RTC_STATUS         0x1A
+#define MAX8907B_RTC_CNTL           0x1B
+#define MAX8907B_RTC_IRQ            0x1C
+#define MAX8907B_RTC_IRQ_MASK       0x1D
+#define MAX8907B_MPL_CNTL           0x1E
+
+// ADC and Touch Screen Controller
+#define MAX8907B_TSC_STA_INT        0x00
+#define MAX8907B_TSC_INT_MASK       0x01
+#define MAX8907B_TSC_CNFG1          0x02
+#define MAX8907B_TSC_CNFG2          0x03
+#define MAX8907B_TSC_CNFG3          0x04
+#define MAX8907B_ADC_RES_CNFG1      0x06
+#define MAX8907B_ADC_AVG_CNFG1      0x07
+#define MAX8907B_ADC_ACQ_CNFG1      0x08
+#define MAX8907B_ADC_ACQ_CNFG2      0x09
+#define MAX8907B_ADC_SCHED          0x10
+#define MAX8907B_X_MSB              0x50
+#define MAX8907B_X_LSB              0x51
+#define MAX8907B_Y_MSB              0x52
+#define MAX8907B_Y_LSB              0x53
+#define MAX8907B_Z1_MSB             0x54
+#define MAX8907B_Z1_LSB             0x55
+#define MAX8907B_Z2_MSB             0x56
+#define MAX8907B_Z2_LSB             0x57
+#define MAX8907B_AUX1_MSB           0x60
+#define MAX8907B_AUX1_LSB           0x61
+#define MAX8907B_AUX2_MSB           0x62
+#define MAX8907B_AUX2_LSB           0x63
+#define MAX8907B_VCHG_MSB           0x64
+#define MAX8907B_VCHG_LSB           0x65
+#define MAX8907B_VBBATT_MSB         0x66
+#define MAX8907B_VBBATT_LSB         0x67
+#define MAX8907B_VMBATT_MSB         0x68
+#define MAX8907B_VMBATT_LSB         0x69
+#define MAX8907B_ISNS_MSB           0x6A
+#define MAX8907B_ISNS_LSB           0x6B
+#define MAX8907B_THM_MSB            0x6C
+#define MAX8907B_THM_LSB            0x6D
+#define MAX8907B_TDIE_MSB           0x6E
+#define MAX8907B_TDIE_LSB           0x6F
+
+// WLED Driver
+#define MAX8907B_WLED_MODE_CNTL     0x84
+#define MAX8907B_ILED_CNTL          0x85
+
+// Chip Identification
+#define MAX8907B_II1RR              0x8E
+#define MAX8907B_II2RR              0x8F
+
+#define MAX8907B_REG_INVALID        0xFF
+
+/* field defines for register bit ops */
+#define MAX8907B_OUT_VOLTAGE_MASK           0x3F
+#define MAX8907B_OUT_VOLTAGE_ENABLE_BIT     0x01
+#define MAX8907B_OUT_VOLTAGE_DISABLE_MASK   0x3E
+
+#define MAX8907B_CTL_SEQ_SHIFT              0x02
+#define MAX8907B_CTL_SEQ_MASK               0x07
+
+// CHG_CNTL_1
+#define MAX8907B_CHG_CNTL1_NOT_CHGEN_SHIFT      0x7
+#define MAX8907B_CHG_CNTL1_NOT_CHGEN_MASK       0x1
+#define MAX8907B_CHG_CNTL1_CHG_TOPOFF_SHIFT     0x5
+#define MAX8907B_CHG_CNTL1_CHG_TOPOFF_MASK      0x3
+#define MAX8907B_CHG_CNTL1_CHG_RST_HYS_SHIFT    0x3
+#define MAX8907B_CHG_CNTL1_CHG_RST_HYS_MASK     0x3
+#define MAX8907B_CHG_CNTL1_FCHG_SHIFT           0x0
+#define MAX8907B_CHG_CNTL1_FCHG_MASK            0x7
+
+#define MAX8907B_CHG_CNTL1_FCHG_85MA            0
+#define MAX8907B_CHG_CNTL1_FCHG_300MA           1
+#define MAX8907B_CHG_CNTL1_FCHG_460MA           2
+#define MAX8907B_CHG_CNTL1_FCHG_600MA           3
+#define MAX8907B_CHG_CNTL1_FCHG_700MA           4
+#define MAX8907B_CHG_CNTL1_FCHG_800MA           5
+#define MAX8907B_CHG_CNTL1_FCHG_900MA           6
+#define MAX8907B_CHG_CNTL1_FCHG_1000MA          7
+
+// CHG_CNTL_1
+#define MAX8907B_CHG_CNTL2_FCHG_TMR_SHIFT       0x4
+#define MAX8907B_CHG_CNTL2_FCHG_TMR_MASK        0x3
+#define MAX8907B_CHG_CNTL2_MBAT_REG_TH_SHIFT    0x3
+#define MAX8907B_CHG_CNTL2_MBAT_REG_TH_MASK     0x1
+#define MAX8907B_CHG_CNTL2_TDIE_THERM_REG_SHIFT 0x0
+#define MAX8907B_CHG_CNTL2_TDIE_THERM_REG_MASK  0x3
+
+// Interrupts
+#define MAX8907B_CHG_STAT_VCHG_OK_SHIFT     0x7
+#define MAX8907B_CHG_STAT_VCHG_OK_MASK      0x1
+#define MAX8907B_CHG_STAT_CHG_TMR_FLT_SHIFT 0x5
+#define MAX8907B_CHG_STAT_CHG_TMR_FLT_MASK  0x1
+#define MAX8907B_CHG_STAT_CHG_EN_STAT_SHIFT 0x4
+#define MAX8907B_CHG_STAT_CHG_EN_STAT_MASK  0x1
+#define MAX8907B_CHG_STAT_CHG_MODE_SHIFT    0x2
+#define MAX8907B_CHG_STAT_CHG_MODE_MASK     0x3
+#define MAX8907B_CHG_STAT_MBDET_SHIFT       0x1
+#define MAX8907B_CHG_STAT_MBDET_MASK        0x1
+#define MAX8907B_CHG_STAT_MBATTLOW_SHIFT    0x0
+#define MAX8907B_CHG_STAT_MBATTLOW_MASK     0x1
+
+#define MAX8907B_CHG_IRQ1_VCHG_R_SHIFT      0x2
+#define MAX8907B_CHG_IRQ1_VCHG_R_MASK       0x1
+#define MAX8907B_CHG_IRQ1_VCHG_F_SHIFT      0x1
+#define MAX8907B_CHG_IRQ1_VCHG_F_MASK       0x1
+#define MAX8907B_CHG_IRQ1_VCHG_OVP_SHIFT    0x0
+#define MAX8907B_CHG_IRQ1_VCHG_OVP_MASK     0x1
+
+#define MAX8907B_CHG_IRQ2_CHG_TMR_FAULT_SHIFT   0x7
+#define MAX8907B_CHG_IRQ2_CHG_TMR_FAULT_MASK    0x1
+#define MAX8907B_CHG_IRQ2_CHG_TOPOFF_SHIFT      0x6
+#define MAX8907B_CHG_IRQ2_CHG_TOPOFF_MASK       0x1
+#define MAX8907B_CHG_IRQ2_CHG_DONE_SHIFT        0x5
+#define MAX8907B_CHG_IRQ2_CHG_DONE_MASK         0x1
+#define MAX8907B_CHG_IRQ2_CHG_RST_SHIFT         0x4
+#define MAX8907B_CHG_IRQ2_CHG_RST_MASK          0x1
+#define MAX8907B_CHG_IRQ2_MBATTLOW_R_SHIFT      0x3
+#define MAX8907B_CHG_IRQ2_MBATTLOW_R_MASK       0x1
+#define MAX8907B_CHG_IRQ2_MBATTLOW_F_SHIFT      0x2
+#define MAX8907B_CHG_IRQ2_MBATTLOW_F_MASK       0x1
+#define MAX8907B_CHG_IRQ2_THM_OK_F_SHIFT        0x1
+#define MAX8907B_CHG_IRQ2_THM_OK_F_MASK         0x1
+#define MAX8907B_CHG_IRQ2_THM_OK_R_SHIFT        0x0
+#define MAX8907B_CHG_IRQ2_THM_OK_R_MASK         0x1
+
+#define MAX8907B_ON_OFF_IRQ1_SW_R_SHIFT         0x7
+#define MAX8907B_ON_OFF_IRQ1_SW_R_MASK          0x1
+#define MAX8907B_ON_OFF_IRQ1_SW_F_SHIFT         0x6
+#define MAX8907B_ON_OFF_IRQ1_SW_F_MASK          0x1
+#define MAX8907B_ON_OFF_IRQ1_SW_1SEC_SHIFT      0x5
+#define MAX8907B_ON_OFF_IRQ1_SW_1SEC_MASK       0x1
+#define MAX8907B_ON_OFF_IRQ1_EXTON_R_SHIFT      0x4
+#define MAX8907B_ON_OFF_IRQ1_EXTON_R_MASK       0x1
+#define MAX8907B_ON_OFF_IRQ1_EXTON_F_SHIFT      0x3
+#define MAX8907B_ON_OFF_IRQ1_EXTON_F_MASK       0x1
+#define MAX8907B_ON_OFF_IRQ1_SW_3SEC_SHIFT      0x2
+#define MAX8907B_ON_OFF_IRQ1_SW_3SEC_MASK       0x1
+#define MAX8907B_ON_OFF_IRQ1_MPL_EVENT_SHIFT    0x1
+#define MAX8907B_ON_OFF_IRQ1_MPL_EVENT_MASK     0x1
+#define MAX8907B_ON_OFF_IRQ1_RSTIN_F_SHIFT      0x0
+#define MAX8907B_ON_OFF_IRQ1_RSTIN_F_MASK       0x1
+
+#define MAX8907B_ON_OFF_IRQ2_SYSCKEN_R_SHIFT    0x1
+#define MAX8907B_ON_OFF_IRQ2_SYSCKEN_R_MASK     0x1
+#define MAX8907B_ON_OFF_IRQ2_SYSCKEN_F_SHIFT    0x0
+#define MAX8907B_ON_OFF_IRQ2_SYSCKEN_F_MASK     0x1
+
+#define MAX8907B_RTC_IRQ_ALARM0_R_SHIFT         0x3
+#define MAX8907B_RTC_IRQ_ALARM0_R_MASK          0x1
+#define MAX8907B_RTC_IRQ_ALARM1_R_SHIFT         0x2
+#define MAX8907B_RTC_IRQ_ALARM1_R_MASK          0x1
+
+// ON/OFF controller
+#define MAX8907B_SYSENSEL_HRDSTEN_SHIFT         0x7
+#define MAX8907B_SYSENSEL_HRDSTEN_MASK          0x1
+
+#define MAX8907B_RESET_CNFG_PWREN_EN_SHIFT      0x7
+#define MAX8907B_RESET_CNFG_PWREN_EN_MASK       0x1
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif //INCLUDED_MAX8907B_REG_HEADER
diff --git a/arch/arm/mach-tegra/odm_kit/adaptations/pmu/max8907b/max8907b_rtc.c b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/max8907b/max8907b_rtc.c
new file mode 100644
index 000000000000..1c4d61a01a98
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/max8907b/max8907b_rtc.c
@@ -0,0 +1,260 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include <linux/time.h>
+#include <linux/rtc.h>
+#include "max8907b.h"
+#include "max8907b_rtc.h"
+#include "max8907b_i2c.h"
+#include "max8907b_reg.h"
+
+/**
+* The Maxim 8907B does not have an RTC that simply counts
+* seconds from some time t0 (as defined by the OS API).
+* Instead, this RTC contains several BCD (Binary Coded Decimal)
+* registers, including: seconds, minutes, hours, days, day of
+* week, date, etc...  These registers account for leap year and
+* the various days of the month as well.
+*
+* Since the OS interpretation of seconds to a particular
+* date/time from some OS-defined t0 is unknown at this level of
+* the implementation, it is not possible to translate the given
+* seconds into these registers (at least, not without a
+* dependency on some OS-specific information).
+*
+*/
+
+#define MAX8907B_SECONDS_PER_DAY    (60*60*24)
+#define MAX8907B_SECONDS_PER_HOUR   (60*60)
+#define MAX8907B_SECONDS_PER_MINUTE (60)
+
+#define LINUX_RTC_BASE_YEAR 1900
+
+/* Macro for conversion of BCD number to decimal format */
+#define BCD_TO_DECIMAL(BCD) \
+            ((((BCD) & 0xF0) >> 4) * 10 + ((BCD) & 0xF))
+/* Macro for conversion of decimal number to BCD format */
+#define DECIMAL_TO_BCD(DEC) \
+            ((((DEC) / 10) << 4) | ((DEC) % 10))
+
+static NvBool bRtcNotInitialized = NV_TRUE;
+
+NvBool
+Max8907bRtcCountRead(
+    NvOdmPmuDeviceHandle hDevice,
+    NvU32* Count)
+{
+    NvU32 data = 0;
+    NvU32 BcdHours, BcdMinutes, BcdSeconds;
+    NvU32 Hours, Minutes, Seconds;
+    NvU32 BcdDD, BcdMM, BcdYY1, BcdYY2;
+    NvU32 DD, MM, YY1, YY2, YYYY;
+#if NV_DEBUG
+    struct rtc_time tm;
+#endif
+
+    *Count = 0;
+    // Read seconds, minute, hour and weekday data from RTC registers
+    if (Max8907bRtcI2cReadTime(hDevice, MAX8907B_RTC_SEC, &data))
+    {
+        NVODMPMU_PRINTF(("\n Read time data-sec=0x%x ", data));
+        // Extract seconds, minute and hour data from RTC registers read
+        BcdHours   = (data >>  8) & 0xFF;
+        BcdMinutes = (data >> 16) & 0xFF;
+        BcdSeconds = (data >> 24) & 0xFF;
+
+        // Convert BCD time into decimal values
+        Hours   = BCD_TO_DECIMAL(BcdHours);
+        Minutes = BCD_TO_DECIMAL(BcdMinutes);
+        Seconds = BCD_TO_DECIMAL(BcdSeconds);
+
+        // Read day, month, yy1 and yy2 data from RTC registers
+        if (Max8907bRtcI2cReadTime(hDevice, MAX8907B_RTC_DATE, &data))
+        {
+            NVODMPMU_PRINTF(("\n Read time data-year=0x%x ", data));
+            // Extract day, month, yy1 and yy2 data from RTC registers read
+            BcdYY2   = (data & 0xFF);
+            BcdYY1   = (data >>  8) & 0xFF;
+            BcdMM = (data >> 16) & 0xFF;
+            BcdDD = (data >> 24) & 0xFF;
+            // convert bcd day/month/year data to decimal values
+            YY2 = BCD_TO_DECIMAL(BcdYY2);
+            YY1 = BCD_TO_DECIMAL(BcdYY1);
+            YYYY = (YY2 * 100 + YY1) & 0xFFFF;
+            MM = BCD_TO_DECIMAL(BcdMM);
+            DD = BCD_TO_DECIMAL(BcdDD);
+            // get seconds since reference time value given
+            // year, month, day, hour, minutes and seconds
+            // NOTE: Using linux specific API mktime for conversion
+            *Count = mktime(YYYY, (MM + 1), DD, Hours, Minutes, Seconds);
+            NVODMPMU_PRINTF(("\n Rtc read count=0x%x ", *Count));
+            NVODMPMU_PRINTF(("\n mktime: YYYY=%d MM=%d DD=%d Hr=%d Min=%d "
+                "Sec=%d, *Count=0x%x ", YYYY, (MM + 1), DD, Hours, Minutes,
+                Seconds, *Count));
+#if NV_DEBUG
+            // Call to verify that reverse conversion of seconds matches date
+            rtc_time_to_tm(*Count, &tm);
+            // Check if Local_rtc_time_to_tm can return values sent to mktime
+            NVODMPMU_PRINTF(("\n rtc_time_to_tm: YYYY=%d MM=%d DD=%d Hr=%d "
+                "Min=%d Sec=%d, *Count=0x%x ", (tm.tm_year +
+                LINUX_RTC_BASE_YEAR), tm.tm_mon, tm.tm_mday, tm.tm_hour,
+                tm.tm_min, tm.tm_sec, *Count));
+#endif
+        }
+        else
+        {
+            NVODMPMU_PRINTF(("\n Max8907bRtcCountRead() error. "));
+            return NV_FALSE;
+        }
+    }
+    else
+    {
+        NVODMPMU_PRINTF(("\n Max8907bRtcCountRead() error. "));
+        return NV_FALSE;
+    }
+    NVODMPMU_PRINTF(("\n *Count=0x%x ", *Count));
+    return NV_TRUE;
+}
+
+NvBool
+Max8907bRtcAlarmCountRead(
+    NvOdmPmuDeviceHandle hDevice,
+    NvU32* Count)
+{
+    return NV_FALSE;
+}
+
+NvBool
+Max8907bRtcCountWrite(
+    NvOdmPmuDeviceHandle hDevice,
+    NvU32 Count)
+{
+    NvU32 BcdHours, BcdMinutes, BcdSeconds;
+    NvU32 data = 0;
+    NvU8 BcdDD, BcdMM, BcdYY1, BcdYY2;
+    NvU16 YYYY;
+    struct rtc_time tm;
+#if NV_DEBUG
+    NvU32 data1;
+#endif
+
+    NVODMPMU_PRINTF(("\n Rtc write count=0x%x ", Count));
+    // convert seconds since reference time into date
+    // NOTE: using linux specific convert function rtc_time_to_tm
+    rtc_time_to_tm(Count, &tm);
+    NVODMPMU_PRINTF(("\n rtc_time_to_tm: YYYY=%d MM=%d DD=%d Hr=%d Min=%d "
+        "Sec=%d, *Count=0x%x ", (tm.tm_year + LINUX_RTC_BASE_YEAR),
+        (tm.tm_mon + 1), tm.tm_mday,
+        tm.tm_hour, tm.tm_min, tm.tm_sec, Count));
+
+    // Convert time to bcd format
+    BcdHours   = DECIMAL_TO_BCD(tm.tm_hour);
+    BcdMinutes = DECIMAL_TO_BCD(tm.tm_min);
+    BcdSeconds = DECIMAL_TO_BCD(tm.tm_sec);
+
+    data = (BcdSeconds << 24) | (BcdMinutes << 16) | (BcdHours << 8);
+    // write time - seconds, minutes and hours in a day to RTC registers
+    if (Max8907bRtcI2cWriteTime(hDevice, MAX8907B_RTC_SEC, data))
+    {
+        // set the day, month, year
+        // Assuming we get the days since 1 Jan 1970
+
+        // convert date to bcd format
+        BcdDD = DECIMAL_TO_BCD((NvU8)tm.tm_mday);
+        BcdMM = DECIMAL_TO_BCD((NvU8)tm.tm_mon);
+        YYYY = (NvU16)tm.tm_year + LINUX_RTC_BASE_YEAR;
+        BcdYY1 = DECIMAL_TO_BCD((NvU8)(YYYY % 100));
+        BcdYY2 = DECIMAL_TO_BCD((NvU8)(YYYY / 100));
+        data = (NvU32)((BcdDD << 24) | (BcdMM << 16) | (BcdYY1 << 8) | BcdYY2);
+        // write date - day, month, and year to RTC registers
+        if (!(Max8907bRtcI2cWriteTime(hDevice, MAX8907B_RTC_DATE, data)))
+        {
+            NVODMPMU_PRINTF(("\n Max8907bRtcCountWrite() error. "));
+            return NV_FALSE;
+        }
+#if NV_DEBUG
+        // verify that read back values from RTC matches written values
+        if (!(Max8907bRtcI2cReadTime(hDevice, MAX8907B_RTC_DATE, &data1)))
+        {
+            NVODMPMU_PRINTF(("\n Max8907bRtcCountRead() error. "));
+            return NV_FALSE;
+        }
+        if (data1 == data)
+        {
+            NVODMPMU_PRINTF(("\n Write read Success. "));
+            return NV_TRUE;
+        }
+        else
+        {
+            // return error when read data does not match written data
+            NVODMPMU_PRINTF(("\n Error: write data=0x%x, rd data=0x%x. ", data, data1));
+            return NV_FALSE;
+        }
+#endif
+    }
+    else
+    {
+        NVODMPMU_PRINTF(("\n Max8907bRtcCountWrite() error. "));
+        return NV_FALSE;
+    }
+
+    return NV_TRUE;
+}
+
+NvBool
+Max8907bRtcAlarmCountWrite(
+    NvOdmPmuDeviceHandle hDevice,
+    NvU32 Count)
+{
+    return NV_FALSE;
+}
+
+NvBool
+Max8907bRtcIsAlarmIntEnabled(NvOdmPmuDeviceHandle hDevice)
+{
+    return NV_FALSE;
+}
+
+NvBool
+Max8907bRtcAlarmIntEnable(
+    NvOdmPmuDeviceHandle hDevice,
+    NvBool Enable)
+{
+    return NV_FALSE;
+}
+
+NvBool
+Max8907bIsRtcInitialized(NvOdmPmuDeviceHandle hDevice)
+{
+    return (!bRtcNotInitialized);
+}
+
diff --git a/arch/arm/mach-tegra/odm_kit/adaptations/pmu/max8907b/max8907b_rtc.h b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/max8907b/max8907b_rtc.h
new file mode 100644
index 000000000000..0baa0de55339
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/max8907b/max8907b_rtc.h
@@ -0,0 +1,97 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_MAX8907B_RTC_HEADER
+#define INCLUDED_MAX8907B_RTC_HEADER
+
+#include "pmu_hal.h"
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+/* Read RTC count register */
+
+NvBool 
+Max8907bRtcCountRead(
+    NvOdmPmuDeviceHandle hDevice, 
+    NvU32* Count);
+
+/* Read RTC alarm count register */
+
+NvBool 
+Max8907bRtcAlarmCountRead(
+    NvOdmPmuDeviceHandle hDevice, 
+    NvU32* Count);
+
+/* Write RTC count register */
+
+NvBool 
+Max8907bRtcCountWrite(
+    NvOdmPmuDeviceHandle hDevice, 
+    NvU32 Count);
+
+/* Write RTC alarm count register */
+
+NvBool 
+Max8907bRtcAlarmCountWrite(
+    NvOdmPmuDeviceHandle hDevice, 
+    NvU32 Count);
+
+/* Reads RTC alarm interrupt mask status */
+
+NvBool 
+Max8907bRtcIsAlarmIntEnabled(NvOdmPmuDeviceHandle hDevice);
+
+/* Enables / Disables the RTC alarm interrupt */
+
+NvBool 
+Max8907bRtcAlarmIntEnable(
+    NvOdmPmuDeviceHandle hDevice, 
+    NvBool Enable);
+
+/* Checks if boot was from nopower / powered state */
+
+NvBool 
+Max8907bRtcWasStartUpFromNoPower(NvOdmPmuDeviceHandle hDevice);
+
+NvBool
+Max8907bIsRtcInitialized(NvOdmPmuDeviceHandle hDevice);
+
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif // INCLUDED_MAX8907B_RTC_HEADER
+
diff --git a/arch/arm/mach-tegra/odm_kit/adaptations/pmu/max8907b/max8907b_supply_info_table.h b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/max8907b/max8907b_supply_info_table.h
new file mode 100644
index 000000000000..1b362aac43f4
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/max8907b/max8907b_supply_info_table.h
@@ -0,0 +1,197 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+ 
+#ifndef INCLUDED_MAX8907B_SUPPLY_INFO_HEADER
+#define INCLUDED_MAX8907B_SUPPLY_INFO_HEADER
+
+#include "nvodm_pmu.h"
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+// Defines for the requested voltage for each supply (mV).
+// This is board specific and ODM should change this based on device.
+#define MAX8907B_REQUESTVOLTAGE_LX_V1       1000
+#define MAX8907B_REQUESTVOLTAGE_LX_V2       1200
+#define MAX8907B_REQUESTVOLTAGE_LX_V3       1800
+
+#define MAX8907B_REQUESTVOLTAGE_LDO1        3300
+#define MAX8907B_REQUESTVOLTAGE_LDO2        1100
+#define MAX8907B_REQUESTVOLTAGE_LDO3        1800
+#define MAX8907B_REQUESTVOLTAGE_LDO4        3300
+#define MAX8907B_REQUESTVOLTAGE_LDO5        2800
+#define MAX8907B_REQUESTVOLTAGE_LDO6        1800
+#define MAX8907B_REQUESTVOLTAGE_LDO7        2800
+#define MAX8907B_REQUESTVOLTAGE_LDO8        3000
+#define MAX8907B_REQUESTVOLTAGE_LDO9        2800
+#define MAX8907B_REQUESTVOLTAGE_LDO10       3000
+#define MAX8907B_REQUESTVOLTAGE_LDO11       3300
+#define MAX8907B_REQUESTVOLTAGE_LDO12       2800
+#define MAX8907B_REQUESTVOLTAGE_LDO13       2800
+#define MAX8907B_REQUESTVOLTAGE_LDO14       2800
+#define MAX8907B_REQUESTVOLTAGE_LDO15       3300
+#define MAX8907B_REQUESTVOLTAGE_LDO16       1300
+#define MAX8907B_REQUESTVOLTAGE_LDO17       1200
+#define MAX8907B_REQUESTVOLTAGE_LDO18       1800
+#define MAX8907B_REQUESTVOLTAGE_LDO19       2800
+#define MAX8907B_REQUESTVOLTAGE_LDO20       1200
+
+#define MAX8907B_REQUESTVOLTAGE_EXT_DCDC_1  5000    // Fixed
+#define MAX8907B_REQUESTVOLTAGE_EXT_DCDC_2     0    // Reserved
+#define MAX8907B_REQUESTVOLTAGE_EXT_DCDC_3  1050    // Fixed (unless FAN5355 is enabled)
+#define MAX8907B_REQUESTVOLTAGE_EXT_DCDC_4     0    // VBL1, controlled by display adaptation
+#define MAX8907B_REQUESTVOLTAGE_EXT_DCDC_5     0    // VBL2, controlled by display adaptation
+#define MAX8907B_REQUESTVOLTAGE_EXT_DCDC_6     0    // Reserved
+
+#define MAX8907B_REQUESTVOLTAGE_SDBY        1100
+
+// Defines default sequencer selection
+#define MAX8907B_SEQSEL_DEFAULT_LX_V1       0   /* SEQ1 (SYSEN) */
+#define MAX8907B_SEQSEL_DEFAULT_LX_V2       0   /* SEQ1 (SYSEN) */
+
+// Defines common for all supplies PWREN  sequencer selection
+#define MAX8907B_SEQSEL_PWREN_LXX           1   /* SEQ2 (PWREN) */
+
+// Defines common for all supplies I2C (s/w) sequencer selection
+#define MAX8907B_SEQSEL_I2CEN_LXX           7   /* I2CEN (s/w) */
+
+// Defines sequencer count default values 
+#define MAX8907B_SEQCNT_DEFAULT_LX_V1       0x1C
+#define MAX8907B_SEQCNT_DEFAULT_LX_V2       0x1C
+
+// Defines sequencer count PWREN control values (these settings applied
+// togeteher, when both CPU/V1 and CORE/V2 rails are attached to PWREN;
+// in case when only CPU/V1 rail is attached no delay is specified)
+// B[7:4] - power up delay in 20us taps
+// B[3:0] - power down delay in 20us taps
+#define MAX8907B_SEQCNT_PWREN_LX_V1         0xC0    /* 240us up delay */
+#define MAX8907B_SEQCNT_PWREN_LX_V2         0x00    /* no delay */
+
+// Defines PMU output timing parameters. Scaling up time is dynamically
+// calculated based on the slew rate maintained by MAX8907B. Turn On delay
+// is fixed at max. Turn Off time is "just in case" placeholder -  no need
+// for s/w to track when output capacitors are discharged.
+#define MAX8907B_SCALE_UP_UV_PER_US         (2500)
+#define MAX8907B_TURN_ON_TIME_US            (3000)
+#define MAX8907B_TURN_OFF_TIME_US           (20)
+
+// Output voltages supplied by PMU
+typedef enum
+{
+    Max8907bPmuSupply_Invalid = 0x0,
+
+    /*-- Step-Down DC Regulators --*/
+    Max8907bPmuSupply_LX_V1,    // LX_V1 (V1), step-down DC regulator
+    Max8907bPmuSupply_LX_V2,    // LX_V2 (V2), step-down DC regulator
+    Max8907bPmuSupply_LX_V3,    // LX_V3 (V3), step-down DC regulator
+
+    /*-- Standby LDO --*/
+    Max8907bPmuSupply_VRTC,     // VRTC (RTC), always-on supply for RTC
+
+    /*-- Linear Regulator Outputs --*/
+    Max8907bPmuSupply_LDO1,     // LDO1 (VOUT1), linear regulator output (default = 2.8V)
+    Max8907bPmuSupply_LDO2,     // LDO2 (VOUT2), linear regulator output (default = 1.2V)
+    Max8907bPmuSupply_LDO3,     // LDO3 (VOUT3), linear regulator output (default = 1.2V)
+    Max8907bPmuSupply_LDO4,     // LDO4 (VOUT4), linear regulator output (default = 3.3V)
+    Max8907bPmuSupply_LDO5,     // LDO5 (VOUT5), linear regulator output (default = 1.8V)
+    Max8907bPmuSupply_LDO6,     // LDO6 (VOUT6), linear regulator output (default = 2.8V)
+    Max8907bPmuSupply_LDO7,     // LDO7 (VOUT7), linear regulator output (default = 2.8V)
+    Max8907bPmuSupply_LDO8,     // LDO8 (VOUT8), linear regulator output (default = 2.8V)
+    Max8907bPmuSupply_LDO9,     // LDO9 (VOUT9), linear regulator output (default = 2.8V)
+    Max8907bPmuSupply_LDO10,    // LDO10 (VOUT10), linear regulator output (default = 1.8V)
+    Max8907bPmuSupply_LDO11,    // LDO11 (VOUT11), linear regulator output (default = 2.8V)
+    Max8907bPmuSupply_LDO12,    // LDO12 (VOUT12), linear regulator output (default = 2.8V)
+    Max8907bPmuSupply_LDO13,    // LDO13 (VOUT13), linear regulator output (default = 2.8V)
+    Max8907bPmuSupply_LDO14,    // LDO14 (VOUT14), linear regulator output (default = 3.3V)
+    Max8907bPmuSupply_LDO15,    // LDO15 (VOUT15), linear regulator output (default = 2.8V)
+    Max8907bPmuSupply_LDO16,    // LDO16 (VOUT16), linear regulator output (default = 2.8V)
+    Max8907bPmuSupply_LDO17,    // LDO17 (VOUT17), linear regulator output (default = 1.2V)
+    Max8907bPmuSupply_LDO18,    // LDO18 (VOUT18), linear regulator output (default = 1.2V)
+    Max8907bPmuSupply_LDO19,    // LDO19 (VOUT19), linear regulator output (default = 3.3V)
+    Max8907bPmuSupply_LDO20,    // LDO20 (VOUT20), linear regulator output (default = 1.2V)
+
+    /*-- White LED --*/
+    Max8907bPmuSupply_WHITE_LED,    // (Boost WLED)
+
+    /*-- External DC/DC switcher --*/
+    Max8907bPmuSupply_EXT_DCDC_1,   // EXT_DC/DC1
+    Max8907bPmuSupply_EXT_DCDC_2,   // EXT_DC/DC2
+    Max8907bPmuSupply_EXT_DCDC_3,   // EXT_DC/DC3
+    Max8907bPmuSupply_EXT_DCDC_4,   // EXT_DC/DC4
+    Max8907bPmuSupply_EXT_DCDC_5,   // EXT_DC/DC5
+    Max8907bPmuSupply_EXT_DCDC_6,   // EXT_DC/DC6
+
+    /** USB1 & USB3 VBus's are getting 5V from DCDC_3  **/
+    Max8907bPmuSupply_EXT_DCDC_3_USB1, //USB1 VBUS
+    Max8907bPmuSupply_EXT_DCDC_3_USB3, // USB3 VBUS
+
+    /** Secondary PMU MIC2826 Rails  **/    
+    MIC2826PmuSupply_BUCK,
+    MIC2826PmuSupply_LDO1,
+    MIC2826PmuSupply_LDO2,
+    MIC2826PmuSupply_LDO3,
+
+    // External DCDC controlled by LX_V1, and scaled by digital
+    // potentiometer (DPM) AD5258
+    Max8907bLxV1_Ad5258_DPM_EXT_DCDC_7,
+
+    Max8907bPmuSupply_Num,
+    Max8907bPmuSupply_Force32 = 0x7FFFFFFF
+} Max8907bPmuSupply;
+
+typedef NvU32  (*Max8907bPmuVoltageFunc)(const NvU32 data);
+
+typedef struct Max8907bPmuSupplyInfoRec
+{
+    Max8907bPmuSupply supply;
+
+    // I2C Registers
+    NvU8 ControlRegAddr;
+    NvU8 SequencerCountRegAddr;
+    NvU8 OutputVoltageRegAddr;
+    NvU8 OutputPort;
+    NvU8 PmuGpio;
+
+    Max8907bPmuVoltageFunc GetVoltage;  // Function to convert register bits to real voltage
+    Max8907bPmuVoltageFunc SetVoltage;  // Function to convert real voltage to register bits
+
+    NvOdmPmuVddRailCapabilities cap;
+} Max8907bPmuSupplyInfo;
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif //INCLUDED_MAX8907B_SUPPLY_INFO_HEADER
+
diff --git a/arch/arm/mach-tegra/odm_kit/adaptations/pmu/max8907b/mic2826_i2c.c b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/max8907b/mic2826_i2c.c
new file mode 100644
index 000000000000..097f0510d581
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/max8907b/mic2826_i2c.c
@@ -0,0 +1,119 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include "nvodm_pmu.h"
+#include "nvodm_services.h"
+#include "mic2826_i2c.h"
+#include "mic2826_reg.h"
+
+NvBool MIC2826I2cWrite8(
+    NvOdmPmuDeviceHandle hDevice,
+    NvU8 Addr,
+    NvU8 Data)
+{  
+    NvU8 WriteBuffer[2];
+    NvOdmI2cStatus status = NvOdmI2cStatus_Success;
+    Max8907bPrivData *hPmu = (Max8907bPrivData*)hDevice->pPrivate;    
+    NvOdmI2cTransactionInfo TransactionInfo;
+
+    WriteBuffer[0] = Addr & 0xFF;   
+    WriteBuffer[1] = Data & 0xFF;   // written data
+
+    TransactionInfo.Address = MIC2826_SLAVE_ADDR;
+    TransactionInfo.Buf = &WriteBuffer[0];
+    TransactionInfo.Flags = NVODM_I2C_IS_WRITE;
+    TransactionInfo.NumBytes = 2;
+
+    status = NvOdmI2cTransaction(hPmu->hOdmI2C, &TransactionInfo, 1, 
+                        MIC2826_I2C_SPEED_KHZ, NV_WAIT_INFINITE);
+    if (status == NvOdmI2cStatus_Success)
+    {
+        return NV_TRUE;
+    }
+    else
+    {
+        switch (status)
+        {
+            case NvOdmI2cStatus_Timeout:
+                NVODMPMU_PRINTF(("NvOdmPmuOWI2cWrite8 Failed: Timeout\n")); 
+                break;
+             case NvOdmI2cStatus_SlaveNotFound:
+             default:
+                NVODMPMU_PRINTF(("NvOdmPmuOWI2cWrite8 Failed: SlaveNotFound\n"));
+                break;             
+        }
+        return NV_FALSE;
+    }    
+}
+
+NvBool MIC2826I2cRead8(
+    NvOdmPmuDeviceHandle hDevice,
+    NvU8 Addr,
+    NvU8 *Data)
+{
+    NvU8 ReadBuffer = 0;
+    NvOdmI2cStatus status = NvOdmI2cStatus_Success;
+    Max8907bPrivData *hPmu = (Max8907bPrivData*)hDevice->pPrivate;    
+    NvOdmI2cTransactionInfo TransactionInfo[2];
+
+    ReadBuffer = Addr & 0xFF;
+
+    TransactionInfo[0].Address = MIC2826_SLAVE_ADDR;
+    TransactionInfo[0].Buf = &ReadBuffer;
+    TransactionInfo[0].Flags = NVODM_I2C_IS_WRITE;
+    TransactionInfo[0].NumBytes = 1;    
+    TransactionInfo[1].Address = (MIC2826_SLAVE_ADDR | 0x1);
+    TransactionInfo[1].Buf = &ReadBuffer;
+    TransactionInfo[1].Flags = 0;
+    TransactionInfo[1].NumBytes = 1;
+
+    status = NvOdmI2cTransaction(hPmu->hOdmI2C, &TransactionInfo[0], 2, 
+                                    MIC2826_I2C_SPEED_KHZ, NV_WAIT_INFINITE);
+    if (status != NvOdmI2cStatus_Success)
+    {
+        switch (status)
+        {
+            case NvOdmI2cStatus_Timeout:
+                NVODMPMU_PRINTF(("NvOdmPmuOWI2cRead8 Failed: Timeout\n")); 
+                break;
+             case NvOdmI2cStatus_SlaveNotFound:
+             default:
+                NVODMPMU_PRINTF(("NvOdmPmuOWI2cRead8 Failed: SlaveNotFound\n"));
+                break;             
+        }
+        return NV_FALSE;
+    }  
+
+    *Data = ReadBuffer;
+    return NV_TRUE;
+}
+
diff --git a/arch/arm/mach-tegra/odm_kit/adaptations/pmu/max8907b/mic2826_i2c.h b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/max8907b/mic2826_i2c.h
new file mode 100644
index 000000000000..850ab9907b11
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/max8907b/mic2826_i2c.h
@@ -0,0 +1,65 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_NVODM_PMU_MIC2826_I2C_H
+#define INCLUDED_NVODM_PMU_MIC2826_I2C_H
+
+#include "nvodm_pmu.h"
+#include "max8907b.h"
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+// Constant definition
+#define MIC2826_SLAVE_ADDR      0xB4
+#define MIC2826_I2C_SPEED_KHZ   400
+
+// Function declaration
+NvBool MIC2826I2cWrite8(
+   NvOdmPmuDeviceHandle hPmu,
+   NvU8 Addr,
+   NvU8 Data);
+
+NvBool MIC2826I2cRead8(
+   NvOdmPmuDeviceHandle hPmu,
+   NvU8 Addr,
+   NvU8 *Data);
+
+#if defined(__cplusplus)
+}
+#endif
+
+/** @} */
+
+#endif // INCLUDED_NVODM_PMU_MIC2826_I2C_H
diff --git a/arch/arm/mach-tegra/odm_kit/adaptations/pmu/max8907b/mic2826_reg.h b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/max8907b/mic2826_reg.h
new file mode 100644
index 000000000000..24b31cfa8824
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/max8907b/mic2826_reg.h
@@ -0,0 +1,181 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+ 
+#ifndef MIC2826_REG_HEADER
+#define MIC2826_REG_HEADER
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+#define MIC2826_REG_INVALID              ~0x0
+#define MIC2826_REG_ADDR_ENABLE          0x00
+#define MIC2826_REG_ADDR_STATUS          0x01
+#define MIC2826_REG_ADDR_BUCK            0x02
+#define MIC2826_REG_ADDR_LD01            0x03
+#define MIC2826_REG_ADDR_LD02            0x04
+#define MIC2826_REG_ADDR_LD03            0x05
+
+#define MIC2826_REG_ENABLE_BK            0x1
+#define MIC2826_REG_ENABLE_LDO1          0x2
+#define MIC2826_REG_ENABLE_LDO2          0x4
+#define MIC2826_REG_ENABLE_LDO3          0x8
+#define MIC2826_REG_ENABLE_SEQCNT       ~0x10
+#define MIC2826_REG_ENABLE_POAF         ~0x20
+
+#define MIC2826_REG_DISABLE_BK          ~0x1
+#define MIC2826_REG_DISABLE_LDO1        ~0x2
+#define MIC2826_REG_DISABLE_LDO2        ~0x4
+#define MIC2826_REG_DISABLE_LDO3        ~0x8
+#define MIC2826_REG_DISABLE_SEQCNT       0x10
+#define MIC2826_REG_DISABLE_POAF         0x20
+
+#define MIC2826_REG_STATUS_BK            0x1
+#define MIC2826_REG_STATUS_LDO1          0x2
+#define MIC2826_REG_STATUS_LDO2          0x4
+#define MIC2826_REG_STATUS_LDO3          0x8
+#define MIC2826_TSD_STATUS_TSD           0x10
+#define MIC2826_REG_STATUS_UVLO          0x20
+#define MIC2826_REG_STATUS_TSD_NORMAL   ~0x10
+#define MIC2826_REG_STATUS_UVLO_NORMAL  ~0x20
+
+#define MIC2826_REG_STATUS_INT_EN        0x40
+#define MIC2826_REG_STATUS_INT_DIS      ~0x40
+
+#define MIC2826_BUCK_OUT_VOLTAGE_0800    0x00  //0.800 V
+#define MIC2826_BUCK_OUT_VOLTAGE_0825    0x01  //0.825 V
+#define MIC2826_BUCK_OUT_VOLTAGE_0850    0x02  //0.850 V
+#define MIC2826_BUCK_OUT_VOLTAGE_0875    0x03  //0.875 V
+#define MIC2826_BUCK_OUT_VOLTAGE_0900    0x04  //0.900 V
+#define MIC2826_BUCK_OUT_VOLTAGE_0925    0x05  //0.925 V
+#define MIC2826_BUCK_OUT_VOLTAGE_0950    0x06  //0.950 V
+#define MIC2826_BUCK_OUT_VOLTAGE_0975    0x07  //0.975 V
+#define MIC2826_BUCK_OUT_VOLTAGE_1000    0x08  //1.000 V
+#define MIC2826_BUCK_OUT_VOLTAGE_1025    0x09  //1.025 V
+#define MIC2826_BUCK_OUT_VOLTAGE_1050    0x0A  //1.050 V
+#define MIC2826_BUCK_OUT_VOLTAGE_1075    0x0B  //1.075 V
+#define MIC2826_BUCK_OUT_VOLTAGE_1100    0x0C  //1.100 V
+#define MIC2826_BUCK_OUT_VOLTAGE_1125    0x0D  //1.125 V
+#define MIC2826_BUCK_OUT_VOLTAGE_1150    0x0E  //1.150 V
+#define MIC2826_BUCK_OUT_VOLTAGE_1175    0x0F  //1.175 V
+#define MIC2826_BUCK_OUT_VOLTAGE_1200    0x10  //1.200 V
+#define MIC2826_BUCK_OUT_VOLTAGE_1250    0x11  //1.250 V
+#define MIC2826_BUCK_OUT_VOLTAGE_1300    0x12  //1.300 V
+#define MIC2826_BUCK_OUT_VOLTAGE_1350    0x13  //1.350 V
+#define MIC2826_BUCK_OUT_VOLTAGE_1400    0x14  //1.400 V
+#define MIC2826_BUCK_OUT_VOLTAGE_1450    0x15  //1.450 V
+#define MIC2826_BUCK_OUT_VOLTAGE_1500    0x16  //1.500 V
+#define MIC2826_BUCK_OUT_VOLTAGE_1550    0x17  //1.550 V
+#define MIC2826_BUCK_OUT_VOLTAGE_1600    0x18  //1.600 V
+#define MIC2826_BUCK_OUT_VOLTAGE_1650    0x19  //1.650 V
+#define MIC2826_BUCK_OUT_VOLTAGE_1700    0x1A  //1.700 V
+#define MIC2826_BUCK_OUT_VOLTAGE_1750    0x1B  //1.750 V
+#define MIC2826_BUCK_OUT_VOLTAGE_1800    0x1C  //1.800 V
+
+#define MIC2826_LDO_OUT_VOLTAGE_0800     0x00  //0.800 V
+#define MIC2826_LDO_OUT_VOLTAGE_0850     0x0B  //0.850 V
+#define MIC2826_LDO_OUT_VOLTAGE_0900     0x14  //0.900 V
+#define MIC2826_LDO_OUT_VOLTAGE_0950     0x1D  //0.950 V
+#define MIC2826_LDO_OUT_VOLTAGE_1000     0x25  //1.000 V
+#define MIC2826_LDO_OUT_VOLTAGE_1050     0x2E  //1.050 V
+#define MIC2826_LDO_OUT_VOLTAGE_1100     0x37  //1.100 V
+#define MIC2826_LDO_OUT_VOLTAGE_1150     0x3E  //1.150 V
+#define MIC2826_LDO_OUT_VOLTAGE_1200     0x45  //1.200 V
+#define MIC2826_LDO_OUT_VOLTAGE_1250     0x4B  //1.250 V
+#define MIC2826_LDO_OUT_VOLTAGE_1300     0x51  //1.300 V
+#define MIC2826_LDO_OUT_VOLTAGE_1350     0x57  //1.350 V
+#define MIC2826_LDO_OUT_VOLTAGE_1400     0x5C  //1.400 V
+#define MIC2826_LDO_OUT_VOLTAGE_1450     0x60  //1.450 V
+#define MIC2826_LDO_OUT_VOLTAGE_1500     0x65  //1.500 V
+#define MIC2826_LDO_OUT_VOLTAGE_1550     0x69  //1.550 V
+#define MIC2826_LDO_OUT_VOLTAGE_1600     0x6D  //1.600 V
+#define MIC2826_LDO_OUT_VOLTAGE_1650     0x72  //1.650 V
+#define MIC2826_LDO_OUT_VOLTAGE_1700     0x78  //1.700 V
+#define MIC2826_LDO_OUT_VOLTAGE_1750     0x75  //1.750 V
+#define MIC2826_LDO_OUT_VOLTAGE_1800     0x85  //1.800 V
+#define MIC2826_LDO_OUT_VOLTAGE_1850     0x8B  //1.850 V
+#define MIC2826_LDO_OUT_VOLTAGE_1900     0x90  //1.900 V
+#define MIC2826_LDO_OUT_VOLTAGE_1950     0x95  //1.950 V
+#define MIC2826_LDO_OUT_VOLTAGE_2000     0x9A  //2.000 V
+#define MIC2826_LDO_OUT_VOLTAGE_2050     0x9F  //2.050 V
+#define MIC2826_LDO_OUT_VOLTAGE_2100     0xA3  //2.100 V
+#define MIC2826_LDO_OUT_VOLTAGE_2150     0xA7  //2.150 V
+#define MIC2826_LDO_OUT_VOLTAGE_2200     0xAB  //2.200 V
+#define MIC2826_LDO_OUT_VOLTAGE_2250     0xA0  //2.250 V
+#define MIC2826_LDO_OUT_VOLTAGE_2300     0xB3  //2.300 V
+#define MIC2826_LDO_OUT_VOLTAGE_2350     0xB7  //2.350 V
+#define MIC2826_LDO_OUT_VOLTAGE_2400     0xBA  //2.400 V
+#define MIC2826_LDO_OUT_VOLTAGE_2450     0xBD  //2.450 V
+#define MIC2826_LDO_OUT_VOLTAGE_2500     0xC1  //2.500 V
+#define MIC2826_LDO_OUT_VOLTAGE_2550     0xC3  //2.550 V
+#define MIC2826_LDO_OUT_VOLTAGE_2600     0xC6  //2.600 V
+#define MIC2826_LDO_OUT_VOLTAGE_2650     0xC9  //2.650 V
+#define MIC2826_LDO_OUT_VOLTAGE_2700     0xCB  //2.700 V
+#define MIC2826_LDO_OUT_VOLTAGE_2750     0xCE  //2.750 V
+#define MIC2826_LDO_OUT_VOLTAGE_2800     0xD1  //2.800 V
+#define MIC2826_LDO_OUT_VOLTAGE_2850     0xD3  //2.850 V
+#define MIC2826_LDO_OUT_VOLTAGE_2900     0xD5  //2.900 V
+#define MIC2826_LDO_OUT_VOLTAGE_2950     0xD8  //2.950 V
+#define MIC2826_LDO_OUT_VOLTAGE_3000     0xDA  //3.000 V
+#define MIC2826_LDO_OUT_VOLTAGE_3050     0xDC  //3.050 V
+#define MIC2826_LDO_OUT_VOLTAGE_3100     0xDE  //3.100 V
+#define MIC2826_LDO_OUT_VOLTAGE_3150     0xE0  //3.150 V
+#define MIC2826_LDO_OUT_VOLTAGE_3200     0xE3  //3.200 V
+#define MIC2826_LDO_OUT_VOLTAGE_3250     0xE6  //3.250 V
+#define MIC2826_LDO_OUT_VOLTAGE_3300     0xE8  //3.300 V
+
+#define MIC2826_BUCK_VOLTAGE_OFFSET      800
+#define MIC2826_BUCK_VOLTAGE_MIN_MV      800
+#define MIC2826_BUCK_VOLTAGE_STEP_MV     25
+#define MIC2826_BUCK_VOLTAGE_STEP_25MV   25
+#define MIC2826_BUCK_VOLTAGE_STEP_50MV   50
+#define MIC2826_BUCK_VOLTAGE_MAX_MV      1800
+#define MIC2826_BUCK_REQUESTVOLTAGE_MV   1800
+
+#define MIC2826_LDO_VOLTAGE_OFFSET       800
+#define MIC2826_LDO_VOLTAGE_MIN_MV       800
+#define MIC2826_LDO_VOLTAGE_STEP_MV      50
+#define MIC2826_LDO_VOLTAGE_MAX_MV       3300
+#define MIC2826_LDO1_REQUESTVOLTAGE_MV   1800
+#define MIC2826_LDO2_REQUESTVOLTAGE_MV   1800
+#define MIC2826_LDO3_REQUESTVOLTAGE_MV   1200
+
+#define MIC2826_INVALID_PORT             0xFF
+
+
+#if defined(__cplusplus)
+}
+#endif
+
+
+#endif
diff --git a/arch/arm/mach-tegra/odm_kit/adaptations/pmu/max8907b/tca6416_expander_i2c.c b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/max8907b/tca6416_expander_i2c.c
new file mode 100644
index 000000000000..4ca397b9951b
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/max8907b/tca6416_expander_i2c.c
@@ -0,0 +1,190 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include "nvodm_pmu.h"
+#include "nvodm_services.h"
+#include "tca6416_expander_i2c.h"
+#include "tca6416_expander_reg.h"
+
+
+
+#define TCA6416_SLAVE_ADDR      0x40    // (7'h20)
+#define TCA6416_I2C_SPEED_KHZ   400
+
+
+NvBool
+Tca6416ConfigPortPin(
+    NvOdmPmuDeviceHandle hDevice,
+    NvU32 PortNo,
+    NvU32 PinNo,
+    GpioPinMode Mode)
+{
+    NvU8 WriteBuffer[2];
+    NvOdmI2cStatus Error;
+    Max8907bPrivData *hPmu = (Max8907bPrivData*)hDevice->pPrivate;
+
+    NvOdmI2cTransactionInfo TransactionInfo;
+    static NvU8  ConfigPort1Val = 0xFF; //  set to default value
+    static NvU8  ConfigPort2Val = 0xFF; //  set to default value
+
+    if (PortNo == TCA6416_PORT_0)
+    {
+        WriteBuffer[0] =  TCA6416_CONFIG_PORT_0 & 0xFF;
+
+        if (Mode == GpioPinMode_Output)
+        {
+            WriteBuffer[1] = ((ConfigPort1Val & (0xFF & (~(1 << PinNo)))) | (0x0 << PinNo));
+        } else if (Mode == GpioPinMode_InputData)
+        {
+            WriteBuffer[1] = ((ConfigPort1Val & (0xFF & (~(1 << PinNo)))) | (0x1 << PinNo));
+        }
+        ConfigPort1Val = WriteBuffer[1];
+    }else if (PortNo == TCA6416_PORT_1)
+    {
+        WriteBuffer[0] = TCA6416_CONFIG_PORT_1 & 0xFF;
+
+        if (Mode == GpioPinMode_Output)
+        {
+            WriteBuffer[1] = (ConfigPort2Val & (0xFF & (~(1 << PinNo))));
+        } else if (Mode == GpioPinMode_InputData)
+        {
+            WriteBuffer[1] = ((ConfigPort2Val & (0xFF & (~(1 << PinNo)))) | (0x1 << PinNo));
+        }
+        ConfigPort2Val = WriteBuffer[1];
+    }
+
+    TransactionInfo.Address = TCA6416_SLAVE_ADDR;
+    TransactionInfo.Buf = WriteBuffer;
+    TransactionInfo.Flags = NVODM_I2C_IS_WRITE;
+    TransactionInfo.NumBytes = 2;
+
+    // write the pmu Offset (from where data gpio need to be set)
+    Error = NvOdmI2cTransaction(hPmu->hOdmI2C, &TransactionInfo, 1,
+                            TCA6416_I2C_SPEED_KHZ, NV_WAIT_INFINITE);
+
+    if (Error == NvOdmI2cStatus_Success)
+    {
+        return NV_TRUE;
+    }
+    else
+    {
+        switch (Error)
+        {
+            case NvOdmI2cStatus_Timeout:
+                NVODMPMU_PRINTF(("Tca6416ConfigPortPin Failed: Timeout\n")); 
+                break;
+             case NvOdmI2cStatus_SlaveNotFound:
+             default:
+                NVODMPMU_PRINTF(("Tca6416ConfigPortPin Failed: SlaveNotFound\n"));
+                break;
+        }
+        return NV_FALSE;
+    }
+}
+
+
+NvBool
+Tca6416WritePortPin(
+    NvOdmPmuDeviceHandle hDevice,
+    NvU32 PortNo,
+    NvU32 PinNo,
+    GpioPinState data)
+{
+    NvOdmI2cTransactionInfo TransactionInfo;
+    NvOdmI2cStatus Error;
+    NvU8 WriteBuffer[2];
+    Max8907bPrivData *hPmu = (Max8907bPrivData*)hDevice->pPrivate;
+
+    static NvU8  OutPut1Val = 0xFF; //  set to default value
+    static NvU8  OutPut2Val = 0xFF; //  set to default value
+
+
+    /* set the command byte */
+    if (PortNo == TCA6416_PORT_0)
+    {
+        WriteBuffer[0] = TCA6416_OUTPUT_PORT_0 & 0xFF;
+        // Set the data 
+        WriteBuffer[1] =  ((OutPut1Val & (0xFF & (~(1 << PinNo)))) | (data << PinNo));
+
+        OutPut1Val = WriteBuffer[1];
+
+    } else if (PortNo == TCA6416_PORT_1)
+    {
+        WriteBuffer[0] = TCA6416_OUTPUT_PORT_1 & 0xFF;
+        // Set the data
+        WriteBuffer[1] =  ((OutPut2Val & (0xFF & (~(1 << PinNo)))) | (data << PinNo));
+
+        OutPut2Val = WriteBuffer[1];
+    }
+
+    TransactionInfo.Address = TCA6416_SLAVE_ADDR;
+    TransactionInfo.Buf = WriteBuffer;
+    TransactionInfo.Flags = NVODM_I2C_IS_WRITE;
+    TransactionInfo.NumBytes = 2;
+
+    Error = NvOdmI2cTransaction(hPmu->hOdmI2C, &TransactionInfo, 1,
+                    TCA6416_I2C_SPEED_KHZ, NV_WAIT_INFINITE);
+
+    if (Error == NvOdmI2cStatus_Success)
+    {
+        return NV_TRUE;
+    }
+    else
+    {
+        switch (Error)
+        {
+            case NvOdmI2cStatus_Timeout:
+                NVODMPMU_PRINTF(("Tca6416I2cWrite8 Failed: Timeout\n")); 
+                break;
+             case NvOdmI2cStatus_SlaveNotFound:
+             default:
+                NVODMPMU_PRINTF(("Tca6416I2cWrite8 Failed: SlaveNotFound\n"));
+                break;
+        }
+        return NV_FALSE;
+    }
+}
+
+NvBool
+Tca6416ReadPortPin(
+    NvOdmPmuDeviceHandle hDevice,
+    NvU32 PortNo,
+    NvU32 PinNo,
+    GpioPinState*State)
+{
+
+    // Need to implement
+    return NV_TRUE;
+}
+
+
+
diff --git a/arch/arm/mach-tegra/odm_kit/adaptations/pmu/max8907b/tca6416_expander_i2c.h b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/max8907b/tca6416_expander_i2c.h
new file mode 100644
index 000000000000..ce14b79df090
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/max8907b/tca6416_expander_i2c.h
@@ -0,0 +1,109 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_TCA6416_EXPANDER_I2C_H
+#define INCLUDED_TCA6416_EXPANDER_I2C_H
+
+#include "nvodm_pmu.h"
+#include "max8907b.h"
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+
+
+/**
+ * @brief Defines the possible modes.
+ */
+
+typedef enum
+{
+
+    /**
+     * Specifies the gpio pin as not in use. 
+     */
+    GpioPinMode_Inactive = 0,
+
+    /// Specifies the gpio pin mode as input.
+    GpioPinMode_InputData,
+
+    /// Specifies the gpio pin mode as output.
+    GpioPinMode_Output,
+
+    GpioPinMode_Num,
+    GpioPinMode_Force32 = 0x7FFFFFFF
+} GpioPinMode;
+
+
+/** 
+ * @brief Defines the pin state
+ */
+
+typedef enum
+{
+   // Pin state high 
+    GpioPinState_Low = 0,
+    // Pin is high
+    GpioPinState_High,
+    GpioPinState_Num,
+    GpioPinState_Force32 = 0x7FFFFFFF
+} GpioPinState;
+
+
+NvBool Tca6416ConfigPortPin(
+    NvOdmPmuDeviceHandle hDevice,
+    NvU32 portNo,
+    NvU32 pinNo,
+    GpioPinMode Mode);
+
+NvBool Tca6416WritePortPin(
+    NvOdmPmuDeviceHandle hDevice,
+    NvU32 portNo,
+    NvU32 pinNo,
+    GpioPinState data);
+
+NvBool Tca6416ReadPortPin(
+    NvOdmPmuDeviceHandle hDevice,
+    NvU32 portNo,
+    NvU32 pinNo, 
+    GpioPinState*State);
+
+
+#if defined(__cplusplus)
+}
+#endif
+
+/** @} */
+
+#endif // INCLUDED_TCA6416_EXPANDER_I2C_H
diff --git a/arch/arm/mach-tegra/odm_kit/adaptations/pmu/max8907b/tca6416_expander_reg.h b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/max8907b/tca6416_expander_reg.h
new file mode 100644
index 000000000000..588335a804c8
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/max8907b/tca6416_expander_reg.h
@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+ 
+#ifndef INCLUDED_TCA6416_EXPANDER_REG_HEADER
+#define INCLUDED_TCA6416_EXPANDER_REG_HEADER
+
+
+// Ports evailable on TCA6416. it is having 2 ports
+#define TCA6416_PORT_0  0
+#define TCA6416_PORT_1  1
+
+
+// Each port is having 8 pins 
+#define TCA6416_PIN_0  0
+#define TCA6416_PIN_1  1
+#define TCA6416_PIN_2  2
+#define TCA6416_PIN_3  3
+#define TCA6416_PIN_4  4
+#define TCA6416_PIN_5  5
+#define TCA6416_PIN_6  6
+#define TCA6416_PIN_7  7
+
+
+// Registers
+#define TCA6416_INPUT_PORT_0            0x00    // For ports 00 to 07
+#define TCA6416_INPUT_PORT_1            0x01    // For ports 10 to 17
+#define TCA6416_OUTPUT_PORT_0           0x02    // For ports 00 to 07
+#define TCA6416_OUTPUT_PORT_1           0x03    // For ports 10 to 17
+#define TCA6416_POLARITY_INV_PORT_0     0x04    // For ports 00 to 07
+#define TCA6416_POLARITY_INV_PORT_1     0x05    // For ports 10 to 17
+#define TCA6416_CONFIG_PORT_0           0x06    // For ports 00 to 07
+#define TCA6416_CONFIG_PORT_1           0x07    // For ports 10 to 17
+
+
+
+#define TCA6416_INVALID_PORT    0xFF
+
+#endif //INCLUDED_TCA6416_EXPANDER_REG_HEADER
+
diff --git a/arch/arm/mach-tegra/odm_kit/adaptations/pmu/pcf50626/Makefile b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/pcf50626/Makefile
new file mode 100644
index 000000000000..9e7fe0bcdb16
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/pcf50626/Makefile
@@ -0,0 +1,21 @@
+ccflags-y += -DNV_IS_AVP=0
+ccflags-y += -DNV_OAL=0
+ccflags-y += -DNV_USE_FUSE_CLOCK_ENABLE=0
+ifeq ($(CONFIG_MACH_TEGRA_GENERIC_DEBUG),y)
+ccflags-y += -DNV_DEBUG=1
+else
+ccflags-y += -DNV_DEBUG=0
+endif
+
+ccflags-y += -Iarch/arm/mach-tegra/odm_kit/adaptations/pmu
+ccflags-y += -Iarch/arm/mach-tegra/odm_kit/adaptations/pmu/pcf50626
+
+obj-y += ds2482_bridge.o
+obj-y += ds2482_i2c.o
+obj-y += pcf50626_adc.o
+obj-y += pcf50626_batterycharger.o
+obj-y += pcf50626.o
+obj-y += pcf50626_i2c.o
+obj-y += pcf50626_interrupt.o
+obj-y += pcf50626_rtc.o
+obj-y += platform.o
diff --git a/arch/arm/mach-tegra/odm_kit/adaptations/pmu/pcf50626/ds2482_bridge.c b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/pcf50626/ds2482_bridge.c
new file mode 100644
index 000000000000..ecc09f8e6775
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/pcf50626/ds2482_bridge.c
@@ -0,0 +1,70 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include "ds2482_bridge.h"
+#include "pcf50626_i2c.h"
+#include "ds2482_i2c.h"
+#include "pcf50626_reg.h"
+#include "ds2482_reg.h"
+
+NvBool 
+Ds2482Setup(NvOdmPmuDeviceHandle hDevice)
+{
+    NvU8 data = 0;
+    
+    // One wire I2C bridge
+    //Device Reset Status
+    if (!Ds2482OWI2cRead8(hDevice, DS2482_DEVICE_RESET, &data))
+        return NV_FALSE;
+    //NVODMPMU_PRINTF(("Device Reset reg 0x%02x = 0x%02x\n", DS2482_DEVICE_RESET, data));
+
+    //1-Wire Reset Status
+    if (!Ds2482OWI2cRead8(hDevice, DS2482_1WIRE_RESET, &data))
+        return NV_FALSE;
+    //NVODMPMU_PRINTF(("1-Wire Reset reg 0x%02x = 0x%02x\n", DS2482_1WIRE_RESET, data));
+
+    while(1)
+    {
+        if (!Ds2482OWI2cWrite8(hDevice, DS2482_READ_DATA_REG_ADDR, DS2482_DEVICE_RESET))
+            return NV_FALSE;
+
+        if (!Ds2482OWI2cRead8(hDevice, DS2482_READ_DATA_REG_ADDR, &data))
+            return NV_FALSE;
+
+        if (!(data & 0x01))
+            break;
+    }
+
+
+    return NV_TRUE;
+}
+
diff --git a/arch/arm/mach-tegra/odm_kit/adaptations/pmu/pcf50626/ds2482_bridge.h b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/pcf50626/ds2482_bridge.h
new file mode 100644
index 000000000000..84111f8a7876
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/pcf50626/ds2482_bridge.h
@@ -0,0 +1,58 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_DS2482_BRIDGE_H
+#define INCLUDED_DS2482_BRIDGE_H
+
+#include "nvodm_pmu.h"
+#include "pcf50626.h"
+
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+NvBool 
+Ds2482Setup(NvOdmPmuDeviceHandle hDevice);
+
+NvBool
+Ds2482BatteryPresented(
+    NvOdmPmuDeviceHandle hDevice, 
+    NvBool *BattPresence);
+
+#if defined(__cplusplus)
+}
+#endif
+
+
+#endif // INCLUDED_DS2482_BRIDGE_H
diff --git a/arch/arm/mach-tegra/odm_kit/adaptations/pmu/pcf50626/ds2482_i2c.c b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/pcf50626/ds2482_i2c.c
new file mode 100644
index 000000000000..09f1194e2a30
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/pcf50626/ds2482_i2c.c
@@ -0,0 +1,119 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include "ds2482_i2c.h"
+#include "nvodm_pmu.h"
+#include "nvodm_services.h"
+#include "ds2482_reg.h"
+
+NvBool Ds2482OWI2cWrite8(
+    NvOdmPmuDeviceHandle hDevice,
+    NvU8 Addr,
+    NvU8 Data)
+{  
+    NvU8 WriteBuffer[2];
+    NvOdmI2cStatus status  = NvOdmI2cStatus_Success;
+    Pcf50626PrivData *hPmu = (Pcf50626PrivData*)hDevice->pPrivate;
+    NvOdmI2cTransactionInfo TransactionInfo;
+
+    WriteBuffer[0] = Addr & 0xFF;   
+    WriteBuffer[1] = Data & 0xFF;   // written data
+
+    TransactionInfo.Address = DS2482_SLAVE_ADDR;
+    TransactionInfo.Buf = &WriteBuffer[0];
+    TransactionInfo.Flags = NVODM_I2C_IS_WRITE;
+    TransactionInfo.NumBytes = 2;
+
+    status = NvOdmI2cTransaction(hPmu->hOdmI2C, &TransactionInfo, 1, 
+                        DS2482_I2C_SPEED_KHZ, NV_WAIT_INFINITE);
+    if (status == NvOdmI2cStatus_Success)
+    {
+        return NV_TRUE;
+    }
+    else
+    {
+        switch (status)
+        {
+            case NvOdmI2cStatus_Timeout:
+                NVODMPMU_PRINTF(("NvOdmPmuOWI2cWrite8 Failed: Timeout\n")); 
+                break;
+             case NvOdmI2cStatus_SlaveNotFound:
+             default:
+                NVODMPMU_PRINTF(("NvOdmPmuOWI2cWrite8 Failed: SlaveNotFound\n"));
+                break;             
+        }
+        return NV_FALSE;
+    }    
+}
+
+NvBool Ds2482OWI2cRead8(
+    NvOdmPmuDeviceHandle hDevice,
+    NvU8 Addr,
+    NvU8 *Data)
+{
+    NvU8 ReadBuffer = 0;
+    NvOdmI2cStatus  status = NvOdmI2cStatus_Success;
+    Pcf50626PrivData *hPmu = (Pcf50626PrivData*)hDevice->pPrivate;
+    NvOdmI2cTransactionInfo TransactionInfo[2];
+
+    ReadBuffer = Addr & 0xFF;
+
+    TransactionInfo[0].Address = DS2482_SLAVE_ADDR;
+    TransactionInfo[0].Buf = &ReadBuffer;
+    TransactionInfo[0].Flags = NVODM_I2C_IS_WRITE;
+    TransactionInfo[0].NumBytes = 1;    
+    TransactionInfo[1].Address = (DS2482_SLAVE_ADDR | 0x1);
+    TransactionInfo[1].Buf = &ReadBuffer;
+    TransactionInfo[1].Flags = 0;
+    TransactionInfo[1].NumBytes = 1;
+
+    status = NvOdmI2cTransaction(hPmu->hOdmI2C, &TransactionInfo[0], 2, 
+                                    DS2482_I2C_SPEED_KHZ, NV_WAIT_INFINITE);
+    if (status != NvOdmI2cStatus_Success)
+    {
+        switch (status)
+        {
+            case NvOdmI2cStatus_Timeout:
+                NVODMPMU_PRINTF(("NvOdmPmuOWI2cRead8 Failed: Timeout\n")); 
+                break;
+             case NvOdmI2cStatus_SlaveNotFound:
+             default:
+                NVODMPMU_PRINTF(("NvOdmPmuOWI2cRead8 Failed: SlaveNotFound\n"));
+                break;             
+        }
+        return NV_FALSE;
+    }  
+
+    *Data = ReadBuffer;
+    return NV_TRUE;
+}
+
diff --git a/arch/arm/mach-tegra/odm_kit/adaptations/pmu/pcf50626/ds2482_i2c.h b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/pcf50626/ds2482_i2c.h
new file mode 100644
index 000000000000..af6ea8c9330e
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/pcf50626/ds2482_i2c.h
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_NVODM_PMU_DS2482_I2C_H
+#define INCLUDED_NVODM_PMU_DS2482_I2C_H
+
+#include "pcf50626.h"
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+// Constant definition
+#define DS2482_SLAVE_ADDR      0x32
+#define DS2482_I2C_SPEED_KHZ   400
+
+// Function declaration
+NvBool Ds2482OWI2cWrite8(
+   NvOdmPmuDeviceHandle hDevice,
+   NvU8 Addr,
+   NvU8 Data);
+
+NvBool Ds2482OWI2cRead8(
+   NvOdmPmuDeviceHandle hDevice,
+   NvU8 Addr,
+   NvU8 *Data);
+
+#if defined(__cplusplus)
+}
+#endif
+
+/** @} */
+
+#endif // INCLUDED_NVODM_PMU_DS2482_I2C_H
diff --git a/arch/arm/mach-tegra/odm_kit/adaptations/pmu/pcf50626/ds2482_reg.h b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/pcf50626/ds2482_reg.h
new file mode 100644
index 000000000000..6ce603046918
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/pcf50626/ds2482_reg.h
@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+ 
+#ifndef DS2482_REG_HEADER
+#define DS2482_REG_HEADER
+
+#define DS2482_DEVICE_RESET     0xF0
+#define DS2482_1WIRE_RESET      0xB4
+#define DS2482_STATUS_REG_ADDR              0xF0
+#define DS2482_READ_DATA_REG_ADDR           0xE1
+#define DS2482_CONFIGURATION_REG_ADDR       0xC3
+
+
+#endif //DS2482_REG_HEADER
+
diff --git a/arch/arm/mach-tegra/odm_kit/adaptations/pmu/pcf50626/nvodm_pmu_pcf50626_supply_info.h b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/pcf50626/nvodm_pmu_pcf50626_supply_info.h
new file mode 100644
index 000000000000..bf46e600401f
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/pcf50626/nvodm_pmu_pcf50626_supply_info.h
@@ -0,0 +1,144 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef PCF50626_SUPPLY_INFO_HEADER
+#define PCF50626_SUPPLY_INFO_HEADER
+
+#include "pcf50626.h"
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+
+ typedef enum
+{
+    PCF50626PmuSupply_Invalid = 0x0,
+
+    //DCD1
+    PCF50626PmuSupply_DCD1,
+
+    //DCD2
+    PCF50626PmuSupply_DCD2,
+
+    //DCUD
+    PCF50626PmuSupply_DCUD,
+    
+    //DCULED
+    PCF50626PmuSupply_DCULED,
+     
+    //RF1REG
+    PCF50626PmuSupply_RF1REG,
+
+    //RF2REG
+    PCF50626PmuSupply_RF2REG,
+
+    //RF3REG
+    PCF50626PmuSupply_RF3REG,
+
+    //RF4REG
+    PCF50626PmuSupply_RF4REG,
+
+    //D1REG
+    PCF50626PmuSupply_D1REG,
+
+    //D2REG
+    PCF50626PmuSupply_D2REG,
+
+    //D3REG
+    PCF50626PmuSupply_D3REG,
+
+    //D4REG
+    PCF50626PmuSupply_D4REG,
+
+    //D5REG
+    PCF50626PmuSupply_D5REG,
+
+    //D6REG
+    PCF50626PmuSupply_D6REG,
+
+    //D7REG
+    PCF50626PmuSupply_D7REG,
+
+    //D8REG
+    PCF50626PmuSupply_D8REG,
+
+    //HCREG
+    PCF50626PmuSupply_HCREG,
+
+    //IOREG
+    PCF50626PmuSupply_IOREG,
+
+    //USIMREG
+    PCF50626PmuSupply_USIMREG,
+
+    //USBREG
+    PCF50626PmuSupply_USBREG,
+
+    //LCREG
+    PCF50626PmuSupply_LCREG,
+
+    //VBAT
+    PCF50626PmuSupply_VBAT,
+
+    PCF50626PmuSupply_Num,
+    PCF50626PmuSupply_Force32 = 0x7FFFFFFF
+} PCF50626PmuSupply;
+
+
+typedef struct PCF50626PmuSupplyInfoRec
+{
+    PCF50626PmuSupply supply;
+    PCF50626PmuSupply supplyInput;
+    NvU8 control1Addr;
+    NvU8 control2Addr;
+    NvU8 control3Addr;
+    NvU8 control4Addr;
+
+    NvU8 dvm1Addr;
+    NvU8 dvm2Addr;
+    NvU8 dvm3Addr;
+    NvU8 dvmTimAddr;
+
+    NvOdmPmuVddRailCapabilities cap;
+    NvU32 offsetVoltage;    
+    NvU32 turnOnTimeMicroSec;
+    NvU32 switchTimeMicroSec;    
+} PCF50626PmuSupplyInfo;
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif //PCF50626_VOLTAGE_INFO_TABLE_HEADER
+
diff --git a/arch/arm/mach-tegra/odm_kit/adaptations/pmu/pcf50626/pcf50626.c b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/pcf50626/pcf50626.c
new file mode 100644
index 000000000000..9272dbdddbc5
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/pcf50626/pcf50626.c
@@ -0,0 +1,938 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include "nvodm_query_discovery.h"
+#include "nvodm_query.h"
+#include "nvodm_services.h"
+#include "pcf50626_i2c.h"
+#include "pcf50626.h"
+#include "pcf50626_batterycharger.h"
+#include "pcf50626_adc.h"
+#include "pcf50626_interrupt.h"
+#include "pcf50626_supply_info_table.h"
+
+#ifndef PMU_MAX
+#define PMU_MAX(a,b)        ((a)<(b)?(b):(a))
+#endif
+
+#define BATTEMP_CONTROL     (0)
+
+// Board IDs
+#define NVODM_PMU_BOARD_ID_E924   0x0918
+#define NVODM_PMU_BOARD_ID_E934   0x0922
+
+// SKUs
+#define NVODM_PMU_BOARD_SAMSUNG_26_MHZ_OSC    0x0A00
+#define NVODM_PMU_BOARD_HYNIX_12_MHZ_XTAL     0x0A01
+
+// h/w configuration
+#define CHARGER_CONSTANT_CURRENT_SET_MA  (NvU32)(125000/127)
+#define MAX_CHARGER_LIMIT_MA 850
+
+// This PMU does not have differnet charger programming 
+// So setting all types of charger limit to the default charger limit
+#define SE0_TYPE_CHARGER_LIMIT_MA MAX_CHARGER_LIMIT_MA
+#define SE1_TYPE_CHARGER_LIMIT_MA MAX_CHARGER_LIMIT_MA
+#define SJ_TYPE_CHARGER_LIMIT_MA MAX_CHARGER_LIMIT_MA
+#define SK_TYPE_CHARGER_LIMIT_MA MAX_CHARGER_LIMIT_MA
+
+
+// threshold for battery status. need to fine tune based on battery/system characterisation
+#define NVODM_BATTERY_FULL_VOLTAGE_MV      4150
+#define NVODM_BATTERY_HIGH_VOLTAGE_MV      3900
+#define NVODM_BATTERY_LOW_VOLTAGE_MV       3300
+#define NVODM_BATTERY_CRITICAL_VOLTAGE_MV  3100
+
+#define NVODM_BATTERY_OVERHEAT_THRESHOLD   70
+
+
+Pcf50626PrivData *pPrivData;
+//Concorde WAR for the USB Host mode
+NvBool UsbHostMode;
+
+#define PMUGUID NV_ODM_GUID('p','c','f','_','p','m','u','0')
+
+
+// Calulate the battery life percentage according to the battery voltage.
+static NvU32 
+Pcf50626CalulateBatteryLifePercent_int(NvU32 vBatSense);
+
+#if BATTEMP_CONTROL
+// switch off the chargeer if the battery temperature is too high
+static NvBool 
+Pcf50626BatteryTemperatureControl_int(
+    NvOdmPmuDeviceHandle hDevice,
+    NvU32 batTemp);
+#endif
+
+// Read the voltage setting from PCF50626 registers
+static NvBool 
+Pcf50626ReadVoltageReg(
+    NvOdmPmuDeviceHandle hDevice, 
+    NvU32 vddRail, 
+    NvU32* pMilliVolts);
+
+// Write the voltage setting from PCF50626 registers
+static NvBool 
+Pcf50626WriteVoltageReg(
+    NvOdmPmuDeviceHandle hDevice, 
+    NvU32 vddRail, 
+    NvU32 MilliVolts, 
+    NvU32* pSettleMicroSeconds);
+
+
+void
+Pcf50626GetCapabilities(
+    NvU32 vddRail,
+    NvOdmPmuVddRailCapabilities* pCapabilities)
+{
+    NvOdmBoardInfo BoardInfo;
+    NvBool Status = NV_FALSE;
+
+    NV_ASSERT(pCapabilities);
+    NV_ASSERT(vddRail < PCF50626PmuSupply_Num);
+
+    *pCapabilities = pcf50626SupplyInfoTable[vddRail].cap;
+
+    if (vddRail == PCF50626PmuSupply_DCD2)
+    {
+        Status = NvOdmPeripheralGetBoardInfo(NVODM_PMU_BOARD_ID_E924, &BoardInfo);
+        if (Status == NV_TRUE)
+        {
+            if ((BoardInfo.SKU == NVODM_PMU_BOARD_SAMSUNG_26_MHZ_OSC) ||
+                (BoardInfo.SKU == NVODM_PMU_BOARD_HYNIX_12_MHZ_XTAL))
+            {
+                // Use 1.8v DDR (TO DO: Don't use a magic number here; define this.)
+                pCapabilities->requestMilliVolts = 1800;
+            }
+        }
+        else
+        {
+            Status = NvOdmPeripheralGetBoardInfo(NVODM_PMU_BOARD_ID_E934, &BoardInfo);
+            if (Status == NV_TRUE)
+            {
+                if (BoardInfo.SKU == NVODM_PMU_BOARD_HYNIX_12_MHZ_XTAL)
+                {
+                    // Use 1.8v DDR (TO DO: Don't use a magic number here; define this.)
+                    pCapabilities->requestMilliVolts = 1800;
+                }
+            }
+            else
+            {
+                // Use default DDR voltage (1.925v)
+                ;
+            }
+        }
+    }
+}
+
+
+NvBool Pcf50626Setup(NvOdmPmuDeviceHandle hDevice)
+{
+    NvOdmIoModule I2cModule = NvOdmIoModule_I2c;
+    NvU32  I2cInstance = 0;
+    NvU32  I2cAddress  = 0;    
+    NvU32  i           = 0;
+    NvBool status      = NV_FALSE;
+    
+    const NvOdmPeripheralConnectivity *pConnectivity = 
+                           NvOdmPeripheralGetGuid(PMUGUID);
+    
+    NV_ASSERT(hDevice);
+
+    
+    pPrivData = (Pcf50626PrivData*) NvOdmOsAlloc(sizeof(Pcf50626PrivData));
+    if (pPrivData == NULL)
+    {
+        NVODMPMU_PRINTF(("Error Allocating Pcf50626PrivData. \n"));
+        return NV_FALSE;
+    }
+    NvOdmOsMemset(pPrivData, 0, sizeof(Pcf50626PrivData));
+    hDevice->pPrivate = pPrivData;
+
+    ((Pcf50626PrivData*)hDevice->pPrivate)->supplyRefCntTable = NvOdmOsAlloc(sizeof(NvU32) * PCF50626PmuSupply_Num);
+    if (((Pcf50626PrivData*)hDevice->pPrivate)->supplyRefCntTable == NULL)
+    {     
+        NVODMPMU_PRINTF(("Error Allocating RefCntTable. \n"));
+        goto fail;
+    }
+        
+    // memset
+    for (i = 0; i < PCF50626PmuSupply_Num; i++)
+    {
+        ((Pcf50626PrivData*)hDevice->pPrivate)->supplyRefCntTable[i] = 0;
+    }
+
+
+    if (pConnectivity != NULL) // PMU is in database
+    {        
+        for (i = 0; i < pConnectivity->NumAddress; i ++)
+        {
+            if (pConnectivity->AddressList[i].Interface == NvOdmIoModule_I2c_Pmu)
+            {
+                I2cModule   = NvOdmIoModule_I2c_Pmu;
+                I2cInstance = pConnectivity->AddressList[i].Instance;
+                I2cAddress  = pConnectivity->AddressList[i].Address;
+                break;
+            }
+        }
+
+        NV_ASSERT(I2cModule  == NvOdmIoModule_I2c_Pmu);
+        NV_ASSERT(I2cAddress != 0);
+
+        ((Pcf50626PrivData*)hDevice->pPrivate)->hOdmI2C = NvOdmI2cOpen(I2cModule, I2cInstance);
+        if (!((Pcf50626PrivData*)hDevice->pPrivate)->hOdmI2C)
+        {
+            NVODMPMU_PRINTF(("[NVODM PMU]Pcf50626Setup: Error Open I2C device. \n"));     
+            NVODMPMU_PRINTF(("[NVODM PMU]Please check PMU device I2C settings. \n"));  
+            goto fail;        
+        }
+        
+        ((Pcf50626PrivData*)hDevice->pPrivate)->DeviceAddr = I2cAddress;
+        ((Pcf50626PrivData*)hDevice->pPrivate)->hOdmPmuSevice = NvOdmServicesPmuOpen();
+        if (!((Pcf50626PrivData*)hDevice->pPrivate)->hOdmPmuSevice)
+        {
+            NVODMPMU_PRINTF(("[NVODM PMU]Pcf50626Setup: Error Open PMU Odm service. \n"));
+            goto fail;        
+        }
+    }   
+    else
+    {
+        // if PMU is not presented in the database, then the platform is PMU-less.
+        NVODMPMU_PRINTF(("[NVODM PMU]Pcf50626Setup: The system did not doscover PMU fromthe data base. \n"));     
+        NVODMPMU_PRINTF(("[NVODM PMU]Pcf50626Setup: If this is not intended, please check the peripheral database for PMU settings. \n"));     
+        goto fail;
+    }
+    
+    if (!Pcf50626BatteryChargerSetup(hDevice))
+    {
+        NVODMPMU_PRINTF(("[NVODM PMU]Pcf50626Setup: Pcf50626BatteryChargerSetup() failed. \n"));
+        goto fail;
+    }
+
+    //Check battery presence
+    if (!Pcf50626BatteryChargerCBCMainBatt(hDevice,&((Pcf50626PrivData*)hDevice->pPrivate)->battPresence))
+    {
+        NVODMPMU_PRINTF(("[NVODM PMU]Pcf50626Setup: Pcf50626BatteryChargerCBCMainBatt() failed. \n"));
+        goto fail;
+    }
+    
+    // The interrupt assumes not supported until pcf50626InterruptHandler() is called. 
+    ((Pcf50626PrivData*)hDevice->pPrivate)->pmuInterruptSupported = NV_FALSE;
+
+    // setup the interrupt any way.
+    if (!Pcf50626SetupInterrupt(hDevice, &((Pcf50626PrivData*)hDevice->pPrivate)->pmuStatus))
+    {
+        NVODMPMU_PRINTF(("[NVODM PMU]Pcf50626Setup: Pcf50626SetupInterrupt() failed. \n"));
+        goto fail;
+    }
+
+    // Check battery Fullness
+    if (((Pcf50626PrivData*)hDevice->pPrivate)->battPresence == NV_TRUE)
+    {   
+        if (!Pcf50626BatteryChargerCBCBattFul(hDevice,&status))
+        {
+            NVODMPMU_PRINTF(("[NVODM PMU]Pcf50626Setup: Pcf50626BatteryChargerCBCBattFul() failed. \n"));
+            goto fail;
+        }
+
+        ((Pcf50626PrivData*)hDevice->pPrivate)->pmuStatus.batFull = status;
+    }
+    else
+    {
+        ((Pcf50626PrivData*)hDevice->pPrivate)->pmuStatus.batFull = NV_FALSE;
+    }
+
+    return NV_TRUE;
+
+fail:
+    Pcf50626Release(hDevice);
+    return NV_FALSE;
+    
+    
+}
+
+void Pcf50626Release(NvOdmPmuDeviceHandle hDevice)
+{
+    if (hDevice->pPrivate != NULL)
+    {
+        if (((Pcf50626PrivData*)hDevice->pPrivate)->hOdmPmuSevice != NULL)
+        {
+            NvOdmServicesPmuClose(((Pcf50626PrivData*)hDevice->pPrivate)->hOdmPmuSevice);
+            ((Pcf50626PrivData*)hDevice->pPrivate)->hOdmPmuSevice = NULL;
+        }
+        
+        if (((Pcf50626PrivData*)hDevice->pPrivate)->hOdmI2C != NULL)
+        {
+            NvOdmI2cClose(((Pcf50626PrivData*)hDevice->pPrivate)->hOdmI2C);
+            ((Pcf50626PrivData*)hDevice->pPrivate)->hOdmI2C = NULL;
+        }
+
+        if (((Pcf50626PrivData*)hDevice->pPrivate)->supplyRefCntTable != NULL)
+        {
+            NvOdmOsFree(((Pcf50626PrivData*)hDevice->pPrivate)->supplyRefCntTable);
+            ((Pcf50626PrivData*)hDevice->pPrivate)->supplyRefCntTable = NULL;
+        }
+
+        NvOdmOsFree(hDevice->pPrivate);
+        hDevice->pPrivate = NULL;
+    }
+}
+
+
+NvBool
+Pcf50626GetVoltage(
+    NvOdmPmuDeviceHandle hDevice,
+    NvU32 vddRail,
+    NvU32* pMilliVolts)
+{   
+    NV_ASSERT(hDevice);
+    NV_ASSERT(pMilliVolts);
+    NV_ASSERT(vddRail < PCF50626PmuSupply_Num);
+
+    if(! Pcf50626ReadVoltageReg(hDevice, vddRail,pMilliVolts))
+        return NV_FALSE;
+    
+    return NV_TRUE;
+}
+
+
+NvBool
+Pcf50626SetVoltage(
+    NvOdmPmuDeviceHandle hDevice,
+    NvU32 vddRail,
+    NvU32 MilliVolts,
+    NvU32* pSettleMicroSeconds)
+{
+    NvU8 data = 0;
+
+    NV_ASSERT(hDevice);
+    NV_ASSERT(vddRail < PCF50626PmuSupply_Num);
+
+    if (pcf50626SupplyInfoTable[vddRail].cap.OdmProtected == NV_TRUE)
+    {
+        NVODMPMU_PRINTF(("[NVODM PMU] Pcf50626SetVoltage Warning: The voltage is protected and can not be set: %d.\n", vddRail));
+        return NV_TRUE;
+    }
+
+    if ((MilliVolts == ODM_VOLTAGE_OFF) ||
+           ((MilliVolts <= pcf50626SupplyInfoTable[vddRail].cap.MaxMilliVolts)
+           && (MilliVolts >= pcf50626SupplyInfoTable[vddRail].cap.MinMilliVolts)))
+    {
+        if (! Pcf50626WriteVoltageReg(hDevice, vddRail, MilliVolts, pSettleMicroSeconds))
+            return NV_FALSE;
+    }
+    else
+    {
+        NVODMPMU_PRINTF(("[NVODM OPMU] Pcf50626SetVoltage Error: The required voltage is not supported..\n"));
+        return NV_FALSE;
+    }
+
+    if (vddRail == PCF50626PmuSupply_DCUD)
+    {
+        // VBUs rail is enabled bydefault, so no need to enable  set voltage.
+        // "Millivolts"  field is used as Enable or disable VBUS GPIO 
+        if (MilliVolts == ODM_VOLTAGE_OFF) 
+        {
+            data = 0x7; // all bits to low fixed 0
+        }
+        else
+        {
+            data = 0x0; // default reset value high impedence state
+        }
+        if (!Pcf50626I2cWrite8(hDevice,PCF50626_GPIO5C1_ADDR, data))
+            return NV_FALSE;
+    }
+    return NV_TRUE;
+}
+
+static NvBool 
+Pcf50626ReadVoltageReg(
+    NvOdmPmuDeviceHandle hDevice, 
+    NvU32 vddRail, 
+    NvU32* pMilliVolts)
+{
+    NvU32 milliVolts = 0;
+    NvU8 data = 0;
+    const PCF50626PmuSupplyInfo *pSupplyInfo = &pcf50626SupplyInfoTable[vddRail];
+
+    NV_ASSERT(pSupplyInfo->supply == (PCF50626PmuSupply)vddRail);
+
+    if(! Pcf50626I2cRead8(hDevice, pSupplyInfo->control2Addr, &data))
+        return NV_FALSE;
+
+    data >>= PCF50626_C2_OPMOD_SHIFT;
+    if (!data) //OFF
+        milliVolts = 0;
+    else
+    {
+        if (!Pcf50626I2cRead8(hDevice, pSupplyInfo->control1Addr, &data))
+            return NV_FALSE;
+        
+        if ( (vddRail == PCF50626PmuSupply_DCD1) 
+            |(vddRail == PCF50626PmuSupply_DCD2) 
+            |(vddRail == PCF50626PmuSupply_DCUD))
+        {
+            milliVolts = pSupplyInfo->offsetVoltage + pSupplyInfo->cap.StepMilliVolts * ((NvU32)(data & 0x7F));
+        }
+        else if (vddRail == PCF50626PmuSupply_LCREG)
+        {
+            milliVolts = pSupplyInfo->offsetVoltage + pSupplyInfo->cap.StepMilliVolts * ((NvU32)(data & 0x7F) >> 1);    
+        }
+        else
+        {
+            milliVolts = pSupplyInfo->offsetVoltage + pSupplyInfo->cap.StepMilliVolts * ((NvU32)(data & 0x7F) >> 2);    
+        }
+    }
+
+    *pMilliVolts = milliVolts;
+    return NV_TRUE;
+}
+
+
+static NvBool 
+Pcf50626WriteVoltageReg(
+    NvOdmPmuDeviceHandle hDevice, 
+    NvU32 vddRail, 
+    NvU32  MilliVolts, 
+    NvU32* pSettleMicroSeconds)
+{
+    NvU8 data = 0;
+    NvU8 reg = 0;
+    NvU32 settleTime = 0;
+
+    const PCF50626PmuSupplyInfo* pSupplyInfo = &pcf50626SupplyInfoTable[vddRail];
+    const PCF50626PmuSupplyInfo* pSupplyInputInfo = &pcf50626SupplyInfoTable[pSupplyInfo->supplyInput];
+
+    NV_ASSERT(pSupplyInfo->supply == (PCF50626PmuSupply)vddRail);
+
+    // Require to turn off the supply
+    if (MilliVolts == ODM_VOLTAGE_OFF)
+    {
+        // check if the supply can be turned off
+        if (((Pcf50626PrivData*)hDevice->pPrivate)->supplyRefCntTable[pSupplyInfo->supply] == 1)
+        {
+            // turn off the supply
+            data = PCF50626_C2_OPMOD_OFF;
+            NvOdmServicesPmuSetSocRailPowerState(
+                ((Pcf50626PrivData*)hDevice->pPrivate)->hOdmPmuSevice, pSupplyInfo->supply, NV_FALSE); 
+            if (!Pcf50626I2cWrite8(hDevice, pSupplyInfo->control2Addr, data))
+                return NV_FALSE;
+        }
+
+        //check if the supply input can be turned off
+        if (((Pcf50626PrivData*)hDevice->pPrivate)->supplyRefCntTable[pSupplyInputInfo->supply] == 1)
+        {
+            // turn off the supply input
+            data = PCF50626_C2_OPMOD_OFF;
+            NvOdmServicesPmuSetSocRailPowerState(
+                ((Pcf50626PrivData*)hDevice->pPrivate)->hOdmPmuSevice, pSupplyInputInfo->supply, NV_FALSE); 
+            if(! Pcf50626I2cWrite8(hDevice, pSupplyInputInfo->control2Addr, data))
+                return NV_FALSE;
+        }
+
+        if (((Pcf50626PrivData*)hDevice->pPrivate)->supplyRefCntTable[pSupplyInfo->supply] != 0)
+            ((Pcf50626PrivData*)hDevice->pPrivate)->supplyRefCntTable[pSupplyInfo->supply] --;
+        if (((Pcf50626PrivData*)hDevice->pPrivate)->supplyRefCntTable[pSupplyInputInfo->supply] != 0)
+            ((Pcf50626PrivData*)hDevice->pPrivate)->supplyRefCntTable[pSupplyInputInfo->supply] --;
+
+        settleTime = PMU_MAX (pSupplyInfo->switchTimeMicroSec, pSupplyInputInfo->switchTimeMicroSec);
+
+        if (pSettleMicroSeconds != NULL)
+            *pSettleMicroSeconds = settleTime;
+        else
+            NvOdmOsWaitUS(settleTime);
+        return NV_TRUE; 
+    }
+
+    // set voltage
+    if ( (vddRail == PCF50626PmuSupply_HCREG) || 
+         ((vddRail == PCF50626PmuSupply_LCREG) &&
+          (MilliVolts > PCF50626_LCREGOUT_VOLTAGE_RESCHANGE_MV)))
+    {
+        data = (NvU8)((MilliVolts - pSupplyInfo->offsetVoltage) / pSupplyInfo->cap.StepMilliVolts);
+        if (data % 2)
+            data --;
+    }
+    else
+    {
+        data = (NvU8)((MilliVolts - pSupplyInfo->offsetVoltage) / pSupplyInfo->cap.StepMilliVolts);
+    }
+
+    reg = 0;
+    reg &= ~PCF50626_C1_OUTPUT_MASK;
+    if ( (pSupplyInfo->supply == PCF50626PmuSupply_DCD1)
+        |(pSupplyInfo->supply == PCF50626PmuSupply_DCD2)
+        |(pSupplyInfo->supply == PCF50626PmuSupply_DCUD))
+    {
+        reg |= data;
+    }
+    else if (pSupplyInfo->supply == PCF50626PmuSupply_LCREG)
+    {
+        reg |= (data << 1);
+    }   
+    else
+    {
+        reg |= (data << 2);
+    }
+    
+    if(! Pcf50626I2cWrite8(hDevice, pSupplyInfo->control1Addr, reg))
+        return NV_FALSE;
+
+    settleTime = pSupplyInfo->switchTimeMicroSec;
+
+    // turn on supply
+    if (((Pcf50626PrivData*)hDevice->pPrivate)->supplyRefCntTable[pSupplyInfo->supply] == 0)
+    {
+        if (! Pcf50626I2cRead8(hDevice, pSupplyInfo->control2Addr, &data))
+            return NV_FALSE;
+        data >>= PCF50626_C2_OPMOD_SHIFT;
+        if (!data)
+        {
+            // Require to turn on the supply
+            data = PCF50626_C2_OPMOD_ON;
+            NvOdmServicesPmuSetSocRailPowerState(
+                ((Pcf50626PrivData*)hDevice->pPrivate)->hOdmPmuSevice, pSupplyInfo->supply, NV_TRUE); 
+            if(! Pcf50626I2cWrite8(hDevice, pSupplyInfo->control2Addr, data))
+                return NV_FALSE;
+
+            settleTime += pSupplyInfo->turnOnTimeMicroSec;
+        }
+    }
+
+    // turn on supply input if necessary
+    if (((Pcf50626PrivData*)hDevice->pPrivate)->supplyRefCntTable[pSupplyInputInfo->supply] == 0)
+    {
+        if(! Pcf50626I2cRead8(hDevice, pSupplyInputInfo->control2Addr, &data))
+            return NV_FALSE;
+
+        data >>= PCF50626_C2_OPMOD_SHIFT;
+        if (!data)
+        {
+            // Require to turn on the supply input
+            data = PCF50626_C2_OPMOD_ON;
+            NvOdmServicesPmuSetSocRailPowerState(
+                ((Pcf50626PrivData*)hDevice->pPrivate)->hOdmPmuSevice, pSupplyInputInfo->supply, NV_TRUE); 
+            if(! Pcf50626I2cWrite8(hDevice,pSupplyInputInfo->control2Addr, data))
+                return NV_FALSE;
+
+            settleTime += pSupplyInputInfo->turnOnTimeMicroSec;
+       }
+    }
+
+    ((Pcf50626PrivData*)hDevice->pPrivate)->supplyRefCntTable[pSupplyInputInfo->supply] ++;
+    ((Pcf50626PrivData*)hDevice->pPrivate)->supplyRefCntTable[pSupplyInfo->supply] ++;
+
+
+    if (pSettleMicroSeconds != NULL)
+        *pSettleMicroSeconds = settleTime;
+    else
+        NvOdmOsWaitUS(settleTime);
+
+    return NV_TRUE;
+}
+
+NvBool 
+Pcf50626GetAcLineStatus(
+    NvOdmPmuDeviceHandle hDevice, 
+    NvOdmPmuAcLineStatus *pStatus)
+{
+    NvBool acLineStatus = NV_FALSE;
+   
+    NV_ASSERT(hDevice);
+    NV_ASSERT(pStatus);
+   
+    // check if charger presents
+    if (((Pcf50626PrivData*)hDevice->pPrivate)->battPresence == NV_FALSE)
+    {
+        *pStatus = NvOdmPmuAcLine_Online;
+        return NV_TRUE;
+    }
+
+    if (((Pcf50626PrivData*)hDevice->pPrivate)->pmuInterruptSupported == NV_TRUE)
+    {
+        if (( ((Pcf50626PrivData*)hDevice->pPrivate)->pmuStatus.mChgPresent == NV_TRUE ) &&
+            (UsbHostMode == NV_FALSE))
+        {
+            *pStatus = NvOdmPmuAcLine_Online;
+            acLineStatus = NV_TRUE;
+        }
+        else
+        {
+            *pStatus = NvOdmPmuAcLine_Offline;
+            acLineStatus = NV_FALSE;
+        }
+    }
+    else
+    {
+        // battery is present, now check if charger presents
+        if (!Pcf50626BatteryChargerMainChgPresent(hDevice, &acLineStatus))
+        {
+            NVODMPMU_PRINTF(("[NVODM PMU] Pcf50626GetAcLineStatus: Error in checking main charger presence.\n"));
+            return NV_FALSE;
+        }
+
+        if ((acLineStatus == NV_TRUE) && (UsbHostMode == NV_FALSE)) 
+            *pStatus = NvOdmPmuAcLine_Online;
+        else
+            *pStatus = NvOdmPmuAcLine_Offline;
+    }    
+    return NV_TRUE;
+}
+
+
+NvBool 
+Pcf50626GetBatteryStatus(
+    NvOdmPmuDeviceHandle hDevice, 
+    NvOdmPmuBatteryInstance batteryInst,
+    NvU8 *pStatus)
+{
+    NvU8 status = 0;
+    
+    NV_ASSERT(hDevice);
+    NV_ASSERT(pStatus);
+    NV_ASSERT(batteryInst <= NvOdmPmuBatteryInst_Num);
+
+    if (batteryInst == NvOdmPmuBatteryInst_Main)
+    {    
+        if (((Pcf50626PrivData*)hDevice->pPrivate)->battPresence == NV_TRUE)
+        {   
+            NvOdmPmuAcLineStatus stat = NvOdmPmuAcLine_Offline;
+            NvU32 VBatSense = 0;
+            if (!Pcf50626GetAcLineStatus(hDevice, &stat))
+                return NV_FALSE;
+            
+            if (stat == NvOdmPmuAcLine_Online)
+            {
+                if (((Pcf50626PrivData*)hDevice->pPrivate)->pmuInterruptSupported == NV_TRUE)
+                {
+                    if (((Pcf50626PrivData*)hDevice->pPrivate)->pmuStatus.batFull == NV_FALSE)
+                        status = NVODM_BATTERY_STATUS_CHARGING;
+                }
+                else
+                {
+                    NvBool batFull = NV_FALSE;
+                    if (!Pcf50626BatteryChargerCBCBattFul(hDevice, &batFull))
+                        return NV_FALSE;
+                    if (batFull == NV_FALSE)
+                        status = NVODM_BATTERY_STATUS_CHARGING;
+                }
+            }
+            
+            // Get VBatSense
+            if (!Pcf50626AdcVBatSenseRead(hDevice, &VBatSense))
+                return NV_FALSE;
+
+            if (VBatSense > NVODM_BATTERY_HIGH_VOLTAGE_MV)
+                status |= NVODM_BATTERY_STATUS_HIGH;
+            else if ((VBatSense < NVODM_BATTERY_LOW_VOLTAGE_MV)&& 
+                (VBatSense > NVODM_BATTERY_CRITICAL_VOLTAGE_MV))
+                status |= NVODM_BATTERY_STATUS_LOW;
+            else if (VBatSense <= NVODM_BATTERY_CRITICAL_VOLTAGE_MV)
+                status |= NVODM_BATTERY_STATUS_CRITICAL;
+                
+        }
+        else
+        {
+            /* Battery is actually not present */
+            status = NVODM_BATTERY_STATUS_NO_BATTERY;
+        }
+
+        *pStatus = status;
+    }
+    
+    else 
+    {
+        *pStatus = NVODM_BATTERY_STATUS_UNKNOWN;
+    }
+
+    return NV_TRUE;
+}
+
+NvBool
+Pcf50626GetBatteryData(
+    NvOdmPmuDeviceHandle hDevice, 
+    NvOdmPmuBatteryInstance batteryInst,
+    NvOdmPmuBatteryData *pData)
+{
+    NvOdmPmuBatteryData batteryData;
+    batteryData.batteryAverageCurrent  = NVODM_BATTERY_DATA_UNKNOWN;
+    batteryData.batteryAverageInterval = NVODM_BATTERY_DATA_UNKNOWN;
+    batteryData.batteryCurrent         = NVODM_BATTERY_DATA_UNKNOWN;
+    batteryData.batteryLifePercent     = NVODM_BATTERY_DATA_UNKNOWN;
+    batteryData.batteryLifeTime        = NVODM_BATTERY_DATA_UNKNOWN;
+    batteryData.batteryMahConsumed     = NVODM_BATTERY_DATA_UNKNOWN;
+    batteryData.batteryTemperature     = NVODM_BATTERY_DATA_UNKNOWN;
+    batteryData.batteryVoltage         = NVODM_BATTERY_DATA_UNKNOWN;
+
+
+    NV_ASSERT(hDevice);
+    NV_ASSERT(pData);
+    NV_ASSERT(batteryInst <= NvOdmPmuBatteryInst_Num);
+    
+
+    if (batteryInst == NvOdmPmuBatteryInst_Main)
+    {
+        NvU32 VBatSense = 0;
+        NvU32 VBatTemp  = 0;
+
+        if (((Pcf50626PrivData*)hDevice->pPrivate)->battPresence == NV_TRUE)
+        {
+            /* retrieve Battery voltage and temperature */
+            
+            // Get VBatSense
+            if (!Pcf50626AdcVBatSenseRead(hDevice, &VBatSense))
+            {
+                NVODMPMU_PRINTF(("[NVODM PMU] Pcf50626GetBatteryData: Error reading VBATSense. \n"));
+                return NV_FALSE;
+            }
+
+            // Get VBatTemp
+            if (!Pcf50626AdcVBatTempRead(hDevice, &VBatTemp))
+            {
+                NVODMPMU_PRINTF(("[NVODM PMU] Pcf50626GetBatteryData: Error reading VBATSense. \n"));
+                return NV_FALSE;
+            }
+
+            batteryData.batteryLifePercent = 
+                    Pcf50626CalulateBatteryLifePercent_int(VBatSense);     
+
+#if BATTEMP_CONTROL
+            if (!Pcf50626BatteryTemperatureControl_int(hDevice, VBatTemp))
+            {
+                NVODMPMU_PRINTF(("[NVODM PMU] Pcf50626GetBatteryData: Error in battery ctemperature controls. \n"));
+                return NV_FALSE;
+            }
+#endif
+
+            batteryData.batteryVoltage = VBatSense;
+            batteryData.batteryTemperature = Pcf50626BatteryTemperature(VBatSense, 
+                                                                        VBatTemp);
+        }
+        
+        *pData = batteryData;
+    }
+    else
+    {
+        *pData = batteryData;
+    }
+
+    return NV_TRUE;
+}
+
+void
+Pcf50626GetBatteryFullLifeTime(
+    NvOdmPmuDeviceHandle hDevice, 
+    NvOdmPmuBatteryInstance batteryInst,
+    NvU32 *pLifeTime)
+{
+    *pLifeTime = NVODM_BATTERY_DATA_UNKNOWN;
+}
+
+void
+Pcf50626GetBatteryChemistry(
+    NvOdmPmuDeviceHandle hDevice, 
+    NvOdmPmuBatteryInstance batteryInst,
+    NvOdmPmuBatteryChemistry *pChemistry)
+{
+    //return fixed data for now.
+    *pChemistry = NvOdmPmuBatteryChemistry_LION;
+}
+
+NvBool 
+Pcf50626SetChargingCurrent( 
+NvOdmPmuDeviceHandle hDevice, 
+NvOdmPmuChargingPath chargingPath, 
+NvU32 chargingCurrentLimitMa,
+NvOdmUsbChargerType chargerType)
+{
+    NvU8 data = 0;
+    NV_ASSERT(hDevice);
+
+    // if no battery, then do nothing
+    if (((Pcf50626PrivData*)hDevice->pPrivate)->battPresence == NV_FALSE)
+        return NV_TRUE;
+    //Concorde s/w WAR for USB Host mode
+    if (chargingCurrentLimitMa == NVODM_USB_HOST_MODE_LIMIT) 
+    {
+        chargingCurrentLimitMa = 0; // turn off the charging path
+        UsbHostMode = NV_TRUE;
+    }
+    else
+    {
+        UsbHostMode = NV_FALSE;
+    }
+
+    // if requested current is more than max supported current then limit to supported
+    if ( chargingCurrentLimitMa > MAX_CHARGER_LIMIT_MA )
+        chargingCurrentLimitMa = MAX_CHARGER_LIMIT_MA;
+
+    if (chargingPath == NvOdmPmuChargingPath_UsbBus)
+    {
+        switch (chargerType)
+        {
+            case NvOdmUsbChargerType_SJ:
+                chargingCurrentLimitMa = SJ_TYPE_CHARGER_LIMIT_MA;
+                break;
+            case NvOdmUsbChargerType_SK:
+                chargingCurrentLimitMa = SK_TYPE_CHARGER_LIMIT_MA;
+                break;
+            case NvOdmUsbChargerType_SE1:
+                chargingCurrentLimitMa = SE1_TYPE_CHARGER_LIMIT_MA;
+                break;
+            case NvOdmUsbChargerType_SE0:
+                chargingCurrentLimitMa = SE0_TYPE_CHARGER_LIMIT_MA;
+                break;
+            case NvOdmUsbChargerType_UsbHost:
+                default:
+                // USB Host based charging, nothing to do. Just pass current limit to PMU.
+                break;
+        }
+    }
+
+    data = (NvU8)((( chargingCurrentLimitMa << 8 ) - chargingCurrentLimitMa ) 
+                / CHARGER_CONSTANT_CURRENT_SET_MA );
+
+    if (!Pcf50626I2cWrite8(hDevice, PCF50626_CBCC3_ADDR, data))
+        return NV_FALSE;
+
+    // turn off the charger path if the requested current limit is 0mA. Turn on the path otherwise. 
+    data = 0;
+    if ( !Pcf50626I2cRead8(hDevice, PCF50626_CBCC1_ADDR, &data) )
+        return NV_FALSE;
+  
+    if ( chargingCurrentLimitMa == 0 )
+        data &= ~(PCF50626_CBCC1_CHGENA_MASK); //off
+    else
+        data |= PCF50626_CBCC1_CHGENA_MASK;    //on
+
+    if ( !Pcf50626I2cWrite8(hDevice, PCF50626_CBCC1_ADDR, data) )
+        return NV_FALSE;
+
+
+    data = 0;
+    if ( !Pcf50626I2cRead8(hDevice, PCF50626_CBCC2_ADDR, &data) )
+       return NV_FALSE;      
+    if ( chargingCurrentLimitMa == 0 )
+    {
+        //enable USB suspend mode regardless of the SCUSB pin state
+        data |= (PCF50626_CBCC2_SUSPENA_MASK << PCF50626_CBCC2_SUSPENA_SHIFT);
+    }
+    else
+    {
+        //disable USB suspend mode regardless of the SCUSB pin state
+        data &= ~(PCF50626_CBCC2_SUSPENA_MASK << PCF50626_CBCC2_SUSPENA_SHIFT);    
+    }
+    if ( !Pcf50626I2cWrite8(hDevice, PCF50626_CBCC2_ADDR, data) )
+        return NV_FALSE;
+
+    //Dump the register value for debug purpose, can be commented out is undesired..
+    NVODMPMU_PRINTF(("NvOdmPmuSetChargingCurrent: \n"));
+    NVODMPMU_PRINTF(("  chargingCurrentLimitMa:%d\n", chargingCurrentLimitMa));    
+
+    if ( !Pcf50626I2cRead8(hDevice, PCF50626_CBCC1_ADDR, &data) )
+      return NV_FALSE;
+    NVODMPMU_PRINTF(("  CBCC1:0x%02x\n", data));    
+
+    if ( !Pcf50626I2cRead8(hDevice, PCF50626_CBCC2_ADDR, &data) )
+          return NV_FALSE;
+    NVODMPMU_PRINTF(("  CBCC2:0x%02x\n", data));    
+
+    if ( !Pcf50626I2cRead8(hDevice, PCF50626_CBCC3_ADDR, &data) )
+          return NV_FALSE;
+    NVODMPMU_PRINTF(("  CBCC3:0x%02x\n", data));    
+    
+    return NV_TRUE;
+}
+
+void Pcf50626InterruptHandler( NvOdmPmuDeviceHandle  hDevice)
+{
+    // If the interrupt handle is called, the interrupt is supported.
+    ((Pcf50626PrivData*)hDevice->pPrivate)->pmuInterruptSupported = NV_TRUE;
+    
+    Pcf50626InterruptHandler_int(hDevice, &((Pcf50626PrivData*)hDevice->pPrivate)->pmuStatus);
+}
+
+
+static NvU32 Pcf50626CalulateBatteryLifePercent_int(NvU32 vBatSense)
+{
+    NvU32 lifePerc = 0;
+    NvU32 vbat = vBatSense;
+
+    if (vbat < NVODM_BATTERY_CRITICAL_VOLTAGE_MV)
+        vbat = NVODM_BATTERY_CRITICAL_VOLTAGE_MV;
+
+    // using the linear mapping between the battery voltage and the life percentage.
+    lifePerc = ( ( vbat - NVODM_BATTERY_CRITICAL_VOLTAGE_MV ) * 50
+                / ( NVODM_BATTERY_FULL_VOLTAGE_MV - NVODM_BATTERY_CRITICAL_VOLTAGE_MV ) )  << 1;
+
+    if (lifePerc > 100)
+        lifePerc = 100;
+    
+    return lifePerc;
+}
+
+
+#if BATTEMP_CONTROL
+static NvBool Pcf50626BatteryTemperatureControl_int(
+                   NvOdmPmuDeviceHandle hDevice,
+                   NvU32 batTemp)
+{
+    NvU8 data = 0;
+    
+    //turn off the charger if the battery is overheating. 
+    if ( batTemp > NVODM_BATTERY_OVERHEAT_THRESHOLD )  
+    {
+        if (!Pcf50626I2cRead8(hDevice, PCF50626_CBCC1_ADDR, &data))
+            return NV_FALSE;
+
+        data &= 0xFE;
+        if (!Pcf50626I2cWrite8(hDevice, PCF50626_CBCC1_ADDR, data))
+            return NV_FALSE;
+    }
+    // turn it on otherwise
+    else
+    {    
+        if (!Pcf50626I2cRead8(hDevice, PCF50626_CBCC1_ADDR, &data))
+            return NV_FALSE;
+        
+        data |= 0x01;
+        if (!Pcf50626I2cWrite8(hDevice, PCF50626_CBCC1_ADDR, data))
+            return NV_FALSE;
+    }
+
+    return NV_TRUE;
+}
+#endif
+
+
+
diff --git a/arch/arm/mach-tegra/odm_kit/adaptations/pmu/pcf50626/pcf50626.h b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/pcf50626/pcf50626.h
new file mode 100644
index 000000000000..2325fb75a9d2
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/pcf50626/pcf50626.h
@@ -0,0 +1,169 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_PMU_PCF50626_H
+#define INCLUDED_PMU_PCF50626_H
+
+#include "nvodm_pmu.h"
+#include"pmu_hal.h"
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+
+#if (NV_DEBUG)
+#define NVODMPMU_PRINTF(x)   NvOdmOsDebugPrintf x
+#else
+#define NVODMPMU_PRINTF(x)
+#endif
+
+
+typedef struct Pcf50626StatusRec
+{
+    /* Low Battery voltage detected by BVM */
+    NvBool lowBatt;
+
+    /* PMU high temperature */
+    NvBool highTemp;
+
+    /* charger switch from CC mode to CV mode */
+    NvBool chgCcToCv;
+
+    /* Main charger Presents */
+    NvBool mChgPresent;
+
+    /* battery Full */
+    NvBool batFull;
+
+} Pcf50626Status;
+
+
+
+typedef struct
+{
+    /* The handle to the I2C */
+    NvOdmServicesI2cHandle hOdmI2C;
+
+    /* The odm pmu service handle */
+    NvOdmServicesPmuHandle hOdmPmuSevice;
+    
+    /* the PMU I2C device Address */
+    NvU32 DeviceAddr;
+
+    /* the PMU status */
+    Pcf50626Status pmuStatus;
+
+    /* battery presence */
+    NvBool battPresence;
+
+    /* PMU interrupt support enabled */
+    NvBool pmuInterruptSupported;
+
+    
+    /* The ref cnt table of the power supplies */
+    NvU32 *supplyRefCntTable;
+
+}Pcf50626PrivData;
+
+
+NvBool 
+Pcf50626Setup(NvOdmPmuDeviceHandle hDevice);
+
+void 
+Pcf50626Release(NvOdmPmuDeviceHandle hDevice);
+
+NvBool
+Pcf50626GetVoltage(
+    NvOdmPmuDeviceHandle hDevice,
+    NvU32 vddRail,
+    NvU32* pMilliVolts);
+
+NvBool
+Pcf50626SetVoltage(
+    NvOdmPmuDeviceHandle hDevice,
+    NvU32 vddRail,
+    NvU32 MilliVolts,
+    NvU32* pSettleMicroSeconds);
+
+void
+Pcf50626GetCapabilities(
+    NvU32 vddRail,
+    NvOdmPmuVddRailCapabilities* pCapabilities);
+
+
+NvBool 
+Pcf50626GetAcLineStatus(
+    NvOdmPmuDeviceHandle hDevice, 
+    NvOdmPmuAcLineStatus *pStatus);
+
+
+NvBool 
+Pcf50626GetBatteryStatus(
+    NvOdmPmuDeviceHandle hDevice, 
+    NvOdmPmuBatteryInstance batteryInst,
+    NvU8 *pStatus);
+
+NvBool
+Pcf50626GetBatteryData(
+    NvOdmPmuDeviceHandle hDevice, 
+    NvOdmPmuBatteryInstance batteryInst,
+    NvOdmPmuBatteryData *pData);
+
+void
+Pcf50626GetBatteryFullLifeTime(
+    NvOdmPmuDeviceHandle hDevice, 
+    NvOdmPmuBatteryInstance batteryInst,
+    NvU32 *pLifeTime);
+
+void
+Pcf50626GetBatteryChemistry(
+    NvOdmPmuDeviceHandle hDevice, 
+    NvOdmPmuBatteryInstance batteryInst,
+    NvOdmPmuBatteryChemistry *pChemistry);
+
+NvBool 
+Pcf50626SetChargingCurrent( 
+    NvOdmPmuDeviceHandle hDevice, 
+    NvOdmPmuChargingPath chargingPath, 
+    NvU32 chargingCurrentLimitMa,
+    NvOdmUsbChargerType ChargerType); 
+
+void Pcf50626InterruptHandler( NvOdmPmuDeviceHandle  hDevice);
+
+#if defined(__cplusplus)
+}
+#endif
+
+
+#endif // INCLUDED_PMU_PCF50626_H
diff --git a/arch/arm/mach-tegra/odm_kit/adaptations/pmu/pcf50626/pcf50626_adc.c b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/pcf50626/pcf50626_adc.c
new file mode 100644
index 000000000000..95347fa42cd7
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/pcf50626/pcf50626_adc.c
@@ -0,0 +1,196 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include "pcf50626_adc.h"
+#include "pcf50626_i2c.h"
+#include "pcf50626_reg.h"
+//#include "pcf50626_supply_info.h"
+
+#define ADC_CONVERSION_DELAY_USEC      70
+#define ADC_CONVERSION_TIMEOUT_USEC    500
+#define ADC_CONVERSION_VOLTAGE_RANGE   2000
+#define ADC_CONVERSION_DIVIDOR         3
+#define ADC_CONVERSION_PRECISION       10
+#define ADC_CONVERSION_SUB_OFFSET      2250
+
+
+static NvBool 
+Pcf50626AdcIn1Read(NvOdmPmuDeviceHandle hDevice, NvU32 *volt);
+
+static NvBool 
+Pcf50626AdcIn2Read(NvOdmPmuDeviceHandle hDevice, NvU32 *volt);
+
+
+/* read voltage from VBATSENSE */
+NvBool 
+Pcf50626AdcVBatSenseRead(NvOdmPmuDeviceHandle hDevice, NvU32 *volt)
+{
+    return Pcf50626AdcIn1Read(hDevice, volt);
+}
+
+static NvBool 
+Pcf50626AdcIn1Read(NvOdmPmuDeviceHandle hDevice, NvU32 *volt)
+{
+    
+    NvU32 timeout = 0;
+    NvU8  dataS1  = 0;
+    NvU8  dataS3  = 0;
+
+    NV_ASSERT(hDevice);
+    NV_ASSERT(volt);
+
+    // Turn off GPIO7
+    if(! Pcf50626I2cWrite8(hDevice, PCF50626_GPIO7C1_ADDR, 0x0))
+        return NV_FALSE;
+
+
+    //ADCC3 - Division sel    
+    if(! Pcf50626I2cWrite8(hDevice, PCF50626_ADCC3_ADDR, PCF50626_ADCC3_RESET))
+        return NV_FALSE;
+
+
+    //ADCC1 -  Resolustion, Mux Sel, Avg sel
+    if(! Pcf50626I2cWrite8(hDevice, PCF50626_ADCC1_ADDR, 0x0C))
+        return NV_FALSE;
+
+    // Start Converstion
+    if(! Pcf50626I2cWrite8(hDevice, PCF50626_ADCC1_ADDR, 0x0D))
+        return NV_FALSE;          
+
+    // Wait for conversion
+    NvOdmOsWaitUS(ADC_CONVERSION_DELAY_USEC);
+
+    // make sure the conversion is completed, or timeout.
+    while (timeout < ADC_CONVERSION_TIMEOUT_USEC)
+    {
+        if(! Pcf50626I2cRead8(hDevice, PCF50626_ADCS3_ADDR, &dataS3))
+            return NV_FALSE;
+
+        if (dataS3 & 0x80)
+            break;
+
+        NvOdmOsWaitUS(ADC_CONVERSION_DELAY_USEC);        
+        timeout += ADC_CONVERSION_DELAY_USEC;
+    }
+
+    if (timeout >= ADC_CONVERSION_TIMEOUT_USEC)
+    {
+        NVODMPMU_PRINTF(("ADC conversion timeout.\n"));
+        return NV_FALSE;
+    }
+
+    // read the conversion result
+    if (!Pcf50626I2cRead8(hDevice, PCF50626_ADCS1_ADDR, &dataS1)) 
+        return NV_FALSE;
+
+    // Get result
+    *volt = (((NvU32)((dataS1 << 2) | (dataS3 & 0x03))) * 
+            ADC_CONVERSION_VOLTAGE_RANGE * ADC_CONVERSION_DIVIDOR) 
+            >> ADC_CONVERSION_PRECISION; 
+
+    return NV_TRUE;
+}
+
+
+
+/* read bat temperature voltage from ADC2 */
+NvBool 
+Pcf50626AdcVBatTempRead(NvOdmPmuDeviceHandle hDevice, NvU32 *volt)
+{
+    return Pcf50626AdcIn2Read(hDevice, volt);
+}
+
+static NvBool 
+Pcf50626AdcIn2Read(NvOdmPmuDeviceHandle hDevice, NvU32 *volt)
+{
+    NvU32 timeout = 0;
+    NvU8  dataS1  = 0;
+    NvU8  dataS3  = 0;
+
+    NV_ASSERT(hDevice);
+    NV_ASSERT(volt);
+
+    // Turn off GPIO7
+    if(! Pcf50626I2cWrite8(hDevice, PCF50626_GPIO7C1_ADDR, 0x0))
+        return NV_FALSE;
+
+
+    //ADCC3 - Division sel    
+    if(! Pcf50626I2cWrite8(hDevice, PCF50626_ADCC3_ADDR, PCF50626_ADCC3_RESET))
+        return NV_FALSE;
+
+
+    //ADCC1 -  Resolustion, Mux Sel, Avg sel
+    if(! Pcf50626I2cWrite8(hDevice, PCF50626_ADCC1_ADDR, 0x2C))
+        return NV_FALSE;
+
+    // Start Converstion
+    if(! Pcf50626I2cWrite8(hDevice, PCF50626_ADCC1_ADDR, 0x2D))
+        return NV_FALSE;          
+
+    // Wait for conversion
+    NvOdmOsWaitUS(ADC_CONVERSION_DELAY_USEC);
+
+    // make sure the conversion is completed, or timeout.
+    while (timeout < ADC_CONVERSION_TIMEOUT_USEC)
+    {
+        if(! Pcf50626I2cRead8(hDevice, PCF50626_ADCS3_ADDR, &dataS3))
+            return NV_FALSE;
+
+        if (dataS3 & 0x80)
+            break;
+
+        NvOdmOsWaitUS(ADC_CONVERSION_DELAY_USEC);        
+        timeout += ADC_CONVERSION_DELAY_USEC;
+    }
+
+    if (timeout >= ADC_CONVERSION_TIMEOUT_USEC)
+    {
+        NVODMPMU_PRINTF(("ADC conversion timeout.\n"));
+        return NV_FALSE;
+    }
+
+    // read the conversion result
+    if (!Pcf50626I2cRead8(hDevice, PCF50626_ADCS1_ADDR, &dataS1)) 
+        return NV_FALSE;
+
+    // Get result
+    *volt = (((NvU32)((dataS1 << 2) | (dataS3 & 0x03))) * 
+            ADC_CONVERSION_VOLTAGE_RANGE * ADC_CONVERSION_DIVIDOR) 
+            >> ADC_CONVERSION_PRECISION; 
+
+    return NV_TRUE;
+}
+
+
+
+
diff --git a/arch/arm/mach-tegra/odm_kit/adaptations/pmu/pcf50626/pcf50626_adc.h b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/pcf50626/pcf50626_adc.h
new file mode 100644
index 000000000000..e5022c449289
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/pcf50626/pcf50626_adc.h
@@ -0,0 +1,71 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_PCF50626_ADC_HEADER
+#define INCLUDED_PCF50626_ADC_HEADER
+
+
+/* the ADC is used for battery voltage conversion */
+#include "pcf50626.h"
+
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+/* read voltage from VBATSENSE */
+
+NvBool 
+Pcf50626AdcVBatSenseRead(
+    NvOdmPmuDeviceHandle hDevice, 
+    NvU32 *volt);
+
+
+/* read bat temperature voltage from ADC2 */
+NvBool 
+Pcf50626AdcVBatTempRead(
+    NvOdmPmuDeviceHandle hDevice, 
+    NvU32 *volt);
+
+/* Calculate the battery temperature */
+NvU32 Pcf50626BatteryTemperature(
+    NvU32 VBatSense, 
+    NvU32 VBatTemp);
+
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif // INCLUDED_PCF50626_ADC_HEADER
+
diff --git a/arch/arm/mach-tegra/odm_kit/adaptations/pmu/pcf50626/pcf50626_batterycharger.c b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/pcf50626/pcf50626_batterycharger.c
new file mode 100644
index 000000000000..814d12319dd5
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/pcf50626/pcf50626_batterycharger.c
@@ -0,0 +1,257 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include "pcf50626_batterycharger.h"
+#include "pcf50626_adc.h"
+#include "pcf50626_i2c.h"
+#include "pcf50626_reg.h"
+
+
+/* Get battery Voltage */
+NvBool 
+Pcf50626BatteryChargerGetVoltage(NvOdmPmuDeviceHandle hDevice, NvU32 *res)
+{
+    NvU32 volt = 0;
+    ///TODO: check on HW to see the relation between adc output and the voltage. for now, assume they are the same.
+    if(! Pcf50626AdcVBatSenseRead(hDevice,&volt))
+        return NV_FALSE;
+
+    *res = volt;
+    return NV_TRUE; 
+}
+
+
+
+/* check OnKey Level */
+NvBool
+Pcf50626BatteryChargerOnKeyStatus(NvOdmPmuDeviceHandle hDevice, NvBool *status)
+{
+    NvU8 data = 0;
+    
+    if(! Pcf50626I2cRead8(hDevice, PCF50626_OOCS_ADDR, &data))
+        return NV_FALSE
+        ;
+    data = (data >> PCF50626_OOCS_ONKEY_SHIFT) & PCF50626_OOCS_ONKEY_MASK;
+    *status = (data == 0 ? NV_FALSE : NV_TRUE ); 
+
+    return NV_TRUE;
+}
+
+/* check OnKey Level */
+NvBool
+Pcf50626BatteryChargerRec1Status(NvOdmPmuDeviceHandle hDevice, NvBool *status)
+{
+    NvU8 data = 0;
+    
+    if(! Pcf50626I2cRead8(hDevice, PCF50626_OOCS_ADDR, &data))
+        return NV_FALSE;
+    data = (data >> PCF50626_OOCS_REC1_SHIFT) & PCF50626_OOCS_REC1_MASK;
+    *status = (data == 0 ? NV_FALSE : NV_TRUE ); 
+
+    return NV_TRUE;
+}
+
+/* check battery status */
+NvBool
+Pcf50626BatteryChargerBattStatus(NvOdmPmuDeviceHandle hDevice, NvBool *status)
+{
+    NvU8 data = 0;
+    
+    if(! Pcf50626I2cRead8(hDevice, PCF50626_OOCS_ADDR, &data))
+        return NV_FALSE;
+    data = (data >> PCF50626_OOCS_BATOK_SHIFT) & PCF50626_OOCS_BATOK_MASK;
+    *status = (data == 0 ? NV_FALSE : NV_TRUE ); 
+
+    return NV_TRUE;
+}
+
+/* check main charger status */
+NvBool
+Pcf50626BatteryChargerMainChgPresent(NvOdmPmuDeviceHandle hDevice, NvBool *status)
+{
+    NvU8 data = 0;
+    
+    if(! Pcf50626I2cRead8(hDevice, PCF50626_OOCS_ADDR, &data))
+        return NV_FALSE;
+
+    data = (data >> PCF50626_OOCS_MCHGOK_SHIFT) & PCF50626_OOCS_MCHGOK_MASK;
+    *status = (data == 0 ? NV_FALSE : NV_TRUE ); 
+    return NV_TRUE;
+}
+
+
+/* check USB charger status */
+NvBool
+Pcf50626BatteryChargerUsbChgPresent(NvOdmPmuDeviceHandle hDevice, NvBool *status)
+{
+    NvU8 data = 0;
+    
+    if(! Pcf50626I2cRead8(hDevice, PCF50626_OOCS_ADDR, &data))
+        return NV_FALSE;
+
+    data = (data >> PCF50626_OOCS_UCHGOK_SHIFT) & PCF50626_OOCS_UCHGOK_MASK;
+    *status = (data == 0 ? NV_FALSE : NV_TRUE ); 
+    return NV_TRUE;
+}
+
+
+/* check temparature status */
+NvBool
+Pcf50626BatteryChargerTempStatus(NvOdmPmuDeviceHandle hDevice, NvBool *status)
+{
+    NvU8 data = 0;
+    
+    if(! Pcf50626I2cRead8(hDevice, PCF50626_OOCS_ADDR, &data))
+        return NV_FALSE;
+
+    data = (data >> PCF50626_OOCS_TEMPOK_SHIFT) & PCF50626_OOCS_TEMPOK_MASK;
+    *status = (data == 0 ? NV_FALSE : NV_TRUE ); 
+    return NV_TRUE;
+}
+
+/* check CBC batt_ful status */
+NvBool
+Pcf50626BatteryChargerCBCBattFul(NvOdmPmuDeviceHandle hDevice, NvBool *status)
+{
+    NvU8 data = 0;
+    
+    if(! Pcf50626I2cRead8(hDevice, PCF50626_CBCS1_ADDR, &data))
+        return NV_FALSE;
+
+    data = (data >> PCF50626_CBCS1_BATTFUL_SHIFT) & PCF50626_CBCS1_BATTFUL_MASK;
+    *status = (data == 0 ? NV_FALSE : NV_TRUE ); 
+    return NV_TRUE;
+}
+
+
+/* check CBC thermal limit activation status */
+NvBool
+Pcf50626BatteryChargerCBCTlimStatus(NvOdmPmuDeviceHandle hDevice, NvBool *status)
+{
+    NvU8 data = 0;
+    
+    if(! Pcf50626I2cRead8(hDevice, PCF50626_CBCS1_ADDR, &data))
+        return NV_FALSE;
+
+    data = (data >> PCF50626_CBCS1_TLIMIT_SHIFT) & PCF50626_CBCS1_TLIMIT_MASK;
+    *status = (data == 0 ? NV_FALSE : NV_TRUE ); 
+    return NV_TRUE;
+}
+
+/* check CBC batt_ful status */
+NvBool
+Pcf50626BatteryChargerCBCWdExpired(NvOdmPmuDeviceHandle hDevice, NvBool *status)
+{
+    NvU8 data = 0;
+    
+    if(! Pcf50626I2cRead8(hDevice, PCF50626_CBCS1_ADDR, &data))
+        return NV_FALSE;
+
+    data = (data >> PCF50626_CBCS1_WDEXP_SHIFT) & PCF50626_CBCS1_WDEXP_MASK;
+    *status = (data == 0 ? NV_FALSE : NV_TRUE ); 
+    return NV_TRUE;
+}
+
+
+/* check CBC charger current status */
+NvBool
+Pcf50626BatteryChargerCBCChgCurStatus(NvOdmPmuDeviceHandle hDevice, NvBool *status)
+{
+    NvU8 data = 0;
+    
+    if(! Pcf50626I2cRead8(hDevice, PCF50626_CBCS1_ADDR, &data))
+        return NV_FALSE;
+
+    data = (data >> PCF50626_CBCS1_ILIMIT_SHIFT) & PCF50626_CBCS1_ILIMIT_MASK;
+    *status = (data == 0 ? NV_FALSE : NV_TRUE ); 
+    return NV_TRUE;
+}
+
+/* check CBC charger voltage status */
+NvBool
+Pcf50626BatteryChargerCBCChgVoltStatus(NvOdmPmuDeviceHandle hDevice, NvBool *status)
+{
+    NvU8 data = 0;
+    
+    if(! Pcf50626I2cRead8(hDevice, PCF50626_CBCS1_ADDR, &data))
+        return NV_FALSE;
+
+    data = (data >> PCF50626_CBCS1_VLIMIT_SHIFT) & PCF50626_CBCS1_VLIMIT_MASK;
+    *status = (data == 0 ? NV_FALSE : NV_TRUE ); 
+    return NV_TRUE;
+}
+
+/* check CBC charger resume status */
+NvBool
+Pcf50626BatteryChargerCBCChgResStatus(NvOdmPmuDeviceHandle hDevice, NvBool *status)
+{
+    NvU8 data = 0;
+    
+    if(! Pcf50626I2cRead8(hDevice, PCF50626_CBCS1_ADDR, &data))
+        return NV_FALSE;
+
+    data = (data >> PCF50626_CBCS1_RESSTAT_SHIFT) & PCF50626_CBCS1_RESSTAT_MASK;
+    *status = (data == 0 ? NV_FALSE : NV_TRUE ); 
+    return NV_TRUE;
+}
+
+
+/* check USB suspend status */
+NvBool
+Pcf50626BatteryChargerCBCUsbSuspStat(NvOdmPmuDeviceHandle hDevice, NvBool *status)
+{
+    NvU8 data = 0;
+    
+    if(! Pcf50626I2cRead8(hDevice, PCF50626_CBCS2_ADDR, &data))
+        return NV_FALSE;
+
+    data = (data >> PCF50626_CBCS2_USBSUSPSTAT_SHIFT) & PCF50626_CBCS2_USBSUSPSTAT_MASK;
+    *status = (data == 0 ? NV_FALSE : NV_TRUE ); 
+    return NV_TRUE;
+}
+
+/* check charger over-voltage protection status */
+NvBool
+Pcf50626BatteryChargerCBCChgOvpStat(NvOdmPmuDeviceHandle hDevice, NvBool *status)
+{
+    NvU8 data = 0;
+    
+    if(! Pcf50626I2cRead8(hDevice, PCF50626_CBCS2_ADDR, &data))
+        return NV_FALSE;
+
+    data = (data >> PCF50626_CBCS2_CHGOVP_SHIFT) & PCF50626_CBCS2_CHGOVP_MASK;
+    *status = (data == 0 ? NV_FALSE : NV_TRUE ); 
+    return NV_TRUE;
+}
+
+
+
diff --git a/arch/arm/mach-tegra/odm_kit/adaptations/pmu/pcf50626/pcf50626_batterycharger.h b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/pcf50626/pcf50626_batterycharger.h
new file mode 100644
index 000000000000..ad5ebbc9f344
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/pcf50626/pcf50626_batterycharger.h
@@ -0,0 +1,158 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_PCF50626_BATTERYCHARGER_HEADER
+#define INCLUDED_PCF50626_BATTERYCHARGER_HEADER
+
+
+
+#include "pcf50626.h"
+
+/* the battery charger functions */
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+/* Initliase all registers that related to battery charger */
+NvBool 
+Pcf50626BatteryChargerSetup(NvOdmPmuDeviceHandle hDevice);
+
+/* Get battery Voltage */
+NvBool 
+Pcf50626BatteryChargerGetVoltage(
+    NvOdmPmuDeviceHandle hDevice, 
+    NvU32 *res);
+
+
+/* check OnKey level */
+NvBool
+Pcf50626BatteryChargerOnKeyStatus(
+     NvOdmPmuDeviceHandle hDevice, 
+     NvBool *status);
+
+/* check rec1 level */
+NvBool
+Pcf50626BatteryChargerRec1Status(
+    NvOdmPmuDeviceHandle hDevice, 
+    NvBool *status);
+
+/* check battery status */
+NvBool
+Pcf50626BatteryChargerBattStatus(
+    NvOdmPmuDeviceHandle hDevice, 
+    NvBool *status);
+
+/* check main charger status */
+NvBool
+Pcf50626BatteryChargerMainChgPresent(
+     NvOdmPmuDeviceHandle hDevice, 
+     NvBool *status);
+
+/* check USB charger status */
+NvBool
+Pcf50626BatteryChargerUsbChgPresent(
+     NvOdmPmuDeviceHandle hDevice, 
+     NvBool *status);
+
+/* check temparature status */
+NvBool
+Pcf50626BatteryChargerTempStatus(
+     NvOdmPmuDeviceHandle hDevice, 
+     NvBool *status);
+
+
+/* check CBC batt_ful status */
+NvBool
+Pcf50626BatteryChargerCBCBattFul(
+    NvOdmPmuDeviceHandle hDevice, 
+    NvBool *status);
+
+
+
+/* check CBC thermal limit activation status */
+NvBool
+Pcf50626BatteryChargerCBCTlimStatus(
+    NvOdmPmuDeviceHandle hDevice, 
+    NvBool *status);
+
+/* check CBC batt_ful status */
+NvBool
+Pcf50626BatteryChargerCBCWdExpired(
+    NvOdmPmuDeviceHandle hDevice, 
+    NvBool *status);
+
+
+/* check CBC charger current status */
+NvBool
+Pcf50626BatteryChargerCBCChgCurStatus(
+    NvOdmPmuDeviceHandle hDevice, 
+    NvBool *status);
+
+/* check CBC charger voltage status */
+NvBool
+Pcf50626BatteryChargerCBCChgVoltStatus(
+    NvOdmPmuDeviceHandle hDevice, 
+    NvBool *status);
+
+/* check CBC charger resume status */
+NvBool
+Pcf50626BatteryChargerCBCChgResStatus(
+    NvOdmPmuDeviceHandle hDevice, 
+    NvBool *status);
+
+/* check CBC main batt presence */
+NvBool
+Pcf50626BatteryChargerCBCMainBatt(
+    NvOdmPmuDeviceHandle hDevice, 
+    NvBool *status);
+
+/* check USB suspend status */
+NvBool
+Pcf50626BatteryChargerCBCUsbSuspStat(
+    NvOdmPmuDeviceHandle hDevice, 
+    NvBool *status);
+
+/* check charger over-voltage protection status */
+NvBool
+Pcf50626BatteryChargerCBCChgOvpStat(
+    NvOdmPmuDeviceHandle hDevice, 
+    NvBool *status);
+
+
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif // INCLUDED_PCF50626_BATTERYCHARGER_HEADER
+
diff --git a/arch/arm/mach-tegra/odm_kit/adaptations/pmu/pcf50626/pcf50626_i2c.c b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/pcf50626/pcf50626_i2c.c
new file mode 100644
index 000000000000..38990b3ffada
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/pcf50626/pcf50626_i2c.c
@@ -0,0 +1,209 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include "pcf50626_i2c.h"
+#include "nvodm_pmu.h"
+#include "nvodm_services.h"
+
+
+NvBool Pcf50626I2cWrite8(
+    NvOdmPmuDeviceHandle hDevice,
+    NvU8 Addr,
+    NvU8 Data)
+{  
+    NvU8 WriteBuffer[2];
+    NvOdmI2cTransactionInfo TransactionInfo;
+    NvOdmI2cStatus status  = NvOdmI2cStatus_Success;    
+    Pcf50626PrivData *hPmu = (Pcf50626PrivData*)hDevice->pPrivate;
+        
+    WriteBuffer[0] = Addr & 0xFF;   // PMU offset
+    WriteBuffer[1] = Data & 0xFF;   // written data
+
+    TransactionInfo.Address = hPmu->DeviceAddr;
+    TransactionInfo.Buf = &WriteBuffer[0];
+    TransactionInfo.Flags = NVODM_I2C_IS_WRITE;
+    TransactionInfo.NumBytes = 2;
+
+    status = NvOdmI2cTransaction(hPmu->hOdmI2C, &TransactionInfo, 1, 
+                        PCF506226_I2C_SPEED_KHZ, NV_WAIT_INFINITE);
+    if (status == NvOdmI2cStatus_Success)
+    {
+        return NV_TRUE;
+    }
+    else
+    {
+        switch (status)
+        {
+            case NvOdmI2cStatus_Timeout:
+                NVODMPMU_PRINTF(("NvOdmPmuI2cWrite8 Failed: Timeout\n")); 
+                break;
+             case NvOdmI2cStatus_SlaveNotFound:
+             default:
+                NVODMPMU_PRINTF(("NvOdmPmuI2cWrite8 Failed: SlaveNotFound\n"));
+                break;             
+        }
+        return NV_FALSE;
+    }    
+}
+
+NvBool Pcf50626I2cRead8(
+    NvOdmPmuDeviceHandle hDevice,
+    NvU8 Addr,
+    NvU8 *Data)
+{
+    NvU8 ReadBuffer = 0;
+    NvOdmI2cStatus  status = NvOdmI2cStatus_Success;    
+    Pcf50626PrivData *hPmu = (Pcf50626PrivData*)hDevice->pPrivate;
+    NvOdmI2cTransactionInfo TransactionInfo[2];
+
+    // Write the PMU offset
+    ReadBuffer = Addr & 0xFF;
+
+    TransactionInfo[0].Address = hPmu->DeviceAddr;
+    TransactionInfo[0].Buf = &ReadBuffer;
+    TransactionInfo[0].Flags = NVODM_I2C_IS_WRITE;
+    TransactionInfo[0].NumBytes = 1;    
+    TransactionInfo[1].Address = (hPmu->DeviceAddr | 0x1);
+    TransactionInfo[1].Buf = &ReadBuffer;
+    TransactionInfo[1].Flags = 0;
+    TransactionInfo[1].NumBytes = 1;
+
+    // Read data from PMU at the specified offset
+    status = NvOdmI2cTransaction(hPmu->hOdmI2C, &TransactionInfo[0], 2, 
+                                    PCF506226_I2C_SPEED_KHZ, NV_WAIT_INFINITE);
+    if (status != NvOdmI2cStatus_Success)
+    {
+        switch (status)
+        {
+            case NvOdmI2cStatus_Timeout:
+                NVODMPMU_PRINTF(("NvOdmPmuI2cRead8 Failed: Timeout\n")); 
+                break;
+             case NvOdmI2cStatus_SlaveNotFound:
+             default:
+                NVODMPMU_PRINTF(("NvOdmPmuI2cRead8 Failed: SlaveNotFound\n"));
+                break;             
+        }
+        return NV_FALSE;
+    }  
+
+    *Data = ReadBuffer;
+    return NV_TRUE;
+}
+
+NvBool Pcf50626I2cWrite32(
+    NvOdmPmuDeviceHandle hDevice,
+    NvU8 Addr,
+    NvU32 Data)
+{
+    NvU8 WriteBuffer[5];
+    NvOdmI2cStatus  status = NvOdmI2cStatus_Success;    
+    Pcf50626PrivData *hPmu = (Pcf50626PrivData*)hDevice->pPrivate;
+    NvOdmI2cTransactionInfo TransactionInfo;
+
+    WriteBuffer[0] = (NvU8)(Addr & 0xFF);  
+    WriteBuffer[1] = (NvU8)((Data >> 24) & 0xFF);
+    WriteBuffer[2] = (NvU8)((Data >> 16) & 0xFF);
+    WriteBuffer[3] = (NvU8)((Data >>  8) & 0xFF);
+    WriteBuffer[4] = (NvU8)(Data & 0xFF);
+
+    TransactionInfo.Address = hPmu->DeviceAddr;
+    TransactionInfo.Buf = &WriteBuffer[0];
+    TransactionInfo.Flags = NVODM_I2C_IS_WRITE;
+    TransactionInfo.NumBytes = 5;
+
+    status = NvOdmI2cTransaction(hPmu->hOdmI2C, &TransactionInfo, 1,
+                                        PCF506226_I2C_SPEED_KHZ, NV_WAIT_INFINITE);
+    if (status != NvOdmI2cStatus_Success)
+    {
+        switch (status)
+        {
+            case NvOdmI2cStatus_Timeout:
+                NVODMPMU_PRINTF(("NvOdmPmuI2cWrite32 Failed: Timeout\n")); 
+                break;
+             case NvOdmI2cStatus_SlaveNotFound:
+             default:
+                NVODMPMU_PRINTF(("NvOdmPmuI2cWrite32 Failed: SlaveNotFound\n"));
+                break;             
+        }
+        return NV_FALSE;
+    }
+
+    return NV_TRUE;
+}
+
+NvBool Pcf50626I2cRead32(
+   NvOdmPmuDeviceHandle hDevice,
+   NvU8 Addr,
+   NvU32 *Data)
+{
+    NvU8 ReadBuffer[5];
+    NvOdmI2cStatus  status = NvOdmI2cStatus_Success;    
+    Pcf50626PrivData *hPmu = (Pcf50626PrivData*)hDevice->pPrivate;
+    NvOdmI2cTransactionInfo TransactionInfo[2];
+
+
+    ReadBuffer[0] = Addr & 0xFF;
+
+    TransactionInfo[0].Address = hPmu->DeviceAddr;
+    TransactionInfo[0].Buf = &ReadBuffer[0];
+    TransactionInfo[0].Flags = NVODM_I2C_IS_WRITE;
+    TransactionInfo[0].NumBytes = 1;
+
+    TransactionInfo[1].Address = (hPmu->DeviceAddr | 0x1);
+    TransactionInfo[1].Buf = &ReadBuffer[0];
+    TransactionInfo[1].Flags = 0;
+    TransactionInfo[1].NumBytes = 4;
+
+    status = NvOdmI2cTransaction(hPmu->hOdmI2C, &TransactionInfo[0], 2,
+                                        PCF506226_I2C_SPEED_KHZ, NV_WAIT_INFINITE);
+    if (status != NvOdmI2cStatus_Success)
+    {
+        switch (status)
+        {
+            case NvOdmI2cStatus_Timeout:
+                NVODMPMU_PRINTF(("NvOdmPmuI2cRead32 Failed: Timeout\n")); 
+                break;
+             case NvOdmI2cStatus_SlaveNotFound:
+             default:
+                NVODMPMU_PRINTF(("NvOdmPmuI2cRead32 Failed: SlaveNotFound\n"));
+                break;             
+        }
+        return NV_FALSE;
+    }
+
+    *Data = (ReadBuffer[0] << 24) | (ReadBuffer[1] << 16) | 
+            (ReadBuffer[2] << 8) | ReadBuffer[3];
+
+    return NV_TRUE;
+}
+
+
diff --git a/arch/arm/mach-tegra/odm_kit/adaptations/pmu/pcf50626/pcf50626_i2c.h b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/pcf50626/pcf50626_i2c.h
new file mode 100644
index 000000000000..bc4b5aead9c8
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/pcf50626/pcf50626_i2c.h
@@ -0,0 +1,76 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_NVODM_PMU_PCF50626_I2C_H
+#define INCLUDED_NVODM_PMU_PCF50626_I2C_H
+
+#include "pcf50626.h"
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+// Constant definition
+#define PMU_PCF50626_DEVADDR      0xE0
+#define PCF506226_I2C_SPEED_KHZ   400
+
+// Function declaration
+NvBool Pcf50626I2cWrite8(
+   NvOdmPmuDeviceHandle hDevice,
+   NvU8 Addr,
+   NvU8 Data);
+
+NvBool Pcf50626I2cRead8(
+   NvOdmPmuDeviceHandle hDevice,
+   NvU8 Addr,
+   NvU8 *Data);
+
+NvBool Pcf50626I2cWrite32(
+   NvOdmPmuDeviceHandle hDevice,
+   NvU8 Addr,
+   NvU32 Data);
+
+NvBool Pcf50626I2cRead32(
+   NvOdmPmuDeviceHandle hDevice,
+   NvU8 Addr,
+   NvU32 *Data);
+
+
+
+#if defined(__cplusplus)
+}
+#endif
+
+/** @} */
+
+#endif // INCLUDED_NVODM_PMU_PCF50626_I2C_H
diff --git a/arch/arm/mach-tegra/odm_kit/adaptations/pmu/pcf50626/pcf50626_interrupt.c b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/pcf50626/pcf50626_interrupt.c
new file mode 100644
index 000000000000..da9c4b605976
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/pcf50626/pcf50626_interrupt.c
@@ -0,0 +1,167 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+
+#include "pcf50626_interrupt.h"
+#include "pcf50626_batterycharger.h"
+#include "pcf50626_i2c.h"
+#include "pcf50626_reg.h"
+#include "nvodm_services.h"
+
+NvBool Pcf50626SetupInterrupt(NvOdmPmuDeviceHandle  hDevice,
+                                  Pcf50626Status *pmuStatus)
+{
+    NvBool status = NV_FALSE;
+    NvU8   data   = 0;
+
+    NV_ASSERT(hDevice);
+    NV_ASSERT(pmuStatus);
+
+    /* Init Pmu Status */
+    pmuStatus->lowBatt       = NV_FALSE;
+    pmuStatus->highTemp      = NV_FALSE;
+    pmuStatus->chgCcToCv     = NV_FALSE;
+
+    if (!Pcf50626BatteryChargerMainChgPresent(hDevice,&status))
+        return NV_FALSE;
+    pmuStatus->mChgPresent = status;
+
+
+    /* Set up Interrupt Mask */
+    data = (NvU8) ~(PCF50626_INT1_LOWBATT | PCF50626_INT1_HIGHTEMP);
+    if(! Pcf50626I2cWrite8(hDevice, PCF50626_INT1M_ADDR, data ))
+        return NV_FALSE;
+
+    data = 0;
+    data = (NvU8) ~PCF50626_INT2_VMAX;
+    if(! Pcf50626I2cWrite8(hDevice, PCF50626_INT2M_ADDR, data ))
+        return NV_FALSE;
+
+    data = 0;
+    data = (NvU8) ~(PCF50626_INT3_MCHGINS | PCF50626_INT3_MCHGRM);
+    if(! Pcf50626I2cWrite8(hDevice, PCF50626_INT3M_ADDR, data ))
+        return NV_FALSE;
+
+    data = 0;
+    data = (NvU8) ~(PCF50626_INT4_BATFUL | PCF50626_INT4_CHGRES);
+    if(! Pcf50626I2cWrite8(hDevice, PCF50626_INT4M_ADDR, data ))
+        return NV_FALSE;
+
+    //if(! Pcf50626I2cWrite8(hDevice, PCF50626_INT5M_ADDR, 0xff))
+    //    return NV_FALSE;
+
+    //if(! Pcf50626I2cWrite8(hDevice, PCF50626_INT6M_ADDR, 0xff))
+    //    return NV_FALSE;
+
+    //if(! Pcf50626I2cWrite8(hDevice, PCF50626_INT7M_ADDR, 0xff))
+    //    return NV_FALSE;
+
+    return NV_TRUE;
+}
+
+void Pcf50626InterruptHandler_int(NvOdmPmuDeviceHandle  hDevice,
+                                  Pcf50626Status *pmuStatus)
+{
+
+    NvU8 data = 0;
+
+    NV_ASSERT(hDevice);
+    NV_ASSERT(pmuStatus);
+
+    // INT1
+    if (!Pcf50626I2cRead8(hDevice, PCF50626_INT1_ADDR, &data))
+    {
+        NVODMPMU_PRINTF(("Error reading INT1"));
+        return;
+    }
+    if (data != 0)
+    {
+        if (data & PCF50626_INT1_HIGHTEMP)
+            pmuStatus->highTemp = NV_TRUE;
+        else
+            pmuStatus->highTemp = NV_FALSE;
+        if (data & PCF50626_INT1_LOWBATT)
+            pmuStatus->lowBatt = NV_TRUE;
+        else
+            pmuStatus->lowBatt = NV_FALSE;
+    }
+
+    // INT2
+    if (!Pcf50626I2cRead8(hDevice, PCF50626_INT2_ADDR, &data))
+    {
+        NVODMPMU_PRINTF(("Error reading INT2"));
+        return;
+    }
+    if (data != 0)
+    {
+        if (data & PCF50626_INT2_VMAX)
+            pmuStatus->chgCcToCv = NV_TRUE;
+        else
+            pmuStatus->chgCcToCv = NV_FALSE;
+    }
+
+    // INT3
+    if (!Pcf50626I2cRead8(hDevice, PCF50626_INT3_ADDR, &data))
+    {
+        NVODMPMU_PRINTF(("Error reading INT3"));
+        return;
+    }
+    if (data != 0)
+    {
+        if (data & PCF50626_INT3_MCHGRM)
+            pmuStatus->mChgPresent = NV_FALSE;
+
+        if (data & PCF50626_INT3_MCHGINS)
+        {
+            pmuStatus->mChgPresent = NV_TRUE;
+            NvOdmEnableOtgCircuitry(NV_TRUE);
+        }
+    }
+
+    // INT4
+    if (!Pcf50626I2cRead8(hDevice, PCF50626_INT4_ADDR, &data))
+    {
+        NVODMPMU_PRINTF(("Error reading INT4"));
+        return;
+    }
+    if (data != 0)
+    {
+        if (data & PCF50626_INT4_CHGRES)
+            pmuStatus->batFull = NV_FALSE;
+
+        if (data & PCF50626_INT4_BATFUL)
+            pmuStatus->batFull = NV_TRUE;
+    }
+
+}
+
+
diff --git a/arch/arm/mach-tegra/odm_kit/adaptations/pmu/pcf50626/pcf50626_interrupt.h b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/pcf50626/pcf50626_interrupt.h
new file mode 100644
index 000000000000..2cf1b404bc8c
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/pcf50626/pcf50626_interrupt.h
@@ -0,0 +1,62 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_PCF50626_INTERRUPT_HEADER
+#define INCLUDED_PCF50626_INTERRUPT_HEADER
+
+#include "pcf50626.h"
+
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+
+NvBool 
+Pcf50626SetupInterrupt(
+    NvOdmPmuDeviceHandle  hDevice, 
+    Pcf50626Status *pmuStatus);
+
+
+
+void 
+Pcf50626InterruptHandler_int(
+    NvOdmPmuDeviceHandle  hDevice, 
+    Pcf50626Status *pmuStatus);
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif // INCLUDED_PCF50626_INTERRUPT_HEADER
+
diff --git a/arch/arm/mach-tegra/odm_kit/adaptations/pmu/pcf50626/pcf50626_reg.h b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/pcf50626/pcf50626_reg.h
new file mode 100644
index 000000000000..2454487149e8
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/pcf50626/pcf50626_reg.h
@@ -0,0 +1,491 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+ 
+#ifndef PCF50626_REG_HEADER
+#define PCF50626_REG_HEADER
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+
+// The following are the OTP reset values
+#define PCF50626_ID_DEFAULT         0x31 // TBD, may change
+#define PCF50626_BVMC_RESET         0x18
+
+#define PCF50626_D1REGC1_RESET      0x6C
+#define PCF50626_D1REGC2_RESET      0x01
+#define PCF50626_D1REGC3_RESET      0x00
+
+#define PCF50626_D2REGC1_RESET      0x6C
+#define PCF50626_D2REGC2_RESET      0xE1
+#define PCF50626_D2REGC3_RESET      0x00
+
+#define PCF50626_D3REGC1_RESET      0x18
+#define PCF50626_D3REGC2_RESET      0xE1
+#define PCF50626_D3REGC3_RESET      0x80
+
+#define PCF50626_D7REGC2_RESET      0x01
+#define PCF50626_D7REGC3_RESET      0x00
+
+#define PCF50626_D8REGC2_RESET      0xE1
+#define PCF50626_D8REGC3_RESET      0x40
+
+#define PCF50626_RF1REGC1_RESET     0x58
+#define PCF50626_RF1REGC2_RESET     0x01
+#define PCF50626_RF1REGC3_RESET     0x40
+
+#define PCF50626_RF2REGC1_RESET     0x58
+#define PCF50626_RF2REGC2_RESET     0x01
+#define PCF50626_RF2REGC3_RESET     0x40
+
+#define PCF50626_IOREGC1_RESET      0x30
+#define PCF50626_IOREGC2_RESET      0xE1
+#define PCF50626_IOREGC3_RESET      0x40
+
+#define PCF50626_USBREGC1_RESET     0x58
+#define PCF50626_USBREGC2_RESET     0xE1
+#define PCF50626_USBREGC3_RESET     0x40
+
+#define PCF50626_LCREGC1_RESET      0x18
+#define PCF50626_LCREGC2_RESET      0xE1
+#define PCF50626_LCREGC3_RESET      0x00
+
+#define PCF50626_DCD1C1_RESET       0x18
+#define PCF50626_DCD1C2_RESET       0xE1
+#define PCF50626_DCD1C3_RESET       0x00
+#define PCF50626_DCD1C4_RESET       0x0F
+
+#define PCF50626_DCD2C1_RESET       0x30
+#define PCF50626_DCD2C2_RESET       0xE1
+#define PCF50626_DCD2C3_RESET       0x80
+#define PCF50626_DCD2C4_RESET       0x0F
+
+#define PCF50626_DCUDC2_RESET       0xE1
+#define PCF50626_DCUDC3_RESET       0xC0
+
+#define PCF50626_ALMCAL_RESET       0x11
+#define PCF50626_ALMCRV1_RESET      0x01
+#define PCF50626_ALMCRV2_RESET      0x28
+#define PCF50626_ALMCRV3_RESET      0x50
+#define PCF50626_ALMCRV4_RESET      0x78
+#define PCF50626_LED1C_RESET        0x4D
+#define PCF50626_LEDCC_RESET        0x01
+
+#define PCF50626_ADCC1_RESET        0x02
+#define PCF50626_ADCC2_RESET        0x00
+#define PCF50626_ADCC3_RESET        0x00
+#define PCF50626_ADCC4_RESET        0x00
+
+#define PCF50626_DCULEDC1_RESET     0x08
+#define PCF50626_DCULEDC2_RESET     0x01
+#define PCF50626_DCULEDC3_RESET     0x00
+#define PCF50626_DCULEDDIMMAN_RESET 0x3F
+
+#define PCF50626_CBCC1_RESET        0x2B
+#define PCF50626_CBCC2_RESET        0x5A
+#define PCF50626_CBCC3_RESET        0x12
+#define PCF50626_CBCC4_RESET        0x12
+#define PCF50626_CBCC5_RESET        0x0B
+#define PCF50626_CBCC6_RESET        0x02
+
+#define PCF50626_BBCC1_RESET        0x00
+
+
+//Table.  168
+#define PCF50626_ID_ADDR            0x00
+#define PCF50626_INT1_ADDR          0x01
+#define PCF50626_INT2_ADDR          0x02
+#define PCF50626_INT3_ADDR          0x03
+#define PCF50626_INT4_ADDR          0x04
+#define PCF50626_INT5_ADDR          0x05
+#define PCF50626_INT6_ADDR          0x06
+#define PCF50626_INT7_ADDR          0x09
+
+#define PCF50626_INT1M_ADDR         0x0A
+#define PCF50626_INT2M_ADDR         0x0B
+#define PCF50626_INT3M_ADDR         0x0C
+#define PCF50626_INT4M_ADDR         0x0D
+#define PCF50626_INT5M_ADDR         0x0E
+#define PCF50626_INT6M_ADDR         0x0F
+#define PCF50626_INT7M_ADDR         0x12
+
+#define PCF50626_ERROR_ADDR         0x13
+
+#define PCF50626_OOCC1_ADDR         0x14
+#define PCF50626_OOCC2_ADDR         0x15
+#define PCF50626_OOCPH_ADDR         0x16
+#define PCF50626_OOCS_ADDR          0x17
+
+#define PCF50626_BVMC_ADDR          0x18
+
+#define PCF50626_RECC1_ADDR         0x19
+#define PCF50626_RECC2_ADDR         0x1A
+#define PCF50626_RECS_ADDR          0x1B
+
+#define PCF50626_RTC1_ADDR          0x1C
+#define PCF50626_RTC2_ADDR          0x1D
+#define PCF50626_RTC3_ADDR          0x1E
+#define PCF50626_RTC4_ADDR          0x1F
+
+#define PCF50626_RTC1A_ADDR         0x20
+#define PCF50626_RTC2A_ADDR         0x21
+#define PCF50626_RTC3A_ADDR         0x22
+#define PCF50626_RTC4A_ADDR         0x23
+
+#define PCF50626_CBCC1_ADDR         0x24
+#define PCF50626_CBCC2_ADDR         0x25
+#define PCF50626_CBCC3_ADDR         0x26
+#define PCF50626_CBCC4_ADDR         0x27
+#define PCF50626_CBCC5_ADDR         0x28
+#define PCF50626_CBCC6_ADDR         0x29
+
+#define PCF50626_CBCS1_ADDR         0x2A
+#define PCF50626_CBCS2_ADDR         0x2B
+#define PCF50626_BBCC1_ADDR         0x2C
+#define PCF50626_PWM1S_ADDR         0x2D
+#define PCF50626_PWM1D_ADDR         0x2E
+#define PCF50626_PWM2S_ADDR         0x2F
+#define PCF50626_PWM2D_ADDR         0x30
+
+#define PCF50626_LED1C_ADDR         0x31
+#define PCF50626_LED2C_ADDR         0x32
+#define PCF50626_LEDCC_ADDR         0x33
+
+#define PCF50626_ADCC2_ADDR         0x34
+#define PCF50626_ADCC3_ADDR         0x35
+#define PCF50626_ADCC4_ADDR         0x36
+#define PCF50626_ADCC1_ADDR         0x37
+#define PCF50626_ADCS1_ADDR         0x38
+#define PCF50626_ADCS2_ADDR         0x39
+#define PCF50626_ADCS3_ADDR         0x3A
+
+#define PCF50626_TSIC2_ADDR         0x3B
+#define PCF50626_TSIC1_ADDR         0x3C
+#define PCF50626_TSIDAT1_ADDR       0x3D
+#define PCF50626_TSIDAT2_ADDR       0x3E
+#define PCF50626_TSIDAT3_ADDR       0x3F
+
+#define PCF50626_GPIO1C1_ADDR       0x40
+#define PCF50626_E1REGC2_ADDR       0x41
+#define PCF50626_E1REGC3_ADDR       0x42
+#define PCF50626_GPIO2C1_ADDR       0x43
+#define PCF50626_E2REGC2_ADDR       0x44
+#define PCF50626_E2REGC3_ADDR       0x45
+#define PCF50626_GPIO3C1_ADDR       0x46
+#define PCF50626_E3REGC2_ADDR       0x47
+#define PCF50626_E3REGC3_ADDR       0x48
+#define PCF50626_GPIO4C1_ADDR       0x49
+#define PCF50626_E4REGC2_ADDR       0x4A
+#define PCF50626_E4REGC3_ADDR       0x4B
+#define PCF50626_GPIO5C1_ADDR       0x4C
+#define PCF50626_E5REGC2_ADDR       0x4D
+#define PCF50626_E5REGC3_ADDR       0x4E
+#define PCF50626_GPIO6C1_ADDR       0x4F
+#define PCF50626_E6REGC2_ADDR       0x50
+#define PCF50626_E6REGC3_ADDR       0x51
+
+#define PCF50626_GPO1C1_ADDR        0x52
+#define PCF50626_EO1REGC2_ADDR      0x53
+#define PCF50626_EO1REGC3_ADDR      0x54
+#define PCF50626_GPO2C1_ADDR        0x55
+#define PCF50626_EO2REGC2_ADDR      0x56
+#define PCF50626_EO2REGC3_ADDR      0x57
+#define PCF50626_GPO3C1_ADDR        0x58
+#define PCF50626_EO3REGC2_ADDR      0x59
+#define PCF50626_EO3REGC3_ADDR      0x5A
+#define PCF50626_GPO4C1_ADDR        0x5B
+#define PCF50626_EO4REGC2_ADDR      0x5C
+#define PCF50626_EO4REGC3_ADDR      0x5D
+
+#define PCF50626_D1REGC1_ADDR       0x5E
+#define PCF50626_D1REGC2_ADDR       0x5F
+#define PCF50626_D1REGC3_ADDR       0x60
+
+#define PCF50626_D2REGC1_ADDR       0x61
+#define PCF50626_D2REGC2_ADDR       0x62
+#define PCF50626_D2REGC3_ADDR       0x63
+
+#define PCF50626_D3REGC1_ADDR       0x64
+#define PCF50626_D3REGC2_ADDR       0x65
+#define PCF50626_D3REGC3_ADDR       0x66
+
+#define PCF50626_D4REGC1_ADDR       0x67
+#define PCF50626_D4REGC2_ADDR       0x68
+#define PCF50626_D4REGC3_ADDR       0x69
+
+#define PCF50626_D5REGC1_ADDR       0x6A
+#define PCF50626_D5REGC2_ADDR       0x6B
+#define PCF50626_D5REGC3_ADDR       0x6C
+
+#define PCF50626_D6REGC1_ADDR       0x6D
+#define PCF50626_D6REGC2_ADDR       0x6E
+#define PCF50626_D6REGC3_ADDR       0x6F
+
+#define PCF50626_D7REGC1_ADDR       0x70
+#define PCF50626_D7REGC2_ADDR       0x71
+#define PCF50626_D7REGC3_ADDR       0x72
+
+#define PCF50626_D8REGC1_ADDR       0x73
+#define PCF50626_D8REGC2_ADDR       0x74
+#define PCF50626_D8REGC3_ADDR       0x75
+
+#define PCF50626_RF1REGC1_ADDR      0x76
+#define PCF50626_RF1REGC2_ADDR      0x77
+#define PCF50626_RF1REGC3_ADDR      0x78
+
+#define PCF50626_RF2REGC1_ADDR      0x79
+#define PCF50626_RF2REGC2_ADDR      0x7A
+#define PCF50626_RF2REGC3_ADDR      0x7B
+
+#define PCF50626_RF3REGC1_ADDR      0x7C
+#define PCF50626_RF3REGC2_ADDR      0x7D
+#define PCF50626_RF3REGC3_ADDR      0x7E
+
+#define PCF50626_RF4REGC1_ADDR      0x7F
+#define PCF50626_RF4REGC2_ADDR      0x80
+#define PCF50626_RF4REGC3_ADDR      0x81
+
+#define PCF50626_IOREGC1_ADDR       0x82
+#define PCF50626_IOREGC2_ADDR       0x83
+#define PCF50626_IOREGC3_ADDR       0x84
+
+#define PCF50626_USBREGC1_ADDR      0x85
+#define PCF50626_USBREGC2_ADDR      0x86
+#define PCF50626_USBREGC3_ADDR      0x87
+
+#define PCF50626_USIMREGC1_ADDR     0x88
+#define PCF50626_USIMREGC2_ADDR     0x89
+#define PCF50626_USIMREGC3_ADDR     0x8A
+
+#define PCF50626_LCREGC1_ADDR       0x8B
+#define PCF50626_LCREGC2_ADDR       0x8C
+#define PCF50626_LCREGC3_ADDR       0x8D
+
+#define PCF50626_HCREGC1_ADDR       0x8E
+#define PCF50626_HCREGC2_ADDR       0x8F
+#define PCF50626_HCREGC3_ADDR       0x90
+
+#define PCF50626_DCD1C1_ADDR        0x91
+#define PCF50626_DCD1C2_ADDR        0x92
+#define PCF50626_DCD1C3_ADDR        0x93
+#define PCF50626_DCD1C4_ADDR        0x94
+
+#define PCF50626_DCD1DVM1_ADDR      0x95
+#define PCF50626_DCD1DVM2_ADDR      0x96
+#define PCF50626_DCD1DVM3_ADDR      0x97
+#define PCF50626_DCD1DVMTIM_ADDR    0x98
+
+#define PCF50626_DCD2C1_ADDR        0x99
+#define PCF50626_DCD2C2_ADDR        0x9A
+#define PCF50626_DCD2C3_ADDR        0x9B
+#define PCF50626_DCD2C4_ADDR        0x9C
+
+#define PCF50626_DCD2DVM1_ADDR      0x9D
+#define PCF50626_DCD2DVM2_ADDR      0x9E
+#define PCF50626_DCD2DVM3_ADDR      0x9F
+#define PCF50626_DCD2DVMTIM_ADDR    0xA0
+
+#define PCF50626_DCUDC1_ADDR        0xA1
+#define PCF50626_DCUDC2_ADDR        0xA2
+#define PCF50626_DCUDC3_ADDR        0xA3
+#define PCF50626_DCUDC4_ADDR        0xA4
+#define PCF50626_DCUDDVMTIM_ADDR    0xA5
+
+#define PCF50626_DCULEDC1_ADDR      0xA6
+#define PCF50626_DCULEDC2_ADDR      0xA7
+#define PCF50626_DCULEDC3_ADDR      0xA8
+#define PCF50626_DCULED_DIMMAN_ADDR 0xA9
+
+#define PCF50626_ALMCAL_ADDR        0xAA
+#define PCF50626_ALMCALMEA_ADDR     0xAB
+#define PCF50626_ALMCRV1_ADDR       0xAC
+#define PCF50626_ALMCRV2_ADDR       0xAD
+#define PCF50626_ALMCRV3_ADDR       0xAE
+#define PCF50626_ALMCRV4_ADDR       0xAF
+
+#define PCF50626_GPIOS_ADDR         0xB0
+#define PCF50626_DREGS1_ADDR        0xB1
+#define PCF50626_DREGS2_ADDR        0xB2
+#define PCF50626_RFREGS_ADDR        0xB3
+#define PCF50626_GREGS_ADDR         0xB4
+
+#define PCF50626_GPIO7C1_ADDR       0xB5
+#define PCF50626_GPIO8C1_ADDR       0xB6
+
+#define PCF50626_USIMDETC_ADDR      0xB7
+
+#define PCF50626_TSINOI_ADDR        0xFE
+#define PCF50626_TSIDAT4_ADDR       0xFF
+
+
+/* field defines for register bit ops */
+#define PCF50626_C2_OPMOD_SHIFT                     0x05
+#define PCF50626_C2_OPMOD_ON                        0xE1
+#define PCF50626_C2_OPMOD_OFF                       0x01
+#define PCF50626_C1_OUTPUT_MASK                     0x7F
+
+#define PCF50626_OOCS_ONKEY_SHIFT                   0x00
+#define PCF50626_OOCS_ONKEY_MASK                    0x01
+#define PCF50626_OOCS_REC1_SHIFT                    0x01
+#define PCF50626_OOCS_REC1_MASK                     0x01
+#define PCF50626_OOCS_BATOK_SHIFT                   0x02
+#define PCF50626_OOCS_BATOK_MASK                    0x01
+#define PCF50626_OOCS_MCHGOK_SHIFT                  0x04
+#define PCF50626_OOCS_MCHGOK_MASK                   0x01
+#define PCF50626_OOCS_UCHGOK_SHIFT                  0x05
+#define PCF50626_OOCS_UCHGOK_MASK                   0x01
+#define PCF50626_OOCS_TEMPOK_SHIFT                  0x06
+#define PCF50626_OOCS_TEMPOK_MASK                   0x01
+
+#define PCF50626_CBCS1_BATTFUL_SHIFT                0x00
+#define PCF50626_CBCS1_BATTFUL_MASK                 0x01
+#define PCF50626_CBCS1_TLIMIT_SHIFT                 0x01
+#define PCF50626_CBCS1_TLIMIT_MASK                  0x01
+#define PCF50626_CBCS1_WDEXP_SHIFT                  0x02
+#define PCF50626_CBCS1_WDEXP_MASK                   0x01
+#define PCF50626_CBCS1_ILIMIT_SHIFT                 0x03
+#define PCF50626_CBCS1_ILIMIT_MASK                  0x01
+#define PCF50626_CBCS1_VLIMIT_SHIFT                 0x04
+#define PCF50626_CBCS1_VLIMIT_MASK                  0x01
+#define PCF50626_CBCS1_RESSTAT_SHIFT                0x07
+#define PCF50626_CBCS1_RESSTAT_MASK                 0x01
+#define PCF50626_CBCS2_NOBAT_SHIFT                  0x00
+#define PCF50626_CBCS2_NOBAT_MASK                   0x01
+#define PCF50626_CBCS2_USBSUSPSTAT_SHIFT            0x02
+#define PCF50626_CBCS2_USBSUSPSTAT_MASK             0x01
+#define PCF50626_CBCS2_CHGOVP_SHIFT                 0x03
+#define PCF50626_CBCS2_CHGOVP_MASK                  0x01
+
+#define PCF50626_ADCC1_STARTCMD_SHIFT               0x00
+#define PCF50626_ADCC1_STARTCMD_MASK                0x01
+#define PCF50626_ADCC1_STARTCMD_START               0x01
+#define PCF50626_ADCC1_STARTCMD_STOP                0x00
+
+#define PCF50626_ADCS3_ADCRDY_SHIFT                 0x07
+#define PCF50626_ADCS3_ADCRDY_MASK                  0x01
+#define PCF50626_ADCS3_ADCRDY_READY                 0x01
+
+#define PCF50626_DCULED_DIMMAN_LEDMAN_MASK          0x3F
+#define PCF50626_DCULED_DIMMAN_LEDMAN_SHIFT         0x00
+
+#define PCF50626_DCULED_DIMMAN_ALMSEL_MASK          0x01
+#define PCF50626_DCULED_DIMMAN_ALMSEL_SHIFT         0x06
+#define PCF50626_DCULED_DIMMAN_ALMSEL_ALM           0x01
+#define PCF50626_DCULED_DIMMAN_ALMSEL_MAN           0x00
+
+#define PCF50626_INT1_LOWBATT                       0x01
+#define PCF50626_INT1_HIGHTEMP                      0x80
+#define PCF50626_INT2_VMAX                          0x40
+#define PCF50626_INT3_MCHGINS                       0x40
+#define PCF50626_INT3_MCHGRM                        0x80
+#define PCF50626_INT4_CHGRES                        0x01
+#define PCF50626_INT4_BATFUL                        0x08
+
+#define PCF50626_CBCC1_CHGENA_SHIFT                 0x00
+#define PCF50626_CBCC1_CHGENA_MASK                  0x01
+#define PCF50626_CBCC2_SUSPENA_SHIFT                 0x02
+#define PCF50626_CBCC2_SUSPENA_MASK                  0x01
+
+//rail specs
+#define PCF50626_DCDXOUT_VOLTAGE_OFFSET_MV                  600
+#define PCF50626_DCDXOUT_VOLTAGE_MIN_MV                     625
+#define PCF50626_DCDXOUT_VOLTAGE_STEP_MV                    25
+#define PCF50626_DCDXOUT_VOLTAGE_MAX_MV                     2700
+#define PCF50626_DCDXOUT_TURNON_TIME_MICROSEC               365
+#define PCF50626_DCDXOUT_SWITCH_TIME_MICROSEC               20
+
+#define PCF50626_DCUDOUT_MODE1_VOLTAGE_OFFSET_MV            2675
+#define PCF50626_DCUDOUT_MODE1_VOLTAGE_MIN_MV               3100
+#define PCF50626_DCUDOUT_MODE1_VOLTAGE_STEP_MV              25
+#define PCF50626_DCUDOUT_MODE1_VOLTAGE_MAX_MV               4975
+#define PCF50626_DCUDOUT_TURNON_TIME_MICROSEC               65
+#define PCF50626_DCUDOUT_SWITCH_TIME_MICROSEC               0
+
+#define PCF50626_DXREGOUT_VOLTAGE_OFFSET_MV                 600
+#define PCF50626_DXREGOUT_VOLTAGE_MIN_MV                    1200
+#define PCF50626_DXREGOUT_VOLTAGE_STEP_MV                   100
+#define PCF50626_DXREGOUT_VOLTAGE_MAX_MV                    3300
+#define PCF50626_DXREGOUT_TURNON_TIME_MICROSEC              85
+#define PCF50626_DXREGOUT_SWITCH_TIME_MICROSEC              0
+
+#define PCF50626_RFXREGOUT_VOLTAGE_OFFSET_MV                600
+#define PCF50626_RFXREGOUT_VOLTAGE_MIN_MV                   1200
+#define PCF50626_RFXREGOUT_VOLTAGE_STEP_MV                  100
+#define PCF50626_RFXREGOUT_VOLTAGE_MAX_MV                   3000
+#define PCF50626_RFXREGOUT_TURNON_TIME_MICROSEC             285
+#define PCF50626_RFXREGOUT_SWITCH_TIME_MICROSEC             0
+
+#define PCF50626_HCREGOUT_VOLTAGE_OFFSET_MV                 600
+#define PCF50626_HCREGOUT_VOLTAGE_MIN_MV                    1800
+#define PCF50626_HCREGOUT_VOLTAGE_STEP_MV                   100
+#define PCF50626_HCREGOUT_VOLTAGE_MAX_MV                    3000
+#define PCF50626_HCREGOUT_TURNON_TIME_MICROSEC              85
+#define PCF50626_HCREGOUT_SWITCH_TIME_MICROSEC              0
+
+#define PCF50626_IOREGOUT_VOLTAGE_OFFSET_MV                 600
+#define PCF50626_IOREGOUT_VOLTAGE_MIN_MV                    1200
+#define PCF50626_IOREGOUT_VOLTAGE_STEP_MV                   100
+#define PCF50626_IOREGOUT_VOLTAGE_MAX_MV                    3300
+#define PCF50626_IOREGOUT_TURNON_TIME_MICROSEC              85
+#define PCF50626_IOREGOUT_SWITCH_TIME_MICROSEC              0
+
+#define PCF50626_USBREGOUT_VOLTAGE_OFFSET_MV                600
+#define PCF50626_USBREGOUT_VOLTAGE_MIN_MV                   1200
+#define PCF50626_USBREGOUT_VOLTAGE_STEP_MV                  100
+#define PCF50626_USBREGOUT_VOLTAGE_MAX_MV                   3300
+#define PCF50626_USBREGOUT_TURNON_TIME_MICROSEC             85
+#define PCF50626_USBREGOUT_SWITCH_TIME_MICROSEC             0
+
+#define PCF50626_USIMREGOUT_VOLTAGE_OFFSET_MV               600
+#define PCF50626_USIMREGOUT_VOLTAGE_MIN_MV                  1800
+#define PCF50626_USIMREGOUT_VOLTAGE_STEP_MV                 100
+#define PCF50626_USIMREGOUT_VOLTAGE_MAX_MV                  3000
+#define PCF50626_USIMREGOUT_TURNON_TIME_MICROSEC            105
+#define PCF50626_USIMREGOUT_SWITCH_TIME_MICROSEC            0
+
+#define PCF50626_LCREGOUT_VOLTAGE_OFFSET_MV                 600
+#define PCF50626_LCREGOUT_VOLTAGE_MIN_MV                    600
+#define PCF50626_LCREGOUT_VOLTAGE_STEP_MV                   50
+#define PCF50626_LCREGOUT_VOLTAGE_MAX_MV                    2900
+#define PCF50626_LCREGOUT_VOLTAGE_RESCHANGE_MV              1400
+#define PCF50626_LCREGOUT_TURNON_TIME_MICROSEC              125
+#define PCF50626_LCREGOUT_SWITCH_TIME_MICROSEC              0
+
+#if defined(__cplusplus)
+}
+#endif
+
+
+#endif //PCF50626_VOLTAGE_INFO_TABLE_HEADER
+
diff --git a/arch/arm/mach-tegra/odm_kit/adaptations/pmu/pcf50626/pcf50626_rtc.c b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/pcf50626/pcf50626_rtc.c
new file mode 100644
index 000000000000..ca35bab03b2d
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/pcf50626/pcf50626_rtc.c
@@ -0,0 +1,155 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include "pcf50626_rtc.h"
+#include "pcf50626_i2c.h"
+#include "pcf50626_reg.h"
+
+/* Read RTC count register */
+
+static NvBool bRtcNotInitialized = NV_TRUE;
+
+NvBool 
+Pcf50626RtcCountRead(
+    NvOdmPmuDeviceHandle hDevice, 
+    NvU32* Count)
+{
+    if (Pcf50626RtcWasStartUpFromNoPower(hDevice) && bRtcNotInitialized)
+    {
+        if (!Pcf50626I2cWrite32 (hDevice, PCF50626_RTC1_ADDR, 0))
+        {
+            return NV_FALSE;
+        }
+        bRtcNotInitialized = NV_FALSE;
+        *Count = 0;
+        return NV_TRUE;
+    } else
+    {   
+        return ( Pcf50626I2cRead32 (hDevice, PCF50626_RTC1_ADDR, Count) );
+    }   
+}
+
+/* Write RTC count register */
+
+NvBool 
+Pcf50626RtcCountWrite(
+    NvOdmPmuDeviceHandle hDevice, 
+    NvU32 Count)
+{
+    NvBool ret;
+
+    ret = Pcf50626I2cWrite32 (hDevice, PCF50626_RTC1_ADDR, Count);
+
+    if (ret && bRtcNotInitialized)
+        bRtcNotInitialized = NV_FALSE;
+    
+    return ret;
+}
+
+/* Read RTC alarm count register */
+
+NvBool 
+Pcf50626RtcAlarmCountRead(
+    NvOdmPmuDeviceHandle hDevice, 
+    NvU32* Count)
+{
+    return ( Pcf50626I2cRead32 (hDevice, PCF50626_RTC1A_ADDR, Count) );
+}
+
+/* Write RTC alarm count register */
+
+NvBool 
+Pcf50626RtcAlarmCountWrite(
+    NvOdmPmuDeviceHandle hDevice, 
+    NvU32 Count)
+{
+    return ( Pcf50626I2cWrite32 (hDevice, PCF50626_RTC1A_ADDR, Count) );
+}
+
+/* Reads RTC alarm interrupt mask status */
+
+NvBool 
+Pcf50626RtcIsAlarmIntEnabled(NvOdmPmuDeviceHandle hDevice)
+{
+    NvU8    Mask;
+
+    if(Pcf50626I2cRead8 (hDevice, PCF50626_INT1M_ADDR, &Mask))
+    {
+        return ((Mask & 0x8)? NV_FALSE:NV_TRUE);
+    }
+
+    return NV_FALSE;
+}
+
+/* Enables / Disables the RTC alarm interrupt */
+
+NvBool 
+Pcf50626RtcAlarmIntEnable(
+    NvOdmPmuDeviceHandle hDevice, 
+    NvBool Enable)
+{
+    NvBool  Status = NV_FALSE;
+    NvU8    Mask;
+
+    if ((Status = Pcf50626I2cRead8(hDevice, PCF50626_INT1M_ADDR, &Mask)) == NV_TRUE)
+    {
+        (Mask = Enable? (Mask & ~0x8):(Mask|0x8));
+        Status = Pcf50626I2cWrite8 (hDevice, PCF50626_INT1M_ADDR, Mask);
+    }
+
+    return Status;
+}
+
+/* Checks if boot was from nopower / powered state */
+
+NvBool 
+Pcf50626RtcWasStartUpFromNoPower(NvOdmPmuDeviceHandle hDevice)
+{
+    NvU8 Data;
+
+    // Check "nopower" bit of the ERROR status register.
+    // Make sure the backup battery charger is enabled (bbce and vsaveen bits). This is done by
+    // the bootloader. If this is not done, the "nopower" bit will remain stuck at 0x1.
+    if ((Pcf50626I2cRead8(hDevice, PCF50626_ERROR_ADDR, &Data)) == NV_TRUE)
+    {
+        return ((Data & 0x20)? NV_TRUE : NV_FALSE);
+    }
+
+    return NV_FALSE;
+}
+
+NvBool
+Pcf50626IsRtcInitialized(NvOdmPmuDeviceHandle hDevice)
+{
+    return ((Pcf50626RtcWasStartUpFromNoPower(hDevice))? NV_FALSE : NV_TRUE);
+}
+
diff --git a/arch/arm/mach-tegra/odm_kit/adaptations/pmu/pcf50626/pcf50626_rtc.h b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/pcf50626/pcf50626_rtc.h
new file mode 100644
index 000000000000..f5979cf5e52d
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/pcf50626/pcf50626_rtc.h
@@ -0,0 +1,97 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_PCF50626_RTC_HEADER
+#define INCLUDED_PCF50626_RTC_HEADER
+
+#include "pmu_hal.h"
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+/* Read RTC count register */
+
+NvBool 
+Pcf50626RtcCountRead(
+    NvOdmPmuDeviceHandle hDevice, 
+    NvU32* Count);
+
+/* Read RTC alarm count register */
+
+NvBool 
+Pcf50626RtcAlarmCountRead(
+    NvOdmPmuDeviceHandle hDevice, 
+    NvU32* Count);
+
+/* Write RTC count register */
+
+NvBool 
+Pcf50626RtcCountWrite(
+    NvOdmPmuDeviceHandle hDevice, 
+    NvU32 Count);
+
+/* Write RTC alarm count register */
+
+NvBool 
+Pcf50626RtcAlarmCountWrite(
+    NvOdmPmuDeviceHandle hDevice, 
+    NvU32 Count);
+
+/* Reads RTC alarm interrupt mask status */
+
+NvBool 
+Pcf50626RtcIsAlarmIntEnabled(NvOdmPmuDeviceHandle hDevice);
+
+/* Enables / Disables the RTC alarm interrupt */
+
+NvBool 
+Pcf50626RtcAlarmIntEnable(
+    NvOdmPmuDeviceHandle hDevice, 
+    NvBool Enable);
+
+/* Checks if boot was from nopower / powered state */
+
+NvBool 
+Pcf50626RtcWasStartUpFromNoPower(NvOdmPmuDeviceHandle hDevice);
+
+NvBool
+Pcf50626IsRtcInitialized(NvOdmPmuDeviceHandle hDevice);
+
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif // INCLUDED_PCF50626_RTC_HEADER
+
diff --git a/arch/arm/mach-tegra/odm_kit/adaptations/pmu/pcf50626/pcf50626_supply_info_table.h b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/pcf50626/pcf50626_supply_info_table.h
new file mode 100644
index 000000000000..7064cf6e68c7
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/pcf50626/pcf50626_supply_info_table.h
@@ -0,0 +1,615 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+ 
+#ifndef PCF50626_SUPPLY_INFO_TABLE_HEADER
+#define PCF50626_SUPPLY_INFO_TABLE_HEADER
+
+#include "nvodm_pmu_pcf50626_supply_info.h"
+#include "pcf50626_reg.h"
+
+
+// defines for the request Voltage. This is board specific and ODM should change this based on 
+// device.
+#define PCF50626_REQUESTVOLTAGE_DCD1_MV       1200
+#define PCF50626_REQUESTVOLTAGE_DCD2_MV       1925
+#define PCF50626_REQUESTVOLTAGE_DCUD_MV       4975
+#define PCF50626_REQUESTVOLTAGE_RF1REG_MV     2800
+#define PCF50626_REQUESTVOLTAGE_RF2REG_MV     2800
+#define PCF50626_REQUESTVOLTAGE_RF3REG_MV     1800
+#define PCF50626_REQUESTVOLTAGE_RF4REG_MV     2800
+#define PCF50626_REQUESTVOLTAGE_D1REG_MV      3300
+#define PCF50626_REQUESTVOLTAGE_D2REG_MV      3300
+#define PCF50626_REQUESTVOLTAGE_D3REG_MV      1200
+#define PCF50626_REQUESTVOLTAGE_D4REG_MV      1200
+#define PCF50626_REQUESTVOLTAGE_D5REG_MV      1800
+#define PCF50626_REQUESTVOLTAGE_D6REG_MV      2800
+#define PCF50626_REQUESTVOLTAGE_D7REG_MV      2800
+#define PCF50626_REQUESTVOLTAGE_D8REG_MV      3100
+#define PCF50626_REQUESTVOLTAGE_HCREG_MV      2800
+#define PCF50626_REQUESTVOLTAGE_IOREG_MV      1800
+#define PCF50626_REQUESTVOLTAGE_USIMREG_MV    3000
+#define PCF50626_REQUESTVOLTAGE_USBREG_MV     2800
+#define PCF50626_REQUESTVOLTAGE_LCREG_MV      1200
+
+// defines for the additional load-dependent TurnOn delays. This is board
+// specific and ODM should change this based on device.
+#define PCF50626_TURNON_DELAY_DCD1_US       0
+#define PCF50626_TURNON_DELAY_DCD2_US       0
+#define PCF50626_TURNON_DELAY_DCUD_US       0
+#define PCF50626_TURNON_DELAY_RF1REG_US     0
+#define PCF50626_TURNON_DELAY_RF2REG_US     0
+#define PCF50626_TURNON_DELAY_RF3REG_US     0
+#define PCF50626_TURNON_DELAY_RF4REG_US     0
+#define PCF50626_TURNON_DELAY_D1REG_US      0
+#define PCF50626_TURNON_DELAY_D2REG_US      0
+#define PCF50626_TURNON_DELAY_D3REG_US      0
+#define PCF50626_TURNON_DELAY_D4REG_US      0
+#define PCF50626_TURNON_DELAY_D5REG_US      2000
+#define PCF50626_TURNON_DELAY_D6REG_US      500
+#define PCF50626_TURNON_DELAY_D7REG_US      0
+#define PCF50626_TURNON_DELAY_D8REG_US      0
+#define PCF50626_TURNON_DELAY_HCREG_US      0
+#define PCF50626_TURNON_DELAY_IOREG_US      0
+#define PCF50626_TURNON_DELAY_USIMREG_US    0
+#define PCF50626_TURNON_DELAY_USBREG_US     0
+#define PCF50626_TURNON_DELAY_LCREG_US      0
+
+
+const PCF50626PmuSupplyInfo pcf50626SupplyInfoTable[] =
+{
+    {
+        PCF50626PmuSupply_Invalid,
+        PCF50626PmuSupply_Invalid,
+        0,0,0,0,   
+        0,0,0,0,
+        {NV_TRUE,0,0,0,0},
+        0,0,0
+    },
+
+     // DCD1
+    {
+        PCF50626PmuSupply_DCD1,
+        PCF50626PmuSupply_VBAT,
+        
+        PCF50626_DCD1C1_ADDR,
+        PCF50626_DCD1C2_ADDR,
+        PCF50626_DCD1C3_ADDR,
+        PCF50626_DCD1C4_ADDR,
+   
+        PCF50626_DCD1DVM1_ADDR,
+        PCF50626_DCD1DVM2_ADDR,
+        PCF50626_DCD1DVM3_ADDR,
+        PCF50626_DCD1DVMTIM_ADDR,
+
+        {
+            NV_FALSE,
+            PCF50626_DCDXOUT_VOLTAGE_MIN_MV, 
+            PCF50626_DCDXOUT_VOLTAGE_STEP_MV,
+            PCF50626_DCDXOUT_VOLTAGE_MAX_MV,       
+            PCF50626_REQUESTVOLTAGE_DCD1_MV
+        },
+
+        PCF50626_DCDXOUT_VOLTAGE_OFFSET_MV,
+        PCF50626_DCDXOUT_TURNON_TIME_MICROSEC + PCF50626_TURNON_DELAY_DCD1_US,
+        PCF50626_DCDXOUT_SWITCH_TIME_MICROSEC
+    },
+
+    //DCD2
+    {
+        PCF50626PmuSupply_DCD2,
+        PCF50626PmuSupply_VBAT,
+        
+        PCF50626_DCD2C1_ADDR,
+        PCF50626_DCD2C2_ADDR,
+        PCF50626_DCD2C3_ADDR,
+        PCF50626_DCD2C4_ADDR,
+    
+        PCF50626_DCD2DVM1_ADDR,
+        PCF50626_DCD2DVM2_ADDR,
+        PCF50626_DCD2DVM3_ADDR,
+        PCF50626_DCD2DVMTIM_ADDR,
+
+        {
+            NV_FALSE,
+            PCF50626_DCDXOUT_VOLTAGE_MIN_MV, 
+            PCF50626_DCDXOUT_VOLTAGE_STEP_MV,
+            PCF50626_DCDXOUT_VOLTAGE_MAX_MV,
+            PCF50626_REQUESTVOLTAGE_DCD2_MV
+        },
+
+        PCF50626_DCDXOUT_VOLTAGE_OFFSET_MV, 
+        PCF50626_DCDXOUT_TURNON_TIME_MICROSEC + PCF50626_TURNON_DELAY_DCD2_US,
+        PCF50626_DCDXOUT_SWITCH_TIME_MICROSEC
+    },
+
+    //DCUD
+    {
+        PCF50626PmuSupply_DCUD,
+        PCF50626PmuSupply_VBAT,
+
+        PCF50626_DCUDC1_ADDR,
+        PCF50626_DCUDC2_ADDR,
+        PCF50626_DCUDC3_ADDR,
+        PCF50626_DCUDC4_ADDR,
+        0,0,0,
+        PCF50626_DCUDDVMTIM_ADDR,
+
+        {
+            NV_FALSE,
+            PCF50626_DCUDOUT_MODE1_VOLTAGE_MIN_MV, 
+            PCF50626_DCUDOUT_MODE1_VOLTAGE_STEP_MV, 
+            PCF50626_DCUDOUT_MODE1_VOLTAGE_MAX_MV,
+            PCF50626_REQUESTVOLTAGE_DCUD_MV
+        },
+
+        PCF50626_DCUDOUT_MODE1_VOLTAGE_OFFSET_MV, 
+        PCF50626_DCUDOUT_TURNON_TIME_MICROSEC + PCF50626_TURNON_DELAY_DCUD_US,
+        PCF50626_DCUDOUT_SWITCH_TIME_MICROSEC
+    },
+
+    //DCULED            
+    {
+        PCF50626PmuSupply_DCULED,
+        PCF50626PmuSupply_VBAT,
+
+        PCF50626_DCULEDC1_ADDR,
+        PCF50626_DCULEDC2_ADDR,
+        PCF50626_DCULEDC3_ADDR,
+        PCF50626_DCULED_DIMMAN_ADDR,
+        0,0,0,0,
+        {NV_TRUE, 0,0,0, 0},
+        0,87,0
+    },        
+
+    //RF1    
+    {
+        PCF50626PmuSupply_RF1REG,
+        PCF50626PmuSupply_VBAT,
+
+        PCF50626_RF1REGC1_ADDR,
+        PCF50626_RF1REGC2_ADDR,
+        PCF50626_RF1REGC3_ADDR,
+        0,
+        0,0,0,0,
+        {
+            NV_FALSE,
+            PCF50626_RFXREGOUT_VOLTAGE_MIN_MV, 
+            PCF50626_RFXREGOUT_VOLTAGE_STEP_MV, 
+            PCF50626_RFXREGOUT_VOLTAGE_MAX_MV,
+            PCF50626_REQUESTVOLTAGE_RF1REG_MV
+        }, 
+
+        PCF50626_RFXREGOUT_VOLTAGE_OFFSET_MV, 
+        PCF50626_RFXREGOUT_TURNON_TIME_MICROSEC + PCF50626_TURNON_DELAY_RF1REG_US,
+        PCF50626_RFXREGOUT_SWITCH_TIME_MICROSEC
+    },
+
+    //RF2
+    {
+        PCF50626PmuSupply_RF2REG,
+        PCF50626PmuSupply_VBAT,
+        
+        PCF50626_RF2REGC1_ADDR,
+        PCF50626_RF2REGC2_ADDR,
+        PCF50626_RF2REGC3_ADDR,
+        0,
+        0,0,0,0,
+
+        {
+            NV_FALSE,
+            PCF50626_RFXREGOUT_VOLTAGE_MIN_MV, 
+            PCF50626_RFXREGOUT_VOLTAGE_STEP_MV, 
+            PCF50626_RFXREGOUT_VOLTAGE_MAX_MV,
+            PCF50626_REQUESTVOLTAGE_RF2REG_MV
+        }, 
+
+        PCF50626_RFXREGOUT_VOLTAGE_OFFSET_MV, 
+        PCF50626_RFXREGOUT_TURNON_TIME_MICROSEC + PCF50626_TURNON_DELAY_RF2REG_US,
+        PCF50626_RFXREGOUT_SWITCH_TIME_MICROSEC
+    },
+
+    //RF3
+    {
+        PCF50626PmuSupply_RF3REG,
+        PCF50626PmuSupply_VBAT,
+
+        PCF50626_RF3REGC1_ADDR,
+        PCF50626_RF3REGC2_ADDR,
+        PCF50626_RF3REGC3_ADDR,
+        0,
+        0,0,0,0,
+
+        {
+            NV_FALSE,
+            PCF50626_RFXREGOUT_VOLTAGE_MIN_MV, 
+            PCF50626_RFXREGOUT_VOLTAGE_STEP_MV, 
+            PCF50626_RFXREGOUT_VOLTAGE_MAX_MV,
+            PCF50626_REQUESTVOLTAGE_RF3REG_MV
+        },
+        
+        PCF50626_RFXREGOUT_VOLTAGE_OFFSET_MV, 
+        PCF50626_RFXREGOUT_TURNON_TIME_MICROSEC + PCF50626_TURNON_DELAY_RF3REG_US,
+        PCF50626_RFXREGOUT_SWITCH_TIME_MICROSEC
+    },
+
+    //RF4
+    {
+        PCF50626PmuSupply_RF4REG,
+        PCF50626PmuSupply_VBAT,
+
+        PCF50626_RF4REGC1_ADDR,
+        PCF50626_RF4REGC2_ADDR,
+        PCF50626_RF4REGC3_ADDR,
+        0,
+        0,0,0,0,
+        
+        {
+            NV_FALSE,
+            PCF50626_RFXREGOUT_VOLTAGE_MIN_MV, 
+            PCF50626_RFXREGOUT_VOLTAGE_STEP_MV, 
+            PCF50626_RFXREGOUT_VOLTAGE_MAX_MV,
+            PCF50626_REQUESTVOLTAGE_RF4REG_MV
+        },
+
+        PCF50626_RFXREGOUT_VOLTAGE_OFFSET_MV,        
+        PCF50626_RFXREGOUT_TURNON_TIME_MICROSEC + PCF50626_TURNON_DELAY_RF4REG_US,
+        PCF50626_RFXREGOUT_SWITCH_TIME_MICROSEC
+    },
+
+    //D1
+    {
+        PCF50626PmuSupply_D1REG,            
+        PCF50626PmuSupply_DCUD,
+        
+        PCF50626_D1REGC1_ADDR,
+        PCF50626_D1REGC2_ADDR,
+        PCF50626_D1REGC3_ADDR,
+        0,
+        0,0,0,0,
+
+        {
+            NV_FALSE,
+            PCF50626_DXREGOUT_VOLTAGE_MIN_MV, 
+            PCF50626_DXREGOUT_VOLTAGE_STEP_MV, 
+            PCF50626_DXREGOUT_VOLTAGE_MAX_MV,
+            PCF50626_REQUESTVOLTAGE_D1REG_MV
+        },
+
+        PCF50626_DXREGOUT_VOLTAGE_OFFSET_MV,         
+        PCF50626_DXREGOUT_TURNON_TIME_MICROSEC + PCF50626_TURNON_DELAY_D1REG_US,
+        PCF50626_DXREGOUT_SWITCH_TIME_MICROSEC
+    },
+
+    //D2
+    {
+        PCF50626PmuSupply_D2REG,
+        PCF50626PmuSupply_DCUD,
+        PCF50626_D2REGC1_ADDR,
+        PCF50626_D2REGC2_ADDR,
+        PCF50626_D2REGC3_ADDR,
+        0,
+        0,0,0,0,
+
+        {
+            NV_FALSE,
+            PCF50626_DXREGOUT_VOLTAGE_MIN_MV, 
+            PCF50626_DXREGOUT_VOLTAGE_STEP_MV, 
+            PCF50626_DXREGOUT_VOLTAGE_MAX_MV,
+            PCF50626_REQUESTVOLTAGE_D2REG_MV
+        },
+        
+        PCF50626_DXREGOUT_VOLTAGE_OFFSET_MV, 
+        PCF50626_DXREGOUT_TURNON_TIME_MICROSEC + PCF50626_TURNON_DELAY_D2REG_US,
+        PCF50626_DXREGOUT_SWITCH_TIME_MICROSEC
+    },
+
+    //D3
+    {
+        PCF50626PmuSupply_D3REG,
+        PCF50626PmuSupply_DCD2,
+
+        PCF50626_D3REGC1_ADDR,
+        PCF50626_D3REGC2_ADDR,
+        PCF50626_D3REGC3_ADDR,
+        0,
+        0,0,0,0,
+        
+        {
+            NV_FALSE,
+            PCF50626_DXREGOUT_VOLTAGE_MIN_MV, 
+            PCF50626_DXREGOUT_VOLTAGE_STEP_MV, 
+            PCF50626_DXREGOUT_VOLTAGE_MAX_MV,
+            PCF50626_REQUESTVOLTAGE_D3REG_MV
+        },
+        
+        PCF50626_DXREGOUT_VOLTAGE_OFFSET_MV, 
+        PCF50626_DXREGOUT_TURNON_TIME_MICROSEC + PCF50626_TURNON_DELAY_D3REG_US,
+        PCF50626_DXREGOUT_SWITCH_TIME_MICROSEC
+    },
+
+    //D4
+    {
+        PCF50626PmuSupply_D4REG,
+        PCF50626PmuSupply_DCD2,
+
+        PCF50626_D4REGC1_ADDR,
+        PCF50626_D4REGC2_ADDR,
+        PCF50626_D4REGC3_ADDR,
+        0,
+        0,0,0,0,
+
+        {
+            NV_FALSE,
+            PCF50626_DXREGOUT_VOLTAGE_MIN_MV, 
+            PCF50626_DXREGOUT_VOLTAGE_STEP_MV, 
+            PCF50626_DXREGOUT_VOLTAGE_MAX_MV,
+            PCF50626_REQUESTVOLTAGE_D4REG_MV
+        },
+        
+        PCF50626_DXREGOUT_VOLTAGE_OFFSET_MV, 
+        PCF50626_DXREGOUT_TURNON_TIME_MICROSEC + PCF50626_TURNON_DELAY_D4REG_US,
+        PCF50626_DXREGOUT_SWITCH_TIME_MICROSEC
+    },
+
+    //D5
+    {
+        PCF50626PmuSupply_D5REG,
+        PCF50626PmuSupply_VBAT,
+
+        PCF50626_D5REGC1_ADDR,
+        PCF50626_D5REGC2_ADDR,
+        PCF50626_D5REGC3_ADDR,
+        0,
+        0,0,0,0,
+
+        {
+            NV_FALSE,
+            PCF50626_DXREGOUT_VOLTAGE_MIN_MV, 
+            PCF50626_DXREGOUT_VOLTAGE_STEP_MV, 
+            PCF50626_DXREGOUT_VOLTAGE_MAX_MV,
+            PCF50626_REQUESTVOLTAGE_D5REG_MV
+        },
+        
+        PCF50626_DXREGOUT_VOLTAGE_OFFSET_MV, 
+        PCF50626_DXREGOUT_TURNON_TIME_MICROSEC + PCF50626_TURNON_DELAY_D5REG_US,
+        PCF50626_DXREGOUT_SWITCH_TIME_MICROSEC
+    },
+
+    //D6
+    {
+        PCF50626PmuSupply_D6REG,
+        PCF50626PmuSupply_VBAT,
+
+        PCF50626_D6REGC1_ADDR,
+        PCF50626_D6REGC2_ADDR,
+        PCF50626_D6REGC3_ADDR,
+        0,
+        0,0,0,0,
+
+        {
+            NV_FALSE,
+            PCF50626_DXREGOUT_VOLTAGE_MIN_MV, 
+            PCF50626_DXREGOUT_VOLTAGE_STEP_MV, 
+            PCF50626_DXREGOUT_VOLTAGE_MAX_MV,
+            PCF50626_REQUESTVOLTAGE_D6REG_MV
+        },
+        
+        PCF50626_DXREGOUT_VOLTAGE_OFFSET_MV, 
+        PCF50626_DXREGOUT_TURNON_TIME_MICROSEC + PCF50626_TURNON_DELAY_D6REG_US,
+        PCF50626_DXREGOUT_SWITCH_TIME_MICROSEC
+    },
+
+    //D7
+    {
+        PCF50626PmuSupply_D7REG,
+        PCF50626PmuSupply_VBAT,
+
+        PCF50626_D7REGC1_ADDR,
+        PCF50626_D7REGC2_ADDR,
+        PCF50626_D7REGC3_ADDR,
+        0,
+        0,0,0,0,
+
+        {
+            NV_FALSE,
+            PCF50626_DXREGOUT_VOLTAGE_MIN_MV, 
+            PCF50626_DXREGOUT_VOLTAGE_STEP_MV, 
+            PCF50626_DXREGOUT_VOLTAGE_MAX_MV,
+            PCF50626_REQUESTVOLTAGE_D7REG_MV
+        },
+        
+        PCF50626_DXREGOUT_VOLTAGE_OFFSET_MV, 
+        PCF50626_DXREGOUT_TURNON_TIME_MICROSEC + PCF50626_TURNON_DELAY_D7REG_US,
+        PCF50626_DXREGOUT_SWITCH_TIME_MICROSEC
+    },
+
+    //D8
+    {
+        PCF50626PmuSupply_D8REG,
+        PCF50626PmuSupply_VBAT,
+
+        PCF50626_D8REGC1_ADDR,
+        PCF50626_D8REGC2_ADDR,
+        PCF50626_D8REGC3_ADDR,
+        0,
+        0,0,0,0,
+
+        {
+            NV_FALSE,
+            PCF50626_DXREGOUT_VOLTAGE_MIN_MV, 
+            PCF50626_DXREGOUT_VOLTAGE_STEP_MV, 
+            PCF50626_DXREGOUT_VOLTAGE_MAX_MV,
+            PCF50626_REQUESTVOLTAGE_D8REG_MV
+        },
+        
+        PCF50626_DXREGOUT_VOLTAGE_OFFSET_MV, 
+        PCF50626_DXREGOUT_TURNON_TIME_MICROSEC + PCF50626_TURNON_DELAY_D8REG_US,
+        PCF50626_DXREGOUT_SWITCH_TIME_MICROSEC
+    },
+
+    //HCREG
+    {
+        PCF50626PmuSupply_HCREG,
+        PCF50626PmuSupply_VBAT,
+
+        PCF50626_HCREGC1_ADDR,
+        PCF50626_HCREGC2_ADDR,
+        PCF50626_HCREGC3_ADDR,
+        0,
+        0,0,0,0,
+
+        {
+            NV_FALSE,
+            PCF50626_HCREGOUT_VOLTAGE_MIN_MV, 
+            PCF50626_HCREGOUT_VOLTAGE_STEP_MV, 
+            PCF50626_HCREGOUT_VOLTAGE_MAX_MV,
+            PCF50626_REQUESTVOLTAGE_HCREG_MV
+        },
+        
+        PCF50626_HCREGOUT_VOLTAGE_OFFSET_MV, 
+        PCF50626_HCREGOUT_TURNON_TIME_MICROSEC + PCF50626_TURNON_DELAY_HCREG_US,
+        PCF50626_HCREGOUT_SWITCH_TIME_MICROSEC
+    },
+
+    //IO
+    {
+        PCF50626PmuSupply_IOREG,
+        PCF50626PmuSupply_VBAT,
+
+        PCF50626_IOREGC1_ADDR,
+        PCF50626_IOREGC2_ADDR,
+        PCF50626_IOREGC3_ADDR,
+        0,
+        0,0,0,0,
+
+        {
+            NV_FALSE,
+            PCF50626_IOREGOUT_VOLTAGE_MIN_MV, 
+            PCF50626_IOREGOUT_VOLTAGE_STEP_MV, 
+            PCF50626_IOREGOUT_VOLTAGE_MAX_MV,
+            PCF50626_REQUESTVOLTAGE_IOREG_MV
+        },
+        
+        PCF50626_IOREGOUT_VOLTAGE_OFFSET_MV, 
+        PCF50626_IOREGOUT_TURNON_TIME_MICROSEC + PCF50626_TURNON_DELAY_IOREG_US,
+        PCF50626_IOREGOUT_SWITCH_TIME_MICROSEC
+    },
+ 
+    //USIM
+    {
+        PCF50626PmuSupply_USIMREG,
+        PCF50626PmuSupply_VBAT,
+
+        PCF50626_USIMREGC1_ADDR,
+        PCF50626_USIMREGC2_ADDR,
+        PCF50626_USIMREGC3_ADDR,
+        0,
+        0,0,0,0,
+
+        {
+            NV_FALSE,
+            PCF50626_USIMREGOUT_VOLTAGE_MIN_MV, 
+            PCF50626_USIMREGOUT_VOLTAGE_STEP_MV, 
+            PCF50626_USIMREGOUT_VOLTAGE_MAX_MV,
+            PCF50626_REQUESTVOLTAGE_USIMREG_MV
+        },
+        
+        PCF50626_USIMREGOUT_VOLTAGE_OFFSET_MV, 
+        PCF50626_USIMREGOUT_TURNON_TIME_MICROSEC + PCF50626_TURNON_DELAY_USIMREG_US,
+        PCF50626_USIMREGOUT_SWITCH_TIME_MICROSEC
+    },
+
+    //USB
+    {
+        PCF50626PmuSupply_USBREG,
+        PCF50626PmuSupply_VBAT,
+
+        PCF50626_USBREGC1_ADDR,
+        PCF50626_USBREGC2_ADDR,
+        PCF50626_USBREGC3_ADDR,
+        0,
+        0,0,0,0,
+
+        {
+            NV_FALSE,
+            PCF50626_USBREGOUT_VOLTAGE_MIN_MV, 
+            PCF50626_USBREGOUT_VOLTAGE_STEP_MV, 
+            PCF50626_USBREGOUT_VOLTAGE_MAX_MV,
+            PCF50626_REQUESTVOLTAGE_USBREG_MV
+        },
+        
+        PCF50626_USBREGOUT_VOLTAGE_OFFSET_MV, 
+        PCF50626_USBREGOUT_TURNON_TIME_MICROSEC + PCF50626_TURNON_DELAY_USBREG_US,
+        PCF50626_USBREGOUT_SWITCH_TIME_MICROSEC
+    },
+
+    //LC
+    {
+        PCF50626PmuSupply_LCREG,
+        PCF50626PmuSupply_VBAT,
+
+        PCF50626_LCREGC1_ADDR,
+        PCF50626_LCREGC2_ADDR,
+        PCF50626_LCREGC3_ADDR,
+        0,
+        0,0,0,0,
+
+        {
+            NV_FALSE,
+            PCF50626_LCREGOUT_VOLTAGE_MIN_MV, 
+            PCF50626_LCREGOUT_VOLTAGE_STEP_MV, 
+            PCF50626_LCREGOUT_VOLTAGE_MAX_MV,
+            PCF50626_REQUESTVOLTAGE_LCREG_MV
+        },
+        
+        PCF50626_LCREGOUT_VOLTAGE_OFFSET_MV, 
+        PCF50626_LCREGOUT_TURNON_TIME_MICROSEC + PCF50626_TURNON_DELAY_LCREG_US,
+        PCF50626_LCREGOUT_SWITCH_TIME_MICROSEC
+    },
+
+    //VBAT
+    {
+        PCF50626PmuSupply_VBAT,
+        PCF50626PmuSupply_Invalid,
+
+        0,0,0,0,
+        0,0,0,0,
+        
+        {NV_TRUE,0,0,0,0},
+        0,0,0
+    }
+};
+
+#define PCF50626SUPPLYINFOTABLESIZE NV_ARRAY_SIZE(pcf50626SupplyInfoTable)
+
+#endif //PCF50626_VOLTAGE_INFO_TABLE_HEADER
+
diff --git a/arch/arm/mach-tegra/odm_kit/adaptations/pmu/pcf50626/platform.c b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/pcf50626/platform.c
new file mode 100644
index 000000000000..dee9641eef7c
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/pcf50626/platform.c
@@ -0,0 +1,148 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include "pcf50626_batterycharger.h"
+#include "pcf50626_adc.h"
+#include "pcf50626_i2c.h"
+#include "pcf50626_reg.h"
+#include "ds2482_bridge.h"
+#include "ds2482_i2c.h"
+#include "nvodm_query_discovery.h"
+#include "nvodm_query.h"
+
+// implementations of platform related functions.
+
+#define OWI2CGUID   NV_ODM_GUID('o','w','i','2','c','_','d','s')
+#define BATTERYGUID NV_ODM_GUID('b','a','t','t','_','m','o','t')
+
+static NvBool ds2482Presented = NV_FALSE;
+
+/* Initliase all registers that related to battery charger */
+NvBool 
+Pcf50626BatteryChargerSetup(NvOdmPmuDeviceHandle hDevice)
+{
+    
+    NvOdmIoModule I2cModule = NvOdmIoModule_I2c;
+    NvU32  I2cInstance = 0;
+    NvU32  I2cAddress  = 0;
+    const NvOdmPeripheralConnectivity *pConnectivity = 
+                           NvOdmPeripheralGetGuid(OWI2CGUID);    
+    NV_ASSERT(hDevice);
+
+    if (pConnectivity != NULL) // OwI2c device is in database
+    {
+        NvU32 i = 0;        
+        for (i = 0; i < pConnectivity->NumAddress; i ++)
+        {
+            if (pConnectivity->AddressList[i].Interface == NvOdmIoModule_I2c_Pmu)
+            {
+                I2cModule   = NvOdmIoModule_I2c_Pmu;
+                I2cInstance = pConnectivity->AddressList[i].Instance;
+                I2cAddress  = pConnectivity->AddressList[i].Address;
+                break;
+            }
+        }
+        ds2482Presented = NV_TRUE;
+    }
+    else
+    {
+        ds2482Presented = NV_FALSE;
+    }
+
+    if (ds2482Presented == NV_TRUE)
+    {
+        // init GPIO8
+        if (!Pcf50626I2cWrite8(hDevice, PCF50626_GPIO8C1_ADDR, 0x0))
+            return NV_FALSE;
+
+        NvOdmOsWaitUS(50000);
+        
+        if (!Ds2482Setup(hDevice))
+            return NV_FALSE;
+
+        return NV_TRUE;
+    }
+
+    //TODO: add battery charger setup implementation here, base on HW.
+    // by default, simply return TRUE if nothing needed.
+    return NV_TRUE;
+}
+
+
+/* check CBC main batt presence */
+NvBool
+Pcf50626BatteryChargerCBCMainBatt(NvOdmPmuDeviceHandle hDevice, NvBool *status)
+{
+    const NvOdmPeripheralConnectivity *pConnectivity = 
+                           NvOdmPeripheralGetGuid(BATTERYGUID);
+    
+    NV_ASSERT(hDevice);
+
+    if (pConnectivity != NULL) // battery is in database
+    {
+        ///TODO: retrieve data from the database;
+        //Nothing needed on Concorde for now
+    }
+
+    if (ds2482Presented == NV_TRUE)
+    {
+        if (!Ds2482BatteryPresented(hDevice, status))
+           return NV_FALSE;
+    }
+    else
+    {
+        //TODO: add battery detection impelentation here. by default always return TRUE.  
+        *status = NV_TRUE;
+    }
+    
+    return NV_TRUE;
+}
+
+/* Calculate the battery temperature */
+NvU32 Pcf50626BatteryTemperature(NvU32 VBatSense, NvU32 VBatTemp)
+{
+    //TODO: implement the temperature algorithm based on the reading of Vbat sense and VBat temp.
+    // Pending approval.
+    return 0;
+}
+
+
+NvBool
+Ds2482BatteryPresented(NvOdmPmuDeviceHandle hDevice, NvBool *BattPresence)
+{
+    ///TODO: detect battery via ds2482 based on the battery spec.
+    ///Pending approval
+    return NV_TRUE;
+}
+
+
+
diff --git a/arch/arm/mach-tegra/odm_kit/adaptations/pmu/pmu_hal.c b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/pmu_hal.c
new file mode 100644
index 000000000000..ec62ac6c4c17
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/pmu_hal.c
@@ -0,0 +1,354 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include "nvcommon.h"
+#include "nvodm_pmu.h"
+#include "nvodm_query_discovery.h"
+#include "pmu_hal.h"
+#include "nvodm_services.h"
+#include "tps6586x/nvodm_pmu_tps6586x.h"
+#include "max8907b/max8907b.h"
+#include "max8907b/max8907b_rtc.h"
+#include "pcf50626/pcf50626.h"
+#include "pcf50626/pcf50626_rtc.h"
+
+static NvOdmPmuDevice*
+GetPmuInstance(NvOdmPmuDeviceHandle hDevice)
+{
+    static NvOdmPmuDevice Pmu;
+    static NvBool         first = NV_TRUE;
+
+    if (first)
+    {
+        NvOdmOsMemset(&Pmu, 0, sizeof(Pmu));
+        first = NV_FALSE;
+
+        if (NvOdmPeripheralGetGuid(NV_ODM_GUID('t','p','s','6','5','8','6','x')))
+        {
+            //  fill in HAL functions here.
+            Pmu.Hal = NV_TRUE;
+            Pmu.pfnSetup = Tps6586xSetup;
+            Pmu.pfnRelease = Tps6586xRelease;
+            Pmu.pfnGetCaps = Tps6586xGetCapabilities;
+            Pmu.pfnGetVoltage = Tps6586xGetVoltage;
+            Pmu.pfnSetVoltage = Tps6586xSetVoltage;
+            Pmu.pfnGetAcLineStatus = Tps6586xGetAcLineStatus;
+            Pmu.pfnGetBatteryStatus = Tps6586xGetBatteryStatus;
+            Pmu.pfnGetBatteryData = Tps6586xGetBatteryData;
+            Pmu.pfnGetBatteryFullLifeTime = Tps6586xGetBatteryFullLifeTime;
+            Pmu.pfnGetBatteryChemistry = Tps6586xGetBatteryChemistry;
+            Pmu.pfnSetChargingCurrent = Tps6586xSetChargingCurrent;
+            Pmu.pfnInterruptHandler = Tps6586xInterruptHandler;
+            Pmu.pfnReadRtc = Tps6586xReadRtc;
+            Pmu.pfnWriteRtc = Tps6586xWriteRtc;
+            Pmu.pfnIsRtcInitialized = Tps6586xIsRtcInitialized;
+        }
+        else if (NvOdmPeripheralGetGuid(NV_ODM_GUID('p','c','f','_','p','m','u','0')))
+        {
+            
+            Pmu.pfnSetup                  = Pcf50626Setup;
+            Pmu.pfnRelease                = Pcf50626Release;
+            Pmu.pfnGetCaps                = Pcf50626GetCapabilities;
+            Pmu.pfnGetVoltage             = Pcf50626GetVoltage;
+            Pmu.pfnSetVoltage             = Pcf50626SetVoltage;
+            Pmu.pfnGetAcLineStatus        = Pcf50626GetAcLineStatus;
+            Pmu.pfnGetBatteryStatus       = Pcf50626GetBatteryStatus;
+            Pmu.pfnGetBatteryData         = Pcf50626GetBatteryData;
+            Pmu.pfnGetBatteryFullLifeTime = Pcf50626GetBatteryFullLifeTime;
+            Pmu.pfnGetBatteryChemistry    = Pcf50626GetBatteryChemistry;
+            Pmu.pfnSetChargingCurrent     = Pcf50626SetChargingCurrent;
+            Pmu.pfnInterruptHandler       = Pcf50626InterruptHandler;
+            Pmu.pfnReadRtc                = Pcf50626RtcCountRead;
+            Pmu.pfnWriteRtc               = Pcf50626RtcCountWrite;
+            Pmu.pfnIsRtcInitialized       = Pcf50626IsRtcInitialized;
+            Pmu.pPrivate                  = NULL;            
+            Pmu.Hal                       = NV_TRUE;  
+            Pmu.Init                      = NV_FALSE;
+        }
+        else if (NvOdmPeripheralGetGuid(NV_ODM_GUID('m','a','x','8','9','0','7','b')))
+        {
+
+            Pmu.pfnSetup                  = Max8907bSetup;
+            Pmu.pfnRelease                = Max8907bRelease;
+            Pmu.pfnGetCaps                = Max8907bGetCapabilities;
+            Pmu.pfnGetVoltage             = Max8907bGetVoltage;
+            Pmu.pfnSetVoltage             = Max8907bSetVoltage;
+            Pmu.pfnGetAcLineStatus        = Max8907bGetAcLineStatus;
+            Pmu.pfnGetBatteryStatus       = Max8907bGetBatteryStatus;
+            Pmu.pfnGetBatteryData         = Max8907bGetBatteryData;
+            Pmu.pfnGetBatteryFullLifeTime = Max8907bGetBatteryFullLifeTime;
+            Pmu.pfnGetBatteryChemistry    = Max8907bGetBatteryChemistry;
+            Pmu.pfnSetChargingCurrent     = Max8907bSetChargingCurrent;
+            Pmu.pfnInterruptHandler       = Max8907bInterruptHandler;
+            Pmu.pfnReadRtc                = Max8907bRtcCountRead;
+            Pmu.pfnWriteRtc               = Max8907bRtcCountWrite;
+            Pmu.pfnIsRtcInitialized       = Max8907bIsRtcInitialized;
+            Pmu.pPrivate                  = NULL;
+            Pmu.Hal                       = NV_TRUE;  
+            Pmu.Init                      = NV_FALSE;
+        }
+    }
+
+    if (hDevice && Pmu.Hal)
+        return &Pmu;
+
+    return NULL;
+}
+
+NvBool
+NvOdmPmuDeviceOpen(NvOdmPmuDeviceHandle *hDevice)
+{
+    NvOdmPmuDevice *pmu = GetPmuInstance((NvOdmPmuDeviceHandle)1);
+
+    *hDevice = (NvOdmPmuDeviceHandle)0;
+
+    if (!pmu || !pmu->pfnSetup)
+        return NV_FALSE;
+
+    if (pmu->Init)
+    {
+        *hDevice = (NvOdmPmuDeviceHandle)1;
+        return NV_TRUE;
+    }
+
+    if (pmu->pfnSetup(pmu))
+    {
+        *hDevice = (NvOdmPmuDeviceHandle)1;
+        pmu->Init = NV_TRUE;
+        return NV_TRUE;
+    }
+
+    return NV_FALSE;
+}
+
+void NvOdmPmuDeviceClose(NvOdmPmuDeviceHandle hDevice)
+{
+    NvOdmPmuDevice *pmu = GetPmuInstance(hDevice);    
+
+    if (!pmu)
+        return;
+
+    if (pmu->pfnRelease)
+        pmu->pfnRelease(pmu);
+
+    pmu->Init = NV_FALSE;
+}
+
+void
+NvOdmPmuGetCapabilities(NvU32 vddId,
+                        NvOdmPmuVddRailCapabilities* pCapabilities)
+{
+    //  use a manual handle, since this function doesn't takea  handle
+    NvOdmPmuDevice* pmu = GetPmuInstance((NvOdmPmuDeviceHandle)1);
+
+    if (pmu && pmu->pfnGetCaps)
+        pmu->pfnGetCaps(vddId, pCapabilities);
+    else if (pCapabilities)
+    {
+        NvOdmOsMemset(pCapabilities, 0, sizeof(NvOdmPmuVddRailCapabilities));
+        pCapabilities->OdmProtected = NV_TRUE;
+    }
+}
+
+
+NvBool
+NvOdmPmuGetVoltage(NvOdmPmuDeviceHandle hDevice,
+                   NvU32 vddId,
+                   NvU32* pMilliVolts)
+{
+    NvOdmPmuDevice* pmu = GetPmuInstance(hDevice);
+
+    if (pmu && pmu->pfnGetVoltage)
+        return pmu->pfnGetVoltage(pmu, vddId, pMilliVolts);
+
+    return NV_TRUE;
+}
+
+NvBool
+NvOdmPmuSetVoltage(NvOdmPmuDeviceHandle hDevice,
+                   NvU32 VddId,
+                   NvU32 MilliVolts,
+                   NvU32* pSettleMicroSeconds)
+{
+    NvOdmPmuDevice *pmu = GetPmuInstance(hDevice);
+
+    if (pmu && pmu->pfnSetVoltage)
+    {
+        return pmu->pfnSetVoltage(pmu, VddId, MilliVolts, pSettleMicroSeconds);
+    }
+
+    if (pSettleMicroSeconds)
+        *pSettleMicroSeconds = 0;
+    return NV_TRUE;
+}
+
+
+NvBool 
+NvOdmPmuGetAcLineStatus(NvOdmPmuDeviceHandle hDevice, 
+                        NvOdmPmuAcLineStatus *pStatus)
+{
+    NvOdmPmuDevice* pmu = GetPmuInstance(hDevice);
+
+    if (pmu && pmu->pfnGetAcLineStatus)
+        return pmu->pfnGetAcLineStatus(pmu, pStatus);
+
+    return NV_TRUE;
+}
+
+
+NvBool 
+NvOdmPmuGetBatteryStatus(NvOdmPmuDeviceHandle hDevice, 
+                         NvOdmPmuBatteryInstance BatteryInst,
+                         NvU8 *pStatus)
+{
+    NvOdmPmuDevice *pmu = GetPmuInstance(hDevice);
+
+    if (pmu && pmu->pfnGetBatteryStatus)
+        return pmu->pfnGetBatteryStatus(pmu, BatteryInst, pStatus);
+
+    return NV_TRUE;
+}
+
+NvBool
+NvOdmPmuGetBatteryData(NvOdmPmuDeviceHandle hDevice, 
+                       NvOdmPmuBatteryInstance BatteryInst,
+                       NvOdmPmuBatteryData *pData)
+{
+    NvOdmPmuDevice *pmu = GetPmuInstance(hDevice);
+
+    if (pmu && pmu->pfnGetBatteryData)
+        return pmu->pfnGetBatteryData(pmu, BatteryInst, pData);
+
+    pData->batteryLifePercent = NVODM_BATTERY_DATA_UNKNOWN;
+    pData->batteryLifeTime = NVODM_BATTERY_DATA_UNKNOWN;
+    pData->batteryVoltage = NVODM_BATTERY_DATA_UNKNOWN;
+    pData->batteryCurrent = NVODM_BATTERY_DATA_UNKNOWN;
+    pData->batteryAverageCurrent = NVODM_BATTERY_DATA_UNKNOWN;
+    pData->batteryAverageInterval = NVODM_BATTERY_DATA_UNKNOWN;
+    pData->batteryMahConsumed = NVODM_BATTERY_DATA_UNKNOWN;
+    pData->batteryTemperature = NVODM_BATTERY_DATA_UNKNOWN;
+
+    return NV_TRUE;
+}
+
+
+void
+NvOdmPmuGetBatteryFullLifeTime(NvOdmPmuDeviceHandle hDevice, 
+                               NvOdmPmuBatteryInstance BatteryInst,
+                               NvU32 *pLifeTime)
+{
+    NvOdmPmuDevice *pmu = GetPmuInstance(hDevice);
+
+    if (pmu && pmu->pfnGetBatteryFullLifeTime)
+        pmu->pfnGetBatteryFullLifeTime(pmu, BatteryInst, pLifeTime);
+
+    else
+    {
+        if (pLifeTime)
+            *pLifeTime = NVODM_BATTERY_DATA_UNKNOWN;
+    }
+}
+
+
+void
+NvOdmPmuGetBatteryChemistry(NvOdmPmuDeviceHandle hDevice, 
+                            NvOdmPmuBatteryInstance BatteryInst,
+                            NvOdmPmuBatteryChemistry *pChemistry)
+{
+    NvOdmPmuDevice *pmu = GetPmuInstance(hDevice);
+
+    if (pmu && pmu->pfnGetBatteryChemistry)
+        pmu->pfnGetBatteryChemistry(pmu, BatteryInst, pChemistry);
+    else
+    {
+        if (pChemistry)
+            *pChemistry = NVODM_BATTERY_DATA_UNKNOWN;
+    }
+}
+
+NvBool 
+NvOdmPmuSetChargingCurrent(NvOdmPmuDeviceHandle hDevice, 
+                           NvOdmPmuChargingPath ChargingPath, 
+                           NvU32 ChargingCurrentLimitMa,
+                           NvOdmUsbChargerType ChargerType)
+{
+    NvOdmPmuDevice *pmu = GetPmuInstance(hDevice);
+
+    if (pmu && pmu->pfnSetChargingCurrent)
+        return pmu->pfnSetChargingCurrent(pmu, ChargingPath, ChargingCurrentLimitMa, ChargerType);
+
+    return NV_TRUE;
+}
+
+
+void NvOdmPmuInterruptHandler(NvOdmPmuDeviceHandle hDevice)
+{
+    NvOdmPmuDevice *pmu = GetPmuInstance(hDevice);
+
+    if (pmu && pmu->pfnInterruptHandler)
+        pmu->pfnInterruptHandler(pmu);
+}
+
+NvBool NvOdmPmuReadRtc(
+    NvOdmPmuDeviceHandle  hDevice,
+    NvU32 *Count)
+{
+    NvOdmPmuDevice *pmu = GetPmuInstance(hDevice);
+
+    if (pmu && pmu->pfnReadRtc)
+        return pmu->pfnReadRtc(pmu, Count);
+    return NV_FALSE;
+}
+
+
+NvBool NvOdmPmuWriteRtc(
+    NvOdmPmuDeviceHandle  hDevice,
+    NvU32 Count)
+{
+    NvOdmPmuDevice *pmu = GetPmuInstance(hDevice);
+
+    if (pmu && pmu->pfnWriteRtc)
+        return pmu->pfnWriteRtc(pmu, Count);
+    return NV_FALSE;
+}
+
+NvBool
+NvOdmPmuIsRtcInitialized(NvOdmPmuDeviceHandle hDevice)
+{
+    NvOdmPmuDevice *pmu = GetPmuInstance(hDevice);
+
+    if (pmu && pmu->pfnIsRtcInitialized)
+        return pmu->pfnIsRtcInitialized(pmu);
+        
+    return NV_FALSE;
+}
+
diff --git a/arch/arm/mach-tegra/odm_kit/adaptations/pmu/pmu_hal.h b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/pmu_hal.h
new file mode 100644
index 000000000000..05cdea828a20
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/pmu_hal.h
@@ -0,0 +1,93 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/** 
+ * @file
+ * <b>NVIDIA Tegra ODM Kit:
+ *         Abstraction layer stub for audio codec adaptations</b>
+ */
+
+#ifndef INCLUDED_NVODM_PMU_ADAPTATION_HAL_H
+#define INCLUDED_NVODM_PMU_ADAPTATION_HAL_H
+
+#include "nvcommon.h"
+#include "nvodm_pmu.h"
+#include "nvodm_services.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+typedef NvBool (*pfnPmuSetup)(NvOdmPmuDeviceHandle);
+typedef void   (*pfnPmuRelease)(NvOdmPmuDeviceHandle);
+typedef void   (*pfnPmuGetCaps)(NvU32, NvOdmPmuVddRailCapabilities*);
+typedef NvBool (*pfnPmuGetVoltage)(NvOdmPmuDeviceHandle, NvU32, NvU32*);
+typedef NvBool (*pfnPmuSetVoltage)(NvOdmPmuDeviceHandle, NvU32, NvU32, NvU32*);
+typedef NvBool (*pfnPmuGetAcLineStatus)(NvOdmPmuDeviceHandle, NvOdmPmuAcLineStatus*);
+typedef NvBool (*pfnPmuGetBatteryStatus)(NvOdmPmuDeviceHandle, NvOdmPmuBatteryInstance, NvU8*);
+typedef NvBool (*pfnPmuGetBatteryData)(NvOdmPmuDeviceHandle, NvOdmPmuBatteryInstance, NvOdmPmuBatteryData*);
+typedef void   (*pfnPmuGetBatteryFullLifeTime)(NvOdmPmuDeviceHandle, NvOdmPmuBatteryInstance, NvU32*);
+typedef void   (*pfnPmuGetBatteryChemistry)(NvOdmPmuDeviceHandle, NvOdmPmuBatteryInstance, NvOdmPmuBatteryChemistry*);
+typedef NvBool (*pfnPmuSetChargingCurrent)(NvOdmPmuDeviceHandle, NvOdmPmuChargingPath, NvU32, NvOdmUsbChargerType);
+typedef void   (*pfnPmuInterruptHandler)(NvOdmPmuDeviceHandle);
+typedef NvBool (*pfnPmuReadRtc)(NvOdmPmuDeviceHandle, NvU32*);
+typedef NvBool (*pfnPmuWriteRtc)(NvOdmPmuDeviceHandle, NvU32);
+typedef NvBool (*pfnPmuIsRtcInitialized)(NvOdmPmuDeviceHandle);
+
+typedef struct NvOdmPmuDeviceRec
+{ 
+    pfnPmuSetup                  pfnSetup;
+    pfnPmuRelease                pfnRelease;
+    pfnPmuGetCaps                pfnGetCaps;
+    pfnPmuGetVoltage             pfnGetVoltage;
+    pfnPmuSetVoltage             pfnSetVoltage;
+    pfnPmuGetAcLineStatus        pfnGetAcLineStatus;
+    pfnPmuGetBatteryStatus       pfnGetBatteryStatus;
+    pfnPmuGetBatteryData         pfnGetBatteryData;
+    pfnPmuGetBatteryFullLifeTime pfnGetBatteryFullLifeTime;
+    pfnPmuGetBatteryChemistry    pfnGetBatteryChemistry;
+    pfnPmuSetChargingCurrent     pfnSetChargingCurrent;
+    pfnPmuInterruptHandler       pfnInterruptHandler;
+    pfnPmuReadRtc                pfnReadRtc;
+    pfnPmuWriteRtc               pfnWriteRtc;
+    pfnPmuIsRtcInitialized       pfnIsRtcInitialized;
+    void                        *pPrivate;
+    NvBool                       Hal;
+    NvBool                       Init;
+} NvOdmPmuDevice;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/arch/arm/mach-tegra/odm_kit/adaptations/pmu/tps6586x/Makefile b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/tps6586x/Makefile
new file mode 100644
index 000000000000..3b4770addf96
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/tps6586x/Makefile
@@ -0,0 +1,18 @@
+ccflags-y += -DNV_IS_AVP=0
+ccflags-y += -DNV_OAL=0
+ccflags-y += -DNV_USE_FUSE_CLOCK_ENABLE=0
+ifeq ($(CONFIG_MACH_TEGRA_GENERIC_DEBUG),y)
+ccflags-y += -DNV_DEBUG=1
+else
+ccflags-y += -DNV_DEBUG=0
+endif
+
+ccflags-y += -Iarch/arm/mach-tegra/odm_kit/adaptations/pmu
+ccflags-y += -Iarch/arm/mach-tegra/odm_kit/adaptations/pmu/tps6586x
+
+obj-y += nvodm_pmu_tps6586x.o
+obj-y += nvodm_pmu_tps6586x_adc.o
+obj-y += nvodm_pmu_tps6586x_batterycharger.o
+obj-y += nvodm_pmu_tps6586x_i2c.o
+obj-y += nvodm_pmu_tps6586x_interrupt.o
+obj-y += nvodm_pmu_tps6586x_rtc.o
diff --git a/arch/arm/mach-tegra/odm_kit/adaptations/pmu/tps6586x/nvodm_pmu_tps6586x.c b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/tps6586x/nvodm_pmu_tps6586x.c
new file mode 100644
index 000000000000..197a2c227e1d
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/tps6586x/nvodm_pmu_tps6586x.c
@@ -0,0 +1,2036 @@
+
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include "nvodm_query_discovery.h"
+#include "nvodm_query.h"
+#include "nvodm_query_gpio.h"
+#include "nvodm_pmu_tps6586x_i2c.h"
+#include "nvodm_pmu_tps6586x_interrupt.h"
+#include "nvodm_pmu_tps6586x_batterycharger.h"
+#include "nvodm_pmu_tps6586x_adc.h"
+#include "nvodm_pmu_tps6586x_rtc.h"
+#include "pmu_hal.h"
+
+/**************************************************************************
+ * NOTE:
+ *  + Please search "FIXME" and then change the code according to your tps6586x fuse
+ *      * each LDO's voltage range and default value
+ *      * each SM's voltage range and default value
+ *      * Interrupt Masks
+ *      + Battery settings
+ **************************************************************************/
+
+/**************************************************************************
+ * TPS6586x has two sets of power supliers:
+ * + 3 DC/DC converters: DCD0/1/2
+ * + 11 Regulators: LDO0-9 and RTC_OUT
+ * Besides that, TPS6586x has 
+ * + 2 sets drivers for LED or other open drain outputs
+ * + 1 dedicated driver for keyboard backlight LED
+ * + 1 dedicated driver for external vibrator motor
+ * + 1 dedicated driver for white LED(SM3)
+ **************************************************************************/
+
+NvBool pmuPresented;
+NvBool battPresence;
+NvBool pmuInterruptSupported;
+TPS6586xStatus pmuStatus;
+NvOdmPmuDeviceTPS *hPmu;
+
+
+// threshold for battery status. need to fine tune based on battery/system characterisation
+#define NVODM_BATTERY_FULL_VOLTAGE_MV      4200
+#define NVODM_BATTERY_HIGH_VOLTAGE_MV      3900
+#define NVODM_BATTERY_LOW_VOLTAGE_MV       3300
+#define NVODM_BATTERY_CRITICAL_VOLTAGE_MV  3100
+
+#define DUMB_CHARGER_LIMIT_MA      250
+#define DEDICATED_CHARGER_LIMIT_MA 1000   // 1000mA for dedicated charger
+
+#define T_START_TIME  210
+#define K_RAMP        7
+
+/* 
+  Only 4 options for charger current; Page36
+  According to TPS658x spec, the charge current = scaling factor / R_ISET.
+  From the schematic, R_ISET shows "1K". So the charge current = scaling factor.
+  Because the min value of the scaling factor is 0.25 and the R_ISET is fixed, 
+  the min charging current = 0.25 / 1  = 0.25 A = 250 mA.
+  Thus, it will only support 1000mA, 750mA, 500mA, 250mA.
+   TODO: In future, we need to change to the actual R_IST value
+*/
+#define R_IST                     1000
+#define MAX_CHARGING_CURRENT      1000000/R_IST
+#define L1_CHARGING_CURRENT        750
+#define L2_CHARGING_CURRENT        500
+#define L3_CHARGING_CURRENT        250
+
+/* Valtage tables for LDOs */
+/* FIXME: Modify those tables according to your fuse */
+static const NvU32 VLDOx[] = {1250, 1500, 1800, 2500, 2700, 2850, 3100, 3300};
+static const NvU32 VLDO2[] = { 725,  750,  775,  800,  825,  850,  875,  900,
+                               925,  950,  975, 1000, 1025, 1050, 1075, 1100,
+                              1125, 1150, 1175, 1200, 1225, 1250, 1275, 1300,
+                              1325, 1350, 1375, 1400, 1425, 1450, 1475, 1500};
+/* FIXME tps65860 only */
+static const NvU32 VLDO4[] = {1700, 1725, 1750, 1775, 1800, 1825, 1850, 1875,
+                              1900, 1925, 1950, 1975, 2000, 2000, 2000, 2000,
+                              2000, 2000, 2000, 2000, 2000, 2000, 2000, 2000,
+                              2000, 2000, 2000, 2000, 2000, 2000, 2000, 2000};
+
+typedef NvU32  (*TPS6586xPmuVoltageFunc)(const NvU32 bits);
+typedef NvBool (*TPS6586xPmuRailCtrlFunc)(const NvU32 rail, NvBool enable);
+
+typedef struct {
+    NvU8    addr;
+    NvU8    start;
+    NvU8    bits;
+    NvU8    flag;                           /*!< see each settings */
+} TPS6586xPmuRegisterInfo;
+
+typedef struct TPS6586xPmuSupplyInfoRec
+{
+    TPS6586xPmuSupply supply;
+
+    TPS6586xPmuRegisterInfo supplyRegInfo;  /*!< Register info to set/get supply voltage */
+    TPS6586xPmuRegisterInfo ctrlRegInfo;    /*!< Register info to enable/disable supply, flag indicates another addr */
+    TPS6586xPmuVoltageFunc getVoltage;      /*!< Func to convert register bits to real voltage */
+    TPS6586xPmuVoltageFunc setVoltage;      /*!< Func to convert real voltage to register bits */
+    TPS6586xPmuRailCtrlFunc railControl;    /*!< Func to enable/disable output for each rail */
+    NvU8 Gpio;                              /*!< GPIO pin used to enable/disable external supplies */
+
+    NvOdmPmuVddRailCapabilities cap;
+
+    
+} TPS6586xPmuSupplyInfo;
+
+static NvU32 TPS6586xPmuVoltageGetSM0(const NvU32 bits);
+static NvU32 TPS6586xPmuVoltageGetSM1(const NvU32 bits);
+static NvU32 TPS6586xPmuVoltageGetSM2(const NvU32 bits);
+static NvU32 TPS6586xPmuVoltageGetVLDOx(const NvU32 bits);
+static NvU32 TPS6586xPmuVoltageGetVLDO1(const NvU32 bits);
+static NvU32 TPS6586xPmuVoltageGetVLDO2(const NvU32 bits);
+static NvU32 TPS6586xPmuVoltageGetVLDO4(const NvU32 bits);
+
+static NvU32 TPS6586xPmuVoltageSetSM0(const NvU32 bits);
+static NvU32 TPS6586xPmuVoltageSetSM1(const NvU32 bits);
+static NvU32 TPS6586xPmuVoltageSetSM2(const NvU32 bits);
+static NvU32 TPS6586xPmuVoltageSetVLDOx(const NvU32 bits);
+static NvU32 TPS6586xPmuVoltageSetVLDO1(const NvU32 bits);
+static NvU32 TPS6586xPmuVoltageSetVLDO2(const NvU32 bits);
+static NvU32 TPS6586xPmuVoltageSetVLDO4(const NvU32 bits);
+
+/* FIXME: Change getVoltage/setVoltage according to your fuse */
+static const TPS6586xPmuSupplyInfo tps6586xSupplyInfoTable[] =
+{
+    {
+        TPS6586xPmuSupply_Invalid,
+        {TPS6586x_RFF_INVALID, 0, 0, 0},
+        {TPS6586x_RFF_INVALID, 0, 0, 0},
+        NULL, NULL, NULL,
+        TPS6586x_RFF_INVALID,
+        {NV_TRUE,0,0,0,0},
+    },
+
+    //DCD0
+    {
+        TPS6586xPmuSupply_DCD0,
+
+        {TPS6586x_R26_SM0V1, 0, 5, 0},   
+        {TPS6586x_R10_SUPPLYENA, 1, 1, TPS6586x_R11_SUPPLYENB},   
+        TPS6586xPmuVoltageGetSM0,
+        TPS6586xPmuVoltageSetSM0,
+        NULL,
+        TPS6586x_RFF_INVALID,
+
+        {
+            NV_FALSE,
+#if defined(CONFIG_TEGRA_ODM_HARMONY)
+            625, 25, 2700, 1200 
+#else
+            900, 25, 1200, 1200 
+#endif
+        },
+    },
+
+    //DCD1
+    {
+        TPS6586xPmuSupply_DCD1,
+
+        {TPS6586x_R23_SM1V1, 0, 5, 0},
+        {TPS6586x_R10_SUPPLYENA, 0, 1, TPS6586x_R11_SUPPLYENB},
+        TPS6586xPmuVoltageGetSM1,
+        TPS6586xPmuVoltageSetSM1,
+        NULL,
+        TPS6586x_RFF_INVALID,
+        {
+            NV_FALSE,
+#if defined(CONFIG_TEGRA_ODM_HARMONY)
+            625, 25, 2700, 1000
+#else
+            1800, 0, 1800, 1800 
+#endif
+        },
+    },
+
+    //DCD2
+    {
+        TPS6586xPmuSupply_DCD2,
+
+        {TPS6586x_R42_SUPPLYV2, 0, 5, 0},   
+        {TPS6586x_R12_SUPPLYENC, 7, 1, TPS6586x_R13_SUPPLYEND},   
+        TPS6586xPmuVoltageGetSM2,
+        TPS6586xPmuVoltageSetSM2,
+        NULL,
+        TPS6586x_RFF_INVALID,
+        {
+            NV_FALSE,
+#if defined(CONFIG_TEGRA_ODM_HARMONY)
+            3000, 50, 4550, 3700
+#else
+            3000, 50, 4550, 3250  // fixme
+#endif
+        },
+    },
+
+    // LD00
+    {
+        TPS6586xPmuSupply_LDO0,
+        
+        {TPS6586x_R41_SUPPLYV1, 5, 3, 0},
+        {TPS6586x_R12_SUPPLYENC, 0, 1, TPS6586x_R13_SUPPLYEND},
+        TPS6586xPmuVoltageGetVLDOx,
+        TPS6586xPmuVoltageSetVLDOx,
+        NULL,
+        TPS6586x_RFF_INVALID,
+   
+        {
+            NV_FALSE,
+#if defined(CONFIG_TEGRA_ODM_HARMONY)
+            1250, 25, 3350, 3300
+#else
+            2800, 0, 2800, 2800
+#endif
+        },
+    },
+
+    // LD01 - V-1V2
+    {
+        TPS6586xPmuSupply_LDO1,
+        
+        {TPS6586x_R41_SUPPLYV1, 0, 5, 0},
+        {TPS6586x_R12_SUPPLYENC, 1, 1, TPS6586x_R13_SUPPLYEND},
+        TPS6586xPmuVoltageGetVLDO1,
+        TPS6586xPmuVoltageSetVLDO1,
+        NULL,
+        TPS6586x_RFF_INVALID,
+        {
+            NV_FALSE,
+#if defined(CONFIG_TEGRA_ODM_HARMONY)
+            725, 25, 1500, 1100
+#else
+            1200, 0, 1200, 1200
+#endif
+        },
+    },
+
+    //LD02 - V-RTC
+    {
+        TPS6586xPmuSupply_LDO2,
+        
+#if defined(CONFIG_TEGRA_ODM_HARMONY)
+        {TPS6586x_R2F_LDO2BV1, 0, 5, 0},
+#else
+        {TPS6586x_R29_LDO2AV1, 0, 5, 0},
+#endif
+        {TPS6586x_R10_SUPPLYENA, 2, 2, TPS6586x_R11_SUPPLYENB},
+        TPS6586xPmuVoltageGetVLDO2,
+        TPS6586xPmuVoltageSetVLDO2,
+        NULL,
+        TPS6586x_RFF_INVALID,
+   
+        {
+            NV_FALSE,
+#if defined(CONFIG_TEGRA_ODM_HARMONY)
+            725, 25, 1500, 1200 
+#else
+            900, 25, 1200, 1200 
+#endif
+        },
+    },
+
+    //LDO3
+    {
+        TPS6586xPmuSupply_LDO3,
+
+        {TPS6586x_R44_SUPPLYV4, 0, 3, 0},
+        {TPS6586x_R12_SUPPLYENC, 2, 1, TPS6586x_R13_SUPPLYEND},
+        TPS6586xPmuVoltageGetVLDOx,
+        TPS6586xPmuVoltageSetVLDOx,
+        NULL,
+        TPS6586x_RFF_INVALID,
+
+        {
+            NV_FALSE,
+#if defined(CONFIG_TEGRA_ODM_HARMONY)
+            1250, 25, 3350, 3300
+#else
+            1800, 0, 1800, 1800
+#endif
+        },
+    },
+
+    //LDO4
+    {
+        TPS6586xPmuSupply_LDO4,
+
+        {TPS6586x_R32_LDO4V1, 0, 5, 0},
+        {TPS6586x_R12_SUPPLYENC, 3, 1, TPS6586x_R13_SUPPLYEND},
+        TPS6586xPmuVoltageGetVLDO4,
+        TPS6586xPmuVoltageSetVLDO4,
+        NULL,
+        TPS6586x_RFF_INVALID,
+
+        {
+            NV_FALSE, 
+#if defined(CONFIG_TEGRA_ODM_HARMONY)
+            1700, 25, 2000, 1800
+#else
+            1800, 0, 1800, 1800
+#endif
+        },
+    },        
+
+    //LDO5
+    {
+        TPS6586xPmuSupply_LDO5,
+
+        {TPS6586x_R46_SUPPLYV6, 0, 3, 0},
+        {TPS6586x_R14_SUPPLYENE, 6, 1, TPS6586x_RFF_INVALID},
+        TPS6586xPmuVoltageGetVLDOx,
+        TPS6586xPmuVoltageSetVLDOx,
+        NULL,
+        TPS6586x_RFF_INVALID,
+
+        {
+            NV_FALSE,
+#if defined(CONFIG_TEGRA_ODM_HARMONY)
+            1250, 25, 3350, 2850
+#else
+            2800, 0, 2800, 2800
+#endif
+        }, 
+    },
+
+    //LDO6 - V-3V3 USB
+    {
+        TPS6586xPmuSupply_LDO6,
+        
+        {TPS6586x_R43_SUPPLYV3, 0, 3, 0},
+        {TPS6586x_R12_SUPPLYENC, 4, 1, TPS6586x_R13_SUPPLYEND},
+        TPS6586xPmuVoltageGetVLDOx,
+        TPS6586xPmuVoltageSetVLDOx,
+        NULL,
+        TPS6586x_RFF_INVALID,
+
+        {
+            NV_FALSE,
+#if defined(CONFIG_TEGRA_ODM_HARMONY)
+            1250, 25, 3350, 2850
+#else
+            3300, 0, 3300, 3300
+#endif
+        }, 
+    },
+
+    //LDO7 - V-SDIO
+    {
+        TPS6586xPmuSupply_LDO7,
+
+        {TPS6586x_R43_SUPPLYV3, 3, 3, 0},
+        {TPS6586x_R12_SUPPLYENC, 5, 1, TPS6586x_R13_SUPPLYEND},
+        TPS6586xPmuVoltageGetVLDOx,
+        TPS6586xPmuVoltageSetVLDOx,
+        NULL,
+        TPS6586x_RFF_INVALID,
+
+        {
+            NV_FALSE,
+#if defined(CONFIG_TEGRA_ODM_HARMONY)
+            1250, 25, 3350, 3300
+#else
+            2800, 0, 2800, 2800
+#endif
+        },
+    },
+
+    //LDO8 - V-2V8 
+    {
+        TPS6586xPmuSupply_LDO8,
+
+        {TPS6586x_R42_SUPPLYV2, 5, 3, 0},
+        {TPS6586x_R12_SUPPLYENC, 6, 1, TPS6586x_R13_SUPPLYEND},
+        TPS6586xPmuVoltageGetVLDOx,
+        TPS6586xPmuVoltageSetVLDOx,
+        NULL,
+        TPS6586x_RFF_INVALID,
+
+        {
+            NV_FALSE,
+#if defined(CONFIG_TEGRA_ODM_HARMONY)
+            1250, 25, 3350, 1800
+#else
+            2800, 0, 2800, 2800
+#endif
+        },
+    },
+
+    //LDO9
+    {
+        TPS6586xPmuSupply_LDO9,            
+        
+        {TPS6586x_R46_SUPPLYV6, 3, 3, 0},
+        {TPS6586x_R14_SUPPLYENE, 7, 1, TPS6586x_RFF_INVALID},
+        TPS6586xPmuVoltageGetVLDOx,
+        TPS6586xPmuVoltageSetVLDOx,
+        NULL,
+        TPS6586x_RFF_INVALID,
+
+        {
+            NV_FALSE,
+#if defined(CONFIG_TEGRA_ODM_HARMONY)
+            1250, 25, 3350, 2850
+#else
+            2500, 0, 2500, 2500,
+#endif
+        },
+    },
+
+    //RTC_OUT
+    {
+        TPS6586xPmuSupply_RTC_OUT,
+
+        {TPS6586x_R44_SUPPLYV4, 3, 3, 0},
+        {TPS6586x_RFF_INVALID, 0, 0, TPS6586x_RFF_INVALID},
+        TPS6586xPmuVoltageGetVLDOx,
+        TPS6586xPmuVoltageSetVLDOx,
+        NULL,
+        TPS6586x_RFF_INVALID,
+
+        {
+            NV_FALSE,
+#if defined(CONFIG_TEGRA_ODM_HARMONY)
+            1250, 25, 3350, 3300
+#else
+            2500, 0, 2500, 2500
+#endif
+        },
+    },
+
+
+    //RED1
+    {
+        TPS6586xPmuSupply_RED1,
+
+        {TPS6586x_R51_RGB1RED, 0, 5, 0},   
+        {TPS6586x_R52_RGB1GREEN, 7, 1, TPS6586x_RFF_INVALID},
+        NULL, NULL, NULL,
+        TPS6586x_RFF_INVALID,
+
+        {
+            NV_FALSE,
+            0, 1, 0x1f, 0
+        },
+    },
+
+    //GREEN1
+    {
+        TPS6586xPmuSupply_GREEN1,
+
+        {TPS6586x_R52_RGB1GREEN, 0, 5, 0},   
+        {TPS6586x_R52_RGB1GREEN, 7, 1, TPS6586x_RFF_INVALID},
+        NULL, NULL, NULL,
+        TPS6586x_RFF_INVALID,
+
+        {
+            NV_FALSE,
+            0, 1, 0x1f, 0
+        },
+    },
+
+    //BLUE1
+    {
+        TPS6586xPmuSupply_BLUE1,
+
+        {TPS6586x_R53_RGB1BLUE, 0, 5, 0},   
+        {TPS6586x_R52_RGB1GREEN, 7, 1, TPS6586x_RFF_INVALID},
+        NULL, NULL, NULL,
+        TPS6586x_RFF_INVALID,
+
+        {
+            NV_FALSE,
+            0, 1, 0x1f, 0
+        },
+    },
+
+    //RED2
+    {
+        TPS6586xPmuSupply_RED2,
+
+        {TPS6586x_R54_RGB2RED, 0, 5, 0},   
+        {TPS6586x_R55_RGB2GREEN, 7, 1, TPS6586x_RFF_INVALID},
+        NULL, NULL, NULL,
+        TPS6586x_RFF_INVALID,
+
+        {
+            NV_FALSE,
+            0, 1, 0x1f, 0
+        },
+    },
+
+    //GREEN2
+    {
+        TPS6586xPmuSupply_GREEN2,
+
+        {TPS6586x_R55_RGB2GREEN, 0, 5, 0},   
+        {TPS6586x_R55_RGB2GREEN, 7, 1, TPS6586x_RFF_INVALID},
+        NULL, NULL, NULL,
+        TPS6586x_RFF_INVALID,
+
+        {
+            NV_FALSE,
+            0, 1, 0x1f, 0
+        },
+    },
+ 
+    //BLUE2
+    {
+        TPS6586xPmuSupply_BLUE2,
+
+        {TPS6586x_R56_RGB2BLUE, 0, 5, 0},
+        {TPS6586x_R55_RGB2GREEN, 7, 1, TPS6586x_RFF_INVALID},
+        NULL, NULL, NULL,
+        TPS6586x_RFF_INVALID,
+
+        {
+            NV_FALSE,
+            0, 1, 0x1f, 0
+        },
+    },
+
+    //LED_PWM
+    {
+        TPS6586xPmuSupply_LED_PWM,
+
+        {TPS6586x_RFF_INVALID, 0, 0, 0},   /* FIXME: how to get the output */
+        {TPS6586x_RFF_INVALID, 0, 0, TPS6586x_RFF_INVALID},
+        NULL, NULL, NULL,
+        TPS6586x_RFF_INVALID,
+
+        {
+            NV_TRUE,
+            0, 0, 0, 0
+        },
+    },
+
+    //PWM
+    {
+        TPS6586xPmuSupply_PWM,
+
+        {TPS6586x_RFF_INVALID, 0, 0, 0},   /* FIXME: how to get the output */
+        {TPS6586x_RFF_INVALID, 0, 0, TPS6586x_RFF_INVALID},
+        NULL, NULL, NULL,
+        TPS6586x_RFF_INVALID,
+
+        {
+            NV_TRUE,
+            0, 0, 0, 0
+        },
+    },
+
+    //White LED(SM3)
+    {
+        TPS6586xPmuSupply_WHITE_LED,
+
+        {TPS6586x_R58_SM3_SET1, 0, 3, 0},   
+        {TPS6586x_R57_SM3_SET0, 0, 8, TPS6586x_RFF_INVALID}, 
+        NULL, NULL, NULL,
+        TPS6586x_RFF_INVALID,
+
+        {
+            NV_FALSE,
+            25000, 0, 25000, 0
+        },
+    },
+#if defined(CONFIG_TEGRA_ODM_HARMONY)
+    {
+        TPS6586xPmuSupply_SoC,
+
+        {TPS6586x_RFF_INVALID, 0, 0, 0},
+        {TPS6586x_R14_SUPPLYENE, 3, 1, TPS6586x_RFF_INVALID},
+        NULL, NULL, NULL,
+        TPS6586x_RFF_INVALID,
+        {NV_FALSE,0,0,0,0},
+    },
+    // External Supplies
+
+    {
+        Ext_TPS62290PmuSupply_BUCK,
+
+        {TPS6586x_RFF_INVALID, 0, 0, 0},
+        {TPS6586x_RFF_INVALID, 0, 0, 0},
+        NULL, NULL, NULL,
+        3,
+        {NV_FALSE,0,1050,1050,1050},
+    },
+
+    {
+        Ext_TPS72012PmuSupply_LDO,
+
+        {TPS6586x_RFF_INVALID, 0, 0, 0},
+        {TPS6586x_RFF_INVALID, 0, 0, 0},
+        NULL, NULL, NULL,
+        2,
+        {NV_FALSE,0,1200,1200,1200},
+    },
+
+    {
+        Ext_TPS74201PmuSupply_LDO,
+
+        {TPS6586x_RFF_INVALID, 0, 0, 0},
+        {TPS6586x_RFF_INVALID, 0, 0, 0},
+        NULL, NULL, NULL,
+        1,
+        {NV_FALSE,0,1500,1500,1500},
+    },
+    {
+        Ext_TPS2051BPmuSupply_VDDIO_VID,
+
+        {TPS6586x_RFF_INVALID, 0, 0, 0},
+        {TPS6586x_RFF_INVALID, 0, 0, 0},
+        NULL, NULL, NULL,
+        TPS6586x_RFF_INVALID,
+        {NV_FALSE,0,5000,5000,5000},
+    },
+
+    {
+        Ext_SWITCHPmuSupply_VDDIO_SD,
+
+        {TPS6586x_RFF_INVALID, 0, 0, 0},
+        {TPS6586x_RFF_INVALID, 0, 0, 0},
+        NULL, NULL, NULL,
+        TPS6586x_RFF_INVALID,
+        {NV_FALSE,0,3300,3300,3300},
+    },
+
+    {
+        Ext_SWITCHPmuSupply_VDDIO_SDMMC,
+
+        {TPS6586x_RFF_INVALID, 0, 0, 0},
+        {TPS6586x_RFF_INVALID, 0, 0, 0},
+        NULL, NULL, NULL,
+        TPS6586x_RFF_INVALID,
+        {NV_FALSE,0,3300,3300,3300},
+    },
+    {
+        Ext_SWITCHPmuSupply_VDD_BL,
+
+        {TPS6586x_RFF_INVALID, 0, 0, 0},
+        {TPS6586x_RFF_INVALID, 0, 0, 0},
+        NULL, NULL, NULL,
+        TPS6586x_RFF_INVALID,
+        {NV_FALSE,0,11100,11100,11100},
+    },
+
+    {
+        Ext_SWITCHPmuSupply_VDD_PNL,
+
+        {TPS6586x_RFF_INVALID, 0, 0, 0},
+        {TPS6586x_R14_SUPPLYENE, 3, 1, TPS6586x_RFF_INVALID},
+        NULL, NULL, NULL,
+        TPS6586x_RFF_INVALID,
+        {NV_FALSE,0,3300,3300,3300},
+    }
+#endif
+};
+
+static NvU32 TPS6586xPmuVoltageGetSM0(const NvU32 bits)
+{
+    NV_ASSERT(bits <= 0x1F);
+
+    return (725 + bits * 25);
+}
+
+static NvU32 TPS6586xPmuVoltageGetSM1(const NvU32 bits)
+{
+    NV_ASSERT(bits <= 0x1F);
+
+#if defined (CONFIG_TEGRA_ODM_HARMONY)
+    return (725 + bits * 25);
+#else
+    return (1450 + bits * 50);
+#endif
+}
+
+static NvU32 TPS6586xPmuVoltageGetSM2(const NvU32 bits)
+{
+    NV_ASSERT(bits <= 0x1F);
+
+    return (3000 + bits * 25);
+}
+
+static NvU32 TPS6586xPmuVoltageGetVLDOx(const NvU32 bits)
+{
+    NV_ASSERT(bits <= 0x7);
+
+    return VLDOx[bits];
+}
+
+static NvU32 TPS6586xPmuVoltageGetVLDO1(const NvU32 bits)
+{
+    /* VLDO1 and VLDO2 use the same table.
+     * See pp. 64 - 66 of TPS658621 data sheet.
+     */
+    NV_ASSERT(bits <= 0x1F);
+
+    return VLDO2[bits];
+}
+
+static NvU32 TPS6586xPmuVoltageGetVLDO2(const NvU32 bits)
+{
+    NV_ASSERT(bits <= 0x1F);
+    return VLDO2[bits];
+}
+static NvU32 TPS6586xPmuVoltageGetVLDO4(const NvU32 bits)
+{
+    NV_ASSERT(bits <= 0x1F);
+    return VLDO4[bits];
+}
+
+#ifndef MIN
+#define MIN(a, b)   (a) <= (b) ? (a) : (b)
+#endif
+
+static NvU32 TPS6586xPmuVoltageSetSM0(const NvU32 millivolts)
+{
+    if (millivolts < 725)
+        return 0;
+    else
+        return MIN((millivolts - 725) / 25, 0x1f);
+}
+
+static NvU32 TPS6586xPmuVoltageSetSM1(const NvU32 millivolts)
+{
+#if defined(CONFIG_TEGRA_ODM_HARMONY)
+    if (millivolts < 725)
+        return 0;
+    else
+        return MIN((millivolts - 725) / 25, 0x1f);
+#else
+    if (millivolts < 1450)
+        return 0;
+    else
+        return MIN((millivolts - 1450) / 50, 0x1f);
+#endif
+}
+
+static NvU32 TPS6586xPmuVoltageSetSM2(const NvU32 millivolts)
+{
+    if (millivolts < 3000)
+        return 0;
+    else 
+        return MIN((millivolts - 3000) / 25, 0x1f);
+}
+
+#define VOLTAGE_SEARCH(mv, vtbl)        \
+    const int cnt = sizeof(vtbl)/sizeof(NvU32);     \
+    int i;                                          \
+    for (i=0; i<cnt; i++)                           \
+    {                                               \
+        if (mv <= (vtbl)[i])                        \
+            break;                                  \
+    }                                               \
+    return MIN(i, cnt-1)
+
+
+static NvU32 TPS6586xPmuVoltageSetVLDOx(const NvU32 millivolts)
+{
+    VOLTAGE_SEARCH(millivolts, VLDOx);
+}
+
+static NvU32 TPS6586xPmuVoltageSetVLDO1(const NvU32 millivolts)
+{
+    /* VLDO1 and VLDO2 use the same table.
+     * See pp. 64 - 66 of TPS658621 data sheet.
+     */
+    VOLTAGE_SEARCH(millivolts, VLDO2);
+}
+
+static NvU32 TPS6586xPmuVoltageSetVLDO2(const NvU32 millivolts)
+{
+    VOLTAGE_SEARCH(millivolts, VLDO2);
+}
+static NvU32 TPS6586xPmuVoltageSetVLDO4(const NvU32 millivolts)
+{
+    VOLTAGE_SEARCH(millivolts, VLDO4);
+}
+
+
+void
+Tps6586xGetCapabilities(
+    NvU32 vddRail,
+    NvOdmPmuVddRailCapabilities* pCapabilities)
+{
+    NV_ASSERT(pCapabilities);
+    NV_ASSERT(vddRail < TPS6586xPmuSupply_Num);
+
+    *pCapabilities = tps6586xSupplyInfoTable[vddRail].cap;
+}
+
+#if defined(CONFIG_TEGRA_ODM_HARMONY)
+static NvBool g_ExternalSupplyEnabled[TPS6586x_EXTERNAL_SUPPLY_NUM] = { 0 };
+
+static NvBool
+Tps6586xGetExternalSupply(
+    NvOdmPmuDeviceHandle hDevice, 
+    NvU32 vddRail,
+    NvU32* pMilliVolts)
+{
+    if (g_ExternalSupplyEnabled[vddRail - (NvU32)(Ext_TPS62290PmuSupply_BUCK)] == NV_TRUE)
+        *pMilliVolts = tps6586xSupplyInfoTable[vddRail].cap.requestMilliVolts;
+    else
+        *pMilliVolts = 0;
+
+    return NV_TRUE;
+}
+#endif
+
+static NvBool
+Tps6586xReadVoltageReg(
+        NvOdmPmuDeviceHandle hDevice,
+        NvU32 vddRail,
+        NvU32* pMilliVolts)
+{
+    const TPS6586xPmuSupplyInfo *pSupplyInfo = &tps6586xSupplyInfoTable[vddRail];
+    NvU32 data = 0;
+
+#if defined(CONFIG_TEGRA_ODM_HARMONY)
+    // External supplies are fixed.
+    if ((vddRail == Ext_TPS62290PmuSupply_BUCK)      ||
+        (vddRail == Ext_TPS72012PmuSupply_LDO)       ||
+        (vddRail == Ext_TPS74201PmuSupply_LDO)       ||
+        (vddRail == Ext_TPS2051BPmuSupply_VDDIO_VID) ||
+        (vddRail == Ext_SWITCHPmuSupply_VDDIO_SD)    ||
+        (vddRail == Ext_SWITCHPmuSupply_VDDIO_SDMMC) ||
+        (vddRail == Ext_SWITCHPmuSupply_VDD_BL)      ||
+        (vddRail == Ext_SWITCHPmuSupply_VDD_PNL))
+    {
+        if (!Tps6586xGetExternalSupply(hDevice, vddRail, pMilliVolts))
+            return NV_FALSE;
+        else
+            return NV_TRUE;
+    }
+#endif
+
+    if (pSupplyInfo->supplyRegInfo.addr == TPS6586x_RFF_INVALID) 
+    {
+        return NV_FALSE;
+    }
+
+    if (! Tps6586xI2cRead8(hDevice, pSupplyInfo->supplyRegInfo.addr, &data))
+        return NV_FALSE;
+
+    if (pSupplyInfo->getVoltage)
+        *pMilliVolts = pSupplyInfo->getVoltage((data >> pSupplyInfo->supplyRegInfo.start) & ((1<<pSupplyInfo->supplyRegInfo.bits)-1));
+    else
+        *pMilliVolts = data;
+
+    Tps6586xI2cRead8(hDevice, pSupplyInfo->ctrlRegInfo.addr, &data);
+    data &= (((1<<pSupplyInfo->ctrlRegInfo.bits)-1)<<pSupplyInfo->ctrlRegInfo.start);
+    if (data == 0)
+    {
+        //since Voltage table is  {1250, 1500, 1800, 2500, 2700, 2850, 3100, 3300} 
+        //need to fill 0 voltage if needed
+        *pMilliVolts = data;
+    } 
+
+
+    return NV_TRUE;
+}
+
+#if 0
+static NvBool
+Tps6586xSupplyCtrl(
+        const NvU32 vddRail, 
+        NvBool ctrl)
+{
+    return NV_TRUE;
+}
+#endif
+
+#if defined(CONFIG_TEGRA_ODM_HARMONY)
+#define NVODM_PORT(x) ((x) - 'a')
+
+static NvBool
+Tps6586xSetExternalSupply(
+    NvOdmPmuDeviceHandle hDevice, 
+    NvU32 vddRail,
+    NvBool Enable)
+{
+    const TPS6586xPmuSupplyInfo* pSupplyInfo = &tps6586xSupplyInfoTable[vddRail];
+    NvU32 data = 0;
+    NvU8 Gpio;
+    NvU32 GpioPort;
+    NvU32 GpioPin;
+
+    NV_ASSERT((vddRail > TPS6586xPmuSupply_Invalid) && (vddRail < TPS6586xPmuSupply_Num));
+
+    // FIXME: Clean this up!  This includes embedding more of these settings in
+    // the supply info table to simplify the code.
+
+    // Switched by PMU GPIO
+    if ((vddRail == Ext_TPS62290PmuSupply_BUCK)||
+        (vddRail == Ext_TPS72012PmuSupply_LDO) ||
+        (vddRail == Ext_TPS74201PmuSupply_LDO))
+    {
+        // Set output mode (TEST: FOR GPIO1 only)
+
+        Gpio = pSupplyInfo->Gpio;
+        switch (Gpio)
+        {
+        case 1:
+            if (!Tps6586xI2cRead8(hDevice, TPS6586x_R5D_GPIOSET1, &data))
+                return NV_FALSE;
+
+            // Reset mode field
+            data &= ~(TPS6586x_R5D_GPIOSET1_GPIO1_MODE_MASK <<
+                      TPS6586x_R5D_GPIOSET1_GPIO1_MODE_SHIFT);
+            // Apply new mode setting (output)
+            data |= (TPS6586x_R5D_GPIO_MODE_OUTPUT <<
+                     TPS6586x_R5D_GPIOSET1_GPIO1_MODE_SHIFT);
+            if (!Tps6586xI2cWrite8(hDevice, TPS6586x_R5D_GPIOSET1, data))
+                return NV_FALSE;
+
+            if (Enable)
+            {
+                // Enable output
+                if (!Tps6586xI2cRead8(hDevice, TPS6586x_R5E_GPIOSET2, &data))
+                    return NV_FALSE;
+
+                data |= (TPS6586x_R5E_GPIOSET2_GPIO1_OUT_MASK <<
+                         TPS6586x_R5E_GPIOSET2_GPIO1_OUT_SHIFT);
+                if (!Tps6586xI2cWrite8(hDevice, TPS6586x_R5E_GPIOSET2, data))
+                    return NV_FALSE;
+            }
+            else
+            {
+                // Disable output
+                if (!Tps6586xI2cRead8(hDevice, TPS6586x_R5E_GPIOSET2, &data))
+                    return NV_FALSE;
+
+                data &= ~(TPS6586x_R5E_GPIOSET2_GPIO1_OUT_MASK <<
+                          TPS6586x_R5E_GPIOSET2_GPIO1_OUT_SHIFT);
+                if (!Tps6586xI2cWrite8(hDevice, TPS6586x_R5E_GPIOSET2, data))
+                    return NV_FALSE;
+            }
+            break;
+
+        case 2:
+            if (!Tps6586xI2cRead8(hDevice, TPS6586x_R5D_GPIOSET1, &data))
+                return NV_FALSE;
+
+            // Reset mode field
+            data &= ~(TPS6586x_R5D_GPIOSET1_GPIO2_MODE_MASK <<
+                      TPS6586x_R5D_GPIOSET1_GPIO2_MODE_SHIFT);
+            // Apply new mode setting (output)
+            data |= (TPS6586x_R5D_GPIO_MODE_OUTPUT <<
+                     TPS6586x_R5D_GPIOSET1_GPIO2_MODE_SHIFT);
+            if (!Tps6586xI2cWrite8(hDevice, TPS6586x_R5D_GPIOSET1, data))
+                return NV_FALSE;
+
+            if (Enable)
+            {
+                // Enable output
+                if (!Tps6586xI2cRead8(hDevice, TPS6586x_R5E_GPIOSET2, &data))
+                    return NV_FALSE;
+
+                data |= (TPS6586x_R5E_GPIOSET2_GPIO2_OUT_MASK <<
+                         TPS6586x_R5E_GPIOSET2_GPIO2_OUT_SHIFT);
+                if (!Tps6586xI2cWrite8(hDevice, TPS6586x_R5E_GPIOSET2, data))
+                    return NV_FALSE;
+            }
+            else
+            {
+                // Disable output
+                if (!Tps6586xI2cRead8(hDevice, TPS6586x_R5E_GPIOSET2, &data))
+                    return NV_FALSE;
+
+                data &= ~(TPS6586x_R5E_GPIOSET2_GPIO2_OUT_MASK <<
+                          TPS6586x_R5E_GPIOSET2_GPIO2_OUT_SHIFT);
+                if (!Tps6586xI2cWrite8(hDevice, TPS6586x_R5E_GPIOSET2, data))
+                    return NV_FALSE;
+            }
+            break;
+
+        case 3:
+            if (!Tps6586xI2cRead8(hDevice, TPS6586x_R5D_GPIOSET1, &data))
+                return NV_FALSE;
+            // Reset mode field
+            data &= ~(TPS6586x_R5D_GPIOSET1_GPIO3_MODE_MASK <<
+                      TPS6586x_R5D_GPIOSET1_GPIO3_MODE_SHIFT);
+            // Apply new mode setting (output)
+            data |= (TPS6586x_R5D_GPIO_MODE_OUTPUT <<
+                     TPS6586x_R5D_GPIOSET1_GPIO3_MODE_SHIFT);
+            if (!Tps6586xI2cWrite8(hDevice, TPS6586x_R5D_GPIOSET1, data))
+                return NV_FALSE;
+
+            if (Enable)
+            {
+                // Enable output
+                if (!Tps6586xI2cRead8(hDevice, TPS6586x_R5E_GPIOSET2, &data))
+                    return NV_FALSE;
+
+                data |= (TPS6586x_R5E_GPIOSET2_GPIO3_OUT_MASK <<
+                         TPS6586x_R5E_GPIOSET2_GPIO3_OUT_SHIFT);
+                if (!Tps6586xI2cWrite8(hDevice, TPS6586x_R5E_GPIOSET2, data))
+                    return NV_FALSE;
+            }
+            else
+            {
+                // Disable output
+                if (!Tps6586xI2cRead8(hDevice, TPS6586x_R5E_GPIOSET2, &data))
+                    return NV_FALSE;
+
+                data &= ~(TPS6586x_R5E_GPIOSET2_GPIO3_OUT_MASK <<
+                          TPS6586x_R5E_GPIOSET2_GPIO3_OUT_SHIFT);
+                if (!Tps6586xI2cWrite8(hDevice, TPS6586x_R5E_GPIOSET2, data))
+                    return NV_FALSE;
+            }
+            break;
+
+        default:
+            return NV_FALSE; // bad parameter
+        }
+    }
+    // Switched by AP GPIO
+    else
+    {
+        // Open GPIO
+        if (!hPmu->hGpio)
+        {
+            hPmu->hGpio = NvOdmGpioOpen();
+
+            if (!hPmu->hGpio)
+                return NV_FALSE;
+        }
+
+        // Get AP GPIO pin assigned to the respective voltage rail
+        // FIXME:  This should be driven by supply info table.
+        switch (vddRail)
+        {
+        case Ext_TPS2051BPmuSupply_VDDIO_VID:
+            GpioPort = NVODM_PORT('t');
+            GpioPin  = 2;
+            break;
+
+        case Ext_SWITCHPmuSupply_VDDIO_SD:
+            GpioPort = NVODM_PORT('t');
+            GpioPin  = 3;
+            break;
+
+        case Ext_SWITCHPmuSupply_VDDIO_SDMMC:
+            GpioPort = NVODM_PORT('i');
+            GpioPin  = 6;
+            break;
+
+        case Ext_SWITCHPmuSupply_VDD_BL:
+            GpioPort = NVODM_PORT('w');
+            GpioPin  = 0;
+            break;
+
+        case Ext_SWITCHPmuSupply_VDD_PNL:
+            GpioPort = NVODM_PORT('c');
+            GpioPin  = 6;
+            break;
+
+        default:
+            return NV_FALSE;
+        }
+
+        NV_ASSERT((NVODM_EXT_AP_GPIO_RAIL(vddRail) >= 0) &&
+                  (NVODM_EXT_AP_GPIO_RAIL(vddRail) < TPS6586x_EXTERNAL_SUPPLY_AP_GPIO_NUM));
+
+        // Acquire Pin Handle
+        if (!hPmu->hPin[NVODM_EXT_AP_GPIO_RAIL(vddRail)])
+        {
+            hPmu->hPin[NVODM_EXT_AP_GPIO_RAIL(vddRail)] = 
+                NvOdmGpioAcquirePinHandle(hPmu->hGpio, GpioPort, GpioPin);
+
+            if (!hPmu->hPin[NVODM_EXT_AP_GPIO_RAIL(vddRail)])
+                return NV_FALSE;
+        }
+
+        if (Enable)
+        {
+            if (vddRail == Ext_TPS2051BPmuSupply_VDDIO_VID)
+            {
+                NvOdmGpioConfig(hPmu->hGpio,
+                                hPmu->hPin[NVODM_EXT_AP_GPIO_RAIL(vddRail)],
+                                NvOdmGpioPinMode_Tristate);
+            }
+            else
+            {
+                NvOdmGpioSetState(hPmu->hGpio,
+                                  hPmu->hPin[NVODM_EXT_AP_GPIO_RAIL(vddRail)],
+                                  NvOdmGpioPinActiveState_High);
+
+                NvOdmGpioConfig(hPmu->hGpio,
+                                hPmu->hPin[NVODM_EXT_AP_GPIO_RAIL(vddRail)],
+                                NvOdmGpioPinMode_Output);
+            }
+        }
+        else
+        {
+            if (vddRail != Ext_TPS2051BPmuSupply_VDDIO_VID)
+            {
+                NvOdmGpioSetState(hPmu->hGpio,
+                              hPmu->hPin[NVODM_EXT_AP_GPIO_RAIL(vddRail)],
+                              NvOdmGpioPinActiveState_Low);
+                NvOdmGpioConfig(hPmu->hGpio,
+                            hPmu->hPin[NVODM_EXT_AP_GPIO_RAIL(vddRail)],
+                            NvOdmGpioPinMode_Output);
+            }
+        }
+    }
+
+    // This isn't thread safe, but it's highly unlikely that will be an issue for these rails.
+    if (Enable)
+    {
+        g_ExternalSupplyEnabled[vddRail - (NvU32)(Ext_TPS62290PmuSupply_BUCK)] = NV_TRUE;
+    }
+    else
+    {
+        g_ExternalSupplyEnabled[vddRail - (NvU32)(Ext_TPS62290PmuSupply_BUCK)] = NV_FALSE;
+    }
+    return NV_TRUE;
+}
+#endif
+
+static NvBool 
+Tps6586xWriteVoltageReg(
+    NvOdmPmuDeviceHandle hDevice, 
+    NvU32 vddRail, 
+    NvU32  MilliVolts, 
+    NvU32* pSettleMicroSeconds)
+{
+    const TPS6586xPmuSupplyInfo* pSupplyInfo = &tps6586xSupplyInfoTable[vddRail];
+    //const TPS6586xPmuSupplyInfo* pSupplyInputInfo = &tps6586xSupplyInfoTable[pSupplyInfo->supplyInput];
+    NvBool status = NV_FALSE;
+    NvU32  settleTime = 0;
+#if !defined(CONFIG_TEGRA_ODM_HARMONY)
+    NvU32  volChange = 0;
+#endif
+
+    NV_ASSERT(pSupplyInfo->supply == (TPS6586xPmuSupply)vddRail);
+
+#if defined(CONFIG_TEGRA_ODM_HARMONY)
+    if ((vddRail != Ext_TPS62290PmuSupply_BUCK)      &&
+        (vddRail != Ext_TPS72012PmuSupply_LDO)       &&
+        (vddRail != Ext_TPS74201PmuSupply_LDO)       &&
+        (vddRail != Ext_TPS2051BPmuSupply_VDDIO_VID) &&
+        (vddRail != Ext_SWITCHPmuSupply_VDDIO_SD)    &&
+        (vddRail != Ext_SWITCHPmuSupply_VDDIO_SDMMC) &&
+        (vddRail != Ext_SWITCHPmuSupply_VDD_BL)      &&
+        (vddRail != Ext_SWITCHPmuSupply_VDD_PNL))
+#endif
+    {
+        if (pSupplyInfo->ctrlRegInfo.addr == TPS6586x_RFF_INVALID)
+        {
+            NVODMPMU_PRINTF(("TPS:The required ctrl register address is INVALID...\n"));
+#if defined(CONFIG_TEGRA_ODM_HARMONY)
+            return NV_TRUE;
+            //return NV_FALSE;
+#else
+            return NV_FALSE;
+#endif
+        }
+    }
+
+    if (MilliVolts == ODM_VOLTAGE_OFF) 
+    {
+        NvU32 data = 0;
+
+        // check if the supply can be turned off
+        //NV_ASSERT(hDevice->supplyRefCntTable[vddRail]);
+
+#if defined(CONFIG_TEGRA_ODM_HARMONY)
+        // Disable external supplies
+        if ((vddRail == Ext_TPS62290PmuSupply_BUCK)      ||
+            (vddRail == Ext_TPS72012PmuSupply_LDO)       ||
+            (vddRail == Ext_TPS74201PmuSupply_LDO)       ||
+            (vddRail == Ext_TPS2051BPmuSupply_VDDIO_VID) ||
+            (vddRail == Ext_SWITCHPmuSupply_VDDIO_SD)    ||
+            (vddRail == Ext_SWITCHPmuSupply_VDDIO_SDMMC) ||
+            (vddRail == Ext_SWITCHPmuSupply_VDD_BL)      ||
+            (vddRail == Ext_SWITCHPmuSupply_VDD_PNL))
+        {
+            status = Tps6586xSetExternalSupply(hDevice, vddRail, NV_FALSE);
+        }
+        else
+#endif
+        if (((NvOdmPmuDeviceTPS *)(hDevice->pPrivate))->supplyRefCntTable[vddRail] == 1)
+        {
+            /* Disable */
+            NvOdmServicesPmuSetSocRailPowerState(
+                ((NvOdmPmuDeviceTPS *)(hDevice->pPrivate))->hOdmPmuSevice, pSupplyInfo->supply, NV_FALSE); 
+            Tps6586xI2cRead8(hDevice, pSupplyInfo->ctrlRegInfo.addr, &data);
+#if defined(CONFIG_TEGRA_ODM_HARMONY)
+            if (vddRail == TPS6586xPmuSupply_SoC)
+            {
+                // SOC Super power rail don't hold the sleep bit
+                data |= (((1<<pSupplyInfo->ctrlRegInfo.bits)-1)<<pSupplyInfo->ctrlRegInfo.start);
+            }
+            else
+#endif
+            {
+                data &= ~(((1<<pSupplyInfo->ctrlRegInfo.bits)-1)<<pSupplyInfo->ctrlRegInfo.start);
+            }
+            status = Tps6586xI2cWrite8(hDevice, pSupplyInfo->ctrlRegInfo.addr, data);
+#if defined(CONFIG_TEGRA_ODM_HARMONY)
+            if (vddRail == TPS6586xPmuSupply_SoC)
+            {
+                // Wait 10 secs for PMU to shutdown
+                NvOdmOsWaitUS(100000000);
+            }
+#endif
+
+            if (status && (pSupplyInfo->ctrlRegInfo.flag != TPS6586x_RFF_INVALID))
+            {
+                status = Tps6586xI2cRead8(hDevice, pSupplyInfo->ctrlRegInfo.flag, &data);
+                if (status) 
+                {
+                    data &= ~(((1<<pSupplyInfo->ctrlRegInfo.bits)-1)<<pSupplyInfo->ctrlRegInfo.start);
+                    status = Tps6586xI2cWrite8(hDevice, pSupplyInfo->ctrlRegInfo.flag, data);
+                }
+            }
+
+            /* Reset to voltage to 0th */
+            MilliVolts = 0;
+            
+#if !defined(CONFIG_TEGRA_ODM_HARMONY)
+            // Calcuate this voltage change
+            volChange = ((NvOdmPmuDeviceTPS *)(hDevice->pPrivate))->curVoltageTable[vddRail];
+
+            ((NvOdmPmuDeviceTPS *)(hDevice->pPrivate))->curVoltageTable[vddRail] = 0;
+            
+            // DCD0/DCD1/DCD2
+            if ((vddRail == TPS6586xPmuSupply_DCD0) ||
+                (vddRail == TPS6586xPmuSupply_DCD1) ||
+                (vddRail == TPS6586xPmuSupply_DCD2))
+            {
+                // delay = Tstart(210) + Voltage change/Kramp
+                settleTime = T_START_TIME + volChange/K_RAMP;
+            }
+            else if ((vddRail == TPS6586xPmuSupply_LDO2) ||
+                     (vddRail == TPS6586xPmuSupply_LDO4))
+            {
+                // Voltage change/Kramp
+                settleTime = volChange/K_RAMP;
+            }
+            else
+            {
+                settleTime = 0;
+            }
+#endif
+        }
+
+        if (((NvOdmPmuDeviceTPS *)(hDevice->pPrivate))->supplyRefCntTable[vddRail] != 0)
+        {
+#if defined(CONFIG_TEGRA_ODM_HARMONY)
+            if(--((NvOdmPmuDeviceTPS *)(hDevice->pPrivate))->supplyRefCntTable[vddRail] != 0)
+            {
+                if (pSettleMicroSeconds)
+                    *pSettleMicroSeconds = 0;
+                return NV_TRUE;
+            }
+#else
+            --((NvOdmPmuDeviceTPS *)(hDevice->pPrivate))->supplyRefCntTable[vddRail];
+#endif
+        }
+
+#if !defined(CONFIG_TEGRA_ODM_HARMONY)        
+        if (pSettleMicroSeconds != NULL)
+            *pSettleMicroSeconds = settleTime;
+        else
+            NvOdmOsWaitUS(settleTime);
+            
+        return NV_TRUE;
+#endif
+    }
+    else
+    {    
+        NvU32 data = 0;
+
+        if (((NvOdmPmuDeviceTPS *)(hDevice->pPrivate))->supplyRefCntTable[vddRail]++ == 0)
+        {
+            // Enable external supplies
+#if defined(CONFIG_TEGRA_ODM_HARMONY)
+            if ((vddRail == Ext_TPS62290PmuSupply_BUCK)      ||
+                (vddRail == Ext_TPS72012PmuSupply_LDO)       ||
+                (vddRail == Ext_TPS74201PmuSupply_LDO)       ||
+                (vddRail == Ext_TPS2051BPmuSupply_VDDIO_VID) ||
+                (vddRail == Ext_SWITCHPmuSupply_VDDIO_SD)    ||
+                (vddRail == Ext_SWITCHPmuSupply_VDDIO_SDMMC) ||
+                (vddRail == Ext_SWITCHPmuSupply_VDD_BL)      ||
+                (vddRail == Ext_SWITCHPmuSupply_VDD_PNL))
+            {
+                status = Tps6586xSetExternalSupply(hDevice, vddRail, NV_TRUE);
+            }
+            else
+#endif
+            {
+#if !defined(CONFIG_TEGRA_ODM_HARMONY)
+                NvOdmServicesPmuSetSocRailPowerState(
+                    ((NvOdmPmuDeviceTPS *)(hDevice->pPrivate))->hOdmPmuSevice, pSupplyInfo->supply, NV_TRUE); 
+#endif
+                status = Tps6586xI2cRead8(hDevice, pSupplyInfo->ctrlRegInfo.addr, &data);
+                if (status && ((data >> pSupplyInfo->ctrlRegInfo.start) & 0x1) == 0)
+                {
+#if defined(CONFIG_TEGRA_ODM_HARMONY)
+                    /* Enable */
+                    NvOdmServicesPmuSetSocRailPowerState(
+                        ((NvOdmPmuDeviceTPS *)(hDevice->pPrivate))->hOdmPmuSevice,
+                        pSupplyInfo->supply, NV_TRUE);
+#endif
+                    data |= (((1<<pSupplyInfo->ctrlRegInfo.bits)-1)<<pSupplyInfo->ctrlRegInfo.start);
+                    if (NV_FALSE == Tps6586xI2cWrite8(hDevice, pSupplyInfo->ctrlRegInfo.addr, data))
+#if defined(CONFIG_TEGRA_ODM_HARMONY)
+                        return NV_TRUE;
+#else
+                        return NV_FALSE;
+#endif
+                }
+            }
+        }
+
+        /* Disable Flash mode 
+         * FIXME: please check whether you need to disable flash */
+        /*
+        if (vddRail == TPS6586xPmuSupply_RED1 ||
+            vddRail == TPS6586xPmuSupply_GREEN1 ||
+            vddRail == TPS6586xPmuSupply_BLUE1)
+        {
+            if (NV_FALSE == Tps6586xI2cWrite8(hDevice, TPS6586x_R50_RGB1FLASH, 0xFF))
+                return NV_FALSE;
+        } 
+        */
+    }
+
+    if (pSupplyInfo->supplyRegInfo.addr == TPS6586x_RFF_INVALID) 
+    {
+#if defined(CONFIG_TEGRA_ODM_HARMONY)
+        return NV_TRUE;
+#else
+        return NV_FALSE;
+#endif
+    }
+    else
+    {
+        const int bits = pSupplyInfo->setVoltage ? pSupplyInfo->setVoltage(MilliVolts) : MilliVolts;
+        NvU32 data = 0;
+
+#if defined(CONFIG_TEGRA_ODM_HARMONY)
+        status = Tps6586xI2cRead8(hDevice, pSupplyInfo->supplyRegInfo.addr, &data);
+        if (NV_FALSE == status)
+            NVODMPMU_PRINTF(("TPS:Writing to PMU I2C fails 1... supplyaddress: %d\n", pSupplyInfo->supplyRegInfo.addr));
+#else
+        if ((vddRail == TPS6586xPmuSupply_DCD0) ||
+            (vddRail == TPS6586xPmuSupply_DCD1) ||
+            (vddRail == TPS6586xPmuSupply_LDO4) ||
+            (vddRail == TPS6586xPmuSupply_LDO2))
+        {
+            status = NV_TRUE;
+        }
+        else
+        {
+            status = Tps6586xI2cRead8(hDevice, pSupplyInfo->supplyRegInfo.addr, &data);
+        }
+#endif
+
+        if (status) 
+        {
+            data &= ~(((1<<pSupplyInfo->supplyRegInfo.bits)-1)<<pSupplyInfo->supplyRegInfo.start);
+            data |= (bits << pSupplyInfo->supplyRegInfo.start);
+            status = Tps6586xI2cWrite8(hDevice, pSupplyInfo->supplyRegInfo.addr, data);
+
+            /* Trigger a voltage change for SM0/SM1/LDO2/LDO4 */
+            if ((vddRail == TPS6586xPmuSupply_DCD0) ||
+                (vddRail == TPS6586xPmuSupply_DCD1) ||
+                (vddRail == TPS6586xPmuSupply_LDO4) ||
+                (vddRail == TPS6586xPmuSupply_LDO2))
+            {
+                data = 0;
+                switch (vddRail) 
+                {
+                case TPS6586xPmuSupply_LDO2:
+                    data |=  (1<<4);
+                    data &=  ~(1<<5);
+                    break;
+
+                case TPS6586xPmuSupply_LDO4:
+                    data |=  (1<<6);
+                    data &=  ~(1<<7);
+                    break;
+
+                case TPS6586xPmuSupply_DCD0:
+                    data |=  (1<<2);
+                    data &=  ~(1<<3);
+                    break;
+
+                case TPS6586xPmuSupply_DCD1:
+                    data |=  (1<<0);
+                    data &=  ~(1<<1);
+                    break;
+                }
+                status = Tps6586xI2cWrite8(hDevice, TPS6586x_R20_VCC1, data);
+            }
+            
+#if !defined(CONFIG_TEGRA_ODM_HARMONY)
+            // Calcuate this voltage change
+            if (((NvOdmPmuDeviceTPS *)(hDevice->pPrivate))->curVoltageTable[vddRail] < MilliVolts)
+                volChange = MilliVolts - ((NvOdmPmuDeviceTPS *)(hDevice->pPrivate))->curVoltageTable[vddRail];
+            else
+                volChange = ((NvOdmPmuDeviceTPS *)(hDevice->pPrivate))->curVoltageTable[vddRail] - MilliVolts;
+            
+            ((NvOdmPmuDeviceTPS *)(hDevice->pPrivate))->curVoltageTable[vddRail] = MilliVolts;
+            
+            // DCD0/DCD1/DCD2
+            if ((vddRail == TPS6586xPmuSupply_DCD0) ||
+                (vddRail == TPS6586xPmuSupply_DCD1) ||
+                (vddRail == TPS6586xPmuSupply_DCD2))
+            {
+                // delay = Tstart(210) + Voltage change/Kramp
+                settleTime = T_START_TIME + volChange/K_RAMP;
+            }
+            else if ((vddRail == TPS6586xPmuSupply_LDO2) ||
+                     (vddRail == TPS6586xPmuSupply_LDO4))
+            {
+                // Voltage change/Kramp
+                settleTime = volChange/K_RAMP;
+            }
+            else
+            {
+                settleTime = 0;
+            }
+#else
+            settleTime = 250;
+#endif
+            
+            if (pSettleMicroSeconds)
+                *pSettleMicroSeconds = settleTime;
+            else
+                NvOdmOsWaitUS(settleTime);
+            return status;
+        }
+    }
+
+    if (pSupplyInfo->supplyRegInfo.addr == TPS6586x_RFF_INVALID) 
+    {
+#if defined(CONFIG_TEGRA_ODM_HARMONY)
+        return NV_TRUE;
+#else
+        return NV_FALSE;
+#endif
+    }
+
+    if (pSettleMicroSeconds)
+#if defined(CONFIG_TEGRA_ODM_HARMONY)
+        *pSettleMicroSeconds = 250;
+    else
+        NvOdmOsWaitUS(250);
+#else
+        *pSettleMicroSeconds = 0;
+#endif
+ 
+    return NV_TRUE;
+}
+
+NvBool
+Tps6586xGetVoltage(
+    NvOdmPmuDeviceHandle hDevice,
+    NvU32 vddRail,
+    NvU32* pMilliVolts)
+{   
+    NV_ASSERT(hDevice);
+    NV_ASSERT(pMilliVolts);
+    NV_ASSERT(vddRail < TPS6586xPmuSupply_Num);
+
+    if(! Tps6586xReadVoltageReg(hDevice, vddRail,pMilliVolts))
+        return NV_FALSE;
+    
+    return NV_TRUE;
+}
+
+NvBool
+Tps6586xSetVoltage(
+    NvOdmPmuDeviceHandle hDevice,
+    NvU32 vddRail,
+    NvU32 MilliVolts,
+    NvU32* pSettleMicroSeconds)
+{
+    NV_ASSERT(hDevice);
+    NV_ASSERT(vddRail < TPS6586xPmuSupply_Num);
+
+    if (pSettleMicroSeconds)
+        *pSettleMicroSeconds = 0;
+
+    if (tps6586xSupplyInfoTable[vddRail].cap.OdmProtected == NV_TRUE)
+    {
+        NVODMPMU_PRINTF(("The voltage is protected and can not be set.\n"));
+        return NV_TRUE;
+    }
+
+    if ((MilliVolts == ODM_VOLTAGE_OFF) ||
+        ((MilliVolts <= tps6586xSupplyInfoTable[vddRail].cap.MaxMilliVolts) &&
+         (MilliVolts >= tps6586xSupplyInfoTable[vddRail].cap.MinMilliVolts)))
+    {
+        if (! Tps6586xWriteVoltageReg(hDevice, vddRail, MilliVolts, pSettleMicroSeconds))
+            return NV_FALSE;
+    }
+    else
+    {
+        NVODMPMU_PRINTF(("The required voltage is not supported..\n"));
+#if defined(CONFIG_TEGRA_ODM_HARMONY)
+        return NV_TRUE;
+        //return NV_FALSE;
+#else
+        return NV_FALSE;
+#endif
+    }
+
+    return NV_TRUE;
+}
+
+#if 0
+void DumpTps6586x(NvOdmPmuDeviceHandle hDevice)
+{
+    int i;
+    NvU32 data;
+    for (i=0; i<0xFF; i++) 
+    {
+        data = 0;
+        Tps6586xI2cRead8(hDevice, i, &data);
+        NVODMPMU_PRINTF(("Register 0x%x = 0x%x\n", i, data));
+    }
+}
+#endif
+
+NvBool Tps6586xSetup(NvOdmPmuDeviceHandle hDevice)
+{
+    NvOdmIoModule I2cModule = NvOdmIoModule_I2c;
+    NvU32 I2cInstance = 0;
+    NvU32 I2cAddress  = 0;
+    NvBool status     = NV_FALSE;
+    NvU32 data = 0;    
+//    static TPS6586xDevice s_tps6586x = {0};
+    
+    const NvOdmPeripheralConnectivity *pConnectivity = 
+                           NvOdmPeripheralGetGuid(PMUGUID);
+
+    NV_ASSERT(hDevice);
+    
+    hPmu = (NvOdmPmuDeviceTPS *)NvOdmOsAlloc(sizeof(NvOdmPmuDeviceTPS));
+    if (hPmu == NULL)
+    {
+        NVODMPMU_PRINTF(("Error Allocating NvOdmPmuDeviceTPS. \n"));
+        return NV_FALSE;
+    }
+    NvOdmOsMemset(hPmu, 0, sizeof(NvOdmPmuDeviceTPS));
+
+    hDevice->pPrivate = hPmu;
+
+    if (pConnectivity != NULL) // PMU is in database
+    {
+        NvU32 i = 0;
+        pmuPresented = NV_TRUE;
+        
+        for (i = 0; i < pConnectivity->NumAddress; i ++)
+        {
+            if (pConnectivity->AddressList[i].Interface == NvOdmIoModule_I2c_Pmu)
+            {
+                I2cModule   = NvOdmIoModule_I2c_Pmu;
+                I2cInstance = pConnectivity->AddressList[i].Instance;
+                I2cAddress  = pConnectivity->AddressList[i].Address;
+                break;
+            }
+        }
+
+        NV_ASSERT(I2cModule  == NvOdmIoModule_I2c_Pmu);
+        NV_ASSERT(I2cAddress != 0);
+
+        hPmu->hOdmI2C = NvOdmI2cOpen(I2cModule, I2cInstance);
+        if (!hPmu->hOdmI2C)
+        {
+            NVODMPMU_PRINTF(("[NVODM PMU]Tps6586xSetup: Error Open I2C device. \n"));
+            NVODMPMU_PRINTF(("[NVODM PMU]Please check PMU device I2C settings. \n"));
+            goto OPEN_FAILED;
+        }
+        hPmu->DeviceAddr = I2cAddress;
+        hPmu->hOdmPmuSevice = NvOdmServicesPmuOpen();
+#if defined(CONFIG_TEGRA_ODM_HARMONY)
+        //if (NV_FALSE == Tps6586xWriteVoltageReg(hDevice, TPS6586xPmuSupply_LDO5, 3300, NULL))
+        if (NV_FALSE == Tps6586xWriteVoltageReg(hDevice, TPS6586xPmuSupply_LDO5, 2850, NULL))
+            NVODMPMU_PRINTF(("TPS: Fail to set the NVDDIO_NAND to 2.85V\n"));
+        else
+            NVODMPMU_PRINTF(("TPS: set the NVDDIO_NAND to 2.85V\n"));
+#endif
+    }   
+    else
+    {
+        // if PMU is not presented in the database, then the platform is PMU-less.
+        NVODMPMU_PRINTF(("[NVODM PMU]Tps6586xSetup: The system did not doscover PMU fromthe data base. \n"));     
+        NVODMPMU_PRINTF(("[NVODM PMU]Tps6586xSetup: If this is not intended, please check the peripheral database for PMU settings. \n"));     
+
+        //uncomment below line if you really need to run pmu adaptation on  pmu-less system.
+        // the system will run in pmu-less mode.
+        //pmuPresented = NV_FALSE;
+
+        goto OPEN_FAILED;
+    }
+
+    //hDevice->priv = &s_tps6586x;
+
+    /* Check Chip Device ID to verify it */
+#if 0
+    I2cInstance = 0;
+    if (!Tps6586xI2cRead8(hDevice, TPS6586x_RCD_VERSIONID, &I2cInstance) || I2cInstance != 0x60)
+    {
+        NV_ASSERT(!"did not find TSP6586x");
+        goto OPEN_FAILED;
+    }
+#endif
+
+#if defined(CONFIG_TEGRA_ODM_HARMONY)
+    /* Initialize the refcont of the rails which are ON by default */
+    hPmu->supplyRefCntTable[TPS6586xPmuSupply_SoC] = 1;
+#endif
+
+#if !defined(CONFIG_TEGRA_ODM_HARMONY)
+    // If your project doesn't use this GPIO, please delete them!
+    // Enable GPIO3 to HIGH
+    // Set GPIO Configure to output
+    data = 0x10;
+    if (!Tps6586xI2cWrite8(hDevice, TPS6586x_R5D_GPIOSET1, data))
+        return NV_FALSE;
+        
+    // Set GPIO to HI, NON-Inverting
+    data = 0x04;
+    if (!Tps6586xI2cWrite8(hDevice, TPS6586x_R5E_GPIOSET2, data))
+        return NV_FALSE;
+#endif
+
+    //NvOdmOsMemset(&s_tps6586x, 0, sizeof(s_tps6586x));
+    //s_tps6586x.pmuPresented = NV_TRUE;
+    pmuPresented = NV_TRUE;
+
+#if NV_DEBUG
+    //DumpTps6586x(hDevice);
+#endif 
+
+    if (!Tps6586xBatteryChargerSetup(hDevice))
+        return NV_FALSE;
+
+    // The interrupt assumes not supported until tps6586xInterruptHandler() is called. 
+    pmuInterruptSupported = NV_FALSE;
+
+    // setup the interrupt any way.
+    if (!Tps6586xSetupInterrupt(hDevice, &pmuStatus))
+        return NV_FALSE;
+
+    //Check battery presence
+    if (!Tps6586xBatteryChargerCBCMainBatt(hDevice, &battPresence))
+        return NV_FALSE;
+   
+    // Check battery Fullness
+    if (battPresence == NV_TRUE)
+    {   
+        if (!Tps6586xBatteryChargerCBCBattFul(hDevice, &status))
+            return NV_FALSE;    
+        pmuStatus.batFull = status;
+    }
+    else
+    {
+        pmuStatus.batFull = NV_FALSE;
+    }
+
+    return NV_TRUE;
+
+OPEN_FAILED:
+    Tps6586xRelease(hDevice);
+    return NV_FALSE;
+}
+
+void Tps6586xRelease(NvOdmPmuDeviceHandle hDevice)
+{
+#if defined(CONFIG_TEGRA_ODM_HARMONY)
+    NvU32 i;
+#endif
+    if (hDevice != NULL && hPmu->hOdmI2C)
+    {
+        NvOdmServicesPmuClose(hPmu->hOdmPmuSevice);
+        hPmu->hOdmPmuSevice = NULL;
+        NvOdmI2cClose(hPmu->hOdmI2C);
+        hPmu->hOdmI2C = NULL;
+        NvOdmOsFree(hPmu);
+        hPmu = NULL;
+
+#if defined(CONFIG_TEGRA_ODM_HARMONY)
+
+        // Release & Close the GPIOs
+        for (i=0; i<(TPS6586x_EXTERNAL_SUPPLY_AP_GPIO_NUM); i++)
+        {
+            NvOdmGpioReleasePinHandle(hPmu->hGpio, hPmu->hPin[i]);
+        }
+        NvOdmGpioClose(hPmu->hGpio);
+#endif
+    }    
+}
+
+NvBool
+Tps6586xGetAcLineStatus(
+    NvOdmPmuDeviceHandle hDevice,
+    NvOdmPmuAcLineStatus *pStatus)
+{
+    NvBool acLineStatus = NV_FALSE;
+   
+    NV_ASSERT(hDevice);
+    NV_ASSERT(pStatus);
+   
+    // check if charger presents
+    if (battPresence == NV_FALSE)
+    {
+        *pStatus = NvOdmPmuAcLine_Online;
+        return NV_TRUE;
+    }
+
+    if (pmuInterruptSupported == NV_TRUE)
+    {
+        if ( pmuStatus.mChgPresent == NV_TRUE )
+        {
+            *pStatus = NvOdmPmuAcLine_Online;
+            acLineStatus = NV_TRUE;
+        }
+        else
+        {
+            *pStatus = NvOdmPmuAcLine_Offline;
+            acLineStatus = NV_FALSE;
+        }
+    }
+    else
+    {
+        // battery is present, now check if charger presents
+        if (!Tps6586xBatteryChargerMainChgPresent(hDevice, &acLineStatus))
+        {
+            NVODMPMU_PRINTF(("Error in checking main charger presence.\n"));
+            return NV_FALSE;
+        }
+
+        if (acLineStatus == NV_TRUE)
+            *pStatus = NvOdmPmuAcLine_Online;
+        else
+            *pStatus = NvOdmPmuAcLine_Offline;
+    }    
+    return NV_TRUE;
+}
+
+NvBool 
+Tps6586xGetBatteryStatus(
+    NvOdmPmuDeviceHandle hDevice, 
+    NvOdmPmuBatteryInstance batteryInst,
+    NvU8 *pStatus)
+{
+    NvU8 status = 0;
+    
+    NV_ASSERT(hDevice);
+    NV_ASSERT(pStatus);
+    NV_ASSERT(batteryInst <= NvOdmPmuBatteryInst_Num);
+
+    if (batteryInst == NvOdmPmuBatteryInst_Main)
+    {
+        if (battPresence == NV_TRUE)
+        {
+            NvOdmPmuAcLineStatus stat = NvOdmPmuAcLine_Offline;
+            NvU32 VBatSense = 0;
+            if (!Tps6586xGetAcLineStatus(hDevice, &stat))
+                return NV_FALSE;
+            
+            if (stat == NvOdmPmuAcLine_Online)
+            {
+                if (pmuInterruptSupported == NV_TRUE)
+                {
+                    if (pmuStatus.batFull == NV_FALSE)
+                        status = NVODM_BATTERY_STATUS_CHARGING;
+                }
+                else
+                {
+                    NvBool batFull = NV_FALSE;    
+                    if (!Tps6586xBatteryChargerCBCBattFul(hDevice, &batFull))
+                        return NV_FALSE;
+                    if (batFull == NV_FALSE)
+                        status = NVODM_BATTERY_STATUS_CHARGING;
+                }
+            }
+            
+            // Get VBatSense
+            if (!Tps6586xAdcVBatSenseRead(hDevice, &VBatSense))
+                return NV_FALSE;
+
+            if (VBatSense > NVODM_BATTERY_HIGH_VOLTAGE_MV)  // maybe modify these parameters
+                status |= NVODM_BATTERY_STATUS_HIGH;
+            else if ((VBatSense < NVODM_BATTERY_LOW_VOLTAGE_MV)&& 
+                (VBatSense > NVODM_BATTERY_CRITICAL_VOLTAGE_MV))
+                status |= NVODM_BATTERY_STATUS_LOW;
+            else if (VBatSense <= NVODM_BATTERY_CRITICAL_VOLTAGE_MV)
+                status |= NVODM_BATTERY_STATUS_CRITICAL;
+                
+        }
+        else
+        {
+            /* Battery is actually not present */
+            status = NVODM_BATTERY_STATUS_NO_BATTERY;
+        }
+
+        *pStatus = status;
+    }    
+    else 
+    {
+        *pStatus = NVODM_BATTERY_STATUS_UNKNOWN;
+    }
+
+    return NV_TRUE;
+}
+
+NvBool
+Tps6586xGetBatteryData(
+    NvOdmPmuDeviceHandle hDevice, 
+    NvOdmPmuBatteryInstance batteryInst,
+    NvOdmPmuBatteryData *pData)
+{
+    NvOdmPmuBatteryData batteryData;
+    
+    batteryData.batteryLifePercent     = NVODM_BATTERY_DATA_UNKNOWN;
+    batteryData.batteryLifeTime        = NVODM_BATTERY_DATA_UNKNOWN;
+    batteryData.batteryVoltage         = NVODM_BATTERY_DATA_UNKNOWN;
+    batteryData.batteryCurrent         = NVODM_BATTERY_DATA_UNKNOWN;
+    batteryData.batteryAverageCurrent  = NVODM_BATTERY_DATA_UNKNOWN;
+    batteryData.batteryAverageInterval = NVODM_BATTERY_DATA_UNKNOWN;
+    batteryData.batteryMahConsumed     = NVODM_BATTERY_DATA_UNKNOWN;
+    batteryData.batteryTemperature     = NVODM_BATTERY_DATA_UNKNOWN;
+    batteryData.batteryVoltage         = NVODM_BATTERY_DATA_UNKNOWN;
+
+    NV_ASSERT(hDevice);
+    NV_ASSERT(pData);
+    NV_ASSERT(batteryInst <= NvOdmPmuBatteryInst_Num);
+
+    if (batteryInst == NvOdmPmuBatteryInst_Main)
+    {
+        NvU32 VBatSense = 0;
+        NvU32 VBatTemp  = 0;
+
+        if (battPresence == NV_TRUE)
+        {
+            /* retrieve Battery voltage and temperature */
+            
+            // Get VBatSense
+            if (!Tps6586xAdcVBatSenseRead(hDevice, &VBatSense))
+            {
+                NVODMPMU_PRINTF(("Error reading VBATSense. \n"));
+                return NV_FALSE;
+            }
+
+            // Get VBatTemp
+            if (!Tps6586xAdcVBatTempRead(hDevice, &VBatTemp))
+            {
+                NVODMPMU_PRINTF(("Error reading VBATSense. \n"));
+                return NV_FALSE;
+            }
+
+            batteryData.batteryVoltage     = VBatSense;
+            batteryData.batteryTemperature = Tps6586xBatteryTemperature(VBatSense, VBatTemp);
+        }
+        
+        *pData = batteryData;
+    }
+    else
+    {
+        *pData = batteryData;
+    }
+
+    return NV_TRUE;
+}
+
+void
+Tps6586xGetBatteryFullLifeTime(
+    NvOdmPmuDeviceHandle hDevice, 
+    NvOdmPmuBatteryInstance batteryInst,
+    NvU32 *pLifeTime)
+{
+    *pLifeTime = NVODM_BATTERY_DATA_UNKNOWN;
+}
+
+void
+Tps6586xGetBatteryChemistry(
+    NvOdmPmuDeviceHandle hDevice, 
+    NvOdmPmuBatteryInstance batteryInst,
+    NvOdmPmuBatteryChemistry *pChemistry)
+{
+    *pChemistry = NvOdmPmuBatteryChemistry_LION;
+}
+
+
+NvBool 
+Tps6586xSetChargingCurrent(
+    NvOdmPmuDeviceHandle hDevice,
+    NvOdmPmuChargingPath chargingPath,
+    NvU32 chargingCurrentLimitMa,
+    NvOdmUsbChargerType ChargerType)
+{
+    NvU32 data = 0;
+    NV_ASSERT(hDevice);
+
+    // if no battery, then do nothing
+    if (battPresence == NV_FALSE)
+        return NV_TRUE;
+
+    if (chargingCurrentLimitMa > DEDICATED_CHARGER_LIMIT_MA)
+        chargingCurrentLimitMa = DEDICATED_CHARGER_LIMIT_MA;
+
+    if (!Tps6586xI2cRead8(hDevice, TPS6586x_R49_CHG1, &data))
+        return NV_FALSE;
+
+    if (chargingPath == NvOdmPmuChargingPath_UsbBus)
+    {
+        switch (ChargerType)
+        {
+            case NvOdmUsbChargerType_SJ:
+                chargingCurrentLimitMa = DEDICATED_CHARGER_LIMIT_MA;
+                break;
+            case NvOdmUsbChargerType_SK:
+                chargingCurrentLimitMa = DEDICATED_CHARGER_LIMIT_MA;
+                break;
+            case NvOdmUsbChargerType_SE1:
+                chargingCurrentLimitMa = DEDICATED_CHARGER_LIMIT_MA;
+                break;
+            case NvOdmUsbChargerType_SE0:
+                chargingCurrentLimitMa = DEDICATED_CHARGER_LIMIT_MA;
+                break;
+            case NvOdmUsbChargerType_Dummy:
+                chargingCurrentLimitMa = DUMB_CHARGER_LIMIT_MA;
+                break;
+            case NvOdmUsbChargerType_UsbHost:
+                default:
+                // USB Host based charging, nothing to do. Just pass current limit to PMU.
+                break;
+        }
+    }
+    
+    if (chargingCurrentLimitMa >= MAX_CHARGING_CURRENT)
+    {
+        data = data & 0xf3;
+        data = data | 0xC;
+    }
+    else if (chargingCurrentLimitMa >= L2_CHARGING_CURRENT)
+    {
+        data = data & 0xf3;
+        data = data | 0x4;
+    }
+    else if (chargingCurrentLimitMa >= L3_CHARGING_CURRENT)
+    {
+        data = data & 0xf3;
+        data = data | 0x0;
+    }
+    // 0 mA
+    else
+    {
+        chargingCurrentLimitMa = 0;
+    }
+
+    //data = (NvU8)((( chargingCurrentLimitMa << 8 ) - chargingCurrentLimitMa ) 
+    //            / CHARGER_CONSTANT_CURRENT_SET_MA );
+
+    if (!Tps6586xI2cWrite8(hDevice, TPS6586x_R49_CHG1, data))
+        return NV_FALSE;
+     
+    if (!Tps6586xI2cRead8(hDevice, TPS6586x_R4A_CHG2, &data))
+        return NV_FALSE;
+        
+    if (chargingCurrentLimitMa == 0)
+    {
+        data = data & 0xfd; // Disable charging!
+    }
+    else
+    {
+        data = data | 0x02; // Enable Charging!
+    }
+    if (!Tps6586xI2cWrite8(hDevice, TPS6586x_R4A_CHG2, data))
+        return NV_FALSE;
+
+    return NV_TRUE;
+}
+
+void Tps6586xInterruptHandler( NvOdmPmuDeviceHandle  hDevice)
+{
+    //TPS6586xHandle tps6586x = hDevice->priv;
+    //tps6586x->pmuStatus.batFull = NV_FALSE;
+    
+    // If the interrupt handle is called, the interrupt is supported.
+    pmuInterruptSupported = NV_TRUE;
+    
+    Tps6586xInterruptHandler_int(hDevice, &pmuStatus);
+}
+
+NvBool Tps6586xReadRtc( NvOdmPmuDeviceHandle  hDevice, NvU32 *Count)
+{
+    *Count = 0;
+    return (Tps6586xRtcCountRead(hDevice, Count));
+}
+
+NvBool Tps6586xWriteRtc( NvOdmPmuDeviceHandle  hDevice, NvU32 Count)
+{
+    return (Tps6586xRtcCountWrite(hDevice, Count));
+}
+
+NvBool Tps6586xIsRtcInitialized( NvOdmPmuDeviceHandle  hDevice)
+{
+    return ((Tps6586xRtcWasStartUpFromNoPower(hDevice))? NV_FALSE: NV_TRUE);
+}
diff --git a/arch/arm/mach-tegra/odm_kit/adaptations/pmu/tps6586x/nvodm_pmu_tps6586x.h b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/tps6586x/nvodm_pmu_tps6586x.h
new file mode 100644
index 000000000000..0c1f4fb2b9af
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/tps6586x/nvodm_pmu_tps6586x.h
@@ -0,0 +1,103 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef NVODM_PMU_TPS6586X_H_HH
+#define NVODM_PMU_TPS6586X_H_HH
+
+#include "nvodm_pmu.h"
+#include "nvodm_services.h"
+#include "nvodm_pmu_tps6586x_supply_info_table.h"
+#include "tps6586x_reg.h"
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+#if (NV_DEBUG)
+#define NVODMPMU_PRINTF(x)   NvOdmOsDebugPrintf x
+#else
+#define NVODMPMU_PRINTF(x)
+#endif
+
+typedef struct NvOdmPmuDeviceTPSRec
+{
+    /* The handle to the I2C */
+    NvOdmServicesI2cHandle hOdmI2C;
+
+    /* The odm pmu service handle */
+    NvOdmServicesPmuHandle hOdmPmuSevice;
+    /* the PMU I2C device Address */
+    NvU32 DeviceAddr;
+
+    /* Device's private data */
+    void *priv;
+    
+#if defined(CONFIG_TEGRA_ODM_HARMONY)
+     /* Gpio Handles (for external supplies) */
+     NvOdmServicesGpioHandle hGpio;
+     NvOdmGpioPinHandle hPin[TPS6586x_EXTERNAL_SUPPLY_AP_GPIO_NUM];
+#else
+    /* The current voltage */
+    NvU32 curVoltageTable[VRAILCOUNT];
+#endif
+
+    /* The ref cnt table of the power supplies */
+#if defined(CONFIG_TEGRA_ODM_HARMONY)
+    NvU32 supplyRefCntTable[TPS6586xPmuSupply_Num];
+#else
+    NvU32 supplyRefCntTable[VRAILCOUNT];
+#endif
+
+} NvOdmPmuDeviceTPS;
+
+void Tps6586xGetCapabilities( NvU32 vddRail, NvOdmPmuVddRailCapabilities* pCapabilities);
+NvBool Tps6586xGetVoltage( NvOdmPmuDeviceHandle hDevice, NvU32 vddRail, NvU32* pMilliVolts);
+NvBool Tps6586xSetVoltage( NvOdmPmuDeviceHandle hDevice, NvU32 vddRail, NvU32 MilliVolts, NvU32* pSettleMicroSeconds);
+NvBool Tps6586xSetup(NvOdmPmuDeviceHandle hDevice);
+void Tps6586xRelease(NvOdmPmuDeviceHandle hDevice);
+NvBool Tps6586xGetAcLineStatus( NvOdmPmuDeviceHandle hDevice, NvOdmPmuAcLineStatus *pStatus);
+NvBool Tps6586xGetBatteryStatus( NvOdmPmuDeviceHandle hDevice, NvOdmPmuBatteryInstance batteryInst, NvU8 *pStatus);
+NvBool Tps6586xGetBatteryData( NvOdmPmuDeviceHandle hDevice, NvOdmPmuBatteryInstance batteryInst, NvOdmPmuBatteryData *pData); 
+void Tps6586xGetBatteryFullLifeTime( NvOdmPmuDeviceHandle hDevice, NvOdmPmuBatteryInstance batteryInst, NvU32 *pLifeTime);
+void Tps6586xGetBatteryChemistry( NvOdmPmuDeviceHandle hDevice, NvOdmPmuBatteryInstance batteryInst, NvOdmPmuBatteryChemistry *pChemistry);
+NvBool Tps6586xSetChargingCurrent( NvOdmPmuDeviceHandle hDevice, NvOdmPmuChargingPath chargingPath, NvU32 chargingCurrentLimitMa, NvOdmUsbChargerType ChargerType); 
+void Tps6586xInterruptHandler( NvOdmPmuDeviceHandle  hDevice);
+NvBool Tps6586xReadRtc( NvOdmPmuDeviceHandle  hDevice, NvU32 *Count);
+NvBool Tps6586xWriteRtc( NvOdmPmuDeviceHandle  hDevice, NvU32 Count);
+NvBool Tps6586xIsRtcInitialized( NvOdmPmuDeviceHandle  hDevice);
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* NVODM_PMU_TPS6586X_H_HH */
diff --git a/arch/arm/mach-tegra/odm_kit/adaptations/pmu/tps6586x/nvodm_pmu_tps6586x_adc.c b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/tps6586x/nvodm_pmu_tps6586x_adc.c
new file mode 100644
index 000000000000..7f2fcb0dd54c
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/tps6586x/nvodm_pmu_tps6586x_adc.c
@@ -0,0 +1,200 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include "nvodm_pmu_tps6586x_adc.h"
+#include "nvodm_pmu_tps6586x_i2c.h"
+#include "tps6586x_reg.h"
+#include "nvodm_pmu_tps6586x_supply_info_table.h"
+
+#define ADC_CONVERSION_DELAY_USEC      70
+#define ADC_CONVERSION_TIMEOUT_USEC    500
+#define ADC_CONVERSION_VOLTAGE_RANGE   2000
+#define ADC_CONVERSION_DIVIDOR         3
+#define ADC_CONVERSION_PRECISION       10
+#define ADC_CONVERSION_SUB_OFFSET      2250
+#define ADC_FULL_SCALE_READING_MV_BAT  4622
+#define ADC_FULL_SCALE_READING_MV_TS   2600
+#define ADC_CONVERSION_PREWAIT_MS      26
+
+/* read voltage from ADC CH10(battery) */
+NvBool 
+Tps6586xAdcVBatSenseRead(NvOdmPmuDeviceHandle hDevice, NvU32 *volt)
+{
+    NvU32 timeout  = 0;
+    NvU32  dataS1  = 0;
+    NvU32  dataH   = 0;
+    NvU32  dataL   = 0;
+
+    NV_ASSERT(hDevice);
+    NV_ASSERT(volt);
+    
+    *volt = 0;    // Default is 0mV. 
+    // Configuring the adc conversion cycle
+    // ADC0_WAIT register(0x62)
+    // Reset all ADC engines and return them to the idle state; ADC0_RESET: 1
+    if(! Tps6586xI2cWrite8(hDevice, TPS6586x_R62_ADC0_WAIT, 0x80))
+        return NV_FALSE;
+        
+    // ADC0_SET register(0x61)
+    // ADC0_EN: 0(Don't start conversion); Number of Readings: 16; CHANNEL: CH10(battery)
+    if(! Tps6586xI2cWrite8(hDevice, TPS6586x_R61_ADC0_SET, 0x19))
+        return NV_FALSE;
+        
+    // ADC0_WAIT register(0x62)
+    // REF_EN: 0; AUTO_REF: 1; Wait time: 0.062ms
+    if(! Tps6586xI2cWrite8(hDevice, TPS6586x_R62_ADC0_WAIT, 0x21))
+        return NV_FALSE;
+
+    // Start conversion!!
+    if(! Tps6586xI2cWrite8(hDevice, TPS6586x_R61_ADC0_SET, 0x99))
+        return NV_FALSE;
+
+    // Wait for conversion
+    //NvOdmOsWaitUS(ADC_CONVERSION_DELAY_USEC);
+    NvOdmOsSleepMS(ADC_CONVERSION_PREWAIT_MS);
+
+    // Make sure the conversion is completed - check for ADC error.
+    while (1)
+    {
+        // Read ADC status register
+        if(! Tps6586xI2cRead8(hDevice, TPS6586x_R9A_ADC0_INT, &dataS1))
+            return NV_FALSE;
+
+        // Conversion is done!
+        if (dataS1 & 0x80)
+            break;
+        
+        // ADC error!
+        if (dataS1 & 0x40)
+        {
+            NVODMPMU_PRINTF(("ADC conversion error.\n"));
+            return NV_FALSE;
+        }
+
+        NvOdmOsWaitUS(ADC_CONVERSION_DELAY_USEC);
+        timeout += ADC_CONVERSION_DELAY_USEC;
+        if (timeout >= ADC_CONVERSION_TIMEOUT_USEC)
+            return NV_FALSE;
+    }
+
+    // Read the ADC conversion Average (SUM).
+    if (!Tps6586xI2cRead8(hDevice, TPS6586x_R94_ADC0_SUM2, &dataH))
+        return NV_FALSE;
+        
+    if (!Tps6586xI2cRead8(hDevice, TPS6586x_R95_ADC0_SUM1, &dataL))
+        return NV_FALSE;
+
+    // Get a result value with mV.
+    *volt = (((dataH << 8) | dataL) * ADC_FULL_SCALE_READING_MV_BAT) / 1023 / 16;
+
+    return NV_TRUE;
+}
+
+/* read voltage from ADC CH5(temperature) */
+NvBool
+Tps6586xAdcVBatTempRead(NvOdmPmuDeviceHandle hDevice, NvU32 *volt)
+{
+    NvU32 timeout  = 0;
+    NvU32  dataS1  = 0;
+    NvU32  dataH   = 0;
+    NvU32  dataL   = 0;
+
+    NV_ASSERT(hDevice);
+    NV_ASSERT(volt);
+    
+    *volt = 0;    // Default is 0'C. 
+    
+    // Configuring the adc conversion cycle    
+    // ADC0_WAIT register(0x62)
+    // Reset all ADC engines and return them to the idle state; ADC0_RESET: 1
+    if(! Tps6586xI2cWrite8(hDevice, TPS6586x_R62_ADC0_WAIT, 0x80))
+        return NV_FALSE; 
+    // ADC0_SET register(0x61)
+    // ADC0_EN: 0(Don't start conversion); Number of Readings: 16; CHANNEL: CH5(temperature)
+    if(! Tps6586xI2cWrite8(hDevice, TPS6586x_R61_ADC0_SET, 0x14))
+        return NV_FALSE;
+        
+    // ADC0_WAIT register(0x62)
+    // REF_EN: 0; AUTO_REF: 1; Wait time: 0.062ms
+    if(! Tps6586xI2cWrite8(hDevice, TPS6586x_R62_ADC0_WAIT, 0x21))
+        return NV_FALSE;
+
+    // Start conversion!!
+    if(! Tps6586xI2cWrite8(hDevice, TPS6586x_R61_ADC0_SET, 0x94))
+        return NV_FALSE;
+
+    // Wait for conversion
+    // NvOdmOsWaitUS(ADC_CONVERSION_DELAY_USEC);
+    NvOdmOsSleepMS(ADC_CONVERSION_PREWAIT_MS);
+
+    // make sure the conversion is completed, or adc error.
+    while (1)
+    {
+        // Read ADC status register
+        if(! Tps6586xI2cRead8(hDevice, TPS6586x_R9A_ADC0_INT, &dataS1))
+            return NV_FALSE;
+
+        // Conversion is done!
+        if (dataS1 & 0x80)
+            break;
+        
+        // ADC error!
+        if (dataS1 & 0x40)
+        {
+            NVODMPMU_PRINTF(("ADC conversion error.\n"));
+            return NV_FALSE;
+        }
+
+        NvOdmOsWaitUS(ADC_CONVERSION_DELAY_USEC);
+        timeout += ADC_CONVERSION_DELAY_USEC;
+        if (timeout >= ADC_CONVERSION_TIMEOUT_USEC)
+            return NV_FALSE;
+    }
+
+    // Read the ADC conversion Average (SUM).
+    if (!Tps6586xI2cRead8(hDevice, TPS6586x_R94_ADC0_SUM2, &dataH))
+        return NV_FALSE;
+        
+    if (!Tps6586xI2cRead8(hDevice, TPS6586x_R95_ADC0_SUM1, &dataL))
+        return NV_FALSE;
+
+    // Get a result value with mV.
+    *volt = (((dataH << 8) | dataL) *  ADC_FULL_SCALE_READING_MV_TS) / 1023 / 16;
+
+    return NV_TRUE;
+}
+
+/* Calculate the battery temperature */
+NvU32 Tps6586xBatteryTemperature(NvU32 VBatSense, NvU32 VBatTemp)
+{
+    return 0;
+}
diff --git a/arch/arm/mach-tegra/odm_kit/adaptations/pmu/tps6586x/nvodm_pmu_tps6586x_adc.h b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/tps6586x/nvodm_pmu_tps6586x_adc.h
new file mode 100644
index 000000000000..803a62856a9b
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/tps6586x/nvodm_pmu_tps6586x_adc.h
@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_TPS6586X_ADC_HEADER
+#define INCLUDED_TPS6586X_ADC_HEADER
+
+/* the ADC is used for battery voltage conversion */
+#include "nvodm_pmu_tps6586x.h"
+
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+/* read voltage from adc */
+NvBool 
+Tps6586xAdcVBatSenseRead(
+    NvOdmPmuDeviceHandle hDevice, 
+    NvU32 *volt);
+
+/* read bat temperature voltage from ADC */
+NvBool 
+Tps6586xAdcVBatTempRead(
+    NvOdmPmuDeviceHandle hDevice, 
+    NvU32 *volt);
+
+/* Calculate the battery temperature */
+NvU32
+Tps6586xBatteryTemperature(
+    NvU32 VBatSense,
+    NvU32 VBatTemp);
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif // INCLUDED_TPS6586X_ADC_HEADER
diff --git a/arch/arm/mach-tegra/odm_kit/adaptations/pmu/tps6586x/nvodm_pmu_tps6586x_batterycharger.c b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/tps6586x/nvodm_pmu_tps6586x_batterycharger.c
new file mode 100644
index 000000000000..8a4573922adf
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/tps6586x/nvodm_pmu_tps6586x_batterycharger.c
@@ -0,0 +1,109 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include "nvodm_pmu_tps6586x_i2c.h"
+#include "nvodm_pmu_tps6586x_batterycharger.h"
+
+NvBool Tps6586xBatteryChargerSetup(NvOdmPmuDeviceHandle hDevice)
+{
+    NvU32 data = 0;
+    // Configure CHARGER RAM registers
+    // CHG1: Charge safety timer value is 4 Hrs; Charge current scaling facotr: 1.0; 
+    data = 0x0c;
+    if (!Tps6586xI2cWrite8(hDevice, TPS6586x_R49_CHG1, data))
+        return NV_FALSE;
+        
+    // CHG2: CHARGE SAFETY TIMER: ON; CHARGE VOLTAGE: 4.2V; CHARGER: ON;
+    data = 0x1a;
+    if (!Tps6586xI2cWrite8(hDevice, TPS6586x_R4A_CHG2, data))
+        return NV_FALSE;
+
+    // CHG3:
+    data = 0x0;
+    if (!Tps6586xI2cWrite8(hDevice, TPS6586x_R4B_CHG3, data))
+        return NV_FALSE;
+        
+    // RAM Control BITS: CHARGE VOLTAGE RANGE: 3.95 - 4.2; USB Input current limit: 500mA;
+    // Auto mode enabled; AC input current limit: 2A
+    data = 0x05;
+    if (!Tps6586xI2cWrite8(hDevice, TPS6586x_R4C_PPATH2, data))
+        return NV_FALSE;
+
+    return NV_TRUE;
+}
+
+/* check CBC main batt presence */
+NvBool
+Tps6586xBatteryChargerCBCMainBatt(NvOdmPmuDeviceHandle hDevice, NvBool *status)
+{
+    NvU32 data = 0;
+    
+    if (!Tps6586xI2cRead8(hDevice, TPS6586x_RB9_STAT1, &data))
+        return NV_FALSE;
+
+    // bit 0 show if battery exists or not
+    data = data & 0x01;
+    
+    *status = (data == 0 ? NV_FALSE : NV_TRUE ); 
+
+    return NV_TRUE;
+}
+
+/* check batt_ful status */
+NvBool
+Tps6586xBatteryChargerCBCBattFul(NvOdmPmuDeviceHandle hDevice, NvBool *status)
+{
+    NvU32 data = 0;
+    
+    if(! Tps6586xI2cRead8(hDevice, TPS6586x_RBA_STAT2, &data))
+        return NV_FALSE;
+
+    data = data & 0x2;
+    *status = (data == 0 ? NV_FALSE : NV_TRUE ); 
+
+    return NV_TRUE;
+}
+
+/* check main charger status */
+NvBool
+Tps6586xBatteryChargerMainChgPresent(NvOdmPmuDeviceHandle hDevice, NvBool *status)
+{
+    NvU32 data = 0;
+    
+    if(! Tps6586xI2cRead8(hDevice, TPS6586x_RBB_STAT3, &data))
+        return NV_FALSE;
+
+    data = data & 0xc;
+    *status = (data == 0 ? NV_FALSE : NV_TRUE ); 
+
+    return NV_TRUE;
+}
diff --git a/arch/arm/mach-tegra/odm_kit/adaptations/pmu/tps6586x/nvodm_pmu_tps6586x_batterycharger.h b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/tps6586x/nvodm_pmu_tps6586x_batterycharger.h
new file mode 100644
index 000000000000..83b538792334
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/tps6586x/nvodm_pmu_tps6586x_batterycharger.h
@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_TPS6586X_BATTERYCHARGER_HEADER
+#define INCLUDED_TPS6586X_BATTERYCHARGER_HEADER
+
+
+
+#include "nvodm_pmu_tps6586x.h"
+
+/* the battery charger functions */
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+/* Initliase all registers that related to battery charger */
+NvBool 
+Tps6586xBatteryChargerSetup(NvOdmPmuDeviceHandle hDevice);
+
+/* check CBC main batt presence */
+NvBool
+Tps6586xBatteryChargerCBCMainBatt(NvOdmPmuDeviceHandle hDevice, NvBool *status);
+
+/* check batt_ful status */
+NvBool
+Tps6586xBatteryChargerCBCBattFul(NvOdmPmuDeviceHandle hDevice, NvBool *status);
+
+/* check main charger status */
+NvBool
+Tps6586xBatteryChargerMainChgPresent(NvOdmPmuDeviceHandle hDevice, NvBool *status);
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif // INCLUDED_TPS6586X_BATTERYCHARGER_HEADER
+
diff --git a/arch/arm/mach-tegra/odm_kit/adaptations/pmu/tps6586x/nvodm_pmu_tps6586x_i2c.c b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/tps6586x/nvodm_pmu_tps6586x_i2c.c
new file mode 100644
index 000000000000..94e806101b10
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/tps6586x/nvodm_pmu_tps6586x_i2c.c
@@ -0,0 +1,207 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include "nvodm_pmu_tps6586x_i2c.h"
+#include "nvodm_pmu_tps6586x.h"
+#include "pmu_hal.h"
+
+NvBool 
+Tps6586xI2cWrite8(
+    NvOdmPmuDeviceHandle hPmu,
+    NvU32 Addr,
+    NvU32 Data)
+{  
+    NvU8 WriteBuffer[2];
+    NvOdmI2cStatus status = NvOdmI2cStatus_Success;    
+    NvOdmI2cTransactionInfo TransactionInfo = {0};
+
+    WriteBuffer[0] = Addr & 0xFF;   // PMU offset
+    WriteBuffer[1] = Data & 0xFF;   // written data
+
+    TransactionInfo.Address = ((NvOdmPmuDeviceTPS *)(hPmu->pPrivate))->DeviceAddr;
+    TransactionInfo.Buf = &WriteBuffer[0];
+    TransactionInfo.Flags = NVODM_I2C_IS_WRITE;
+    TransactionInfo.NumBytes = 2;
+
+    status = NvOdmI2cTransaction(((NvOdmPmuDeviceTPS *)(hPmu->pPrivate))->hOdmI2C, &TransactionInfo, 1, 
+                        TPS6586x_I2C_SPEED_KHZ, NV_WAIT_INFINITE);
+    if (status == NvOdmI2cStatus_Success)
+    {
+        return NV_TRUE;
+    }
+    else
+    {
+        switch (status)
+        {
+            case NvOdmI2cStatus_Timeout:
+                NVODMPMU_PRINTF(("NvOdmPmuI2cWrite8 Failed: Timeout\n")); 
+                break;
+             case NvOdmI2cStatus_SlaveNotFound:
+             default:
+                NVODMPMU_PRINTF(("NvOdmPmuI2cWrite8 Failed: SlaveNotFound\n"));
+                break;             
+        }
+        return NV_FALSE;
+    }    
+}
+
+NvBool
+Tps6586xI2cRead8(
+    NvOdmPmuDeviceHandle hPmu,
+    NvU32 Addr,
+    NvU32 *Data)
+{
+    NvU8 ReadBuffer=0;
+    NvOdmI2cStatus status = NvOdmI2cStatus_Success;    
+    NvOdmI2cTransactionInfo TransactionInfo[2];
+
+    // Write the PMU offset
+    ReadBuffer = Addr & 0xFF;
+
+    TransactionInfo[0].Address = ((NvOdmPmuDeviceTPS *)(hPmu->pPrivate))->DeviceAddr;
+    TransactionInfo[0].Buf = &ReadBuffer;
+    TransactionInfo[0].Flags = NVODM_I2C_IS_WRITE;
+    TransactionInfo[0].NumBytes = 1;    
+    TransactionInfo[1].Address = (((NvOdmPmuDeviceTPS *)(hPmu->pPrivate))->DeviceAddr | 0x1);
+    TransactionInfo[1].Buf = &ReadBuffer;
+    TransactionInfo[1].Flags = 0;
+    TransactionInfo[1].NumBytes = 1;
+
+    // Read data from PMU at the specified offset
+    status = NvOdmI2cTransaction(((NvOdmPmuDeviceTPS *)(hPmu->pPrivate))->hOdmI2C, &TransactionInfo[0], 2, 
+                                    TPS6586x_I2C_SPEED_KHZ, NV_WAIT_INFINITE);
+    if (status != NvOdmI2cStatus_Success)
+    {
+        switch (status)
+        {
+            case NvOdmI2cStatus_Timeout:
+                NVODMPMU_PRINTF(("NvOdmPmuI2cRead8 Failed: Timeout\n")); 
+                break;
+             case NvOdmI2cStatus_SlaveNotFound:
+             default:
+                NVODMPMU_PRINTF(("NvOdmPmuI2cRead8 Failed: SlaveNotFound\n"));
+                break;             
+        }
+        return NV_FALSE;
+    }  
+
+    *Data = ReadBuffer;
+    return NV_TRUE;
+}
+
+NvBool Tps6586xI2cWrite32(
+    NvOdmPmuDeviceHandle hPmu,
+    NvU32 Addr,
+    NvU32 Data)
+{
+    NvU8 WriteBuffer[5];
+    NvOdmI2cStatus status = NvOdmI2cStatus_Success;
+    NvOdmI2cTransactionInfo TransactionInfo = {0};
+    
+    WriteBuffer[0] = (NvU8)(Addr & 0xFF);  
+    WriteBuffer[1] = (NvU8)((Data >> 24) & 0xFF);
+    WriteBuffer[2] = (NvU8)((Data >> 16) & 0xFF);
+    WriteBuffer[3] = (NvU8)((Data >>  8) & 0xFF);
+    WriteBuffer[4] = (NvU8)(Data & 0xFF);
+
+    TransactionInfo.Address = ((NvOdmPmuDeviceTPS *)(hPmu->pPrivate))->DeviceAddr;
+    TransactionInfo.Buf = &WriteBuffer[0];
+    TransactionInfo.Flags = NVODM_I2C_IS_WRITE;
+    TransactionInfo.NumBytes = 5;
+
+    status = NvOdmI2cTransaction(((NvOdmPmuDeviceTPS *)(hPmu->pPrivate))->hOdmI2C, &TransactionInfo, 1, 
+                        TPS6586x_I2C_SPEED_KHZ, NV_WAIT_INFINITE);
+    if (status == NvOdmI2cStatus_Success)
+    {
+        return NV_TRUE;
+    }
+    else
+    {
+        switch (status)
+        {
+            case NvOdmI2cStatus_Timeout:
+                NVODMPMU_PRINTF(("NvOdmPmuI2cWrite8 Failed: Timeout\n")); 
+                break;
+             case NvOdmI2cStatus_SlaveNotFound:
+             default:
+                NVODMPMU_PRINTF(("NvOdmPmuI2cWrite8 Failed: SlaveNotFound\n"));
+                break;             
+        }
+        return NV_FALSE;
+    }
+}    
+    
+NvBool Tps6586xI2cRead32(
+    NvOdmPmuDeviceHandle hPmu,
+    NvU32 Addr,
+    NvU32 *Data)
+{
+    NvU8 ReadBuffer[5];
+    NvOdmI2cStatus status = NvOdmI2cStatus_Success;    
+    NvOdmI2cTransactionInfo TransactionInfo[2];
+
+    // Write the PMU offset
+    ReadBuffer[0] = Addr & 0xFF;
+
+    TransactionInfo[0].Address = ((NvOdmPmuDeviceTPS *)(hPmu->pPrivate))->DeviceAddr;
+    TransactionInfo[0].Buf = &ReadBuffer[0];
+    TransactionInfo[0].Flags = NVODM_I2C_IS_WRITE;
+    TransactionInfo[0].NumBytes = 1;
+  
+    TransactionInfo[1].Address = (((NvOdmPmuDeviceTPS *)(hPmu->pPrivate))->DeviceAddr | 0x1);
+    TransactionInfo[1].Buf = &ReadBuffer[0];
+    TransactionInfo[1].Flags = 0;
+    TransactionInfo[1].NumBytes = 4;
+
+    // Read data from PMU at the specified offset
+    status = NvOdmI2cTransaction(((NvOdmPmuDeviceTPS *)(hPmu->pPrivate))->hOdmI2C, &TransactionInfo[0], 2, 
+                                    TPS6586x_I2C_SPEED_KHZ, NV_WAIT_INFINITE);
+    if (status != NvOdmI2cStatus_Success)
+    {
+        switch (status)
+        {
+            case NvOdmI2cStatus_Timeout:
+                NVODMPMU_PRINTF(("NvOdmPmuI2cRead8 Failed: Timeout\n")); 
+                break;
+             case NvOdmI2cStatus_SlaveNotFound:
+             default:
+                NVODMPMU_PRINTF(("NvOdmPmuI2cRead8 Failed: SlaveNotFound\n"));
+                break;             
+        }
+        return NV_FALSE;
+    }  
+
+    *Data = (ReadBuffer[0] << 24) | (ReadBuffer[1] << 16) |
+            (ReadBuffer[2] <<  8) |  ReadBuffer[3];
+    return NV_TRUE;
+}
+
diff --git a/arch/arm/mach-tegra/odm_kit/adaptations/pmu/tps6586x/nvodm_pmu_tps6586x_i2c.h b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/tps6586x/nvodm_pmu_tps6586x_i2c.h
new file mode 100644
index 000000000000..df17ff6c2cf0
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/tps6586x/nvodm_pmu_tps6586x_i2c.h
@@ -0,0 +1,74 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_NVODM_PMU_TPS6856X_I2C_H
+#define INCLUDED_NVODM_PMU_TPS6856X_I2C_H
+
+#include "nvodm_pmu_tps6586x.h"
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+// Constant definition
+#define TPS6586x_I2C_SPEED_KHZ   100
+
+// Function declaration
+NvBool Tps6586xI2cWrite8(
+    NvOdmPmuDeviceHandle hPmu,
+    NvU32 Addr,
+    NvU32 Data);
+
+NvBool Tps6586xI2cRead8(
+    NvOdmPmuDeviceHandle hPmu,
+    NvU32 Addr,
+    NvU32 *Data);
+    
+NvBool Tps6586xI2cWrite32(
+    NvOdmPmuDeviceHandle hPmu,
+    NvU32 Addr,
+    NvU32 Data);
+    
+NvBool Tps6586xI2cRead32(
+    NvOdmPmuDeviceHandle hPmu,
+    NvU32 Addr,
+    NvU32 *Data);
+    
+
+#if defined(__cplusplus)
+}
+#endif
+
+/** @} */
+
+#endif // INCLUDED_NVODM_PMU_TPS6856X_I2C_H
diff --git a/arch/arm/mach-tegra/odm_kit/adaptations/pmu/tps6586x/nvodm_pmu_tps6586x_interrupt.c b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/tps6586x/nvodm_pmu_tps6586x_interrupt.c
new file mode 100644
index 000000000000..b3ac0b954a4e
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/tps6586x/nvodm_pmu_tps6586x_interrupt.c
@@ -0,0 +1,150 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+
+#include "nvodm_pmu_tps6586x_interrupt.h"
+#include "nvodm_pmu_tps6586x_i2c.h"
+#include "nvodm_pmu_tps6586x_supply_info_table.h"
+#include "nvodm_services.h"
+#include "nvodm_pmu_tps6586x_batterycharger.h"
+
+#define TPS6586X_INT_BATT_INST 0x01
+#define TPS6586X_INT_PACK_COLD_DET 0x02
+#define TPS6586X_INT_PACK_HOT_DET 0x04
+
+#define TPS6586X_INT_USB_DETECTION 0x04
+#define TPS6586X_INT_AC_DETECTION  0x08
+#define TPS6586X_INT_LOWSYS_DETECTION 0x40
+
+NvBool Tps6586xSetupInterrupt(NvOdmPmuDeviceHandle  hDevice,
+                              TPS6586xStatus *pmuStatus)
+{
+    NvBool status = NV_FALSE;
+    NvU32   data = 0;
+
+    NV_ASSERT(hDevice);
+    NV_ASSERT(pmuStatus);
+
+    /* Init Pmu Status */
+    pmuStatus->lowBatt    = NV_FALSE;
+    pmuStatus->highTemp   = NV_FALSE;
+
+    if (!Tps6586xBatteryChargerMainChgPresent(hDevice,&status))
+        return NV_FALSE;
+    pmuStatus->mChgPresent = status;
+
+    /* Set up Interrupt Mask */
+    /* Mask1 */
+    data = 0xFF;
+    if(! Tps6586xI2cWrite8(hDevice, TPS6586x_RB0_INT_MASK1, data ))
+        return NV_FALSE;
+
+    /* Mask2 */
+    data = 0xFF;
+    if(! Tps6586xI2cWrite8(hDevice, TPS6586x_RB1_INT_MASK2, data ))
+        return NV_FALSE;
+
+    /* Mask3: Battery detction, etc */
+    data = 0;
+    data = (NvU32)~(TPS6586X_INT_BATT_INST|TPS6586X_INT_PACK_COLD_DET|TPS6586X_INT_PACK_HOT_DET);
+    if(! Tps6586xI2cWrite8(hDevice, TPS6586x_RB2_INT_MASK3, data ))
+        return NV_FALSE;
+
+    /* Mask4 */
+    data = 0xFF;
+    if(! Tps6586xI2cWrite8(hDevice, TPS6586x_RB3_INT_MASK4, data ))
+        return NV_FALSE;
+
+    /* Mask5: USB Detection; AC Detection; Low System detection;  */
+    data = 0;
+    data = (NvU32) ~(TPS6586X_INT_USB_DETECTION|TPS6586X_INT_AC_DETECTION|TPS6586X_INT_LOWSYS_DETECTION);
+    if(! Tps6586xI2cWrite8(hDevice, TPS6586x_RB4_INT_MASK5, data ))
+        return NV_FALSE;
+
+    return NV_TRUE;
+}
+
+void Tps6586xInterruptHandler_int(NvOdmPmuDeviceHandle  hDevice,
+                                  TPS6586xStatus *pmuStatus)
+{
+    NvU32   data = 0;
+
+    /* INT_ACK1 */
+    if (!Tps6586xI2cRead8(hDevice, TPS6586x_RB5_INT_ACK1, &data))
+    {
+        return;
+    }
+    pmuStatus->powerGood = (data & 0xFF);
+
+
+    /* INT_ACK2 */
+    if (!Tps6586xI2cRead8(hDevice, TPS6586x_RB6_INT_ACK2, &data))
+    {
+        return;
+    }
+    pmuStatus->powerGood |= ((data & 0xFF)<<8);
+
+    /* INT_ACK3 */
+    /* LOW SYS */
+    if (!Tps6586xI2cRead8(hDevice, TPS6586x_RB7_INT_ACK3, &data))
+    {
+        return;
+    }
+    if (data != 0)
+    {
+        if (data&0x40)
+        {
+            pmuStatus->highTemp = NV_TRUE;
+        }
+        if (data&0xc0)
+        {
+            pmuStatus->mChgPresent = NV_TRUE;
+#if !defined(CONFIG_TEGRA_ODM_HARMONY)
+            NvOdmEnableOtgCircuitry(NV_TRUE);
+#endif
+        }
+    }
+
+    /* INT_ACK4 */
+    /* CHG TEMP */
+    if (!Tps6586xI2cRead8(hDevice, TPS6586x_RB8_INT_ACK4, &data))
+    {
+        return;
+    }
+    if (data != 0)
+    {
+        if (data&0x02)
+        {
+            pmuStatus->lowBatt = NV_TRUE;
+        }
+    }
+}
diff --git a/arch/arm/mach-tegra/odm_kit/adaptations/pmu/tps6586x/nvodm_pmu_tps6586x_interrupt.h b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/tps6586x/nvodm_pmu_tps6586x_interrupt.h
new file mode 100644
index 000000000000..8e9ff0464135
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/tps6586x/nvodm_pmu_tps6586x_interrupt.h
@@ -0,0 +1,93 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_TPS6586X_INTERRUPT_HEADER
+#define INCLUDED_TPS6586X_INTERRUPT_HEADER
+
+#include "nvodm_pmu_tps6586x.h"
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+typedef struct TPS6586xStatusRef
+{
+    /* Low Battery voltage detected by BVM */
+    NvBool lowBatt;
+
+    /* PMU high temperature */
+    NvBool highTemp;
+
+    /* Main charger Presents */
+    NvBool mChgPresent;
+
+    /* battery Full */
+    NvBool batFull;
+
+    /* Porwer In type*/
+    NvU32   powerType;      /* Bit meanings:
+                                0: AC_DET, 
+                                1: USB_DET,
+                                2: BAT_DET */                           
+    NvU32   powerGood;      /* Bit meanings:
+                                0-7: LDO0 to LDO7 
+                                10-11: LDO8 and LDO9,
+                                12-15: SMO0 to SM11 */
+}TPS6586xStatus;
+
+#if 0
+typedef struct {
+    NvBool pmuInterruptSupported;
+    NvBool pmuPresented; 
+    NvBool battPresence;
+    TPS6586xStatus pmuStatus;
+} TPS6586xDevice, *TPS6586xHandle;
+#endif
+
+NvBool 
+Tps6586xSetupInterrupt(
+    NvOdmPmuDeviceHandle hDevice,
+    TPS6586xStatus *pmuStatus);
+
+
+
+void 
+Tps6586xInterruptHandler_int(
+    NvOdmPmuDeviceHandle hDevice,
+    TPS6586xStatus *pmuStatus);
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif // INCLUDED_TPS6586X_INTERRUPT_HEADER
diff --git a/arch/arm/mach-tegra/odm_kit/adaptations/pmu/tps6586x/nvodm_pmu_tps6586x_rtc.c b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/tps6586x/nvodm_pmu_tps6586x_rtc.c
new file mode 100644
index 000000000000..889cf2bbc6ff
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/tps6586x/nvodm_pmu_tps6586x_rtc.c
@@ -0,0 +1,193 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include <linux/time.h>
+#include "nvodm_pmu_tps6586x_rtc.h"
+#include "nvodm_pmu_tps6586x_i2c.h"
+#include "tps6586x_reg.h"
+
+// macro OFFSET_BASE_YEAR if 1, uses epoch as reference year instead of 1970
+// This is because RTC in PMU TPS6586x can store duration of 34 years,
+// else we cannot retain date beyond 2004
+#define OFFSET_BASE_YEAR 1
+#if OFFSET_BASE_YEAR
+static unsigned long epoch = 2009;
+static unsigned long epoch_sec = 0;
+#endif
+
+static NvBool bRtcNotInitialized = NV_TRUE;
+
+/* Read RTC count register */
+NvBool
+Tps6586xRtcCountRead(
+    NvOdmPmuDeviceHandle hDevice,
+    NvU32* Count)
+{
+    NvU32 ReadBuffer[2];
+
+    // 1) The I2C address pointer must not be left pointing in the range 0xC6 to 0xCA
+    // 2) The maximum time for the address pointer to be in this range is 1ms
+    // 3) Always read RTC_ALARM2 in the following order to prevent the address pointer
+    // from stopping at 0xC6: RTC_ALARM2_LO, then RTC_ALARM2_HI
+
+    if (Tps6586xRtcWasStartUpFromNoPower(hDevice) && bRtcNotInitialized)
+    {
+        Tps6586xRtcCountWrite(hDevice, 0);
+        *Count = 0;
+    }
+    else
+    {
+        // The unit of the RTC count is second!!! 1024 tick = 1s.
+        // Read all 40 bit and right move 10 = Read the hightest 32bit and right move 2
+        Tps6586xI2cRead32(hDevice, TPS6586x_RC6_RTC_COUNT4, &ReadBuffer[0]);
+
+        Tps6586xI2cRead8(hDevice, TPS6586x_RCA_RTC_COUNT0, &ReadBuffer[1]);
+
+        Tps6586xI2cRead8(hDevice, TPS6586x_RC0_RTC_CTRL, &ReadBuffer[1]);
+
+        // return second
+        *Count = ReadBuffer[0]>>2;
+    }
+#if OFFSET_BASE_YEAR
+    // calculate epoch_sec once
+    if (!epoch_sec)
+        epoch_sec = mktime(epoch,1,1,0,0,0);
+    *Count += epoch_sec;
+#endif
+
+    return NV_TRUE;
+}
+
+/* Write RTC count register */
+
+NvBool
+Tps6586xRtcCountWrite(
+    NvOdmPmuDeviceHandle hDevice,
+    NvU32 Count)
+{
+    NvU32 ReadBuffer = 0;
+#if OFFSET_BASE_YEAR
+    // calculate epoch_sec once
+    if (!epoch_sec)
+        epoch_sec = mktime(epoch,1,1,0,0,0);
+    if (Count < (NvU32)epoch_sec)
+    {
+        // prevent setting date earlier than 'epoch'
+        pr_warning("\n Date being set cannot be earlier than least "
+            "year=%d. Setting as least year. ", (int)epoch);
+        // base year seconds count is 0
+        Count = 0;
+    }
+    else
+        Count -= (NvU32)epoch_sec;
+#endif
+
+    // Switch to 32KHz crystal oscillator
+    // POR_SRC_SEL=1 and OSC_SRC_SEL=1
+    Tps6586xI2cRead8(hDevice, TPS6586x_RC0_RTC_CTRL, &ReadBuffer);
+    ReadBuffer = ReadBuffer | 0xC0;
+    Tps6586xI2cWrite8(hDevice, TPS6586x_RC0_RTC_CTRL, ReadBuffer);
+
+    // To enable incrementing of the RTC_COUNT[39:0] from an initial value set by the host,
+    // the RTC_ENABLE bit should be written to 1 only after the RTC_OUT voltage reaches
+    // the operating range
+
+    // Clear RTC_ENABLE before writing RTC_COUNT
+    Tps6586xI2cRead8(hDevice, TPS6586x_RC0_RTC_CTRL, &ReadBuffer);
+    ReadBuffer = ReadBuffer & 0xDF;
+    Tps6586xI2cWrite8(hDevice, TPS6586x_RC0_RTC_CTRL, ReadBuffer);
+
+    Tps6586xI2cWrite32(hDevice, TPS6586x_RC6_RTC_COUNT4, (Count<<2));
+    Tps6586xI2cWrite8(hDevice,  TPS6586x_RCA_RTC_COUNT0, 0);
+
+    // Set RTC_ENABLE after writing RTC_COUNT
+    Tps6586xI2cRead8(hDevice, TPS6586x_RC0_RTC_CTRL, &ReadBuffer);
+    ReadBuffer = ReadBuffer | 0x20;
+    Tps6586xI2cWrite8(hDevice, TPS6586x_RC0_RTC_CTRL, ReadBuffer);
+
+    if (bRtcNotInitialized)
+        bRtcNotInitialized = NV_FALSE;
+
+    return NV_TRUE;
+}
+
+/* Read RTC alarm count register */
+
+NvBool
+Tps6586xRtcAlarmCountRead(
+    NvOdmPmuDeviceHandle hDevice,
+    NvU32* Count)
+{
+    return NV_FALSE;
+}
+
+/* Write RTC alarm count register */
+
+NvBool
+Tps6586xRtcAlarmCountWrite(
+    NvOdmPmuDeviceHandle hDevice,
+    NvU32 Count)
+{
+    return NV_FALSE;
+}
+
+/* Reads RTC alarm interrupt mask status */
+
+NvBool
+Tps6586xRtcIsAlarmIntEnabled(NvOdmPmuDeviceHandle hDevice)
+{
+    return NV_FALSE;
+}
+
+/* Enables / Disables the RTC alarm interrupt */
+
+NvBool
+Tps6586xRtcAlarmIntEnable(
+    NvOdmPmuDeviceHandle hDevice,
+    NvBool Enable)
+{
+    return NV_FALSE;
+}
+
+/* Checks if boot was from nopower / powered state */
+
+NvBool
+Tps6586xRtcWasStartUpFromNoPower(NvOdmPmuDeviceHandle hDevice)
+{
+    NvU32 Data = 0;
+
+    if ((Tps6586xI2cRead8(hDevice, TPS6586x_RC0_RTC_CTRL, &Data)) == NV_TRUE)
+    {
+        return ((Data & 0x20)? NV_FALSE : NV_TRUE);
+    }
+    return NV_FALSE;
+}
diff --git a/arch/arm/mach-tegra/odm_kit/adaptations/pmu/tps6586x/nvodm_pmu_tps6586x_rtc.h b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/tps6586x/nvodm_pmu_tps6586x_rtc.h
new file mode 100644
index 000000000000..8137c95e1702
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/tps6586x/nvodm_pmu_tps6586x_rtc.h
@@ -0,0 +1,93 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_TPS6586X_RTC_HEADER
+#define INCLUDED_TPS6586X_RTC_HEADER
+
+#include "nvodm_pmu_tps6586x.h"
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+/* Read RTC count register */
+
+NvBool 
+Tps6586xRtcCountRead(
+    NvOdmPmuDeviceHandle hDevice, 
+    NvU32* Count);
+
+/* Read RTC alarm count register */
+
+NvBool 
+Tps6586xRtcAlarmCountRead(
+    NvOdmPmuDeviceHandle hDevice, 
+    NvU32* Count);
+
+/* Write RTC count register */
+
+NvBool 
+Tps6586xRtcCountWrite(
+    NvOdmPmuDeviceHandle hDevice, 
+    NvU32 Count);
+
+/* Write RTC alarm count register */
+
+NvBool 
+Tps6586xRtcAlarmCountWrite(
+    NvOdmPmuDeviceHandle hDevice, 
+    NvU32 Count);
+
+/* Reads RTC alarm interrupt mask status */
+
+NvBool 
+Tps6586xRtcIsAlarmIntEnabled(NvOdmPmuDeviceHandle hDevice);
+
+/* Enables / Disables the RTC alarm interrupt */
+
+NvBool 
+Tps6586xRtcAlarmIntEnable(
+    NvOdmPmuDeviceHandle hDevice, 
+    NvBool Enable);
+
+/* Checks if boot was from nopower / powered state */
+
+NvBool 
+Tps6586xRtcWasStartUpFromNoPower(NvOdmPmuDeviceHandle hDevice);
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif // INCLUDED_TPS6586X_RTC_HEADER
+
diff --git a/arch/arm/mach-tegra/odm_kit/adaptations/pmu/tps6586x/nvodm_pmu_tps6586x_supply_info_table.h b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/tps6586x/nvodm_pmu_tps6586x_supply_info_table.h
new file mode 100644
index 000000000000..fe34d3a02ca1
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/tps6586x/nvodm_pmu_tps6586x_supply_info_table.h
@@ -0,0 +1,193 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef TPS6586x_SUPPLY_INFO_TABLE_H_
+#define TPS6586x_SUPPLY_INFO_TABLE_H_
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+#define PMUGUID NV_ODM_GUID('t','p','s','6','5','8','6','x')
+
+#if defined(CONFIG_TEGRA_ODM_HARMONY)
+
+/// The total number of external supplies (which use both AP and PMU GPIOs)
+#define TPS6586x_EXTERNAL_SUPPLY_NUM \
+    (NvU32)(TPS6586xPmuSupply_Num - Ext_TPS62290PmuSupply_BUCK)
+
+/// Macro for converting a vddRail to AP GPIO pin index.
+#define NVODM_EXT_AP_GPIO_RAIL(x) ((x) - Ext_TPS2051BPmuSupply_VDDIO_VID)
+
+/// The total number of external supplies which use AP GPIO pins for enable
+#define TPS6586x_EXTERNAL_SUPPLY_AP_GPIO_NUM \
+    (NvU32)NVODM_EXT_AP_GPIO_RAIL(TPS6586xPmuSupply_Num)
+
+#else
+
+/* FIXME: modify this table according to your schematics */
+#define V_CORE      TPS6586xPmuSupply_DCD0      
+#define V_1V8       TPS6586xPmuSupply_DCD1      
+#define LCD_2V8     TPS6586xPmuSupply_LDO0      
+#define V_1V2       TPS6586xPmuSupply_LDO1      
+#define V_RTC       TPS6586xPmuSupply_LDO2      
+#define V_CAM_1V8   TPS6586xPmuSupply_LDO3      
+#define V_CODEC_1V8 TPS6586xPmuSupply_LDO4      
+#define V_CAM_2V8   TPS6586xPmuSupply_LDO5      
+#define V_3V3       TPS6586xPmuSupply_LDO6      
+#define V_SDIO      TPS6586xPmuSupply_LDO7      
+#define V_2V8       TPS6586xPmuSupply_LDO8      
+#define V_2V5       TPS6586xPmuSupply_LDO9      
+#define V_25V       TPS6586xPmuSupply_WHITE_LED
+#define V_CHARGE    TPS6586xPmuSupply_DCD2
+#define V_MODEM     V_1V8   /* Alias for V_1V8 */
+#define V_GND       TPS6586xPmuSupply_Invalid
+#define V_INVALID   TPS6586xPmuSupply_Invalid
+#define VRAILCOUNT  TPS6586xPmuSupply_Num
+#endif
+
+typedef enum
+{
+    TPS6586xPmuSupply_Invalid = 0x0,
+
+    //DCD0
+    TPS6586xPmuSupply_DCD0,
+
+    //DCD1
+    TPS6586xPmuSupply_DCD1,
+
+    //DCD2
+    TPS6586xPmuSupply_DCD2,
+
+
+    //LDO0
+    TPS6586xPmuSupply_LDO0,
+
+    //LDO1
+    TPS6586xPmuSupply_LDO1,
+
+    //LDO2
+    TPS6586xPmuSupply_LDO2,
+
+    //LDO3
+    TPS6586xPmuSupply_LDO3,
+    
+    //LDO4
+    TPS6586xPmuSupply_LDO4,
+     
+    //LDO5
+    TPS6586xPmuSupply_LDO5,
+
+    //LDO6
+    TPS6586xPmuSupply_LDO6,
+
+    //LDO7
+    TPS6586xPmuSupply_LDO7,
+
+    //LDO8
+    TPS6586xPmuSupply_LDO8,
+
+    //LDO9
+    TPS6586xPmuSupply_LDO9,
+
+    //RTC_OUT
+    TPS6586xPmuSupply_RTC_OUT,
+
+    //RED1
+    TPS6586xPmuSupply_RED1,
+
+    //GREEN1
+    TPS6586xPmuSupply_GREEN1,
+
+    //BLUE1
+    TPS6586xPmuSupply_BLUE1,
+
+    //RED2
+    TPS6586xPmuSupply_RED2,
+
+    //GREEN2
+    TPS6586xPmuSupply_GREEN2,
+
+    //BLUE2
+    TPS6586xPmuSupply_BLUE2,
+
+    //LED_PWM
+    TPS6586xPmuSupply_LED_PWM,
+
+    //PWM
+    TPS6586xPmuSupply_PWM,
+
+    //White LED(SW3)
+    TPS6586xPmuSupply_WHITE_LED,
+#if defined(CONFIG_TEGRA_ODM_HARMONY)
+    //SOC
+    TPS6586xPmuSupply_SoC,
+
+    /*--- Secondary/External PMU Rails ---*/
+
+    // PMU GPIO-3: VDD_1V05
+    Ext_TPS62290PmuSupply_BUCK,
+
+    // PMU GPIO-2: VDD_1V2
+    Ext_TPS72012PmuSupply_LDO,
+
+    // PMU GPIO-1: VDD_1V5
+    Ext_TPS74201PmuSupply_LDO,
+
+    // AP GPIO(T,2): VDDIO_HDMI, VDDIO_VGA (5V @ 500ma)
+    Ext_TPS2051BPmuSupply_VDDIO_VID,
+
+    // AP GPIO(T,3): VDDIO_SD
+    Ext_SWITCHPmuSupply_VDDIO_SD,
+
+    // AP GPIO(I,6): VDDIO_SDMMC
+    Ext_SWITCHPmuSupply_VDDIO_SDMMC,
+
+    // AP GPIO(W,0): VDD_BL
+    // FIXME: This is already supplied by nvodm_query_gpio in the display GPIO settings.
+    Ext_SWITCHPmuSupply_VDD_BL,
+
+    // AP GPIO(C,6): VDD_PNL
+    // FIXME: This is already supplied by nvodm_query_gpio in the display GPIO settings.
+    Ext_SWITCHPmuSupply_VDD_PNL,
+#endif
+
+    TPS6586xPmuSupply_Num,
+    TPS6586xPmuSupply_Force32 = 0x7FFFFFFF
+} TPS6586xPmuSupply;
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* TPS6586x_SUPPLY_INFO_TABLE_H_ */
diff --git a/arch/arm/mach-tegra/odm_kit/adaptations/pmu/tps6586x/tps6586x_reg.h b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/tps6586x/tps6586x_reg.h
new file mode 100644
index 000000000000..c22cc43854ae
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/tps6586x/tps6586x_reg.h
@@ -0,0 +1,200 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef TPS6586X_REG_HEADER
+#define TPS6586X_REG_HEADER
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+
+
+/* TPS6586x registers */
+
+/* Supply Control and Voltage Settings */
+#define TPS6586x_R10_SUPPLYENA              0x10
+#define TPS6586x_R11_SUPPLYENB              0x11
+#define TPS6586x_R12_SUPPLYENC              0x12
+#define TPS6586x_R13_SUPPLYEND              0x13
+#define TPS6586x_R14_SUPPLYENE              0x14
+#define TPS6586x_R20_VCC1                   0x20
+#define TPS6586x_R21_VCC2                   0x21
+#define TPS6586x_R23_SM1V1                  0x23
+#define TPS6586x_R24_SM1V2                  0x24
+#define TPS6586x_R25_SM1SL                  0x25
+#define TPS6586x_R26_SM0V1                  0x26
+#define TPS6586x_R27_SM0V2                  0x27
+#define TPS6586x_R28_SM0SL                  0x28
+#define TPS6586x_R29_LDO2AV1                0x29
+#define TPS6586x_R2A_LDO2AV2                0x2A
+#define TPS6586x_R2F_LDO2BV1                0x2F
+#define TPS6586x_R30_LDO2BV2                0x30
+#define TPS6586x_R32_LDO4V1                 0x32
+#define TPS6586x_R33_LDO4V2                 0x33
+
+/* Converter Settings */
+#define TPS6586x_R41_SUPPLYV1               0x41
+#define TPS6586x_R42_SUPPLYV2               0x42
+#define TPS6586x_R43_SUPPLYV3               0x43
+#define TPS6586x_R44_SUPPLYV4               0x44
+#define TPS6586x_R45_SUPPLYV5               0x45
+#define TPS6586x_R46_SUPPLYV6               0x46
+#define TPS6586x_R47_SMODE1                 0x47
+#define TPS6586x_R48_SMODE2                 0x48
+
+/* Charger Setup */
+#define TPS6586x_R49_CHG1                   0x49
+#define TPS6586x_R4A_CHG2                   0x4A
+#define TPS6586x_R4B_CHG3                   0x4B
+
+/* Power Path Setup */
+#define TPS6586x_R4C_PPATH2                 0x4C
+
+/* Sequencing */
+#define TPS6586x_R4D_PGFLTMSK1              0x4D
+#define TPS6586x_R4E_PGFLTMSK2              0x4E
+
+/* Peripheral Control */
+#define TPS6586x_R50_RGB1FLASH              0x50
+#define TPS6586x_R51_RGB1RED                0x51
+#define TPS6586x_R52_RGB1GREEN              0x52
+#define TPS6586x_R53_RGB1BLUE               0x53
+#define TPS6586x_R54_RGB2RED                0x54
+#define TPS6586x_R55_RGB2GREEN              0x55
+#define TPS6586x_R56_RGB2BLUE               0x56
+#define TPS6586x_R57_SM3_SET0               0x57
+#define TPS6586x_R58_SM3_SET1               0x58
+#define TPS6586x_R59_LED_PWM                0x59
+#define TPS6586x_R5A_DIG_PWM                0x5A
+#define TPS6586x_R5B_PWM                    0x5B
+#define TPS6586x_R5C_DIG_PWM1               0x5C
+#define TPS6586x_R5D_GPIOSET1               0x5D
+#define TPS6586x_R5E_GPIOSET2               0x5E
+
+#if defined(CONFIG_TEGRA_ODM_HARMONY)
+/*-- GPIO Register Bit Shifts/Masks --*/
+// GPIO1
+#define TPS6586x_R5D_GPIOSET1_GPIO1_MODE_SHIFT  0x0
+#define TPS6586x_R5D_GPIOSET1_GPIO1_MODE_MASK   0x3
+#define TPS6586x_R5E_GPIOSET2_GPIO1_OUT_SHIFT   0x0
+#define TPS6586x_R5E_GPIOSET2_GPIO1_OUT_MASK    0x1
+#define TPS6586x_R5E_GPIOSET2_GPIO1_INV_SHIFT   0x4
+#define TPS6586x_R5E_GPIOSET2_GPIO1_INV_MASK    0x1
+
+// GPIO2
+#define TPS6586x_R5D_GPIOSET1_GPIO2_MODE_SHIFT  0x2
+#define TPS6586x_R5D_GPIOSET1_GPIO2_MODE_MASK   0x3
+#define TPS6586x_R5E_GPIOSET2_GPIO2_OUT_SHIFT   0x1
+#define TPS6586x_R5E_GPIOSET2_GPIO2_OUT_MASK    0x1
+#define TPS6586x_R5E_GPIOSET2_GPIO2_INV_SHIFT   0x5
+#define TPS6586x_R5E_GPIOSET2_GPIO2_INV_MASK    0x1
+
+// GPIO3
+#define TPS6586x_R5D_GPIOSET1_GPIO3_MODE_SHIFT  0x4
+#define TPS6586x_R5D_GPIOSET1_GPIO3_MODE_MASK   0x3
+#define TPS6586x_R5E_GPIOSET2_GPIO3_OUT_SHIFT   0x2
+#define TPS6586x_R5E_GPIOSET2_GPIO3_OUT_MASK    0x1
+#define TPS6586x_R5E_GPIOSET2_GPIO3_INV_SHIFT   0x6
+#define TPS6586x_R5E_GPIOSET2_GPIO3_INV_MASK    0x1
+
+// GPIO4
+#define TPS6586x_R5D_GPIOSET1_GPIO4_MODE_SHIFT  0x6
+#define TPS6586x_R5D_GPIOSET1_GPIO4_MODE_MASK   0x3
+#define TPS6586x_R5E_GPIOSET2_GPIO4_OUT_SHIFT   0x3
+#define TPS6586x_R5E_GPIOSET2_GPIO4_OUT_MASK    0x1
+#define TPS6586x_R5E_GPIOSET2_GPIO4_INV_SHIFT   0x7
+#define TPS6586x_R5E_GPIOSET2_GPIO4_INV_MASK    0x1
+
+#define TPS6586x_R5D_GPIO_MODE_NOT_CONFIG   0x0
+#define TPS6586x_R5D_GPIO_MODE_OUTPUT       0x1
+#define TPS6586x_R5D_GPIO_MODE_INPUT_ADC    0x2
+#define TPS6586x_R5D_GPIO_MODE_INPUT_LDO    0x3
+#endif
+
+/* ADC0 Engine Setup */
+#define TPS6586x_R60_ADCANLG                0x60
+   /* Not finish yet */
+
+/* ADC0 Engine Data */
+#define TPS6586x_R61_ADC0_SET               0x61
+#define TPS6586x_R62_ADC0_WAIT              0x62
+#define TPS6586x_R94_ADC0_SUM2              0x94
+#define TPS6586x_R95_ADC0_SUM1              0x95
+#define TPS6586x_R9A_ADC0_INT               0x9A
+
+/* Interrupt Control */
+#define TPS6586x_RB0_INT_MASK1              0xB0
+#define TPS6586x_RB1_INT_MASK2              0xB1
+#define TPS6586x_RB2_INT_MASK3              0xB2
+#define TPS6586x_RB3_INT_MASK4              0xB3
+#define TPS6586x_RB4_INT_MASK5              0xB4
+#define TPS6586x_RB5_INT_ACK1               0xB5
+#define TPS6586x_RB6_INT_ACK2               0xB6
+#define TPS6586x_RB7_INT_ACK3               0xB7
+#define TPS6586x_RB8_INT_ACK4               0xB8
+
+/* System Status */
+#define TPS6586x_RB9_STAT1                  0xB9
+#define TPS6586x_RBA_STAT2                  0xBA
+#define TPS6586x_RBB_STAT3                  0xBB
+#define TPS6586x_RBC_STAT4                  0xBC
+
+/* RTC */
+#define TPS6586x_RC0_RTC_CTRL               0xC0
+#define TPS6586x_RC1_RTC_ALARM1_HI          0xC1
+#define TPS6586x_RC2_RTC_ALARM1_MID         0xC2
+#define TPS6586x_RC3_RTC_ALARM1_LO          0xC3
+#define TPS6586x_RC4_RTC_ALARM2_HI          0xC4
+#define TPS6586x_RC5_RTC_ALARM2_LO          0xC5
+#define TPS6586x_RC6_RTC_COUNT4             0xC6
+#define TPS6586x_RC7_RTC_COUNT3             0xC7
+#define TPS6586x_RC8_RTC_COUNT2             0xC8
+#define TPS6586x_RC9_RTC_COUNT1             0xC9
+#define TPS6586x_RCA_RTC_COUNT0             0xCA
+
+/* Device ID */
+#define TPS6586x_RCD_VERSIONID              0xCD
+
+#define TPS6586x_RFF_INVALID                0xFF
+
+/* RTC */
+   /* Not finish yet */
+   
+   
+#if defined(__cplusplus)
+}
+#endif
+
+
+#endif //TPS6586X_REG_HEADER
diff --git a/arch/arm/mach-tegra/odm_kit/adaptations/tmon/Makefile b/arch/arm/mach-tegra/odm_kit/adaptations/tmon/Makefile
new file mode 100644
index 000000000000..d2245a6505fa
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/adaptations/tmon/Makefile
@@ -0,0 +1,11 @@
+ccflags-y += -DNV_IS_AVP=0
+ccflags-y += -DNV_OAL=0
+ccflags-y += -DNV_USE_FUSE_CLOCK_ENABLE=0
+ifeq ($(CONFIG_MACH_TEGRA_GENERIC_DEBUG),y)
+ccflags-y += -DNV_DEBUG=1
+else
+ccflags-y += -DNV_DEBUG=0
+endif
+
+obj-y += tmon_hal.o
+obj-y += adt7461/
diff --git a/arch/arm/mach-tegra/odm_kit/adaptations/tmon/adt7461/Makefile b/arch/arm/mach-tegra/odm_kit/adaptations/tmon/adt7461/Makefile
new file mode 100644
index 000000000000..03f222cbeee4
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/adaptations/tmon/adt7461/Makefile
@@ -0,0 +1,13 @@
+ccflags-y += -DNV_IS_AVP=0
+ccflags-y += -DNV_OAL=0
+ccflags-y += -DNV_USE_FUSE_CLOCK_ENABLE=0
+ifeq ($(CONFIG_MACH_TEGRA_GENERIC_DEBUG),y)
+ccflags-y += -DNV_DEBUG=1
+else
+ccflags-y += -DNV_DEBUG=0
+endif
+
+ccflags-y += -Iarch/arm/mach-tegra/odm_kit/adaptations/tmon
+ccflags-y += -Iarch/arm/mach-tegra/odm_kit/adaptations/tmon/adt7461
+
+obj-y += nvodm_tmon_adt7461.o
diff --git a/arch/arm/mach-tegra/odm_kit/adaptations/tmon/adt7461/nvodm_tmon_adt7461.c b/arch/arm/mach-tegra/odm_kit/adaptations/tmon/adt7461/nvodm_tmon_adt7461.c
new file mode 100644
index 000000000000..dc76869f6dec
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/adaptations/tmon/adt7461/nvodm_tmon_adt7461.c
@@ -0,0 +1,934 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+
+#include "nvodm_tmon_adt7461.h"
+#include "tmon_hal.h"
+
+// TODO: Always Disable before check-in
+// Always debug module: 0=disable, 1=enable
+#define NV_ADT7461_DEBUG (0)
+
+#if (NV_DEBUG || NV_ADT7461_DEBUG)
+#define NVODM_ADT7461_PRINTF(x)   NvOdmOsDebugPrintf x
+#else
+#define NVODM_ADT7461_PRINTF(x)
+#endif
+
+#define ADT7461_ALERT_DEBOUNCE (1)
+
+// ADT7461 Descrriptor
+static const ADT7461Info s_Adt7461Info = 
+{
+    // TMON device conversion channels
+    {
+        // Invalid channel
+        {0},
+
+        // Local channel
+        {
+            ADT7461ChannelID_Local,
+            {
+                ADT7461_ODM_LOCAL_RATE_PROTECTED,
+                ADT7461_ODM_LOCAL_INTR_LIMITS_PROTECTED,
+                ADT7461_ODM_LOCAL_COMPARATOR_LIMIT_PROTECTED
+            },
+            {
+                ADT7461_LOCAL_INTR_LIMIT_HIGH_RD_ADDR,
+                ADT7461_LOCAL_INTR_LIMIT_HIGH_WR_ADDR,
+            },
+            {
+                ADT7461_LOCAL_INTR_LIMIT_LOW_RD_ADDR,
+                ADT7461_LOCAL_INTR_LIMIT_LOW_WR_ADDR,
+            },
+            {
+                ADT7461_LOCAL_COMPARATOR_LIMIT_ADDR,
+                ADT7461_LOCAL_COMPARATOR_LIMIT_ADDR,
+            },
+            {
+                ADT7461_INVALID_ADDR,   // Local offset does not exist
+                ADT7461_INVALID_ADDR,
+            },
+            {
+                ADT7461_LOCAL_TDATA_RD_ADDR,
+                ADT7461_INVALID_ADDR,
+            },
+        },
+
+        // Remote channel
+        {
+            ADT7461ChannelID_Remote,
+            {
+                ADT7461_ODM_REMOTE_RATE_PROTECTED,
+                ADT7461_ODM_REMOTE_INTR_LIMITS_PROTECTED,
+                ADT7461_ODM_REMOTE_COMPARATOR_LIMIT_PROTECTED
+            },
+            {
+                ADT7461_REMOTE_INTR_LIMIT_HIGH_RD_ADDR,
+                ADT7461_REMOTE_INTR_LIMIT_HIGH_WR_ADDR,
+            },
+            {
+                ADT7461_REMOTE_INTR_LIMIT_LOW_RD_ADDR,
+                ADT7461_REMOTE_INTR_LIMIT_LOW_WR_ADDR,
+            },
+            {
+                ADT7461_REMOTE_COMPARATOR_LIMIT_ADDR,
+                ADT7461_REMOTE_COMPARATOR_LIMIT_ADDR,
+            },
+            {
+                ADT7461_REMOTE_TOFFSET_ADDR,
+                ADT7461_REMOTE_TOFFSET_ADDR,
+            },
+            {
+                ADT7461_REMOTE_TDATA_RD_ADDR,
+                ADT7461_INVALID_ADDR,
+            },
+        }
+    },
+    
+    // TMON device common status/control registers
+    {
+        ADT7461_STATUS_RD_ADDR,
+        ADT7461_INVALID_ADDR,
+    },
+    {
+        ADT7461_CONFIG_RD_ADDR,
+        ADT7461_CONFIG_WR_ADDR,
+    },
+    {
+        ADT7461_RATE_RD_ADDR,
+        ADT7461_RATE_WR_ADDR,
+    },
+    {
+        ADT7461_INVALID_ADDR,
+        ADT7461_ONE_SHOT_WR_ADDR,
+    },
+    {
+        ADT7461_COMPARATOR_HYSTERESIS_ADDR,
+        ADT7461_COMPARATOR_HYSTERESIS_ADDR,
+    },
+    {
+        ADT7461_INTR_CNT_DELAY_ADDR,
+        ADT7461_INTR_CNT_DELAY_ADDR,
+    },
+};
+
+// ADT7461 sample intervals
+static const NvS32 s_Adt7461SampleIntervalsMS[] =
+{
+    ADT7461_SAMPLE_INTERVALS_MS
+};
+
+// ADT7461 converison times
+static const NvS32 s_Adt7461ConversionTimesMS[] =
+{
+    ADT7461_CONVERSION_TIME_MS
+};
+
+NV_CT_ASSERT(NV_ARRAY_SIZE(s_Adt7461SampleIntervalsMS) ==
+             NV_ARRAY_SIZE(s_Adt7461ConversionTimesMS));
+
+/*****************************************************************************/
+
+#define ADT7461_T_DATA_TO_VALUE(ExtRange, data) \
+    ( (ExtRange) ? \
+        ((NvS32)((NvU32)(data) - ADT7461_RANGE_EXTENDED_DATA_OFFSET)) : \
+        ((NvS32)((NvS8)data)) \
+    )
+
+#define ADT7461_T_VALUE_TO_DATA(ExtRange, val) \
+    ( (ExtRange) ? \
+        ((NvU8)((NvU32)(val) + ADT7461_RANGE_EXTENDED_DATA_OFFSET)) : \
+        ((NvU8)(val)) \
+    )
+
+#define ADT7461_T_RANGE_LIMIT_HIGH(ExtRange) \
+    ( (ExtRange) ? \
+        ADT7461_RANGE_EXTENDED_LIMIT_HIGH : \
+        ADT7461_RANGE_STANDARD_LIMIT_HIGH \
+    )
+
+#define ADT7461_T_RANGE_LIMIT_LOW(ExtRange) \
+    ( (ExtRange) ? \
+        ADT7461_RANGE_EXTENDED_LIMIT_LOW : \
+        ADT7461_RANGE_STANDARD_LIMIT_LOW \
+    )
+
+/*****************************************************************************/
+
+static NvBool
+Adt7461WriteReg(
+    ADT7461PrivData* pPrivData,
+    const ADT7461RegisterInfo* pReg,
+    NvU8 Data)
+{  
+    NvU32 i;
+    NvU8 WriteBuffer[2];
+    NvOdmI2cStatus status;
+    NvOdmI2cTransactionInfo TransactionInfo;
+
+    NV_ASSERT(pPrivData && pReg);
+    NV_ASSERT(pReg->WrAddr != ADT7461_INVALID_ADDR);
+
+    for (i = 0; i < ADT7461_I2C_RETRY_CNT; i++)
+    {
+        WriteBuffer[0] = pReg->WrAddr;
+        WriteBuffer[1] = Data;
+
+        TransactionInfo.Address = pPrivData->DeviceI2cAddr;
+        TransactionInfo.Buf = &WriteBuffer[0];
+        TransactionInfo.Flags = NVODM_I2C_IS_WRITE;
+        TransactionInfo.NumBytes = 2;
+
+        status = NvOdmI2cTransaction(pPrivData->hOdmI2C, &TransactionInfo, 1,
+                    ADT7461_I2C_SPEED_KHZ, ADT7461_I2C_TIMEOUT_MS);
+        if (status == NvOdmI2cStatus_Success)
+            break;
+    }
+
+    switch (status)
+    {
+        case NvOdmI2cStatus_Success:
+            pPrivData->ShadowRegPtr = pReg->WrAddr;
+            return NV_TRUE;
+
+        case NvOdmI2cStatus_Timeout:
+            NVODM_ADT7461_PRINTF(("ADT7461: WriteReg Timeout\n")); 
+            return NV_FALSE;
+
+         case NvOdmI2cStatus_SlaveNotFound:
+         default:
+            NVODM_ADT7461_PRINTF(("ADT7461: WriteReg SlaveNotFound\n"));
+            return NV_FALSE;
+    }
+}
+
+static NvBool
+Adt7461ReadReg(
+    ADT7461PrivData* pPrivData,
+    const ADT7461RegisterInfo* pReg,
+    NvU8* pData)
+{
+    NvU32 i;
+    NvU8 Buffer = 0;
+    NvOdmI2cStatus status;    
+    NvOdmI2cTransactionInfo TransactionInfo[2];
+
+    NV_ASSERT(pPrivData && pReg && pData);
+    NV_ASSERT(pReg->RdAddr != ADT7461_INVALID_ADDR);
+
+    // TODO: possible optimization - is shadow pointer matches register
+    // address, just send one read transaction (can be done only if Read/Wr
+    // Reg routines are serialized).
+
+    for (i = 0; i < ADT7461_I2C_RETRY_CNT; i++)
+    {
+        Buffer = pReg->RdAddr;
+
+        TransactionInfo[0].Address = pPrivData->DeviceI2cAddr;
+        TransactionInfo[0].Buf = &Buffer;
+        TransactionInfo[0].Flags = NVODM_I2C_IS_WRITE;
+        TransactionInfo[0].NumBytes = 1;
+
+        TransactionInfo[1].Address = (pPrivData->DeviceI2cAddr | 0x1);
+        TransactionInfo[1].Buf = &Buffer;
+        TransactionInfo[1].Flags = 0;
+        TransactionInfo[1].NumBytes = 1;
+
+        status = NvOdmI2cTransaction(pPrivData->hOdmI2C, &TransactionInfo[0], 2,
+                    ADT7461_I2C_SPEED_KHZ, ADT7461_I2C_TIMEOUT_MS);
+        if (status == NvOdmI2cStatus_Success)
+            break;
+    }
+
+    switch (status)
+    {
+        case NvOdmI2cStatus_Success:
+            pPrivData->ShadowRegPtr = pReg->RdAddr;
+            *pData = Buffer;
+            return NV_TRUE;
+
+        case NvOdmI2cStatus_Timeout:
+            NVODM_ADT7461_PRINTF(("ADT7461: ReadReg Timeout\n")); 
+            return NV_FALSE;
+
+         case NvOdmI2cStatus_SlaveNotFound:
+         default:
+            NVODM_ADT7461_PRINTF(("ADT7461: ReadReg SlaveNotFound\n"));
+            return NV_FALSE;
+    }
+}
+
+static void Adt7461ReadAra(ADT7461PrivData* pPrivData)
+{
+    NvU32 i;
+    NvU8 Buffer = 0;
+    NvOdmI2cStatus status;    
+    NvOdmI2cTransactionInfo TransactionInfo;
+
+    NV_ASSERT(pPrivData);
+
+    for (i = 0; i < ADT7461_ARA_RETRY_CNT; i++)
+    {
+        TransactionInfo.Address = (ADT7461_ARA | 0x1);
+        TransactionInfo.Buf = &Buffer;
+        TransactionInfo.Flags = 0;
+        TransactionInfo.NumBytes = 1;
+
+        status = NvOdmI2cTransaction(pPrivData->hOdmI2C, &TransactionInfo, 1,
+                    ADT7461_I2C_SPEED_KHZ, ADT7461_I2C_TIMEOUT_MS);
+        if ((status == NvOdmI2cStatus_SlaveNotFound) ||     // False alarm
+            ((status == NvOdmI2cStatus_Success) &&
+            ((Buffer & 0xFE) == (NvU8)pPrivData->DeviceI2cAddr))  // Cleared ARA
+            )
+            break;
+    }
+}
+
+static NvBool
+Adt7461ConfigureSampleInterval(
+    ADT7461PrivData* pPrivData,
+    NvBool OdmProtected,
+    NvS32* pTargetMs)
+{
+    NvU8 i;
+    NvS32 Delta;
+    const ADT7461RegisterInfo* pReg = &pPrivData->pDeviceInfo->Rate;
+
+    if (OdmProtected ||
+        ((*pTargetMs) == ODM_TMON_PARAMETER_UNSPECIFIED))
+    {
+        // Read ADT7461 rate register (fail the call if returned data
+        // does not make sense)
+        if(!Adt7461ReadReg(pPrivData, pReg, &i))
+            return NV_FALSE;
+        if (i >= NV_ARRAY_SIZE(s_Adt7461SampleIntervalsMS))
+            return NV_FALSE;
+    }
+    else
+    {
+        // Find and set the best floor approximation of the target sample
+        // interval. Note the descending order of sample intervals array.
+        for (i = 0; i < NV_ARRAY_SIZE(s_Adt7461SampleIntervalsMS); i++)
+        {
+            Delta = (*pTargetMs) - s_Adt7461SampleIntervalsMS[i];
+            if(Delta >= 0)
+                break;
+        }
+        if (i == NV_ARRAY_SIZE(s_Adt7461SampleIntervalsMS))
+            i--;    // min interval is the best we can do
+
+        if(!Adt7461WriteReg(pPrivData, pReg, i))
+            return NV_FALSE;
+        pPrivData->ShadowRate = i;
+    }
+    *pTargetMs = s_Adt7461SampleIntervalsMS[i];
+    return NV_TRUE;
+}
+
+/*****************************************************************************/
+
+static void Adt7461Isr(void* arg)
+{
+    NvU8 Data;
+    ADT7461PrivData* pPrivData = (ADT7461PrivData*)arg;
+    NvOdmInterruptHandler volatile Callback = pPrivData->Callback;
+    void* volatile CallbackArg = pPrivData->CallbackArg;
+    const ADT7461RegisterInfo* pReg = NULL;
+
+    if (Callback && CallbackArg)
+    {
+        Callback(CallbackArg);
+    }
+#if ADT7461_ALERT_DEBOUNCE
+    // New range limits set by callback are not guaranteed to take effect
+    // before the next temperature conversion is completed, and interrupt
+    // can not be cleared until then. Hence, the debounce delay below.
+    NvOdmOsSleepMS(s_Adt7461SampleIntervalsMS[pPrivData->ShadowRate] +
+                   s_Adt7461ConversionTimesMS[pPrivData->ShadowRate] + 1);
+#endif
+    // Read status and ARA to finish clearing interrupt after callback
+    pReg = &pPrivData->pDeviceInfo->Status;
+    (void)Adt7461ReadReg(pPrivData, pReg, &Data);
+    Adt7461ReadAra(pPrivData);
+
+    // Re-enable interrupt
+    if (pPrivData->hGpioIntr)
+        NvOdmGpioInterruptDone(pPrivData->hGpioIntr);
+}
+
+static void Adt7461FreePrivData(ADT7461PrivData* pPrivData)
+{
+    if (pPrivData)
+    {
+        if (pPrivData->hGpioIntr)
+        {
+            NvOdmGpioInterruptUnregister(
+                pPrivData->hGpio, pPrivData->hGpioPin, pPrivData->hGpioIntr);
+        }
+        NvOdmI2cClose(pPrivData->hOdmI2C);
+        NvOdmGpioReleasePinHandle(pPrivData->hGpio, pPrivData->hGpioPin);
+        NvOdmGpioClose(pPrivData->hGpio);
+        NvOdmServicesPmuClose(pPrivData->hOdmPmuSevice);
+        NvOdmOsFree(pPrivData);
+    }
+}
+
+/*****************************************************************************/
+
+NvBool Adt7461Init(NvOdmTmonDeviceHandle hTmon)
+{
+    NvU8 Data;
+    NvBool ExtRange;
+    NvU32 i = 0;
+    NvU32 I2cInstance = 0;
+    NvOdmIoModule I2cModule = NvOdmIoModule_Num;    // Inavlid module
+    const ADT7461RegisterInfo* pReg = NULL;
+    ADT7461PrivData* pPrivData = NULL;
+    
+    NV_ASSERT(hTmon && hTmon->pConn && hTmon->pConn->AddressList);
+    
+    // Allocate and clear priavte data
+    pPrivData = (ADT7461PrivData*) NvOdmOsAlloc(sizeof(ADT7461PrivData));
+    if (pPrivData == NULL)
+    {
+        NVODM_ADT7461_PRINTF(("ADT7461: Error Allocating PrivData. \n"));
+        return NV_FALSE;
+    }
+    NvOdmOsMemset(pPrivData, 0, sizeof(ADT7461PrivData));
+    hTmon->pPrivate = pPrivData;
+
+    // Register for PMU services
+    pPrivData->hOdmPmuSevice = NvOdmServicesPmuOpen();
+    if (pPrivData->hOdmPmuSevice == NULL)
+    {
+        NVODM_ADT7461_PRINTF(("ADT7461: Error Open PMU service. \n"));
+        goto fail;
+    }
+
+    // Register for GPIO services
+    pPrivData->hGpio = NvOdmGpioOpen();
+    if (pPrivData->hOdmPmuSevice == NULL)
+    {
+        NVODM_ADT7461_PRINTF(("ADT7461: Error Open GPIO service. \n"));
+        goto fail;
+    }
+
+    /*
+     * Parse connectivity data: turn On power to the device, acquire I2C
+     * interface and GPIO interrupt (optional); map device channels to
+     * thermal zones
+     */
+    for (i = 0; i < hTmon->pConn->NumAddress; i ++)
+    {
+        const NvOdmIoAddress* pIoAddress = &hTmon->pConn->AddressList[i];
+        if (pIoAddress->Interface == NvOdmIoModule_I2c_Pmu)
+        {
+            I2cModule   = NvOdmIoModule_I2c_Pmu;
+            I2cInstance = pIoAddress->Instance;
+            NV_ASSERT(pIoAddress->Address != 0);
+            pPrivData->DeviceI2cAddr = pIoAddress->Address;
+        }
+        else if (pIoAddress->Interface == NvOdmIoModule_Tsense)
+        {
+            NV_ASSERT(pIoAddress->Instance < NvOdmTmonZoneID_Num);
+            NV_ASSERT(pIoAddress->Address < ADT7461ChannelID_Num);
+            pPrivData->ConnectivityMap[pIoAddress->Instance] =
+                pIoAddress->Address;
+        }
+        else if (pIoAddress->Interface == NvOdmIoModule_Vdd)
+        {
+            NvU32 usec = 0;
+            NvU32 RailAddress = pIoAddress->Address;
+            NvOdmServicesPmuVddRailCapabilities RailCapabilities = {0};
+            NvOdmServicesPmuGetCapabilities(
+                pPrivData->hOdmPmuSevice, RailAddress, &RailCapabilities);
+            NvOdmServicesPmuSetVoltage(pPrivData->hOdmPmuSevice, RailAddress,
+                              RailCapabilities.requestMilliVolts, &usec);
+            NvOdmOsWaitUS(usec + (ADT7461_POWERUP_DELAY_MS * 1000));
+        }
+        else if (pIoAddress->Interface == NvOdmIoModule_Gpio)
+        {
+            NvU32 port = pIoAddress->Instance;
+            NvU32 pin = pIoAddress->Address;
+            pPrivData->hGpioPin = NvOdmGpioAcquirePinHandle(
+                pPrivData->hGpio, port, pin);
+        }
+
+    }
+    NV_ASSERT(I2cModule == NvOdmIoModule_I2c_Pmu);
+    pPrivData->hOdmI2C = NvOdmI2cOpen(I2cModule, I2cInstance);
+    if (pPrivData->hOdmI2C == NULL)
+    {
+        NVODM_ADT7461_PRINTF(("ADT7461: Error Open I2C device. \n"));     
+        goto fail;
+    }
+
+    /*
+     * Initialize device info and configuration. Force standby mode to avoid
+     * glitch on shutdown comparator output when temperature range and/or
+     * comparator limit is changing during initialization. The Adt7461Run()
+     * call from the hal that follows initialization will switch device to
+     * run mode and re-start temperature monitoring (note that out of limit
+     * interrupt is always masked during and after initialization)
+     */
+    pPrivData->pDeviceInfo = &s_Adt7461Info;
+    pPrivData->ShadowRegPtr = ADT7461_INVALID_ADDR;
+
+    pReg = &pPrivData->pDeviceInfo->Config;
+    if (!Adt7461ReadReg(pPrivData, pReg, &Data))
+        goto fail;
+    if ((Data & ADT7461ConfigBits_ExtendedRange) !=
+        (ADT7461_INITIAL_CONFIG & ADT7461ConfigBits_ExtendedRange))
+    {
+        // Only switch from standard to extended range is supported
+        NV_ASSERT((Data & ADT7461ConfigBits_ExtendedRange) == 0);
+        Data |= ADT7461ConfigBits_Standby;
+        if(!Adt7461WriteReg(pPrivData, pReg, Data))
+            goto fail;
+    }
+    Data = ADT7461_INITIAL_CONFIG | ADT7461ConfigBits_Standby;
+    if(!Adt7461WriteReg(pPrivData, pReg, Data))
+        goto fail;
+    pPrivData->ShadowConfig = Data;
+    ExtRange = ((Data & ADT7461ConfigBits_ExtendedRange) != 0);
+
+    // Program shutdown comparators settings
+    Data = ADT7461_T_VALUE_TO_DATA(
+        ExtRange, ADT7461_ODM_LOCAL_COMPARATOR_LIMIT_VALUE);
+    pReg = &pPrivData->pDeviceInfo->Channels[
+        ADT7461ChannelID_Local].ComparatorLimit;
+    if(!Adt7461WriteReg(pPrivData, pReg, Data))
+        goto fail;
+
+    Data = ADT7461_T_VALUE_TO_DATA(
+        ExtRange, ADT7461_ODM_REMOTE_COMPARATOR_LIMIT_VALUE);
+    pReg = &pPrivData->pDeviceInfo->Channels[
+        ADT7461ChannelID_Remote].ComparatorLimit;
+    if(!Adt7461WriteReg(pPrivData, pReg, Data))
+        goto fail;
+
+    // Set interrupt limits to the range boundaries to prevent out of limit
+    // interrupt
+    Data = ADT7461_T_VALUE_TO_DATA(
+        ExtRange, ADT7461_T_RANGE_LIMIT_HIGH(ExtRange)); 
+    pReg = &pPrivData->pDeviceInfo->Channels[
+        ADT7461ChannelID_Local].IntrLimitHigh;
+    if(!Adt7461WriteReg(pPrivData, pReg, Data))
+        goto fail;
+    pReg = &pPrivData->pDeviceInfo->Channels[
+        ADT7461ChannelID_Remote].IntrLimitHigh;
+    if(!Adt7461WriteReg(pPrivData, pReg, Data))
+        goto fail;
+
+    Data = ADT7461_T_VALUE_TO_DATA(
+            ExtRange, ADT7461_T_RANGE_LIMIT_LOW(ExtRange));
+    pReg = &pPrivData->pDeviceInfo->Channels[
+        ADT7461ChannelID_Local].IntrLimitLow;
+    if(!Adt7461WriteReg(pPrivData, pReg, Data))
+        goto fail;
+    pReg = &pPrivData->pDeviceInfo->Channels[
+        ADT7461ChannelID_Remote].IntrLimitLow;
+    if(!Adt7461WriteReg(pPrivData, pReg, Data))
+        goto fail;
+
+    // Set initial rate
+    Data = ADT7461_INITIAL_RATE_SETTING;  
+    pReg = &pPrivData->pDeviceInfo->Rate;
+    if(!Adt7461WriteReg(pPrivData, pReg, Data))
+        goto fail;
+    pPrivData->ShadowRate = Data;
+
+    // Set remote channel offset (8-bit 2's complement value for any range)
+    Data = ((NvU8)ADT7461_ODM_REMOTE_OFFSET_VALUE);
+    pReg = &pPrivData->pDeviceInfo->Channels[
+        ADT7461ChannelID_Remote].Toffset;
+    if(!Adt7461WriteReg(pPrivData, pReg, Data))
+        goto fail;
+
+    // Read ADT7461 status and ARA (clear pending Alert interrupt, if any)
+    pReg = &pPrivData->pDeviceInfo->Status;
+    if (!Adt7461ReadReg(pPrivData, pReg, &Data))
+        goto fail;
+    // TODO: check open remote circuit error
+
+    Adt7461ReadAra(pPrivData);
+    return NV_TRUE;
+
+fail:
+    Adt7461FreePrivData(pPrivData);
+    hTmon->pPrivate = NULL;
+    return NV_FALSE;
+}
+
+void Adt7461Deinit(NvOdmTmonDeviceHandle hTmon)
+{
+    if (hTmon && hTmon->pPrivate)
+    {
+        ADT7461PrivData* pPrivData = hTmon->pPrivate;
+        (void)Adt7461WriteReg(pPrivData, &pPrivData->pDeviceInfo->Config,
+            ADT7461_INITIAL_CONFIG);    //leave device in default configuration
+                                        // with power rail ON (forever)
+        Adt7461FreePrivData(pPrivData);
+        hTmon->pPrivate = NULL;
+    }
+}
+
+/*****************************************************************************/
+
+NvBool Adt7461Run(NvOdmTmonDeviceHandle hTmon, NvOdmTmonZoneID ZoneId)
+{
+    NvU8 Data; 
+    NvBool IsRunning;
+    ADT7461PrivData* pPrivData;
+
+    NV_ASSERT(hTmon && hTmon->pPrivate);
+    pPrivData = hTmon->pPrivate;
+    IsRunning = (pPrivData->ShadowConfig & ADT7461ConfigBits_Standby) == 0;
+
+    if (!IsRunning)
+    {
+        Data = pPrivData->ShadowConfig & (~ADT7461ConfigBits_Standby);
+        if(!Adt7461WriteReg(pPrivData, &pPrivData->pDeviceInfo->Config, Data))
+            return NV_FALSE;
+        pPrivData->ShadowConfig = Data;
+    }
+    pPrivData->RunRefCount++;
+    return NV_TRUE;
+}
+
+NvBool Adt7461Stop(NvOdmTmonDeviceHandle hTmon, NvOdmTmonZoneID ZoneId)
+{
+    NvU8 Data; 
+    NvBool IsRunning;
+    ADT7461PrivData* pPrivData;
+
+    NV_ASSERT(hTmon && hTmon->pPrivate);
+    pPrivData = hTmon->pPrivate;
+    IsRunning = (pPrivData->ShadowConfig & ADT7461ConfigBits_Standby) == 0;
+
+    if (ADT7461_ODM_STANDBY_ENABLED &&
+        IsRunning && (pPrivData->RunRefCount == 1))
+    {
+        Data = pPrivData->ShadowConfig | ADT7461ConfigBits_Standby;
+        if(!Adt7461WriteReg(pPrivData, &pPrivData->pDeviceInfo->Config, Data))
+            return NV_FALSE;
+        pPrivData->ShadowConfig = Data;
+    }
+    if (pPrivData->RunRefCount != 0)
+    {
+        pPrivData->RunRefCount--;
+        return NV_TRUE;
+    }
+    NV_ASSERT(!"RunRefCount balance failed");
+    NVODM_ADT7461_PRINTF(("ADT7461: RunRefCount balance failed. \n"));
+    return NV_FALSE;
+}
+
+/*****************************************************************************/
+// ADT7461 aborts and restarts conversion cycle when temperature is read
+// (actually on any I2C access for that matter, but other accesses are rare).
+// TODO: add time stamps and implement refresh policy to make sure that
+// frequent temperature reads would not stall the conversion forever.
+
+NvBool 
+Adt7461TemperatureGet(
+    NvOdmTmonDeviceHandle hTmon,
+    NvOdmTmonZoneID ZoneId,
+    NvS32* pDegreesC)
+{
+    NvU8 Data;
+    NvBool ExtRange;
+    ADT7461ChannelID ChannelId;
+    ADT7461PrivData* pPrivData;
+    const ADT7461RegisterInfo* pReg;
+
+    NV_ASSERT(hTmon && hTmon->pPrivate && pDegreesC);
+    pPrivData = hTmon->pPrivate;
+    ExtRange = ((pPrivData->ShadowConfig &
+                 ADT7461ConfigBits_ExtendedRange) != 0);
+    ChannelId = pPrivData->ConnectivityMap[ZoneId];
+    pReg = &pPrivData->pDeviceInfo->Channels[ChannelId].Tdata;
+
+    if(!Adt7461ReadReg(pPrivData, pReg, &Data))
+        return NV_FALSE;
+
+    *pDegreesC = ADT7461_T_DATA_TO_VALUE(ExtRange, Data);
+    return NV_TRUE;
+}
+
+/*****************************************************************************/
+
+void 
+Adt7461CapabilitiesGet(
+    NvOdmTmonDeviceHandle hTmon,
+    NvOdmTmonZoneID ZoneId,
+    NvOdmTmonCapabilities* pCaps)
+{
+    NvBool ExtRange;
+    ADT7461PrivData* pPrivData;
+
+    NV_ASSERT(hTmon && hTmon->pPrivate && pCaps);
+    pPrivData = hTmon->pPrivate;
+    ExtRange = ((pPrivData->ShadowConfig &
+                 ADT7461ConfigBits_ExtendedRange) != 0);
+    
+    pCaps->Tmax = ADT7461_T_RANGE_LIMIT_HIGH(ExtRange);
+    pCaps->Tmin = ADT7461_T_RANGE_LIMIT_LOW(ExtRange);
+    pCaps->IntrSupported = NV_TRUE;
+    pCaps->HwCriticalSupported = NV_TRUE;
+    pCaps->HwCoolingSupported = NV_FALSE;
+}
+
+void
+Adt7461ParameterCapsGet(
+    NvOdmTmonDeviceHandle hTmon,
+    NvOdmTmonZoneID ZoneId,
+    NvOdmTmonConfigParam ParamId,
+    NvOdmTmonParameterCaps* pCaps)
+{
+    NvBool ExtRange;
+    ADT7461PrivData* pPrivData;
+    const ADT7461ChannelInfo* pChannel;
+
+    NV_ASSERT(hTmon && hTmon->pPrivate && pCaps);
+    pPrivData = hTmon->pPrivate;
+    ExtRange = ((pPrivData->ShadowConfig &
+                 ADT7461ConfigBits_ExtendedRange) != 0);
+    pChannel = &pPrivData->pDeviceInfo->Channels[(
+        pPrivData->ConnectivityMap[ZoneId])];
+
+    switch (ParamId)
+    {
+        case NvOdmTmonConfigParam_IntrLimitHigh:
+        case NvOdmTmonConfigParam_IntrLimitLow:
+            pCaps->OdmProtected =
+                pChannel->ChannelPolicy.IntrLimitsOdmProtected;
+            break;
+
+        case NvOdmTmonConfigParam_HwLimitCrit:
+            pCaps->OdmProtected =
+                pChannel->ChannelPolicy.HwLimitCritOdmProtected;
+            break;
+
+        case NvOdmTmonConfigParam_SampleMs:
+            // smaple intervals in descending order
+            pCaps->MaxValue = s_Adt7461SampleIntervalsMS[0];
+            pCaps->MinValue = s_Adt7461SampleIntervalsMS[(
+                NV_ARRAY_SIZE(s_Adt7461SampleIntervalsMS) - 1)];
+            pCaps->OdmProtected = pChannel->ChannelPolicy.RateOdmProtected;
+            return;
+
+        default:        // unsupported parameter
+            pCaps->MaxValue = ODM_TMON_PARAMETER_UNSPECIFIED;
+            pCaps->MinValue = ODM_TMON_PARAMETER_UNSPECIFIED;
+            pCaps->OdmProtected = NV_TRUE;
+            return;
+    }
+
+    // Common range for limits
+    pCaps->MaxValue = ADT7461_T_RANGE_LIMIT_HIGH(ExtRange);
+    pCaps->MinValue = ADT7461_T_RANGE_LIMIT_LOW(ExtRange);
+}
+
+NvBool
+Adt7461ParameterConfig(
+    NvOdmTmonDeviceHandle hTmon,
+    NvOdmTmonZoneID ZoneId,
+    NvOdmTmonConfigParam ParamId,
+    NvS32* pSetting)
+{
+    NvU8 Data;
+    NvBool ExtRange, OdmProtected;
+    ADT7461PrivData* pPrivData;
+    const ADT7461RegisterInfo* pReg;
+    const ADT7461ChannelInfo* pChannel;
+
+    NV_ASSERT(hTmon && hTmon->pPrivate && pSetting);
+    pPrivData = hTmon->pPrivate;
+    ExtRange = ((pPrivData->ShadowConfig &
+                 ADT7461ConfigBits_ExtendedRange) != 0);
+    pChannel = &pPrivData->pDeviceInfo->Channels[(
+        pPrivData->ConnectivityMap[ZoneId])];
+
+    switch (ParamId)
+    {
+        case NvOdmTmonConfigParam_IntrLimitHigh:
+            pReg = &pChannel->IntrLimitHigh;
+            OdmProtected = pChannel->ChannelPolicy.IntrLimitsOdmProtected;
+            break;
+
+        case NvOdmTmonConfigParam_IntrLimitLow:
+            pReg = &pChannel->IntrLimitLow;
+            OdmProtected = pChannel->ChannelPolicy.IntrLimitsOdmProtected;
+            break;
+
+        case NvOdmTmonConfigParam_HwLimitCrit:
+            pReg = &pChannel->ComparatorLimit;
+            OdmProtected = pChannel->ChannelPolicy.HwLimitCritOdmProtected;
+            break;
+
+        case NvOdmTmonConfigParam_SampleMs:
+            OdmProtected = pChannel->ChannelPolicy.RateOdmProtected;
+            return Adt7461ConfigureSampleInterval(
+                pPrivData, OdmProtected, pSetting);
+
+        default:        // unsupported parameter
+            *pSetting = ODM_TMON_PARAMETER_UNSPECIFIED;
+            return NV_TRUE;
+    }
+
+    // Common processing for temperature limits configuration
+    if ((OdmProtected) ||
+        ((*pSetting) == ODM_TMON_PARAMETER_UNSPECIFIED))
+    {
+        // Read ADT7461 register and convert data to current parameter value
+        if(!Adt7461ReadReg(pPrivData, pReg, &Data))
+            return NV_FALSE;
+
+        *pSetting = ADT7461_T_DATA_TO_VALUE(ExtRange, Data);
+    }
+    else
+    {
+        // Clip target setting to temperature range 
+        if ((*pSetting) > ADT7461_T_RANGE_LIMIT_HIGH(ExtRange))
+            *pSetting = ADT7461_T_RANGE_LIMIT_HIGH(ExtRange);
+        else if ((*pSetting) < ADT7461_T_RANGE_LIMIT_LOW(ExtRange))
+            *pSetting = ADT7461_T_RANGE_LIMIT_LOW(ExtRange);
+
+        // Convert new configuration setting and write to ADT7461 register
+        Data = ADT7461_T_VALUE_TO_DATA(ExtRange, *pSetting);
+        if(!Adt7461WriteReg(pPrivData, pReg, Data))
+            return NV_FALSE;
+    }
+    return NV_TRUE;
+}
+
+/*****************************************************************************/
+
+NvOdmTmonIntrHandle
+Adt7461IntrRegister(
+    NvOdmTmonDeviceHandle hTmon,
+    NvOdmTmonZoneID ZoneId,
+    NvOdmInterruptHandler Callback,
+    void* CallbackArg)
+{
+    NvU8 Data;
+    ADT7461PrivData* pPrivData;
+    const ADT7461ChannelInfo* pChannel;
+    NvOdmServicesGpioIntrHandle hGpioIntr = NULL;
+
+    NV_ASSERT(hTmon && hTmon->pPrivate && Callback && CallbackArg);
+    pPrivData = hTmon->pPrivate;
+
+    // No registration, if no GPIO pin available or interrupt already registred
+    if (!pPrivData->hGpioPin || pPrivData->hGpioIntr)
+        return NULL;
+
+    // No registration for other than remote channel
+    pChannel = &pPrivData->pDeviceInfo->Channels[(
+        pPrivData->ConnectivityMap[ZoneId])];
+    if (pChannel->ChannelId != ADT7461ChannelID_Remote)
+        return NULL;
+
+    // Register GPIO interrupt (will be enabled at SoC IC, but still disabled
+    // at ADT7461 device)
+    pPrivData->Callback = Callback;
+    pPrivData->CallbackArg = CallbackArg;
+    if (!NvOdmGpioInterruptRegister(
+        pPrivData->hGpio, &hGpioIntr, pPrivData->hGpioPin,
+        ADT7461_ODM_INTR_POLARITY, Adt7461Isr, (void *)pPrivData, 0))
+    {
+        pPrivData->Callback = NULL;
+        pPrivData->CallbackArg = NULL;
+        return NULL;
+    }
+    NV_ASSERT(hGpioIntr);
+    pPrivData->hGpioIntr = hGpioIntr;
+    
+    // Finally enable ADT7461 device interrupt output (interrupt may or may
+    // not be generated depending on temperature and limt settings).
+    Data = pPrivData->ShadowConfig & (~ADT7461ConfigBits_IntrDisabled);
+    if(!Adt7461WriteReg(pPrivData, &pPrivData->pDeviceInfo->Config, Data))
+    {
+        NvOdmGpioInterruptUnregister(
+            pPrivData->hGpio, pPrivData->hGpioPin, hGpioIntr);
+        pPrivData->Callback = NULL;
+        pPrivData->CallbackArg = NULL;
+        pPrivData->hGpioIntr = NULL;
+        return NULL;
+    }
+    pPrivData->ShadowConfig = Data;
+
+    return (NvOdmTmonIntrHandle)hGpioIntr;
+}
+
+void
+Adt7461IntrUnregister(
+    NvOdmTmonDeviceHandle hTmon,
+    NvOdmTmonZoneID ZoneId,
+    NvOdmTmonIntrHandle hIntr)
+{
+    NvU8 Data;
+    ADT7461PrivData* pPrivData;
+    const ADT7461ChannelInfo* pChannel;
+
+    // Ignore invalid handles
+    if(!hIntr || !hTmon || !hTmon->pPrivate) 
+        return;
+
+    pPrivData = hTmon->pPrivate;
+    if (hIntr != ((NvOdmTmonIntrHandle)pPrivData->hGpioIntr))
+        return;
+
+    // Ignore any channel other than remote
+    pChannel = &pPrivData->pDeviceInfo->Channels[(
+        pPrivData->ConnectivityMap[ZoneId])];
+    if (pChannel->ChannelId != ADT7461ChannelID_Remote)
+        return;
+
+    // Disable ADT7461 interrupt output
+    Data = pPrivData->ShadowConfig | ADT7461ConfigBits_IntrDisabled;
+    if(Adt7461WriteReg(pPrivData, &pPrivData->pDeviceInfo->Config, Data))
+        pPrivData->ShadowConfig = Data;
+
+    // Unregister GPIO interrupt, clear callbacks and handle
+    NvOdmGpioInterruptUnregister(
+        pPrivData->hGpio, pPrivData->hGpioPin, pPrivData->hGpioIntr);
+
+    pPrivData->Callback = NULL;
+    pPrivData->CallbackArg = NULL;
+    pPrivData->hGpioIntr = NULL;
+}
+
+/*****************************************************************************/
+
diff --git a/arch/arm/mach-tegra/odm_kit/adaptations/tmon/adt7461/nvodm_tmon_adt7461.h b/arch/arm/mach-tegra/odm_kit/adaptations/tmon/adt7461/nvodm_tmon_adt7461.h
new file mode 100644
index 000000000000..ffe4bf15dbec
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/adaptations/tmon/adt7461/nvodm_tmon_adt7461.h
@@ -0,0 +1,199 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+ 
+#ifndef INCLUDED_NVODM_TMON_ADT7461_H
+#define INCLUDED_NVODM_TMON_ADT7461_H
+
+#include "nvodm_tmon.h"
+#include "nvodm_tmon_adt7461_reg.h"
+#include "nvodm_tmon_adt7461_channel.h"
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+typedef struct ADT7461RegisterInfoRec
+{
+    NvU8 RdAddr;            // Invalid if WO
+    NvU8 WrAddr;            // Invalid if RO
+} ADT7461RegisterInfo;
+
+typedef struct ADT7461ChannelOdmPolicyRec
+{
+    NvBool RateOdmProtected;
+    NvBool IntrLimitsOdmProtected;
+    NvBool HwLimitCritOdmProtected;
+} ADT7461ChannelOdmPolicy;
+
+typedef struct ADT7461ChannelInfoRec
+{
+    // TMON device conversion channel ID
+    ADT7461ChannelID  ChannelId;
+
+    // ODM channel policy
+    ADT7461ChannelOdmPolicy ChannelPolicy;
+
+    // Alert Interrupt limits registers
+    ADT7461RegisterInfo IntrLimitHigh;
+    ADT7461RegisterInfo IntrLimitLow;
+
+    // Thermal comparator limit register
+    ADT7461RegisterInfo ComparatorLimit;
+
+    // Temperature measurement offset
+    ADT7461RegisterInfo Toffset;
+
+    // Temperature Data register
+    ADT7461RegisterInfo Tdata;
+} ADT7461ChannelInfo;
+
+typedef struct ADT7461InfoRec
+{
+    // TMON device conversion channels
+    ADT7461ChannelInfo  Channels[ADT7461ChannelID_Num];
+
+    // Chip status register
+    ADT7461RegisterInfo Status;
+
+    // Common configration controls
+    ADT7461RegisterInfo Config;
+
+    // Common conversion rate
+    ADT7461RegisterInfo Rate;
+
+    // One-shot trigger register
+    ADT7461RegisterInfo OneShot;
+
+    // Common comparator hysteresis 
+    ADT7461RegisterInfo ComparatorHysteresis;
+
+    // Number of consecutive limit violation before
+    // interrupt is generated
+    ADT7461RegisterInfo IntrCntDelay;
+} ADT7461Info;
+
+typedef struct ADT7461PrivDataRec
+{
+    // ADT7461 device registers descriptors
+    const ADT7461Info* pDeviceInfo;
+
+    // ADT7461 I2C device Address
+    NvU32 DeviceI2cAddr;
+
+    // The handle to the I2C controller
+    NvOdmServicesI2cHandle hOdmI2C;
+
+    // The odm pmu service handle
+    NvOdmServicesPmuHandle hOdmPmuSevice;
+
+    // Zone => Channel map
+    ADT7461ChannelID ConnectivityMap[NvOdmTmonZoneID_Num];
+
+    // ADR7461 run mode reference count 
+    NvU32 RunRefCount;
+
+    // Shadow of ADT7461 internal configuration register
+    NvU8 ShadowConfig;
+
+    // Shadow of ADT7461 internal rate settings
+    NvU8 ShadowRate;
+
+    // Shadow of ADT7461 internal address pointer
+    NvU8 ShadowRegPtr;
+
+    // The odm GPIO service handle
+    NvOdmServicesGpioHandle hGpio;
+
+    // SoC GPIO dedicated for ADT7461 out of limit interrupt
+    NvOdmGpioPinHandle hGpioPin;
+
+    // The ADT7461 interrupt handle
+    NvOdmServicesGpioIntrHandle hGpioIntr;
+
+    // The ADT7461 interrupt callback
+    NvOdmInterruptHandler Callback;
+
+    // The ADT7461 interrupt callback context
+    void* CallbackArg;
+} ADT7461PrivData;
+
+NvBool Adt7461Init(NvOdmTmonDeviceHandle hTmon);
+void Adt7461Deinit(NvOdmTmonDeviceHandle hTmon);
+NvBool Adt7461Run(NvOdmTmonDeviceHandle hTmon, NvOdmTmonZoneID ZoneId);
+NvBool Adt7461Stop(NvOdmTmonDeviceHandle hTmon, NvOdmTmonZoneID ZoneId);
+
+NvBool 
+Adt7461TemperatureGet(
+    NvOdmTmonDeviceHandle hTmon,
+    NvOdmTmonZoneID ZoneId,
+    NvS32* pDegreesC);
+
+void 
+Adt7461CapabilitiesGet(
+    NvOdmTmonDeviceHandle hTmon,
+    NvOdmTmonZoneID ZoneId,
+    NvOdmTmonCapabilities* pCaps);
+
+void
+Adt7461ParameterCapsGet(
+    NvOdmTmonDeviceHandle hTmon,
+    NvOdmTmonZoneID ZoneId,
+    NvOdmTmonConfigParam ParamId,
+    NvOdmTmonParameterCaps* pCaps);
+
+NvBool
+Adt7461ParameterConfig(
+    NvOdmTmonDeviceHandle hTmon,
+    NvOdmTmonZoneID ZoneId,
+    NvOdmTmonConfigParam ParamId,
+    NvS32* pSetting);
+
+NvOdmTmonIntrHandle
+Adt7461IntrRegister(
+    NvOdmTmonDeviceHandle hTmon,
+    NvOdmTmonZoneID ZoneId,
+    NvOdmInterruptHandler Callback,
+    void* arg);
+
+void
+Adt7461IntrUnregister(
+    NvOdmTmonDeviceHandle hTmon,
+    NvOdmTmonZoneID ZoneId,
+    NvOdmTmonIntrHandle hIntr);
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif //INCLUDED_NVODM_TMON_ADT7461_H
+
diff --git a/arch/arm/mach-tegra/odm_kit/adaptations/tmon/adt7461/nvodm_tmon_adt7461_channel.h b/arch/arm/mach-tegra/odm_kit/adaptations/tmon/adt7461/nvodm_tmon_adt7461_channel.h
new file mode 100644
index 000000000000..8d9f9bb22d95
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/adaptations/tmon/adt7461/nvodm_tmon_adt7461_channel.h
@@ -0,0 +1,58 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+ 
+#ifndef INCLUDED_NVODM_TMON_ADT7461_CHANNEL_H
+#define INCLUDED_NVODM_TMON_ADT7461_CHANNEL_H
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+typedef enum
+{
+    // Local sensor
+    ADT7461ChannelID_Local = 1,
+
+    // Remote sensor
+    ADT7461ChannelID_Remote,
+
+    ADT7461ChannelID_Num,
+    ADT7461ChannelID_Force32 = 0x7FFFFFFFUL
+} ADT7461ChannelID;
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif //INCLUDED_NVODM_TMON_ADT7461_CHANNEL_H
+
diff --git a/arch/arm/mach-tegra/odm_kit/adaptations/tmon/adt7461/nvodm_tmon_adt7461_reg.h b/arch/arm/mach-tegra/odm_kit/adaptations/tmon/adt7461/nvodm_tmon_adt7461_reg.h
new file mode 100644
index 000000000000..e0e930e79fe7
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/adaptations/tmon/adt7461/nvodm_tmon_adt7461_reg.h
@@ -0,0 +1,203 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+ 
+#ifndef INCLUDED_NVODM_TMON_ADT7461_REG_H
+#define INCLUDED_NVODM_TMON_ADT7461_REG_H
+
+#include "nvodm_tmon_adt7461.h"
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+// ODM policy: use ADT7461 extended=1 (standard=0) range
+#define ADT7461_ODM_EXTENDED_RANGE (1)
+
+// ODM policy: enable=1 (disable=0) ADT7461 standby mode
+#define ADT7461_ODM_STANDBY_ENABLED (0)
+
+// ODM policy: protect=1 (not=0) thermal limits from being overwritten by API
+#define ADT7461_ODM_LOCAL_INTR_LIMITS_PROTECTED         (1)
+#define ADT7461_ODM_LOCAL_COMPARATOR_LIMIT_PROTECTED    (1)
+
+#define ADT7461_ODM_REMOTE_INTR_LIMITS_PROTECTED        (0)
+#define ADT7461_ODM_REMOTE_COMPARATOR_LIMIT_PROTECTED   (1)
+
+// ODM policy: protect=1 (not=0) sample rate from being overwritten by API
+#define ADT7461_ODM_LOCAL_RATE_PROTECTED                (1)
+#define ADT7461_ODM_REMOTE_RATE_PROTECTED               (0)
+
+// ODM policy: comparator limit values for critical shutdown (in degrees C)
+#define ADT7461_ODM_LOCAL_COMPARATOR_LIMIT_VALUE        (120L)
+#define ADT7461_ODM_REMOTE_COMPARATOR_LIMIT_VALUE       (115L)
+
+// ODM ADT7461 remote channel measurement offset
+#define ADT7461_ODM_REMOTE_OFFSET_VALUE                 (6L)
+
+// ODM ADT7461 interrupt polarity
+#define ADT7461_ODM_INTR_POLARITY (NvOdmGpioPinMode_InputInterruptLow)
+
+// ADT7461 Register POR settings
+#define ADT7461_LOCAL_TDATA_POR                         (0x00)
+#define ADT7461_REMOTE_TDATA_POR                        (0x00)
+// #define ADT7461_STATUS_POR  unknown
+#define ADT7461_CONFIG_POR                              (0x00)
+#define ADT7461_RATE_POR                                (0x08)
+#define ADT7461_LOCAL_INTR_LIMIT_HIGH_POR               (0x55)
+#define ADT7461_LOCAL_INTR_LIMIT_LOW_POR                (0x00)
+#define ADT7461_REMOTE_INTR_LIMIT_HIGH_POR              (0x55)
+#define ADT7461_REMOTE_INTR_LIMIT_LOW_POR               (0x00)
+// #define ADT7461_ONE_SHOT_POR unknown
+#define ADT7461_REMOTE_TDATA_FRACTION_POR               (0x00)
+#define ADT7461_REMOTE_TOFFSET_POR                      (0x00)
+#define ADT7461_REMOTE_TOFFSET_FRACTION_POR             (0x00)
+#define ADT7461_REMOTE_INTR_LIMIT_HIGH_FRACTION_POR     (0x00)
+#define ADT7461_REMOTE_INTR_LIMIT_LOW_FRACTION_POR      (0x00)
+#define ADT7461_REMOTE_COMPARATOR_LIMIT_POR             (0x55)
+#define ADT7461_LOCAL_COMPARATOR_LIMIT_POR              (0x55)
+#define ADT7461_COMPARATOR_HYSTERESIS_POR               (0x0A)
+#define ADT7461_INTR_CNT_DELAY_POR                      (0x01)
+#define ADT7461_CHIP_ID_POR                             (0x41)
+#define ADT7461_CHIP_REV_POR                            (0x51)
+
+
+// ADT7461 Register Addresses
+#define ADT7461_LOCAL_TDATA_RD_ADDR                     (0x00)
+#define ADT7461_REMOTE_TDATA_RD_ADDR                    (0x01)
+                                                              
+#define ADT7461_STATUS_RD_ADDR                          (0x02)
+#define ADT7461_CONFIG_RD_ADDR                          (0x03)
+#define ADT7461_CONFIG_WR_ADDR                          (0x09)
+#define ADT7461_RATE_RD_ADDR                            (0x04)
+#define ADT7461_RATE_WR_ADDR                            (0x0A)
+                                                              
+#define ADT7461_LOCAL_INTR_LIMIT_HIGH_RD_ADDR           (0x05)
+#define ADT7461_LOCAL_INTR_LIMIT_HIGH_WR_ADDR           (0x0B)
+#define ADT7461_LOCAL_INTR_LIMIT_LOW_RD_ADDR            (0x06)
+#define ADT7461_LOCAL_INTR_LIMIT_LOW_WR_ADDR            (0x0C)
+                                                              
+#define ADT7461_REMOTE_INTR_LIMIT_HIGH_RD_ADDR          (0x07)
+#define ADT7461_REMOTE_INTR_LIMIT_HIGH_WR_ADDR          (0x0D)
+#define ADT7461_REMOTE_INTR_LIMIT_LOW_RD_ADDR           (0x08)
+#define ADT7461_REMOTE_INTR_LIMIT_LOW_WR_ADDR           (0x0E)
+                                                              
+#define ADT7461_ONE_SHOT_WR_ADDR                        (0x0F)
+                                                              
+#define ADT7461_REMOTE_TDATA_FRACTION_RD_ADDR           (0x10)
+#define ADT7461_REMOTE_TOFFSET_ADDR                     (0x11)
+#define ADT7461_REMOTE_TOFFSET_FRACTION_ADDR            (0x12)
+#define ADT7461_REMOTE_INTR_LIMIT_HIGH_FRACTION_ADDR    (0x13)
+#define ADT7461_REMOTE_INTR_LIMIT_LOW_FRACTION_ADDR     (0x14)
+
+#define ADT7461_REMOTE_COMPARATOR_LIMIT_ADDR            (0x19)
+#define ADT7461_LOCAL_COMPARATOR_LIMIT_ADDR             (0x20)
+#define ADT7461_COMPARATOR_HYSTERESIS_ADDR              (0x21)
+
+#define ADT7461_INTR_CNT_DELAY_ADDR                     (0x22)
+#define ADT7461_CHIP_ID_RD_ADDR                         (0xFE)
+#define ADT7461_CHIP_REV_RD_ADDR                        (0xFF)
+
+#define ADT7461_INVALID_ADDR                            (0xF0)
+
+
+// ADT7461 conversion range (signed values)
+#define ADT7461_RANGE_STANDARD_LIMIT_HIGH               (127L)
+#define ADT7461_RANGE_STANDARD_LIMIT_LOW                (0L)
+#define ADT7461_RANGE_EXTENDED_LIMIT_HIGH               (150L)
+#define ADT7461_RANGE_EXTENDED_LIMIT_LOW                (-64L)
+
+// ADT7461 data reading offsets (unsigned data)
+#define ADT7461_RANGE_STANDARD_DATA_OFFSET              (0UL)
+#define ADT7461_RANGE_EXTENDED_DATA_OFFSET              (64UL)
+
+
+// ADT7461 Configuration Register bitfields
+typedef enum
+{
+    // If set - extended temperature range (-55C to 150C); data offset 64C
+    // If cleared - stnadard temperature range (0C to 127C); data offset 0 
+    ADT7461ConfigBits_ExtendedRange =   (0x1 << 2),
+
+    // If set - interrupt output works as second auto cleared comparator
+    // If cleared - interrupt output works as level out of limit interrupt,
+    // cleared by (a) reading status and (b) alert response protocol over I2C
+    ADT7461ConfigBits_IntrAutoClear =   (0x1 << 5),
+
+    // If set - put device in stanby mode
+    // If cleared - put device in running mode
+    ADT7461ConfigBits_Standby =         (0x1 << 6),
+
+    // If set - interrupt from device is disabled
+    // If cleared - interrupt from device is enabled
+    ADT7461ConfigBits_IntrDisabled =    (0x1 << 7),
+} ADT7461ConfigBits;
+
+// ADT7461 initial configuration set by adaptation:
+// ADT7461 THERM1 output is dedicated for critical h/w shutdown, and ADT7461
+// ALERT/THERM2 output is always configured as out of limit ALERT interrupt.
+// Monitor is in running mode, in the range selected per ODM policy.
+#define ADT7461_INITIAL_CONFIG \
+        ((ADT7461ConfigBits_IntrDisabled) | \
+         (ADT7461_ODM_EXTENDED_RANGE  ? ADT7461ConfigBits_ExtendedRange : 0))
+
+
+// ADT7461 sample intervals and conversion time limits rounded to the nearest
+// milliseconds, in descending order indexed by rate register DATA settings
+
+// RATE: 1/16   1/8   1/4   1/2     1     2     4     8    16    32    64 (1/s)
+// DATA: 0x00  0x01  0x02  0x03  0x04  0x05  0x06  0x07  0x08  0x09  0x0A 
+#define ADT7461_SAMPLE_INTERVALS_MS \
+        16000, 8000, 4000, 2000, 1000,  500,  250,  125,   63,   31,   16
+#define ADT7461_CONVERSION_TIME_MS \
+          115,  115,  115,  115,  115,  115,  115,  115,   13,   13,   13
+
+#define ADT7461_INITIAL_RATE_SETTING        (0x0A)
+
+
+// ADT7461 I2C (SMBus) clock speed, bus timeout, retries, and fixed
+// Alert Response Address (ARA).
+#define ADT7461_I2C_SPEED_KHZ   (400)
+#define ADT7461_I2C_TIMEOUT_MS  (500)
+#define ADT7461_I2C_RETRY_CNT   (2)
+#define ADT7461_ARA_RETRY_CNT   (4)
+#define ADT7461_ARA             (0x18)
+
+// ADT7461 power up delay (TODO: get spec for delay from vendor)
+#define ADT7461_POWERUP_DELAY_MS    (5)
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif //INCLUDED_NVODM_TMON_ADT7461_REG_H
+
diff --git a/arch/arm/mach-tegra/odm_kit/adaptations/tmon/tmon_hal.c b/arch/arm/mach-tegra/odm_kit/adaptations/tmon/tmon_hal.c
new file mode 100644
index 000000000000..acabf8492c35
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/adaptations/tmon/tmon_hal.c
@@ -0,0 +1,304 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include "tmon_hal.h"
+#include "adt7461/nvodm_tmon_adt7461.h"
+
+/*
+ * TMON adaptation is a singleton linked directly with NVRM only.
+ * Thread safety for TMON APIs is provided by NVRM as well.  
+ */
+
+
+// Temperature Monitors suported under hal
+#define TMON_ADT7461_ID (NV_ODM_GUID('a','d','t','7','4','6','1',' '))
+
+#define TMON_ZONE_PSEUDOHANDLE(h, z) \
+    ( (NvOdmTmonDeviceHandle)((((NvU32)(h)) << 16) | (z)) )
+#define TMON_PSEUDOHANDLE_ZONE(h) ( ((NvU32)(h)) & 0xFFFF )
+
+/*****************************************************************************/
+
+static NvOdmTmonDevice*
+TmonGetInstance(NvOdmTmonZoneID ZoneId)
+{
+    static NvOdmTmonDevice s_TmonArray[NvOdmTmonZoneID_Num];
+    static NvOdmTmonDevice* s_TmonMap[NvOdmTmonZoneID_Num];
+    static NvBool s_Initialized = NV_FALSE;
+
+    NvU32 i, j;
+    NvOdmTmonDevice* pTmon = NULL;
+    const NvOdmPeripheralConnectivity* pConn = NULL;
+
+    // Check for invalid zone
+    if (ZoneId == 0)
+        return NULL;
+
+    if (!s_Initialized)
+    {
+        NvOdmOsMemset(s_TmonArray, 0, sizeof(s_TmonArray));
+        NvOdmOsMemset(s_TmonMap, 0, sizeof(s_TmonMap));
+        s_Initialized = NV_TRUE;
+        i = 0;  // allocation index
+
+        pConn = NvOdmPeripheralGetGuid(TMON_ADT7461_ID);
+        if (pConn)
+        {
+            pTmon = &s_TmonArray[i++];
+            pTmon->pfnInit              = Adt7461Init;
+            pTmon->pfnDeinit            = Adt7461Deinit;
+            pTmon->pfnTemperatureGet    = Adt7461TemperatureGet;
+            pTmon->pfnCapabilitiesGet   = Adt7461CapabilitiesGet;
+            pTmon->pfnParameterCapsGet  = Adt7461ParameterCapsGet;
+            pTmon->pfnParameterConfig   = Adt7461ParameterConfig;
+            pTmon->pfnRun               = Adt7461Run;
+            pTmon->pfnStop              = Adt7461Stop;         
+            pTmon->pfnIntrRegister      = Adt7461IntrRegister;
+            pTmon->pfnIntrUnregister    = Adt7461IntrUnregister;
+            pTmon->pConn = pConn;
+            pTmon->RefCount = 0;
+            pTmon->pPrivate = NULL;
+
+            // Fill in Zones => TMON devices map
+            NV_ASSERT(pConn->AddressList);
+            for (j = 0; j < pConn->NumAddress; j++)
+            {
+                if (pConn->AddressList[j].Interface == NvOdmIoModule_Tsense)
+                    s_TmonMap[pConn->AddressList[j].Instance] = pTmon;
+            }
+        }
+    }
+    // Find TMON instance for the given zone
+    if(ZoneId < NvOdmTmonZoneID_Num)
+    {
+        pTmon = s_TmonMap[ZoneId];
+        if (pTmon && pTmon->pConn)
+            return pTmon;
+    }
+    return NULL;
+}
+
+/*****************************************************************************/
+
+NvOdmTmonDeviceHandle
+NvOdmTmonDeviceOpen(NvOdmTmonZoneID ZoneId)
+{
+    NvOdmTmonDevice* pTmon = TmonGetInstance(ZoneId);
+
+    if (pTmon)
+    {
+        NV_ASSERT(pTmon->pfnInit && pTmon->pfnRun);
+        // Init TMON device on the 1st open
+        if (pTmon->RefCount == 0)
+        {
+            if (!pTmon->pfnInit(pTmon))
+                return NULL;
+        }
+        // Make sure targeted zone is monitored
+        if (pTmon->pfnRun(pTmon, ZoneId))
+        {
+            pTmon->RefCount++;
+            return TMON_ZONE_PSEUDOHANDLE(pTmon, ZoneId);
+        }
+    }
+    return NULL;
+}
+
+void NvOdmTmonDeviceClose(NvOdmTmonDeviceHandle hTmon)
+{
+    NvOdmTmonZoneID ZoneId = TMON_PSEUDOHANDLE_ZONE(hTmon);
+    NvOdmTmonDevice* pTmon = TmonGetInstance(ZoneId);
+
+    if (pTmon)
+    {
+        NV_ASSERT(pTmon->pfnDeinit && pTmon->pfnStop);
+        (void)pTmon->pfnStop(pTmon, ZoneId);
+        if (pTmon->RefCount == 1)
+            pTmon->pfnDeinit(pTmon);
+
+        if (pTmon->RefCount)
+        {
+            pTmon->RefCount--;
+            return;
+        }
+        NV_ASSERT(!"RefCount balance failed");
+    }
+}
+
+NvBool NvOdmTmonSuspend(NvOdmTmonDeviceHandle hTmon)
+{
+    NvOdmTmonZoneID ZoneId = TMON_PSEUDOHANDLE_ZONE(hTmon);
+    NvOdmTmonDevice* pTmon = TmonGetInstance(ZoneId);
+
+    if (pTmon && pTmon->RefCount)
+    {
+        NV_ASSERT(pTmon->pfnStop);
+        if (pTmon->pfnStop(pTmon, ZoneId))
+            return NV_TRUE;
+    }
+    return NV_FALSE;
+}
+
+NvBool NvOdmTmonResume(NvOdmTmonDeviceHandle hTmon)
+{
+    NvOdmTmonZoneID ZoneId = TMON_PSEUDOHANDLE_ZONE(hTmon);
+    NvOdmTmonDevice* pTmon = TmonGetInstance(ZoneId);
+
+    if (pTmon && pTmon->RefCount)
+    {
+        NV_ASSERT(pTmon->pfnRun);
+        if (pTmon->pfnRun(pTmon, ZoneId))
+            return NV_TRUE;
+    }
+    return NV_FALSE;
+}
+
+/*****************************************************************************/
+
+NvBool
+NvOdmTmonTemperatureGet(
+    NvOdmTmonDeviceHandle hTmon,
+    NvS32* pDegreesC)
+{
+    NvOdmTmonZoneID ZoneId = TMON_PSEUDOHANDLE_ZONE(hTmon);
+    NvOdmTmonDevice* pTmon = TmonGetInstance(ZoneId);
+
+    if (pTmon && pTmon->RefCount)
+    {
+        NV_ASSERT(pTmon->pfnTemperatureGet);
+        if (pTmon->pfnTemperatureGet(pTmon, ZoneId, pDegreesC))
+            return NV_TRUE;
+    }
+    return NV_FALSE;
+}
+
+/*****************************************************************************/
+
+void
+NvOdmTmonCapabilitiesGet(
+    NvOdmTmonDeviceHandle hTmon,
+    NvOdmTmonCapabilities* pCaps)
+{
+    NvOdmTmonZoneID ZoneId = TMON_PSEUDOHANDLE_ZONE(hTmon);
+    NvOdmTmonDevice* pTmon = TmonGetInstance(ZoneId);
+
+    if (pTmon && pTmon->RefCount)
+    {
+        NV_ASSERT(pTmon->pfnCapabilitiesGet);
+        pTmon->pfnCapabilitiesGet(pTmon, ZoneId, pCaps);
+    }
+    else if (pCaps)
+    {
+        NvOdmOsMemset(pCaps, 0, sizeof(NvOdmTmonCapabilities));
+        pCaps->Tmax = ODM_TMON_PARAMETER_UNSPECIFIED;
+        pCaps->Tmin = ODM_TMON_PARAMETER_UNSPECIFIED;
+    }
+}
+
+void
+NvOdmTmonParameterCapsGet(
+    NvOdmTmonDeviceHandle hTmon,
+    NvOdmTmonConfigParam ParamId,
+    NvOdmTmonParameterCaps* pCaps)
+{
+    NvOdmTmonZoneID ZoneId = TMON_PSEUDOHANDLE_ZONE(hTmon);
+    NvOdmTmonDevice* pTmon = TmonGetInstance(ZoneId);
+
+    if (pTmon && pTmon->RefCount)
+    {
+        NV_ASSERT(pTmon->pfnParameterCapsGet);
+        pTmon->pfnParameterCapsGet(pTmon, ZoneId, ParamId, pCaps);
+    }
+    else if (pCaps)
+    {
+        NvOdmOsMemset(pCaps, 0, sizeof(NvOdmTmonParameterCaps));
+        pCaps->MaxValue = ODM_TMON_PARAMETER_UNSPECIFIED;
+        pCaps->MinValue = ODM_TMON_PARAMETER_UNSPECIFIED;
+        pCaps->OdmProtected = NV_TRUE;
+    }
+}
+
+NvBool
+NvOdmTmonParameterConfig(
+    NvOdmTmonDeviceHandle hTmon,
+    NvOdmTmonConfigParam ParamId,
+    NvS32* pSetting)
+{
+    NvOdmTmonZoneID ZoneId = TMON_PSEUDOHANDLE_ZONE(hTmon);
+    NvOdmTmonDevice* pTmon = TmonGetInstance(ZoneId);
+
+    if (pTmon && pTmon->RefCount)
+    {
+        NV_ASSERT(pTmon->pfnParameterConfig);
+        if (pTmon->pfnParameterConfig(pTmon, ZoneId, ParamId, pSetting))
+            return NV_TRUE;
+    }
+    return NV_FALSE;
+}
+
+/*****************************************************************************/
+
+NvOdmTmonIntrHandle
+NvOdmTmonIntrRegister(
+    NvOdmTmonDeviceHandle hTmon,
+    NvOdmInterruptHandler Callback,
+    void* CallbackArg)
+{
+    NvOdmTmonZoneID ZoneId = TMON_PSEUDOHANDLE_ZONE(hTmon);
+    NvOdmTmonDevice* pTmon = TmonGetInstance(ZoneId);
+
+    NvOdmTmonIntrHandle hIntr = NULL;
+    if (pTmon && pTmon->RefCount)
+    {
+        NV_ASSERT(pTmon->pfnIntrRegister);
+        hIntr = pTmon->pfnIntrRegister(
+            pTmon, ZoneId, Callback, CallbackArg);
+    }
+    return hIntr;
+}
+
+void
+NvOdmTmonIntrUnregister(
+    NvOdmTmonDeviceHandle hTmon,
+    NvOdmTmonIntrHandle hIntr)
+{
+    NvOdmTmonZoneID ZoneId = TMON_PSEUDOHANDLE_ZONE(hTmon);
+    NvOdmTmonDevice* pTmon = TmonGetInstance(ZoneId);
+
+    if (pTmon && pTmon->RefCount)
+    {
+        NV_ASSERT(pTmon->pfnIntrUnregister);
+        pTmon->pfnIntrUnregister(pTmon, ZoneId, hIntr);
+    }
+}
+
+/*****************************************************************************/
diff --git a/arch/arm/mach-tegra/odm_kit/adaptations/tmon/tmon_hal.h b/arch/arm/mach-tegra/odm_kit/adaptations/tmon/tmon_hal.h
new file mode 100644
index 000000000000..5e5e1141c584
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/adaptations/tmon/tmon_hal.h
@@ -0,0 +1,86 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/** 
+ * @file
+ * <b>NVIDIA Tegra ODM Kit:
+ *         Abstraction layer stub for Temperature Monitor adaptations</b>
+ */
+
+#ifndef INCLUDED_NVODM_TMON_ADAPTATION_HAL_H
+#define INCLUDED_NVODM_TMON_ADAPTATION_HAL_H
+
+#include "nvcommon.h"
+#include "nvodm_tmon.h"
+#include "nvodm_query_discovery.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+typedef NvBool (*pfnTmonInit)(NvOdmTmonDeviceHandle);
+typedef void   (*pfnTmonDeinit)(NvOdmTmonDeviceHandle);
+typedef NvBool (*pfnTmonTemperatureGet)(NvOdmTmonDeviceHandle, NvOdmTmonZoneID, NvS32*);
+typedef void   (*pfnTmonCapabilitiesGet)(NvOdmTmonDeviceHandle, NvOdmTmonZoneID, NvOdmTmonCapabilities*);
+typedef void   (*pfnTmonParameterCapsGet)
+               (NvOdmTmonDeviceHandle, NvOdmTmonZoneID, NvOdmTmonConfigParam, NvOdmTmonParameterCaps*);
+typedef NvBool (*pfnTmonParameterConfig)(NvOdmTmonDeviceHandle, NvOdmTmonZoneID, NvOdmTmonConfigParam, NvS32*);
+typedef NvBool (*pfnTmonRun)(NvOdmTmonDeviceHandle, NvOdmTmonZoneID);
+typedef NvBool (*pfnTmonStop)(NvOdmTmonDeviceHandle, NvOdmTmonZoneID);
+typedef NvOdmTmonIntrHandle
+               (*pfnTmonIntrRegister)(NvOdmTmonDeviceHandle, NvOdmTmonZoneID, NvOdmInterruptHandler, void*);
+typedef void   (*pfnTmonIntrUnregister)(NvOdmTmonDeviceHandle, NvOdmTmonZoneID, NvOdmTmonIntrHandle);
+
+typedef struct NvOdmTmonDeviceRec
+{ 
+    pfnTmonInit                 pfnInit;
+    pfnTmonDeinit               pfnDeinit;
+    pfnTmonTemperatureGet       pfnTemperatureGet;
+    pfnTmonCapabilitiesGet      pfnCapabilitiesGet;
+    pfnTmonParameterCapsGet     pfnParameterCapsGet;
+    pfnTmonParameterConfig      pfnParameterConfig;
+    pfnTmonRun                  pfnRun;
+    pfnTmonStop                 pfnStop;
+    pfnTmonIntrRegister         pfnIntrRegister;
+    pfnTmonIntrUnregister       pfnIntrUnregister;
+
+    const NvOdmPeripheralConnectivity*  pConn;
+    NvU32                       RefCount;
+    void                        *pPrivate;
+} NvOdmTmonDevice;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  //INCLUDED_NVODM_TMON_ADAPTATION_HAL_H
diff --git a/arch/arm/mach-tegra/odm_kit/platform/Makefile b/arch/arm/mach-tegra/odm_kit/platform/Makefile
new file mode 100644
index 000000000000..8cf34fa4b7f6
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/platform/Makefile
@@ -0,0 +1,8 @@
+obj-$(CONFIG_INPUT_TEGRA_ODM_ACCEL)	+= accelerometer/
+obj-$(CONFIG_INPUT_TEGRA_ODM_SCROLL)	+= scrollwheel/
+obj-$(CONFIG_KEYBOARD_TEGRA_NVEC)	+= keyboard/
+obj-$(CONFIG_TOUCHSCREEN_TEGRA_ODM)	+= touch/
+obj-$(CONFIG_TEGRA_ODM_VIBRATE)		+= vibrate/
+obj-$(CONFIG_MOUSE_TEGRA_NVEC)		+= mouse/
+obj-$(CONFIG_TEGRA_BATTERY_NVEC)	+= battery/
+obj-$(CONFIG_BATTERY_TEGRA_ODM)		+= battery/
diff --git a/arch/arm/mach-tegra/odm_kit/platform/accelerometer/Makefile b/arch/arm/mach-tegra/odm_kit/platform/accelerometer/Makefile
new file mode 100644
index 000000000000..0ec8a6b4ea03
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/platform/accelerometer/Makefile
@@ -0,0 +1,12 @@
+ccflags-y += -DNV_IS_AVP=0
+ccflags-y += -DNV_OAL=0
+ccflags-y += -DNV_USE_FUSE_CLOCK_ENABLE=0
+ifeq ($(CONFIG_MACH_TEGRA_GENERIC_DEBUG),y)
+ccflags-y += -DNV_DEBUG=1
+else
+ccflags-y += -DNV_DEBUG=0
+endif
+
+obj-$(CONFIG_TEGRA_ODM_CONCORDE)	+= nvodm_accelerometer_adi340.o
+obj-$(CONFIG_TEGRA_ODM_HARMONY)		+= nvodm_accelerometer_bma150.o
+obj-$(CONFIG_TEGRA_ODM_WHISTLER)	+= nvodm_accelerometer_adi340.o
diff --git a/arch/arm/mach-tegra/odm_kit/platform/accelerometer/nvodm_accelerometer_adi340.c b/arch/arm/mach-tegra/odm_kit/platform/accelerometer/nvodm_accelerometer_adi340.c
new file mode 100644
index 000000000000..9a6ae96a3b52
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/platform/accelerometer/nvodm_accelerometer_adi340.c
@@ -0,0 +1,1204 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+ 
+/*  NVIDIA Tegra ODM Kit Sample Accelerometer Adaptation of the
+ *  WinCE Accelerometer Driver
+ */
+
+
+#include "nvodm_accelerometer_adi340.h"
+#include "nvodm_services.h"
+#include "nvodm_query_discovery.h"
+#include "nvos.h"
+
+#define NV_ACCELEROMETER_REGISTER_RANGE 8
+// When acc is put in horizontal, the max value from acc.
+#define NV_ADI340_ACCELEROMETER_NORMAL_THRESHOLD 30
+#define NV_ADI340_ACCELEROMETER_TAP_THRESHOLD 40
+#define NV_ADI340_LOW_POWER_SAMPLERATE 3
+#define NV_ADI340_FULL_RUN_SAMPLERATE  100
+#define NV_ADI340_FORCE_FACTOR 1000
+#define NV_ADI340_MAX_FORCE_IN_REG 128 // It indicates force register length. 
+#define NV_DEBOUNCE_TIME_MS 0
+//static NvU32 g_thresholdG_shadow = 70;
+
+// For interrupt handle, set GPIO when an interrupt happens.
+static void GpioInterruptHandler(void *arg);
+NvBool NvAccelerometerI2COpen(NvOdmServicesI2cHandle* hI2CDevice, NvU32 id);
+void   NvAccelerometerI2CClose(NvOdmServicesI2cHandle hI2CDevice);
+NvBool NvAccelerometerI2CSetRegs(NvOdmAccelHandle hDevice, NvU8 offset, NvU8* value, NvU32 len);
+NvBool NvAccelerometerI2CGetRegs(NvOdmAccelHandle hDevice, NvU8 offset, NvU8* value, NvU32 len);
+NvBool NvAccelerometerConnectSemaphore(NvOdmAccelHandle hDevice);
+void NvAccelerometerSetPowerRail(NvOdmServicesPmuHandle hPMUDevice, NvU32 Id, NvBool IsEnable);
+void NvAccelerometerGetInterruptSouce(NvOdmAccelHandle hDevice, 
+                                         NvOdmAccelIntType  *IntType,
+                                         NvOdmAccelAxisType *IntMotionAxis,
+                                         NvOdmAccelAxisType *IntTapAxis);
+
+/*
+ * Set accelerometer registers.
+ * [in] attrib: The register flag. 
+ * [out] info: The value to be set into the register of accelerometer.
+ * Returns NV_TRUE if successful, or NV_FALSE otherwise.
+ */
+NvBool NvOdmAccelerometerSetParameter(NvOdmAccelHandle hDevice, NvU8 attrib, NvU32 info)
+{
+    // Because there are only 8 bits for one accelerometer register.
+    NvU8 LocalInfo = 0;
+    LocalInfo = (NvU8)(info);
+    // Due to the register length, we only accept the lowest 8 bits.
+    NvOdmOsMemcpy(&LocalInfo, &info, sizeof(NvU8));
+    //NVODMACCELEROMETER_PRINTF("NV ODM ACCELEROMETER NvOdmAccelerometerSetParameter +++\n");
+    switch (attrib)
+    {
+        case XLR_CTL:
+            //NvOdmOsDebugPrintf("set XLR_CTL = 0x%x\n", LocalInfo);
+            hDevice->RegsWrite( hDevice, XLR_CTL, &LocalInfo, 1);
+            break;
+        case XLR_INTCONTROL:
+            //NvOdmOsDebugPrintf("set XLR_INTCONTROL = 0x%x\n", LocalInfo);
+            hDevice->RegsWrite( hDevice, XLR_INTCONTROL, &LocalInfo, 1);
+            break;
+        case XLR_INTCONTROL2:
+            //NvOdmOsDebugPrintf("set XLR_INTCONTROL2 = 0x%x\n", LocalInfo);
+            hDevice->RegsWrite( hDevice, XLR_INTCONTROL2, &LocalInfo, 1);
+             break;
+        case XLR_THRESHG:
+            //NVODMACCELEROMETER_PRINTF("set XLR_THRESHG = 0x%x\n", LocalInfo);
+            hDevice->RegsWrite( hDevice, XLR_THRESHG, &LocalInfo, 1);
+            break;
+        case XLR_THRESHC:
+            hDevice->RegsWrite( hDevice, XLR_THRESHC, &LocalInfo, 1);
+            break;
+        case XLR_OFSX:
+            hDevice->RegsWrite( hDevice, XLR_OFSX, &LocalInfo, 1);
+            break;
+        case XLR_OFSY:
+            hDevice->RegsWrite( hDevice, XLR_OFSY, &LocalInfo, 1);
+            break;
+        case XLR_OFSZ:
+            hDevice->RegsWrite( hDevice, XLR_OFSZ, &LocalInfo, 1);
+            break;
+        case XLR_DUR:
+            hDevice->RegsWrite( hDevice, XLR_DUR, &LocalInfo, 1);
+            break;
+        case XLR_LATENT:
+            hDevice->RegsWrite( hDevice, XLR_LATENT, &LocalInfo, 1);
+            break;
+        case XLR_INTVL:
+            hDevice->RegsWrite( hDevice, XLR_INTVL, &LocalInfo, 1);
+            break;
+        default:
+            //NVODMACCELEROMETER_PRINTF("NV ODM ACCELEROMETER NvOdmAccelerometerSetParameter DONT SUPPORT SUCH ATTRIBUTE ---\n");
+            return NV_FALSE;
+    }
+    //NVODMACCELEROMETER_PRINTF("NV ODM ACCELEROMETER NvOdmAccelerometerSetParameter ---\n");
+    return NV_TRUE;
+}
+
+
+
+/*
+ * Get acceleromter registers.
+ * [in] attrib: The regsiter flag. 
+ * [out] info: The value from register of accelerometer.
+ * Returns NV_TRUE if successful, or NV_FALSE otherwise.
+ */
+NvBool NvOdmAccelerometerGetParameter(NvOdmAccelHandle hDevice, NvU8 attrib, NvU32* info)
+{
+    NvU8 LocalInfo = 0;
+    NvS32 temp;
+
+    //NVODMACCELEROMETER_PRINTF("NV ODM ACCELEROMETER NvOdmAccelerometerGetParameter +++\n");
+    switch (attrib)
+    {
+        case XLR_DEVID:
+            hDevice->RegsRead( hDevice, XLR_DEVID, &LocalInfo, 1);
+            break;
+        case XLR_WHOAMI:
+            hDevice->RegsRead( hDevice, XLR_WHOAMI, &LocalInfo, 1);
+            break;
+        case XLR_STATUS:
+            hDevice->RegsRead( hDevice, XLR_STATUS, &LocalInfo, 1);
+            break;
+        case XLR_INTSOURCE:
+            hDevice->RegsRead( hDevice, XLR_INTSOURCE, &LocalInfo, 1);
+            break;
+        case XLR_CTL:
+            hDevice->RegsRead( hDevice, XLR_CTL, &LocalInfo, 1);
+            break;
+        case XLR_INTCONTROL:
+            hDevice->RegsRead( hDevice, XLR_INTCONTROL, &LocalInfo, 1);
+            break;
+        case XLR_INTCONTROL2:
+            hDevice->RegsRead( hDevice, XLR_INTCONTROL2, &LocalInfo, 1);
+            break;
+        case XLR_DATAX:
+            // Because it is a signed char.
+            hDevice->RegsRead( hDevice, XLR_DATAX, &LocalInfo, 1);
+            temp = (LocalInfo<128)?LocalInfo:(LocalInfo-256);
+            NvOdmOsMemcpy(info, &temp, sizeof(NvU32));
+            //NVODMACCELEROMETER_PRINTF("NV ODM ACCELEROMETER NvOdmAccelerometerGetParameter ---\n");
+            return NV_TRUE;
+        case XLR_DATAY:
+            // Because it is a signed char.
+            hDevice->RegsRead( hDevice, XLR_DATAY, &LocalInfo, 1);
+            temp = (LocalInfo<128)?LocalInfo:(LocalInfo-256);
+            NvOdmOsMemcpy(info, &temp, sizeof(NvU32));
+            //NVODMACCELEROMETER_PRINTF("NV ODM ACCELEROMETER NvOdmAccelerometerGetParameter ---\n");
+            return NV_TRUE;
+        case XLR_DATAZ:
+            // Because it is a signed char.
+            hDevice->RegsRead( hDevice, XLR_DATAZ, &LocalInfo, 1);
+            temp = (LocalInfo<128)?LocalInfo:(LocalInfo-256);
+            NvOdmOsMemcpy(info, &temp, sizeof(NvU32));
+            //NVODMACCELEROMETER_PRINTF("NV ODM ACCELEROMETER NvOdmAccelerometerGetParameter ---\n");
+            return NV_TRUE;
+        case XLR_MOREINFO:
+            hDevice->RegsRead( hDevice, XLR_MOREINFO, &LocalInfo, 1);
+            break;
+        case XLR_THRESHG:
+            hDevice->RegsRead( hDevice, XLR_THRESHG, &LocalInfo, 1);
+            break;
+        case XLR_THRESHC:
+            hDevice->RegsRead( hDevice, XLR_THRESHC, &LocalInfo, 1);
+            break;
+        case XLR_OFSX:
+            hDevice->RegsRead( hDevice, XLR_OFSX, &LocalInfo, 1);
+            break;
+        case XLR_OFSY:
+            hDevice->RegsRead( hDevice, XLR_OFSY, &LocalInfo, 1);
+            break;
+        case XLR_OFSZ:
+            hDevice->RegsRead( hDevice, XLR_OFSZ, &LocalInfo, 1);
+            break;
+        case XLR_DUR:
+            hDevice->RegsRead( hDevice, XLR_DUR, &LocalInfo, 1);
+            break;
+        case XLR_LATENT:
+            hDevice->RegsRead( hDevice, XLR_LATENT, &LocalInfo, 1);
+            break;
+        case XLR_INTVL:
+            hDevice->RegsRead( hDevice, XLR_INTVL, &LocalInfo, 1);
+            break;
+        case XLR_SCALE:
+            hDevice->RegsRead( hDevice, XLR_CTL, &LocalInfo, 1);            
+            if ((LocalInfo&(0x01)) == 0)
+            {
+                LocalInfo = 2;
+            }
+            else
+            {
+                LocalInfo = 8;
+            }
+            break;
+        case XLR_ROTATE:
+            *info = 1;
+            break;
+        case XLR_GYRO:
+            *info = 0;
+            break;
+        default:
+            //NVODMACCELEROMETER_PRINTF("NV ODM ACCELEROMETER NvOdmAccelerometerGetParameter DONT SUPPORT SUCH ATTRIBUTE ---\n");
+            return NV_FALSE;
+    }
+    *info = LocalInfo;
+    //NVODMACCELEROMETER_PRINTF("NV ODM ACCELEROMETER NvOdmAccelerometerGetParameter ---\n");
+    return NV_TRUE;
+}
+
+void NvAccelerometerSetPowerRail(NvOdmServicesPmuHandle hPMUDevice, NvU32 Id, NvBool IsEnable)
+{
+    NvOdmServicesPmuVddRailCapabilities vddrailcap;
+    NvU32 settletime;
+
+    if (hPMUDevice)
+    {       
+        NvOdmServicesPmuGetCapabilities(hPMUDevice, Id, &vddrailcap);
+        if (IsEnable)
+        {
+            NvOdmServicesPmuSetVoltage(hPMUDevice, Id, vddrailcap.requestMilliVolts, &settletime);
+        }
+        else
+        {
+            NvOdmServicesPmuSetVoltage(hPMUDevice, Id, vddrailcap.MinMilliVolts, &settletime);
+        }
+        NvOdmOsWaitUS(settletime);  // wait to settle power
+    }
+}
+
+
+/*
+ * Get interrupt type and source.
+ */
+void NvAccelerometerGetInterruptSouce(NvOdmAccelHandle hDevice, 
+                                              NvOdmAccelIntType  *IntType,
+                                              NvOdmAccelAxisType *IntMotionAxis,
+                                              NvOdmAccelAxisType *IntTapAxis)
+{
+    NvU32    reg_val;
+
+    NV_ASSERT(hDevice != 0);
+    NV_ASSERT(IntType != 0);
+    NV_ASSERT(IntMotionAxis != 0); 
+    NV_ASSERT(IntTapAxis != 0); 
+
+    *IntType = NvOdmAccelInt_None;
+    *IntMotionAxis = NvOdmAccelAxis_None;
+    *IntTapAxis = NvOdmAccelAxis_None;
+    
+    if(NULL != hDevice)
+    {
+        NvOdmAccelerometerGetParameter(hDevice, XLR_INTSOURCE, &reg_val);
+        if(reg_val & XLR_INTSOURCE_X_COM_MASK)
+        {
+            *IntType |= NvOdmAccelInt_MotionThreshold;
+            *IntMotionAxis |= NvOdmAccelAxis_X;
+        }
+        if(reg_val & XLR_INTSOURCE_Y_COM_MASK)
+        {
+            *IntType |= NvOdmAccelInt_MotionThreshold;
+            *IntMotionAxis |= NvOdmAccelAxis_Y;
+        }
+        if(reg_val & XLR_INTSOURCE_Z_COM_MASK)
+        {
+            *IntType |= NvOdmAccelInt_MotionThreshold;
+            *IntMotionAxis |= NvOdmAccelAxis_Z;
+        }
+        if(reg_val & XLR_INTSOURCE_X_TAP_MASK)
+        {
+            *IntType |= NvOdmAccelInt_TapThreshold;
+            *IntTapAxis |= NvOdmAccelAxis_X;
+        }
+        if(reg_val & XLR_INTSOURCE_Y_TAP_MASK)
+        {
+            *IntType |= NvOdmAccelInt_TapThreshold;
+            *IntTapAxis |= NvOdmAccelAxis_Y;
+        }
+        if(reg_val & XLR_INTSOURCE_Z_TAP_MASK)
+        {
+            *IntType |= NvOdmAccelInt_TapThreshold;
+            *IntTapAxis |= NvOdmAccelAxis_Z;
+        }
+   }
+   //NvOdmOsDebugPrintf("IntType =%d, IntAxis = %d\n", *IntType, *IntAxis);
+}
+
+
+static void 
+GpioInterruptHandler(void *arg)
+{
+    NvOdmGpioPinMode mode; 
+    
+    NvU32 pinValue;
+    NvOdmAccelHandle hDevice =  (NvOdmAccelHandle)arg;
+    //NvOdmOsSemaphoreHandle s = (NvOdmOsSemaphoreHandle)arg;
+    
+    NvOdmGpioGetState(hDevice->hGpioINT, hDevice->hPinINT, &pinValue); 
+    if (pinValue == 1)
+    {
+        mode = NvOdmGpioPinMode_InputInterruptLow;
+    }
+    else
+    {
+        mode = NvOdmGpioPinMode_InputInterruptHigh;
+    }
+    
+    NvOdmGpioConfig(hDevice->hGpioINT, hDevice->hPinINT, mode);
+    
+    if (pinValue == 1) 
+    {
+        NvOdmOsSemaphoreSignal(hDevice->SemaphoreForINT);
+    }
+    NvOdmGpioInterruptDone(hDevice->hGpioInterrupt);
+    return;
+}
+
+/*
+ * Connect semaphore with interrupt pins according to your configuration.
+ */
+NvBool NvAccelerometerConnectSemaphore(NvOdmAccelHandle hDevice)
+{
+    NvOdmGpioPinMode mode; 
+    NvOdmInterruptHandler callback = (NvOdmInterruptHandler)GpioInterruptHandler;
+         
+    hDevice->hGpioINT = (NvOdmServicesGpioHandle)NvOdmGpioOpen();
+    if(!(hDevice->hGpioINT))
+    {
+        //NVODMACCELEROMETER_PRINTF("NvOdm Accelerometer : NvOdmGpioOpen Error \n");
+        return NV_FALSE;
+    }
+
+    hDevice->hPinINT = NvOdmGpioAcquirePinHandle(hDevice->hGpioINT, 
+                                                 hDevice->GPIOPortINT, 
+                                                 hDevice->GPIOPinINT);
+
+    hDevice->SemaphoreForINT = NvOdmOsSemaphoreCreate(0);
+
+    if(!(hDevice->SemaphoreForINT))
+    {
+        //NVODMACCELEROMETER_PRINTF("NvOdm Accelerometer : NvOdmOsSemaphoreCreate Error \n");
+        NvOdmGpioClose(hDevice->hGpioINT);
+        return NV_FALSE;
+    }
+          
+    mode = NvOdmGpioPinMode_InputInterruptHigh;
+    
+    if (NvOdmGpioInterruptRegister(hDevice->hGpioINT, &hDevice->hGpioInterrupt,
+        hDevice->hPinINT, mode, callback, hDevice, NV_DEBOUNCE_TIME_MS) == NV_FALSE)
+    {
+        return NV_FALSE;
+    }
+
+    if(!(hDevice->hGpioInterrupt))
+    {
+        //NVODMACCELEROMETER_PRINTF("NvOdm Accelerometer : NvOdmGpioInterruptRegister Error \n");
+        NvOdmGpioClose(hDevice->hGpioINT);
+        NvOdmOsSemaphoreDestroy(hDevice->SemaphoreForINT);
+        return NV_FALSE;
+    }
+    
+    return NV_TRUE;
+}
+
+/*
+ * Initialize I2C for accelerometer.
+ */
+NvBool NvAccelerometerI2COpen(NvOdmServicesI2cHandle* hI2CDevice, NvU32 id)
+{
+    // Open I2C handle.
+    *hI2CDevice = NvOdmI2cOpen(NvOdmIoModule_I2c, id);
+    if (*hI2CDevice == NULL)
+    {
+        return NV_FALSE;
+    }
+    return NV_TRUE;
+}
+
+
+/*
+ * De-initialize I2C for accelerometer.
+ */
+void NvAccelerometerI2CClose(NvOdmServicesI2cHandle hI2CDevice)
+{
+    // Close I2C handle.
+    if(NULL != hI2CDevice)
+    {
+        NvOdmI2cClose(hI2CDevice);
+    }
+}
+
+
+/*
+ * Write I2C register function.
+ * offset[Input]: I2C register offset of accelerometer.
+ * value[Input]: register value you will write.
+ * len[Input]: requested bytes.
+ * Returns NV_TRUE if successful, or NV_FALSE otherwise.
+ */
+NvBool NvAccelerometerI2CSetRegs(NvOdmAccelHandle hDevice, NvU8 offset, NvU8* value, NvU32 len)
+{
+    NvOdmI2cTransactionInfo TransactionInfo;
+
+    if( (NULL == hDevice) || (NULL == value) || (len > I2C_ACCELRATOR_PACKET_SIZE-1 ))
+    {
+        //NVODMACCELEROMETER_PRINTF("NvOdmI2c Set Regs Failed, max size is %d bytes\n", I2C_ACCELRATOR_PACKET_SIZE-1);
+        return NV_FALSE;
+    }
+    
+    NvOdmOsMemset(s_WriteBuffer, 0, sizeof(s_WriteBuffer));
+    s_WriteBuffer[0] = offset;
+    NvOdmOsMemcpy(&s_WriteBuffer[1], value, len);
+
+    TransactionInfo.Address = hDevice->nDevAddr;
+    TransactionInfo.Buf = s_WriteBuffer;
+    TransactionInfo.Flags = NVODM_I2C_IS_WRITE;
+    TransactionInfo.NumBytes = len+1;
+
+    // Write the accelerator offset (from where data is to be read).
+    if(NvOdmI2cStatus_Success != NvOdmI2cTransaction(hDevice->hOdmI2C, &TransactionInfo, 1, 400, I2C_ACCELRATOR_TRANSACTION_TIMEOUT))
+    {
+        return NV_FALSE;
+    };    
+        
+    return NV_TRUE;
+}
+
+/*
+ * Read I2C register function.
+ * offset[Input]: I2C register offset of accelerometer.
+ * value[Output]: Fegister value you get.
+ * len[Input]: Requested bytes.
+ * Returns NV_TRUE if successful, or NV_FALSE otherwise.
+ */
+
+NvBool NvAccelerometerI2CGetRegs(NvOdmAccelHandle hDevice, NvU8 offset, NvU8* value, NvU32 len)
+{
+    NvOdmI2cTransactionInfo TransactionInfo;
+
+    if( (NULL == hDevice) || (NULL == value) || (len > I2C_ACCELRATOR_PACKET_SIZE-1 ))
+    {
+        //NVODMACCELEROMETER_PRINTF("NvOdmI2c Get Regs Failed, max size is %d bytes\n", I2C_ACCELRATOR_PACKET_SIZE-1);
+        return NV_FALSE;
+    }
+    
+    NvOdmOsMemset(s_WriteBuffer, 0, sizeof(s_WriteBuffer));
+    s_WriteBuffer[0] = offset;
+
+    TransactionInfo.Address = hDevice->nDevAddr;
+    TransactionInfo.Buf = s_WriteBuffer;
+    TransactionInfo.Flags = NVODM_I2C_IS_WRITE;
+    TransactionInfo.NumBytes = 1;
+
+    // Write the accelerometor offset (from where data is to be read).
+    if(NvOdmI2cStatus_Success != NvOdmI2cTransaction(hDevice->hOdmI2C, &TransactionInfo, 1, 400, I2C_ACCELRATOR_TRANSACTION_TIMEOUT))
+    {
+        return NV_FALSE;
+    };
+  
+    NvOdmOsMemset(s_ReadBuffer, 0, sizeof(s_ReadBuffer));    
+    s_ReadBuffer[0] = 0;
+
+    TransactionInfo.Address = (hDevice->nDevAddr| 0x1);
+    TransactionInfo.Buf = s_ReadBuffer;
+    TransactionInfo.Flags = 0;
+    TransactionInfo.NumBytes = len;
+
+    //Read the data from the eeprom at the specified offset
+    if(NvOdmI2cStatus_Success != NvOdmI2cTransaction(hDevice->hOdmI2C, &TransactionInfo, 1, 400, I2C_ACCELRATOR_TRANSACTION_TIMEOUT))
+    {
+        return NV_FALSE;
+    };    
+
+    NvOdmOsMemcpy(value, &s_ReadBuffer[0], len);
+        
+    return NV_TRUE;
+} 
+
+//-----------------------------------------------------------------
+//--------------------------------New API--------------------------
+//-----------------------------------------------------------------
+NvBool
+NvOdmAccelOpen(NvOdmAccelHandle* hDevice)
+{
+    NvU32    test_val;
+    NvU32 i;
+    NvBool foundGpio = NV_FALSE, foundI2cModule = NV_FALSE;
+    const NvOdmPeripheralConnectivity *pConnectivity;
+    NvOdmAccelHandle  hAccel;
+
+    hAccel = NvOdmOsAlloc(sizeof(NvOdmAccel));
+    if (hAccel == NULL)
+    {
+        //NVODMACCELEROMETER_PRINTF("Error Allocating NvOdmAccel. \n");
+        return NV_FALSE;
+    }
+    NvOdmOsMemset(hAccel, 0, sizeof(NvOdmAccel));
+
+    hAccel->hPmu = NULL;
+    hAccel->hOdmI2C =  NULL;
+    hAccel->nBusType = NV_ACCELEROMETER_BUS_I2C;
+    
+    // Chip init cfg info here, here just a sample for common interrupt now!
+    // This part will move to a configuration table later.
+    // Start here.
+    // Only enable common interrupt
+    // Enable common and single tap at the same time.
+    hAccel->CtrlRegsList[0].RegAddr = XLR_CTL; //0x12
+    hAccel->CtrlRegsList[0].RegValue = 0x20;
+    hAccel->CtrlRegsList[1].RegAddr = XLR_INTCONTROL; //0x13
+    hAccel->CtrlRegsList[1].RegValue = 0xF3;  // modify so that sw is compatible
+    hAccel->CtrlRegsList[2].RegAddr = XLR_INTCONTROL2; //0x14
+    hAccel->CtrlRegsList[2].RegValue = 0xe0;
+    hAccel->CtrlRegsList[3].RegAddr = XLR_THRESHG; //0x1C
+    hAccel->CtrlRegsList[3].RegValue = NV_ADI340_ACCELEROMETER_NORMAL_THRESHOLD;
+    hAccel->CtrlRegsList[4].RegAddr = XLR_OFSX; //0x1E
+    hAccel->CtrlRegsList[4].RegValue = 0;
+    hAccel->CtrlRegsList[5].RegAddr = XLR_OFSY; //0x1F
+    hAccel->CtrlRegsList[5].RegValue = 0;
+    hAccel->CtrlRegsList[6].RegAddr = XLR_OFSZ; //0x20
+    hAccel->CtrlRegsList[6].RegValue = 0;
+    hAccel->CtrlRegsList[7].RegAddr = XLR_THRESHC; //0x1D
+    hAccel->CtrlRegsList[7].RegValue = NV_ADI340_ACCELEROMETER_TAP_THRESHOLD;
+    hAccel->CtrlRegsList[8].RegAddr = XLR_DUR; //0x21
+    hAccel->CtrlRegsList[8].RegValue = 0x40;
+    hAccel->CtrlRegsList[9].RegAddr = XLR_LATENT; //0x22
+    hAccel->CtrlRegsList[9].RegValue = 0xff;
+    hAccel->CtrlRegsList[10].RegAddr = XLR_INTVL; //0x23
+    hAccel->CtrlRegsList[10].RegValue = 0;
+    hAccel->CtrlRegsList[11].RegAddr = XLR_INTCONTROL2; //0x14
+    hAccel->CtrlRegsList[11].RegValue = 0xe1;
+    hAccel->CtrlRegsList[12].RegAddr = XLR_INTCONTROL2; //0x14
+    hAccel->CtrlRegsList[12].RegValue = 0xe0;
+    hAccel->nLength = 13;
+    // Stop here.
+    // Info of accelerometer with current setting.
+    hAccel->Caption.MaxForceInGs = 2000;
+    hAccel->Caption.MaxTapTimeDeltaInUs = 255;
+    hAccel->Caption.NumMotionThresholds = 1;
+    hAccel->Caption.SupportsFreefallInt = 0;
+    hAccel->Caption.MaxSampleRate = 100;
+    hAccel->Caption.MinSampleRate = 3;
+    hAccel->PowerState = NvOdmAccelPower_Fullrun;
+    hAccel->AxisXMapping = NvOdmAccelAxis_X;
+    hAccel->AxisXDirection = 1;
+    hAccel->AxisYMapping = NvOdmAccelAxis_Y;
+    hAccel->AxisYDirection = 1;
+    hAccel->AxisZMapping = NvOdmAccelAxis_Z;
+    hAccel->AxisZDirection = -1;
+    
+    hAccel->hPmu = NvOdmServicesPmuOpen();
+    if (!hAccel->hPmu)
+    {
+        //NVODMACCELEROMETER_PRINTF("NvOdmServicesPmuOpen Error \n");
+        goto error;
+    }
+    
+    pConnectivity = (NvOdmPeripheralConnectivity*)NvOdmPeripheralGetGuid(NV_ODM_GUID('a','c','c','e','l','e','r','o'));
+    if (!pConnectivity)
+    {
+        NvOdmOsDebugPrintf("NvOdmPeripheralGetGuid doesn't detect accelerometer device\n");
+        goto error;
+    }
+ 
+    if(pConnectivity->Class != NvOdmPeripheralClass_Other)
+    {
+        goto error;
+    }
+        
+    for( i = 0; i < pConnectivity->NumAddress; i++)
+    {
+        switch(pConnectivity->AddressList[i].Interface)
+        {
+            case NvOdmIoModule_I2c:
+                hAccel->I2CChannelId = pConnectivity->AddressList[i].Instance;
+                hAccel->nDevAddr = (NvU8)pConnectivity->AddressList[i].Address;
+                foundI2cModule = NV_TRUE;
+                break;
+            case NvOdmIoModule_Gpio:
+                hAccel->GPIOPortINT = pConnectivity->AddressList[i].Instance;
+                hAccel->GPIOPinINT = pConnectivity->AddressList[i].Address;
+                foundGpio = NV_TRUE;
+                break;
+            case NvOdmIoModule_Vdd:
+                hAccel->VddId = pConnectivity->AddressList[i].Address;
+                // Power on accelerometer according to Vddid
+                NvAccelerometerSetPowerRail(hAccel->hPmu, hAccel->VddId, NV_TRUE);
+                break;
+            default:
+                break;
+        }
+    }
+
+    if(foundGpio != NV_TRUE || foundI2cModule != NV_TRUE)
+    {
+        //NVODMACCELEROMETER_PRINTF("Accelerometer : didn't find any periperal in discovery query for touch device Error \n");
+        goto error;
+    }
+
+    
+    // Set up I2C bus.
+    if(NV_FALSE == NvAccelerometerI2COpen(&hAccel->hOdmI2C, hAccel->I2CChannelId))
+    {
+        goto error;
+    };
+    hAccel->RegsRead  = NvAccelerometerI2CGetRegs;
+    hAccel->RegsWrite = NvAccelerometerI2CSetRegs;
+    
+    NvOdmAccelerometerGetParameter(hAccel, XLR_WHOAMI, &test_val);
+    if(XLR_IDNUM != test_val)
+    {
+        goto error;
+    }
+    
+    NvOdmAccelerometerGetParameter(hAccel, XLR_DEVID, &test_val);
+    if (test_val == XLR_NEWCHIPID)
+    {
+        // This chip is ADXL345
+        //NvOdmOsDebugPrintf("This chip is ADXL345!!!\n");
+        hAccel->CtrlRegsList[4].RegValue = 0x0A; // offset X
+        hAccel->CtrlRegsList[5].RegValue = 0x0B; // offset Y
+        hAccel->CtrlRegsList[6].RegValue = 0x14; // offset Z
+    }
+    //NVODMACCELEROMETER_PRINTF("ID is 0x%x\n", test_val);
+    
+    /* We don't know the reset state of the accelerometer. So, program the
+     * accelerometer to disable generation of interrupts.
+     *  
+     *  Write to INTCONTROL register to disable genetration of the interrupts.
+     *  Write to INTCONTROL2 to clear the already latched interrupts.
+     */
+    NvOdmAccelerometerSetParameter(hAccel, XLR_ATTR_INTCONTROL, 0x0);
+    NvOdmAccelerometerSetParameter(hAccel, XLR_ATTR_INTCONTROL2, 0x1);
+    if(NV_FALSE == NvAccelerometerConnectSemaphore(hAccel))
+    {
+        goto error;
+    }
+    
+    //init accelerometer
+    for(i=0; i<hAccel->nLength; i++)
+    {
+            NvOdmAccelerometerSetParameter(hAccel,
+                                           hAccel->CtrlRegsList[i].RegAddr, 
+                                           hAccel->CtrlRegsList[i].RegValue);
+    }
+    // Set up event.
+    
+    //NvOdmAccelerometerGetParameter(XLR_SCALE, hAccel);
+    *hDevice = hAccel;
+    return NV_TRUE;
+    error:
+        // Release all of resources requested.
+        if(NULL != hAccel)
+        {
+            NvAccelerometerSetPowerRail(hAccel->hPmu, hAccel->VddId, NV_FALSE);
+            NvOdmServicesPmuClose(hAccel->hPmu);
+            hAccel->hPmu = NULL;
+            NvAccelerometerI2CClose(hAccel->hOdmI2C);
+            hAccel->hOdmI2C = NULL;
+            NvOdmOsFree(hAccel);
+            *hDevice = NULL;
+        }
+        return NV_FALSE;
+}
+
+void
+NvOdmAccelClose(NvOdmAccelHandle hDevice)
+{
+    if(NULL != hDevice)
+    {
+        if(NULL != hDevice->SemaphoreForINT &&
+           NULL != hDevice->hGpioINT &&
+           NULL != hDevice->hPinINT &&
+           NULL != hDevice->hGpioInterrupt)
+        {
+            NvOdmGpioInterruptUnregister(hDevice->hGpioINT,
+                                         hDevice->hPinINT,
+                                         hDevice->hGpioInterrupt);
+            NvOdmOsSemaphoreDestroy(hDevice->SemaphoreForINT);   
+            NvOdmGpioReleasePinHandle(hDevice->hGpioINT, hDevice->hPinINT);
+            NvOdmGpioClose(hDevice->hGpioINT);
+        }
+        NvAccelerometerI2CClose(hDevice->hOdmI2C);
+
+        // Power off accelermeter
+        NvAccelerometerSetPowerRail(hDevice->hPmu, hDevice->VddId, NV_FALSE);
+        if (hDevice->hPmu)
+        {
+            //NvAccelerometerSetPowerOn(0);
+            NvOdmServicesPmuClose(hDevice->hPmu);
+        }
+        
+        return;
+    }
+}
+
+/*
+ * After setting the force threshold, we should remove all of interrupt flag
+ * that may be left from the last threshold.
+ */
+NvBool
+NvOdmAccelSetIntForceThreshold(NvOdmAccelHandle  hDevice,
+                               NvOdmAccelIntType IntType,
+                               NvU32             IntNum,
+                               NvU32             Threshold)
+{
+    // At first, we need to translate the threshold to register value for acc.
+    // The first step is get current work range.
+    NvU32 uMaxThreshold;
+    NvU32 uThresholdToRegister;
+    NvU32 temp;
+
+    
+    NV_ASSERT(NULL != hDevice);
+    uMaxThreshold = hDevice->Caption.MaxForceInGs;
+    if(Threshold > uMaxThreshold)
+    {
+        //NVODMACCELEROMETER_PRINTF("Current accelerometer supprt max threshold is %d g\n", uMaxThreshold);
+        Threshold = uMaxThreshold;
+    }
+
+    uThresholdToRegister = (NvU8)(Threshold*((1<<(NV_ACCELEROMETER_REGISTER_RANGE-1))-1)/uMaxThreshold);
+    
+    // ADI345 can't receive interrupt while threshold = 0
+    if (uThresholdToRegister == 0)
+        uThresholdToRegister = 1;
+    
+    // We only enable 2 interrupt pins, INT2 for Motion, INT1 for single tap.
+    switch(IntType)
+    {
+        case NvOdmAccelInt_MotionThreshold:
+            //NvOdmOsDebugPrintf("Current motion setting threshold is %d \n", uThresholdToRegister);
+            //NvOdmOsDebugPrintf("the motion threshold program into reg is %d \n", uThresholdToRegister);
+            NvOdmAccelerometerSetParameter(hDevice, XLR_THRESHG, uThresholdToRegister);
+            break;
+        case NvOdmAccelInt_TapThreshold:
+            //NvOdmOsDebugPrintf("Current tap setting threshold is %d \n", uThresholdToRegister);
+            //NvOdmOsDebugPrintf("the tap threshold program into reg is %d \n", uThresholdToRegister);
+            NvOdmAccelerometerSetParameter(hDevice, XLR_THRESHC, uThresholdToRegister);
+            break;
+        default:
+            //NVODMACCELEROMETER_PRINTF("Do not support such Interrupt!\n");
+            return NV_FALSE;
+    }
+
+    // Clear interrupt flag.
+    NvOdmAccelerometerGetParameter(hDevice, XLR_INTCONTROL2, &temp); 
+    temp |= XLR_INTCONTROL2_CLR_INT;
+    NvOdmAccelerometerSetParameter(hDevice, XLR_INTCONTROL2, temp);
+    temp &= XLR_INTCONTROL2_CLR_INT_MASK;
+    NvOdmAccelerometerSetParameter(hDevice, XLR_INTCONTROL2, temp);
+    return NV_TRUE;
+}
+
+/*
+ * After setting the time threshold, we should remove all of interrupt flag
+ * that may be left from the last threshold.
+ */
+NvBool
+NvOdmAccelSetIntTimeThreshold(NvOdmAccelHandle  hDevice,
+                              NvOdmAccelIntType IntType,
+                              NvU32             IntNum,
+                              NvU32             Threshold)
+{
+    NvU32 temp;
+    NV_ASSERT(NULL != hDevice);
+    //its due adi340 limitation.
+    if(Threshold > 0xff)
+    {
+        //NVODMACCELEROMETER_PRINTF("The max threshold support is 255 ms for adi340\n");
+        return NV_FALSE;
+    }
+    //NvOdmOsDebugPrintf("The threshold is %d\n", Threshold);
+    switch(IntType)
+    {
+        case NvOdmAccelInt_TapThreshold:
+            NvOdmAccelerometerSetParameter(hDevice, XLR_DUR, Threshold);
+            NvOdmAccelerometerSetParameter(hDevice, XLR_INTVL, 0);
+            NvOdmAccelerometerSetParameter(hDevice, XLR_LATENT, 0);
+            break;
+        default:
+            //NVODMACCELEROMETER_PRINTF("Do not need set time threshold for such Interrupt!\n");
+            return NV_FALSE;
+    }
+
+    // Clear interrupt flag.
+    NvOdmAccelerometerGetParameter(hDevice, XLR_INTCONTROL2, &temp); 
+    temp |= XLR_INTCONTROL2_CLR_INT;
+    NvOdmAccelerometerSetParameter(hDevice, XLR_INTCONTROL2, temp);
+    temp &= XLR_INTCONTROL2_CLR_INT_MASK;
+    NvOdmAccelerometerSetParameter(hDevice, XLR_INTCONTROL2, temp);
+    return NV_TRUE;
+}
+
+/*
+ * After enable/disable threshold, we should remove all of interrupt flag
+ * that may be left from that last threshold.
+ */
+NvBool
+NvOdmAccelSetIntEnable(NvOdmAccelHandle  hDevice,
+                       NvOdmAccelIntType  IntType,
+                       NvOdmAccelAxisType IntAxis,
+                       NvU32              IntNum,
+                       NvBool             Toggle)
+{
+    NvU32 uTemp = 0;
+    NV_ASSERT(NULL != hDevice);
+    
+    switch(IntType)
+    {
+        case NvOdmAccelInt_MotionThreshold:
+            NvOdmAccelerometerGetParameter(hDevice, XLR_INTCONTROL, &uTemp);
+            //NvOdmOsDebugPrintf("INTCONTROL is 0x%x g\n", uTemp);
+            uTemp |= XLR_INTCONTROL_COM_INT_ENABLE;
+            switch(IntAxis)
+            {
+                case NvOdmAccelAxis_X:
+                {
+                    if(Toggle == NV_TRUE)
+                    {
+                        uTemp |= XLR_INTCONTROL_COM_SRC_X;
+                    }
+                    else
+                    {
+                        uTemp &= XLR_INTCONTROL_COM_SRC_X_MASK;
+                    }
+                    break;
+                }
+                case NvOdmAccelAxis_Y:
+                {
+                    if(Toggle == NV_TRUE)
+                    {
+                        uTemp |= XLR_INTCONTROL_COM_SRC_Y;
+                    }
+                    else
+                    {
+                        uTemp &= XLR_INTCONTROL_COM_SRC_Y_MASK;
+                    }
+                    break;
+                }
+                case NvOdmAccelAxis_Z:
+                {
+                    if(Toggle == NV_TRUE)
+                    {
+                        uTemp |= XLR_INTCONTROL_COM_SRC_Z;
+                    }
+                    else
+                    {
+                        uTemp &= XLR_INTCONTROL_COM_SRC_Z_MASK;
+                    }
+                    break;
+                }
+                case NvOdmAccelAxis_All:
+                {
+                    if(Toggle == NV_TRUE)
+                    {
+                        uTemp |= XLR_INTCONTROL_COM_SRC_X;
+                        uTemp |= XLR_INTCONTROL_COM_SRC_Y;
+                        uTemp |= XLR_INTCONTROL_COM_SRC_Z;
+                    }
+                    else
+                    {
+                        uTemp &= XLR_INTCONTROL_COM_SRC_X_MASK;
+                        uTemp &= XLR_INTCONTROL_COM_SRC_Y_MASK;
+                        uTemp &= XLR_INTCONTROL_COM_SRC_Z_MASK;
+                    }
+                    break;
+                }
+                default:
+                    return NV_FALSE;
+            }
+            NvOdmAccelerometerSetParameter(hDevice, XLR_INTCONTROL, uTemp);
+            break;
+        case NvOdmAccelInt_TapThreshold:
+            NvOdmAccelerometerGetParameter(hDevice, XLR_INTCONTROL, &uTemp);
+            //NvOdmOsDebugPrintf("INTCONTROL is 0x%x \n", uTemp);
+            uTemp |= XLR_INTCONTROL_TAP_INT_ENABLE;
+            NvOdmAccelerometerSetParameter(hDevice, XLR_INTCONTROL, uTemp);
+            NvOdmAccelerometerGetParameter(hDevice, XLR_INTCONTROL2, &uTemp);
+            //NvOdmOsDebugPrintf("INTCONTROL2 is 0x%x \n", uTemp);
+            switch(IntAxis)
+            {
+                case NvOdmAccelAxis_X:
+                {
+                    if(Toggle == NV_TRUE)
+                    {
+                        uTemp |= XLR_INTCONTROL2_TAP_SRC_X;
+                    }
+                    else
+                    {
+                        uTemp &= XLR_INTCONTROL2_TAP_SRC_X_MASK;
+                    }
+                        break;
+                }
+                case NvOdmAccelAxis_Y:
+                {
+                    if(Toggle == NV_TRUE)
+                    {
+                        uTemp |= XLR_INTCONTROL2_TAP_SRC_Y;
+                    }
+                    else
+                    {
+                        uTemp &= XLR_INTCONTROL2_TAP_SRC_Y_MASK;
+                    }
+                        break;
+                }
+                case NvOdmAccelAxis_Z:
+                {
+                    if(Toggle == NV_TRUE)
+                    {
+                        uTemp |= XLR_INTCONTROL2_TAP_SRC_Z;
+                    }
+                    else
+                    {
+                        uTemp &= XLR_INTCONTROL2_TAP_SRC_Z_MASK;
+                    }
+                        break;
+                }
+                case NvOdmAccelAxis_All:
+                {
+                    if(Toggle == NV_TRUE)
+                    {
+                        uTemp |= XLR_INTCONTROL2_TAP_SRC_X;
+                        uTemp |= XLR_INTCONTROL2_TAP_SRC_Y;
+                        uTemp |= XLR_INTCONTROL2_TAP_SRC_Z;
+                    }
+                    else
+                    {
+                        uTemp &= XLR_INTCONTROL2_TAP_SRC_X_MASK;
+                        uTemp &= XLR_INTCONTROL2_TAP_SRC_Y_MASK;
+                        uTemp &= XLR_INTCONTROL2_TAP_SRC_Z_MASK;
+                    }
+                        break;
+                }
+                default:
+                    return NV_FALSE;
+            }
+            NvOdmAccelerometerSetParameter(hDevice, XLR_INTCONTROL2, uTemp);
+            break;
+        default:
+            //NVODMACCELEROMETER_PRINTF("Do not support such Interrupt!\n");
+            return NV_FALSE;
+    }
+
+    // Clear interrupt flag.
+    NvOdmAccelerometerGetParameter(hDevice, XLR_INTCONTROL2, &uTemp); 
+    uTemp |= XLR_INTCONTROL2_CLR_INT;
+    NvOdmAccelerometerSetParameter(hDevice, XLR_INTCONTROL2, uTemp);
+    uTemp &= XLR_INTCONTROL2_CLR_INT_MASK;
+    NvOdmAccelerometerSetParameter(hDevice, XLR_INTCONTROL2, uTemp);
+    return NV_TRUE;
+}
+
+
+void
+NvOdmAccelWaitInt(NvOdmAccelHandle    hDevice,
+                          NvOdmAccelIntType  *IntType,
+                          NvOdmAccelAxisType *IntMotionAxis,
+                          NvOdmAccelAxisType *IntTapAxis)
+{
+    NvU32  temp;
+    NV_ASSERT(NULL != hDevice);
+    NV_ASSERT(NULL != IntType);
+    NV_ASSERT(NULL != IntMotionAxis);
+    NV_ASSERT(NULL != IntTapAxis);
+    
+    NvOdmOsSemaphoreWait( hDevice->SemaphoreForINT);
+    
+    NvAccelerometerGetInterruptSouce( hDevice , IntType, IntMotionAxis, IntTapAxis);
+    //NvOdmOsDebugPrintf("Captured interrupt!!!\n");
+    NvOdmAccelerometerGetParameter(hDevice, XLR_INTCONTROL2, &temp); 
+    temp |= XLR_INTCONTROL2_CLR_INT;
+    NvOdmAccelerometerSetParameter(hDevice, XLR_INTCONTROL2, temp);
+    temp &= XLR_INTCONTROL2_CLR_INT_MASK;
+    NvOdmAccelerometerSetParameter(hDevice, XLR_INTCONTROL2, temp);
+
+    //This is a WAR for ADI340 to prevent I2C register from unstable state
+    NvOdmAccelerometerGetParameter(hDevice, XLR_INTCONTROL, &temp);
+    //NvOdmOsDebugPrintf("XLR_INTCONTROL is 0x%x\n", temp);
+    NvOdmAccelerometerGetParameter(hDevice, XLR_THRESHG, &temp);
+    //NvOdmOsDebugPrintf("XLR_THRESHG is 0x%x\n", temp);
+    NvOdmAccelerometerGetParameter(hDevice, XLR_INTSOURCE, &temp);
+    //NvOdmOsDebugPrintf("XLR_INTSOURCE is 0x%x\n", temp);
+    return ;
+}
+
+
+void NvOdmAccelSignal(NvOdmAccelHandle hDevice)
+{
+    NvOdmOsSemaphoreSignal(hDevice->SemaphoreForINT);
+}
+
+NvBool
+NvOdmAccelGetAcceleration(NvOdmAccelHandle hDevice,
+                          NvS32           *AccelX,
+                          NvS32           *AccelY,
+                          NvS32           *AccelZ)
+{
+    NvS32 data = 0;
+    NV_ASSERT(NULL != hDevice);
+    NV_ASSERT(NULL != AccelX);
+    NV_ASSERT(NULL != AccelY);
+    NV_ASSERT(NULL != AccelZ);
+    
+    //fix error for adi340 i2c bug. XLR_OFSZ will be set to 0xA0 randomly.
+    NvOdmAccelerometerSetParameter(hDevice, XLR_OFSZ, 0);
+
+    NvOdmAccelerometerGetParameter(hDevice, XLR_DATAX, (NvU32*)&data);
+    //NvOdmOsDebugPrintf("DATAX is %d , after normalization is ", data);
+    data = (((NvS32)(hDevice->Caption.MaxForceInGs))*data+(NvS32)(NV_ADI340_MAX_FORCE_IN_REG/2))/
+             (NvS32)NV_ADI340_MAX_FORCE_IN_REG;
+    switch(hDevice->AxisXMapping)
+    {
+        case NvOdmAccelAxis_X:
+            *AccelX = data*hDevice->AxisXDirection;
+            break;
+        case NvOdmAccelAxis_Y:
+            *AccelY = data*hDevice->AxisYDirection;
+            break;
+        case NvOdmAccelAxis_Z:
+            *AccelZ = data*hDevice->AxisZDirection;
+            break;
+        default:
+            return NV_FALSE;
+    }
+    //NvOdmOsDebugPrintf("%d \n", data);
+    NvOdmAccelerometerGetParameter(hDevice, XLR_DATAY, (NvU32*)&data);
+    //NvOdmOsDebugPrintf("DATAY is %d , after normalization is ", data);
+    data = (((NvS32)(hDevice->Caption.MaxForceInGs))*data+(NvS32)(NV_ADI340_MAX_FORCE_IN_REG/2))/
+             (NvS32)NV_ADI340_MAX_FORCE_IN_REG;
+    switch(hDevice->AxisYMapping)
+    {
+        case NvOdmAccelAxis_X:
+            *AccelX = data*hDevice->AxisXDirection;
+            break;
+        case NvOdmAccelAxis_Y:
+            *AccelY = data*hDevice->AxisYDirection;
+            break;
+        case NvOdmAccelAxis_Z:
+            *AccelZ = data*hDevice->AxisZDirection;
+            break;
+        default:
+            return NV_FALSE;
+    }
+    //NvOdmOsDebugPrintf("%d \n", data);
+    NvOdmAccelerometerGetParameter(hDevice, XLR_DATAZ, (NvU32*)&data);
+    //NvOdmOsDebugPrintf("DATAZ is %d , after normalization is ", data);
+    data = (((NvS32)(hDevice->Caption.MaxForceInGs))*data+(NvS32)(NV_ADI340_MAX_FORCE_IN_REG/2))/
+             (NvS32)NV_ADI340_MAX_FORCE_IN_REG;
+    switch(hDevice->AxisZMapping)
+    {
+        case NvOdmAccelAxis_X:
+            *AccelX = data*hDevice->AxisXDirection;
+            break;
+        case NvOdmAccelAxis_Y:
+            *AccelY = data*hDevice->AxisYDirection;
+            break;
+        case NvOdmAccelAxis_Z:
+            *AccelZ = data*hDevice->AxisZDirection;
+            break;
+        default:
+            return NV_FALSE;
+    }
+    //NvOdmOsDebugPrintf("%d \n", data);
+    return NV_TRUE;
+}
+
+NvOdmAccelerometerCaps
+NvOdmAccelGetCaps(NvOdmAccelHandle hDevice)
+{
+    NV_ASSERT(NULL != hDevice);
+    
+    return hDevice->Caption;
+}
+
+NvBool
+NvOdmAccelSetSampleRate(NvOdmAccelHandle hDevice, NvU32 SampleRate)
+{
+    NvU32 PowerFlag = 0;
+    NV_ASSERT(NULL != hDevice);
+    NvOdmAccelerometerGetParameter(hDevice, XLR_CTL, &PowerFlag);
+    if(SampleRate > NV_ADI340_LOW_POWER_SAMPLERATE)////3 is the info get from datasheet
+    {
+        //if(NvOdmAccelPower_Fullrun != hDevice->PowerState)
+        {
+                PowerFlag &= XLR_CTL_POWER_MASK;
+                PowerFlag |= XLR_CTL_FULL_RUN;
+                PowerFlag &= XLR_CTL_MODE_MASK;
+                PowerFlag |= XLR_CTL_MEASURE_MODE;
+                NvOdmAccelerometerSetParameter(hDevice, XLR_CTL, PowerFlag);
+                hDevice->PowerState = NvOdmAccelPower_Fullrun;
+        }
+    }
+    else
+    {
+        //if(NvOdmAccelPower_Low != hDevice->PowerState)
+        {
+                PowerFlag &= XLR_CTL_POWER_MASK;
+                PowerFlag |= XLR_CTL_LOW_POWER;
+                PowerFlag &= XLR_CTL_MODE_MASK;
+                PowerFlag |= XLR_CTL_MEASURE_MODE;
+                NvOdmAccelerometerSetParameter(hDevice, XLR_CTL, PowerFlag);
+                hDevice->PowerState = NvOdmAccelPower_Low;
+        }
+    }
+    return NV_TRUE;
+}
+
+NvBool
+NvOdmAccelGetSampleRate(NvOdmAccelHandle hDevice, NvU32 *pSampleRate)
+{
+    NvU32 SampleFlag = 0;
+    NV_ASSERT(NULL != hDevice);
+    NvOdmAccelerometerGetParameter(hDevice, XLR_CTL, &SampleFlag);
+    
+    if((SampleFlag&XLR_CTL_LOW_POWER))
+    {
+        *pSampleRate = NV_ADI340_LOW_POWER_SAMPLERATE;
+    }
+    else
+    {
+        *pSampleRate = NV_ADI340_FULL_RUN_SAMPLERATE;
+    }
+    return NV_TRUE;
+}
+
+NvBool
+NvOdmAccelSetPowerState(NvOdmAccelHandle hDevice, NvOdmAccelPowerType PowerState)
+{
+    NvU32 PowerFlag = 0;
+    NV_ASSERT(NULL != hDevice);
+    NvOdmAccelerometerGetParameter(hDevice, XLR_CTL, &PowerFlag);
+    switch(PowerState)
+    {
+        case NvOdmAccelPower_Fullrun:
+            if(NvOdmAccelPower_Fullrun != hDevice->PowerState)
+            {
+                PowerFlag &= XLR_CTL_POWER_MASK;
+                PowerFlag |= XLR_CTL_FULL_RUN;
+                PowerFlag &= XLR_CTL_MODE_MASK;
+                PowerFlag |= XLR_CTL_MEASURE_MODE;
+                NvOdmAccelerometerSetParameter(hDevice, XLR_CTL, PowerFlag);
+                hDevice->PowerState = NvOdmAccelPower_Fullrun;
+            }
+            break;
+        case NvOdmAccelPower_Low:
+            if(NvOdmAccelPower_Low != hDevice->PowerState)
+            {
+                PowerFlag &= XLR_CTL_POWER_MASK;
+                PowerFlag |= XLR_CTL_LOW_POWER;
+                PowerFlag &= XLR_CTL_MODE_MASK;
+                PowerFlag |= XLR_CTL_MEASURE_MODE;
+                NvOdmAccelerometerSetParameter(hDevice, XLR_CTL, PowerFlag);
+                hDevice->PowerState = NvOdmAccelPower_Low;
+            }
+            break;
+        case NvOdmAccelPower_Standby:
+            if(NvOdmAccelPower_Standby != hDevice->PowerState)
+            {
+                PowerFlag &= XLR_CTL_MODE_MASK;
+                PowerFlag |= XLR_CTL_STANDBY_MODE;
+                NvOdmAccelerometerSetParameter(hDevice, XLR_CTL, PowerFlag);
+                hDevice->PowerState = NvOdmAccelPower_Standby;
+            }
+            break;
+        case NvOdmAccelPower_Off:
+            //the implementation should consider real board connection
+            //sometimes we need use acc's interrupt to resum the whole
+            //system, so the power are alway supplied.
+            return NV_FALSE;
+        default:
+            return NV_FALSE;
+    }
+    return NV_TRUE;
+}
+
diff --git a/arch/arm/mach-tegra/odm_kit/platform/accelerometer/nvodm_accelerometer_adi340.h b/arch/arm/mach-tegra/odm_kit/platform/accelerometer/nvodm_accelerometer_adi340.h
new file mode 100644
index 000000000000..3febae3b1f40
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/platform/accelerometer/nvodm_accelerometer_adi340.h
@@ -0,0 +1,321 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+ 
+/*  NVIDIA Tegra ODM Kit Sample Accelerometer Adaptation of the
+ *  WinCE Accelerometer Driver
+ */
+
+#ifndef INCLUDED_NVODM_ACCELEROMETER_ADI340_H
+#define INCLUDED_NVODM_ACCELEROMETER_ADI340_H
+
+#if defined(_cplusplus)
+extern "C"
+{
+#endif
+
+#include "nvodm_services.h"
+#include "nvodm_accelerometer.h"
+
+ /* Will keep some attributes from customer in the future */
+ #define XLR_ATTR_CTL 0
+ #define XLR_ATTR_INTCONTROL 1
+ #define XLR_ATTR_INTCONTROL2 2
+ #define XLR_ATTR_THRESHG 3
+ #define XLR_ATTR_THRESHC 4
+ #define XLR_ATTR_OFSX 5
+ #define XLR_ATTR_OFSY 6
+ #define XLR_ATTR_OFSZ 7
+ #define XLR_ATTR_DUR  8
+ #define XLR_ATTR_LATENT 9
+ #define XLR_ATTR_INTVL 10
+ #define XLR_ATTR_WHOAMI 11
+ #define XLR_ATTR_STATUS 12
+ #define XLR_ATTR_INTSOURCE 13
+ #define XLR_ATTR_DATAX 14
+ #define XLR_ATTR_DATAY 15
+ #define XLR_ATTR_DATAZ 16
+ #define XLR_ATTR_MOREINFO 17
+ #define XLR_ATTR_SCALE  18
+ #define XLR_ATTR_ROTATE 19
+ #define XLR_ATTR_GYRO  20
+ 
+// AD22345 register definitions
+#define XLR_DEVID 0x00
+
+// AD22340 register definitions
+#define XLR_WHOAMI      0x0f        // RO - device identification
+#define XLR_STATUS      0x10        // RO - device status bits
+#define XLR_STATUS_DATA_READY            0x80 //0b10000000  indicate that data in XLR_DATAX,Y,Z can be read.
+#define XLR_STATUS_DATA_OVERRUN         0x02 //0b00000010  indicate that the old data in XLR_DATAX,Y,Z have not be read
+#define XLR_STATUS_INTRRUPT_PENDING     0x01 //0b00000001  indicate that interrupt is active.
+
+#define XLR_INTSOURCE   0x11        // RO - interrupt source
+#define XLR_INTSOURCE_X_TAP_MASK        0x80 //0b10000000  tap interrupt is from x-axis
+#define XLR_INTSOURCE_Y_TAP_MASK        0x40 //0b01000000  tap interrupt is from y-axis
+#define XLR_INTSOURCE_Z_TAP_MASK        0x20 //0b00100000  tap interrupt is from z-axis
+#define XLR_INTSOURCE_X_COM_MASK        0x10 //0b00010000  comm interrupt is from x-axis
+#define XLR_INTSOURCE_Y_COM_MASK        0x8  //0b00001000  comm interrupt is from y-axis
+#define XLR_INTSOURCE_Z_COM_MASK        0x4  //0b00000100  comm interrupt is from z-axis
+#define XLR_INTSOURCE_SINGLE_TAP_MASK    0x2  //0b00000010  single tap mask
+#define XLR_INTSOURCE_DOUBLE_TAP_MASK    0x1  //0b00000001  double tap mask
+
+#define XLR_CTL         0x12        // RW - device control reg
+#define XLR_CTL_POWER_MASK              0xbf //0b10111111
+#define XLR_CTL_LOW_POWER               0x40 //0b01000000  low power mode
+#define XLR_CTL_FULL_RUN                0x00 //0b00000000  full run mode
+#define XLR_CTL_MODE_MASK               0xdf //0b11011111
+#define XLR_CTL_STANDBY_MODE            0x0  //0b00000000  standby mode
+#define XLR_CTL_MEASURE_MODE            0x20 //0b00100000  measure mode
+#define XLR_CTL_SPI_3_BUS               0x0  //0b00000000  3 wires SPI mode
+#define XLR_CTL_SPI_4_BUS               0x10 //0b00010000  4 wires SPI mode
+#define XLR_CTL_SELF_TEST_MODE          0x4  //0b00000100  self test mode
+#define XLR_CTL_INT1_FUNC_MASK            0xfd //0b11111101  range mask
+#define XLR_CTL_INT1_DATA_READY_MODE      0x2  //0b00000010  INT1 pin is data ready flag
+#define XLR_CTL_INT1_INTRUPT_MODE         0x0  //0b00000000  INT1 pin is interrupt flag
+#define XLR_CTL_RANGE_MASK              0xfe //0b11111110  range mask
+#define XLR_CTL_8G_RANGE                0x1  //0b00000001  range is 8g
+#define XLR_CTL_2G_RANGE                0x0  //0b00000000  range is 2g
+
+#define XLR_INTCONTROL  0x13        // RW - interrupt control/config reg
+#define XLR_INTCONTROL_COM_SRC_X_MASK 0x7f //0b01111111
+#define XLR_INTCONTROL_COM_SRC_X      0x80 //0b10000000  x participate common interrupt
+#define XLR_INTCONTROL_COM_SRC_Y_MASK 0xbf //0b10111111
+#define XLR_INTCONTROL_COM_SRC_Y      0x40 //0b01000000  y participate common interrupt
+#define XLR_INTCONTROL_COM_SRC_Z_MASK 0xdf //0b11011111
+#define XLR_INTCONTROL_COM_SRC_Z      0x20 //0b00100000  z participate common interrupt
+#define XLR_INTCONTROL_SINGLE_DOUBLE_MASK 0xef //0b11101111
+#define XLR_INTCONTROL_SINGLE_TAP       0x10 //0b00010000  detect single tap
+#define XLR_INTCONTROL_DOUBLE_TAP       0x0  //0b00000000  detect double tap
+#define XLR_INTCONTROL_INTERRUPT_MAP_MASK 0xfb //0b11111011
+#define XLR_INTCONTROL_INTERRUPT_MAP1   0x4  //0b00000100  common interrupt map to INT2, tap interrupt map to INT1
+#define XLR_INTCONTROL_INTERRUPT_MAP2   0x0  //0b00000000  common interrupt map to INT1, tap interrupt map to INT2
+#define XLR_INTCONTROL_TAP_INT_MASK     0xfd //0b11111101
+#define XLR_INTCONTROL_TAP_INT_ENABLE   0x2  //0b00000010  enable the tap interrupt.
+#define XLR_INTCONTROL_COM_INT_MASK     0xfe //0b11111110
+#define XLR_INTCONTROL_COM_INT_ENABLE   0x1  //0b00000001  enable the common interrupt.
+
+#define XLR_INTCONTROL2 0x14        // RW - interrupt control/config reg 2
+#define XLR_INTCONTROL2_TAP_SRC_X_MASK 0x7f //0b01111111
+#define XLR_INTCONTROL2_TAP_SRC_X      0x80 //0b10000000  x participate tap interrupt
+#define XLR_INTCONTROL2_TAP_SRC_Y_MASK 0xbf //0b10111111
+#define XLR_INTCONTROL2_TAP_SRC_Y      0x40 //0b01000000  y participate tap interrupt
+#define XLR_INTCONTROL2_TAP_SRC_Z_MASK 0xdf //0b11011111
+#define XLR_INTCONTROL2_TAP_SRC_Z      0x20 //0b00100000  z participate tap interrupt
+#define XLR_INTCONTROL2_CLR_INT_MASK   0xfe //0b11111110
+#define XLR_INTCONTROL2_CLR_INT        0x1  //0b00000001  clear interrupt bit and pin
+
+#define XLR_DATAX       0x15        // RO - data from X axis
+#define XLR_DATAY       0x16        // RO - data from Y axis
+#define XLR_DATAZ       0x17        // RO - data from Z axis
+#define XLR_MOREINFO    0x1b        // RO - additional device info
+
+#define XLR_THRESHG     0x1c        // RW - common interrupt threshold reg
+#define XLR_THRESHC     0x1d        // RW - click threshold reg
+
+#define XLR_OFSX        0x1e        // RW - x axis offset reg
+#define XLR_OFSY        0x1f        // RW - y axis offset reg
+#define XLR_OFSZ        0x20        // RW - z axis offset reg
+#define XLR_DUR         0x21        // RW - click duration reg
+#define XLR_LATENT      0x22        // RW - click latency reg
+#define XLR_INTVL       0x23        // RW - click interval reg
+
+//virtual register which should translated in driver.
+#define XLR_SCALE       0x24
+#define XLR_ROTATE      0x25
+#define XLR_GYRO        0x26
+
+/*
+ * Defines the threshold source for the accelerometer.
+ */
+typedef enum
+{
+    /// Indicates the accelerometer generated interrupt by exceeding the x threshold.
+    NvOdmAccelerometerThresholdSource_X = 0,
+
+    /// Indicates the accelerometer generated interrupt by exceeding the y threshold.
+    NvOdmAccelerometerThresholdSource_Y,
+
+    /// Indicates the accelerometer generated interrupt by exceeding the z threshold.
+    NvOdmAccelerometerThresholdSource_Z,
+
+    NvOdmAccelerometerThresholdSource_Force32 = 0x7FFFFFFF
+} NvOdmAccelerometerThresholdSource;
+
+// I2C device address from accelerator.
+enum { I2C_ACCELRATOR_ADDRESS = 0x3A};
+// Timeout for I2C transaction.
+enum { I2C_ACCELRATOR_TRANSACTION_TIMEOUT = 1000 };
+// Maximum number of packetsize supported by the I2C controller.
+enum { I2C_ACCELRATOR_PACKET_SIZE = 8};
+static NvU8 s_ReadBuffer[I2C_ACCELRATOR_PACKET_SIZE];
+static NvU8 s_WriteBuffer[I2C_ACCELRATOR_PACKET_SIZE];
+
+// Fixed device identification code.
+#define XLR_IDNUM       0x4A
+
+#define XLR_NEWCHIPID   0xE5
+
+#define INT_EVENT_TIMEOUT 100
+#define NV_ACCELEROMETER_BUS_I2C 0
+#define NV_ACCELEROMETER_BUS_SPI_3 1
+#define NV_ACCELEROMETER_BUS_SPI_4 2
+/*
+// All of interrupt pins from accelerometer are connected to one interrupt pin of ap15.
+#define NV_ACCELEROMETER_INTERRUPT_GPIO_PORT   'C'-'A'
+#define NV_ACCELEROMETER_INTERRUPT_GPIO_PIN    7
+// only work for ap10 hw connection
+#define NV_ACCELEROMETER_INTERRUPT1_GPIO_PORT   'C'-'A'
+#define NV_ACCELEROMETER_INTERRUPT1_GPIO_PIN    7
+#define NV_ACCELEROMETER_INTERRUPT2_GPIO_PORT   'C'-'A'
+#define NV_ACCELEROMETER_INTERRUPT2_GPIO_PIN    1
+*/
+/*g value under 8g*/
+#define NVODM_ACCELEROMETER_G_UNDER_8G   16
+/*g value under 2g*/
+#define NVODM_ACCELEROMETER_G_UNDER_2G   64
+
+// Module debug: 0=disable, 1=enable
+#define NVODMACCELEROMETER_ENABLE_PRINTF (0)
+
+#if NVODMACCELEROMETER_ENABLE_PRINTF
+    #define NVODMACCELEROMETER_PRINTF   NvOdmOsDebugPrintf
+#else
+    #define NVODMACCELEROMETER_PRINTF   (void)
+#endif
+/*
+ * Defines the way to read accelerometer registers.
+ */
+typedef NvBool (*AccelerometerRegsRead)(NvOdmAccelHandle hDevice, NvU8 nRegOffset, NvU8* nData, NvU32 nLen);
+/*
+ * Defines the way to write accelerometer registers.
+ */
+typedef NvBool (*AccelerometerRegsWrite)(NvOdmAccelHandle hDevice, NvU8 nRegOffset, NvU8* nData, NvU32 nLen);
+/*
+ * Holds register address and value pairs. 
+ */
+typedef struct NvDevCtrlRegRec {
+   /// Holds the register offset.
+   NvU8 RegAddr;
+   /// Holds the value programmed into the upper address.
+   NvU8 RegValue;
+} NvDevCtrlReg;
+/*
+ * Max accelerometer registers number.
+ */
+#define ACCELEROMETER_CONTROL_REGS_MAX_LENGHT 100
+/*
+ * Max accelerometer callback functions number.
+ */
+#define ACCELEROMETER_CALLBACK_ARRAY_LENGTH   5
+
+/*
+ * Gets parameters relating to the accelerometer.
+ * attrib: Specifies the attributes to get.
+ * - XLR_ATTR_DATAX--gets data from x-axis.
+ * - XLR_ATTR_DATAY--gets data from y-axis.
+ * - XLR_ATTR_DATAZ--gets data from z-axis.
+ * - XLR_ATTR_OFSX--gets the x-axis offset.
+ * - XLR_ATTR_OFSY--gets the y-axis offset.
+ * - XLR_ATTR_OFSZ--gets the z-axis offset.
+ *   
+ * info: A pointer to the returned parameters.
+ * Returns NV_TRUE if successful, or NV_FALSE otherwise.
+ */
+NvBool
+NvOdmAccelerometerGetParameter(NvOdmAccelHandle hDevice, NvU8 attrib, NvU32* info);
+
+/*
+ * Sets parameters relating to the accelerometer,
+ * according to the caller's requirements.
+ * attrib: Specifies the attributes to set.
+ * - XLR_ATTR_OFSX--sets the x-axis offset.
+ * - XLR_ATTR_OFSY--sets the y-axis offset.
+ * - XLR_ATTR_OFSZ--sets the z-axis offset.
+ * info: Specifies the parameter information to set.
+ * Returns NV_TRUE if successful, or NV_FALSE otherwise.
+ */
+ 
+NvBool
+NvOdmAccelerometerSetParameter(NvOdmAccelHandle hDevice, NvU8 attrib, NvU32 info);
+
+//-----------------------------------------------------------------
+//--------------------------New API--------------------------------
+//-----------------------------------------------------------------
+
+typedef struct NvOdmAccelRec
+{
+    // Specifies use I2C or SPI to configure accelerometer registers.
+    NvU8 nBusType;
+    // Specifies accelerometer device address, for example, I2C write address.
+    NvU8 nDevAddr;
+    // Specifies the initial value that make accelerometer work, ACCELEROMETER_CONTROL_REGS_MAX_LENGHT is always 100.
+    NvDevCtrlReg CtrlRegsList[ACCELEROMETER_CONTROL_REGS_MAX_LENGHT];
+    // Specifies the initial CtrlRegsList length.
+    NvU8 nLength;
+    // Specifies accelerometer chip ID.
+    NvU8 nChipID;
+    // Specifies the way to get accelerometer register information.
+    AccelerometerRegsRead RegsRead;
+    // Specifies the way to set accelerometer register information.
+    AccelerometerRegsWrite RegsWrite;
+    // Specifies I2C handle from the system.
+    NvOdmServicesI2cHandle  hOdmI2C;
+    // Interrupt pin to ap15.
+    NvOdmServicesGpioHandle hGpioINT;
+    NvOdmGpioPinHandle      hPinINT;
+    NvU32 GPIOPortINT;
+    NvU32 GPIOPinINT;
+    NvOdmOsSemaphoreHandle SemaphoreForINT;
+    NvOdmServicesGpioIntrHandle hGpioInterrupt;
+    NvOdmAccelIntType Data;
+    NvOdmServicesPmuHandle hPmu;
+    NvU32 VddId;
+    NvU32 I2CChannelId;
+    NvOdmAccelerometerCaps Caption;
+    NvOdmAccelPowerType PowerState;
+    // In real case, when the board put in frontispiece, the value from z axis
+    // should be g, but due to physical connect on different board, the axis
+    // should be remapped to the correct one.
+    NvOdmAccelAxisType AxisXMapping;
+    // If the physical direct is the same with our expection, the value
+    // should be set to 1, or else the value should be -1.
+    NvS32              AxisXDirection;
+    NvOdmAccelAxisType AxisYMapping;
+    NvS32              AxisYDirection;
+    NvOdmAccelAxisType AxisZMapping;
+    NvS32              AxisZDirection;
+} NvOdmAccel;
+
+#if defined(__cplusplus)
+}
+#endif
+#endif
diff --git a/arch/arm/mach-tegra/odm_kit/platform/accelerometer/nvodm_accelerometer_bma150.c b/arch/arm/mach-tegra/odm_kit/platform/accelerometer/nvodm_accelerometer_bma150.c
new file mode 100644
index 000000000000..aedf87c837a9
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/platform/accelerometer/nvodm_accelerometer_bma150.c
@@ -0,0 +1,622 @@
+/*
+ * Copyright (c) 2010 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/*  NVIDIA Tegra ODM Kit Sample Accelerometer Adaptation of the
+ *  WinCE Accelerometer Driver
+ */
+
+#include "nvodm_accelerometer_bma150.h"
+#include "nvodm_services.h"
+#include "nvodm_query_discovery.h"
+#include "nvos.h"
+
+#define NVODMACCELEROMETER_ENABLE_PRINTF 0
+
+#if NVODMACCELEROMETER_ENABLE_PRINTF
+    #define NVODMACCELEROMETER_PRINTF(x) \
+    do { \
+        NvOdmOsPrintf x; \
+    } while (0)
+#else
+    #define NVODMACCELEROMETER_PRINTF(x)
+#endif
+
+#define NV_BMA150_MAX_FORCE_IN_REG 512 // It indicates force register length.
+#define NV_DEBOUNCE_TIME_MS 0
+
+#define ENABLE_XYZ_POLLING 0
+
+//FIXME: protect this variable using spinlock.
+static volatile int g_WaitCounter = 0;
+static void BMA150_ResetInterrupt(NvOdmAccelHandle hDevice);
+
+static void
+SetPowerRail(
+    NvOdmServicesPmuHandle hPMUDevice,
+    NvU32 Id,
+    NvBool IsEnable)
+{
+    NvOdmServicesPmuVddRailCapabilities vddrailcap;
+    NvU32 settletime;
+
+    if (hPMUDevice && Id)
+    {
+        NvOdmServicesPmuGetCapabilities(hPMUDevice, Id, &vddrailcap);
+        if (IsEnable)
+        {
+            NvOdmServicesPmuSetVoltage(hPMUDevice, Id,
+                vddrailcap.requestMilliVolts, &settletime);
+        }
+        else
+        {
+            NvOdmServicesPmuSetVoltage(hPMUDevice, Id,
+                vddrailcap.MinMilliVolts, &settletime);
+        }
+        NvOdmOsWaitUS(settletime);
+    }
+}
+
+static void GpioInterruptHandler(void *arg)
+{
+    NvU32 pinValue;
+    NvOdmAccelHandle hDevice =  (NvOdmAccelHandle)arg;
+
+    NvOdmGpioGetState(hDevice->hGpioINT, hDevice->hPinINT, &pinValue);
+    if (pinValue == 1)
+    {
+        NVODMACCELEROMETER_PRINTF(("\r\nBMA150 Interrupt"));
+        g_WaitCounter = 10;
+        BMA150_ResetInterrupt(hDevice);
+    } else
+        NVODMACCELEROMETER_PRINTF(("\r\nBMA150 non-Interrupt"));
+
+    if (pinValue == 1)
+    {
+        NvOdmOsSemaphoreSignal(hDevice->SemaphoreForINT);
+    }
+    NvOdmGpioInterruptDone(hDevice->hGpioInterrupt);
+    return;
+}
+
+static NvBool ConnectSemaphore(NvOdmAccelHandle hDevice)
+{
+    NvOdmGpioPinMode mode;
+    NvOdmInterruptHandler callback =
+        (NvOdmInterruptHandler)GpioInterruptHandler;
+
+    hDevice->hGpioINT = (NvOdmServicesGpioHandle)NvOdmGpioOpen();
+    if (!(hDevice->hGpioINT))
+    {
+        NVODMACCELEROMETER_PRINTF((
+            "NvOdm Accelerometer : NvOdmGpioOpen Error \n"));
+        return NV_FALSE;
+    }
+
+    hDevice->hPinINT = NvOdmGpioAcquirePinHandle(hDevice->hGpioINT,
+                           hDevice->GPIOPortINT,
+                           hDevice->GPIOPinINT);
+    hDevice->SemaphoreForINT = NvOdmOsSemaphoreCreate(0);
+
+    if (!(hDevice->SemaphoreForINT))
+    {
+        NVODMACCELEROMETER_PRINTF((
+            "NvOdm Accelerometer : NvOdmOsSemaphoreCreate Error \n"));
+        NvOdmGpioClose(hDevice->hGpioINT);
+        return NV_FALSE;
+    }
+
+    mode = NvOdmGpioPinMode_InputInterruptHigh;
+    if (NvOdmGpioInterruptRegister(hDevice->hGpioINT,
+        &hDevice->hGpioInterrupt, hDevice->hPinINT, mode, callback,
+        hDevice, NV_DEBOUNCE_TIME_MS) == NV_FALSE)
+    {
+        return NV_FALSE;
+    }
+
+    if (!(hDevice->hGpioInterrupt))
+    {
+        NVODMACCELEROMETER_PRINTF((
+            "NvOdm Accelerometer : NvOdmGpioInterruptRegister Error \n"));
+        NvOdmGpioClose(hDevice->hGpioINT);
+        NvOdmOsSemaphoreDestroy(hDevice->SemaphoreForINT);
+        return NV_FALSE;
+    }
+    return NV_TRUE;
+}
+
+static NvBool
+WriteReg(
+    NvOdmAccelHandle hDevice,
+    NvU8 RegAddr,
+    NvU8* value,
+    NvU32 len)
+{
+    NvOdmI2cTransactionInfo TransactionInfo;
+
+    if ( (NULL == hDevice) || (NULL == value) ||
+         (len > I2C_ACCELRATOR_PACKET_SIZE-1 ) )
+    {
+        NVODMACCELEROMETER_PRINTF((
+            "NvOdmI2c Set Regs Failed, max size is %d bytes\n",
+            I2C_ACCELRATOR_PACKET_SIZE-1));
+        return NV_FALSE;
+    }
+
+    s_WriteBuffer[0] = RegAddr;
+    NvOdmOsMemcpy(&s_WriteBuffer[1], value, len);
+
+    TransactionInfo.Address = hDevice->nDevAddr;
+    TransactionInfo.Buf = s_WriteBuffer;
+    TransactionInfo.Flags = NVODM_I2C_IS_WRITE;
+    TransactionInfo.NumBytes = len+1;
+
+    // Write the accelerator RegAddr (from where data is to be read).
+    if (NvOdmI2cTransaction(hDevice->hOdmI2C, &TransactionInfo, 1, 400,
+            I2C_ACCELRATOR_TRANSACTION_TIMEOUT) != NvOdmI2cStatus_Success)
+        return NV_FALSE;
+
+    return NV_TRUE;
+}
+
+static NvBool
+ReadReg(
+    NvOdmAccelHandle hDevice,
+    NvU8 RegAddr,
+    NvU8* value,
+    NvU32 len)
+{
+    NvOdmI2cTransactionInfo TransactionInfo;
+
+    if ( (NULL == hDevice) || (NULL == value) ||
+         (len > I2C_ACCELRATOR_PACKET_SIZE-1 ) )
+    {
+        NVODMACCELEROMETER_PRINTF((
+            "NvOdmI2c Get Regs Failed, max size is %d bytes\n",
+            I2C_ACCELRATOR_PACKET_SIZE-1));
+        return NV_FALSE;
+    }
+
+    s_WriteBuffer[0] = RegAddr;
+    TransactionInfo.Address = hDevice->nDevAddr;
+    TransactionInfo.Buf = s_WriteBuffer;
+    TransactionInfo.Flags = NVODM_I2C_IS_WRITE;
+    TransactionInfo.NumBytes = 1;
+
+    // Write the accelerometor RegAddr (from where data is to be read).
+    if (NvOdmI2cTransaction(hDevice->hOdmI2C, &TransactionInfo, 1, 400,
+            I2C_ACCELRATOR_TRANSACTION_TIMEOUT) != NvOdmI2cStatus_Success)
+        return NV_FALSE;
+
+    s_ReadBuffer[0] = 0;
+    TransactionInfo.Address = (hDevice->nDevAddr| 0x1);
+    TransactionInfo.Buf = s_ReadBuffer;
+    TransactionInfo.Flags = 0;
+    TransactionInfo.NumBytes = len;
+
+    //Read the data from the eeprom at the specified RegAddr
+    if (NvOdmI2cTransaction(hDevice->hOdmI2C, &TransactionInfo, 1, 400,
+            I2C_ACCELRATOR_TRANSACTION_TIMEOUT) != NvOdmI2cStatus_Success)
+        return NV_FALSE;
+
+    NvOdmOsMemcpy(value, &s_ReadBuffer[0], len);
+    return NV_TRUE;
+}
+
+static NvBool BMA150_Init(NvOdmAccelHandle hAccel)
+{
+    NvU8 TestVal;
+
+    ReadReg(hAccel, CHIP_ID_REG, &TestVal, 1);
+    if (TestVal != BMA150_CHIP_ID)
+    {
+        NVODMACCELEROMETER_PRINTF(("Unknown BMA150 ID = 0x%x\n", TestVal));
+        goto error;
+    }
+    NVODMACCELEROMETER_PRINTF(("BMA150 ID is 0x%x\n", TestVal));
+
+    // Init Hw
+    if (!ReadReg(hAccel, RANGE_BWIDTH_REG, &TestVal, 1))
+        goto error;
+    TestVal &= 0xE0;
+    TestVal |= 0x04; //Set bandwidth to 375hz
+    if (!WriteReg(hAccel, RANGE_BWIDTH_REG, &TestVal, 1))
+        goto error;
+
+    if (!ReadReg(hAccel, SMB150_CONF2_REG, &TestVal, 1))
+        goto error;
+    // Enable Advanced interrupt(6), latch int(4)
+    TestVal |= (0 << 3) | (1 << 6) | (1 << 4);
+    if (!WriteReg(hAccel, SMB150_CONF2_REG, &TestVal, 1))
+        goto error;
+    // Init Hw end
+    // Set mode
+    if (!ReadReg(hAccel, SMB150_CTRL_REG, &TestVal, 1))
+        goto error;
+    TestVal &= 0xFE;
+    if (!WriteReg(hAccel, SMB150_CTRL_REG, &TestVal, 1))
+        goto error;
+    // Set mode end
+
+    // Set motion thres
+    if (!ReadReg(hAccel, MOTION_THRS_REG, &TestVal, 1))
+        goto error;
+    TestVal = 0x0A;
+    if (!WriteReg(hAccel, MOTION_THRS_REG, &TestVal, 1))
+        goto error;
+    // Set motion thres end
+
+    // Set any motion int
+    if (!ReadReg(hAccel, SMB150_CONF1_REG, &TestVal, 1))
+        goto error;
+    TestVal &= 0xFC;
+    TestVal |= (1 << 6) | (1 << 1) | (1 << 0);
+    if (!WriteReg(hAccel, SMB150_CONF1_REG, &TestVal, 1))
+        goto error;
+    // Set any motion int end
+    NVODMACCELEROMETER_PRINTF(("\n BMA150_Init passed"));
+    return NV_TRUE;
+error:
+    NVODMACCELEROMETER_PRINTF(("\n BMA150_Init failed"));
+    return NV_FALSE;
+}
+
+static NvBool
+BMA150_ReadXYZ(
+    NvOdmAccelHandle hDevice,
+    NvS32* X,
+    NvS32* Y,
+    NvS32* Z)
+{
+    NvU8 Data[6];
+    NvBool NewData = 0;
+
+    if (!ReadReg(hDevice, X_AXIS_LSB_REG, &Data[0], 6))
+        return NV_FALSE;
+    NewData = ( (Data[0] & 0x1) || (Data[2] & 0x1) || (Data[4] & 0x1) ) ? 1 : 0;
+
+    *X = ((Data[1] << 2) | (Data[0] >> 6));
+    *Y = ((Data[3] << 2) | (Data[2] >> 6));
+    *Z = ((Data[5] << 2) | (Data[4] >> 6));
+
+    // Preserve sign bits.
+    *X = *X << ((sizeof(*X)*8) - 10);
+    *X = *X >> ((sizeof(*X)*8) - 10);
+    *Y = *Y << ((sizeof(*Y)*8) - 10);
+    *Y = *Y >> ((sizeof(*Y)*8) - 10);
+    *Z = *Z << ((sizeof(*Z)*8) - 10);
+    *Z = *Z >> ((sizeof(*Z)*8) - 10);
+    return NewData;
+}
+
+static void BMA150_ResetInterrupt(NvOdmAccelHandle hDevice)
+{
+    NvU8 Data = (1 << 6);
+
+    WriteReg(hDevice, SMB150_CTRL_REG, &Data, 1);
+}
+
+NvBool NvOdmAccelOpen(NvOdmAccelHandle* hDevice)
+{
+    NvU32 i;
+    NvOdmAccelHandle  hAccel;
+    NvOdmIoModule IoModule = NvOdmIoModule_I2c;
+    const NvOdmPeripheralConnectivity *pConnectivity;
+    NvBool FoundGpio = NV_FALSE, FoundI2cModule = NV_FALSE;
+
+    hAccel = NvOdmOsAlloc(sizeof(NvOdmAccel));
+    if (hAccel == NULL)
+    {
+        NVODMACCELEROMETER_PRINTF(("Error Allocating NvOdmAccel. \n"));
+        return NV_FALSE;
+    }
+    NvOdmOsMemset(hAccel, 0, sizeof(NvOdmAccel));
+    hAccel->nBusType = NV_ACCELEROMETER_BUS_I2C;
+
+    // Info of accelerometer with current setting.
+    hAccel->Caption.MaxForceInGs = 2000;
+    hAccel->Caption.MaxTapTimeDeltaInUs = 255;
+    hAccel->Caption.NumMotionThresholds = 1;
+    hAccel->Caption.SupportsFreefallInt = 0;
+    hAccel->Caption.MaxSampleRate = 100;
+    hAccel->Caption.MinSampleRate = 3;
+    hAccel->PowerState = NvOdmAccelPower_Fullrun;
+    hAccel->AxisXMapping = NvOdmAccelAxis_Y;
+    hAccel->AxisXDirection = -1;
+    hAccel->AxisYMapping = NvOdmAccelAxis_X;
+    hAccel->AxisYDirection = 1;
+    hAccel->AxisZMapping = NvOdmAccelAxis_Z;
+    hAccel->AxisZDirection = -1;
+
+    hAccel->hPmu = NvOdmServicesPmuOpen();
+    if (!hAccel->hPmu)
+    {
+        NVODMACCELEROMETER_PRINTF(("NvOdmServicesPmuOpen Error \n"));
+        goto error;
+    }
+
+    pConnectivity = (NvOdmPeripheralConnectivity*)NvOdmPeripheralGetGuid(
+                        NV_ODM_GUID('b','m','a','1','5','0','a','c'));
+    if (!pConnectivity)
+    {
+        NvOdmOsDebugPrintf(("NvOdmPeripheralGetGuid doesn't detect\
+            BMA150 accelerometer device\n"));
+        goto error;
+    }
+
+    if (pConnectivity->Class != NvOdmPeripheralClass_Other)
+        goto error;
+
+    for( i = 0; i < pConnectivity->NumAddress; i++)
+    {
+        switch(pConnectivity->AddressList[i].Interface)
+        {
+            case NvOdmIoModule_I2c:
+            case NvOdmIoModule_I2c_Pmu:
+                hAccel->I2CChannelId = pConnectivity->AddressList[i].Instance;
+                hAccel->nDevAddr = (NvU8)pConnectivity->AddressList[i].Address;
+                FoundI2cModule = NV_TRUE;
+                IoModule = pConnectivity->AddressList[i].Interface;
+                break;
+            case NvOdmIoModule_Gpio:
+                hAccel->GPIOPortINT = pConnectivity->AddressList[i].Instance;
+                hAccel->GPIOPinINT = pConnectivity->AddressList[i].Address;
+                FoundGpio = NV_TRUE;
+                break;
+            case NvOdmIoModule_Vdd:
+                hAccel->VddId = pConnectivity->AddressList[i].Address;
+                // Power on accelerometer according to Vddid
+                SetPowerRail(hAccel->hPmu, hAccel->VddId, NV_TRUE);
+                break;
+            default:
+                break;
+        }
+    }
+
+    if (!FoundGpio || !FoundI2cModule)
+    {
+        NVODMACCELEROMETER_PRINTF(("Accelerometer : didn't find any periperal\
+            in discovery query for touch device Error \n"));
+        goto error;
+    }
+
+    // Open I2C handle.
+    hAccel->hOdmI2C = NvOdmI2cOpen(IoModule, hAccel->I2CChannelId);
+    if (!hAccel->hOdmI2C)
+        goto error;
+
+    hAccel->RegsRead  = ReadReg;
+    hAccel->RegsWrite = WriteReg;
+
+    if (!BMA150_Init(hAccel))
+        goto error;
+    if (!ConnectSemaphore(hAccel))
+        goto error;
+
+    *hDevice = hAccel;
+    return NV_TRUE;
+    error:
+        NVODMACCELEROMETER_PRINTF(("Error during BMA150 NvOdmAccelOpen\n"));
+        // Release all of resources requested.
+        if (hAccel)
+        {
+            SetPowerRail(hAccel->hPmu, hAccel->VddId, NV_FALSE);
+            NvOdmServicesPmuClose(hAccel->hPmu);
+            hAccel->hPmu = NULL;
+            NvOdmI2cClose(hAccel->hOdmI2C);
+            hAccel->hOdmI2C = NULL;
+            NvOdmOsFree(hAccel);
+            *hDevice = NULL;
+        }
+        return NV_FALSE;
+}
+
+void NvOdmAccelClose(NvOdmAccelHandle hDevice)
+{
+    if (hDevice)
+    {
+        if (hDevice->SemaphoreForINT && hDevice->hGpioINT &&
+            hDevice->hPinINT && hDevice->hGpioInterrupt)
+        {
+            NvOdmGpioInterruptUnregister(hDevice->hGpioINT,
+                hDevice->hPinINT, hDevice->hGpioInterrupt);
+            NvOdmOsSemaphoreDestroy(hDevice->SemaphoreForINT);
+            NvOdmGpioReleasePinHandle(hDevice->hGpioINT, hDevice->hPinINT);
+            NvOdmGpioClose(hDevice->hGpioINT);
+        }
+        NvOdmI2cClose(hDevice->hOdmI2C);
+
+        // Power off accelermeter
+        SetPowerRail(hDevice->hPmu, hDevice->VddId, NV_FALSE);
+        if (hDevice->hPmu)
+        {
+            //NvAccelerometerSetPowerOn(0);
+            NvOdmServicesPmuClose(hDevice->hPmu);
+        }
+    }
+}
+
+NvBool
+NvOdmAccelSetIntForceThreshold(
+    NvOdmAccelHandle  hDevice,
+    NvOdmAccelIntType IntType,
+    NvU32             IntNum,
+    NvU32             Threshold)
+{
+    return NV_TRUE;
+}
+
+NvBool
+NvOdmAccelSetIntTimeThreshold(
+    NvOdmAccelHandle  hDevice,
+    NvOdmAccelIntType IntType,
+    NvU32             IntNum,
+    NvU32             Threshold)
+{
+    return NV_TRUE;
+}
+
+NvBool
+NvOdmAccelSetIntEnable(
+    NvOdmAccelHandle  hDevice,
+    NvOdmAccelIntType  IntType,
+    NvOdmAccelAxisType IntAxis,
+    NvU32              IntNum,
+    NvBool             Toggle)
+{
+    return NV_TRUE;
+}
+
+void
+NvOdmAccelWaitInt(
+    NvOdmAccelHandle    hDevice,
+    NvOdmAccelIntType  *IntType,
+    NvOdmAccelAxisType *IntMotionAxis,
+    NvOdmAccelAxisType *IntTapAxis)
+{
+    NV_ASSERT(hDevice);
+    NV_ASSERT(IntType);
+    NV_ASSERT(IntMotionAxis);
+    NV_ASSERT(IntTapAxis);
+
+    if ((g_WaitCounter > 0) || ENABLE_XYZ_POLLING)
+    {
+        NvOdmOsSemaphoreWaitTimeout( hDevice->SemaphoreForINT, 300);
+        g_WaitCounter--;
+    }
+    else
+        NvOdmOsSemaphoreWait( hDevice->SemaphoreForINT);
+}
+
+void NvOdmAccelSignal(NvOdmAccelHandle hDevice)
+{
+    NvOdmOsSemaphoreSignal(hDevice->SemaphoreForINT);
+}
+
+NvBool
+NvOdmAccelGetAcceleration(
+    NvOdmAccelHandle hDevice,
+    NvS32           *AccelX,
+    NvS32           *AccelY,
+    NvS32           *AccelZ)
+{
+    NvS32 data;
+    NvBool NewData = 0;
+    NvS32 TempAccelX = 0;
+    NvS32 TempAccelY = 0;
+    NvS32 TempAccelZ = 0;
+
+    NV_ASSERT(NULL != hDevice);
+    NV_ASSERT(NULL != AccelX);
+    NV_ASSERT(NULL != AccelY);
+    NV_ASSERT(NULL != AccelZ);
+    NewData = BMA150_ReadXYZ(hDevice, &TempAccelX, &TempAccelY, &TempAccelZ);
+
+    data = (((NvS32)(hDevice->Caption.MaxForceInGs))*TempAccelX+(NvS32)(NV_BMA150_MAX_FORCE_IN_REG/2))/
+             (NvS32)NV_BMA150_MAX_FORCE_IN_REG;
+    switch(hDevice->AxisXMapping)
+    {
+        case NvOdmAccelAxis_X:
+            *AccelX = data*hDevice->AxisXDirection;
+            break;
+        case NvOdmAccelAxis_Y:
+            *AccelY = data*hDevice->AxisYDirection;
+            break;
+        case NvOdmAccelAxis_Z:
+            *AccelZ = data*hDevice->AxisZDirection;
+            break;
+        default:
+            return NV_FALSE;
+    }
+
+    data = (((NvS32)(hDevice->Caption.MaxForceInGs))*TempAccelY+(NvS32)(NV_BMA150_MAX_FORCE_IN_REG/2))/
+             (NvS32)NV_BMA150_MAX_FORCE_IN_REG;
+    switch(hDevice->AxisYMapping)
+    {
+        case NvOdmAccelAxis_X:
+            *AccelX = data*hDevice->AxisXDirection;
+            break;
+        case NvOdmAccelAxis_Y:
+            *AccelY = data*hDevice->AxisYDirection;
+            break;
+        case NvOdmAccelAxis_Z:
+            *AccelZ = data*hDevice->AxisZDirection;
+            break;
+        default:
+            return NV_FALSE;
+    }
+
+    data = (((NvS32)(hDevice->Caption.MaxForceInGs))*TempAccelZ+(NvS32)(NV_BMA150_MAX_FORCE_IN_REG/2))/
+             (NvS32)NV_BMA150_MAX_FORCE_IN_REG;
+    switch(hDevice->AxisZMapping)
+    {
+        case NvOdmAccelAxis_X:
+            *AccelX = data*hDevice->AxisXDirection;
+            break;
+        case NvOdmAccelAxis_Y:
+            *AccelY = data*hDevice->AxisYDirection;
+            break;
+        case NvOdmAccelAxis_Z:
+            *AccelZ = data*hDevice->AxisZDirection;
+            break;
+        default:
+            return NV_FALSE;
+    }
+
+    NVODMACCELEROMETER_PRINTF(("\naccel output, x=%d,y=%d,z=%d, NewData=%d",
+        *AccelX, *AccelY, *AccelZ, NewData));
+    return NewData;
+}
+
+NvOdmAccelerometerCaps NvOdmAccelGetCaps(NvOdmAccelHandle hDevice)
+{
+    NV_ASSERT(NULL != hDevice);
+    return hDevice->Caption;
+}
+
+NvBool NvOdmAccelSetSampleRate(NvOdmAccelHandle hDevice, NvU32 SampleRate)
+{
+    return NV_TRUE;
+}
+
+NvBool NvOdmAccelGetSampleRate(NvOdmAccelHandle hDevice, NvU32 *pSampleRate)
+{
+    return NV_TRUE;
+}
+
+NvBool
+NvOdmAccelSetPowerState(
+    NvOdmAccelHandle hDevice,
+    NvOdmAccelPowerType PowerState)
+{
+    return NV_TRUE;
+}
+
diff --git a/arch/arm/mach-tegra/odm_kit/platform/accelerometer/nvodm_accelerometer_bma150.h b/arch/arm/mach-tegra/odm_kit/platform/accelerometer/nvodm_accelerometer_bma150.h
new file mode 100644
index 000000000000..1b8efb12ad0c
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/platform/accelerometer/nvodm_accelerometer_bma150.h
@@ -0,0 +1,212 @@
+/*
+ * Copyright (c) 2010 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/*  NVIDIA Tegra ODM Kit Sample Accelerometer Adaptation of the
+ *  WinCE Accelerometer Driver
+ */
+
+#ifndef INCLUDED_NVODM_ACCELEROMETER_BMA150_H
+#define INCLUDED_NVODM_ACCELEROMETER_BMA150_H
+
+#if defined(_cplusplus)
+extern "C"
+{
+#endif
+
+#include "nvodm_services.h"
+#include "nvodm_accelerometer.h"
+
+/* BMA150 register address */
+#define CHIP_ID_REG             0x00
+#define VERSION_REG             0x01
+#define X_AXIS_LSB_REG          0x02
+#define X_AXIS_MSB_REG          0x03
+#define Y_AXIS_LSB_REG          0x04
+#define Y_AXIS_MSB_REG          0x05
+#define Z_AXIS_LSB_REG          0x06
+#define Z_AXIS_MSB_REG          0x07
+#define TEMP_RD_REG             0x08
+#define SMB150_STATUS_REG       0x09
+#define SMB150_CTRL_REG         0x0a
+#define SMB150_CONF1_REG        0x0b
+#define LG_THRESHOLD_REG        0x0c
+#define LG_DURATION_REG         0x0d
+#define HG_THRESHOLD_REG        0x0e
+#define HG_DURATION_REG         0x0f
+#define MOTION_THRS_REG         0x10
+#define HYSTERESIS_REG          0x11
+#define CUSTOMER1_REG           0x12
+#define CUSTOMER2_REG           0x13
+#define RANGE_BWIDTH_REG        0x14
+#define SMB150_CONF2_REG        0x15
+
+#define OFFS_GAIN_X_REG         0x16
+#define OFFS_GAIN_Y_REG         0x17
+#define OFFS_GAIN_Z_REG         0x18
+#define OFFS_GAIN_T_REG         0x19
+#define OFFSET_X_REG            0x1a
+#define OFFSET_Y_REG            0x1b
+#define OFFSET_Z_REG            0x1c
+#define OFFSET_T_REG            0x1d
+
+/* range and bandwidth */
+#define BMA_RANGE_2G            0
+#define BMA_RANGE_4G            1
+#define BMA_RANGE_8G            2
+
+#define BMA_BW_25HZ             0
+#define BMA_BW_50HZ             1
+#define BMA_BW_100HZ            2
+#define BMA_BW_190HZ            3
+#define BMA_BW_375HZ            4
+#define BMA_BW_750HZ            5
+#define BMA_BW_1500HZ           6
+
+/* mode settings */
+#define BMA_MODE_NORMAL         0
+#define BMA_MODE_SLEEP          1
+
+#define BMA150_CHIP_ID      0x02        // RO - device identification
+/*
+ * Defines the threshold source for the accelerometer.
+ */
+typedef enum
+{
+    /// Indicates the accelerometer generated interrupt by exceeding the x threshold.
+    NvOdmAccelerometerThresholdSource_X = 0,
+
+    /// Indicates the accelerometer generated interrupt by exceeding the y threshold.
+    NvOdmAccelerometerThresholdSource_Y,
+
+    /// Indicates the accelerometer generated interrupt by exceeding the z threshold.
+    NvOdmAccelerometerThresholdSource_Z,
+
+    NvOdmAccelerometerThresholdSource_Force32 = 0x7FFFFFFF
+} NvOdmAccelerometerThresholdSource;
+
+// Timeout for I2C transaction.
+enum { I2C_ACCELRATOR_TRANSACTION_TIMEOUT = 1000 };
+// Maximum number of packetsize supported by the I2C controller.
+enum { I2C_ACCELRATOR_PACKET_SIZE = 8};
+static NvU8 s_ReadBuffer[I2C_ACCELRATOR_PACKET_SIZE];
+static NvU8 s_WriteBuffer[I2C_ACCELRATOR_PACKET_SIZE];
+
+#define INT_EVENT_TIMEOUT 100
+#define NV_ACCELEROMETER_BUS_I2C 0
+#define NV_ACCELEROMETER_BUS_SPI_3 1
+#define NV_ACCELEROMETER_BUS_SPI_4 2
+
+/*
+ * Defines the way to read accelerometer registers.
+ */
+typedef NvBool
+(*AccelerometerRegsRead)(
+    NvOdmAccelHandle hDevice,
+    NvU8 nRegOffset,
+    NvU8* nData,
+    NvU32 nLen);
+/*
+ * Defines the way to write accelerometer registers.
+ */
+typedef NvBool
+(*AccelerometerRegsWrite)(
+    NvOdmAccelHandle hDevice,
+    NvU8 nRegOffset,
+    NvU8* nData,
+    NvU32 nLen);
+/*
+ * Holds register address and value pairs.
+ */
+typedef struct NvDevCtrlRegRec {
+   /// Holds the register offset.
+   NvU8 RegAddr;
+   /// Holds the value programmed into the upper address.
+   NvU8 RegValue;
+} NvDevCtrlReg;
+/*
+ * Max accelerometer registers number.
+ */
+#define ACCELEROMETER_CONTROL_REGS_MAX_LENGHT 100
+/*
+ * Max accelerometer callback functions number.
+ */
+#define ACCELEROMETER_CALLBACK_ARRAY_LENGTH   5
+
+typedef struct NvOdmAccelRec
+{
+    // Specifies use I2C or SPI to configure accelerometer registers.
+    NvU8 nBusType;
+    // Specifies accelerometer device address, for example, I2C write address.
+    NvU8 nDevAddr;
+    // Specifies the initial value that make accelerometer work,
+    // ACCELEROMETER_CONTROL_REGS_MAX_LENGHT is always 100.
+    NvDevCtrlReg CtrlRegsList[ACCELEROMETER_CONTROL_REGS_MAX_LENGHT];
+    // Specifies the initial CtrlRegsList length.
+    NvU8 nLength;
+    // Specifies accelerometer chip ID.
+    NvU8 nChipID;
+    // Specifies the way to get accelerometer register information.
+    AccelerometerRegsRead RegsRead;
+    // Specifies the way to set accelerometer register information.
+    AccelerometerRegsWrite RegsWrite;
+    // Specifies I2C handle from the system.
+    NvOdmServicesI2cHandle  hOdmI2C;
+    // Interrupt pin to ap15.
+    NvOdmServicesGpioHandle hGpioINT;
+    NvOdmGpioPinHandle      hPinINT;
+    NvU32 GPIOPortINT;
+    NvU32 GPIOPinINT;
+    NvOdmOsSemaphoreHandle SemaphoreForINT;
+    NvOdmServicesGpioIntrHandle hGpioInterrupt;
+    NvOdmAccelIntType Data;
+    NvOdmServicesPmuHandle hPmu;
+    NvU32 VddId;
+    NvU32 I2CChannelId;
+    NvOdmAccelerometerCaps Caption;
+    NvOdmAccelPowerType PowerState;
+    // In real case, when the board put in frontispiece, the value from z axis
+    // should be g, but due to physical connect on different board, the axis
+    // should be remapped to the correct one.
+    NvOdmAccelAxisType AxisXMapping;
+    // If the physical direct is the same with our expection, the value
+    // should be set to 1, or else the value should be -1.
+    NvS32              AxisXDirection;
+    NvOdmAccelAxisType AxisYMapping;
+    NvS32              AxisYDirection;
+    NvOdmAccelAxisType AxisZMapping;
+    NvS32              AxisZDirection;
+} NvOdmAccel;
+
+#if defined(__cplusplus)
+}
+#endif
+#endif
diff --git a/arch/arm/mach-tegra/odm_kit/platform/accelerometer/nvodm_accelerometer_stub.c b/arch/arm/mach-tegra/odm_kit/platform/accelerometer/nvodm_accelerometer_stub.c
new file mode 100644
index 000000000000..b10e15f84754
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/platform/accelerometer/nvodm_accelerometer_stub.c
@@ -0,0 +1,150 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/**
+ * @file          NvAccelerometer.c
+ * @brief         <b>Device Driver for Accelerometer</b>
+ *
+ * @Description : Implementation of the WinCE Accelerometer driver
+ */
+
+#include "nvodm_accelerometer.h"
+
+
+NvBool
+NvOdmAccelOpen(NvOdmAccelHandle* hDevice)
+{
+    *hDevice = NULL;
+    return NV_FALSE;
+}
+
+
+void
+NvOdmAccelClose(NvOdmAccelHandle hDevice)
+{
+}
+
+
+/**
+ * After setting the force threshold, we should remove all of interrupt flag
+ * Which may be left from last threshold
+ */
+NvBool
+NvOdmAccelSetIntForceThreshold(NvOdmAccelHandle  hDevice,
+                               NvOdmAccelIntType IntType,
+                               NvU32             IntNum,
+                               NvU32             Threshold)
+{
+    return NV_FALSE;
+}
+
+/**
+ * After setting the time threshold, we should remove all of interrupt flag
+ * Which may be left from last threshold
+ */
+NvBool
+NvOdmAccelSetIntTimeThreshold(NvOdmAccelHandle  hDevice,
+                              NvOdmAccelIntType IntType,
+                              NvU32             IntNum,
+                              NvU32             Threshold)
+{
+    return NV_FALSE;
+}
+
+
+/**
+ * After enable/disable threshold, we should remove all of interrupt flag
+ * Which may be left from last threshold
+ */
+NvBool
+NvOdmAccelSetIntEnable(NvOdmAccelHandle   hDevice,
+                       NvOdmAccelIntType  IntType,
+                       NvOdmAccelAxisType IntAxis,
+                       NvU32              IntNum,
+                       NvBool             Toggle)
+{
+    return NV_FALSE;
+}
+
+
+void
+NvOdmAccelWaitInt(NvOdmAccelHandle    hDevice,
+                  NvOdmAccelIntType  *IntType,
+                  NvOdmAccelAxisType *IntMotionAxis,
+                  NvOdmAccelAxisType *IntTapAxis)
+{
+}
+
+
+void NvOdmAccelSignal(NvOdmAccelHandle hDevice)
+{
+}
+
+NvBool
+NvOdmAccelGetAcceleration(NvOdmAccelHandle hDevice,
+                          NvS32           *AccelX,
+                          NvS32           *AccelY,
+                          NvS32           *AccelZ)
+{
+    return NV_FALSE;
+}
+
+
+NvOdmAccelerometerCaps
+NvOdmAccelGetCaps(NvOdmAccelHandle hDevice)
+{
+    NvOdmAccelerometerCaps caps;
+    NvOdmOsMemset(&caps, 0, sizeof(NvOdmAccelerometerCaps));
+
+    return caps;
+}
+
+
+NvBool
+NvOdmAccelSetSampleRate(NvOdmAccelHandle hDevice, NvU32 SampleRate)
+{
+    return NV_FALSE;
+}
+
+
+NvBool
+NvOdmAccelGetSampleRate(NvOdmAccelHandle hDevice, NvU32 *pSampleRate)
+{
+    return NV_FALSE;
+}
+
+NvBool
+NvOdmAccelSetPowerState(NvOdmAccelHandle hDevice, NvOdmAccelPowerType PowerState)
+{
+    return NV_FALSE;
+}
+
diff --git a/arch/arm/mach-tegra/odm_kit/platform/battery/Makefile b/arch/arm/mach-tegra/odm_kit/platform/battery/Makefile
new file mode 100644
index 000000000000..9c1a4b43b4ab
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/platform/battery/Makefile
@@ -0,0 +1,11 @@
+ccflags-y += -DNV_IS_AVP=0
+ccflags-y += -DNV_OAL=0
+ccflags-y += -DNV_USE_FUSE_CLOCK_ENABLE=0
+ifeq ($(CONFIG_MACH_TEGRA_GENERIC_DEBUG),y)
+ccflags-y += -DNV_DEBUG=1
+else
+ccflags-y += -DNV_DEBUG=0
+endif
+
+obj-$(CONFIG_TEGRA_ODM_HARMONY)		+= nvodm_battery.o
+obj-$(CONFIG_TEGRA_ODM_WHISTLER)	+= nvodm_battery_stub.o
diff --git a/arch/arm/mach-tegra/odm_kit/platform/battery/nvodm_battery.c b/arch/arm/mach-tegra/odm_kit/platform/battery/nvodm_battery.c
new file mode 100644
index 000000000000..9a3d775f5308
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/platform/battery/nvodm_battery.c
@@ -0,0 +1,1896 @@
+/*
+ * Copyright (c) 2009-2010 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include "nvodm_query_discovery.h"
+#include "nvodm_services.h"
+#include "nvodm_battery_int.h"
+#include "nvodm_battery.h"
+#include "nvec.h"
+
+NvBool NvOdmBatteryPrivGetSlotStatusAndCapacityGuage(
+       NvOdmBatteryDevice *pBattContext,
+       NvOdmBatteryInstance BatteryInst,
+       NvU8 *BatterySlotStatus,
+       NvU8 *BatteryCapacityGuage);
+
+NvBool NvOdmBatteryPrivGetLifeTime(
+       NvOdmBatteryDevice *pBattContext,
+       NvOdmBatteryInstance BatteryInst,
+       NvU32 *BatteryLifeTime);
+
+NvBool NvOdmPrivBattGetBatteryVoltage(
+       NvOdmBatteryDevice *pBattContext,
+       NvOdmBatteryInstance BatteryInst,
+       NvU32 *BatteryVoltage);
+
+NvBool NvOdmBatteryPrivGetCurrent(
+       NvOdmBatteryDeviceHandle hDevice,
+       NvOdmBatteryInstance BatteryInst,
+       NvS32 *pCurrent);
+
+NvBool NvOdmBatteryPrivGetAverageCurrent(
+       NvOdmBatteryDeviceHandle hDevice,
+       NvOdmBatteryInstance BatteryInst,
+       NvS32 *pAverageCurrent);
+
+NvBool NvOdmBatteryPrivGetAverageTimeInterval(
+       NvOdmBatteryDeviceHandle hDevice,
+       NvOdmBatteryInstance BatteryInst,
+       NvU32 *pAverageTimeInterval);
+
+NvBool NvOdmBatteryPrivGetTemperature(
+       NvOdmBatteryDeviceHandle hDevice,
+       NvOdmBatteryInstance BatteryInst,
+       NvU32 *pBatteryTemp);
+
+NvBool NvOdmBatteryPrivGetRemainingCapacity(
+       NvOdmBatteryDeviceHandle hDevice,
+       NvOdmBatteryInstance BatteryInst,
+       NvU32 *pRemCapacity);
+
+NvBool NvOdmBatteryPrivGetLastFullChargeCapacity(
+       NvOdmBatteryDeviceHandle hDevice,
+       NvOdmBatteryInstance BatteryInst,
+       NvU32 *pLastFullChargeCapacity);
+
+NvBool NvOdmBatteryPrivGetCriticalCapacity(
+       NvOdmBatteryDeviceHandle hDevice,
+       NvOdmBatteryInstance BatteryInst,
+       NvU32 *pCriticalCapacity);
+
+NvBool NvOdmBatterySetRemCapacityAlarm(
+       NvOdmBatteryDeviceHandle hDevice,
+       NvOdmBatteryInstance BatteryInst,
+       NvU16 RemCapAlarm);
+
+#if BATTERY_EXTRA_INFO
+NvBool NvOdmBatteryGetRemCapacityAlarm(
+       NvOdmBatteryDeviceHandle hDevice,
+       NvOdmBatteryInstance BatteryInst,
+       NvU16 *RemCapAlarm);
+
+NvBool NvOdmBatterySetConfiguration(
+       NvOdmBatteryDeviceHandle hDevice,
+       NvOdmBatteryInstance BatteryInst,
+       NvU8 Configuration);
+
+NvBool NvOdmBatteryGetConfiguration(
+       NvOdmBatteryDeviceHandle hDevice,
+       NvOdmBatteryInstance BatteryInst,
+       NvU8 *Configuration);
+#endif
+
+#if NVODM_LOWBATTERY_GPIO_INT
+/*
+ * GPIO interrupt handle for battery events
+ */
+static void
+NvOdmBatteryGpioInterruptHandler(void *args)
+{
+    NvOdmBatteryDevice *pBattContext = args;
+
+    NVODMBATTERY_PRINTF(("NvOdmBatteryGpioInterruptHandler:\n"));
+
+    if (pBattContext)
+    {
+        pBattContext->BatteryEvent = NvOdmBatteryEventType_RemainingCapacityAlarm;
+
+        if (pBattContext->hClientBattEventSem)
+            NvOdmOsSemaphoreSignal(pBattContext->hClientBattEventSem);
+    }
+
+    NvRmGpioInterruptDone(pBattContext->GpioIntrHandle);
+}
+#endif
+
+/*
+ * Gets the EC Firmware version number
+ */
+static NvError NvOdmBatteryPrivEcGetFirmwareVersion(
+               NvOdmBatteryDevice *pBattContext,
+               NvS32 *MajorVersion,
+               NvS32 *MinorVersion)
+{
+    NvEcControlGetFirmwareVersionResponsePayload FirmwareVersion;
+    NvError      RetVal = NvSuccess;
+    NvEcRequest  EcRequest = {0};
+    NvEcResponse EcResponse = {0};
+    NvS32        Version = 0;
+
+    EcRequest.PacketType = NvEcPacketType_Request;
+    EcRequest.RequestType = NvEcRequestResponseType_Control;
+    EcRequest.RequestSubtype = (NvEcRequestResponseSubtype)
+                          NvEcControlSubtype_GetFirmwareVersion;
+    EcRequest.NumPayloadBytes = 0;
+    RetVal = NvEcSendRequest(pBattContext->hEc, &EcRequest, &EcResponse,
+                            sizeof(EcRequest), sizeof(EcResponse));
+    if (RetVal != NvSuccess)
+        return RetVal;
+
+    if (EcResponse.Status != NvEcStatus_Success)
+        return NvError_BadValue;
+
+    NvOdmOsMemcpy(&FirmwareVersion, EcResponse.Payload,
+                EcResponse.NumPayloadBytes);
+
+    Version = (FirmwareVersion.VersionMajor[1] << 24) |
+              (FirmwareVersion.VersionMajor[0] << 16) |
+              (FirmwareVersion.VersionMinor[1] << 8) |
+              (FirmwareVersion.VersionMinor[0] << 0);
+
+    *MajorVersion = Version & 0xFF00;
+    *MinorVersion = Version & 0xFF;
+    return NvSuccess;
+}
+
+static void NvOdmBatteryEventHandler(void *args)
+{
+    NvOdmBatteryDevice *pBattContext = args;
+    NvError NvStatus = NvError_Success;
+    NvEcEvent EcEvent = {0};
+    NvU8      BattEvent = 0, ChargingState = 0;
+
+    for (;;)
+    {
+        NvOdmOsSemaphoreWait(pBattContext->hBattEventSem);
+
+        if (pBattContext->ExitThread == NV_TRUE)
+            break;
+
+        NVODMBATTERY_PRINTF(("NvOdmBatteryEventHandler:hBattEventSem signaled\n"));
+
+        if (pBattContext->hEcEventReg)
+        {
+            NvStatus = NvEcGetEvent(pBattContext->hEcEventReg,
+                                    &EcEvent, sizeof(NvEcEvent));
+            if (NvStatus != NvError_Success)
+            {
+                NV_ASSERT(!"Could not receive EC event\n");
+                continue;
+            }
+
+            if (EcEvent.NumPayloadBytes == 0)
+            {
+                NV_ASSERT(!"Received Battery event with no data\n");
+                continue;
+            }
+
+            /* EcEvent.Payload[0] is Slot number */
+
+            /* EcEvent.Payload[1] has 4 lsb bits for battery events */
+            BattEvent = EcEvent.Payload[1] & NVODM_BATTERY_EVENT_MASK;
+
+            pBattContext->BatteryEvent = 0;
+            /* Read the Battery Slot status to set the proper event */
+            if (BattEvent & NVODM_BATTERY_PRESENT_IN_SLOT)
+                pBattContext->BatteryEvent |= NvOdmBatteryEventType_Present;
+
+            ChargingState = BattEvent >> NVODM_BATTERY_CHARGING_STATE_SHIFT;
+            ChargingState &= NVODM_BATTERY_CHARGING_STATE_MASK;
+            if (ChargingState == NVODM_BATTERY_CHARGING_STATE_IDLE)
+                pBattContext->BatteryEvent |= NvOdmBatteryEventType_Idle;
+            else if (ChargingState == NVODM_BATTERY_CHARGING_STATE_CHARGING)
+                pBattContext->BatteryEvent |= NvOdmBatteryEventType_Charging;
+            else if (ChargingState == NVODM_BATTERY_CHARGING_STATE_DISCHARGING)
+                pBattContext->BatteryEvent |= NvOdmBatteryEventType_Disharging;
+
+            ChargingState = BattEvent >> NVODM_BATTERY_REM_CAP_ALARM_SHIFT;
+            if (ChargingState == NVODM_BATTERY_REM_CAP_ALARM_IS_SET)
+                pBattContext->BatteryEvent |= NvOdmBatteryEventType_RemainingCapacityAlarm;
+
+            /* Signal the Battery Client for arrival of the valid event */
+            if ((pBattContext->hClientBattEventSem != 0) &&
+                (pBattContext->BatteryEvent != 0))
+                 NvOdmOsSemaphoreSignal(pBattContext->hClientBattEventSem);
+        }
+    }
+}
+
+/**
+ * Gets the battery event.
+ *
+ * @param hDevice A handle to the EC.
+ * @param pBatteryEvent Battery events
+ *
+ */
+void NvOdmBatteryGetEvent(
+     NvOdmBatteryDeviceHandle hDevice,
+     NvU8   *pBatteryEvent)
+{
+    NvOdmBatteryDevice *pBattContext = NULL;
+
+    NVODMBATTERY_PRINTF(("[ENTER] NvOdmBatteryGetEvent.\n"));
+
+    pBattContext = (NvOdmBatteryDevice *)hDevice;
+
+    *pBatteryEvent = pBattContext->BatteryEvent;
+}
+
+/**
+ * Sets the battery remaining capacity alarm threshold.
+ *
+ * @param hDevice [IN] A handle to the EC.
+ * @param BatteryInst [IN] The battery type.
+ * @param RemCapAlarm [IN] Capacity Units
+ */
+NvBool NvOdmBatterySetRemCapacityAlarm(
+       NvOdmBatteryDeviceHandle hDevice,
+       NvOdmBatteryInstance BatteryInst,
+       NvU16 RemCapAlarm)
+{
+#if NVEC_BATTERY_DISABLED
+    ;
+#else
+    NvError NvStatus = NvError_Success;
+    NvEcRequest EcRequest = {0};
+    NvEcResponse EcResponse = {0};
+    NvOdmBatteryDevice *pBattContext = NULL;
+
+    NVODMBATTERY_PRINTF(("[ENTER]NvOdmBatterySetRemCapacityAlarm.\n"));
+    pBattContext = (NvOdmBatteryDevice *)hDevice;
+
+    /* Fill up request structure */
+    EcRequest.PacketType = NvEcPacketType_Request;
+    EcRequest.RequestType = NvEcRequestResponseType_Battery;
+    EcRequest.RequestSubtype = NvEcBatterySubtype_SetRemainingCapacityAlarm;
+    EcRequest.NumPayloadBytes = 2;
+    EcRequest.Payload[0] = (RemCapAlarm & 0x00FF);
+    EcRequest.Payload[1] = (RemCapAlarm & 0xFF00) >> 8;
+
+    /* Request to EC */
+    NvStatus = NvEcSendRequest(pBattContext->hEc, &EcRequest, &EcResponse,
+                              sizeof(EcRequest), sizeof(EcResponse));
+    if (NvSuccess != NvStatus)
+    {
+        NVODMBATTERY_PRINTF(("NvEcSendRequest failed for NvOdmBatterySetRemCapacityAlarm\n"));
+        return NV_FALSE;
+    }
+
+    if(EcResponse.Status == NvEcStatus_Success)
+    {
+        NVODMBATTERY_PRINTF(("EcResponse.Status failed for NvOdmBatterySetRemCapacityAlarm\n"));
+        return NV_FALSE;
+    }
+
+    NVODMBATTERY_PRINTF(("[EXIT]NvOdmBatterySetRemCapacityAlarm.\n"));
+#endif /* end of NVEC_BATTERY_DISABLED */
+    return NV_TRUE;
+}
+
+#if BATTERY_EXTRA_INFO
+/**
+ * Gets the battery remaining capacity alarm threshold.
+ *
+ * @param hDevice [IN] A handle to the EC.
+ * @param BatteryInst [IN] The battery type.
+ * @param RemCapAlarm [OUT] Capacity Units
+ */
+NvBool NvOdmBatteryGetRemCapacityAlarm(
+       NvOdmBatteryDeviceHandle hDevice,
+       NvOdmBatteryInstance BatteryInst,
+       NvU16 *RemCapAlarm)
+{
+#if NVEC_BATTERY_DISABLED
+    *RemCapAlarm = 0;
+#else
+    NvError NvStatus = NvError_Success;
+    NvEcRequest EcRequest = {0};
+    NvEcResponse EcResponse = {0};
+    NvOdmBatteryDevice *pBattContext = NULL;
+
+    NVODMBATTERY_PRINTF(("[ENTER]NvOdmBatteryGetRemCapacityAlarm.\n"));
+    *RemCapAlarm = 0;
+    pBattContext = (NvOdmBatteryDevice *)hDevice;
+
+    /* Fill up request structure */
+    EcRequest.PacketType = NvEcPacketType_Request;
+    EcRequest.RequestType = NvEcRequestResponseType_Battery;
+    EcRequest.RequestSubtype = NvEcBatterySubtype_GetRemainingCapacityAlarm;
+    EcRequest.NumPayloadBytes = 0;
+    EcRequest.Payload[0] = 0;
+
+    /* Request to EC */
+    NvStatus = NvEcSendRequest(pBattContext->hEc, &EcRequest, &EcResponse,
+                              sizeof(EcRequest), sizeof(EcResponse));
+    if (NvSuccess != NvStatus)
+    {
+        NVODMBATTERY_PRINTF(("NvEcSendRequest failed for NvOdmBatteryGetRemCapacityAlarm\n"));
+        return NV_FALSE;
+    }
+
+    if(EcResponse.Status == NvEcStatus_Success)
+    {
+        *RemCapAlarm = EcResponse.Payload[0];
+        *RemCapAlarm |= EcResponse.Payload[1] << 8;
+    }
+
+    NVODMBATTERY_PRINTF(("[EXIT]NvOdmBatteryGetRemCapacityAlarm.\n"));
+#endif /* end of NVEC_BATTERY_DISABLED */
+    return NV_TRUE;
+}
+
+/**
+ * Sets the battery capacity unit configuration (mAh or 10mWh)
+ *
+ * @param hDevice [IN] A handle to the EC.
+ * @param BatteryInst [IN] The battery type.
+ * @param Configuration [IN] Capacity Unit
+ */
+NvBool NvOdmBatterySetConfiguration(
+       NvOdmBatteryDeviceHandle hDevice,
+       NvOdmBatteryInstance BatteryInst,
+       NvU8 Configuration)
+{
+#if NVEC_BATTERY_DISABLED
+    ;
+#else
+    NvError NvStatus = NvError_Success;
+    NvEcRequest EcRequest = {0};
+    NvEcResponse EcResponse = {0};
+    NvOdmBatteryDevice *pBattContext = NULL;
+
+    NVODMBATTERY_PRINTF(("[ENTER]NvOdmBatterySetConfiguration.\n"));
+    pBattContext = (NvOdmBatteryDevice *)hDevice;
+
+    /* Fill up request structure */
+    EcRequest.PacketType = NvEcPacketType_Request;
+    EcRequest.RequestType = NvEcRequestResponseType_Battery;
+    EcRequest.RequestSubtype = NvEcBatterySubtype_SetConfiguration;
+    EcRequest.NumPayloadBytes = 1;
+    EcRequest.Payload[0] = Configuration;
+
+    /* Request to EC */
+    NvStatus = NvEcSendRequest(pBattContext->hEc, &EcRequest, &EcResponse,
+                              sizeof(EcRequest), sizeof(EcResponse));
+    if (NvSuccess != NvStatus)
+    {
+        NVODMBATTERY_PRINTF(("NvEcSendRequest failed for NvOdmBatterySetConfiguration\n"));
+        return NV_FALSE;
+    }
+
+    if(EcResponse.Status == NvEcStatus_Success)
+    {
+        NVODMBATTERY_PRINTF(("EcResponse.Status failed for NvOdmBatterySetConfiguration\n"));
+        return NV_FALSE;
+    }
+
+    NVODMBATTERY_PRINTF(("[EXIT]NvOdmBatterySetConfiguration.\n"));
+#endif /* end of NVEC_BATTERY_DISABLED */
+    return NV_TRUE;
+}
+
+/**
+ * Gets the battery capacity unit configuration (mAh or 10mWh).
+ *
+ * @param hDevice [IN] A handle to the EC.
+ * @param BatteryInst [IN] The battery type.
+ * @param Configuration [OUT] Capacity Unit
+ */
+NvBool NvOdmBatteryGetConfiguration(
+       NvOdmBatteryDeviceHandle hDevice,
+       NvOdmBatteryInstance BatteryInst,
+       NvU8 *Configuration)
+{
+#if NVEC_BATTERY_DISABLED
+    *Configuration = 0;
+#else
+    NvError NvStatus = NvError_Success;
+    NvEcRequest EcRequest = {0};
+    NvEcResponse EcResponse = {0};
+    NvOdmBatteryDevice *pBattContext = NULL;
+
+    NVODMBATTERY_PRINTF(("[ENTER]NvOdmBatteryGetConfiguration.\n"));
+    *Configuration = 0;
+    pBattContext = (NvOdmBatteryDevice *)hDevice;
+
+    /* Fill up request structure */
+    EcRequest.PacketType = NvEcPacketType_Request;
+    EcRequest.RequestType = NvEcRequestResponseType_Battery;
+    EcRequest.RequestSubtype = NvEcBatterySubtype_GetConfiguration;
+    EcRequest.NumPayloadBytes = 0;
+    EcRequest.Payload[0] = 0;
+
+    /* Request to EC */
+    NvStatus = NvEcSendRequest(pBattContext->hEc, &EcRequest, &EcResponse,
+                              sizeof(EcRequest), sizeof(EcResponse));
+    if (NvSuccess != NvStatus)
+    {
+        NVODMBATTERY_PRINTF(("NvEcSendRequest failed for NvOdmBatteryGetConfiguration\n"));
+        return NV_FALSE;
+    }
+
+    if(EcResponse.Status == NvEcStatus_Success)
+    {
+        *Configuration = EcResponse.Payload[0];
+    }
+
+    NVODMBATTERY_PRINTF(("[EXIT]NvOdmBatteryGetConfiguration.\n"));
+#endif /* end of NVEC_BATTERY_DISABLED */
+    return NV_TRUE;
+}
+#endif
+
+/**
+ * Gets the battery Current.
+ *
+ * @param hDevice [IN] A handle to the EC.
+ * @param BatteryInst [IN] The battery type.
+ * @param pCurrent [OUT] A pointer to the battery current
+ */
+NvBool NvOdmBatteryPrivGetCurrent(
+       NvOdmBatteryDeviceHandle hDevice,
+       NvOdmBatteryInstance BatteryInst,
+       NvS32 *pCurrent)
+{
+#if NVEC_BATTERY_DISABLED
+    *pCurrent = NVODM_BATTERY_DATA_UNKNOWN;
+#else
+    NvError NvStatus = NvError_Success;
+    NvEcRequest EcRequest = {0};
+    NvEcResponse EcResponse = {0};
+    NvEcBatteryGetCurrentResponsePayload BatteryCurrent;
+    NvOdmBatteryDevice *pBattContext = NULL;
+
+    NVODMBATTERY_PRINTF(("[ENTER]NvOdmBatteryPrivGetCurrent.\n"));
+    *pCurrent = NVODM_BATTERY_DATA_UNKNOWN;
+    pBattContext = (NvOdmBatteryDevice *)hDevice;
+
+    /* Fill up request structure */
+    EcRequest.PacketType = NvEcPacketType_Request;
+    EcRequest.RequestType = NvEcRequestResponseType_Battery;
+    EcRequest.RequestSubtype = NvEcBatterySubtype_GetCurrent;
+    EcRequest.NumPayloadBytes = 0;
+    EcRequest.Payload[0] = 0;
+
+    /* Request to EC */
+    NvStatus = NvEcSendRequest(pBattContext->hEc, &EcRequest, &EcResponse,
+                               sizeof(EcRequest), sizeof(EcResponse));
+    if (NvSuccess != NvStatus)
+    {
+        NVODMBATTERY_PRINTF(("NvEcSendRequest failed for \
+                              NvOdmBatteryPrivGetCurrent\n"));
+        return NV_FALSE;
+    }
+
+    if(EcResponse.Status == NvEcStatus_Success)
+    {
+        NvOdmOsMemcpy(&BatteryCurrent, EcResponse.Payload,
+                    EcResponse.NumPayloadBytes);
+        *pCurrent = BatteryCurrent.PresentCurrent[0];
+        *pCurrent |= BatteryCurrent.PresentCurrent[1] << 8;
+    }
+
+    NVODMBATTERY_PRINTF(("[EXIT]NvOdmBatteryPrivGetCurrent.\n"));
+#endif /* end of NVEC_BATTERY_DISABLED */
+    return NV_TRUE;
+}
+
+/**
+ * Gets the Battery Average Current.
+ *
+ * @param hDevice [IN] A handle to the EC.
+ * @param BatteryInst [IN] The battery type.
+ * @param pAverageCurrent [OUT] A pointer to the battery average current
+ */
+NvBool NvOdmBatteryPrivGetAverageCurrent(
+       NvOdmBatteryDeviceHandle hDevice,
+       NvOdmBatteryInstance BatteryInst,
+       NvS32 *pAverageCurrent)
+{
+#if NVEC_BATTERY_DISABLED
+    *pAverageCurrent = NVODM_BATTERY_DATA_UNKNOWN;
+#else
+    NvError NvStatus = NvError_Success;
+    NvEcRequest EcRequest = {0};
+    NvEcResponse EcResponse = {0};
+    NvEcBatteryGetAverageCurrentResponsePayload BatteryAverageCurrent;
+    NvOdmBatteryDevice *pBattContext = NULL;
+
+    NVODMBATTERY_PRINTF(("[ENTER]NvOdmBatteryPrivGetAverageCurrent.\n"));
+    *pAverageCurrent = NVODM_BATTERY_DATA_UNKNOWN;
+    pBattContext = (NvOdmBatteryDevice *)hDevice;
+
+    /* Fill up request structure */
+    EcRequest.PacketType = NvEcPacketType_Request;
+    EcRequest.RequestType = NvEcRequestResponseType_Battery;
+    EcRequest.RequestSubtype = NvEcBatterySubtype_GetAverageCurrent;
+    EcRequest.NumPayloadBytes = 0;
+    EcRequest.Payload[0] = 0;
+
+    /* Request to EC */
+    NvStatus = NvEcSendRequest(pBattContext->hEc, &EcRequest, &EcResponse,
+                              sizeof(EcRequest), sizeof(EcResponse));
+    if (NvSuccess != NvStatus)
+    {
+        NVODMBATTERY_PRINTF(("NvEcSendRequest failed for \
+                              NvOdmBatteryPrivGetAverageCurrent\n"));
+        return NV_FALSE;
+    }
+
+    if(EcResponse.Status == NvEcStatus_Success)
+    {
+        NvOdmOsMemcpy(&BatteryAverageCurrent, EcResponse.Payload,
+                    EcResponse.NumPayloadBytes);
+        *pAverageCurrent = BatteryAverageCurrent.AverageCurrent[0];
+        *pAverageCurrent |= BatteryAverageCurrent.AverageCurrent[1] << 8;
+    }
+
+    NVODMBATTERY_PRINTF(("[EXIT]NvOdmBatteryPrivGetAverageCurrent.\n"));
+#endif /* end of NVEC_BATTERY_DISABLED */
+    return NV_TRUE;
+}
+
+/**
+ * Gets the Battery Average time interval.
+ *
+ * @param hDevice [IN] A handle to the EC.
+ * @param BatteryInst [IN] The battery type.
+ * @param pAverageTimeInterval [OUT] A pointer to the battery average
+ *        time interval
+ */
+NvBool NvOdmBatteryPrivGetAverageTimeInterval(
+       NvOdmBatteryDeviceHandle hDevice,
+       NvOdmBatteryInstance BatteryInst,
+       NvU32 *pAverageTimeInterval)
+{
+#if NVEC_BATTERY_DISABLED
+    *pAverageTimeInterval = NVODM_BATTERY_DATA_UNKNOWN;
+#else
+    NvError NvStatus = NvError_Success;
+    NvEcRequest EcRequest = {0};
+    NvEcResponse EcResponse = {0};
+    NvEcBatteryGetAveragingTimeIntervalResponsePayload \
+                            BatteryAverageTimeInterval;
+    NvOdmBatteryDevice *pBattContext = NULL;
+
+    NVODMBATTERY_PRINTF(("[ENTER]NvOdmBatteryPrivGetAverageTimeInterval.\n"));
+    *pAverageTimeInterval = NVODM_BATTERY_DATA_UNKNOWN;
+    pBattContext = (NvOdmBatteryDevice *)hDevice;
+
+    /* Fill up request structure */
+    EcRequest.PacketType = NvEcPacketType_Request;
+    EcRequest.RequestType = NvEcRequestResponseType_Battery;
+    EcRequest.RequestSubtype = NvEcBatterySubtype_GetAveragingTimeInterval;
+    EcRequest.NumPayloadBytes = 0;
+    EcRequest.Payload[0] = 0;
+
+    /* Request to EC */
+    NvStatus = NvEcSendRequest(pBattContext->hEc, &EcRequest, &EcResponse,
+                              sizeof(EcRequest), sizeof(EcResponse));
+    if (NvSuccess != NvStatus)
+    {
+        NVODMBATTERY_PRINTF(("NvEcSendRequest failed for \
+                              NvOdmBatteryPrivGetAverageTimeInterval\n"));
+        return NV_FALSE;
+    }
+
+    if(EcResponse.Status == NvEcStatus_Success)
+    {
+        NvOdmOsMemcpy(&BatteryAverageTimeInterval, EcResponse.Payload,
+                    EcResponse.NumPayloadBytes);
+        *pAverageTimeInterval = BatteryAverageTimeInterval.TimeInterval[0];
+        *pAverageTimeInterval |= \
+         BatteryAverageTimeInterval.TimeInterval[1] << 8;
+    }
+
+    NVODMBATTERY_PRINTF(("[EXIT]NvOdmBatteryPrivGetAverageTimeInterval.\n"));
+#endif /* end of NVEC_BATTERY_DISABLED */
+    return NV_TRUE;
+}
+
+/**
+ * Gets the Battery Temperature.
+ *
+ * @param hDevice [IN] A handle to the EC.
+ * @param BatteryInst [IN] The battery type.
+ * @param pBatteryTemp [OUT] A pointer to the battery Temperature
+ */
+NvBool NvOdmBatteryPrivGetTemperature(
+       NvOdmBatteryDeviceHandle hDevice,
+       NvOdmBatteryInstance BatteryInst,
+       NvU32 *pBatteryTemp)
+{
+#if NVEC_BATTERY_DISABLED
+    *pBatteryTemp = NVODM_BATTERY_DATA_UNKNOWN;
+#else
+    NvError NvStatus = NvError_Success;
+    NvEcRequest EcRequest = {0};
+    NvEcResponse EcResponse = {0};
+    NvEcBatteryGetTemperatureResponsePayload BatteryTemperature;
+    NvOdmBatteryDevice *pBattContext = NULL;
+
+    NVODMBATTERY_PRINTF(("[ENTER]NvOdmBatteryPrivGetTemperature.\n"));
+    *pBatteryTemp = NVODM_BATTERY_DATA_UNKNOWN;
+    pBattContext = (NvOdmBatteryDevice *)hDevice;
+
+    /* Fill up request structure */
+    EcRequest.PacketType = NvEcPacketType_Request;
+    EcRequest.RequestType = NvEcRequestResponseType_Battery;
+    EcRequest.RequestSubtype = NvEcBatterySubtype_GetTemperature;
+    EcRequest.NumPayloadBytes = 0;
+    EcRequest.Payload[0] = 0;
+
+    /* Request to EC */
+    NvStatus = NvEcSendRequest(pBattContext->hEc, &EcRequest, &EcResponse,
+                              sizeof(EcRequest), sizeof(EcResponse));
+    if (NvSuccess != NvStatus)
+    {
+        NVODMBATTERY_PRINTF(("NvEcSendRequest failed for \
+                              NvOdmBatteryPrivGetTemperature\n"));
+        return NV_FALSE;
+    }
+
+    if(EcResponse.Status == NvEcStatus_Success)
+    {
+        NvOdmOsMemcpy(&BatteryTemperature, EcResponse.Payload,
+                    EcResponse.NumPayloadBytes);
+        *pBatteryTemp = BatteryTemperature.Temperature[0];
+        *pBatteryTemp |= BatteryTemperature.Temperature[1] << 8;
+    }
+
+    NVODMBATTERY_PRINTF(("[EXIT]NvOdmBatteryPrivGetTemperature.\n"));
+#endif /* end of NVEC_BATTERY_DISABLED */
+    return NV_TRUE;
+}
+
+/**
+ * Gets the Battery Manufacturer.
+ *
+ * @param hDevice [IN] A handle to the EC.
+ * @param BatteryInst [IN] The battery type.
+ * @param pBatteryManufacturer [OUT] A pointer to the battery Manufacturer
+ */
+NvBool NvOdmBatteryGetManufacturer(
+       NvOdmBatteryDeviceHandle hDevice,
+       NvOdmBatteryInstance BatteryInst,
+       NvU8 *pBatteryManufacturer)
+{
+#if NVEC_BATTERY_DISABLED
+    *pBatteryManufacturer = '\0';
+#else
+    NvError NvStatus = NvError_Success;
+    NvEcRequest EcRequest = {0};
+    NvEcResponse EcResponse = {0};
+    NvEcBatteryGetManufacturerResponsePayload BatteryManufacturer;
+    NvOdmBatteryDevice *pBattContext = NULL;
+
+    NVODMBATTERY_PRINTF(("[ENTER]NvOdmBatteryGetManufacturer.\n"));
+    *pBatteryManufacturer = '\0';
+    pBattContext = (NvOdmBatteryDevice *)hDevice;
+
+    /* Fill up request structure */
+    EcRequest.PacketType = NvEcPacketType_Request;
+    EcRequest.RequestType = NvEcRequestResponseType_Battery;
+    EcRequest.RequestSubtype = NvEcBatterySubtype_GetManufacturer;
+    EcRequest.NumPayloadBytes = 0;
+    EcRequest.Payload[0] = 0;
+
+    /* Request to EC */
+    NvStatus = NvEcSendRequest(pBattContext->hEc, &EcRequest, &EcResponse,
+                              sizeof(EcRequest), sizeof(EcResponse));
+    if (NvSuccess != NvStatus)
+    {
+        NVODMBATTERY_PRINTF(("NvEcSendRequest failed for \
+                              NvOdmBatteryGetManufacturer\n"));
+        return NV_FALSE;
+    }
+
+    if(EcResponse.Status == NvEcStatus_Success)
+    {
+        NvOdmOsMemcpy(&BatteryManufacturer, EcResponse.Payload,
+                    EcResponse.NumPayloadBytes);
+        NvOdmOsMemcpy(pBatteryManufacturer, BatteryManufacturer.Manufacturer,
+                    EcResponse.NumPayloadBytes);
+    }
+
+    NVODMBATTERY_PRINTF(("[EXIT]NvOdmBatteryGetManufacturer.\n"));
+#endif /* end of NVEC_BATTERY_DISABLED */
+    return NV_TRUE;
+}
+
+/**
+ * Gets the Battery Model.
+ *
+ * @param hDevice [IN] A handle to the EC.
+ * @param BatteryInst [IN] The battery type.
+ * @param pBatteryModel [OUT] A pointer to the battery model
+ */
+NvBool NvOdmBatteryGetModel(
+       NvOdmBatteryDeviceHandle hDevice,
+       NvOdmBatteryInstance BatteryInst,
+       NvU8 *pBatteryModel)
+{
+#if NVEC_BATTERY_DISABLED
+    *pBatteryModel = '\0';
+#else
+    NvError NvStatus = NvError_Success;
+    NvEcRequest EcRequest = {0};
+    NvEcResponse EcResponse = {0};
+    NvEcBatteryGetModelResponsePayload BatteryModel;
+    NvOdmBatteryDevice *pBattContext = NULL;
+
+    NVODMBATTERY_PRINTF(("[ENTER]NvOdmBatteryGetModel.\n"));
+    *pBatteryModel = '\0';
+    pBattContext = (NvOdmBatteryDevice *)hDevice;
+
+    /* Fill up request structure */
+    EcRequest.PacketType = NvEcPacketType_Request;
+    EcRequest.RequestType = NvEcRequestResponseType_Battery;
+    EcRequest.RequestSubtype = NvEcBatterySubtype_GetModel;
+    EcRequest.NumPayloadBytes = 0;
+    EcRequest.Payload[0] = 0;
+
+    /* Request to EC */
+    NvStatus = NvEcSendRequest(pBattContext->hEc, &EcRequest, &EcResponse,
+                              sizeof(EcRequest), sizeof(EcResponse));
+    if (NvSuccess != NvStatus)
+    {
+        NVODMBATTERY_PRINTF(("NvEcSendRequest failed for \
+                              NvOdmBatteryGetModel\n"));
+        return NV_FALSE;
+    }
+
+    if(EcResponse.Status == NvEcStatus_Success)
+    {
+        NvOdmOsMemcpy(&BatteryModel, EcResponse.Payload,
+                    EcResponse.NumPayloadBytes);
+        NvOdmOsMemcpy(pBatteryModel, BatteryModel.Model,
+                   EcResponse.NumPayloadBytes);
+    }
+
+    NVODMBATTERY_PRINTF(("[EXIT]NvOdmBatteryGetModel.\n"));
+#endif /* end of NVEC_BATTERY_DISABLED */
+    return NV_TRUE;
+}
+/**
+ * Gets the Battery Remaining Capacity.
+ *
+ * @param hDevice [IN] A handle to the EC.
+ * @param BatteryInst [IN] The battery type.
+ * @param pRemCapacity [OUT] A pointer to the battery remaining capacity
+ */
+NvBool NvOdmBatteryPrivGetRemainingCapacity(
+       NvOdmBatteryDeviceHandle hDevice,
+       NvOdmBatteryInstance BatteryInst,
+       NvU32 *pRemCapacity)
+{
+#if NVEC_BATTERY_DISABLED
+    *pRemCapacity = NVODM_BATTERY_DATA_UNKNOWN;
+#else
+    NvError NvStatus = NvError_Success;
+    NvEcRequest EcRequest = {0};
+    NvEcResponse EcResponse = {0};
+    NvEcBatteryGetCapacityRemainingResponsePayload BatteryRemCap;
+    NvOdmBatteryDevice *pBattContext = NULL;
+
+    NVODMBATTERY_PRINTF(("[ENTER]NvOdmBatteryPrivGetRemainingCapacity.\n"));
+    *pRemCapacity = NVODM_BATTERY_DATA_UNKNOWN;
+    pBattContext = (NvOdmBatteryDevice *)hDevice;
+
+    /* Fill up request structure */
+    EcRequest.PacketType = NvEcPacketType_Request;
+    EcRequest.RequestType = NvEcRequestResponseType_Battery;
+    EcRequest.RequestSubtype = NvEcBatterySubtype_GetCapacityRemaining;
+    EcRequest.NumPayloadBytes = 0;
+    EcRequest.Payload[0] = 0;
+
+    /* Request to EC */
+    NvStatus = NvEcSendRequest(pBattContext->hEc, &EcRequest, &EcResponse,
+                              sizeof(EcRequest), sizeof(EcResponse));
+    if (NvSuccess != NvStatus)
+    {
+        NVODMBATTERY_PRINTF(("NvEcSendRequest failed for \
+                              NvOdmBatteryPrivGetRemainingCapacity\n"));
+        return NV_FALSE;
+    }
+
+    if(EcResponse.Status == NvEcStatus_Success)
+    {
+        NvOdmOsMemcpy(&BatteryRemCap, EcResponse.Payload,
+                    EcResponse.NumPayloadBytes);
+        *pRemCapacity = BatteryRemCap.CapacityRemaining[0];
+        *pRemCapacity |= BatteryRemCap.CapacityRemaining[1] << 8;
+    }
+
+    NVODMBATTERY_PRINTF(("[EXIT]NvOdmBatteryPrivGetRemainingCapacity.\n"));
+#endif /* end of NVEC_BATTERY_DISABLED */
+    return NV_TRUE;
+}
+
+/**
+ * Gets the Battery Last FullCharge Capacity
+ *
+ * @param hDevice [IN] A handle to the EC.
+ * @param BatteryInst [IN] The battery type.
+ * @param pLastFullChargeCapacity [OUT] A pointer to the battery
+ *        last fullcharge capacity
+ */
+NvBool NvOdmBatteryPrivGetLastFullChargeCapacity(
+       NvOdmBatteryDeviceHandle hDevice,
+       NvOdmBatteryInstance BatteryInst,
+       NvU32 *pLastFullChargeCapacity)
+{
+#if NVEC_BATTERY_DISABLED
+    *pLastFullChargeCapacity = NVODM_BATTERY_DATA_UNKNOWN;
+#else
+    NvError NvStatus = NvError_Success;
+    NvEcRequest EcRequest = {0};
+    NvEcResponse EcResponse = {0};
+    NvEcBatteryGetLastFullChargeCapacityResponsePayload \
+        BatteryLastFullChargeCap;
+    NvOdmBatteryDevice *pBattContext = NULL;
+
+    NVODMBATTERY_PRINTF(("+NvOdmBatteryPrivGetLastFullChargeCapacity.\n"));
+    *pLastFullChargeCapacity = NVODM_BATTERY_DATA_UNKNOWN;
+    pBattContext = (NvOdmBatteryDevice *)hDevice;
+
+    /* Fill up request structure */
+    EcRequest.PacketType = NvEcPacketType_Request;
+    EcRequest.RequestType = NvEcRequestResponseType_Battery;
+    EcRequest.RequestSubtype = NvEcBatterySubtype_GetLastFullChargeCapacity;
+    EcRequest.NumPayloadBytes = 0;
+    EcRequest.Payload[0] = 0;
+
+    /* Request to EC */
+    NvStatus = NvEcSendRequest(pBattContext->hEc, &EcRequest, &EcResponse,
+                              sizeof(EcRequest), sizeof(EcResponse));
+    if (NvSuccess != NvStatus)
+    {
+        NVODMBATTERY_PRINTF(("NvEcSendRequest failed for \
+                        NvOdmBatteryPrivGetLastFullChargeCapacity\n"));
+        return NV_FALSE;
+    }
+
+    if(EcResponse.Status == NvEcStatus_Success)
+    {
+        NvOdmOsMemcpy(&BatteryLastFullChargeCap, EcResponse.Payload,
+                    EcResponse.NumPayloadBytes);
+        *pLastFullChargeCapacity = \
+            BatteryLastFullChargeCap.LastFullChargeCapacity[0];
+        *pLastFullChargeCapacity |= \
+            BatteryLastFullChargeCap.LastFullChargeCapacity[1] << 8;
+    }
+
+    NVODMBATTERY_PRINTF(("-NvOdmBatteryPrivGetLastFullChargeCapacity.\n"));
+#endif /* end of NVEC_BATTERY_DISABLED */
+    return NV_TRUE;
+}
+
+/**
+ * Gets the Battery critical capacity
+ *
+ * @param hDevice [IN] A handle to the EC.
+ * @param BatteryInst [IN] The battery type.
+ * @param pCriticalCapacity [OUT] A pointer to the battery critical capacity
+ */
+NvBool NvOdmBatteryPrivGetCriticalCapacity(
+       NvOdmBatteryDeviceHandle hDevice,
+       NvOdmBatteryInstance BatteryInst,
+       NvU32 *pCriticalCapacity)
+{
+#if NVEC_BATTERY_DISABLED
+    *pCriticalCapacity = NVODM_BATTERY_DATA_UNKNOWN;
+#else
+    NvError NvStatus = NvError_Success;
+    NvEcRequest EcRequest = {0};
+    NvEcResponse EcResponse = {0};
+    NvEcBatteryGetCriticalCapacityResponsePayload BatteryCriticalCap;
+    NvOdmBatteryDevice *pBattContext = NULL;
+
+    NVODMBATTERY_PRINTF(("[ENTER]NvOdmBatteryPrivGetCriticalCapacity.\n"));
+    *pCriticalCapacity = NVODM_BATTERY_DATA_UNKNOWN;
+    pBattContext = (NvOdmBatteryDevice *)hDevice;
+
+    /* Fill up request structure */
+    EcRequest.PacketType = NvEcPacketType_Request;
+    EcRequest.RequestType = NvEcRequestResponseType_Battery;
+    EcRequest.RequestSubtype = NvEcBatterySubtype_GetCriticalCapacity;
+    EcRequest.NumPayloadBytes = 0;
+    EcRequest.Payload[0] = 0;
+
+    /* Request to EC */
+    NvStatus = NvEcSendRequest(pBattContext->hEc, &EcRequest, &EcResponse,
+                              sizeof(EcRequest), sizeof(EcResponse));
+    if (NvSuccess != NvStatus)
+    {
+        NVODMBATTERY_PRINTF(("NvEcSendRequest failed for \
+                        NvOdmBatteryPrivGetCriticalCapacity\n"));
+        return NV_FALSE;
+    }
+
+    if(EcResponse.Status == NvEcStatus_Success)
+    {
+        NvOdmOsMemcpy(&BatteryCriticalCap, EcResponse.Payload,
+                    EcResponse.NumPayloadBytes);
+        *pCriticalCapacity = BatteryCriticalCap.CriticalCapacity[0];
+        *pCriticalCapacity |= BatteryCriticalCap.CriticalCapacity[1] << 8;
+    }
+
+    NVODMBATTERY_PRINTF(("[EXIT]NvOdmBatteryPrivGetCriticalCapacity.\n"));
+#endif /* end of NVEC_BATTERY_DISABLED */
+    return NV_TRUE;
+}
+
+/**
+ * Gets Battery Slot status and Capacity Guage.
+ *
+ * @param pBattContext [IN] Handle to the Battery Context.
+ * @param BatteryInst  [IN] battery type.
+ * @param BatterySlotStatus [OUT] gives battery presence and charging status
+ * @param BatteryCapacityGuage [OUT] Battery's relative remaining capacity in %
+ *
+ * @return NV_TRUE if successful, or NV_FALSE otherwise.
+ */
+NvBool
+NvOdmBatteryPrivGetSlotStatusAndCapacityGuage(NvOdmBatteryDevice *pBattContext,
+                                              NvOdmBatteryInstance BatteryInst,
+                                              NvU8 *BatterySlotStatus,
+                                              NvU8 *BatteryCapacityGuage)
+{
+#if NVEC_BATTERY_DISABLED
+    return NV_FALSE;
+#else
+    NvError NvStatus = NvError_Success;
+    NvEcRequest EcRequest = {0};
+    NvEcResponse EcResponse = {0};
+
+    NVODMBATTERY_PRINTF(("NvOdmBatteryPrivGetSlotStatusAndCapacityGuage:Enter"));
+
+    /* Fill up request structure */
+    EcRequest.PacketType = NvEcPacketType_Request;
+    EcRequest.RequestType = NvEcRequestResponseType_Battery;
+    EcRequest.RequestSubtype = NvEcBatterySubtype_GetSlotStatus;
+    EcRequest.NumPayloadBytes = 0;
+    EcRequest.Payload[0] = 0;
+
+    /* Request to EC */
+    NvStatus = NvEcSendRequest(pBattContext->hEc, &EcRequest, &EcResponse,
+                               sizeof(EcRequest), sizeof(EcResponse));
+    if (NvSuccess != NvStatus)
+    {
+        NVODMBATTERY_PRINTF(("NvEcSendRequest failed for \
+                NvOdmBatteryPrivGetSlotStatusAndCapacityGuage\n"));
+        return NV_FALSE;
+    }
+
+    if(EcResponse.Status == NvEcStatus_Success)
+    {
+        *BatterySlotStatus = \
+            EcResponse.Payload[NVODM_BATTERY_SLOT_STATUS_DATA];
+        *BatteryCapacityGuage = \
+            EcResponse.Payload[NVODM_BATTERY_CAPACITY_GUAGE_DATA];
+    }
+    else
+    {
+        *BatterySlotStatus = 0;
+        *BatteryCapacityGuage = 0;
+        /*
+         * if the response status is unavailable (0x03) that means
+         *  HW is unavailable
+         * in that case return TRUE to tell that Battery is not present.
+         */
+        if (EcResponse.Status == NvEcStatus_Unavailable)
+            return NV_TRUE;
+
+        return NV_FALSE;
+    }
+
+    NVODMBATTERY_PRINTF(("NvOdmBatteryPrivGetSlotStatusAndCapacityGuage:Exit"));
+    return NV_TRUE;
+#endif /* end of NVEC_BATTERY_DISABLED */
+}
+
+/**
+ * Gets Battery's Life time
+ *
+ * @param pBattContext [IN] Handle to the Battery Context.
+ * @param BatteryInst [IN] battery type.
+ * @param BatteryLifeTime [OUT] Estimated remaining time to empty
+ *                        for discharging.
+ *                        battery at present rate (in [min])
+ *                        Report 0FFFFh if battery is not discharging
+ *
+ * @return NV_TRUE if successful, or NV_FALSE otherwise.
+ */
+NvBool NvOdmBatteryPrivGetLifeTime(NvOdmBatteryDevice *pBattContext,
+                                   NvOdmBatteryInstance BatteryInst,
+                                   NvU32 *BatteryLifeTime)
+{
+#if NVEC_BATTERY_DISABLED
+    return NV_FALSE;
+#else
+    NvError NvStatus = NvError_Success;
+    NvEcRequest EcRequest = {0};
+    NvEcResponse EcResponse = {0};
+    NvEcBatteryGetTimeRemainingResponsePayload BattTimeRemain;
+
+    /* Fill up request structure */
+    EcRequest.PacketType = NvEcPacketType_Request;
+    EcRequest.RequestType = NvEcRequestResponseType_Battery;
+    EcRequest.RequestSubtype = NvEcBatterySubtype_GetTimeRemaining;
+    EcRequest.NumPayloadBytes = 0;
+    EcRequest.Payload[0] = 0;
+
+    /* Request to EC */
+    NvStatus = NvEcSendRequest(pBattContext->hEc, &EcRequest, &EcResponse,
+                               sizeof(EcRequest), sizeof(EcResponse));
+    if (NvSuccess != NvStatus)
+    {
+        NVODMBATTERY_PRINTF(("NvEcSendRequest failed for \
+                NvOdmBatteryPrivGetLifeTime\n"));
+        return NV_FALSE;
+    }
+
+    if(EcResponse.Status == NvEcStatus_Success)
+    {
+        NvOdmOsMemcpy(&BattTimeRemain, EcResponse.Payload,
+            EcResponse.NumPayloadBytes);
+        *BatteryLifeTime  = BattTimeRemain.TimeRemaining[0];
+        *BatteryLifeTime |= BattTimeRemain.TimeRemaining[1] << 8;
+    }
+    else
+    {
+        NVODMBATTERY_PRINTF(("EcResponse.Status failed for \
+                    NvOdmBatteryPrivGetLifeTime\n"));
+        *BatteryLifeTime = 0;
+        return NV_FALSE;
+    }
+
+    return NV_TRUE;
+#endif /* end of NVEC_BATTERY_DISABLED */
+}
+
+/**
+ * Gets Battery's Present voltage
+ *
+ * @param pBattContext [IN] Handle to the Battery Context.
+ * @param BatteryInst  [IN] battery type.
+ * @param BatteryVoltage [OUT] Battery's present voltage
+ *        (16-bit unsigned  value, in [mV])
+ * @return NV_TRUE if successful, or NV_FALSE otherwise.
+ */
+NvBool NvOdmPrivBattGetBatteryVoltage(NvOdmBatteryDevice *pBattContext,
+                                      NvOdmBatteryInstance BatteryInst,
+                                      NvU32 *BatteryVoltage)
+{
+#if NVEC_BATTERY_DISABLED
+    return NV_FALSE;
+#else
+    NvError      NvStatus   = NvError_Success;
+    NvEcRequest  EcRequest  = {0};
+    NvEcResponse EcResponse = {0};
+    NvEcBatteryGetVoltageResponsePayload BattVoltage;
+
+    /* Fill up request structure */
+    EcRequest.PacketType = NvEcPacketType_Request;
+    EcRequest.RequestType = NvEcRequestResponseType_Battery;
+    EcRequest.RequestSubtype = NvEcBatterySubtype_GetVoltage;
+    EcRequest.NumPayloadBytes = 0;
+    EcRequest.Payload[0] = 0;
+
+    /* Request to EC */
+    NvStatus = NvEcSendRequest(pBattContext->hEc, &EcRequest, &EcResponse,
+                               sizeof(EcRequest), sizeof(EcResponse));
+    if (NvSuccess != NvStatus)
+    {
+        NVODMBATTERY_PRINTF(("NvEcSendRequest failed \
+                    NvOdmPrivBattGetBatteryVoltage\n"));
+        return NV_FALSE;
+    }
+
+    if(EcResponse.Status == NvEcStatus_Success)
+    {
+        NvOdmOsMemcpy(&BattVoltage, EcResponse.Payload,
+                    EcResponse.NumPayloadBytes);
+        NvOdmOsMemcpy(BatteryVoltage, BattVoltage.PresentVoltage,
+                    sizeof(BattVoltage.PresentVoltage));
+    }
+    else
+    {
+        NVODMBATTERY_PRINTF(("EcResponse.Status failed in \
+                    NvOdmPrivBattGetBatteryVoltage\n"));
+        *BatteryVoltage = 0;
+        return NV_FALSE;
+    }
+
+    return NV_TRUE;
+#endif /* end of NVEC_BATTERY_DISABLED */
+}
+
+/**
+ *  Openes the battery device handle
+ *
+ * @param hDevice [OUT] handle to Battery Device.
+ *
+ * @return NV_TRUE on success.
+ */
+NvBool NvOdmBatteryDeviceOpen(NvOdmBatteryDeviceHandle *hDevice,
+                              NvOdmOsSemaphoreHandle *hOdmSemaphore)
+{
+    NvOdmBatteryDevice *pBattContext = NULL;
+    NvError NvStatus = NvError_Success;
+    NvEcEventType EventTypes[] = {NvEcEventType_Battery};
+    NvS32    MajorVersion = 0, MinorVersion = 0;
+    NvEcRequest  EcRequest = {0};
+    NvEcResponse EcResponse = {0};
+#if NVODM_LOWBATTERY_GPIO_INT
+    NvOsInterruptHandler IntrHandler = {NULL};
+#endif
+    NvU32 BatteryDesignCap = 0;
+    NvU16 RemCapAlarm = 0;
+
+    NVODMBATTERY_PRINTF(("[ENTER] NvOdmBatteryDeviceOpen. \n"));
+
+    /* Allocate the context */
+    pBattContext = NvOdmOsAlloc(sizeof(NvOdmBatteryDevice));
+    if (!pBattContext)
+    {
+        NVODMBATTERY_PRINTF(("NvOdmOsAlloc failed to allocate pBattContext."));
+        return NV_FALSE;
+    }
+
+    NvOdmOsMemset(pBattContext, 0, sizeof(NvOdmBatteryDevice));
+
+    /* Get nvec handle */
+    NvStatus = NvEcOpen(&pBattContext->hEc, 0 /* instance */);
+    if (NvStatus != NvError_Success)
+    {
+        NVODMBATTERY_PRINTF(("NvEcOpen failed for NvOdmBatteryDeviceOpen.\n"));
+        goto Cleanup;
+    }
+
+    /* Get the EC Firmware version */
+    NvStatus = NvOdmBatteryPrivEcGetFirmwareVersion(pBattContext,
+                                                    &MajorVersion,
+                                                    &MinorVersion);
+    if (NvStatus != NvError_Success)
+    {
+        goto Cleanup;
+    }
+
+    pBattContext->ECVersion = MinorVersion;
+    NVODMBATTERY_PRINTF(("EC Firmware Version = 0x%x\n", MinorVersion));
+
+    if (hOdmSemaphore != NULL && *hOdmSemaphore != NULL)
+    {
+        pBattContext->hClientBattEventSem = *hOdmSemaphore;
+
+        /* Semaphore to receive Battery events from EC */
+        pBattContext->hBattEventSem = NvOdmOsSemaphoreCreate(0);
+        if (!pBattContext->hBattEventSem)
+        {
+            goto Cleanup;
+        }
+
+        /* Thread to handle Battery events */
+        pBattContext->hBattEventThread = NvOdmOsThreadCreate(
+                               (NvOdmOsThreadFunction)NvOdmBatteryEventHandler,
+                               (void *)pBattContext);
+        if (!pBattContext->hBattEventThread)
+        {
+            goto Cleanup;
+        }
+
+        if (pBattContext->ECVersion >= NVODM_BATTERY_EC_FIRMWARE_VER_R04)
+        {
+#if NVODM_WAKEUP_FROM_BATTERY_EVENT
+           /* Configure the Batter present event as a wakeup */
+            EcRequest.PacketType = NvEcPacketType_Request;
+            EcRequest.RequestType = NvEcRequestResponseType_Battery;
+            EcRequest.RequestSubtype = (NvEcRequestResponseSubtype)
+                                  NvEcBatterySubtype_ConfigureWake;
+            EcRequest.NumPayloadBytes = 2;
+            EcRequest.Payload[0] = NVEC_BATTERY_REPORT_ENABLE_0_ACTION_ENABLE;
+            EcRequest.Payload[1] = NVODM_BATTERY_SET_PRESENT_EVENT
+#if NVODM_BATTERY_LOW_CAPACITY_ALARM
+                | NVODM_BATTERY_SET_REM_CAP_ALARM_EVENT
+#endif
+                ;
+
+            NvStatus = NvEcSendRequest(pBattContext->hEc, &EcRequest, &EcResponse,
+                     sizeof(EcRequest), sizeof(EcResponse));
+            if (NvStatus != NvSuccess)
+                goto Cleanup;
+
+            if (EcResponse.Status != NvEcStatus_Success)
+                goto Cleanup;
+#endif
+
+#if NVODM_WAKEUP_FROM_AC_EVENT
+           /* Configure the AC present event  as a wakeup */
+            EcRequest.PacketType = NvEcPacketType_Request;
+            EcRequest.RequestType = NvEcRequestResponseType_System;
+            EcRequest.RequestSubtype = (NvEcRequestResponseSubtype)
+                                  NvEcSystemSubtype_ConfigureWake;
+            EcRequest.NumPayloadBytes = 2;
+            EcRequest.Payload[0] = NVEC_SYSTEM_REPORT_ENABLE_0_ACTION_ENABLE;
+            EcRequest.Payload[1] = NVEC_SYSTEM_STATE1_0_AC_PRESENT;
+
+            NvStatus = NvEcSendRequest(pBattContext->hEc, &EcRequest, &EcResponse,
+                     sizeof(EcRequest), sizeof(EcResponse));
+            if (NvStatus != NvSuccess)
+                goto Cleanup;
+
+            if (EcResponse.Status != NvEcStatus_Success)
+                goto Cleanup;
+#endif
+            /* Configure the Battery events */
+            EcRequest.PacketType = NvEcPacketType_Request;
+            EcRequest.RequestType = NvEcRequestResponseType_Battery;
+            EcRequest.RequestSubtype = (NvEcRequestResponseSubtype)
+                                  NvEcBatterySubtype_ConfigureEventReporting;
+            EcRequest.NumPayloadBytes = 2;
+            EcRequest.Payload[0] = NVEC_BATTERY_REPORT_ENABLE_0_ACTION_ENABLE;
+             /* Bit 0 = Present State event */
+             /* Bit 1 = Charging State event */
+             /* Bit 2 = Remaining Capacity Alaram event */
+            EcRequest.Payload[1] = NVODM_BATTERY_SET_PRESENT_EVENT |
+                                   NVODM_BATTERY_SET_CHARGING_EVENT|
+                                   NVODM_BATTERY_SET_REM_CAP_ALARM_EVENT;
+
+            NvStatus = NvEcSendRequest(pBattContext->hEc, &EcRequest, &EcResponse,
+                     sizeof(EcRequest), sizeof(EcResponse));
+            if (NvStatus != NvSuccess)
+                goto Cleanup;
+
+            if (EcResponse.Status != NvEcStatus_Success)
+                goto Cleanup;
+
+            /* Get the design capacity */
+            NvOdmBatteryGetBatteryFullLifeTime(pBattContext, NvOdmBatteryInst_Main,
+                                               &BatteryDesignCap);
+            /* Set the remaining capacity alarm for 10% of the design capacity */
+            RemCapAlarm = (BatteryDesignCap * 10)/100;
+            NvOdmBatterySetRemCapacityAlarm(pBattContext, NvOdmBatteryInst_Main, RemCapAlarm);
+        }
+
+        /* Register for Battery events */
+        NvStatus = NvEcRegisterForEvents(
+                   pBattContext->hEc,
+                   &pBattContext->hEcEventReg,
+                   (NvOsSemaphoreHandle)pBattContext->hBattEventSem,
+                   sizeof(EventTypes)/sizeof(NvEcEventType),
+                   EventTypes,
+                   1,
+                   sizeof(NvEcEvent));
+        if (NvStatus != NvError_Success)
+        {
+            goto Cleanup;
+        }
+
+#if NVODM_LOWBATTERY_GPIO_INT
+        NvStatus = NvRmOpen(&pBattContext->hRm, 0);
+        if (NvStatus != NvError_Success)
+            goto Cleanup;
+
+        NvStatus = NvRmGpioOpen(pBattContext->hRm, &pBattContext->hGpio);
+        if (NvStatus != NvError_Success)
+            goto Cleanup;
+
+        pBattContext->pGpioPinInfo = NvOdmQueryGpioPinMap(
+                                     NvOdmGpioPinGroup_Battery,
+                                     0,
+                                     &pBattContext->PinCount);
+        if (pBattContext->pGpioPinInfo != NULL)
+        {
+
+            IntrHandler = (NvOsInterruptHandler)NvOdmBatteryGpioInterruptHandler;
+
+            if (pBattContext->pGpioPinInfo[0].Port != 0 &&
+                pBattContext->pGpioPinInfo[0].Pin != 0)
+            {
+
+                NvRmGpioAcquirePinHandle(
+                        pBattContext->hGpio,
+                        pBattContext->pGpioPinInfo[0].Port,
+                        pBattContext->pGpioPinInfo[0].Pin,
+                        &pBattContext->hPin);
+                if (!pBattContext->hPin)
+                {
+                    goto Cleanup;
+                }
+
+                /* Register to receive GPIO events */
+                NvStatus = NvRmGpioInterruptRegister(
+                           pBattContext->hGpio,
+                           pBattContext->hRm,
+                           pBattContext->hPin,
+                           IntrHandler,
+                           NvRmGpioPinMode_InputInterruptAny,
+                           pBattContext,
+                           &pBattContext->GpioIntrHandle,
+                           0);
+                if (NvStatus != NvError_Success)
+                {
+                    goto Cleanup;
+                }
+
+                NvStatus = NvRmGpioInterruptEnable(pBattContext->GpioIntrHandle);
+                if (NvStatus != NvError_Success)
+                {
+                    goto Cleanup;
+                }
+            }
+        }
+#endif
+    }
+
+    *hDevice = pBattContext;
+    NVODMBATTERY_PRINTF(("[EXIT] NvOdmBatteryDeviceOpen.\n"));
+    return NV_TRUE;
+
+Cleanup:
+    NvOdmBatteryDeviceClose(pBattContext);
+
+    return NV_FALSE;
+}
+
+/**
+ *  Closes the battery device
+ *
+ * @param hDevice [IN] handle to Battery Device.
+ * 
+ * @return void.
+ */
+void NvOdmBatteryDeviceClose(NvOdmBatteryDeviceHandle hDevice)
+{
+    NvOdmBatteryDevice *pBattContext = NULL;
+
+    pBattContext = (NvOdmBatteryDevice *)hDevice;
+
+#if NVODM_LOWBATTERY_GPIO_INT
+    if (pBattContext->hGpio)
+    {
+        if (pBattContext->GpioIntrHandle)
+        {
+            NvRmGpioInterruptUnregister(pBattContext->hGpio, pBattContext->hRm,
+                pBattContext->GpioIntrHandle);
+            pBattContext->GpioIntrHandle = NULL;
+        }
+
+        NvRmGpioReleasePinHandles(pBattContext->hGpio, &pBattContext->hPin,
+            pBattContext->PinCount);
+        NvRmGpioClose(pBattContext->hGpio);
+    }
+
+    if (pBattContext->hRm)
+    {
+        NvRmClose(pBattContext->hRm);
+        pBattContext->hRm = NULL;
+    }
+#endif
+
+    if (pBattContext->hBattEventSem)
+    {
+        pBattContext->ExitThread = NV_TRUE;
+        NvOdmOsSemaphoreSignal(pBattContext->hBattEventSem);
+        NvOdmOsSemaphoreDestroy(pBattContext->hBattEventSem);
+        pBattContext->hBattEventSem = NULL;
+    }
+
+    if (pBattContext->hBattEventThread)
+    {
+        NvOdmOsThreadJoin(pBattContext->hBattEventThread);
+        pBattContext->hBattEventThread = NULL;
+    }
+
+    if (pBattContext->hEc)
+    {
+        if (pBattContext->hEcEventReg)
+        {
+            NvEcUnregisterForEvents(pBattContext->hEcEventReg);
+            pBattContext->hEcEventReg = NULL;
+        }
+
+        NvEcClose(pBattContext->hEc);
+        pBattContext->hEc = NULL;
+    }
+
+    if (pBattContext)
+        NvOdmOsFree(pBattContext);
+}
+
+/**
+ * Gets the AC line status.
+ *
+ * @param hDevice [IN] A handle to the EC.
+ * @param pStatus [OUT] A pointer to the AC line
+ *  status returned by the ODM.
+ *
+ * @return NV_TRUE if successful, or NV_FALSE otherwise.
+ */
+NvBool NvOdmBatteryGetAcLineStatus(
+       NvOdmBatteryDeviceHandle hDevice,
+       NvOdmBatteryAcLineStatus *pStatus)
+{
+#if NVEC_BATTERY_DISABLED
+    *pStatus = NvOdmBatteryAcLine_Online;
+#else
+    NvError NvStatus = NvError_Success;
+    NvEcRequest EcRequest = {0};
+    NvEcResponse EcResponse = {0};
+    NvU8 ACStatus = 0;
+    NvEcSystemGetStateResponsePayload SysQueryState;
+
+    NvOdmBatteryDevice *pBattContext = NULL;
+
+    NVODMBATTERY_PRINTF(("[ENTER] NvOdmBatteryGetAcLineStatus.\n"));
+
+    pBattContext = (NvOdmBatteryDevice *)hDevice;
+
+    /* For R01 EC Firware report AC is online as it has not support for this */
+    if (pBattContext->ECVersion == NVODM_BATTERY_EC_FIRMWARE_VER_R01)
+    {
+        *pStatus = NvOdmBatteryAcLine_Online;
+        return NV_TRUE;
+    }
+
+    /* Fill up request structure */
+    EcRequest.PacketType = NvEcPacketType_Request;
+    EcRequest.RequestType = NvEcRequestResponseType_System;
+    EcRequest.RequestSubtype = NvEcSystemSubtype_GetStatus;
+    EcRequest.NumPayloadBytes = 0;
+    EcRequest.Payload[0] = 0;
+
+    /* Request to EC */
+    NvStatus = NvEcSendRequest(pBattContext->hEc, &EcRequest, &EcResponse,
+                              sizeof(EcRequest), sizeof(EcResponse));
+    if (NvSuccess != NvStatus)
+    {
+        NVODMBATTERY_PRINTF(("NvEcSendRequest failed for \
+                              NvOdmBatteryGetAcLineStatus\n"));
+        *pStatus = NvOdmBatteryAcLine_Num;
+        return NV_FALSE;
+    }
+
+    if(EcResponse.Status == NvEcStatus_Success)
+    {
+        NvOdmOsMemcpy(&SysQueryState, EcResponse.Payload,
+                    EcResponse.NumPayloadBytes);
+
+        ACStatus = SysQueryState.State[NVODM_BATTERY_SYSTEM_STATE_DATA1];
+
+        /* AC is present or not */
+        if (ACStatus & NVODM_BATTERY_SYSTEM_STATE_AC_PRESENT)
+        {
+            *pStatus = NvOdmBatteryAcLine_Online;
+        }
+        else
+        {
+            *pStatus = NvOdmBatteryAcLine_Offline;
+        }
+    }
+
+    NVODMBATTERY_PRINTF(("[EXIT] NvOdmBatteryGetAcLineStatus.\n"));
+#endif /* end of NVEC_BATTERY_DISABLED */
+    return NV_TRUE;
+}
+
+/**
+ * Gets the battery status.
+ *
+ * @param hDevice [IN] A handle to the EC.
+ * @param BatteryInst [IN] The battery type.
+ * @param pStatus [OUT] A pointer to the battery
+ *  status returned by the ODM.
+ *
+ * @return NV_TRUE if successful, or NV_FALSE otherwise.
+ */
+NvBool NvOdmBatteryGetBatteryStatus(
+       NvOdmBatteryDeviceHandle hDevice,
+       NvOdmBatteryInstance BatteryInst,
+       NvU8 *pStatus)
+{
+#if NVEC_BATTERY_DISABLED
+    *pStatus = NVODM_BATTERY_STATUS_UNKNOWN;
+#else
+    NvU8  BatterySlotStatus = 0, BatteryCapacityGuage = 0,
+          BattPresentState = 0, BattChargingState = 0;
+    NvU32 BatteryVoltage = 0; /* in mV */
+    NvOdmBatteryDevice *pBattContext = NULL;
+
+    pBattContext = (NvOdmBatteryDevice *)hDevice;
+
+    NVODMBATTERY_PRINTF(("[ENTER] NvOdmBatteryGetBatteryStatus.\n"));
+
+    *pStatus = 0;
+
+    /*
+     * For R01 firmware Battery support is not present.
+     */
+    if (pBattContext->ECVersion == NVODM_BATTERY_EC_FIRMWARE_VER_R01)
+    {
+        *pStatus = NVODM_BATTERY_STATUS_UNKNOWN;
+         NVODMBATTERY_PRINTF(("NvOdmBatteryGetBatteryStatus:EC Firmware R01"));
+        return NV_TRUE;
+    }
+
+    if (BatteryInst == NvOdmBatteryInst_Main)
+    {
+        if(NvOdmBatteryPrivGetSlotStatusAndCapacityGuage(pBattContext,
+                                                NvOdmBatteryInst_Main,
+                                                &BatterySlotStatus,
+                                                &BatteryCapacityGuage))
+        {
+            BattPresentState = BatterySlotStatus & NVODM_BATTERY_PRESENT_IN_SLOT;
+            if (BattPresentState == NVODM_BATTERY_PRESENT_IN_SLOT)
+            {
+                BattChargingState = BatterySlotStatus >> NVODM_BATTERY_CHARGING_STATE_SHIFT;
+                BattChargingState &= NVODM_BATTERY_CHARGING_STATE_MASK;
+                if (BattChargingState == NVODM_BATTERY_CHARGING_STATE_CHARGING)
+                    *pStatus |= NVODM_BATTERY_STATUS_CHARGING;
+                else if  (BattChargingState == NVODM_BATTERY_CHARGING_STATE_DISCHARGING)
+                    *pStatus |= NVODM_BATTERY_STATUS_DISCHARGING;
+                else if  (BattChargingState == NVODM_BATTERY_CHARGING_STATE_IDLE)
+                    *pStatus |= NVODM_BATTERY_STATUS_IDLE;
+            }
+            else
+            {
+                *pStatus = NVODM_BATTERY_STATUS_NO_BATTERY;
+                return NV_TRUE;
+            }
+        }
+        else
+        {
+            *pStatus = NVODM_BATTERY_STATUS_UNKNOWN;
+            return NV_TRUE;
+        }
+
+        /* Get the battery voltage to detetmine the Battery Flag */
+        if (NvOdmPrivBattGetBatteryVoltage(pBattContext, NvOdmBatteryInst_Main,
+                                        &BatteryVoltage))
+        {
+            if (BatteryVoltage >= NVODM_BATTERY_HIGH_VOLTAGE_MV)
+                *pStatus |= NVODM_BATTERY_STATUS_HIGH;
+            else if (BatteryVoltage >= NVODM_BATTERY_LOW_VOLTAGE_MV)
+                *pStatus |= NVODM_BATTERY_STATUS_LOW;
+            else
+            {
+                *pStatus |= NVODM_BATTERY_STATUS_CRITICAL;
+                /*
+                 * Additional flag which tells battery is very critical
+                 * and needs system shutdown.
+                 */
+                if (BatteryVoltage <= NVODM_BATTERY_CRITICAL_VOLTAGE_MV)
+                    *pStatus |= NVODM_BATTERY_STATUS_VERY_CRITICAL;
+            }
+        }
+        else
+        {
+            *pStatus = NVODM_BATTERY_STATUS_UNKNOWN;
+            return NV_TRUE;
+        }
+    }
+    else
+    {
+        *pStatus = NVODM_BATTERY_STATUS_UNKNOWN;
+    }
+
+    NVODMBATTERY_PRINTF(("[EXIT] NvOdmBatteryGetBatteryStatus.\n"));
+#endif /* end of NVEC_BATTERY_DISABLED */
+    return NV_TRUE;
+}
+
+/**
+ * Gets the battery data.
+ *
+ * @param hDevice [IN] A handle to the EC.
+ * @param BatteryInst [IN] The battery type.
+ * @param pData [OUT] A pointer to the battery
+ *  data returned by the ODM.
+ *
+ * @return NV_TRUE if successful, or NV_FALSE otherwise.
+ */
+NvBool NvOdmBatteryGetBatteryData(
+       NvOdmBatteryDeviceHandle hDevice,
+       NvOdmBatteryInstance BatteryInst,
+       NvOdmBatteryData *pData)
+{
+    NvOdmBatteryData BatteryData;
+    NvU32 BatteryVoltage = 0, BatteryLifeTime = 0;
+    NvS32 BatteryCurrent = 0, BatteryAvgCurrent = 0;
+    NvU32 BatteryAvgTimeInterval = 0;
+    NvU32 BatteryTemp = 0;
+    NvU32 BattRemCap = 0, BattLastChargeFullCap = 0, BattCriticalCap = 0;
+#if BATTERY_EXTRA_INFO
+    NvU16 RemCapAlarm = 0;
+    NvU8 ConfigurationUnit = NVEC_BATTERY_CONFIGURATION_0_CAPACITY_UNITS_MAH;
+    NvU8 BattManufact[NVEC_MAX_RESPONSE_STRING_SIZE] = {0},
+         BattModel[NVEC_MAX_RESPONSE_STRING_SIZE] = {0};
+#endif
+    NvOdmBatteryDevice *pBattContext = NULL;
+    NvU8  BatterySlotStatus = 0, BatteryCapacityGuage = 0;
+
+    NVODMBATTERY_PRINTF(("[ENTER] NvOdmBatteryGetBatteryData.\n"));
+
+    pBattContext = (NvOdmBatteryDevice *)hDevice;
+
+    BatteryData.BatteryAverageCurrent  = NVODM_BATTERY_DATA_UNKNOWN;
+    BatteryData.BatteryAverageInterval = NVODM_BATTERY_DATA_UNKNOWN;
+    BatteryData.BatteryCurrent         = NVODM_BATTERY_DATA_UNKNOWN;
+    BatteryData.BatteryLifePercent     = NVODM_BATTERY_DATA_UNKNOWN;
+    BatteryData.BatteryLifeTime        = NVODM_BATTERY_DATA_UNKNOWN;
+    BatteryData.BatteryMahConsumed     = NVODM_BATTERY_DATA_UNKNOWN;
+    BatteryData.BatteryTemperature     = NVODM_BATTERY_DATA_UNKNOWN;
+    BatteryData.BatteryVoltage         = NVODM_BATTERY_DATA_UNKNOWN;
+    BatteryData.BatteryRemainingCapacity = NVODM_BATTERY_DATA_UNKNOWN;
+    BatteryData.BatteryLastChargeFullCapacity = NVODM_BATTERY_DATA_UNKNOWN;
+    BatteryData.BatteryCriticalCapacity = NVODM_BATTERY_DATA_UNKNOWN;
+
+    NV_ASSERT(hDevice);
+    NV_ASSERT(pData);
+    NV_ASSERT(BatteryInst <= NvOdmBatteryInst_Num);
+
+    if (BatteryInst == NvOdmBatteryInst_Main)
+    {
+        if (NvOdmPrivBattGetBatteryVoltage(pBattContext, NvOdmBatteryInst_Main,
+                                           &BatteryVoltage))
+        {
+            BatteryData.BatteryVoltage = BatteryVoltage;
+        }
+
+        if(NvOdmBatteryPrivGetSlotStatusAndCapacityGuage(pBattContext,
+           NvOdmBatteryInst_Main, &BatterySlotStatus, &BatteryCapacityGuage))
+        {
+            BatteryData.BatteryLifePercent = BatteryCapacityGuage;
+        }
+
+#if BATTERY_EXTRA_INFO
+        /* ConfigurationUnit = NVEC_BATTERY_CONFIGURATION_0_CAPACITY_UNITS_10MWH; */
+        NvOdmBatterySetConfiguration(pBattContext, NvOdmBatteryInst_Main, ConfigurationUnit);
+        NvOdmBatteryGetConfiguration(pBattContext, NvOdmBatteryInst_Main, &ConfigurationUnit);
+#endif
+
+        if(NvOdmBatteryPrivGetLifeTime(pBattContext, NvOdmBatteryInst_Main, &BatteryLifeTime))
+        {
+            BatteryData.BatteryLifeTime = BatteryLifeTime;
+        }
+
+        if(NvOdmBatteryPrivGetCurrent(pBattContext, NvOdmBatteryInst_Main,
+           &BatteryCurrent))
+        {
+            BatteryData.BatteryCurrent = BatteryCurrent;
+        }
+
+        if(NvOdmBatteryPrivGetAverageCurrent(pBattContext,
+           NvOdmBatteryInst_Main, &BatteryAvgCurrent))
+        {
+            BatteryData.BatteryAverageCurrent = BatteryAvgCurrent;
+        }
+
+        if(NvOdmBatteryPrivGetAverageTimeInterval(pBattContext,
+           NvOdmBatteryInst_Main, &BatteryAvgTimeInterval))
+        {
+            BatteryData.BatteryAverageInterval = BatteryAvgTimeInterval;
+        }
+
+        if(NvOdmBatteryPrivGetTemperature(pBattContext, NvOdmBatteryInst_Main,
+           &BatteryTemp))
+        {
+            BatteryData.BatteryTemperature = BatteryTemp;
+        }
+
+        if(NvOdmBatteryPrivGetRemainingCapacity(pBattContext,
+           NvOdmBatteryInst_Main, &BattRemCap))
+        {
+            BatteryData.BatteryRemainingCapacity = BattRemCap;
+        }
+
+        if(NvOdmBatteryPrivGetLastFullChargeCapacity(pBattContext,
+           NvOdmBatteryInst_Main, &BattLastChargeFullCap))
+        {
+            BatteryData.BatteryLastChargeFullCapacity = BattLastChargeFullCap;
+        }
+
+        if(NvOdmBatteryPrivGetCriticalCapacity(pBattContext,
+           NvOdmBatteryInst_Main, &BattCriticalCap))
+        {
+            BatteryData.BatteryCriticalCapacity = BattCriticalCap;
+        }
+
+#if BATTERY_EXTRA_INFO
+        /* RemCapAlarm = 0x0101;*/ /* Some random value */
+        NvOdmBatterySetRemCapacityAlarm(pBattContext, NvOdmBatteryInst_Main, RemCapAlarm);
+        RemCapAlarm = 0;
+        NvOdmBatteryGetRemCapacityAlarm(pBattContext, NvOdmBatteryInst_Main, &RemCapAlarm);
+
+        NvOdmBatteryGetManufacturer(pBattContext, NvOdmBatteryInst_Main, BattManufact);
+        NvOdmBatteryGetModel(pBattContext, NvOdmBatteryInst_Main, BattModel);
+#endif
+
+        *pData = BatteryData;
+    }
+    else
+    {
+        *pData = BatteryData;
+    }
+
+    NVODMBATTERY_PRINTF(("[EXIT] NvOdmBatteryGetBatteryData.\n"));
+#if NVEC_BATTERY_DISABLED
+    *pData = BatteryData;
+#endif
+    return NV_TRUE;
+}
+
+/**
+ * Gets the battery full life time.
+ *
+ * @param hDevice [IN] A handle to the EC.
+ * @param BatteryInst [IN] The battery type.
+ * @param pLifeTime [OUT] A pointer to the battery
+ *  full life time returned by the ODM.
+ *
+ */
+void NvOdmBatteryGetBatteryFullLifeTime(
+     NvOdmBatteryDeviceHandle hDevice,
+     NvOdmBatteryInstance BatteryInst,
+     NvU32 *pLifeTime)
+{
+#if NVEC_BATTERY_DISABLED
+    *pLifeTime = NVODM_BATTERY_DATA_UNKNOWN;
+#else
+    NvError NvStatus = NvError_Success;
+    NvEcRequest EcRequest = {0};
+    NvEcResponse EcResponse = {0};
+    NvEcBatteryGetDesignCapacityResponsePayload BatteryCapacity;
+    NvOdmBatteryDevice *pBattContext = NULL;
+
+    NVODMBATTERY_PRINTF(("[ENTER]NvOdmBatteryGetBatteryFullLifeTime.\n"));
+    *pLifeTime = NVODM_BATTERY_DATA_UNKNOWN;
+    pBattContext = (NvOdmBatteryDevice *)hDevice;
+
+    /* Fill up request structure */
+    EcRequest.PacketType = NvEcPacketType_Request;
+    EcRequest.RequestType = NvEcRequestResponseType_Battery;
+    EcRequest.RequestSubtype = NvEcBatterySubtype_GetDesignCapacity;
+    EcRequest.NumPayloadBytes = 0;
+    EcRequest.Payload[0] = 0;
+
+    /* Request to EC */
+    NvStatus = NvEcSendRequest(pBattContext->hEc, &EcRequest, &EcResponse,
+                              sizeof(EcRequest), sizeof(EcResponse));
+    if (NvSuccess != NvStatus)
+    {
+        NVODMBATTERY_PRINTF(("NvEcSendRequest failed for \
+                        NvOdmBatteryGetBatteryFullLifeTime\n"));
+    }
+    else
+    {
+        if(EcResponse.Status == NvEcStatus_Success)
+        {
+            NvOdmOsMemcpy(&BatteryCapacity, EcResponse.Payload,
+                        EcResponse.NumPayloadBytes);
+            *pLifeTime = BatteryCapacity.DesignCapacity[0];
+            *pLifeTime |= BatteryCapacity.DesignCapacity[1] << 8;
+        }
+    }
+
+    NVODMBATTERY_PRINTF(("[EXIT]NvOdmBatteryGetBatteryFullLifeTime.\n"));
+#endif /* end of NVEC_BATTERY_DISABLED */
+}
+
+
+/**
+ * Gets the battery chemistry.
+ *
+ * @param hDevice [IN] A handle to the EC.
+ * @param BatteryInst [IN] The battery type.
+ * @param pChemistry [OUT] A pointer to the battery
+ *  chemistry returned by the ODM.
+ *
+ */
+void NvOdmBatteryGetBatteryChemistry(
+     NvOdmBatteryDeviceHandle hDevice,
+     NvOdmBatteryInstance BatteryInst,
+     NvOdmBatteryChemistry *pChemistry)
+{
+#if NVEC_BATTERY_DISABLED
+    *pChemistry = NVODM_BATTERY_DATA_UNKNOWN;
+#else
+    NvError NvStatus = NvError_Success;
+    NvEcRequest EcRequest = {0};
+    NvEcResponse EcResponse = {0};
+    NvEcBatteryGetTypeResponsePayload BatteryType;
+
+    NvOdmBatteryDevice *pBattContext = NULL;
+
+    NVODMBATTERY_PRINTF(("[ENTER] NvOdmBatteryGetBatteryChemistry.\n"));
+    *pChemistry = NVODM_BATTERY_DATA_UNKNOWN;
+
+    pBattContext = (NvOdmBatteryDevice *)hDevice;
+
+    /* Fill up request structure */
+    EcRequest.PacketType = NvEcPacketType_Request;
+    EcRequest.RequestType = NvEcRequestResponseType_Battery;
+    EcRequest.RequestSubtype = NvEcBatterySubtype_GetType;
+    EcRequest.NumPayloadBytes = 0;
+    EcRequest.Payload[0] = 0;
+
+    /* Request to EC */
+    NvStatus = NvEcSendRequest(pBattContext->hEc, &EcRequest, &EcResponse,
+                              sizeof(EcRequest), sizeof(EcResponse));
+    if (NvSuccess != NvStatus)
+    {
+        NVODMBATTERY_PRINTF(("NvEcSendRequest failed for \
+                              NvOdmBatteryGetBatteryChemistry\n"));
+}
+    else
+    {
+        if(EcResponse.Status == NvEcStatus_Success)
+        {
+            NvOdmOsMemcpy(&BatteryType, EcResponse.Payload,
+                        EcResponse.NumPayloadBytes);
+
+            if(!NvOsStrncmp(BatteryType.Type, "LION",
+                            EcResponse.NumPayloadBytes))
+                *pChemistry = NvOdmBatteryChemistry_LION;
+            else if(!NvOsStrncmp(BatteryType.Type, "Alkaline",
+                                 EcResponse.NumPayloadBytes))
+                *pChemistry = NvOdmBatteryChemistry_Alkaline;
+            else if(!NvOsStrncmp(BatteryType.Type, "NICD",
+                                 EcResponse.NumPayloadBytes))
+                *pChemistry = NvOdmBatteryChemistry_NICD;
+            else if(!NvOsStrncmp(BatteryType.Type, "NIMH",
+                                 EcResponse.NumPayloadBytes))
+                *pChemistry = NvOdmBatteryChemistry_NIMH;
+            else if(!NvOsStrncmp(BatteryType.Type, "LIPOLY",
+                                 EcResponse.NumPayloadBytes))
+                *pChemistry = NvOdmBatteryChemistry_LIPOLY;
+            else if(!NvOsStrncmp(BatteryType.Type, "XINCAIR",
+                                 EcResponse.NumPayloadBytes))
+                *pChemistry = NvOdmBatteryChemistry_XINCAIR;
+        }
+    }
+
+    NVODMBATTERY_PRINTF(("[EXIT] NvOdmBatteryGetBatteryChemistry.\n"));
+#endif /* end of NVEC_BATTERY_DISABLED */
+}
diff --git a/arch/arm/mach-tegra/odm_kit/platform/battery/nvodm_battery_int.h b/arch/arm/mach-tegra/odm_kit/platform/battery/nvodm_battery_int.h
new file mode 100644
index 000000000000..3ec7313a0bd4
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/platform/battery/nvodm_battery_int.h
@@ -0,0 +1,181 @@
+/*
+ * Copyright (c) 2009-2010 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_NVODM_BATTERY_INT_H
+#define INCLUDED_NVODM_BATTERY_INT_H
+
+#include "nvodm_query_gpio.h"
+#include "nvrm_gpio.h"
+#include "nvodm_services.h"
+#include "nvec.h"
+
+/* Module debug msg: 0=disable, 1=enable */
+#define NVODMBATTERY_ENABLE_PRINTF (0)
+
+#if (NVODMBATTERY_ENABLE_PRINTF)
+#define NVODMBATTERY_PRINTF(x)   NvOdmOsDebugPrintf x
+#else
+#define NVODMBATTERY_PRINTF(x)
+#endif
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+/****************************************************************************/
+/*
+ * Macro to disable EC calls for battery operations
+ * until EC firware supports it
+ */
+#define NVEC_BATTERY_DISABLED 0
+/*
+ * Some extra battery info added which is not yet part of the
+ * BatteryData struct.
+ * Enable it to verify the these extra info with the EC firware
+ */
+#define BATTERY_EXTRA_INFO    0
+
+/* Enable to wakeup the AP from suspend */
+#define NVODM_WAKEUP_FROM_BATTERY_EVENT 1
+#define NVODM_WAKEUP_FROM_AC_EVENT      1
+
+/* Enable the Low Battery GPIO Interrupt */
+#define NVODM_LOWBATTERY_GPIO_INT       1
+
+/* Enable low capacity alarm wakeup */
+#define NVODM_BATTERY_LOW_CAPACITY_ALARM 1
+/****************************************************************************/
+
+#define NVODM_BATTERY_NUM_BATTERY_SLOTS_MASK 0x0F
+
+/* Battery Slot Status and Capacity Gauge Report */
+/* Data Byte 3 : Battery Slot Status */
+#define NVODM_BATTERY_SLOT_STATUS_DATA  0
+/*
+ * Data Byte 4 : Battery Capacity Gauge :
+ * Battery's relative remaining capacity in %
+ */
+#define NVODM_BATTERY_CAPACITY_GUAGE_DATA  1
+
+/*
+ * Battery Slot Status :
+ * Bit 0 = Present State:
+ * 1 = Battery is present in the respective slot
+ */
+#define NVODM_BATTERY_PRESENT_IN_SLOT  0x01
+
+#define NVODM_BATTERY_CHARGING_STATE_SHIFT  1
+#define NVODM_BATTERY_CHARGING_STATE_MASK   0x03
+
+/* Battery Slot Status : Bits 1-2 = Charging state */
+#define NVODM_BATTERY_CHARGING_STATE_IDLE         0x00
+#define NVODM_BATTERY_CHARGING_STATE_CHARGING     0x01
+#define NVODM_BATTERY_CHARGING_STATE_DISCHARGING  0x02
+#define NVODM_BATTERY_CHARGING_STATE_RESERVED     0x03
+
+/* Remaining capacity alarm bit is 3rd in slot status */
+#define NVODM_BATTERY_REM_CAP_ALARM_SHIFT 3
+#define NVODM_BATTERY_REM_CAP_ALARM_IS_SET 1
+
+/* Response System Status : Data Byte 3 System State Bits 7-0 */
+#define NVODM_BATTERY_SYSTEM_STATE_DATA1 0
+/* Response System Status : Data Byte 4 System State Bits 15-8 */
+#define NVODM_BATTERY_SYSTEM_STATE_DATA2 1
+/* System State Flags : AC Present : System State Bit 0 */
+#define NVODM_BATTERY_SYSTEM_STATE_AC_PRESENT 0x01
+
+#define NVODM_BATTERY_CHARGING_RATE_DATA_BYTES 3
+#define NVODM_BATTERY_CHARGING_RATE_UNIT 3
+
+/* Threshold for battery status.*/
+#define NVODM_BATTERY_FULL_VOLTAGE_MV      12600
+#define NVODM_BATTERY_HIGH_VOLTAGE_MV      10200
+#define NVODM_BATTERY_LOW_VOLTAGE_MV       10000
+#define NVODM_BATTERY_CRITICAL_VOLTAGE_MV   9500
+
+#define NVODM_BATTERY_EC_FIRMWARE_VER_R01 2
+#define NVODM_BATTERY_EC_FIRMWARE_VER_R04 8
+
+/* Bit 0 = Present State event */
+/* Bit 1 = Charging State event */
+/* Bit 2 = Remaining Capacity Alaram event */
+#define NVODM_BATTERY_SET_PRESENT_EVENT       0x01
+#define NVODM_BATTERY_SET_CHARGING_EVENT      0x02
+#define NVODM_BATTERY_SET_REM_CAP_ALARM_EVENT 0x04
+
+/*
+ * Bit 0   => 0=Not Present, 1=Present
+ * Bit 1:2 => 00=Idle, 01=Charging,10=Discharging, 11=Reserved
+ * Bit 3   => 1=Remaining Capacity Alaram set
+ */
+#define NVODM_BATTERY_EVENT_MASK 0x0F
+
+typedef enum
+{
+    NvOdmBattCharingUnit_mW, /* Milli Watt */
+    NvOdmBattCharingUnit_mA, /* Milli Amps */
+    NvOdmBattCharingUnit_10mW, /* Milli Watt * 10 */
+
+    NvOdmBattCharingUnit_Num,
+    NvOdmBattCharingUnit_Max = 0x7fffffff
+
+} NvOdmBattCharingUnit;
+
+typedef struct NvOdmBatteryDeviceRec
+{
+    NvEcHandle     hEc;
+    NvEcEventRegistrationHandle hEcEventReg;
+    NvOdmOsSemaphoreHandle      hBattEventSem;
+    NvOdmOsSemaphoreHandle      hClientBattEventSem;
+    NvOdmOsThreadHandle         hBattEventThread;
+#if NVODM_LOWBATTERY_GPIO_INT
+    const NvOdmGpioPinInfo      *pGpioPinInfo;
+    NvRmGpioPinHandle           hPin;
+    NvRmGpioInterruptHandle     GpioIntrHandle;
+    NvU32                       PinCount;
+    NvRmDeviceHandle            hRm;
+    NvRmGpioHandle              hGpio;
+#endif
+    NvU8                        BatteryEvent;
+    NvU8                        ECVersion;
+    NvBool                      ExitThread;
+} NvOdmBatteryDevice;
+
+#if defined(__cplusplus)
+}
+#endif
+
+/** @} */
+
+#endif /* INCLUDED_NVODM_BATTERY_INT_H */
+
diff --git a/arch/arm/mach-tegra/odm_kit/platform/battery/nvodm_battery_stub.c b/arch/arm/mach-tegra/odm_kit/platform/battery/nvodm_battery_stub.c
new file mode 100644
index 000000000000..63f51d9bdbd2
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/platform/battery/nvodm_battery_stub.c
@@ -0,0 +1,174 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include "nvcommon.h"
+#include "nvodm_battery.h"
+
+typedef struct NvOdmBatteryDeviceRec
+{
+    NvBool                      bBattPresent;
+    NvBool                      bBattFull;
+} NvOdmBatteryDevice;
+
+/**
+ * Gets the battery event.
+ *
+ * @param hDevice A handle to the EC.
+ * @param pBatteryEvent Battery events
+ * 
+ */
+void NvOdmBatteryGetEvent(
+     NvOdmBatteryDeviceHandle hDevice,
+     NvU8   *pBatteryEvent)
+{
+    NvOdmBatteryDevice *pBattContext = NULL;
+
+    pBattContext = (NvOdmBatteryDevice *)hDevice;
+
+    *pBatteryEvent = 0;
+}
+
+NvBool NvOdmBatteryDeviceOpen(NvOdmBatteryDeviceHandle *hDevice,
+                              NvOdmOsSemaphoreHandle *hOdmSemaphore)
+{
+    *hDevice = NULL;
+    return NV_FALSE;
+}
+
+void NvOdmBatteryDeviceClose(NvOdmBatteryDeviceHandle hDevice)
+{
+}
+
+/**
+ * Gets the AC line status.
+ *
+ * @param hDevice A handle to the EC.
+ * @param pStatus A pointer to the AC line
+ *  status returned by the ODM.
+ * 
+ * @return NV_TRUE if successful, or NV_FALSE otherwise.
+ */
+NvBool NvOdmBatteryGetAcLineStatus(
+       NvOdmBatteryDeviceHandle hDevice,
+       NvOdmBatteryAcLineStatus *pStatus)
+{
+    *pStatus = NvOdmBatteryAcLine_Offline;
+    return NV_FALSE;
+}
+
+
+/**
+ * Gets the battery status.
+ *
+ * @param hDevice A handle to the EC.
+ * @param batteryInst The battery type.
+ * @param pStatus A pointer to the battery
+ *  status returned by the ODM.
+ * 
+ * @return NV_TRUE if successful, or NV_FALSE otherwise.
+ */
+NvBool NvOdmBatteryGetBatteryStatus(
+       NvOdmBatteryDeviceHandle hDevice,
+       NvOdmBatteryInstance batteryInst,
+       NvU8 *pStatus)
+{
+    *pStatus = NVODM_BATTERY_STATUS_UNKNOWN;
+    return NV_FALSE;
+}
+
+/**
+ * Gets the battery data.
+ *
+ * @param hDevice A handle to the EC.
+ * @param batteryInst The battery type.
+ * @param pData A pointer to the battery
+ *  data returned by the ODM.
+ * 
+ * @return NV_TRUE if successful, or NV_FALSE otherwise.
+ */
+NvBool NvOdmBatteryGetBatteryData(
+       NvOdmBatteryDeviceHandle hDevice,
+       NvOdmBatteryInstance batteryInst,
+       NvOdmBatteryData *pData)
+{
+    NvOdmBatteryData BatteryData;
+
+    BatteryData.BatteryAverageCurrent  = NVODM_BATTERY_DATA_UNKNOWN;
+    BatteryData.BatteryAverageInterval = NVODM_BATTERY_DATA_UNKNOWN;
+    BatteryData.BatteryCurrent         = NVODM_BATTERY_DATA_UNKNOWN;
+    BatteryData.BatteryLifePercent     = NVODM_BATTERY_DATA_UNKNOWN;
+    BatteryData.BatteryLifeTime        = NVODM_BATTERY_DATA_UNKNOWN;
+    BatteryData.BatteryMahConsumed     = NVODM_BATTERY_DATA_UNKNOWN;
+    BatteryData.BatteryTemperature     = NVODM_BATTERY_DATA_UNKNOWN;
+    BatteryData.BatteryVoltage         = NVODM_BATTERY_DATA_UNKNOWN;
+
+    *pData = BatteryData;
+    return NV_FALSE;
+}
+
+/**
+ * Gets the battery full life time.
+ *
+ * @param hDevice A handle to the EC.
+ * @param batteryInst The battery type.
+ * @param pLifeTime A pointer to the battery
+ *  full life time returned by the ODM.
+ * 
+ */
+void NvOdmBatteryGetBatteryFullLifeTime(
+     NvOdmBatteryDeviceHandle hDevice,
+     NvOdmBatteryInstance batteryInst,
+     NvU32 *pLifeTime)
+{
+    *pLifeTime = NVODM_BATTERY_DATA_UNKNOWN;
+}
+
+
+/**
+ * Gets the battery chemistry.
+ *
+ * @param hDevice A handle to the EC.
+ * @param batteryInst The battery type.
+ * @param pChemistry A pointer to the battery
+ *  chemistry returned by the ODM.
+ * 
+ */
+void NvOdmBatteryGetBatteryChemistry(
+     NvOdmBatteryDeviceHandle hDevice,
+     NvOdmBatteryInstance batteryInst,
+     NvOdmBatteryChemistry *pChemistry)
+{
+    *pChemistry = NVODM_BATTERY_DATA_UNKNOWN;
+}
+
+
+
diff --git a/arch/arm/mach-tegra/odm_kit/platform/keyboard/Makefile b/arch/arm/mach-tegra/odm_kit/platform/keyboard/Makefile
new file mode 100644
index 000000000000..8f6e46d214c6
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/platform/keyboard/Makefile
@@ -0,0 +1,12 @@
+ccflags-y += -DNV_IS_AVP=0
+ccflags-y += -DNV_OAL=0
+ccflags-y += -DNV_USE_FUSE_CLOCK_ENABLE=0
+ifeq ($(CONFIG_MACH_TEGRA_GENERIC_DEBUG),y)
+ccflags-y += -DNV_DEBUG=1
+else
+ccflags-y += -DNV_DEBUG=0
+endif
+
+obj-$(CONFIG_TEGRA_ODM_HARMONY)		+= nvodm_keyboard.o
+obj-$(CONFIG_TEGRA_ODM_WHISTLER)	+= nvodm_keyboard_stub.o
+obj-$(CONFIG_TEGRA_ODM_CONCORDE)	+= nvodm_keyboard_stub.o
diff --git a/arch/arm/mach-tegra/odm_kit/platform/keyboard/nvodm_keyboard.c b/arch/arm/mach-tegra/odm_kit/platform/keyboard/nvodm_keyboard.c
new file mode 100644
index 000000000000..86ba9cbc6083
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/platform/keyboard/nvodm_keyboard.c
@@ -0,0 +1,485 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include "mach/nvrm_linux.h" // for s_hRmGlobal
+#include "nvodm_keyboard.h"
+#include "nvodm_query_discovery.h"
+#include "nvodm_services.h"
+#include "nvodm_query_gpio.h"
+#include "nvrm_gpio.h"
+#include "nvec.h"
+
+// Module debug: 0=disable, 1=enable
+#define NVODM_ENABLE_PRINTF      0
+
+#if NVODM_ENABLE_PRINTF
+#define NVODM_PRINTF(x) NvOdmOsDebugPrintf x
+#else
+#define NVODM_PRINTF(x)
+#endif
+
+// wake from keyboard disabled for now
+#define WAKE_FROM_KEYBOARD	1
+
+/* command main category */
+#define EC_KBC_COMMAND 0x5
+
+/* number of LEDS on the keyboard */
+enum {NUM_OF_LEDS = 3};
+
+/* Keyboard specific sub-commands */
+#define KBD_RESET_COMMAND 0xFF
+
+/* Special Scan Code set 1 codes */
+#define SC1_LSHIFT (0x2A)
+#define SC1_RSHIFT (0x36)
+#define SC1_SCROLL (0x46)
+#define SC1_PREFIX_E0 (0xE0)
+#define SC1_PREFIX_E1 (0xE1)
+
+/* Scan Code Set 1 break mask */
+#define SC1_BREAK_MASK (0x80)
+
+static NvEcHandle s_NvEcHandle = NULL;  // nvec handle
+NvEcEventType EventTypes[] = {NvEcEventType_Keyboard};  // get only keyboard events from EC
+NvEcEvent KbdEvent = {0};
+static NvOdmOsSemaphoreHandle s_hKbcKeyScanRecvSema = NULL;
+static NvEcEventRegistrationHandle s_hEcEventRegistration = NULL;
+static NvBool s_KeyboardDeinit = NV_FALSE;
+
+#if WAKE_FROM_KEYBOARD
+extern NvRmGpioHandle s_hGpioGlobal;
+#define DEBOUNCE_TIME_MS	5 /* GPIO debounce time in ms */
+typedef struct NvOdmKbdContextRec
+{
+	const NvOdmGpioPinInfo *GpioPinInfo;
+	NvRmGpioPinHandle hPin;
+	NvRmGpioInterruptHandle GpioIntrHandle;
+	NvU32 PinCount;
+} NvOdmKbdContext;
+NvOdmKbdContext *hOdm;
+
+static void GpioInterruptHandler(void *args)
+{
+	NvOdmKbdContext *Odm = (NvOdmKbdContext *)args;
+
+	if (Odm)
+	{
+		NvRmGpioInterruptDone(Odm->GpioIntrHandle);
+	}
+}
+
+#endif
+
+// Shadow LED state
+NvU8 s_LedState = 0;
+
+NvBool NvOdmKeyboardInit(void)
+{
+    NvError NvStatus = NvError_Success;
+    NvEcRequest Request = {0};
+    NvEcResponse Response = {0};
+
+    /* get nvec handle */
+    NvStatus = NvEcOpen(&s_NvEcHandle, 0 /* instance */);
+    if (NvStatus != NvError_Success)
+    {
+        goto fail;
+    }
+
+    /* reset the EC to start the keyboard scanning */
+    Request.PacketType = NvEcPacketType_Request;
+    Request.RequestType = NvEcRequestResponseType_Keyboard;
+    Request.RequestSubtype = (NvEcRequestResponseSubtype) NvEcKeyboardSubtype_Enable;
+    Request.NumPayloadBytes = 0;
+
+    NvStatus = NvEcSendRequest(s_NvEcHandle, &Request, &Response, sizeof(Request), sizeof(Response));
+    if (NvStatus != NvError_Success)
+    {
+        goto cleanup;
+    }
+
+    /* check if command passed */
+    if (Response.Status != NvEcStatus_Success)
+    {
+        goto cleanup;
+    }
+
+#if WAKE_FROM_KEYBOARD
+	hOdm = NvOdmOsAlloc(sizeof(NvOdmKbdContext));
+	if (!hOdm) {
+		goto cleanup;
+	}
+
+	/* Check the supported GPIOs */
+	hOdm->GpioPinInfo = NvOdmQueryGpioPinMap(NvOdmGpioPinGroup_WakeFromECKeyboard,
+					0,
+					&hOdm->PinCount);
+
+	NvRmGpioAcquirePinHandle(s_hGpioGlobal,
+		hOdm->GpioPinInfo->Port,
+		hOdm->GpioPinInfo->Pin,
+		&hOdm->hPin);
+	if (!hOdm->hPin) {
+		goto cleanup;
+	}
+
+	/* register to receive GPIO events */
+	NvStatus = NvRmGpioInterruptRegister(s_hGpioGlobal,
+		s_hRmGlobal,
+		hOdm->hPin,
+		(NvOsInterruptHandler)GpioInterruptHandler,
+		NvRmGpioPinMode_InputData,
+		hOdm,
+		&hOdm->GpioIntrHandle,
+		DEBOUNCE_TIME_MS);
+	if (NvStatus != NvError_Success) {
+		goto cleanup;
+	}
+
+	NvStatus = NvRmGpioInterruptEnable(hOdm->GpioIntrHandle);
+	if (NvStatus != NvError_Success) {
+		goto cleanup;
+	}
+
+	/* enable keyboard as wake up source */
+	Request.PacketType = NvEcPacketType_Request;
+	Request.RequestType = NvEcRequestResponseType_Keyboard;
+	Request.RequestSubtype = (NvEcRequestResponseSubtype)
+	NvEcKeyboardSubtype_ConfigureWake;
+	Request.NumPayloadBytes = 2;
+	Request.Payload[0] = NVEC_KEYBOARD_WAKE_ENABLE_0_ACTION_ENABLE;
+	Request.Payload[1] = NVEC_KEYBOARD_EVENT_TYPE_0_ANY_KEY_PRESS_ENABLE;
+
+	NvStatus = NvEcSendRequest(s_NvEcHandle,
+		&Request,
+		&Response,
+		sizeof(Request),
+		sizeof(Response));
+	if (NvStatus != NvError_Success) {
+		goto cleanup;
+        }
+
+	if (Response.Status != NvEcStatus_Success) {
+		goto cleanup;
+	}
+
+        /* enable key reporting on wake up */
+	Request.PacketType = NvEcPacketType_Request;
+	Request.RequestType = NvEcRequestResponseType_Keyboard;
+	Request.RequestSubtype = (NvEcRequestResponseSubtype)
+	NvEcKeyboardSubtype_ConfigureWakeKeyReport;
+	Request.NumPayloadBytes = 1;
+	Request.Payload[0] = NVEC_KEYBOARD_REPORT_WAKE_KEY_0_ACTION_ENABLE;
+
+	NvStatus = NvEcSendRequest(s_NvEcHandle,
+		&Request,
+		&Response,
+		sizeof(Request),
+		sizeof(Response));
+	if (NvStatus != NvError_Success) {
+		goto cleanup;
+        }
+
+	if (Response.Status != NvEcStatus_Success) {
+		goto cleanup;
+	}
+#endif
+
+    /* create semaphore which can be used to send scan codes to the clients */
+    s_hKbcKeyScanRecvSema = NvOdmOsSemaphoreCreate(0);
+    if (!s_hKbcKeyScanRecvSema)
+    {
+        goto cleanup;
+    }
+
+    /* register for keyboard events */
+    NvStatus = NvEcRegisterForEvents(
+                    s_NvEcHandle,       // nvec handle
+                    &s_hEcEventRegistration,
+                    (NvOsSemaphoreHandle)s_hKbcKeyScanRecvSema,
+                    sizeof(EventTypes)/sizeof(NvEcEventType),
+                    EventTypes, // receive keyboard scan codes
+                    1,          // currently buffer only 1 packet from ECI at a time
+                    sizeof(NvEcEvent));
+    if (NvStatus != NvError_Success)
+    {
+        goto cleanup;
+    }
+
+    /* success */
+    return NV_TRUE;
+
+cleanup:
+#if WAKE_FROM_KEYBOARD
+	NvRmGpioInterruptUnregister(s_hGpioGlobal, s_hRmGlobal, hOdm->GpioIntrHandle);
+	hOdm->GpioIntrHandle = NULL;
+	NvRmGpioReleasePinHandles(s_hGpioGlobal, &hOdm->hPin, hOdm->PinCount);
+	NvOdmOsFree(hOdm);
+	hOdm = NULL;
+#endif
+    (void)NvEcUnregisterForEvents(s_hEcEventRegistration);
+    s_hEcEventRegistration = NULL;
+
+    NvOdmOsSemaphoreDestroy(s_hKbcKeyScanRecvSema);
+    s_hKbcKeyScanRecvSema = NULL;
+
+    NvEcClose(s_NvEcHandle);
+fail:
+    s_NvEcHandle = NULL;
+
+    return NV_FALSE;
+}
+
+void NvOdmKeyboardDeInit(void)
+{
+#if WAKE_FROM_KEYBOARD
+	NvRmGpioInterruptUnregister(s_hGpioGlobal, s_hRmGlobal, hOdm->GpioIntrHandle);
+	hOdm->GpioIntrHandle = NULL;
+	NvRmGpioReleasePinHandles(s_hGpioGlobal, &hOdm->hPin, hOdm->PinCount);
+	hOdm->PinCount = 0;
+	NvOdmOsFree(hOdm);
+	hOdm = NULL;
+#endif
+
+    (void)NvEcUnregisterForEvents(s_hEcEventRegistration);
+    s_hEcEventRegistration = NULL;
+
+    s_KeyboardDeinit = NV_TRUE;
+    NvOdmOsSemaphoreSignal(s_hKbcKeyScanRecvSema);
+    NvOdmOsSemaphoreDestroy(s_hKbcKeyScanRecvSema);
+    s_hKbcKeyScanRecvSema = NULL;
+
+    NvEcClose(s_NvEcHandle);
+    s_NvEcHandle = NULL;
+}
+
+/* Gets the actual scan code for a key press */
+NvBool NvOdmKeyboardGetKeyData(NvU32 *pKeyScanCode, NvU8 *pScanCodeFlags, NvU32 Timeout)
+{
+    NvError NvStatus = NvError_Success;
+    NvU32 OutCode, OutCodeBytes, i;
+    NvU8 ScanCodeFlags;
+
+    if (!pKeyScanCode || !pScanCodeFlags || s_KeyboardDeinit)
+    {
+        return NV_FALSE;
+    }
+
+    if (Timeout != 0)
+    {
+        /* Use the timeout value */
+        if (!NvOdmOsSemaphoreWaitTimeout(s_hKbcKeyScanRecvSema, Timeout))
+            return NV_FALSE; // timed out
+    }
+    else
+    {
+        /* wait till we receive a scan code from the EC */
+        NvOdmOsSemaphoreWait(s_hKbcKeyScanRecvSema);
+    }
+
+    // stop scanning
+    if (s_KeyboardDeinit)
+        return NV_FALSE;
+
+    if (s_hEcEventRegistration)
+    {
+        NvStatus = NvEcGetEvent(s_hEcEventRegistration, &KbdEvent, sizeof(NvEcEvent));
+        if (NvStatus != NvError_Success)
+        {
+            NV_ASSERT(!"Could not receive scan code");
+            return NV_FALSE;
+        }
+        if (KbdEvent.NumPayloadBytes == 0)
+        {
+            NV_ASSERT(!"Received keyboard event with no scan codes");
+            return NV_FALSE;
+        }
+
+        // Pack scan code bytes from payload buffer into 32-bit dword
+        OutCode = (NvU32)KbdEvent.Payload[0];
+        OutCodeBytes = 1;
+        ScanCodeFlags = 0;
+
+        if (KbdEvent.NumPayloadBytes == 1)
+            NVODM_PRINTF(("EC Payload = 0x%x", KbdEvent.Payload[0]));
+        else
+        {
+            for (i = 0; i < KbdEvent.NumPayloadBytes; i++)
+                NVODM_PRINTF(("EC Payload = 0x%x", KbdEvent.Payload[i]));
+        }
+
+        for (i = 1; i < KbdEvent.NumPayloadBytes; i++)
+        {
+            if (KbdEvent.Payload[i-1] == SC1_PREFIX_E0)
+            {
+                // Temporary clear break flag just to check for extended shifts.
+                // If detected, remove the entire extended shift sequence, as
+                // it has no effect on SC1-to-VK translation
+                NvU8 sc = KbdEvent.Payload[i] & (~SC1_BREAK_MASK);
+                if ((sc == SC1_LSHIFT) || (sc == SC1_RSHIFT))
+                {
+                    OutCode = OutCode >> 8;
+                    OutCodeBytes--;
+                    continue;
+                }
+                else if (KbdEvent.Payload[i] == SC1_SCROLL)
+                {
+                    // If extended ScrollLock = Ctrl+Break, detected store it,
+                    // set both make/break flags, and abort buffer packing, as
+                    // the following bytes are just the break part of sequence
+                    OutCode = (OutCode << 8) | ((NvU32)KbdEvent.Payload[i]);
+                    OutCodeBytes++;
+                    ScanCodeFlags = NV_ODM_SCAN_CODE_FLAG_MAKE |
+                                    NV_ODM_SCAN_CODE_FLAG_BREAK;
+                    break;
+                }
+            }
+            if (KbdEvent.Payload[i] == SC1_PREFIX_E1)
+            {
+                // If 2nd half of Pause key is detected, set both make/break
+                // flags, and abort buffer packing, as the following bytes
+                // are just the break part of sequence
+                ScanCodeFlags = NV_ODM_SCAN_CODE_FLAG_MAKE |
+                                NV_ODM_SCAN_CODE_FLAG_BREAK;
+                break;
+            }
+            // If not intercepted by special cases, pack scan code byte into
+            // the output dword
+            OutCode = (OutCode << 8) | ((NvU32)KbdEvent.Payload[i]);
+            OutCodeBytes++;
+        }
+
+        // After above packing all SC1 sequences are shrinked to 1-3 byte
+        // scan codes; 3-byte scan code always has both make/break flags
+        // already set; 2- and 1- byte scan code have break flag in low byte
+        // of low word
+        if (!ScanCodeFlags)
+        {
+            switch (OutCodeBytes)
+            {
+                case 2:
+                case 1:
+                    ScanCodeFlags = (OutCode & ((NvU32)SC1_BREAK_MASK)) ?
+                                    NV_ODM_SCAN_CODE_FLAG_BREAK :
+                                    NV_ODM_SCAN_CODE_FLAG_MAKE;
+                    OutCode &= ~((NvU32)SC1_BREAK_MASK);
+                    break;
+
+                case 0:
+                    // Dummy sequence, no actual keystrokes (FIXME - assert ?)
+                    return NV_FALSE;
+
+                default:
+                    NV_ASSERT(!"Not an SC1 payload - failed to pack");
+                    return NV_FALSE;
+            }
+        }
+        *pScanCodeFlags = ScanCodeFlags;
+        *pKeyScanCode = OutCode;
+        return NV_TRUE;
+    }
+
+    return NV_FALSE;
+}
+
+NvBool NvOdmKeyboardToggleLights(NvU32 LedId)
+{
+    NvError NvStatus = NvError_Success;
+    NvEcRequest Request = {0};
+    NvEcResponse Response = {0};
+    NvU8 NewLedState[NUM_OF_LEDS] = {0}, i = 0;
+
+    /* return if EC handle is not available */
+    if (!s_NvEcHandle)
+        return NV_FALSE;
+
+    /* get the current state for each LED and toggle it */
+    for (i = 0; i < NUM_OF_LEDS; i++)
+    {
+        NewLedState[i] = s_LedState & (LedId & (1 << i));
+
+        if (LedId & (1 << i))
+        {
+            NewLedState[i] = (~NewLedState[i]) & 0x1;
+        }
+    }
+
+    /* update the new LED states to be programmed */
+    s_LedState = 0;
+    for (i = 0; i < NUM_OF_LEDS; i++)
+    {
+        s_LedState |= (NewLedState[i] << i);
+    }
+
+    NVODM_PRINTF(("NvOdmKeyboardToggleLights: LED State = 0x%x", s_LedState));
+
+    /* issue the Set LED command */
+    Request.PacketType = NvEcPacketType_Request;
+    Request.RequestType = NvEcRequestResponseType_Keyboard;
+    Request.RequestSubtype = (NvEcRequestResponseSubtype) NvEcKeyboardSubtype_SetLeds;
+    Request.NumPayloadBytes = 1;
+    Request.Payload[0] = (NvU8)s_LedState;
+
+    NvStatus = NvEcSendRequest(s_NvEcHandle, &Request, &Response, sizeof(Request), sizeof(Response));
+    if (NvStatus != NvError_Success)
+    {
+        NVODM_PRINTF(("NvOdmKeyboardToggleLights: NvEcSendRequest time out"));
+        return NV_FALSE;
+    }
+
+    /* check if command passed */
+    if (Response.Status != NvEcStatus_Success)
+    {
+        return NV_FALSE;
+    }
+
+    return NV_TRUE;
+}
+
+NvBool NvOdmKeyboardPowerHandler(NvBool PowerDown)
+{
+    return NV_TRUE;
+}
+
+/* -----------Stub Implemetation for Hold Switch Adaptation, since we do not need these-------*/
+
+NvBool NvOdmHoldSwitchInit(void)
+{
+    // firefly should not concerned about the "hold" key
+    return NV_FALSE;
+}
+
+void NvOdmHoldSwitchDeInit(void)
+{
+    // do nothing
+}
diff --git a/arch/arm/mach-tegra/odm_kit/platform/keyboard/nvodm_keyboard_stub.c b/arch/arm/mach-tegra/odm_kit/platform/keyboard/nvodm_keyboard_stub.c
new file mode 100644
index 000000000000..7779766c97ba
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/platform/keyboard/nvodm_keyboard_stub.c
@@ -0,0 +1,70 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include "nvodm_keyboard.h"
+
+
+NvBool NvOdmKeyboardInit(void)
+{
+    return NV_FALSE;
+}
+
+void NvOdmKeyboardDeInit(void)
+{
+}
+
+NvBool NvOdmKeyboardGetKeyData(NvU32 *KeyScanCode, NvBool *IsKeyUp, NvU32 Timeout)
+{
+    return NV_FALSE;
+}
+
+NvBool NvOdmKeyboardToggleLights(NvU32 LedId)
+{
+    return NV_FALSE;
+}
+
+NvBool NvOdmKeyboardPowerHandler(NvBool PowerDown)
+{
+    return NV_FALSE;
+}
+
+/* -----------Implemetation for Hold Switch Adaptation starts here-------*/
+
+NvBool NvOdmHoldSwitchInit(void)
+{
+    return NV_FALSE;
+}
+
+void NvOdmHoldSwitchDeInit(void)
+{
+}
+
diff --git a/arch/arm/mach-tegra/odm_kit/platform/mouse/Makefile b/arch/arm/mach-tegra/odm_kit/platform/mouse/Makefile
new file mode 100644
index 000000000000..a8897024bf2c
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/platform/mouse/Makefile
@@ -0,0 +1,10 @@
+ccflags-y += -DNV_IS_AVP=0
+ccflags-y += -DNV_OAL=0
+ccflags-y += -DNV_USE_FUSE_CLOCK_ENABLE=0
+ifeq ($(CONFIG_MACH_TEGRA_GENERIC_DEBUG),y)
+ccflags-y += -DNV_DEBUG=1
+else
+ccflags-y += -DNV_DEBUG=0
+endif
+
+obj-$(CONFIG_TEGRA_ODM_HARMONY)		+= nvodm_mouse.o
diff --git a/arch/arm/mach-tegra/odm_kit/platform/mouse/nvodm_mouse.c b/arch/arm/mach-tegra/odm_kit/platform/mouse/nvodm_mouse.c
new file mode 100644
index 000000000000..a527ea540d55
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/platform/mouse/nvodm_mouse.c
@@ -0,0 +1,586 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+#include "nvodm_mouse.h"
+#include "nvodm_mouse_int.h"
+#include "nvrm_drf.h"
+
+// Module debug: 0=disable, 1=enable
+#define NVODM_ENABLE_PRINTF      0
+
+#if NVODM_ENABLE_PRINTF
+#define NVODM_PRINTF(x) NvOdmOsDebugPrintf x
+#else
+#define NVODM_PRINTF(x)
+#endif
+
+// wake from mouse disabled for now
+#define WAKE_FROM_MOUSE 1
+
+/**
+ * streaming data from mouse can be compressed if (uncompressed) packet size is
+ * 3 bytes (as it is for all legacy ps2 mice).  Compression works by not sending
+ * the first byte of the packet when it hasn't change.
+ */
+
+#define ENABLE_COMPRESSION 1
+
+#define ECI_MOUSE_DISABLE_SUPPORTED 1
+
+#define MAX_PAYLOAD_BYTES 32
+
+/**
+ * specify the ps2 port where the mouse is connected
+ */
+#define MOUSE_PS2_PORT_ID_0 NVEC_SUBTYPE_0_AUX_PORT_ID_0
+#define MOUSE_PS2_PORT_ID_1 NVEC_SUBTYPE_0_AUX_PORT_ID_1
+
+/** Implementation for the NvOdm Mouse */
+
+NvBool
+NvOdmMouseDeviceOpen(
+    NvOdmMouseDeviceHandle *hDevice)
+{
+    NvOdmMouseDevice *hMouseDev = NULL;
+    NvBool ret = NV_FALSE;
+    NvU32 InstanceId = 0, count = 0, MousePort = 0, i = 0;
+#if WAKE_FROM_MOUSE
+    NvError err = NvError_Success;
+    NvEcRequest Request = {0};
+    NvEcResponse Response = {0};
+#endif
+
+    // Allocate memory for request type structure
+    hMouseDev = (NvOdmMouseDevice *)NvOdmOsAlloc(sizeof(NvOdmMouseDevice));
+    if (!hMouseDev)
+    {
+        ret = NV_FALSE;
+        NVODMMOUSE_PRINTF(("NvOdmOsAlloc failed to allocate hMouseDev!!"));
+        goto fail_safe;
+    }
+    NvOdmOsMemset(hMouseDev, 0, sizeof(NvOdmMouseDevice));
+
+    // open channel to the EC
+    if ((NvEcOpen(&hMouseDev->hEc, InstanceId)) != NvSuccess)
+    {
+        ret = NV_FALSE;
+        NVODMMOUSE_PRINTF(("NvEcOpen failed !!"));
+        goto fail_safe;
+    }
+
+    hMouseDev->pRequest = NULL;
+    hMouseDev->pResponse = NULL;
+    hMouseDev->pEvent = NULL;
+    hMouseDev->CompressionEnabled = NV_FALSE;
+    hMouseDev->CompressionState = 0x0;
+
+    do
+    {
+        hMouseDev->ValidMousePorts[count] = INVALID_MOUSE_PORT_ID;
+        count++;
+    } while (count <= MAX_NUM_MOUSE_PORTS);
+
+    // Allocate memory for request type structure
+    hMouseDev->pRequest = NvOdmOsAlloc(sizeof(NvEcRequest));
+    if (!hMouseDev->pRequest)
+    {
+        ret = NV_FALSE;
+        NVODMMOUSE_PRINTF(("NvOdmOsAlloc failed to allocate pRequest!!"));
+        goto fail_safe;
+    }
+    NvOdmOsMemset(hMouseDev->pRequest, 0, sizeof(NvEcRequest));
+
+    // Allocate memory for response type structure
+    hMouseDev->pResponse = NvOdmOsAlloc(sizeof(NvEcResponse));
+    if (!hMouseDev->pResponse)
+    {
+        ret = NV_FALSE;
+        NVODMMOUSE_PRINTF(("NvOdmOsAlloc failed to allocate pResponse!!"));
+        goto fail_safe;
+    }
+    NvOdmOsMemset(hMouseDev->pResponse, 0, sizeof(NvEcResponse));
+
+    // Allocate memory for event type structure
+    hMouseDev->pEvent = NvOdmOsAlloc(sizeof(NvEcEvent));
+    if (!hMouseDev->pEvent)
+    {
+        ret = NV_FALSE;
+        NVODMMOUSE_PRINTF(("NvOdmOsAlloc failed to allocate pEvent!!"));
+        goto fail_safe;
+    }
+    NvOdmOsMemset(hMouseDev->pEvent, 0, sizeof(NvEcEvent));
+
+    MousePort = MOUSE_PS2_PORT_ID_0;
+    count = CMD_MAX_RETRIES + 1; i = 0;
+    while (count--)
+    {
+        // fill up request structure
+        Request.PacketType = NvEcPacketType_Request;
+        Request.RequestType = NvEcRequestResponseType_AuxDevice;
+        Request.RequestSubtype = 
+            ((NvEcRequestResponseSubtype) 
+             (NV_DRF_NUM(NVEC,SUBTYPE,AUX_PORT_ID,MousePort))) |
+            ((NvEcRequestResponseSubtype) 
+             NvEcAuxDeviceSubtype_SendCommand);
+        Request.NumPayloadBytes = 2;
+        Request.Payload[0] = 0xFF; // set the reset command
+        Request.Payload[1] = 3;
+
+        // Request to EC
+        err = NvEcSendRequest(hMouseDev->hEc, &Request, &Response, sizeof(Request),
+                        sizeof(Response));
+
+        if (NvSuccess != err)
+        {
+            NVODMMOUSE_PRINTF(("NvEcSendRequest failed !!"));
+            break;
+        }
+
+        // mouse not found
+        if (NvEcStatus_Success != Response.Status)
+        {
+            NVODMMOUSE_PRINTF(("EC response failed !!"));
+            if (MousePort != MOUSE_PS2_PORT_ID_1)
+            {
+                count = CMD_MAX_RETRIES + 1;
+                MousePort = MOUSE_PS2_PORT_ID_1;
+                continue;
+            }
+            break;
+        }
+
+        if (Response.NumPayloadBytes != 3)
+            continue;
+
+        // success
+        if (Response.Payload[0] == 0xFA)
+        {
+            hMouseDev->ValidMousePorts[i] = MousePort;
+            if (MousePort != MOUSE_PS2_PORT_ID_1)
+            {
+                count = CMD_MAX_RETRIES + 1;
+                MousePort = MOUSE_PS2_PORT_ID_1;
+                i++;
+                continue;
+            }
+            break;
+        }
+    }
+
+#if WAKE_FROM_MOUSE
+    i = 0;
+    do
+    {
+        /* enable mouse as wake up source */
+        Request.PacketType = NvEcPacketType_Request;
+        Request.RequestType = NvEcRequestResponseType_AuxDevice;
+        Request.RequestSubtype = ((NvEcRequestResponseSubtype) 
+             (NV_DRF_NUM(NVEC,SUBTYPE,AUX_PORT_ID,hMouseDev->ValidMousePorts[i]))) |
+             (NvEcRequestResponseSubtype)
+             NvEcAuxDeviceSubtype_ConfigureWake;
+        Request.NumPayloadBytes = 2;
+        Request.Payload[0] = NVEC_AUX_DEVICE_WAKE_ENABLE_0_ACTION_ENABLE;
+        Request.Payload[1] = NVEC_AUX_DEVICE_EVENT_TYPE_0_ANY_EVENT_ENABLE;
+
+        err = NvEcSendRequest(
+                    hMouseDev->hEc,
+                    &Request,
+                    &Response,
+                    sizeof(Request),
+                    sizeof(Response));
+        if (err != NvError_Success)
+        {
+            ret = NV_FALSE;
+            goto fail_safe;
+        }
+
+        if (Response.Status != NvEcStatus_Success)
+        {
+            ret = NV_FALSE;
+            goto fail_safe;
+        }
+    } while (hMouseDev->ValidMousePorts[++i] != INVALID_MOUSE_PORT_ID);
+#endif
+
+    *hDevice = (NvOdmMouseDeviceHandle)hMouseDev;
+    ret = NV_TRUE;
+    return ret;
+
+fail_safe:
+    NvOdmMouseDeviceClose((NvOdmMouseDeviceHandle)hMouseDev);
+    hMouseDev = NULL;
+    return ret;
+}
+
+void
+NvOdmMouseDeviceClose(
+    NvOdmMouseDeviceHandle hDevice)
+{
+    if (hDevice)
+    {
+        // close channel to the EC
+        NvEcClose(hDevice->hEc);
+        hDevice->hEc = NULL;
+        // Free the request/response structure objects
+        NvOdmOsFree(hDevice->pRequest);
+        hDevice->pRequest = NULL;
+        NvOdmOsFree(hDevice->pResponse);
+        hDevice->pResponse = NULL;
+        NvOdmOsFree(hDevice->pEvent);
+        hDevice->pEvent = NULL;
+        NvOdmOsFree(hDevice);
+        hDevice = NULL;
+    }
+}
+
+NvBool NvOdmMouseEnableInterrupt(
+    NvOdmMouseDeviceHandle hDevice, 
+    NvOdmOsSemaphoreHandle hInterruptSemaphore)
+{
+    NvError Status = NvSuccess;
+    NvEcEventType EventTypes[] = {
+        (NvEcEventType) (NvEcEventType_AuxDevice0 + MOUSE_PS2_PORT_ID_0),
+        (NvEcEventType) (NvEcEventType_AuxDevice0 + MOUSE_PS2_PORT_ID_1)
+    };
+
+    Status = NvEcRegisterForEvents(
+        hDevice->hEc,
+        &hDevice->hEcEventRegister,
+        (NvOsSemaphoreHandle)hInterruptSemaphore,
+        NV_ARRAY_SIZE(EventTypes), // number of EventType's
+        EventTypes,                // Auxillary 0 event
+        1,                         // One event packet is expected
+        // event packet size = packet overhead + size of the mouse sample;
+        // max sample size is 4 bytes (for an Intellimouse 5-button mouse)
+        NVEC_MIN_EVENT_SIZE+4); 
+
+    if (Status != NvSuccess)
+        return NV_FALSE;
+
+    return NV_TRUE;
+}
+
+NvBool
+NvOdmMouseDisableInterrupt(
+    NvOdmMouseDeviceHandle hDevice)
+{
+    NvError Status = NvSuccess;
+
+    // Un-register the events
+    Status = NvEcUnregisterForEvents(hDevice->hEcEventRegister);
+    if (Status != NvSuccess)
+        return NV_FALSE;
+
+    return NV_TRUE;
+}
+
+NvBool NvOdmMouseGetEventInfo(
+    NvOdmMouseDeviceHandle hDevice,
+    NvU32 *NumPayLoad,
+    NvU8 *PayLoadBuf)
+{
+    NvError Status = NvSuccess;
+
+    // Retrive the event info
+    Status = NvEcGetEvent(hDevice->hEcEventRegister,
+                          hDevice->pEvent,
+                          sizeof(NvEcEvent));
+
+    if (Status != NvSuccess)
+        return NV_FALSE;
+
+    /**
+     * if compression is enabled, latch the first data byte whenever a full-size
+     * packet is received; then insert the latched data whenever a compressed
+     * packet is seen.
+     */
+    if (hDevice->CompressionEnabled && hDevice->pEvent->NumPayloadBytes == 3)
+    {
+        hDevice->CompressionState = hDevice->pEvent->Payload[0];
+    }
+    
+    /**
+     * fill in the payload and number of bytes
+     */
+    if (hDevice->CompressionEnabled && hDevice->pEvent->NumPayloadBytes == 2)
+    {
+        // compressed packet, so insert latched data at beginning
+        *NumPayLoad = 3;
+        PayLoadBuf[0] = hDevice->CompressionState;
+        PayLoadBuf[1] = hDevice->pEvent->Payload[0];
+        PayLoadBuf[2] = hDevice->pEvent->Payload[1];
+    }
+    else
+    {
+        *NumPayLoad = hDevice->pEvent->NumPayloadBytes;
+        NvOdmOsMemcpy(PayLoadBuf, hDevice->pEvent->Payload, *NumPayLoad);
+    }
+
+    return NV_TRUE;
+}
+
+NvBool
+NvOdmMouseSendRequest(
+    NvOdmMouseDeviceHandle hDevice, 
+    NvU32 cmd, 
+    NvU32 ExpectedResponseSize,
+    NvU32 *NumPayLoad, 
+    NvU8 *PayLoadBuf)
+{
+    NvError e;
+    NvEcRequest *pRequest = hDevice->pRequest;
+    NvEcResponse *pResponse = hDevice->pResponse;
+    NvU32 Index = 0;
+
+    do
+    {
+        // fill up request structure
+        pRequest->PacketType = NvEcPacketType_Request;
+        pRequest->RequestType = NvEcRequestResponseType_AuxDevice;
+        pRequest->RequestSubtype = 
+            ((NvEcRequestResponseSubtype) 
+             (NV_DRF_NUM(NVEC,SUBTYPE,AUX_PORT_ID,hDevice->ValidMousePorts[Index]))) |
+            ((NvEcRequestResponseSubtype) 
+             NvEcAuxDeviceSubtype_SendCommand);
+        pRequest->NumPayloadBytes = 2;
+        pRequest->Payload[0] = cmd; // set the command
+        pRequest->Payload[1] = ExpectedResponseSize;
+
+        // Request to EC
+        e = NvEcSendRequest(hDevice->hEc, pRequest, pResponse, sizeof(*pRequest),
+                        sizeof(*pResponse));
+        
+        if (NvSuccess != e)
+        {
+            NVODMMOUSE_PRINTF(("NvEcSendRequest failed !!"));
+            return NV_FALSE;
+        }
+
+        if (NvEcStatus_Success != pResponse->Status)
+        {
+            NVODMMOUSE_PRINTF(("EC response failed !!"));
+            return NV_FALSE;
+        }
+
+        // store/process the Mouse response and return to the client driver
+        *NumPayLoad = pResponse->NumPayloadBytes;
+        NvOdmOsMemcpy(PayLoadBuf, &pResponse->Payload, *NumPayLoad);
+    } while (hDevice->ValidMousePorts[++Index] != INVALID_MOUSE_PORT_ID);
+
+    return NV_TRUE;
+}
+
+NvBool
+NvOdmMouseStartStreaming(
+    NvOdmMouseDeviceHandle hDevice,
+    NvU32 NumBytesPerSample)
+{
+    NvError e;
+    NvEcRequest *pRequest = hDevice->pRequest;
+    NvEcResponse *pResponse = hDevice->pResponse;
+    NvU32 Index = 0;
+
+    if (!hDevice)
+        return NV_FALSE;
+
+    hDevice->NumBytesPerSample = NumBytesPerSample;
+
+#if ENABLE_COMPRESSION
+    /**
+     * automatically enable compression if sample size is 3 bytes
+     *
+     * compression is supported only for 3-byte data packets (which is the
+     * common case for ps/2 mice and mouses
+     *
+     * compression reduces communication bandwidth by eliminating the first data
+     * byte of the packet when it hasn't changed relative to the previous
+     * packet.  Whenever a full-sized packet is sent, the first payload byte is
+     * latched so that it can be inserted into an n y following compressed packets.
+     */
+
+    if (NumBytesPerSample == 3)
+    {
+        do
+        {
+            // prepare Aux Device request for Set Compression
+            pRequest->PacketType = NvEcPacketType_Request;
+            pRequest->RequestType = NvEcRequestResponseType_AuxDevice;
+            pRequest->RequestSubtype = 
+                ((NvEcRequestResponseSubtype) 
+                 (NV_DRF_NUM(NVEC,SUBTYPE,AUX_PORT_ID,hDevice->ValidMousePorts[Index]))) |
+                ((NvEcRequestResponseSubtype) 
+                 NvEcAuxDeviceSubtype_SetCompression);
+            pRequest->NumPayloadBytes = 1; 
+            pRequest->Payload[0] = 1; // enable compression
+
+            // send request to EC
+            e = NvEcSendRequest(hDevice->hEc, pRequest, pResponse, sizeof(*pRequest),
+                                sizeof(*pResponse));
+
+            if (NvSuccess != e)
+            {
+                NVODMMOUSE_PRINTF(("NvEcSendRequest (compression) failed !!"));
+                return NV_FALSE;
+            }
+
+            // check status reported by EC
+            if (NvEcStatus_Success != pResponse->Status)
+            {
+                NVODMMOUSE_PRINTF(("EC response (compression) failed !!"));
+                return NV_FALSE;
+            }
+        } while(hDevice->ValidMousePorts[++Index] != INVALID_MOUSE_PORT_ID);
+
+        hDevice->CompressionEnabled = NV_TRUE;
+        hDevice->CompressionState = 0x0;
+    }
+    else
+    {
+        // compression not supported due to packet size (!= 3 bytes)
+        hDevice->CompressionEnabled = NV_FALSE;
+    }
+#else // ENABLE_COMPRESSION
+    // disable compression
+    hDevice->CompressionEnabled = NV_FALSE;
+#endif // ENABLE_COMPRESSION
+
+    // prepare Aux Device request for Auto-Receive N Bytes
+    Index = 0;
+    do
+    {
+        pRequest->PacketType = NvEcPacketType_Request;
+        pRequest->RequestType = NvEcRequestResponseType_AuxDevice;
+        pRequest->RequestSubtype = 
+            ((NvEcRequestResponseSubtype) 
+             (NV_DRF_NUM(NVEC,SUBTYPE,AUX_PORT_ID,hDevice->ValidMousePorts[Index]))) |
+            ((NvEcRequestResponseSubtype) 
+             NvEcAuxDeviceSubtype_AutoReceiveBytes);
+        pRequest->NumPayloadBytes = 1; 
+        pRequest->Payload[0] = NumBytesPerSample;
+
+        // send request to EC
+        e = NvEcSendRequest(hDevice->hEc, pRequest, pResponse, sizeof(*pRequest),
+                        sizeof(*pResponse));
+
+        if (NvSuccess != e)
+        {
+            NVODMMOUSE_PRINTF(("NvEcSendRequest (auto-receive) failed !!"));
+            return NV_FALSE;
+        }
+
+        // check status reported by EC
+        if (NvEcStatus_Success != pResponse->Status)
+        {
+            NVODMMOUSE_PRINTF(("EC response (auto-receive) failed !!"));
+            return NV_FALSE;
+        }
+    } while(hDevice->ValidMousePorts[++Index] != INVALID_MOUSE_PORT_ID);
+
+    return NV_TRUE;
+}
+
+/**
+ *  Power suspend for mouse.
+ *
+ */
+NvBool NvOdmMousePowerSuspend(NvOdmMouseDeviceHandle hDevice)
+{
+#if ECI_MOUSE_DISABLE_SUPPORTED
+    NvError e;
+    NvEcRequest *pRequest = hDevice->pRequest;
+    NvEcResponse *pResponse = hDevice->pResponse;
+    NvU32 Index = 0;
+
+    if (!hDevice || !pRequest || !pResponse)
+        return NV_FALSE;
+
+    NV_ASSERT(hDevice->hEc);
+    NV_ASSERT(hDevice->pRequest);
+    NV_ASSERT(hDevice->pResponse);
+
+    // cancel auto-receive (disables event reporting)
+
+    NVODM_PRINTF(("NvOdmMousePowerSuspend: Cancel Auto Receive\n"));
+
+    do
+    {
+        // fill up request structure
+        pRequest->PacketType = NvEcPacketType_Request;
+        pRequest->RequestType = NvEcRequestResponseType_AuxDevice;
+        pRequest->RequestSubtype = 
+            ((NvEcRequestResponseSubtype) 
+             (NV_DRF_NUM(NVEC,SUBTYPE,AUX_PORT_ID,hDevice->ValidMousePorts[Index]))) |
+            ((NvEcRequestResponseSubtype) 
+             NvEcAuxDeviceSubtype_CancelAutoReceive);
+        pRequest->NumPayloadBytes = 0;
+
+        // Request to EC
+        e = NvEcSendRequest(hDevice->hEc, pRequest, pResponse, sizeof(*pRequest),
+                        sizeof(*pResponse));
+        
+        if (NvSuccess != e)
+        {
+            NVODMMOUSE_PRINTF(("NvOdmMousePowerSuspend: NvEcSendRequest failed !!"));
+            return NV_FALSE;
+        }
+
+        if (NvEcStatus_Success != pResponse->Status)
+        {
+            NVODMMOUSE_PRINTF(("NvOdmMousePowerSuspend: EC response failed !!"));
+            return NV_FALSE;
+        }
+     } while(hDevice->ValidMousePorts[++Index] != INVALID_MOUSE_PORT_ID);
+#endif
+    NVODM_PRINTF(("NvOdmMousePowerSuspend: Exit success\n"));
+
+    return NV_TRUE;
+}
+
+/**
+ *  Power resume for mouse.
+ *
+ */
+NvBool NvOdmMousePowerResume(NvOdmMouseDeviceHandle hDevice)
+{
+#if ECI_MOUSE_DISABLE_SUPPORTED
+    if (!hDevice)
+        return NV_FALSE;
+
+    NVODM_PRINTF(("NvOdmMousePowerResume: Start Streaming\n"));
+
+    if (!NvOdmMouseStartStreaming(hDevice, hDevice->NumBytesPerSample))
+        return NV_FALSE;
+#endif
+    NVODM_PRINTF(("NvOdmMousePowerResume: Exit success\n"));
+
+    return NV_TRUE;
+}
+
diff --git a/arch/arm/mach-tegra/odm_kit/platform/mouse/nvodm_mouse_int.h b/arch/arm/mach-tegra/odm_kit/platform/mouse/nvodm_mouse_int.h
new file mode 100644
index 000000000000..2e3a6cc8b71a
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/platform/mouse/nvodm_mouse_int.h
@@ -0,0 +1,78 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_NVODM_MOUSE_INT_H
+#define INCLUDED_NVODM_MOUSE_INT_H
+
+#include "nvodm_services.h"
+#include "nvodm_touch.h"
+#include "nvec.h"
+
+// Module debug: 0=disable, 1=enable
+#define NVODMMOUSE_ENABLE_PRINTF (0)
+
+#define MAX_NUM_MOUSE_PORTS       4
+#define INVALID_MOUSE_PORT_ID     0xF
+#define CMD_MAX_RETRIES           3
+
+#if (NVODMMOUSE_ENABLE_PRINTF)
+#define NVODMMOUSE_PRINTF(x)   NvOdmOsDebugPrintf x
+#else
+#define NVODMMOUSE_PRINTF(x)
+#endif
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+typedef struct NvOdmMouseDeviceRec
+{
+    NvEcHandle                  hEc;
+    NvEcRequest                 *pRequest;
+    NvEcResponse                *pResponse;
+    NvEcEvent                   *pEvent;
+    NvEcEventRegistrationHandle hEcEventRegister;
+    NvBool                      CompressionEnabled;
+    NvU8                        CompressionState;
+    NvU32                       NumBytesPerSample;
+    NvU32                       ValidMousePorts[MAX_NUM_MOUSE_PORTS + 1];
+} NvOdmMouseDevice;
+
+#if defined(__cplusplus)
+}
+#endif
+
+/** @} */
+
+#endif // INCLUDED_NVODM_MOUSE_INT_H
+
diff --git a/arch/arm/mach-tegra/odm_kit/platform/scrollwheel/Makefile b/arch/arm/mach-tegra/odm_kit/platform/scrollwheel/Makefile
new file mode 100644
index 000000000000..071c1f60cc28
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/platform/scrollwheel/Makefile
@@ -0,0 +1,12 @@
+ccflags-y += -DNV_IS_AVP=0
+ccflags-y += -DNV_OAL=0
+ccflags-y += -DNV_USE_FUSE_CLOCK_ENABLE=0
+ifeq ($(CONFIG_MACH_TEGRA_GENERIC_DEBUG),y)
+ccflags-y += -DNV_DEBUG=1
+else
+ccflags-y += -DNV_DEBUG=0
+endif
+
+obj-$(CONFIG_TEGRA_ODM_HARMONY)		+= nvodm_scrollwheel_stub.o
+obj-$(CONFIG_TEGRA_ODM_WHISTLER)	+= nvodm_scrollwheel.o
+obj-$(CONFIG_TEGRA_ODM_CONCORDE)	+= nvodm_scrollwheel.o
diff --git a/arch/arm/mach-tegra/odm_kit/platform/scrollwheel/nvodm_scrollwheel.c b/arch/arm/mach-tegra/odm_kit/platform/scrollwheel/nvodm_scrollwheel.c
new file mode 100644
index 000000000000..392ff053ae1f
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/platform/scrollwheel/nvodm_scrollwheel.c
@@ -0,0 +1,396 @@
+/*
+ * Copyright (c) 2006-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include "nvodm_scrollwheel.h"
+#include "nvodm_services.h"
+#include "nvodm_query_discovery.h"
+#include "nvodm_query.h"
+
+#define SCROLL_WHEEL_GUID NV_ODM_GUID('s', 'c', 'r', 'o', 'l', 'w', 'h', 'l')
+#define DEBOUNCE_TIME_MS 0
+
+typedef struct NvOdmScrollWheelRec
+{
+    // Gpio Handle
+    NvOdmServicesGpioHandle hGpio;
+    // Pin handles to all the 4 Gpio pins
+    NvOdmGpioPinHandle hInputPin1;
+    NvOdmGpioPinHandle hInputPin2;
+    NvOdmGpioPinHandle hSelectPin;
+    NvOdmGpioPinHandle hOnOffPin;
+    // Stores the key events the client had registered for.
+    NvOdmScrollWheelEvent RegisterEvents;
+    NvOdmOsSemaphoreHandle EventSema;
+    NvOdmServicesGpioIntrHandle IntrHandle[2];
+    NvOdmScrollWheelEvent Event;
+    NvU32 LastPin1Val;
+    NvOdmOsMutexHandle hKeyEventMutex;
+    NvOdmOsThreadHandle hDebounceRotThread;
+    NvOdmOsSemaphoreHandle hDebounceRotSema;
+    NvOdmOsSemaphoreHandle hDummySema;
+    volatile NvU32 shutdown;
+    volatile NvBool Debouncing;
+} NvOdmScrollWheel;
+
+static NvU32
+GetReliablePinValue(NvOdmServicesGpioHandle hGpio,
+                    NvOdmGpioPinHandle hPin)
+{
+    NvU32 data = (NvU32)-1;
+    const int sampleCount = 10;
+    int i = 0;
+
+    while (i < sampleCount)
+    {
+        NvU32 currData;
+        NvOdmGpioGetState(hGpio, hPin, &currData);
+        if (currData == data)
+        {
+            i++;
+        }
+        else
+        {
+            data = currData;
+            i = 0;
+        }
+    }
+
+    return data;
+}
+
+static void
+ScrollWheelDebounceRotThread(void *arg)
+{
+    NvOdmScrollWheelHandle hOdmScrollWheel = (NvOdmScrollWheelHandle)arg;
+    const NvU32 debounceTimeMS = 2;
+
+    while (!hOdmScrollWheel->shutdown)
+    {
+        //  If a scroll wheel event is detected, wait <debounceTime> milliseconds
+        //  and then read the Terminal 1 pin to determine the current level
+        NvOdmOsSemaphoreWait(hOdmScrollWheel->hDebounceRotSema);
+        // The dummy semaphore never gets signalled so it will always timeout
+        NvOdmOsSemaphoreWaitTimeout(hOdmScrollWheel->hDummySema, debounceTimeMS);
+        //NvOdmGpioGetState(hOdmScrollWheel->hGpio, hOdmScrollWheel->hInputPin1, &hOdmScrollWheel->LastPin1Val);
+        hOdmScrollWheel->LastPin1Val = GetReliablePinValue(hOdmScrollWheel->hGpio, hOdmScrollWheel->hInputPin1);
+        NvOdmGpioConfig(hOdmScrollWheel->hGpio,
+                        hOdmScrollWheel->hInputPin1,
+                        hOdmScrollWheel->LastPin1Val ?
+                        NvOdmGpioPinMode_InputInterruptFallingEdge :
+                        NvOdmGpioPinMode_InputInterruptRisingEdge);
+        hOdmScrollWheel->Debouncing = NV_FALSE;
+    }
+}
+
+static void RotGpioInterruptHandler(void *arg)
+{
+    NvOdmScrollWheelHandle hOdmScrollWheel = (NvOdmScrollWheelHandle)arg;
+    NvU32 InPinValue2;
+    NvOdmScrollWheelEvent Event = NvOdmScrollWheelEvent_None;
+
+    /* if still debouncing, ignore interrupt */
+    if (hOdmScrollWheel->Debouncing) 
+    {
+        NvOdmGpioInterruptDone(hOdmScrollWheel->IntrHandle[1]);
+        return;
+    }
+    NvOdmGpioGetState(hOdmScrollWheel->hGpio, hOdmScrollWheel->hInputPin2, &InPinValue2);
+    
+    if (InPinValue2 == hOdmScrollWheel->LastPin1Val)
+    {
+        Event = NvOdmScrollWheelEvent_RotateAntiClockWise;
+    }
+    else
+    {
+        Event = NvOdmScrollWheelEvent_RotateClockWise;
+    }
+
+    Event &= hOdmScrollWheel->RegisterEvents;
+    if (Event)
+    {
+        NvOdmOsMutexLock(hOdmScrollWheel->hKeyEventMutex);
+        hOdmScrollWheel->Event &= ~(NvOdmScrollWheelEvent_RotateClockWise |
+                                    NvOdmScrollWheelEvent_RotateAntiClockWise);
+        hOdmScrollWheel->Event |= Event;
+        NvOdmOsMutexUnlock(hOdmScrollWheel->hKeyEventMutex);
+        NvOdmOsSemaphoreSignal(hOdmScrollWheel->EventSema);
+    }
+    /* start debounce */
+    hOdmScrollWheel->Debouncing = NV_TRUE;
+    NvOdmOsSemaphoreSignal(hOdmScrollWheel->hDebounceRotSema);
+
+    NvOdmGpioInterruptDone(hOdmScrollWheel->IntrHandle[1]);
+}
+
+static void SelectGpioInterruptHandler(void *arg)
+{
+    NvOdmScrollWheelHandle hOdmScrollWheel = (NvOdmScrollWheelHandle)arg;
+    NvU32 CurrSelectPinState;
+    NvOdmScrollWheelEvent Event = NvOdmScrollWheelEvent_None;
+
+    NvOdmGpioGetState(hOdmScrollWheel->hGpio, hOdmScrollWheel->hSelectPin, &CurrSelectPinState);
+    Event = (CurrSelectPinState) ? NvOdmScrollWheelEvent_Release : NvOdmScrollWheelEvent_Press;
+    Event &= hOdmScrollWheel->RegisterEvents;
+
+    if (Event)
+    {
+        NvOdmOsMutexLock(hOdmScrollWheel->hKeyEventMutex);
+        hOdmScrollWheel->Event &= ~(NvOdmScrollWheelEvent_Press | NvOdmScrollWheelEvent_Release);
+        hOdmScrollWheel->Event |= Event;
+        NvOdmOsMutexUnlock(hOdmScrollWheel->hKeyEventMutex);
+        NvOdmOsSemaphoreSignal(hOdmScrollWheel->EventSema);
+    }
+
+    NvOdmGpioInterruptDone(hOdmScrollWheel->IntrHandle[0]);
+}
+
+NvOdmScrollWheelHandle 
+NvOdmScrollWheelOpen( 
+    NvOdmOsSemaphoreHandle hNotifySema,
+    NvOdmScrollWheelEvent RegisterEvents)
+{
+    NvOdmScrollWheelHandle hOdmScroll = NULL;
+    NvOdmPeripheralConnectivity *pConnectivity;
+    NvU32 i;
+    NvOdmInterruptHandler RotIntrHandler = (NvOdmInterruptHandler)RotGpioInterruptHandler;
+    NvOdmInterruptHandler SelectIntrHandler = (NvOdmInterruptHandler)SelectGpioInterruptHandler;
+    NvU32 GpioInstance[4];
+    NvU32 GpioPin[4];
+    NvU32 GpioIndex;
+    
+    pConnectivity = (NvOdmPeripheralConnectivity *)NvOdmPeripheralGetGuid(SCROLL_WHEEL_GUID);
+
+    if (pConnectivity == NULL)
+        return NULL;
+
+    // Should be IO class device
+    if (pConnectivity->Class != NvOdmPeripheralClass_HCI)
+        return NULL;
+
+    // Minimum 4 entry for the 4 line of GPIO
+    if (pConnectivity->NumAddress < 4)
+        return NULL;
+
+    GpioIndex = 0;
+    for (i=0; i<pConnectivity->NumAddress; i++)
+    {
+        if (pConnectivity->AddressList[i].Interface == NvOdmIoModule_Gpio)
+        {
+            GpioInstance[GpioIndex] = pConnectivity->AddressList[i].Instance;
+            GpioPin[GpioIndex++] = pConnectivity->AddressList[i].Address;
+        }
+    }
+
+    // 4 GPIO entry for the scroll wheel
+    if (GpioIndex != 4)
+        return NULL;
+        
+    hOdmScroll  = NvOdmOsAlloc(sizeof(NvOdmScrollWheel));
+    
+    if(!hOdmScroll)
+    {
+        return NULL;
+    }
+     
+    NvOdmOsMemset(hOdmScroll, 0, sizeof(NvOdmScrollWheel));
+
+    hOdmScroll->EventSema = hNotifySema;
+    hOdmScroll->RegisterEvents = RegisterEvents;
+    hOdmScroll->Event = NvOdmScrollWheelEvent_None;
+
+    hOdmScroll->hKeyEventMutex = NvOdmOsMutexCreate();
+    hOdmScroll->hDebounceRotSema = NvOdmOsSemaphoreCreate(0);
+    hOdmScroll->hDummySema = NvOdmOsSemaphoreCreate(0);
+    
+    if (!hOdmScroll->hKeyEventMutex ||
+        !hOdmScroll->hDebounceRotSema ||
+        !hOdmScroll->hDummySema)
+    {
+        goto ErrorExit;
+    }
+
+    // Getting the OdmGpio Handle
+    hOdmScroll->hGpio = NvOdmGpioOpen();
+    if (!hOdmScroll->hGpio)
+    {
+        goto ErrorExit;
+    }
+
+    hOdmScroll->hDebounceRotThread =
+        NvOdmOsThreadCreate((NvOdmOsThreadFunction)ScrollWheelDebounceRotThread,
+                            (void*)hOdmScroll);
+    if (!hOdmScroll->hDebounceRotThread)
+    {
+        goto ErrorExit;
+    }
+
+    // Acquiring Pin Handles for all the four Gpio Pins
+    // First entry is Input GPIO1
+    // Second entry should be Input GPIO2
+    // Third entry should be Select
+    // 4 th entry should be OnOff pin
+    hOdmScroll->hInputPin1= NvOdmGpioAcquirePinHandle(hOdmScroll ->hGpio, 
+                            GpioInstance[3], GpioPin[3]);
+
+    hOdmScroll->hInputPin2 = NvOdmGpioAcquirePinHandle(hOdmScroll ->hGpio, 
+                            GpioInstance[0], GpioPin[0]);
+
+    hOdmScroll->hSelectPin= NvOdmGpioAcquirePinHandle(hOdmScroll ->hGpio, 
+                            GpioInstance[2], GpioPin[2]);
+
+    hOdmScroll->hOnOffPin= NvOdmGpioAcquirePinHandle(hOdmScroll ->hGpio, 
+                            GpioInstance[1], GpioPin[1]);
+
+    if (!hOdmScroll->hInputPin1 || !hOdmScroll->hInputPin2 ||
+        !hOdmScroll->hSelectPin || !hOdmScroll->hOnOffPin)
+    {
+        goto ErrorExit;
+    }
+
+    // Setting the ON/OFF pin to output mode and setting to Low.
+    NvOdmGpioConfig(hOdmScroll->hGpio, hOdmScroll->hOnOffPin, NvOdmGpioPinMode_Output);
+    NvOdmGpioSetState(hOdmScroll->hGpio, hOdmScroll->hOnOffPin, 0);
+
+    // Configuring the other pins as input
+    //    NvOdmGpioConfig(hOdmScroll->hGpio, hOdmScroll->hSelectPin, NvOdmGpioPinMode_InputData);
+    NvOdmGpioConfig(hOdmScroll->hGpio, hOdmScroll->hInputPin1, NvOdmGpioPinMode_InputData);
+    NvOdmGpioConfig(hOdmScroll->hGpio, hOdmScroll->hInputPin2, NvOdmGpioPinMode_InputData);
+
+    if (NvOdmGpioInterruptRegister(hOdmScroll->hGpio, &hOdmScroll->IntrHandle[0],
+        hOdmScroll->hSelectPin, NvOdmGpioPinMode_InputInterruptAny,
+        SelectIntrHandler, (void *)(hOdmScroll), DEBOUNCE_TIME_MS) == NV_FALSE)
+    {
+        goto ErrorExit;
+    }
+
+    hOdmScroll->LastPin1Val = GetReliablePinValue(hOdmScroll->hGpio, hOdmScroll->hInputPin1);
+    
+    if (NvOdmGpioInterruptRegister(hOdmScroll->hGpio, &hOdmScroll->IntrHandle[1],
+        hOdmScroll->hInputPin1, hOdmScroll->LastPin1Val ?
+            NvOdmGpioPinMode_InputInterruptFallingEdge :
+            NvOdmGpioPinMode_InputInterruptRisingEdge,
+        RotIntrHandler, (void *)(hOdmScroll), DEBOUNCE_TIME_MS) == NV_FALSE)
+    {
+        goto ErrorExit;
+    }
+
+    if (!hOdmScroll->IntrHandle[0] || !hOdmScroll->IntrHandle[1])
+    {
+        goto ErrorExit;
+    }
+
+    hOdmScroll->Debouncing = NV_FALSE;
+    
+    return hOdmScroll;
+
+   ErrorExit:
+    NvOdmScrollWheelClose(hOdmScroll);
+    return NULL;
+}
+
+void NvOdmScrollWheelClose(NvOdmScrollWheelHandle hOdmScrollWheel)
+{
+    if (hOdmScrollWheel)
+    {
+        hOdmScrollWheel->shutdown = 1;
+
+        if (hOdmScrollWheel->hDebounceRotThread)
+        {
+            if (hOdmScrollWheel->hDebounceRotSema)                
+                NvOdmOsSemaphoreSignal(hOdmScrollWheel->hDebounceRotSema);
+            NvOdmOsThreadJoin(hOdmScrollWheel->hDebounceRotThread);
+        }
+ 
+        if (hOdmScrollWheel->hGpio)
+        {
+            if (hOdmScrollWheel->IntrHandle[0])
+            {
+                NvOdmGpioInterruptUnregister(hOdmScrollWheel->hGpio,
+                                            hOdmScrollWheel->hSelectPin,
+                                            hOdmScrollWheel->IntrHandle[0]);
+            }
+            if (hOdmScrollWheel->IntrHandle[1])
+            {
+                NvOdmGpioInterruptUnregister(hOdmScrollWheel->hGpio,
+                                            hOdmScrollWheel->hInputPin1,
+                                            hOdmScrollWheel->IntrHandle[1]);
+            }
+        
+            if (hOdmScrollWheel->hOnOffPin)
+            {
+                NvOdmGpioReleasePinHandle(hOdmScrollWheel->hGpio, hOdmScrollWheel->hOnOffPin);
+            }
+        
+            if (hOdmScrollWheel->hInputPin1)
+            {
+                NvOdmGpioReleasePinHandle(hOdmScrollWheel->hGpio, hOdmScrollWheel->hInputPin1);
+            }
+            if (hOdmScrollWheel->hInputPin2)
+            {
+                NvOdmGpioReleasePinHandle(hOdmScrollWheel->hGpio, hOdmScrollWheel->hInputPin2);
+            }
+        
+            if (hOdmScrollWheel->hSelectPin)
+            {
+                NvOdmGpioReleasePinHandle(hOdmScrollWheel->hGpio, hOdmScrollWheel->hSelectPin);
+            }
+
+            NvOdmGpioClose(hOdmScrollWheel->hGpio);
+        }
+
+        if (hOdmScrollWheel->hDummySema)
+        {
+            NvOdmOsSemaphoreDestroy(hOdmScrollWheel->hDummySema);
+        }
+        if (hOdmScrollWheel->hDebounceRotSema)
+        {
+            NvOdmOsSemaphoreDestroy(hOdmScrollWheel->hDebounceRotSema);
+        }
+        if (hOdmScrollWheel->hKeyEventMutex)
+        {
+            NvOdmOsMutexDestroy(hOdmScrollWheel->hKeyEventMutex);
+        }
+
+        NvOdmOsFree(hOdmScrollWheel);
+    }
+}
+
+NvOdmScrollWheelEvent NvOdmScrollWheelGetEvent(NvOdmScrollWheelHandle hOdmScrollWheel)
+{
+    NvOdmScrollWheelEvent Event;
+    NvOdmOsMutexLock(hOdmScrollWheel->hKeyEventMutex);
+    Event = hOdmScrollWheel->Event;
+    hOdmScrollWheel->Event = NvOdmScrollWheelEvent_None;
+    NvOdmOsMutexUnlock(hOdmScrollWheel->hKeyEventMutex);
+    return Event;
+}
+
diff --git a/arch/arm/mach-tegra/odm_kit/platform/scrollwheel/nvodm_scrollwheel_stub.c b/arch/arm/mach-tegra/odm_kit/platform/scrollwheel/nvodm_scrollwheel_stub.c
new file mode 100644
index 000000000000..cba93b0b9d2d
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/platform/scrollwheel/nvodm_scrollwheel_stub.c
@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) 2006-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include "nvodm_scrollwheel.h"
+
+
+NvOdmScrollWheelHandle
+NvOdmScrollWheelOpen(
+    NvOdmOsSemaphoreHandle hNotifySema,
+    NvOdmScrollWheelEvent RegisterEvents)
+{
+    return NULL;
+}
+
+void NvOdmScrollWheelClose(NvOdmScrollWheelHandle hOdmScrollWheel)
+{
+}
+
+NvOdmScrollWheelEvent NvOdmScrollWheelGetEvent(NvOdmScrollWheelHandle hOdmScrollWheel)
+{
+    return NvOdmScrollWheelEvent_None;
+}
+
diff --git a/arch/arm/mach-tegra/odm_kit/platform/touch/Makefile b/arch/arm/mach-tegra/odm_kit/platform/touch/Makefile
new file mode 100644
index 000000000000..457bacd20c8c
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/platform/touch/Makefile
@@ -0,0 +1,27 @@
+ccflags-y += -DNV_IS_AVP=0
+ccflags-y += -DNV_OAL=0
+ccflags-y += -DNV_USE_FUSE_CLOCK_ENABLE=0
+ifeq ($(CONFIG_MACH_TEGRA_GENERIC_DEBUG),y)
+ccflags-y += -DNV_DEBUG=1
+else
+ccflags-y += -DNV_DEBUG=0
+endif
+
+ifeq ($(CONFIG_TEGRA_ODM_CONCORDE),y)
+  is_tpk_touch := y
+endif
+
+ifeq ($(CONFIG_TEGRA_ODM_WHISTLER),y)
+  is_tpk_touch := y
+endif
+
+ifeq ($(CONFIG_TEGRA_ODM_HARMONY),y)
+  is_panjit_touch := y
+endif
+
+ccflags-$(is_tpk_touch) += -DNV_TOUCH_TPK
+ccflags-$(is_panjit_touch) += -DNV_TOUCH_PANJIT
+
+obj-y			+= nvodm_touch.o
+obj-$(is_tpk_touch)	+= nvodm_touch_tpk.o
+obj-$(is_panjit_touch)	+= nvodm_touch_panjit.o
diff --git a/arch/arm/mach-tegra/odm_kit/platform/touch/nvodm_touch.c b/arch/arm/mach-tegra/odm_kit/platform/touch/nvodm_touch.c
new file mode 100644
index 000000000000..bf7d3eaa3049
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/platform/touch/nvodm_touch.c
@@ -0,0 +1,125 @@
+/*
+ * Copyright (c) 2006-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include "nvodm_touch.h"
+#include "nvodm_touch_int.h"
+
+#if defined(NV_TOUCH_TPK)
+#include "nvodm_touch_tpk.h"
+#endif
+#if defined(NV_TOUCH_PANJIT)
+#include "nvodm_touch_panjit.h"
+#endif
+
+/** Implementation for the NvOdm TouchPad */
+
+NvBool
+NvOdmTouchDeviceOpen( NvOdmTouchDeviceHandle *hDevice )
+{
+    NvBool ret = NV_TRUE;
+
+#if defined(NV_TOUCH_TPK)
+    ret = TPK_Open(hDevice);
+#endif
+#if defined(NV_TOUCH_PANJIT)
+    ret = PANJIT_Open(hDevice);
+#endif
+
+    return ret;
+}
+
+
+void
+NvOdmTouchDeviceGetCapabilities(NvOdmTouchDeviceHandle hDevice, NvOdmTouchCapabilities* pCapabilities)
+{
+    hDevice->GetCapabilities(hDevice, pCapabilities);
+}
+
+
+NvBool
+NvOdmTouchReadCoordinate( NvOdmTouchDeviceHandle hDevice, NvOdmTouchCoordinateInfo *coord)
+{
+    return hDevice->ReadCoordinate(hDevice, coord);
+}
+
+NvBool
+NvOdmTouchGetSampleRate(NvOdmTouchDeviceHandle hDevice, NvOdmTouchSampleRate* pTouchSampleRate)
+{
+    return hDevice->GetSampleRate(hDevice, pTouchSampleRate);
+}
+
+void NvOdmTouchDeviceClose(NvOdmTouchDeviceHandle hDevice)
+{
+    hDevice->Close(hDevice);    
+}
+
+NvBool NvOdmTouchEnableInterrupt(NvOdmTouchDeviceHandle hDevice, NvOdmOsSemaphoreHandle hInterruptSemaphore)
+{
+    return hDevice->EnableInterrupt(hDevice, hInterruptSemaphore);
+}
+
+NvBool NvOdmTouchHandleInterrupt(NvOdmTouchDeviceHandle hDevice)
+{
+    return hDevice->HandleInterrupt(hDevice);
+}
+
+NvBool
+NvOdmTouchSetSampleRate(NvOdmTouchDeviceHandle hDevice, NvU32 SampleRate)
+{
+    return hDevice->SetSampleRate(hDevice, SampleRate);
+}
+
+
+NvBool
+NvOdmTouchPowerControl(NvOdmTouchDeviceHandle hDevice, NvOdmTouchPowerModeType mode)
+{
+    return hDevice->PowerControl(hDevice, mode);
+}
+
+void
+NvOdmTouchPowerOnOff(NvOdmTouchDeviceHandle hDevice, NvBool OnOff)
+{
+    hDevice->PowerOnOff(hDevice, OnOff);
+}
+
+
+NvBool
+NvOdmTouchOutputDebugMessage(NvOdmTouchDeviceHandle hDevice)
+{
+    return hDevice->OutputDebugMessage;
+}
+
+NvBool
+NvOdmTouchGetCalibrationData(NvOdmTouchDeviceHandle hDevice, NvU32 NumOfCalibrationData, NvS32* pRawCoordBuffer)
+{
+    return hDevice->GetCalibrationData(hDevice, NumOfCalibrationData, pRawCoordBuffer);
+}
diff --git a/arch/arm/mach-tegra/odm_kit/platform/touch/nvodm_touch_int.h b/arch/arm/mach-tegra/odm_kit/platform/touch/nvodm_touch_int.h
new file mode 100644
index 000000000000..d980c99b5c3e
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/platform/touch/nvodm_touch_int.h
@@ -0,0 +1,78 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_NVODM_TOUCH_INT_H
+#define INCLUDED_NVODM_TOUCH_INT_H
+
+#include "nvodm_services.h"
+#include "nvodm_touch.h"
+
+
+// Module debug: 0=disable, 1=enable
+#define NVODMTOUCH_ENABLE_PRINTF (0)
+
+#if (NV_DEBUG && NVODMTOUCH_ENABLE_PRINTF)
+#define NVODMTOUCH_PRINTF(x)   NvOdmOsDebugPrintf x
+#else
+#define NVODMTOUCH_PRINTF(x)
+#endif
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+ 
+typedef struct NvOdmTouchDeviceRec{
+    NvBool (*ReadCoordinate)    (NvOdmTouchDeviceHandle hDevice, NvOdmTouchCoordinateInfo *coord);
+    NvBool (*EnableInterrupt)   (NvOdmTouchDeviceHandle hDevice, NvOdmOsSemaphoreHandle hInterruptSemaphore);
+    NvBool (*HandleInterrupt)   (NvOdmTouchDeviceHandle hDevice);
+    NvBool (*GetSampleRate)     (NvOdmTouchDeviceHandle hDevice, NvOdmTouchSampleRate* pTouchSampleRate);
+    NvBool (*SetSampleRate)     (NvOdmTouchDeviceHandle hDevice, NvU32 rate);
+    NvBool (*PowerControl)      (NvOdmTouchDeviceHandle hDevice, NvOdmTouchPowerModeType mode);
+    NvBool (*PowerOnOff)        (NvOdmTouchDeviceHandle hDevice, NvBool OnOff);
+    void   (*GetCapabilities)   (NvOdmTouchDeviceHandle hDevice, NvOdmTouchCapabilities* pCapabilities);
+    NvBool (*GetCalibrationData)(NvOdmTouchDeviceHandle hDevice, NvU32 NumOfCalibrationData, NvS32* pRawCoordBuffer);
+    void   (*Close)             (NvOdmTouchDeviceHandle hDevice);
+    NvU16                       CurrentSampleRate;
+    NvBool                      OutputDebugMessage;
+} NvOdmTouchDevice;
+
+
+
+#if defined(__cplusplus)
+}
+#endif
+
+/** @} */
+
+#endif // INCLUDED_NVODM_TOUCH_INT_H
+
diff --git a/arch/arm/mach-tegra/odm_kit/platform/touch/nvodm_touch_panjit.c b/arch/arm/mach-tegra/odm_kit/platform/touch/nvodm_touch_panjit.c
new file mode 100644
index 000000000000..6516ccbce839
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/platform/touch/nvodm_touch_panjit.c
@@ -0,0 +1,603 @@
+/*

+ * Copyright (c) 2010 NVIDIA Corporation.

+ * All rights reserved.

+ *

+ * Redistribution and use in source and binary forms, with or without

+ * modification, are permitted provided that the following conditions are met:

+ *

+ * Redistributions of source code must retain the above copyright notice,

+ * this list of conditions and the following disclaimer.

+ *

+ * Redistributions in binary form must reproduce the above copyright notice,

+ * this list of conditions and the following disclaimer in the documentation

+ * and/or other materials provided with the distribution.

+ *

+ * Neither the name of the NVIDIA Corporation nor the names of its contributors

+ * may be used to endorse or promote products derived from this software

+ * without specific prior written permission.

+ *

+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"

+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE

+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE

+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE

+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR

+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF

+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS

+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN

+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)

+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE

+ * POSSIBILITY OF SUCH DAMAGE.

+ *

+ */

+

+#include "nvodm_touch_panjit.h"

+#include "nvodm_query_discovery.h"

+#include "nvos.h"

+

+#define PANJIT_BENCHMARK_SAMPLE                     0

+#define PANJIT_TOUCH_DEVICE_GUID NV_ODM_GUID('p','a','n','j','i','t','_','0')

+#define PANJIT_READ(dev, reg, buffer, len) \

+    PANJIT_ReadRegister(dev, reg, buffer, len)

+#define PANJIT_I2C_SPEED_KHZ                        400

+#define SAMPLES_PER_SECOND                          80

+

+#define SLEEP_MODE_NORMAL                           0x00

+#define SLEEP_MODE_SENSOR_SLEEP                     0x01

+

+#define X_MIN                                       0x00

+#define Y_MIN                                       0x00

+#define X_MAX                                       4095

+#define Y_MAX                                       4095

+#define PANJIT_I2C_TIMEOUT                          1000

+#define PANJIT_DEBOUNCE_TIME_MS                     1

+#define TP_DATA_LENGTH                              12

+#define TP_TOUCH_STATE_BYTE                         0

+#define TP_FINGER_ONE_MASK                          0x01

+#define TP_FINGER_TWO_MASK                          0x02

+#define TP_SPECIAL_FUNCTION_BYTE                    9

+

+static const

+NvOdmTouchCapabilities PANJIT_Capabilities =

+{

+    1,      // IsMultiTouchSupported

+    2,      // MaxNumberOfFingerCoordReported;

+    0,      // IsRelativeDataSupported

+    0,      // MaxNumberOfRelativeCoordReported

+    0,      // MaxNumberOfWidthReported

+    0,      // MaxNumberOfPressureReported

+    (NvU32)NvOdmTouchGesture_Not_Supported, // Gesture

+    0,      // IsWidthSupported

+    0,      // IsPressureSupported

+    1,      // IsFingersSupported

+    X_MIN,   // XMinPosition

+    Y_MIN,   // YMinPosition

+    X_MAX,   // XMaxPosition

+    Y_MAX,   // YMaxPosition

+    0

+};

+

+#define INT_PIN_ACTIVE_STATE 0

+

+static NvBool

+PANJIT_ReadRegister(

+    PANJIT_TouchDevice* hTouch,

+    NvU8 reg,

+    NvU8* buffer,

+    NvU32 len)

+{

+    NvOdmI2cStatus Error;

+    NvOdmI2cTransactionInfo TransactionInfo;

+

+    TransactionInfo.Address = (hTouch->DeviceAddr | 0x1);

+    TransactionInfo.Buf = buffer;

+    TransactionInfo.Flags = 0;

+    TransactionInfo.NumBytes = len;

+

+    Error = NvOdmI2cTransaction(hTouch->hOdmI2c,

+                                &TransactionInfo,

+                                1,

+                                hTouch->I2cClockSpeedKHz,

+                                PANJIT_I2C_TIMEOUT);

+

+    if (Error != NvOdmI2cStatus_Success)

+    {

+        NVODMTOUCH_PRINTF(("I2C Read Failure = %d (addr=0x%x, reg=0x%x)\r\n", Error,

+                           hTouch->DeviceAddr, reg));

+        return NV_FALSE;

+    }

+

+    return NV_TRUE;

+}

+

+static NvBool

+PANJIT_WriteRegister(

+    PANJIT_TouchDevice* hTouch,

+    NvU8 reg,

+    NvU8* buffer,

+    NvU32 len)

+{

+    NvOdmI2cStatus Error;

+    NvOdmI2cTransactionInfo TransactionInfo;

+

+    TransactionInfo.Address = hTouch->DeviceAddr;

+    TransactionInfo.Buf = buffer;

+    TransactionInfo.Flags = NVODM_I2C_IS_WRITE;

+    TransactionInfo.NumBytes = len;

+

+    Error = NvOdmI2cTransaction(hTouch->hOdmI2c,

+                                &TransactionInfo,

+                                1,

+                                hTouch->I2cClockSpeedKHz,

+                                PANJIT_I2C_TIMEOUT);

+

+    if (Error != NvOdmI2cStatus_Success)

+    {

+        NVODMTOUCH_PRINTF(("I2C Write Failure = %d (addr=0x%x, reg=0x%x)\r\n",

+            Error, hTouch->DeviceAddr, reg));

+        return NV_FALSE;

+    }

+    return NV_TRUE;

+}

+

+static void PANJIT_EnableScanMode(PANJIT_TouchDevice* hTouch)

+{

+    NvU8 buff[4];

+

+    // Enable Scan Mode.

+    buff[0] = 0;

+    buff[1] = 8;

+    PANJIT_WriteRegister(hTouch, 0, buff, 2);

+}

+

+static void PANJIT_ClearInterrupt(PANJIT_TouchDevice* hTouch)

+{

+    NvU8 buff[4];

+

+    // Clear Interrupt.

+    buff[0] = 1;

+    buff[1] = 0;

+    PANJIT_WriteRegister(hTouch, 0, buff, 2);

+}

+

+static NvBool PANJIT_Configure(PANJIT_TouchDevice* hTouch)

+{

+

+    NVODMTOUCH_PRINTF(("PANJIT_Configure\r\n"));

+

+    hTouch->SleepMode = SLEEP_MODE_NORMAL;

+    hTouch->SampleRate = SAMPLES_PER_SECOND;

+

+    // Enable Scan Mode.

+    PANJIT_EnableScanMode(hTouch);

+    // Clear Interrupt.

+    PANJIT_ClearInterrupt(hTouch);

+    return NV_TRUE;

+}

+

+static NvBool

+PANJIT_GetSample(

+    PANJIT_TouchDevice* hTouch,

+    NvOdmTouchCoordinateInfo* coord)

+{

+    NvU8 TouchData[TP_DATA_LENGTH] = {0};

+

+    NVODMTOUCH_PRINTF(("PANJIT_GetSample+\r\n"));

+

+    if (!hTouch || !coord)

+        return NV_FALSE;

+

+    if (!PANJIT_READ(hTouch, 0, &TouchData[0], TP_DATA_LENGTH))

+        return NV_FALSE;

+

+    NVODMTOUCH_PRINTF(("TouchData=0x%x %x %x %x %x %x %x %x %x %x %x %x\r\n",

+        TouchData[0], TouchData[1], TouchData[2], TouchData[3], TouchData[4],

+        TouchData[5], TouchData[6], TouchData[7],TouchData[8], TouchData[9],

+        TouchData[10], TouchData[11]));

+

+    /* Ignore No finger */

+    coord->fingerstate = (TouchData[10] & (TP_FINGER_ONE_MASK | TP_FINGER_TWO_MASK)) ?

+        NvOdmTouchSampleValidFlag : NvOdmTouchSampleIgnore;

+

+    if (coord->fingerstate == NvOdmTouchSampleIgnore)

+    {

+        if (hTouch->PrevFingers == 0)

+        {

+            NVODMTOUCH_PRINTF(("NvOdmTouchSampleIgnore\r\n"));

+            return NV_TRUE;

+        }

+        coord->fingerstate = NvOdmTouchSampleValidFlag;

+    }

+

+    // get the finger count

+    coord->additionalInfo.Fingers = TouchData[10];

+    if (coord->additionalInfo.Fingers > hTouch->Caps.MaxNumberOfFingerCoordReported)

+        coord->additionalInfo.Fingers = hTouch->Caps.MaxNumberOfFingerCoordReported;

+

+    NVODMTOUCH_PRINTF(("coord->additionalInfo.Fingers = %d\r\n",

+        coord->additionalInfo.Fingers));

+

+    if (coord->additionalInfo.Fingers)

+    {

+        coord->fingerstate |= NvOdmTouchSampleDownFlag;

+        coord->xcoord = TouchData[2];

+        coord->xcoord = ((coord->xcoord<<8)|(TouchData[3]));

+        coord->ycoord = TouchData[4];

+        coord->ycoord = ((coord->ycoord<<8)|(TouchData[5]));

+        coord->additionalInfo.multi_XYCoords[0][0] = coord->xcoord;

+        coord->additionalInfo.multi_XYCoords[0][1] = coord->ycoord;

+        coord->additionalInfo.multi_XYCoords[1][0] = (TouchData[6]<<8) | (TouchData[7]);

+        coord->additionalInfo.multi_XYCoords[1][1] = (TouchData[8]<<8) | (TouchData[9]);

+    }

+    hTouch->PrevFingers = coord->additionalInfo.Fingers;

+    NVODMTOUCH_PRINTF(("(%d,%d)\r\n", coord->xcoord, coord->ycoord));

+    return NV_TRUE;

+}

+

+static void PANJIT_GpioIsr(void *arg)

+{

+    PANJIT_TouchDevice *hTouch = (PANJIT_TouchDevice *)arg;

+

+    /* Signal the touch thread to read the sample. After it is done reading the

+     * sample it should re-enable the interrupt. */

+    NvOdmOsSemaphoreSignal(hTouch->hIntSema);

+}

+

+NvBool

+PANJIT_ReadCoordinate(

+    NvOdmTouchDeviceHandle hDevice,

+    NvOdmTouchCoordinateInfo* coord)

+{

+    PANJIT_TouchDevice *hTouch = (PANJIT_TouchDevice *)hDevice;

+    NvBool status = NV_FALSE;

+    static NvU32 prevSamleTime;

+    NvU32 CurrentSampleTime;

+#if PANJIT_BENCHMARK_SAMPLE

+    NvU32 time;

+#endif

+    NvU32 pinValue;

+

+    NvOdmGpioGetState(hTouch->hGpio, hTouch->hPin, &pinValue);

+    if (pinValue != INT_PIN_ACTIVE_STATE)

+        return NV_FALSE;

+

+    CurrentSampleTime = NvOdmOsGetTimeMS();

+    if (prevSamleTime)

+    {

+        if ((1000/hTouch->SampleRate) > (CurrentSampleTime - prevSamleTime))

+        {

+            NvOsSleepMS((1000/hTouch->SampleRate) - (CurrentSampleTime - prevSamleTime));

+        }

+    }

+    prevSamleTime = CurrentSampleTime;

+

+#if PANJIT_BENCHMARK_SAMPLE

+    time = CurrentSampleTime;

+#endif

+

+    status = PANJIT_GetSample(hTouch, coord);

+

+#if PANJIT_BENCHMARK_SAMPLE

+    NvOdmOsDebugPrintf("Touch sample time %d\r\n", NvOdmOsGetTimeMS() - time);

+#endif

+    return status;

+}

+

+void

+PANJIT_GetCapabilities(

+    NvOdmTouchDeviceHandle hDevice,

+    NvOdmTouchCapabilities* pCapabilities)

+{

+    PANJIT_TouchDevice *hTouch = (PANJIT_TouchDevice *)hDevice;

+

+    if (hTouch && pCapabilities)

+        *pCapabilities = hTouch->Caps;

+}

+

+void PANJIT_Close (NvOdmTouchDeviceHandle hDevice)

+{

+    PANJIT_TouchDevice *hTouch = (PANJIT_TouchDevice *)hDevice;

+

+    if (hTouch)

+    {

+        if (hTouch->hGpio)

+        {

+            if (hTouch->hGpioIntr)

+            {

+                NvOdmGpioInterruptUnregister(hTouch->hGpio,

+                    hTouch->hPin, hTouch->hGpioIntr);

+                hTouch->hGpioIntr = NULL;

+            }

+

+            if (hTouch->hPin)

+            {

+                NvOdmGpioReleasePinHandle(hTouch->hGpio, hTouch->hPin);

+                hTouch->hPin = NULL;

+            }

+

+            NvOdmGpioClose(hTouch->hGpio);

+            hTouch->hGpio = NULL;

+        }

+

+        if (hTouch->hOdmI2c)

+        {

+            NvOdmI2cClose(hTouch->hOdmI2c);

+            hTouch->hOdmI2c = NULL;

+        }

+

+        NvOdmOsFree(hTouch);

+        hTouch = NULL;

+    }

+}

+

+static void InitOdmTouch (NvOdmTouchDevice *pDev)

+{

+    if (pDev)

+    {

+        pDev->Close              = PANJIT_Close;

+        pDev->GetCapabilities    = PANJIT_GetCapabilities;

+        pDev->ReadCoordinate     = PANJIT_ReadCoordinate;

+        pDev->EnableInterrupt    = PANJIT_EnableInterrupt;

+        pDev->HandleInterrupt    = PANJIT_HandleInterrupt;

+        pDev->GetSampleRate      = PANJIT_GetSampleRate;

+        pDev->SetSampleRate      = PANJIT_SetSampleRate;

+        pDev->PowerControl       = PANJIT_PowerControl;

+        pDev->PowerOnOff         = PANJIT_PowerOnOff;

+        pDev->GetCalibrationData = PANJIT_GetCalibrationData;

+        pDev->OutputDebugMessage = NV_TRUE;

+    }

+}

+

+NvBool PANJIT_Open(NvOdmTouchDeviceHandle *hDevice)

+{

+    PANJIT_TouchDevice *hTouch = NULL;

+    NvU32 i = 0;

+    NvU32 found = 0;

+    NvU32 GpioPort = 0;

+    NvU32 GpioPin = 0;

+    NvU32 I2cInstance = 0;

+    NvOdmIoModule IoModule = NvOdmIoModule_I2c;

+    const NvOdmPeripheralConnectivity *pConnectivity = NULL;

+

+    NVODMTOUCH_PRINTF(("NvOdm Touch : PANJIT_Open() \r\n"));

+

+    // allocate memory to be used for the handle

+    hTouch = NvOdmOsAlloc(sizeof(PANJIT_TouchDevice));

+    if (!hTouch)

+        return NV_FALSE;

+

+    NvOdmOsMemset(hTouch, 0, sizeof(PANJIT_TouchDevice));

+

+    /* set function pointers */

+    InitOdmTouch(&hTouch->OdmTouch);

+

+    // read the query database

+    pConnectivity = NvOdmPeripheralGetGuid(PANJIT_TOUCH_DEVICE_GUID);

+    if (!pConnectivity)

+    {

+        NVODMTOUCH_PRINTF(("NvOdm Touch : pConnectivity is NULL Error \r\n"));

+        goto fail;

+    }

+

+    if (pConnectivity->Class != NvOdmPeripheralClass_HCI)

+    {

+        NVODMTOUCH_PRINTF(("NvOdm Touch : didn't find any periperal\

+            in discovery query for touch device Error \r\n"));

+        goto fail;

+    }

+

+    for (i = 0; i < pConnectivity->NumAddress; i++)

+    {

+        switch (pConnectivity->AddressList[i].Interface)

+        {

+            case NvOdmIoModule_I2c:

+            case NvOdmIoModule_I2c_Pmu:

+                hTouch->DeviceAddr = pConnectivity->AddressList[i].Address;

+                I2cInstance = pConnectivity->AddressList[i].Instance;

+                found |= 1;

+                IoModule = pConnectivity->AddressList[i].Interface;

+                break;

+

+            case NvOdmIoModule_Gpio:

+                GpioPort = pConnectivity->AddressList[i].Instance;

+                GpioPin = pConnectivity->AddressList[i].Address;

+                found |= 2;

+                break;

+

+            default:

+                break;

+        }

+    }

+

+    // see if we found the bus and GPIO used by the hardware

+    if ((found & 3) != 3)

+    {

+        NVODMTOUCH_PRINTF(("NvOdm Touch:peripheral connectivity problem \r\n"));

+        goto fail;

+    }

+

+    // allocate I2C instance

+    hTouch->hOdmI2c = NvOdmI2cOpen(IoModule, I2cInstance);

+    if (!hTouch->hOdmI2c)

+    {

+        NVODMTOUCH_PRINTF(("NvOdm Touch : NvOdmI2cOpen Error \r\n"));

+        goto fail;

+    }

+

+    // get the handle to the pin used as pen down interrupt

+    hTouch->hGpio = (NvOdmServicesGpioHandle)NvOdmGpioOpen();

+    if (!hTouch->hGpio)

+    {

+        NVODMTOUCH_PRINTF(("NvOdm Touch : NvOdmGpioOpen Error \r\n"));

+        goto fail;

+    }

+

+    hTouch->hPin = NvOdmGpioAcquirePinHandle(hTouch->hGpio, GpioPort, GpioPin);

+    if (!hTouch->hPin)

+    {

+        NVODMTOUCH_PRINTF(("NvOdm Touch : Couldn't get GPIO pin \r\n"));

+        goto fail;

+    }

+

+    NvOdmGpioConfig(hTouch->hGpio, hTouch->hPin, NvOdmGpioPinMode_InputData);

+

+    /* set default capabilities */

+    NvOdmOsMemcpy(&hTouch->Caps, &PANJIT_Capabilities,

+        sizeof(NvOdmTouchCapabilities));

+

+    /* set default I2C speed */

+    hTouch->I2cClockSpeedKHz = PANJIT_I2C_SPEED_KHZ;

+

+    /* set max positions */

+    hTouch->Caps.XMaxPosition = X_MAX;

+    hTouch->Caps.YMaxPosition = Y_MAX;

+

+    PANJIT_Configure(hTouch);

+

+    *hDevice = (NvOdmTouchDeviceHandle)hTouch;

+    return NV_TRUE;

+

+ fail:

+    PANJIT_Close((NvOdmTouchDeviceHandle)hTouch);

+    hTouch = NULL;

+    return NV_FALSE;

+}

+

+NvBool

+PANJIT_EnableInterrupt(

+    NvOdmTouchDeviceHandle hDevice,

+    NvOdmOsSemaphoreHandle hIntSema)

+{

+    PANJIT_TouchDevice *hTouch = (PANJIT_TouchDevice *)hDevice;

+

+    NV_ASSERT(hIntSema);

+

+    /* can only be initialized once */

+    if (hTouch->hGpioIntr || hTouch->hIntSema)

+        return NV_FALSE;

+

+    hTouch->hIntSema = hIntSema;

+

+    if (NvOdmGpioInterruptRegister(

+                hTouch->hGpio,

+                &hTouch->hGpioIntr,

+                hTouch->hPin,

+                NvOdmGpioPinMode_InputInterruptLow,

+                PANJIT_GpioIsr,

+                (void*)hTouch,

+                PANJIT_DEBOUNCE_TIME_MS) == NV_FALSE)

+    {

+        return NV_FALSE;

+    }

+

+    if (!hTouch->hGpioIntr)

+        return NV_FALSE;

+    return NV_TRUE;

+}

+

+NvBool PANJIT_HandleInterrupt(NvOdmTouchDeviceHandle hDevice)

+{

+    PANJIT_TouchDevice *hTouch = (PANJIT_TouchDevice *)hDevice;

+    NvU32 pinValue;

+

+    if (hTouch)

+    {

+        NvOdmGpioGetState(hTouch->hGpio, hTouch->hPin, &pinValue);

+        if (pinValue == INT_PIN_ACTIVE_STATE)

+        {

+            // Clear Interrupt.

+            PANJIT_ClearInterrupt(hTouch);

+            NvOdmGpioInterruptDone(hTouch->hGpioIntr);

+            return NV_TRUE;

+        }

+    }

+    return NV_FALSE;

+}

+

+NvBool

+PANJIT_GetSampleRate(

+    NvOdmTouchDeviceHandle hDevice,

+    NvOdmTouchSampleRate* pTouchSampleRate)

+{

+    if (pTouchSampleRate)

+    {

+        pTouchSampleRate->NvOdmTouchSampleRateHigh = SAMPLES_PER_SECOND;

+        pTouchSampleRate->NvOdmTouchSampleRateLow = SAMPLES_PER_SECOND;

+        pTouchSampleRate->NvOdmTouchCurrentSampleRate = 0; // 0 = low , 1 = high

+    }

+    return NV_TRUE;

+}

+

+NvBool PANJIT_SetSampleRate(NvOdmTouchDeviceHandle hDevice, NvU32 rate)

+{

+    PANJIT_TouchDevice *hTouch = (PANJIT_TouchDevice *)hDevice;

+

+    if (hTouch)

+    {

+        if (rate > SAMPLES_PER_SECOND)

+            hTouch->SampleRate = SAMPLES_PER_SECOND;

+        else

+            hTouch->SampleRate = rate;

+    }

+    return NV_TRUE;

+}

+

+NvBool

+PANJIT_PowerControl(

+    NvOdmTouchDeviceHandle hDevice,

+    NvOdmTouchPowerModeType mode)

+{

+    PANJIT_TouchDevice *hTouch = (PANJIT_TouchDevice *)hDevice;

+    NvU8 SleepMode;

+

+    switch(mode)

+    {

+        case NvOdmTouch_PowerMode_0:

+            SleepMode = SLEEP_MODE_NORMAL;

+            break;

+        case NvOdmTouch_PowerMode_1:

+        case NvOdmTouch_PowerMode_2:

+        case NvOdmTouch_PowerMode_3:

+            SleepMode = SLEEP_MODE_SENSOR_SLEEP;

+            break;

+        default:

+            return NV_FALSE;

+    }

+

+    if (hTouch->SleepMode == SleepMode)

+        return NV_TRUE;

+    hTouch->SleepMode = SleepMode;

+    return NV_TRUE;

+}

+

+NvBool

+PANJIT_GetCalibrationData(

+    NvOdmTouchDeviceHandle hDevice,

+    NvU32 NumOfCalibrationData,

+    NvS32* pRawCoordBuffer)

+{

+    static NvS32 RawCoordBuffer[] = {2048,2048,840,840,840,3330,3280,3330,3280,840};

+

+    if (!pRawCoordBuffer)

+        return NV_FALSE;

+

+    if (NumOfCalibrationData * 2 != (sizeof(RawCoordBuffer) / sizeof(NvS32)))

+    {

+        NVODMTOUCH_PRINTF(("WARNING: number of calibration data isn't matched\r\n"));

+        return NV_FALSE;

+    }

+

+    NvOdmOsMemcpy(pRawCoordBuffer, RawCoordBuffer, sizeof(RawCoordBuffer));

+    return NV_TRUE;

+}

+

+NvBool PANJIT_PowerOnOff(NvOdmTouchDeviceHandle hDevice, NvBool OnOff)

+{

+    if (!hDevice)

+        return NV_FALSE;

+

+    if (OnOff)

+        return PANJIT_PowerControl(hDevice, NvOdmTouch_PowerMode_0); // power ON

+    else

+        return PANJIT_PowerControl(hDevice, NvOdmTouch_PowerMode_3); // power OFF

+}

+

diff --git a/arch/arm/mach-tegra/odm_kit/platform/touch/nvodm_touch_panjit.h b/arch/arm/mach-tegra/odm_kit/platform/touch/nvodm_touch_panjit.h
new file mode 100644
index 000000000000..bfff86fe21ce
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/platform/touch/nvodm_touch_panjit.h
@@ -0,0 +1,188 @@
+/*

+ * Copyright (c) 2010 NVIDIA Corporation.

+ * All rights reserved.

+ *

+ * Redistribution and use in source and binary forms, with or without

+ * modification, are permitted provided that the following conditions are met:

+ *

+ * Redistributions of source code must retain the above copyright notice,

+ * this list of conditions and the following disclaimer.

+ *

+ * Redistributions in binary form must reproduce the above copyright notice,

+ * this list of conditions and the following disclaimer in the documentation

+ * and/or other materials provided with the distribution.

+ *

+ * Neither the name of the NVIDIA Corporation nor the names of its contributors

+ * may be used to endorse or promote products derived from this software

+ * without specific prior written permission.

+ *

+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"

+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE

+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE

+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE

+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR

+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF

+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS

+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN

+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)

+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE

+ * POSSIBILITY OF SUCH DAMAGE.

+ *

+ */

+

+#ifndef INCLUDED_NVODM_TOUCH_PANJIT_H

+#define INCLUDED_NVODM_TOUCH_PANJIT_H

+

+#include "nvodm_touch_int.h"

+#include "nvodm_services.h"

+

+#if defined(__cplusplus)

+extern "C"

+{

+#endif

+

+typedef struct PANJIT_TouchDevice_Rec

+{

+    NvOdmTouchDevice OdmTouch;

+    NvOdmTouchCapabilities Caps;

+    NvOdmServicesI2cHandle hOdmI2c;

+    NvOdmServicesGpioHandle hGpio;

+    NvOdmServicesPmuHandle hPmu;

+    NvOdmGpioPinHandle hPin;

+    NvOdmServicesGpioIntrHandle hGpioIntr;

+    NvOdmOsSemaphoreHandle hIntSema;

+    NvU32 PrevFingers;

+    NvU32 DeviceAddr;

+    NvU32 SampleRate;

+    NvU32 SleepMode;

+    NvBool PowerOn;

+    NvU32 I2cClockSpeedKHz;

+} PANJIT_TouchDevice;

+

+/**

+ * Gets a handle to the touch pad in the system.

+ *

+ * @param hDevice A pointer to the handle of the touch pad.

+ * @return NV_TRUE if successful, or NV_FALSE otherwise.

+ */

+NvBool PANJIT_Open(NvOdmTouchDeviceHandle *hDevice);

+

+/**

+ *  Releases the touch pad handle.

+ *

+ * @param hDevice The touch pad handle to be released. If

+ *     NULL, this API has no effect.

+ */

+void PANJIT_Close(NvOdmTouchDeviceHandle hDevice);

+

+/**

+ * Gets capabilities for the specified touch device.

+ *

+ * @param hDevice The handle of the touch pad.

+ * @param pCapabilities A pointer to the targeted

+ *  capabilities returned by the ODM.

+ */

+void

+PANJIT_GetCapabilities(

+    NvOdmTouchDeviceHandle hDevice,

+    NvOdmTouchCapabilities* pCapabilities);

+

+/**

+ * Gets coordinate info from the touch device.

+ *

+ * @param hDevice The handle to the touch pad.

+ * @param coord  A pointer to the structure holding coordinate info.

+ * @return NV_TRUE if successful, or NV_FALSE otherwise.

+ */

+NvBool

+PANJIT_ReadCoordinate(

+    NvOdmTouchDeviceHandle hDevice,

+    NvOdmTouchCoordinateInfo *pCoord);

+

+/**

+ * Hooks up the interrupt handle to the GPIO interrupt and enables the interrupt.

+ *

+ * @param hDevice The handle to the touch pad.

+ * @param hInterruptSemaphore A handle to hook up the interrupt.

+ * @return NV_TRUE if successful, or NV_FALSE otherwise.

+ */

+NvBool

+PANJIT_EnableInterrupt(

+    NvOdmTouchDeviceHandle hDevice,

+    NvOdmOsSemaphoreHandle hInterruptSemaphore);

+

+/**

+ * Prepares the next interrupt to get notified from the touch device.

+ *

+ * @param hDevice A handle to the touch pad.

+ * @return NV_TRUE if successful, or NV_FALSE otherwise.

+ */

+NvBool PANJIT_HandleInterrupt(NvOdmTouchDeviceHandle hDevice);

+

+/**

+ * Gets the touch ADC sample rate.

+ *

+ * @param hDevice A handle to the touch ADC.

+ * @param pTouchSampleRate A pointer to the NvOdmTouchSampleRate stucture.

+ *

+ * @return NV_TRUE if successful, or NV_FALSE otherwise.

+*/

+NvBool

+PANJIT_GetSampleRate(

+    NvOdmTouchDeviceHandle hDevice,

+    NvOdmTouchSampleRate* pTouchSampleRate);

+

+/**

+ * Sets the touch ADC sample rate.

+ *

+ * @param hDevice A handle to the touch ADC.

+ * @param SampleRate 1 indicates high frequency, 0 indicates low frequency.

+ *

+ * @return NV_TRUE if successful, or NV_FALSE otherwise.

+*/

+NvBool PANJIT_SetSampleRate(NvOdmTouchDeviceHandle hDevice, NvU32 rate);

+

+/**

+ * Sets the touch panel power mode.

+ *

+ * @param hDevice A handle to the touch ADC.

+ * @param mode The mode, ranging from full power to power off.

+ *

+ * @return NV_TRUE if successful, or NV_FALSE otherwise.

+*/

+NvBool

+PANJIT_PowerControl(

+    NvOdmTouchDeviceHandle hDevice,

+    NvOdmTouchPowerModeType mode);

+

+/**

+ * Gets the touch panel calibration data.

+ * This is optional as calibration may perform after the OS is up.

+ * This is not required to bring up the touch panel.

+ *

+ * @param hDevice A handle to the touch panel.

+ * @param NumOfCalibrationData Indicates the number of calibration points.

+ * @param pRawCoordBuffer The collection of X/Y coordinate data.

+ *

+ * @return NV_TRUE if preset calibration data is required, or NV_FALSE otherwise.

+ */

+NvBool

+PANJIT_GetCalibrationData(

+    NvOdmTouchDeviceHandle hDevice,

+    NvU32 NumOfCalibrationData,

+    NvS32* pRawCoordBuffer);

+

+/**

+ * Powers the touch device on or off.

+ *

+ * @param hDevice A handle to the touch ADC.

+ * @param OnOff  Specify 1 to power ON, 0 to power OFF.

+*/

+NvBool PANJIT_PowerOnOff(NvOdmTouchDeviceHandle hDevice, NvBool OnOff);

+

+#if defined(__cplusplus)

+}

+#endif

+

+#endif // INCLUDED_NVODM_TOUCH_PANJIT_H

+

diff --git a/arch/arm/mach-tegra/odm_kit/platform/touch/nvodm_touch_tpk.c b/arch/arm/mach-tegra/odm_kit/platform/touch/nvodm_touch_tpk.c
new file mode 100644
index 000000000000..c57663299cc8
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/platform/touch/nvodm_touch_tpk.c
@@ -0,0 +1,861 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include "nvodm_touch_int.h"
+#include "nvodm_services.h"
+#include "nvodm_touch_tpk.h"
+#include "nvodm_query_discovery.h"
+#include "tpk_reg.h"
+
+#define TPK_I2C_SPEED_KHZ                          40
+#define TPK_I2C_TIMEOUT                            500
+#define TPK_LOW_SAMPLE_RATE                        0    //40 reports per-second
+#define TPK_HIGH_SAMPLE_RATE                       1    //80 reports per-second
+#define TPK_MAX_READ_BYTES                         16
+#define TPK_MAX_PACKET_SIZE                        8
+#define TPK_CHECK_ERRORS                           0
+#define TPK_BENCHMARK_SAMPLE                       0
+#define TPK_REPORT_WAR_SUCCESS                     0
+#define TPK_REPORT_2ND_FINGER_DATA                 0
+#define TPK_DUMP_REGISTER                           0
+#define TPK_SCREEN_ANGLE                            0   //0=Landscape, 1=Portrait
+#define TPK_QUERY_SENSOR_RESOLUTION                0    //units per millimeter
+#define TPK_SET_MAX_POSITION                       0
+#define TPK_PAGE_CHANGE_DELAY                      0 //This should be unnecessary
+#define TPK_POR_DELAY                              100 //Dealy after Power-On Reset
+                                                       //500ms(Max) is suggested 
+                                                       //by RMI Interface Guide
+                                                       //(511-000099-01 Rev.B)
+
+#define TPK_ADL340_WAR                              0
+/* WAR for spurious zero reports from panel: verify zero
+   fingers sample data by waiting one refresh interval and
+   retrying reading data */
+#define TPK_SPURIOUS_ZERO_WAR                      1
+
+#define TPK_TOUCH_DEVICE_GUID NV_ODM_GUID('t','p','k','t','o','u','c','h')
+
+#define TPK_WRITE(dev, reg, byte) TPK_WriteRegister(dev, reg, byte)
+#define TPK_READ(dev, reg, buffer, len) TPK_ReadRegisterSafe(dev, reg, buffer, len)
+#define TPK_DEBOUNCE_TIME_MS 0
+
+typedef struct TPK_TouchDeviceRec
+{
+    NvOdmTouchDevice OdmTouch;
+    NvOdmTouchCapabilities Caps;
+    NvOdmServicesI2cHandle hOdmI2c;
+    NvOdmServicesGpioHandle hGpio;
+    NvOdmServicesPmuHandle hPmu;
+    NvOdmGpioPinHandle hPin;
+    NvOdmServicesGpioIntrHandle hGpioIntr;
+    NvOdmOsSemaphoreHandle hIntSema;
+    NvBool PrevFingers;
+    NvU32 DeviceAddr;
+    NvU32 SampleRate;
+    NvU32 SleepMode;
+    NvBool PowerOn;
+    NvU32 VddId;    
+    NvU32 ChipRevisionId; //Id=0x01:TPK chip on Concorde1
+                          //id=0x02:TPK chip with updated firmware on Concorde2
+    NvU32 I2cClockSpeedKHz;
+} TPK_TouchDevice;
+
+
+static const NvOdmTouchCapabilities TPK_Capabilities =
+{
+    1, //IsMultiTouchSupported
+    2, //MaxNumberOfFingerCoordReported;
+    0, //IsRelativeDataSupported
+    1, //MaxNumberOfRelativeCoordReported
+    15, //MaxNumberOfWidthReported
+    255, //MaxNumberOfPressureReported
+    (NvU32)NvOdmTouchGesture_Not_Supported, //Gesture
+    1, //IsWidthSupported
+    1, //IsPressureSupported
+    1, //IsFingersSupported
+    0, //XMinPosition
+    0, //YMinPosition
+    0, //XMaxPosition
+    0, //YMaxPosition
+#if TPK_SCREEN_ANGLE
+    (NvU32)NvOdmTouchOrientation_H_FLIP // Orientation 4 inch tpk panel
+#else
+    (NvU32)(NvOdmTouchOrientation_XY_SWAP | NvOdmTouchOrientation_H_FLIP | NvOdmTouchOrientation_V_FLIP)
+#endif    
+};
+
+#if TPK_ADL340_WAR
+// Dummy write accelerometer in order to workaround a HW bug of ADL340
+// Will Remove it once we use new accelerometer
+static NvBool NvAccDummyI2CSetRegs(TPK_TouchDevice* hTouch)
+{
+    NvOdmI2cTransactionInfo TransactionInfo;
+    NvU8 arr[2];
+    NvOdmI2cStatus Error;    
+
+    arr[0] = 0x0;
+    arr[1] = 0x0;
+
+    TransactionInfo.Address = 0x3A;
+    TransactionInfo.Buf = arr;
+    TransactionInfo.Flags = NVODM_I2C_IS_WRITE;
+    TransactionInfo.NumBytes = 2;
+
+    // Write dummy data to accelerometer
+
+    do
+    {
+        Error = NvOdmI2cTransaction(hTouch->hOdmI2c,
+                                    &TransactionInfo,
+                                    1,
+                                    hTouch->I2cClockSpeedKHz,
+                                    TPK_I2C_TIMEOUT);
+    } while (Error == NvOdmI2cStatus_Timeout);
+
+    if (Error != NvOdmI2cStatus_Success)
+    {
+        //NvOdmOsDebugPrintf("error!\r\n");
+        return NV_FALSE;
+    }                        
+    //NvOdmOsDebugPrintf("dummy!\r\n");
+    return NV_TRUE;
+}
+#endif
+
+static NvBool TPK_WriteRegister (TPK_TouchDevice* hTouch, NvU8 reg, NvU8 val)
+{
+    NvOdmI2cStatus Error;
+    NvOdmI2cTransactionInfo TransactionInfo;
+    NvU8 arr[2];
+#if TPK_ADL340_WAR    
+    // dummy write
+    Error = NvAccDummyI2CSetRegs(hTouch);
+#endif
+    arr[0] = reg;
+    arr[1] = val;
+    
+    TransactionInfo.Address = hTouch->DeviceAddr;
+    TransactionInfo.Buf = arr;
+    TransactionInfo.Flags = NVODM_I2C_IS_WRITE;
+    TransactionInfo.NumBytes = 2;
+    
+    do
+    {
+        Error = NvOdmI2cTransaction(hTouch->hOdmI2c,
+                                    &TransactionInfo,
+                                    1,
+                                    hTouch->I2cClockSpeedKHz,
+                                    TPK_I2C_TIMEOUT);
+    } while (Error == NvOdmI2cStatus_Timeout); 
+
+    if (Error != NvOdmI2cStatus_Success)
+    {
+        NVODMTOUCH_PRINTF(("I2C Write Failure = %d (addr=0x%x, reg=0x%x, val=0x%0x)\n", Error, 
+                           hTouch->DeviceAddr, reg, val));
+        return NV_FALSE;
+    }
+    return NV_TRUE;
+}
+
+#define TPK_MAX_READS (((TPK_MAX_READ_BYTES+(TPK_MAX_PACKET_SIZE-1))/TPK_MAX_PACKET_SIZE))
+
+static NvBool TPK_ReadRegisterOnce (TPK_TouchDevice* hTouch, NvU8 reg, NvU8* buffer, NvU32 len)
+{
+    NvOdmI2cStatus Error;
+    NvOdmI2cTransactionInfo TransactionInfo[2 * TPK_MAX_READS];
+    int reads = (len+(TPK_MAX_PACKET_SIZE-1))/TPK_MAX_PACKET_SIZE;
+    int left = len;
+    int i;
+    
+    NV_ASSERT(len <= TPK_MAX_READ_BYTES);
+#if TPK_ADL340_WAR    
+    // dummy write
+    Error = NvAccDummyI2CSetRegs(hTouch);
+#endif
+    ////////////////////////////////////////////////////////////////////////////
+    // For multi-byte reads, the TPK panel supports just sending the first
+    // address and then keep reading registers (non-standard SMBus operation).
+    // The limit for I2C packets is 8 bytes, so we read up to 8 bytes per
+    // multi-byte read transaction.
+    ////////////////////////////////////////////////////////////////////////////
+
+    for (i = 0; i < reads; i++)
+    {
+        int ind = i*2;
+
+        TransactionInfo[ind].Address = hTouch->DeviceAddr;
+        TransactionInfo[ind].Buf = &reg;
+        TransactionInfo[ind].Flags = NVODM_I2C_IS_WRITE;
+        TransactionInfo[ind].NumBytes = 1;
+
+        ind++;
+
+        TransactionInfo[ind].Address = hTouch->DeviceAddr | 0x1;
+        TransactionInfo[ind].Buf = buffer + i*TPK_MAX_PACKET_SIZE;
+        TransactionInfo[ind].Flags = 0;
+        TransactionInfo[ind].NumBytes =
+            left > TPK_MAX_PACKET_SIZE ? TPK_MAX_PACKET_SIZE : left;
+        
+        left -= TPK_MAX_PACKET_SIZE;
+    }
+    
+    do
+    {
+        Error = NvOdmI2cTransaction(hTouch->hOdmI2c,
+                                    TransactionInfo,
+                                    reads * 2,
+                                    hTouch->I2cClockSpeedKHz,
+                                    TPK_I2C_TIMEOUT);
+    } while (Error == NvOdmI2cStatus_Timeout);
+
+    if (Error != NvOdmI2cStatus_Success)
+    {
+        NVODMTOUCH_PRINTF(("I2C Read Failure = %d (addr=0x%x, reg=0x%x)\n", Error,
+                           hTouch->DeviceAddr, reg));
+        return NV_FALSE;
+    }
+
+    return NV_TRUE;
+}
+
+static NvBool TPK_ReadRegisterSafe (TPK_TouchDevice* hTouch, NvU8 reg, NvU8* buffer, NvU32 len)
+{
+    
+    if (!TPK_ReadRegisterOnce(hTouch, reg, buffer, len))
+        return NV_FALSE;
+
+
+    return NV_TRUE;
+}
+
+static NvBool TPK_SetPage (TPK_TouchDevice* hTouch, NvU8 page)
+{
+#if TPK_PAGE_CHANGE_DELAY
+    NvU32 SetPageDelayMs = 100; //Wait for 100 millisecond after change page
+#endif
+
+    if (!TPK_WRITE(hTouch, TPK_PAGE_SELECT, page)) return NV_FALSE;
+
+#if TPK_PAGE_CHANGE_DELAY
+    NvOdmOsSleepMS(SetPageDelayMs);
+#endif
+    
+    return NV_TRUE;
+}
+
+#if TPK_CHECK_ERRORS
+static void TPK_CheckError (TPK_TouchDevice* hTouch)
+{
+    NvU8 status;
+    TPK_READ(hTouch, TPK_DEVICE_STATUS, &status, 1);
+    if (status & 0x80)
+    {
+        NvU8 error;
+        TPK_READ(hTouch, TPK_ERROR_STATUE, &error, 1);
+        NvOdmOsDebugPrintf("Panel error %x %x\n", status, error);
+    }
+#if TPK_DUMP_REGISTER
+    TPK_READ(hTouch, TPK_DEVICE_STATUS, &status, 1);
+    NvOdmOsDebugPrintf("DeviceStatus(0x%x)=0x%x\n", TPK_DEVICE_STATUS, status);
+    
+    TPK_READ(hTouch, TPK_DEVICE_CONTROL, &status, 1);
+    NvOdmOsDebugPrintf("DeviceControl(0x%x)=0x%x\n", TPK_DEVICE_CONTROL, status);
+        
+    TPK_READ(hTouch, TPK_INTR_ENABLE, &status, 1);
+    NvOdmOsDebugPrintf("InterruptEnable(0x%x)=0x%x\n", TPK_INTR_ENABLE, status);
+        
+    TPK_READ(hTouch, TPK_ERROR_STATUE, &status, 1);
+    NvOdmOsDebugPrintf("TPK_ERROR_STATUE(0x%x)=0x%x\n", TPK_ERROR_STATUE, status);
+       
+    TPK_READ(hTouch, TPK_INTR_STATUS, &status, 1);
+    NvOdmOsDebugPrintf("InterruptStatus(0x%x)=0x%x\n", TPK_INTR_STATUS, status);
+        
+    TPK_READ(hTouch, TPK_DEVICE_COMMAND, &status, 1);
+    NvOdmOsDebugPrintf("DeviceCommand(0x%x)=0x%x\n", TPK_DEVICE_COMMAND, status);
+#endif      
+}
+#endif
+
+static NvBool TPK_Configure (TPK_TouchDevice* hTouch)
+{
+    hTouch->SleepMode = 0x0;
+    hTouch->SampleRate = 0; /* this forces register write */
+    return TPK_SetSampleRate(&hTouch->OdmTouch, TPK_HIGH_SAMPLE_RATE);
+}
+
+static NvBool TPK_GetSample (TPK_TouchDevice* hTouch, NvOdmTouchCoordinateInfo* coord)
+{
+    NvU8 Finger0[6] = {0};
+    NvU8 Finger1[6] = {0};
+    NvU8 Relative[2] = {0};
+    int status = 0;
+
+    NVODMTOUCH_PRINTF(("TPK_GetSample+\n"));
+    coord->fingerstate = NvOdmTouchSampleIgnore;
+
+    if (!TPK_ReadRegisterOnce(hTouch, TPK_DATA_0, Finger0, 6))
+        return NV_FALSE;
+    else
+        status = (Finger0[0] & 0x7);
+
+    if (!TPK_ReadRegisterOnce(hTouch, TPK_DATA_0+6, Finger1, 6))
+        return NV_FALSE;
+
+    if (!TPK_ReadRegisterOnce(hTouch, TPK_DATA_0+12, Relative, 2))
+        return NV_FALSE; 
+
+    /* tell windows to ignore transitional finger count samples */
+    coord->fingerstate = (status > 2) ? NvOdmTouchSampleIgnore : NvOdmTouchSampleValidFlag;
+    coord->additionalInfo.Fingers = status;
+
+    if (Finger0[0] & 0x8)
+        // Bit 3 of status indicates a tap. Driver still doesn't expose
+        // gesture capabilities. This is added more for testing of the support
+        // in the hardware for gesture support.
+    {
+        coord->additionalInfo.Gesture = NvOdmTouchGesture_Tap;
+        // NvOdmOsDebugPrintf("Detected the Tap gesture\n");
+    }
+
+    if (status)
+    {
+        /* always read first finger data, even if transitional */
+        coord->fingerstate |= NvOdmTouchSampleDownFlag;
+
+        coord->xcoord =
+        coord->additionalInfo.multi_XYCoords[0][0] =
+            (((NvU16)Finger0[2] & 0x1f) << 8) | (NvU16)Finger0[3];
+
+        coord->ycoord =
+        coord->additionalInfo.multi_XYCoords[0][1] =
+            (((NvU16)Finger0[4] & 0x1f) << 8) | (NvU16)Finger0[5];
+
+        coord->additionalInfo.width[0] = Finger0[0] >> 4;
+        coord->additionalInfo.Pressure[0] = Finger0[1];
+
+        /* only read second finger data if reported */
+        if (status == 2)
+        {
+            coord->additionalInfo.multi_XYCoords[1][0] =
+                (((NvU16)Finger1[2] & 0x1f) << 8) | (NvU16)Finger1[3];
+
+            coord->additionalInfo.multi_XYCoords[1][1] =
+            (((NvU16)Finger1[4] & 0x1f) << 8) | (NvU16)Finger1[5];
+
+            /* these are not supported, zero out just in case */
+            coord->additionalInfo.width[1] = 0;
+            coord->additionalInfo.Pressure[1] = 0;
+            if ( coord->additionalInfo.multi_XYCoords[1][0] <= 0 ||
+                coord->additionalInfo.multi_XYCoords[1][0] >= hTouch->Caps.XMaxPosition ||
+                coord->additionalInfo.multi_XYCoords[1][1] <= 0 || 
+                coord->additionalInfo.multi_XYCoords[1][1] >= hTouch->Caps.YMaxPosition)
+                coord->fingerstate = NvOdmTouchSampleIgnore;
+#if TPK_REPORT_2ND_FINGER_DATA
+            else
+                NvOdmOsDebugPrintf("catch 2 fingers width=0x%x, X=%d, Y=%d, DeltaX=%d, DeltaY=%d\n",
+                                    coord->additionalInfo.width[0],
+                                    coord->additionalInfo.multi_XYCoords[1][0],
+                                    coord->additionalInfo.multi_XYCoords[1][1],
+                                    Relative[0], Relative[1]);
+#endif
+        }
+    }
+    else if (!hTouch->PrevFingers)
+    {
+        /* two successive 0 finger samples */
+        coord->fingerstate = NvOdmTouchSampleIgnore;
+    }
+
+    hTouch->PrevFingers = status;
+        
+    NVODMTOUCH_PRINTF(("TPK_GetSample-\n"));
+    return NV_TRUE;
+}
+
+static void InitOdmTouch (NvOdmTouchDevice* Dev)
+{
+    Dev->Close              = TPK_Close;
+    Dev->GetCapabilities    = TPK_GetCapabilities;
+    Dev->ReadCoordinate     = TPK_ReadCoordinate;
+    Dev->EnableInterrupt    = TPK_EnableInterrupt;
+    Dev->HandleInterrupt    = TPK_HandleInterrupt;
+    Dev->GetSampleRate      = TPK_GetSampleRate;
+    Dev->SetSampleRate      = TPK_SetSampleRate;
+    Dev->PowerControl       = TPK_PowerControl;
+    Dev->PowerOnOff         = TPK_PowerOnOff;
+    Dev->GetCalibrationData = TPK_GetCalibrationData;
+    Dev->OutputDebugMessage = NV_FALSE;
+}
+
+static void TPK_GpioIsr(void *arg)
+{
+    TPK_TouchDevice* hTouch = (TPK_TouchDevice*)arg;
+
+    /* Signal the touch thread to read the sample. After it is done reading the
+     * sample it should re-enable the interrupt. */
+    NvOdmOsSemaphoreSignal(hTouch->hIntSema);            
+}
+
+NvBool TPK_ReadCoordinate (NvOdmTouchDeviceHandle hDevice, NvOdmTouchCoordinateInfo* coord)
+{
+    TPK_TouchDevice* hTouch = (TPK_TouchDevice*)hDevice;
+
+#if TPK_BENCHMARK_SAMPLE    
+    NvU32 time = NvOdmOsGetTimeMS();
+#endif
+    NVODMTOUCH_PRINTF(("GpioIst+\n"));
+
+#if TPK_CHECK_ERRORS
+    TPK_CheckError(hTouch);
+#endif
+
+    for (;;)
+    {
+        if (TPK_GetSample(hTouch, coord))
+        {
+            break;
+        }
+
+        /* If reading the data failed, the panel may be resetting itself.
+           Poll device status register to find when panel is back up
+           and reconfigure */
+        for (;;)
+        {
+            NvU8 status;
+            
+            while (!TPK_READ(hTouch, TPK_DEVICE_STATUS, &status, 1))
+            {
+                NvOdmOsSleepMS(10);
+            }
+
+            /* if we have a panel error, force reset and wait for status again */
+            if (status & 0x80)
+            {
+                TPK_WRITE(hTouch, TPK_DEVICE_COMMAND, 0x1);
+                continue;
+            }
+
+            /* reconfigure panel, if failed start again */
+            if (!TPK_Configure(hTouch))
+                continue;
+
+            /* re-enable interrupts for absolute data only */
+            if (!TPK_WRITE(hTouch, TPK_INTR_ENABLE, 0x3))
+                continue;
+
+            break;
+        }
+    }
+
+#if TPK_BENCHMARK_SAMPLE    
+    NvOdmOsDebugPrintf("Touch sample time %d\n", NvOdmOsGetTimeMS() - time);
+#endif
+    
+    return NV_TRUE;
+}
+
+void TPK_GetCapabilities (NvOdmTouchDeviceHandle hDevice, NvOdmTouchCapabilities* pCapabilities)
+{
+    TPK_TouchDevice* hTouch = (TPK_TouchDevice*)hDevice;
+    *pCapabilities = hTouch->Caps;
+}
+
+NvBool TPK_PowerOnOff (NvOdmTouchDeviceHandle hDevice, NvBool OnOff)
+{
+    TPK_TouchDevice* hTouch = (TPK_TouchDevice*)hDevice;
+
+    hTouch->hPmu = NvOdmServicesPmuOpen();
+
+    if (!hTouch->hPmu)
+    {
+        NVODMTOUCH_PRINTF(("NvOdm Touch : NvOdmServicesPmuOpen Error \n"));
+        return NV_FALSE;
+    }
+    
+    if (OnOff != hTouch->PowerOn)
+    {
+        NvOdmServicesPmuVddRailCapabilities vddrailcap;
+        NvU32 settletime;
+
+        NvOdmServicesPmuGetCapabilities( hTouch->hPmu, hTouch->VddId, &vddrailcap);
+
+        if(OnOff)
+            NvOdmServicesPmuSetVoltage( hTouch->hPmu, hTouch->VddId, vddrailcap.requestMilliVolts, &settletime);
+        else
+            NvOdmServicesPmuSetVoltage( hTouch->hPmu, hTouch->VddId, NVODM_VOLTAGE_OFF, &settletime);
+
+        if (settletime)
+            NvOdmOsWaitUS(settletime); // wait to settle power
+
+        hTouch->PowerOn = OnOff;
+
+        if(OnOff)
+            NvOdmOsSleepMS(TPK_POR_DELAY);
+    }
+
+    NvOdmServicesPmuClose(hTouch->hPmu);
+
+    return NV_TRUE;
+}
+
+NvBool TPK_Open (NvOdmTouchDeviceHandle* hDevice)
+{
+    TPK_TouchDevice* hTouch;
+    NvU32 i;
+    NvU32 found = 0;
+    NvU32 GpioPort = 0;
+    NvU32 GpioPin = 0;
+    NvU32 I2cInstance = 0;
+    NvU8 Buf[4];
+#if TPK_QUERY_SENSOR_RESOLUTION
+    NvU8  sensorresolution = 0; //units per millimeter
+#endif
+#if TPK_SET_MAX_POSITION
+    NvU32 SET_MAX_POSITION = 8191; //Max Position range from 0x0002 to 0x1fff
+    NvU32 SENSOR_MAX_POSITION = 0;
+#endif
+    NvU8 TPKChipRevID;
+
+    const NvOdmPeripheralConnectivity *pConnectivity = NULL;
+
+    hTouch = NvOdmOsAlloc(sizeof(TPK_TouchDevice));
+    if (!hTouch) return NV_FALSE;
+
+    NvOdmOsMemset(hTouch, 0, sizeof(TPK_TouchDevice));
+
+    /* set function pointers */
+    InitOdmTouch(&hTouch->OdmTouch);
+
+    pConnectivity = NvOdmPeripheralGetGuid(TPK_TOUCH_DEVICE_GUID);
+    if (!pConnectivity)
+    {
+        NVODMTOUCH_PRINTF(("NvOdm Touch : pConnectivity is NULL Error \n"));
+        goto fail;
+    }
+
+    if (pConnectivity->Class != NvOdmPeripheralClass_HCI)
+    {
+        NVODMTOUCH_PRINTF(("NvOdm Touch : didn't find any periperal in discovery query for touch device Error \n"));
+        goto fail;
+    }
+
+    for (i = 0; i < pConnectivity->NumAddress; i++)
+    {
+        switch (pConnectivity->AddressList[i].Interface)
+        {
+            case NvOdmIoModule_I2c:
+                hTouch->DeviceAddr = (pConnectivity->AddressList[i].Address << 1);
+                I2cInstance = pConnectivity->AddressList[i].Instance;
+                found |= 1;
+                break;
+            case NvOdmIoModule_Gpio:
+                GpioPort = pConnectivity->AddressList[i].Instance;
+                GpioPin = pConnectivity->AddressList[i].Address;
+                found |= 2;
+                break;
+            case NvOdmIoModule_Vdd:
+                hTouch->VddId = pConnectivity->AddressList[i].Address;
+                found |= 4;
+                break;
+            default:
+                break;
+        }
+    }
+
+    if ((found & 3) != 3)
+    {
+        NVODMTOUCH_PRINTF(("NvOdm Touch : peripheral connectivity problem \n"));
+        goto fail;
+    }
+
+    if ((found & 4) != 0)
+    {
+        if (NV_FALSE == TPK_PowerOnOff(&hTouch->OdmTouch, 1))
+            goto fail;            
+    }
+    else
+    {
+        hTouch->VddId = 0xFF; 
+    }
+
+    hTouch->hOdmI2c = NvOdmI2cOpen(NvOdmIoModule_I2c, I2cInstance);
+    if (!hTouch->hOdmI2c)
+    {
+        NVODMTOUCH_PRINTF(("NvOdm Touch : NvOdmI2cOpen Error \n"));
+        goto fail;
+    }
+
+    hTouch->hGpio = NvOdmGpioOpen();
+
+    if (!hTouch->hGpio)
+    {        
+        NVODMTOUCH_PRINTF(("NvOdm Touch : NvOdmGpioOpen Error \n"));
+        goto fail;
+    }
+
+    hTouch->hPin = NvOdmGpioAcquirePinHandle(hTouch->hGpio, GpioPort, GpioPin);
+    if (!hTouch->hPin)
+    {
+        NVODMTOUCH_PRINTF(("NvOdm Touch : Couldn't get GPIO pin \n"));
+        goto fail;
+    }
+
+    NvOdmGpioConfig(hTouch->hGpio,
+                    hTouch->hPin,
+                    NvOdmGpioPinMode_InputData);
+
+    /* set default capabilities */
+    NvOdmOsMemcpy(&hTouch->Caps, &TPK_Capabilities, sizeof(NvOdmTouchCapabilities));
+
+    /* set default I2C speed */
+    hTouch->I2cClockSpeedKHz = TPK_I2C_SPEED_KHZ;
+    
+    /* disable interrupts */
+    if (!TPK_WRITE(hTouch, TPK_INTR_ENABLE, 0))
+        goto fail;
+
+#if TPK_SET_MAX_POSITION
+    if (!TPK_READ(hTouch, TPK_SENSOR_MAXPOSITION_0, Buf, 2)) goto fail;
+    SENSOR_MAX_POSITION =  ((NvU32)Buf[0] << 8) | (NvU32)Buf[1];
+    NVODMTOUCH_PRINTF(("Touch Max Postion = %d\n", SENSOR_MAX_POSITION));
+    
+    if (!TPK_WRITE(hTouch, TPK_SENSOR_MAXPOSITION_0, (NvU8)((SET_MAX_POSITION & 0x1fff) >> 8))) goto fail;
+    if (!TPK_WRITE(hTouch, TPK_SENSOR_MAXPOSITION_1, (NvU8)(SET_MAX_POSITION & 0xff))) goto fail;   
+    
+    if (!TPK_READ(hTouch, TPK_SENSOR_MAXPOSITION_0, Buf, 2)) goto fail;
+    SENSOR_MAX_POSITION =  ((NvU32)Buf[0] << 8) | (NvU32)Buf[1];
+    NVODMTOUCH_PRINTF(("Touch Max Postion = %d\n", SENSOR_MAX_POSITION));
+#endif
+
+    /* get max positions */
+    /* There is no SMBus Aliased Address to query max position, change page to 0x10 */ 
+    if (!TPK_SetPage(hTouch, ((TPK_RMI_SENSOR_X_MAX_POSITION_0 >> 8) & 0xFF))) goto fail;
+
+    if (!TPK_READ(hTouch, 0x04, Buf, 4)) goto fail;
+       
+    hTouch->Caps.XMaxPosition = ((NvU32)Buf[0] << 8) | (NvU32)Buf[1];
+    hTouch->Caps.YMaxPosition = ((NvU32)Buf[2] << 8) | (NvU32)Buf[3];
+
+#if TPK_QUERY_SENSOR_RESOLUTION
+    /* get sensor resulution */
+    /* There is no SMBus Aliased Address to query sensor resolution, change page to 0x10 */ 
+    if (!TPK_SetPage(hTouch, ((TPK_RMI_SENSOR_RESOLUTION >> 8) & 0xFF))) goto fail;
+
+    if (!TPK_READ(hTouch, TPK_RMI_SENSOR_RESOLUTION, &sensorresolution, 1)) goto fail;
+    NVODMTOUCH_PRINTF(("Touch Sensor Resolution = %d\n", sensorresolution));
+#endif
+    /* change page back to 0x04 */
+    if (!TPK_SetPage(hTouch, ((TPK_RMI_DATA_0 >> 8) & 0xFF))) goto fail;
+    
+    /* get chip revision id */
+    if (!TPK_READ(hTouch, TPK_PRODUCT_INFO_QUERY_1, &TPKChipRevID, 1)) goto fail;
+
+    hTouch->ChipRevisionId = (NvU32)TPKChipRevID;
+    NVODMTOUCH_PRINTF(("Touch controller Revision ID = %d\n", hTouch->ChipRevisionId));
+
+    /* boost I2c spped to 100Khz when it is new tpk chip */
+    if (hTouch->ChipRevisionId == 0x02)
+        hTouch->I2cClockSpeedKHz = 100;
+    
+    /* configure panel */
+    if (!TPK_Configure(hTouch)) goto fail;
+
+    *hDevice = &hTouch->OdmTouch;
+    return NV_TRUE;
+
+ fail:
+    TPK_Close(&hTouch->OdmTouch);
+    return NV_FALSE;
+}
+
+NvBool TPK_EnableInterrupt (NvOdmTouchDeviceHandle hDevice, NvOdmOsSemaphoreHandle hIntSema)
+{
+    TPK_TouchDevice* hTouch = (TPK_TouchDevice*)hDevice;
+    NvOdmTouchCoordinateInfo coord;
+
+    NV_ASSERT(hIntSema);
+    
+    /* can only be initialized once */
+    if (hTouch->hGpioIntr || hTouch->hIntSema)
+        return NV_FALSE;
+
+    /* zero intr status */
+    (void)TPK_GetSample(hTouch, &coord);        
+
+    hTouch->hIntSema = hIntSema;    
+
+    if (NvOdmGpioInterruptRegister(hTouch->hGpio, &hTouch->hGpioIntr,
+        hTouch->hPin, NvOdmGpioPinMode_InputInterruptLow, TPK_GpioIsr,
+        (void*)hTouch, TPK_DEBOUNCE_TIME_MS) == NV_FALSE)
+    {
+        return NV_FALSE;
+    }
+
+    if (!hTouch->hGpioIntr)
+        return NV_FALSE;    
+
+    /* enable interrupts -- only for absolute data */
+    if (!TPK_WRITE(hTouch, TPK_INTR_ENABLE, 0x3))
+    {
+        NvOdmGpioInterruptUnregister(hTouch->hGpio, hTouch->hPin, hTouch->hGpioIntr);
+        hTouch->hGpioIntr = NULL;
+        return NV_FALSE;
+    }
+    
+    return NV_TRUE;
+}
+
+NvBool TPK_HandleInterrupt(NvOdmTouchDeviceHandle hDevice)
+{
+    TPK_TouchDevice* hTouch = (TPK_TouchDevice*)hDevice;
+    NvU32 pinValue;
+    
+    NvOdmGpioGetState(hTouch->hGpio, hTouch->hPin, &pinValue);
+    if (!pinValue)
+    {
+        //interrupt pin is still LOW, read data until interrupt pin is released.
+        return NV_FALSE;
+    }
+    else
+        NvOdmGpioInterruptDone(hTouch->hGpioIntr);
+    
+    return NV_TRUE;
+}
+
+NvBool TPK_GetSampleRate (NvOdmTouchDeviceHandle hDevice, NvOdmTouchSampleRate* pTouchSampleRate)
+{
+    TPK_TouchDevice* hTouch = (TPK_TouchDevice*)hDevice;
+    pTouchSampleRate->NvOdmTouchSampleRateHigh = 80;
+    pTouchSampleRate->NvOdmTouchSampleRateLow = 40;
+    pTouchSampleRate->NvOdmTouchCurrentSampleRate = (hTouch->SampleRate >> 1);
+    return NV_TRUE;
+}
+
+NvBool TPK_SetSampleRate (NvOdmTouchDeviceHandle hDevice, NvU32 rate)
+{
+    TPK_TouchDevice* hTouch = (TPK_TouchDevice*)hDevice;
+
+    if (rate != 0 && rate != 1)
+        return NV_FALSE;
+    
+    rate = 1 << rate;
+    
+    if (hTouch->SampleRate == rate)
+        return NV_TRUE;
+
+    if (!TPK_WRITE(hTouch, TPK_DEVICE_CONTROL, (NvU8)((rate << 6) | hTouch->SleepMode)))
+        return NV_FALSE;
+    
+    hTouch->SampleRate = rate;
+    return NV_TRUE;
+}
+
+
+NvBool TPK_PowerControl (NvOdmTouchDeviceHandle hDevice, NvOdmTouchPowerModeType mode)
+{
+    TPK_TouchDevice* hTouch = (TPK_TouchDevice*)hDevice;
+    NvU32 SleepMode;
+
+    NV_ASSERT(hTouch->VddId != 0xFF);
+    
+    switch(mode)
+    {
+        case NvOdmTouch_PowerMode_0:
+            SleepMode = 0x0;
+            break;
+        case NvOdmTouch_PowerMode_1:
+        case NvOdmTouch_PowerMode_2:
+        case NvOdmTouch_PowerMode_3:
+            SleepMode = 0x03;
+            break;
+        default:
+            return NV_FALSE;
+    }
+
+    if (hTouch->SleepMode == SleepMode)
+        return NV_TRUE;
+    
+    if (!TPK_WRITE(hTouch, TPK_DEVICE_CONTROL, (NvU8)((hTouch->SampleRate << 6) | SleepMode)))
+        return NV_FALSE;
+    
+    hTouch->SleepMode = SleepMode;    
+    return NV_TRUE;
+}
+
+NvBool TPK_GetCalibrationData(NvOdmTouchDeviceHandle hDevice, NvU32 NumOfCalibrationData, NvS32* pRawCoordBuffer)
+{
+#if TPK_SCREEN_ANGLE
+    //Portrait
+    static const NvS32 RawCoordBuffer[] = {2054, 3624, 3937, 809, 3832, 6546, 453, 6528, 231, 890};
+#else
+    //Landscape
+    static NvS32 RawCoordBuffer[] = {2054, 3624, 3832, 6546, 453, 6528, 231, 890, 3937, 809};
+#endif
+
+    if (NumOfCalibrationData*2 != (sizeof(RawCoordBuffer)/sizeof(NvS32)))
+    {
+        NVODMTOUCH_PRINTF(("WARNING: number of calibration data isn't matched\n"));
+        return NV_FALSE;
+    }
+    
+    NvOdmOsMemcpy(pRawCoordBuffer, RawCoordBuffer, sizeof(RawCoordBuffer));
+
+    return NV_TRUE;
+}
+
+
+void TPK_Close (NvOdmTouchDeviceHandle hDevice)
+{
+    TPK_TouchDevice* hTouch = (TPK_TouchDevice*)hDevice;
+
+    if (!hTouch) return;
+        
+    if (hTouch->hGpio)
+    {
+        if (hTouch->hPin)
+        {
+            if (hTouch->hGpioIntr)
+                NvOdmGpioInterruptUnregister(hTouch->hGpio, hTouch->hPin, hTouch->hGpioIntr);
+
+            NvOdmGpioReleasePinHandle(hTouch->hGpio, hTouch->hPin);
+        }
+
+        NvOdmGpioClose(hTouch->hGpio);
+    }
+
+    if (hTouch->hOdmI2c)
+        NvOdmI2cClose(hTouch->hOdmI2c);
+
+    NvOdmOsFree(hTouch);
+}
+
+
diff --git a/arch/arm/mach-tegra/odm_kit/platform/touch/nvodm_touch_tpk.h b/arch/arm/mach-tegra/odm_kit/platform/touch/nvodm_touch_tpk.h
new file mode 100644
index 000000000000..6cab3eb66ed1
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/platform/touch/nvodm_touch_tpk.h
@@ -0,0 +1,72 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_NVODM_TOUCH_TPK_H
+#define INCLUDED_NVODM_TOUCH_TPK_H
+
+#include "nvodm_touch_int.h"
+#include "nvodm_services.h"
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+NvBool TPK_Open( NvOdmTouchDeviceHandle *hDevice);
+
+void TPK_GetCapabilities(NvOdmTouchDeviceHandle hDevice, NvOdmTouchCapabilities* pCapabilities);
+
+NvBool TPK_ReadCoordinate( NvOdmTouchDeviceHandle hDevice, NvOdmTouchCoordinateInfo *coord);
+
+NvBool TPK_EnableInterrupt(NvOdmTouchDeviceHandle hDevice, NvOdmOsSemaphoreHandle hInterruptSemaphore);
+
+NvBool TPK_HandleInterrupt(NvOdmTouchDeviceHandle hDevice);
+
+NvBool TPK_GetSampleRate(NvOdmTouchDeviceHandle hDevice, NvOdmTouchSampleRate* pTouchSampleRate);
+
+NvBool TPK_SetSampleRate(NvOdmTouchDeviceHandle hDevice, NvU32 rate);
+
+NvBool TPK_PowerControl(NvOdmTouchDeviceHandle hDevice, NvOdmTouchPowerModeType mode);
+
+NvBool TPK_GetCalibrationData(NvOdmTouchDeviceHandle hDevice, NvU32 NumOfCalibrationData, NvS32* pRawCoordBuffer);
+
+NvBool TPK_PowerOnOff(NvOdmTouchDeviceHandle hDevice, NvBool OnOff);
+
+void TPK_Close( NvOdmTouchDeviceHandle hDevice);
+
+
+#if defined(__cplusplus)
+}
+#endif
+
+
+#endif // INCLUDED_NVODM_TOUCH_TPK_H
diff --git a/arch/arm/mach-tegra/odm_kit/platform/touch/tpk_reg.h b/arch/arm/mach-tegra/odm_kit/platform/touch/tpk_reg.h
new file mode 100644
index 000000000000..141a522bb944
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/platform/touch/tpk_reg.h
@@ -0,0 +1,165 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+ 
+#ifndef TPK_REG_HEADER
+#define TPK_REG_HEADER
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+
+// SMBus Aliased Address
+/* To make most efficient use of the SMBus paged addressing scheme, Synaptics
+ * RMI-on-SMBus devices define that for all commonly used RMI device registers, 
+ * there will be a duplicate aliased register located at a new RMI address. 
+ * The entire set of aliased register addresses are grouped into a single page
+ * of the RMI address space. This will enable user software to access all commonly
+ * used RMI registers without ever having to rewrite the Page Select register.
+ *
+ * The aliased addresses occupy page $04xx in the general RMI address map. At reset,
+ * all RMI-on-SMBus devices initialize their Page Select register to the value $04. 
+ * This means that by default, all SMBus register accesses will access the RMI
+ * Aliased Address space.
+ *
+ * ----------------------------------------------------------------------------
+ * | Aliased Address | General RMI Address | Register Group                  |
+ * ----------------------------------------------------------------------------
+ * | $0400-$041F     | $0400-$041F          | RMI Data Register and           |
+ * |                 |                      | Device Status Reg               |
+ * ----------------------------------------------------------------------------
+ * | $04E0-$04E7     | $0200-$0207          | RMI Product ID queries          |
+ * ----------------------------------------------------------------------------
+ * | $04F0-$04F4     | $0000-$0004          | RMI control, command, and       |
+ * |                 |                      | general status registers        |
+ * ----------------------------------------------------------------------------
+ * | $04FF           | $xxFF                | Page Select Register            |
+ * ----------------------------------------------------------------------------
+ 
+*/
+#define TPK_DATA_0                                 0x00 //Data Reg 0 - Finger #0
+#define TPK_DATA_1                                 0x01 //Data Reg 1 - Finger #0
+#define TPK_DATA_2                                 0x02 //Data Reg 2 - Finger #0
+#define TPK_DATA_3                                 0x03 //Data Reg 3 - Finger #0
+#define TPK_DATA_4                                 0x04 //Data Reg 4 - Finger #0
+#define TPK_DATA_5                                 0x05 //Data Reg 5 - Finger #0
+#define TPK_DATA_6                                 0x06 //Data Reg 6 - Finger #1
+#define TPK_DATA_7                                 0x07 //Data Reg 7 - Finger #1
+#define TPK_DATA_8                                 0x08 //Data Reg 8 - Finger #1
+#define TPK_DATA_9                                 0x09 //Data Reg 9 - Finger #1
+#define TPK_DATA_A                                 0x0A //Data Reg 10 - Finger #1
+#define TPK_DATA_B                                 0x0B //Data Reg 11 - Finger #1
+#define TPK_RELATIVE_DATA_X                        0x0C //Relative Horizontal Motion - Finger #0
+#define TPK_RELATIVE_DATA_Y                        0x0D //Relative Vertical Motion - Finger #0
+#define TPK_DEVICE_STATUS                          0x0E //Device Status Register
+#define TPK_2D_CONTROL                             0x21 //Func10: General 2D Control Reg
+#define TPK_2D_RELATIVE_SPEED                      0x22 //Func10: General 2D Relative Speed Reg
+#define TPK_2D_ACCLELERATION                       0x23 //Func10: General 2D Relative Acceleration Reg
+#define TPK_SENSOR_SENSITIVITY                     0x24 //Func10: Sensor Sensitivity
+#define TPK_SENSOR_MAXPOSITION_0                   0x26 //Func10: Sensor Max Position (bit 12:8)
+#define TPK_SENSOR_MAXPOSITION_1                   0x27 //Func10: Sensor Max Position (bit 7:0)
+#define TPK_RMI_PROTOCOL_VERSION                   0xE0 //RMI Protocol Version
+#define TPK_MANUFACTURER_ID                        0xE1 //Manufacturer ID
+#define TPK_PHYSICAL_INTERFACE_VERSION             0xE2 //Physical Interface Version
+#define TPK_PRODUCT_QUERY                          0xE3 //Product Property
+#define TPK_PRODUCT_INFO_QUERY_0                   0xE4 //Product Info 0
+#define TPK_PRODUCT_INFO_QUERY_1                   0xE5 //Product Info 1 (REVISION_ID)
+#define TPK_PRODUCT_INFO_QUERY_2                   0xE6 //Product Info 2
+#define TPK_PRODUCT_INFO_QUERY_3                   0xE7 //Product Info 3
+#define TPK_DEVICE_CONTROL                         0xF0 //Device Control Register
+#define TPK_INTR_ENABLE                            0xF1 //Interrupt Enable Register
+#define TPK_ERROR_STATUE                           0xF2 //Error Status Register
+#define TPK_INTR_STATUS                            0xF3 //Interrupt Request Status Register
+#define TPK_DEVICE_COMMAND                         0xF4 //Device Command Register
+#define TPK_PAGE_SELECT                            0xFF //Page Select Register
+
+// RMI Address Space
+// Data registers
+#define TPK_RMI_DATA_0                             0x0400 //Data Reg 0 - Finger #0
+#define TPK_RMI_DATA_1                             0x0401 //Data Reg 1 - Finger #0
+#define TPK_RMI_DATA_2                             0x0402 //Data Reg 2 - Finger #0
+#define TPK_RMI_DATA_3                             0x0403 //Data Reg 3 - Finger #0
+#define TPK_RMI_DATA_4                             0x0404 //Data Reg 4 - Finger #0
+#define TPK_RMI_DATA_5                             0x0405 //Data Reg 5 - Finger #0
+#define TPK_RMI_DATA_6                             0x0406 //Data Reg 6 - Finger #1
+#define TPK_RMI_DATA_7                             0x0407 //Data Reg 7 - Finger #1
+#define TPK_RMI_DATA_8                             0x0408 //Data Reg 8 - Finger #1
+#define TPK_RMI_DATA_9                             0x0409 //Data Reg 9 - Finger #1
+#define TPK_RMI_DATA_A                             0x040A //Data Reg 10 - Finger #1
+#define TPK_RMI_DATA_B                             0x040B //Data Reg 11 - Finger #1
+#define TPK_RMI_RELATIVE_DATA_X                    0x040C //Relative Horizontal Motion - Finger #0
+#define TPK_RMI_RELATIVE_DATA_Y                    0x040D //Relative Vertical Motion - Finger #0
+#define TPK_RMI_DEVICE_STATUS                      0x040E //Device Status Register
+
+// Function $10 register pages
+#define TPK_RMI_FUNCTION_VERSION                   0x1000 //Func10: Function Version query
+#define TPK_RMI_2D_PROPERTIES                      0x1001 //Func10: General 2D Properties query
+#define TPK_RMI_SENSOR_PROPERTIES_0                0x1002 //Func10: Sensor Properties
+#define TPK_RMI_SENSOR_PROPERTIES_1                0x1003 //Func10: Sensor Properties
+#define TPK_RMI_SENSOR_X_MAX_POSITION_0            0x1004 //Func10: Sensor X Max Position (bits 12:8)
+#define TPK_RMI_SENSOR_X_MAX_POSITION_1            0x1005 //Func10: Sensor X Max Position (bits 7:0)
+#define TPK_RMI_SENSOR_Y_MAX_POSITION_0            0x1006 //Func10: Sensor Y Max Position (bits 12:8)
+#define TPK_RMI_SENSOR_Y_MAX_POSITION_1            0x1007 //Func10: Sensor Y Max Position (bits 7:0)
+#define TPK_RMI_SENSOR_RESOLUTION                  0x1008 //Func10: Sensor Resolution
+#define TPK_RMI_2D_CONTROL                         0x1041 //Func10: General 2D Control Reg
+#define TPK_RMI_2D_RELATIVE_SPEED                  0x1042 //Func10: General 2D Relative Speed Reg
+#define TPK_RMI_2D_ACCLELERATION                   0x1043 //Func10: General 2D Relative Acceleration Reg
+#define TPK_RMI_SENSOR_SENSITIVITY                 0x1044 //Func10: Sensor Sensitivity
+#define TPK_RMI_SENSOR_MAXPOSITION_0               0x1046 //Func10: Sensor Max Position (bit 12:8)
+#define TPK_RMI_SENSOR_MAXPOSITION_1               0x1047 //Func10: Sensor Max Position (bit 7:0)
+
+// General product information and version queries
+#define TPK_RMI_RMI_PROTOCOL_VERSION               0x2000 //RMI Protocol Version
+#define TPK_RMI_MANUFACTURER_ID                    0x2001 //Manufacturer ID
+#define TPK_RMI_PHYSICAL_INTERFACE_VERSION         0x2002 //Physical Interface Version
+#define TPK_RMI_PRODUCT_QUERY                      0x2003 //Product Property
+#define TPK_RMI_PRODUCT_INFO_QUERY_0               0x2004 //Product Info 0
+#define TPK_RMI_PRODUCT_INFO_QUERY_1               0x2005 //Product Info 1 (REVISION_ID)
+#define TPK_RMI_PRODUCT_INFO_QUERY_2               0x2006 //Product Info 2
+#define TPK_RMI_PRODUCT_INFO_QUERY_3               0x2007 //Product Info 3
+
+// Standard RMI control, command, and status registers
+#define TPK_RMI_DEVICE_CONTROL                     0x0000 //Device Control Register
+#define TPK_RMI_INTR_ENABLE                        0x0001 //Interrupt Enable Register
+#define TPK_RMI_ERROR_STATUE                       0x0002 //Error Status Register
+#define TPK_RMI_INTR_STATUS                        0x0003 //Interrupt Request Status Register
+#define TPK_RMI_DEVICE_COMMAND                     0x0004 //Device Command Register
+
+#if defined(__cplusplus)
+}
+#endif
+
+
+#endif //TPK_REG_HEADER
+
+
diff --git a/arch/arm/mach-tegra/odm_kit/platform/vibrate/Makefile b/arch/arm/mach-tegra/odm_kit/platform/vibrate/Makefile
new file mode 100644
index 000000000000..d8807f63e73a
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/platform/vibrate/Makefile
@@ -0,0 +1,10 @@
+ccflags-y += -DNV_IS_AVP=0
+ccflags-y += -DNV_OAL=0
+ccflags-y += -DNV_USE_FUSE_CLOCK_ENABLE=0
+ifeq ($(CONFIG_MACH_TEGRA_GENERIC_DEBUG),y)
+ccflags-y += -DNV_DEBUG=1
+else
+ccflags-y += -DNV_DEBUG=0
+endif
+
+obj-y += nvodm_vibrate.o
diff --git a/arch/arm/mach-tegra/odm_kit/platform/vibrate/nvodm_vibrate.c b/arch/arm/mach-tegra/odm_kit/platform/vibrate/nvodm_vibrate.c
new file mode 100644
index 000000000000..43cc3cbf5ee4
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/platform/vibrate/nvodm_vibrate.c
@@ -0,0 +1,272 @@
+/*
+ * Copyright (c) 2006-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/**
+ * @file
+ * <b>NVIDIA Tegra ODM Kit:
+ *         Vibrate Interface</b>
+ *
+ * @b Description: Defines the ODM interface for Vibrate devices.
+ *
+ */
+
+#include "nvodm_vibrate.h"
+#include "nvos.h"
+#include "nvassert.h"
+#include "nvodm_services.h"
+#include "nvodm_query_discovery.h"
+#include "nvodm_pmu.h"
+
+#define VIBRATE_DEVICE_GUID NV_ODM_GUID('v','i','b','r','a','t','o','r')
+
+/**
+ * @brief Used to enable/disable debug print messages.
+ */
+#define NV_ODM_DEBUG 0
+
+#if NV_ODM_DEBUG
+    #define NV_ODM_TRACE NvOdmOsDebugPrintf
+#else
+    #define NV_ODM_TRACE (void)
+#endif
+
+typedef struct NvOdmVibDeviceRec
+{
+    /* The handle to the Pmu device */
+    NvOdmServicesPmuHandle hOdmServicePmuDevice;
+
+    /*Pmu Vdd Rail capabilities*/
+    NvOdmServicesPmuVddRailCapabilities RailCaps;
+
+    /* Pmu Rail ID*/
+    NvU32  VddId;
+
+} NvOdmVibDevice;
+
+
+/**
+ *  @brief Allocates a handle to the device. Configures the PWM
+ *   control to the Vibro motor with default values. To change
+ *   the amplitude and frequency use NvOdmVibrateSetParameter API.
+ *  @param hOdmVibrate  [IN] Opaque handle to the device.
+ *  @return  NV_TRUE on success and NV_FALSE on error
+ */
+NvBool
+NvOdmVibOpen(NvOdmVibDeviceHandle *hOdmVibrate)
+{
+    const NvOdmPeripheralConnectivity *pConnectivity = NULL;
+    NvU32 Index = 0;
+
+    NV_ASSERT(hOdmVibrate);
+
+    /* Allocate the handle */
+    (*hOdmVibrate) = (NvOdmVibDeviceHandle)NvOdmOsAlloc(sizeof(NvOdmVibDevice));
+    if (*hOdmVibrate == NULL)
+    {
+        NV_ODM_TRACE(("Error Allocating NvOdmPmuDevice. \n"));
+        return NV_FALSE;
+    }
+    NvOsMemset((*hOdmVibrate), 0, sizeof(NvOdmVibDevice));
+
+    /* Get the PMU handle */
+    (*hOdmVibrate)->hOdmServicePmuDevice = NvOdmServicesPmuOpen();
+    if (!(*hOdmVibrate)->hOdmServicePmuDevice)
+    {
+        NV_ODM_TRACE(("Error Opening Pmu device. \n"));
+        NvOdmOsFree(*hOdmVibrate);
+        *hOdmVibrate = NULL;
+        return NV_FALSE;
+    }
+
+        // Get the peripheral connectivity information
+    pConnectivity = NvOdmPeripheralGetGuid(VIBRATE_DEVICE_GUID);
+    if (pConnectivity == NULL)
+        return NV_FALSE;
+
+        // Search for the Vdd rail and set the proper volage to the rail.
+    for (Index = 0; Index < pConnectivity->NumAddress; ++Index)
+    {
+        if (pConnectivity->AddressList[Index].Interface == NvOdmIoModule_Vdd)
+        {
+            (*hOdmVibrate)->VddId = pConnectivity->AddressList[Index].Address;
+            NvOdmServicesPmuGetCapabilities((*hOdmVibrate)->hOdmServicePmuDevice, (*hOdmVibrate)->VddId, &((*hOdmVibrate)->RailCaps));
+            break;
+        }
+    }
+
+    return NV_TRUE;
+}
+
+/**
+ *  @brief Closes the ODM device and destroys all allocated resources.
+ *  @param hOdmVibrate  [IN] Opaque handle to the device.
+ *  @return None.
+ */
+void NvOdmVibClose(NvOdmVibDeviceHandle hOdmVibrate)
+{
+    if (hOdmVibrate != NULL)
+    {
+        NvOdmServicesPmuClose(hOdmVibrate->hOdmServicePmuDevice);
+        hOdmVibrate->hOdmServicePmuDevice = NULL;
+
+        hOdmVibrate->VddId  = 0;
+
+        NvOsMemset(&hOdmVibrate->RailCaps, 0, sizeof(NvOdmServicesPmuVddRailCapabilities));
+
+        NvOdmOsFree(hOdmVibrate);
+        hOdmVibrate = NULL;
+    }
+}
+
+
+/**
+ *  @brief Gets capabilities of the Vibrate device.
+ *  @param hOdmVibrate    [IN] Opaque handle to the device.
+ *  @param RequestedCaps  [IN] Specifies the capability to get.
+ *  @param pCapsValue    [OUT] A pointer to the returned value.
+ *  @return NV_TRUE on success and NV_FALSE on error
+ */
+NvBool
+NvOdmVibGetCaps(
+    NvOdmVibDeviceHandle hOdmVibrate,
+    NvOdmVibCaps RequestedCaps,
+    NvU32 *pCapsValue)
+{
+    NV_ASSERT(hOdmVibrate);
+    NV_ASSERT(pCapsValue);
+
+    if (!hOdmVibrate || !pCapsValue)
+    {
+        return NV_FALSE;
+    }
+
+    return NV_TRUE;
+}
+
+/**
+ *  @brief The frequency to the Vibro motor can be set
+ *    using this function. A frequency less than zero will be
+ *    clamped to zero and a frequency value beyond the max supported value
+ *    will be clamped to the max supported value.
+ *  @param hOdmVibrate  [IN] Opaque handle to the device.
+ *  @param Freq         [IN] Frequency in Hz
+ *  @return NV_TRUE on success and NV_FALSE on error
+ */
+NvBool
+NvOdmVibSetFrequency(NvOdmVibDeviceHandle hOdmVibrate, NvS32 Freq)
+{
+    //AP20 Vibrator does'nt support setting Frequency
+    return NV_TRUE;
+}
+
+/**
+ *  @brief The dutycycle of the PWM driving the Vibro motor can be set
+ *    using this function. A dutycycle less than zero will be
+ *    clamped to zero and value beyond the max supported value
+ *    will be clamped to the max supported value.
+ *  @param hOdmVibrate  [IN] Opaque handle to the device.
+ *  @param DCycle       [IN] Duty Cycle value in percentage (0%-100%)
+ *  @return NV_TRUE on success and NV_FALSE on error
+ */
+NvBool
+NvOdmVibSetDutyCycle(NvOdmVibDeviceHandle hOdmVibrate, NvS32 DCycle)
+{
+    //AP20 Vibrator does'nt support setting DutyCycle
+    return NV_TRUE;
+}
+
+/**
+ *  @brief Starts the Vibro with the frequency and duty-cycle set using the
+ *    Set API.
+ *  @param hOdmVibrate  [IN] Opaque handle to the device.
+ *  @return NV_TRUE on success and NV_FALSE on error
+ */
+NvBool
+NvOdmVibStart(NvOdmVibDeviceHandle hOdmVibrate)
+{
+    NvU32 SettlingTime = 0;
+
+    NV_ASSERT(hOdmVibrate);
+
+    if (!hOdmVibrate)
+    {
+        return NV_FALSE;
+    }
+
+    if (hOdmVibrate->hOdmServicePmuDevice != NULL)
+    {
+        // Search for the Vdd rail and power Off the module
+        if (hOdmVibrate->VddId)
+        {
+            NvOdmServicesPmuSetVoltage(hOdmVibrate->hOdmServicePmuDevice,
+                   hOdmVibrate->VddId, hOdmVibrate->RailCaps.requestMilliVolts, &SettlingTime);
+
+            if (SettlingTime)
+                NvOdmOsWaitUS(SettlingTime);
+        }
+    }
+
+    return NV_TRUE;
+}
+
+/**
+ *  @brief Stops the Vibro motor
+ *  @param hOdmVibrate  [IN] Opaque handle to the device.
+ *  @return NV_TRUE on success and NV_FALSE on error
+ */
+NvBool
+NvOdmVibStop(NvOdmVibDeviceHandle hOdmVibrate)
+{
+    NvU32 SettlingTime;
+
+    NV_ASSERT(hOdmVibrate);
+
+    if (!hOdmVibrate)
+    {
+        return NV_FALSE;
+    }
+
+    if (hOdmVibrate->hOdmServicePmuDevice != NULL)
+    {
+        // Search for the Vdd rail and power Off the module
+        if (hOdmVibrate->VddId)
+        {
+            NvOdmServicesPmuSetVoltage(hOdmVibrate->hOdmServicePmuDevice,
+                        hOdmVibrate->VddId, NVODM_VOLTAGE_OFF, &SettlingTime);
+
+            if (SettlingTime)
+                NvOdmOsWaitUS(SettlingTime);
+        }
+    }
+
+    return NV_TRUE;
+}
diff --git a/arch/arm/mach-tegra/odm_kit/query/Makefile b/arch/arm/mach-tegra/odm_kit/query/Makefile
new file mode 100644
index 000000000000..ef54c3faed47
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/query/Makefile
@@ -0,0 +1,3 @@
+obj-$(CONFIG_TEGRA_ODM_HARMONY)		+= harmony/
+obj-$(CONFIG_TEGRA_ODM_WHISTLER)	+= whistler/
+
diff --git a/arch/arm/mach-tegra/odm_kit/query/harmony/Makefile b/arch/arm/mach-tegra/odm_kit/query/harmony/Makefile
new file mode 100644
index 000000000000..bdc7cbfee77f
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/query/harmony/Makefile
@@ -0,0 +1,19 @@
+ccflags-y += -DNV_IS_AVP=0
+ccflags-y += -DNV_OAL=0
+ccflags-y += -DNV_USE_FUSE_CLOCK_ENABLE=0
+ifeq ($(CONFIG_MACH_TEGRA_GENERIC_DEBUG),y)
+ccflags-y += -DNV_DEBUG=1
+else
+ccflags-y += -DNV_DEBUG=0
+endif
+
+ccflags-y += -Iarch/arm/mach-tegra/odm_kit/adaptations
+ccflags-y += -Iarch/arm/mach-tegra/odm_kit/adaptations
+
+obj-y += nvodm_query.o
+obj-y += nvodm_query_discovery.o
+obj-y += nvodm_query_nand.o
+obj-y += nvodm_query_gpio.o
+obj-y += nvodm_query_pinmux.o
+obj-y += nvodm_query_kbc.o
+
diff --git a/arch/arm/mach-tegra/odm_kit/query/harmony/nvodm_query.c b/arch/arm/mach-tegra/odm_kit/query/harmony/nvodm_query.c
new file mode 100644
index 000000000000..62243eded55d
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/query/harmony/nvodm_query.c
@@ -0,0 +1,869 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/**
+ * @file
+ * <b>NVIDIA APX ODM Kit:
+ *         Implementation of the ODM Query API</b>
+ *
+ * @b Description: Implements the query functions for ODMs that may be
+ *                 accessed at boot-time, runtime, or anywhere in between.
+ */
+
+#include "nvodm_query.h"
+#include "nvodm_query_gpio.h"
+#include "nvodm_query_memc.h"
+#include "nvodm_query_discovery.h"
+#include "nvodm_query_pins.h"
+#include "nvodm_query_pins_ap20.h"
+#include "tegra_devkit_custopt.h"
+#include "nvodm_keylist_reserved.h"
+#include "nvrm_drf.h"
+
+#if !defined(NV_OAL)
+#define NV_OAL (0)
+#endif
+
+#define BOARD_ID_HARMONY 0x0B3E
+#define HARMONY_HYS5C1GB_SKU 0x3829
+
+#define NVODM_ENABLE_EMC_DVFS (1)
+
+// Although AP16 Concorde2 and AP16 Vail boards can support PMU
+// interrupt, keep it disabled for now because of PMU VBUS input
+// latch problem
+#define NVODM_PMU_INT_ENABLED (0)
+
+static const NvU8
+s_NvOdmQueryDeviceNamePrefixValue[] = {'T','e','g','r','a',0};
+
+static const NvU8
+s_NvOdmQueryManufacturerSetting[] = {'N','V','I','D','I','A',0};
+
+static const NvU8
+s_NvOdmQueryModelSetting[] = {'A','P','2','0',0};
+
+static const NvU8
+s_NvOdmQueryPlatformSetting[] = {'H','a','r','m','o','n','y',0};
+
+static const NvU8
+s_NvOdmQueryProjectNameSetting[] = {'O','D','M',' ','K','i','t',0};
+
+static const NvOdmDownloadTransport
+s_NvOdmQueryDownloadTransportSetting = NvOdmDownloadTransport_None;
+
+static const NvOdmQuerySdioInterfaceProperty s_NvOdmQuerySdioInterfaceProperty[4] =
+{
+    { NV_FALSE, 10,  NV_TRUE, 0x8, NvOdmQuerySdioSlotUsage_wlan   },
+    { NV_TRUE,   0, NV_FALSE, 0x5, NvOdmQuerySdioSlotUsage_Media  },
+    { NV_TRUE,   0, NV_FALSE, 0x6, NvOdmQuerySdioSlotUsage_unused },
+    { NV_TRUE,   0, NV_FALSE, 0x4, NvOdmQuerySdioSlotUsage_Media  }
+};
+
+static const NvOdmQuerySpiDeviceInfo s_NvOdmQuerySpiDeviceInfoTable [] =
+{
+    {NvOdmQuerySpiSignalMode_0, NV_TRUE}    // Spi1_Devices_0 (chip sel 0)
+};
+
+// Spi idle signal state
+static const NvOdmQuerySpiIdleSignalState s_NvOdmQuerySpiIdleSignalStateLevel[] =
+{
+    {NV_FALSE, NvOdmQuerySpiSignalMode_0, NV_FALSE}    // Spi 1
+};
+// We can have two I2s Instances
+static const NvOdmQueryI2sInterfaceProperty s_NvOdmQueryI2sInterfacePropertySetting[] =
+{
+    {
+        NvOdmQueryI2sMode_Master,               // Mode
+        NvOdmQueryI2sLRLineControl_LeftOnLow,   // I2sLRLineControl
+        NvOdmQueryI2sDataCommFormat_I2S,        // I2sDataCommunicationFormat
+        NV_FALSE,                               // IsFixedMCLK  
+        0                                       // FixedMCLKFrequency 
+    },
+    {
+        NvOdmQueryI2sMode_Master,               // Mode
+        NvOdmQueryI2sLRLineControl_LeftOnLow,   // I2sLRLineControl
+        NvOdmQueryI2sDataCommFormat_I2S,        // I2sDataCommunicationFormat
+        NV_FALSE,                               // IsFixedMCLK  
+        0                                       // FixedMCLKFrequency 
+    }
+};
+
+
+static const NvOdmQuerySpdifInterfaceProperty s_NvOdmQuerySpdifInterfacePropertySetting =
+{
+    NvOdmQuerySpdifDataCaptureControl_FromLeft
+};
+
+static const NvOdmQueryAc97InterfaceProperty s_NvOdmQueryAc97InterfacePropertySetting =
+{
+    NV_FALSE,
+    NV_FALSE,
+    NV_FALSE,
+    NV_FALSE,
+    NV_TRUE
+};
+
+// Add support for the Codec Formats
+// It must the order (dapIndex) how the codec is connected to the Dap port
+static const NvOdmQueryI2sACodecInterfaceProp s_NvOdmQueryI2sACodecInterfacePropSetting[] =
+{
+    {
+        NV_FALSE,                               // IsCodecMaster
+        0,                                      // DapPortIndex
+        0x36,                                   // DevAddress
+        NV_FALSE,                               // IsUsbmode
+        NvOdmQueryI2sLRLineControl_LeftOnLow,   // I2sCodecLRLineControl
+        NvOdmQueryI2sDataCommFormat_I2S         // I2sCodecDataCommFormat
+    }
+};
+
+static const NvOdmQueryDapPortConnection s_NvOdmQueryDapPortConnectionTable[] =
+{
+    // the Default Music Path
+    { NvOdmDapConnectionIndex_Music_Path, 2,
+    { {NvOdmDapPort_I2s1, NvOdmDapPort_Dap1, NV_TRUE},
+      {NvOdmDapPort_Dap1, NvOdmDapPort_I2s1, NV_FALSE}
+    }},
+
+    // Bluetooth to Codec
+    { NvOdmDapConnectionIndex_BlueTooth_Codec, 3,
+    { {NvOdmDapPort_Dap4, NvOdmDapPort_I2s1, NV_TRUE},
+      {NvOdmDapPort_I2s1, NvOdmDapPort_Dap4, NV_FALSE},
+      {NvOdmDapPort_I2s2, NvOdmDapPort_Dap1, NV_FALSE}
+    }}
+};
+
+
+// Ap20 support 5 dap ports
+// For port is connected to DAC(I2s) then PortMode is not valid- as Dac would be driving it
+static const NvOdmQueryDapPortProperty s_NvOdmQueryDapPortInfoTable[] =
+{
+    {NvOdmDapPort_None, NvOdmDapPort_None , {0, 0, 0, 0} }, // Reserved
+    // I2S1 (DAC1) <-> DAP1 <-> HIFICODEC
+    {NvOdmDapPort_I2s1, NvOdmDapPort_HifiCodecType,
+        {2, 16, 44100, NvOdmQueryI2sDataCommFormat_I2S}},   // Dap1
+    {NvOdmDapPort_None, NvOdmDapPort_None , {0, 0, 0, 0} }, // Dap2
+    {NvOdmDapPort_None, NvOdmDapPort_None , {0, 0, 0, 0} }, // Dap3
+    // I2S2 (DAC2) <-> DAP4 <-> BLUETOOTH
+    {NvOdmDapPort_I2s2, NvOdmDapPort_BlueTooth,
+        {2, 16, 8000, NvOdmQueryI2sDataCommFormat_I2S}}     // Dap4
+};
+
+static const NvOdmSdramControllerConfigAdv s_NvOdmHyS5c1GbEmcConfigTable[] =
+{
+    {
+                  0x20,   /* Rev 2.0 */
+                166500,   /* SDRAM frquency */
+                   950,   /* EMC core voltage */
+                    46,   /* Number of EMC parameters below */
+        {
+            0x0000000A,   /* RC */
+            0x00000016,   /* RFC */
+            0x00000008,   /* RAS */
+            0x00000003,   /* RP */
+            0x00000004,   /* R2W */
+            0x00000004,   /* W2R */
+            0x00000002,   /* R2P */
+            0x0000000C,   /* W2P */
+            0x00000003,   /* RD_RCD */
+            0x00000003,   /* WR_RCD */
+            0x00000002,   /* RRD */
+            0x00000001,   /* REXT */
+            0x00000004,   /* WDV */
+            0x00000005,   /* QUSE */
+            0x00000004,   /* QRST */
+            0x00000009,   /* QSAFE */
+            0x0000000D,   /* RDV */
+            0x000004DF,   /* REFRESH */
+            0x00000000,   /* BURST_REFRESH_NUM */
+            0x00000003,   /* PDEX2WR */
+            0x00000003,   /* PDEX2RD */
+            0x00000003,   /* PCHG2PDEN */
+            0x00000003,   /* ACT2PDEN */
+            0x00000001,   /* AR2PDEN */
+            0x0000000A,   /* RW2PDEN */
+            0x000000C8,   /* TXSR */
+            0x00000003,   /* TCKE */
+            0x00000006,   /* TFAW */
+            0x00000004,   /* TRPAB */
+            0x00000008,   /* TCLKSTABLE */
+            0x00000002,   /* TCLKSTOP */
+            0x00000000,   /* TREFBW */
+            0x00000000,   /* QUSE_EXTRA */
+            0x00000002,   /* FBIO_CFG6 */
+            0x00000000,   /* ODT_WRITE */
+            0x00000000,   /* ODT_READ */
+            0x00000083,   /* FBIO_CFG5 */
+            0xE03B0323,   /* CFG_DIG_DLL */
+            0x007FC010,   /* DLL_XFORM_DQS */
+            0x00008010,   /* DLL_XFORM_QUSE */
+            0x00000000,   /* ZCAL_REF_CNT */
+            0x00000000,   /* ZCAL_WAIT_CNT */
+            0x00000000,   /* AUTO_CAL_INTERVAL */
+            0x00000000,   /* CFG_CLKTRIM_0 */
+            0x00000000,   /* CFG_CLKTRIM_1 */
+            0x00000000,   /* CFG_CLKTRIM_2 */
+        }
+    },
+    {
+                  0x20,   /* Rev 2.0 */
+                333000,   /* SDRAM frquency */
+                  1200,   /* EMC core voltage */
+                    46,   /* Number of EMC parameters below */
+        {
+            0x00000014,   /* RC */
+            0x0000002B,   /* RFC */
+            0x0000000F,   /* RAS */
+            0x00000005,   /* RP */
+            0x00000004,   /* R2W */
+            0x00000005,   /* W2R */
+            0x00000003,   /* R2P */
+            0x0000000C,   /* W2P */
+            0x00000005,   /* RD_RCD */
+            0x00000005,   /* WR_RCD */
+            0x00000003,   /* RRD */
+            0x00000001,   /* REXT */
+            0x00000004,   /* WDV */
+            0x00000005,   /* QUSE */
+            0x00000004,   /* QRST */
+            0x00000009,   /* QSAFE */
+            0x0000000D,   /* RDV */
+            0x000009FF,   /* REFRESH */
+            0x00000000,   /* BURST_REFRESH_NUM */
+            0x00000003,   /* PDEX2WR */
+            0x00000003,   /* PDEX2RD */
+            0x00000005,   /* PCHG2PDEN */
+            0x00000005,   /* ACT2PDEN */
+            0x00000001,   /* AR2PDEN */
+            0x0000000F,   /* RW2PDEN */
+            0x000000C8,   /* TXSR */
+            0x00000003,   /* TCKE */
+            0x0000000C,   /* TFAW */
+            0x00000006,   /* TRPAB */
+            0x00000008,   /* TCLKSTABLE */
+            0x00000002,   /* TCLKSTOP */
+            0x00000000,   /* TREFBW */
+            0x00000000,   /* QUSE_EXTRA */
+            0x00000002,   /* FBIO_CFG6 */
+            0x00000000,   /* ODT_WRITE */
+            0x00000000,   /* ODT_READ */
+            0x00000083,   /* FBIO_CFG5 */
+            0xF0320303,   /* CFG_DIG_DLL */
+            0x007FC010,   /* DLL_XFORM_DQS */
+            0x00008010,   /* DLL_XFORM_QUSE */
+            0x00000000,   /* ZCAL_REF_CNT */
+            0x00000000,   /* ZCAL_WAIT_CNT */
+            0x00000000,   /* AUTO_CAL_INTERVAL */
+            0x00000000,   /* CFG_CLKTRIM_0 */
+            0x00000000,   /* CFG_CLKTRIM_1 */
+            0x00000000,   /* CFG_CLKTRIM_2 */
+        }
+    }
+};
+
+// Wake Events
+static NvOdmWakeupPadInfo s_NvOdmWakeupPadInfo[] =
+{
+    {NV_FALSE,  0, NvOdmWakeupPadPolarity_Low},     // Wake Event  0 - ulpi_data4 (UART_RI)
+    {NV_FALSE,  1, NvOdmWakeupPadPolarity_High},    // Wake Event  1 - gp3_pv[3] (BB_MOD, MODEM_RESET_OUT)
+    {NV_FALSE,  2, NvOdmWakeupPadPolarity_High},    // Wake Event  2 - dvi_d3
+    {NV_FALSE,  3, NvOdmWakeupPadPolarity_Low},     // Wake Event  3 - sdio3_dat1
+    {NV_FALSE,  4, NvOdmWakeupPadPolarity_High},    // Wake Event  4 - hdmi_int (HDMI_HPD)
+    {NV_TRUE,   5, NvOdmWakeupPadPolarity_Low},     // Wake Event  5 - vgp[6] (VI_GP6, Flash_EN2)
+    {NV_FALSE,  6, NvOdmWakeupPadPolarity_High},    // Wake Event  6 - gp3_pu[5] (GPS_ON_OFF, GPS_IRQ)
+    {NV_FALSE,  7, NvOdmWakeupPadPolarity_AnyEdge}, // Wake Event  7 - gp3_pu[6] (GPS_INT, BT_IRQ)
+    {NV_FALSE,  8, NvOdmWakeupPadPolarity_AnyEdge}, // Wake Event  8 - gmi_wp_n (MICRO SD_CD)
+    {NV_FALSE,  9, NvOdmWakeupPadPolarity_High},    // Wake Event  9 - gp3_ps[2] (KB_COL10)
+    {NV_FALSE, 10, NvOdmWakeupPadPolarity_High},    // Wake Event 10 - gmi_ad21 (Accelerometer_TH/TAP)
+    {NV_TRUE,  11, NvOdmWakeupPadPolarity_Low},     // Wake Event 11 - spi2_cs2 (PEN_INT, AUDIO-IRQ, LOW_BAT#)
+    {NV_FALSE, 12, NvOdmWakeupPadPolarity_Low},     // Wake Event 12 - spi2_cs1 (HEADSET_DET, not used)
+    {NV_FALSE, 13, NvOdmWakeupPadPolarity_Low},     // Wake Event 13 - sdio1_dat1
+    {NV_FALSE, 14, NvOdmWakeupPadPolarity_High},    // Wake Event 14 - gp3_pv[6] (WLAN_INT)
+    {NV_FALSE, 15, NvOdmWakeupPadPolarity_AnyEdge}, // Wake Event 15 - gmi_ad16  (SPI3_DOUT, DTV_SPI4_CS1)
+    {NV_TRUE,  16, NvOdmWakeupPadPolarity_High},    // Wake Event 16 - rtc_irq
+#ifdef CONFIG_KEYBOARD_TEGRA
+    {NV_TRUE,  17, NvOdmWakeupPadPolarity_High},    // Wake Event 17 - kbc_interrupt
+#else
+    {NV_FALSE, 17, NvOdmWakeupPadPolarity_High},
+#endif
+    {NV_FALSE, 18, NvOdmWakeupPadPolarity_Low},     // Wake Event 18 - pwr_int (PMIC_INT)
+    {NV_FALSE, 19, NvOdmWakeupPadPolarity_AnyEdge}, // Wake Event 19 - usb_vbus_wakeup[0]
+    {NV_FALSE, 20, NvOdmWakeupPadPolarity_High},    // Wake Event 20 - usb_vbus_wakeup[1]
+    {NV_FALSE, 21, NvOdmWakeupPadPolarity_Low},     // Wake Event 21 - usb_iddig[0]
+    {NV_FALSE, 22, NvOdmWakeupPadPolarity_Low},     // Wake Event 22 - usb_iddig[1]
+    {NV_TRUE,  23, NvOdmWakeupPadPolarity_AnyEdge}, // Wake Event 23 - gmi_iordy (HSMMC_CLK)
+    {NV_FALSE, 24, NvOdmWakeupPadPolarity_High},    // Wake Event 24 - gp3_pv[2] (BB_MOD, MODEM WAKEUP_AP15, SPI-SS)
+    {NV_FALSE, 25, NvOdmWakeupPadPolarity_High},    // Wake Event 25 - gp3_ps[4] (KB_COL12)
+    {NV_FALSE, 26, NvOdmWakeupPadPolarity_High},    // Wake Event 26 - gp3_ps[5] (KB_COL10)
+    {NV_FALSE, 27, NvOdmWakeupPadPolarity_High},    // Wake Event 27 - gp3_ps[0] (KB_COL8)
+    {NV_FALSE, 28, NvOdmWakeupPadPolarity_Low},     // Wake Event 28 - gp3_pq[6] (KB_ROW6)
+    {NV_FALSE, 29, NvOdmWakeupPadPolarity_Low},     // Wake Event 29 - gp3_pq[7] (KB_ROW6)
+    {NV_FALSE, 30, NvOdmWakeupPadPolarity_High}     // Wake Event 30 - dap1_dout (DAP1_DOUT)
+};
+
+/* --- Function Implementations ---*/
+static NvU32
+GetBctKeyValue(void)
+{
+    NvOdmServicesKeyListHandle hKeyList = NULL;
+    NvU32 BctCustOpt = 0;
+
+    hKeyList = NvOdmServicesKeyListOpen();
+    if (hKeyList)
+    {
+        BctCustOpt =
+            NvOdmServicesGetKeyValue(hKeyList,
+                                     NvOdmKeyListId_ReservedBctCustomerOption);
+        NvOdmServicesKeyListClose(hKeyList);
+    }
+
+    return BctCustOpt;
+}
+
+NvOdmDebugConsole
+NvOdmQueryDebugConsole(void)
+{
+    NvU32 CustOpt = GetBctKeyValue();
+    switch (NV_DRF_VAL(TEGRA_DEVKIT, BCT_CUSTOPT, CONSOLE, CustOpt))
+    {
+    case TEGRA_DEVKIT_BCT_CUSTOPT_0_CONSOLE_DEFAULT:
+    case TEGRA_DEVKIT_BCT_CUSTOPT_0_CONSOLE_DCC:
+        return NvOdmDebugConsole_Dcc;
+    case TEGRA_DEVKIT_BCT_CUSTOPT_0_CONSOLE_NONE:
+        return NvOdmDebugConsole_None;
+    case TEGRA_DEVKIT_BCT_CUSTOPT_0_CONSOLE_UART:
+        return NvOdmDebugConsole_UartA +
+            NV_DRF_VAL(TEGRA_DEVKIT, BCT_CUSTOPT, CONSOLE_OPTION, CustOpt);
+    default:
+        return NvOdmDebugConsole_None;
+    }
+}
+
+NvOdmDownloadTransport
+NvOdmQueryDownloadTransport(void)
+{
+    NvU32 CustOpt = GetBctKeyValue();
+
+    switch (NV_DRF_VAL(TEGRA_DEVKIT, BCT_CUSTOPT, TRANSPORT, CustOpt))
+    {
+    case TEGRA_DEVKIT_BCT_CUSTOPT_0_TRANSPORT_NONE:
+        return NvOdmDownloadTransport_None;
+    case TEGRA_DEVKIT_BCT_CUSTOPT_0_TRANSPORT_USB:
+        return NvOdmDownloadTransport_Usb;
+    case TEGRA_DEVKIT_BCT_CUSTOPT_0_TRANSPORT_ETHERNET:
+        switch (NV_DRF_VAL(TEGRA_DEVKIT, BCT_CUSTOPT, ETHERNET_OPTION, CustOpt))
+        {
+        case TEGRA_DEVKIT_BCT_CUSTOPT_0_ETHERNET_OPTION_SPI:
+        case TEGRA_DEVKIT_BCT_CUSTOPT_0_ETHERNET_OPTION_DEFAULT:
+        default:
+            return NvOdmDownloadTransport_SpiEthernet;
+        }
+    case TEGRA_DEVKIT_BCT_CUSTOPT_0_TRANSPORT_UART:
+        switch (NV_DRF_VAL(TEGRA_DEVKIT, BCT_CUSTOPT, UART_OPTION, CustOpt))
+        {
+        case TEGRA_DEVKIT_BCT_CUSTOPT_0_UART_OPTION_B:
+            return NvOdmDownloadTransport_UartB;
+        case TEGRA_DEVKIT_BCT_CUSTOPT_0_UART_OPTION_C:
+            return NvOdmDownloadTransport_UartC;
+        case TEGRA_DEVKIT_BCT_CUSTOPT_0_UART_OPTION_DEFAULT:
+        case TEGRA_DEVKIT_BCT_CUSTOPT_0_UART_OPTION_A:
+        default:
+            return NvOdmDownloadTransport_UartA;
+        }
+    case TEGRA_DEVKIT_BCT_CUSTOPT_0_TRANSPORT_DEFAULT:
+    default:
+        return s_NvOdmQueryDownloadTransportSetting;
+    }
+}
+
+const NvU8*
+NvOdmQueryDeviceNamePrefix(void)
+{
+    return s_NvOdmQueryDeviceNamePrefixValue;
+}
+
+const NvOdmQuerySpiDeviceInfo *
+NvOdmQuerySpiGetDeviceInfo(
+    NvOdmIoModule OdmIoModule,
+    NvU32 ControllerId,
+    NvU32 ChipSelect)
+{
+    if (OdmIoModule == NvOdmIoModule_Spi)
+    {
+        switch (ControllerId)
+        {
+            case 0:
+                if (ChipSelect == 0)
+                    return &s_NvOdmQuerySpiDeviceInfoTable[0];
+                break;
+
+            default:
+                break;
+        }
+        return NULL;
+    }
+    return NULL;
+}
+
+const NvOdmQuerySpiIdleSignalState *
+NvOdmQuerySpiGetIdleSignalState(
+    NvOdmIoModule OdmIoModule,
+    NvU32 ControllerId)
+{
+    if (OdmIoModule == NvOdmIoModule_Spi)
+    {
+        if (ControllerId == 0)
+            return &s_NvOdmQuerySpiIdleSignalStateLevel[0];
+    }
+    return NULL;
+}
+
+const NvOdmQueryI2sInterfaceProperty *
+NvOdmQueryI2sGetInterfaceProperty(
+    NvU32 I2sInstanceId)
+{
+    if ((I2sInstanceId == 0) || (I2sInstanceId == 1))
+        return &s_NvOdmQueryI2sInterfacePropertySetting[I2sInstanceId];
+
+    return NULL;
+}
+
+const NvOdmQueryDapPortProperty *
+NvOdmQueryDapPortGetProperty(
+    NvU32 DapPortId)
+{
+    if (DapPortId > 0 && DapPortId < NV_ARRAY_SIZE(s_NvOdmQueryDapPortInfoTable) )
+        return &s_NvOdmQueryDapPortInfoTable[DapPortId];
+
+    return NULL;
+}
+
+const NvOdmQueryDapPortConnection*
+NvOdmQueryDapPortGetConnectionTable(
+    NvU32 ConnectionIndex)
+{
+    NvU32 TableIndex   = 0;
+    for( TableIndex = 0; 
+         TableIndex < NV_ARRAY_SIZE(s_NvOdmQueryDapPortConnectionTable);
+         TableIndex++)
+    {
+        if (s_NvOdmQueryDapPortConnectionTable[TableIndex].UseIndex 
+                                                    == ConnectionIndex)
+            return &s_NvOdmQueryDapPortConnectionTable[TableIndex];
+    }
+    return NULL;
+}
+
+const NvOdmQuerySpdifInterfaceProperty *
+NvOdmQuerySpdifGetInterfaceProperty(
+    NvU32 SpdifInstanceId)
+{
+    if (SpdifInstanceId == 0)
+        return &s_NvOdmQuerySpdifInterfacePropertySetting;
+
+    return NULL;
+}
+
+const NvOdmQueryAc97InterfaceProperty *
+NvOdmQueryAc97GetInterfaceProperty(
+    NvU32 Ac97InstanceId)
+{
+    if (Ac97InstanceId == 0)
+        return &s_NvOdmQueryAc97InterfacePropertySetting;
+
+    return NULL;
+}
+
+const NvOdmQueryI2sACodecInterfaceProp *
+NvOdmQueryGetI2sACodecInterfaceProperty(
+    NvU32 AudioCodecId)
+{
+    NvU32 NumInstance = sizeof(s_NvOdmQueryI2sACodecInterfacePropSetting)/
+                            sizeof(s_NvOdmQueryI2sACodecInterfacePropSetting[0]);
+    if (AudioCodecId < NumInstance)
+        return &s_NvOdmQueryI2sACodecInterfacePropSetting[AudioCodecId];
+
+    return NULL;
+}
+
+/**
+ * This function is called from early boot process.
+ * Therefore, it cannot use global variables.
+ */
+NvBool NvOdmQueryAsynchMemConfig(
+    NvU32 ChipSelect,
+    NvOdmAsynchMemConfig *pMemConfig)
+{
+    return NV_FALSE;
+}
+
+const void*
+NvOdmQuerySdramControllerConfigGet(NvU32 *pEntries, NvU32 *pRevision)
+{
+#if NVODM_ENABLE_EMC_DVFS
+    NvOdmBoardInfo BoardInfo;
+
+    if (NvOdmPeripheralGetBoardInfo(BOARD_ID_HARMONY, &BoardInfo))
+    {
+        if (BoardInfo.SKU == HARMONY_HYS5C1GB_SKU)
+        {
+            if (pRevision)
+                *pRevision = s_NvOdmHyS5c1GbEmcConfigTable[0].Revision;
+            if (pEntries)
+                *pEntries = NV_ARRAY_SIZE(s_NvOdmHyS5c1GbEmcConfigTable);
+            return (const void*)s_NvOdmHyS5c1GbEmcConfigTable;
+        }
+    }
+#endif
+    if (pEntries)
+        *pEntries = 0;
+    return NULL;
+}
+
+NvOdmQueryOscillator NvOdmQueryGetOscillatorSource(void)
+{
+    return NvOdmQueryOscillator_Xtal;
+}
+
+NvU32 NvOdmQueryGetOscillatorDriveStrength(void)
+{
+    /// Oscillator drive strength range is 0 to 0x3F
+    return 0x04;
+}
+
+const NvOdmWakeupPadInfo *NvOdmQueryGetWakeupPadTable(NvU32 *pSize)
+{
+    if (pSize)
+        *pSize = NV_ARRAY_SIZE(s_NvOdmWakeupPadInfo);
+
+    return (const NvOdmWakeupPadInfo *) s_NvOdmWakeupPadInfo;
+}
+
+const NvU8* NvOdmQueryManufacturer(void)
+{
+    return s_NvOdmQueryManufacturerSetting;
+}
+
+const NvU8* NvOdmQueryModel(void)
+{
+    return s_NvOdmQueryModelSetting;
+}
+
+const NvU8* NvOdmQueryPlatform(void)
+{
+    return s_NvOdmQueryPlatformSetting;
+}
+
+const NvU8* NvOdmQueryProjectName(void)
+{
+    return s_NvOdmQueryProjectNameSetting;
+}
+
+#define EXT 0     // external pull-up/down resistor
+#define INT_PU 1  // internal pull-up
+#define INT_PD 2  // internal pull-down
+
+#define HIGHSPEED 1
+#define SCHMITT 1
+#define VREF    1
+#define OHM_50 3
+#define OHM_100 2
+#define OHM_200 1
+#define OHM_400 0
+
+ // Pin attributes
+static const NvOdmPinAttrib pin_config[] = {
+    // Pull ups for the kbc pins
+    { NvOdmPinRegister_Ap20_PullUpDown_B,
+     NVODM_QUERY_PIN_AP20_PULLUPDOWN_B(0x0, 0x0, 0x0, 0x0, 0x2, 0x2, 0x2, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0) },
+
+    // Pull ups for the kbc pins
+    { NvOdmPinRegister_Ap20_PullUpDown_E,
+     NVODM_QUERY_PIN_AP20_PULLUPDOWN_E(0x2, 0x2, 0x0, 0x0, 0x0, 0x0, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x2, 0x0, 0x2, 0x2) },
+
+    // Set pad control for the sdio2 - - AOCFG1 and AOCFG2 pad control register
+    { NvOdmPinRegister_Ap20_PadCtrl_AOCFG1PADCTRL,
+      NVODM_QUERY_PIN_AP20_PADCTRL_AOCFG1PADCTRL(!HIGHSPEED, SCHMITT, OHM_50, 31, 31, 3, 3) },
+
+    { NvOdmPinRegister_Ap20_PadCtrl_AOCFG2PADCTRL,
+      NVODM_QUERY_PIN_AP20_PADCTRL_AOCFG1PADCTRL(!HIGHSPEED, SCHMITT, OHM_50, 31, 31, 3, 3) },
+
+    // Set pad control for the sdio3 - SDIO2 and SDIO3 pad control register
+    { NvOdmPinRegister_Ap20_PadCtrl_SDIO2CFGPADCTRL,
+      NVODM_QUERY_PIN_AP20_PADCTRL_AOCFG1PADCTRL(!HIGHSPEED, SCHMITT, OHM_50, 31, 31, 3, 3) },
+
+    { NvOdmPinRegister_Ap20_PadCtrl_SDIO3CFGPADCTRL,
+      NVODM_QUERY_PIN_AP20_PADCTRL_AOCFG1PADCTRL(!HIGHSPEED, SCHMITT, OHM_50, 31, 31, 3, 3) },
+
+    // Set pad control for I2C1 pins
+    { NvOdmPinRegister_Ap20_PadCtrl_DBGCFGPADCTRL,
+      NVODM_QUERY_PIN_AP20_PADCTRL_AOCFG1PADCTRL(!HIGHSPEED, SCHMITT, OHM_50, 31, 31, 3, 3) },
+
+    { NvOdmPinRegister_Ap20_PadCtrl_VICFG1PADCTRL,
+      NVODM_QUERY_PIN_AP20_PADCTRL_AOCFG1PADCTRL(!HIGHSPEED, SCHMITT, OHM_50, 31, 31, 3, 3) },
+
+    { NvOdmPinRegister_Ap20_PadCtrl_VICFG2PADCTRL,
+      NVODM_QUERY_PIN_AP20_PADCTRL_AOCFG1PADCTRL(!HIGHSPEED, SCHMITT, OHM_50, 31, 31, 3, 3) },
+
+    // Set pad control for I2C2 (DDC) pins
+    { NvOdmPinRegister_Ap20_PadCtrl_DDCCFGPADCTRL,
+      NVODM_QUERY_PIN_AP20_PADCTRL_AOCFG1PADCTRL(!HIGHSPEED, SCHMITT, OHM_50, 31, 31, 3, 3) },
+
+    // Set pad control for the sdio1 - SDIO1 pad control register
+    { NvOdmPinRegister_Ap20_PadCtrl_SDIO1CFGPADCTRL,
+      NVODM_QUERY_PIN_AP20_PADCTRL_AOCFG1PADCTRL(!HIGHSPEED, SCHMITT, OHM_50, 31, 31, 3, 3) },
+
+     // WiFi Pins (DTA, DTD) need to be pulled up
+    { NvOdmPinRegister_Ap20_PullUpDown_A,
+      NVODM_QUERY_PIN_AP20_PULLUPDOWN_A(0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x2, 0x0, 0x0, 0x2, 0x0, 0x0, 0x0) },
+
+    // Set pad control for the sdio4- ATCCFG1 and ATCCFG2 pad control register
+    { NvOdmPinRegister_Ap20_PadCtrl_ATCFG1PADCTRL,
+      NVODM_QUERY_PIN_AP20_PADCTRL_AOCFG1PADCTRL(!HIGHSPEED, SCHMITT, OHM_50, 31, 31, 3, 3) },
+
+    { NvOdmPinRegister_Ap20_PadCtrl_ATCFG2PADCTRL,
+      NVODM_QUERY_PIN_AP20_PADCTRL_AOCFG1PADCTRL(!HIGHSPEED, SCHMITT, OHM_50, 31, 31, 3, 3) }
+};
+
+NvU32
+NvOdmQueryPinAttributes(const NvOdmPinAttrib** pPinAttributes)
+{
+    if (pPinAttributes)
+    {
+        *pPinAttributes = &pin_config[0];
+        return NV_ARRAY_SIZE(pin_config);
+    }
+    return 0;
+}
+
+NvBool NvOdmQueryGetPmuProperty(NvOdmPmuProperty* pPmuProperty)
+{
+    pPmuProperty->IrqConnected = NV_FALSE;
+    pPmuProperty->PowerGoodCount = 0x7E;
+    pPmuProperty->IrqPolarity = NvOdmInterruptPolarity_Low;
+    pPmuProperty->CorePowerReqPolarity = NvOdmCorePowerReqPolarity_Low;
+    pPmuProperty->SysClockReqPolarity = NvOdmSysClockReqPolarity_High;
+    pPmuProperty->CombinedPowerReq = NV_FALSE;
+    pPmuProperty->CpuPowerGoodUs = 2000;
+    pPmuProperty->AccuracyPercent = 3;
+    pPmuProperty->VCpuOTPOnWakeup = NV_FALSE;
+    return NV_TRUE;
+}
+
+/**
+ * Gets the lowest soc power state supported by the hardware
+ *
+ * @returns information about the SocPowerState
+ */
+const NvOdmSocPowerStateInfo* NvOdmQueryLowestSocPowerState(void)
+{
+
+    static                      NvOdmSocPowerStateInfo  PowerStateInfo;
+    const static                NvOdmSocPowerStateInfo* pPowerStateInfo = NULL;
+    NvOdmServicesKeyListHandle  hKeyList;
+    NvU32                       LPStateSelection = 0;
+    if (pPowerStateInfo == NULL)
+    {
+
+        hKeyList = NvOdmServicesKeyListOpen();
+        if (hKeyList)
+        {
+            LPStateSelection = NvOdmServicesGetKeyValue(hKeyList,
+                                                NvOdmKeyListId_ReservedBctCustomerOption);
+            NvOdmServicesKeyListClose(hKeyList);
+            LPStateSelection = NV_DRF_VAL(TEGRA_DEVKIT, BCT_CUSTOPT, LPSTATE, LPStateSelection);
+        }
+        // Lowest power state controlled by the flashed custom option.
+        PowerStateInfo.LowestPowerState =  ((LPStateSelection != TEGRA_DEVKIT_BCT_CUSTOPT_0_LPSTATE_LP1)?
+                                            NvOdmSocPowerState_Suspend : NvOdmSocPowerState_DeepSleep);
+        pPowerStateInfo = (const NvOdmSocPowerStateInfo*) &PowerStateInfo;
+    }
+    return (pPowerStateInfo);
+}
+
+const NvOdmUsbProperty*
+NvOdmQueryGetUsbProperty(NvOdmIoModule OdmIoModule,
+                         NvU32 Instance)
+{
+    static const NvOdmUsbProperty Usb1Property =
+    {
+        NvOdmUsbInterfaceType_Utmi,
+        (NvOdmUsbChargerType_SE0 | NvOdmUsbChargerType_SE1 | NvOdmUsbChargerType_SK),
+        20,
+        NV_TRUE,
+        NvOdmUsbModeType_Device,
+        NvOdmUsbIdPinType_CableId,
+        NvOdmUsbConnectorsMuxType_None,
+        NV_TRUE
+    };
+
+     static const NvOdmUsbProperty Usb2Property =
+     {
+        NvOdmUsbInterfaceType_UlpiExternalPhy,
+        NvOdmUsbChargerType_UsbHost,
+        20,
+        NV_TRUE,
+        NvOdmUsbModeType_Host,
+        NvOdmUsbIdPinType_None,
+        NvOdmUsbConnectorsMuxType_None,
+        NV_TRUE
+    };
+
+    static const NvOdmUsbProperty Usb3Property =
+    {
+        NvOdmUsbInterfaceType_Utmi,
+        NvOdmUsbChargerType_UsbHost,
+        20,
+        NV_TRUE,
+        NvOdmUsbModeType_Host,
+        NvOdmUsbIdPinType_None,
+        NvOdmUsbConnectorsMuxType_None,
+        NV_TRUE
+    };
+
+    if (OdmIoModule == NvOdmIoModule_Usb && Instance == 0)
+        return &(Usb1Property);
+
+    if (OdmIoModule == NvOdmIoModule_Usb && Instance == 1)
+        return &(Usb2Property);
+
+    if (OdmIoModule == NvOdmIoModule_Usb && Instance == 2)
+        return &(Usb3Property);
+
+    return (const NvOdmUsbProperty *)NULL;
+}
+
+const NvOdmQuerySdioInterfaceProperty* NvOdmQueryGetSdioInterfaceProperty(NvU32 Instance)
+{
+    return &s_NvOdmQuerySdioInterfaceProperty[Instance];
+}
+
+const NvOdmQueryHsmmcInterfaceProperty* NvOdmQueryGetHsmmcInterfaceProperty(NvU32 Instance)
+{
+    return NULL;
+}
+
+NvU32
+NvOdmQueryGetBlockDeviceSectorSize(NvOdmIoModule OdmIoModule)
+{
+    return 0;
+}
+
+const NvOdmQueryOwrDeviceInfo* NvOdmQueryGetOwrDeviceInfo(NvU32 Instance)
+{
+    return NULL;
+}
+
+const NvOdmGpioWakeupSource *NvOdmQueryGetWakeupSources(NvU32 *pCount)
+{
+    *pCount = 0;
+    return NULL;
+}
+
+/**
+ * This function is called from early boot process.
+ * Therefore, it cannot use global variables.
+ */
+NvU32 NvOdmQueryMemSize(NvOdmMemoryType MemType)
+{
+    NvOdmOsOsInfo Info;
+    NvU32 MemBctCustOpt = GetBctKeyValue();
+
+    switch (MemType)
+    {
+        // NOTE:
+        // For Windows CE/WM operating systems the total size of SDRAM may
+        // need to be reduced due to limitations in the virtual address map.
+        // Under the legacy physical memory manager, Windows OSs have a
+        // maximum 512MB statically mapped virtual address space. Under the
+        // new physical memory manager, Windows OSs have a maximum 1GB
+        // statically mapped virtual address space. Out of that virtual
+        // address space, the upper 32 or 36 MB (depending upon the SOC)
+        // of the virtual address space is reserved for SOC register
+        // apertures.
+        //
+        // Refer to virtual_tables_apxx.arm for the reserved aperture list.
+        // If the cumulative size of the reserved apertures changes, the
+        // maximum size of SDRAM will also change.
+        case NvOdmMemoryType_Sdram:
+            switch (NV_DRF_VAL(TEGRA_DEVKIT, BCT_SYSTEM, MEMORY, MemBctCustOpt))
+            {
+                case TEGRA_DEVKIT_BCT_SYSTEM_0_MEMORY_256:
+                    if ( NvOdmOsGetOsInformation(&Info) &&
+                         ((Info.OsType!=NvOdmOsOs_Windows) ||
+                          (Info.OsType==NvOdmOsOs_Windows && Info.MajorVersion>=7)) )
+                        return 0x10000000;
+                    else
+                        return 0x0DD00000;  // Legacy Physical Memory Manager: 256 MB - 35 MB
+    
+                case TEGRA_DEVKIT_BCT_SYSTEM_0_MEMORY_1024:
+                    if ( NvOdmOsGetOsInformation(&Info) &&
+                         ((Info.OsType!=NvOdmOsOs_Windows) ||
+                          (Info.OsType==NvOdmOsOs_Windows && Info.MajorVersion>=7)) )
+                        return 0x40000000;
+                    else
+                        // Earlier versions of WinCE only support 512MB max memory size
+                        return 0x1E000000;  // Legacy Physical Memory Manager: 512 MB - 32 MB
+
+                case TEGRA_DEVKIT_BCT_SYSTEM_0_MEMORY_512:
+                case TEGRA_DEVKIT_BCT_SYSTEM_0_MEMORY_DEFAULT:
+                default:
+                    if ( NvOdmOsGetOsInformation(&Info) &&
+                         ((Info.OsType!=NvOdmOsOs_Windows) ||
+                          (Info.OsType==NvOdmOsOs_Windows && Info.MajorVersion>=7)) )
+                        return 0x20000000;
+                    else
+                        return 0x1E000000;  // Legacy Physical Memory Manager: 512 MB - 32 MB
+            }
+
+        case NvOdmMemoryType_Nor:
+            return 0x00400000;  // 4 MB
+
+        case NvOdmMemoryType_Nand:
+        case NvOdmMemoryType_I2CEeprom:
+        case NvOdmMemoryType_Hsmmc:
+        case NvOdmMemoryType_Mio:
+        default:
+            return 0;
+    }
+}
+
+NvU32 NvOdmQueryCarveoutSize(void)
+{
+    return 0x04000000;  // 64 MB
+}
+
+NvU32 NvOdmQuerySecureRegionSize(void)
+{
+    return 0x00800000;// 8 MB
+}
diff --git a/arch/arm/mach-tegra/odm_kit/query/harmony/nvodm_query_discovery.c b/arch/arm/mach-tegra/odm_kit/query/harmony/nvodm_query_discovery.c
new file mode 100644
index 000000000000..6b0b896d0cf3
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/query/harmony/nvodm_query_discovery.c
@@ -0,0 +1,770 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/**
+ * @file
+ * <b>NVIDIA APX ODM Kit::
+ *         Implementation of the ODM Peripheral Discovery API</b>
+ *
+ * @b Description: The peripheral connectivity database implementation.
+ */
+
+#include "nvcommon.h"
+#include "nvodm_query_gpio.h"
+#include "nvodm_modules.h"
+#include "nvodm_query_discovery.h"
+#include "nvodm_keylist_reserved.h"
+#include "tegra_devkit_custopt.h"
+#include "nvodm_query.h"
+#include "nvrm_drf.h"
+
+#include "subboards/nvodm_query_discovery_e1162_addresses.h"
+
+static NvOdmPeripheralConnectivity s_Peripherals_Default[] =
+{
+#include "subboards/nvodm_query_discovery_e1162_peripherals.h"
+};
+
+#define NVODM_QUERY_BOARD_ID_UNKNOWN    0xFFFF
+
+#define NVODM_QUERY_MAX_PERIPHERALS     0x400
+#define NVODM_QUERY_MAX_IO_ADDRESSES    0x400
+
+#define NVODM_QUERY_MAX_EEPROMS         8   // Maximum number of EEPROMs per bus segment
+
+#define NVODM_QUERY_ERASED_EEPROM_VALUE 0xFF
+
+#define PROCESSOR_BOARD_ID_I2C_ADDRESS ((0x56)<<1)
+#define PROCESSOR_BOARD_ID_I2C_SEGMENT (0x00)
+
+// The following are used to store entries read from EEPROMs at runtime.
+static NvOdmPeripheralConnectivity s_Peripherals[NVODM_QUERY_MAX_PERIPHERALS];
+static NvOdmIoAddress s_Peripheral_IoAddresses[NVODM_QUERY_MAX_IO_ADDRESSES];
+static NvOdmBoardInfo s_BoardModuleTable[NVODM_QUERY_MAX_EEPROMS];
+
+#define NVODM_QUERY_I2C_CLOCK_SPEED      100    // kHz
+
+#define NVODM_QUERY_ENTRY_HEADER_SIZE    0x30   // Size of EERPOM "Entry Header"
+#define NVODM_QUERY_BOARD_HEADER_START   0x04   // Offset to Part Number in EERPOM
+
+#define NVODM_QUERY_I2C_EEPROM_ADDRESS   0xA0   // I2C device base address for EEPROM (7'h50)
+
+#define NVODM_QUERY_PERIPH_CONN_STRUCT_COMPRESSED   10  // See EEPROM_format.txt
+#define NVODM_PERIPH_IO_ADDR_STRUCT_SZ_COMPRESSED   2   // See EEPROM_format.txt
+
+
+static NvOdmI2cStatus
+NvOdmPeripheralI2cRead8(
+    NvOdmServicesI2cHandle hOdmI2c,
+    NvU8 I2cAddr,
+    NvU8 Offset,
+    NvU8 *pData)
+{
+    NvU8 ReadBuffer[1];
+    NvOdmI2cStatus Error;    
+    NvOdmI2cTransactionInfo TransactionInfo;
+
+    ReadBuffer[0] = Offset;
+
+    TransactionInfo.Address = I2cAddr;
+    TransactionInfo.Buf = ReadBuffer;
+    TransactionInfo.Flags = NVODM_I2C_IS_WRITE;
+    TransactionInfo.NumBytes = 1;
+
+    Error = NvOdmI2cTransaction(
+        hOdmI2c, &TransactionInfo, 1, NVODM_QUERY_I2C_CLOCK_SPEED, NV_WAIT_INFINITE);
+    if (Error != NvOdmI2cStatus_Success)
+    {
+        return Error;
+    }
+
+    NvOdmOsMemset(ReadBuffer, 0, sizeof(ReadBuffer));  
+
+    TransactionInfo.Address = (I2cAddr | 0x1);
+    TransactionInfo.Buf = ReadBuffer;
+    TransactionInfo.Flags = 0;
+    TransactionInfo.NumBytes = 1;
+
+    // Read data from ROM at the specified offset
+    Error = NvOdmI2cTransaction(
+        hOdmI2c, &TransactionInfo, 1, NVODM_QUERY_I2C_CLOCK_SPEED, NV_WAIT_INFINITE);
+    if (Error != NvOdmI2cStatus_Success)
+    {
+        return Error;
+    }
+    *pData = ReadBuffer[0];
+    return Error;
+}
+
+static NvBool
+NvOdmPeripheralReadNumPeripherals(
+    NvOdmServicesI2cHandle hOdmI2c,
+    NvU8 EepromInst,
+    NvU8 *pNumModulePeripherals)
+{
+    NvOdmI2cStatus Error;    
+    NvU8 I2cAddr, Offset;
+
+    // EepromInst*2, since 7-bit addressing
+    I2cAddr = NVODM_QUERY_I2C_EEPROM_ADDRESS + (EepromInst << 1);
+
+    /**
+     * Offset to numPeripherals in NvOdmPeripheralConnectivity Structure.
+     * It's the first parameter after the "Entry Header."
+     */
+    Offset = NVODM_QUERY_ENTRY_HEADER_SIZE;
+
+    Error = NvOdmPeripheralI2cRead8(
+        hOdmI2c, I2cAddr, Offset, pNumModulePeripherals);
+    if (Error != NvOdmI2cStatus_Success)
+    {
+        return NV_FALSE;
+    }
+    return NV_TRUE;
+}
+
+static NvBool
+NvOdmPeripheralReadPeripheral(
+    NvOdmServicesI2cHandle hOdmI2c,
+    NvU8 EepromInst,
+    NvU8 Peripheral,
+    NvU64 *pGuid,
+    NvU8 *pEepromAddressListOffset,
+    NvU32 *pNumAddress,
+    NvOdmPeripheralClass *pClass)
+{
+    NvOdmI2cStatus Error;    
+    NvU32 i;
+    NvU8 ConnMemberIndex=0; // Offset to members in NvOdmPeripheralConnectivity
+    NvU8 I2cAddr, Offset;
+    NvU8 ReadBuffer[NVODM_QUERY_PERIPH_CONN_STRUCT_COMPRESSED];
+    NvU8 NumAddrAndClass;
+
+    // EepromInst*2, since 7-bit addressing
+    I2cAddr = NVODM_QUERY_I2C_EEPROM_ADDRESS + (EepromInst << 1);
+
+    /**
+     * Calculate offset to pGuid in NvOdmPeripheralConnectivity Structure
+     * 
+     *  Offset = sizeof(eeprom Entry Header) + 
+     *           sizeof(NvOdmPeripheralConnectivity)*peripheral + 
+     *           pGuid offset    <-- First field, so this is 0
+     */
+    Offset = NVODM_QUERY_ENTRY_HEADER_SIZE + 
+        sizeof(NvOdmPeripheralConnectivity)*Peripheral;
+
+    for (i=0; i<NVODM_QUERY_PERIPH_CONN_STRUCT_COMPRESSED; i++)
+    {
+        Error = NvOdmPeripheralI2cRead8(
+            hOdmI2c, I2cAddr, Offset, (NvU8 *)&ReadBuffer[i]);
+        if (Error != NvOdmI2cStatus_Success)
+        {
+            return NV_FALSE;
+        }
+    }
+    // Save pGuid entry
+    NvOdmOsMemcpy(pGuid, &ReadBuffer[0], sizeof(NvU64));
+
+    // Save EEPROM offset
+    ConnMemberIndex += sizeof(NvU64); // Increment to next member
+    *pEepromAddressListOffset = ReadBuffer[ConnMemberIndex];
+
+    // Save pNumAddress & Class
+    ConnMemberIndex += sizeof(NvU8); // Increment to next member
+    NumAddrAndClass = ReadBuffer[ConnMemberIndex];
+    *pNumAddress = (NvU32)((NumAddrAndClass >> 3) & 0x0000001F);
+    *pClass = (NvOdmPeripheralClass)(NumAddrAndClass & 0x00000007);
+
+    return NV_TRUE;
+}
+
+static NvBool
+NvOdmPeripheralReadIoAddressData(
+    NvOdmServicesI2cHandle hOdmI2c,
+    NvU8 EepromInst,
+    NvU8 EepromAddressListOffset,
+    NvOdmIoAddress *pIoAddressEntry)
+{
+    NvOdmI2cStatus Error;    
+    NvU32 i;
+    NvU8 I2cAddr;
+    NvU8 ReadBuffer[NVODM_PERIPH_IO_ADDR_STRUCT_SZ_COMPRESSED];
+    NvU16 CompressedIoAddressEntry;
+
+    // EepromInst*2, since 7-bit addressing
+    I2cAddr = NVODM_QUERY_I2C_EEPROM_ADDRESS + (EepromInst << 1);
+
+    for (i=0; i<NVODM_PERIPH_IO_ADDR_STRUCT_SZ_COMPRESSED; i++)
+    {
+        Error = NvOdmPeripheralI2cRead8(
+            hOdmI2c, I2cAddr, EepromAddressListOffset, (NvU8 *)&ReadBuffer[i]);
+        if (Error != NvOdmI2cStatus_Success)
+        {
+            return NV_FALSE;
+        }
+    }
+    // Save pIoAddressEntry: interface, instance, address
+    CompressedIoAddressEntry = ((((NvU16)ReadBuffer[1]) << 8) & 0xFF00) | ReadBuffer[0];
+
+    pIoAddressEntry->Interface = (NvOdmIoModule)((CompressedIoAddressEntry >> 11) & 0x1F);
+
+    if (pIoAddressEntry->Interface != NvOdmIoModule_Gpio)
+    {
+        pIoAddressEntry->Instance = (NvU32)((CompressedIoAddressEntry >> 7) & 0xF);
+        pIoAddressEntry->Address = (NvU32)(CompressedIoAddressEntry & 0x7F);
+    }
+    else
+    {
+        pIoAddressEntry->Address = (NvU32)((CompressedIoAddressEntry >> 6) & 0x3F);
+        pIoAddressEntry->Instance = (NvU32)(CompressedIoAddressEntry & 0x3F);
+    }
+
+    return NV_TRUE;
+}
+
+static NvBool NvOdmPeripheralGetEntries(NvU32 *pNum)
+{
+    NvBool RetVal;
+    NvBool IsMatch = NV_FALSE;
+    NvOdmServicesI2cHandle hOdmI2c = NULL;
+    NvU8 EepromInst;
+
+    // Peripheral counters
+    NvU8 NumPeripherals = 0;
+    NvU8 CurrentPeripheral = 0;
+    NvU32 TotalPeripherals = 0;
+    NvU32 StaticPeripherals;
+
+    NvU32 CurrentIoAddressNum = 0;
+    NvU32 TotalIoAddressEntries = 0;
+
+    NvU32 i,j;
+    NvU8 EepromAddressListOffset;
+
+    if (!pNum) {
+        return NV_FALSE;
+    }
+
+    // Auto-detect -- Read I2C-EEPROMs on each sub-board
+
+    hOdmI2c = NvOdmI2cOpen(NvOdmIoModule_I2c_Pmu, 0);
+    if (!hOdmI2c)
+        return NV_FALSE;
+
+    for (EepromInst=0; EepromInst < NVODM_QUERY_MAX_EEPROMS; EepromInst++)
+    {
+        RetVal = NvOdmPeripheralReadNumPeripherals(
+            hOdmI2c, EepromInst, &NumPeripherals);
+
+        if ( (RetVal == NV_TRUE) &&
+             (NumPeripherals != NVODM_QUERY_ERASED_EEPROM_VALUE) )
+        {
+            if (NumPeripherals > 0)
+            {
+                if ((NumPeripherals + TotalPeripherals) > NVODM_QUERY_MAX_PERIPHERALS)
+                {
+                    NV_ASSERT( !"ERROR: s_Peripherals[] is too small to accommodate entries!" );
+
+                    // Break out of loop and use static/default configuration
+                    break;
+                }
+
+                for (CurrentPeripheral=0; \
+                      CurrentPeripheral < NumPeripherals; \
+                      CurrentPeripheral++)
+                {
+                    RetVal = NvOdmPeripheralReadPeripheral(
+                        hOdmI2c,
+                        EepromInst,
+                        CurrentPeripheral,
+                        &s_Peripherals[TotalPeripherals+CurrentPeripheral].Guid,
+                        &EepromAddressListOffset,
+                        &s_Peripherals[TotalPeripherals+CurrentPeripheral].NumAddress,
+                        &s_Peripherals[TotalPeripherals+CurrentPeripheral].Class);
+
+                    if (RetVal == NV_FALSE)
+                    {
+                        NV_ASSERT(!"Unable to read EEPROM peripheral entry!");
+                        break;  // Go to next EEPROM
+                    }
+                    else // Process peripheral entry
+                    {
+                        /**
+                         * Process NvOdmIoAddress arrays --
+                         * 
+                         * These are separate data structures.  The addressList value
+                         * read from the EEPROM (EepromAddressListOffset) represents
+                         * an offset address within the I2C-EEPROM.  This offset value
+                         * identifies where to find the first instance of the
+                         * NvOdmIoAddress data.
+                         * 
+                         * The total number of NvOdmIoAddress entries is identified
+                         * by the numAddress variable following the addressList entry
+                         * in EEPROM.
+                         * 
+                         * Once the offset and number of entries are determined (from
+                         * above NvOdmPeripheralReadPeripheral function call), a loop
+                         * fills in entries within the fixed storage area
+                         * (e.g., s_Peripheral_IoAddresses) and the actual
+                         * addressList pointer is assigned a value that corresponds
+                         * to the first entry of the current class within this array.
+                         * In other words, there might be prior entries in the
+                         * s_Peripheral_IoAddresses array, but the first entry
+                         * corresponding to the current class might be the third
+                         * element in this array.  Therefore, the actual addressList
+                         * pointer for the current NvOdmPeripheralConnectivity.addressList
+                         * parameter would be the address of the third entry, which is
+                         * &s_Peripheral_IoAddresses[2] in this example.
+                         */
+
+                        // Read all of the entries and save them in s_Peripheral_IoAddresses
+                        for (CurrentIoAddressNum=0; \
+                              CurrentIoAddressNum < s_Peripherals[TotalPeripherals+CurrentPeripheral].NumAddress; \
+                              CurrentIoAddressNum++)
+                        {
+                            if (TotalIoAddressEntries > NVODM_QUERY_MAX_IO_ADDRESSES)
+                            {
+                                NV_ASSERT( !"ERROR: s_Peripheral_IoAddresses[] is too small to accommodate entries!" );
+
+                                // Cannot recover from this error.
+                                NvOdmI2cClose(hOdmI2c);
+                                return NV_FALSE;
+                            }
+
+                            RetVal = NvOdmPeripheralReadIoAddressData(
+                                hOdmI2c,
+                                EepromInst,
+                                EepromAddressListOffset,
+                                &s_Peripheral_IoAddresses[TotalIoAddressEntries+CurrentIoAddressNum]);
+
+                            if (RetVal == NV_FALSE)
+                            {
+                                NV_ASSERT(!"Unable to read EEPROM (IoAddresses)!");
+
+                                // Cannot recover from this error.
+                                NvOdmI2cClose(hOdmI2c);
+                                return NV_FALSE;
+                            }
+                            else // Process IoAddresses entry
+                            {
+                                /**
+                                 * Save the addressList pointer. This points to the first 
+                                 * IoAddresses entry of this class.  Then update the overall 
+                                 * IoAddresses array counter (TotalIoAddressEntries).
+                                 */
+                                s_Peripherals[TotalPeripherals+CurrentPeripheral].AddressList = 
+                                    &s_Peripheral_IoAddresses[TotalIoAddressEntries];
+
+                                TotalIoAddressEntries += CurrentIoAddressNum;
+
+                                // >-- End of NvOdmIoAddress array processing --<
+                            }
+                        }
+                    }
+                }
+            }
+            TotalPeripherals += NumPeripherals;
+        }
+    }
+
+    // Done reading I2C-EEPROM; close it.
+    NvOdmI2cClose(hOdmI2c);
+
+    /** 
+     *  Append static peripheral entries (if any) to dynamic list
+     *  read from EEPROMs (this list may also be empty), except for
+     *  duplicate GUIDs.  The dynamic list takes precedence when
+     *  duplicate entries are found in the static list.
+     */
+    StaticPeripherals = NV_ARRAY_SIZE(s_Peripherals_Default);
+    for (i=0; i<StaticPeripherals; i++)
+    {
+        for (j=0; j<TotalPeripherals; j++)
+        {
+            if (s_Peripherals_Default[i].Guid == s_Peripherals[j].Guid)
+            {
+                IsMatch = NV_TRUE;
+                break;  // Ignore duplicate entry from static list.
+            }
+        }
+        if (IsMatch != NV_TRUE)
+        {
+            // Append unique entry to dynamic list
+
+            s_Peripherals[TotalPeripherals].Guid = 
+                s_Peripherals_Default[i].Guid;
+
+            s_Peripherals[TotalPeripherals].AddressList = 
+                s_Peripherals_Default[i].AddressList;
+
+            s_Peripherals[TotalPeripherals].NumAddress = 
+                s_Peripherals_Default[i].NumAddress;
+
+            s_Peripherals[TotalPeripherals].Class = 
+                s_Peripherals_Default[i].Class;
+
+            TotalPeripherals++;
+        }
+    }
+    *pNum = TotalPeripherals;
+    return NV_TRUE;
+}
+
+static NvBool
+NvOdmPeripheralReadPartNumber(
+    NvOdmServicesI2cHandle hOdmI2c,
+    NvU8 EepromInst,
+    NvOdmBoardInfo *pBoardInfo)
+{
+    NvOdmI2cStatus Error;
+    NvU32 i;
+    NvU8 I2cAddr, Offset;
+    NvU8 ReadBuffer[sizeof(NvOdmBoardInfo)];
+
+    NvOdmOsMemset(ReadBuffer, 0, sizeof(ReadBuffer));  
+
+    // EepromInst*2, since 7-bit addressing
+    I2cAddr = NVODM_QUERY_I2C_EEPROM_ADDRESS + (EepromInst << 1);
+
+    /**
+     * Offset to the board number entry in EEPROM.
+     */
+    Offset = NVODM_QUERY_BOARD_HEADER_START;
+
+    for (i=0; i<sizeof(NvOdmBoardInfo); i++)
+    {
+        Error = NvOdmPeripheralI2cRead8(
+            hOdmI2c, I2cAddr, Offset+i, (NvU8 *)&ReadBuffer[i]);
+        if (Error != NvOdmI2cStatus_Success)
+        {
+            return NV_FALSE;
+        }
+    }
+    NvOdmOsMemcpy(pBoardInfo, &ReadBuffer[0], sizeof(NvOdmBoardInfo));
+    return NV_TRUE;
+}
+
+NvBool
+NvOdmPeripheralGetBoardInfo(
+    NvU16 BoardId,
+    NvOdmBoardInfo *pBoardInfo)
+{
+    NvBool RetVal = NV_FALSE;
+    NvOdmServicesI2cHandle hOdmI2c = NULL;
+    NvU8 EepromInst, CurrentBoard;
+    static NvU8 NumBoards = 0;
+    static NvBool s_ReadBoardInfoDone = NV_FALSE;
+
+    if (!s_ReadBoardInfoDone)
+    {
+        s_ReadBoardInfoDone = NV_TRUE;
+        hOdmI2c = NvOdmI2cOpen(NvOdmIoModule_I2c_Pmu, 0);
+        if (!hOdmI2c)
+        {
+            // Exit
+            pBoardInfo = NULL;
+            return NV_FALSE;
+        }
+
+        for (EepromInst=0; EepromInst < NVODM_QUERY_MAX_EEPROMS; EepromInst++)
+        {
+            RetVal = NvOdmPeripheralReadPartNumber(
+                    hOdmI2c, EepromInst, &s_BoardModuleTable[NumBoards]);
+            if (RetVal == NV_TRUE)
+                NumBoards++;
+        }
+        NvOdmI2cClose(hOdmI2c);
+    }
+
+    if (NumBoards)
+    {
+        // Linear search for given BoardId; if found, return entry
+        for (CurrentBoard=0; CurrentBoard < NumBoards; CurrentBoard++)
+        {
+            if (s_BoardModuleTable[CurrentBoard].BoardID == BoardId)
+            {
+                // Match found
+                pBoardInfo->BoardID  = s_BoardModuleTable[CurrentBoard].BoardID;
+                pBoardInfo->SKU      = s_BoardModuleTable[CurrentBoard].SKU;
+                pBoardInfo->Fab      = s_BoardModuleTable[CurrentBoard].Fab;
+                pBoardInfo->Revision = s_BoardModuleTable[CurrentBoard].Revision;
+                pBoardInfo->MinorRevision = s_BoardModuleTable[CurrentBoard].MinorRevision;
+                return NV_TRUE;
+            }           
+        }
+    }
+
+    // Match not found
+    pBoardInfo = NULL;
+    return NV_FALSE;
+}
+
+// This will compare the peripheral GUID against a list of known-bad GUIDs
+// for certain development kit personalities, and return NV_TRUE if it is
+// known to be unsupported (filtered) on the current configuration
+static NvBool
+NvIsFilteredPeripheral(const NvOdmPeripheralConnectivity* pConnectivity)
+{
+    NvOdmServicesKeyListHandle hKeyList;
+    NvU32 Personality = 0;
+    NvU32 opt = 0;
+    NvOdmIoModule OdmModule;
+    const NvU32 *OdmConfigs=NULL;
+    NvU32 NumOdmConfigs = 0;
+    const NvOdmPeripheralConnectivity* pFilteredPeriph = pConnectivity;
+
+    if((!pConnectivity) || (!pConnectivity->NumAddress))
+        return NV_TRUE;
+
+    hKeyList = NvOdmServicesKeyListOpen();
+
+    if (hKeyList)
+    {
+        Personality =
+            NvOdmServicesGetKeyValue(hKeyList,
+                                     NvOdmKeyListId_ReservedBctCustomerOption);
+        NvOdmServicesKeyListClose(hKeyList);
+        Personality = 
+            NV_DRF_VAL(TEGRA_DEVKIT, BCT_CUSTOPT, PERSONALITY, Personality);
+        opt =
+            NV_DRF_VAL(TEGRA_DEVKIT, BCT_CUSTOPT, DISPLAY_OPTION, opt);
+    }
+
+    if (!Personality)
+        Personality = TEGRA_DEVKIT_DEFAULT_PERSONALITY;
+
+    OdmModule = pFilteredPeriph->AddressList[0].Interface;
+
+    if(OdmModule != NvOdmIoModule_Gpio)
+        NvOdmQueryPinMux(OdmModule, &OdmConfigs, &NumOdmConfigs);
+
+    switch (OdmModule)
+    {
+    case NvOdmIoModule_Gpio:
+        // Filter scroll wheel when trace is enabled
+        if ( (pConnectivity->Guid == NV_ODM_GUID('s','c','r','o','l','w','h','l')) &&
+             ((Personality == TEGRA_DEVKIT_BCT_CUSTOPT_0_PERSONALITY_11) ||
+              (Personality == TEGRA_DEVKIT_BCT_CUSTOPT_0_PERSONALITY_15) ||
+              (Personality == TEGRA_DEVKIT_BCT_CUSTOPT_0_PERSONALITY_C1)) )
+            return NV_TRUE;
+        else
+            return NV_FALSE;
+
+    default:
+        return NV_FALSE;
+    }
+}
+
+static const NvOdmPeripheralConnectivity* 
+NvApGetAllPeripherals (NvU32 *pNum)
+{
+    static NvBool s_AutoDetectDone = NV_FALSE;
+    NvBool RetVal = NV_TRUE;
+    static NvU32 s_TotalPeripherals;
+    NvOdmBoardInfo BoardInfo;
+
+    if (!pNum)
+        return NULL;
+
+    if (!s_AutoDetectDone)
+    {
+        /**
+         *  Read & cache the board ID info from the I2C-EEPROMs.  This
+         *  is necessary because once Whistler's thermal power rail is
+         *  enabled, the ID ROMs cannot be read. NvApGetAllPeripherals()
+         *  is called before that rail is enabled.
+         */
+        NvOdmPeripheralGetBoardInfo(NVODM_QUERY_BOARD_ID_UNKNOWN, &BoardInfo);
+
+        RetVal = NvOdmPeripheralGetEntries(&s_TotalPeripherals);
+        if (RetVal == NV_FALSE)
+        {
+            *pNum = 0;
+            return NULL;
+        }
+        s_AutoDetectDone = NV_TRUE;
+    }
+
+    *pNum = s_TotalPeripherals;
+    return (const NvOdmPeripheralConnectivity *)s_Peripherals;
+}
+
+// This implements a simple linear search across the entire set of currently-
+// connected peripherals to find the set of GUIDs that Match the search
+// criteria.  More clever implementations are possible, but given the
+// relatively small search space (max dozens of peripherals) and the relative
+// infrequency of enumerating peripherals, this is the easiest implementation.
+const NvOdmPeripheralConnectivity *
+NvOdmPeripheralGetGuid(NvU64 SearchGuid)
+{
+    const NvOdmPeripheralConnectivity *pAllPeripherals;
+    NvU32 NumPeripherals;
+    NvU32 i;
+
+    pAllPeripherals = NvApGetAllPeripherals(&NumPeripherals);
+
+    if (!pAllPeripherals || !NumPeripherals)
+        return NULL;
+
+    for (i=0; i<NumPeripherals; i++) 
+    {
+        if (SearchGuid == pAllPeripherals[i].Guid)
+        {
+            if (NvIsFilteredPeripheral(&pAllPeripherals[i]))
+                return NULL;
+            return &pAllPeripherals[i];
+        }
+    }
+
+    return NULL;
+}
+
+static NvBool
+IsBusMatch(
+    const NvOdmPeripheralConnectivity *pPeriph,
+    const NvOdmPeripheralSearch *pSearchAttrs,
+    const NvU32 *pSearchVals,
+    NvU32 offset,
+    NvU32 NumAttrs)
+{
+    NvU32 i, j;
+    NvBool IsMatch = NV_FALSE;
+
+    for (i=0; i<pPeriph->NumAddress; i++)
+    {
+        j = offset;
+        do
+        {
+            switch (pSearchAttrs[j])
+            {
+            case NvOdmPeripheralSearch_IoModule:
+                IsMatch = (pSearchVals[j] ==
+                           (NvU32)(pPeriph->AddressList[i].Interface));
+                break;
+            case NvOdmPeripheralSearch_Address:
+                IsMatch = (pSearchVals[j] == pPeriph->AddressList[i].Address);
+                break;
+            case NvOdmPeripheralSearch_Instance:
+                IsMatch = (pSearchVals[j] == pPeriph->AddressList[i].Instance);
+                break;
+            case NvOdmPeripheralSearch_PeripheralClass:
+            default:
+                NV_ASSERT(!"Bad Query!");
+                break;
+            }
+            j++;
+        } while (IsMatch && j<NumAttrs &&
+                 pSearchAttrs[j]!=NvOdmPeripheralSearch_IoModule);
+
+        if (IsMatch)
+        {
+            return NV_TRUE;
+        }
+    }
+    return NV_FALSE;
+}
+
+static NvBool
+IsPeripheralMatch(
+    const NvOdmPeripheralConnectivity *pPeriph,
+    const NvOdmPeripheralSearch *pSearchAttrs,
+    const NvU32 *pSearchVals,
+    NvU32 NumAttrs)
+{
+    NvU32 i;
+    NvBool IsMatch = NV_TRUE;
+
+    for (i=0; i<NumAttrs && IsMatch; i++)
+    {
+        switch (pSearchAttrs[i])
+        {
+        case NvOdmPeripheralSearch_PeripheralClass:
+            IsMatch = (pSearchVals[i] == (NvU32)(pPeriph->Class));
+            break;
+        case NvOdmPeripheralSearch_IoModule:
+            IsMatch = IsBusMatch(pPeriph, pSearchAttrs, pSearchVals, i, NumAttrs);
+            break;
+        case NvOdmPeripheralSearch_Address:
+        case NvOdmPeripheralSearch_Instance:
+            // In correctly-formed searches, these parameters will be parsed by
+            // IsBusMatch, so we ignore them here.
+            break;
+        default:
+            NV_ASSERT(!"Bad search attribute!");
+            break;
+        }
+    }
+    return IsMatch;
+}
+
+NvU32
+NvOdmPeripheralEnumerate(
+    const NvOdmPeripheralSearch *pSearchAttrs,
+    const NvU32 *pSearchVals,
+    NvU32 NumAttrs,
+    NvU64 *pGuidList,
+    NvU32 NumGuids)
+{
+    const NvOdmPeripheralConnectivity *pAllPeripherals;
+    NvU32 NumPeripherals;
+    NvU32 Matches;
+    NvU32 i;
+
+    pAllPeripherals = NvApGetAllPeripherals(&NumPeripherals);
+
+    if (!pAllPeripherals || !NumPeripherals)
+    {
+        return 0;
+    }
+
+    if (!pSearchAttrs || !pSearchVals)
+    {
+        NumAttrs = 0;
+    }
+    for (i=0, Matches=0; i<NumPeripherals &&
+             (Matches < NumGuids || !pGuidList); i++)
+    {
+        if ( !NumAttrs || IsPeripheralMatch(&pAllPeripherals[i],
+                                            pSearchAttrs, pSearchVals,
+                                            NumAttrs) )
+        {
+            if (NvIsFilteredPeripheral(&pAllPeripherals[i]))
+                continue;
+
+            if (pGuidList)
+                pGuidList[Matches] = pAllPeripherals[i].Guid;
+            Matches++;
+        }
+    }
+    return Matches;
+}
+
diff --git a/arch/arm/mach-tegra/odm_kit/query/harmony/nvodm_query_gpio.c b/arch/arm/mach-tegra/odm_kit/query/harmony/nvodm_query_gpio.c
new file mode 100644
index 000000000000..8d384db176ee
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/query/harmony/nvodm_query_gpio.c
@@ -0,0 +1,240 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include "nvodm_query_gpio.h"
+#include "nvodm_services.h"
+#include "nvrm_drf.h"
+
+#define NVODM_ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+#define NVODM_PORT(x) ((x) - 'a')
+
+static const NvOdmGpioPinInfo s_vi[] = {
+    {NVODM_PORT('t'), 3, NvOdmGpioPinActiveState_High}, // EN_VDDIO_SD
+};
+
+static const NvOdmGpioPinInfo s_display[] = {
+
+    // TO DO: Verify these settings for harmony.
+
+    /* Panel 0 -- sony vga */
+    { NVODM_PORT('m'), 3, NvOdmGpioPinActiveState_Low },
+    { NVODM_PORT('b'), 2, NvOdmGpioPinActiveState_Low },
+    { NVODM_PORT('n'), 4, NvOdmGpioPinActiveState_Low },
+    { NVODM_PORT('j'), 3, NvOdmGpioPinActiveState_Low },
+    { NVODM_PORT('j'), 4, NvOdmGpioPinActiveState_Low },
+    // this pin is not needed for ap15
+    {NVODM_GPIO_INVALID_PORT, NVODM_GPIO_INVALID_PIN,
+        NvOdmGpioPinActiveState_Low},
+
+    /* Panel 1 -- samtek */
+    {NVODM_GPIO_INVALID_PORT, NVODM_GPIO_INVALID_PIN,
+        NvOdmGpioPinActiveState_Low},
+    {NVODM_GPIO_INVALID_PORT, NVODM_GPIO_INVALID_PIN,
+        NvOdmGpioPinActiveState_Low},
+    {NVODM_GPIO_INVALID_PORT, NVODM_GPIO_INVALID_PIN,
+        NvOdmGpioPinActiveState_Low},
+    {NVODM_GPIO_INVALID_PORT, NVODM_GPIO_INVALID_PIN,
+        NvOdmGpioPinActiveState_Low},
+
+    /* Panel 2 -- sharp wvga */
+    { NVODM_PORT('v'), 7, NvOdmGpioPinActiveState_Low },
+
+    /* Panel 3 -- sharp qvga */
+    { NVODM_PORT('n'), 6, NvOdmGpioPinActiveState_High },   // LCD_DC0
+    { NVODM_PORT('n'), 4, NvOdmGpioPinActiveState_Low },    // LCD_CS0
+    { NVODM_PORT('b'), 3, NvOdmGpioPinActiveState_Low },    // LCD_PCLK
+    { NVODM_PORT('b'), 2, NvOdmGpioPinActiveState_Low },    // LCD_PWR0
+    { NVODM_PORT('e'), 0, NvOdmGpioPinActiveState_High },   // LCD_D0
+    { NVODM_PORT('e'), 1, NvOdmGpioPinActiveState_High },   // LCD_D1
+    { NVODM_PORT('e'), 2, NvOdmGpioPinActiveState_High },   // LCD_D2
+    { NVODM_PORT('e'), 3, NvOdmGpioPinActiveState_High },   // LCD_D3
+    { NVODM_PORT('e'), 4, NvOdmGpioPinActiveState_High },   // LCD_D4
+    { NVODM_PORT('e'), 5, NvOdmGpioPinActiveState_High },   // LCD_D5
+    { NVODM_PORT('e'), 6, NvOdmGpioPinActiveState_High },   // LCD_D6
+    { NVODM_PORT('e'), 7, NvOdmGpioPinActiveState_High },   // LCD_D7
+    { NVODM_PORT('f'), 0, NvOdmGpioPinActiveState_High },   // LCD_D8
+    { NVODM_PORT('f'), 1, NvOdmGpioPinActiveState_High },   // LCD_D9
+    { NVODM_PORT('f'), 2, NvOdmGpioPinActiveState_High },   // LCD_D10
+    { NVODM_PORT('f'), 3, NvOdmGpioPinActiveState_High },   // LCD_D11
+    { NVODM_PORT('f'), 4, NvOdmGpioPinActiveState_High },   // LCD_D12
+    { NVODM_PORT('f'), 5, NvOdmGpioPinActiveState_High },   // LCD_D13
+    { NVODM_PORT('f'), 6, NvOdmGpioPinActiveState_High },   // LCD_D14
+    { NVODM_PORT('f'), 7, NvOdmGpioPinActiveState_High },   // LCD_D15
+    { NVODM_PORT('m'), 3, NvOdmGpioPinActiveState_High },   // LCD_D19
+
+    /* Panel 4 -- auo */
+    { NVODM_PORT('v'), 7, NvOdmGpioPinActiveState_Low },
+
+    /* Panel 5 -- firefly p1138 lvds interface */
+    {NVODM_GPIO_INVALID_PORT, NVODM_GPIO_INVALID_PIN, NvOdmGpioPinActiveState_Low},
+    { NVODM_PORT('b'), 4, NvOdmGpioPinActiveState_High },   // LCD_BL_PWM
+    { NVODM_PORT('b'), 5, NvOdmGpioPinActiveState_High },   // LCD_BL_EN
+    { NVODM_PORT('c'), 6, NvOdmGpioPinActiveState_High },   // EN_VDD_PNL
+};
+
+static const NvOdmGpioPinInfo s_hdmi[] =
+{
+    /* hdmi hot-plug interrupt pin */
+    { NVODM_PORT('n'), 7, NvOdmGpioPinActiveState_High },    // HDMI HPD
+};
+
+static const NvOdmGpioPinInfo s_crt[] =
+{
+    /* crt hot-plug interrupt pin */
+    { NVODM_PORT('x'), 2, NvOdmGpioPinActiveState_Low }, // VGA_DET#
+};
+
+static const NvOdmGpioPinInfo s_sdio[] = {
+    {NVODM_PORT('i'), 5, NvOdmGpioPinActiveState_Low},    // Card Detect for SDIO instance 2
+    /* High for WP and low for read/write */
+    {NVODM_PORT('h'), 1, NvOdmGpioPinActiveState_High},    // Write Protect for SDIO instance 2 
+};
+
+static const NvOdmGpioPinInfo s_sdio3[] = {
+    {NVODM_PORT('h'), 2, NvOdmGpioPinActiveState_Low},    // Card Detect for SDIO instance 3
+    /* High for WP and low for read/write */
+    {NVODM_PORT('h'), 3, NvOdmGpioPinActiveState_High},    // Write Protect for SDIO instance 3
+};
+
+static const NvOdmGpioPinInfo s_NandFlash[] = {
+    {NVODM_PORT('c'), 7, NvOdmGpioPinActiveState_High}, // Raw NAND WP_N
+};
+
+static const NvOdmGpioPinInfo s_spi_ethernet[] = {
+    {NVODM_PORT('c'), 1, NvOdmGpioPinActiveState_Low}   // DBG_IRQ
+};
+
+static const NvOdmGpioPinInfo s_Bluetooth[] = {
+    {NVODM_PORT('u'), 0, NvOdmGpioPinActiveState_Low}   // BT_RST#
+};
+
+static const NvOdmGpioPinInfo s_Wlan[] = {
+    {NVODM_PORT('k'), 5, NvOdmGpioPinActiveState_Low},  // WF_PWDN#
+    {NVODM_PORT('k'), 6, NvOdmGpioPinActiveState_Low}   // WF_RST#
+};
+
+static const NvOdmGpioPinInfo s_Power[] = {
+    // lid open/close, High = Lid Closed
+    {NVODM_PORT('u'), 5, NvOdmGpioPinActiveState_High},
+    // power button
+    {NVODM_PORT('v'), 2, NvOdmGpioPinActiveState_Low}
+};
+
+static const NvOdmGpioPinInfo s_WakeFromKeyBoard[] = {
+    {NVODM_PORT('a'), 0, NvOdmGpioPinActiveState_Low}   // EC Keyboard Wakeup
+};
+
+static const NvOdmGpioPinInfo s_Battery[] = {
+    // Low Battery
+    {NVODM_PORT('w'), 3, NvOdmGpioPinActiveState_Low},
+};
+
+const NvOdmGpioPinInfo *NvOdmQueryGpioPinMap(NvOdmGpioPinGroup Group,
+    NvU32 Instance, NvU32 *pCount)
+{
+    switch (Group)
+    {
+        case NvOdmGpioPinGroup_Display:
+            *pCount = NVODM_ARRAY_SIZE(s_display);
+            return s_display;
+
+        case NvOdmGpioPinGroup_Hdmi:
+            *pCount = NVODM_ARRAY_SIZE(s_hdmi);
+            return s_hdmi;
+
+        case NvOdmGpioPinGroup_Crt:
+            *pCount = NVODM_ARRAY_SIZE(s_crt);
+            return s_crt;
+
+        case NvOdmGpioPinGroup_Sdio:
+            if (Instance == 1)
+            {
+                *pCount = NVODM_ARRAY_SIZE(s_sdio);
+                return s_sdio;
+            }
+            else if (Instance == 3)
+            {
+                *pCount = NVODM_ARRAY_SIZE(s_sdio3);
+                return s_sdio3;
+            }
+            else
+            {
+                *pCount = 0;
+                return NULL;
+            }
+
+        case NvOdmGpioPinGroup_NandFlash:
+            *pCount = NVODM_ARRAY_SIZE(s_NandFlash);
+            return s_NandFlash;
+
+        case NvOdmGpioPinGroup_Bluetooth:
+            *pCount = NVODM_ARRAY_SIZE(s_Bluetooth);
+            return s_Bluetooth;
+
+        case NvOdmGpioPinGroup_Wlan:
+            *pCount = NVODM_ARRAY_SIZE(s_Wlan);
+            return s_Wlan;
+
+        case NvOdmGpioPinGroup_SpiEthernet:
+            if (NvOdmQueryDownloadTransport() ==
+                NvOdmDownloadTransport_SpiEthernet)
+            {
+                *pCount = NVODM_ARRAY_SIZE(s_spi_ethernet);
+                return s_spi_ethernet;
+            }
+            else
+            {
+                *pCount = 0;
+                return NULL;
+            }
+        
+        case NvOdmGpioPinGroup_Vi:
+            *pCount = NVODM_ARRAY_SIZE(s_vi);
+            return s_vi;
+
+        case NvOdmGpioPinGroup_Power:
+            *pCount = NVODM_ARRAY_SIZE(s_Power);
+            return s_Power;
+
+        case NvOdmGpioPinGroup_WakeFromECKeyboard:
+            *pCount = NVODM_ARRAY_SIZE(s_WakeFromKeyBoard);
+            return s_WakeFromKeyBoard;
+
+        case NvOdmGpioPinGroup_Battery:
+            *pCount = NVODM_ARRAY_SIZE(s_Battery);
+            return s_Battery;
+
+        default:
+            *pCount = 0;
+            return NULL;
+    }
+}
diff --git a/arch/arm/mach-tegra/odm_kit/query/harmony/nvodm_query_kbc.c b/arch/arm/mach-tegra/odm_kit/query/harmony/nvodm_query_kbc.c
new file mode 100644
index 000000000000..951fc9730f41
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/query/harmony/nvodm_query_kbc.c
@@ -0,0 +1,100 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/**
+ * @file
+ * @brief <b>NVIDIA Driver Development Kit:
+ *                  ODM Kbc interface</b>
+ *
+ */
+
+#include "nvodm_query_kbc.h"
+#include "nvodm_query_kbc_gpio_def.h"
+#include "nvodm_query_kbc_qwerty_def.h"
+
+static NvU32 RowNumbers[] = {1, 15};
+static NvU32 ColNumbers[] = {7, 0};
+
+void
+NvOdmKbcGetParameter(
+        NvOdmKbcParameter Param,
+        NvU32 SizeOfValue,
+        void * pValue)
+{
+    NvU32 *pTempVar;
+    switch (Param)
+    {
+        case NvOdmKbcParameter_DebounceTime:
+            pTempVar = (NvU32 *)pValue;
+            *pTempVar = 2;
+            break;
+        case NvOdmKbcParameter_RepeatCycleTime:
+            pTempVar = (NvU32 *)pValue;
+            *pTempVar = 5;
+            break;
+        default:
+            break;
+    }
+}
+
+NvU32 
+NvOdmKbcGetKeyCode(
+    NvU32 Row, 
+    NvU32 Column,
+    NvU32 RowCount,
+    NvU32 ColumnCount)
+{
+    NvU32 CodeData;
+    if (Row < KBC_QWERTY_FUNCTION_KEY_ROW_BASE)
+    {
+        CodeData = KBC_QWERTY_NORMAL_KEY_CODE_BASE + ((Row * ColumnCount) + Column);
+    }    
+    else
+    {
+        CodeData = KBC_QWERTY_FUNCTION_KEY_CODE_BASE + 
+                        (((Row - KBC_QWERTY_FUNCTION_KEY_ROW_BASE) * ColumnCount) + Column);
+    }
+    return CodeData;
+}
+
+NvBool
+NvOdmKbcIsSelectKeysWkUpEnabled(
+    NvU32 **pRowNumber,
+    NvU32 **pColNumber,
+    NvU32 *NumOfKeys)
+{
+    *pRowNumber = &RowNumbers[0];
+    *pColNumber = &ColNumbers[0];
+    *NumOfKeys = 2;
+    return NV_TRUE;
+}
+
diff --git a/arch/arm/mach-tegra/odm_kit/query/harmony/nvodm_query_kbc_gpio_def.h b/arch/arm/mach-tegra/odm_kit/query/harmony/nvodm_query_kbc_gpio_def.h
new file mode 100644
index 000000000000..2e625eb6217d
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/query/harmony/nvodm_query_kbc_gpio_def.h
@@ -0,0 +1,75 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/**
+ * @file
+ * <b>NVIDIA APX ODM Kit::
+ *         The KBC GPIO pin definitions</b>
+ *
+ * @b Description: Define the KBC GPIO pins in row and column numbers.
+ */
+
+#ifndef NVODM_QUERY_KBC_GPIO_DEF_H
+#define NVODM_QUERY_KBC_GPIO_DEF_H
+
+typedef enum
+{
+    NvOdmKbcGpioPin_KBRow0 = 0,
+    NvOdmKbcGpioPin_KBRow1,
+    NvOdmKbcGpioPin_KBRow2,
+    NvOdmKbcGpioPin_KBRow3,
+    NvOdmKbcGpioPin_KBRow4,
+    NvOdmKbcGpioPin_KBRow5,
+    NvOdmKbcGpioPin_KBRow6,
+    NvOdmKbcGpioPin_KBRow7,
+    NvOdmKbcGpioPin_KBRow8,
+    NvOdmKbcGpioPin_KBRow9,
+    NvOdmKbcGpioPin_KBRow10,
+    NvOdmKbcGpioPin_KBRow11,
+    NvOdmKbcGpioPin_KBRow12,
+    NvOdmKbcGpioPin_KBRow13,
+    NvOdmKbcGpioPin_KBRow14,
+    NvOdmKbcGpioPin_KBRow15,
+    NvOdmKbcGpioPin_KBCol0,
+    NvOdmKbcGpioPin_KBCol1,
+    NvOdmKbcGpioPin_KBCol2,
+    NvOdmKbcGpioPin_KBCol3,
+    NvOdmKbcGpioPin_KBCol4,
+    NvOdmKbcGpioPin_KBCol5,
+    NvOdmKbcGpioPin_KBCol6,
+    NvOdmKbcGpioPin_KBCol7,
+    NvOdmKbcGpioPin_Num,
+    NvOdmKbcGpioPin_Force32 = 0x7FFFFFFF
+}NvOdmKbcGpioPin;
+
+#endif // NVODM_QUERY_KBC_GPIO_DEF_H
+
diff --git a/arch/arm/mach-tegra/odm_kit/query/harmony/nvodm_query_kbc_qwerty_def.h b/arch/arm/mach-tegra/odm_kit/query/harmony/nvodm_query_kbc_qwerty_def.h
new file mode 100644
index 000000000000..c5c82bb5df35
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/query/harmony/nvodm_query_kbc_qwerty_def.h
@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/**
+ * @file
+ * <b>NVIDIA APX ODM Kit::
+ *         The KBC qwerty property definitions</b>
+ *
+ * @b Description: Define the qwerty keyboard support definitions which is used
+ * by multiple functions.
+ */
+
+#ifndef NVODM_QUERY_KBC_QWERTY_DEF_H
+#define NVODM_QUERY_KBC_QWERTY_DEF_H
+
+#define KBC_QWERTY_NORMAL_KEY_CODE_BASE 0x1000
+#define KBC_QWERTY_FUNCTION_KEY_CODE_BASE 0x2000
+
+#define KBC_QWERTY_FUNCTION_KEY_ROW_BASE 0x100
+#define KBC_QWERTY_FUNCTION_KEY_ROW_NUMBER 0
+#define KBC_QWERTY_FUNCTION_KEY_COLUMN_NUMBER 7
+
+
+#endif // NVODM_QUERY_KBC_QWERTY_DEF_H
+
diff --git a/arch/arm/mach-tegra/odm_kit/query/harmony/nvodm_query_nand.c b/arch/arm/mach-tegra/odm_kit/query/harmony/nvodm_query_nand.c
new file mode 100644
index 000000000000..18a2c903cbb4
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/query/harmony/nvodm_query_nand.c
@@ -0,0 +1,255 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/**
+ * @file
+ * @brief <b>NVIDIA Driver Development Kit:
+ *                  ODM Uart interface</b>
+ *
+ * @b Description: Implements the ODM for the Uart communication.
+ *
+ */
+
+#include "nvodm_query_nand.h"
+#include "nvcommon.h"
+
+// fill params for all required nand flashes here.
+// this list will end when vendor id and chipd id will be zero.
+// hence, all supported chips should be listed before that.
+NvOdmNandFlashParams g_Params[] =
+{
+    /*
+    {
+        VendorId, DeviceId, NandType, IsCopyBackCommandSupported, IsCacheWriteSupported, CapacityInMB, ZonesPerDevice,
+        BlocksPerZone, OperationSuccessStatus, InterleaveCapability, EccAlgorithm,
+        ErrorsCorrectable, SkippedSpareBytes,
+        TRP, TRH (TREH), TWP, TWH, TCS, TWHR, TWB, TREA, TADL,
+        TCLS, TCLH, TCH, TALS, TALH, TRC, TWC, TCR(TCLR), TAR, TRR, NandDeviceType, ReadIdFourthByte
+    }
+    Note :
+    TADL values for flashes K9F1G08Q0M, K9F1G08U0M, TH58NVG4D4CTG00,
+    TH58NVG3D4BTG00, TH58NVG2S3BFT00 is not available from their data sheets.
+    Hence TADL is computed as
+        tADL = (tALH + tALS + tWP).
+    */
+    // filling odm parameter structure for Samsung K9K8G08U0M
+    {
+        0xEC, 0xD3, NvOdmNandFlashType_Slc, NV_TRUE, NV_FALSE, 1024, 4,
+        2048, 0x40, SINGLE_PLANE, NvOdmNandECCAlgorithm_ReedSolomon,
+        NvOdmNandNumberOfCorrectableSymbolErrors_Four, NvOdmNandSkipSpareBytes_4,
+        15, 10, 15, 10, 20, 60, 100, 26, 70,
+        12, 5, 5, 12, 5, 25, 25, 10, 10, 20, NvOdmNandDeviceType_Type1, 0x95
+     },
+    // filling odm parameter structure for Samsung K9GAG08U0D
+    {
+        0xEC, 0xD5, NvOdmNandFlashType_Mlc, NV_TRUE, NV_FALSE, 2048, 2,
+        2048, 0x60, SINGLE_PLANE, NvOdmNandECCAlgorithm_ReedSolomon,
+        NvOdmNandNumberOfCorrectableSymbolErrors_Eight, NvOdmNandSkipSpareBytes_4,
+        15, 10, 15, 10, 20, 60, 100, 20, 100,
+        15, 5, 5, 15, 5, 30, 30, 10, 10, 20, NvOdmNandDeviceType_Type2, 0x29
+    },
+    // filling odm parameter structure for Samsung K9W8G08U1M
+    {
+        0xEC, 0xDC, NvOdmNandFlashType_Slc, NV_TRUE, NV_TRUE, 1024, 2,
+        4096, 0x60, SINGLE_PLANE, NvOdmNandECCAlgorithm_ReedSolomon,
+        NvOdmNandNumberOfCorrectableSymbolErrors_Four, NvOdmNandSkipSpareBytes_4,
+        15, 10, 15, 10, 15, 60, 100, 18, 100,
+        10, 5, 5, 10, 5, 30, 30, 10, 10, 20, NvOdmNandDeviceType_Type1, 0x15
+    },
+    // filling odm parameter structure for Samsung K9F1G08Q0M
+    {
+        0xEC, 0xA1, NvOdmNandFlashType_Slc, NV_TRUE, NV_TRUE, 128, 1,
+        1024, 0x60, SINGLE_PLANE, NvOdmNandECCAlgorithm_ReedSolomon,
+        NvOdmNandNumberOfCorrectableSymbolErrors_Four, NvOdmNandSkipSpareBytes_4,
+        60, 20, 60, 20, 0, 60, 100, 60, 70,
+        0, 10, 10, 0, 10, 80, 80, 10, 10, 20, NvOdmNandDeviceType_Type1, 0x15
+    },
+    // filling odm parameter structure for Samsung K9F1G08U0M
+    {
+        0xEC, 0xF1, NvOdmNandFlashType_Slc, NV_TRUE, NV_TRUE, 128, 1,
+        1024, 0x40, SINGLE_PLANE, NvOdmNandECCAlgorithm_ReedSolomon,
+        NvOdmNandNumberOfCorrectableSymbolErrors_Four, NvOdmNandSkipSpareBytes_4,
+        25, 15, 25, 15, 0, 60, 100, 30, 35,
+        0, 10, 10, 0, 10, 50, 45, 10, 10, 20, NvOdmNandDeviceType_Type1, 0x15
+     },
+    // filling odm parameter structure for Samsung K9L8G08U0M
+    {
+        0xEC, 0xD3, NvOdmNandFlashType_Mlc, NV_FALSE, NV_FALSE, 1024, 4,
+        1024, 0x40, SINGLE_PLANE, NvOdmNandECCAlgorithm_ReedSolomon,
+        NvOdmNandNumberOfCorrectableSymbolErrors_Four, NvOdmNandSkipSpareBytes_4,
+        15, 10, 15, 10, 20, 60, 100, 20, 35,
+        15, 5, 5, 15, 5, 30, 30, 10, 10, 20, NvOdmNandDeviceType_Type1, 0x25
+     },
+    // filling odm parameter structure for Samsung K9G4G08U0M
+    {
+        0xEC, 0xDC, NvOdmNandFlashType_Mlc, NV_FALSE, NV_FALSE, 512, 2,
+        1024, 0x40, SINGLE_PLANE, NvOdmNandECCAlgorithm_ReedSolomon,
+        NvOdmNandNumberOfCorrectableSymbolErrors_Four, NvOdmNandSkipSpareBytes_4,
+        15, 10, 15, 15, 15, 60, 100, 18, 50,
+        10, 5, 5, 10, 5, 30, 45, 10, 10, 20, NvOdmNandDeviceType_Type1, 0x25
+     },
+    // filling odm parameter structure for Samsung K5E2G1GACM
+    {
+        0xEC, 0xAA, NvOdmNandFlashType_Slc, NV_TRUE, NV_FALSE, 256, 2,
+        1024, 0x40, SINGLE_PLANE, NvOdmNandECCAlgorithm_ReedSolomon,
+        NvOdmNandNumberOfCorrectableSymbolErrors_Four, NvOdmNandSkipSpareBytes_4,
+        21, 15, 21, 15, 31, 60, 100, 30, 100,
+        21, 5, 5, 21, 5, 42, 42, 10, 10, 20, NvOdmNandDeviceType_Type1, 0x15
+     },
+/*
+    // filling odm parameter structure for Toshiba TH58NVG4D4CTG00
+    {
+        0x98, 0xD5, NvOdmNandFlashType_Mlc, NV_FALSE, NV_FALSE, 2048, 1,
+        8192, 0x40, SINGLE_PLANE, NvOdmNandECCAlgorithm_ReedSolomon,
+        NvOdmNandNumberOfCorrectableSymbolErrors_Four, NvOdmNandSkipSpareBytes_4,
+        41, 15, 15, 10, 0, 30, 20, 200, 41, 21,
+        0, 6, 6, 0, 6, NvOdmNandDeviceType_Type1, 0x25
+    },
+    // filling odm parameter structure for Toshiba TH58NVG3D4BTG00
+    {
+        0x98, 0xD3, NvOdmNandFlashType_Mlc, NV_FALSE, NV_TRUE, 1024, 1,
+        4096, 0x60, SINGLE_PLANE, NvOdmNandECCAlgorithm_ReedSolomon,
+        NvOdmNandNumberOfCorrectableSymbolErrors_Four, NvOdmNandSkipSpareBytes_4,
+        41, 15, 15, 10, 0, 30, 20, 200, 41, 35,
+        0, 10, 10, 0, 10, NvOdmNandDeviceType_Type1, 0x25
+     },
+    // filling odm parameter structure for Toshiba TH58NVG2S3BFT00
+    {
+        0x98, 0xDC, NvOdmNandFlashType_Slc, NV_FALSE, NV_FALSE, 512, 1,
+        1024, 0x60, SINGLE_PLANE, NvOdmNandECCAlgorithm_ReedSolomon,
+        NvOdmNandNumberOfCorrectableSymbolErrors_Four, NvOdmNandSkipSpareBytes_4,
+        41, 15, 15, 10, 0, 30, 20, 200, 41, 35,
+        0, 10, 10, 0, 10, NvOdmNandDeviceType_Type1, 0x25
+     },
+*/
+    // filling odm parameter structure for Samsung K9LBG08U0M
+    {
+        0xEC, 0xD7, NvOdmNandFlashType_Mlc, NV_TRUE, NV_FALSE, 4096, 4, 2048,
+        0x40, SINGLE_PLANE, NvOdmNandECCAlgorithm_ReedSolomon,
+        NvOdmNandNumberOfCorrectableSymbolErrors_Six, NvOdmNandSkipSpareBytes_4,
+        12, 10, 12, 10, 20, 60, 100, 20, 100,
+        12, 5, 5, 12, 5, 25, 25, 10, 10, 20, NvOdmNandDeviceType_Type1, 0xB6
+    },
+    //Hynix H8BES0UQ0MCP 
+     {
+        0xAD, 0xBC,  NvOdmNandFlashType_Slc, NV_TRUE, NV_FALSE, 512, 2, 2048, 
+        0x40, SINGLE_PLANE, NvOdmNandECCAlgorithm_ReedSolomon,  
+        NvOdmNandNumberOfCorrectableSymbolErrors_Four, NvOdmNandSkipSpareBytes_4, 
+        25, 10, 25, 15, 35, 60, 100, 30, 100,
+        25, 10, 10, 25, 10, 45, 45, 10, 10, 20, NvOdmNandDeviceType_Type1, 0x55
+     },
+     //Hynix H8BCS0SJ0MCP 
+    {
+        0xAD, 0xBA, NvOdmNandFlashType_Slc, NV_TRUE, NV_FALSE, 256, 1, 2048, 
+        0x60, SINGLE_PLANE, NvOdmNandECCAlgorithm_ReedSolomon,  
+        NvOdmNandNumberOfCorrectableSymbolErrors_Four, NvOdmNandSkipSpareBytes_4, 
+        25, 15, 25, 15, 35, 60, 100, 30, 100,
+        25, 10, 10, 25, 10, 45, 45, 10, 10, 25, NvOdmNandDeviceType_Type1, 0x55
+     },
+
+     //Hynix H8BCS0RJ0MCP 
+    {
+        0xAD, 0xAA, NvOdmNandFlashType_Slc, NV_TRUE, NV_FALSE, 256, 1, 2048, 
+        0x60, SINGLE_PLANE, NvOdmNandECCAlgorithm_ReedSolomon, 
+        NvOdmNandNumberOfCorrectableSymbolErrors_Four, NvOdmNandSkipSpareBytes_4, 
+        25, 10, 25, 15, 35, 60, 100, 30, 100,
+        25, 10, 10, 25, 10, 45, 45, 10, 10, 25, NvOdmNandDeviceType_Type1, 0x15
+     },
+     /*Numonyx MCP - NAND02GR3B2D*/ 
+    {
+        0x20, 0xAA, NvOdmNandFlashType_Slc, NV_TRUE, NV_FALSE, 256, 1, 
+        2048, 0x40, SINGLE_PLANE, NvOdmNandECCAlgorithm_ReedSolomon, 
+        NvOdmNandNumberOfCorrectableSymbolErrors_Four, NvOdmNandSkipSpareBytes_4,
+        25, 15, 25, 15, 35, 60, 100, 30, 100,
+        25, 10, 10, 25, 10, 45, 45, 10, 10, 25, NvOdmNandDeviceType_Type1, 0x15
+     },
+     // Hynix HY27UF084G2B (readid 4th byte 0x95)
+     {
+        0xAD, 0xDC, NvOdmNandFlashType_Slc, NV_TRUE, NV_FALSE, 512, 2,
+        2048, 0x60, SINGLE_PLANE, NvOdmNandECCAlgorithm_ReedSolomon, 
+        NvOdmNandNumberOfCorrectableSymbolErrors_Four, NvOdmNandSkipSpareBytes_4, 
+        12, 10, 12, 10, 20, 80, 100, 20, 70,
+        12, 5, 5, 12, 5, 25, 25, 10, 10, 20, NvOdmNandDeviceType_Type1, 0x95
+     },
+    /* "This is the end of device list please do not modify this. To add support for more flash parts,
+        add device category for those parts before this element"*/
+    {
+        0, 0, NvOdmNandFlashType_UnKnown, NV_FALSE, NV_FALSE, 0, 0,
+        0, 0, SINGLE_PLANE, NvOdmNandECCAlgorithm_ReedSolomon,
+        NvOdmNandNumberOfCorrectableSymbolErrors_Four, NvOdmNandSkipSpareBytes_4,
+        0, 0, 0, 0, 0, 0, 0, 0, 0,
+        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, NvOdmNandDeviceType_Type1, 0
+    }
+};
+
+NvOdmNandFlashParams *NvOdmNandGetFlashInfo (NvU32 ReadID)
+{
+    NvU8 TempValue;
+    NvU8 VendorId = 0;
+    NvU8 DeviceId = 0;
+    NvU8 ReadIdFourthByte = 0;
+    NvOdmNandFlashType NandType;
+    NvU8 i = 0;
+    // To extract Vendor Id
+    VendorId = (NvU8) (ReadID & 0xFF);
+    // To extract Device Id
+    DeviceId = (NvU8) ((ReadID >> DEVICE_SHIFT) & 0xFF);
+    // To extract Fourth ID byte of Read ID - for checking if the flash is 42nm.
+    ReadIdFourthByte = (NvU8) ((ReadID >> FOURTH_ID_SHIFT) & 0xFF);
+    // To extract device Type Mask
+    TempValue = (NvU8) ((ReadID >> FLASH_TYPE_SHIFT) & 0xC);
+    if (TempValue)
+    {
+        NandType = NvOdmNandFlashType_Mlc;
+    }
+    else
+    {
+        NandType = NvOdmNandFlashType_Slc;
+    }
+    // following ORing is done to check if we reached the end of the list.
+    while ((g_Params[i].VendorId) | (g_Params[i].DeviceId))
+    {
+        if ((g_Params[i].VendorId == VendorId) &&
+            (g_Params[i].DeviceId == DeviceId) &&
+            (g_Params[i].ReadIdFourthByte == ReadIdFourthByte) &&
+            (g_Params[i].NandType == NandType))
+        {
+            return &g_Params[i];
+        }
+        else
+            i++;
+    }
+    // This condition will be reached if "g_Params" is not having Parameters of the flash used.
+    // Hence add the parameters required in the table.
+    return NULL;
+}
+
diff --git a/arch/arm/mach-tegra/odm_kit/query/harmony/nvodm_query_pinmux.c b/arch/arm/mach-tegra/odm_kit/query/harmony/nvodm_query_pinmux.c
new file mode 100644
index 000000000000..e8ec4b70b3dc
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/query/harmony/nvodm_query_pinmux.c
@@ -0,0 +1,305 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/*
+ * This file implements the pin-mux configuration tables for each I/O module.
+ */
+
+// THESE SETTINGS ARE PLATFORM-SPECIFIC (not SOC-specific).
+// PLATFORM = Harmony
+
+#include "nvodm_query_pinmux.h"
+#include "nvassert.h"
+#include "nvodm_query.h"
+#include "nvodm_services.h"
+
+#define NVODM_PINMUX_ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+static const NvU32 s_NvOdmPinMuxConfig_Uart[] = {
+    NvOdmUartPinMap_Config4,    // UART1, 2 lines
+    NvOdmUartPinMap_Config2,    // UART2, 2 lines
+    NvOdmUartPinMap_Config1,    // UART3, 4 lines
+    NvOdmUartPinMap_Config2,    // UART4, 4 lines
+    0                           // UART5
+};
+
+static const NvU32 s_NvOdmPinMuxConfig_Spi[] = {
+    NvOdmSpiPinMap_Config4,
+    0,
+    0,
+    0,
+    0
+};
+
+static const NvU32 s_NvOdmPinMuxConfig_Twc[] = {
+    0
+};
+
+static const NvU32 s_NvOdmPinMuxConfig_I2c[] = {
+    NvOdmI2cPinMap_Config1,
+    NvOdmI2cPinMap_Config1,
+    NvOdmI2cPinMap_Config1
+};
+
+static const NvU32 s_NvOdmPinMuxConfig_I2cPmu[] = {
+    NvOdmI2cPmuPinMap_Config1
+};
+
+static const NvU32 s_NvOdmPinMuxConfig_Ulpi[] = {
+    NvOdmUlpiPinMap_Config1
+};
+
+static const NvU32 s_NvOdmPinMuxConfig_Sdio[] = {
+    NvOdmSdioPinMap_Config1, 
+    NvOdmSdioPinMap_Config5,
+    0,
+    NvOdmSdioPinMap_Config2
+};
+
+static const NvU32 s_NvOdmPinMuxConfig_Spdif[] = {
+    NvOdmSpdifPinMap_Config2
+};
+
+static const NvU32 s_NvOdmPinMuxConfig_Hsi[] = {
+    0
+};
+
+static const NvU32 s_NvOdmPinMuxConfig_Hdcp[] = {
+    NvOdmHdcpPinMap_Config1
+};
+
+static const NvU32 s_NvOdmPinMuxConfig_Hdmi[] = {
+    NvOdmHdmiPinMap_Config1
+};
+
+static const NvU32 s_NvOdmPinMuxConfig_Pwm[] = {
+    NvOdmPwmPinMap_Config6
+};
+
+static const NvU32 s_NvOdmPinMuxConfig_Ata[] = {
+    0
+};
+
+static const NvU32 s_NvOdmPinMuxConfig_Nand[] = {
+    NvOdmNandPinMap_Config4, 
+};
+
+static const NvU32 s_NvOdmPinMuxConfig_Dap[] = {
+    NvOdmDapPinMap_Config1,
+    NvOdmDapPinMap_Config1, 
+    0, 
+    NvOdmDapPinMap_Config1,
+    0
+};
+
+static const NvU32 s_NvOdmPinMuxConfig_Kbd[] = {
+    NvOdmKbdPinMap_Config1
+};
+
+static const NvU32 s_NvOdmPinMuxConfig_SyncNor[] = {
+    0
+};
+
+static const NvU32 s_NvOdmPinMuxConfig_Mio[] = {
+    0
+};
+
+static const NvU32 s_NvOdmPinMuxConfig_ExternalClock[] = {
+    NvOdmExternalClockPinMap_Config2,  
+    NvOdmExternalClockPinMap_Config3,
+    NvOdmExternalClockPinMap_Config1
+};
+
+static const NvU32 s_NvOdmPinMuxConfig_VideoInput[] = {
+    0
+};
+
+static const NvU32 s_NvOdmPinMuxConfig_Display[] = {
+    NvOdmDisplayPinMap_Config1,
+    0  // Only 1 display is connected to the LCD pins
+};
+
+static const NvU32 s_NvOdmPinMuxConfig_BacklightPwm[] = {
+    0,
+    0
+};
+
+static const NvU32 s_NvOdmPinMuxConfig_Crt[] = {
+    NvOdmCrtPinMap_Config1,
+};
+
+static const NvU32 s_NvOdmPinMuxConfig_Tvo[] = {
+    NvOdmTvoPinMap_Config1,
+};
+
+static const NvU32 s_NvOdmPinMuxConfig_OneWire[] = {
+    0
+};
+
+static const NvU32 s_NvOdmPinMuxConfig_PciExpress[] = {
+    NvOdmPciExpressPinMap_Config1,
+};
+
+void
+NvOdmQueryPinMux(
+    NvOdmIoModule IoModule,
+    const NvU32 **pPinMuxConfigTable,
+    NvU32 *pCount)
+{
+    switch (IoModule)
+    {
+    case NvOdmIoModule_Display:
+        *pPinMuxConfigTable = s_NvOdmPinMuxConfig_Display;
+        *pCount = NVODM_PINMUX_ARRAY_SIZE(s_NvOdmPinMuxConfig_Display);
+        break;
+
+    case NvOdmIoModule_Dap:
+        *pPinMuxConfigTable = s_NvOdmPinMuxConfig_Dap;
+        *pCount = NVODM_PINMUX_ARRAY_SIZE(s_NvOdmPinMuxConfig_Dap);
+        break;
+
+    case NvOdmIoModule_Hdcp:
+        *pPinMuxConfigTable = s_NvOdmPinMuxConfig_Hdcp;
+        *pCount = NVODM_PINMUX_ARRAY_SIZE(s_NvOdmPinMuxConfig_Hdcp);
+        break;
+
+    case NvOdmIoModule_Hdmi:
+        *pPinMuxConfigTable = s_NvOdmPinMuxConfig_Hdmi;
+        *pCount = NVODM_PINMUX_ARRAY_SIZE(s_NvOdmPinMuxConfig_Hdmi);
+        break;
+
+    case NvOdmIoModule_I2c:
+        *pPinMuxConfigTable = s_NvOdmPinMuxConfig_I2c;
+        *pCount = NVODM_PINMUX_ARRAY_SIZE(s_NvOdmPinMuxConfig_I2c);
+        break;
+
+    case NvOdmIoModule_I2c_Pmu:
+        *pPinMuxConfigTable = s_NvOdmPinMuxConfig_I2cPmu;
+        *pCount = NVODM_PINMUX_ARRAY_SIZE(s_NvOdmPinMuxConfig_I2cPmu);
+        break;
+
+    case NvOdmIoModule_Nand:
+        *pPinMuxConfigTable = s_NvOdmPinMuxConfig_Nand;
+        *pCount = NVODM_PINMUX_ARRAY_SIZE(s_NvOdmPinMuxConfig_Nand);
+        break;
+
+    case NvOdmIoModule_Sdio:
+       *pPinMuxConfigTable = s_NvOdmPinMuxConfig_Sdio;
+       *pCount = NVODM_PINMUX_ARRAY_SIZE(s_NvOdmPinMuxConfig_Sdio);
+        break;
+
+    case NvOdmIoModule_Spi:
+        *pPinMuxConfigTable = s_NvOdmPinMuxConfig_Spi;
+        *pCount = NVODM_PINMUX_ARRAY_SIZE(s_NvOdmPinMuxConfig_Spi);
+        break;
+
+    case NvOdmIoModule_Uart:
+        *pPinMuxConfigTable = s_NvOdmPinMuxConfig_Uart;
+        *pCount = NVODM_PINMUX_ARRAY_SIZE(s_NvOdmPinMuxConfig_Uart);
+        break;
+
+    case NvOdmIoModule_ExternalClock:
+        *pPinMuxConfigTable = s_NvOdmPinMuxConfig_ExternalClock;
+        *pCount = NVODM_PINMUX_ARRAY_SIZE(s_NvOdmPinMuxConfig_ExternalClock);
+        break;
+    
+    case NvOdmIoModule_Crt:
+        *pPinMuxConfigTable = s_NvOdmPinMuxConfig_Crt;
+        *pCount = NVODM_PINMUX_ARRAY_SIZE(s_NvOdmPinMuxConfig_Crt);
+        break;
+
+    case NvOdmIoModule_PciExpress:
+        *pPinMuxConfigTable = s_NvOdmPinMuxConfig_PciExpress;
+        *pCount = NVODM_PINMUX_ARRAY_SIZE(s_NvOdmPinMuxConfig_PciExpress); 
+        break;
+        
+    case NvOdmIoModule_Tvo:
+        *pPinMuxConfigTable = s_NvOdmPinMuxConfig_Tvo;
+        *pCount = NVODM_PINMUX_ARRAY_SIZE(s_NvOdmPinMuxConfig_Tvo);
+        break;
+    case NvOdmIoModule_BacklightPwm:
+        *pPinMuxConfigTable = s_NvOdmPinMuxConfig_BacklightPwm;
+        *pCount = NVODM_PINMUX_ARRAY_SIZE(s_NvOdmPinMuxConfig_BacklightPwm);
+        break;
+
+    case NvOdmIoModule_Pwm:
+        *pPinMuxConfigTable = s_NvOdmPinMuxConfig_Pwm;
+        *pCount = NVODM_PINMUX_ARRAY_SIZE(s_NvOdmPinMuxConfig_Pwm);
+        break;
+
+    case NvOdmIoModule_Ulpi:
+        *pPinMuxConfigTable = s_NvOdmPinMuxConfig_Ulpi;
+        *pCount = NVODM_PINMUX_ARRAY_SIZE(s_NvOdmPinMuxConfig_Ulpi);
+        break;
+
+    case NvOdmIoModule_Spdif:
+        *pPinMuxConfigTable = s_NvOdmPinMuxConfig_Spdif;
+        *pCount = NVODM_PINMUX_ARRAY_SIZE(s_NvOdmPinMuxConfig_Spdif);
+        break;
+
+    case NvOdmIoModule_Kbd:
+        *pPinMuxConfigTable = s_NvOdmPinMuxConfig_Kbd;
+        *pCount = NVODM_PINMUX_ARRAY_SIZE(s_NvOdmPinMuxConfig_Kbd);
+        break;
+
+    case NvOdmIoModule_Twc:
+    case NvOdmIoModule_Hsi:
+    case NvOdmIoModule_Ata:
+    case NvOdmIoModule_SyncNor:
+    case NvOdmIoModule_Mio:
+    case NvOdmIoModule_VideoInput:
+    case NvOdmIoModule_OneWire:
+        *pPinMuxConfigTable = NULL;
+        *pCount = 0;
+        break;
+
+    default:
+        *pCount = 0;
+        break;
+    }
+}
+
+void
+NvOdmQueryClockLimits(
+    NvOdmIoModule IoModule,
+    const NvU32 **pClockSpeedLimits,
+    NvU32 *pCount)
+{
+    switch (IoModule)
+    {
+        default:
+            *pClockSpeedLimits = NULL;
+            *pCount = 0;
+            break;
+    }
+}
+
diff --git a/arch/arm/mach-tegra/odm_kit/query/harmony/subboards/nvodm_query_discovery_e1162_addresses.h b/arch/arm/mach-tegra/odm_kit/query/harmony/subboards/nvodm_query_discovery_e1162_addresses.h
new file mode 100644
index 000000000000..000fd861577e
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/query/harmony/subboards/nvodm_query_discovery_e1162_addresses.h
@@ -0,0 +1,428 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/**
+ * @file
+ * <b>NVIDIA APX ODM Kit::
+ *         Implementation of the ODM Peripheral Discovery API</b>
+ *
+ * @b Description: Specifies the peripheral connectivity database NvOdmIoAddress entries
+ *                 for the peripherals on E1162 module.
+ */
+
+#include "pmu/tps6586x/nvodm_pmu_tps6586x_supply_info_table.h"
+#include "tmon/adt7461/nvodm_tmon_adt7461_channel.h"
+#include "nvodm_tmon.h"
+#include "../nvodm_query_kbc_gpio_def.h"
+
+
+// RTC voltage rail
+static const NvOdmIoAddress s_RtcAddresses[] = 
+{
+    { NvOdmIoModule_Vdd, 0x00, TPS6586xPmuSupply_LDO2 }  /* VDD_RTC -> LD02 */
+};
+
+// Core voltage rail
+static const NvOdmIoAddress s_CoreAddresses[] = 
+{
+    { NvOdmIoModule_Vdd, 0x00, TPS6586xPmuSupply_DCD0 }  /* VDD_CORE -> SM0 */
+};
+
+// CPU voltage rail
+static const NvOdmIoAddress s_ffaCpuAddresses[] = 
+{
+    { NvOdmIoModule_Vdd, 0x00, TPS6586xPmuSupply_DCD1 }  /* VDD_CPU -> SM1 */
+};
+
+// PLLA voltage rail
+static const NvOdmIoAddress s_PllAAddresses[] = 
+{
+    { NvOdmIoModule_Vdd, 0x00, TPS6586xPmuSupply_LDO1 } /* AVDDPLLX_1V2 -> LDO1 */
+};
+
+// PLLM voltage rail
+static const NvOdmIoAddress s_PllMAddresses[] = 
+{
+    { NvOdmIoModule_Vdd, 0x00, TPS6586xPmuSupply_LDO1 } /* AVDDPLLX_1V2 -> LDO1 */
+};
+
+// PLLP voltage rail
+static const NvOdmIoAddress s_PllPAddresses[] = 
+{
+    { NvOdmIoModule_Vdd, 0x00, TPS6586xPmuSupply_LDO1 } /* AVDDPLLX_1V2 -> LDO1 */
+};
+
+// PLLC voltage rail
+static const NvOdmIoAddress s_PllCAddresses[] = 
+{
+    { NvOdmIoModule_Vdd, 0x00, TPS6586xPmuSupply_LDO1 } /* AVDDPLLX_1V2 -> LDO1 */
+};
+
+// PLLE voltage rail
+static const NvOdmIoAddress s_PllEAddresses[] = 
+{
+    { NvOdmIoModule_Vdd, 0x00, Ext_TPS62290PmuSupply_BUCK } /* AVDD_PLLE -> VDD_1V05 */
+};
+
+// PLLU voltage rail
+static const NvOdmIoAddress s_PllUAddresses[] = 
+{
+    { NvOdmIoModule_Vdd, 0x00, TPS6586xPmuSupply_LDO1 } /* AVDD_PLLU -> LDO1 */
+};
+
+// PLLU1 voltage rail
+static const NvOdmIoAddress s_ffaPllU1Addresses[] = 
+{
+    { NvOdmIoModule_Vdd, 0x00, TPS6586xPmuSupply_LDO1 } /* AVDD_PLLU -> LDO1 */
+};
+
+// PLLS voltage rail
+static const NvOdmIoAddress s_PllSAddresses[] = 
+{
+    { NvOdmIoModule_Vdd, 0x00, TPS6586xPmuSupply_LDO1 } /* PLL_S -> LDO1 */
+};
+
+// PLLHD voltage rail
+static const NvOdmIoAddress s_PllHdmiAddresses[] = 
+{
+    { NvOdmIoModule_Vdd, 0x00, TPS6586xPmuSupply_LDO8 } /* AVDD_HDMI_PLL -> LDO8 */
+};
+
+// OSC voltage rail
+static const NvOdmIoAddress s_VddOscAddresses[] = 
+{
+    { NvOdmIoModule_Vdd, 0x00, TPS6586xPmuSupply_LDO4 } /* AVDD_OSC -> LDO4 */
+};
+
+// PLLX voltage rail
+static const NvOdmIoAddress s_PllXAddresses[] = 
+{
+    { NvOdmIoModule_Vdd, 0x00, TPS6586xPmuSupply_LDO1 } /* AVDDPLLX -> LDO1 */
+};
+
+// PLL_USB voltage rail
+static const NvOdmIoAddress s_PllUsbAddresses[] = 
+{
+    { NvOdmIoModule_Vdd, 0x00, TPS6586xPmuSupply_LDO3 } /* AVDD_USB_PLL -> derived from LDO3 (VDD_3V3) */
+};
+
+// SYS IO voltage rail
+static const NvOdmIoAddress s_VddSysAddresses[] = 
+{
+    { NvOdmIoModule_Vdd, 0x00, TPS6586xPmuSupply_LDO4 } /* VDDIO_SYS -> LDO4 */
+};
+
+// USB voltage rail
+static const NvOdmIoAddress s_VddUsbAddresses[] = 
+{
+    { NvOdmIoModule_Vdd, 0x00, TPS6586xPmuSupply_LDO3 } /* AVDD_USB -> derived from LDO3 (VDD_3V3) */
+};
+
+// HDMI voltage rail
+static const NvOdmIoAddress s_VddHdmiAddresses[] = 
+{
+    { NvOdmIoModule_Vdd, 0x00, TPS6586xPmuSupply_LDO7 } /* AVDD_HDMI -> LDO7 */
+};
+
+// MIPI voltage rail (DSI_CSI)
+static const NvOdmIoAddress s_VddMipiAddresses[] = 
+{
+    { NvOdmIoModule_Vdd, 0x00, Ext_TPS72012PmuSupply_LDO  } /* AVDD_DSI_CSI -> VDD_1V2 */
+};
+
+// LCD voltage rail
+static const NvOdmIoAddress s_VddLcdAddresses[] = 
+{
+    // This is in the AON domain
+    { NvOdmIoModule_Vdd, 0x00, TPS6586xPmuSupply_LDO4 } /* VDDIO_LCD -> (LDO4PG) */
+};
+
+// Audio voltage rail
+static const NvOdmIoAddress s_VddAudAddresses[] = 
+{
+    // This is in the AON domain
+    { NvOdmIoModule_Vdd, 0x00, TPS6586xPmuSupply_LDO4 } /* VDDIO_AUDIO -> (LDO4PG) */
+};
+
+// DDR voltage rail
+static const NvOdmIoAddress s_VddDdrAddresses[] = 
+{
+    // This is in the AON domain
+    { NvOdmIoModule_Vdd, 0x00, TPS6586xPmuSupply_LDO4 }  /* VDDIO_DDR -> (LDO4PG) */
+};
+
+// DDR_RX voltage rail
+static const NvOdmIoAddress s_VddDdrRxAddresses[] = 
+{
+    { NvOdmIoModule_Vdd, 0x00, TPS6586xPmuSupply_LDO9 }  /* VDDIO_RX_DDR(2.7-3.3) -> LDO9 */
+};
+
+// NAND voltage rail
+static const NvOdmIoAddress s_VddNandAddresses[] = 
+{
+    // This is in the AON domain
+    { NvOdmIoModule_Vdd, 0x00, TPS6586xPmuSupply_LDO3 }  /* VDDIO_NAND_3V3 -> derived from LDO3 (VDD_3V3) */
+};
+
+// UART voltage rail
+static const NvOdmIoAddress s_VddUartAddresses[] = 
+{
+    // This is in the AON domain
+    { NvOdmIoModule_Vdd, 0x00, TPS6586xPmuSupply_LDO4 } /* VDDIO_UART -> (LDO4PG) */
+};
+
+// SDIO voltage rail
+static const NvOdmIoAddress s_VddSdioAddresses[] = 
+{
+    { NvOdmIoModule_Vdd, 0x00, TPS6586xPmuSupply_LDO3 } /* VDDIO_SDIO -> derived from LDO3 (VDD_3V3) */
+};
+
+// VDAC voltage rail
+static const NvOdmIoAddress s_VddVdacAddresses[] = 
+{
+    { NvOdmIoModule_Vdd, 0x00, TPS6586xPmuSupply_LDO6 } /* AVDD_VDAC -> LDO6 */
+};
+
+// VI voltage rail
+static const NvOdmIoAddress s_VddViAddresses[] = 
+{
+    { NvOdmIoModule_Vdd, 0x00, TPS6586xPmuSupply_LDO3 } /* VDDIO_VI -> derived from LDO3 (VDD_3V3) */
+};
+
+// BB voltage rail
+static const NvOdmIoAddress s_VddBbAddresses[] = 
+{
+    // This is in the AON domain
+    { NvOdmIoModule_Vdd, 0x00, TPS6586xPmuSupply_LDO4 } /* VDDIO_BB -> (LDO4PG) */
+};
+
+// Super power voltage rail for the SOC
+static const NvOdmIoAddress s_VddSocAddresses[]=
+{
+    { NvOdmIoModule_Vdd, 0x00, TPS6586xPmuSupply_SoC } /* VDD SOC */
+};
+
+// PEX_CLK voltage rail
+static const NvOdmIoAddress s_VddPexClkAddresses[] = 
+{
+    { NvOdmIoModule_Vdd, 0x00, TPS6586xPmuSupply_LDO0 }, /* VDDIO_PEX_CLK -> LDO0 */
+    { NvOdmIoModule_Vdd, 0x00, Ext_TPS62290PmuSupply_BUCK }, /* AVDD_PLLE -> VDD_1V05 */
+    { NvOdmIoModule_Vdd, 0x00, Ext_TPS74201PmuSupply_LDO }, /* PMU_GPIO-1 -> VDD_1V5 */
+};
+
+// PMU0
+static const NvOdmIoAddress s_Pmu0Addresses[] = 
+{
+    { NvOdmIoModule_I2c_Pmu, 0x00, 0x68 },
+};
+
+// SPI1 for Spi Ethernet Kitl only
+static const NvOdmIoAddress s_SpiEthernetAddresses[] =
+{
+    { NvOdmIoModule_Spi, 0, 0 },
+    { NvOdmIoModule_Gpio, (NvU32)'c'-'a', 1 },  // DBQ_IRQ, Port C, Pin 1
+};
+
+// P1160 ULPI USB
+static const NvOdmIoAddress s_UlpiUsbAddresses[] = 
+{
+    { NvOdmIoModule_ExternalClock, 1, 0 }, /* ULPI PHY Clock -> DAP_MCLK2 */
+};
+
+//  LVDS LCD Display
+static const NvOdmIoAddress s_LvdsDisplayAddresses[] = 
+{
+    { NvOdmIoModule_Display, 0, 0 },
+    { NvOdmIoModule_Vdd, 0x00, TPS6586xPmuSupply_LDO4},     /* VDDIO_LCD (AON:VDD_1V8) */
+    { NvOdmIoModule_Vdd, 0x00, TPS6586xPmuSupply_LDO3 },    /* VDD_LVDS (VDD_3V3) */
+};
+
+//  HDMI addresses based on Concorde 2 design
+static const NvOdmIoAddress s_HdmiAddresses[] =
+{
+    { NvOdmIoModule_Hdmi, 0, 0 },
+
+    // Display Data Channel (DDC) for Extended Display Identification
+    // Data (EDID)
+    { NvOdmIoModule_I2c, 0x01, 0xA0 },
+
+    // HDCP ROM
+    { NvOdmIoModule_I2c, 0x01, 0x74 },
+
+    /* AVDD_HDMI */
+    { NvOdmIoModule_Vdd, 0x00, Ext_TPS2051BPmuSupply_VDDIO_VID },   // VDDIO_HDMI
+    { NvOdmIoModule_Vdd, 0x00, TPS6586xPmuSupply_LDO8 },            // AVDD_HDMI_PLL
+
+    /* lcd i/o rail (for hot plug pin) */
+    { NvOdmIoModule_Vdd, 0x00, TPS6586xPmuSupply_LDO4 },    // VDDIO_LCD (VDD_1V8)
+};
+
+// CRT address based on Concorde 2 design
+static const NvOdmIoAddress s_CrtAddresses[] =
+{
+    { NvOdmIoModule_Crt, 0, 0 },
+
+    // Display Data Channel (DDC) for Extended Display Identification
+    // Data (EDID)
+    // FIXME: Disable this for now since it causes some TV not display.
+    { NvOdmIoModule_I2c, 0x01, 0xA0 },
+
+    /* tvdac rail */
+    { NvOdmIoModule_Vdd, 0x00, TPS6586xPmuSupply_LDO6 },    // VDDIO_VDAC
+
+    /* lcd rail (required for crt out) */
+    { NvOdmIoModule_Vdd, 0x00, TPS6586xPmuSupply_LDO4 },    // VDDIO_LCD (VDD_1V8)
+    { NvOdmIoModule_Vdd, 0x00, Ext_TPS2051BPmuSupply_VDDIO_VID },   // VDDIO_VGA
+};
+
+static const NvOdmIoAddress s_ffaVideoDacAddresses[] =
+{
+    { NvOdmIoModule_Tvo, 0x00, 0x00 },
+    /* tvdac rail */
+    { NvOdmIoModule_Vdd, 0x00, TPS6586xPmuSupply_LDO6 },    // AVDD_VDAC
+};
+
+// Sdio
+static const NvOdmIoAddress s_SdioAddresses[] =
+{
+    { NvOdmIoModule_Sdio, 0x1,  0x0 },                      /* SD Memory on SD Bus */
+    { NvOdmIoModule_Sdio, 0x3,  0x0 },                      /* SD Memory on SD Bus */
+    { NvOdmIoModule_Vdd,  0x00, Ext_SWITCHPmuSupply_VDDIO_SD },   /* EN_VDDIO_SD */
+    { NvOdmIoModule_Vdd, 0x00, TPS6586xPmuSupply_LDO3 } /* VDDIO_SDIO -> derived from LDO3 (VDD_3V3) */
+};
+
+static const NvOdmIoAddress s_I2cSmbusAddresses[] = 
+{
+    { NvOdmIoModule_I2c, 2, 0x8A },
+    { NvOdmIoModule_Gpio, 27, 1} //Port BB:01 is used on harmony. 
+};
+
+static const NvOdmIoAddress s_UsbMuxAddress[] = 
+{
+    {NvOdmIoModule_Usb, 1, 0}
+};
+
+static const NvOdmIoAddress s_QwertyKeyPad16x8Addresses[] =
+{
+    // instance = 1 indicates Column info.
+    // instance = 0 indicates Row info.
+    // address holds KBC pin number used for row/column.
+
+    // All Row info has to be defined contiguously from 0 to max.
+    { NvOdmIoModule_Kbd, 0x00, NvOdmKbcGpioPin_KBRow0}, // Row 0
+    { NvOdmIoModule_Kbd, 0x00, NvOdmKbcGpioPin_KBRow1}, // Row 1
+    { NvOdmIoModule_Kbd, 0x00, NvOdmKbcGpioPin_KBRow2}, // Row 2
+    { NvOdmIoModule_Kbd, 0x00, NvOdmKbcGpioPin_KBRow3}, // Row 3
+    { NvOdmIoModule_Kbd, 0x00, NvOdmKbcGpioPin_KBRow4}, // Row 4
+    { NvOdmIoModule_Kbd, 0x00, NvOdmKbcGpioPin_KBRow5}, // Row 5
+    { NvOdmIoModule_Kbd, 0x00, NvOdmKbcGpioPin_KBRow6}, // Row 6
+    { NvOdmIoModule_Kbd, 0x00, NvOdmKbcGpioPin_KBRow7}, // Row 7
+    { NvOdmIoModule_Kbd, 0x00, NvOdmKbcGpioPin_KBRow8}, // Row 8
+    { NvOdmIoModule_Kbd, 0x00, NvOdmKbcGpioPin_KBRow9}, // Row 9
+    { NvOdmIoModule_Kbd, 0x00, NvOdmKbcGpioPin_KBRow10}, // Row 10
+    { NvOdmIoModule_Kbd, 0x00, NvOdmKbcGpioPin_KBRow11}, // Row 11
+    { NvOdmIoModule_Kbd, 0x00, NvOdmKbcGpioPin_KBRow12}, // Row 12
+    { NvOdmIoModule_Kbd, 0x00, NvOdmKbcGpioPin_KBRow13}, // Row 13
+    { NvOdmIoModule_Kbd, 0x00, NvOdmKbcGpioPin_KBRow14}, // Row 14
+    { NvOdmIoModule_Kbd, 0x00, NvOdmKbcGpioPin_KBRow15}, // Row 15
+    
+    // All Column info has to be defined contiguously from 0 to max.
+    { NvOdmIoModule_Kbd, 0x01, NvOdmKbcGpioPin_KBCol0}, // Column 0
+    { NvOdmIoModule_Kbd, 0x01, NvOdmKbcGpioPin_KBCol1}, // Column 1
+    { NvOdmIoModule_Kbd, 0x01, NvOdmKbcGpioPin_KBCol2}, // Column 2
+    { NvOdmIoModule_Kbd, 0x01, NvOdmKbcGpioPin_KBCol3}, // Column 3
+    { NvOdmIoModule_Kbd, 0x01, NvOdmKbcGpioPin_KBCol4}, // Column 4
+    { NvOdmIoModule_Kbd, 0x01, NvOdmKbcGpioPin_KBCol5}, // Column 5
+    { NvOdmIoModule_Kbd, 0x01, NvOdmKbcGpioPin_KBCol6}, // Column 6
+    { NvOdmIoModule_Kbd, 0x01, NvOdmKbcGpioPin_KBCol7}, // Column 7
+};
+
+
+static const NvOdmIoAddress s_Tmon0Addresses[] = 
+{
+    { NvOdmIoModule_I2c_Pmu, 0x00, 0x98 },                  /* I2C bus */
+    { NvOdmIoModule_Vdd, 0x00, TPS6586xPmuSupply_LDO3 },    /* TMON pwer rail -> LDO3 (VDD_3V3) */
+    { NvOdmIoModule_Gpio, (NvU32)'n'-'a', 6 },              /* GPIO Port N and Pin 6 */
+
+    /* Temperature zone mapping */
+    { NvOdmIoModule_Tsense, NvOdmTmonZoneID_Core, ADT7461ChannelID_Remote },   /* TSENSOR */
+    { NvOdmIoModule_Tsense, NvOdmTmonZoneID_Ambient, ADT7461ChannelID_Local }, /* TSENSOR */
+};
+
+// Bluetooth
+static const NvOdmIoAddress s_p1162BluetoothAddresses[] =
+{
+    { NvOdmIoModule_Uart, 0x2,  0x0 },                  // FIXME: Is this used?
+    { NvOdmIoModule_Gpio, (NvU32)'u'-'a', 0 },          /* BT_RST#: GPIO Port U and Pin 0 */
+    { NvOdmIoModule_Vdd, 0x00, TPS6586xPmuSupply_LDO4 } /* VDDHOSTIF_BT -> LDO4 (AON:VDD_1V8) */
+};
+
+// Wlan
+static const NvOdmIoAddress s_WlanAddresses[] =
+{
+    { NvOdmIoModule_Sdio, 0x0, 0x0 },                      /* WLAN is on SD Bus */
+    { NvOdmIoModule_Gpio, 0xa, 0x5 },                      /* GPIO Port K and Pin 5 - WIFI_PWR*/
+    { NvOdmIoModule_Gpio, 0xa, 0x6 },                      /* GPIO Port K and Pin 6 - WIFI_RST */
+    { NvOdmIoModule_Vdd,  0x00, TPS6586xPmuSupply_LDO4 },  /* VDDIO_WLAN (AON:VDD_1V8) */
+    { NvOdmIoModule_Vdd,  0x00, Ext_TPS72012PmuSupply_LDO } /* VCORE_WIFI (VDD_1V2) */
+};
+
+// Audio Codec
+static const NvOdmIoAddress s_AudioCodecAddresses[] = 
+{
+    { NvOdmIoModule_ExternalClock, 0, 0 },       /* Codec MCLK -> APxx DAP_MCLK1 */
+    { NvOdmIoModule_I2c_Pmu, 0x00, 0x34 },       /* Codec I2C ->  APxx PMU I2C, segment 0 */
+                                                 /* Codec I2C address is 0x34 */
+};
+
+// Audio Codec on GEN1_I2C (I2C_1)
+static const NvOdmIoAddress s_AudioCodecAddressesI2C_1[] = 
+{
+    { NvOdmIoModule_ExternalClock, 0, 0 },       /* Codec MCLK -> APxx DAP_MCLK1 */
+    { NvOdmIoModule_I2c, 0x00, 0x34 },           /* Codec I2C ->  APxx PMU I2C, segment 0 */
+                                                 /* Codec I2C address is 0x34 */
+};
+
+// TouchPanel
+static const NvOdmIoAddress s_TouchPanelAddresses[] = 
+{
+    { NvOdmIoModule_I2c_Pmu, 0x00, 0x06 }, /* I2C address (7-bit) 0x03<<1=0x06(8-bit)  */
+    { NvOdmIoModule_Gpio, (NvU32)'d'-'a', 0x02 }, /* GPIO Port D and Pin 2 */
+};
+
+static const NvOdmIoAddress s_AcceleroAddresses[] =
+{
+    { NvOdmIoModule_I2c_Pmu, 0x00, 0x70 }, /* I2C address (7-bit) 0x38<<1 = 0x70(8-bit) */
+    { NvOdmIoModule_Gpio, (NvU32)'c'-'a', 0x03 }, /* Gpio port C and Pin 3 */
+};
+
+
diff --git a/arch/arm/mach-tegra/odm_kit/query/harmony/subboards/nvodm_query_discovery_e1162_peripherals.h b/arch/arm/mach-tegra/odm_kit/query/harmony/subboards/nvodm_query_discovery_e1162_peripherals.h
new file mode 100644
index 000000000000..df91cc1e6d22
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/query/harmony/subboards/nvodm_query_discovery_e1162_peripherals.h
@@ -0,0 +1,453 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/**
+ * @file
+ * <b>NVIDIA APX ODM Kit::
+ *         Implementation of the ODM Peripheral Discovery API</b>
+ *
+ * @b Description: Specifies the peripheral connectivity database Peripheral entries
+ *                 for the peripherals on P1162 module.
+ */
+// AP20 doesn't have PLL_D rail.
+// PLLD (NV reserved) / Use PLL_U
+{
+    NV_VDD_PLLD_ODM_ID,
+    s_PllUAddresses,
+    NV_ARRAY_SIZE(s_PllUAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// RTC (NV reserved)
+{
+    NV_VDD_RTC_ODM_ID,
+    s_RtcAddresses,
+    NV_ARRAY_SIZE(s_RtcAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// CORE (NV reserved)
+{
+    NV_VDD_CORE_ODM_ID,
+    s_CoreAddresses,
+    NV_ARRAY_SIZE(s_CoreAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// CPU (NV reserved)
+{
+    NV_VDD_CPU_ODM_ID,
+    s_ffaCpuAddresses,
+    NV_ARRAY_SIZE(s_ffaCpuAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// PLLA (NV reserved)
+{
+    NV_VDD_PLLA_ODM_ID,
+    s_PllAAddresses,
+    NV_ARRAY_SIZE(s_PllAAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// PLLM (NV reserved)
+{
+    NV_VDD_PLLM_ODM_ID,
+    s_PllMAddresses,
+    NV_ARRAY_SIZE(s_PllMAddresses),
+    NvOdmPeripheralClass_Other
+},
+    
+// PLLP (NV reserved)
+{
+    NV_VDD_PLLP_ODM_ID,
+    s_PllPAddresses,
+    NV_ARRAY_SIZE(s_PllPAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// PLLC (NV reserved)
+{
+    NV_VDD_PLLC_ODM_ID,
+    s_PllCAddresses,
+    NV_ARRAY_SIZE(s_PllCAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// PLLE (NV reserved)
+{
+    NV_VDD_PLLE_ODM_ID,
+    s_PllEAddresses,
+    NV_ARRAY_SIZE(s_PllEAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// PLLU (NV reserved)
+{
+    NV_VDD_PLLU_ODM_ID,
+    s_PllUAddresses,
+    NV_ARRAY_SIZE(s_PllUAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// PLLU1 (NV reserved)
+{
+    NV_VDD_PLLU1_ODM_ID,
+    s_ffaPllU1Addresses,
+    NV_ARRAY_SIZE(s_ffaPllU1Addresses),
+    NvOdmPeripheralClass_Other
+},
+
+// PLLS (NV reserved)
+{
+    NV_VDD_PLLS_ODM_ID,
+    s_PllSAddresses,
+    NV_ARRAY_SIZE(s_PllSAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// HDMI PLL (NV reserved)
+{
+    NV_VDD_PLLHDMI_ODM_ID,
+    s_PllHdmiAddresses,
+    NV_ARRAY_SIZE(s_PllHdmiAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// OSC VDD (NV reserved)
+{
+    NV_VDD_OSC_ODM_ID,
+    s_VddOscAddresses,
+    NV_ARRAY_SIZE(s_VddOscAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// PLLX (NV reserved)
+{
+    NV_VDD_PLLX_ODM_ID,
+    s_PllXAddresses,
+    NV_ARRAY_SIZE(s_PllXAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// PLL_USB (NV reserved)
+{
+    NV_VDD_PLL_USB_ODM_ID,
+    s_PllUsbAddresses,
+    NV_ARRAY_SIZE(s_PllUsbAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// System IO VDD (NV reserved)
+{
+    NV_VDD_SYS_ODM_ID,
+    s_VddSysAddresses,
+    NV_ARRAY_SIZE(s_VddSysAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// USB VDD (NV reserved)
+{
+    NV_VDD_USB_ODM_ID,
+    s_VddUsbAddresses,
+    NV_ARRAY_SIZE(s_VddUsbAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// HDMI VDD (NV reserved)
+{
+    NV_VDD_HDMI_ODM_ID,
+    s_VddHdmiAddresses,
+    NV_ARRAY_SIZE(s_VddHdmiAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// MIPI VDD (NV reserved) / AVDD_DSI_CSI
+{
+    NV_VDD_MIPI_ODM_ID,
+    s_VddMipiAddresses,
+    NV_ARRAY_SIZE(s_VddMipiAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// LCD VDD (NV reserved)
+{
+    NV_VDD_LCD_ODM_ID,
+    s_VddLcdAddresses,
+    NV_ARRAY_SIZE(s_VddLcdAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// AUDIO VDD (NV reserved)
+{
+    NV_VDD_AUD_ODM_ID,
+    s_VddAudAddresses,
+    NV_ARRAY_SIZE(s_VddAudAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// DDR VDD (NV reserved)
+{
+    NV_VDD_DDR_ODM_ID,
+    s_VddDdrAddresses,
+    NV_ARRAY_SIZE(s_VddDdrAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// DDR_RX (NV reserved)
+{
+    NV_VDD_DDR_RX_ODM_ID,
+    s_VddDdrRxAddresses,
+    NV_ARRAY_SIZE(s_VddDdrRxAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// NAND VDD (NV reserved)
+{
+    NV_VDD_NAND_ODM_ID,
+    s_VddNandAddresses,
+    NV_ARRAY_SIZE(s_VddNandAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// UART VDD (NV reserved)
+{
+    NV_VDD_UART_ODM_ID,
+    s_VddUartAddresses,
+    NV_ARRAY_SIZE(s_VddUartAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// SDIO VDD (NV reserved)
+{
+    NV_VDD_SDIO_ODM_ID,
+    s_VddSdioAddresses,
+    NV_ARRAY_SIZE(s_VddSdioAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// VDAC VDD (NV reserved)
+{
+    NV_VDD_VDAC_ODM_ID,
+    s_VddVdacAddresses,
+    NV_ARRAY_SIZE(s_VddVdacAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// VI VDD (NV reserved)
+{
+    NV_VDD_VI_ODM_ID,
+    s_VddViAddresses,
+    NV_ARRAY_SIZE(s_VddViAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// BB VDD (NV reserved)
+{
+    NV_VDD_BB_ODM_ID,
+    s_VddBbAddresses,
+    NV_ARRAY_SIZE(s_VddBbAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// PEX_CLK (NV reserved)
+{
+    NV_VDD_PEX_CLK_ODM_ID,
+    s_VddPexClkAddresses,
+    NV_ARRAY_SIZE(s_VddPexClkAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+#if 0
+//  VBUS
+{
+    NV_VDD_VBUS_ODM_ID,
+    s_VddVBusAddresses,
+    NV_ARRAY_SIZE(s_VddVBusAddresses),
+    NvOdmPeripheralClass_Other
+},
+#endif
+
+//SOC
+{
+    NV_VDD_SoC_ODM_ID,
+    s_VddSocAddresses,
+    NV_ARRAY_SIZE(s_VddSocAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+//  PMU0
+{
+    NV_ODM_GUID('t','p','s','6','5','8','6','x'),
+    s_Pmu0Addresses,
+    NV_ARRAY_SIZE(s_Pmu0Addresses),
+    NvOdmPeripheralClass_Other
+},
+
+//  ENC28J60 SPI Ethernet module
+{
+    NV_ODM_GUID('e','n','c','2','8','j','6','0'),
+    s_SpiEthernetAddresses,
+    NV_ARRAY_SIZE(s_SpiEthernetAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+//  SMSC3317 ULPI USB PHY
+{
+    NV_ODM_GUID('s','m','s','c','3','3','1','7'),
+    s_UlpiUsbAddresses,
+    NV_ARRAY_SIZE(s_UlpiUsbAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+//  LVDS LCD Display
+{
+    NV_ODM_GUID('L','V','D','S','W','S','V','G'),   // LVDS WSVGA panel
+    s_LvdsDisplayAddresses,
+    NV_ARRAY_SIZE(s_LvdsDisplayAddresses),
+    NvOdmPeripheralClass_Display
+},
+
+// HDMI (based on Concorde 2 design)
+{
+    NV_ODM_GUID('f','f','a','2','h','d','m','i'),
+    s_HdmiAddresses,
+    NV_ARRAY_SIZE(s_HdmiAddresses),
+    NvOdmPeripheralClass_Display    
+},
+
+// CRT (based on Concorde 2 design)
+{
+    NV_ODM_GUID('f','f','a','_','_','c','r','t'),
+    s_CrtAddresses,
+    NV_ARRAY_SIZE(s_CrtAddresses),
+    NvOdmPeripheralClass_Display
+},
+
+// TV Out Video Dac
+{
+    NV_ODM_GUID('f','f','a','t','v','o','u','t'),
+    s_ffaVideoDacAddresses,
+    NV_ARRAY_SIZE(s_ffaVideoDacAddresses),
+    NvOdmPeripheralClass_Display
+},
+
+// Sdio
+{
+    NV_ODM_GUID('s','d','i','o','_','m','e','m'),
+    s_SdioAddresses,
+    NV_ARRAY_SIZE(s_SdioAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// I2c SmBus transport.
+{
+    NV_ODM_GUID('I','2','c','S','m','B','u','s'),
+    s_I2cSmbusAddresses,
+    NV_ARRAY_SIZE(s_I2cSmbusAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// USB Mux J7A1 and J6A1
+{
+   NV_ODM_GUID('u','s','b','m','x','J','7','6'),
+    s_UsbMuxAddress,
+    NV_ARRAY_SIZE(s_UsbMuxAddress),
+    NvOdmPeripheralClass_Other
+
+},
+
+// Qwerty key baord for 16x8
+{
+    NV_ODM_GUID('q','w','e','r','t','y',' ',' '),
+    s_QwertyKeyPad16x8Addresses,
+    NV_ARRAY_SIZE(s_QwertyKeyPad16x8Addresses),
+    NvOdmPeripheralClass_HCI
+},
+
+// Temperature Monitor (TMON)
+{
+    NV_ODM_GUID('a','d','t','7','4','6','1',' '),
+    s_Tmon0Addresses,
+    NV_ARRAY_SIZE(s_Tmon0Addresses),
+    NvOdmPeripheralClass_Other
+},
+
+// Bluetooth
+{
+    NV_ODM_GUID('b','l','u','t','o','o','t','h'),
+    s_p1162BluetoothAddresses,
+    NV_ARRAY_SIZE(s_p1162BluetoothAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// Sdio wlan  on COMMs Module
+{
+    NV_ODM_GUID('s','d','i','o','w','l','a','n'),
+    s_WlanAddresses,
+    NV_ARRAY_SIZE(s_WlanAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// Audio codec (I2C_PMU edition)
+{
+    NV_ODM_GUID('w','o','l','f','8','9','0','3'),
+    s_AudioCodecAddresses,
+    NV_ARRAY_SIZE(s_AudioCodecAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// Audio codec (I2C_1 edition)
+{
+    NV_ODM_GUID('w','o','8','9','0','3','_','1'),
+    s_AudioCodecAddressesI2C_1,
+    NV_ARRAY_SIZE(s_AudioCodecAddressesI2C_1),
+    NvOdmPeripheralClass_Other
+},
+
+// Touch panel
+{
+    NV_ODM_GUID('p','a','n','j','i','t','_','0'),
+    s_TouchPanelAddresses,
+    NV_ARRAY_SIZE(s_TouchPanelAddresses),
+    NvOdmPeripheralClass_HCI
+},
+
+// Accelerometer Module
+{
+    NV_ODM_GUID('b','m','a','1','5','0','a','c'),
+    s_AcceleroAddresses,
+    NV_ARRAY_SIZE(s_AcceleroAddresses),
+    NvOdmPeripheralClass_Other,
+},
+
+// NOTE: This list *must* end with a trailing comma.
diff --git a/arch/arm/mach-tegra/odm_kit/query/harmony/tegra_devkit_custopt.h b/arch/arm/mach-tegra/odm_kit/query/harmony/tegra_devkit_custopt.h
new file mode 100644
index 000000000000..1ec701091145
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/query/harmony/tegra_devkit_custopt.h
@@ -0,0 +1,153 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/**
+ * @file
+ * <b>NVIDIA Tegra ODM Kit:
+ *         Definition of bitfields inside the BCT customer option</b>
+ *
+ * @b Description: Defines the board-specific bitfields of the 
+ *                 BCT customer option parameter, for NVIDIA
+ *                 Tegra development platforms.
+ *  
+ *                 This file pertains to Whistler and Voyager.
+ */
+
+#ifndef NVIDIA_TEGRA_DEVKIT_CUSTOPT_H
+#define NVIDIA_TEGRA_DEVKIT_CUSTOPT_H
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+//---------- BOARD PERSONALITIES (BEGIN) ----------//
+// On the Whistler boards, be sure to match the following
+// switches with the personality setting you choose.
+// 
+//      SW2 = bits 3:0 (low nibble)
+//      SW3 = bits 7:4 (high nibble)
+
+#define TEGRA_DEVKIT_DEFAULT_PERSONALITY \
+    TEGRA_DEVKIT_BCT_CUSTOPT_0_PERSONALITY_75
+
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_PERSONALITY_RANGE     7:0
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_PERSONALITY_DEFAULT  0x0UL
+
+// VOYAGER, eMMC, NO TRACE (10x8 keypad)
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_PERSONALITY_01       0x01UL  // ULPI = baseband
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_PERSONALITY_05       0x05UL  // ULPI = UART1
+
+// VOYAGER, eMMC, with TRACE (7x1 keypad)
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_PERSONALITY_11       0x11UL  // ULPI = baseband
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_PERSONALITY_15       0x15UL  // ULPI = UART1
+
+// VOYAGER, NAND, NO TRACE (10x8 keypad)
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_PERSONALITY_75       0x75UL  // Voyager, NAND
+
+// WHISTLER, stand-alone
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_PERSONALITY_C1       0xC1UL  // KB = 13x1, TRACE, GMI = A/D NOR
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_PERSONALITY_C3       0xC3UL  // KB = 16x8, NO TRACE, GMI = NAND
+
+// VOYAGER, USB2-ULPI (No UART1)
+// Personality 71 is similar to the 75, except ULPI is enabled instead of UART1.
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_PERSONALITY_71       0x71UL  
+
+
+//---------- BOARD PERSONALITIES (END) ----------//
+
+/// Download transport
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_TRANSPORT_RANGE      10:8
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_TRANSPORT_DEFAULT    0x0UL
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_TRANSPORT_NONE       0x1UL
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_TRANSPORT_UART       0x2UL
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_TRANSPORT_USB        0x3UL
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_TRANSPORT_ETHERNET   0x4UL
+
+/// Transport option (bus selector), for UART and Ethernet transport
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_UART_OPTION_RANGE   12:11
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_UART_OPTION_DEFAULT 0x0UL
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_UART_OPTION_A       0x1UL
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_UART_OPTION_B       0x2UL
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_UART_OPTION_C       0x3UL
+
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_ETHERNET_OPTION_RANGE   12:11
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_ETHERNET_OPTION_DEFAULT 0x0UL
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_ETHERNET_OPTION_SPI     0x1UL
+
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_CONSOLE_OPTION_RANGE    17:15
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_CONSOLE_OPTION_DEFAULT  0
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_CONSOLE_OPTION_UARTA    0
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_CONSOLE_OPTION_UARTB    1
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_CONSOLE_OPTION_UARTC    2
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_CONSOLE_OPTION_UARTD    3
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_CONSOLE_OPTION_UARTE    4
+
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_CONSOLE_RANGE           19:18
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_CONSOLE_DEFAULT         0
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_CONSOLE_NONE            1
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_CONSOLE_DCC             2
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_CONSOLE_UART            3
+
+// display options
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_DISPLAY_OPTION_RANGE      22:20
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_DISPLAY_OPTION_DEFAULT    0x0UL
+// embedded panel (lvds, dsi, etc)
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_DISPLAY_OPTION_EMBEDDED   0x0UL
+// no panels (external or embedded)
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_DISPLAY_OPTION_NULL       0x1UL
+// use hdmi as the primary
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_DISPLAY_OPTION_HDMI       0x2UL
+// use crt as the primary 
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_DISPLAY_OPTION_CRT        0x3UL
+
+// Enable DHCP
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_DHCP_RANGE           23:23
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_DHCP_DEFAULT         0x0UL
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_DHCP_ENABLE          0x1UL
+
+/// Total RAM
+#define TEGRA_DEVKIT_BCT_SYSTEM_0_MEMORY_RANGE    30:28
+#define TEGRA_DEVKIT_BCT_SYSTEM_0_MEMORY_DEFAULT  0x0UL // 512 MB
+#define TEGRA_DEVKIT_BCT_SYSTEM_0_MEMORY_256      0x1UL // 256 MB
+#define TEGRA_DEVKIT_BCT_SYSTEM_0_MEMORY_512      0x2UL // 512 MB
+#define TEGRA_DEVKIT_BCT_SYSTEM_0_MEMORY_1024     0x3UL // 1024 MB (1 GB)
+
+/// Soc low power state
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_LPSTATE_RANGE            31:31
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_LPSTATE_LP0              0x0UL
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_LPSTATE_LP1              0x1UL
+#if defined(__cplusplus)
+}
+#endif
+
+#endif
diff --git a/arch/arm/mach-tegra/odm_kit/query/whistler/Makefile b/arch/arm/mach-tegra/odm_kit/query/whistler/Makefile
new file mode 100644
index 000000000000..cd3c24b7f540
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/query/whistler/Makefile
@@ -0,0 +1,18 @@
+ccflags-y += -DNV_IS_AVP=0
+ccflags-y += -DNV_OAL=0
+ccflags-y += -DNV_USE_FUSE_CLOCK_ENABLE=0
+ifeq ($(CONFIG_MACH_TEGRA_GENERIC_DEBUG),y)
+ccflags-y += -DNV_DEBUG=1
+else
+ccflags-y += -DNV_DEBUG=0
+endif
+
+ccflags-y += -Iarch/arm/mach-tegra/odm_kit/adaptations
+
+obj-y += nvodm_query.o
+obj-y += nvodm_query_discovery.o
+obj-y += nvodm_query_nand.o
+obj-y += nvodm_query_gpio.o
+obj-y += nvodm_query_pinmux.o
+obj-y += nvodm_query_kbc.o
+
diff --git a/arch/arm/mach-tegra/odm_kit/query/whistler/include/nvodm_imager_guids.h b/arch/arm/mach-tegra/odm_kit/query/whistler/include/nvodm_imager_guids.h
new file mode 100644
index 000000000000..869aedf1eb67
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/query/whistler/include/nvodm_imager_guids.h
@@ -0,0 +1,191 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+#ifndef NVODM_IMAGER_GUIDS_H
+#define NVODM_IMAGER_GUIDS_H
+
+#include "nvodm_query_discovery.h"
+
+// E912-A02 and Concorde2 Sensors
+#define OV5630_GUID NV_ODM_GUID('s','_','O','V','5','6','3','0')
+
+// E911 Sensors
+#define MI5130_GUID NV_ODM_GUID('s','_','M','I','5','1','3','0')
+#define SEMCOVGA_GUID NV_ODM_GUID('S','E','M','C','O','V','G','A')
+
+// E911 Focusers
+// focuser for MI5130
+#define DW9710_GUID NV_ODM_GUID('f','_','D','W','9','7','1','0')
+
+/// focuser for OV5630
+#define AD5820_GUID NV_ODM_GUID('f','_','A','D','5','8','2','0')
+
+// E911 Flash
+#define LTC3216_GUID NV_ODM_GUID('l','_','L','T','3','2','1','6')
+
+// io addresses common to all imagers (clock)
+#define COMMONIMAGER_GUID NV_ODM_GUID('s', '_', 'c', 'o', 'm', 'm', 'o', 'n')
+
+// Pin Use Codes:
+// VI/CSI Parallel and Serial Pins and GPIO Pins
+
+// More than one device may be retrieved thru the query
+#define NVODM_CAMERA_DEVICE_IS_DEFAULT   (1)
+
+// The imager devices can connect to the parallel bus or the serial bus
+// Parallel connections use pins VD0 thru VD9.
+// Serial connections use the mipi pins (ex: CSI_D1AN/CSI_D1AP)
+#define NVODM_CAMERA_DATA_PIN_SHIFT      (1)
+#define NVODM_CAMERA_DATA_PIN_MASK       0x0F
+#define NVODM_CAMERA_PARALLEL_VD0_TO_VD9 (1 << NVODM_CAMERA_DATA_PIN_SHIFT)
+#define NVODM_CAMERA_PARALLEL_VD0_TO_VD7 (2 << NVODM_CAMERA_DATA_PIN_SHIFT)
+#define NVODM_CAMERA_SERIAL_CSI_D1A      (4 << NVODM_CAMERA_DATA_PIN_SHIFT)
+#define NVODM_CAMERA_SERIAL_CSI_D2A      (5 << NVODM_CAMERA_DATA_PIN_SHIFT)
+#define NVODM_CAMERA_SERIAL_CSI_D1A_D2A  (6 << NVODM_CAMERA_DATA_PIN_SHIFT)
+#define NVODM_CAMERA_SERIAL_CSI_D1B      (7 << NVODM_CAMERA_DATA_PIN_SHIFT)
+
+// Switching the encoding from the VideoInput module address to use with
+// each GPIO module address.
+// NVODM_IMAGER_GPIO will tell the nvodm imager how to use each gpio
+// A gpio can be used for powerdown (lo, hi) or !powerdown (hi, lo)
+// used for reset (hi, lo, hi) or for !reset (lo, hi, lo)
+// Or, for mclk or pwm (unimplemented yet)
+// We have moved the flash to its own, so it is not needed here
+#define NVODM_IMAGER_GPIO_PIN_SHIFT    (24)
+#define NVODM_IMAGER_UNUSED            (0x0)
+#define NVODM_IMAGER_RESET             (0x1 << NVODM_IMAGER_GPIO_PIN_SHIFT)
+#define NVODM_IMAGER_RESET_AL          (0x2 << NVODM_IMAGER_GPIO_PIN_SHIFT)
+#define NVODM_IMAGER_POWERDOWN         (0x3 << NVODM_IMAGER_GPIO_PIN_SHIFT)
+#define NVODM_IMAGER_POWERDOWN_AL      (0x4 << NVODM_IMAGER_GPIO_PIN_SHIFT)
+// only on VGP0
+#define NVODM_IMAGER_MCLK              (0x8 << NVODM_IMAGER_GPIO_PIN_SHIFT)
+// only on VGP6
+#define NVODM_IMAGER_PWM               (0x9 << NVODM_IMAGER_GPIO_PIN_SHIFT)
+// If flash code wants the gpio's labelled
+// use for any purpose, or not at all
+#define NVODM_IMAGER_FLASH0           (0x5 << NVODM_IMAGER_GPIO_PIN_SHIFT)
+#define NVODM_IMAGER_FLASH1           (0x6 << NVODM_IMAGER_GPIO_PIN_SHIFT)
+#define NVODM_IMAGER_FLASH2           (0x7 << NVODM_IMAGER_GPIO_PIN_SHIFT)
+// Shutter control
+#define NVOSM_IMAGER_SHUTTER          (0xA << NVODM_IMAGER_GPIO_PIN_SHIFT)
+// 
+
+#define NVODM_IMAGER_MASK              (0xF << NVODM_IMAGER_GPIO_PIN_SHIFT)
+#define NVODM_IMAGER_CLEAR(_s)         ((_s) & ~(NVODM_IMAGER_MASK))
+#define NVODM_IMAGER_IS_SET(_s)        (((_s) & (NVODM_IMAGER_MASK)) != 0)
+#define NVODM_IMAGER_FIELD(_s)         ((_s) >> NVODM_IMAGER_GPIO_PIN_SHIFT)
+
+// The imager devices can connect to the vi gpio (VGP) pins
+// for various reasons: flash, powerdown, reset, pwm, mclk.
+// Only certain pins can be used for certain activities.
+// These flags should be OR'd together to form the proper 'address'
+// in the NvOdmIoAddress for VideoInput.
+// VGP1 & VGP2 are used for i2c
+// _AL means 'active low', otherwise active high is assumed
+
+#define NVODM_CAMERA_GPIO_PIN_SHIFT        (8)
+#define NVODM_CAMERA_GPIO_PIN_MASK         (0x7)
+#define NVODM_CAMERA_GPIO_PIN_WIDTH         3
+#define NVODM_CAMERA_GPIO_PIN_COUNT         7
+
+#define NVODM_CAMERA_UNUSED                (0x0)
+#define NVODM_CAMERA_RESET(_s)         (0x1 << (_s+NVODM_CAMERA_GPIO_PIN_SHIFT))
+#define NVODM_CAMERA_RESET_AL(_s)      (0x2 << (_s+NVODM_CAMERA_GPIO_PIN_SHIFT))
+#define NVODM_CAMERA_POWERDOWN(_s)     (0x3 << (_s+NVODM_CAMERA_GPIO_PIN_SHIFT))
+#define NVODM_CAMERA_POWERDOWN_AL(_s)  (0x4 << (_s+NVODM_CAMERA_GPIO_PIN_SHIFT))
+#define NVODM_CAMERA_FLASH_LOW(_s)     (0x5 << (_s+NVODM_CAMERA_GPIO_PIN_SHIFT))
+#define NVODM_CAMERA_FLASH_HIGH(_s)    (0x6 << (_s+NVODM_CAMERA_GPIO_PIN_SHIFT))
+// only on VGP0
+#define NVODM_CAMERA_MCLK(_s)          (0x7 << (_s+NVODM_CAMERA_GPIO_PIN_SHIFT))
+// only on VGP6
+#define NVODM_CAMERA_PWM(_s)           (0x7 << (_s+NVODM_CAMERA_GPIO_PIN_SHIFT))
+
+#define NVODM_VGP0_SHIFT            0
+#define NVODM_VD10_SHIFT            (1*NVODM_CAMERA_GPIO_PIN_WIDTH)
+#define NVODM_VD11_SHIFT            (2*NVODM_CAMERA_GPIO_PIN_WIDTH)
+#define NVODM_VGP3_SHIFT            (3*NVODM_CAMERA_GPIO_PIN_WIDTH)
+#define NVODM_VGP4_SHIFT            (4*NVODM_CAMERA_GPIO_PIN_WIDTH)
+#define NVODM_VGP5_SHIFT            (5*NVODM_CAMERA_GPIO_PIN_WIDTH)
+#define NVODM_VGP6_SHIFT            (6*NVODM_CAMERA_GPIO_PIN_WIDTH)
+
+// VGP0
+#define NVODM_CAMERA_VGP0_RESET        NVODM_CAMERA_RESET(NVODM_VGP0_SHIFT)
+#define NVODM_CAMERA_VGP0_RESET_AL     NVODM_CAMERA_RESET_AL(NVODM_VGP0_SHIFT)
+#define NVODM_CAMERA_VGP0_POWERDOWN    NVODM_CAMERA_POWERDOWN(NVODM_VGP0_SHIFT)
+#define NVODM_CAMERA_VGP0_POWERDOWN_AL NVODM_CAMERA_POWERDOWN_AL(NVODM_VGP0_SHIFT)
+#define NVODM_CAMERA_VGP0_FLASH_LOW    NVODM_CAMERA_FLASH_LOW(NVODM_VGP0_SHIFT)
+#define NVODM_CAMERA_VGP0_FLASH_HIGH   NVODM_CAMERA_FLASH_HIGH(NVODM_VGP0_SHIFT)
+#define NVODM_CAMERA_VGP0_MCLK         NVODM_CAMERA_MCLK(NVODM_VGP0_SHIFT)
+// VD10
+#define NVODM_CAMERA_VD10_RESET        NVODM_CAMERA_RESET(NVODM_VD10_SHIFT)
+#define NVODM_CAMERA_VD10_RESET_AL     NVODM_CAMERA_RESET_AL(NVODM_VD10_SHIFT)
+#define NVODM_CAMERA_VD10_POWERDOWN    NVODM_CAMERA_POWERDOWN(NVODM_VD10_SHIFT)
+#define NVODM_CAMERA_VD10_POWERDOWN_AL NVODM_CAMERA_POWERDOWN_AL(NVODM_VD10_SHIFT)
+#define NVODM_CAMERA_VD10_FLASH_LOW    NVODM_CAMERA_FLASH_LOW(NVODM_VD10_SHIFT)
+#define NVODM_CAMERA_VD10_FLASH_HIGH   NVODM_CAMERA_FLASH_HIGH(NVODM_VD10_SHIFT)
+// VD11
+#define NVODM_CAMERA_VD11_RESET        NVODM_CAMERA_RESET(NVODM_VD11_SHIFT)
+#define NVODM_CAMERA_VD11_RESET_AL     NVODM_CAMERA_RESET_AL(NVODM_VD11_SHIFT)
+#define NVODM_CAMERA_VD11_POWERDOWN    NVODM_CAMERA_POWERDOWN(NVODM_VD11_SHIFT)
+#define NVODM_CAMERA_VD11_POWERDOWN_AL NVODM_CAMERA_POWERDOWN_AL(NVODM_VD11_SHIFT)
+#define NVODM_CAMERA_VD11_FLASH_LOW    NVODM_CAMERA_FLASH_LOW(NVODM_VD11_SHIFT)
+#define NVODM_CAMERA_VD11_FLASH_HIGH   NVODM_CAMERA_FLASH_HIGH(NVODM_VD11_SHIFT)
+// VGP3
+#define NVODM_CAMERA_VGP3_RESET        NVODM_CAMERA_RESET(NVODM_VGP3_SHIFT)
+#define NVODM_CAMERA_VGP3_RESET_AL     NVODM_CAMERA_RESET_AL(NVODM_VGP3_SHIFT)
+#define NVODM_CAMERA_VGP3_POWERDOWN    NVODM_CAMERA_POWERDOWN(NVODM_VGP3_SHIFT)
+#define NVODM_CAMERA_VGP3_POWERDOWN_AL NVODM_CAMERA_POWERDOWN_AL(NVODM_VGP3_SHIFT)
+#define NVODM_CAMERA_VGP3_FLASH_LOW    NVODM_CAMERA_FLASH_LOW(NVODM_VGP3_SHIFT)
+#define NVODM_CAMERA_VGP3_FLASH_HIGH   NVODM_CAMERA_FLASH_HIGH(NVODM_VGP3_SHIFT)
+// VGP4
+#define NVODM_CAMERA_VGP4_RESET        NVODM_CAMERA_RESET(NVODM_VGP4_SHIFT)
+#define NVODM_CAMERA_VGP4_RESET_AL     NVODM_CAMERA_RESET_AL(NVODM_VGP4_SHIFT)
+#define NVODM_CAMERA_VGP4_POWERDOWN    NVODM_CAMERA_POWERDOWN(NVODM_VGP4_SHIFT)
+#define NVODM_CAMERA_VGP4_POWERDOWN_AL NVODM_CAMERA_POWERDOWN_AL(NVODM_VGP4_SHIFT)
+#define NVODM_CAMERA_VGP4_FLASH_LOW    NVODM_CAMERA_FLASH_LOW(NVODM_VGP4_SHIFT)
+#define NVODM_CAMERA_VGP4_FLASH_HIGH   NVODM_CAMERA_FLASH_HIGH(NVODM_VGP4_SHIFT)
+// VGP5
+#define NVODM_CAMERA_VGP5_RESET        NVODM_CAMERA_RESET(NVODM_VGP5_SHIFT)
+#define NVODM_CAMERA_VGP5_RESET_AL     NVODM_CAMERA_RESET_AL(NVODM_VGP5_SHIFT)
+#define NVODM_CAMERA_VGP5_POWERDOWN    NVODM_CAMERA_POWERDOWN(NVODM_VGP5_SHIFT)
+#define NVODM_CAMERA_VGP5_POWERDOWN_AL NVODM_CAMERA_POWERDOWN_AL(NVODM_VGP5_SHIFT)
+#define NVODM_CAMERA_VGP5_FLASH_LOW    NVODM_CAMERA_FLASH_LOW(NVODM_VGP5_SHIFT)
+#define NVODM_CAMERA_VGP5_FLASH_HIGH   NVODM_CAMERA_FLASH_HIGH(NVODM_VGP5_SHIFT)
+// VGP6
+#define NVODM_CAMERA_VGP6_RESET        NVODM_CAMERA_RESET(NVODM_VGP6_SHIFT)
+#define NVODM_CAMERA_VGP6_RESET_AL     NVODM_CAMERA_RESET_AL(NVODM_VGP6_SHIFT)
+#define NVODM_CAMERA_VGP6_POWERDOWN    NVODM_CAMERA_POWERDOWN(NVODM_VGP6_SHIFT)
+#define NVODM_CAMERA_VGP6_POWERDOWN_AL NVODM_CAMERA_POWERDOWN_AL(NVODM_VGP6_SHIFT)
+#define NVODM_CAMERA_VGP6_FLASH_LOW    NVODM_CAMERA_FLASH_LOW(NVODM_VGP6_SHIFT)
+#define NVODM_CAMERA_VGP6_FLASH_HIGH   NVODM_CAMERA_FLASH_HIGH(NVODM_VGP6_SHIFT)
+#define NVODM_CAMERA_VGP6_PWM          NVODM_CAMERA_PWM(NVODM_VGP6_SHIFT)
+
+#endif
diff --git a/arch/arm/mach-tegra/odm_kit/query/whistler/nvodm_query.c b/arch/arm/mach-tegra/odm_kit/query/whistler/nvodm_query.c
new file mode 100644
index 000000000000..d17f12b59559
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/query/whistler/nvodm_query.c
@@ -0,0 +1,1490 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/**
+ * @file
+ * <b>NVIDIA APX ODM Kit:
+ *         Implementation of the ODM Query API</b>
+ *
+ * @b Description: Implements the query functions for ODMs that may be
+ *                 accessed at boot-time, runtime, or anywhere in between.
+ */
+
+#include "nvodm_query.h"
+#include "nvodm_query_gpio.h"
+#include "nvodm_query_memc.h"
+#include "nvodm_query_discovery.h"
+#include "nvodm_query_pins.h"
+#include "nvodm_query_pins_ap20.h"
+#include "tegra_devkit_custopt.h"
+#include "nvodm_keylist_reserved.h"
+#include "nvrm_drf.h"
+
+#define BOARD_ID_WHISTLER_E1108 0x0B08
+#define BOARD_ID_WHISTLER_E1109 0x0B09
+#define BOARD_ID_WHISTLER_PMU_E1116 0x0B10
+#define BOARD_ID_WHISTLER_MOTHERBOARD_E1120 0xB14
+#define BOARD_ID_VOYAGER_MAINBOARD_E1215    0xC0F
+#define BOARD_REV_ALL ((NvU8)0xFF)
+
+#define NVODM_ENABLE_EMC_DVFS (1)
+
+// Function to auto-detect boards with external CPU power supply
+NvBool NvOdmIsCpuExtSupply(void);
+
+static const NvU8
+s_NvOdmQueryDeviceNamePrefixValue[] = { 'T','e','g','r','a',0};
+
+static const NvU8
+s_NvOdmQueryManufacturerSetting[] = {'N','V','I','D','I','A',0};
+
+static const NvU8
+s_NvOdmQueryModelSetting[] = {'A','P','2','0',0};
+
+static const NvU8
+s_NvOdmQueryPlatformSetting[] = {'W','h','i','s','t','l','e','r',0};
+
+static const NvU8
+s_NvOdmQueryProjectNameSetting[] = {'O','D','M',' ','K','i','t',0};
+
+static const NvOdmDownloadTransport
+s_NvOdmQueryDownloadTransportSetting = NvOdmDownloadTransport_None;
+
+static NvOdmQuerySdioInterfaceProperty s_NvOdmQuerySdioInterfaceProperty_Whistler[4] =
+{
+    { NV_FALSE, 10, NV_FALSE, 0x6, NvOdmQuerySdioSlotUsage_unused },
+    {  NV_TRUE, 10,  NV_TRUE, 0xF, NvOdmQuerySdioSlotUsage_wlan   },
+    { NV_FALSE, 10, NV_FALSE, 0x4, NvOdmQuerySdioSlotUsage_Media  },
+    {  NV_TRUE, 10,  NV_TRUE, 0x6, NvOdmQuerySdioSlotUsage_Boot   },
+};
+
+static NvOdmQuerySdioInterfaceProperty s_NvOdmQuerySdioInterfaceProperty_Voyager[4] =
+{
+    { NV_FALSE, 10, NV_FALSE, 0x4, NvOdmQuerySdioSlotUsage_unused },
+    {  NV_TRUE, 10,  NV_TRUE, 0x4, NvOdmQuerySdioSlotUsage_wlan   },
+    { NV_FALSE, 10, NV_FALSE, 0x4, NvOdmQuerySdioSlotUsage_Media  },
+    { NV_FALSE, 10, NV_FALSE, 0x4, NvOdmQuerySdioSlotUsage_Boot   },
+};
+
+static const NvOdmQueryOwrDeviceInfo s_NvOdmQueryOwrInfo = {
+    NV_FALSE,
+    0x1, /* Tsu */
+    0xF, /* TRelease */
+    0xF,  /* TRdv */
+    0X3C, /* TLow0 */
+    0x1, /* TLow1 */
+    0x77, /* TSlot */
+
+    0x78, /* TPdl */
+    0x1E, /* TPdh */
+    0x1DF, /* TRstl */
+    0x1DF, /* TRsth */
+
+    0x1E0, /* Tpp */
+    0x5, /* Tfp */
+    0x5, /* Trp */
+    0x5, /* Tdv */
+    0x5, /* Tpd */
+
+    0x7, /* Read data sample clk */
+    0x50, /* Presence sample clk */
+    2,  /* Memory address size */
+    0x80 /* Memory size*/
+};
+
+static const NvOdmSdramControllerConfigAdv s_NvOdmE1109EmcConfigTable[] =
+{
+    {
+                  0x20,   /* Rev 2.0 */
+                166500,   /* SDRAM frquency */
+                  1000,   /* EMC core voltage */
+                    46,   /* Number of EMC parameters below */
+        {
+            0x0000000A,   /* RC */
+            0x00000016,   /* RFC */
+            0x00000008,   /* RAS */
+            0x00000003,   /* RP */
+            0x00000004,   /* R2W */
+            0x00000004,   /* W2R */
+            0x00000002,   /* R2P */
+            0x0000000F,   /* W2P */
+            0x00000003,   /* RD_RCD */
+            0x00000003,   /* WR_RCD */
+            0x00000002,   /* RRD */
+            0x00000001,   /* REXT */
+            0x00000005,   /* WDV */
+            0x00000006,   /* QUSE */
+            0x00000005,   /* QRST */
+            0x00000009,   /* QSAFE */
+            0x0000000E,   /* RDV */
+            0x000004DF,   /* REFRESH */
+            0x00000000,   /* BURST_REFRESH_NUM */
+            0x00000004,   /* PDEX2WR */
+            0x00000004,   /* PDEX2RD */
+            0x00000003,   /* PCHG2PDEN */
+            0x00000003,   /* ACT2PDEN */
+            0x00000001,   /* AR2PDEN */
+            0x0000000B,   /* RW2PDEN */
+            0x000000C8,   /* TXSR */
+            0x00000003,   /* TCKE */
+            0x00000008,   /* TFAW */
+            0x00000004,   /* TRPAB */
+            0x0000000B,   /* TCLKSTABLE */
+            0x00000002,   /* TCLKSTOP */
+            0x00000000,   /* TREFBW */
+            0x00000000,   /* QUSE_EXTRA */
+            0x00000002,   /* FBIO_CFG6 */
+            0x00000000,   /* ODT_WRITE */
+            0x00000000,   /* ODT_READ */
+            0x00000083,   /* FBIO_CFG5 */
+            0x00400006,   /* CFG_DIG_DLL */
+            0x007FD010,   /* DLL_XFORM_DQS */
+            0x00001010,   /* DLL_XFORM_QUSE */
+            0x00000000,   /* ZCAL_REF_CNT */
+            0x00000000,   /* ZCAL_WAIT_CNT */
+            0x00000000,   /* AUTO_CAL_INTERVAL */
+            0x00000000,   /* CFG_CLKTRIM_0 */
+            0x00000000,   /* CFG_CLKTRIM_1 */
+            0x00000000,   /* CFG_CLKTRIM_2 */
+        }
+    },
+    {
+                  0x20,   /* Rev 2.0 */
+                333000,   /* SDRAM frquency */
+                  1200,   /* EMC core voltage */
+                    46,   /* Number of EMC parameters below */
+        {
+            0x00000014,   /* RC */
+            0x0000002B,   /* RFC */
+            0x0000000F,   /* RAS */
+            0x00000005,   /* RP */
+            0x00000004,   /* R2W */
+            0x00000005,   /* W2R */
+            0x00000003,   /* R2P */
+            0x0000000F,   /* W2P */
+            0x00000005,   /* RD_RCD */
+            0x00000005,   /* WR_RCD */
+            0x00000004,   /* RRD */
+            0x00000001,   /* REXT */
+            0x00000005,   /* WDV */
+            0x00000006,   /* QUSE */
+            0x00000005,   /* QRST */
+            0x00000009,   /* QSAFE */
+            0x0000000E,   /* RDV */
+            0x000009FF,   /* REFRESH */
+            0x00000000,   /* BURST_REFRESH_NUM */
+            0x00000004,   /* PDEX2WR */
+            0x00000004,   /* PDEX2RD */
+            0x00000005,   /* PCHG2PDEN */
+            0x00000005,   /* ACT2PDEN */
+            0x00000001,   /* AR2PDEN */
+            0x00000010,   /* RW2PDEN */
+            0x000000C8,   /* TXSR */
+            0x00000003,   /* TCKE */
+            0x0000000F,   /* TFAW */
+            0x00000006,   /* TRPAB */
+            0x0000000B,   /* TCLKSTABLE */
+            0x00000002,   /* TCLKSTOP */
+            0x00000000,   /* TREFBW */
+            0x00000000,   /* QUSE_EXTRA */
+            0x00000002,   /* FBIO_CFG6 */
+            0x00000000,   /* ODT_WRITE */
+            0x00000000,   /* ODT_READ */
+            0x00000083,   /* FBIO_CFG5 */
+            0x002C0006,   /* CFG_DIG_DLL */
+            0x007FD010,   /* DLL_XFORM_DQS */
+            0x00001010,   /* DLL_XFORM_QUSE */
+            0x00000000,   /* ZCAL_REF_CNT */
+            0x00000000,   /* ZCAL_WAIT_CNT */
+            0x00000000,   /* AUTO_CAL_INTERVAL */
+            0x00000000,   /* CFG_CLKTRIM_0 */
+            0x00000000,   /* CFG_CLKTRIM_1 */
+            0x00000000,   /* CFG_CLKTRIM_2 */
+        }
+    }
+};
+
+static const NvOdmSdramControllerConfigAdv s_NvOdmE1108HynixEmcConfigTable[] =
+{
+    {
+                  0x20,   /* Rev 2.0 */
+                 18000,   /* SDRAM frquency */
+                   950,   /* EMC core voltage */
+                    46,   /* Number of EMC parameters below */
+        {
+            0x00000002,   /* RC */
+            0x00000006,   /* RFC */
+            0x00000003,   /* RAS */
+            0x00000003,   /* RP */
+            0x00000006,   /* R2W */
+            0x00000004,   /* W2R */
+            0x00000002,   /* R2P */
+            0x0000000B,   /* W2P */
+            0x00000003,   /* RD_RCD */
+            0x00000003,   /* WR_RCD */
+            0x00000002,   /* RRD */
+            0x00000002,   /* REXT */
+            0x00000003,   /* WDV */
+            0x00000005,   /* QUSE */
+            0x00000004,   /* QRST */
+            0x00000008,   /* QSAFE */
+            0x0000000C,   /* RDV */
+            0x00000070,   /* REFRESH */
+            0x00000000,   /* BURST_REFRESH_NUM */
+            0x00000003,   /* PDEX2WR */
+            0x00000003,   /* PDEX2RD */
+            0x00000003,   /* PCHG2PDEN */
+            0x00000003,   /* ACT2PDEN */
+            0x00000001,   /* AR2PDEN */
+            0x0000000B,   /* RW2PDEN */
+            0x00000003,   /* TXSR */
+            0x00000003,   /* TCKE */
+            0x00000008,   /* TFAW */
+            0x00000004,   /* TRPAB */
+            0x00000008,   /* TCLKSTABLE */
+            0x00000002,   /* TCLKSTOP */
+            0x0000004B,   /* TREFBW */
+            0x00000000,   /* QUSE_EXTRA */
+            0x00000003,   /* FBIO_CFG6 */
+            0x00000000,   /* ODT_WRITE */
+            0x00000000,   /* ODT_READ */
+            0x00000082,   /* FBIO_CFG5 */
+            0x00780006,   /* CFG_DIG_DLL */
+            0x00000010,   /* DLL_XFORM_DQS */
+            0x00000008,   /* DLL_XFORM_QUSE */
+            0x00000000,   /* ZCAL_REF_CNT */
+            0x00000002,   /* ZCAL_WAIT_CNT */
+            0x00000000,   /* AUTO_CAL_INTERVAL */
+            0x00000000,   /* CFG_CLKTRIM_0 */
+            0x00000000,   /* CFG_CLKTRIM_1 */
+            0x00000000,   /* CFG_CLKTRIM_2 */
+        }
+    },
+    {
+                  0x20,   /* Rev 2.0 */
+                 27000,   /* SDRAM frquency */
+                   950,   /* EMC core voltage */
+                    46,   /* Number of EMC parameters below */
+        {
+            0x00000002,   /* RC */
+            0x00000006,   /* RFC */
+            0x00000003,   /* RAS */
+            0x00000003,   /* RP */
+            0x00000006,   /* R2W */
+            0x00000004,   /* W2R */
+            0x00000002,   /* R2P */
+            0x0000000B,   /* W2P */
+            0x00000003,   /* RD_RCD */
+            0x00000003,   /* WR_RCD */
+            0x00000002,   /* RRD */
+            0x00000002,   /* REXT */
+            0x00000003,   /* WDV */
+            0x00000005,   /* QUSE */
+            0x00000004,   /* QRST */
+            0x00000008,   /* QSAFE */
+            0x0000000C,   /* RDV */
+            0x000000A8,   /* REFRESH */
+            0x00000000,   /* BURST_REFRESH_NUM */
+            0x00000003,   /* PDEX2WR */
+            0x00000003,   /* PDEX2RD */
+            0x00000003,   /* PCHG2PDEN */
+            0x00000003,   /* ACT2PDEN */
+            0x00000001,   /* AR2PDEN */
+            0x0000000B,   /* RW2PDEN */
+            0x00000004,   /* TXSR */
+            0x00000003,   /* TCKE */
+            0x00000008,   /* TFAW */
+            0x00000004,   /* TRPAB */
+            0x00000008,   /* TCLKSTABLE */
+            0x00000002,   /* TCLKSTOP */
+            0x00000071,   /* TREFBW */
+            0x00000000,   /* QUSE_EXTRA */
+            0x00000003,   /* FBIO_CFG6 */
+            0x00000000,   /* ODT_WRITE */
+            0x00000000,   /* ODT_READ */
+            0x00000082,   /* FBIO_CFG5 */
+            0x00780006,   /* CFG_DIG_DLL */
+            0x00000010,   /* DLL_XFORM_DQS */
+            0x00000008,   /* DLL_XFORM_QUSE */
+            0x00000000,   /* ZCAL_REF_CNT */
+            0x00000003,   /* ZCAL_WAIT_CNT */
+            0x00000000,   /* AUTO_CAL_INTERVAL */
+            0x00000000,   /* CFG_CLKTRIM_0 */
+            0x00000000,   /* CFG_CLKTRIM_1 */
+            0x00000000,   /* CFG_CLKTRIM_2 */
+        }
+    },
+    {
+                  0x20,   /* Rev 2.0 */
+                 54000,   /* SDRAM frquency */
+                  1000,   /* EMC core voltage */
+                    46,   /* Number of EMC parameters below */
+        {
+            0x00000004,   /* RC */
+            0x00000008,   /* RFC */
+            0x00000003,   /* RAS */
+            0x00000003,   /* RP */
+            0x00000006,   /* R2W */
+            0x00000004,   /* W2R */
+            0x00000002,   /* R2P */
+            0x0000000B,   /* W2P */
+            0x00000003,   /* RD_RCD */
+            0x00000003,   /* WR_RCD */
+            0x00000002,   /* RRD */
+            0x00000002,   /* REXT */
+            0x00000003,   /* WDV */
+            0x00000006,   /* QUSE */
+            0x00000004,   /* QRST */
+            0x00000008,   /* QSAFE */
+            0x0000000C,   /* RDV */
+            0x0000017F,   /* REFRESH */
+            0x00000000,   /* BURST_REFRESH_NUM */
+            0x00000003,   /* PDEX2WR */
+            0x00000003,   /* PDEX2RD */
+            0x00000003,   /* PCHG2PDEN */
+            0x00000003,   /* ACT2PDEN */
+            0x00000001,   /* AR2PDEN */
+            0x0000000B,   /* RW2PDEN */
+            0x00000008,   /* TXSR */
+            0x00000003,   /* TCKE */
+            0x00000008,   /* TFAW */
+            0x00000004,   /* TRPAB */
+            0x00000008,   /* TCLKSTABLE */
+            0x00000002,   /* TCLKSTOP */
+            0x000000E1,   /* TREFBW */
+            0x00000000,   /* QUSE_EXTRA */
+            0x00000000,   /* FBIO_CFG6 */
+            0x00000000,   /* ODT_WRITE */
+            0x00000000,   /* ODT_READ */
+            0x00000082,   /* FBIO_CFG5 */
+            0x00780006,   /* CFG_DIG_DLL */
+            0x00000010,   /* DLL_XFORM_DQS */
+            0x00000008,   /* DLL_XFORM_QUSE */
+            0x00000000,   /* ZCAL_REF_CNT */
+            0x00000005,   /* ZCAL_WAIT_CNT */
+            0x00000000,   /* AUTO_CAL_INTERVAL */
+            0x00000000,   /* CFG_CLKTRIM_0 */
+            0x00000000,   /* CFG_CLKTRIM_1 */
+            0x00000000,   /* CFG_CLKTRIM_2 */
+        }
+    },
+    {
+                  0x20,   /* Rev 2.0 */
+                108000,   /* SDRAM frquency */
+                  1000,   /* EMC core voltage */
+                    46,   /* Number of EMC parameters below */
+        {
+            0x00000007,   /* RC */
+            0x0000000F,   /* RFC */
+            0x00000005,   /* RAS */
+            0x00000003,   /* RP */
+            0x00000006,   /* R2W */
+            0x00000004,   /* W2R */
+            0x00000002,   /* R2P */
+            0x0000000B,   /* W2P */
+            0x00000003,   /* RD_RCD */
+            0x00000003,   /* WR_RCD */
+            0x00000002,   /* RRD */
+            0x00000002,   /* REXT */
+            0x00000003,   /* WDV */
+            0x00000006,   /* QUSE */
+            0x00000004,   /* QRST */
+            0x00000008,   /* QSAFE */
+            0x0000000C,   /* RDV */
+            0x0000031F,   /* REFRESH */
+            0x00000000,   /* BURST_REFRESH_NUM */
+            0x00000003,   /* PDEX2WR */
+            0x00000003,   /* PDEX2RD */
+            0x00000003,   /* PCHG2PDEN */
+            0x00000003,   /* ACT2PDEN */
+            0x00000001,   /* AR2PDEN */
+            0x0000000B,   /* RW2PDEN */
+            0x00000010,   /* TXSR */
+            0x00000003,   /* TCKE */
+            0x00000008,   /* TFAW */
+            0x00000004,   /* TRPAB */
+            0x00000008,   /* TCLKSTABLE */
+            0x00000002,   /* TCLKSTOP */
+            0x000001C2,   /* TREFBW */
+            0x00000000,   /* QUSE_EXTRA */
+            0x00000000,   /* FBIO_CFG6 */
+            0x00000000,   /* ODT_WRITE */
+            0x00000000,   /* ODT_READ */
+            0x00000082,   /* FBIO_CFG5 */
+            0xD0780323,   /* CFG_DIG_DLL */
+            0x007FD010,   /* DLL_XFORM_DQS */
+            0x00000010,   /* DLL_XFORM_QUSE */
+            0x00000000,   /* ZCAL_REF_CNT */
+            0x0000000A,   /* ZCAL_WAIT_CNT */
+            0x00000000,   /* AUTO_CAL_INTERVAL */
+            0x00000000,   /* CFG_CLKTRIM_0 */
+            0x00000000,   /* CFG_CLKTRIM_1 */
+            0x00000000,   /* CFG_CLKTRIM_2 */
+        }
+    },
+    {
+                  0x20,   /* Rev 2.0 */
+                150000,   /* SDRAM frquency */
+                  1000,   /* EMC core voltage */
+                    46,   /* Number of EMC parameters below */
+        {
+            0x00000009,   /* RC */
+            0x00000014,   /* RFC */
+            0x00000007,   /* RAS */
+            0x00000003,   /* RP */
+            0x00000006,   /* R2W */
+            0x00000004,   /* W2R */
+            0x00000002,   /* R2P */
+            0x0000000B,   /* W2P */
+            0x00000003,   /* RD_RCD */
+            0x00000003,   /* WR_RCD */
+            0x00000002,   /* RRD */
+            0x00000002,   /* REXT */
+            0x00000003,   /* WDV */
+            0x00000006,   /* QUSE */
+            0x00000004,   /* QRST */
+            0x00000008,   /* QSAFE */
+            0x0000000C,   /* RDV */
+            0x0000045F,   /* REFRESH */
+            0x00000000,   /* BURST_REFRESH_NUM */
+            0x00000003,   /* PDEX2WR */
+            0x00000003,   /* PDEX2RD */
+            0x00000003,   /* PCHG2PDEN */
+            0x00000003,   /* ACT2PDEN */
+            0x00000001,   /* AR2PDEN */
+            0x0000000B,   /* RW2PDEN */
+            0x00000015,   /* TXSR */
+            0x00000003,   /* TCKE */
+            0x00000008,   /* TFAW */
+            0x00000004,   /* TRPAB */
+            0x00000008,   /* TCLKSTABLE */
+            0x00000002,   /* TCLKSTOP */
+            0x00000270,   /* TREFBW */
+            0x00000000,   /* QUSE_EXTRA */
+            0x00000001,   /* FBIO_CFG6 */
+            0x00000000,   /* ODT_WRITE */
+            0x00000000,   /* ODT_READ */
+            0x00000082,   /* FBIO_CFG5 */
+            0xD05E0323,   /* CFG_DIG_DLL */
+            0x007FD010,   /* DLL_XFORM_DQS */
+            0x00000010,   /* DLL_XFORM_QUSE */
+            0x00000000,   /* ZCAL_REF_CNT */
+            0x0000000E,   /* ZCAL_WAIT_CNT */
+            0x00000000,   /* AUTO_CAL_INTERVAL */
+            0x00000000,   /* CFG_CLKTRIM_0 */
+            0x00000000,   /* CFG_CLKTRIM_1 */
+            0x00000000,   /* CFG_CLKTRIM_2 */
+        }
+    },
+    {
+                  0x20,   /* Rev 2.0 */
+                300000,   /* SDRAM frquency */
+                  1100,   /* EMC core voltage */
+                    46,   /* Number of EMC parameters below */
+        {
+            0x00000012,   /* RC */
+            0x00000027,   /* RFC */
+            0x0000000D,   /* RAS */
+            0x00000006,   /* RP */
+            0x00000007,   /* R2W */
+            0x00000005,   /* W2R */
+            0x00000003,   /* R2P */
+            0x0000000B,   /* W2P */
+            0x00000006,   /* RD_RCD */
+            0x00000006,   /* WR_RCD */
+            0x00000003,   /* RRD */
+            0x00000003,   /* REXT */
+            0x00000003,   /* WDV */
+            0x00000006,   /* QUSE */
+            0x00000004,   /* QRST */
+            0x00000009,   /* QSAFE */
+            0x0000000D,   /* RDV */
+            0x000008FF,   /* REFRESH */
+            0x00000000,   /* BURST_REFRESH_NUM */
+            0x00000004,   /* PDEX2WR */
+            0x00000004,   /* PDEX2RD */
+            0x00000006,   /* PCHG2PDEN */
+            0x00000006,   /* ACT2PDEN */
+            0x00000001,   /* AR2PDEN */
+            0x0000000F,   /* RW2PDEN */
+            0x0000002A,   /* TXSR */
+            0x00000003,   /* TCKE */
+            0x0000000F,   /* TFAW */
+            0x00000007,   /* TRPAB */
+            0x00000007,   /* TCLKSTABLE */
+            0x00000002,   /* TCLKSTOP */
+            0x000004E0,   /* TREFBW */
+            0x00000000,   /* QUSE_EXTRA */
+            0x00000002,   /* FBIO_CFG6 */
+            0x00000000,   /* ODT_WRITE */
+            0x00000000,   /* ODT_READ */
+            0x00000282,   /* FBIO_CFG5 */
+            0xE03A0303,   /* CFG_DIG_DLL */
+            0x007FD010,   /* DLL_XFORM_DQS */
+            0x00000010,   /* DLL_XFORM_QUSE */
+            0x00000000,   /* ZCAL_REF_CNT */
+            0x0000001B,   /* ZCAL_WAIT_CNT */
+            0x00000000,   /* AUTO_CAL_INTERVAL */
+            0x00000000,   /* CFG_CLKTRIM_0 */
+            0x00000000,   /* CFG_CLKTRIM_1 */
+            0x00000000,   /* CFG_CLKTRIM_2 */
+        }
+    }
+};
+
+
+// Wake Events
+static NvOdmWakeupPadInfo s_NvOdmWakeupPadInfo[] =
+{
+    {NV_FALSE,  0, NvOdmWakeupPadPolarity_Low},     // Wake Event  0 - ulpi_data4 (UART_RI)
+    {NV_FALSE,  1, NvOdmWakeupPadPolarity_High},    // Wake Event  1 - gp3_pv[3] (BB_MOD, MODEM_RESET_OUT)
+    {NV_FALSE,  2, NvOdmWakeupPadPolarity_High},    // Wake Event  2 - dvi_d3
+    {NV_FALSE,  3, NvOdmWakeupPadPolarity_Low},     // Wake Event  3 - sdio3_dat1
+    {NV_FALSE,  4, NvOdmWakeupPadPolarity_High},    // Wake Event  4 - hdmi_int (HDMI_HPD)
+    {NV_FALSE,  5, NvOdmWakeupPadPolarity_High},    // Wake Event  5 - vgp[6] (VI_GP6, Flash_EN2)
+    {NV_FALSE,  6, NvOdmWakeupPadPolarity_High},    // Wake Event  6 - gp3_pu[5] (GPS_ON_OFF, GPS_IRQ)
+    {NV_FALSE,  7, NvOdmWakeupPadPolarity_AnyEdge}, // Wake Event  7 - gp3_pu[6] (GPS_INT, BT_IRQ)
+    {NV_FALSE,  8, NvOdmWakeupPadPolarity_AnyEdge}, // Wake Event  8 - gmi_wp_n (MICRO SD_CD)
+    {NV_FALSE,  9, NvOdmWakeupPadPolarity_High},    // Wake Event  9 - gp3_ps[2] (KB_COL10)
+    {NV_FALSE, 10, NvOdmWakeupPadPolarity_High},    // Wake Event 10 - gmi_ad21 (Accelerometer_TH/TAP)
+    {NV_FALSE, 11, NvOdmWakeupPadPolarity_Low},     // Wake Event 11 - spi2_cs2 (PEN_INT, AUDIO-IRQ)
+    {NV_FALSE, 12, NvOdmWakeupPadPolarity_Low},     // Wake Event 12 - spi2_cs1 (HEADSET_DET, not used)
+    {NV_FALSE, 13, NvOdmWakeupPadPolarity_Low},     // Wake Event 13 - sdio1_dat1
+    {NV_FALSE, 14, NvOdmWakeupPadPolarity_AnyEdge}, // Wake Event 14 - gp3_pv[6] (WLAN_INT)
+    {NV_FALSE, 15, NvOdmWakeupPadPolarity_AnyEdge}, // Wake Event 15 - gmi_ad16  (SPI3_DOUT, DTV_SPI4_CS1)
+    {NV_FALSE, 16, NvOdmWakeupPadPolarity_High},    // Wake Event 16 - rtc_irq
+    {NV_TRUE,  17, NvOdmWakeupPadPolarity_High},    // Wake Event 17 - kbc_interrupt
+    {NV_FALSE, 18, NvOdmWakeupPadPolarity_Low},     // Wake Event 18 - pwr_int (PMIC_INT)
+    {NV_FALSE, 19, NvOdmWakeupPadPolarity_AnyEdge}, // Wake Event 19 - usb_vbus_wakeup[0]
+    {NV_FALSE, 20, NvOdmWakeupPadPolarity_High},    // Wake Event 20 - usb_vbus_wakeup[1]
+    {NV_FALSE, 21, NvOdmWakeupPadPolarity_Low},     // Wake Event 21 - usb_iddig[0]
+    {NV_FALSE, 22, NvOdmWakeupPadPolarity_Low},     // Wake Event 22 - usb_iddig[1]
+    {NV_FALSE, 23, NvOdmWakeupPadPolarity_AnyEdge}, // Wake Event 23 - gmi_iordy (HSMMC_CLK)
+    {NV_FALSE, 24, NvOdmWakeupPadPolarity_High},    // Wake Event 24 - gp3_pv[2] (BB_MOD, MODEM WAKEUP_AP15, SPI-SS)
+    {NV_FALSE, 25, NvOdmWakeupPadPolarity_High},    // Wake Event 25 - gp3_ps[4] (KB_COL12)
+    {NV_FALSE, 26, NvOdmWakeupPadPolarity_High},    // Wake Event 26 - gp3_ps[5] (KB_COL10)
+    {NV_FALSE, 27, NvOdmWakeupPadPolarity_High},    // Wake Event 27 - gp3_ps[0] (KB_COL8)
+    {NV_FALSE, 28, NvOdmWakeupPadPolarity_Low},     // Wake Event 28 - gp3_pq[6] (KB_ROW6)
+    {NV_FALSE, 29, NvOdmWakeupPadPolarity_Low},     // Wake Event 29 - gp3_pq[7] (KB_ROW6)
+    {NV_FALSE, 30, NvOdmWakeupPadPolarity_High}     // Wake Event 30 - dap1_dout (DAP1_DOUT)
+};
+
+/* --- Function Implementations ---*/
+
+static NvBool
+NvOdmIsBoardPresent(
+    const NvOdmBoardInfo* pBoardList,
+    NvU32 ListSize)
+{
+    NvU32 i;
+    NvOdmBoardInfo BoardInfo;
+
+    // Scan for presence of any board in the list
+    // ID/SKU/FAB fields must match, revision may be masked
+    if (pBoardList)
+    {
+        for (i=0; i < ListSize; i++)
+        {
+            if (NvOdmPeripheralGetBoardInfo(
+                pBoardList[i].BoardID, &BoardInfo))
+            {
+                if ((pBoardList[i].Fab == BoardInfo.Fab) &&
+                    (pBoardList[i].SKU == BoardInfo.SKU) &&
+                    ((pBoardList[i].Revision == BOARD_REV_ALL) ||
+                     (pBoardList[i].Revision == BoardInfo.Revision)) &&
+                    ((pBoardList[i].MinorRevision == BOARD_REV_ALL) ||
+                     (pBoardList[i].MinorRevision == BoardInfo.MinorRevision)))
+                {
+                    return NV_TRUE; // Board found
+                }
+            }
+        }
+    }
+    return NV_FALSE;
+}
+
+#if NVODM_ENABLE_EMC_DVFS
+static NvBool NvOdmIsE1108Hynix(void)
+{
+    // A list of Whistler E1108 processor boards with Hynix LPDDR2
+    // charcterized by s_NvOdmE1108HynixEmcConfigTable (fill in
+    // ID/SKU/FAB fields, revision fields are ignored)
+    static const NvOdmBoardInfo s_WhistlerE1108Hynix[] =
+    {
+        // ID                      SKU     FAB   Rev            Minor Rev  
+        { BOARD_ID_WHISTLER_E1108, 0x0A14, 0x01, BOARD_REV_ALL, BOARD_REV_ALL},
+        { BOARD_ID_WHISTLER_E1108, 0x0A1E, 0x01, BOARD_REV_ALL, BOARD_REV_ALL},
+        { BOARD_ID_WHISTLER_E1108, 0x0A00, 0x02, BOARD_REV_ALL, BOARD_REV_ALL},
+        { BOARD_ID_WHISTLER_E1108, 0x0A0A, 0x02, BOARD_REV_ALL, BOARD_REV_ALL}
+    };
+    return NvOdmIsBoardPresent(s_WhistlerE1108Hynix,
+                               NV_ARRAY_SIZE(s_WhistlerE1108Hynix));
+}
+#endif
+
+static NvBool NvOdmIsCpuRailPreserved(void)
+{
+    // A list of Whistler PMU boards that preserves CPU voltage across LP2/LP1
+    static const NvOdmBoardInfo s_WhistlerCpuPreservedBoards[] =
+    {
+        // ID                          SKU     FAB   Rev            Minor Rev
+        { BOARD_ID_WHISTLER_PMU_E1116, 0x0A0A, 0x01, BOARD_REV_ALL, BOARD_REV_ALL},
+    };
+    return NvOdmIsBoardPresent(s_WhistlerCpuPreservedBoards,
+                               NV_ARRAY_SIZE(s_WhistlerCpuPreservedBoards));
+}
+
+NvBool NvOdmIsCpuExtSupply(void)
+{
+    // A list of Whistler processor boards that use external DCDC as CPU
+    // power supply (fill in ID/SKU/FAB fields, revision fields are ignored)
+    static const NvOdmBoardInfo s_WhistlerCpuExtSupplyBoards[] =
+    {
+        // ID                      SKU     FAB   Rev            Minor Rev  
+        { BOARD_ID_WHISTLER_E1108, 0x0A14, 0x01, BOARD_REV_ALL, BOARD_REV_ALL},
+        { BOARD_ID_WHISTLER_E1108, 0x0A00, 0x02, BOARD_REV_ALL, BOARD_REV_ALL}
+    };
+    return NvOdmIsBoardPresent(s_WhistlerCpuExtSupplyBoards,
+                               NV_ARRAY_SIZE(s_WhistlerCpuExtSupplyBoards));
+}
+
+static NvU32
+GetBctKeyValue(void)
+{
+    NvOdmServicesKeyListHandle hKeyList = NULL;
+    NvU32 BctCustOpt = 0;
+
+    hKeyList = NvOdmServicesKeyListOpen();
+    if (hKeyList)
+    {
+        BctCustOpt =
+            NvOdmServicesGetKeyValue(hKeyList,
+                                     NvOdmKeyListId_ReservedBctCustomerOption);
+        NvOdmServicesKeyListClose(hKeyList);
+    }
+
+    return BctCustOpt;
+}
+
+NvOdmDebugConsole
+NvOdmQueryDebugConsole(void)
+{
+    NvU32 CustOpt = GetBctKeyValue();
+    switch (NV_DRF_VAL(TEGRA_DEVKIT, BCT_CUSTOPT, CONSOLE, CustOpt))
+    {
+    case TEGRA_DEVKIT_BCT_CUSTOPT_0_CONSOLE_DEFAULT:
+    case TEGRA_DEVKIT_BCT_CUSTOPT_0_CONSOLE_DCC:
+        return NvOdmDebugConsole_Dcc;
+    case TEGRA_DEVKIT_BCT_CUSTOPT_0_CONSOLE_NONE:
+        return NvOdmDebugConsole_None;
+    case TEGRA_DEVKIT_BCT_CUSTOPT_0_CONSOLE_UART:
+        return NvOdmDebugConsole_UartA +
+            NV_DRF_VAL(TEGRA_DEVKIT, BCT_CUSTOPT, CONSOLE_OPTION, CustOpt);
+    default:
+        return NvOdmDebugConsole_None;
+    }
+}
+
+NvOdmDownloadTransport
+NvOdmQueryDownloadTransport(void)
+{
+    NvU32 CustOpt = GetBctKeyValue();
+
+    switch (NV_DRF_VAL(TEGRA_DEVKIT, BCT_CUSTOPT, TRANSPORT, CustOpt))
+    {
+    case TEGRA_DEVKIT_BCT_CUSTOPT_0_TRANSPORT_NONE:
+        return NvOdmDownloadTransport_None;
+    case TEGRA_DEVKIT_BCT_CUSTOPT_0_TRANSPORT_USB:
+        return NvOdmDownloadTransport_Usb;
+    case TEGRA_DEVKIT_BCT_CUSTOPT_0_TRANSPORT_ETHERNET:
+        switch (NV_DRF_VAL(TEGRA_DEVKIT, BCT_CUSTOPT, ETHERNET_OPTION, CustOpt))
+        {
+        case TEGRA_DEVKIT_BCT_CUSTOPT_0_ETHERNET_OPTION_SPI:
+        case TEGRA_DEVKIT_BCT_CUSTOPT_0_ETHERNET_OPTION_DEFAULT:
+        default:
+            return NvOdmDownloadTransport_SpiEthernet;
+        }
+    case TEGRA_DEVKIT_BCT_CUSTOPT_0_TRANSPORT_UART:
+        switch (NV_DRF_VAL(TEGRA_DEVKIT, BCT_CUSTOPT, UART_OPTION, CustOpt))
+        {
+        case TEGRA_DEVKIT_BCT_CUSTOPT_0_UART_OPTION_B:
+            return NvOdmDownloadTransport_UartB;
+        case TEGRA_DEVKIT_BCT_CUSTOPT_0_UART_OPTION_C:
+            return NvOdmDownloadTransport_UartC;
+        case TEGRA_DEVKIT_BCT_CUSTOPT_0_UART_OPTION_DEFAULT:
+        case TEGRA_DEVKIT_BCT_CUSTOPT_0_UART_OPTION_A:
+        default:
+            return NvOdmDownloadTransport_UartA;
+        }
+    case TEGRA_DEVKIT_BCT_CUSTOPT_0_TRANSPORT_DEFAULT:
+    default:
+        return s_NvOdmQueryDownloadTransportSetting;
+    }
+}
+
+const NvU8*
+NvOdmQueryDeviceNamePrefix(void)
+{
+    return s_NvOdmQueryDeviceNamePrefixValue;
+}
+
+static const NvOdmQuerySpdifInterfaceProperty s_NvOdmQuerySpdifInterfacePropertySetting =
+{
+    NvOdmQuerySpdifDataCaptureControl_FromLeft
+};
+
+const NvOdmQuerySpiDeviceInfo *
+
+NvOdmQuerySpiGetDeviceInfo(
+    NvOdmIoModule OdmIoModule,
+    NvU32 ControllerId,
+    NvU32 ChipSelect)
+{
+    static const NvOdmQuerySpiDeviceInfo s_Spi1Cs0Info_EmpRil =
+        {NvOdmQuerySpiSignalMode_0, NV_TRUE, NV_TRUE};
+
+    static const NvOdmQuerySpiDeviceInfo s_Spi1Cs0Info_IfxRil =
+        {NvOdmQuerySpiSignalMode_1, NV_TRUE, NV_FALSE};
+
+    static const NvOdmQuerySpiDeviceInfo s_Spi1Cs0Info =
+        {NvOdmQuerySpiSignalMode_0, NV_TRUE, NV_FALSE};
+
+    static const NvOdmQuerySpiDeviceInfo s_Spi2Cs1Info =
+        {NvOdmQuerySpiSignalMode_0, NV_TRUE, NV_FALSE};
+
+    static const NvOdmQuerySpiDeviceInfo s_Spi3Cs1Info =
+        {NvOdmQuerySpiSignalMode_0, NV_TRUE, NV_FALSE};
+
+    NvU32 CustOpt = GetBctKeyValue();
+    switch (NV_DRF_VAL(TEGRA_DEVKIT, BCT_CUSTOPT, RIL, CustOpt))
+    {
+    case TEGRA_DEVKIT_BCT_CUSTOPT_0_RIL_EMP_RAINBOW:
+        if ((OdmIoModule == NvOdmIoModule_Spi) &&
+            (ControllerId == 0 ) && (ChipSelect == 0))
+            return &s_Spi1Cs0Info_EmpRil;
+        break;
+    case TEGRA_DEVKIT_BCT_CUSTOPT_0_RIL_IFX:
+        if ((OdmIoModule == NvOdmIoModule_Spi) &&
+            (ControllerId == 0 ) && (ChipSelect == 0))
+            return &s_Spi1Cs0Info_IfxRil;
+        break;
+    }
+
+    if ((OdmIoModule == NvOdmIoModule_Spi) &&
+        (ControllerId == 1 || ControllerId == 0) && (ChipSelect == 0))
+        return &s_Spi1Cs0Info;
+
+    if ((OdmIoModule == NvOdmIoModule_Spi) &&
+        (ControllerId == 1 ) && ((ChipSelect == 1)|| (ChipSelect == 3)))
+        return &s_Spi2Cs1Info;
+
+    if ((OdmIoModule == NvOdmIoModule_Spi) &&
+        (ControllerId == 2 ) && (ChipSelect == 1))
+        return &s_Spi3Cs1Info;
+
+    if ((OdmIoModule == NvOdmIoModule_Spi) &&
+        (ControllerId == 2 ) && (ChipSelect == 2))
+        return &s_Spi3Cs1Info;
+
+    return NULL;
+}
+
+
+const NvOdmQuerySpiIdleSignalState *
+NvOdmQuerySpiGetIdleSignalState(
+    NvOdmIoModule OdmIoModule,
+    NvU32 ControllerId)
+{
+    return NULL;
+}
+
+const NvOdmQueryI2sInterfaceProperty *
+NvOdmQueryI2sGetInterfaceProperty(
+    NvU32 I2sInstanceId)
+{
+    static const NvOdmQueryI2sInterfaceProperty s_Property =
+    {
+        NvOdmQueryI2sMode_Slave,
+        NvOdmQueryI2sLRLineControl_LeftOnLow,
+        NvOdmQueryI2sDataCommFormat_I2S,
+        NV_FALSE,
+        0
+    };
+
+    if ((!I2sInstanceId) || (I2sInstanceId == 1))
+        return &s_Property;
+
+    return NULL;
+}
+
+const NvOdmQueryDapPortProperty *
+NvOdmQueryDapPortGetProperty(
+    NvU32 DapPortId)
+{
+    static const NvOdmQueryDapPortProperty s_Property[] =
+    {
+        { NvOdmDapPort_None, NvOdmDapPort_None, { 0, 0, 0, 0 } },
+        // I2S1 (DAC1) <-> DAP1 <-> HIFICODEC
+        { NvOdmDapPort_I2s1, NvOdmDapPort_HifiCodecType,
+          { 2, 16, 44100, NvOdmQueryI2sDataCommFormat_I2S } }, // Dap1
+          // I2S2 (DAC2) <-> DAP2 <-> VOICECODEC
+        {NvOdmDapPort_I2s2, NvOdmDapPort_VoiceCodecType,
+          {2, 16, 8000, NvOdmQueryI2sDataCommFormat_I2S } },   // Dap2
+    };
+    static const NvOdmQueryDapPortProperty s_Property_Ril_Emp_Rainbow[] =
+    {
+        { NvOdmDapPort_None, NvOdmDapPort_None, { 0, 0, 0, 0 } },
+        // I2S1 (DAC1) <-> DAP1 <-> HIFICODEC
+        { NvOdmDapPort_I2s1, NvOdmDapPort_HifiCodecType,
+          { 2, 16, 44100, NvOdmQueryI2sDataCommFormat_I2S } }, // Dap1
+        // I2S2 (DAC2) <-> DAP2 <-> VOICECODEC
+        {NvOdmDapPort_I2s2, NvOdmDapPort_VoiceCodecType,
+          {2, 16, 8000, NvOdmQueryI2sDataCommFormat_I2S } },   // Dap2
+        // I2S2 (DAC2) <-> DAP3 <-> BASEBAND
+        {NvOdmDapPort_I2s2, NvOdmDapPort_BaseBand,
+          {2, 16, 8000, NvOdmQueryI2sDataCommFormat_I2S } },   // Dap3
+        // I2S2 (DAC2) <-> DAP4 <-> BLUETOOTH
+        {NvOdmDapPort_I2s2, NvOdmDapPort_BlueTooth,
+          {2, 16, 8000, NvOdmQueryI2sDataCommFormat_I2S } },   // Dap4
+    };
+    NvU32 CustOpt = GetBctKeyValue();
+    switch (NV_DRF_VAL(TEGRA_DEVKIT, BCT_CUSTOPT, RIL, CustOpt))
+    {
+    case TEGRA_DEVKIT_BCT_CUSTOPT_0_RIL_EMP_RAINBOW:
+    case TEGRA_DEVKIT_BCT_CUSTOPT_0_RIL_IFX:
+        if (DapPortId && DapPortId<NV_ARRAY_SIZE(s_Property_Ril_Emp_Rainbow))
+            return &s_Property_Ril_Emp_Rainbow[DapPortId];
+        break;
+    default:
+        if (DapPortId && DapPortId<NV_ARRAY_SIZE(s_Property))
+            return &s_Property[DapPortId];
+        break;
+    }
+    return NULL;
+}
+
+const NvOdmQueryDapPortConnection*
+NvOdmQueryDapPortGetConnectionTable(
+    NvU32 ConnectionIndex)
+{
+    static const NvOdmQueryDapPortConnection s_Property[] =
+    {
+        { NvOdmDapConnectionIndex_Music_Path,
+          2, { {NvOdmDapPort_I2s1, NvOdmDapPort_Dap1, NV_FALSE},
+               {NvOdmDapPort_Dap1, NvOdmDapPort_I2s1, NV_TRUE} } },
+    };
+    static const NvOdmQueryDapPortConnection s_Property_Ril_Emp_Rainbow[] =
+    {
+        { NvOdmDapConnectionIndex_Music_Path,
+          2, { {NvOdmDapPort_I2s1, NvOdmDapPort_Dap1, NV_FALSE},
+               {NvOdmDapPort_Dap1, NvOdmDapPort_I2s1, NV_TRUE} } },
+
+        // Voicecall without Bluetooth
+        { NvOdmDapConnectionIndex_VoiceCall_NoBlueTooth,
+          3, { {NvOdmDapPort_Dap3, NvOdmDapPort_Dap2, NV_FALSE},
+               {NvOdmDapPort_Dap2, NvOdmDapPort_Dap3, NV_TRUE},
+               {NvOdmDapPort_Dap2, NvOdmDapPort_I2s2, NV_TRUE} } },
+
+        // Voicecall with Bluetooth
+        { NvOdmDapConnectionIndex_VoiceCall_WithBlueTooth,
+          2, { {NvOdmDapPort_Dap4, NvOdmDapPort_Dap3, NV_TRUE},
+              {NvOdmDapPort_Dap3, NvOdmDapPort_Dap4, NV_FALSE}
+            }},
+
+    };
+    NvU32 TableIndex = 0;
+    NvU32 CustOpt = GetBctKeyValue();
+    switch (NV_DRF_VAL(TEGRA_DEVKIT, BCT_CUSTOPT, RIL, CustOpt))
+    {
+    case TEGRA_DEVKIT_BCT_CUSTOPT_0_RIL_EMP_RAINBOW:
+    case TEGRA_DEVKIT_BCT_CUSTOPT_0_RIL_IFX:
+        {
+            for( TableIndex = 0;
+                 TableIndex < NV_ARRAY_SIZE(s_Property_Ril_Emp_Rainbow); TableIndex++)
+            {
+                if (s_Property_Ril_Emp_Rainbow[TableIndex].UseIndex == ConnectionIndex)
+                    return &s_Property_Ril_Emp_Rainbow[TableIndex];
+            }
+        }
+        break;
+    default:
+        {
+            for( TableIndex = 0; TableIndex < NV_ARRAY_SIZE(s_Property); TableIndex++)
+            {
+                if (s_Property[TableIndex].UseIndex == ConnectionIndex)
+                    return &s_Property[TableIndex];
+            }
+        }
+        break;
+    }
+    return NULL;
+}
+
+const NvOdmQuerySpdifInterfaceProperty *
+NvOdmQuerySpdifGetInterfaceProperty(
+    NvU32 SpdifInstanceId)
+{
+    if (SpdifInstanceId == 0)
+        return &s_NvOdmQuerySpdifInterfacePropertySetting;
+
+    return NULL;
+}
+
+const NvOdmQueryAc97InterfaceProperty *
+NvOdmQueryAc97GetInterfaceProperty(
+    NvU32 Ac97InstanceId)
+{
+    return NULL;
+}
+
+const NvOdmQueryI2sACodecInterfaceProp *
+NvOdmQueryGetI2sACodecInterfaceProperty(
+    NvU32 AudioCodecId)
+{
+    static const NvOdmQueryI2sACodecInterfaceProp s_Property =
+    {
+        NV_TRUE,
+        0,
+        0x34,
+        NV_FALSE,
+        NvOdmQueryI2sLRLineControl_LeftOnLow,
+        NvOdmQueryI2sDataCommFormat_I2S
+    };
+    if (!AudioCodecId)
+        return &s_Property;
+    return NULL;
+}
+
+NvBool NvOdmQueryAsynchMemConfig(
+    NvU32 ChipSelect,
+    NvOdmAsynchMemConfig *pMemConfig)
+{
+    return NV_FALSE;
+}
+
+const void*
+NvOdmQuerySdramControllerConfigGet(NvU32 *pEntries, NvU32 *pRevision)
+{
+#if NVODM_ENABLE_EMC_DVFS
+    NvOdmBoardInfo BoardInfo;
+
+    if (NvOdmPeripheralGetBoardInfo(BOARD_ID_WHISTLER_E1109, &BoardInfo))
+    {
+        if (pRevision)
+            *pRevision = s_NvOdmE1109EmcConfigTable[0].Revision;
+        if (pEntries)
+            *pEntries = NV_ARRAY_SIZE(s_NvOdmE1109EmcConfigTable);
+        return (const void*)s_NvOdmE1109EmcConfigTable;
+    }
+    else if (NvOdmIsE1108Hynix())
+    {
+        if (pRevision)
+            *pRevision = s_NvOdmE1108HynixEmcConfigTable[0].Revision;
+        if (pEntries)
+            *pEntries = NV_ARRAY_SIZE(s_NvOdmE1108HynixEmcConfigTable);
+        return (const void*)s_NvOdmE1108HynixEmcConfigTable;
+    }
+#endif
+    if (pEntries)
+        *pEntries = 0;
+    return NULL;
+}
+
+NvOdmQueryOscillator NvOdmQueryGetOscillatorSource(void)
+{
+    return NvOdmQueryOscillator_Xtal;
+}
+
+NvU32 NvOdmQueryGetOscillatorDriveStrength(void)
+{
+    return 0x04;
+}
+
+const NvOdmWakeupPadInfo *NvOdmQueryGetWakeupPadTable(NvU32 *pSize)
+{
+    NvU32 CustOpt;
+    if (pSize)
+        *pSize = NV_ARRAY_SIZE(s_NvOdmWakeupPadInfo);
+
+    CustOpt = GetBctKeyValue();
+    switch (NV_DRF_VAL(TEGRA_DEVKIT, BCT_CUSTOPT, RIL, CustOpt))
+    {
+    case TEGRA_DEVKIT_BCT_CUSTOPT_0_RIL_EMP_RAINBOW:
+        s_NvOdmWakeupPadInfo[24].enable = NV_TRUE;
+        break;
+    case TEGRA_DEVKIT_BCT_CUSTOPT_0_RIL_IFX:
+        s_NvOdmWakeupPadInfo[13].enable = NV_TRUE;
+        break;
+    default:
+        break;
+    }
+
+    return (const NvOdmWakeupPadInfo *) s_NvOdmWakeupPadInfo;
+}
+
+
+const NvU8* NvOdmQueryManufacturer(void)
+{
+    return s_NvOdmQueryManufacturerSetting;
+}
+
+const NvU8* NvOdmQueryModel(void)
+{
+    return s_NvOdmQueryModelSetting;
+}
+
+const NvU8* NvOdmQueryPlatform(void)
+{
+    return s_NvOdmQueryPlatformSetting;
+}
+
+const NvU8* NvOdmQueryProjectName(void)
+{
+    return s_NvOdmQueryProjectNameSetting;
+}
+
+
+#define EXT 0     // external pull-up/down resistor
+#define INT_PU 1  // internal pull-up
+#define INT_PD 2  // internal pull-down
+
+#define HIGHSPEED 1
+#define SCHMITT 1
+#define VREF    1
+#define OHM_50 3
+#define OHM_100 2
+#define OHM_200 1
+#define OHM_400 0
+
+ // Pin attributes
+ static const NvOdmPinAttrib s_pin_config_attributes[] = {
+
+   { NvOdmPinRegister_Ap20_PullUpDown_A,
+     NVODM_QUERY_PIN_AP20_PULLUPDOWN_A(0x2, 0x2, 0x2, 0x0, 0x0, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x0, 0x1, 0x0) },
+    // Pull ups for the kbc pins
+   { NvOdmPinRegister_Ap20_PullUpDown_B,
+     NVODM_QUERY_PIN_AP20_PULLUPDOWN_B(0x0, 0x0, 0x2, 0x0, 0x2, 0x2, 0x2, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0) },
+
+   { NvOdmPinRegister_Ap20_PullUpDown_C,
+     NVODM_QUERY_PIN_AP20_PULLUPDOWN_C(0x1, 0x1, 0x1, 0x1, 0x2, 0x1, 0x2, 0x1, 0x2, 0x2, 0x2, 0x2, 0x2, 0x0, 0x0) },
+
+    // Pull ups for the kbc pins
+    { NvOdmPinRegister_Ap20_PullUpDown_E,
+      NVODM_QUERY_PIN_AP20_PULLUPDOWN_E(0x2, 0x2, 0x0, 0x0, 0x0, 0x0, 0x2, 0x0, 0x0, 0x0, 0x0, 0x2, 0x2, 0x2, 0x2, 0x2) },
+
+    // Set pad control for the sdio2 - - AOCFG1 and AOCFG2 pad control register
+    { NvOdmPinRegister_Ap20_PadCtrl_AOCFG1PADCTRL,
+      NVODM_QUERY_PIN_AP20_PADCTRL_AOCFG1PADCTRL(!HIGHSPEED, SCHMITT, OHM_50, 31, 31, 3, 3) },
+
+    { NvOdmPinRegister_Ap20_PadCtrl_AOCFG2PADCTRL,
+      NVODM_QUERY_PIN_AP20_PADCTRL_AOCFG1PADCTRL(!HIGHSPEED, SCHMITT, OHM_50, 31, 31, 3, 3) },
+
+    // Set pad control for the sdio1 - SDIO1 pad control register
+    { NvOdmPinRegister_Ap20_PadCtrl_SDIO1CFGPADCTRL,
+      NVODM_QUERY_PIN_AP20_PADCTRL_AOCFG1PADCTRL(!HIGHSPEED, SCHMITT, OHM_50, 31, 31, 3, 3) },
+
+    // Set pad control for the sdio3 - SDIO2 and SDIO3 pad control register
+    { NvOdmPinRegister_Ap20_PadCtrl_SDIO2CFGPADCTRL,
+      NVODM_QUERY_PIN_AP20_PADCTRL_AOCFG1PADCTRL(!HIGHSPEED, SCHMITT, OHM_50, 31, 31, 3, 3) },
+
+    { NvOdmPinRegister_Ap20_PadCtrl_SDIO3CFGPADCTRL,
+      NVODM_QUERY_PIN_AP20_PADCTRL_AOCFG1PADCTRL(!HIGHSPEED, SCHMITT, OHM_50, 31, 31, 3, 3) },
+
+    // Set pad control for the sdio4- ATCCFG1 and ATCCFG2 pad control register
+    { NvOdmPinRegister_Ap20_PadCtrl_ATCFG1PADCTRL,
+      NVODM_QUERY_PIN_AP20_PADCTRL_AOCFG1PADCTRL(!HIGHSPEED, SCHMITT, OHM_50, 31, 31, 3, 3) },
+
+    { NvOdmPinRegister_Ap20_PadCtrl_ATCFG2PADCTRL,
+      NVODM_QUERY_PIN_AP20_PADCTRL_AOCFG1PADCTRL(!HIGHSPEED, SCHMITT, OHM_50, 31, 31, 3, 3) },
+
+    // Set pad control for I2C1 pins
+    { NvOdmPinRegister_Ap20_PadCtrl_DBGCFGPADCTRL,
+      NVODM_QUERY_PIN_AP20_PADCTRL_AOCFG1PADCTRL(!HIGHSPEED, SCHMITT, OHM_50, 31, 31, 3, 3) },
+
+    { NvOdmPinRegister_Ap20_PadCtrl_VICFG1PADCTRL,
+      NVODM_QUERY_PIN_AP20_PADCTRL_AOCFG1PADCTRL(!HIGHSPEED, SCHMITT, OHM_50, 31, 31, 3, 3) },
+
+    { NvOdmPinRegister_Ap20_PadCtrl_VICFG2PADCTRL,
+      NVODM_QUERY_PIN_AP20_PADCTRL_AOCFG1PADCTRL(!HIGHSPEED, SCHMITT, OHM_50, 31, 31, 3, 3) },
+
+    // Set pad control for I2C2 (DDC) pins
+    { NvOdmPinRegister_Ap20_PadCtrl_DDCCFGPADCTRL,
+      NVODM_QUERY_PIN_AP20_PADCTRL_AOCFG1PADCTRL(!HIGHSPEED, SCHMITT, OHM_50, 31, 31, 3, 3) },
+
+    // Set pad control for Dap pins 1 - 4
+    { NvOdmPinRegister_Ap20_PadCtrl_DAP1CFGPADCTRL,
+      NVODM_QUERY_PIN_AP20_PADCTRL_AOCFG1PADCTRL(!HIGHSPEED, SCHMITT, OHM_400, 0, 0, 0, 0) },
+
+    { NvOdmPinRegister_Ap20_PadCtrl_DAP2CFGPADCTRL,
+      NVODM_QUERY_PIN_AP20_PADCTRL_AOCFG1PADCTRL(!HIGHSPEED, SCHMITT, OHM_400, 0, 0, 0, 0) },
+
+    { NvOdmPinRegister_Ap20_PadCtrl_DAP3CFGPADCTRL,
+      NVODM_QUERY_PIN_AP20_PADCTRL_AOCFG1PADCTRL(!HIGHSPEED, SCHMITT, OHM_400, 0, 0, 0, 0) },
+
+    { NvOdmPinRegister_Ap20_PadCtrl_DAP3CFGPADCTRL,
+      NVODM_QUERY_PIN_AP20_PADCTRL_AOCFG1PADCTRL(!HIGHSPEED, SCHMITT, OHM_400, 0, 0, 0, 0) },
+ };
+
+
+NvU32
+NvOdmQueryPinAttributes(const NvOdmPinAttrib** pPinAttributes)
+{
+    *pPinAttributes = &s_pin_config_attributes[0];
+    return NV_ARRAY_SIZE(s_pin_config_attributes);
+}
+
+NvBool NvOdmQueryGetPmuProperty(NvOdmPmuProperty* pPmuProperty)
+{
+#ifdef CONFIG_TEGRA_USB_VBUS_DETECT_BY_PMU
+    pPmuProperty->IrqConnected = NV_TRUE;
+#else
+    pPmuProperty->IrqConnected = NV_FALSE;
+#endif
+    pPmuProperty->PowerGoodCount = 0x7E;
+    pPmuProperty->IrqPolarity = NvOdmInterruptPolarity_Low;
+    
+    // Not there yet, add it later ...
+    //pPmuProperty->CpuPowerReqPolarity = ;
+
+    pPmuProperty->CorePowerReqPolarity = NvOdmCorePowerReqPolarity_High;
+    pPmuProperty->SysClockReqPolarity = NvOdmSysClockReqPolarity_High;
+    pPmuProperty->CombinedPowerReq = NV_TRUE;
+    pPmuProperty->CpuPowerGoodUs = 2000;
+    pPmuProperty->AccuracyPercent = 3;
+
+    if (NvOdmIsCpuExtSupply() ||
+        NvOdmIsCpuRailPreserved())
+        pPmuProperty->VCpuOTPOnWakeup = NV_FALSE;
+    else
+        pPmuProperty->VCpuOTPOnWakeup = NV_TRUE;
+
+    return NV_TRUE;
+}
+
+/**
+ * Gets the lowest soc power state supported by the hardware
+ *
+ * @returns information about the SocPowerState
+ */
+const NvOdmSocPowerStateInfo* NvOdmQueryLowestSocPowerState(void)
+{
+
+    static                      NvOdmSocPowerStateInfo  PowerStateInfo;
+    const static                NvOdmSocPowerStateInfo* pPowerStateInfo = NULL;
+    NvOdmServicesKeyListHandle  hKeyList;
+    NvU32                       LPStateSelection = 0;
+    if (pPowerStateInfo == NULL)
+    {
+        hKeyList = NvOdmServicesKeyListOpen();
+        if (hKeyList)
+        {
+            LPStateSelection = NvOdmServicesGetKeyValue(hKeyList,
+                                                NvOdmKeyListId_ReservedBctCustomerOption);
+            NvOdmServicesKeyListClose(hKeyList);
+            LPStateSelection = NV_DRF_VAL(TEGRA_DEVKIT, BCT_CUSTOPT, LPSTATE, LPStateSelection);
+        }
+        // Lowest power state controlled by the flashed custom option.
+        PowerStateInfo.LowestPowerState =  ((LPStateSelection != TEGRA_DEVKIT_BCT_CUSTOPT_0_LPSTATE_LP1)?
+                                            NvOdmSocPowerState_Suspend : NvOdmSocPowerState_DeepSleep);
+        pPowerStateInfo = (const NvOdmSocPowerStateInfo*) &PowerStateInfo;
+    }
+    return (pPowerStateInfo);
+}
+
+const NvOdmUsbProperty*
+NvOdmQueryGetUsbProperty(NvOdmIoModule OdmIoModule,
+                         NvU32 Instance)
+{
+#ifdef CONFIG_TEGRA_USB_VBUS_DETECT_BY_PMU
+#define NVODM_USE_INTERNAL_PHY_VBUS_DETECTION  NV_FALSE
+#else
+#define NVODM_USE_INTERNAL_PHY_VBUS_DETECTION  NV_TRUE
+#endif
+    static const NvOdmUsbProperty Usb1Property =
+    {
+        NvOdmUsbInterfaceType_Utmi,
+        (NvOdmUsbChargerType_SE0 | NvOdmUsbChargerType_SE1 | NvOdmUsbChargerType_SK),
+        20,
+        NVODM_USE_INTERNAL_PHY_VBUS_DETECTION,
+#ifdef CONFIG_USB_TEGRA_OTG
+        NvOdmUsbModeType_OTG,
+#else
+        NvOdmUsbModeType_Device,
+#endif
+        NvOdmUsbIdPinType_CableId,
+        NvOdmUsbConnectorsMuxType_None,
+        NV_FALSE
+    };
+
+    static const NvOdmUsbProperty Usb2Property =
+    {
+        NvOdmUsbInterfaceType_UlpiExternalPhy,
+        NvOdmUsbChargerType_UsbHost,
+        20,
+        NVODM_USE_INTERNAL_PHY_VBUS_DETECTION,
+        NvOdmUsbModeType_None,
+        NvOdmUsbIdPinType_None,
+        NvOdmUsbConnectorsMuxType_None,
+        NV_FALSE
+    };
+
+    static const NvOdmUsbProperty Usb2NullPhyProperty =
+    {
+        NvOdmUsbInterfaceType_UlpiNullPhy,
+        NvOdmUsbChargerType_UsbHost,
+        20,
+        NVODM_USE_INTERNAL_PHY_VBUS_DETECTION,
+        NvOdmUsbModeType_Host,
+        NvOdmUsbIdPinType_None,
+        NvOdmUsbConnectorsMuxType_None,
+        NV_FALSE,
+        {10, 1, 1, 1}
+    };
+
+    static const NvOdmUsbProperty Usb3Property =
+    {
+        NvOdmUsbInterfaceType_Utmi,
+        NvOdmUsbChargerType_UsbHost,
+        20,
+        NVODM_USE_INTERNAL_PHY_VBUS_DETECTION,
+        NvOdmUsbModeType_Host,
+        NvOdmUsbIdPinType_CableId,
+        NvOdmUsbConnectorsMuxType_None,
+        NV_FALSE
+    };
+
+    /* E1108 has no ID pin for USB3, so disable USB3 Host */
+    static const NvOdmUsbProperty Usb3Property_E1108 =
+    {
+        NvOdmUsbInterfaceType_Utmi,
+        NvOdmUsbChargerType_UsbHost,
+        20,
+        NVODM_USE_INTERNAL_PHY_VBUS_DETECTION,
+        NvOdmUsbModeType_None,
+        NvOdmUsbIdPinType_None,
+        NvOdmUsbConnectorsMuxType_None,
+        NV_FALSE
+    };
+
+    if (OdmIoModule == NvOdmIoModule_Usb && Instance == 0)
+        return &(Usb1Property);
+
+    if (OdmIoModule == NvOdmIoModule_Usb && Instance == 1)
+    {
+        NvU32 CustOpt = GetBctKeyValue();
+
+        if (NV_DRF_VAL(TEGRA_DEVKIT, BCT_CUSTOPT, RIL, CustOpt) ==
+            TEGRA_DEVKIT_BCT_CUSTOPT_0_RIL_EMP_RAINBOW_ULPI)
+            return &(Usb2NullPhyProperty);
+        else
+            return &(Usb2Property);
+    }
+
+    if (OdmIoModule == NvOdmIoModule_Usb && Instance == 2)
+    {
+        NvOdmBoardInfo BoardInfo;
+        if (NvOdmPeripheralGetBoardInfo(BOARD_ID_WHISTLER_E1108, &BoardInfo))
+        {
+            return &(Usb3Property_E1108);
+        }
+        else
+        {
+            return &(Usb3Property);
+        }
+    }
+
+    return (const NvOdmUsbProperty *)NULL;
+}
+
+const NvOdmQuerySdioInterfaceProperty* NvOdmQueryGetSdioInterfaceProperty(NvU32 Instance)
+{
+    NvU32 CustomerOption = 0;
+    NvU32 Personality = 0;
+    NvOdmServicesKeyListHandle hKeyList;
+    static NvBool s_IsVoyagerBoard = NV_FALSE;
+    NvOdmBoardInfo BoardInfo;
+    static NvBool s_IsBoardInfoDone = NV_FALSE;
+
+    // Detect whether the board is voyager or not
+    if (!s_IsBoardInfoDone)
+    {
+        s_IsVoyagerBoard = NvOdmPeripheralGetBoardInfo(
+                            BOARD_ID_VOYAGER_MAINBOARD_E1215, &BoardInfo);
+        s_IsBoardInfoDone = NV_TRUE;
+    }
+
+    hKeyList = NvOdmServicesKeyListOpen();
+    if (hKeyList)
+    {
+        CustomerOption =
+            NvOdmServicesGetKeyValue(hKeyList,
+                                     NvOdmKeyListId_ReservedBctCustomerOption);
+        NvOdmServicesKeyListClose(hKeyList);
+        Personality =
+            NV_DRF_VAL(TEGRA_DEVKIT, BCT_CUSTOPT, PERSONALITY, CustomerOption);
+    }
+
+    if (!Personality)
+        Personality = TEGRA_DEVKIT_DEFAULT_PERSONALITY;
+
+    if (s_IsVoyagerBoard)
+        return &s_NvOdmQuerySdioInterfaceProperty_Voyager[Instance];
+
+    if (Personality == TEGRA_DEVKIT_BCT_CUSTOPT_0_PERSONALITY_75 ||
+        Personality == TEGRA_DEVKIT_BCT_CUSTOPT_0_PERSONALITY_15 ||
+        Personality == TEGRA_DEVKIT_BCT_CUSTOPT_0_PERSONALITY_05 ||
+        Personality == TEGRA_DEVKIT_BCT_CUSTOPT_0_PERSONALITY_C3)
+        s_NvOdmQuerySdioInterfaceProperty_Whistler[2].IsCardRemovable = NV_TRUE;
+
+    return &s_NvOdmQuerySdioInterfaceProperty_Whistler[Instance];
+}
+
+const NvOdmQueryHsmmcInterfaceProperty* NvOdmQueryGetHsmmcInterfaceProperty(NvU32 Instance)
+{
+    return NULL;
+}
+
+NvU32
+NvOdmQueryGetBlockDeviceSectorSize(NvOdmIoModule OdmIoModule)
+{
+    return 0;
+}
+
+const NvOdmQueryOwrDeviceInfo* NvOdmQueryGetOwrDeviceInfo(NvU32 Instance)
+{
+    return &s_NvOdmQueryOwrInfo;
+}
+
+const NvOdmGpioWakeupSource *NvOdmQueryGetWakeupSources(NvU32 *pCount)
+{
+    *pCount = 0;
+    return NULL;
+}
+
+/**
+ * This function is called from early boot process.
+ * Therefore, it cannot use global variables.
+ */
+NvU32 NvOdmQueryMemSize(NvOdmMemoryType MemType)
+{
+    NvOdmOsOsInfo Info;
+    NvU32 SdramSize;
+    NvU32 SdramBctCustOpt;
+    
+    switch (MemType)
+    {
+        // NOTE:
+        // For Windows CE/WM operating systems the total size of SDRAM may
+        // need to be reduced due to limitations in the virtual address map.
+        // Under the legacy physical memory manager, Windows OSs have a
+        // maximum 512MB statically mapped virtual address space. Under the
+        // new physical memory manager, Windows OSs have a maximum 1GB
+        // statically mapped virtual address space. Out of that virtual
+        // address space, the upper 32 or 36 MB (depending upon the SOC)
+        // of the virtual address space is reserved for SOC register
+        // apertures.
+        //
+        // Refer to virtual_tables_apxx.arm for the reserved aperture list.
+        // If the cumulative size of the reserved apertures changes, the
+        // maximum size of SDRAM will also change.
+        case NvOdmMemoryType_Sdram:
+        {
+            SdramBctCustOpt = GetBctKeyValue();
+            switch (NV_DRF_VAL(TEGRA_DEVKIT, BCT_SYSTEM, MEMORY, SdramBctCustOpt))
+            {
+                case TEGRA_DEVKIT_BCT_SYSTEM_0_MEMORY_1:
+                    SdramSize = 0x10000000; //256 MB
+                    break;
+                case TEGRA_DEVKIT_BCT_SYSTEM_0_MEMORY_3:
+                    SdramSize = 0x40000000; //1GB
+                    break;
+                case TEGRA_DEVKIT_BCT_SYSTEM_0_MEMORY_2:
+                case TEGRA_DEVKIT_BCT_SYSTEM_0_MEMORY_DEFAULT:
+                default:
+                    SdramSize = 0x20000000; //512 MB
+                    break;
+            }
+            
+            if ( NvOdmOsGetOsInformation(&Info) &&
+                 ((Info.OsType!=NvOdmOsOs_Windows) ||
+                  (Info.OsType==NvOdmOsOs_Windows && Info.MajorVersion>=7)) )
+                return SdramSize;
+
+            // Legacy Physical Memory Manager: SdramSize MB - Carveout MB
+            return (SdramSize - NvOdmQueryCarveoutSize());
+        }
+        
+        case NvOdmMemoryType_Nor:
+            return 0x00400000;  // 4 MB
+
+        case NvOdmMemoryType_Nand:
+        case NvOdmMemoryType_I2CEeprom:
+        case NvOdmMemoryType_Hsmmc:
+        case NvOdmMemoryType_Mio:
+        default:
+            return 0;
+    }
+}
+
+NvU32 NvOdmQueryCarveoutSize(void)
+{
+    NvU32 CarveBctCustOpt = GetBctKeyValue();
+
+    switch (NV_DRF_VAL(TEGRA_DEVKIT, BCT_CARVEOUT, MEMORY, CarveBctCustOpt))
+    {
+        case TEGRA_DEVKIT_BCT_CARVEOUT_0_MEMORY_1:
+            return 0x00400000;// 4MB
+        case TEGRA_DEVKIT_BCT_CARVEOUT_0_MEMORY_2:
+            return 0x00800000;// 8MB
+        case TEGRA_DEVKIT_BCT_CARVEOUT_0_MEMORY_3:
+            return 0x00C00000;// 12MB
+        case TEGRA_DEVKIT_BCT_CARVEOUT_0_MEMORY_4:
+            return 0x01000000;// 16MB
+        case TEGRA_DEVKIT_BCT_CARVEOUT_0_MEMORY_5:
+            return 0x01400000;// 20MB
+        case TEGRA_DEVKIT_BCT_CARVEOUT_0_MEMORY_6:
+            return 0x01800000;// 24MB
+        case TEGRA_DEVKIT_BCT_CARVEOUT_0_MEMORY_7:
+            return 0x01C00000;// 28MB
+        case TEGRA_DEVKIT_BCT_CARVEOUT_0_MEMORY_8:
+            return 0x02000000; // 32 MB
+        case TEGRA_DEVKIT_BCT_CARVEOUT_0_MEMORY_DEFAULT:
+        default:
+            return 0x04000000; // 64 MB
+    }
+}
+
+NvU32 NvOdmQuerySecureRegionSize(void)
+{
+    return 0x00800000;// 8 MB
+}
+
diff --git a/arch/arm/mach-tegra/odm_kit/query/whistler/nvodm_query_discovery.c b/arch/arm/mach-tegra/odm_kit/query/whistler/nvodm_query_discovery.c
new file mode 100644
index 000000000000..9cf5ddf199a2
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/query/whistler/nvodm_query_discovery.c
@@ -0,0 +1,997 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/**
+ * @file
+ * <b>NVIDIA APX ODM Kit::
+ *         Implementation of the ODM Peripheral Discovery API</b>
+ *
+ * @b Description: The peripheral connectivity database implementation.
+ */
+
+#include "nvcommon.h"
+#include "nvodm_query_gpio.h"
+#include "nvodm_modules.h"
+#include "nvodm_query_discovery.h"
+#include "nvodm_keylist_reserved.h"
+#include "tegra_devkit_custopt.h"
+#include "nvodm_query.h"
+#include "nvrm_drf.h"
+
+#include "subboards/nvodm_query_discovery_e888_addresses.h"
+#include "subboards/nvodm_query_discovery_e906_addresses.h"
+#include "subboards/nvodm_query_discovery_e911_addresses.h"
+#include "subboards/nvodm_query_discovery_e936_addresses.h"
+#include "subboards/nvodm_query_discovery_e951_addresses.h"
+#include "subboards/nvodm_query_discovery_e1109_addresses.h"
+#include "subboards/nvodm_query_discovery_e1116_addresses.h"
+#include "subboards/nvodm_query_discovery_e1120_addresses.h"
+#include "subboards/nvodm_query_discovery_e1129_addresses.h"
+//#include "subboards/nvodm_query_discovery_e1215_addresses.h" // enable with accelerometer bring-up (Voyager)
+
+static NvOdmPeripheralConnectivity s_Peripherals_Default[] =
+{
+#include "subboards/nvodm_query_discovery_e888_peripherals.h"
+#include "subboards/nvodm_query_discovery_e906_peripherals.h"
+#include "subboards/nvodm_query_discovery_e911_peripherals.h"
+#include "subboards/nvodm_query_discovery_e936_peripherals.h"
+#include "subboards/nvodm_query_discovery_e951_peripherals.h"
+#include "subboards/nvodm_query_discovery_e1109_peripherals.h"
+#include "subboards/nvodm_query_discovery_e1116_peripherals.h"
+#include "subboards/nvodm_query_discovery_e1120_peripherals.h"
+#include "subboards/nvodm_query_discovery_e1129_peripherals.h"
+//#include "subboards/nvodm_query_discovery_e1215_peripherals.h" // enable with accelerometer bring-up (Voyager)
+};
+
+// Function to auto-detect boards with external CPU power supply
+// defined in nvodm_query.c
+extern NvBool NvOdmIsCpuExtSupply(void);
+
+#define NVODM_QUERY_BOARD_ID_UNKNOWN    0xFFFF
+
+#define NVODM_QUERY_MAX_PERIPHERALS     0x400
+#define NVODM_QUERY_MAX_IO_ADDRESSES    0x400
+
+#define NVODM_QUERY_MAX_BUS_SEGMENTS    4   // # of Bus Segments defined by I2C extender
+#define NVODM_QUERY_MAX_EEPROMS         8   // Maximum number of EEPROMs per bus segment
+
+#define NVODM_QUERY_ERASED_EEPROM_VALUE 0xFF
+
+#define PROCESSOR_BOARD_ID_I2C_ADDRESS ((0x56)<<1)
+#define PROCESSOR_BOARD_ID_I2C_SEGMENT (0x00)
+
+// The following are used to store entries read from EEPROMs at runtime.
+static NvOdmPeripheralConnectivity s_Peripherals[NVODM_QUERY_MAX_PERIPHERALS];
+static NvOdmIoAddress s_Peripheral_IoAddresses[NVODM_QUERY_MAX_IO_ADDRESSES];
+static NvOdmBoardInfo s_BoardModuleTable[NVODM_QUERY_MAX_BUS_SEGMENTS * NVODM_QUERY_MAX_EEPROMS];
+
+#define NVODM_QUERY_I2C_CLOCK_SPEED      100    // kHz
+
+#define NVODM_QUERY_ENTRY_HEADER_SIZE    0x30   // Size of EERPOM "Entry Header"
+#define NVODM_QUERY_BOARD_HEADER_START   0x04   // Offset to Part Number in EERPOM
+
+#define NVODM_QUERY_I2C_EEPROM_ADDRESS   0xA0   // I2C device base address for EEPROM (7'h50)
+#define NVODM_QUERY_I2C_EXTENDER_ADDRESS 0x42   // I2C bus extender address (7'h21)
+
+#define NVODM_QUERY_PERIPH_CONN_STRUCT_COMPRESSED   10  // See EEPROM_format.txt
+#define NVODM_PERIPH_IO_ADDR_STRUCT_SZ_COMPRESSED   2   // See EEPROM_format.txt
+
+// The following board IDs are used to auto-configure the thermal rail (VOUT15)
+#define BOARD_ID_E1107          0x0B07
+#define BOARD_ID_E1108          0x0B08
+#define BOARD_ID_E1109          0x0B09
+#define BOARD_ID_E1117          0x0B11
+#define BOARD_ID_E951           0x0933
+
+#define PROCESSOR_MODULE_REV_A  0
+
+// A list of the Whistler processor boards
+static NvU32 gs_WhistlerProcessorBoards[] = {
+    BOARD_ID_E1107,
+    BOARD_ID_E1108,
+    BOARD_ID_E1109
+};
+
+// A list of Whistler DDR2 processor boards
+static NvU32 s_WhistlerDDR2Boards[] = {
+    BOARD_ID_E1107,
+    BOARD_ID_E1109,
+    BOARD_ID_E1117
+};
+
+
+static NvOdmI2cStatus
+NvOdmPeripheralI2cRead8(
+    NvOdmServicesI2cHandle hOdmI2c,
+    NvU8 I2cAddr,
+    NvU8 Offset,
+    NvU8 *pData)
+{
+    NvU8 ReadBuffer[1];
+    NvOdmI2cStatus Error;    
+    NvOdmI2cTransactionInfo TransactionInfo;
+
+    ReadBuffer[0] = Offset;
+
+    TransactionInfo.Address = I2cAddr;
+    TransactionInfo.Buf = ReadBuffer;
+    TransactionInfo.Flags = NVODM_I2C_IS_WRITE;
+    TransactionInfo.NumBytes = 1;
+
+    Error = NvOdmI2cTransaction(
+        hOdmI2c, &TransactionInfo, 1, NVODM_QUERY_I2C_CLOCK_SPEED, NV_WAIT_INFINITE);
+    if (Error != NvOdmI2cStatus_Success)
+    {
+        return Error;
+    }
+
+    NvOdmOsMemset(ReadBuffer, 0, sizeof(ReadBuffer));  
+
+    TransactionInfo.Address = (I2cAddr | 0x1);
+    TransactionInfo.Buf = ReadBuffer;
+    TransactionInfo.Flags = 0;
+    TransactionInfo.NumBytes = 1;
+
+    // Read data from ROM at the specified offset
+    Error = NvOdmI2cTransaction(
+        hOdmI2c, &TransactionInfo, 1, NVODM_QUERY_I2C_CLOCK_SPEED, NV_WAIT_INFINITE);
+    if (Error != NvOdmI2cStatus_Success)
+    {
+        return Error;
+    }
+    *pData = ReadBuffer[0];
+    return Error;
+}
+
+static NvBool
+NvOdmPeripheralSetBusSegment(
+    NvOdmServicesI2cHandle hOdmI2c,
+    NvU16 BusSegment)
+{
+    NvU8 WriteBuffer[2];
+    NvOdmI2cStatus Error;    
+    NvOdmI2cTransactionInfo TransactionInfo;
+    NvU8 Data;
+
+    Data = (NvU8)(BusSegment & 0xF);
+
+    WriteBuffer[0] = 0x03;  // Register (0x03)
+    WriteBuffer[1] = 0x00;  // Data
+
+    TransactionInfo.Address = NVODM_QUERY_I2C_EXTENDER_ADDRESS;
+    TransactionInfo.Buf = WriteBuffer;
+    TransactionInfo.Flags = NVODM_I2C_IS_WRITE;
+    TransactionInfo.NumBytes = 2;
+
+    Error = NvOdmI2cTransaction(
+        hOdmI2c, &TransactionInfo, 1, NVODM_QUERY_I2C_CLOCK_SPEED, NV_WAIT_INFINITE);
+    if (Error != NvOdmI2cStatus_Success)
+    {
+        return NV_FALSE;
+    }
+    
+    WriteBuffer[0] = 0x01;  // Register (0x01)
+    WriteBuffer[1] = Data;  // Data (bus segment 0 thru 3)
+
+    Error = NvOdmI2cTransaction(
+        hOdmI2c, &TransactionInfo, 1, NVODM_QUERY_I2C_CLOCK_SPEED, NV_WAIT_INFINITE);
+    if (Error != NvOdmI2cStatus_Success)
+    {
+        return NV_FALSE;
+    }
+
+    return NV_TRUE;
+}
+
+static NvBool
+NvOdmPeripheralReadNumPeripherals(
+    NvOdmServicesI2cHandle hOdmI2c,
+    NvU8 EepromInst,
+    NvU8 *pNumModulePeripherals)
+{
+    NvOdmI2cStatus Error;    
+    NvU8 I2cAddr, Offset;
+
+    // EepromInst*2, since 7-bit addressing
+    I2cAddr = NVODM_QUERY_I2C_EEPROM_ADDRESS + (EepromInst << 1);
+
+    /**
+     * Offset to numPeripherals in NvOdmPeripheralConnectivity Structure.
+     * It's the first parameter after the "Entry Header."
+     */
+    Offset = NVODM_QUERY_ENTRY_HEADER_SIZE;
+
+    Error = NvOdmPeripheralI2cRead8(
+        hOdmI2c, I2cAddr, Offset, pNumModulePeripherals);
+    if (Error != NvOdmI2cStatus_Success)
+    {
+        return NV_FALSE;
+    }
+    return NV_TRUE;
+}
+
+static NvBool
+NvOdmPeripheralReadPeripheral(
+    NvOdmServicesI2cHandle hOdmI2c,
+    NvU8 EepromInst,
+    NvU8 Peripheral,
+    NvU64 *pGuid,
+    NvU8 *pEepromAddressListOffset,
+    NvU32 *pNumAddress,
+    NvOdmPeripheralClass *pClass)
+{
+    NvOdmI2cStatus Error;    
+    NvU32 i;
+    NvU8 ConnMemberIndex=0; // Offset to members in NvOdmPeripheralConnectivity
+    NvU8 I2cAddr, Offset;
+    NvU8 ReadBuffer[NVODM_QUERY_PERIPH_CONN_STRUCT_COMPRESSED];
+    NvU8 NumAddrAndClass;
+
+    // EepromInst*2, since 7-bit addressing
+    I2cAddr = NVODM_QUERY_I2C_EEPROM_ADDRESS + (EepromInst << 1);
+
+    /**
+     * Calculate offset to pGuid in NvOdmPeripheralConnectivity Structure
+     * 
+     *  Offset = sizeof(eeprom Entry Header) + 
+     *           sizeof(NvOdmPeripheralConnectivity)*peripheral + 
+     *           pGuid offset    <-- First field, so this is 0
+     */
+    Offset = NVODM_QUERY_ENTRY_HEADER_SIZE + 
+        sizeof(NvOdmPeripheralConnectivity)*Peripheral;
+
+    for (i=0; i<NVODM_QUERY_PERIPH_CONN_STRUCT_COMPRESSED; i++)
+    {
+        Error = NvOdmPeripheralI2cRead8(
+            hOdmI2c, I2cAddr, Offset, (NvU8 *)&ReadBuffer[i]);
+        if (Error != NvOdmI2cStatus_Success)
+        {
+            return NV_FALSE;
+        }
+    }
+    // Save pGuid entry
+    NvOdmOsMemcpy(pGuid, &ReadBuffer[0], sizeof(NvU64));
+
+    // Save EEPROM offset
+    ConnMemberIndex += sizeof(NvU64); // Increment to next member
+    *pEepromAddressListOffset = ReadBuffer[ConnMemberIndex];
+
+    // Save pNumAddress & Class
+    ConnMemberIndex += sizeof(NvU8); // Increment to next member
+    NumAddrAndClass = ReadBuffer[ConnMemberIndex];
+    *pNumAddress = (NvU32)((NumAddrAndClass >> 3) & 0x0000001F);
+    *pClass = (NvOdmPeripheralClass)(NumAddrAndClass & 0x00000007);
+
+    return NV_TRUE;
+}
+
+static NvBool
+NvOdmPeripheralReadIoAddressData(
+    NvOdmServicesI2cHandle hOdmI2c,
+    NvU8 EepromInst,
+    NvU8 EepromAddressListOffset,
+    NvOdmIoAddress *pIoAddressEntry)
+{
+    NvOdmI2cStatus Error;    
+    NvU32 i;
+    NvU8 I2cAddr;
+    NvU8 ReadBuffer[NVODM_PERIPH_IO_ADDR_STRUCT_SZ_COMPRESSED];
+    NvU16 CompressedIoAddressEntry;
+
+    // EepromInst*2, since 7-bit addressing
+    I2cAddr = NVODM_QUERY_I2C_EEPROM_ADDRESS + (EepromInst << 1);
+
+    for (i=0; i<NVODM_PERIPH_IO_ADDR_STRUCT_SZ_COMPRESSED; i++)
+    {
+        Error = NvOdmPeripheralI2cRead8(
+            hOdmI2c, I2cAddr, EepromAddressListOffset, (NvU8 *)&ReadBuffer[i]);
+        if (Error != NvOdmI2cStatus_Success)
+        {
+            return NV_FALSE;
+        }
+    }
+    // Save pIoAddressEntry: interface, instance, address
+    CompressedIoAddressEntry = ((((NvU16)ReadBuffer[1]) << 8) & 0xFF00) | ReadBuffer[0];
+
+    pIoAddressEntry->Interface = (NvOdmIoModule)((CompressedIoAddressEntry >> 11) & 0x1F);
+
+    if (pIoAddressEntry->Interface != NvOdmIoModule_Gpio)
+    {
+        pIoAddressEntry->Instance = (NvU32)((CompressedIoAddressEntry >> 7) & 0xF);
+        pIoAddressEntry->Address = (NvU32)(CompressedIoAddressEntry & 0x7F);
+    }
+    else
+    {
+        pIoAddressEntry->Address = (NvU32)((CompressedIoAddressEntry >> 6) & 0x3F);
+        pIoAddressEntry->Instance = (NvU32)(CompressedIoAddressEntry & 0x3F);
+    }
+
+    return NV_TRUE;
+}
+
+static NvBool NvOdmPeripheralGetEntries(NvU32 *pNum)
+{
+    NvBool RetVal;
+    NvBool IsMatch = NV_FALSE;
+    NvOdmServicesI2cHandle hOdmI2c = NULL;
+    NvU8 BusSegment, EepromInst;
+
+    // Peripheral counters
+    NvU8 NumPeripherals = 0;
+    NvU8 CurrentPeripheral = 0;
+    NvU32 TotalPeripherals = 0;
+    NvU32 StaticPeripherals;
+
+    NvU32 CurrentIoAddressNum = 0;
+    NvU32 TotalIoAddressEntries = 0;
+
+    NvU32 i,j;
+    NvU8 EepromAddressListOffset;
+
+    if (!pNum) {
+        return NV_FALSE;
+    }
+
+    // Auto-detect -- Read I2C-EEPROMs on each sub-board
+
+    hOdmI2c = NvOdmI2cOpen(NvOdmIoModule_I2c_Pmu, 0);
+    if (!hOdmI2c)
+        return NV_FALSE;
+
+    for (BusSegment=0; BusSegment < NVODM_QUERY_MAX_BUS_SEGMENTS; BusSegment++)
+    {
+        RetVal = NvOdmPeripheralSetBusSegment(hOdmI2c, BusSegment);
+        if (RetVal == NV_FALSE)
+        {
+            /** 
+             * Bus segment not found. Set BusSegment to MAX and try reading 
+             * any ID EEPROMS which might be available without the bus 
+             * expander. 
+             */
+            BusSegment = NVODM_QUERY_MAX_BUS_SEGMENTS;
+        }
+
+        for (EepromInst=0; EepromInst < NVODM_QUERY_MAX_EEPROMS; EepromInst++)
+        {
+            RetVal = NvOdmPeripheralReadNumPeripherals(
+                hOdmI2c, EepromInst, &NumPeripherals);
+
+            if ( (RetVal == NV_TRUE) &&
+                 (NumPeripherals != NVODM_QUERY_ERASED_EEPROM_VALUE) )
+            {
+                if (NumPeripherals > 0)
+                {
+                    if ((NumPeripherals + TotalPeripherals) > NVODM_QUERY_MAX_PERIPHERALS)
+                    {
+                        NV_ASSERT( !"ERROR: s_Peripherals[] is too small to accommodate entries!" );
+
+                        // Break out of loop and use static/default configuration
+                        break;
+                    }
+
+                    for (CurrentPeripheral=0; \
+                          CurrentPeripheral < NumPeripherals; \
+                          CurrentPeripheral++)
+                    {
+                        RetVal = NvOdmPeripheralReadPeripheral(
+                            hOdmI2c,
+                            EepromInst,
+                            CurrentPeripheral,
+                            &s_Peripherals[TotalPeripherals+CurrentPeripheral].Guid,
+                            &EepromAddressListOffset,
+                            &s_Peripherals[TotalPeripherals+CurrentPeripheral].NumAddress,
+                            &s_Peripherals[TotalPeripherals+CurrentPeripheral].Class);
+
+                        if (RetVal == NV_FALSE)
+                        {
+                            NV_ASSERT(!"Unable to read EEPROM peripheral entry!");
+                            break;  // Go to next EEPROM
+                        }
+                        else // Process peripheral entry
+                        {
+                            /**
+                             * Process NvOdmIoAddress arrays --
+                             * 
+                             * These are separate data structures.  The addressList value
+                             * read from the EEPROM (EepromAddressListOffset) represents
+                             * an offset address within the I2C-EEPROM.  This offset value
+                             * identifies where to find the first instance of the
+                             * NvOdmIoAddress data.
+                             * 
+                             * The total number of NvOdmIoAddress entries is identified
+                             * by the numAddress variable following the addressList entry
+                             * in EEPROM.
+                             * 
+                             * Once the offset and number of entries are determined (from
+                             * above NvOdmPeripheralReadPeripheral function call), a loop
+                             * fills in entries within the fixed storage area
+                             * (e.g., s_Peripheral_IoAddresses) and the actual
+                             * addressList pointer is assigned a value that corresponds
+                             * to the first entry of the current class within this array.
+                             * In other words, there might be prior entries in the
+                             * s_Peripheral_IoAddresses array, but the first entry
+                             * corresponding to the current class might be the third
+                             * element in this array.  Therefore, the actual addressList
+                             * pointer for the current NvOdmPeripheralConnectivity.addressList
+                             * parameter would be the address of the third entry, which is
+                             * &s_Peripheral_IoAddresses[2] in this example.
+                             */
+    
+                            // Read all of the entries and save them in s_Peripheral_IoAddresses
+                            for (CurrentIoAddressNum=0; \
+                                  CurrentIoAddressNum < s_Peripherals[TotalPeripherals+CurrentPeripheral].NumAddress; \
+                                  CurrentIoAddressNum++)
+                            {
+                                if (TotalIoAddressEntries > NVODM_QUERY_MAX_IO_ADDRESSES)
+                                {
+                                    NV_ASSERT( !"ERROR: s_Peripheral_IoAddresses[] is too small to accommodate entries!" );
+
+                                    // Cannot recover from this error.
+                                    NvOdmI2cClose(hOdmI2c);
+                                    return NV_FALSE;
+                                }
+
+                                RetVal = NvOdmPeripheralReadIoAddressData(
+                                    hOdmI2c,
+                                    EepromInst,
+                                    EepromAddressListOffset,
+                                    &s_Peripheral_IoAddresses[TotalIoAddressEntries+CurrentIoAddressNum]);
+    
+                                if (RetVal == NV_FALSE)
+                                {
+                                    NV_ASSERT(!"Unable to read EEPROM (IoAddresses)!");
+
+                                    // Cannot recover from this error.
+                                    NvOdmI2cClose(hOdmI2c);
+                                    return NV_FALSE;
+                                }
+                                else // Process IoAddresses entry
+                                {
+                                    /**
+                                     * Save the addressList pointer. This points to the first 
+                                     * IoAddresses entry of this class.  Then update the overall 
+                                     * IoAddresses array counter (TotalIoAddressEntries).
+                                     */
+                                    s_Peripherals[TotalPeripherals+CurrentPeripheral].AddressList = 
+                                        &s_Peripheral_IoAddresses[TotalIoAddressEntries];
+
+                                    TotalIoAddressEntries += CurrentIoAddressNum;
+
+                                    // >-- End of NvOdmIoAddress array processing --<
+                                }
+                            }
+                        }
+                    }
+                }
+                TotalPeripherals += NumPeripherals;
+            }
+        }
+    }
+
+    // Done reading I2C-EEPROM; close it.
+    NvOdmI2cClose(hOdmI2c);
+
+    /** 
+     *  Append static peripheral entries (if any) to dynamic list
+     *  read from EEPROMs (this list may also be empty), except for
+     *  duplicate GUIDs.  The dynamic list takes precedence when
+     *  duplicate entries are found in the static list.
+     */
+    StaticPeripherals = NV_ARRAY_SIZE(s_Peripherals_Default);
+    for (i=0; i<StaticPeripherals; i++)
+    {
+        for (j=0; j<TotalPeripherals; j++)
+        {
+            if (s_Peripherals_Default[i].Guid == s_Peripherals[j].Guid)
+            {
+                IsMatch = NV_TRUE;
+                break;  // Ignore duplicate entry from static list.
+            }
+        }
+        if (IsMatch != NV_TRUE)
+        {
+            // Append unique entry to dynamic list
+
+            s_Peripherals[TotalPeripherals].Guid = 
+                s_Peripherals_Default[i].Guid;
+
+            s_Peripherals[TotalPeripherals].AddressList = 
+                s_Peripherals_Default[i].AddressList;
+
+            s_Peripherals[TotalPeripherals].NumAddress = 
+                s_Peripherals_Default[i].NumAddress;
+
+            s_Peripherals[TotalPeripherals].Class = 
+                s_Peripherals_Default[i].Class;
+
+            // Overwrite DDR IO rail address list for DDR2 board
+            if (s_Peripherals_Default[i].Guid == NV_VDD_DDR_ODM_ID)
+            {
+                NvU32 k;
+                NvOdmBoardInfo BoardInfo;
+                for (k = 0; k < NV_ARRAY_SIZE(s_WhistlerDDR2Boards); k++)
+                {
+                    if (NvOdmPeripheralGetBoardInfo(
+                        s_WhistlerDDR2Boards[k], &BoardInfo))
+                    {
+                        s_Peripherals[TotalPeripherals].AddressList =
+                            s_ffaVddDdr2Addresses;
+                        break;
+                    }
+                }
+            }
+
+            // Overwrite CPU rail address list for board with external DCDC
+            if (s_Peripherals_Default[i].Guid == NV_VDD_CPU_ODM_ID)
+            {
+                if (NvOdmIsCpuExtSupply())
+                {
+                    s_Peripherals[TotalPeripherals].AddressList =
+                        s_ffaCpuExtSupplyAddresses;
+                    NV_ASSERT(s_Peripherals[TotalPeripherals].NumAddress ==
+                              NV_ARRAY_SIZE(s_ffaCpuExtSupplyAddresses));
+                }
+            }
+            TotalPeripherals++;
+        }
+    }
+    *pNum = TotalPeripherals;
+    return NV_TRUE;
+}
+
+static NvBool
+NvOdmPeripheralReadPartNumber(
+    NvOdmServicesI2cHandle hOdmI2c,
+    NvU8 EepromInst,
+    NvOdmBoardInfo *pBoardInfo)
+{
+    NvOdmI2cStatus Error;
+    NvU32 i;
+    NvU8 I2cAddr, Offset;
+    NvU8 ReadBuffer[sizeof(NvOdmBoardInfo)];
+
+    NvOdmOsMemset(ReadBuffer, 0, sizeof(ReadBuffer));  
+
+    // EepromInst*2, since 7-bit addressing
+    I2cAddr = NVODM_QUERY_I2C_EEPROM_ADDRESS + (EepromInst << 1);
+
+    /**
+     * Offset to the board number entry in EEPROM.
+     */
+    Offset = NVODM_QUERY_BOARD_HEADER_START;
+
+    for (i=0; i<sizeof(NvOdmBoardInfo); i++)
+    {
+        Error = NvOdmPeripheralI2cRead8(
+            hOdmI2c, I2cAddr, Offset+i, (NvU8 *)&ReadBuffer[i]);
+        if (Error != NvOdmI2cStatus_Success)
+        {
+            return NV_FALSE;
+        }
+    }
+    NvOdmOsMemcpy(pBoardInfo, &ReadBuffer[0], sizeof(NvOdmBoardInfo));
+    return NV_TRUE;
+}
+
+NvBool
+NvOdmPeripheralGetBoardInfo(
+    NvU16 BoardId,
+    NvOdmBoardInfo *pBoardInfo)
+{
+    NvBool RetVal = NV_FALSE;
+    NvOdmServicesI2cHandle hOdmI2c = NULL;
+    NvU8 BusSegment, EepromInst, CurrentBoard;
+    static NvU8 NumBoards = 0;
+    static NvBool s_ReadBoardInfoDone = NV_FALSE;
+
+    if (!s_ReadBoardInfoDone)
+    {
+        s_ReadBoardInfoDone = NV_TRUE;
+        hOdmI2c = NvOdmI2cOpen(NvOdmIoModule_I2c_Pmu, 0);
+        if (!hOdmI2c)
+        {
+            // Exit
+            pBoardInfo = NULL;
+            return NV_FALSE;
+        }
+
+        for (BusSegment=0; BusSegment < NVODM_QUERY_MAX_BUS_SEGMENTS; BusSegment++)
+        {
+            RetVal = NvOdmPeripheralSetBusSegment(hOdmI2c, BusSegment);
+            if (RetVal == NV_FALSE)
+            {
+                /** 
+                 * Bus segment not found. Set BusSegment to MAX and try reading 
+                 * any ID EEPROMS which might be available without the bus 
+                 * expander. 
+                 */
+                BusSegment = NVODM_QUERY_MAX_BUS_SEGMENTS;
+            }
+
+            for (EepromInst=0; EepromInst < NVODM_QUERY_MAX_EEPROMS; EepromInst++)
+            {
+                RetVal = NvOdmPeripheralReadPartNumber(
+                        hOdmI2c, EepromInst, &s_BoardModuleTable[NumBoards]);
+                if (RetVal == NV_TRUE)
+                    NumBoards++;
+            }
+        }
+        NvOdmI2cClose(hOdmI2c);
+    }
+
+    if (NumBoards)
+    {
+        // Linear search for given BoardId; if found, return entry
+        for (CurrentBoard=0; CurrentBoard < NumBoards; CurrentBoard++)
+        {
+            if (s_BoardModuleTable[CurrentBoard].BoardID == BoardId)
+            {
+                // Match found
+                pBoardInfo->BoardID  = s_BoardModuleTable[CurrentBoard].BoardID;
+                pBoardInfo->SKU      = s_BoardModuleTable[CurrentBoard].SKU;
+                pBoardInfo->Fab      = s_BoardModuleTable[CurrentBoard].Fab;
+                pBoardInfo->Revision = s_BoardModuleTable[CurrentBoard].Revision;
+                return NV_TRUE;
+            }           
+        }
+    }
+
+    // Match not found
+    pBoardInfo = NULL;
+    return NV_FALSE;
+}
+
+// This will compare the peripheral GUID against a list of known-bad GUIDs
+// for certain development kit personalities, and return NV_TRUE if it is
+// known to be unsupported (filtered) on the current configuration
+static NvBool
+NvIsFilteredPeripheral(const NvOdmPeripheralConnectivity* pConnectivity)
+{
+    NvOdmServicesKeyListHandle hKeyList;
+    NvU32 CustOpt = 0;
+    NvU32 Personality = 0;
+    NvU32 opt = 0;
+    NvU32 ril = 0;
+    NvOdmIoModule OdmModule;
+    const NvU32 *OdmConfigs=NULL;
+    NvU32 NumOdmConfigs = 0;
+    const NvOdmPeripheralConnectivity* pFilteredPeriph = pConnectivity;
+    NvOdmBoardInfo BoardInfo;
+    NvU32 i, TotalBoards;
+    NvBool status = NV_FALSE;
+
+    if((!pConnectivity) || (!pConnectivity->NumAddress))
+        return NV_TRUE;
+
+    if (pConnectivity->Guid == NV_ODM_GUID('a','d','t','7','4','6','1',' '))
+    {
+        /**
+         * The following board detection is used to keep thermal rail 
+         * (VOUT15) disabled for certain board SKUs where the board ID 
+         * ROMs cannot be read when the thermal rail is enabled. 
+         */
+        TotalBoards = NV_ARRAY_SIZE(gs_WhistlerProcessorBoards);
+
+        // Scan for processor boards
+        for (i=0; i<TotalBoards; i++)
+        {
+            if ( NvOdmPeripheralGetBoardInfo(gs_WhistlerProcessorBoards[i], &BoardInfo) )
+            {
+                // Found the processor module
+                if (BoardInfo.Fab == PROCESSOR_MODULE_REV_A)
+                {
+                    // Filter out this peripheral for REV_A processor modules
+                    return NV_TRUE;
+                }
+            }
+        }
+    }
+
+    if (pConnectivity->Guid == NV_ODM_GUID('b','l','u','t','o','o','t','h'))
+    {
+        /**
+         * The following board detection is used to detect presence of Bluetooth Chip.
+         * In case of whistler only ossibility is having E951 board.
+         */
+         status = NvOdmPeripheralGetBoardInfo((BOARD_ID_E951), &BoardInfo);
+         if(NV_TRUE == status)
+         {
+              return NV_FALSE; // BT module found; don't filter it.
+         }else
+         {
+              return NV_TRUE; // BT module not found; filter the BT peripheral. 
+         }
+    }
+
+    hKeyList = NvOdmServicesKeyListOpen();
+
+    if (hKeyList)
+    {
+        CustOpt =
+            NvOdmServicesGetKeyValue(hKeyList,
+                                     NvOdmKeyListId_ReservedBctCustomerOption);
+        NvOdmServicesKeyListClose(hKeyList);
+        Personality = 
+            NV_DRF_VAL(TEGRA_DEVKIT, BCT_CUSTOPT, PERSONALITY, CustOpt);
+        opt =
+            NV_DRF_VAL(TEGRA_DEVKIT, BCT_CUSTOPT, DISPLAY_OPTION, CustOpt);
+        ril =
+            NV_DRF_VAL(TEGRA_DEVKIT, BCT_CUSTOPT, RIL, CustOpt);
+    }
+
+    if (pConnectivity->Guid == NV_ODM_GUID('e','m','p',' ','_','m','d','m'))
+    {
+        if (ril == TEGRA_DEVKIT_BCT_CUSTOPT_0_RIL_EMP_RAINBOW)
+        {
+            return NV_FALSE; // EMP RAINBOW supported - don't filter it
+        }
+        else
+        {
+            return NV_TRUE; // EMP RAINBOW not supported - filter it
+        }
+    }
+
+    if (pConnectivity->Guid == NV_ODM_GUID('e','m','p',' ','M','5','7','0'))
+    {
+        if (ril == TEGRA_DEVKIT_BCT_CUSTOPT_0_RIL_EMP_RAINBOW_ULPI)
+        {
+            return NV_FALSE; // EMP RAINBOW ULPI supported - don't filter it
+        }
+        else
+        {
+            return NV_TRUE; // EMP RAINBOW ULPI not supported - filter it
+        }
+    }
+
+    if (pConnectivity->Guid == NV_ODM_GUID('s','p','i',' ','_','i','p','c'))
+    {
+        if (ril == TEGRA_DEVKIT_BCT_CUSTOPT_0_RIL_IFX)
+        {
+            return NV_FALSE; // IFX supported - don't filter it
+        }
+        else
+        {
+            return NV_TRUE; // IFX not supported - filter it
+        }
+    }
+
+
+    if (!Personality)
+        Personality = TEGRA_DEVKIT_DEFAULT_PERSONALITY;
+
+    OdmModule = pFilteredPeriph->AddressList[0].Interface;
+
+    if(OdmModule != NvOdmIoModule_Gpio)
+        NvOdmQueryPinMux(OdmModule, &OdmConfigs, &NumOdmConfigs);
+
+    switch (OdmModule)
+    {
+    case NvOdmIoModule_Gpio:
+        // Filter scroll wheel when trace is enabled
+        if ( (pConnectivity->Guid == NV_ODM_GUID('s','c','r','o','l','w','h','l')) &&
+             ((Personality == TEGRA_DEVKIT_BCT_CUSTOPT_0_PERSONALITY_11) ||
+              (Personality == TEGRA_DEVKIT_BCT_CUSTOPT_0_PERSONALITY_15) ||
+              (Personality == TEGRA_DEVKIT_BCT_CUSTOPT_0_PERSONALITY_C1)) )
+            return NV_TRUE;
+        else
+            return NV_FALSE;
+
+    default:
+        return NV_FALSE;
+    }
+}
+
+static const NvOdmPeripheralConnectivity* 
+NvApGetAllPeripherals (NvU32 *pNum)
+{
+    static NvBool s_AutoDetectDone = NV_FALSE;
+    NvBool RetVal = NV_TRUE;
+    static NvU32 s_TotalPeripherals;
+    NvOdmBoardInfo BoardInfo;
+
+    if (!pNum)
+        return NULL;
+
+    if (!s_AutoDetectDone)
+    {
+        /**
+         *  Read & cache the board ID info from the I2C-EEPROMs.  This
+         *  is necessary because once Whistler's thermal power rail is
+         *  enabled, the ID ROMs cannot be read. NvApGetAllPeripherals()
+         *  is called before that rail is enabled.
+         */
+        NvOdmPeripheralGetBoardInfo(NVODM_QUERY_BOARD_ID_UNKNOWN, &BoardInfo);
+
+        RetVal = NvOdmPeripheralGetEntries(&s_TotalPeripherals);
+        if (RetVal == NV_FALSE)
+        {
+            *pNum = 0;
+            return NULL;
+        }
+        s_AutoDetectDone = NV_TRUE;
+    }
+
+    *pNum = s_TotalPeripherals;
+    return (const NvOdmPeripheralConnectivity *)s_Peripherals;
+}
+
+// This implements a simple linear search across the entire set of currently-
+// connected peripherals to find the set of GUIDs that Match the search
+// criteria.  More clever implementations are possible, but given the
+// relatively small search space (max dozens of peripherals) and the relative
+// infrequency of enumerating peripherals, this is the easiest implementation.
+const NvOdmPeripheralConnectivity *
+NvOdmPeripheralGetGuid(NvU64 SearchGuid)
+{
+    const NvOdmPeripheralConnectivity *pAllPeripherals;
+    NvU32 NumPeripherals;
+    NvU32 i;
+
+    pAllPeripherals = NvApGetAllPeripherals(&NumPeripherals);
+
+    if (!pAllPeripherals || !NumPeripherals)
+        return NULL;
+
+    for (i=0; i<NumPeripherals; i++) 
+    {
+        if (SearchGuid == pAllPeripherals[i].Guid)
+        {
+            if (NvIsFilteredPeripheral(&pAllPeripherals[i]))
+                return NULL;
+            return &pAllPeripherals[i];
+        }
+    }
+
+    return NULL;
+}
+
+static NvBool
+IsBusMatch(
+    const NvOdmPeripheralConnectivity *pPeriph,
+    const NvOdmPeripheralSearch *pSearchAttrs,
+    const NvU32 *pSearchVals,
+    NvU32 offset,
+    NvU32 NumAttrs)
+{
+    NvU32 i, j;
+    NvBool IsMatch = NV_FALSE;
+
+    for (i=0; i<pPeriph->NumAddress; i++)
+    {
+        j = offset;
+        do
+        {
+            switch (pSearchAttrs[j])
+            {
+            case NvOdmPeripheralSearch_IoModule:
+                IsMatch = (pSearchVals[j] ==
+                           (NvU32)(pPeriph->AddressList[i].Interface));
+                break;
+            case NvOdmPeripheralSearch_Address:
+                IsMatch = (pSearchVals[j] == pPeriph->AddressList[i].Address);
+                break;
+            case NvOdmPeripheralSearch_Instance:
+                IsMatch = (pSearchVals[j] == pPeriph->AddressList[i].Instance);
+                break;
+            case NvOdmPeripheralSearch_PeripheralClass:
+            default:
+                NV_ASSERT(!"Bad Query!");
+                break;
+            }
+            j++;
+        } while (IsMatch && j<NumAttrs &&
+                 pSearchAttrs[j]!=NvOdmPeripheralSearch_IoModule);
+
+        if (IsMatch)
+        {
+            return NV_TRUE;
+        }
+    }
+    return NV_FALSE;
+}
+
+static NvBool
+IsPeripheralMatch(
+    const NvOdmPeripheralConnectivity *pPeriph,
+    const NvOdmPeripheralSearch *pSearchAttrs,
+    const NvU32 *pSearchVals,
+    NvU32 NumAttrs)
+{
+    NvU32 i;
+    NvBool IsMatch = NV_TRUE;
+
+    for (i=0; i<NumAttrs && IsMatch; i++)
+    {
+        switch (pSearchAttrs[i])
+        {
+        case NvOdmPeripheralSearch_PeripheralClass:
+            IsMatch = (pSearchVals[i] == (NvU32)(pPeriph->Class));
+            break;
+        case NvOdmPeripheralSearch_IoModule:
+            IsMatch = IsBusMatch(pPeriph, pSearchAttrs, pSearchVals, i, NumAttrs);
+            break;
+        case NvOdmPeripheralSearch_Address:
+        case NvOdmPeripheralSearch_Instance:
+            // In correctly-formed searches, these parameters will be parsed by
+            // IsBusMatch, so we ignore them here.
+            break;
+        default:
+            NV_ASSERT(!"Bad search attribute!");
+            break;
+        }
+    }
+    return IsMatch;
+}
+
+NvU32
+NvOdmPeripheralEnumerate(
+    const NvOdmPeripheralSearch *pSearchAttrs,
+    const NvU32 *pSearchVals,
+    NvU32 NumAttrs,
+    NvU64 *pGuidList,
+    NvU32 NumGuids)
+{
+    const NvOdmPeripheralConnectivity *pAllPeripherals;
+    NvU32 NumPeripherals;
+    NvU32 Matches;
+    NvU32 i;
+
+    pAllPeripherals = NvApGetAllPeripherals(&NumPeripherals);
+
+    if (!pAllPeripherals || !NumPeripherals)
+    {
+        return 0;
+    }
+
+    if (!pSearchAttrs || !pSearchVals)
+    {
+        NumAttrs = 0;
+    }
+
+    for (i=0, Matches=0; i<NumPeripherals &&
+             (Matches < NumGuids || !pGuidList); i++)
+    {
+        if ( !NumAttrs || IsPeripheralMatch(&pAllPeripherals[i],
+                                            pSearchAttrs, pSearchVals,
+                                            NumAttrs) )
+        {
+            if (NvIsFilteredPeripheral(&pAllPeripherals[i]))
+                continue;
+
+            if (pGuidList)
+                pGuidList[Matches] = pAllPeripherals[i].Guid;
+            Matches++;
+        }
+    }
+    return Matches;
+}
+
diff --git a/arch/arm/mach-tegra/odm_kit/query/whistler/nvodm_query_gpio.c b/arch/arm/mach-tegra/odm_kit/query/whistler/nvodm_query_gpio.c
new file mode 100644
index 000000000000..eea1843af763
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/query/whistler/nvodm_query_gpio.c
@@ -0,0 +1,216 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include "nvodm_query_gpio.h"
+#include "nvodm_services.h"
+#include "tegra_devkit_custopt.h"
+#include "nvodm_keylist_reserved.h"
+#include "nvrm_drf.h"
+
+#define NVODM_ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+#define NVODM_PORT(x) ((x) - 'a')
+
+static const NvOdmGpioPinInfo s_vi[] = {
+    {NVODM_PORT('t'), 3, NvOdmGpioPinActiveState_High},
+};
+
+static const NvOdmGpioPinInfo s_display[] = {
+    /* Panel 0 -- sony vga */
+    { NVODM_PORT('m'), 3, NvOdmGpioPinActiveState_Low },
+    { NVODM_PORT('b'), 2, NvOdmGpioPinActiveState_Low },
+    { NVODM_PORT('n'), 4, NvOdmGpioPinActiveState_Low },
+    { NVODM_PORT('j'), 3, NvOdmGpioPinActiveState_Low },
+    { NVODM_PORT('j'), 4, NvOdmGpioPinActiveState_Low },
+    // this pin is not needed for ap15
+    {NVODM_GPIO_INVALID_PORT, NVODM_GPIO_INVALID_PIN,
+        NvOdmGpioPinActiveState_Low},
+
+    /* Panel 1 -- samtek */
+    {NVODM_GPIO_INVALID_PORT, NVODM_GPIO_INVALID_PIN,
+        NvOdmGpioPinActiveState_Low},
+    {NVODM_GPIO_INVALID_PORT, NVODM_GPIO_INVALID_PIN,
+        NvOdmGpioPinActiveState_Low},
+    {NVODM_GPIO_INVALID_PORT, NVODM_GPIO_INVALID_PIN,
+        NvOdmGpioPinActiveState_Low},
+    {NVODM_GPIO_INVALID_PORT, NVODM_GPIO_INVALID_PIN,
+        NvOdmGpioPinActiveState_Low},
+
+    /* Panel 2 -- sharp wvga */
+    { NVODM_PORT('v'), 7, NvOdmGpioPinActiveState_Low },
+
+    /* Panel 3 -- sharp qvga */
+    { NVODM_PORT('n'), 6, NvOdmGpioPinActiveState_High },   // LCD_DC0
+    { NVODM_PORT('n'), 4, NvOdmGpioPinActiveState_Low },    // LCD_CS0
+    { NVODM_PORT('b'), 3, NvOdmGpioPinActiveState_Low },    // LCD_PCLK
+    { NVODM_PORT('b'), 2, NvOdmGpioPinActiveState_Low },    // LCD_PWR0
+    { NVODM_PORT('e'), 0, NvOdmGpioPinActiveState_High },   // LCD_D0
+    { NVODM_PORT('e'), 1, NvOdmGpioPinActiveState_High },   // LCD_D1
+    { NVODM_PORT('e'), 2, NvOdmGpioPinActiveState_High },   // LCD_D2
+    { NVODM_PORT('e'), 3, NvOdmGpioPinActiveState_High },   // LCD_D3
+    { NVODM_PORT('e'), 4, NvOdmGpioPinActiveState_High },   // LCD_D4
+    { NVODM_PORT('e'), 5, NvOdmGpioPinActiveState_High },   // LCD_D5
+    { NVODM_PORT('e'), 6, NvOdmGpioPinActiveState_High },   // LCD_D6
+    { NVODM_PORT('e'), 7, NvOdmGpioPinActiveState_High },   // LCD_D7
+    { NVODM_PORT('f'), 0, NvOdmGpioPinActiveState_High },   // LCD_D8
+    { NVODM_PORT('f'), 1, NvOdmGpioPinActiveState_High },   // LCD_D9
+    { NVODM_PORT('f'), 2, NvOdmGpioPinActiveState_High },   // LCD_D10
+    { NVODM_PORT('f'), 3, NvOdmGpioPinActiveState_High },   // LCD_D11
+    { NVODM_PORT('f'), 4, NvOdmGpioPinActiveState_High },   // LCD_D12
+    { NVODM_PORT('f'), 5, NvOdmGpioPinActiveState_High },   // LCD_D13
+    { NVODM_PORT('f'), 6, NvOdmGpioPinActiveState_High },   // LCD_D14
+    { NVODM_PORT('f'), 7, NvOdmGpioPinActiveState_High },   // LCD_D15
+    { NVODM_PORT('m'), 3, NvOdmGpioPinActiveState_High },   // LCD_D19
+
+     /* Panel 4 -- auo */
+     { NVODM_PORT('v'), 7, NvOdmGpioPinActiveState_Low },
+};
+
+static const NvOdmGpioPinInfo s_Sdio2[] = {
+    {NVODM_PORT('i'), 5, NvOdmGpioPinActiveState_Low},    // Card Detect for SDIO instance 2
+    /* High for WP and low for read/write */
+    {NVODM_PORT('v'), 5, NvOdmGpioPinActiveState_High},    // Write Protect for SDIO instance 2 
+};
+
+static const NvOdmGpioPinInfo s_NandFlash[] = {
+    {NVODM_PORT('c'), 7, NvOdmGpioPinActiveState_High},     // MICRO SD_CD#
+};
+
+static const NvOdmGpioPinInfo s_spi_ethernet[] = {
+    {NVODM_PORT('c'), 1, NvOdmGpioPinActiveState_Low}       // SPI_ENET_IRQ (EMC_INT)
+};
+
+static const NvOdmGpioPinInfo s_ScrollWheel[] = {
+    {NVODM_PORT('q'), 4, NvOdmGpioPinActiveState_Low},  // Scroll wheel -QP1 (terminal  1)
+    {NVODM_PORT('r'), 3, NvOdmGpioPinActiveState_Low},  // Scroll wheel_ONOFF
+    {NVODM_PORT('q'), 5, NvOdmGpioPinActiveState_Low},  // Scroll wheel -SELECT (terminal 3)
+    {NVODM_PORT('q'), 3, NvOdmGpioPinActiveState_Low},  // Scroll wheel -QP2 (terminal  4)
+};
+
+static const NvOdmGpioPinInfo s_ScrollWheel_TraceMode[] = {
+    {NVODM_PORT('r'), 3, NvOdmGpioPinActiveState_Low},  // Scroll wheel_ONOFF
+};
+
+static const NvOdmGpioPinInfo s_Bluetooth[] = {
+    {NVODM_PORT('u'), 0, NvOdmGpioPinActiveState_Low},  // Bluetooth Controls: BT_RST
+};
+
+static const NvOdmGpioPinInfo s_Wlan[] = {
+    {NVODM_PORT('k'), 5, NvOdmGpioPinActiveState_Low},  // WLAN-OFF
+    {NVODM_PORT('k'), 6, NvOdmGpioPinActiveState_Low},  // WLAN-RESET
+};
+
+static const NvOdmGpioPinInfo s_hdmi[] =
+{
+    /* hdmi hot-plug interrupt pin */
+    { NVODM_PORT('n'), 7, NvOdmGpioPinActiveState_High},
+};
+
+const NvOdmGpioPinInfo *NvOdmQueryGpioPinMap(NvOdmGpioPinGroup Group,
+    NvU32 Instance, NvU32 *pCount)
+{
+    NvU32 CustomerOption = 0;
+    NvU32 Personality = 0;
+    NvOdmServicesKeyListHandle hKeyList;
+
+    hKeyList = NvOdmServicesKeyListOpen();
+    if (hKeyList)
+    {
+        CustomerOption = 
+            NvOdmServicesGetKeyValue(hKeyList,
+                                     NvOdmKeyListId_ReservedBctCustomerOption);
+        NvOdmServicesKeyListClose(hKeyList);
+        Personality =
+            NV_DRF_VAL(TEGRA_DEVKIT, BCT_CUSTOPT, PERSONALITY, CustomerOption);
+    }
+
+    if (!Personality)
+        Personality = TEGRA_DEVKIT_DEFAULT_PERSONALITY;
+
+    switch (Group)
+    {
+        case NvOdmGpioPinGroup_Display:
+            *pCount = NVODM_ARRAY_SIZE(s_display);
+            return s_display;
+
+        case NvOdmGpioPinGroup_Sdio:
+            if (Instance == 2)
+            {
+                *pCount = NVODM_ARRAY_SIZE(s_Sdio2);
+                return s_Sdio2;
+            }
+            else
+            {
+                *pCount = 0;
+                return NULL;
+            }
+
+        case NvOdmGpioPinGroup_ScrollWheel:
+            if ((Personality == TEGRA_DEVKIT_BCT_CUSTOPT_0_PERSONALITY_11) ||
+                (Personality == TEGRA_DEVKIT_BCT_CUSTOPT_0_PERSONALITY_15) ||
+                (Personality == TEGRA_DEVKIT_BCT_CUSTOPT_0_PERSONALITY_C1))
+            {
+                *pCount = NVODM_ARRAY_SIZE(s_ScrollWheel_TraceMode);
+                return s_ScrollWheel_TraceMode;
+            }
+            else
+            {
+                *pCount = NVODM_ARRAY_SIZE(s_ScrollWheel);
+                return s_ScrollWheel;
+            }
+
+        case NvOdmGpioPinGroup_NandFlash:
+            *pCount = NVODM_ARRAY_SIZE(s_NandFlash);
+            return s_NandFlash;
+
+        case NvOdmGpioPinGroup_Bluetooth:
+            *pCount = NVODM_ARRAY_SIZE(s_Bluetooth);
+            return s_Bluetooth;
+
+        case NvOdmGpioPinGroup_Wlan:
+            *pCount = NVODM_ARRAY_SIZE(s_Wlan);
+            return s_Wlan;
+
+        case NvOdmGpioPinGroup_SpiEthernet:
+            *pCount = NVODM_ARRAY_SIZE(s_spi_ethernet);
+            return s_spi_ethernet;
+        case NvOdmGpioPinGroup_Vi:
+            *pCount = NVODM_ARRAY_SIZE(s_vi);
+            return s_vi;
+        case NvOdmGpioPinGroup_Hdmi:
+            *pCount = NVODM_ARRAY_SIZE(s_hdmi);
+            return s_hdmi;
+
+        default:
+            *pCount = 0;
+            return NULL;
+    }
+}
diff --git a/arch/arm/mach-tegra/odm_kit/query/whistler/nvodm_query_kbc.c b/arch/arm/mach-tegra/odm_kit/query/whistler/nvodm_query_kbc.c
new file mode 100644
index 000000000000..1781b6f0ed99
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/query/whistler/nvodm_query_kbc.c
@@ -0,0 +1,88 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/**
+ * @file
+ * @brief <b>NVIDIA Driver Development Kit:
+ *                  ODM Kbc interface</b>
+ *
+ */
+
+#include "nvodm_query_kbc.h"
+
+static NvU32 *RowNumbers = NULL;
+static NvU32 *ColNumbers = NULL;
+
+void
+NvOdmKbcGetParameter(
+        NvOdmKbcParameter Param,
+        NvU32 SizeOfValue,
+        void * pValue)
+{
+    NvU32 *pTempVar;
+    switch (Param)
+    {
+        case NvOdmKbcParameter_DebounceTime:
+            pTempVar = (NvU32 *)pValue;
+            *pTempVar = 10;
+            break;
+        case NvOdmKbcParameter_RepeatCycleTime:
+            pTempVar = (NvU32 *)pValue;
+            *pTempVar = 32;
+            break;
+        default:
+            break;
+    }
+}
+
+NvU32 
+NvOdmKbcGetKeyCode(
+    NvU32 Row, 
+    NvU32 Column,
+    NvU32 RowCount,
+    NvU32 ColumnCount)
+{
+    return ((Row * ColumnCount) + Column);
+}
+
+NvBool
+NvOdmKbcIsSelectKeysWkUpEnabled(
+    NvU32 **pRowNumber,
+    NvU32 **pColNumber,
+    NvU32 *NumOfKeys)
+{
+    *pRowNumber = RowNumbers;
+    *pColNumber = ColNumbers;
+    *NumOfKeys = 0;
+    return NV_FALSE;
+}
+
diff --git a/arch/arm/mach-tegra/odm_kit/query/whistler/nvodm_query_kbc_gpio_def.h b/arch/arm/mach-tegra/odm_kit/query/whistler/nvodm_query_kbc_gpio_def.h
new file mode 100644
index 000000000000..40b0664eeee1
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/query/whistler/nvodm_query_kbc_gpio_def.h
@@ -0,0 +1,74 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/**
+ * @file
+ * <b>NVIDIA APX ODM Kit::
+ *         The KBC GPIO pin definitions</b>
+ *
+ * @b Description: Define the KBC GPIO pins in row and column numbers.
+ */
+
+#ifndef NVODM_QUERY_KBC_GPIO_DEF_H
+#define NVODM_QUERY_KBC_GPIO_DEF_H
+
+typedef enum
+{
+    NvOdmKbcGpioPin_KBRow0 = 0,
+    NvOdmKbcGpioPin_KBRow1,
+    NvOdmKbcGpioPin_KBRow2,
+    NvOdmKbcGpioPin_KBRow3,
+    NvOdmKbcGpioPin_KBRow4,
+    NvOdmKbcGpioPin_KBRow5,
+    NvOdmKbcGpioPin_KBRow6,
+    NvOdmKbcGpioPin_KBRow7,
+    NvOdmKbcGpioPin_KBRow8,
+    NvOdmKbcGpioPin_KBRow9,
+    NvOdmKbcGpioPin_KBRow10,
+    NvOdmKbcGpioPin_KBRow11,
+    NvOdmKbcGpioPin_KBRow12,
+    NvOdmKbcGpioPin_KBRow13,
+    NvOdmKbcGpioPin_KBRow14,
+    NvOdmKbcGpioPin_KBRow15,
+    NvOdmKbcGpioPin_KBCol0,
+    NvOdmKbcGpioPin_KBCol1,
+    NvOdmKbcGpioPin_KBCol2,
+    NvOdmKbcGpioPin_KBCol3,
+    NvOdmKbcGpioPin_KBCol4,
+    NvOdmKbcGpioPin_KBCol5,
+    NvOdmKbcGpioPin_KBCol6,
+    NvOdmKbcGpioPin_KBCol7,
+    NvOdmKbcGpioPin_Num,
+    NvOdmKbcGpioPin_Force32 = 0x7FFFFFFF
+}NvOdmKbcGpioPin;
+
+#endif // NVODM_QUERY_KBC_GPIO_DEF_H
diff --git a/arch/arm/mach-tegra/odm_kit/query/whistler/nvodm_query_nand.c b/arch/arm/mach-tegra/odm_kit/query/whistler/nvodm_query_nand.c
new file mode 100644
index 000000000000..1b7519c77434
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/query/whistler/nvodm_query_nand.c
@@ -0,0 +1,254 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/**
+ * @file
+ * @brief <b>NVIDIA Driver Development Kit:
+ *                  ODM Uart interface</b>
+ *
+ * @b Description: Implements the ODM for the Uart communication.
+ *
+ */
+
+#include "nvodm_query_nand.h"
+#include "nvcommon.h"
+
+// fill params for all required nand flashes here.
+// this list will end when vendor id and chipd id will be zero.
+// hence, all supported chips should be listed before that.
+NvOdmNandFlashParams g_Params[] =
+{
+    /*
+    {
+        VendorId, DeviceId, NandType, IsCopyBackCommandSupported, IsCacheWriteSupported, CapacityInMB, ZonesPerDevice,
+        BlocksPerZone, OperationSuccessStatus, InterleaveCapability, EccAlgorithm,
+        ErrorsCorrectable, SkippedSpareBytes,
+        TRP, TRH (TREH), TWP, TWH, TCS, TWHR, TWB, TREA, TADL,
+        TCLS, TCLH, TCH, TALS, TALH, TRC, TWC, TCR(TCLR), TAR, TRR, NandDeviceType, ReadIdFourthByte
+    }
+    Note :
+    TADL values for flashes K9F1G08Q0M, K9F1G08U0M, TH58NVG4D4CTG00,
+    TH58NVG3D4BTG00, TH58NVG2S3BFT00 is not available from their data sheets.
+    Hence TADL is computed as
+        tADL = (tALH + tALS + tWP).
+    */
+    // filling odm parameter structure for Samsung K9K8G08U0M
+    {
+        0xEC, 0xD3, NvOdmNandFlashType_Slc, NV_TRUE, NV_FALSE, 1024, 4,
+        2048, 0x40, SINGLE_PLANE, NvOdmNandECCAlgorithm_ReedSolomon,
+        NvOdmNandNumberOfCorrectableSymbolErrors_Four, NvOdmNandSkipSpareBytes_4,
+        15, 10, 15, 10, 20, 60, 100, 26, 70,
+        12, 5, 5, 12, 5, 25, 25, 10, 10, 20, NvOdmNandDeviceType_Type1, 0x95
+     },
+    // filling odm parameter structure for Samsung K9W8G08U1M
+    {
+        0xEC, 0xDC, NvOdmNandFlashType_Slc, NV_TRUE, NV_TRUE, 1024, 2,
+        4096, 0x60, SINGLE_PLANE, NvOdmNandECCAlgorithm_ReedSolomon,
+        NvOdmNandNumberOfCorrectableSymbolErrors_Four, NvOdmNandSkipSpareBytes_4,
+        15, 10, 15, 10, 15, 60, 100, 18, 100,
+        10, 5, 5, 10, 5, 30, 30, 10, 10, 20, NvOdmNandDeviceType_Type1, 0x15
+    },
+    // filling odm parameter structure for Samsung K9F1G08Q0M
+    {
+        0xEC, 0xA1, NvOdmNandFlashType_Slc, NV_TRUE, NV_TRUE, 128, 1,
+        1024, 0x60, SINGLE_PLANE, NvOdmNandECCAlgorithm_ReedSolomon,
+        NvOdmNandNumberOfCorrectableSymbolErrors_Four, NvOdmNandSkipSpareBytes_4,
+        60, 20, 60, 20, 0, 60, 100, 60, 70,
+        0, 10, 10, 0, 10, 80, 80, 10, 10, 20, NvOdmNandDeviceType_Type1, 0x15
+    },
+    // filling odm parameter structure for Samsung K9F1G08U0M
+    {
+        0xEC, 0xF1, NvOdmNandFlashType_Slc, NV_TRUE, NV_TRUE, 128, 1,
+        1024, 0x40, SINGLE_PLANE, NvOdmNandECCAlgorithm_ReedSolomon,
+        NvOdmNandNumberOfCorrectableSymbolErrors_Four, NvOdmNandSkipSpareBytes_4,
+        25, 15, 25, 15, 0, 60, 100, 30, 35,
+        0, 10, 10, 0, 10, 50, 45, 10, 10, 20, NvOdmNandDeviceType_Type1, 0x15
+     },
+    // filling odm parameter structure for Samsung K9L8G08U0M
+    {
+        0xEC, 0xD3, NvOdmNandFlashType_Mlc, NV_FALSE, NV_FALSE, 1024, 4,
+        1024, 0x40, SINGLE_PLANE, NvOdmNandECCAlgorithm_ReedSolomon,
+        NvOdmNandNumberOfCorrectableSymbolErrors_Four, NvOdmNandSkipSpareBytes_4,
+        15, 10, 15, 10, 20, 60, 100, 20, 35,
+        15, 5, 5, 15, 5, 30, 30, 10, 10, 20, NvOdmNandDeviceType_Type1, 0x25
+     },
+    // filling odm parameter structure for Samsung K9G4G08U0M
+    {
+        0xEC, 0xDC, NvOdmNandFlashType_Mlc, NV_FALSE, NV_FALSE, 512, 2,
+        1024, 0x40, SINGLE_PLANE, NvOdmNandECCAlgorithm_ReedSolomon,
+        NvOdmNandNumberOfCorrectableSymbolErrors_Four, NvOdmNandSkipSpareBytes_4,
+        15, 10, 15, 15, 15, 60, 100, 18, 50,
+        10, 5, 5, 10, 5, 30, 45, 10, 10, 20, NvOdmNandDeviceType_Type1, 0x25
+     },
+    // filling odm parameter structure for Samsung K5E2G1GACM
+    {
+        0xEC, 0xAA, NvOdmNandFlashType_Slc, NV_TRUE, NV_FALSE, 256, 2,
+        1024, 0x40, SINGLE_PLANE, NvOdmNandECCAlgorithm_ReedSolomon,
+        NvOdmNandNumberOfCorrectableSymbolErrors_Four, NvOdmNandSkipSpareBytes_4,
+        21, 15, 21, 15, 31, 60, 100, 30, 100,
+        21, 5, 5, 21, 5, 42, 42, 10, 10, 20, NvOdmNandDeviceType_Type1, 0x15
+     },
+/*
+    // filling odm parameter structure for Toshiba TH58NVG4D4CTG00
+    {
+        0x98, 0xD5, NvOdmNandFlashType_Mlc, NV_FALSE, NV_FALSE, 2048, 1,
+        8192, 0x40, SINGLE_PLANE, NvOdmNandECCAlgorithm_ReedSolomon,
+        NvOdmNandNumberOfCorrectableSymbolErrors_Four, NvOdmNandSkipSpareBytes_4,
+        41, 15, 15, 10, 0, 30, 20, 200, 41, 21,
+        0, 6, 6, 0, 6, NvOdmNandDeviceType_Type1, 0x25
+    },
+    // filling odm parameter structure for Toshiba TH58NVG3D4BTG00
+    {
+        0x98, 0xD3, NvOdmNandFlashType_Mlc, NV_FALSE, NV_TRUE, 1024, 1,
+        4096, 0x60, SINGLE_PLANE, NvOdmNandECCAlgorithm_ReedSolomon,
+        NvOdmNandNumberOfCorrectableSymbolErrors_Four, NvOdmNandSkipSpareBytes_4,
+        41, 15, 15, 10, 0, 30, 20, 200, 41, 35,
+        0, 10, 10, 0, 10, NvOdmNandDeviceType_Type1, 0x25
+     },
+    // filling odm parameter structure for Toshiba TH58NVG2S3BFT00
+    {
+        0x98, 0xDC, NvOdmNandFlashType_Slc, NV_FALSE, NV_FALSE, 512, 1,
+        1024, 0x60, SINGLE_PLANE, NvOdmNandECCAlgorithm_ReedSolomon,
+        NvOdmNandNumberOfCorrectableSymbolErrors_Four, NvOdmNandSkipSpareBytes_4,
+        41, 15, 15, 10, 0, 30, 20, 200, 41, 35,
+        0, 10, 10, 0, 10, NvOdmNandDeviceType_Type1, 0x25
+     },
+*/
+    // filling odm parameter structure for Samsung K9LBG08U0M
+    {
+        0xEC, 0xD7, NvOdmNandFlashType_Mlc, NV_TRUE, NV_FALSE, 4096, 4, 2048,
+        0x40, SINGLE_PLANE, NvOdmNandECCAlgorithm_ReedSolomon,
+        NvOdmNandNumberOfCorrectableSymbolErrors_Four, NvOdmNandSkipSpareBytes_4,
+        12, 10, 12, 10, 20, 60, 100, 20, 100,
+        12, 5, 5, 12, 5, 25, 25, 10, 10, 20, NvOdmNandDeviceType_Type1, 0xB6
+    },
+    // filling odm parameter structure for Samsung K9LBG08U0D - 42 nm Nand
+    {
+        0xEC, 0xD7, NvOdmNandFlashType_Mlc, NV_TRUE, NV_FALSE, 4096, 4, 2048,
+        0x40, SINGLE_PLANE, NvOdmNandECCAlgorithm_ReedSolomon,
+        NvOdmNandNumberOfCorrectableSymbolErrors_Eight, NvOdmNandSkipSpareBytes_4,
+        15, 10, 15, 10, 20, 60, 100, 20, 100,
+        15, 5, 5, 15, 5, 30, 30, 10, 10, 20, NvOdmNandDeviceType_Type2, 0x29
+    },
+    //Hynix H8BES0UQ0MCR 
+     {
+        0xAD, 0xBC,  NvOdmNandFlashType_Slc, NV_TRUE, NV_FALSE, 512, 2, 2048,
+        0x40, SINGLE_PLANE, NvOdmNandECCAlgorithm_ReedSolomon, 
+        NvOdmNandNumberOfCorrectableSymbolErrors_Four, NvOdmNandSkipSpareBytes_4, 
+        25, 10, 25, 15, 35, 60, 100, 30, 100,
+        25, 10, 10, 25, 10, 45, 45, 10, 10, 20, NvOdmNandDeviceType_Type1, 0x55
+     },
+     //Hynix H8BCS0SJ0MCP 
+    {
+        0xAD, 0xBA, NvOdmNandFlashType_Slc, NV_TRUE, NV_FALSE, 256, 1, 2048, 
+        0x60, SINGLE_PLANE, NvOdmNandECCAlgorithm_ReedSolomon, 
+        NvOdmNandNumberOfCorrectableSymbolErrors_Four, NvOdmNandSkipSpareBytes_4, 
+        25, 15, 25, 15, 35, 60, 100, 30, 100,
+        25, 10, 10, 25, 10, 45, 45, 10, 10, 25, NvOdmNandDeviceType_Type1, 0x55
+     },
+     //Hynix H8BCS0RJ0MCP 
+    {
+        0xAD, 0xAA, NvOdmNandFlashType_Slc, NV_TRUE, NV_FALSE, 256, 1, 2048, 
+        0x60, SINGLE_PLANE, NvOdmNandECCAlgorithm_ReedSolomon, 
+        NvOdmNandNumberOfCorrectableSymbolErrors_Four, NvOdmNandSkipSpareBytes_4, 
+        25, 10, 25, 15, 35, 60, 100, 30, 100,
+        25, 10, 10, 25, 10, 45, 45, 10, 10, 25, NvOdmNandDeviceType_Type1, 0x15
+     },
+     /*Numonyx MCP - NAND02GR3B2D*/ 
+    {
+        0x20, 0xAA, NvOdmNandFlashType_Slc, NV_TRUE, NV_FALSE, 256, 1, 
+        2048, 0x40, SINGLE_PLANE, NvOdmNandECCAlgorithm_ReedSolomon, 
+        NvOdmNandNumberOfCorrectableSymbolErrors_Four, NvOdmNandSkipSpareBytes_4,
+        25, 15, 25, 15, 35, 60, 100, 30, 100,
+        25, 10, 10, 25, 10, 45, 45, 10, 10, 25, NvOdmNandDeviceType_Type1, 0x15
+     },
+    // Micron ONFI 16 Bit Nand MT29F2G16ABD
+    {
+        0x2C, 0xBA, NvOdmNandFlashType_Slc, NV_FALSE, NV_FALSE, 256, 1, 2048, 
+        0x60, SINGLE_PLANE, NvOdmNandECCAlgorithm_ReedSolomon, 
+        NvOdmNandNumberOfCorrectableSymbolErrors_Four, NvOdmNandSkipSpareBytes_4, 
+        12, 10, 17, 15, 24, 60, 100, 20, 100,
+        15, 5, 4, 15, 4, 25, 35, 10, 10, 20, NvOdmNandDeviceType_Type1, 0x55
+    },
+    /* "This is the end of device list please do not modify this. To add support for more flash parts,
+        add device category for those parts before this element"*/
+    {
+        0, 0, NvOdmNandFlashType_UnKnown, NV_FALSE, NV_FALSE, 0, 0,
+        0, 0, SINGLE_PLANE, NvOdmNandECCAlgorithm_ReedSolomon,
+        NvOdmNandNumberOfCorrectableSymbolErrors_Four, NvOdmNandSkipSpareBytes_4,
+        0, 0, 0, 0, 0, 0, 0, 0, 0,
+        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, NvOdmNandDeviceType_Type1, 0
+    }
+};
+
+NvOdmNandFlashParams *NvOdmNandGetFlashInfo (NvU32 ReadID)
+{
+    NvU8 TempValue;
+    NvU8 VendorId = 0;
+    NvU8 DeviceId = 0;
+    NvU8 ReadIdFourthByte = 0;
+    NvOdmNandFlashType NandType;
+    NvU8 i = 0;
+    // To extract Vendor Id
+    VendorId = (NvU8) (ReadID & 0xFF);
+    // To extract Device Id
+    DeviceId = (NvU8) ((ReadID >> DEVICE_SHIFT) & 0xFF);
+    // To extract Fourth ID byte of Read ID - for checking if the flash is 42nm.
+    ReadIdFourthByte = (NvU8) ((ReadID >> FOURTH_ID_SHIFT) & 0xFF);
+    // To extract device Type Mask
+    TempValue = (NvU8) ((ReadID >> FLASH_TYPE_SHIFT) & 0xC);
+    if (TempValue)
+    {
+        NandType = NvOdmNandFlashType_Mlc;
+    }
+    else
+    {
+        NandType = NvOdmNandFlashType_Slc;
+    }
+    // following ORing is done to check if we reached the end of the list.
+    while ((g_Params[i].VendorId) | (g_Params[i].DeviceId))
+    {
+        if ((g_Params[i].VendorId == VendorId) &&
+            (g_Params[i].DeviceId == DeviceId) &&
+            (g_Params[i].ReadIdFourthByte == ReadIdFourthByte) &&
+            (g_Params[i].NandType == NandType))
+        {
+            return &g_Params[i];
+        }
+        else
+            i++;
+    }
+    // This condition will be reached if "g_Params" is not having Parameters of the flash used.
+    // Hence add the parameters required in the table.
+    return NULL;
+}
+
diff --git a/arch/arm/mach-tegra/odm_kit/query/whistler/nvodm_query_pinmux.c b/arch/arm/mach-tegra/odm_kit/query/whistler/nvodm_query_pinmux.c
new file mode 100644
index 000000000000..1e9aeef4e584
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/query/whistler/nvodm_query_pinmux.c
@@ -0,0 +1,482 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/*
+ * This file implements the pin-mux configuration tables for each I/O module.
+ */
+
+// THESE SETTINGS ARE PLATFORM-SPECIFIC (not SOC-specific).
+// PLATFORM = AP20 Whistler/Voyager
+
+#include "nvodm_query_pinmux.h"
+#include "nvassert.h"
+#include "nvodm_services.h"
+#include "tegra_devkit_custopt.h"
+#include "nvodm_keylist_reserved.h"
+#include "nvrm_drf.h"
+
+#define NVODM_PINMUX_ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+
+static const NvU32 s_NvOdmPinMuxConfig_Uart_Hsi_Ulpi[] = {
+    NvOdmUartPinMap_Config7,    // Instance 0: UART-A is mapped to SDIO1 pins when ULPI is used
+    NvOdmUartPinMap_Config1,    // Instance 1: UART-B
+    NvOdmUartPinMap_Config1,    // Instance 2: UART-C
+    0, // UART-D function disabled: pins used by BB (SPI1)
+    0, // UART-E function disabled: pins used by WiFi (SDIO1)
+};
+
+
+static const NvU32 s_NvOdmPinMuxConfig_Uart[] = {
+    NvOdmUartPinMap_Config1,
+    NvOdmUartPinMap_Config1,
+    NvOdmUartPinMap_Config1,
+    0, // UART-D function disabled: pins used by BB (SPI1)
+    0, // UART-E function disabled: pins used by WiFi (SDIO1)
+};
+
+static const NvU32 s_NvOdmPinMuxConfig_Spi[] = {
+    NvOdmSpiPinMap_Config1,
+    NvOdmSpiPinMap_Config3,
+    NvOdmSpiPinMap_Multiplexed,
+    0,
+    0,
+};
+
+static const NvU32 s_NvOdmPinMuxConfig_Twc[] = {
+    0,
+};
+
+static const NvU32 s_NvOdmPinMuxConfig_I2c[] = {
+    NvOdmI2cPinMap_Config1,
+    NvOdmI2cPinMap_Config1,
+    NvOdmI2cPinMap_Config1,
+};
+
+static const NvU32 s_NvOdmPinMuxConfig_I2c_Pmu[] = {
+    NvOdmI2cPmuPinMap_Config1,
+};
+
+static const NvU32 s_NvOdmPinMuxConfig_Ulpi[] = {
+    NvOdmUlpiPinMap_Config1,
+};
+
+static const NvU32 s_NvOdmPinMuxConfig_Sdio[] = {
+    0,
+    NvOdmSdioPinMap_Config1,    /* Wifi */
+    NvOdmSdioPinMap_Config1,
+    NvOdmSdioPinMap_Config2,    // NAND enabled
+};
+
+static const NvU32 s_NvOdmPinMuxConfig_Sdio_05[] = {
+    0,
+    NvOdmSdioPinMap_Config1,    /* Wifi */
+    NvOdmSdioPinMap_Config1,
+    NvOdmSdioPinMap_Config1,    // Personality 5 uses SDIO (disables NAND)
+};
+
+static const NvU32 s_NvOdmPinMuxConfig_Spdif[] = {
+    0,
+};
+
+static const NvU32 s_NvOdmPinMuxConfig_Hsi[] = {
+    0,
+};
+
+static const NvU32 s_NvOdmPinMuxConfig_Hdmi[] = {
+    NvOdmHdmiPinMap_Config1,
+};
+
+static const NvU32 s_NvOdmPinMuxConfig_Pwm[] = {
+    0,
+};
+
+static const NvU32 s_NvOdmPinMuxConfig_Ata[] = {
+    0,
+};
+
+static const NvU32 s_NvOdmPinMuxConfig_Nand[] = {
+    NvOdmNandPinMap_Config2, // disable sdio4 pinmux for enabling nand
+};
+
+static const NvU32 s_NvOdmPinMuxConfig_Nand_05[] = {
+    0, // Personality 5 disables NAND
+};
+
+static const NvU32 s_NvOdmPinMuxConfig_Dsi[] = {
+    NvOdmDapPinMap_Config1, // fake one, otherwise, ddk display will assert.
+};
+
+static const NvU32 s_NvOdmPinMuxConfig_Dap[] = {
+    NvOdmDapPinMap_Config1,
+    NvOdmDapPinMap_Config1,
+    NvOdmDapPinMap_Config1,
+    NvOdmDapPinMap_Config1,
+    NvOdmDapPinMap_Config1,
+};
+
+static const NvU32 s_NvOdmPinMuxConfig_Kbd[] = {
+    NvOdmKbdPinMap_Config4,
+};
+
+static const NvU32 s_NvOdmPinMuxConfig_Hdcp[] = {
+    NvOdmHdcpPinMap_Config1,
+};
+
+static const NvU32 s_NvOdmPinMuxConfig_SyncNor[] = {
+    0,
+};
+
+static const NvU32 s_NvOdmPinMuxConfig_Mio[] = {
+    0,
+};
+
+static const NvU32 s_NvOdmPinMuxConfig_ExternalClock[] = {
+    NvOdmExternalClockPinMap_Config2,
+    NvOdmExternalClockPinMap_Config2,
+    NvOdmExternalClockPinMap_Config1, // CSUS -> VI_Sensor_CLK
+};
+
+static const NvU32 s_NvOdmPinMuxConfig_VideoInput[] = {
+    NvOdmVideoInputPinMap_Config2,
+};
+
+static const NvU32 s_NvOdmPinMuxConfig_Display[] = {
+    NvOdmDisplayPinMap_Config1,
+    0,
+};
+
+static const NvU32 s_NvOdmPinMuxConfig_BacklightPwm[] = {
+    0,
+    NvOdmBacklightPwmPinMap_Config1,
+};
+
+static const NvU32 s_NvOdmPinMuxConfig_Crt[] = {
+    NvOdmDisplayPinMap_Config1,
+    0,
+};
+
+static const NvU32 s_NvOdmPinMuxConfig_Tvo[] = {
+    NvOdmTvoPinMap_Config1, // FIXME: is this the correct config?
+};
+
+static const NvU32 s_NvOdmPinMuxConfig_OneWire[] = {
+    NvOdmOneWirePinMap_Config1,
+};
+
+static const NvU32 s_NvOdmPinMuxConfig_PciExpress[] = {
+    0, // To enable Pcie, set pinmux config for SDIO3 to 0
+};
+
+static const NvU32 s_NvOdmClockLimit_Sdio[] = {
+    50000,
+    32000,
+    50000,
+    50000,
+};
+
+static const NvU32 s_NvOdmPinMuxConfig_Ptm[] = {
+    NvOdmPtmPinMap_Config1,
+};
+
+void
+NvOdmQueryPinMux(
+    NvOdmIoModule IoModule,
+    const NvU32 **pPinMuxConfigTable,
+    NvU32 *pCount)
+{
+    NvU32 CustomerOption = 0;
+    NvU32 Personality = 0;
+    NvU32 Ril = 0;
+    NvOdmServicesKeyListHandle hKeyList;
+
+    hKeyList = NvOdmServicesKeyListOpen();
+    if (hKeyList)
+    {
+        CustomerOption =
+            NvOdmServicesGetKeyValue(hKeyList,
+                                     NvOdmKeyListId_ReservedBctCustomerOption);
+        NvOdmServicesKeyListClose(hKeyList);
+        Personality =
+            NV_DRF_VAL(TEGRA_DEVKIT, BCT_CUSTOPT, PERSONALITY, CustomerOption);
+	Ril =
+            NV_DRF_VAL(TEGRA_DEVKIT, BCT_CUSTOPT, RIL, CustomerOption);
+    }
+
+    if (!Personality)
+        Personality = TEGRA_DEVKIT_DEFAULT_PERSONALITY;
+
+    if (!Ril)
+        Ril = TEGRA_DEVKIT_BCT_CUSTOPT_0_RIL_DEFAULT;
+
+    switch (IoModule)
+    {
+    case NvOdmIoModule_Display:
+        *pPinMuxConfigTable = s_NvOdmPinMuxConfig_Display;
+        *pCount = NV_ARRAY_SIZE(s_NvOdmPinMuxConfig_Display);
+        break;
+
+    case NvOdmIoModule_Dap:
+        *pPinMuxConfigTable = s_NvOdmPinMuxConfig_Dap;
+        *pCount = NV_ARRAY_SIZE(s_NvOdmPinMuxConfig_Dap);
+        break;
+
+    case NvOdmIoModule_Hdcp:
+        *pPinMuxConfigTable = s_NvOdmPinMuxConfig_Hdcp;
+        *pCount = NV_ARRAY_SIZE(s_NvOdmPinMuxConfig_Hdcp);
+        break;
+
+    case NvOdmIoModule_Hdmi:
+        *pPinMuxConfigTable = s_NvOdmPinMuxConfig_Hdmi;
+        *pCount = NV_ARRAY_SIZE(s_NvOdmPinMuxConfig_Hdmi);
+        break;
+
+    case NvOdmIoModule_I2c:
+        *pPinMuxConfigTable = s_NvOdmPinMuxConfig_I2c;
+        *pCount = NV_ARRAY_SIZE(s_NvOdmPinMuxConfig_I2c);
+        break;
+
+    case NvOdmIoModule_I2c_Pmu:
+        *pPinMuxConfigTable = s_NvOdmPinMuxConfig_I2c_Pmu;
+        *pCount = NV_ARRAY_SIZE(s_NvOdmPinMuxConfig_I2c_Pmu);
+        break;
+
+    case NvOdmIoModule_Kbd:
+        if ((Personality == TEGRA_DEVKIT_BCT_CUSTOPT_0_PERSONALITY_11) ||
+            (Personality == TEGRA_DEVKIT_BCT_CUSTOPT_0_PERSONALITY_15) ||
+            (Personality == TEGRA_DEVKIT_BCT_CUSTOPT_0_PERSONALITY_C1))
+        {
+            // Disable KBD pin-mux when PTM trace enabled (shares kbcc pin-group)
+            *pPinMuxConfigTable = NULL;
+            *pCount = 0;
+        }
+        else
+        {
+            *pPinMuxConfigTable = s_NvOdmPinMuxConfig_Kbd;
+            *pCount = NV_ARRAY_SIZE(s_NvOdmPinMuxConfig_Kbd);
+        }
+        break;
+
+    case NvOdmIoModule_Mio:
+        *pPinMuxConfigTable = s_NvOdmPinMuxConfig_Mio;
+        *pCount = NV_ARRAY_SIZE(s_NvOdmPinMuxConfig_Mio);
+        break;
+
+    case NvOdmIoModule_Nand:
+        if ((Personality == TEGRA_DEVKIT_BCT_CUSTOPT_0_PERSONALITY_05) ||
+            (Personality == TEGRA_DEVKIT_BCT_CUSTOPT_0_PERSONALITY_15))
+        {
+            *pPinMuxConfigTable = s_NvOdmPinMuxConfig_Nand_05;
+            *pCount = NV_ARRAY_SIZE(s_NvOdmPinMuxConfig_Nand_05);
+        }
+        else
+        {
+            *pPinMuxConfigTable = s_NvOdmPinMuxConfig_Nand;
+            *pCount = NV_ARRAY_SIZE(s_NvOdmPinMuxConfig_Nand);
+        }
+        break;
+
+    case NvOdmIoModule_Sdio:
+        if ((Personality == TEGRA_DEVKIT_BCT_CUSTOPT_0_PERSONALITY_05) ||
+            (Personality == TEGRA_DEVKIT_BCT_CUSTOPT_0_PERSONALITY_15) ||
+            (Personality == TEGRA_DEVKIT_BCT_CUSTOPT_0_PERSONALITY_C4))
+        {
+            *pPinMuxConfigTable = s_NvOdmPinMuxConfig_Sdio_05;
+            *pCount = NV_ARRAY_SIZE(s_NvOdmPinMuxConfig_Sdio_05);
+        }
+        else
+        {
+            *pPinMuxConfigTable = s_NvOdmPinMuxConfig_Sdio;
+            *pCount = NV_ARRAY_SIZE(s_NvOdmPinMuxConfig_Sdio);
+        }
+        break;
+
+    case NvOdmIoModule_Spdif:
+        *pPinMuxConfigTable = s_NvOdmPinMuxConfig_Spdif;
+        *pCount = NV_ARRAY_SIZE(s_NvOdmPinMuxConfig_Spdif);
+        break;
+
+    case NvOdmIoModule_Spi:
+        *pPinMuxConfigTable = s_NvOdmPinMuxConfig_Spi;
+        *pCount = NV_ARRAY_SIZE(s_NvOdmPinMuxConfig_Spi);
+        break;
+
+    case NvOdmIoModule_Uart:
+        if (Ril == TEGRA_DEVKIT_BCT_CUSTOPT_0_RIL_EMP_RAINBOW_ULPI)
+        {
+            *pPinMuxConfigTable = s_NvOdmPinMuxConfig_Uart_Hsi_Ulpi;
+            *pCount = NV_ARRAY_SIZE(s_NvOdmPinMuxConfig_Uart_Hsi_Ulpi);
+        }
+        else
+        {
+            *pPinMuxConfigTable = s_NvOdmPinMuxConfig_Uart;
+            *pCount = NV_ARRAY_SIZE(s_NvOdmPinMuxConfig_Uart);
+        }
+        break;
+
+    case NvOdmIoModule_ExternalClock:
+        *pPinMuxConfigTable = s_NvOdmPinMuxConfig_ExternalClock;
+        *pCount = NV_ARRAY_SIZE(s_NvOdmPinMuxConfig_ExternalClock);
+        break;
+
+    case NvOdmIoModule_VideoInput:
+        *pPinMuxConfigTable = s_NvOdmPinMuxConfig_VideoInput;
+        *pCount = NV_ARRAY_SIZE(s_NvOdmPinMuxConfig_VideoInput);
+        break;
+
+    case NvOdmIoModule_Crt:
+        *pPinMuxConfigTable = s_NvOdmPinMuxConfig_Crt;
+        *pCount = NV_ARRAY_SIZE(s_NvOdmPinMuxConfig_Crt);
+        break;
+
+    case NvOdmIoModule_Tvo:
+        *pPinMuxConfigTable = s_NvOdmPinMuxConfig_Tvo;
+        *pCount = NV_ARRAY_SIZE(s_NvOdmPinMuxConfig_Tvo);
+        break;
+
+    case NvOdmIoModule_Ata:
+        *pPinMuxConfigTable = s_NvOdmPinMuxConfig_Ata;
+        *pCount = NV_ARRAY_SIZE(s_NvOdmPinMuxConfig_Ata);
+        break;
+
+    case NvOdmIoModule_Pwm:
+        *pPinMuxConfigTable = s_NvOdmPinMuxConfig_Pwm;
+        *pCount = NV_ARRAY_SIZE(s_NvOdmPinMuxConfig_Pwm);
+        break;
+
+    case NvOdmIoModule_Dsi:
+        *pPinMuxConfigTable = s_NvOdmPinMuxConfig_Dsi;
+        *pCount = NV_ARRAY_SIZE(s_NvOdmPinMuxConfig_Dsi);
+        break;
+
+    case NvOdmIoModule_Hsi:
+        *pPinMuxConfigTable = s_NvOdmPinMuxConfig_Hsi;
+        *pCount = NV_ARRAY_SIZE(s_NvOdmPinMuxConfig_Hsi);
+        break;
+
+    case NvOdmIoModule_Twc:
+        *pPinMuxConfigTable = s_NvOdmPinMuxConfig_Twc;
+        *pCount = NV_ARRAY_SIZE(s_NvOdmPinMuxConfig_Twc);
+        break;
+
+    case NvOdmIoModule_Ulpi:
+        if (Ril == TEGRA_DEVKIT_BCT_CUSTOPT_0_RIL_EMP_RAINBOW_ULPI)
+        {
+            *pPinMuxConfigTable = s_NvOdmPinMuxConfig_Ulpi;
+            *pCount = NV_ARRAY_SIZE(s_NvOdmPinMuxConfig_Ulpi);
+        }
+        else
+        {
+            *pPinMuxConfigTable = NULL;
+            *pCount = 0;
+        }
+        break;
+
+    case NvOdmIoModule_OneWire:
+        *pPinMuxConfigTable = s_NvOdmPinMuxConfig_OneWire;
+        *pCount = NV_ARRAY_SIZE(s_NvOdmPinMuxConfig_OneWire);
+        break;
+
+    case NvOdmIoModule_SyncNor:
+        *pPinMuxConfigTable = s_NvOdmPinMuxConfig_SyncNor;
+        *pCount = NV_ARRAY_SIZE(s_NvOdmPinMuxConfig_SyncNor);
+        break;
+
+    case NvOdmIoModule_PciExpress:
+        *pPinMuxConfigTable = s_NvOdmPinMuxConfig_PciExpress;
+        *pCount = NV_ARRAY_SIZE(s_NvOdmPinMuxConfig_PciExpress);
+        break;
+
+    case NvOdmIoModule_Trace:
+        if ((Personality == TEGRA_DEVKIT_BCT_CUSTOPT_0_PERSONALITY_11) ||
+            (Personality == TEGRA_DEVKIT_BCT_CUSTOPT_0_PERSONALITY_15) ||
+            (Personality == TEGRA_DEVKIT_BCT_CUSTOPT_0_PERSONALITY_C1))
+        {
+            *pPinMuxConfigTable = s_NvOdmPinMuxConfig_Ptm;
+            *pCount = NV_ARRAY_SIZE(s_NvOdmPinMuxConfig_Ptm);
+        }
+        else
+        {
+            *pCount = 0;
+        }
+        break;
+
+    case NvOdmIoModule_BacklightPwm:
+        *pPinMuxConfigTable = s_NvOdmPinMuxConfig_BacklightPwm;
+        *pCount = NV_ARRAY_SIZE(s_NvOdmPinMuxConfig_BacklightPwm);
+        break;
+
+    case NvOdmIoModule_Hsmmc:
+    case NvOdmIoModule_Csi:
+    case NvOdmIoModule_Sflash:
+    case NvOdmIoModule_Slink:
+    case NvOdmIoModule_Gpio:
+    case NvOdmIoModule_I2s:
+    case NvOdmIoModule_Usb:
+    case NvOdmIoModule_Vdd:
+    case NvOdmIoModule_Xio:
+    case NvOdmIoModule_Tsense:
+        *pCount = 0;
+        break;
+
+    default:
+        NV_ASSERT(!"Bad Parameter!");
+        *pCount = 0;
+        break;
+    }
+}
+
+void
+NvOdmQueryClockLimits(
+    NvOdmIoModule IoModule,
+    const NvU32 **pClockSpeedLimits,
+    NvU32 *pCount)
+{
+    switch (IoModule)
+    {
+    case NvOdmIoModule_Hsmmc:
+        *pCount = 0;
+        break;
+
+    case NvOdmIoModule_Sdio:
+        *pClockSpeedLimits = s_NvOdmClockLimit_Sdio;
+        *pCount = NVODM_PINMUX_ARRAY_SIZE(s_NvOdmClockLimit_Sdio);
+        break;
+
+
+    default:
+        *pClockSpeedLimits = NULL;
+        *pCount = 0;
+        break;
+    }
+}
+
diff --git a/arch/arm/mach-tegra/odm_kit/query/whistler/subboards/nvodm_query_discovery_e1109_addresses.h b/arch/arm/mach-tegra/odm_kit/query/whistler/subboards/nvodm_query_discovery_e1109_addresses.h
new file mode 100644
index 000000000000..4752fca7b93e
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/query/whistler/subboards/nvodm_query_discovery_e1109_addresses.h
@@ -0,0 +1,102 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/**
+ * @file
+ * <b>NVIDIA APX ODM Kit::
+ *         Implementation of the ODM Peripheral Discovery API</b>
+ *
+ * @b Description: Specifies the peripheral connectivity 
+ *                 database NvOdmIoAddress entries for the E1109
+ *                 Processor Module.
+ */
+
+#include "pmu/max8907b/max8907b_supply_info_table.h"
+#include "tmon/adt7461/nvodm_tmon_adt7461_channel.h"
+#include "nvodm_tmon.h"
+
+static const NvOdmIoAddress s_ffaHdmiAddresses[] =
+{
+    { NvOdmIoModule_Hdmi, 0, 0 },
+
+    /* Display Data Channel (DDC) for Extended Display Identification
+     * Data (EDID)
+     */
+    { NvOdmIoModule_I2c, 0x01, 0xA0 },
+
+    /* HDCP downstream */
+    { NvOdmIoModule_I2c, 0x01, 0x74 },
+
+    /* AVDD_HDMI -> D1REG */
+    { NvOdmIoModule_Vdd, 0x00, Max8907bPmuSupply_LDO11 },
+
+    /* MIPI PLL */
+    { NvOdmIoModule_Vdd, 0, Max8907bPmuSupply_LDO6 },
+
+    /* lcd i/o rail (for hot plug pin) */
+    { NvOdmIoModule_Vdd, 0x00, Max8907bPmuSupply_LX_V3 },
+};
+
+static const NvOdmIoAddress s_ffaCrtAddresses[] =
+{
+    { NvOdmIoModule_Crt, 0, 0 },
+
+    /* Display Data Channel (DDC) for Extended Display Identification
+     * Data (EDID)
+     */
+    { NvOdmIoModule_I2c, 0x01, 0xA0 },
+
+    /* tvdac rail (required) */
+    { NvOdmIoModule_Vdd, 0x00,  Max8907bPmuSupply_LDO14 },
+
+    /* lcd i/o rail (for hot plug pin) */
+    { NvOdmIoModule_Vdd, 0x00, Max8907bPmuSupply_LX_V3 },
+};
+
+static const NvOdmIoAddress s_ffaVideoDacAddresses[] =
+{
+    { NvOdmIoModule_Tvo, 0x00, 0x00 },
+    /* tvdac rail */
+    { NvOdmIoModule_Vdd, 0x00, Max8907bPmuSupply_LDO14 },
+};
+
+static const NvOdmIoAddress s_Tmon0Addresses[] = 
+{
+    { NvOdmIoModule_I2c_Pmu, 0x00, 0x98 }, /* I2C bus */
+    { NvOdmIoModule_Vdd, 0x00, Max8907bPmuSupply_LDO15 }, /* TMON pwer rail -> D4REG */
+    { NvOdmIoModule_Gpio, 0x08, 0x02 },                   /* GPIO Port I and Pin 2 */
+
+    /* Temperature zone mapping */
+    { NvOdmIoModule_Tsense, NvOdmTmonZoneID_Core, ADT7461ChannelID_Remote },   /* TSENSOR */
+    { NvOdmIoModule_Tsense, NvOdmTmonZoneID_Ambient, ADT7461ChannelID_Local }, /* TSENSOR */
+};
+
diff --git a/arch/arm/mach-tegra/odm_kit/query/whistler/subboards/nvodm_query_discovery_e1109_peripherals.h b/arch/arm/mach-tegra/odm_kit/query/whistler/subboards/nvodm_query_discovery_e1109_peripherals.h
new file mode 100644
index 000000000000..9f213e0c35ab
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/query/whistler/subboards/nvodm_query_discovery_e1109_peripherals.h
@@ -0,0 +1,75 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/**
+ * @file
+ * <b>NVIDIA APX ODM Kit::
+ *         Implementation of the ODM Peripheral Discovery API</b>
+ * 
+ * @b Description: Specifies the peripheral connectivity
+ *                 database Peripheral entries for the E91109
+ *                 Processor Module.
+ */
+
+// HDMI
+{
+    NV_ODM_GUID('f','f','a','_','h','d','m','i'),
+    s_ffaHdmiAddresses,
+    NV_ARRAY_SIZE(s_ffaHdmiAddresses),
+    NvOdmPeripheralClass_Display
+},
+
+// CRT
+{
+    NV_ODM_GUID('f','f','a','_','-','c','r','t'),
+    s_ffaCrtAddresses,
+    NV_ARRAY_SIZE(s_ffaCrtAddresses),
+    NvOdmPeripheralClass_Display
+},
+
+// TV Out Video Dac
+{
+    NV_ODM_GUID('f','f','a','t','v','o','u','t'),
+    s_ffaVideoDacAddresses,
+    NV_ARRAY_SIZE(s_ffaVideoDacAddresses),
+    NvOdmPeripheralClass_Display
+},
+
+// Temperature Monitor (TMON)
+{
+    NV_ODM_GUID('a','d','t','7','4','6','1',' '),
+    s_Tmon0Addresses,
+    NV_ARRAY_SIZE(s_Tmon0Addresses),
+    NvOdmPeripheralClass_Other
+},
+ 
+// NOTE: This list *must* end with a trailing comma.
diff --git a/arch/arm/mach-tegra/odm_kit/query/whistler/subboards/nvodm_query_discovery_e1116_addresses.h b/arch/arm/mach-tegra/odm_kit/query/whistler/subboards/nvodm_query_discovery_e1116_addresses.h
new file mode 100644
index 000000000000..2b5ca7f8bacd
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/query/whistler/subboards/nvodm_query_discovery_e1116_addresses.h
@@ -0,0 +1,270 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+
+/**
+ * @file
+ * <b>NVIDIA APX ODM Kit::
+ *         Implementation of the ODM Peripheral Discovery API</b>
+ *
+ * @b Description: Specifies the peripheral connectivity 
+ *                 database NvOdmIoAddress entries for the E1116
+ *                 Power module.
+ */
+
+#include "pmu/max8907b/max8907b_supply_info_table.h"
+
+// Persistent voltage rail (ie, for RTC, Standby, etc...)
+static const NvOdmIoAddress s_ffaRtcAddresses[] = 
+{
+    // On Maxim 8907B, the standby rail automatically follows V2
+    { NvOdmIoModule_Vdd, 0x00, Max8907bPmuSupply_LX_V2 }  /* VDD_RTC -> RTC */
+};
+
+// Core voltage rail
+static const NvOdmIoAddress s_ffaCoreAddresses[] = 
+{
+    { NvOdmIoModule_Vdd, 0x00, Max8907bPmuSupply_LX_V2 }  /* VDD_CORE -> V2 */
+};
+
+// PMU CPU voltage rail
+static const NvOdmIoAddress s_ffaCpuAddresses[] = 
+{
+    { NvOdmIoModule_Vdd, 0x00, Max8907bPmuSupply_LX_V1 }  /* VDD_CPU_PMU -> V1 */
+};
+
+// External CPU DCDC voltage rail
+static const NvOdmIoAddress s_ffaCpuExtSupplyAddresses[] = 
+{
+    { NvOdmIoModule_Vdd, 0x00, Max8907bLxV1_Ad5258_DPM_EXT_DCDC_7 }  /* VDD_CPU_PMU -> DCDC7 */
+};
+
+// PLLA voltage rail
+static const NvOdmIoAddress s_ffaPllAAddresses[] = 
+{
+    { NvOdmIoModule_Vdd, 0x00, Max8907bPmuSupply_LDO2 } /* AVDD_PLLA_P_C_S -> VOUT2 */
+};
+
+// PLLM voltage rail
+static const NvOdmIoAddress s_ffaPllMAddresses[] = 
+{
+    { NvOdmIoModule_Vdd, 0x00, Max8907bPmuSupply_LDO2 } /* AVDD_PLLM -> VOUT2 */
+};
+
+// PLLP voltage rail
+static const NvOdmIoAddress s_ffaPllPAddresses[] = 
+{
+    { NvOdmIoModule_Vdd, 0x00, Max8907bPmuSupply_LDO2 } /* AVDD_PLLA_P_C_S -> VOUT2 */
+};
+
+// PLLC voltage rail
+static const NvOdmIoAddress s_ffaPllCAddresses[] = 
+{
+    { NvOdmIoModule_Vdd, 0x00, Max8907bPmuSupply_LDO2 } /* AVDD_PLLA_P_C_S -> VOUT2 */
+};
+
+// PLLE voltage rail
+static const NvOdmIoAddress s_ffaPllEAddresses[] = 
+{
+    { NvOdmIoModule_Vdd, 0x00, Max8907bPmuSupply_LDO2 } /* AVDD_PLL_E -> VOUT2 */
+};
+
+// PLLU1 voltage rail
+static const NvOdmIoAddress s_ffaPllU1Addresses[] = 
+{
+    { NvOdmIoModule_Vdd, 0x00, Max8907bPmuSupply_LDO2 } /* AVDD_PLLU -> VOUT2 */
+};
+
+// PLLS voltage rail
+static const NvOdmIoAddress s_ffaPllSAddresses[] = 
+{
+    { NvOdmIoModule_Vdd, 0x00, Max8907bPmuSupply_LDO2 } /* AVDD_PLLA_P_C_S -> VOUT2 */
+};
+
+// PLLHD voltage rail
+static const NvOdmIoAddress s_ffaPllHdmiAddresses[] = 
+{
+    { NvOdmIoModule_Vdd, 0x00, Max8907bPmuSupply_LDO6 } /* AVDD_HDMI_PLL -> VOUT6 */
+};
+
+// OSC voltage rail
+static const NvOdmIoAddress s_ffaVddOscAddresses[] = 
+{
+    { NvOdmIoModule_Vdd, 0x00, Max8907bPmuSupply_LX_V3 } /* AVDD_OSC -> V3 */
+};
+
+// PLLX voltage rail
+static const NvOdmIoAddress s_ffaPllXAddresses[] = 
+{
+    { NvOdmIoModule_Vdd, 0x00, Max8907bPmuSupply_LDO2 } /* AVDD_PLLX -> VOUT2 */
+};
+
+// PLL_USB voltage rail
+static const NvOdmIoAddress s_ffaPllUsbAddresses[] = 
+{
+    { NvOdmIoModule_Vdd, 0x00, Max8907bPmuSupply_LDO4 } /* AVDD_USB_PLL -> VOUT4 */
+};
+
+// SYS IO voltage rail
+static const NvOdmIoAddress s_ffaVddSysAddresses[] = 
+{
+    { NvOdmIoModule_Vdd, 0x00, Max8907bPmuSupply_LX_V3 } /* VDDIO_SYS -> V3 */
+};
+
+// USB voltage rail
+static const NvOdmIoAddress s_ffaVddUsbAddresses[] = 
+{
+    { NvOdmIoModule_Vdd, 0x00, Max8907bPmuSupply_LDO4 } /* AVDD_USB -> VOUT4 */
+};
+
+// HDMI voltage rail
+static const NvOdmIoAddress s_ffaVddHdmiAddresses[] = 
+{
+    { NvOdmIoModule_Vdd, 0x00, Max8907bPmuSupply_LDO11 } /* AVDD_HDMI -> VOUT11 */
+};
+
+// MIPI voltage rail
+static const NvOdmIoAddress s_ffaVddMipiAddresses[] = 
+{
+    { NvOdmIoModule_Vdd, 0x00, Max8907bPmuSupply_LDO17 } /* VDDIO_MIPI -> VOUT17 */
+};
+
+// LCD voltage rail
+static const NvOdmIoAddress s_ffaVddLcdAddresses[] = 
+{
+    { NvOdmIoModule_Vdd, 0x00, Max8907bPmuSupply_LX_V3 } /* VDDIO_LCD_PMU -> V3 */
+};
+
+// Audio voltage rail
+static const NvOdmIoAddress s_ffaVddAudAddresses[] = 
+{
+    { NvOdmIoModule_Vdd, 0x00, Max8907bPmuSupply_LX_V3 } /* VDDIO_AUDIO -> V3 */
+};
+
+// LPDDR2 voltage rail (default)
+static const NvOdmIoAddress s_ffaVddDdrAddresses[] = 
+{
+    { NvOdmIoModule_Vdd, 0x00, Max8907bPmuSupply_LDO20 }  /* VDDIO_DDR_1V2 -> VOUT20 */
+};
+
+// DDR2 voltage rail (on E1109 board ext 1.8V DCDC is controlled by LDO5)
+static const NvOdmIoAddress s_ffaVddDdr2Addresses[] = 
+{
+    { NvOdmIoModule_Vdd, 0x00, Max8907bPmuSupply_LDO5 }  /* VDDIO_DDR_1V8 -> VOUT05 */
+};
+
+// DDR_RX voltage rail
+static const NvOdmIoAddress s_ffaVddDdrRxAddresses[] = 
+{
+    { NvOdmIoModule_Vdd, 0x00, Max8907bPmuSupply_LDO1 }  /* VDDIO_RX_DDR(2.7-3.3) -> VOUT1 */
+};
+
+// NAND voltage rail
+static const NvOdmIoAddress s_ffaVddNandAddresses[] = 
+{
+    { NvOdmIoModule_Vdd, 0x00, Max8907bPmuSupply_LX_V3 } /* VDDIO_NAND_PMU -> V3 */
+};
+
+// UART voltage rail
+static const NvOdmIoAddress s_ffaVddUartAddresses[] = 
+{
+    { NvOdmIoModule_Vdd, 0x00, Max8907bPmuSupply_LX_V3 } /* VDDIO_UART -> V3 */
+};
+
+// SDIO voltage rail
+static const NvOdmIoAddress s_ffaVddSdioAddresses[] = 
+{
+    { NvOdmIoModule_Vdd, 0x00, Max8907bPmuSupply_LDO12 } /* VDDIO_SDIO -> VOUT12 */
+};
+
+// VDAC voltage rail
+static const NvOdmIoAddress s_ffaVddVdacAddresses[] = 
+{
+    { NvOdmIoModule_Vdd, 0x00, Max8907bPmuSupply_LDO14 } /* AVDD_VDAC -> VOUT14 */
+};
+
+// VI voltage rail
+static const NvOdmIoAddress s_ffaVddViAddresses[] = 
+{
+    { NvOdmIoModule_Vdd, 0x00, Max8907bPmuSupply_LDO18 } /* VDDIO_VI -> VOUT18 */
+};
+
+// BB voltage rail
+static const NvOdmIoAddress s_ffaVddBbAddresses[] = 
+{
+    { NvOdmIoModule_Vdd, 0x00, Max8907bPmuSupply_LX_V3 } /* VDDIO_BB -> V3 */
+};
+
+// HSIC voltage rail
+static const NvOdmIoAddress s_ffaVddHsicAddresses[] = 
+{
+    { NvOdmIoModule_Vdd, 0x00, Max8907bPmuSupply_LDO20 } /* VDDIO_HSIC -> VOUT20 */
+};
+
+// USB_IC voltage rail
+static const NvOdmIoAddress s_ffaVddUsbIcAddresses[] = 
+{
+    { NvOdmIoModule_Vdd, 0x00, Max8907bPmuSupply_LX_V3 } /* AVDD_USB_IC -> V3 */
+};
+
+// PEX_CLK voltage rail
+static const NvOdmIoAddress s_ffaVddPexClkAddresses[] = 
+{
+    { NvOdmIoModule_Vdd, 0x00, Max8907bPmuSupply_LDO11 }, /* VDDIO_PEX_CLK -> VOUT11 */
+    { NvOdmIoModule_Vdd, 0x00, Max8907bPmuSupply_LDO12 }, /* VDDIO_PEX_CLK -> VOUT12 */
+    { NvOdmIoModule_Vdd, 0x00, Max8907bPmuSupply_EXT_DCDC_3 } 
+};
+
+// PMU0
+static const NvOdmIoAddress s_Pmu0Addresses[] = 
+{
+    { NvOdmIoModule_I2c_Pmu, 0x00, 0x78 },
+};
+
+// I2C IO Expander
+static const NvOdmIoAddress s_I2cioexpanderAddress[] = 
+{
+    { NvOdmIoModule_I2c_Pmu, 0x00, 0x40 },
+};
+
+// USB1 VBus voltage rail
+static const NvOdmIoAddress s_ffaVddUsb1VBusAddresses[] = 
+{
+    { NvOdmIoModule_Vdd, 0x00, Max8907bPmuSupply_EXT_DCDC_3_USB1 },
+};
+
+// USB3 VBus voltage rail
+static const NvOdmIoAddress s_ffaVddUsb3VBusAddresses[] = 
+{
+    { NvOdmIoModule_Vdd, 0x00, Max8907bPmuSupply_EXT_DCDC_3_USB3 },
+};
+
diff --git a/arch/arm/mach-tegra/odm_kit/query/whistler/subboards/nvodm_query_discovery_e1116_peripherals.h b/arch/arm/mach-tegra/odm_kit/query/whistler/subboards/nvodm_query_discovery_e1116_peripherals.h
new file mode 100644
index 000000000000..5145bf5b0711
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/query/whistler/subboards/nvodm_query_discovery_e1116_peripherals.h
@@ -0,0 +1,349 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/**
+ * @file
+ * <b>NVIDIA APX ODM Kit::
+ *         Implementation of the ODM Peripheral Discovery API</b>
+ *
+ * @b Description: Specifies the peripheral connectivity 
+ *                 database Peripheral entries for the E1116
+ *                 power module.
+ */
+
+/*  All of the reserved values, for SOC voltage domains.
+ */
+
+// WHISTLER_AP16_ONLY - AP20 doesn't have PLL_D rail.
+// PLLD (NV reserved) / Use PLL_U
+{
+    NV_VDD_PLLD_ODM_ID,
+    s_ffaPllU1Addresses,
+    NV_ARRAY_SIZE(s_ffaPllU1Addresses),
+    NvOdmPeripheralClass_Other
+},
+// -------- END WHISTLER_AP16_ONLY -------- 
+
+
+// RTC (NV reserved)
+{
+    NV_VDD_RTC_ODM_ID,
+    s_ffaRtcAddresses,
+    NV_ARRAY_SIZE(s_ffaRtcAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// CORE (NV reserved)
+{
+    NV_VDD_CORE_ODM_ID,
+    s_ffaCoreAddresses,
+    NV_ARRAY_SIZE(s_ffaCoreAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// CPU (NV reserved)
+{
+    NV_VDD_CPU_ODM_ID,
+    s_ffaCpuAddresses,
+    NV_ARRAY_SIZE(s_ffaCpuAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// PLLA (NV reserved)
+{
+    NV_VDD_PLLA_ODM_ID,
+    s_ffaPllAAddresses,
+    NV_ARRAY_SIZE(s_ffaPllAAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// PLLM (NV reserved)
+{
+    NV_VDD_PLLM_ODM_ID,
+    s_ffaPllMAddresses,
+    NV_ARRAY_SIZE(s_ffaPllMAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// PLLP (NV reserved)
+{
+    NV_VDD_PLLP_ODM_ID,
+    s_ffaPllPAddresses,
+    NV_ARRAY_SIZE(s_ffaPllPAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// PLLC (NV reserved)
+{
+    NV_VDD_PLLC_ODM_ID,
+    s_ffaPllCAddresses,
+    NV_ARRAY_SIZE(s_ffaPllCAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// PLLE (NV reserved)
+{
+    NV_VDD_PLLE_ODM_ID,
+    s_ffaPllEAddresses,
+    NV_ARRAY_SIZE(s_ffaPllEAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// PLLU (NV reserved)
+{
+    NV_VDD_PLLU_ODM_ID,
+    s_ffaPllUsbAddresses,
+    NV_ARRAY_SIZE(s_ffaPllUsbAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// PLLU1 (NV reserved)
+{
+    NV_VDD_PLLU1_ODM_ID,
+    s_ffaPllU1Addresses,
+    NV_ARRAY_SIZE(s_ffaPllU1Addresses),
+    NvOdmPeripheralClass_Other
+},
+
+// PLLS (NV reserved)
+{
+    NV_VDD_PLLS_ODM_ID,
+    s_ffaPllSAddresses,
+    NV_ARRAY_SIZE(s_ffaPllSAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// HDMI PLL (NV reserved)
+{
+    NV_VDD_PLLHDMI_ODM_ID,
+    s_ffaPllHdmiAddresses,
+    NV_ARRAY_SIZE(s_ffaPllHdmiAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// OSC VDD (NV reserved)
+{
+    NV_VDD_OSC_ODM_ID,
+    s_ffaVddOscAddresses,
+    NV_ARRAY_SIZE(s_ffaVddOscAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// PLLX (NV reserved)
+{
+    NV_VDD_PLLX_ODM_ID,
+    s_ffaPllXAddresses,
+    NV_ARRAY_SIZE(s_ffaPllXAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// PLL_USB (NV reserved)
+{
+    NV_VDD_PLL_USB_ODM_ID,
+    s_ffaPllUsbAddresses,
+    NV_ARRAY_SIZE(s_ffaPllUsbAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// (TBD) PLL_PEX (NV reserved)
+
+// System IO VDD (NV reserved)
+{
+    NV_VDD_SYS_ODM_ID,
+    s_ffaVddSysAddresses,
+    NV_ARRAY_SIZE(s_ffaVddSysAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// USB VDD (NV reserved)
+{
+    NV_VDD_USB_ODM_ID,
+    s_ffaVddUsbAddresses,
+    NV_ARRAY_SIZE(s_ffaVddUsbAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+//  VBUS for USB1
+{
+    NV_VDD_VBUS_ODM_ID,
+    s_ffaVddUsb1VBusAddresses,
+    NV_ARRAY_SIZE(s_ffaVddUsb1VBusAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+//  VBUS for USB3
+{
+    NV_VDD_USB3_VBUS_ODM_ID,
+    s_ffaVddUsb3VBusAddresses,
+    NV_ARRAY_SIZE(s_ffaVddUsb3VBusAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+
+// HDMI VDD (NV reserved)
+{
+    NV_VDD_HDMI_ODM_ID,
+    s_ffaVddHdmiAddresses,
+    NV_ARRAY_SIZE(s_ffaVddHdmiAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// MIPI VDD (NV reserved)
+{
+    NV_VDD_MIPI_ODM_ID,
+    s_ffaVddMipiAddresses,
+    NV_ARRAY_SIZE(s_ffaVddMipiAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// LCD VDD (NV reserved)
+{
+    NV_VDD_LCD_ODM_ID,
+    s_ffaVddLcdAddresses,
+    NV_ARRAY_SIZE(s_ffaVddLcdAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// AUDIO VDD (NV reserved)
+{
+    NV_VDD_AUD_ODM_ID,
+    s_ffaVddAudAddresses,
+    NV_ARRAY_SIZE(s_ffaVddAudAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// DDR VDD (NV reserved)
+{
+    NV_VDD_DDR_ODM_ID,
+    s_ffaVddDdrAddresses,
+    NV_ARRAY_SIZE(s_ffaVddDdrAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// DDR_RX (NV reserved)
+{
+    NV_VDD_DDR_RX_ODM_ID,
+    s_ffaVddDdrRxAddresses,
+    NV_ARRAY_SIZE(s_ffaVddDdrRxAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// NAND VDD (NV reserved)
+{
+    NV_VDD_NAND_ODM_ID,
+    s_ffaVddNandAddresses,
+    NV_ARRAY_SIZE(s_ffaVddNandAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// UART VDD (NV reserved)
+{
+    NV_VDD_UART_ODM_ID,
+    s_ffaVddUartAddresses,
+    NV_ARRAY_SIZE(s_ffaVddUartAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// SDIO VDD (NV reserved)
+{
+    NV_VDD_SDIO_ODM_ID,
+    s_ffaVddSdioAddresses,
+    NV_ARRAY_SIZE(s_ffaVddSdioAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// VDAC VDD (NV reserved)
+{
+    NV_VDD_VDAC_ODM_ID,
+    s_ffaVddVdacAddresses,
+    NV_ARRAY_SIZE(s_ffaVddVdacAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// VI VDD (NV reserved)
+{
+    NV_VDD_VI_ODM_ID,
+    s_ffaVddViAddresses,
+    NV_ARRAY_SIZE(s_ffaVddViAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// BB VDD (NV reserved)
+{
+    NV_VDD_BB_ODM_ID,
+    s_ffaVddBbAddresses,
+    NV_ARRAY_SIZE(s_ffaVddBbAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// HSIC (NV reserved)
+{
+    NV_VDD_HSIC_ODM_ID,
+    s_ffaVddHsicAddresses,
+    NV_ARRAY_SIZE(s_ffaVddHsicAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// USB_IC (NV reserved)
+{
+    NV_VDD_USB_IC_ODM_ID,
+    s_ffaVddUsbIcAddresses,
+    NV_ARRAY_SIZE(s_ffaVddUsbIcAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// (TBD) PEX (NV reserved)
+
+// PEX_CLK (NV reserved)
+{
+    NV_VDD_PEX_CLK_ODM_ID,
+    s_ffaVddPexClkAddresses,
+    NV_ARRAY_SIZE(s_ffaVddPexClkAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+//  PMU0
+{
+    NV_ODM_GUID('m','a','x','8','9','0','7','b'),
+    s_Pmu0Addresses,
+    NV_ARRAY_SIZE(s_Pmu0Addresses),
+    NvOdmPeripheralClass_Other
+},
+//  I2C IO expander
+{
+    NV_ODM_GUID('t','c','a','_','6','4','1','6'),
+    s_I2cioexpanderAddress,
+    NV_ARRAY_SIZE(s_I2cioexpanderAddress),
+    NvOdmPeripheralClass_Other
+},
+
+// NOTE: This list *must* end with a trailing comma.
diff --git a/arch/arm/mach-tegra/odm_kit/query/whistler/subboards/nvodm_query_discovery_e1120_addresses.h b/arch/arm/mach-tegra/odm_kit/query/whistler/subboards/nvodm_query_discovery_e1120_addresses.h
new file mode 100644
index 000000000000..7085868e5374
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/query/whistler/subboards/nvodm_query_discovery_e1120_addresses.h
@@ -0,0 +1,74 @@
+
+
+/*
+ * Copyright (c) 2010 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/**
+ * @file
+ * <b>NVIDIA APX ODM Kit::
+ *         Implementation of the ODM Peripheral Discovery API</b>
+ *
+ * @b Description: Specifies the peripheral connectivity 
+ *                 database NvOdmIoAddress entries for the E1120
+ *                 AP20 Development System Motherboard.
+ */
+
+#include "pmu/max8907b/max8907b_supply_info_table.h"
+
+static const NvOdmIoAddress s_enc28j60EthernetAddresses[] =
+{
+    { NvOdmIoModule_Spi, 1, 1 },
+    { NvOdmIoModule_Gpio, (NvU32)'c'-'a', 1 }
+};
+
+static const NvOdmIoAddress s_SdioAddresses[] =
+{
+    { NvOdmIoModule_Sdio, 0x0, 0x0 },
+    { NvOdmIoModule_Sdio, 0x2, 0x0 },
+    { NvOdmIoModule_Sdio, 0x3, 0x0 },
+    { NvOdmIoModule_Vdd, 0x00, Max8907bPmuSupply_LDO12 }, /* VDDIO_SDIO -> VOUT12 */
+    { NvOdmIoModule_Vdd, 0x00, Max8907bPmuSupply_LDO5 } /* VCORE_MMC -> VOUT05 */
+};
+
+static const NvOdmIoAddress s_VibAddresses[] =
+{
+    { NvOdmIoModule_Vdd, 0x0, Max8907bPmuSupply_LDO16},
+};
+
+static const NvOdmIoAddress s_AcceleroAddresses[] =
+{
+    { NvOdmIoModule_I2c, 0x0, 0x3A }, /* I2C address (7-bit) 0x1D < 1 = 0x3A (8-bit) */
+    { NvOdmIoModule_Gpio, 0x1A, 0x1 }, /* Gpio port AA[1] = (A=0, Z=25) thus AA = 26 = 0x1A */
+    { NvOdmIoModule_Vdd, 0x0, Max8907bPmuSupply_LX_V3 }, /* VDDIO_UART = V3 */
+    { NvOdmIoModule_Vdd, 0x0, Max8907bPmuSupply_LDO1 }, /* VCORE_ACC = VOUT1 = 2.8v */
+};
+
diff --git a/arch/arm/mach-tegra/odm_kit/query/whistler/subboards/nvodm_query_discovery_e1120_peripherals.h b/arch/arm/mach-tegra/odm_kit/query/whistler/subboards/nvodm_query_discovery_e1120_peripherals.h
new file mode 100644
index 000000000000..90d038ba2ab2
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/query/whistler/subboards/nvodm_query_discovery_e1120_peripherals.h
@@ -0,0 +1,75 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/**
+ * @file
+ * <b>NVIDIA APX ODM Kit::
+ *         Implementation of the ODM Peripheral Discovery API</b>
+ *
+ * @b Description: Specifies the peripheral connectivity database Peripheral
+ *                 entries for the E1120 AP20 Development System
+ *                 Motherboard.
+ */
+
+//  Ethernet module
+{
+    NV_ODM_GUID('e','n','c','2','8','j','6','0'),
+    s_enc28j60EthernetAddresses,
+    NV_ARRAY_SIZE(s_enc28j60EthernetAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+//  Sdio module
+{
+    NV_ODM_GUID('s','d','i','o','_','m','e','m'),
+    s_SdioAddresses,
+    NV_ARRAY_SIZE(s_SdioAddresses),
+    NvOdmPeripheralClass_Other,
+},
+
+//..Vibrate Module
+{
+    NV_ODM_GUID('v','i','b','r','a','t','o','r'),
+    s_VibAddresses,
+    NV_ARRAY_SIZE(s_VibAddresses),
+    NvOdmPeripheralClass_Other,
+},
+
+// Accelerometer Module
+{
+    NV_ODM_GUID('a','c','c','e','l','e','r','o'),
+    s_AcceleroAddresses,
+    NV_ARRAY_SIZE(s_AcceleroAddresses),
+    NvOdmPeripheralClass_Other,
+},
+
+// NOTE: This list *must* end with a trailing comma.
diff --git a/arch/arm/mach-tegra/odm_kit/query/whistler/subboards/nvodm_query_discovery_e1129_addresses.h b/arch/arm/mach-tegra/odm_kit/query/whistler/subboards/nvodm_query_discovery_e1129_addresses.h
new file mode 100644
index 000000000000..bedebff4a8e4
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/query/whistler/subboards/nvodm_query_discovery_e1129_addresses.h
@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/**
+ * @file
+ * <b>NVIDIA APX ODM Kit::
+ *         Implementation of the ODM Peripheral Discovery API</b>
+ *
+ * @b Description: Specifies the peripheral connectivity
+ *                 database NvOdmIoAddress entries for the E1129
+ *                 keypad module.
+ */
+#include "../nvodm_query_kbc_gpio_def.h"
+
+// Key Pad
+static const NvOdmIoAddress s_KeyPadAddresses[] =
+{
+    // instance = 1 indicates Column info.
+    // instance = 0 indicates Row info.
+    // address holds KBC pin number used for row/column.
+
+    // All Row info has to be defined contiguously from 0 to max.
+    { NvOdmIoModule_Kbd,0x00, NvOdmKbcGpioPin_KBRow0}, // Row 0
+    { NvOdmIoModule_Kbd,0x00, NvOdmKbcGpioPin_KBRow1}, // Row 1
+    { NvOdmIoModule_Kbd,0x00 ,NvOdmKbcGpioPin_KBRow2}, // Row 2
+
+    // All Column info has to be defined contiguously from 0 to max.
+    { NvOdmIoModule_Kbd,0x01, NvOdmKbcGpioPin_KBCol0}, // Column 0
+    { NvOdmIoModule_Kbd,0x01, NvOdmKbcGpioPin_KBCol1}, // Column 1
+};
+
+// s_ffa ScrollWheel...  only supported for personality 1
+static const NvOdmIoAddress s_ffaScrollWheelAddresses[] =
+{
+    { NvOdmIoModule_Gpio, 0x10, 0x3 }, // GPIO Port q - Pin3
+    { NvOdmIoModule_Gpio, 0x11, 0x3 }, // GpIO Port r - Pin 3
+    { NvOdmIoModule_Gpio, 0x10, 0x5 }, // GPIO Port q - Pin 5
+    { NvOdmIoModule_Gpio, 0x10, 0x4 }, // GPIO Port q - Pin 4
+};
+
diff --git a/arch/arm/mach-tegra/odm_kit/query/whistler/subboards/nvodm_query_discovery_e1129_peripherals.h b/arch/arm/mach-tegra/odm_kit/query/whistler/subboards/nvodm_query_discovery_e1129_peripherals.h
new file mode 100644
index 000000000000..3df1481a6894
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/query/whistler/subboards/nvodm_query_discovery_e1129_peripherals.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/**
+ * @file
+ * <b>NVIDIA APX ODM Kit::
+ *         Implementation of the ODM Peripheral Discovery API</b>
+ *
+ * @b Description: Specifies the peripheral connectivity
+ *                 database Peripheral entries for the E1129
+ *                 keypad module.
+ */
+
+// Key Pad
+{
+    NV_ODM_GUID('k','e','y','b','o','a','r','d'),
+    s_KeyPadAddresses,
+    NV_ARRAY_SIZE(s_KeyPadAddresses),
+    NvOdmPeripheralClass_HCI
+},
+
+// Scroll Wheel
+{
+    NV_ODM_GUID('s','c','r','o','l','w','h','l'),
+    s_ffaScrollWheelAddresses,
+    NV_ARRAY_SIZE(s_ffaScrollWheelAddresses),
+    NvOdmPeripheralClass_HCI
+},
+
+// NOTE: This list *must* end with a trailing comma.
diff --git a/arch/arm/mach-tegra/odm_kit/query/whistler/subboards/nvodm_query_discovery_e888_addresses.h b/arch/arm/mach-tegra/odm_kit/query/whistler/subboards/nvodm_query_discovery_e888_addresses.h
new file mode 100644
index 000000000000..8946a5cb3056
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/query/whistler/subboards/nvodm_query_discovery_e888_addresses.h
@@ -0,0 +1,57 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/**
+ * @file
+ * <b>NVIDIA APX ODM Kit::
+ *         Implementation of the ODM Peripheral Discovery API</b>
+ *
+ * @b Description: Specifies the peripheral connectivity
+ *                 database NvOdmIoAddress entries for the E888
+ *                 audio module.
+ */
+
+#include "pmu/max8907b/max8907b_supply_info_table.h"
+
+// Audio Codec
+static const NvOdmIoAddress s_AudioCodecAddresses[] =
+{
+    { NvOdmIoModule_Vdd, 0x00, Max8907bPmuSupply_LDO7},  /* AUDIO_PLL etc -> DCD2 */
+    { NvOdmIoModule_ExternalClock, 0, 0 },                  // connected to CDEV1
+#if 1
+    { NvOdmIoModule_Spi, 2,     1 },                      /* FFA Audio codec on SP3- CS1*/
+#else
+    { NvOdmIoModule_I2c_Pmu, 0, 0x34},          /* FFA Audio codec on DVC*/
+
+#endif
+    { NvOdmIoModule_Dap, 0, 0 },                            /* Dap port Index 0 is used for codec*/
+};
diff --git a/arch/arm/mach-tegra/odm_kit/query/whistler/subboards/nvodm_query_discovery_e888_peripherals.h b/arch/arm/mach-tegra/odm_kit/query/whistler/subboards/nvodm_query_discovery_e888_peripherals.h
new file mode 100644
index 000000000000..939ae49f8175
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/query/whistler/subboards/nvodm_query_discovery_e888_peripherals.h
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/**
+ * @file
+ * <b>NVIDIA APX ODM Kit::
+ *         Implementation of the ODM Peripheral Discovery API</b>
+ *
+ * @b Description: Specifies the peripheral connectivity 
+ *                 database Peripheral entries for the E888
+ *                 audio module.
+ */
+
+//  audio codec
+{
+    NV_ODM_GUID('w','o','l','f','8','7','5','3'),
+    s_AudioCodecAddresses,
+    NV_ARRAY_SIZE(s_AudioCodecAddresses),
+    NvOdmPeripheralClass_Other
+},
+// NOTE: This list *must* end with a trailing comma.
diff --git a/arch/arm/mach-tegra/odm_kit/query/whistler/subboards/nvodm_query_discovery_e906_addresses.h b/arch/arm/mach-tegra/odm_kit/query/whistler/subboards/nvodm_query_discovery_e906_addresses.h
new file mode 100644
index 000000000000..09f3197447ea
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/query/whistler/subboards/nvodm_query_discovery_e906_addresses.h
@@ -0,0 +1,76 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/**
+ * @file
+ * <b>NVIDIA APX ODM Kit::
+ *         Implementation of the ODM Peripheral Discovery API</b>
+ *
+ * @b Description: Specifies the peripheral connectivity 
+ *                 database NvOdmIoAddress entries for the E906
+ *                 LCD Module.
+ */
+
+#include "pmu/max8907b/max8907b_supply_info_table.h"
+
+// Main LCD
+static const NvOdmIoAddress s_ffaMainDisplayAddresses[] = 
+{
+    { NvOdmIoModule_Display, 0, 0 },
+    { NvOdmIoModule_Spi, 0x2, 0x2 },                        // TBD (this is a guess)
+    { NvOdmIoModule_Vdd, 0x00, Max8907bPmuSupply_LX_V3 },   /* VDDIO_LCD -> V3 */
+    { NvOdmIoModule_Vdd, 0x00, Max8907bPmuSupply_LDO5 },    /* AVDD_LCD_1 -> VOUT5 */
+    { NvOdmIoModule_Vdd, 0x00, Max8907bPmuSupply_LDO19  },  /* AVDD_LCD_2 -> VOUT19 */
+};
+
+// DSI LCD
+// WARNING: Whistler's board personality needs to be set to 077 for the
+// reset gpio pin to work
+static const NvOdmIoAddress s_DsiAddresses[] = 
+{
+    { NvOdmIoModule_Display, 0, 0 },
+
+    { NvOdmIoModule_Gpio, (NvU32)('c' - 'a'), 1 },
+
+    { NvOdmIoModule_Vdd, 0x00, Max8907bPmuSupply_LX_V3 },   /* VDDIO_LCD -> V3 */
+    { NvOdmIoModule_Vdd, 0x00, Max8907bPmuSupply_LDO5 },    /* AVDD_LCD_1 -> VOUT5 */
+    { NvOdmIoModule_Vdd, 0x00, Max8907bPmuSupply_LDO19  },  /* AVDD_LCD_2 -> VOUT19 */
+    { NvOdmIoModule_Vdd, 0x00, Max8907bPmuSupply_LDO17  },  /* MIPI DSI 1.2V */
+};
+
+// TouchPanel
+static const NvOdmIoAddress s_ffaTouchPanelAddresses[] = 
+{
+    { NvOdmIoModule_I2c, 0x00, 0x20 },/* I2C device address is 0x20 */
+    { NvOdmIoModule_Gpio, 'c' - 'a', 6}, /* GPIO Port V and Pin 3 */
+    { NvOdmIoModule_Vdd, 0x00, Max8907bPmuSupply_LDO19 }
+};
diff --git a/arch/arm/mach-tegra/odm_kit/query/whistler/subboards/nvodm_query_discovery_e906_peripherals.h b/arch/arm/mach-tegra/odm_kit/query/whistler/subboards/nvodm_query_discovery_e906_peripherals.h
new file mode 100644
index 000000000000..44f7a967ff40
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/query/whistler/subboards/nvodm_query_discovery_e906_peripherals.h
@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/**
+ * @file
+ * <b>NVIDIA APX ODM Kit::
+ *         Implementation of the ODM Peripheral Discovery API</b>
+ * 
+ * @b Description: Specifies the peripheral connectivity
+ *                 database Peripheral entries for the E906 LCD
+ *                 Module.
+ */
+
+// LCD module
+{
+    NV_ODM_GUID('S','H','P','_','A','P','2','0'),   // Sharp WVGA panel with AP20 backlight control
+    s_ffaMainDisplayAddresses,
+    NV_ARRAY_SIZE(s_ffaMainDisplayAddresses),
+    NvOdmPeripheralClass_Display,
+},
+
+// DSI module
+{
+    NV_ODM_GUID('s','h','a','r','p','d','s','i'),
+    s_DsiAddresses,
+    NV_ARRAY_SIZE(s_DsiAddresses),
+    NvOdmPeripheralClass_Display,
+},
+
+//  Touch Panel
+{
+    NV_ODM_GUID('t','p','k','t','o','u','c','h'),
+    s_ffaTouchPanelAddresses,
+    NV_ARRAY_SIZE(s_ffaTouchPanelAddresses),
+    NvOdmPeripheralClass_HCI
+},
+
+// NOTE: This list *must* end with a trailing comma.
diff --git a/arch/arm/mach-tegra/odm_kit/query/whistler/subboards/nvodm_query_discovery_e911_addresses.h b/arch/arm/mach-tegra/odm_kit/query/whistler/subboards/nvodm_query_discovery_e911_addresses.h
new file mode 100644
index 000000000000..fe193db73d5e
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/query/whistler/subboards/nvodm_query_discovery_e911_addresses.h
@@ -0,0 +1,99 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/**
+ * @file
+ * <b>NVIDIA APX ODM Kit::
+ *         Implementation of the ODM Peripheral Discovery API</b>
+ *
+ * @b Description: Specifies the peripheral connectivity database NvOdmIoAddress entries
+ *                 for the E911 5MP + 1.3MP + VGA VI Camera module.
+ */
+#include "nvodm_query_gpio.h"
+#include "../include/nvodm_imager_guids.h"
+#include "pmu/max8907b/max8907b_supply_info_table.h"
+
+#define NVODM_PORT(x) ((x) - 'a')
+/* VGP5 is apparently inverted on some boards.
+ * For E912- A01, you may need to change the VGP5_RESET_AL line to:
+ * NVODM_CAMERA_VGP5_RESET
+ * If you find other boards for which it needs to be inverted, please
+ * add your information to this comment.
+ */
+#define OV5630_PINS (NVODM_CAMERA_SERIAL_CSI_D1A | \
+                     NVODM_CAMERA_DEVICE_IS_DEFAULT)
+static const NvOdmIoAddress s_ffaImagerOV5630Addresses[] =
+{
+    { NvOdmIoModule_I2c,  0x02, 0x6C }, 
+    { NvOdmIoModule_Gpio, NVODM_GPIO_CAMERA_PORT, 5 | NVODM_IMAGER_RESET_AL },
+    { NvOdmIoModule_Gpio, NVODM_PORT('t'), 3 | NVODM_IMAGER_POWERDOWN },
+    { NvOdmIoModule_Vdd,  0x00, Max8907bPmuSupply_LDO18 }, //VDDIO_VI
+    { NvOdmIoModule_Vdd,  0x00, Max8907bPmuSupply_LDO9 }, //AVDD_CAM1
+    { NvOdmIoModule_Vdd,  0x00, Max8907bPmuSupply_LDO13 }, //VDDIO_AF
+    { NvOdmIoModule_Vdd,  0x00, Max8907bPmuSupply_LDO17 }, //VDDIO_MIPI
+    { NvOdmIoModule_VideoInput, 0x00, OV5630_PINS },
+    { NvOdmIoModule_ExternalClock, 2, 0 } // CSUS
+};
+
+// OV5630 focuser
+static const NvOdmIoAddress s_ffaImagerAD5820Addresses[] =
+{
+    { NvOdmIoModule_I2c,  0x02, 0x18 },  // focuser i2c
+};
+
+// OV5630 flash
+static const NvOdmIoAddress s_ffaFlashLTC3216Addresses[] =
+{
+    { NvOdmIoModule_Gpio, NVODM_GPIO_CAMERA_PORT, 3 | NVODM_IMAGER_FLASH0 },  // Flash 200mA
+    { NvOdmIoModule_Gpio, NVODM_GPIO_CAMERA_PORT, 6 | NVODM_IMAGER_FLASH1 }   // Flash 600mA
+};
+
+// For SEMCO VGA
+#define SOC380_PINS (NVODM_CAMERA_PARALLEL_VD0_TO_VD7)
+static const NvOdmIoAddress s_ffaImagerSOC380Addresses[] =
+{
+    { NvOdmIoModule_I2c,  0x02, 0x78 },
+    { NvOdmIoModule_Gpio, NVODM_GPIO_CAMERA_PORT, 4 | NVODM_IMAGER_POWERDOWN_AL },
+    { NvOdmIoModule_Gpio, NVODM_GPIO_CAMERA_PORT, 0 | NVODM_IMAGER_RESET_AL },
+    { NvOdmIoModule_Vdd,  0x00, Max8907bPmuSupply_LDO18}, //VDDIO_VI
+    { NvOdmIoModule_Vdd,  0x00, Max8907bPmuSupply_LDO9 }, //AVDD_CAM2
+    { NvOdmIoModule_Vdd,  0x00, Max8907bPmuSupply_LDO13}, //VDDIO_AF
+    { NvOdmIoModule_VideoInput, 0x00, SOC380_PINS },
+    { NvOdmIoModule_ExternalClock, 2, 0 } // CSUS
+};
+
+static const NvOdmIoAddress s_CommonImagerAddresses[] =
+{
+    { NvOdmIoModule_ExternalClock, 2, 0 } // CSUS
+};
+
+
diff --git a/arch/arm/mach-tegra/odm_kit/query/whistler/subboards/nvodm_query_discovery_e911_peripherals.h b/arch/arm/mach-tegra/odm_kit/query/whistler/subboards/nvodm_query_discovery_e911_peripherals.h
new file mode 100644
index 000000000000..c6fc1fb9f564
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/query/whistler/subboards/nvodm_query_discovery_e911_peripherals.h
@@ -0,0 +1,96 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/**
+ * @file
+ * <b>NVIDIA APX ODM Kit::
+ *         Implementation of the ODM Peripheral Discovery API</b>
+ *
+ * @b Description: Specifies the peripheral connectivity database Peripheral entries
+ *                 for the E911 5MP + 1.3MP + VGA VI Camera module.
+ */
+#include "../include/nvodm_imager_guids.h"
+
+// !!! DON'T MOVE THINGS AROUND !!!
+// Position 0 is used as default primary for E912
+// Position 1 is used as default secondary for E912 and E911
+// Position 2 is used as default primary for E911
+
+// Imager - Primary  
+// E912 A01 and Whistler Imager
+{
+    OV5630_GUID,
+    s_ffaImagerOV5630Addresses,
+    NV_ARRAY_SIZE(s_ffaImagerOV5630Addresses),
+    NvOdmPeripheralClass_Imager
+},
+// Imager - Secondary
+// sensor for SEMCO VGA
+{
+    // Aptina (Micron) SOC380
+    SEMCOVGA_GUID,
+    s_ffaImagerSOC380Addresses,
+    NV_ARRAY_SIZE(s_ffaImagerSOC380Addresses),
+    NvOdmPeripheralClass_Imager
+},
+
+// Dummy Entry for Whistler
+{
+    MI5130_GUID,
+    s_ffaImagerOV5630Addresses,
+    NV_ARRAY_SIZE(s_ffaImagerOV5630Addresses),
+    NvOdmPeripheralClass_Imager
+},
+
+// focuser for OV5630 module
+{
+    // VCM driver IC AD5820 Analog Devices
+    AD5820_GUID,
+    s_ffaImagerAD5820Addresses,
+    NV_ARRAY_SIZE(s_ffaImagerAD5820Addresses),
+    NvOdmPeripheralClass_Other
+},
+
+// flash device 
+{
+    LTC3216_GUID,
+    s_ffaFlashLTC3216Addresses,
+    NV_ARRAY_SIZE(s_ffaFlashLTC3216Addresses),
+    NvOdmPeripheralClass_Other
+},
+
+{
+    COMMONIMAGER_GUID,
+    s_CommonImagerAddresses,
+    NV_ARRAY_SIZE(s_CommonImagerAddresses),
+    NvOdmPeripheralClass_Other
+},
diff --git a/arch/arm/mach-tegra/odm_kit/query/whistler/subboards/nvodm_query_discovery_e936_addresses.h b/arch/arm/mach-tegra/odm_kit/query/whistler/subboards/nvodm_query_discovery_e936_addresses.h
new file mode 100644
index 000000000000..327edf62901a
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/query/whistler/subboards/nvodm_query_discovery_e936_addresses.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/**
+ * @file
+ * <b>NVIDIA APX ODM Kit::
+ *         Implementation of the ODM Peripheral Discovery API</b>
+ *
+ * @b Description: Specifies the peripheral connectivity 
+ *                 database NvOdmIoAddress entries for the E936
+ *                 ISDB-T module.
+ */
+
+#include "pmu/max8907b/max8907b_supply_info_table.h"
+
+// VIP raw bitstream addresses
+static const NvOdmIoAddress s_ffaVIPBitstreamAddresses[] =
+{
+    { NvOdmIoModule_Vdd,  0x00, Max8907bPmuSupply_LX_V3  },
+    { NvOdmIoModule_Vdd,  0x00, Max8907bPmuSupply_LDO9 },
+    { NvOdmIoModule_Vdd,  0x00, Max8907bPmuSupply_LDO18 },
+    // Reset. vgp0 and vgp5:
+    { NvOdmIoModule_Gpio, 27, 1 },      // vgp[0] - Port BB(27), Pin 1
+    { NvOdmIoModule_Gpio, 'd'-'a', 2 }, // vgp[5] - Port D, Pin 2
+};
+
diff --git a/arch/arm/mach-tegra/odm_kit/query/whistler/subboards/nvodm_query_discovery_e936_peripherals.h b/arch/arm/mach-tegra/odm_kit/query/whistler/subboards/nvodm_query_discovery_e936_peripherals.h
new file mode 100644
index 000000000000..c2733b11531c
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/query/whistler/subboards/nvodm_query_discovery_e936_peripherals.h
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/**
+ * @file
+ * <b>NVIDIA APX ODM Kit::
+ *         Implementation of the ODM Peripheral Discovery API</b>
+ *
+ * @b Description: Specifies the peripheral connectivity database Peripheral
+ *                 entries for the E936 ISDB-T module.
+ */
+
+// Murata tuner source
+{
+    NV_ODM_GUID('m','u','r','a','t','a','5','7'),
+    s_ffaVIPBitstreamAddresses,
+    NV_ARRAY_SIZE(s_ffaVIPBitstreamAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// NOTE: This list *must* end with a trailing comma.
diff --git a/arch/arm/mach-tegra/odm_kit/query/whistler/subboards/nvodm_query_discovery_e951_addresses.h b/arch/arm/mach-tegra/odm_kit/query/whistler/subboards/nvodm_query_discovery_e951_addresses.h
new file mode 100644
index 000000000000..70f20af74044
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/query/whistler/subboards/nvodm_query_discovery_e951_addresses.h
@@ -0,0 +1,96 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/**
+ * @file
+ * <b>NVIDIA APX ODM Kit::
+ *         Implementation of the ODM Peripheral Discovery API</b>
+ *
+ * @b Description: Specifies the peripheral connectivity
+ *                 database NvOdmIoAddress entries for the E951
+ *                 COMMS module.
+ */
+
+#include "pmu/max8907b/max8907b_supply_info_table.h"
+// Bluetooth
+static const NvOdmIoAddress ffaBluetoothAddresses[] =
+{
+    { NvOdmIoModule_Uart, 0x2,  0x0 },
+    { NvOdmIoModule_Gpio, 0x14, 0x0 },     /* GPIO Port U and Pin 0 */
+    { NvOdmIoModule_Vdd, 0x00, MIC2826PmuSupply_LDO3 }  /* VDD -> MIC2826 LDO3 */
+};
+
+
+// Wlan
+static const NvOdmIoAddress s_ffaWlanAddresses[] =
+{
+    { NvOdmIoModule_Sdio, 0x01, 0x0 },    /* WLAN is on SD Bus */
+    { NvOdmIoModule_Gpio, 0x0a, 0x5 },    /* GPIO Port K and Pin 5 */
+    { NvOdmIoModule_Gpio, 0x0a, 0x6 },    /* GPIO Port K and Pin 6 */
+    { NvOdmIoModule_Vdd, 0x00, Max8907bPmuSupply_LDO8 },  /* VDD -> LDO8 (VOUT8) */
+    { NvOdmIoModule_Vdd, 0x00, Max8907bPmuSupply_LDO11 },  /* VDD -> LDO11 (VOUT11) */
+    { NvOdmIoModule_Vdd, 0x00, MIC2826PmuSupply_LDO3 }  /* VDD -> MIC2826 LDO3 */    
+};
+
+// EMP Rainbow module
+static const NvOdmIoAddress s_ffaEmpAddresses[] =
+{
+    { NvOdmIoModule_Uart, 0x0,  0x0 },                      /* UART 0 */
+    { NvOdmIoModule_Gpio, 0x15, 0x0 },                      /* GPIO Port V and Pin 0 Reset */
+    { NvOdmIoModule_Gpio, 0x15, 0x1 },                      /* GPIO Port V and Pin 1 Power */
+    { NvOdmIoModule_Gpio, 0x19, 0x0 },                      /* GPIO Port Z and Pin 0 AWR */
+    { NvOdmIoModule_Gpio, 0x18, 0x6 },                      /* GPIO Port Y and Pin 6 CWR */
+    { NvOdmIoModule_Gpio, 0x0e, 0x6 },                      /* GPIO Port O and Pin 6 SpiInt */
+    { NvOdmIoModule_Gpio, 0x15, 0x2 },                      /* GPIO Port V and Pin 2 SpiSlaveSelect */
+    { NvOdmIoModule_Slink, 0x0,  0x0 }                      /* Slink 0 */
+};
+
+// EMP M570 module
+static const NvOdmIoAddress s_ffaEmpM570Addresses[] =
+{
+    { NvOdmIoModule_Uart, 0x0,  0x0 },                      /* UART 0 */
+    { NvOdmIoModule_Gpio, 0x15, 0x0 },                      /* GPIO Port V and Pin 0 Reset */
+    { NvOdmIoModule_Gpio, 0x15, 0x1 },                      /* GPIO Port V and Pin 1 Power */
+    { NvOdmIoModule_Gpio, 0x19, 0x0 },                      /* GPIO Port Z and Pin 0 AWR */
+    { NvOdmIoModule_Gpio, 0x18, 0x6 },                      /* GPIO Port Y and Pin 6 CWR */
+};
+
+// IFX Modem module
+static const NvOdmIoAddress s_ffaInfnAddresses[] =
+{
+    { NvOdmIoModule_Spi, 0x0,  0x0 },                      /* Spi Controller 0 and Chip Select 0 */
+    { NvOdmIoModule_Gpio, 0x18, 0x6 },                      /* GPIO Port Y and Pin 6 SRDY */
+    { NvOdmIoModule_Gpio, 0x19, 0x0 },                      /* GPIO Port Z and Pin 0 MRDY */
+    { NvOdmIoModule_Gpio, 0x15, 0x0 },                      /* GPIO Port V and Pin 0 Reset */
+    { NvOdmIoModule_Gpio, 0x15, 0x1 }                      /* GPIO Port V and Pin 1 Power */
+};
+
diff --git a/arch/arm/mach-tegra/odm_kit/query/whistler/subboards/nvodm_query_discovery_e951_peripherals.h b/arch/arm/mach-tegra/odm_kit/query/whistler/subboards/nvodm_query_discovery_e951_peripherals.h
new file mode 100644
index 000000000000..69b364f11689
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/query/whistler/subboards/nvodm_query_discovery_e951_peripherals.h
@@ -0,0 +1,82 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/**
+ * @file
+ * <b>NVIDIA APX ODM Kit::
+ *         Implementation of the ODM Peripheral Discovery API</b>
+ *
+ * @b Description: Specifies the peripheral connectivity 
+ *                 database Peripheral entries for the E951
+ *                 COMMS module.
+ */
+// Bluetooth on COMMs Module
+{
+     NV_ODM_GUID('b','l','u','t','o','o','t','h'),
+     ffaBluetoothAddresses,
+     NV_ARRAY_SIZE(ffaBluetoothAddresses),
+     NvOdmPeripheralClass_Other
+},
+
+// Sdio wlan  on COMMs Module
+{
+    NV_ODM_GUID('s','d','i','o','w','l','a','n'),
+    s_ffaWlanAddresses,
+    NV_ARRAY_SIZE(s_ffaWlanAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// EMP Modem on COMMs Module
+{
+    NV_ODM_GUID('e','m','p',' ','_','m','d','m'),
+    s_ffaEmpAddresses,
+    NV_ARRAY_SIZE(s_ffaEmpAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// EMP M570 Modem on COMMs Module
+{
+    NV_ODM_GUID('e','m','p',' ','M','5','7','0'),
+    s_ffaEmpM570Addresses,
+    NV_ARRAY_SIZE(s_ffaEmpM570Addresses),
+    NvOdmPeripheralClass_Other
+},
+
+// IFX Modem on COMMs Module
+{
+    NV_ODM_GUID('s','p','i',' ','_','i','p','c'),
+    s_ffaInfnAddresses,
+    NV_ARRAY_SIZE(s_ffaInfnAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// NOTE: This list *must* end with a trailing comma.
diff --git a/arch/arm/mach-tegra/odm_kit/query/whistler/tegra_devkit_custopt.h b/arch/arm/mach-tegra/odm_kit/query/whistler/tegra_devkit_custopt.h
new file mode 100644
index 000000000000..bfbedb35945f
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/query/whistler/tegra_devkit_custopt.h
@@ -0,0 +1,180 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/**
+ * @file
+ * <b>NVIDIA Tegra ODM Kit:
+ *         Definition of bitfields inside the BCT customer option</b>
+ *
+ * @b Description: Defines the board-specific bitfields of the 
+ *                 BCT customer option parameter, for NVIDIA
+ *                 Tegra development platforms.
+ *  
+ *                 This file pertains to Whistler and Voyager.
+ */
+
+#ifndef NVIDIA_TEGRA_DEVKIT_CUSTOPT_H
+#define NVIDIA_TEGRA_DEVKIT_CUSTOPT_H
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+//---------- BOARD PERSONALITIES (BEGIN) ----------//
+// On the Whistler boards, be sure to match the following
+// switches with the personality setting you choose.
+// 
+//      SW2 = bits 3:0 (low nibble)
+//      SW3 = bits 7:4 (high nibble)
+
+#define TEGRA_DEVKIT_DEFAULT_PERSONALITY \
+    TEGRA_DEVKIT_BCT_CUSTOPT_0_PERSONALITY_75
+
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_PERSONALITY_RANGE     7:0
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_PERSONALITY_DEFAULT  0x0UL
+
+// VOYAGER, eMMC, NO TRACE (10x8 keypad)
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_PERSONALITY_01       0x01UL  // ULPI = baseband
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_PERSONALITY_05       0x05UL  // ULPI = UART1
+
+// VOYAGER, eMMC, with TRACE (7x1 keypad)
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_PERSONALITY_11       0x11UL  // ULPI = baseband
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_PERSONALITY_15       0x15UL  // ULPI = UART1
+
+// VOYAGER, NAND, NO TRACE (10x8 keypad)
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_PERSONALITY_75       0x75UL  // Voyager, NAND
+
+// WHISTLER, stand-alone
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_PERSONALITY_C1       0xC1UL  // KB = 13x1, TRACE, GMI = A/D NOR
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_PERSONALITY_C3       0xC3UL  // KB = 16x8, NO TRACE, GMI = NAND
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_PERSONALITY_C4       0xC4UL  
+
+
+// VOYAGER, USB2-ULPI (No UART1)
+// Personality 71 is similar to the 75, except ULPI is enabled instead of UART1.
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_PERSONALITY_71       0x71UL  
+
+
+//---------- BOARD PERSONALITIES (END) ----------//
+
+/// Download transport
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_TRANSPORT_RANGE      10:8
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_TRANSPORT_DEFAULT    0x0UL
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_TRANSPORT_NONE       0x1UL
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_TRANSPORT_UART       0x2UL
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_TRANSPORT_USB        0x3UL
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_TRANSPORT_ETHERNET   0x4UL
+
+/// Transport option (bus selector), for UART and Ethernet transport
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_UART_OPTION_RANGE   12:11
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_UART_OPTION_DEFAULT 0x0UL
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_UART_OPTION_A       0x1UL
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_UART_OPTION_B       0x2UL
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_UART_OPTION_C       0x3UL
+
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_ETHERNET_OPTION_RANGE   12:11
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_ETHERNET_OPTION_DEFAULT 0x0UL
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_ETHERNET_OPTION_SPI     0x1UL
+
+/// RIL selection
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_RIL_RANGE              14:13
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_RIL_DEFAULT            0x0UL
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_RIL_EMP_RAINBOW        0x1UL
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_RIL_EMP_RAINBOW_ULPI   0x2UL
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_RIL_IFX                0x3UL
+
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_CONSOLE_OPTION_RANGE    17:15
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_CONSOLE_OPTION_DEFAULT  0
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_CONSOLE_OPTION_UARTA    0
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_CONSOLE_OPTION_UARTB    1
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_CONSOLE_OPTION_UARTC    2
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_CONSOLE_OPTION_UARTD    3
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_CONSOLE_OPTION_UARTE    4
+
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_CONSOLE_RANGE           19:18
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_CONSOLE_DEFAULT         0
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_CONSOLE_NONE            1
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_CONSOLE_DCC             2
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_CONSOLE_UART            3
+
+// display options
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_DISPLAY_OPTION_RANGE      22:20
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_DISPLAY_OPTION_DEFAULT    0x0UL
+// embedded panel (lvds, dsi, etc)
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_DISPLAY_OPTION_EMBEDDED   0x0UL
+// no panels (external or embedded)
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_DISPLAY_OPTION_NULL       0x1UL
+// use hdmi as the primary
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_DISPLAY_OPTION_HDMI       0x2UL
+// use crt as the primary 
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_DISPLAY_OPTION_CRT        0x3UL
+
+
+// Enable DHCP
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_DHCP_RANGE           23:23
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_DHCP_DEFAULT         0x0UL
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_DHCP_ENABLE          0x1UL
+
+/// Carveout RAM
+#define TEGRA_DEVKIT_BCT_CARVEOUT_0_MEMORY_RANGE    27:24
+#define TEGRA_DEVKIT_BCT_CARVEOUT_0_MEMORY_DEFAULT  0x0UL
+#define TEGRA_DEVKIT_BCT_CARVEOUT_0_MEMORY_1        0x1UL
+#define TEGRA_DEVKIT_BCT_CARVEOUT_0_MEMORY_2        0x2UL
+#define TEGRA_DEVKIT_BCT_CARVEOUT_0_MEMORY_3        0x3UL
+#define TEGRA_DEVKIT_BCT_CARVEOUT_0_MEMORY_4        0x4UL
+#define TEGRA_DEVKIT_BCT_CARVEOUT_0_MEMORY_5        0x5UL
+#define TEGRA_DEVKIT_BCT_CARVEOUT_0_MEMORY_6        0x6UL
+#define TEGRA_DEVKIT_BCT_CARVEOUT_0_MEMORY_7        0x7UL
+#define TEGRA_DEVKIT_BCT_CARVEOUT_0_MEMORY_8        0x8UL //32 MB
+
+
+/// Total RAM
+#define TEGRA_DEVKIT_BCT_SYSTEM_0_MEMORY_RANGE    30:28
+#define TEGRA_DEVKIT_BCT_SYSTEM_0_MEMORY_DEFAULT  0x0UL
+#define TEGRA_DEVKIT_BCT_SYSTEM_0_MEMORY_1        0x1UL
+#define TEGRA_DEVKIT_BCT_SYSTEM_0_MEMORY_2        0x2UL
+#define TEGRA_DEVKIT_BCT_SYSTEM_0_MEMORY_3        0x3UL
+#define TEGRA_DEVKIT_BCT_SYSTEM_0_MEMORY_4        0x4UL
+#define TEGRA_DEVKIT_BCT_SYSTEM_0_MEMORY_5        0x5UL
+#define TEGRA_DEVKIT_BCT_SYSTEM_0_MEMORY_6        0x6UL
+#define TEGRA_DEVKIT_BCT_SYSTEM_0_MEMORY_7        0x7UL
+/// Soc low power state
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_LPSTATE_RANGE            31:31
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_LPSTATE_LP0              0x0UL
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_LPSTATE_LP1              0x1UL
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif
diff --git a/arch/arm/mach-tegra/pinmux.c b/arch/arm/mach-tegra/pinmux.c
index 77846cb945a1..10f66b82def6 100644
--- a/arch/arm/mach-tegra/pinmux.c
+++ b/arch/arm/mach-tegra/pinmux.c
@@ -381,6 +381,13 @@ int tegra_pinmux_cancel_func(tegra_pingroup_t pg, tegra_mux_func_t func)
 	return 0;
 }
 
+int tegra_pinmux_get_vddio(tegra_pingroup_t pg)
+{
+	if (pg < 0 || pg >=  TEGRA_MAX_PINGROUP)
+		return -EINVAL;
+	return pingroups[pg].vddio;
+}
+
 int tegra_pinmux_set_func(tegra_pingroup_t pg, tegra_mux_func_t func)
 {
 	int mux = -1;